diff --git a/.github/workflows/msc313e_images.yml b/.github/workflows/msc313e_images.yml new file mode 100644 index 00000000..29c5866e --- /dev/null +++ b/.github/workflows/msc313e_images.yml @@ -0,0 +1,139 @@ +name: "MSC313E" + +on: + push: + branches: + - production + tags: + - "v*" + # schedule: + # - cron: "00 01 * * *" + workflow_dispatch: + +jobs: + build_core: + name: OpenIPC firmware for MSC313E + runs-on: ubuntu-18.04 + + steps: + + - name: Checkout + id: checkout + uses: actions/checkout@v2 + + - name: Install build dependencies + id: install + run: | + make install-deps + mkdir -p tmp + + - name: Free disk space + id: freshing + run: | + sudo swapoff -a + sudo rm -f /swapfile + sudo apt clean + docker rmi $(docker image ls -aq) + df -h + + - name: Prepare buildroot + id: prepare + run: | + HEAD_TAG=$(git tag --points-at HEAD) + GIT_HASH=$(git rev-parse --short $GITHUB_SHA) + BRANCH_NAME=$(echo $GITHUB_REF | cut -d'/' -f 3) + if [ -z "$HEAD_TAG" ]; then + TAG_NAME="latest" + RELEASE_NAME="Development Build" + PRERELEASE=true + else + TAG_NAME=${{ github.ref }} + RELEASE_NAME="Release ${{ github.ref }}" + PRERELEASE=false + fi + echo "GIT_HASH=$GIT_HASH" >> $GITHUB_ENV + echo "TAG_NAME=$TAG_NAME" >> $GITHUB_ENV + echo "RELEASE_NAME=$RELEASE_NAME" >> $GITHUB_ENV + echo "PRERELEASE=$PRERELEASE" >> $GITHUB_ENV + echo "BRANCH_NAME=$BRANCH_NAME" >> $GITHUB_ENV + cd $GITHUB_WORKSPACE + make prepare + + - name: Build MSC313E firmware + id: build-msc313e-firmware + continue-on-error: true + run: | + ARCHIVE_FW="${GITHUB_WORKSPACE}/output/images/openipc.msc313e-br.tgz" + echo "ARCHIVE_FW=$ARCHIVE_FW" >> $GITHUB_ENV + cd $GITHUB_WORKSPACE + make PLATFORM=sigmastar BOARD=unknown_unknown_msc313e_openipc all + [[ $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/uImage) -gt 2097152 ]] && echo "TG_NOTIFY=Warning, kernel size exceeded : $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/uImage) vs 2097152... MSC313E" >> $GITHUB_ENV && exit 1 + [[ $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/rootfs.squashfs) -gt 5242880 ]] && echo "TG_NOTIFY=Warning, rootfs size exceeded - $(stat --printf="%s" ${GITHUB_WORKSPACE}/output/images/rootfs.squashfs) vs 5242880... MSC313E" >> $GITHUB_ENV && exit 1 + cd ${GITHUB_WORKSPACE}/output/images + mv uImage uImage.msc313e + mv rootfs.squashfs rootfs.squashfs.msc313e + md5sum rootfs.squashfs.msc313e > rootfs.squashfs.msc313e.md5sum + md5sum uImage.msc313e > uImage.msc313e.md5sum + tar -cvzf $ARCHIVE_FW *msc313e* + + - name: Build MSC313E SDK + id: build-msc313e-sdk + continue-on-error: true + run: | + ARCHIVE_SDK="${GITHUB_WORKSPACE}/output/images/arm-openipc-linux-musleabihf_sdk-buildroot.tar.gz" + echo "ARCHIVE_SDK=$ARCHIVE_SDK" >> $GITHUB_ENV + cd $GITHUB_WORKSPACE/output + make sdk + + - name: Send warning message to telegram channel + env: + TG_TOKEN: ${{ secrets.TELEGRAM_TOKEN_BOT_OPENIPC }} + TG_CHANNEL: ${{ secrets.TELEGRAM_CHANNEL_OPENIPC_DEV }} + if: steps.build-msc313e-firmware.outcome != 'success' || steps.build-msc313e-sdk.outcome != 'success' + run: | + TG_OPTIONS="-s --connect-timeout 30 --max-time 30" + TG_NOTIFY="${TG_NOTIFY:=Warning, Buildroot compiling error... MSC313E}" + TG_HEADER=$(echo -e "\r\n$TG_NOTIFY \r\n\r\nCommit: $GIT_HASH \r\nBranch: $BRANCH_NAME \r\nTag: $TAG_NAME \r\n\r\n\xE2\x9A\xA0 GitHub Actions") + curl $TG_OPTIONS -H "Content-Type: multipart/form-data" -X POST https://api.telegram.org/bot$TG_TOKEN/sendMessage \ + -F chat_id=$TG_CHANNEL -F text="$TG_HEADER" + + - name: Create release + uses: actions/create-release@v1 + continue-on-error: true + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: ${{ env.TAG_NAME }} + release_name: ${{ env.RELEASE_NAME }} + draft: false + prerelease: ${{ env.PRERELEASE }} + + - name: Upload FW to release + uses: svenstaro/upload-release-action@v2 + continue-on-error: true + with: + repo_token: ${{ secrets.GITHUB_TOKEN }} + file: ${{ env.ARCHIVE_FW }} + asset_name: "openipc.msc313e-br.tgz" + tag: ${{ env.TAG_NAME }} + overwrite: true + + - name: Upload SDK to release + uses: svenstaro/upload-release-action@v2 + continue-on-error: true + with: + repo_token: ${{ secrets.GITHUB_TOKEN }} + file: ${{ env.ARCHIVE_SDK }} + asset_name: "arm-openipc-msc313e-linux-musleabihf_sdk-buildroot.tar.gz" + tag: ${{ env.TAG_NAME }} + overwrite: true + + - name: Send binary file to telegram channel + env: + TG_TOKEN: ${{ secrets.TELEGRAM_TOKEN_BOT_OPENIPC }} + TG_CHANNEL: ${{ secrets.TELEGRAM_CHANNEL_OPENIPC_DEV }} + run: | + TG_OPTIONS="-s --connect-timeout 30 --max-time 30" + TG_HEADER=$(echo -e "\r\nCommit: $GIT_HASH \r\nBranch: $BRANCH_NAME \r\nTag: $TAG_NAME \r\n\r\n\xE2\x9C\x85 GitHub Actions") + curl $TG_OPTIONS -H "Content-Type: multipart/form-data" -X POST https://api.telegram.org/bot$TG_TOKEN/sendDocument \ + -F chat_id=$TG_CHANNEL -F document="@$ARCHIVE_FW" -F caption="$TG_HEADER" diff --git a/br-ext-chip-sigmastar/Config.in b/br-ext-chip-sigmastar/Config.in index 0f7d2844..5acfc527 100644 --- a/br-ext-chip-sigmastar/Config.in +++ b/br-ext-chip-sigmastar/Config.in @@ -23,6 +23,7 @@ source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/motors/Config.in" source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/node-exporter/Config.in" source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/opus-openipc/Config.in" source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/rtl8188fu-openipc/Config.in" +source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/sigmastar-osdrv-msc313e/Config.in" source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/sigmastar-osdrv-ssc335/Config.in" source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/uacme-openipc/Config.in" source "$BR2_EXTERNAL_SIGMASTAR_PATH/package/vtund-openipc/Config.in" diff --git a/br-ext-chip-sigmastar/board/infinity3/kernel/msc313e.generic.config b/br-ext-chip-sigmastar/board/infinity3/kernel/msc313e.generic.config new file mode 100644 index 00000000..097ece0f --- /dev/null +++ b/br-ext-chip-sigmastar/board/infinity3/kernel/msc313e.generic.config @@ -0,0 +1,2441 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.18.30 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_ARM_HAS_SG_CHAIN=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_XZ=y +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_CROSS_MEMORY_ATTACH is not set +# CONFIG_FHANDLE is not set +# CONFIG_USELIB is not set +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_IRQ_DOMAIN=y +CONFIG_HANDLE_DOMAIN_IRQ=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_TASKS_RCU is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +# CONFIG_BUILD_BIN2C is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_FREEZER is not set +# CONFIG_CGROUP_DEVICE is not set +# CONFIG_CPUSETS is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_CGROUP_SCHED is not set +# CONFIG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +# CONFIG_USER_NS is not set +CONFIG_PID_NS=y +CONFIG_NET_NS=y +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_BASE_FULL is not set +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +# CONFIG_TIMERFD is not set +CONFIG_EVENTFD=y +# CONFIG_BPF_SYSCALL is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_ADVISE_SYSCALLS is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_SYSTEM_TRUSTED_KEYRING is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_JUMP_LABEL=y +# CONFIG_UPROBES is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR_NONE is not set +CONFIG_CC_STACKPROTECTOR_REGULAR=y +# CONFIG_CC_STACKPROTECTOR_STRONG is not set +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=1 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULE_SIG is not set +# CONFIG_MODULE_COMPRESS is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_CMDLINE_PARSER is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_DEADLINE=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +# CONFIG_FREEZER is not set + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE_LEGACY is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_ARCH_BERLIN is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_HISI is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MESON is not set +CONFIG_ARCH_MSTAR=y +# CONFIG_ARCH_CEDRIC is not set +# CONFIG_ARCH_CHICAGO is not set +# CONFIG_ARCH_INFINITY is not set +CONFIG_ARCH_INFINITY3=y + +# +# Options +# +CONFIG_MS_BUILTIN_DTB="" +CONFIG_MS_KERNEL_TYPE="" +CONFIG_MSTAR_CHIP_NAME="infinity3" +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MEDIATEK is not set + +# +# TI OMAP/AM/DM/DRA Family +# +# CONFIG_ARCH_OMAP3 is not set +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP5 is not set +# CONFIG_SOC_AM33XX is not set +# CONFIG_SOC_AM43XX is not set +# CONFIG_SOC_DRA7XX is not set +# CONFIG_ARCH_QCOM is not set +# CONFIG_ARCH_ROCKCHIP is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_STI is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHMOBILE_MULTI is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_ARM_VIRT_EXT is not set +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_754322 is not set +# CONFIG_ARM_ERRATA_775420 is not set +# CONFIG_ARM_ERRATA_773022 is not set + +# +# Bus support +# +# CONFIG_PCI is not set +# CONFIG_PCI_SYSCALL is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +# CONFIG_SMP is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_ARM_PSCI is not set +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ_FIXED=0 +CONFIG_HZ_100=y +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +CONFIG_THUMB2_KERNEL=y +CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y +CONFIG_ARM_ASM_UNIFIED=y +CONFIG_AEABI=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_NO_BOOTMEM=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_CMA=y +CONFIG_CMA_DEBUG=y +CONFIG_CMA_DEBUGFS=y +# CONFIG_CMA_BUFFER_LIST is not set +CONFIG_CMA_AREAS=1 +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +CONFIG_FORCE_MAX_ZONEORDER=10 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set +CONFIG_CMDLINE="" +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +# CONFIG_CPUFREQ_DT is not set + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set + +# +# CPU Idle +# +# CONFIG_CPU_IDLE is not set +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +# CONFIG_PM_RUNTIME is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_ARM_CPU_SUSPEND is not set +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set +CONFIG_UNIX=y +# CONFIG_UNIX_DIAG is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_IP_MROUTE is not set +CONFIG_SYN_COOKIES=y +CONFIG_NET_UDP_TUNNEL=y +CONFIG_NET_FOU=y +# CONFIG_GENEVE is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_GRE is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NET_PTP_CLASSIFY is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_MMAP is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_NET_MPLS_GSO is not set +# CONFIG_HSR is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +# CONFIG_UEVENT_HELPER is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +# CONFIG_ALLOW_DEV_COREDUMP is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +# CONFIG_DMA_SHARED_BUFFER is not set +CONFIG_DMA_CMA=y + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=16 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=4 + +# +# Bus devices +# +# CONFIG_BRCMSTB_GISB_ARB is not set +# CONFIG_ARM_CCI is not set +# CONFIG_VEXPRESS_CONFIG is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_OF_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +CONFIG_MTD_NAND_ECC=m +# CONFIG_MTD_NAND_ECC_SMC is not set +CONFIG_MTD_NAND=m +# CONFIG_MTD_NAND_ECC_BCH is not set +# CONFIG_MTD_SM_COMMON is not set +# CONFIG_MTD_NAND_DENALI is not set +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set +CONFIG_MTD_NAND_IDS=m +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_DOCG4 is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR & LPDDR2 PCM memory drivers +# +# CONFIG_MTD_LPDDR is not set +# CONFIG_MTD_LPDDR2_NVM is not set +# CONFIG_MTD_SPI_NOR is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MTD=y +CONFIG_OF_RESERVED_MEM=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_SRAM is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_LEGACY=m +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# Intel MIC Bus Driver +# + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# +# CONFIG_ECHO is not set +# CONFIG_CXL_BASE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=m +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_MQ_DEFAULT is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_SCSI_UFSHCD is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +# CONFIG_NET_CORE is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +# CONFIG_NET_DSA_MV88E6171 is not set +# CONFIG_NET_DSA_BCM_SF2 is not set +# CONFIG_ETHERNET is not set +# CONFIG_PHYLIB is not set +# CONFIG_MICREL_KS8995MA is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Host-side USB support is needed for USB Network Adapter support +# +# CONFIG_USB_NET_DRIVERS is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_ATH_CARDS is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMSMAC is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_HOSTAP is not set +# CONFIG_LIBERTAS is not set +# CONFIG_P54_COMMON is not set +# CONFIG_RT2X00 is not set +CONFIG_RTL_CARDS=m +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTLWIFI_USB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTL8192C_COMMON=m +# CONFIG_WL_TI is not set +# CONFIG_ZD1211RW is not set +# CONFIG_MWIFIEX is not set +# CONFIG_CW1200 is not set +# CONFIG_RSI_91X is not set +CONFIG_MT7601U=m + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +# CONFIG_PTP_1588_CLOCK is not set + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_DWAPB is not set +# CONFIG_GPIO_EM is not set +# CONFIG_GPIO_ZEVIO is not set +# CONFIG_GPIO_SCH311X is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# LPC GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_POWER_AVS is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MEN_A21_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_AXP20X is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_PM8921_CORE is not set +# CONFIG_MFD_RTSX_USB is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# + +# +# Direct Rendering Manager +# +# CONFIG_DRM is not set + +# +# Frame buffer Devices +# +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CMDLINE=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SSD1307 is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_VGASTATE is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_COMPRESS_OFFLOAD=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set + +# +# HD-Audio +# +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set + +# +# SoC Audio for Freescale CPUs +# + +# +# Common SoC Audio options for Freescale CPUs: +# +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +CONFIG_SND_SOC_I2C_AND_SPI=y + +# +# CODEC drivers +# +# CONFIG_SND_SOC_ADAU1701 is not set +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS42L73 is not set +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271 is not set +# CONFIG_SND_SOC_CS42XX8_I2C is not set +# CONFIG_SND_SOC_HDMI_CODEC is not set +# CONFIG_SND_SOC_ES8328 is not set +# CONFIG_SND_SOC_PCM1681 is not set +# CONFIG_SND_SOC_PCM1792A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +# CONFIG_SND_SOC_SGTL5000 is not set +# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SPDIF is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA350 is not set +# CONFIG_SND_SOC_TAS2552 is not set +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +# CONFIG_SND_SOC_WM8731 is not set +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8804 is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_MP_USB_MSTAR=y +CONFIG_MP_USB_STR_PATCH=y +CONFIG_USB_COMMON=m +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=m +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_FSM is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_FUSBH200_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_MAX3421_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_USB_PHY is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_AM335X_PHY_USB is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_MS_OTG_ENABLE=y +# CONFIG_USB_ULPI is not set +# CONFIG_USB_GADGET is not set +# CONFIG_UWB is not set +CONFIG_MMC=m +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=m +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_HYM8563 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_ISL12057 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1343 is not set +# CONFIG_RTC_DRV_DS1347 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set +# CONFIG_RTC_DRV_MCP795 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_SNVS is not set +# CONFIG_RTC_DRV_XGENE is not set + +# +# HID Sensor RTC drivers +# +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=y +# CONFIG_UIO_DMEM_GENIRQ is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_PRISM2_USB is not set +# CONFIG_COMEDI is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +CONFIG_R8188EU=m +CONFIG_88EU_AP_MODE=y +# CONFIG_LINE6_USB is not set +# CONFIG_VT6656 is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=m +CONFIG_ANDROID_BINDER_IPC_32BIT=y +# CONFIG_ASHMEM is not set +CONFIG_ANDROID_LOGGER=y +# CONFIG_ANDROID_TIMED_OUTPUT is not set +# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set +# CONFIG_ANDROID_INTF_ALARM_DEV is not set +# CONFIG_SYNC is not set +# CONFIG_ION is not set +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_WIMAX_GDM72XX is not set +# CONFIG_LTE_GDM724X is not set +# CONFIG_MTD_SPINAND_MT29F is not set +# CONFIG_LUSTRE_FS is not set +# CONFIG_DGAP is not set +# CONFIG_GS_FPGABOOT is not set + +# +# SOC (System On Chip) specific Drivers +# +# CONFIG_SOC_TI is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI570 is not set +# CONFIG_COMMON_CLK_PXA is not set +# CONFIG_COMMON_CLK_QCOM is not set + +# +# Hardware Spinlock drivers +# + +# +# Clock Source drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ATMEL_PIT is not set +# CONFIG_SH_TIMER_CMT is not set +# CONFIG_SH_TIMER_MTU2 is not set +# CONFIG_SH_TIMER_TMU is not set +# CONFIG_EM_TIMER_STI is not set +# CONFIG_CLKSRC_VERSATILE is not set +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# + +# +# SOC (System On Chip) specific Drivers +# +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +CONFIG_PWM=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_PCA9685 is not set +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set +CONFIG_TI_CMEM=m +CONFIG_MSTAR_DRIVERS=y +CONFIG_MS_PIU_TIMER=y +CONFIG_MS_MSYS=y +CONFIG_MS_ZEN=y +CONFIG_MS_SERIAL=y +CONFIG_MS_USCLK=m +CONFIG_MS_ISP=y +CONFIG_MS_ISP_INFINITY3=y +# CONFIG_MS_NAND is not set +# CONFIG_MS_EMMC is not set +CONFIG_MS_SDMMC=m +CONFIG_MS_SDMMC_SLOTNUMS=1 +CONFIG_MS_SDMMC1_IP=0 +CONFIG_MS_SDMMC2_IP=1 +CONFIG_MS_SDMMC3_IP=2 +CONFIG_MS_SDMMC1_PAD=0 +CONFIG_MS_SDMMC2_PAD=1 +CONFIG_MS_SDMMC3_PAD=2 +# CONFIG_MS_SDMMC_REVCDZ is not set +CONFIG_MS_SDMMC_TCARD=y +CONFIG_MS_SDMMC1_MAXCLK=48000000 +CONFIG_MS_SDMMC1_MAXDLVL=0 +CONFIG_MS_SDMMC1_PASSLVL=0 +CONFIG_MS_SDMMC1_INTCDZ=y +CONFIG_MS_SDMMC2_MAXCLK=48000000 +CONFIG_MS_SDMMC2_MAXDLVL=0 +CONFIG_MS_SDMMC2_PASSLVL=0 +CONFIG_MS_SDMMC2_INTCDZ=y +CONFIG_MS_SDMMC3_MAXCLK=48000000 +CONFIG_MS_SDMMC3_MAXDLVL=0 +CONFIG_MS_SDMMC3_PASSLVL=0 +CONFIG_MS_SDMMC3_INTCDZ=y +CONFIG_MS_SOUND=y +CONFIG_MS_SOUND_INFINITY3=y +# CONFIG_MS_FB is not set +CONFIG_MS_SCL=y +CONFIG_MS_SCL_INFINITY3=y +CONFIG_MS_EMAC=y +# CONFIG_EMAC_SUPPLY_RNG is not set +CONFIG_ETHERNET_ALBANY=y +# CONFIG_MSTAR_HW_TX_CHECKSUM is not set +# CONFIG_K3_RX_SWPATCH is not set +CONFIG_DISCONNECT_DELAY_S=1 +# CONFIG_MSTAR_EEE is not set +# CONFIG_MS_IR is not set +CONFIG_MS_I2C=y +CONFIG_MS_I2C_INFINITY3=y +CONFIG_MS_GPIO=y +# CONFIG_MS_SW_I2C is not set +CONFIG_MS_WATCHDOG=y +CONFIG_MS_SAR=y +CONFIG_MS_IRCUT=y +CONFIG_MS_VHE=y +CONFIG_MS_MFEV5=y +CONFIG_MS_RTC=y +CONFIG_MS_JPE=y +CONFIG_MS_FLASH_ISP=y +CONFIG_MS_FLASH_ISP_MXP_PARTS=y +CONFIG_MS_FLASH_ISP_INFINITY3=y +# CONFIG_MS_XPM is not set +CONFIG_MS_CRYPTO=m +CONFIG_MS_CPU_FREQ=y +CONFIG_MS_PWM=m +CONFIG_MS_SPINAND=m +# CONFIG_NAND_SINGLE_READ is not set +# CONFIG_NAND_DUAL_READ is not set +# CONFIG_NAND_QUAL_READ is not set +CONFIG_AUTO_DETECT=y +# CONFIG_NAND_QUAL_WRITE is not set +CONFIG_AUTO_DETECT_WRITE=y +# CONFIG_MS_SPI_INFINITY is not set +# CONFIG_MS_PM is not set +CONFIG_MS_IVE=y +CONFIG_MS_NOTIFY=m + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_QUOTACTL is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_OVERLAY_FS=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=y +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_YAFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +# CONFIG_JFFS2_FS_WRITEBUFFER is not set +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_SINGLE=y +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set +# CONFIG_SQUASHFS_XATTR is not set +# CONFIG_SQUASHFS_ZLIB is not set +# CONFIG_SQUASHFS_LZO is not set +CONFIG_SQUASHFS_XZ=y +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +CONFIG_SQUASHFS_EMBEDDED=y +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_F2FS_FS=m +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_POSIX_ACL=y +# CONFIG_F2FS_FS_SECURITY is not set +# CONFIG_F2FS_CHECK_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +# CONFIG_PRINTK_TIME is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=4096 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_PREEMPT is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_TORTURE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_CPU_STALL_VERBOSE is not set +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set + +# +# Runtime Testing +# +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_TEST_LKM is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_BPF is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_ARM_PTDUMP is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_UART_PL01X is not set +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_UART_BCM63XX is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set +# CONFIG_DEBUG_SET_MODULE_RONX is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_MCRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +# CONFIG_CRYPTO_GCM is not set +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA1_ARM is not set +# CONFIG_CRYPTO_SHA1_ARM_NEON is not set +CONFIG_CRYPTO_SHA256=y +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA512_ARM_NEON is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_AES_ARM_BS is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_ZLIB=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +# CONFIG_VIRTUALIZATION is not set diff --git a/br-ext-chip-sigmastar/board/infinity3/kernel/overlay/include/linux/compiler-gcc7.h b/br-ext-chip-sigmastar/board/infinity3/kernel/overlay/include/linux/compiler-gcc7.h new file mode 100644 index 00000000..c8c56595 --- /dev/null +++ b/br-ext-chip-sigmastar/board/infinity3/kernel/overlay/include/linux/compiler-gcc7.h @@ -0,0 +1,65 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +#define __used __attribute__((__used__)) +#define __must_check __attribute__((warn_unused_result)) +#define __compiler_offsetof(a, b) __builtin_offsetof(a, b) + +/* Mark functions as cold. gcc will assume any path leading to a call + to them will be unlikely. This means a lot of manual unlikely()s + are unnecessary now for any paths leading to the usual suspects + like BUG(), printk(), panic() etc. [but let's keep them for now for + older compilers] + + Early snapshots of gcc 4.3 don't support this and we can't detect this + in the preprocessor, but we can live with this because they're unreleased. + Maketime probing would be overkill here. + + gcc also has a __attribute__((__hot__)) to move hot functions into + a special section, but I don't see any sense in this right now in + the kernel context */ +#define __cold __attribute__((__cold__)) + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ + +/* + * Mark a position in code as unreachable. This can be used to + * suppress control flow warnings after asm blocks that transfer + * control elsewhere. + * + * Early snapshots of gcc 4.5 don't support this and we can't detect + * this in the preprocessor, but we can live with this because they're + * unreleased. Really, we need to have autoconf for the kernel. + */ +#define unreachable() __builtin_unreachable() + +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +/* + * Tell the optimizer that something else uses this function or variable. + */ +#define __visible __attribute__((externally_visible)) + +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ +#define __HAVE_BUILTIN_BSWAP16__ +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/br-ext-chip-sigmastar/board/infinity3/kernel/patches/0000-infinity3-linux-3.18.30.patch b/br-ext-chip-sigmastar/board/infinity3/kernel/patches/0000-infinity3-linux-3.18.30.patch new file mode 100644 index 00000000..83f80523 --- /dev/null +++ b/br-ext-chip-sigmastar/board/infinity3/kernel/patches/0000-infinity3-linux-3.18.30.patch @@ -0,0 +1,784587 @@ +diff --git a/Makefile b/Makefile +index cdc9cf7c..f38bdbae 100644 +--- a/Makefile ++++ b/Makefile +@@ -398,7 +398,7 @@ LINUXINCLUDE := \ + + KBUILD_CPPFLAGS := -D__KERNEL__ + +-KBUILD_CFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \ ++KBUILD_CFLAGS := -Wno-error -Wundef -Wstrict-prototypes -Wno-trigraphs \ + -fno-strict-aliasing -fno-common \ + -Werror-implicit-function-declaration \ + -Wno-format-security \ +@@ -940,9 +940,51 @@ define filechk_kernel.release + echo "$(KERNELVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))" + endef + ++MS_KERNEL_TYPE := ++ifneq ($(CONFIG_MS_KERNEL_TYPE),"") ++ MS_KERNEL_TYPE=--lib_type $(CONFIG_MS_KERNEL_TYPE) ++endif ++MS_PLATFORM_ID := ++ifneq ($(CONFIG_ARCH_CEDRIC),) ++MS_PLATFORM_ID := C3 ++endif ++ifneq ($(CONFIG_ARCH_INFINITY),) ++MS_PLATFORM_ID := I1 ++endif ++ifneq ($(CONFIG_ARCH_INFINITY3),) ++MS_PLATFORM_ID := I3 ++endif ++ifneq ($(CONFIG_ARCH_CHICAGO),) ++MS_PLATFORM_ID := C4 ++endif ++ ++ ++COMMITNUMBER := g$(shell git log --format=%h -n 1 2> /dev/null) ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++ifeq ($(COMMITNUMBER),g) ++file := gitInformation.txt ++gitLog := $(shell strings ${file}) ++gitTemp := $(subst \#, ,$(gitLog)) ++COMMITNUMBER := g$(word 1, $(gitTemp)) ++BRANCH_ID := g$(word 2, $(gitTemp)) ++endif ++ + # Store (new) KERNELRELEASE string in include/config/kernel.release + include/config/kernel.release: include/config/auto.conf FORCE + $(call filechk,kernel.release) ++# @python scripts/ms_gen_mvxv_h.py drivers/mstar/include/ms_version.h --comp_id KL_LX318 \ ++# --changelist G$$(git describe --match CL* --tags --long | cut -b 12-18 | awk '{print toupper($$0)}') ++ifeq ($(MS_PLATFORM_ID),) ++ @echo "ERROR!! MS_PLATOFRM_ID is empty!!"; /bin/false ++else ++ @echo ' MVXV' ++ @echo ' changelist ${COMMITNUMBER}' ++ @echo ' BRANCHID ${BRANCH_ID} ' ++ @python scripts/ms_gen_mvxv_h.py drivers/mstar/include/ms_version.h --comp_id KL_LX318 \ ++ --changelist $(COMMITNUMBER) --chip_id $(MS_PLATFORM_ID) --branch $(BRANCH_ID) $(MS_KERNEL_TYPE) ++endif ++ + + + # Things we need to do before we recursively start building the kernel +@@ -1092,6 +1134,9 @@ all: modules + # A module can be listed more than once in obj-m resulting in + # duplicate lines in modules.order files. Those are removed + # using awk while concatenating to the final file. ++ifdef CONFIG_XIP_KERNEL ++ MODULE_PACK_OPTIONS += "-x" ++endif + + PHONY += modules + modules: $(vmlinux-dirs) $(if $(KBUILD_BUILTIN),vmlinux) modules.builtin +diff --git a/README b/README +index a24ec89b..a2930faf 100644 +--- a/README ++++ b/README +@@ -1,5 +1,6 @@ + Linux kernel release 3.x + ++ + These are the release notes for Linux version 3. Read them carefully, + as they tell you what this is all about, explain how to install the + kernel, and what to do if something goes wrong. +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 89c4b5cc..75fe0358 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -214,6 +214,9 @@ config FIQ + config NEED_RET_TO_USER + bool + ++config MULTIPLATFORM_XIP_CAPABLE ++ bool ++ + config ARCH_MTD_XIP + bool + +@@ -310,7 +313,7 @@ config ARCH_MULTIPLATFORM + depends on MMU + select ARCH_WANT_OPTIONAL_GPIOLIB + select ARM_HAS_SG_CHAIN +- select ARM_PATCH_PHYS_VIRT ++ select ARM_PATCH_PHYS_VIRT if !XIP_KERNEL + select AUTO_ZRELADDR + select CLKSRC_OF + select COMMON_CLK +@@ -898,6 +901,8 @@ source "arch/arm/mach-meson/Kconfig" + + source "arch/arm/mach-msm/Kconfig" + ++source "arch/arm/mach-mstar/Kconfig" ++ + source "arch/arm/mach-moxart/Kconfig" + + source "arch/arm/mach-mv78xx0/Kconfig" +@@ -1712,6 +1717,7 @@ config FORCE_MAX_ZONEORDER + range 11 64 if ARCH_SHMOBILE_LEGACY + default "12" if SOC_AM33XX + default "9" if SA1111 || ARCH_EFM32 ++ default "10" if ARCH_MSTAR + default "11" + help + The kernel memory allocator divides physically contiguous memory +@@ -1973,7 +1979,7 @@ endchoice + + config XIP_KERNEL + bool "Kernel Execute-In-Place from ROM" +- depends on !ARM_LPAE && !ARCH_MULTIPLATFORM ++ depends on (!ARM_LPAE && !ARCH_MULTIPLATFORM) || (!ARM_LPAE && MULTIPLATFORM_XIP_CAPABLE) + help + Execute-In-Place allows the kernel to run from non-volatile storage + directly addressable by the CPU, such as NOR flash. This saves RAM +@@ -2159,7 +2165,7 @@ config ARCH_HIBERNATION_POSSIBLE + bool + depends on MMU + default y if ARCH_SUSPEND_POSSIBLE +- ++ + endmenu + + source "net/Kconfig" +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index b5d79884..cc30c609 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -179,6 +179,7 @@ machine-$(CONFIG_ARCH_MESON) += meson + machine-$(CONFIG_ARCH_MMP) += mmp + machine-$(CONFIG_ARCH_MOXART) += moxart + machine-$(CONFIG_ARCH_MSM) += msm ++machine-$(CONFIG_ARCH_MSTAR) += mstar + machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 + machine-$(CONFIG_ARCH_MVEBU) += mvebu + machine-$(CONFIG_ARCH_MXC) += imx +@@ -215,6 +216,7 @@ machine-$(CONFIG_ARCH_W90X900) += w90x900 + machine-$(CONFIG_ARCH_ZYNQ) += zynq + machine-$(CONFIG_PLAT_SPEAR) += spear + ++ + # Platform directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. + plat-$(CONFIG_ARCH_EXYNOS) += samsung +@@ -318,6 +320,12 @@ $(INSTALL_TARGETS): + + %.dtb: | scripts + $(Q)$(MAKE) $(build)=$(boot)/dts MACHINE=$(MACHINE) $(boot)/dts/$@ ++ @if [ -e arch/arm/boot/Image ]; then \ ++ echo " BNDTB $@"; \ ++ python scripts/ms_builtin_dtb_update.py arch/arm/boot/Image arch/arm/boot/dts/$@; \ ++ echo; \ ++ fi; ++ + + PHONY += dtbs dtbs_install + dtbs dtbs_install: prepare scripts +diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile +index ec2f8065..c9806770 100644 +--- a/arch/arm/boot/Makefile ++++ b/arch/arm/boot/Makefile +@@ -11,6 +11,29 @@ + # Copyright (C) 1995-2002 Russell King + # + ++ ++MKIMAGE_BIN = scripts/mkimage ++MZ_BIN = scripts/mz ++KERNEL_RELEASE_FILE = include/config/kernel.release ++ROOTFS = $(obj)/ramdisk_linaro4.8_minit.img.xz ++ ++MS_BUILTIN_DTB=arch/arm/boot/dts/infinity3-BGA128M.dtb ++_BUILTIN_DTB_NAME=$(strip $(shell echo ${CONFIG_MS_BUILTIN_DTB})) ++ifneq ($(_BUILTIN_DTB_NAME),) ++ifneq ($(wildcard arch/arm/boot/dts/$(_BUILTIN_DTB_NAME).dts),) ++MS_BUILTIN_DTB=arch/arm/boot/dts/$(_BUILTIN_DTB_NAME).dtb ++endif ++endif ++ ++MS_EXTRA_DTBS= ++ifneq ($(CONFIG_ARCH_INFINITY),) ++MS_EXTRA_DTBS=arch/arm/boot/dts/infinity-fpga.dtb arch/arm/boot/dts/infinity-zebu.dtb ++endif ++ ++#ifneq ($(CONFIG_ARCH_INFINITY3),) ++#MS_EXTRA_DTBS=arch/arm/boot/dts/infinity3-fpga.dtb arch/arm/boot/dts/infinity3-fpgaxl.dtb ++#endif ++ + ifneq ($(MACHINE),) + include $(srctree)/$(MACHINE)/Makefile.boot + endif +@@ -19,6 +42,7 @@ endif + # ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET) + # PARAMS_PHYS must be within 4MB of ZRELADDR + # INITRD_PHYS must be in RAM ++LOADADDR := 0x40008000 + ZRELADDR := $(zreladdr-y) + PARAMS_PHYS := $(params_phys-y) + INITRD_PHYS := $(initrd_phys-y) +@@ -29,9 +53,19 @@ targets := Image zImage xipImage bootpImage uImage + + ifeq ($(CONFIG_XIP_KERNEL),y) + +-$(obj)/xipImage: vmlinux FORCE ++$(obj)/xipImage: vmlinux FORCE $(MS_BUILTIN_DTB) $(MS_EXTRA_DTBS) + $(call if_changed,objcopy) + @$(kecho) ' Kernel: $@ is ready (physical address: $(CONFIG_XIP_PHYS_ADDR))' ++ @test "${MS_BUILTIN_DTB}" = "" || \ ++ if [ -e ${MS_BUILTIN_DTB} ]; then \ ++ echo " BNDTB ${MS_BUILTIN_DTB}"; \ ++ python scripts/ms_builtin_dtb_update.py $@ ${MS_BUILTIN_DTB}; \ ++ echo; \ ++ fi; ++ @python scripts/ms_bin_option_update_int.py $@ '#IMG_SZ#' $$(stat -c %s $@) ++ @python scripts/ms_bin_option_update_int.py $@ '#XIP_PA#' $(CONFIG_XIP_PHYS_ADDR) ++ @echo " xipImage size: $(shell stat -c %s $@) bytes" ++ + + $(obj)/Image $(obj)/zImage: FORCE + @echo 'Kernel configured for XIP (CONFIG_XIP_KERNEL=y)' +@@ -44,9 +78,87 @@ $(obj)/xipImage: FORCE + @echo 'Kernel not configured for XIP (CONFIG_XIP_KERNEL!=y)' + @false + +-$(obj)/Image: vmlinux FORCE ++$(obj)/Image: vmlinux FORCE $(MS_BUILTIN_DTB) $(MS_EXTRA_DTBS) + $(call if_changed,objcopy) +- @$(kecho) ' Kernel: $@ is ready' ++ ++ #update builtin DTB ++ @test "${MS_BUILTIN_DTB}" = "" || \ ++ if [ -e ${MS_BUILTIN_DTB} ]; then \ ++ echo " BNDTB ${MS_BUILTIN_DTB}"; \ ++ python scripts/ms_builtin_dtb_update.py $@ ${MS_BUILTIN_DTB}; \ ++ echo; \ ++ fi; ++ ++ #update the image size into Image ++ @python scripts/ms_bin_option_update_int.py $@ '#IMG_SZ#' $$(stat -c %s $@) ++ ++ #build Image ++ @LD_ADDR=40008000; \ ++ IMGNAME=Linux-`cat $(KERNEL_RELEASE_FILE)`; \ ++# if [ -e ${MKIMAGE_BIN} ]; then \ ++# ${MKIMAGE_BIN} -A arm -O linux -T kernel -C none -a $${LD_ADDR} -e $${LD_ADDR} -n $${IMGNAME} -d $@ $(obj)/uImage; \ ++# echo; \ ++# else \ ++# echo ">> Can't find $${MKIMAGE}. Please check the u-boot path or build u-boot <<"; \ ++# fi; \ ++# if [ -e $(ROOTFS) ]; then \ ++# ${MKIMAGE_BIN} -A arm -O linux -T multi -C none -a $${LD_ADDR} -e $${LD_ADDR} -n $${IMGNAME} -d $@:$(ROOTFS) $(obj)/kernel.img; \ ++# echo; \ ++# if [ -e ${MZ_BIN} ]; then \ ++# ${MZ_BIN} c $@ $@.mz ; \ ++# echo; \ ++# ${MKIMAGE_BIN} -A arm -O linux -T multi -C mz -a $${LD_ADDR} -e $${LD_ADDR} -n $${IMGNAME} -d $@.mz:$(ROOTFS) $(obj)/kernel.mz.img; \ ++# echo; \ ++# fi; \ ++# fi; ++ @$(kecho) ' Kernel: $@ is ready' ++ @echo ++ifneq ($(CONFIG_ARCH_INFINITY),) ++ @echo 'Building extra images wifh different DTB for iNfinity:' ++ @echo ++# @if [ -e "arch/arm/boot/dts/infinity-zebu.dtb" ]; then \ ++# echo " IMAGE $(obj)/Image-zebu"; \ ++# cp -f $(obj)/Image $(obj)/Image-zebu; \ ++# echo " BNDTB infinity-zebu.dtb"; \ ++# python scripts/ms_builtin_dtb_update.py $(obj)/Image-zebu "arch/arm/boot/dts/infinity-zebu.dtb"; \ ++# echo; \ ++# fi; ++ ++ @if [ -e "arch/arm/boot/dts/infinity-fpga.dtb" ]; then \ ++ echo " IMAGE $(obj)/Image-fpga"; \ ++ cp -f $(obj)/Image $(obj)/Image-fpga; \ ++ echo " BNDTB infinity-fpga.dtb"; \ ++ python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpga "arch/arm/boot/dts/infinity-fpga.dtb"; \ ++ echo; \ ++ fi; ++endif ++ifneq ($(CONFIG_ARCH_INFINITY3),) ++# @echo 'Building extra images wifh different DTB for iNfinity3:' ++# @echo ++# @if [ -e "arch/arm/boot/dts/inf3-zebu.dtb" ]; then \ ++# echo " IMAGE $(obj)/Image-zebu"; \ ++# cp -f $(obj)/Image $(obj)/Image-zebu; \ ++# echo " BNDTB inf3-zebu.dtb"; \ ++# python scripts/ms_builtin_dtb_update.py $(obj)/Image-zebu "arch/arm/boot/dts/inf3-zebu.dtb"; \ ++# echo; \ ++# fi; ++ ++# @if [ -e "arch/arm/boot/dts/infinity3-fpga.dtb" ]; then \ ++# echo " IMAGE $(obj)/Image-fpga"; \ ++# cp -f $(obj)/Image $(obj)/Image-fpga; \ ++# echo " BNDTB infinity3-fpga.dtb"; \ ++# python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpga "arch/arm/boot/dts/infinity3-fpga.dtb"; \ ++# echo; \ ++# fi; ++## Run Kernel file system on norflash with infinity3-fpgaxl.dts ++# @if [ -e "arch/arm/boot/dts/infinity3-fpgaxl.dtb" ]; then \ ++# echo " IMAGE $(obj)/Image-fpgaxl"; \ ++# cp -f $(obj)/Image $(obj)/Image-fpgaxl; \ ++# echo " BNDTB infinity3-fpgaxl.dtb"; \ ++# python scripts/ms_builtin_dtb_update.py $(obj)/Image-fpgaxl "arch/arm/boot/dts/infinity3-fpgaxl.dtb"; \ ++# echo; \ ++# fi; ++endif + + $(obj)/compressed/vmlinux: $(obj)/Image FORCE + $(Q)$(MAKE) $(build)=$(obj)/compressed $@ +diff --git a/arch/arm/boot/dts/cedric-154a.dts b/arch/arm/boot/dts/cedric-154a.dts +new file mode 100644 +index 00000000..d4e5e6ce +--- /dev/null ++++ b/arch/arm/boot/dts/cedric-154a.dts +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "cedric.dtsi" ++ ++/ { ++ model = "Cedric MST154A Board"; ++ compatible = "mstar,cedric"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ /*bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait sysp=squashfs:/dev/block/mtdblock0 datap=jffs2:/dev/block/mtdblock1";*/ ++ ++ linux,initrd-start = <0x45000000>; ++ linux,initrd-end = <0x45020000>; ++ }; ++ ++ ++ ++ memory { ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ sysp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x50000000 0x02000000>; ++ bank-width = <1>; ++ }; ++ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x52000000 0x00020000>; ++ bank-width = <1>; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/cedric-clks.dtsi b/arch/arm/boot/dts/cedric-clks.dtsi +new file mode 100644 +index 00000000..6ca5c23f +--- /dev/null ++++ b/arch/arm/boot/dts/cedric-clks.dtsi +@@ -0,0 +1,1153 @@ ++&clks { ++ ++ clk_mpll_432M: clk_mpll_432M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++ }; ++ ++ clk_mpll_288M: clk_mpll_288M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++ }; ++ ++ clk_utmi_240M: clk_utmi_240M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <240000000>; ++ }; ++ ++ clk_mpll_216M: clk_mpll_216M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++ }; ++ ++ clk_utmi_192M: clk_utmi_192M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <192000000>; ++ }; ++ ++ clk_mpll_172M: clk_mpll_172M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172000000>; ++ }; ++ ++ clk_utmi_160M: clk_utmi_160M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <160000000>; ++ }; ++ ++ clk_mpll_123M: clk_mpll_123M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123000000>; ++ }; ++ ++ clk_mpll_86M: clk_mpll_86M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86000000>; ++ }; ++ ++ clk_mpll_144M: clk_mpll_144M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_288M>; ++ clock-mult = <1>; ++ clock-div = <2>; ++ }; ++ ++ clk_mpll_72M: clk_mpll_72M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_288M>; ++ clock-mult = <1>; ++ clock-div = <4>; ++ }; ++ ++ clk_mpll_36M: clk_mpll_36M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_288M>; ++ clock-mult = <1>; ++ clock-div = <8>; ++ }; ++ ++ clk_mpll_108M: clk_mpll_108M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_216M>; ++ clock-mult = <1>; ++ clock-div = <2>; ++ }; ++ ++ clk_mpll_54M: clk_mpll_54M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_216M>; ++ clock-mult = <1>; ++ clock-div = <4>; ++ }; ++ ++ clk_mpll_27M: clk_mpll_27M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_216M>; ++ clock-mult = <1>; ++ clock-div = <8>; ++ }; ++ ++ clk_mpll_61M: clk_mpll_61M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_123M>; ++ clock-mult = <1>; ++ clock-div = <2>; ++ }; ++ ++ clk_mpll_43M: clk_mpll_43M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_86M>; ++ clock-mult = <1>; ++ clock-div = <2>; ++ }; ++ ++ clk_mpll_21M: clk_mpll_21M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_86M>; ++ clock-mult = <1>; ++ clock-div = <4>; ++ }; ++ ++ clk_mpll_5M: clk_mpll_5M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_mpll_86M>; ++ clock-mult = <1>; ++ clock-div = <16>; ++ }; ++ ++ clk_utmi_48M: clk_utmi_48M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_utmi_192M>; ++ clock-mult = <1>; ++ clock-div = <4>; ++ }; ++ ++ clk_utmi_40M: clk_utmi_40M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_utmi_160M>; ++ clock-mult = <1>; ++ clock-div = <4>; ++ }; ++ ++ clk_utmi_32M: clk_utmi_32M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_utmi_160M>; ++ clock-mult = <1>; ++ clock-div = <5>; ++ }; ++ ++ clk_utmi_20M: clk_utmi_20M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_utmi_160M>; ++ clock-mult = <1>; ++ clock-div = <8>; ++ }; ++ ++ clk_xtali_12M: clk_xtali_12M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++ }; ++ ++ clk_xtali_1M: clk_xtali_1M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_xtali_12M>; ++ clock-mult = <1>; ++ clock-div = <8>; ++ }; ++ ++ clk_xtali_750K: clk_xtali_750K { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_xtali_12M>; ++ clock-mult = <1>; ++ clock-div = <16>; ++ }; ++ ++ clk_xtali_300K: clk_xtali_300K { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_xtali_12M>; ++ clock-mult = <1>; ++ clock-div = <40>; ++ }; ++ ++ clk_xtali_187K: clk_xtali_187K { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_xtali_12M>; ++ clock-mult = <1>; ++ clock-div = <64>; ++ }; ++ ++ clk_xtali_93K: clk_xtali_93K { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&clk_xtali_12M>; ++ clock-mult = <1>; ++ clock-div = <128>; ++ }; ++ ++ clk_RTC_CLK_32K: clk_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ }; ++ ++ clk_miupll_clk: clk_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_ddrpll_clk: clk_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_lpll_clk: clk_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_cpupll_clk: clk_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_in: clk_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_top: clk_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_sc_gp: clk_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_vhe_gp: clk_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_hemcu_gp: clk_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_mipi_if_gp: clk_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_riu_w_clk_mcu_if_gp: clk_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_fuart0_synth_out: clk_clk_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_miu: clk_clk_miu { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_miu_p: clk_clk_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_miu_vhe_gp_p: clk_clk_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_miu_sc_gp_p: clk_clk_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_miu2x_p: clk_clk_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_mcu_p: clk_clk_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_mcu_pm_p: clk_clk_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_isp_p: clk_clk_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_fclk1_p: clk_clk_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_sdio_p: clk_clk_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_fcie_p: clk_clk_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_tck_buf: clk_clk_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_pad2isp_sr_pclk: clk_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_csi2_mac_p: clk_clk_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_ccir_in_clk: clk_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_eth_buf: clk_clk_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_rmii_buf: clk_clk_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_clk_emac_testrx125_in_lan: clk_clk_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <0>; ++ }; ++ ++ clk_miu: clk_miu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_216M>, <&clk_miupll_clk>; ++ bist = <0>; ++ glitch = <1>; ++ }; ++ ++ clk_miu_ff: clk_miu_ff { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc_gp: clk_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_vhe_gp: clk_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_dig: clk_miu_dig { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_xd2miu: clk_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_urdma: clk_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_bdma: clk_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_vhe: clk_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_vhe_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_mfeh: clk_miu_mfeh { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_mfe: clk_miu_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_jpe1: clk_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_jpe0: clk_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_bach: clk_miu_bach { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_file: clk_miu_file { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_uhc0: clk_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_emac: clk_miu_emac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_cmdq: clk_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_isp_dnr: clk_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_isp_rot: clk_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_isp_dma: clk_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_isp_sta: clk_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_gop: clk_miu_gop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc_dnr: clk_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc_dnr_sad: clk_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc_crop: clk_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc1_frm: clk_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc1_snp: clk_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc1_snpi: clk_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc1_dbg: clk_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc2_frm: clk_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc2_snpi: clk_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sc3_frm: clk_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_fcie: clk_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_sdio: clk_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_sc_gp_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu: clk_riu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_top>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu_nogating: clk_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_in>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu_sc_gp: clk_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_sc_gp>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu_vhe_gp: clk_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_vhe_gp>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu_hemcu_gp: clk_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_hemcu_gp>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu_mipi_gp: clk_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_mipi_if_gp>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_riu_mcu_if: clk_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_riu_w_clk_mcu_if_gp>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu2x: clk_miu2x { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_ddrpll_clk>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_axi2x: clk_axi2x { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu2x_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_ddr_syn: clk_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_432M>, <&clk_mpll_216M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miu_rec: clk_miu_rec { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_1M>, <&clk_xtali_750K>, <&clk_xtali_187K>, <&clk_xtali_93K>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_tck: clk_tck { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_tck_buf>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_mcu: clk_mcu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_216M>, <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_mpll_108M>; ++ bist = <0>; ++ glitch = <1>; ++ }; ++ ++ clk_riubrdg: clk_riubrdg { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_mcu_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_bdma: clk_bdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_spi: clk_spi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_216M>, <&clk_mpll_108M>, <&clk_mpll_86M>, <&clk_mpll_72M>; ++ bist = <0>; ++ glitch = <1>; ++ }; ++ ++ clk_uart0: clk_uart0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_uart1: clk_uart1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_fuart0_synth_in: clk_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_432M>, <&clk_mpll_216M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_fuart: clk_fuart { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_144M>, <&clk_xtali_12M>, <&clk_clk_fuart0_synth_out>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_mspi0: clk_mspi0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_mspi1: clk_mspi1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miic0: clk_miic0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_72M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_miic1: clk_miic1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_72M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_bist: clk_bist { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <1>; ++ glitch = <0>; ++ }; ++ ++ clk_xtali: clk_xtali { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_live: clk_live { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_sr_mclk: clk_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_27M>, <&clk_mpll_21M>, <&clk_xtali_12M>, <&clk_mpll_5M>, <&clk_mpll_36M>, <&clk_mpll_54M>, <&clk_mpll_43M>, <&clk_mpll_61M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_bist_pm: clk_bist_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <1>; ++ glitch = <0>; ++ }; ++ ++ clk_bist_vhe_gp: clk_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <1>; ++ glitch = <0>; ++ }; ++ ++ clk_vhe: clk_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_utmi_240M>, <&clk_mpll_216M>, <&clk_utmi_192M>, <&clk_utmi_160M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_xtali_sc_gp: clk_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_bist_sc_gp: clk_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <1>; ++ glitch = <0>; ++ }; ++ ++ clk_imi: clk_imi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_emac_ahb: clk_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_144M>, <&clk_mpll_123M>, <&clk_mpll_86M>, <&clk_clk_emac_testrx125_in_lan>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_mfe: clk_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_288M>, <&clk_utmi_240M>, <&clk_utmi_192M>, <&clk_mpll_123M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_jpe: clk_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_288M>, <&clk_mpll_216M>, <&clk_mpll_54M>, <&clk_mpll_27M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_aesdma: clk_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_86M>, <&clk_mpll_172M>; ++ bist = <0>; ++ glitch = <1>; ++ }; ++ ++ clk_sdio: clk_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_utmi_48M>, <&clk_mpll_43M>, <&clk_utmi_40M>, <&clk_mpll_36M>, <&clk_utmi_32M>, <&clk_utmi_20M>, <&clk_xtali_12M>, <&clk_xtali_300K>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_fcie: clk_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_72M>, <&clk_mpll_61M>, <&clk_mpll_54M>, <&clk_xtali_12M>, <&clk_mpll_86M>, <&clk_utmi_48M>, <&clk_mpll_43M>, <&clk_utmi_40M>, <&clk_mpll_36M>, <&clk_utmi_32M>, <&clk_utmi_20M>, <&clk_mpll_5M>, <&clk_xtali_300K>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_sdio: clk_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_sdio_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_fcie: clk_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_fcie_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_ecc: clk_ecc { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_utmi_160M>, <&clk_mpll_108M>, <&clk_mpll_54M>, <&clk_xtali_12M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_sr: clk_sr { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_pad2isp_sr_pclk>, <&clk_clk_csi2_mac_p>, <&clk_utmi_40M>, <&clk_mpll_86M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_isp: clk_isp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_123M>, <&clk_mpll_86M>, <&clk_mpll_72M>, <&clk_mpll_54M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_idclk: clk_idclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_isp_p>, <&clk_ccir_in_clk>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_fclk1: clk_fclk1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_86M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_fclk2: clk_fclk2 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_172M>, <&clk_mpll_86M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_odclk: clk_odclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_86M>, <&clk_mpll_43M>, <&clk_mpll_21M>, <&clk_lpll_clk>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_gop: clk_gop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_fclk1_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_nlm: clk_nlm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_miu_p>, <&clk_clk_fclk1_p>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_emac_tx: clk_emac_tx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_eth_buf>, <&clk_clk_rmii_buf>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_emac_rx: clk_emac_rx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_eth_buf>, <&clk_clk_rmii_buf>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_emac_tx_ref: clk_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_rmii_buf>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_emac_rx_ref: clk_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_clk_rmii_buf>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_hemcu_216m: clk_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_mpll_216M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_csi_mac: clk_csi_mac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_12M>, <&clk_mpll_216M>, <&clk_mpll_288M>, <&clk_mpll_172M>, <&clk_mpll_123M>, <&clk_mpll_86M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_mac_lptx: clk_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_12M>, <&clk_mpll_216M>, <&clk_mpll_288M>, <&clk_mpll_172M>, <&clk_mpll_123M>, <&clk_mpll_86M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++ clk_ns: clk_ns { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&clk_xtali_12M>, <&clk_mpll_216M>; ++ bist = <0>; ++ glitch = <0>; ++ }; ++ ++}; +\ No newline at end of file +diff --git a/arch/arm/boot/dts/cedric.dtsi b/arch/arm/boot/dts/cedric.dtsi +new file mode 100644 +index 00000000..9b14175c +--- /dev/null ++++ b/arch/arm/boot/dts/cedric.dtsi +@@ -0,0 +1,260 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../drivers/mstar/include/cedric/irqs.h> ++#include "skeleton.dtsi" ++ ++/ { ++ compatible = "mstar,cedric"; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a9"; ++ reg = <0x0>; ++ }; ++ ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <26000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ sdmmc0 = &sd0; ++ sdmmc1 = &sd1; ++ sdmmc2 = &sd2; ++ iic0 = &i2c0; ++ iic1 = &i2c1; ++ }; ++ ++ ++ ++ soc { ++ ++ compatible = "simple-bus"; ++ interrupt-parent = <&intrctl>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xFFFFFFFF>; ++ ++ intrctl: interrupt-controller@0 { ++ compatible = "mstar,intrctl-cedric"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ ++ cpuclk: clk@1F221800 { ++ compatible = "mstar,cedric-cpuclk"; ++ #clock-cells = <1>; ++ reg = <0x1F221800 0x100>; ++ clocks = <&xtal>; ++ }; ++ ++ ++ timer_clocksource: timer@16000200 { ++ compatible = "mstar,arm-gt-clocksource"; ++ reg = <0x16000200 0x100>; ++ clocks = <&cpuclk 1>; ++ }; ++ ++ ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ uart0: uart@1F201300 { ++ compatible = "mstar,uart"; ++ reg = <0x1F201300 0x100>; ++ interrupts= ; ++ clocks = <&uart0clk>; ++ tolerance = <2>; ++ status = "ok"; ++ }; ++ ++ emmc:emmc0{ ++ compatible = "mstar,emmc-cedric"; ++// reg = <0x1F201300 0x100>; ++ interrupts=; ++ }; ++ ++ sd0: sd@0 { ++ compatible = "mstar,sdmmc-cedric"; ++// reg = <0x1F201300 0x100>; ++ interrupts=,; ++ }; ++ ++ sd1: sd@1 { ++ compatible = "mstar,sdmmc-cedric"; ++// reg = <0x1F201300 0x100>; ++ interrupts=,; ++ }; ++ ++ sd2: sd@2 { ++ compatible = "mstar,sdmmc-cedric"; ++// reg = <0x1F201300 0x100>; ++ interrupts=,; ++ }; ++ ++ sound { ++ compatible = "mstar,bach-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ ++ mpll_442M: mpll_442M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&xtal>; ++ clock-mult = <34>; ++ clock-div = <2>; ++ }; ++ ++ mpll_221M: mpll_221M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&xtal>; ++ clock-mult = <34>; ++ clock-div = <4>; ++ }; ++ ++ mpll_176M: mpll_176M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&xtal>; ++ clock-mult = <34>; ++ clock-div = <5>; ++ }; ++ ++ mpll_147M: mpll_147M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&xtal>; ++ clock-mult = <34>; ++ clock-div = <6>; ++ }; ++ ++ mpll_126M: mpll_126M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&xtal>; ++ clock-mult = <34>; ++ clock-div = <7>; ++ }; ++ ++ mpll_110M: mpll_110M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&xtal>; ++ clock-mult = <34>; ++ clock-div = <8>; ++ }; ++ ++ usbpll_480M: usbpll_480M { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <480000000>; ++ }; ++ ++ usbpll_160M: usbpll_160M { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&usbpll_480M>; ++ clock-mult = <1>; ++ clock-div = <3>; ++ }; ++ ++ uart0clk: uart0clk { ++ #clock-cells = <0>; ++ compatible = "mstar,cedric-uartclk"; ++ clocks = <&mpll_176M>, <&usbpll_160M>, <&mpll_147M>, <&mpll_126M>, <&mpll_110M>; ++ reg = <0x1F20164C 0x4>; ++ mux-shift = <10>; ++ mux-width = <3>; ++ gate-shift = <8>; ++ }; ++ ++ mfe: mfe { ++ compatible = "mstar,mfe"; ++ reg = <0x1F206600 0x100>,<0x1F222000 0x200>; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ banks = <0x1F2A0C00>,<0x1F2A0E00>,<0x1F2A1000>,<0x1F2A1200>,<0x1F2A1400 >,<0x1F2A1600 >,<0x1F2A1800 >,<0x1F2A1A00 >; ++ interrupts=; ++ }; ++ ir:ir0{ ++ compatible = "mstar,ir"; ++ reg = <0x1F007A00 0x100>; ++ interrupts=,; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ }; ++ ++ i2c0: i2c@0{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203400 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ i2c-group = <0>; ++ i2c-speed = <2>;//0~6 ++ ++ 24c02@54 { ++ compatible = "mstar,24c02"; ++ reg = <0x54>; ++ }; ++ }; ++ ++ i2c1: i2c@1{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ i2c-group = <1>; ++ i2c-speed = <2>;//0~6 ++ status = "disable"; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "mstar,gpio"; ++ reg = <0x1F207800 0x200>,<0x1F203C00 0x200>; ++ gpio-num = <183>; ++ }; ++ ++ }; ++}; ++ ++ ++/include/ "cedric-clks.dtsi" +diff --git a/arch/arm/boot/dts/chicago.dts b/arch/arm/boot/dts/chicago.dts +new file mode 100644 +index 00000000..d3ca9ad2 +--- /dev/null ++++ b/arch/arm/boot/dts/chicago.dts +@@ -0,0 +1,33 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "chicago.dtsi" ++ ++/ { ++ model = "CHICAGO XXXXX Board"; ++ compatible = "mstar,chicago"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x25000000>; ++ linux,initrd-end = <0x25040000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x07000000>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/chicago.dtsi b/arch/arm/boot/dts/chicago.dtsi +new file mode 100644 +index 00000000..db25e6c9 +--- /dev/null ++++ b/arch/arm/boot/dts/chicago.dtsi +@@ -0,0 +1,104 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../drivers/mstar/include/chicago/irqs.h> ++#include "skeleton.dtsi" ++ ++/ { ++ compatible = "mstar,chicago"; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ clock-frequency = <800000000>; ++ }; ++ ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <26000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ //sdmmc0 = &sd0; ++ }; ++ ++ ++ ++ soc { ++ ++ compatible = "simple-bus"; ++ interrupt-parent = <&intrctl>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xFFFFFFFF>; ++ ++ intrctl: interrupt-controller@0 { ++ compatible = "mstar,intrctl-chicago"; ++ #interrupt-cells = <1>; ++ interrupt-controller; ++ }; ++ /* ++ cpuclk: clk@1F221800 { ++ compatible = "mstar,chicago-cpuclk"; ++ #clock-cells = <1>; ++ reg = <0x1F221800 0x100>; ++ clocks = <&xtal>; ++ };*/ ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ /*interrupts = , ++ , ++ , ++ ;*/ ++ clock-frequency = <400000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ timer_clocksource: timer@1F007780 { ++ compatible = "mstar,piu-clocksource"; ++ reg = <0x1F007780 0x40>; ++ clocks = <&xtal>; ++ }; ++ ++ ++ timer_clockevent: timer@1F0069C0 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F0069C0 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ uart0: uart@1F007600 { ++ compatible = "mstar,uart"; ++ reg = <0x1F007600 0x100>; ++ interrupts= ; ++ clocks = <&xtal>; ++ tolerance = <2>; ++ status = "ok"; ++ }; ++ ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-MSC315.dts b/arch/arm/boot/dts/infinity-MSC315.dts +new file mode 100644 +index 00000000..0505cf53 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-MSC315.dts +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity.dtsi" ++ ++/ { ++ model = "INFINITY MSC315"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++/* ++ sysp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x14380000 0x00400000>; ++ bank-width = <1>; ++ }; ++*/ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ miu_bist_mem: miu_bist_mem@27F80000 { ++ reg = <0x23F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x02800000>; ++ linux,cma-default; ++ }; ++ ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-MSC316.dts b/arch/arm/boot/dts/infinity-MSC316.dts +new file mode 100644 +index 00000000..bb16c8d6 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-MSC316.dts +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity.dtsi" ++ ++/ { ++ model = "INFINITY MSC316"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++/* ++ sysp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x14380000 0x00400000>; ++ bank-width = <1>; ++ }; ++*/ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ miu_bist_mem: miu_bist_mem@27F80000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x06000000>; ++ linux,cma-default; ++ }; ++ ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-MST240A-256M.dts b/arch/arm/boot/dts/infinity-MST240A-256M.dts +new file mode 100644 +index 00000000..e156626e +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-MST240A-256M.dts +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity.dtsi" ++ ++/ { ++ model = "MST240A MSC316Q"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@2FF00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-MST240A.dts b/arch/arm/boot/dts/infinity-MST240A.dts +new file mode 100644 +index 00000000..edd7cf3c +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-MST240A.dts +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity.dtsi" ++ ++/ { ++ model = "MST240A MSC316D"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-MST240B.dts b/arch/arm/boot/dts/infinity-MST240B.dts +new file mode 100644 +index 00000000..31ccf43b +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-MST240B.dts +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity.dtsi" ++ ++/ { ++ model = "MST240B MSC315"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x02000000>; ++ linux,cma-default; ++ }; ++ ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-MST240C.dts b/arch/arm/boot/dts/infinity-MST240C.dts +new file mode 100644 +index 00000000..e8b4d205 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-MST240C.dts +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity.dtsi" ++ ++/ { ++ model = "MST240C MSC313"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x02000000>; ++ linux,cma-default; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-clks.dtsi b/arch/arm/boot/dts/infinity-clks.dtsi +new file mode 100644 +index 00000000..0374f3cb +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-clks.dtsi +@@ -0,0 +1,1473 @@ ++/* generated by CLK_DT_GEN_4 */ ++/* CLK FILENAME: I1\20151127\iNfinity_Clock_Table_20151127.xls */ ++/* REG FILENAME: I1\20151127\iNfinity_reg_CLKGEN_20151127.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_xtali_12m>; ++}; ++ ++CLK_usb: CLK_usb { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_utmi>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172000000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123000000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86000000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32768>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_pm>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_isp_p: CLK_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_isp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fcie_p: CLK_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fcie>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_tx_in_lan: CLK_emac_tx_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_rx_in_lan: CLK_emac_rx_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_mii_tx: CLK_mii_tx { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_mii_rx: CLK_mii_rx { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_tx_reg_pad: CLK_emac_tx_reg_pad { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp: CLK_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe: CLK_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfeh: CLK_miu_mfeh { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfe: CLK_miu_mfe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe1: CLK_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe0: CLK_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bach: CLK_miu_bach { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_file: CLK_miu_file { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_uhc0: CLK_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_emac: CLK_miu_emac { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_cmdq: CLK_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dnr: CLK_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_rot: CLK_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dma: CLK_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_sta: CLK_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_gop: CLK_miu_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr: CLK_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_crop: CLK_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_frm: CLK_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snp: CLK_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snpi: CLK_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_dbg: CLK_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_frm: CLK_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_snpi: CLK_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc3_frm: CLK_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_fcie: CLK_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sdio: CLK_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_top: CLK_riu_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_vhe_gp: CLK_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck: CLK_tck { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_tck_buf>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop: CLK_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_csi_mac>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_ddrpll_clk>,<&CLK_VOID>,<&CLK_miupll_clk>,<&CLK_mpll_216m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr_mclk: CLK_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_mpll_288m_div8>,<&CLK_mpll_216m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_123m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_bist_pm: CLK_bist_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_VOID>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_utmi_160m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++}; ++ ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_miu_p>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_IMI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++}; ++ ++CLK_mfe: CLK_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_fcie: CLK_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_mpll_86m_div16>,<&CLK_xtali_12m_div40>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCIE_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_FCIE_OFFSET ++}; ++ ++CLK_ecc: CLK_ecc { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET ++}; ++ ++CLK_sr: CLK_sr { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_pad2isp_sr_pclk>,<&CLK_csi2_mac_p>,<&CLK_utmi_160m_div4>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SR_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SR_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++}; ++ ++CLK_idclk: CLK_idclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_isp_p>,<&CLK_ccir_in_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_IDCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_IDCLK_OFFSET ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++}; ++ ++CLK_fclk2: CLK_fclk2 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++}; ++ ++CLK_gop_psram: CLK_gop_psram { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_GOP_PSRAM_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_GOP_PSRAM_OFFSET ++}; ++ ++CLK_nlm: CLK_nlm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_emac_tx_in_lan>,<&CLK_mii_tx>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_emac_rx_in_lan>,<&CLK_mii_rx>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_emac_tx_reg_pad>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_emac_tx_reg_pad>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++}; ++ ++CLK_csi_mac: CLK_csi_mac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET ++}; ++ ++CLK_mac_lptx: CLK_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET ++}; ++ ++CLK_ns: CLK_ns { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_NS_OFFSET ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET ++ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++ auto-enable = <1>; ++}; ++ ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_VOID>, <&CLK_aesdma>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_pm>, <&CLK_bist_sc_gp>, <&CLK_bist_vhe_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_csi_mac>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_ecc>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_in_lan>, <&CLK_emac_rx_ref>, <&CLK_emac_tx>, <&CLK_emac_tx_in_lan>, <&CLK_emac_tx_ref>, <&CLK_emac_tx_reg_pad>, <&CLK_fcie>, <&CLK_fcie_p>, <&CLK_fclk1>, <&CLK_fclk1_p>, <&CLK_fclk2>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_gop>, <&CLK_gop_psram>, <&CLK_hemcu_216m>, <&CLK_idclk>, <&CLK_imi>, <&CLK_ir>, <&CLK_isp>, <&CLK_isp_p>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_mac_lptx>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_mfe>, <&CLK_mii_rx>, <&CLK_mii_tx>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_bach>, <&CLK_miu_bdma>, <&CLK_miu_cmdq>, <&CLK_miu_dig>, <&CLK_miu_emac>, <&CLK_miu_fcie>, <&CLK_miu_ff>, <&CLK_miu_file>, <&CLK_miu_gop>, <&CLK_miu_isp_dma>, <&CLK_miu_isp_dnr>, <&CLK_miu_isp_rot>, <&CLK_miu_isp_sta>, <&CLK_miu_jpe0>, <&CLK_miu_jpe1>, <&CLK_miu_mfe>, <&CLK_miu_mfeh>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc1_dbg>, <&CLK_miu_sc1_frm>, <&CLK_miu_sc1_snp>, <&CLK_miu_sc1_snpi>, <&CLK_miu_sc2_frm>, <&CLK_miu_sc2_snpi>, <&CLK_miu_sc3_frm>, <&CLK_miu_sc_crop>, <&CLK_miu_sc_dnr>, <&CLK_miu_sc_dnr_sad>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_sdio>, <&CLK_miu_uhc0>, <&CLK_miu_urdma>, <&CLK_miu_vhe>, <&CLK_miu_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi0>, <&CLK_mspi1>, <&CLK_nlm>, <&CLK_ns>, <&CLK_odclk>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_riu>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_top>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_sr>, <&CLK_sr_mclk>, <&CLK_tck>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_vhe>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>, <&CLK_usb>; ++ clock-count = <174>; ++}; ++ +diff --git a/arch/arm/boot/dts/infinity-fpga.dts b/arch/arm/boot/dts/infinity-fpga.dts +new file mode 100644 +index 00000000..bb4ee66a +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-fpga.dts +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity-fpga.dtsi" ++ ++/ { ++ model = "INFINITY XXXXX Board"; ++ compatible = "mstar,infinity"; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait sysp=squashfs:/dev/block/mtdblock0 datap=jffs2:/dev/block/mtdblock1"; ++ linux,initrd-start = <0x25000000>; ++ linux,initrd-end = <0x25020000>; ++ }; ++ ++ ++ sysp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x26000000 0x01F00000>; ++ bank-width = <1>; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27F00000 0x00020000>; ++ bank-width = <1>; ++ }; ++ ++ ++ memory { ++ reg = <0x20000000 0x06000000>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-fpga.dtsi b/arch/arm/boot/dts/infinity-fpga.dtsi +new file mode 100644 +index 00000000..3081ff91 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-fpga.dtsi +@@ -0,0 +1,129 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/mstar/include/infinity/irqs.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++/ { ++ compatible = "mstar,infninity"; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xFFFFFFFF>; ++ ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <12000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ mfe: mfe { ++ compatible = "mstar,mfe"; ++ reg = <0x1F207000 0x100>,<0x1F264800 0x200>; ++ }; ++ ++ vhe: vhe { ++ compatible = "mstar,vhe"; ++ reg = <0x1F207000 0x100>,<0x1F265200 0x200>,<0x1F265000 0x100>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ emac { ++ compatible = "mstar-emac"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>; ++ interrupts= ; ++ }; ++ ++ sound { ++ compatible = "mstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ }; ++ ++ rtc { ++ compatible = "mstar,infinity-rtc"; ++ reg = <0x1F002400 0x100>; ++ clocks = <&xtal>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-gates.dtsi b/arch/arm/boot/dts/infinity-gates.dtsi +new file mode 100644 +index 00000000..fee27904 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-gates.dtsi +@@ -0,0 +1,158 @@ ++GATE_MCM_vhe: GATE_MCM_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226800 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_mfe: GATE_MCM_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226400 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_jpe: GATE_MCM_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226400 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_aesdma: GATE_MCM_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226404 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_emac: GATE_MCM_emac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226408 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_gop: GATE_MCM_gop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226410 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_bach: GATE_MCM_bach { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226404 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_usb: GATE_MCM_usb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226408 0x4>; ++ gate-shift = <0>; ++}; ++ ++ ++GATE_MCM_fcie: GATE_MCM_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226424 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_sdio: GATE_MCM_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226424 0x4>; ++ gate-shift = <8>; ++}; ++ ++/* ++GATE_MCM_urdma: GATE_MCM_urdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226000 0x4>; ++ gate-shift = <8>; ++}; ++*/ ++ ++GATE_SRAM_vhe: GATE_SRAM_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226A40 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_mfe: GATE_SRAM_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <9>; ++}; ++ ++GATE_SRAM_jpe: GATE_SRAM_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_SRAM_aesdma: GATE_SRAM_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <1>; ++}; ++ ++GATE_SRAM_emac: GATE_SRAM_emac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <3>; ++}; ++ ++GATE_SRAM_gop: GATE_SRAM_gop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <5>; ++}; ++ ++GATE_SRAM_bach: GATE_SRAM_bach { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_usb: GATE_SRAM_usb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <11>; ++}; ++ ++ ++GATE_SRAM_fcie: GATE_SRAM_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <4>; ++}; ++ ++GATE_SRAM_sdio: GATE_SRAM_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226640 0x4>; ++ gate-shift = <10>; ++}; ++ ++ ++GATE_SRAM_mailbox: GATE_SRAM_mailbox { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F226240 0x4>; ++ gate-shift = <2>; ++}; +diff --git a/arch/arm/boot/dts/infinity-zebu.dts b/arch/arm/boot/dts/infinity-zebu.dts +new file mode 100644 +index 00000000..86028d5d +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-zebu.dts +@@ -0,0 +1,50 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity-zebu.dtsi" ++ ++/ { ++ model = "INFINITY XXXXX Board"; ++ compatible = "mstar,infinity"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait sysp=squashfs:/dev/block/mtdblock0 datap=jffs2:/dev/block/mtdblock1"; ++// bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x25000000>; ++ linux,initrd-end = <0x25020000>; ++ }; ++ ++ ++ sysp:rammtd@0 { ++ compatible = "mtd-ram"; ++// reg= <0x26000000 0x02000000>; ++ reg= <0x28000000 0x02000000>; ++ bank-width = <1>; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++// reg= <0x25F00000 0x00100000>; ++ reg= <0x2A000000 0x00020000>; ++ bank-width = <1>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity-zebu.dtsi b/arch/arm/boot/dts/infinity-zebu.dtsi +new file mode 100644 +index 00000000..acc614b0 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity-zebu.dtsi +@@ -0,0 +1,105 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/mstar/include/infinity/irqs.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++/ { ++ compatible = "mstar,infninity"; ++ ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <12000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xFFFFFFFF>; ++ ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <500000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ }; ++*/ ++ uart0: uart@1F220400 { ++ compatible = "mstar,uart"; ++ reg = <0x1F220400 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>; ++ interrupts= ; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity.dtsi b/arch/arm/boot/dts/infinity.dtsi +new file mode 100644 +index 00000000..aa95aec7 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity.dtsi +@@ -0,0 +1,395 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/mstar/include/infinity/irqs.h> ++#include <../../../../drivers/mstar/include/infinity/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&CLK_cpupll_clk>; ++ }; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_pmsleep_intr: interrupt-controller@0 { ++ compatible = "mstar,pmsleep-intr"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "mstar,mfe"; ++ reg = <0x1F264800 0x200>; ++ interrupts=; ++ clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "mstar,vhe"; ++ reg = <0x1F265200 0x200>,<0x1F265000 0x100>; ++ interrupts=; ++ clocks = <&CLK_vhe>,<&GATE_MCM_vhe>, <&GATE_SRAM_vhe>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "mstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "mstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "mstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "mstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "mstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "mstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "mstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "mstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "mstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++ status = "ok"; ++ }; ++ uart1: uart@1F221200 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++ status = "ok"; ++ }; ++ fuart: uart@1F220400 { ++ compatible = "mstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++ dma = <1>; ++ status = "ok"; ++ }; ++ ++ emac { ++ compatible = "mstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>,<&GATE_MCM_emac>, <&GATE_SRAM_emac>; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ }; ++ ++ nandflash { ++ compatible = "ms-nand"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ }; ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++ }; ++ ++ Mstar-ehci-1 { ++ compatible = "Mstar-ehci-1"; ++ clocks = <&CLK_usb>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ }; ++ spi: spi { ++ compatible = "mstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ }; ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts = ; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "mstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>,<&GATE_MCM_jpe>, <&GATE_SRAM_jpe>; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ i2c0: i2c@0{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ i2c-speed = <2>;//0~6 ++ status = "disable"; ++ }; ++ ++ i2c1: i2c@1{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ i2c-speed = <2>;//0~6 ++ 24c512@54 { ++ compatible = "mstar,24c512"; ++ reg = <0x54>; ++ }; ++ }; ++ ++ gpio:gpio{ ++ compatible = "mstar,gpio"; ++ reg = <0x1F207800 0x200>,<0x1F203C00 0x200>,<0x1F001E00 0x200>,<0x1F001C00 0x200>; ++ gpio-num = <102>; ++ }; ++ ++ sound { ++ compatible = "mstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-sel=<11>; //0~31 ++ linein-gain-level=<2>;//0~7 ++ clocks = <&CLK_usb>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>; ++ }; ++ ++ sdmmc { ++ compatible = "mstar,sdmmc"; ++ interrupts=, ++ , ++ , ++ ; ++ //,,.... fice1->fice2->fice3 setting ++ clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>; ++ }; ++ ++ aesdma { ++ compatible = "mstar,infinity-aes"; ++ clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; ++ }; ++ ++ gop{ ++ compatible = "mstar,infinity-gop"; ++ clocks = <&CLK_gop_psram>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ }; ++ ++ rtc { ++ compatible = "mstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++ }; ++ ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "mstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ }; ++ ++ sar: sar { ++ compatible = "mstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ }; ++ ++ ircut { ++ compatible = "mstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ }; ++ ++ pwm { ++ compatible = "mstar,infinity-pwm"; ++ }; ++ ++ gpioi2c { ++ compatible = "mstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ }; ++ ++ pm { ++ compatible = "mstar,infinity-pm"; ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ detect-gpio = ; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/mstar/include/infinity/reg_clks.h> ++ #include "infinity-clks.dtsi" ++ #include "infinity-gates.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity3-BGA128M.dts b/arch/arm/boot/dts/infinity3-BGA128M.dts +new file mode 100644 +index 00000000..523f4a75 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-BGA128M.dts +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S01A"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++/* ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ ++ }; ++ ++ soc{ ++ //Mstar-ehci-1 { ++ // dpdm_swap=<1>; ++ //}; ++ ++ //Mstar-ehci-2 { ++ // dpdm_swap=<1>; ++ //}; ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-BGA256M.dts b/arch/arm/boot/dts/infinity3-BGA256M.dts +new file mode 100644 +index 00000000..baffffa7 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-BGA256M.dts +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S01A-256M"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x9000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x4>; //max image size 4M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-EXT256M.dts b/arch/arm/boot/dts/infinity3-EXT256M.dts +new file mode 100644 +index 00000000..dc3e2e80 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-EXT256M.dts +@@ -0,0 +1,62 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S02A-256M"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x9000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-EXT512M.dts b/arch/arm/boot/dts/infinity3-EXT512M.dts +new file mode 100644 +index 00000000..513fd301 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-EXT512M.dts +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S02A-512M"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x10000000>; ++ }; ++ ++ temp0:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x30000000 0x10000000>; ++ bank-width = <1>; ++ erase-size = <0x10000>; ++ linux,mtd-name = "temp0"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x2FF00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x7000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN128M.dts b/arch/arm/boot/dts/infinity3-QFN128M.dts +new file mode 100644 +index 00000000..fdcf9844 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN128M.dts +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S04A"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x2>; //enable DNR and disable ROT ++ isp-res = <0x5>; //max image size 4M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN128MDC.dts b/arch/arm/boot/dts/infinity3-QFN128MDC.dts +new file mode 100644 +index 00000000..39f920b7 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN128MDC.dts +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S04A"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@27F00000 { ++ reg = <0x27F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x05000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x3>; //enable DNR and ROT ++ isp-res = <0x5>; //max image size 5M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN64M.dts b/arch/arm/boot/dts/infinity3-QFN64M.dts +new file mode 100644 +index 00000000..4823cd09 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN64M.dts +@@ -0,0 +1,71 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S03A-64M"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@23F00000 { ++ reg = <0x23F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01C00000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0x0>; //Disable DNR and ROT ++ isp-res = <0x1>; //max image size 2M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ vip: vip { ++ CMDQ-mode = <0>; ++ }; ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-QFN64MC.dts b/arch/arm/boot/dts/infinity3-QFN64MC.dts +new file mode 100644 +index 00000000..9af07782 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-QFN64MC.dts +@@ -0,0 +1,72 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3.dtsi" ++ ++/ { ++ model = "INFINITY3 MSC000A-S03A-64M C313"; ++ compatible = "mstar,infinity3"; ++ ++ ++ chosen { ++ bootargs = "console=ttyS0,115200n8r root=/dev/ram rootwait isp_flag=0x0"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ memory { ++ reg = <0x20000000 0x04000000>; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++/* ++ miu_bist_mem: miu_bist_mem@23F00000 { ++ reg = <0x23F00000 0x00100000>; ++ no-map ; ++ status = "okay"; ++ }; ++*/ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x01C00000>; ++ linux,cma-default; ++ }; ++ }; ++ ++ soc { ++ isp: isp { ++ //clk-pad = ; ++ clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ isp-flag = <0>; //disable DNR and ROT ++ isp-res = <1>; //max image size 2M ++ }; ++ Mstar-ehci-1 { ++ power-enable-pad = ; ++ }; ++ vip: vip { ++ CMDQ-mode = <0>; ++ }; ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++ vid1-gpio = ; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/infinity3-clks.dtsi b/arch/arm/boot/dts/infinity3-clks.dtsi +new file mode 100644 +index 00000000..a56653c6 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-clks.dtsi +@@ -0,0 +1,1519 @@ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++CLK_VOID: CLK_VOID { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_mpll_432m: CLK_mpll_432m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <432000000>; ++}; ++ ++CLK_upll_384m: CLK_upll_384m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <5>; ++ clock-mult = <4>; ++}; ++ ++CLK_upll_320m: CLK_upll_320m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_upll>; ++ clock-div = <3>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_288m: CLK_mpll_288m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <288000000>; ++}; ++ ++CLK_utmi_240m: CLK_utmi_240m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m: CLK_mpll_216m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <216000000>; ++}; ++ ++CLK_utmi_192m: CLK_utmi_192m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <5>; ++ clock-mult = <2>; ++}; ++ ++CLK_mpll_172m: CLK_mpll_172m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <172000000>; ++}; ++ ++CLK_utmi_160m: CLK_utmi_160m { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi>; ++ clock-div = <3>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m: CLK_mpll_123m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <123000000>; ++}; ++ ++CLK_mpll_86m: CLK_mpll_86m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <86000000>; ++}; ++ ++CLK_mpll_288m_div2: CLK_mpll_288m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div4: CLK_mpll_288m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_288m_div8: CLK_mpll_288m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_288m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div2: CLK_mpll_216m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div4: CLK_mpll_216m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_216m_div8: CLK_mpll_216m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_216m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_123m_div2: CLK_mpll_123m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_123m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div2: CLK_mpll_86m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div4: CLK_mpll_86m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_86m_div16: CLK_mpll_86m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_86m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_192m_div4: CLK_utmi_192m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_192m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div4: CLK_utmi_160m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div5: CLK_utmi_160m_div5 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <5>; ++ clock-mult = <1>; ++}; ++ ++CLK_utmi_160m_div8: CLK_utmi_160m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_utmi_160m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m: CLK_xtali_12m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <12000000>; ++}; ++ ++CLK_xtali_12m_div8: CLK_xtali_12m_div8 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <8>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div16: CLK_xtali_12m_div16 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <16>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div40: CLK_xtali_12m_div40 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <40>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div64: CLK_xtali_12m_div64 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <64>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div128: CLK_xtali_12m_div128 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <128>; ++ clock-mult = <1>; ++}; ++ ++CLK_RTC_CLK_32K: CLK_RTC_CLK_32K { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_pm_riu_w_clk_in: CLK_pm_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_in: CLK_riu_w_clk_in { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_top: CLK_riu_w_clk_top { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_sc_gp: CLK_riu_w_clk_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_vhe_gp: CLK_riu_w_clk_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_hemcu_gp: CLK_riu_w_clk_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mipi_if_gp: CLK_riu_w_clk_mipi_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_w_clk_mcu_if_gp: CLK_riu_w_clk_mcu_if_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_p: CLK_miu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp_p: CLK_miu_vhe_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp_p: CLK_miu_sc_gp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x_p: CLK_miu2x_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_p: CLK_mcu_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mcu_pm_p: CLK_mcu_pm_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mcu_pm>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_isp_p: CLK_isp_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_isp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk1_p: CLK_fclk1_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fclk2_p: CLK_fclk2_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_sdio_p: CLK_sdio_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_sdio>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_fcie_p: CLK_fcie_p { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fcie>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck_buf: CLK_tck_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_pad2isp_sr_pclk: CLK_pad2isp_sr_pclk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_ccir_in_clk: CLK_ccir_in_clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_eth_buf: CLK_eth_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_rmii_buf: CLK_rmii_buf { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_emac_testrx125_in_lan: CLK_emac_testrx125_in_lan { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <1>; ++}; ++ ++CLK_miu_ff: CLK_miu_ff { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_gp: CLK_miu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe_gp: CLK_miu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_dig: CLK_miu_dig { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_xd2miu: CLK_miu_xd2miu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_urdma: CLK_miu_urdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bdma: CLK_miu_bdma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_vhe: CLK_miu_vhe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_vhe_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfeh: CLK_miu_mfeh { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_mfe: CLK_miu_mfe { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe1: CLK_miu_jpe1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_jpe0: CLK_miu_jpe0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_bach: CLK_miu_bach { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_file: CLK_miu_file { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_uhc0: CLK_miu_uhc0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_emac: CLK_miu_emac { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_cmdq: CLK_miu_cmdq { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dnr: CLK_miu_isp_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_rot: CLK_miu_isp_rot { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_dma: CLK_miu_isp_dma { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_isp_sta: CLK_miu_isp_sta { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_gop: CLK_miu_gop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr: CLK_miu_sc_dnr { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_dnr_sad: CLK_miu_sc_dnr_sad { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc_crop: CLK_miu_sc_crop { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_frm: CLK_miu_sc1_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snp: CLK_miu_sc1_snp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_snpi: CLK_miu_sc1_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc1_dbg: CLK_miu_sc1_dbg { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_frm: CLK_miu_sc2_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc2_snpi: CLK_miu_sc2_snpi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sc3_frm: CLK_miu_sc3_frm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_fcie: CLK_miu_fcie { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_sdio: CLK_miu_sdio { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu_ive: CLK_miu_ive { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_sc_gp_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu: CLK_riu { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_top>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_nogating: CLK_riu_nogating { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_sc_gp: CLK_riu_sc_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_sc_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_vhe_gp: CLK_riu_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_vhe_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_hemcu_gp: CLK_riu_hemcu_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_hemcu_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mipi_gp: CLK_riu_mipi_gp { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mipi_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_mcu_if: CLK_riu_mcu_if { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_riu_w_clk_mcu_if_gp>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miu2x: CLK_miu2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_ddrpll_clk>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_axi2x: CLK_axi2x { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu2x_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_tck: CLK_tck { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_tck_buf>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_imi: CLK_imi { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_miu_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop0: CLK_gop0 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop1: CLK_gop1 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk1_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_gop2: CLK_gop2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_fclk2_p>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m: CLK_mpll_144m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <144000000>; ++}; ++ ++CLK_mpll_144m_div2: CLK_mpll_144m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_mpll_144m_div4: CLK_mpll_144m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_mpll_144m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_24m: CLK_xtali_24m { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++}; ++ ++CLK_xtali_12m_div2: CLK_xtali_12m_div2 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <2>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div4: CLK_xtali_12m_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_xtali_12m_div12: CLK_xtali_12m_div12 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_12m>; ++ clock-div = <12>; ++ clock-mult = <1>; ++}; ++ ++CLK_rtc_32k: CLK_rtc_32k { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++}; ++ ++CLK_rtc_32k_div4: CLK_rtc_32k_div4 { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_rtc_32k>; ++ clock-div = <4>; ++ clock-mult = <1>; ++}; ++ ++CLK_live_pm: CLK_live_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_xtali_24m>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_riu_pm: CLK_riu_pm { ++ #clock-cells = <0>; ++ compatible = "fixed-factor-clock"; ++ clocks = <&CLK_pm_riu_w_clk_in>; ++ clock-div = <1>; ++ clock-mult = <1>; ++}; ++ ++CLK_miupll_clk: CLK_miupll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_xtali_24m>; ++}; ++ ++CLK_ddrpll_clk: CLK_ddrpll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_ddr_syn>; ++}; ++ ++CLK_lpll_clk: CLK_lpll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_cpupll_clk: CLK_cpupll_clk { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_mpll_432m>; ++}; ++ ++CLK_utmi: CLK_utmi { ++ #clock-cells = <0>; ++// compatible = "mstar,complex-clock"; ++// clocks = <&CLK_upll>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_upll: CLK_upll { ++ #clock-cells = <0>; ++// compatible = "mstar,complex-clock"; ++// clocks = <&CLK_xtali_24m>; ++ compatible = "fixed-clock"; ++ clock-frequency = <480000000>; ++}; ++ ++CLK_fuart0_synth_out: CLK_fuart0_synth_out { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_fuart0_synth_in>; ++}; ++ ++CLK_csi2_mac_p: CLK_csi2_mac_p { ++ #clock-cells = <0>; ++ compatible = "mstar,complex-clock"; ++ clocks = <&CLK_csi_mac>; ++}; ++ ++CLK_miu: CLK_miu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_miupll_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MIU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ddr_syn: CLK_ddr_syn { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_DDR_SYN_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_DDR_SYN_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_miu_rec: CLK_miu_rec { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div64>,<&CLK_xtali_12m_div128>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIU_REC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIU_REC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_mcu: CLK_mcu { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_216m_div2>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MCU_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_MCU_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_riubrdg: CLK_riubrdg { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mcu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_RIUBRDG_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_RIUBRDG_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bdma: CLK_bdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BDMA_OFFSET ++}; ++ ++CLK_spi: CLK_spi { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SPI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SPI_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_SPI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_uart0: CLK_uart0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_UART0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_UART0_OFFSET ++}; ++ ++CLK_uart1: CLK_uart1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_UART1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_UART1_OFFSET ++}; ++ ++CLK_fuart0_synth_in: CLK_fuart0_synth_in { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_432m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_FUART0_SYNTH_IN_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_FUART0_SYNTH_IN_OFFSET ++}; ++ ++CLK_fuart: CLK_fuart { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_288m_div2>,<&CLK_xtali_12m>,<&CLK_fuart0_synth_out>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FUART_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FUART_OFFSET ++}; ++ ++CLK_mspi0: CLK_mspi0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MSPI0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MSPI0_OFFSET ++}; ++ ++CLK_mspi1: CLK_mspi1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MSPI1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MSPI1_OFFSET ++}; ++ ++CLK_miic0: CLK_miic0 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MIIC0_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_MIIC0_OFFSET ++}; ++ ++CLK_miic1: CLK_miic1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MIIC1_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_MIIC1_OFFSET ++}; ++ ++CLK_bist: CLK_bist { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_OFFSET ++}; ++ ++CLK_xtali: CLK_xtali { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_XTALI_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_XTALI_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_live: CLK_live { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_LIVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_LIVE_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_sr_mclk: CLK_sr_mclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m_div8>,<&CLK_mpll_86m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m_div16>,<&CLK_mpll_288m_div8>,<&CLK_mpll_216m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_123m_div2>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SR_MCLK_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_SR_MCLK_OFFSET ++}; ++ ++CLK_bist_pm: CLK_bist_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_PM_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_PM_OFFSET ++}; ++ ++CLK_bist_vhe_gp: CLK_bist_vhe_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_BIST_VHE_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_BIST_VHE_GP_OFFSET ++}; ++ ++CLK_vhe: CLK_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_utmi_240m>,<&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_utmi_160m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_VHE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_VHE_OFFSET ++}; ++ ++CLK_xtali_sc_gp: CLK_xtali_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <6>; //2+REG_CKG_XTALI_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <4>; //0+REG_CKG_XTALI_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_bist_sc_gp: CLK_bist_sc_gp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_BIST_SC_GP_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_BIST_SC_GP_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_ahb: CLK_emac_ahb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_emac_testrx125_in_lan>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_AHB_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_AHB_OFFSET ++}; ++ ++CLK_mfe: CLK_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_utmi_240m>,<&CLK_utmi_192m>,<&CLK_mpll_123m>,<&CLK_upll_384m>,<&CLK_upll_320m>,<&CLK_mpll_172m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MFE_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_MFE_OFFSET ++}; ++ ++CLK_jpe: CLK_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m>,<&CLK_mpll_216m>,<&CLK_mpll_216m_div4>,<&CLK_mpll_216m_div8>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_JPE_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_JPE_OFFSET ++}; ++ ++CLK_aesdma: CLK_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_172m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_AESDMA_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_AESDMA_OFFSET ++ glitch-shift = <4>; //4+REG_CKG_AESDMA_OFFSET ++}; ++ ++CLK_sdio: CLK_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_xtali_12m>,<&CLK_xtali_12m_div40>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SDIO_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_SDIO_OFFSET ++}; ++ ++CLK_fcie: CLK_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_288m_div4>,<&CLK_mpll_123m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>,<&CLK_mpll_86m>,<&CLK_utmi_192m_div4>,<&CLK_mpll_86m_div2>,<&CLK_utmi_160m_div4>,<&CLK_mpll_288m_div8>,<&CLK_utmi_160m_div5>,<&CLK_utmi_160m_div8>,<&CLK_mpll_86m_div16>,<&CLK_xtali_12m_div40>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCIE_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_FCIE_OFFSET ++}; ++ ++CLK_ecc: CLK_ecc { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_utmi_160m>,<&CLK_mpll_216m_div2>,<&CLK_mpll_216m_div4>,<&CLK_xtali_12m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ECC_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ECC_OFFSET ++}; ++ ++CLK_sr: CLK_sr { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_pad2isp_sr_pclk>,<&CLK_csi2_mac_p>,<&CLK_utmi_160m_div4>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_SR_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_SR_OFFSET ++}; ++ ++CLK_isp: CLK_isp { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_mpll_288m_div4>,<&CLK_mpll_216m_div4>,<&CLK_mpll_288m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_ISP_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_ISP_OFFSET ++}; ++ ++CLK_idclk: CLK_idclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_isp_p>,<&CLK_ccir_in_clk>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_IDCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_IDCLK_OFFSET ++}; ++ ++CLK_fclk1: CLK_fclk1 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK1_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK1_OFFSET ++}; ++ ++CLK_fclk2: CLK_fclk2 { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_172m>,<&CLK_mpll_86m>,<&CLK_mpll_216m>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_FCLK2_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_FCLK2_OFFSET ++}; ++ ++CLK_odclk: CLK_odclk { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_86m>,<&CLK_mpll_86m_div2>,<&CLK_mpll_86m_div4>,<&CLK_lpll_clk>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_ODCLK_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_ODCLK_OFFSET ++}; ++ ++CLK_ive: CLK_ive { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_IVE_OFFSET ++ mux-width = <2>; ++ gate-shift = <8>; //0+REG_CKG_IVE_OFFSET ++}; ++ ++CLK_nlm: CLK_nlm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_miu_p>,<&CLK_fclk1_p>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_NLM_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_NLM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_emac_tx: CLK_emac_tx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_TX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_TX_OFFSET ++}; ++ ++CLK_emac_rx: CLK_emac_rx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_eth_buf>,<&CLK_rmii_buf>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_EMAC_RX_OFFSET ++ mux-width = <1>; ++ gate-shift = <0>; //0+REG_CKG_EMAC_RX_OFFSET ++}; ++ ++CLK_emac_tx_ref: CLK_emac_tx_ref { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_TX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_TX_REF_OFFSET ++}; ++ ++CLK_emac_rx_ref: CLK_emac_rx_ref { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_rmii_buf>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_EMAC_RX_REF_OFFSET ++ mux-width = <1>; ++ gate-shift = <8>; //0+REG_CKG_EMAC_RX_REF_OFFSET ++}; ++ ++CLK_hemcu_216m: CLK_hemcu_216m { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>; ++ reg = ; ++ gate-shift = <0>; //0+REG_CKG_HEMCU_216M_OFFSET ++}; ++ ++CLK_csi_mac: CLK_csi_mac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_CSI_MAC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_CSI_MAC_OFFSET ++}; ++ ++CLK_mac_lptx: CLK_mac_lptx { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_mpll_288m>,<&CLK_mpll_172m>,<&CLK_mpll_123m>,<&CLK_mpll_86m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_MAC_LPTX_OFFSET ++ mux-width = <3>; ++ gate-shift = <8>; //0+REG_CKG_MAC_LPTX_OFFSET ++}; ++ ++CLK_ns: CLK_ns { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_mpll_216m>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_NS_OFFSET ++ mux-width = <2>; ++ gate-shift = <0>; //0+REG_CKG_NS_OFFSET ++}; ++ ++CLK_mcu_pm: CLK_mcu_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_mpll_216m>,<&CLK_utmi_192m>,<&CLK_mpll_172m>,<&CLK_utmi_160m>,<&CLK_mpll_288m_div2>,<&CLK_mpll_123m>,<&CLK_mpll_216m_div2>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_24m>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_MCU_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <0>; //0+REG_CKG_MCU_PM_OFFSET ++ glitch-shift = <7>; //7+REG_CKG_MCU_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_spi_pm: CLK_spi_pm { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_rtc_32k>,<&CLK_mpll_216m_div8>,<&CLK_mpll_144m_div4>,<&CLK_mpll_86m_div2>,<&CLK_mpll_216m_div4>,<&CLK_mpll_144m_div2>,<&CLK_mpll_86m>,<&CLK_mpll_216m_div2>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>,<&CLK_xtali_12m>,<&CLK_xtali_24m>; ++ reg = ; ++ mux-shift = <10>; //2+REG_CKG_SPI_PM_OFFSET ++ mux-width = <4>; ++ gate-shift = <8>; //0+REG_CKG_SPI_PM_OFFSET ++ glitch-shift = <14>; //6+REG_CKG_SPI_PM_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_pm_sleep: CLK_pm_sleep { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <12>; //2+REG_CKG_PM_SLEEP_OFFSET ++ mux-width = <3>; ++}; ++ ++CLK_sar: CLK_sar { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_SAR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_SAR_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_rtc: CLK_rtc { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>,<&CLK_VOID>; ++ reg = ; ++ mux-shift = <2>; //2+REG_CKG_RTC_OFFSET ++ mux-width = <3>; ++ gate-shift = <0>; //0+REG_CKG_RTC_OFFSET ++ auto-enable = <1>; ++}; ++ ++CLK_ir: CLK_ir { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ clocks = <&CLK_xtali_12m>,<&CLK_rtc_32k>,<&CLK_xtali_12m_div8>,<&CLK_xtali_12m_div12>,<&CLK_rtc_32k_div4>,<&CLK_xtali_12m_div16>,<&CLK_xtali_12m_div2>,<&CLK_xtali_12m_div4>; ++ reg = ; ++ mux-shift = <7>; //2+REG_CKG_IR_OFFSET ++ mux-width = <3>; ++ gate-shift = <5>; //0+REG_CKG_IR_OFFSET ++ auto-enable = <1>; ++}; ++ ++usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&CLK_RTC_CLK_32K>, <&CLK_VOID>, <&CLK_aesdma>, <&CLK_axi2x>, <&CLK_bdma>, <&CLK_bist>, <&CLK_bist_pm>, <&CLK_bist_sc_gp>, <&CLK_bist_vhe_gp>, <&CLK_ccir_in_clk>, <&CLK_cpupll_clk>, <&CLK_csi2_mac_p>, <&CLK_csi_mac>, <&CLK_ddr_syn>, <&CLK_ddrpll_clk>, <&CLK_ecc>, <&CLK_emac_ahb>, <&CLK_emac_rx>, <&CLK_emac_rx_ref>, <&CLK_emac_testrx125_in_lan>, <&CLK_emac_tx>, <&CLK_emac_tx_ref>, <&CLK_eth_buf>, <&CLK_fcie>, <&CLK_fcie_p>, <&CLK_fclk1>, <&CLK_fclk1_p>, <&CLK_fclk2>, <&CLK_fclk2_p>, <&CLK_fuart>, <&CLK_fuart0_synth_in>, <&CLK_fuart0_synth_out>, <&CLK_gop0>, <&CLK_gop1>, <&CLK_gop2>, <&CLK_hemcu_216m>, <&CLK_idclk>, <&CLK_imi>, <&CLK_ir>, <&CLK_isp>, <&CLK_isp_p>, <&CLK_ive>, <&CLK_jpe>, <&CLK_live>, <&CLK_live_pm>, <&CLK_lpll_clk>, <&CLK_mac_lptx>, <&CLK_mcu>, <&CLK_mcu_p>, <&CLK_mcu_pm>, <&CLK_mcu_pm_p>, <&CLK_mfe>, <&CLK_miic0>, <&CLK_miic1>, <&CLK_miu>, <&CLK_miu2x>, <&CLK_miu2x_p>, <&CLK_miu_bach>, <&CLK_miu_bdma>, <&CLK_miu_cmdq>, <&CLK_miu_dig>, <&CLK_miu_emac>, <&CLK_miu_fcie>, <&CLK_miu_ff>, <&CLK_miu_file>, <&CLK_miu_gop>, <&CLK_miu_isp_dma>, <&CLK_miu_isp_dnr>, <&CLK_miu_isp_rot>, <&CLK_miu_isp_sta>, <&CLK_miu_ive>, <&CLK_miu_jpe0>, <&CLK_miu_jpe1>, <&CLK_miu_mfe>, <&CLK_miu_mfeh>, <&CLK_miu_p>, <&CLK_miu_rec>, <&CLK_miu_sc1_dbg>, <&CLK_miu_sc1_frm>, <&CLK_miu_sc1_snp>, <&CLK_miu_sc1_snpi>, <&CLK_miu_sc2_frm>, <&CLK_miu_sc2_snpi>, <&CLK_miu_sc3_frm>, <&CLK_miu_sc_crop>, <&CLK_miu_sc_dnr>, <&CLK_miu_sc_dnr_sad>, <&CLK_miu_sc_gp>, <&CLK_miu_sc_gp_p>, <&CLK_miu_sdio>, <&CLK_miu_uhc0>, <&CLK_miu_urdma>, <&CLK_miu_vhe>, <&CLK_miu_vhe_gp>, <&CLK_miu_vhe_gp_p>, <&CLK_miu_xd2miu>, <&CLK_miupll_clk>, <&CLK_mpll_123m>, <&CLK_mpll_123m_div2>, <&CLK_mpll_144m>, <&CLK_mpll_144m_div2>, <&CLK_mpll_144m_div4>, <&CLK_mpll_172m>, <&CLK_mpll_216m>, <&CLK_mpll_216m_div2>, <&CLK_mpll_216m_div4>, <&CLK_mpll_216m_div8>, <&CLK_mpll_288m>, <&CLK_mpll_288m_div2>, <&CLK_mpll_288m_div4>, <&CLK_mpll_288m_div8>, <&CLK_mpll_432m>, <&CLK_mpll_86m>, <&CLK_mpll_86m_div16>, <&CLK_mpll_86m_div2>, <&CLK_mpll_86m_div4>, <&CLK_mspi0>, <&CLK_mspi1>, <&CLK_nlm>, <&CLK_ns>, <&CLK_odclk>, <&CLK_pad2isp_sr_pclk>, <&CLK_pm_riu_w_clk_in>, <&CLK_pm_sleep>, <&CLK_riu>, <&CLK_riu_hemcu_gp>, <&CLK_riu_mcu_if>, <&CLK_riu_mipi_gp>, <&CLK_riu_nogating>, <&CLK_riu_pm>, <&CLK_riu_sc_gp>, <&CLK_riu_vhe_gp>, <&CLK_riu_w_clk_hemcu_gp>, <&CLK_riu_w_clk_in>, <&CLK_riu_w_clk_mcu_if_gp>, <&CLK_riu_w_clk_mipi_if_gp>, <&CLK_riu_w_clk_sc_gp>, <&CLK_riu_w_clk_top>, <&CLK_riu_w_clk_vhe_gp>, <&CLK_riubrdg>, <&CLK_rmii_buf>, <&CLK_rtc>, <&CLK_rtc_32k>, <&CLK_rtc_32k_div4>, <&CLK_sar>, <&CLK_sdio>, <&CLK_sdio_p>, <&CLK_spi>, <&CLK_spi_pm>, <&CLK_sr>, <&CLK_sr_mclk>, <&CLK_tck>, <&CLK_tck_buf>, <&CLK_uart0>, <&CLK_uart1>, <&CLK_upll>, <&CLK_upll_320m>, <&CLK_upll_384m>, <&CLK_utmi>, <&CLK_utmi_160m>, <&CLK_utmi_160m_div4>, <&CLK_utmi_160m_div5>, <&CLK_utmi_160m_div8>, <&CLK_utmi_192m>, <&CLK_utmi_192m_div4>, <&CLK_utmi_240m>, <&CLK_vhe>, <&CLK_xtali>, <&CLK_xtali_12m>, <&CLK_xtali_12m_div12>, <&CLK_xtali_12m_div128>, <&CLK_xtali_12m_div16>, <&CLK_xtali_12m_div2>, <&CLK_xtali_12m_div4>, <&CLK_xtali_12m_div40>, <&CLK_xtali_12m_div64>, <&CLK_xtali_12m_div8>, <&CLK_xtali_24m>, <&CLK_xtali_sc_gp>; ++ clock-count = <179>; ++}; ++ +diff --git a/arch/arm/boot/dts/infinity3-fpga.dts b/arch/arm/boot/dts/infinity3-fpga.dts +new file mode 100644 +index 00000000..fd77cd11 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpga.dts +@@ -0,0 +1,101 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++ /* ++ * Memory Layout ++ * 0x20000000-0x24000000 64M Kernel ++ * 0x24000000-0x24800000 8M system ++ * 0x24800000-0x24900000 1M data ++ * 0x24900000-0x25000000 7M temp0 ++ * 0x25000000-0x28000000 48M temp1 ++ */ ++/dts-v1/; ++#include "infinity3-fpga.dtsi" ++ ++/ { ++ model = "INFINITY3 FPGA"; ++ compatible = "mstar,infinity3"; ++ ++ memory { ++ reg = <0x20000000 0x05000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x23000000>; ++ linux,initrd-end = <0x23040000>; ++ }; ++ ++ sysp:rammtd@0 { ++ compatible = "mtd-ram"; ++ reg= <0x27000000 0x00400000>; ++ bank-width = <1>; ++ linux,mtd-name = "SYSTEM"; ++ }; ++ ++ /* Size of this partition must be identical to the size of data.jffs2 due to JFFS2 limitation */ ++ datap:rammtd@1 { ++ compatible = "mtd-ram"; ++ reg= <0x27400000 0x00100000>; ++ bank-width = <1>; ++ linux,mtd-name = "DATA"; ++ erase-size = <0x10000>; ++ }; ++ ++ extp:rammtd@2 { ++ compatible = "mtd-ram"; ++ reg= <0x27600000 0x00300000>; ++ bank-width = <1>; ++ linux,mtd-name = "EXT"; ++ erase-size = <0x10000>; ++ }; ++ ++ temp0:rammtd@3 { ++ compatible = "mtd-ram"; ++ reg= <0x27900000 0x00700000>; ++ bank-width = <1>; ++ linux,mtd-name = "temp0"; ++ }; ++ ++ temp1:rammtd@4 { ++ compatible = "mtd-ram"; ++ reg= <0x25000000 0x01000000>; ++ bank-width = <1>; ++ linux,mtd-name = "temp1"; ++ }; ++ ++ temp2:rammtd@5 { ++ compatible = "mtd-ram"; ++ reg= <0x26000000 0x01000000>; ++ bank-width = <1>; ++ linux,mtd-name = "temp2"; ++ }; ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x02000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity3-fpga.dtsi b/arch/arm/boot/dts/infinity3-fpga.dtsi +new file mode 100644 +index 00000000..540e057f +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpga.dtsi +@@ -0,0 +1,298 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/mstar/include/infinity3/irqs.h> ++#include <../../../../drivers/mstar/include/infinity3/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ reg = <0x0>; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <54000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0xFFFFFFFF>; ++ ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_pmsleep_intr: interrupt-controller@0 { ++ compatible = "mstar,pmsleep-intr"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <54000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "mstar,mfe"; ++ reg = <0x1F264800 0x400>; ++ interrupts=; ++ clocks = <&xtal>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "mstar,vhe"; ++ reg = <0x1F265200 0x600>,<0x1F265000 0x200>; ++ interrupts=; ++ clocks = <&xtal>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "mstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "mstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "mstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "mstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "mstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "mstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "mstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "mstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "mstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts= ; ++ status = "ok"; ++ clocks = <&xtal>; ++ }; ++ ++ ++ ++ emac { ++ compatible = "mstar-emac"; ++ interrupts = , ; ++ status = "ok"; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "disabled"; ++ }; ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ }; ++ ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts= ; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "mstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "mstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ sound { ++ compatible = "mstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ }; ++ ++ gop{ ++ compatible = "mstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "mstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "mstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ rtc { ++ compatible = "mstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ ++ ++ ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/mstar/include/infinity3/reg_clks.h> ++ #include "infinity3-clks.dtsi" ++ #include "infinity-gates.dtsi" ++}; ++ +diff --git a/arch/arm/boot/dts/infinity3-fpgaxl.dts b/arch/arm/boot/dts/infinity3-fpgaxl.dts +new file mode 100644 +index 00000000..1efa0be6 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpgaxl.dts +@@ -0,0 +1,48 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/dts-v1/; ++#include "infinity3-fpgaxl.dtsi" ++ ++/ { ++ model = "INFINITY3 FPGA"; ++ compatible = "mstar,infinity3"; ++ memory { ++ reg = <0x20000000 0x08000000>; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyS0,38400n8r androidboot.console=ttyS0 root=/dev/ram rootwait"; ++ linux,initrd-start = <0x20FE0000>; ++ linux,initrd-end = <0x21000000>; ++ }; ++ ++ ++/*!!IMPORTANT!! The reserved memory must be 1MB aligned*/ ++ reserved-memory { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ cma0 { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x03000000>; ++ alignment = <0x1000>; ++ linux,cma-default; ++ }; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/infinity3-fpgaxl.dtsi b/arch/arm/boot/dts/infinity3-fpgaxl.dtsi +new file mode 100644 +index 00000000..3b2f3913 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-fpgaxl.dtsi +@@ -0,0 +1,428 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/mstar/include/infinity3/irqs.h> ++#include <../../../../drivers/mstar/include/infinity3/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&xtal>; ++ }; ++ }; ++ ++ xtal: oscillator { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <27000000>; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_pmsleep_intr: interrupt-controller@0 { ++ compatible = "mstar,pmsleep-intr"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <27000000>; /* arch_timer must use clock-frequency*/ ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "mstar,mfe"; ++ reg = <0x1F264800 0x200>; ++ interrupts=; ++ clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "mstar,vhe"; ++ reg = <0x1F265200 0x200>,<0x1F265000 0x100>; ++ interrupts=; ++ clocks = <&CLK_vhe>,<&GATE_MCM_vhe>, <&GATE_SRAM_vhe>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "mstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "mstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "mstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "mstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "mstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "mstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "mstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "mstar,vip"; ++ status = "ok"; ++ ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "mstar,pnl"; ++ status = "ok"; ++ ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart@1F221000 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ status = "ok"; ++ }; ++ uart1: uart@1F221200 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ status = "disabled"; ++ }; ++ fuart: uart@1F220400 { ++ compatible = "mstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&xtal>; ++ dma = <1>; ++ status = "disabled"; ++ }; ++ ++ emac { ++ compatible = "mstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>,<&GATE_MCM_emac>, <&GATE_SRAM_emac>; ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ nandflash { ++ compatible = "ms-nand"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++ status = "disabled"; ++ }; ++ ++ Mstar-ehci-1 { ++ compatible = "Mstar-ehci-1"; ++ clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ }; ++ spi: spi { ++ compatible = "mstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ status = "disabled"; ++ }; ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "mstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&xtal>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ i2c0: i2c@0{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++ i2c-speed = <2>;//0~6 ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@1{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ i2c-speed = <2>;//0~6 ++ status = "disabled"; ++ 24c512@54 { ++ compatible = "mstar,24c512"; ++ reg = <0x54>; ++ }; ++ }; ++ ++ gpio:gpio{ ++ compatible = "mstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "mstar,infinity-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~76 ++ capture-volume-level=<64>; ++ micin-gain-level=<0>; //0~5 ++ linein-gain-level=<1>;//0~6 ++ lineout-gain-level=<1>;//0~2 ++ clocks = <&CLK_utmi>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>; ++ }; ++ ++ sdmmc { ++ compatible = "mstar,sdmmc"; ++ interrupts=, ++ , ++ , ++ ; ++ //,,.... fice1->fice2->fice3 setting ++ clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>; ++ status = "disabled"; ++ }; ++ ++ aesdma { ++ compatible = "mstar,infinity-aes"; ++ clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; ++ }; ++ ++ gop{ ++ compatible = "mstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "mstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "mstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ rtc { ++ compatible = "mstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&xtal>; ++ }; ++ ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++ status = "disabled"; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "mstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ status = "disabled"; ++ }; ++ ++ sar: sar { ++ compatible = "mstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ status = "disabled"; ++ }; ++ ++ ircut { ++ compatible = "mstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ pwm { ++ compatible = "mstar,infinity-pwm"; ++ status = "disabled"; ++ }; ++ ++ gpioi2c { ++ compatible = "mstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ status = "disabled"; ++ }; ++ ++ pm { ++ compatible = "mstar,infinity-pm"; ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ detect-gpio = ; ++ status = "disabled"; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/mstar/include/infinity3/reg_clks.h> ++ #include "infinity3-clks.dtsi" ++ #include "infinity-gates.dtsi" ++}; +diff --git a/arch/arm/boot/dts/infinity3-gates.dtsi b/arch/arm/boot/dts/infinity3-gates.dtsi +new file mode 100644 +index 00000000..8aadcbea +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3-gates.dtsi +@@ -0,0 +1,158 @@ ++GATE_MCM_vhe: GATE_MCM_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_mfe: GATE_MCM_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_jpe: GATE_MCM_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_aesdma: GATE_MCM_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_emac: GATE_MCM_emac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_gop: GATE_MCM_gop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_MCM_bach: GATE_MCM_bach { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_usb: GATE_MCM_usb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++ ++GATE_MCM_fcie: GATE_MCM_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_MCM_sdio: GATE_MCM_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++/* ++GATE_MCM_urdma: GATE_MCM_urdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++*/ ++ ++GATE_SRAM_vhe: GATE_SRAM_vhe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_mfe: GATE_SRAM_mfe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <9>; ++}; ++ ++GATE_SRAM_jpe: GATE_SRAM_jpe { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <8>; ++}; ++ ++GATE_SRAM_aesdma: GATE_SRAM_aesdma { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <1>; ++}; ++ ++GATE_SRAM_emac: GATE_SRAM_emac { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <3>; ++}; ++ ++GATE_SRAM_gop: GATE_SRAM_gop { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <5>; ++}; ++ ++GATE_SRAM_bach: GATE_SRAM_bach { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <0>; ++}; ++ ++GATE_SRAM_usb: GATE_SRAM_usb { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <11>; ++}; ++ ++ ++GATE_SRAM_fcie: GATE_SRAM_fcie { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <4>; ++}; ++ ++GATE_SRAM_sdio: GATE_SRAM_sdio { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <10>; ++}; ++ ++ ++GATE_SRAM_mailbox: GATE_SRAM_mailbox { ++ #clock-cells = <0>; ++ compatible = "mstar,composite-clock"; ++ reg = <0x1F200804 0x4>; ++ gate-shift = <2>; ++}; +diff --git a/arch/arm/boot/dts/infinity3.dtsi b/arch/arm/boot/dts/infinity3.dtsi +new file mode 100644 +index 00000000..fbd5c7a9 +--- /dev/null ++++ b/arch/arm/boot/dts/infinity3.dtsi +@@ -0,0 +1,491 @@ ++/* ++ * Copyright (c) 2014 MundoReader S.L. ++ * Author: Matthias Brugger ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <../../../../drivers/mstar/include/infinity3/irqs.h> ++#include <../../../../drivers/mstar/include/infinity3/gpio.h> ++#include ++#include ++#include "skeleton.dtsi" ++ ++ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a7"; ++ clocks = <&CLK_cpupll_clk>; ++ }; ++ }; ++ ++ aliases { ++ console = &uart0; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &fuart; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ interrupt-parent = <&gic>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ gic: interrupt-controller@16000000 { ++ compatible = "arm,cortex-a7-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ interrupt-controller; ++ reg = <0x16001000 0x1000>, ++ <0x16002000 0x1000>; ++ }; ++ ++ ms_pmsleep_intr: interrupt-controller@0 { ++ compatible = "mstar,pmsleep-intr"; ++ #interrupt-cells = <1>; ++ interrupt-parent=<&gic>; ++ interrupt-controller; ++ }; ++ ++ ++ arch_timer { ++ compatible = "arm,cortex-a7-timer", "arm,armv7-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <6000000>; ++ }; ++ ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ clks: clocks{ ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ }; ++ ++/* ++ timer_clockevent: timer@1F006040 { ++ compatible = "mstar,piu-clockevent"; ++ reg = <0x1F006040 0x100>; ++ interrupts=; ++ clocks = <&CLK_xtali_12m>; ++ }; ++*/ ++ mfe: mfe { ++ compatible = "mstar,mfe"; ++ reg = <0x1F264800 0x200>; ++ interrupts=; ++ clocks = <&CLK_mfe>,<&GATE_MCM_mfe>, <&GATE_SRAM_mfe>; ++ clock-names = "CKG_mfe"; ++ status = "ok"; ++ }; ++ ++ vhe: vhe { ++ compatible = "mstar,vhe"; ++ reg = <0x1F265200 0x200>,<0x1F265000 0x100>; ++ interrupts=; ++ clocks = <&CLK_vhe>,<&GATE_MCM_vhe>, <&GATE_SRAM_vhe>; ++ clock-names = "CKG_vhe"; ++ status = "ok"; ++ }; ++ ++ hvsp1: hvsp1 { ++ compatible = "mstar,hvsp1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ DigitalZoom-Dropmode = <1>; ++ interrupts = , ; ++ }; ++ ++ hvsp2: hvsp2 { ++ compatible = "mstar,hvsp2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ hvsp3: hvsp3 { ++ compatible = "mstar,hvsp3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,hvsp0,sc0,dnr,ldc ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = , ; ++ }; ++ ++ scldma1: scldma1 { ++ compatible = "mstar,scldma1"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma2: scldma2 { ++ compatible = "mstar,scldma2"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma3: scldma3 { ++ compatible = "mstar,scldma3"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ scldma4: scldma4 { ++ compatible = "mstar,scldma4"; ++ //reg = <0x1F000000 0x100>; ++ //clk,chiptop,scldma ++ clocks = <&CLK_idclk>,<&CLK_fclk1>,<&CLK_fclk2>,<&CLK_odclk>; ++ clock-names = "CLK_idclk","CLK_fclk1","CLK_fclk2","CLK_odclk"; ++ status = "ok"; ++ interrupts = ; ++ }; ++ ++ vip: vip { ++ compatible = "mstar,vip"; ++ status = "ok"; ++ CMDQ-mode = <1>; ++ //reg = <0x1F224000 0x200>; ++ }; ++ ++ pnl: pnl { ++ compatible = "mstar,pnl"; ++ status = "ok"; ++ ttl-mode = <1>; ++ jtag-mode = <0>; ++ //Reg = <0x1F224000 0x200>; ++ }; ++ ++ uart0: uart0@1F221000 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart0>; ++ status = "ok"; ++ }; ++ uart1: uart1@1F221200 { ++ compatible = "mstar,uart"; ++ reg = <0x1F221200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_uart1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ fuart: uart2@1F220400 { ++ compatible = "mstar,uart"; ++ reg = <0x1F220400 0x100>, <0x1F220600 0x100>; ++ interrupts = , ; ++ clocks = <&CLK_fuart>; ++ dma = <1>; ++ pad = ; ++ //pad = ; ++ //pad = ; ++ status = "ok"; ++ }; ++ ++ emac { ++ compatible = "mstar-emac"; ++ interrupts = , ; ++ clocks = <&CLK_emac_ahb>,<&CLK_emac_tx>,<&CLK_emac_rx>,<&GATE_MCM_emac>, <&GATE_SRAM_emac>; ++ //led-orange = ; //software toggle GPIO LED For QFN ++ //led-green = ; //software toggle GPIO LED For QFN ++ }; ++ ++ flashisp { ++ compatible = "mtd-flashisp"; ++ clocks = <&CLK_bdma>; ++ quadread = <0>; ++ status = "ok"; ++ }; ++ ++ nandflash { ++ compatible = "ms-nand"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ emmc { ++ compatible = "mstar_mci"; ++ clocks =<&CLK_fcie>, <&CLK_ecc>, <&GATE_MCM_fcie>, <&GATE_SRAM_fcie>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ ++ spinandflash { ++ compatible = "ms-spinand"; ++ clocks =<&CLK_bdma>; ++ status = "ok"; ++ }; ++ ++ Mstar-ehci-1 { ++ compatible = "Mstar-ehci-1"; ++ clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ dpdm_swap=<0>; ++ power-enable-pad = ; //PAD_SPI0_CK ++ status = "ok"; ++ }; ++ ++ Mstar-ehci-2 { ++ compatible = "Mstar-ehci-2"; ++ clocks = <&CLK_utmi>, <&GATE_MCM_usb>, <&GATE_SRAM_usb>; ++ interrupts = ; ++ dpdm_swap=<0>; ++ status = "ok"; ++ }; ++ ++ Mstar-udc { ++ compatible = "Mstar-udc"; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ isp: isp { ++ compatible = "isp"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1302>,<0x1303>,<0x1304>,<0x1305>,<0x1306>,<0x1307>,<0x1308>,<0x1309>,<0x130A>,<0x130B>; ++ interrupts = ; ++ clocks = <&CLK_isp>,<&CLK_sr_mclk>,<&CLK_sr>,<&CLK_csi_mac>; ++ status = "ok"; ++ clk-pad = ; ++ //clk-pad = ; //be compatible with the previous QFN, so it must reserved 4 pins for SPI0 pads ++ //isp-flag = <0>; ++ }; ++ spi: spi { ++ compatible = "mstar_spi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1110>,<0x1111>,<0x1038>,<0x101E>; ++ interrupts = ,; ++ spi0_mode = <1>; ++ spi1_mode = <1>; ++ status = "disabled"; ++ }; ++ spidev: spidev { ++ compatible = "spidev"; ++ }; ++ csi: csi { ++ compatible = "csi"; ++ io_phy_addr = <0x1f000000>; ++ banks = <0x1204>; ++ interrupts = ; ++ status = "ok"; ++ }; ++ ++ jpe0: jpe@0x1F264000 { ++ compatible = "mstar,cedric-jpe"; ++ reg = <0x1F264000 0x100>; ++ interrupts = ; ++ clocks = <&CLK_jpe>,<&GATE_MCM_jpe>, <&GATE_SRAM_jpe>; ++ clock-names = "CKG_jpe"; ++ clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ status = "ok"; ++ }; ++ ++ ive0: ive@0x1F2A4000 { ++ compatible = "mstar,infinity3-ive"; ++ reg = <0x1F2A4000 0x100>,<0x1F2A4200 0x100>; ++ interrupts = ; ++ clocks = <&CLK_ive>,<&CLK_miu_ive>; ++ status = "ok"; ++ }; ++ ++ i2c0@0{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223000 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic0>; ++ i2c-group = <0>; ++// status = "disable"; ++ /* ++ * padmux: 1 -> PAD_I2C0_SCL, PAD_I2C0_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ }; ++ ++ i2c1@1{ ++ compatible = "mstar,i2c"; ++ reg = <0x1F223200 0x200>,<0x1F203c00 0x200>,<0x1F207000 0x200>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&CLK_miic1>; ++ i2c-group = <1>; ++ /* ++ * padmux: 1 -> PAD_I2C1_SCL, PAD_I2C1_SDA ++ * 2 -> PAD_PWM0, PAD_PWM1 ++ * 3 -> PAD_SR_IO00, PAD_SR_IO01 ++ */ ++ i2c-padmux = <1>; ++ ++// 24c512@54 { ++// compatible = "mstar,24c512"; ++// reg = <0x54>; ++// }; ++ }; ++ ++ ++ gpio:gpio{ ++ compatible = "mstar,gpio"; ++ }; ++ ++ sound { ++ compatible = "mstar,infinity3-audio"; ++// reg = <0x1F000000 0x1000000>; ++ interrupts=; ++ playback-volume-level=<64>; //0~94 ++ capture-volume-level=<64>; ++ // micin-pregain-level=<1>; //0~3 ++ micin-pregain-level=<0>; //0~3 ++ micin-gain-level=<3>; //0~7 ++ linein-gain-level=<2>; //0~7 ++ amp-gpio = ; ++ clocks = <&CLK_upll_384m>, <&GATE_MCM_bach>, <&GATE_SRAM_bach>; ++ // playback-dma-buffer=<98304>; //512(ms)*48(kHz)*2(ch)*2(16bits) ++ // capture-dma-buffer=<81920>; //640(ms)*32(kHz)*2(ch)*2(16bits) ++ }; ++ ++ sdmmc { ++ compatible = "mstar,sdmmc"; ++ ++ slotnum = <1>; ++ revcdz = <0>; ++ ++ slot-ip-orders = <0>,<1>,<2>; ++ slot-pad-orders = <0>,<1>,<2>; ++ slot-max-clks = <48000000>,<48000000>,<48000000>; ++ slot-intcdzs = <1>,<1>,<1>; ++ slot-fakecdzs = <0>,<0>,<0>; ++ slot-pwr-gpios = <19>,<0>,<0>; ++ ++ clocks = <&CLK_sdio>,<&GATE_MCM_sdio>,<&GATE_SRAM_sdio>,<&CLK_fcie>,<&GATE_MCM_fcie>,<&GATE_SRAM_fcie>; ++ ++ }; ++ ++ aesdma { ++ compatible = "mstar,infinity-aes"; ++ clocks = <&CLK_aesdma>,<&GATE_MCM_aesdma>, <&GATE_SRAM_aesdma>; ++ }; ++ ++ gop{ ++ compatible = "mstar,infinity-gop"; ++ clocks = <&CLK_gop0>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop1{ ++ compatible = "mstar,infinity-gop1"; ++ clocks = <&CLK_gop1>,<&CLK_fclk1>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ gop2{ ++ compatible = "mstar,infinity-gop2"; ++ clocks = <&CLK_gop2>,<&CLK_fclk2>,<&GATE_MCM_gop>, <&GATE_SRAM_gop>; ++ status = "ok"; ++ }; ++ ++ rtc { ++ compatible = "mstar,infinity-rtc"; ++ reg = <0x1F002400 0x40>; ++ interrupts=; ++ clocks = <&CLK_rtc>; ++ }; ++ ++ cpufreq { ++ compatible = "mstar,infinity-cpufreq"; ++// vid0-gpio = ; ++ vid1-gpio = ; ++ }; ++ ++ watchdog: watchdog { ++ compatible = "mstar,infinity-wdt"; ++ reg = <0x1F006000 0x40>; ++ }; ++ ++ sar: sar { ++ compatible = "mstar,infinity-sar"; ++ reg = <0x1F002800 0x200>; ++ }; ++ ++ ircut { ++ compatible = "mstar,infinity-ircut"; ++ ircut-gpio-num = ;///PM_GPIO_IRIN ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ }; ++ ++ pwm { ++ compatible = "mstar,infinity3-pwm"; ++ reg = <0x1F003400 0x400>; ++ clocks = <&CLK_xtali_12m>; ++ npwm = <8>; ++ pad-ctrl = ; ++ }; ++ ++ gpioi2c { ++ compatible = "mstar,infinity-gpioi2c"; ++ sda-gpio = ; ++ scl-gpio = ; ++ }; ++ ++ pm { ++ compatible = "mstar,infinity-pm"; ++ interrupt-parent = <&ms_pmsleep_intr>; ++ interrupts = ; ++ detect-gpio = ; ++ }; ++ }; ++}; ++ ++&clks { ++ #include <../../../../drivers/mstar/include/infinity3/reg_clks.h> ++ #include "infinity3-clks.dtsi" ++ #include "infinity3-gates.dtsi" ++}; ++ +diff --git a/arch/arm/configs/cedric_00_defconfig b/arch/arm/configs/cedric_00_defconfig +new file mode 100644 +index 00000000..bc8e2d31 +--- /dev/null ++++ b/arch/arm/configs/cedric_00_defconfig +@@ -0,0 +1,1396 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=16 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++ ++# ++# Altera FPGA firmware download module ++# ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++# CONFIG_UNIX98_PTYS is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++# CONFIG_I2C is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_ISP is not set ++# CONFIG_MS_SOUND is not set ++# CONFIG_MS_USB_CEDRIC is not set ++# CONFIG_MS_SCALER is not set ++# CONFIG_MS_DIP is not set ++# CONFIG_MS_MFE is not set ++# CONFIG_MS_FB is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++# CONFIG_NETWORK_FILESYSTEMS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_0_defconfig b/arch/arm/configs/cedric_0_defconfig +new file mode 100644 +index 00000000..aeaccb3b +--- /dev/null ++++ b/arch/arm/configs/cedric_0_defconfig +@@ -0,0 +1,1613 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_DMA_CMA is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_ISP is not set ++# CONFIG_MS_SOUND is not set ++# CONFIG_MS_USB_CEDRIC is not set ++# CONFIG_MS_USB_CHICAGO is not set ++# CONFIG_MS_SCALER is not set ++# CONFIG_MS_DIP is not set ++# CONFIG_MS_MFE is not set ++# CONFIG_MS_FB is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_1_defconfig b/arch/arm/configs/cedric_1_defconfig +new file mode 100644 +index 00000000..7844a021 +--- /dev/null ++++ b/arch/arm/configs/cedric_1_defconfig +@@ -0,0 +1,1757 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_DMA_CMA is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_HUION is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_ISP is not set ++# CONFIG_MS_SOUND is not set ++CONFIG_MS_USB_CEDRIC=y ++# CONFIG_MS_USB_CHICAGO is not set ++# CONFIG_MS_SCALER is not set ++# CONFIG_MS_DIP is not set ++# CONFIG_MS_MFE is not set ++# CONFIG_MS_FB is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_2_defconfig b/arch/arm/configs/cedric_2_defconfig +new file mode 100644 +index 00000000..8259f9e5 +--- /dev/null ++++ b/arch/arm/configs/cedric_2_defconfig +@@ -0,0 +1,1869 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_DMA_CMA is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_PCM_XRUN_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_HUION is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++# CONFIG_MS_SOUND_CHICAGO is not set ++CONFIG_MS_USB_CEDRIC=y ++# CONFIG_MS_USB_CHICAGO is not set ++# CONFIG_MS_SCALER is not set ++# CONFIG_MS_DIP is not set ++# CONFIG_MS_MFE is not set ++# CONFIG_MS_FB is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_3_defconfig b/arch/arm/configs/cedric_3_defconfig +new file mode 100644 +index 00000000..d3b400ea +--- /dev/null ++++ b/arch/arm/configs/cedric_3_defconfig +@@ -0,0 +1,1871 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_DMA_CMA is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_PCM_XRUN_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_HUION is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++# CONFIG_MS_SOUND_CHICAGO is not set ++CONFIG_MS_USB_CEDRIC=y ++# CONFIG_MS_USB_CHICAGO is not set ++CONFIG_MS_SCALER=y ++# CONFIG_MS_CLONE_SCREEN is not set ++CONFIG_MS_SCALER_BOOT_PNL=y ++CONFIG_MS_DIP=y ++# CONFIG_MS_MFE is not set ++# CONFIG_MS_FB is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_4_defconfig b/arch/arm/configs/cedric_4_defconfig +new file mode 100644 +index 00000000..abd09a15 +--- /dev/null ++++ b/arch/arm/configs/cedric_4_defconfig +@@ -0,0 +1,1871 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_DMA_CMA is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_PCM_XRUN_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_HUION is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++# CONFIG_MS_SOUND_CHICAGO is not set ++CONFIG_MS_USB_CEDRIC=y ++# CONFIG_MS_USB_CHICAGO is not set ++CONFIG_MS_SCALER=y ++# CONFIG_MS_CLONE_SCREEN is not set ++CONFIG_MS_SCALER_BOOT_PNL=y ++CONFIG_MS_DIP=y ++CONFIG_MS_MFE=y ++# CONFIG_MS_FB is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_5_defconfig b/arch/arm/configs/cedric_5_defconfig +new file mode 100644 +index 00000000..a201c26d +--- /dev/null ++++ b/arch/arm/configs/cedric_5_defconfig +@@ -0,0 +1,1873 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++# CONFIG_KERNEL_MODE_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++# CONFIG_PACKET is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_NET_KEY is not set ++# CONFIG_INET is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_ATM is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++# CONFIG_DMA_CMA is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++CONFIG_SND_VERBOSE_PROCFS=y ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_PCM_XRUN_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++CONFIG_SND_ARM=y ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=y ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_HUION is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=y ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++CONFIG_ARM_GLOBAL_TIMER=y ++CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_CA9_GT_CLOCKSOURCE=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++# CONFIG_MS_SOUND_CHICAGO is not set ++CONFIG_MS_USB_CEDRIC=y ++# CONFIG_MS_USB_CHICAGO is not set ++CONFIG_MS_SCALER=y ++# CONFIG_MS_CLONE_SCREEN is not set ++CONFIG_MS_SCALER_BOOT_PNL=y ++CONFIG_MS_DIP=y ++CONFIG_MS_MFE=y ++CONFIG_MS_FB=y ++CONFIG_MS_FB_CEDRIC=y ++# CONFIG_MS_FB_CHICAGO is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++# CONFIG_MSDOS_FS is not set ++# CONFIG_VFAT_FS is not set ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++# CONFIG_DEBUG_INFO is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_SF_defconfig b/arch/arm/configs/cedric_SF_defconfig +new file mode 100644 +index 00000000..6cb4d437 +--- /dev/null ++++ b/arch/arm/configs/cedric_SF_defconfig +@@ -0,0 +1,2044 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.18 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++# CONFIG_ARCH_CHICAGO is not set ++CONFIG_ARCH_INFINITY=y ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="infinity" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++# CONFIG_COREDUMP is not set ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++# CONFIG_MTD_UBI is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_MG_DISK is not set ++# CONFIG_BLK_DEV_RBD is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AT803X_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AMD_XGBE_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++# CONFIG_UNIX98_PTYS is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++# CONFIG_RC_MAP is not set ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=y ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOGGER is not set ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_CEDRIC=y ++# CONFIG_MS_ISP_INFINITY is not set ++# CONFIG_MS_NAND is not set ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++# CONFIG_MS_SOUND_INFINITY is not set ++# CONFIG_MS_USB_CEDRIC is not set ++CONFIG_MS_SCALER=y ++# CONFIG_MS_CLONE_SCREEN is not set ++# CONFIG_MS_SCALER_BOOT_PNL is not set ++CONFIG_MS_DIP=y ++CONFIG_MS_MFE=y ++# CONFIG_MS_FB is not set ++# CONFIG_MS_SCL is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_ETHERNET_ALBANY is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_IR=m ++# CONFIG_MS_IR_FANTASY_MODE is not set ++CONFIG_MS_IR_INPUT_DEVICE=y ++# CONFIG_IR_SUPPLY_RNG is not set ++# CONFIG_MS_IR_MULTIPLE_MODE is not set ++# CONFIG_MSTAR_PM_SWIR is not set ++CONFIG_MS_VHE=y ++# CONFIG_MS_RTC is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_LZO=y ++# CONFIG_SQUASHFS_XZ is not set ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++CONFIG_PRINTK_TIME=y ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_INFO_REDUCED=y ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++CONFIG_CRYPTO_ZLIB=y ++# CONFIG_CRYPTO_LZO is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/cedric_defconfig b/arch/arm/configs/cedric_defconfig +new file mode 100644 +index 00000000..774dffa3 +--- /dev/null ++++ b/arch/arm/configs/cedric_defconfig +@@ -0,0 +1,2302 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.21 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_DOMAIN_DEBUG=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="cedric-154a" ++CONFIG_MS_L2X0_PATCH=y ++CONFIG_MS_KERNEL_TYPE="" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_MG_DISK is not set ++# CONFIG_BLK_DEV_RBD is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++CONFIG_NET_CORE=y ++# CONFIG_BONDING is not set ++# CONFIG_DUMMY is not set ++# CONFIG_EQUALIZER is not set ++# CONFIG_NET_TEAM is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_VXLAN is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_TUN is not set ++# CONFIG_VETH is not set ++# CONFIG_NLMON is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AT803X_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AMD_XGBE_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++CONFIG_USB_NET_DRIVERS=y ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=y ++# CONFIG_USB_NET_AX88179_178A is not set ++# CONFIG_USB_NET_CDCETHER is not set ++# CONFIG_USB_NET_CDC_EEM is not set ++# CONFIG_USB_NET_CDC_NCM is not set ++# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set ++# CONFIG_USB_NET_CDC_MBIM is not set ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SR9700 is not set ++# CONFIG_USB_NET_SR9800 is not set ++# CONFIG_USB_NET_SMSC75XX is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++# CONFIG_USB_NET_GL620A is not set ++# CONFIG_USB_NET_NET1080 is not set ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++# CONFIG_USB_NET_RNDIS_HOST is not set ++# CONFIG_USB_NET_CDC_SUBSET is not set ++# CONFIG_USB_NET_ZAURUS is not set ++# CONFIG_USB_NET_CX82310_ETH is not set ++# CONFIG_USB_NET_KALMIA is not set ++# CONFIG_USB_NET_QMI_WWAN is not set ++# CONFIG_USB_NET_INT51X1 is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_USB_SIERRA_NET is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++CONFIG_SND_SUPPORT_OLD_API=y ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++# CONFIG_SND_DRIVERS is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++CONFIG_SND_SPI=y ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++ ++# ++# USB HID support ++# ++# CONFIG_USB_HID is not set ++# CONFIG_HID_PID is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=y ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_LINE6_USB is not set ++# CONFIG_BCM_WIMAX is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=y ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++CONFIG_ASHMEM=y ++# CONFIG_ANDROID_LOGGER is not set ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_USB_WPAN_HCD is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_CEDRIC=y ++CONFIG_MS_NAND=y ++CONFIG_MS_EMMC=y ++CONFIG_MS_EMMC_CEDRIC=y ++CONFIG_MS_SDMMC=y ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC_SECONDCARD=y ++CONFIG_MS_SDMMC_THIRDCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=36000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_HOTP=y ++CONFIG_MS_SDMMC2_MAXCLK=36000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_HOTP=y ++CONFIG_MS_SDMMC3_MAXCLK=24000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++# CONFIG_MS_SDMMC3_HOTP is not set ++CONFIG_MS_SDMMC3_FAKECDZ=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++CONFIG_MS_USB_CEDRIC=y ++CONFIG_MS_SCALER=y ++# CONFIG_MS_CLONE_SCREEN is not set ++CONFIG_MS_SCALER_BOOT_PNL=y ++CONFIG_MS_DIP=y ++CONFIG_MS_MFE=y ++CONFIG_MS_FB=y ++CONFIG_MS_FB_CEDRIC=y ++# CONFIG_MS_IR is not set ++# CONFIG_MS_I2C is not set ++# CONFIG_MS_GPIO is not set ++# CONFIG_MS_FLASH_ISP is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT23=y ++# CONFIG_EXT4_FS_POSIX_ACL is not set ++# CONFIG_EXT4_FS_SECURITY is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++CONFIG_JFFS2_FS_WRITEBUFFER=y ++# CONFIG_JFFS2_FS_WBUF_VERIFY is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_LZO=y ++# CONFIG_SQUASHFS_XZ is not set ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++# CONFIG_NFS_V2 is not set ++CONFIG_NFS_V3=m ++# CONFIG_NFS_V3_ACL is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=y ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++CONFIG_PRINTK_TIME=y ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_INFO_REDUCED=y ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++CONFIG_DEBUG_KMEMLEAK=y ++CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 ++# CONFIG_DEBUG_KMEMLEAK_TEST is not set ++# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++CONFIG_RCU_CPU_STALL_VERBOSE=y ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++CONFIG_CRYPTO_ZLIB=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_INFINITY is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/chicago_defconfig b/arch/arm/configs/chicago_defconfig +new file mode 100644 +index 00000000..4aa75e32 +--- /dev/null ++++ b/arch/arm/configs/chicago_defconfig +@@ -0,0 +1,1774 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.18 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++CONFIG_BUILD_BIN2C=y ++CONFIG_IKCONFIG=y ++# CONFIG_IKCONFIG_PROC is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++CONFIG_VM_EVENT_COUNTERS=y ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++CONFIG_ARCH_CHICAGO=y ++# CONFIG_ARCH_INFINITY is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="chicago" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_LRO=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++# CONFIG_MTD_UBI is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AT803X_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AMD_XGBE_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++# CONFIG_UNIX98_PTYS is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ANDROID is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++# CONFIG_MS_SOUND is not set ++# CONFIG_MS_USB_CHICAGO is not set ++CONFIG_MS_FB=y ++# CONFIG_MS_FB_CHICAGO is not set ++# CONFIG_MS_FLASH_ISP is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_LZO=y ++# CONFIG_SQUASHFS_XZ is not set ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_UPCALL is not set ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_DFS_UPCALL is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++CONFIG_PRINTK_TIME=y ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++CONFIG_DEBUG_PREEMPT=y ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++CONFIG_DEBUG_SPINLOCK=y ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++CONFIG_RCU_CPU_STALL_VERBOSE=y ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=m ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=m ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=m ++CONFIG_CRYPTO_HMAC=m ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_MD5=m ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=m ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=m ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++CONFIG_CRYPTO_ZLIB=y ++# CONFIG_CRYPTO_LZO is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/i1_c3_defconfig b/arch/arm/configs/i1_c3_defconfig +new file mode 100644 +index 00000000..66bbc712 +--- /dev/null ++++ b/arch/arm/configs/i1_c3_defconfig +@@ -0,0 +1,2229 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.18 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++CONFIG_ARCH_CEDRIC=y ++CONFIG_CEDRIC_MASTER0_ONLY_PATCH=y ++# CONFIG_ARCH_CHICAGO is not set ++CONFIG_ARCH_INFINITY=y ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="infinity" ++CONFIG_MS_L2X0_PATCH=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_OUTER_CACHE=y ++CONFIG_OUTER_CACHE_SYNC=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++CONFIG_CACHE_L2X0=y ++CONFIG_CACHE_PL310=y ++# CONFIG_PL310_ERRATA_588369 is not set ++# CONFIG_PL310_ERRATA_727915 is not set ++# CONFIG_PL310_ERRATA_753970 is not set ++# CONFIG_PL310_ERRATA_769419 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++# CONFIG_NEON is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++# CONFIG_COREDUMP is not set ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++# CONFIG_MTD_UBI is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_AT25 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++# CONFIG_SCSI is not set ++# CONFIG_SCSI_DMA is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AT803X_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AMD_XGBE_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++CONFIG_USB_NET_DRIVERS=m ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++# CONFIG_USB_RTL8152 is not set ++CONFIG_USB_USBNET=m ++CONFIG_USB_NET_AX8817X=m ++# CONFIG_USB_NET_AX88179_178A is not set ++# CONFIG_USB_NET_CDCETHER is not set ++# CONFIG_USB_NET_CDC_EEM is not set ++# CONFIG_USB_NET_CDC_NCM is not set ++# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set ++# CONFIG_USB_NET_CDC_MBIM is not set ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SR9700 is not set ++# CONFIG_USB_NET_SR9800 is not set ++# CONFIG_USB_NET_SMSC75XX is not set ++# CONFIG_USB_NET_SMSC95XX is not set ++# CONFIG_USB_NET_GL620A is not set ++# CONFIG_USB_NET_NET1080 is not set ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++# CONFIG_USB_NET_RNDIS_HOST is not set ++# CONFIG_USB_NET_CDC_SUBSET is not set ++# CONFIG_USB_NET_ZAURUS is not set ++# CONFIG_USB_NET_CX82310_ETH is not set ++# CONFIG_USB_NET_KALMIA is not set ++# CONFIG_USB_NET_QMI_WWAN is not set ++# CONFIG_USB_NET_INT51X1 is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_USB_SIERRA_NET is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++# CONFIG_UNIX98_PTYS is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=y ++# CONFIG_RC_MAP is not set ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++CONFIG_DVB_TUNER_DIB0070=m ++CONFIG_DVB_TUNER_DIB0090=m ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++CONFIG_SND_JACK=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++CONFIG_SND_DEBUG=y ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++CONFIG_SND_USB=y ++# CONFIG_SND_USB_AUDIO is not set ++# CONFIG_SND_USB_UA101 is not set ++# CONFIG_SND_USB_CAIAQ is not set ++# CONFIG_SND_USB_6FIRE is not set ++# CONFIG_SND_USB_HIFACE is not set ++# CONFIG_SND_BCD2000 is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++ ++# ++# USB HID support ++# ++# CONFIG_USB_HID is not set ++# CONFIG_HID_PID is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_LINE6_USB is not set ++# CONFIG_BCM_WIMAX is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=y ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++# CONFIG_ASHMEM is not set ++# CONFIG_ANDROID_LOGGER is not set ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_USB_WPAN_HCD is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_CEDRIC=y ++# CONFIG_MS_ISP_INFINITY is not set ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++# CONFIG_MS_SDMMC is not set ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_CEDRIC=y ++# CONFIG_MS_SOUND_INFINITY is not set ++CONFIG_MS_USB_CEDRIC=y ++CONFIG_MS_SCALER=y ++# CONFIG_MS_CLONE_SCREEN is not set ++# CONFIG_MS_SCALER_BOOT_PNL is not set ++CONFIG_MS_DIP=y ++CONFIG_MS_MFE=y ++# CONFIG_MS_FB is not set ++# CONFIG_MS_SCL is not set ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++# CONFIG_ETHERNET_ALBANY is not set ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_IR=m ++# CONFIG_MS_IR_FANTASY_MODE is not set ++CONFIG_MS_IR_INPUT_DEVICE=y ++# CONFIG_IR_SUPPLY_RNG is not set ++# CONFIG_MS_IR_MULTIPLE_MODE is not set ++# CONFIG_MSTAR_PM_SWIR is not set ++CONFIG_MS_VHE=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="utf8" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++CONFIG_SQUASHFS_FILE_CACHE=y ++# CONFIG_SQUASHFS_FILE_DIRECT is not set ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++# CONFIG_SQUASHFS_ZLIB is not set ++CONFIG_SQUASHFS_LZO=y ++# CONFIG_SQUASHFS_XZ is not set ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++# CONFIG_NLS_CODEPAGE_437 is not set ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++CONFIG_PRINTK_TIME=y ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++CONFIG_DEBUG_SPINLOCK=y ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++CONFIG_CRYPTO_ZLIB=y ++# CONFIG_CRYPTO_LZO is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity3_defconfig b/arch/arm/configs/infinity3_defconfig +new file mode 100644 +index 00000000..00b4b1ae +--- /dev/null ++++ b/arch/arm/configs/infinity3_defconfig +@@ -0,0 +1,2385 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.30 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_RESOURCE_COUNTERS is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++# CONFIG_TIMERFD is not set ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++# CONFIG_ARCH_INFINITY is not set ++CONFIG_ARCH_INFINITY3=y ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_MSTAR_CHIP_NAME="infinity3" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++# CONFIG_ARM_VIRT_EXT is not set ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++CONFIG_THUMB2_KERNEL=y ++CONFIG_THUMB2_AVOID_R_ARM_THM_JUMP11=y ++CONFIG_ARM_ASM_UNIFIED=y ++CONFIG_AEABI=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++# CONFIG_CMA_BUFFER_LIST is not set ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPUFREQ_DT is not set ++ ++# ++# ARM CPU frequency scaling drivers ++# ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++CONFIG_INET_LRO=y ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_REG_DEBUG is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=4 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++# CONFIG_PHYLIB is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_ATH_CARDS is not set ++# CONFIG_BRCMFMAC is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_LIBERTAS is not set ++# CONFIG_WL_TI is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_MT7601U=m ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++# CONFIG_USB_OTG_FSM is not set ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++# CONFIG_USB_PHY is not set ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++CONFIG_MS_OTG_ENABLE=y ++# CONFIG_USB_ULPI is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12057 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_XGENE is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++# CONFIG_LINE6_USB is not set ++# CONFIG_BCM_WIMAX is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=m ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++# CONFIG_ASHMEM is not set ++CONFIG_ANDROID_LOGGER=y ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ANDROID_INTF_ALARM_DEV is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_USB_WPAN_HCD is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_TI_CMEM=m ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_USCLK=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY3=y ++# CONFIG_MS_NAND is not set ++# CONFIG_MS_EMMC is not set ++CONFIG_MS_SDMMC=m ++CONFIG_MS_SDMMC_SLOTNUMS=1 ++CONFIG_MS_SDMMC1_IP=0 ++CONFIG_MS_SDMMC2_IP=1 ++CONFIG_MS_SDMMC3_IP=2 ++CONFIG_MS_SDMMC1_PAD=0 ++CONFIG_MS_SDMMC2_PAD=1 ++CONFIG_MS_SDMMC3_PAD=2 ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_INTCDZ=y ++CONFIG_MS_SDMMC2_MAXCLK=48000000 ++CONFIG_MS_SDMMC2_MAXDLVL=0 ++CONFIG_MS_SDMMC2_PASSLVL=0 ++CONFIG_MS_SDMMC2_INTCDZ=y ++CONFIG_MS_SDMMC3_MAXCLK=48000000 ++CONFIG_MS_SDMMC3_MAXDLVL=0 ++CONFIG_MS_SDMMC3_PASSLVL=0 ++CONFIG_MS_SDMMC3_INTCDZ=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_INFINITY3=y ++CONFIG_MS_FB=y ++CONFIG_MS_FB_INFINITY3=y ++CONFIG_MS_FB1_INFINITY3=y ++CONFIG_MS_FB2_INFINITY3=y ++CONFIG_MS_SCL=y ++CONFIG_MS_SCL_INFINITY3=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++CONFIG_ETHERNET_ALBANY=y ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY3=y ++CONFIG_MS_GPIO=y ++# CONFIG_MS_SW_I2C is not set ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MS_IRCUT=y ++CONFIG_MS_VHE=y ++CONFIG_MS_MFEV5=y ++CONFIG_MS_RTC=y ++CONFIG_MS_JPE=y ++CONFIG_MS_FLASH_ISP=y ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY3=y ++# CONFIG_MS_XPM is not set ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=m ++CONFIG_MS_SPINAND=m ++# CONFIG_NAND_SINGLE_READ is not set ++# CONFIG_NAND_DUAL_READ is not set ++# CONFIG_NAND_QUAL_READ is not set ++CONFIG_AUTO_DETECT=y ++# CONFIG_NAND_QUAL_WRITE is not set ++CONFIG_AUTO_DETECT_WRITE=y ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_PM is not set ++CONFIG_MS_IVE=y ++CONFIG_MS_NOTIFY=m ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++CONFIG_CRYPTO_SEQIV=y ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_ZLIB=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity_XIP_defconfig b/arch/arm/configs/infinity_XIP_defconfig +new file mode 100644 +index 00000000..ab609037 +--- /dev/null ++++ b/arch/arm/configs/infinity_XIP_defconfig +@@ -0,0 +1,2620 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.30 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_MULTIPLATFORM_XIP_CAPABLE=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_PHYS_OFFSET=0x20000000 ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_RESOURCE_COUNTERS is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++CONFIG_ARCH_INFINITY=y ++# CONFIG_ARCH_INFINITY3 is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="infinity-MST240A" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_MS_ARMV7_XIP=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++# CONFIG_ARM_VIRT_EXT is not set ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++# CONFIG_HZ_100 is not set ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++CONFIG_HZ_500=y ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=500 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++CONFIG_XIP_KERNEL=y ++CONFIG_XIP_PHYS_ADDR=0x14060080 ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPUFREQ_DT is not set ++ ++# ++# ARM CPU frequency scaling drivers ++# ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_PM_SLEEP=y ++CONFIG_PM_AUTOSLEEP=y ++# CONFIG_PM_WAKELOCKS is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++CONFIG_IP_MROUTE=y ++# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++CONFIG_INET_LRO=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_REG_DEBUG is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++# CONFIG_DEVTMPFS_MOUNT is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_MG_DISK is not set ++# CONFIG_BLK_DEV_RBD is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++# CONFIG_SENSORS_LIS3_SPI is not set ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++CONFIG_SCSI_LOGGING=y ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AT803X_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AMD_XGBE_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_ATH_CARDS is not set ++# CONFIG_BRCMFMAC is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_LIBERTAS is not set ++# CONFIG_WL_TI is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_MT7601U=m ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=m ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++CONFIG_MEDIA_SUPPORT=y ++ ++# ++# Multimedia core support ++# ++# CONFIG_MEDIA_CAMERA_SUPPORT is not set ++# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set ++# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set ++# CONFIG_MEDIA_RADIO_SUPPORT is not set ++# CONFIG_MEDIA_SDR_SUPPORT is not set ++CONFIG_MEDIA_RC_SUPPORT=y ++# CONFIG_VIDEO_ADV_DEBUG is not set ++# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set ++# CONFIG_TTPCI_EEPROM is not set ++ ++# ++# Media drivers ++# ++CONFIG_RC_CORE=m ++# CONFIG_RC_MAP is not set ++# CONFIG_RC_DECODERS is not set ++# CONFIG_RC_DEVICES is not set ++# CONFIG_MEDIA_USB_SUPPORT is not set ++ ++# ++# Supported MMC/SDIO adapters ++# ++# CONFIG_CYPRESS_FIRMWARE is not set ++ ++# ++# Media ancillary drivers (tuners, sensors, i2c, frontends) ++# ++ ++# ++# Customise DVB Frontends ++# ++# CONFIG_DVB_TUNER_DIB0070 is not set ++# CONFIG_DVB_TUNER_DIB0090 is not set ++ ++# ++# Tools to develop new frontends ++# ++# CONFIG_DVB_DUMMY_FE is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_DEBUG_VERBOSE is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L52 is not set ++# CONFIG_SND_SOC_CS42L56 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8962 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++ ++# ++# HID support ++# ++CONFIG_HID=m ++# CONFIG_HIDRAW is not set ++# CONFIG_UHID is not set ++CONFIG_HID_GENERIC=m ++ ++# ++# Special HID drivers ++# ++# CONFIG_HID_A4TECH is not set ++# CONFIG_HID_ACRUX is not set ++# CONFIG_HID_APPLE is not set ++# CONFIG_HID_APPLEIR is not set ++# CONFIG_HID_AUREAL is not set ++# CONFIG_HID_BELKIN is not set ++# CONFIG_HID_CHERRY is not set ++# CONFIG_HID_CHICONY is not set ++# CONFIG_HID_PRODIKEYS is not set ++# CONFIG_HID_CP2112 is not set ++# CONFIG_HID_CYPRESS is not set ++# CONFIG_HID_DRAGONRISE is not set ++# CONFIG_HID_EMS_FF is not set ++# CONFIG_HID_ELECOM is not set ++# CONFIG_HID_ELO is not set ++# CONFIG_HID_EZKEY is not set ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_HUION is not set ++# CONFIG_HID_KEYTOUCH is not set ++# CONFIG_HID_KYE is not set ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++# CONFIG_HID_GYRATION is not set ++# CONFIG_HID_ICADE is not set ++# CONFIG_HID_TWINHAN is not set ++# CONFIG_HID_KENSINGTON is not set ++# CONFIG_HID_LCPOWER is not set ++# CONFIG_HID_LENOVO is not set ++# CONFIG_HID_LOGITECH is not set ++# CONFIG_HID_MAGICMOUSE is not set ++# CONFIG_HID_MICROSOFT is not set ++# CONFIG_HID_MONTEREY is not set ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++# CONFIG_HID_ORTEK is not set ++# CONFIG_HID_PANTHERLORD is not set ++# CONFIG_HID_PENMOUNT is not set ++# CONFIG_HID_PETALYNX is not set ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_PRIMAX is not set ++# CONFIG_HID_ROCCAT is not set ++# CONFIG_HID_SAITEK is not set ++# CONFIG_HID_SAMSUNG is not set ++# CONFIG_HID_SPEEDLINK is not set ++# CONFIG_HID_STEELSERIES is not set ++# CONFIG_HID_SUNPLUS is not set ++# CONFIG_HID_RMI is not set ++# CONFIG_HID_GREENASIA is not set ++# CONFIG_HID_SMARTJOYPLUS is not set ++# CONFIG_HID_TIVO is not set ++# CONFIG_HID_TOPSEED is not set ++# CONFIG_HID_THRUSTMASTER is not set ++# CONFIG_HID_WACOM is not set ++# CONFIG_HID_XINMO is not set ++# CONFIG_HID_ZEROPLUS is not set ++# CONFIG_HID_ZYDACRON is not set ++# CONFIG_HID_SENSOR_HUB is not set ++ ++# ++# USB HID support ++# ++CONFIG_USB_HID=m ++# CONFIG_HID_PID is not set ++# CONFIG_USB_HIDDEV is not set ++ ++# ++# USB HID Boot Protocol drivers ++# ++# CONFIG_USB_KBD is not set ++# CONFIG_USB_MOUSE is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++CONFIG_USB_OTG_FSM=m ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++CONFIG_USB_PHY=y ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++CONFIG_MS_OTG_ENABLE=y ++CONFIG_USB_MS_OTG=m ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++CONFIG_USB_GADGET_MSB250X=m ++CONFIG_USB_MSB250X=m ++CONFIG_USB_MSB250X_DMA=m ++# CONFIG_USB_MSB250X_DEBUG is not set ++# CONFIG_USB_MSB250X_PROC is not set ++# CONFIG_USB_MSB250X_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_USB_F_ACM=m ++CONFIG_USB_U_SERIAL=m ++CONFIG_USB_F_SERIAL=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++CONFIG_USB_G_ANDROID=m ++CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED=y ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12057 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_XGENE is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++# CONFIG_LINE6_USB is not set ++# CONFIG_BCM_WIMAX is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=m ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++CONFIG_ASHMEM=m ++CONFIG_ANDROID_LOGGER=y ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ANDROID_INTF_ALARM_DEV is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_USB_WPAN_HCD is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_TI_CMEM=m ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_USCLK=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY=y ++CONFIG_MS_NAND=m ++CONFIG_MS_SDMMC=m ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++# CONFIG_MS_SDMMC_SECONDCARD is not set ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_HOTP=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_INFINITY=y ++CONFIG_MS_USB_INFINITY=m ++CONFIG_MS_FB=y ++CONFIG_MS_FB_INFINITY=y ++CONFIG_MS_SCL=y ++CONFIG_MS_SCL_INFINITY=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++CONFIG_ETHERNET_ALBANY=y ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++CONFIG_MS_IR=m ++# CONFIG_MS_IR_FANTASY_MODE is not set ++CONFIG_MS_IR_INPUT_DEVICE=y ++# CONFIG_IR_SUPPLY_RNG is not set ++# CONFIG_MS_IR_MULTIPLE_MODE is not set ++# CONFIG_MSTAR_PM_SWIR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_GPIO_INFINITY=y ++# CONFIG_MS_SW_I2C_INFINITY is not set ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MS_IRCUT=y ++CONFIG_MS_VHE=y ++CONFIG_MS_MFEV5=y ++CONFIG_MS_RTC=y ++CONFIG_MS_JPE=y ++CONFIG_MS_FLASH_ISP=y ++# CONFIG_FLASH_ISP_READFUNC_MAP is not set ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY=y ++CONFIG_MS_XPM=y ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=m ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_PM is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++# CONFIG_NFS_FS is not set ++# CONFIG_NFSD is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=y ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++CONFIG_CRYPTO_SEQIV=y ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_ZLIB=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity_defconfig b/arch/arm/configs/infinity_defconfig +new file mode 100644 +index 00000000..d9b6474f +--- /dev/null ++++ b/arch/arm/configs/infinity_defconfig +@@ -0,0 +1,2452 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.30 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_MULTIPLATFORM_XIP_CAPABLE=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_CROSS_MEMORY_ATTACH is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++# CONFIG_BUILD_BIN2C is not set ++# CONFIG_IKCONFIG is not set ++CONFIG_LOG_BUF_SHIFT=15 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_RESOURCE_COUNTERS is not set ++# CONFIG_CGROUP_SCHED is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++CONFIG_IPC_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++CONFIG_RD_GZIP=y ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++# CONFIG_KALLSYMS is not set ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++# CONFIG_BASE_FULL is not set ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++# CONFIG_TIMERFD is not set ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++# CONFIG_ADVISE_SYSCALLS is not set ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++CONFIG_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR_NONE is not set ++CONFIG_CC_STACKPROTECTOR_REGULAR=y ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=1 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_BLOCK=y ++# CONFIG_LBDAF is not set ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++# CONFIG_IOSCHED_CFQ is not set ++CONFIG_DEFAULT_DEADLINE=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="deadline" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++CONFIG_ARCH_INFINITY=y ++# CONFIG_ARCH_INFINITY3 is not set ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="infinity-MST240A" ++CONFIG_MS_KERNEL_TYPE="" ++CONFIG_MS_ARMV7_XIP=y ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++# CONFIG_ARM_VIRT_EXT is not set ++# CONFIG_SWP_EMULATE is not set ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++# CONFIG_SMP is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++CONFIG_CMA_DEBUG=y ++CONFIG_CMA_DEBUGFS=y ++CONFIG_CMA_AREAS=1 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=10 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_GOV_COMMON=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_STAT_DETAILS=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set ++# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set ++# CONFIG_CPUFREQ_DT is not set ++ ++# ++# ARM CPU frequency scaling drivers ++# ++# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_PM_SLEEP=y ++CONFIG_PM_AUTOSLEEP=y ++# CONFIG_PM_WAKELOCKS is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM_CPU_SUSPEND=y ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++CONFIG_UNIX_DIAG=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++# CONFIG_IP_FIB_TRIE_STATS is not set ++# CONFIG_IP_MULTIPLE_TABLES is not set ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_IP_MROUTE is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++CONFIG_INET_LRO=y ++# CONFIG_INET_DIAG is not set ++CONFIG_TCP_CONG_ADVANCED=y ++# CONFIG_TCP_CONG_BIC is not set ++CONFIG_TCP_CONG_CUBIC=y ++# CONFIG_TCP_CONG_WESTWOOD is not set ++# CONFIG_TCP_CONG_HTCP is not set ++# CONFIG_TCP_CONG_HSTCP is not set ++# CONFIG_TCP_CONG_HYBLA is not set ++# CONFIG_TCP_CONG_VEGAS is not set ++# CONFIG_TCP_CONG_SCALABLE is not set ++# CONFIG_TCP_CONG_LP is not set ++# CONFIG_TCP_CONG_VENO is not set ++# CONFIG_TCP_CONG_YEAH is not set ++# CONFIG_TCP_CONG_ILLINOIS is not set ++# CONFIG_TCP_CONG_DCTCP is not set ++CONFIG_DEFAULT_CUBIC=y ++# CONFIG_DEFAULT_RENO is not set ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++CONFIG_HAVE_NET_DSA=y ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++# CONFIG_CGROUP_NET_PRIO is not set ++# CONFIG_CGROUP_NET_CLASSID is not set ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++CONFIG_WIRELESS=y ++CONFIG_WIRELESS_EXT=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_WEXT_PRIV=y ++CONFIG_CFG80211=m ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_REG_DEBUG is not set ++# CONFIG_CFG80211_CERTIFICATION_ONUS is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_DEBUGFS is not set ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_WEXT=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++# CONFIG_DEVTMPFS is not set ++# CONFIG_STANDALONE is not set ++# CONFIG_PREVENT_FIRMWARE_BUILD is not set ++# CONFIG_FW_LOADER is not set ++# CONFIG_ALLOW_DEV_COREDUMP is not set ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++CONFIG_REGMAP=y ++CONFIG_REGMAP_I2C=y ++CONFIG_REGMAP_SPI=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++CONFIG_MTD_TESTS=m ++# CONFIG_MTD_REDBOOT_PARTS is not set ++CONFIG_MTD_CMDLINE_PARTS=y ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++CONFIG_MTD_BLKDEVS=y ++CONFIG_MTD_BLOCK=y ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++CONFIG_MTD_RAM=y ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++CONFIG_MTD_PHYSMAP_OF=y ++CONFIG_MTD_PLATRAM=y ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_DATAFLASH is not set ++# CONFIG_MTD_SST25L is not set ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=m ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=m ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_GPIO is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=m ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=m ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_NET=y ++CONFIG_OF_MDIO=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++# CONFIG_BLK_DEV is not set ++ ++# ++# Misc devices ++# ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_TI_DAC7512 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_BMP085_SPI is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_LATTICE_ECP3_CONFIG is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++CONFIG_EEPROM_AT24=m ++# CONFIG_EEPROM_AT25 is not set ++CONFIG_EEPROM_LEGACY=m ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_EEPROM_93XX46 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=m ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=m ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++CONFIG_SCSI_LOGGING=y ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++CONFIG_MII=y ++# CONFIG_NET_CORE is not set ++ ++# ++# CAIF transport drivers ++# ++ ++# ++# Distributed Switch Architecture drivers ++# ++# CONFIG_NET_DSA_MV88E6XXX is not set ++# CONFIG_NET_DSA_MV88E6060 is not set ++# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set ++# CONFIG_NET_DSA_MV88E6131 is not set ++# CONFIG_NET_DSA_MV88E6123_61_65 is not set ++# CONFIG_NET_DSA_MV88E6171 is not set ++# CONFIG_NET_DSA_BCM_SF2 is not set ++# CONFIG_ETHERNET is not set ++CONFIG_PHYLIB=y ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_AT803X_PHY is not set ++# CONFIG_AMD_PHY is not set ++# CONFIG_AMD_XGBE_PHY is not set ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_BCM7XXX_PHY is not set ++# CONFIG_BCM87XX_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++# CONFIG_FIXED_PHY is not set ++# CONFIG_MDIO_BITBANG is not set ++# CONFIG_MDIO_BUS_MUX_GPIO is not set ++# CONFIG_MDIO_BUS_MUX_MMIOREG is not set ++# CONFIG_MDIO_BCM_UNIMAC is not set ++# CONFIG_MICREL_KS8995MA is not set ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++ ++# ++# Host-side USB support is needed for USB Network Adapter support ++# ++# CONFIG_USB_NET_DRIVERS is not set ++CONFIG_WLAN=y ++# CONFIG_USB_ZD1201 is not set ++# CONFIG_USB_NET_RNDIS_WLAN is not set ++# CONFIG_ATH_CARDS is not set ++# CONFIG_BRCMFMAC is not set ++# CONFIG_HOSTAP is not set ++# CONFIG_LIBERTAS is not set ++# CONFIG_WL_TI is not set ++# CONFIG_MWIFIEX is not set ++CONFIG_MT7601U=m ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++# CONFIG_WAN is not set ++# CONFIG_ISDN is not set ++ ++# ++# Input device support ++# ++# CONFIG_INPUT is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++# CONFIG_VT is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++# CONFIG_SERIAL_MAX3100 is not set ++# CONFIG_SERIAL_MAX310X is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_IFX6X60 is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++# CONFIG_I2C_COMPAT is not set ++CONFIG_I2C_CHARDEV=y ++# CONFIG_I2C_MUX is not set ++# CONFIG_I2C_HELPER_AUTO is not set ++# CONFIG_I2C_SMBUS is not set ++ ++# ++# I2C Algorithms ++# ++# CONFIG_I2C_ALGOBIT is not set ++# CONFIG_I2C_ALGOPCF is not set ++# CONFIG_I2C_ALGOPCA is not set ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_CBUS_GPIO is not set ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_GPIO is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_DIOLAN_U2C is not set ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_ROBOTFUZZ_OSIF is not set ++# CONFIG_I2C_TAOS_EVM is not set ++# CONFIG_I2C_TINY_USB is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++CONFIG_SPI=y ++# CONFIG_SPI_DEBUG is not set ++CONFIG_SPI_MASTER=y ++ ++# ++# SPI Master Controller Drivers ++# ++# CONFIG_SPI_ALTERA is not set ++# CONFIG_SPI_BITBANG is not set ++# CONFIG_SPI_CADENCE is not set ++# CONFIG_SPI_GPIO is not set ++# CONFIG_SPI_FSL_SPI is not set ++# CONFIG_SPI_OC_TINY is not set ++# CONFIG_SPI_PXA2XX_PCI is not set ++# CONFIG_SPI_ROCKCHIP is not set ++# CONFIG_SPI_SC18IS602 is not set ++# CONFIG_SPI_XCOMM is not set ++# CONFIG_SPI_XILINX is not set ++# CONFIG_SPI_DESIGNWARE is not set ++ ++# ++# SPI Protocol Masters ++# ++# CONFIG_SPI_SPIDEV is not set ++# CONFIG_SPI_TLE62X0 is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_EM is not set ++# CONFIG_GPIO_ZEVIO is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++# CONFIG_GPIO_MAX7300 is not set ++# CONFIG_GPIO_MAX732X is not set ++# CONFIG_GPIO_PCA953X is not set ++# CONFIG_GPIO_PCF857X is not set ++# CONFIG_GPIO_SX150X is not set ++# CONFIG_GPIO_ADP5588 is not set ++# CONFIG_GPIO_ADNP is not set ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++# CONFIG_GPIO_MAX7301 is not set ++# CONFIG_GPIO_MCP23S08 is not set ++# CONFIG_GPIO_MC33880 is not set ++# CONFIG_GPIO_74X164 is not set ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++CONFIG_WATCHDOG=y ++CONFIG_WATCHDOG_CORE=y ++CONFIG_WATCHDOG_NOWAYOUT=y ++ ++# ++# Watchdog Device Drivers ++# ++# CONFIG_SOFT_WATCHDOG is not set ++# CONFIG_GPIO_WATCHDOG is not set ++# CONFIG_XILINX_WATCHDOG is not set ++# CONFIG_CADENCE_WATCHDOG is not set ++# CONFIG_DW_WATCHDOG is not set ++# CONFIG_MAX63XX_WATCHDOG is not set ++# CONFIG_MEN_A21_WDT is not set ++ ++# ++# USB-based Watchdog Cards ++# ++# CONFIG_USBPCWATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_AAT2870_CORE is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_ASIC3 is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_SPI is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_SPI is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_EGPIO is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_HTC_I2CPLD is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_EZX_PCAP is not set ++# CONFIG_MFD_VIPERBOARD is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RTSX_USB is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS65010 is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS65910 is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TPS65912_I2C is not set ++# CONFIG_MFD_TPS65912_SPI is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_ARIZONA_SPI is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM831X_SPI is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++CONFIG_FB_SYS_FILLRECT=y ++CONFIG_FB_SYS_COPYAREA=y ++CONFIG_FB_SYS_IMAGEBLIT=y ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++CONFIG_FB_SYS_FOPS=y ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_SMSCUFX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_FB_SSD1307 is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_LOGO is not set ++CONFIG_SOUND=y ++# CONFIG_SOUND_OSS_CORE is not set ++CONFIG_SND=y ++CONFIG_SND_TIMER=y ++CONFIG_SND_PCM=y ++CONFIG_SND_COMPRESS_OFFLOAD=y ++# CONFIG_SND_SEQUENCER is not set ++# CONFIG_SND_MIXER_OSS is not set ++# CONFIG_SND_PCM_OSS is not set ++# CONFIG_SND_HRTIMER is not set ++# CONFIG_SND_DYNAMIC_MINORS is not set ++# CONFIG_SND_SUPPORT_OLD_API is not set ++# CONFIG_SND_VERBOSE_PROCFS is not set ++# CONFIG_SND_VERBOSE_PRINTK is not set ++# CONFIG_SND_DEBUG is not set ++# CONFIG_SND_RAWMIDI_SEQ is not set ++# CONFIG_SND_OPL3_LIB_SEQ is not set ++# CONFIG_SND_OPL4_LIB_SEQ is not set ++# CONFIG_SND_SBAWE_SEQ is not set ++# CONFIG_SND_EMU10K1_SEQ is not set ++CONFIG_SND_DRIVERS=y ++# CONFIG_SND_DUMMY is not set ++# CONFIG_SND_ALOOP is not set ++# CONFIG_SND_MTPAV is not set ++# CONFIG_SND_SERIAL_U16550 is not set ++# CONFIG_SND_MPU401 is not set ++ ++# ++# HD-Audio ++# ++# CONFIG_SND_ARM is not set ++# CONFIG_SND_SPI is not set ++# CONFIG_SND_USB is not set ++CONFIG_SND_SOC=y ++# CONFIG_SND_ATMEL_SOC is not set ++# CONFIG_SND_DESIGNWARE_I2S is not set ++ ++# ++# SoC Audio for Freescale CPUs ++# ++ ++# ++# Common SoC Audio options for Freescale CPUs: ++# ++# CONFIG_SND_SOC_FSL_ASRC is not set ++# CONFIG_SND_SOC_FSL_SAI is not set ++# CONFIG_SND_SOC_FSL_SSI is not set ++# CONFIG_SND_SOC_FSL_SPDIF is not set ++# CONFIG_SND_SOC_FSL_ESAI is not set ++# CONFIG_SND_SOC_IMX_AUDMUX is not set ++CONFIG_SND_SOC_I2C_AND_SPI=y ++ ++# ++# CODEC drivers ++# ++# CONFIG_SND_SOC_ADAU1701 is not set ++# CONFIG_SND_SOC_AK4104 is not set ++# CONFIG_SND_SOC_AK4554 is not set ++# CONFIG_SND_SOC_AK4642 is not set ++# CONFIG_SND_SOC_AK5386 is not set ++# CONFIG_SND_SOC_ALC5623 is not set ++# CONFIG_SND_SOC_CS35L32 is not set ++# CONFIG_SND_SOC_CS42L73 is not set ++# CONFIG_SND_SOC_CS4265 is not set ++# CONFIG_SND_SOC_CS4270 is not set ++# CONFIG_SND_SOC_CS4271 is not set ++# CONFIG_SND_SOC_CS42XX8_I2C is not set ++# CONFIG_SND_SOC_HDMI_CODEC is not set ++# CONFIG_SND_SOC_ES8328 is not set ++# CONFIG_SND_SOC_PCM1681 is not set ++# CONFIG_SND_SOC_PCM1792A is not set ++# CONFIG_SND_SOC_PCM512x_I2C is not set ++# CONFIG_SND_SOC_PCM512x_SPI is not set ++# CONFIG_SND_SOC_SGTL5000 is not set ++# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set ++# CONFIG_SND_SOC_SPDIF is not set ++# CONFIG_SND_SOC_SSM2602_SPI is not set ++# CONFIG_SND_SOC_SSM2602_I2C is not set ++# CONFIG_SND_SOC_SSM4567 is not set ++# CONFIG_SND_SOC_STA350 is not set ++# CONFIG_SND_SOC_TAS2552 is not set ++# CONFIG_SND_SOC_TAS5086 is not set ++# CONFIG_SND_SOC_TLV320AIC31XX is not set ++# CONFIG_SND_SOC_TLV320AIC3X is not set ++# CONFIG_SND_SOC_WM8510 is not set ++# CONFIG_SND_SOC_WM8523 is not set ++# CONFIG_SND_SOC_WM8580 is not set ++# CONFIG_SND_SOC_WM8711 is not set ++# CONFIG_SND_SOC_WM8728 is not set ++# CONFIG_SND_SOC_WM8731 is not set ++# CONFIG_SND_SOC_WM8737 is not set ++# CONFIG_SND_SOC_WM8741 is not set ++# CONFIG_SND_SOC_WM8750 is not set ++# CONFIG_SND_SOC_WM8753 is not set ++# CONFIG_SND_SOC_WM8770 is not set ++# CONFIG_SND_SOC_WM8776 is not set ++# CONFIG_SND_SOC_WM8804 is not set ++# CONFIG_SND_SOC_WM8903 is not set ++# CONFIG_SND_SOC_WM8978 is not set ++# CONFIG_SND_SOC_TPA6130A2 is not set ++# CONFIG_SND_SIMPLE_CARD is not set ++# CONFIG_SOUND_PRIME is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++CONFIG_USB_SUPPORT=y ++CONFIG_MP_USB_MSTAR=y ++CONFIG_MP_USB_STR_PATCH=y ++CONFIG_USB_COMMON=m ++CONFIG_USB_ARCH_HAS_HCD=y ++CONFIG_USB=m ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++CONFIG_USB_DEFAULT_PERSIST=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++CONFIG_USB_OTG=y ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++CONFIG_USB_OTG_FSM=m ++# CONFIG_USB_MON is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_XHCI_HCD is not set ++CONFIG_USB_EHCI_HCD=m ++CONFIG_USB_EHCI_ROOT_HUB_TT=y ++CONFIG_USB_EHCI_TT_NEWSCHED=y ++# CONFIG_USB_EHCI_HCD_PLATFORM is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_FUSBH200_HCD is not set ++# CONFIG_USB_FOTG210_HCD is not set ++# CONFIG_USB_MAX3421_HCD is not set ++# CONFIG_USB_OHCI_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HCD_TEST_MODE is not set ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=m ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++# CONFIG_USBIP_CORE is not set ++# CONFIG_USB_MUSB_HDRC is not set ++# CONFIG_USB_DWC3 is not set ++# CONFIG_USB_DWC2 is not set ++# CONFIG_USB_CHIPIDEA is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_SISUSBVGA is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_EHSET_TEST_FIXTURE is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_EZUSB_FX2 is not set ++# CONFIG_USB_HSIC_USB3503 is not set ++# CONFIG_USB_LINK_LAYER_TEST is not set ++ ++# ++# USB Physical Layer drivers ++# ++CONFIG_USB_PHY=y ++# CONFIG_NOP_USB_XCEIV is not set ++# CONFIG_AM335X_PHY_USB is not set ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ISP1301 is not set ++CONFIG_MS_OTG_ENABLE=y ++CONFIG_USB_MS_OTG=m ++# CONFIG_USB_ULPI is not set ++CONFIG_USB_GADGET=m ++# CONFIG_USB_GADGET_DEBUG is not set ++# CONFIG_USB_GADGET_DEBUG_FILES is not set ++# CONFIG_USB_GADGET_DEBUG_FS is not set ++CONFIG_USB_GADGET_VBUS_DRAW=2 ++CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 ++ ++# ++# USB Peripheral Controller ++# ++CONFIG_USB_GADGET_MSB250X=m ++CONFIG_USB_MSB250X=m ++CONFIG_USB_MSB250X_DMA=m ++# CONFIG_USB_MSB250X_DEBUG is not set ++# CONFIG_USB_MSB250X_PROC is not set ++# CONFIG_USB_MSB250X_FPGA is not set ++# CONFIG_USB_CHARGER_DETECT is not set ++# CONFIG_USB_FUSB300 is not set ++# CONFIG_USB_FOTG210_UDC is not set ++# CONFIG_USB_GR_UDC is not set ++# CONFIG_USB_R8A66597 is not set ++# CONFIG_USB_PXA27X is not set ++# CONFIG_USB_MV_UDC is not set ++# CONFIG_USB_MV_U3D is not set ++# CONFIG_USB_M66592 is not set ++# CONFIG_USB_NET2272 is not set ++# CONFIG_USB_GADGET_XILINX is not set ++# CONFIG_USB_DUMMY_HCD is not set ++CONFIG_USB_LIBCOMPOSITE=m ++CONFIG_USB_F_ACM=m ++CONFIG_USB_U_SERIAL=m ++CONFIG_USB_F_SERIAL=m ++# CONFIG_USB_CONFIGFS is not set ++# CONFIG_USB_ZERO is not set ++# CONFIG_USB_AUDIO is not set ++# CONFIG_USB_ETH is not set ++# CONFIG_USB_G_NCM is not set ++# CONFIG_USB_GADGETFS is not set ++# CONFIG_USB_FUNCTIONFS is not set ++# CONFIG_USB_MASS_STORAGE is not set ++# CONFIG_USB_G_SERIAL is not set ++# CONFIG_USB_MIDI_GADGET is not set ++# CONFIG_USB_G_PRINTER is not set ++CONFIG_USB_G_ANDROID=m ++CONFIG_USB_ANDROID_RNDIS_DWORD_ALIGNED=y ++# CONFIG_USB_CDC_COMPOSITE is not set ++# CONFIG_USB_G_ACM_MS is not set ++# CONFIG_USB_G_MULTI is not set ++# CONFIG_USB_G_HID is not set ++# CONFIG_USB_G_DBGP is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=m ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=m ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_SPI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_HCTOSYS=y ++CONFIG_RTC_SYSTOHC=y ++CONFIG_RTC_HCTOSYS_DEVICE="rtc0" ++# CONFIG_RTC_DEBUG is not set ++ ++# ++# RTC interfaces ++# ++CONFIG_RTC_INTF_SYSFS=y ++CONFIG_RTC_INTF_PROC=y ++CONFIG_RTC_INTF_DEV=y ++# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set ++# CONFIG_RTC_DRV_TEST is not set ++ ++# ++# I2C RTC drivers ++# ++# CONFIG_RTC_DRV_DS1307 is not set ++# CONFIG_RTC_DRV_DS1374 is not set ++# CONFIG_RTC_DRV_DS1672 is not set ++# CONFIG_RTC_DRV_DS3232 is not set ++# CONFIG_RTC_DRV_HYM8563 is not set ++# CONFIG_RTC_DRV_MAX6900 is not set ++# CONFIG_RTC_DRV_RS5C372 is not set ++# CONFIG_RTC_DRV_ISL1208 is not set ++# CONFIG_RTC_DRV_ISL12022 is not set ++# CONFIG_RTC_DRV_ISL12057 is not set ++# CONFIG_RTC_DRV_X1205 is not set ++# CONFIG_RTC_DRV_PCF2127 is not set ++# CONFIG_RTC_DRV_PCF8523 is not set ++# CONFIG_RTC_DRV_PCF8563 is not set ++# CONFIG_RTC_DRV_PCF85063 is not set ++# CONFIG_RTC_DRV_PCF8583 is not set ++# CONFIG_RTC_DRV_M41T80 is not set ++# CONFIG_RTC_DRV_BQ32K is not set ++# CONFIG_RTC_DRV_S35390A is not set ++# CONFIG_RTC_DRV_FM3130 is not set ++# CONFIG_RTC_DRV_RX8581 is not set ++# CONFIG_RTC_DRV_RX8025 is not set ++# CONFIG_RTC_DRV_EM3027 is not set ++# CONFIG_RTC_DRV_RV3029C2 is not set ++ ++# ++# SPI RTC drivers ++# ++# CONFIG_RTC_DRV_M41T93 is not set ++# CONFIG_RTC_DRV_M41T94 is not set ++# CONFIG_RTC_DRV_DS1305 is not set ++# CONFIG_RTC_DRV_DS1343 is not set ++# CONFIG_RTC_DRV_DS1347 is not set ++# CONFIG_RTC_DRV_DS1390 is not set ++# CONFIG_RTC_DRV_MAX6902 is not set ++# CONFIG_RTC_DRV_R9701 is not set ++# CONFIG_RTC_DRV_RS5C348 is not set ++# CONFIG_RTC_DRV_DS3234 is not set ++# CONFIG_RTC_DRV_PCF2123 is not set ++# CONFIG_RTC_DRV_RX4581 is not set ++# CONFIG_RTC_DRV_MCP795 is not set ++ ++# ++# Platform RTC drivers ++# ++# CONFIG_RTC_DRV_CMOS is not set ++# CONFIG_RTC_DRV_DS1286 is not set ++# CONFIG_RTC_DRV_DS1511 is not set ++# CONFIG_RTC_DRV_DS1553 is not set ++# CONFIG_RTC_DRV_DS1742 is not set ++# CONFIG_RTC_DRV_DS2404 is not set ++# CONFIG_RTC_DRV_STK17TA8 is not set ++# CONFIG_RTC_DRV_M48T86 is not set ++# CONFIG_RTC_DRV_M48T35 is not set ++# CONFIG_RTC_DRV_M48T59 is not set ++# CONFIG_RTC_DRV_MSM6242 is not set ++# CONFIG_RTC_DRV_BQ4802 is not set ++# CONFIG_RTC_DRV_RP5C01 is not set ++# CONFIG_RTC_DRV_V3020 is not set ++ ++# ++# on-CPU RTC drivers ++# ++# CONFIG_RTC_DRV_SNVS is not set ++# CONFIG_RTC_DRV_XGENE is not set ++ ++# ++# HID Sensor RTC drivers ++# ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++CONFIG_UIO=y ++CONFIG_UIO_PDRV_GENIRQ=y ++# CONFIG_UIO_DMEM_GENIRQ is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_PRISM2_USB is not set ++# CONFIG_COMEDI is not set ++# CONFIG_RTLLIB is not set ++# CONFIG_R8712U is not set ++# CONFIG_R8188EU is not set ++# CONFIG_LINE6_USB is not set ++# CONFIG_BCM_WIMAX is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++CONFIG_ANDROID=y ++CONFIG_ANDROID_BINDER_IPC=m ++CONFIG_ANDROID_BINDER_IPC_32BIT=y ++# CONFIG_ASHMEM is not set ++CONFIG_ANDROID_LOGGER=y ++# CONFIG_ANDROID_TIMED_OUTPUT is not set ++# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set ++# CONFIG_ANDROID_INTF_ALARM_DEV is not set ++# CONFIG_SYNC is not set ++# CONFIG_ION is not set ++# CONFIG_USB_WPAN_HCD is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LTE_GDM724X is not set ++# CONFIG_MTD_SPINAND_MT29F is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++CONFIG_PWM=y ++CONFIG_PWM_SYSFS=y ++# CONFIG_PWM_FSL_FTM is not set ++# CONFIG_PWM_PCA9685 is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_TI_CMEM=m ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_ZEN=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_USCLK=m ++CONFIG_MS_ISP=y ++CONFIG_MS_ISP_INFINITY=y ++CONFIG_MS_NAND=m ++CONFIG_MS_SDMMC=m ++# CONFIG_MS_SDMMC_REVCDZ is not set ++CONFIG_MS_SDMMC_TCARD=y ++# CONFIG_MS_SDMMC_SECONDCARD is not set ++CONFIG_MS_SDMMC1_MAXCLK=48000000 ++CONFIG_MS_SDMMC1_MAXDLVL=0 ++CONFIG_MS_SDMMC1_PASSLVL=0 ++CONFIG_MS_SDMMC1_HOTP=y ++CONFIG_MS_SOUND=y ++CONFIG_MS_SOUND_INFINITY=y ++CONFIG_MS_USB_INFINITY=m ++CONFIG_MS_FB=y ++CONFIG_MS_FB_INFINITY=y ++CONFIG_MS_SCL=y ++CONFIG_MS_SCL_INFINITY=y ++CONFIG_MS_EMAC=y ++# CONFIG_EMAC_SUPPLY_RNG is not set ++CONFIG_ETHERNET_ALBANY=y ++# CONFIG_MSTAR_HW_TX_CHECKSUM is not set ++# CONFIG_K3_RX_SWPATCH is not set ++CONFIG_DISCONNECT_DELAY_S=1 ++# CONFIG_MSTAR_EEE is not set ++# CONFIG_MS_IR is not set ++CONFIG_MS_I2C=y ++CONFIG_MS_I2C_INFINITY=y ++CONFIG_MS_GPIO=y ++CONFIG_MS_GPIO_INFINITY=y ++# CONFIG_MS_SW_I2C_INFINITY is not set ++CONFIG_MS_WATCHDOG=y ++CONFIG_MS_SAR=y ++CONFIG_MS_IRCUT=y ++CONFIG_MS_VHE=y ++CONFIG_MS_MFEV5=y ++CONFIG_MS_RTC=y ++CONFIG_MS_JPE=y ++CONFIG_MS_FLASH_ISP=y ++# CONFIG_FLASH_ISP_READFUNC_MAP is not set ++CONFIG_MS_FLASH_ISP_MXP_PARTS=y ++CONFIG_MS_FLASH_ISP_INFINITY=y ++CONFIG_MS_XPM=y ++CONFIG_MS_CRYPTO=m ++CONFIG_MS_CPU_FREQ=y ++CONFIG_MS_PWM=m ++# CONFIG_MS_SPINAND is not set ++# CONFIG_MS_SPI_INFINITY is not set ++# CONFIG_MS_PM is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++# CONFIG_EXT4_FS is not set ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=m ++CONFIG_MSDOS_FS=m ++CONFIG_VFAT_FS=m ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_TMPFS_XATTR=y ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_YAFFS_FS is not set ++CONFIG_JFFS2_FS=y ++CONFIG_JFFS2_FS_DEBUG=0 ++# CONFIG_JFFS2_FS_WRITEBUFFER is not set ++# CONFIG_JFFS2_SUMMARY is not set ++# CONFIG_JFFS2_FS_XATTR is not set ++# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set ++CONFIG_JFFS2_ZLIB=y ++# CONFIG_JFFS2_LZO is not set ++CONFIG_JFFS2_RTIME=y ++# CONFIG_JFFS2_RUBIN is not set ++CONFIG_UBIFS_FS=m ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++CONFIG_SQUASHFS=y ++# CONFIG_SQUASHFS_FILE_CACHE is not set ++CONFIG_SQUASHFS_FILE_DIRECT=y ++CONFIG_SQUASHFS_DECOMP_SINGLE=y ++# CONFIG_SQUASHFS_DECOMP_MULTI is not set ++# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set ++# CONFIG_SQUASHFS_XATTR is not set ++CONFIG_SQUASHFS_ZLIB=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y ++CONFIG_SQUASHFS_EMBEDDED=y ++CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=m ++CONFIG_NFS_V2=m ++# CONFIG_NFS_V3 is not set ++# CONFIG_NFS_V4 is not set ++# CONFIG_NFS_SWAP is not set ++# CONFIG_NFSD is not set ++CONFIG_GRACE_PERIOD=m ++CONFIG_LOCKD=m ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=m ++# CONFIG_SUNRPC_DEBUG is not set ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_XATTR is not set ++# CONFIG_CIFS_DEBUG is not set ++# CONFIG_CIFS_SMB2 is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=3 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=4096 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_PREEMPT is not set ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++CONFIG_DEBUG_RT_MUTEXES=y ++CONFIG_DEBUG_SPINLOCK=y ++CONFIG_DEBUG_MUTEXES=y ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++# CONFIG_RCU_CPU_STALL_VERBOSE is not set ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=y ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++# CONFIG_CRYPTO_USER is not set ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++CONFIG_CRYPTO_SEQIV=y ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_CTR=y ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=y ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_CMAC=y ++CONFIG_CRYPTO_HMAC=y ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++# CONFIG_CRYPTO_CRC32C is not set ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=y ++CONFIG_CRYPTO_MD5=y ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++CONFIG_CRYPTO_SHA256=y ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=y ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=y ++CONFIG_CRYPTO_ZLIB=y ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_ZLIB_DEFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++# CONFIG_XZ_DEC_X86 is not set ++# CONFIG_XZ_DEC_POWERPC is not set ++# CONFIG_XZ_DEC_IA64 is not set ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++# CONFIG_XZ_DEC_SPARC is not set ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity_fpga_defconfig b/arch/arm/configs/infinity_fpga_defconfig +new file mode 100644 +index 00000000..b9b90733 +--- /dev/null ++++ b/arch/arm/configs/infinity_fpga_defconfig +@@ -0,0 +1,1780 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_DOMAIN_DEBUG=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_RCU_USER_QS is not set ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_RCU_FAST_NO_HZ is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++CONFIG_BUILD_BIN2C=y ++CONFIG_IKCONFIG=y ++# CONFIG_IKCONFIG_PROC is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++CONFIG_VM_EVENT_COUNTERS=y ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_STOP_MACHINE=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++CONFIG_ARCH_INFINITY=y ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="infinity-fpga" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_643719 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++CONFIG_ARM_ERRATA_798181=y ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_MCPM=y ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=16 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_LRO=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++# CONFIG_MTD_BLOCK is not set ++# CONFIG_MTD_BLOCK_RO is not set ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_SWAP is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ANDROID is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_SCL=y ++CONFIG_MS_SCL_INFINITY=y ++CONFIG_MS_INFINITY_ISP=y ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT23=y ++# CONFIG_EXT4_FS_POSIX_ACL is not set ++# CONFIG_EXT4_FS_SECURITY is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++# CONFIG_NFS_FS is not set ++# CONFIG_NFSD is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_INFO_REDUCED=y ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++CONFIG_DEBUG_KMEMLEAK=y ++CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=800 ++# CONFIG_DEBUG_KMEMLEAK_TEST is not set ++# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++CONFIG_DEBUG_PREEMPT=y ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++CONFIG_RCU_CPU_STALL_VERBOSE=y ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_USER is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_PCRYPT is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_CMAC is not set ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/configs/infinity_zebu_defconfig b/arch/arm/configs/infinity_zebu_defconfig +new file mode 100644 +index 00000000..c57473e5 +--- /dev/null ++++ b/arch/arm/configs/infinity_zebu_defconfig +@@ -0,0 +1,1782 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.18.14 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_ARM_HAS_SG_CHAIN=y ++CONFIG_MIGHT_HAVE_PCI=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_ARCH_SUPPORTS_UPROBES=y ++CONFIG_VECTORS_BASE=0xffff0000 ++CONFIG_ARM_PATCH_PHYS_VIRT=y ++CONFIG_GENERIC_BUG=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_XZ=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_HAVE_KERNEL_LZ4=y ++# CONFIG_KERNEL_GZIP is not set ++# CONFIG_KERNEL_LZMA is not set ++CONFIG_KERNEL_XZ=y ++# CONFIG_KERNEL_LZO is not set ++# CONFIG_KERNEL_LZ4 is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++# CONFIG_SYSVIPC is not set ++# CONFIG_POSIX_MQUEUE is not set ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++CONFIG_USELIB=y ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++CONFIG_IRQ_DOMAIN_DEBUG=y ++CONFIG_IRQ_FORCED_THREADING=y ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++# CONFIG_IRQ_TIME_ACCOUNTING is not set ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_TASKSTATS is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_RCU_USER_QS is not set ++CONFIG_RCU_FANOUT=32 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_RCU_FAST_NO_HZ is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++CONFIG_BUILD_BIN2C=y ++CONFIG_IKCONFIG=y ++# CONFIG_IKCONFIG_PROC is not set ++CONFIG_LOG_BUF_SHIFT=17 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 ++CONFIG_GENERIC_SCHED_CLOCK=y ++# CONFIG_CGROUPS is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++CONFIG_UTS_NS=y ++# CONFIG_USER_NS is not set ++CONFIG_PID_NS=y ++CONFIG_NET_NS=y ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="" ++# CONFIG_RD_GZIP is not set ++# CONFIG_RD_BZIP2 is not set ++# CONFIG_RD_LZMA is not set ++CONFIG_RD_XZ=y ++# CONFIG_RD_LZO is not set ++# CONFIG_RD_LZ4 is not set ++CONFIG_CC_OPTIMIZE_FOR_SIZE=y ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_BPF=y ++CONFIG_EXPERT=y ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++# CONFIG_KALLSYMS_ALL is not set ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++CONFIG_VM_EVENT_COUNTERS=y ++# CONFIG_SLUB_DEBUG is not set ++CONFIG_COMPAT_BRK=y ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++# CONFIG_SLOB is not set ++CONFIG_SLUB_CPU_PARTIAL=y ++# CONFIG_SYSTEM_TRUSTED_KEYRING is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_ARCH_USE_BUILTIN_BSWAP=y ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_GENERIC_IDLE_POLL_SETUP=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_ARCH_SECCOMP_FILTER=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y ++CONFIG_HAVE_MOD_ARCH_SPECIFIC=y ++CONFIG_MODULES_USE_ELF_REL=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++CONFIG_MODULE_FORCE_LOAD=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODULE_FORCE_UNLOAD=y ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++CONFIG_MODULE_COMPRESS=y ++# CONFIG_MODULE_COMPRESS_GZIP is not set ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_STOP_MACHINE=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++CONFIG_BLK_DEV_BSG=y ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++# CONFIG_FREEZER is not set ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++CONFIG_ARCH_MULTIPLATFORM=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE_LEGACY is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C24XX is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP1 is not set ++ ++# ++# Multiple platform selection ++# ++ ++# ++# CPU Core family selection ++# ++# CONFIG_ARCH_MULTI_V6 is not set ++CONFIG_ARCH_MULTI_V7=y ++CONFIG_ARCH_MULTI_V6_V7=y ++# CONFIG_ARCH_MULTI_CPU_AUTO is not set ++# CONFIG_ARCH_VIRT is not set ++# CONFIG_ARCH_MVEBU is not set ++# CONFIG_ARCH_BCM is not set ++# CONFIG_ARCH_BERLIN is not set ++# CONFIG_ARCH_HIGHBANK is not set ++# CONFIG_ARCH_HISI is not set ++# CONFIG_ARCH_KEYSTONE is not set ++# CONFIG_ARCH_MESON is not set ++CONFIG_ARCH_MSTAR=y ++# CONFIG_ARCH_CEDRIC is not set ++# CONFIG_ARCH_CHICAGO is not set ++CONFIG_ARCH_INFINITY=y ++ ++# ++# Options ++# ++CONFIG_MS_BUILTIN_DTB="infinity-zebu" ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MEDIATEK is not set ++ ++# ++# TI OMAP/AM/DM/DRA Family ++# ++# CONFIG_ARCH_OMAP3 is not set ++# CONFIG_ARCH_OMAP4 is not set ++# CONFIG_SOC_OMAP5 is not set ++# CONFIG_SOC_AM33XX is not set ++# CONFIG_SOC_AM43XX is not set ++# CONFIG_SOC_DRA7XX is not set ++# CONFIG_ARCH_QCOM is not set ++# CONFIG_ARCH_ROCKCHIP is not set ++# CONFIG_ARCH_SOCFPGA is not set ++# CONFIG_PLAT_SPEAR is not set ++# CONFIG_ARCH_STI is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS is not set ++# CONFIG_ARCH_SHMOBILE_MULTI is not set ++# CONFIG_ARCH_SUNXI is not set ++# CONFIG_ARCH_SIRF is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_WM8850 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V7=y ++CONFIG_CPU_32v6K=y ++CONFIG_CPU_32v7=y ++CONFIG_CPU_ABRT_EV7=y ++CONFIG_CPU_PABRT_V7=y ++CONFIG_CPU_CACHE_V7=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V7=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++ ++# ++# Processor Features ++# ++# CONFIG_ARM_LPAE is not set ++# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set ++CONFIG_ARM_THUMB=y ++CONFIG_ARM_THUMBEE=y ++CONFIG_ARM_VIRT_EXT=y ++CONFIG_SWP_EMULATE=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_KUSER_HELPERS=y ++CONFIG_MIGHT_HAVE_CACHE_L2X0=y ++# CONFIG_CACHE_L2X0 is not set ++CONFIG_ARM_L1_CACHE_SHIFT_6=y ++CONFIG_ARM_L1_CACHE_SHIFT=6 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_MULTI_IRQ_HANDLER=y ++# CONFIG_ARM_ERRATA_430973 is not set ++# CONFIG_ARM_ERRATA_643719 is not set ++# CONFIG_ARM_ERRATA_720789 is not set ++# CONFIG_ARM_ERRATA_754322 is not set ++# CONFIG_ARM_ERRATA_754327 is not set ++# CONFIG_ARM_ERRATA_764369 is not set ++# CONFIG_ARM_ERRATA_775420 is not set ++CONFIG_ARM_ERRATA_798181=y ++# CONFIG_ARM_ERRATA_773022 is not set ++ ++# ++# Bus support ++# ++# CONFIG_PCI is not set ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_HAVE_SMP=y ++CONFIG_SMP=y ++CONFIG_SMP_ON_UP=y ++CONFIG_ARM_CPU_TOPOLOGY=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_HAVE_ARM_ARCH_TIMER=y ++CONFIG_MCPM=y ++# CONFIG_BIG_LITTLE is not set ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_NR_CPUS=16 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_ARM_PSCI is not set ++CONFIG_ARCH_NR_GPIO=0 ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ_FIXED=0 ++CONFIG_HZ_100=y ++# CONFIG_HZ_200 is not set ++# CONFIG_HZ_250 is not set ++# CONFIG_HZ_300 is not set ++# CONFIG_HZ_500 is not set ++# CONFIG_HZ_1000 is not set ++CONFIG_HZ=100 ++CONFIG_SCHED_HRTICK=y ++# CONFIG_THUMB2_KERNEL is not set ++CONFIG_AEABI=y ++# CONFIG_OABI_COMPAT is not set ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HIGHMEM=y ++# CONFIG_HIGHPTE is not set ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_CLEANCACHE is not set ++# CONFIG_FRONTSWAP is not set ++# CONFIG_CMA is not set ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_FORCE_MAX_ZONEORDER=13 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++# CONFIG_XEN is not set ++ ++# ++# Boot options ++# ++CONFIG_USE_OF=y ++CONFIG_ATAGS=y ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++CONFIG_ZBOOT_ROM_TEXT=0 ++CONFIG_ZBOOT_ROM_BSS=0 ++CONFIG_ARM_APPENDED_DTB=y ++CONFIG_ARM_ATAG_DTB_COMPAT=y ++CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set ++CONFIG_CMDLINE="" ++# CONFIG_CRASH_DUMP is not set ++CONFIG_AUTO_ZRELADDR=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++CONFIG_VFP=y ++CONFIG_VFPv3=y ++CONFIG_NEON=y ++CONFIG_KERNEL_MODE_NEON=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++ ++# ++# Power management options ++# ++# CONFIG_SUSPEND is not set ++# CONFIG_HIBERNATION is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++# CONFIG_ARM_CPU_SUSPEND is not set ++CONFIG_ARCH_HIBERNATION_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++# CONFIG_PACKET_DIAG is not set ++CONFIG_UNIX=y ++# CONFIG_UNIX_DIAG is not set ++CONFIG_XFRM=y ++# CONFIG_XFRM_USER is not set ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++# CONFIG_NET_KEY is not set ++CONFIG_INET=y ++# CONFIG_IP_MULTICAST is not set ++# CONFIG_IP_ADVANCED_ROUTER is not set ++# CONFIG_IP_PNP is not set ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_NET_IP_TUNNEL is not set ++# CONFIG_SYN_COOKIES is not set ++# CONFIG_NET_IPVTI is not set ++# CONFIG_NET_UDP_TUNNEL is not set ++# CONFIG_NET_FOU is not set ++# CONFIG_GENEVE is not set ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++CONFIG_INET_XFRM_MODE_TRANSPORT=y ++CONFIG_INET_XFRM_MODE_TUNNEL=y ++CONFIG_INET_XFRM_MODE_BEET=y ++CONFIG_INET_LRO=y ++CONFIG_INET_DIAG=y ++CONFIG_INET_TCP_DIAG=y ++# CONFIG_INET_UDP_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NET_PTP_CLASSIFY is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++# CONFIG_DNS_RESOLVER is not set ++# CONFIG_BATMAN_ADV is not set ++# CONFIG_OPENVSWITCH is not set ++# CONFIG_VSOCKETS is not set ++# CONFIG_NETLINK_MMAP is not set ++# CONFIG_NETLINK_DIAG is not set ++# CONFIG_NET_MPLS_GSO is not set ++# CONFIG_HSR is not set ++CONFIG_RPS=y ++CONFIG_RFS_ACCEL=y ++CONFIG_XPS=y ++CONFIG_NET_RX_BUSY_POLL=y ++CONFIG_BQL=y ++# CONFIG_BPF_JIT is not set ++CONFIG_NET_FLOW_LIMIT=y ++ ++# ++# Network testing ++# ++# CONFIG_NET_PKTGEN is not set ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++# CONFIG_WIRELESS is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER=y ++CONFIG_UEVENT_HELPER_PATH="" ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_SOC_BUS=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++ ++# ++# Bus devices ++# ++# CONFIG_BRCMSTB_GISB_ARB is not set ++# CONFIG_ARM_CCI is not set ++# CONFIG_VEXPRESS_CONFIG is not set ++# CONFIG_CONNECTOR is not set ++CONFIG_MTD=y ++# CONFIG_MTD_TESTS is not set ++# CONFIG_MTD_REDBOOT_PARTS is not set ++# CONFIG_MTD_CMDLINE_PARTS is not set ++# CONFIG_MTD_AFS_PARTS is not set ++# CONFIG_MTD_OF_PARTS is not set ++# CONFIG_MTD_AR7_PARTS is not set ++ ++# ++# User Modules And Translation Layers ++# ++# CONFIG_MTD_BLOCK is not set ++# CONFIG_MTD_BLOCK_RO is not set ++# CONFIG_FTL is not set ++# CONFIG_NFTL is not set ++# CONFIG_INFTL is not set ++# CONFIG_RFD_FTL is not set ++# CONFIG_SSFDC is not set ++# CONFIG_SM_FTL is not set ++# CONFIG_MTD_OOPS is not set ++# CONFIG_MTD_SWAP is not set ++ ++# ++# RAM/ROM/Flash chip drivers ++# ++# CONFIG_MTD_CFI is not set ++# CONFIG_MTD_JEDECPROBE is not set ++CONFIG_MTD_MAP_BANK_WIDTH_1=y ++CONFIG_MTD_MAP_BANK_WIDTH_2=y ++CONFIG_MTD_MAP_BANK_WIDTH_4=y ++# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set ++# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set ++CONFIG_MTD_CFI_I1=y ++CONFIG_MTD_CFI_I2=y ++# CONFIG_MTD_CFI_I4 is not set ++# CONFIG_MTD_CFI_I8 is not set ++# CONFIG_MTD_RAM is not set ++# CONFIG_MTD_ROM is not set ++# CONFIG_MTD_ABSENT is not set ++ ++# ++# Mapping drivers for chip access ++# ++# CONFIG_MTD_COMPLEX_MAPPINGS is not set ++# CONFIG_MTD_PLATRAM is not set ++ ++# ++# Self-contained MTD device drivers ++# ++# CONFIG_MTD_SLRAM is not set ++# CONFIG_MTD_PHRAM is not set ++# CONFIG_MTD_MTDRAM is not set ++# CONFIG_MTD_BLOCK2MTD is not set ++ ++# ++# Disk-On-Chip Device Drivers ++# ++# CONFIG_MTD_DOCG3 is not set ++CONFIG_MTD_NAND_ECC=y ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND=y ++# CONFIG_MTD_NAND_ECC_BCH is not set ++# CONFIG_MTD_SM_COMMON is not set ++# CONFIG_MTD_NAND_DENALI is not set ++# CONFIG_MTD_NAND_OMAP_BCH_BUILD is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_MTD_NAND_DOCG4 is not set ++# CONFIG_MTD_NAND_NANDSIM is not set ++# CONFIG_MTD_NAND_PLATFORM is not set ++# CONFIG_MTD_ONENAND is not set ++ ++# ++# LPDDR & LPDDR2 PCM memory drivers ++# ++# CONFIG_MTD_LPDDR is not set ++# CONFIG_MTD_LPDDR2_NVM is not set ++# CONFIG_MTD_SPI_NOR is not set ++CONFIG_MTD_UBI=y ++CONFIG_MTD_UBI_WL_THRESHOLD=4096 ++CONFIG_MTD_UBI_BEB_LIMIT=20 ++# CONFIG_MTD_UBI_FASTMAP is not set ++# CONFIG_MTD_UBI_GLUEBI is not set ++# CONFIG_MTD_UBI_BLOCK is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_MTD=y ++CONFIG_OF_RESERVED_MEM=y ++CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++# CONFIG_BLK_DEV_DRBD is not set ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_BLK_DEV_RBD is not set ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_AD525X_DPOT is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ICS932S401 is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_APDS9802ALS is not set ++# CONFIG_ISL29003 is not set ++# CONFIG_ISL29020 is not set ++# CONFIG_SENSORS_TSL2550 is not set ++# CONFIG_SENSORS_BH1780 is not set ++# CONFIG_SENSORS_BH1770 is not set ++# CONFIG_SENSORS_APDS990X is not set ++# CONFIG_HMC6352 is not set ++# CONFIG_DS1682 is not set ++# CONFIG_BMP085_I2C is not set ++# CONFIG_USB_SWITCH_FSA9480 is not set ++# CONFIG_SRAM is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_AT24 is not set ++# CONFIG_EEPROM_LEGACY is not set ++# CONFIG_EEPROM_MAX6875 is not set ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_SENSORS_LIS3_I2C is not set ++ ++# ++# Altera FPGA firmware download module ++# ++# CONFIG_ALTERA_STAPL is not set ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_MQ_DEFAULT is not set ++CONFIG_SCSI_PROC_FS=y ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++CONFIG_SCSI_LOWLEVEL=y ++# CONFIG_ISCSI_TCP is not set ++# CONFIG_ISCSI_BOOT_SYSFS is not set ++# CONFIG_SCSI_UFSHCD is not set ++# CONFIG_SCSI_DEBUG is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++# CONFIG_NETDEVICES is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++# CONFIG_SERIO is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++# CONFIG_VT_HW_CONSOLE_BINDING is not set ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=256 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_MSTAR is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_SC16IS7XX is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_SERIAL_ST_ASC is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++CONFIG_HW_RANDOM=y ++# CONFIG_HW_RANDOM_TIMERIOMEM is not set ++# CONFIG_R3964 is not set ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++# CONFIG_I2C_CHARDEV is not set ++# CONFIG_I2C_MUX is not set ++CONFIG_I2C_HELPER_AUTO=y ++ ++# ++# I2C Hardware Bus support ++# ++ ++# ++# I2C system bus drivers (mostly embedded / system-on-chip) ++# ++# CONFIG_I2C_DESIGNWARE_PLATFORM is not set ++# CONFIG_I2C_OCORES is not set ++# CONFIG_I2C_PCA_PLATFORM is not set ++# CONFIG_I2C_PXA_PCI is not set ++# CONFIG_I2C_RK3X is not set ++# CONFIG_I2C_SIMTEC is not set ++# CONFIG_I2C_XILINX is not set ++ ++# ++# External I2C/SMBus adapter drivers ++# ++# CONFIG_I2C_PARPORT_LIGHT is not set ++# CONFIG_I2C_TAOS_EVM is not set ++ ++# ++# Other I2C/SMBus bus drivers ++# ++# CONFIG_I2C_STUB is not set ++# CONFIG_I2C_DEBUG_CORE is not set ++# CONFIG_I2C_DEBUG_ALGO is not set ++# CONFIG_I2C_DEBUG_BUS is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++# CONFIG_PTP_1588_CLOCK is not set ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++# CONFIG_GPIOLIB is not set ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_AS3711 is not set ++# CONFIG_MFD_AS3722 is not set ++# CONFIG_PMIC_ADP5520 is not set ++# CONFIG_MFD_BCM590XX is not set ++# CONFIG_MFD_AXP20X is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_PMIC_DA903X is not set ++# CONFIG_MFD_DA9052_I2C is not set ++# CONFIG_MFD_DA9055 is not set ++# CONFIG_MFD_DA9063 is not set ++# CONFIG_MFD_MC13XXX_I2C is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_INTEL_SOC_PMIC is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_88PM800 is not set ++# CONFIG_MFD_88PM805 is not set ++# CONFIG_MFD_88PM860X is not set ++# CONFIG_MFD_MAX14577 is not set ++# CONFIG_MFD_MAX77686 is not set ++# CONFIG_MFD_MAX77693 is not set ++# CONFIG_MFD_MAX8907 is not set ++# CONFIG_MFD_MAX8925 is not set ++# CONFIG_MFD_MAX8997 is not set ++# CONFIG_MFD_MAX8998 is not set ++# CONFIG_MFD_MENF21BMC is not set ++# CONFIG_MFD_RETU is not set ++# CONFIG_MFD_PCF50633 is not set ++# CONFIG_MFD_PM8921_CORE is not set ++# CONFIG_MFD_RC5T583 is not set ++# CONFIG_MFD_RK808 is not set ++# CONFIG_MFD_RN5T618 is not set ++# CONFIG_MFD_SEC_CORE is not set ++# CONFIG_MFD_SI476X_CORE is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_MFD_SMSC is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_STMPE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_LP3943 is not set ++# CONFIG_MFD_LP8788 is not set ++# CONFIG_MFD_PALMAS is not set ++# CONFIG_TPS6105X is not set ++# CONFIG_TPS6507X is not set ++# CONFIG_MFD_TPS65090 is not set ++# CONFIG_MFD_TPS65217 is not set ++# CONFIG_MFD_TPS65218 is not set ++# CONFIG_MFD_TPS6586X is not set ++# CONFIG_MFD_TPS80031 is not set ++# CONFIG_TWL4030_CORE is not set ++# CONFIG_TWL6040_CORE is not set ++# CONFIG_MFD_WL1273_CORE is not set ++# CONFIG_MFD_LM3533 is not set ++# CONFIG_MFD_TC3589X is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_T7L66XB is not set ++# CONFIG_MFD_TC6387XB is not set ++# CONFIG_MFD_TC6393XB is not set ++# CONFIG_MFD_ARIZONA_I2C is not set ++# CONFIG_MFD_WM8400 is not set ++# CONFIG_MFD_WM831X_I2C is not set ++# CONFIG_MFD_WM8350_I2C is not set ++# CONFIG_MFD_WM8994 is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++CONFIG_FB_CMDLINE=y ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++# CONFIG_FB_CFB_FILLRECT is not set ++# CONFIG_FB_CFB_COPYAREA is not set ++# CONFIG_FB_CFB_IMAGEBLIT is not set ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++# CONFIG_FB_OPENCORES is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_FB_AUO_K190X is not set ++# CONFIG_FB_SIMPLE is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE is not set ++# CONFIG_LOGO is not set ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++ ++# ++# I2C HID support ++# ++# CONFIG_I2C_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_SDHCI is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_USDHI6ROL0 is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++# CONFIG_EDAC is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_MMIO is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++CONFIG_STAGING=y ++# CONFIG_COMEDI is not set ++# CONFIG_FT1000 is not set ++ ++# ++# Speakup console speech ++# ++# CONFIG_SPEAKUP is not set ++# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set ++# CONFIG_STAGING_MEDIA is not set ++ ++# ++# Android ++# ++# CONFIG_ANDROID is not set ++# CONFIG_WIMAX_GDM72XX is not set ++# CONFIG_LUSTRE_FS is not set ++# CONFIG_DGAP is not set ++# CONFIG_GS_FPGABOOT is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++# CONFIG_COMMON_CLK_SI5351 is not set ++# CONFIG_COMMON_CLK_SI570 is not set ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++CONFIG_MSTAR_DRIVERS=y ++CONFIG_MS_PIU_TIMER=y ++CONFIG_MS_MSYS=y ++CONFIG_MS_SERIAL=y ++CONFIG_MS_INFINITY_ISP=y ++# CONFIG_MS_SOUND is not set ++CONFIG_MS_SCL=y ++CONFIG_MS_SCL_INFINITY=y ++# CONFIG_MS_EMAC is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT23=y ++# CONFIG_EXT4_FS_POSIX_ACL is not set ++# CONFIG_EXT4_FS_SECURITY is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++# CONFIG_FUSE_FS is not set ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_JFFS2_FS is not set ++CONFIG_UBIFS_FS=y ++CONFIG_UBIFS_FS_ADVANCED_COMPR=y ++CONFIG_UBIFS_FS_LZO=y ++# CONFIG_UBIFS_FS_ZLIB is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_QNX6FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++# CONFIG_F2FS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++# CONFIG_NFS_FS is not set ++# CONFIG_NFSD is not set ++# CONFIG_CEPH_FS is not set ++# CONFIG_CIFS is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++CONFIG_NLS_UTF8=y ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_INFO_REDUCED=y ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_MAGIC_SYSRQ is not set ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++CONFIG_DEBUG_KMEMLEAK=y ++CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=800 ++# CONFIG_DEBUG_KMEMLEAK_TEST is not set ++# CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_HIGHMEM is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++CONFIG_LOCKUP_DETECTOR=y ++# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set ++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 ++# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set ++CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++CONFIG_SCHED_DEBUG=y ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++CONFIG_DEBUG_PREEMPT=y ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++CONFIG_STACKTRACE=y ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++CONFIG_RCU_CPU_STALL_VERBOSE=y ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_BPF is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_ARM_PTDUMP is not set ++# CONFIG_STRICT_DEVMEM is not set ++CONFIG_ARM_UNWIND=y ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" ++# CONFIG_DEBUG_UART_PL01X is not set ++# CONFIG_DEBUG_UART_8250 is not set ++# CONFIG_DEBUG_UART_BCM63XX is not set ++CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_PERSISTENT_KEYRINGS is not set ++# CONFIG_BIG_KEYS is not set ++# CONFIG_ENCRYPTED_KEYS is not set ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_USER is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_PCRYPT is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_CMAC is not set ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA1_ARM is not set ++# CONFIG_CRYPTO_SHA1_ARM_NEON is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_SHA512_ARM_NEON is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_AES_ARM is not set ++# CONFIG_CRYPTO_AES_ARM_BS is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++CONFIG_CRYPTO_LZO=y ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_ASYMMETRIC_KEY_TYPE is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_NET_UTILS=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++# CONFIG_AUDIT_ARCH_COMPAT_GENERIC is not set ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_ASSOCIATIVE_ARRAY=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT_MAP=y ++CONFIG_HAS_DMA=y ++CONFIG_CPU_RMAP=y ++CONFIG_DQL=y ++CONFIG_NLATTR=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y ++# CONFIG_VIRTUALIZATION is not set +diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h +index 891a56b3..1d82294b 100644 +--- a/arch/arm/include/asm/outercache.h ++++ b/arch/arm/include/asm/outercache.h +@@ -36,6 +36,11 @@ struct outer_cache_fns { + + /* This is an ARM L2C thing */ + void (*write_sec)(unsigned long, unsigned); ++ ++#ifdef CONFIG_MS_L2X0_PATCH ++ void (*flush_MIU_pipe)(void); ++#endif ++ + }; + + extern struct outer_cache_fns outer_cache; +diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c +index 11c54de9..9ccee243 100644 +--- a/arch/arm/kernel/devtree.c ++++ b/arch/arm/kernel/devtree.c +@@ -27,6 +27,10 @@ + #include + #include + ++#ifdef CONFIG_MS_BUILTIN_DTB ++extern void *builtin_dtb_start; ++#endif ++ + + #ifdef CONFIG_SMP + extern struct of_cpu_method __cpu_method_of_table[]; +@@ -213,7 +217,27 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys) + #endif + + if (!dt_phys || !early_init_dt_verify(phys_to_virt(dt_phys))) +- return NULL; ++ { ++#ifdef CONFIG_MS_BUILTIN_DTB ++ if(early_init_dt_verify(builtin_dtb_start)) ++ { ++ extern int early_atags_to_fdt(void *atag_list, void *fdt, int total_space); ++ extern u32 builtin_dtb_size; ++ ++// early_print("early_init_dt_verify() pass...\n"); ++ if((!dt_phys ) || (!early_atags_to_fdt(phys_to_virt(dt_phys),builtin_dtb_start,builtin_dtb_size))) ++ { ++ early_print("early_atags_to_fdt() success\n"); ++ } ++ ++ ++ } ++ else ++#endif ++ { ++ return NULL; ++ } ++ } + + mdesc = of_flat_dt_match_machine(mdesc_best, arch_get_next_mach); + +diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c +index 6a4dffef..30e83ceb 100644 +--- a/arch/arm/kernel/module.c ++++ b/arch/arm/kernel/module.c +@@ -34,7 +34,11 @@ + * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. + */ + #undef MODULES_VADDR +-#define MODULES_VADDR (((unsigned long)_etext + ~PMD_MASK) & PMD_MASK) ++#ifdef CONFIG_MS_ARMV7_XIP ++#define MODULES_VADDR (((unsigned long)_edata_loc + ~PMD_MASK) & PMD_MASK) ++#else ++#define MODULES_VADDR (((unsigned long)_etext + ~PMD_MASK) & PMD_MASK) ++#endif + #endif + + #ifdef CONFIG_MMU +diff --git a/arch/arm/mach-mstar/Kconfig b/arch/arm/mach-mstar/Kconfig +new file mode 100644 +index 00000000..8127ccd3 +--- /dev/null ++++ b/arch/arm/mach-mstar/Kconfig +@@ -0,0 +1,78 @@ ++menuconfig ARCH_MSTAR ++ bool "MStar ARM SoCs" ++ ++if ARCH_MSTAR ++config ARCH_CEDRIC ++ bool "SoC Cedric (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ ++ help ++ Support for Cedric SoC ++ ++config CEDRIC_MASTER0_ONLY_PATCH ++ bool ++ depends on ARCH_CEDRIC ++ default y ++ ++config ARCH_CHICAGO ++ bool "SoC Chicago (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select VFP ++ select VFPv3 ++ ++ help ++ Support for Chicago SoC ++ ++config ARCH_INFINITY ++ bool "SoC iNfinity (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ select MULTIPLATFORM_XIP_CAPABLE ++ help ++ Support for iNfinity SoC ++ ++config ARCH_INFINITY3 ++ bool "SoC iNfinity3 (ARCH_MULTI_V7)" if ARCH_MULTI_V7 ++ select SOC_BUS ++ select ARM_GIC ++ select VFP ++ select VFPv3 ++ select WIRELESS_EXT if WIRELESS && NET ++ select WEXT_PRIV if WIRELESS && NET ++ help ++ Support for iNfinity3 SoC ++ ++comment "Options" ++config MS_BUILTIN_DTB ++ string "Builtin DTB" ++ default "" ++ ++config MS_L2X0_PATCH ++ bool "L2X0 patch" ++ depends on CACHE_L2X0 ++ default y ++ ++config MS_KERNEL_TYPE ++ string ++ default "" ++ ++config MS_ARMV7_XIP ++ bool ++ default y ++ depends on XIP_KERNEL ++ ++config MSTAR_CHIP_NAME ++ string ++ default "infinity3" if ARCH_INFINITY3 ++ default "infinity" if ARCH_INFINITY ++ default "chicago" if ARCH_CHICAGO ++ ++endif ++ +diff --git a/arch/arm/mach-mstar/Makefile b/arch/arm/mach-mstar/Makefile +new file mode 100644 +index 00000000..420856ea +--- /dev/null ++++ b/arch/arm/mach-mstar/Makefile +@@ -0,0 +1,8 @@ ++ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++ ++obj-y += ms_chip.o atags_to_fdt.o ++obj-$(CONFIG_TI_CMEM_STUB) += cmemk_stub.o ++obj-y += $(CONFIG_MSTAR_CHIP_NAME)/ +diff --git a/arch/arm/mach-mstar/atags_to_fdt.c b/arch/arm/mach-mstar/atags_to_fdt.c +new file mode 100644 +index 00000000..83c58525 +--- /dev/null ++++ b/arch/arm/mach-mstar/atags_to_fdt.c +@@ -0,0 +1,201 @@ ++#include ++#include "libfdt.h" ++ ++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) ++#define do_extend_cmdline 1 ++#else ++#define do_extend_cmdline 0 ++#endif ++ ++#define NR_BANKS 16 ++ ++static int node_offset(void *fdt, const char *node_path) ++{ ++ int offset = fdt_path_offset(fdt, node_path); ++ if (offset == -FDT_ERR_NOTFOUND) ++ offset = fdt_add_subnode(fdt, 0, node_path); ++ return offset; ++} ++#if 0 ++static int setprop(void *fdt, const char *node_path, const char *property, ++ uint32_t *val_array, int size) ++{ ++ int offset = node_offset(fdt, node_path); ++ if (offset < 0) ++ return offset; ++ return fdt_setprop(fdt, offset, property, val_array, size); ++} ++#endif ++ ++static int setprop_string(void *fdt, const char *node_path, ++ const char *property, const char *string) ++{ ++ int offset = node_offset(fdt, node_path); ++ if (offset < 0) ++ return offset; ++ return fdt_setprop_string(fdt, offset, property, string); ++} ++ ++static int setprop_cell(void *fdt, const char *node_path, ++ const char *property, uint32_t val) ++{ ++ int offset = node_offset(fdt, node_path); ++ if (offset < 0) ++ return offset; ++ return fdt_setprop_cell(fdt, offset, property, val); ++} ++ ++static const void *getprop(const void *fdt, const char *node_path, ++ const char *property, int *len) ++{ ++ int offset = fdt_path_offset(fdt, node_path); ++ ++ if (offset == -FDT_ERR_NOTFOUND) ++ return NULL; ++ ++ return fdt_getprop(fdt, offset, property, len); ++} ++#if 0 ++static uint32_t get_cell_size(const void *fdt) ++{ ++ int len; ++ uint32_t cell_size = 1; ++ const uint32_t *size_len = getprop(fdt, "/", "#size-cells", &len); ++ ++ if (size_len) ++ cell_size = fdt32_to_cpu(*size_len); ++ return cell_size; ++} ++#endif ++static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline) ++{ ++ char cmdline[COMMAND_LINE_SIZE]; ++ const char *fdt_bootargs; ++ char *ptr = cmdline; ++ int len = 0; ++ ++ /* copy the fdt command line into the buffer */ ++ fdt_bootargs = getprop(fdt, "/chosen", "bootargs", &len); ++ if (fdt_bootargs) ++ if (len < COMMAND_LINE_SIZE) { ++ memcpy(ptr, fdt_bootargs, len); ++ /* len is the length of the string ++ * including the NULL terminator */ ++ ptr += len - 1; ++ } ++ ++ /* and append the ATAG_CMDLINE */ ++ if (fdt_cmdline) { ++ len = strlen(fdt_cmdline); ++ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) { ++ *ptr++ = ' '; ++ memcpy(ptr, fdt_cmdline, len); ++ ptr += len; ++ } ++ } ++ *ptr = '\0'; ++ ++ setprop_string(fdt, "/chosen", "bootargs", cmdline); ++} ++ ++/* ++ * Convert and fold provided ATAGs into the provided FDT. ++ * ++ * REturn values: ++ * = 0 -> pretend success ++ * = 1 -> bad ATAG (may retry with another possible ATAG pointer) ++ * < 0 -> error from libfdt ++ */ ++int early_atags_to_fdt(void *atag_list, void *fdt, int total_space) ++{ ++ struct tag *atag = atag_list; ++ /* In the case of 64 bits memory size, need to reserve 2 cells for ++ * address and size for each bank */ ++#if 0 /* Ignore memory atag, always use dtb */ ++ uint32_t mem_reg_property[2 * 2 * NR_BANKS]; ++ int memcount = 0, memsize; ++#endif ++ int ret; ++ ++ /* make sure we've got an aligned pointer */ ++ if ((u32)atag_list & 0x3) ++ return 1; ++ ++ /* if we get a DTB here we're done already */ ++ if (*(u32 *)atag_list == fdt32_to_cpu(FDT_MAGIC)) ++ return 0; ++ ++ /* validate the ATAG */ ++ if (atag->hdr.tag != ATAG_CORE || ++ (atag->hdr.size != tag_size(tag_core) && ++ atag->hdr.size != 2)) ++ return 1; ++ ++ /* let's give it all the room it could need */ ++ ret = fdt_open_into(fdt, fdt, total_space); ++ if (ret < 0) ++ return ret; ++ ++ for_each_tag(atag, atag_list) { ++ if (atag->hdr.tag == ATAG_CMDLINE) { ++ /* Append the ATAGS command line to the device tree ++ * command line. ++ * NB: This means that if the same parameter is set in ++ * the device tree and in the tags, the one from the ++ * tags will be chosen. ++ */ ++ if (do_extend_cmdline) ++ merge_fdt_bootargs(fdt, ++ atag->u.cmdline.cmdline); ++ else ++ setprop_string(fdt, "/chosen", "bootargs", ++ atag->u.cmdline.cmdline); ++ } ++#if 0 /* Ignore memory atag, always use dtb */ ++ else if (atag->hdr.tag == ATAG_MEM) { ++ if (memcount >= sizeof(mem_reg_property)/4) ++ continue; ++ if (!atag->u.mem.size) ++ continue; ++ memsize = get_cell_size(fdt); ++ ++ if (memsize == 2) { ++ /* if memsize is 2, that means that ++ * each data needs 2 cells of 32 bits, ++ * so the data are 64 bits */ ++ uint64_t *mem_reg_prop64 = ++ (uint64_t *)mem_reg_property; ++ if (memcount >= (sizeof(mem_reg_property)/4)*2*2) ++ continue; ++ mem_reg_prop64[memcount++] = ++ cpu_to_fdt64(atag->u.mem.start); ++ mem_reg_prop64[memcount++] = ++ cpu_to_fdt64(atag->u.mem.size); ++ } else { ++ mem_reg_property[memcount++] = ++ cpu_to_fdt32(atag->u.mem.start); ++ mem_reg_property[memcount++] = ++ cpu_to_fdt32(atag->u.mem.size); ++ } ++ ++ } ++#endif ++ else if (atag->hdr.tag == ATAG_INITRD2) { ++ uint32_t initrd_start, initrd_size; ++ initrd_start = atag->u.initrd.start; ++ initrd_size = atag->u.initrd.size; ++ setprop_cell(fdt, "/chosen", "linux,initrd-start", ++ initrd_start); ++ setprop_cell(fdt, "/chosen", "linux,initrd-end", ++ initrd_start + initrd_size); ++ } ++ } ++#if 0 ++ if (memcount) { ++ setprop(fdt, "/memory", "reg", mem_reg_property, ++ 4 * memcount * memsize); ++ } ++#endif ++ ++ return fdt_pack(fdt); ++} +diff --git a/arch/arm/mach-mstar/cedric/Makefile b/arch/arm/mach-mstar/cedric/Makefile +new file mode 100644 +index 00000000..a1e68a7e +--- /dev/null ++++ b/arch/arm/mach-mstar/cedric/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++obj-y += cedric.o ++obj-$(CONFIG_SMP) += smp_platform.o smp_head.o ++obj-y += cedric.o reset.o +\ No newline at end of file +diff --git a/arch/arm/mach-mstar/cedric/cedric.c b/arch/arm/mach-mstar/cedric/cedric.c +new file mode 100644 +index 00000000..6811eb63 +--- /dev/null ++++ b/arch/arm/mach-mstar/cedric/cedric.c +@@ -0,0 +1,523 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cedric/registers.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#define CEDRIC_MIU0_BASE 0x40000000 ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define PERI_PHYS 0x16000000 ++#define PERI_VIRT (PERI_PHYS+PERI_OFFSET) //from IO_ADDRESS(x) ++#define PERI_OFFSET (MS_IO_OFFSET) ++#define PERI_SIZE 0x2000 ++ ++#define L2_CACHE_PHYS 0x15000000 ++#define L2_CACHE_VIRT (L2_CACHE_PHYS+L2_CACHE_OFFSET) ++#define L2_CACHE_OFFSET (MS_IO_OFFSET) ++#define L2_CACHE_SIZE 0x1000 ++ ++#define MS_DEVINFO_PHYS 0x40000000 ++#define MS_DEVINFO_VIRT 0xFE000000 ++#define MS_DEVINFO_OFFSET (MS_DEVINFO_VIRT-MS_DEVINFO_PHYS) ++#define MS_DEVINFO_SIZE 0x100000 ++ ++//#define IMI_PHYS 0xE0000000 ++//#define IMI_VIRT 0xF9000000 ++//#define INI_OFFSET (IMI_VIRT-IMI_PHYS) ++//#define IMI_SIZE 0x50000 ++ ++ ++ ++#define L2_LINEFILL 0 ++#define L2_PREFETCH 0 ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++static void __iomem * l2x0_base = (void __iomem *)(IO_ADDRESS(L2_CACHE_PHYS)); ++ ++extern void cedric_reset_cpu(int i); ++ ++#define PLATFORM_NAME PLATFORM_NAME_CEDRIC ++ ++static void cedric_restart(enum reboot_mode mode, const char *cmd) ++{ ++ cedric_reset_cpu(0); ++} ++ ++ ++/* IO tables */ ++static struct map_desc cedric_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ { ++ .virtual = IO_VIRT, ++ .pfn = __phys_to_pfn(IO_PHYS), ++ .length = IO_SIZE, ++ .type = MT_DEVICE ++ }, ++ ++ /* Define periphral physcial and virtual addresses */ ++ { ++ .virtual = PERI_VIRT, ++ .pfn = __phys_to_pfn(PERI_PHYS), ++ .length = PERI_SIZE, ++ .type = MT_DEVICE ++ }, ++ ++ { ++ .virtual = L2_CACHE_VIRT, ++ .pfn = __phys_to_pfn(L2_CACHE_PHYS), ++ .length = L2_CACHE_SIZE, ++ .type = MT_DEVICE, ++ }, ++ ++ { ++ .virtual = MS_DEVINFO_VIRT, ++ .pfn = __phys_to_pfn(MS_DEVINFO_PHYS), ++ .length = MS_DEVINFO_SIZE, ++ .type = MT_DEVICE, ++ }, ++ ++ ++ ++// /*IMI physical and virtual*/ ++// { ++// .virtual = IMI_VIRT, ++// .pfn = __phys_to_pfn(IMI_PHYS), ++// .length = IMI_SIZE, ++// .type = MT_DEVICE, ++// }, ++ ++}; ++ ++ ++ ++ ++typedef struct _DEVINFO{ ++ unsigned char header[8]; ++ unsigned short board_name; ++ unsigned char package_name; ++ unsigned char miu0_type; ++ unsigned char miu0_size; ++ unsigned char miu1_type; ++ unsigned char miu1_size; ++ unsigned char panel_type; ++ unsigned char rtk_flag; ++ unsigned char boot_device; ++ unsigned char uartpad_select; ++ unsigned char cpu_speed; ++ unsigned char rom_flag; ++ unsigned char customer_flag[4]; ++ unsigned char rtk_qst_cfg; ++}DEVINFO_st; ++ ++//address layout ++#define DEVINFO_PHYS_ADDR 0x4003F800 ++//#define DEVINFO_SIZE 0x800 ++ ++ ++//static MS_MEMCFG memcfg; ++static MS_BOOT_DEV_TYPE cedric_boot_type; ++ ++ ++static const char *cedric_dt_compat[] __initconst = { ++ "mstar,cedric", ++ NULL, ++}; ++ ++static void __init cedric_map_io(void) ++{ ++ iotable_init(cedric_io_desc, ARRAY_SIZE(cedric_io_desc)); ++ ++} ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++#define _BIT(x) (1<<(x)) ++ ++static DEFINE_SPINLOCK(cedric_l2prefetch_lock); ++ ++static void cedric_uart_disable_line(int line) ++{ ++ if(line == 0) ++ { ++ CLRREG16(BASE_REG_PMMISC_PA+REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ CLRREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT2); ++ } ++ else if(line==2) ++ { ++ CLRREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT3); ++ } ++ else if(line==3) ++ { ++ CLRREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT4); ++ } ++ else if(line==4) ++ { ++ CLRREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT5); ++ } ++ else if(line==5) ++ { ++ CLRREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT6); ++ } ++ ++} ++static void cedric_uart_enable_line(int line) ++{ ++ if(line == 0) ++ { ++ SETREG16(BASE_REG_PMMISC_PA+REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ if((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_53)& 0x00F0) == 0x00F0) ++ { ++ OUTREG16(BASE_REG_CHIPTOP_PA + REG_ID_53,((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_53)& 0xFF0F)|0x0030)); ++ } ++ SETREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT2); ++ } ++ else if(line==2) ++ { ++ if((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_53)& 0x0F00) == 0x0F00) ++ { ++ OUTREG16(BASE_REG_CHIPTOP_PA + REG_ID_53,((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_53)& 0xF0FF)|0x0400)); ++ } ++ SETREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT3); ++ } ++ else if(line==3) ++ { ++ if((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_53)& 0xF000) == 0xF000) ++ { ++ OUTREG16(BASE_REG_CHIPTOP_PA + REG_ID_53,((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_53)& 0x0FFF)|0x5000)); ++ } ++ SETREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT4); ++ } ++ else if(line==4) ++ { ++ if((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_54)& 0x000F) == 0x000F) ++ { ++ OUTREG16(BASE_REG_CHIPTOP_PA + REG_ID_54,((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_54)& 0xFFF0)|0x0000)); ++ } ++ SETREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT5); ++ } ++ else if(line==5) ++ { ++ if((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_54)& 0x00F0) == 0x00F0) ++ { ++ OUTREG16(BASE_REG_CHIPTOP_PA + REG_ID_54,((INREG16(BASE_REG_CHIPTOP_PA + REG_ID_54)& 0xFF0F)|0x0010)); ++ } ++ SETREG16(BASE_REG_CHIPGPIO1_PA + REG_ID_03,BIT6); ++ } ++ ++} ++ ++static int cedric_get_device_id(void) ++{ ++ return (int)(INREG16(0x1F003C00) & 0x00FF); ++} ++ ++static int cedric_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(0x1F003C00+0x67*4)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++ ++static int __init cedric_early_devinfo_config(void) ++{ ++ DEVINFO_st *devinfo; ++ devinfo = (DEVINFO_st*)(DEVINFO_PHYS_ADDR+MS_DEVINFO_OFFSET); // start address: 30K, size: 2K ++ // check header ++ ++ if (devinfo->header[0]!='D' || devinfo->header[1]!='E' || devinfo->header[2]!='V' || devinfo->header[3]!='I' || ++ devinfo->header[4]!='N' || devinfo->header[5]!='F' || devinfo->header[6]!='O' || devinfo->header[7]!='.') ++ { ++ pr_info("***********************************************************\n"); ++ pr_info("* [MS:DEVINFO] header check failed !!! *\n"); ++ pr_info("* Please program DEVINFO section. *\n"); ++ pr_info("***********************************************************\n"); ++ ++ } ++ else ++ { ++// unsigned int m0size=0; ++// unsigned int i; ++ ++ pr_info("[MS:DEVINFO] header check passed !!\n"); ++ ++ ++ ++ cedric_boot_type=(MS_BOOT_DEV_TYPE)devinfo->boot_device; ++// panel_type=(DEVINFO_PANEL_TYPE)devinfo->panel_type; ++// board_type = (DEVINFO_BOARD_TYPE)devinfo->board_name; ++// rtk_flag = (DEVINFO_RTK_FLAG)devinfo->rtk_flag; ++// rtk_qst_cfg = devinfo->rtk_qst_cfg; ++ ++// rtkinfo_init(); ++ ++ } ++ ++ return 0; ++ ++} ++ ++ ++static void cedric_chip_flush_miu_pipe(void) ++{ ++ unsigned long dwLockFlag = 0; ++ unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&cedric_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD203114) = 0x0; ++ *(volatile unsigned short *)(0xFD203114) = 0x1; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD203140); ++ dwReadData &= _BIT(12); //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&cedric_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static u64 cedric_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - CEDRIC_MIU0_BASE); ++} ++ ++static u64 cedric_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + CEDRIC_MIU0_BASE); ++} ++ ++ ++static int cedric_outer_cache_is_enable(void) ++{ ++ ++ return (readl_relaxed(l2x0_base + L2X0_CTRL) & 1); ++} ++ ++struct soc_device_attribute cedric_soc_dev_attr; ++extern struct outer_cache_fns outer_cache; ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int cedric_get_boot_type(void) ++{ ++ return (int)cedric_boot_type; ++} ++ ++static char cedric_platform_name[]=PLATFORM_NAME_CEDRIC; ++ ++static char* cedric_get_platform_name(void) ++{ ++ return cedric_platform_name; ++} ++ ++ ++static unsigned long long cedric_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int cedric_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++// Define PM_GPIO registers ++#define REG_PM_GPIO_BASE 0xFD001E00 ++#define REG_PM_GPIO_00H (REG_PM_GPIO_BASE + 0x0000*4) ++ ++#define REG_PM_MISC_BASE 0xFD005C00 ++#define REG_PM_MISC_21H (REG_PM_MISC_BASE + 0x0021*4) ++ ++static int cedric_ir_enable(int param) ++{ ++ ++ ++ (*(volatile u32 *)(REG_PM_GPIO_00H)) |= 0x0008; ++ (*(volatile u32 *)(REG_PM_MISC_21H)) &= 0xfe1f; ++ ++ return 0; ++} ++ ++static int cedric_chip_function_set(int function_id, int param) ++{ ++ int res=0; ++ ++ printk("[%s]CHIP_FUNCTION SET. ID=%d, param=%d\n",PLATFORM_NAME,function_id,param); ++ switch (function_id) ++ { ++ ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ cedric_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ cedric_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ cedric_ir_enable(param); ++ break; ++ default: ++ res=-1; ++ printk(KERN_ERR"[%s]Unsupport CHIP_FUNCTION!! ID=%d\n",PLATFORM_NAME,function_id); ++ ++ } ++ ++ return res; ++} ++ ++static void __init cedric_init_early(void) ++{ ++ struct ms_chip *chip=NULL; ++ ++ ms_chip_init_default(); ++ ++ cedric_early_devinfo_config(); ++ ++ chip=ms_chip_get(); ++ ++ ++ chip->chip_flush_miu_pipe=cedric_chip_flush_miu_pipe; ++ chip->phys_to_miu=cedric_phys_to_MIU; ++ chip->miu_to_phys=cedric_MIU_to_phys; ++ ++ chip->cache_outer_is_enabled=cedric_outer_cache_is_enable; ++// ++ ++ chip->chip_get_device_id=cedric_get_device_id; ++ chip->chip_get_revision=cedric_get_revision; ++ chip->chip_get_boot_dev_type=cedric_get_boot_type; ++ chip->chip_get_platform_name=cedric_get_platform_name; ++ ++ chip->chip_get_riu_phys=cedric_chip_get_riu_phys; ++ chip->chip_get_riu_size=cedric_chip_get_riu_size; ++ chip->chip_function_set=cedric_chip_function_set; ++ ++} ++ ++ ++ ++extern MS_VERSION LX_VERSION; ++static void __init cedric_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ char ver[33]={0}; ++ memcpy(ver,(void *)&LX_VERSION,32); ++ ++ pr_info("[cedric_init_machine]"); ++ pr_info("%s\n",ver); ++ ++ ++ ++#ifdef CONFIG_MS_L2X0_PATCH ++ outer_cache.flush_MIU_pipe=&cedric_chip_flush_miu_pipe; ++#endif ++ ++ ++#ifdef CONFIG_CACHE_L2X0 ++ { ++ //void __iomem * l2x0_base = (void __iomem *)(IO_ADDRESS(L2_CACHE_PHYS)); ++#if L2_LINEFILL ++ val = L2_CACHE_read( L2_CACHE_PHYS + PREFETCH_CTL_REG ); ++ L2_CACHE_write(( val | DOUBLE_LINEFILL_ENABLE | LINEFILL_WRAP_DISABLE ), L2_CACHE_PHYS + PREFETCH_CTL_REG); ++#endif ++ ++#if L2_PREFETCH ++ val = L2_CACHE_read( L2_CACHE_PHYS + PREFETCH_CTL_REG ); ++ L2_CACHE_write(( val | I_PREFETCH_ENABLE | D_PREFETCH_ENABLE | PREFETCH_OFFSET ), L2_CACHE_PHYS + PREFETCH_CTL_REG ); ++#endif ++ ++ /* set RAM latencies to 1 cycle for this core tile. */ ++ writel(0x113, l2x0_base + L310_TAG_LATENCY_CTRL); ++ writel(0x111, l2x0_base + L310_DATA_LATENCY_CTRL); ++ ++ l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff); ++ } ++#endif ++ ++ ++ ++ ++ ++ cedric_soc_dev_attr.family = kasprintf(GFP_KERNEL, cedric_platform_name); ++ cedric_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", cedric_get_revision()); ++ cedric_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", cedric_get_device_id()); ++ cedric_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ ++ soc_dev = soc_device_register(&cedric_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)cedric_soc_dev_attr.family); ++ kfree((void *)cedric_soc_dev_attr.revision); ++ kfree((void *)cedric_soc_dev_attr.soc_id); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++ ++ ++ out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++} ++ ++ ++ ++ ++ ++ ++#ifdef CONFIG_SMP ++extern struct smp_operations cedric_smp_ops; ++#endif ++ ++DT_MACHINE_START(MS_CEDRIC_DT, "MStar Cedric (Flattened Device Tree)") ++ .dt_compat = cedric_dt_compat, ++ .map_io =cedric_map_io, ++ .init_machine = cedric_init_machine, ++ .init_early = cedric_init_early, ++ .restart = cedric_restart, ++#ifdef CONFIG_SMP ++ .smp = smp_ops(cedric_smp_ops), ++#endif ++// .init_time = ms_init_timer, ++// ++MACHINE_END +diff --git a/arch/arm/mach-mstar/cedric/reset.S b/arch/arm/mach-mstar/cedric/reset.S +new file mode 100644 +index 00000000..09edd249 +--- /dev/null ++++ b/arch/arm/mach-mstar/cedric/reset.S +@@ -0,0 +1,21 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++ ++ .align 5 ++.globl cedric_reset_cpu ++cedric_reset_cpu: ++ ++ mov r3, #0x0000 ++ ldr r1, =0xFD005C80 ++ str r3, [r1] ++ mov r3, #0x0079 ++ ldr r1, =0xFD005CB8 ++ str r3, [r1] ++ nop ++ nop ++ nop ++ nop ++ ++_loop_forever: ++ b _loop_forever +diff --git a/arch/arm/mach-mstar/cedric/smp_head.S b/arch/arm/mach-mstar/cedric/smp_head.S +new file mode 100644 +index 00000000..188754b8 +--- /dev/null ++++ b/arch/arm/mach-mstar/cedric/smp_head.S +@@ -0,0 +1,42 @@ ++/* ++ * copied from linux/arch/arm/plat-versatile/headsmp.S ++ * ++ * Copyright (c) 2003 ARM Limited ++ * All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++ ++ __CPUINIT ++ ++/* ++ * Realview/Versatile Express specific entry point for secondary CPUs. ++ * This provides a "holding pen" into which all secondary cores are held ++ * until we're ready for them to initialise. ++ */ ++ENTRY(cedric_secondary_startup) ++ mrc p15, 0, r0, c0, c0, 5 ++ and r0, r0, #15 ++ adr r4, 1f ++ ldmia r4, {r5, r6} ++ sub r4, r4, r5 ++ add r6, r6, r4 ++pen: ldr r7, [r6] ++ cmp r7, r0 ++ bne pen ++ ++ /* ++ * we've been released from the holding pen: secondary_stack ++ * should now contain the SVC stack for this core ++ */ ++ b secondary_startup ++ ++ ++ .align 2 ++1: .long . ++ .long pen_release ++ENDPROC(cedric_secondary_startup) +diff --git a/arch/arm/mach-mstar/cedric/smp_platform.c b/arch/arm/mach-mstar/cedric/smp_platform.c +new file mode 100644 +index 00000000..1582d766 +--- /dev/null ++++ b/arch/arm/mach-mstar/cedric/smp_platform.c +@@ -0,0 +1,353 @@ ++/* ++ * cedric_smp.c ++ * ++ * Created on: 2015�~4��30�� ++ * Author: Administrator ++ */ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++ ++extern int cedric_platform_cpu_kill(unsigned int cpu); ++extern void cedric_platform_cpu_die(unsigned int cpu); ++extern int cedric_platform_cpu_disable(unsigned int cpu); ++ ++extern volatile int __cpuinitdata pen_release; ++extern void Chip_Flush_CacheAll(void); ++ ++#define SCU_PHYS 0x16000000 ++ ++ ++static inline void cpu_enter_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk("ms_hotplug.c cpu_enter_lowpower: in\n"); ++ ++ flush_cache_all(); ++ asm volatile( ++ " mcr p15, 0, %1, c7, c5, 0\n" ++ " mcr p15, 0, %1, c7, c10, 4\n" ++ /* ++ * Turn off coherency ++ */ ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " bic %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ " mrc p15, 0, %0, c1, c0, 0\n" ++ " bic %0, %0, %2\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ : "=&r" (v) ++ : "r" (0), "Ir" (CR_C) ++ : "cc"); ++ ++ printk("ms_hotplug.c cpu_enter_lowpower: out\n"); ++} ++ ++static inline void cpu_leave_lowpower(void) ++{ ++ unsigned int v; ++ ++ printk("ms_hotplug.c cpu_leave_lowpower: in\n"); ++ ++ asm volatile( "mrc p15, 0, %0, c1, c0, 0\n" ++ " orr %0, %0, %1\n" ++ " mcr p15, 0, %0, c1, c0, 0\n" ++ " mrc p15, 0, %0, c1, c0, 1\n" ++ " orr %0, %0, #0x20\n" ++ " mcr p15, 0, %0, c1, c0, 1\n" ++ : "=&r" (v) ++ : "Ir" (CR_C) ++ : "cc"); ++ ++ printk("ms_hotplug.c cpu_leave_lowpower: out\n"); ++} ++ ++static inline void platform_do_lowpower(unsigned int cpu, int *spurious) ++{ ++ //printk("ms_hotplug.c platform_do_lowpower: before %d cpu go into WFI, spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * there is no power-control hardware on this platform, so all ++ * we can do is put the core into WFI; this is safe as the calling ++ * code will have already disabled interrupts ++ */ ++ for (;;) { ++ /* ++ * here's the WFI ++ */ ++ asm(".word 0xe320f003\n" ++ : ++ : ++ : "memory", "cc"); ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up, spurious =%d \n", cpu, *spurious); ++ ++ if (pen_release == cpu_logical_map(cpu)) { ++ /* ++ * OK, proper wakeup, we're done ++ */ ++ break; ++ } ++ ++ //printk("ms_hotplug.c platform_do_lowpower: %d cpu wake up error(cpuID != pen_release), spurious =%d \n", cpu, *spurious); ++ ++ /* ++ * Getting here, means that we have come out of WFI without ++ * having been woken up - this shouldn't happen ++ * ++ * Just note it happening - when we're woken, we can report ++ * its occurrence. ++ */ ++ (*spurious)++; ++ } ++} ++ ++int cedric_platform_cpu_kill(unsigned int cpu) ++{ ++ return 1; ++} ++ ++/* ++ * platform-specific code to shutdown a CPU ++ * ++ * Called with IRQs disabled ++ */ ++void __ref cedric_platform_cpu_die(unsigned int cpu) ++{ ++ int spurious = 0; ++ ++ //printk("ms_hotplug.c platform_cpu_die: in cpu = %d \n", cpu); ++ ++ Chip_Flush_CacheAll(); ++ ++ /* ++ * we're ready for shutdown now, so do it ++ */ ++ //cpu_enter_lowpower(); ++ platform_do_lowpower(cpu, &spurious); ++ ++ /* ++ * bring this CPU back into the world of cache ++ * coherency, and then restore interrupts ++ */ ++ //cpu_leave_lowpower(); ++ ++ printk("ms_hotplug.c platform_cpu_die: out cpu = %d \n", cpu); ++ ++ if (spurious) ++ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious); ++} ++ ++int cedric_platform_cpu_disable(unsigned int cpu) ++{ ++ /* ++ * we don't allow CPU 0 to be shutdown (it is still too special ++ * e.g. clock tick interrupts) ++ */ ++ ++ printk("ms_hotplug.c platform_cpu_disable: in cpu = %d \n", cpu); ++ return cpu == 0 ? -EPERM : 0; ++} ++ ++ ++/* ++ * control for which core is the next to come out of the secondary ++ * boot "holding pen" ++ */ ++//volatile int __cpuinitdata pen_release = -1; ++ ++static void __iomem *scu_base_addr(void) ++{ ++ return (void __iomem *)(IO_ADDRESS(SCU_PHYS)); ++} ++ ++/* ++ * Write pen_release in a way that is guaranteed to be visible to all ++ * observers, irrespective of whether they're taking part in coherency ++ * or not. This is necessary for the hotplug code to work reliably. ++ */ ++static void __cpuinit write_pen_release(int val) ++{ ++ pen_release = val; ++ smp_wmb(); ++ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); ++ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); ++} ++ ++static DEFINE_SPINLOCK(boot_lock); ++ ++void __cpuinit cedric_secondary_init(unsigned int cpu) ++{ ++ ++ /* ++ * if any interrupts are already enabled for the primary ++ * core (e.g. timer irq), then they will not have been enabled ++ * for us: do so ++ */ ++ //gic_secondary_init(0); ++ ++ /* ++ * let the primary processor know we're out of the ++ * pen, then head off into the C entry point ++ */ ++ write_pen_release(-1); ++ ++ /* ++ * Synchronise with the boot thread. ++ */ ++ spin_lock(&boot_lock); ++ spin_unlock(&boot_lock); ++} ++ ++ ++int __cpuinit cedric_boot_secondary(unsigned int cpu, struct task_struct *idle) ++{ ++ unsigned long timeout; ++ /* ++ * Set synchronisation state between this boot processor ++ * and the secondary one ++ */ ++ spin_lock(&boot_lock); ++ ++ /* ++ * This is really belt and braces; we hold unintended secondary ++ * CPUs in the holding pen until we're ready for them. However, ++ * since we haven't sent them a soft interrupt, they shouldn't ++ * be there. ++ */ ++ write_pen_release(cpu_logical_map(cpu)); ++ ++ /* ++ * Send the secondary CPU a soft interrupt, thereby causing ++ * the boot monitor to read the system wide flags register, ++ * and branch to the address found there. ++ */ ++ arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ++ ++ timeout = jiffies + (1 * HZ); ++ while (time_before(jiffies, timeout)) { ++ smp_rmb(); ++ if (pen_release == -1) ++ break; ++ ++ udelay(10); ++ } ++ ++ /* ++ * now the secondary core is starting up let it run its ++ * calibrations, then wait for it to finish ++ */ ++ spin_unlock(&boot_lock); ++ ++ return pen_release != -1 ? -ENOSYS : 0; ++} ++ ++ ++ ++#include ++#include ++ ++#define SECOND_START_ADDR_HI 0x1F206740 ++#define SECOND_START_ADDR_LO 0x1F206744 ++//#define SECOND_MAGIC_NUMBER_ADRESS 0xC0008000 ++//#define SECOND_START_ADDR 0xC0008004 ++ ++extern void cedric_secondary_startup(void); ++ ++#define SCU_CTRL 0x00 ++ ++void __init cedric_smp_prepare_cpus(unsigned int max_cpus) ++{ ++ int i; ++ u32 scu_ctrl; ++ printk(KERN_ERR "[%s]\n",__FUNCTION__); ++ /* ++ * Initialise the present map, which describes the set of CPUs ++ * actually populated at the present time. ++ */ ++ for (i = 0; i < max_cpus; i++) ++ { ++ set_cpu_present(i, true); ++ } ++ ++#if defined(CONFIG_CEDRIC_MASTER0_ONLY_PATCH) ++ __raw_writel(0xe0000000, scu_base_addr() + 0x40); ++ __raw_writel(0xe0100000, scu_base_addr() + 0x44); ++ scu_ctrl = __raw_readl(scu_base_addr() + SCU_CTRL); ++ scu_ctrl |= 0x02; ++ __raw_writel(scu_ctrl, scu_base_addr() + SCU_CTRL); ++ printk(KERN_WARNING"SCU: Filter to Master0 only\n"); ++#endif ++ ++ scu_enable(scu_base_addr()); // SCU PA = 0x16000000 ++ ++ ++ ++ /* ++ * Write the address of secondary startup into the ++ * system-wide flags register. The boot monitor waits ++ * until it receives a soft interrupt, and then the ++ * secondary CPU branches to this address. ++ */ ++ ++ do{ ++ OUTREG16(SECOND_START_ADDR_LO,(virt_to_phys(cedric_secondary_startup) & 0xFFFF)); ++ }while(INREG16(SECOND_START_ADDR_LO)!= (virt_to_phys(cedric_secondary_startup) & 0xFFFF)); ++ ++ ++ do{ ++ OUTREG16(SECOND_START_ADDR_HI,(virt_to_phys(cedric_secondary_startup)>>16)); ++ }while(INREG16(SECOND_START_ADDR_HI)!=(virt_to_phys(cedric_secondary_startup)>>16)); ++ ++ __cpuc_flush_kern_all(); ++ ++ ++} ++ ++void __init cedric_smp_init_cpus(void) ++{ ++ ++ void __iomem *scu_base =scu_base_addr(); ++ unsigned int i, ncores; ++ ++ ncores = scu_base ? scu_get_core_count(scu_base) : 1; ++ ++ for (i = 0; i < 2; i++) ++ { ++ set_cpu_possible(i, true); ++ } ++} ++ ++ ++struct smp_operations __initdata cedric_smp_ops = { ++ .smp_init_cpus = cedric_smp_init_cpus, ++ .smp_prepare_cpus = cedric_smp_prepare_cpus, ++ .smp_secondary_init = cedric_secondary_init, ++ .smp_boot_secondary = cedric_boot_secondary, ++ ++ .cpu_kill = cedric_platform_cpu_kill, ++ .cpu_die = cedric_platform_cpu_die, ++ .cpu_disable = cedric_platform_cpu_disable, ++ ++}; ++ +diff --git a/arch/arm/mach-mstar/chicago/Makefile b/arch/arm/mach-mstar/chicago/Makefile +new file mode 100644 +index 00000000..8e1872bb +--- /dev/null ++++ b/arch/arm/mach-mstar/chicago/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++obj-y += chicago.o ++obj-y += reset.o +diff --git a/arch/arm/mach-mstar/chicago/chicago.c b/arch/arm/mach-mstar/chicago/chicago.c +new file mode 100644 +index 00000000..efce8cc4 +--- /dev/null ++++ b/arch/arm/mach-mstar/chicago/chicago.c +@@ -0,0 +1,301 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "chicago/registers.h" ++#include "chicago/irqs.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++#define CHICAGO_MIU0_BASE 0x20000000 ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++ ++//#define IMI_PHYS 0xA0000000 ++//#define IMI_VIRT 0xF9000000 ++//#define INI_OFFSET (IMI_VIRT-IMI_PHYS) ++//#define IMI_SIZE 0x50000 ++ ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++extern void chicago_reset_cpu(int i); ++ ++ ++#define PLATFORM_NAME PLATFORM_NAME_CHICAGO ++ ++static void chicago_restart(enum reboot_mode mode, const char *cmd) ++{ ++ chicago_reset_cpu(0); ++} ++ ++ ++/* IO tables */ ++static struct map_desc chicago_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ { ++ .virtual = IO_VIRT, ++ .pfn = __phys_to_pfn(IO_PHYS), ++ .length = IO_SIZE, ++ .type = MT_DEVICE ++ }, ++ ++/* ++ { ++ .virtual = PERI_VIRT, ++ .pfn = __phys_to_pfn(PERI_PHYS), ++ .length = PERI_SIZE, ++ .type = MT_DEVICE ++ }, ++*/ ++ ++/* ++ { ++ .virtual = IMI_VIRT, ++ .pfn = __phys_to_pfn(IMI_PHYS), ++ .length = IMI_SIZE, ++ .type = MT_DEVICE, ++ }, ++*/ ++}; ++ ++ ++static const char *chicago_dt_compat[] __initconst = { ++ "mstar,chicago", ++ NULL, ++}; ++ ++static void __init chicago_map_io(void) ++{ ++ iotable_init(chicago_io_desc, ARRAY_SIZE(chicago_io_desc)); ++ ++} ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++ ++static DEFINE_SPINLOCK(chicago_l2prefetch_lock); ++ ++static void chicago_uart_disable_line(int line) ++{ ++ if(line == 0) ++ { ++ //CLRREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT0); ++ } ++ else if(line == 1) ++ { ++ CLRREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT1); ++ } ++ else if(line==2) ++ { ++ CLRREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT3); ++ } ++ else if(line==3) ++ { ++ CLRREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT5); ++ } ++} ++ ++static void chicago_uart_enable_line(int line) ++{ ++ if(line == 0) ++ { ++ //SETREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT0); ++ } ++ else if(line == 1) ++ { ++ SETREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT1); ++ } ++ else if(line==2) ++ { ++ SETREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT3); ++ } ++ else if(line==3) ++ { ++ SETREG16(BASE_REG_PADTOP_PA + REG_ID_03, BIT5); ++ } ++} ++ ++static int chicago_get_device_id(void) ++{ ++ return (int)DEVICE_ID_CHICAGO; ++} ++ ++static int chicago_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_CHIPTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++ ++static void chicago_chip_flush_miu_pipe(void) ++{ ++ unsigned long dwLockFlag = 0; ++ unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&chicago_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD002114) = 0x0; ++ *(volatile unsigned short *)(0xFD002114) = 0x1; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD002140); ++ dwReadData &= BIT(12); //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&chicago_l2prefetch_lock, dwLockFlag); ++} ++ ++static u64 chicago_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - CHICAGO_MIU0_BASE); ++} ++ ++static u64 chicago_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + CHICAGO_MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute chicago_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int chicago_get_boot_type(void) ++{ ++ //spade: to be finished... ++ return 0; ++} ++ ++static char chicago_platform_name[]=PLATFORM_NAME_CHICAGO; ++ ++char* chicago_get_platform_name(void) ++{ ++ return chicago_platform_name; ++} ++ ++static unsigned long long chicago_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int chicago_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++int chicago_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("[%s]CHIP_FUNCTION SET. ID=%d, param=%d\n", PLATFORM_NAME, function_id, param); ++ ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ chicago_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ chicago_uart_disable_line(param); ++ break; ++ ++ default: ++ printk(KERN_ERR"[%s]Unsupport CHIP_FUNCTION!! ID=%d\n", PLATFORM_NAME, function_id); ++ ++ } ++ ++ ++ ++ return res; ++} ++ ++static void __init chicago_init_early(void) ++{ ++ struct ms_chip *chip=NULL; ++ ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ ++ chip->chip_flush_miu_pipe=chicago_chip_flush_miu_pipe; ++ chip->phys_to_miu=chicago_phys_to_MIU; ++ chip->miu_to_phys=chicago_MIU_to_phys; ++ chip->chip_get_device_id=chicago_get_device_id; ++ chip->chip_get_revision=chicago_get_revision; ++ chip->chip_get_boot_dev_type=chicago_get_boot_type; ++ chip->chip_get_platform_name=chicago_get_platform_name; ++ chip->chip_get_riu_phys=chicago_chip_get_riu_phys; ++ chip->chip_get_riu_size=chicago_chip_get_riu_size; ++ ++ chip->chip_function_set=chicago_chip_function_set; ++} ++ ++static void __init chicago_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("[chicago_init_machine]\n"); ++ ++ chicago_soc_dev_attr.family = kasprintf(GFP_KERNEL, chicago_platform_name); ++ chicago_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", chicago_get_revision()); ++ chicago_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", chicago_get_device_id()); ++ ++ soc_dev = soc_device_register(&chicago_soc_dev_attr); ++ if (IS_ERR(soc_dev)) ++ { ++ kfree((void *)chicago_soc_dev_attr.family); ++ kfree((void *)chicago_soc_dev_attr.revision); ++ kfree((void *)chicago_soc_dev_attr.soc_id); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++} ++ ++ ++DT_MACHINE_START(MS_CHICAGO_DT, "MStar Chicago (Flattened Device Tree)") ++ .dt_compat = chicago_dt_compat, ++ .map_io = chicago_map_io, ++ .init_machine = chicago_init_machine, ++ .init_early = chicago_init_early, ++ .restart = chicago_restart, ++// .init_time = ms_init_timer, ++// .init_irq = chicago_init_irq, ++ .nr_irqs = CHICAGO_NR_IRQS, ++MACHINE_END +diff --git a/arch/arm/mach-mstar/chicago/reset.S b/arch/arm/mach-mstar/chicago/reset.S +new file mode 100644 +index 00000000..e508b018 +--- /dev/null ++++ b/arch/arm/mach-mstar/chicago/reset.S +@@ -0,0 +1,21 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++ ++ .align 5 ++.globl chicago_reset_cpu ++chicago_reset_cpu: ++ ++ mov r3, #0x00FF ++ ldr r1, =0xFD003C18 ++ str r3, [r1] ++ mov r3, #0x0079 ++ ldr r1, =0xFD003C18 ++ str r3, [r1] ++ nop ++ nop ++ nop ++ nop ++ ++_loop_forever: ++ b _loop_forever +diff --git a/arch/arm/mach-mstar/fdt.h b/arch/arm/mach-mstar/fdt.h +new file mode 100644 +index 00000000..48ccfd91 +--- /dev/null ++++ b/arch/arm/mach-mstar/fdt.h +@@ -0,0 +1,60 @@ ++#ifndef _FDT_H ++#define _FDT_H ++ ++#ifndef __ASSEMBLY__ ++ ++struct fdt_header { ++ uint32_t magic; /* magic word FDT_MAGIC */ ++ uint32_t totalsize; /* total size of DT block */ ++ uint32_t off_dt_struct; /* offset to structure */ ++ uint32_t off_dt_strings; /* offset to strings */ ++ uint32_t off_mem_rsvmap; /* offset to memory reserve map */ ++ uint32_t version; /* format version */ ++ uint32_t last_comp_version; /* last compatible version */ ++ ++ /* version 2 fields below */ ++ uint32_t boot_cpuid_phys; /* Which physical CPU id we're ++ booting on */ ++ /* version 3 fields below */ ++ uint32_t size_dt_strings; /* size of the strings block */ ++ ++ /* version 17 fields below */ ++ uint32_t size_dt_struct; /* size of the structure block */ ++}; ++ ++struct fdt_reserve_entry { ++ uint64_t address; ++ uint64_t size; ++}; ++ ++struct fdt_node_header { ++ uint32_t tag; ++ char name[0]; ++}; ++ ++struct fdt_property { ++ uint32_t tag; ++ uint32_t len; ++ uint32_t nameoff; ++ char data[0]; ++}; ++ ++#endif /* !__ASSEMBLY */ ++ ++#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ ++#define FDT_TAGSIZE sizeof(uint32_t) ++ ++#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ ++#define FDT_END_NODE 0x2 /* End node */ ++#define FDT_PROP 0x3 /* Property: name off, ++ size, content */ ++#define FDT_NOP 0x4 /* nop */ ++#define FDT_END 0x9 ++ ++#define FDT_V1_SIZE (7*sizeof(uint32_t)) ++#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(uint32_t)) ++#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(uint32_t)) ++#define FDT_V16_SIZE FDT_V3_SIZE ++#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(uint32_t)) ++ ++#endif /* _FDT_H */ +diff --git a/arch/arm/mach-mstar/infinity/Makefile b/arch/arm/mach-mstar/infinity/Makefile +new file mode 100644 +index 00000000..a79ee6df +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity/Makefile +@@ -0,0 +1,6 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++obj-y += infinity.o ++obj-y += reset.o ++obj-y += pm.o ++obj-y += sram.o +\ No newline at end of file +diff --git a/arch/arm/mach-mstar/infinity/infinity.c b/arch/arm/mach-mstar/infinity/infinity.c +new file mode 100644 +index 00000000..d505f39d +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity/infinity.c +@@ -0,0 +1,945 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "infinity/registers.h" ++#include "infinity/mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++/* IO tables */ ++static struct map_desc infinity_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ //{IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *infinity_dt_compat[] __initconst = { ++ "mstar,infinity", ++ NULL, ++}; ++ ++static void __init infinity_map_io(void) ++{ ++ iotable_init(infinity_io_desc, ARRAY_SIZE(infinity_io_desc)); ++} ++ ++#define PLATFORM_NAME PLATFORM_NAME_INFINITY ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init infinity_init_irqchip(void); ++extern void infinity_restart(enum reboot_mode mode, const char *cmd); ++extern struct timecounter *arch_timer_get_timecounter(void); ++ ++ ++static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(infinity_l2prefetch_lock); ++ ++static void infinity_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void infinity_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int infinity_get_device_id(void) ++{ ++ return (int)(INREG16(0x1F003C00) & 0x00FF);; ++} ++ ++static int infinity_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++ ++static void infinity_chip_flush_miu_pipe(void) ++{ ++ unsigned long dwLockFlag = 0; ++ unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&infinity_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x0; ++ *(volatile unsigned short *)(0xFD204414) = 0x1; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&infinity_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static u64 infinity_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - INFINITY_MIU0_BASE); ++} ++ ++static u64 infinity_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + INFINITY_MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute infinity_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int infinity_get_storage_type(void) ++{ ++ u8 type = ((INREG16(BASE_REG_DIDKEY_PA + 0x70) >> 4) & 0x3); ++ ++ if(1 == type) ++ return (int)MS_STORAGE_NAND; ++ else if(2 == type) ++ return (int)MS_STORAGE_NOR; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int infinity_get_package_type(void) ++{ ++ if(!strcmp(&infinity_soc_dev_attr.machine[8], "MSC316D")) ++ return MS_PACKAGE_BGA; ++ else if(!strcmp(&infinity_soc_dev_attr.machine[8], "MSC316Q")) ++ return MS_PACKAGE_BGA_256M; ++ else if(!strcmp(&infinity_soc_dev_attr.machine[8], "MSC315")) ++ return MS_PACKAGE_QFP; ++ else if(!strcmp(&infinity_soc_dev_attr.machine[8], "MSC313")) ++ return MS_PACKAGE_QFN; ++ else ++ { ++ printk(KERN_ERR "** ERROR ** Machine name [%s] not support\n", infinity_soc_dev_attr.machine); ++ return MS_PACKAGE_UNKNOWN; ++ } ++} ++static char infinity_platform_name[]=PLATFORM_NAME_INFINITY; ++ ++char* infinity_get_platform_name(void) ++{ ++ return infinity_platform_name; ++} ++ ++static unsigned long long infinity_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int infinity_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int infinity_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int infinity_usb_vbus_control(int param) ++{ ++ int package = infinity_get_package_type(); ++ ++ if(0 == param) //disable vbus ++ { ++ if(MS_PACKAGE_BGA == package || MS_PACKAGE_BGA_256M == package) ++ { ++ // BGA (PAD_PM_GPIO2) ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_28, BIT6|BIT7); //reg_pwm2_mode = 0 ++ CLRREG8(BASE_REG_PMGPIO_PA + REG_ID_02, BIT1); //output = 0 ++ CLRREG8(BASE_REG_PMGPIO_PA + REG_ID_02, BIT0); //oen = 0 ++ } ++ else if(MS_PACKAGE_QFP == package || MS_PACKAGE_QFN == package) ++ { ++ // QFP (PAD_SPI0_CK) need to check many register, please refer to GPIO table ++ CLRREG8(0x1F2079C4, BIT4); //output = 0 ++ CLRREG8(0x1F2079C4, BIT5); //oen = 0 ++ } ++ else ++ { ++ printk(KERN_ERR "[%s] TODO: package type =%d\n", __FUNCTION__, package); ++ return 0; ++ } ++ printk(KERN_INFO "[%s] Disable USB VBUS\n", __FUNCTION__); ++ } ++ else if(1 == param) ++ { ++ if(MS_PACKAGE_BGA == package || MS_PACKAGE_BGA_256M == package) ++ { ++ // BGA (PAD_PM_GPIO2) ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_28, BIT6|BIT7); //reg_pwm2_mode = 0 ++ SETREG8(BASE_REG_PMGPIO_PA + REG_ID_02, BIT1); //output = 1 ++ CLRREG8(BASE_REG_PMGPIO_PA + REG_ID_02, BIT0); //oen = 0 ++ } ++ else if(MS_PACKAGE_QFP == package || MS_PACKAGE_QFN == package) ++ { ++ // QFP (PAD_SPI0_CK) need to check many register, please refer to GPIO table ++ SETREG8(0x1F2079C4, BIT4); //output = 1 ++ CLRREG8(0x1F2079C4, BIT5); //oen = 0 ++ } ++ else ++ { ++ printk(KERN_ERR "[%s] TODO: package type =%d\n", __FUNCTION__, package); ++ return 0; ++ } ++ printk(KERN_INFO "[%s] Enable USB VBUS\n", __FUNCTION__); ++ } ++ else ++ { ++ printk(KERN_ERR "[%s] param invalid\n", __FUNCTION__); ++ } ++ return 0; ++} ++ ++extern u32 arch_timer_get_rate(void); ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++static u64 infinity_chip_get_us_ticks(void) ++{ ++ const struct cyclecounter *arch_cc=arch_timer_get_timecounter()->cc; ++ u64 cycles=(arch_cc->read(arch_cc)-us_ticks_cycle_offset); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void intinify_reset_us_ticks_cycle_offset(void) ++{ ++ const struct cyclecounter *arch_cc=arch_timer_get_timecounter()->cc; ++ us_ticks_cycle_offset=arch_cc->read(arch_cc); ++} ++ ++static int infinity_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("[%s]CHIP_FUNCTION SET. ID=%d, param=%d\n",PLATFORM_NAME,function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ infinity_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ infinity_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ infinity_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ infinity_usb_vbus_control(param); ++ break; ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++ default: ++ printk(KERN_ERR "[%s]Unsupport CHIP_FUNCTION!! ID=%d\n",PLATFORM_NAME,function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init infinity_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ ++ chip->chip_flush_miu_pipe=infinity_chip_flush_miu_pipe; ++ chip->phys_to_miu=infinity_phys_to_MIU; ++ chip->miu_to_phys=infinity_MIU_to_phys; ++ chip->chip_get_device_id=infinity_get_device_id; ++ chip->chip_get_revision=infinity_get_revision; ++ chip->chip_get_platform_name=infinity_get_platform_name; ++ chip->chip_get_riu_phys=infinity_chip_get_riu_phys; ++ chip->chip_get_riu_size=infinity_chip_get_riu_size; ++ ++ chip->chip_function_set=infinity_chip_function_set; ++ chip->chip_get_storage_type=infinity_get_storage_type; ++ chip->chip_get_package_type=infinity_get_package_type; ++ chip->chip_get_us_ticks=infinity_chip_get_us_ticks; ++ ++} ++ ++extern char* LX_VERSION; ++static void __init infinity_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\n[INFINITY] : %s\n\n",LX_VERSION); ++ ++ intinify_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ infinity_soc_dev_attr.family = kasprintf(GFP_KERNEL, infinity_platform_name); ++ infinity_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", infinity_get_revision()); ++ infinity_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", infinity_get_device_id()); ++ infinity_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ infinity_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&infinity_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)infinity_soc_dev_attr.family); ++ kfree((void *)infinity_soc_dev_attr.revision); ++ kfree((void *)infinity_soc_dev_attr.soc_id); ++ kfree((void *)infinity_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //disable ETAG pad setting if QFP or QFN package ++ if(MS_PACKAGE_QFP == infinity_get_package_type() || MS_PACKAGE_QFN == infinity_get_package_type()) ++ CLRREG8(BASE_REG_CHIPTOP_PA + REG_ID_0F, BIT0|BIT1); ++} ++ ++ ++ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client{ ++ char* name; ++ short bw_client_id; ++ short bw_enabled; ++ short bw_val; ++ short bw_val_thread; ++}; ++ ++static struct miu_client miu0_clients[] = { ++ {"OVERALL ",0x00,0,0,0}, ++ {"MFE(F) ",0x01,0,0,0}, ++ {"MFE(B) ",0x02,0,0,0}, ++ {"VHE ",0x03,0,0,0}, ++ {"JPE1 ",0x04,0,0,0}, ++ {"JPE0 ",0x05,0,0,0}, ++ {"BACH ",0x06,0,0,0}, ++ {"FILE ",0x07,0,0,0}, ++ {"UHC0 ",0x08,0,0,0}, ++ {"EMAC ",0x09,0,0,0}, ++ {"MCU51 ",0x0A,0,0,0}, ++ {"URDMA ",0x0B,0,0,0}, ++ {"BDMA ",0x0C,0,0,0}, ++ {"NA ",0x0D,0,0,0}, ++ {"NA ",0x0E,0,0,0}, ++ {"NA ",0x0F,0,0,0}, ++ {"CMDQ ",0x10,0,0,0}, ++ {"ISP_DNR ",0x11,0,0,0}, ++ {"ISP_ROT ",0x12,0,0,0}, ++ {"ISP_DMA ",0x13,0,0,0}, ++ {"ISP_STA ",0x14,0,0,0}, ++ {"GOP ",0x15,0,0,0}, ++ {"SC_DNR ",0x16,0,0,0}, ++ {"SC_DNR_SAD",0x17,0,0,0}, ++ {"SC_CROP ",0x18,0,0,0}, ++ {"SC1_FRM ",0x19,0,0,0}, ++ {"SC1_SNP ",0x1A,0,0,0}, ++ {"SC1_DBG ",0x1B,0,0,0}, ++ {"SC2_FRM ",0x1C,0,0,0}, ++ {"SC3_FRM ",0x1D,0,0,0}, ++ {"FCIE ",0x1E,0,0,0}, ++ {"SDIO ",0x1F,0,0,0}, ++ {"CPU ",0x70,0,0,0}, ++ ++}; ++ ++static struct miu_device miu0; ++ ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++static struct task_struct *pBWmonitorThread=NULL; ++struct mutex bw_monitor_mutex; ++ ++ ++int BW_measure(short bwclientid) ++{ ++ short BW_val=0; ++ mutex_lock(&bw_monitor_mutex); ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x50)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ mdelay(300); ++ BW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ ++ mutex_unlock(&bw_monitor_mutex); ++ ++ return BW_val; ++} ++ ++static int BW_monitor(void *arg) ++{ ++ int i=0; ++ short tempBW_val=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ ++ if(miu0_clients[i].bw_enabled) ++ { ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x50)) ;//reset ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ //mdelay(300); ++ //tempBW_val=0; ++ //tempBW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ tempBW_val=BW_measure(miu0_clients[i].bw_client_id); ++ ++ if(miu0_clients[i].bw_val_thread= (sizeof(miu0_clients)/sizeof(miu0_clients[0])) ) return -EINVAL; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ miu0_clients[idx].bw_enabled=enabled; ++ } ++ return n; ++} ++ ++static ssize_t bw_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return set_miu_client_enable(dev,buf,n,1); ++} ++ ++static ssize_t bw_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ str += scnprintf(str, end - str, "%d ",(short)i); ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t bw_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return set_miu_client_enable(dev,buf,n,0); ++} ++ ++static ssize_t bw_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%04X][%d]\n",(short)i,miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t bw_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return 0; ++} ++ ++static ssize_t bw_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int ip_loop_time=1; ++ int i=0, temp_loop_time=0; ++ short tempBW_val=0; ++ ++ //reset all bw value ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_val=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ for (temp_loop_time=0;temp_loop_timekobj.name[3])) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ //read from bw register and saved back to bw_val ++ str += scnprintf(str, end - str, "%2d:%s[0x%04X] BW_val=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id,miu0_clients[i].bw_val,miu0_clients[i].bw_val*100/1024, ++ (miu0_clients[i].bw_val*10000/1024)%100); ++ ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++ ++ ++static int set_bw_thread_enable(struct device *dev, const char *buf, size_t n) ++{ ++ long idx=-1; ++ int i=0; ++ int ret; ++ ++ if (kstrtol(buf, 10, &idx) != 0 || idx<0 || idx >= 2 ) return -EINVAL; ++ ++ if(idx==1)//enable thread ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) //reset all bandwidth value ++ { ++ miu0_clients[i].bw_val_thread=0; ++ } ++ ++ if(pBWmonitorThread==NULL) ++ { ++ pBWmonitorThread = kthread_create(BW_monitor,(void *)&pBWmonitorThread,"BW Monitor"); ++ if (IS_ERR(pBWmonitorThread)) ++ { ++ ret = PTR_ERR(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ return ret; ++ } ++ wake_up_process(pBWmonitorThread); ++ } ++ } ++ else if (idx==0 && (pBWmonitorThread!=NULL))//disable thread ++ { ++ kthread_stop(pBWmonitorThread); ++ } ++ return n; ++} ++ ++ ++static ssize_t bw_thread_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return set_bw_thread_enable(dev,buf,n); ++} ++ ++ ++static ssize_t bw_thread_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ //read from bw register and saved back to bw_val ++ str += scnprintf(str, end - str, "%2d:%s[0x%04X] BW_val_thread=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id,miu0_clients[i].bw_val_thread,miu0_clients[i].bw_val_thread*100/1024, ++ (miu0_clients[i].bw_val_thread*10000/1024)%100); ++ ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++ ++ ++DEVICE_ATTR(bw_enable, 0644, bw_enable_show, bw_enable_store); ++DEVICE_ATTR(bw_disable, 0644, bw_disable_show, bw_disable_store); ++DEVICE_ATTR(bw, 0644, bw_show, bw_store); ++DEVICE_ATTR(bw_thread, 0644, bw_thread_show, bw_thread_store); ++ ++ ++static void __init infinity_create_MIU_node(void) ++{ ++ int ret; ++ ++ miu0.index=0; ++ miu0.dev.kobj.name="miu0"; ++ miu0.dev.bus=&miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ++ ret=device_register(&miu0.dev); ++ ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_bw_enable); ++ device_create_file(&miu0.dev, &dev_attr_bw_disable); ++ device_create_file(&miu0.dev, &dev_attr_bw); ++ device_create_file(&miu0.dev, &dev_attr_bw_thread); ++ mutex_init(&bw_monitor_mutex); ++} ++ ++struct mcm_client{ ++ char* name; ++ short index; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, 0}, ++ {"VHE", MCM_ID_VHE, 0}, ++ {"MFE", MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, 0}, ++ {"AESDMA", MCM_ID_AESDMA, 0}, ++ {"UHC", MCM_ID_UHC, 0}, ++ {"EMAC", MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, 0}, ++ {"GOP", MCM_ID_GOP, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, 0}, ++ {"*ALL_CLIENTS*", MCM_ID_ALL, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ return 0; ++ } ++ else if(index == MCM_ID_MCU51) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x0; ++ else if (index == MCM_ID_URDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x1; ++ else if (index == MCM_ID_BDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x4; ++ else if (index == MCM_ID_VHE) ++ addr = BASE_REG_MCM_VHE_GP_PA + 0x0; ++ else if (index == MCM_ID_MFE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x0; ++ else if (index == MCM_ID_JPE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1; ++ else if (index == MCM_ID_BACH) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x4; ++ else if (index == MCM_ID_AESDMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x5; ++ else if (index == MCM_ID_UHC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x8; ++ else if (index == MCM_ID_EMAC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x9; ++ else if (index == MCM_ID_CMDQ) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xC; ++ else if (index == MCM_ID_ISP_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xD; ++ else if (index == MCM_ID_ISP_DMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x10; ++ else if (index == MCM_ID_GOP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x11; ++ else if (index == MCM_ID_SC_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x14; ++ else if (index == MCM_ID_SC_DNR_SAD) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x15; ++ else if (index == MCM_ID_SC_CROP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x18; ++ else if (index == MCM_ID_SC1_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x19; ++ else if (index == MCM_ID_SC1_SNP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1C; ++ else if (index == MCM_ID_SC1_DBG) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1D; ++ else if (index == MCM_ID_SC2_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x20; ++ else if (index == MCM_ID_SC3_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x21; ++ else if (index == MCM_ID_FCIE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x24; ++ else if (index == MCM_ID_SDIO) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x25; ++ else if (index == MCM_ID_SC1_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x28; ++ else if (index == MCM_ID_SC2_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x29; ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init infinity_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++ ++ ++ ++ ++extern int infinity_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init infinity_init_late(void) ++{ ++ infinity_pm_init(); ++ infinity_create_MIU_node(); ++ infinity_create_MCM_node(); ++} ++ ++DT_MACHINE_START(MS_INFINITY_DT, "MStar Infinity (Flattened Device Tree)") ++ .dt_compat = infinity_dt_compat, ++ .map_io = infinity_map_io, ++ .init_machine = infinity_init_machine, ++ .init_early = infinity_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = infinity_init_irqchip, ++ .init_late = infinity_init_late, ++ .restart = infinity_restart, //in reset.S ++MACHINE_END +diff --git a/arch/arm/mach-mstar/infinity/pm.c b/arch/arm/mach-mstar/infinity/pm.c +new file mode 100644 +index 00000000..cc301e19 +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity/pm.c +@@ -0,0 +1,71 @@ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void infinity_suspend_imi(void); ++static void (*infinity_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int infinity_suspend_ready(unsigned long ret) ++{ ++ infinity_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&infinity_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ infinity_suspend_imi_fn(); ++ return 0; ++} ++ ++static int infinity_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, infinity_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++extern void intinify_reset_us_ticks_cycle_offset(void); ++static void infinity_suspend_finish(void) ++{ ++ intinify_reset_us_ticks_cycle_offset(); ++} ++ ++/* sequence: begin, prepare, prepare_late, enter, wake, finish, end */ ++struct platform_suspend_ops infinity_suspend_ops = { ++ .enter = infinity_suspend_enter, ++ .valid = suspend_valid_only_mem, ++ .finish = infinity_suspend_finish, ++}; ++ ++ ++int __init infinity_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&infinity_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-mstar/infinity/reset.S b/arch/arm/mach-mstar/infinity/reset.S +new file mode 100644 +index 00000000..aed3155c +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity/reset.S +@@ -0,0 +1,20 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++ ++ .align 5 ++.globl infinity_restart ++ ++infinity_restart: ++ mov r3, #0x00FF ++ ldr r1, =0xFD001CB8 ++ str r3, [r1] ++ mov r3, #0x0079 ++ str r3, [r1] ++ nop ++ nop ++ nop ++ nop ++ ++_loop_forever: ++ b _loop_forever +diff --git a/arch/arm/mach-mstar/infinity/sram.S b/arch/arm/mach-mstar/infinity/sram.S +new file mode 100644 +index 00000000..0218aab3 +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity/sram.S +@@ -0,0 +1,134 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++.align 3 ++.globl infinity_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(infinity_suspend_imi) ++ //These instructions are run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ // 3. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 4. PM sleep mode ++ //wriu -w 0x0e40 0x0000 //reg_ckg_mcu, reg_ckg_spi to xtal ++ //wriu 0x170e 0x03 //reg_spi_arb_ctrl[1:0] ++ //wriu -w 0x1710 0x007f //reg_non_pm_ack_timeout_len[15:0] ++ //wriu 0x3c24 0x30 //reg_pwoff_rst0_en, reg_pwoff_rst1_en ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x0e38 0x0c //reg_link_isoen2gpio4, reg_link_wkint2gpio4 ++ //wriu -w 0x0e24 0xbabe //reg_gpio_pm_lock[15:0] ++ //wriu 0x0e6e 0xa5 //reg_gpio_pm_lock3[7:0] ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ ldr r0, =0xA5 ++ strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x0f08 0x10 //set PM_GPIO_4 oen=0, out=0 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ b . ++ENDPROC(infinity_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-mstar/infinity3/Makefile b/arch/arm/mach-mstar/infinity3/Makefile +new file mode 100644 +index 00000000..f4f0fc77 +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity3/Makefile +@@ -0,0 +1,6 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++obj-y += infinity3.o ++obj-$(CONFIG_PM_SLEEP) += pm.o ++obj-y += sram.o ++obj-y += miu_bw.o +\ No newline at end of file +diff --git a/arch/arm/mach-mstar/infinity3/infinity3.c b/arch/arm/mach-mstar/infinity3/infinity3.c +new file mode 100644 +index 00000000..900dfb95 +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity3/infinity3.c +@@ -0,0 +1,637 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "infinity3/gpio.h" ++#include "infinity3/registers.h" ++#include "infinity3/mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++/* IO tables */ ++static struct map_desc mstar_io_desc[] __initdata = ++{ ++ /* Define Registers' physcial and virtual addresses */ ++ {IO_VIRT, __phys_to_pfn(IO_PHYS), IO_SIZE, MT_DEVICE}, ++ {SPI_VIRT, __phys_to_pfn(SPI_PHYS), SPI_SIZE, MT_DEVICE}, ++ {GIC_VIRT, __phys_to_pfn(GIC_PHYS), GIC_SIZE, MT_DEVICE}, ++ //{IMI_VIRT, __phys_to_pfn(IMI_PHYS), IMI_SIZE, MT_DEVICE}, ++}; ++ ++ ++static const char *mstar_dt_compat[] __initconst = { ++ "mstar,infinity3", ++ NULL, ++}; ++ ++static void __init mstar_map_io(void) ++{ ++ iotable_init(mstar_io_desc, ARRAY_SIZE(mstar_io_desc)); ++} ++ ++#define PLATFORM_NAME PLATFORM_NAME_INFINITY3 ++ ++extern struct ms_chip* ms_chip_get(void); ++extern void __init ms_chip_init_default(void); ++//extern void __init mstar_init_irqchip(void); ++//extern void infinity_restart(enum reboot_mode mode, const char *cmd); ++extern struct timecounter *arch_timer_get_timecounter(void); ++ ++ ++static int mcm_rw(int index, int ratio, int write); ++ ++ ++/************************************* ++* Mstar chip flush function ++*************************************/ ++static DEFINE_SPINLOCK(mstar_l2prefetch_lock); ++ ++static void mstar_uart_disable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> X ++ //CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4 | BIT5); ++ //CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT11); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8 | BIT9); ++ } ++ else if(line == 2) ++ { ++ // FUART_Mode -> X ++ CLRREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0 | BIT1); ++ } ++} ++ ++static void mstar_uart_enable_line(int line) ++{ ++ if(line == 0) //for debug, do not change ++ { ++ // UART0_Mode -> PAD_UART0_TX/RX ++ //SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT4); ++ } ++ else if(line == 1) ++ { ++ // UART1_Mode -> PAD_UART1_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT8); ++ } ++ else if(line==2) ++ { ++ // FUART_Mode -> PAD_FUART_TX/RX ++ SETREG16(BASE_REG_CHIPTOP_PA + REG_ID_03, BIT0); ++ } ++} ++ ++static int mstar_get_device_id(void) ++{ ++ return (int)(INREG16(BASE_REG_PMTOP_PA) & 0x00FF);; ++} ++ ++static int mstar_get_revision(void) ++{ ++ u16 tmp = 0; ++ tmp = INREG16((unsigned int)(BASE_REG_PMTOP_PA + REG_ID_67)); ++ tmp=((tmp >> 8) & 0x00FF); ++ ++ return (tmp+1); ++} ++ ++ ++static void mstar_chip_flush_miu_pipe(void) ++{ ++ unsigned long dwLockFlag = 0; ++ unsigned short dwReadData = 0; ++ ++ spin_lock_irqsave(&mstar_l2prefetch_lock, dwLockFlag); ++ //toggle the flush miu pipe fire bit ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ *(volatile unsigned short *)(0xFD204414) = 0x11; ++ ++ do ++ { ++ dwReadData = *(volatile unsigned short *)(0xFD204440); ++ dwReadData &= BIT12; //Check Status of Flush Pipe Finish ++ ++ } while(dwReadData == 0); ++ ++ spin_unlock_irqrestore(&mstar_l2prefetch_lock, dwLockFlag); ++ ++} ++ ++static u64 mstar_phys_to_MIU(u64 x) ++{ ++ ++ return ((x) - MIU0_BASE); ++} ++ ++static u64 mstar_MIU_to_phys(u64 x) ++{ ++ ++ return ((x) + MIU0_BASE); ++} ++ ++ ++struct soc_device_attribute mstar_soc_dev_attr; ++ ++extern const struct of_device_id of_default_bus_match_table[]; ++ ++static int mstar_get_storage_type(void) ++{ ++/*//check DIDKEY bank, offset 0x70 ++#define STORAGE_SPI_NAND BIT2 ++#define STORAGE_EMMC BIT3 ++#define STORAGE_P_NAND BIT4 ++#define STORAGE_SPI_NOR BIT5 ++*/ ++ u8 type = (INREG16(BASE_REG_DIDKEY_PA + 0x70*4) & 0x3C); ++ ++ if(BIT4 == type) ++ return (int)MS_STORAGE_NAND; ++ else if(BIT5 == type) ++ return (int)MS_STORAGE_NOR; ++ else if(BIT3 == type) ++ return (int)MS_STORAGE_EMMC; ++ else if(BIT2 == type) ++ return (int)MS_STORAGE_SPINAND_ECC; ++ else ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int mstar_get_package_type(void) ++{ ++ if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S01A")) ++ return MS_I3_PACKAGE_BGA_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S02A-256M") || !strcmp(&mstar_soc_dev_attr.machine[10], "MSC250C")) ++ return MS_I3_PACKAGE_DDR3_1866_256MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S04A")) ++ return MS_I3_PACKAGE_QFN_DDR3_128MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "MSC000A-S03A-64M")) ++ return MS_I3_PACKAGE_QFN_DDR2_64MB; ++ else if(!strcmp(&mstar_soc_dev_attr.machine[10], "FPGA")) ++ return MS_I3_PACKAGE_FPGA_128MB; ++ else ++ { ++ printk(KERN_ERR "!!!!! Machine name [%s] \n", mstar_soc_dev_attr.machine); ++ return MS_I3_PACKAGE_UNKNOWN; ++ } ++} ++static char mstar_platform_name[]=PLATFORM_NAME_INFINITY3; ++ ++char* mstar_get_platform_name(void) ++{ ++ return mstar_platform_name; ++} ++ ++static unsigned long long mstar_chip_get_riu_phys(void) ++{ ++ return IO_PHYS; ++} ++ ++static int mstar_chip_get_riu_size(void) ++{ ++ return IO_SIZE; ++} ++ ++ ++static int mstar_ir_enable(int param) ++{ ++ printk(KERN_ERR "NOT YET IMPLEMENTED!![%s]",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mstar_usb_vbus_control(int param) ++{ ++ ++ int ret; ++ //int package = mstar_get_package_type(); ++ static int power_en_gpio=-1; ++ ++ struct device_node *np; ++ int pin_data; ++ if(param<0 || param>1) ++ { ++ printk(KERN_ERR "[%s] param invalid\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ if (power_en_gpio<0) ++ { ++ np = of_find_node_by_path("/soc/Mstar-ehci-1"); ++ if(!of_property_read_u32(np, "power-enable-pad", &pin_data)) ++ { ++ printk(KERN_ERR "Get power-enable-pad from DTS GPIO(%d)\n", pin_data); ++ power_en_gpio = (unsigned char)pin_data; ++ } ++ else ++ { ++ printk(KERN_ERR "Can't get power-enable-pad from DTS, set default GPIO(%d)\n", pin_data); ++ power_en_gpio = PAD_PM_GPIO2; ++ } ++ ++ ret = gpio_request(power_en_gpio, "USB0-power-enable"); ++ if (ret < 0) { ++ printk(KERN_INFO "Failed to request USB0-power-enable GPIO(%d)\n", power_en_gpio); ++ power_en_gpio =-1; ++ return ret; ++ } ++ } ++ ++ if(0 == param) //disable vbus ++ { ++ gpio_direction_output(power_en_gpio, 0); ++ printk(KERN_INFO "[%s] Disable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ else if(1 == param) ++ { ++ gpio_direction_output(power_en_gpio, 1); ++ printk(KERN_INFO "[%s] Enable USB VBUS GPIO(%d)\n", __FUNCTION__,power_en_gpio); ++ } ++ return 0; ++} ++ ++extern u32 arch_timer_get_rate(void); ++static cycle_t us_ticks_cycle_offset=0; ++static u64 us_ticks_factor=1; ++ ++static u64 mstar_chip_get_us_ticks(void) ++{ ++ const struct cyclecounter *arch_cc=arch_timer_get_timecounter()->cc; ++ u64 cycles=(arch_cc->read(arch_cc)-us_ticks_cycle_offset); ++ u64 usticks=div64_u64(cycles,us_ticks_factor); ++ return usticks; ++} ++ ++void mstar_reset_us_ticks_cycle_offset(void) ++{ ++ const struct cyclecounter *arch_cc=arch_timer_get_timecounter()->cc; ++ us_ticks_cycle_offset=arch_cc->read(arch_cc); ++} ++ ++static int mstar_chip_function_set(int function_id, int param) ++{ ++ int res=-1; ++ ++ printk("CHIP_FUNCTION SET. ID=%d, param=%d\n",function_id,param); ++ switch (function_id) ++ { ++ case CHIP_FUNC_UART_ENABLE_LINE: ++ mstar_uart_enable_line(param); ++ break; ++ case CHIP_FUNC_UART_DISABLE_LINE: ++ mstar_uart_disable_line(param); ++ break; ++ case CHIP_FUNC_IR_ENABLE: ++ mstar_ir_enable(param); ++ break; ++ case CHIP_FUNC_USB_VBUS_CONTROL: ++ mstar_usb_vbus_control(param); ++ break; ++ case CHIP_FUNC_MCM_DISABLE_ID: ++ mcm_rw(param, 0, 1); ++ break; ++ case CHIP_FUNC_MCM_ENABLE_ID: ++ mcm_rw(param, 15, 1); ++ break; ++ default: ++ printk(KERN_ERR "Unsupport CHIP_FUNCTION!! ID=%d\n",function_id); ++ ++ } ++ ++ return res; ++} ++ ++ ++static void __init mstar_init_early(void) ++{ ++ ++ ++ struct ms_chip *chip=NULL; ++ ms_chip_init_default(); ++ ++ chip=ms_chip_get(); ++ ++ //enable axi exclusive access ++ *(volatile unsigned short *)(0xFD204414) = 0x10; ++ ++ chip->chip_flush_miu_pipe=mstar_chip_flush_miu_pipe; ++ chip->phys_to_miu=mstar_phys_to_MIU; ++ chip->miu_to_phys=mstar_MIU_to_phys; ++ chip->chip_get_device_id=mstar_get_device_id; ++ chip->chip_get_revision=mstar_get_revision; ++ chip->chip_get_platform_name=mstar_get_platform_name; ++ chip->chip_get_riu_phys=mstar_chip_get_riu_phys; ++ chip->chip_get_riu_size=mstar_chip_get_riu_size; ++ ++ chip->chip_function_set=mstar_chip_function_set; ++ chip->chip_get_storage_type=mstar_get_storage_type; ++ chip->chip_get_package_type=mstar_get_package_type; ++ chip->chip_get_us_ticks=mstar_chip_get_us_ticks; ++ ++} ++ ++extern char* LX_VERSION; ++static void __init mstar_init_machine(void) ++{ ++ struct soc_device *soc_dev; ++ struct device *parent = NULL; ++ ++ pr_info("\n\nVersion : %s\n\n",LX_VERSION); ++ ++ mstar_reset_us_ticks_cycle_offset(); ++ us_ticks_factor=div64_u64(arch_timer_get_rate(),1000000); ++ ++ mstar_soc_dev_attr.family = kasprintf(GFP_KERNEL, mstar_platform_name); ++ mstar_soc_dev_attr.revision = kasprintf(GFP_KERNEL, "%d", mstar_get_revision()); ++ mstar_soc_dev_attr.soc_id = kasprintf(GFP_KERNEL, "%u", mstar_get_device_id()); ++ mstar_soc_dev_attr.api_version = kasprintf(GFP_KERNEL, ms_chip_get()->chip_get_API_version()); ++ mstar_soc_dev_attr.machine = kasprintf(GFP_KERNEL, of_flat_dt_get_machine_name()); ++ ++ soc_dev = soc_device_register(&mstar_soc_dev_attr); ++ if (IS_ERR(soc_dev)) { ++ kfree((void *)mstar_soc_dev_attr.family); ++ kfree((void *)mstar_soc_dev_attr.revision); ++ kfree((void *)mstar_soc_dev_attr.soc_id); ++ kfree((void *)mstar_soc_dev_attr.machine); ++ goto out; ++ } ++ ++ parent = soc_device_to_device(soc_dev); ++ ++ /* ++ * Finished with the static registrations now; fill in the missing ++ * devices ++ */ ++out: ++ of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); ++ ++ //write log_buf address to mailbox ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x08), (int)log_buf_addr_get() & 0xFFFF); ++ OUTREG16(BASE_REG_MAILBOX_PA+BK_REG(0x09), ((int)log_buf_addr_get() >> 16 )& 0xFFFF); ++} ++ ++struct mcm_client{ ++ char* name; ++ short index; ++ short slow_down_ratio; ++}; ++ ++ ++static struct mcm_client mcm_clients[] = { ++ {"MCU51", MCM_ID_MCU51, 0}, ++ {"URDMA", MCM_ID_URDMA, 0}, ++ {"BDMA", MCM_ID_BDMA, 0}, ++ {"VHE", MCM_ID_VHE, 0}, ++ {"MFE", MCM_ID_MFE, 0}, ++ {"JPE", MCM_ID_JPE, 0}, ++ {"BACH", MCM_ID_BACH, 0}, ++ {"AESDMA", MCM_ID_AESDMA, 0}, ++ {"UHC", MCM_ID_UHC, 0}, ++ {"EMAC", MCM_ID_EMAC, 0}, ++ {"CMDQ", MCM_ID_CMDQ, 0}, ++ {"ISP_DNR", MCM_ID_ISP_DNR, 0}, ++ {"ISP_DMA", MCM_ID_ISP_DMA, 0}, ++ {"GOP", MCM_ID_GOP, 0}, ++ {"SC_DNR", MCM_ID_SC_DNR, 0}, ++ {"SC_DNR_SAD", MCM_ID_SC_DNR_SAD, 0}, ++ {"SC_CROP", MCM_ID_SC_CROP, 0}, ++ {"SC1_FRM", MCM_ID_SC1_FRM, 0}, ++ {"SC1_SNP", MCM_ID_SC1_SNP, 0}, ++ {"SC1_DBG", MCM_ID_SC1_DBG, 0}, ++ {"SC2_FRM", MCM_ID_SC2_FRM, 0}, ++ {"SC3_FRM", MCM_ID_SC3_FRM, 0}, ++ {"FCIE", MCM_ID_FCIE, 0}, ++ {"SDIO", MCM_ID_SDIO, 0}, ++ {"SC1_SNPI", MCM_ID_SC1_SNPI, 0}, ++ {"SC2_SNPI", MCM_ID_SC2_SNPI, 0}, ++ {"*ALL_CLIENTS*", MCM_ID_ALL, 0} //use carefully ++}; ++ ++struct device mcm_dev; ++ ++static struct bus_type mcm_subsys = { ++ .name = "mcm", ++ .dev_name = "mcm", ++}; ++ ++static int mcm_rw(int index, int ratio, int write) ++{ ++ int i, addr; ++ ++ if(index == MCM_ID_ALL && write) ++ { ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ mcm_rw(i, ratio, write); ++ return 0; ++ } ++ else if(index == MCM_ID_MCU51) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x0; ++ else if (index == MCM_ID_URDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x1; ++ else if (index == MCM_ID_BDMA) ++ addr = BASE_REG_MCM_DIG_GP_PA + 0x4; ++ else if (index == MCM_ID_VHE) ++ addr = BASE_REG_MCM_VHE_GP_PA + 0x0; ++ else if (index == MCM_ID_MFE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x0; ++ else if (index == MCM_ID_JPE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1; ++ else if (index == MCM_ID_BACH) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x4; ++ else if (index == MCM_ID_AESDMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x5; ++ else if (index == MCM_ID_UHC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x8; ++ else if (index == MCM_ID_EMAC) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x9; ++ else if (index == MCM_ID_CMDQ) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xC; ++ else if (index == MCM_ID_ISP_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0xD; ++ else if (index == MCM_ID_ISP_DMA) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x10; ++ else if (index == MCM_ID_GOP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x11; ++ else if (index == MCM_ID_SC_DNR) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x14; ++ else if (index == MCM_ID_SC_DNR_SAD) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x15; ++ else if (index == MCM_ID_SC_CROP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x18; ++ else if (index == MCM_ID_SC1_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x19; ++ else if (index == MCM_ID_SC1_SNP) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1C; ++ else if (index == MCM_ID_SC1_DBG) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x1D; ++ else if (index == MCM_ID_SC2_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x20; ++ else if (index == MCM_ID_SC3_FRM) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x21; ++ else if (index == MCM_ID_FCIE) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x24; ++ else if (index == MCM_ID_SDIO) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x25; ++ else if (index == MCM_ID_SC1_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x28; ++ else if (index == MCM_ID_SC2_SNPI) ++ addr = BASE_REG_MCM_SC_GP_PA + 0x29; ++ else ++ { ++ printk(KERN_ERR "mcm_clients[%d] not exists\n", index); ++ return -1; ++ } ++ ++ if(write) ++ OUTREG8(addr, (ratio << 4)); ++ else ++ mcm_clients[index].slow_down_ratio = (INREG8(addr) >> 4); ++ ++ return 0; ++} ++ ++ ++static ssize_t mcm_slow_ratio_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int index, ratio; ++ sscanf(buf, "%d %d", &index, &ratio); ++ ++ if(0 > ratio || ratio > 15) ++ { ++ printk(KERN_ERR "MCM slow down ratio should be 0~15\n"); ++ return -1; ++ } ++ ++ return mcm_rw(index, ratio, 1)?-1:n; ++} ++ ++static ssize_t mcm_slow_ratio_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ for(i=0; i<(sizeof(mcm_clients)/sizeof(mcm_clients[0]))-1;i++) ++ { ++ mcm_rw(i, 0, 0); ++ str += scnprintf(str, end - str, "[%d] %s: %d\n", mcm_clients[i].index, mcm_clients[i].name, mcm_clients[i].slow_down_ratio); ++ } ++ str += scnprintf(str, end - str, "[%d] %s\n", mcm_clients[i].index, mcm_clients[i].name); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(mcm_slow_ratio, 0644, mcm_slow_ratio_show, mcm_slow_ratio_store); ++ ++static void __init mstar_create_MCM_node(void) ++{ ++ int ret; ++ ++ mcm_dev.kobj.name="mcm"; ++ mcm_dev.bus=&mcm_subsys; ++ ++ ret = subsys_system_register(&mcm_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register MCM sub system!! %d\n",ret); ++ return; ++ } ++ ++ ret = device_register(&mcm_dev); ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register MCM device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&mcm_dev, &dev_attr_mcm_slow_ratio); ++} ++ ++ ++ ++ ++extern void mstar_create_MIU_node(void); ++extern int mstar_pm_init(void); ++extern void init_proc_zen(void); ++static inline void __init mstar_init_late(void) ++{ ++#ifdef CONFIG_PM_SLEEP ++ mstar_pm_init(); ++#endif ++ mstar_create_MIU_node(); ++ mstar_create_MCM_node(); ++} ++ ++static void infinity_restart(enum reboot_mode mode, const char * cmd) ++{ ++ U16 i=0; ++#if 0 ++ //fsp ++ //Check flash status ++ SETREG16(0x1f002dbc, BIT0);//h6F ++ OUTREG16(0x1f002db0, 0x0000);//h6C ++// do ++// { ++ OUTREG16(0x1f002d80, 0x0005); //h60 ++ OUTREG16(0x1f002da8, 0x0001); //h6A ++ OUTREG16(0x1f002dac, 0x0001); //h6B ++ OUTREG16(0x1f002db0, 0x2007); //h6C ++ OUTREG16(0x1f002db4, 0x0001); //h6D ++ while(!(INREG16(0x1f002db8)&BIT0)) //h6E ++ ; ++ SETREG16(0x1f002dbc, BIT0); //h6F// ++ } while((INREG16(0x1f002d94)&BIT0) == BIT0); //h65 ++#else ++ //riu_isp ++ OUTREG16(0x1f001000, 0xAAAA); ++ //password ++ do { ++ i++; ++ OUTREG16(0x1f001004, 0x0005); //cmd ++ OUTREG16(0x1f001030, 0x0001); //trigger ++ while((INREG16(0x1f001054) & 0x1) != 0x1) //check read data ready ++ ; ++ ++ if (Chip_Get_Storage_Type()!= MS_STORAGE_NOR) //if no nor-flash ++ break; ++ }while((INREG16(0x1f001014) & 0x1) != 0x0);//check WIP=0 ++#endif ++ ++ while(1) ++ { ++ OUTREG8(0x1f221000, 0x30+i); ++ mdelay(5); ++ OUTREG8(0x1f001cb8, 0x79); ++ } ++} ++ ++DT_MACHINE_START(MS_DT, "MStar Infinity3 (Flattened Device Tree)") ++ .dt_compat = mstar_dt_compat, ++ .map_io = mstar_map_io, ++ .init_machine = mstar_init_machine, ++ .init_early = mstar_init_early, ++// .init_time = ms_init_timer, ++// .init_irq = mstar_init_irqchip, ++ .init_late = mstar_init_late, ++ .restart = infinity_restart, //in reset.S ++MACHINE_END +diff --git a/arch/arm/mach-mstar/infinity3/miu_bw.c b/arch/arm/mach-mstar/infinity3/miu_bw.c +new file mode 100644 +index 00000000..e47844da +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity3/miu_bw.c +@@ -0,0 +1,682 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include "infinity3/gpio.h" ++#include "infinity3/registers.h" ++#include "infinity3/mcm_id.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "_ms_private.h" ++ ++ ++ ++struct miu_device { ++ struct device dev; ++ int index; ++}; ++ ++struct miu_client{ ++ char* name; ++ short bw_client_id; ++ short bw_enabled; ++ short bw_max; ++ short bw_avg; ++ short effi_avg; ++ short effi_min; ++// short bw_val_thread; ++}; ++ ++static struct miu_client miu0_clients[] = { ++ {"OVERALL ",0x00,1,0,0}, ++ {"MFE(F) ",0x01,0,0,0}, ++ {"MFE(B) ",0x02,0,0,0}, ++ {"VHE ",0x03,0,0,0}, ++ {"JPE1 ",0x04,0,0,0}, ++ {"JPE0 ",0x05,0,0,0}, ++ {"BACH ",0x06,0,0,0}, ++ {"AESDMA ",0x07,0,0,0}, ++ {"UHC0 ",0x08,0,0,0}, ++ {"EMAC ",0x09,0,0,0}, ++ {"MCU51 ",0x0A,0,0,0}, ++ {"URDMA ",0x0B,0,0,0}, ++ {"BDMA ",0x0C,0,0,0}, ++ {"NA ",0x0D,0,0,0}, ++ {"NA ",0x0E,0,0,0}, ++ {"NA ",0x0F,0,0,0}, ++ {"CMDQ ",0x10,0,0,0}, ++ {"ISP_DNR ",0x11,0,0,0}, ++ {"ISP_ROT ",0x12,0,0,0}, ++ {"ISP_STA ",0x13,0,0,0}, ++ {"ISP_MNL ",0x14,0,0,0}, ++ {"GOP0 ",0x15,0,0,0}, ++ {"SC_DNR ",0x16,0,0,0}, ++ {"SC_DNR_SAD",0x17,0,0,0}, ++ {"SC_CROP ",0x18,0,0,0}, ++ {"SC1_FRM ",0x19,0,0,0}, ++ {"SC1_SNP ",0x1A,0,0,0}, ++ {"SC1_DBG ",0x1B,0,0,0}, ++ {"SC2_FRM ",0x1C,0,0,0}, ++ {"SC3_FRM ",0x1D,0,0,0}, ++ {"FCIE ",0x1E,0,0,0}, ++ {"SDIO ",0x1F,0,0,0}, ++ {"CMDQ1 ",0x20,0,0,0}, ++ {"CMDQ2 ",0x21,0,0,0}, ++ {"NA ",0x22,0,0,0}, ++ {"ISP_STA1 ",0x23,0,0,0}, ++ {"GOP1 ",0x24,0,0,0}, ++ {"GOP2 ",0x25,0,0,0}, ++ {"UHC1 ",0x26,0,0,0}, ++ {"IVE ",0x27,0,0,0}, ++ {"MIIC1 ",0x28,0,0,0}, ++ {"CPU ",0x70,0,0,0}, ++ ++}; ++ ++ ++static struct miu_device miu0; ++ ++ ++static struct bus_type miu_subsys = { ++ .name = "miu", ++ .dev_name = "miu", ++}; ++ ++//static struct task_struct *pBWmonitorThread=NULL; ++//struct mutex bw_monitor_mutex; ++ ++int gmonitor_interval = 14; ++int gmonitor_duration = 1800; ++ ++ ++/* ++int BW_measure(short bwclientid) ++{ ++ short BW_val=0; ++ mutex_lock(&bw_monitor_mutex); ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x50)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((bwclientid << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ mdelay(300); ++ BW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ ++ mutex_unlock(&bw_monitor_mutex); ++ ++ return BW_val; ++} ++ ++static int BW_monitor(void *arg) ++{ ++ int i=0; ++ short tempBW_val=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ ++ if(miu0_clients[i].bw_enabled) ++ { ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x50)) ;//reset ++ //OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x51)) ;//set to read peak ++ ++ //mdelay(300); ++ //tempBW_val=0; ++ //tempBW_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ ++ tempBW_val=BW_measure(miu0_clients[i].bw_client_id); ++ ++ if(miu0_clients[i].bw_val_thread= (sizeof(miu0_clients)/sizeof(miu0_clients[0])) ) return -EINVAL; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ miu0_clients[idx].bw_enabled=enabled; ++ } ++ return n; ++} ++ ++static ssize_t monitor_client_enable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if(!strncmp(buf, "all",strlen("all"))) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_enabled=1; ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev,opt,n,1); ++ } ++ kfree(pt); ++ return n; ++} ++static ssize_t monitor_client_disable_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ int i; ++ char* pt; ++ char* opt; ++ ++ if(!strncmp(buf, "all",strlen("all"))) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_enabled=0; ++ } ++ return n; ++ } ++ ++ pt = kmalloc(strlen(buf)+1, GFP_KERNEL); ++ strcpy(pt, buf); ++ while ((opt = strsep(&pt, ";, ")) != NULL) ++ { ++ set_miu_client_enable(dev,opt,n,0); ++ } ++ kfree(pt); ++ return n; ++ ++} ++ ++static ssize_t monitor_client_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i,miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++static ssize_t monitor_client_disable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ str += scnprintf(str, end - str, "Num:IP_name [BW_Idx][Enable(1)/Disable(0)]\n"); ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ str += scnprintf(str, end - str, "%3d:%s[0x%02X][%d]\n",(short)i,miu0_clients[i].name,(short)miu0_clients[i].bw_client_id,(char)miu0_clients[i].bw_enabled); ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t monitor_set_interval_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_interval = input; ++ return count; ++} ++static ssize_t monitor_set_interval_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gmonitor_interval); ++} ++ ++static ssize_t monitor_set_counts_avg_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gmonitor_duration = input; ++ return count; ++} ++static ssize_t monitor_set_counts_avg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gmonitor_duration); ++} ++ ++ ++static ssize_t measure_bandwidth_MAX_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int ip_loop_time=1; ++ int i=0, temp_loop_time=0; ++ short tempBW_val=0; ++ ++ //reset all bw value ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_max=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ for (temp_loop_time=0;temp_loop_time buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++ ++static ssize_t measure_bandwidth_AVG_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ short temp_val=0; ++ ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ //reset all bw value ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].bw_avg=0; ++ miu0_clients[i].bw_max=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x40)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x41)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ if(gmonitor_interval>10) ++ msleep(gmonitor_interval); ++ else ++ mdelay(gmonitor_interval); ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].bw_max buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_efficiency_AVG_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ ++ short temp_val=0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].effi_min=0x3ff; ++ miu0_clients[i].effi_avg=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x30)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x35)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ if(gmonitor_interval>10) ++ msleep(gmonitor_interval); ++ else ++ mdelay(gmonitor_interval); ++ ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].effi_min>temp_val) ++ { ++ miu0_clients[i].effi_min=temp_val; ++ } ++ temp_loop_time++; ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ miu0_clients[i].effi_avg=total_temp/temp_loop_time; ++ ++ //str += scnprintf(str, end - str, "%2d:%s[0x%02X] EFFI_avg=%4d,%3d.%02d%% EFFI_min=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ printk( "%2d:%s[0x%02X] EFFI_avg=%4d,%3d.%02d%% EFFI_min=%4d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id, ++ miu0_clients[i].effi_avg, ++ miu0_clients[i].effi_avg*100/1024, ++ (miu0_clients[i].effi_avg*10000/1024)%100, ++ miu0_clients[i].effi_min, ++ miu0_clients[i].effi_min*100/1024, ++ (miu0_clients[i].effi_min*10000/1024)%100); ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t measure_all_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0, temp_loop_time=0; ++ ++ short temp_val=0; ++ unsigned long total_temp; ++ unsigned long deadline; ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ miu0_clients[i].effi_min=0x3ff; ++ miu0_clients[i].effi_avg=0; ++ miu0_clients[i].bw_avg=0; ++ miu0_clients[i].bw_max=0; ++ } ++ ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x30)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x35)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ if(gmonitor_interval>10) ++ msleep(gmonitor_interval); ++ else ++ mdelay(gmonitor_interval); ++ ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].effi_min>temp_val) ++ { ++ miu0_clients[i].effi_min=temp_val; ++ } ++ temp_loop_time++; ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D),0) ;//reset all ++ miu0_clients[i].effi_avg=total_temp/temp_loop_time; ++ ++ printk( "%2d:%s[0x%02X] EFFI_avg=%2d.%02d%% ",(short)i, ++ miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id, ++ miu0_clients[i].effi_avg*100/1024, (miu0_clients[i].effi_avg*10000/1024)%100); ++ ++ total_temp = 0; ++ temp_loop_time=0; ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x40)) ;//reset ++ OUTREG16( (BASE_REG_MIU_PA+REG_ID_0D), ( ((miu0_clients[i].bw_client_id << 8) & 0xFF00) | 0x41)) ;//set to read peak ++ deadline = jiffies + gmonitor_duration*HZ/1000; ++ do{ ++ msleep(gmonitor_interval); //mdelay(gmonitor_interval); ++ temp_val=INREG16((BASE_REG_MIU_PA+REG_ID_0E)); ++ total_temp += temp_val; ++ if(miu0_clients[i].bw_max buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++/* ++static int set_bw_thread_enable(struct device *dev, const char *buf, size_t n) ++{ ++ long idx=-1; ++ int i=0; ++ int ret; ++ ++ if (kstrtol(buf, 10, &idx) != 0 || idx<0 || idx >= 2 ) return -EINVAL; ++ ++ if(idx==1)//enable thread ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) //reset all bandwidth value ++ { ++ miu0_clients[i].bw_val_thread=0; ++ } ++ ++ if(pBWmonitorThread==NULL) ++ { ++ pBWmonitorThread = kthread_create(BW_monitor,(void *)&pBWmonitorThread,"BW Monitor"); ++ if (IS_ERR(pBWmonitorThread)) ++ { ++ ret = PTR_ERR(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ return ret; ++ } ++ wake_up_process(pBWmonitorThread); ++ } ++ } ++ else if (idx==0 && (pBWmonitorThread!=NULL))//disable thread ++ { ++ kthread_stop(pBWmonitorThread); ++ pBWmonitorThread = NULL; ++ } ++ return n; ++} ++ ++ ++static ssize_t bw_thread_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return set_bw_thread_enable(dev,buf,n); ++} ++ ++ ++static ssize_t bw_thread_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int i=0; ++ ++ if('0'== (dev->kobj.name[3])) ++ { ++ for(i=0; i<(sizeof(miu0_clients)/sizeof(miu0_clients[0]));i++) ++ { ++ if(miu0_clients[i].bw_enabled) ++ { ++ //read from bw register and saved back to bw_val ++ str += scnprintf(str, end - str, "%2d:%s[0x%04X] BW_val_thread=%3d,%3d.%02d%%\n",(short)i,miu0_clients[i].name, ++ (short)miu0_clients[i].bw_client_id,miu0_clients[i].bw_val_thread,miu0_clients[i].bw_val_thread*100/1024, ++ (miu0_clients[i].bw_val_thread*10000/1024)%100); ++ ++ } ++ } ++ } ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++ ++} ++DEVICE_ATTR(bw_thread, 0644, bw_thread_show, bw_thread_store); ++*/ ++ ++DEVICE_ATTR(monitor_client_enable, 0644, monitor_client_enable_show, monitor_client_enable_store); ++DEVICE_ATTR(monitor_client_disable, 0644, monitor_client_disable_show, monitor_client_disable_store); ++DEVICE_ATTR(measure_max_bandwidth, 0444, measure_bandwidth_MAX_show, NULL); ++DEVICE_ATTR(measure_avg_bandwidth, 0444, measure_bandwidth_AVG_show, NULL); ++DEVICE_ATTR(measure_avg_efficiency, 0444, measure_efficiency_AVG_show, NULL); ++DEVICE_ATTR(measure_all, 0444, measure_all_show, NULL); ++DEVICE_ATTR(monitor_set_interval_ms, 0644, monitor_set_interval_avg_show, monitor_set_interval_avg_store); ++DEVICE_ATTR(monitor_set_duration_ms, 0644, monitor_set_counts_avg_show, monitor_set_counts_avg_store); ++ ++void mstar_create_MIU_node(void) ++{ ++ int ret; ++ ++ miu0.index=0; ++ miu0.dev.kobj.name="miu0"; ++ miu0.dev.bus=&miu_subsys; ++ ++ ret = subsys_system_register(&miu_subsys, NULL); ++ if (ret) ++ { ++ printk(KERN_ERR "Failed to register miu sub system!! %d\n",ret); ++ return; ++ } ++ ++ ++ ret=device_register(&miu0.dev); ++ ++ if(ret) ++ { ++ printk(KERN_ERR "Failed to register miu0 device!! %d\n",ret); ++ return; ++ } ++ ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_enable); ++ device_create_file(&miu0.dev, &dev_attr_monitor_client_disable); ++ //device_create_file(&miu0.dev, &dev_attr_bw_thread); ++ device_create_file(&miu0.dev, &dev_attr_measure_max_bandwidth); ++ device_create_file(&miu0.dev, &dev_attr_measure_avg_bandwidth); ++ device_create_file(&miu0.dev, &dev_attr_measure_avg_efficiency); ++ device_create_file(&miu0.dev, &dev_attr_measure_all); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_interval_ms); ++ device_create_file(&miu0.dev, &dev_attr_monitor_set_duration_ms); ++ ++ //mutex_init(&bw_monitor_mutex); ++} +diff --git a/arch/arm/mach-mstar/infinity3/pm.c b/arch/arm/mach-mstar/infinity3/pm.c +new file mode 100644 +index 00000000..c076f970 +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity3/pm.c +@@ -0,0 +1,63 @@ ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#define FIN printk(KERN_ERR"[%s]+++\n",__FUNCTION__) ++#define FOUT printk(KERN_ERR"[%s]---\n",__FUNCTION__) ++#define HERE printk(KERN_ERR"%s: %d\n",__FILE__,__LINE__) ++ ++extern void infinity_suspend_imi(void); ++static void (*mstar_suspend_imi_fn)(void); ++static void __iomem *suspend_imi_vbase; ++ ++static int mstar_suspend_ready(unsigned long ret) ++{ ++ mstar_suspend_imi_fn = fncpy(suspend_imi_vbase, (void*)&infinity_suspend_imi, 0x1000); ++ ++ //flush cache to ensure memory is updated before self-refresh ++ __cpuc_flush_kern_all(); ++ //flush tlb to ensure following translation is all in tlb ++ local_flush_tlb_all(); ++ mstar_suspend_imi_fn(); ++ return 0; ++} ++ ++static int mstar_suspend_enter(suspend_state_t state) ++{ ++ FIN; ++ switch (state) ++ { ++ case PM_SUSPEND_MEM: ++ printk(KERN_INFO "state = PM_SUSPEND_MEM\n"); ++ cpu_suspend(0, mstar_suspend_ready); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++struct platform_suspend_ops mstar_suspend_ops = { ++ .enter = mstar_suspend_enter, ++ .valid = suspend_valid_only_mem, ++}; ++ ++ ++int __init mstar_pm_init(void) ++{ ++ unsigned int resume_pbase = virt_to_phys(cpu_resume); ++ suspend_imi_vbase = __arm_ioremap_exec(0xA0010000, 0x1000, false); //put suspend code at IMI offset 64K; ++ ++ suspend_set_ops(&mstar_suspend_ops); ++ ++ OUTREG16(0x1F001CEC, (resume_pbase & 0xFFFF)); ++ OUTREG16(0x1F001CF0, ((resume_pbase >> 16) & 0xFFFF)); ++ ++ printk(KERN_INFO "[%s] resume_pbase=0x%08X, suspend_imi_vbase=0x%08X\n", __func__, (unsigned int)resume_pbase, (unsigned int)suspend_imi_vbase); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-mstar/infinity3/sram.S b/arch/arm/mach-mstar/infinity3/sram.S +new file mode 100644 +index 00000000..6014d6de +--- /dev/null ++++ b/arch/arm/mach-mstar/infinity3/sram.S +@@ -0,0 +1,174 @@ ++/*------------------------------------------------------------------------------ ++ Function Code ++-------------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++ ++ .align 3 ++.globl infinity_suspend_imi ++.globl v7_cpu_resume ++ ++ENTRY(infinity_suspend_imi) ++ //Below flow is run at SRAM(IMI) ++ ++ // 1. DDR enter self-refresh ++ //wriu -w 0x101246,0xFFFE ++ //wriu -w 0x101266,0xFFFF ++ //wriu -w 0x101286,0xFFFF ++ //wriu -w 0x1012A6,0xFFFF ++ //wriu -w 0x101106,0xFFFF ++ //wriu -w 0x101126,0xFFFF ++ ++ ldr r1, =0xFD000000 ++ ldr r3, =0x101200 ++ ldr r4, =0x101100 ++ ldr r5, =0x101000 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0xFFFE ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x66 << 1] ++ str r0, [r2, #0x86 << 1] ++ str r0, [r2, #0xA6 << 1] ++ add r2, r1, r4, lsl #1 ++ str r0, [r2, #0x06 << 1] ++ str r0, [r2, #0x26 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ //wriu -w 0x101218,0x0400 //reg_mrx ++ //wriu -w 0x101200,0x002f //Bit[05]reg_auto_ref_off ++ //wriu -w 0x101200,0x052e //trig precharge all ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101200,0x032e ++ //wriu -w 0x101200,0x002e ++ //wriu -w 0x101206,0x1430 ++ ++ //wriu -w 0x101246,0xFFFF ++ //wriu -w 0x101200,0x202e ++ ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0400 ++ str r0, [r2, #0x18 << 1] ++ ldr r0, =0x002F ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x052E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x032E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x002E ++ str r0, [r2, #0x00 << 1] ++ ldr r0, =0x1430 ++ str r0, [r2, #0x06 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ ldr r0, =0xFFFF ++ str r0, [r2, #0x46 << 1] ++ ldr r0, =0x202E ++ str r0, [r2, #0x00 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 2. AN power down ++ //wriu -b 0x101203 0xF0 0xF0 ++ //wriu -b 0x101000 0x18 0x18 ++ //wriu -w 0x101054 0xc070 ++ //wriu -w 0x101008 0x0000 ++ ++ ldrb r0, [r2, #0x05] ++ orr r0, r0, #0xF0 ++ strb r0, [r2, #0x05] ++ add r2, r1, r5, lsl #1 ++ ldrb r0, [r2, #0x00 << 1] ++ orr r0, r0, #0x18 ++ strb r0, [r2, #0x00 << 1] ++ ldr r0, =0xC070 ++ str r0, [r2, #0x54 << 1] ++ ldr r0, =0x0000 ++ str r0, [r2, #0x08 << 1] ++ ++ //delay ++ ldr r0,=0x10000 ++1: ++ subs r0, #1 ++ bne 1b ++ ++ // 3. Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x40 << 1] ++ bic r0, r0, #0x1 << 7 ++ bic r0, r0, #0x1 << 14 ++ str r0, [r2, #0x40 << 1] ++ ++ // 4. Set wake up source(SAR, WOL, RTC) ++ ldr r3, =0x000E00 ++ add r2, r1, r3, lsl #1 ++ ldr r0, [r2, #0x10 << 1] ++ bic r0, r0, #0x16 //[1]:SAR, [2]:WOL, [4]:RTC ++ str r0, [r2, #0x10 << 1] ++ ++ // 5. PM enter sleep ++ //wriu 0x0000170e 0x03 ++ //wriu -w 0x00001710 0x007f ++ //wriu 0x00003c24 0x30 ++ ldr r3, =0x000E00 ++ ldr r4, =0x000F00 ++ ldr r5, =0x001700 ++ ldr r6, =0x003C00 ++ add r2, r1, r5, lsl #1 ++ ldr r0, =0x03 ++ strb r0, [r2, #0x0E << 1] ++ ldr r0, =0x007F ++ str r0, [r2, #0x10 << 1] ++ add r2, r1, r6, lsl #1 ++ ldr r0, =0x30 ++ strb r0, [r2, #0x24 << 1] ++ ++ //wriu 0x00000e38 0x0c ++ //wriu -w 0x00000e24 0xbabe ++ //wriu 0x00000e6e 0xa5 ++ add r2, r1, r3, lsl #1 ++ ldr r0, =0x0c ++ strb r0, [r2, #0x38 << 1] ++ ldr r0, =0xBABE ++ str r0, [r2, #0x24 << 1] ++ //ldr r0, =0xA5 ++ //strb r0, [r2, #0x6E << 1] ++ nop ++ nop ++ nop ++ nop ++ //wriu 0x00000f08 0x10 ++ add r2, r1, r4, lsl #1 ++ ldr r0, =0x10 ++ strb r0, [r2, #0x08 << 1] ++ nop ++ nop ++ nop ++ nop ++ ++ ++ ++ ++ ++ ++ENDPROC(infinity_suspend_imi) ++.ltorg +\ No newline at end of file +diff --git a/arch/arm/mach-mstar/libfdt.h b/arch/arm/mach-mstar/libfdt.h +new file mode 100644 +index 00000000..ea1ddcdb +--- /dev/null ++++ b/arch/arm/mach-mstar/libfdt.h +@@ -0,0 +1,1478 @@ ++#ifndef _LIBFDT_H ++#define _LIBFDT_H ++/* ++ * libfdt - Flat Device Tree manipulation ++ * Copyright (C) 2006 David Gibson, IBM Corporation. ++ * ++ * libfdt is dual licensed: you can use it either under the terms of ++ * the GPL, or the BSD license, at your option. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public ++ * License along with this library; if not, write to the Free ++ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, ++ * MA 02110-1301 USA ++ * ++ * Alternatively, ++ * ++ * b) Redistribution and use in source and binary forms, with or ++ * without modification, are permitted provided that the following ++ * conditions are met: ++ * ++ * 1. Redistributions of source code must retain the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer. ++ * 2. Redistributions in binary form must reproduce the above ++ * copyright notice, this list of conditions and the following ++ * disclaimer in the documentation and/or other materials ++ * provided with the distribution. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND ++ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, ++ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ++ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ++ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ++ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ++ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ++ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++#include "libfdt_env.h" ++#include "fdt.h" ++ ++#define FDT_FIRST_SUPPORTED_VERSION 0x10 ++#define FDT_LAST_SUPPORTED_VERSION 0x11 ++ ++/* Error codes: informative error codes */ ++#define FDT_ERR_NOTFOUND 1 ++ /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ ++#define FDT_ERR_EXISTS 2 ++ /* FDT_ERR_EXISTS: Attemped to create a node or property which ++ * already exists */ ++#define FDT_ERR_NOSPACE 3 ++ /* FDT_ERR_NOSPACE: Operation needed to expand the device ++ * tree, but its buffer did not have sufficient space to ++ * contain the expanded tree. Use fdt_open_into() to move the ++ * device tree to a buffer with more space. */ ++ ++/* Error codes: codes for bad parameters */ ++#define FDT_ERR_BADOFFSET 4 ++ /* FDT_ERR_BADOFFSET: Function was passed a structure block ++ * offset which is out-of-bounds, or which points to an ++ * unsuitable part of the structure for the operation. */ ++#define FDT_ERR_BADPATH 5 ++ /* FDT_ERR_BADPATH: Function was passed a badly formatted path ++ * (e.g. missing a leading / for a function which requires an ++ * absolute path) */ ++#define FDT_ERR_BADPHANDLE 6 ++ /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle ++ * value. phandle values of 0 and -1 are not permitted. */ ++#define FDT_ERR_BADSTATE 7 ++ /* FDT_ERR_BADSTATE: Function was passed an incomplete device ++ * tree created by the sequential-write functions, which is ++ * not sufficiently complete for the requested operation. */ ++ ++/* Error codes: codes for bad device tree blobs */ ++#define FDT_ERR_TRUNCATED 8 ++ /* FDT_ERR_TRUNCATED: Structure block of the given device tree ++ * ends without an FDT_END tag. */ ++#define FDT_ERR_BADMAGIC 9 ++ /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a ++ * device tree at all - it is missing the flattened device ++ * tree magic number. */ ++#define FDT_ERR_BADVERSION 10 ++ /* FDT_ERR_BADVERSION: Given device tree has a version which ++ * can't be handled by the requested operation. For ++ * read-write functions, this may mean that fdt_open_into() is ++ * required to convert the tree to the expected version. */ ++#define FDT_ERR_BADSTRUCTURE 11 ++ /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt ++ * structure block or other serious error (e.g. misnested ++ * nodes, or subnodes preceding properties). */ ++#define FDT_ERR_BADLAYOUT 12 ++ /* FDT_ERR_BADLAYOUT: For read-write functions, the given ++ * device tree has it's sub-blocks in an order that the ++ * function can't handle (memory reserve map, then structure, ++ * then strings). Use fdt_open_into() to reorganize the tree ++ * into a form suitable for the read-write operations. */ ++ ++/* "Can't happen" error indicating a bug in libfdt */ ++#define FDT_ERR_INTERNAL 13 ++ /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. ++ * Should never be returned, if it is, it indicates a bug in ++ * libfdt itself. */ ++ ++#define FDT_ERR_MAX 13 ++ ++/**********************************************************************/ ++/* Low-level functions (you probably don't need these) */ ++/**********************************************************************/ ++ ++const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); ++static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) ++{ ++ return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); ++} ++ ++uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); ++ ++/**********************************************************************/ ++/* Traversal functions */ ++/**********************************************************************/ ++ ++int fdt_next_node(const void *fdt, int offset, int *depth); ++ ++/**********************************************************************/ ++/* General functions */ ++/**********************************************************************/ ++ ++#define fdt_get_header(fdt, field) \ ++ (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) ++#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) ++#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) ++#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) ++#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) ++#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) ++#define fdt_version(fdt) (fdt_get_header(fdt, version)) ++#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) ++#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) ++#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) ++#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) ++ ++#define __fdt_set_hdr(name) \ ++ static inline void fdt_set_##name(void *fdt, uint32_t val) \ ++ { \ ++ struct fdt_header *fdth = (struct fdt_header*)fdt; \ ++ fdth->name = cpu_to_fdt32(val); \ ++ } ++__fdt_set_hdr(magic); ++__fdt_set_hdr(totalsize); ++__fdt_set_hdr(off_dt_struct); ++__fdt_set_hdr(off_dt_strings); ++__fdt_set_hdr(off_mem_rsvmap); ++__fdt_set_hdr(version); ++__fdt_set_hdr(last_comp_version); ++__fdt_set_hdr(boot_cpuid_phys); ++__fdt_set_hdr(size_dt_strings); ++__fdt_set_hdr(size_dt_struct); ++#undef __fdt_set_hdr ++ ++/** ++ * fdt_check_header - sanity check a device tree or possible device tree ++ * @fdt: pointer to data which might be a flattened device tree ++ * ++ * fdt_check_header() checks that the given buffer contains what ++ * appears to be a flattened device tree with sane information in its ++ * header. ++ * ++ * returns: ++ * 0, if the buffer appears to contain a valid device tree ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings, as above ++ */ ++int fdt_check_header(const void *fdt); ++ ++/** ++ * fdt_move - move a device tree around in memory ++ * @fdt: pointer to the device tree to move ++ * @buf: pointer to memory where the device is to be moved ++ * @bufsize: size of the memory space at buf ++ * ++ * fdt_move() relocates, if possible, the device tree blob located at ++ * fdt to the buffer at buf of size bufsize. The buffer may overlap ++ * with the existing device tree blob at fdt. Therefore, ++ * fdt_move(fdt, fdt, fdt_totalsize(fdt)) ++ * should always succeed. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++int fdt_move(const void *fdt, void *buf, int bufsize); ++ ++/**********************************************************************/ ++/* Read-only functions */ ++/**********************************************************************/ ++ ++/** ++ * fdt_string - retrieve a string from the strings block of a device tree ++ * @fdt: pointer to the device tree blob ++ * @stroffset: offset of the string within the strings block (native endian) ++ * ++ * fdt_string() retrieves a pointer to a single string from the ++ * strings block of the device tree blob at fdt. ++ * ++ * returns: ++ * a pointer to the string, on success ++ * NULL, if stroffset is out of bounds ++ */ ++const char *fdt_string(const void *fdt, int stroffset); ++ ++/** ++ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries ++ * @fdt: pointer to the device tree blob ++ * ++ * Returns the number of entries in the device tree blob's memory ++ * reservation map. This does not include the terminating 0,0 entry ++ * or any other (0,0) entries reserved for expansion. ++ * ++ * returns: ++ * the number of entries ++ */ ++int fdt_num_mem_rsv(const void *fdt); ++ ++/** ++ * fdt_get_mem_rsv - retrieve one memory reserve map entry ++ * @fdt: pointer to the device tree blob ++ * @address, @size: pointers to 64-bit variables ++ * ++ * On success, *address and *size will contain the address and size of ++ * the n-th reserve map entry from the device tree blob, in ++ * native-endian format. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); ++ ++/** ++ * fdt_subnode_offset_namelen - find a subnode based on substring ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * @namelen: number of characters of name to consider ++ * ++ * Identical to fdt_subnode_offset(), but only examine the first ++ * namelen characters of name for matching the subnode name. This is ++ * useful for finding subnodes based on a portion of a larger string, ++ * such as a full path. ++ */ ++int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, ++ const char *name, int namelen); ++/** ++ * fdt_subnode_offset - find a subnode of a given node ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * ++ * fdt_subnode_offset() finds a subnode of the node at structure block ++ * offset parentoffset with the given name. name may include a unit ++ * address, in which case fdt_subnode_offset() will find the subnode ++ * with that unit address, or the unit address may be omitted, in ++ * which case fdt_subnode_offset() will find an arbitrary subnode ++ * whose name excluding unit address matches the given name. ++ * ++ * returns: ++ * structure block offset of the requested subnode (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the requested subnode does not exist ++ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); ++ ++/** ++ * fdt_path_offset - find a tree node by its full path ++ * @fdt: pointer to the device tree blob ++ * @path: full path of the node to locate ++ * ++ * fdt_path_offset() finds a node of a given path in the device tree. ++ * Each path component may omit the unit address portion, but the ++ * results of this are undefined if any such path component is ++ * ambiguous (that is if there are multiple nodes at the relevant ++ * level matching the given component, differentiated only by unit ++ * address). ++ * ++ * returns: ++ * structure block offset of the node with the requested path (>=0), on success ++ * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid ++ * -FDT_ERR_NOTFOUND, if the requested node does not exist ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_path_offset(const void *fdt, const char *path); ++ ++/** ++ * fdt_get_name - retrieve the name of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of the starting node ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_get_name() retrieves the name (including unit address) of the ++ * device tree node at structure block offset nodeoffset. If lenp is ++ * non-NULL, the length of this name is also returned, in the integer ++ * pointed to by lenp. ++ * ++ * returns: ++ * pointer to the node's name, on success ++ * If lenp is non-NULL, *lenp contains the length of that name (>=0) ++ * NULL, on error ++ * if lenp is non-NULL *lenp contains an error code (<0): ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); ++ ++/** ++ * fdt_first_property_offset - find the offset of a node's first property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of a node ++ * ++ * fdt_first_property_offset() finds the first property of the node at ++ * the given structure block offset. ++ * ++ * returns: ++ * structure block offset of the property (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the requested node has no properties ++ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_first_property_offset(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_next_property_offset - step through a node's properties ++ * @fdt: pointer to the device tree blob ++ * @offset: structure block offset of a property ++ * ++ * fdt_next_property_offset() finds the property immediately after the ++ * one at the given structure block offset. This will be a property ++ * of the same node as the given property. ++ * ++ * returns: ++ * structure block offset of the next property (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the given property is the last in its node ++ * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_next_property_offset(const void *fdt, int offset); ++ ++/** ++ * fdt_get_property_by_offset - retrieve the property at a given offset ++ * @fdt: pointer to the device tree blob ++ * @offset: offset of the property to retrieve ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_get_property_by_offset() retrieves a pointer to the ++ * fdt_property structure within the device tree blob at the given ++ * offset. If lenp is non-NULL, the length of the property value is ++ * also returned, in the integer pointed to by lenp. ++ * ++ * returns: ++ * pointer to the structure representing the property ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const struct fdt_property *fdt_get_property_by_offset(const void *fdt, ++ int offset, ++ int *lenp); ++ ++/** ++ * fdt_get_property_namelen - find a property based on substring ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @namelen: number of characters of name to consider ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * Identical to fdt_get_property_namelen(), but only examine the first ++ * namelen characters of name for matching the property name. ++ */ ++const struct fdt_property *fdt_get_property_namelen(const void *fdt, ++ int nodeoffset, ++ const char *name, ++ int namelen, int *lenp); ++ ++/** ++ * fdt_get_property - find a given property in a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_get_property() retrieves a pointer to the fdt_property ++ * structure within the device tree blob corresponding to the property ++ * named 'name' of the node at offset nodeoffset. If lenp is ++ * non-NULL, the length of the property value is also returned, in the ++ * integer pointed to by lenp. ++ * ++ * returns: ++ * pointer to the structure representing the property ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_NOTFOUND, node does not have named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, ++ const char *name, int *lenp); ++static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, ++ const char *name, ++ int *lenp) ++{ ++ return (struct fdt_property *)(uintptr_t) ++ fdt_get_property(fdt, nodeoffset, name, lenp); ++} ++ ++/** ++ * fdt_getprop_by_offset - retrieve the value of a property at a given offset ++ * @fdt: pointer to the device tree blob ++ * @ffset: offset of the property to read ++ * @namep: pointer to a string variable (will be overwritten) or NULL ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_getprop_by_offset() retrieves a pointer to the value of the ++ * property at structure block offset 'offset' (this will be a pointer ++ * to within the device blob itself, not a copy of the value). If ++ * lenp is non-NULL, the length of the property value is also ++ * returned, in the integer pointed to by lenp. If namep is non-NULL, ++ * the property's namne will also be returned in the char * pointed to ++ * by namep (this will be a pointer to within the device tree's string ++ * block, not a new copy of the name). ++ * ++ * returns: ++ * pointer to the property's value ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * if namep is non-NULL *namep contiains a pointer to the property ++ * name. ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const void *fdt_getprop_by_offset(const void *fdt, int offset, ++ const char **namep, int *lenp); ++ ++/** ++ * fdt_getprop_namelen - get property value based on substring ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @namelen: number of characters of name to consider ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * Identical to fdt_getprop(), but only examine the first namelen ++ * characters of name for matching the property name. ++ */ ++const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, ++ const char *name, int namelen, int *lenp); ++ ++/** ++ * fdt_getprop - retrieve the value of a given property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to find ++ * @name: name of the property to find ++ * @lenp: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_getprop() retrieves a pointer to the value of the property ++ * named 'name' of the node at offset nodeoffset (this will be a ++ * pointer to within the device blob itself, not a copy of the value). ++ * If lenp is non-NULL, the length of the property value is also ++ * returned, in the integer pointed to by lenp. ++ * ++ * returns: ++ * pointer to the property's value ++ * if lenp is non-NULL, *lenp contains the length of the property ++ * value (>=0) ++ * NULL, on error ++ * if lenp is non-NULL, *lenp contains an error code (<0): ++ * -FDT_ERR_NOTFOUND, node does not have named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++const void *fdt_getprop(const void *fdt, int nodeoffset, ++ const char *name, int *lenp); ++static inline void *fdt_getprop_w(void *fdt, int nodeoffset, ++ const char *name, int *lenp) ++{ ++ return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); ++} ++ ++/** ++ * fdt_get_phandle - retrieve the phandle of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of the node ++ * ++ * fdt_get_phandle() retrieves the phandle of the device tree node at ++ * structure block offset nodeoffset. ++ * ++ * returns: ++ * the phandle of the node at nodeoffset, on success (!= 0, != -1) ++ * 0, if the node has no phandle, or another error occurs ++ */ ++uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_get_alias_namelen - get alias based on substring ++ * @fdt: pointer to the device tree blob ++ * @name: name of the alias th look up ++ * @namelen: number of characters of name to consider ++ * ++ * Identical to fdt_get_alias(), but only examine the first namelen ++ * characters of name for matching the alias name. ++ */ ++const char *fdt_get_alias_namelen(const void *fdt, ++ const char *name, int namelen); ++ ++/** ++ * fdt_get_alias - retreive the path referenced by a given alias ++ * @fdt: pointer to the device tree blob ++ * @name: name of the alias th look up ++ * ++ * fdt_get_alias() retrieves the value of a given alias. That is, the ++ * value of the property named 'name' in the node /aliases. ++ * ++ * returns: ++ * a pointer to the expansion of the alias named 'name', of it exists ++ * NULL, if the given alias or the /aliases node does not exist ++ */ ++const char *fdt_get_alias(const void *fdt, const char *name); ++ ++/** ++ * fdt_get_path - determine the full path of a node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose path to find ++ * @buf: character buffer to contain the returned path (will be overwritten) ++ * @buflen: size of the character buffer at buf ++ * ++ * fdt_get_path() computes the full path of the node at offset ++ * nodeoffset, and records that path in the buffer at buf. ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset. ++ * ++ * returns: ++ * 0, on success ++ * buf contains the absolute path of the node at ++ * nodeoffset, as a NUL-terminated string. ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) ++ * characters and will not fit in the given buffer. ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); ++ ++/** ++ * fdt_supernode_atdepth_offset - find a specific ancestor of a node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose parent to find ++ * @supernodedepth: depth of the ancestor to find ++ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL ++ * ++ * fdt_supernode_atdepth_offset() finds an ancestor of the given node ++ * at a specific depth from the root (where the root itself has depth ++ * 0, its immediate subnodes depth 1 and so forth). So ++ * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); ++ * will always return 0, the offset of the root node. If the node at ++ * nodeoffset has depth D, then: ++ * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); ++ * will return nodeoffset itself. ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset. ++ * ++ * returns: ++ ++ * structure block offset of the node at node offset's ancestor ++ * of depth supernodedepth (>=0), on success ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, ++ int supernodedepth, int *nodedepth); ++ ++/** ++ * fdt_node_depth - find the depth of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose parent to find ++ * ++ * fdt_node_depth() finds the depth of a given node. The root node ++ * has depth 0, its immediate subnodes depth 1 and so forth. ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset. ++ * ++ * returns: ++ * depth of the node at nodeoffset (>=0), on success ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_depth(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_parent_offset - find the parent of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose parent to find ++ * ++ * fdt_parent_offset() locates the parent node of a given node (that ++ * is, it finds the offset of the node which contains the node at ++ * nodeoffset as a subnode). ++ * ++ * NOTE: This function is expensive, as it must scan the device tree ++ * structure from the start to nodeoffset, *twice*. ++ * ++ * returns: ++ * structure block offset of the parent of the node at nodeoffset ++ * (>=0), on success ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_parent_offset(const void *fdt, int nodeoffset); ++ ++/** ++ * fdt_node_offset_by_prop_value - find nodes with a given property value ++ * @fdt: pointer to the device tree blob ++ * @startoffset: only find nodes after this offset ++ * @propname: property name to check ++ * @propval: property value to search for ++ * @proplen: length of the value in propval ++ * ++ * fdt_node_offset_by_prop_value() returns the offset of the first ++ * node after startoffset, which has a property named propname whose ++ * value is of length proplen and has value equal to propval; or if ++ * startoffset is -1, the very first such node in the tree. ++ * ++ * To iterate through all nodes matching the criterion, the following ++ * idiom can be used: ++ * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, ++ * propval, proplen); ++ * while (offset != -FDT_ERR_NOTFOUND) { ++ * // other code here ++ * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, ++ * propval, proplen); ++ * } ++ * ++ * Note the -1 in the first call to the function, if 0 is used here ++ * instead, the function will never locate the root node, even if it ++ * matches the criterion. ++ * ++ * returns: ++ * structure block offset of the located node (>= 0, >startoffset), ++ * on success ++ * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the ++ * tree after startoffset ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, ++ const char *propname, ++ const void *propval, int proplen); ++ ++/** ++ * fdt_node_offset_by_phandle - find the node with a given phandle ++ * @fdt: pointer to the device tree blob ++ * @phandle: phandle value ++ * ++ * fdt_node_offset_by_phandle() returns the offset of the node ++ * which has the given phandle value. If there is more than one node ++ * in the tree with the given phandle (an invalid tree), results are ++ * undefined. ++ * ++ * returns: ++ * structure block offset of the located node (>= 0), on success ++ * -FDT_ERR_NOTFOUND, no node with that phandle exists ++ * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); ++ ++/** ++ * fdt_node_check_compatible: check a node's compatible property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of a tree node ++ * @compatible: string to match against ++ * ++ * ++ * fdt_node_check_compatible() returns 0 if the given node contains a ++ * 'compatible' property with the given string as one of its elements, ++ * it returns non-zero otherwise, or on error. ++ * ++ * returns: ++ * 0, if the node has a 'compatible' property listing the given string ++ * 1, if the node has a 'compatible' property, but it does not list ++ * the given string ++ * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property ++ * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_check_compatible(const void *fdt, int nodeoffset, ++ const char *compatible); ++ ++/** ++ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value ++ * @fdt: pointer to the device tree blob ++ * @startoffset: only find nodes after this offset ++ * @compatible: 'compatible' string to match against ++ * ++ * fdt_node_offset_by_compatible() returns the offset of the first ++ * node after startoffset, which has a 'compatible' property which ++ * lists the given compatible string; or if startoffset is -1, the ++ * very first such node in the tree. ++ * ++ * To iterate through all nodes matching the criterion, the following ++ * idiom can be used: ++ * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); ++ * while (offset != -FDT_ERR_NOTFOUND) { ++ * // other code here ++ * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); ++ * } ++ * ++ * Note the -1 in the first call to the function, if 0 is used here ++ * instead, the function will never locate the root node, even if it ++ * matches the criterion. ++ * ++ * returns: ++ * structure block offset of the located node (>= 0, >startoffset), ++ * on success ++ * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the ++ * tree after startoffset ++ * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, standard meanings ++ */ ++int fdt_node_offset_by_compatible(const void *fdt, int startoffset, ++ const char *compatible); ++ ++/**********************************************************************/ ++/* Write-in-place functions */ ++/**********************************************************************/ ++ ++/** ++ * fdt_setprop_inplace - change a property's value, but not its size ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: pointer to data to replace the property value with ++ * @len: length of the property value ++ * ++ * fdt_setprop_inplace() replaces the value of a given property with ++ * the data in val, of length len. This function cannot change the ++ * size of a property, and so will only work if len is equal to the ++ * current length of the property. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the given property value, and will not alter or move any other part ++ * of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, if len is not equal to the property's current length ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, ++ const void *val, int len); ++ ++/** ++ * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 32-bit integer value to replace the property with ++ * ++ * fdt_setprop_inplace_u32() replaces the value of a given property ++ * with the 32-bit integer value in val, converting val to big-endian ++ * if necessary. This function cannot change the size of a property, ++ * and so will only work if the property already exists and has length ++ * 4. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the given property value, and will not alter or move any other part ++ * of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 64-bit integer value to replace the property with ++ * ++ * fdt_setprop_inplace_u64() replaces the value of a given property ++ * with the 64-bit integer value in val, converting val to big-endian ++ * if necessary. This function cannot change the size of a property, ++ * and so will only work if the property already exists and has length ++ * 8. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the given property value, and will not alter or move any other part ++ * of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, ++ const char *name, uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_inplace_cell - change the value of a single-cell property ++ * ++ * This is an alternative name for fdt_setprop_inplace_u32() ++ */ ++static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); ++} ++ ++/** ++ * fdt_nop_property - replace a property with nop tags ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to nop ++ * @name: name of the property to nop ++ * ++ * fdt_nop_property() will replace a given property's representation ++ * in the blob with FDT_NOP tags, effectively removing it from the ++ * tree. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the property, and will not alter or move any other part of the ++ * tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_nop_property(void *fdt, int nodeoffset, const char *name); ++ ++/** ++ * fdt_nop_node - replace a node (subtree) with nop tags ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node to nop ++ * ++ * fdt_nop_node() will replace a given node's representation in the ++ * blob, including all its subnodes, if any, with FDT_NOP tags, ++ * effectively removing it from the tree. ++ * ++ * This function will alter only the bytes in the blob which contain ++ * the node and its properties and subnodes, and will not alter or ++ * move any other part of the tree. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_nop_node(void *fdt, int nodeoffset); ++ ++/**********************************************************************/ ++/* Sequential write functions */ ++/**********************************************************************/ ++ ++int fdt_create(void *buf, int bufsize); ++int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); ++int fdt_finish_reservemap(void *fdt); ++int fdt_begin_node(void *fdt, const char *name); ++int fdt_property(void *fdt, const char *name, const void *val, int len); ++static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_property(fdt, name, &val, sizeof(val)); ++} ++static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_property(fdt, name, &val, sizeof(val)); ++} ++static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) ++{ ++ return fdt_property_u32(fdt, name, val); ++} ++#define fdt_property_string(fdt, name, str) \ ++ fdt_property(fdt, name, str, strlen(str)+1) ++int fdt_end_node(void *fdt); ++int fdt_finish(void *fdt); ++ ++/**********************************************************************/ ++/* Read-write functions */ ++/**********************************************************************/ ++ ++int fdt_create_empty_tree(void *buf, int bufsize); ++int fdt_open_into(const void *fdt, void *buf, int bufsize); ++int fdt_pack(void *fdt); ++ ++/** ++ * fdt_add_mem_rsv - add one memory reserve map entry ++ * @fdt: pointer to the device tree blob ++ * @address, @size: 64-bit values (native endian) ++ * ++ * Adds a reserve map entry to the given blob reserving a region at ++ * address address of length size. ++ * ++ * This function will insert data into the reserve map and will ++ * therefore change the indexes of some entries in the table. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new reservation entry ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); ++ ++/** ++ * fdt_del_mem_rsv - remove a memory reserve map entry ++ * @fdt: pointer to the device tree blob ++ * @n: entry to remove ++ * ++ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from ++ * the blob. ++ * ++ * This function will delete data from the reservation table and will ++ * therefore change the indexes of some entries in the table. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there ++ * are less than n+1 reserve map entries) ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_del_mem_rsv(void *fdt, int n); ++ ++/** ++ * fdt_set_name - change the name of a given node ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: structure block offset of a node ++ * @name: name to give the node ++ * ++ * fdt_set_name() replaces the name (including unit address, if any) ++ * of the given node with the given string. NOTE: this function can't ++ * efficiently check if the new name is unique amongst the given ++ * node's siblings; results are undefined if this function is invoked ++ * with a name equal to one of the given node's siblings. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob ++ * to contain the new name ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, standard meanings ++ */ ++int fdt_set_name(void *fdt, int nodeoffset, const char *name); ++ ++/** ++ * fdt_setprop - create or change a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: pointer to data to set the property value to ++ * @len: length of the property value ++ * ++ * fdt_setprop() sets the value of the named property in the given ++ * node to the given value and length, creating the property if it ++ * does not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_setprop(void *fdt, int nodeoffset, const char *name, ++ const void *val, int len); ++ ++/** ++ * fdt_setprop_u32 - set a property to a 32-bit integer ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 32-bit integer value for the property (native endian) ++ * ++ * fdt_setprop_u32() sets the value of the named property in the given ++ * node to the given 32-bit integer value (converting to big-endian if ++ * necessary), or creates a new property with that value if it does ++ * not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, ++ uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_u64 - set a property to a 64-bit integer ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 64-bit integer value for the property (native endian) ++ * ++ * fdt_setprop_u64() sets the value of the named property in the given ++ * node to the given 64-bit integer value (converting to big-endian if ++ * necessary), or creates a new property with that value if it does ++ * not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, ++ uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_setprop_cell - set a property to a single cell value ++ * ++ * This is an alternative name for fdt_setprop_u32() ++ */ ++static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, ++ uint32_t val) ++{ ++ return fdt_setprop_u32(fdt, nodeoffset, name, val); ++} ++ ++/** ++ * fdt_setprop_string - set a property to a string value ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @str: string value for the property ++ * ++ * fdt_setprop_string() sets the value of the named property in the ++ * given node to the given string value (using the length of the ++ * string to determine the new length of the property), or creates a ++ * new property with that value if it does not already exist. ++ * ++ * This function may insert or delete data from the blob, and will ++ * therefore change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++#define fdt_setprop_string(fdt, nodeoffset, name, str) \ ++ fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) ++ ++/** ++ * fdt_appendprop - append to or create a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to append to ++ * @val: pointer to data to append to the property value ++ * @len: length of the data to append to the property value ++ * ++ * fdt_appendprop() appends the value to the named property in the ++ * given node, creating the property if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_appendprop(void *fdt, int nodeoffset, const char *name, ++ const void *val, int len); ++ ++/** ++ * fdt_appendprop_u32 - append a 32-bit integer value to a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 32-bit integer value to append to the property (native endian) ++ * ++ * fdt_appendprop_u32() appends the given 32-bit integer value ++ * (converting to big-endian if necessary) to the value of the named ++ * property in the given node, or creates a new property with that ++ * value if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ val = cpu_to_fdt32(val); ++ return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_appendprop_u64 - append a 64-bit integer value to a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @val: 64-bit integer value to append to the property (native endian) ++ * ++ * fdt_appendprop_u64() appends the given 64-bit integer value ++ * (converting to big-endian if necessary) to the value of the named ++ * property in the given node, or creates a new property with that ++ * value if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, ++ const char *name, uint64_t val) ++{ ++ val = cpu_to_fdt64(val); ++ return fdt_appendprop(fdt, nodeoffset, name, &val, sizeof(val)); ++} ++ ++/** ++ * fdt_appendprop_cell - append a single cell value to a property ++ * ++ * This is an alternative name for fdt_appendprop_u32() ++ */ ++static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, ++ const char *name, uint32_t val) ++{ ++ return fdt_appendprop_u32(fdt, nodeoffset, name, val); ++} ++ ++/** ++ * fdt_appendprop_string - append a string to a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to change ++ * @name: name of the property to change ++ * @str: string value to append to the property ++ * ++ * fdt_appendprop_string() appends the given string to the value of ++ * the named property in the given node, or creates a new property ++ * with that value if it does not already exist. ++ * ++ * This function may insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to ++ * contain the new property value ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ ++ fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) ++ ++/** ++ * fdt_delprop - delete a property ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node whose property to nop ++ * @name: name of the property to nop ++ * ++ * fdt_del_property() will delete the given property. ++ * ++ * This function will delete data from the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_NOTFOUND, node does not have the named property ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_delprop(void *fdt, int nodeoffset, const char *name); ++ ++/** ++ * fdt_add_subnode_namelen - creates a new node based on substring ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * @namelen: number of characters of name to consider ++ * ++ * Identical to fdt_add_subnode(), but use only the first namelen ++ * characters of name as the name of the new node. This is useful for ++ * creating subnodes based on a portion of a larger string, such as a ++ * full path. ++ */ ++int fdt_add_subnode_namelen(void *fdt, int parentoffset, ++ const char *name, int namelen); ++ ++/** ++ * fdt_add_subnode - creates a new node ++ * @fdt: pointer to the device tree blob ++ * @parentoffset: structure block offset of a node ++ * @name: name of the subnode to locate ++ * ++ * fdt_add_subnode() creates a new node as a subnode of the node at ++ * structure block offset parentoffset, with the given name (which ++ * should include the unit address, if any). ++ * ++ * This function will insert data into the blob, and will therefore ++ * change the offsets of some existing nodes. ++ ++ * returns: ++ * structure block offset of the created nodeequested subnode (>=0), on success ++ * -FDT_ERR_NOTFOUND, if the requested subnode does not exist ++ * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag ++ * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of ++ * the given name ++ * -FDT_ERR_NOSPACE, if there is insufficient free space in the ++ * blob to contain the new node ++ * -FDT_ERR_NOSPACE ++ * -FDT_ERR_BADLAYOUT ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings. ++ */ ++int fdt_add_subnode(void *fdt, int parentoffset, const char *name); ++ ++/** ++ * fdt_del_node - delete a node (subtree) ++ * @fdt: pointer to the device tree blob ++ * @nodeoffset: offset of the node to nop ++ * ++ * fdt_del_node() will remove the given node, including all its ++ * subnodes if any, from the blob. ++ * ++ * This function will delete data from the blob, and will therefore ++ * change the offsets of some existing nodes. ++ * ++ * returns: ++ * 0, on success ++ * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag ++ * -FDT_ERR_BADLAYOUT, ++ * -FDT_ERR_BADMAGIC, ++ * -FDT_ERR_BADVERSION, ++ * -FDT_ERR_BADSTATE, ++ * -FDT_ERR_BADSTRUCTURE, ++ * -FDT_ERR_TRUNCATED, standard meanings ++ */ ++int fdt_del_node(void *fdt, int nodeoffset); ++ ++/**********************************************************************/ ++/* Debugging / informational functions */ ++/**********************************************************************/ ++ ++const char *fdt_strerror(int errval); ++ ++#endif /* _LIBFDT_H */ +diff --git a/arch/arm/mach-mstar/libfdt_env.h b/arch/arm/mach-mstar/libfdt_env.h +new file mode 100644 +index 00000000..1f4e7187 +--- /dev/null ++++ b/arch/arm/mach-mstar/libfdt_env.h +@@ -0,0 +1,15 @@ ++#ifndef _ARM_LIBFDT_ENV_H ++#define _ARM_LIBFDT_ENV_H ++ ++#include ++#include ++#include ++ ++#define fdt16_to_cpu(x) be16_to_cpu(x) ++#define cpu_to_fdt16(x) cpu_to_be16(x) ++#define fdt32_to_cpu(x) be32_to_cpu(x) ++#define cpu_to_fdt32(x) cpu_to_be32(x) ++#define fdt64_to_cpu(x) be64_to_cpu(x) ++#define cpu_to_fdt64(x) cpu_to_be64(x) ++ ++#endif +diff --git a/arch/arm/mach-mstar/ms_chip.c b/arch/arm/mach-mstar/ms_chip.c +new file mode 100644 +index 00000000..1b8f00b8 +--- /dev/null ++++ b/arch/arm/mach-mstar/ms_chip.c +@@ -0,0 +1,609 @@ ++#include ++#include ++#include ++#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++// ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++// ++//#include ++#include ++#include ++#include ++#include "mdrv_API_version.h" ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_version.h" ++#include "registers.h" ++ ++#define UNUSED(var) (void)((var) = (var)) ++ ++DEFINE_SEMAPHORE(PfModeSem); ++DEFINE_MUTEX(FCIE3_mutex); ++EXPORT_SYMBOL(FCIE3_mutex); ++static struct ms_chip chip_funcs; ++ ++const struct MS_BIN_OPTION ms_image_size __attribute__ ((aligned (16))) = ++{ ++ {'#','I','M','G','_','S','Z','#'}, ++ {0,0,0,0,0,0,0,0} ++}; ++ ++const struct MS_BIN_OPTION ms_XIP_phys_addr __attribute__ ((aligned (16))) = ++{ ++ {'#','X','I','P','_','P','A','#'}, ++ {0,0,0,0,0,0,0,0} ++}; ++ ++//const char cedric_machine_name[]="cedric"; ++//const char chicago_machine_name[]="chicago"; ++//const char infinity_machine_name[]="infinity"; ++static char NONE_platform_name[]="NONE"; ++////const struct MS_BIN_OPTION ms_builtin_dtb_size __attribute__ ((aligned (16)))= ++////{ ++//// {'#','D','T','B','_','S','Z','#'}, ++//// {0,0,0,0,0,0,0,0} ++////}; ++// ++// ++#define BUILTIN_DTB_SZ (64*1024) ++struct MS_BUILTIN_DTB ++{ ++ struct MS_BIN_OPTION ms_dtb; ++ u8 content[BUILTIN_DTB_SZ]; ++}; ++ ++ ++struct MS_BUILTIN_DTB builtin_dtb __attribute__ ((aligned (16)))= ++{ ++ .ms_dtb={ {'#','M','S','_','D','T','B','#'}, {0,0,0,0,0,0,0,0}}, ++}; ++void *builtin_dtb_start=(void *)builtin_dtb.content; ++const u32 builtin_dtb_size=BUILTIN_DTB_SZ; ++ ++ ++//MS_VERSION LX_VERSION = ++//{ ++// {'M','V','X'}, ++// MVXV_HEAD_VER, ++// MVXV_LIB_TYPE, //R = general release version ++// MVXV_CHIP_ID, ++// MVXV_CHANGELIST, ++// MVXV_COMP_ID, ++// {'#'}, ++// {'X','V','M'}, ++//}; ++ ++#if defined(MVXV_EXT) ++#define MVXV_V2 "MVX" MVXV_HEAD_VER MVXV_LIB_TYPE MVXV_CHIP_ID MVXV_CHANGELIST MVXV_COMP_ID MVXV_EXT "#XVM" ++#else ++#define MVXV_V2 "MVX" MVXV_HEAD_VER MVXV_LIB_TYPE MVXV_CHIP_ID MVXV_CHANGELIST MVXV_COMP_ID "#XVM" ++#endif ++const char* LX_VERSION=MVXV_V2; ++ ++const char *ms_API_version=""KL_API_VERSION; ++ ++void Chip_Flush_MIU_Pipe(void){ ++ chip_funcs.chip_flush_miu_pipe(); ++} ++ ++void Chip_Flush_Memory(void){ ++ chip_funcs.chip_flush_memory(); ++} ++ ++void Chip_Read_Memory(void){ ++ chip_funcs.chip_read_memory(); ++} ++ ++void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ chip_funcs.cache_flush_range_va_pa(u32VAddr,u32PAddr,u32Size); ++} ++ ++void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ chip_funcs.cache_clean_range_va_pa(u32VAddr,u32PAddr,u32Size); ++} ++ ++void Chip_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ chip_funcs.cache_flush_range(u32Addr,u32Size); ++} ++ ++void Chip_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ chip_funcs.cache_clean_range(u32Addr,u32Size); ++} ++ ++void Chip_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ chip_funcs.cache_invalidate_range(u32Addr,u32Size); ++} ++ ++void Chip_Flush_CacheAll(void) ++{ ++ chip_funcs.cache_flush_all(); ++} ++ ++ ++u64 Chip_Phys_to_MIU(u64 phys) ++{ ++ return chip_funcs.phys_to_miu(phys); ++} ++ ++u64 Chip_MIU_to_Phys(u64 miu) ++{ ++ return chip_funcs.miu_to_phys(miu); ++} ++ ++ ++int Chip_Get_Device_ID(void) ++{ ++ return chip_funcs.chip_get_device_id(); ++} ++ ++int Chip_Get_Revision(void) ++{ ++ return chip_funcs.chip_get_revision(); ++} ++ ++ ++int Chip_Cache_Outer_Is_Enabled(void) ++{ ++ return chip_funcs.cache_outer_is_enabled(); ++} ++ ++ ++int Chip_Boot_Get_Dev_Type(void) ++{ ++ return (int)((MS_BOOT_DEV_TYPE)chip_funcs.chip_get_boot_dev_type()); ++} ++ ++char* Chip_Get_Platform_Name(void) ++{ ++ char *name=chip_funcs.chip_get_platform_name(); ++ if(name==NULL || strlen(name) > 15 ) ++ { ++ printk(KERN_ERR "platform name invalid!! must not be NULL & < 15 chars\n"); ++ BUG(); ++ } ++ ++ return name; ++} ++ ++const char* Chip_Get_API_Version(void) ++{ ++ return chip_funcs.chip_get_API_version(); ++} ++ ++ ++//u32 Chip_Get_Image_Size(void) ++//{ ++// return (u32)(__le32_to_cpu(*((__le64 *)((void *)&ms_.args[0])))); ++//} ++//// ++//u32 Chip_Get_DTB_Size(void) ++//{ ++// return (u32)(__le32_to_cpu(*((__le64 *)((void *)&MS_DTB_SIZE.args[0])))); ++//} ++ ++/************************************* ++* default chip function ++*************************************/ ++ ++static char* _default_Get_Platform_Name(void) ++{ ++ return NONE_platform_name; ++} ++ ++ ++static u64 _default_Phys_to_MIU(u64 phys) ++{ ++ return phys; ++} ++ ++static u64 _default_MIU_to_Phys(u64 miu) ++{ ++ return miu; ++} ++ ++static void _default_flush_miu_pipe(void) ++{ ++ ++} ++// ++ ++static void _default_Flush_Memory(void) ++{ ++ ++#ifdef CONFIG_MS_L2X0_PATCH ++ if(outer_cache.sync) ++ outer_cache.sync(); ++ else ++#endif ++ Chip_Flush_MIU_Pipe(); ++} ++ ++ ++static void _default_Read_Memory(void) ++{ ++ ++#ifdef CONFIG_MS_L2X0_PATCH ++ if(outer_cache.sync) ++ outer_cache.sync(); ++ else ++#endif ++ Chip_Flush_MIU_Pipe(); ++} ++ ++ ++//DCACHE_FLUSH function ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++void hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++static void _default_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ if(((void *) u32VAddr) == NULL) ++ { ++ printk("u32VAddr is invalid\n"); ++ return; ++ } ++ //Clean L1 ++ dmac_map_area((void *)u32VAddr,u32Size,1); ++ ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ //Clean L2 by Way ++ outer_cache.clean_range(u32PAddr,u32PAddr + u32Size); ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe(); ++#endif ++} ++ ++ ++ ++static void _default_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size) ++{ ++ if(((void *) u32VAddr) == NULL) ++ { ++ printk("u32VAddr is invalid\n"); ++ return; ++ } ++ //Clean & Invalid L1 ++ dmac_flush_range((void *)u32VAddr, (void *)(u32VAddr + u32Size)); ++ ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ //Clean&Inv L2 by range ++ outer_cache.flush_range(u32PAddr,u32PAddr + u32Size); ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe(); ++#endif ++} ++ ++ ++ ++static void _default_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ if( u32Addr == (unsigned long) NULL ) ++ { ++ printk("u32Addr is invalid\n"); ++ return; ++ } ++ //Clean L1 & Inv L1 ++ dmac_flush_range((const void *)u32Addr,(const void *)(u32Addr + u32Size)); ++ ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1 )) ++ //Clean&Inv L2 by Way ++ outer_cache.flush_all(); ++ else ++ //Clean&Inv L2 by Range ++ outer_cache.flush_range(__pa(u32Addr) , __pa(u32Addr) + u32Size); ++ ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe(); ++#endif ++ ++} ++ ++ ++static void _default_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ if( u32Addr ==(unsigned long) NULL ) ++ { ++ printk("u32Addr is invalid\n"); ++ return; ++ } ++ //Clean L1 ++ dmac_map_area((const void *)u32Addr,(size_t)u32Size,1); ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1)) ++ //Clean L2 by range ++ outer_cache.flush_all(); ++ else ++ //Clean&Inv L2 by Range ++ outer_cache.clean_range(__pa(u32Addr) , __pa(u32Addr) + u32Size); ++ } ++#endif ++ ++ #ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe(); ++ #endif ++} ++ ++ ++static void _default_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size) ++{ ++ if( u32Addr == (unsigned long) NULL ) ++ { ++ printk("u32Addr is invalid\n"); ++ return; ++ } ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ if(!virt_addr_valid(u32Addr) || !virt_addr_valid(u32Addr+ u32Size - 1)) ++ { ++ printk("%s:Input VA can't be converted to PA\n",__func__); ++ } ++ else ++ { ++ //Inv L2 by range ++ outer_cache.inv_range(__pa(u32Addr) , __pa(u32Addr)+ u32Size); ++ } ++ } ++#endif ++ //Inv L1 ++ dmac_map_area((const void *)u32Addr,(size_t)u32Size,2); ++ ++} ++ ++static void _default_Flush_CacheAll(void) ++{ ++ ++ __cpuc_flush_icache_all(); ++ __cpuc_flush_kern_all(); ++ __cpuc_flush_user_all(); ++#ifdef CONFIG_OUTER_CACHE ++#ifdef CONFIG_MS_L2X0_PATCH ++ if (Chip_Cache_Outer_Is_Enabled()) //check if L2 is enabled ++#endif ++ { ++ //Clean&Inv L2 by range ++ outer_cache.flush_all(); ++ } ++#endif ++ ++#ifndef CONFIG_OUTER_CACHE ++ Chip_Flush_MIU_Pipe(); ++#endif ++} ++ ++ ++static int _default_Get_Revision(void) ++{ ++ return 0; ++} ++ ++static int _default_Get_ID(void) ++{ ++ return (int)DEVICE_ID_END; ++} ++ ++ ++static int _default_Get_Boot_Dev_Type(void) ++{ ++ return (int)MS_BOOT_DEV_NONE; ++} ++ ++static int _default_get_storage_type(void) ++{ ++ return (int)MS_STORAGE_UNKNOWN; ++} ++ ++static int _default_get_package_type(void) ++{ ++ return 0; ++} ++ ++ ++static int _default_Outer_Cache_Is_Enabled(void) ++{ ++ return 0; ++} ++ ++ ++static unsigned long long _default_Get_RIU_Phys(void) ++{ ++ return 0; ++} ++ ++static int _default_Get_RIU_Size(void) ++{ ++ return 0; ++} ++ ++static int _default_chip_function_set(int id, int param) ++{ ++ UNUSED(id); ++ UNUSED(param); ++ printk(KERN_ERR "CHIP_FUNCTION not yet implemented\n!!"); ++ return -1; ++} ++ ++ ++static const char* _default_chip_get_API_version(void) ++{ ++ return ms_API_version; ++} ++ ++static u64 _default_chip_get_us_ticks(void) ++{ ++ return 0; ++} ++ ++struct ms_chip* ms_chip_get(void) ++{ ++ return &chip_funcs; ++} ++ ++void __init ms_chip_init_default(void) ++{ ++ chip_funcs.cache_clean_range=_default_Clean_Cache_Range; ++ chip_funcs.cache_flush_range=_default_Flush_Cache_Range; ++ chip_funcs.cache_flush_all=_default_Flush_CacheAll; ++ chip_funcs.cache_invalidate_range=_default_Inv_Cache_Range; ++ ++ chip_funcs.cache_clean_range_va_pa=_default_Clean_Cache_Range_VA_PA; ++ chip_funcs.cache_flush_range_va_pa=_default_Flush_Cache_Range_VA_PA; ++ ++ ++ chip_funcs.chip_flush_memory=_default_Flush_Memory; ++ chip_funcs.chip_read_memory=_default_Read_Memory; ++ chip_funcs.chip_flush_miu_pipe=_default_flush_miu_pipe; ++ ++ chip_funcs.phys_to_miu=_default_Phys_to_MIU; ++ chip_funcs.miu_to_phys=_default_MIU_to_Phys; ++ ++ chip_funcs.chip_get_device_id=_default_Get_ID; ++ chip_funcs.chip_get_revision=_default_Get_Revision; ++ ++ chip_funcs.cache_outer_is_enabled=_default_Outer_Cache_Is_Enabled; ++ ++ chip_funcs.chip_get_boot_dev_type=_default_Get_Boot_Dev_Type; ++ chip_funcs.chip_get_platform_name=_default_Get_Platform_Name; ++ ++ chip_funcs.chip_get_riu_phys=_default_Get_RIU_Phys; ++ chip_funcs.chip_get_riu_size=_default_Get_RIU_Size; ++ ++ chip_funcs.chip_function_set=_default_chip_function_set; ++ ++ chip_funcs.chip_get_API_version=_default_chip_get_API_version; ++ ++ chip_funcs.chip_get_storage_type=_default_get_storage_type; ++ chip_funcs.chip_get_package_type=_default_get_package_type; ++ ++ chip_funcs.chip_get_us_ticks=_default_chip_get_us_ticks; ++ ++} ++ ++unsigned long long Chip_Get_RIU_Phys(void) ++{ ++ return chip_funcs.chip_get_riu_phys(); ++} ++ ++int Chip_Get_RIU_Size(void) ++{ ++ return chip_funcs.chip_get_riu_size(); ++} ++ ++ ++int Chip_Function_Set(int function_id, int param) ++{ ++ return chip_funcs.chip_function_set(function_id,param); ++} ++ ++int Chip_Get_Storage_Type(void) ++{ ++ return (int)chip_funcs.chip_get_storage_type(); ++} ++ ++int Chip_Get_Package_Type(void) ++{ ++ return (int)chip_funcs.chip_get_package_type(); ++} ++ ++u64 Chip_Get_US_Ticks(void) ++{ ++ return chip_funcs.chip_get_us_ticks(); ++} ++ ++EXPORT_SYMBOL(ms_chip_get); ++ ++EXPORT_SYMBOL(Chip_Flush_MIU_Pipe); ++EXPORT_SYMBOL(Chip_Flush_Memory); ++EXPORT_SYMBOL(Chip_Read_Memory); ++EXPORT_SYMBOL(Chip_Flush_Cache_Range_VA_PA); ++EXPORT_SYMBOL(Chip_Clean_Cache_Range_VA_PA); ++EXPORT_SYMBOL(Chip_Flush_Cache_Range); ++EXPORT_SYMBOL(Chip_Clean_Cache_Range); ++EXPORT_SYMBOL(Chip_Inv_Cache_Range); ++EXPORT_SYMBOL(Chip_Flush_CacheAll); ++EXPORT_SYMBOL(Chip_Phys_to_MIU); ++EXPORT_SYMBOL(Chip_MIU_to_Phys); ++ ++EXPORT_SYMBOL(Chip_Cache_Outer_Is_Enabled); ++ ++EXPORT_SYMBOL(Chip_Get_Device_ID); ++EXPORT_SYMBOL(Chip_Get_Revision); ++EXPORT_SYMBOL(Chip_Get_Platform_Name); ++EXPORT_SYMBOL(Chip_Boot_Get_Dev_Type); ++EXPORT_SYMBOL(Chip_Get_Storage_Type); ++EXPORT_SYMBOL(Chip_Get_Package_Type); ++ ++EXPORT_SYMBOL(Chip_Get_US_Ticks); ++ ++EXPORT_SYMBOL(Chip_Get_RIU_Phys); ++EXPORT_SYMBOL(Chip_Get_RIU_Size); ++EXPORT_SYMBOL(Chip_Function_Set); ++ ++ ++ ++ ++ +diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig +index 7eb94e6f..70503c6c 100644 +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -656,7 +656,7 @@ config ARM_THUMBEE + make use of it. Say N for code that can run on CPUs without ThumbEE. + + config ARM_VIRT_EXT +- bool ++ bool "Enable ARM Virtualization Extension" + depends on MMU + default y if CPU_V7 + help +diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c +index 5e65ca8d..490e92ca 100644 +--- a/arch/arm/mm/cache-l2x0.c ++++ b/arch/arm/mm/cache-l2x0.c +@@ -33,6 +33,7 @@ + #include "cache-tauros3.h" + #include "cache-aurora-l2.h" + ++ + struct l2c_init_data { + const char *type; + unsigned way_size_0; +@@ -54,6 +55,7 @@ static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; + + struct l2x0_regs l2x0_saved_regs; + ++ + /* + * Common code for all cache controllers. + */ +@@ -225,6 +227,12 @@ static void l2c_save(void __iomem *base) + static void __l2c210_cache_sync(void __iomem *base) + { + writel_relaxed(0, base + sync_reg_offset); ++#ifdef CONFIG_MS_L2X0_PATCH ++ if(outer_cache.flush_MIU_pipe) ++ { ++ outer_cache.flush_MIU_pipe(); ++ } ++#endif + } + + static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start, +@@ -619,6 +627,13 @@ static void l2c310_resume(void) + { + void __iomem *base = l2x0_base; + ++#if defined(CONFIG_MS_L2X0_PATCH) ++ if(outer_cache.flush_MIU_pipe) ++ { ++ outer_cache.flush_MIU_pipe(); ++ } ++#endif ++ + if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) { + unsigned revision; + +diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c +index fb9d305c..4a13d15b 100644 +--- a/arch/arm/mm/mmu.c ++++ b/arch/arm/mm/mmu.c +@@ -1168,7 +1168,11 @@ static inline void prepare_page_table(void) + + #ifdef CONFIG_XIP_KERNEL + /* The XIP kernel is mapped in the module area -- skip over it */ ++#ifdef CONFIG_MS_ARMV7_XIP ++ addr = ((unsigned long)_edata_loc + PMD_SIZE - 1) & PMD_MASK; ++#else + addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; ++#endif + #endif + for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) + pmd_clear(pmd_off_k(addr)); +@@ -1247,7 +1251,11 @@ static void __init devicemaps_init(const struct machine_desc *mdesc) + #ifdef CONFIG_XIP_KERNEL + map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); + map.virtual = MODULES_VADDR; ++#ifdef CONFIG_MS_ARMV7_XIP ++ map.length = ((unsigned long)_edata_loc - map.virtual + ~SECTION_MASK) & SECTION_MASK; ++#else + map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; ++#endif + map.type = MT_ROM; + create_mapping(&map); + #endif +diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S +index 22ac2a6f..9949bd43 100644 +--- a/arch/arm/mm/proc-v7.S ++++ b/arch/arm/mm/proc-v7.S +@@ -319,7 +319,11 @@ __v7_pj4b_setup: + #endif /* CONFIG_CPU_PJ4B */ + + __v7_setup: +- adr r12, __v7_setup_stack @ the local stack ++#ifdef CONFIG_XIP_KERNEL ++ ldr r12, =PLAT_PHYS_OFFSET @ the local stack ++#else ++ adr r12, __v7_setup_stack @ the local stack ++#endif + stmia r12, {r0-r5, r7, r9, r11, lr} + bl v7_flush_dcache_louis + ldmia r12, {r0-r5, r7, r9, r11, lr} +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 00b9c487..612f60b9 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -165,6 +165,16 @@ config ARCH_XGENE + bool "AppliedMicro X-Gene SOC Family" + help + This enables support for AppliedMicro X-Gene SOC Family ++ ++config ARCH_ESL_ARM_V8 ++ bool "ESL ARMv8 Platform" ++ help ++ This enables support for ESL ARMv8 platform. May need to select the VEXPRESS together. ++ ++config BUILTIN_DTB ++ string "DTB to build into the kernel image" ++ depends on OF ++ + + endmenu + +diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile +index 2d54c554..e02f826a 100644 +--- a/arch/arm64/Makefile ++++ b/arch/arm64/Makefile +@@ -57,6 +57,11 @@ libs-y := arch/arm64/lib/ $(libs-y) + libs-y += $(LIBGCC) + libs-$(CONFIG_EFI_STUB) += drivers/firmware/efi/libstub/ + ++ifneq ($(CONFIG_BUILTIN_DTB),"") ++core-$(CONFIG_OF) += arch/arm64/boot/dts/ ++endif ++ ++ + # Default target when executing plain make + KBUILD_IMAGE := Image.gz + KBUILD_DTBS := dtbs +diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile +index f8001a62..09e782ef 100644 +--- a/arch/arm64/boot/dts/Makefile ++++ b/arch/arm64/boot/dts/Makefile +@@ -1,10 +1,15 @@ + dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb +-dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb ++dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb esl_v8.dtb + dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb + + targets += dtbs + targets += $(dtb-y) + ++BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB)).dtb.o ++ifneq ($(CONFIG_BUILTIN_DTB),"") ++obj-$(CONFIG_OF) += $(BUILTIN_DTB) ++endif ++ + dtbs: $(addprefix $(obj)/, $(dtb-y)) + + clean-files := *.dtb +diff --git a/arch/arm64/boot/dts/esl_v8.dts b/arch/arm64/boot/dts/esl_v8.dts +new file mode 100644 +index 00000000..5033ce1f +--- /dev/null ++++ b/arch/arm64/boot/dts/esl_v8.dts +@@ -0,0 +1,166 @@ ++/* ++ * ARM Ltd. Fast Models ++ * ++ * Architecture Envelope Model (AEM) ARMv8-A ++ * ARMAEMv8AMPCT ++ * ++ * MSTAR_ESL_AEMv8A ++ */ ++ ++/dts-v1/; ++ ++/memreserve/ 0x20000000 0x00010000; ++ ++/ { ++ model = "MSTAR_ESL_AEMv8A"; ++ compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress"; ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ chosen { ++ bootargs = "console=ttySY0 selinux=0 maxcpus=8 devtmpfs.mount=1 earlycon=mstar,0x1f220d00 debug"; ++ }; ++ ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x0>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++/* ++ cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x1>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++ ++ cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x2>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++ cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x3>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++ ++ cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x100>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++ ++ cpu@101 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x101>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++ ++ cpu@102 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x102>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++ ++ cpu@103 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x103>; ++ enable-method = "spin-table"; ++ cpu-release-addr = <0x0 0x2000fff8>; ++ }; ++*/ ++ }; ++ ++ memory@20000000 { ++ device_type = "memory"; ++ reg = <0x0 0x20000000 0 0x10000000>; ++ }; ++ ++ gic: interrupt-controller@120000000 { ++ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; ++ #interrupt-cells = <3>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ interrupt-controller; ++ reg = <0x1 0x20001000 0 0x1000>, ++ <0x1 0x20002000 0 0x1000>; ++/* ++ interrupts = <1 9 0xf04>; ++*/ ++ }; ++ ++ mic: ms-irq@1F202000 { ++ compatible = "mstar,ms-irq"; ++ #interrupt-cells = <2>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ host = <2>; ++ ++ interrupt-controller; ++ interrupt-parent = <&gic>; ++ reg = <0x0 0x1F202000 0 0x1000>, ++ <0x0 0x1F203000 0 0x1000>; ++ ++ interrupts = <1 15 0xff04>, ++ <1 12 0xff04>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <1 13 0xff01>, ++ <1 14 0xff01>, ++ <1 11 0xff01>, ++ <1 10 0xff01>; ++ clock-frequency = <233000000>; ++ }; ++ ++ ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = <0 60 4>, ++ <0 61 4>, ++ <0 62 4>, ++ <0 63 4>; ++ }; ++ ++ ++ serial0: uart@1F220d00 { ++ compatible = "mstar,uart"; ++ reg = <0 0x1F220d00 0 0x1000>; ++ interrupts = <0 50 0x01>; ++// interrupts = <0>; ++ clock-frequency = <115200>; ++/* ++ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; ++ clock-names = "uartclk", "apb_pclk"; ++ compatible = "arm,XXXX"; ++ reg = <0 0x1F001000 0 0x1000>; ++*/ ++ }; ++ ++ ++ ++ ++}; +diff --git a/arch/arm64/configs/esl_defconfig b/arch/arm64/configs/esl_defconfig +new file mode 100644 +index 00000000..ee3b9f0e +--- /dev/null ++++ b/arch/arm64/configs/esl_defconfig +@@ -0,0 +1,1302 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm64 3.18.10 Kernel Configuration ++# ++CONFIG_ARM64=y ++CONFIG_64BIT=y ++CONFIG_ARCH_PHYS_ADDR_T_64BIT=y ++CONFIG_MMU=y ++CONFIG_NO_IOPORT_MAP=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_RWSEM_XCHGADD_ALGORITHM=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CSUM=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_ZONE_DMA=y ++CONFIG_HAVE_GENERIC_RCU_GUP=y ++CONFIG_ARCH_DMA_ADDR_T_64BIT=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_NEED_SG_DMA_LENGTH=y ++CONFIG_SWIOTLB=y ++CONFIG_IOMMU_HELPER=y ++CONFIG_KERNEL_MODE_NEON=y ++CONFIG_FIX_EARLYCON_MEM=y ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_IRQ_WORK=y ++CONFIG_BUILDTIME_EXTABLE_SORT=y ++ ++# ++# General setup ++# ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++# CONFIG_COMPILE_TEST is not set ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++# CONFIG_SWAP is not set ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_CROSS_MEMORY_ATTACH=y ++# CONFIG_FHANDLE is not set ++# CONFIG_USELIB is not set ++CONFIG_HAVE_ARCH_AUDITSYSCALL=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_GENERIC_IRQ_SHOW=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_IRQ_DOMAIN=y ++CONFIG_HANDLE_DOMAIN_IRQ=y ++# CONFIG_IRQ_DOMAIN_DEBUG is not set ++CONFIG_SPARSE_IRQ=y ++CONFIG_GENERIC_TIME_VSYSCALL=y ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++CONFIG_ARCH_HAS_TICK_BROADCAST=y ++CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y ++ ++# ++# Timers subsystem ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ_COMMON=y ++# CONFIG_HZ_PERIODIC is not set ++CONFIG_NO_HZ_IDLE=y ++# CONFIG_NO_HZ_FULL is not set ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++ ++# ++# CPU/Task time and stats accounting ++# ++CONFIG_TICK_CPU_ACCOUNTING=y ++# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++ ++# ++# RCU Subsystem ++# ++CONFIG_TREE_PREEMPT_RCU=y ++CONFIG_PREEMPT_RCU=y ++# CONFIG_TASKS_RCU is not set ++CONFIG_RCU_STALL_COMMON=y ++# CONFIG_RCU_USER_QS is not set ++CONFIG_RCU_FANOUT=64 ++CONFIG_RCU_FANOUT_LEAF=16 ++# CONFIG_RCU_FANOUT_EXACT is not set ++# CONFIG_RCU_FAST_NO_HZ is not set ++# CONFIG_TREE_RCU_TRACE is not set ++# CONFIG_RCU_BOOST is not set ++# CONFIG_RCU_NOCB_CPU is not set ++CONFIG_BUILD_BIN2C=y ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=14 ++CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 ++CONFIG_GENERIC_SCHED_CLOCK=y ++CONFIG_CGROUPS=y ++# CONFIG_CGROUP_DEBUG is not set ++# CONFIG_CGROUP_FREEZER is not set ++# CONFIG_CGROUP_DEVICE is not set ++# CONFIG_CPUSETS is not set ++# CONFIG_CGROUP_CPUACCT is not set ++# CONFIG_RESOURCE_COUNTERS is not set ++# CONFIG_CGROUP_PERF is not set ++CONFIG_CGROUP_SCHED=y ++CONFIG_FAIR_GROUP_SCHED=y ++# CONFIG_CFS_BANDWIDTH is not set ++# CONFIG_RT_GROUP_SCHED is not set ++# CONFIG_BLK_CGROUP is not set ++# CONFIG_CHECKPOINT_RESTORE is not set ++CONFIG_NAMESPACES=y ++# CONFIG_UTS_NS is not set ++# CONFIG_IPC_NS is not set ++# CONFIG_USER_NS is not set ++# CONFIG_PID_NS is not set ++CONFIG_SCHED_AUTOGROUP=y ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="arch/arm64/boot/rootfs_esl.cpio" ++CONFIG_INITRAMFS_ROOT_UID=0 ++CONFIG_INITRAMFS_ROOT_GID=0 ++CONFIG_RD_GZIP=y ++CONFIG_RD_BZIP2=y ++CONFIG_RD_LZMA=y ++CONFIG_RD_XZ=y ++CONFIG_RD_LZO=y ++CONFIG_RD_LZ4=y ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_HAVE_UID16=y ++CONFIG_SYSCTL_EXCEPTION_TRACE=y ++# CONFIG_EXPERT is not set ++CONFIG_UID16=y ++# CONFIG_SGETMASK_SYSCALL is not set ++CONFIG_SYSFS_SYSCALL=y ++# CONFIG_SYSCTL_SYSCALL is not set ++CONFIG_KALLSYMS=y ++CONFIG_KALLSYMS_ALL=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++CONFIG_ELF_CORE=y ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++# CONFIG_BPF_SYSCALL is not set ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_ADVISE_SYSCALLS=y ++# CONFIG_EMBEDDED is not set ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++CONFIG_PERF_EVENTS=y ++# CONFIG_DEBUG_PERF_USE_VMALLOC is not set ++CONFIG_VM_EVENT_COUNTERS=y ++CONFIG_SLUB_DEBUG=y ++# CONFIG_COMPAT_BRK is not set ++# CONFIG_SLAB is not set ++CONFIG_SLUB=y ++CONFIG_SLUB_CPU_PARTIAL=y ++CONFIG_PROFILING=y ++CONFIG_JUMP_LABEL=y ++# CONFIG_UPROBES is not set ++# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set ++CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y ++CONFIG_HAVE_ARCH_TRACEHOOK=y ++CONFIG_HAVE_DMA_ATTRS=y ++CONFIG_HAVE_DMA_CONTIGUOUS=y ++CONFIG_GENERIC_SMP_IDLE_THREAD=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++CONFIG_HAVE_HW_BREAKPOINT=y ++CONFIG_HAVE_PERF_REGS=y ++CONFIG_HAVE_PERF_USER_STACK_DUMP=y ++CONFIG_HAVE_ARCH_JUMP_LABEL=y ++CONFIG_HAVE_RCU_TABLE_FREE=y ++CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y ++CONFIG_HAVE_CC_STACKPROTECTOR=y ++# CONFIG_CC_STACKPROTECTOR is not set ++CONFIG_CC_STACKPROTECTOR_NONE=y ++# CONFIG_CC_STACKPROTECTOR_REGULAR is not set ++# CONFIG_CC_STACKPROTECTOR_STRONG is not set ++CONFIG_HAVE_CONTEXT_TRACKING=y ++CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y ++CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y ++CONFIG_MODULES_USE_ELF_RELA=y ++CONFIG_CLONE_BACKWARDS=y ++CONFIG_OLD_SIGSUSPEND3=y ++CONFIG_COMPAT_OLD_SIGACTION=y ++ ++# ++# GCOV-based kernel profiling ++# ++# CONFIG_GCOV_KERNEL is not set ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++# CONFIG_MODVERSIONS is not set ++# CONFIG_MODULE_SRCVERSION_ALL is not set ++# CONFIG_MODULE_SIG is not set ++# CONFIG_MODULE_COMPRESS is not set ++CONFIG_STOP_MACHINE=y ++CONFIG_BLOCK=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++# CONFIG_BLK_CMDLINE_PARSER is not set ++ ++# ++# Partition Types ++# ++# CONFIG_PARTITION_ADVANCED is not set ++CONFIG_MSDOS_PARTITION=y ++CONFIG_EFI_PARTITION=y ++CONFIG_BLOCK_COMPAT=y ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++# CONFIG_IOSCHED_DEADLINE is not set ++CONFIG_IOSCHED_CFQ=y ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++CONFIG_UNINLINE_SPIN_UNLOCK=y ++CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y ++CONFIG_MUTEX_SPIN_ON_OWNER=y ++CONFIG_RWSEM_SPIN_ON_OWNER=y ++CONFIG_FREEZER=y ++ ++# ++# Platform selection ++# ++# CONFIG_ARCH_THUNDER is not set ++CONFIG_ARCH_VEXPRESS=y ++# CONFIG_ARCH_XGENE is not set ++CONFIG_ARCH_ESL_ARM_V8=y ++CONFIG_BUILTIN_DTB="esl_v8" ++ ++# ++# Bus support ++# ++CONFIG_ARM_AMBA=y ++# CONFIG_PCI is not set ++# CONFIG_PCI_DOMAINS is not set ++# CONFIG_PCI_DOMAINS_GENERIC is not set ++# CONFIG_PCI_SYSCALL is not set ++ ++# ++# Kernel Features ++# ++CONFIG_ARM64_4K_PAGES=y ++# CONFIG_ARM64_64K_PAGES is not set ++CONFIG_ARM64_VA_BITS_39=y ++# CONFIG_ARM64_VA_BITS_48 is not set ++CONFIG_ARM64_VA_BITS=39 ++CONFIG_ARM64_PGTABLE_LEVELS=3 ++# CONFIG_CPU_BIG_ENDIAN is not set ++CONFIG_SMP=y ++# CONFIG_SCHED_MC is not set ++# CONFIG_SCHED_SMT is not set ++CONFIG_NR_CPUS=8 ++CONFIG_HOTPLUG_CPU=y ++# CONFIG_PREEMPT_NONE is not set ++# CONFIG_PREEMPT_VOLUNTARY is not set ++CONFIG_PREEMPT=y ++CONFIG_PREEMPT_COUNT=y ++CONFIG_HZ=100 ++CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y ++CONFIG_ARCH_SPARSEMEM_ENABLE=y ++CONFIG_ARCH_SPARSEMEM_DEFAULT=y ++CONFIG_ARCH_SELECT_MEMORY_MODEL=y ++CONFIG_HAVE_ARCH_PFN_VALID=y ++CONFIG_HW_PERF_EVENTS=y ++CONFIG_SYS_SUPPORTS_HUGETLBFS=y ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y ++CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y ++CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_SPARSEMEM_MANUAL=y ++CONFIG_SPARSEMEM=y ++CONFIG_HAVE_MEMORY_PRESENT=y ++CONFIG_SPARSEMEM_EXTREME=y ++CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y ++CONFIG_SPARSEMEM_VMEMMAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_NO_BOOTMEM=y ++CONFIG_MEMORY_ISOLATION=y ++# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++CONFIG_COMPACTION=y ++CONFIG_MIGRATION=y ++CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_ZONE_DMA_FLAG=1 ++CONFIG_BOUNCE=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++# CONFIG_TRANSPARENT_HUGEPAGE is not set ++# CONFIG_CLEANCACHE is not set ++CONFIG_CMA=y ++# CONFIG_CMA_DEBUG is not set ++CONFIG_CMA_AREAS=7 ++# CONFIG_ZPOOL is not set ++# CONFIG_ZBUD is not set ++# CONFIG_ZSMALLOC is not set ++CONFIG_GENERIC_EARLY_IOREMAP=y ++# CONFIG_XEN is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++ ++# ++# Boot options ++# ++CONFIG_CMDLINE="console=ttyAMA0" ++# CONFIG_CMDLINE_FORCE is not set ++# CONFIG_EFI is not set ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_COMPAT_BINFMT_ELF=y ++CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y ++# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set ++CONFIG_BINFMT_SCRIPT=y ++# CONFIG_HAVE_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++CONFIG_COREDUMP=y ++CONFIG_COMPAT=y ++CONFIG_SYSVIPC_COMPAT=y ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_PM_SLEEP=y ++CONFIG_PM_SLEEP_SMP=y ++# CONFIG_PM_AUTOSLEEP is not set ++# CONFIG_PM_WAKELOCKS is not set ++# CONFIG_PM_RUNTIME is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++CONFIG_PM_CLK=y ++# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set ++CONFIG_CPU_PM=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_ARM64_CPU_SUSPEND=y ++ ++# ++# CPU Power Management ++# ++ ++# ++# CPU Idle ++# ++# CONFIG_CPU_IDLE is not set ++# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set ++ ++# ++# CPU Frequency scaling ++# ++# CONFIG_CPU_FREQ is not set ++# CONFIG_NET is not set ++CONFIG_HAVE_BPF_JIT=y ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++# CONFIG_UEVENT_HELPER is not set ++CONFIG_DEVTMPFS=y ++# CONFIG_DEVTMPFS_MOUNT is not set ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set ++CONFIG_ALLOW_DEV_COREDUMP=y ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_GENERIC_CPU_DEVICES is not set ++CONFIG_GENERIC_CPU_AUTOPROBE=y ++CONFIG_REGMAP=y ++# CONFIG_DMA_SHARED_BUFFER is not set ++CONFIG_DMA_CMA=y ++ ++# ++# Default contiguous memory area size: ++# ++CONFIG_CMA_SIZE_MBYTES=16 ++CONFIG_CMA_SIZE_SEL_MBYTES=y ++# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set ++# CONFIG_CMA_SIZE_SEL_MIN is not set ++# CONFIG_CMA_SIZE_SEL_MAX is not set ++CONFIG_CMA_ALIGNMENT=8 ++ ++# ++# Bus devices ++# ++# CONFIG_ARM_CCN is not set ++CONFIG_VEXPRESS_CONFIG=y ++# CONFIG_MTD is not set ++CONFIG_DTC=y ++CONFIG_OF=y ++ ++# ++# Device Tree and Open Firmware support ++# ++# CONFIG_OF_SELFTEST is not set ++CONFIG_OF_FLATTREE=y ++CONFIG_OF_EARLY_FLATTREE=y ++CONFIG_OF_ADDRESS=y ++CONFIG_OF_IRQ=y ++CONFIG_OF_RESERVED_MEM=y ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_NULL_BLK is not set ++# CONFIG_BLK_DEV_COW_COMMON is not set ++# CONFIG_BLK_DEV_LOOP is not set ++ ++# ++# DRBD disabled because PROC_FS or INET not selected ++# ++# CONFIG_BLK_DEV_RAM is not set ++# CONFIG_CDROM_PKTCDVD is not set ++CONFIG_VIRTIO_BLK=y ++ ++# ++# Misc devices ++# ++# CONFIG_SENSORS_LIS3LV02D is not set ++# CONFIG_DUMMY_IRQ is not set ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_SRAM is not set ++# CONFIG_VEXPRESS_SYSCFG is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_93CX6 is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++ ++# ++# Altera FPGA firmware download module ++# ++ ++# ++# Intel MIC Bus Driver ++# ++ ++# ++# Intel MIC Host Driver ++# ++ ++# ++# Intel MIC Card Driver ++# ++# CONFIG_ECHO is not set ++# CONFIG_CXL_BASE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_MQ_DEFAULT is not set ++# CONFIG_SCSI_PROC_FS is not set ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=y ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++# CONFIG_BLK_DEV_SR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++CONFIG_HAVE_PATA_PLATFORM=y ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++# CONFIG_INPUT_MATRIXKMAP is not set ++ ++# ++# Userland interfaces ++# ++# CONFIG_INPUT_MOUSEDEV is not set ++# CONFIG_INPUT_JOYDEV is not set ++# CONFIG_INPUT_EVDEV is not set ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++# CONFIG_INPUT_MISC is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=y ++# CONFIG_SERIO_SERPORT is not set ++# CONFIG_SERIO_AMBAKMI is not set ++CONFIG_SERIO_LIBPS2=y ++# CONFIG_SERIO_RAW is not set ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++# CONFIG_SERIO_ARC_PS2 is not set ++# CONFIG_SERIO_APBPS2 is not set ++# CONFIG_GAMEPORT is not set ++ ++# ++# Character devices ++# ++CONFIG_TTY=y ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_VT_CONSOLE_SLEEP=y ++CONFIG_HW_CONSOLE=y ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++CONFIG_LEGACY_PTYS=y ++CONFIG_LEGACY_PTY_COUNT=16 ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_TRACE_SINK is not set ++CONFIG_DEVKMEM=y ++ ++# ++# Serial drivers ++# ++CONFIG_SERIAL_EARLYCON=y ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++CONFIG_SERIAL_MSTAR=y ++CONFIG_SERIAL_MSTAR_UART_CONSOLE=y ++# CONFIG_SERIAL_AMBA_PL010 is not set ++# CONFIG_SERIAL_AMBA_PL011 is not set ++# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_SCCNXP is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_SERIAL_ARC is not set ++# CONFIG_SERIAL_FSL_LPUART is not set ++# CONFIG_VIRTIO_CONSOLE is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++ ++# ++# PCMCIA character devices ++# ++# CONFIG_RAW_DRIVER is not set ++# CONFIG_TCG_TPM is not set ++# CONFIG_XILLYBUS is not set ++ ++# ++# I2C support ++# ++# CONFIG_I2C is not set ++# CONFIG_SPI is not set ++# CONFIG_SPMI is not set ++# CONFIG_HSI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++ ++# ++# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. ++# ++CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++CONFIG_GPIO_DEVRES=y ++CONFIG_OF_GPIO=y ++# CONFIG_DEBUG_GPIO is not set ++# CONFIG_GPIO_SYSFS is not set ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_DWAPB is not set ++# CONFIG_GPIO_PL061 is not set ++# CONFIG_GPIO_SCH311X is not set ++# CONFIG_GPIO_XGENE is not set ++# CONFIG_GPIO_GRGPIO is not set ++ ++# ++# I2C GPIO expanders: ++# ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# LPC GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++ ++# ++# USB GPIO expanders: ++# ++# CONFIG_W1 is not set ++CONFIG_POWER_SUPPLY=y ++# CONFIG_POWER_SUPPLY_DEBUG is not set ++# CONFIG_PDA_POWER is not set ++# CONFIG_TEST_POWER is not set ++# CONFIG_BATTERY_DS2780 is not set ++# CONFIG_BATTERY_DS2781 is not set ++# CONFIG_BATTERY_BQ27x00 is not set ++# CONFIG_CHARGER_MAX8903 is not set ++# CONFIG_CHARGER_GPIO is not set ++CONFIG_POWER_RESET=y ++# CONFIG_POWER_RESET_GPIO is not set ++# CONFIG_POWER_RESET_GPIO_RESTART is not set ++# CONFIG_POWER_RESET_LTC2952 is not set ++CONFIG_POWER_RESET_VEXPRESS=y ++# CONFIG_POWER_RESET_XGENE is not set ++# CONFIG_POWER_RESET_SYSCON is not set ++# CONFIG_POWER_AVS is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++ ++# ++# Multifunction device drivers ++# ++# CONFIG_MFD_CORE is not set ++# CONFIG_MFD_CROS_EC is not set ++# CONFIG_MFD_HI6421_PMIC is not set ++# CONFIG_HTC_PASIC3 is not set ++# CONFIG_MFD_KEMPLD is not set ++# CONFIG_MFD_SM501 is not set ++# CONFIG_ABX500_CORE is not set ++# CONFIG_MFD_SYSCON is not set ++# CONFIG_MFD_TI_AM335X_TSCADC is not set ++# CONFIG_MFD_TPS65912 is not set ++# CONFIG_MFD_TMIO is not set ++# CONFIG_MFD_VEXPRESS_SYSREG is not set ++CONFIG_REGULATOR=y ++# CONFIG_REGULATOR_DEBUG is not set ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set ++# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set ++# CONFIG_REGULATOR_GPIO is not set ++# CONFIG_REGULATOR_VEXPRESS is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++ ++# ++# Direct Rendering Manager ++# ++# CONFIG_DRM is not set ++ ++# ++# Frame buffer Devices ++# ++# CONFIG_FB is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++# CONFIG_VGASTATE is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++# CONFIG_SOUND is not set ++ ++# ++# HID support ++# ++# CONFIG_HID is not set ++CONFIG_USB_OHCI_LITTLE_ENDIAN=y ++# CONFIG_USB_SUPPORT is not set ++# CONFIG_UWB is not set ++# CONFIG_MMC is not set ++# CONFIG_MEMSTICK is not set ++# CONFIG_NEW_LEDS is not set ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++# CONFIG_VIRT_DRIVERS is not set ++CONFIG_VIRTIO=y ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_BALLOON is not set ++CONFIG_VIRTIO_MMIO=y ++# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set ++ ++# ++# Microsoft Hyper-V guest support ++# ++# CONFIG_STAGING is not set ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_SOC_TI is not set ++CONFIG_CLKDEV_LOOKUP=y ++CONFIG_HAVE_CLK_PREPARE=y ++CONFIG_COMMON_CLK=y ++ ++# ++# Common Clock Framework ++# ++CONFIG_COMMON_CLK_VERSATILE=y ++# CONFIG_CLK_SP810 is not set ++# CONFIG_CLK_VEXPRESS_OSC is not set ++CONFIG_COMMON_CLK_XGENE=y ++# CONFIG_COMMON_CLK_PXA is not set ++# CONFIG_COMMON_CLK_QCOM is not set ++ ++# ++# Hardware Spinlock drivers ++# ++ ++# ++# Clock Source drivers ++# ++CONFIG_CLKSRC_OF=y ++CONFIG_ARM_ARCH_TIMER=y ++CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y ++# CONFIG_ATMEL_PIT is not set ++# CONFIG_SH_TIMER_CMT is not set ++# CONFIG_SH_TIMER_MTU2 is not set ++# CONFIG_SH_TIMER_TMU is not set ++# CONFIG_EM_TIMER_STI is not set ++# CONFIG_CLKSRC_VERSATILE is not set ++# CONFIG_MAILBOX is not set ++# CONFIG_IOMMU_SUPPORT is not set ++ ++# ++# Remoteproc drivers ++# ++# CONFIG_STE_MODEM_RPROC is not set ++ ++# ++# Rpmsg drivers ++# ++ ++# ++# SOC (System On Chip) specific Drivers ++# ++# CONFIG_PM_DEVFREQ is not set ++# CONFIG_EXTCON is not set ++# CONFIG_MEMORY is not set ++# CONFIG_IIO is not set ++# CONFIG_PWM is not set ++CONFIG_IRQCHIP=y ++CONFIG_ARM_GIC=y ++CONFIG_ARM_GIC_V3=y ++# CONFIG_IPACK_BUS is not set ++# CONFIG_RESET_CONTROLLER is not set ++# CONFIG_FMC is not set ++ ++# ++# PHY Subsystem ++# ++# CONFIG_GENERIC_PHY is not set ++# CONFIG_BCM_KONA_USB2_PHY is not set ++# CONFIG_PHY_XGENE is not set ++# CONFIG_POWERCAP is not set ++# CONFIG_MCB is not set ++ ++# ++# Firmware Drivers ++# ++# CONFIG_FIRMWARE_MEMMAP is not set ++ ++# ++# File systems ++# ++CONFIG_DCACHE_WORD_ACCESS=y ++# CONFIG_EXT2_FS is not set ++# CONFIG_EXT3_FS is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_USE_FOR_EXT23=y ++# CONFIG_EXT4_FS_POSIX_ACL is not set ++# CONFIG_EXT4_FS_SECURITY is not set ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_JBD2=y ++# CONFIG_JBD2_DEBUG is not set ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++# CONFIG_FS_POSIX_ACL is not set ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++# CONFIG_AUTOFS4_FS is not set ++CONFIG_FUSE_FS=y ++CONFIG_CUSE=y ++# CONFIG_OVERLAY_FS is not set ++ ++# ++# Caches ++# ++# CONFIG_FSCACHE is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++# CONFIG_ISO9660_FS is not set ++# CONFIG_UDF_FS is not set ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++# CONFIG_MSDOS_FS is not set ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" ++# CONFIG_NTFS_FS is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++# CONFIG_PROC_KCORE is not set ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_KERNFS=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLBFS is not set ++# CONFIG_HUGETLB_PAGE is not set ++# CONFIG_CONFIGFS_FS is not set ++# CONFIG_MISC_FILESYSTEMS is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="iso8859-1" ++CONFIG_NLS_CODEPAGE_437=y ++# CONFIG_NLS_CODEPAGE_737 is not set ++# CONFIG_NLS_CODEPAGE_775 is not set ++# CONFIG_NLS_CODEPAGE_850 is not set ++# CONFIG_NLS_CODEPAGE_852 is not set ++# CONFIG_NLS_CODEPAGE_855 is not set ++# CONFIG_NLS_CODEPAGE_857 is not set ++# CONFIG_NLS_CODEPAGE_860 is not set ++# CONFIG_NLS_CODEPAGE_861 is not set ++# CONFIG_NLS_CODEPAGE_862 is not set ++# CONFIG_NLS_CODEPAGE_863 is not set ++# CONFIG_NLS_CODEPAGE_864 is not set ++# CONFIG_NLS_CODEPAGE_865 is not set ++# CONFIG_NLS_CODEPAGE_866 is not set ++# CONFIG_NLS_CODEPAGE_869 is not set ++# CONFIG_NLS_CODEPAGE_936 is not set ++# CONFIG_NLS_CODEPAGE_950 is not set ++# CONFIG_NLS_CODEPAGE_932 is not set ++# CONFIG_NLS_CODEPAGE_949 is not set ++# CONFIG_NLS_CODEPAGE_874 is not set ++# CONFIG_NLS_ISO8859_8 is not set ++# CONFIG_NLS_CODEPAGE_1250 is not set ++# CONFIG_NLS_CODEPAGE_1251 is not set ++# CONFIG_NLS_ASCII is not set ++CONFIG_NLS_ISO8859_1=y ++# CONFIG_NLS_ISO8859_2 is not set ++# CONFIG_NLS_ISO8859_3 is not set ++# CONFIG_NLS_ISO8859_4 is not set ++# CONFIG_NLS_ISO8859_5 is not set ++# CONFIG_NLS_ISO8859_6 is not set ++# CONFIG_NLS_ISO8859_7 is not set ++# CONFIG_NLS_ISO8859_9 is not set ++# CONFIG_NLS_ISO8859_13 is not set ++# CONFIG_NLS_ISO8859_14 is not set ++# CONFIG_NLS_ISO8859_15 is not set ++# CONFIG_NLS_KOI8_R is not set ++# CONFIG_NLS_KOI8_U is not set ++# CONFIG_NLS_MAC_ROMAN is not set ++# CONFIG_NLS_MAC_CELTIC is not set ++# CONFIG_NLS_MAC_CENTEURO is not set ++# CONFIG_NLS_MAC_CROATIAN is not set ++# CONFIG_NLS_MAC_CYRILLIC is not set ++# CONFIG_NLS_MAC_GAELIC is not set ++# CONFIG_NLS_MAC_GREEK is not set ++# CONFIG_NLS_MAC_ICELAND is not set ++# CONFIG_NLS_MAC_INUIT is not set ++# CONFIG_NLS_MAC_ROMANIAN is not set ++# CONFIG_NLS_MAC_TURKISH is not set ++# CONFIG_NLS_UTF8 is not set ++# CONFIG_VIRTUALIZATION is not set ++ ++# ++# Kernel hacking ++# ++ ++# ++# printk and dmesg options ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_DYNAMIC_DEBUG is not set ++ ++# ++# Compile-time checks and compiler options ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_INFO_REDUCED is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set ++# CONFIG_DEBUG_INFO_DWARF4 is not set ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=2048 ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_READABLE_ASM is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++CONFIG_DEBUG_FS=y ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_ARCH_WANT_FRAME_POINTERS=y ++CONFIG_FRAME_POINTER=y ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++CONFIG_MAGIC_SYSRQ=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 ++CONFIG_DEBUG_KERNEL=y ++ ++# ++# Memory Debugging ++# ++# CONFIG_DEBUG_PAGEALLOC is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_SLUB_DEBUG_ON is not set ++# CONFIG_SLUB_STATS is not set ++CONFIG_HAVE_DEBUG_KMEMLEAK=y ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_VM is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++# CONFIG_DEBUG_PER_CPU_MAPS is not set ++# CONFIG_DEBUG_SHIRQ is not set ++ ++# ++# Debug Lockups and Hangs ++# ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_PANIC_ON_OOPS is not set ++CONFIG_PANIC_ON_OOPS_VALUE=0 ++CONFIG_PANIC_TIMEOUT=0 ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_SCHED_STACK_END_CHECK is not set ++# CONFIG_TIMER_STATS is not set ++CONFIG_DEBUG_PREEMPT=y ++ ++# ++# Lock Debugging (spinlocks, mutexes, etc...) ++# ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_LOCK_TORTURE_TEST is not set ++# CONFIG_STACKTRACE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++CONFIG_HAVE_DEBUG_BUGVERBOSE=y ++CONFIG_DEBUG_BUGVERBOSE=y ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_DEBUG_PI_LIST is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++ ++# ++# RCU Debugging ++# ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_TORTURE_TEST is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++CONFIG_RCU_CPU_STALL_TIMEOUT=21 ++CONFIG_RCU_CPU_STALL_VERBOSE=y ++# CONFIG_RCU_CPU_STALL_INFO is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_NOTIFIER_ERROR_INJECTION is not set ++# CONFIG_FAULT_INJECTION is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_SYSCALL_TRACEPOINTS=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++ ++# ++# Runtime Testing ++# ++# CONFIG_LKDTM is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_RBTREE_TEST is not set ++# CONFIG_INTERVAL_TREE_TEST is not set ++# CONFIG_PERCPU_TEST is not set ++CONFIG_ATOMIC64_SELFTEST=y ++# CONFIG_TEST_STRING_HELPERS is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_TEST_RHASHTABLE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_TEST_LKM is not set ++# CONFIG_TEST_USER_COPY is not set ++# CONFIG_TEST_FIRMWARE is not set ++# CONFIG_TEST_UDELAY is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_PID_IN_CONTEXTIDR is not set ++# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set ++# CONFIG_DEBUG_SET_MODULE_RONX is not set ++ ++# ++# Security options ++# ++# CONFIG_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=y ++CONFIG_CRYPTO_RNG2=y ++# CONFIG_CRYPTO_MANAGER is not set ++# CONFIG_CRYPTO_MANAGER2 is not set ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++# CONFIG_CRYPTO_PCRYPT is not set ++# CONFIG_CRYPTO_CRYPTD is not set ++# CONFIG_CRYPTO_MCRYPTD is not set ++# CONFIG_CRYPTO_AUTHENC is not set ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++# CONFIG_CRYPTO_SEQIV is not set ++ ++# ++# Block modes ++# ++# CONFIG_CRYPTO_CBC is not set ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++# CONFIG_CRYPTO_ECB is not set ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++# CONFIG_CRYPTO_CMAC is not set ++# CONFIG_CRYPTO_HMAC is not set ++# CONFIG_CRYPTO_XCBC is not set ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_CRC32 is not set ++# CONFIG_CRYPTO_CRCT10DIF is not set ++# CONFIG_CRYPTO_GHASH is not set ++# CONFIG_CRYPTO_MD4 is not set ++# CONFIG_CRYPTO_MD5 is not set ++# CONFIG_CRYPTO_MICHAEL_MIC is not set ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++# CONFIG_CRYPTO_SHA1 is not set ++# CONFIG_CRYPTO_SHA256 is not set ++# CONFIG_CRYPTO_SHA512 is not set ++# CONFIG_CRYPTO_TGR192 is not set ++# CONFIG_CRYPTO_WP512 is not set ++ ++# ++# Ciphers ++# ++CONFIG_CRYPTO_AES=y ++# CONFIG_CRYPTO_ANUBIS is not set ++# CONFIG_CRYPTO_ARC4 is not set ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++# CONFIG_CRYPTO_CAST5 is not set ++# CONFIG_CRYPTO_CAST6 is not set ++# CONFIG_CRYPTO_DES is not set ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++# CONFIG_CRYPTO_DEFLATE is not set ++# CONFIG_CRYPTO_ZLIB is not set ++# CONFIG_CRYPTO_LZO is not set ++# CONFIG_CRYPTO_LZ4 is not set ++# CONFIG_CRYPTO_LZ4HC is not set ++ ++# ++# Random Number Generation ++# ++CONFIG_CRYPTO_ANSI_CPRNG=y ++# CONFIG_CRYPTO_DRBG_MENU is not set ++CONFIG_CRYPTO_HW=y ++# CONFIG_CRYPTO_DEV_CCP is not set ++# CONFIG_ARM64_CRYPTO is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_GENERIC_STRNCPY_FROM_USER=y ++CONFIG_GENERIC_STRNLEN_USER=y ++CONFIG_GENERIC_PCI_IOMAP=y ++CONFIG_GENERIC_IOMAP=y ++CONFIG_GENERIC_IO=y ++CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y ++# CONFIG_CRC_CCITT is not set ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++# CONFIG_CRC_ITU_T is not set ++CONFIG_CRC32=y ++# CONFIG_CRC32_SELFTEST is not set ++CONFIG_CRC32_SLICEBY8=y ++# CONFIG_CRC32_SLICEBY4 is not set ++# CONFIG_CRC32_SARWATE is not set ++# CONFIG_CRC32_BIT is not set ++# CONFIG_CRC7 is not set ++# CONFIG_LIBCRC32C is not set ++# CONFIG_CRC8 is not set ++CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y ++# CONFIG_RANDOM32_SELFTEST is not set ++CONFIG_ZLIB_INFLATE=y ++CONFIG_LZO_COMPRESS=y ++CONFIG_LZO_DECOMPRESS=y ++CONFIG_LZ4_DECOMPRESS=y ++CONFIG_XZ_DEC=y ++CONFIG_XZ_DEC_X86=y ++CONFIG_XZ_DEC_POWERPC=y ++CONFIG_XZ_DEC_IA64=y ++CONFIG_XZ_DEC_ARM=y ++CONFIG_XZ_DEC_ARMTHUMB=y ++CONFIG_XZ_DEC_SPARC=y ++CONFIG_XZ_DEC_BCJ=y ++# CONFIG_XZ_DEC_TEST is not set ++CONFIG_DECOMPRESS_GZIP=y ++CONFIG_DECOMPRESS_BZIP2=y ++CONFIG_DECOMPRESS_LZMA=y ++CONFIG_DECOMPRESS_XZ=y ++CONFIG_DECOMPRESS_LZO=y ++CONFIG_DECOMPRESS_LZ4=y ++CONFIG_GENERIC_ALLOCATOR=y ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_DMA=y ++CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set ++# CONFIG_DDR is not set ++CONFIG_LIBFDT=y ++CONFIG_ARCH_HAS_SG_CHAIN=y +diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c +index b5853eec..85431f83 100644 +--- a/arch/arm64/kernel/setup.c ++++ b/arch/arm64/kernel/setup.c +@@ -106,6 +106,13 @@ static struct resource mem_res[] = { + #define kernel_code mem_res[0] + #define kernel_data mem_res[1] + ++ ++#ifdef CONFIG_BUILTIN_DTB ++extern char __dtb_start[]; ++extern char __dtb_end[]; ++void *builtin_dtb_start = __dtb_start; ++#endif ++ + void __init early_print(const char *str, ...) + { + char buf[256]; +@@ -304,16 +311,42 @@ static void __init setup_processor(void) + + static void __init setup_machine_fdt(phys_addr_t dt_phys) + { ++ void *dt_address=NULL; + if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) { ++#ifdef CONFIG_BUILTIN_DTB ++ early_print("\n" ++ "Warning: invalid external DTB at physical address 0x%p (virtual address 0x%p)\n" ++ "Try to load builtin DTB...\n", ++ dt_phys, phys_to_virt(dt_phys)); ++ ++ if(early_init_dt_scan(builtin_dtb_start)) ++ { ++ dt_address=builtin_dtb_start; ++ goto DT_SCAN_PASS; ++ } ++ else ++ { ++ early_print("\n" ++ "Error: both external DTB & builtin DTB are invalid.\n" ++ "\nSystem hang now...881...\n"); ++ } ++#else + early_print("\n" + "Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n" + "The dtb must be 8-byte aligned and passed in the first 512MB of memory\n" + "\nPlease check your bootloader.\n", + dt_phys, phys_to_virt(dt_phys)); +- ++#endif + while (true) + cpu_relax(); + } ++ else ++ { ++ dt_address=phys_to_virt(dt_phys); ++ } ++ ++DT_SCAN_PASS: ++ early_print("DTB loaded success at virtual address 0x%p\n\n",dt_address); + } + + /* +diff --git a/block/partitions/Makefile b/block/partitions/Makefile +index 37a95270..1eab15e6 100644 +--- a/block/partitions/Makefile ++++ b/block/partitions/Makefile +@@ -20,3 +20,4 @@ obj-$(CONFIG_IBM_PARTITION) += ibm.o + obj-$(CONFIG_EFI_PARTITION) += efi.o + obj-$(CONFIG_KARMA_PARTITION) += karma.o + obj-$(CONFIG_SYSV68_PARTITION) += sysv68.o ++obj-$(CONFIG_MS_EMMC) += emmc.o +\ No newline at end of file +diff --git a/block/partitions/check.c b/block/partitions/check.c +index 9ac1df74..fba1d5d9 100644 +--- a/block/partitions/check.c ++++ b/block/partitions/check.c +@@ -35,6 +35,9 @@ + #include "karma.h" + #include "sysv68.h" + #include "cmdline.h" ++#ifdef CONFIG_MS_EMMC ++#include "emmc.h" ++#endif + + int warn_no_part = 1; /*This is ugly: should make genhd removable media aware*/ + +@@ -43,6 +46,9 @@ static int (*check_part[])(struct parsed_partitions *) = { + * Probe partition formats with tables at disk address 0 + * that also have an ADFS boot block at 0xdc0. + */ ++#ifdef CONFIG_MS_EMMC ++ emmc_partition, ++#endif + #ifdef CONFIG_ACORN_PARTITION_ICS + adfspart_check_ICS, + #endif +diff --git a/block/partitions/emmc.c b/block/partitions/emmc.c +new file mode 100644 +index 00000000..d6903b06 +--- /dev/null ++++ b/block/partitions/emmc.c +@@ -0,0 +1,196 @@ ++/* ++ * fs/partitions/emmc.c ++ * ++ * Code extracted from drivers/block/genhd.c ++ * Copyright (C) 1991-1998 Linus Torvalds ++ * Re-organised Feb 1998 Russell King ++ */ ++ ++#include ++#include "check.h" ++#include "emmc.h" ++ ++//extern int get_NVRAM_start_sector(U32 *u32_startsector); ++extern int get_NVRAM_max_part_count(void); ++extern int get_DEVNODE_start_sector(unsigned int *u32_startsector); ++// ++///* ++// * read Driver Descriptor Block ++// */ ++//static int part_emmc_read_ddb (block_dev_desc_t *dev_desc, emmc_driver_desc_t *ddb_p) ++//{ ++// u32 u32_err; ++// ++// if(0 == g_eMMCDrv.u32_PartDevNodeStartSector){ ++// u32_err = eMMC_SearchDevNodeStartSector(); ++// if(eMMC_ST_SUCCESS != u32_err){ ++// printf ("** Err, %s **\n", __func__); ++// return (-1); ++// } ++// } ++// printf("read_ddb from: 0x%Xh\n", (unsigned int)g_eMMCDrv.u32_PartDevNodeStartSector); ++// ++// u32_err = eMMC_ReadData((uchar*)ddb_p, 512, g_eMMCDrv.u32_PartDevNodeStartSector); ++// if(eMMC_ST_SUCCESS != u32_err){ ++// printf ("** Can't read Driver Desriptor Block **\n"); ++// return (-1); ++// } ++// ++// if (ddb_p->signature != EMMC_DRIVER_MAGIC) { ++// printf ("** Bad Signature: expected 0x%04x, got 0x%04x\n", ++// EMMC_DRIVER_MAGIC, ddb_p->signature); ++// return (-1); ++// } ++// ++// return (0); ++//} ++// ++///* ++// * read Partition Descriptor Block ++// */ ++//static int part_emmc_read_pdb (block_dev_desc_t *dev_desc, int part_index, emmc_partition_t *pdb_p) ++//{ ++// u32 u32_err; ++// int part=part_index+=1; ++// ++// u32_err = eMMC_ReadData((uchar*)pdb_p, 512, ++// g_eMMCDrv.u32_PartDevNodeStartSector + part); ++// ++// if(eMMC_ST_SUCCESS != u32_err){ ++// printf ("** Can't read Driver Desriptor Block **\n"); ++// return (-1); ++// } ++// ++//// if (pdb_p->signature != EMMC_PARTITION_MAGIC) { ++//// //printf ("** Bad Signature: " ++//// // "expected 0x%04x, got 0x%04x\n", ++//// // EMMC_PARTITION_MAGIC, pdb_p->signature); ++//// return (-1); ++//// } ++// ++// return 0; ++//} ++ ++#define PART_START_BLK_OFFSET 1 ++ ++#include "linux/mmc/host.h" ++#include "linux/mmc/card.h" ++ ++struct mmc_card *mmc_blkdev_to_card(struct block_device *blkdev); ++extern bool mstar_mci_is_mstar_host(struct mmc_card* card); ++extern int get_NVRAM_max_part_count(void); ++extern int get_DEVNODE_start_sector(unsigned int *u32_startsector); ++ ++ ++bool __attribute__((weak)) mstar_mci_is_mstar_host(struct mmc_card* card) ++{ ++ return false; ++} ++ ++int __attribute__((weak)) get_NVRAM_max_part_count(void) ++{ ++ return 0; ++} ++ ++int __attribute__((weak)) get_DEVNODE_start_sector(unsigned int *u32_startsector) ++{ ++ return 0; ++} ++ ++int emmc_partition(struct parsed_partitions *state) ++{ ++ int slot = 1; ++ Sector sect; ++ int blk, blocks_in_map; ++ struct emmc_partition *part; ++ struct emmc_driver_desc *md; ++ struct mmc_card *card; ++ ++ unsigned int start_sector; ++ sect.v = NULL; ++ ++ card=mmc_blkdev_to_card(state->bdev); ++ ++ if((!card) || (!mstar_mci_is_mstar_host(card))) ++ { ++ return 0; ++ } ++ ++// if( NULL==(card) ++// || NULL==(card->host) ++// || NULL==(mci_host=((struct mstar_mci_host *)card->host->private) ) ++// || 0!=strnmp(mci_host->name,MSTAR_MCI_NAME,strlen(MSTAR_MCI_NAME)) ++// ) ++// { ++// return 0; ++// } ++ ++ printk(KERN_INFO"[EMMC] checking EMMC partitions...\n"); ++ ++ if(0!= get_DEVNODE_start_sector(&start_sector)) ++ { ++ printk(KERN_ERR"failed to get DEVNODE start sector!!\n"); ++ //put_dev_sector(sect); ++ return -1; ++ } ++ ++ ++ ++ /* Get 0th block and look at the first partition map entry. */ ++ md = read_part_sector(state, start_sector, §); ++ if ((!md )|| md->signature != EMMC_DRIVER_MAGIC) ++ { ++ printk(KERN_ERR"failed to read part sector or is not emmc!!!\n"); ++ if(sect.v != NULL) ++ put_dev_sector(sect); ++ return 0; ++ } ++ ++// if () { ++// //can not found the partiton map! ++// //printk("error founding EMMC_DRIVER_MAGIC!! MAGIC0x%x\n",md->signature); ++// put_dev_sector(sect); ++// return 0; ++// } ++// ++ ++ blocks_in_map=get_NVRAM_max_part_count(); ++ ++// part = (struct emmc_partition *)read_part_sector(state, start_sector+PART_START_BLK_OFFSET, §); ++// if ((!part)||part->signature != EMMC_PARTITION_MAGIC) ++// { ++// put_dev_sector(sect); ++// return 0; ++// } ++ ++ ++ for (blk = PART_START_BLK_OFFSET; blk <= blocks_in_map; ++blk) ++ { ++ ++ part = (struct emmc_partition *)read_part_sector(state, start_sector+(blk), §); ++ if (!part) ++ { ++ printk(KERN_ERR"failed to read part sector!!!\n"); ++ if(sect.v != NULL) ++ put_dev_sector(sect); ++ return -1; ++ } ++ ++ if (part->signature != EMMC_PARTITION_MAGIC) ++ { ++ continue; ++ } ++ ++ ++ put_partition(state, slot, (part->start_block), (part->block_count)); ++ strcpy(state->parts[slot].info.uuid, part->name); /* put parsed partition name into state */ ++ printk(KERN_INFO"[EMMC] partition[%d]: start=0x%08X, count=0x%08X, name='%s'\n", slot, part->start_block, part->block_count, part->name); ++ ++ ++slot; ++ } ++ ++ if(sect.v != NULL) ++ put_dev_sector(sect); ++ printk("\n"); ++ return 1; ++} +diff --git a/block/partitions/emmc.h b/block/partitions/emmc.h +new file mode 100644 +index 00000000..255e276c +--- /dev/null ++++ b/block/partitions/emmc.h +@@ -0,0 +1,51 @@ ++/* ++ * fs/partitions/emmc.h ++ */ ++ ++#define EMMC_PARTITION_MAGIC 0x5840 ++#define EMMC_RESERVED_FOR_MAP 10 ++ ++/* type field value for A/UX or other Unix partitions */ ++//#define APPLE_AUX_TYPE "Apple_UNIX_SVR2" ++ ++struct emmc_partition { ++ __be16 signature; /* expected to be MAC_PARTITION_MAGIC */ ++ __be16 res1; ++ __be32 map_count; /* # blocks in partition map */ ++ __be32 start_block; /* absolute starting block # of partition */ ++ __be32 block_count; /* number of blocks in partition */ ++ char name[32]; /* partition name */ ++ char type[32]; /* string type description */ ++ __be32 data_start; /* rel block # of first data block */ ++ __be32 data_count; /* number of data blocks */ ++ __be32 status; /* partition status bits */ ++ __be32 boot_start; ++ __be32 boot_size; ++ __be32 boot_load; ++ __be32 boot_load2; ++ __be32 boot_entry; ++ __be32 boot_entry2; ++ __be32 boot_cksum; ++ char processor[16]; /* identifies ISA of boot */ ++ /* there is more stuff after this that we don't need */ ++}; ++ ++#define EMMC_STATUS_BOOTABLE 8 /* partition is bootable */ ++ ++#define EMMC_DRIVER_MAGIC 0x1630 ++#define EMMC_PARTITIONTABLE_VERSION2 0x2000 ++ ++/* Driver descriptor structure, in block 0 */ ++struct emmc_driver_desc { ++ __be16 signature; /* expected to be EMMC_DRIVER_MAGIC */ ++ __be16 block_size; /* block size of device */ ++ __be32 block_count; /* number of blocks on device */ ++ __be16 dev_type; /* device type */ ++ __be16 dev_id; /* device id */ ++ __be32 data; /* reserved */ ++ __be16 version; /* version number of partition table */ ++ __be16 drvr_cnt; /* number of blocks reserved for partition table */ ++ /* ... more stuff */ ++}; ++ ++int emmc_partition(struct parsed_partitions *state); +diff --git a/crypto/testmgr.c b/crypto/testmgr.c +index 29a0cbdd..701757fd 100644 +--- a/crypto/testmgr.c ++++ b/crypto/testmgr.c +@@ -225,7 +225,7 @@ static int __test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, + tcrypt_complete, &tresult); + + j = 0; +- for (i = 0; i < tcount; i++) { ++ for (i = 1; i < tcount; i++) { + if (template[i].np) + continue; + +@@ -394,26 +394,23 @@ static int test_hash(struct crypto_ahash *tfm, struct hash_testvec *template, + { + unsigned int alignmask; + int ret; +- +- ret = __test_hash(tfm, template, tcount, use_digest, 0); +- if (ret) +- return ret; +- +- /* test unaligned buffers, check with one byte offset */ +- ret = __test_hash(tfm, template, tcount, use_digest, 1); +- if (ret) +- return ret; +- +- alignmask = crypto_tfm_alg_alignmask(&tfm->base); +- if (alignmask) { +- /* Check if alignment mask for tfm is correctly set. */ +- ret = __test_hash(tfm, template, tcount, use_digest, +- alignmask + 1); +- if (ret) +- return ret; +- } +- +- return 0; ++ ret = __test_hash(tfm, template, tcount, use_digest, 0); ++ if (ret) ++ return ret; ++ ++ /* test unaligned buffers, check with one byte offset */ ++ ret = __test_hash(tfm, template, tcount, use_digest, 1); ++ if (ret) ++ return ret; ++ alignmask = crypto_tfm_alg_alignmask(&tfm->base); ++ if (alignmask) { ++ /* Check if alignment mask for tfm is correctly set. */ ++ ret = __test_hash(tfm, template, tcount, use_digest, ++ alignmask + 1); ++ if (ret) ++ return ret; ++ } ++ return 0; + } + + static int __test_aead(struct crypto_aead *tfm, int enc, +@@ -849,56 +846,48 @@ static int test_cipher(struct crypto_cipher *tfm, int enc, + e = "encryption"; + else + e = "decryption"; +- + j = 0; +- for (i = 0; i < tcount; i++) { +- if (template[i].np) +- continue; +- +- j++; +- +- ret = -EINVAL; +- if (WARN_ON(template[i].ilen > PAGE_SIZE)) +- goto out; +- +- data = xbuf[0]; +- memcpy(data, template[i].input, template[i].ilen); +- +- crypto_cipher_clear_flags(tfm, ~0); +- if (template[i].wk) +- crypto_cipher_set_flags(tfm, CRYPTO_TFM_REQ_WEAK_KEY); +- +- ret = crypto_cipher_setkey(tfm, template[i].key, +- template[i].klen); +- if (!ret == template[i].fail) { +- printk(KERN_ERR "alg: cipher: setkey failed " +- "on test %d for %s: flags=%x\n", j, +- algo, crypto_cipher_get_flags(tfm)); +- goto out; +- } else if (ret) +- continue; +- +- for (k = 0; k < template[i].ilen; +- k += crypto_cipher_blocksize(tfm)) { +- if (enc) +- crypto_cipher_encrypt_one(tfm, data + k, +- data + k); +- else +- crypto_cipher_decrypt_one(tfm, data + k, +- data + k); +- } +- +- q = data; +- if (memcmp(q, template[i].result, template[i].rlen)) { +- printk(KERN_ERR "alg: cipher: Test %d failed " +- "on %s for %s\n", j, e, algo); +- hexdump(q, template[i].rlen); +- ret = -EINVAL; +- goto out; +- } +- } +- +- ret = 0; ++ for (i = 0; i < tcount; i++) { ++ if (template[i].np) ++ continue; ++ ++ j++; ++ ret = -EINVAL; ++ if (WARN_ON(template[i].ilen > PAGE_SIZE)) ++ goto out; ++ data = xbuf[0]; ++ memcpy(data, template[i].input, template[i].ilen); ++ crypto_cipher_clear_flags(tfm, ~0); ++ if (template[i].wk) ++ crypto_cipher_set_flags(tfm, CRYPTO_TFM_REQ_WEAK_KEY); ++ ret = crypto_cipher_setkey(tfm, template[i].key, ++ template[i].klen); ++ if (!ret == template[i].fail) { ++ printk(KERN_ERR "alg: cipher: setkey failed " ++ "on test %d for %s: flags=%x\n", j, ++ algo, crypto_cipher_get_flags(tfm)); ++ goto out; ++ } else if (ret) ++ continue; ++ for (k = 0; k < template[i].ilen; ++ k += crypto_cipher_blocksize(tfm)) { ++ if (enc) ++ crypto_cipher_encrypt_one(tfm, data + k, ++ data + k); ++ else ++ crypto_cipher_decrypt_one(tfm, data + k, ++ data + k); ++ } ++ q = data; ++ if (memcmp(q, template[i].result, template[i].rlen)) { ++ printk(KERN_ERR "alg: cipher: Test %d failed " ++ "on %s for %s\n", j, e, algo); ++ hexdump(q, template[i].rlen); ++ ret = -EINVAL; ++ goto out; ++ } ++ } ++ ret = 0; + + out: + testmgr_free_buf(xbuf); +diff --git a/drivers/Kconfig b/drivers/Kconfig +index 1a693d3f..1a784d04 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -182,4 +182,16 @@ source "drivers/ras/Kconfig" + + source "drivers/thunderbolt/Kconfig" + ++ ++source "drivers/cmem/Kconfig" ++ ++menuconfig MSTAR_DRIVERS ++ bool "MStar SoC platform drivers" ++ depends on ARCH_MSTAR ++ default n ++ ++if ( MSTAR_DRIVERS ) ++source "drivers/mstar/Kconfig" ++endif ++ + endmenu +diff --git a/drivers/Makefile b/drivers/Makefile +index ebee5553..5e3be538 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -161,3 +161,5 @@ obj-$(CONFIG_POWERCAP) += powercap/ + obj-$(CONFIG_MCB) += mcb/ + obj-$(CONFIG_RAS) += ras/ + obj-$(CONFIG_THUNDERBOLT) += thunderbolt/ ++obj-$(CONFIG_MSTAR_DRIVERS) += mstar/ ++obj-$(CONFIG_TI_CMEM) += cmem/ +diff --git a/drivers/char/random.c b/drivers/char/random.c +index 9cd6968e..572fae8d 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -661,7 +661,7 @@ retry: + if (r == &nonblocking_pool) { + prandom_reseed_late(); + wake_up_interruptible(&urandom_init_wait); +- pr_notice("random: %s pool is initialized\n", r->name); ++ pr_debug("random: %s pool is initialized\n", r->name); + } + } + +diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c +index 7d74830e..d7afecbc 100644 +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -1534,9 +1534,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate) + /* prevent racing with updates to the clock topology */ + clk_prepare_lock(); + ++#ifndef CONFIG_ARCH_MSTAR + /* bail early if nothing to do */ + if (rate == clk_get_rate(clk)) + goto out; ++#endif + + if ((clk->flags & CLK_SET_RATE_GATE) && clk->prepare_count) { + ret = -EBUSY; +@@ -1680,8 +1682,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent) + /* prevent racing with updates to the clock topology */ + clk_prepare_lock(); + ++#ifndef CONFIG_ARCH_MSTAR + if (clk->parent == parent) + goto out; ++#endif + + /* check that we are allowed to re-parent if the clock is in use */ + if ((clk->flags & CLK_SET_PARENT_GATE) && clk->prepare_count) { +diff --git a/drivers/cmem/Kconfig b/drivers/cmem/Kconfig +new file mode 100644 +index 00000000..27939044 +--- /dev/null ++++ b/drivers/cmem/Kconfig +@@ -0,0 +1,7 @@ ++config TI_CMEM ++ config TI_CMEM ++ tristate "TI Contiguous Memory Manager" ++ select TI_CMEM_STUB ++ help ++ ++ +\ No newline at end of file +diff --git a/drivers/cmem/Makefile b/drivers/cmem/Makefile +new file mode 100644 +index 00000000..fcda3646 +--- /dev/null ++++ b/drivers/cmem/Makefile +@@ -0,0 +1,3 @@ ++#EXTRA_CFLAGS += -D__DEBUG ++#obj-y += cmemk_stub.o ++obj-$(CONFIG_TI_CMEM) += cmemk.o +diff --git a/drivers/cmem/cmemk.c b/drivers/cmem/cmemk.c +new file mode 100644 +index 00000000..78f9ed05 +--- /dev/null ++++ b/drivers/cmem/cmemk.c +@@ -0,0 +1,2853 @@ ++/* ++ * Copyright (C) 2007-2014 Texas Instruments Incorporated - http://www.ti.com ++ * ++ * This program is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; version 2 of the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see ++ */ ++/* ++ * cmemk.c ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++ ++/* ++ * USE_MMAPSEM means acquire/release current->mm->mmap_sem around calls ++ * to dma_[flush/clean/inv]_range. ++ */ ++//#define USE_MMAPSEM ++ ++/* ++ * CHECK_FOR_ALLOCATED_BUFFER means ensure that the passed addr/size block ++ * is actually an allocated, CMEM-defined buffer. ++ */ ++//#define CHECK_FOR_ALLOCATED_BUFFER ++ ++/* HEAP_ALIGN is used in place of sizeof(HeapMem_Header) */ ++#define HEAP_ALIGN PAGE_SIZE ++ ++ ++#ifdef __DEBUG ++#define __D(fmt, args...) printk(KERN_DEBUG "CMEMK Debug: " fmt, ## args) ++#else ++#define __D(fmt, args...) ++#endif ++ ++#define __E(fmt, args...) printk(KERN_ERR "CMEMK Error: " fmt, ## args) ++ ++#define MAXTYPE(T) ((T) (((T)1 << ((sizeof(T) * 8) - 1) ^ ((T) -1)))) ++ ++/* ++ * Change here for supporting more than 4 blocks. Also change all ++ * NBLOCKS-based arrays to have NBLOCKS-worth of initialization values. ++ */ ++#define NBLOCKS 4 ++ ++#define BLOCK_IOREMAP (1 << 0) ++#define BLOCK_MEMREGION (1 << 1) ++#define BLOCK_REGION (1 << 2) ++ ++#ifndef VM_RESERVED ++#define VM_RESERVED 0x00080000 ++#endif ++ ++static struct vm_struct *ioremap_area; ++static unsigned int nblocks = 0; ++static unsigned int block_flags[NBLOCKS] = {0, 0, 0, 0}; ++static unsigned long long block_start[NBLOCKS] = {0, 0, 0, 0}; ++static unsigned long long block_end[NBLOCKS] = {0, 0, 0, 0}; ++static unsigned long long block_avail_size[NBLOCKS] = {0, 0, 0, 0}; ++static unsigned int total_num_buffers[NBLOCKS] = {0, 0, 0, 0}; ++static int pool_num_buffers[NBLOCKS][MAX_POOLS]; ++static unsigned long long pool_size[NBLOCKS][MAX_POOLS]; ++ ++static int cmem_major; ++static struct proc_dir_entry *cmem_proc_entry; ++static atomic_t reference_count = ATOMIC_INIT(0); ++static unsigned int version = CMEM_VERSION; ++ ++static struct class *cmem_class; ++ ++/* Register the module parameters. */ ++MODULE_PARM_DESC(phys_start, "\n\t\t Start Address for CMEM Pool Memory"); ++static char *phys_start = NULL; ++MODULE_PARM_DESC(phys_end, "\n\t\t End Address for CMEM Pool Memory"); ++static char *phys_end = NULL; ++module_param(phys_start, charp, S_IRUGO); ++module_param(phys_end, charp, S_IRUGO); ++ ++static int npools[NBLOCKS + 1] = {0, 0, 0, 0, 0}; ++ ++static char *pools[MAX_POOLS] = { ++ NULL ++}; ++MODULE_PARM_DESC(pools, ++ "\n\t\t List of Pool Sizes and Number of Entries, comma separated," ++ "\n\t\t decimal sizes"); ++module_param_array(pools, charp, &npools[0], S_IRUGO); ++ ++/* begin block 1 */ ++MODULE_PARM_DESC(phys_start_1, "\n\t\t Start Address for Extended CMEM Pool Memory"); ++static char *phys_start_1 = NULL; ++MODULE_PARM_DESC(phys_end_1, "\n\t\t End Address for Extended CMEM Pool Memory"); ++static char *phys_end_1 = NULL; ++module_param(phys_start_1, charp, S_IRUGO); ++module_param(phys_end_1, charp, S_IRUGO); ++ ++static char *pools_1[MAX_POOLS] = { ++ NULL ++}; ++MODULE_PARM_DESC(pools_1, ++ "\n\t\t List of Pool Sizes and Number of Entries, comma separated," ++ "\n\t\t decimal sizes, for Extended CMEM Pool"); ++module_param_array(pools_1, charp, &npools[1], S_IRUGO); ++/* end block 1 */ ++ ++/* begin block 2 */ ++MODULE_PARM_DESC(phys_start_2, "\n\t\t Start Address for Extended CMEM Pool Memory"); ++static char *phys_start_2 = NULL; ++MODULE_PARM_DESC(phys_end_2, "\n\t\t End Address for Extended CMEM Pool Memory"); ++static char *phys_end_2 = NULL; ++module_param(phys_start_2, charp, S_IRUGO); ++module_param(phys_end_2, charp, S_IRUGO); ++ ++static char *pools_2[MAX_POOLS] = { ++ NULL ++}; ++MODULE_PARM_DESC(pools_2, ++ "\n\t\t List of Pool Sizes and Number of Entries, comma separated," ++ "\n\t\t decimal sizes, for Extended CMEM Pool"); ++module_param_array(pools_2, charp, &npools[2], S_IRUGO); ++/* end block 2 */ ++ ++/* cut-and-paste below as part of adding support for more than 4 blocks */ ++/* begin block 3 */ ++MODULE_PARM_DESC(phys_start_3, "\n\t\t Start Address for Extended CMEM Pool Memory"); ++static char *phys_start_3 = NULL; ++MODULE_PARM_DESC(phys_end_3, "\n\t\t End Address for Extended CMEM Pool Memory"); ++static char *phys_end_3 = NULL; ++module_param(phys_start_3, charp, S_IRUGO); ++module_param(phys_end_3, charp, S_IRUGO); ++ ++static char *pools_3[MAX_POOLS] = { ++ NULL ++}; ++MODULE_PARM_DESC(pools_3, ++ "\n\t\t List of Pool Sizes and Number of Entries, comma separated," ++ "\n\t\t decimal sizes, for Extended CMEM Pool"); ++module_param_array(pools_3, charp, &npools[3], S_IRUGO); ++/* end block 3 */ ++/* cut-and-paste above as part of adding support for more than 4 blocks */ ++ ++static int allowOverlap = -1; ++MODULE_PARM_DESC(allowOverlap, ++ "\n\t\t DEPRECATED - ignored if found" ++ "\n\t\t Set to 1 if cmem range is allowed to overlap memory range" ++ "\n\t\t allocated to kernel physical mem (via mem=xxx)"); ++module_param(allowOverlap, int, S_IRUGO); ++ ++static int useHeapIfPoolUnavailable = 0; ++MODULE_PARM_DESC(useHeapIfPoolUnavailable, ++ "\n\t\t Set to 1 if you want a pool-based allocation request to" ++ "\n\t\t fall back to a heap-based allocation attempt"); ++module_param(useHeapIfPoolUnavailable, int, S_IRUGO); ++ ++static struct mutex cmem_mutex; ++ ++/* Describes a pool buffer */ ++typedef struct pool_buffer { ++ struct list_head element; ++ struct list_head users; ++ dma_addr_t dma; /* used only for CMA-based allocs */ ++ int id; ++ phys_addr_t physp; ++ int flags; /* CMEM_CACHED or CMEM_NONCACHED */ ++ void *kvirtp; /* used only for CMA-based allocs */ ++ unsigned long long size; /* used only for heap-based allocs */ ++ struct device *dev; /* used only for CMA-based allocs */ ++} pool_buffer; ++ ++typedef struct registered_user { ++ struct list_head element; ++ struct file *filp; ++} registered_user; ++ ++#ifdef CMEM_KERNEL_STUB ++ ++#include ++ ++typedef struct pool_object pool_object; ++ ++#else ++ ++/* Describes a pool */ ++typedef struct pool_object { ++ struct list_head freelist; ++ struct list_head busylist; ++ unsigned int numbufs; ++ unsigned long long size; ++ unsigned long long reqsize; ++} pool_object; ++ ++static int cmem_cma_npools = 0; ++static int cmem_cma_heapsize = 0; ++static struct device *cmem_cma_dev; ++static struct pool_object *cmem_cma_p_objs; ++ ++#endif ++ ++/* ++ * For CMA allocations we treat p_objs[NBLOCKS] as a special "pool" array. ++ */ ++static pool_object p_objs[NBLOCKS + 1][MAX_POOLS]; ++ ++ ++/* Forward declaration of system calls */ ++static long ioctl(struct file *filp, unsigned int cmd, unsigned long args); ++static int mmap(struct file *filp, struct vm_area_struct *vma); ++static int open(struct inode *inode, struct file *filp); ++static int release(struct inode *inode, struct file *filp); ++ ++static struct file_operations cmem_fxns = { ++ owner: THIS_MODULE, ++ unlocked_ioctl: ioctl, ++ mmap: mmap, ++ open: open, ++ release: release ++}; ++ ++ ++/* ++ * NOTE: The following implementation of a heap is taken from the ++ * DSP/BIOS 6.0 source tree (avala-f15/src/ti/sysbios/heaps). Changes ++ * are necessary due to the fact that CMEM is not built in an XDC ++ * build environment, and therefore XDC types and helper APIs (e.g., ++ * Assert) are not available. However, these changes were kept to a ++ * minimum. ++ * ++ * The changes include: ++ * - renaming XDC types to standard C types ++ * - replacing sizeof(HeapMem_Header) w/ HEAP_ALIGN throughout ++ * ++ * As merged with CMEM, the heap becomes a distinguished "pool" and ++ * is sometimes treated specially, and at other times can be treated ++ * as a normal pool instance. ++ */ ++ ++/* ++ * HeapMem compatibility stuff ++ */ ++typedef struct HeapMem_Header { ++ phys_addr_t next; ++ size_t size; ++} HeapMem_Header; ++ ++#define ALLOCRUN 0 ++#define DRYRUN 1 ++ ++phys_addr_t HeapMem_alloc(int bi, size_t size, size_t align, int dryrun); ++void HeapMem_free(int bi, phys_addr_t block, size_t size); ++ ++/* ++ * Heap configuration stuff ++ * ++ * For CMA global heap allocations, we treat heap_pool[NBLOCKS] as ++ * its own block. For example, if you have 4 physically-specified ++ * blocks then NBLOCKS = 4. heap_pool[0]|[1]|[2]|[3] are the real blocks, and ++ * heap_pool[4] represents the global CMA area. ++ * ++ * Only heap_pool[] gets extended with NBLOCKS + 1 dimension, since the ++ * other heap_*[] arrays are used only with the real blocks. You can't ++ * use heap_pool[NBLOCKS] for HeapMem_alloc(). ++ */ ++static int heap_pool[NBLOCKS + 1] = {-1, -1, -1, -1, 0}; ++ ++static unsigned long heap_size[NBLOCKS] = {0, 0, 0, 0}; ++static phys_addr_t heap_physp[NBLOCKS] = {0, 0, 0, 0}; ++static HeapMem_Header heap_head[NBLOCKS] = { ++ { ++ 0, /* next */ ++ 0 /* size */ ++ }, ++ { ++ 0, /* next */ ++ 0 /* size */ ++ }, ++ { ++ 0, /* next */ ++ 0 /* size */ ++ }, ++/* cut-and-paste below as part of adding support for more than 4 blocks */ ++ { ++ 0, /* next */ ++ 0 /* size */ ++ }, ++/* cut-and-paste above as part of adding support for more than 4 blocks */ ++}; ++ ++static int map_header(void **vaddrp, phys_addr_t physp, struct vm_struct **vm) ++{ ++ unsigned long vaddr; ++ ++ *vm = __get_vm_area(PAGE_SIZE, VM_IOREMAP, VMALLOC_START, VMALLOC_END); ++ if (!*vm) { ++ __E("__get_vm_area() failed\n"); ++ ++ return -ENOMEM; ++ } ++ ++ vaddr = (unsigned long)(*vm)->addr; ++ ioremap_page_range((unsigned long)vaddr, (unsigned long)vaddr + PAGE_SIZE, ++ physp, PAGE_KERNEL); ++ *vaddrp = (*vm)->addr; ++ ++ __D("map_header: ioremap_page_range(%#llx, %#lx)=0x%p\n", ++ (unsigned long long)physp, PAGE_SIZE, *vaddrp); ++ ++ return 0; ++} ++ ++static void unmap_header(void *vaddr, struct vm_struct *vm) ++{ ++ __D("unmap_header: unmap_kernel_page_rage(0x%p, %#lx)\n", vaddr, PAGE_SIZE); ++ ++ unmap_kernel_range_noflush((unsigned long)vaddr, PAGE_SIZE); ++ free_vm_area(vm); ++} ++ ++/* ++ * ======== HeapMem_alloc ======== ++ * HeapMem is implemented such that all of the memory and blocks it works ++ * with have an alignment that is a multiple of HEAP_ALIGN and have a size ++ * which is a multiple of HEAP_ALIGN. Maintaining this requirement ++ * throughout the implementation ensures that there are never any odd ++ * alignments or odd block sizes to deal with. ++ * ++ * Specifically: ++ * The buffer managed by HeapMem: ++ * 1. Is aligned on a multiple of HEAP_ALIGN ++ * 2. Has an adjusted size that is a multiple of HEAP_ALIGN ++ * All blocks on the freelist: ++ * 1. Are aligned on a multiple of HEAP_ALIGN ++ * 2. Have a size that is a multiple of HEAP_ALIGN ++ * All allocated blocks: ++ * 1. Are aligned on a multiple of HEAP_ALIGN ++ * 2. Have a size that is a multiple of HEAP_ALIGN ++ * ++ */ ++phys_addr_t HeapMem_alloc(int bi, size_t reqSize, size_t reqAlign, int dryrun) ++{ ++ struct vm_struct *curHeader_vm_area; ++ struct vm_struct *prevHeader_vm_area; ++ struct vm_struct *newHeader_vm_area; ++ HeapMem_Header *curHeader; ++ HeapMem_Header *prevHeader; ++ HeapMem_Header *newHeader; ++ phys_addr_t curHeaderPhys; ++ phys_addr_t prevHeaderPhys = 0; ++ phys_addr_t newHeaderPhys = 0; /* init to quiet compiler */ ++ phys_addr_t allocAddr; ++ size_t curSize, adjSize; ++ size_t remainSize; /* free memory after allocated memory */ ++ size_t adjAlign, offset; ++ ++ adjSize = reqSize; ++ ++ /* Make size requested a multiple of HEAP_ALIGN */ ++ if ((offset = (adjSize & (HEAP_ALIGN - 1))) != 0) { ++ adjSize = adjSize + (HEAP_ALIGN - offset); ++ } ++ ++ /* ++ * Make sure the alignment is at least as large as HEAP_ALIGN. ++ * Note: adjAlign must be a power of 2 (by function constraint) and ++ * HEAP_ALIGN is also a power of 2, ++ */ ++ adjAlign = reqAlign; ++ if (adjAlign & (HEAP_ALIGN - 1)) { ++ /* adjAlign is less than HEAP_ALIGN */ ++ adjAlign = HEAP_ALIGN; ++ } ++ ++ /* ++ * The block will be allocated from curHeader. Maintain a pointer to ++ * prevHeader so prevHeader->next can be updated after the alloc. ++ */ ++ curHeaderPhys = heap_head[bi].next; ++ ++ /* Loop over the free list. */ ++ while (curHeaderPhys != 0) { ++ map_header((void **)&curHeader, curHeaderPhys, &curHeader_vm_area); ++ curSize = curHeader->size; ++ ++ /* ++ * Determine the offset from the beginning to make sure ++ * the alignment request is honored. ++ */ ++ offset = (unsigned long)curHeaderPhys & (adjAlign - 1); ++ if (offset) { ++ offset = adjAlign - offset; ++ } ++ ++ /* big enough? */ ++ if (curSize >= (adjSize + offset)) { ++ /* Set the pointer that will be returned. Alloc from front */ ++ allocAddr = curHeaderPhys + offset; ++ ++ if (dryrun) { ++ return allocAddr; ++ } ++ ++ /* ++ * Determine the remaining memory after the allocated block. ++ * Note: this cannot be negative because of above comparison. ++ */ ++ remainSize = curSize - adjSize - offset; ++ ++ if (remainSize) { ++ newHeaderPhys = allocAddr + adjSize; ++ map_header((void **)&newHeader, newHeaderPhys, ++ &newHeader_vm_area); ++ ++ newHeader->next = curHeader->next; ++ newHeader->size = remainSize; ++ ++ unmap_header(newHeader, newHeader_vm_area); ++ } ++ ++ /* ++ * If there is memory at the beginning (due to alignment ++ * requirements), maintain it in the list. ++ * ++ * offset and remainSize must be multiples of ++ * HEAP_ALIGN. Therefore the address of the newHeader ++ * below must be a multiple of the HEAP_ALIGN, thus ++ * maintaining the requirement. ++ */ ++ if (offset) { ++ /* Adjust the curHeader size accordingly */ ++ curHeader->size = offset; ++ ++ /* ++ * If there is remaining memory, add into the free list. ++ * Note: no need to coalesce and we have HeapMem locked so ++ * it is safe. ++ */ ++ if (remainSize) { ++ curHeader->next = newHeaderPhys; ++ } ++ } ++ else { ++ /* ++ * If there is any remaining, link it in, ++ * else point to the next free block. ++ * Note: no need to coalesce and we have HeapMem locked so ++ * it is safe. ++ */ ++ if (prevHeaderPhys != 0) { ++ map_header((void **)&prevHeader, prevHeaderPhys, ++ &prevHeader_vm_area); ++ } ++ else { ++ prevHeader = &heap_head[bi]; ++ } ++ ++ if (remainSize) { ++ prevHeader->next = newHeaderPhys; ++ } ++ else { ++ prevHeader->next = curHeader->next; ++ } ++ ++ if (prevHeader != &heap_head[bi]) { ++ unmap_header(prevHeader, prevHeader_vm_area); ++ } ++ } ++ ++ unmap_header(curHeader, curHeader_vm_area); ++ ++ /* Success, return the allocated memory */ ++ return allocAddr; ++ } ++ else { ++ prevHeaderPhys = curHeaderPhys; ++ curHeaderPhys = curHeader->next; ++ ++ unmap_header(curHeader, curHeader_vm_area); ++ } ++ } ++ ++ return 0; ++} ++ ++/* ++ * ======== HeapMem_free ======== ++ */ ++void HeapMem_free(int bi, phys_addr_t block, size_t size) ++{ ++ struct vm_struct *curHeader_vm_area; ++ struct vm_struct *newHeader_vm_area; ++ struct vm_struct *nextHeader_vm_area; ++ HeapMem_Header *curHeader; ++ HeapMem_Header *newHeader; ++ HeapMem_Header *nextHeader; ++ phys_addr_t curHeaderPhys = 0; ++ phys_addr_t newHeaderPhys; ++ phys_addr_t nextHeaderPhys; ++ size_t offset; ++ ++ /* Restore size to actual allocated size */ ++ if ((offset = size & (HEAP_ALIGN - 1)) != 0) { ++ size += HEAP_ALIGN - offset; ++ } ++ ++ newHeaderPhys = block; ++ nextHeaderPhys = heap_head[bi].next; ++ ++ /* Go down freelist and find right place for buf */ ++ while (nextHeaderPhys != 0 && nextHeaderPhys < newHeaderPhys) { ++ map_header((void **)&nextHeader, nextHeaderPhys, &nextHeader_vm_area); ++ ++ curHeaderPhys = nextHeaderPhys; ++ nextHeaderPhys = nextHeader->next; ++ ++ unmap_header(nextHeader, nextHeader_vm_area); ++ } ++ ++ map_header((void **)&newHeader, newHeaderPhys, &newHeader_vm_area); ++ ++ if (curHeaderPhys != 0) { ++ map_header((void **)&curHeader, curHeaderPhys, &curHeader_vm_area); ++ } ++ else { ++ curHeader = &heap_head[bi]; ++ } ++ ++ newHeader->next = nextHeaderPhys; ++ newHeader->size = size; ++ curHeader->next = newHeaderPhys; ++ ++ /* Join contiguous free blocks */ ++ /* Join with upper block */ ++ if (nextHeaderPhys != 0 && (newHeaderPhys + size) == nextHeaderPhys) { ++ map_header((void **)&nextHeader, nextHeaderPhys, &nextHeader_vm_area); ++ ++ newHeader->next = nextHeader->next; ++ newHeader->size += nextHeader->size; ++ ++ unmap_header(nextHeader, nextHeader_vm_area); ++ } ++ ++ /* ++ * Join with lower block. Make sure to check to see if not the ++ * first block. ++ */ ++ if (curHeader != &heap_head[bi]) { ++ if ((curHeaderPhys + curHeader->size) == newHeaderPhys) { ++ curHeader->next = newHeader->next; ++ curHeader->size += newHeader->size; ++ } ++ ++ unmap_header(curHeader, curHeader_vm_area); ++ } ++ ++ unmap_header(newHeader, newHeader_vm_area); ++} ++ ++/* Traverses the page tables and translates a virtual address to a physical. */ ++static phys_addr_t get_phys(void *virtp) ++{ ++ unsigned long virt = (unsigned long)virtp; ++ phys_addr_t physp = ~(0LL); ++ struct mm_struct *mm = current->mm; ++ struct vm_area_struct *vma; ++ ++ /* For kernel direct-mapped memory, take the easy way */ ++ if (virt >= PAGE_OFFSET) { ++ physp = virt_to_phys(virtp); ++ __D("get_phys: virt_to_phys translated direct-mapped %#lx to %#llx\n", ++ virt, (unsigned long long)physp); ++ } ++ ++ /* this will catch, kernel-allocated, mmaped-to-usermode addresses */ ++ else if ((vma = find_vma(mm, virt)) && ++ (vma->vm_flags & VM_IO) && ++ (vma->vm_pgoff)) { ++ physp = ((unsigned long long)vma->vm_pgoff << PAGE_SHIFT) + ++ (virt - vma->vm_start); ++ __D("get_phys: find_vma translated user %#lx to %#llx\n", virt, ++ (unsigned long long)physp); ++ } ++ ++ /* otherwise, use get_user_pages() for general userland pages */ ++ else { ++ int res, nr_pages = 1; ++ struct page *pages; ++ ++ down_read(¤t->mm->mmap_sem); ++ res = get_user_pages(current, current->mm, virt, nr_pages, 1, 0, ++ &pages, NULL); ++ up_read(¤t->mm->mmap_sem); ++ ++ if (res == nr_pages) { ++ physp = __pa(page_address(&pages[0]) + (virt & ~PAGE_MASK)); ++ __D("get_phys: get_user_pages translated user %#lx to %#llx\n", ++ virt, (unsigned long long)physp); ++ } else { ++ __E("%s: Unable to find phys addr for %#lx\n", ++ __FUNCTION__, virt); ++ __E("%s: get_user_pages() failed: %d\n", __FUNCTION__, res); ++ } ++ } ++ ++ return physp; ++} ++ ++/* Allocates space from the top "highmem" contiguous buffer for pool buffer. */ ++static phys_addr_t alloc_pool_buffer(int bi, unsigned long long size) ++{ ++ phys_addr_t physp; ++ ++ __D("alloc_pool_buffer: Called for size 0x%llx\n", size); ++ ++ if (size <= block_avail_size[bi]) { ++ __D("alloc_pool_buffer: Fits req %#llx < avail: %#llx\n", ++ size, block_avail_size[bi]); ++ block_avail_size[bi] -= size; ++ physp = block_start[bi] + block_avail_size[bi]; ++ ++ __D("alloc_pool_buffer: new available block size is %#llx\n", ++ block_avail_size[bi]); ++ ++ __D("alloc_pool_buffer: returning allocated buffer at %#llx\n", ++ (unsigned long long)physp); ++ ++ return physp; ++ } ++ ++ __E("Failed to find a big enough free block\n"); ++ ++ return 0; ++} ++ ++ ++#ifdef __DEBUG ++/* Only for debug */ ++static void dump_lists(int bi, int idx) ++{ ++ struct list_head *freelistp = &p_objs[bi][idx].freelist; ++ struct list_head *busylistp = &p_objs[bi][idx].busylist; ++ struct list_head *e; ++ struct pool_buffer *entry; ++ ++/* way too chatty, neuter for now */ ++return; ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return; ++ } ++ ++ __D("Busylist for pool %d:\n", idx); ++ for (e = busylistp->next; e != busylistp; e = e->next) { ++ ++ entry = list_entry(e, struct pool_buffer, element); ++ ++ __D("Busy: Buffer with id %d and physical address %#llx\n", ++ entry->id, (unsigned long long)entry->physp); ++ } ++ ++ __D("Freelist for pool %d:\n", idx); ++ for (e = freelistp->next; e != freelistp; e = e->next) { ++ ++ entry = list_entry(e, struct pool_buffer, element); ++ ++ __D("Free: Buffer with id %d and physical address %#llx\n", ++ entry->id, (unsigned long long)entry->physp); ++ } ++ ++ mutex_unlock(&cmem_mutex); ++} ++#endif ++ ++/* ++ * ======== find_busy_entry ======== ++ * find_busy_entry looks for an allocated pool buffer containing ++ * physical addr physp -> (physp + *sizep). ++ * ++ * Should be called with the cmem_mutex held. ++ */ ++static struct pool_buffer *find_busy_entry(phys_addr_t physp, int *poolp, struct list_head **ep, int *bip, size_t *sizep) ++{ ++ struct list_head *busylistp; ++ struct list_head *e; ++ struct pool_buffer *entry; ++ int num_pools; ++ int i; ++ int bi; ++ ++ /* loop for NBLOCKS + 1 to handle special CMA global area "block" */ ++ for (bi = 0; bi < (NBLOCKS + 1); bi++) { ++ num_pools = npools[bi]; ++ if (heap_pool[bi] != -1) { ++ num_pools++; ++ } ++ ++ for (i = 0; i < num_pools; i++) { ++ busylistp = &p_objs[bi][i].busylist; ++ ++ for (e = busylistp->next; e != busylistp; e = e->next) { ++ entry = list_entry(e, struct pool_buffer, element); ++ if ((!sizep && entry->physp == physp) || ++ (sizep && ++ (physp >= entry->physp && ++ (physp + *sizep) <= (entry->physp + entry->size) ++ ) ++ ) ++ ) { ++ if (poolp) { ++ *poolp = i; ++ } ++ if (ep) { ++ *ep = e; ++ } ++ if (bip) { ++ *bip = bi; ++ } ++ ++ return entry; ++ } ++ } ++ } ++ } ++ ++ return NULL; ++} ++ ++static void cmem_seq_stop(struct seq_file *s, void *v); ++static void *cmem_seq_start(struct seq_file *s, loff_t *pos); ++static void *cmem_seq_next(struct seq_file *s, void *v, loff_t *pos); ++static int cmem_seq_show(struct seq_file *s, void *v); ++ ++static struct seq_operations cmem_seq_ops = { ++ .start = cmem_seq_start, ++ .next = cmem_seq_next, ++ .stop = cmem_seq_stop, ++ .show = cmem_seq_show, ++}; ++ ++#define SHOW_BUSY_BANNER (1 << 0) ++#define SHOW_PREV_FREE_BANNER (1 << 1) ++#define SHOW_LAST_FREE_BANNER (1 << 2) ++#define BUSY_ENTRY (1 << 3) ++#define FREE_ENTRY (1 << 4) ++ ++void *find_buffer_n(struct seq_file *s, int n) ++{ ++ struct list_head *listp = NULL; ++ int busy_empty; ++ int free_empty = 0; ++ int found = 0; ++ int count; ++ int i; ++ int bi; ++ ++ __D("find_buffer_n: n=%d\n", n); ++ ++ s->private = (void *)0; ++ count = 0; ++ ++ for (bi = 0; bi < NBLOCKS; bi++) { ++ for (i = 0; i < npools[bi]; i++) { ++ listp = &p_objs[bi][i].busylist; ++ listp = listp->next; ++ busy_empty = 1; ++ while (listp != &p_objs[bi][i].busylist) { ++ busy_empty = 0; ++ if (count == n) { ++ found = 1; ++ s->private = (void *)((int)s->private | BUSY_ENTRY); ++ ++ break; ++ } ++ count++; ++ listp = listp->next; ++ } ++ if (found) { ++ break; ++ } ++ ++ listp = &p_objs[bi][i].freelist; ++ listp = listp->next; ++ free_empty = 1; ++ while (listp != &p_objs[bi][i].freelist) { ++ if (i == 0 || ++ (p_objs[bi][i - 1].freelist.next != ++ &p_objs[bi][i - 1].freelist)) { ++ ++ free_empty = 0; ++ } ++ if (count == n) { ++ found = 1; ++ s->private = (void *)((int)s->private | FREE_ENTRY); ++ ++ break; ++ } ++ count++; ++ listp = listp->next; ++ } ++ if (found) { ++ break; ++ } ++ } ++ if (found) { ++ break; ++ } ++ } ++ ++ if (!found) { ++ listp = NULL; ++ } ++ else { ++ if (busy_empty) { ++ s->private = (void *)((int)s->private | SHOW_BUSY_BANNER); ++ } ++ if (free_empty) { ++ s->private = (void *)((int)s->private | SHOW_PREV_FREE_BANNER); ++ } ++ if (count == (total_num_buffers[bi] - 1)) { ++ s->private = (void *)((int)s->private | SHOW_LAST_FREE_BANNER); ++ } ++ } ++ ++ return listp; ++} ++ ++static void cmem_seq_stop(struct seq_file *s, void *v) ++{ ++ __D("cmem_seq_stop: v=0x%p\n", v); ++ ++ mutex_unlock(&cmem_mutex); ++} ++ ++static void *cmem_seq_start(struct seq_file *s, loff_t *pos) ++{ ++ struct list_head *listp; ++ int total_num; ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return ERR_PTR(-ERESTARTSYS); ++ } ++ ++ __D("cmem_seq_start: *pos=%d\n", (int)*pos); ++ ++ total_num = total_num_buffers[0] + total_num_buffers[1]; ++ if (*pos >= total_num) { ++ __D(" %d >= %d\n", (int)*pos, total_num); ++ ++ return NULL; ++ } ++ ++ listp = find_buffer_n(s, *pos); ++ ++ __D(" returning 0x%p\n", listp); ++ ++ return listp; ++} ++ ++static void *cmem_seq_next(struct seq_file *s, void *v, loff_t *pos) ++{ ++ struct list_head *listp; ++ int total_num; ++ ++ __D("cmem_seq_next: *pos=%d\n", (int)*pos); ++ ++ __D(" incrementing *pos\n"); ++ ++(*pos); ++ ++ total_num = total_num_buffers[0] + total_num_buffers[1]; ++ if (*pos >= total_num) { ++ __D(" %d >= %d\n", (int)*pos, total_num); ++ ++ return NULL; ++ } ++ ++ listp = find_buffer_n(s, *pos); ++ ++ __D(" returning 0x%p\n", listp); ++ ++ return listp; ++} ++ ++int show_busy_banner(int bi, struct seq_file *s, int n) ++{ ++ return seq_printf(s, "\nBlock %d: Pool %d: %d bufs size 0x%llx" ++ " (0x%llx requested)\n\nPool %d busy bufs:\n", ++ bi, n, p_objs[bi][n].numbufs, p_objs[bi][n].size, ++ p_objs[bi][n].reqsize, n); ++} ++ ++int show_free_banner(struct seq_file *s, int n) ++{ ++ return seq_printf(s, "\nPool %d free bufs:\n", n); ++} ++ ++/* ++ * Show one pool entry, w/ banners for first entries in a pool's busy or ++ * free list. ++ */ ++static int cmem_seq_show(struct seq_file *s, void *v) ++{ ++ struct list_head *listp = v; ++ struct list_head *e = v; ++ struct pool_buffer *entry; ++ char *attr; ++ int i; ++ int bi; ++ int rv; ++ ++ __D("cmem_seq_show:\n"); ++ ++ for (bi = 0; bi < NBLOCKS; bi++) { ++ /* look for banners to show */ ++ for (i = 0; i < npools[bi]; i++) { ++ if (listp == p_objs[bi][i].busylist.next) { ++ /* first buffer in busylist */ ++ if ((int)s->private & SHOW_PREV_FREE_BANNER) { ++ /* ++ * Previous pool's freelist empty, need to show banner. ++ */ ++ show_free_banner(s, i - 1); ++ } ++ show_busy_banner(bi, s, i); ++ ++ break; ++ } ++ if (listp == p_objs[bi][i].freelist.next) { ++ /* first buffer in freelist */ ++ if ((int)s->private & SHOW_PREV_FREE_BANNER) { ++ /* ++ * Previous pool's freelist & this pool's busylist empty, ++ * need to show banner. ++ */ ++ show_free_banner(s, i - 1); ++ } ++ if ((int)s->private & SHOW_BUSY_BANNER) { ++ /* ++ * This pool's busylist empty, need to show banner. ++ */ ++ show_busy_banner(bi, s, i); ++ } ++ show_free_banner(s, i); ++ ++ break; ++ } ++ } ++ } ++ ++ entry = list_entry(e, struct pool_buffer, element); ++ ++ /* ++ * Check the final seq_printf return value. No need to check previous ++ * ones, since if they fail then the seq_file object is not changed and ++ * any subsequent seq_printf will also fail w/o changing the object. ++ */ ++ if ((int)s->private & BUSY_ENTRY) { ++ attr = entry->flags & CMEM_CACHED ? "(cached)" : "(noncached)"; ++ rv = seq_printf(s, "id %d: phys addr %#llx %s\n", entry->id, ++ (unsigned long long)entry->physp, attr); ++ } ++ else { ++ rv = seq_printf(s, "id %d: phys addr %#llx\n", entry->id, ++ (unsigned long long)entry->physp); ++ } ++ if (rv == -1) { ++ __D("seq_printf returned -1\n"); ++ ++ return -1; ++ } ++ ++ if ((int)s->private & BUSY_ENTRY && ++ (int)s->private & SHOW_LAST_FREE_BANNER) { ++ ++ /* FIXME */ ++ rv = show_free_banner(s, npools[0] - 1); ++ if (rv == -1) { ++ __D("seq_printf returned -1\n"); ++ ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++static int cmem_proc_open(struct inode *inode, struct file *file); ++ ++static struct file_operations cmem_proc_ops = { ++ .owner = THIS_MODULE, ++ .open = cmem_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = seq_release, ++}; ++ ++static int cmem_proc_open(struct inode *inode, struct file *file) ++{ ++ return seq_open(file, &cmem_seq_ops); ++} ++ ++/* Allocate a contiguous memory pool. */ ++static int alloc_pool(int bi, int idx, int num, unsigned long long reqsize, phys_addr_t *physpRet) ++{ ++ struct pool_buffer *entry; ++ struct list_head *freelistp = &p_objs[bi][idx].freelist; ++ struct list_head *busylistp = &p_objs[bi][idx].busylist; ++ unsigned long long size = PAGE_ALIGN(reqsize); ++ phys_addr_t physp; ++ int i; ++ ++ __D("Allocating %d buffers of size 0x%llx (requested 0x%llx)\n", ++ num, size, reqsize); ++ ++ p_objs[bi][idx].reqsize = reqsize; ++ p_objs[bi][idx].numbufs = num; ++ p_objs[bi][idx].size = size; ++ ++ INIT_LIST_HEAD(freelistp); ++ INIT_LIST_HEAD(busylistp); ++ ++ for (i = 0; i < num; i++) { ++ entry = kmalloc(sizeof(struct pool_buffer), GFP_KERNEL); ++ ++ if (!entry) { ++ __E("alloc_pool failed to malloc pool_buffer struct"); ++ return -ENOMEM; ++ } ++ ++ physp = alloc_pool_buffer(bi, size); ++ ++ if (physp == 0) { ++ __E("alloc_pool failed to get contiguous area of size %llu\n", ++ size); ++ ++ /* ++ * Need to free this entry now since it didn't get added to ++ * a list that will be freed during module removal (cmem_exit()) ++ * Fixes SDSCM00027040. ++ */ ++ kfree(entry); ++ ++ return -ENOMEM; ++ } ++ ++ entry->id = i; ++ entry->physp = physp; ++ entry->size = size; ++ INIT_LIST_HEAD(&entry->users); ++ ++ if (physpRet) { ++ *physpRet++ = physp; ++ } ++ ++ __D("Allocated buffer %d, physical %#llx and size %#llx\n", ++ entry->id, (unsigned long long)entry->physp, size); ++ ++ list_add_tail(&entry->element, freelistp); ++ } ++ ++#ifdef __DEBUG ++ dump_lists(bi, idx); ++#endif ++ ++ return 0; ++} ++ ++struct block_struct { ++ void *addr; ++ size_t size; ++}; ++ ++static long ioctl(struct file *filp, unsigned int cmd, unsigned long args) ++{ ++ unsigned int __user *argp = (unsigned int __user *) args; ++ unsigned long long __user *llargp = (unsigned long long __user *) args; ++ unsigned long virtArg; ++ unsigned long long physArg; ++ struct list_head *freelistp = NULL; ++ struct list_head *busylistp = NULL; ++ struct list_head *registeredlistp; ++ struct list_head *e = NULL; ++ struct list_head *u; ++ struct list_head *unext; ++ struct pool_buffer *entry; ++ struct registered_user *user; ++ phys_addr_t physp; ++ void *virtp; ++ void *virtp_end; ++ dma_addr_t dma = 0; ++ size_t reqsize, align; ++ size_t size = 0; ++ unsigned long long lsize, lreqsize; ++ unsigned long long delta = MAXTYPE(unsigned long long); ++ int pool = -1; ++ int i; ++ int bi; ++ int id; ++ int pool_alloc; ++ struct block_struct block; ++ union CMEM_AllocUnion allocDesc; ++ struct device *dev = NULL; ++ ++ if (_IOC_TYPE(cmd) != _IOC_TYPE(CMEM_IOCMAGIC)) { ++ __E("ioctl(): bad command type %#x (should be %#x)\n", ++ _IOC_TYPE(cmd), _IOC_TYPE(CMEM_IOCMAGIC)); ++ } ++ ++ switch (cmd & CMEM_IOCCMDMASK) { ++ case CMEM_IOCALLOCHEAP: ++ if (copy_from_user(&allocDesc, argp, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ size = allocDesc.alloc_heap_inparams.size; ++ align = allocDesc.alloc_heap_inparams.align; ++ bi = allocDesc.alloc_heap_inparams.blockid; ++ ++ if (bi == CMEM_CMABLOCKID) { ++ bi = NBLOCKS; ++ ++ if (cmem_cma_heapsize == 0) { ++ __D("no explicit CMEM CMA heap, using global area\n"); ++ dev = NULL; ++ } ++ else { ++ dev = &cmem_cma_dev[heap_pool[bi]]; ++ } ++ } ++ ++ __D("ALLOCHEAP%s ioctl received on heap pool for block %d\n", ++ cmd & CMEM_CACHED ? "CACHED" : "", bi); ++ ++ if (bi > NBLOCKS || bi < 0) { ++ __E("ioctl: invalid block id %d, must be < %d\n", ++ bi, NBLOCKS); ++ return -EINVAL; ++ } ++ ++ /* heap_pool[NBLOCKS] (the CMA heap) is always available */ ++ if (bi < NBLOCKS && heap_pool[bi] == -1) { ++ __E("ioctl: no heap available in block %d\n", bi); ++ return -EINVAL; ++ } ++ ++ pool = heap_pool[bi]; ++ ++ pool_alloc = 0; ++alloc: ++ entry = kmalloc(sizeof(struct pool_buffer), GFP_KERNEL); ++ if (!entry) { ++ __E("ioctl: failed to kmalloc pool_buffer struct for heap"); ++ ++ return -ENOMEM; ++ } ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ size = PAGE_ALIGN(size); ++ ++ if (bi == NBLOCKS) { ++ virtp = dma_alloc_coherent(dev, size, &dma, GFP_KERNEL); ++ ++#if IS_ENABLED(CONFIG_ARCH_KEYSTONE) && IS_ENABLED(CONFIG_ARM_LPAE) ++ /* adjust from 32-bit alias to 36-bit phys */ ++ physp = dma + 0x780000000ULL; ++#else ++ physp = dma; ++#endif ++ entry->dev = dev; ++ entry->kvirtp = virtp; ++ } ++ else { ++ physp = HeapMem_alloc(bi, size, align, ALLOCRUN); ++ ++ /* set only for test just below here */ ++ virtp = (void *)(unsigned int)physp; ++ } ++ ++ if (virtp == NULL) { ++ __E("ioctl: failed to allocate heap buffer of size %#x\n", ++ size); ++ ++ mutex_unlock(&cmem_mutex); ++ kfree(entry); ++ ++ return -ENOMEM; ++ } ++ ++ entry->dma = dma; ++ entry->id = pool; ++ entry->physp = physp; ++ entry->size = size; ++ entry->flags = cmd & ~CMEM_IOCCMDMASK; ++ INIT_LIST_HEAD(&entry->users); ++ ++ busylistp = &p_objs[bi][pool].busylist; ++ list_add_tail(&entry->element, busylistp); ++ ++ user = kmalloc(sizeof(struct registered_user), GFP_KERNEL); ++ user->filp = filp; ++ list_add(&user->element, &entry->users); ++ ++ mutex_unlock(&cmem_mutex); ++ ++ if (pool_alloc) { ++ allocDesc.alloc_pool_outparams.physp = physp; ++ allocDesc.alloc_pool_outparams.size = size; ++ ++ if (copy_to_user(argp, &allocDesc, sizeof(allocDesc))) { ++ mutex_unlock(&cmem_mutex); ++ return -EFAULT; ++ } ++ } ++ else { ++ if (put_user(physp, llargp)) { ++ return -EFAULT; ++ } ++ } ++ ++ __D("ALLOCHEAP%s: allocated %#x size buffer at %#llx (phys address)\n", ++ cmd & CMEM_CACHED ? "CACHED" : "", (size_t)entry->size, ++ (unsigned long long)entry->physp); ++ ++ break; ++ ++ /* ++ * argp contains a pointer to an alloc descriptor coming in, and the ++ * physical address and size of the allocated buffer when returning. ++ */ ++ case CMEM_IOCALLOC: ++ if (copy_from_user(&allocDesc, argp, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ pool = allocDesc.alloc_pool_inparams.poolid; ++ bi = allocDesc.alloc_pool_inparams.blockid; ++ ++ if (bi == CMEM_CMABLOCKID) { ++ bi = NBLOCKS; ++ } ++ ++ __D("ALLOC%s ioctl received on pool %d for memory block %d\n", ++ cmd & CMEM_CACHED ? "CACHED" : "", pool, bi); ++ ++ if (bi > NBLOCKS || bi < 0) { ++ __E("ioctl: invalid block id %d, must be < %d\n", ++ bi, NBLOCKS); ++ return -EINVAL; ++ } ++ ++ if (pool >= npools[bi] || pool < 0) { ++ __E("ALLOC%s: invalid pool (%d) passed.\n", ++ cmd & CMEM_CACHED ? "CACHED" : "", pool); ++ return -EINVAL; ++ } ++ ++ if (bi == NBLOCKS) { ++ lsize = p_objs[bi][pool].size; ++ dev = &cmem_cma_dev[pool]; ++ align = 0; ++ pool_alloc = 1; ++ ++ goto alloc; ++ } ++ ++ busylistp = &p_objs[bi][pool].busylist; ++ freelistp = &p_objs[bi][pool].freelist; ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ e = freelistp->next; ++ if (e == freelistp) { ++ __E("ALLOC%s: No free buffers available for pool %d\n", ++ cmd & CMEM_CACHED ? "CACHED" : "", pool); ++ mutex_unlock(&cmem_mutex); ++ return -ENOMEM; ++ } ++ entry = list_entry(e, struct pool_buffer, element); ++ ++ allocDesc.alloc_pool_outparams.physp = entry->physp; ++ allocDesc.alloc_pool_outparams.size = p_objs[bi][pool].size; ++ ++ if (copy_to_user(argp, &allocDesc, sizeof(allocDesc))) { ++ mutex_unlock(&cmem_mutex); ++ return -EFAULT; ++ } ++ ++ entry->flags = cmd & ~CMEM_IOCCMDMASK; ++ ++ list_del_init(e); ++ list_add(e, busylistp); ++ ++ user = kmalloc(sizeof(struct registered_user), GFP_KERNEL); ++ user->filp = filp; ++ list_add(&user->element, &entry->users); ++ ++ mutex_unlock(&cmem_mutex); ++ ++ __D("ALLOC%s: allocated a buffer at %#llx (phys address)\n", ++ cmd & CMEM_CACHED ? "CACHED" : "", ++ (unsigned long long)entry->physp); ++ ++#ifdef __DEBUG ++ dump_lists(bi, pool); ++#endif ++ break; ++ ++ /* ++ * argp contains either the user virtual address or the physical ++ * address of the buffer to free coming in, and contains the pool ++ * where it was freed from and the size of the block on return. ++ */ ++ case CMEM_IOCFREE: ++ __D("FREE%s%s ioctl received.\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", ++ cmd & CMEM_PHYS ? "PHYS" : ""); ++ ++ if (!(cmd & CMEM_PHYS)) { ++ if (get_user(virtArg, argp)) { ++ return -EFAULT; ++ } ++ ++ physp = get_phys((void *)virtArg); ++ ++ if (physp == ~(0LL)) { ++ __E("FREE%s: Failed to convert virtual %#lx to physical\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", virtArg); ++ return -EFAULT; ++ } ++ ++ virtp = (void *)virtArg; ++ ++ __D("FREE%s: translated 0x%p user virtual to %#llx physical\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", ++ virtp, (unsigned long long)physp); ++ } ++ else { ++ virtp = 0L; /* silence the compiler warning */ ++ if (copy_from_user(&physArg, llargp, ++ sizeof(unsigned long long))) { ++ return -EFAULT; ++ } ++ physp = physArg; ++ } ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ size = 0; ++ ++ entry = find_busy_entry(physp, &pool, &e, &bi, NULL); ++ if (entry) { ++ /* record values in case entry gets kfree()'d for CMEM_HEAP */ ++ id = entry->id; ++ size = (size_t)entry->size; ++ ++ registeredlistp = &entry->users; ++ u = registeredlistp->next; ++ while (u != registeredlistp) { ++ unext = u->next; ++ ++ user = list_entry(u, struct registered_user, element); ++ if (user->filp == filp) { ++ __D("FREE%s%s: Removing file 0x%p from user list of buffer %#llx...\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", ++ cmd & CMEM_PHYS ? "PHYS" : "", ++ filp, (unsigned long long)physp); ++ ++ list_del(u); ++ kfree(user); ++ ++ break; ++ } ++ ++ u = unext; ++ } ++ ++ if (u == registeredlistp) { ++ __E("FREE%s%s: Not a registered user of physical buffer %#llx\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", ++ cmd & CMEM_PHYS ? "PHYS" : "", ++ (unsigned long long)physp); ++ mutex_unlock(&cmem_mutex); ++ ++ return -EFAULT; ++ } ++ ++ if (registeredlistp->next == registeredlistp) { ++ /* no more registered users, free buffer */ ++ if (bi == NBLOCKS || pool == heap_pool[bi]) { ++ if (!(cmd & CMEM_PHYS) && bi != NBLOCKS) { ++ /* ++ * Need to invalidate possible cached entry for ++ * user's virt addr since the kernel is about to ++ * do a non-cached write to the entry in ++ * HeapMem_free() ++ */ ++ virtp_end = virtp + size; ++ outer_inv_range(physp, physp + size); ++ dmac_map_area(virtp, size, DMA_FROM_DEVICE); ++ ++ __D("FREEHEAP: invalidated user virtual " ++ "0x%p -> 0x%p\n", virtp, virtp_end); ++ } ++ ++ if (bi == NBLOCKS) { ++ dma_free_coherent(entry->dev, (size_t)entry->size, ++ entry->kvirtp, entry->dma); ++ } ++ else { ++ HeapMem_free(bi, entry->physp, (size_t)entry->size); ++ } ++ list_del(e); ++ kfree(entry); ++ } ++ else { ++ list_del_init(e); ++ list_add(e, &p_objs[bi][pool].freelist); ++ } ++ ++ __D("FREE%s%s: Successfully freed buffer %d from pool %d\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", ++ cmd & CMEM_PHYS ? "PHYS" : "", id, pool); ++ } ++ } ++ ++ mutex_unlock(&cmem_mutex); ++ ++ if (!entry) { ++ __E("Failed to free memory at %#llx\n", ++ (unsigned long long)physp); ++ return -EFAULT; ++ } ++ ++#ifdef __DEBUG ++ dump_lists(bi, pool); ++#endif ++ if (cmd & CMEM_PHYS) { ++ __D("FREE%sPHYS: returning\n", cmd & CMEM_HEAP ? "HEAP" : ""); ++ } ++ else { ++ if (pool == heap_pool[bi]) { ++ allocDesc.free_outparams.size = size; ++ } ++ else { ++ allocDesc.free_outparams.size = p_objs[bi][pool].size; ++ } ++ allocDesc.free_outparams.poolid = pool; ++ if (copy_to_user(argp, &allocDesc, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ __D("FREE%s%s: returning size 0x%x, poolid %d\n", ++ cmd & CMEM_HEAP ? "HEAP" : "", ++ cmd & CMEM_PHYS ? "PHYS" : "", ++ allocDesc.free_outparams.size, ++ allocDesc.free_outparams.poolid); ++ } ++ ++ break; ++ ++ /* ++ * argp contains the user virtual address of the buffer to translate ++ * coming in, and the translated physical address on return. ++ */ ++ case CMEM_IOCGETPHYS: ++ __D("GETPHYS ioctl received.\n"); ++ if (get_user(virtArg, argp)) { ++ return -EFAULT; ++ } ++ ++ physp = get_phys((void *)virtArg); ++ ++ if (physp == ~(0LL)) { ++ __E("GETPHYS: Failed to convert virtual %#lx to physical.\n", ++ virtArg); ++ return -EFAULT; ++ } ++ ++ if (put_user(physp, llargp)) { ++ return -EFAULT; ++ } ++ ++ __D("GETPHYS: returning %#llx\n", (unsigned long long)physp); ++ break; ++ ++ /* ++ * argp contains the pool to query for size coming in, and the size ++ * of the pool on return. ++ */ ++ case CMEM_IOCGETSIZE: ++ __D("GETSIZE ioctl received\n"); ++ if (copy_from_user(&allocDesc, argp, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ pool = allocDesc.get_size_inparams.poolid; ++ bi = allocDesc.get_size_inparams.blockid; ++ ++ if (bi == CMEM_CMABLOCKID) { ++ bi = NBLOCKS; ++ } ++ ++ if (bi > NBLOCKS || bi < 0) { ++ __E("ioctl: invalid block id %d, must be < %d\n", ++ bi, NBLOCKS); ++ return -EINVAL; ++ } ++ ++ if (pool >= npools[bi] || pool < 0) { ++ __E("GETSIZE: invalid pool (%d) passed.\n", pool); ++ return -EINVAL; ++ } ++ ++ if (put_user(p_objs[bi][pool].size, argp)) { ++ return -EFAULT; ++ } ++ __D("GETSIZE returning %#llx\n", p_objs[bi][pool].size); ++ break; ++ ++ /* ++ * argp contains the requested pool buffers size coming in, and the ++ * pool id (index) on return. ++ */ ++ case CMEM_IOCGETPOOL: ++ __D("GETPOOL ioctl received.\n"); ++ if (copy_from_user(&allocDesc, argp, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ lreqsize = allocDesc.get_pool_inparams.size; ++ bi = allocDesc.get_pool_inparams.blockid; ++ ++ if (bi == CMEM_CMABLOCKID) { ++ bi = NBLOCKS; ++ } ++ ++ if (bi > NBLOCKS || bi < 0) { ++ __E("ioctl: invalid block id %d, must be < %d\n", ++ bi, NBLOCKS); ++ return -EINVAL; ++ } ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ __D("GETPOOL: Trying to find a pool to fit size %#llx\n", lreqsize); ++ for (i = 0; i < npools[bi]; i++) { ++ lsize = p_objs[bi][i].size; ++ freelistp = &p_objs[bi][i].freelist; ++ ++ __D("GETPOOL: size (%#llx) > reqsize (%#llx)?\n", ++ lsize, lreqsize); ++ if (lsize >= lreqsize) { ++ __D("GETPOOL: delta (%#llx) < olddelta (%#llx)?\n", ++ lsize - lreqsize, delta); ++ if ((lsize - lreqsize) < delta) { ++ if (bi < NBLOCKS) { ++ if (!list_empty(freelistp)) { ++ delta = lsize - lreqsize; ++ pool = i; ++ __D("GETPOOL: Found a best fit delta %#llx in pool %d\n", ++ delta, pool); ++ } ++ } ++ else { ++ delta = lsize - lreqsize; ++ pool = i; ++ __D("GETPOOL: Found a best fit delta %#llx in CMA block\n", ++ delta); ++ } ++ } ++ } ++ } ++ ++ if (pool == -1 && heap_pool[bi] != -1) { ++ if (useHeapIfPoolUnavailable) { ++ /* no pool buffer available, try heap */ ++ ++ reqsize = lreqsize; ++ physp = HeapMem_alloc(bi, reqsize, HEAP_ALIGN, DRYRUN); ++ if (physp != 0) { ++ /* ++ * Indicate heap pool with magic negative value. ++ * -1 indicates no pool and no heap. ++ * -2 indicates no pool but heap available and allowed. ++ */ ++ pool = -2; ++ ++ __D("GETPOOL: no pool-based buffer available, " ++ "returning heap \"pool\" instead (due to config " ++ "override)\n"); ++ } ++ } ++ } ++ ++ mutex_unlock(&cmem_mutex); ++ ++ if (pool == -1) { ++ __E("Failed to find a pool which fits %#llx\n", lreqsize); ++ ++ return -ENOMEM; ++ } ++ ++ if (put_user(pool, argp)) { ++ return -EFAULT; ++ } ++ __D("GETPOOL: returning %d\n", pool); ++ break; ++ ++ case CMEM_IOCCACHEWBINVALL: ++ flush_cache_all(); ++ __D("CACHEWBINVALL: flush all cache\n"); ++ ++ break; ++ ++ case CMEM_IOCCACHE: ++ __D("CACHE%s%s ioctl received.\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : ""); ++ ++ if (copy_from_user(&block, argp, sizeof(block))) { ++ return -EFAULT; ++ } ++ virtp = block.addr; ++ virtp_end = virtp + block.size; ++ ++#ifdef CHECK_FOR_ALLOCATED_BUFFER ++ physp = get_phys(virtp); ++ if (physp == ~(0LL)) { ++ __E("CACHE%s%s: Failed to convert virtual 0x%p to physical\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : "", ++ virtp); ++ return -EFAULT; ++ } ++ ++ __D("CACHE%s%s: translated 0x%p user virtual to %#lx physical\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : "", ++ virtp, physp); ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ entry = find_busy_entry(physp, &pool, &e, &bi, &block.size); ++ mutex_unlock(&cmem_mutex); ++ if (!entry) { ++ __E("CACHE%s%s: Failed to find allocated buffer at virtual 0x%p\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : "", ++ virtp); ++ return -ENXIO; ++ } ++ if (!(entry->flags & CMEM_CACHED)) { ++ __E("CACHE%s%s: virtual buffer 0x%p not cached\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : "", ++ virtp); ++ return -EINVAL; ++ } ++#endif ++ ++#ifdef USE_MMAPSEM ++ __D("CACHE%s%s: acquiring mmap_sem ...\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : ""); ++ down_write(¤t->mm->mmap_sem); ++#endif ++ ++ physp = get_phys(virtp); ++ ++ switch (cmd & ~CMEM_IOCMAGIC) { ++ case CMEM_IOCCACHEWB: ++ dmac_map_area(virtp, block.size, DMA_TO_DEVICE); ++ outer_clean_range(physp, physp + block.size); ++ ++ __D("CACHEWB: cleaned user virtual 0x%p -> 0x%p\n", ++ virtp, virtp_end); ++ ++ break; ++ ++ case CMEM_IOCCACHEINV: ++ outer_inv_range(physp, physp + block.size); ++ dmac_map_area(virtp, block.size, DMA_FROM_DEVICE); ++ ++ __D("CACHEINV: invalidated user virtual 0x%p -> 0x%p\n", ++ virtp, virtp_end); ++ ++ break; ++ ++ case CMEM_IOCCACHEWBINV: ++ dmac_map_area(virtp, block.size, DMA_BIDIRECTIONAL); ++ outer_flush_range(physp, physp + block.size); ++ ++ __D("CACHEWBINV: flushed user virtual 0x%p -> 0x%p\n", ++ virtp, virtp_end); ++ ++ break; ++ } ++ ++#ifdef USE_MMAPSEM ++ __D("CACHE%s%s: releasing mmap_sem ...\n", ++ cmd & CMEM_WB ? "WB" : "", cmd & CMEM_INV ? "INV" : ""); ++ up_write(¤t->mm->mmap_sem); ++#endif ++ ++ break; ++ ++ case CMEM_IOCGETVERSION: ++ __D("GETVERSION ioctl received, returning %#x.\n", version); ++ ++ if (put_user(version, argp)) { ++ return -EFAULT; ++ } ++ ++ break; ++ ++ case CMEM_IOCGETBLOCK: ++ __D("GETBLOCK ioctl received.\n"); ++ ++ if (copy_from_user(&allocDesc, argp, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ bi = allocDesc.blockid; ++ if (bi >= nblocks || bi < 0) { ++ __E("GETBLOCK: invalid block ID %d\n", bi); ++ ++ return -EINVAL; ++ } ++ ++ allocDesc.get_block_outparams.physp = block_start[bi]; ++ allocDesc.get_block_outparams.size = block_end[bi] - ++ block_start[bi]; ++ ++ __D("GETBLOCK: returning phys base " ++ "%#llx, size %#llx.\n", allocDesc.get_block_outparams.physp, ++ allocDesc.get_block_outparams.size); ++ ++ if (copy_to_user(argp, &allocDesc, sizeof(allocDesc))) { ++ return -EFAULT; ++ } ++ ++ break; ++ ++ case CMEM_IOCGETNUMBLOCKS: ++ __D("GETNUMBLOCKS ioctl received, returning %d.\n", nblocks); ++ ++ if (put_user(nblocks, argp)) { ++ return -EFAULT; ++ } ++ ++ break; ++ ++ case CMEM_IOCREGUSER: ++ __D("REGUSER ioctl received.\n"); ++ ++ if (copy_from_user(&physArg, llargp, sizeof(unsigned long long))) { ++ return -EFAULT; ++ } ++ physp = physArg; ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ entry = find_busy_entry(physp, &pool, &e, &bi, NULL); ++ if (entry) { ++ /* ++ * Should we check if the "current" process is already on ++ * the list and return error if so? Or should we just ++ * silently not put it on the list twice and return success? ++ * Or should we put it on the list a second time, which seems ++ * to be OK to do and will require being removed from the ++ * list twice? So many questions... ++ * ++ * The code below, lacking the test, will put a process on ++ * the list multiple times (every time IOCREGUSER is called). ++ */ ++ user = kmalloc(sizeof(struct registered_user), GFP_KERNEL); ++ user->filp = filp; ++ list_add(&user->element, &entry->users); ++ } ++ ++ mutex_unlock(&cmem_mutex); ++ ++ if (!entry) { ++ return -EFAULT; ++ } ++ ++ if (put_user(entry->size, argp)) { ++ return -EFAULT; ++ } ++ ++ break; ++ ++ default: ++ __E("Unknown ioctl received.\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ phys_addr_t physp; ++ struct pool_buffer *entry; ++ unsigned long size = vma->vm_end - vma->vm_start; ++ size_t s; ++ ++ __D("mmap: vma->vm_start = %#lx\n", vma->vm_start); ++ __D("mmap: vma->vm_end = %#lx\n", vma->vm_end); ++ __D("mmap: size = %#lx\n", size); ++ __D("mmap: vma->vm_pgoff = %#lx\n", vma->vm_pgoff); ++ ++ physp = (unsigned long long)vma->vm_pgoff << PAGE_SHIFT; ++ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ s = size; ++ entry = find_busy_entry(physp, NULL, NULL, NULL, &s); ++ mutex_unlock(&cmem_mutex); ++ ++ if (entry != NULL) { ++ if (size > entry->size) { ++ __E("mmap: requested size %#llx too big (should be <= %#llx)\n", ++ (unsigned long long)size, (unsigned long long)entry->size); ++ ++ return -EINVAL; ++ } ++ ++ if (entry->flags & CMEM_CACHED) { ++ vma->vm_page_prot = __pgprot(pgprot_val(vma->vm_page_prot) | ++ (L_PTE_MT_WRITEALLOC | L_PTE_MT_BUFFERABLE)); ++ } ++ else { ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ } ++ vma->vm_flags |= VM_RESERVED | VM_IO; ++ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, ++ vma->vm_page_prot)) { ++ __E("mmap: failed remap_pfn_range\n"); ++ ++ return -EAGAIN; ++ } ++ ++ return 0; ++ } ++ else { ++ __E("mmap: can't find allocated buffer with physp %#llx\n", ++ (unsigned long long)physp); ++ ++ return -EINVAL; ++ } ++} ++ ++static int open(struct inode *inode, struct file *filp) ++{ ++ __D("open: called.\n"); ++ ++ atomic_inc(&reference_count); ++ ++ return 0; ++} ++ ++static int release(struct inode *inode, struct file *filp) ++{ ++ struct list_head *registeredlistp; ++ struct list_head *freelistp; ++ struct list_head *busylistp; ++ struct list_head *e; ++ struct list_head *u; ++ struct list_head *next; ++ struct list_head *unext; ++ struct pool_buffer *entry; ++ struct registered_user *user; ++ int last_close = 0; ++ int num_pools; ++ int bi; ++ int i; ++ ++ __D("close: called.\n"); ++ ++ /* Force free all buffers owned by the 'current' process */ ++ ++ if (atomic_dec_and_test(&reference_count)) { ++ __D("close: all references closed, force freeing all busy buffers.\n"); ++ ++ last_close = 1; ++ } ++ ++ for (bi = 0; bi < (NBLOCKS + 1); bi++) { ++ num_pools = npools[bi]; ++ if (heap_pool[bi] != -1) { ++ num_pools++; ++ } ++ ++ /* Clean up any buffers on the busy list when cmem is closed */ ++ for (i = 0; i < num_pools; i++) { ++ __D("Forcing free on pool %d\n", i); ++ ++ /* acquire the mutex in case this isn't the last close */ ++ if (mutex_lock_interruptible(&cmem_mutex)) { ++ return -ERESTARTSYS; ++ } ++ ++ freelistp = &p_objs[bi][i].freelist; ++ busylistp = &p_objs[bi][i].busylist; ++ ++ e = busylistp->next; ++ while (e != busylistp) { ++ __D("busy entry(s) found\n"); ++ ++ next = e->next; ++ ++ entry = list_entry(e, struct pool_buffer, element); ++ registeredlistp = &entry->users; ++ u = registeredlistp->next; ++ while (u != registeredlistp) { ++ unext = u->next; ++ ++ user = list_entry(u, struct registered_user, element); ++ ++ if (last_close || user->filp == filp) { ++ __D("Removing file 0x%p from user list of buffer %#llx...\n", ++ user->filp, (unsigned long long)entry->physp); ++ ++ list_del(u); ++ kfree(user); ++ } ++ ++ u = unext; ++ } ++ ++ if (registeredlistp->next == registeredlistp) { ++ /* no more registered users, free buffer */ ++ ++ if ((heap_pool[bi] != -1) && (i == (num_pools - 1))) { ++ /* HEAP */ ++ __D("Warning: Freeing 'busy' buffer from heap at " ++ "%#llx\n", (unsigned long long)entry->physp); ++ ++ if (bi == NBLOCKS) { ++ dma_free_coherent(NULL, entry->size, ++ entry->kvirtp, entry->dma); ++ } ++ else { ++ HeapMem_free(bi, entry->physp, entry->size); ++ } ++ list_del(e); ++ kfree(entry); ++ } ++ else { ++ /* POOL */ ++ __D("Warning: Putting 'busy' buffer from pool %d at " ++ "%#llx on freelist\n", ++ i, (unsigned long long)entry->physp); ++ ++ list_del_init(e); ++ list_add(e, freelistp); ++ } ++ } ++ ++ e = next; ++ } ++ ++ mutex_unlock(&cmem_mutex); ++ } ++ } ++ ++ __D("close: returning\n"); ++ ++ return 0; ++} ++ ++static void banner(void) ++{ ++// printk(KERN_INFO "CMEMK module: built on " __DATE__ " at " __TIME__ "\n"); ++ printk(KERN_INFO " Reference Linux version %d.%d.%d\n", ++ (LINUX_VERSION_CODE & 0x00ff0000) >> 16, ++ (LINUX_VERSION_CODE & 0x0000ff00) >> 8, ++ (LINUX_VERSION_CODE & 0x000000ff) >> 0 ++ ); ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) ++ ++/* ++ * dt_config needs to set: ++ * block_start[bi] ++ * block_end[bi] ++ * npools[bi] ++ * pool_num_buffers[bi][p] ++ * pool_size[bi][p] ++ * for blocks specified in DT ++ */ ++int dt_config(void) ++{ ++ struct device_node *np, *block, *mem; ++ int ret; ++ u32 tmp[MAX_POOLS * 2]; ++ u32 addr; ++ u32 size; ++ int n, p; ++ int num_pools; ++ int num_buffers; ++ int buffer_size; ++ int block_num; ++ ++ np = of_find_compatible_node(NULL, NULL, "ti,cmem"); ++ if (!np) { ++ __D("no cmem node found in device tree\n"); ++ return -ENODEV; ++ } ++ ++ __D("found cmem node in device tree, getting child nodes\n"); ++ ++ if (of_get_available_child_count(np) == 0) { ++ __E("no child block node(s) found\n"); ++ return -EINVAL; ++ } ++ ++ block = NULL; ++ ++ while ((block = of_get_next_available_child(np, block)) != NULL) { ++ __D("got child\n"); ++ ++ if (of_property_read_u32(block, "reg", &block_num)) { ++ __E("cmem block has no reg property\n"); ++ return -EINVAL; ++ } ++ if (block_num < 0 || block_num >= NBLOCKS) { ++ __E("cmem block 'address' (reg property) %d out of range\n" ++ " must be 0 -> %d\n", block_num, NBLOCKS - 1); ++ return -EINVAL; ++ } ++ if (block_start[block_num] != 0) { ++ __E("cmem block %d already assigned\n", block_num); ++ return -EINVAL; ++ } ++ ++ __D(" looking for memory-region phandle\n"); ++ ++ mem = of_parse_phandle(block, "memory-region", 0); ++ if (mem) { ++ __D("got memory-region\n"); ++ ++ ret = of_property_read_u32_array(mem, "reg", tmp, 2); ++ if (ret) { ++ return ret; ++ } ++ addr = tmp[0]; ++ size = tmp[1]; ++ ++ block_start[block_num] = addr; ++ block_end[block_num] = addr + size; ++ ++ __D("got addr size: 0x%x 0x%x\n", addr, size); ++ ++ num_pools = 0; ++ if (of_get_property(block, "cmem-buf-pools", &n) != NULL) { ++ /* n is number of bytes, need multiple of 8 */ ++ if ((n % 8) != 0) { ++ __E("bad cmem-buf-pools: must be even number of ints\n"); ++ return -EINVAL; ++ } ++ ++ num_pools = n / 8; ++ } ++ ++ if (num_pools > MAX_POOLS) { ++ __E("bad cmem-buf-pools: too many pools\n" ++ " must be <= %d\n", MAX_POOLS); ++ return -EINVAL; ++ } ++ ++ __D("num_pools=%d\n", num_pools); ++ ++ npools[block_num] = num_pools; ++ if (num_pools) { ++ ret = of_property_read_u32_array(block, "cmem-buf-pools", ++ tmp, n / 4); ++ if (!ret) { ++ n = 0; ++ p = 0; ++ while (num_pools) { ++ num_buffers = tmp[n++]; ++ buffer_size = tmp[n++]; ++ pool_num_buffers[block_num][p] = num_buffers; ++ pool_size[block_num][p] = buffer_size; ++ ++ num_pools--; ++ p++; ++ ++ __D("got a pool: %d x 0x%x\n", ++ num_buffers, buffer_size); ++ } ++ } ++ } ++ } ++ else { ++ __E("no memory-region phandle\n"); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++#endif /* KERNEL_VERSION >= 3.14.0 */ ++ ++/* ++ * cl_config needs to set: ++ * block_start[bi] ++ * block_end[bi] ++ * npools[bi] ++ * pool_num_buffers[bi][p] ++ * pool_size[bi][p] ++ * for blocks *not* specified in DT that *are* specified on the command line ++ */ ++int cl_config(void) ++{ ++ char *pstart[NBLOCKS]; ++ char *pend[NBLOCKS]; ++ char **pool_table[MAX_POOLS]; ++ int err = 0; ++ int bi; ++ int i; ++ char *t; ++ ++ /* if allowOverlap != -1 then it was set on the command line (to 0 or 1) */ ++ if (allowOverlap != -1) { ++ pr_warn("cmem_init: allowOverlap parameter has been deprecated, ignoring...\n"); ++ } ++ ++ if (npools[0] > MAX_POOLS) { ++ __E("Too many pools specified (%d) for Block 0, only %d supported.\n", npools[0], MAX_POOLS); ++ return -EINVAL; ++ } ++ ++ if (npools[1] > MAX_POOLS) { ++ __E("Too many pools specified (%d) for Block 0, only %d supported.\n", npools[1], MAX_POOLS); ++ return -EINVAL; ++ } ++ ++ if (npools[2] > MAX_POOLS) { ++ __E("Too many pools specified (%d) for Block 0, only %d supported.\n", npools[1], MAX_POOLS); ++ return -EINVAL; ++ } ++ ++/* cut-and-paste below as part of adding support for more than 4 blocks */ ++ if (npools[3] > MAX_POOLS) { ++ __E("Too many pools specified (%d) for Block 0, only %d supported.\n", npools[1], MAX_POOLS); ++ return -EINVAL; ++ } ++/* cut-and-paste above as part of adding support for more than 4 blocks */ ++ ++ pstart[0] = phys_start; ++ pend[0] = phys_end; ++ pool_table[0] = pools; ++ ++ pstart[1] = phys_start_1; ++ pend[1] = phys_end_1; ++ pool_table[1] = pools_1; ++ ++ pstart[2] = phys_start_2; ++ pend[2] = phys_end_2; ++ pool_table[2] = pools_2; ++ ++/* cut-and-paste below as part of adding support for more than 4 blocks */ ++ pstart[3] = phys_start_3; ++ pend[3] = phys_end_3; ++ pool_table[3] = pools_3; ++/* cut-and-paste above as part of adding support for more than 4 blocks */ ++ ++ for (bi = 0; bi < NBLOCKS; bi++) { ++ if (!pstart[bi]) { ++ continue; ++ } ++ ++ if (block_start[bi]) { ++ __D("block %d specified in DT, ignoring cmd line\n", bi); ++ continue; ++ } ++ ++ /* Get the start and end of CMEM memory */ ++ block_start[bi] = PAGE_ALIGN(simple_strtoll(pstart[bi], NULL, 16)); ++ block_end[bi] = PAGE_ALIGN(simple_strtoll(pend[bi], NULL, 16)); ++ ++ /* Parse the pools */ ++ for (i = 0; i < npools[bi]; i++) { ++ t = strsep(&pool_table[bi][i], "x"); ++ if (!t) { ++ err = -EINVAL; ++ goto fail; ++ } ++ pool_num_buffers[bi][i] = simple_strtol(t, NULL, 10); ++ ++ t = strsep(&pool_table[bi][i], "\0"); ++ if (!t) { ++ err = -EINVAL; ++ goto fail; ++ } ++ pool_size[bi][i] = simple_strtoll(t, NULL, 10); ++ } ++ } ++ ++fail: ++ return err; ++} ++ ++int __init cmem_init(void) ++{ ++ int bi; ++ int i; ++ int err; ++ unsigned long long length; ++ HeapMem_Header *header; ++ char tmp_str[4]; ++ void *virtp; ++ ++ banner(); ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0) ++ if ((err = dt_config()) == -EINVAL) { ++ __E("bad DT config\n"); ++ return err; ++ } ++ else { ++ if (err == -ENODEV) { ++ __D("no DT config\n"); ++ } ++ } ++#endif /* KERNEL_VERSION >= 3.14.0 */ ++ ++ if ((err = cl_config()) != 0) { ++ __E("error %d processing command line\n", err); ++ return err; ++ } ++ ++ mutex_init(&cmem_mutex); ++ ++ cmem_major = register_chrdev(0, "cmem", &cmem_fxns); ++ ++ if (cmem_major < 0) { ++ __E("Failed to allocate major number.\n"); ++ return -ENODEV; ++ } ++ ++ __D("Allocated major number: %d\n", cmem_major); ++ ++ cmem_class = class_create(THIS_MODULE, "cmem"); ++ if (IS_ERR(cmem_class)) { ++ __E("Error creating cmem device class.\n"); ++ err = -EIO; ++ goto fail_after_reg; ++ } ++ ++ device_create(cmem_class, NULL, MKDEV(cmem_major, 0), NULL, "cmem"); ++ ++ for (bi = 0; bi < NBLOCKS; bi++) { ++ if (!block_start[bi] || !block_end[bi]) { ++ if (bi != 0) { ++ continue; ++ } ++ ++ /* we know block 0 wasn't specified, ensure no pools for it */ ++ if (pool_num_buffers[0][0]) { ++ __E("pools specified: must specify both phys_start and phys_end, exiting...\n"); ++ err = -EINVAL; ++ goto fail_after_create; ++ } ++ else { ++ printk(KERN_INFO "no physical memory specified\n"); ++ ++ break; ++ } ++ } ++ ++ length = block_end[bi] - block_start[bi]; ++ ++ if (block_start[bi] == 0) { ++ sprintf(tmp_str, "_%d", bi); ++ __E("Physical address of 0 not allowed (phys_start%s)\n", ++ bi == 0 ? "" : tmp_str); ++ __E(" (minimum physical address is %#lx)\n", PAGE_SIZE); ++ err = -EINVAL; ++ goto fail_after_create; ++ } ++ ++ if (block_end[bi] < block_start[bi]) { ++ __E("phys_end (%#llx) < phys_start (%#llx)\n", ++ block_end[bi], block_start[bi]); ++ err = -EINVAL; ++ goto fail_after_create; ++ } ++ ++ block_avail_size[bi] = length; ++ ++ __D("calling request_mem_region(%#llx, %#llx, \"CMEM\")\n", ++ block_start[bi], length); ++ ++ if (!request_mem_region(block_start[bi], length, "CMEM")) { ++ __E("Failed to request_mem_region(%#llx, %#llx)\n", ++ block_start[bi], length); ++ err = -EFAULT; ++ goto fail_after_create; ++ } ++ else { ++ block_flags[bi] |= BLOCK_MEMREGION; ++ } ++ ++ /* Allocate the pools */ ++ for (i = 0; i < npools[bi]; i++) { ++ if (alloc_pool(bi, i, pool_num_buffers[bi][i], pool_size[bi][i], ++ NULL) < 0) { ++ __E("Failed to alloc pool of size 0x%llu and number of buffers %d\n", pool_size[bi][i], pool_num_buffers[bi][i]); ++ err = -ENOMEM; ++ goto fail_after_create; ++ } ++ ++ total_num_buffers[bi] += pool_num_buffers[bi][i]; ++ } ++ ++ /* use whatever is left for the heap */ ++ heap_size[bi] = block_avail_size[bi] & PAGE_MASK; ++ if (heap_size[bi] > 0) { ++ err = alloc_pool(bi, npools[bi], 1, heap_size[bi], &heap_physp[bi]); ++ if (err < 0) { ++ __E("Failed to alloc heap of size %#lx\n", heap_size[bi]); ++ goto fail_after_create; ++ } ++ printk(KERN_INFO "allocated heap buffer %#llx of size %#lx\n", ++ (unsigned long long)heap_physp[bi], heap_size[bi]); ++ heap_pool[bi] = npools[bi]; ++ heap_head[bi].next = heap_physp[bi]; ++ heap_head[bi].size = heap_size[bi]; ++ ++ map_header((void **)&virtp, heap_physp[bi], &ioremap_area); ++ ++ header = (HeapMem_Header *)virtp; ++ header->next = 0; ++ header->size = heap_size[bi]; ++ ++ unmap_header(virtp, ioremap_area); ++ ++ if (useHeapIfPoolUnavailable) { ++ printk(KERN_INFO "heap fallback enabled - will try heap if " ++ "pool buffer is not available\n"); ++ } ++ } ++ else { ++ __D("no remaining memory for heap, no heap created " ++ "for memory block %d\n", bi); ++ heap_head[bi].next = 0; ++ } ++ ++ __D("cmem initialized %d pools between %#llx and %#llx\n", ++ npools[bi], block_start[bi], block_end[bi]); ++ ++ nblocks++; ++ } ++ ++ ++ if (cmem_cma_npools == 0) { ++ /* no explicit pools, assuming global CMA area */ ++ __D("no CMEM CMA pools found\n"); ++ ++ INIT_LIST_HEAD(&p_objs[NBLOCKS][0].busylist); ++ p_objs[NBLOCKS][0].reqsize = 0; ++ p_objs[NBLOCKS][0].size = 0; ++ p_objs[NBLOCKS][0].numbufs = 1; ++ ++ heap_pool[NBLOCKS] = 0; ++ npools[NBLOCKS] = 0; ++ } ++ else { ++ __D("%d CMEM CMA pools\n", cmem_cma_npools); ++ ++ for (i = 0; i < cmem_cma_npools; i++) { ++ INIT_LIST_HEAD(&p_objs[NBLOCKS][i].busylist); ++ p_objs[NBLOCKS][i].reqsize = cmem_cma_p_objs[i].reqsize; ++ p_objs[NBLOCKS][i].size = cmem_cma_p_objs[i].size; ++ p_objs[NBLOCKS][i].numbufs = cmem_cma_p_objs[i].numbufs; ++ ++ cmem_cma_dev[i].coherent_dma_mask = DMA_BIT_MASK(32); ++ ++ __D(" pool %d: size=%#llx numbufs=%d\n", i, ++ p_objs[NBLOCKS][i].size, p_objs[NBLOCKS][i].numbufs); ++ } ++ ++ if (cmem_cma_heapsize) { ++ /* already init'ed p_objs in loop above */ ++ heap_pool[NBLOCKS] = cmem_cma_npools - 1; ++ npools[NBLOCKS] = cmem_cma_npools - 1; ++ } ++ else { ++ INIT_LIST_HEAD(&p_objs[NBLOCKS][cmem_cma_npools].busylist); ++ p_objs[NBLOCKS][cmem_cma_npools].reqsize = 0; ++ p_objs[NBLOCKS][cmem_cma_npools].size = 0; ++ p_objs[NBLOCKS][cmem_cma_npools].numbufs = 1; ++ ++ heap_pool[NBLOCKS] = cmem_cma_npools; ++ npools[NBLOCKS] = cmem_cma_npools; ++ } ++ } ++ ++ /* Create the /proc entry */ ++ cmem_proc_entry = proc_create("cmem", 0, NULL, &cmem_proc_ops); ++ ++ printk(KERN_INFO "cmemk initialized\n"); ++ ++ return 0; ++ ++fail_after_create: ++ ++ length = block_end[bi] - block_start[bi]; ++ ++ for (bi = 0; bi < NBLOCKS; bi++) { ++ if (block_flags[bi] & BLOCK_MEMREGION) { ++ __D("calling release_mem_region(%#llx, %#llx)...\n", ++ block_start[bi], length); ++ ++ release_mem_region(block_start[bi], length); ++ ++ block_flags[bi] &= ~BLOCK_MEMREGION; ++ } ++ } ++ ++ device_destroy(cmem_class, MKDEV(cmem_major, 0)); ++ class_destroy(cmem_class); ++ ++fail_after_reg: ++ __D("Unregistering character device cmem\n"); ++ unregister_chrdev(cmem_major, "cmem"); ++ ++ return err; ++} ++ ++void __exit cmem_exit(void) ++{ ++ struct list_head *registeredlistp; ++ struct list_head *freelistp; ++ struct list_head *busylistp; ++ struct list_head *e; ++ struct list_head *u; ++ struct list_head *unext; ++ struct pool_buffer *entry; ++ struct registered_user *user; ++ unsigned long long length; ++ int num_pools; ++ int bi; ++ int i; ++ ++ __D("In cmem_exit()\n"); ++ ++ /* Remove the /proc entry */ ++ remove_proc_entry("cmem", NULL); ++ ++ for (bi = 0; bi < NBLOCKS; bi++) { ++ num_pools = npools[bi]; ++ ++ if (heap_pool[bi] != -1) { ++ num_pools++; ++ } ++ ++ /* Free the pool structures and empty the lists. */ ++ for (i = 0; i < num_pools; i++) { ++ __D("Freeing memory associated with pool %d\n", i); ++ ++ freelistp = &p_objs[bi][i].freelist; ++ busylistp = &p_objs[bi][i].busylist; ++ ++ e = busylistp->next; ++ while (e != busylistp) { ++ entry = list_entry(e, struct pool_buffer, element); ++ ++ __D("Warning: Freeing busy entry %d at %#llx\n", ++ entry->id, (unsigned long long)entry->physp); ++ ++ registeredlistp = &entry->users; ++ u = registeredlistp->next; ++ while (u != registeredlistp) { ++ unext = u->next; ++ ++ user = list_entry(u, struct registered_user, element); ++ ++ __D("Removing file 0x%p from user list of buffer %#llx...\n", ++ user->filp, (unsigned long long)entry->physp); ++ ++ list_del(u); ++ kfree(user); ++ ++ u = unext; ++ } ++ ++ e = e->next; ++ kfree(entry); ++ } ++ ++ e = freelistp->next; ++ while (e != freelistp) { ++ entry = list_entry(e, struct pool_buffer, element); ++ ++ __D("Freeing free entry %d at %#llx\n", ++ entry->id, (unsigned long long)entry->physp); ++ ++ registeredlistp = &entry->users; ++ u = registeredlistp->next; ++ while (u != registeredlistp) { ++ /* should never happen, but check to avoid mem leak */ ++ unext = u->next; ++ ++ user = list_entry(u, struct registered_user, element); ++ ++ __D("Removing file 0x%p from user list of buffer %#llx...\n", ++ user->filp, (unsigned long long)entry->physp); ++ ++ list_del(u); ++ kfree(user); ++ ++ u = unext; ++ } ++ ++ e = e->next; ++ kfree(entry); ++ } ++ } ++ ++ length = block_end[bi] - block_start[bi]; ++ ++ if (block_flags[bi] & BLOCK_MEMREGION) { ++ __D("calling release_mem_region(%#llx, %#llx)...\n", ++ block_start[bi], length); ++ ++ release_mem_region(block_start[bi], length); ++ ++ block_flags[bi] &= ~BLOCK_MEMREGION; ++ } ++ } ++ ++ device_destroy(cmem_class, MKDEV(cmem_major, 0)); ++ class_destroy(cmem_class); ++ ++ __D("Unregistering character device cmem\n"); ++ unregister_chrdev(cmem_major, "cmem"); ++ ++ printk(KERN_INFO "cmemk unregistered\n"); ++} ++ ++MODULE_LICENSE("GPL"); ++module_init(cmem_init); ++module_exit(cmem_exit); ++ ++ ++#if !defined(MULTI_CACHE) ++ ++//#warning "MULTI_CACHE is *not* #defined, using work-around for asm cache functions" ++ ++#ifdef CONFIG_CPU_ARM926T ++ ++/* ++ * The following assembly functions were taken from ++ * arch/arm/mm/proc-arm926.S ++ * Since we can't use the C preprocessor to evaluate #defines, the ++ * code that was taken is the code encapsulated by ++ * #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH ++ * ... ++ * #endif ++ * (note that this is #ifndef, i.e., #if !defined) ++ */ ++ ++/* ++ * the cache line size of the I and D cache ++ */ ++/* ++ * Leave here for documentation purposes, but we don't use it since ++ * asm("") statements won't get preprocessed (inside a string). ++ */ ++#define CACHE_DLINESIZE 32 ++ ++asm("\n \ ++ .global arm926_dma_map_area\n \ ++arm926_dma_map_area:\n \ ++ add r1, r1, r0\n \ ++@ cmp r2, #DMA_TO_DEVICE\n \ ++ cmp r2, #1\n \ ++ beq arm926_dma_clean_range\n \ ++ bcs arm926_dma_inv_range\n \ ++ b arm926_dma_flush_range\n \ ++"); ++ ++/* ++ * dma_inv_range(start, end) ++ * ++ * Invalidate (discard) the specified virtual address range. ++ * May not write back any entries. If 'start' or 'end' ++ * are not cache line aligned, those lines must be written ++ * back. ++ * ++ * - start - virtual start address ++ * - end - virtual end address ++ * ++ * (same as v4wb) ++ENTRY(arm926_dma_inv_range) ++ */ ++asm("\n \ ++ .global arm926_dma_inv_range\n \ ++arm926_dma_inv_range:\n \ ++@ tst r0, #CACHE_DLINESIZE - 1\n \ ++ tst r0, #32 - 1\n \ ++ mcrne p15, 0, r0, c7, c10, 1 @ clean D entry\n \ ++@ tst r1, #CACHE_DLINESIZE - 1\n \ ++ tst r1, #32 - 1\n \ ++ mcrne p15, 0, r1, c7, c10, 1 @ clean D entry\n \ ++@ bic r0, r0, #CACHE_DLINESIZE - 1\n \ ++ bic r0, r0, #32 - 1\n \ ++1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry\n \ ++@ add r0, r0, #CACHE_DLINESIZE\n \ ++ add r0, r0, #32\n \ ++ cmp r0, r1\n \ ++ blo 1b\n \ ++ mcr p15, 0, r0, c7, c10, 4 @ drain WB\n \ ++ mov pc, lr\n \ ++"); ++ ++/* ++ * dma_clean_range(start, end) ++ * ++ * Clean the specified virtual address range. ++ * ++ * - start - virtual start address ++ * - end - virtual end address ++ * ++ * (same as v4wb) ++ENTRY(arm926_dma_clean_range) ++ */ ++asm("\n \ ++ .global arm926_dma_clean_range\n \ ++arm926_dma_clean_range:\n \ ++@ bic r0, r0, #CACHE_DLINESIZE - 1\n \ ++ bic r0, r0, #32 - 1\n \ ++1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry\n \ ++@ add r0, r0, #CACHE_DLINESIZE\n \ ++ add r0, r0, #32\n \ ++ cmp r0, r1\n \ ++ blo 1b\n \ ++ mcr p15, 0, r0, c7, c10, 4 @ drain WB\n \ ++ mov pc, lr\n \ ++"); ++ ++/* ++ * dma_flush_range(start, end) ++ * ++ * Clean and invalidate the specified virtual address range. ++ * ++ * - start - virtual start address ++ * - end - virtual end address ++ENTRY(arm926_dma_flush_range) ++ */ ++asm("\n \ ++ .global arm926_dma_flush_range\n \ ++arm926_dma_flush_range:\n \ ++@ bic r0, r0, #CACHE_DLINESIZE - 1\n \ ++ bic r0, r0, #32 - 1\n \ ++1:\n \ ++ mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry\n \ ++@ add r0, r0, #CACHE_DLINESIZE\n \ ++ add r0, r0, #32\n \ ++ cmp r0, r1\n \ ++ blo 1b\n \ ++ mcr p15, 0, r0, c7, c10, 4 @ drain WB\n \ ++ mov pc, lr\n \ ++"); ++ ++#else /* CONFIG_CPU_ARM926T */ ++#if 1 ++ ++/* ++ * v7_dma_inv_range(start,end) ++ * ++ * Invalidate the data cache within the specified region; we will ++ * be performing a DMA operation in this region and we want to ++ * purge old data in the cache. ++ * ++ * - start - virtual start address of region ++ * - end - virtual end address of region ++ */ ++asm("\n \ ++ .global v7_dma_inv_range\n \ ++v7_dma_inv_range:\n \ ++@ dcache_line_size r2, r3\n \ ++ mrc p15, 0, r3, c0, c0, 1 @ read ctr\n \ ++ lsr r3, r3, #16\n \ ++ and r3, r3, #0xf @ cache line size encoding\n \ ++ mov r2, #4 @ bytes per word\n \ ++ mov r2, r2, lsl r3 @ actual cache line size\n \ ++\n \ ++ sub r3, r2, #1\n \ ++ tst r0, r3\n \ ++ bic r0, r0, r3\n \ ++@ #ifdef CONFIG_ARM_ERRATA_764369\n \ ++@ ALT_SMP(W(dsb))\n \ ++@ ALT_UP(W(nop))\n \ ++@ #endif\n \ ++ mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line\n \ ++ tst r1, r3\n \ ++ bic r1, r1, r3\n \ ++ mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line\n \ ++1:\n \ ++ mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line\n \ ++ add r0, r0, r2\n \ ++ cmp r0, r1\n \ ++ blo 1b\n \ ++ dsb\n \ ++ mov pc, lr\n \ ++"); ++ ++/* ++ * v7_dma_clean_range(start,end) ++ * - start - virtual start address of region ++ * - end - virtual end address of region ++ */ ++asm("\n \ ++ .global v7_dma_clean_range\n \ ++v7_dma_clean_range:\n \ ++@ dcache_line_size r2, r3\n \ ++ mrc p15, 0, r3, c0, c0, 1 @ read ctr\n \ ++ lsr r3, r3, #16\n \ ++ and r3, r3, #0xf @ cache line size encoding\n \ ++ mov r2, #4 @ bytes per word\n \ ++ mov r2, r2, lsl r3 @ actual cache line size\n \ ++\n \ ++ sub r3, r2, #1\n \ ++ bic r0, r0, r3\n \ ++@ #ifdef CONFIG_ARM_ERRATA_764369\n \ ++@ ALT_SMP(W(dsb))\n \ ++@ ALT_UP(W(nop))\n \ ++@ #endif\n \ ++1:\n \ ++ mcr p15, 0, r0, c7, c10, 1 @ clean D / U line\n \ ++ add r0, r0, r2\n \ ++ cmp r0, r1\n \ ++ blo 1b\n \ ++ dsb\n \ ++ mov pc, lr\n \ ++"); ++ ++/* ++ * v7_dma_flush_range(start,end) ++ * - start - virtual start address of region ++ * - end - virtual end address of region ++ */ ++asm("\n \ ++ .global v7_dma_flush_range\n \ ++v7_dma_flush_range:\n \ ++@ dcache_line_size r2, r3\n \ ++ mrc p15, 0, r3, c0, c0, 1 @ read ctr\n \ ++ lsr r3, r3, #16\n \ ++ and r3, r3, #0xf @ cache line size encoding\n \ ++ mov r2, #4 @ bytes per word\n \ ++ mov r2, r2, lsl r3 @ actual cache line size\n \ ++\n \ ++ sub r3, r2, #1\n \ ++ bic r0, r0, r3\n \ ++@ #ifdef CONFIG_ARM_ERRATA_764369\n \ ++@ ALT_SMP(W(dsb))\n \ ++@ ALT_UP(W(nop))\n \ ++@ #endif\n \ ++1:\n \ ++ mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line\n \ ++ add r0, r0, r2\n \ ++ cmp r0, r1\n \ ++ blo 1b\n \ ++ dsb\n \ ++ mov pc, lr\n \ ++"); ++ ++/* ++ * dma_map_area(start, size, dir) ++ * - start - kernel virtual start address ++ * - size - size of region ++ * - dir - DMA direction ++ */ ++asm("\n \ ++ .global v7_dma_map_area\n \ ++v7_dma_map_area:\n \ ++ add r1, r1, r0\n \ ++@ cmp r2, #DMA_TO_DEVICE\n \ ++ cmp r2, #1\n \ ++ beq v7_dma_clean_range\n \ ++ bcs v7_dma_inv_range\n \ ++ b v7_dma_flush_range\n \ ++"); ++ ++/* ++ * dma_unmap_area(start, size, dir) ++ * - start - kernel virtual start address ++ * - size - size of region ++ * - dir - DMA direction ++ */ ++asm("\n \ ++ .global v7_dma_unmap_area\n \ ++v7_dma_unmap_area:\n \ ++ add r1, r1, r0\n \ ++@ teq r2, #DMA_TO_DEVICE\n \ ++ teq r2, #1\n \ ++ bne v7_dma_inv_range\n \ ++ mov pc, lr\n \ ++"); ++ ++#endif ++#endif /* CONFIG_CPU_ARM926T */ ++ ++#endif /* !defined(MULTI_CACHE) */ +diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig +index 2fb0fdfc..ee93e48f 100644 +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -435,5 +435,4 @@ config CRYPTO_DEV_QCE + This driver supports Qualcomm crypto engine accelerator + hardware. To compile this driver as a module, choose M here. The + module will be called qcrypto. +- + endif # CRYPTO_HW +diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig +index e3b4b0f0..f827c4db 100644 +--- a/drivers/gpu/drm/Kconfig ++++ b/drivers/gpu/drm/Kconfig +@@ -120,7 +120,7 @@ config DRM_RADEON + + source "drivers/gpu/drm/radeon/Kconfig" + +-source "drivers/gpu/drm/nouveau/Kconfig" ++#source "drivers/gpu/drm/nouveau/Kconfig" + + config DRM_I810 + tristate "Intel I810" +diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile +index 9292a761..aafdefb8 100644 +--- a/drivers/gpu/drm/Makefile ++++ b/drivers/gpu/drm/Makefile +@@ -47,7 +47,7 @@ obj-$(CONFIG_DRM_SIS) += sis/ + obj-$(CONFIG_DRM_SAVAGE)+= savage/ + obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/ + obj-$(CONFIG_DRM_VIA) +=via/ +-obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/ ++#obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/ + obj-$(CONFIG_DRM_EXYNOS) +=exynos/ + obj-$(CONFIG_DRM_GMA500) += gma500/ + obj-$(CONFIG_DRM_UDL) += udl/ +diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig +deleted file mode 100644 +index 40afc69a..00000000 +--- a/drivers/gpu/drm/nouveau/Kconfig ++++ /dev/null +@@ -1,70 +0,0 @@ +-config DRM_NOUVEAU +- tristate "Nouveau (NVIDIA) cards" +- depends on DRM && PCI +- select FW_LOADER +- select DRM_KMS_HELPER +- select DRM_KMS_FB_HELPER +- select DRM_TTM +- select FB_CFB_FILLRECT +- select FB_CFB_COPYAREA +- select FB_CFB_IMAGEBLIT +- select FB +- select FRAMEBUFFER_CONSOLE if !EXPERT +- select FB_BACKLIGHT if DRM_NOUVEAU_BACKLIGHT +- select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && INPUT +- select X86_PLATFORM_DEVICES if ACPI && X86 +- select ACPI_WMI if ACPI && X86 +- select MXM_WMI if ACPI && X86 +- select POWER_SUPPLY +- # Similar to i915, we need to select ACPI_VIDEO and it's dependencies +- select BACKLIGHT_LCD_SUPPORT if ACPI && X86 +- select BACKLIGHT_CLASS_DEVICE if ACPI && X86 +- select INPUT if ACPI && X86 +- select THERMAL if ACPI && X86 +- select ACPI_VIDEO if ACPI && X86 +- help +- Choose this option for open-source NVIDIA support. +- +-config NOUVEAU_PLATFORM_DRIVER +- tristate "Nouveau (NVIDIA) SoC GPUs" +- depends on DRM_NOUVEAU && ARCH_TEGRA +- default y +- help +- Support for Nouveau platform driver, used for SoC GPUs as found +- on NVIDIA Tegra K1. +- +-config NOUVEAU_DEBUG +- int "Maximum debug level" +- depends on DRM_NOUVEAU +- range 0 7 +- default 5 +- help +- Selects the maximum debug level to compile support for. +- +- 0 - fatal +- 1 - error +- 2 - warning +- 3 - info +- 4 - debug +- 5 - trace (recommended) +- 6 - paranoia +- 7 - spam +- +- The paranoia and spam levels will add a lot of extra checks which +- may potentially slow down driver operation. +- +-config NOUVEAU_DEBUG_DEFAULT +- int "Default debug level" +- depends on DRM_NOUVEAU +- range 0 7 +- default 3 +- help +- Selects the default debug level +- +-config DRM_NOUVEAU_BACKLIGHT +- bool "Support for backlight control" +- depends on DRM_NOUVEAU +- default y +- help +- Say Y here if you want to control the backlight of your display +- (e.g. a laptop panel). +diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile +deleted file mode 100644 +index 12c24c8a..00000000 +--- a/drivers/gpu/drm/nouveau/Makefile ++++ /dev/null +@@ -1,382 +0,0 @@ +-# +-# Makefile for the drm device driver. This driver provides support for the +-# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. +- +-ccflags-y := -Iinclude/drm +-ccflags-y += -I$(src)/core/include +-ccflags-y += -I$(src)/core +-ccflags-y += -I$(src) +- +-nouveau-y := core/core/client.o +-nouveau-y += core/core/engctx.o +-nouveau-y += core/core/engine.o +-nouveau-y += core/core/enum.o +-nouveau-y += core/core/event.o +-nouveau-y += core/core/gpuobj.o +-nouveau-y += core/core/handle.o +-nouveau-y += core/core/ioctl.o +-nouveau-y += core/core/mm.o +-nouveau-y += core/core/namedb.o +-nouveau-y += core/core/notify.o +-nouveau-y += core/core/object.o +-nouveau-y += core/core/option.o +-nouveau-y += core/core/parent.o +-nouveau-y += core/core/printk.o +-nouveau-y += core/core/ramht.o +-nouveau-y += core/core/subdev.o +- +-nouveau-y += core/subdev/bar/base.o +-nouveau-y += core/subdev/bar/nv50.o +-nouveau-y += core/subdev/bar/nvc0.o +-nouveau-y += core/subdev/bar/gk20a.o +-nouveau-y += core/subdev/bios/base.o +-nouveau-y += core/subdev/bios/bit.o +-nouveau-y += core/subdev/bios/boost.o +-nouveau-y += core/subdev/bios/conn.o +-nouveau-y += core/subdev/bios/cstep.o +-nouveau-y += core/subdev/bios/dcb.o +-nouveau-y += core/subdev/bios/disp.o +-nouveau-y += core/subdev/bios/dp.o +-nouveau-y += core/subdev/bios/extdev.o +-nouveau-y += core/subdev/bios/fan.o +-nouveau-y += core/subdev/bios/gpio.o +-nouveau-y += core/subdev/bios/i2c.o +-nouveau-y += core/subdev/bios/init.o +-nouveau-y += core/subdev/bios/mxm.o +-nouveau-y += core/subdev/bios/perf.o +-nouveau-y += core/subdev/bios/pll.o +-nouveau-y += core/subdev/bios/ramcfg.o +-nouveau-y += core/subdev/bios/rammap.o +-nouveau-y += core/subdev/bios/timing.o +-nouveau-y += core/subdev/bios/therm.o +-nouveau-y += core/subdev/bios/vmap.o +-nouveau-y += core/subdev/bios/volt.o +-nouveau-y += core/subdev/bios/xpio.o +-nouveau-y += core/subdev/bios/M0205.o +-nouveau-y += core/subdev/bios/M0209.o +-nouveau-y += core/subdev/bios/P0260.o +-nouveau-y += core/subdev/bus/hwsq.o +-nouveau-y += core/subdev/bus/nv04.o +-nouveau-y += core/subdev/bus/nv31.o +-nouveau-y += core/subdev/bus/nv50.o +-nouveau-y += core/subdev/bus/nv94.o +-nouveau-y += core/subdev/bus/nvc0.o +-nouveau-y += core/subdev/clock/base.o +-nouveau-y += core/subdev/clock/nv04.o +-nouveau-y += core/subdev/clock/nv40.o +-nouveau-y += core/subdev/clock/nv50.o +-nouveau-y += core/subdev/clock/nv84.o +-nouveau-y += core/subdev/clock/nva3.o +-nouveau-y += core/subdev/clock/nvaa.o +-nouveau-y += core/subdev/clock/nvc0.o +-nouveau-y += core/subdev/clock/nve0.o +-nouveau-y += core/subdev/clock/gk20a.o +-nouveau-y += core/subdev/clock/pllnv04.o +-nouveau-y += core/subdev/clock/pllnva3.o +-nouveau-y += core/subdev/devinit/base.o +-nouveau-y += core/subdev/devinit/nv04.o +-nouveau-y += core/subdev/devinit/nv05.o +-nouveau-y += core/subdev/devinit/nv10.o +-nouveau-y += core/subdev/devinit/nv1a.o +-nouveau-y += core/subdev/devinit/nv20.o +-nouveau-y += core/subdev/devinit/nv50.o +-nouveau-y += core/subdev/devinit/nv84.o +-nouveau-y += core/subdev/devinit/nv98.o +-nouveau-y += core/subdev/devinit/nva3.o +-nouveau-y += core/subdev/devinit/nvaf.o +-nouveau-y += core/subdev/devinit/nvc0.o +-nouveau-y += core/subdev/devinit/gm107.o +-nouveau-y += core/subdev/fb/base.o +-nouveau-y += core/subdev/fb/nv04.o +-nouveau-y += core/subdev/fb/nv10.o +-nouveau-y += core/subdev/fb/nv1a.o +-nouveau-y += core/subdev/fb/nv20.o +-nouveau-y += core/subdev/fb/nv25.o +-nouveau-y += core/subdev/fb/nv30.o +-nouveau-y += core/subdev/fb/nv35.o +-nouveau-y += core/subdev/fb/nv36.o +-nouveau-y += core/subdev/fb/nv40.o +-nouveau-y += core/subdev/fb/nv41.o +-nouveau-y += core/subdev/fb/nv44.o +-nouveau-y += core/subdev/fb/nv46.o +-nouveau-y += core/subdev/fb/nv47.o +-nouveau-y += core/subdev/fb/nv49.o +-nouveau-y += core/subdev/fb/nv4e.o +-nouveau-y += core/subdev/fb/nv50.o +-nouveau-y += core/subdev/fb/nv84.o +-nouveau-y += core/subdev/fb/nva3.o +-nouveau-y += core/subdev/fb/nvaa.o +-nouveau-y += core/subdev/fb/nvaf.o +-nouveau-y += core/subdev/fb/nvc0.o +-nouveau-y += core/subdev/fb/nve0.o +-nouveau-y += core/subdev/fb/gk20a.o +-nouveau-y += core/subdev/fb/gm107.o +-nouveau-y += core/subdev/fb/ramnv04.o +-nouveau-y += core/subdev/fb/ramnv10.o +-nouveau-y += core/subdev/fb/ramnv1a.o +-nouveau-y += core/subdev/fb/ramnv20.o +-nouveau-y += core/subdev/fb/ramnv40.o +-nouveau-y += core/subdev/fb/ramnv41.o +-nouveau-y += core/subdev/fb/ramnv44.o +-nouveau-y += core/subdev/fb/ramnv49.o +-nouveau-y += core/subdev/fb/ramnv4e.o +-nouveau-y += core/subdev/fb/ramnv50.o +-nouveau-y += core/subdev/fb/ramnva3.o +-nouveau-y += core/subdev/fb/ramnvaa.o +-nouveau-y += core/subdev/fb/ramnvc0.o +-nouveau-y += core/subdev/fb/ramnve0.o +-nouveau-y += core/subdev/fb/ramgk20a.o +-nouveau-y += core/subdev/fb/ramgm107.o +-nouveau-y += core/subdev/fb/sddr2.o +-nouveau-y += core/subdev/fb/sddr3.o +-nouveau-y += core/subdev/fb/gddr5.o +-nouveau-y += core/subdev/fuse/base.o +-nouveau-y += core/subdev/fuse/g80.o +-nouveau-y += core/subdev/fuse/gf100.o +-nouveau-y += core/subdev/fuse/gm107.o +-nouveau-y += core/subdev/gpio/base.o +-nouveau-y += core/subdev/gpio/nv10.o +-nouveau-y += core/subdev/gpio/nv50.o +-nouveau-y += core/subdev/gpio/nv94.o +-nouveau-y += core/subdev/gpio/nvd0.o +-nouveau-y += core/subdev/gpio/nve0.o +-nouveau-y += core/subdev/i2c/base.o +-nouveau-y += core/subdev/i2c/anx9805.o +-nouveau-y += core/subdev/i2c/aux.o +-nouveau-y += core/subdev/i2c/bit.o +-nouveau-y += core/subdev/i2c/pad.o +-nouveau-y += core/subdev/i2c/padnv04.o +-nouveau-y += core/subdev/i2c/padnv94.o +-nouveau-y += core/subdev/i2c/nv04.o +-nouveau-y += core/subdev/i2c/nv4e.o +-nouveau-y += core/subdev/i2c/nv50.o +-nouveau-y += core/subdev/i2c/nv94.o +-nouveau-y += core/subdev/i2c/nvd0.o +-nouveau-y += core/subdev/i2c/gf117.o +-nouveau-y += core/subdev/i2c/nve0.o +-nouveau-y += core/subdev/ibus/nvc0.o +-nouveau-y += core/subdev/ibus/nve0.o +-nouveau-y += core/subdev/ibus/gk20a.o +-nouveau-y += core/subdev/instmem/base.o +-nouveau-y += core/subdev/instmem/nv04.o +-nouveau-y += core/subdev/instmem/nv40.o +-nouveau-y += core/subdev/instmem/nv50.o +-nouveau-y += core/subdev/ltc/base.o +-nouveau-y += core/subdev/ltc/gf100.o +-nouveau-y += core/subdev/ltc/gk104.o +-nouveau-y += core/subdev/ltc/gm107.o +-nouveau-y += core/subdev/mc/base.o +-nouveau-y += core/subdev/mc/nv04.o +-nouveau-y += core/subdev/mc/nv40.o +-nouveau-y += core/subdev/mc/nv44.o +-nouveau-y += core/subdev/mc/nv4c.o +-nouveau-y += core/subdev/mc/nv50.o +-nouveau-y += core/subdev/mc/nv94.o +-nouveau-y += core/subdev/mc/nv98.o +-nouveau-y += core/subdev/mc/nvc0.o +-nouveau-y += core/subdev/mc/nvc3.o +-nouveau-y += core/subdev/mc/gk20a.o +-nouveau-y += core/subdev/mxm/base.o +-nouveau-y += core/subdev/mxm/mxms.o +-nouveau-y += core/subdev/mxm/nv50.o +-nouveau-y += core/subdev/pwr/base.o +-nouveau-y += core/subdev/pwr/memx.o +-nouveau-y += core/subdev/pwr/nva3.o +-nouveau-y += core/subdev/pwr/nvc0.o +-nouveau-y += core/subdev/pwr/nvd0.o +-nouveau-y += core/subdev/pwr/gk104.o +-nouveau-y += core/subdev/pwr/nv108.o +-nouveau-y += core/subdev/therm/base.o +-nouveau-y += core/subdev/therm/fan.o +-nouveau-y += core/subdev/therm/fannil.o +-nouveau-y += core/subdev/therm/fanpwm.o +-nouveau-y += core/subdev/therm/fantog.o +-nouveau-y += core/subdev/therm/ic.o +-nouveau-y += core/subdev/therm/temp.o +-nouveau-y += core/subdev/therm/nv40.o +-nouveau-y += core/subdev/therm/nv50.o +-nouveau-y += core/subdev/therm/nv84.o +-nouveau-y += core/subdev/therm/nva3.o +-nouveau-y += core/subdev/therm/nvd0.o +-nouveau-y += core/subdev/therm/gm107.o +-nouveau-y += core/subdev/timer/base.o +-nouveau-y += core/subdev/timer/nv04.o +-nouveau-y += core/subdev/timer/gk20a.o +-nouveau-y += core/subdev/vm/base.o +-nouveau-y += core/subdev/vm/nv04.o +-nouveau-y += core/subdev/vm/nv41.o +-nouveau-y += core/subdev/vm/nv44.o +-nouveau-y += core/subdev/vm/nv50.o +-nouveau-y += core/subdev/vm/nvc0.o +-nouveau-y += core/subdev/volt/base.o +-nouveau-y += core/subdev/volt/gpio.o +-nouveau-y += core/subdev/volt/nv40.o +- +-nouveau-y += core/engine/falcon.o +-nouveau-y += core/engine/xtensa.o +-nouveau-y += core/engine/dmaobj/base.o +-nouveau-y += core/engine/dmaobj/nv04.o +-nouveau-y += core/engine/dmaobj/nv50.o +-nouveau-y += core/engine/dmaobj/nvc0.o +-nouveau-y += core/engine/dmaobj/nvd0.o +-nouveau-y += core/engine/bsp/nv84.o +-nouveau-y += core/engine/bsp/nv98.o +-nouveau-y += core/engine/bsp/nvc0.o +-nouveau-y += core/engine/bsp/nve0.o +-nouveau-y += core/engine/copy/nva3.o +-nouveau-y += core/engine/copy/nvc0.o +-nouveau-y += core/engine/copy/nve0.o +-nouveau-y += core/engine/crypt/nv84.o +-nouveau-y += core/engine/crypt/nv98.o +-nouveau-y += core/engine/device/acpi.o +-nouveau-y += core/engine/device/base.o +-nouveau-y += core/engine/device/ctrl.o +-nouveau-y += core/engine/device/nv04.o +-nouveau-y += core/engine/device/nv10.o +-nouveau-y += core/engine/device/nv20.o +-nouveau-y += core/engine/device/nv30.o +-nouveau-y += core/engine/device/nv40.o +-nouveau-y += core/engine/device/nv50.o +-nouveau-y += core/engine/device/nvc0.o +-nouveau-y += core/engine/device/nve0.o +-nouveau-y += core/engine/device/gm100.o +-nouveau-y += core/engine/disp/base.o +-nouveau-y += core/engine/disp/conn.o +-nouveau-y += core/engine/disp/outp.o +-nouveau-y += core/engine/disp/outpdp.o +-nouveau-y += core/engine/disp/nv04.o +-nouveau-y += core/engine/disp/nv50.o +-nouveau-y += core/engine/disp/nv84.o +-nouveau-y += core/engine/disp/nv94.o +-nouveau-y += core/engine/disp/nva0.o +-nouveau-y += core/engine/disp/nva3.o +-nouveau-y += core/engine/disp/nvd0.o +-nouveau-y += core/engine/disp/nve0.o +-nouveau-y += core/engine/disp/nvf0.o +-nouveau-y += core/engine/disp/gm107.o +-nouveau-y += core/engine/disp/dacnv50.o +-nouveau-y += core/engine/disp/dport.o +-nouveau-y += core/engine/disp/hdanva3.o +-nouveau-y += core/engine/disp/hdanvd0.o +-nouveau-y += core/engine/disp/hdminv84.o +-nouveau-y += core/engine/disp/hdminva3.o +-nouveau-y += core/engine/disp/hdminvd0.o +-nouveau-y += core/engine/disp/hdminve0.o +-nouveau-y += core/engine/disp/piornv50.o +-nouveau-y += core/engine/disp/sornv50.o +-nouveau-y += core/engine/disp/sornv94.o +-nouveau-y += core/engine/disp/sornvd0.o +-nouveau-y += core/engine/disp/vga.o +-nouveau-y += core/engine/fifo/base.o +-nouveau-y += core/engine/fifo/nv04.o +-nouveau-y += core/engine/fifo/nv10.o +-nouveau-y += core/engine/fifo/nv17.o +-nouveau-y += core/engine/fifo/nv40.o +-nouveau-y += core/engine/fifo/nv50.o +-nouveau-y += core/engine/fifo/nv84.o +-nouveau-y += core/engine/fifo/nvc0.o +-nouveau-y += core/engine/fifo/nve0.o +-nouveau-y += core/engine/fifo/gk20a.o +-nouveau-y += core/engine/fifo/nv108.o +-nouveau-y += core/engine/graph/ctxnv40.o +-nouveau-y += core/engine/graph/ctxnv50.o +-nouveau-y += core/engine/graph/ctxnvc0.o +-nouveau-y += core/engine/graph/ctxnvc1.o +-nouveau-y += core/engine/graph/ctxnvc4.o +-nouveau-y += core/engine/graph/ctxnvc8.o +-nouveau-y += core/engine/graph/ctxnvd7.o +-nouveau-y += core/engine/graph/ctxnvd9.o +-nouveau-y += core/engine/graph/ctxnve4.o +-nouveau-y += core/engine/graph/ctxgk20a.o +-nouveau-y += core/engine/graph/ctxnvf0.o +-nouveau-y += core/engine/graph/ctxgk110b.o +-nouveau-y += core/engine/graph/ctxnv108.o +-nouveau-y += core/engine/graph/ctxgm107.o +-nouveau-y += core/engine/graph/nv04.o +-nouveau-y += core/engine/graph/nv10.o +-nouveau-y += core/engine/graph/nv20.o +-nouveau-y += core/engine/graph/nv25.o +-nouveau-y += core/engine/graph/nv2a.o +-nouveau-y += core/engine/graph/nv30.o +-nouveau-y += core/engine/graph/nv34.o +-nouveau-y += core/engine/graph/nv35.o +-nouveau-y += core/engine/graph/nv40.o +-nouveau-y += core/engine/graph/nv50.o +-nouveau-y += core/engine/graph/nvc0.o +-nouveau-y += core/engine/graph/nvc1.o +-nouveau-y += core/engine/graph/nvc4.o +-nouveau-y += core/engine/graph/nvc8.o +-nouveau-y += core/engine/graph/nvd7.o +-nouveau-y += core/engine/graph/nvd9.o +-nouveau-y += core/engine/graph/nve4.o +-nouveau-y += core/engine/graph/gk20a.o +-nouveau-y += core/engine/graph/nvf0.o +-nouveau-y += core/engine/graph/gk110b.o +-nouveau-y += core/engine/graph/nv108.o +-nouveau-y += core/engine/graph/gm107.o +-nouveau-y += core/engine/mpeg/nv31.o +-nouveau-y += core/engine/mpeg/nv40.o +-nouveau-y += core/engine/mpeg/nv44.o +-nouveau-y += core/engine/mpeg/nv50.o +-nouveau-y += core/engine/mpeg/nv84.o +-nouveau-y += core/engine/perfmon/base.o +-nouveau-y += core/engine/perfmon/daemon.o +-nouveau-y += core/engine/perfmon/nv40.o +-nouveau-y += core/engine/perfmon/nv50.o +-nouveau-y += core/engine/perfmon/nv84.o +-nouveau-y += core/engine/perfmon/nva3.o +-nouveau-y += core/engine/perfmon/nvc0.o +-nouveau-y += core/engine/perfmon/nve0.o +-nouveau-y += core/engine/perfmon/nvf0.o +-nouveau-y += core/engine/ppp/nv98.o +-nouveau-y += core/engine/ppp/nvc0.o +-nouveau-y += core/engine/software/nv04.o +-nouveau-y += core/engine/software/nv10.o +-nouveau-y += core/engine/software/nv50.o +-nouveau-y += core/engine/software/nvc0.o +-nouveau-y += core/engine/vp/nv84.o +-nouveau-y += core/engine/vp/nv98.o +-nouveau-y += core/engine/vp/nvc0.o +-nouveau-y += core/engine/vp/nve0.o +- +-# nvif +-nouveau-y += nvif/object.o +-nouveau-y += nvif/client.o +-nouveau-y += nvif/device.o +-nouveau-y += nvif/notify.o +- +-# drm/core +-nouveau-y += nouveau_drm.o nouveau_chan.o nouveau_dma.o nouveau_fence.o +-nouveau-y += nouveau_vga.o nouveau_agp.o +-nouveau-y += nouveau_ttm.o nouveau_sgdma.o nouveau_bo.o nouveau_gem.o +-nouveau-y += nouveau_prime.o nouveau_abi16.o +-nouveau-y += nouveau_nvif.o nouveau_usif.o +-nouveau-y += nv04_fence.o nv10_fence.o nv17_fence.o +-nouveau-y += nv50_fence.o nv84_fence.o nvc0_fence.o +- +-# drm/kms +-nouveau-y += nouveau_bios.o nouveau_fbcon.o nouveau_display.o +-nouveau-y += nouveau_connector.o nouveau_dp.o +-nouveau-y += nv04_fbcon.o nv50_fbcon.o nvc0_fbcon.o +- +-# drm/kms/nv04:nv50 +-include $(src)/dispnv04/Makefile +- +-# drm/kms/nv50- +-nouveau-y += nv50_display.o +- +-# drm/pm +-nouveau-y += nouveau_hwmon.o nouveau_sysfs.o +- +-# other random bits +-nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o +-ifdef CONFIG_X86 +-nouveau-$(CONFIG_ACPI) += nouveau_acpi.o +-endif +-nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o +-nouveau-$(CONFIG_DEBUG_FS) += nouveau_debugfs.o +- +-obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o +- +-# platform driver +-obj-$(CONFIG_NOUVEAU_PLATFORM_DRIVER) += nouveau_platform.o +diff --git a/drivers/gpu/drm/nouveau/core/core/client.c b/drivers/gpu/drm/nouveau/core/core/client.c +deleted file mode 100644 +index e9624332..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/client.c ++++ /dev/null +@@ -1,271 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-struct nvkm_client_notify { +- struct nouveau_client *client; +- struct nvkm_notify n; +- u8 version; +- u8 size; +- union { +- struct nvif_notify_rep_v0 v0; +- } rep; +-}; +- +-static int +-nvkm_client_notify(struct nvkm_notify *n) +-{ +- struct nvkm_client_notify *notify = container_of(n, typeof(*notify), n); +- struct nouveau_client *client = notify->client; +- return client->ntfy(¬ify->rep, notify->size, n->data, n->size); +-} +- +-int +-nvkm_client_notify_put(struct nouveau_client *client, int index) +-{ +- if (index < ARRAY_SIZE(client->notify)) { +- if (client->notify[index]) { +- nvkm_notify_put(&client->notify[index]->n); +- return 0; +- } +- } +- return -ENOENT; +-} +- +-int +-nvkm_client_notify_get(struct nouveau_client *client, int index) +-{ +- if (index < ARRAY_SIZE(client->notify)) { +- if (client->notify[index]) { +- nvkm_notify_get(&client->notify[index]->n); +- return 0; +- } +- } +- return -ENOENT; +-} +- +-int +-nvkm_client_notify_del(struct nouveau_client *client, int index) +-{ +- if (index < ARRAY_SIZE(client->notify)) { +- if (client->notify[index]) { +- nvkm_notify_fini(&client->notify[index]->n); +- kfree(client->notify[index]); +- client->notify[index] = NULL; +- return 0; +- } +- } +- return -ENOENT; +-} +- +-int +-nvkm_client_notify_new(struct nouveau_object *object, +- struct nvkm_event *event, void *data, u32 size) +-{ +- struct nouveau_client *client = nouveau_client(object); +- struct nvkm_client_notify *notify; +- union { +- struct nvif_notify_req_v0 v0; +- } *req = data; +- u8 index, reply; +- int ret; +- +- for (index = 0; index < ARRAY_SIZE(client->notify); index++) { +- if (!client->notify[index]) +- break; +- } +- +- if (index == ARRAY_SIZE(client->notify)) +- return -ENOSPC; +- +- notify = kzalloc(sizeof(*notify), GFP_KERNEL); +- if (!notify) +- return -ENOMEM; +- +- nv_ioctl(client, "notify new size %d\n", size); +- if (nvif_unpack(req->v0, 0, 0, true)) { +- nv_ioctl(client, "notify new vers %d reply %d route %02x " +- "token %llx\n", req->v0.version, +- req->v0.reply, req->v0.route, req->v0.token); +- notify->version = req->v0.version; +- notify->size = sizeof(notify->rep.v0); +- notify->rep.v0.version = req->v0.version; +- notify->rep.v0.route = req->v0.route; +- notify->rep.v0.token = req->v0.token; +- reply = req->v0.reply; +- } +- +- if (ret == 0) { +- ret = nvkm_notify_init(object, event, nvkm_client_notify, +- false, data, size, reply, ¬ify->n); +- if (ret == 0) { +- client->notify[index] = notify; +- notify->client = client; +- return index; +- } +- } +- +- kfree(notify); +- return ret; +-} +- +-static int +-nouveau_client_devlist(struct nouveau_object *object, void *data, u32 size) +-{ +- union { +- struct nv_client_devlist_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "client devlist size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "client devlist vers %d count %d\n", +- args->v0.version, args->v0.count); +- if (size == sizeof(args->v0.device[0]) * args->v0.count) { +- ret = nouveau_device_list(args->v0.device, +- args->v0.count); +- if (ret >= 0) { +- args->v0.count = ret; +- ret = 0; +- } +- } else { +- ret = -EINVAL; +- } +- } +- +- return ret; +-} +- +-static int +-nouveau_client_mthd(struct nouveau_object *object, u32 mthd, +- void *data, u32 size) +-{ +- switch (mthd) { +- case NV_CLIENT_DEVLIST: +- return nouveau_client_devlist(object, data, size); +- default: +- break; +- } +- return -EINVAL; +-} +- +-static void +-nouveau_client_dtor(struct nouveau_object *object) +-{ +- struct nouveau_client *client = (void *)object; +- int i; +- for (i = 0; i < ARRAY_SIZE(client->notify); i++) +- nvkm_client_notify_del(client, i); +- nouveau_object_ref(NULL, &client->device); +- nouveau_handle_destroy(client->root); +- nouveau_namedb_destroy(&client->base); +-} +- +-static struct nouveau_oclass +-nouveau_client_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .dtor = nouveau_client_dtor, +- .mthd = nouveau_client_mthd, +- }, +-}; +- +-int +-nouveau_client_create_(const char *name, u64 devname, const char *cfg, +- const char *dbg, int length, void **pobject) +-{ +- struct nouveau_object *device; +- struct nouveau_client *client; +- int ret; +- +- device = (void *)nouveau_device_find(devname); +- if (!device) +- return -ENODEV; +- +- ret = nouveau_namedb_create_(NULL, NULL, &nouveau_client_oclass, +- NV_CLIENT_CLASS, NULL, +- (1ULL << NVDEV_ENGINE_DEVICE), +- length, pobject); +- client = *pobject; +- if (ret) +- return ret; +- +- ret = nouveau_handle_create(nv_object(client), ~0, ~0, +- nv_object(client), &client->root); +- if (ret) +- return ret; +- +- /* prevent init/fini being called, os in in charge of this */ +- atomic_set(&nv_object(client)->usecount, 2); +- +- nouveau_object_ref(device, &client->device); +- snprintf(client->name, sizeof(client->name), "%s", name); +- client->debug = nouveau_dbgopt(dbg, "CLIENT"); +- return 0; +-} +- +-int +-nouveau_client_init(struct nouveau_client *client) +-{ +- int ret; +- nv_debug(client, "init running\n"); +- ret = nouveau_handle_init(client->root); +- nv_debug(client, "init completed with %d\n", ret); +- return ret; +-} +- +-int +-nouveau_client_fini(struct nouveau_client *client, bool suspend) +-{ +- const char *name[2] = { "fini", "suspend" }; +- int ret, i; +- nv_debug(client, "%s running\n", name[suspend]); +- nv_debug(client, "%s notify\n", name[suspend]); +- for (i = 0; i < ARRAY_SIZE(client->notify); i++) +- nvkm_client_notify_put(client, i); +- nv_debug(client, "%s object\n", name[suspend]); +- ret = nouveau_handle_fini(client->root, suspend); +- nv_debug(client, "%s completed with %d\n", name[suspend], ret); +- return ret; +-} +- +-const char * +-nouveau_client_name(void *obj) +-{ +- const char *client_name = "unknown"; +- struct nouveau_client *client = nouveau_client(obj); +- if (client) +- client_name = client->name; +- return client_name; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/engctx.c b/drivers/gpu/drm/nouveau/core/core/engctx.c +deleted file mode 100644 +index 84c71fad..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/engctx.c ++++ /dev/null +@@ -1,251 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-static inline int +-nouveau_engctx_exists(struct nouveau_object *parent, +- struct nouveau_engine *engine, void **pobject) +-{ +- struct nouveau_engctx *engctx; +- struct nouveau_object *parctx; +- +- list_for_each_entry(engctx, &engine->contexts, head) { +- parctx = nv_pclass(nv_object(engctx), NV_PARENT_CLASS); +- if (parctx == parent) { +- atomic_inc(&nv_object(engctx)->refcount); +- *pobject = engctx; +- return 1; +- } +- } +- +- return 0; +-} +- +-int +-nouveau_engctx_create_(struct nouveau_object *parent, +- struct nouveau_object *engobj, +- struct nouveau_oclass *oclass, +- struct nouveau_object *pargpu, +- u32 size, u32 align, u32 flags, +- int length, void **pobject) +-{ +- struct nouveau_client *client = nouveau_client(parent); +- struct nouveau_engine *engine = nv_engine(engobj); +- struct nouveau_object *engctx; +- unsigned long save; +- int ret; +- +- /* check if this engine already has a context for the parent object, +- * and reference it instead of creating a new one +- */ +- spin_lock_irqsave(&engine->lock, save); +- ret = nouveau_engctx_exists(parent, engine, pobject); +- spin_unlock_irqrestore(&engine->lock, save); +- if (ret) +- return ret; +- +- /* create the new context, supports creating both raw objects and +- * objects backed by instance memory +- */ +- if (size) { +- ret = nouveau_gpuobj_create_(parent, engobj, oclass, +- NV_ENGCTX_CLASS, +- pargpu, size, align, flags, +- length, pobject); +- } else { +- ret = nouveau_object_create_(parent, engobj, oclass, +- NV_ENGCTX_CLASS, length, pobject); +- } +- +- engctx = *pobject; +- if (ret) +- return ret; +- +- /* must take the lock again and re-check a context doesn't already +- * exist (in case of a race) - the lock had to be dropped before as +- * it's not possible to allocate the object with it held. +- */ +- spin_lock_irqsave(&engine->lock, save); +- ret = nouveau_engctx_exists(parent, engine, pobject); +- if (ret) { +- spin_unlock_irqrestore(&engine->lock, save); +- nouveau_object_ref(NULL, &engctx); +- return ret; +- } +- +- if (client->vm) +- atomic_inc(&client->vm->engref[nv_engidx(engobj)]); +- list_add(&nv_engctx(engctx)->head, &engine->contexts); +- nv_engctx(engctx)->addr = ~0ULL; +- spin_unlock_irqrestore(&engine->lock, save); +- return 0; +-} +- +-void +-nouveau_engctx_destroy(struct nouveau_engctx *engctx) +-{ +- struct nouveau_object *engobj = nv_object(engctx)->engine; +- struct nouveau_engine *engine = nv_engine(engobj); +- struct nouveau_client *client = nouveau_client(engctx); +- unsigned long save; +- +- nouveau_gpuobj_unmap(&engctx->vma); +- spin_lock_irqsave(&engine->lock, save); +- list_del(&engctx->head); +- spin_unlock_irqrestore(&engine->lock, save); +- +- if (client->vm) +- atomic_dec(&client->vm->engref[nv_engidx(engobj)]); +- +- if (engctx->base.size) +- nouveau_gpuobj_destroy(&engctx->base); +- else +- nouveau_object_destroy(&engctx->base.base); +-} +- +-int +-nouveau_engctx_init(struct nouveau_engctx *engctx) +-{ +- struct nouveau_object *object = nv_object(engctx); +- struct nouveau_subdev *subdev = nv_subdev(object->engine); +- struct nouveau_object *parent; +- struct nouveau_subdev *pardev; +- int ret; +- +- ret = nouveau_gpuobj_init(&engctx->base); +- if (ret) +- return ret; +- +- parent = nv_pclass(object->parent, NV_PARENT_CLASS); +- pardev = nv_subdev(parent->engine); +- if (nv_parent(parent)->context_attach) { +- mutex_lock(&pardev->mutex); +- ret = nv_parent(parent)->context_attach(parent, object); +- mutex_unlock(&pardev->mutex); +- } +- +- if (ret) { +- nv_error(parent, "failed to attach %s context, %d\n", +- subdev->name, ret); +- return ret; +- } +- +- nv_debug(parent, "attached %s context\n", subdev->name); +- return 0; +-} +- +-int +-nouveau_engctx_fini(struct nouveau_engctx *engctx, bool suspend) +-{ +- struct nouveau_object *object = nv_object(engctx); +- struct nouveau_subdev *subdev = nv_subdev(object->engine); +- struct nouveau_object *parent; +- struct nouveau_subdev *pardev; +- int ret = 0; +- +- parent = nv_pclass(object->parent, NV_PARENT_CLASS); +- pardev = nv_subdev(parent->engine); +- if (nv_parent(parent)->context_detach) { +- mutex_lock(&pardev->mutex); +- ret = nv_parent(parent)->context_detach(parent, suspend, object); +- mutex_unlock(&pardev->mutex); +- } +- +- if (ret) { +- nv_error(parent, "failed to detach %s context, %d\n", +- subdev->name, ret); +- return ret; +- } +- +- nv_debug(parent, "detached %s context\n", subdev->name); +- return nouveau_gpuobj_fini(&engctx->base, suspend); +-} +- +-int +-_nouveau_engctx_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_engctx *engctx; +- int ret; +- +- ret = nouveau_engctx_create(parent, engine, oclass, NULL, 256, 256, +- NVOBJ_FLAG_ZERO_ALLOC, &engctx); +- *pobject = nv_object(engctx); +- return ret; +-} +- +-void +-_nouveau_engctx_dtor(struct nouveau_object *object) +-{ +- nouveau_engctx_destroy(nv_engctx(object)); +-} +- +-int +-_nouveau_engctx_init(struct nouveau_object *object) +-{ +- return nouveau_engctx_init(nv_engctx(object)); +-} +- +- +-int +-_nouveau_engctx_fini(struct nouveau_object *object, bool suspend) +-{ +- return nouveau_engctx_fini(nv_engctx(object), suspend); +-} +- +-struct nouveau_object * +-nouveau_engctx_get(struct nouveau_engine *engine, u64 addr) +-{ +- struct nouveau_engctx *engctx; +- unsigned long flags; +- +- spin_lock_irqsave(&engine->lock, flags); +- list_for_each_entry(engctx, &engine->contexts, head) { +- if (engctx->addr == addr) { +- engctx->save = flags; +- return nv_object(engctx); +- } +- } +- spin_unlock_irqrestore(&engine->lock, flags); +- return NULL; +-} +- +-void +-nouveau_engctx_put(struct nouveau_object *object) +-{ +- if (object) { +- struct nouveau_engine *engine = nv_engine(object->engine); +- struct nouveau_engctx *engctx = nv_engctx(object); +- spin_unlock_irqrestore(&engine->lock, engctx->save); +- } +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/engine.c b/drivers/gpu/drm/nouveau/core/core/engine.c +deleted file mode 100644 +index 1f6954ae..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/engine.c ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-int +-nouveau_engine_create_(struct nouveau_object *parent, +- struct nouveau_object *engobj, +- struct nouveau_oclass *oclass, bool enable, +- const char *iname, const char *fname, +- int length, void **pobject) +-{ +- struct nouveau_engine *engine; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engobj, oclass, NV_ENGINE_CLASS, +- iname, fname, length, pobject); +- engine = *pobject; +- if (ret) +- return ret; +- +- if (parent) { +- struct nouveau_device *device = nv_device(parent); +- int engidx = nv_engidx(nv_object(engine)); +- +- if (device->disable_mask & (1ULL << engidx)) { +- if (!nouveau_boolopt(device->cfgopt, iname, false)) { +- nv_debug(engine, "engine disabled by hw/fw\n"); +- return -ENODEV; +- } +- +- nv_warn(engine, "ignoring hw/fw engine disable\n"); +- } +- +- if (!nouveau_boolopt(device->cfgopt, iname, enable)) { +- if (!enable) +- nv_warn(engine, "disabled, %s=1 to enable\n", iname); +- return -ENODEV; +- } +- } +- +- INIT_LIST_HEAD(&engine->contexts); +- spin_lock_init(&engine->lock); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/enum.c b/drivers/gpu/drm/nouveau/core/core/enum.c +deleted file mode 100644 +index dd434790..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/enum.c ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * Copyright (C) 2010 Nouveau Project +- * +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include +- +-const struct nouveau_enum * +-nouveau_enum_find(const struct nouveau_enum *en, u32 value) +-{ +- while (en->name) { +- if (en->value == value) +- return en; +- en++; +- } +- +- return NULL; +-} +- +-const struct nouveau_enum * +-nouveau_enum_print(const struct nouveau_enum *en, u32 value) +-{ +- en = nouveau_enum_find(en, value); +- if (en) +- pr_cont("%s", en->name); +- else +- pr_cont("(unknown enum 0x%08x)", value); +- return en; +-} +- +-void +-nouveau_bitfield_print(const struct nouveau_bitfield *bf, u32 value) +-{ +- while (bf->name) { +- if (value & bf->mask) { +- pr_cont(" %s", bf->name); +- value &= ~bf->mask; +- } +- +- bf++; +- } +- +- if (value) +- pr_cont(" (unknown bits 0x%08x)", value); +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/event.c b/drivers/gpu/drm/nouveau/core/core/event.c +deleted file mode 100644 +index 760947e3..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/event.c ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* +- * Copyright 2013-2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-void +-nvkm_event_put(struct nvkm_event *event, u32 types, int index) +-{ +- assert_spin_locked(&event->refs_lock); +- while (types) { +- int type = __ffs(types); types &= ~(1 << type); +- if (--event->refs[index * event->types_nr + type] == 0) { +- if (event->func->fini) +- event->func->fini(event, 1 << type, index); +- } +- } +-} +- +-void +-nvkm_event_get(struct nvkm_event *event, u32 types, int index) +-{ +- assert_spin_locked(&event->refs_lock); +- while (types) { +- int type = __ffs(types); types &= ~(1 << type); +- if (++event->refs[index * event->types_nr + type] == 1) { +- if (event->func->init) +- event->func->init(event, 1 << type, index); +- } +- } +-} +- +-void +-nvkm_event_send(struct nvkm_event *event, u32 types, int index, +- void *data, u32 size) +-{ +- struct nvkm_notify *notify; +- unsigned long flags; +- +- if (!event->refs || WARN_ON(index >= event->index_nr)) +- return; +- +- spin_lock_irqsave(&event->list_lock, flags); +- list_for_each_entry(notify, &event->list, head) { +- if (notify->index == index && (notify->types & types)) { +- if (event->func->send) { +- event->func->send(data, size, notify); +- continue; +- } +- nvkm_notify_send(notify, data, size); +- } +- } +- spin_unlock_irqrestore(&event->list_lock, flags); +-} +- +-void +-nvkm_event_fini(struct nvkm_event *event) +-{ +- if (event->refs) { +- kfree(event->refs); +- event->refs = NULL; +- } +-} +- +-int +-nvkm_event_init(const struct nvkm_event_func *func, int types_nr, int index_nr, +- struct nvkm_event *event) +-{ +- event->refs = kzalloc(sizeof(*event->refs) * index_nr * types_nr, +- GFP_KERNEL); +- if (!event->refs) +- return -ENOMEM; +- +- event->func = func; +- event->types_nr = types_nr; +- event->index_nr = index_nr; +- spin_lock_init(&event->refs_lock); +- spin_lock_init(&event->list_lock); +- INIT_LIST_HEAD(&event->list); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/gpuobj.c b/drivers/gpu/drm/nouveau/core/core/gpuobj.c +deleted file mode 100644 +index daee8770..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/gpuobj.c ++++ /dev/null +@@ -1,323 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +-#include +- +-void +-nouveau_gpuobj_destroy(struct nouveau_gpuobj *gpuobj) +-{ +- int i; +- +- if (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE) { +- for (i = 0; i < gpuobj->size; i += 4) +- nv_wo32(gpuobj, i, 0x00000000); +- } +- +- if (gpuobj->node) { +- nouveau_mm_free(&nv_gpuobj(gpuobj->parent)->heap, +- &gpuobj->node); +- } +- +- if (gpuobj->heap.block_size) +- nouveau_mm_fini(&gpuobj->heap); +- +- nouveau_object_destroy(&gpuobj->base); +-} +- +-int +-nouveau_gpuobj_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 pclass, +- struct nouveau_object *pargpu, +- u32 size, u32 align, u32 flags, +- int length, void **pobject) +-{ +- struct nouveau_instmem *imem = nouveau_instmem(parent); +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nouveau_gpuobj *gpuobj; +- struct nouveau_mm *heap = NULL; +- int ret, i; +- u64 addr; +- +- *pobject = NULL; +- +- if (pargpu) { +- while ((pargpu = nv_pclass(pargpu, NV_GPUOBJ_CLASS))) { +- if (nv_gpuobj(pargpu)->heap.block_size) +- break; +- pargpu = pargpu->parent; +- } +- +- if (unlikely(pargpu == NULL)) { +- nv_error(parent, "no gpuobj heap\n"); +- return -EINVAL; +- } +- +- addr = nv_gpuobj(pargpu)->addr; +- heap = &nv_gpuobj(pargpu)->heap; +- atomic_inc(&parent->refcount); +- } else { +- ret = imem->alloc(imem, parent, size, align, &parent); +- pargpu = parent; +- if (ret) +- return ret; +- +- addr = nv_memobj(pargpu)->addr; +- size = nv_memobj(pargpu)->size; +- +- if (bar && bar->alloc) { +- struct nouveau_instobj *iobj = (void *)parent; +- struct nouveau_mem **mem = (void *)(iobj + 1); +- struct nouveau_mem *node = *mem; +- if (!bar->alloc(bar, parent, node, &pargpu)) { +- nouveau_object_ref(NULL, &parent); +- parent = pargpu; +- } +- } +- } +- +- ret = nouveau_object_create_(parent, engine, oclass, pclass | +- NV_GPUOBJ_CLASS, length, pobject); +- nouveau_object_ref(NULL, &parent); +- gpuobj = *pobject; +- if (ret) +- return ret; +- +- gpuobj->parent = pargpu; +- gpuobj->flags = flags; +- gpuobj->addr = addr; +- gpuobj->size = size; +- +- if (heap) { +- ret = nouveau_mm_head(heap, 0, 1, size, size, +- max(align, (u32)1), &gpuobj->node); +- if (ret) +- return ret; +- +- gpuobj->addr += gpuobj->node->offset; +- } +- +- if (gpuobj->flags & NVOBJ_FLAG_HEAP) { +- ret = nouveau_mm_init(&gpuobj->heap, 0, gpuobj->size, 1); +- if (ret) +- return ret; +- } +- +- if (flags & NVOBJ_FLAG_ZERO_ALLOC) { +- for (i = 0; i < gpuobj->size; i += 4) +- nv_wo32(gpuobj, i, 0x00000000); +- } +- +- return ret; +-} +- +-struct nouveau_gpuobj_class { +- struct nouveau_object *pargpu; +- u64 size; +- u32 align; +- u32 flags; +-}; +- +-static int +-_nouveau_gpuobj_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj_class *args = data; +- struct nouveau_gpuobj *object; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, args->pargpu, +- args->size, args->align, args->flags, +- &object); +- *pobject = nv_object(object); +- if (ret) +- return ret; +- +- return 0; +-} +- +-void +-_nouveau_gpuobj_dtor(struct nouveau_object *object) +-{ +- nouveau_gpuobj_destroy(nv_gpuobj(object)); +-} +- +-int +-_nouveau_gpuobj_init(struct nouveau_object *object) +-{ +- return nouveau_gpuobj_init(nv_gpuobj(object)); +-} +- +-int +-_nouveau_gpuobj_fini(struct nouveau_object *object, bool suspend) +-{ +- return nouveau_gpuobj_fini(nv_gpuobj(object), suspend); +-} +- +-u32 +-_nouveau_gpuobj_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_gpuobj *gpuobj = nv_gpuobj(object); +- struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent); +- if (gpuobj->node) +- addr += gpuobj->node->offset; +- return pfuncs->rd32(gpuobj->parent, addr); +-} +- +-void +-_nouveau_gpuobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nouveau_gpuobj *gpuobj = nv_gpuobj(object); +- struct nouveau_ofuncs *pfuncs = nv_ofuncs(gpuobj->parent); +- if (gpuobj->node) +- addr += gpuobj->node->offset; +- pfuncs->wr32(gpuobj->parent, addr, data); +-} +- +-static struct nouveau_oclass +-_nouveau_gpuobj_oclass = { +- .handle = 0x00000000, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_gpuobj_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +- }, +-}; +- +-int +-nouveau_gpuobj_new(struct nouveau_object *parent, struct nouveau_object *pargpu, +- u32 size, u32 align, u32 flags, +- struct nouveau_gpuobj **pgpuobj) +-{ +- struct nouveau_object *engine = parent; +- struct nouveau_gpuobj_class args = { +- .pargpu = pargpu, +- .size = size, +- .align = align, +- .flags = flags, +- }; +- +- if (!nv_iclass(engine, NV_SUBDEV_CLASS)) +- engine = engine->engine; +- BUG_ON(engine == NULL); +- +- return nouveau_object_ctor(parent, engine, &_nouveau_gpuobj_oclass, +- &args, sizeof(args), +- (struct nouveau_object **)pgpuobj); +-} +- +-int +-nouveau_gpuobj_map(struct nouveau_gpuobj *gpuobj, u32 access, +- struct nouveau_vma *vma) +-{ +- struct nouveau_bar *bar = nouveau_bar(gpuobj); +- int ret = -EINVAL; +- +- if (bar && bar->umap) { +- struct nouveau_instobj *iobj = (void *) +- nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); +- struct nouveau_mem **mem = (void *)(iobj + 1); +- ret = bar->umap(bar, *mem, access, vma); +- } +- +- return ret; +-} +- +-int +-nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm, +- u32 access, struct nouveau_vma *vma) +-{ +- struct nouveau_instobj *iobj = (void *) +- nv_pclass(nv_object(gpuobj), NV_MEMOBJ_CLASS); +- struct nouveau_mem **mem = (void *)(iobj + 1); +- int ret; +- +- ret = nouveau_vm_get(vm, gpuobj->size, 12, access, vma); +- if (ret) +- return ret; +- +- nouveau_vm_map(vma, *mem); +- return 0; +-} +- +-void +-nouveau_gpuobj_unmap(struct nouveau_vma *vma) +-{ +- if (vma->node) { +- nouveau_vm_unmap(vma); +- nouveau_vm_put(vma); +- } +-} +- +-/* the below is basically only here to support sharing the paged dma object +- * for PCI(E)GART on <=nv4x chipsets, and should *not* be expected to work +- * anywhere else. +- */ +- +-static void +-nouveau_gpudup_dtor(struct nouveau_object *object) +-{ +- struct nouveau_gpuobj *gpuobj = (void *)object; +- nouveau_object_ref(NULL, &gpuobj->parent); +- nouveau_object_destroy(&gpuobj->base); +-} +- +-static struct nouveau_oclass +-nouveau_gpudup_oclass = { +- .handle = NV_GPUOBJ_CLASS, +- .ofuncs = &(struct nouveau_ofuncs) { +- .dtor = nouveau_gpudup_dtor, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- }, +-}; +- +-int +-nouveau_gpuobj_dup(struct nouveau_object *parent, struct nouveau_gpuobj *base, +- struct nouveau_gpuobj **pgpuobj) +-{ +- struct nouveau_gpuobj *gpuobj; +- int ret; +- +- ret = nouveau_object_create(parent, parent->engine, +- &nouveau_gpudup_oclass, 0, &gpuobj); +- *pgpuobj = gpuobj; +- if (ret) +- return ret; +- +- nouveau_object_ref(nv_object(base), &gpuobj->parent); +- gpuobj->addr = base->addr; +- gpuobj->size = base->size; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/handle.c b/drivers/gpu/drm/nouveau/core/core/handle.c +deleted file mode 100644 +index a490b805..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/handle.c ++++ /dev/null +@@ -1,337 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#define hprintk(h,l,f,a...) do { \ +- struct nouveau_client *c = nouveau_client((h)->object); \ +- struct nouveau_handle *p = (h)->parent; u32 n = p ? p->name : ~0; \ +- nv_printk((c), l, "0x%08x:0x%08x "f, n, (h)->name, ##a); \ +-} while(0) +- +-int +-nouveau_handle_init(struct nouveau_handle *handle) +-{ +- struct nouveau_handle *item; +- int ret; +- +- hprintk(handle, TRACE, "init running\n"); +- ret = nouveau_object_inc(handle->object); +- if (ret) +- return ret; +- +- hprintk(handle, TRACE, "init children\n"); +- list_for_each_entry(item, &handle->tree, head) { +- ret = nouveau_handle_init(item); +- if (ret) +- goto fail; +- } +- +- hprintk(handle, TRACE, "init completed\n"); +- return 0; +-fail: +- hprintk(handle, ERROR, "init failed with %d\n", ret); +- list_for_each_entry_continue_reverse(item, &handle->tree, head) { +- nouveau_handle_fini(item, false); +- } +- +- nouveau_object_dec(handle->object, false); +- return ret; +-} +- +-int +-nouveau_handle_fini(struct nouveau_handle *handle, bool suspend) +-{ +- static char *name[2] = { "fini", "suspend" }; +- struct nouveau_handle *item; +- int ret; +- +- hprintk(handle, TRACE, "%s children\n", name[suspend]); +- list_for_each_entry(item, &handle->tree, head) { +- ret = nouveau_handle_fini(item, suspend); +- if (ret && suspend) +- goto fail; +- } +- +- hprintk(handle, TRACE, "%s running\n", name[suspend]); +- if (handle->object) { +- ret = nouveau_object_dec(handle->object, suspend); +- if (ret && suspend) +- goto fail; +- } +- +- hprintk(handle, TRACE, "%s completed\n", name[suspend]); +- return 0; +-fail: +- hprintk(handle, ERROR, "%s failed with %d\n", name[suspend], ret); +- list_for_each_entry_continue_reverse(item, &handle->tree, head) { +- int rret = nouveau_handle_init(item); +- if (rret) +- hprintk(handle, FATAL, "failed to restart, %d\n", rret); +- } +- +- return ret; +-} +- +-int +-nouveau_handle_create(struct nouveau_object *parent, u32 _parent, u32 _handle, +- struct nouveau_object *object, +- struct nouveau_handle **phandle) +-{ +- struct nouveau_object *namedb; +- struct nouveau_handle *handle; +- int ret; +- +- namedb = parent; +- while (!nv_iclass(namedb, NV_NAMEDB_CLASS)) +- namedb = namedb->parent; +- +- handle = kzalloc(sizeof(*handle), GFP_KERNEL); +- if (!handle) +- return -ENOMEM; +- +- INIT_LIST_HEAD(&handle->head); +- INIT_LIST_HEAD(&handle->tree); +- handle->name = _handle; +- handle->priv = ~0; +- +- ret = nouveau_namedb_insert(nv_namedb(namedb), _handle, object, handle); +- if (ret) { +- kfree(handle); +- return ret; +- } +- +- if (nv_parent(parent)->object_attach) { +- ret = nv_parent(parent)->object_attach(parent, object, _handle); +- if (ret < 0) { +- nouveau_handle_destroy(handle); +- return ret; +- } +- +- handle->priv = ret; +- } +- +- if (object != namedb) { +- while (!nv_iclass(namedb, NV_CLIENT_CLASS)) +- namedb = namedb->parent; +- +- handle->parent = nouveau_namedb_get(nv_namedb(namedb), _parent); +- if (handle->parent) { +- list_add(&handle->head, &handle->parent->tree); +- nouveau_namedb_put(handle->parent); +- } +- } +- +- hprintk(handle, TRACE, "created\n"); +- *phandle = handle; +- return 0; +-} +- +-void +-nouveau_handle_destroy(struct nouveau_handle *handle) +-{ +- struct nouveau_handle *item, *temp; +- +- hprintk(handle, TRACE, "destroy running\n"); +- list_for_each_entry_safe(item, temp, &handle->tree, head) { +- nouveau_handle_destroy(item); +- } +- list_del(&handle->head); +- +- if (handle->priv != ~0) { +- struct nouveau_object *parent = handle->parent->object; +- nv_parent(parent)->object_detach(parent, handle->priv); +- } +- +- hprintk(handle, TRACE, "destroy completed\n"); +- nouveau_namedb_remove(handle); +- kfree(handle); +-} +- +-struct nouveau_object * +-nouveau_handle_ref(struct nouveau_object *parent, u32 name) +-{ +- struct nouveau_object *object = NULL; +- struct nouveau_handle *handle; +- +- while (!nv_iclass(parent, NV_NAMEDB_CLASS)) +- parent = parent->parent; +- +- handle = nouveau_namedb_get(nv_namedb(parent), name); +- if (handle) { +- nouveau_object_ref(handle->object, &object); +- nouveau_namedb_put(handle); +- } +- +- return object; +-} +- +-struct nouveau_handle * +-nouveau_handle_get_class(struct nouveau_object *engctx, u16 oclass) +-{ +- struct nouveau_namedb *namedb; +- if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) +- return nouveau_namedb_get_class(namedb, oclass); +- return NULL; +-} +- +-struct nouveau_handle * +-nouveau_handle_get_vinst(struct nouveau_object *engctx, u64 vinst) +-{ +- struct nouveau_namedb *namedb; +- if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) +- return nouveau_namedb_get_vinst(namedb, vinst); +- return NULL; +-} +- +-struct nouveau_handle * +-nouveau_handle_get_cinst(struct nouveau_object *engctx, u32 cinst) +-{ +- struct nouveau_namedb *namedb; +- if (engctx && (namedb = (void *)nv_pclass(engctx, NV_NAMEDB_CLASS))) +- return nouveau_namedb_get_cinst(namedb, cinst); +- return NULL; +-} +- +-void +-nouveau_handle_put(struct nouveau_handle *handle) +-{ +- if (handle) +- nouveau_namedb_put(handle); +-} +- +-int +-nouveau_handle_new(struct nouveau_object *client, u32 _parent, u32 _handle, +- u16 _oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_object *parent = NULL; +- struct nouveau_object *engctx = NULL; +- struct nouveau_object *object = NULL; +- struct nouveau_object *engine; +- struct nouveau_oclass *oclass; +- struct nouveau_handle *handle; +- int ret; +- +- /* lookup parent object and ensure it *is* a parent */ +- parent = nouveau_handle_ref(client, _parent); +- if (!parent) { +- nv_error(client, "parent 0x%08x not found\n", _parent); +- return -ENOENT; +- } +- +- if (!nv_iclass(parent, NV_PARENT_CLASS)) { +- nv_error(parent, "cannot have children\n"); +- ret = -EINVAL; +- goto fail_class; +- } +- +- /* check that parent supports the requested subclass */ +- ret = nouveau_parent_sclass(parent, _oclass, &engine, &oclass); +- if (ret) { +- nv_debug(parent, "illegal class 0x%04x\n", _oclass); +- goto fail_class; +- } +- +- /* make sure engine init has been completed *before* any objects +- * it controls are created - the constructors may depend on +- * state calculated at init (ie. default context construction) +- */ +- if (engine) { +- ret = nouveau_object_inc(engine); +- if (ret) +- goto fail_class; +- } +- +- /* if engine requires it, create a context object to insert +- * between the parent and its children (eg. PGRAPH context) +- */ +- if (engine && nv_engine(engine)->cclass) { +- ret = nouveau_object_ctor(parent, engine, +- nv_engine(engine)->cclass, +- data, size, &engctx); +- if (ret) +- goto fail_engctx; +- } else { +- nouveau_object_ref(parent, &engctx); +- } +- +- /* finally, create new object and bind it to its handle */ +- ret = nouveau_object_ctor(engctx, engine, oclass, data, size, &object); +- *pobject = object; +- if (ret) +- goto fail_ctor; +- +- ret = nouveau_object_inc(object); +- if (ret) +- goto fail_init; +- +- ret = nouveau_handle_create(parent, _parent, _handle, object, &handle); +- if (ret) +- goto fail_handle; +- +- ret = nouveau_handle_init(handle); +- if (ret) +- nouveau_handle_destroy(handle); +- +-fail_handle: +- nouveau_object_dec(object, false); +-fail_init: +- nouveau_object_ref(NULL, &object); +-fail_ctor: +- nouveau_object_ref(NULL, &engctx); +-fail_engctx: +- if (engine) +- nouveau_object_dec(engine, false); +-fail_class: +- nouveau_object_ref(NULL, &parent); +- return ret; +-} +- +-int +-nouveau_handle_del(struct nouveau_object *client, u32 _parent, u32 _handle) +-{ +- struct nouveau_object *parent = NULL; +- struct nouveau_object *namedb = NULL; +- struct nouveau_handle *handle = NULL; +- +- parent = nouveau_handle_ref(client, _parent); +- if (!parent) +- return -ENOENT; +- +- namedb = nv_pclass(parent, NV_NAMEDB_CLASS); +- if (namedb) { +- handle = nouveau_namedb_get(nv_namedb(namedb), _handle); +- if (handle) { +- nouveau_namedb_put(handle); +- nouveau_handle_fini(handle, false); +- nouveau_handle_destroy(handle); +- } +- } +- +- nouveau_object_ref(NULL, &parent); +- return handle ? 0 : -EINVAL; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/ioctl.c b/drivers/gpu/drm/nouveau/core/core/ioctl.c +deleted file mode 100644 +index 692aa92d..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/ioctl.c ++++ /dev/null +@@ -1,530 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-static int +-nvkm_ioctl_nop(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_nop none; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "nop size %d\n", size); +- if (nvif_unvers(args->none)) { +- nv_ioctl(object, "nop\n"); +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_sclass(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_sclass_v0 v0; +- } *args = data; +- int ret; +- +- if (!nv_iclass(object, NV_PARENT_CLASS)) { +- nv_debug(object, "cannot have children (sclass)\n"); +- return -ENODEV; +- } +- +- nv_ioctl(object, "sclass size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "sclass vers %d count %d\n", +- args->v0.version, args->v0.count); +- if (size == args->v0.count * sizeof(args->v0.oclass[0])) { +- ret = nouveau_parent_lclass(object, args->v0.oclass, +- args->v0.count); +- if (ret >= 0) { +- args->v0.count = ret; +- ret = 0; +- } +- } else { +- ret = -EINVAL; +- } +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_new(struct nouveau_handle *parent, void *data, u32 size) +-{ +- union { +- struct nvif_ioctl_new_v0 v0; +- } *args = data; +- struct nouveau_client *client = nouveau_client(parent->object); +- struct nouveau_object *engctx = NULL; +- struct nouveau_object *object = NULL; +- struct nouveau_object *engine; +- struct nouveau_oclass *oclass; +- struct nouveau_handle *handle; +- u32 _handle, _oclass; +- int ret; +- +- nv_ioctl(client, "new size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- _handle = args->v0.handle; +- _oclass = args->v0.oclass; +- } else +- return ret; +- +- nv_ioctl(client, "new vers %d handle %08x class %08x " +- "route %02x token %llx\n", +- args->v0.version, _handle, _oclass, +- args->v0.route, args->v0.token); +- +- if (!nv_iclass(parent->object, NV_PARENT_CLASS)) { +- nv_debug(parent->object, "cannot have children (ctor)\n"); +- ret = -ENODEV; +- goto fail_class; +- } +- +- /* check that parent supports the requested subclass */ +- ret = nouveau_parent_sclass(parent->object, _oclass, &engine, &oclass); +- if (ret) { +- nv_debug(parent->object, "illegal class 0x%04x\n", _oclass); +- goto fail_class; +- } +- +- /* make sure engine init has been completed *before* any objects +- * it controls are created - the constructors may depend on +- * state calculated at init (ie. default context construction) +- */ +- if (engine) { +- ret = nouveau_object_inc(engine); +- if (ret) +- goto fail_class; +- } +- +- /* if engine requires it, create a context object to insert +- * between the parent and its children (eg. PGRAPH context) +- */ +- if (engine && nv_engine(engine)->cclass) { +- ret = nouveau_object_ctor(parent->object, engine, +- nv_engine(engine)->cclass, +- data, size, &engctx); +- if (ret) +- goto fail_engctx; +- } else { +- nouveau_object_ref(parent->object, &engctx); +- } +- +- /* finally, create new object and bind it to its handle */ +- ret = nouveau_object_ctor(engctx, engine, oclass, data, size, &object); +- client->data = object; +- if (ret) +- goto fail_ctor; +- +- ret = nouveau_object_inc(object); +- if (ret) +- goto fail_init; +- +- ret = nouveau_handle_create(parent->object, parent->name, +- _handle, object, &handle); +- if (ret) +- goto fail_handle; +- +- ret = nouveau_handle_init(handle); +- handle->route = args->v0.route; +- handle->token = args->v0.token; +- if (ret) +- nouveau_handle_destroy(handle); +- +-fail_handle: +- nouveau_object_dec(object, false); +-fail_init: +- nouveau_object_ref(NULL, &object); +-fail_ctor: +- nouveau_object_ref(NULL, &engctx); +-fail_engctx: +- if (engine) +- nouveau_object_dec(engine, false); +-fail_class: +- return ret; +-} +- +-static int +-nvkm_ioctl_del(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_del none; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "delete size %d\n", size); +- if (nvif_unvers(args->none)) { +- nv_ioctl(object, "delete\n"); +- nouveau_handle_fini(handle, false); +- nouveau_handle_destroy(handle); +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_mthd(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; +- union { +- struct nvif_ioctl_mthd_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "mthd size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "mthd vers %d mthd %02x\n", +- args->v0.version, args->v0.method); +- if (ret = -ENODEV, ofuncs->mthd) +- ret = ofuncs->mthd(object, args->v0.method, data, size); +- } +- +- return ret; +-} +- +- +-static int +-nvkm_ioctl_rd(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; +- union { +- struct nvif_ioctl_rd_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "rd size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "rd vers %d size %d addr %016llx\n", +- args->v0.version, args->v0.size, args->v0.addr); +- switch (args->v0.size) { +- case 1: +- if (ret = -ENODEV, ofuncs->rd08) { +- args->v0.data = nv_ro08(object, args->v0.addr); +- ret = 0; +- } +- break; +- case 2: +- if (ret = -ENODEV, ofuncs->rd16) { +- args->v0.data = nv_ro16(object, args->v0.addr); +- ret = 0; +- } +- break; +- case 4: +- if (ret = -ENODEV, ofuncs->rd32) { +- args->v0.data = nv_ro32(object, args->v0.addr); +- ret = 0; +- } +- break; +- default: +- ret = -EINVAL; +- break; +- } +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_wr(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; +- union { +- struct nvif_ioctl_wr_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "wr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "wr vers %d size %d addr %016llx data %08x\n", +- args->v0.version, args->v0.size, args->v0.addr, +- args->v0.data); +- switch (args->v0.size) { +- case 1: +- if (ret = -ENODEV, ofuncs->wr08) { +- nv_wo08(object, args->v0.addr, args->v0.data); +- ret = 0; +- } +- break; +- case 2: +- if (ret = -ENODEV, ofuncs->wr16) { +- nv_wo16(object, args->v0.addr, args->v0.data); +- ret = 0; +- } +- break; +- case 4: +- if (ret = -ENODEV, ofuncs->wr32) { +- nv_wo32(object, args->v0.addr, args->v0.data); +- ret = 0; +- } +- break; +- default: +- ret = -EINVAL; +- break; +- } +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_map(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; +- union { +- struct nvif_ioctl_map_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "map size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "map vers %d\n", args->v0.version); +- if (ret = -ENODEV, ofuncs->map) { +- ret = ofuncs->map(object, &args->v0.handle, +- &args->v0.length); +- } +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_unmap(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_unmap none; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "unmap size %d\n", size); +- if (nvif_unvers(args->none)) { +- nv_ioctl(object, "unmap\n"); +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_ntfy_new(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_object *object = handle->object; +- struct nouveau_ofuncs *ofuncs = object->oclass->ofuncs; +- union { +- struct nvif_ioctl_ntfy_new_v0 v0; +- } *args = data; +- struct nvkm_event *event; +- int ret; +- +- nv_ioctl(object, "ntfy new size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "ntfy new vers %d event %02x\n", +- args->v0.version, args->v0.event); +- if (ret = -ENODEV, ofuncs->ntfy) +- ret = ofuncs->ntfy(object, args->v0.event, &event); +- if (ret == 0) { +- ret = nvkm_client_notify_new(object, event, data, size); +- if (ret >= 0) { +- args->v0.index = ret; +- ret = 0; +- } +- } +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_ntfy_del(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_client *client = nouveau_client(handle->object); +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_ntfy_del_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "ntfy del size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "ntfy del vers %d index %d\n", +- args->v0.version, args->v0.index); +- ret = nvkm_client_notify_del(client, args->v0.index); +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_ntfy_get(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_client *client = nouveau_client(handle->object); +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_ntfy_get_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "ntfy get size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "ntfy get vers %d index %d\n", +- args->v0.version, args->v0.index); +- ret = nvkm_client_notify_get(client, args->v0.index); +- } +- +- return ret; +-} +- +-static int +-nvkm_ioctl_ntfy_put(struct nouveau_handle *handle, void *data, u32 size) +-{ +- struct nouveau_client *client = nouveau_client(handle->object); +- struct nouveau_object *object = handle->object; +- union { +- struct nvif_ioctl_ntfy_put_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "ntfy put size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "ntfy put vers %d index %d\n", +- args->v0.version, args->v0.index); +- ret = nvkm_client_notify_put(client, args->v0.index); +- } +- +- return ret; +-} +- +-static struct { +- int version; +- int (*func)(struct nouveau_handle *, void *, u32); +-} +-nvkm_ioctl_v0[] = { +- { 0x00, nvkm_ioctl_nop }, +- { 0x00, nvkm_ioctl_sclass }, +- { 0x00, nvkm_ioctl_new }, +- { 0x00, nvkm_ioctl_del }, +- { 0x00, nvkm_ioctl_mthd }, +- { 0x00, nvkm_ioctl_rd }, +- { 0x00, nvkm_ioctl_wr }, +- { 0x00, nvkm_ioctl_map }, +- { 0x00, nvkm_ioctl_unmap }, +- { 0x00, nvkm_ioctl_ntfy_new }, +- { 0x00, nvkm_ioctl_ntfy_del }, +- { 0x00, nvkm_ioctl_ntfy_get }, +- { 0x00, nvkm_ioctl_ntfy_put }, +-}; +- +-static int +-nvkm_ioctl_path(struct nouveau_handle *parent, u32 type, u32 nr, +- u32 *path, void *data, u32 size, +- u8 owner, u8 *route, u64 *token) +-{ +- struct nouveau_handle *handle = parent; +- struct nouveau_namedb *namedb; +- struct nouveau_object *object; +- int ret; +- +- while ((object = parent->object), nr--) { +- nv_ioctl(object, "path 0x%08x\n", path[nr]); +- if (!nv_iclass(object, NV_PARENT_CLASS)) { +- nv_debug(object, "cannot have children (path)\n"); +- return -EINVAL; +- } +- +- if (!(namedb = (void *)nv_pclass(object, NV_NAMEDB_CLASS)) || +- !(handle = nouveau_namedb_get(namedb, path[nr]))) { +- nv_debug(object, "handle 0x%08x not found\n", path[nr]); +- return -ENOENT; +- } +- nouveau_namedb_put(handle); +- parent = handle; +- } +- +- if (owner != NVIF_IOCTL_V0_OWNER_ANY && +- owner != handle->route) { +- nv_ioctl(object, "object route != owner\n"); +- return -EACCES; +- } +- *route = handle->route; +- *token = handle->token; +- +- if (ret = -EINVAL, type < ARRAY_SIZE(nvkm_ioctl_v0)) { +- if (nvkm_ioctl_v0[type].version == 0) { +- ret = nvkm_ioctl_v0[type].func(handle, data, size); +- } +- } +- +- return ret; +-} +- +-int +-nvkm_ioctl(struct nouveau_client *client, bool supervisor, +- void *data, u32 size, void **hack) +-{ +- union { +- struct nvif_ioctl_v0 v0; +- } *args = data; +- int ret; +- +- client->super = supervisor; +- nv_ioctl(client, "size %d\n", size); +- +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(client, "vers %d type %02x path %d owner %02x\n", +- args->v0.version, args->v0.type, args->v0.path_nr, +- args->v0.owner); +- ret = nvkm_ioctl_path(client->root, args->v0.type, +- args->v0.path_nr, args->v0.path, +- data, size, args->v0.owner, +- &args->v0.route, &args->v0.token); +- } +- +- nv_ioctl(client, "return %d\n", ret); +- if (hack) { +- *hack = client->data; +- client->data = NULL; +- } +- client->super = false; +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/mm.c b/drivers/gpu/drm/nouveau/core/core/mm.c +deleted file mode 100644 +index b4f5db66..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/mm.c ++++ /dev/null +@@ -1,303 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "core/os.h" +-#include "core/mm.h" +- +-#define node(root, dir) ((root)->nl_entry.dir == &mm->nodes) ? NULL : \ +- list_entry((root)->nl_entry.dir, struct nouveau_mm_node, nl_entry) +- +-static void +-nouveau_mm_dump(struct nouveau_mm *mm, const char *header) +-{ +- struct nouveau_mm_node *node; +- +- printk(KERN_ERR "nouveau: %s\n", header); +- printk(KERN_ERR "nouveau: node list:\n"); +- list_for_each_entry(node, &mm->nodes, nl_entry) { +- printk(KERN_ERR "nouveau: \t%08x %08x %d\n", +- node->offset, node->length, node->type); +- } +- printk(KERN_ERR "nouveau: free list:\n"); +- list_for_each_entry(node, &mm->free, fl_entry) { +- printk(KERN_ERR "nouveau: \t%08x %08x %d\n", +- node->offset, node->length, node->type); +- } +-} +- +-void +-nouveau_mm_free(struct nouveau_mm *mm, struct nouveau_mm_node **pthis) +-{ +- struct nouveau_mm_node *this = *pthis; +- +- if (this) { +- struct nouveau_mm_node *prev = node(this, prev); +- struct nouveau_mm_node *next = node(this, next); +- +- if (prev && prev->type == NVKM_MM_TYPE_NONE) { +- prev->length += this->length; +- list_del(&this->nl_entry); +- kfree(this); this = prev; +- } +- +- if (next && next->type == NVKM_MM_TYPE_NONE) { +- next->offset = this->offset; +- next->length += this->length; +- if (this->type == NVKM_MM_TYPE_NONE) +- list_del(&this->fl_entry); +- list_del(&this->nl_entry); +- kfree(this); this = NULL; +- } +- +- if (this && this->type != NVKM_MM_TYPE_NONE) { +- list_for_each_entry(prev, &mm->free, fl_entry) { +- if (this->offset < prev->offset) +- break; +- } +- +- list_add_tail(&this->fl_entry, &prev->fl_entry); +- this->type = NVKM_MM_TYPE_NONE; +- } +- } +- +- *pthis = NULL; +-} +- +-static struct nouveau_mm_node * +-region_head(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size) +-{ +- struct nouveau_mm_node *b; +- +- if (a->length == size) +- return a; +- +- b = kmalloc(sizeof(*b), GFP_KERNEL); +- if (unlikely(b == NULL)) +- return NULL; +- +- b->offset = a->offset; +- b->length = size; +- b->heap = a->heap; +- b->type = a->type; +- a->offset += size; +- a->length -= size; +- list_add_tail(&b->nl_entry, &a->nl_entry); +- if (b->type == NVKM_MM_TYPE_NONE) +- list_add_tail(&b->fl_entry, &a->fl_entry); +- return b; +-} +- +-int +-nouveau_mm_head(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max, +- u32 size_min, u32 align, struct nouveau_mm_node **pnode) +-{ +- struct nouveau_mm_node *prev, *this, *next; +- u32 mask = align - 1; +- u32 splitoff; +- u32 s, e; +- +- BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE); +- +- list_for_each_entry(this, &mm->free, fl_entry) { +- if (unlikely(heap != NVKM_MM_HEAP_ANY)) { +- if (this->heap != heap) +- continue; +- } +- e = this->offset + this->length; +- s = this->offset; +- +- prev = node(this, prev); +- if (prev && prev->type != type) +- s = roundup(s, mm->block_size); +- +- next = node(this, next); +- if (next && next->type != type) +- e = rounddown(e, mm->block_size); +- +- s = (s + mask) & ~mask; +- e &= ~mask; +- if (s > e || e - s < size_min) +- continue; +- +- splitoff = s - this->offset; +- if (splitoff && !region_head(mm, this, splitoff)) +- return -ENOMEM; +- +- this = region_head(mm, this, min(size_max, e - s)); +- if (!this) +- return -ENOMEM; +- +- this->type = type; +- list_del(&this->fl_entry); +- *pnode = this; +- return 0; +- } +- +- return -ENOSPC; +-} +- +-static struct nouveau_mm_node * +-region_tail(struct nouveau_mm *mm, struct nouveau_mm_node *a, u32 size) +-{ +- struct nouveau_mm_node *b; +- +- if (a->length == size) +- return a; +- +- b = kmalloc(sizeof(*b), GFP_KERNEL); +- if (unlikely(b == NULL)) +- return NULL; +- +- a->length -= size; +- b->offset = a->offset + a->length; +- b->length = size; +- b->heap = a->heap; +- b->type = a->type; +- +- list_add(&b->nl_entry, &a->nl_entry); +- if (b->type == NVKM_MM_TYPE_NONE) +- list_add(&b->fl_entry, &a->fl_entry); +- return b; +-} +- +-int +-nouveau_mm_tail(struct nouveau_mm *mm, u8 heap, u8 type, u32 size_max, +- u32 size_min, u32 align, struct nouveau_mm_node **pnode) +-{ +- struct nouveau_mm_node *prev, *this, *next; +- u32 mask = align - 1; +- +- BUG_ON(type == NVKM_MM_TYPE_NONE || type == NVKM_MM_TYPE_HOLE); +- +- list_for_each_entry_reverse(this, &mm->free, fl_entry) { +- u32 e = this->offset + this->length; +- u32 s = this->offset; +- u32 c = 0, a; +- if (unlikely(heap != NVKM_MM_HEAP_ANY)) { +- if (this->heap != heap) +- continue; +- } +- +- prev = node(this, prev); +- if (prev && prev->type != type) +- s = roundup(s, mm->block_size); +- +- next = node(this, next); +- if (next && next->type != type) { +- e = rounddown(e, mm->block_size); +- c = next->offset - e; +- } +- +- s = (s + mask) & ~mask; +- a = e - s; +- if (s > e || a < size_min) +- continue; +- +- a = min(a, size_max); +- s = (e - a) & ~mask; +- c += (e - s) - a; +- +- if (c && !region_tail(mm, this, c)) +- return -ENOMEM; +- +- this = region_tail(mm, this, a); +- if (!this) +- return -ENOMEM; +- +- this->type = type; +- list_del(&this->fl_entry); +- *pnode = this; +- return 0; +- } +- +- return -ENOSPC; +-} +- +-int +-nouveau_mm_init(struct nouveau_mm *mm, u32 offset, u32 length, u32 block) +-{ +- struct nouveau_mm_node *node, *prev; +- u32 next; +- +- if (nouveau_mm_initialised(mm)) { +- prev = list_last_entry(&mm->nodes, typeof(*node), nl_entry); +- next = prev->offset + prev->length; +- if (next != offset) { +- BUG_ON(next > offset); +- if (!(node = kzalloc(sizeof(*node), GFP_KERNEL))) +- return -ENOMEM; +- node->type = NVKM_MM_TYPE_HOLE; +- node->offset = next; +- node->length = offset - next; +- list_add_tail(&node->nl_entry, &mm->nodes); +- } +- BUG_ON(block != mm->block_size); +- } else { +- INIT_LIST_HEAD(&mm->nodes); +- INIT_LIST_HEAD(&mm->free); +- mm->block_size = block; +- mm->heap_nodes = 0; +- } +- +- node = kzalloc(sizeof(*node), GFP_KERNEL); +- if (!node) +- return -ENOMEM; +- +- if (length) { +- node->offset = roundup(offset, mm->block_size); +- node->length = rounddown(offset + length, mm->block_size); +- node->length -= node->offset; +- } +- +- list_add_tail(&node->nl_entry, &mm->nodes); +- list_add_tail(&node->fl_entry, &mm->free); +- node->heap = ++mm->heap_nodes; +- return 0; +-} +- +-int +-nouveau_mm_fini(struct nouveau_mm *mm) +-{ +- struct nouveau_mm_node *node, *temp; +- int nodes = 0; +- +- if (!nouveau_mm_initialised(mm)) +- return 0; +- +- list_for_each_entry(node, &mm->nodes, nl_entry) { +- if (node->type != NVKM_MM_TYPE_HOLE) { +- if (++nodes > mm->heap_nodes) { +- nouveau_mm_dump(mm, "mm not clean!"); +- return -EBUSY; +- } +- } +- } +- +- list_for_each_entry_safe(node, temp, &mm->nodes, nl_entry) { +- list_del(&node->nl_entry); +- kfree(node); +- } +- mm->heap_nodes = 0; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/namedb.c b/drivers/gpu/drm/nouveau/core/core/namedb.c +deleted file mode 100644 +index 0594a599..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/namedb.c ++++ /dev/null +@@ -1,203 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-static struct nouveau_handle * +-nouveau_namedb_lookup(struct nouveau_namedb *namedb, u32 name) +-{ +- struct nouveau_handle *handle; +- +- list_for_each_entry(handle, &namedb->list, node) { +- if (handle->name == name) +- return handle; +- } +- +- return NULL; +-} +- +-static struct nouveau_handle * +-nouveau_namedb_lookup_class(struct nouveau_namedb *namedb, u16 oclass) +-{ +- struct nouveau_handle *handle; +- +- list_for_each_entry(handle, &namedb->list, node) { +- if (nv_mclass(handle->object) == oclass) +- return handle; +- } +- +- return NULL; +-} +- +-static struct nouveau_handle * +-nouveau_namedb_lookup_vinst(struct nouveau_namedb *namedb, u64 vinst) +-{ +- struct nouveau_handle *handle; +- +- list_for_each_entry(handle, &namedb->list, node) { +- if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { +- if (nv_gpuobj(handle->object)->addr == vinst) +- return handle; +- } +- } +- +- return NULL; +-} +- +-static struct nouveau_handle * +-nouveau_namedb_lookup_cinst(struct nouveau_namedb *namedb, u32 cinst) +-{ +- struct nouveau_handle *handle; +- +- list_for_each_entry(handle, &namedb->list, node) { +- if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { +- if (nv_gpuobj(handle->object)->node && +- nv_gpuobj(handle->object)->node->offset == cinst) +- return handle; +- } +- } +- +- return NULL; +-} +- +-int +-nouveau_namedb_insert(struct nouveau_namedb *namedb, u32 name, +- struct nouveau_object *object, +- struct nouveau_handle *handle) +-{ +- int ret = -EEXIST; +- write_lock_irq(&namedb->lock); +- if (!nouveau_namedb_lookup(namedb, name)) { +- nouveau_object_ref(object, &handle->object); +- handle->namedb = namedb; +- list_add(&handle->node, &namedb->list); +- ret = 0; +- } +- write_unlock_irq(&namedb->lock); +- return ret; +-} +- +-void +-nouveau_namedb_remove(struct nouveau_handle *handle) +-{ +- struct nouveau_namedb *namedb = handle->namedb; +- struct nouveau_object *object = handle->object; +- write_lock_irq(&namedb->lock); +- list_del(&handle->node); +- write_unlock_irq(&namedb->lock); +- nouveau_object_ref(NULL, &object); +-} +- +-struct nouveau_handle * +-nouveau_namedb_get(struct nouveau_namedb *namedb, u32 name) +-{ +- struct nouveau_handle *handle; +- read_lock(&namedb->lock); +- handle = nouveau_namedb_lookup(namedb, name); +- if (handle == NULL) +- read_unlock(&namedb->lock); +- return handle; +-} +- +-struct nouveau_handle * +-nouveau_namedb_get_class(struct nouveau_namedb *namedb, u16 oclass) +-{ +- struct nouveau_handle *handle; +- read_lock(&namedb->lock); +- handle = nouveau_namedb_lookup_class(namedb, oclass); +- if (handle == NULL) +- read_unlock(&namedb->lock); +- return handle; +-} +- +-struct nouveau_handle * +-nouveau_namedb_get_vinst(struct nouveau_namedb *namedb, u64 vinst) +-{ +- struct nouveau_handle *handle; +- read_lock(&namedb->lock); +- handle = nouveau_namedb_lookup_vinst(namedb, vinst); +- if (handle == NULL) +- read_unlock(&namedb->lock); +- return handle; +-} +- +-struct nouveau_handle * +-nouveau_namedb_get_cinst(struct nouveau_namedb *namedb, u32 cinst) +-{ +- struct nouveau_handle *handle; +- read_lock(&namedb->lock); +- handle = nouveau_namedb_lookup_cinst(namedb, cinst); +- if (handle == NULL) +- read_unlock(&namedb->lock); +- return handle; +-} +- +-void +-nouveau_namedb_put(struct nouveau_handle *handle) +-{ +- if (handle) +- read_unlock(&handle->namedb->lock); +-} +- +-int +-nouveau_namedb_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 pclass, +- struct nouveau_oclass *sclass, u64 engcls, +- int length, void **pobject) +-{ +- struct nouveau_namedb *namedb; +- int ret; +- +- ret = nouveau_parent_create_(parent, engine, oclass, pclass | +- NV_NAMEDB_CLASS, sclass, engcls, +- length, pobject); +- namedb = *pobject; +- if (ret) +- return ret; +- +- rwlock_init(&namedb->lock); +- INIT_LIST_HEAD(&namedb->list); +- return 0; +-} +- +-int +-_nouveau_namedb_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_namedb *object; +- int ret; +- +- ret = nouveau_namedb_create(parent, engine, oclass, 0, NULL, 0, &object); +- *pobject = nv_object(object); +- if (ret) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/notify.c b/drivers/gpu/drm/nouveau/core/core/notify.c +deleted file mode 100644 +index 839a3257..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/notify.c ++++ /dev/null +@@ -1,168 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +- +-static inline void +-nvkm_notify_put_locked(struct nvkm_notify *notify) +-{ +- if (notify->block++ == 0) +- nvkm_event_put(notify->event, notify->types, notify->index); +-} +- +-void +-nvkm_notify_put(struct nvkm_notify *notify) +-{ +- struct nvkm_event *event = notify->event; +- unsigned long flags; +- if (likely(event) && +- test_and_clear_bit(NVKM_NOTIFY_USER, ¬ify->flags)) { +- spin_lock_irqsave(&event->refs_lock, flags); +- nvkm_notify_put_locked(notify); +- spin_unlock_irqrestore(&event->refs_lock, flags); +- if (test_bit(NVKM_NOTIFY_WORK, ¬ify->flags)) +- flush_work(¬ify->work); +- } +-} +- +-static inline void +-nvkm_notify_get_locked(struct nvkm_notify *notify) +-{ +- if (--notify->block == 0) +- nvkm_event_get(notify->event, notify->types, notify->index); +-} +- +-void +-nvkm_notify_get(struct nvkm_notify *notify) +-{ +- struct nvkm_event *event = notify->event; +- unsigned long flags; +- if (likely(event) && +- !test_and_set_bit(NVKM_NOTIFY_USER, ¬ify->flags)) { +- spin_lock_irqsave(&event->refs_lock, flags); +- nvkm_notify_get_locked(notify); +- spin_unlock_irqrestore(&event->refs_lock, flags); +- } +-} +- +-static inline void +-nvkm_notify_func(struct nvkm_notify *notify) +-{ +- struct nvkm_event *event = notify->event; +- int ret = notify->func(notify); +- unsigned long flags; +- if ((ret == NVKM_NOTIFY_KEEP) || +- !test_and_clear_bit(NVKM_NOTIFY_USER, ¬ify->flags)) { +- spin_lock_irqsave(&event->refs_lock, flags); +- nvkm_notify_get_locked(notify); +- spin_unlock_irqrestore(&event->refs_lock, flags); +- } +-} +- +-static void +-nvkm_notify_work(struct work_struct *work) +-{ +- struct nvkm_notify *notify = container_of(work, typeof(*notify), work); +- nvkm_notify_func(notify); +-} +- +-void +-nvkm_notify_send(struct nvkm_notify *notify, void *data, u32 size) +-{ +- struct nvkm_event *event = notify->event; +- unsigned long flags; +- +- assert_spin_locked(&event->list_lock); +- BUG_ON(size != notify->size); +- +- spin_lock_irqsave(&event->refs_lock, flags); +- if (notify->block) { +- spin_unlock_irqrestore(&event->refs_lock, flags); +- return; +- } +- nvkm_notify_put_locked(notify); +- spin_unlock_irqrestore(&event->refs_lock, flags); +- +- if (test_bit(NVKM_NOTIFY_WORK, ¬ify->flags)) { +- memcpy((void *)notify->data, data, size); +- schedule_work(¬ify->work); +- } else { +- notify->data = data; +- nvkm_notify_func(notify); +- notify->data = NULL; +- } +-} +- +-void +-nvkm_notify_fini(struct nvkm_notify *notify) +-{ +- unsigned long flags; +- if (notify->event) { +- nvkm_notify_put(notify); +- spin_lock_irqsave(¬ify->event->list_lock, flags); +- list_del(¬ify->head); +- spin_unlock_irqrestore(¬ify->event->list_lock, flags); +- kfree((void *)notify->data); +- notify->event = NULL; +- } +-} +- +-int +-nvkm_notify_init(struct nouveau_object *object, struct nvkm_event *event, +- int (*func)(struct nvkm_notify *), bool work, +- void *data, u32 size, u32 reply, +- struct nvkm_notify *notify) +-{ +- unsigned long flags; +- int ret = -ENODEV; +- if ((notify->event = event), event->refs) { +- ret = event->func->ctor(object, data, size, notify); +- if (ret == 0 && (ret = -EINVAL, notify->size == reply)) { +- notify->flags = 0; +- notify->block = 1; +- notify->func = func; +- notify->data = NULL; +- if (ret = 0, work) { +- INIT_WORK(¬ify->work, nvkm_notify_work); +- set_bit(NVKM_NOTIFY_WORK, ¬ify->flags); +- notify->data = kmalloc(reply, GFP_KERNEL); +- if (!notify->data) +- ret = -ENOMEM; +- } +- } +- if (ret == 0) { +- spin_lock_irqsave(&event->list_lock, flags); +- list_add_tail(¬ify->head, &event->list); +- spin_unlock_irqrestore(&event->list_lock, flags); +- } +- } +- if (ret) +- notify->event = NULL; +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/object.c b/drivers/gpu/drm/nouveau/core/core/object.c +deleted file mode 100644 +index b0863057..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/object.c ++++ /dev/null +@@ -1,334 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#ifdef NOUVEAU_OBJECT_MAGIC +-static struct list_head _objlist = LIST_HEAD_INIT(_objlist); +-static DEFINE_SPINLOCK(_objlist_lock); +-#endif +- +-int +-nouveau_object_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 pclass, +- int size, void **pobject) +-{ +- struct nouveau_object *object; +- +- object = *pobject = kzalloc(size, GFP_KERNEL); +- if (!object) +- return -ENOMEM; +- +- nouveau_object_ref(parent, &object->parent); +- nouveau_object_ref(engine, &object->engine); +- object->oclass = oclass; +- object->oclass->handle |= pclass; +- atomic_set(&object->refcount, 1); +- atomic_set(&object->usecount, 0); +- +-#ifdef NOUVEAU_OBJECT_MAGIC +- object->_magic = NOUVEAU_OBJECT_MAGIC; +- spin_lock(&_objlist_lock); +- list_add(&object->list, &_objlist); +- spin_unlock(&_objlist_lock); +-#endif +- return 0; +-} +- +-int +-_nouveau_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- if (size != 0) +- return -ENOSYS; +- return nouveau_object_create(parent, engine, oclass, 0, pobject); +-} +- +-void +-nouveau_object_destroy(struct nouveau_object *object) +-{ +-#ifdef NOUVEAU_OBJECT_MAGIC +- spin_lock(&_objlist_lock); +- list_del(&object->list); +- spin_unlock(&_objlist_lock); +-#endif +- nouveau_object_ref(NULL, &object->engine); +- nouveau_object_ref(NULL, &object->parent); +- kfree(object); +-} +- +-int +-nouveau_object_init(struct nouveau_object *object) +-{ +- return 0; +-} +- +-int +-nouveau_object_fini(struct nouveau_object *object, bool suspend) +-{ +- return 0; +-} +- +-struct nouveau_ofuncs +-nouveau_object_ofuncs = { +- .ctor = _nouveau_object_ctor, +- .dtor = nouveau_object_destroy, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +-}; +- +-int +-nouveau_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_ofuncs *ofuncs = oclass->ofuncs; +- struct nouveau_object *object = NULL; +- int ret; +- +- ret = ofuncs->ctor(parent, engine, oclass, data, size, &object); +- *pobject = object; +- if (ret < 0) { +- if (ret != -ENODEV) { +- nv_error(parent, "failed to create 0x%08x, %d\n", +- oclass->handle, ret); +- } +- +- if (object) { +- ofuncs->dtor(object); +- *pobject = NULL; +- } +- +- return ret; +- } +- +- if (ret == 0) { +- nv_trace(object, "created\n"); +- atomic_set(&object->refcount, 1); +- } +- +- return 0; +-} +- +-static void +-nouveau_object_dtor(struct nouveau_object *object) +-{ +- nv_trace(object, "destroying\n"); +- nv_ofuncs(object)->dtor(object); +-} +- +-void +-nouveau_object_ref(struct nouveau_object *obj, struct nouveau_object **ref) +-{ +- if (obj) { +- atomic_inc(&obj->refcount); +- nv_trace(obj, "inc() == %d\n", atomic_read(&obj->refcount)); +- } +- +- if (*ref) { +- int dead = atomic_dec_and_test(&(*ref)->refcount); +- nv_trace(*ref, "dec() == %d\n", atomic_read(&(*ref)->refcount)); +- if (dead) +- nouveau_object_dtor(*ref); +- } +- +- *ref = obj; +-} +- +-int +-nouveau_object_inc(struct nouveau_object *object) +-{ +- int ref = atomic_add_return(1, &object->usecount); +- int ret; +- +- nv_trace(object, "use(+1) == %d\n", atomic_read(&object->usecount)); +- if (ref != 1) +- return 0; +- +- nv_trace(object, "initialising...\n"); +- if (object->parent) { +- ret = nouveau_object_inc(object->parent); +- if (ret) { +- nv_error(object, "parent failed, %d\n", ret); +- goto fail_parent; +- } +- } +- +- if (object->engine) { +- mutex_lock(&nv_subdev(object->engine)->mutex); +- ret = nouveau_object_inc(object->engine); +- mutex_unlock(&nv_subdev(object->engine)->mutex); +- if (ret) { +- nv_error(object, "engine failed, %d\n", ret); +- goto fail_engine; +- } +- } +- +- ret = nv_ofuncs(object)->init(object); +- atomic_set(&object->usecount, 1); +- if (ret) { +- nv_error(object, "init failed, %d\n", ret); +- goto fail_self; +- } +- +- nv_trace(object, "initialised\n"); +- return 0; +- +-fail_self: +- if (object->engine) { +- mutex_lock(&nv_subdev(object->engine)->mutex); +- nouveau_object_dec(object->engine, false); +- mutex_unlock(&nv_subdev(object->engine)->mutex); +- } +-fail_engine: +- if (object->parent) +- nouveau_object_dec(object->parent, false); +-fail_parent: +- atomic_dec(&object->usecount); +- return ret; +-} +- +-static int +-nouveau_object_decf(struct nouveau_object *object) +-{ +- int ret; +- +- nv_trace(object, "stopping...\n"); +- +- ret = nv_ofuncs(object)->fini(object, false); +- atomic_set(&object->usecount, 0); +- if (ret) +- nv_warn(object, "failed fini, %d\n", ret); +- +- if (object->engine) { +- mutex_lock(&nv_subdev(object->engine)->mutex); +- nouveau_object_dec(object->engine, false); +- mutex_unlock(&nv_subdev(object->engine)->mutex); +- } +- +- if (object->parent) +- nouveau_object_dec(object->parent, false); +- +- nv_trace(object, "stopped\n"); +- return 0; +-} +- +-static int +-nouveau_object_decs(struct nouveau_object *object) +-{ +- int ret, rret; +- +- nv_trace(object, "suspending...\n"); +- +- ret = nv_ofuncs(object)->fini(object, true); +- atomic_set(&object->usecount, 0); +- if (ret) { +- nv_error(object, "failed suspend, %d\n", ret); +- return ret; +- } +- +- if (object->engine) { +- mutex_lock(&nv_subdev(object->engine)->mutex); +- ret = nouveau_object_dec(object->engine, true); +- mutex_unlock(&nv_subdev(object->engine)->mutex); +- if (ret) { +- nv_warn(object, "engine failed suspend, %d\n", ret); +- goto fail_engine; +- } +- } +- +- if (object->parent) { +- ret = nouveau_object_dec(object->parent, true); +- if (ret) { +- nv_warn(object, "parent failed suspend, %d\n", ret); +- goto fail_parent; +- } +- } +- +- nv_trace(object, "suspended\n"); +- return 0; +- +-fail_parent: +- if (object->engine) { +- mutex_lock(&nv_subdev(object->engine)->mutex); +- rret = nouveau_object_inc(object->engine); +- mutex_unlock(&nv_subdev(object->engine)->mutex); +- if (rret) +- nv_fatal(object, "engine failed to reinit, %d\n", rret); +- } +- +-fail_engine: +- rret = nv_ofuncs(object)->init(object); +- if (rret) +- nv_fatal(object, "failed to reinit, %d\n", rret); +- +- return ret; +-} +- +-int +-nouveau_object_dec(struct nouveau_object *object, bool suspend) +-{ +- int ref = atomic_add_return(-1, &object->usecount); +- int ret; +- +- nv_trace(object, "use(-1) == %d\n", atomic_read(&object->usecount)); +- +- if (ref == 0) { +- if (suspend) +- ret = nouveau_object_decs(object); +- else +- ret = nouveau_object_decf(object); +- +- if (ret) { +- atomic_inc(&object->usecount); +- return ret; +- } +- } +- +- return 0; +-} +- +-void +-nouveau_object_debug(void) +-{ +-#ifdef NOUVEAU_OBJECT_MAGIC +- struct nouveau_object *object; +- if (!list_empty(&_objlist)) { +- nv_fatal(NULL, "*******************************************\n"); +- nv_fatal(NULL, "* AIIIII! object(s) still exist!!!\n"); +- nv_fatal(NULL, "*******************************************\n"); +- list_for_each_entry(object, &_objlist, list) { +- nv_fatal(object, "%p/%p/%d/%d\n", +- object->parent, object->engine, +- atomic_read(&object->refcount), +- atomic_read(&object->usecount)); +- } +- } +-#endif +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/option.c b/drivers/gpu/drm/nouveau/core/core/option.c +deleted file mode 100644 +index 9f6fcc5f..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/option.c ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-const char * +-nouveau_stropt(const char *optstr, const char *opt, int *arglen) +-{ +- while (optstr && *optstr != '\0') { +- int len = strcspn(optstr, ",="); +- switch (optstr[len]) { +- case '=': +- if (!strncasecmpz(optstr, opt, len)) { +- optstr += len + 1; +- *arglen = strcspn(optstr, ",="); +- return *arglen ? optstr : NULL; +- } +- optstr++; +- break; +- case ',': +- optstr++; +- break; +- default: +- break; +- } +- optstr += len; +- } +- +- return NULL; +-} +- +-bool +-nouveau_boolopt(const char *optstr, const char *opt, bool value) +-{ +- int arglen; +- +- optstr = nouveau_stropt(optstr, opt, &arglen); +- if (optstr) { +- if (!strncasecmpz(optstr, "0", arglen) || +- !strncasecmpz(optstr, "no", arglen) || +- !strncasecmpz(optstr, "off", arglen) || +- !strncasecmpz(optstr, "false", arglen)) +- value = false; +- else +- if (!strncasecmpz(optstr, "1", arglen) || +- !strncasecmpz(optstr, "yes", arglen) || +- !strncasecmpz(optstr, "on", arglen) || +- !strncasecmpz(optstr, "true", arglen)) +- value = true; +- } +- +- return value; +-} +- +-int +-nouveau_dbgopt(const char *optstr, const char *sub) +-{ +- int mode = 1, level = CONFIG_NOUVEAU_DEBUG_DEFAULT; +- +- while (optstr) { +- int len = strcspn(optstr, ",="); +- switch (optstr[len]) { +- case '=': +- if (strncasecmpz(optstr, sub, len)) +- mode = 0; +- optstr++; +- break; +- default: +- if (mode) { +- if (!strncasecmpz(optstr, "fatal", len)) +- level = NV_DBG_FATAL; +- else if (!strncasecmpz(optstr, "error", len)) +- level = NV_DBG_ERROR; +- else if (!strncasecmpz(optstr, "warn", len)) +- level = NV_DBG_WARN; +- else if (!strncasecmpz(optstr, "info", len)) +- level = NV_DBG_INFO_NORMAL; +- else if (!strncasecmpz(optstr, "debug", len)) +- level = NV_DBG_DEBUG; +- else if (!strncasecmpz(optstr, "trace", len)) +- level = NV_DBG_TRACE; +- else if (!strncasecmpz(optstr, "paranoia", len)) +- level = NV_DBG_PARANOIA; +- else if (!strncasecmpz(optstr, "spam", len)) +- level = NV_DBG_SPAM; +- } +- +- if (optstr[len] != '\0') { +- optstr++; +- mode = 1; +- break; +- } +- +- return level; +- } +- optstr += len; +- } +- +- return level; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/parent.c b/drivers/gpu/drm/nouveau/core/core/parent.c +deleted file mode 100644 +index 30a29118..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/parent.c ++++ /dev/null +@@ -1,161 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-int +-nouveau_parent_sclass(struct nouveau_object *parent, u16 handle, +- struct nouveau_object **pengine, +- struct nouveau_oclass **poclass) +-{ +- struct nouveau_sclass *sclass; +- struct nouveau_engine *engine; +- struct nouveau_oclass *oclass; +- u64 mask; +- +- sclass = nv_parent(parent)->sclass; +- while (sclass) { +- if ((sclass->oclass->handle & 0xffff) == handle) { +- *pengine = parent->engine; +- *poclass = sclass->oclass; +- return 0; +- } +- +- sclass = sclass->sclass; +- } +- +- mask = nv_parent(parent)->engine; +- while (mask) { +- int i = __ffs64(mask); +- +- if (nv_iclass(parent, NV_CLIENT_CLASS)) +- engine = nv_engine(nv_client(parent)->device); +- else +- engine = nouveau_engine(parent, i); +- +- if (engine) { +- oclass = engine->sclass; +- while (oclass->ofuncs) { +- if ((oclass->handle & 0xffff) == handle) { +- *pengine = nv_object(engine); +- *poclass = oclass; +- return 0; +- } +- oclass++; +- } +- } +- +- mask &= ~(1ULL << i); +- } +- +- return -EINVAL; +-} +- +-int +-nouveau_parent_lclass(struct nouveau_object *parent, u32 *lclass, int size) +-{ +- struct nouveau_sclass *sclass; +- struct nouveau_engine *engine; +- struct nouveau_oclass *oclass; +- int nr = -1, i; +- u64 mask; +- +- sclass = nv_parent(parent)->sclass; +- while (sclass) { +- if (++nr < size) +- lclass[nr] = sclass->oclass->handle & 0xffff; +- sclass = sclass->sclass; +- } +- +- mask = nv_parent(parent)->engine; +- while (i = __ffs64(mask), mask) { +- engine = nouveau_engine(parent, i); +- if (engine && (oclass = engine->sclass)) { +- while (oclass->ofuncs) { +- if (++nr < size) +- lclass[nr] = oclass->handle & 0xffff; +- oclass++; +- } +- } +- +- mask &= ~(1ULL << i); +- } +- +- return nr + 1; +-} +- +-int +-nouveau_parent_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 pclass, +- struct nouveau_oclass *sclass, u64 engcls, +- int size, void **pobject) +-{ +- struct nouveau_parent *object; +- struct nouveau_sclass *nclass; +- int ret; +- +- ret = nouveau_object_create_(parent, engine, oclass, pclass | +- NV_PARENT_CLASS, size, pobject); +- object = *pobject; +- if (ret) +- return ret; +- +- while (sclass && sclass->ofuncs) { +- nclass = kzalloc(sizeof(*nclass), GFP_KERNEL); +- if (!nclass) +- return -ENOMEM; +- +- nclass->sclass = object->sclass; +- object->sclass = nclass; +- nclass->engine = engine ? nv_engine(engine) : NULL; +- nclass->oclass = sclass; +- sclass++; +- } +- +- object->engine = engcls; +- return 0; +-} +- +-void +-nouveau_parent_destroy(struct nouveau_parent *parent) +-{ +- struct nouveau_sclass *sclass; +- +- while ((sclass = parent->sclass)) { +- parent->sclass = sclass->sclass; +- kfree(sclass); +- } +- +- nouveau_object_destroy(&parent->base); +-} +- +- +-void +-_nouveau_parent_dtor(struct nouveau_object *object) +-{ +- nouveau_parent_destroy(nv_parent(object)); +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/printk.c b/drivers/gpu/drm/nouveau/core/core/printk.c +deleted file mode 100644 +index 03e0060b..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/printk.c ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-int nv_info_debug_level = NV_DBG_INFO_NORMAL; +- +-void +-nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...) +-{ +- static const char name[] = { '!', 'E', 'W', ' ', 'D', 'T', 'P', 'S' }; +- const char *pfx; +- char mfmt[256]; +- va_list args; +- +- switch (level) { +- case NV_DBG_FATAL: +- pfx = KERN_CRIT; +- break; +- case NV_DBG_ERROR: +- pfx = KERN_ERR; +- break; +- case NV_DBG_WARN: +- pfx = KERN_WARNING; +- break; +- case NV_DBG_INFO_NORMAL: +- pfx = KERN_INFO; +- break; +- case NV_DBG_DEBUG: +- case NV_DBG_PARANOIA: +- case NV_DBG_TRACE: +- case NV_DBG_SPAM: +- default: +- pfx = KERN_DEBUG; +- break; +- } +- +- if (object && !nv_iclass(object, NV_CLIENT_CLASS)) { +- struct nouveau_object *device = object; +- struct nouveau_object *subdev = object; +- char obuf[64], *ofmt = ""; +- +- if (object->engine) { +- snprintf(obuf, sizeof(obuf), "[0x%08x][%p]", +- nv_hclass(object), object); +- ofmt = obuf; +- subdev = object->engine; +- device = object->engine; +- } +- +- if (subdev->parent) +- device = subdev->parent; +- +- if (level > nv_subdev(subdev)->debug) +- return; +- +- snprintf(mfmt, sizeof(mfmt), "%snouveau %c[%8s][%s]%s %s", pfx, +- name[level], nv_subdev(subdev)->name, +- nv_device(device)->name, ofmt, fmt); +- } else +- if (object && nv_iclass(object, NV_CLIENT_CLASS)) { +- if (level > nv_client(object)->debug) +- return; +- +- snprintf(mfmt, sizeof(mfmt), "%snouveau %c[%8s] %s", pfx, +- name[level], nv_client(object)->name, fmt); +- } else { +- snprintf(mfmt, sizeof(mfmt), "%snouveau: %s", pfx, fmt); +- } +- +- va_start(args, fmt); +- vprintk(mfmt, args); +- va_end(args); +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/ramht.c b/drivers/gpu/drm/nouveau/core/core/ramht.c +deleted file mode 100644 +index f3b9bddc..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/ramht.c ++++ /dev/null +@@ -1,108 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-#include +- +-static u32 +-nouveau_ramht_hash(struct nouveau_ramht *ramht, int chid, u32 handle) +-{ +- u32 hash = 0; +- +- while (handle) { +- hash ^= (handle & ((1 << ramht->bits) - 1)); +- handle >>= ramht->bits; +- } +- +- hash ^= chid << (ramht->bits - 4); +- hash = hash << 3; +- return hash; +-} +- +-int +-nouveau_ramht_insert(struct nouveau_ramht *ramht, int chid, +- u32 handle, u32 context) +-{ +- struct nouveau_bar *bar = nouveau_bar(ramht); +- u32 co, ho; +- +- co = ho = nouveau_ramht_hash(ramht, chid, handle); +- do { +- if (!nv_ro32(ramht, co + 4)) { +- nv_wo32(ramht, co + 0, handle); +- nv_wo32(ramht, co + 4, context); +- if (bar) +- bar->flush(bar); +- return co; +- } +- +- co += 8; +- if (co >= nv_gpuobj(ramht)->size) +- co = 0; +- } while (co != ho); +- +- return -ENOMEM; +-} +- +-void +-nouveau_ramht_remove(struct nouveau_ramht *ramht, int cookie) +-{ +- struct nouveau_bar *bar = nouveau_bar(ramht); +- nv_wo32(ramht, cookie + 0, 0x00000000); +- nv_wo32(ramht, cookie + 4, 0x00000000); +- if (bar) +- bar->flush(bar); +-} +- +-static struct nouveau_oclass +-nouveau_ramht_oclass = { +- .handle = 0x0000abcd, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = NULL, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +- }, +-}; +- +-int +-nouveau_ramht_new(struct nouveau_object *parent, struct nouveau_object *pargpu, +- u32 size, u32 align, struct nouveau_ramht **pramht) +-{ +- struct nouveau_ramht *ramht; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, parent->engine ? +- parent->engine : parent, /* bits = order_base_2(nv_gpuobj(ramht)->size >> 3); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/core/subdev.c b/drivers/gpu/drm/nouveau/core/core/subdev.c +deleted file mode 100644 +index 2ea5568b..00000000 +--- a/drivers/gpu/drm/nouveau/core/core/subdev.c ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-void +-nouveau_subdev_reset(struct nouveau_object *subdev) +-{ +- nv_trace(subdev, "resetting...\n"); +- nv_ofuncs(subdev)->fini(subdev, false); +- nv_debug(subdev, "reset\n"); +-} +- +-int +-nouveau_subdev_init(struct nouveau_subdev *subdev) +-{ +- int ret = nouveau_object_init(&subdev->base); +- if (ret) +- return ret; +- +- nouveau_subdev_reset(&subdev->base); +- return 0; +-} +- +-int +-_nouveau_subdev_init(struct nouveau_object *object) +-{ +- return nouveau_subdev_init(nv_subdev(object)); +-} +- +-int +-nouveau_subdev_fini(struct nouveau_subdev *subdev, bool suspend) +-{ +- if (subdev->unit) { +- nv_mask(subdev, 0x000200, subdev->unit, 0x00000000); +- nv_mask(subdev, 0x000200, subdev->unit, subdev->unit); +- } +- +- return nouveau_object_fini(&subdev->base, suspend); +-} +- +-int +-_nouveau_subdev_fini(struct nouveau_object *object, bool suspend) +-{ +- return nouveau_subdev_fini(nv_subdev(object), suspend); +-} +- +-void +-nouveau_subdev_destroy(struct nouveau_subdev *subdev) +-{ +- int subidx = nv_hclass(subdev) & 0xff; +- nv_device(subdev)->subdev[subidx] = NULL; +- nouveau_object_destroy(&subdev->base); +-} +- +-void +-_nouveau_subdev_dtor(struct nouveau_object *object) +-{ +- nouveau_subdev_destroy(nv_subdev(object)); +-} +- +-int +-nouveau_subdev_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 pclass, +- const char *subname, const char *sysname, +- int size, void **pobject) +-{ +- struct nouveau_subdev *subdev; +- int ret; +- +- ret = nouveau_object_create_(parent, engine, oclass, pclass | +- NV_SUBDEV_CLASS, size, pobject); +- subdev = *pobject; +- if (ret) +- return ret; +- +- __mutex_init(&subdev->mutex, subname, &oclass->lock_class_key); +- subdev->name = subname; +- +- if (parent) { +- struct nouveau_device *device = nv_device(parent); +- subdev->debug = nouveau_dbgopt(device->dbgopt, subname); +- subdev->mmio = nv_subdev(device)->mmio; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c +deleted file mode 100644 +index 1e8e75c0..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv84.c ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs, Ilia Mirkin +- */ +- +-#include +-#include +- +-/******************************************************************************* +- * BSP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_bsp_sclass[] = { +- { 0x74b0, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * BSP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_bsp_cclass = { +- .handle = NV_ENGCTX(BSP, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_xtensa_engctx_ctor, +- .dtor = _nouveau_engctx_dtor, +- .init = _nouveau_engctx_init, +- .fini = _nouveau_engctx_fini, +- .rd32 = _nouveau_engctx_rd32, +- .wr32 = _nouveau_engctx_wr32, +- }, +-}; +- +-/******************************************************************************* +- * BSP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv84_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_xtensa *priv; +- int ret; +- +- ret = nouveau_xtensa_create(parent, engine, oclass, 0x103000, true, +- "PBSP", "bsp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x04008000; +- nv_engine(priv)->cclass = &nv84_bsp_cclass; +- nv_engine(priv)->sclass = nv84_bsp_sclass; +- priv->fifo_val = 0x1111; +- priv->unkd28 = 0x90044; +- return 0; +-} +- +-struct nouveau_oclass +-nv84_bsp_oclass = { +- .handle = NV_ENGINE(BSP, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_bsp_ctor, +- .dtor = _nouveau_xtensa_dtor, +- .init = _nouveau_xtensa_init, +- .fini = _nouveau_xtensa_fini, +- .rd32 = _nouveau_xtensa_rd32, +- .wr32 = _nouveau_xtensa_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c +deleted file mode 100644 +index 6b089e02..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nv98.c ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin +- */ +- +-#include +-#include +- +-struct nv98_bsp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * BSP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_bsp_sclass[] = { +- { 0x88b1, &nouveau_object_ofuncs }, +- { 0x85b1, &nouveau_object_ofuncs }, +- { 0x86b1, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PBSP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_bsp_cclass = { +- .handle = NV_ENGCTX(BSP, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PBSP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv98_bsp_init(struct nouveau_object *object) +-{ +- struct nv98_bsp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x084010, 0x0000ffd2); +- nv_wr32(priv, 0x08401c, 0x0000fff2); +- return 0; +-} +- +-static int +-nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv98_bsp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, +- "PBSP", "bsp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x04008000; +- nv_engine(priv)->cclass = &nv98_bsp_cclass; +- nv_engine(priv)->sclass = nv98_bsp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nv98_bsp_oclass = { +- .handle = NV_ENGINE(BSP, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv98_bsp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nv98_bsp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c +deleted file mode 100644 +index ce860de4..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nvc0.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Maarten Lankhorst +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Maarten Lankhorst +- */ +- +-#include +-#include +- +-struct nvc0_bsp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * BSP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_bsp_sclass[] = { +- { 0x90b1, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PBSP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_bsp_cclass = { +- .handle = NV_ENGCTX(BSP, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PBSP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nvc0_bsp_init(struct nouveau_object *object) +-{ +- struct nvc0_bsp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x084010, 0x0000fff2); +- nv_wr32(priv, 0x08401c, 0x0000fff2); +- return 0; +-} +- +-static int +-nvc0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_bsp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, +- "PBSP", "bsp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00008000; +- nv_subdev(priv)->intr = nouveau_falcon_intr; +- nv_engine(priv)->cclass = &nvc0_bsp_cclass; +- nv_engine(priv)->sclass = nvc0_bsp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_bsp_oclass = { +- .handle = NV_ENGINE(BSP, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_bsp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nvc0_bsp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c +deleted file mode 100644 +index ba6aeca0..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/bsp/nve0.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-struct nve0_bsp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * BSP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve0_bsp_sclass[] = { +- { 0x95b1, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PBSP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve0_bsp_cclass = { +- .handle = NV_ENGCTX(BSP, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PBSP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nve0_bsp_init(struct nouveau_object *object) +-{ +- struct nve0_bsp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x084010, 0x0000fff2); +- nv_wr32(priv, 0x08401c, 0x0000fff2); +- return 0; +-} +- +-static int +-nve0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_bsp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, +- "PBSP", "bsp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00008000; +- nv_subdev(priv)->intr = nouveau_falcon_intr; +- nv_engine(priv)->cclass = &nve0_bsp_cclass; +- nv_engine(priv)->sclass = nve0_bsp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nve0_bsp_oclass = { +- .handle = NV_ENGINE(BSP, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_bsp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nve0_bsp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc +deleted file mode 100644 +index 219850d5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc ++++ /dev/null +@@ -1,872 +0,0 @@ +-/* fuc microcode for copy engine on nva3- chipsets +- * +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-/* To build for nva3:nvc0 +- * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h +- * +- * To build for nvc0- +- * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h +- */ +- +-ifdef(`NVA3', +-.section #nva3_pcopy_data +-, +-.section #nvc0_pcopy_data +-) +- +-ctx_object: .b32 0 +-ifdef(`NVA3', +-ctx_dma: +-ctx_dma_query: .b32 0 +-ctx_dma_src: .b32 0 +-ctx_dma_dst: .b32 0 +-,) +-.equ #ctx_dma_count 3 +-ctx_query_address_high: .b32 0 +-ctx_query_address_low: .b32 0 +-ctx_query_counter: .b32 0 +-ctx_src_address_high: .b32 0 +-ctx_src_address_low: .b32 0 +-ctx_src_pitch: .b32 0 +-ctx_src_tile_mode: .b32 0 +-ctx_src_xsize: .b32 0 +-ctx_src_ysize: .b32 0 +-ctx_src_zsize: .b32 0 +-ctx_src_zoff: .b32 0 +-ctx_src_xoff: .b32 0 +-ctx_src_yoff: .b32 0 +-ctx_src_cpp: .b32 0 +-ctx_dst_address_high: .b32 0 +-ctx_dst_address_low: .b32 0 +-ctx_dst_pitch: .b32 0 +-ctx_dst_tile_mode: .b32 0 +-ctx_dst_xsize: .b32 0 +-ctx_dst_ysize: .b32 0 +-ctx_dst_zsize: .b32 0 +-ctx_dst_zoff: .b32 0 +-ctx_dst_xoff: .b32 0 +-ctx_dst_yoff: .b32 0 +-ctx_dst_cpp: .b32 0 +-ctx_format: .b32 0 +-ctx_swz_const0: .b32 0 +-ctx_swz_const1: .b32 0 +-ctx_xcnt: .b32 0 +-ctx_ycnt: .b32 0 +-.align 256 +- +-dispatch_table: +-// mthd 0x0000, NAME +-.b16 0x000 1 +-.b32 #ctx_object ~0xffffffff +-// mthd 0x0100, NOP +-.b16 0x040 1 +-.b32 0x00010000 + #cmd_nop ~0xffffffff +-// mthd 0x0140, PM_TRIGGER +-.b16 0x050 1 +-.b32 0x00010000 + #cmd_pm_trigger ~0xffffffff +-ifdef(`NVA3', ` +-// mthd 0x0180-0x018c, DMA_ +-.b16 0x060 #ctx_dma_count +-dispatch_dma: +-.b32 0x00010000 + #cmd_dma ~0xffffffff +-.b32 0x00010000 + #cmd_dma ~0xffffffff +-.b32 0x00010000 + #cmd_dma ~0xffffffff +-',) +-// mthd 0x0200-0x0218, SRC_TILE +-.b16 0x80 7 +-.b32 #ctx_src_tile_mode ~0x00000fff +-.b32 #ctx_src_xsize ~0x0007ffff +-.b32 #ctx_src_ysize ~0x00001fff +-.b32 #ctx_src_zsize ~0x000007ff +-.b32 #ctx_src_zoff ~0x00000fff +-.b32 #ctx_src_xoff ~0x0007ffff +-.b32 #ctx_src_yoff ~0x00001fff +-// mthd 0x0220-0x0238, DST_TILE +-.b16 0x88 7 +-.b32 #ctx_dst_tile_mode ~0x00000fff +-.b32 #ctx_dst_xsize ~0x0007ffff +-.b32 #ctx_dst_ysize ~0x00001fff +-.b32 #ctx_dst_zsize ~0x000007ff +-.b32 #ctx_dst_zoff ~0x00000fff +-.b32 #ctx_dst_xoff ~0x0007ffff +-.b32 #ctx_dst_yoff ~0x00001fff +-// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH +-.b16 0xc0 2 +-.b32 0x00010000 + #cmd_exec ~0xffffffff +-.b32 0x00010000 + #cmd_wrcache_flush ~0xffffffff +-// mthd 0x030c-0x0340, various stuff +-.b16 0xc3 14 +-.b32 #ctx_src_address_high ~0x000000ff +-.b32 #ctx_src_address_low ~0xffffffff +-.b32 #ctx_dst_address_high ~0x000000ff +-.b32 #ctx_dst_address_low ~0xffffffff +-.b32 #ctx_src_pitch ~0x0007ffff +-.b32 #ctx_dst_pitch ~0x0007ffff +-.b32 #ctx_xcnt ~0x0000ffff +-.b32 #ctx_ycnt ~0x00001fff +-.b32 #ctx_format ~0x0333ffff +-.b32 #ctx_swz_const0 ~0xffffffff +-.b32 #ctx_swz_const1 ~0xffffffff +-.b32 #ctx_query_address_high ~0x000000ff +-.b32 #ctx_query_address_low ~0xffffffff +-.b32 #ctx_query_counter ~0xffffffff +-.b16 0x800 0 +- +-ifdef(`NVA3', +-.section #nva3_pcopy_code +-, +-.section #nvc0_pcopy_code +-) +- +-main: +- clear b32 $r0 +- mov $sp $r0 +- +- // setup i0 handler and route fifo and ctxswitch to it +- mov $r1 #ih +- mov $iv0 $r1 +- mov $r1 0x400 +- movw $r2 0xfff3 +- sethi $r2 0 +- iowr I[$r1 + 0x300] $r2 +- +- // enable interrupts +- or $r2 0xc +- iowr I[$r1] $r2 +- bset $flags ie0 +- +- // enable fifo access and context switching +- mov $r1 0x1200 +- mov $r2 3 +- iowr I[$r1] $r2 +- +- // sleep forever, waking for interrupts +- bset $flags $p0 +- spin: +- sleep $p0 +- bra #spin +- +-// i0 handler +-ih: +- iord $r1 I[$r0 + 0x200] +- +- and $r2 $r1 0x00000008 +- bra e #ih_no_chsw +- call #chsw +- ih_no_chsw: +- and $r2 $r1 0x00000004 +- bra e #ih_no_cmd +- call #dispatch +- +- ih_no_cmd: +- and $r1 $r1 0x0000000c +- iowr I[$r0 + 0x100] $r1 +- iret +- +-// $p1 direction (0 = unload, 1 = load) +-// $r3 channel +-swctx: +- mov $r4 0x7700 +- mov $xtargets $r4 +-ifdef(`NVA3', ` +- // target 7 hardcoded to ctx dma object +- mov $xdbase $r0 +-', ` // NVC0 +- // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1 +- mov $r4 0x2100 +- iord $r4 I[$r4 + 0] +- and $r4 1 +- shl b32 $r4 4 +- add b32 $r4 0x30 +- +- // channel is in vram +- mov $r15 0x61c +- shl b32 $r15 6 +- mov $r5 0x114 +- iowrs I[$r15] $r5 +- +- // read 16-byte PCOPYn info, containing context pointer, from channel +- shl b32 $r5 $r3 4 +- add b32 $r5 2 +- mov $xdbase $r5 +- mov $r5 $sp +- // get a chunk of stack space, aligned to 256 byte boundary +- sub b32 $r5 0x100 +- mov $r6 0xff +- not b32 $r6 +- and $r5 $r6 +- sethi $r5 0x00020000 +- xdld $r4 $r5 +- xdwait +- sethi $r5 0 +- +- // set context pointer, from within channel VM +- mov $r14 0 +- iowrs I[$r15] $r14 +- ld b32 $r4 D[$r5 + 0] +- shr b32 $r4 8 +- ld b32 $r6 D[$r5 + 4] +- shl b32 $r6 24 +- or $r4 $r6 +- mov $xdbase $r4 +-') +- // 256-byte context, at start of data segment +- mov b32 $r4 $r0 +- sethi $r4 0x60000 +- +- // swap! +- bra $p1 #swctx_load +- xdst $r0 $r4 +- bra #swctx_done +- swctx_load: +- xdld $r0 $r4 +- swctx_done: +- xdwait +- ret +- +-chsw: +- // read current channel +- mov $r2 0x1400 +- iord $r3 I[$r2] +- +- // if it's active, unload it and return +- xbit $r15 $r3 0x1e +- bra e #chsw_no_unload +- bclr $flags $p1 +- call #swctx +- bclr $r3 0x1e +- iowr I[$r2] $r3 +- mov $r4 1 +- iowr I[$r2 + 0x200] $r4 +- ret +- +- // read next channel +- chsw_no_unload: +- iord $r3 I[$r2 + 0x100] +- +- // is there a channel waiting to be loaded? +- xbit $r13 $r3 0x1e +- bra e #chsw_finish_load +- bset $flags $p1 +- call #swctx +-ifdef(`NVA3', +- // load dma objects back into TARGET regs +- mov $r5 #ctx_dma +- mov $r6 #ctx_dma_count +- chsw_load_ctx_dma: +- ld b32 $r7 D[$r5 + $r6 * 4] +- add b32 $r8 $r6 0x180 +- shl b32 $r8 8 +- iowr I[$r8] $r7 +- sub b32 $r6 1 +- bra nc #chsw_load_ctx_dma +-,) +- +- chsw_finish_load: +- mov $r3 2 +- iowr I[$r2 + 0x200] $r3 +- ret +- +-dispatch: +- // read incoming fifo command +- mov $r3 0x1900 +- iord $r2 I[$r3 + 0x100] +- iord $r3 I[$r3 + 0x000] +- and $r4 $r2 0x7ff +- // $r2 will be used to store exception data +- shl b32 $r2 0x10 +- +- // lookup method in the dispatch table, ILLEGAL_MTHD if not found +- mov $r5 #dispatch_table +- clear b32 $r6 +- clear b32 $r7 +- dispatch_loop: +- ld b16 $r6 D[$r5 + 0] +- ld b16 $r7 D[$r5 + 2] +- add b32 $r5 4 +- cmpu b32 $r4 $r6 +- bra c #dispatch_illegal_mthd +- add b32 $r7 $r6 +- cmpu b32 $r4 $r7 +- bra c #dispatch_valid_mthd +- sub b32 $r7 $r6 +- shl b32 $r7 3 +- add b32 $r5 $r7 +- bra #dispatch_loop +- +- // ensure no bits set in reserved fields, INVALID_BITFIELD +- dispatch_valid_mthd: +- sub b32 $r4 $r6 +- shl b32 $r4 3 +- add b32 $r4 $r5 +- ld b32 $r5 D[$r4 + 4] +- and $r5 $r3 +- cmpu b32 $r5 0 +- bra ne #dispatch_invalid_bitfield +- +- // depending on dispatch flags: execute method, or save data as state +- ld b16 $r5 D[$r4 + 0] +- ld b16 $r6 D[$r4 + 2] +- cmpu b32 $r6 0 +- bra ne #dispatch_cmd +- st b32 D[$r5] $r3 +- bra #dispatch_done +- dispatch_cmd: +- bclr $flags $p1 +- call $r5 +- bra $p1 #dispatch_error +- bra #dispatch_done +- +- dispatch_invalid_bitfield: +- or $r2 2 +- dispatch_illegal_mthd: +- or $r2 1 +- +- // store exception data in SCRATCH0/SCRATCH1, signal hostirq +- dispatch_error: +- mov $r4 0x1000 +- iowr I[$r4 + 0x000] $r2 +- iowr I[$r4 + 0x100] $r3 +- mov $r2 0x40 +- iowr I[$r0] $r2 +- hostirq_wait: +- iord $r2 I[$r0 + 0x200] +- and $r2 0x40 +- cmpu b32 $r2 0 +- bra ne #hostirq_wait +- +- dispatch_done: +- mov $r2 0x1d00 +- mov $r3 1 +- iowr I[$r2] $r3 +- ret +- +-// No-operation +-// +-// Inputs: +-// $r1: irqh state +-// $r2: hostirq state +-// $r3: data +-// $r4: dispatch table entry +-// Outputs: +-// $r1: irqh state +-// $p1: set on error +-// $r2: hostirq state +-// $r3: data +-cmd_nop: +- ret +- +-// PM_TRIGGER +-// +-// Inputs: +-// $r1: irqh state +-// $r2: hostirq state +-// $r3: data +-// $r4: dispatch table entry +-// Outputs: +-// $r1: irqh state +-// $p1: set on error +-// $r2: hostirq state +-// $r3: data +-cmd_pm_trigger: +- mov $r2 0x2200 +- clear b32 $r3 +- sethi $r3 0x20000 +- iowr I[$r2] $r3 +- ret +- +-ifdef(`NVA3', +-// SET_DMA_* method handler +-// +-// Inputs: +-// $r1: irqh state +-// $r2: hostirq state +-// $r3: data +-// $r4: dispatch table entry +-// Outputs: +-// $r1: irqh state +-// $p1: set on error +-// $r2: hostirq state +-// $r3: data +-cmd_dma: +- sub b32 $r4 #dispatch_dma +- shr b32 $r4 1 +- bset $r3 0x1e +- st b32 D[$r4 + #ctx_dma] $r3 +- add b32 $r4 0x600 +- shl b32 $r4 6 +- iowr I[$r4] $r3 +- ret +-,) +- +-// Calculates the hw swizzle mask and adjusts the surface's xcnt to match +-// +-cmd_exec_set_format: +- // zero out a chunk of the stack to store the swizzle into +- add $sp -0x10 +- st b32 D[$sp + 0x00] $r0 +- st b32 D[$sp + 0x04] $r0 +- st b32 D[$sp + 0x08] $r0 +- st b32 D[$sp + 0x0c] $r0 +- +- // extract cpp, src_ncomp and dst_ncomp from FORMAT +- ld b32 $r4 D[$r0 + #ctx_format] +- extr $r5 $r4 16:17 +- add b32 $r5 1 +- extr $r6 $r4 20:21 +- add b32 $r6 1 +- extr $r7 $r4 24:25 +- add b32 $r7 1 +- +- // convert FORMAT swizzle mask to hw swizzle mask +- bclr $flags $p2 +- clear b32 $r8 +- clear b32 $r9 +- ncomp_loop: +- and $r10 $r4 0xf +- shr b32 $r4 4 +- clear b32 $r11 +- bpc_loop: +- cmpu b8 $r10 4 +- bra nc #cmp_c0 +- mulu $r12 $r10 $r5 +- add b32 $r12 $r11 +- bset $flags $p2 +- bra #bpc_next +- cmp_c0: +- bra ne #cmp_c1 +- mov $r12 0x10 +- add b32 $r12 $r11 +- bra #bpc_next +- cmp_c1: +- cmpu b8 $r10 6 +- bra nc #cmp_zero +- mov $r12 0x14 +- add b32 $r12 $r11 +- bra #bpc_next +- cmp_zero: +- mov $r12 0x80 +- bpc_next: +- st b8 D[$sp + $r8] $r12 +- add b32 $r8 1 +- add b32 $r11 1 +- cmpu b32 $r11 $r5 +- bra c #bpc_loop +- add b32 $r9 1 +- cmpu b32 $r9 $r7 +- bra c #ncomp_loop +- +- // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang) +- mulu $r6 $r5 +- st b32 D[$r0 + #ctx_src_cpp] $r6 +- ld b32 $r8 D[$r0 + #ctx_xcnt] +- mulu $r6 $r8 +- bra $p2 #dst_xcnt +- clear b32 $r6 +- +- dst_xcnt: +- mulu $r7 $r5 +- st b32 D[$r0 + #ctx_dst_cpp] $r7 +- mulu $r7 $r8 +- +- mov $r5 0x810 +- shl b32 $r5 6 +- iowr I[$r5 + 0x000] $r6 +- iowr I[$r5 + 0x100] $r7 +- add b32 $r5 0x800 +- ld b32 $r6 D[$r0 + #ctx_dst_cpp] +- sub b32 $r6 1 +- shl b32 $r6 8 +- ld b32 $r7 D[$r0 + #ctx_src_cpp] +- sub b32 $r7 1 +- or $r6 $r7 +- iowr I[$r5 + 0x000] $r6 +- add b32 $r5 0x100 +- ld b32 $r6 D[$sp + 0x00] +- iowr I[$r5 + 0x000] $r6 +- ld b32 $r6 D[$sp + 0x04] +- iowr I[$r5 + 0x100] $r6 +- ld b32 $r6 D[$sp + 0x08] +- iowr I[$r5 + 0x200] $r6 +- ld b32 $r6 D[$sp + 0x0c] +- iowr I[$r5 + 0x300] $r6 +- add b32 $r5 0x400 +- ld b32 $r6 D[$r0 + #ctx_swz_const0] +- iowr I[$r5 + 0x000] $r6 +- ld b32 $r6 D[$r0 + #ctx_swz_const1] +- iowr I[$r5 + 0x100] $r6 +- add $sp 0x10 +- ret +- +-// Setup to handle a tiled surface +-// +-// Calculates a number of parameters the hardware requires in order +-// to correctly handle tiling. +-// +-// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE): +-// nTx = round_up(w * cpp, 1 << Tp) >> Tp +-// nTy = round_up(h, 1 << Th) >> Th +-// Txo = (x * cpp) & ((1 << Tp) - 1) +-// Tx = (x * cpp) >> Tp +-// Tyo = y & ((1 << Th) - 1) +-// Ty = y >> Th +-// Tzo = z & ((1 << Td) - 1) +-// Tz = z >> Td +-// +-// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo +-// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp; +-// +-// Inputs: +-// $r4: hw command (0x104800) +-// $r5: ctx offset adjustment for src/dst selection +-// $p2: set if dst surface +-// +-cmd_exec_set_surface_tiled: +- // translate TILE_MODE into Tp, Th, Td shift values +- ld b32 $r7 D[$r5 + #ctx_src_tile_mode] +- extr $r9 $r7 8:11 +- extr $r8 $r7 4:7 +-ifdef(`NVA3', +- add b32 $r8 2 +-, +- add b32 $r8 3 +-) +- extr $r7 $r7 0:3 +- cmp b32 $r7 0xe +- bra ne #xtile64 +- mov $r7 4 +- bra #xtileok +- xtile64: +- xbit $r7 $flags $p2 +- add b32 $r7 17 +- bset $r4 $r7 +- mov $r7 6 +- xtileok: +- +- // Op = (x * cpp) & ((1 << Tp) - 1) +- // Tx = (x * cpp) >> Tp +- ld b32 $r10 D[$r5 + #ctx_src_xoff] +- ld b32 $r11 D[$r5 + #ctx_src_cpp] +- mulu $r10 $r11 +- mov $r11 1 +- shl b32 $r11 $r7 +- sub b32 $r11 1 +- and $r12 $r10 $r11 +- shr b32 $r10 $r7 +- +- // Tyo = y & ((1 << Th) - 1) +- // Ty = y >> Th +- ld b32 $r13 D[$r5 + #ctx_src_yoff] +- mov $r14 1 +- shl b32 $r14 $r8 +- sub b32 $r14 1 +- and $r11 $r13 $r14 +- shr b32 $r13 $r8 +- +- // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo) +- add b32 $r14 1 +- shl b32 $r15 $r14 12 +- sub b32 $r14 $r11 +- or $r15 $r14 +- xbit $r6 $flags $p2 +- add b32 $r6 0x208 +- shl b32 $r6 8 +- iowr I[$r6 + 0x000] $r15 +- +- // Op += Tyo << Tp +- shl b32 $r11 $r7 +- add b32 $r12 $r11 +- +- // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp) +- ld b32 $r15 D[$r5 + #ctx_src_xsize] +- ld b32 $r11 D[$r5 + #ctx_src_cpp] +- mulu $r15 $r11 +- mov $r11 1 +- shl b32 $r11 $r7 +- sub b32 $r11 1 +- add b32 $r15 $r11 +- shr b32 $r15 $r7 +- push $r15 +- +- // nTy = (h + ((1 << Th) - 1)) >> Th +- ld b32 $r15 D[$r5 + #ctx_src_ysize] +- mov $r11 1 +- shl b32 $r11 $r8 +- sub b32 $r11 1 +- add b32 $r15 $r11 +- shr b32 $r15 $r8 +- push $r15 +- +- // Tys = Tp + Th +- // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td +- add b32 $r7 $r8 +- sub b32 $r8 2 +- mov $r11 1 +- shl b32 $r11 $r8 +- shl b32 $r11 $r9 +- +- // Tzo = z & ((1 << Td) - 1) +- // Tz = z >> Td +- // Op += Tzo << Tys +- // Ts = Tys + Td +- ld b32 $r8 D[$r5 + #ctx_src_zoff] +- mov $r14 1 +- shl b32 $r14 $r9 +- sub b32 $r14 1 +- and $r15 $r8 $r14 +- shl b32 $r15 $r7 +- add b32 $r12 $r15 +- add b32 $r7 $r9 +- shr b32 $r8 $r9 +- +- // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts +- pop $r15 +- pop $r9 +- mulu $r13 $r9 +- add b32 $r10 $r13 +- mulu $r8 $r9 +- mulu $r8 $r15 +- add b32 $r10 $r8 +- shl b32 $r10 $r7 +- +- // PITCH = (nTx - 1) << Ts +- sub b32 $r9 1 +- shl b32 $r9 $r7 +- iowr I[$r6 + 0x200] $r9 +- +- // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff +- // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16 +- ld b32 $r7 D[$r5 + #ctx_src_address_low] +- ld b32 $r8 D[$r5 + #ctx_src_address_high] +- add b32 $r10 $r12 +- add b32 $r7 $r10 +- adc b32 $r8 0 +- shl b32 $r8 16 +- or $r8 $r11 +- sub b32 $r6 0x600 +- iowr I[$r6 + 0x000] $r7 +- add b32 $r6 0x400 +- iowr I[$r6 + 0x000] $r8 +- ret +- +-// Setup to handle a linear surface +-// +-// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting +-// +-cmd_exec_set_surface_linear: +- xbit $r6 $flags $p2 +- add b32 $r6 0x202 +- shl b32 $r6 8 +- ld b32 $r7 D[$r5 + #ctx_src_address_low] +- iowr I[$r6 + 0x000] $r7 +- add b32 $r6 0x400 +- ld b32 $r7 D[$r5 + #ctx_src_address_high] +- shl b32 $r7 16 +- iowr I[$r6 + 0x000] $r7 +- add b32 $r6 0x400 +- ld b32 $r7 D[$r5 + #ctx_src_pitch] +- iowr I[$r6 + 0x000] $r7 +- ret +- +-// wait for regs to be available for use +-cmd_exec_wait: +- push $r0 +- push $r1 +- mov $r0 0x800 +- shl b32 $r0 6 +- loop: +- iord $r1 I[$r0] +- and $r1 1 +- bra ne #loop +- pop $r1 +- pop $r0 +- ret +- +-cmd_exec_query: +- // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI } +- xbit $r4 $r3 13 +- bra ne #query_counter +- call #cmd_exec_wait +- mov $r4 0x80c +- shl b32 $r4 6 +- ld b32 $r5 D[$r0 + #ctx_query_address_low] +- add b32 $r5 4 +- iowr I[$r4 + 0x000] $r5 +- iowr I[$r4 + 0x100] $r0 +- mov $r5 0xc +- iowr I[$r4 + 0x200] $r5 +- add b32 $r4 0x400 +- ld b32 $r5 D[$r0 + #ctx_query_address_high] +- shl b32 $r5 16 +- iowr I[$r4 + 0x000] $r5 +- add b32 $r4 0x500 +- mov $r5 0x00000b00 +- sethi $r5 0x00010000 +- iowr I[$r4 + 0x000] $r5 +- mov $r5 0x00004040 +- shl b32 $r5 1 +- sethi $r5 0x80800000 +- iowr I[$r4 + 0x100] $r5 +- mov $r5 0x00001110 +- sethi $r5 0x13120000 +- iowr I[$r4 + 0x200] $r5 +- mov $r5 0x00001514 +- sethi $r5 0x17160000 +- iowr I[$r4 + 0x300] $r5 +- mov $r5 0x00002601 +- sethi $r5 0x00010000 +- mov $r4 0x800 +- shl b32 $r4 6 +- iowr I[$r4 + 0x000] $r5 +- +- // write COUNTER +- query_counter: +- call #cmd_exec_wait +- mov $r4 0x80c +- shl b32 $r4 6 +- ld b32 $r5 D[$r0 + #ctx_query_address_low] +- iowr I[$r4 + 0x000] $r5 +- iowr I[$r4 + 0x100] $r0 +- mov $r5 0x4 +- iowr I[$r4 + 0x200] $r5 +- add b32 $r4 0x400 +- ld b32 $r5 D[$r0 + #ctx_query_address_high] +- shl b32 $r5 16 +- iowr I[$r4 + 0x000] $r5 +- add b32 $r4 0x500 +- mov $r5 0x00000300 +- iowr I[$r4 + 0x000] $r5 +- mov $r5 0x00001110 +- sethi $r5 0x13120000 +- iowr I[$r4 + 0x100] $r5 +- ld b32 $r5 D[$r0 + #ctx_query_counter] +- add b32 $r4 0x500 +- iowr I[$r4 + 0x000] $r5 +- mov $r5 0x00002601 +- sethi $r5 0x00010000 +- mov $r4 0x800 +- shl b32 $r4 6 +- iowr I[$r4 + 0x000] $r5 +- ret +- +-// Execute a copy operation +-// +-// Inputs: +-// $r1: irqh state +-// $r2: hostirq state +-// $r3: data +-// 000002000 QUERY_SHORT +-// 000001000 QUERY +-// 000000100 DST_LINEAR +-// 000000010 SRC_LINEAR +-// 000000001 FORMAT +-// $r4: dispatch table entry +-// Outputs: +-// $r1: irqh state +-// $p1: set on error +-// $r2: hostirq state +-// $r3: data +-cmd_exec: +- call #cmd_exec_wait +- +- // if format requested, call function to calculate it, otherwise +- // fill in cpp/xcnt for both surfaces as if (cpp == 1) +- xbit $r15 $r3 0 +- bra e #cmd_exec_no_format +- call #cmd_exec_set_format +- mov $r4 0x200 +- bra #cmd_exec_init_src_surface +- cmd_exec_no_format: +- mov $r6 0x810 +- shl b32 $r6 6 +- mov $r7 1 +- st b32 D[$r0 + #ctx_src_cpp] $r7 +- st b32 D[$r0 + #ctx_dst_cpp] $r7 +- ld b32 $r7 D[$r0 + #ctx_xcnt] +- iowr I[$r6 + 0x000] $r7 +- iowr I[$r6 + 0x100] $r7 +- clear b32 $r4 +- +- cmd_exec_init_src_surface: +- bclr $flags $p2 +- clear b32 $r5 +- xbit $r15 $r3 4 +- bra e #src_tiled +- call #cmd_exec_set_surface_linear +- bra #cmd_exec_init_dst_surface +- src_tiled: +- call #cmd_exec_set_surface_tiled +- bset $r4 7 +- +- cmd_exec_init_dst_surface: +- bset $flags $p2 +- mov $r5 #ctx_dst_address_high - #ctx_src_address_high +- xbit $r15 $r3 8 +- bra e #dst_tiled +- call #cmd_exec_set_surface_linear +- bra #cmd_exec_kick +- dst_tiled: +- call #cmd_exec_set_surface_tiled +- bset $r4 8 +- +- cmd_exec_kick: +- mov $r5 0x800 +- shl b32 $r5 6 +- ld b32 $r6 D[$r0 + #ctx_ycnt] +- iowr I[$r5 + 0x100] $r6 +- mov $r6 0x0041 +- // SRC_TARGET = 1, DST_TARGET = 2 +- sethi $r6 0x44000000 +- or $r4 $r6 +- iowr I[$r5] $r4 +- +- // if requested, queue up a QUERY write after the copy has completed +- xbit $r15 $r3 12 +- bra e #cmd_exec_done +- call #cmd_exec_query +- +- cmd_exec_done: +- ret +- +-// Flush write cache +-// +-// Inputs: +-// $r1: irqh state +-// $r2: hostirq state +-// $r3: data +-// $r4: dispatch table entry +-// Outputs: +-// $r1: irqh state +-// $p1: set on error +-// $r2: hostirq state +-// $r3: data +-cmd_wrcache_flush: +- mov $r2 0x2200 +- clear b32 $r3 +- sethi $r3 0x10000 +- iowr I[$r2] $r3 +- ret +- +-.align 0x100 +diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h +deleted file mode 100644 +index 241b2720..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nva3.fuc.h ++++ /dev/null +@@ -1,620 +0,0 @@ +-uint32_t nva3_pcopy_data[] = { +-/* 0x0000: ctx_object */ +- 0x00000000, +-/* 0x0004: ctx_dma */ +-/* 0x0004: ctx_dma_query */ +- 0x00000000, +-/* 0x0008: ctx_dma_src */ +- 0x00000000, +-/* 0x000c: ctx_dma_dst */ +- 0x00000000, +-/* 0x0010: ctx_query_address_high */ +- 0x00000000, +-/* 0x0014: ctx_query_address_low */ +- 0x00000000, +-/* 0x0018: ctx_query_counter */ +- 0x00000000, +-/* 0x001c: ctx_src_address_high */ +- 0x00000000, +-/* 0x0020: ctx_src_address_low */ +- 0x00000000, +-/* 0x0024: ctx_src_pitch */ +- 0x00000000, +-/* 0x0028: ctx_src_tile_mode */ +- 0x00000000, +-/* 0x002c: ctx_src_xsize */ +- 0x00000000, +-/* 0x0030: ctx_src_ysize */ +- 0x00000000, +-/* 0x0034: ctx_src_zsize */ +- 0x00000000, +-/* 0x0038: ctx_src_zoff */ +- 0x00000000, +-/* 0x003c: ctx_src_xoff */ +- 0x00000000, +-/* 0x0040: ctx_src_yoff */ +- 0x00000000, +-/* 0x0044: ctx_src_cpp */ +- 0x00000000, +-/* 0x0048: ctx_dst_address_high */ +- 0x00000000, +-/* 0x004c: ctx_dst_address_low */ +- 0x00000000, +-/* 0x0050: ctx_dst_pitch */ +- 0x00000000, +-/* 0x0054: ctx_dst_tile_mode */ +- 0x00000000, +-/* 0x0058: ctx_dst_xsize */ +- 0x00000000, +-/* 0x005c: ctx_dst_ysize */ +- 0x00000000, +-/* 0x0060: ctx_dst_zsize */ +- 0x00000000, +-/* 0x0064: ctx_dst_zoff */ +- 0x00000000, +-/* 0x0068: ctx_dst_xoff */ +- 0x00000000, +-/* 0x006c: ctx_dst_yoff */ +- 0x00000000, +-/* 0x0070: ctx_dst_cpp */ +- 0x00000000, +-/* 0x0074: ctx_format */ +- 0x00000000, +-/* 0x0078: ctx_swz_const0 */ +- 0x00000000, +-/* 0x007c: ctx_swz_const1 */ +- 0x00000000, +-/* 0x0080: ctx_xcnt */ +- 0x00000000, +-/* 0x0084: ctx_ycnt */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: dispatch_table */ +- 0x00010000, +- 0x00000000, +- 0x00000000, +- 0x00010040, +- 0x00010160, +- 0x00000000, +- 0x00010050, +- 0x00010162, +- 0x00000000, +- 0x00030060, +-/* 0x0128: dispatch_dma */ +- 0x00010170, +- 0x00000000, +- 0x00010170, +- 0x00000000, +- 0x00010170, +- 0x00000000, +- 0x00070080, +- 0x00000028, +- 0xfffff000, +- 0x0000002c, +- 0xfff80000, +- 0x00000030, +- 0xffffe000, +- 0x00000034, +- 0xfffff800, +- 0x00000038, +- 0xfffff000, +- 0x0000003c, +- 0xfff80000, +- 0x00000040, +- 0xffffe000, +- 0x00070088, +- 0x00000054, +- 0xfffff000, +- 0x00000058, +- 0xfff80000, +- 0x0000005c, +- 0xffffe000, +- 0x00000060, +- 0xfffff800, +- 0x00000064, +- 0xfffff000, +- 0x00000068, +- 0xfff80000, +- 0x0000006c, +- 0xffffe000, +- 0x000200c0, +- 0x00010492, +- 0x00000000, +- 0x0001051b, +- 0x00000000, +- 0x000e00c3, +- 0x0000001c, +- 0xffffff00, +- 0x00000020, +- 0x00000000, +- 0x00000048, +- 0xffffff00, +- 0x0000004c, +- 0x00000000, +- 0x00000024, +- 0xfff80000, +- 0x00000050, +- 0xfff80000, +- 0x00000080, +- 0xffff0000, +- 0x00000084, +- 0xffffe000, +- 0x00000074, +- 0xfccc0000, +- 0x00000078, +- 0x00000000, +- 0x0000007c, +- 0x00000000, +- 0x00000010, +- 0xffffff00, +- 0x00000014, +- 0x00000000, +- 0x00000018, +- 0x00000000, +- 0x00000800, +-}; +- +-uint32_t nva3_pcopy_code[] = { +-/* 0x0000: main */ +- 0x04fe04bd, +- 0x3517f000, +- 0xf10010fe, +- 0xf1040017, +- 0xf0fff327, +- 0x12d00023, +- 0x0c25f0c0, +- 0xf40012d0, +- 0x17f11031, +- 0x27f01200, +- 0x0012d003, +-/* 0x002f: spin */ +- 0xf40031f4, +- 0x0ef40028, +-/* 0x0035: ih */ +- 0x8001cffd, +- 0xf40812c4, +- 0x21f4060b, +-/* 0x0041: ih_no_chsw */ +- 0x0412c472, +- 0xf4060bf4, +-/* 0x004a: ih_no_cmd */ +- 0x11c4c321, +- 0x4001d00c, +-/* 0x0052: swctx */ +- 0x47f101f8, +- 0x4bfe7700, +- 0x0007fe00, +- 0xf00204b9, +- 0x01f40643, +- 0x0604fa09, +-/* 0x006b: swctx_load */ +- 0xfa060ef4, +-/* 0x006e: swctx_done */ +- 0x03f80504, +-/* 0x0072: chsw */ +- 0x27f100f8, +- 0x23cf1400, +- 0x1e3fc800, +- 0xf4170bf4, +- 0x21f40132, +- 0x1e3af052, +- 0xf00023d0, +- 0x24d00147, +-/* 0x0093: chsw_no_unload */ +- 0xcf00f880, +- 0x3dc84023, +- 0x220bf41e, +- 0xf40131f4, +- 0x57f05221, +- 0x0367f004, +-/* 0x00a8: chsw_load_ctx_dma */ +- 0xa07856bc, +- 0xb6018068, +- 0x87d00884, +- 0x0162b600, +-/* 0x00bb: chsw_finish_load */ +- 0xf0f018f4, +- 0x23d00237, +-/* 0x00c3: dispatch */ +- 0xf100f880, +- 0xcf190037, +- 0x33cf4032, +- 0xff24e400, +- 0x1024b607, +- 0x010057f1, +- 0x74bd64bd, +-/* 0x00dc: dispatch_loop */ +- 0x58005658, +- 0x50b60157, +- 0x0446b804, +- 0xbb4d08f4, +- 0x47b80076, +- 0x0f08f404, +- 0xb60276bb, +- 0x57bb0374, +- 0xdf0ef400, +-/* 0x0100: dispatch_valid_mthd */ +- 0xb60246bb, +- 0x45bb0344, +- 0x01459800, +- 0xb00453fd, +- 0x1bf40054, +- 0x00455820, +- 0xb0014658, +- 0x1bf40064, +- 0x00538009, +-/* 0x0127: dispatch_cmd */ +- 0xf4300ef4, +- 0x55f90132, +- 0xf40c01f4, +-/* 0x0132: dispatch_invalid_bitfield */ +- 0x25f0250e, +-/* 0x0135: dispatch_illegal_mthd */ +- 0x0125f002, +-/* 0x0138: dispatch_error */ +- 0x100047f1, +- 0xd00042d0, +- 0x27f04043, +- 0x0002d040, +-/* 0x0148: hostirq_wait */ +- 0xf08002cf, +- 0x24b04024, +- 0xf71bf400, +-/* 0x0154: dispatch_done */ +- 0x1d0027f1, +- 0xd00137f0, +- 0x00f80023, +-/* 0x0160: cmd_nop */ +-/* 0x0162: cmd_pm_trigger */ +- 0x27f100f8, +- 0x34bd2200, +- 0xd00233f0, +- 0x00f80023, +-/* 0x0170: cmd_dma */ +- 0x012842b7, +- 0xf00145b6, +- 0x43801e39, +- 0x0040b701, +- 0x0644b606, +- 0xf80043d0, +-/* 0x0189: cmd_exec_set_format */ +- 0xf030f400, +- 0xb00001b0, +- 0x01b00101, +- 0x0301b002, +- 0xc71d0498, +- 0x50b63045, +- 0x3446c701, +- 0xc70160b6, +- 0x70b63847, +- 0x0232f401, +- 0x94bd84bd, +-/* 0x01b4: ncomp_loop */ +- 0xb60f4ac4, +- 0xb4bd0445, +-/* 0x01bc: bpc_loop */ +- 0xf404a430, +- 0xa5ff0f18, +- 0x00cbbbc0, +- 0xf40231f4, +-/* 0x01ce: cmp_c0 */ +- 0x1bf4220e, +- 0x10c7f00c, +- 0xf400cbbb, +-/* 0x01da: cmp_c1 */ +- 0xa430160e, +- 0x0c18f406, +- 0xbb14c7f0, +- 0x0ef400cb, +-/* 0x01e9: cmp_zero */ +- 0x80c7f107, +-/* 0x01ed: bpc_next */ +- 0x01c83800, +- 0xb60180b6, +- 0xb5b801b0, +- 0xc308f404, +- 0xb80190b6, +- 0x08f40497, +- 0x0065fdb2, +- 0x98110680, +- 0x68fd2008, +- 0x0502f400, +-/* 0x0216: dst_xcnt */ +- 0x75fd64bd, +- 0x1c078000, +- 0xf10078fd, +- 0xb6081057, +- 0x56d00654, +- 0x4057d000, +- 0x080050b7, +- 0xb61c0698, +- 0x64b60162, +- 0x11079808, +- 0xfd0172b6, +- 0x56d00567, +- 0x0050b700, +- 0x0060b401, +- 0xb40056d0, +- 0x56d00160, +- 0x0260b440, +- 0xb48056d0, +- 0x56d00360, +- 0x0050b7c0, +- 0x1e069804, +- 0x980056d0, +- 0x56d01f06, +- 0x1030f440, +-/* 0x0276: cmd_exec_set_surface_tiled */ +- 0x579800f8, +- 0x6879c70a, +- 0xb66478c7, +- 0x77c70280, +- 0x0e76b060, +- 0xf0091bf4, +- 0x0ef40477, +-/* 0x0291: xtile64 */ +- 0x027cf00f, +- 0xfd1170b6, +- 0x77f00947, +-/* 0x029d: xtileok */ +- 0x0f5a9806, +- 0xfd115b98, +- 0xb7f000ab, +- 0x04b7bb01, +- 0xff01b2b6, +- 0xa7bbc4ab, +- 0x105d9805, +- 0xbb01e7f0, +- 0xe2b604e8, +- 0xb4deff01, +- 0xb605d8bb, +- 0xef9401e0, +- 0x02ebbb0c, +- 0xf005fefd, +- 0x60b7026c, +- 0x64b60208, +- 0x006fd008, +- 0xbb04b7bb, +- 0x5f9800cb, +- 0x115b980b, +- 0xf000fbfd, +- 0xb7bb01b7, +- 0x01b2b604, +- 0xbb00fbbb, +- 0xf0f905f7, +- 0xf00c5f98, +- 0xb8bb01b7, +- 0x01b2b604, +- 0xbb00fbbb, +- 0xf0f905f8, +- 0xb60078bb, +- 0xb7f00282, +- 0x04b8bb01, +- 0x9804b9bb, +- 0xe7f00e58, +- 0x04e9bb01, +- 0xff01e2b6, +- 0xf7bbf48e, +- 0x00cfbb04, +- 0xbb0079bb, +- 0xf0fc0589, +- 0xd9fd90fc, +- 0x00adbb00, +- 0xfd0089fd, +- 0xa8bb008f, +- 0x04a7bb00, +- 0xbb0192b6, +- 0x69d00497, +- 0x08579880, +- 0xbb075898, +- 0x7abb00ac, +- 0x0081b600, +- 0xfd1084b6, +- 0x62b7058b, +- 0x67d00600, +- 0x0060b700, +- 0x0068d004, +-/* 0x0382: cmd_exec_set_surface_linear */ +- 0x6cf000f8, +- 0x0260b702, +- 0x0864b602, +- 0xd0085798, +- 0x60b70067, +- 0x57980400, +- 0x1074b607, +- 0xb70067d0, +- 0x98040060, +- 0x67d00957, +-/* 0x03ab: cmd_exec_wait */ +- 0xf900f800, +- 0xf110f900, +- 0xb6080007, +-/* 0x03b6: loop */ +- 0x01cf0604, +- 0x0114f000, +- 0xfcfa1bf4, +- 0xf800fc10, +-/* 0x03c5: cmd_exec_query */ +- 0x0d34c800, +- 0xf5701bf4, +- 0xf103ab21, +- 0xb6080c47, +- 0x05980644, +- 0x0450b605, +- 0xd00045d0, +- 0x57f04040, +- 0x8045d00c, +- 0x040040b7, +- 0xb6040598, +- 0x45d01054, +- 0x0040b700, +- 0x0057f105, +- 0x0153f00b, +- 0xf10045d0, +- 0xb6404057, +- 0x53f10154, +- 0x45d08080, +- 0x1057f140, +- 0x1253f111, +- 0x8045d013, +- 0x151457f1, +- 0x171653f1, +- 0xf1c045d0, +- 0xf0260157, +- 0x47f10153, +- 0x44b60800, +- 0x0045d006, +-/* 0x0438: query_counter */ +- 0x03ab21f5, +- 0x080c47f1, +- 0x980644b6, +- 0x45d00505, +- 0x4040d000, +- 0xd00457f0, +- 0x40b78045, +- 0x05980400, +- 0x1054b604, +- 0xb70045d0, +- 0xf1050040, +- 0xd0030057, +- 0x57f10045, +- 0x53f11110, +- 0x45d01312, +- 0x06059840, +- 0x050040b7, +- 0xf10045d0, +- 0xf0260157, +- 0x47f10153, +- 0x44b60800, +- 0x0045d006, +-/* 0x0492: cmd_exec */ +- 0x21f500f8, +- 0x3fc803ab, +- 0x0e0bf400, +- 0x018921f5, +- 0x020047f1, +-/* 0x04a7: cmd_exec_no_format */ +- 0xf11e0ef4, +- 0xb6081067, +- 0x77f00664, +- 0x11078001, +- 0x981c0780, +- 0x67d02007, +- 0x4067d000, +-/* 0x04c2: cmd_exec_init_src_surface */ +- 0x32f444bd, +- 0xc854bd02, +- 0x0bf4043f, +- 0x8221f50a, +- 0x0a0ef403, +-/* 0x04d4: src_tiled */ +- 0x027621f5, +-/* 0x04db: cmd_exec_init_dst_surface */ +- 0xf40749f0, +- 0x57f00231, +- 0x083fc82c, +- 0xf50a0bf4, +- 0xf4038221, +-/* 0x04ee: dst_tiled */ +- 0x21f50a0e, +- 0x49f00276, +-/* 0x04f5: cmd_exec_kick */ +- 0x0057f108, +- 0x0654b608, +- 0xd0210698, +- 0x67f04056, +- 0x0063f141, +- 0x0546fd44, +- 0xc80054d0, +- 0x0bf40c3f, +- 0xc521f507, +-/* 0x0519: cmd_exec_done */ +-/* 0x051b: cmd_wrcache_flush */ +- 0xf100f803, +- 0xbd220027, +- 0x0133f034, +- 0xf80023d0, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h +deleted file mode 100644 +index 98cc4216..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/copy/fuc/nvc0.fuc.h ++++ /dev/null +@@ -1,606 +0,0 @@ +-uint32_t nvc0_pcopy_data[] = { +-/* 0x0000: ctx_object */ +- 0x00000000, +-/* 0x0004: ctx_query_address_high */ +- 0x00000000, +-/* 0x0008: ctx_query_address_low */ +- 0x00000000, +-/* 0x000c: ctx_query_counter */ +- 0x00000000, +-/* 0x0010: ctx_src_address_high */ +- 0x00000000, +-/* 0x0014: ctx_src_address_low */ +- 0x00000000, +-/* 0x0018: ctx_src_pitch */ +- 0x00000000, +-/* 0x001c: ctx_src_tile_mode */ +- 0x00000000, +-/* 0x0020: ctx_src_xsize */ +- 0x00000000, +-/* 0x0024: ctx_src_ysize */ +- 0x00000000, +-/* 0x0028: ctx_src_zsize */ +- 0x00000000, +-/* 0x002c: ctx_src_zoff */ +- 0x00000000, +-/* 0x0030: ctx_src_xoff */ +- 0x00000000, +-/* 0x0034: ctx_src_yoff */ +- 0x00000000, +-/* 0x0038: ctx_src_cpp */ +- 0x00000000, +-/* 0x003c: ctx_dst_address_high */ +- 0x00000000, +-/* 0x0040: ctx_dst_address_low */ +- 0x00000000, +-/* 0x0044: ctx_dst_pitch */ +- 0x00000000, +-/* 0x0048: ctx_dst_tile_mode */ +- 0x00000000, +-/* 0x004c: ctx_dst_xsize */ +- 0x00000000, +-/* 0x0050: ctx_dst_ysize */ +- 0x00000000, +-/* 0x0054: ctx_dst_zsize */ +- 0x00000000, +-/* 0x0058: ctx_dst_zoff */ +- 0x00000000, +-/* 0x005c: ctx_dst_xoff */ +- 0x00000000, +-/* 0x0060: ctx_dst_yoff */ +- 0x00000000, +-/* 0x0064: ctx_dst_cpp */ +- 0x00000000, +-/* 0x0068: ctx_format */ +- 0x00000000, +-/* 0x006c: ctx_swz_const0 */ +- 0x00000000, +-/* 0x0070: ctx_swz_const1 */ +- 0x00000000, +-/* 0x0074: ctx_xcnt */ +- 0x00000000, +-/* 0x0078: ctx_ycnt */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: dispatch_table */ +- 0x00010000, +- 0x00000000, +- 0x00000000, +- 0x00010040, +- 0x0001019f, +- 0x00000000, +- 0x00010050, +- 0x000101a1, +- 0x00000000, +- 0x00070080, +- 0x0000001c, +- 0xfffff000, +- 0x00000020, +- 0xfff80000, +- 0x00000024, +- 0xffffe000, +- 0x00000028, +- 0xfffff800, +- 0x0000002c, +- 0xfffff000, +- 0x00000030, +- 0xfff80000, +- 0x00000034, +- 0xffffe000, +- 0x00070088, +- 0x00000048, +- 0xfffff000, +- 0x0000004c, +- 0xfff80000, +- 0x00000050, +- 0xffffe000, +- 0x00000054, +- 0xfffff800, +- 0x00000058, +- 0xfffff000, +- 0x0000005c, +- 0xfff80000, +- 0x00000060, +- 0xffffe000, +- 0x000200c0, +- 0x000104b8, +- 0x00000000, +- 0x00010541, +- 0x00000000, +- 0x000e00c3, +- 0x00000010, +- 0xffffff00, +- 0x00000014, +- 0x00000000, +- 0x0000003c, +- 0xffffff00, +- 0x00000040, +- 0x00000000, +- 0x00000018, +- 0xfff80000, +- 0x00000044, +- 0xfff80000, +- 0x00000074, +- 0xffff0000, +- 0x00000078, +- 0xffffe000, +- 0x00000068, +- 0xfccc0000, +- 0x0000006c, +- 0x00000000, +- 0x00000070, +- 0x00000000, +- 0x00000004, +- 0xffffff00, +- 0x00000008, +- 0x00000000, +- 0x0000000c, +- 0x00000000, +- 0x00000800, +-}; +- +-uint32_t nvc0_pcopy_code[] = { +-/* 0x0000: main */ +- 0x04fe04bd, +- 0x3517f000, +- 0xf10010fe, +- 0xf1040017, +- 0xf0fff327, +- 0x12d00023, +- 0x0c25f0c0, +- 0xf40012d0, +- 0x17f11031, +- 0x27f01200, +- 0x0012d003, +-/* 0x002f: spin */ +- 0xf40031f4, +- 0x0ef40028, +-/* 0x0035: ih */ +- 0x8001cffd, +- 0xf40812c4, +- 0x21f4060b, +-/* 0x0041: ih_no_chsw */ +- 0x0412c4ca, +- 0xf5070bf4, +-/* 0x004b: ih_no_cmd */ +- 0xc4010221, +- 0x01d00c11, +-/* 0x0053: swctx */ +- 0xf101f840, +- 0xfe770047, +- 0x47f1004b, +- 0x44cf2100, +- 0x0144f000, +- 0xb60444b6, +- 0xf7f13040, +- 0xf4b6061c, +- 0x1457f106, +- 0x00f5d101, +- 0xb6043594, +- 0x57fe0250, +- 0x0145fe00, +- 0x010052b7, +- 0x00ff67f1, +- 0x56fd60bd, +- 0x0253f004, +- 0xf80545fa, +- 0x0053f003, +- 0xd100e7f0, +- 0x549800fe, +- 0x0845b600, +- 0xb6015698, +- 0x46fd1864, +- 0x0047fe05, +- 0xf00204b9, +- 0x01f40643, +- 0x0604fa09, +-/* 0x00c3: swctx_load */ +- 0xfa060ef4, +-/* 0x00c6: swctx_done */ +- 0x03f80504, +-/* 0x00ca: chsw */ +- 0x27f100f8, +- 0x23cf1400, +- 0x1e3fc800, +- 0xf4170bf4, +- 0x21f40132, +- 0x1e3af053, +- 0xf00023d0, +- 0x24d00147, +-/* 0x00eb: chsw_no_unload */ +- 0xcf00f880, +- 0x3dc84023, +- 0x090bf41e, +- 0xf40131f4, +-/* 0x00fa: chsw_finish_load */ +- 0x37f05321, +- 0x8023d002, +-/* 0x0102: dispatch */ +- 0x37f100f8, +- 0x32cf1900, +- 0x0033cf40, +- 0x07ff24e4, +- 0xf11024b6, +- 0xbd010057, +-/* 0x011b: dispatch_loop */ +- 0x5874bd64, +- 0x57580056, +- 0x0450b601, +- 0xf40446b8, +- 0x76bb4d08, +- 0x0447b800, +- 0xbb0f08f4, +- 0x74b60276, +- 0x0057bb03, +-/* 0x013f: dispatch_valid_mthd */ +- 0xbbdf0ef4, +- 0x44b60246, +- 0x0045bb03, +- 0xfd014598, +- 0x54b00453, +- 0x201bf400, +- 0x58004558, +- 0x64b00146, +- 0x091bf400, +- 0xf4005380, +-/* 0x0166: dispatch_cmd */ +- 0x32f4300e, +- 0xf455f901, +- 0x0ef40c01, +-/* 0x0171: dispatch_invalid_bitfield */ +- 0x0225f025, +-/* 0x0174: dispatch_illegal_mthd */ +-/* 0x0177: dispatch_error */ +- 0xf10125f0, +- 0xd0100047, +- 0x43d00042, +- 0x4027f040, +-/* 0x0187: hostirq_wait */ +- 0xcf0002d0, +- 0x24f08002, +- 0x0024b040, +-/* 0x0193: dispatch_done */ +- 0xf1f71bf4, +- 0xf01d0027, +- 0x23d00137, +-/* 0x019f: cmd_nop */ +- 0xf800f800, +-/* 0x01a1: cmd_pm_trigger */ +- 0x0027f100, +- 0xf034bd22, +- 0x23d00233, +-/* 0x01af: cmd_exec_set_format */ +- 0xf400f800, +- 0x01b0f030, +- 0x0101b000, +- 0xb00201b0, +- 0x04980301, +- 0x3045c71a, +- 0xc70150b6, +- 0x60b63446, +- 0x3847c701, +- 0xf40170b6, +- 0x84bd0232, +-/* 0x01da: ncomp_loop */ +- 0x4ac494bd, +- 0x0445b60f, +-/* 0x01e2: bpc_loop */ +- 0xa430b4bd, +- 0x0f18f404, +- 0xbbc0a5ff, +- 0x31f400cb, +- 0x220ef402, +-/* 0x01f4: cmp_c0 */ +- 0xf00c1bf4, +- 0xcbbb10c7, +- 0x160ef400, +-/* 0x0200: cmp_c1 */ +- 0xf406a430, +- 0xc7f00c18, +- 0x00cbbb14, +-/* 0x020f: cmp_zero */ +- 0xf1070ef4, +-/* 0x0213: bpc_next */ +- 0x380080c7, +- 0x80b601c8, +- 0x01b0b601, +- 0xf404b5b8, +- 0x90b6c308, +- 0x0497b801, +- 0xfdb208f4, +- 0x06800065, +- 0x1d08980e, +- 0xf40068fd, +- 0x64bd0502, +-/* 0x023c: dst_xcnt */ +- 0x800075fd, +- 0x78fd1907, +- 0x1057f100, +- 0x0654b608, +- 0xd00056d0, +- 0x50b74057, +- 0x06980800, +- 0x0162b619, +- 0x980864b6, +- 0x72b60e07, +- 0x0567fd01, +- 0xb70056d0, +- 0xb4010050, +- 0x56d00060, +- 0x0160b400, +- 0xb44056d0, +- 0x56d00260, +- 0x0360b480, +- 0xb7c056d0, +- 0x98040050, +- 0x56d01b06, +- 0x1c069800, +- 0xf44056d0, +- 0x00f81030, +-/* 0x029c: cmd_exec_set_surface_tiled */ +- 0xc7075798, +- 0x78c76879, +- 0x0380b664, +- 0xb06077c7, +- 0x1bf40e76, +- 0x0477f009, +-/* 0x02b7: xtile64 */ +- 0xf00f0ef4, +- 0x70b6027c, +- 0x0947fd11, +-/* 0x02c3: xtileok */ +- 0x980677f0, +- 0x5b980c5a, +- 0x00abfd0e, +- 0xbb01b7f0, +- 0xb2b604b7, +- 0xc4abff01, +- 0x9805a7bb, +- 0xe7f00d5d, +- 0x04e8bb01, +- 0xff01e2b6, +- 0xd8bbb4de, +- 0x01e0b605, +- 0xbb0cef94, +- 0xfefd02eb, +- 0x026cf005, +- 0x020860b7, +- 0xd00864b6, +- 0xb7bb006f, +- 0x00cbbb04, +- 0x98085f98, +- 0xfbfd0e5b, +- 0x01b7f000, +- 0xb604b7bb, +- 0xfbbb01b2, +- 0x05f7bb00, +- 0x5f98f0f9, +- 0x01b7f009, +- 0xb604b8bb, +- 0xfbbb01b2, +- 0x05f8bb00, +- 0x78bbf0f9, +- 0x0282b600, +- 0xbb01b7f0, +- 0xb9bb04b8, +- 0x0b589804, +- 0xbb01e7f0, +- 0xe2b604e9, +- 0xf48eff01, +- 0xbb04f7bb, +- 0x79bb00cf, +- 0x0589bb00, +- 0x90fcf0fc, +- 0xbb00d9fd, +- 0x89fd00ad, +- 0x008ffd00, +- 0xbb00a8bb, +- 0x92b604a7, +- 0x0497bb01, +- 0x988069d0, +- 0x58980557, +- 0x00acbb04, +- 0xb6007abb, +- 0x84b60081, +- 0x058bfd10, +- 0x060062b7, +- 0xb70067d0, +- 0xd0040060, +- 0x00f80068, +-/* 0x03a8: cmd_exec_set_surface_linear */ +- 0xb7026cf0, +- 0xb6020260, +- 0x57980864, +- 0x0067d005, +- 0x040060b7, +- 0xb6045798, +- 0x67d01074, +- 0x0060b700, +- 0x06579804, +- 0xf80067d0, +-/* 0x03d1: cmd_exec_wait */ +- 0xf900f900, +- 0x0007f110, +- 0x0604b608, +-/* 0x03dc: loop */ +- 0xf00001cf, +- 0x1bf40114, +- 0xfc10fcfa, +-/* 0x03eb: cmd_exec_query */ +- 0xc800f800, +- 0x1bf40d34, +- 0xd121f570, +- 0x0c47f103, +- 0x0644b608, +- 0xb6020598, +- 0x45d00450, +- 0x4040d000, +- 0xd00c57f0, +- 0x40b78045, +- 0x05980400, +- 0x1054b601, +- 0xb70045d0, +- 0xf1050040, +- 0xf00b0057, +- 0x45d00153, +- 0x4057f100, +- 0x0154b640, +- 0x808053f1, +- 0xf14045d0, +- 0xf1111057, +- 0xd0131253, +- 0x57f18045, +- 0x53f11514, +- 0x45d01716, +- 0x0157f1c0, +- 0x0153f026, +- 0x080047f1, +- 0xd00644b6, +-/* 0x045e: query_counter */ +- 0x21f50045, +- 0x47f103d1, +- 0x44b6080c, +- 0x02059806, +- 0xd00045d0, +- 0x57f04040, +- 0x8045d004, +- 0x040040b7, +- 0xb6010598, +- 0x45d01054, +- 0x0040b700, +- 0x0057f105, +- 0x0045d003, +- 0x111057f1, +- 0x131253f1, +- 0x984045d0, +- 0x40b70305, +- 0x45d00500, +- 0x0157f100, +- 0x0153f026, +- 0x080047f1, +- 0xd00644b6, +- 0x00f80045, +-/* 0x04b8: cmd_exec */ +- 0x03d121f5, +- 0xf4003fc8, +- 0x21f50e0b, +- 0x47f101af, +- 0x0ef40200, +-/* 0x04cd: cmd_exec_no_format */ +- 0x1067f11e, +- 0x0664b608, +- 0x800177f0, +- 0x07800e07, +- 0x1d079819, +- 0xd00067d0, +- 0x44bd4067, +-/* 0x04e8: cmd_exec_init_src_surface */ +- 0xbd0232f4, +- 0x043fc854, +- 0xf50a0bf4, +- 0xf403a821, +-/* 0x04fa: src_tiled */ +- 0x21f50a0e, +- 0x49f0029c, +-/* 0x0501: cmd_exec_init_dst_surface */ +- 0x0231f407, +- 0xc82c57f0, +- 0x0bf4083f, +- 0xa821f50a, +- 0x0a0ef403, +-/* 0x0514: dst_tiled */ +- 0x029c21f5, +-/* 0x051b: cmd_exec_kick */ +- 0xf10849f0, +- 0xb6080057, +- 0x06980654, +- 0x4056d01e, +- 0xf14167f0, +- 0xfd440063, +- 0x54d00546, +- 0x0c3fc800, +- 0xf5070bf4, +-/* 0x053f: cmd_exec_done */ +- 0xf803eb21, +-/* 0x0541: cmd_wrcache_flush */ +- 0x0027f100, +- 0xf034bd22, +- 0x23d00133, +- 0x0000f800, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c b/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c +deleted file mode 100644 +index abb410ef..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/copy/nva3.c ++++ /dev/null +@@ -1,156 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +- +- +-#include "fuc/nva3.fuc.h" +- +-struct nva3_copy_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * Copy object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nva3_copy_sclass[] = { +- { 0x85b5, &nouveau_object_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * PCOPY context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nva3_copy_cclass = { +- .handle = NV_ENGCTX(COPY0, 0xa3), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- +- }, +-}; +- +-/******************************************************************************* +- * PCOPY engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_enum nva3_copy_isr_error_name[] = { +- { 0x0001, "ILLEGAL_MTHD" }, +- { 0x0002, "INVALID_ENUM" }, +- { 0x0003, "INVALID_BITFIELD" }, +- {} +-}; +- +-void +-nva3_copy_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_falcon *falcon = (void *)subdev; +- struct nouveau_object *engctx; +- u32 dispatch = nv_ro32(falcon, 0x01c); +- u32 stat = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); +- u64 inst = nv_ro32(falcon, 0x050) & 0x3fffffff; +- u32 ssta = nv_ro32(falcon, 0x040) & 0x0000ffff; +- u32 addr = nv_ro32(falcon, 0x040) >> 16; +- u32 mthd = (addr & 0x07ff) << 2; +- u32 subc = (addr & 0x3800) >> 11; +- u32 data = nv_ro32(falcon, 0x044); +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat & 0x00000040) { +- nv_error(falcon, "DISPATCH_ERROR ["); +- nouveau_enum_print(nva3_copy_isr_error_name, ssta); +- pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", +- chid, inst << 12, nouveau_client_name(engctx), subc, +- mthd, data); +- nv_wo32(falcon, 0x004, 0x00000040); +- stat &= ~0x00000040; +- } +- +- if (stat) { +- nv_error(falcon, "unhandled intr 0x%08x\n", stat); +- nv_wo32(falcon, 0x004, stat); +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static int +-nva3_copy_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- bool enable = (nv_device(parent)->chipset != 0xaf); +- struct nva3_copy_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, enable, +- "PCE0", "copy0", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00802000; +- nv_subdev(priv)->intr = nva3_copy_intr; +- nv_engine(priv)->cclass = &nva3_copy_cclass; +- nv_engine(priv)->sclass = nva3_copy_sclass; +- nv_falcon(priv)->code.data = nva3_pcopy_code; +- nv_falcon(priv)->code.size = sizeof(nva3_pcopy_code); +- nv_falcon(priv)->data.data = nva3_pcopy_data; +- nv_falcon(priv)->data.size = sizeof(nva3_pcopy_data); +- return 0; +-} +- +-struct nouveau_oclass +-nva3_copy_oclass = { +- .handle = NV_ENGINE(COPY0, 0xa3), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva3_copy_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = _nouveau_falcon_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c +deleted file mode 100644 +index 9261694d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/copy/nvc0.c ++++ /dev/null +@@ -1,172 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +- +-#include "fuc/nvc0.fuc.h" +- +-struct nvc0_copy_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * Copy object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_copy0_sclass[] = { +- { 0x90b5, &nouveau_object_ofuncs }, +- {}, +-}; +- +-static struct nouveau_oclass +-nvc0_copy1_sclass[] = { +- { 0x90b8, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PCOPY context +- ******************************************************************************/ +- +-static struct nouveau_ofuncs +-nvc0_copy_context_ofuncs = { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +-}; +- +-static struct nouveau_oclass +-nvc0_copy0_cclass = { +- .handle = NV_ENGCTX(COPY0, 0xc0), +- .ofuncs = &nvc0_copy_context_ofuncs, +-}; +- +-static struct nouveau_oclass +-nvc0_copy1_cclass = { +- .handle = NV_ENGCTX(COPY1, 0xc0), +- .ofuncs = &nvc0_copy_context_ofuncs, +-}; +- +-/******************************************************************************* +- * PCOPY engine/subdev functions +- ******************************************************************************/ +- +-static int +-nvc0_copy_init(struct nouveau_object *object) +-{ +- struct nvc0_copy_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wo32(priv, 0x084, nv_engidx(object) - NVDEV_ENGINE_COPY0); +- return 0; +-} +- +-static int +-nvc0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_copy_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x104000, true, +- "PCE0", "copy0", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000040; +- nv_subdev(priv)->intr = nva3_copy_intr; +- nv_engine(priv)->cclass = &nvc0_copy0_cclass; +- nv_engine(priv)->sclass = nvc0_copy0_sclass; +- nv_falcon(priv)->code.data = nvc0_pcopy_code; +- nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code); +- nv_falcon(priv)->data.data = nvc0_pcopy_data; +- nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data); +- return 0; +-} +- +-static int +-nvc0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_copy_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x105000, true, +- "PCE1", "copy1", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000080; +- nv_subdev(priv)->intr = nva3_copy_intr; +- nv_engine(priv)->cclass = &nvc0_copy1_cclass; +- nv_engine(priv)->sclass = nvc0_copy1_sclass; +- nv_falcon(priv)->code.data = nvc0_pcopy_code; +- nv_falcon(priv)->code.size = sizeof(nvc0_pcopy_code); +- nv_falcon(priv)->data.data = nvc0_pcopy_data; +- nv_falcon(priv)->data.size = sizeof(nvc0_pcopy_data); +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_copy0_oclass = { +- .handle = NV_ENGINE(COPY0, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_copy0_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nvc0_copy_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +- +-struct nouveau_oclass +-nvc0_copy1_oclass = { +- .handle = NV_ENGINE(COPY1, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_copy1_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nvc0_copy_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c b/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c +deleted file mode 100644 +index c7194b35..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/copy/nve0.c ++++ /dev/null +@@ -1,176 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +- +-struct nve0_copy_priv { +- struct nouveau_engine base; +-}; +- +-/******************************************************************************* +- * Copy object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve0_copy_sclass[] = { +- { 0xa0b5, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PCOPY context +- ******************************************************************************/ +- +-static struct nouveau_ofuncs +-nve0_copy_context_ofuncs = { +- .ctor = _nouveau_engctx_ctor, +- .dtor = _nouveau_engctx_dtor, +- .init = _nouveau_engctx_init, +- .fini = _nouveau_engctx_fini, +- .rd32 = _nouveau_engctx_rd32, +- .wr32 = _nouveau_engctx_wr32, +-}; +- +-static struct nouveau_oclass +-nve0_copy_cclass = { +- .handle = NV_ENGCTX(COPY0, 0xc0), +- .ofuncs = &nve0_copy_context_ofuncs, +-}; +- +-/******************************************************************************* +- * PCOPY engine/subdev functions +- ******************************************************************************/ +- +-static void +-nve0_copy_intr(struct nouveau_subdev *subdev) +-{ +- const int ce = nv_subidx(nv_object(subdev)) - NVDEV_ENGINE_COPY0; +- struct nve0_copy_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, 0x104908 + (ce * 0x1000)); +- +- if (stat) { +- nv_warn(priv, "unhandled intr 0x%08x\n", stat); +- nv_wr32(priv, 0x104908 + (ce * 0x1000), stat); +- } +-} +- +-static int +-nve0_copy0_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_copy_priv *priv; +- int ret; +- +- ret = nouveau_engine_create(parent, engine, oclass, true, +- "PCE0", "copy0", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000040; +- nv_subdev(priv)->intr = nve0_copy_intr; +- nv_engine(priv)->cclass = &nve0_copy_cclass; +- nv_engine(priv)->sclass = nve0_copy_sclass; +- return 0; +-} +- +-static int +-nve0_copy1_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_copy_priv *priv; +- int ret; +- +- ret = nouveau_engine_create(parent, engine, oclass, true, +- "PCE1", "copy1", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000080; +- nv_subdev(priv)->intr = nve0_copy_intr; +- nv_engine(priv)->cclass = &nve0_copy_cclass; +- nv_engine(priv)->sclass = nve0_copy_sclass; +- return 0; +-} +- +-static int +-nve0_copy2_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_copy_priv *priv; +- int ret; +- +- ret = nouveau_engine_create(parent, engine, oclass, true, +- "PCE2", "copy2", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00200000; +- nv_subdev(priv)->intr = nve0_copy_intr; +- nv_engine(priv)->cclass = &nve0_copy_cclass; +- nv_engine(priv)->sclass = nve0_copy_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nve0_copy0_oclass = { +- .handle = NV_ENGINE(COPY0, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_copy0_ctor, +- .dtor = _nouveau_engine_dtor, +- .init = _nouveau_engine_init, +- .fini = _nouveau_engine_fini, +- }, +-}; +- +-struct nouveau_oclass +-nve0_copy1_oclass = { +- .handle = NV_ENGINE(COPY1, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_copy1_ctor, +- .dtor = _nouveau_engine_dtor, +- .init = _nouveau_engine_init, +- .fini = _nouveau_engine_fini, +- }, +-}; +- +-struct nouveau_oclass +-nve0_copy2_oclass = { +- .handle = NV_ENGINE(COPY2, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_copy2_ctor, +- .dtor = _nouveau_engine_dtor, +- .init = _nouveau_engine_init, +- .fini = _nouveau_engine_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc +deleted file mode 100644 +index 629da02d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc ++++ /dev/null +@@ -1,698 +0,0 @@ +-/* +- * fuc microcode for nv98 pcrypt engine +- * Copyright (C) 2010 Marcin KoÅ›cielnicki +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +- */ +- +-.section #nv98_pcrypt_data +- +-ctx_dma: +-ctx_dma_query: .b32 0 +-ctx_dma_src: .b32 0 +-ctx_dma_dst: .b32 0 +-.equ #dma_count 3 +-ctx_query_address_high: .b32 0 +-ctx_query_address_low: .b32 0 +-ctx_query_counter: .b32 0 +-ctx_cond_address_high: .b32 0 +-ctx_cond_address_low: .b32 0 +-ctx_cond_off: .b32 0 +-ctx_src_address_high: .b32 0 +-ctx_src_address_low: .b32 0 +-ctx_dst_address_high: .b32 0 +-ctx_dst_address_low: .b32 0 +-ctx_mode: .b32 0 +-.align 16 +-ctx_key: .skip 16 +-ctx_iv: .skip 16 +- +-.align 0x80 +-swap: +-.skip 32 +- +-.align 8 +-common_cmd_dtable: +-.b32 #ctx_query_address_high + 0x20000 ~0xff +-.b32 #ctx_query_address_low + 0x20000 ~0xfffffff0 +-.b32 #ctx_query_counter + 0x20000 ~0xffffffff +-.b32 #cmd_query_get + 0x00000 ~1 +-.b32 #ctx_cond_address_high + 0x20000 ~0xff +-.b32 #ctx_cond_address_low + 0x20000 ~0xfffffff0 +-.b32 #cmd_cond_mode + 0x00000 ~7 +-.b32 #cmd_wrcache_flush + 0x00000 ~0 +-.equ #common_cmd_max 0x88 +- +- +-.align 8 +-engine_cmd_dtable: +-.b32 #ctx_key + 0x0 + 0x20000 ~0xffffffff +-.b32 #ctx_key + 0x4 + 0x20000 ~0xffffffff +-.b32 #ctx_key + 0x8 + 0x20000 ~0xffffffff +-.b32 #ctx_key + 0xc + 0x20000 ~0xffffffff +-.b32 #ctx_iv + 0x0 + 0x20000 ~0xffffffff +-.b32 #ctx_iv + 0x4 + 0x20000 ~0xffffffff +-.b32 #ctx_iv + 0x8 + 0x20000 ~0xffffffff +-.b32 #ctx_iv + 0xc + 0x20000 ~0xffffffff +-.b32 #ctx_src_address_high + 0x20000 ~0xff +-.b32 #ctx_src_address_low + 0x20000 ~0xfffffff0 +-.b32 #ctx_dst_address_high + 0x20000 ~0xff +-.b32 #ctx_dst_address_low + 0x20000 ~0xfffffff0 +-.b32 #crypt_cmd_mode + 0x00000 ~0xf +-.b32 #crypt_cmd_length + 0x10000 ~0x0ffffff0 +-.equ #engine_cmd_max 0xce +- +-.align 4 +-crypt_dtable: +-.b16 #crypt_copy_prep #crypt_do_inout +-.b16 #crypt_store_prep #crypt_do_out +-.b16 #crypt_ecb_e_prep #crypt_do_inout +-.b16 #crypt_ecb_d_prep #crypt_do_inout +-.b16 #crypt_cbc_e_prep #crypt_do_inout +-.b16 #crypt_cbc_d_prep #crypt_do_inout +-.b16 #crypt_pcbc_e_prep #crypt_do_inout +-.b16 #crypt_pcbc_d_prep #crypt_do_inout +-.b16 #crypt_cfb_e_prep #crypt_do_inout +-.b16 #crypt_cfb_d_prep #crypt_do_inout +-.b16 #crypt_ofb_prep #crypt_do_inout +-.b16 #crypt_ctr_prep #crypt_do_inout +-.b16 #crypt_cbc_mac_prep #crypt_do_in +-.b16 #crypt_cmac_finish_complete_prep #crypt_do_in +-.b16 #crypt_cmac_finish_partial_prep #crypt_do_in +- +-.align 0x100 +- +-.section #nv98_pcrypt_code +- +- // $r0 is always set to 0 in our code - this allows some space savings. +- clear b32 $r0 +- +- // set up the interrupt handler +- mov $r1 #ih +- mov $iv0 $r1 +- +- // init stack pointer +- mov $sp $r0 +- +- // set interrupt dispatch - route timer, fifo, ctxswitch to i0, others to host +- movw $r1 0xfff0 +- sethi $r1 0 +- mov $r2 0x400 +- iowr I[$r2 + 0x300] $r1 +- +- // enable the interrupts +- or $r1 0xc +- iowr I[$r2] $r1 +- +- // enable fifo access and context switching +- mov $r1 3 +- mov $r2 0x1200 +- iowr I[$r2] $r1 +- +- // enable i0 delivery +- bset $flags ie0 +- +- // sleep forver, waking only for interrupts. +- bset $flags $p0 +- spin: +- sleep $p0 +- bra #spin +- +-// i0 handler +-ih: +- // see which interrupts we got +- iord $r1 I[$r0 + 0x200] +- +- and $r2 $r1 0x8 +- cmpu b32 $r2 0 +- bra e #noctx +- +- // context switch... prepare the regs for xfer +- mov $r2 0x7700 +- mov $xtargets $r2 +- mov $xdbase $r0 +- // 128-byte context. +- mov $r2 0 +- sethi $r2 0x50000 +- +- // read current channel +- mov $r3 0x1400 +- iord $r4 I[$r3] +- // if bit 30 set, it's active, so we have to unload it first. +- shl b32 $r5 $r4 1 +- cmps b32 $r5 0 +- bra nc #ctxload +- +- // unload the current channel - save the context +- xdst $r0 $r2 +- xdwait +- // and clear bit 30, then write back +- bclr $r4 0x1e +- iowr I[$r3] $r4 +- // tell PFIFO we unloaded +- mov $r4 1 +- iowr I[$r3 + 0x200] $r4 +- +- bra #noctx +- +- ctxload: +- // no channel loaded - perhaps we're requested to load one +- iord $r4 I[$r3 + 0x100] +- shl b32 $r15 $r4 1 +- cmps b32 $r15 0 +- // if bit 30 of next channel not set, probably PFIFO is just +- // killing a context. do a faux load, without the active bit. +- bra nc #dummyload +- +- // ok, do a real context load. +- xdld $r0 $r2 +- xdwait +- mov $r5 #ctx_dma +- mov $r6 #dma_count - 1 +- ctxload_dma_loop: +- ld b32 $r7 D[$r5 + $r6 * 4] +- add b32 $r8 $r6 0x180 +- shl b32 $r8 8 +- iowr I[$r8] $r7 +- sub b32 $r6 1 +- bra nc #ctxload_dma_loop +- +- dummyload: +- // tell PFIFO we're done +- mov $r5 2 +- iowr I[$r3 + 0x200] $r5 +- +- noctx: +- and $r2 $r1 0x4 +- cmpu b32 $r2 0 +- bra e #nocmd +- +- // incoming fifo command. +- mov $r3 0x1900 +- iord $r2 I[$r3 + 0x100] +- iord $r3 I[$r3] +- // extract the method +- and $r4 $r2 0x7ff +- // shift the addr to proper position if we need to interrupt later +- shl b32 $r2 0x10 +- +- // mthd 0 and 0x100 [NAME, NOP]: ignore +- and $r5 $r4 0x7bf +- cmpu b32 $r5 0 +- bra e #cmddone +- +- mov $r5 #engine_cmd_dtable - 0xc0 * 8 +- mov $r6 #engine_cmd_max +- cmpu b32 $r4 0xc0 +- bra nc #dtable_cmd +- mov $r5 #common_cmd_dtable - 0x80 * 8 +- mov $r6 #common_cmd_max +- cmpu b32 $r4 0x80 +- bra nc #dtable_cmd +- cmpu b32 $r4 0x60 +- bra nc #dma_cmd +- cmpu b32 $r4 0x50 +- bra ne #illegal_mthd +- +- // mthd 0x140: PM_TRIGGER +- mov $r2 0x2200 +- clear b32 $r3 +- sethi $r3 0x20000 +- iowr I[$r2] $r3 +- bra #cmddone +- +- dma_cmd: +- // mthd 0x180...: DMA_* +- cmpu b32 $r4 0x60+#dma_count +- bra nc #illegal_mthd +- shl b32 $r5 $r4 2 +- add b32 $r5 ((#ctx_dma - 0x60 * 4) & 0xffff) +- bset $r3 0x1e +- st b32 D[$r5] $r3 +- add b32 $r4 0x180 - 0x60 +- shl b32 $r4 8 +- iowr I[$r4] $r3 +- bra #cmddone +- +- dtable_cmd: +- cmpu b32 $r4 $r6 +- bra nc #illegal_mthd +- shl b32 $r4 3 +- add b32 $r4 $r5 +- ld b32 $r5 D[$r4 + 4] +- and $r5 $r3 +- cmpu b32 $r5 0 +- bra ne #invalid_bitfield +- ld b16 $r5 D[$r4] +- ld b16 $r6 D[$r4 + 2] +- cmpu b32 $r6 2 +- bra e #cmd_setctx +- ld b32 $r7 D[$r0 + #ctx_cond_off] +- and $r6 $r7 +- cmpu b32 $r6 1 +- bra e #cmddone +- call $r5 +- bra $p1 #dispatch_error +- bra #cmddone +- +- cmd_setctx: +- st b32 D[$r5] $r3 +- bra #cmddone +- +- +- invalid_bitfield: +- or $r2 1 +- dispatch_error: +- illegal_mthd: +- mov $r4 0x1000 +- iowr I[$r4] $r2 +- iowr I[$r4 + 0x100] $r3 +- mov $r4 0x40 +- iowr I[$r0] $r4 +- +- im_loop: +- iord $r4 I[$r0 + 0x200] +- and $r4 0x40 +- cmpu b32 $r4 0 +- bra ne #im_loop +- +- cmddone: +- // remove the command from FIFO +- mov $r3 0x1d00 +- mov $r4 1 +- iowr I[$r3] $r4 +- +- nocmd: +- // ack the processed interrupts +- and $r1 $r1 0xc +- iowr I[$r0 + 0x100] $r1 +-iret +- +-cmd_query_get: +- // if bit 0 of param set, trigger interrupt afterwards. +- setp $p1 $r3 +- or $r2 3 +- +- // read PTIMER, beware of races... +- mov $r4 0xb00 +- ptimer_retry: +- iord $r6 I[$r4 + 0x100] +- iord $r5 I[$r4] +- iord $r7 I[$r4 + 0x100] +- cmpu b32 $r6 $r7 +- bra ne #ptimer_retry +- +- // prepare the query structure +- ld b32 $r4 D[$r0 + #ctx_query_counter] +- st b32 D[$r0 + #swap + 0x0] $r4 +- st b32 D[$r0 + #swap + 0x4] $r0 +- st b32 D[$r0 + #swap + 0x8] $r5 +- st b32 D[$r0 + #swap + 0xc] $r6 +- +- // will use target 0, DMA_QUERY. +- mov $xtargets $r0 +- +- ld b32 $r4 D[$r0 + #ctx_query_address_high] +- shl b32 $r4 0x18 +- mov $xdbase $r4 +- +- ld b32 $r4 D[$r0 + #ctx_query_address_low] +- mov $r5 #swap +- sethi $r5 0x20000 +- xdst $r4 $r5 +- xdwait +- +- ret +- +-cmd_cond_mode: +- // if >= 5, INVALID_ENUM +- bset $flags $p1 +- or $r2 2 +- cmpu b32 $r3 5 +- bra nc #return +- +- // otherwise, no error. +- bclr $flags $p1 +- +- // if < 2, no QUERY object is involved +- cmpu b32 $r3 2 +- bra nc #cmd_cond_mode_queryful +- +- xor $r3 1 +- st b32 D[$r0 + #ctx_cond_off] $r3 +- return: +- ret +- +- cmd_cond_mode_queryful: +- // ok, will need to pull a QUERY object, prepare offsets +- ld b32 $r4 D[$r0 + #ctx_cond_address_high] +- ld b32 $r5 D[$r0 + #ctx_cond_address_low] +- and $r6 $r5 0xff +- shr b32 $r5 8 +- shl b32 $r4 0x18 +- or $r4 $r5 +- mov $xdbase $r4 +- mov $xtargets $r0 +- +- // pull the first one +- mov $r5 #swap +- sethi $r5 0x20000 +- xdld $r6 $r5 +- +- // if == 2, only a single QUERY is involved... +- cmpu b32 $r3 2 +- bra ne #cmd_cond_mode_double +- +- xdwait +- ld b32 $r4 D[$r0 + #swap + 4] +- cmpu b32 $r4 0 +- xbit $r4 $flags z +- st b32 D[$r0 + #ctx_cond_off] $r4 +- ret +- +- // ok, we'll need to pull second one too +- cmd_cond_mode_double: +- add b32 $r6 0x10 +- add b32 $r5 0x10 +- xdld $r6 $r5 +- xdwait +- +- // compare COUNTERs +- ld b32 $r5 D[$r0 + #swap + 0x00] +- ld b32 $r6 D[$r0 + #swap + 0x10] +- cmpu b32 $r5 $r6 +- xbit $r4 $flags z +- +- // compare RESen +- ld b32 $r5 D[$r0 + #swap + 0x04] +- ld b32 $r6 D[$r0 + #swap + 0x14] +- cmpu b32 $r5 $r6 +- xbit $r5 $flags z +- and $r4 $r5 +- +- // and negate or not, depending on mode +- cmpu b32 $r3 3 +- xbit $r5 $flags z +- xor $r4 $r5 +- st b32 D[$r0 + #ctx_cond_off] $r4 +- ret +- +-cmd_wrcache_flush: +- bclr $flags $p1 +- mov $r2 0x2200 +- clear b32 $r3 +- sethi $r3 0x10000 +- iowr I[$r2] $r3 +- ret +- +-crypt_cmd_mode: +- // if >= 0xf, INVALID_ENUM +- bset $flags $p1 +- or $r2 2 +- cmpu b32 $r3 0xf +- bra nc #crypt_cmd_mode_return +- +- bclr $flags $p1 +- st b32 D[$r0 + #ctx_mode] $r3 +- +- crypt_cmd_mode_return: +- ret +- +-crypt_cmd_length: +- // nop if length == 0 +- cmpu b32 $r3 0 +- bra e #crypt_cmd_mode_return +- +- // init key, IV +- cxset 3 +- mov $r4 #ctx_key +- sethi $r4 0x70000 +- xdst $r0 $r4 +- mov $r4 #ctx_iv +- sethi $r4 0x60000 +- xdst $r0 $r4 +- xdwait +- ckeyreg $c7 +- +- // prepare the targets +- mov $r4 0x2100 +- mov $xtargets $r4 +- +- // prepare src address +- ld b32 $r4 D[$r0 + #ctx_src_address_high] +- ld b32 $r5 D[$r0 + #ctx_src_address_low] +- shr b32 $r8 $r5 8 +- shl b32 $r4 0x18 +- or $r4 $r8 +- and $r5 $r5 0xff +- +- // prepare dst address +- ld b32 $r6 D[$r0 + #ctx_dst_address_high] +- ld b32 $r7 D[$r0 + #ctx_dst_address_low] +- shr b32 $r8 $r7 8 +- shl b32 $r6 0x18 +- or $r6 $r8 +- and $r7 $r7 0xff +- +- // find the proper prep & do functions +- ld b32 $r8 D[$r0 + #ctx_mode] +- shl b32 $r8 2 +- +- // run prep +- ld b16 $r9 D[$r8 + #crypt_dtable] +- call $r9 +- +- // do it +- ld b16 $r9 D[$r8 + #crypt_dtable + 2] +- call $r9 +- cxset 1 +- xdwait +- cxset 0x61 +- xdwait +- xdwait +- +- // update src address +- shr b32 $r8 $r4 0x18 +- shl b32 $r9 $r4 8 +- add b32 $r9 $r5 +- adc b32 $r8 0 +- st b32 D[$r0 + #ctx_src_address_high] $r8 +- st b32 D[$r0 + #ctx_src_address_low] $r9 +- +- // update dst address +- shr b32 $r8 $r6 0x18 +- shl b32 $r9 $r6 8 +- add b32 $r9 $r7 +- adc b32 $r8 0 +- st b32 D[$r0 + #ctx_dst_address_high] $r8 +- st b32 D[$r0 + #ctx_dst_address_low] $r9 +- +- // pull updated IV +- cxset 2 +- mov $r4 #ctx_iv +- sethi $r4 0x60000 +- xdld $r0 $r4 +- xdwait +- +- ret +- +- +-crypt_copy_prep: +- cs0begin 2 +- cxsin $c0 +- cxsout $c0 +- ret +- +-crypt_store_prep: +- cs0begin 1 +- cxsout $c6 +- ret +- +-crypt_ecb_e_prep: +- cs0begin 3 +- cxsin $c0 +- cenc $c0 $c0 +- cxsout $c0 +- ret +- +-crypt_ecb_d_prep: +- ckexp $c7 $c7 +- cs0begin 3 +- cxsin $c0 +- cdec $c0 $c0 +- cxsout $c0 +- ret +- +-crypt_cbc_e_prep: +- cs0begin 4 +- cxsin $c0 +- cxor $c6 $c0 +- cenc $c6 $c6 +- cxsout $c6 +- ret +- +-crypt_cbc_d_prep: +- ckexp $c7 $c7 +- cs0begin 5 +- cmov $c2 $c6 +- cxsin $c6 +- cdec $c0 $c6 +- cxor $c0 $c2 +- cxsout $c0 +- ret +- +-crypt_pcbc_e_prep: +- cs0begin 5 +- cxsin $c0 +- cxor $c6 $c0 +- cenc $c6 $c6 +- cxsout $c6 +- cxor $c6 $c0 +- ret +- +-crypt_pcbc_d_prep: +- ckexp $c7 $c7 +- cs0begin 5 +- cxsin $c0 +- cdec $c1 $c0 +- cxor $c6 $c1 +- cxsout $c6 +- cxor $c6 $c0 +- ret +- +-crypt_cfb_e_prep: +- cs0begin 4 +- cenc $c6 $c6 +- cxsin $c0 +- cxor $c6 $c0 +- cxsout $c6 +- ret +- +-crypt_cfb_d_prep: +- cs0begin 4 +- cenc $c0 $c6 +- cxsin $c6 +- cxor $c0 $c6 +- cxsout $c0 +- ret +- +-crypt_ofb_prep: +- cs0begin 4 +- cenc $c6 $c6 +- cxsin $c0 +- cxor $c0 $c6 +- cxsout $c0 +- ret +- +-crypt_ctr_prep: +- cs0begin 5 +- cenc $c1 $c6 +- cadd $c6 1 +- cxsin $c0 +- cxor $c0 $c1 +- cxsout $c0 +- ret +- +-crypt_cbc_mac_prep: +- cs0begin 3 +- cxsin $c0 +- cxor $c6 $c0 +- cenc $c6 $c6 +- ret +- +-crypt_cmac_finish_complete_prep: +- cs0begin 7 +- cxsin $c0 +- cxor $c6 $c0 +- cxor $c0 $c0 +- cenc $c0 $c0 +- cprecmac $c0 $c0 +- cxor $c6 $c0 +- cenc $c6 $c6 +- ret +- +-crypt_cmac_finish_partial_prep: +- cs0begin 8 +- cxsin $c0 +- cxor $c6 $c0 +- cxor $c0 $c0 +- cenc $c0 $c0 +- cprecmac $c0 $c0 +- cprecmac $c0 $c0 +- cxor $c6 $c0 +- cenc $c6 $c6 +- ret +- +-// TODO +-crypt_do_in: +- add b32 $r3 $r5 +- mov $xdbase $r4 +- mov $r9 #swap +- sethi $r9 0x20000 +- crypt_do_in_loop: +- xdld $r5 $r9 +- xdwait +- cxset 0x22 +- xdst $r0 $r9 +- cs0exec 1 +- xdwait +- add b32 $r5 0x10 +- cmpu b32 $r5 $r3 +- bra ne #crypt_do_in_loop +- cxset 1 +- xdwait +- ret +- +-crypt_do_out: +- add b32 $r3 $r7 +- mov $xdbase $r6 +- mov $r9 #swap +- sethi $r9 0x20000 +- crypt_do_out_loop: +- cs0exec 1 +- cxset 0x61 +- xdld $r7 $r9 +- xdst $r7 $r9 +- cxset 1 +- xdwait +- add b32 $r7 0x10 +- cmpu b32 $r7 $r3 +- bra ne #crypt_do_out_loop +- ret +- +-crypt_do_inout: +- add b32 $r3 $r5 +- mov $r9 #swap +- sethi $r9 0x20000 +- crypt_do_inout_loop: +- mov $xdbase $r4 +- xdld $r5 $r9 +- xdwait +- cxset 0x21 +- xdst $r0 $r9 +- cs0exec 1 +- cxset 0x61 +- mov $xdbase $r6 +- xdld $r7 $r9 +- xdst $r7 $r9 +- cxset 1 +- xdwait +- add b32 $r5 0x10 +- add b32 $r7 0x10 +- cmpu b32 $r5 $r3 +- bra ne #crypt_do_inout_loop +- ret +- +-.align 0x100 +diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h b/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h +deleted file mode 100644 +index 38676c74..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/crypt/fuc/nv98.fuc.h ++++ /dev/null +@@ -1,584 +0,0 @@ +-uint32_t nv98_pcrypt_data[] = { +-/* 0x0000: ctx_dma */ +-/* 0x0000: ctx_dma_query */ +- 0x00000000, +-/* 0x0004: ctx_dma_src */ +- 0x00000000, +-/* 0x0008: ctx_dma_dst */ +- 0x00000000, +-/* 0x000c: ctx_query_address_high */ +- 0x00000000, +-/* 0x0010: ctx_query_address_low */ +- 0x00000000, +-/* 0x0014: ctx_query_counter */ +- 0x00000000, +-/* 0x0018: ctx_cond_address_high */ +- 0x00000000, +-/* 0x001c: ctx_cond_address_low */ +- 0x00000000, +-/* 0x0020: ctx_cond_off */ +- 0x00000000, +-/* 0x0024: ctx_src_address_high */ +- 0x00000000, +-/* 0x0028: ctx_src_address_low */ +- 0x00000000, +-/* 0x002c: ctx_dst_address_high */ +- 0x00000000, +-/* 0x0030: ctx_dst_address_low */ +- 0x00000000, +-/* 0x0034: ctx_mode */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0040: ctx_key */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0050: ctx_iv */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0080: swap */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x00a0: common_cmd_dtable */ +- 0x0002000c, +- 0xffffff00, +- 0x00020010, +- 0x0000000f, +- 0x00020014, +- 0x00000000, +- 0x00000192, +- 0xfffffffe, +- 0x00020018, +- 0xffffff00, +- 0x0002001c, +- 0x0000000f, +- 0x000001d7, +- 0xfffffff8, +- 0x00000260, +- 0xffffffff, +-/* 0x00e0: engine_cmd_dtable */ +- 0x00020040, +- 0x00000000, +- 0x00020044, +- 0x00000000, +- 0x00020048, +- 0x00000000, +- 0x0002004c, +- 0x00000000, +- 0x00020050, +- 0x00000000, +- 0x00020054, +- 0x00000000, +- 0x00020058, +- 0x00000000, +- 0x0002005c, +- 0x00000000, +- 0x00020024, +- 0xffffff00, +- 0x00020028, +- 0x0000000f, +- 0x0002002c, +- 0xffffff00, +- 0x00020030, +- 0x0000000f, +- 0x00000271, +- 0xfffffff0, +- 0x00010285, +- 0xf000000f, +-/* 0x0150: crypt_dtable */ +- 0x04db0321, +- 0x04b1032f, +- 0x04db0339, +- 0x04db034b, +- 0x04db0361, +- 0x04db0377, +- 0x04db0395, +- 0x04db03af, +- 0x04db03cd, +- 0x04db03e3, +- 0x04db03f9, +- 0x04db040f, +- 0x04830429, +- 0x0483043b, +- 0x0483045d, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nv98_pcrypt_code[] = { +- 0x17f004bd, +- 0x0010fe35, +- 0xf10004fe, +- 0xf0fff017, +- 0x27f10013, +- 0x21d00400, +- 0x0c15f0c0, +- 0xf00021d0, +- 0x27f10317, +- 0x21d01200, +- 0x1031f400, +-/* 0x002f: spin */ +- 0xf40031f4, +- 0x0ef40028, +-/* 0x0035: ih */ +- 0x8001cffd, +- 0xb00812c4, +- 0x0bf40024, +- 0x0027f167, +- 0x002bfe77, +- 0xf00007fe, +- 0x23f00027, +- 0x0037f105, +- 0x0034cf14, +- 0xb0014594, +- 0x18f40055, +- 0x0602fa17, +- 0x4af003f8, +- 0x0034d01e, +- 0xd00147f0, +- 0x0ef48034, +-/* 0x0075: ctxload */ +- 0x4034cf33, +- 0xb0014f94, +- 0x18f400f5, +- 0x0502fa21, +- 0x57f003f8, +- 0x0267f000, +-/* 0x008c: ctxload_dma_loop */ +- 0xa07856bc, +- 0xb6018068, +- 0x87d00884, +- 0x0162b600, +-/* 0x009f: dummyload */ +- 0xf0f018f4, +- 0x35d00257, +-/* 0x00a5: noctx */ +- 0x0412c480, +- 0xf50024b0, +- 0xf100df0b, +- 0xcf190037, +- 0x33cf4032, +- 0xff24e400, +- 0x1024b607, +- 0x07bf45e4, +- 0xf50054b0, +- 0xf100b90b, +- 0xf1fae057, +- 0xb000ce67, +- 0x18f4c044, +- 0xa057f14d, +- 0x8867f1fc, +- 0x8044b000, +- 0xb03f18f4, +- 0x18f46044, +- 0x5044b019, +- 0xf1741bf4, +- 0xbd220027, +- 0x0233f034, +- 0xf50023d0, +-/* 0x0103: dma_cmd */ +- 0xb000810e, +- 0x18f46344, +- 0x0245945e, +- 0xfe8050b7, +- 0x801e39f0, +- 0x40b70053, +- 0x44b60120, +- 0x0043d008, +-/* 0x0123: dtable_cmd */ +- 0xb8600ef4, +- 0x18f40446, +- 0x0344b63e, +- 0x980045bb, +- 0x53fd0145, +- 0x0054b004, +- 0x58291bf4, +- 0x46580045, +- 0x0264b001, +- 0x98170bf4, +- 0x67fd0807, +- 0x0164b004, +- 0xf9300bf4, +- 0x0f01f455, +-/* 0x015b: cmd_setctx */ +- 0x80280ef4, +- 0x0ef40053, +-/* 0x0161: invalid_bitfield */ +- 0x0125f022, +-/* 0x0164: dispatch_error */ +-/* 0x0164: illegal_mthd */ +- 0x100047f1, +- 0xd00042d0, +- 0x47f04043, +- 0x0004d040, +-/* 0x0174: im_loop */ +- 0xf08004cf, +- 0x44b04044, +- 0xf71bf400, +-/* 0x0180: cmddone */ +- 0x1d0037f1, +- 0xd00147f0, +-/* 0x018a: nocmd */ +- 0x11c40034, +- 0x4001d00c, +-/* 0x0192: cmd_query_get */ +- 0x38f201f8, +- 0x0325f001, +- 0x0b0047f1, +-/* 0x019c: ptimer_retry */ +- 0xcf4046cf, +- 0x47cf0045, +- 0x0467b840, +- 0x98f41bf4, +- 0x04800504, +- 0x21008020, +- 0x80220580, +- 0x0bfe2306, +- 0x03049800, +- 0xfe1844b6, +- 0x04980047, +- 0x8057f104, +- 0x0253f000, +- 0xf80645fa, +-/* 0x01d7: cmd_cond_mode */ +- 0xf400f803, +- 0x25f00131, +- 0x0534b002, +- 0xf41218f4, +- 0x34b00132, +- 0x0b18f402, +- 0x800136f0, +-/* 0x01f2: return */ +- 0x00f80803, +-/* 0x01f4: cmd_cond_mode_queryful */ +- 0x98060498, +- 0x56c40705, +- 0x0855b6ff, +- 0xfd1844b6, +- 0x47fe0545, +- 0x000bfe00, +- 0x008057f1, +- 0xfa0253f0, +- 0x34b00565, +- 0x131bf402, +- 0x049803f8, +- 0x0044b021, +- 0x800b4cf0, +- 0x00f80804, +-/* 0x022c: cmd_cond_mode_double */ +- 0xb61060b6, +- 0x65fa1050, +- 0x9803f805, +- 0x06982005, +- 0x0456b824, +- 0x980b4cf0, +- 0x06982105, +- 0x0456b825, +- 0xfd0b5cf0, +- 0x34b00445, +- 0x0b5cf003, +- 0x800645fd, +- 0x00f80804, +-/* 0x0260: cmd_wrcache_flush */ +- 0xf10132f4, +- 0xbd220027, +- 0x0133f034, +- 0xf80023d0, +-/* 0x0271: crypt_cmd_mode */ +- 0x0131f400, +- 0xb00225f0, +- 0x18f40f34, +- 0x0132f409, +-/* 0x0283: crypt_cmd_mode_return */ +- 0xf80d0380, +-/* 0x0285: crypt_cmd_length */ +- 0x0034b000, +- 0xf4fb0bf4, +- 0x47f0033c, +- 0x0743f040, +- 0xf00604fa, +- 0x43f05047, +- 0x0604fa06, +- 0x3cf503f8, +- 0x47f1c407, +- 0x4bfe2100, +- 0x09049800, +- 0x950a0598, +- 0x44b60858, +- 0x0548fd18, +- 0x98ff55c4, +- 0x07980b06, +- 0x0878950c, +- 0xfd1864b6, +- 0x77c40568, +- 0x0d0898ff, +- 0x580284b6, +- 0x95f9a889, +- 0xf9a98958, +- 0x013cf495, +- 0x3cf403f8, +- 0xf803f861, +- 0x18489503, +- 0xbb084994, +- 0x81b60095, +- 0x09088000, +- 0x950a0980, +- 0x69941868, +- 0x0097bb08, +- 0x800081b6, +- 0x09800b08, +- 0x023cf40c, +- 0xf05047f0, +- 0x04fa0643, +- 0xf803f805, +-/* 0x0321: crypt_copy_prep */ +- 0x203cf500, +- 0x003cf594, +- 0x003cf588, +-/* 0x032f: crypt_store_prep */ +- 0xf500f88c, +- 0xf594103c, +- 0xf88c063c, +-/* 0x0339: crypt_ecb_e_prep */ +- 0x303cf500, +- 0x003cf594, +- 0x003cf588, +- 0x003cf5d0, +-/* 0x034b: crypt_ecb_d_prep */ +- 0xf500f88c, +- 0xf5c8773c, +- 0xf594303c, +- 0xf588003c, +- 0xf5d4003c, +- 0xf88c003c, +-/* 0x0361: crypt_cbc_e_prep */ +- 0x403cf500, +- 0x003cf594, +- 0x063cf588, +- 0x663cf5ac, +- 0x063cf5d0, +-/* 0x0377: crypt_cbc_d_prep */ +- 0xf500f88c, +- 0xf5c8773c, +- 0xf594503c, +- 0xf584623c, +- 0xf588063c, +- 0xf5d4603c, +- 0xf5ac203c, +- 0xf88c003c, +-/* 0x0395: crypt_pcbc_e_prep */ +- 0x503cf500, +- 0x003cf594, +- 0x063cf588, +- 0x663cf5ac, +- 0x063cf5d0, +- 0x063cf58c, +-/* 0x03af: crypt_pcbc_d_prep */ +- 0xf500f8ac, +- 0xf5c8773c, +- 0xf594503c, +- 0xf588003c, +- 0xf5d4013c, +- 0xf5ac163c, +- 0xf58c063c, +- 0xf8ac063c, +-/* 0x03cd: crypt_cfb_e_prep */ +- 0x403cf500, +- 0x663cf594, +- 0x003cf5d0, +- 0x063cf588, +- 0x063cf5ac, +-/* 0x03e3: crypt_cfb_d_prep */ +- 0xf500f88c, +- 0xf594403c, +- 0xf5d0603c, +- 0xf588063c, +- 0xf5ac603c, +- 0xf88c003c, +-/* 0x03f9: crypt_ofb_prep */ +- 0x403cf500, +- 0x663cf594, +- 0x003cf5d0, +- 0x603cf588, +- 0x003cf5ac, +-/* 0x040f: crypt_ctr_prep */ +- 0xf500f88c, +- 0xf594503c, +- 0xf5d0613c, +- 0xf5b0163c, +- 0xf588003c, +- 0xf5ac103c, +- 0xf88c003c, +-/* 0x0429: crypt_cbc_mac_prep */ +- 0x303cf500, +- 0x003cf594, +- 0x063cf588, +- 0x663cf5ac, +-/* 0x043b: crypt_cmac_finish_complete_prep */ +- 0xf500f8d0, +- 0xf594703c, +- 0xf588003c, +- 0xf5ac063c, +- 0xf5ac003c, +- 0xf5d0003c, +- 0xf5bc003c, +- 0xf5ac063c, +- 0xf8d0663c, +-/* 0x045d: crypt_cmac_finish_partial_prep */ +- 0x803cf500, +- 0x003cf594, +- 0x063cf588, +- 0x003cf5ac, +- 0x003cf5ac, +- 0x003cf5d0, +- 0x003cf5bc, +- 0x063cf5bc, +- 0x663cf5ac, +-/* 0x0483: crypt_do_in */ +- 0xbb00f8d0, +- 0x47fe0035, +- 0x8097f100, +- 0x0293f000, +-/* 0x0490: crypt_do_in_loop */ +- 0xf80559fa, +- 0x223cf403, +- 0xf50609fa, +- 0xf898103c, +- 0x1050b603, +- 0xf40453b8, +- 0x3cf4e91b, +- 0xf803f801, +-/* 0x04b1: crypt_do_out */ +- 0x0037bb00, +- 0xf10067fe, +- 0xf0008097, +-/* 0x04be: crypt_do_out_loop */ +- 0x3cf50293, +- 0x3cf49810, +- 0x0579fa61, +- 0xf40679fa, +- 0x03f8013c, +- 0xb81070b6, +- 0x1bf40473, +-/* 0x04db: crypt_do_inout */ +- 0xbb00f8e8, +- 0x97f10035, +- 0x93f00080, +-/* 0x04e5: crypt_do_inout_loop */ +- 0x0047fe02, +- 0xf80559fa, +- 0x213cf403, +- 0xf50609fa, +- 0xf498103c, +- 0x67fe613c, +- 0x0579fa00, +- 0xf40679fa, +- 0x03f8013c, +- 0xb61050b6, +- 0x53b81070, +- 0xd41bf404, +- 0x000000f8, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c +deleted file mode 100644 +index ea5c42f3..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv84.c ++++ /dev/null +@@ -1,188 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include +-#include +- +-struct nv84_crypt_priv { +- struct nouveau_engine base; +-}; +- +-/******************************************************************************* +- * Crypt object classes +- ******************************************************************************/ +- +-static int +-nv84_crypt_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj *obj; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, +- 16, 16, 0, &obj); +- *pobject = nv_object(obj); +- if (ret) +- return ret; +- +- nv_wo32(obj, 0x00, nv_mclass(obj)); +- nv_wo32(obj, 0x04, 0x00000000); +- nv_wo32(obj, 0x08, 0x00000000); +- nv_wo32(obj, 0x0c, 0x00000000); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv84_crypt_ofuncs = { +- .ctor = nv84_crypt_object_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +-}; +- +-static struct nouveau_oclass +-nv84_crypt_sclass[] = { +- { 0x74c1, &nv84_crypt_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * PCRYPT context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_crypt_cclass = { +- .handle = NV_ENGCTX(CRYPT, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_engctx_ctor, +- .dtor = _nouveau_engctx_dtor, +- .init = _nouveau_engctx_init, +- .fini = _nouveau_engctx_fini, +- .rd32 = _nouveau_engctx_rd32, +- .wr32 = _nouveau_engctx_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PCRYPT engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_bitfield nv84_crypt_intr_mask[] = { +- { 0x00000001, "INVALID_STATE" }, +- { 0x00000002, "ILLEGAL_MTHD" }, +- { 0x00000004, "ILLEGAL_CLASS" }, +- { 0x00000080, "QUERY" }, +- { 0x00000100, "FAULT" }, +- {} +-}; +- +-static void +-nv84_crypt_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nv84_crypt_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, 0x102130); +- u32 mthd = nv_rd32(priv, 0x102190); +- u32 data = nv_rd32(priv, 0x102194); +- u32 inst = nv_rd32(priv, 0x102188) & 0x7fffffff; +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat) { +- nv_error(priv, "%s", ""); +- nouveau_bitfield_print(nv84_crypt_intr_mask, stat); +- pr_cont(" ch %d [0x%010llx %s] mthd 0x%04x data 0x%08x\n", +- chid, (u64)inst << 12, nouveau_client_name(engctx), +- mthd, data); +- } +- +- nv_wr32(priv, 0x102130, stat); +- nv_wr32(priv, 0x10200c, 0x10); +- +- nouveau_engctx_put(engctx); +-} +- +-static int +-nv84_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv84_crypt_priv *priv; +- int ret; +- +- ret = nouveau_engine_create(parent, engine, oclass, true, +- "PCRYPT", "crypt", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00004000; +- nv_subdev(priv)->intr = nv84_crypt_intr; +- nv_engine(priv)->cclass = &nv84_crypt_cclass; +- nv_engine(priv)->sclass = nv84_crypt_sclass; +- return 0; +-} +- +-static int +-nv84_crypt_init(struct nouveau_object *object) +-{ +- struct nv84_crypt_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_engine_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x102130, 0xffffffff); +- nv_wr32(priv, 0x102140, 0xffffffbf); +- nv_wr32(priv, 0x10200c, 0x00000010); +- return 0; +-} +- +-struct nouveau_oclass +-nv84_crypt_oclass = { +- .handle = NV_ENGINE(CRYPT, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_crypt_ctor, +- .dtor = _nouveau_engine_dtor, +- .init = nv84_crypt_init, +- .fini = _nouveau_engine_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c b/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c +deleted file mode 100644 +index 5571c095..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/crypt/nv98.c ++++ /dev/null +@@ -1,156 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +-#include +- +-#include "fuc/nv98.fuc.h" +- +-struct nv98_crypt_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * Crypt object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_crypt_sclass[] = { +- { 0x88b4, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PCRYPT context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_crypt_cclass = { +- .handle = NV_ENGCTX(CRYPT, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PCRYPT engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_enum nv98_crypt_isr_error_name[] = { +- { 0x0000, "ILLEGAL_MTHD" }, +- { 0x0001, "INVALID_BITFIELD" }, +- { 0x0002, "INVALID_ENUM" }, +- { 0x0003, "QUERY" }, +- {} +-}; +- +-static void +-nv98_crypt_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nv98_crypt_priv *priv = (void *)subdev; +- u32 disp = nv_rd32(priv, 0x08701c); +- u32 stat = nv_rd32(priv, 0x087008) & disp & ~(disp >> 16); +- u32 inst = nv_rd32(priv, 0x087050) & 0x3fffffff; +- u32 ssta = nv_rd32(priv, 0x087040) & 0x0000ffff; +- u32 addr = nv_rd32(priv, 0x087040) >> 16; +- u32 mthd = (addr & 0x07ff) << 2; +- u32 subc = (addr & 0x3800) >> 11; +- u32 data = nv_rd32(priv, 0x087044); +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat & 0x00000040) { +- nv_error(priv, "DISPATCH_ERROR ["); +- nouveau_enum_print(nv98_crypt_isr_error_name, ssta); +- pr_cont("] ch %d [0x%010llx %s] subc %d mthd 0x%04x data 0x%08x\n", +- chid, (u64)inst << 12, nouveau_client_name(engctx), +- subc, mthd, data); +- nv_wr32(priv, 0x087004, 0x00000040); +- stat &= ~0x00000040; +- } +- +- if (stat) { +- nv_error(priv, "unhandled intr 0x%08x\n", stat); +- nv_wr32(priv, 0x087004, stat); +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static int +-nv98_crypt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv98_crypt_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x087000, true, +- "PCRYPT", "crypt", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00004000; +- nv_subdev(priv)->intr = nv98_crypt_intr; +- nv_engine(priv)->cclass = &nv98_crypt_cclass; +- nv_engine(priv)->sclass = nv98_crypt_sclass; +- nv_falcon(priv)->code.data = nv98_pcrypt_code; +- nv_falcon(priv)->code.size = sizeof(nv98_pcrypt_code); +- nv_falcon(priv)->data.data = nv98_pcrypt_data; +- nv_falcon(priv)->data.size = sizeof(nv98_pcrypt_data); +- return 0; +-} +- +-struct nouveau_oclass +-nv98_crypt_oclass = { +- .handle = NV_ENGINE(CRYPT, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv98_crypt_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = _nouveau_falcon_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c b/drivers/gpu/drm/nouveau/core/engine/device/acpi.c +deleted file mode 100644 +index 4dbf0ba8..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.c ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "acpi.h" +- +-#ifdef CONFIG_ACPI +-static int +-nvkm_acpi_ntfy(struct notifier_block *nb, unsigned long val, void *data) +-{ +- struct nouveau_device *device = +- container_of(nb, typeof(*device), acpi.nb); +- struct acpi_bus_event *info = data; +- +- if (!strcmp(info->device_class, "ac_adapter")) +- nvkm_event_send(&device->event, 1, 0, NULL, 0); +- +- return NOTIFY_DONE; +-} +-#endif +- +-int +-nvkm_acpi_fini(struct nouveau_device *device, bool suspend) +-{ +-#ifdef CONFIG_ACPI +- unregister_acpi_notifier(&device->acpi.nb); +-#endif +- return 0; +-} +- +-int +-nvkm_acpi_init(struct nouveau_device *device) +-{ +-#ifdef CONFIG_ACPI +- device->acpi.nb.notifier_call = nvkm_acpi_ntfy; +- register_acpi_notifier(&device->acpi.nb); +-#endif +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h b/drivers/gpu/drm/nouveau/core/engine/device/acpi.h +deleted file mode 100644 +index cc49f4f5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/acpi.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NVKM_DEVICE_ACPI_H__ +-#define __NVKM_DEVICE_ACPI_H__ +- +-#include +- +-int nvkm_acpi_init(struct nouveau_device *); +-int nvkm_acpi_fini(struct nouveau_device *, bool); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/base.c b/drivers/gpu/drm/nouveau/core/engine/device/base.c +deleted file mode 100644 +index 0ef5a571..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/base.c ++++ /dev/null +@@ -1,705 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include "priv.h" +-#include "acpi.h" +- +-static DEFINE_MUTEX(nv_devices_mutex); +-static LIST_HEAD(nv_devices); +- +-struct nouveau_device * +-nouveau_device_find(u64 name) +-{ +- struct nouveau_device *device, *match = NULL; +- mutex_lock(&nv_devices_mutex); +- list_for_each_entry(device, &nv_devices, head) { +- if (device->handle == name) { +- match = device; +- break; +- } +- } +- mutex_unlock(&nv_devices_mutex); +- return match; +-} +- +-int +-nouveau_device_list(u64 *name, int size) +-{ +- struct nouveau_device *device; +- int nr = 0; +- mutex_lock(&nv_devices_mutex); +- list_for_each_entry(device, &nv_devices, head) { +- if (nr++ < size) +- name[nr - 1] = device->handle; +- } +- mutex_unlock(&nv_devices_mutex); +- return nr; +-} +- +-/****************************************************************************** +- * nouveau_devobj (0x0080): class implementation +- *****************************************************************************/ +- +-struct nouveau_devobj { +- struct nouveau_parent base; +- struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; +-}; +- +-static int +-nouveau_devobj_info(struct nouveau_object *object, void *data, u32 size) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nouveau_fb *pfb = nouveau_fb(device); +- struct nouveau_instmem *imem = nouveau_instmem(device); +- union { +- struct nv_device_info_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "device info size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "device info vers %d\n", args->v0.version); +- } else +- return ret; +- +- switch (device->chipset) { +- case 0x01a: +- case 0x01f: +- case 0x04c: +- case 0x04e: +- case 0x063: +- case 0x067: +- case 0x068: +- case 0x0aa: +- case 0x0ac: +- case 0x0af: +- args->v0.platform = NV_DEVICE_INFO_V0_IGP; +- break; +- default: +- if (device->pdev) { +- if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP)) +- args->v0.platform = NV_DEVICE_INFO_V0_AGP; +- else +- if (pci_is_pcie(device->pdev)) +- args->v0.platform = NV_DEVICE_INFO_V0_PCIE; +- else +- args->v0.platform = NV_DEVICE_INFO_V0_PCI; +- } else { +- args->v0.platform = NV_DEVICE_INFO_V0_SOC; +- } +- break; +- } +- +- switch (device->card_type) { +- case NV_04: args->v0.family = NV_DEVICE_INFO_V0_TNT; break; +- case NV_10: +- case NV_11: args->v0.family = NV_DEVICE_INFO_V0_CELSIUS; break; +- case NV_20: args->v0.family = NV_DEVICE_INFO_V0_KELVIN; break; +- case NV_30: args->v0.family = NV_DEVICE_INFO_V0_RANKINE; break; +- case NV_40: args->v0.family = NV_DEVICE_INFO_V0_CURIE; break; +- case NV_50: args->v0.family = NV_DEVICE_INFO_V0_TESLA; break; +- case NV_C0: args->v0.family = NV_DEVICE_INFO_V0_FERMI; break; +- case NV_E0: args->v0.family = NV_DEVICE_INFO_V0_KEPLER; break; +- case GM100: args->v0.family = NV_DEVICE_INFO_V0_MAXWELL; break; +- default: +- args->v0.family = 0; +- break; +- } +- +- args->v0.chipset = device->chipset; +- args->v0.revision = device->chipset >= 0x10 ? nv_rd32(device, 0) : 0x00; +- if (pfb) args->v0.ram_size = args->v0.ram_user = pfb->ram->size; +- else args->v0.ram_size = args->v0.ram_user = 0; +- if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved; +- return 0; +-} +- +-static int +-nouveau_devobj_mthd(struct nouveau_object *object, u32 mthd, +- void *data, u32 size) +-{ +- switch (mthd) { +- case NV_DEVICE_V0_INFO: +- return nouveau_devobj_info(object, data, size); +- default: +- break; +- } +- return -EINVAL; +-} +- +-static u8 +-nouveau_devobj_rd08(struct nouveau_object *object, u64 addr) +-{ +- return nv_rd08(object->engine, addr); +-} +- +-static u16 +-nouveau_devobj_rd16(struct nouveau_object *object, u64 addr) +-{ +- return nv_rd16(object->engine, addr); +-} +- +-static u32 +-nouveau_devobj_rd32(struct nouveau_object *object, u64 addr) +-{ +- return nv_rd32(object->engine, addr); +-} +- +-static void +-nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data) +-{ +- nv_wr08(object->engine, addr, data); +-} +- +-static void +-nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data) +-{ +- nv_wr16(object->engine, addr, data); +-} +- +-static void +-nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- nv_wr32(object->engine, addr, data); +-} +- +-static int +-nouveau_devobj_map(struct nouveau_object *object, u64 *addr, u32 *size) +-{ +- struct nouveau_device *device = nv_device(object); +- *addr = nv_device_resource_start(device, 0); +- *size = nv_device_resource_len(device, 0); +- return 0; +-} +- +-static const u64 disable_map[] = { +- [NVDEV_SUBDEV_VBIOS] = NV_DEVICE_V0_DISABLE_VBIOS, +- [NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_TIMER] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_FB] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_LTC] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_IBUS] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_INSTMEM] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_VM] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_BAR] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_VOLT] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_THERM] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_SUBDEV_PWR] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_ENGINE_PERFMON] = NV_DEVICE_V0_DISABLE_CORE, +- [NVDEV_ENGINE_FIFO] = NV_DEVICE_V0_DISABLE_FIFO, +- [NVDEV_ENGINE_SW] = NV_DEVICE_V0_DISABLE_FIFO, +- [NVDEV_ENGINE_GR] = NV_DEVICE_V0_DISABLE_GRAPH, +- [NVDEV_ENGINE_MPEG] = NV_DEVICE_V0_DISABLE_MPEG, +- [NVDEV_ENGINE_ME] = NV_DEVICE_V0_DISABLE_ME, +- [NVDEV_ENGINE_VP] = NV_DEVICE_V0_DISABLE_VP, +- [NVDEV_ENGINE_CRYPT] = NV_DEVICE_V0_DISABLE_CRYPT, +- [NVDEV_ENGINE_BSP] = NV_DEVICE_V0_DISABLE_BSP, +- [NVDEV_ENGINE_PPP] = NV_DEVICE_V0_DISABLE_PPP, +- [NVDEV_ENGINE_COPY0] = NV_DEVICE_V0_DISABLE_COPY0, +- [NVDEV_ENGINE_COPY1] = NV_DEVICE_V0_DISABLE_COPY1, +- [NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC, +- [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC, +- [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, +- [NVDEV_SUBDEV_NR] = 0, +-}; +- +-static void +-nouveau_devobj_dtor(struct nouveau_object *object) +-{ +- struct nouveau_devobj *devobj = (void *)object; +- int i; +- +- for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) +- nouveau_object_ref(NULL, &devobj->subdev[i]); +- +- nouveau_parent_destroy(&devobj->base); +-} +- +-static struct nouveau_oclass +-nouveau_devobj_oclass_super = { +- .handle = NV_DEVICE, +- .ofuncs = &(struct nouveau_ofuncs) { +- .dtor = nouveau_devobj_dtor, +- .init = _nouveau_parent_init, +- .fini = _nouveau_parent_fini, +- .mthd = nouveau_devobj_mthd, +- .map = nouveau_devobj_map, +- .rd08 = nouveau_devobj_rd08, +- .rd16 = nouveau_devobj_rd16, +- .rd32 = nouveau_devobj_rd32, +- .wr08 = nouveau_devobj_wr08, +- .wr16 = nouveau_devobj_wr16, +- .wr32 = nouveau_devobj_wr32, +- } +-}; +- +-static int +-nouveau_devobj_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv_device_v0 v0; +- } *args = data; +- struct nouveau_client *client = nv_client(parent); +- struct nouveau_device *device; +- struct nouveau_devobj *devobj; +- u32 boot0, strap; +- u64 disable, mmio_base, mmio_size; +- void __iomem *map; +- int ret, i, c; +- +- nv_ioctl(parent, "create device size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create device v%d device %016llx " +- "disable %016llx debug0 %016llx\n", +- args->v0.version, args->v0.device, +- args->v0.disable, args->v0.debug0); +- } else +- return ret; +- +- /* give priviledged clients register access */ +- if (client->super) +- oclass = &nouveau_devobj_oclass_super; +- +- /* find the device subdev that matches what the client requested */ +- device = nv_device(client->device); +- if (args->v0.device != ~0) { +- device = nouveau_device_find(args->v0.device); +- if (!device) +- return -ENODEV; +- } +- +- ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, +- nouveau_control_oclass, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_FIFO) | +- (1ULL << NVDEV_ENGINE_DISP) | +- (1ULL << NVDEV_ENGINE_PERFMON), &devobj); +- *pobject = nv_object(devobj); +- if (ret) +- return ret; +- +- mmio_base = nv_device_resource_start(device, 0); +- mmio_size = nv_device_resource_len(device, 0); +- +- /* translate api disable mask into internal mapping */ +- disable = args->v0.debug0; +- for (i = 0; i < NVDEV_SUBDEV_NR; i++) { +- if (args->v0.disable & disable_map[i]) +- disable |= (1ULL << i); +- } +- +- /* identify the chipset, and determine classes of subdev/engines */ +- if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_IDENTIFY) && +- !device->card_type) { +- map = ioremap(mmio_base, 0x102000); +- if (map == NULL) +- return -ENOMEM; +- +- /* switch mmio to cpu's native endianness */ +-#ifndef __BIG_ENDIAN +- if (ioread32_native(map + 0x000004) != 0x00000000) +-#else +- if (ioread32_native(map + 0x000004) == 0x00000000) +-#endif +- iowrite32_native(0x01000001, map + 0x000004); +- +- /* read boot0 and strapping information */ +- boot0 = ioread32_native(map + 0x000000); +- strap = ioread32_native(map + 0x101000); +- iounmap(map); +- +- /* determine chipset and derive architecture from it */ +- if ((boot0 & 0x1f000000) > 0) { +- device->chipset = (boot0 & 0x1ff00000) >> 20; +- switch (device->chipset & 0x1f0) { +- case 0x010: { +- if (0x461 & (1 << (device->chipset & 0xf))) +- device->card_type = NV_10; +- else +- device->card_type = NV_11; +- break; +- } +- case 0x020: device->card_type = NV_20; break; +- case 0x030: device->card_type = NV_30; break; +- case 0x040: +- case 0x060: device->card_type = NV_40; break; +- case 0x050: +- case 0x080: +- case 0x090: +- case 0x0a0: device->card_type = NV_50; break; +- case 0x0c0: +- case 0x0d0: device->card_type = NV_C0; break; +- case 0x0e0: +- case 0x0f0: +- case 0x100: device->card_type = NV_E0; break; +- case 0x110: device->card_type = GM100; break; +- default: +- break; +- } +- } else +- if ((boot0 & 0xff00fff0) == 0x20004000) { +- if (boot0 & 0x00f00000) +- device->chipset = 0x05; +- else +- device->chipset = 0x04; +- device->card_type = NV_04; +- } +- +- switch (device->card_type) { +- case NV_04: ret = nv04_identify(device); break; +- case NV_10: +- case NV_11: ret = nv10_identify(device); break; +- case NV_20: ret = nv20_identify(device); break; +- case NV_30: ret = nv30_identify(device); break; +- case NV_40: ret = nv40_identify(device); break; +- case NV_50: ret = nv50_identify(device); break; +- case NV_C0: ret = nvc0_identify(device); break; +- case NV_E0: ret = nve0_identify(device); break; +- case GM100: ret = gm100_identify(device); break; +- default: +- ret = -EINVAL; +- break; +- } +- +- if (ret) { +- nv_error(device, "unknown chipset, 0x%08x\n", boot0); +- return ret; +- } +- +- nv_info(device, "BOOT0 : 0x%08x\n", boot0); +- nv_info(device, "Chipset: %s (NV%02X)\n", +- device->cname, device->chipset); +- nv_info(device, "Family : NV%02X\n", device->card_type); +- +- /* determine frequency of timing crystal */ +- if ( device->card_type <= NV_10 || device->chipset < 0x17 || +- (device->chipset >= 0x20 && device->chipset < 0x25)) +- strap &= 0x00000040; +- else +- strap &= 0x00400040; +- +- switch (strap) { +- case 0x00000000: device->crystal = 13500; break; +- case 0x00000040: device->crystal = 14318; break; +- case 0x00400000: device->crystal = 27000; break; +- case 0x00400040: device->crystal = 25000; break; +- } +- +- nv_debug(device, "crystal freq: %dKHz\n", device->crystal); +- } +- +- if (!(args->v0.disable & NV_DEVICE_V0_DISABLE_MMIO) && +- !nv_subdev(device)->mmio) { +- nv_subdev(device)->mmio = ioremap(mmio_base, mmio_size); +- if (!nv_subdev(device)->mmio) { +- nv_error(device, "unable to map device registers\n"); +- return -ENOMEM; +- } +- } +- +- /* ensure requested subsystems are available for use */ +- for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) { +- if (!(oclass = device->oclass[i]) || (disable & (1ULL << i))) +- continue; +- +- if (device->subdev[i]) { +- nouveau_object_ref(device->subdev[i], +- &devobj->subdev[i]); +- continue; +- } +- +- ret = nouveau_object_ctor(nv_object(device), NULL, +- oclass, NULL, i, +- &devobj->subdev[i]); +- if (ret == -ENODEV) +- continue; +- if (ret) +- return ret; +- +- device->subdev[i] = devobj->subdev[i]; +- +- /* note: can't init *any* subdevs until devinit has been run +- * due to not knowing exactly what the vbios init tables will +- * mess with. devinit also can't be run until all of its +- * dependencies have been created. +- * +- * this code delays init of any subdev until all of devinit's +- * dependencies have been created, and then initialises each +- * subdev in turn as they're created. +- */ +- while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) { +- struct nouveau_object *subdev = devobj->subdev[c++]; +- if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) { +- ret = nouveau_object_inc(subdev); +- if (ret) +- return ret; +- atomic_dec(&nv_object(device)->usecount); +- } else +- if (subdev) { +- nouveau_subdev_reset(subdev); +- } +- } +- } +- +- return 0; +-} +- +-static struct nouveau_ofuncs +-nouveau_devobj_ofuncs = { +- .ctor = nouveau_devobj_ctor, +- .dtor = nouveau_devobj_dtor, +- .init = _nouveau_parent_init, +- .fini = _nouveau_parent_fini, +- .mthd = nouveau_devobj_mthd, +-}; +- +-/****************************************************************************** +- * nouveau_device: engine functions +- *****************************************************************************/ +- +-static struct nouveau_oclass +-nouveau_device_sclass[] = { +- { 0x0080, &nouveau_devobj_ofuncs }, +- {} +-}; +- +-static int +-nouveau_device_event_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- if (!WARN_ON(size != 0)) { +- notify->size = 0; +- notify->types = 1; +- notify->index = 0; +- return 0; +- } +- return -EINVAL; +-} +- +-static const struct nvkm_event_func +-nouveau_device_event_func = { +- .ctor = nouveau_device_event_ctor, +-}; +- +-static int +-nouveau_device_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_device *device = (void *)object; +- struct nouveau_object *subdev; +- int ret, i; +- +- for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) { +- if ((subdev = device->subdev[i])) { +- if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { +- ret = nouveau_object_dec(subdev, suspend); +- if (ret && suspend) +- goto fail; +- } +- } +- } +- +- ret = nvkm_acpi_fini(device, suspend); +-fail: +- for (; ret && i < NVDEV_SUBDEV_NR; i++) { +- if ((subdev = device->subdev[i])) { +- if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { +- ret = nouveau_object_inc(subdev); +- if (ret) { +- /* XXX */ +- } +- } +- } +- } +- +- return ret; +-} +- +-static int +-nouveau_device_init(struct nouveau_object *object) +-{ +- struct nouveau_device *device = (void *)object; +- struct nouveau_object *subdev; +- int ret, i = 0; +- +- ret = nvkm_acpi_init(device); +- if (ret) +- goto fail; +- +- for (i = 0; i < NVDEV_SUBDEV_NR; i++) { +- if ((subdev = device->subdev[i])) { +- if (!nv_iclass(subdev, NV_ENGINE_CLASS)) { +- ret = nouveau_object_inc(subdev); +- if (ret) +- goto fail; +- } else { +- nouveau_subdev_reset(subdev); +- } +- } +- } +- +- ret = 0; +-fail: +- for (--i; ret && i >= 0; i--) { +- if ((subdev = device->subdev[i])) { +- if (!nv_iclass(subdev, NV_ENGINE_CLASS)) +- nouveau_object_dec(subdev, false); +- } +- } +- +- if (ret) +- nvkm_acpi_fini(device, false); +- return ret; +-} +- +-static void +-nouveau_device_dtor(struct nouveau_object *object) +-{ +- struct nouveau_device *device = (void *)object; +- +- nvkm_event_fini(&device->event); +- +- mutex_lock(&nv_devices_mutex); +- list_del(&device->head); +- mutex_unlock(&nv_devices_mutex); +- +- if (nv_subdev(device)->mmio) +- iounmap(nv_subdev(device)->mmio); +- +- nouveau_engine_destroy(&device->base); +-} +- +-resource_size_t +-nv_device_resource_start(struct nouveau_device *device, unsigned int bar) +-{ +- if (nv_device_is_pci(device)) { +- return pci_resource_start(device->pdev, bar); +- } else { +- struct resource *res; +- res = platform_get_resource(device->platformdev, +- IORESOURCE_MEM, bar); +- if (!res) +- return 0; +- return res->start; +- } +-} +- +-resource_size_t +-nv_device_resource_len(struct nouveau_device *device, unsigned int bar) +-{ +- if (nv_device_is_pci(device)) { +- return pci_resource_len(device->pdev, bar); +- } else { +- struct resource *res; +- res = platform_get_resource(device->platformdev, +- IORESOURCE_MEM, bar); +- if (!res) +- return 0; +- return resource_size(res); +- } +-} +- +-int +-nv_device_get_irq(struct nouveau_device *device, bool stall) +-{ +- if (nv_device_is_pci(device)) { +- return device->pdev->irq; +- } else { +- return platform_get_irq_byname(device->platformdev, +- stall ? "stall" : "nonstall"); +- } +-} +- +-static struct nouveau_oclass +-nouveau_device_oclass = { +- .handle = NV_ENGINE(DEVICE, 0x00), +- .ofuncs = &(struct nouveau_ofuncs) { +- .dtor = nouveau_device_dtor, +- .init = nouveau_device_init, +- .fini = nouveau_device_fini, +- }, +-}; +- +-int +-nouveau_device_create_(void *dev, enum nv_bus_type type, u64 name, +- const char *sname, const char *cfg, const char *dbg, +- int length, void **pobject) +-{ +- struct nouveau_device *device; +- int ret = -EEXIST; +- +- mutex_lock(&nv_devices_mutex); +- list_for_each_entry(device, &nv_devices, head) { +- if (device->handle == name) +- goto done; +- } +- +- ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true, +- "DEVICE", "device", length, pobject); +- device = *pobject; +- if (ret) +- goto done; +- +- switch (type) { +- case NOUVEAU_BUS_PCI: +- device->pdev = dev; +- break; +- case NOUVEAU_BUS_PLATFORM: +- device->platformdev = dev; +- break; +- } +- device->handle = name; +- device->cfgopt = cfg; +- device->dbgopt = dbg; +- device->name = sname; +- +- nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE"); +- nv_engine(device)->sclass = nouveau_device_sclass; +- list_add(&device->head, &nv_devices); +- +- ret = nvkm_event_init(&nouveau_device_event_func, 1, 1, +- &device->event); +-done: +- mutex_unlock(&nv_devices_mutex); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c +deleted file mode 100644 +index e34101a3..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/ctrl.c ++++ /dev/null +@@ -1,205 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include "priv.h" +- +-static int +-nouveau_control_mthd_pstate_info(struct nouveau_object *object, +- void *data, u32 size) +-{ +- union { +- struct nvif_control_pstate_info_v0 v0; +- } *args = data; +- struct nouveau_clock *clk = nouveau_clock(object); +- int ret; +- +- nv_ioctl(object, "control pstate info size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "control pstate info vers %d\n", +- args->v0.version); +- } else +- return ret; +- +- if (clk) { +- args->v0.count = clk->state_nr; +- args->v0.ustate_ac = clk->ustate_ac; +- args->v0.ustate_dc = clk->ustate_dc; +- args->v0.pwrsrc = clk->pwrsrc; +- args->v0.pstate = clk->pstate; +- } else { +- args->v0.count = 0; +- args->v0.ustate_ac = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; +- args->v0.ustate_dc = NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE; +- args->v0.pwrsrc = -ENOSYS; +- args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN; +- } +- +- return 0; +-} +- +-static int +-nouveau_control_mthd_pstate_attr(struct nouveau_object *object, +- void *data, u32 size) +-{ +- union { +- struct nvif_control_pstate_attr_v0 v0; +- } *args = data; +- struct nouveau_clock *clk = nouveau_clock(object); +- struct nouveau_clocks *domain; +- struct nouveau_pstate *pstate; +- struct nouveau_cstate *cstate; +- int i = 0, j = -1; +- u32 lo, hi; +- int ret; +- +- nv_ioctl(object, "control pstate attr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "control pstate attr vers %d state %d " +- "index %d\n", +- args->v0.version, args->v0.state, args->v0.index); +- if (!clk) +- return -ENODEV; +- if (args->v0.state < NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) +- return -EINVAL; +- if (args->v0.state >= clk->state_nr) +- return -EINVAL; +- } else +- return ret; +- domain = clk->domains; +- +- while (domain->name != nv_clk_src_max) { +- if (domain->mname && ++j == args->v0.index) +- break; +- domain++; +- } +- +- if (domain->name == nv_clk_src_max) +- return -EINVAL; +- +- if (args->v0.state != NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT) { +- list_for_each_entry(pstate, &clk->states, head) { +- if (i++ == args->v0.state) +- break; +- } +- +- lo = pstate->base.domain[domain->name]; +- hi = lo; +- list_for_each_entry(cstate, &pstate->list, head) { +- lo = min(lo, cstate->domain[domain->name]); +- hi = max(hi, cstate->domain[domain->name]); +- } +- +- args->v0.state = pstate->pstate; +- } else { +- lo = max(clk->read(clk, domain->name), 0); +- hi = lo; +- } +- +- snprintf(args->v0.name, sizeof(args->v0.name), "%s", domain->mname); +- snprintf(args->v0.unit, sizeof(args->v0.unit), "MHz"); +- args->v0.min = lo / domain->mdiv; +- args->v0.max = hi / domain->mdiv; +- +- args->v0.index = 0; +- while ((++domain)->name != nv_clk_src_max) { +- if (domain->mname) { +- args->v0.index = ++j; +- break; +- } +- } +- +- return 0; +-} +- +-static int +-nouveau_control_mthd_pstate_user(struct nouveau_object *object, +- void *data, u32 size) +-{ +- union { +- struct nvif_control_pstate_user_v0 v0; +- } *args = data; +- struct nouveau_clock *clk = nouveau_clock(object); +- int ret; +- +- nv_ioctl(object, "control pstate user size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "control pstate user vers %d ustate %d " +- "pwrsrc %d\n", args->v0.version, +- args->v0.ustate, args->v0.pwrsrc); +- if (!clk) +- return -ENODEV; +- } else +- return ret; +- +- if (args->v0.pwrsrc >= 0) { +- ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc); +- } else { +- ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0); +- ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1); +- } +- +- return ret; +-} +- +-static int +-nouveau_control_mthd(struct nouveau_object *object, u32 mthd, +- void *data, u32 size) +-{ +- switch (mthd) { +- case NVIF_CONTROL_PSTATE_INFO: +- return nouveau_control_mthd_pstate_info(object, data, size); +- case NVIF_CONTROL_PSTATE_ATTR: +- return nouveau_control_mthd_pstate_attr(object, data, size); +- case NVIF_CONTROL_PSTATE_USER: +- return nouveau_control_mthd_pstate_user(object, data, size); +- default: +- break; +- } +- return -EINVAL; +-} +- +-static struct nouveau_ofuncs +-nouveau_control_ofuncs = { +- .ctor = _nouveau_object_ctor, +- .dtor = nouveau_object_destroy, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- .mthd = nouveau_control_mthd, +-}; +- +-struct nouveau_oclass +-nouveau_control_oclass[] = { +- { .handle = NVIF_IOCTL_NEW_V0_CONTROL, +- .ofuncs = &nouveau_control_ofuncs +- }, +- {} +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c b/drivers/gpu/drm/nouveau/core/engine/device/gm100.c +deleted file mode 100644 +index 6295668e..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/gm100.c ++++ /dev/null +@@ -1,107 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-gm100_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x117: +- device->cname = "GM107"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = gm107_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; +- +-#if 0 +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +-#endif +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = gm107_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = gm107_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +-#if 0 +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +-#endif +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +-#if 0 +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +-#endif +- break; +- default: +- nv_fatal(device, "unknown Maxwell chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c b/drivers/gpu/drm/nouveau/core/engine/device/nv04.c +deleted file mode 100644 +index 573b55f5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nv04.c ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nv04_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x04: +- device->cname = "NV04"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x05: +- device->cname = "NV05"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- default: +- nv_fatal(device, "unknown RIVA chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c b/drivers/gpu/drm/nouveau/core/engine/device/nv10.c +deleted file mode 100644 +index 183a85a6..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nv10.c ++++ /dev/null +@@ -1,204 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nv10_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x10: +- device->cname = "NV10"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x15: +- device->cname = "NV15"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x16: +- device->cname = "NV16"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x1a: +- device->cname = "nForce"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x11: +- device->cname = "NV11"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x17: +- device->cname = "NV17"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x1f: +- device->cname = "nForce2"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x18: +- device->cname = "NV18"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- default: +- nv_fatal(device, "unknown Celsius chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c b/drivers/gpu/drm/nouveau/core/engine/device/nv20.c +deleted file mode 100644 +index aa564c68..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nv20.c ++++ /dev/null +@@ -1,131 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nv20_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x20: +- device->cname = "NV20"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x25: +- device->cname = "NV25"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x28: +- device->cname = "NV28"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x2a: +- device->cname = "NV2A"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- default: +- nv_fatal(device, "unknown Kelvin chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c b/drivers/gpu/drm/nouveau/core/engine/device/nv30.c +deleted file mode 100644 +index 11bd31da..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nv30.c ++++ /dev/null +@@ -1,153 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nv30_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x30: +- device->cname = "NV30"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x35: +- device->cname = "NV35"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x31: +- device->cname = "NV31"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x36: +- device->cname = "NV36"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- case 0x34: +- device->cname = "NV34"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- break; +- default: +- nv_fatal(device, "unknown Rankine chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c b/drivers/gpu/drm/nouveau/core/engine/device/nv40.c +deleted file mode 100644 +index e96c223c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nv40.c ++++ /dev/null +@@ -1,427 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nv40_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x40: +- device->cname = "NV40"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x41: +- device->cname = "NV41"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x42: +- device->cname = "NV42"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x43: +- device->cname = "NV43"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x45: +- device->cname = "NV45"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x47: +- device->cname = "G70"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x49: +- device->cname = "G71"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x4b: +- device->cname = "G73"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x44: +- device->cname = "NV44"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x46: +- device->cname = "G72"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x4a: +- device->cname = "NV44A"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x4c: +- device->cname = "C61"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x4e: +- device->cname = "C51"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x63: +- device->cname = "C73"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x67: +- device->cname = "C67"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- case 0x68: +- device->cname = "C68"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv04_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass; +- break; +- default: +- nv_fatal(device, "unknown Curie chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c b/drivers/gpu/drm/nouveau/core/engine/device/nv50.c +deleted file mode 100644 +index 96f568d1..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nv50.c ++++ /dev/null +@@ -1,475 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nv50_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0x50: +- device->cname = "G80"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv50_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass; +- break; +- case 0x84: +- device->cname = "G84"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0x86: +- device->cname = "G86"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0x92: +- device->cname = "G92"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv84_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0x94: +- device->cname = "G94"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0x96: +- device->cname = "G96"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0x98: +- device->cname = "G98"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0xa0: +- device->cname = "G200"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva0_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0xaa: +- device->cname = "MCP77/MCP78"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0xac: +- device->cname = "MCP79/MCP7A"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; +- break; +- case 0xa3: +- device->cname = "GT215"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; +- break; +- case 0xa5: +- device->cname = "GT216"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; +- break; +- case 0xa8: +- device->cname = "GT218"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; +- break; +- case 0xaf: +- device->cname = "MCP89"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nva3_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass; +- break; +- default: +- nv_fatal(device, "unknown Tesla chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c +deleted file mode 100644 +index 72a40f95..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nvc0.c ++++ /dev/null +@@ -1,357 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nvc0_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0xc0: +- device->cname = "GF100"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xc4: +- device->cname = "GF104"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xc3: +- device->cname = "GF106"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xce: +- device->cname = "GF114"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xcf: +- device->cname = "GF116"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xc1: +- device->cname = "GF108"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xc8: +- device->cname = "GF110"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvc0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xd9: +- device->cname = "GF119"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- case 0xd7: +- device->cname = "GF117"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass; +- break; +- default: +- nv_fatal(device, "unknown Fermi chipset\n"); +- return -EINVAL; +- } +- +- return 0; +- } +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c b/drivers/gpu/drm/nouveau/core/engine/device/nve0.c +deleted file mode 100644 +index b1b2e484..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/nve0.c ++++ /dev/null +@@ -1,290 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-int +-nve0_identify(struct nouveau_device *device) +-{ +- switch (device->chipset) { +- case 0xe4: +- device->cname = "GK104"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; +- break; +- case 0xe7: +- device->cname = "GK107"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; +- break; +- case 0xe6: +- device->cname = "GK106"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = gk104_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nve0_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; +- break; +- case 0xea: +- device->cname = "GK20A"; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = gk20a_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = gk20a_graph_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; +- break; +- case 0xf0: +- device->cname = "GK110"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; +- break; +- case 0xf1: +- device->cname = "GK110B"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nvd0_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = gk110b_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; +- break; +- case 0x108: +- device->cname = "GK208"; +- device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass; +- device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass; +- device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass; +- device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass; +- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass; +- device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass; +- device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass; +- device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass; +- device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass; +- device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass; +- device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; +- device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass; +- device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; +- device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass; +- device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; +- device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass; +- device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass; +- device->oclass[NVDEV_SUBDEV_PWR ] = nv108_pwr_oclass; +- device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; +- device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; +- device->oclass[NVDEV_ENGINE_FIFO ] = nv108_fifo_oclass; +- device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; +- device->oclass[NVDEV_ENGINE_GR ] = nv108_graph_oclass; +- device->oclass[NVDEV_ENGINE_DISP ] = nvf0_disp_oclass; +- device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; +- device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; +- device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; +- device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; +- device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; +- device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; +- break; +- default: +- nv_fatal(device, "unknown Kepler chipset\n"); +- return -EINVAL; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/device/priv.h b/drivers/gpu/drm/nouveau/core/engine/device/priv.h +deleted file mode 100644 +index 035fd5b9..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/device/priv.h ++++ /dev/null +@@ -1,8 +0,0 @@ +-#ifndef __NVKM_DEVICE_PRIV_H__ +-#define __NVKM_DEVICE_PRIV_H__ +- +-#include +- +-extern struct nouveau_oclass nouveau_control_oclass[]; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/base.c b/drivers/gpu/drm/nouveau/core/engine/disp/base.c +deleted file mode 100644 +index 64b84667..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/base.c ++++ /dev/null +@@ -1,242 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include "priv.h" +-#include "outp.h" +-#include "conn.h" +- +-int +-nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- struct nouveau_disp *disp = +- container_of(notify->event, typeof(*disp), vblank); +- union { +- struct nvif_notify_head_req_v0 v0; +- } *req = data; +- int ret; +- +- if (nvif_unpack(req->v0, 0, 0, false)) { +- notify->size = sizeof(struct nvif_notify_head_rep_v0); +- if (ret = -ENXIO, req->v0.head <= disp->vblank.index_nr) { +- notify->types = 1; +- notify->index = req->v0.head; +- return 0; +- } +- } +- +- return ret; +-} +- +-void +-nouveau_disp_vblank(struct nouveau_disp *disp, int head) +-{ +- struct nvif_notify_head_rep_v0 rep = {}; +- nvkm_event_send(&disp->vblank, 1, head, &rep, sizeof(rep)); +-} +- +-static int +-nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- struct nouveau_disp *disp = +- container_of(notify->event, typeof(*disp), hpd); +- union { +- struct nvif_notify_conn_req_v0 v0; +- } *req = data; +- struct nvkm_output *outp; +- int ret; +- +- if (nvif_unpack(req->v0, 0, 0, false)) { +- notify->size = sizeof(struct nvif_notify_conn_rep_v0); +- list_for_each_entry(outp, &disp->outp, head) { +- if (ret = -ENXIO, outp->conn->index == req->v0.conn) { +- if (ret = -ENODEV, outp->conn->hpd.event) { +- notify->types = req->v0.mask; +- notify->index = req->v0.conn; +- ret = 0; +- } +- break; +- } +- } +- } +- +- return ret; +-} +- +-static const struct nvkm_event_func +-nouveau_disp_hpd_func = { +- .ctor = nouveau_disp_hpd_ctor +-}; +- +-int +-nouveau_disp_ntfy(struct nouveau_object *object, u32 type, +- struct nvkm_event **event) +-{ +- struct nouveau_disp *disp = (void *)object->engine; +- switch (type) { +- case NV04_DISP_NTFY_VBLANK: +- *event = &disp->vblank; +- return 0; +- case NV04_DISP_NTFY_CONN: +- *event = &disp->hpd; +- return 0; +- default: +- break; +- } +- return -EINVAL; +-} +- +-int +-_nouveau_disp_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_disp *disp = (void *)object; +- struct nvkm_output *outp; +- int ret; +- +- list_for_each_entry(outp, &disp->outp, head) { +- ret = nv_ofuncs(outp)->fini(nv_object(outp), suspend); +- if (ret && suspend) +- goto fail_outp; +- } +- +- return nouveau_engine_fini(&disp->base, suspend); +- +-fail_outp: +- list_for_each_entry_continue_reverse(outp, &disp->outp, head) { +- nv_ofuncs(outp)->init(nv_object(outp)); +- } +- +- return ret; +-} +- +-int +-_nouveau_disp_init(struct nouveau_object *object) +-{ +- struct nouveau_disp *disp = (void *)object; +- struct nvkm_output *outp; +- int ret; +- +- ret = nouveau_engine_init(&disp->base); +- if (ret) +- return ret; +- +- list_for_each_entry(outp, &disp->outp, head) { +- ret = nv_ofuncs(outp)->init(nv_object(outp)); +- if (ret) +- goto fail_outp; +- } +- +- return ret; +- +-fail_outp: +- list_for_each_entry_continue_reverse(outp, &disp->outp, head) { +- nv_ofuncs(outp)->fini(nv_object(outp), false); +- } +- +- return ret; +-} +- +-void +-_nouveau_disp_dtor(struct nouveau_object *object) +-{ +- struct nouveau_disp *disp = (void *)object; +- struct nvkm_output *outp, *outt; +- +- nvkm_event_fini(&disp->vblank); +- nvkm_event_fini(&disp->hpd); +- +- if (disp->outp.next) { +- list_for_each_entry_safe(outp, outt, &disp->outp, head) { +- nouveau_object_ref(NULL, (struct nouveau_object **)&outp); +- } +- } +- +- nouveau_engine_destroy(&disp->base); +-} +- +-int +-nouveau_disp_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int heads, +- const char *intname, const char *extname, +- int length, void **pobject) +-{ +- struct nouveau_disp_impl *impl = (void *)oclass; +- struct nouveau_bios *bios = nouveau_bios(parent); +- struct nouveau_disp *disp; +- struct nouveau_oclass **sclass; +- struct nouveau_object *object; +- struct dcb_output dcbE; +- u8 hpd = 0, ver, hdr; +- u32 data; +- int ret, i; +- +- ret = nouveau_engine_create_(parent, engine, oclass, true, +- intname, extname, length, pobject); +- disp = *pobject; +- if (ret) +- return ret; +- +- INIT_LIST_HEAD(&disp->outp); +- +- /* create output objects for each display path in the vbios */ +- i = -1; +- while ((data = dcb_outp_parse(bios, ++i, &ver, &hdr, &dcbE))) { +- if (dcbE.type == DCB_OUTPUT_UNUSED) +- continue; +- if (dcbE.type == DCB_OUTPUT_EOL) +- break; +- data = dcbE.location << 4 | dcbE.type; +- +- oclass = nvkm_output_oclass; +- sclass = impl->outp; +- while (sclass && sclass[0]) { +- if (sclass[0]->handle == data) { +- oclass = sclass[0]; +- break; +- } +- sclass++; +- } +- +- nouveau_object_ctor(*pobject, *pobject, oclass, +- &dcbE, i, &object); +- hpd = max(hpd, (u8)(dcbE.connector + 1)); +- } +- +- ret = nvkm_event_init(&nouveau_disp_hpd_func, 3, hpd, &disp->hpd); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(impl->vblank, 1, heads, &disp->vblank); +- if (ret) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c b/drivers/gpu/drm/nouveau/core/engine/disp/conn.c +deleted file mode 100644 +index 1496b567..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.c ++++ /dev/null +@@ -1,175 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "conn.h" +-#include "outp.h" +- +-static int +-nvkm_connector_hpd(struct nvkm_notify *notify) +-{ +- struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd); +- struct nouveau_disp *disp = nouveau_disp(conn); +- struct nouveau_gpio *gpio = nouveau_gpio(conn); +- const struct nvkm_gpio_ntfy_rep *line = notify->data; +- struct nvif_notify_conn_rep_v0 rep; +- int index = conn->index; +- +- DBG("HPD: %d\n", line->mask); +- +- if (!gpio->get(gpio, 0, DCB_GPIO_UNUSED, conn->hpd.index)) +- rep.mask = NVIF_NOTIFY_CONN_V0_UNPLUG; +- else +- rep.mask = NVIF_NOTIFY_CONN_V0_PLUG; +- rep.version = 0; +- +- nvkm_event_send(&disp->hpd, rep.mask, index, &rep, sizeof(rep)); +- return NVKM_NOTIFY_KEEP; +-} +- +-int +-_nvkm_connector_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvkm_connector *conn = (void *)object; +- nvkm_notify_put(&conn->hpd); +- return nouveau_object_fini(&conn->base, suspend); +-} +- +-int +-_nvkm_connector_init(struct nouveau_object *object) +-{ +- struct nvkm_connector *conn = (void *)object; +- int ret = nouveau_object_init(&conn->base); +- if (ret == 0) +- nvkm_notify_get(&conn->hpd); +- return ret; +-} +- +-void +-_nvkm_connector_dtor(struct nouveau_object *object) +-{ +- struct nvkm_connector *conn = (void *)object; +- nvkm_notify_fini(&conn->hpd); +- nouveau_object_destroy(&conn->base); +-} +- +-int +-nvkm_connector_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- struct nvbios_connE *info, int index, +- int length, void **pobject) +-{ +- static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 }; +- struct nouveau_gpio *gpio = nouveau_gpio(parent); +- struct nouveau_disp *disp = (void *)engine; +- struct nvkm_connector *conn; +- struct nvkm_output *outp; +- struct dcb_gpio_func func; +- int ret; +- +- list_for_each_entry(outp, &disp->outp, head) { +- if (outp->conn && outp->conn->index == index) { +- atomic_inc(&nv_object(outp->conn)->refcount); +- *pobject = outp->conn; +- return 1; +- } +- } +- +- ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject); +- conn = *pobject; +- if (ret) +- return ret; +- +- conn->info = *info; +- conn->index = index; +- +- DBG("type %02x loc %d hpd %02x dp %x di %x sr %x lcdid %x\n", +- info->type, info->location, info->hpd, info->dp, +- info->di, info->sr, info->lcdid); +- +- if ((info->hpd = ffs(info->hpd))) { +- if (--info->hpd >= ARRAY_SIZE(hpd)) { +- ERR("hpd %02x unknown\n", info->hpd); +- return 0; +- } +- info->hpd = hpd[info->hpd]; +- +- ret = gpio->find(gpio, 0, info->hpd, DCB_GPIO_UNUSED, &func); +- if (ret) { +- ERR("func %02x lookup failed, %d\n", info->hpd, ret); +- return 0; +- } +- +- ret = nvkm_notify_init(NULL, &gpio->event, nvkm_connector_hpd, +- true, &(struct nvkm_gpio_ntfy_req) { +- .mask = NVKM_GPIO_TOGGLED, +- .line = func.line, +- }, +- sizeof(struct nvkm_gpio_ntfy_req), +- sizeof(struct nvkm_gpio_ntfy_rep), +- &conn->hpd); +- if (ret) { +- ERR("func %02x failed, %d\n", info->hpd, ret); +- } else { +- DBG("func %02x (HPD)\n", info->hpd); +- } +- } +- +- return 0; +-} +- +-int +-_nvkm_connector_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *info, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nvkm_connector *conn; +- int ret; +- +- ret = nvkm_connector_create(parent, engine, oclass, info, index, &conn); +- *pobject = nv_object(conn); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-nvkm_connector_oclass = &(struct nvkm_connector_impl) { +- .base = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_connector_ctor, +- .dtor = _nvkm_connector_dtor, +- .init = _nvkm_connector_init, +- .fini = _nvkm_connector_fini, +- }, +- }, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h b/drivers/gpu/drm/nouveau/core/engine/disp/conn.h +deleted file mode 100644 +index 55e5f5c8..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/conn.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-#ifndef __NVKM_DISP_CONN_H__ +-#define __NVKM_DISP_CONN_H__ +- +-#include "priv.h" +- +-struct nvkm_connector { +- struct nouveau_object base; +- struct list_head head; +- +- struct nvbios_connE info; +- int index; +- +- struct nvkm_notify hpd; +-}; +- +-#define nvkm_connector_create(p,e,c,b,i,d) \ +- nvkm_connector_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d) +-#define nvkm_connector_destroy(d) ({ \ +- struct nvkm_connector *disp = (d); \ +- _nvkm_connector_dtor(nv_object(disp)); \ +-}) +-#define nvkm_connector_init(d) ({ \ +- struct nvkm_connector *disp = (d); \ +- _nvkm_connector_init(nv_object(disp)); \ +-}) +-#define nvkm_connector_fini(d,s) ({ \ +- struct nvkm_connector *disp = (d); \ +- _nvkm_connector_fini(nv_object(disp), (s)); \ +-}) +- +-int nvkm_connector_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, struct nvbios_connE *, +- int, int, void **); +- +-int _nvkm_connector_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void _nvkm_connector_dtor(struct nouveau_object *); +-int _nvkm_connector_init(struct nouveau_object *); +-int _nvkm_connector_fini(struct nouveau_object *, bool); +- +-struct nvkm_connector_impl { +- struct nouveau_oclass base; +-}; +- +-#ifndef MSG +-#define MSG(l,f,a...) do { \ +- struct nvkm_connector *_conn = (void *)conn; \ +- nv_##l(nv_object(conn)->engine, "%02x:%02x%02x: "f, _conn->index, \ +- _conn->info.location, _conn->info.type, ##a); \ +-} while(0) +-#define DBG(f,a...) MSG(debug, f, ##a) +-#define ERR(f,a...) MSG(error, f, ##a) +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c +deleted file mode 100644 +index b36addff..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nv50_dac_power(NV50_DISP_MTHD_V1) +-{ +- const u32 doff = outp->or * 0x800; +- union { +- struct nv50_disp_dac_pwr_v0 v0; +- } *args = data; +- u32 stat; +- int ret; +- +- nv_ioctl(object, "disp dac pwr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp dac pwr vers %d state %d data %d " +- "vsync %d hsync %d\n", +- args->v0.version, args->v0.state, args->v0.data, +- args->v0.vsync, args->v0.hsync); +- stat = 0x00000040 * !args->v0.state; +- stat |= 0x00000010 * !args->v0.data; +- stat |= 0x00000004 * !args->v0.vsync; +- stat |= 0x00000001 * !args->v0.hsync; +- } else +- return ret; +- +- nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); +- nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); +- nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); +- return 0; +-} +- +-int +-nv50_dac_sense(NV50_DISP_MTHD_V1) +-{ +- union { +- struct nv50_disp_dac_load_v0 v0; +- } *args = data; +- const u32 doff = outp->or * 0x800; +- u32 loadval; +- int ret; +- +- nv_ioctl(object, "disp dac load size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp dac load vers %d data %08x\n", +- args->v0.version, args->v0.data); +- if (args->v0.data & 0xfff00000) +- return -EINVAL; +- loadval = args->v0.data; +- } else +- return ret; +- +- nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000); +- nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); +- +- nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval); +- mdelay(9); +- udelay(500); +- loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000); +- +- nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000); +- nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); +- +- nv_debug(priv, "DAC%d sense: 0x%08x\n", outp->or, loadval); +- if (!(loadval & 0x80000000)) +- return -ETIMEDOUT; +- +- args->v0.load = (loadval & 0x38000000) >> 27; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c b/drivers/gpu/drm/nouveau/core/engine/disp/dport.c +deleted file mode 100644 +index 39890221..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.c ++++ /dev/null +@@ -1,399 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include +- +-#include "dport.h" +-#include "outpdp.h" +- +-/****************************************************************************** +- * link training +- *****************************************************************************/ +-struct dp_state { +- struct nvkm_output_dp *outp; +- int link_nr; +- u32 link_bw; +- u8 stat[6]; +- u8 conf[4]; +- bool pc2; +- u8 pc2stat; +- u8 pc2conf[2]; +-}; +- +-static int +-dp_set_link_config(struct dp_state *dp) +-{ +- struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); +- struct nvkm_output_dp *outp = dp->outp; +- struct nouveau_disp *disp = nouveau_disp(outp); +- struct nouveau_bios *bios = nouveau_bios(disp); +- struct nvbios_init init = { +- .subdev = nv_subdev(disp), +- .bios = bios, +- .offset = 0x0000, +- .outp = &outp->base.info, +- .crtc = -1, +- .execute = 1, +- }; +- u32 lnkcmp; +- u8 sink[2]; +- int ret; +- +- DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw); +- +- /* set desired link configuration on the source */ +- if ((lnkcmp = dp->outp->info.lnkcmp)) { +- if (outp->version < 0x30) { +- while ((dp->link_bw / 10) < nv_ro16(bios, lnkcmp)) +- lnkcmp += 4; +- init.offset = nv_ro16(bios, lnkcmp + 2); +- } else { +- while ((dp->link_bw / 27000) < nv_ro08(bios, lnkcmp)) +- lnkcmp += 3; +- init.offset = nv_ro16(bios, lnkcmp + 1); +- } +- +- nvbios_exec(&init); +- } +- +- ret = impl->lnk_ctl(outp, dp->link_nr, dp->link_bw / 27000, +- outp->dpcd[DPCD_RC02] & +- DPCD_RC02_ENHANCED_FRAME_CAP); +- if (ret) { +- if (ret < 0) +- ERR("lnk_ctl failed with %d\n", ret); +- return ret; +- } +- +- impl->lnk_pwr(outp, dp->link_nr); +- +- /* set desired link configuration on the sink */ +- sink[0] = dp->link_bw / 27000; +- sink[1] = dp->link_nr; +- if (outp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP) +- sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN; +- +- return nv_wraux(outp->base.edid, DPCD_LC00_LINK_BW_SET, sink, 2); +-} +- +-static void +-dp_set_training_pattern(struct dp_state *dp, u8 pattern) +-{ +- struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); +- struct nvkm_output_dp *outp = dp->outp; +- u8 sink_tp; +- +- DBG("training pattern %d\n", pattern); +- impl->pattern(outp, pattern); +- +- nv_rdaux(outp->base.edid, DPCD_LC02, &sink_tp, 1); +- sink_tp &= ~DPCD_LC02_TRAINING_PATTERN_SET; +- sink_tp |= pattern; +- nv_wraux(outp->base.edid, DPCD_LC02, &sink_tp, 1); +-} +- +-static int +-dp_link_train_commit(struct dp_state *dp, bool pc) +-{ +- struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp); +- struct nvkm_output_dp *outp = dp->outp; +- int ret, i; +- +- for (i = 0; i < dp->link_nr; i++) { +- u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; +- u8 lpc2 = (dp->pc2stat >> (i * 2)) & 0x3; +- u8 lpre = (lane & 0x0c) >> 2; +- u8 lvsw = (lane & 0x03) >> 0; +- u8 hivs = 3 - lpre; +- u8 hipe = 3; +- u8 hipc = 3; +- +- if (lpc2 >= hipc) +- lpc2 = hipc | DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED; +- if (lpre >= hipe) { +- lpre = hipe | DPCD_LC03_MAX_SWING_REACHED; /* yes. */ +- lvsw = hivs = 3 - (lpre & 3); +- } else +- if (lvsw >= hivs) { +- lvsw = hivs | DPCD_LC03_MAX_SWING_REACHED; +- } +- +- dp->conf[i] = (lpre << 3) | lvsw; +- dp->pc2conf[i >> 1] |= lpc2 << ((i & 1) * 4); +- +- DBG("config lane %d %02x %02x\n", i, dp->conf[i], lpc2); +- impl->drv_ctl(outp, i, lvsw & 3, lpre & 3, lpc2 & 3); +- } +- +- ret = nv_wraux(outp->base.edid, DPCD_LC03(0), dp->conf, 4); +- if (ret) +- return ret; +- +- if (pc) { +- ret = nv_wraux(outp->base.edid, DPCD_LC0F, dp->pc2conf, 2); +- if (ret) +- return ret; +- } +- +- return 0; +-} +- +-static int +-dp_link_train_update(struct dp_state *dp, bool pc, u32 delay) +-{ +- struct nvkm_output_dp *outp = dp->outp; +- int ret; +- +- if (outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) +- mdelay(outp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); +- else +- udelay(delay); +- +- ret = nv_rdaux(outp->base.edid, DPCD_LS02, dp->stat, 6); +- if (ret) +- return ret; +- +- if (pc) { +- ret = nv_rdaux(outp->base.edid, DPCD_LS0C, &dp->pc2stat, 1); +- if (ret) +- dp->pc2stat = 0x00; +- DBG("status %6ph pc2 %02x\n", dp->stat, dp->pc2stat); +- } else { +- DBG("status %6ph\n", dp->stat); +- } +- +- return 0; +-} +- +-static int +-dp_link_train_cr(struct dp_state *dp) +-{ +- bool cr_done = false, abort = false; +- int voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; +- int tries = 0, i; +- +- dp_set_training_pattern(dp, 1); +- +- do { +- if (dp_link_train_commit(dp, false) || +- dp_link_train_update(dp, false, 100)) +- break; +- +- cr_done = true; +- for (i = 0; i < dp->link_nr; i++) { +- u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; +- if (!(lane & DPCD_LS02_LANE0_CR_DONE)) { +- cr_done = false; +- if (dp->conf[i] & DPCD_LC03_MAX_SWING_REACHED) +- abort = true; +- break; +- } +- } +- +- if ((dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET) != voltage) { +- voltage = dp->conf[0] & DPCD_LC03_VOLTAGE_SWING_SET; +- tries = 0; +- } +- } while (!cr_done && !abort && ++tries < 5); +- +- return cr_done ? 0 : -1; +-} +- +-static int +-dp_link_train_eq(struct dp_state *dp) +-{ +- struct nvkm_output_dp *outp = dp->outp; +- bool eq_done = false, cr_done = true; +- int tries = 0, i; +- +- if (outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED) +- dp_set_training_pattern(dp, 3); +- else +- dp_set_training_pattern(dp, 2); +- +- do { +- if ((tries && +- dp_link_train_commit(dp, dp->pc2)) || +- dp_link_train_update(dp, dp->pc2, 400)) +- break; +- +- eq_done = !!(dp->stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE); +- for (i = 0; i < dp->link_nr && eq_done; i++) { +- u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; +- if (!(lane & DPCD_LS02_LANE0_CR_DONE)) +- cr_done = false; +- if (!(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || +- !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) +- eq_done = false; +- } +- } while (!eq_done && cr_done && ++tries <= 5); +- +- return eq_done ? 0 : -1; +-} +- +-static void +-dp_link_train_init(struct dp_state *dp, bool spread) +-{ +- struct nvkm_output_dp *outp = dp->outp; +- struct nouveau_disp *disp = nouveau_disp(outp); +- struct nouveau_bios *bios = nouveau_bios(disp); +- struct nvbios_init init = { +- .subdev = nv_subdev(disp), +- .bios = bios, +- .outp = &outp->base.info, +- .crtc = -1, +- .execute = 1, +- }; +- +- /* set desired spread */ +- if (spread) +- init.offset = outp->info.script[2]; +- else +- init.offset = outp->info.script[3]; +- nvbios_exec(&init); +- +- /* pre-train script */ +- init.offset = outp->info.script[0]; +- nvbios_exec(&init); +-} +- +-static void +-dp_link_train_fini(struct dp_state *dp) +-{ +- struct nvkm_output_dp *outp = dp->outp; +- struct nouveau_disp *disp = nouveau_disp(outp); +- struct nouveau_bios *bios = nouveau_bios(disp); +- struct nvbios_init init = { +- .subdev = nv_subdev(disp), +- .bios = bios, +- .outp = &outp->base.info, +- .crtc = -1, +- .execute = 1, +- }; +- +- /* post-train script */ +- init.offset = outp->info.script[1], +- nvbios_exec(&init); +-} +- +-static const struct dp_rates { +- u32 rate; +- u8 bw; +- u8 nr; +-} nouveau_dp_rates[] = { +- { 2160000, 0x14, 4 }, +- { 1080000, 0x0a, 4 }, +- { 1080000, 0x14, 2 }, +- { 648000, 0x06, 4 }, +- { 540000, 0x0a, 2 }, +- { 540000, 0x14, 1 }, +- { 324000, 0x06, 2 }, +- { 270000, 0x0a, 1 }, +- { 162000, 0x06, 1 }, +- {} +-}; +- +-void +-nouveau_dp_train(struct work_struct *w) +-{ +- struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work); +- struct nouveau_disp *disp = nouveau_disp(outp); +- const struct dp_rates *cfg = nouveau_dp_rates; +- struct dp_state _dp = { +- .outp = outp, +- }, *dp = &_dp; +- u32 datarate = 0; +- int ret; +- +- /* bring capabilities within encoder limits */ +- if (nv_mclass(disp) < GF110_DISP) +- outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; +- if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { +- outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; +- outp->dpcd[2] |= outp->base.info.dpconf.link_nr; +- } +- if (outp->dpcd[1] > outp->base.info.dpconf.link_bw) +- outp->dpcd[1] = outp->base.info.dpconf.link_bw; +- dp->pc2 = outp->dpcd[2] & DPCD_RC02_TPS3_SUPPORTED; +- +- /* restrict link config to the lowest required rate, if requested */ +- if (datarate) { +- datarate = (datarate / 8) * 10; /* 8B/10B coding overhead */ +- while (cfg[1].rate >= datarate) +- cfg++; +- } +- cfg--; +- +- /* disable link interrupt handling during link training */ +- nvkm_notify_put(&outp->irq); +- +- /* enable down-spreading and execute pre-train script from vbios */ +- dp_link_train_init(dp, outp->dpcd[3] & 0x01); +- +- while (ret = -EIO, (++cfg)->rate) { +- /* select next configuration supported by encoder and sink */ +- while (cfg->nr > (outp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT) || +- cfg->bw > (outp->dpcd[DPCD_RC01_MAX_LINK_RATE])) +- cfg++; +- dp->link_bw = cfg->bw * 27000; +- dp->link_nr = cfg->nr; +- +- /* program selected link configuration */ +- ret = dp_set_link_config(dp); +- if (ret == 0) { +- /* attempt to train the link at this configuration */ +- memset(dp->stat, 0x00, sizeof(dp->stat)); +- if (!dp_link_train_cr(dp) && +- !dp_link_train_eq(dp)) +- break; +- } else +- if (ret) { +- /* dp_set_link_config() handled training, or +- * we failed to communicate with the sink. +- */ +- break; +- } +- } +- +- /* finish link training and execute post-train script from vbios */ +- dp_set_training_pattern(dp, 0); +- if (ret < 0) +- ERR("link training failed\n"); +- +- dp_link_train_fini(dp); +- +- /* signal completion and enable link interrupt handling */ +- DBG("training complete\n"); +- atomic_set(&outp->lt.done, 1); +- wake_up(&outp->lt.wait); +- nvkm_notify_get(&outp->irq); +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h b/drivers/gpu/drm/nouveau/core/engine/disp/dport.h +deleted file mode 100644 +index 5628d2d5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/dport.h ++++ /dev/null +@@ -1,75 +0,0 @@ +-#ifndef __NVKM_DISP_DPORT_H__ +-#define __NVKM_DISP_DPORT_H__ +- +-/* DPCD Receiver Capabilities */ +-#define DPCD_RC00_DPCD_REV 0x00000 +-#define DPCD_RC01_MAX_LINK_RATE 0x00001 +-#define DPCD_RC02 0x00002 +-#define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 +-#define DPCD_RC02_TPS3_SUPPORTED 0x40 +-#define DPCD_RC02_MAX_LANE_COUNT 0x1f +-#define DPCD_RC03 0x00003 +-#define DPCD_RC03_MAX_DOWNSPREAD 0x01 +-#define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e +- +-/* DPCD Link Configuration */ +-#define DPCD_LC00_LINK_BW_SET 0x00100 +-#define DPCD_LC01 0x00101 +-#define DPCD_LC01_ENHANCED_FRAME_EN 0x80 +-#define DPCD_LC01_LANE_COUNT_SET 0x1f +-#define DPCD_LC02 0x00102 +-#define DPCD_LC02_TRAINING_PATTERN_SET 0x03 +-#define DPCD_LC03(l) ((l) + 0x00103) +-#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 +-#define DPCD_LC03_PRE_EMPHASIS_SET 0x18 +-#define DPCD_LC03_MAX_SWING_REACHED 0x04 +-#define DPCD_LC03_VOLTAGE_SWING_SET 0x03 +-#define DPCD_LC0F 0x0010f +-#define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 +-#define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 +-#define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 +-#define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 +-#define DPCD_LC10 0x00110 +-#define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 +-#define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 +-#define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 +-#define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 +- +-/* DPCD Link/Sink Status */ +-#define DPCD_LS02 0x00202 +-#define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 +-#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 +-#define DPCD_LS02_LANE1_CR_DONE 0x10 +-#define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 +-#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 +-#define DPCD_LS02_LANE0_CR_DONE 0x01 +-#define DPCD_LS03 0x00203 +-#define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 +-#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 +-#define DPCD_LS03_LANE3_CR_DONE 0x10 +-#define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 +-#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 +-#define DPCD_LS03_LANE2_CR_DONE 0x01 +-#define DPCD_LS04 0x00204 +-#define DPCD_LS04_LINK_STATUS_UPDATED 0x80 +-#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 +-#define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 +-#define DPCD_LS06 0x00206 +-#define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 +-#define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 +-#define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c +-#define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 +-#define DPCD_LS07 0x00207 +-#define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 +-#define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 +-#define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c +-#define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 +-#define DPCD_LS0C 0x0020c +-#define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 +-#define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 +-#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c +-#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 +- +-void nouveau_dp_train(struct work_struct *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c +deleted file mode 100644 +index b3df3fe2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/gm107.c ++++ /dev/null +@@ -1,107 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-gm107_disp_sclass[] = { +- { GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, +- { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, +- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, +- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, +- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-gm107_disp_base_oclass[] = { +- { GM107_DISP, &nvd0_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int heads = nv_rd32(parent, 0x022448); +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, heads, +- "PDISP", "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = gm107_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nvd0_disp_intr; +- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); +- priv->sclass = gm107_disp_sclass; +- priv->head.nr = heads; +- priv->dac.nr = 3; +- priv->sor.nr = 4; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hda_eld = nvd0_hda_eld; +- priv->sor.hdmi = nve0_hdmi_ctrl; +- return 0; +-} +- +-struct nouveau_oclass * +-gm107_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x07), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gm107_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nvd0_disp_vblank_func, +- .base.outp = nvd0_disp_outp_sclass, +- .mthd.core = &nve0_disp_mast_mthd_chan, +- .mthd.base = &nvd0_disp_sync_mthd_chan, +- .mthd.ovly = &nve0_disp_ovly_mthd_chan, +- .mthd.prev = -0x020000, +- .head.scanoutpos = nvd0_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c +deleted file mode 100644 +index fe9ef589..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanva3.c ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-int +-nva3_hda_eld(NV50_DISP_MTHD_V1) +-{ +- union { +- struct nv50_disp_sor_hda_eld_v0 v0; +- } *args = data; +- const u32 soff = outp->or * 0x800; +- int ret, i; +- +- nv_ioctl(object, "disp sor hda eld size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version); +- if (size > 0x60) +- return -E2BIG; +- } else +- return ret; +- +- if (size && args->v0.data[0]) { +- if (outp->info.type == DCB_OUTPUT_DP) { +- nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001); +- nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000); +- } +- for (i = 0; i < size; i++) +- nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]); +- for (; i < 0x60; i++) +- nv_wr32(priv, 0x61c440 + soff, (i << 8)); +- nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003); +- } else { +- if (outp->info.type == DCB_OUTPUT_DP) { +- nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000); +- nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000); +- } +- nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c +deleted file mode 100644 +index 1d4e8432..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdanvd0.c ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-int +-nvd0_hda_eld(NV50_DISP_MTHD_V1) +-{ +- union { +- struct nv50_disp_sor_hda_eld_v0 v0; +- } *args = data; +- const u32 soff = outp->or * 0x030; +- const u32 hoff = head * 0x800; +- int ret, i; +- +- nv_ioctl(object, "disp sor hda eld size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "disp sor hda eld vers %d\n", args->v0.version); +- if (size > 0x60) +- return -E2BIG; +- } else +- return ret; +- +- if (size && args->v0.data[0]) { +- if (outp->info.type == DCB_OUTPUT_DP) { +- nv_mask(priv, 0x616618 + hoff, 0x8000000c, 0x80000001); +- nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000); +- } +- nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000); +- for (i = 0; i < size; i++) +- nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); +- for (; i < 0x60; i++) +- nv_wr32(priv, 0x10ec00 + soff, (i << 8)); +- nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003); +- } else { +- if (outp->info.type == DCB_OUTPUT_DP) { +- nv_mask(priv, 0x616618 + hoff, 0x80000001, 0x80000000); +- nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000); +- } +- nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c +deleted file mode 100644 +index fa276ded..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nv84_hdmi_ctrl(NV50_DISP_MTHD_V1) +-{ +- const u32 hoff = (head * 0x800); +- union { +- struct nv50_disp_sor_hdmi_pwr_v0 v0; +- } *args = data; +- u32 ctrl; +- int ret; +- +- nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " +- "max_ac_packet %d rekey %d\n", +- args->v0.version, args->v0.state, +- args->v0.max_ac_packet, args->v0.rekey); +- if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) +- return -EINVAL; +- ctrl = 0x40000000 * !!args->v0.state; +- ctrl |= args->v0.max_ac_packet << 16; +- ctrl |= args->v0.rekey; +- ctrl |= 0x1f000000; /* ??? */ +- } else +- return ret; +- +- if (!(ctrl & 0x40000000)) { +- nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000); +- nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000); +- nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000); +- return 0; +- } +- +- /* AVI InfoFrame */ +- nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x616528 + hoff, 0x000d0282); +- nv_wr32(priv, 0x61652c + hoff, 0x0000006f); +- nv_wr32(priv, 0x616530 + hoff, 0x00000000); +- nv_wr32(priv, 0x616534 + hoff, 0x00000000); +- nv_wr32(priv, 0x616538 + hoff, 0x00000000); +- nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001); +- +- /* Audio InfoFrame */ +- nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x616508 + hoff, 0x000a0184); +- nv_wr32(priv, 0x61650c + hoff, 0x00000071); +- nv_wr32(priv, 0x616510 + hoff, 0x00000000); +- nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001); +- +- nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ +- nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ +- nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ +- +- /* ??? */ +- nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ +- nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ +- nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ +- +- /* HDMI_CTRL */ +- nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, ctrl); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c +deleted file mode 100644 +index 57eeed1d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminva3.c ++++ /dev/null +@@ -1,91 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nva3_hdmi_ctrl(NV50_DISP_MTHD_V1) +-{ +- const u32 soff = outp->or * 0x800; +- union { +- struct nv50_disp_sor_hdmi_pwr_v0 v0; +- } *args = data; +- u32 ctrl; +- int ret; +- +- nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " +- "max_ac_packet %d rekey %d\n", +- args->v0.version, args->v0.state, +- args->v0.max_ac_packet, args->v0.rekey); +- if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) +- return -EINVAL; +- ctrl = 0x40000000 * !!args->v0.state; +- ctrl |= args->v0.max_ac_packet << 16; +- ctrl |= args->v0.rekey; +- ctrl |= 0x1f000000; /* ??? */ +- } else +- return ret; +- +- if (!(ctrl & 0x40000000)) { +- nv_mask(priv, 0x61c5a4 + soff, 0x40000000, 0x00000000); +- nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000); +- nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000); +- return 0; +- } +- +- /* AVI InfoFrame */ +- nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x61c528 + soff, 0x000d0282); +- nv_wr32(priv, 0x61c52c + soff, 0x0000006f); +- nv_wr32(priv, 0x61c530 + soff, 0x00000000); +- nv_wr32(priv, 0x61c534 + soff, 0x00000000); +- nv_wr32(priv, 0x61c538 + soff, 0x00000000); +- nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000001); +- +- /* Audio InfoFrame */ +- nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x61c508 + soff, 0x000a0184); +- nv_wr32(priv, 0x61c50c + soff, 0x00000071); +- nv_wr32(priv, 0x61c510 + soff, 0x00000000); +- nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001); +- +- nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ +- nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ +- nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ +- +- /* ??? */ +- nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ +- nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ +- nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ +- +- /* HDMI_CTRL */ +- nv_mask(priv, 0x61c5a4 + soff, 0x5f1f007f, ctrl); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c +deleted file mode 100644 +index bac4fc45..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminvd0.c ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1) +-{ +- const u32 hoff = (head * 0x800); +- union { +- struct nv50_disp_sor_hdmi_pwr_v0 v0; +- } *args = data; +- u32 ctrl; +- int ret; +- +- nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " +- "max_ac_packet %d rekey %d\n", +- args->v0.version, args->v0.state, +- args->v0.max_ac_packet, args->v0.rekey); +- if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) +- return -EINVAL; +- ctrl = 0x40000000 * !!args->v0.state; +- ctrl |= args->v0.max_ac_packet << 16; +- ctrl |= args->v0.rekey; +- } else +- return ret; +- +- if (!(ctrl & 0x40000000)) { +- nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000); +- nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); +- nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); +- return 0; +- } +- +- /* AVI InfoFrame */ +- nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x61671c + hoff, 0x000d0282); +- nv_wr32(priv, 0x616720 + hoff, 0x0000006f); +- nv_wr32(priv, 0x616724 + hoff, 0x00000000); +- nv_wr32(priv, 0x616728 + hoff, 0x00000000); +- nv_wr32(priv, 0x61672c + hoff, 0x00000000); +- nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000001); +- +- /* ??? InfoFrame? */ +- nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x6167ac + hoff, 0x00000010); +- nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000001); +- +- /* HDMI_CTRL */ +- nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c +deleted file mode 100644 +index 528d14ec..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminve0.c ++++ /dev/null +@@ -1,83 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nve0_hdmi_ctrl(NV50_DISP_MTHD_V1) +-{ +- const u32 hoff = (head * 0x800); +- const u32 hdmi = (head * 0x400); +- union { +- struct nv50_disp_sor_hdmi_pwr_v0 v0; +- } *args = data; +- u32 ctrl; +- int ret; +- +- nv_ioctl(object, "disp sor hdmi ctrl size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor hdmi ctrl vers %d state %d " +- "max_ac_packet %d rekey %d\n", +- args->v0.version, args->v0.state, +- args->v0.max_ac_packet, args->v0.rekey); +- if (args->v0.max_ac_packet > 0x1f || args->v0.rekey > 0x7f) +- return -EINVAL; +- ctrl = 0x40000000 * !!args->v0.state; +- ctrl |= args->v0.max_ac_packet << 16; +- ctrl |= args->v0.rekey; +- } else +- return ret; +- +- if (!(ctrl & 0x40000000)) { +- nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000); +- nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000); +- nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000); +- return 0; +- } +- +- /* AVI InfoFrame */ +- nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x690008 + hdmi, 0x000d0282); +- nv_wr32(priv, 0x69000c + hdmi, 0x0000006f); +- nv_wr32(priv, 0x690010 + hdmi, 0x00000000); +- nv_wr32(priv, 0x690014 + hdmi, 0x00000000); +- nv_wr32(priv, 0x690018 + hdmi, 0x00000000); +- nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000001); +- +- /* ??? InfoFrame? */ +- nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000); +- nv_wr32(priv, 0x6900cc + hdmi, 0x00000010); +- nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000001); +- +- /* ??? */ +- nv_wr32(priv, 0x690080 + hdmi, 0x82000000); +- +- /* HDMI_CTRL */ +- nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c +deleted file mode 100644 +index 366f315f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv04.c ++++ /dev/null +@@ -1,205 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-#include +-#include +-#include +-#include +- +-struct nv04_disp_priv { +- struct nouveau_disp base; +-}; +- +-static int +-nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv, +- void *data, u32 size, int head) +-{ +- const u32 hoff = head * 0x2000; +- union { +- struct nv04_disp_scanoutpos_v0 v0; +- } *args = data; +- u32 line; +- int ret; +- +- nv_ioctl(object, "disp scanoutpos size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); +- args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff; +- args->v0.vtotal = nv_rd32(priv, 0x680804 + hoff) & 0xffff; +- args->v0.vblanke = args->v0.vtotal - 1; +- +- args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff; +- args->v0.htotal = nv_rd32(priv, 0x680824 + hoff) & 0xffff; +- args->v0.hblanke = args->v0.htotal - 1; +- +- /* +- * If output is vga instead of digital then vtotal/htotal is +- * invalid so we have to give up and trigger the timestamping +- * fallback in the drm core. +- */ +- if (!args->v0.vtotal || !args->v0.htotal) +- return -ENOTSUPP; +- +- args->v0.time[0] = ktime_to_ns(ktime_get()); +- line = nv_rd32(priv, 0x600868 + hoff); +- args->v0.time[1] = ktime_to_ns(ktime_get()); +- args->v0.hline = (line & 0xffff0000) >> 16; +- args->v0.vline = (line & 0x0000ffff); +- } else +- return ret; +- +- return 0; +-} +- +-static int +-nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) +-{ +- union { +- struct nv04_disp_mthd_v0 v0; +- } *args = data; +- struct nv04_disp_priv *priv = (void *)object->engine; +- int head, ret; +- +- nv_ioctl(object, "disp mthd size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "disp mthd vers %d mthd %02x head %d\n", +- args->v0.version, args->v0.method, args->v0.head); +- mthd = args->v0.method; +- head = args->v0.head; +- } else +- return ret; +- +- if (head < 0 || head >= 2) +- return -ENXIO; +- +- switch (mthd) { +- case NV04_DISP_SCANOUTPOS: +- return nv04_disp_scanoutpos(object, priv, data, size, head); +- default: +- break; +- } +- +- return -EINVAL; +-} +- +-static struct nouveau_ofuncs +-nv04_disp_ofuncs = { +- .ctor = _nouveau_object_ctor, +- .dtor = nouveau_object_destroy, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- .mthd = nv04_disp_mthd, +- .ntfy = nouveau_disp_ntfy, +-}; +- +-static struct nouveau_oclass +-nv04_disp_sclass[] = { +- { NV04_DISP, &nv04_disp_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static void +-nv04_disp_vblank_init(struct nvkm_event *event, int type, int head) +-{ +- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); +- nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001); +-} +- +-static void +-nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head) +-{ +- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); +- nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000); +-} +- +-static const struct nvkm_event_func +-nv04_disp_vblank_func = { +- .ctor = nouveau_disp_vblank_ctor, +- .init = nv04_disp_vblank_init, +- .fini = nv04_disp_vblank_fini, +-}; +- +-static void +-nv04_disp_intr(struct nouveau_subdev *subdev) +-{ +- struct nv04_disp_priv *priv = (void *)subdev; +- u32 crtc0 = nv_rd32(priv, 0x600100); +- u32 crtc1 = nv_rd32(priv, 0x602100); +- u32 pvideo; +- +- if (crtc0 & 0x00000001) { +- nouveau_disp_vblank(&priv->base, 0); +- nv_wr32(priv, 0x600100, 0x00000001); +- } +- +- if (crtc1 & 0x00000001) { +- nouveau_disp_vblank(&priv->base, 1); +- nv_wr32(priv, 0x602100, 0x00000001); +- } +- +- if (nv_device(priv)->chipset >= 0x10 && +- nv_device(priv)->chipset <= 0x40) { +- pvideo = nv_rd32(priv, 0x8100); +- if (pvideo & ~0x11) +- nv_info(priv, "PVIDEO intr: %08x\n", pvideo); +- nv_wr32(priv, 0x8100, pvideo); +- } +-} +- +-static int +-nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_disp_priv *priv; +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY", +- "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nv04_disp_sclass; +- nv_subdev(priv)->intr = nv04_disp_intr; +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_disp_oclass = &(struct nouveau_disp_impl) { +- .base.handle = NV_ENGINE(DISP, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .vblank = &nv04_disp_vblank_func, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c +deleted file mode 100644 +index 2df3a937..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c ++++ /dev/null +@@ -1,2015 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * EVO channel base class +- ******************************************************************************/ +- +-static int +-nv50_disp_chan_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int head, +- int length, void **pobject) +-{ +- const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs; +- struct nv50_disp_base *base = (void *)parent; +- struct nv50_disp_chan *chan; +- int chid = impl->chid + head; +- int ret; +- +- if (base->chan & (1 << chid)) +- return -EBUSY; +- base->chan |= (1 << chid); +- +- ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, +- (1ULL << NVDEV_ENGINE_DMAOBJ), +- length, pobject); +- chan = *pobject; +- if (ret) +- return ret; +- chan->chid = chid; +- +- nv_parent(chan)->object_attach = impl->attach; +- nv_parent(chan)->object_detach = impl->detach; +- return 0; +-} +- +-static void +-nv50_disp_chan_destroy(struct nv50_disp_chan *chan) +-{ +- struct nv50_disp_base *base = (void *)nv_object(chan)->parent; +- base->chan &= ~(1 << chan->chid); +- nouveau_namedb_destroy(&chan->base); +-} +- +-static void +-nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); +- nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index); +-} +- +-static void +-nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) +-{ +- struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); +- nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index); +-} +- +-void +-nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid) +-{ +- struct nvif_notify_uevent_rep { +- } rep; +- +- nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep)); +-} +- +-int +-nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- struct nv50_disp_dmac *dmac = (void *)object; +- union { +- struct nvif_notify_uevent_req none; +- } *args = data; +- int ret; +- +- if (nvif_unvers(args->none)) { +- notify->size = sizeof(struct nvif_notify_uevent_rep); +- notify->types = 1; +- notify->index = dmac->base.chid; +- return 0; +- } +- +- return ret; +-} +- +-const struct nvkm_event_func +-nv50_disp_chan_uevent = { +- .ctor = nv50_disp_chan_uevent_ctor, +- .init = nv50_disp_chan_uevent_init, +- .fini = nv50_disp_chan_uevent_fini, +-}; +- +-int +-nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type, +- struct nvkm_event **pevent) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- switch (type) { +- case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT: +- *pevent = &priv->uevent; +- return 0; +- default: +- break; +- } +- return -EINVAL; +-} +- +-int +-nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size) +-{ +- struct nv50_disp_chan *chan = (void *)object; +- *addr = nv_device_resource_start(nv_device(object), 0) + +- 0x640000 + (chan->chid * 0x1000); +- *size = 0x001000; +- return 0; +-} +- +-u32 +-nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_chan *chan = (void *)object; +- return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); +-} +- +-void +-nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_chan *chan = (void *)object; +- nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); +-} +- +-/******************************************************************************* +- * EVO DMA channel base class +- ******************************************************************************/ +- +-static int +-nv50_disp_dmac_object_attach(struct nouveau_object *parent, +- struct nouveau_object *object, u32 name) +-{ +- struct nv50_disp_base *base = (void *)parent->parent; +- struct nv50_disp_chan *chan = (void *)parent; +- u32 addr = nv_gpuobj(object)->node->offset; +- u32 chid = chan->chid; +- u32 data = (chid << 28) | (addr << 10) | chid; +- return nouveau_ramht_insert(base->ramht, chid, name, data); +-} +- +-static void +-nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie) +-{ +- struct nv50_disp_base *base = (void *)parent->parent; +- nouveau_ramht_remove(base->ramht, cookie); +-} +- +-static int +-nv50_disp_dmac_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 pushbuf, int head, +- int length, void **pobject) +-{ +- struct nv50_disp_dmac *dmac; +- int ret; +- +- ret = nv50_disp_chan_create_(parent, engine, oclass, head, +- length, pobject); +- dmac = *pobject; +- if (ret) +- return ret; +- +- dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); +- if (!dmac->pushdma) +- return -ENOENT; +- +- switch (nv_mclass(dmac->pushdma)) { +- case 0x0002: +- case 0x003d: +- if (dmac->pushdma->limit - dmac->pushdma->start != 0xfff) +- return -EINVAL; +- +- switch (dmac->pushdma->target) { +- case NV_MEM_TARGET_VRAM: +- dmac->push = 0x00000000 | dmac->pushdma->start >> 8; +- break; +- case NV_MEM_TARGET_PCI_NOSNOOP: +- dmac->push = 0x00000003 | dmac->pushdma->start >> 8; +- break; +- default: +- return -EINVAL; +- } +- break; +- default: +- return -EINVAL; +- } +- +- return 0; +-} +- +-void +-nv50_disp_dmac_dtor(struct nouveau_object *object) +-{ +- struct nv50_disp_dmac *dmac = (void *)object; +- nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma); +- nv50_disp_chan_destroy(&dmac->base); +-} +- +-static int +-nv50_disp_dmac_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *dmac = (void *)object; +- int chid = dmac->base.chid; +- int ret; +- +- ret = nv50_disp_chan_init(&dmac->base); +- if (ret) +- return ret; +- +- /* enable error reporting */ +- nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid); +- +- /* initialise channel for dma command submission */ +- nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); +- nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); +- nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); +- nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); +- nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); +- nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); +- +- /* wait for it to go inactive */ +- if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { +- nv_error(dmac, "init timeout, 0x%08x\n", +- nv_rd32(priv, 0x610200 + (chid * 0x10))); +- return -EBUSY; +- } +- +- return 0; +-} +- +-static int +-nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *dmac = (void *)object; +- int chid = dmac->base.chid; +- +- /* deactivate channel */ +- nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); +- nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); +- if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { +- nv_error(dmac, "fini timeout, 0x%08x\n", +- nv_rd32(priv, 0x610200 + (chid * 0x10))); +- if (suspend) +- return -EBUSY; +- } +- +- /* disable error reporting and completion notifications */ +- nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); +- +- return nv50_disp_chan_fini(&dmac->base, suspend); +-} +- +-/******************************************************************************* +- * EVO master channel object +- ******************************************************************************/ +- +-static void +-nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, +- const struct nv50_disp_mthd_list *list, int inst) +-{ +- struct nouveau_object *disp = nv_object(priv); +- int i; +- +- for (i = 0; list->data[i].mthd; i++) { +- if (list->data[i].addr) { +- u32 next = nv_rd32(priv, list->data[i].addr + base + 0); +- u32 prev = nv_rd32(priv, list->data[i].addr + base + c); +- u32 mthd = list->data[i].mthd + (list->mthd * inst); +- const char *name = list->data[i].name; +- char mods[16]; +- +- if (prev != next) +- snprintf(mods, sizeof(mods), "-> 0x%08x", next); +- else +- snprintf(mods, sizeof(mods), "%13c", ' '); +- +- nv_printk_(disp, debug, "\t0x%04x: 0x%08x %s%s%s\n", +- mthd, prev, mods, name ? " // " : "", +- name ? name : ""); +- } +- } +-} +- +-void +-nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, +- const struct nv50_disp_mthd_chan *chan) +-{ +- struct nouveau_object *disp = nv_object(priv); +- const struct nv50_disp_impl *impl = (void *)disp->oclass; +- const struct nv50_disp_mthd_list *list; +- int i, j; +- +- if (debug > nv_subdev(priv)->debug) +- return; +- +- for (i = 0; (list = chan->data[i].mthd) != NULL; i++) { +- u32 base = head * chan->addr; +- for (j = 0; j < chan->data[i].nr; j++, base += list->addr) { +- const char *cname = chan->name; +- const char *sname = ""; +- char cname_[16], sname_[16]; +- +- if (chan->addr) { +- snprintf(cname_, sizeof(cname_), "%s %d", +- chan->name, head); +- cname = cname_; +- } +- +- if (chan->data[i].nr > 1) { +- snprintf(sname_, sizeof(sname_), " - %s %d", +- chan->data[i].name, j); +- sname = sname_; +- } +- +- nv_printk_(disp, debug, "%s%s:\n", cname, sname); +- nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev, +- list, j); +- } +- } +-} +- +-const struct nv50_disp_mthd_list +-nv50_disp_mast_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x000000 }, +- { 0x0084, 0x610bb8 }, +- { 0x0088, 0x610b9c }, +- { 0x008c, 0x000000 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_list +-nv50_disp_mast_mthd_dac = { +- .mthd = 0x0080, +- .addr = 0x000008, +- .data = { +- { 0x0400, 0x610b58 }, +- { 0x0404, 0x610bdc }, +- { 0x0420, 0x610828 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nv50_disp_mast_mthd_sor = { +- .mthd = 0x0040, +- .addr = 0x000008, +- .data = { +- { 0x0600, 0x610b70 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nv50_disp_mast_mthd_pior = { +- .mthd = 0x0040, +- .addr = 0x000008, +- .data = { +- { 0x0700, 0x610b80 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_list +-nv50_disp_mast_mthd_head = { +- .mthd = 0x0400, +- .addr = 0x000540, +- .data = { +- { 0x0800, 0x610ad8 }, +- { 0x0804, 0x610ad0 }, +- { 0x0808, 0x610a48 }, +- { 0x080c, 0x610a78 }, +- { 0x0810, 0x610ac0 }, +- { 0x0814, 0x610af8 }, +- { 0x0818, 0x610b00 }, +- { 0x081c, 0x610ae8 }, +- { 0x0820, 0x610af0 }, +- { 0x0824, 0x610b08 }, +- { 0x0828, 0x610b10 }, +- { 0x082c, 0x610a68 }, +- { 0x0830, 0x610a60 }, +- { 0x0834, 0x000000 }, +- { 0x0838, 0x610a40 }, +- { 0x0840, 0x610a24 }, +- { 0x0844, 0x610a2c }, +- { 0x0848, 0x610aa8 }, +- { 0x084c, 0x610ab0 }, +- { 0x0860, 0x610a84 }, +- { 0x0864, 0x610a90 }, +- { 0x0868, 0x610b18 }, +- { 0x086c, 0x610b20 }, +- { 0x0870, 0x610ac8 }, +- { 0x0874, 0x610a38 }, +- { 0x0880, 0x610a58 }, +- { 0x0884, 0x610a9c }, +- { 0x08a0, 0x610a70 }, +- { 0x08a4, 0x610a50 }, +- { 0x08a8, 0x610ae0 }, +- { 0x08c0, 0x610b28 }, +- { 0x08c4, 0x610b30 }, +- { 0x08c8, 0x610b40 }, +- { 0x08d4, 0x610b38 }, +- { 0x08d8, 0x610b48 }, +- { 0x08dc, 0x610b50 }, +- { 0x0900, 0x610a18 }, +- { 0x0904, 0x610ab8 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_chan +-nv50_disp_mast_mthd_chan = { +- .name = "Core", +- .addr = 0x000000, +- .data = { +- { "Global", 1, &nv50_disp_mast_mthd_base }, +- { "DAC", 3, &nv50_disp_mast_mthd_dac }, +- { "SOR", 2, &nv50_disp_mast_mthd_sor }, +- { "PIOR", 3, &nv50_disp_mast_mthd_pior }, +- { "HEAD", 2, &nv50_disp_mast_mthd_head }, +- {} +- } +-}; +- +-int +-nv50_disp_mast_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_disp_core_channel_dma_v0 v0; +- } *args = data; +- struct nv50_disp_dmac *mast; +- int ret; +- +- nv_ioctl(parent, "create disp core channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create disp core channel dma vers %d " +- "pushbuf %08x\n", +- args->v0.version, args->v0.pushbuf); +- } else +- return ret; +- +- ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, +- 0, sizeof(*mast), (void **)&mast); +- *pobject = nv_object(mast); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static int +-nv50_disp_mast_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *mast = (void *)object; +- int ret; +- +- ret = nv50_disp_chan_init(&mast->base); +- if (ret) +- return ret; +- +- /* enable error reporting */ +- nv_mask(priv, 0x610028, 0x00010000, 0x00010000); +- +- /* attempt to unstick channel from some unknown state */ +- if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000) +- nv_mask(priv, 0x610200, 0x00800000, 0x00800000); +- if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000) +- nv_mask(priv, 0x610200, 0x00600000, 0x00600000); +- +- /* initialise channel for dma command submission */ +- nv_wr32(priv, 0x610204, mast->push); +- nv_wr32(priv, 0x610208, 0x00010000); +- nv_wr32(priv, 0x61020c, 0x00000000); +- nv_mask(priv, 0x610200, 0x00000010, 0x00000010); +- nv_wr32(priv, 0x640000, 0x00000000); +- nv_wr32(priv, 0x610200, 0x01000013); +- +- /* wait for it to go inactive */ +- if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) { +- nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); +- return -EBUSY; +- } +- +- return 0; +-} +- +-static int +-nv50_disp_mast_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *mast = (void *)object; +- +- /* deactivate channel */ +- nv_mask(priv, 0x610200, 0x00000010, 0x00000000); +- nv_mask(priv, 0x610200, 0x00000003, 0x00000000); +- if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) { +- nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); +- if (suspend) +- return -EBUSY; +- } +- +- /* disable error reporting and completion notifications */ +- nv_mask(priv, 0x610028, 0x00010001, 0x00000000); +- +- return nv50_disp_chan_fini(&mast->base, suspend); +-} +- +-struct nv50_disp_chan_impl +-nv50_disp_mast_ofuncs = { +- .base.ctor = nv50_disp_mast_ctor, +- .base.dtor = nv50_disp_dmac_dtor, +- .base.init = nv50_disp_mast_init, +- .base.fini = nv50_disp_mast_fini, +- .base.map = nv50_disp_chan_map, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 0, +- .attach = nv50_disp_dmac_object_attach, +- .detach = nv50_disp_dmac_object_detach, +-}; +- +-/******************************************************************************* +- * EVO sync channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nv50_disp_sync_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x000000 }, +- { 0x0084, 0x0008c4 }, +- { 0x0088, 0x0008d0 }, +- { 0x008c, 0x0008dc }, +- { 0x0090, 0x0008e4 }, +- { 0x0094, 0x610884 }, +- { 0x00a0, 0x6108a0 }, +- { 0x00a4, 0x610878 }, +- { 0x00c0, 0x61086c }, +- { 0x00e0, 0x610858 }, +- { 0x00e4, 0x610860 }, +- { 0x00e8, 0x6108ac }, +- { 0x00ec, 0x6108b4 }, +- { 0x0100, 0x610894 }, +- { 0x0110, 0x6108bc }, +- { 0x0114, 0x61088c }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nv50_disp_sync_mthd_image = { +- .mthd = 0x0400, +- .addr = 0x000000, +- .data = { +- { 0x0800, 0x6108f0 }, +- { 0x0804, 0x6108fc }, +- { 0x0808, 0x61090c }, +- { 0x080c, 0x610914 }, +- { 0x0810, 0x610904 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_chan +-nv50_disp_sync_mthd_chan = { +- .name = "Base", +- .addr = 0x000540, +- .data = { +- { "Global", 1, &nv50_disp_sync_mthd_base }, +- { "Image", 2, &nv50_disp_sync_mthd_image }, +- {} +- } +-}; +- +-int +-nv50_disp_sync_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_disp_base_channel_dma_v0 v0; +- } *args = data; +- struct nv50_disp_priv *priv = (void *)engine; +- struct nv50_disp_dmac *dmac; +- int ret; +- +- nv_ioctl(parent, "create disp base channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create disp base channel dma vers %d " +- "pushbuf %08x head %d\n", +- args->v0.version, args->v0.pushbuf, args->v0.head); +- if (args->v0.head > priv->head.nr) +- return -EINVAL; +- } else +- return ret; +- +- ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, +- args->v0.head, sizeof(*dmac), +- (void **)&dmac); +- *pobject = nv_object(dmac); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nv50_disp_chan_impl +-nv50_disp_sync_ofuncs = { +- .base.ctor = nv50_disp_sync_ctor, +- .base.dtor = nv50_disp_dmac_dtor, +- .base.init = nv50_disp_dmac_init, +- .base.fini = nv50_disp_dmac_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 1, +- .attach = nv50_disp_dmac_object_attach, +- .detach = nv50_disp_dmac_object_detach, +-}; +- +-/******************************************************************************* +- * EVO overlay channel objects +- ******************************************************************************/ +- +-const struct nv50_disp_mthd_list +-nv50_disp_ovly_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x000000 }, +- { 0x0084, 0x0009a0 }, +- { 0x0088, 0x0009c0 }, +- { 0x008c, 0x0009c8 }, +- { 0x0090, 0x6109b4 }, +- { 0x0094, 0x610970 }, +- { 0x00a0, 0x610998 }, +- { 0x00a4, 0x610964 }, +- { 0x00c0, 0x610958 }, +- { 0x00e0, 0x6109a8 }, +- { 0x00e4, 0x6109d0 }, +- { 0x00e8, 0x6109d8 }, +- { 0x0100, 0x61094c }, +- { 0x0104, 0x610984 }, +- { 0x0108, 0x61098c }, +- { 0x0800, 0x6109f8 }, +- { 0x0808, 0x610a08 }, +- { 0x080c, 0x610a10 }, +- { 0x0810, 0x610a00 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_chan +-nv50_disp_ovly_mthd_chan = { +- .name = "Overlay", +- .addr = 0x000540, +- .data = { +- { "Global", 1, &nv50_disp_ovly_mthd_base }, +- {} +- } +-}; +- +-int +-nv50_disp_ovly_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_disp_overlay_channel_dma_v0 v0; +- } *args = data; +- struct nv50_disp_priv *priv = (void *)engine; +- struct nv50_disp_dmac *dmac; +- int ret; +- +- nv_ioctl(parent, "create disp overlay channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create disp overlay channel dma vers %d " +- "pushbuf %08x head %d\n", +- args->v0.version, args->v0.pushbuf, args->v0.head); +- if (args->v0.head > priv->head.nr) +- return -EINVAL; +- } else +- return ret; +- +- ret = nv50_disp_dmac_create_(parent, engine, oclass, args->v0.pushbuf, +- args->v0.head, sizeof(*dmac), +- (void **)&dmac); +- *pobject = nv_object(dmac); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nv50_disp_chan_impl +-nv50_disp_ovly_ofuncs = { +- .base.ctor = nv50_disp_ovly_ctor, +- .base.dtor = nv50_disp_dmac_dtor, +- .base.init = nv50_disp_dmac_init, +- .base.fini = nv50_disp_dmac_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 3, +- .attach = nv50_disp_dmac_object_attach, +- .detach = nv50_disp_dmac_object_detach, +-}; +- +-/******************************************************************************* +- * EVO PIO channel base class +- ******************************************************************************/ +- +-static int +-nv50_disp_pioc_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int head, +- int length, void **pobject) +-{ +- return nv50_disp_chan_create_(parent, engine, oclass, head, +- length, pobject); +-} +- +-void +-nv50_disp_pioc_dtor(struct nouveau_object *object) +-{ +- struct nv50_disp_pioc *pioc = (void *)object; +- nv50_disp_chan_destroy(&pioc->base); +-} +- +-static int +-nv50_disp_pioc_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_pioc *pioc = (void *)object; +- int chid = pioc->base.chid; +- int ret; +- +- ret = nv50_disp_chan_init(&pioc->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000); +- if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { +- nv_error(pioc, "timeout0: 0x%08x\n", +- nv_rd32(priv, 0x610200 + (chid * 0x10))); +- return -EBUSY; +- } +- +- nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001); +- if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { +- nv_error(pioc, "timeout1: 0x%08x\n", +- nv_rd32(priv, 0x610200 + (chid * 0x10))); +- return -EBUSY; +- } +- +- return 0; +-} +- +-static int +-nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_pioc *pioc = (void *)object; +- int chid = pioc->base.chid; +- +- nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); +- if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { +- nv_error(pioc, "timeout: 0x%08x\n", +- nv_rd32(priv, 0x610200 + (chid * 0x10))); +- if (suspend) +- return -EBUSY; +- } +- +- return nv50_disp_chan_fini(&pioc->base, suspend); +-} +- +-/******************************************************************************* +- * EVO immediate overlay channel objects +- ******************************************************************************/ +- +-int +-nv50_disp_oimm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_disp_overlay_v0 v0; +- } *args = data; +- struct nv50_disp_priv *priv = (void *)engine; +- struct nv50_disp_pioc *pioc; +- int ret; +- +- nv_ioctl(parent, "create disp overlay size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create disp overlay vers %d head %d\n", +- args->v0.version, args->v0.head); +- if (args->v0.head > priv->head.nr) +- return -EINVAL; +- } else +- return ret; +- +- ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, +- sizeof(*pioc), (void **)&pioc); +- *pobject = nv_object(pioc); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nv50_disp_chan_impl +-nv50_disp_oimm_ofuncs = { +- .base.ctor = nv50_disp_oimm_ctor, +- .base.dtor = nv50_disp_pioc_dtor, +- .base.init = nv50_disp_pioc_init, +- .base.fini = nv50_disp_pioc_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 5, +-}; +- +-/******************************************************************************* +- * EVO cursor channel objects +- ******************************************************************************/ +- +-int +-nv50_disp_curs_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_disp_cursor_v0 v0; +- } *args = data; +- struct nv50_disp_priv *priv = (void *)engine; +- struct nv50_disp_pioc *pioc; +- int ret; +- +- nv_ioctl(parent, "create disp cursor size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create disp cursor vers %d head %d\n", +- args->v0.version, args->v0.head); +- if (args->v0.head > priv->head.nr) +- return -EINVAL; +- } else +- return ret; +- +- ret = nv50_disp_pioc_create_(parent, engine, oclass, args->v0.head, +- sizeof(*pioc), (void **)&pioc); +- *pobject = nv_object(pioc); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nv50_disp_chan_impl +-nv50_disp_curs_ofuncs = { +- .base.ctor = nv50_disp_curs_ctor, +- .base.dtor = nv50_disp_pioc_dtor, +- .base.init = nv50_disp_pioc_init, +- .base.fini = nv50_disp_pioc_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 7, +-}; +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-int +-nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0) +-{ +- const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540)); +- const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540)); +- const u32 total = nv_rd32(priv, 0x610afc + (head * 0x540)); +- union { +- struct nv04_disp_scanoutpos_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "disp scanoutpos size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); +- args->v0.vblanke = (blanke & 0xffff0000) >> 16; +- args->v0.hblanke = (blanke & 0x0000ffff); +- args->v0.vblanks = (blanks & 0xffff0000) >> 16; +- args->v0.hblanks = (blanks & 0x0000ffff); +- args->v0.vtotal = ( total & 0xffff0000) >> 16; +- args->v0.htotal = ( total & 0x0000ffff); +- args->v0.time[0] = ktime_to_ns(ktime_get()); +- args->v0.vline = /* vline read locks hline */ +- nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; +- args->v0.time[1] = ktime_to_ns(ktime_get()); +- args->v0.hline = +- nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff; +- } else +- return ret; +- +- return 0; +-} +- +-int +-nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd, +- void *data, u32 size) +-{ +- const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine); +- union { +- struct nv50_disp_mthd_v0 v0; +- struct nv50_disp_mthd_v1 v1; +- } *args = data; +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nvkm_output *outp = NULL; +- struct nvkm_output *temp; +- u16 type, mask = 0; +- int head, ret; +- +- if (mthd != NV50_DISP_MTHD) +- return -EINVAL; +- +- nv_ioctl(object, "disp mthd size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(object, "disp mthd vers %d mthd %02x head %d\n", +- args->v0.version, args->v0.method, args->v0.head); +- mthd = args->v0.method; +- head = args->v0.head; +- } else +- if (nvif_unpack(args->v1, 1, 1, true)) { +- nv_ioctl(object, "disp mthd vers %d mthd %02x " +- "type %04x mask %04x\n", +- args->v1.version, args->v1.method, +- args->v1.hasht, args->v1.hashm); +- mthd = args->v1.method; +- type = args->v1.hasht; +- mask = args->v1.hashm; +- head = ffs((mask >> 8) & 0x0f) - 1; +- } else +- return ret; +- +- if (head < 0 || head >= priv->head.nr) +- return -ENXIO; +- +- if (mask) { +- list_for_each_entry(temp, &priv->base.outp, head) { +- if ((temp->info.hasht == type) && +- (temp->info.hashm & mask) == mask) { +- outp = temp; +- break; +- } +- } +- if (outp == NULL) +- return -ENXIO; +- } +- +- switch (mthd) { +- case NV50_DISP_SCANOUTPOS: +- return impl->head.scanoutpos(object, priv, data, size, head); +- default: +- break; +- } +- +- switch (mthd * !!outp) { +- case NV50_DISP_MTHD_V1_DAC_PWR: +- return priv->dac.power(object, priv, data, size, head, outp); +- case NV50_DISP_MTHD_V1_DAC_LOAD: +- return priv->dac.sense(object, priv, data, size, head, outp); +- case NV50_DISP_MTHD_V1_SOR_PWR: +- return priv->sor.power(object, priv, data, size, head, outp); +- case NV50_DISP_MTHD_V1_SOR_HDA_ELD: +- if (!priv->sor.hda_eld) +- return -ENODEV; +- return priv->sor.hda_eld(object, priv, data, size, head, outp); +- case NV50_DISP_MTHD_V1_SOR_HDMI_PWR: +- if (!priv->sor.hdmi) +- return -ENODEV; +- return priv->sor.hdmi(object, priv, data, size, head, outp); +- case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: { +- union { +- struct nv50_disp_sor_lvds_script_v0 v0; +- } *args = data; +- nv_ioctl(object, "disp sor lvds script size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor lvds script " +- "vers %d name %04x\n", +- args->v0.version, args->v0.script); +- priv->sor.lvdsconf = args->v0.script; +- return 0; +- } else +- return ret; +- } +- break; +- case NV50_DISP_MTHD_V1_SOR_DP_PWR: { +- struct nvkm_output_dp *outpdp = (void *)outp; +- union { +- struct nv50_disp_sor_dp_pwr_v0 v0; +- } *args = data; +- nv_ioctl(object, "disp sor dp pwr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor dp pwr vers %d state %d\n", +- args->v0.version, args->v0.state); +- if (args->v0.state == 0) { +- nvkm_notify_put(&outpdp->irq); +- ((struct nvkm_output_dp_impl *)nv_oclass(outp)) +- ->lnk_pwr(outpdp, 0); +- atomic_set(&outpdp->lt.done, 0); +- return 0; +- } else +- if (args->v0.state != 0) { +- nvkm_output_dp_train(&outpdp->base, 0, true); +- return 0; +- } +- } else +- return ret; +- } +- break; +- case NV50_DISP_MTHD_V1_PIOR_PWR: +- if (!priv->pior.power) +- return -ENODEV; +- return priv->pior.power(object, priv, data, size, head, outp); +- default: +- break; +- } +- +- return -EINVAL; +-} +- +-int +-nv50_disp_base_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv = (void *)engine; +- struct nv50_disp_base *base; +- int ret; +- +- ret = nouveau_parent_create(parent, engine, oclass, 0, +- priv->sclass, 0, &base); +- *pobject = nv_object(base); +- if (ret) +- return ret; +- +- return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0, +- &base->ramht); +-} +- +-void +-nv50_disp_base_dtor(struct nouveau_object *object) +-{ +- struct nv50_disp_base *base = (void *)object; +- nouveau_ramht_ref(NULL, &base->ramht); +- nouveau_parent_destroy(&base->base); +-} +- +-static int +-nv50_disp_base_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_base *base = (void *)object; +- int ret, i; +- u32 tmp; +- +- ret = nouveau_parent_init(&base->base); +- if (ret) +- return ret; +- +- /* The below segments of code copying values from one register to +- * another appear to inform EVO of the display capabilities or +- * something similar. NFI what the 0x614004 caps are for.. +- */ +- tmp = nv_rd32(priv, 0x614004); +- nv_wr32(priv, 0x610184, tmp); +- +- /* ... CRTC caps */ +- for (i = 0; i < priv->head.nr; i++) { +- tmp = nv_rd32(priv, 0x616100 + (i * 0x800)); +- nv_wr32(priv, 0x610190 + (i * 0x10), tmp); +- tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); +- nv_wr32(priv, 0x610194 + (i * 0x10), tmp); +- tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); +- nv_wr32(priv, 0x610198 + (i * 0x10), tmp); +- tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); +- nv_wr32(priv, 0x61019c + (i * 0x10), tmp); +- } +- +- /* ... DAC caps */ +- for (i = 0; i < priv->dac.nr; i++) { +- tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); +- nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp); +- } +- +- /* ... SOR caps */ +- for (i = 0; i < priv->sor.nr; i++) { +- tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); +- nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp); +- } +- +- /* ... PIOR caps */ +- for (i = 0; i < priv->pior.nr; i++) { +- tmp = nv_rd32(priv, 0x61e000 + (i * 0x800)); +- nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp); +- } +- +- /* steal display away from vbios, or something like that */ +- if (nv_rd32(priv, 0x610024) & 0x00000100) { +- nv_wr32(priv, 0x610024, 0x00000100); +- nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); +- if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { +- nv_error(priv, "timeout acquiring display\n"); +- return -EBUSY; +- } +- } +- +- /* point at display engine memory area (hash table, objects) */ +- nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); +- +- /* enable supervisor interrupts, disable everything else */ +- nv_wr32(priv, 0x61002c, 0x00000370); +- nv_wr32(priv, 0x610028, 0x00000000); +- return 0; +-} +- +-static int +-nv50_disp_base_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_base *base = (void *)object; +- +- /* disable all interrupts */ +- nv_wr32(priv, 0x610024, 0x00000000); +- nv_wr32(priv, 0x610020, 0x00000000); +- +- return nouveau_parent_fini(&base->base, suspend); +-} +- +-struct nouveau_ofuncs +-nv50_disp_base_ofuncs = { +- .ctor = nv50_disp_base_ctor, +- .dtor = nv50_disp_base_dtor, +- .init = nv50_disp_base_init, +- .fini = nv50_disp_base_fini, +- .mthd = nv50_disp_base_mthd, +- .ntfy = nouveau_disp_ntfy, +-}; +- +-static struct nouveau_oclass +-nv50_disp_base_oclass[] = { +- { NV50_DISP, &nv50_disp_base_ofuncs }, +- {} +-}; +- +-static struct nouveau_oclass +-nv50_disp_sclass[] = { +- { NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, +- { NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, +- { NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, +- { NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, +- { NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, +- {} +-}; +- +-/******************************************************************************* +- * Display context, tracks instmem allocation and prevents more than one +- * client using the display hardware at any time. +- ******************************************************************************/ +- +-static int +-nv50_disp_data_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv = (void *)engine; +- struct nouveau_engctx *ectx; +- int ret = -EBUSY; +- +- /* no context needed for channel objects... */ +- if (nv_mclass(parent) != NV_DEVICE) { +- atomic_inc(&parent->refcount); +- *pobject = parent; +- return 1; +- } +- +- /* allocate display hardware to client */ +- mutex_lock(&nv_subdev(priv)->mutex); +- if (list_empty(&nv_engine(priv)->contexts)) { +- ret = nouveau_engctx_create(parent, engine, oclass, NULL, +- 0x10000, 0x10000, +- NVOBJ_FLAG_HEAP, &ectx); +- *pobject = nv_object(ectx); +- } +- mutex_unlock(&nv_subdev(priv)->mutex); +- return ret; +-} +- +-struct nouveau_oclass +-nv50_disp_cclass = { +- .handle = NV_ENGCTX(DISP, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_disp_data_ctor, +- .dtor = _nouveau_engctx_dtor, +- .init = _nouveau_engctx_init, +- .fini = _nouveau_engctx_fini, +- .rd32 = _nouveau_engctx_rd32, +- .wr32 = _nouveau_engctx_wr32, +- }, +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static void +-nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head) +-{ +- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); +- nv_mask(disp, 0x61002c, (4 << head), 0); +-} +- +-static void +-nv50_disp_vblank_init(struct nvkm_event *event, int type, int head) +-{ +- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); +- nv_mask(disp, 0x61002c, (4 << head), (4 << head)); +-} +- +-const struct nvkm_event_func +-nv50_disp_vblank_func = { +- .ctor = nouveau_disp_vblank_ctor, +- .init = nv50_disp_vblank_init, +- .fini = nv50_disp_vblank_fini, +-}; +- +-static const struct nouveau_enum +-nv50_disp_intr_error_type[] = { +- { 3, "ILLEGAL_MTHD" }, +- { 4, "INVALID_VALUE" }, +- { 5, "INVALID_STATE" }, +- { 7, "INVALID_HANDLE" }, +- {} +-}; +- +-static const struct nouveau_enum +-nv50_disp_intr_error_code[] = { +- { 0x00, "" }, +- {} +-}; +- +-static void +-nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) +-{ +- struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; +- u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08)); +- u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08)); +- u32 code = (addr & 0x00ff0000) >> 16; +- u32 type = (addr & 0x00007000) >> 12; +- u32 mthd = (addr & 0x00000ffc); +- const struct nouveau_enum *ec, *et; +- char ecunk[6], etunk[6]; +- +- et = nouveau_enum_find(nv50_disp_intr_error_type, type); +- if (!et) +- snprintf(etunk, sizeof(etunk), "UNK%02X", type); +- +- ec = nouveau_enum_find(nv50_disp_intr_error_code, code); +- if (!ec) +- snprintf(ecunk, sizeof(ecunk), "UNK%02X", code); +- +- nv_error(priv, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n", +- et ? et->name : etunk, ec ? ec->name : ecunk, +- chid, mthd, data); +- +- if (chid == 0) { +- switch (mthd) { +- case 0x0080: +- nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, +- impl->mthd.core); +- break; +- default: +- break; +- } +- } else +- if (chid <= 2) { +- switch (mthd) { +- case 0x0080: +- nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, +- impl->mthd.base); +- break; +- default: +- break; +- } +- } else +- if (chid <= 4) { +- switch (mthd) { +- case 0x0080: +- nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3, +- impl->mthd.ovly); +- break; +- default: +- break; +- } +- } +- +- nv_wr32(priv, 0x610020, 0x00010000 << chid); +- nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000); +-} +- +-static struct nvkm_output * +-exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, +- u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_outp *info) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvkm_output *outp; +- u16 mask, type; +- +- if (or < 4) { +- type = DCB_OUTPUT_ANALOG; +- mask = 0; +- } else +- if (or < 8) { +- switch (ctrl & 0x00000f00) { +- case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; +- case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; +- case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; +- case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; +- case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; +- case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; +- default: +- nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); +- return NULL; +- } +- or -= 4; +- } else { +- or = or - 8; +- type = 0x0010; +- mask = 0; +- switch (ctrl & 0x00000f00) { +- case 0x00000000: type |= priv->pior.type[or]; break; +- default: +- nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl); +- return NULL; +- } +- } +- +- mask = 0x00c0 & (mask << 6); +- mask |= 0x0001 << or; +- mask |= 0x0100 << head; +- +- list_for_each_entry(outp, &priv->base.outp, head) { +- if ((outp->info.hasht & 0xff) == type && +- (outp->info.hashm & mask) == mask) { +- *data = nvbios_outp_match(bios, outp->info.hasht, +- outp->info.hashm, +- ver, hdr, cnt, len, info); +- if (!*data) +- return NULL; +- return outp; +- } +- } +- +- return NULL; +-} +- +-static struct nvkm_output * +-exec_script(struct nv50_disp_priv *priv, int head, int id) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvkm_output *outp; +- struct nvbios_outp info; +- u8 ver, hdr, cnt, len; +- u32 data, ctrl = 0; +- u32 reg; +- int i; +- +- /* DAC */ +- for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) +- ctrl = nv_rd32(priv, 0x610b5c + (i * 8)); +- +- /* SOR */ +- if (!(ctrl & (1 << head))) { +- if (nv_device(priv)->chipset < 0x90 || +- nv_device(priv)->chipset == 0x92 || +- nv_device(priv)->chipset == 0xa0) { +- reg = 0x610b74; +- } else { +- reg = 0x610798; +- } +- for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) +- ctrl = nv_rd32(priv, reg + (i * 8)); +- i += 4; +- } +- +- /* PIOR */ +- if (!(ctrl & (1 << head))) { +- for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) +- ctrl = nv_rd32(priv, 0x610b84 + (i * 8)); +- i += 8; +- } +- +- if (!(ctrl & (1 << head))) +- return NULL; +- i--; +- +- outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); +- if (outp) { +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = bios, +- .offset = info.script[id], +- .outp = &outp->info, +- .crtc = head, +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- } +- +- return outp; +-} +- +-static struct nvkm_output * +-exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvkm_output *outp; +- struct nvbios_outp info1; +- struct nvbios_ocfg info2; +- u8 ver, hdr, cnt, len; +- u32 data, ctrl = 0; +- u32 reg; +- int i; +- +- /* DAC */ +- for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) +- ctrl = nv_rd32(priv, 0x610b58 + (i * 8)); +- +- /* SOR */ +- if (!(ctrl & (1 << head))) { +- if (nv_device(priv)->chipset < 0x90 || +- nv_device(priv)->chipset == 0x92 || +- nv_device(priv)->chipset == 0xa0) { +- reg = 0x610b70; +- } else { +- reg = 0x610794; +- } +- for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) +- ctrl = nv_rd32(priv, reg + (i * 8)); +- i += 4; +- } +- +- /* PIOR */ +- if (!(ctrl & (1 << head))) { +- for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) +- ctrl = nv_rd32(priv, 0x610b80 + (i * 8)); +- i += 8; +- } +- +- if (!(ctrl & (1 << head))) +- return NULL; +- i--; +- +- outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); +- if (!outp) +- return NULL; +- +- if (outp->info.location == 0) { +- switch (outp->info.type) { +- case DCB_OUTPUT_TMDS: +- *conf = (ctrl & 0x00000f00) >> 8; +- if (pclk >= 165000) +- *conf |= 0x0100; +- break; +- case DCB_OUTPUT_LVDS: +- *conf = priv->sor.lvdsconf; +- break; +- case DCB_OUTPUT_DP: +- *conf = (ctrl & 0x00000f00) >> 8; +- break; +- case DCB_OUTPUT_ANALOG: +- default: +- *conf = 0x00ff; +- break; +- } +- } else { +- *conf = (ctrl & 0x00000f00) >> 8; +- pclk = pclk / 2; +- } +- +- data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2); +- if (data && id < 0xff) { +- data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); +- if (data) { +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = bios, +- .offset = data, +- .outp = &outp->info, +- .crtc = head, +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- } +- } +- +- return outp; +-} +- +-static void +-nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head) +-{ +- exec_script(priv, head, 1); +-} +- +-static void +-nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) +-{ +- struct nvkm_output *outp = exec_script(priv, head, 2); +- +- /* the binary driver does this outside of the supervisor handling +- * (after the third supervisor from a detach). we (currently?) +- * allow both detach/attach to happen in the same set of +- * supervisor interrupts, so it would make sense to execute this +- * (full power down?) script after all the detach phases of the +- * supervisor handling. like with training if needed from the +- * second supervisor, nvidia doesn't do this, so who knows if it's +- * entirely safe, but it does appear to work.. +- * +- * without this script being run, on some configurations i've +- * seen, switching from DP to TMDS on a DP connector may result +- * in a blank screen (SOR_PWR off/on can restore it) +- */ +- if (outp && outp->info.type == DCB_OUTPUT_DP) { +- struct nvkm_output_dp *outpdp = (void *)outp; +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = nouveau_bios(priv), +- .outp = &outp->info, +- .crtc = head, +- .offset = outpdp->info.script[4], +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- atomic_set(&outpdp->lt.done, 0); +- } +-} +- +-static void +-nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head) +-{ +- struct nouveau_devinit *devinit = nouveau_devinit(priv); +- u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; +- if (pclk) +- devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); +-} +- +-static void +-nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head, +- struct dcb_output *outp, u32 pclk) +-{ +- const int link = !(outp->sorconf.link & 1); +- const int or = ffs(outp->or) - 1; +- const u32 soff = ( or * 0x800); +- const u32 loff = (link * 0x080) + soff; +- const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8)); +- const u32 symbol = 100000; +- const s32 vactive = nv_rd32(priv, 0x610af8 + (head * 0x540)) & 0xffff; +- const s32 vblanke = nv_rd32(priv, 0x610ae8 + (head * 0x540)) & 0xffff; +- const s32 vblanks = nv_rd32(priv, 0x610af0 + (head * 0x540)) & 0xffff; +- u32 dpctrl = nv_rd32(priv, 0x61c10c + loff); +- u32 clksor = nv_rd32(priv, 0x614300 + soff); +- int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; +- int TU, VTUi, VTUf, VTUa; +- u64 link_data_rate, link_ratio, unk; +- u32 best_diff = 64 * symbol; +- u32 link_nr, link_bw, bits; +- u64 value; +- +- link_bw = (clksor & 0x000c0000) ? 270000 : 162000; +- link_nr = hweight32(dpctrl & 0x000f0000); +- +- /* symbols/hblank - algorithm taken from comments in tegra driver */ +- value = vblanke + vactive - vblanks - 7; +- value = value * link_bw; +- do_div(value, pclk); +- value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); +- nv_mask(priv, 0x61c1e8 + soff, 0x0000ffff, value); +- +- /* symbols/vblank - algorithm taken from comments in tegra driver */ +- value = vblanks - vblanke - 25; +- value = value * link_bw; +- do_div(value, pclk); +- value = value - ((36 / link_nr) + 3) - 1; +- nv_mask(priv, 0x61c1ec + soff, 0x00ffffff, value); +- +- /* watermark / activesym */ +- if ((ctrl & 0xf0000) == 0x60000) bits = 30; +- else if ((ctrl & 0xf0000) == 0x50000) bits = 24; +- else bits = 18; +- +- link_data_rate = (pclk * bits / 8) / link_nr; +- +- /* calculate ratio of packed data rate to link symbol rate */ +- link_ratio = link_data_rate * symbol; +- do_div(link_ratio, link_bw); +- +- for (TU = 64; TU >= 32; TU--) { +- /* calculate average number of valid symbols in each TU */ +- u32 tu_valid = link_ratio * TU; +- u32 calc, diff; +- +- /* find a hw representation for the fraction.. */ +- VTUi = tu_valid / symbol; +- calc = VTUi * symbol; +- diff = tu_valid - calc; +- if (diff) { +- if (diff >= (symbol / 2)) { +- VTUf = symbol / (symbol - diff); +- if (symbol - (VTUf * diff)) +- VTUf++; +- +- if (VTUf <= 15) { +- VTUa = 1; +- calc += symbol - (symbol / VTUf); +- } else { +- VTUa = 0; +- VTUf = 1; +- calc += symbol; +- } +- } else { +- VTUa = 0; +- VTUf = min((int)(symbol / diff), 15); +- calc += symbol / VTUf; +- } +- +- diff = calc - tu_valid; +- } else { +- /* no remainder, but the hw doesn't like the fractional +- * part to be zero. decrement the integer part and +- * have the fraction add a whole symbol back +- */ +- VTUa = 0; +- VTUf = 1; +- VTUi--; +- } +- +- if (diff < best_diff) { +- best_diff = diff; +- bestTU = TU; +- bestVTUa = VTUa; +- bestVTUf = VTUf; +- bestVTUi = VTUi; +- if (diff == 0) +- break; +- } +- } +- +- if (!bestTU) { +- nv_error(priv, "unable to find suitable dp config\n"); +- return; +- } +- +- /* XXX close to vbios numbers, but not right */ +- unk = (symbol - link_ratio) * bestTU; +- unk *= link_ratio; +- do_div(unk, symbol); +- do_div(unk, symbol); +- unk += 6; +- +- nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2); +- nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | +- bestVTUf << 16 | +- bestVTUi << 8 | unk); +-} +- +-static void +-nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) +-{ +- struct nvkm_output *outp; +- u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; +- u32 hval, hreg = 0x614200 + (head * 0x800); +- u32 oval, oreg; +- u32 mask, conf; +- +- outp = exec_clkcmp(priv, head, 0xff, pclk, &conf); +- if (!outp) +- return; +- +- /* we allow both encoder attach and detach operations to occur +- * within a single supervisor (ie. modeset) sequence. the +- * encoder detach scripts quite often switch off power to the +- * lanes, which requires the link to be re-trained. +- * +- * this is not generally an issue as the sink "must" (heh) +- * signal an irq when it's lost sync so the driver can +- * re-train. +- * +- * however, on some boards, if one does not configure at least +- * the gpu side of the link *before* attaching, then various +- * things can go horribly wrong (PDISP disappearing from mmio, +- * third supervisor never happens, etc). +- * +- * the solution is simply to retrain here, if necessary. last +- * i checked, the binary driver userspace does not appear to +- * trigger this situation (it forces an UPDATE between steps). +- */ +- if (outp->info.type == DCB_OUTPUT_DP) { +- u32 soff = (ffs(outp->info.or) - 1) * 0x08; +- u32 ctrl, datarate; +- +- if (outp->info.location == 0) { +- ctrl = nv_rd32(priv, 0x610794 + soff); +- soff = 1; +- } else { +- ctrl = nv_rd32(priv, 0x610b80 + soff); +- soff = 2; +- } +- +- switch ((ctrl & 0x000f0000) >> 16) { +- case 6: datarate = pclk * 30; break; +- case 5: datarate = pclk * 24; break; +- case 2: +- default: +- datarate = pclk * 18; +- break; +- } +- +- if (nvkm_output_dp_train(outp, datarate / soff, true)) +- ERR("link not trained before attach\n"); +- } +- +- exec_clkcmp(priv, head, 0, pclk, &conf); +- +- if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { +- oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; +- oval = 0x00000000; +- hval = 0x00000000; +- mask = 0xffffffff; +- } else +- if (!outp->info.location) { +- if (outp->info.type == DCB_OUTPUT_DP) +- nv50_disp_intr_unk20_2_dp(priv, head, &outp->info, pclk); +- oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; +- oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; +- hval = 0x00000000; +- mask = 0x00000707; +- } else { +- oreg = 0x614380 + (ffs(outp->info.or) - 1) * 0x800; +- oval = 0x00000001; +- hval = 0x00000001; +- mask = 0x00000707; +- } +- +- nv_mask(priv, hreg, 0x0000000f, hval); +- nv_mask(priv, oreg, mask, oval); +-} +- +-/* If programming a TMDS output on a SOR that can also be configured for +- * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off. +- * +- * It looks like the VBIOS TMDS scripts make an attempt at this, however, +- * the VBIOS scripts on at least one board I have only switch it off on +- * link 0, causing a blank display if the output has previously been +- * programmed for DisplayPort. +- */ +-static void +-nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- const int link = !(outp->sorconf.link & 1); +- const int or = ffs(outp->or) - 1; +- const u32 loff = (or * 0x800) + (link * 0x80); +- const u16 mask = (outp->sorconf.link << 6) | outp->or; +- struct dcb_output match; +- u8 ver, hdr; +- +- if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) +- nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000); +-} +- +-static void +-nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head) +-{ +- struct nvkm_output *outp; +- u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; +- u32 conf; +- +- outp = exec_clkcmp(priv, head, 1, pclk, &conf); +- if (!outp) +- return; +- +- if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) +- nv50_disp_intr_unk40_0_tmds(priv, &outp->info); +-} +- +-void +-nv50_disp_intr_supervisor(struct work_struct *work) +-{ +- struct nv50_disp_priv *priv = +- container_of(work, struct nv50_disp_priv, supervisor); +- struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; +- u32 super = nv_rd32(priv, 0x610030); +- int head; +- +- nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); +- +- if (priv->super & 0x00000010) { +- nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core); +- for (head = 0; head < priv->head.nr; head++) { +- if (!(super & (0x00000020 << head))) +- continue; +- if (!(super & (0x00000080 << head))) +- continue; +- nv50_disp_intr_unk10_0(priv, head); +- } +- } else +- if (priv->super & 0x00000020) { +- for (head = 0; head < priv->head.nr; head++) { +- if (!(super & (0x00000080 << head))) +- continue; +- nv50_disp_intr_unk20_0(priv, head); +- } +- for (head = 0; head < priv->head.nr; head++) { +- if (!(super & (0x00000200 << head))) +- continue; +- nv50_disp_intr_unk20_1(priv, head); +- } +- for (head = 0; head < priv->head.nr; head++) { +- if (!(super & (0x00000080 << head))) +- continue; +- nv50_disp_intr_unk20_2(priv, head); +- } +- } else +- if (priv->super & 0x00000040) { +- for (head = 0; head < priv->head.nr; head++) { +- if (!(super & (0x00000080 << head))) +- continue; +- nv50_disp_intr_unk40_0(priv, head); +- } +- } +- +- nv_wr32(priv, 0x610030, 0x80000000); +-} +- +-void +-nv50_disp_intr(struct nouveau_subdev *subdev) +-{ +- struct nv50_disp_priv *priv = (void *)subdev; +- u32 intr0 = nv_rd32(priv, 0x610020); +- u32 intr1 = nv_rd32(priv, 0x610024); +- +- while (intr0 & 0x001f0000) { +- u32 chid = __ffs(intr0 & 0x001f0000) - 16; +- nv50_disp_intr_error(priv, chid); +- intr0 &= ~(0x00010000 << chid); +- } +- +- while (intr0 & 0x0000001f) { +- u32 chid = __ffs(intr0 & 0x0000001f); +- nv50_disp_chan_uevent_send(priv, chid); +- intr0 &= ~(0x00000001 << chid); +- } +- +- if (intr1 & 0x00000004) { +- nouveau_disp_vblank(&priv->base, 0); +- nv_wr32(priv, 0x610024, 0x00000004); +- intr1 &= ~0x00000004; +- } +- +- if (intr1 & 0x00000008) { +- nouveau_disp_vblank(&priv->base, 1); +- nv_wr32(priv, 0x610024, 0x00000008); +- intr1 &= ~0x00000008; +- } +- +- if (intr1 & 0x00000070) { +- priv->super = (intr1 & 0x00000070); +- schedule_work(&priv->supervisor); +- nv_wr32(priv, 0x610024, priv->super); +- intr1 &= ~0x00000070; +- } +-} +- +-static int +-nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", +- "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nv50_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nv50_disp_intr; +- INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); +- priv->sclass = nv50_disp_sclass; +- priv->head.nr = 2; +- priv->dac.nr = 3; +- priv->sor.nr = 2; +- priv->pior.nr = 3; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->pior.power = nv50_pior_power; +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_disp_outp_sclass[] = { +- &nv50_pior_dp_impl.base.base, +- NULL +-}; +- +-struct nouveau_oclass * +-nv50_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x50), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nv50_disp_vblank_func, +- .base.outp = nv50_disp_outp_sclass, +- .mthd.core = &nv50_disp_mast_mthd_chan, +- .mthd.base = &nv50_disp_sync_mthd_chan, +- .mthd.ovly = &nv50_disp_ovly_mthd_chan, +- .mthd.prev = 0x000004, +- .head.scanoutpos = nv50_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h +deleted file mode 100644 +index 5279feef..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.h ++++ /dev/null +@@ -1,247 +0,0 @@ +-#ifndef __NV50_DISP_H__ +-#define __NV50_DISP_H__ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include "dport.h" +-#include "priv.h" +-#include "outp.h" +-#include "outpdp.h" +- +-#define NV50_DISP_MTHD_ struct nouveau_object *object, \ +- struct nv50_disp_priv *priv, void *data, u32 size +-#define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head +-#define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp +- +-struct nv50_disp_priv { +- struct nouveau_disp base; +- struct nouveau_oclass *sclass; +- +- struct work_struct supervisor; +- u32 super; +- +- struct nvkm_event uevent; +- +- struct { +- int nr; +- } head; +- struct { +- int nr; +- int (*power)(NV50_DISP_MTHD_V1); +- int (*sense)(NV50_DISP_MTHD_V1); +- } dac; +- struct { +- int nr; +- int (*power)(NV50_DISP_MTHD_V1); +- int (*hda_eld)(NV50_DISP_MTHD_V1); +- int (*hdmi)(NV50_DISP_MTHD_V1); +- u32 lvdsconf; +- } sor; +- struct { +- int nr; +- int (*power)(NV50_DISP_MTHD_V1); +- u8 type[3]; +- } pior; +-}; +- +-struct nv50_disp_impl { +- struct nouveau_disp_impl base; +- struct { +- const struct nv50_disp_mthd_chan *core; +- const struct nv50_disp_mthd_chan *base; +- const struct nv50_disp_mthd_chan *ovly; +- int prev; +- } mthd; +- struct { +- int (*scanoutpos)(NV50_DISP_MTHD_V0); +- } head; +-}; +- +-int nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0); +-int nv50_disp_base_mthd(struct nouveau_object *, u32, void *, u32); +- +-int nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0); +- +-int nv50_dac_power(NV50_DISP_MTHD_V1); +-int nv50_dac_sense(NV50_DISP_MTHD_V1); +- +-int nva3_hda_eld(NV50_DISP_MTHD_V1); +-int nvd0_hda_eld(NV50_DISP_MTHD_V1); +- +-int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1); +-int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1); +-int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1); +-int nve0_hdmi_ctrl(NV50_DISP_MTHD_V1); +- +-int nv50_sor_power(NV50_DISP_MTHD_V1); +- +-int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16, +- u32, struct dcb_output *); +-int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16, +- u32, struct dcb_output *); +-int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32, +- struct dcb_output *); +-int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, +- struct dcb_output *); +-int nv94_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, +- struct dcb_output *); +- +-int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32, +- struct dcb_output *); +-int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, +- struct dcb_output *); +-int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32, +- struct dcb_output *); +- +-int nv50_pior_power(NV50_DISP_MTHD_V1); +- +-struct nv50_disp_base { +- struct nouveau_parent base; +- struct nouveau_ramht *ramht; +- u32 chan; +-}; +- +-struct nv50_disp_chan_impl { +- struct nouveau_ofuncs base; +- int chid; +- int (*attach)(struct nouveau_object *, struct nouveau_object *, u32); +- void (*detach)(struct nouveau_object *, int); +-}; +- +-struct nv50_disp_chan { +- struct nouveau_namedb base; +- int chid; +-}; +- +-int nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **); +-int nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *); +-u32 nv50_disp_chan_rd32(struct nouveau_object *, u64); +-void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32); +-extern const struct nvkm_event_func nv50_disp_chan_uevent; +-int nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32, +- struct nvkm_notify *); +-void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int); +- +-extern const struct nvkm_event_func nvd0_disp_chan_uevent; +- +-#define nv50_disp_chan_init(a) \ +- nouveau_namedb_init(&(a)->base) +-#define nv50_disp_chan_fini(a,b) \ +- nouveau_namedb_fini(&(a)->base, (b)) +- +-struct nv50_disp_dmac { +- struct nv50_disp_chan base; +- struct nouveau_dmaobj *pushdma; +- u32 push; +-}; +- +-void nv50_disp_dmac_dtor(struct nouveau_object *); +- +-struct nv50_disp_pioc { +- struct nv50_disp_chan base; +-}; +- +-void nv50_disp_pioc_dtor(struct nouveau_object *); +- +-struct nv50_disp_mthd_list { +- u32 mthd; +- u32 addr; +- struct { +- u32 mthd; +- u32 addr; +- const char *name; +- } data[]; +-}; +- +-struct nv50_disp_mthd_chan { +- const char *name; +- u32 addr; +- struct { +- const char *name; +- int nr; +- const struct nv50_disp_mthd_list *mthd; +- } data[]; +-}; +- +-extern struct nv50_disp_chan_impl nv50_disp_mast_ofuncs; +-int nv50_disp_mast_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base; +-extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor; +-extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior; +-extern struct nv50_disp_chan_impl nv50_disp_sync_ofuncs; +-int nv50_disp_sync_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image; +-extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs; +-int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base; +-extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs; +-int nv50_disp_oimm_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs; +-int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-extern struct nouveau_ofuncs nv50_disp_base_ofuncs; +-int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv50_disp_base_dtor(struct nouveau_object *); +-extern struct nouveau_omthds nv50_disp_base_omthds[]; +-extern struct nouveau_oclass nv50_disp_cclass; +-void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head, +- const struct nv50_disp_mthd_chan *); +-void nv50_disp_intr_supervisor(struct work_struct *); +-void nv50_disp_intr(struct nouveau_subdev *); +-extern const struct nvkm_event_func nv50_disp_vblank_func; +- +-extern const struct nv50_disp_mthd_chan nv84_disp_mast_mthd_chan; +-extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_dac; +-extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_head; +-extern const struct nv50_disp_mthd_chan nv84_disp_sync_mthd_chan; +-extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan; +- +-extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan; +- +-extern struct nv50_disp_chan_impl nvd0_disp_mast_ofuncs; +-extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base; +-extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac; +-extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor; +-extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior; +-extern struct nv50_disp_chan_impl nvd0_disp_sync_ofuncs; +-extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs; +-extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan; +-extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs; +-extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs; +-extern struct nouveau_ofuncs nvd0_disp_base_ofuncs; +-extern struct nouveau_oclass nvd0_disp_cclass; +-void nvd0_disp_intr_supervisor(struct work_struct *); +-void nvd0_disp_intr(struct nouveau_subdev *); +-extern const struct nvkm_event_func nvd0_disp_vblank_func; +- +-extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan; +-extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan; +- +-extern struct nvkm_output_dp_impl nv50_pior_dp_impl; +-extern struct nouveau_oclass *nv50_disp_outp_sclass[]; +- +-extern struct nvkm_output_dp_impl nv94_sor_dp_impl; +-int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int); +-extern struct nouveau_oclass *nv94_disp_outp_sclass[]; +- +-extern struct nvkm_output_dp_impl nvd0_sor_dp_impl; +-extern struct nouveau_oclass *nvd0_disp_outp_sclass[]; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c +deleted file mode 100644 +index d3628471..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c ++++ /dev/null +@@ -1,276 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * EVO master channel object +- ******************************************************************************/ +- +-const struct nv50_disp_mthd_list +-nv84_disp_mast_mthd_dac = { +- .mthd = 0x0080, +- .addr = 0x000008, +- .data = { +- { 0x0400, 0x610b58 }, +- { 0x0404, 0x610bdc }, +- { 0x0420, 0x610bc4 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nv84_disp_mast_mthd_head = { +- .mthd = 0x0400, +- .addr = 0x000540, +- .data = { +- { 0x0800, 0x610ad8 }, +- { 0x0804, 0x610ad0 }, +- { 0x0808, 0x610a48 }, +- { 0x080c, 0x610a78 }, +- { 0x0810, 0x610ac0 }, +- { 0x0814, 0x610af8 }, +- { 0x0818, 0x610b00 }, +- { 0x081c, 0x610ae8 }, +- { 0x0820, 0x610af0 }, +- { 0x0824, 0x610b08 }, +- { 0x0828, 0x610b10 }, +- { 0x082c, 0x610a68 }, +- { 0x0830, 0x610a60 }, +- { 0x0834, 0x000000 }, +- { 0x0838, 0x610a40 }, +- { 0x0840, 0x610a24 }, +- { 0x0844, 0x610a2c }, +- { 0x0848, 0x610aa8 }, +- { 0x084c, 0x610ab0 }, +- { 0x085c, 0x610c5c }, +- { 0x0860, 0x610a84 }, +- { 0x0864, 0x610a90 }, +- { 0x0868, 0x610b18 }, +- { 0x086c, 0x610b20 }, +- { 0x0870, 0x610ac8 }, +- { 0x0874, 0x610a38 }, +- { 0x0878, 0x610c50 }, +- { 0x0880, 0x610a58 }, +- { 0x0884, 0x610a9c }, +- { 0x089c, 0x610c68 }, +- { 0x08a0, 0x610a70 }, +- { 0x08a4, 0x610a50 }, +- { 0x08a8, 0x610ae0 }, +- { 0x08c0, 0x610b28 }, +- { 0x08c4, 0x610b30 }, +- { 0x08c8, 0x610b40 }, +- { 0x08d4, 0x610b38 }, +- { 0x08d8, 0x610b48 }, +- { 0x08dc, 0x610b50 }, +- { 0x0900, 0x610a18 }, +- { 0x0904, 0x610ab8 }, +- { 0x0910, 0x610c70 }, +- { 0x0914, 0x610c78 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nv84_disp_mast_mthd_chan = { +- .name = "Core", +- .addr = 0x000000, +- .data = { +- { "Global", 1, &nv50_disp_mast_mthd_base }, +- { "DAC", 3, &nv84_disp_mast_mthd_dac }, +- { "SOR", 2, &nv50_disp_mast_mthd_sor }, +- { "PIOR", 3, &nv50_disp_mast_mthd_pior }, +- { "HEAD", 2, &nv84_disp_mast_mthd_head }, +- {} +- } +-}; +- +-/******************************************************************************* +- * EVO sync channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nv84_disp_sync_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x000000 }, +- { 0x0084, 0x0008c4 }, +- { 0x0088, 0x0008d0 }, +- { 0x008c, 0x0008dc }, +- { 0x0090, 0x0008e4 }, +- { 0x0094, 0x610884 }, +- { 0x00a0, 0x6108a0 }, +- { 0x00a4, 0x610878 }, +- { 0x00c0, 0x61086c }, +- { 0x00c4, 0x610800 }, +- { 0x00c8, 0x61080c }, +- { 0x00cc, 0x610818 }, +- { 0x00e0, 0x610858 }, +- { 0x00e4, 0x610860 }, +- { 0x00e8, 0x6108ac }, +- { 0x00ec, 0x6108b4 }, +- { 0x00fc, 0x610824 }, +- { 0x0100, 0x610894 }, +- { 0x0104, 0x61082c }, +- { 0x0110, 0x6108bc }, +- { 0x0114, 0x61088c }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nv84_disp_sync_mthd_chan = { +- .name = "Base", +- .addr = 0x000540, +- .data = { +- { "Global", 1, &nv84_disp_sync_mthd_base }, +- { "Image", 2, &nv50_disp_sync_mthd_image }, +- {} +- } +-}; +- +-/******************************************************************************* +- * EVO overlay channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nv84_disp_ovly_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x000000 }, +- { 0x0084, 0x6109a0 }, +- { 0x0088, 0x6109c0 }, +- { 0x008c, 0x6109c8 }, +- { 0x0090, 0x6109b4 }, +- { 0x0094, 0x610970 }, +- { 0x00a0, 0x610998 }, +- { 0x00a4, 0x610964 }, +- { 0x00c0, 0x610958 }, +- { 0x00e0, 0x6109a8 }, +- { 0x00e4, 0x6109d0 }, +- { 0x00e8, 0x6109d8 }, +- { 0x0100, 0x61094c }, +- { 0x0104, 0x610984 }, +- { 0x0108, 0x61098c }, +- { 0x0800, 0x6109f8 }, +- { 0x0808, 0x610a08 }, +- { 0x080c, 0x610a10 }, +- { 0x0810, 0x610a00 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nv84_disp_ovly_mthd_chan = { +- .name = "Overlay", +- .addr = 0x000540, +- .data = { +- { "Global", 1, &nv84_disp_ovly_mthd_base }, +- {} +- } +-}; +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_disp_sclass[] = { +- { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, +- { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, +- { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, +- { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, +- { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-nv84_disp_base_oclass[] = { +- { G82_DISP, &nv50_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", +- "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nv84_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nv50_disp_intr; +- INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); +- priv->sclass = nv84_disp_sclass; +- priv->head.nr = 2; +- priv->dac.nr = 3; +- priv->sor.nr = 2; +- priv->pior.nr = 3; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hdmi = nv84_hdmi_ctrl; +- priv->pior.power = nv50_pior_power; +- return 0; +-} +- +-struct nouveau_oclass * +-nv84_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x82), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nv50_disp_vblank_func, +- .base.outp = nv50_disp_outp_sclass, +- .mthd.core = &nv84_disp_mast_mthd_chan, +- .mthd.base = &nv84_disp_sync_mthd_chan, +- .mthd.ovly = &nv84_disp_ovly_mthd_chan, +- .mthd.prev = 0x000004, +- .head.scanoutpos = nv50_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c +deleted file mode 100644 +index a1170640..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c ++++ /dev/null +@@ -1,142 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * EVO master channel object +- ******************************************************************************/ +- +-const struct nv50_disp_mthd_list +-nv94_disp_mast_mthd_sor = { +- .mthd = 0x0040, +- .addr = 0x000008, +- .data = { +- { 0x0600, 0x610794 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nv94_disp_mast_mthd_chan = { +- .name = "Core", +- .addr = 0x000000, +- .data = { +- { "Global", 1, &nv50_disp_mast_mthd_base }, +- { "DAC", 3, &nv84_disp_mast_mthd_dac }, +- { "SOR", 4, &nv94_disp_mast_mthd_sor }, +- { "PIOR", 3, &nv50_disp_mast_mthd_pior }, +- { "HEAD", 2, &nv84_disp_mast_mthd_head }, +- {} +- } +-}; +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv94_disp_sclass[] = { +- { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, +- { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, +- { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, +- { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, +- { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-nv94_disp_base_oclass[] = { +- { GT206_DISP, &nv50_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", +- "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nv94_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nv50_disp_intr; +- INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); +- priv->sclass = nv94_disp_sclass; +- priv->head.nr = 2; +- priv->dac.nr = 3; +- priv->sor.nr = 4; +- priv->pior.nr = 3; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hdmi = nv84_hdmi_ctrl; +- priv->pior.power = nv50_pior_power; +- return 0; +-} +- +-struct nouveau_oclass * +-nv94_disp_outp_sclass[] = { +- &nv50_pior_dp_impl.base.base, +- &nv94_sor_dp_impl.base.base, +- NULL +-}; +- +-struct nouveau_oclass * +-nv94_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x88), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv94_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nv50_disp_vblank_func, +- .base.outp = nv94_disp_outp_sclass, +- .mthd.core = &nv94_disp_mast_mthd_chan, +- .mthd.base = &nv84_disp_sync_mthd_chan, +- .mthd.ovly = &nv84_disp_ovly_mthd_chan, +- .mthd.prev = 0x000004, +- .head.scanoutpos = nv50_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c +deleted file mode 100644 +index c67e68aa..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva0.c ++++ /dev/null +@@ -1,152 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * EVO overlay channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nva0_disp_ovly_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x000000 }, +- { 0x0084, 0x6109a0 }, +- { 0x0088, 0x6109c0 }, +- { 0x008c, 0x6109c8 }, +- { 0x0090, 0x6109b4 }, +- { 0x0094, 0x610970 }, +- { 0x00a0, 0x610998 }, +- { 0x00a4, 0x610964 }, +- { 0x00b0, 0x610c98 }, +- { 0x00b4, 0x610ca4 }, +- { 0x00b8, 0x610cac }, +- { 0x00c0, 0x610958 }, +- { 0x00e0, 0x6109a8 }, +- { 0x00e4, 0x6109d0 }, +- { 0x00e8, 0x6109d8 }, +- { 0x0100, 0x61094c }, +- { 0x0104, 0x610984 }, +- { 0x0108, 0x61098c }, +- { 0x0800, 0x6109f8 }, +- { 0x0808, 0x610a08 }, +- { 0x080c, 0x610a10 }, +- { 0x0810, 0x610a00 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_chan +-nva0_disp_ovly_mthd_chan = { +- .name = "Overlay", +- .addr = 0x000540, +- .data = { +- { "Global", 1, &nva0_disp_ovly_mthd_base }, +- {} +- } +-}; +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nva0_disp_sclass[] = { +- { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, +- { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, +- { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, +- { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, +- { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-nva0_disp_base_oclass[] = { +- { GT200_DISP, &nv50_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", +- "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nva0_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nv50_disp_intr; +- INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); +- priv->sclass = nva0_disp_sclass; +- priv->head.nr = 2; +- priv->dac.nr = 3; +- priv->sor.nr = 2; +- priv->pior.nr = 3; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hdmi = nv84_hdmi_ctrl; +- priv->pior.power = nv50_pior_power; +- return 0; +-} +- +-struct nouveau_oclass * +-nva0_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x83), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva0_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nv50_disp_vblank_func, +- .base.outp = nv50_disp_outp_sclass, +- .mthd.core = &nv84_disp_mast_mthd_chan, +- .mthd.base = &nv84_disp_sync_mthd_chan, +- .mthd.ovly = &nva0_disp_ovly_mthd_chan, +- .mthd.prev = 0x000004, +- .head.scanoutpos = nv50_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c +deleted file mode 100644 +index 22969f35..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c ++++ /dev/null +@@ -1,108 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nva3_disp_sclass[] = { +- { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base }, +- { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base }, +- { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, +- { GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, +- { GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-nva3_disp_base_oclass[] = { +- { GT214_DISP, &nv50_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP", +- "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nva3_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nv50_disp_intr; +- INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); +- priv->sclass = nva3_disp_sclass; +- priv->head.nr = 2; +- priv->dac.nr = 3; +- priv->sor.nr = 4; +- priv->pior.nr = 3; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hda_eld = nva3_hda_eld; +- priv->sor.hdmi = nva3_hdmi_ctrl; +- priv->pior.power = nv50_pior_power; +- return 0; +-} +- +-struct nouveau_oclass * +-nva3_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x85), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva3_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nv50_disp_vblank_func, +- .base.outp = nv94_disp_outp_sclass, +- .mthd.core = &nv94_disp_mast_mthd_chan, +- .mthd.base = &nv84_disp_sync_mthd_chan, +- .mthd.ovly = &nv84_disp_ovly_mthd_chan, +- .mthd.prev = 0x000004, +- .head.scanoutpos = nv50_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c +deleted file mode 100644 +index 747e64bb..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c ++++ /dev/null +@@ -1,1300 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * EVO channel base class +- ******************************************************************************/ +- +-static void +-nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); +- nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index); +-} +- +-static void +-nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) +-{ +- struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); +- nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index); +-} +- +-const struct nvkm_event_func +-nvd0_disp_chan_uevent = { +- .ctor = nv50_disp_chan_uevent_ctor, +- .init = nvd0_disp_chan_uevent_init, +- .fini = nvd0_disp_chan_uevent_fini, +-}; +- +-/******************************************************************************* +- * EVO DMA channel base class +- ******************************************************************************/ +- +-static int +-nvd0_disp_dmac_object_attach(struct nouveau_object *parent, +- struct nouveau_object *object, u32 name) +-{ +- struct nv50_disp_base *base = (void *)parent->parent; +- struct nv50_disp_chan *chan = (void *)parent; +- u32 addr = nv_gpuobj(object)->node->offset; +- u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001; +- return nouveau_ramht_insert(base->ramht, chan->chid, name, data); +-} +- +-static void +-nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie) +-{ +- struct nv50_disp_base *base = (void *)parent->parent; +- nouveau_ramht_remove(base->ramht, cookie); +-} +- +-static int +-nvd0_disp_dmac_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *dmac = (void *)object; +- int chid = dmac->base.chid; +- int ret; +- +- ret = nv50_disp_chan_init(&dmac->base); +- if (ret) +- return ret; +- +- /* enable error reporting */ +- nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); +- +- /* initialise channel for dma command submission */ +- nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push); +- nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000); +- nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001); +- nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); +- nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); +- nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013); +- +- /* wait for it to go inactive */ +- if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) { +- nv_error(dmac, "init: 0x%08x\n", +- nv_rd32(priv, 0x610490 + (chid * 0x10))); +- return -EBUSY; +- } +- +- return 0; +-} +- +-static int +-nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *dmac = (void *)object; +- int chid = dmac->base.chid; +- +- /* deactivate channel */ +- nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); +- nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); +- if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) { +- nv_error(dmac, "fini: 0x%08x\n", +- nv_rd32(priv, 0x610490 + (chid * 0x10))); +- if (suspend) +- return -EBUSY; +- } +- +- /* disable error reporting and completion notification */ +- nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); +- nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); +- +- return nv50_disp_chan_fini(&dmac->base, suspend); +-} +- +-/******************************************************************************* +- * EVO master channel object +- ******************************************************************************/ +- +-const struct nv50_disp_mthd_list +-nvd0_disp_mast_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x660080 }, +- { 0x0084, 0x660084 }, +- { 0x0088, 0x660088 }, +- { 0x008c, 0x000000 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nvd0_disp_mast_mthd_dac = { +- .mthd = 0x0020, +- .addr = 0x000020, +- .data = { +- { 0x0180, 0x660180 }, +- { 0x0184, 0x660184 }, +- { 0x0188, 0x660188 }, +- { 0x0190, 0x660190 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nvd0_disp_mast_mthd_sor = { +- .mthd = 0x0020, +- .addr = 0x000020, +- .data = { +- { 0x0200, 0x660200 }, +- { 0x0204, 0x660204 }, +- { 0x0208, 0x660208 }, +- { 0x0210, 0x660210 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_list +-nvd0_disp_mast_mthd_pior = { +- .mthd = 0x0020, +- .addr = 0x000020, +- .data = { +- { 0x0300, 0x660300 }, +- { 0x0304, 0x660304 }, +- { 0x0308, 0x660308 }, +- { 0x0310, 0x660310 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_list +-nvd0_disp_mast_mthd_head = { +- .mthd = 0x0300, +- .addr = 0x000300, +- .data = { +- { 0x0400, 0x660400 }, +- { 0x0404, 0x660404 }, +- { 0x0408, 0x660408 }, +- { 0x040c, 0x66040c }, +- { 0x0410, 0x660410 }, +- { 0x0414, 0x660414 }, +- { 0x0418, 0x660418 }, +- { 0x041c, 0x66041c }, +- { 0x0420, 0x660420 }, +- { 0x0424, 0x660424 }, +- { 0x0428, 0x660428 }, +- { 0x042c, 0x66042c }, +- { 0x0430, 0x660430 }, +- { 0x0434, 0x660434 }, +- { 0x0438, 0x660438 }, +- { 0x0440, 0x660440 }, +- { 0x0444, 0x660444 }, +- { 0x0448, 0x660448 }, +- { 0x044c, 0x66044c }, +- { 0x0450, 0x660450 }, +- { 0x0454, 0x660454 }, +- { 0x0458, 0x660458 }, +- { 0x045c, 0x66045c }, +- { 0x0460, 0x660460 }, +- { 0x0468, 0x660468 }, +- { 0x046c, 0x66046c }, +- { 0x0470, 0x660470 }, +- { 0x0474, 0x660474 }, +- { 0x0480, 0x660480 }, +- { 0x0484, 0x660484 }, +- { 0x048c, 0x66048c }, +- { 0x0490, 0x660490 }, +- { 0x0494, 0x660494 }, +- { 0x0498, 0x660498 }, +- { 0x04b0, 0x6604b0 }, +- { 0x04b8, 0x6604b8 }, +- { 0x04bc, 0x6604bc }, +- { 0x04c0, 0x6604c0 }, +- { 0x04c4, 0x6604c4 }, +- { 0x04c8, 0x6604c8 }, +- { 0x04d0, 0x6604d0 }, +- { 0x04d4, 0x6604d4 }, +- { 0x04e0, 0x6604e0 }, +- { 0x04e4, 0x6604e4 }, +- { 0x04e8, 0x6604e8 }, +- { 0x04ec, 0x6604ec }, +- { 0x04f0, 0x6604f0 }, +- { 0x04f4, 0x6604f4 }, +- { 0x04f8, 0x6604f8 }, +- { 0x04fc, 0x6604fc }, +- { 0x0500, 0x660500 }, +- { 0x0504, 0x660504 }, +- { 0x0508, 0x660508 }, +- { 0x050c, 0x66050c }, +- { 0x0510, 0x660510 }, +- { 0x0514, 0x660514 }, +- { 0x0518, 0x660518 }, +- { 0x051c, 0x66051c }, +- { 0x052c, 0x66052c }, +- { 0x0530, 0x660530 }, +- { 0x054c, 0x66054c }, +- { 0x0550, 0x660550 }, +- { 0x0554, 0x660554 }, +- { 0x0558, 0x660558 }, +- { 0x055c, 0x66055c }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_chan +-nvd0_disp_mast_mthd_chan = { +- .name = "Core", +- .addr = 0x000000, +- .data = { +- { "Global", 1, &nvd0_disp_mast_mthd_base }, +- { "DAC", 3, &nvd0_disp_mast_mthd_dac }, +- { "SOR", 8, &nvd0_disp_mast_mthd_sor }, +- { "PIOR", 4, &nvd0_disp_mast_mthd_pior }, +- { "HEAD", 4, &nvd0_disp_mast_mthd_head }, +- {} +- } +-}; +- +-static int +-nvd0_disp_mast_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *mast = (void *)object; +- int ret; +- +- ret = nv50_disp_chan_init(&mast->base); +- if (ret) +- return ret; +- +- /* enable error reporting */ +- nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001); +- +- /* initialise channel for dma command submission */ +- nv_wr32(priv, 0x610494, mast->push); +- nv_wr32(priv, 0x610498, 0x00010000); +- nv_wr32(priv, 0x61049c, 0x00000001); +- nv_mask(priv, 0x610490, 0x00000010, 0x00000010); +- nv_wr32(priv, 0x640000, 0x00000000); +- nv_wr32(priv, 0x610490, 0x01000013); +- +- /* wait for it to go inactive */ +- if (!nv_wait(priv, 0x610490, 0x80000000, 0x00000000)) { +- nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490)); +- return -EBUSY; +- } +- +- return 0; +-} +- +-static int +-nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_dmac *mast = (void *)object; +- +- /* deactivate channel */ +- nv_mask(priv, 0x610490, 0x00000010, 0x00000000); +- nv_mask(priv, 0x610490, 0x00000003, 0x00000000); +- if (!nv_wait(priv, 0x610490, 0x001e0000, 0x00000000)) { +- nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490)); +- if (suspend) +- return -EBUSY; +- } +- +- /* disable error reporting and completion notification */ +- nv_mask(priv, 0x610090, 0x00000001, 0x00000000); +- nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000); +- +- return nv50_disp_chan_fini(&mast->base, suspend); +-} +- +-struct nv50_disp_chan_impl +-nvd0_disp_mast_ofuncs = { +- .base.ctor = nv50_disp_mast_ctor, +- .base.dtor = nv50_disp_dmac_dtor, +- .base.init = nvd0_disp_mast_init, +- .base.fini = nvd0_disp_mast_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 0, +- .attach = nvd0_disp_dmac_object_attach, +- .detach = nvd0_disp_dmac_object_detach, +-}; +- +-/******************************************************************************* +- * EVO sync channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nvd0_disp_sync_mthd_base = { +- .mthd = 0x0000, +- .addr = 0x000000, +- .data = { +- { 0x0080, 0x661080 }, +- { 0x0084, 0x661084 }, +- { 0x0088, 0x661088 }, +- { 0x008c, 0x66108c }, +- { 0x0090, 0x661090 }, +- { 0x0094, 0x661094 }, +- { 0x00a0, 0x6610a0 }, +- { 0x00a4, 0x6610a4 }, +- { 0x00c0, 0x6610c0 }, +- { 0x00c4, 0x6610c4 }, +- { 0x00c8, 0x6610c8 }, +- { 0x00cc, 0x6610cc }, +- { 0x00e0, 0x6610e0 }, +- { 0x00e4, 0x6610e4 }, +- { 0x00e8, 0x6610e8 }, +- { 0x00ec, 0x6610ec }, +- { 0x00fc, 0x6610fc }, +- { 0x0100, 0x661100 }, +- { 0x0104, 0x661104 }, +- { 0x0108, 0x661108 }, +- { 0x010c, 0x66110c }, +- { 0x0110, 0x661110 }, +- { 0x0114, 0x661114 }, +- { 0x0118, 0x661118 }, +- { 0x011c, 0x66111c }, +- { 0x0130, 0x661130 }, +- { 0x0134, 0x661134 }, +- { 0x0138, 0x661138 }, +- { 0x013c, 0x66113c }, +- { 0x0140, 0x661140 }, +- { 0x0144, 0x661144 }, +- { 0x0148, 0x661148 }, +- { 0x014c, 0x66114c }, +- { 0x0150, 0x661150 }, +- { 0x0154, 0x661154 }, +- { 0x0158, 0x661158 }, +- { 0x015c, 0x66115c }, +- { 0x0160, 0x661160 }, +- { 0x0164, 0x661164 }, +- { 0x0168, 0x661168 }, +- { 0x016c, 0x66116c }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_list +-nvd0_disp_sync_mthd_image = { +- .mthd = 0x0400, +- .addr = 0x000400, +- .data = { +- { 0x0400, 0x661400 }, +- { 0x0404, 0x661404 }, +- { 0x0408, 0x661408 }, +- { 0x040c, 0x66140c }, +- { 0x0410, 0x661410 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nvd0_disp_sync_mthd_chan = { +- .name = "Base", +- .addr = 0x001000, +- .data = { +- { "Global", 1, &nvd0_disp_sync_mthd_base }, +- { "Image", 2, &nvd0_disp_sync_mthd_image }, +- {} +- } +-}; +- +-struct nv50_disp_chan_impl +-nvd0_disp_sync_ofuncs = { +- .base.ctor = nv50_disp_sync_ctor, +- .base.dtor = nv50_disp_dmac_dtor, +- .base.init = nvd0_disp_dmac_init, +- .base.fini = nvd0_disp_dmac_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 1, +- .attach = nvd0_disp_dmac_object_attach, +- .detach = nvd0_disp_dmac_object_detach, +-}; +- +-/******************************************************************************* +- * EVO overlay channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nvd0_disp_ovly_mthd_base = { +- .mthd = 0x0000, +- .data = { +- { 0x0080, 0x665080 }, +- { 0x0084, 0x665084 }, +- { 0x0088, 0x665088 }, +- { 0x008c, 0x66508c }, +- { 0x0090, 0x665090 }, +- { 0x0094, 0x665094 }, +- { 0x00a0, 0x6650a0 }, +- { 0x00a4, 0x6650a4 }, +- { 0x00b0, 0x6650b0 }, +- { 0x00b4, 0x6650b4 }, +- { 0x00b8, 0x6650b8 }, +- { 0x00c0, 0x6650c0 }, +- { 0x00e0, 0x6650e0 }, +- { 0x00e4, 0x6650e4 }, +- { 0x00e8, 0x6650e8 }, +- { 0x0100, 0x665100 }, +- { 0x0104, 0x665104 }, +- { 0x0108, 0x665108 }, +- { 0x010c, 0x66510c }, +- { 0x0110, 0x665110 }, +- { 0x0118, 0x665118 }, +- { 0x011c, 0x66511c }, +- { 0x0120, 0x665120 }, +- { 0x0124, 0x665124 }, +- { 0x0130, 0x665130 }, +- { 0x0134, 0x665134 }, +- { 0x0138, 0x665138 }, +- { 0x013c, 0x66513c }, +- { 0x0140, 0x665140 }, +- { 0x0144, 0x665144 }, +- { 0x0148, 0x665148 }, +- { 0x014c, 0x66514c }, +- { 0x0150, 0x665150 }, +- { 0x0154, 0x665154 }, +- { 0x0158, 0x665158 }, +- { 0x015c, 0x66515c }, +- { 0x0160, 0x665160 }, +- { 0x0164, 0x665164 }, +- { 0x0168, 0x665168 }, +- { 0x016c, 0x66516c }, +- { 0x0400, 0x665400 }, +- { 0x0408, 0x665408 }, +- { 0x040c, 0x66540c }, +- { 0x0410, 0x665410 }, +- {} +- } +-}; +- +-static const struct nv50_disp_mthd_chan +-nvd0_disp_ovly_mthd_chan = { +- .name = "Overlay", +- .addr = 0x001000, +- .data = { +- { "Global", 1, &nvd0_disp_ovly_mthd_base }, +- {} +- } +-}; +- +-struct nv50_disp_chan_impl +-nvd0_disp_ovly_ofuncs = { +- .base.ctor = nv50_disp_ovly_ctor, +- .base.dtor = nv50_disp_dmac_dtor, +- .base.init = nvd0_disp_dmac_init, +- .base.fini = nvd0_disp_dmac_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 5, +- .attach = nvd0_disp_dmac_object_attach, +- .detach = nvd0_disp_dmac_object_detach, +-}; +- +-/******************************************************************************* +- * EVO PIO channel base class +- ******************************************************************************/ +- +-static int +-nvd0_disp_pioc_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_pioc *pioc = (void *)object; +- int chid = pioc->base.chid; +- int ret; +- +- ret = nv50_disp_chan_init(&pioc->base); +- if (ret) +- return ret; +- +- /* enable error reporting */ +- nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); +- +- /* activate channel */ +- nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001); +- if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) { +- nv_error(pioc, "init: 0x%08x\n", +- nv_rd32(priv, 0x610490 + (chid * 0x10))); +- return -EBUSY; +- } +- +- return 0; +-} +- +-static int +-nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_pioc *pioc = (void *)object; +- int chid = pioc->base.chid; +- +- nv_mask(priv, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); +- if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) { +- nv_error(pioc, "timeout: 0x%08x\n", +- nv_rd32(priv, 0x610490 + (chid * 0x10))); +- if (suspend) +- return -EBUSY; +- } +- +- /* disable error reporting and completion notification */ +- nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); +- nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); +- +- return nv50_disp_chan_fini(&pioc->base, suspend); +-} +- +-/******************************************************************************* +- * EVO immediate overlay channel objects +- ******************************************************************************/ +- +-struct nv50_disp_chan_impl +-nvd0_disp_oimm_ofuncs = { +- .base.ctor = nv50_disp_oimm_ctor, +- .base.dtor = nv50_disp_pioc_dtor, +- .base.init = nvd0_disp_pioc_init, +- .base.fini = nvd0_disp_pioc_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 9, +-}; +- +-/******************************************************************************* +- * EVO cursor channel objects +- ******************************************************************************/ +- +-struct nv50_disp_chan_impl +-nvd0_disp_curs_ofuncs = { +- .base.ctor = nv50_disp_curs_ctor, +- .base.dtor = nv50_disp_pioc_dtor, +- .base.init = nvd0_disp_pioc_init, +- .base.fini = nvd0_disp_pioc_fini, +- .base.ntfy = nv50_disp_chan_ntfy, +- .base.map = nv50_disp_chan_map, +- .base.rd32 = nv50_disp_chan_rd32, +- .base.wr32 = nv50_disp_chan_wr32, +- .chid = 13, +-}; +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-int +-nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0) +-{ +- const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300)); +- const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300)); +- const u32 blanks = nv_rd32(priv, 0x640420 + (head * 0x300)); +- union { +- struct nv04_disp_scanoutpos_v0 v0; +- } *args = data; +- int ret; +- +- nv_ioctl(object, "disp scanoutpos size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); +- args->v0.vblanke = (blanke & 0xffff0000) >> 16; +- args->v0.hblanke = (blanke & 0x0000ffff); +- args->v0.vblanks = (blanks & 0xffff0000) >> 16; +- args->v0.hblanks = (blanks & 0x0000ffff); +- args->v0.vtotal = ( total & 0xffff0000) >> 16; +- args->v0.htotal = ( total & 0x0000ffff); +- args->v0.time[0] = ktime_to_ns(ktime_get()); +- args->v0.vline = /* vline read locks hline */ +- nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; +- args->v0.time[1] = ktime_to_ns(ktime_get()); +- args->v0.hline = +- nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff; +- } else +- return ret; +- +- return 0; +-} +- +-static int +-nvd0_disp_base_init(struct nouveau_object *object) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_base *base = (void *)object; +- int ret, i; +- u32 tmp; +- +- ret = nouveau_parent_init(&base->base); +- if (ret) +- return ret; +- +- /* The below segments of code copying values from one register to +- * another appear to inform EVO of the display capabilities or +- * something similar. +- */ +- +- /* ... CRTC caps */ +- for (i = 0; i < priv->head.nr; i++) { +- tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); +- nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp); +- tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); +- nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp); +- tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); +- nv_wr32(priv, 0x6101bc + (i * 0x800), tmp); +- } +- +- /* ... DAC caps */ +- for (i = 0; i < priv->dac.nr; i++) { +- tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); +- nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp); +- } +- +- /* ... SOR caps */ +- for (i = 0; i < priv->sor.nr; i++) { +- tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); +- nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp); +- } +- +- /* steal display away from vbios, or something like that */ +- if (nv_rd32(priv, 0x6100ac) & 0x00000100) { +- nv_wr32(priv, 0x6100ac, 0x00000100); +- nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); +- if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { +- nv_error(priv, "timeout acquiring display\n"); +- return -EBUSY; +- } +- } +- +- /* point at display engine memory area (hash table, objects) */ +- nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9); +- +- /* enable supervisor interrupts, disable everything else */ +- nv_wr32(priv, 0x610090, 0x00000000); +- nv_wr32(priv, 0x6100a0, 0x00000000); +- nv_wr32(priv, 0x6100b0, 0x00000307); +- +- /* disable underflow reporting, preventing an intermittent issue +- * on some nve4 boards where the production vbios left this +- * setting enabled by default. +- * +- * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt +- */ +- for (i = 0; i < priv->head.nr; i++) +- nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); +- +- return 0; +-} +- +-static int +-nvd0_disp_base_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_disp_priv *priv = (void *)object->engine; +- struct nv50_disp_base *base = (void *)object; +- +- /* disable all interrupts */ +- nv_wr32(priv, 0x6100b0, 0x00000000); +- +- return nouveau_parent_fini(&base->base, suspend); +-} +- +-struct nouveau_ofuncs +-nvd0_disp_base_ofuncs = { +- .ctor = nv50_disp_base_ctor, +- .dtor = nv50_disp_base_dtor, +- .init = nvd0_disp_base_init, +- .fini = nvd0_disp_base_fini, +- .mthd = nv50_disp_base_mthd, +- .ntfy = nouveau_disp_ntfy, +-}; +- +-static struct nouveau_oclass +-nvd0_disp_base_oclass[] = { +- { GF110_DISP, &nvd0_disp_base_ofuncs }, +- {} +-}; +- +-static struct nouveau_oclass +-nvd0_disp_sclass[] = { +- { GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, +- { GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, +- { GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, +- { GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, +- { GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static void +-nvd0_disp_vblank_init(struct nvkm_event *event, int type, int head) +-{ +- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); +- nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001); +-} +- +-static void +-nvd0_disp_vblank_fini(struct nvkm_event *event, int type, int head) +-{ +- struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank); +- nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000); +-} +- +-const struct nvkm_event_func +-nvd0_disp_vblank_func = { +- .ctor = nouveau_disp_vblank_ctor, +- .init = nvd0_disp_vblank_init, +- .fini = nvd0_disp_vblank_fini, +-}; +- +-static struct nvkm_output * +-exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, +- u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_outp *info) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvkm_output *outp; +- u16 mask, type; +- +- if (or < 4) { +- type = DCB_OUTPUT_ANALOG; +- mask = 0; +- } else { +- or -= 4; +- switch (ctrl & 0x00000f00) { +- case 0x00000000: type = DCB_OUTPUT_LVDS; mask = 1; break; +- case 0x00000100: type = DCB_OUTPUT_TMDS; mask = 1; break; +- case 0x00000200: type = DCB_OUTPUT_TMDS; mask = 2; break; +- case 0x00000500: type = DCB_OUTPUT_TMDS; mask = 3; break; +- case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; +- case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; +- default: +- nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); +- return 0x0000; +- } +- } +- +- mask = 0x00c0 & (mask << 6); +- mask |= 0x0001 << or; +- mask |= 0x0100 << head; +- +- list_for_each_entry(outp, &priv->base.outp, head) { +- if ((outp->info.hasht & 0xff) == type && +- (outp->info.hashm & mask) == mask) { +- *data = nvbios_outp_match(bios, outp->info.hasht, +- outp->info.hashm, +- ver, hdr, cnt, len, info); +- if (!*data) +- return NULL; +- return outp; +- } +- } +- +- return NULL; +-} +- +-static struct nvkm_output * +-exec_script(struct nv50_disp_priv *priv, int head, int id) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvkm_output *outp; +- struct nvbios_outp info; +- u8 ver, hdr, cnt, len; +- u32 data, ctrl = 0; +- int or; +- +- for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { +- ctrl = nv_rd32(priv, 0x640180 + (or * 0x20)); +- if (ctrl & (1 << head)) +- break; +- } +- +- if (or == 8) +- return NULL; +- +- outp = exec_lookup(priv, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info); +- if (outp) { +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = bios, +- .offset = info.script[id], +- .outp = &outp->info, +- .crtc = head, +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- } +- +- return outp; +-} +- +-static struct nvkm_output * +-exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvkm_output *outp; +- struct nvbios_outp info1; +- struct nvbios_ocfg info2; +- u8 ver, hdr, cnt, len; +- u32 data, ctrl = 0; +- int or; +- +- for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { +- ctrl = nv_rd32(priv, 0x660180 + (or * 0x20)); +- if (ctrl & (1 << head)) +- break; +- } +- +- if (or == 8) +- return NULL; +- +- outp = exec_lookup(priv, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); +- if (!outp) +- return NULL; +- +- switch (outp->info.type) { +- case DCB_OUTPUT_TMDS: +- *conf = (ctrl & 0x00000f00) >> 8; +- if (pclk >= 165000) +- *conf |= 0x0100; +- break; +- case DCB_OUTPUT_LVDS: +- *conf = priv->sor.lvdsconf; +- break; +- case DCB_OUTPUT_DP: +- *conf = (ctrl & 0x00000f00) >> 8; +- break; +- case DCB_OUTPUT_ANALOG: +- default: +- *conf = 0x00ff; +- break; +- } +- +- data = nvbios_ocfg_match(bios, data, *conf, &ver, &hdr, &cnt, &len, &info2); +- if (data && id < 0xff) { +- data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); +- if (data) { +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = bios, +- .offset = data, +- .outp = &outp->info, +- .crtc = head, +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- } +- } +- +- return outp; +-} +- +-static void +-nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head) +-{ +- exec_script(priv, head, 1); +-} +- +-static void +-nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) +-{ +- struct nvkm_output *outp = exec_script(priv, head, 2); +- +- /* see note in nv50_disp_intr_unk20_0() */ +- if (outp && outp->info.type == DCB_OUTPUT_DP) { +- struct nvkm_output_dp *outpdp = (void *)outp; +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = nouveau_bios(priv), +- .outp = &outp->info, +- .crtc = head, +- .offset = outpdp->info.script[4], +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- atomic_set(&outpdp->lt.done, 0); +- } +-} +- +-static void +-nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head) +-{ +- struct nouveau_devinit *devinit = nouveau_devinit(priv); +- u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; +- if (pclk) +- devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); +- nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000); +-} +- +-static void +-nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, +- struct dcb_output *outp) +-{ +- const int or = ffs(outp->or) - 1; +- const u32 ctrl = nv_rd32(priv, 0x660200 + (or * 0x020)); +- const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300)); +- const s32 vactive = nv_rd32(priv, 0x660414 + (head * 0x300)) & 0xffff; +- const s32 vblanke = nv_rd32(priv, 0x66041c + (head * 0x300)) & 0xffff; +- const s32 vblanks = nv_rd32(priv, 0x660420 + (head * 0x300)) & 0xffff; +- const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; +- const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1; +- const u32 hoff = (head * 0x800); +- const u32 soff = ( or * 0x800); +- const u32 loff = (link * 0x080) + soff; +- const u32 symbol = 100000; +- const u32 TU = 64; +- u32 dpctrl = nv_rd32(priv, 0x61c10c + loff); +- u32 clksor = nv_rd32(priv, 0x612300 + soff); +- u32 datarate, link_nr, link_bw, bits; +- u64 ratio, value; +- +- link_nr = hweight32(dpctrl & 0x000f0000); +- link_bw = (clksor & 0x007c0000) >> 18; +- link_bw *= 27000; +- +- /* symbols/hblank - algorithm taken from comments in tegra driver */ +- value = vblanke + vactive - vblanks - 7; +- value = value * link_bw; +- do_div(value, pclk); +- value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); +- nv_mask(priv, 0x616620 + hoff, 0x0000ffff, value); +- +- /* symbols/vblank - algorithm taken from comments in tegra driver */ +- value = vblanks - vblanke - 25; +- value = value * link_bw; +- do_div(value, pclk); +- value = value - ((36 / link_nr) + 3) - 1; +- nv_mask(priv, 0x616624 + hoff, 0x00ffffff, value); +- +- /* watermark */ +- if ((conf & 0x3c0) == 0x180) bits = 30; +- else if ((conf & 0x3c0) == 0x140) bits = 24; +- else bits = 18; +- datarate = (pclk * bits) / 8; +- +- ratio = datarate; +- ratio *= symbol; +- do_div(ratio, link_nr * link_bw); +- +- value = (symbol - ratio) * TU; +- value *= ratio; +- do_div(value, symbol); +- do_div(value, symbol); +- +- value += 5; +- value |= 0x08000000; +- +- nv_wr32(priv, 0x616610 + hoff, value); +-} +- +-static void +-nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) +-{ +- struct nvkm_output *outp; +- u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; +- u32 conf, addr, data; +- +- outp = exec_clkcmp(priv, head, 0xff, pclk, &conf); +- if (!outp) +- return; +- +- /* see note in nv50_disp_intr_unk20_2() */ +- if (outp->info.type == DCB_OUTPUT_DP) { +- u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300)); +- switch ((sync & 0x000003c0) >> 6) { +- case 6: pclk = pclk * 30; break; +- case 5: pclk = pclk * 24; break; +- case 2: +- default: +- pclk = pclk * 18; +- break; +- } +- +- if (nvkm_output_dp_train(outp, pclk, true)) +- ERR("link not trained before attach\n"); +- } +- +- exec_clkcmp(priv, head, 0, pclk, &conf); +- +- if (outp->info.type == DCB_OUTPUT_ANALOG) { +- addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800; +- data = 0x00000000; +- } else { +- if (outp->info.type == DCB_OUTPUT_DP) +- nvd0_disp_intr_unk2_2_tu(priv, head, &outp->info); +- addr = 0x612300 + (ffs(outp->info.or) - 1) * 0x800; +- data = (conf & 0x0100) ? 0x00000101 : 0x00000000; +- } +- +- nv_mask(priv, addr, 0x00000707, data); +-} +- +-static void +-nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head) +-{ +- u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; +- u32 conf; +- +- exec_clkcmp(priv, head, 1, pclk, &conf); +-} +- +-void +-nvd0_disp_intr_supervisor(struct work_struct *work) +-{ +- struct nv50_disp_priv *priv = +- container_of(work, struct nv50_disp_priv, supervisor); +- struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; +- u32 mask[4]; +- int head; +- +- nv_debug(priv, "supervisor %d\n", ffs(priv->super)); +- for (head = 0; head < priv->head.nr; head++) { +- mask[head] = nv_rd32(priv, 0x6101d4 + (head * 0x800)); +- nv_debug(priv, "head %d: 0x%08x\n", head, mask[head]); +- } +- +- if (priv->super & 0x00000001) { +- nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core); +- for (head = 0; head < priv->head.nr; head++) { +- if (!(mask[head] & 0x00001000)) +- continue; +- nv_debug(priv, "supervisor 1.0 - head %d\n", head); +- nvd0_disp_intr_unk1_0(priv, head); +- } +- } else +- if (priv->super & 0x00000002) { +- for (head = 0; head < priv->head.nr; head++) { +- if (!(mask[head] & 0x00001000)) +- continue; +- nv_debug(priv, "supervisor 2.0 - head %d\n", head); +- nvd0_disp_intr_unk2_0(priv, head); +- } +- for (head = 0; head < priv->head.nr; head++) { +- if (!(mask[head] & 0x00010000)) +- continue; +- nv_debug(priv, "supervisor 2.1 - head %d\n", head); +- nvd0_disp_intr_unk2_1(priv, head); +- } +- for (head = 0; head < priv->head.nr; head++) { +- if (!(mask[head] & 0x00001000)) +- continue; +- nv_debug(priv, "supervisor 2.2 - head %d\n", head); +- nvd0_disp_intr_unk2_2(priv, head); +- } +- } else +- if (priv->super & 0x00000004) { +- for (head = 0; head < priv->head.nr; head++) { +- if (!(mask[head] & 0x00001000)) +- continue; +- nv_debug(priv, "supervisor 3.0 - head %d\n", head); +- nvd0_disp_intr_unk4_0(priv, head); +- } +- } +- +- for (head = 0; head < priv->head.nr; head++) +- nv_wr32(priv, 0x6101d4 + (head * 0x800), 0x00000000); +- nv_wr32(priv, 0x6101d0, 0x80000000); +-} +- +-static void +-nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid) +-{ +- const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; +- u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12)); +- u32 data = nv_rd32(priv, 0x6101f4 + (chid * 12)); +- u32 unkn = nv_rd32(priv, 0x6101f8 + (chid * 12)); +- +- nv_error(priv, "chid %d mthd 0x%04x data 0x%08x " +- "0x%08x 0x%08x\n", +- chid, (mthd & 0x0000ffc), data, mthd, unkn); +- +- if (chid == 0) { +- switch (mthd & 0xffc) { +- case 0x0080: +- nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, +- impl->mthd.core); +- break; +- default: +- break; +- } +- } else +- if (chid <= 4) { +- switch (mthd & 0xffc) { +- case 0x0080: +- nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, +- impl->mthd.base); +- break; +- default: +- break; +- } +- } else +- if (chid <= 8) { +- switch (mthd & 0xffc) { +- case 0x0080: +- nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 5, +- impl->mthd.ovly); +- break; +- default: +- break; +- } +- } +- +- nv_wr32(priv, 0x61009c, (1 << chid)); +- nv_wr32(priv, 0x6101f0 + (chid * 12), 0x90000000); +-} +- +-void +-nvd0_disp_intr(struct nouveau_subdev *subdev) +-{ +- struct nv50_disp_priv *priv = (void *)subdev; +- u32 intr = nv_rd32(priv, 0x610088); +- int i; +- +- if (intr & 0x00000001) { +- u32 stat = nv_rd32(priv, 0x61008c); +- while (stat) { +- int chid = __ffs(stat); stat &= ~(1 << chid); +- nv50_disp_chan_uevent_send(priv, chid); +- nv_wr32(priv, 0x61008c, 1 << chid); +- } +- intr &= ~0x00000001; +- } +- +- if (intr & 0x00000002) { +- u32 stat = nv_rd32(priv, 0x61009c); +- int chid = ffs(stat) - 1; +- if (chid >= 0) +- nvd0_disp_intr_error(priv, chid); +- intr &= ~0x00000002; +- } +- +- if (intr & 0x00100000) { +- u32 stat = nv_rd32(priv, 0x6100ac); +- if (stat & 0x00000007) { +- priv->super = (stat & 0x00000007); +- schedule_work(&priv->supervisor); +- nv_wr32(priv, 0x6100ac, priv->super); +- stat &= ~0x00000007; +- } +- +- if (stat) { +- nv_info(priv, "unknown intr24 0x%08x\n", stat); +- nv_wr32(priv, 0x6100ac, stat); +- } +- +- intr &= ~0x00100000; +- } +- +- for (i = 0; i < priv->head.nr; i++) { +- u32 mask = 0x01000000 << i; +- if (mask & intr) { +- u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800)); +- if (stat & 0x00000001) +- nouveau_disp_vblank(&priv->base, i); +- nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0); +- nv_rd32(priv, 0x6100c0 + (i * 0x800)); +- } +- } +-} +- +-static int +-nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int heads = nv_rd32(parent, 0x022448); +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, heads, +- "PDISP", "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nvd0_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nvd0_disp_intr; +- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); +- priv->sclass = nvd0_disp_sclass; +- priv->head.nr = heads; +- priv->dac.nr = 3; +- priv->sor.nr = 4; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hda_eld = nvd0_hda_eld; +- priv->sor.hdmi = nvd0_hdmi_ctrl; +- return 0; +-} +- +-struct nouveau_oclass * +-nvd0_disp_outp_sclass[] = { +- &nvd0_sor_dp_impl.base.base, +- NULL +-}; +- +-struct nouveau_oclass * +-nvd0_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x90), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvd0_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nvd0_disp_vblank_func, +- .base.outp = nvd0_disp_outp_sclass, +- .mthd.core = &nvd0_disp_mast_mthd_chan, +- .mthd.base = &nvd0_disp_sync_mthd_chan, +- .mthd.ovly = &nvd0_disp_ovly_mthd_chan, +- .mthd.prev = -0x020000, +- .head.scanoutpos = nvd0_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c +deleted file mode 100644 +index db144b2c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nve0.c ++++ /dev/null +@@ -1,272 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * EVO master channel object +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nve0_disp_mast_mthd_head = { +- .mthd = 0x0300, +- .addr = 0x000300, +- .data = { +- { 0x0400, 0x660400 }, +- { 0x0404, 0x660404 }, +- { 0x0408, 0x660408 }, +- { 0x040c, 0x66040c }, +- { 0x0410, 0x660410 }, +- { 0x0414, 0x660414 }, +- { 0x0418, 0x660418 }, +- { 0x041c, 0x66041c }, +- { 0x0420, 0x660420 }, +- { 0x0424, 0x660424 }, +- { 0x0428, 0x660428 }, +- { 0x042c, 0x66042c }, +- { 0x0430, 0x660430 }, +- { 0x0434, 0x660434 }, +- { 0x0438, 0x660438 }, +- { 0x0440, 0x660440 }, +- { 0x0444, 0x660444 }, +- { 0x0448, 0x660448 }, +- { 0x044c, 0x66044c }, +- { 0x0450, 0x660450 }, +- { 0x0454, 0x660454 }, +- { 0x0458, 0x660458 }, +- { 0x045c, 0x66045c }, +- { 0x0460, 0x660460 }, +- { 0x0468, 0x660468 }, +- { 0x046c, 0x66046c }, +- { 0x0470, 0x660470 }, +- { 0x0474, 0x660474 }, +- { 0x047c, 0x66047c }, +- { 0x0480, 0x660480 }, +- { 0x0484, 0x660484 }, +- { 0x0488, 0x660488 }, +- { 0x048c, 0x66048c }, +- { 0x0490, 0x660490 }, +- { 0x0494, 0x660494 }, +- { 0x0498, 0x660498 }, +- { 0x04a0, 0x6604a0 }, +- { 0x04b0, 0x6604b0 }, +- { 0x04b8, 0x6604b8 }, +- { 0x04bc, 0x6604bc }, +- { 0x04c0, 0x6604c0 }, +- { 0x04c4, 0x6604c4 }, +- { 0x04c8, 0x6604c8 }, +- { 0x04d0, 0x6604d0 }, +- { 0x04d4, 0x6604d4 }, +- { 0x04e0, 0x6604e0 }, +- { 0x04e4, 0x6604e4 }, +- { 0x04e8, 0x6604e8 }, +- { 0x04ec, 0x6604ec }, +- { 0x04f0, 0x6604f0 }, +- { 0x04f4, 0x6604f4 }, +- { 0x04f8, 0x6604f8 }, +- { 0x04fc, 0x6604fc }, +- { 0x0500, 0x660500 }, +- { 0x0504, 0x660504 }, +- { 0x0508, 0x660508 }, +- { 0x050c, 0x66050c }, +- { 0x0510, 0x660510 }, +- { 0x0514, 0x660514 }, +- { 0x0518, 0x660518 }, +- { 0x051c, 0x66051c }, +- { 0x0520, 0x660520 }, +- { 0x0524, 0x660524 }, +- { 0x052c, 0x66052c }, +- { 0x0530, 0x660530 }, +- { 0x054c, 0x66054c }, +- { 0x0550, 0x660550 }, +- { 0x0554, 0x660554 }, +- { 0x0558, 0x660558 }, +- { 0x055c, 0x66055c }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nve0_disp_mast_mthd_chan = { +- .name = "Core", +- .addr = 0x000000, +- .data = { +- { "Global", 1, &nvd0_disp_mast_mthd_base }, +- { "DAC", 3, &nvd0_disp_mast_mthd_dac }, +- { "SOR", 8, &nvd0_disp_mast_mthd_sor }, +- { "PIOR", 4, &nvd0_disp_mast_mthd_pior }, +- { "HEAD", 4, &nve0_disp_mast_mthd_head }, +- {} +- } +-}; +- +-/******************************************************************************* +- * EVO overlay channel objects +- ******************************************************************************/ +- +-static const struct nv50_disp_mthd_list +-nve0_disp_ovly_mthd_base = { +- .mthd = 0x0000, +- .data = { +- { 0x0080, 0x665080 }, +- { 0x0084, 0x665084 }, +- { 0x0088, 0x665088 }, +- { 0x008c, 0x66508c }, +- { 0x0090, 0x665090 }, +- { 0x0094, 0x665094 }, +- { 0x00a0, 0x6650a0 }, +- { 0x00a4, 0x6650a4 }, +- { 0x00b0, 0x6650b0 }, +- { 0x00b4, 0x6650b4 }, +- { 0x00b8, 0x6650b8 }, +- { 0x00c0, 0x6650c0 }, +- { 0x00c4, 0x6650c4 }, +- { 0x00e0, 0x6650e0 }, +- { 0x00e4, 0x6650e4 }, +- { 0x00e8, 0x6650e8 }, +- { 0x0100, 0x665100 }, +- { 0x0104, 0x665104 }, +- { 0x0108, 0x665108 }, +- { 0x010c, 0x66510c }, +- { 0x0110, 0x665110 }, +- { 0x0118, 0x665118 }, +- { 0x011c, 0x66511c }, +- { 0x0120, 0x665120 }, +- { 0x0124, 0x665124 }, +- { 0x0130, 0x665130 }, +- { 0x0134, 0x665134 }, +- { 0x0138, 0x665138 }, +- { 0x013c, 0x66513c }, +- { 0x0140, 0x665140 }, +- { 0x0144, 0x665144 }, +- { 0x0148, 0x665148 }, +- { 0x014c, 0x66514c }, +- { 0x0150, 0x665150 }, +- { 0x0154, 0x665154 }, +- { 0x0158, 0x665158 }, +- { 0x015c, 0x66515c }, +- { 0x0160, 0x665160 }, +- { 0x0164, 0x665164 }, +- { 0x0168, 0x665168 }, +- { 0x016c, 0x66516c }, +- { 0x0400, 0x665400 }, +- { 0x0404, 0x665404 }, +- { 0x0408, 0x665408 }, +- { 0x040c, 0x66540c }, +- { 0x0410, 0x665410 }, +- {} +- } +-}; +- +-const struct nv50_disp_mthd_chan +-nve0_disp_ovly_mthd_chan = { +- .name = "Overlay", +- .addr = 0x001000, +- .data = { +- { "Global", 1, &nve0_disp_ovly_mthd_base }, +- {} +- } +-}; +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve0_disp_sclass[] = { +- { GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, +- { GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, +- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, +- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, +- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-nve0_disp_base_oclass[] = { +- { GK104_DISP, &nvd0_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int heads = nv_rd32(parent, 0x022448); +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, heads, +- "PDISP", "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nve0_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nvd0_disp_intr; +- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); +- priv->sclass = nve0_disp_sclass; +- priv->head.nr = heads; +- priv->dac.nr = 3; +- priv->sor.nr = 4; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hda_eld = nvd0_hda_eld; +- priv->sor.hdmi = nve0_hdmi_ctrl; +- return 0; +-} +- +-struct nouveau_oclass * +-nve0_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x91), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nvd0_disp_vblank_func, +- .base.outp = nvd0_disp_outp_sclass, +- .mthd.core = &nve0_disp_mast_mthd_chan, +- .mthd.base = &nvd0_disp_sync_mthd_chan, +- .mthd.ovly = &nve0_disp_ovly_mthd_chan, +- .mthd.prev = -0x020000, +- .head.scanoutpos = nvd0_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c +deleted file mode 100644 +index 402d7d67..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvf0.c ++++ /dev/null +@@ -1,107 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * Base display object +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvf0_disp_sclass[] = { +- { GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base }, +- { GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base }, +- { GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base }, +- { GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base }, +- { GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base }, +- {} +-}; +- +-static struct nouveau_oclass +-nvf0_disp_base_oclass[] = { +- { GK110_DISP, &nvd0_disp_base_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * Display engine implementation +- ******************************************************************************/ +- +-static int +-nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_disp_priv *priv; +- int heads = nv_rd32(parent, 0x022448); +- int ret; +- +- ret = nouveau_disp_create(parent, engine, oclass, heads, +- "PDISP", "display", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent); +- if (ret) +- return ret; +- +- nv_engine(priv)->sclass = nvf0_disp_base_oclass; +- nv_engine(priv)->cclass = &nv50_disp_cclass; +- nv_subdev(priv)->intr = nvd0_disp_intr; +- INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor); +- priv->sclass = nvf0_disp_sclass; +- priv->head.nr = heads; +- priv->dac.nr = 3; +- priv->sor.nr = 4; +- priv->dac.power = nv50_dac_power; +- priv->dac.sense = nv50_dac_sense; +- priv->sor.power = nv50_sor_power; +- priv->sor.hda_eld = nvd0_hda_eld; +- priv->sor.hdmi = nve0_hdmi_ctrl; +- return 0; +-} +- +-struct nouveau_oclass * +-nvf0_disp_oclass = &(struct nv50_disp_impl) { +- .base.base.handle = NV_ENGINE(DISP, 0x92), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvf0_disp_ctor, +- .dtor = _nouveau_disp_dtor, +- .init = _nouveau_disp_init, +- .fini = _nouveau_disp_fini, +- }, +- .base.vblank = &nvd0_disp_vblank_func, +- .base.outp = nvd0_disp_outp_sclass, +- .mthd.core = &nve0_disp_mast_mthd_chan, +- .mthd.base = &nvd0_disp_sync_mthd_chan, +- .mthd.ovly = &nve0_disp_ovly_mthd_chan, +- .mthd.prev = -0x020000, +- .head.scanoutpos = nvd0_disp_base_scanoutpos, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outp.c +deleted file mode 100644 +index a5ff00a9..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.c ++++ /dev/null +@@ -1,138 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "outp.h" +- +-int +-_nvkm_output_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvkm_output *outp = (void *)object; +- nv_ofuncs(outp->conn)->fini(nv_object(outp->conn), suspend); +- return nouveau_object_fini(&outp->base, suspend); +-} +- +-int +-_nvkm_output_init(struct nouveau_object *object) +-{ +- struct nvkm_output *outp = (void *)object; +- int ret = nouveau_object_init(&outp->base); +- if (ret == 0) +- nv_ofuncs(outp->conn)->init(nv_object(outp->conn)); +- return 0; +-} +- +-void +-_nvkm_output_dtor(struct nouveau_object *object) +-{ +- struct nvkm_output *outp = (void *)object; +- list_del(&outp->head); +- nouveau_object_ref(NULL, (void *)&outp->conn); +- nouveau_object_destroy(&outp->base); +-} +- +-int +-nvkm_output_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- struct dcb_output *dcbE, int index, +- int length, void **pobject) +-{ +- struct nouveau_bios *bios = nouveau_bios(engine); +- struct nouveau_i2c *i2c = nouveau_i2c(parent); +- struct nouveau_disp *disp = (void *)engine; +- struct nvbios_connE connE; +- struct nvkm_output *outp; +- u8 ver, hdr; +- u32 data; +- int ret; +- +- ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject); +- outp = *pobject; +- if (ret) +- return ret; +- +- outp->info = *dcbE; +- outp->index = index; +- outp->or = ffs(outp->info.or) - 1; +- +- DBG("type %02x loc %d or %d link %d con %x edid %x bus %d head %x\n", +- dcbE->type, dcbE->location, dcbE->or, dcbE->type >= 2 ? +- dcbE->sorconf.link : 0, dcbE->connector, dcbE->i2c_index, +- dcbE->bus, dcbE->heads); +- +- outp->port = i2c->find(i2c, outp->info.i2c_index); +- outp->edid = outp->port; +- +- data = nvbios_connEp(bios, outp->info.connector, &ver, &hdr, &connE); +- if (!data) { +- DBG("vbios connector data not found\n"); +- memset(&connE, 0x00, sizeof(connE)); +- connE.type = DCB_CONNECTOR_NONE; +- } +- +- ret = nouveau_object_ctor(parent, engine, nvkm_connector_oclass, +- &connE, outp->info.connector, +- (struct nouveau_object **)&outp->conn); +- if (ret < 0) { +- ERR("error %d creating connector, disabling\n", ret); +- return ret; +- } +- +- list_add_tail(&outp->head, &disp->outp); +- return 0; +-} +- +-int +-_nvkm_output_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *dcbE, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nvkm_output *outp; +- int ret; +- +- ret = nvkm_output_create(parent, engine, oclass, dcbE, index, &outp); +- *pobject = nv_object(outp); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-nvkm_output_oclass = &(struct nvkm_output_impl) { +- .base = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_output_ctor, +- .dtor = _nvkm_output_dtor, +- .init = _nvkm_output_init, +- .fini = _nvkm_output_fini, +- }, +- }, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h b/drivers/gpu/drm/nouveau/core/engine/disp/outp.h +deleted file mode 100644 +index 187f435a..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/outp.h ++++ /dev/null +@@ -1,60 +0,0 @@ +-#ifndef __NVKM_DISP_OUTP_H__ +-#define __NVKM_DISP_OUTP_H__ +- +-#include "priv.h" +- +-struct nvkm_output { +- struct nouveau_object base; +- struct list_head head; +- +- struct dcb_output info; +- int index; +- int or; +- +- struct nouveau_i2c_port *port; +- struct nouveau_i2c_port *edid; +- +- struct nvkm_connector *conn; +-}; +- +-#define nvkm_output_create(p,e,c,b,i,d) \ +- nvkm_output_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d) +-#define nvkm_output_destroy(d) ({ \ +- struct nvkm_output *_outp = (d); \ +- _nvkm_output_dtor(nv_object(_outp)); \ +-}) +-#define nvkm_output_init(d) ({ \ +- struct nvkm_output *_outp = (d); \ +- _nvkm_output_init(nv_object(_outp)); \ +-}) +-#define nvkm_output_fini(d,s) ({ \ +- struct nvkm_output *_outp = (d); \ +- _nvkm_output_fini(nv_object(_outp), (s)); \ +-}) +- +-int nvkm_output_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, struct dcb_output *, +- int, int, void **); +- +-int _nvkm_output_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void _nvkm_output_dtor(struct nouveau_object *); +-int _nvkm_output_init(struct nouveau_object *); +-int _nvkm_output_fini(struct nouveau_object *, bool); +- +-struct nvkm_output_impl { +- struct nouveau_oclass base; +-}; +- +-#ifndef MSG +-#define MSG(l,f,a...) do { \ +- struct nvkm_output *_outp = (void *)outp; \ +- nv_##l(nv_object(outp)->engine, "%02x:%04x:%04x: "f, _outp->index, \ +- _outp->info.hasht, _outp->info.hashm, ##a); \ +-} while(0) +-#define DBG(f,a...) MSG(debug, f, ##a) +-#define ERR(f,a...) MSG(error, f, ##a) +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c +deleted file mode 100644 +index 667a9070..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.c ++++ /dev/null +@@ -1,302 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-#include "outpdp.h" +-#include "conn.h" +-#include "dport.h" +- +-int +-nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait) +-{ +- struct nvkm_output_dp *outp = (void *)base; +- bool retrain = true; +- u8 link[2], stat[3]; +- u32 linkrate; +- int ret, i; +- +- /* check that the link is trained at a high enough rate */ +- ret = nv_rdaux(outp->base.edid, DPCD_LC00_LINK_BW_SET, link, 2); +- if (ret) { +- DBG("failed to read link config, assuming no sink\n"); +- goto done; +- } +- +- linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET); +- linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */ +- datarate = (datarate + 9) / 10; /* -> decakilobits */ +- if (linkrate < datarate) { +- DBG("link not trained at sufficient rate\n"); +- goto done; +- } +- +- /* check that link is still trained */ +- ret = nv_rdaux(outp->base.edid, DPCD_LS02, stat, 3); +- if (ret) { +- DBG("failed to read link status, assuming no sink\n"); +- goto done; +- } +- +- if (stat[2] & DPCD_LS04_INTERLANE_ALIGN_DONE) { +- for (i = 0; i < (link[1] & DPCD_LC01_LANE_COUNT_SET); i++) { +- u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; +- if (!(lane & DPCD_LS02_LANE0_CR_DONE) || +- !(lane & DPCD_LS02_LANE0_CHANNEL_EQ_DONE) || +- !(lane & DPCD_LS02_LANE0_SYMBOL_LOCKED)) { +- DBG("lane %d not equalised\n", lane); +- goto done; +- } +- } +- retrain = false; +- } else { +- DBG("no inter-lane alignment\n"); +- } +- +-done: +- if (retrain || !atomic_read(&outp->lt.done)) { +- /* no sink, but still need to configure source */ +- if (outp->dpcd[DPCD_RC00_DPCD_REV] == 0x00) { +- outp->dpcd[DPCD_RC01_MAX_LINK_RATE] = +- outp->base.info.dpconf.link_bw; +- outp->dpcd[DPCD_RC02] = +- outp->base.info.dpconf.link_nr; +- } +- atomic_set(&outp->lt.done, 0); +- schedule_work(&outp->lt.work); +- } else { +- nvkm_notify_get(&outp->irq); +- } +- +- if (wait) { +- if (!wait_event_timeout(outp->lt.wait, +- atomic_read(&outp->lt.done), +- msecs_to_jiffies(2000))) +- ret = -ETIMEDOUT; +- } +- +- return ret; +-} +- +-static void +-nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present) +-{ +- struct nouveau_i2c_port *port = outp->base.edid; +- if (present) { +- if (!outp->present) { +- nouveau_i2c(port)->acquire_pad(port, 0); +- DBG("aux power -> always\n"); +- outp->present = true; +- } +- nvkm_output_dp_train(&outp->base, 0, true); +- } else { +- if (outp->present) { +- nouveau_i2c(port)->release_pad(port); +- DBG("aux power -> demand\n"); +- outp->present = false; +- } +- atomic_set(&outp->lt.done, 0); +- } +-} +- +-static void +-nvkm_output_dp_detect(struct nvkm_output_dp *outp) +-{ +- struct nouveau_i2c_port *port = outp->base.edid; +- int ret = nouveau_i2c(port)->acquire_pad(port, 0); +- if (ret == 0) { +- ret = nv_rdaux(outp->base.edid, DPCD_RC00_DPCD_REV, +- outp->dpcd, sizeof(outp->dpcd)); +- nvkm_output_dp_enable(outp, ret == 0); +- nouveau_i2c(port)->release_pad(port); +- } +-} +- +-static int +-nvkm_output_dp_hpd(struct nvkm_notify *notify) +-{ +- struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd); +- struct nvkm_output_dp *outp; +- struct nouveau_disp *disp = nouveau_disp(conn); +- const struct nvkm_i2c_ntfy_rep *line = notify->data; +- struct nvif_notify_conn_rep_v0 rep = {}; +- +- list_for_each_entry(outp, &disp->outp, base.head) { +- if (outp->base.conn == conn && +- outp->info.type == DCB_OUTPUT_DP) { +- DBG("HPD: %d\n", line->mask); +- nvkm_output_dp_detect(outp); +- +- if (line->mask & NVKM_I2C_UNPLUG) +- rep.mask |= NVIF_NOTIFY_CONN_V0_UNPLUG; +- if (line->mask & NVKM_I2C_PLUG) +- rep.mask |= NVIF_NOTIFY_CONN_V0_PLUG; +- +- nvkm_event_send(&disp->hpd, rep.mask, conn->index, +- &rep, sizeof(rep)); +- return NVKM_NOTIFY_KEEP; +- } +- } +- +- WARN_ON(1); +- return NVKM_NOTIFY_DROP; +-} +- +-static int +-nvkm_output_dp_irq(struct nvkm_notify *notify) +-{ +- struct nvkm_output_dp *outp = container_of(notify, typeof(*outp), irq); +- struct nouveau_disp *disp = nouveau_disp(outp); +- const struct nvkm_i2c_ntfy_rep *line = notify->data; +- struct nvif_notify_conn_rep_v0 rep = { +- .mask = NVIF_NOTIFY_CONN_V0_IRQ, +- }; +- int index = outp->base.info.connector; +- +- DBG("IRQ: %d\n", line->mask); +- nvkm_output_dp_train(&outp->base, 0, true); +- +- nvkm_event_send(&disp->hpd, rep.mask, index, &rep, sizeof(rep)); +- return NVKM_NOTIFY_DROP; +-} +- +-int +-_nvkm_output_dp_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvkm_output_dp *outp = (void *)object; +- nvkm_notify_put(&outp->irq); +- nvkm_output_dp_enable(outp, false); +- return nvkm_output_fini(&outp->base, suspend); +-} +- +-int +-_nvkm_output_dp_init(struct nouveau_object *object) +-{ +- struct nvkm_output_dp *outp = (void *)object; +- nvkm_output_dp_detect(outp); +- return nvkm_output_init(&outp->base); +-} +- +-void +-_nvkm_output_dp_dtor(struct nouveau_object *object) +-{ +- struct nvkm_output_dp *outp = (void *)object; +- nvkm_notify_fini(&outp->irq); +- nvkm_output_destroy(&outp->base); +-} +- +-int +-nvkm_output_dp_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- struct dcb_output *info, int index, +- int length, void **pobject) +-{ +- struct nouveau_bios *bios = nouveau_bios(parent); +- struct nouveau_i2c *i2c = nouveau_i2c(parent); +- struct nvkm_output_dp *outp; +- u8 hdr, cnt, len; +- u32 data; +- int ret; +- +- ret = nvkm_output_create_(parent, engine, oclass, info, index, +- length, pobject); +- outp = *pobject; +- if (ret) +- return ret; +- +- nvkm_notify_fini(&outp->base.conn->hpd); +- +- /* access to the aux channel is not optional... */ +- if (!outp->base.edid) { +- ERR("aux channel not found\n"); +- return -ENODEV; +- } +- +- /* nor is the bios data for this output... */ +- data = nvbios_dpout_match(bios, outp->base.info.hasht, +- outp->base.info.hashm, &outp->version, +- &hdr, &cnt, &len, &outp->info); +- if (!data) { +- ERR("no bios dp data\n"); +- return -ENODEV; +- } +- +- DBG("bios dp %02x %02x %02x %02x\n", outp->version, hdr, cnt, len); +- +- /* link training */ +- INIT_WORK(&outp->lt.work, nouveau_dp_train); +- init_waitqueue_head(&outp->lt.wait); +- atomic_set(&outp->lt.done, 0); +- +- /* link maintenance */ +- ret = nvkm_notify_init(NULL, &i2c->event, nvkm_output_dp_irq, true, +- &(struct nvkm_i2c_ntfy_req) { +- .mask = NVKM_I2C_IRQ, +- .port = outp->base.edid->index, +- }, +- sizeof(struct nvkm_i2c_ntfy_req), +- sizeof(struct nvkm_i2c_ntfy_rep), +- &outp->irq); +- if (ret) { +- ERR("error monitoring aux irq event: %d\n", ret); +- return ret; +- } +- +- /* hotplug detect, replaces gpio-based mechanism with aux events */ +- ret = nvkm_notify_init(NULL, &i2c->event, nvkm_output_dp_hpd, true, +- &(struct nvkm_i2c_ntfy_req) { +- .mask = NVKM_I2C_PLUG | NVKM_I2C_UNPLUG, +- .port = outp->base.edid->index, +- }, +- sizeof(struct nvkm_i2c_ntfy_req), +- sizeof(struct nvkm_i2c_ntfy_rep), +- &outp->base.conn->hpd); +- if (ret) { +- ERR("error monitoring aux hpd events: %d\n", ret); +- return ret; +- } +- +- return 0; +-} +- +-int +-_nvkm_output_dp_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *info, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nvkm_output_dp *outp; +- int ret; +- +- ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); +- *pobject = nv_object(outp); +- if (ret) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h b/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h +deleted file mode 100644 +index 1fac367c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/outpdp.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-#ifndef __NVKM_DISP_OUTP_DP_H__ +-#define __NVKM_DISP_OUTP_DP_H__ +- +-#include +-#include +- +-#include "outp.h" +- +-struct nvkm_output_dp { +- struct nvkm_output base; +- +- struct nvbios_dpout info; +- u8 version; +- +- struct nvkm_notify irq; +- bool present; +- u8 dpcd[16]; +- +- struct { +- struct work_struct work; +- wait_queue_head_t wait; +- atomic_t done; +- } lt; +-}; +- +-#define nvkm_output_dp_create(p,e,c,b,i,d) \ +- nvkm_output_dp_create_((p), (e), (c), (b), (i), sizeof(**d), (void **)d) +-#define nvkm_output_dp_destroy(d) ({ \ +- struct nvkm_output_dp *_outp = (d); \ +- _nvkm_output_dp_dtor(nv_object(_outp)); \ +-}) +-#define nvkm_output_dp_init(d) ({ \ +- struct nvkm_output_dp *_outp = (d); \ +- _nvkm_output_dp_init(nv_object(_outp)); \ +-}) +-#define nvkm_output_dp_fini(d,s) ({ \ +- struct nvkm_output_dp *_outp = (d); \ +- _nvkm_output_dp_fini(nv_object(_outp), (s)); \ +-}) +- +-int nvkm_output_dp_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, struct dcb_output *, +- int, int, void **); +- +-int _nvkm_output_dp_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void _nvkm_output_dp_dtor(struct nouveau_object *); +-int _nvkm_output_dp_init(struct nouveau_object *); +-int _nvkm_output_dp_fini(struct nouveau_object *, bool); +- +-struct nvkm_output_dp_impl { +- struct nvkm_output_impl base; +- int (*pattern)(struct nvkm_output_dp *, int); +- int (*lnk_pwr)(struct nvkm_output_dp *, int nr); +- int (*lnk_ctl)(struct nvkm_output_dp *, int nr, int bw, bool ef); +- int (*drv_ctl)(struct nvkm_output_dp *, int ln, int vs, int pe, int pc); +-}; +- +-int nvkm_output_dp_train(struct nvkm_output *, u32 rate, bool wait); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c +deleted file mode 100644 +index d00f89a4..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/piornv50.c ++++ /dev/null +@@ -1,172 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-#include "nv50.h" +- +-/****************************************************************************** +- * TMDS +- *****************************************************************************/ +- +-static int +-nv50_pior_tmds_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *info, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nouveau_i2c *i2c = nouveau_i2c(parent); +- struct nvkm_output *outp; +- int ret; +- +- ret = nvkm_output_create(parent, engine, oclass, info, index, &outp); +- *pobject = nv_object(outp); +- if (ret) +- return ret; +- +- outp->edid = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(outp->info.extdev)); +- return 0; +-} +- +-struct nvkm_output_impl +-nv50_pior_tmds_impl = { +- .base.handle = DCB_OUTPUT_TMDS | 0x0100, +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_pior_tmds_ctor, +- .dtor = _nvkm_output_dtor, +- .init = _nvkm_output_init, +- .fini = _nvkm_output_fini, +- }, +-}; +- +-/****************************************************************************** +- * DisplayPort +- *****************************************************************************/ +- +-static int +-nv50_pior_dp_pattern(struct nvkm_output_dp *outp, int pattern) +-{ +- struct nouveau_i2c_port *port = outp->base.edid; +- if (port && port->func->pattern) +- return port->func->pattern(port, pattern); +- return port ? 0 : -ENODEV; +-} +- +-static int +-nv50_pior_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) +-{ +- return 0; +-} +- +-static int +-nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) +-{ +- struct nouveau_i2c_port *port = outp->base.edid; +- if (port && port->func->lnk_ctl) +- return port->func->lnk_ctl(port, nr, bw, ef); +- return port ? 0 : -ENODEV; +-} +- +-static int +-nv50_pior_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) +-{ +- struct nouveau_i2c_port *port = outp->base.edid; +- if (port && port->func->drv_ctl) +- return port->func->drv_ctl(port, ln, vs, pe); +- return port ? 0 : -ENODEV; +-} +- +-static int +-nv50_pior_dp_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *info, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nouveau_i2c *i2c = nouveau_i2c(parent); +- struct nvkm_output_dp *outp; +- int ret; +- +- ret = nvkm_output_dp_create(parent, engine, oclass, info, index, &outp); +- *pobject = nv_object(outp); +- if (ret) +- return ret; +- +- outp->base.edid = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX( +- outp->base.info.extdev)); +- return 0; +-} +- +-struct nvkm_output_dp_impl +-nv50_pior_dp_impl = { +- .base.base.handle = DCB_OUTPUT_DP | 0x0010, +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_pior_dp_ctor, +- .dtor = _nvkm_output_dp_dtor, +- .init = _nvkm_output_dp_init, +- .fini = _nvkm_output_dp_fini, +- }, +- .pattern = nv50_pior_dp_pattern, +- .lnk_pwr = nv50_pior_dp_lnk_pwr, +- .lnk_ctl = nv50_pior_dp_lnk_ctl, +- .drv_ctl = nv50_pior_dp_drv_ctl, +-}; +- +-/****************************************************************************** +- * General PIOR handling +- *****************************************************************************/ +- +-int +-nv50_pior_power(NV50_DISP_MTHD_V1) +-{ +- const u32 soff = outp->or * 0x800; +- union { +- struct nv50_disp_pior_pwr_v0 v0; +- } *args = data; +- u32 ctrl, type; +- int ret; +- +- nv_ioctl(object, "disp pior pwr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp pior pwr vers %d state %d type %x\n", +- args->v0.version, args->v0.state, args->v0.type); +- if (args->v0.type > 0x0f) +- return -EINVAL; +- ctrl = !!args->v0.state; +- type = args->v0.type; +- } else +- return ret; +- +- nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000); +- nv_mask(priv, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); +- nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000); +- priv->pior.type[outp->or] = type; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h b/drivers/gpu/drm/nouveau/core/engine/disp/priv.h +deleted file mode 100644 +index 6a0511d5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/priv.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-#ifndef __NVKM_DISP_PRIV_H__ +-#define __NVKM_DISP_PRIV_H__ +- +-#include +-#include +-#include +- +-#include +- +-struct nouveau_disp_impl { +- struct nouveau_oclass base; +- struct nouveau_oclass **outp; +- struct nouveau_oclass **conn; +- const struct nvkm_event_func *vblank; +-}; +- +-#define nouveau_disp_create(p,e,c,h,i,x,d) \ +- nouveau_disp_create_((p), (e), (c), (h), (i), (x), \ +- sizeof(**d), (void **)d) +-#define nouveau_disp_destroy(d) ({ \ +- struct nouveau_disp *disp = (d); \ +- _nouveau_disp_dtor(nv_object(disp)); \ +-}) +-#define nouveau_disp_init(d) ({ \ +- struct nouveau_disp *disp = (d); \ +- _nouveau_disp_init(nv_object(disp)); \ +-}) +-#define nouveau_disp_fini(d,s) ({ \ +- struct nouveau_disp *disp = (d); \ +- _nouveau_disp_fini(nv_object(disp), (s)); \ +-}) +- +-int nouveau_disp_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int heads, +- const char *, const char *, int, void **); +-void _nouveau_disp_dtor(struct nouveau_object *); +-int _nouveau_disp_init(struct nouveau_object *); +-int _nouveau_disp_fini(struct nouveau_object *, bool); +- +-extern struct nouveau_oclass *nvkm_output_oclass; +-extern struct nouveau_oclass *nvkm_connector_oclass; +- +-int nouveau_disp_vblank_ctor(struct nouveau_object *, void *data, u32 size, +- struct nvkm_notify *); +-void nouveau_disp_vblank(struct nouveau_disp *, int head); +-int nouveau_disp_ntfy(struct nouveau_object *, u32, struct nvkm_event **); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c +deleted file mode 100644 +index ddf1760c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nv50_sor_power(NV50_DISP_MTHD_V1) +-{ +- union { +- struct nv50_disp_sor_pwr_v0 v0; +- } *args = data; +- const u32 soff = outp->or * 0x800; +- u32 stat; +- int ret; +- +- nv_ioctl(object, "disp sor pwr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "disp sor pwr vers %d state %d\n", +- args->v0.version, args->v0.state); +- stat = !!args->v0.state; +- } else +- return ret; +- +- nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000); +- nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); +- nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000); +- nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c +deleted file mode 100644 +index 39f85d62..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +-#include +-#include +- +-#include "nv50.h" +-#include "outpdp.h" +- +-static inline u32 +-nv94_sor_soff(struct nvkm_output_dp *outp) +-{ +- return (ffs(outp->base.info.or) - 1) * 0x800; +-} +- +-static inline u32 +-nv94_sor_loff(struct nvkm_output_dp *outp) +-{ +- return nv94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; +-} +- +-static inline u32 +-nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) +-{ +- static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ +- static const u8 nv94[] = { 16, 8, 0, 24 }; +- if (nv_device(priv)->chipset == 0xaf) +- return nvaf[lane]; +- return nv94[lane]; +-} +- +-static int +-nv94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- const u32 loff = nv94_sor_loff(outp); +- nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24); +- return 0; +-} +- +-int +-nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- const u32 soff = nv94_sor_soff(outp); +- const u32 loff = nv94_sor_loff(outp); +- u32 mask = 0, i; +- +- for (i = 0; i < nr; i++) +- mask |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3); +- +- nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); +- nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); +- nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000); +- return 0; +-} +- +-static int +-nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- const u32 soff = nv94_sor_soff(outp); +- const u32 loff = nv94_sor_loff(outp); +- u32 dpctrl = 0x00000000; +- u32 clksor = 0x00000000; +- +- dpctrl |= ((1 << nr) - 1) << 16; +- if (ef) +- dpctrl |= 0x00004000; +- if (bw > 0x06) +- clksor |= 0x00040000; +- +- nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor); +- nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); +- return 0; +-} +- +-static int +-nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- struct nouveau_bios *bios = nouveau_bios(priv); +- const u32 shift = nv94_sor_dp_lane_map(priv, ln); +- const u32 loff = nv94_sor_loff(outp); +- u32 addr, data[3]; +- u8 ver, hdr, cnt, len; +- struct nvbios_dpout info; +- struct nvbios_dpcfg ocfg; +- +- addr = nvbios_dpout_match(bios, outp->base.info.hasht, +- outp->base.info.hashm, +- &ver, &hdr, &cnt, &len, &info); +- if (!addr) +- return -ENODEV; +- +- addr = nvbios_dpcfg_match(bios, addr, 0, vs, pe, +- &ver, &hdr, &cnt, &len, &ocfg); +- if (!addr) +- return -EINVAL; +- +- data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); +- data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); +- data[2] = nv_rd32(priv, 0x61c130 + loff); +- if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) +- data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); +- nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); +- nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); +- nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); +- return 0; +-} +- +-struct nvkm_output_dp_impl +-nv94_sor_dp_impl = { +- .base.base.handle = DCB_OUTPUT_DP, +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_output_dp_ctor, +- .dtor = _nvkm_output_dp_dtor, +- .init = _nvkm_output_dp_init, +- .fini = _nvkm_output_dp_fini, +- }, +- .pattern = nv94_sor_dp_pattern, +- .lnk_pwr = nv94_sor_dp_lnk_pwr, +- .lnk_ctl = nv94_sor_dp_lnk_ctl, +- .drv_ctl = nv94_sor_dp_drv_ctl, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c +deleted file mode 100644 +index 7b7bbc3e..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c ++++ /dev/null +@@ -1,131 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +-#include +-#include +- +-#include "nv50.h" +- +-static inline u32 +-nvd0_sor_soff(struct nvkm_output_dp *outp) +-{ +- return (ffs(outp->base.info.or) - 1) * 0x800; +-} +- +-static inline u32 +-nvd0_sor_loff(struct nvkm_output_dp *outp) +-{ +- return nvd0_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80; +-} +- +-static inline u32 +-nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) +-{ +- static const u8 nvd0[] = { 16, 8, 0, 24 }; +- return nvd0[lane]; +-} +- +-static int +-nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- const u32 loff = nvd0_sor_loff(outp); +- nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); +- return 0; +-} +- +-static int +-nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- const u32 soff = nvd0_sor_soff(outp); +- const u32 loff = nvd0_sor_loff(outp); +- u32 dpctrl = 0x00000000; +- u32 clksor = 0x00000000; +- +- clksor |= bw << 18; +- dpctrl |= ((1 << nr) - 1) << 16; +- if (ef) +- dpctrl |= 0x00004000; +- +- nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor); +- nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); +- return 0; +-} +- +-static int +-nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) +-{ +- struct nv50_disp_priv *priv = (void *)nouveau_disp(outp); +- struct nouveau_bios *bios = nouveau_bios(priv); +- const u32 shift = nvd0_sor_dp_lane_map(priv, ln); +- const u32 loff = nvd0_sor_loff(outp); +- u32 addr, data[4]; +- u8 ver, hdr, cnt, len; +- struct nvbios_dpout info; +- struct nvbios_dpcfg ocfg; +- +- addr = nvbios_dpout_match(bios, outp->base.info.hasht, +- outp->base.info.hashm, +- &ver, &hdr, &cnt, &len, &info); +- if (!addr) +- return -ENODEV; +- +- addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe, +- &ver, &hdr, &cnt, &len, &ocfg); +- if (!addr) +- return -EINVAL; +- +- data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); +- data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); +- data[2] = nv_rd32(priv, 0x61c130 + loff); +- if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) +- data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); +- nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); +- nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); +- nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.tx_pu << 8)); +- data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); +- nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); +- return 0; +-} +- +-struct nvkm_output_dp_impl +-nvd0_sor_dp_impl = { +- .base.base.handle = DCB_OUTPUT_DP, +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_output_dp_ctor, +- .dtor = _nvkm_output_dp_dtor, +- .init = _nvkm_output_dp_init, +- .fini = _nvkm_output_dp_fini, +- }, +- .pattern = nvd0_sor_dp_pattern, +- .lnk_pwr = nv94_sor_dp_lnk_pwr, +- .lnk_ctl = nvd0_sor_dp_lnk_ctl, +- .drv_ctl = nvd0_sor_dp_drv_ctl, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c b/drivers/gpu/drm/nouveau/core/engine/disp/vga.c +deleted file mode 100644 +index 8836c3cb..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/disp/vga.c ++++ /dev/null +@@ -1,220 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u8 +-nv_rdport(void *obj, int head, u16 port) +-{ +- struct nouveau_device *device = nv_device(obj); +- +- if (device->card_type >= NV_50) +- return nv_rd08(obj, 0x601000 + port); +- +- if (port == 0x03c0 || port == 0x03c1 || /* AR */ +- port == 0x03c2 || port == 0x03da || /* INP0 */ +- port == 0x03d4 || port == 0x03d5) /* CR */ +- return nv_rd08(obj, 0x601000 + (head * 0x2000) + port); +- +- if (port == 0x03c2 || port == 0x03cc || /* MISC */ +- port == 0x03c4 || port == 0x03c5 || /* SR */ +- port == 0x03ce || port == 0x03cf) { /* GR */ +- if (device->card_type < NV_40) +- head = 0; /* CR44 selects head */ +- return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port); +- } +- +- nv_error(obj, "unknown vga port 0x%04x\n", port); +- return 0x00; +-} +- +-void +-nv_wrport(void *obj, int head, u16 port, u8 data) +-{ +- struct nouveau_device *device = nv_device(obj); +- +- if (device->card_type >= NV_50) +- nv_wr08(obj, 0x601000 + port, data); +- else +- if (port == 0x03c0 || port == 0x03c1 || /* AR */ +- port == 0x03c2 || port == 0x03da || /* INP0 */ +- port == 0x03d4 || port == 0x03d5) /* CR */ +- nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data); +- else +- if (port == 0x03c2 || port == 0x03cc || /* MISC */ +- port == 0x03c4 || port == 0x03c5 || /* SR */ +- port == 0x03ce || port == 0x03cf) { /* GR */ +- if (device->card_type < NV_40) +- head = 0; /* CR44 selects head */ +- nv_wr08(obj, 0x0c0000 + (head * 0x2000) + port, data); +- } else +- nv_error(obj, "unknown vga port 0x%04x\n", port); +-} +- +-u8 +-nv_rdvgas(void *obj, int head, u8 index) +-{ +- nv_wrport(obj, head, 0x03c4, index); +- return nv_rdport(obj, head, 0x03c5); +-} +- +-void +-nv_wrvgas(void *obj, int head, u8 index, u8 value) +-{ +- nv_wrport(obj, head, 0x03c4, index); +- nv_wrport(obj, head, 0x03c5, value); +-} +- +-u8 +-nv_rdvgag(void *obj, int head, u8 index) +-{ +- nv_wrport(obj, head, 0x03ce, index); +- return nv_rdport(obj, head, 0x03cf); +-} +- +-void +-nv_wrvgag(void *obj, int head, u8 index, u8 value) +-{ +- nv_wrport(obj, head, 0x03ce, index); +- nv_wrport(obj, head, 0x03cf, value); +-} +- +-u8 +-nv_rdvgac(void *obj, int head, u8 index) +-{ +- nv_wrport(obj, head, 0x03d4, index); +- return nv_rdport(obj, head, 0x03d5); +-} +- +-void +-nv_wrvgac(void *obj, int head, u8 index, u8 value) +-{ +- nv_wrport(obj, head, 0x03d4, index); +- nv_wrport(obj, head, 0x03d5, value); +-} +- +-u8 +-nv_rdvgai(void *obj, int head, u16 port, u8 index) +-{ +- if (port == 0x03c4) return nv_rdvgas(obj, head, index); +- if (port == 0x03ce) return nv_rdvgag(obj, head, index); +- if (port == 0x03d4) return nv_rdvgac(obj, head, index); +- nv_error(obj, "unknown indexed vga port 0x%04x\n", port); +- return 0x00; +-} +- +-void +-nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value) +-{ +- if (port == 0x03c4) nv_wrvgas(obj, head, index, value); +- else if (port == 0x03ce) nv_wrvgag(obj, head, index, value); +- else if (port == 0x03d4) nv_wrvgac(obj, head, index, value); +- else nv_error(obj, "unknown indexed vga port 0x%04x\n", port); +-} +- +-bool +-nv_lockvgac(void *obj, bool lock) +-{ +- struct nouveau_device *dev = nv_device(obj); +- +- bool locked = !nv_rdvgac(obj, 0, 0x1f); +- u8 data = lock ? 0x99 : 0x57; +- if (dev->card_type < NV_50) +- nv_wrvgac(obj, 0, 0x1f, data); +- else +- nv_wrvgac(obj, 0, 0x3f, data); +- if (dev->chipset == 0x11) { +- if (!(nv_rd32(obj, 0x001084) & 0x10000000)) +- nv_wrvgac(obj, 1, 0x1f, data); +- } +- return locked; +-} +- +-/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) +- * it affects only the 8 bit vga io regs, which we access using mmio at +- * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* +- * in general, the set value of cr44 does not matter: reg access works as +- * expected and values can be set for the appropriate head by using a 0x2000 +- * offset as required +- * however: +- * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and +- * cr44 must be set to 0 or 3 for accessing values on the correct head +- * through the common 0xc03c* addresses +- * b) in tied mode (4) head B is programmed to the values set on head A, and +- * access using the head B addresses can have strange results, ergo we leave +- * tied mode in init once we know to what cr44 should be restored on exit +- * +- * the owner parameter is slightly abused: +- * 0 and 1 are treated as head values and so the set value is (owner * 3) +- * other values are treated as literal values to set +- */ +-u8 +-nv_rdvgaowner(void *obj) +-{ +- if (nv_device(obj)->card_type < NV_50) { +- if (nv_device(obj)->chipset == 0x11) { +- u32 tied = nv_rd32(obj, 0x001084) & 0x10000000; +- if (tied == 0) { +- u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80; +- u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01; +- u8 slB = nv_rdvgac(obj, 1, 0x28) & 0x80; +- u8 tvB = nv_rdvgac(obj, 1, 0x33) & 0x01; +- if (slA && !tvA) return 0x00; +- if (slB && !tvB) return 0x03; +- if (slA) return 0x00; +- if (slB) return 0x03; +- return 0x00; +- } +- return 0x04; +- } +- +- return nv_rdvgac(obj, 0, 0x44); +- } +- +- nv_error(obj, "rdvgaowner after nv4x\n"); +- return 0x00; +-} +- +-void +-nv_wrvgaowner(void *obj, u8 select) +-{ +- if (nv_device(obj)->card_type < NV_50) { +- u8 owner = (select == 1) ? 3 : select; +- if (nv_device(obj)->chipset == 0x11) { +- /* workaround hw lockup bug */ +- nv_rdvgac(obj, 0, 0x1f); +- nv_rdvgac(obj, 1, 0x1f); +- } +- +- nv_wrvgac(obj, 0, 0x44, owner); +- +- if (nv_device(obj)->chipset == 0x11) { +- nv_wrvgac(obj, 0, 0x2e, owner); +- nv_wrvgac(obj, 0, 0x2e, owner); +- } +- } else +- nv_error(obj, "wrvgaowner after nv4x\n"); +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c +deleted file mode 100644 +index e1500f77..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/base.c ++++ /dev/null +@@ -1,165 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include "priv.h" +- +-static int +-nvkm_dmaobj_bind(struct nouveau_dmaobj *dmaobj, struct nouveau_object *parent, +- struct nouveau_gpuobj **pgpuobj) +-{ +- const struct nvkm_dmaeng_impl *impl = (void *) +- nv_oclass(nv_object(dmaobj)->engine); +- int ret = 0; +- +- if (nv_object(dmaobj) == parent) { /* ctor bind */ +- if (nv_mclass(parent->parent) == NV_DEVICE) { +- /* delayed, or no, binding */ +- return 0; +- } +- ret = impl->bind(dmaobj, parent, pgpuobj); +- if (ret == 0) +- nouveau_object_ref(NULL, &parent); +- return ret; +- } +- +- return impl->bind(dmaobj, parent, pgpuobj); +-} +- +-int +-nvkm_dmaobj_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void **pdata, u32 *psize, +- int length, void **pobject) +-{ +- union { +- struct nv_dma_v0 v0; +- } *args = *pdata; +- struct nouveau_instmem *instmem = nouveau_instmem(parent); +- struct nouveau_client *client = nouveau_client(parent); +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_dmaobj *dmaobj; +- void *data = *pdata; +- u32 size = *psize; +- int ret; +- +- ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject); +- dmaobj = *pobject; +- if (ret) +- return ret; +- +- nv_ioctl(parent, "create dma size %d\n", *psize); +- if (nvif_unpack(args->v0, 0, 0, true)) { +- nv_ioctl(parent, "create dma vers %d target %d access %d " +- "start %016llx limit %016llx\n", +- args->v0.version, args->v0.target, args->v0.access, +- args->v0.start, args->v0.limit); +- dmaobj->target = args->v0.target; +- dmaobj->access = args->v0.access; +- dmaobj->start = args->v0.start; +- dmaobj->limit = args->v0.limit; +- } else +- return ret; +- +- *pdata = data; +- *psize = size; +- +- if (dmaobj->start > dmaobj->limit) +- return -EINVAL; +- +- switch (dmaobj->target) { +- case NV_DMA_V0_TARGET_VM: +- dmaobj->target = NV_MEM_TARGET_VM; +- break; +- case NV_DMA_V0_TARGET_VRAM: +- if (!client->super) { +- if (dmaobj->limit >= pfb->ram->size - instmem->reserved) +- return -EACCES; +- if (device->card_type >= NV_50) +- return -EACCES; +- } +- dmaobj->target = NV_MEM_TARGET_VRAM; +- break; +- case NV_DMA_V0_TARGET_PCI: +- if (!client->super) +- return -EACCES; +- dmaobj->target = NV_MEM_TARGET_PCI; +- break; +- case NV_DMA_V0_TARGET_PCI_US: +- case NV_DMA_V0_TARGET_AGP: +- if (!client->super) +- return -EACCES; +- dmaobj->target = NV_MEM_TARGET_PCI_NOSNOOP; +- break; +- default: +- return -EINVAL; +- } +- +- switch (dmaobj->access) { +- case NV_DMA_V0_ACCESS_VM: +- dmaobj->access = NV_MEM_ACCESS_VM; +- break; +- case NV_DMA_V0_ACCESS_RD: +- dmaobj->access = NV_MEM_ACCESS_RO; +- break; +- case NV_DMA_V0_ACCESS_WR: +- dmaobj->access = NV_MEM_ACCESS_WO; +- break; +- case NV_DMA_V0_ACCESS_RDWR: +- dmaobj->access = NV_MEM_ACCESS_RW; +- break; +- default: +- return -EINVAL; +- } +- +- return ret; +-} +- +-int +-_nvkm_dmaeng_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- const struct nvkm_dmaeng_impl *impl = (void *)oclass; +- struct nouveau_dmaeng *dmaeng; +- int ret; +- +- ret = nouveau_engine_create(parent, engine, oclass, true, "DMAOBJ", +- "dmaobj", &dmaeng); +- *pobject = nv_object(dmaeng); +- if (ret) +- return ret; +- +- nv_engine(dmaeng)->sclass = impl->sclass; +- dmaeng->bind = nvkm_dmaobj_bind; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c +deleted file mode 100644 +index 20c9dbfe..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv04.c ++++ /dev/null +@@ -1,165 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +- +-#include "priv.h" +- +-struct nv04_dmaobj_priv { +- struct nouveau_dmaobj base; +- bool clone; +- u32 flags0; +- u32 flags2; +-}; +- +-static int +-nv04_dmaobj_bind(struct nouveau_dmaobj *dmaobj, +- struct nouveau_object *parent, +- struct nouveau_gpuobj **pgpuobj) +-{ +- struct nv04_dmaobj_priv *priv = (void *)dmaobj; +- struct nouveau_gpuobj *gpuobj; +- u64 offset = priv->base.start & 0xfffff000; +- u64 adjust = priv->base.start & 0x00000fff; +- u32 length = priv->base.limit - priv->base.start; +- int ret; +- +- if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { +- switch (nv_mclass(parent->parent)) { +- case NV03_CHANNEL_DMA: +- case NV10_CHANNEL_DMA: +- case NV17_CHANNEL_DMA: +- case NV40_CHANNEL_DMA: +- break; +- default: +- return -EINVAL; +- } +- } +- +- if (priv->clone) { +- struct nv04_vmmgr_priv *vmm = nv04_vmmgr(dmaobj); +- struct nouveau_gpuobj *pgt = vmm->vm->pgt[0].obj[0]; +- if (!dmaobj->start) +- return nouveau_gpuobj_dup(parent, pgt, pgpuobj); +- offset = nv_ro32(pgt, 8 + (offset >> 10)); +- offset &= 0xfffff000; +- } +- +- ret = nouveau_gpuobj_new(parent, parent, 16, 16, 0, &gpuobj); +- *pgpuobj = gpuobj; +- if (ret == 0) { +- nv_wo32(*pgpuobj, 0x00, priv->flags0 | (adjust << 20)); +- nv_wo32(*pgpuobj, 0x04, length); +- nv_wo32(*pgpuobj, 0x08, priv->flags2 | offset); +- nv_wo32(*pgpuobj, 0x0c, priv->flags2 | offset); +- } +- +- return ret; +-} +- +-static int +-nv04_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_dmaeng *dmaeng = (void *)engine; +- struct nv04_vmmgr_priv *vmm = nv04_vmmgr(engine); +- struct nv04_dmaobj_priv *priv; +- int ret; +- +- ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); +- *pobject = nv_object(priv); +- if (ret || (ret = -ENOSYS, size)) +- return ret; +- +- if (priv->base.target == NV_MEM_TARGET_VM) { +- if (nv_object(vmm)->oclass == &nv04_vmmgr_oclass) +- priv->clone = true; +- priv->base.target = NV_MEM_TARGET_PCI; +- priv->base.access = NV_MEM_ACCESS_RW; +- } +- +- priv->flags0 = nv_mclass(priv); +- switch (priv->base.target) { +- case NV_MEM_TARGET_VRAM: +- priv->flags0 |= 0x00003000; +- break; +- case NV_MEM_TARGET_PCI: +- priv->flags0 |= 0x00023000; +- break; +- case NV_MEM_TARGET_PCI_NOSNOOP: +- priv->flags0 |= 0x00033000; +- break; +- default: +- return -EINVAL; +- } +- +- switch (priv->base.access) { +- case NV_MEM_ACCESS_RO: +- priv->flags0 |= 0x00004000; +- break; +- case NV_MEM_ACCESS_WO: +- priv->flags0 |= 0x00008000; +- case NV_MEM_ACCESS_RW: +- priv->flags2 |= 0x00000002; +- break; +- default: +- return -EINVAL; +- } +- +- return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); +-} +- +-static struct nouveau_ofuncs +-nv04_dmaobj_ofuncs = { +- .ctor = nv04_dmaobj_ctor, +- .dtor = _nvkm_dmaobj_dtor, +- .init = _nvkm_dmaobj_init, +- .fini = _nvkm_dmaobj_fini, +-}; +- +-static struct nouveau_oclass +-nv04_dmaeng_sclass[] = { +- { NV_DMA_FROM_MEMORY, &nv04_dmaobj_ofuncs }, +- { NV_DMA_TO_MEMORY, &nv04_dmaobj_ofuncs }, +- { NV_DMA_IN_MEMORY, &nv04_dmaobj_ofuncs }, +- {} +-}; +- +-struct nouveau_oclass * +-nv04_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { +- .base.handle = NV_ENGINE(DMAOBJ, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_dmaeng_ctor, +- .dtor = _nvkm_dmaeng_dtor, +- .init = _nvkm_dmaeng_init, +- .fini = _nvkm_dmaeng_fini, +- }, +- .sclass = nv04_dmaeng_sclass, +- .bind = nv04_dmaobj_bind, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c +deleted file mode 100644 +index a740ddba..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nv50.c ++++ /dev/null +@@ -1,197 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +- +-#include "priv.h" +- +-struct nv50_dmaobj_priv { +- struct nouveau_dmaobj base; +- u32 flags0; +- u32 flags5; +-}; +- +-static int +-nv50_dmaobj_bind(struct nouveau_dmaobj *dmaobj, +- struct nouveau_object *parent, +- struct nouveau_gpuobj **pgpuobj) +-{ +- struct nv50_dmaobj_priv *priv = (void *)dmaobj; +- int ret; +- +- if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { +- switch (nv_mclass(parent->parent)) { +- case NV40_CHANNEL_DMA: +- case NV50_CHANNEL_GPFIFO: +- case G82_CHANNEL_GPFIFO: +- case NV50_DISP_CORE_CHANNEL_DMA: +- case G82_DISP_CORE_CHANNEL_DMA: +- case GT206_DISP_CORE_CHANNEL_DMA: +- case GT200_DISP_CORE_CHANNEL_DMA: +- case GT214_DISP_CORE_CHANNEL_DMA: +- case NV50_DISP_BASE_CHANNEL_DMA: +- case G82_DISP_BASE_CHANNEL_DMA: +- case GT200_DISP_BASE_CHANNEL_DMA: +- case GT214_DISP_BASE_CHANNEL_DMA: +- case NV50_DISP_OVERLAY_CHANNEL_DMA: +- case G82_DISP_OVERLAY_CHANNEL_DMA: +- case GT200_DISP_OVERLAY_CHANNEL_DMA: +- case GT214_DISP_OVERLAY_CHANNEL_DMA: +- break; +- default: +- return -EINVAL; +- } +- } +- +- ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); +- if (ret == 0) { +- nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj)); +- nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit)); +- nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start)); +- nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 | +- upper_32_bits(priv->base.start)); +- nv_wo32(*pgpuobj, 0x10, 0x00000000); +- nv_wo32(*pgpuobj, 0x14, priv->flags5); +- } +- +- return ret; +-} +- +-static int +-nv50_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_dmaeng *dmaeng = (void *)engine; +- union { +- struct nv50_dma_v0 v0; +- } *args; +- struct nv50_dmaobj_priv *priv; +- u32 user, part, comp, kind; +- int ret; +- +- ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- args = data; +- +- nv_ioctl(parent, "create nv50 dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create nv50 dma vers %d priv %d part %d " +- "comp %d kind %02x\n", args->v0.version, +- args->v0.priv, args->v0.part, args->v0.comp, +- args->v0.kind); +- user = args->v0.priv; +- part = args->v0.part; +- comp = args->v0.comp; +- kind = args->v0.kind; +- } else +- if (size == 0) { +- if (priv->base.target != NV_MEM_TARGET_VM) { +- user = NV50_DMA_V0_PRIV_US; +- part = NV50_DMA_V0_PART_256; +- comp = NV50_DMA_V0_COMP_NONE; +- kind = NV50_DMA_V0_KIND_PITCH; +- } else { +- user = NV50_DMA_V0_PRIV_VM; +- part = NV50_DMA_V0_PART_VM; +- comp = NV50_DMA_V0_COMP_VM; +- kind = NV50_DMA_V0_KIND_VM; +- } +- } else +- return ret; +- +- if (user > 2 || part > 2 || comp > 3 || kind > 0x7f) +- return -EINVAL; +- priv->flags0 = (comp << 29) | (kind << 22) | (user << 20); +- priv->flags5 = (part << 16); +- +- switch (priv->base.target) { +- case NV_MEM_TARGET_VM: +- priv->flags0 |= 0x00000000; +- break; +- case NV_MEM_TARGET_VRAM: +- priv->flags0 |= 0x00010000; +- break; +- case NV_MEM_TARGET_PCI: +- priv->flags0 |= 0x00020000; +- break; +- case NV_MEM_TARGET_PCI_NOSNOOP: +- priv->flags0 |= 0x00030000; +- break; +- default: +- return -EINVAL; +- } +- +- switch (priv->base.access) { +- case NV_MEM_ACCESS_VM: +- break; +- case NV_MEM_ACCESS_RO: +- priv->flags0 |= 0x00040000; +- break; +- case NV_MEM_ACCESS_WO: +- case NV_MEM_ACCESS_RW: +- priv->flags0 |= 0x00080000; +- break; +- default: +- return -EINVAL; +- } +- +- return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); +-} +- +-static struct nouveau_ofuncs +-nv50_dmaobj_ofuncs = { +- .ctor = nv50_dmaobj_ctor, +- .dtor = _nvkm_dmaobj_dtor, +- .init = _nvkm_dmaobj_init, +- .fini = _nvkm_dmaobj_fini, +-}; +- +-static struct nouveau_oclass +-nv50_dmaeng_sclass[] = { +- { NV_DMA_FROM_MEMORY, &nv50_dmaobj_ofuncs }, +- { NV_DMA_TO_MEMORY, &nv50_dmaobj_ofuncs }, +- { NV_DMA_IN_MEMORY, &nv50_dmaobj_ofuncs }, +- {} +-}; +- +-struct nouveau_oclass * +-nv50_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { +- .base.handle = NV_ENGINE(DMAOBJ, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_dmaeng_ctor, +- .dtor = _nvkm_dmaeng_dtor, +- .init = _nvkm_dmaeng_init, +- .fini = _nvkm_dmaeng_fini, +- }, +- .sclass = nv50_dmaeng_sclass, +- .bind = nv50_dmaobj_bind, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c +deleted file mode 100644 +index 88ec33b2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c ++++ /dev/null +@@ -1,179 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include "priv.h" +- +-struct nvc0_dmaobj_priv { +- struct nouveau_dmaobj base; +- u32 flags0; +- u32 flags5; +-}; +- +-static int +-nvc0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, +- struct nouveau_object *parent, +- struct nouveau_gpuobj **pgpuobj) +-{ +- struct nvc0_dmaobj_priv *priv = (void *)dmaobj; +- int ret; +- +- if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { +- switch (nv_mclass(parent->parent)) { +- case GT214_DISP_CORE_CHANNEL_DMA: +- case GT214_DISP_BASE_CHANNEL_DMA: +- case GT214_DISP_OVERLAY_CHANNEL_DMA: +- break; +- default: +- return -EINVAL; +- } +- } else +- return 0; +- +- ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); +- if (ret == 0) { +- nv_wo32(*pgpuobj, 0x00, priv->flags0 | nv_mclass(dmaobj)); +- nv_wo32(*pgpuobj, 0x04, lower_32_bits(priv->base.limit)); +- nv_wo32(*pgpuobj, 0x08, lower_32_bits(priv->base.start)); +- nv_wo32(*pgpuobj, 0x0c, upper_32_bits(priv->base.limit) << 24 | +- upper_32_bits(priv->base.start)); +- nv_wo32(*pgpuobj, 0x10, 0x00000000); +- nv_wo32(*pgpuobj, 0x14, priv->flags5); +- } +- +- return ret; +-} +- +-static int +-nvc0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_dmaeng *dmaeng = (void *)engine; +- union { +- struct gf100_dma_v0 v0; +- } *args; +- struct nvc0_dmaobj_priv *priv; +- u32 kind, user, unkn; +- int ret; +- +- ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- args = data; +- +- nv_ioctl(parent, "create gf100 dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create gf100 dma vers %d priv %d kind %02x\n", +- args->v0.version, args->v0.priv, args->v0.kind); +- kind = args->v0.kind; +- user = args->v0.priv; +- unkn = 0; +- } else +- if (size == 0) { +- if (priv->base.target != NV_MEM_TARGET_VM) { +- kind = GF100_DMA_V0_KIND_PITCH; +- user = GF100_DMA_V0_PRIV_US; +- unkn = 2; +- } else { +- kind = GF100_DMA_V0_KIND_VM; +- user = GF100_DMA_V0_PRIV_VM; +- unkn = 0; +- } +- } else +- return ret; +- +- if (user > 2) +- return -EINVAL; +- priv->flags0 |= (kind << 22) | (user << 20); +- priv->flags5 |= (unkn << 16); +- +- switch (priv->base.target) { +- case NV_MEM_TARGET_VM: +- priv->flags0 |= 0x00000000; +- break; +- case NV_MEM_TARGET_VRAM: +- priv->flags0 |= 0x00010000; +- break; +- case NV_MEM_TARGET_PCI: +- priv->flags0 |= 0x00020000; +- break; +- case NV_MEM_TARGET_PCI_NOSNOOP: +- priv->flags0 |= 0x00030000; +- break; +- default: +- return -EINVAL; +- } +- +- switch (priv->base.access) { +- case NV_MEM_ACCESS_VM: +- break; +- case NV_MEM_ACCESS_RO: +- priv->flags0 |= 0x00040000; +- break; +- case NV_MEM_ACCESS_WO: +- case NV_MEM_ACCESS_RW: +- priv->flags0 |= 0x00080000; +- break; +- } +- +- return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); +-} +- +-static struct nouveau_ofuncs +-nvc0_dmaobj_ofuncs = { +- .ctor = nvc0_dmaobj_ctor, +- .dtor = _nvkm_dmaobj_dtor, +- .init = _nvkm_dmaobj_init, +- .fini = _nvkm_dmaobj_fini, +-}; +- +-static struct nouveau_oclass +-nvc0_dmaeng_sclass[] = { +- { NV_DMA_FROM_MEMORY, &nvc0_dmaobj_ofuncs }, +- { NV_DMA_TO_MEMORY, &nvc0_dmaobj_ofuncs }, +- { NV_DMA_IN_MEMORY, &nvc0_dmaobj_ofuncs }, +- {} +-}; +- +-struct nouveau_oclass * +-nvc0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { +- .base.handle = NV_ENGINE(DMAOBJ, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_dmaeng_ctor, +- .dtor = _nvkm_dmaeng_dtor, +- .init = _nvkm_dmaeng_init, +- .fini = _nvkm_dmaeng_fini, +- }, +- .sclass = nvc0_dmaeng_sclass, +- .bind = nvc0_dmaobj_bind, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c +deleted file mode 100644 +index 3fc4f0b0..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/nvd0.c ++++ /dev/null +@@ -1,167 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include "priv.h" +- +-struct nvd0_dmaobj_priv { +- struct nouveau_dmaobj base; +- u32 flags0; +-}; +- +-static int +-nvd0_dmaobj_bind(struct nouveau_dmaobj *dmaobj, +- struct nouveau_object *parent, +- struct nouveau_gpuobj **pgpuobj) +-{ +- struct nvd0_dmaobj_priv *priv = (void *)dmaobj; +- int ret; +- +- if (!nv_iclass(parent, NV_ENGCTX_CLASS)) { +- switch (nv_mclass(parent->parent)) { +- case GF110_DISP_CORE_CHANNEL_DMA: +- case GK104_DISP_CORE_CHANNEL_DMA: +- case GK110_DISP_CORE_CHANNEL_DMA: +- case GM107_DISP_CORE_CHANNEL_DMA: +- case GF110_DISP_BASE_CHANNEL_DMA: +- case GK104_DISP_BASE_CHANNEL_DMA: +- case GK110_DISP_BASE_CHANNEL_DMA: +- case GF110_DISP_OVERLAY_CONTROL_DMA: +- case GK104_DISP_OVERLAY_CONTROL_DMA: +- break; +- default: +- return -EINVAL; +- } +- } else +- return 0; +- +- ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj); +- if (ret == 0) { +- nv_wo32(*pgpuobj, 0x00, priv->flags0); +- nv_wo32(*pgpuobj, 0x04, priv->base.start >> 8); +- nv_wo32(*pgpuobj, 0x08, priv->base.limit >> 8); +- nv_wo32(*pgpuobj, 0x0c, 0x00000000); +- nv_wo32(*pgpuobj, 0x10, 0x00000000); +- nv_wo32(*pgpuobj, 0x14, 0x00000000); +- } +- +- return ret; +-} +- +-static int +-nvd0_dmaobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_dmaeng *dmaeng = (void *)engine; +- union { +- struct gf110_dma_v0 v0; +- } *args; +- struct nvd0_dmaobj_priv *priv; +- u32 kind, page; +- int ret; +- +- ret = nvkm_dmaobj_create(parent, engine, oclass, &data, &size, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- args = data; +- +- nv_ioctl(parent, "create gf110 dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create gf100 dma vers %d page %d kind %02x\n", +- args->v0.version, args->v0.page, args->v0.kind); +- kind = args->v0.kind; +- page = args->v0.page; +- } else +- if (size == 0) { +- if (priv->base.target != NV_MEM_TARGET_VM) { +- kind = GF110_DMA_V0_KIND_PITCH; +- page = GF110_DMA_V0_PAGE_SP; +- } else { +- kind = GF110_DMA_V0_KIND_VM; +- page = GF110_DMA_V0_PAGE_LP; +- } +- } else +- return ret; +- +- if (page > 1) +- return -EINVAL; +- priv->flags0 = (kind << 20) | (page << 6); +- +- switch (priv->base.target) { +- case NV_MEM_TARGET_VRAM: +- priv->flags0 |= 0x00000009; +- break; +- case NV_MEM_TARGET_VM: +- case NV_MEM_TARGET_PCI: +- case NV_MEM_TARGET_PCI_NOSNOOP: +- /* XXX: don't currently know how to construct a real one +- * of these. we only use them to represent pushbufs +- * on these chipsets, and the classes that use them +- * deal with the target themselves. +- */ +- break; +- default: +- return -EINVAL; +- } +- +- return dmaeng->bind(&priv->base, nv_object(priv), (void *)pobject); +-} +- +-static struct nouveau_ofuncs +-nvd0_dmaobj_ofuncs = { +- .ctor = nvd0_dmaobj_ctor, +- .dtor = _nvkm_dmaobj_dtor, +- .init = _nvkm_dmaobj_init, +- .fini = _nvkm_dmaobj_fini, +-}; +- +-static struct nouveau_oclass +-nvd0_dmaeng_sclass[] = { +- { NV_DMA_FROM_MEMORY, &nvd0_dmaobj_ofuncs }, +- { NV_DMA_TO_MEMORY, &nvd0_dmaobj_ofuncs }, +- { NV_DMA_IN_MEMORY, &nvd0_dmaobj_ofuncs }, +- {} +-}; +- +-struct nouveau_oclass * +-nvd0_dmaeng_oclass = &(struct nvkm_dmaeng_impl) { +- .base.handle = NV_ENGINE(DMAOBJ, 0xd0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_dmaeng_ctor, +- .dtor = _nvkm_dmaeng_dtor, +- .init = _nvkm_dmaeng_init, +- .fini = _nvkm_dmaeng_fini, +- }, +- .sclass = nvd0_dmaeng_sclass, +- .bind = nvd0_dmaobj_bind, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h b/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h +deleted file mode 100644 +index 36f74386..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/dmaobj/priv.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-#ifndef __NVKM_DMAOBJ_PRIV_H__ +-#define __NVKM_DMAOBJ_PRIV_H__ +- +-#include +- +-#define nvkm_dmaobj_create(p,e,c,pa,sa,d) \ +- nvkm_dmaobj_create_((p), (e), (c), (pa), (sa), sizeof(**d), (void **)d) +- +-int nvkm_dmaobj_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void **, u32 *, +- int, void **); +-#define _nvkm_dmaobj_dtor nouveau_object_destroy +-#define _nvkm_dmaobj_init nouveau_object_init +-#define _nvkm_dmaobj_fini nouveau_object_fini +- +-int _nvkm_dmaeng_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-#define _nvkm_dmaeng_dtor _nouveau_engine_dtor +-#define _nvkm_dmaeng_init _nouveau_engine_init +-#define _nvkm_dmaeng_fini _nouveau_engine_fini +- +-struct nvkm_dmaeng_impl { +- struct nouveau_oclass base; +- struct nouveau_oclass *sclass; +- int (*bind)(struct nouveau_dmaobj *, struct nouveau_object *, +- struct nouveau_gpuobj **); +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/falcon.c b/drivers/gpu/drm/nouveau/core/engine/falcon.c +deleted file mode 100644 +index 2914646c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/falcon.c ++++ /dev/null +@@ -1,278 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-void +-nouveau_falcon_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_falcon *falcon = (void *)subdev; +- u32 dispatch = nv_ro32(falcon, 0x01c); +- u32 intr = nv_ro32(falcon, 0x008) & dispatch & ~(dispatch >> 16); +- +- if (intr & 0x00000010) { +- nv_debug(falcon, "ucode halted\n"); +- nv_wo32(falcon, 0x004, 0x00000010); +- intr &= ~0x00000010; +- } +- +- if (intr) { +- nv_error(falcon, "unhandled intr 0x%08x\n", intr); +- nv_wo32(falcon, 0x004, intr); +- } +-} +- +-u32 +-_nouveau_falcon_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_falcon *falcon = (void *)object; +- return nv_rd32(falcon, falcon->addr + addr); +-} +- +-void +-_nouveau_falcon_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nouveau_falcon *falcon = (void *)object; +- nv_wr32(falcon, falcon->addr + addr, data); +-} +- +-static void * +-vmemdup(const void *src, size_t len) +-{ +- void *p = vmalloc(len); +- +- if (p) +- memcpy(p, src, len); +- return p; +-} +- +-int +-_nouveau_falcon_init(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nouveau_falcon *falcon = (void *)object; +- const struct firmware *fw; +- char name[32] = "internal"; +- int ret, i; +- u32 caps; +- +- /* enable engine, and determine its capabilities */ +- ret = nouveau_engine_init(&falcon->base); +- if (ret) +- return ret; +- +- if (device->chipset < 0xa3 || +- device->chipset == 0xaa || device->chipset == 0xac) { +- falcon->version = 0; +- falcon->secret = (falcon->addr == 0x087000) ? 1 : 0; +- } else { +- caps = nv_ro32(falcon, 0x12c); +- falcon->version = (caps & 0x0000000f); +- falcon->secret = (caps & 0x00000030) >> 4; +- } +- +- caps = nv_ro32(falcon, 0x108); +- falcon->code.limit = (caps & 0x000001ff) << 8; +- falcon->data.limit = (caps & 0x0003fe00) >> 1; +- +- nv_debug(falcon, "falcon version: %d\n", falcon->version); +- nv_debug(falcon, "secret level: %d\n", falcon->secret); +- nv_debug(falcon, "code limit: %d\n", falcon->code.limit); +- nv_debug(falcon, "data limit: %d\n", falcon->data.limit); +- +- /* wait for 'uc halted' to be signalled before continuing */ +- if (falcon->secret && falcon->version < 4) { +- if (!falcon->version) +- nv_wait(falcon, 0x008, 0x00000010, 0x00000010); +- else +- nv_wait(falcon, 0x180, 0x80000000, 0); +- nv_wo32(falcon, 0x004, 0x00000010); +- } +- +- /* disable all interrupts */ +- nv_wo32(falcon, 0x014, 0xffffffff); +- +- /* no default ucode provided by the engine implementation, try and +- * locate a "self-bootstrapping" firmware image for the engine +- */ +- if (!falcon->code.data) { +- snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03x", +- device->chipset, falcon->addr >> 12); +- +- ret = request_firmware(&fw, name, nv_device_base(device)); +- if (ret == 0) { +- falcon->code.data = vmemdup(fw->data, fw->size); +- falcon->code.size = fw->size; +- falcon->data.data = NULL; +- falcon->data.size = 0; +- release_firmware(fw); +- } +- +- falcon->external = true; +- } +- +- /* next step is to try and load "static code/data segment" firmware +- * images for the engine +- */ +- if (!falcon->code.data) { +- snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xd", +- device->chipset, falcon->addr >> 12); +- +- ret = request_firmware(&fw, name, nv_device_base(device)); +- if (ret) { +- nv_error(falcon, "unable to load firmware data\n"); +- return ret; +- } +- +- falcon->data.data = vmemdup(fw->data, fw->size); +- falcon->data.size = fw->size; +- release_firmware(fw); +- if (!falcon->data.data) +- return -ENOMEM; +- +- snprintf(name, sizeof(name), "nouveau/nv%02x_fuc%03xc", +- device->chipset, falcon->addr >> 12); +- +- ret = request_firmware(&fw, name, nv_device_base(device)); +- if (ret) { +- nv_error(falcon, "unable to load firmware code\n"); +- return ret; +- } +- +- falcon->code.data = vmemdup(fw->data, fw->size); +- falcon->code.size = fw->size; +- release_firmware(fw); +- if (!falcon->code.data) +- return -ENOMEM; +- } +- +- nv_debug(falcon, "firmware: %s (%s)\n", name, falcon->data.data ? +- "static code/data segments" : "self-bootstrapping"); +- +- /* ensure any "self-bootstrapping" firmware image is in vram */ +- if (!falcon->data.data && !falcon->core) { +- ret = nouveau_gpuobj_new(object->parent, NULL, +- falcon->code.size, 256, 0, +- &falcon->core); +- if (ret) { +- nv_error(falcon, "core allocation failed, %d\n", ret); +- return ret; +- } +- +- for (i = 0; i < falcon->code.size; i += 4) +- nv_wo32(falcon->core, i, falcon->code.data[i / 4]); +- } +- +- /* upload firmware bootloader (or the full code segments) */ +- if (falcon->core) { +- if (device->card_type < NV_C0) +- nv_wo32(falcon, 0x618, 0x04000000); +- else +- nv_wo32(falcon, 0x618, 0x00000114); +- nv_wo32(falcon, 0x11c, 0); +- nv_wo32(falcon, 0x110, falcon->core->addr >> 8); +- nv_wo32(falcon, 0x114, 0); +- nv_wo32(falcon, 0x118, 0x00006610); +- } else { +- if (falcon->code.size > falcon->code.limit || +- falcon->data.size > falcon->data.limit) { +- nv_error(falcon, "ucode exceeds falcon limit(s)\n"); +- return -EINVAL; +- } +- +- if (falcon->version < 3) { +- nv_wo32(falcon, 0xff8, 0x00100000); +- for (i = 0; i < falcon->code.size / 4; i++) +- nv_wo32(falcon, 0xff4, falcon->code.data[i]); +- } else { +- nv_wo32(falcon, 0x180, 0x01000000); +- for (i = 0; i < falcon->code.size / 4; i++) { +- if ((i & 0x3f) == 0) +- nv_wo32(falcon, 0x188, i >> 6); +- nv_wo32(falcon, 0x184, falcon->code.data[i]); +- } +- } +- } +- +- /* upload data segment (if necessary), zeroing the remainder */ +- if (falcon->version < 3) { +- nv_wo32(falcon, 0xff8, 0x00000000); +- for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) +- nv_wo32(falcon, 0xff4, falcon->data.data[i]); +- for (; i < falcon->data.limit; i += 4) +- nv_wo32(falcon, 0xff4, 0x00000000); +- } else { +- nv_wo32(falcon, 0x1c0, 0x01000000); +- for (i = 0; !falcon->core && i < falcon->data.size / 4; i++) +- nv_wo32(falcon, 0x1c4, falcon->data.data[i]); +- for (; i < falcon->data.limit / 4; i++) +- nv_wo32(falcon, 0x1c4, 0x00000000); +- } +- +- /* start it running */ +- nv_wo32(falcon, 0x10c, 0x00000001); /* BLOCK_ON_FIFO */ +- nv_wo32(falcon, 0x104, 0x00000000); /* ENTRY */ +- nv_wo32(falcon, 0x100, 0x00000002); /* TRIGGER */ +- nv_wo32(falcon, 0x048, 0x00000003); /* FIFO | CHSW */ +- return 0; +-} +- +-int +-_nouveau_falcon_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_falcon *falcon = (void *)object; +- +- if (!suspend) { +- nouveau_gpuobj_ref(NULL, &falcon->core); +- if (falcon->external) { +- vfree(falcon->data.data); +- vfree(falcon->code.data); +- falcon->code.data = NULL; +- } +- } +- +- nv_mo32(falcon, 0x048, 0x00000003, 0x00000000); +- nv_wo32(falcon, 0x014, 0xffffffff); +- +- return nouveau_engine_fini(&falcon->base, suspend); +-} +- +-int +-nouveau_falcon_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 addr, bool enable, +- const char *iname, const char *fname, +- int length, void **pobject) +-{ +- struct nouveau_falcon *falcon; +- int ret; +- +- ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, +- fname, length, pobject); +- falcon = *pobject; +- if (ret) +- return ret; +- +- falcon->addr = addr; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c b/drivers/gpu/drm/nouveau/core/engine/fifo/base.c +deleted file mode 100644 +index ac8375cf..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/base.c ++++ /dev/null +@@ -1,283 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-static int +-nouveau_fifo_event_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- if (size == 0) { +- notify->size = 0; +- notify->types = 1; +- notify->index = 0; +- return 0; +- } +- return -ENOSYS; +-} +- +-static const struct nvkm_event_func +-nouveau_fifo_event_func = { +- .ctor = nouveau_fifo_event_ctor, +-}; +- +-int +-nouveau_fifo_channel_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int bar, u32 addr, u32 size, u32 pushbuf, +- u64 engmask, int len, void **ptr) +-{ +- struct nouveau_device *device = nv_device(engine); +- struct nouveau_fifo *priv = (void *)engine; +- struct nouveau_fifo_chan *chan; +- struct nouveau_dmaeng *dmaeng; +- unsigned long flags; +- int ret; +- +- /* create base object class */ +- ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL, +- engmask, len, ptr); +- chan = *ptr; +- if (ret) +- return ret; +- +- /* validate dma object representing push buffer */ +- chan->pushdma = (void *)nouveau_handle_ref(parent, pushbuf); +- if (!chan->pushdma) +- return -ENOENT; +- +- dmaeng = (void *)chan->pushdma->base.engine; +- switch (chan->pushdma->base.oclass->handle) { +- case NV_DMA_FROM_MEMORY: +- case NV_DMA_IN_MEMORY: +- break; +- default: +- return -EINVAL; +- } +- +- ret = dmaeng->bind(chan->pushdma, parent, &chan->pushgpu); +- if (ret) +- return ret; +- +- /* find a free fifo channel */ +- spin_lock_irqsave(&priv->lock, flags); +- for (chan->chid = priv->min; chan->chid < priv->max; chan->chid++) { +- if (!priv->channel[chan->chid]) { +- priv->channel[chan->chid] = nv_object(chan); +- break; +- } +- } +- spin_unlock_irqrestore(&priv->lock, flags); +- +- if (chan->chid == priv->max) { +- nv_error(priv, "no free channels\n"); +- return -ENOSPC; +- } +- +- chan->addr = nv_device_resource_start(device, bar) + +- addr + size * chan->chid; +- chan->size = size; +- nvkm_event_send(&priv->cevent, 1, 0, NULL, 0); +- return 0; +-} +- +-void +-nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *chan) +-{ +- struct nouveau_fifo *priv = (void *)nv_object(chan)->engine; +- unsigned long flags; +- +- if (chan->user) +- iounmap(chan->user); +- +- spin_lock_irqsave(&priv->lock, flags); +- priv->channel[chan->chid] = NULL; +- spin_unlock_irqrestore(&priv->lock, flags); +- +- nouveau_gpuobj_ref(NULL, &chan->pushgpu); +- nouveau_object_ref(NULL, (struct nouveau_object **)&chan->pushdma); +- nouveau_namedb_destroy(&chan->base); +-} +- +-void +-_nouveau_fifo_channel_dtor(struct nouveau_object *object) +-{ +- struct nouveau_fifo_chan *chan = (void *)object; +- nouveau_fifo_channel_destroy(chan); +-} +- +-int +-_nouveau_fifo_channel_map(struct nouveau_object *object, u64 *addr, u32 *size) +-{ +- struct nouveau_fifo_chan *chan = (void *)object; +- *addr = chan->addr; +- *size = chan->size; +- return 0; +-} +- +-u32 +-_nouveau_fifo_channel_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_fifo_chan *chan = (void *)object; +- if (unlikely(!chan->user)) { +- chan->user = ioremap(chan->addr, chan->size); +- if (WARN_ON_ONCE(chan->user == NULL)) +- return 0; +- } +- return ioread32_native(chan->user + addr); +-} +- +-void +-_nouveau_fifo_channel_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nouveau_fifo_chan *chan = (void *)object; +- if (unlikely(!chan->user)) { +- chan->user = ioremap(chan->addr, chan->size); +- if (WARN_ON_ONCE(chan->user == NULL)) +- return; +- } +- iowrite32_native(data, chan->user + addr); +-} +- +-int +-nouveau_fifo_uevent_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- union { +- struct nvif_notify_uevent_req none; +- } *req = data; +- int ret; +- +- if (nvif_unvers(req->none)) { +- notify->size = sizeof(struct nvif_notify_uevent_rep); +- notify->types = 1; +- notify->index = 0; +- } +- +- return ret; +-} +- +-void +-nouveau_fifo_uevent(struct nouveau_fifo *fifo) +-{ +- struct nvif_notify_uevent_rep rep = { +- }; +- nvkm_event_send(&fifo->uevent, 1, 0, &rep, sizeof(rep)); +-} +- +-int +-_nouveau_fifo_channel_ntfy(struct nouveau_object *object, u32 type, +- struct nvkm_event **event) +-{ +- struct nouveau_fifo *fifo = (void *)object->engine; +- switch (type) { +- case G82_CHANNEL_DMA_V0_NTFY_UEVENT: +- if (nv_mclass(object) >= G82_CHANNEL_DMA) { +- *event = &fifo->uevent; +- return 0; +- } +- break; +- default: +- break; +- } +- return -EINVAL; +-} +- +-static int +-nouveau_fifo_chid(struct nouveau_fifo *priv, struct nouveau_object *object) +-{ +- int engidx = nv_hclass(priv) & 0xff; +- +- while (object && object->parent) { +- if ( nv_iclass(object->parent, NV_ENGCTX_CLASS) && +- (nv_hclass(object->parent) & 0xff) == engidx) +- return nouveau_fifo_chan(object)->chid; +- object = object->parent; +- } +- +- return -1; +-} +- +-const char * +-nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid) +-{ +- struct nouveau_fifo_chan *chan = NULL; +- unsigned long flags; +- +- spin_lock_irqsave(&fifo->lock, flags); +- if (chid >= fifo->min && chid <= fifo->max) +- chan = (void *)fifo->channel[chid]; +- spin_unlock_irqrestore(&fifo->lock, flags); +- +- return nouveau_client_name(chan); +-} +- +-void +-nouveau_fifo_destroy(struct nouveau_fifo *priv) +-{ +- kfree(priv->channel); +- nvkm_event_fini(&priv->uevent); +- nvkm_event_fini(&priv->cevent); +- nouveau_engine_destroy(&priv->base); +-} +- +-int +-nouveau_fifo_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int min, int max, int length, void **pobject) +-{ +- struct nouveau_fifo *priv; +- int ret; +- +- ret = nouveau_engine_create_(parent, engine, oclass, true, "PFIFO", +- "fifo", length, pobject); +- priv = *pobject; +- if (ret) +- return ret; +- +- priv->min = min; +- priv->max = max; +- priv->channel = kzalloc(sizeof(*priv->channel) * (max + 1), GFP_KERNEL); +- if (!priv->channel) +- return -ENOMEM; +- +- ret = nvkm_event_init(&nouveau_fifo_event_func, 1, 1, &priv->cevent); +- if (ret) +- return ret; +- +- priv->chid = nouveau_fifo_chid; +- spin_lock_init(&priv->lock); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c +deleted file mode 100644 +index 327456ea..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/gk20a.c ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include "nve0.h" +- +-struct nouveau_oclass * +-gk20a_fifo_oclass = &(struct nve0_fifo_impl) { +- .base.handle = NV_ENGINE(FIFO, 0xea), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_fifo_ctor, +- .dtor = nve0_fifo_dtor, +- .init = nve0_fifo_init, +- .fini = nve0_fifo_fini, +- }, +- .channels = 128, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c +deleted file mode 100644 +index 1931057f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c ++++ /dev/null +@@ -1,656 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-#include +- +-#include "nv04.h" +- +-static struct ramfc_desc +-nv04_ramfc[] = { +- { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, +- { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, +- { 16, 0, 0x08, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, +- { 16, 16, 0x08, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, +- { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_STATE }, +- { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, +- { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_ENGINE }, +- { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_PULL1 }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-int +-nv04_fifo_object_attach(struct nouveau_object *parent, +- struct nouveau_object *object, u32 handle) +-{ +- struct nv04_fifo_priv *priv = (void *)parent->engine; +- struct nv04_fifo_chan *chan = (void *)parent; +- u32 context, chid = chan->base.chid; +- int ret; +- +- if (nv_iclass(object, NV_GPUOBJ_CLASS)) +- context = nv_gpuobj(object)->addr >> 4; +- else +- context = 0x00000004; /* just non-zero */ +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_DMAOBJ: +- case NVDEV_ENGINE_SW: +- context |= 0x00000000; +- break; +- case NVDEV_ENGINE_GR: +- context |= 0x00010000; +- break; +- case NVDEV_ENGINE_MPEG: +- context |= 0x00020000; +- break; +- default: +- return -EINVAL; +- } +- +- context |= 0x80000000; /* valid */ +- context |= chid << 24; +- +- mutex_lock(&nv_subdev(priv)->mutex); +- ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); +- mutex_unlock(&nv_subdev(priv)->mutex); +- return ret; +-} +- +-void +-nv04_fifo_object_detach(struct nouveau_object *parent, int cookie) +-{ +- struct nv04_fifo_priv *priv = (void *)parent->engine; +- mutex_lock(&nv_subdev(priv)->mutex); +- nouveau_ramht_remove(priv->ramht, cookie); +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-int +-nv04_fifo_context_attach(struct nouveau_object *parent, +- struct nouveau_object *object) +-{ +- nv_engctx(object)->addr = nouveau_fifo_chan(parent)->chid; +- return 0; +-} +- +-static int +-nv04_fifo_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv03_channel_dma_v0 v0; +- } *args = data; +- struct nv04_fifo_priv *priv = (void *)engine; +- struct nv04_fifo_chan *chan; +- int ret; +- +- nv_ioctl(parent, "create channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " +- "offset %016llx\n", args->v0.version, +- args->v0.pushbuf, args->v0.offset); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, +- 0x10000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->object_attach = nv04_fifo_object_attach; +- nv_parent(chan)->object_detach = nv04_fifo_object_detach; +- nv_parent(chan)->context_attach = nv04_fifo_context_attach; +- chan->ramfc = chan->base.chid * 32; +- +- nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); +- nv_wo32(priv->ramfc, chan->ramfc + 0x10, +- NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | +- NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +-#ifdef __BIG_ENDIAN +- NV_PFIFO_CACHE1_BIG_ENDIAN | +-#endif +- NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); +- return 0; +-} +- +-void +-nv04_fifo_chan_dtor(struct nouveau_object *object) +-{ +- struct nv04_fifo_priv *priv = (void *)object->engine; +- struct nv04_fifo_chan *chan = (void *)object; +- struct ramfc_desc *c = priv->ramfc_desc; +- +- do { +- nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); +- } while ((++c)->bits); +- +- nouveau_fifo_channel_destroy(&chan->base); +-} +- +-int +-nv04_fifo_chan_init(struct nouveau_object *object) +-{ +- struct nv04_fifo_priv *priv = (void *)object->engine; +- struct nv04_fifo_chan *chan = (void *)object; +- u32 mask = 1 << chan->base.chid; +- unsigned long flags; +- int ret; +- +- ret = nouveau_fifo_channel_init(&chan->base); +- if (ret) +- return ret; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- nv_mask(priv, NV04_PFIFO_MODE, mask, mask); +- spin_unlock_irqrestore(&priv->base.lock, flags); +- return 0; +-} +- +-int +-nv04_fifo_chan_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv04_fifo_priv *priv = (void *)object->engine; +- struct nv04_fifo_chan *chan = (void *)object; +- struct nouveau_gpuobj *fctx = priv->ramfc; +- struct ramfc_desc *c; +- unsigned long flags; +- u32 data = chan->ramfc; +- u32 chid; +- +- /* prevent fifo context switches */ +- spin_lock_irqsave(&priv->base.lock, flags); +- nv_wr32(priv, NV03_PFIFO_CACHES, 0); +- +- /* if this channel is active, replace it with a null context */ +- chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; +- if (chid == chan->base.chid) { +- nv_mask(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001, 0); +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 0); +- nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0); +- +- c = priv->ramfc_desc; +- do { +- u32 rm = ((1ULL << c->bits) - 1) << c->regs; +- u32 cm = ((1ULL << c->bits) - 1) << c->ctxs; +- u32 rv = (nv_rd32(priv, c->regp) & rm) >> c->regs; +- u32 cv = (nv_ro32(fctx, c->ctxp + data) & ~cm); +- nv_wo32(fctx, c->ctxp + data, cv | (rv << c->ctxs)); +- } while ((++c)->bits); +- +- c = priv->ramfc_desc; +- do { +- nv_wr32(priv, c->regp, 0x00000000); +- } while ((++c)->bits); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_GET, 0); +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUT, 0); +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); +- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); +- } +- +- /* restore normal operation, after disabling dma mode */ +- nv_mask(priv, NV04_PFIFO_MODE, 1 << chan->base.chid, 0); +- nv_wr32(priv, NV03_PFIFO_CACHES, 1); +- spin_unlock_irqrestore(&priv->base.lock, flags); +- +- return nouveau_fifo_channel_fini(&chan->base, suspend); +-} +- +-static struct nouveau_ofuncs +-nv04_fifo_ofuncs = { +- .ctor = nv04_fifo_chan_ctor, +- .dtor = nv04_fifo_chan_dtor, +- .init = nv04_fifo_chan_init, +- .fini = nv04_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nv04_fifo_sclass[] = { +- { NV03_CHANNEL_DMA, &nv04_fifo_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - basically just the instmem reserved for the channel +- ******************************************************************************/ +- +-int +-nv04_fifo_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_fifo_base *base; +- int ret; +- +- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, +- 0x1000, NVOBJ_FLAG_HEAP, &base); +- *pobject = nv_object(base); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static struct nouveau_oclass +-nv04_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fifo_context_ctor, +- .dtor = _nouveau_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-void +-nv04_fifo_pause(struct nouveau_fifo *pfifo, unsigned long *pflags) +-__acquires(priv->base.lock) +-{ +- struct nv04_fifo_priv *priv = (void *)pfifo; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- *pflags = flags; +- +- nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000000); +- nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); +- +- /* in some cases the puller may be left in an inconsistent state +- * if you try to stop it while it's busy translating handles. +- * sometimes you get a CACHE_ERROR, sometimes it just fails +- * silently; sending incorrect instance offsets to PGRAPH after +- * it's started up again. +- * +- * to avoid this, we invalidate the most recently calculated +- * instance. +- */ +- if (!nv_wait(priv, NV04_PFIFO_CACHE1_PULL0, +- NV04_PFIFO_CACHE1_PULL0_HASH_BUSY, 0x00000000)) +- nv_warn(priv, "timeout idling puller\n"); +- +- if (nv_rd32(priv, NV04_PFIFO_CACHE1_PULL0) & +- NV04_PFIFO_CACHE1_PULL0_HASH_FAILED) +- nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); +- +- nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0x00000000); +-} +- +-void +-nv04_fifo_start(struct nouveau_fifo *pfifo, unsigned long *pflags) +-__releases(priv->base.lock) +-{ +- struct nv04_fifo_priv *priv = (void *)pfifo; +- unsigned long flags = *pflags; +- +- nv_mask(priv, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); +- nv_wr32(priv, NV03_PFIFO_CACHES, 0x00000001); +- +- spin_unlock_irqrestore(&priv->base.lock, flags); +-} +- +-static const char * +-nv_dma_state_err(u32 state) +-{ +- static const char * const desc[] = { +- "NONE", "CALL_SUBR_ACTIVE", "INVALID_MTHD", "RET_SUBR_INACTIVE", +- "INVALID_CMD", "IB_EMPTY"/* NV50+ */, "MEM_FAULT", "UNK" +- }; +- return desc[(state >> 29) & 0x7]; +-} +- +-static bool +-nv04_fifo_swmthd(struct nv04_fifo_priv *priv, u32 chid, u32 addr, u32 data) +-{ +- struct nv04_fifo_chan *chan = NULL; +- struct nouveau_handle *bind; +- const int subc = (addr >> 13) & 0x7; +- const int mthd = addr & 0x1ffc; +- bool handled = false; +- unsigned long flags; +- u32 engine; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- if (likely(chid >= priv->base.min && chid <= priv->base.max)) +- chan = (void *)priv->base.channel[chid]; +- if (unlikely(!chan)) +- goto out; +- +- switch (mthd) { +- case 0x0000: +- bind = nouveau_namedb_get(nv_namedb(chan), data); +- if (unlikely(!bind)) +- break; +- +- if (nv_engidx(bind->object->engine) == NVDEV_ENGINE_SW) { +- engine = 0x0000000f << (subc * 4); +- chan->subc[subc] = data; +- handled = true; +- +- nv_mask(priv, NV04_PFIFO_CACHE1_ENGINE, engine, 0); +- } +- +- nouveau_namedb_put(bind); +- break; +- default: +- engine = nv_rd32(priv, NV04_PFIFO_CACHE1_ENGINE); +- if (unlikely(((engine >> (subc * 4)) & 0xf) != 0)) +- break; +- +- bind = nouveau_namedb_get(nv_namedb(chan), chan->subc[subc]); +- if (likely(bind)) { +- if (!nv_call(bind->object, mthd, data)) +- handled = true; +- nouveau_namedb_put(bind); +- } +- break; +- } +- +-out: +- spin_unlock_irqrestore(&priv->base.lock, flags); +- return handled; +-} +- +-static void +-nv04_fifo_cache_error(struct nouveau_device *device, +- struct nv04_fifo_priv *priv, u32 chid, u32 get) +-{ +- u32 mthd, data; +- int ptr; +- +- /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before wrapping on my +- * G80 chips, but CACHE1 isn't big enough for this much data.. Tests +- * show that it wraps around to the start at GET=0x800.. No clue as to +- * why.. +- */ +- ptr = (get & 0x7ff) >> 2; +- +- if (device->card_type < NV_40) { +- mthd = nv_rd32(priv, NV04_PFIFO_CACHE1_METHOD(ptr)); +- data = nv_rd32(priv, NV04_PFIFO_CACHE1_DATA(ptr)); +- } else { +- mthd = nv_rd32(priv, NV40_PFIFO_CACHE1_METHOD(ptr)); +- data = nv_rd32(priv, NV40_PFIFO_CACHE1_DATA(ptr)); +- } +- +- if (!nv04_fifo_swmthd(priv, chid, mthd, data)) { +- const char *client_name = +- nouveau_client_name_for_fifo_chid(&priv->base, chid); +- nv_error(priv, +- "CACHE_ERROR - ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", +- chid, client_name, (mthd >> 13) & 7, mthd & 0x1ffc, +- data); +- } +- +- nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, 0); +- nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, +- nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) & ~1); +- nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, +- nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH0) | 1); +- nv_wr32(priv, NV04_PFIFO_CACHE1_HASH, 0); +- +- nv_wr32(priv, NV04_PFIFO_CACHE1_DMA_PUSH, +- nv_rd32(priv, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); +- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); +-} +- +-static void +-nv04_fifo_dma_pusher(struct nouveau_device *device, struct nv04_fifo_priv *priv, +- u32 chid) +-{ +- const char *client_name; +- u32 dma_get = nv_rd32(priv, 0x003244); +- u32 dma_put = nv_rd32(priv, 0x003240); +- u32 push = nv_rd32(priv, 0x003220); +- u32 state = nv_rd32(priv, 0x003228); +- +- client_name = nouveau_client_name_for_fifo_chid(&priv->base, chid); +- +- if (device->card_type == NV_50) { +- u32 ho_get = nv_rd32(priv, 0x003328); +- u32 ho_put = nv_rd32(priv, 0x003320); +- u32 ib_get = nv_rd32(priv, 0x003334); +- u32 ib_put = nv_rd32(priv, 0x003330); +- +- nv_error(priv, +- "DMA_PUSHER - ch %d [%s] get 0x%02x%08x put 0x%02x%08x ib_get 0x%08x ib_put 0x%08x state 0x%08x (err: %s) push 0x%08x\n", +- chid, client_name, ho_get, dma_get, ho_put, dma_put, +- ib_get, ib_put, state, nv_dma_state_err(state), push); +- +- /* METHOD_COUNT, in DMA_STATE on earlier chipsets */ +- nv_wr32(priv, 0x003364, 0x00000000); +- if (dma_get != dma_put || ho_get != ho_put) { +- nv_wr32(priv, 0x003244, dma_put); +- nv_wr32(priv, 0x003328, ho_put); +- } else +- if (ib_get != ib_put) +- nv_wr32(priv, 0x003334, ib_put); +- } else { +- nv_error(priv, +- "DMA_PUSHER - ch %d [%s] get 0x%08x put 0x%08x state 0x%08x (err: %s) push 0x%08x\n", +- chid, client_name, dma_get, dma_put, state, +- nv_dma_state_err(state), push); +- +- if (dma_get != dma_put) +- nv_wr32(priv, 0x003244, dma_put); +- } +- +- nv_wr32(priv, 0x003228, 0x00000000); +- nv_wr32(priv, 0x003220, 0x00000001); +- nv_wr32(priv, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); +-} +- +-void +-nv04_fifo_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_device *device = nv_device(subdev); +- struct nv04_fifo_priv *priv = (void *)subdev; +- uint32_t status, reassign; +- int cnt = 0; +- +- reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1; +- while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) { +- uint32_t chid, get; +- +- nv_wr32(priv, NV03_PFIFO_CACHES, 0); +- +- chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max; +- get = nv_rd32(priv, NV03_PFIFO_CACHE1_GET); +- +- if (status & NV_PFIFO_INTR_CACHE_ERROR) { +- nv04_fifo_cache_error(device, priv, chid, get); +- status &= ~NV_PFIFO_INTR_CACHE_ERROR; +- } +- +- if (status & NV_PFIFO_INTR_DMA_PUSHER) { +- nv04_fifo_dma_pusher(device, priv, chid); +- status &= ~NV_PFIFO_INTR_DMA_PUSHER; +- } +- +- if (status & NV_PFIFO_INTR_SEMAPHORE) { +- uint32_t sem; +- +- status &= ~NV_PFIFO_INTR_SEMAPHORE; +- nv_wr32(priv, NV03_PFIFO_INTR_0, +- NV_PFIFO_INTR_SEMAPHORE); +- +- sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE); +- nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_GET, get + 4); +- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); +- } +- +- if (device->card_type == NV_50) { +- if (status & 0x00000010) { +- status &= ~0x00000010; +- nv_wr32(priv, 0x002100, 0x00000010); +- } +- +- if (status & 0x40000000) { +- nv_wr32(priv, 0x002100, 0x40000000); +- nouveau_fifo_uevent(&priv->base); +- status &= ~0x40000000; +- } +- } +- +- if (status) { +- nv_warn(priv, "unknown intr 0x%08x, ch %d\n", +- status, chid); +- nv_wr32(priv, NV03_PFIFO_INTR_0, status); +- status = 0; +- } +- +- nv_wr32(priv, NV03_PFIFO_CACHES, reassign); +- } +- +- if (status) { +- nv_error(priv, "still angry after %d spins, halt\n", cnt); +- nv_wr32(priv, 0x002140, 0); +- nv_wr32(priv, 0x000140, 0); +- } +- +- nv_wr32(priv, 0x000100, 0x00000100); +-} +- +-static int +-nv04_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_instmem_priv *imem = nv04_instmem(parent); +- struct nv04_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 0, 15, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nouveau_ramht_ref(imem->ramht, &priv->ramht); +- nouveau_gpuobj_ref(imem->ramro, &priv->ramro); +- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nv04_fifo_intr; +- nv_engine(priv)->cclass = &nv04_fifo_cclass; +- nv_engine(priv)->sclass = nv04_fifo_sclass; +- priv->base.pause = nv04_fifo_pause; +- priv->base.start = nv04_fifo_start; +- priv->ramfc_desc = nv04_ramfc; +- return 0; +-} +- +-void +-nv04_fifo_dtor(struct nouveau_object *object) +-{ +- struct nv04_fifo_priv *priv = (void *)object; +- nouveau_gpuobj_ref(NULL, &priv->ramfc); +- nouveau_gpuobj_ref(NULL, &priv->ramro); +- nouveau_ramht_ref(NULL, &priv->ramht); +- nouveau_fifo_destroy(&priv->base); +-} +- +-int +-nv04_fifo_init(struct nouveau_object *object) +-{ +- struct nv04_fifo_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fifo_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); +- nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); +- +- nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | +- ((priv->ramht->bits - 9) << 16) | +- (priv->ramht->base.addr >> 8)); +- nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); +- nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); +- +- nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); +- nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); +- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); +- nv_wr32(priv, NV03_PFIFO_CACHES, 1); +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fifo_ctor, +- .dtor = nv04_fifo_dtor, +- .init = nv04_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h +deleted file mode 100644 +index 496a4b4f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv04.h ++++ /dev/null +@@ -1,178 +0,0 @@ +-#ifndef __NV04_FIFO_H__ +-#define __NV04_FIFO_H__ +- +-#include +- +-#define NV04_PFIFO_DELAY_0 0x00002040 +-#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 +-#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 +-#define NV03_PFIFO_INTR_0 0x00002100 +-#define NV03_PFIFO_INTR_EN_0 0x00002140 +-# define NV_PFIFO_INTR_CACHE_ERROR (1<<0) +-# define NV_PFIFO_INTR_RUNOUT (1<<4) +-# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) +-# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) +-# define NV_PFIFO_INTR_DMA_PT (1<<16) +-# define NV_PFIFO_INTR_SEMAPHORE (1<<20) +-# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) +-#define NV03_PFIFO_RAMHT 0x00002210 +-#define NV03_PFIFO_RAMFC 0x00002214 +-#define NV03_PFIFO_RAMRO 0x00002218 +-#define NV40_PFIFO_RAMFC 0x00002220 +-#define NV03_PFIFO_CACHES 0x00002500 +-#define NV04_PFIFO_MODE 0x00002504 +-#define NV04_PFIFO_DMA 0x00002508 +-#define NV04_PFIFO_SIZE 0x0000250c +-#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) +-#define NV50_PFIFO_CTX_TABLE__SIZE 128 +-#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) +-#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) +-#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF +-#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF +-#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 +-#define NV03_PFIFO_CACHE0_PULL0 0x00003040 +-#define NV04_PFIFO_CACHE0_PULL0 0x00003050 +-#define NV04_PFIFO_CACHE0_PULL1 0x00003054 +-#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 +-#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 +-#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) +-#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) +-#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f +-#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f +-#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f +-#define NV03_PFIFO_CACHE1_PUT 0x00003210 +-#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 +-#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 +-# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 +-# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF +-# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 +-#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 +-#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c +-#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 +-#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 +-#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 +-#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 +-#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C +-#define NV03_PFIFO_CACHE1_PULL0 0x00003240 +-#define NV04_PFIFO_CACHE1_PULL0 0x00003250 +-# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 +-# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 +-#define NV03_PFIFO_CACHE1_PULL1 0x00003250 +-#define NV04_PFIFO_CACHE1_PULL1 0x00003254 +-#define NV04_PFIFO_CACHE1_HASH 0x00003258 +-#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 +-#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 +-#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 +-#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C +-#define NV03_PFIFO_CACHE1_GET 0x00003270 +-#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 +-#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 +-#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 +-#define NV40_PFIFO_UNK32E4 0x000032E4 +-#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) +-#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) +-#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) +-#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) +- +-struct ramfc_desc { +- unsigned bits:6; +- unsigned ctxs:5; +- unsigned ctxp:8; +- unsigned regs:5; +- unsigned regp; +-}; +- +-struct nv04_fifo_priv { +- struct nouveau_fifo base; +- struct ramfc_desc *ramfc_desc; +- struct nouveau_ramht *ramht; +- struct nouveau_gpuobj *ramro; +- struct nouveau_gpuobj *ramfc; +-}; +- +-struct nv04_fifo_base { +- struct nouveau_fifo_base base; +-}; +- +-struct nv04_fifo_chan { +- struct nouveau_fifo_chan base; +- u32 subc[8]; +- u32 ramfc; +-}; +- +-int nv04_fifo_object_attach(struct nouveau_object *, +- struct nouveau_object *, u32); +-void nv04_fifo_object_detach(struct nouveau_object *, int); +- +-void nv04_fifo_chan_dtor(struct nouveau_object *); +-int nv04_fifo_chan_init(struct nouveau_object *); +-int nv04_fifo_chan_fini(struct nouveau_object *, bool suspend); +- +-int nv04_fifo_context_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-void nv04_fifo_dtor(struct nouveau_object *); +-int nv04_fifo_init(struct nouveau_object *); +-void nv04_fifo_pause(struct nouveau_fifo *, unsigned long *); +-void nv04_fifo_start(struct nouveau_fifo *, unsigned long *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c +deleted file mode 100644 +index 2a32add5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c ++++ /dev/null +@@ -1,183 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-#include "nv04.h" +- +-static struct ramfc_desc +-nv10_ramfc[] = { +- { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, +- { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, +- { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, +- { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, +- { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, +- { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, +- { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, +- { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, +- { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static int +-nv10_fifo_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv03_channel_dma_v0 v0; +- } *args = data; +- struct nv04_fifo_priv *priv = (void *)engine; +- struct nv04_fifo_chan *chan; +- int ret; +- +- nv_ioctl(parent, "create channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " +- "offset %016llx\n", args->v0.version, +- args->v0.pushbuf, args->v0.offset); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, +- 0x10000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->object_attach = nv04_fifo_object_attach; +- nv_parent(chan)->object_detach = nv04_fifo_object_detach; +- nv_parent(chan)->context_attach = nv04_fifo_context_attach; +- chan->ramfc = chan->base.chid * 32; +- +- nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); +- nv_wo32(priv->ramfc, chan->ramfc + 0x14, +- NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | +- NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +-#ifdef __BIG_ENDIAN +- NV_PFIFO_CACHE1_BIG_ENDIAN | +-#endif +- NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv10_fifo_ofuncs = { +- .ctor = nv10_fifo_chan_ctor, +- .dtor = nv04_fifo_chan_dtor, +- .init = nv04_fifo_chan_init, +- .fini = nv04_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nv10_fifo_sclass[] = { +- { NV10_CHANNEL_DMA, &nv10_fifo_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - basically just the instmem reserved for the channel +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv10_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0x10), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fifo_context_ctor, +- .dtor = _nouveau_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static int +-nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_instmem_priv *imem = nv04_instmem(parent); +- struct nv04_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nouveau_ramht_ref(imem->ramht, &priv->ramht); +- nouveau_gpuobj_ref(imem->ramro, &priv->ramro); +- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nv04_fifo_intr; +- nv_engine(priv)->cclass = &nv10_fifo_cclass; +- nv_engine(priv)->sclass = nv10_fifo_sclass; +- priv->base.pause = nv04_fifo_pause; +- priv->base.start = nv04_fifo_start; +- priv->ramfc_desc = nv10_ramfc; +- return 0; +-} +- +-struct nouveau_oclass * +-nv10_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0x10), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv10_fifo_ctor, +- .dtor = nv04_fifo_dtor, +- .init = nv04_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c +deleted file mode 100644 +index 09362a51..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv108.c ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nve0.h" +- +-struct nouveau_oclass * +-nv108_fifo_oclass = &(struct nve0_fifo_impl) { +- .base.handle = NV_ENGINE(FIFO, 0x08), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_fifo_ctor, +- .dtor = nve0_fifo_dtor, +- .init = nve0_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +- .channels = 1024, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c +deleted file mode 100644 +index 12d76c8a..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c ++++ /dev/null +@@ -1,220 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-#include "nv04.h" +- +-static struct ramfc_desc +-nv17_ramfc[] = { +- { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, +- { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, +- { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, +- { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, +- { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, +- { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE }, +- { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, +- { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE }, +- { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 }, +- { 32, 0, 0x20, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, +- { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, +- { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, +- { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, +- { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static int +-nv17_fifo_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv03_channel_dma_v0 v0; +- } *args = data; +- struct nv04_fifo_priv *priv = (void *)engine; +- struct nv04_fifo_chan *chan; +- int ret; +- +- nv_ioctl(parent, "create channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " +- "offset %016llx\n", args->v0.version, +- args->v0.pushbuf, args->v0.offset); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0x800000, +- 0x10000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_MPEG), /* NV31- */ +- &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->object_attach = nv04_fifo_object_attach; +- nv_parent(chan)->object_detach = nv04_fifo_object_detach; +- nv_parent(chan)->context_attach = nv04_fifo_context_attach; +- chan->ramfc = chan->base.chid * 64; +- +- nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); +- nv_wo32(priv->ramfc, chan->ramfc + 0x14, +- NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | +- NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +-#ifdef __BIG_ENDIAN +- NV_PFIFO_CACHE1_BIG_ENDIAN | +-#endif +- NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv17_fifo_ofuncs = { +- .ctor = nv17_fifo_chan_ctor, +- .dtor = nv04_fifo_chan_dtor, +- .init = nv04_fifo_chan_init, +- .fini = nv04_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nv17_fifo_sclass[] = { +- { NV17_CHANNEL_DMA, &nv17_fifo_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - basically just the instmem reserved for the channel +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv17_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0x17), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fifo_context_ctor, +- .dtor = _nouveau_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static int +-nv17_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_instmem_priv *imem = nv04_instmem(parent); +- struct nv04_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nouveau_ramht_ref(imem->ramht, &priv->ramht); +- nouveau_gpuobj_ref(imem->ramro, &priv->ramro); +- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nv04_fifo_intr; +- nv_engine(priv)->cclass = &nv17_fifo_cclass; +- nv_engine(priv)->sclass = nv17_fifo_sclass; +- priv->base.pause = nv04_fifo_pause; +- priv->base.start = nv04_fifo_start; +- priv->ramfc_desc = nv17_ramfc; +- return 0; +-} +- +-static int +-nv17_fifo_init(struct nouveau_object *object) +-{ +- struct nv04_fifo_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fifo_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, NV04_PFIFO_DELAY_0, 0x000000ff); +- nv_wr32(priv, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); +- +- nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | +- ((priv->ramht->bits - 9) << 16) | +- (priv->ramht->base.addr >> 8)); +- nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); +- nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); +- +- nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); +- nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); +- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); +- nv_wr32(priv, NV03_PFIFO_CACHES, 1); +- return 0; +-} +- +-struct nouveau_oclass * +-nv17_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0x17), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv17_fifo_ctor, +- .dtor = nv04_fifo_dtor, +- .init = nv17_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c +deleted file mode 100644 +index 9f49c3a2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c ++++ /dev/null +@@ -1,361 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-#include "nv04.h" +- +-static struct ramfc_desc +-nv40_ramfc[] = { +- { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, +- { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, +- { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, +- { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, +- { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, +- { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE }, +- { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, +- { 2, 28, 0x18, 28, 0x002058 }, +- { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE }, +- { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 }, +- { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, +- { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, +- { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, +- { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, +- { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, +- { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE }, +- { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE }, +- { 32, 0, 0x40, 0, 0x0032e4 }, +- { 32, 0, 0x44, 0, 0x0032e8 }, +- { 32, 0, 0x4c, 0, 0x002088 }, +- { 32, 0, 0x50, 0, 0x003300 }, +- { 32, 0, 0x54, 0, 0x00330c }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static int +-nv40_fifo_object_attach(struct nouveau_object *parent, +- struct nouveau_object *object, u32 handle) +-{ +- struct nv04_fifo_priv *priv = (void *)parent->engine; +- struct nv04_fifo_chan *chan = (void *)parent; +- u32 context, chid = chan->base.chid; +- int ret; +- +- if (nv_iclass(object, NV_GPUOBJ_CLASS)) +- context = nv_gpuobj(object)->addr >> 4; +- else +- context = 0x00000004; /* just non-zero */ +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_DMAOBJ: +- case NVDEV_ENGINE_SW: +- context |= 0x00000000; +- break; +- case NVDEV_ENGINE_GR: +- context |= 0x00100000; +- break; +- case NVDEV_ENGINE_MPEG: +- context |= 0x00200000; +- break; +- default: +- return -EINVAL; +- } +- +- context |= chid << 23; +- +- mutex_lock(&nv_subdev(priv)->mutex); +- ret = nouveau_ramht_insert(priv->ramht, chid, handle, context); +- mutex_unlock(&nv_subdev(priv)->mutex); +- return ret; +-} +- +-static int +-nv40_fifo_context_attach(struct nouveau_object *parent, +- struct nouveau_object *engctx) +-{ +- struct nv04_fifo_priv *priv = (void *)parent->engine; +- struct nv04_fifo_chan *chan = (void *)parent; +- unsigned long flags; +- u32 reg, ctx; +- +- switch (nv_engidx(engctx->engine)) { +- case NVDEV_ENGINE_SW: +- return 0; +- case NVDEV_ENGINE_GR: +- reg = 0x32e0; +- ctx = 0x38; +- break; +- case NVDEV_ENGINE_MPEG: +- reg = 0x330c; +- ctx = 0x54; +- break; +- default: +- return -EINVAL; +- } +- +- spin_lock_irqsave(&priv->base.lock, flags); +- nv_engctx(engctx)->addr = nv_gpuobj(engctx)->addr >> 4; +- nv_mask(priv, 0x002500, 0x00000001, 0x00000000); +- +- if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) +- nv_wr32(priv, reg, nv_engctx(engctx)->addr); +- nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); +- +- nv_mask(priv, 0x002500, 0x00000001, 0x00000001); +- spin_unlock_irqrestore(&priv->base.lock, flags); +- return 0; +-} +- +-static int +-nv40_fifo_context_detach(struct nouveau_object *parent, bool suspend, +- struct nouveau_object *engctx) +-{ +- struct nv04_fifo_priv *priv = (void *)parent->engine; +- struct nv04_fifo_chan *chan = (void *)parent; +- unsigned long flags; +- u32 reg, ctx; +- +- switch (nv_engidx(engctx->engine)) { +- case NVDEV_ENGINE_SW: +- return 0; +- case NVDEV_ENGINE_GR: +- reg = 0x32e0; +- ctx = 0x38; +- break; +- case NVDEV_ENGINE_MPEG: +- reg = 0x330c; +- ctx = 0x54; +- break; +- default: +- return -EINVAL; +- } +- +- spin_lock_irqsave(&priv->base.lock, flags); +- nv_mask(priv, 0x002500, 0x00000001, 0x00000000); +- +- if ((nv_rd32(priv, 0x003204) & priv->base.max) == chan->base.chid) +- nv_wr32(priv, reg, 0x00000000); +- nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000); +- +- nv_mask(priv, 0x002500, 0x00000001, 0x00000001); +- spin_unlock_irqrestore(&priv->base.lock, flags); +- return 0; +-} +- +-static int +-nv40_fifo_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv03_channel_dma_v0 v0; +- } *args = data; +- struct nv04_fifo_priv *priv = (void *)engine; +- struct nv04_fifo_chan *chan; +- int ret; +- +- nv_ioctl(parent, "create channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " +- "offset %016llx\n", args->v0.version, +- args->v0.pushbuf, args->v0.offset); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, +- 0x1000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_MPEG), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->context_attach = nv40_fifo_context_attach; +- nv_parent(chan)->context_detach = nv40_fifo_context_detach; +- nv_parent(chan)->object_attach = nv40_fifo_object_attach; +- nv_parent(chan)->object_detach = nv04_fifo_object_detach; +- chan->ramfc = chan->base.chid * 128; +- +- nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->v0.offset); +- nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); +- nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | +- NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | +- NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | +-#ifdef __BIG_ENDIAN +- NV_PFIFO_CACHE1_BIG_ENDIAN | +-#endif +- NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); +- nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv40_fifo_ofuncs = { +- .ctor = nv40_fifo_chan_ctor, +- .dtor = nv04_fifo_chan_dtor, +- .init = nv04_fifo_chan_init, +- .fini = nv04_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nv40_fifo_sclass[] = { +- { NV40_CHANNEL_DMA, &nv40_fifo_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - basically just the instmem reserved for the channel +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv40_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fifo_context_ctor, +- .dtor = _nouveau_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static int +-nv40_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_instmem_priv *imem = nv04_instmem(parent); +- struct nv04_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 0, 31, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nouveau_ramht_ref(imem->ramht, &priv->ramht); +- nouveau_gpuobj_ref(imem->ramro, &priv->ramro); +- nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nv04_fifo_intr; +- nv_engine(priv)->cclass = &nv40_fifo_cclass; +- nv_engine(priv)->sclass = nv40_fifo_sclass; +- priv->base.pause = nv04_fifo_pause; +- priv->base.start = nv04_fifo_start; +- priv->ramfc_desc = nv40_ramfc; +- return 0; +-} +- +-static int +-nv40_fifo_init(struct nouveau_object *object) +-{ +- struct nv04_fifo_priv *priv = (void *)object; +- struct nouveau_fb *pfb = nouveau_fb(object); +- int ret; +- +- ret = nouveau_fifo_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x002040, 0x000000ff); +- nv_wr32(priv, 0x002044, 0x2101ffff); +- nv_wr32(priv, 0x002058, 0x00000001); +- +- nv_wr32(priv, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | +- ((priv->ramht->bits - 9) << 16) | +- (priv->ramht->base.addr >> 8)); +- nv_wr32(priv, NV03_PFIFO_RAMRO, priv->ramro->addr >> 8); +- +- switch (nv_device(priv)->chipset) { +- case 0x47: +- case 0x49: +- case 0x4b: +- nv_wr32(priv, 0x002230, 0x00000001); +- case 0x40: +- case 0x41: +- case 0x42: +- case 0x43: +- case 0x45: +- case 0x48: +- nv_wr32(priv, 0x002220, 0x00030002); +- break; +- default: +- nv_wr32(priv, 0x002230, 0x00000000); +- nv_wr32(priv, 0x002220, ((pfb->ram->size - 512 * 1024 + +- priv->ramfc->addr) >> 16) | +- 0x00030000); +- break; +- } +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH1, priv->base.max); +- +- nv_wr32(priv, NV03_PFIFO_INTR_0, 0xffffffff); +- nv_wr32(priv, NV03_PFIFO_INTR_EN_0, 0xffffffff); +- +- nv_wr32(priv, NV03_PFIFO_CACHE1_PUSH0, 1); +- nv_wr32(priv, NV04_PFIFO_CACHE1_PULL0, 1); +- nv_wr32(priv, NV03_PFIFO_CACHES, 1); +- return 0; +-} +- +-struct nouveau_oclass * +-nv40_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_fifo_ctor, +- .dtor = nv04_fifo_dtor, +- .init = nv40_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c +deleted file mode 100644 +index 5d1e86bc..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c ++++ /dev/null +@@ -1,541 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +- +-#include "nv04.h" +-#include "nv50.h" +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static void +-nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv) +-{ +- struct nouveau_bar *bar = nouveau_bar(priv); +- struct nouveau_gpuobj *cur; +- int i, p; +- +- cur = priv->playlist[priv->cur_playlist]; +- priv->cur_playlist = !priv->cur_playlist; +- +- for (i = priv->base.min, p = 0; i < priv->base.max; i++) { +- if (nv_rd32(priv, 0x002600 + (i * 4)) & 0x80000000) +- nv_wo32(cur, p++ * 4, i); +- } +- +- bar->flush(bar); +- +- nv_wr32(priv, 0x0032f4, cur->addr >> 12); +- nv_wr32(priv, 0x0032ec, p); +- nv_wr32(priv, 0x002500, 0x00000101); +-} +- +-void +-nv50_fifo_playlist_update(struct nv50_fifo_priv *priv) +-{ +- mutex_lock(&nv_subdev(priv)->mutex); +- nv50_fifo_playlist_update_locked(priv); +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-static int +-nv50_fifo_context_attach(struct nouveau_object *parent, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_base *base = (void *)parent->parent; +- struct nouveau_gpuobj *ectx = (void *)object; +- u64 limit = ectx->addr + ectx->size - 1; +- u64 start = ectx->addr; +- u32 addr; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_GR : addr = 0x0000; break; +- case NVDEV_ENGINE_MPEG : addr = 0x0060; break; +- default: +- return -EINVAL; +- } +- +- nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; +- nv_wo32(base->eng, addr + 0x00, 0x00190000); +- nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); +- nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); +- nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | +- upper_32_bits(start)); +- nv_wo32(base->eng, addr + 0x10, 0x00000000); +- nv_wo32(base->eng, addr + 0x14, 0x00000000); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nv50_fifo_context_detach(struct nouveau_object *parent, bool suspend, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_priv *priv = (void *)parent->engine; +- struct nv50_fifo_base *base = (void *)parent->parent; +- struct nv50_fifo_chan *chan = (void *)parent; +- u32 addr, me; +- int ret = 0; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_GR : addr = 0x0000; break; +- case NVDEV_ENGINE_MPEG : addr = 0x0060; break; +- default: +- return -EINVAL; +- } +- +- /* HW bug workaround: +- * +- * PFIFO will hang forever if the connected engines don't report +- * that they've processed the context switch request. +- * +- * In order for the kickoff to work, we need to ensure all the +- * connected engines are in a state where they can answer. +- * +- * Newer chipsets don't seem to suffer from this issue, and well, +- * there's also a "ignore these engines" bitmask reg we can use +- * if we hit the issue there.. +- */ +- me = nv_mask(priv, 0x00b860, 0x00000001, 0x00000001); +- +- /* do the kickoff... */ +- nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); +- if (!nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff)) { +- nv_error(priv, "channel %d [%s] unload timeout\n", +- chan->base.chid, nouveau_client_name(chan)); +- if (suspend) +- ret = -EBUSY; +- } +- nv_wr32(priv, 0x00b860, me); +- +- if (ret == 0) { +- nv_wo32(base->eng, addr + 0x00, 0x00000000); +- nv_wo32(base->eng, addr + 0x04, 0x00000000); +- nv_wo32(base->eng, addr + 0x08, 0x00000000); +- nv_wo32(base->eng, addr + 0x0c, 0x00000000); +- nv_wo32(base->eng, addr + 0x10, 0x00000000); +- nv_wo32(base->eng, addr + 0x14, 0x00000000); +- bar->flush(bar); +- } +- +- return ret; +-} +- +-static int +-nv50_fifo_object_attach(struct nouveau_object *parent, +- struct nouveau_object *object, u32 handle) +-{ +- struct nv50_fifo_chan *chan = (void *)parent; +- u32 context; +- +- if (nv_iclass(object, NV_GPUOBJ_CLASS)) +- context = nv_gpuobj(object)->node->offset >> 4; +- else +- context = 0x00000004; /* just non-zero */ +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_DMAOBJ: +- case NVDEV_ENGINE_SW : context |= 0x00000000; break; +- case NVDEV_ENGINE_GR : context |= 0x00100000; break; +- case NVDEV_ENGINE_MPEG : context |= 0x00200000; break; +- default: +- return -EINVAL; +- } +- +- return nouveau_ramht_insert(chan->ramht, 0, handle, context); +-} +- +-void +-nv50_fifo_object_detach(struct nouveau_object *parent, int cookie) +-{ +- struct nv50_fifo_chan *chan = (void *)parent; +- nouveau_ramht_remove(chan->ramht, cookie); +-} +- +-static int +-nv50_fifo_chan_ctor_dma(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv03_channel_dma_v0 v0; +- } *args = data; +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_base *base = (void *)parent; +- struct nv50_fifo_chan *chan; +- int ret; +- +- nv_ioctl(parent, "create channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " +- "offset %016llx\n", args->v0.version, +- args->v0.pushbuf, args->v0.offset); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, +- 0x2000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_MPEG), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->context_attach = nv50_fifo_context_attach; +- nv_parent(chan)->context_detach = nv50_fifo_context_detach; +- nv_parent(chan)->object_attach = nv50_fifo_object_attach; +- nv_parent(chan)->object_detach = nv50_fifo_object_detach; +- +- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, +- &chan->ramht); +- if (ret) +- return ret; +- +- nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x3c, 0x003f6078); +- nv_wo32(base->ramfc, 0x44, 0x01003fff); +- nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); +- nv_wo32(base->ramfc, 0x4c, 0xffffffff); +- nv_wo32(base->ramfc, 0x60, 0x7fffffff); +- nv_wo32(base->ramfc, 0x78, 0x00000000); +- nv_wo32(base->ramfc, 0x7c, 0x30000001); +- nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | +- (4 << 24) /* SEARCH_FULL */ | +- (chan->ramht->base.node->offset >> 4)); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nv50_fifo_chan_ctor_ind(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_channel_gpfifo_v0 v0; +- } *args = data; +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_base *base = (void *)parent; +- struct nv50_fifo_chan *chan; +- u64 ioffset, ilength; +- int ret; +- +- nv_ioctl(parent, "create channel gpfifo size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " +- "ioffset %016llx ilength %08x\n", +- args->v0.version, args->v0.pushbuf, args->v0.ioffset, +- args->v0.ilength); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, +- 0x2000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_MPEG), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->context_attach = nv50_fifo_context_attach; +- nv_parent(chan)->context_detach = nv50_fifo_context_detach; +- nv_parent(chan)->object_attach = nv50_fifo_object_attach; +- nv_parent(chan)->object_detach = nv50_fifo_object_detach; +- +- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, +- &chan->ramht); +- if (ret) +- return ret; +- +- ioffset = args->v0.ioffset; +- ilength = order_base_2(args->v0.ilength / 8); +- +- nv_wo32(base->ramfc, 0x3c, 0x403f6078); +- nv_wo32(base->ramfc, 0x44, 0x01003fff); +- nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); +- nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); +- nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); +- nv_wo32(base->ramfc, 0x60, 0x7fffffff); +- nv_wo32(base->ramfc, 0x78, 0x00000000); +- nv_wo32(base->ramfc, 0x7c, 0x30000001); +- nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | +- (4 << 24) /* SEARCH_FULL */ | +- (chan->ramht->base.node->offset >> 4)); +- bar->flush(bar); +- return 0; +-} +- +-void +-nv50_fifo_chan_dtor(struct nouveau_object *object) +-{ +- struct nv50_fifo_chan *chan = (void *)object; +- nouveau_ramht_ref(NULL, &chan->ramht); +- nouveau_fifo_channel_destroy(&chan->base); +-} +- +-static int +-nv50_fifo_chan_init(struct nouveau_object *object) +-{ +- struct nv50_fifo_priv *priv = (void *)object->engine; +- struct nv50_fifo_base *base = (void *)object->parent; +- struct nv50_fifo_chan *chan = (void *)object; +- struct nouveau_gpuobj *ramfc = base->ramfc; +- u32 chid = chan->base.chid; +- int ret; +- +- ret = nouveau_fifo_channel_init(&chan->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 12); +- nv50_fifo_playlist_update(priv); +- return 0; +-} +- +-int +-nv50_fifo_chan_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_fifo_priv *priv = (void *)object->engine; +- struct nv50_fifo_chan *chan = (void *)object; +- u32 chid = chan->base.chid; +- +- /* remove channel from playlist, fifo will unload context */ +- nv_mask(priv, 0x002600 + (chid * 4), 0x80000000, 0x00000000); +- nv50_fifo_playlist_update(priv); +- nv_wr32(priv, 0x002600 + (chid * 4), 0x00000000); +- +- return nouveau_fifo_channel_fini(&chan->base, suspend); +-} +- +-static struct nouveau_ofuncs +-nv50_fifo_ofuncs_dma = { +- .ctor = nv50_fifo_chan_ctor_dma, +- .dtor = nv50_fifo_chan_dtor, +- .init = nv50_fifo_chan_init, +- .fini = nv50_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_ofuncs +-nv50_fifo_ofuncs_ind = { +- .ctor = nv50_fifo_chan_ctor_ind, +- .dtor = nv50_fifo_chan_dtor, +- .init = nv50_fifo_chan_init, +- .fini = nv50_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nv50_fifo_sclass[] = { +- { NV50_CHANNEL_DMA, &nv50_fifo_ofuncs_dma }, +- { NV50_CHANNEL_GPFIFO, &nv50_fifo_ofuncs_ind }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - basically just the instmem reserved for the channel +- ******************************************************************************/ +- +-static int +-nv50_fifo_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_fifo_base *base; +- int ret; +- +- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000, +- 0x1000, NVOBJ_FLAG_HEAP, &base); +- *pobject = nv_object(base); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, +- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0, +- NVOBJ_FLAG_ZERO_ALLOC, &base->eng); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0, +- &base->pgd); +- if (ret) +- return ret; +- +- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); +- if (ret) +- return ret; +- +- return 0; +-} +- +-void +-nv50_fifo_context_dtor(struct nouveau_object *object) +-{ +- struct nv50_fifo_base *base = (void *)object; +- nouveau_vm_ref(NULL, &base->vm, base->pgd); +- nouveau_gpuobj_ref(NULL, &base->pgd); +- nouveau_gpuobj_ref(NULL, &base->eng); +- nouveau_gpuobj_ref(NULL, &base->ramfc); +- nouveau_gpuobj_ref(NULL, &base->cache); +- nouveau_fifo_context_destroy(&base->base); +-} +- +-static struct nouveau_oclass +-nv50_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fifo_context_ctor, +- .dtor = nv50_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static int +-nv50_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, +- &priv->playlist[0]); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, +- &priv->playlist[1]); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nv04_fifo_intr; +- nv_engine(priv)->cclass = &nv50_fifo_cclass; +- nv_engine(priv)->sclass = nv50_fifo_sclass; +- priv->base.pause = nv04_fifo_pause; +- priv->base.start = nv04_fifo_start; +- return 0; +-} +- +-void +-nv50_fifo_dtor(struct nouveau_object *object) +-{ +- struct nv50_fifo_priv *priv = (void *)object; +- +- nouveau_gpuobj_ref(NULL, &priv->playlist[1]); +- nouveau_gpuobj_ref(NULL, &priv->playlist[0]); +- +- nouveau_fifo_destroy(&priv->base); +-} +- +-int +-nv50_fifo_init(struct nouveau_object *object) +-{ +- struct nv50_fifo_priv *priv = (void *)object; +- int ret, i; +- +- ret = nouveau_fifo_init(&priv->base); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x000200, 0x00000100, 0x00000000); +- nv_mask(priv, 0x000200, 0x00000100, 0x00000100); +- nv_wr32(priv, 0x00250c, 0x6f3cfc34); +- nv_wr32(priv, 0x002044, 0x01003fff); +- +- nv_wr32(priv, 0x002100, 0xffffffff); +- nv_wr32(priv, 0x002140, 0xbfffffff); +- +- for (i = 0; i < 128; i++) +- nv_wr32(priv, 0x002600 + (i * 4), 0x00000000); +- nv50_fifo_playlist_update_locked(priv); +- +- nv_wr32(priv, 0x003200, 0x00000001); +- nv_wr32(priv, 0x003250, 0x00000001); +- nv_wr32(priv, 0x002500, 0x00000001); +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fifo_ctor, +- .dtor = nv50_fifo_dtor, +- .init = nv50_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h +deleted file mode 100644 +index 3a9ceb31..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-#ifndef __NV50_FIFO_H__ +-#define __NV50_FIFO_H__ +- +-struct nv50_fifo_priv { +- struct nouveau_fifo base; +- struct nouveau_gpuobj *playlist[2]; +- int cur_playlist; +-}; +- +-struct nv50_fifo_base { +- struct nouveau_fifo_base base; +- struct nouveau_gpuobj *ramfc; +- struct nouveau_gpuobj *cache; +- struct nouveau_gpuobj *eng; +- struct nouveau_gpuobj *pgd; +- struct nouveau_vm *vm; +-}; +- +-struct nv50_fifo_chan { +- struct nouveau_fifo_chan base; +- u32 subc[8]; +- struct nouveau_ramht *ramht; +-}; +- +-void nv50_fifo_playlist_update(struct nv50_fifo_priv *); +- +-void nv50_fifo_object_detach(struct nouveau_object *, int); +-void nv50_fifo_chan_dtor(struct nouveau_object *); +-int nv50_fifo_chan_fini(struct nouveau_object *, bool); +- +-void nv50_fifo_context_dtor(struct nouveau_object *); +- +-void nv50_fifo_dtor(struct nouveau_object *); +-int nv50_fifo_init(struct nouveau_object *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c +deleted file mode 100644 +index 1f42996b..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c ++++ /dev/null +@@ -1,481 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +- +-#include "nv04.h" +-#include "nv50.h" +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static int +-nv84_fifo_context_attach(struct nouveau_object *parent, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_base *base = (void *)parent->parent; +- struct nouveau_gpuobj *ectx = (void *)object; +- u64 limit = ectx->addr + ectx->size - 1; +- u64 start = ectx->addr; +- u32 addr; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_GR : addr = 0x0020; break; +- case NVDEV_ENGINE_VP : addr = 0x0040; break; +- case NVDEV_ENGINE_PPP : +- case NVDEV_ENGINE_MPEG : addr = 0x0060; break; +- case NVDEV_ENGINE_BSP : addr = 0x0080; break; +- case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break; +- case NVDEV_ENGINE_COPY0: addr = 0x00c0; break; +- default: +- return -EINVAL; +- } +- +- nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; +- nv_wo32(base->eng, addr + 0x00, 0x00190000); +- nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); +- nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); +- nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | +- upper_32_bits(start)); +- nv_wo32(base->eng, addr + 0x10, 0x00000000); +- nv_wo32(base->eng, addr + 0x14, 0x00000000); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_priv *priv = (void *)parent->engine; +- struct nv50_fifo_base *base = (void *)parent->parent; +- struct nv50_fifo_chan *chan = (void *)parent; +- u32 addr, save, engn; +- bool done; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break; +- case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break; +- case NVDEV_ENGINE_PPP : +- case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; +- case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break; +- case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break; +- case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break; +- default: +- return -EINVAL; +- } +- +- save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn); +- nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); +- done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff); +- nv_wr32(priv, 0x002520, save); +- if (!done) { +- nv_error(priv, "channel %d [%s] unload timeout\n", +- chan->base.chid, nouveau_client_name(chan)); +- if (suspend) +- return -EBUSY; +- } +- +- nv_wo32(base->eng, addr + 0x00, 0x00000000); +- nv_wo32(base->eng, addr + 0x04, 0x00000000); +- nv_wo32(base->eng, addr + 0x08, 0x00000000); +- nv_wo32(base->eng, addr + 0x0c, 0x00000000); +- nv_wo32(base->eng, addr + 0x10, 0x00000000); +- nv_wo32(base->eng, addr + 0x14, 0x00000000); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nv84_fifo_object_attach(struct nouveau_object *parent, +- struct nouveau_object *object, u32 handle) +-{ +- struct nv50_fifo_chan *chan = (void *)parent; +- u32 context; +- +- if (nv_iclass(object, NV_GPUOBJ_CLASS)) +- context = nv_gpuobj(object)->node->offset >> 4; +- else +- context = 0x00000004; /* just non-zero */ +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_DMAOBJ: +- case NVDEV_ENGINE_SW : context |= 0x00000000; break; +- case NVDEV_ENGINE_GR : context |= 0x00100000; break; +- case NVDEV_ENGINE_MPEG : +- case NVDEV_ENGINE_PPP : context |= 0x00200000; break; +- case NVDEV_ENGINE_ME : +- case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break; +- case NVDEV_ENGINE_VP : context |= 0x00400000; break; +- case NVDEV_ENGINE_CRYPT : +- case NVDEV_ENGINE_VIC : context |= 0x00500000; break; +- case NVDEV_ENGINE_BSP : context |= 0x00600000; break; +- default: +- return -EINVAL; +- } +- +- return nouveau_ramht_insert(chan->ramht, 0, handle, context); +-} +- +-static int +-nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv03_channel_dma_v0 v0; +- } *args = data; +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_base *base = (void *)parent; +- struct nv50_fifo_chan *chan; +- int ret; +- +- nv_ioctl(parent, "create channel dma size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel dma vers %d pushbuf %08x " +- "offset %016llx\n", args->v0.version, +- args->v0.pushbuf, args->v0.offset); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, +- 0x2000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_MPEG) | +- (1ULL << NVDEV_ENGINE_ME) | +- (1ULL << NVDEV_ENGINE_VP) | +- (1ULL << NVDEV_ENGINE_CRYPT) | +- (1ULL << NVDEV_ENGINE_BSP) | +- (1ULL << NVDEV_ENGINE_PPP) | +- (1ULL << NVDEV_ENGINE_COPY0) | +- (1ULL << NVDEV_ENGINE_VIC), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, +- &chan->ramht); +- if (ret) +- return ret; +- +- nv_parent(chan)->context_attach = nv84_fifo_context_attach; +- nv_parent(chan)->context_detach = nv84_fifo_context_detach; +- nv_parent(chan)->object_attach = nv84_fifo_object_attach; +- nv_parent(chan)->object_detach = nv50_fifo_object_detach; +- +- nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset)); +- nv_wo32(base->ramfc, 0x3c, 0x003f6078); +- nv_wo32(base->ramfc, 0x44, 0x01003fff); +- nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); +- nv_wo32(base->ramfc, 0x4c, 0xffffffff); +- nv_wo32(base->ramfc, 0x60, 0x7fffffff); +- nv_wo32(base->ramfc, 0x78, 0x00000000); +- nv_wo32(base->ramfc, 0x7c, 0x30000001); +- nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | +- (4 << 24) /* SEARCH_FULL */ | +- (chan->ramht->base.node->offset >> 4)); +- nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10); +- nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_channel_gpfifo_v0 v0; +- } *args = data; +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_fifo_base *base = (void *)parent; +- struct nv50_fifo_chan *chan; +- u64 ioffset, ilength; +- int ret; +- +- nv_ioctl(parent, "create channel gpfifo size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " +- "ioffset %016llx ilength %08x\n", +- args->v0.version, args->v0.pushbuf, args->v0.ioffset, +- args->v0.ilength); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000, +- 0x2000, args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_DMAOBJ) | +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_MPEG) | +- (1ULL << NVDEV_ENGINE_ME) | +- (1ULL << NVDEV_ENGINE_VP) | +- (1ULL << NVDEV_ENGINE_CRYPT) | +- (1ULL << NVDEV_ENGINE_BSP) | +- (1ULL << NVDEV_ENGINE_PPP) | +- (1ULL << NVDEV_ENGINE_COPY0) | +- (1ULL << NVDEV_ENGINE_VIC), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16, +- &chan->ramht); +- if (ret) +- return ret; +- +- nv_parent(chan)->context_attach = nv84_fifo_context_attach; +- nv_parent(chan)->context_detach = nv84_fifo_context_detach; +- nv_parent(chan)->object_attach = nv84_fifo_object_attach; +- nv_parent(chan)->object_detach = nv50_fifo_object_detach; +- +- ioffset = args->v0.ioffset; +- ilength = order_base_2(args->v0.ilength / 8); +- +- nv_wo32(base->ramfc, 0x3c, 0x403f6078); +- nv_wo32(base->ramfc, 0x44, 0x01003fff); +- nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); +- nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset)); +- nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); +- nv_wo32(base->ramfc, 0x60, 0x7fffffff); +- nv_wo32(base->ramfc, 0x78, 0x00000000); +- nv_wo32(base->ramfc, 0x7c, 0x30000001); +- nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | +- (4 << 24) /* SEARCH_FULL */ | +- (chan->ramht->base.node->offset >> 4)); +- nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10); +- nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nv84_fifo_chan_init(struct nouveau_object *object) +-{ +- struct nv50_fifo_priv *priv = (void *)object->engine; +- struct nv50_fifo_base *base = (void *)object->parent; +- struct nv50_fifo_chan *chan = (void *)object; +- struct nouveau_gpuobj *ramfc = base->ramfc; +- u32 chid = chan->base.chid; +- int ret; +- +- ret = nouveau_fifo_channel_init(&chan->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8); +- nv50_fifo_playlist_update(priv); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv84_fifo_ofuncs_dma = { +- .ctor = nv84_fifo_chan_ctor_dma, +- .dtor = nv50_fifo_chan_dtor, +- .init = nv84_fifo_chan_init, +- .fini = nv50_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_ofuncs +-nv84_fifo_ofuncs_ind = { +- .ctor = nv84_fifo_chan_ctor_ind, +- .dtor = nv50_fifo_chan_dtor, +- .init = nv84_fifo_chan_init, +- .fini = nv50_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nv84_fifo_sclass[] = { +- { G82_CHANNEL_DMA, &nv84_fifo_ofuncs_dma }, +- { G82_CHANNEL_GPFIFO, &nv84_fifo_ofuncs_ind }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - basically just the instmem reserved for the channel +- ******************************************************************************/ +- +-static int +-nv84_fifo_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_fifo_base *base; +- int ret; +- +- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000, +- 0x1000, NVOBJ_FLAG_HEAP, &base); +- *pobject = nv_object(base); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0, +- NVOBJ_FLAG_ZERO_ALLOC, &base->eng); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, +- 0, &base->pgd); +- if (ret) +- return ret; +- +- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000, +- 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100, +- 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static struct nouveau_oclass +-nv84_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_fifo_context_ctor, +- .dtor = nv50_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static void +-nv84_fifo_uevent_init(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); +- nv_mask(fifo, 0x002140, 0x40000000, 0x40000000); +-} +- +-static void +-nv84_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); +- nv_mask(fifo, 0x002140, 0x40000000, 0x00000000); +-} +- +-static const struct nvkm_event_func +-nv84_fifo_uevent_func = { +- .ctor = nouveau_fifo_uevent_ctor, +- .init = nv84_fifo_uevent_init, +- .fini = nv84_fifo_uevent_fini, +-}; +- +-static int +-nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, +- &priv->playlist[0]); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0, +- &priv->playlist[1]); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nv84_fifo_uevent_func, 1, 1, &priv->base.uevent); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nv04_fifo_intr; +- nv_engine(priv)->cclass = &nv84_fifo_cclass; +- nv_engine(priv)->sclass = nv84_fifo_sclass; +- priv->base.pause = nv04_fifo_pause; +- priv->base.start = nv04_fifo_start; +- return 0; +-} +- +-struct nouveau_oclass * +-nv84_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_fifo_ctor, +- .dtor = nv50_fifo_dtor, +- .init = nv50_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c +deleted file mode 100644 +index 074d434c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c ++++ /dev/null +@@ -1,975 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-struct nvc0_fifo_priv { +- struct nouveau_fifo base; +- +- struct work_struct fault; +- u64 mask; +- +- struct { +- struct nouveau_gpuobj *mem[2]; +- int active; +- wait_queue_head_t wait; +- } runlist; +- +- struct { +- struct nouveau_gpuobj *mem; +- struct nouveau_vma bar; +- } user; +- int spoon_nr; +-}; +- +-struct nvc0_fifo_base { +- struct nouveau_fifo_base base; +- struct nouveau_gpuobj *pgd; +- struct nouveau_vm *vm; +-}; +- +-struct nvc0_fifo_chan { +- struct nouveau_fifo_chan base; +- enum { +- STOPPED, +- RUNNING, +- KILLED +- } state; +-}; +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static void +-nvc0_fifo_runlist_update(struct nvc0_fifo_priv *priv) +-{ +- struct nouveau_bar *bar = nouveau_bar(priv); +- struct nouveau_gpuobj *cur; +- int i, p; +- +- mutex_lock(&nv_subdev(priv)->mutex); +- cur = priv->runlist.mem[priv->runlist.active]; +- priv->runlist.active = !priv->runlist.active; +- +- for (i = 0, p = 0; i < 128; i++) { +- struct nvc0_fifo_chan *chan = (void *)priv->base.channel[i]; +- if (chan && chan->state == RUNNING) { +- nv_wo32(cur, p + 0, i); +- nv_wo32(cur, p + 4, 0x00000004); +- p += 8; +- } +- } +- bar->flush(bar); +- +- nv_wr32(priv, 0x002270, cur->addr >> 12); +- nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3)); +- +- if (wait_event_timeout(priv->runlist.wait, +- !(nv_rd32(priv, 0x00227c) & 0x00100000), +- msecs_to_jiffies(2000)) == 0) +- nv_error(priv, "runlist update timeout\n"); +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-static int +-nvc0_fifo_context_attach(struct nouveau_object *parent, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nvc0_fifo_base *base = (void *)parent->parent; +- struct nouveau_engctx *ectx = (void *)object; +- u32 addr; +- int ret; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_GR : addr = 0x0210; break; +- case NVDEV_ENGINE_COPY0: addr = 0x0230; break; +- case NVDEV_ENGINE_COPY1: addr = 0x0240; break; +- case NVDEV_ENGINE_BSP : addr = 0x0270; break; +- case NVDEV_ENGINE_VP : addr = 0x0250; break; +- case NVDEV_ENGINE_PPP : addr = 0x0260; break; +- default: +- return -EINVAL; +- } +- +- if (!ectx->vma.node) { +- ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, +- NV_MEM_ACCESS_RW, &ectx->vma); +- if (ret) +- return ret; +- +- nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; +- } +- +- nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); +- nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nvc0_fifo_priv *priv = (void *)parent->engine; +- struct nvc0_fifo_base *base = (void *)parent->parent; +- struct nvc0_fifo_chan *chan = (void *)parent; +- u32 addr; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_GR : addr = 0x0210; break; +- case NVDEV_ENGINE_COPY0: addr = 0x0230; break; +- case NVDEV_ENGINE_COPY1: addr = 0x0240; break; +- case NVDEV_ENGINE_BSP : addr = 0x0270; break; +- case NVDEV_ENGINE_VP : addr = 0x0250; break; +- case NVDEV_ENGINE_PPP : addr = 0x0260; break; +- default: +- return -EINVAL; +- } +- +- nv_wr32(priv, 0x002634, chan->base.chid); +- if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { +- nv_error(priv, "channel %d [%s] kick timeout\n", +- chan->base.chid, nouveau_client_name(chan)); +- if (suspend) +- return -EBUSY; +- } +- +- nv_wo32(base, addr + 0x00, 0x00000000); +- nv_wo32(base, addr + 0x04, 0x00000000); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nvc0_fifo_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nv50_channel_gpfifo_v0 v0; +- } *args = data; +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nvc0_fifo_priv *priv = (void *)engine; +- struct nvc0_fifo_base *base = (void *)parent; +- struct nvc0_fifo_chan *chan; +- u64 usermem, ioffset, ilength; +- int ret, i; +- +- nv_ioctl(parent, "create channel gpfifo size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " +- "ioffset %016llx ilength %08x\n", +- args->v0.version, args->v0.pushbuf, args->v0.ioffset, +- args->v0.ilength); +- } else +- return ret; +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, +- priv->user.bar.offset, 0x1000, +- args->v0.pushbuf, +- (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_GR) | +- (1ULL << NVDEV_ENGINE_COPY0) | +- (1ULL << NVDEV_ENGINE_COPY1) | +- (1ULL << NVDEV_ENGINE_BSP) | +- (1ULL << NVDEV_ENGINE_VP) | +- (1ULL << NVDEV_ENGINE_PPP), &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->context_attach = nvc0_fifo_context_attach; +- nv_parent(chan)->context_detach = nvc0_fifo_context_detach; +- +- usermem = chan->base.chid * 0x1000; +- ioffset = args->v0.ioffset; +- ilength = order_base_2(args->v0.ilength / 8); +- +- for (i = 0; i < 0x1000; i += 4) +- nv_wo32(priv->user.mem, usermem + i, 0x00000000); +- +- nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); +- nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); +- nv_wo32(base, 0x10, 0x0000face); +- nv_wo32(base, 0x30, 0xfffff902); +- nv_wo32(base, 0x48, lower_32_bits(ioffset)); +- nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); +- nv_wo32(base, 0x54, 0x00000002); +- nv_wo32(base, 0x84, 0x20400000); +- nv_wo32(base, 0x94, 0x30000001); +- nv_wo32(base, 0x9c, 0x00000100); +- nv_wo32(base, 0xa4, 0x1f1f1f1f); +- nv_wo32(base, 0xa8, 0x1f1f1f1f); +- nv_wo32(base, 0xac, 0x0000001f); +- nv_wo32(base, 0xb8, 0xf8000000); +- nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ +- nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ +- bar->flush(bar); +- return 0; +-} +- +-static int +-nvc0_fifo_chan_init(struct nouveau_object *object) +-{ +- struct nouveau_gpuobj *base = nv_gpuobj(object->parent); +- struct nvc0_fifo_priv *priv = (void *)object->engine; +- struct nvc0_fifo_chan *chan = (void *)object; +- u32 chid = chan->base.chid; +- int ret; +- +- ret = nouveau_fifo_channel_init(&chan->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); +- +- if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { +- nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001); +- nvc0_fifo_runlist_update(priv); +- } +- +- return 0; +-} +- +-static void nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv); +- +-static int +-nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvc0_fifo_priv *priv = (void *)object->engine; +- struct nvc0_fifo_chan *chan = (void *)object; +- u32 chid = chan->base.chid; +- +- if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { +- nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000); +- nvc0_fifo_runlist_update(priv); +- } +- +- nvc0_fifo_intr_engine(priv); +- +- nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000); +- return nouveau_fifo_channel_fini(&chan->base, suspend); +-} +- +-static struct nouveau_ofuncs +-nvc0_fifo_ofuncs = { +- .ctor = nvc0_fifo_chan_ctor, +- .dtor = _nouveau_fifo_channel_dtor, +- .init = nvc0_fifo_chan_init, +- .fini = nvc0_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nvc0_fifo_sclass[] = { +- { FERMI_CHANNEL_GPFIFO, &nvc0_fifo_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - instmem heap and vm setup +- ******************************************************************************/ +- +-static int +-nvc0_fifo_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_fifo_base *base; +- int ret; +- +- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, +- 0x1000, NVOBJ_FLAG_ZERO_ALLOC | +- NVOBJ_FLAG_HEAP, &base); +- *pobject = nv_object(base); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, +- &base->pgd); +- if (ret) +- return ret; +- +- nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); +- nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); +- nv_wo32(base, 0x0208, 0xffffffff); +- nv_wo32(base, 0x020c, 0x000000ff); +- +- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static void +-nvc0_fifo_context_dtor(struct nouveau_object *object) +-{ +- struct nvc0_fifo_base *base = (void *)object; +- nouveau_vm_ref(NULL, &base->vm, base->pgd); +- nouveau_gpuobj_ref(NULL, &base->pgd); +- nouveau_fifo_context_destroy(&base->base); +-} +- +-static struct nouveau_oclass +-nvc0_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_fifo_context_ctor, +- .dtor = nvc0_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static inline int +-nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) +-{ +- switch (engn) { +- case NVDEV_ENGINE_GR : engn = 0; break; +- case NVDEV_ENGINE_BSP : engn = 1; break; +- case NVDEV_ENGINE_PPP : engn = 2; break; +- case NVDEV_ENGINE_VP : engn = 3; break; +- case NVDEV_ENGINE_COPY0: engn = 4; break; +- case NVDEV_ENGINE_COPY1: engn = 5; break; +- default: +- return -1; +- } +- +- return engn; +-} +- +-static inline struct nouveau_engine * +-nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) +-{ +- switch (engn) { +- case 0: engn = NVDEV_ENGINE_GR; break; +- case 1: engn = NVDEV_ENGINE_BSP; break; +- case 2: engn = NVDEV_ENGINE_PPP; break; +- case 3: engn = NVDEV_ENGINE_VP; break; +- case 4: engn = NVDEV_ENGINE_COPY0; break; +- case 5: engn = NVDEV_ENGINE_COPY1; break; +- default: +- return NULL; +- } +- +- return nouveau_engine(priv, engn); +-} +- +-static void +-nvc0_fifo_recover_work(struct work_struct *work) +-{ +- struct nvc0_fifo_priv *priv = container_of(work, typeof(*priv), fault); +- struct nouveau_object *engine; +- unsigned long flags; +- u32 engn, engm = 0; +- u64 mask, todo; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- mask = priv->mask; +- priv->mask = 0ULL; +- spin_unlock_irqrestore(&priv->base.lock, flags); +- +- for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) +- engm |= 1 << nvc0_fifo_engidx(priv, engn); +- nv_mask(priv, 0x002630, engm, engm); +- +- for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { +- if ((engine = (void *)nouveau_engine(priv, engn))) { +- nv_ofuncs(engine)->fini(engine, false); +- WARN_ON(nv_ofuncs(engine)->init(engine)); +- } +- } +- +- nvc0_fifo_runlist_update(priv); +- nv_wr32(priv, 0x00262c, engm); +- nv_mask(priv, 0x002630, engm, 0x00000000); +-} +- +-static void +-nvc0_fifo_recover(struct nvc0_fifo_priv *priv, struct nouveau_engine *engine, +- struct nvc0_fifo_chan *chan) +-{ +- struct nouveau_object *engobj = nv_object(engine); +- u32 chid = chan->base.chid; +- unsigned long flags; +- +- nv_error(priv, "%s engine fault on channel %d, recovering...\n", +- nv_subdev(engine)->name, chid); +- +- nv_mask(priv, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); +- chan->state = KILLED; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- priv->mask |= 1ULL << nv_engidx(engobj); +- spin_unlock_irqrestore(&priv->base.lock, flags); +- schedule_work(&priv->fault); +-} +- +-static int +-nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +-{ +- struct nvc0_fifo_chan *chan = NULL; +- struct nouveau_handle *bind; +- unsigned long flags; +- int ret = -EINVAL; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- if (likely(chid >= priv->base.min && chid <= priv->base.max)) +- chan = (void *)priv->base.channel[chid]; +- if (unlikely(!chan)) +- goto out; +- +- bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); +- if (likely(bind)) { +- if (!mthd || !nv_call(bind->object, mthd, data)) +- ret = 0; +- nouveau_namedb_put(bind); +- } +- +-out: +- spin_unlock_irqrestore(&priv->base.lock, flags); +- return ret; +-} +- +-static const struct nouveau_enum +-nvc0_fifo_sched_reason[] = { +- { 0x0a, "CTXSW_TIMEOUT" }, +- {} +-}; +- +-static void +-nvc0_fifo_intr_sched_ctxsw(struct nvc0_fifo_priv *priv) +-{ +- struct nouveau_engine *engine; +- struct nvc0_fifo_chan *chan; +- u32 engn; +- +- for (engn = 0; engn < 6; engn++) { +- u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); +- u32 busy = (stat & 0x80000000); +- u32 save = (stat & 0x00100000); /* maybe? */ +- u32 unk0 = (stat & 0x00040000); +- u32 unk1 = (stat & 0x00001000); +- u32 chid = (stat & 0x0000007f); +- (void)save; +- +- if (busy && unk0 && unk1) { +- if (!(chan = (void *)priv->base.channel[chid])) +- continue; +- if (!(engine = nvc0_fifo_engine(priv, engn))) +- continue; +- nvc0_fifo_recover(priv, engine, chan); +- } +- } +-} +- +-static void +-nvc0_fifo_intr_sched(struct nvc0_fifo_priv *priv) +-{ +- u32 intr = nv_rd32(priv, 0x00254c); +- u32 code = intr & 0x000000ff; +- const struct nouveau_enum *en; +- char enunk[6] = ""; +- +- en = nouveau_enum_find(nvc0_fifo_sched_reason, code); +- if (!en) +- snprintf(enunk, sizeof(enunk), "UNK%02x", code); +- +- nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); +- +- switch (code) { +- case 0x0a: +- nvc0_fifo_intr_sched_ctxsw(priv); +- break; +- default: +- break; +- } +-} +- +-static const struct nouveau_enum +-nvc0_fifo_fault_engine[] = { +- { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, +- { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, +- { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, +- { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, +- { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, +- { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP }, +- { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, +- { 0x13, "PCOUNTER" }, +- { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, +- { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 }, +- { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 }, +- { 0x17, "PDAEMON" }, +- {} +-}; +- +-static const struct nouveau_enum +-nvc0_fifo_fault_reason[] = { +- { 0x00, "PT_NOT_PRESENT" }, +- { 0x01, "PT_TOO_SHORT" }, +- { 0x02, "PAGE_NOT_PRESENT" }, +- { 0x03, "VM_LIMIT_EXCEEDED" }, +- { 0x04, "NO_CHANNEL" }, +- { 0x05, "PAGE_SYSTEM_ONLY" }, +- { 0x06, "PAGE_READ_ONLY" }, +- { 0x0a, "COMPRESSED_SYSRAM" }, +- { 0x0c, "INVALID_STORAGE_TYPE" }, +- {} +-}; +- +-static const struct nouveau_enum +-nvc0_fifo_fault_hubclient[] = { +- { 0x01, "PCOPY0" }, +- { 0x02, "PCOPY1" }, +- { 0x04, "DISPATCH" }, +- { 0x05, "CTXCTL" }, +- { 0x06, "PFIFO" }, +- { 0x07, "BAR_READ" }, +- { 0x08, "BAR_WRITE" }, +- { 0x0b, "PVP" }, +- { 0x0c, "PPPP" }, +- { 0x0d, "PBSP" }, +- { 0x11, "PCOUNTER" }, +- { 0x12, "PDAEMON" }, +- { 0x14, "CCACHE" }, +- { 0x15, "CCACHE_POST" }, +- {} +-}; +- +-static const struct nouveau_enum +-nvc0_fifo_fault_gpcclient[] = { +- { 0x01, "TEX" }, +- { 0x0c, "ESETUP" }, +- { 0x0e, "CTXCTL" }, +- { 0x0f, "PROP" }, +- {} +-}; +- +-static void +-nvc0_fifo_intr_fault(struct nvc0_fifo_priv *priv, int unit) +-{ +- u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); +- u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); +- u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); +- u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); +- u32 gpc = (stat & 0x1f000000) >> 24; +- u32 client = (stat & 0x00001f00) >> 8; +- u32 write = (stat & 0x00000080); +- u32 hub = (stat & 0x00000040); +- u32 reason = (stat & 0x0000000f); +- struct nouveau_object *engctx = NULL, *object; +- struct nouveau_engine *engine = NULL; +- const struct nouveau_enum *er, *eu, *ec; +- char erunk[6] = ""; +- char euunk[6] = ""; +- char ecunk[6] = ""; +- char gpcid[3] = ""; +- +- er = nouveau_enum_find(nvc0_fifo_fault_reason, reason); +- if (!er) +- snprintf(erunk, sizeof(erunk), "UNK%02X", reason); +- +- eu = nouveau_enum_find(nvc0_fifo_fault_engine, unit); +- if (eu) { +- switch (eu->data2) { +- case NVDEV_SUBDEV_BAR: +- nv_mask(priv, 0x001704, 0x00000000, 0x00000000); +- break; +- case NVDEV_SUBDEV_INSTMEM: +- nv_mask(priv, 0x001714, 0x00000000, 0x00000000); +- break; +- case NVDEV_ENGINE_IFB: +- nv_mask(priv, 0x001718, 0x00000000, 0x00000000); +- break; +- default: +- engine = nouveau_engine(priv, eu->data2); +- if (engine) +- engctx = nouveau_engctx_get(engine, inst); +- break; +- } +- } else { +- snprintf(euunk, sizeof(euunk), "UNK%02x", unit); +- } +- +- if (hub) { +- ec = nouveau_enum_find(nvc0_fifo_fault_hubclient, client); +- } else { +- ec = nouveau_enum_find(nvc0_fifo_fault_gpcclient, client); +- snprintf(gpcid, sizeof(gpcid), "%d", gpc); +- } +- +- if (!ec) +- snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); +- +- nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " +- "channel 0x%010llx [%s]\n", write ? "write" : "read", +- (u64)vahi << 32 | valo, er ? er->name : erunk, +- eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", +- ec ? ec->name : ecunk, (u64)inst << 12, +- nouveau_client_name(engctx)); +- +- object = engctx; +- while (object) { +- switch (nv_mclass(object)) { +- case FERMI_CHANNEL_GPFIFO: +- nvc0_fifo_recover(priv, engine, (void *)object); +- break; +- } +- object = object->parent; +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static const struct nouveau_bitfield +-nvc0_fifo_pbdma_intr[] = { +-/* { 0x00008000, "" } seen with null ib push */ +- { 0x00200000, "ILLEGAL_MTHD" }, +- { 0x00800000, "EMPTY_SUBC" }, +- {} +-}; +- +-static void +-nvc0_fifo_intr_pbdma(struct nvc0_fifo_priv *priv, int unit) +-{ +- u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); +- u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); +- u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); +- u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f; +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00003ffc); +- u32 show = stat; +- +- if (stat & 0x00800000) { +- if (!nvc0_fifo_swmthd(priv, chid, mthd, data)) +- show &= ~0x00800000; +- } +- +- if (show) { +- nv_error(priv, "PBDMA%d:", unit); +- nouveau_bitfield_print(nvc0_fifo_pbdma_intr, show); +- pr_cont("\n"); +- nv_error(priv, +- "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", +- unit, chid, +- nouveau_client_name_for_fifo_chid(&priv->base, chid), +- subc, mthd, data); +- } +- +- nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); +- nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); +-} +- +-static void +-nvc0_fifo_intr_runlist(struct nvc0_fifo_priv *priv) +-{ +- u32 intr = nv_rd32(priv, 0x002a00); +- +- if (intr & 0x10000000) { +- wake_up(&priv->runlist.wait); +- nv_wr32(priv, 0x002a00, 0x10000000); +- intr &= ~0x10000000; +- } +- +- if (intr) { +- nv_error(priv, "RUNLIST 0x%08x\n", intr); +- nv_wr32(priv, 0x002a00, intr); +- } +-} +- +-static void +-nvc0_fifo_intr_engine_unit(struct nvc0_fifo_priv *priv, int engn) +-{ +- u32 intr = nv_rd32(priv, 0x0025a8 + (engn * 0x04)); +- u32 inte = nv_rd32(priv, 0x002628); +- u32 unkn; +- +- nv_wr32(priv, 0x0025a8 + (engn * 0x04), intr); +- +- for (unkn = 0; unkn < 8; unkn++) { +- u32 ints = (intr >> (unkn * 0x04)) & inte; +- if (ints & 0x1) { +- nouveau_fifo_uevent(&priv->base); +- ints &= ~1; +- } +- if (ints) { +- nv_error(priv, "ENGINE %d %d %01x", engn, unkn, ints); +- nv_mask(priv, 0x002628, ints, 0); +- } +- } +-} +- +-static void +-nvc0_fifo_intr_engine(struct nvc0_fifo_priv *priv) +-{ +- u32 mask = nv_rd32(priv, 0x0025a4); +- while (mask) { +- u32 unit = __ffs(mask); +- nvc0_fifo_intr_engine_unit(priv, unit); +- mask &= ~(1 << unit); +- } +-} +- +-static void +-nvc0_fifo_intr(struct nouveau_subdev *subdev) +-{ +- struct nvc0_fifo_priv *priv = (void *)subdev; +- u32 mask = nv_rd32(priv, 0x002140); +- u32 stat = nv_rd32(priv, 0x002100) & mask; +- +- if (stat & 0x00000001) { +- u32 intr = nv_rd32(priv, 0x00252c); +- nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr); +- nv_wr32(priv, 0x002100, 0x00000001); +- stat &= ~0x00000001; +- } +- +- if (stat & 0x00000100) { +- nvc0_fifo_intr_sched(priv); +- nv_wr32(priv, 0x002100, 0x00000100); +- stat &= ~0x00000100; +- } +- +- if (stat & 0x00010000) { +- u32 intr = nv_rd32(priv, 0x00256c); +- nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr); +- nv_wr32(priv, 0x002100, 0x00010000); +- stat &= ~0x00010000; +- } +- +- if (stat & 0x01000000) { +- u32 intr = nv_rd32(priv, 0x00258c); +- nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr); +- nv_wr32(priv, 0x002100, 0x01000000); +- stat &= ~0x01000000; +- } +- +- if (stat & 0x10000000) { +- u32 mask = nv_rd32(priv, 0x00259c); +- while (mask) { +- u32 unit = __ffs(mask); +- nvc0_fifo_intr_fault(priv, unit); +- nv_wr32(priv, 0x00259c, (1 << unit)); +- mask &= ~(1 << unit); +- } +- stat &= ~0x10000000; +- } +- +- if (stat & 0x20000000) { +- u32 mask = nv_rd32(priv, 0x0025a0); +- while (mask) { +- u32 unit = __ffs(mask); +- nvc0_fifo_intr_pbdma(priv, unit); +- nv_wr32(priv, 0x0025a0, (1 << unit)); +- mask &= ~(1 << unit); +- } +- stat &= ~0x20000000; +- } +- +- if (stat & 0x40000000) { +- nvc0_fifo_intr_runlist(priv); +- stat &= ~0x40000000; +- } +- +- if (stat & 0x80000000) { +- nvc0_fifo_intr_engine(priv); +- stat &= ~0x80000000; +- } +- +- if (stat) { +- nv_error(priv, "INTR 0x%08x\n", stat); +- nv_mask(priv, 0x002140, stat, 0x00000000); +- nv_wr32(priv, 0x002100, stat); +- } +-} +- +-static void +-nvc0_fifo_uevent_init(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); +- nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); +-} +- +-static void +-nvc0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); +- nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); +-} +- +-static const struct nvkm_event_func +-nvc0_fifo_uevent_func = { +- .ctor = nouveau_fifo_uevent_ctor, +- .init = nvc0_fifo_uevent_init, +- .fini = nvc0_fifo_uevent_fini, +-}; +- +-static int +-nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_fifo_priv *priv; +- int ret; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- INIT_WORK(&priv->fault, nvc0_fifo_recover_work); +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, +- &priv->runlist.mem[0]); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0, +- &priv->runlist.mem[1]); +- if (ret) +- return ret; +- +- init_waitqueue_head(&priv->runlist.wait); +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0, +- &priv->user.mem); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, +- &priv->user.bar); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nvc0_fifo_uevent_func, 1, 1, &priv->base.uevent); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nvc0_fifo_intr; +- nv_engine(priv)->cclass = &nvc0_fifo_cclass; +- nv_engine(priv)->sclass = nvc0_fifo_sclass; +- return 0; +-} +- +-static void +-nvc0_fifo_dtor(struct nouveau_object *object) +-{ +- struct nvc0_fifo_priv *priv = (void *)object; +- +- nouveau_gpuobj_unmap(&priv->user.bar); +- nouveau_gpuobj_ref(NULL, &priv->user.mem); +- nouveau_gpuobj_ref(NULL, &priv->runlist.mem[0]); +- nouveau_gpuobj_ref(NULL, &priv->runlist.mem[1]); +- +- nouveau_fifo_destroy(&priv->base); +-} +- +-static int +-nvc0_fifo_init(struct nouveau_object *object) +-{ +- struct nvc0_fifo_priv *priv = (void *)object; +- int ret, i; +- +- ret = nouveau_fifo_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x000204, 0xffffffff); +- nv_wr32(priv, 0x002204, 0xffffffff); +- +- priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204)); +- nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); +- +- /* assign engines to PBDMAs */ +- if (priv->spoon_nr >= 3) { +- nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ +- nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ +- nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */ +- nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */ +- nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ +- nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ +- } +- +- /* PBDMA[n] */ +- for (i = 0; i < priv->spoon_nr; i++) { +- nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); +- nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ +- nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ +- } +- +- nv_mask(priv, 0x002200, 0x00000001, 0x00000001); +- nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); +- +- nv_wr32(priv, 0x002100, 0xffffffff); +- nv_wr32(priv, 0x002140, 0x7fffffff); +- nv_wr32(priv, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ +- return 0; +-} +- +-struct nouveau_oclass * +-nvc0_fifo_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(FIFO, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_fifo_ctor, +- .dtor = nvc0_fifo_dtor, +- .init = nvc0_fifo_init, +- .fini = _nouveau_fifo_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c +deleted file mode 100644 +index f8734eb7..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c ++++ /dev/null +@@ -1,1111 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-#include +- +-#include "nve0.h" +- +-#define _(a,b) { (a), ((1ULL << (a)) | (b)) } +-static const struct { +- u64 subdev; +- u64 mask; +-} fifo_engine[] = { +- _(NVDEV_ENGINE_GR , (1ULL << NVDEV_ENGINE_SW) | +- (1ULL << NVDEV_ENGINE_COPY2)), +- _(NVDEV_ENGINE_VP , 0), +- _(NVDEV_ENGINE_PPP , 0), +- _(NVDEV_ENGINE_BSP , 0), +- _(NVDEV_ENGINE_COPY0 , 0), +- _(NVDEV_ENGINE_COPY1 , 0), +- _(NVDEV_ENGINE_VENC , 0), +-}; +-#undef _ +-#define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine) +- +-struct nve0_fifo_engn { +- struct nouveau_gpuobj *runlist[2]; +- int cur_runlist; +- wait_queue_head_t wait; +-}; +- +-struct nve0_fifo_priv { +- struct nouveau_fifo base; +- +- struct work_struct fault; +- u64 mask; +- +- struct nve0_fifo_engn engine[FIFO_ENGINE_NR]; +- struct { +- struct nouveau_gpuobj *mem; +- struct nouveau_vma bar; +- } user; +- int spoon_nr; +-}; +- +-struct nve0_fifo_base { +- struct nouveau_fifo_base base; +- struct nouveau_gpuobj *pgd; +- struct nouveau_vm *vm; +-}; +- +-struct nve0_fifo_chan { +- struct nouveau_fifo_chan base; +- u32 engine; +- enum { +- STOPPED, +- RUNNING, +- KILLED +- } state; +-}; +- +-/******************************************************************************* +- * FIFO channel objects +- ******************************************************************************/ +- +-static void +-nve0_fifo_runlist_update(struct nve0_fifo_priv *priv, u32 engine) +-{ +- struct nouveau_bar *bar = nouveau_bar(priv); +- struct nve0_fifo_engn *engn = &priv->engine[engine]; +- struct nouveau_gpuobj *cur; +- int i, p; +- +- mutex_lock(&nv_subdev(priv)->mutex); +- cur = engn->runlist[engn->cur_runlist]; +- engn->cur_runlist = !engn->cur_runlist; +- +- for (i = 0, p = 0; i < priv->base.max; i++) { +- struct nve0_fifo_chan *chan = (void *)priv->base.channel[i]; +- if (chan && chan->state == RUNNING && chan->engine == engine) { +- nv_wo32(cur, p + 0, i); +- nv_wo32(cur, p + 4, 0x00000000); +- p += 8; +- } +- } +- bar->flush(bar); +- +- nv_wr32(priv, 0x002270, cur->addr >> 12); +- nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3)); +- +- if (wait_event_timeout(engn->wait, !(nv_rd32(priv, 0x002284 + +- (engine * 0x08)) & 0x00100000), +- msecs_to_jiffies(2000)) == 0) +- nv_error(priv, "runlist %d update timeout\n", engine); +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-static int +-nve0_fifo_context_attach(struct nouveau_object *parent, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nve0_fifo_base *base = (void *)parent->parent; +- struct nouveau_engctx *ectx = (void *)object; +- u32 addr; +- int ret; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : +- return 0; +- case NVDEV_ENGINE_COPY0: +- case NVDEV_ENGINE_COPY1: +- case NVDEV_ENGINE_COPY2: +- nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; +- return 0; +- case NVDEV_ENGINE_GR : addr = 0x0210; break; +- case NVDEV_ENGINE_BSP : addr = 0x0270; break; +- case NVDEV_ENGINE_VP : addr = 0x0250; break; +- case NVDEV_ENGINE_PPP : addr = 0x0260; break; +- default: +- return -EINVAL; +- } +- +- if (!ectx->vma.node) { +- ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, +- NV_MEM_ACCESS_RW, &ectx->vma); +- if (ret) +- return ret; +- +- nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; +- } +- +- nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); +- nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); +- bar->flush(bar); +- return 0; +-} +- +-static int +-nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, +- struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nve0_fifo_priv *priv = (void *)parent->engine; +- struct nve0_fifo_base *base = (void *)parent->parent; +- struct nve0_fifo_chan *chan = (void *)parent; +- u32 addr; +- +- switch (nv_engidx(object->engine)) { +- case NVDEV_ENGINE_SW : return 0; +- case NVDEV_ENGINE_COPY0: +- case NVDEV_ENGINE_COPY1: +- case NVDEV_ENGINE_COPY2: addr = 0x0000; break; +- case NVDEV_ENGINE_GR : addr = 0x0210; break; +- case NVDEV_ENGINE_BSP : addr = 0x0270; break; +- case NVDEV_ENGINE_VP : addr = 0x0250; break; +- case NVDEV_ENGINE_PPP : addr = 0x0260; break; +- default: +- return -EINVAL; +- } +- +- nv_wr32(priv, 0x002634, chan->base.chid); +- if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) { +- nv_error(priv, "channel %d [%s] kick timeout\n", +- chan->base.chid, nouveau_client_name(chan)); +- if (suspend) +- return -EBUSY; +- } +- +- if (addr) { +- nv_wo32(base, addr + 0x00, 0x00000000); +- nv_wo32(base, addr + 0x04, 0x00000000); +- bar->flush(bar); +- } +- +- return 0; +-} +- +-static int +-nve0_fifo_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct kepler_channel_gpfifo_a_v0 v0; +- } *args = data; +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nve0_fifo_priv *priv = (void *)engine; +- struct nve0_fifo_base *base = (void *)parent; +- struct nve0_fifo_chan *chan; +- u64 usermem, ioffset, ilength; +- int ret, i; +- +- nv_ioctl(parent, "create channel gpfifo size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " +- "ioffset %016llx ilength %08x engine %08x\n", +- args->v0.version, args->v0.pushbuf, args->v0.ioffset, +- args->v0.ilength, args->v0.engine); +- } else +- return ret; +- +- for (i = 0; i < FIFO_ENGINE_NR; i++) { +- if (args->v0.engine & (1 << i)) { +- if (nouveau_engine(parent, fifo_engine[i].subdev)) { +- args->v0.engine = (1 << i); +- break; +- } +- } +- } +- +- if (i == FIFO_ENGINE_NR) { +- nv_error(priv, "unsupported engines 0x%08x\n", args->v0.engine); +- return -ENODEV; +- } +- +- ret = nouveau_fifo_channel_create(parent, engine, oclass, 1, +- priv->user.bar.offset, 0x200, +- args->v0.pushbuf, +- fifo_engine[i].mask, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- args->v0.chid = chan->base.chid; +- +- nv_parent(chan)->context_attach = nve0_fifo_context_attach; +- nv_parent(chan)->context_detach = nve0_fifo_context_detach; +- chan->engine = i; +- +- usermem = chan->base.chid * 0x200; +- ioffset = args->v0.ioffset; +- ilength = order_base_2(args->v0.ilength / 8); +- +- for (i = 0; i < 0x200; i += 4) +- nv_wo32(priv->user.mem, usermem + i, 0x00000000); +- +- nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem)); +- nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem)); +- nv_wo32(base, 0x10, 0x0000face); +- nv_wo32(base, 0x30, 0xfffff902); +- nv_wo32(base, 0x48, lower_32_bits(ioffset)); +- nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); +- nv_wo32(base, 0x84, 0x20400000); +- nv_wo32(base, 0x94, 0x30000001); +- nv_wo32(base, 0x9c, 0x00000100); +- nv_wo32(base, 0xac, 0x0000001f); +- nv_wo32(base, 0xe8, chan->base.chid); +- nv_wo32(base, 0xb8, 0xf8000000); +- nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */ +- nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */ +- bar->flush(bar); +- return 0; +-} +- +-static int +-nve0_fifo_chan_init(struct nouveau_object *object) +-{ +- struct nouveau_gpuobj *base = nv_gpuobj(object->parent); +- struct nve0_fifo_priv *priv = (void *)object->engine; +- struct nve0_fifo_chan *chan = (void *)object; +- u32 chid = chan->base.chid; +- int ret; +- +- ret = nouveau_fifo_channel_init(&chan->base); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16); +- nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12); +- +- if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { +- nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); +- nve0_fifo_runlist_update(priv, chan->engine); +- nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400); +- } +- +- return 0; +-} +- +-static int +-nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nve0_fifo_priv *priv = (void *)object->engine; +- struct nve0_fifo_chan *chan = (void *)object; +- u32 chid = chan->base.chid; +- +- if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { +- nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800); +- nve0_fifo_runlist_update(priv, chan->engine); +- } +- +- nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000); +- return nouveau_fifo_channel_fini(&chan->base, suspend); +-} +- +-static struct nouveau_ofuncs +-nve0_fifo_ofuncs = { +- .ctor = nve0_fifo_chan_ctor, +- .dtor = _nouveau_fifo_channel_dtor, +- .init = nve0_fifo_chan_init, +- .fini = nve0_fifo_chan_fini, +- .map = _nouveau_fifo_channel_map, +- .rd32 = _nouveau_fifo_channel_rd32, +- .wr32 = _nouveau_fifo_channel_wr32, +- .ntfy = _nouveau_fifo_channel_ntfy +-}; +- +-static struct nouveau_oclass +-nve0_fifo_sclass[] = { +- { KEPLER_CHANNEL_GPFIFO_A, &nve0_fifo_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * FIFO context - instmem heap and vm setup +- ******************************************************************************/ +- +-static int +-nve0_fifo_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_fifo_base *base; +- int ret; +- +- ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000, +- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base); +- *pobject = nv_object(base); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, +- &base->pgd); +- if (ret) +- return ret; +- +- nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr)); +- nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr)); +- nv_wo32(base, 0x0208, 0xffffffff); +- nv_wo32(base, 0x020c, 0x000000ff); +- +- ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static void +-nve0_fifo_context_dtor(struct nouveau_object *object) +-{ +- struct nve0_fifo_base *base = (void *)object; +- nouveau_vm_ref(NULL, &base->vm, base->pgd); +- nouveau_gpuobj_ref(NULL, &base->pgd); +- nouveau_fifo_context_destroy(&base->base); +-} +- +-static struct nouveau_oclass +-nve0_fifo_cclass = { +- .handle = NV_ENGCTX(FIFO, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_fifo_context_ctor, +- .dtor = nve0_fifo_context_dtor, +- .init = _nouveau_fifo_context_init, +- .fini = _nouveau_fifo_context_fini, +- .rd32 = _nouveau_fifo_context_rd32, +- .wr32 = _nouveau_fifo_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PFIFO engine +- ******************************************************************************/ +- +-static inline int +-nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) +-{ +- switch (engn) { +- case NVDEV_ENGINE_GR : +- case NVDEV_ENGINE_COPY2: engn = 0; break; +- case NVDEV_ENGINE_BSP : engn = 1; break; +- case NVDEV_ENGINE_PPP : engn = 2; break; +- case NVDEV_ENGINE_VP : engn = 3; break; +- case NVDEV_ENGINE_COPY0: engn = 4; break; +- case NVDEV_ENGINE_COPY1: engn = 5; break; +- case NVDEV_ENGINE_VENC : engn = 6; break; +- default: +- return -1; +- } +- +- return engn; +-} +- +-static inline struct nouveau_engine * +-nve0_fifo_engine(struct nve0_fifo_priv *priv, u32 engn) +-{ +- if (engn >= ARRAY_SIZE(fifo_engine)) +- return NULL; +- return nouveau_engine(priv, fifo_engine[engn].subdev); +-} +- +-static void +-nve0_fifo_recover_work(struct work_struct *work) +-{ +- struct nve0_fifo_priv *priv = container_of(work, typeof(*priv), fault); +- struct nouveau_object *engine; +- unsigned long flags; +- u32 engn, engm = 0; +- u64 mask, todo; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- mask = priv->mask; +- priv->mask = 0ULL; +- spin_unlock_irqrestore(&priv->base.lock, flags); +- +- for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) +- engm |= 1 << nve0_fifo_engidx(priv, engn); +- nv_mask(priv, 0x002630, engm, engm); +- +- for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { +- if ((engine = (void *)nouveau_engine(priv, engn))) { +- nv_ofuncs(engine)->fini(engine, false); +- WARN_ON(nv_ofuncs(engine)->init(engine)); +- } +- nve0_fifo_runlist_update(priv, nve0_fifo_engidx(priv, engn)); +- } +- +- nv_wr32(priv, 0x00262c, engm); +- nv_mask(priv, 0x002630, engm, 0x00000000); +-} +- +-static void +-nve0_fifo_recover(struct nve0_fifo_priv *priv, struct nouveau_engine *engine, +- struct nve0_fifo_chan *chan) +-{ +- struct nouveau_object *engobj = nv_object(engine); +- u32 chid = chan->base.chid; +- unsigned long flags; +- +- nv_error(priv, "%s engine fault on channel %d, recovering...\n", +- nv_subdev(engine)->name, chid); +- +- nv_mask(priv, 0x800004 + (chid * 0x08), 0x00000800, 0x00000800); +- chan->state = KILLED; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- priv->mask |= 1ULL << nv_engidx(engobj); +- spin_unlock_irqrestore(&priv->base.lock, flags); +- schedule_work(&priv->fault); +-} +- +-static int +-nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data) +-{ +- struct nve0_fifo_chan *chan = NULL; +- struct nouveau_handle *bind; +- unsigned long flags; +- int ret = -EINVAL; +- +- spin_lock_irqsave(&priv->base.lock, flags); +- if (likely(chid >= priv->base.min && chid <= priv->base.max)) +- chan = (void *)priv->base.channel[chid]; +- if (unlikely(!chan)) +- goto out; +- +- bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e); +- if (likely(bind)) { +- if (!mthd || !nv_call(bind->object, mthd, data)) +- ret = 0; +- nouveau_namedb_put(bind); +- } +- +-out: +- spin_unlock_irqrestore(&priv->base.lock, flags); +- return ret; +-} +- +-static const struct nouveau_enum +-nve0_fifo_bind_reason[] = { +- { 0x01, "BIND_NOT_UNBOUND" }, +- { 0x02, "SNOOP_WITHOUT_BAR1" }, +- { 0x03, "UNBIND_WHILE_RUNNING" }, +- { 0x05, "INVALID_RUNLIST" }, +- { 0x06, "INVALID_CTX_TGT" }, +- { 0x0b, "UNBIND_WHILE_PARKED" }, +- {} +-}; +- +-static void +-nve0_fifo_intr_bind(struct nve0_fifo_priv *priv) +-{ +- u32 intr = nv_rd32(priv, 0x00252c); +- u32 code = intr & 0x000000ff; +- const struct nouveau_enum *en; +- char enunk[6] = ""; +- +- en = nouveau_enum_find(nve0_fifo_bind_reason, code); +- if (!en) +- snprintf(enunk, sizeof(enunk), "UNK%02x", code); +- +- nv_error(priv, "BIND_ERROR [ %s ]\n", en ? en->name : enunk); +-} +- +-static const struct nouveau_enum +-nve0_fifo_sched_reason[] = { +- { 0x0a, "CTXSW_TIMEOUT" }, +- {} +-}; +- +-static void +-nve0_fifo_intr_sched_ctxsw(struct nve0_fifo_priv *priv) +-{ +- struct nouveau_engine *engine; +- struct nve0_fifo_chan *chan; +- u32 engn; +- +- for (engn = 0; engn < ARRAY_SIZE(fifo_engine); engn++) { +- u32 stat = nv_rd32(priv, 0x002640 + (engn * 0x04)); +- u32 busy = (stat & 0x80000000); +- u32 next = (stat & 0x07ff0000) >> 16; +- u32 chsw = (stat & 0x00008000); +- u32 save = (stat & 0x00004000); +- u32 load = (stat & 0x00002000); +- u32 prev = (stat & 0x000007ff); +- u32 chid = load ? next : prev; +- (void)save; +- +- if (busy && chsw) { +- if (!(chan = (void *)priv->base.channel[chid])) +- continue; +- if (!(engine = nve0_fifo_engine(priv, engn))) +- continue; +- nve0_fifo_recover(priv, engine, chan); +- } +- } +-} +- +-static void +-nve0_fifo_intr_sched(struct nve0_fifo_priv *priv) +-{ +- u32 intr = nv_rd32(priv, 0x00254c); +- u32 code = intr & 0x000000ff; +- const struct nouveau_enum *en; +- char enunk[6] = ""; +- +- en = nouveau_enum_find(nve0_fifo_sched_reason, code); +- if (!en) +- snprintf(enunk, sizeof(enunk), "UNK%02x", code); +- +- nv_error(priv, "SCHED_ERROR [ %s ]\n", en ? en->name : enunk); +- +- switch (code) { +- case 0x0a: +- nve0_fifo_intr_sched_ctxsw(priv); +- break; +- default: +- break; +- } +-} +- +-static void +-nve0_fifo_intr_chsw(struct nve0_fifo_priv *priv) +-{ +- u32 stat = nv_rd32(priv, 0x00256c); +- nv_error(priv, "CHSW_ERROR 0x%08x\n", stat); +- nv_wr32(priv, 0x00256c, stat); +-} +- +-static void +-nve0_fifo_intr_dropped_fault(struct nve0_fifo_priv *priv) +-{ +- u32 stat = nv_rd32(priv, 0x00259c); +- nv_error(priv, "DROPPED_MMU_FAULT 0x%08x\n", stat); +-} +- +-static const struct nouveau_enum +-nve0_fifo_fault_engine[] = { +- { 0x00, "GR", NULL, NVDEV_ENGINE_GR }, +- { 0x03, "IFB", NULL, NVDEV_ENGINE_IFB }, +- { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, +- { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, +- { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, +- { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, +- { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, +- { 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP }, +- { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP }, +- { 0x13, "PERF" }, +- { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP }, +- { 0x15, "CE0", NULL, NVDEV_ENGINE_COPY0 }, +- { 0x16, "CE1", NULL, NVDEV_ENGINE_COPY1 }, +- { 0x17, "PMU" }, +- { 0x19, "MSENC", NULL, NVDEV_ENGINE_VENC }, +- { 0x1b, "CE2", NULL, NVDEV_ENGINE_COPY2 }, +- {} +-}; +- +-static const struct nouveau_enum +-nve0_fifo_fault_reason[] = { +- { 0x00, "PDE" }, +- { 0x01, "PDE_SIZE" }, +- { 0x02, "PTE" }, +- { 0x03, "VA_LIMIT_VIOLATION" }, +- { 0x04, "UNBOUND_INST_BLOCK" }, +- { 0x05, "PRIV_VIOLATION" }, +- { 0x06, "RO_VIOLATION" }, +- { 0x07, "WO_VIOLATION" }, +- { 0x08, "PITCH_MASK_VIOLATION" }, +- { 0x09, "WORK_CREATION" }, +- { 0x0a, "UNSUPPORTED_APERTURE" }, +- { 0x0b, "COMPRESSION_FAILURE" }, +- { 0x0c, "UNSUPPORTED_KIND" }, +- { 0x0d, "REGION_VIOLATION" }, +- { 0x0e, "BOTH_PTES_VALID" }, +- { 0x0f, "INFO_TYPE_POISONED" }, +- {} +-}; +- +-static const struct nouveau_enum +-nve0_fifo_fault_hubclient[] = { +- { 0x00, "VIP" }, +- { 0x01, "CE0" }, +- { 0x02, "CE1" }, +- { 0x03, "DNISO" }, +- { 0x04, "FE" }, +- { 0x05, "FECS" }, +- { 0x06, "HOST" }, +- { 0x07, "HOST_CPU" }, +- { 0x08, "HOST_CPU_NB" }, +- { 0x09, "ISO" }, +- { 0x0a, "MMU" }, +- { 0x0b, "MSPDEC" }, +- { 0x0c, "MSPPP" }, +- { 0x0d, "MSVLD" }, +- { 0x0e, "NISO" }, +- { 0x0f, "P2P" }, +- { 0x10, "PD" }, +- { 0x11, "PERF" }, +- { 0x12, "PMU" }, +- { 0x13, "RASTERTWOD" }, +- { 0x14, "SCC" }, +- { 0x15, "SCC_NB" }, +- { 0x16, "SEC" }, +- { 0x17, "SSYNC" }, +- { 0x18, "GR_COPY" }, +- { 0x19, "CE2" }, +- { 0x1a, "XV" }, +- { 0x1b, "MMU_NB" }, +- { 0x1c, "MSENC" }, +- { 0x1d, "DFALCON" }, +- { 0x1e, "SKED" }, +- { 0x1f, "AFALCON" }, +- {} +-}; +- +-static const struct nouveau_enum +-nve0_fifo_fault_gpcclient[] = { +- { 0x00, "L1_0" }, { 0x01, "T1_0" }, { 0x02, "PE_0" }, +- { 0x03, "L1_1" }, { 0x04, "T1_1" }, { 0x05, "PE_1" }, +- { 0x06, "L1_2" }, { 0x07, "T1_2" }, { 0x08, "PE_2" }, +- { 0x09, "L1_3" }, { 0x0a, "T1_3" }, { 0x0b, "PE_3" }, +- { 0x0c, "RAST" }, +- { 0x0d, "GCC" }, +- { 0x0e, "GPCCS" }, +- { 0x0f, "PROP_0" }, +- { 0x10, "PROP_1" }, +- { 0x11, "PROP_2" }, +- { 0x12, "PROP_3" }, +- { 0x13, "L1_4" }, { 0x14, "T1_4" }, { 0x15, "PE_4" }, +- { 0x16, "L1_5" }, { 0x17, "T1_5" }, { 0x18, "PE_5" }, +- { 0x19, "L1_6" }, { 0x1a, "T1_6" }, { 0x1b, "PE_6" }, +- { 0x1c, "L1_7" }, { 0x1d, "T1_7" }, { 0x1e, "PE_7" }, +- { 0x1f, "GPM" }, +- { 0x20, "LTP_UTLB_0" }, +- { 0x21, "LTP_UTLB_1" }, +- { 0x22, "LTP_UTLB_2" }, +- { 0x23, "LTP_UTLB_3" }, +- { 0x24, "GPC_RGG_UTLB" }, +- {} +-}; +- +-static void +-nve0_fifo_intr_fault(struct nve0_fifo_priv *priv, int unit) +-{ +- u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10)); +- u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10)); +- u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10)); +- u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10)); +- u32 gpc = (stat & 0x1f000000) >> 24; +- u32 client = (stat & 0x00001f00) >> 8; +- u32 write = (stat & 0x00000080); +- u32 hub = (stat & 0x00000040); +- u32 reason = (stat & 0x0000000f); +- struct nouveau_object *engctx = NULL, *object; +- struct nouveau_engine *engine = NULL; +- const struct nouveau_enum *er, *eu, *ec; +- char erunk[6] = ""; +- char euunk[6] = ""; +- char ecunk[6] = ""; +- char gpcid[3] = ""; +- +- er = nouveau_enum_find(nve0_fifo_fault_reason, reason); +- if (!er) +- snprintf(erunk, sizeof(erunk), "UNK%02X", reason); +- +- eu = nouveau_enum_find(nve0_fifo_fault_engine, unit); +- if (eu) { +- switch (eu->data2) { +- case NVDEV_SUBDEV_BAR: +- nv_mask(priv, 0x001704, 0x00000000, 0x00000000); +- break; +- case NVDEV_SUBDEV_INSTMEM: +- nv_mask(priv, 0x001714, 0x00000000, 0x00000000); +- break; +- case NVDEV_ENGINE_IFB: +- nv_mask(priv, 0x001718, 0x00000000, 0x00000000); +- break; +- default: +- engine = nouveau_engine(priv, eu->data2); +- if (engine) +- engctx = nouveau_engctx_get(engine, inst); +- break; +- } +- } else { +- snprintf(euunk, sizeof(euunk), "UNK%02x", unit); +- } +- +- if (hub) { +- ec = nouveau_enum_find(nve0_fifo_fault_hubclient, client); +- } else { +- ec = nouveau_enum_find(nve0_fifo_fault_gpcclient, client); +- snprintf(gpcid, sizeof(gpcid), "%d", gpc); +- } +- +- if (!ec) +- snprintf(ecunk, sizeof(ecunk), "UNK%02x", client); +- +- nv_error(priv, "%s fault at 0x%010llx [%s] from %s/%s%s%s%s on " +- "channel 0x%010llx [%s]\n", write ? "write" : "read", +- (u64)vahi << 32 | valo, er ? er->name : erunk, +- eu ? eu->name : euunk, hub ? "" : "GPC", gpcid, hub ? "" : "/", +- ec ? ec->name : ecunk, (u64)inst << 12, +- nouveau_client_name(engctx)); +- +- object = engctx; +- while (object) { +- switch (nv_mclass(object)) { +- case KEPLER_CHANNEL_GPFIFO_A: +- nve0_fifo_recover(priv, engine, (void *)object); +- break; +- } +- object = object->parent; +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static const struct nouveau_bitfield nve0_fifo_pbdma_intr[] = { +- { 0x00000001, "MEMREQ" }, +- { 0x00000002, "MEMACK_TIMEOUT" }, +- { 0x00000004, "MEMACK_EXTRA" }, +- { 0x00000008, "MEMDAT_TIMEOUT" }, +- { 0x00000010, "MEMDAT_EXTRA" }, +- { 0x00000020, "MEMFLUSH" }, +- { 0x00000040, "MEMOP" }, +- { 0x00000080, "LBCONNECT" }, +- { 0x00000100, "LBREQ" }, +- { 0x00000200, "LBACK_TIMEOUT" }, +- { 0x00000400, "LBACK_EXTRA" }, +- { 0x00000800, "LBDAT_TIMEOUT" }, +- { 0x00001000, "LBDAT_EXTRA" }, +- { 0x00002000, "GPFIFO" }, +- { 0x00004000, "GPPTR" }, +- { 0x00008000, "GPENTRY" }, +- { 0x00010000, "GPCRC" }, +- { 0x00020000, "PBPTR" }, +- { 0x00040000, "PBENTRY" }, +- { 0x00080000, "PBCRC" }, +- { 0x00100000, "XBARCONNECT" }, +- { 0x00200000, "METHOD" }, +- { 0x00400000, "METHODCRC" }, +- { 0x00800000, "DEVICE" }, +- { 0x02000000, "SEMAPHORE" }, +- { 0x04000000, "ACQUIRE" }, +- { 0x08000000, "PRI" }, +- { 0x20000000, "NO_CTXSW_SEG" }, +- { 0x40000000, "PBSEG" }, +- { 0x80000000, "SIGNATURE" }, +- {} +-}; +- +-static void +-nve0_fifo_intr_pbdma(struct nve0_fifo_priv *priv, int unit) +-{ +- u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000)); +- u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000)); +- u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000)); +- u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff; +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00003ffc); +- u32 show = stat; +- +- if (stat & 0x00800000) { +- if (!nve0_fifo_swmthd(priv, chid, mthd, data)) +- show &= ~0x00800000; +- } +- +- if (show) { +- nv_error(priv, "PBDMA%d:", unit); +- nouveau_bitfield_print(nve0_fifo_pbdma_intr, show); +- pr_cont("\n"); +- nv_error(priv, +- "PBDMA%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n", +- unit, chid, +- nouveau_client_name_for_fifo_chid(&priv->base, chid), +- subc, mthd, data); +- } +- +- nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008); +- nv_wr32(priv, 0x040108 + (unit * 0x2000), stat); +-} +- +-static void +-nve0_fifo_intr_runlist(struct nve0_fifo_priv *priv) +-{ +- u32 mask = nv_rd32(priv, 0x002a00); +- while (mask) { +- u32 engn = __ffs(mask); +- wake_up(&priv->engine[engn].wait); +- nv_wr32(priv, 0x002a00, 1 << engn); +- mask &= ~(1 << engn); +- } +-} +- +-static void +-nve0_fifo_intr_engine(struct nve0_fifo_priv *priv) +-{ +- nouveau_fifo_uevent(&priv->base); +-} +- +-static void +-nve0_fifo_intr(struct nouveau_subdev *subdev) +-{ +- struct nve0_fifo_priv *priv = (void *)subdev; +- u32 mask = nv_rd32(priv, 0x002140); +- u32 stat = nv_rd32(priv, 0x002100) & mask; +- +- if (stat & 0x00000001) { +- nve0_fifo_intr_bind(priv); +- nv_wr32(priv, 0x002100, 0x00000001); +- stat &= ~0x00000001; +- } +- +- if (stat & 0x00000010) { +- nv_error(priv, "PIO_ERROR\n"); +- nv_wr32(priv, 0x002100, 0x00000010); +- stat &= ~0x00000010; +- } +- +- if (stat & 0x00000100) { +- nve0_fifo_intr_sched(priv); +- nv_wr32(priv, 0x002100, 0x00000100); +- stat &= ~0x00000100; +- } +- +- if (stat & 0x00010000) { +- nve0_fifo_intr_chsw(priv); +- nv_wr32(priv, 0x002100, 0x00010000); +- stat &= ~0x00010000; +- } +- +- if (stat & 0x00800000) { +- nv_error(priv, "FB_FLUSH_TIMEOUT\n"); +- nv_wr32(priv, 0x002100, 0x00800000); +- stat &= ~0x00800000; +- } +- +- if (stat & 0x01000000) { +- nv_error(priv, "LB_ERROR\n"); +- nv_wr32(priv, 0x002100, 0x01000000); +- stat &= ~0x01000000; +- } +- +- if (stat & 0x08000000) { +- nve0_fifo_intr_dropped_fault(priv); +- nv_wr32(priv, 0x002100, 0x08000000); +- stat &= ~0x08000000; +- } +- +- if (stat & 0x10000000) { +- u32 mask = nv_rd32(priv, 0x00259c); +- while (mask) { +- u32 unit = __ffs(mask); +- nve0_fifo_intr_fault(priv, unit); +- nv_wr32(priv, 0x00259c, (1 << unit)); +- mask &= ~(1 << unit); +- } +- stat &= ~0x10000000; +- } +- +- if (stat & 0x20000000) { +- u32 mask = nv_rd32(priv, 0x0025a0); +- while (mask) { +- u32 unit = __ffs(mask); +- nve0_fifo_intr_pbdma(priv, unit); +- nv_wr32(priv, 0x0025a0, (1 << unit)); +- mask &= ~(1 << unit); +- } +- stat &= ~0x20000000; +- } +- +- if (stat & 0x40000000) { +- nve0_fifo_intr_runlist(priv); +- stat &= ~0x40000000; +- } +- +- if (stat & 0x80000000) { +- nv_wr32(priv, 0x002100, 0x80000000); +- nve0_fifo_intr_engine(priv); +- stat &= ~0x80000000; +- } +- +- if (stat) { +- nv_error(priv, "INTR 0x%08x\n", stat); +- nv_mask(priv, 0x002140, stat, 0x00000000); +- nv_wr32(priv, 0x002100, stat); +- } +-} +- +-static void +-nve0_fifo_uevent_init(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); +- nv_mask(fifo, 0x002140, 0x80000000, 0x80000000); +-} +- +-static void +-nve0_fifo_uevent_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_fifo *fifo = container_of(event, typeof(*fifo), uevent); +- nv_mask(fifo, 0x002140, 0x80000000, 0x00000000); +-} +- +-static const struct nvkm_event_func +-nve0_fifo_uevent_func = { +- .ctor = nouveau_fifo_uevent_ctor, +- .init = nve0_fifo_uevent_init, +- .fini = nve0_fifo_uevent_fini, +-}; +- +-int +-nve0_fifo_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nve0_fifo_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fifo_fini(&priv->base, suspend); +- if (ret) +- return ret; +- +- /* allow mmu fault interrupts, even when we're not using fifo */ +- nv_mask(priv, 0x002140, 0x10000000, 0x10000000); +- return 0; +-} +- +-int +-nve0_fifo_init(struct nouveau_object *object) +-{ +- struct nve0_fifo_priv *priv = (void *)object; +- int ret, i; +- +- ret = nouveau_fifo_init(&priv->base); +- if (ret) +- return ret; +- +- /* enable all available PBDMA units */ +- nv_wr32(priv, 0x000204, 0xffffffff); +- priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204)); +- nv_debug(priv, "%d PBDMA unit(s)\n", priv->spoon_nr); +- +- /* PBDMA[n] */ +- for (i = 0; i < priv->spoon_nr; i++) { +- nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); +- nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ +- nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ +- } +- +- nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12); +- +- nv_wr32(priv, 0x002100, 0xffffffff); +- nv_wr32(priv, 0x002140, 0x7fffffff); +- return 0; +-} +- +-void +-nve0_fifo_dtor(struct nouveau_object *object) +-{ +- struct nve0_fifo_priv *priv = (void *)object; +- int i; +- +- nouveau_gpuobj_unmap(&priv->user.bar); +- nouveau_gpuobj_ref(NULL, &priv->user.mem); +- +- for (i = 0; i < FIFO_ENGINE_NR; i++) { +- nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[1]); +- nouveau_gpuobj_ref(NULL, &priv->engine[i].runlist[0]); +- } +- +- nouveau_fifo_destroy(&priv->base); +-} +- +-int +-nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_fifo_impl *impl = (void *)oclass; +- struct nve0_fifo_priv *priv; +- int ret, i; +- +- ret = nouveau_fifo_create(parent, engine, oclass, 0, +- impl->channels - 1, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- INIT_WORK(&priv->fault, nve0_fifo_recover_work); +- +- for (i = 0; i < FIFO_ENGINE_NR; i++) { +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, +- 0, &priv->engine[i].runlist[0]); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000, +- 0, &priv->engine[i].runlist[1]); +- if (ret) +- return ret; +- +- init_waitqueue_head(&priv->engine[i].wait); +- } +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, impl->channels * 0x200, +- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW, +- &priv->user.bar); +- if (ret) +- return ret; +- +- ret = nvkm_event_init(&nve0_fifo_uevent_func, 1, 1, &priv->base.uevent); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000100; +- nv_subdev(priv)->intr = nve0_fifo_intr; +- nv_engine(priv)->cclass = &nve0_fifo_cclass; +- nv_engine(priv)->sclass = nve0_fifo_sclass; +- return 0; +-} +- +-struct nouveau_oclass * +-nve0_fifo_oclass = &(struct nve0_fifo_impl) { +- .base.handle = NV_ENGINE(FIFO, 0xe0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_fifo_ctor, +- .dtor = nve0_fifo_dtor, +- .init = nve0_fifo_init, +- .fini = nve0_fifo_fini, +- }, +- .channels = 4096, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h b/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h +deleted file mode 100644 +index e96b32bb..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nve0.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-#ifndef __NVKM_FIFO_NVE0_H__ +-#define __NVKM_FIFO_NVE0_H__ +- +-#include +- +-int nve0_fifo_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nve0_fifo_dtor(struct nouveau_object *); +-int nve0_fifo_init(struct nouveau_object *); +-int nve0_fifo_fini(struct nouveau_object *, bool); +- +-struct nve0_fifo_impl { +- struct nouveau_oclass base; +- u32 channels; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h b/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h +deleted file mode 100644 +index e1947013..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctx.h ++++ /dev/null +@@ -1,129 +0,0 @@ +-#ifndef __NOUVEAU_GRCTX_H__ +-#define __NOUVEAU_GRCTX_H__ +- +-struct nouveau_grctx { +- struct nouveau_device *device; +- +- enum { +- NOUVEAU_GRCTX_PROG, +- NOUVEAU_GRCTX_VALS +- } mode; +- void *data; +- +- u32 ctxprog_max; +- u32 ctxprog_len; +- u32 ctxprog_reg; +- int ctxprog_label[32]; +- u32 ctxvals_pos; +- u32 ctxvals_base; +-}; +- +-static inline void +-cp_out(struct nouveau_grctx *ctx, u32 inst) +-{ +- u32 *ctxprog = ctx->data; +- +- if (ctx->mode != NOUVEAU_GRCTX_PROG) +- return; +- +- BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max); +- ctxprog[ctx->ctxprog_len++] = inst; +-} +- +-static inline void +-cp_lsr(struct nouveau_grctx *ctx, u32 val) +-{ +- cp_out(ctx, CP_LOAD_SR | val); +-} +- +-static inline void +-cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length) +-{ +- ctx->ctxprog_reg = (reg - 0x00400000) >> 2; +- +- ctx->ctxvals_base = ctx->ctxvals_pos; +- ctx->ctxvals_pos = ctx->ctxvals_base + length; +- +- if (length > (CP_CTX_COUNT >> CP_CTX_COUNT_SHIFT)) { +- cp_lsr(ctx, length); +- length = 0; +- } +- +- cp_out(ctx, CP_CTX | (length << CP_CTX_COUNT_SHIFT) | ctx->ctxprog_reg); +-} +- +-static inline void +-cp_name(struct nouveau_grctx *ctx, int name) +-{ +- u32 *ctxprog = ctx->data; +- int i; +- +- if (ctx->mode != NOUVEAU_GRCTX_PROG) +- return; +- +- ctx->ctxprog_label[name] = ctx->ctxprog_len; +- for (i = 0; i < ctx->ctxprog_len; i++) { +- if ((ctxprog[i] & 0xfff00000) != 0xff400000) +- continue; +- if ((ctxprog[i] & CP_BRA_IP) != ((name) << CP_BRA_IP_SHIFT)) +- continue; +- ctxprog[i] = (ctxprog[i] & 0x00ff00ff) | +- (ctx->ctxprog_len << CP_BRA_IP_SHIFT); +- } +-} +- +-static inline void +-_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name) +-{ +- int ip = 0; +- +- if (mod != 2) { +- ip = ctx->ctxprog_label[name] << CP_BRA_IP_SHIFT; +- if (ip == 0) +- ip = 0xff000000 | (name << CP_BRA_IP_SHIFT); +- } +- +- cp_out(ctx, CP_BRA | (mod << 18) | ip | flag | +- (state ? 0 : CP_BRA_IF_CLEAR)); +-} +-#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n) +-#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n) +-#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0) +- +-static inline void +-_cp_wait(struct nouveau_grctx *ctx, int flag, int state) +-{ +- cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0)); +-} +-#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s) +- +-static inline void +-_cp_set(struct nouveau_grctx *ctx, int flag, int state) +-{ +- cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0)); +-} +-#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s) +- +-static inline void +-cp_pos(struct nouveau_grctx *ctx, int offset) +-{ +- ctx->ctxvals_pos = offset; +- ctx->ctxvals_base = ctx->ctxvals_pos; +- +- cp_lsr(ctx, ctx->ctxvals_pos); +- cp_out(ctx, CP_SET_CONTEXT_POINTER); +-} +- +-static inline void +-gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val) +-{ +- if (ctx->mode != NOUVEAU_GRCTX_VALS) +- return; +- +- reg = (reg - 0x00400000) / 4; +- reg = (reg - ctx->ctxprog_reg) + ctx->ctxvals_base; +- +- nv_wo32(ctx->data, reg * 4, val); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c +deleted file mode 100644 +index 3adb7fe9..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk110b.c ++++ /dev/null +@@ -1,104 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-gk110b_grctx_init_sm_0[] = { +- { 0x419e04, 1, 0x04, 0x00000000 }, +- { 0x419e08, 1, 0x04, 0x0000001d }, +- { 0x419e0c, 1, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00001c02 }, +- { 0x419e44, 1, 0x04, 0x0013eff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000007f }, +- { 0x419e50, 2, 0x04, 0x00000000 }, +- { 0x419e58, 1, 0x04, 0x00000001 }, +- { 0x419e5c, 3, 0x04, 0x00000000 }, +- { 0x419e68, 1, 0x04, 0x00000002 }, +- { 0x419e6c, 12, 0x04, 0x00000000 }, +- { 0x419eac, 1, 0x04, 0x00001f8f }, +- { 0x419eb0, 1, 0x04, 0x0db00d2f }, +- { 0x419eb8, 1, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x0001304f }, +- { 0x419f30, 4, 0x04, 0x00000000 }, +- { 0x419f40, 1, 0x04, 0x00000018 }, +- { 0x419f44, 3, 0x04, 0x00000000 }, +- { 0x419f58, 1, 0x04, 0x00000000 }, +- { 0x419f70, 1, 0x04, 0x00006300 }, +- { 0x419f78, 1, 0x04, 0x000000eb }, +- { 0x419f7c, 1, 0x04, 0x00000404 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gk110b_grctx_pack_tpc[] = { +- { nvd7_grctx_init_pe_0 }, +- { nvf0_grctx_init_tex_0 }, +- { nvf0_grctx_init_mpc_0 }, +- { nvf0_grctx_init_l1c_0 }, +- { gk110b_grctx_init_sm_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-struct nouveau_oclass * +-gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xf1), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nve4_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = nvf0_grctx_pack_hub, +- .gpc = nvf0_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = gk110b_grctx_pack_tpc, +- .ppc = nvf0_grctx_pack_ppc, +- .icmd = nvf0_grctx_pack_icmd, +- .mthd = nvf0_grctx_pack_mthd, +- .bundle = nve4_grctx_generate_bundle, +- .bundle_size = 0x3000, +- .bundle_min_gpm_fifo_depth = 0x180, +- .bundle_token_limit = 0x600, +- .pagepool = nve4_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvd7_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x7ff, +- .alpha_nr = 0x648, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c +deleted file mode 100644 +index 36fc9831..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgk20a.c ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include "ctxnvc0.h" +- +-static const struct nvc0_graph_pack +-gk20a_grctx_pack_mthd[] = { +- { nve4_grctx_init_a097_0, 0xa297 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- {} +-}; +- +-struct nouveau_oclass * +-gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xea), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nve4_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = nve4_grctx_pack_hub, +- .gpc = nve4_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nve4_grctx_pack_tpc, +- .ppc = nve4_grctx_pack_ppc, +- .icmd = nve4_grctx_pack_icmd, +- .mthd = gk20a_grctx_pack_mthd, +- .bundle = nve4_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .bundle_min_gpm_fifo_depth = 0x62, +- .bundle_token_limit = 0x100, +- .pagepool = nve4_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvd7_grctx_generate_attrib, +- .attrib_nr_max = 0x240, +- .attrib_nr = 0x240, +- .alpha_nr_max = 0x648 + (0x648 / 2), +- .alpha_nr = 0x648, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c +deleted file mode 100644 +index 62e918b9..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxgm107.c ++++ /dev/null +@@ -1,1032 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-gm107_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x0000b1, 2, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000a8, 1, 0x01, 0x0000ffff }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002f2, 2, 0x01, 0x00000001 }, +- { 0x0002f5, 1, 0x01, 0x00000001 }, +- { 0x0002f7, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x0000de, 1, 0x01, 0x00000001 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000383, 1, 0x01, 0x00000011 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x0005d0, 1, 0x01, 0x20181008 }, +- { 0x0005d1, 1, 0x01, 0x40383028 }, +- { 0x0005d2, 1, 0x01, 0x60585048 }, +- { 0x0005d3, 1, 0x01, 0x80787068 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000550, 32, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x000595, 1, 0x01, 0x00400040 }, +- { 0x000596, 1, 0x01, 0x00000492 }, +- { 0x000597, 1, 0x01, 0x08080203 }, +- { 0x0005ad, 1, 0x01, 0x00000008 }, +- { 0x000598, 1, 0x01, 0x00020001 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000662, 1, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x000a0d, 1, 0x01, 0x00000006 }, +- { 0x00097d, 1, 0x01, 0x0000000c }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000687, 1, 0x01, 0x003fffff }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00400008 }, +- { 0x000841, 1, 0x01, 0x08000080 }, +- { 0x000842, 1, 0x01, 0x00400008 }, +- { 0x000843, 1, 0x01, 0x08000080 }, +- { 0x000818, 8, 0x01, 0x00000000 }, +- { 0x000848, 16, 0x01, 0x00000000 }, +- { 0x000738, 1, 0x01, 0x00000000 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000008 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000818, 8, 0x01, 0x00000000 }, +- { 0x000848, 16, 0x01, 0x00000000 }, +- { 0x000738, 1, 0x01, 0x00000000 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_grctx_pack_icmd[] = { +- { gm107_grctx_init_icmd_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_b097_0[] = { +- { 0x000800, 8, 0x40, 0x00000000 }, +- { 0x000804, 8, 0x40, 0x00000000 }, +- { 0x000808, 8, 0x40, 0x00000400 }, +- { 0x00080c, 8, 0x40, 0x00000300 }, +- { 0x000810, 1, 0x04, 0x000000cf }, +- { 0x000850, 7, 0x40, 0x00000000 }, +- { 0x000814, 8, 0x40, 0x00000040 }, +- { 0x000818, 8, 0x40, 0x00000001 }, +- { 0x00081c, 8, 0x40, 0x00000000 }, +- { 0x000820, 8, 0x40, 0x00000000 }, +- { 0x001c00, 16, 0x10, 0x00000000 }, +- { 0x001c04, 16, 0x10, 0x00000000 }, +- { 0x001c08, 16, 0x10, 0x00000000 }, +- { 0x001c0c, 16, 0x10, 0x00000000 }, +- { 0x001d00, 16, 0x10, 0x00000000 }, +- { 0x001d04, 16, 0x10, 0x00000000 }, +- { 0x001d08, 16, 0x10, 0x00000000 }, +- { 0x001d0c, 16, 0x10, 0x00000000 }, +- { 0x001f00, 16, 0x08, 0x00000000 }, +- { 0x001f04, 16, 0x08, 0x00000000 }, +- { 0x001f80, 16, 0x08, 0x00000000 }, +- { 0x001f84, 16, 0x08, 0x00000000 }, +- { 0x002000, 1, 0x04, 0x00000000 }, +- { 0x002040, 1, 0x04, 0x00000011 }, +- { 0x002080, 1, 0x04, 0x00000020 }, +- { 0x0020c0, 1, 0x04, 0x00000030 }, +- { 0x002100, 1, 0x04, 0x00000040 }, +- { 0x002140, 1, 0x04, 0x00000051 }, +- { 0x00200c, 6, 0x40, 0x00000001 }, +- { 0x002010, 1, 0x04, 0x00000000 }, +- { 0x002050, 1, 0x04, 0x00000000 }, +- { 0x002090, 1, 0x04, 0x00000001 }, +- { 0x0020d0, 1, 0x04, 0x00000002 }, +- { 0x002110, 1, 0x04, 0x00000003 }, +- { 0x002150, 1, 0x04, 0x00000004 }, +- { 0x000380, 4, 0x20, 0x00000000 }, +- { 0x000384, 4, 0x20, 0x00000000 }, +- { 0x000388, 4, 0x20, 0x00000000 }, +- { 0x00038c, 4, 0x20, 0x00000000 }, +- { 0x000700, 4, 0x10, 0x00000000 }, +- { 0x000704, 4, 0x10, 0x00000000 }, +- { 0x000708, 4, 0x10, 0x00000000 }, +- { 0x002800, 128, 0x04, 0x00000000 }, +- { 0x000a00, 16, 0x20, 0x00000000 }, +- { 0x000a04, 16, 0x20, 0x00000000 }, +- { 0x000a08, 16, 0x20, 0x00000000 }, +- { 0x000a0c, 16, 0x20, 0x00000000 }, +- { 0x000a10, 16, 0x20, 0x00000000 }, +- { 0x000a14, 16, 0x20, 0x00000000 }, +- { 0x000c00, 16, 0x10, 0x00000000 }, +- { 0x000c04, 16, 0x10, 0x00000000 }, +- { 0x000c08, 16, 0x10, 0x00000000 }, +- { 0x000c0c, 16, 0x10, 0x3f800000 }, +- { 0x000d00, 8, 0x08, 0xffff0000 }, +- { 0x000d04, 8, 0x08, 0xffff0000 }, +- { 0x000e00, 16, 0x10, 0x00000000 }, +- { 0x000e04, 16, 0x10, 0xffff0000 }, +- { 0x000e08, 16, 0x10, 0xffff0000 }, +- { 0x000d40, 4, 0x08, 0x00000000 }, +- { 0x000d44, 4, 0x08, 0x00000000 }, +- { 0x001e00, 8, 0x20, 0x00000001 }, +- { 0x001e04, 8, 0x20, 0x00000001 }, +- { 0x001e08, 8, 0x20, 0x00000002 }, +- { 0x001e0c, 8, 0x20, 0x00000001 }, +- { 0x001e10, 8, 0x20, 0x00000001 }, +- { 0x001e14, 8, 0x20, 0x00000002 }, +- { 0x001e18, 8, 0x20, 0x00000001 }, +- { 0x001480, 8, 0x10, 0x00000000 }, +- { 0x001484, 8, 0x10, 0x00000000 }, +- { 0x001488, 8, 0x10, 0x00000000 }, +- { 0x003400, 128, 0x04, 0x00000000 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x001514, 1, 0x04, 0x00000000 }, +- { 0x000d68, 1, 0x04, 0x0000ffff }, +- { 0x00121c, 1, 0x04, 0x0fac6881 }, +- { 0x000fac, 1, 0x04, 0x00000001 }, +- { 0x001538, 1, 0x04, 0x00000001 }, +- { 0x000fe0, 2, 0x04, 0x00000000 }, +- { 0x000fe8, 1, 0x04, 0x00000014 }, +- { 0x000fec, 1, 0x04, 0x00000040 }, +- { 0x000ff0, 1, 0x04, 0x00000000 }, +- { 0x00179c, 1, 0x04, 0x00000000 }, +- { 0x001228, 1, 0x04, 0x00000400 }, +- { 0x00122c, 1, 0x04, 0x00000300 }, +- { 0x001230, 1, 0x04, 0x00010001 }, +- { 0x0007f8, 1, 0x04, 0x00000000 }, +- { 0x0015b4, 1, 0x04, 0x00000001 }, +- { 0x0015cc, 1, 0x04, 0x00000000 }, +- { 0x001534, 1, 0x04, 0x00000000 }, +- { 0x000754, 1, 0x04, 0x00000001 }, +- { 0x000fb0, 1, 0x04, 0x00000000 }, +- { 0x0015d0, 1, 0x04, 0x00000000 }, +- { 0x00153c, 1, 0x04, 0x00000000 }, +- { 0x0016b4, 1, 0x04, 0x00000003 }, +- { 0x000fbc, 4, 0x04, 0x0000ffff }, +- { 0x000df8, 2, 0x04, 0x00000000 }, +- { 0x001948, 1, 0x04, 0x00000000 }, +- { 0x001970, 1, 0x04, 0x00000001 }, +- { 0x00161c, 1, 0x04, 0x000009f0 }, +- { 0x000dcc, 1, 0x04, 0x00000010 }, +- { 0x0015e4, 1, 0x04, 0x00000000 }, +- { 0x001160, 32, 0x04, 0x25e00040 }, +- { 0x001880, 32, 0x04, 0x00000000 }, +- { 0x000f84, 2, 0x04, 0x00000000 }, +- { 0x0017c8, 2, 0x04, 0x00000000 }, +- { 0x0017d0, 1, 0x04, 0x000000ff }, +- { 0x0017d4, 1, 0x04, 0xffffffff }, +- { 0x0017d8, 1, 0x04, 0x00000002 }, +- { 0x0017dc, 1, 0x04, 0x00000000 }, +- { 0x0015f4, 2, 0x04, 0x00000000 }, +- { 0x001434, 2, 0x04, 0x00000000 }, +- { 0x000d74, 1, 0x04, 0x00000000 }, +- { 0x0013a4, 1, 0x04, 0x00000000 }, +- { 0x001318, 1, 0x04, 0x00000001 }, +- { 0x001080, 2, 0x04, 0x00000000 }, +- { 0x001088, 2, 0x04, 0x00000001 }, +- { 0x001090, 1, 0x04, 0x00000000 }, +- { 0x001094, 1, 0x04, 0x00000001 }, +- { 0x001098, 1, 0x04, 0x00000000 }, +- { 0x00109c, 1, 0x04, 0x00000001 }, +- { 0x0010a0, 2, 0x04, 0x00000000 }, +- { 0x001644, 1, 0x04, 0x00000000 }, +- { 0x000748, 1, 0x04, 0x00000000 }, +- { 0x000de8, 1, 0x04, 0x00000000 }, +- { 0x001648, 1, 0x04, 0x00000000 }, +- { 0x0012a4, 1, 0x04, 0x00000000 }, +- { 0x001120, 4, 0x04, 0x00000000 }, +- { 0x001118, 1, 0x04, 0x00000000 }, +- { 0x00164c, 1, 0x04, 0x00000000 }, +- { 0x001658, 1, 0x04, 0x00000000 }, +- { 0x001910, 1, 0x04, 0x00000290 }, +- { 0x001518, 1, 0x04, 0x00000000 }, +- { 0x00165c, 1, 0x04, 0x00000001 }, +- { 0x001520, 1, 0x04, 0x00000000 }, +- { 0x001604, 1, 0x04, 0x00000000 }, +- { 0x001570, 1, 0x04, 0x00000000 }, +- { 0x0013b0, 2, 0x04, 0x3f800000 }, +- { 0x00020c, 1, 0x04, 0x00000000 }, +- { 0x001670, 1, 0x04, 0x30201000 }, +- { 0x001674, 1, 0x04, 0x70605040 }, +- { 0x001678, 1, 0x04, 0xb8a89888 }, +- { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, +- { 0x00166c, 1, 0x04, 0x00000000 }, +- { 0x001680, 1, 0x04, 0x00ffff00 }, +- { 0x0012d0, 1, 0x04, 0x00000003 }, +- { 0x0012d4, 1, 0x04, 0x00000002 }, +- { 0x001684, 2, 0x04, 0x00000000 }, +- { 0x000dac, 2, 0x04, 0x00001b02 }, +- { 0x000db4, 1, 0x04, 0x00000000 }, +- { 0x00168c, 1, 0x04, 0x00000000 }, +- { 0x0015bc, 1, 0x04, 0x00000000 }, +- { 0x00156c, 1, 0x04, 0x00000000 }, +- { 0x00187c, 1, 0x04, 0x00000000 }, +- { 0x001110, 1, 0x04, 0x00000001 }, +- { 0x000dc0, 3, 0x04, 0x00000000 }, +- { 0x000f40, 5, 0x04, 0x00000000 }, +- { 0x001234, 1, 0x04, 0x00000000 }, +- { 0x001690, 1, 0x04, 0x00000000 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x001000, 1, 0x04, 0x00000010 }, +- { 0x0010fc, 1, 0x04, 0x00000000 }, +- { 0x001290, 1, 0x04, 0x00000000 }, +- { 0x000218, 1, 0x04, 0x00000010 }, +- { 0x0012d8, 1, 0x04, 0x00000000 }, +- { 0x0012dc, 1, 0x04, 0x00000010 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x00155c, 2, 0x04, 0x00000000 }, +- { 0x001564, 1, 0x04, 0x00000fff }, +- { 0x001574, 2, 0x04, 0x00000000 }, +- { 0x00157c, 1, 0x04, 0x000fffff }, +- { 0x001354, 1, 0x04, 0x00000000 }, +- { 0x001610, 1, 0x04, 0x00000012 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x00260c, 1, 0x04, 0x00000000 }, +- { 0x0007ac, 1, 0x04, 0x00000000 }, +- { 0x00162c, 1, 0x04, 0x00000003 }, +- { 0x000210, 1, 0x04, 0x00000000 }, +- { 0x000320, 1, 0x04, 0x00000000 }, +- { 0x000324, 6, 0x04, 0x3f800000 }, +- { 0x000750, 1, 0x04, 0x00000000 }, +- { 0x000760, 1, 0x04, 0x39291909 }, +- { 0x000764, 1, 0x04, 0x79695949 }, +- { 0x000768, 1, 0x04, 0xb9a99989 }, +- { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x000770, 1, 0x04, 0x30201000 }, +- { 0x000774, 1, 0x04, 0x70605040 }, +- { 0x000778, 1, 0x04, 0x00009080 }, +- { 0x000780, 1, 0x04, 0x39291909 }, +- { 0x000784, 1, 0x04, 0x79695949 }, +- { 0x000788, 1, 0x04, 0xb9a99989 }, +- { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x0007d0, 1, 0x04, 0x30201000 }, +- { 0x0007d4, 1, 0x04, 0x70605040 }, +- { 0x0007d8, 1, 0x04, 0x00009080 }, +- { 0x00037c, 1, 0x04, 0x00000001 }, +- { 0x000740, 2, 0x04, 0x00000000 }, +- { 0x002600, 1, 0x04, 0x00000000 }, +- { 0x001918, 1, 0x04, 0x00000000 }, +- { 0x00191c, 1, 0x04, 0x00000900 }, +- { 0x001920, 1, 0x04, 0x00000405 }, +- { 0x001308, 1, 0x04, 0x00000001 }, +- { 0x001924, 1, 0x04, 0x00000000 }, +- { 0x0013ac, 1, 0x04, 0x00000000 }, +- { 0x00192c, 1, 0x04, 0x00000001 }, +- { 0x00193c, 1, 0x04, 0x00002c1c }, +- { 0x000d7c, 1, 0x04, 0x00000000 }, +- { 0x000f8c, 1, 0x04, 0x00000000 }, +- { 0x0002c0, 1, 0x04, 0x00000001 }, +- { 0x001510, 1, 0x04, 0x00000000 }, +- { 0x001940, 1, 0x04, 0x00000000 }, +- { 0x000ff4, 2, 0x04, 0x00000000 }, +- { 0x00194c, 2, 0x04, 0x00000000 }, +- { 0x001968, 1, 0x04, 0x00000000 }, +- { 0x001590, 1, 0x04, 0x0000003f }, +- { 0x0007e8, 4, 0x04, 0x00000000 }, +- { 0x00196c, 1, 0x04, 0x00000011 }, +- { 0x0002e4, 1, 0x04, 0x0000b001 }, +- { 0x00036c, 2, 0x04, 0x00000000 }, +- { 0x00197c, 1, 0x04, 0x00000000 }, +- { 0x000fcc, 2, 0x04, 0x00000000 }, +- { 0x0002d8, 1, 0x04, 0x00000040 }, +- { 0x001980, 1, 0x04, 0x00000080 }, +- { 0x001504, 1, 0x04, 0x00000080 }, +- { 0x001984, 1, 0x04, 0x00000000 }, +- { 0x000f60, 1, 0x04, 0x00000000 }, +- { 0x000f64, 1, 0x04, 0x00400040 }, +- { 0x000f68, 1, 0x04, 0x00002212 }, +- { 0x000f6c, 1, 0x04, 0x08080203 }, +- { 0x001108, 1, 0x04, 0x00000008 }, +- { 0x000f70, 1, 0x04, 0x00080001 }, +- { 0x000ffc, 1, 0x04, 0x00000000 }, +- { 0x000300, 1, 0x04, 0x00000001 }, +- { 0x0013a8, 1, 0x04, 0x00000000 }, +- { 0x0012ec, 1, 0x04, 0x00000000 }, +- { 0x001310, 1, 0x04, 0x00000000 }, +- { 0x001314, 1, 0x04, 0x00000001 }, +- { 0x001380, 1, 0x04, 0x00000000 }, +- { 0x001384, 4, 0x04, 0x00000001 }, +- { 0x001394, 1, 0x04, 0x00000000 }, +- { 0x00139c, 1, 0x04, 0x00000000 }, +- { 0x001398, 1, 0x04, 0x00000000 }, +- { 0x001594, 1, 0x04, 0x00000000 }, +- { 0x001598, 4, 0x04, 0x00000001 }, +- { 0x000f54, 3, 0x04, 0x00000000 }, +- { 0x0019bc, 1, 0x04, 0x00000000 }, +- { 0x000f9c, 2, 0x04, 0x00000000 }, +- { 0x0012cc, 1, 0x04, 0x00000000 }, +- { 0x0012e8, 1, 0x04, 0x00000000 }, +- { 0x00130c, 1, 0x04, 0x00000001 }, +- { 0x001360, 8, 0x04, 0x00000000 }, +- { 0x00133c, 2, 0x04, 0x00000001 }, +- { 0x001344, 1, 0x04, 0x00000002 }, +- { 0x001348, 2, 0x04, 0x00000001 }, +- { 0x001350, 1, 0x04, 0x00000002 }, +- { 0x001358, 1, 0x04, 0x00000001 }, +- { 0x0012e4, 1, 0x04, 0x00000000 }, +- { 0x00131c, 4, 0x04, 0x00000000 }, +- { 0x0019c0, 1, 0x04, 0x00000000 }, +- { 0x001140, 1, 0x04, 0x00000000 }, +- { 0x000dd0, 1, 0x04, 0x00000000 }, +- { 0x000dd4, 1, 0x04, 0x00000001 }, +- { 0x0002f4, 1, 0x04, 0x00000000 }, +- { 0x0019c4, 1, 0x04, 0x00000000 }, +- { 0x0019c8, 1, 0x04, 0x00001500 }, +- { 0x00135c, 1, 0x04, 0x00000000 }, +- { 0x000f90, 1, 0x04, 0x00000000 }, +- { 0x0019e0, 8, 0x04, 0x00000001 }, +- { 0x0019cc, 1, 0x04, 0x00000001 }, +- { 0x0015b8, 1, 0x04, 0x00000000 }, +- { 0x001a00, 1, 0x04, 0x00001111 }, +- { 0x001a04, 7, 0x04, 0x00000000 }, +- { 0x000d6c, 2, 0x04, 0xffff0000 }, +- { 0x0010f8, 1, 0x04, 0x00001010 }, +- { 0x000d80, 5, 0x04, 0x00000000 }, +- { 0x000da0, 1, 0x04, 0x00000000 }, +- { 0x0007a4, 2, 0x04, 0x00000000 }, +- { 0x001508, 1, 0x04, 0x80000000 }, +- { 0x00150c, 1, 0x04, 0x40000000 }, +- { 0x001668, 1, 0x04, 0x00000000 }, +- { 0x000318, 2, 0x04, 0x00000008 }, +- { 0x000d9c, 1, 0x04, 0x00000001 }, +- { 0x000f14, 1, 0x04, 0x00000000 }, +- { 0x000374, 1, 0x04, 0x00000000 }, +- { 0x000378, 1, 0x04, 0x0000000c }, +- { 0x0007dc, 1, 0x04, 0x00000000 }, +- { 0x00074c, 1, 0x04, 0x00000055 }, +- { 0x001420, 1, 0x04, 0x00000003 }, +- { 0x001008, 1, 0x04, 0x00000008 }, +- { 0x00100c, 1, 0x04, 0x00000040 }, +- { 0x001010, 1, 0x04, 0x0000012c }, +- { 0x000d60, 1, 0x04, 0x00000040 }, +- { 0x001018, 1, 0x04, 0x00000020 }, +- { 0x00101c, 1, 0x04, 0x00000001 }, +- { 0x001020, 1, 0x04, 0x00000020 }, +- { 0x001024, 1, 0x04, 0x00000001 }, +- { 0x001444, 3, 0x04, 0x00000000 }, +- { 0x000360, 1, 0x04, 0x20164010 }, +- { 0x000364, 1, 0x04, 0x00000020 }, +- { 0x000368, 1, 0x04, 0x00000000 }, +- { 0x000da8, 1, 0x04, 0x00000030 }, +- { 0x000de4, 1, 0x04, 0x00000000 }, +- { 0x000204, 1, 0x04, 0x00000006 }, +- { 0x0002d0, 1, 0x04, 0x003fffff }, +- { 0x001220, 1, 0x04, 0x00000005 }, +- { 0x000fdc, 1, 0x04, 0x00000000 }, +- { 0x000f98, 1, 0x04, 0x00400008 }, +- { 0x001284, 1, 0x04, 0x08000080 }, +- { 0x001450, 1, 0x04, 0x00400008 }, +- { 0x001454, 1, 0x04, 0x08000080 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_grctx_pack_mthd[] = { +- { gm107_grctx_init_b097_0, 0xb097 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_fe_0[] = { +- { 0x404004, 8, 0x04, 0x00000000 }, +- { 0x404024, 1, 0x04, 0x0000e000 }, +- { 0x404028, 8, 0x04, 0x00000000 }, +- { 0x4040a8, 8, 0x04, 0x00000000 }, +- { 0x4040c8, 1, 0x04, 0xf800008f }, +- { 0x4040d0, 6, 0x04, 0x00000000 }, +- { 0x4040f8, 1, 0x04, 0x00000000 }, +- { 0x404100, 10, 0x04, 0x00000000 }, +- { 0x404130, 2, 0x04, 0x00000000 }, +- { 0x404150, 1, 0x04, 0x0000002e }, +- { 0x404154, 1, 0x04, 0x00000400 }, +- { 0x404158, 1, 0x04, 0x00000200 }, +- { 0x404164, 1, 0x04, 0x00000045 }, +- { 0x40417c, 2, 0x04, 0x00000000 }, +- { 0x404194, 1, 0x04, 0x01000700 }, +- { 0x4041a0, 4, 0x04, 0x00000000 }, +- { 0x404200, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x0f8001bf }, +- { 0x405830, 1, 0x04, 0x0aa01000 }, +- { 0x405834, 1, 0x04, 0x08000000 }, +- { 0x405838, 1, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- { 0x405a1c, 1, 0x04, 0x000000ff }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x07410001 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b0, 3, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x80400280 }, +- { 0x4064c4, 1, 0x04, 0x0400ffff }, +- { 0x4064c8, 1, 0x04, 0x018001ff }, +- { 0x4064cc, 9, 0x04, 0x00000000 }, +- { 0x4064fc, 1, 0x04, 0x0000022a }, +- { 0x406500, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x32802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x1003e005 }, +- { 0x408840, 1, 0x04, 0x0000000b }, +- { 0x408900, 1, 0x04, 0xb080b801 }, +- { 0x408904, 1, 0x04, 0x63038001 }, +- { 0x408908, 1, 0x04, 0x02c8102f }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { gm107_grctx_init_fe_0 }, +- { nvf0_grctx_init_pri_0 }, +- { nve4_grctx_init_memfmt_0 }, +- { gm107_grctx_init_ds_0 }, +- { nvf0_grctx_init_cwd_0 }, +- { gm107_grctx_init_pd_0 }, +- { nv108_grctx_init_rstr2d_0 }, +- { nve4_grctx_init_scc_0 }, +- { gm107_grctx_init_be_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_gpc_unk_0[] = { +- { 0x418380, 1, 0x04, 0x00000056 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_gpc_unk_1[] = { +- { 0x418600, 1, 0x04, 0x0000007f }, +- { 0x418684, 1, 0x04, 0x0000001f }, +- { 0x418700, 1, 0x04, 0x00000002 }, +- { 0x418704, 1, 0x04, 0x00000080 }, +- { 0x418708, 1, 0x04, 0x40000000 }, +- { 0x41870c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x7006863a }, +- { 0x418810, 1, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00000044 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100058 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_gpc_unk_2[] = { +- { 0x418d24, 1, 0x04, 0x00000000 }, +- { 0x418e00, 1, 0x04, 0x90000000 }, +- { 0x418e24, 1, 0x04, 0x00000000 }, +- { 0x418e28, 1, 0x04, 0x00000030 }, +- { 0x418e30, 1, 0x04, 0x00000000 }, +- { 0x418e34, 1, 0x04, 0x00010000 }, +- { 0x418e38, 1, 0x04, 0x00000000 }, +- { 0x418e40, 22, 0x04, 0x00000000 }, +- { 0x418ea0, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_grctx_pack_gpc[] = { +- { gm107_grctx_init_gpc_unk_0 }, +- { nv108_grctx_init_prop_0 }, +- { gm107_grctx_init_gpc_unk_1 }, +- { gm107_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nv108_grctx_init_crstr_0 }, +- { nve4_grctx_init_gpm_0 }, +- { gm107_grctx_init_gpc_unk_2 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000300f0 }, +- { 0x419a04, 1, 0x04, 0x00000005 }, +- { 0x419a08, 1, 0x04, 0x00000421 }, +- { 0x419a0c, 1, 0x04, 0x00120000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00002200 }, +- { 0x419a1c, 1, 0x04, 0x0000c000 }, +- { 0x419a20, 1, 0x04, 0x20008a00 }, +- { 0x419a30, 1, 0x04, 0x00000001 }, +- { 0x419a3c, 1, 0x04, 0x00000002 }, +- { 0x419ac4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_mpc_0[] = { +- { 0x419c00, 1, 0x04, 0x0000001a }, +- { 0x419c04, 1, 0x04, 0x80000006 }, +- { 0x419c08, 1, 0x04, 0x00000002 }, +- { 0x419c20, 1, 0x04, 0x00000000 }, +- { 0x419c24, 1, 0x04, 0x00084210 }, +- { 0x419c28, 1, 0x04, 0x3efbefbe }, +- { 0x419c2c, 1, 0x04, 0x00000000 }, +- { 0x419c34, 1, 0x04, 0x01ff1ff3 }, +- { 0x419c3c, 1, 0x04, 0x00001919 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_l1c_0[] = { +- { 0x419c84, 1, 0x04, 0x00000020 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_sm_0[] = { +- { 0x419e04, 3, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00001c02 }, +- { 0x419e44, 1, 0x04, 0x00d3eff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000007f }, +- { 0x419e50, 1, 0x04, 0x00000000 }, +- { 0x419e60, 4, 0x04, 0x00000000 }, +- { 0x419e74, 10, 0x04, 0x00000000 }, +- { 0x419eac, 1, 0x04, 0x0001cf8b }, +- { 0x419eb0, 1, 0x04, 0x00030300 }, +- { 0x419eb8, 1, 0x04, 0x00000000 }, +- { 0x419ef0, 24, 0x04, 0x00000000 }, +- { 0x419f68, 2, 0x04, 0x00000000 }, +- { 0x419f70, 1, 0x04, 0x00000020 }, +- { 0x419f78, 1, 0x04, 0x000003eb }, +- { 0x419f7c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_grctx_pack_tpc[] = { +- { nvd7_grctx_init_pe_0 }, +- { gm107_grctx_init_tex_0 }, +- { gm107_grctx_init_mpc_0 }, +- { gm107_grctx_init_l1c_0 }, +- { gm107_grctx_init_sm_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_cbm_0[] = { +- { 0x41bec0, 1, 0x04, 0x00000000 }, +- { 0x41bec4, 1, 0x04, 0x01050000 }, +- { 0x41bee4, 1, 0x04, 0x00000000 }, +- { 0x41bef0, 1, 0x04, 0x000003ff }, +- { 0x41bef4, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_grctx_init_wwdx_0[] = { +- { 0x41bf00, 1, 0x04, 0x0a418820 }, +- { 0x41bf04, 1, 0x04, 0x062080e6 }, +- { 0x41bf08, 1, 0x04, 0x020398a4 }, +- { 0x41bf0c, 1, 0x04, 0x0e629062 }, +- { 0x41bf10, 1, 0x04, 0x0a418820 }, +- { 0x41bf14, 1, 0x04, 0x000000e6 }, +- { 0x41bfd0, 1, 0x04, 0x00900103 }, +- { 0x41bfe0, 1, 0x04, 0x80000000 }, +- { 0x41bfe4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_grctx_pack_ppc[] = { +- { nve4_grctx_init_pes_0 }, +- { gm107_grctx_init_cbm_0 }, +- { gm107_grctx_init_wwdx_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-static void +-gm107_grctx_generate_bundle(struct nvc0_grctx *info) +-{ +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); +- const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, +- impl->bundle_size / 0x20); +- const u32 token_limit = impl->bundle_token_limit; +- const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; +- const int s = 8; +- const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); +- mmio_refn(info, 0x408004, 0x00000000, s, b); +- mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); +- mmio_refn(info, 0x418e24, 0x00000000, s, b); +- mmio_refn(info, 0x418e28, 0x80000000 | (impl->bundle_size >> s), 0, b); +- mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); +-} +- +-static void +-gm107_grctx_generate_pagepool(struct nvc0_grctx *info) +-{ +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); +- const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; +- const int s = 8; +- const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); +- mmio_refn(info, 0x40800c, 0x00000000, s, b); +- mmio_wr32(info, 0x408010, 0x80000000); +- mmio_refn(info, 0x419004, 0x00000000, s, b); +- mmio_wr32(info, 0x419008, 0x00000000); +- mmio_wr32(info, 0x4064cc, 0x80000000); +- mmio_wr32(info, 0x418e30, 0x80000000); /* guess at it being related */ +-} +- +-static void +-gm107_grctx_generate_attrib(struct nvc0_grctx *info) +-{ +- struct nvc0_graph_priv *priv = info->priv; +- const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv); +- const u32 alpha = impl->alpha_nr; +- const u32 attrib = impl->attrib_nr; +- const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); +- const u32 access = NV_MEM_ACCESS_RW; +- const int s = 12; +- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); +- const int max_batches = 0xffff; +- u32 bo = 0; +- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; +- int gpc, ppc, n = 0; +- +- mmio_refn(info, 0x418810, 0x80000000, s, b); +- mmio_refn(info, 0x419848, 0x10000000, s, b); +- mmio_refn(info, 0x419c2c, 0x10000000, s, b); +- mmio_wr32(info, 0x405830, (attrib << 16) | alpha); +- mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++, n++) { +- const u32 as = alpha * priv->ppc_tpc_nr[gpc][ppc]; +- const u32 bs = attrib * priv->ppc_tpc_nr[gpc][ppc]; +- const u32 u = 0x418ea0 + (n * 0x04); +- const u32 o = PPC_UNIT(gpc, ppc, 0); +- mmio_wr32(info, o + 0xc0, bs); +- mmio_wr32(info, o + 0xf4, bo); +- bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; +- mmio_wr32(info, o + 0xe4, as); +- mmio_wr32(info, o + 0xf8, ao); +- ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; +- mmio_wr32(info, u, (0x715 /*XXX*/ << 16) | bs); +- } +- } +-} +- +-static void +-gm107_grctx_generate_tpcid(struct nvc0_graph_priv *priv) +-{ +- int gpc, tpc, id; +- +- for (tpc = 0, id = 0; tpc < 4; tpc++) { +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- if (tpc < priv->tpc_nr[gpc]) { +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); +- id++; +- } +- +- nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); +- } +- } +-} +- +-static void +-gm107_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +-{ +- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; +- int i; +- +- nvc0_graph_mmio(priv, oclass->hub); +- nvc0_graph_mmio(priv, oclass->gpc); +- nvc0_graph_mmio(priv, oclass->zcull); +- nvc0_graph_mmio(priv, oclass->tpc); +- nvc0_graph_mmio(priv, oclass->ppc); +- +- nv_wr32(priv, 0x404154, 0x00000000); +- +- oclass->bundle(info); +- oclass->pagepool(info); +- oclass->attrib(info); +- oclass->unkn(priv); +- +- gm107_grctx_generate_tpcid(priv); +- nvc0_grctx_generate_r406028(priv); +- nve4_grctx_generate_r418bb8(priv); +- nvc0_grctx_generate_r406800(priv); +- +- nv_wr32(priv, 0x4064d0, 0x00000001); +- for (i = 1; i < 8; i++) +- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); +- nv_wr32(priv, 0x406500, 0x00000001); +- +- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); +- +- if (priv->gpc_nr == 1) { +- nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); +- nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); +- } else { +- nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); +- nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); +- } +- +- nvc0_graph_icmd(priv, oclass->icmd); +- nv_wr32(priv, 0x404154, 0x00000400); +- nvc0_graph_mthd(priv, oclass->mthd); +- +- nv_mask(priv, 0x419e00, 0x00808080, 0x00808080); +- nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000); +- nv_mask(priv, 0x419f80, 0x80000000, 0x80000000); +- nv_mask(priv, 0x419f88, 0x80000000, 0x80000000); +-} +- +-struct nouveau_oclass * +-gm107_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0x08), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = gm107_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = gm107_grctx_pack_hub, +- .gpc = gm107_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = gm107_grctx_pack_tpc, +- .ppc = gm107_grctx_pack_ppc, +- .icmd = gm107_grctx_pack_icmd, +- .mthd = gm107_grctx_pack_mthd, +- .bundle = gm107_grctx_generate_bundle, +- .bundle_size = 0x3000, +- .bundle_min_gpm_fifo_depth = 0x180, +- .bundle_token_limit = 0x2c0, +- .pagepool = gm107_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = gm107_grctx_generate_attrib, +- .attrib_nr_max = 0xff0, +- .attrib_nr = 0xaa0, +- .alpha_nr_max = 0x1800, +- .alpha_nr = 0x1000, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c +deleted file mode 100644 +index ce252adb..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv108.c ++++ /dev/null +@@ -1,565 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nv108_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x0002f2, 2, 0x01, 0x00000001 }, +- { 0x0002f5, 1, 0x01, 0x00000001 }, +- { 0x0002f7, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000383, 1, 0x01, 0x00000011 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000662, 1, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x00080b, 1, 0x01, 0x00000002 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x000a0d, 1, 0x01, 0x00000006 }, +- { 0x00097d, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x003fffff }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00400008 }, +- { 0x000841, 1, 0x01, 0x08000080 }, +- { 0x000842, 1, 0x01, 0x00400008 }, +- { 0x000843, 1, 0x01, 0x08000080 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x00c500, 1, 0x01, 0x00000003 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000008 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x00c500, 1, 0x01, 0x00000003 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nv108_grctx_pack_icmd[] = { +- { nv108_grctx_init_icmd_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_fe_0[] = { +- { 0x404004, 8, 0x04, 0x00000000 }, +- { 0x404024, 1, 0x04, 0x0000e000 }, +- { 0x404028, 8, 0x04, 0x00000000 }, +- { 0x4040a8, 8, 0x04, 0x00000000 }, +- { 0x4040c8, 1, 0x04, 0xf800008f }, +- { 0x4040d0, 6, 0x04, 0x00000000 }, +- { 0x4040e8, 1, 0x04, 0x00001000 }, +- { 0x4040f8, 1, 0x04, 0x00000000 }, +- { 0x404100, 10, 0x04, 0x00000000 }, +- { 0x404130, 2, 0x04, 0x00000000 }, +- { 0x404138, 1, 0x04, 0x20000040 }, +- { 0x404150, 1, 0x04, 0x0000002e }, +- { 0x404154, 1, 0x04, 0x00000400 }, +- { 0x404158, 1, 0x04, 0x00000200 }, +- { 0x404164, 1, 0x04, 0x00000055 }, +- { 0x40417c, 2, 0x04, 0x00000000 }, +- { 0x404194, 1, 0x04, 0x01000700 }, +- { 0x4041a0, 4, 0x04, 0x00000000 }, +- { 0x404200, 1, 0x04, 0x0000a197 }, +- { 0x404204, 1, 0x04, 0x0000a1c0 }, +- { 0x404208, 1, 0x04, 0x0000a140 }, +- { 0x40420c, 1, 0x04, 0x0000902d }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x0f8000bf }, +- { 0x405830, 1, 0x04, 0x02180648 }, +- { 0x405834, 1, 0x04, 0x08000000 }, +- { 0x405838, 1, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- { 0x405a1c, 1, 0x04, 0x000000ff }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x034103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b0, 3, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x802000f0 }, +- { 0x4064c4, 1, 0x04, 0x0192ffff }, +- { 0x4064c8, 1, 0x04, 0x00c20200 }, +- { 0x4064cc, 9, 0x04, 0x00000000 }, +- { 0x4064fc, 1, 0x04, 0x0000022a }, +- {} +-}; +- +-const struct nvc0_graph_init +-nv108_grctx_init_rstr2d_0[] = { +- { 0x407804, 1, 0x04, 0x00000063 }, +- { 0x40780c, 1, 0x04, 0x0a418820 }, +- { 0x407810, 1, 0x04, 0x062080e6 }, +- { 0x407814, 1, 0x04, 0x020398a4 }, +- { 0x407818, 1, 0x04, 0x0e629062 }, +- { 0x40781c, 1, 0x04, 0x0a418820 }, +- { 0x407820, 1, 0x04, 0x000000e6 }, +- { 0x4078bc, 1, 0x04, 0x00000103 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x32802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x1003e005 }, +- { 0x408840, 1, 0x04, 0x0000000b }, +- { 0x408900, 1, 0x04, 0xb080b801 }, +- { 0x408904, 1, 0x04, 0x62000001 }, +- { 0x408908, 1, 0x04, 0x02c8102f }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nv108_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nv108_grctx_init_fe_0 }, +- { nvf0_grctx_init_pri_0 }, +- { nve4_grctx_init_memfmt_0 }, +- { nv108_grctx_init_ds_0 }, +- { nvf0_grctx_init_cwd_0 }, +- { nv108_grctx_init_pd_0 }, +- { nv108_grctx_init_rstr2d_0 }, +- { nve4_grctx_init_scc_0 }, +- { nv108_grctx_init_be_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nv108_grctx_init_prop_0[] = { +- { 0x418400, 1, 0x04, 0x38005e00 }, +- { 0x418404, 1, 0x04, 0x71e0ffff }, +- { 0x41840c, 1, 0x04, 0x00001008 }, +- { 0x418410, 1, 0x04, 0x0fff0fff }, +- { 0x418414, 1, 0x04, 0x02200fff }, +- { 0x418450, 6, 0x04, 0x00000000 }, +- { 0x418468, 1, 0x04, 0x00000001 }, +- { 0x41846c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_gpc_unk_1[] = { +- { 0x418600, 1, 0x04, 0x0000007f }, +- { 0x418684, 1, 0x04, 0x0000001f }, +- { 0x418700, 1, 0x04, 0x00000002 }, +- { 0x418704, 2, 0x04, 0x00000080 }, +- { 0x41870c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x7006863a }, +- { 0x418808, 1, 0x04, 0x00000000 }, +- { 0x41880c, 1, 0x04, 0x00000030 }, +- { 0x418810, 1, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00000044 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100058 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nv108_grctx_init_crstr_0[] = { +- { 0x418b00, 1, 0x04, 0x0000001e }, +- { 0x418b08, 1, 0x04, 0x0a418820 }, +- { 0x418b0c, 1, 0x04, 0x062080e6 }, +- { 0x418b10, 1, 0x04, 0x020398a4 }, +- { 0x418b14, 1, 0x04, 0x0e629062 }, +- { 0x418b18, 1, 0x04, 0x0a418820 }, +- { 0x418b1c, 1, 0x04, 0x000000e6 }, +- { 0x418bb8, 1, 0x04, 0x00000103 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_gpm_0[] = { +- { 0x418c08, 1, 0x04, 0x00000001 }, +- { 0x418c10, 8, 0x04, 0x00000000 }, +- { 0x418c40, 1, 0x04, 0xffffffff }, +- { 0x418c6c, 1, 0x04, 0x00000001 }, +- { 0x418c80, 1, 0x04, 0x2020000c }, +- { 0x418c8c, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nv108_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nv108_grctx_init_prop_0 }, +- { nv108_grctx_init_gpc_unk_1 }, +- { nv108_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nv108_grctx_init_crstr_0 }, +- { nv108_grctx_init_gpm_0 }, +- { nvf0_grctx_init_gpc_unk_2 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000100f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000421 }, +- { 0x419a0c, 1, 0x04, 0x00120000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- { 0x419a1c, 1, 0x04, 0x0000c000 }, +- { 0x419a20, 1, 0x04, 0x00000800 }, +- { 0x419a30, 1, 0x04, 0x00000001 }, +- { 0x419ac4, 1, 0x04, 0x0037f440 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_sm_0[] = { +- { 0x419e04, 1, 0x04, 0x00000000 }, +- { 0x419e08, 1, 0x04, 0x0000001d }, +- { 0x419e0c, 1, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00001c02 }, +- { 0x419e44, 1, 0x04, 0x0013eff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000007f }, +- { 0x419e50, 2, 0x04, 0x00000000 }, +- { 0x419e58, 1, 0x04, 0x00000001 }, +- { 0x419e5c, 3, 0x04, 0x00000000 }, +- { 0x419e68, 1, 0x04, 0x00000002 }, +- { 0x419e6c, 12, 0x04, 0x00000000 }, +- { 0x419eac, 1, 0x04, 0x00001f8f }, +- { 0x419eb0, 1, 0x04, 0x0db00d2f }, +- { 0x419eb8, 1, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x0001304f }, +- { 0x419f30, 4, 0x04, 0x00000000 }, +- { 0x419f40, 1, 0x04, 0x00000018 }, +- { 0x419f44, 3, 0x04, 0x00000000 }, +- { 0x419f58, 1, 0x04, 0x00000020 }, +- { 0x419f70, 1, 0x04, 0x00000000 }, +- { 0x419f78, 1, 0x04, 0x000001eb }, +- { 0x419f7c, 1, 0x04, 0x00000404 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nv108_grctx_pack_tpc[] = { +- { nvd7_grctx_init_pe_0 }, +- { nv108_grctx_init_tex_0 }, +- { nvf0_grctx_init_mpc_0 }, +- { nvf0_grctx_init_l1c_0 }, +- { nv108_grctx_init_sm_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_grctx_init_cbm_0[] = { +- { 0x41bec0, 1, 0x04, 0x10000000 }, +- { 0x41bec4, 1, 0x04, 0x00037f7f }, +- { 0x41bee4, 1, 0x04, 0x00000000 }, +- { 0x41bef0, 1, 0x04, 0x000003ff }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nv108_grctx_pack_ppc[] = { +- { nve4_grctx_init_pes_0 }, +- { nv108_grctx_init_cbm_0 }, +- { nvd7_grctx_init_wwdx_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nv108_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0x08), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nve4_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = nv108_grctx_pack_hub, +- .gpc = nv108_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nv108_grctx_pack_tpc, +- .ppc = nv108_grctx_pack_ppc, +- .icmd = nv108_grctx_pack_icmd, +- .mthd = nvf0_grctx_pack_mthd, +- .bundle = nve4_grctx_generate_bundle, +- .bundle_size = 0x3000, +- .bundle_min_gpm_fifo_depth = 0xc2, +- .bundle_token_limit = 0x200, +- .pagepool = nve4_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvd7_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x7ff, +- .alpha_nr = 0x648, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c +deleted file mode 100644 +index 7bbb1e1b..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv40.c ++++ /dev/null +@@ -1,695 +0,0 @@ +-/* +- * Copyright 2009 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-/* NVIDIA context programs handle a number of other conditions which are +- * not implemented in our versions. It's not clear why NVIDIA context +- * programs have this code, nor whether it's strictly necessary for +- * correct operation. We'll implement additional handling if/when we +- * discover it's necessary. +- * +- * - On context save, NVIDIA set 0x400314 bit 0 to 1 if the "3D state" +- * flag is set, this gets saved into the context. +- * - On context save, the context program for all cards load nsource +- * into a flag register and check for ILLEGAL_MTHD. If it's set, +- * opcode 0x60000d is called before resuming normal operation. +- * - Some context programs check more conditions than the above. NV44 +- * checks: ((nsource & 0x0857) || (0x400718 & 0x0100) || (intr & 0x0001)) +- * and calls 0x60000d before resuming normal operation. +- * - At the very beginning of NVIDIA's context programs, flag 9 is checked +- * and if true 0x800001 is called with count=0, pos=0, the flag is cleared +- * and then the ctxprog is aborted. It looks like a complicated NOP, +- * its purpose is unknown. +- * - In the section of code that loads the per-vs state, NVIDIA check +- * flag 10. If it's set, they only transfer the small 0x300 byte block +- * of state + the state for a single vs as opposed to the state for +- * all vs units. It doesn't seem likely that it'll occur in normal +- * operation, especially seeing as it appears NVIDIA may have screwed +- * up the ctxprogs for some cards and have an invalid instruction +- * rather than a cp_lsr(ctx, dwords_for_1_vs_unit) instruction. +- * - There's a number of places where context offset 0 (where we place +- * the PRAMIN offset of the context) is loaded into either 0x408000, +- * 0x408004 or 0x408008. Not sure what's up there either. +- * - The ctxprogs for some cards save 0x400a00 again during the cleanup +- * path for auto-loadctx. +- */ +- +-#define CP_FLAG_CLEAR 0 +-#define CP_FLAG_SET 1 +-#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) +-#define CP_FLAG_SWAP_DIRECTION_LOAD 0 +-#define CP_FLAG_SWAP_DIRECTION_SAVE 1 +-#define CP_FLAG_USER_SAVE ((0 * 32) + 5) +-#define CP_FLAG_USER_SAVE_NOT_PENDING 0 +-#define CP_FLAG_USER_SAVE_PENDING 1 +-#define CP_FLAG_USER_LOAD ((0 * 32) + 6) +-#define CP_FLAG_USER_LOAD_NOT_PENDING 0 +-#define CP_FLAG_USER_LOAD_PENDING 1 +-#define CP_FLAG_STATUS ((3 * 32) + 0) +-#define CP_FLAG_STATUS_IDLE 0 +-#define CP_FLAG_STATUS_BUSY 1 +-#define CP_FLAG_AUTO_SAVE ((3 * 32) + 4) +-#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 +-#define CP_FLAG_AUTO_SAVE_PENDING 1 +-#define CP_FLAG_AUTO_LOAD ((3 * 32) + 5) +-#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 +-#define CP_FLAG_AUTO_LOAD_PENDING 1 +-#define CP_FLAG_UNK54 ((3 * 32) + 6) +-#define CP_FLAG_UNK54_CLEAR 0 +-#define CP_FLAG_UNK54_SET 1 +-#define CP_FLAG_ALWAYS ((3 * 32) + 8) +-#define CP_FLAG_ALWAYS_FALSE 0 +-#define CP_FLAG_ALWAYS_TRUE 1 +-#define CP_FLAG_UNK57 ((3 * 32) + 9) +-#define CP_FLAG_UNK57_CLEAR 0 +-#define CP_FLAG_UNK57_SET 1 +- +-#define CP_CTX 0x00100000 +-#define CP_CTX_COUNT 0x000fc000 +-#define CP_CTX_COUNT_SHIFT 14 +-#define CP_CTX_REG 0x00003fff +-#define CP_LOAD_SR 0x00200000 +-#define CP_LOAD_SR_VALUE 0x000fffff +-#define CP_BRA 0x00400000 +-#define CP_BRA_IP 0x0000ff00 +-#define CP_BRA_IP_SHIFT 8 +-#define CP_BRA_IF_CLEAR 0x00000080 +-#define CP_BRA_FLAG 0x0000007f +-#define CP_WAIT 0x00500000 +-#define CP_WAIT_SET 0x00000080 +-#define CP_WAIT_FLAG 0x0000007f +-#define CP_SET 0x00700000 +-#define CP_SET_1 0x00000080 +-#define CP_SET_FLAG 0x0000007f +-#define CP_NEXT_TO_SWAP 0x00600007 +-#define CP_NEXT_TO_CURRENT 0x00600009 +-#define CP_SET_CONTEXT_POINTER 0x0060000a +-#define CP_END 0x0060000e +-#define CP_LOAD_MAGIC_UNK01 0x00800001 /* unknown */ +-#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */ +-#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */ +- +-#include "nv40.h" +-#include "ctx.h" +- +-/* TODO: +- * - get vs count from 0x1540 +- */ +- +-static int +-nv40_graph_vs_count(struct nouveau_device *device) +-{ +- +- switch (device->chipset) { +- case 0x47: +- case 0x49: +- case 0x4b: +- return 8; +- case 0x40: +- return 6; +- case 0x41: +- case 0x42: +- return 5; +- case 0x43: +- case 0x44: +- case 0x46: +- case 0x4a: +- return 3; +- case 0x4c: +- case 0x4e: +- case 0x67: +- default: +- return 1; +- } +-} +- +- +-enum cp_label { +- cp_check_load = 1, +- cp_setup_auto_load, +- cp_setup_load, +- cp_setup_save, +- cp_swap_state, +- cp_swap_state3d_3_is_save, +- cp_prepare_exit, +- cp_exit, +-}; +- +-static void +-nv40_graph_construct_general(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- +- cp_ctx(ctx, 0x4000a4, 1); +- gr_def(ctx, 0x4000a4, 0x00000008); +- cp_ctx(ctx, 0x400144, 58); +- gr_def(ctx, 0x400144, 0x00000001); +- cp_ctx(ctx, 0x400314, 1); +- gr_def(ctx, 0x400314, 0x00000000); +- cp_ctx(ctx, 0x400400, 10); +- cp_ctx(ctx, 0x400480, 10); +- cp_ctx(ctx, 0x400500, 19); +- gr_def(ctx, 0x400514, 0x00040000); +- gr_def(ctx, 0x400524, 0x55555555); +- gr_def(ctx, 0x400528, 0x55555555); +- gr_def(ctx, 0x40052c, 0x55555555); +- gr_def(ctx, 0x400530, 0x55555555); +- cp_ctx(ctx, 0x400560, 6); +- gr_def(ctx, 0x400568, 0x0000ffff); +- gr_def(ctx, 0x40056c, 0x0000ffff); +- cp_ctx(ctx, 0x40057c, 5); +- cp_ctx(ctx, 0x400710, 3); +- gr_def(ctx, 0x400710, 0x20010001); +- gr_def(ctx, 0x400714, 0x0f73ef00); +- cp_ctx(ctx, 0x400724, 1); +- gr_def(ctx, 0x400724, 0x02008821); +- cp_ctx(ctx, 0x400770, 3); +- if (device->chipset == 0x40) { +- cp_ctx(ctx, 0x400814, 4); +- cp_ctx(ctx, 0x400828, 5); +- cp_ctx(ctx, 0x400840, 5); +- gr_def(ctx, 0x400850, 0x00000040); +- cp_ctx(ctx, 0x400858, 4); +- gr_def(ctx, 0x400858, 0x00000040); +- gr_def(ctx, 0x40085c, 0x00000040); +- gr_def(ctx, 0x400864, 0x80000000); +- cp_ctx(ctx, 0x40086c, 9); +- gr_def(ctx, 0x40086c, 0x80000000); +- gr_def(ctx, 0x400870, 0x80000000); +- gr_def(ctx, 0x400874, 0x80000000); +- gr_def(ctx, 0x400878, 0x80000000); +- gr_def(ctx, 0x400888, 0x00000040); +- gr_def(ctx, 0x40088c, 0x80000000); +- cp_ctx(ctx, 0x4009c0, 8); +- gr_def(ctx, 0x4009cc, 0x80000000); +- gr_def(ctx, 0x4009dc, 0x80000000); +- } else { +- cp_ctx(ctx, 0x400840, 20); +- if (nv44_graph_class(ctx->device)) { +- for (i = 0; i < 8; i++) +- gr_def(ctx, 0x400860 + (i * 4), 0x00000001); +- } +- gr_def(ctx, 0x400880, 0x00000040); +- gr_def(ctx, 0x400884, 0x00000040); +- gr_def(ctx, 0x400888, 0x00000040); +- cp_ctx(ctx, 0x400894, 11); +- gr_def(ctx, 0x400894, 0x00000040); +- if (!nv44_graph_class(ctx->device)) { +- for (i = 0; i < 8; i++) +- gr_def(ctx, 0x4008a0 + (i * 4), 0x80000000); +- } +- cp_ctx(ctx, 0x4008e0, 2); +- cp_ctx(ctx, 0x4008f8, 2); +- if (device->chipset == 0x4c || +- (device->chipset & 0xf0) == 0x60) +- cp_ctx(ctx, 0x4009f8, 1); +- } +- cp_ctx(ctx, 0x400a00, 73); +- gr_def(ctx, 0x400b0c, 0x0b0b0b0c); +- cp_ctx(ctx, 0x401000, 4); +- cp_ctx(ctx, 0x405004, 1); +- switch (device->chipset) { +- case 0x47: +- case 0x49: +- case 0x4b: +- cp_ctx(ctx, 0x403448, 1); +- gr_def(ctx, 0x403448, 0x00001010); +- break; +- default: +- cp_ctx(ctx, 0x403440, 1); +- switch (device->chipset) { +- case 0x40: +- gr_def(ctx, 0x403440, 0x00000010); +- break; +- case 0x44: +- case 0x46: +- case 0x4a: +- gr_def(ctx, 0x403440, 0x00003010); +- break; +- case 0x41: +- case 0x42: +- case 0x43: +- case 0x4c: +- case 0x4e: +- case 0x67: +- default: +- gr_def(ctx, 0x403440, 0x00001010); +- break; +- } +- break; +- } +-} +- +-static void +-nv40_graph_construct_state3d(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- +- if (device->chipset == 0x40) { +- cp_ctx(ctx, 0x401880, 51); +- gr_def(ctx, 0x401940, 0x00000100); +- } else +- if (device->chipset == 0x46 || device->chipset == 0x47 || +- device->chipset == 0x49 || device->chipset == 0x4b) { +- cp_ctx(ctx, 0x401880, 32); +- for (i = 0; i < 16; i++) +- gr_def(ctx, 0x401880 + (i * 4), 0x00000111); +- if (device->chipset == 0x46) +- cp_ctx(ctx, 0x401900, 16); +- cp_ctx(ctx, 0x401940, 3); +- } +- cp_ctx(ctx, 0x40194c, 18); +- gr_def(ctx, 0x401954, 0x00000111); +- gr_def(ctx, 0x401958, 0x00080060); +- gr_def(ctx, 0x401974, 0x00000080); +- gr_def(ctx, 0x401978, 0xffff0000); +- gr_def(ctx, 0x40197c, 0x00000001); +- gr_def(ctx, 0x401990, 0x46400000); +- if (device->chipset == 0x40) { +- cp_ctx(ctx, 0x4019a0, 2); +- cp_ctx(ctx, 0x4019ac, 5); +- } else { +- cp_ctx(ctx, 0x4019a0, 1); +- cp_ctx(ctx, 0x4019b4, 3); +- } +- gr_def(ctx, 0x4019bc, 0xffff0000); +- switch (device->chipset) { +- case 0x46: +- case 0x47: +- case 0x49: +- case 0x4b: +- cp_ctx(ctx, 0x4019c0, 18); +- for (i = 0; i < 16; i++) +- gr_def(ctx, 0x4019c0 + (i * 4), 0x88888888); +- break; +- } +- cp_ctx(ctx, 0x401a08, 8); +- gr_def(ctx, 0x401a10, 0x0fff0000); +- gr_def(ctx, 0x401a14, 0x0fff0000); +- gr_def(ctx, 0x401a1c, 0x00011100); +- cp_ctx(ctx, 0x401a2c, 4); +- cp_ctx(ctx, 0x401a44, 26); +- for (i = 0; i < 16; i++) +- gr_def(ctx, 0x401a44 + (i * 4), 0x07ff0000); +- gr_def(ctx, 0x401a8c, 0x4b7fffff); +- if (device->chipset == 0x40) { +- cp_ctx(ctx, 0x401ab8, 3); +- } else { +- cp_ctx(ctx, 0x401ab8, 1); +- cp_ctx(ctx, 0x401ac0, 1); +- } +- cp_ctx(ctx, 0x401ad0, 8); +- gr_def(ctx, 0x401ad0, 0x30201000); +- gr_def(ctx, 0x401ad4, 0x70605040); +- gr_def(ctx, 0x401ad8, 0xb8a89888); +- gr_def(ctx, 0x401adc, 0xf8e8d8c8); +- cp_ctx(ctx, 0x401b10, device->chipset == 0x40 ? 2 : 1); +- gr_def(ctx, 0x401b10, 0x40100000); +- cp_ctx(ctx, 0x401b18, device->chipset == 0x40 ? 6 : 5); +- gr_def(ctx, 0x401b28, device->chipset == 0x40 ? +- 0x00000004 : 0x00000000); +- cp_ctx(ctx, 0x401b30, 25); +- gr_def(ctx, 0x401b34, 0x0000ffff); +- gr_def(ctx, 0x401b68, 0x435185d6); +- gr_def(ctx, 0x401b6c, 0x2155b699); +- gr_def(ctx, 0x401b70, 0xfedcba98); +- gr_def(ctx, 0x401b74, 0x00000098); +- gr_def(ctx, 0x401b84, 0xffffffff); +- gr_def(ctx, 0x401b88, 0x00ff7000); +- gr_def(ctx, 0x401b8c, 0x0000ffff); +- if (device->chipset != 0x44 && device->chipset != 0x4a && +- device->chipset != 0x4e) +- cp_ctx(ctx, 0x401b94, 1); +- cp_ctx(ctx, 0x401b98, 8); +- gr_def(ctx, 0x401b9c, 0x00ff0000); +- cp_ctx(ctx, 0x401bc0, 9); +- gr_def(ctx, 0x401be0, 0x00ffff00); +- cp_ctx(ctx, 0x401c00, 192); +- for (i = 0; i < 16; i++) { /* fragment texture units */ +- gr_def(ctx, 0x401c40 + (i * 4), 0x00018488); +- gr_def(ctx, 0x401c80 + (i * 4), 0x00028202); +- gr_def(ctx, 0x401d00 + (i * 4), 0x0000aae4); +- gr_def(ctx, 0x401d40 + (i * 4), 0x01012000); +- gr_def(ctx, 0x401d80 + (i * 4), 0x00080008); +- gr_def(ctx, 0x401e00 + (i * 4), 0x00100008); +- } +- for (i = 0; i < 4; i++) { /* vertex texture units */ +- gr_def(ctx, 0x401e90 + (i * 4), 0x0001bc80); +- gr_def(ctx, 0x401ea0 + (i * 4), 0x00000202); +- gr_def(ctx, 0x401ec0 + (i * 4), 0x00000008); +- gr_def(ctx, 0x401ee0 + (i * 4), 0x00080008); +- } +- cp_ctx(ctx, 0x400f5c, 3); +- gr_def(ctx, 0x400f5c, 0x00000002); +- cp_ctx(ctx, 0x400f84, 1); +-} +- +-static void +-nv40_graph_construct_state3d_2(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- +- cp_ctx(ctx, 0x402000, 1); +- cp_ctx(ctx, 0x402404, device->chipset == 0x40 ? 1 : 2); +- switch (device->chipset) { +- case 0x40: +- gr_def(ctx, 0x402404, 0x00000001); +- break; +- case 0x4c: +- case 0x4e: +- case 0x67: +- gr_def(ctx, 0x402404, 0x00000020); +- break; +- case 0x46: +- case 0x49: +- case 0x4b: +- gr_def(ctx, 0x402404, 0x00000421); +- break; +- default: +- gr_def(ctx, 0x402404, 0x00000021); +- } +- if (device->chipset != 0x40) +- gr_def(ctx, 0x402408, 0x030c30c3); +- switch (device->chipset) { +- case 0x44: +- case 0x46: +- case 0x4a: +- case 0x4c: +- case 0x4e: +- case 0x67: +- cp_ctx(ctx, 0x402440, 1); +- gr_def(ctx, 0x402440, 0x00011001); +- break; +- default: +- break; +- } +- cp_ctx(ctx, 0x402480, device->chipset == 0x40 ? 8 : 9); +- gr_def(ctx, 0x402488, 0x3e020200); +- gr_def(ctx, 0x40248c, 0x00ffffff); +- switch (device->chipset) { +- case 0x40: +- gr_def(ctx, 0x402490, 0x60103f00); +- break; +- case 0x47: +- gr_def(ctx, 0x402490, 0x40103f00); +- break; +- case 0x41: +- case 0x42: +- case 0x49: +- case 0x4b: +- gr_def(ctx, 0x402490, 0x20103f00); +- break; +- default: +- gr_def(ctx, 0x402490, 0x0c103f00); +- break; +- } +- gr_def(ctx, 0x40249c, device->chipset <= 0x43 ? +- 0x00020000 : 0x00040000); +- cp_ctx(ctx, 0x402500, 31); +- gr_def(ctx, 0x402530, 0x00008100); +- if (device->chipset == 0x40) +- cp_ctx(ctx, 0x40257c, 6); +- cp_ctx(ctx, 0x402594, 16); +- cp_ctx(ctx, 0x402800, 17); +- gr_def(ctx, 0x402800, 0x00000001); +- switch (device->chipset) { +- case 0x47: +- case 0x49: +- case 0x4b: +- cp_ctx(ctx, 0x402864, 1); +- gr_def(ctx, 0x402864, 0x00001001); +- cp_ctx(ctx, 0x402870, 3); +- gr_def(ctx, 0x402878, 0x00000003); +- if (device->chipset != 0x47) { /* belong at end!! */ +- cp_ctx(ctx, 0x402900, 1); +- cp_ctx(ctx, 0x402940, 1); +- cp_ctx(ctx, 0x402980, 1); +- cp_ctx(ctx, 0x4029c0, 1); +- cp_ctx(ctx, 0x402a00, 1); +- cp_ctx(ctx, 0x402a40, 1); +- cp_ctx(ctx, 0x402a80, 1); +- cp_ctx(ctx, 0x402ac0, 1); +- } +- break; +- case 0x40: +- cp_ctx(ctx, 0x402844, 1); +- gr_def(ctx, 0x402844, 0x00000001); +- cp_ctx(ctx, 0x402850, 1); +- break; +- default: +- cp_ctx(ctx, 0x402844, 1); +- gr_def(ctx, 0x402844, 0x00001001); +- cp_ctx(ctx, 0x402850, 2); +- gr_def(ctx, 0x402854, 0x00000003); +- break; +- } +- +- cp_ctx(ctx, 0x402c00, 4); +- gr_def(ctx, 0x402c00, device->chipset == 0x40 ? +- 0x80800001 : 0x00888001); +- switch (device->chipset) { +- case 0x47: +- case 0x49: +- case 0x4b: +- cp_ctx(ctx, 0x402c20, 40); +- for (i = 0; i < 32; i++) +- gr_def(ctx, 0x402c40 + (i * 4), 0xffffffff); +- cp_ctx(ctx, 0x4030b8, 13); +- gr_def(ctx, 0x4030dc, 0x00000005); +- gr_def(ctx, 0x4030e8, 0x0000ffff); +- break; +- default: +- cp_ctx(ctx, 0x402c10, 4); +- if (device->chipset == 0x40) +- cp_ctx(ctx, 0x402c20, 36); +- else +- if (device->chipset <= 0x42) +- cp_ctx(ctx, 0x402c20, 24); +- else +- if (device->chipset <= 0x4a) +- cp_ctx(ctx, 0x402c20, 16); +- else +- cp_ctx(ctx, 0x402c20, 8); +- cp_ctx(ctx, 0x402cb0, device->chipset == 0x40 ? 12 : 13); +- gr_def(ctx, 0x402cd4, 0x00000005); +- if (device->chipset != 0x40) +- gr_def(ctx, 0x402ce0, 0x0000ffff); +- break; +- } +- +- cp_ctx(ctx, 0x403400, device->chipset == 0x40 ? 4 : 3); +- cp_ctx(ctx, 0x403410, device->chipset == 0x40 ? 4 : 3); +- cp_ctx(ctx, 0x403420, nv40_graph_vs_count(ctx->device)); +- for (i = 0; i < nv40_graph_vs_count(ctx->device); i++) +- gr_def(ctx, 0x403420 + (i * 4), 0x00005555); +- +- if (device->chipset != 0x40) { +- cp_ctx(ctx, 0x403600, 1); +- gr_def(ctx, 0x403600, 0x00000001); +- } +- cp_ctx(ctx, 0x403800, 1); +- +- cp_ctx(ctx, 0x403c18, 1); +- gr_def(ctx, 0x403c18, 0x00000001); +- switch (device->chipset) { +- case 0x46: +- case 0x47: +- case 0x49: +- case 0x4b: +- cp_ctx(ctx, 0x405018, 1); +- gr_def(ctx, 0x405018, 0x08e00001); +- cp_ctx(ctx, 0x405c24, 1); +- gr_def(ctx, 0x405c24, 0x000e3000); +- break; +- } +- if (device->chipset != 0x4e) +- cp_ctx(ctx, 0x405800, 11); +- cp_ctx(ctx, 0x407000, 1); +-} +- +-static void +-nv40_graph_construct_state3d_3(struct nouveau_grctx *ctx) +-{ +- int len = nv44_graph_class(ctx->device) ? 0x0084 : 0x0684; +- +- cp_out (ctx, 0x300000); +- cp_lsr (ctx, len - 4); +- cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_swap_state3d_3_is_save); +- cp_lsr (ctx, len); +- cp_name(ctx, cp_swap_state3d_3_is_save); +- cp_out (ctx, 0x800001); +- +- ctx->ctxvals_pos += len; +-} +- +-static void +-nv40_graph_construct_shader(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- struct nouveau_gpuobj *obj = ctx->data; +- int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset; +- int offset, i; +- +- vs_nr = nv40_graph_vs_count(ctx->device); +- vs_nr_b0 = 363; +- vs_nr_b1 = device->chipset == 0x40 ? 128 : 64; +- if (device->chipset == 0x40) { +- b0_offset = 0x2200/4; /* 33a0 */ +- b1_offset = 0x55a0/4; /* 1500 */ +- vs_len = 0x6aa0/4; +- } else +- if (device->chipset == 0x41 || device->chipset == 0x42) { +- b0_offset = 0x2200/4; /* 2200 */ +- b1_offset = 0x4400/4; /* 0b00 */ +- vs_len = 0x4f00/4; +- } else { +- b0_offset = 0x1d40/4; /* 2200 */ +- b1_offset = 0x3f40/4; /* 0b00 : 0a40 */ +- vs_len = nv44_graph_class(device) ? 0x4980/4 : 0x4a40/4; +- } +- +- cp_lsr(ctx, vs_len * vs_nr + 0x300/4); +- cp_out(ctx, nv44_graph_class(device) ? 0x800029 : 0x800041); +- +- offset = ctx->ctxvals_pos; +- ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len)); +- +- if (ctx->mode != NOUVEAU_GRCTX_VALS) +- return; +- +- offset += 0x0280/4; +- for (i = 0; i < 16; i++, offset += 2) +- nv_wo32(obj, offset * 4, 0x3f800000); +- +- for (vs = 0; vs < vs_nr; vs++, offset += vs_len) { +- for (i = 0; i < vs_nr_b0 * 6; i += 6) +- nv_wo32(obj, (offset + b0_offset + i) * 4, 0x00000001); +- for (i = 0; i < vs_nr_b1 * 4; i += 4) +- nv_wo32(obj, (offset + b1_offset + i) * 4, 0x3f800000); +- } +-} +- +-static void +-nv40_grctx_generate(struct nouveau_grctx *ctx) +-{ +- /* decide whether we're loading/unloading the context */ +- cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); +- cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); +- +- cp_name(ctx, cp_check_load); +- cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); +- cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); +- cp_bra (ctx, ALWAYS, TRUE, cp_exit); +- +- /* setup for context load */ +- cp_name(ctx, cp_setup_auto_load); +- cp_wait(ctx, STATUS, IDLE); +- cp_out (ctx, CP_NEXT_TO_SWAP); +- cp_name(ctx, cp_setup_load); +- cp_wait(ctx, STATUS, IDLE); +- cp_set (ctx, SWAP_DIRECTION, LOAD); +- cp_out (ctx, 0x00910880); /* ?? */ +- cp_out (ctx, 0x00901ffe); /* ?? */ +- cp_out (ctx, 0x01940000); /* ?? */ +- cp_lsr (ctx, 0x20); +- cp_out (ctx, 0x0060000b); /* ?? */ +- cp_wait(ctx, UNK57, CLEAR); +- cp_out (ctx, 0x0060000c); /* ?? */ +- cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); +- +- /* setup for context save */ +- cp_name(ctx, cp_setup_save); +- cp_set (ctx, SWAP_DIRECTION, SAVE); +- +- /* general PGRAPH state */ +- cp_name(ctx, cp_swap_state); +- cp_pos (ctx, 0x00020/4); +- nv40_graph_construct_general(ctx); +- cp_wait(ctx, STATUS, IDLE); +- +- /* 3D state, block 1 */ +- cp_bra (ctx, UNK54, CLEAR, cp_prepare_exit); +- nv40_graph_construct_state3d(ctx); +- cp_wait(ctx, STATUS, IDLE); +- +- /* 3D state, block 2 */ +- nv40_graph_construct_state3d_2(ctx); +- +- /* Some other block of "random" state */ +- nv40_graph_construct_state3d_3(ctx); +- +- /* Per-vertex shader state */ +- cp_pos (ctx, ctx->ctxvals_pos); +- nv40_graph_construct_shader(ctx); +- +- /* pre-exit state updates */ +- cp_name(ctx, cp_prepare_exit); +- cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); +- cp_bra (ctx, USER_SAVE, PENDING, cp_exit); +- cp_out (ctx, CP_NEXT_TO_CURRENT); +- +- cp_name(ctx, cp_exit); +- cp_set (ctx, USER_SAVE, NOT_PENDING); +- cp_set (ctx, USER_LOAD, NOT_PENDING); +- cp_out (ctx, CP_END); +-} +- +-void +-nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) +-{ +- nv40_grctx_generate(&(struct nouveau_grctx) { +- .device = device, +- .mode = NOUVEAU_GRCTX_VALS, +- .data = mem, +- }); +-} +- +-int +-nv40_grctx_init(struct nouveau_device *device, u32 *size) +-{ +- u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i; +- struct nouveau_grctx ctx = { +- .device = device, +- .mode = NOUVEAU_GRCTX_PROG, +- .data = ctxprog, +- .ctxprog_max = 256, +- }; +- +- if (!ctxprog) +- return -ENOMEM; +- +- nv40_grctx_generate(&ctx); +- +- nv_wr32(device, 0x400324, 0); +- for (i = 0; i < ctx.ctxprog_len; i++) +- nv_wr32(device, 0x400328, ctxprog[i]); +- *size = ctx.ctxvals_pos * 4; +- +- kfree(ctxprog); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c +deleted file mode 100644 +index 1d0e33fb..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnv50.c ++++ /dev/null +@@ -1,3347 +0,0 @@ +-/* +- * Copyright 2009 Marcin Kościelnicki +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-#define CP_FLAG_CLEAR 0 +-#define CP_FLAG_SET 1 +-#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) +-#define CP_FLAG_SWAP_DIRECTION_LOAD 0 +-#define CP_FLAG_SWAP_DIRECTION_SAVE 1 +-#define CP_FLAG_UNK01 ((0 * 32) + 1) +-#define CP_FLAG_UNK01_CLEAR 0 +-#define CP_FLAG_UNK01_SET 1 +-#define CP_FLAG_UNK03 ((0 * 32) + 3) +-#define CP_FLAG_UNK03_CLEAR 0 +-#define CP_FLAG_UNK03_SET 1 +-#define CP_FLAG_USER_SAVE ((0 * 32) + 5) +-#define CP_FLAG_USER_SAVE_NOT_PENDING 0 +-#define CP_FLAG_USER_SAVE_PENDING 1 +-#define CP_FLAG_USER_LOAD ((0 * 32) + 6) +-#define CP_FLAG_USER_LOAD_NOT_PENDING 0 +-#define CP_FLAG_USER_LOAD_PENDING 1 +-#define CP_FLAG_UNK0B ((0 * 32) + 0xb) +-#define CP_FLAG_UNK0B_CLEAR 0 +-#define CP_FLAG_UNK0B_SET 1 +-#define CP_FLAG_XFER_SWITCH ((0 * 32) + 0xe) +-#define CP_FLAG_XFER_SWITCH_DISABLE 0 +-#define CP_FLAG_XFER_SWITCH_ENABLE 1 +-#define CP_FLAG_STATE ((0 * 32) + 0x1c) +-#define CP_FLAG_STATE_STOPPED 0 +-#define CP_FLAG_STATE_RUNNING 1 +-#define CP_FLAG_UNK1D ((0 * 32) + 0x1d) +-#define CP_FLAG_UNK1D_CLEAR 0 +-#define CP_FLAG_UNK1D_SET 1 +-#define CP_FLAG_UNK20 ((1 * 32) + 0) +-#define CP_FLAG_UNK20_CLEAR 0 +-#define CP_FLAG_UNK20_SET 1 +-#define CP_FLAG_STATUS ((2 * 32) + 0) +-#define CP_FLAG_STATUS_BUSY 0 +-#define CP_FLAG_STATUS_IDLE 1 +-#define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) +-#define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 +-#define CP_FLAG_AUTO_SAVE_PENDING 1 +-#define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) +-#define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 +-#define CP_FLAG_AUTO_LOAD_PENDING 1 +-#define CP_FLAG_NEWCTX ((2 * 32) + 10) +-#define CP_FLAG_NEWCTX_BUSY 0 +-#define CP_FLAG_NEWCTX_DONE 1 +-#define CP_FLAG_XFER ((2 * 32) + 11) +-#define CP_FLAG_XFER_IDLE 0 +-#define CP_FLAG_XFER_BUSY 1 +-#define CP_FLAG_ALWAYS ((2 * 32) + 13) +-#define CP_FLAG_ALWAYS_FALSE 0 +-#define CP_FLAG_ALWAYS_TRUE 1 +-#define CP_FLAG_INTR ((2 * 32) + 15) +-#define CP_FLAG_INTR_NOT_PENDING 0 +-#define CP_FLAG_INTR_PENDING 1 +- +-#define CP_CTX 0x00100000 +-#define CP_CTX_COUNT 0x000f0000 +-#define CP_CTX_COUNT_SHIFT 16 +-#define CP_CTX_REG 0x00003fff +-#define CP_LOAD_SR 0x00200000 +-#define CP_LOAD_SR_VALUE 0x000fffff +-#define CP_BRA 0x00400000 +-#define CP_BRA_IP 0x0001ff00 +-#define CP_BRA_IP_SHIFT 8 +-#define CP_BRA_IF_CLEAR 0x00000080 +-#define CP_BRA_FLAG 0x0000007f +-#define CP_WAIT 0x00500000 +-#define CP_WAIT_SET 0x00000080 +-#define CP_WAIT_FLAG 0x0000007f +-#define CP_SET 0x00700000 +-#define CP_SET_1 0x00000080 +-#define CP_SET_FLAG 0x0000007f +-#define CP_NEWCTX 0x00600004 +-#define CP_NEXT_TO_SWAP 0x00600005 +-#define CP_SET_CONTEXT_POINTER 0x00600006 +-#define CP_SET_XFER_POINTER 0x00600007 +-#define CP_ENABLE 0x00600009 +-#define CP_END 0x0060000c +-#define CP_NEXT_TO_CURRENT 0x0060000d +-#define CP_DISABLE1 0x0090ffff +-#define CP_DISABLE2 0x0091ffff +-#define CP_XFER_1 0x008000ff +-#define CP_XFER_2 0x008800ff +-#define CP_SEEK_1 0x00c000ff +-#define CP_SEEK_2 0x00c800ff +- +-#include "nv50.h" +-#include "ctx.h" +- +-#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf) +-#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac) +- +-#include +- +-/* +- * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's +- * the GPU itself that does context-switching, but it needs a special +- * microcode to do it. And it's the driver's task to supply this microcode, +- * further known as ctxprog, as well as the initial context values, known +- * as ctxvals. +- * +- * Without ctxprog, you cannot switch contexts. Not even in software, since +- * the majority of context [xfer strands] isn't accessible directly. You're +- * stuck with a single channel, and you also suffer all the problems resulting +- * from missing ctxvals, since you cannot load them. +- * +- * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to +- * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, +- * since you don't have... some sort of needed setup. +- * +- * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since +- * it's too much hassle to handle no-ctxprog as a special case. +- */ +- +-/* +- * How ctxprogs work. +- * +- * The ctxprog is written in its own kind of microcode, with very small and +- * crappy set of available commands. You upload it to a small [512 insns] +- * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to +- * switch channel. or when the driver explicitely requests it. Stuff visible +- * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, +- * the per-channel context save area in VRAM [known as ctxvals or grctx], +- * 4 flags registers, a scratch register, two grctx pointers, plus many +- * random poorly-understood details. +- * +- * When ctxprog runs, it's supposed to check what operations are asked of it, +- * save old context if requested, optionally reset PGRAPH and switch to the +- * new channel, and load the new context. Context consists of three major +- * parts: subset of MMIO registers and two "xfer areas". +- */ +- +-/* TODO: +- * - document unimplemented bits compared to nvidia +- * - NVAx: make a TP subroutine, use it. +- * - use 0x4008fc instead of 0x1540? +- */ +- +-enum cp_label { +- cp_check_load = 1, +- cp_setup_auto_load, +- cp_setup_load, +- cp_setup_save, +- cp_swap_state, +- cp_prepare_exit, +- cp_exit, +-}; +- +-static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx); +- +-/* Main function: construct the ctxprog skeleton, call the other functions. */ +- +-static int +-nv50_grctx_generate(struct nouveau_grctx *ctx) +-{ +- cp_set (ctx, STATE, RUNNING); +- cp_set (ctx, XFER_SWITCH, ENABLE); +- /* decide whether we're loading/unloading the context */ +- cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); +- cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); +- +- cp_name(ctx, cp_check_load); +- cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); +- cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); +- cp_bra (ctx, ALWAYS, TRUE, cp_prepare_exit); +- +- /* setup for context load */ +- cp_name(ctx, cp_setup_auto_load); +- cp_out (ctx, CP_DISABLE1); +- cp_out (ctx, CP_DISABLE2); +- cp_out (ctx, CP_ENABLE); +- cp_out (ctx, CP_NEXT_TO_SWAP); +- cp_set (ctx, UNK01, SET); +- cp_name(ctx, cp_setup_load); +- cp_out (ctx, CP_NEWCTX); +- cp_wait(ctx, NEWCTX, BUSY); +- cp_set (ctx, UNK1D, CLEAR); +- cp_set (ctx, SWAP_DIRECTION, LOAD); +- cp_bra (ctx, UNK0B, SET, cp_prepare_exit); +- cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); +- +- /* setup for context save */ +- cp_name(ctx, cp_setup_save); +- cp_set (ctx, UNK1D, SET); +- cp_wait(ctx, STATUS, BUSY); +- cp_wait(ctx, INTR, PENDING); +- cp_bra (ctx, STATUS, BUSY, cp_setup_save); +- cp_set (ctx, UNK01, SET); +- cp_set (ctx, SWAP_DIRECTION, SAVE); +- +- /* general PGRAPH state */ +- cp_name(ctx, cp_swap_state); +- cp_set (ctx, UNK03, SET); +- cp_pos (ctx, 0x00004/4); +- cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ +- cp_pos (ctx, 0x00100/4); +- nv50_graph_construct_mmio(ctx); +- nv50_graph_construct_xfer1(ctx); +- nv50_graph_construct_xfer2(ctx); +- +- cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); +- +- cp_set (ctx, UNK20, SET); +- cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ +- cp_lsr (ctx, ctx->ctxvals_base); +- cp_out (ctx, CP_SET_XFER_POINTER); +- cp_lsr (ctx, 4); +- cp_out (ctx, CP_SEEK_1); +- cp_out (ctx, CP_XFER_1); +- cp_wait(ctx, XFER, BUSY); +- +- /* pre-exit state updates */ +- cp_name(ctx, cp_prepare_exit); +- cp_set (ctx, UNK01, CLEAR); +- cp_set (ctx, UNK03, CLEAR); +- cp_set (ctx, UNK1D, CLEAR); +- +- cp_bra (ctx, USER_SAVE, PENDING, cp_exit); +- cp_out (ctx, CP_NEXT_TO_CURRENT); +- +- cp_name(ctx, cp_exit); +- cp_set (ctx, USER_SAVE, NOT_PENDING); +- cp_set (ctx, USER_LOAD, NOT_PENDING); +- cp_set (ctx, XFER_SWITCH, DISABLE); +- cp_set (ctx, STATE, STOPPED); +- cp_out (ctx, CP_END); +- ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ +- +- return 0; +-} +- +-void +-nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem) +-{ +- nv50_grctx_generate(&(struct nouveau_grctx) { +- .device = device, +- .mode = NOUVEAU_GRCTX_VALS, +- .data = mem, +- }); +-} +- +-int +-nv50_grctx_init(struct nouveau_device *device, u32 *size) +-{ +- u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i; +- struct nouveau_grctx ctx = { +- .device = device, +- .mode = NOUVEAU_GRCTX_PROG, +- .data = ctxprog, +- .ctxprog_max = 512, +- }; +- +- if (!ctxprog) +- return -ENOMEM; +- nv50_grctx_generate(&ctx); +- +- nv_wr32(device, 0x400324, 0); +- for (i = 0; i < ctx.ctxprog_len; i++) +- nv_wr32(device, 0x400328, ctxprog[i]); +- *size = ctx.ctxvals_pos * 4; +- kfree(ctxprog); +- return 0; +-} +- +-/* +- * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which +- * registers to save/restore and the default values for them. +- */ +- +-static void +-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx); +- +-static void +-nv50_graph_construct_mmio(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i, j; +- int offset, base; +- u32 units = nv_rd32 (ctx->device, 0x1540); +- +- /* 0800: DISPATCH */ +- cp_ctx(ctx, 0x400808, 7); +- gr_def(ctx, 0x400814, 0x00000030); +- cp_ctx(ctx, 0x400834, 0x32); +- if (device->chipset == 0x50) { +- gr_def(ctx, 0x400834, 0xff400040); +- gr_def(ctx, 0x400838, 0xfff00080); +- gr_def(ctx, 0x40083c, 0xfff70090); +- gr_def(ctx, 0x400840, 0xffe806a8); +- } +- gr_def(ctx, 0x400844, 0x00000002); +- if (IS_NVA3F(device->chipset)) +- gr_def(ctx, 0x400894, 0x00001000); +- gr_def(ctx, 0x4008e8, 0x00000003); +- gr_def(ctx, 0x4008ec, 0x00001000); +- if (device->chipset == 0x50) +- cp_ctx(ctx, 0x400908, 0xb); +- else if (device->chipset < 0xa0) +- cp_ctx(ctx, 0x400908, 0xc); +- else +- cp_ctx(ctx, 0x400908, 0xe); +- +- if (device->chipset >= 0xa0) +- cp_ctx(ctx, 0x400b00, 0x1); +- if (IS_NVA3F(device->chipset)) { +- cp_ctx(ctx, 0x400b10, 0x1); +- gr_def(ctx, 0x400b10, 0x0001629d); +- cp_ctx(ctx, 0x400b20, 0x1); +- gr_def(ctx, 0x400b20, 0x0001629d); +- } +- +- nv50_graph_construct_mmio_ddata(ctx); +- +- /* 0C00: VFETCH */ +- cp_ctx(ctx, 0x400c08, 0x2); +- gr_def(ctx, 0x400c08, 0x0000fe0c); +- +- /* 1000 */ +- if (device->chipset < 0xa0) { +- cp_ctx(ctx, 0x401008, 0x4); +- gr_def(ctx, 0x401014, 0x00001000); +- } else if (!IS_NVA3F(device->chipset)) { +- cp_ctx(ctx, 0x401008, 0x5); +- gr_def(ctx, 0x401018, 0x00001000); +- } else { +- cp_ctx(ctx, 0x401008, 0x5); +- gr_def(ctx, 0x401018, 0x00004000); +- } +- +- /* 1400 */ +- cp_ctx(ctx, 0x401400, 0x8); +- cp_ctx(ctx, 0x401424, 0x3); +- if (device->chipset == 0x50) +- gr_def(ctx, 0x40142c, 0x0001fd87); +- else +- gr_def(ctx, 0x40142c, 0x00000187); +- cp_ctx(ctx, 0x401540, 0x5); +- gr_def(ctx, 0x401550, 0x00001018); +- +- /* 1800: STREAMOUT */ +- cp_ctx(ctx, 0x401814, 0x1); +- gr_def(ctx, 0x401814, 0x000000ff); +- if (device->chipset == 0x50) { +- cp_ctx(ctx, 0x40181c, 0xe); +- gr_def(ctx, 0x401850, 0x00000004); +- } else if (device->chipset < 0xa0) { +- cp_ctx(ctx, 0x40181c, 0xf); +- gr_def(ctx, 0x401854, 0x00000004); +- } else { +- cp_ctx(ctx, 0x40181c, 0x13); +- gr_def(ctx, 0x401864, 0x00000004); +- } +- +- /* 1C00 */ +- cp_ctx(ctx, 0x401c00, 0x1); +- switch (device->chipset) { +- case 0x50: +- gr_def(ctx, 0x401c00, 0x0001005f); +- break; +- case 0x84: +- case 0x86: +- case 0x94: +- gr_def(ctx, 0x401c00, 0x044d00df); +- break; +- case 0x92: +- case 0x96: +- case 0x98: +- case 0xa0: +- case 0xaa: +- case 0xac: +- gr_def(ctx, 0x401c00, 0x042500df); +- break; +- case 0xa3: +- case 0xa5: +- case 0xa8: +- case 0xaf: +- gr_def(ctx, 0x401c00, 0x142500df); +- break; +- } +- +- /* 2000 */ +- +- /* 2400 */ +- cp_ctx(ctx, 0x402400, 0x1); +- if (device->chipset == 0x50) +- cp_ctx(ctx, 0x402408, 0x1); +- else +- cp_ctx(ctx, 0x402408, 0x2); +- gr_def(ctx, 0x402408, 0x00000600); +- +- /* 2800: CSCHED */ +- cp_ctx(ctx, 0x402800, 0x1); +- if (device->chipset == 0x50) +- gr_def(ctx, 0x402800, 0x00000006); +- +- /* 2C00: ZCULL */ +- cp_ctx(ctx, 0x402c08, 0x6); +- if (device->chipset != 0x50) +- gr_def(ctx, 0x402c14, 0x01000000); +- gr_def(ctx, 0x402c18, 0x000000ff); +- if (device->chipset == 0x50) +- cp_ctx(ctx, 0x402ca0, 0x1); +- else +- cp_ctx(ctx, 0x402ca0, 0x2); +- if (device->chipset < 0xa0) +- gr_def(ctx, 0x402ca0, 0x00000400); +- else if (!IS_NVA3F(device->chipset)) +- gr_def(ctx, 0x402ca0, 0x00000800); +- else +- gr_def(ctx, 0x402ca0, 0x00000400); +- cp_ctx(ctx, 0x402cac, 0x4); +- +- /* 3000: ENG2D */ +- cp_ctx(ctx, 0x403004, 0x1); +- gr_def(ctx, 0x403004, 0x00000001); +- +- /* 3400 */ +- if (device->chipset >= 0xa0) { +- cp_ctx(ctx, 0x403404, 0x1); +- gr_def(ctx, 0x403404, 0x00000001); +- } +- +- /* 5000: CCACHE */ +- cp_ctx(ctx, 0x405000, 0x1); +- switch (device->chipset) { +- case 0x50: +- gr_def(ctx, 0x405000, 0x00300080); +- break; +- case 0x84: +- case 0xa0: +- case 0xa3: +- case 0xa5: +- case 0xa8: +- case 0xaa: +- case 0xac: +- case 0xaf: +- gr_def(ctx, 0x405000, 0x000e0080); +- break; +- case 0x86: +- case 0x92: +- case 0x94: +- case 0x96: +- case 0x98: +- gr_def(ctx, 0x405000, 0x00000080); +- break; +- } +- cp_ctx(ctx, 0x405014, 0x1); +- gr_def(ctx, 0x405014, 0x00000004); +- cp_ctx(ctx, 0x40501c, 0x1); +- cp_ctx(ctx, 0x405024, 0x1); +- cp_ctx(ctx, 0x40502c, 0x1); +- +- /* 6000? */ +- if (device->chipset == 0x50) +- cp_ctx(ctx, 0x4063e0, 0x1); +- +- /* 6800: M2MF */ +- if (device->chipset < 0x90) { +- cp_ctx(ctx, 0x406814, 0x2b); +- gr_def(ctx, 0x406818, 0x00000f80); +- gr_def(ctx, 0x406860, 0x007f0080); +- gr_def(ctx, 0x40689c, 0x007f0080); +- } else { +- cp_ctx(ctx, 0x406814, 0x4); +- if (device->chipset == 0x98) +- gr_def(ctx, 0x406818, 0x00000f80); +- else +- gr_def(ctx, 0x406818, 0x00001f80); +- if (IS_NVA3F(device->chipset)) +- gr_def(ctx, 0x40681c, 0x00000030); +- cp_ctx(ctx, 0x406830, 0x3); +- } +- +- /* 7000: per-ROP group state */ +- for (i = 0; i < 8; i++) { +- if (units & (1<<(i+16))) { +- cp_ctx(ctx, 0x407000 + (i<<8), 3); +- if (device->chipset == 0x50) +- gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); +- else if (device->chipset != 0xa5) +- gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); +- else +- gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); +- gr_def(ctx, 0x407004 + (i<<8), 0x89058001); +- +- if (device->chipset == 0x50) { +- cp_ctx(ctx, 0x407010 + (i<<8), 1); +- } else if (device->chipset < 0xa0) { +- cp_ctx(ctx, 0x407010 + (i<<8), 2); +- gr_def(ctx, 0x407010 + (i<<8), 0x00001000); +- gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); +- } else { +- cp_ctx(ctx, 0x407010 + (i<<8), 3); +- gr_def(ctx, 0x407010 + (i<<8), 0x00001000); +- if (device->chipset != 0xa5) +- gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); +- else +- gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); +- } +- +- cp_ctx(ctx, 0x407080 + (i<<8), 4); +- if (device->chipset != 0xa5) +- gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); +- else +- gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); +- if (device->chipset == 0x50) +- gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); +- else +- gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); +- gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); +- +- if (device->chipset < 0xa0) +- cp_ctx(ctx, 0x407094 + (i<<8), 1); +- else if (!IS_NVA3F(device->chipset)) +- cp_ctx(ctx, 0x407094 + (i<<8), 3); +- else { +- cp_ctx(ctx, 0x407094 + (i<<8), 4); +- gr_def(ctx, 0x4070a0 + (i<<8), 1); +- } +- } +- } +- +- cp_ctx(ctx, 0x407c00, 0x3); +- if (device->chipset < 0x90) +- gr_def(ctx, 0x407c00, 0x00010040); +- else if (device->chipset < 0xa0) +- gr_def(ctx, 0x407c00, 0x00390040); +- else +- gr_def(ctx, 0x407c00, 0x003d0040); +- gr_def(ctx, 0x407c08, 0x00000022); +- if (device->chipset >= 0xa0) { +- cp_ctx(ctx, 0x407c10, 0x3); +- cp_ctx(ctx, 0x407c20, 0x1); +- cp_ctx(ctx, 0x407c2c, 0x1); +- } +- +- if (device->chipset < 0xa0) { +- cp_ctx(ctx, 0x407d00, 0x9); +- } else { +- cp_ctx(ctx, 0x407d00, 0x15); +- } +- if (device->chipset == 0x98) +- gr_def(ctx, 0x407d08, 0x00380040); +- else { +- if (device->chipset < 0x90) +- gr_def(ctx, 0x407d08, 0x00010040); +- else if (device->chipset < 0xa0) +- gr_def(ctx, 0x407d08, 0x00390040); +- else { +- if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5) +- gr_def(ctx, 0x407d08, 0x003d0040); +- else +- gr_def(ctx, 0x407d08, 0x003c0040); +- } +- gr_def(ctx, 0x407d0c, 0x00000022); +- } +- +- /* 8000+: per-TP state */ +- for (i = 0; i < 10; i++) { +- if (units & (1<chipset < 0xa0) +- base = 0x408000 + (i<<12); +- else +- base = 0x408000 + (i<<11); +- if (device->chipset < 0xa0) +- offset = base + 0xc00; +- else +- offset = base + 0x80; +- cp_ctx(ctx, offset + 0x00, 1); +- gr_def(ctx, offset + 0x00, 0x0000ff0a); +- cp_ctx(ctx, offset + 0x08, 1); +- +- /* per-MP state */ +- for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) { +- if (!(units & (1 << (j+24)))) continue; +- if (device->chipset < 0xa0) +- offset = base + 0x200 + (j<<7); +- else +- offset = base + 0x100 + (j<<7); +- cp_ctx(ctx, offset, 0x20); +- gr_def(ctx, offset + 0x00, 0x01800000); +- gr_def(ctx, offset + 0x04, 0x00160000); +- gr_def(ctx, offset + 0x08, 0x01800000); +- gr_def(ctx, offset + 0x18, 0x0003ffff); +- switch (device->chipset) { +- case 0x50: +- gr_def(ctx, offset + 0x1c, 0x00080000); +- break; +- case 0x84: +- gr_def(ctx, offset + 0x1c, 0x00880000); +- break; +- case 0x86: +- gr_def(ctx, offset + 0x1c, 0x018c0000); +- break; +- case 0x92: +- case 0x96: +- case 0x98: +- gr_def(ctx, offset + 0x1c, 0x118c0000); +- break; +- case 0x94: +- gr_def(ctx, offset + 0x1c, 0x10880000); +- break; +- case 0xa0: +- case 0xa5: +- gr_def(ctx, offset + 0x1c, 0x310c0000); +- break; +- case 0xa3: +- case 0xa8: +- case 0xaa: +- case 0xac: +- case 0xaf: +- gr_def(ctx, offset + 0x1c, 0x300c0000); +- break; +- } +- gr_def(ctx, offset + 0x40, 0x00010401); +- if (device->chipset == 0x50) +- gr_def(ctx, offset + 0x48, 0x00000040); +- else +- gr_def(ctx, offset + 0x48, 0x00000078); +- gr_def(ctx, offset + 0x50, 0x000000bf); +- gr_def(ctx, offset + 0x58, 0x00001210); +- if (device->chipset == 0x50) +- gr_def(ctx, offset + 0x5c, 0x00000080); +- else +- gr_def(ctx, offset + 0x5c, 0x08000080); +- if (device->chipset >= 0xa0) +- gr_def(ctx, offset + 0x68, 0x0000003e); +- } +- +- if (device->chipset < 0xa0) +- cp_ctx(ctx, base + 0x300, 0x4); +- else +- cp_ctx(ctx, base + 0x300, 0x5); +- if (device->chipset == 0x50) +- gr_def(ctx, base + 0x304, 0x00007070); +- else if (device->chipset < 0xa0) +- gr_def(ctx, base + 0x304, 0x00027070); +- else if (!IS_NVA3F(device->chipset)) +- gr_def(ctx, base + 0x304, 0x01127070); +- else +- gr_def(ctx, base + 0x304, 0x05127070); +- +- if (device->chipset < 0xa0) +- cp_ctx(ctx, base + 0x318, 1); +- else +- cp_ctx(ctx, base + 0x320, 1); +- if (device->chipset == 0x50) +- gr_def(ctx, base + 0x318, 0x0003ffff); +- else if (device->chipset < 0xa0) +- gr_def(ctx, base + 0x318, 0x03ffffff); +- else +- gr_def(ctx, base + 0x320, 0x07ffffff); +- +- if (device->chipset < 0xa0) +- cp_ctx(ctx, base + 0x324, 5); +- else +- cp_ctx(ctx, base + 0x328, 4); +- +- if (device->chipset < 0xa0) { +- cp_ctx(ctx, base + 0x340, 9); +- offset = base + 0x340; +- } else if (!IS_NVA3F(device->chipset)) { +- cp_ctx(ctx, base + 0x33c, 0xb); +- offset = base + 0x344; +- } else { +- cp_ctx(ctx, base + 0x33c, 0xd); +- offset = base + 0x344; +- } +- gr_def(ctx, offset + 0x0, 0x00120407); +- gr_def(ctx, offset + 0x4, 0x05091507); +- if (device->chipset == 0x84) +- gr_def(ctx, offset + 0x8, 0x05100202); +- else +- gr_def(ctx, offset + 0x8, 0x05010202); +- gr_def(ctx, offset + 0xc, 0x00030201); +- if (device->chipset == 0xa3) +- cp_ctx(ctx, base + 0x36c, 1); +- +- cp_ctx(ctx, base + 0x400, 2); +- gr_def(ctx, base + 0x404, 0x00000040); +- cp_ctx(ctx, base + 0x40c, 2); +- gr_def(ctx, base + 0x40c, 0x0d0c0b0a); +- gr_def(ctx, base + 0x410, 0x00141210); +- +- if (device->chipset < 0xa0) +- offset = base + 0x800; +- else +- offset = base + 0x500; +- cp_ctx(ctx, offset, 6); +- gr_def(ctx, offset + 0x0, 0x000001f0); +- gr_def(ctx, offset + 0x4, 0x00000001); +- gr_def(ctx, offset + 0x8, 0x00000003); +- if (device->chipset == 0x50 || IS_NVAAF(device->chipset)) +- gr_def(ctx, offset + 0xc, 0x00008000); +- gr_def(ctx, offset + 0x14, 0x00039e00); +- cp_ctx(ctx, offset + 0x1c, 2); +- if (device->chipset == 0x50) +- gr_def(ctx, offset + 0x1c, 0x00000040); +- else +- gr_def(ctx, offset + 0x1c, 0x00000100); +- gr_def(ctx, offset + 0x20, 0x00003800); +- +- if (device->chipset >= 0xa0) { +- cp_ctx(ctx, base + 0x54c, 2); +- if (!IS_NVA3F(device->chipset)) +- gr_def(ctx, base + 0x54c, 0x003fe006); +- else +- gr_def(ctx, base + 0x54c, 0x003fe007); +- gr_def(ctx, base + 0x550, 0x003fe000); +- } +- +- if (device->chipset < 0xa0) +- offset = base + 0xa00; +- else +- offset = base + 0x680; +- cp_ctx(ctx, offset, 1); +- gr_def(ctx, offset, 0x00404040); +- +- if (device->chipset < 0xa0) +- offset = base + 0xe00; +- else +- offset = base + 0x700; +- cp_ctx(ctx, offset, 2); +- if (device->chipset < 0xa0) +- gr_def(ctx, offset, 0x0077f005); +- else if (device->chipset == 0xa5) +- gr_def(ctx, offset, 0x6cf7f007); +- else if (device->chipset == 0xa8) +- gr_def(ctx, offset, 0x6cfff007); +- else if (device->chipset == 0xac) +- gr_def(ctx, offset, 0x0cfff007); +- else +- gr_def(ctx, offset, 0x0cf7f007); +- if (device->chipset == 0x50) +- gr_def(ctx, offset + 0x4, 0x00007fff); +- else if (device->chipset < 0xa0) +- gr_def(ctx, offset + 0x4, 0x003f7fff); +- else +- gr_def(ctx, offset + 0x4, 0x02bf7fff); +- cp_ctx(ctx, offset + 0x2c, 1); +- if (device->chipset == 0x50) { +- cp_ctx(ctx, offset + 0x50, 9); +- gr_def(ctx, offset + 0x54, 0x000003ff); +- gr_def(ctx, offset + 0x58, 0x00000003); +- gr_def(ctx, offset + 0x5c, 0x00000003); +- gr_def(ctx, offset + 0x60, 0x000001ff); +- gr_def(ctx, offset + 0x64, 0x0000001f); +- gr_def(ctx, offset + 0x68, 0x0000000f); +- gr_def(ctx, offset + 0x6c, 0x0000000f); +- } else if (device->chipset < 0xa0) { +- cp_ctx(ctx, offset + 0x50, 1); +- cp_ctx(ctx, offset + 0x70, 1); +- } else { +- cp_ctx(ctx, offset + 0x50, 1); +- cp_ctx(ctx, offset + 0x60, 5); +- } +- } +- } +-} +- +-static void +-dd_emit(struct nouveau_grctx *ctx, int num, u32 val) { +- int i; +- if (val && ctx->mode == NOUVEAU_GRCTX_VALS) +- for (i = 0; i < num; i++) +- nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val); +- ctx->ctxvals_pos += num; +-} +- +-static void +-nv50_graph_construct_mmio_ddata(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int base, num; +- base = ctx->ctxvals_pos; +- +- /* tesla state */ +- dd_emit(ctx, 1, 0); /* 00000001 UNK0F90 */ +- dd_emit(ctx, 1, 0); /* 00000001 UNK135C */ +- +- /* SRC_TIC state */ +- dd_emit(ctx, 1, 0); /* 00000007 SRC_TILE_MODE_Z */ +- dd_emit(ctx, 1, 2); /* 00000007 SRC_TILE_MODE_Y */ +- dd_emit(ctx, 1, 1); /* 00000001 SRC_LINEAR #1 */ +- dd_emit(ctx, 1, 0); /* 000000ff SRC_ADDRESS_HIGH */ +- dd_emit(ctx, 1, 0); /* 00000001 SRC_SRGB */ +- if (device->chipset >= 0x94) +- dd_emit(ctx, 1, 0); /* 00000003 eng2d UNK0258 */ +- dd_emit(ctx, 1, 1); /* 00000fff SRC_DEPTH */ +- dd_emit(ctx, 1, 0x100); /* 0000ffff SRC_HEIGHT */ +- +- /* turing state */ +- dd_emit(ctx, 1, 0); /* 0000000f TEXTURES_LOG2 */ +- dd_emit(ctx, 1, 0); /* 0000000f SAMPLERS_LOG2 */ +- dd_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ +- dd_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ +- dd_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ +- dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ +- dd_emit(ctx, 1, 1); /* 0000ffff BLOCK_ALLOC_THREADS */ +- dd_emit(ctx, 1, 1); /* 00000001 LANES32 */ +- dd_emit(ctx, 1, 0); /* 000000ff UNK370 */ +- dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_UNK */ +- dd_emit(ctx, 1, 0); /* 000000ff USER_PARAM_COUNT */ +- dd_emit(ctx, 1, 1); /* 000000ff UNK384 bits 8-15 */ +- dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ +- dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ +- dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ +- dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_X */ +- dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_XMY */ +- dd_emit(ctx, 1, 0); /* 00000001 BLOCKDIM_XMY_OVERFLOW */ +- dd_emit(ctx, 1, 1); /* 0003ffff BLOCKDIM_XMYMZ */ +- dd_emit(ctx, 1, 1); /* 000007ff BLOCKDIM_Y */ +- dd_emit(ctx, 1, 1); /* 0000007f BLOCKDIM_Z */ +- dd_emit(ctx, 1, 4); /* 000000ff CP_REG_ALLOC_TEMP */ +- dd_emit(ctx, 1, 1); /* 00000001 BLOCKDIM_DIRTY */ +- if (IS_NVA3F(device->chipset)) +- dd_emit(ctx, 1, 0); /* 00000003 UNK03E8 */ +- dd_emit(ctx, 1, 1); /* 0000007f BLOCK_ALLOC_HALFWARPS */ +- dd_emit(ctx, 1, 1); /* 00000007 LOCAL_WARPS_NO_CLAMP */ +- dd_emit(ctx, 1, 7); /* 00000007 LOCAL_WARPS_LOG_ALLOC */ +- dd_emit(ctx, 1, 1); /* 00000007 STACK_WARPS_NO_CLAMP */ +- dd_emit(ctx, 1, 7); /* 00000007 STACK_WARPS_LOG_ALLOC */ +- dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_PACKED */ +- dd_emit(ctx, 1, 1); /* 00001fff BLOCK_ALLOC_REGSLOTS_STRIDED */ +- dd_emit(ctx, 1, 1); /* 000007ff BLOCK_ALLOC_THREADS */ +- +- /* compat 2d state */ +- if (device->chipset == 0x50) { +- dd_emit(ctx, 4, 0); /* 0000ffff clip X, Y, W, H */ +- +- dd_emit(ctx, 1, 1); /* ffffffff chroma COLOR_FORMAT */ +- +- dd_emit(ctx, 1, 1); /* ffffffff pattern COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff pattern SHAPE */ +- dd_emit(ctx, 1, 1); /* ffffffff pattern PATTERN_SELECT */ +- +- dd_emit(ctx, 1, 0xa); /* ffffffff surf2d SRC_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff surf2d DMA_SRC */ +- dd_emit(ctx, 1, 0); /* 000000ff surf2d SRC_ADDRESS_HIGH */ +- dd_emit(ctx, 1, 0); /* ffffffff surf2d SRC_ADDRESS_LOW */ +- dd_emit(ctx, 1, 0x40); /* 0000ffff surf2d SRC_PITCH */ +- dd_emit(ctx, 1, 0); /* 0000000f surf2d SRC_TILE_MODE_Z */ +- dd_emit(ctx, 1, 2); /* 0000000f surf2d SRC_TILE_MODE_Y */ +- dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_HEIGHT */ +- dd_emit(ctx, 1, 1); /* 00000001 surf2d SRC_LINEAR */ +- dd_emit(ctx, 1, 0x100); /* ffffffff surf2d SRC_WIDTH */ +- +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_X */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_B_Y */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_X */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_C_Y */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_X */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect CLIP_D_Y */ +- dd_emit(ctx, 1, 1); /* ffffffff gdirect COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff gdirect OPERATION */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_X */ +- dd_emit(ctx, 1, 0); /* 0000ffff gdirect POINT_Y */ +- +- dd_emit(ctx, 1, 0); /* 0000ffff blit SRC_Y */ +- dd_emit(ctx, 1, 0); /* ffffffff blit OPERATION */ +- +- dd_emit(ctx, 1, 0); /* ffffffff ifc OPERATION */ +- +- dd_emit(ctx, 1, 0); /* ffffffff iifc INDEX_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff iifc LUT_OFFSET */ +- dd_emit(ctx, 1, 4); /* ffffffff iifc COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff iifc OPERATION */ +- } +- +- /* m2mf state */ +- dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_COUNT */ +- dd_emit(ctx, 1, 0); /* ffffffff m2mf LINE_LENGTH_IN */ +- dd_emit(ctx, 2, 0); /* ffffffff m2mf OFFSET_IN, OFFSET_OUT */ +- dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_OUT */ +- dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_OUT */ +- dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_OUT_Z */ +- dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_OUT */ +- dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_OUT_X, Y */ +- dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_OUT */ +- dd_emit(ctx, 1, 1); /* ffffffff m2mf TILING_DEPTH_IN */ +- dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_HEIGHT_IN */ +- dd_emit(ctx, 1, 0); /* ffffffff m2mf TILING_POSITION_IN_Z */ +- dd_emit(ctx, 1, 1); /* 00000001 m2mf LINEAR_IN */ +- dd_emit(ctx, 2, 0); /* 0000ffff m2mf TILING_POSITION_IN_X, Y */ +- dd_emit(ctx, 1, 0x100); /* ffffffff m2mf TILING_PITCH_IN */ +- +- /* more compat 2d state */ +- if (device->chipset == 0x50) { +- dd_emit(ctx, 1, 1); /* ffffffff line COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff line OPERATION */ +- +- dd_emit(ctx, 1, 1); /* ffffffff triangle COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff triangle OPERATION */ +- +- dd_emit(ctx, 1, 0); /* 0000000f sifm TILE_MODE_Z */ +- dd_emit(ctx, 1, 2); /* 0000000f sifm TILE_MODE_Y */ +- dd_emit(ctx, 1, 0); /* 000000ff sifm FORMAT_FILTER */ +- dd_emit(ctx, 1, 1); /* 000000ff sifm FORMAT_ORIGIN */ +- dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_PITCH */ +- dd_emit(ctx, 1, 1); /* 00000001 sifm SRC_LINEAR */ +- dd_emit(ctx, 1, 0); /* 000000ff sifm SRC_OFFSET_HIGH */ +- dd_emit(ctx, 1, 0); /* ffffffff sifm SRC_OFFSET */ +- dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_HEIGHT */ +- dd_emit(ctx, 1, 0); /* 0000ffff sifm SRC_WIDTH */ +- dd_emit(ctx, 1, 3); /* ffffffff sifm COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff sifm OPERATION */ +- +- dd_emit(ctx, 1, 0); /* ffffffff sifc OPERATION */ +- } +- +- /* tesla state */ +- dd_emit(ctx, 1, 0); /* 0000000f GP_TEXTURES_LOG2 */ +- dd_emit(ctx, 1, 0); /* 0000000f GP_SAMPLERS_LOG2 */ +- dd_emit(ctx, 1, 0); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* ffffffff */ +- dd_emit(ctx, 1, 4); /* 000000ff UNK12B0_0 */ +- dd_emit(ctx, 1, 0x70); /* 000000ff UNK12B0_1 */ +- dd_emit(ctx, 1, 0x80); /* 000000ff UNK12B0_3 */ +- dd_emit(ctx, 1, 0); /* 000000ff UNK12B0_2 */ +- dd_emit(ctx, 1, 0); /* 0000000f FP_TEXTURES_LOG2 */ +- dd_emit(ctx, 1, 0); /* 0000000f FP_SAMPLERS_LOG2 */ +- if (IS_NVA3F(device->chipset)) { +- dd_emit(ctx, 1, 0); /* ffffffff */ +- dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */ +- } else { +- dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */ +- } +- dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */ +- if (device->chipset != 0x50) +- dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */ +- dd_emit(ctx, 1, 8); /* 000000ff SEMANTIC_COLOR.COLR_NR */ +- dd_emit(ctx, 1, 0x14); /* 000000ff SEMANTIC_COLOR.FFC0_ID */ +- if (device->chipset == 0x50) { +- dd_emit(ctx, 1, 0); /* 000000ff SEMANTIC_LAYER */ +- dd_emit(ctx, 1, 0); /* 00000001 */ +- } else { +- dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_PTSZ.ENABLE */ +- dd_emit(ctx, 1, 0x29); /* 000000ff SEMANTIC_PTSZ.PTSZ_ID */ +- dd_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM */ +- dd_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ +- dd_emit(ctx, 1, 8); /* 0000000f SMENATIC_CLIP.CLIP_HIGH */ +- dd_emit(ctx, 1, 4); /* 000000ff SEMANTIC_CLIP.CLIP_LO */ +- dd_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ +- dd_emit(ctx, 1, 0); /* 00000001 UNK1900 */ +- } +- dd_emit(ctx, 1, 0); /* 00000007 RT_CONTROL_MAP0 */ +- dd_emit(ctx, 1, 1); /* 00000007 RT_CONTROL_MAP1 */ +- dd_emit(ctx, 1, 2); /* 00000007 RT_CONTROL_MAP2 */ +- dd_emit(ctx, 1, 3); /* 00000007 RT_CONTROL_MAP3 */ +- dd_emit(ctx, 1, 4); /* 00000007 RT_CONTROL_MAP4 */ +- dd_emit(ctx, 1, 5); /* 00000007 RT_CONTROL_MAP5 */ +- dd_emit(ctx, 1, 6); /* 00000007 RT_CONTROL_MAP6 */ +- dd_emit(ctx, 1, 7); /* 00000007 RT_CONTROL_MAP7 */ +- dd_emit(ctx, 1, 1); /* 0000000f RT_CONTROL_COUNT */ +- dd_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_UNK */ +- dd_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ +- dd_emit(ctx, 1, 0xcf); /* 000000ff RT_FORMAT */ +- dd_emit(ctx, 7, 0); /* 000000ff RT_FORMAT */ +- if (device->chipset != 0x50) +- dd_emit(ctx, 3, 0); /* 1, 1, 1 */ +- else +- dd_emit(ctx, 2, 0); /* 1, 1 */ +- dd_emit(ctx, 1, 0); /* ffffffff GP_ENABLE */ +- dd_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT*/ +- dd_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ +- dd_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- if (IS_NVA3F(device->chipset)) { +- dd_emit(ctx, 1, 3); /* 00000003 */ +- dd_emit(ctx, 1, 0); /* 00000001 UNK1418. Alone. */ +- } +- if (device->chipset != 0x50) +- dd_emit(ctx, 1, 3); /* 00000003 UNK15AC */ +- dd_emit(ctx, 1, 1); /* ffffffff RASTERIZE_ENABLE */ +- dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.EXPORTS_Z */ +- if (device->chipset != 0x50) +- dd_emit(ctx, 1, 0); /* 00000001 FP_CONTROL.MULTIPLE_RESULTS */ +- dd_emit(ctx, 1, 0x12); /* 000000ff FP_INTERPOLANT_CTRL.COUNT */ +- dd_emit(ctx, 1, 0x10); /* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */ +- dd_emit(ctx, 1, 0xc); /* 000000ff FP_INTERPOLANT_CTRL.OFFSET */ +- dd_emit(ctx, 1, 1); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.W */ +- dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */ +- dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */ +- dd_emit(ctx, 1, 0); /* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */ +- dd_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ +- dd_emit(ctx, 1, 2); /* ffffffff REG_MODE */ +- dd_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ +- if (device->chipset >= 0xa0) +- dd_emit(ctx, 1, 0); /* ffffffff */ +- dd_emit(ctx, 1, 0); /* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */ +- dd_emit(ctx, 1, 0); /* ffffffff STRMOUT_ENABLE */ +- dd_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ +- dd_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ +- dd_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE*/ +- if (device->chipset != 0x50) +- dd_emit(ctx, 8, 0); /* 00000001 */ +- if (device->chipset >= 0xa0) { +- dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.COMP */ +- dd_emit(ctx, 1, 1); /* 00000007 VTX_ATTR_DEFINE.SIZE */ +- dd_emit(ctx, 1, 2); /* 00000007 VTX_ATTR_DEFINE.TYPE */ +- dd_emit(ctx, 1, 0); /* 000000ff VTX_ATTR_DEFINE.ATTR */ +- } +- dd_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- dd_emit(ctx, 1, 0x14); /* 0000001f ZETA_FORMAT */ +- dd_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- dd_emit(ctx, 1, 0); /* 0000000f VP_TEXTURES_LOG2 */ +- dd_emit(ctx, 1, 0); /* 0000000f VP_SAMPLERS_LOG2 */ +- if (IS_NVA3F(device->chipset)) +- dd_emit(ctx, 1, 0); /* 00000001 */ +- dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_BACK */ +- if (device->chipset >= 0xa0) +- dd_emit(ctx, 1, 0); /* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */ +- dd_emit(ctx, 1, 0); /* 0000ffff CB_ADDR_INDEX */ +- if (device->chipset >= 0xa0) +- dd_emit(ctx, 1, 0); /* 00000003 */ +- dd_emit(ctx, 1, 0); /* 00000001 CULL_FACE_ENABLE */ +- dd_emit(ctx, 1, 1); /* 00000003 CULL_FACE */ +- dd_emit(ctx, 1, 0); /* 00000001 FRONT_FACE */ +- dd_emit(ctx, 1, 2); /* 00000003 POLYGON_MODE_FRONT */ +- dd_emit(ctx, 1, 0x1000); /* 00007fff UNK141C */ +- if (device->chipset != 0x50) { +- dd_emit(ctx, 1, 0xe00); /* 7fff */ +- dd_emit(ctx, 1, 0x1000); /* 7fff */ +- dd_emit(ctx, 1, 0x1e00); /* 7fff */ +- } +- dd_emit(ctx, 1, 0); /* 00000001 BEGIN_END_ACTIVE */ +- dd_emit(ctx, 1, 1); /* 00000001 POLYGON_MODE_??? */ +- dd_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP / 4 rounded up */ +- dd_emit(ctx, 1, 1); /* 000000ff FP_REG_ALLOC_TEMP... without /4? */ +- dd_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP / 4 rounded up */ +- dd_emit(ctx, 1, 1); /* 00000001 */ +- dd_emit(ctx, 1, 0); /* 00000001 */ +- dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK0 nonempty */ +- dd_emit(ctx, 1, 0); /* 00000001 VTX_ATTR_MASK_UNK1 nonempty */ +- dd_emit(ctx, 1, 0x200); /* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */ +- if (IS_NVA3F(device->chipset)) +- dd_emit(ctx, 1, 0x200); +- dd_emit(ctx, 1, 0); /* 00000001 */ +- if (device->chipset < 0xa0) { +- dd_emit(ctx, 1, 1); /* 00000001 */ +- dd_emit(ctx, 1, 0x70); /* 000000ff */ +- dd_emit(ctx, 1, 0x80); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* 00000001 */ +- dd_emit(ctx, 1, 1); /* 00000001 */ +- dd_emit(ctx, 1, 0x70); /* 000000ff */ +- dd_emit(ctx, 1, 0x80); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* 000000ff */ +- } else { +- dd_emit(ctx, 1, 1); /* 00000001 */ +- dd_emit(ctx, 1, 0xf0); /* 000000ff */ +- dd_emit(ctx, 1, 0xff); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* 00000001 */ +- dd_emit(ctx, 1, 1); /* 00000001 */ +- dd_emit(ctx, 1, 0xf0); /* 000000ff */ +- dd_emit(ctx, 1, 0xff); /* 000000ff */ +- dd_emit(ctx, 1, 0); /* 000000ff */ +- dd_emit(ctx, 1, 9); /* 0000003f UNK114C.COMP,SIZE */ +- } +- +- /* eng2d state */ +- dd_emit(ctx, 1, 0); /* 00000001 eng2d COLOR_KEY_ENABLE */ +- dd_emit(ctx, 1, 0); /* 00000007 eng2d COLOR_KEY_FORMAT */ +- dd_emit(ctx, 1, 1); /* ffffffff eng2d DST_DEPTH */ +- dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DST_FORMAT */ +- dd_emit(ctx, 1, 0); /* ffffffff eng2d DST_LAYER */ +- dd_emit(ctx, 1, 1); /* 00000001 eng2d DST_LINEAR */ +- dd_emit(ctx, 1, 0); /* 00000007 eng2d PATTERN_COLOR_FORMAT */ +- dd_emit(ctx, 1, 0); /* 00000007 eng2d OPERATION */ +- dd_emit(ctx, 1, 0); /* 00000003 eng2d PATTERN_SELECT */ +- dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SIFC_FORMAT */ +- dd_emit(ctx, 1, 0); /* 00000001 eng2d SIFC_BITMAP_ENABLE */ +- dd_emit(ctx, 1, 2); /* 00000003 eng2d SIFC_BITMAP_UNK808 */ +- dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DU_DX_FRACT */ +- dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DU_DX_INT */ +- dd_emit(ctx, 1, 0); /* ffffffff eng2d BLIT_DV_DY_FRACT */ +- dd_emit(ctx, 1, 1); /* ffffffff eng2d BLIT_DV_DY_INT */ +- dd_emit(ctx, 1, 0); /* 00000001 eng2d BLIT_CONTROL_FILTER */ +- dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d DRAW_COLOR_FORMAT */ +- dd_emit(ctx, 1, 0xcf); /* 000000ff eng2d SRC_FORMAT */ +- dd_emit(ctx, 1, 1); /* 00000001 eng2d SRC_LINEAR #2 */ +- +- num = ctx->ctxvals_pos - base; +- ctx->ctxvals_pos = base; +- if (IS_NVA3F(device->chipset)) +- cp_ctx(ctx, 0x404800, num); +- else +- cp_ctx(ctx, 0x405400, num); +-} +- +-/* +- * xfer areas. These are a pain. +- * +- * There are 2 xfer areas: the first one is big and contains all sorts of +- * stuff, the second is small and contains some per-TP context. +- * +- * Each area is split into 8 "strands". The areas, when saved to grctx, +- * are made of 8-word blocks. Each block contains a single word from +- * each strand. The strands are independent of each other, their +- * addresses are unrelated to each other, and data in them is closely +- * packed together. The strand layout varies a bit between cards: here +- * and there, a single word is thrown out in the middle and the whole +- * strand is offset by a bit from corresponding one on another chipset. +- * For this reason, addresses of stuff in strands are almost useless. +- * Knowing sequence of stuff and size of gaps between them is much more +- * useful, and that's how we build the strands in our generator. +- * +- * NVA0 takes this mess to a whole new level by cutting the old strands +- * into a few dozen pieces [known as genes], rearranging them randomly, +- * and putting them back together to make new strands. Hopefully these +- * genes correspond more or less directly to the same PGRAPH subunits +- * as in 400040 register. +- * +- * The most common value in default context is 0, and when the genes +- * are separated by 0's, gene bounduaries are quite speculative... +- * some of them can be clearly deduced, others can be guessed, and yet +- * others won't be resolved without figuring out the real meaning of +- * given ctxval. For the same reason, ending point of each strand +- * is unknown. Except for strand 0, which is the longest strand and +- * its end corresponds to end of the whole xfer. +- * +- * An unsolved mystery is the seek instruction: it takes an argument +- * in bits 8-18, and that argument is clearly the place in strands to +- * seek to... but the offsets don't seem to correspond to offsets as +- * seen in grctx. Perhaps there's another, real, not randomly-changing +- * addressing in strands, and the xfer insn just happens to skip over +- * the unused bits? NV10-NV30 PIPE comes to mind... +- * +- * As far as I know, there's no way to access the xfer areas directly +- * without the help of ctxprog. +- */ +- +-static void +-xf_emit(struct nouveau_grctx *ctx, int num, u32 val) { +- int i; +- if (val && ctx->mode == NOUVEAU_GRCTX_VALS) +- for (i = 0; i < num; i++) +- nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val); +- ctx->ctxvals_pos += num << 3; +-} +- +-/* Gene declarations... */ +- +-static void nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx); +-static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx); +- +-static void +-nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- int offset; +- int size = 0; +- u32 units = nv_rd32 (ctx->device, 0x1540); +- +- offset = (ctx->ctxvals_pos+0x3f)&~0x3f; +- ctx->ctxvals_base = offset; +- +- if (device->chipset < 0xa0) { +- /* Strand 0 */ +- ctx->ctxvals_pos = offset; +- nv50_graph_construct_gene_dispatch(ctx); +- nv50_graph_construct_gene_m2mf(ctx); +- nv50_graph_construct_gene_unk24xx(ctx); +- nv50_graph_construct_gene_clipid(ctx); +- nv50_graph_construct_gene_zcull(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 1 */ +- ctx->ctxvals_pos = offset + 0x1; +- nv50_graph_construct_gene_vfetch(ctx); +- nv50_graph_construct_gene_eng2d(ctx); +- nv50_graph_construct_gene_csched(ctx); +- nv50_graph_construct_gene_ropm1(ctx); +- nv50_graph_construct_gene_ropm2(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 2 */ +- ctx->ctxvals_pos = offset + 0x2; +- nv50_graph_construct_gene_ccache(ctx); +- nv50_graph_construct_gene_unk1cxx(ctx); +- nv50_graph_construct_gene_strmout(ctx); +- nv50_graph_construct_gene_unk14xx(ctx); +- nv50_graph_construct_gene_unk10xx(ctx); +- nv50_graph_construct_gene_unk34xx(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 3: per-ROP group state */ +- ctx->ctxvals_pos = offset + 3; +- for (i = 0; i < 6; i++) +- if (units & (1 << (i + 16))) +- nv50_graph_construct_gene_ropc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strands 4-7: per-TP state */ +- for (i = 0; i < 4; i++) { +- ctx->ctxvals_pos = offset + 4 + i; +- if (units & (1 << (2 * i))) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << (2 * i + 1))) +- nv50_graph_construct_xfer_tp(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- } +- } else { +- /* Strand 0 */ +- ctx->ctxvals_pos = offset; +- nv50_graph_construct_gene_dispatch(ctx); +- nv50_graph_construct_gene_m2mf(ctx); +- nv50_graph_construct_gene_unk34xx(ctx); +- nv50_graph_construct_gene_csched(ctx); +- nv50_graph_construct_gene_unk1cxx(ctx); +- nv50_graph_construct_gene_strmout(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 1 */ +- ctx->ctxvals_pos = offset + 1; +- nv50_graph_construct_gene_unk10xx(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 2 */ +- ctx->ctxvals_pos = offset + 2; +- if (device->chipset == 0xa0) +- nv50_graph_construct_gene_unk14xx(ctx); +- nv50_graph_construct_gene_unk24xx(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 3 */ +- ctx->ctxvals_pos = offset + 3; +- nv50_graph_construct_gene_vfetch(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 4 */ +- ctx->ctxvals_pos = offset + 4; +- nv50_graph_construct_gene_ccache(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 5 */ +- ctx->ctxvals_pos = offset + 5; +- nv50_graph_construct_gene_ropm2(ctx); +- nv50_graph_construct_gene_ropm1(ctx); +- /* per-ROP context */ +- for (i = 0; i < 8; i++) +- if (units & (1<<(i+16))) +- nv50_graph_construct_gene_ropc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 6 */ +- ctx->ctxvals_pos = offset + 6; +- nv50_graph_construct_gene_zcull(ctx); +- nv50_graph_construct_gene_clipid(ctx); +- nv50_graph_construct_gene_eng2d(ctx); +- if (units & (1 << 0)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 1)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 2)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 3)) +- nv50_graph_construct_xfer_tp(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 7 */ +- ctx->ctxvals_pos = offset + 7; +- if (device->chipset == 0xa0) { +- if (units & (1 << 4)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 5)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 6)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 7)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 8)) +- nv50_graph_construct_xfer_tp(ctx); +- if (units & (1 << 9)) +- nv50_graph_construct_xfer_tp(ctx); +- } else { +- nv50_graph_construct_gene_unk14xx(ctx); +- } +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- } +- +- ctx->ctxvals_pos = offset + size * 8; +- ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; +- cp_lsr (ctx, offset); +- cp_out (ctx, CP_SET_XFER_POINTER); +- cp_lsr (ctx, size); +- cp_out (ctx, CP_SEEK_1); +- cp_out (ctx, CP_XFER_1); +- cp_wait(ctx, XFER, BUSY); +-} +- +-/* +- * non-trivial demagiced parts of ctx init go here +- */ +- +-static void +-nv50_graph_construct_gene_dispatch(struct nouveau_grctx *ctx) +-{ +- /* start of strand 0 */ +- struct nouveau_device *device = ctx->device; +- /* SEEK */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 5, 0); +- else if (!IS_NVA3F(device->chipset)) +- xf_emit(ctx, 6, 0); +- else +- xf_emit(ctx, 4, 0); +- /* SEEK */ +- /* the PGRAPH's internal FIFO */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 8*3, 0); +- else +- xf_emit(ctx, 0x100*3, 0); +- /* and another bonus slot?!? */ +- xf_emit(ctx, 3, 0); +- /* and YET ANOTHER bonus slot? */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 3, 0); +- /* SEEK */ +- /* CTX_SWITCH: caches of gr objects bound to subchannels. 8 values, last used index */ +- xf_emit(ctx, 9, 0); +- /* SEEK */ +- xf_emit(ctx, 9, 0); +- /* SEEK */ +- xf_emit(ctx, 9, 0); +- /* SEEK */ +- xf_emit(ctx, 9, 0); +- /* SEEK */ +- if (device->chipset < 0x90) +- xf_emit(ctx, 4, 0); +- /* SEEK */ +- xf_emit(ctx, 2, 0); +- /* SEEK */ +- xf_emit(ctx, 6*2, 0); +- xf_emit(ctx, 2, 0); +- /* SEEK */ +- xf_emit(ctx, 2, 0); +- /* SEEK */ +- xf_emit(ctx, 6*2, 0); +- xf_emit(ctx, 2, 0); +- /* SEEK */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 0x1c, 0); +- else if (device->chipset < 0xa0) +- xf_emit(ctx, 0x1e, 0); +- else +- xf_emit(ctx, 0x22, 0); +- /* SEEK */ +- xf_emit(ctx, 0x15, 0); +-} +- +-static void +-nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx) +-{ +- /* Strand 0, right after dispatch */ +- struct nouveau_device *device = ctx->device; +- int smallm2mf = 0; +- if (device->chipset < 0x92 || device->chipset == 0x98) +- smallm2mf = 1; +- /* SEEK */ +- xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ +- xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ +- xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ +- xf_emit (ctx, 1, 0); /* OFFSET_IN */ +- xf_emit (ctx, 1, 0); /* OFFSET_OUT */ +- xf_emit (ctx, 1, 0); /* PITCH_IN */ +- xf_emit (ctx, 1, 0); /* PITCH_OUT */ +- xf_emit (ctx, 1, 0); /* LINE_LENGTH */ +- xf_emit (ctx, 1, 0); /* LINE_COUNT */ +- xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ +- xf_emit (ctx, 1, 1); /* LINEAR_IN */ +- xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ +- xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ +- xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ +- xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ +- xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ +- xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ +- xf_emit (ctx, 1, 1); /* LINEAR_OUT */ +- xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ +- xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ +- xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ +- xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ +- xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ +- xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ +- xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ +- xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ +- /* SEEK */ +- if (smallm2mf) +- xf_emit(ctx, 0x40, 0); /* 20 * ffffffff, 3ffff */ +- else +- xf_emit(ctx, 0x100, 0); /* 80 * ffffffff, 3ffff */ +- xf_emit(ctx, 4, 0); /* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */ +- /* SEEK */ +- if (smallm2mf) +- xf_emit(ctx, 0x400, 0); /* ffffffff */ +- else +- xf_emit(ctx, 0x800, 0); /* ffffffff */ +- xf_emit(ctx, 4, 0); /* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */ +- /* SEEK */ +- xf_emit(ctx, 0x40, 0); /* 20 * bits ffffffff, 3ffff */ +- xf_emit(ctx, 0x6, 0); /* 1f, 0, 1f, 0, 1f, 0 */ +-} +- +-static void +-nv50_graph_construct_gene_ccache(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- xf_emit(ctx, 2, 0); /* RO */ +- xf_emit(ctx, 0x800, 0); /* ffffffff */ +- switch (device->chipset) { +- case 0x50: +- case 0x92: +- case 0xa0: +- xf_emit(ctx, 0x2b, 0); +- break; +- case 0x84: +- xf_emit(ctx, 0x29, 0); +- break; +- case 0x94: +- case 0x96: +- case 0xa3: +- xf_emit(ctx, 0x27, 0); +- break; +- case 0x86: +- case 0x98: +- case 0xa5: +- case 0xa8: +- case 0xaa: +- case 0xac: +- case 0xaf: +- xf_emit(ctx, 0x25, 0); +- break; +- } +- /* CB bindings, 0x80 of them. first word is address >> 8, second is +- * size >> 4 | valid << 24 */ +- xf_emit(ctx, 0x100, 0); /* ffffffff CB_DEF */ +- xf_emit(ctx, 1, 0); /* 0000007f CB_ADDR_BUFFER */ +- xf_emit(ctx, 1, 0); /* 0 */ +- xf_emit(ctx, 0x30, 0); /* ff SET_PROGRAM_CB */ +- xf_emit(ctx, 1, 0); /* 3f last SET_PROGRAM_CB */ +- xf_emit(ctx, 4, 0); /* RO */ +- xf_emit(ctx, 0x100, 0); /* ffffffff */ +- xf_emit(ctx, 8, 0); /* 1f, 0, 0, ... */ +- xf_emit(ctx, 8, 0); /* ffffffff */ +- xf_emit(ctx, 4, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 3 */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_CODE_CB */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_TIC */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_TSC */ +- xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ +- xf_emit(ctx, 1, 0); /* 000000ff TIC_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff TIC_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0x3fffff); /* 003fffff TIC_LIMIT */ +- xf_emit(ctx, 1, 0); /* 000000ff TSC_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff TSC_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0x1fff); /* 000fffff TSC_LIMIT */ +- xf_emit(ctx, 1, 0); /* 000000ff VP_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff VP_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0); /* 00ffffff VP_START_ID */ +- xf_emit(ctx, 1, 0); /* 000000ff CB_DEF_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff CB_DEF_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0); /* 000000ff GP_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff GP_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0); /* 00ffffff GP_START_ID */ +- xf_emit(ctx, 1, 0); /* 000000ff FP_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0); /* 00ffffff FP_START_ID */ +-} +- +-static void +-nv50_graph_construct_gene_unk10xx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- /* end of area 2 on pre-NVA0, area 1 on NVAx */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 1, 0x3ff); +- else +- xf_emit(ctx, 1, 0x7ff); /* 000007ff */ +- xf_emit(ctx, 1, 0); /* 111/113 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- for (i = 0; i < 8; i++) { +- switch (device->chipset) { +- case 0x50: +- case 0x86: +- case 0x98: +- case 0xaa: +- case 0xac: +- xf_emit(ctx, 0xa0, 0); /* ffffffff */ +- break; +- case 0x84: +- case 0x92: +- case 0x94: +- case 0x96: +- xf_emit(ctx, 0x120, 0); +- break; +- case 0xa5: +- case 0xa8: +- xf_emit(ctx, 0x100, 0); /* ffffffff */ +- break; +- case 0xa0: +- case 0xa3: +- case 0xaf: +- xf_emit(ctx, 0x400, 0); /* ffffffff */ +- break; +- } +- xf_emit(ctx, 4, 0); /* 3f, 0, 0, 0 */ +- xf_emit(ctx, 4, 0); /* ffffffff */ +- } +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_TEMP */ +- xf_emit(ctx, 1, 1); /* 00000001 RASTERIZE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0x27); /* 000000ff UNK0FD4 */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +-} +- +-static void +-nv50_graph_construct_gene_unk34xx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- /* end of area 2 on pre-NVA0, area 1 on NVAx */ +- xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ +- xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */ +- xf_emit(ctx, 0x10, 0x04000000); /* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */ +- xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ +- xf_emit(ctx, 0x20, 0); /* ffffffff POLYGON_STIPPLE */ +- xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ +- xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ +- xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0x1fe21); /* 0001ffff tesla UNK0FAC */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 0x0fac6881); +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 1); +- xf_emit(ctx, 3, 0); +- } +-} +- +-static void +-nv50_graph_construct_gene_unk14xx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ +- if (device->chipset != 0x50) { +- xf_emit(ctx, 5, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 2, 4); /* 7f, ff */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- } +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* 000000ff VP_CLIP_DISTANCE_ENABLE */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 0); /* 3ff */ +- xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1940 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ +- xf_emit(ctx, 1, 0x804); /* 00000fff SEMANTIC_CLIP */ +- xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 0x7f); /* 000000ff tesla UNK0FFC */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 1); /* 00000001 SHADE_MODEL */ +- xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0D7C */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0F8C */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ +- else +- xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ +- xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ +- xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */ +- xf_emit(ctx, 3, 0); /* f, 0, 0 */ +- xf_emit(ctx, 3, 0); /* ffffffff last VIEWPORT_SCALE? */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 1); /* 00000001 VIEWPORT_TRANSFORM_EN */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ +- xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 0x30, 0); /* ffffffff VIEWPORT_TRANSLATE */ +- xf_emit(ctx, 3, 0); /* f, 0, 0 */ +- xf_emit(ctx, 3, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 2, 0x88); /* 000001ff tesla UNK19D8 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ +- xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ +- xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ +- xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ +- xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +- xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +- xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ +- if (device->chipset != 0x50) { +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- } +- xf_emit(ctx, 0x20, 0); /* 10xbits ffffffff, 3fffff. SCISSOR_* */ +- xf_emit(ctx, 1, 0); /* f */ +- xf_emit(ctx, 1, 0); /* 0? */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 003fffff */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 0x26); /* 000000ff SEMANTIC_LAYER */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +-} +- +-static void +-nv50_graph_construct_gene_zcull(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- /* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */ +- /* SEEK */ +- xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ +- xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ +- xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ +- xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ +- xf_emit(ctx, 1, 0); /* 0000ffff */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK0FB0 */ +- xf_emit(ctx, 1, 0); /* 00000001 POLYGON_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1108 */ +- xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ +- /* SEEK */ +- xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ +- xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ +- xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ +- xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ +- xf_emit(ctx, 1, 0x10); /* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */ +- xf_emit(ctx, 1, 3); /* 00000003 FP_CTRL_UNK196C */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1968 */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 0); /* 0fffffff tesla UNK1104 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK151C */ +-} +- +-static void +-nv50_graph_construct_gene_clipid(struct nouveau_grctx *ctx) +-{ +- /* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 00000007 UNK0FB4 */ +- /* SEEK */ +- xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_HORIZ */ +- xf_emit(ctx, 4, 0); /* 07ffffff CLIPID_REGION_VERT */ +- xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ +- xf_emit(ctx, 2, 0x04000000); /* 07ffffff UNK1508 */ +- xf_emit(ctx, 1, 0); /* 00000001 CLIPID_ENABLE */ +- xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_WIDTH */ +- xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ID */ +- xf_emit(ctx, 1, 0); /* 000000ff CLIPID_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff CLIPID_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0x80); /* 00003fff CLIPID_HEIGHT */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_CLIPID */ +-} +- +-static void +-nv50_graph_construct_gene_unk24xx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- /* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */ +- /* SEEK */ +- xf_emit(ctx, 0x33, 0); +- /* SEEK */ +- xf_emit(ctx, 2, 0); +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 4, 0); /* RO */ +- xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ +- xf_emit(ctx, 1, 0); /* 1ff */ +- xf_emit(ctx, 8, 0); /* 0? */ +- xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ +- +- xf_emit(ctx, 4, 0); /* RO */ +- xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ +- xf_emit(ctx, 1, 0); /* 1ff */ +- xf_emit(ctx, 8, 0); /* 0? */ +- xf_emit(ctx, 9, 0); /* ffffffff, 7ff */ +- } else { +- xf_emit(ctx, 0xc, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ +- xf_emit(ctx, 1, 0); /* 1ff */ +- xf_emit(ctx, 8, 0); /* 0? */ +- +- /* SEEK */ +- xf_emit(ctx, 0xc, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */ +- xf_emit(ctx, 1, 0); /* 1ff */ +- xf_emit(ctx, 8, 0); /* 0? */ +- } +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ +- xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ +- xf_emit(ctx, 1, 1); /* 00000001 */ +- /* SEEK */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 2, 4); /* 000000ff */ +- xf_emit(ctx, 1, 0x80c14); /* 01ffffff SEMANTIC_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 0x27); /* 000000ff SEMANTIC_PRIM_ID */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +- xf_emit(ctx, 1, 1); /* 00000001 */ +- for (i = 0; i < 10; i++) { +- /* SEEK */ +- xf_emit(ctx, 0x40, 0); /* ffffffff */ +- xf_emit(ctx, 0x10, 0); /* 3, 0, 0.... */ +- xf_emit(ctx, 0x10, 0); /* ffffffff */ +- } +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_CTRL */ +- xf_emit(ctx, 1, 1); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 4, 0); /* ffffffff NOPERSPECTIVE_BITMAP */ +- xf_emit(ctx, 0x10, 0); /* 00ffffff POINT_COORD_REPLACE_MAP */ +- xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 0); /* 000003ff */ +-} +- +-static void +-nv50_graph_construct_gene_vfetch(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int acnt = 0x10, rep, i; +- /* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */ +- if (IS_NVA3F(device->chipset)) +- acnt = 0x20; +- /* SEEK */ +- if (device->chipset >= 0xa0) { +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK13A4 */ +- xf_emit(ctx, 1, 1); /* 00000fff tesla UNK1318 */ +- } +- xf_emit(ctx, 1, 0); /* ffffffff VERTEX_BUFFER_FIRST */ +- xf_emit(ctx, 1, 0); /* 00000001 PRIMITIVE_RESTART_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK0DE8 */ +- xf_emit(ctx, 1, 0); /* ffffffff PRIMITIVE_RESTART_INDEX */ +- xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATR_MASK_UNK0DD0 */ +- xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ +- xf_emit(ctx, 1, 0x20); /* 0000ffff tesla UNK129C */ +- xf_emit(ctx, 1, 0); /* 000000ff turing UNK370??? */ +- xf_emit(ctx, 1, 0); /* 0000ffff turing USER_PARAM_COUNT */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0xb, 0); /* RO */ +- else if (device->chipset >= 0xa0) +- xf_emit(ctx, 0x9, 0); /* RO */ +- else +- xf_emit(ctx, 0x8, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 00000001 EDGE_FLAG */ +- xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +- /* SEEK */ +- xf_emit(ctx, 0xc, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 7f/ff */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ +- xf_emit(ctx, 1, 4); /* 000001ff UNK1A28 */ +- xf_emit(ctx, 1, 8); /* 000001ff UNK0DF0 */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 1, 0x3ff); /* 3ff tesla UNK0D68 */ +- else +- xf_emit(ctx, 1, 0x7ff); /* 7ff tesla UNK0D68 */ +- if (device->chipset == 0xa8) +- xf_emit(ctx, 1, 0x1e00); /* 7fff */ +- /* SEEK */ +- xf_emit(ctx, 0xc, 0); /* RO or close */ +- /* SEEK */ +- xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ +- if (device->chipset > 0x50 && device->chipset < 0xa0) +- xf_emit(ctx, 2, 0); /* ffffffff */ +- else +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0FD8 */ +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 0x10, 0); /* 0? */ +- xf_emit(ctx, 2, 0); /* weird... */ +- xf_emit(ctx, 2, 0); /* RO */ +- } else { +- xf_emit(ctx, 8, 0); /* 0? */ +- xf_emit(ctx, 1, 0); /* weird... */ +- xf_emit(ctx, 2, 0); /* RO */ +- } +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* ffffffff VB_ELEMENT_BASE */ +- xf_emit(ctx, 1, 0); /* ffffffff UNK1438 */ +- xf_emit(ctx, acnt, 0); /* 1 tesla UNK1000 */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1118? */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ +- xf_emit(ctx, 1, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_UNK90C */ +- xf_emit(ctx, 1, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* RO */ +- xf_emit(ctx, 2, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK111C? */ +- xf_emit(ctx, 1, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 000000ff UNK15F4_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff UNK15F4_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0); /* 000000ff UNK0F84_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff UNK0F84_ADDRESS_LOW */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* 00000fff VERTEX_ARRAY_STRIDE */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_ARRAY_LOW */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_ARRAY_HIGH */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* ffffffff VERTEX_LIMIT_LOW */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- /* SEEK */ +- xf_emit(ctx, acnt, 0); /* 000000ff VERTEX_LIMIT_HIGH */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, acnt, 0); /* f */ +- xf_emit(ctx, 3, 0); /* f/1f */ +- } +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 2, 0); /* RO */ +- else +- xf_emit(ctx, 5, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* ffff DMA_VTXBUF */ +- /* SEEK */ +- if (device->chipset < 0xa0) { +- xf_emit(ctx, 0x41, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 0x11, 0); /* RO */ +- } else if (!IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x50, 0); /* RO */ +- else +- xf_emit(ctx, 0x58, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, 1, 1); /* 1 UNK0DEC */ +- /* SEEK */ +- xf_emit(ctx, acnt*4, 0); /* ffffffff VTX_ATTR */ +- xf_emit(ctx, 4, 0); /* f/1f, 0, 0, 0 */ +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x1d, 0); /* RO */ +- else +- xf_emit(ctx, 0x16, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ +- /* SEEK */ +- if (device->chipset < 0xa0) +- xf_emit(ctx, 8, 0); /* RO */ +- else if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0xc, 0); /* RO */ +- else +- xf_emit(ctx, 7, 0); /* RO */ +- /* SEEK */ +- xf_emit(ctx, 0xa, 0); /* RO */ +- if (device->chipset == 0xa0) +- rep = 0xc; +- else +- rep = 4; +- for (i = 0; i < rep; i++) { +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x20, 0); /* ffffffff */ +- xf_emit(ctx, 0x200, 0); /* ffffffff */ +- xf_emit(ctx, 4, 0); /* 7f/ff, 0, 0, 0 */ +- xf_emit(ctx, 4, 0); /* ffffffff */ +- } +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 113/111 */ +- xf_emit(ctx, 1, 0xf); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, (acnt/8)-1, 0); /* ffffffff VP_ATTR_EN */ +- xf_emit(ctx, acnt/8, 0); /* ffffffff VTX_ATTR_MASK_UNK0DD0 */ +- xf_emit(ctx, 1, 0); /* 0000000f VP_GP_BUILTIN_ATTR_EN */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- /* SEEK */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 7, 0); /* weird... */ +- else +- xf_emit(ctx, 5, 0); /* weird... */ +-} +- +-static void +-nv50_graph_construct_gene_eng2d(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- /* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */ +- /* SEEK */ +- xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */ +- xf_emit(ctx, 2, 0); /* 0000ffff CLIP_W, CLIP_H */ +- xf_emit(ctx, 1, 0); /* 00000001 CLIP_ENABLE */ +- if (device->chipset < 0xa0) { +- /* this is useless on everything but the original NV50, +- * guess they forgot to nuke it. Or just didn't bother. */ +- xf_emit(ctx, 2, 0); /* 0000ffff IFC_CLIP_X, Y */ +- xf_emit(ctx, 2, 1); /* 0000ffff IFC_CLIP_W, H */ +- xf_emit(ctx, 1, 0); /* 00000001 IFC_CLIP_ENABLE */ +- } +- xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ +- xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ +- xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ +- xf_emit(ctx, 1, 0x11); /* 3f[NV50]/7f[NV84+] DST_FORMAT */ +- xf_emit(ctx, 1, 0); /* 0001ffff DRAW_POINT_X */ +- xf_emit(ctx, 1, 8); /* 0000000f DRAW_UNK58C */ +- xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_X_FRACT */ +- xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_X_INT */ +- xf_emit(ctx, 1, 0); /* 000fffff SIFC_DST_Y_FRACT */ +- xf_emit(ctx, 1, 0); /* 0001ffff SIFC_DST_Y_INT */ +- xf_emit(ctx, 1, 0); /* 000fffff SIFC_DX_DU_FRACT */ +- xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DX_DU_INT */ +- xf_emit(ctx, 1, 0); /* 000fffff SIFC_DY_DV_FRACT */ +- xf_emit(ctx, 1, 1); /* 0001ffff SIFC_DY_DV_INT */ +- xf_emit(ctx, 1, 1); /* 0000ffff SIFC_WIDTH */ +- xf_emit(ctx, 1, 1); /* 0000ffff SIFC_HEIGHT */ +- xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ +- xf_emit(ctx, 1, 2); /* 00000003 SIFC_BITMAP_UNK808 */ +- xf_emit(ctx, 1, 0); /* 00000003 SIFC_BITMAP_LINE_PACK_MODE */ +- xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_LSB_FIRST */ +- xf_emit(ctx, 1, 0); /* 00000001 SIFC_BITMAP_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_X */ +- xf_emit(ctx, 1, 0); /* 0000ffff BLIT_DST_Y */ +- xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ +- xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ +- xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ +- xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ +- xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_W */ +- xf_emit(ctx, 1, 1); /* 0000ffff BLIT_DST_H */ +- xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_X_FRACT */ +- xf_emit(ctx, 1, 0); /* 0001ffff BLIT_SRC_X_INT */ +- xf_emit(ctx, 1, 0); /* 000fffff BLIT_SRC_Y_FRACT */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK888 */ +- xf_emit(ctx, 1, 4); /* 0000003f UNK884 */ +- xf_emit(ctx, 1, 0); /* 00000007 UNK880 */ +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK0FB8 */ +- xf_emit(ctx, 1, 0x15); /* 000000ff tesla UNK128C */ +- xf_emit(ctx, 2, 0); /* 00000007, ffff0ff3 */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK260 */ +- xf_emit(ctx, 1, 0x4444480); /* 1fffffff UNK870 */ +- /* SEEK */ +- xf_emit(ctx, 0x10, 0); +- /* SEEK */ +- xf_emit(ctx, 0x27, 0); +-} +- +-static void +-nv50_graph_construct_gene_csched(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- /* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */ +- /* SEEK */ +- xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1924 */ +- xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* ffffffff turing UNK364 */ +- xf_emit(ctx, 1, 0); /* 0000000f turing UNK36C */ +- xf_emit(ctx, 1, 0); /* 0000ffff USER_PARAM_COUNT */ +- xf_emit(ctx, 1, 0x100); /* 00ffffff turing UNK384 */ +- xf_emit(ctx, 1, 0); /* 0000000f turing UNK2A0 */ +- xf_emit(ctx, 1, 0); /* 0000ffff GRIDID */ +- xf_emit(ctx, 1, 0x10001); /* ffffffff GRIDDIM_XY */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ +- xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ +- xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ +- xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ +- xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ +- xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ +- /* SEEK */ +- xf_emit(ctx, 0x40, 0); /* ffffffff USER_PARAM */ +- switch (device->chipset) { +- case 0x50: +- case 0x92: +- xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ +- xf_emit(ctx, 0x80, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 0x10*2, 0); /* ffffffff, 1f */ +- break; +- case 0x84: +- xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ +- xf_emit(ctx, 0x60, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ +- break; +- case 0x94: +- case 0x96: +- xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ +- xf_emit(ctx, 0x40, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 8*2, 0); /* ffffffff, 1f */ +- break; +- case 0x86: +- case 0x98: +- xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ +- xf_emit(ctx, 0x10, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ +- break; +- case 0xa0: +- xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ +- xf_emit(ctx, 0xf0, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 0x1e*2, 0); /* ffffffff, 1f */ +- break; +- case 0xa3: +- xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ +- xf_emit(ctx, 0x60, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 0xc*2, 0); /* ffffffff, 1f */ +- break; +- case 0xa5: +- case 0xaf: +- xf_emit(ctx, 8, 0); /* 7, 0, 0, 0, ... */ +- xf_emit(ctx, 0x30, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 6*2, 0); /* ffffffff, 1f */ +- break; +- case 0xaa: +- xf_emit(ctx, 0x12, 0); +- break; +- case 0xa8: +- case 0xac: +- xf_emit(ctx, 4, 0); /* f, 0, 0, 0 */ +- xf_emit(ctx, 0x10, 0); /* fff */ +- xf_emit(ctx, 2, 0); /* ff, fff */ +- xf_emit(ctx, 2*2, 0); /* ffffffff, 1f */ +- break; +- } +- xf_emit(ctx, 1, 0); /* 0000000f */ +- xf_emit(ctx, 1, 0); /* 00000000 */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 0000001f */ +- xf_emit(ctx, 4, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 4, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 00000003 turing UNK35C */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 000000ff */ +-} +- +-static void +-nv50_graph_construct_gene_unk1cxx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ +- xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ +- xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ +- xf_emit(ctx, 3, 0); /* 00000001 POLYGON_OFFSET_*_ENABLE */ +- xf_emit(ctx, 1, 4); /* 0000000f CULL_MODE */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ +- xf_emit(ctx, 0x10, 0); /* 00000001 SCISSOR_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ +- xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_UNITS */ +- xf_emit(ctx, 1, 0); /* ffffffff POLYGON_OFFSET_FACTOR */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ +- xf_emit(ctx, 2, 0); /* 07ffffff SCREEN_SCISSOR */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ +- xf_emit(ctx, 8, 0); /* 00000001 RT_HORIZ_LINEAR */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 3); /* 00000003 UNK16B4 */ +- else if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 1); /* 00000001 UNK16B4 */ +- xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ +- xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ +- xf_emit(ctx, 2, 0x04000000); /* 07ffffff tesla UNK0D6C */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ +- xf_emit(ctx, 1, 5); /* 0000000f UNK1408 */ +- xf_emit(ctx, 1, 0x52); /* 000001ff SEMANTIC_PTSZ */ +- xf_emit(ctx, 1, 0); /* ffffffff POINT_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 00000007 tesla UNK0FB4 */ +- if (device->chipset != 0x50) { +- xf_emit(ctx, 1, 0); /* 3ff */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK1110 */ +- } +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ +- xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ +- xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ +- xf_emit(ctx, 1, 0x10); /* 000000ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 0x20, 0); /* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff). */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK187C */ +- xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ +- xf_emit(ctx, 1, 0x8100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 5); /* 0000000f tesla UNK1220 */ +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 000000ff tesla UNK1A20 */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ +- xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ +- if (device->chipset < 0xa0) +- xf_emit(ctx, 0x1c, 0); /* RO */ +- else if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x9, 0); +- xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +- xf_emit(ctx, 1, 0); /* 00000003 WINDOW_ORIGIN */ +- if (device->chipset != 0x50) { +- xf_emit(ctx, 1, 3); /* 00000003 tesla UNK1100 */ +- xf_emit(ctx, 1, 0); /* 3ff */ +- } +- /* XXX: the following block could belong either to unk1cxx, or +- * to STRMOUT. Rather hard to tell. */ +- if (device->chipset < 0xa0) +- xf_emit(ctx, 0x25, 0); +- else +- xf_emit(ctx, 0x3b, 0); +-} +- +-static void +-nv50_graph_construct_gene_strmout(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ +- xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ +- xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ +- if (device->chipset >= 0xa0) { +- xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ +- xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ +- } +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 4); /* 0000007f VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 1, 0x3ff); /* 000003ff tesla UNK0D68 */ +- else +- xf_emit(ctx, 1, 0x7ff); /* 000007ff tesla UNK0D68 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- /* SEEK */ +- xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */ +- xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */ +- xf_emit(ctx, 4, 0); /* 000000ff STRMOUT_ADDRESS_HIGH */ +- xf_emit(ctx, 4, 0); /* ffffffff STRMOUT_ADDRESS_LOW */ +- xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */ +- if (device->chipset >= 0xa0) { +- xf_emit(ctx, 4, 0); /* ffffffff UNK1A8C */ +- xf_emit(ctx, 4, 0); /* ffffffff UNK1780 */ +- } +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_STRMOUT */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ +- xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ +- xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */ +- xf_emit(ctx, 2, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- /* SEEK */ +- xf_emit(ctx, 0x20, 0); /* ffffffff STRMOUT_MAP */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +- xf_emit(ctx, 1, 0); /* 00000000? */ +- xf_emit(ctx, 2, 0); /* ffffffff */ +-} +- +-static void +-nv50_graph_construct_gene_ropm1(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ +- xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +-} +- +-static void +-nv50_graph_construct_gene_ropm2(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 2, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ +- xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ +- xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 7 */ +- /* SEEK */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */ +- xf_emit(ctx, 1, 0); /* 000000ff QUERY_ADDRESS_HIGH */ +- xf_emit(ctx, 2, 0); /* ffffffff QUERY_ADDRESS_LOW, COUNTER */ +- xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */ +- xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */ +- xf_emit(ctx, 1, 0); /* 00000001 eng2d UNK260 */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 0x11); /* 000000ff tesla UNK1968 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +-} +- +-static void +-nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int magic2; +- if (device->chipset == 0x50) { +- magic2 = 0x00003e60; +- } else if (!IS_NVA3F(device->chipset)) { +- magic2 = 0x001ffe67; +- } else { +- magic2 = 0x00087e67; +- } +- xf_emit(ctx, 1, 0); /* f/7 MUTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset)) +- xf_emit(ctx, 1, 0x15); /* 000000ff */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ +- xf_emit(ctx, 1, 0x10); /* 3ff/ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chipset >= 0xa0) { +- xf_emit(ctx, 3, 0); /* ff, ffffffff, ffffffff */ +- xf_emit(ctx, 1, 4); /* 7 */ +- xf_emit(ctx, 1, 0x400); /* fffffff */ +- xf_emit(ctx, 1, 0x300); /* ffff */ +- xf_emit(ctx, 1, 0x1001); /* 1fff */ +- if (device->chipset != 0xa0) { +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 0); /* 0000000f UNK15C8 */ +- else +- xf_emit(ctx, 1, 0x15); /* ff */ +- } +- } +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ +- xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1900 */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ +- xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 0x10, 0); /* ffffffff DEPTH_RANGE_NEAR */ +- xf_emit(ctx, 0x10, 0x3f800000); /* ffffffff DEPTH_RANGE_FAR */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_BACK_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_FUNC_REF */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 2, 0); /* ffffffff DEPTH_BOUNDS */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000007 DEPTH_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 000000ff CLEAR_STENCIL */ +- xf_emit(ctx, 1, 0); /* 00000007 STENCIL_FRONT_FUNC_FUNC */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_FUNC_REF */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 1, 0x10); /* 7f/ff VIEW_VOLUME_CLIP_CTRL */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */ +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 2, 0); /* ffff0ff3, ffff */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff CLEAR_DEPTH */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ +- if (device->chipset >= 0xa0) { +- xf_emit(ctx, 2, 0); +- xf_emit(ctx, 1, 0x1001); +- xf_emit(ctx, 0xb, 0); +- } else { +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- } +- xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f */ +- xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ +- if (device->chipset != 0x50) { +- xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ +- xf_emit(ctx, 1, 0); /* 000000ff */ +- } +- xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ +- xf_emit(ctx, 2, 1); /* 00000007 BLEND_EQUATION_RGB, ALPHA */ +- xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK12E4 */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ +- xf_emit(ctx, 2, 0); /* 00000001 */ +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* 0000000f */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 2, 0); /* 00000001 */ +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- } else if (device->chipset >= 0xa0) { +- xf_emit(ctx, 2, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 2, 0); /* 00000001 */ +- } else { +- xf_emit(ctx, 1, 0); /* 00000007 MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1430 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- } +- xf_emit(ctx, 4, 0); /* ffffffff CLEAR_COLOR */ +- xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR A R G B */ +- xf_emit(ctx, 1, 0); /* 00000fff eng2d UNK2B0 */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 2, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ +- xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f LOGIC_OP */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 0); /* 00000001 UNK12E4? NVA3+ only? */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK15C4 */ +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1140 */ +- } +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ +- xf_emit(ctx, 1, 0); /* 00000007 PATTERN_COLOR_FORMAT */ +- xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 PATTERN_MONO_FORMAT */ +- xf_emit(ctx, 2, 0); /* ffffffff PATTERN_MONO_BITMAP */ +- xf_emit(ctx, 1, 0); /* 00000003 PATTERN_SELECT */ +- xf_emit(ctx, 1, 0); /* 000000ff ROP */ +- xf_emit(ctx, 1, 0); /* ffffffff BETA1 */ +- xf_emit(ctx, 1, 0); /* ffffffff BETA4 */ +- xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ +- xf_emit(ctx, 0x50, 0); /* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */ +-} +- +-static void +-nv50_graph_construct_xfer_unk84xx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int magic3; +- switch (device->chipset) { +- case 0x50: +- magic3 = 0x1000; +- break; +- case 0x86: +- case 0x98: +- case 0xa8: +- case 0xaa: +- case 0xac: +- case 0xaf: +- magic3 = 0x1e00; +- break; +- default: +- magic3 = 0; +- } +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 7f/ff[NVA0+] VP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0); /* 111/113[NVA0+] */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x1f, 0); /* ffffffff */ +- else if (device->chipset >= 0xa0) +- xf_emit(ctx, 0x0f, 0); /* ffffffff */ +- else +- xf_emit(ctx, 0x10, 0); /* fffffff VP_RESULT_MAP_1 up */ +- xf_emit(ctx, 2, 0); /* f/1f[NVA3], fffffff/ffffffff[NVA0+] */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 0x03020100); /* ffffffff */ +- else +- xf_emit(ctx, 1, 0x00608080); /* fffffff VP_RESULT_MAP_0 */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 2, 0); /* 111/113, 7f/ff */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ +- if (magic3) +- xf_emit(ctx, 1, magic3); /* 00007fff tesla UNK141C */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0); /* 111/113 */ +- xf_emit(ctx, 0x1f, 0); /* ffffffff GP_RESULT_MAP_1 up */ +- xf_emit(ctx, 1, 0); /* 0000001f */ +- xf_emit(ctx, 1, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 0x80); /* 0000ffff GP_VERTEX_OUTPUT_COUNT */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0x03020100); /* ffffffff GP_RESULT_MAP_0 */ +- xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ +- if (magic3) +- xf_emit(ctx, 1, magic3); /* 7fff tesla UNK141C */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0); /* 111/113 */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ +- xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK13A0 */ +- xf_emit(ctx, 1, 4); /* 7f/ff VP_REG_ALLOC_RESULT */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- xf_emit(ctx, 1, 0); /* 111/113 */ +- if (device->chipset == 0x94 || device->chipset == 0x96) +- xf_emit(ctx, 0x1020, 0); /* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ +- else if (device->chipset < 0xa0) +- xf_emit(ctx, 0xa20, 0); /* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */ +- else if (!IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x210, 0); /* ffffffff */ +- else +- xf_emit(ctx, 0x410, 0); /* ffffffff */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */ +- xf_emit(ctx, 1, 3); /* 00000003 GP_OUTPUT_PRIMITIVE_TYPE */ +- xf_emit(ctx, 1, 0); /* 00000001 PROVOKING_VERTEX_LAST */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +-} +- +-static void +-nv50_graph_construct_xfer_tprop(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int magic1, magic2; +- if (device->chipset == 0x50) { +- magic1 = 0x3ff; +- magic2 = 0x00003e60; +- } else if (!IS_NVA3F(device->chipset)) { +- magic1 = 0x7ff; +- magic2 = 0x001ffe67; +- } else { +- magic1 = 0x7ff; +- magic2 = 0x00087e67; +- } +- xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* ffffffff ALPHA_TEST_REF */ +- xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000000f UNK16A0 */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_BACK_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 4, 0); /* ffffffff BLEND_COLOR */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK19C0 */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK0FDC */ +- xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ +- xf_emit(ctx, 1, 0); /* ff[NV50]/3ff[NV84+] */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ +- xf_emit(ctx, 3, 0); /* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_BACK_ENABLE */ +- xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ +- xf_emit(ctx, 1, 0); /* 7 */ +- xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff COLOR_KEY */ +- xf_emit(ctx, 1, 0); /* 00000001 COLOR_KEY_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 COLOR_KEY_FORMAT */ +- xf_emit(ctx, 2, 0); /* ffffffff SIFC_BITMAP_COLOR */ +- xf_emit(ctx, 1, 1); /* 00000001 SIFC_BITMAP_WRITE_BIT0_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1298 */ +- } else if (device->chipset >= 0xa0) { +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK16B4 */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- } else { +- xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ +- } +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_RGB */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_RGB */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_SRC_ALPHA */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_DST_ALPHA */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ +- } +- xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ +- xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ +- xf_emit(ctx, 1, 0); /* 7 */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ +- xf_emit(ctx, 1, 0); /* 00000007 OPERATION */ +- xf_emit(ctx, 1, 0xcf); /* 000000ff SIFC_FORMAT */ +- xf_emit(ctx, 1, 0xcf); /* 000000ff DRAW_COLOR_FORMAT */ +- xf_emit(ctx, 1, 0xcf); /* 000000ff SRC_FORMAT */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- xf_emit(ctx, 1, 0); /* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 8, 1); /* 00000001 UNK19E0 */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 1, 0); /* ff */ +- else +- xf_emit(ctx, 3, 0); /* 1, 7, 3ff */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ +- xf_emit(ctx, 1, 0); /* 000fffff BLIT_DU_DX_FRACT */ +- xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DU_DX_INT */ +- xf_emit(ctx, 1, 0); /* 000fffff BLIT_DV_DY_FRACT */ +- xf_emit(ctx, 1, 1); /* 0001ffff BLIT_DV_DY_INT */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, magic1); /* 3ff/7ff tesla UNK0D68 */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 8, 0); /* 0000ffff DMA_COLOR */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_GLOBAL */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_LOCAL */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_STACK */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_DST */ +- xf_emit(ctx, 1, 0); /* 7 */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 8, 0); /* 000000ff RT_ADDRESS_HIGH */ +- xf_emit(ctx, 8, 0); /* ffffffff RT_LAYER_STRIDE */ +- xf_emit(ctx, 8, 0); /* ffffffff RT_ADDRESS_LOW */ +- xf_emit(ctx, 8, 8); /* 0000007f RT_TILE_MODE */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 8, 0x400); /* 0fffffff RT_HORIZ */ +- xf_emit(ctx, 8, 0x300); /* 0000ffff RT_VERT */ +- xf_emit(ctx, 1, 1); /* 00001fff RT_ARRAY_MODE */ +- xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 1, 0x20); /* 00000fff DST_TILE_MODE */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 0x100); /* 0001ffff DST_HEIGHT */ +- xf_emit(ctx, 1, 0); /* 000007ff DST_LAYER */ +- xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */ +- xf_emit(ctx, 1, 0); /* ffffffff DST_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0); /* 000000ff DST_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0x40); /* 0007ffff DST_PITCH */ +- xf_emit(ctx, 1, 0x100); /* 0001ffff DST_WIDTH */ +- xf_emit(ctx, 1, 0); /* 0000ffff */ +- xf_emit(ctx, 1, 3); /* 00000003 tesla UNK15AC */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 2); /* 00000003 tesla UNK143C */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_ZETA */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 2, 0); /* ffff, ff/3ff */ +- xf_emit(ctx, 1, 0); /* 0001ffff GP_BUILTIN_RESULT_EN */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 000000ff STENCIL_FRONT_MASK */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* ffffffff ZETA_LAYER_STRIDE */ +- xf_emit(ctx, 1, 0); /* 000000ff ZETA_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff ZETA_ADDRESS_LOW */ +- xf_emit(ctx, 1, 4); /* 00000007 ZETA_TILE_MODE */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- xf_emit(ctx, 1, 0x400); /* 0fffffff ZETA_HORIZ */ +- xf_emit(ctx, 1, 0x300); /* 0000ffff ZETA_VERT */ +- xf_emit(ctx, 1, 0x1001); /* 00001fff ZETA_ARRAY_MODE */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 0); /* 00000001 */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 3f/7f RT_FORMAT */ +- xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0xf); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 7, 0); /* 0000000f COLOR_MASK */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000003 UNK0F90 */ +- xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ +- xf_emit(ctx, 1, 0); /* 7 */ +- xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- } +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 0x0fac6881); /* fffffff */ +- xf_emit(ctx, 1, magic2); /* 001fffff tesla UNK0F78 */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_BOUNDS_EN */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE_ENABLE */ +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK0FB0 */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000001 STENCIL_FRONT_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK15B4 */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK19CC */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0); /* 00000001 SAMPLECNT_ENABLE */ +- xf_emit(ctx, 1, 0); /* 0000000f ZETA_FORMAT */ +- xf_emit(ctx, 1, 1); /* 00000001 ZETA_ENABLE */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* 0000000f tesla UNK15C8 */ +- } +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A3C */ +- if (device->chipset >= 0xa0) { +- xf_emit(ctx, 3, 0); /* 7/f, 1, ffff0ff3 */ +- xf_emit(ctx, 1, 0xfac6881); /* fffffff */ +- xf_emit(ctx, 4, 0); /* 1, 1, 1, 3ff */ +- xf_emit(ctx, 1, 4); /* 7 */ +- xf_emit(ctx, 1, 0); /* 1 */ +- xf_emit(ctx, 2, 1); /* 1 */ +- xf_emit(ctx, 2, 0); /* 7, f */ +- xf_emit(ctx, 1, 1); /* 1 */ +- xf_emit(ctx, 1, 0); /* 7/f */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 0x9, 0); /* 1 */ +- else +- xf_emit(ctx, 0x8, 0); /* 1 */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 8, 1); /* 1 */ +- xf_emit(ctx, 1, 0x11); /* 7f */ +- xf_emit(ctx, 7, 0); /* 7f */ +- xf_emit(ctx, 1, 0xfac6881); /* fffffff */ +- xf_emit(ctx, 1, 0xf); /* f */ +- xf_emit(ctx, 7, 0); /* f */ +- xf_emit(ctx, 1, 0x11); /* 7f */ +- xf_emit(ctx, 1, 1); /* 1 */ +- xf_emit(ctx, 5, 0); /* 1, 7, 3ff, 3, 7 */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- } +- } +-} +- +-static void +-nv50_graph_construct_xfer_tex(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */ +- if (device->chipset != 0x50) +- xf_emit(ctx, 1, 0); /* 3 */ +- xf_emit(ctx, 1, 1); /* 1ffff BLIT_DU_DX_INT */ +- xf_emit(ctx, 1, 0); /* fffff BLIT_DU_DX_FRACT */ +- xf_emit(ctx, 1, 1); /* 1ffff BLIT_DV_DY_INT */ +- xf_emit(ctx, 1, 0); /* fffff BLIT_DV_DY_FRACT */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 1, 0); /* 3 BLIT_CONTROL */ +- else +- xf_emit(ctx, 2, 0); /* 3ff, 1 */ +- xf_emit(ctx, 1, 0x2a712488); /* ffffffff SRC_TIC_0 */ +- xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_1 */ +- xf_emit(ctx, 1, 0x4085c000); /* ffffffff SRC_TIC_2 */ +- xf_emit(ctx, 1, 0x40); /* ffffffff SRC_TIC_3 */ +- xf_emit(ctx, 1, 0x100); /* ffffffff SRC_TIC_4 */ +- xf_emit(ctx, 1, 0x10100); /* ffffffff SRC_TIC_5 */ +- xf_emit(ctx, 1, 0x02800000); /* ffffffff SRC_TIC_6 */ +- xf_emit(ctx, 1, 0); /* ffffffff SRC_TIC_7 */ +- if (device->chipset == 0x50) { +- xf_emit(ctx, 1, 0); /* 00000001 turing UNK358 */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ +- xf_emit(ctx, 1, 0); /* 00000003 turing UNK37C tesla UNK1690 */ +- xf_emit(ctx, 1, 0); /* 00000003 BLIT_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000001 turing UNK32C tesla UNK0F94 */ +- } else if (!IS_NVAAF(device->chipset)) { +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34? */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1664 / turing UNK03E8 */ +- xf_emit(ctx, 1, 0); /* 00000003 */ +- xf_emit(ctx, 1, 0); /* 000003ff */ +- } else { +- xf_emit(ctx, 0x6, 0); +- } +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_TEXTURE */ +- xf_emit(ctx, 1, 0); /* 0000ffff DMA_SRC */ +-} +- +-static void +-nv50_graph_construct_xfer_unk8cxx(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ +- xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0D64 */ +- xf_emit(ctx, 1, 0x04e3bfdf); /* ffffffff UNK0DF4 */ +- xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK0F98 */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1668 */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_STIPPLE_ENABLE */ +- xf_emit(ctx, 1, 0x00ffff00); /* 00ffffff LINE_STIPPLE_PATTERN */ +- xf_emit(ctx, 1, 0); /* 00000001 POLYGON_SMOOTH_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1658 */ +- xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */ +- xf_emit(ctx, 1, 0); /* ffff0ff3 */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 DEPTH_WRITE */ +- xf_emit(ctx, 1, 1); /* 00000001 UNK15B4 */ +- xf_emit(ctx, 1, 0); /* 00000001 POINT_SPRITE_ENABLE */ +- xf_emit(ctx, 1, 1); /* 00000001 tesla UNK165C */ +- xf_emit(ctx, 1, 0x30201000); /* ffffffff tesla UNK1670 */ +- xf_emit(ctx, 1, 0x70605040); /* ffffffff tesla UNK1670 */ +- xf_emit(ctx, 1, 0xb8a89888); /* ffffffff tesla UNK1670 */ +- xf_emit(ctx, 1, 0xf8e8d8c8); /* ffffffff tesla UNK1670 */ +- xf_emit(ctx, 1, 0); /* 00000001 VERTEX_TWO_SIDE_ENABLE */ +- xf_emit(ctx, 1, 0x1a); /* 0000001f POLYGON_MODE */ +-} +- +-static void +-nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- if (device->chipset < 0xa0) { +- nv50_graph_construct_xfer_unk84xx(ctx); +- nv50_graph_construct_xfer_tprop(ctx); +- nv50_graph_construct_xfer_tex(ctx); +- nv50_graph_construct_xfer_unk8cxx(ctx); +- } else { +- nv50_graph_construct_xfer_tex(ctx); +- nv50_graph_construct_xfer_tprop(ctx); +- nv50_graph_construct_xfer_unk8cxx(ctx); +- nv50_graph_construct_xfer_unk84xx(ctx); +- } +-} +- +-static void +-nv50_graph_construct_xfer_mpc(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i, mpcnt = 2; +- switch (device->chipset) { +- case 0x98: +- case 0xaa: +- mpcnt = 1; +- break; +- case 0x50: +- case 0x84: +- case 0x86: +- case 0x92: +- case 0x94: +- case 0x96: +- case 0xa8: +- case 0xac: +- mpcnt = 2; +- break; +- case 0xa0: +- case 0xa3: +- case 0xa5: +- case 0xaf: +- mpcnt = 3; +- break; +- } +- for (i = 0; i < mpcnt; i++) { +- xf_emit(ctx, 1, 0); /* ff */ +- xf_emit(ctx, 1, 0x80); /* ffffffff tesla UNK1404 */ +- xf_emit(ctx, 1, 0x80007004); /* ffffffff tesla UNK12B0 */ +- xf_emit(ctx, 1, 0x04000400); /* ffffffff */ +- if (device->chipset >= 0xa0) +- xf_emit(ctx, 1, 0xc0); /* 00007fff tesla UNK152C */ +- xf_emit(ctx, 1, 0x1000); /* 0000ffff tesla UNK0D60 */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A30 */ +- if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(device->chipset)) { +- xf_emit(ctx, 1, 0xe00); /* 7fff */ +- xf_emit(ctx, 1, 0x1e00); /* 7fff */ +- } +- xf_emit(ctx, 1, 1); /* 000000ff VP_REG_ALLOC_TEMP */ +- xf_emit(ctx, 1, 0); /* 00000001 LINKED_TSC */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 2, 0x1000); /* 7fff tesla UNK141C */ +- xf_emit(ctx, 1, 1); /* 000000ff GP_REG_ALLOC_TEMP */ +- xf_emit(ctx, 1, 0); /* 00000001 GP_ENABLE */ +- xf_emit(ctx, 1, 4); /* 000000ff FP_REG_ALLOC_TEMP */ +- xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ +- if (IS_NVAAF(device->chipset)) +- xf_emit(ctx, 0xb, 0); /* RO */ +- else if (device->chipset >= 0xa0) +- xf_emit(ctx, 0xc, 0); /* RO */ +- else +- xf_emit(ctx, 0xa, 0); /* RO */ +- } +- xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- if (device->chipset >= 0xa0) { +- xf_emit(ctx, 1, 0x1fe21); /* 0003ffff tesla UNK0FAC */ +- } +- xf_emit(ctx, 3, 0); /* 7fff, 0, 0 */ +- xf_emit(ctx, 1, 0); /* 00000001 tesla UNK1534 */ +- xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */ +- xf_emit(ctx, 4, 0xffff); /* 0000ffff MSAA_MASK */ +- xf_emit(ctx, 1, 1); /* 00000001 LANES32 */ +- xf_emit(ctx, 1, 0x10001); /* 00ffffff BLOCK_ALLOC */ +- xf_emit(ctx, 1, 0x10001); /* ffffffff BLOCKDIM_XY */ +- xf_emit(ctx, 1, 1); /* 0000ffff BLOCKDIM_Z */ +- xf_emit(ctx, 1, 0); /* ffffffff SHARED_SIZE */ +- xf_emit(ctx, 1, 0x1fe21); /* 1ffff/3ffff[NVA0+] tesla UNk0FAC */ +- xf_emit(ctx, 1, 0); /* ffffffff tesla UNK1A34 */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */ +- xf_emit(ctx, 1, 0); /* ff/3ff */ +- xf_emit(ctx, 1, 0); /* 1 LINKED_TSC */ +- xf_emit(ctx, 1, 0); /* ff FP_ADDRESS_HIGH */ +- xf_emit(ctx, 1, 0); /* ffffffff FP_ADDRESS_LOW */ +- xf_emit(ctx, 1, 0x08100c12); /* 1fffffff FP_INTERPOLANT_CTRL */ +- xf_emit(ctx, 1, 4); /* 00000007 FP_CONTROL */ +- xf_emit(ctx, 1, 0); /* 000000ff FRAG_COLOR_CLAMP_EN */ +- xf_emit(ctx, 1, 2); /* 00000003 REG_MODE */ +- xf_emit(ctx, 1, 0x11); /* 0000007f RT_FORMAT */ +- xf_emit(ctx, 7, 0); /* 0000007f RT_FORMAT */ +- xf_emit(ctx, 1, 0); /* 00000007 */ +- xf_emit(ctx, 1, 0xfac6881); /* 0fffffff RT_CONTROL */ +- xf_emit(ctx, 1, 0); /* 00000003 MULTISAMPLE_CTRL */ +- if (IS_NVA3F(device->chipset)) +- xf_emit(ctx, 1, 3); /* 00000003 tesla UNK16B4 */ +- xf_emit(ctx, 1, 0); /* 00000001 ALPHA_TEST_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000007 ALPHA_TEST_FUNC */ +- xf_emit(ctx, 1, 0); /* 00000001 FRAMEBUFFER_SRGB */ +- xf_emit(ctx, 1, 4); /* ffffffff tesla UNK1400 */ +- xf_emit(ctx, 8, 0); /* 00000001 BLEND_ENABLE */ +- xf_emit(ctx, 1, 0); /* 00000001 LOGIC_OP_ENABLE */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_RGB */ +- xf_emit(ctx, 1, 2); /* 0000001f BLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 1, 1); /* 0000001f BLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 1, 1); /* 00000007 BLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 1, 1); /* 00000001 UNK133C */ +- if (IS_NVA3F(device->chipset)) { +- xf_emit(ctx, 1, 0); /* 00000001 UNK12E4 */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_RGB */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_RGB */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_RGB */ +- xf_emit(ctx, 8, 2); /* 0000001f IBLEND_FUNC_SRC_ALPHA */ +- xf_emit(ctx, 8, 1); /* 0000001f IBLEND_FUNC_DST_ALPHA */ +- xf_emit(ctx, 8, 1); /* 00000007 IBLEND_EQUATION_ALPHA */ +- xf_emit(ctx, 8, 1); /* 00000001 IBLEND_UNK00 */ +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK1928 */ +- xf_emit(ctx, 1, 0); /* 00000001 UNK1140 */ +- } +- xf_emit(ctx, 1, 0); /* 00000003 tesla UNK0F90 */ +- xf_emit(ctx, 1, 4); /* 000000ff FP_RESULT_COUNT */ +- /* XXX: demagic this part some day */ +- if (device->chipset == 0x50) +- xf_emit(ctx, 0x3a0, 0); +- else if (device->chipset < 0x94) +- xf_emit(ctx, 0x3a2, 0); +- else if (device->chipset == 0x98 || device->chipset == 0xaa) +- xf_emit(ctx, 0x39f, 0); +- else +- xf_emit(ctx, 0x3a3, 0); +- xf_emit(ctx, 1, 0x11); /* 3f/7f DST_FORMAT */ +- xf_emit(ctx, 1, 0); /* 7 OPERATION */ +- xf_emit(ctx, 1, 1); /* 1 DST_LINEAR */ +- xf_emit(ctx, 0x2d, 0); +-} +- +-static void +-nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) +-{ +- struct nouveau_device *device = ctx->device; +- int i; +- u32 offset; +- u32 units = nv_rd32 (ctx->device, 0x1540); +- int size = 0; +- +- offset = (ctx->ctxvals_pos+0x3f)&~0x3f; +- +- if (device->chipset < 0xa0) { +- for (i = 0; i < 8; i++) { +- ctx->ctxvals_pos = offset + i; +- /* that little bugger belongs to csched. No idea +- * what it's doing here. */ +- if (i == 0) +- xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ +- if (units & (1 << i)) +- nv50_graph_construct_xfer_mpc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- } +- } else { +- /* Strand 0: TPs 0, 1 */ +- ctx->ctxvals_pos = offset; +- /* that little bugger belongs to csched. No idea +- * what it's doing here. */ +- xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */ +- if (units & (1 << 0)) +- nv50_graph_construct_xfer_mpc(ctx); +- if (units & (1 << 1)) +- nv50_graph_construct_xfer_mpc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 1: TPs 2, 3 */ +- ctx->ctxvals_pos = offset + 1; +- if (units & (1 << 2)) +- nv50_graph_construct_xfer_mpc(ctx); +- if (units & (1 << 3)) +- nv50_graph_construct_xfer_mpc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 2: TPs 4, 5, 6 */ +- ctx->ctxvals_pos = offset + 2; +- if (units & (1 << 4)) +- nv50_graph_construct_xfer_mpc(ctx); +- if (units & (1 << 5)) +- nv50_graph_construct_xfer_mpc(ctx); +- if (units & (1 << 6)) +- nv50_graph_construct_xfer_mpc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- +- /* Strand 3: TPs 7, 8, 9 */ +- ctx->ctxvals_pos = offset + 3; +- if (units & (1 << 7)) +- nv50_graph_construct_xfer_mpc(ctx); +- if (units & (1 << 8)) +- nv50_graph_construct_xfer_mpc(ctx); +- if (units & (1 << 9)) +- nv50_graph_construct_xfer_mpc(ctx); +- if ((ctx->ctxvals_pos-offset)/8 > size) +- size = (ctx->ctxvals_pos-offset)/8; +- } +- ctx->ctxvals_pos = offset + size * 8; +- ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; +- cp_lsr (ctx, offset); +- cp_out (ctx, CP_SET_XFER_POINTER); +- cp_lsr (ctx, size); +- cp_out (ctx, CP_SEEK_2); +- cp_out (ctx, CP_XFER_2); +- cp_wait(ctx, XFER, BUSY); +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +deleted file mode 100644 +index b8e5fe60..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c ++++ /dev/null +@@ -1,1386 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000b2, 40, 0x01, 0x00000000 }, +- { 0x000210, 8, 0x01, 0x00000040 }, +- { 0x000218, 8, 0x01, 0x0000c080 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00001fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x003fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x0005e0, 5, 0x01, 0x00000022 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x00000c48 }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00300008 }, +- { 0x000841, 1, 0x01, 0x04000080 }, +- { 0x000842, 1, 0x01, 0x00300008 }, +- { 0x000843, 1, 0x01, 0x04000080 }, +- { 0x000818, 8, 0x01, 0x00000000 }, +- { 0x000848, 16, 0x01, 0x00000000 }, +- { 0x000738, 1, 0x01, 0x00000000 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x000944, 1, 0x01, 0x00000022 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000014 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvc0_grctx_pack_icmd[] = { +- { nvc0_grctx_init_icmd_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_9097_0[] = { +- { 0x000800, 8, 0x40, 0x00000000 }, +- { 0x000804, 8, 0x40, 0x00000000 }, +- { 0x000808, 8, 0x40, 0x00000400 }, +- { 0x00080c, 8, 0x40, 0x00000300 }, +- { 0x000810, 1, 0x04, 0x000000cf }, +- { 0x000850, 7, 0x40, 0x00000000 }, +- { 0x000814, 8, 0x40, 0x00000040 }, +- { 0x000818, 8, 0x40, 0x00000001 }, +- { 0x00081c, 8, 0x40, 0x00000000 }, +- { 0x000820, 8, 0x40, 0x00000000 }, +- { 0x002700, 8, 0x20, 0x00000000 }, +- { 0x002704, 8, 0x20, 0x00000000 }, +- { 0x002708, 8, 0x20, 0x00000000 }, +- { 0x00270c, 8, 0x20, 0x00000000 }, +- { 0x002710, 8, 0x20, 0x00014000 }, +- { 0x002714, 8, 0x20, 0x00000040 }, +- { 0x001c00, 16, 0x10, 0x00000000 }, +- { 0x001c04, 16, 0x10, 0x00000000 }, +- { 0x001c08, 16, 0x10, 0x00000000 }, +- { 0x001c0c, 16, 0x10, 0x00000000 }, +- { 0x001d00, 16, 0x10, 0x00000000 }, +- { 0x001d04, 16, 0x10, 0x00000000 }, +- { 0x001d08, 16, 0x10, 0x00000000 }, +- { 0x001d0c, 16, 0x10, 0x00000000 }, +- { 0x001f00, 16, 0x08, 0x00000000 }, +- { 0x001f04, 16, 0x08, 0x00000000 }, +- { 0x001f80, 16, 0x08, 0x00000000 }, +- { 0x001f84, 16, 0x08, 0x00000000 }, +- { 0x002200, 5, 0x10, 0x00000022 }, +- { 0x002000, 1, 0x04, 0x00000000 }, +- { 0x002040, 1, 0x04, 0x00000011 }, +- { 0x002080, 1, 0x04, 0x00000020 }, +- { 0x0020c0, 1, 0x04, 0x00000030 }, +- { 0x002100, 1, 0x04, 0x00000040 }, +- { 0x002140, 1, 0x04, 0x00000051 }, +- { 0x00200c, 6, 0x40, 0x00000001 }, +- { 0x002010, 1, 0x04, 0x00000000 }, +- { 0x002050, 1, 0x04, 0x00000000 }, +- { 0x002090, 1, 0x04, 0x00000001 }, +- { 0x0020d0, 1, 0x04, 0x00000002 }, +- { 0x002110, 1, 0x04, 0x00000003 }, +- { 0x002150, 1, 0x04, 0x00000004 }, +- { 0x000380, 4, 0x20, 0x00000000 }, +- { 0x000384, 4, 0x20, 0x00000000 }, +- { 0x000388, 4, 0x20, 0x00000000 }, +- { 0x00038c, 4, 0x20, 0x00000000 }, +- { 0x000700, 4, 0x10, 0x00000000 }, +- { 0x000704, 4, 0x10, 0x00000000 }, +- { 0x000708, 4, 0x10, 0x00000000 }, +- { 0x002800, 128, 0x04, 0x00000000 }, +- { 0x000a00, 16, 0x20, 0x00000000 }, +- { 0x000a04, 16, 0x20, 0x00000000 }, +- { 0x000a08, 16, 0x20, 0x00000000 }, +- { 0x000a0c, 16, 0x20, 0x00000000 }, +- { 0x000a10, 16, 0x20, 0x00000000 }, +- { 0x000a14, 16, 0x20, 0x00000000 }, +- { 0x000c00, 16, 0x10, 0x00000000 }, +- { 0x000c04, 16, 0x10, 0x00000000 }, +- { 0x000c08, 16, 0x10, 0x00000000 }, +- { 0x000c0c, 16, 0x10, 0x3f800000 }, +- { 0x000d00, 8, 0x08, 0xffff0000 }, +- { 0x000d04, 8, 0x08, 0xffff0000 }, +- { 0x000e00, 16, 0x10, 0x00000000 }, +- { 0x000e04, 16, 0x10, 0xffff0000 }, +- { 0x000e08, 16, 0x10, 0xffff0000 }, +- { 0x000d40, 4, 0x08, 0x00000000 }, +- { 0x000d44, 4, 0x08, 0x00000000 }, +- { 0x001e00, 8, 0x20, 0x00000001 }, +- { 0x001e04, 8, 0x20, 0x00000001 }, +- { 0x001e08, 8, 0x20, 0x00000002 }, +- { 0x001e0c, 8, 0x20, 0x00000001 }, +- { 0x001e10, 8, 0x20, 0x00000001 }, +- { 0x001e14, 8, 0x20, 0x00000002 }, +- { 0x001e18, 8, 0x20, 0x00000001 }, +- { 0x003400, 128, 0x04, 0x00000000 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x001514, 1, 0x04, 0x00000000 }, +- { 0x000d68, 1, 0x04, 0x0000ffff }, +- { 0x00121c, 1, 0x04, 0x0fac6881 }, +- { 0x000fac, 1, 0x04, 0x00000001 }, +- { 0x001538, 1, 0x04, 0x00000001 }, +- { 0x000fe0, 2, 0x04, 0x00000000 }, +- { 0x000fe8, 1, 0x04, 0x00000014 }, +- { 0x000fec, 1, 0x04, 0x00000040 }, +- { 0x000ff0, 1, 0x04, 0x00000000 }, +- { 0x00179c, 1, 0x04, 0x00000000 }, +- { 0x001228, 1, 0x04, 0x00000400 }, +- { 0x00122c, 1, 0x04, 0x00000300 }, +- { 0x001230, 1, 0x04, 0x00010001 }, +- { 0x0007f8, 1, 0x04, 0x00000000 }, +- { 0x0015b4, 1, 0x04, 0x00000001 }, +- { 0x0015cc, 1, 0x04, 0x00000000 }, +- { 0x001534, 1, 0x04, 0x00000000 }, +- { 0x000fb0, 1, 0x04, 0x00000000 }, +- { 0x0015d0, 1, 0x04, 0x00000000 }, +- { 0x00153c, 1, 0x04, 0x00000000 }, +- { 0x0016b4, 1, 0x04, 0x00000003 }, +- { 0x000fbc, 4, 0x04, 0x0000ffff }, +- { 0x000df8, 2, 0x04, 0x00000000 }, +- { 0x001948, 1, 0x04, 0x00000000 }, +- { 0x001970, 1, 0x04, 0x00000001 }, +- { 0x00161c, 1, 0x04, 0x000009f0 }, +- { 0x000dcc, 1, 0x04, 0x00000010 }, +- { 0x00163c, 1, 0x04, 0x00000000 }, +- { 0x0015e4, 1, 0x04, 0x00000000 }, +- { 0x001160, 32, 0x04, 0x25e00040 }, +- { 0x001880, 32, 0x04, 0x00000000 }, +- { 0x000f84, 2, 0x04, 0x00000000 }, +- { 0x0017c8, 2, 0x04, 0x00000000 }, +- { 0x0017d0, 1, 0x04, 0x000000ff }, +- { 0x0017d4, 1, 0x04, 0xffffffff }, +- { 0x0017d8, 1, 0x04, 0x00000002 }, +- { 0x0017dc, 1, 0x04, 0x00000000 }, +- { 0x0015f4, 2, 0x04, 0x00000000 }, +- { 0x001434, 2, 0x04, 0x00000000 }, +- { 0x000d74, 1, 0x04, 0x00000000 }, +- { 0x000dec, 1, 0x04, 0x00000001 }, +- { 0x0013a4, 1, 0x04, 0x00000000 }, +- { 0x001318, 1, 0x04, 0x00000001 }, +- { 0x001644, 1, 0x04, 0x00000000 }, +- { 0x000748, 1, 0x04, 0x00000000 }, +- { 0x000de8, 1, 0x04, 0x00000000 }, +- { 0x001648, 1, 0x04, 0x00000000 }, +- { 0x0012a4, 1, 0x04, 0x00000000 }, +- { 0x001120, 4, 0x04, 0x00000000 }, +- { 0x001118, 1, 0x04, 0x00000000 }, +- { 0x00164c, 1, 0x04, 0x00000000 }, +- { 0x001658, 1, 0x04, 0x00000000 }, +- { 0x001910, 1, 0x04, 0x00000290 }, +- { 0x001518, 1, 0x04, 0x00000000 }, +- { 0x00165c, 1, 0x04, 0x00000001 }, +- { 0x001520, 1, 0x04, 0x00000000 }, +- { 0x001604, 1, 0x04, 0x00000000 }, +- { 0x001570, 1, 0x04, 0x00000000 }, +- { 0x0013b0, 2, 0x04, 0x3f800000 }, +- { 0x00020c, 1, 0x04, 0x00000000 }, +- { 0x001670, 1, 0x04, 0x30201000 }, +- { 0x001674, 1, 0x04, 0x70605040 }, +- { 0x001678, 1, 0x04, 0xb8a89888 }, +- { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, +- { 0x00166c, 1, 0x04, 0x00000000 }, +- { 0x001680, 1, 0x04, 0x00ffff00 }, +- { 0x0012d0, 1, 0x04, 0x00000003 }, +- { 0x0012d4, 1, 0x04, 0x00000002 }, +- { 0x001684, 2, 0x04, 0x00000000 }, +- { 0x000dac, 2, 0x04, 0x00001b02 }, +- { 0x000db4, 1, 0x04, 0x00000000 }, +- { 0x00168c, 1, 0x04, 0x00000000 }, +- { 0x0015bc, 1, 0x04, 0x00000000 }, +- { 0x00156c, 1, 0x04, 0x00000000 }, +- { 0x00187c, 1, 0x04, 0x00000000 }, +- { 0x001110, 1, 0x04, 0x00000001 }, +- { 0x000dc0, 3, 0x04, 0x00000000 }, +- { 0x001234, 1, 0x04, 0x00000000 }, +- { 0x001690, 1, 0x04, 0x00000000 }, +- { 0x0012ac, 1, 0x04, 0x00000001 }, +- { 0x0002c4, 1, 0x04, 0x00000000 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x001000, 1, 0x04, 0x00000010 }, +- { 0x0010fc, 1, 0x04, 0x00000000 }, +- { 0x001290, 1, 0x04, 0x00000000 }, +- { 0x000218, 1, 0x04, 0x00000010 }, +- { 0x0012d8, 1, 0x04, 0x00000000 }, +- { 0x0012dc, 1, 0x04, 0x00000010 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x00155c, 2, 0x04, 0x00000000 }, +- { 0x001564, 1, 0x04, 0x00001fff }, +- { 0x001574, 2, 0x04, 0x00000000 }, +- { 0x00157c, 1, 0x04, 0x003fffff }, +- { 0x001354, 1, 0x04, 0x00000000 }, +- { 0x001664, 1, 0x04, 0x00000000 }, +- { 0x001610, 1, 0x04, 0x00000012 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x00162c, 1, 0x04, 0x00000003 }, +- { 0x000210, 1, 0x04, 0x00000000 }, +- { 0x000320, 1, 0x04, 0x00000000 }, +- { 0x000324, 6, 0x04, 0x3f800000 }, +- { 0x000750, 1, 0x04, 0x00000000 }, +- { 0x000760, 1, 0x04, 0x39291909 }, +- { 0x000764, 1, 0x04, 0x79695949 }, +- { 0x000768, 1, 0x04, 0xb9a99989 }, +- { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x000770, 1, 0x04, 0x30201000 }, +- { 0x000774, 1, 0x04, 0x70605040 }, +- { 0x000778, 1, 0x04, 0x00009080 }, +- { 0x000780, 1, 0x04, 0x39291909 }, +- { 0x000784, 1, 0x04, 0x79695949 }, +- { 0x000788, 1, 0x04, 0xb9a99989 }, +- { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x0007d0, 1, 0x04, 0x30201000 }, +- { 0x0007d4, 1, 0x04, 0x70605040 }, +- { 0x0007d8, 1, 0x04, 0x00009080 }, +- { 0x00037c, 1, 0x04, 0x00000001 }, +- { 0x000740, 2, 0x04, 0x00000000 }, +- { 0x002600, 1, 0x04, 0x00000000 }, +- { 0x001918, 1, 0x04, 0x00000000 }, +- { 0x00191c, 1, 0x04, 0x00000900 }, +- { 0x001920, 1, 0x04, 0x00000405 }, +- { 0x001308, 1, 0x04, 0x00000001 }, +- { 0x001924, 1, 0x04, 0x00000000 }, +- { 0x0013ac, 1, 0x04, 0x00000000 }, +- { 0x00192c, 1, 0x04, 0x00000001 }, +- { 0x00193c, 1, 0x04, 0x00002c1c }, +- { 0x000d7c, 1, 0x04, 0x00000000 }, +- { 0x000f8c, 1, 0x04, 0x00000000 }, +- { 0x0002c0, 1, 0x04, 0x00000001 }, +- { 0x001510, 1, 0x04, 0x00000000 }, +- { 0x001940, 1, 0x04, 0x00000000 }, +- { 0x000ff4, 2, 0x04, 0x00000000 }, +- { 0x00194c, 2, 0x04, 0x00000000 }, +- { 0x001968, 1, 0x04, 0x00000000 }, +- { 0x001590, 1, 0x04, 0x0000003f }, +- { 0x0007e8, 4, 0x04, 0x00000000 }, +- { 0x00196c, 1, 0x04, 0x00000011 }, +- { 0x00197c, 1, 0x04, 0x00000000 }, +- { 0x000fcc, 2, 0x04, 0x00000000 }, +- { 0x0002d8, 1, 0x04, 0x00000040 }, +- { 0x001980, 1, 0x04, 0x00000080 }, +- { 0x001504, 1, 0x04, 0x00000080 }, +- { 0x001984, 1, 0x04, 0x00000000 }, +- { 0x000300, 1, 0x04, 0x00000001 }, +- { 0x0013a8, 1, 0x04, 0x00000000 }, +- { 0x0012ec, 1, 0x04, 0x00000000 }, +- { 0x001310, 1, 0x04, 0x00000000 }, +- { 0x001314, 1, 0x04, 0x00000001 }, +- { 0x001380, 1, 0x04, 0x00000000 }, +- { 0x001384, 4, 0x04, 0x00000001 }, +- { 0x001394, 1, 0x04, 0x00000000 }, +- { 0x00139c, 1, 0x04, 0x00000000 }, +- { 0x001398, 1, 0x04, 0x00000000 }, +- { 0x001594, 1, 0x04, 0x00000000 }, +- { 0x001598, 4, 0x04, 0x00000001 }, +- { 0x000f54, 3, 0x04, 0x00000000 }, +- { 0x0019bc, 1, 0x04, 0x00000000 }, +- { 0x000f9c, 2, 0x04, 0x00000000 }, +- { 0x0012cc, 1, 0x04, 0x00000000 }, +- { 0x0012e8, 1, 0x04, 0x00000000 }, +- { 0x00130c, 1, 0x04, 0x00000001 }, +- { 0x001360, 8, 0x04, 0x00000000 }, +- { 0x00133c, 2, 0x04, 0x00000001 }, +- { 0x001344, 1, 0x04, 0x00000002 }, +- { 0x001348, 2, 0x04, 0x00000001 }, +- { 0x001350, 1, 0x04, 0x00000002 }, +- { 0x001358, 1, 0x04, 0x00000001 }, +- { 0x0012e4, 1, 0x04, 0x00000000 }, +- { 0x00131c, 4, 0x04, 0x00000000 }, +- { 0x0019c0, 1, 0x04, 0x00000000 }, +- { 0x001140, 1, 0x04, 0x00000000 }, +- { 0x0019c4, 1, 0x04, 0x00000000 }, +- { 0x0019c8, 1, 0x04, 0x00001500 }, +- { 0x00135c, 1, 0x04, 0x00000000 }, +- { 0x000f90, 1, 0x04, 0x00000000 }, +- { 0x0019e0, 8, 0x04, 0x00000001 }, +- { 0x0019cc, 1, 0x04, 0x00000001 }, +- { 0x0015b8, 1, 0x04, 0x00000000 }, +- { 0x001a00, 1, 0x04, 0x00001111 }, +- { 0x001a04, 7, 0x04, 0x00000000 }, +- { 0x000d6c, 2, 0x04, 0xffff0000 }, +- { 0x0010f8, 1, 0x04, 0x00001010 }, +- { 0x000d80, 5, 0x04, 0x00000000 }, +- { 0x000da0, 1, 0x04, 0x00000000 }, +- { 0x001508, 1, 0x04, 0x80000000 }, +- { 0x00150c, 1, 0x04, 0x40000000 }, +- { 0x001668, 1, 0x04, 0x00000000 }, +- { 0x000318, 2, 0x04, 0x00000008 }, +- { 0x000d9c, 1, 0x04, 0x00000001 }, +- { 0x0007dc, 1, 0x04, 0x00000000 }, +- { 0x00074c, 1, 0x04, 0x00000055 }, +- { 0x001420, 1, 0x04, 0x00000003 }, +- { 0x0017bc, 2, 0x04, 0x00000000 }, +- { 0x0017c4, 1, 0x04, 0x00000001 }, +- { 0x001008, 1, 0x04, 0x00000008 }, +- { 0x00100c, 1, 0x04, 0x00000040 }, +- { 0x001010, 1, 0x04, 0x0000012c }, +- { 0x000d60, 1, 0x04, 0x00000040 }, +- { 0x00075c, 1, 0x04, 0x00000003 }, +- { 0x001018, 1, 0x04, 0x00000020 }, +- { 0x00101c, 1, 0x04, 0x00000001 }, +- { 0x001020, 1, 0x04, 0x00000020 }, +- { 0x001024, 1, 0x04, 0x00000001 }, +- { 0x001444, 3, 0x04, 0x00000000 }, +- { 0x000360, 1, 0x04, 0x20164010 }, +- { 0x000364, 1, 0x04, 0x00000020 }, +- { 0x000368, 1, 0x04, 0x00000000 }, +- { 0x000de4, 1, 0x04, 0x00000000 }, +- { 0x000204, 1, 0x04, 0x00000006 }, +- { 0x000208, 1, 0x04, 0x00000000 }, +- { 0x0002cc, 1, 0x04, 0x003fffff }, +- { 0x0002d0, 1, 0x04, 0x00000c48 }, +- { 0x001220, 1, 0x04, 0x00000005 }, +- { 0x000fdc, 1, 0x04, 0x00000000 }, +- { 0x000f98, 1, 0x04, 0x00300008 }, +- { 0x001284, 1, 0x04, 0x04000080 }, +- { 0x001450, 1, 0x04, 0x00300008 }, +- { 0x001454, 1, 0x04, 0x04000080 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_902d_0[] = { +- { 0x000200, 1, 0x04, 0x000000cf }, +- { 0x000204, 1, 0x04, 0x00000001 }, +- { 0x000208, 1, 0x04, 0x00000020 }, +- { 0x00020c, 1, 0x04, 0x00000001 }, +- { 0x000210, 1, 0x04, 0x00000000 }, +- { 0x000214, 1, 0x04, 0x00000080 }, +- { 0x000218, 2, 0x04, 0x00000100 }, +- { 0x000220, 2, 0x04, 0x00000000 }, +- { 0x000230, 1, 0x04, 0x000000cf }, +- { 0x000234, 1, 0x04, 0x00000001 }, +- { 0x000238, 1, 0x04, 0x00000020 }, +- { 0x00023c, 1, 0x04, 0x00000001 }, +- { 0x000244, 1, 0x04, 0x00000080 }, +- { 0x000248, 2, 0x04, 0x00000100 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_9039_0[] = { +- { 0x00030c, 3, 0x04, 0x00000000 }, +- { 0x000320, 1, 0x04, 0x00000000 }, +- { 0x000238, 2, 0x04, 0x00000000 }, +- { 0x000318, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_90c0_0[] = { +- { 0x00270c, 8, 0x20, 0x00000000 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x000758, 1, 0x04, 0x00000100 }, +- { 0x0002c4, 1, 0x04, 0x00000000 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x000204, 3, 0x04, 0x00000000 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- { 0x00024c, 1, 0x04, 0x00000000 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x001664, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvc0_grctx_pack_mthd[] = { +- { nvc0_grctx_init_9097_0, 0x9097 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- { nvc0_grctx_init_9039_0, 0x9039 }, +- { nvc0_grctx_init_90c0_0, 0x90c0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_main_0[] = { +- { 0x400204, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_fe_0[] = { +- { 0x404004, 11, 0x04, 0x00000000 }, +- { 0x404044, 1, 0x04, 0x00000000 }, +- { 0x404094, 13, 0x04, 0x00000000 }, +- { 0x4040c8, 1, 0x04, 0xf0000087 }, +- { 0x4040d0, 6, 0x04, 0x00000000 }, +- { 0x4040e8, 1, 0x04, 0x00001000 }, +- { 0x4040f8, 1, 0x04, 0x00000000 }, +- { 0x404130, 2, 0x04, 0x00000000 }, +- { 0x404138, 1, 0x04, 0x20000040 }, +- { 0x404150, 1, 0x04, 0x0000002e }, +- { 0x404154, 1, 0x04, 0x00000400 }, +- { 0x404158, 1, 0x04, 0x00000200 }, +- { 0x404164, 1, 0x04, 0x00000055 }, +- { 0x404168, 1, 0x04, 0x00000000 }, +- { 0x404174, 3, 0x04, 0x00000000 }, +- { 0x404200, 8, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_pri_0[] = { +- { 0x404404, 14, 0x04, 0x00000000 }, +- { 0x404460, 2, 0x04, 0x00000000 }, +- { 0x404468, 1, 0x04, 0x00ffffff }, +- { 0x40446c, 1, 0x04, 0x00000000 }, +- { 0x404480, 1, 0x04, 0x00000001 }, +- { 0x404498, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_memfmt_0[] = { +- { 0x404604, 1, 0x04, 0x00000015 }, +- { 0x404608, 1, 0x04, 0x00000000 }, +- { 0x40460c, 1, 0x04, 0x00002e00 }, +- { 0x404610, 1, 0x04, 0x00000100 }, +- { 0x404618, 8, 0x04, 0x00000000 }, +- { 0x404638, 1, 0x04, 0x00000004 }, +- { 0x40463c, 8, 0x04, 0x00000000 }, +- { 0x40465c, 1, 0x04, 0x007f0100 }, +- { 0x404660, 7, 0x04, 0x00000000 }, +- { 0x40467c, 1, 0x04, 0x00000002 }, +- { 0x404680, 8, 0x04, 0x00000000 }, +- { 0x4046a0, 1, 0x04, 0x007f0080 }, +- { 0x4046a4, 18, 0x04, 0x00000000 }, +- { 0x4046f0, 2, 0x04, 0x00000000 }, +- { 0x404700, 13, 0x04, 0x00000000 }, +- { 0x404734, 1, 0x04, 0x00000100 }, +- { 0x404738, 8, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x078000bf }, +- { 0x405830, 1, 0x04, 0x02180000 }, +- { 0x405834, 2, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x000103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b4, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_rstr2d_0[] = { +- { 0x407804, 1, 0x04, 0x00000023 }, +- { 0x40780c, 1, 0x04, 0x0a418820 }, +- { 0x407810, 1, 0x04, 0x062080e6 }, +- { 0x407814, 1, 0x04, 0x020398a4 }, +- { 0x407818, 1, 0x04, 0x0e629062 }, +- { 0x40781c, 1, 0x04, 0x0a418820 }, +- { 0x407820, 1, 0x04, 0x000000e6 }, +- { 0x4078bc, 1, 0x04, 0x00000103 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_scc_0[] = { +- { 0x408000, 2, 0x04, 0x00000000 }, +- { 0x408008, 1, 0x04, 0x00000018 }, +- { 0x40800c, 2, 0x04, 0x00000000 }, +- { 0x408014, 1, 0x04, 0x00000069 }, +- { 0x408018, 1, 0x04, 0xe100e100 }, +- { 0x408064, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x02802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x0003e00d }, +- { 0x408900, 1, 0x04, 0x3080b801 }, +- { 0x408904, 1, 0x04, 0x02000001 }, +- { 0x408908, 1, 0x04, 0x00c80929 }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvc0_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nvc0_grctx_init_fe_0 }, +- { nvc0_grctx_init_pri_0 }, +- { nvc0_grctx_init_memfmt_0 }, +- { nvc0_grctx_init_ds_0 }, +- { nvc0_grctx_init_pd_0 }, +- { nvc0_grctx_init_rstr2d_0 }, +- { nvc0_grctx_init_scc_0 }, +- { nvc0_grctx_init_be_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_gpc_unk_0[] = { +- { 0x418380, 1, 0x04, 0x00000016 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_prop_0[] = { +- { 0x418400, 1, 0x04, 0x38004e00 }, +- { 0x418404, 1, 0x04, 0x71e0ffff }, +- { 0x418408, 1, 0x04, 0x00000000 }, +- { 0x41840c, 1, 0x04, 0x00001008 }, +- { 0x418410, 1, 0x04, 0x0fff0fff }, +- { 0x418414, 1, 0x04, 0x00200fff }, +- { 0x418450, 6, 0x04, 0x00000000 }, +- { 0x418468, 1, 0x04, 0x00000001 }, +- { 0x41846c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_gpc_unk_1[] = { +- { 0x418600, 1, 0x04, 0x0000001f }, +- { 0x418684, 1, 0x04, 0x0000000f }, +- { 0x418700, 1, 0x04, 0x00000002 }, +- { 0x418704, 1, 0x04, 0x00000080 }, +- { 0x418708, 1, 0x04, 0x00000000 }, +- { 0x41870c, 1, 0x04, 0x07c80000 }, +- { 0x418710, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x0006860a }, +- { 0x418808, 3, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00008442 }, +- { 0x418830, 1, 0x04, 0x00000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x00100000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_zcull_0[] = { +- { 0x41891c, 1, 0x04, 0x00ff00ff }, +- { 0x418924, 1, 0x04, 0x00000000 }, +- { 0x418928, 1, 0x04, 0x00ffff00 }, +- { 0x41892c, 1, 0x04, 0x0000ff00 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_crstr_0[] = { +- { 0x418b00, 1, 0x04, 0x00000000 }, +- { 0x418b08, 1, 0x04, 0x0a418820 }, +- { 0x418b0c, 1, 0x04, 0x062080e6 }, +- { 0x418b10, 1, 0x04, 0x020398a4 }, +- { 0x418b14, 1, 0x04, 0x0e629062 }, +- { 0x418b18, 1, 0x04, 0x0a418820 }, +- { 0x418b1c, 1, 0x04, 0x000000e6 }, +- { 0x418bb8, 1, 0x04, 0x00000103 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_gpm_0[] = { +- { 0x418c08, 1, 0x04, 0x00000001 }, +- { 0x418c10, 8, 0x04, 0x00000000 }, +- { 0x418c80, 1, 0x04, 0x20200004 }, +- { 0x418c8c, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_gcc_0[] = { +- { 0x419000, 1, 0x04, 0x00000780 }, +- { 0x419004, 2, 0x04, 0x00000000 }, +- { 0x419014, 1, 0x04, 0x00000004 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvc0_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvc0_grctx_init_prop_0 }, +- { nvc0_grctx_init_gpc_unk_1 }, +- { nvc0_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvc0_grctx_init_crstr_0 }, +- { nvc0_grctx_init_gpm_0 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_zcullr_0[] = { +- { 0x418a00, 3, 0x04, 0x00000000 }, +- { 0x418a0c, 1, 0x04, 0x00010000 }, +- { 0x418a10, 3, 0x04, 0x00000000 }, +- { 0x418a20, 3, 0x04, 0x00000000 }, +- { 0x418a2c, 1, 0x04, 0x00010000 }, +- { 0x418a30, 3, 0x04, 0x00000000 }, +- { 0x418a40, 3, 0x04, 0x00000000 }, +- { 0x418a4c, 1, 0x04, 0x00010000 }, +- { 0x418a50, 3, 0x04, 0x00000000 }, +- { 0x418a60, 3, 0x04, 0x00000000 }, +- { 0x418a6c, 1, 0x04, 0x00010000 }, +- { 0x418a70, 3, 0x04, 0x00000000 }, +- { 0x418a80, 3, 0x04, 0x00000000 }, +- { 0x418a8c, 1, 0x04, 0x00010000 }, +- { 0x418a90, 3, 0x04, 0x00000000 }, +- { 0x418aa0, 3, 0x04, 0x00000000 }, +- { 0x418aac, 1, 0x04, 0x00010000 }, +- { 0x418ab0, 3, 0x04, 0x00000000 }, +- { 0x418ac0, 3, 0x04, 0x00000000 }, +- { 0x418acc, 1, 0x04, 0x00010000 }, +- { 0x418ad0, 3, 0x04, 0x00000000 }, +- { 0x418ae0, 3, 0x04, 0x00000000 }, +- { 0x418aec, 1, 0x04, 0x00010000 }, +- { 0x418af0, 3, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvc0_grctx_pack_zcull[] = { +- { nvc0_grctx_init_zcullr_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_pe_0[] = { +- { 0x419818, 1, 0x04, 0x00000000 }, +- { 0x41983c, 1, 0x04, 0x00038bc7 }, +- { 0x419848, 1, 0x04, 0x00000000 }, +- { 0x419864, 1, 0x04, 0x0000012a }, +- { 0x419888, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000001f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000023 }, +- { 0x419a0c, 1, 0x04, 0x00020000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_wwdx_0[] = { +- { 0x419b00, 1, 0x04, 0x0a418820 }, +- { 0x419b04, 1, 0x04, 0x062080e6 }, +- { 0x419b08, 1, 0x04, 0x020398a4 }, +- { 0x419b0c, 1, 0x04, 0x0e629062 }, +- { 0x419b10, 1, 0x04, 0x0a418820 }, +- { 0x419b14, 1, 0x04, 0x000000e6 }, +- { 0x419bd0, 1, 0x04, 0x00900103 }, +- { 0x419be0, 1, 0x04, 0x00000001 }, +- { 0x419be4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_mpc_0[] = { +- { 0x419c00, 1, 0x04, 0x00000002 }, +- { 0x419c04, 1, 0x04, 0x00000006 }, +- { 0x419c08, 1, 0x04, 0x00000002 }, +- { 0x419c20, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_l1c_0[] = { +- { 0x419cb0, 1, 0x04, 0x00060048 }, +- { 0x419ce8, 1, 0x04, 0x00000000 }, +- { 0x419cf4, 1, 0x04, 0x00000183 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_grctx_init_tpccs_0[] = { +- { 0x419d20, 1, 0x04, 0x02180000 }, +- { 0x419d24, 1, 0x04, 0x00001fff }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_grctx_init_sm_0[] = { +- { 0x419e04, 3, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00000002 }, +- { 0x419e44, 1, 0x04, 0x001beff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000000f }, +- { 0x419e50, 17, 0x04, 0x00000000 }, +- { 0x419e98, 1, 0x04, 0x00000000 }, +- { 0x419f50, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvc0_grctx_pack_tpc[] = { +- { nvc0_grctx_init_pe_0 }, +- { nvc0_grctx_init_tex_0 }, +- { nvc0_grctx_init_wwdx_0 }, +- { nvc0_grctx_init_mpc_0 }, +- { nvc0_grctx_init_l1c_0 }, +- { nvc0_grctx_init_tpccs_0 }, +- { nvc0_grctx_init_sm_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-int +-nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access) +-{ +- if (info->data) { +- info->buffer[info->buffer_nr] = round_up(info->addr, align); +- info->addr = info->buffer[info->buffer_nr] + size; +- info->data->size = size; +- info->data->align = align; +- info->data->access = access; +- info->data++; +- return info->buffer_nr++; +- } +- return -1; +-} +- +-void +-nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data, +- int shift, int buffer) +-{ +- if (info->data) { +- if (shift >= 0) { +- info->mmio->addr = addr; +- info->mmio->data = data; +- info->mmio->shift = shift; +- info->mmio->buffer = buffer; +- if (buffer >= 0) +- data |= info->buffer[buffer] >> shift; +- info->mmio++; +- } else +- return; +- } else { +- if (buffer >= 0) +- return; +- } +- +- nv_wr32(info->priv, addr, data); +-} +- +-void +-nvc0_grctx_generate_bundle(struct nvc0_grctx *info) +-{ +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); +- const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; +- const int s = 8; +- const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); +- mmio_refn(info, 0x408004, 0x00000000, s, b); +- mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); +- mmio_refn(info, 0x418808, 0x00000000, s, b); +- mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); +-} +- +-void +-nvc0_grctx_generate_pagepool(struct nvc0_grctx *info) +-{ +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); +- const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; +- const int s = 8; +- const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); +- mmio_refn(info, 0x40800c, 0x00000000, s, b); +- mmio_wr32(info, 0x408010, 0x80000000); +- mmio_refn(info, 0x419004, 0x00000000, s, b); +- mmio_wr32(info, 0x419008, 0x00000000); +-} +- +-void +-nvc0_grctx_generate_attrib(struct nvc0_grctx *info) +-{ +- struct nvc0_graph_priv *priv = info->priv; +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); +- const u32 attrib = impl->attrib_nr; +- const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); +- const u32 access = NV_MEM_ACCESS_RW; +- const int s = 12; +- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); +- int gpc, tpc; +- u32 bo = 0; +- +- mmio_refn(info, 0x418810, 0x80000000, s, b); +- mmio_refn(info, 0x419848, 0x10000000, s, b); +- mmio_wr32(info, 0x405830, (attrib << 16)); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { +- const u32 o = TPC_UNIT(gpc, tpc, 0x0520); +- mmio_skip(info, o, (attrib << 16) | ++bo); +- mmio_wr32(info, o, (attrib << 16) | --bo); +- bo += impl->attrib_nr_max; +- } +- } +-} +- +-void +-nvc0_grctx_generate_unkn(struct nvc0_graph_priv *priv) +-{ +-} +- +-void +-nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *priv) +-{ +- int gpc, tpc, id; +- +- for (tpc = 0, id = 0; tpc < 4; tpc++) { +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- if (tpc < priv->tpc_nr[gpc]) { +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x698), id); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x4e8), id); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x088), id); +- id++; +- } +- +- nv_wr32(priv, GPC_UNIT(gpc, 0x0c08), priv->tpc_nr[gpc]); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0c8c), priv->tpc_nr[gpc]); +- } +- } +-} +- +-void +-nvc0_grctx_generate_r406028(struct nvc0_graph_priv *priv) +-{ +- u32 tmp[GPC_MAX / 8] = {}, i = 0; +- for (i = 0; i < priv->gpc_nr; i++) +- tmp[i / 8] |= priv->tpc_nr[i] << ((i % 8) * 4); +- for (i = 0; i < 4; i++) { +- nv_wr32(priv, 0x406028 + (i * 4), tmp[i]); +- nv_wr32(priv, 0x405870 + (i * 4), tmp[i]); +- } +-} +- +-void +-nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *priv) +-{ +- u8 tpcnr[GPC_MAX], data[TPC_MAX]; +- int gpc, tpc, i; +- +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- memset(data, 0x1f, sizeof(data)); +- +- gpc = -1; +- for (tpc = 0; tpc < priv->tpc_total; tpc++) { +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpcnr[gpc]--; +- data[tpc] = gpc; +- } +- +- for (i = 0; i < 4; i++) +- nv_wr32(priv, 0x4060a8 + (i * 4), ((u32 *)data)[i]); +-} +- +-void +-nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) +-{ +- u32 data[6] = {}, data2[2] = {}; +- u8 tpcnr[GPC_MAX]; +- u8 shift, ntpcv; +- int gpc, tpc, i; +- +- /* calculate first set of magics */ +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- +- gpc = -1; +- for (tpc = 0; tpc < priv->tpc_total; tpc++) { +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpcnr[gpc]--; +- +- data[tpc / 6] |= gpc << ((tpc % 6) * 5); +- } +- +- for (; tpc < 32; tpc++) +- data[tpc / 6] |= 7 << ((tpc % 6) * 5); +- +- /* and the second... */ +- shift = 0; +- ntpcv = priv->tpc_total; +- while (!(ntpcv & (1 << 4))) { +- ntpcv <<= 1; +- shift++; +- } +- +- data2[0] = (ntpcv << 16); +- data2[0] |= (shift << 21); +- data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); +- for (i = 1; i < 7; i++) +- data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); +- +- /* GPC_BROADCAST */ +- nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | +- priv->magic_not_rop_nr); +- for (i = 0; i < 6; i++) +- nv_wr32(priv, 0x418b08 + (i * 4), data[i]); +- +- /* GPC_BROADCAST.TP_BROADCAST */ +- nv_wr32(priv, 0x419bd0, (priv->tpc_total << 8) | +- priv->magic_not_rop_nr | data2[0]); +- nv_wr32(priv, 0x419be4, data2[1]); +- for (i = 0; i < 6; i++) +- nv_wr32(priv, 0x419b00 + (i * 4), data[i]); +- +- /* UNK78xx */ +- nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | +- priv->magic_not_rop_nr); +- for (i = 0; i < 6; i++) +- nv_wr32(priv, 0x40780c + (i * 4), data[i]); +-} +- +-void +-nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) +-{ +- u64 tpc_mask = 0, tpc_set = 0; +- u8 tpcnr[GPC_MAX]; +- int gpc, tpc; +- int i, a, b; +- +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) +- tpc_mask |= ((1ULL << priv->tpc_nr[gpc]) - 1) << (gpc * 8); +- +- for (i = 0, gpc = -1, b = -1; i < 32; i++) { +- a = (i * (priv->tpc_total - 1)) / 32; +- if (a != b) { +- b = a; +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; +- +- tpc_set |= 1ULL << ((gpc * 8) + tpc); +- } +- +- nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set)); +- nv_wr32(priv, 0x406c00 + (i * 0x20), lower_32_bits(tpc_set ^ tpc_mask)); +- if (priv->gpc_nr > 4) { +- nv_wr32(priv, 0x406804 + (i * 0x20), upper_32_bits(tpc_set)); +- nv_wr32(priv, 0x406c04 + (i * 0x20), upper_32_bits(tpc_set ^ tpc_mask)); +- } +- } +-} +- +-void +-nvc0_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +-{ +- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; +- +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); +- +- nvc0_graph_mmio(priv, oclass->hub); +- nvc0_graph_mmio(priv, oclass->gpc); +- nvc0_graph_mmio(priv, oclass->zcull); +- nvc0_graph_mmio(priv, oclass->tpc); +- nvc0_graph_mmio(priv, oclass->ppc); +- +- nv_wr32(priv, 0x404154, 0x00000000); +- +- oclass->bundle(info); +- oclass->pagepool(info); +- oclass->attrib(info); +- oclass->unkn(priv); +- +- nvc0_grctx_generate_tpcid(priv); +- nvc0_grctx_generate_r406028(priv); +- nvc0_grctx_generate_r4060a8(priv); +- nvc0_grctx_generate_r418bb8(priv); +- nvc0_grctx_generate_r406800(priv); +- +- nvc0_graph_icmd(priv, oclass->icmd); +- nv_wr32(priv, 0x404154, 0x00000400); +- nvc0_graph_mthd(priv, oclass->mthd); +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +-} +- +-int +-nvc0_grctx_generate(struct nvc0_graph_priv *priv) +-{ +- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; +- struct nouveau_bar *bar = nouveau_bar(priv); +- struct nouveau_gpuobj *chan; +- struct nvc0_grctx info; +- int ret, i; +- +- /* allocate memory to for a "channel", which we'll use to generate +- * the default context values +- */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size, +- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- if (ret) { +- nv_error(priv, "failed to allocate channel memory, %d\n", ret); +- return ret; +- } +- +- /* PGD pointer */ +- nv_wo32(chan, 0x0200, lower_32_bits(chan->addr + 0x1000)); +- nv_wo32(chan, 0x0204, upper_32_bits(chan->addr + 0x1000)); +- nv_wo32(chan, 0x0208, 0xffffffff); +- nv_wo32(chan, 0x020c, 0x000000ff); +- +- /* PGT[0] pointer */ +- nv_wo32(chan, 0x1000, 0x00000000); +- nv_wo32(chan, 0x1004, 0x00000001 | (chan->addr + 0x2000) >> 8); +- +- /* identity-map the whole "channel" into its own vm */ +- for (i = 0; i < chan->size / 4096; i++) { +- u64 addr = ((chan->addr + (i * 4096)) >> 8) | 1; +- nv_wo32(chan, 0x2000 + (i * 8), lower_32_bits(addr)); +- nv_wo32(chan, 0x2004 + (i * 8), upper_32_bits(addr)); +- } +- +- /* context pointer (virt) */ +- nv_wo32(chan, 0x0210, 0x00080004); +- nv_wo32(chan, 0x0214, 0x00000000); +- +- bar->flush(bar); +- +- nv_wr32(priv, 0x100cb8, (chan->addr + 0x1000) >> 8); +- nv_wr32(priv, 0x100cbc, 0x80000001); +- nv_wait(priv, 0x100c80, 0x00008000, 0x00008000); +- +- /* setup default state for mmio list construction */ +- info.priv = priv; +- info.data = priv->mmio_data; +- info.mmio = priv->mmio_list; +- info.addr = 0x2000 + (i * 8); +- info.buffer_nr = 0; +- +- /* make channel current */ +- if (priv->firmware) { +- nv_wr32(priv, 0x409840, 0x00000030); +- nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); +- nv_wr32(priv, 0x409504, 0x00000003); +- if (!nv_wait(priv, 0x409800, 0x00000010, 0x00000010)) +- nv_error(priv, "load_ctx timeout\n"); +- +- nv_wo32(chan, 0x8001c, 1); +- nv_wo32(chan, 0x80020, 0); +- nv_wo32(chan, 0x80028, 0); +- nv_wo32(chan, 0x8002c, 0); +- bar->flush(bar); +- } else { +- nv_wr32(priv, 0x409840, 0x80000000); +- nv_wr32(priv, 0x409500, 0x80000000 | chan->addr >> 12); +- nv_wr32(priv, 0x409504, 0x00000001); +- if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) +- nv_error(priv, "HUB_SET_CHAN timeout\n"); +- } +- +- oclass->main(priv, &info); +- +- /* trigger a context unload by unsetting the "next channel valid" bit +- * and faking a context switch interrupt +- */ +- nv_mask(priv, 0x409b04, 0x80000000, 0x00000000); +- nv_wr32(priv, 0x409000, 0x00000100); +- if (!nv_wait(priv, 0x409b00, 0x80000000, 0x00000000)) { +- nv_error(priv, "grctx template channel unload timeout\n"); +- ret = -EBUSY; +- goto done; +- } +- +- priv->data = kmalloc(priv->size, GFP_KERNEL); +- if (priv->data) { +- for (i = 0; i < priv->size; i += 4) +- priv->data[i / 4] = nv_ro32(chan, 0x80000 + i); +- ret = 0; +- } else { +- ret = -ENOMEM; +- } +- +-done: +- nouveau_gpuobj_ref(NULL, &chan); +- return ret; +-} +- +-struct nouveau_oclass * +-nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nvc0_grctx_generate_main, +- .unkn = nvc0_grctx_generate_unkn, +- .hub = nvc0_grctx_pack_hub, +- .gpc = nvc0_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvc0_grctx_pack_tpc, +- .icmd = nvc0_grctx_pack_icmd, +- .mthd = nvc0_grctx_pack_mthd, +- .bundle = nvc0_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .pagepool = nvc0_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvc0_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h +deleted file mode 100644 +index c776cd71..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h ++++ /dev/null +@@ -1,202 +0,0 @@ +-#ifndef __NVKM_GRCTX_NVC0_H__ +-#define __NVKM_GRCTX_NVC0_H__ +- +-#include "nvc0.h" +- +-struct nvc0_grctx { +- struct nvc0_graph_priv *priv; +- struct nvc0_graph_data *data; +- struct nvc0_graph_mmio *mmio; +- int buffer_nr; +- u64 buffer[4]; +- u64 addr; +-}; +- +-int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access); +-void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int); +- +-#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d)) +-#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e)) +-#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1) +-#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1) +- +-struct nvc0_grctx_oclass { +- struct nouveau_oclass base; +- /* main context generation function */ +- void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *); +- /* context-specific modify-on-first-load list generation function */ +- void (*unkn)(struct nvc0_graph_priv *); +- /* mmio context data */ +- const struct nvc0_graph_pack *hub; +- const struct nvc0_graph_pack *gpc; +- const struct nvc0_graph_pack *zcull; +- const struct nvc0_graph_pack *tpc; +- const struct nvc0_graph_pack *ppc; +- /* indirect context data, generated with icmds/mthds */ +- const struct nvc0_graph_pack *icmd; +- const struct nvc0_graph_pack *mthd; +- /* bundle circular buffer */ +- void (*bundle)(struct nvc0_grctx *); +- u32 bundle_size; +- u32 bundle_min_gpm_fifo_depth; +- u32 bundle_token_limit; +- /* pagepool */ +- void (*pagepool)(struct nvc0_grctx *); +- u32 pagepool_size; +- /* attribute(/alpha) circular buffer */ +- void (*attrib)(struct nvc0_grctx *); +- u32 attrib_nr_max; +- u32 attrib_nr; +- u32 alpha_nr_max; +- u32 alpha_nr; +-}; +- +-static inline const struct nvc0_grctx_oclass * +-nvc0_grctx_impl(struct nvc0_graph_priv *priv) +-{ +- return (void *)nv_engine(priv)->cclass; +-} +- +-extern struct nouveau_oclass *nvc0_grctx_oclass; +-int nvc0_grctx_generate(struct nvc0_graph_priv *); +-void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); +-void nvc0_grctx_generate_bundle(struct nvc0_grctx *); +-void nvc0_grctx_generate_pagepool(struct nvc0_grctx *); +-void nvc0_grctx_generate_attrib(struct nvc0_grctx *); +-void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *); +-void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *); +-void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *); +-void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *); +-void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *); +-void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *); +- +-extern struct nouveau_oclass *nvc1_grctx_oclass; +-void nvc1_grctx_generate_attrib(struct nvc0_grctx *); +-void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *); +- +-extern struct nouveau_oclass *nvc4_grctx_oclass; +-extern struct nouveau_oclass *nvc8_grctx_oclass; +- +-extern struct nouveau_oclass *nvd7_grctx_oclass; +-void nvd7_grctx_generate_attrib(struct nvc0_grctx *); +- +-extern struct nouveau_oclass *nvd9_grctx_oclass; +- +-extern struct nouveau_oclass *nve4_grctx_oclass; +-extern struct nouveau_oclass *gk20a_grctx_oclass; +-void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *); +-void nve4_grctx_generate_bundle(struct nvc0_grctx *); +-void nve4_grctx_generate_pagepool(struct nvc0_grctx *); +-void nve4_grctx_generate_unkn(struct nvc0_graph_priv *); +-void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *); +- +-extern struct nouveau_oclass *nvf0_grctx_oclass; +-extern struct nouveau_oclass *gk110b_grctx_oclass; +-extern struct nouveau_oclass *nv108_grctx_oclass; +-extern struct nouveau_oclass *gm107_grctx_oclass; +- +-/* context init value lists */ +- +-extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[]; +- +-extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[]; +- +-extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_main_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[]; +- +-extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_prop_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_gpc_unk_1[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_zcull_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_crstr_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_gpm_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_gcc_0[]; +- +-extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[]; +- +-extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_pe_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_wwdx_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_mpc_0[]; +-extern const struct nvc0_graph_init nvc0_grctx_init_tpccs_0[]; +- +-extern const struct nvc0_graph_init nvc4_grctx_init_tex_0[]; +-extern const struct nvc0_graph_init nvc4_grctx_init_l1c_0[]; +-extern const struct nvc0_graph_init nvc4_grctx_init_sm_0[]; +- +-extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[]; +- +-extern const struct nvc0_graph_init nvc1_grctx_init_gpm_0[]; +- +-extern const struct nvc0_graph_init nvc1_grctx_init_pe_0[]; +-extern const struct nvc0_graph_init nvc1_grctx_init_wwdx_0[]; +-extern const struct nvc0_graph_init nvc1_grctx_init_tpccs_0[]; +- +-extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[]; +-extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[]; +- +-extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[]; +- +-extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[]; +- +-extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[]; +-extern const struct nvc0_graph_init nvd9_grctx_init_be_0[]; +- +-extern const struct nvc0_graph_init nvd9_grctx_init_prop_0[]; +-extern const struct nvc0_graph_init nvd9_grctx_init_gpc_unk_1[]; +-extern const struct nvc0_graph_init nvd9_grctx_init_crstr_0[]; +- +-extern const struct nvc0_graph_init nvd9_grctx_init_sm_0[]; +- +-extern const struct nvc0_graph_init nvd7_grctx_init_pe_0[]; +- +-extern const struct nvc0_graph_init nvd7_grctx_init_wwdx_0[]; +- +-extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[]; +-extern const struct nvc0_graph_init nve4_grctx_init_ds_0[]; +-extern const struct nvc0_graph_init nve4_grctx_init_scc_0[]; +- +-extern const struct nvc0_graph_init nve4_grctx_init_gpm_0[]; +- +-extern const struct nvc0_graph_init nve4_grctx_init_pes_0[]; +- +-extern const struct nvc0_graph_pack nve4_grctx_pack_hub[]; +-extern const struct nvc0_graph_pack nve4_grctx_pack_gpc[]; +-extern const struct nvc0_graph_pack nve4_grctx_pack_tpc[]; +-extern const struct nvc0_graph_pack nve4_grctx_pack_ppc[]; +-extern const struct nvc0_graph_pack nve4_grctx_pack_icmd[]; +-extern const struct nvc0_graph_init nve4_grctx_init_a097_0[]; +- +-extern const struct nvc0_graph_pack nvf0_grctx_pack_icmd[]; +- +-extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[]; +- +-extern const struct nvc0_graph_pack nvf0_grctx_pack_hub[]; +-extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[]; +-extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[]; +- +-extern const struct nvc0_graph_pack nvf0_grctx_pack_gpc[]; +-extern const struct nvc0_graph_init nvf0_grctx_init_gpc_unk_2[]; +- +-extern const struct nvc0_graph_init nvf0_grctx_init_tex_0[]; +-extern const struct nvc0_graph_init nvf0_grctx_init_mpc_0[]; +-extern const struct nvc0_graph_init nvf0_grctx_init_l1c_0[]; +- +-extern const struct nvc0_graph_pack nvf0_grctx_pack_ppc[]; +- +-extern const struct nvc0_graph_init nv108_grctx_init_rstr2d_0[]; +- +-extern const struct nvc0_graph_init nv108_grctx_init_prop_0[]; +-extern const struct nvc0_graph_init nv108_grctx_init_crstr_0[]; +- +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c +deleted file mode 100644 +index c6ba8fed..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c ++++ /dev/null +@@ -1,805 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvc1_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000b2, 40, 0x01, 0x00000000 }, +- { 0x000210, 8, 0x01, 0x00000040 }, +- { 0x000218, 8, 0x01, 0x0000c080 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00001fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x003fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x0005e0, 5, 0x01, 0x00000022 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x00000c48 }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00300008 }, +- { 0x000841, 1, 0x01, 0x04000080 }, +- { 0x000842, 1, 0x01, 0x00300008 }, +- { 0x000843, 1, 0x01, 0x04000080 }, +- { 0x000818, 8, 0x01, 0x00000000 }, +- { 0x000848, 16, 0x01, 0x00000000 }, +- { 0x000738, 1, 0x01, 0x00000000 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x000944, 1, 0x01, 0x00000022 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000014 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc1_grctx_pack_icmd[] = { +- { nvc1_grctx_init_icmd_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc1_grctx_init_9097_0[] = { +- { 0x000800, 8, 0x40, 0x00000000 }, +- { 0x000804, 8, 0x40, 0x00000000 }, +- { 0x000808, 8, 0x40, 0x00000400 }, +- { 0x00080c, 8, 0x40, 0x00000300 }, +- { 0x000810, 1, 0x04, 0x000000cf }, +- { 0x000850, 7, 0x40, 0x00000000 }, +- { 0x000814, 8, 0x40, 0x00000040 }, +- { 0x000818, 8, 0x40, 0x00000001 }, +- { 0x00081c, 8, 0x40, 0x00000000 }, +- { 0x000820, 8, 0x40, 0x00000000 }, +- { 0x002700, 8, 0x20, 0x00000000 }, +- { 0x002704, 8, 0x20, 0x00000000 }, +- { 0x002708, 8, 0x20, 0x00000000 }, +- { 0x00270c, 8, 0x20, 0x00000000 }, +- { 0x002710, 8, 0x20, 0x00014000 }, +- { 0x002714, 8, 0x20, 0x00000040 }, +- { 0x001c00, 16, 0x10, 0x00000000 }, +- { 0x001c04, 16, 0x10, 0x00000000 }, +- { 0x001c08, 16, 0x10, 0x00000000 }, +- { 0x001c0c, 16, 0x10, 0x00000000 }, +- { 0x001d00, 16, 0x10, 0x00000000 }, +- { 0x001d04, 16, 0x10, 0x00000000 }, +- { 0x001d08, 16, 0x10, 0x00000000 }, +- { 0x001d0c, 16, 0x10, 0x00000000 }, +- { 0x001f00, 16, 0x08, 0x00000000 }, +- { 0x001f04, 16, 0x08, 0x00000000 }, +- { 0x001f80, 16, 0x08, 0x00000000 }, +- { 0x001f84, 16, 0x08, 0x00000000 }, +- { 0x002200, 5, 0x10, 0x00000022 }, +- { 0x002000, 1, 0x04, 0x00000000 }, +- { 0x002040, 1, 0x04, 0x00000011 }, +- { 0x002080, 1, 0x04, 0x00000020 }, +- { 0x0020c0, 1, 0x04, 0x00000030 }, +- { 0x002100, 1, 0x04, 0x00000040 }, +- { 0x002140, 1, 0x04, 0x00000051 }, +- { 0x00200c, 6, 0x40, 0x00000001 }, +- { 0x002010, 1, 0x04, 0x00000000 }, +- { 0x002050, 1, 0x04, 0x00000000 }, +- { 0x002090, 1, 0x04, 0x00000001 }, +- { 0x0020d0, 1, 0x04, 0x00000002 }, +- { 0x002110, 1, 0x04, 0x00000003 }, +- { 0x002150, 1, 0x04, 0x00000004 }, +- { 0x000380, 4, 0x20, 0x00000000 }, +- { 0x000384, 4, 0x20, 0x00000000 }, +- { 0x000388, 4, 0x20, 0x00000000 }, +- { 0x00038c, 4, 0x20, 0x00000000 }, +- { 0x000700, 4, 0x10, 0x00000000 }, +- { 0x000704, 4, 0x10, 0x00000000 }, +- { 0x000708, 4, 0x10, 0x00000000 }, +- { 0x002800, 128, 0x04, 0x00000000 }, +- { 0x000a00, 16, 0x20, 0x00000000 }, +- { 0x000a04, 16, 0x20, 0x00000000 }, +- { 0x000a08, 16, 0x20, 0x00000000 }, +- { 0x000a0c, 16, 0x20, 0x00000000 }, +- { 0x000a10, 16, 0x20, 0x00000000 }, +- { 0x000a14, 16, 0x20, 0x00000000 }, +- { 0x000c00, 16, 0x10, 0x00000000 }, +- { 0x000c04, 16, 0x10, 0x00000000 }, +- { 0x000c08, 16, 0x10, 0x00000000 }, +- { 0x000c0c, 16, 0x10, 0x3f800000 }, +- { 0x000d00, 8, 0x08, 0xffff0000 }, +- { 0x000d04, 8, 0x08, 0xffff0000 }, +- { 0x000e00, 16, 0x10, 0x00000000 }, +- { 0x000e04, 16, 0x10, 0xffff0000 }, +- { 0x000e08, 16, 0x10, 0xffff0000 }, +- { 0x000d40, 4, 0x08, 0x00000000 }, +- { 0x000d44, 4, 0x08, 0x00000000 }, +- { 0x001e00, 8, 0x20, 0x00000001 }, +- { 0x001e04, 8, 0x20, 0x00000001 }, +- { 0x001e08, 8, 0x20, 0x00000002 }, +- { 0x001e0c, 8, 0x20, 0x00000001 }, +- { 0x001e10, 8, 0x20, 0x00000001 }, +- { 0x001e14, 8, 0x20, 0x00000002 }, +- { 0x001e18, 8, 0x20, 0x00000001 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x001514, 1, 0x04, 0x00000000 }, +- { 0x000d68, 1, 0x04, 0x0000ffff }, +- { 0x00121c, 1, 0x04, 0x0fac6881 }, +- { 0x000fac, 1, 0x04, 0x00000001 }, +- { 0x001538, 1, 0x04, 0x00000001 }, +- { 0x000fe0, 2, 0x04, 0x00000000 }, +- { 0x000fe8, 1, 0x04, 0x00000014 }, +- { 0x000fec, 1, 0x04, 0x00000040 }, +- { 0x000ff0, 1, 0x04, 0x00000000 }, +- { 0x00179c, 1, 0x04, 0x00000000 }, +- { 0x001228, 1, 0x04, 0x00000400 }, +- { 0x00122c, 1, 0x04, 0x00000300 }, +- { 0x001230, 1, 0x04, 0x00010001 }, +- { 0x0007f8, 1, 0x04, 0x00000000 }, +- { 0x0015b4, 1, 0x04, 0x00000001 }, +- { 0x0015cc, 1, 0x04, 0x00000000 }, +- { 0x001534, 1, 0x04, 0x00000000 }, +- { 0x000fb0, 1, 0x04, 0x00000000 }, +- { 0x0015d0, 1, 0x04, 0x00000000 }, +- { 0x00153c, 1, 0x04, 0x00000000 }, +- { 0x0016b4, 1, 0x04, 0x00000003 }, +- { 0x000fbc, 4, 0x04, 0x0000ffff }, +- { 0x000df8, 2, 0x04, 0x00000000 }, +- { 0x001948, 1, 0x04, 0x00000000 }, +- { 0x001970, 1, 0x04, 0x00000001 }, +- { 0x00161c, 1, 0x04, 0x000009f0 }, +- { 0x000dcc, 1, 0x04, 0x00000010 }, +- { 0x00163c, 1, 0x04, 0x00000000 }, +- { 0x0015e4, 1, 0x04, 0x00000000 }, +- { 0x001160, 32, 0x04, 0x25e00040 }, +- { 0x001880, 32, 0x04, 0x00000000 }, +- { 0x000f84, 2, 0x04, 0x00000000 }, +- { 0x0017c8, 2, 0x04, 0x00000000 }, +- { 0x0017d0, 1, 0x04, 0x000000ff }, +- { 0x0017d4, 1, 0x04, 0xffffffff }, +- { 0x0017d8, 1, 0x04, 0x00000002 }, +- { 0x0017dc, 1, 0x04, 0x00000000 }, +- { 0x0015f4, 2, 0x04, 0x00000000 }, +- { 0x001434, 2, 0x04, 0x00000000 }, +- { 0x000d74, 1, 0x04, 0x00000000 }, +- { 0x000dec, 1, 0x04, 0x00000001 }, +- { 0x0013a4, 1, 0x04, 0x00000000 }, +- { 0x001318, 1, 0x04, 0x00000001 }, +- { 0x001644, 1, 0x04, 0x00000000 }, +- { 0x000748, 1, 0x04, 0x00000000 }, +- { 0x000de8, 1, 0x04, 0x00000000 }, +- { 0x001648, 1, 0x04, 0x00000000 }, +- { 0x0012a4, 1, 0x04, 0x00000000 }, +- { 0x001120, 4, 0x04, 0x00000000 }, +- { 0x001118, 1, 0x04, 0x00000000 }, +- { 0x00164c, 1, 0x04, 0x00000000 }, +- { 0x001658, 1, 0x04, 0x00000000 }, +- { 0x001910, 1, 0x04, 0x00000290 }, +- { 0x001518, 1, 0x04, 0x00000000 }, +- { 0x00165c, 1, 0x04, 0x00000001 }, +- { 0x001520, 1, 0x04, 0x00000000 }, +- { 0x001604, 1, 0x04, 0x00000000 }, +- { 0x001570, 1, 0x04, 0x00000000 }, +- { 0x0013b0, 2, 0x04, 0x3f800000 }, +- { 0x00020c, 1, 0x04, 0x00000000 }, +- { 0x001670, 1, 0x04, 0x30201000 }, +- { 0x001674, 1, 0x04, 0x70605040 }, +- { 0x001678, 1, 0x04, 0xb8a89888 }, +- { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, +- { 0x00166c, 1, 0x04, 0x00000000 }, +- { 0x001680, 1, 0x04, 0x00ffff00 }, +- { 0x0012d0, 1, 0x04, 0x00000003 }, +- { 0x0012d4, 1, 0x04, 0x00000002 }, +- { 0x001684, 2, 0x04, 0x00000000 }, +- { 0x000dac, 2, 0x04, 0x00001b02 }, +- { 0x000db4, 1, 0x04, 0x00000000 }, +- { 0x00168c, 1, 0x04, 0x00000000 }, +- { 0x0015bc, 1, 0x04, 0x00000000 }, +- { 0x00156c, 1, 0x04, 0x00000000 }, +- { 0x00187c, 1, 0x04, 0x00000000 }, +- { 0x001110, 1, 0x04, 0x00000001 }, +- { 0x000dc0, 3, 0x04, 0x00000000 }, +- { 0x001234, 1, 0x04, 0x00000000 }, +- { 0x001690, 1, 0x04, 0x00000000 }, +- { 0x0012ac, 1, 0x04, 0x00000001 }, +- { 0x0002c4, 1, 0x04, 0x00000000 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x001000, 1, 0x04, 0x00000010 }, +- { 0x0010fc, 1, 0x04, 0x00000000 }, +- { 0x001290, 1, 0x04, 0x00000000 }, +- { 0x000218, 1, 0x04, 0x00000010 }, +- { 0x0012d8, 1, 0x04, 0x00000000 }, +- { 0x0012dc, 1, 0x04, 0x00000010 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x00155c, 2, 0x04, 0x00000000 }, +- { 0x001564, 1, 0x04, 0x00001fff }, +- { 0x001574, 2, 0x04, 0x00000000 }, +- { 0x00157c, 1, 0x04, 0x003fffff }, +- { 0x001354, 1, 0x04, 0x00000000 }, +- { 0x001664, 1, 0x04, 0x00000000 }, +- { 0x001610, 1, 0x04, 0x00000012 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x00162c, 1, 0x04, 0x00000003 }, +- { 0x000210, 1, 0x04, 0x00000000 }, +- { 0x000320, 1, 0x04, 0x00000000 }, +- { 0x000324, 6, 0x04, 0x3f800000 }, +- { 0x000750, 1, 0x04, 0x00000000 }, +- { 0x000760, 1, 0x04, 0x39291909 }, +- { 0x000764, 1, 0x04, 0x79695949 }, +- { 0x000768, 1, 0x04, 0xb9a99989 }, +- { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x000770, 1, 0x04, 0x30201000 }, +- { 0x000774, 1, 0x04, 0x70605040 }, +- { 0x000778, 1, 0x04, 0x00009080 }, +- { 0x000780, 1, 0x04, 0x39291909 }, +- { 0x000784, 1, 0x04, 0x79695949 }, +- { 0x000788, 1, 0x04, 0xb9a99989 }, +- { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x0007d0, 1, 0x04, 0x30201000 }, +- { 0x0007d4, 1, 0x04, 0x70605040 }, +- { 0x0007d8, 1, 0x04, 0x00009080 }, +- { 0x00037c, 1, 0x04, 0x00000001 }, +- { 0x000740, 2, 0x04, 0x00000000 }, +- { 0x002600, 1, 0x04, 0x00000000 }, +- { 0x001918, 1, 0x04, 0x00000000 }, +- { 0x00191c, 1, 0x04, 0x00000900 }, +- { 0x001920, 1, 0x04, 0x00000405 }, +- { 0x001308, 1, 0x04, 0x00000001 }, +- { 0x001924, 1, 0x04, 0x00000000 }, +- { 0x0013ac, 1, 0x04, 0x00000000 }, +- { 0x00192c, 1, 0x04, 0x00000001 }, +- { 0x00193c, 1, 0x04, 0x00002c1c }, +- { 0x000d7c, 1, 0x04, 0x00000000 }, +- { 0x000f8c, 1, 0x04, 0x00000000 }, +- { 0x0002c0, 1, 0x04, 0x00000001 }, +- { 0x001510, 1, 0x04, 0x00000000 }, +- { 0x001940, 1, 0x04, 0x00000000 }, +- { 0x000ff4, 2, 0x04, 0x00000000 }, +- { 0x00194c, 2, 0x04, 0x00000000 }, +- { 0x001968, 1, 0x04, 0x00000000 }, +- { 0x001590, 1, 0x04, 0x0000003f }, +- { 0x0007e8, 4, 0x04, 0x00000000 }, +- { 0x00196c, 1, 0x04, 0x00000011 }, +- { 0x00197c, 1, 0x04, 0x00000000 }, +- { 0x000fcc, 2, 0x04, 0x00000000 }, +- { 0x0002d8, 1, 0x04, 0x00000040 }, +- { 0x001980, 1, 0x04, 0x00000080 }, +- { 0x001504, 1, 0x04, 0x00000080 }, +- { 0x001984, 1, 0x04, 0x00000000 }, +- { 0x000300, 1, 0x04, 0x00000001 }, +- { 0x0013a8, 1, 0x04, 0x00000000 }, +- { 0x0012ec, 1, 0x04, 0x00000000 }, +- { 0x001310, 1, 0x04, 0x00000000 }, +- { 0x001314, 1, 0x04, 0x00000001 }, +- { 0x001380, 1, 0x04, 0x00000000 }, +- { 0x001384, 4, 0x04, 0x00000001 }, +- { 0x001394, 1, 0x04, 0x00000000 }, +- { 0x00139c, 1, 0x04, 0x00000000 }, +- { 0x001398, 1, 0x04, 0x00000000 }, +- { 0x001594, 1, 0x04, 0x00000000 }, +- { 0x001598, 4, 0x04, 0x00000001 }, +- { 0x000f54, 3, 0x04, 0x00000000 }, +- { 0x0019bc, 1, 0x04, 0x00000000 }, +- { 0x000f9c, 2, 0x04, 0x00000000 }, +- { 0x0012cc, 1, 0x04, 0x00000000 }, +- { 0x0012e8, 1, 0x04, 0x00000000 }, +- { 0x00130c, 1, 0x04, 0x00000001 }, +- { 0x001360, 8, 0x04, 0x00000000 }, +- { 0x00133c, 2, 0x04, 0x00000001 }, +- { 0x001344, 1, 0x04, 0x00000002 }, +- { 0x001348, 2, 0x04, 0x00000001 }, +- { 0x001350, 1, 0x04, 0x00000002 }, +- { 0x001358, 1, 0x04, 0x00000001 }, +- { 0x0012e4, 1, 0x04, 0x00000000 }, +- { 0x00131c, 4, 0x04, 0x00000000 }, +- { 0x0019c0, 1, 0x04, 0x00000000 }, +- { 0x001140, 1, 0x04, 0x00000000 }, +- { 0x0019c4, 1, 0x04, 0x00000000 }, +- { 0x0019c8, 1, 0x04, 0x00001500 }, +- { 0x00135c, 1, 0x04, 0x00000000 }, +- { 0x000f90, 1, 0x04, 0x00000000 }, +- { 0x0019e0, 8, 0x04, 0x00000001 }, +- { 0x0019cc, 1, 0x04, 0x00000001 }, +- { 0x0015b8, 1, 0x04, 0x00000000 }, +- { 0x001a00, 1, 0x04, 0x00001111 }, +- { 0x001a04, 7, 0x04, 0x00000000 }, +- { 0x000d6c, 2, 0x04, 0xffff0000 }, +- { 0x0010f8, 1, 0x04, 0x00001010 }, +- { 0x000d80, 5, 0x04, 0x00000000 }, +- { 0x000da0, 1, 0x04, 0x00000000 }, +- { 0x001508, 1, 0x04, 0x80000000 }, +- { 0x00150c, 1, 0x04, 0x40000000 }, +- { 0x001668, 1, 0x04, 0x00000000 }, +- { 0x000318, 2, 0x04, 0x00000008 }, +- { 0x000d9c, 1, 0x04, 0x00000001 }, +- { 0x0007dc, 1, 0x04, 0x00000000 }, +- { 0x00074c, 1, 0x04, 0x00000055 }, +- { 0x001420, 1, 0x04, 0x00000003 }, +- { 0x0017bc, 2, 0x04, 0x00000000 }, +- { 0x0017c4, 1, 0x04, 0x00000001 }, +- { 0x001008, 1, 0x04, 0x00000008 }, +- { 0x00100c, 1, 0x04, 0x00000040 }, +- { 0x001010, 1, 0x04, 0x0000012c }, +- { 0x000d60, 1, 0x04, 0x00000040 }, +- { 0x00075c, 1, 0x04, 0x00000003 }, +- { 0x001018, 1, 0x04, 0x00000020 }, +- { 0x00101c, 1, 0x04, 0x00000001 }, +- { 0x001020, 1, 0x04, 0x00000020 }, +- { 0x001024, 1, 0x04, 0x00000001 }, +- { 0x001444, 3, 0x04, 0x00000000 }, +- { 0x000360, 1, 0x04, 0x20164010 }, +- { 0x000364, 1, 0x04, 0x00000020 }, +- { 0x000368, 1, 0x04, 0x00000000 }, +- { 0x000de4, 1, 0x04, 0x00000000 }, +- { 0x000204, 1, 0x04, 0x00000006 }, +- { 0x000208, 1, 0x04, 0x00000000 }, +- { 0x0002cc, 1, 0x04, 0x003fffff }, +- { 0x0002d0, 1, 0x04, 0x00000c48 }, +- { 0x001220, 1, 0x04, 0x00000005 }, +- { 0x000fdc, 1, 0x04, 0x00000000 }, +- { 0x000f98, 1, 0x04, 0x00300008 }, +- { 0x001284, 1, 0x04, 0x04000080 }, +- { 0x001450, 1, 0x04, 0x00300008 }, +- { 0x001454, 1, 0x04, 0x04000080 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_grctx_init_9197_0[] = { +- { 0x003400, 128, 0x04, 0x00000000 }, +- { 0x0002e4, 1, 0x04, 0x0000b001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc1_grctx_pack_mthd[] = { +- { nvc1_grctx_init_9097_0, 0x9097 }, +- { nvc1_grctx_init_9197_0, 0x9197 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- { nvc0_grctx_init_9039_0, 0x9039 }, +- { nvc0_grctx_init_90c0_0, 0x90c0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x0f8000bf }, +- { 0x405830, 1, 0x04, 0x02180218 }, +- { 0x405834, 2, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x000103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b4, 2, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x80140078 }, +- { 0x4064c4, 1, 0x04, 0x0086ffff }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x02802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x1003e005 }, +- { 0x408900, 1, 0x04, 0x3080b801 }, +- { 0x408904, 1, 0x04, 0x62000001 }, +- { 0x408908, 1, 0x04, 0x00c80929 }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc1_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nvc0_grctx_init_fe_0 }, +- { nvc0_grctx_init_pri_0 }, +- { nvc0_grctx_init_memfmt_0 }, +- { nvc1_grctx_init_ds_0 }, +- { nvc1_grctx_init_pd_0 }, +- { nvc0_grctx_init_rstr2d_0 }, +- { nvc0_grctx_init_scc_0 }, +- { nvc1_grctx_init_be_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x0006860a }, +- { 0x418808, 3, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00008442 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x00100018 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc1_grctx_init_gpm_0[] = { +- { 0x418c08, 1, 0x04, 0x00000001 }, +- { 0x418c10, 8, 0x04, 0x00000000 }, +- { 0x418c6c, 1, 0x04, 0x00000001 }, +- { 0x418c80, 1, 0x04, 0x20200004 }, +- { 0x418c8c, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc1_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvc0_grctx_init_prop_0 }, +- { nvc0_grctx_init_gpc_unk_1 }, +- { nvc1_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvc0_grctx_init_crstr_0 }, +- { nvc1_grctx_init_gpm_0 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc1_grctx_init_pe_0[] = { +- { 0x419818, 1, 0x04, 0x00000000 }, +- { 0x41983c, 1, 0x04, 0x00038bc7 }, +- { 0x419848, 1, 0x04, 0x00000000 }, +- { 0x419864, 1, 0x04, 0x00000129 }, +- { 0x419888, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc1_grctx_init_wwdx_0[] = { +- { 0x419b00, 1, 0x04, 0x0a418820 }, +- { 0x419b04, 1, 0x04, 0x062080e6 }, +- { 0x419b08, 1, 0x04, 0x020398a4 }, +- { 0x419b0c, 1, 0x04, 0x0e629062 }, +- { 0x419b10, 1, 0x04, 0x0a418820 }, +- { 0x419b14, 1, 0x04, 0x000000e6 }, +- { 0x419bd0, 1, 0x04, 0x00900103 }, +- { 0x419be0, 1, 0x04, 0x00400001 }, +- { 0x419be4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc1_grctx_init_tpccs_0[] = { +- { 0x419d20, 1, 0x04, 0x12180000 }, +- { 0x419d24, 1, 0x04, 0x00001fff }, +- { 0x419d44, 1, 0x04, 0x02180218 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc1_grctx_pack_tpc[] = { +- { nvc1_grctx_init_pe_0 }, +- { nvc4_grctx_init_tex_0 }, +- { nvc1_grctx_init_wwdx_0 }, +- { nvc0_grctx_init_mpc_0 }, +- { nvc4_grctx_init_l1c_0 }, +- { nvc1_grctx_init_tpccs_0 }, +- { nvc4_grctx_init_sm_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-void +-nvc1_grctx_generate_attrib(struct nvc0_grctx *info) +-{ +- struct nvc0_graph_priv *priv = info->priv; +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); +- const u32 alpha = impl->alpha_nr; +- const u32 beta = impl->attrib_nr; +- const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); +- const u32 access = NV_MEM_ACCESS_RW; +- const int s = 12; +- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); +- const int timeslice_mode = 1; +- const int max_batches = 0xffff; +- u32 bo = 0; +- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; +- int gpc, tpc; +- +- mmio_refn(info, 0x418810, 0x80000000, s, b); +- mmio_refn(info, 0x419848, 0x10000000, s, b); +- mmio_wr32(info, 0x405830, (beta << 16) | alpha); +- mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { +- const u32 a = alpha; +- const u32 b = beta; +- const u32 t = timeslice_mode; +- const u32 o = TPC_UNIT(gpc, tpc, 0x500); +- mmio_skip(info, o + 0x20, (t << 28) | (b << 16) | ++bo); +- mmio_wr32(info, o + 0x20, (t << 28) | (b << 16) | --bo); +- bo += impl->attrib_nr_max; +- mmio_wr32(info, o + 0x44, (a << 16) | ao); +- ao += impl->alpha_nr_max; +- } +- } +-} +- +-void +-nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv) +-{ +- nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); +- nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); +- nv_mask(priv, 0x419814, 0x00000004, 0x00000004); +- nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); +- nv_mask(priv, 0x405800, 0x08000000, 0x08000000); +- nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +-} +- +-struct nouveau_oclass * +-nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xc1), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nvc0_grctx_generate_main, +- .unkn = nvc1_grctx_generate_unkn, +- .hub = nvc1_grctx_pack_hub, +- .gpc = nvc1_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvc1_grctx_pack_tpc, +- .icmd = nvc1_grctx_pack_icmd, +- .mthd = nvc1_grctx_pack_mthd, +- .bundle = nvc0_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .pagepool = nvc0_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvc1_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x324, +- .alpha_nr = 0x218, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c +deleted file mode 100644 +index 41705c60..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nvc4_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000001f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000023 }, +- { 0x419a0c, 1, 0x04, 0x00020000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- { 0x419a1c, 1, 0x04, 0x00000000 }, +- { 0x419a20, 1, 0x04, 0x00000800 }, +- { 0x419ac4, 1, 0x04, 0x0007f440 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc4_grctx_init_l1c_0[] = { +- { 0x419cb0, 1, 0x04, 0x00020048 }, +- { 0x419ce8, 1, 0x04, 0x00000000 }, +- { 0x419cf4, 1, 0x04, 0x00000183 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc4_grctx_init_sm_0[] = { +- { 0x419e04, 3, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00000002 }, +- { 0x419e44, 1, 0x04, 0x001beff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000000f }, +- { 0x419e50, 17, 0x04, 0x00000000 }, +- { 0x419e98, 1, 0x04, 0x00000000 }, +- { 0x419ee0, 1, 0x04, 0x00011110 }, +- { 0x419f30, 11, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc4_grctx_pack_tpc[] = { +- { nvc0_grctx_init_pe_0 }, +- { nvc4_grctx_init_tex_0 }, +- { nvc0_grctx_init_wwdx_0 }, +- { nvc0_grctx_init_mpc_0 }, +- { nvc4_grctx_init_l1c_0 }, +- { nvc0_grctx_init_tpccs_0 }, +- { nvc4_grctx_init_sm_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xc3), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nvc0_grctx_generate_main, +- .unkn = nvc0_grctx_generate_unkn, +- .hub = nvc0_grctx_pack_hub, +- .gpc = nvc0_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvc4_grctx_pack_tpc, +- .icmd = nvc0_grctx_pack_icmd, +- .mthd = nvc0_grctx_pack_mthd, +- .bundle = nvc0_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .pagepool = nvc0_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvc0_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c +deleted file mode 100644 +index 8f804cd8..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c ++++ /dev/null +@@ -1,360 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvc8_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000b2, 40, 0x01, 0x00000000 }, +- { 0x000210, 8, 0x01, 0x00000040 }, +- { 0x000218, 8, 0x01, 0x0000c080 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00001fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x003fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x0005e0, 5, 0x01, 0x00000022 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x00097d, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x00000c48 }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00300008 }, +- { 0x000841, 1, 0x01, 0x04000080 }, +- { 0x000842, 1, 0x01, 0x00300008 }, +- { 0x000843, 1, 0x01, 0x04000080 }, +- { 0x000818, 8, 0x01, 0x00000000 }, +- { 0x000848, 16, 0x01, 0x00000000 }, +- { 0x000738, 1, 0x01, 0x00000000 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x000944, 1, 0x01, 0x00000022 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000014 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc8_grctx_pack_icmd[] = { +- { nvc8_grctx_init_icmd_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc8_grctx_init_9197_0[] = { +- { 0x0002e4, 1, 0x04, 0x0000b001 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc8_grctx_init_9297_0[] = { +- { 0x003400, 128, 0x04, 0x00000000 }, +- { 0x00036c, 2, 0x04, 0x00000000 }, +- { 0x0007a4, 2, 0x04, 0x00000000 }, +- { 0x000374, 1, 0x04, 0x00000000 }, +- { 0x000378, 1, 0x04, 0x00000020 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc8_grctx_pack_mthd[] = { +- { nvc1_grctx_init_9097_0, 0x9097 }, +- { nvc8_grctx_init_9197_0, 0x9197 }, +- { nvc8_grctx_init_9297_0, 0x9297 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- { nvc0_grctx_init_9039_0, 0x9039 }, +- { nvc0_grctx_init_90c0_0, 0x90c0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc8_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x0006860a }, +- { 0x418808, 3, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00008442 }, +- { 0x418830, 1, 0x04, 0x00000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc8_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvc0_grctx_init_prop_0 }, +- { nvc0_grctx_init_gpc_unk_1 }, +- { nvc8_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvc0_grctx_init_crstr_0 }, +- { nvc0_grctx_init_gpm_0 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xc8), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nvc0_grctx_generate_main, +- .unkn = nvc0_grctx_generate_unkn, +- .hub = nvc0_grctx_pack_hub, +- .gpc = nvc8_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvc0_grctx_pack_tpc, +- .icmd = nvc8_grctx_pack_icmd, +- .mthd = nvc8_grctx_pack_mthd, +- .bundle = nvc0_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .pagepool = nvc0_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvc0_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c +deleted file mode 100644 +index fcf534fd..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c ++++ /dev/null +@@ -1,282 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x0f8000bf }, +- { 0x405830, 1, 0x04, 0x02180324 }, +- { 0x405834, 1, 0x04, 0x08000000 }, +- { 0x405838, 1, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x000103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b4, 3, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x801a0078 }, +- { 0x4064c4, 1, 0x04, 0x00c9ffff }, +- { 0x4064d0, 8, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd7_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nvd9_grctx_init_fe_0 }, +- { nvc0_grctx_init_pri_0 }, +- { nvc0_grctx_init_memfmt_0 }, +- { nvd7_grctx_init_ds_0 }, +- { nvd7_grctx_init_pd_0 }, +- { nvc0_grctx_init_rstr2d_0 }, +- { nvc0_grctx_init_scc_0 }, +- { nvd9_grctx_init_be_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x7006860a }, +- { 0x418808, 3, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00008442 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100018 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd7_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvd9_grctx_init_prop_0 }, +- { nvd9_grctx_init_gpc_unk_1 }, +- { nvd7_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvd9_grctx_init_crstr_0 }, +- { nvc1_grctx_init_gpm_0 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd7_grctx_init_pe_0[] = { +- { 0x419848, 1, 0x04, 0x00000000 }, +- { 0x419864, 1, 0x04, 0x00000129 }, +- { 0x419888, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000001f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000023 }, +- { 0x419a0c, 1, 0x04, 0x00020000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- { 0x419a1c, 1, 0x04, 0x00008000 }, +- { 0x419a20, 1, 0x04, 0x00000800 }, +- { 0x419ac4, 1, 0x04, 0x0017f440 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_mpc_0[] = { +- { 0x419c00, 1, 0x04, 0x0000000a }, +- { 0x419c04, 1, 0x04, 0x00000006 }, +- { 0x419c08, 1, 0x04, 0x00000002 }, +- { 0x419c20, 1, 0x04, 0x00000000 }, +- { 0x419c24, 1, 0x04, 0x00084210 }, +- { 0x419c28, 1, 0x04, 0x3efbefbe }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd7_grctx_pack_tpc[] = { +- { nvd7_grctx_init_pe_0 }, +- { nvd7_grctx_init_tex_0 }, +- { nvd7_grctx_init_mpc_0 }, +- { nvc4_grctx_init_l1c_0 }, +- { nvd9_grctx_init_sm_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_pes_0[] = { +- { 0x41be24, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd7_grctx_init_cbm_0[] = { +- { 0x41bec0, 1, 0x04, 0x12180000 }, +- { 0x41bec4, 1, 0x04, 0x00003fff }, +- { 0x41bee4, 1, 0x04, 0x03240218 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd7_grctx_init_wwdx_0[] = { +- { 0x41bf00, 1, 0x04, 0x0a418820 }, +- { 0x41bf04, 1, 0x04, 0x062080e6 }, +- { 0x41bf08, 1, 0x04, 0x020398a4 }, +- { 0x41bf0c, 1, 0x04, 0x0e629062 }, +- { 0x41bf10, 1, 0x04, 0x0a418820 }, +- { 0x41bf14, 1, 0x04, 0x000000e6 }, +- { 0x41bfd0, 1, 0x04, 0x00900103 }, +- { 0x41bfe0, 1, 0x04, 0x00400001 }, +- { 0x41bfe4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd7_grctx_pack_ppc[] = { +- { nvd7_grctx_init_pes_0 }, +- { nvd7_grctx_init_cbm_0 }, +- { nvd7_grctx_init_wwdx_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-void +-nvd7_grctx_generate_attrib(struct nvc0_grctx *info) +-{ +- struct nvc0_graph_priv *priv = info->priv; +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv); +- const u32 alpha = impl->alpha_nr; +- const u32 beta = impl->attrib_nr; +- const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max); +- const u32 access = NV_MEM_ACCESS_RW; +- const int s = 12; +- const int b = mmio_vram(info, size * priv->tpc_total, (1 << s), access); +- const int timeslice_mode = 1; +- const int max_batches = 0xffff; +- u32 bo = 0; +- u32 ao = bo + impl->attrib_nr_max * priv->tpc_total; +- int gpc, ppc; +- +- mmio_refn(info, 0x418810, 0x80000000, s, b); +- mmio_refn(info, 0x419848, 0x10000000, s, b); +- mmio_wr32(info, 0x405830, (beta << 16) | alpha); +- mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) | max_batches); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- for (ppc = 0; ppc < priv->ppc_nr[gpc]; ppc++) { +- const u32 a = alpha * priv->ppc_tpc_nr[gpc][ppc]; +- const u32 b = beta * priv->ppc_tpc_nr[gpc][ppc]; +- const u32 t = timeslice_mode; +- const u32 o = PPC_UNIT(gpc, ppc, 0); +- mmio_skip(info, o + 0xc0, (t << 28) | (b << 16) | ++bo); +- mmio_wr32(info, o + 0xc0, (t << 28) | (b << 16) | --bo); +- bo += impl->attrib_nr_max * priv->ppc_tpc_nr[gpc][ppc]; +- mmio_wr32(info, o + 0xe4, (a << 16) | ao); +- ao += impl->alpha_nr_max * priv->ppc_tpc_nr[gpc][ppc]; +- } +- } +-} +- +-void +-nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +-{ +- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; +- int i; +- +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); +- +- nvc0_graph_mmio(priv, oclass->hub); +- nvc0_graph_mmio(priv, oclass->gpc); +- nvc0_graph_mmio(priv, oclass->zcull); +- nvc0_graph_mmio(priv, oclass->tpc); +- nvc0_graph_mmio(priv, oclass->ppc); +- +- nv_wr32(priv, 0x404154, 0x00000000); +- +- oclass->bundle(info); +- oclass->pagepool(info); +- oclass->attrib(info); +- oclass->unkn(priv); +- +- nvc0_grctx_generate_tpcid(priv); +- nvc0_grctx_generate_r406028(priv); +- nvc0_grctx_generate_r4060a8(priv); +- nve4_grctx_generate_r418bb8(priv); +- nvc0_grctx_generate_r406800(priv); +- +- for (i = 0; i < 8; i++) +- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); +- +- nvc0_graph_icmd(priv, oclass->icmd); +- nv_wr32(priv, 0x404154, 0x00000400); +- nvc0_graph_mthd(priv, oclass->mthd); +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +-} +- +-struct nouveau_oclass * +-nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xd7), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nvd7_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = nvd7_grctx_pack_hub, +- .gpc = nvd7_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvd7_grctx_pack_tpc, +- .ppc = nvd7_grctx_pack_ppc, +- .icmd = nvd9_grctx_pack_icmd, +- .mthd = nvd9_grctx_pack_mthd, +- .bundle = nvc0_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .pagepool = nvc0_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvd7_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x7ff, +- .alpha_nr = 0x324, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c +deleted file mode 100644 +index b9a301b6..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c ++++ /dev/null +@@ -1,530 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000b2, 40, 0x01, 0x00000000 }, +- { 0x000210, 8, 0x01, 0x00000040 }, +- { 0x000400, 24, 0x01, 0x00000040 }, +- { 0x000218, 8, 0x01, 0x0000c080 }, +- { 0x000440, 24, 0x01, 0x0000c080 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00001fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x003fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x0005e0, 5, 0x01, 0x00000022 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x00097d, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x00000c48 }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00300008 }, +- { 0x000841, 1, 0x01, 0x04000080 }, +- { 0x000842, 1, 0x01, 0x00300008 }, +- { 0x000843, 1, 0x01, 0x04000080 }, +- { 0x000818, 8, 0x01, 0x00000000 }, +- { 0x000848, 16, 0x01, 0x00000000 }, +- { 0x000738, 1, 0x01, 0x00000000 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x000944, 1, 0x01, 0x00000022 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000014 }, +- { 0x000351, 1, 0x01, 0x00000100 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095d, 1, 0x01, 0x00000001 }, +- { 0x00082b, 1, 0x01, 0x00000004 }, +- { 0x000942, 1, 0x01, 0x00010001 }, +- { 0x000943, 1, 0x01, 0x00000001 }, +- { 0x0007c5, 1, 0x01, 0x00010001 }, +- { 0x000834, 1, 0x01, 0x00000001 }, +- { 0x0007c7, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x00080c, 1, 0x01, 0x00000002 }, +- { 0x00080d, 2, 0x01, 0x00000100 }, +- { 0x00080f, 1, 0x01, 0x00000001 }, +- { 0x000823, 1, 0x01, 0x00000002 }, +- { 0x000824, 2, 0x01, 0x00000100 }, +- { 0x000826, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvd9_grctx_pack_icmd[] = { +- { nvd9_grctx_init_icmd_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_90c0_0[] = { +- { 0x002700, 8, 0x20, 0x00000000 }, +- { 0x002704, 8, 0x20, 0x00000000 }, +- { 0x002708, 8, 0x20, 0x00000000 }, +- { 0x00270c, 8, 0x20, 0x00000000 }, +- { 0x002710, 8, 0x20, 0x00014000 }, +- { 0x002714, 8, 0x20, 0x00000040 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x000758, 1, 0x04, 0x00000100 }, +- { 0x0002c4, 1, 0x04, 0x00000000 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x000204, 3, 0x04, 0x00000000 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- { 0x00024c, 1, 0x04, 0x00000000 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x001664, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvd9_grctx_pack_mthd[] = { +- { nvc1_grctx_init_9097_0, 0x9097 }, +- { nvc8_grctx_init_9197_0, 0x9197 }, +- { nvc8_grctx_init_9297_0, 0x9297 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- { nvc0_grctx_init_9039_0, 0x9039 }, +- { nvd9_grctx_init_90c0_0, 0x90c0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_grctx_init_fe_0[] = { +- { 0x404004, 10, 0x04, 0x00000000 }, +- { 0x404044, 1, 0x04, 0x00000000 }, +- { 0x404094, 13, 0x04, 0x00000000 }, +- { 0x4040c8, 1, 0x04, 0xf0000087 }, +- { 0x4040d0, 6, 0x04, 0x00000000 }, +- { 0x4040e8, 1, 0x04, 0x00001000 }, +- { 0x4040f8, 1, 0x04, 0x00000000 }, +- { 0x404130, 2, 0x04, 0x00000000 }, +- { 0x404138, 1, 0x04, 0x20000040 }, +- { 0x404150, 1, 0x04, 0x0000002e }, +- { 0x404154, 1, 0x04, 0x00000400 }, +- { 0x404158, 1, 0x04, 0x00000200 }, +- { 0x404164, 1, 0x04, 0x00000055 }, +- { 0x404168, 1, 0x04, 0x00000000 }, +- { 0x404178, 2, 0x04, 0x00000000 }, +- { 0x404200, 8, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x0f8000bf }, +- { 0x405830, 1, 0x04, 0x02180218 }, +- { 0x405834, 1, 0x04, 0x08000000 }, +- { 0x405838, 1, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x000103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b4, 3, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x80140078 }, +- { 0x4064c4, 1, 0x04, 0x0086ffff }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x02802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x1043e005 }, +- { 0x408900, 1, 0x04, 0x3080b801 }, +- { 0x408904, 1, 0x04, 0x62000001 }, +- { 0x408908, 1, 0x04, 0x00c8102f }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd9_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nvd9_grctx_init_fe_0 }, +- { nvc0_grctx_init_pri_0 }, +- { nvc0_grctx_init_memfmt_0 }, +- { nvd9_grctx_init_ds_0 }, +- { nvd9_grctx_init_pd_0 }, +- { nvc0_grctx_init_rstr2d_0 }, +- { nvc0_grctx_init_scc_0 }, +- { nvd9_grctx_init_be_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_grctx_init_prop_0[] = { +- { 0x418400, 1, 0x04, 0x38004e00 }, +- { 0x418404, 1, 0x04, 0x71e0ffff }, +- { 0x41840c, 1, 0x04, 0x00001008 }, +- { 0x418410, 1, 0x04, 0x0fff0fff }, +- { 0x418414, 1, 0x04, 0x02200fff }, +- { 0x418450, 6, 0x04, 0x00000000 }, +- { 0x418468, 1, 0x04, 0x00000001 }, +- { 0x41846c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_grctx_init_gpc_unk_1[] = { +- { 0x418600, 1, 0x04, 0x0000001f }, +- { 0x418684, 1, 0x04, 0x0000000f }, +- { 0x418700, 1, 0x04, 0x00000002 }, +- { 0x418704, 1, 0x04, 0x00000080 }, +- { 0x418708, 3, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x7006860a }, +- { 0x418808, 3, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00008442 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100008 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_grctx_init_crstr_0[] = { +- { 0x418b00, 1, 0x04, 0x00000006 }, +- { 0x418b08, 1, 0x04, 0x0a418820 }, +- { 0x418b0c, 1, 0x04, 0x062080e6 }, +- { 0x418b10, 1, 0x04, 0x020398a4 }, +- { 0x418b14, 1, 0x04, 0x0e629062 }, +- { 0x418b18, 1, 0x04, 0x0a418820 }, +- { 0x418b1c, 1, 0x04, 0x000000e6 }, +- { 0x418bb8, 1, 0x04, 0x00000103 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd9_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvd9_grctx_init_prop_0 }, +- { nvd9_grctx_init_gpc_unk_1 }, +- { nvd9_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvd9_grctx_init_crstr_0 }, +- { nvc1_grctx_init_gpm_0 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000001f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000023 }, +- { 0x419a0c, 1, 0x04, 0x00020000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- { 0x419a1c, 1, 0x04, 0x00000000 }, +- { 0x419a20, 1, 0x04, 0x00000800 }, +- { 0x419ac4, 1, 0x04, 0x0017f440 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_grctx_init_mpc_0[] = { +- { 0x419c00, 1, 0x04, 0x0000000a }, +- { 0x419c04, 1, 0x04, 0x00000006 }, +- { 0x419c08, 1, 0x04, 0x00000002 }, +- { 0x419c20, 1, 0x04, 0x00000000 }, +- { 0x419c24, 1, 0x04, 0x00084210 }, +- { 0x419c28, 1, 0x04, 0x3cf3cf3c }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_grctx_init_sm_0[] = { +- { 0x419e04, 3, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00000002 }, +- { 0x419e44, 1, 0x04, 0x001beff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000000f }, +- { 0x419e50, 17, 0x04, 0x00000000 }, +- { 0x419e98, 1, 0x04, 0x00000000 }, +- { 0x419ee0, 1, 0x04, 0x00010110 }, +- { 0x419f30, 11, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd9_grctx_pack_tpc[] = { +- { nvc1_grctx_init_pe_0 }, +- { nvd9_grctx_init_tex_0 }, +- { nvc1_grctx_init_wwdx_0 }, +- { nvd9_grctx_init_mpc_0 }, +- { nvc4_grctx_init_l1c_0 }, +- { nvc1_grctx_init_tpccs_0 }, +- { nvd9_grctx_init_sm_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xd9), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nvc0_grctx_generate_main, +- .unkn = nvc1_grctx_generate_unkn, +- .hub = nvd9_grctx_pack_hub, +- .gpc = nvd9_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvd9_grctx_pack_tpc, +- .icmd = nvd9_grctx_pack_icmd, +- .mthd = nvd9_grctx_pack_mthd, +- .bundle = nvc0_grctx_generate_bundle, +- .bundle_size = 0x1800, +- .pagepool = nvc0_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvc1_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x324, +- .alpha_nr = 0x218, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c +deleted file mode 100644 +index ccac2ee1..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnve4.c ++++ /dev/null +@@ -1,1020 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nve4_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000383, 1, 0x01, 0x00000011 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x00097d, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x003fffff }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00400008 }, +- { 0x000841, 1, 0x01, 0x08000080 }, +- { 0x000842, 1, 0x01, 0x00400008 }, +- { 0x000843, 1, 0x01, 0x08000080 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x00c500, 1, 0x01, 0x00000003 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000008 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x00c500, 1, 0x01, 0x00000003 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nve4_grctx_pack_icmd[] = { +- { nve4_grctx_init_icmd_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_grctx_init_a097_0[] = { +- { 0x000800, 8, 0x40, 0x00000000 }, +- { 0x000804, 8, 0x40, 0x00000000 }, +- { 0x000808, 8, 0x40, 0x00000400 }, +- { 0x00080c, 8, 0x40, 0x00000300 }, +- { 0x000810, 1, 0x04, 0x000000cf }, +- { 0x000850, 7, 0x40, 0x00000000 }, +- { 0x000814, 8, 0x40, 0x00000040 }, +- { 0x000818, 8, 0x40, 0x00000001 }, +- { 0x00081c, 8, 0x40, 0x00000000 }, +- { 0x000820, 8, 0x40, 0x00000000 }, +- { 0x001c00, 16, 0x10, 0x00000000 }, +- { 0x001c04, 16, 0x10, 0x00000000 }, +- { 0x001c08, 16, 0x10, 0x00000000 }, +- { 0x001c0c, 16, 0x10, 0x00000000 }, +- { 0x001d00, 16, 0x10, 0x00000000 }, +- { 0x001d04, 16, 0x10, 0x00000000 }, +- { 0x001d08, 16, 0x10, 0x00000000 }, +- { 0x001d0c, 16, 0x10, 0x00000000 }, +- { 0x001f00, 16, 0x08, 0x00000000 }, +- { 0x001f04, 16, 0x08, 0x00000000 }, +- { 0x001f80, 16, 0x08, 0x00000000 }, +- { 0x001f84, 16, 0x08, 0x00000000 }, +- { 0x002000, 1, 0x04, 0x00000000 }, +- { 0x002040, 1, 0x04, 0x00000011 }, +- { 0x002080, 1, 0x04, 0x00000020 }, +- { 0x0020c0, 1, 0x04, 0x00000030 }, +- { 0x002100, 1, 0x04, 0x00000040 }, +- { 0x002140, 1, 0x04, 0x00000051 }, +- { 0x00200c, 6, 0x40, 0x00000001 }, +- { 0x002010, 1, 0x04, 0x00000000 }, +- { 0x002050, 1, 0x04, 0x00000000 }, +- { 0x002090, 1, 0x04, 0x00000001 }, +- { 0x0020d0, 1, 0x04, 0x00000002 }, +- { 0x002110, 1, 0x04, 0x00000003 }, +- { 0x002150, 1, 0x04, 0x00000004 }, +- { 0x000380, 4, 0x20, 0x00000000 }, +- { 0x000384, 4, 0x20, 0x00000000 }, +- { 0x000388, 4, 0x20, 0x00000000 }, +- { 0x00038c, 4, 0x20, 0x00000000 }, +- { 0x000700, 4, 0x10, 0x00000000 }, +- { 0x000704, 4, 0x10, 0x00000000 }, +- { 0x000708, 4, 0x10, 0x00000000 }, +- { 0x002800, 128, 0x04, 0x00000000 }, +- { 0x000a00, 16, 0x20, 0x00000000 }, +- { 0x000a04, 16, 0x20, 0x00000000 }, +- { 0x000a08, 16, 0x20, 0x00000000 }, +- { 0x000a0c, 16, 0x20, 0x00000000 }, +- { 0x000a10, 16, 0x20, 0x00000000 }, +- { 0x000a14, 16, 0x20, 0x00000000 }, +- { 0x000c00, 16, 0x10, 0x00000000 }, +- { 0x000c04, 16, 0x10, 0x00000000 }, +- { 0x000c08, 16, 0x10, 0x00000000 }, +- { 0x000c0c, 16, 0x10, 0x3f800000 }, +- { 0x000d00, 8, 0x08, 0xffff0000 }, +- { 0x000d04, 8, 0x08, 0xffff0000 }, +- { 0x000e00, 16, 0x10, 0x00000000 }, +- { 0x000e04, 16, 0x10, 0xffff0000 }, +- { 0x000e08, 16, 0x10, 0xffff0000 }, +- { 0x000d40, 4, 0x08, 0x00000000 }, +- { 0x000d44, 4, 0x08, 0x00000000 }, +- { 0x001e00, 8, 0x20, 0x00000001 }, +- { 0x001e04, 8, 0x20, 0x00000001 }, +- { 0x001e08, 8, 0x20, 0x00000002 }, +- { 0x001e0c, 8, 0x20, 0x00000001 }, +- { 0x001e10, 8, 0x20, 0x00000001 }, +- { 0x001e14, 8, 0x20, 0x00000002 }, +- { 0x001e18, 8, 0x20, 0x00000001 }, +- { 0x003400, 128, 0x04, 0x00000000 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x001514, 1, 0x04, 0x00000000 }, +- { 0x000d68, 1, 0x04, 0x0000ffff }, +- { 0x00121c, 1, 0x04, 0x0fac6881 }, +- { 0x000fac, 1, 0x04, 0x00000001 }, +- { 0x001538, 1, 0x04, 0x00000001 }, +- { 0x000fe0, 2, 0x04, 0x00000000 }, +- { 0x000fe8, 1, 0x04, 0x00000014 }, +- { 0x000fec, 1, 0x04, 0x00000040 }, +- { 0x000ff0, 1, 0x04, 0x00000000 }, +- { 0x00179c, 1, 0x04, 0x00000000 }, +- { 0x001228, 1, 0x04, 0x00000400 }, +- { 0x00122c, 1, 0x04, 0x00000300 }, +- { 0x001230, 1, 0x04, 0x00010001 }, +- { 0x0007f8, 1, 0x04, 0x00000000 }, +- { 0x0015b4, 1, 0x04, 0x00000001 }, +- { 0x0015cc, 1, 0x04, 0x00000000 }, +- { 0x001534, 1, 0x04, 0x00000000 }, +- { 0x000fb0, 1, 0x04, 0x00000000 }, +- { 0x0015d0, 1, 0x04, 0x00000000 }, +- { 0x00153c, 1, 0x04, 0x00000000 }, +- { 0x0016b4, 1, 0x04, 0x00000003 }, +- { 0x000fbc, 4, 0x04, 0x0000ffff }, +- { 0x000df8, 2, 0x04, 0x00000000 }, +- { 0x001948, 1, 0x04, 0x00000000 }, +- { 0x001970, 1, 0x04, 0x00000001 }, +- { 0x00161c, 1, 0x04, 0x000009f0 }, +- { 0x000dcc, 1, 0x04, 0x00000010 }, +- { 0x00163c, 1, 0x04, 0x00000000 }, +- { 0x0015e4, 1, 0x04, 0x00000000 }, +- { 0x001160, 32, 0x04, 0x25e00040 }, +- { 0x001880, 32, 0x04, 0x00000000 }, +- { 0x000f84, 2, 0x04, 0x00000000 }, +- { 0x0017c8, 2, 0x04, 0x00000000 }, +- { 0x0017d0, 1, 0x04, 0x000000ff }, +- { 0x0017d4, 1, 0x04, 0xffffffff }, +- { 0x0017d8, 1, 0x04, 0x00000002 }, +- { 0x0017dc, 1, 0x04, 0x00000000 }, +- { 0x0015f4, 2, 0x04, 0x00000000 }, +- { 0x001434, 2, 0x04, 0x00000000 }, +- { 0x000d74, 1, 0x04, 0x00000000 }, +- { 0x000dec, 1, 0x04, 0x00000001 }, +- { 0x0013a4, 1, 0x04, 0x00000000 }, +- { 0x001318, 1, 0x04, 0x00000001 }, +- { 0x001644, 1, 0x04, 0x00000000 }, +- { 0x000748, 1, 0x04, 0x00000000 }, +- { 0x000de8, 1, 0x04, 0x00000000 }, +- { 0x001648, 1, 0x04, 0x00000000 }, +- { 0x0012a4, 1, 0x04, 0x00000000 }, +- { 0x001120, 4, 0x04, 0x00000000 }, +- { 0x001118, 1, 0x04, 0x00000000 }, +- { 0x00164c, 1, 0x04, 0x00000000 }, +- { 0x001658, 1, 0x04, 0x00000000 }, +- { 0x001910, 1, 0x04, 0x00000290 }, +- { 0x001518, 1, 0x04, 0x00000000 }, +- { 0x00165c, 1, 0x04, 0x00000001 }, +- { 0x001520, 1, 0x04, 0x00000000 }, +- { 0x001604, 1, 0x04, 0x00000000 }, +- { 0x001570, 1, 0x04, 0x00000000 }, +- { 0x0013b0, 2, 0x04, 0x3f800000 }, +- { 0x00020c, 1, 0x04, 0x00000000 }, +- { 0x001670, 1, 0x04, 0x30201000 }, +- { 0x001674, 1, 0x04, 0x70605040 }, +- { 0x001678, 1, 0x04, 0xb8a89888 }, +- { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, +- { 0x00166c, 1, 0x04, 0x00000000 }, +- { 0x001680, 1, 0x04, 0x00ffff00 }, +- { 0x0012d0, 1, 0x04, 0x00000003 }, +- { 0x0012d4, 1, 0x04, 0x00000002 }, +- { 0x001684, 2, 0x04, 0x00000000 }, +- { 0x000dac, 2, 0x04, 0x00001b02 }, +- { 0x000db4, 1, 0x04, 0x00000000 }, +- { 0x00168c, 1, 0x04, 0x00000000 }, +- { 0x0015bc, 1, 0x04, 0x00000000 }, +- { 0x00156c, 1, 0x04, 0x00000000 }, +- { 0x00187c, 1, 0x04, 0x00000000 }, +- { 0x001110, 1, 0x04, 0x00000001 }, +- { 0x000dc0, 3, 0x04, 0x00000000 }, +- { 0x001234, 1, 0x04, 0x00000000 }, +- { 0x001690, 1, 0x04, 0x00000000 }, +- { 0x0012ac, 1, 0x04, 0x00000001 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x001000, 1, 0x04, 0x00000010 }, +- { 0x0010fc, 1, 0x04, 0x00000000 }, +- { 0x001290, 1, 0x04, 0x00000000 }, +- { 0x000218, 1, 0x04, 0x00000010 }, +- { 0x0012d8, 1, 0x04, 0x00000000 }, +- { 0x0012dc, 1, 0x04, 0x00000010 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x00155c, 2, 0x04, 0x00000000 }, +- { 0x001564, 1, 0x04, 0x00000fff }, +- { 0x001574, 2, 0x04, 0x00000000 }, +- { 0x00157c, 1, 0x04, 0x000fffff }, +- { 0x001354, 1, 0x04, 0x00000000 }, +- { 0x001610, 1, 0x04, 0x00000012 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x00260c, 1, 0x04, 0x00000000 }, +- { 0x0007ac, 1, 0x04, 0x00000000 }, +- { 0x00162c, 1, 0x04, 0x00000003 }, +- { 0x000210, 1, 0x04, 0x00000000 }, +- { 0x000320, 1, 0x04, 0x00000000 }, +- { 0x000324, 6, 0x04, 0x3f800000 }, +- { 0x000750, 1, 0x04, 0x00000000 }, +- { 0x000760, 1, 0x04, 0x39291909 }, +- { 0x000764, 1, 0x04, 0x79695949 }, +- { 0x000768, 1, 0x04, 0xb9a99989 }, +- { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x000770, 1, 0x04, 0x30201000 }, +- { 0x000774, 1, 0x04, 0x70605040 }, +- { 0x000778, 1, 0x04, 0x00009080 }, +- { 0x000780, 1, 0x04, 0x39291909 }, +- { 0x000784, 1, 0x04, 0x79695949 }, +- { 0x000788, 1, 0x04, 0xb9a99989 }, +- { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x0007d0, 1, 0x04, 0x30201000 }, +- { 0x0007d4, 1, 0x04, 0x70605040 }, +- { 0x0007d8, 1, 0x04, 0x00009080 }, +- { 0x00037c, 1, 0x04, 0x00000001 }, +- { 0x000740, 2, 0x04, 0x00000000 }, +- { 0x002600, 1, 0x04, 0x00000000 }, +- { 0x001918, 1, 0x04, 0x00000000 }, +- { 0x00191c, 1, 0x04, 0x00000900 }, +- { 0x001920, 1, 0x04, 0x00000405 }, +- { 0x001308, 1, 0x04, 0x00000001 }, +- { 0x001924, 1, 0x04, 0x00000000 }, +- { 0x0013ac, 1, 0x04, 0x00000000 }, +- { 0x00192c, 1, 0x04, 0x00000001 }, +- { 0x00193c, 1, 0x04, 0x00002c1c }, +- { 0x000d7c, 1, 0x04, 0x00000000 }, +- { 0x000f8c, 1, 0x04, 0x00000000 }, +- { 0x0002c0, 1, 0x04, 0x00000001 }, +- { 0x001510, 1, 0x04, 0x00000000 }, +- { 0x001940, 1, 0x04, 0x00000000 }, +- { 0x000ff4, 2, 0x04, 0x00000000 }, +- { 0x00194c, 2, 0x04, 0x00000000 }, +- { 0x001968, 1, 0x04, 0x00000000 }, +- { 0x001590, 1, 0x04, 0x0000003f }, +- { 0x0007e8, 4, 0x04, 0x00000000 }, +- { 0x00196c, 1, 0x04, 0x00000011 }, +- { 0x0002e4, 1, 0x04, 0x0000b001 }, +- { 0x00036c, 2, 0x04, 0x00000000 }, +- { 0x00197c, 1, 0x04, 0x00000000 }, +- { 0x000fcc, 2, 0x04, 0x00000000 }, +- { 0x0002d8, 1, 0x04, 0x00000040 }, +- { 0x001980, 1, 0x04, 0x00000080 }, +- { 0x001504, 1, 0x04, 0x00000080 }, +- { 0x001984, 1, 0x04, 0x00000000 }, +- { 0x000300, 1, 0x04, 0x00000001 }, +- { 0x0013a8, 1, 0x04, 0x00000000 }, +- { 0x0012ec, 1, 0x04, 0x00000000 }, +- { 0x001310, 1, 0x04, 0x00000000 }, +- { 0x001314, 1, 0x04, 0x00000001 }, +- { 0x001380, 1, 0x04, 0x00000000 }, +- { 0x001384, 4, 0x04, 0x00000001 }, +- { 0x001394, 1, 0x04, 0x00000000 }, +- { 0x00139c, 1, 0x04, 0x00000000 }, +- { 0x001398, 1, 0x04, 0x00000000 }, +- { 0x001594, 1, 0x04, 0x00000000 }, +- { 0x001598, 4, 0x04, 0x00000001 }, +- { 0x000f54, 3, 0x04, 0x00000000 }, +- { 0x0019bc, 1, 0x04, 0x00000000 }, +- { 0x000f9c, 2, 0x04, 0x00000000 }, +- { 0x0012cc, 1, 0x04, 0x00000000 }, +- { 0x0012e8, 1, 0x04, 0x00000000 }, +- { 0x00130c, 1, 0x04, 0x00000001 }, +- { 0x001360, 8, 0x04, 0x00000000 }, +- { 0x00133c, 2, 0x04, 0x00000001 }, +- { 0x001344, 1, 0x04, 0x00000002 }, +- { 0x001348, 2, 0x04, 0x00000001 }, +- { 0x001350, 1, 0x04, 0x00000002 }, +- { 0x001358, 1, 0x04, 0x00000001 }, +- { 0x0012e4, 1, 0x04, 0x00000000 }, +- { 0x00131c, 4, 0x04, 0x00000000 }, +- { 0x0019c0, 1, 0x04, 0x00000000 }, +- { 0x001140, 1, 0x04, 0x00000000 }, +- { 0x0019c4, 1, 0x04, 0x00000000 }, +- { 0x0019c8, 1, 0x04, 0x00001500 }, +- { 0x00135c, 1, 0x04, 0x00000000 }, +- { 0x000f90, 1, 0x04, 0x00000000 }, +- { 0x0019e0, 8, 0x04, 0x00000001 }, +- { 0x0019cc, 1, 0x04, 0x00000001 }, +- { 0x0015b8, 1, 0x04, 0x00000000 }, +- { 0x001a00, 1, 0x04, 0x00001111 }, +- { 0x001a04, 7, 0x04, 0x00000000 }, +- { 0x000d6c, 2, 0x04, 0xffff0000 }, +- { 0x0010f8, 1, 0x04, 0x00001010 }, +- { 0x000d80, 5, 0x04, 0x00000000 }, +- { 0x000da0, 1, 0x04, 0x00000000 }, +- { 0x0007a4, 2, 0x04, 0x00000000 }, +- { 0x001508, 1, 0x04, 0x80000000 }, +- { 0x00150c, 1, 0x04, 0x40000000 }, +- { 0x001668, 1, 0x04, 0x00000000 }, +- { 0x000318, 2, 0x04, 0x00000008 }, +- { 0x000d9c, 1, 0x04, 0x00000001 }, +- { 0x000374, 1, 0x04, 0x00000000 }, +- { 0x000378, 1, 0x04, 0x00000020 }, +- { 0x0007dc, 1, 0x04, 0x00000000 }, +- { 0x00074c, 1, 0x04, 0x00000055 }, +- { 0x001420, 1, 0x04, 0x00000003 }, +- { 0x0017bc, 2, 0x04, 0x00000000 }, +- { 0x0017c4, 1, 0x04, 0x00000001 }, +- { 0x001008, 1, 0x04, 0x00000008 }, +- { 0x00100c, 1, 0x04, 0x00000040 }, +- { 0x001010, 1, 0x04, 0x0000012c }, +- { 0x000d60, 1, 0x04, 0x00000040 }, +- { 0x00075c, 1, 0x04, 0x00000003 }, +- { 0x001018, 1, 0x04, 0x00000020 }, +- { 0x00101c, 1, 0x04, 0x00000001 }, +- { 0x001020, 1, 0x04, 0x00000020 }, +- { 0x001024, 1, 0x04, 0x00000001 }, +- { 0x001444, 3, 0x04, 0x00000000 }, +- { 0x000360, 1, 0x04, 0x20164010 }, +- { 0x000364, 1, 0x04, 0x00000020 }, +- { 0x000368, 1, 0x04, 0x00000000 }, +- { 0x000de4, 1, 0x04, 0x00000000 }, +- { 0x000204, 1, 0x04, 0x00000006 }, +- { 0x000208, 1, 0x04, 0x00000000 }, +- { 0x0002cc, 2, 0x04, 0x003fffff }, +- { 0x001220, 1, 0x04, 0x00000005 }, +- { 0x000fdc, 1, 0x04, 0x00000000 }, +- { 0x000f98, 1, 0x04, 0x00400008 }, +- { 0x001284, 1, 0x04, 0x08000080 }, +- { 0x001450, 1, 0x04, 0x00400008 }, +- { 0x001454, 1, 0x04, 0x08000080 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nve4_grctx_pack_mthd[] = { +- { nve4_grctx_init_a097_0, 0xa097 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_fe_0[] = { +- { 0x404010, 5, 0x04, 0x00000000 }, +- { 0x404024, 1, 0x04, 0x0000e000 }, +- { 0x404028, 1, 0x04, 0x00000000 }, +- { 0x4040a8, 8, 0x04, 0x00000000 }, +- { 0x4040c8, 1, 0x04, 0xf800008f }, +- { 0x4040d0, 6, 0x04, 0x00000000 }, +- { 0x4040e8, 1, 0x04, 0x00001000 }, +- { 0x4040f8, 1, 0x04, 0x00000000 }, +- { 0x404130, 2, 0x04, 0x00000000 }, +- { 0x404138, 1, 0x04, 0x20000040 }, +- { 0x404150, 1, 0x04, 0x0000002e }, +- { 0x404154, 1, 0x04, 0x00000400 }, +- { 0x404158, 1, 0x04, 0x00000200 }, +- { 0x404164, 1, 0x04, 0x00000055 }, +- { 0x4041a0, 4, 0x04, 0x00000000 }, +- { 0x404200, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_grctx_init_memfmt_0[] = { +- { 0x404604, 1, 0x04, 0x00000014 }, +- { 0x404608, 1, 0x04, 0x00000000 }, +- { 0x40460c, 1, 0x04, 0x00003fff }, +- { 0x404610, 1, 0x04, 0x00000100 }, +- { 0x404618, 4, 0x04, 0x00000000 }, +- { 0x40462c, 2, 0x04, 0x00000000 }, +- { 0x404640, 1, 0x04, 0x00000000 }, +- { 0x404654, 1, 0x04, 0x00000000 }, +- { 0x404660, 1, 0x04, 0x00000000 }, +- { 0x404678, 1, 0x04, 0x00000000 }, +- { 0x40467c, 1, 0x04, 0x00000002 }, +- { 0x404680, 8, 0x04, 0x00000000 }, +- { 0x4046a0, 1, 0x04, 0x007f0080 }, +- { 0x4046a4, 8, 0x04, 0x00000000 }, +- { 0x4046c8, 3, 0x04, 0x00000000 }, +- { 0x404700, 3, 0x04, 0x00000000 }, +- { 0x404718, 7, 0x04, 0x00000000 }, +- { 0x404734, 1, 0x04, 0x00000100 }, +- { 0x404738, 2, 0x04, 0x00000000 }, +- { 0x404744, 2, 0x04, 0x00000000 }, +- { 0x404754, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_grctx_init_ds_0[] = { +- { 0x405800, 1, 0x04, 0x0f8000bf }, +- { 0x405830, 1, 0x04, 0x02180648 }, +- { 0x405834, 1, 0x04, 0x08000000 }, +- { 0x405838, 1, 0x04, 0x00000000 }, +- { 0x405854, 1, 0x04, 0x00000000 }, +- { 0x405870, 4, 0x04, 0x00000001 }, +- { 0x405a00, 2, 0x04, 0x00000000 }, +- { 0x405a18, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_cwd_0[] = { +- { 0x405b00, 1, 0x04, 0x00000000 }, +- { 0x405b10, 1, 0x04, 0x00001000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x004103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b4, 2, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x801a00f0 }, +- { 0x4064c4, 1, 0x04, 0x0192ffff }, +- { 0x4064c8, 1, 0x04, 0x01800600 }, +- { 0x4064cc, 9, 0x04, 0x00000000 }, +- { 0x4064fc, 1, 0x04, 0x0000022a }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_sked_0[] = { +- { 0x407040, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_grctx_init_scc_0[] = { +- { 0x408000, 2, 0x04, 0x00000000 }, +- { 0x408008, 1, 0x04, 0x00000030 }, +- { 0x40800c, 2, 0x04, 0x00000000 }, +- { 0x408014, 1, 0x04, 0x00000069 }, +- { 0x408018, 1, 0x04, 0xe100e100 }, +- { 0x408064, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x02802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x1043e005 }, +- { 0x408840, 1, 0x04, 0x0000000b }, +- { 0x408900, 1, 0x04, 0x3080b801 }, +- { 0x408904, 1, 0x04, 0x62000001 }, +- { 0x408908, 1, 0x04, 0x00c8102f }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nve4_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nve4_grctx_init_fe_0 }, +- { nvc0_grctx_init_pri_0 }, +- { nve4_grctx_init_memfmt_0 }, +- { nve4_grctx_init_ds_0 }, +- { nve4_grctx_init_cwd_0 }, +- { nve4_grctx_init_pd_0 }, +- { nve4_grctx_init_sked_0 }, +- { nvc0_grctx_init_rstr2d_0 }, +- { nve4_grctx_init_scc_0 }, +- { nve4_grctx_init_be_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x7006860a }, +- { 0x418808, 3, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00000044 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100018 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_grctx_init_gpm_0[] = { +- { 0x418c08, 1, 0x04, 0x00000001 }, +- { 0x418c10, 8, 0x04, 0x00000000 }, +- { 0x418c40, 1, 0x04, 0xffffffff }, +- { 0x418c6c, 1, 0x04, 0x00000001 }, +- { 0x418c80, 1, 0x04, 0x20200004 }, +- { 0x418c8c, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nve4_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvd9_grctx_init_prop_0 }, +- { nvd9_grctx_init_gpc_unk_1 }, +- { nve4_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvd9_grctx_init_crstr_0 }, +- { nve4_grctx_init_gpm_0 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000000f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000021 }, +- { 0x419a0c, 1, 0x04, 0x00020000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- { 0x419a1c, 1, 0x04, 0x0000c000 }, +- { 0x419a20, 1, 0x04, 0x00000800 }, +- { 0x419a30, 1, 0x04, 0x00000001 }, +- { 0x419ac4, 1, 0x04, 0x0037f440 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_mpc_0[] = { +- { 0x419c00, 1, 0x04, 0x0000000a }, +- { 0x419c04, 1, 0x04, 0x80000006 }, +- { 0x419c08, 1, 0x04, 0x00000002 }, +- { 0x419c20, 1, 0x04, 0x00000000 }, +- { 0x419c24, 1, 0x04, 0x00084210 }, +- { 0x419c28, 1, 0x04, 0x3efbefbe }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_l1c_0[] = { +- { 0x419ce8, 1, 0x04, 0x00000000 }, +- { 0x419cf4, 1, 0x04, 0x00003203 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_sm_0[] = { +- { 0x419e04, 3, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00000402 }, +- { 0x419e44, 1, 0x04, 0x0013eff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000007f }, +- { 0x419e50, 19, 0x04, 0x00000000 }, +- { 0x419eac, 1, 0x04, 0x00001f8f }, +- { 0x419eb0, 1, 0x04, 0x00000d3f }, +- { 0x419ec8, 1, 0x04, 0x0001304f }, +- { 0x419f30, 8, 0x04, 0x00000000 }, +- { 0x419f58, 1, 0x04, 0x00000000 }, +- { 0x419f70, 1, 0x04, 0x00000000 }, +- { 0x419f78, 1, 0x04, 0x0000000b }, +- { 0x419f7c, 1, 0x04, 0x0000027c }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nve4_grctx_pack_tpc[] = { +- { nvd7_grctx_init_pe_0 }, +- { nve4_grctx_init_tex_0 }, +- { nve4_grctx_init_mpc_0 }, +- { nve4_grctx_init_l1c_0 }, +- { nve4_grctx_init_sm_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_grctx_init_pes_0[] = { +- { 0x41be24, 1, 0x04, 0x00000006 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_grctx_init_cbm_0[] = { +- { 0x41bec0, 1, 0x04, 0x12180000 }, +- { 0x41bec4, 1, 0x04, 0x00037f7f }, +- { 0x41bee4, 1, 0x04, 0x06480430 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nve4_grctx_pack_ppc[] = { +- { nve4_grctx_init_pes_0 }, +- { nve4_grctx_init_cbm_0 }, +- { nvd7_grctx_init_wwdx_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-void +-nve4_grctx_generate_bundle(struct nvc0_grctx *info) +-{ +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); +- const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth, +- impl->bundle_size / 0x20); +- const u32 token_limit = impl->bundle_token_limit; +- const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; +- const int s = 8; +- const int b = mmio_vram(info, impl->bundle_size, (1 << s), access); +- mmio_refn(info, 0x408004, 0x00000000, s, b); +- mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b); +- mmio_refn(info, 0x418808, 0x00000000, s, b); +- mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b); +- mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit); +-} +- +-void +-nve4_grctx_generate_pagepool(struct nvc0_grctx *info) +-{ +- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv); +- const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS; +- const int s = 8; +- const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access); +- mmio_refn(info, 0x40800c, 0x00000000, s, b); +- mmio_wr32(info, 0x408010, 0x80000000); +- mmio_refn(info, 0x419004, 0x00000000, s, b); +- mmio_wr32(info, 0x419008, 0x00000000); +- mmio_wr32(info, 0x4064cc, 0x80000000); +-} +- +-void +-nve4_grctx_generate_unkn(struct nvc0_graph_priv *priv) +-{ +- nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001); +- nv_mask(priv, 0x41980c, 0x00000010, 0x00000010); +- nv_mask(priv, 0x41be08, 0x00000004, 0x00000004); +- nv_mask(priv, 0x4064c0, 0x80000000, 0x80000000); +- nv_mask(priv, 0x405800, 0x08000000, 0x08000000); +- nv_mask(priv, 0x419c00, 0x00000008, 0x00000008); +-} +- +-void +-nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *priv) +-{ +- u32 data[6] = {}, data2[2] = {}; +- u8 tpcnr[GPC_MAX]; +- u8 shift, ntpcv; +- int gpc, tpc, i; +- +- /* calculate first set of magics */ +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- +- gpc = -1; +- for (tpc = 0; tpc < priv->tpc_total; tpc++) { +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpcnr[gpc]--; +- +- data[tpc / 6] |= gpc << ((tpc % 6) * 5); +- } +- +- for (; tpc < 32; tpc++) +- data[tpc / 6] |= 7 << ((tpc % 6) * 5); +- +- /* and the second... */ +- shift = 0; +- ntpcv = priv->tpc_total; +- while (!(ntpcv & (1 << 4))) { +- ntpcv <<= 1; +- shift++; +- } +- +- data2[0] = (ntpcv << 16); +- data2[0] |= (shift << 21); +- data2[0] |= (((1 << (0 + 5)) % ntpcv) << 24); +- for (i = 1; i < 7; i++) +- data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5); +- +- /* GPC_BROADCAST */ +- nv_wr32(priv, 0x418bb8, (priv->tpc_total << 8) | +- priv->magic_not_rop_nr); +- for (i = 0; i < 6; i++) +- nv_wr32(priv, 0x418b08 + (i * 4), data[i]); +- +- /* GPC_BROADCAST.TP_BROADCAST */ +- nv_wr32(priv, 0x41bfd0, (priv->tpc_total << 8) | +- priv->magic_not_rop_nr | data2[0]); +- nv_wr32(priv, 0x41bfe4, data2[1]); +- for (i = 0; i < 6; i++) +- nv_wr32(priv, 0x41bf00 + (i * 4), data[i]); +- +- /* UNK78xx */ +- nv_wr32(priv, 0x4078bc, (priv->tpc_total << 8) | +- priv->magic_not_rop_nr); +- for (i = 0; i < 6; i++) +- nv_wr32(priv, 0x40780c + (i * 4), data[i]); +-} +- +-void +-nve4_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info) +-{ +- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass; +- int i; +- +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); +- +- nvc0_graph_mmio(priv, oclass->hub); +- nvc0_graph_mmio(priv, oclass->gpc); +- nvc0_graph_mmio(priv, oclass->zcull); +- nvc0_graph_mmio(priv, oclass->tpc); +- nvc0_graph_mmio(priv, oclass->ppc); +- +- nv_wr32(priv, 0x404154, 0x00000000); +- +- oclass->bundle(info); +- oclass->pagepool(info); +- oclass->attrib(info); +- oclass->unkn(priv); +- +- nvc0_grctx_generate_tpcid(priv); +- nvc0_grctx_generate_r406028(priv); +- nve4_grctx_generate_r418bb8(priv); +- nvc0_grctx_generate_r406800(priv); +- +- for (i = 0; i < 8; i++) +- nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000); +- +- nv_wr32(priv, 0x405b00, (priv->tpc_total << 8) | priv->gpc_nr); +- if (priv->gpc_nr == 1) { +- nv_mask(priv, 0x408850, 0x0000000f, priv->tpc_nr[0]); +- nv_mask(priv, 0x408958, 0x0000000f, priv->tpc_nr[0]); +- } else { +- nv_mask(priv, 0x408850, 0x0000000f, priv->gpc_nr); +- nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr); +- } +- nv_mask(priv, 0x419f78, 0x00000001, 0x00000000); +- +- nvc0_graph_icmd(priv, oclass->icmd); +- nv_wr32(priv, 0x404154, 0x00000400); +- nvc0_graph_mthd(priv, oclass->mthd); +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +- +- nv_mask(priv, 0x418800, 0x00200000, 0x00200000); +- nv_mask(priv, 0x41be10, 0x00800000, 0x00800000); +-} +- +-struct nouveau_oclass * +-nve4_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xe4), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nve4_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = nve4_grctx_pack_hub, +- .gpc = nve4_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nve4_grctx_pack_tpc, +- .ppc = nve4_grctx_pack_ppc, +- .icmd = nve4_grctx_pack_icmd, +- .mthd = nve4_grctx_pack_mthd, +- .bundle = nve4_grctx_generate_bundle, +- .bundle_size = 0x3000, +- .bundle_min_gpm_fifo_depth = 0x180, +- .bundle_token_limit = 0x600, +- .pagepool = nve4_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvd7_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x7ff, +- .alpha_nr = 0x648, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c +deleted file mode 100644 +index e9b0dcf9..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvf0.c ++++ /dev/null +@@ -1,843 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH context register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_icmd_0[] = { +- { 0x001000, 1, 0x01, 0x00000004 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x0000a9, 1, 0x01, 0x0000ffff }, +- { 0x000038, 1, 0x01, 0x0fac6881 }, +- { 0x00003d, 1, 0x01, 0x00000001 }, +- { 0x0000e8, 8, 0x01, 0x00000400 }, +- { 0x000078, 8, 0x01, 0x00000300 }, +- { 0x000050, 1, 0x01, 0x00000011 }, +- { 0x000058, 8, 0x01, 0x00000008 }, +- { 0x000208, 8, 0x01, 0x00000001 }, +- { 0x000081, 1, 0x01, 0x00000001 }, +- { 0x000085, 1, 0x01, 0x00000004 }, +- { 0x000088, 1, 0x01, 0x00000400 }, +- { 0x000090, 1, 0x01, 0x00000300 }, +- { 0x000098, 1, 0x01, 0x00001001 }, +- { 0x0000e3, 1, 0x01, 0x00000001 }, +- { 0x0000da, 1, 0x01, 0x00000001 }, +- { 0x0000f8, 1, 0x01, 0x00000003 }, +- { 0x0000fa, 1, 0x01, 0x00000001 }, +- { 0x00009f, 4, 0x01, 0x0000ffff }, +- { 0x0000b1, 1, 0x01, 0x00000001 }, +- { 0x0000ad, 1, 0x01, 0x0000013e }, +- { 0x0000e1, 1, 0x01, 0x00000010 }, +- { 0x000290, 16, 0x01, 0x00000000 }, +- { 0x0003b0, 16, 0x01, 0x00000000 }, +- { 0x0002a0, 16, 0x01, 0x00000000 }, +- { 0x000420, 16, 0x01, 0x00000000 }, +- { 0x0002b0, 16, 0x01, 0x00000000 }, +- { 0x000430, 16, 0x01, 0x00000000 }, +- { 0x0002c0, 16, 0x01, 0x00000000 }, +- { 0x0004d0, 16, 0x01, 0x00000000 }, +- { 0x000720, 16, 0x01, 0x00000000 }, +- { 0x0008c0, 16, 0x01, 0x00000000 }, +- { 0x000890, 16, 0x01, 0x00000000 }, +- { 0x0008e0, 16, 0x01, 0x00000000 }, +- { 0x0008a0, 16, 0x01, 0x00000000 }, +- { 0x0008f0, 16, 0x01, 0x00000000 }, +- { 0x00094c, 1, 0x01, 0x000000ff }, +- { 0x00094d, 1, 0x01, 0xffffffff }, +- { 0x00094e, 1, 0x01, 0x00000002 }, +- { 0x0002ec, 1, 0x01, 0x00000001 }, +- { 0x0002f2, 2, 0x01, 0x00000001 }, +- { 0x0002f5, 1, 0x01, 0x00000001 }, +- { 0x0002f7, 1, 0x01, 0x00000001 }, +- { 0x000303, 1, 0x01, 0x00000001 }, +- { 0x0002e6, 1, 0x01, 0x00000001 }, +- { 0x000466, 1, 0x01, 0x00000052 }, +- { 0x000301, 1, 0x01, 0x3f800000 }, +- { 0x000304, 1, 0x01, 0x30201000 }, +- { 0x000305, 1, 0x01, 0x70605040 }, +- { 0x000306, 1, 0x01, 0xb8a89888 }, +- { 0x000307, 1, 0x01, 0xf8e8d8c8 }, +- { 0x00030a, 1, 0x01, 0x00ffff00 }, +- { 0x00030b, 1, 0x01, 0x0000001a }, +- { 0x00030c, 1, 0x01, 0x00000001 }, +- { 0x000318, 1, 0x01, 0x00000001 }, +- { 0x000340, 1, 0x01, 0x00000000 }, +- { 0x000375, 1, 0x01, 0x00000001 }, +- { 0x00037d, 1, 0x01, 0x00000006 }, +- { 0x0003a0, 1, 0x01, 0x00000002 }, +- { 0x0003aa, 1, 0x01, 0x00000001 }, +- { 0x0003a9, 1, 0x01, 0x00000001 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000383, 1, 0x01, 0x00000011 }, +- { 0x000360, 1, 0x01, 0x00000040 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x00037a, 1, 0x01, 0x00000012 }, +- { 0x000619, 1, 0x01, 0x00000003 }, +- { 0x000811, 1, 0x01, 0x00000003 }, +- { 0x000812, 1, 0x01, 0x00000004 }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000815, 1, 0x01, 0x0000000b }, +- { 0x000800, 6, 0x01, 0x00000001 }, +- { 0x000632, 1, 0x01, 0x00000001 }, +- { 0x000633, 1, 0x01, 0x00000002 }, +- { 0x000634, 1, 0x01, 0x00000003 }, +- { 0x000635, 1, 0x01, 0x00000004 }, +- { 0x000654, 1, 0x01, 0x3f800000 }, +- { 0x000657, 1, 0x01, 0x3f800000 }, +- { 0x000655, 2, 0x01, 0x3f800000 }, +- { 0x0006cd, 1, 0x01, 0x3f800000 }, +- { 0x0007f5, 1, 0x01, 0x3f800000 }, +- { 0x0007dc, 1, 0x01, 0x39291909 }, +- { 0x0007dd, 1, 0x01, 0x79695949 }, +- { 0x0007de, 1, 0x01, 0xb9a99989 }, +- { 0x0007df, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007e8, 1, 0x01, 0x00003210 }, +- { 0x0007e9, 1, 0x01, 0x00007654 }, +- { 0x0007ea, 1, 0x01, 0x00000098 }, +- { 0x0007ec, 1, 0x01, 0x39291909 }, +- { 0x0007ed, 1, 0x01, 0x79695949 }, +- { 0x0007ee, 1, 0x01, 0xb9a99989 }, +- { 0x0007ef, 1, 0x01, 0xf9e9d9c9 }, +- { 0x0007f0, 1, 0x01, 0x00003210 }, +- { 0x0007f1, 1, 0x01, 0x00007654 }, +- { 0x0007f2, 1, 0x01, 0x00000098 }, +- { 0x0005a5, 1, 0x01, 0x00000001 }, +- { 0x000980, 128, 0x01, 0x00000000 }, +- { 0x000468, 1, 0x01, 0x00000004 }, +- { 0x00046c, 1, 0x01, 0x00000001 }, +- { 0x000470, 96, 0x01, 0x00000000 }, +- { 0x000510, 16, 0x01, 0x3f800000 }, +- { 0x000520, 1, 0x01, 0x000002b6 }, +- { 0x000529, 1, 0x01, 0x00000001 }, +- { 0x000530, 16, 0x01, 0xffff0000 }, +- { 0x000585, 1, 0x01, 0x0000003f }, +- { 0x000576, 1, 0x01, 0x00000003 }, +- { 0x00057b, 1, 0x01, 0x00000059 }, +- { 0x000586, 1, 0x01, 0x00000040 }, +- { 0x000582, 2, 0x01, 0x00000080 }, +- { 0x0005c2, 1, 0x01, 0x00000001 }, +- { 0x000638, 2, 0x01, 0x00000001 }, +- { 0x00063a, 1, 0x01, 0x00000002 }, +- { 0x00063b, 2, 0x01, 0x00000001 }, +- { 0x00063d, 1, 0x01, 0x00000002 }, +- { 0x00063e, 1, 0x01, 0x00000001 }, +- { 0x0008b8, 8, 0x01, 0x00000001 }, +- { 0x000900, 8, 0x01, 0x00000001 }, +- { 0x000908, 8, 0x01, 0x00000002 }, +- { 0x000910, 16, 0x01, 0x00000001 }, +- { 0x000920, 8, 0x01, 0x00000002 }, +- { 0x000928, 8, 0x01, 0x00000001 }, +- { 0x000662, 1, 0x01, 0x00000001 }, +- { 0x000648, 9, 0x01, 0x00000001 }, +- { 0x000658, 1, 0x01, 0x0000000f }, +- { 0x0007ff, 1, 0x01, 0x0000000a }, +- { 0x00066a, 1, 0x01, 0x40000000 }, +- { 0x00066b, 1, 0x01, 0x10000000 }, +- { 0x00066c, 2, 0x01, 0xffff0000 }, +- { 0x0007af, 2, 0x01, 0x00000008 }, +- { 0x0007f6, 1, 0x01, 0x00000001 }, +- { 0x00080b, 1, 0x01, 0x00000002 }, +- { 0x0006b2, 1, 0x01, 0x00000055 }, +- { 0x0007ad, 1, 0x01, 0x00000003 }, +- { 0x000937, 1, 0x01, 0x00000001 }, +- { 0x000971, 1, 0x01, 0x00000008 }, +- { 0x000972, 1, 0x01, 0x00000040 }, +- { 0x000973, 1, 0x01, 0x0000012c }, +- { 0x00097c, 1, 0x01, 0x00000040 }, +- { 0x000979, 1, 0x01, 0x00000003 }, +- { 0x000975, 1, 0x01, 0x00000020 }, +- { 0x000976, 1, 0x01, 0x00000001 }, +- { 0x000977, 1, 0x01, 0x00000020 }, +- { 0x000978, 1, 0x01, 0x00000001 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x00095e, 1, 0x01, 0x20164010 }, +- { 0x00095f, 1, 0x01, 0x00000020 }, +- { 0x000a0d, 1, 0x01, 0x00000006 }, +- { 0x00097d, 1, 0x01, 0x00000020 }, +- { 0x000683, 1, 0x01, 0x00000006 }, +- { 0x000685, 1, 0x01, 0x003fffff }, +- { 0x000687, 1, 0x01, 0x003fffff }, +- { 0x0006a0, 1, 0x01, 0x00000005 }, +- { 0x000840, 1, 0x01, 0x00400008 }, +- { 0x000841, 1, 0x01, 0x08000080 }, +- { 0x000842, 1, 0x01, 0x00400008 }, +- { 0x000843, 1, 0x01, 0x08000080 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ab, 1, 0x01, 0x00000002 }, +- { 0x0006ac, 1, 0x01, 0x00000080 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x0006bb, 1, 0x01, 0x000000cf }, +- { 0x0006ce, 1, 0x01, 0x2a712488 }, +- { 0x000739, 1, 0x01, 0x4085c000 }, +- { 0x00073a, 1, 0x01, 0x00000080 }, +- { 0x000786, 1, 0x01, 0x80000100 }, +- { 0x00073c, 1, 0x01, 0x00010100 }, +- { 0x00073d, 1, 0x01, 0x02800000 }, +- { 0x000787, 1, 0x01, 0x000000cf }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x000836, 1, 0x01, 0x00000001 }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c1b0, 8, 0x01, 0x0000000f }, +- { 0x00c1b8, 1, 0x01, 0x0fac6881 }, +- { 0x00c1b9, 1, 0x01, 0x00fac688 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x00c500, 1, 0x01, 0x00000003 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000002 }, +- { 0x0006aa, 1, 0x01, 0x00000001 }, +- { 0x0006ad, 2, 0x01, 0x00000100 }, +- { 0x0006b1, 1, 0x01, 0x00000011 }, +- { 0x00078c, 1, 0x01, 0x00000008 }, +- { 0x000792, 1, 0x01, 0x00000001 }, +- { 0x000794, 3, 0x01, 0x00000001 }, +- { 0x000797, 1, 0x01, 0x000000cf }, +- { 0x00079a, 1, 0x01, 0x00000002 }, +- { 0x000833, 1, 0x01, 0x04444480 }, +- { 0x0007a1, 1, 0x01, 0x00000001 }, +- { 0x0007a3, 3, 0x01, 0x00000001 }, +- { 0x000831, 1, 0x01, 0x00000004 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000008 }, +- { 0x000039, 3, 0x01, 0x00000000 }, +- { 0x000380, 1, 0x01, 0x00000001 }, +- { 0x000366, 2, 0x01, 0x00000000 }, +- { 0x000368, 1, 0x01, 0x00000fff }, +- { 0x000370, 2, 0x01, 0x00000000 }, +- { 0x000372, 1, 0x01, 0x000fffff }, +- { 0x000813, 1, 0x01, 0x00000006 }, +- { 0x000814, 1, 0x01, 0x00000008 }, +- { 0x000957, 1, 0x01, 0x00000003 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x000a04, 1, 0x01, 0x000000ff }, +- { 0x000a0b, 1, 0x01, 0x00000040 }, +- { 0x00097f, 1, 0x01, 0x00000100 }, +- { 0x000a02, 1, 0x01, 0x00000001 }, +- { 0x000809, 1, 0x01, 0x00000007 }, +- { 0x00c221, 1, 0x01, 0x00000040 }, +- { 0x00c401, 1, 0x01, 0x00000001 }, +- { 0x00c402, 1, 0x01, 0x00010001 }, +- { 0x00c403, 2, 0x01, 0x00000001 }, +- { 0x00c40e, 1, 0x01, 0x00000020 }, +- { 0x00c500, 1, 0x01, 0x00000003 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- { 0x001000, 1, 0x01, 0x00000001 }, +- { 0x000b07, 1, 0x01, 0x00000002 }, +- { 0x000b08, 2, 0x01, 0x00000100 }, +- { 0x000b0a, 1, 0x01, 0x00000001 }, +- { 0x01e100, 1, 0x01, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvf0_grctx_pack_icmd[] = { +- { nvf0_grctx_init_icmd_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_a197_0[] = { +- { 0x000800, 8, 0x40, 0x00000000 }, +- { 0x000804, 8, 0x40, 0x00000000 }, +- { 0x000808, 8, 0x40, 0x00000400 }, +- { 0x00080c, 8, 0x40, 0x00000300 }, +- { 0x000810, 1, 0x04, 0x000000cf }, +- { 0x000850, 7, 0x40, 0x00000000 }, +- { 0x000814, 8, 0x40, 0x00000040 }, +- { 0x000818, 8, 0x40, 0x00000001 }, +- { 0x00081c, 8, 0x40, 0x00000000 }, +- { 0x000820, 8, 0x40, 0x00000000 }, +- { 0x001c00, 16, 0x10, 0x00000000 }, +- { 0x001c04, 16, 0x10, 0x00000000 }, +- { 0x001c08, 16, 0x10, 0x00000000 }, +- { 0x001c0c, 16, 0x10, 0x00000000 }, +- { 0x001d00, 16, 0x10, 0x00000000 }, +- { 0x001d04, 16, 0x10, 0x00000000 }, +- { 0x001d08, 16, 0x10, 0x00000000 }, +- { 0x001d0c, 16, 0x10, 0x00000000 }, +- { 0x001f00, 16, 0x08, 0x00000000 }, +- { 0x001f04, 16, 0x08, 0x00000000 }, +- { 0x001f80, 16, 0x08, 0x00000000 }, +- { 0x001f84, 16, 0x08, 0x00000000 }, +- { 0x002000, 1, 0x04, 0x00000000 }, +- { 0x002040, 1, 0x04, 0x00000011 }, +- { 0x002080, 1, 0x04, 0x00000020 }, +- { 0x0020c0, 1, 0x04, 0x00000030 }, +- { 0x002100, 1, 0x04, 0x00000040 }, +- { 0x002140, 1, 0x04, 0x00000051 }, +- { 0x00200c, 6, 0x40, 0x00000001 }, +- { 0x002010, 1, 0x04, 0x00000000 }, +- { 0x002050, 1, 0x04, 0x00000000 }, +- { 0x002090, 1, 0x04, 0x00000001 }, +- { 0x0020d0, 1, 0x04, 0x00000002 }, +- { 0x002110, 1, 0x04, 0x00000003 }, +- { 0x002150, 1, 0x04, 0x00000004 }, +- { 0x000380, 4, 0x20, 0x00000000 }, +- { 0x000384, 4, 0x20, 0x00000000 }, +- { 0x000388, 4, 0x20, 0x00000000 }, +- { 0x00038c, 4, 0x20, 0x00000000 }, +- { 0x000700, 4, 0x10, 0x00000000 }, +- { 0x000704, 4, 0x10, 0x00000000 }, +- { 0x000708, 4, 0x10, 0x00000000 }, +- { 0x002800, 128, 0x04, 0x00000000 }, +- { 0x000a00, 16, 0x20, 0x00000000 }, +- { 0x000a04, 16, 0x20, 0x00000000 }, +- { 0x000a08, 16, 0x20, 0x00000000 }, +- { 0x000a0c, 16, 0x20, 0x00000000 }, +- { 0x000a10, 16, 0x20, 0x00000000 }, +- { 0x000a14, 16, 0x20, 0x00000000 }, +- { 0x000c00, 16, 0x10, 0x00000000 }, +- { 0x000c04, 16, 0x10, 0x00000000 }, +- { 0x000c08, 16, 0x10, 0x00000000 }, +- { 0x000c0c, 16, 0x10, 0x3f800000 }, +- { 0x000d00, 8, 0x08, 0xffff0000 }, +- { 0x000d04, 8, 0x08, 0xffff0000 }, +- { 0x000e00, 16, 0x10, 0x00000000 }, +- { 0x000e04, 16, 0x10, 0xffff0000 }, +- { 0x000e08, 16, 0x10, 0xffff0000 }, +- { 0x000d40, 4, 0x08, 0x00000000 }, +- { 0x000d44, 4, 0x08, 0x00000000 }, +- { 0x001e00, 8, 0x20, 0x00000001 }, +- { 0x001e04, 8, 0x20, 0x00000001 }, +- { 0x001e08, 8, 0x20, 0x00000002 }, +- { 0x001e0c, 8, 0x20, 0x00000001 }, +- { 0x001e10, 8, 0x20, 0x00000001 }, +- { 0x001e14, 8, 0x20, 0x00000002 }, +- { 0x001e18, 8, 0x20, 0x00000001 }, +- { 0x003400, 128, 0x04, 0x00000000 }, +- { 0x00030c, 1, 0x04, 0x00000001 }, +- { 0x001944, 1, 0x04, 0x00000000 }, +- { 0x001514, 1, 0x04, 0x00000000 }, +- { 0x000d68, 1, 0x04, 0x0000ffff }, +- { 0x00121c, 1, 0x04, 0x0fac6881 }, +- { 0x000fac, 1, 0x04, 0x00000001 }, +- { 0x001538, 1, 0x04, 0x00000001 }, +- { 0x000fe0, 2, 0x04, 0x00000000 }, +- { 0x000fe8, 1, 0x04, 0x00000014 }, +- { 0x000fec, 1, 0x04, 0x00000040 }, +- { 0x000ff0, 1, 0x04, 0x00000000 }, +- { 0x00179c, 1, 0x04, 0x00000000 }, +- { 0x001228, 1, 0x04, 0x00000400 }, +- { 0x00122c, 1, 0x04, 0x00000300 }, +- { 0x001230, 1, 0x04, 0x00010001 }, +- { 0x0007f8, 1, 0x04, 0x00000000 }, +- { 0x0015b4, 1, 0x04, 0x00000001 }, +- { 0x0015cc, 1, 0x04, 0x00000000 }, +- { 0x001534, 1, 0x04, 0x00000000 }, +- { 0x000fb0, 1, 0x04, 0x00000000 }, +- { 0x0015d0, 1, 0x04, 0x00000000 }, +- { 0x00153c, 1, 0x04, 0x00000000 }, +- { 0x0016b4, 1, 0x04, 0x00000003 }, +- { 0x000fbc, 4, 0x04, 0x0000ffff }, +- { 0x000df8, 2, 0x04, 0x00000000 }, +- { 0x001948, 1, 0x04, 0x00000000 }, +- { 0x001970, 1, 0x04, 0x00000001 }, +- { 0x00161c, 1, 0x04, 0x000009f0 }, +- { 0x000dcc, 1, 0x04, 0x00000010 }, +- { 0x00163c, 1, 0x04, 0x00000000 }, +- { 0x0015e4, 1, 0x04, 0x00000000 }, +- { 0x001160, 32, 0x04, 0x25e00040 }, +- { 0x001880, 32, 0x04, 0x00000000 }, +- { 0x000f84, 2, 0x04, 0x00000000 }, +- { 0x0017c8, 2, 0x04, 0x00000000 }, +- { 0x0017d0, 1, 0x04, 0x000000ff }, +- { 0x0017d4, 1, 0x04, 0xffffffff }, +- { 0x0017d8, 1, 0x04, 0x00000002 }, +- { 0x0017dc, 1, 0x04, 0x00000000 }, +- { 0x0015f4, 2, 0x04, 0x00000000 }, +- { 0x001434, 2, 0x04, 0x00000000 }, +- { 0x000d74, 1, 0x04, 0x00000000 }, +- { 0x000dec, 1, 0x04, 0x00000001 }, +- { 0x0013a4, 1, 0x04, 0x00000000 }, +- { 0x001318, 1, 0x04, 0x00000001 }, +- { 0x001644, 1, 0x04, 0x00000000 }, +- { 0x000748, 1, 0x04, 0x00000000 }, +- { 0x000de8, 1, 0x04, 0x00000000 }, +- { 0x001648, 1, 0x04, 0x00000000 }, +- { 0x0012a4, 1, 0x04, 0x00000000 }, +- { 0x001120, 4, 0x04, 0x00000000 }, +- { 0x001118, 1, 0x04, 0x00000000 }, +- { 0x00164c, 1, 0x04, 0x00000000 }, +- { 0x001658, 1, 0x04, 0x00000000 }, +- { 0x001910, 1, 0x04, 0x00000290 }, +- { 0x001518, 1, 0x04, 0x00000000 }, +- { 0x00165c, 1, 0x04, 0x00000001 }, +- { 0x001520, 1, 0x04, 0x00000000 }, +- { 0x001604, 1, 0x04, 0x00000000 }, +- { 0x001570, 1, 0x04, 0x00000000 }, +- { 0x0013b0, 2, 0x04, 0x3f800000 }, +- { 0x00020c, 1, 0x04, 0x00000000 }, +- { 0x001670, 1, 0x04, 0x30201000 }, +- { 0x001674, 1, 0x04, 0x70605040 }, +- { 0x001678, 1, 0x04, 0xb8a89888 }, +- { 0x00167c, 1, 0x04, 0xf8e8d8c8 }, +- { 0x00166c, 1, 0x04, 0x00000000 }, +- { 0x001680, 1, 0x04, 0x00ffff00 }, +- { 0x0012d0, 1, 0x04, 0x00000003 }, +- { 0x0012d4, 1, 0x04, 0x00000002 }, +- { 0x001684, 2, 0x04, 0x00000000 }, +- { 0x000dac, 2, 0x04, 0x00001b02 }, +- { 0x000db4, 1, 0x04, 0x00000000 }, +- { 0x00168c, 1, 0x04, 0x00000000 }, +- { 0x0015bc, 1, 0x04, 0x00000000 }, +- { 0x00156c, 1, 0x04, 0x00000000 }, +- { 0x00187c, 1, 0x04, 0x00000000 }, +- { 0x001110, 1, 0x04, 0x00000001 }, +- { 0x000dc0, 3, 0x04, 0x00000000 }, +- { 0x001234, 1, 0x04, 0x00000000 }, +- { 0x001690, 1, 0x04, 0x00000000 }, +- { 0x0012ac, 1, 0x04, 0x00000001 }, +- { 0x0002c4, 1, 0x04, 0x00000000 }, +- { 0x000790, 5, 0x04, 0x00000000 }, +- { 0x00077c, 1, 0x04, 0x00000000 }, +- { 0x001000, 1, 0x04, 0x00000010 }, +- { 0x0010fc, 1, 0x04, 0x00000000 }, +- { 0x001290, 1, 0x04, 0x00000000 }, +- { 0x000218, 1, 0x04, 0x00000010 }, +- { 0x0012d8, 1, 0x04, 0x00000000 }, +- { 0x0012dc, 1, 0x04, 0x00000010 }, +- { 0x000d94, 1, 0x04, 0x00000001 }, +- { 0x00155c, 2, 0x04, 0x00000000 }, +- { 0x001564, 1, 0x04, 0x00000fff }, +- { 0x001574, 2, 0x04, 0x00000000 }, +- { 0x00157c, 1, 0x04, 0x000fffff }, +- { 0x001354, 1, 0x04, 0x00000000 }, +- { 0x001610, 1, 0x04, 0x00000012 }, +- { 0x001608, 2, 0x04, 0x00000000 }, +- { 0x00260c, 1, 0x04, 0x00000000 }, +- { 0x0007ac, 1, 0x04, 0x00000000 }, +- { 0x00162c, 1, 0x04, 0x00000003 }, +- { 0x000210, 1, 0x04, 0x00000000 }, +- { 0x000320, 1, 0x04, 0x00000000 }, +- { 0x000324, 6, 0x04, 0x3f800000 }, +- { 0x000750, 1, 0x04, 0x00000000 }, +- { 0x000760, 1, 0x04, 0x39291909 }, +- { 0x000764, 1, 0x04, 0x79695949 }, +- { 0x000768, 1, 0x04, 0xb9a99989 }, +- { 0x00076c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x000770, 1, 0x04, 0x30201000 }, +- { 0x000774, 1, 0x04, 0x70605040 }, +- { 0x000778, 1, 0x04, 0x00009080 }, +- { 0x000780, 1, 0x04, 0x39291909 }, +- { 0x000784, 1, 0x04, 0x79695949 }, +- { 0x000788, 1, 0x04, 0xb9a99989 }, +- { 0x00078c, 1, 0x04, 0xf9e9d9c9 }, +- { 0x0007d0, 1, 0x04, 0x30201000 }, +- { 0x0007d4, 1, 0x04, 0x70605040 }, +- { 0x0007d8, 1, 0x04, 0x00009080 }, +- { 0x00037c, 1, 0x04, 0x00000001 }, +- { 0x000740, 2, 0x04, 0x00000000 }, +- { 0x002600, 1, 0x04, 0x00000000 }, +- { 0x001918, 1, 0x04, 0x00000000 }, +- { 0x00191c, 1, 0x04, 0x00000900 }, +- { 0x001920, 1, 0x04, 0x00000405 }, +- { 0x001308, 1, 0x04, 0x00000001 }, +- { 0x001924, 1, 0x04, 0x00000000 }, +- { 0x0013ac, 1, 0x04, 0x00000000 }, +- { 0x00192c, 1, 0x04, 0x00000001 }, +- { 0x00193c, 1, 0x04, 0x00002c1c }, +- { 0x000d7c, 1, 0x04, 0x00000000 }, +- { 0x000f8c, 1, 0x04, 0x00000000 }, +- { 0x0002c0, 1, 0x04, 0x00000001 }, +- { 0x001510, 1, 0x04, 0x00000000 }, +- { 0x001940, 1, 0x04, 0x00000000 }, +- { 0x000ff4, 2, 0x04, 0x00000000 }, +- { 0x00194c, 2, 0x04, 0x00000000 }, +- { 0x001968, 1, 0x04, 0x00000000 }, +- { 0x001590, 1, 0x04, 0x0000003f }, +- { 0x0007e8, 4, 0x04, 0x00000000 }, +- { 0x00196c, 1, 0x04, 0x00000011 }, +- { 0x0002e4, 1, 0x04, 0x0000b001 }, +- { 0x00036c, 2, 0x04, 0x00000000 }, +- { 0x00197c, 1, 0x04, 0x00000000 }, +- { 0x000fcc, 2, 0x04, 0x00000000 }, +- { 0x0002d8, 1, 0x04, 0x00000040 }, +- { 0x001980, 1, 0x04, 0x00000080 }, +- { 0x001504, 1, 0x04, 0x00000080 }, +- { 0x001984, 1, 0x04, 0x00000000 }, +- { 0x000300, 1, 0x04, 0x00000001 }, +- { 0x0013a8, 1, 0x04, 0x00000000 }, +- { 0x0012ec, 1, 0x04, 0x00000000 }, +- { 0x001310, 1, 0x04, 0x00000000 }, +- { 0x001314, 1, 0x04, 0x00000001 }, +- { 0x001380, 1, 0x04, 0x00000000 }, +- { 0x001384, 4, 0x04, 0x00000001 }, +- { 0x001394, 1, 0x04, 0x00000000 }, +- { 0x00139c, 1, 0x04, 0x00000000 }, +- { 0x001398, 1, 0x04, 0x00000000 }, +- { 0x001594, 1, 0x04, 0x00000000 }, +- { 0x001598, 4, 0x04, 0x00000001 }, +- { 0x000f54, 3, 0x04, 0x00000000 }, +- { 0x0019bc, 1, 0x04, 0x00000000 }, +- { 0x000f9c, 2, 0x04, 0x00000000 }, +- { 0x0012cc, 1, 0x04, 0x00000000 }, +- { 0x0012e8, 1, 0x04, 0x00000000 }, +- { 0x00130c, 1, 0x04, 0x00000001 }, +- { 0x001360, 8, 0x04, 0x00000000 }, +- { 0x00133c, 2, 0x04, 0x00000001 }, +- { 0x001344, 1, 0x04, 0x00000002 }, +- { 0x001348, 2, 0x04, 0x00000001 }, +- { 0x001350, 1, 0x04, 0x00000002 }, +- { 0x001358, 1, 0x04, 0x00000001 }, +- { 0x0012e4, 1, 0x04, 0x00000000 }, +- { 0x00131c, 4, 0x04, 0x00000000 }, +- { 0x0019c0, 1, 0x04, 0x00000000 }, +- { 0x001140, 1, 0x04, 0x00000000 }, +- { 0x0019c4, 1, 0x04, 0x00000000 }, +- { 0x0019c8, 1, 0x04, 0x00001500 }, +- { 0x00135c, 1, 0x04, 0x00000000 }, +- { 0x000f90, 1, 0x04, 0x00000000 }, +- { 0x0019e0, 8, 0x04, 0x00000001 }, +- { 0x0019cc, 1, 0x04, 0x00000001 }, +- { 0x0015b8, 1, 0x04, 0x00000000 }, +- { 0x001a00, 1, 0x04, 0x00001111 }, +- { 0x001a04, 7, 0x04, 0x00000000 }, +- { 0x000d6c, 2, 0x04, 0xffff0000 }, +- { 0x0010f8, 1, 0x04, 0x00001010 }, +- { 0x000d80, 5, 0x04, 0x00000000 }, +- { 0x000da0, 1, 0x04, 0x00000000 }, +- { 0x0007a4, 2, 0x04, 0x00000000 }, +- { 0x001508, 1, 0x04, 0x80000000 }, +- { 0x00150c, 1, 0x04, 0x40000000 }, +- { 0x001668, 1, 0x04, 0x00000000 }, +- { 0x000318, 2, 0x04, 0x00000008 }, +- { 0x000d9c, 1, 0x04, 0x00000001 }, +- { 0x000ddc, 1, 0x04, 0x00000002 }, +- { 0x000374, 1, 0x04, 0x00000000 }, +- { 0x000378, 1, 0x04, 0x00000020 }, +- { 0x0007dc, 1, 0x04, 0x00000000 }, +- { 0x00074c, 1, 0x04, 0x00000055 }, +- { 0x001420, 1, 0x04, 0x00000003 }, +- { 0x0017bc, 2, 0x04, 0x00000000 }, +- { 0x0017c4, 1, 0x04, 0x00000001 }, +- { 0x001008, 1, 0x04, 0x00000008 }, +- { 0x00100c, 1, 0x04, 0x00000040 }, +- { 0x001010, 1, 0x04, 0x0000012c }, +- { 0x000d60, 1, 0x04, 0x00000040 }, +- { 0x00075c, 1, 0x04, 0x00000003 }, +- { 0x001018, 1, 0x04, 0x00000020 }, +- { 0x00101c, 1, 0x04, 0x00000001 }, +- { 0x001020, 1, 0x04, 0x00000020 }, +- { 0x001024, 1, 0x04, 0x00000001 }, +- { 0x001444, 3, 0x04, 0x00000000 }, +- { 0x000360, 1, 0x04, 0x20164010 }, +- { 0x000364, 1, 0x04, 0x00000020 }, +- { 0x000368, 1, 0x04, 0x00000000 }, +- { 0x000de4, 1, 0x04, 0x00000000 }, +- { 0x000204, 1, 0x04, 0x00000006 }, +- { 0x000208, 1, 0x04, 0x00000000 }, +- { 0x0002cc, 2, 0x04, 0x003fffff }, +- { 0x001220, 1, 0x04, 0x00000005 }, +- { 0x000fdc, 1, 0x04, 0x00000000 }, +- { 0x000f98, 1, 0x04, 0x00400008 }, +- { 0x001284, 1, 0x04, 0x08000080 }, +- { 0x001450, 1, 0x04, 0x00400008 }, +- { 0x001454, 1, 0x04, 0x08000080 }, +- { 0x000214, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvf0_grctx_pack_mthd[] = { +- { nvf0_grctx_init_a197_0, 0xa197 }, +- { nvc0_grctx_init_902d_0, 0x902d }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_fe_0[] = { +- { 0x404004, 8, 0x04, 0x00000000 }, +- { 0x404024, 1, 0x04, 0x0000e000 }, +- { 0x404028, 8, 0x04, 0x00000000 }, +- { 0x4040a8, 8, 0x04, 0x00000000 }, +- { 0x4040c8, 1, 0x04, 0xf800008f }, +- { 0x4040d0, 6, 0x04, 0x00000000 }, +- { 0x4040e8, 1, 0x04, 0x00001000 }, +- { 0x4040f8, 1, 0x04, 0x00000000 }, +- { 0x404100, 10, 0x04, 0x00000000 }, +- { 0x404130, 2, 0x04, 0x00000000 }, +- { 0x404138, 1, 0x04, 0x20000040 }, +- { 0x404150, 1, 0x04, 0x0000002e }, +- { 0x404154, 1, 0x04, 0x00000400 }, +- { 0x404158, 1, 0x04, 0x00000200 }, +- { 0x404164, 1, 0x04, 0x00000055 }, +- { 0x40417c, 2, 0x04, 0x00000000 }, +- { 0x4041a0, 4, 0x04, 0x00000000 }, +- { 0x404200, 1, 0x04, 0x0000a197 }, +- { 0x404204, 1, 0x04, 0x0000a1c0 }, +- { 0x404208, 1, 0x04, 0x0000a140 }, +- { 0x40420c, 1, 0x04, 0x0000902d }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_grctx_init_pri_0[] = { +- { 0x404404, 12, 0x04, 0x00000000 }, +- { 0x404438, 1, 0x04, 0x00000000 }, +- { 0x404460, 2, 0x04, 0x00000000 }, +- { 0x404468, 1, 0x04, 0x00ffffff }, +- { 0x40446c, 1, 0x04, 0x00000000 }, +- { 0x404480, 1, 0x04, 0x00000001 }, +- { 0x404498, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_grctx_init_cwd_0[] = { +- { 0x405b00, 1, 0x04, 0x00000000 }, +- { 0x405b10, 1, 0x04, 0x00001000 }, +- { 0x405b20, 1, 0x04, 0x04000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_pd_0[] = { +- { 0x406020, 1, 0x04, 0x034103c1 }, +- { 0x406028, 4, 0x04, 0x00000001 }, +- { 0x4064a8, 1, 0x04, 0x00000000 }, +- { 0x4064ac, 1, 0x04, 0x00003fff }, +- { 0x4064b0, 3, 0x04, 0x00000000 }, +- { 0x4064c0, 1, 0x04, 0x802000f0 }, +- { 0x4064c4, 1, 0x04, 0x0192ffff }, +- { 0x4064c8, 1, 0x04, 0x018007c0 }, +- { 0x4064cc, 9, 0x04, 0x00000000 }, +- { 0x4064fc, 1, 0x04, 0x0000022a }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_be_0[] = { +- { 0x408800, 1, 0x04, 0x12802a3c }, +- { 0x408804, 1, 0x04, 0x00000040 }, +- { 0x408808, 1, 0x04, 0x1003e005 }, +- { 0x408840, 1, 0x04, 0x0000000b }, +- { 0x408900, 1, 0x04, 0x3080b801 }, +- { 0x408904, 1, 0x04, 0x62000001 }, +- { 0x408908, 1, 0x04, 0x00c8102f }, +- { 0x408980, 1, 0x04, 0x0000011d }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvf0_grctx_pack_hub[] = { +- { nvc0_grctx_init_main_0 }, +- { nvf0_grctx_init_fe_0 }, +- { nvf0_grctx_init_pri_0 }, +- { nve4_grctx_init_memfmt_0 }, +- { nve4_grctx_init_ds_0 }, +- { nvf0_grctx_init_cwd_0 }, +- { nvf0_grctx_init_pd_0 }, +- { nvc0_grctx_init_rstr2d_0 }, +- { nve4_grctx_init_scc_0 }, +- { nvf0_grctx_init_be_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_setup_0[] = { +- { 0x418800, 1, 0x04, 0x7006860a }, +- { 0x418808, 1, 0x04, 0x00000000 }, +- { 0x41880c, 1, 0x04, 0x00000030 }, +- { 0x418810, 1, 0x04, 0x00000000 }, +- { 0x418828, 1, 0x04, 0x00000044 }, +- { 0x418830, 1, 0x04, 0x10000001 }, +- { 0x4188d8, 1, 0x04, 0x00000008 }, +- { 0x4188e0, 1, 0x04, 0x01000000 }, +- { 0x4188e8, 5, 0x04, 0x00000000 }, +- { 0x4188fc, 1, 0x04, 0x20100018 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_grctx_init_gpc_unk_2[] = { +- { 0x418d24, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvf0_grctx_pack_gpc[] = { +- { nvc0_grctx_init_gpc_unk_0 }, +- { nvd9_grctx_init_prop_0 }, +- { nvd9_grctx_init_gpc_unk_1 }, +- { nvf0_grctx_init_setup_0 }, +- { nvc0_grctx_init_zcull_0 }, +- { nvd9_grctx_init_crstr_0 }, +- { nve4_grctx_init_gpm_0 }, +- { nvf0_grctx_init_gpc_unk_2 }, +- { nvc0_grctx_init_gcc_0 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_grctx_init_tex_0[] = { +- { 0x419a00, 1, 0x04, 0x000000f0 }, +- { 0x419a04, 1, 0x04, 0x00000001 }, +- { 0x419a08, 1, 0x04, 0x00000021 }, +- { 0x419a0c, 1, 0x04, 0x00020000 }, +- { 0x419a10, 1, 0x04, 0x00000000 }, +- { 0x419a14, 1, 0x04, 0x00000200 }, +- { 0x419a1c, 1, 0x04, 0x0000c000 }, +- { 0x419a20, 1, 0x04, 0x00020800 }, +- { 0x419a30, 1, 0x04, 0x00000001 }, +- { 0x419ac4, 1, 0x04, 0x0037f440 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_grctx_init_mpc_0[] = { +- { 0x419c00, 1, 0x04, 0x0000001a }, +- { 0x419c04, 1, 0x04, 0x80000006 }, +- { 0x419c08, 1, 0x04, 0x00000002 }, +- { 0x419c20, 1, 0x04, 0x00000000 }, +- { 0x419c24, 1, 0x04, 0x00084210 }, +- { 0x419c28, 1, 0x04, 0x3efbefbe }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_grctx_init_l1c_0[] = { +- { 0x419ce8, 1, 0x04, 0x00000000 }, +- { 0x419cf4, 1, 0x04, 0x00000203 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_sm_0[] = { +- { 0x419e04, 1, 0x04, 0x00000000 }, +- { 0x419e08, 1, 0x04, 0x0000001d }, +- { 0x419e0c, 1, 0x04, 0x00000000 }, +- { 0x419e10, 1, 0x04, 0x00001c02 }, +- { 0x419e44, 1, 0x04, 0x0013eff2 }, +- { 0x419e48, 1, 0x04, 0x00000000 }, +- { 0x419e4c, 1, 0x04, 0x0000007f }, +- { 0x419e50, 2, 0x04, 0x00000000 }, +- { 0x419e58, 1, 0x04, 0x00000001 }, +- { 0x419e5c, 3, 0x04, 0x00000000 }, +- { 0x419e68, 1, 0x04, 0x00000002 }, +- { 0x419e6c, 12, 0x04, 0x00000000 }, +- { 0x419eac, 1, 0x04, 0x00001f8f }, +- { 0x419eb0, 1, 0x04, 0x0db00d2f }, +- { 0x419eb8, 1, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x0001304f }, +- { 0x419f30, 4, 0x04, 0x00000000 }, +- { 0x419f40, 1, 0x04, 0x00000018 }, +- { 0x419f44, 3, 0x04, 0x00000000 }, +- { 0x419f58, 1, 0x04, 0x00000000 }, +- { 0x419f70, 1, 0x04, 0x00007300 }, +- { 0x419f78, 1, 0x04, 0x000000eb }, +- { 0x419f7c, 1, 0x04, 0x00000404 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvf0_grctx_pack_tpc[] = { +- { nvd7_grctx_init_pe_0 }, +- { nvf0_grctx_init_tex_0 }, +- { nvf0_grctx_init_mpc_0 }, +- { nvf0_grctx_init_l1c_0 }, +- { nvf0_grctx_init_sm_0 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_grctx_init_cbm_0[] = { +- { 0x41bec0, 1, 0x04, 0x10000000 }, +- { 0x41bec4, 1, 0x04, 0x00037f7f }, +- { 0x41bee4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nvf0_grctx_pack_ppc[] = { +- { nve4_grctx_init_pes_0 }, +- { nvf0_grctx_init_cbm_0 }, +- { nvd7_grctx_init_wwdx_0 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context implementation +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) { +- .base.handle = NV_ENGCTX(GR, 0xf0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_context_ctor, +- .dtor = nvc0_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +- .main = nve4_grctx_generate_main, +- .unkn = nve4_grctx_generate_unkn, +- .hub = nvf0_grctx_pack_hub, +- .gpc = nvf0_grctx_pack_gpc, +- .zcull = nvc0_grctx_pack_zcull, +- .tpc = nvf0_grctx_pack_tpc, +- .ppc = nvf0_grctx_pack_ppc, +- .icmd = nvf0_grctx_pack_icmd, +- .mthd = nvf0_grctx_pack_mthd, +- .bundle = nve4_grctx_generate_bundle, +- .bundle_size = 0x3000, +- .bundle_min_gpm_fifo_depth = 0x180, +- .bundle_token_limit = 0x7c0, +- .pagepool = nve4_grctx_generate_pagepool, +- .pagepool_size = 0x8000, +- .attrib = nvd7_grctx_generate_attrib, +- .attrib_nr_max = 0x324, +- .attrib_nr = 0x218, +- .alpha_nr_max = 0x7ff, +- .alpha_nr = 0x648, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc +deleted file mode 100644 +index e37d8106..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/com.fuc ++++ /dev/null +@@ -1,335 +0,0 @@ +-/* fuc microcode util functions for nvc0 PGRAPH +- * +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_CODE +-// queue_put - add request to queue +-// +-// In : $r13 queue pointer +-// $r14 command +-// $r15 data +-// +-queue_put: +- // make sure we have space.. +- ld b32 $r8 D[$r13 + 0x0] // GET +- ld b32 $r9 D[$r13 + 0x4] // PUT +- xor $r8 8 +- cmpu b32 $r8 $r9 +- bra ne #queue_put_next +- mov $r15 E_CMD_OVERFLOW +- call(error) +- ret +- +- // store cmd/data on queue +- queue_put_next: +- and $r8 $r9 7 +- shl b32 $r8 3 +- add b32 $r8 $r13 +- add b32 $r8 8 +- st b32 D[$r8 + 0x0] $r14 +- st b32 D[$r8 + 0x4] $r15 +- +- // update PUT +- add b32 $r9 1 +- and $r9 0xf +- st b32 D[$r13 + 0x4] $r9 +- ret +- +-// queue_get - fetch request from queue +-// +-// In : $r13 queue pointer +-// +-// Out: $p1 clear on success (data available) +-// $r14 command +-// $r15 data +-// +-queue_get: +- bset $flags $p1 +- ld b32 $r8 D[$r13 + 0x0] // GET +- ld b32 $r9 D[$r13 + 0x4] // PUT +- cmpu b32 $r8 $r9 +- bra e #queue_get_done +- // fetch first cmd/data pair +- and $r9 $r8 7 +- shl b32 $r9 3 +- add b32 $r9 $r13 +- add b32 $r9 8 +- ld b32 $r14 D[$r9 + 0x0] +- ld b32 $r15 D[$r9 + 0x4] +- +- // update GET +- add b32 $r8 1 +- and $r8 0xf +- st b32 D[$r13 + 0x0] $r8 +- bclr $flags $p1 +-queue_get_done: +- ret +- +-// nv_rd32 - read 32-bit value from nv register +-// +-// In : $r14 register +-// Out: $r15 value +-// +-nv_rd32: +- mov b32 $r12 $r14 +- bset $r12 31 // MMIO_CTRL_PENDING +- nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) +- nv_rd32_wait: +- nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) +- xbit $r12 $r12 31 +- bra ne #nv_rd32_wait +- mov $r10 6 // DONE_MMIO_RD +- call(wait_doneo) +- nv_iord($r15, NV_PGRAPH_FECS_MMIO_RDVAL, 0) +- ret +- +-// nv_wr32 - write 32-bit value to nv register +-// +-// In : $r14 register +-// $r15 value +-// +-nv_wr32: +- nv_iowr(NV_PGRAPH_FECS_MMIO_WRVAL, 0, $r15) +- mov b32 $r12 $r14 +- bset $r12 31 // MMIO_CTRL_PENDING +- bset $r12 30 // MMIO_CTRL_WRITE +- nv_iowr(NV_PGRAPH_FECS_MMIO_CTRL, 0, $r12) +- nv_wr32_wait: +- nv_iord($r12, NV_PGRAPH_FECS_MMIO_CTRL, 0) +- xbit $r12 $r12 31 +- bra ne #nv_wr32_wait +- ret +- +-// wait_donez - wait on FUC_DONE bit to become clear +-// +-// In : $r10 bit to wait on +-// +-wait_donez: +- trace_set(T_WAIT); +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) +- wait_donez_ne: +- nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) +- xbit $r8 $r8 $r10 +- bra ne #wait_donez_ne +- trace_clr(T_WAIT) +- ret +- +-// wait_doneo - wait on FUC_DONE bit to become set +-// +-// In : $r10 bit to wait on +-// +-wait_doneo: +- trace_set(T_WAIT); +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(6), 0, $r10) +- wait_doneo_e: +- nv_iord($r8, NV_PGRAPH_FECS_SIGNAL, 0) +- xbit $r8 $r8 $r10 +- bra e #wait_doneo_e +- trace_clr(T_WAIT) +- ret +- +-// mmctx_size - determine size of a mmio list transfer +-// +-// In : $r14 mmio list head +-// $r15 mmio list tail +-// Out: $r15 transfer size (in bytes) +-// +-mmctx_size: +- clear b32 $r9 +- nv_mmctx_size_loop: +- ld b32 $r8 D[$r14] +- shr b32 $r8 26 +- add b32 $r8 1 +- shl b32 $r8 2 +- add b32 $r9 $r8 +- add b32 $r14 4 +- cmpu b32 $r14 $r15 +- bra ne #nv_mmctx_size_loop +- mov b32 $r15 $r9 +- ret +- +-// mmctx_xfer - execute a list of mmio transfers +-// +-// In : $r10 flags +-// bit 0: direction (0 = save, 1 = load) +-// bit 1: set if first transfer +-// bit 2: set if last transfer +-// $r11 base +-// $r12 mmio list head +-// $r13 mmio list tail +-// $r14 multi_stride +-// $r15 multi_mask +-// +-mmctx_xfer: +- trace_set(T_MMCTX) +- clear b32 $r9 +- or $r11 $r11 +- bra e #mmctx_base_disabled +- nv_iowr(NV_PGRAPH_FECS_MMCTX_BASE, 0, $r11) +- bset $r9 0 // BASE_EN +- mmctx_base_disabled: +- or $r14 $r14 +- bra e #mmctx_multi_disabled +- nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE, 0, $r14) +- nv_iowr(NV_PGRAPH_FECS_MMCTX_MULTI_MASK, 0, $r15) +- bset $r9 1 // MULTI_EN +- mmctx_multi_disabled: +- +- xbit $r11 $r10 0 +- shl b32 $r11 16 // DIR +- bset $r11 12 // QLIMIT = 0x10 +- xbit $r14 $r10 1 +- shl b32 $r14 17 +- or $r11 $r14 // START_TRIGGER +- nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) +- +- // loop over the mmio list, and send requests to the hw +- mmctx_exec_loop: +- // wait for space in mmctx queue +- mmctx_wait_free: +- nv_iord($r14, NV_PGRAPH_FECS_MMCTX_CTRL, 0) +- and $r14 0x1f +- bra e #mmctx_wait_free +- +- // queue up an entry +- ld b32 $r14 D[$r12] +- or $r14 $r9 +- nv_iowr(NV_PGRAPH_FECS_MMCTX_QUEUE, 0, $r14) +- add b32 $r12 4 +- cmpu b32 $r12 $r13 +- bra ne #mmctx_exec_loop +- +- xbit $r11 $r10 2 +- bra ne #mmctx_stop +- // wait for queue to empty +- mmctx_fini_wait: +- nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) +- and $r11 0x1f +- cmpu b32 $r11 0x10 +- bra ne #mmctx_fini_wait +- mov $r10 5 // DONE_MMCTX +- call(wait_donez) +- bra #mmctx_done +- mmctx_stop: +- xbit $r11 $r10 0 +- shl b32 $r11 16 // DIR +- bset $r11 12 // QLIMIT = 0x10 +- bset $r11 18 // STOP_TRIGGER +- nv_iowr(NV_PGRAPH_FECS_MMCTX_CTRL, 0, $r11) +- mmctx_stop_wait: +- // wait for STOP_TRIGGER to clear +- nv_iord($r11, NV_PGRAPH_FECS_MMCTX_CTRL, 0) +- xbit $r11 $r11 18 +- bra ne #mmctx_stop_wait +- mmctx_done: +- trace_clr(T_MMCTX) +- ret +- +-// Wait for DONE_STRAND +-// +-strand_wait: +- push $r10 +- mov $r10 2 +- call(wait_donez) +- pop $r10 +- ret +- +-// unknown - call before issuing strand commands +-// +-strand_pre: +- mov $r9 NV_PGRAPH_FECS_STRAND_CMD_ENABLE +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) +- call(strand_wait) +- ret +- +-// unknown - call after issuing strand commands +-// +-strand_post: +- mov $r9 NV_PGRAPH_FECS_STRAND_CMD_DISABLE +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r9) +- call(strand_wait) +- ret +- +-// Selects strand set?! +-// +-// In: $r14 id +-// +-strand_set: +- mov $r12 0xf +- nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r12) +- mov $r12 NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) +- nv_iowr(NV_PGRAPH_FECS_STRAND_FILTER, 0x3f, $r14) +- mov $r12 NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) +- call(strand_wait) +- ret +- +-// Initialise strand context data +-// +-// In : $r15 context base +-// Out: $r15 context size (in bytes) +-// +-// Strandset(?) 3 hardcoded currently +-// +-strand_ctx_init: +- trace_set(T_STRINIT) +- call(strand_pre) +- mov $r14 3 +- call(strand_set) +- +- clear b32 $r12 +- nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r12) +- mov $r12 NV_PGRAPH_FECS_STRAND_CMD_SEEK +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) +- call(strand_wait) +- sub b32 $r12 $r0 1 +- nv_iowr(NV_PGRAPH_FECS_STRAND_DATA, 0x3f, $r12) +- mov $r12 NV_PGRAPH_FECS_STRAND_CMD_GET_INFO +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r12) +- call(strand_wait) +- call(strand_post) +- +- // read the size of each strand, poke the context offset of +- // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry +- // about it later then. +- nv_mkio($r8, NV_PGRAPH_FECS_STRAND_SAVE_SWBASE, 0x00) +- nv_iord($r9, NV_PGRAPH_FECS_STRANDS_CNT, 0x00) +- shr b32 $r14 $r15 8 +- ctx_init_strand_loop: +- iowr I[$r8 + 0x000] $r14 // STRAND_SAVE_SWBASE +- iowr I[$r8 + 0x100] $r14 // STRAND_LOAD_SWBASE +- iord $r10 I[$r8 + 0x200] // STRAND_SIZE +- shr b32 $r10 6 +- add b32 $r10 1 +- add b32 $r14 $r10 +- add b32 $r8 4 +- sub b32 $r9 1 +- bra ne #ctx_init_strand_loop +- +- shl b32 $r14 8 +- sub b32 $r15 $r14 $r15 +- trace_clr(T_STRINIT) +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc +deleted file mode 100644 +index 7445f12b..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpc.fuc ++++ /dev/null +@@ -1,378 +0,0 @@ +-/* fuc microcode for nvc0 PGRAPH/GPC +- * +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-/* TODO +- * - bracket certain functions with scratch writes, useful for debugging +- * - watchdog timer around ctx operations +- */ +- +-#ifdef INCLUDE_DATA +-gpc_mmio_list_head: .b32 #mmio_list_base +-gpc_mmio_list_tail: +-tpc_mmio_list_head: .b32 #mmio_list_base +-tpc_mmio_list_tail: +-unk_mmio_list_head: .b32 #mmio_list_base +-unk_mmio_list_tail: .b32 #mmio_list_base +- +-gpc_id: .b32 0 +- +-tpc_count: .b32 0 +-tpc_mask: .b32 0 +- +-#if NV_PGRAPH_GPCX_UNK__SIZE > 0 +-unk_count: .b32 0 +-unk_mask: .b32 0 +-#endif +- +-cmd_queue: queue_init +- +-mmio_list_base: +-#endif +- +-#ifdef INCLUDE_CODE +-// reports an exception to the host +-// +-// In: $r15 error code (see os.h) +-// +-error: +- push $r14 +- nv_wr32(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), $r15) +- mov $r15 1 +- nv_wr32(NV_PGRAPH_FECS_INTR_UP_SET, $r15) +- pop $r14 +- ret +- +-// GPC fuc initialisation, executed by triggering ucode start, will +-// fall through to main loop after completion. +-// +-// Input: +-// CC_SCRATCH[1]: context base +-// +-// Output: +-// CC_SCRATCH[0]: +-// 31:31: set to signal completion +-// CC_SCRATCH[1]: +-// 31:0: GPC context size +-// +-init: +- clear b32 $r0 +- +- // setup stack +- nv_iord($r1, NV_PGRAPH_GPCX_GPCCS_CAPS, 0) +- extr $r1 $r1 9:17 +- shl b32 $r1 8 +- mov $sp $r1 +- +- // enable fifo access +- mov $r2 NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_ACCESS, 0, $r2) +- +- // setup i0 handler, and route all interrupts to it +- mov $r1 #ih +- mov $iv0 $r1 +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE, 0, $r0) +- +- // enable fifo interrupt +- mov $r2 NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET, 0, $r2) +- +- // enable interrupts +- bset $flags ie0 +- +- // figure out which GPC we are, and how many TPCs we have +- nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_UNITS, 0) +- mov $r3 1 +- and $r2 0x1f +- shl b32 $r3 $r2 +- sub b32 $r3 1 +- st b32 D[$r0 + #tpc_count] $r2 +- st b32 D[$r0 + #tpc_mask] $r3 +- nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_MYINDEX, 0) +- st b32 D[$r0 + #gpc_id] $r2 +- +-#if NV_PGRAPH_GPCX_UNK__SIZE > 0 +- // figure out which, and how many, UNKs are actually present +- imm32($r14, 0x500c30) +- clear b32 $r2 +- clear b32 $r3 +- clear b32 $r4 +- init_unk_loop: +- call(nv_rd32) +- cmp b32 $r15 0 +- bra z #init_unk_next +- mov $r15 1 +- shl b32 $r15 $r2 +- or $r4 $r15 +- add b32 $r3 1 +- init_unk_next: +- add b32 $r2 1 +- add b32 $r14 4 +- cmp b32 $r2 NV_PGRAPH_GPCX_UNK__SIZE +- bra ne #init_unk_loop +- init_unk_done: +- st b32 D[$r0 + #unk_count] $r3 +- st b32 D[$r0 + #unk_mask] $r4 +-#endif +- +- // initialise context base, and size tracking +- nv_iord($r2, NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0) +- clear b32 $r3 // track GPC context size here +- +- // set mmctx base addresses now so we don't have to do it later, +- // they don't currently ever change +- shr b32 $r5 $r2 8 +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE, 0, $r5) +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE, 0, $r5) +- +- // calculate GPC mmio context size +- ld b32 $r14 D[$r0 + #gpc_mmio_list_head] +- ld b32 $r15 D[$r0 + #gpc_mmio_list_tail] +- call(mmctx_size) +- add b32 $r2 $r15 +- add b32 $r3 $r15 +- +- // calculate per-TPC mmio context size +- ld b32 $r14 D[$r0 + #tpc_mmio_list_head] +- ld b32 $r15 D[$r0 + #tpc_mmio_list_tail] +- call(mmctx_size) +- ld b32 $r14 D[$r0 + #tpc_count] +- mulu $r14 $r15 +- add b32 $r2 $r14 +- add b32 $r3 $r14 +- +-#if NV_PGRAPH_GPCX_UNK__SIZE > 0 +- // calculate per-UNK mmio context size +- ld b32 $r14 D[$r0 + #unk_mmio_list_head] +- ld b32 $r15 D[$r0 + #unk_mmio_list_tail] +- call(mmctx_size) +- ld b32 $r14 D[$r0 + #unk_count] +- mulu $r14 $r15 +- add b32 $r2 $r14 +- add b32 $r3 $r14 +-#endif +- +- // round up base/size to 256 byte boundary (for strand SWBASE) +- shr b32 $r3 2 +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT, 0, $r3) // wtf for?! +- shr b32 $r2 8 +- shr b32 $r3 6 +- add b32 $r2 1 +- add b32 $r3 1 +- shl b32 $r2 8 +- shl b32 $r3 8 +- +- // calculate size of strand context data +- mov b32 $r15 $r2 +- call(strand_ctx_init) +- add b32 $r3 $r15 +- +- // save context size, and tell HUB we're done +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(1), 0, $r3) +- clear b32 $r2 +- bset $r2 31 +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(0), 0, $r2) +- +-// Main program loop, very simple, sleeps until woken up by the interrupt +-// handler, pulls a command from the queue and executes its handler +-// +-main: +- bset $flags $p0 +- sleep $p0 +- mov $r13 #cmd_queue +- call(queue_get) +- bra $p1 #main +- +- // 0x0000-0x0003 are all context transfers +- cmpu b32 $r14 0x04 +- bra nc #main_not_ctx_xfer +- // fetch $flags and mask off $p1/$p2 +- mov $r1 $flags +- mov $r2 0x0006 +- not b32 $r2 +- and $r1 $r2 +- // set $p1/$p2 according to transfer type +- shl b32 $r14 1 +- or $r1 $r14 +- mov $flags $r1 +- // transfer context data +- call(ctx_xfer) +- bra #main +- +- main_not_ctx_xfer: +- shl b32 $r15 $r14 16 +- or $r15 E_BAD_COMMAND +- call(error) +- bra #main +- +-// interrupt handler +-ih: +- push $r8 +- mov $r8 $flags +- push $r8 +- push $r9 +- push $r10 +- push $r11 +- push $r13 +- push $r14 +- push $r15 +- clear b32 $r0 +- +- // incoming fifo command? +- nv_iord($r10, NV_PGRAPH_GPCX_GPCCS_INTR, 0) +- and $r11 $r10 NV_PGRAPH_GPCX_GPCCS_INTR_FIFO +- bra e #ih_no_fifo +- // queue incoming fifo command for later processing +- mov $r13 #cmd_queue +- nv_iord($r14, NV_PGRAPH_GPCX_GPCCS_FIFO_CMD, 0) +- nv_iord($r15, NV_PGRAPH_GPCX_GPCCS_FIFO_DATA, 0) +- call(queue_put) +- mov $r14 1 +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_FIFO_ACK, 0, $r14) +- +- // ack, and wake up main() +- ih_no_fifo: +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_INTR_ACK, 0, $r10) +- +- pop $r15 +- pop $r14 +- pop $r13 +- pop $r11 +- pop $r10 +- pop $r9 +- pop $r8 +- mov $flags $r8 +- pop $r8 +- bclr $flags $p0 +- iret +- +-// Set this GPC's bit in HUB_BAR, used to signal completion of various +-// activities to the HUB fuc +-// +-hub_barrier_done: +- mov $r15 1 +- ld b32 $r14 D[$r0 + #gpc_id] +- shl b32 $r15 $r14 +- nv_wr32(0x409418, $r15) // 0x409418 - HUB_BAR_SET +- ret +- +-// Disables various things, waits a bit, and re-enables them.. +-// +-// Not sure how exactly this helps, perhaps "ENABLE" is not such a +-// good description for the bits we turn off? Anyways, without this, +-// funny things happen. +-// +-ctx_redswitch: +- mov $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) +- mov $r14 8 +- ctx_redswitch_delay: +- sub b32 $r14 1 +- bra ne #ctx_redswitch_delay +- or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 +- or $r15 NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_RED_SWITCH, 0, $r15) +- ret +- +-// Transfer GPC context data between GPU and storage area +-// +-// In: $r15 context base address +-// $p1 clear on save, set on load +-// $p2 set if opposite direction done/will be done, so: +-// on save it means: "a load will follow this save" +-// on load it means: "a save preceeded this load" +-// +-ctx_xfer: +- // set context base address +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_MEM_BASE, 0, $r15) +- bra not $p1 #ctx_xfer_not_load +- call(ctx_redswitch) +- ctx_xfer_not_load: +- +- // strands +- call(strand_pre) +- clear b32 $r2 +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT, 0x3f, $r2) +- xbit $r2 $flags $p1 // SAVE/LOAD +- add b32 $r2 NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE +- nv_iowr(NV_PGRAPH_GPCX_GPCCS_STRAND_CMD, 0x3f, $r2) +- +- // mmio context +- xbit $r10 $flags $p1 // direction +- or $r10 2 // first +- imm32($r11,0x500000) +- ld b32 $r12 D[$r0 + #gpc_id] +- shl b32 $r12 15 +- add b32 $r11 $r12 // base = NV_PGRAPH_GPCn +- ld b32 $r12 D[$r0 + #gpc_mmio_list_head] +- ld b32 $r13 D[$r0 + #gpc_mmio_list_tail] +- mov $r14 0 // not multi +- call(mmctx_xfer) +- +- // per-TPC mmio context +- xbit $r10 $flags $p1 // direction +-#if !NV_PGRAPH_GPCX_UNK__SIZE +- or $r10 4 // last +-#endif +- imm32($r11, 0x504000) +- ld b32 $r12 D[$r0 + #gpc_id] +- shl b32 $r12 15 +- add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_TPC0 +- ld b32 $r12 D[$r0 + #tpc_mmio_list_head] +- ld b32 $r13 D[$r0 + #tpc_mmio_list_tail] +- ld b32 $r15 D[$r0 + #tpc_mask] +- mov $r14 0x800 // stride = 0x800 +- call(mmctx_xfer) +- +-#if NV_PGRAPH_GPCX_UNK__SIZE > 0 +- // per-UNK mmio context +- xbit $r10 $flags $p1 // direction +- or $r10 4 // last +- imm32($r11, 0x503000) +- ld b32 $r12 D[$r0 + #gpc_id] +- shl b32 $r12 15 +- add b32 $r11 $r12 // base = NV_PGRAPH_GPCn_UNK0 +- ld b32 $r12 D[$r0 + #unk_mmio_list_head] +- ld b32 $r13 D[$r0 + #unk_mmio_list_tail] +- ld b32 $r15 D[$r0 + #unk_mask] +- mov $r14 0x200 // stride = 0x200 +- call(mmctx_xfer) +-#endif +- +- // wait for strands to finish +- call(strand_wait) +- +- // if load, or a save without a load following, do some +- // unknown stuff that's done after finishing a block of +- // strand commands +- bra $p1 #ctx_xfer_post +- bra not $p2 #ctx_xfer_done +- ctx_xfer_post: +- call(strand_post) +- +- // mark completion in HUB's barrier +- ctx_xfer_done: +- call(hub_barrier_done) +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 +deleted file mode 100644 +index e7306038..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5 ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 +- +-#define CHIPSET GK208 +-#include "macros.fuc" +- +-.section #gm107_grgpc_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "gpc.fuc" +-#undef INCLUDE_DATA +- +-.section #gm107_grgpc_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "gpc.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h +deleted file mode 100644 +index 6d53b67d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcgm107.fuc5.h ++++ /dev/null +@@ -1,473 +0,0 @@ +-uint32_t gm107_grgpc_data[] = { +-/* 0x0000: gpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0004: gpc_mmio_list_tail */ +-/* 0x0004: tpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0008: tpc_mmio_list_tail */ +-/* 0x0008: unk_mmio_list_head */ +- 0x0000006c, +-/* 0x000c: unk_mmio_list_tail */ +- 0x0000006c, +-/* 0x0010: gpc_id */ +- 0x00000000, +-/* 0x0014: tpc_count */ +- 0x00000000, +-/* 0x0018: tpc_mask */ +- 0x00000000, +-/* 0x001c: unk_count */ +- 0x00000000, +-/* 0x0020: unk_mask */ +- 0x00000000, +-/* 0x0024: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t gm107_grgpc_code[] = { +- 0x03140ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0xf489a408, +- 0x020f0b1b, +- 0x0002f87e, +-/* 0x001a: queue_put_next */ +- 0x98c400f8, +- 0x0384b607, +- 0xb6008dbb, +- 0x8eb50880, +- 0x018fb500, +- 0xf00190b6, +- 0xd9b50f94, +-/* 0x0037: queue_get */ +- 0xf400f801, +- 0xd8980131, +- 0x01d99800, +- 0x0bf489a4, +- 0x0789c421, +- 0xbb0394b6, +- 0x90b6009d, +- 0x009e9808, +- 0xb6019f98, +- 0x84f00180, +- 0x00d8b50f, +-/* 0x0063: queue_get_done */ +- 0xf80132f4, +-/* 0x0065: nv_rd32 */ +- 0xf0ecb200, +- 0x00801fc9, +- 0x0cf601ca, +-/* 0x0073: nv_rd32_wait */ +- 0x8c04bd00, +- 0xcf01ca00, +- 0xccc800cc, +- 0xf61bf41f, +- 0xec7e060a, +- 0x008f0000, +- 0xffcf01cb, +-/* 0x008f: nv_wr32 */ +- 0x8000f800, +- 0xf601cc00, +- 0x04bd000f, +- 0xc9f0ecb2, +- 0x1ec9f01f, +- 0x01ca0080, +- 0xbd000cf6, +-/* 0x00a9: nv_wr32_wait */ +- 0xca008c04, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f61b, +-/* 0x00b8: wait_donez */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x00cf: wait_donez_ne */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf61bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x00ec: wait_doneo */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x0103: wait_doneo_e */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf60bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x0120: mmctx_size */ +-/* 0x0122: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0x1bf4efa4, +- 0xf89fb2ec, +-/* 0x013d: mmctx_xfer */ +- 0xf094bd00, +- 0x00800199, +- 0x09f60237, +- 0xbd04bd00, +- 0x05bbfd94, +- 0x800f0bf4, +- 0xf601c400, +- 0x04bd000b, +-/* 0x015f: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0xc6008018, +- 0x000ef601, +- 0x008004bd, +- 0x0ff601c7, +- 0xf004bd00, +-/* 0x017a: mmctx_multi_disabled */ +- 0xabc80199, +- 0x10b4b600, +- 0xc80cb9f0, +- 0xe4b601ae, +- 0x05befd11, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x0195: mmctx_exec_loop */ +-/* 0x0195: mmctx_wait_free */ +- 0xc5008e04, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f60b, +- 0x05e9fd00, +- 0x01c80080, +- 0xbd000ef6, +- 0x04c0b604, +- 0x1bf4cda4, +- 0x02abc8df, +-/* 0x01bf: mmctx_fini_wait */ +- 0x8b1c1bf4, +- 0xcf01c500, +- 0xb4f000bb, +- 0x10b4b01f, +- 0x0af31bf4, +- 0x00b87e05, +- 0x250ef400, +-/* 0x01d8: mmctx_stop */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x12b9f00c, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x01ed: mmctx_stop_wait */ +- 0xc5008b04, +- 0x00bbcf01, +- 0xf412bbc8, +-/* 0x01fa: mmctx_done */ +- 0x94bdf61b, +- 0x800199f0, +- 0xf6021700, +- 0x04bd0009, +-/* 0x020a: strand_wait */ +- 0xa0f900f8, +- 0xb87e020a, +- 0xa0fc0000, +-/* 0x0216: strand_pre */ +- 0x0c0900f8, +- 0x024afc80, +- 0xbd0009f6, +- 0x020a7e04, +-/* 0x0227: strand_post */ +- 0x0900f800, +- 0x4afc800d, +- 0x0009f602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0238: strand_set */ +- 0xfc800f0c, +- 0x0cf6024f, +- 0x0c04bd00, +- 0x4afc800b, +- 0x000cf602, +- 0xfc8004bd, +- 0x0ef6024f, +- 0x0c04bd00, +- 0x4afc800a, +- 0x000cf602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0268: strand_ctx_init */ +- 0x99f094bd, +- 0x37008003, +- 0x0009f602, +- 0x167e04bd, +- 0x030e0002, +- 0x0002387e, +- 0xfc80c4bd, +- 0x0cf60247, +- 0x0c04bd00, +- 0x4afc8001, +- 0x000cf602, +- 0x0a7e04bd, +- 0x0c920002, +- 0x46fc8001, +- 0x000cf602, +- 0x020c04bd, +- 0x024afc80, +- 0xbd000cf6, +- 0x020a7e04, +- 0x02277e00, +- 0x42008800, +- 0x20008902, +- 0x0099cf02, +-/* 0x02c7: ctx_init_strand_loop */ +- 0xf608fe95, +- 0x8ef6008e, +- 0x808acf40, +- 0xb606a5b6, +- 0xeabb01a0, +- 0x0480b600, +- 0xf40192b6, +- 0xe4b6e81b, +- 0xf2efbc08, +- 0x99f094bd, +- 0x17008003, +- 0x0009f602, +- 0x00f804bd, +-/* 0x02f8: error */ +- 0xffb2e0f9, +- 0x4098148e, +- 0x00008f7e, +- 0xffb2010f, +- 0x409c1c8e, +- 0x00008f7e, +- 0x00f8e0fc, +-/* 0x0314: init */ +- 0x004104bd, +- 0x0011cf42, +- 0x010911e7, +- 0xfe0814b6, +- 0x02020014, +- 0xf6120040, +- 0x04bd0002, +- 0xfe047241, +- 0x00400010, +- 0x0000f607, +- 0x040204bd, +- 0xf6040040, +- 0x04bd0002, +- 0x821031f4, +- 0xcf018200, +- 0x01030022, +- 0xbb1f24f0, +- 0x32b60432, +- 0x0502b501, +- 0x820603b5, +- 0xcf018600, +- 0x02b50022, +- 0x0c308e04, +- 0xbd24bd50, +-/* 0x0377: init_unk_loop */ +- 0x7e44bd34, +- 0xb0000065, +- 0x0bf400f6, +- 0xbb010f0e, +- 0x4ffd04f2, +- 0x0130b605, +-/* 0x038c: init_unk_next */ +- 0xb60120b6, +- 0x26b004e0, +- 0xe21bf402, +-/* 0x0398: init_unk_done */ +- 0xb50703b5, +- 0x00820804, +- 0x22cf0201, +- 0x9534bd00, +- 0x00800825, +- 0x05f601c0, +- 0x8004bd00, +- 0xf601c100, +- 0x04bd0005, +- 0x98000e98, +- 0x207e010f, +- 0x2fbb0001, +- 0x003fbb00, +- 0x98010e98, +- 0x207e020f, +- 0x0e980001, +- 0x00effd05, +- 0xbb002ebb, +- 0x0e98003e, +- 0x030f9802, +- 0x0001207e, +- 0xfd070e98, +- 0x2ebb00ef, +- 0x003ebb00, +- 0x800235b6, +- 0xf601d300, +- 0x04bd0003, +- 0xb60825b6, +- 0x20b60635, +- 0x0130b601, +- 0xb60824b6, +- 0x2fb20834, +- 0x0002687e, +- 0x80003fbb, +- 0xf6020100, +- 0x04bd0003, +- 0x29f024bd, +- 0x3000801f, +- 0x0002f602, +-/* 0x0436: main */ +- 0x31f404bd, +- 0x0028f400, +- 0x377e240d, +- 0x01f40000, +- 0x04e4b0f4, +- 0xfe1d18f4, +- 0x06020181, +- 0x12fd20bd, +- 0x01e4b604, +- 0xfe051efd, +- 0x097e0018, +- 0x0ef40005, +-/* 0x0465: main_not_ctx_xfer */ +- 0x10ef94d4, +- 0x7e01f5f0, +- 0xf40002f8, +-/* 0x0472: ih */ +- 0x80f9c70e, +- 0xf90188fe, +- 0xf990f980, +- 0xf9b0f9a0, +- 0xf9e0f9d0, +- 0x4a04bdf0, +- 0xaacf0200, +- 0x04abc400, +- 0x0d1f0bf4, +- 0x1a004e24, +- 0x4f00eecf, +- 0xffcf1900, +- 0x00047e00, +- 0x40010e00, +- 0x0ef61d00, +-/* 0x04af: ih_no_fifo */ +- 0x4004bd00, +- 0x0af60100, +- 0xfc04bd00, +- 0xfce0fcf0, +- 0xfcb0fcd0, +- 0xfc90fca0, +- 0x0088fe80, +- 0x32f480fc, +-/* 0x04cf: hub_barrier_done */ +- 0x0f01f800, +- 0x040e9801, +- 0xb204febb, +- 0x94188eff, +- 0x008f7e40, +-/* 0x04e3: ctx_redswitch */ +- 0x0f00f800, +- 0x85008020, +- 0x000ff601, +- 0x080e04bd, +-/* 0x04f0: ctx_redswitch_delay */ +- 0xf401e2b6, +- 0xf5f1fd1b, +- 0xf5f10800, +- 0x00800200, +- 0x0ff60185, +- 0xf804bd00, +-/* 0x0509: ctx_xfer */ +- 0x81008000, +- 0x000ff602, +- 0x11f404bd, +- 0x04e37e07, +-/* 0x0519: ctx_xfer_not_load */ +- 0x02167e00, +- 0x8024bd00, +- 0xf60247fc, +- 0x04bd0002, +- 0xb6012cf0, +- 0xfc800320, +- 0x02f6024a, +- 0xf004bd00, +- 0xa5f001ac, +- 0x00008b02, +- 0x040c9850, +- 0xbb0fc4b6, +- 0x0c9800bc, +- 0x010d9800, +- 0x3d7e000e, +- 0xacf00001, +- 0x40008b01, +- 0x040c9850, +- 0xbb0fc4b6, +- 0x0c9800bc, +- 0x020d9801, +- 0x4e060f98, +- 0x3d7e0800, +- 0xacf00001, +- 0x04a5f001, +- 0x5030008b, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x020c9800, +- 0x98030d98, +- 0x004e080f, +- 0x013d7e02, +- 0x020a7e00, +- 0x0601f400, +-/* 0x05a3: ctx_xfer_post */ +- 0x7e0712f4, +-/* 0x05a7: ctx_xfer_done */ +- 0x7e000227, +- 0xf80004cf, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 +deleted file mode 100644 +index bd30262d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5 ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 +- +-#define CHIPSET GK208 +-#include "macros.fuc" +- +-.section #nv108_grgpc_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "gpc.fuc" +-#undef INCLUDE_DATA +- +-.section #nv108_grgpc_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "gpc.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h +deleted file mode 100644 +index 31922707..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnv108.fuc5.h ++++ /dev/null +@@ -1,473 +0,0 @@ +-uint32_t nv108_grgpc_data[] = { +-/* 0x0000: gpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0004: gpc_mmio_list_tail */ +-/* 0x0004: tpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0008: tpc_mmio_list_tail */ +-/* 0x0008: unk_mmio_list_head */ +- 0x0000006c, +-/* 0x000c: unk_mmio_list_tail */ +- 0x0000006c, +-/* 0x0010: gpc_id */ +- 0x00000000, +-/* 0x0014: tpc_count */ +- 0x00000000, +-/* 0x0018: tpc_mask */ +- 0x00000000, +-/* 0x001c: unk_count */ +- 0x00000000, +-/* 0x0020: unk_mask */ +- 0x00000000, +-/* 0x0024: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nv108_grgpc_code[] = { +- 0x03140ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0xf489a408, +- 0x020f0b1b, +- 0x0002f87e, +-/* 0x001a: queue_put_next */ +- 0x98c400f8, +- 0x0384b607, +- 0xb6008dbb, +- 0x8eb50880, +- 0x018fb500, +- 0xf00190b6, +- 0xd9b50f94, +-/* 0x0037: queue_get */ +- 0xf400f801, +- 0xd8980131, +- 0x01d99800, +- 0x0bf489a4, +- 0x0789c421, +- 0xbb0394b6, +- 0x90b6009d, +- 0x009e9808, +- 0xb6019f98, +- 0x84f00180, +- 0x00d8b50f, +-/* 0x0063: queue_get_done */ +- 0xf80132f4, +-/* 0x0065: nv_rd32 */ +- 0xf0ecb200, +- 0x00801fc9, +- 0x0cf601ca, +-/* 0x0073: nv_rd32_wait */ +- 0x8c04bd00, +- 0xcf01ca00, +- 0xccc800cc, +- 0xf61bf41f, +- 0xec7e060a, +- 0x008f0000, +- 0xffcf01cb, +-/* 0x008f: nv_wr32 */ +- 0x8000f800, +- 0xf601cc00, +- 0x04bd000f, +- 0xc9f0ecb2, +- 0x1ec9f01f, +- 0x01ca0080, +- 0xbd000cf6, +-/* 0x00a9: nv_wr32_wait */ +- 0xca008c04, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f61b, +-/* 0x00b8: wait_donez */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x00cf: wait_donez_ne */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf61bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x00ec: wait_doneo */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x0103: wait_doneo_e */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf60bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x0120: mmctx_size */ +-/* 0x0122: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0x1bf4efa4, +- 0xf89fb2ec, +-/* 0x013d: mmctx_xfer */ +- 0xf094bd00, +- 0x00800199, +- 0x09f60237, +- 0xbd04bd00, +- 0x05bbfd94, +- 0x800f0bf4, +- 0xf601c400, +- 0x04bd000b, +-/* 0x015f: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0xc6008018, +- 0x000ef601, +- 0x008004bd, +- 0x0ff601c7, +- 0xf004bd00, +-/* 0x017a: mmctx_multi_disabled */ +- 0xabc80199, +- 0x10b4b600, +- 0xc80cb9f0, +- 0xe4b601ae, +- 0x05befd11, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x0195: mmctx_exec_loop */ +-/* 0x0195: mmctx_wait_free */ +- 0xc5008e04, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f60b, +- 0x05e9fd00, +- 0x01c80080, +- 0xbd000ef6, +- 0x04c0b604, +- 0x1bf4cda4, +- 0x02abc8df, +-/* 0x01bf: mmctx_fini_wait */ +- 0x8b1c1bf4, +- 0xcf01c500, +- 0xb4f000bb, +- 0x10b4b01f, +- 0x0af31bf4, +- 0x00b87e05, +- 0x250ef400, +-/* 0x01d8: mmctx_stop */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x12b9f00c, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x01ed: mmctx_stop_wait */ +- 0xc5008b04, +- 0x00bbcf01, +- 0xf412bbc8, +-/* 0x01fa: mmctx_done */ +- 0x94bdf61b, +- 0x800199f0, +- 0xf6021700, +- 0x04bd0009, +-/* 0x020a: strand_wait */ +- 0xa0f900f8, +- 0xb87e020a, +- 0xa0fc0000, +-/* 0x0216: strand_pre */ +- 0x0c0900f8, +- 0x024afc80, +- 0xbd0009f6, +- 0x020a7e04, +-/* 0x0227: strand_post */ +- 0x0900f800, +- 0x4afc800d, +- 0x0009f602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0238: strand_set */ +- 0xfc800f0c, +- 0x0cf6024f, +- 0x0c04bd00, +- 0x4afc800b, +- 0x000cf602, +- 0xfc8004bd, +- 0x0ef6024f, +- 0x0c04bd00, +- 0x4afc800a, +- 0x000cf602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0268: strand_ctx_init */ +- 0x99f094bd, +- 0x37008003, +- 0x0009f602, +- 0x167e04bd, +- 0x030e0002, +- 0x0002387e, +- 0xfc80c4bd, +- 0x0cf60247, +- 0x0c04bd00, +- 0x4afc8001, +- 0x000cf602, +- 0x0a7e04bd, +- 0x0c920002, +- 0x46fc8001, +- 0x000cf602, +- 0x020c04bd, +- 0x024afc80, +- 0xbd000cf6, +- 0x020a7e04, +- 0x02277e00, +- 0x42008800, +- 0x20008902, +- 0x0099cf02, +-/* 0x02c7: ctx_init_strand_loop */ +- 0xf608fe95, +- 0x8ef6008e, +- 0x808acf40, +- 0xb606a5b6, +- 0xeabb01a0, +- 0x0480b600, +- 0xf40192b6, +- 0xe4b6e81b, +- 0xf2efbc08, +- 0x99f094bd, +- 0x17008003, +- 0x0009f602, +- 0x00f804bd, +-/* 0x02f8: error */ +- 0xffb2e0f9, +- 0x4098148e, +- 0x00008f7e, +- 0xffb2010f, +- 0x409c1c8e, +- 0x00008f7e, +- 0x00f8e0fc, +-/* 0x0314: init */ +- 0x004104bd, +- 0x0011cf42, +- 0x010911e7, +- 0xfe0814b6, +- 0x02020014, +- 0xf6120040, +- 0x04bd0002, +- 0xfe047241, +- 0x00400010, +- 0x0000f607, +- 0x040204bd, +- 0xf6040040, +- 0x04bd0002, +- 0x821031f4, +- 0xcf018200, +- 0x01030022, +- 0xbb1f24f0, +- 0x32b60432, +- 0x0502b501, +- 0x820603b5, +- 0xcf018600, +- 0x02b50022, +- 0x0c308e04, +- 0xbd24bd50, +-/* 0x0377: init_unk_loop */ +- 0x7e44bd34, +- 0xb0000065, +- 0x0bf400f6, +- 0xbb010f0e, +- 0x4ffd04f2, +- 0x0130b605, +-/* 0x038c: init_unk_next */ +- 0xb60120b6, +- 0x26b004e0, +- 0xe21bf401, +-/* 0x0398: init_unk_done */ +- 0xb50703b5, +- 0x00820804, +- 0x22cf0201, +- 0x9534bd00, +- 0x00800825, +- 0x05f601c0, +- 0x8004bd00, +- 0xf601c100, +- 0x04bd0005, +- 0x98000e98, +- 0x207e010f, +- 0x2fbb0001, +- 0x003fbb00, +- 0x98010e98, +- 0x207e020f, +- 0x0e980001, +- 0x00effd05, +- 0xbb002ebb, +- 0x0e98003e, +- 0x030f9802, +- 0x0001207e, +- 0xfd070e98, +- 0x2ebb00ef, +- 0x003ebb00, +- 0x800235b6, +- 0xf601d300, +- 0x04bd0003, +- 0xb60825b6, +- 0x20b60635, +- 0x0130b601, +- 0xb60824b6, +- 0x2fb20834, +- 0x0002687e, +- 0x80003fbb, +- 0xf6020100, +- 0x04bd0003, +- 0x29f024bd, +- 0x3000801f, +- 0x0002f602, +-/* 0x0436: main */ +- 0x31f404bd, +- 0x0028f400, +- 0x377e240d, +- 0x01f40000, +- 0x04e4b0f4, +- 0xfe1d18f4, +- 0x06020181, +- 0x12fd20bd, +- 0x01e4b604, +- 0xfe051efd, +- 0x097e0018, +- 0x0ef40005, +-/* 0x0465: main_not_ctx_xfer */ +- 0x10ef94d4, +- 0x7e01f5f0, +- 0xf40002f8, +-/* 0x0472: ih */ +- 0x80f9c70e, +- 0xf90188fe, +- 0xf990f980, +- 0xf9b0f9a0, +- 0xf9e0f9d0, +- 0x4a04bdf0, +- 0xaacf0200, +- 0x04abc400, +- 0x0d1f0bf4, +- 0x1a004e24, +- 0x4f00eecf, +- 0xffcf1900, +- 0x00047e00, +- 0x40010e00, +- 0x0ef61d00, +-/* 0x04af: ih_no_fifo */ +- 0x4004bd00, +- 0x0af60100, +- 0xfc04bd00, +- 0xfce0fcf0, +- 0xfcb0fcd0, +- 0xfc90fca0, +- 0x0088fe80, +- 0x32f480fc, +-/* 0x04cf: hub_barrier_done */ +- 0x0f01f800, +- 0x040e9801, +- 0xb204febb, +- 0x94188eff, +- 0x008f7e40, +-/* 0x04e3: ctx_redswitch */ +- 0x0f00f800, +- 0x85008020, +- 0x000ff601, +- 0x080e04bd, +-/* 0x04f0: ctx_redswitch_delay */ +- 0xf401e2b6, +- 0xf5f1fd1b, +- 0xf5f10800, +- 0x00800200, +- 0x0ff60185, +- 0xf804bd00, +-/* 0x0509: ctx_xfer */ +- 0x81008000, +- 0x000ff602, +- 0x11f404bd, +- 0x04e37e07, +-/* 0x0519: ctx_xfer_not_load */ +- 0x02167e00, +- 0x8024bd00, +- 0xf60247fc, +- 0x04bd0002, +- 0xb6012cf0, +- 0xfc800320, +- 0x02f6024a, +- 0xf004bd00, +- 0xa5f001ac, +- 0x00008b02, +- 0x040c9850, +- 0xbb0fc4b6, +- 0x0c9800bc, +- 0x010d9800, +- 0x3d7e000e, +- 0xacf00001, +- 0x40008b01, +- 0x040c9850, +- 0xbb0fc4b6, +- 0x0c9800bc, +- 0x020d9801, +- 0x4e060f98, +- 0x3d7e0800, +- 0xacf00001, +- 0x04a5f001, +- 0x5030008b, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x020c9800, +- 0x98030d98, +- 0x004e080f, +- 0x013d7e02, +- 0x020a7e00, +- 0x0601f400, +-/* 0x05a3: ctx_xfer_post */ +- 0x7e0712f4, +-/* 0x05a7: ctx_xfer_done */ +- 0x7e000227, +- 0xf80004cf, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc +deleted file mode 100644 +index 5ae06a2d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000000 +- +-#define CHIPSET GF100 +-#include "macros.fuc" +- +-.section #nvc0_grgpc_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "gpc.fuc" +-#undef INCLUDE_DATA +- +-.section #nvc0_grgpc_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "gpc.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h +deleted file mode 100644 +index 325cc7b7..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h ++++ /dev/null +@@ -1,530 +0,0 @@ +-uint32_t nvc0_grgpc_data[] = { +-/* 0x0000: gpc_mmio_list_head */ +- 0x00000064, +-/* 0x0004: gpc_mmio_list_tail */ +-/* 0x0004: tpc_mmio_list_head */ +- 0x00000064, +-/* 0x0008: tpc_mmio_list_tail */ +-/* 0x0008: unk_mmio_list_head */ +- 0x00000064, +-/* 0x000c: unk_mmio_list_tail */ +- 0x00000064, +-/* 0x0010: gpc_id */ +- 0x00000000, +-/* 0x0014: tpc_count */ +- 0x00000000, +-/* 0x0018: tpc_mask */ +- 0x00000000, +-/* 0x001c: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nvc0_grgpc_code[] = { +- 0x03a10ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0xe0f900f8, +- 0xf102ffb9, +- 0xf09814e7, +- 0x21f440e3, +- 0x01f7f09d, +- 0xf102ffb9, +- 0xf09c1ce7, +- 0x21f440e3, +- 0xf8e0fc9d, +-/* 0x03a1: init */ +- 0xf104bd00, +- 0xf0420017, +- 0x11cf0013, +- 0x0911e700, +- 0x0814b601, +- 0xf00014fe, +- 0x07f10227, +- 0x03f01200, +- 0x0002d000, +- 0x17f104bd, +- 0x10fe04e6, +- 0x0007f100, +- 0x0003f007, +- 0xbd0000d0, +- 0x0427f004, +- 0x040007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0xf11031f4, +- 0xf0820027, +- 0x22cf0123, +- 0x0137f000, +- 0xbb1f24f0, +- 0x32b60432, +- 0x05028001, +- 0xf1060380, +- 0xf0860027, +- 0x22cf0123, +- 0x04028000, +- 0x010027f1, +- 0xcf0223f0, +- 0x34bd0022, +- 0xf1082595, +- 0xf0c00007, +- 0x05d00103, +- 0xf104bd00, +- 0xf0c10007, +- 0x05d00103, +- 0x9804bd00, +- 0x0f98000e, +- 0x5021f501, +- 0x002fbb01, +- 0x98003fbb, +- 0x0f98010e, +- 0x5021f502, +- 0x050e9801, +- 0xbb00effd, +- 0x3ebb002e, +- 0x0235b600, +- 0xd30007f1, +- 0xd00103f0, +- 0x04bd0003, +- 0xb60825b6, +- 0x20b60635, +- 0x0130b601, +- 0xb60824b6, +- 0x2fb90834, +- 0xd321f502, +- 0x003fbb02, +- 0x010007f1, +- 0xd00203f0, +- 0x04bd0003, +- 0x29f024bd, +- 0x0007f11f, +- 0x0203f008, +- 0xbd0002d0, +-/* 0x04a9: main */ +- 0x0031f404, +- 0xf00028f4, +- 0x21f41cd7, +- 0xf401f439, +- 0xf404e4b0, +- 0x81fe1e18, +- 0x0627f001, +- 0x12fd20bd, +- 0x01e4b604, +- 0xfe051efd, +- 0x21f50018, +- 0x0ef4059e, +-/* 0x04d9: main_not_ctx_xfer */ +- 0x10ef94d3, +- 0xf501f5f0, +- 0xf4037e21, +-/* 0x04e6: ih */ +- 0x80f9c60e, +- 0xf90188fe, +- 0xf990f980, +- 0xf9b0f9a0, +- 0xf9e0f9d0, +- 0xf104bdf0, +- 0xf00200a7, +- 0xaacf00a3, +- 0x04abc400, +- 0xf02c0bf4, +- 0xe7f11cd7, +- 0xe3f01a00, +- 0x00eecf00, +- 0x1900f7f1, +- 0xcf00f3f0, +- 0x21f400ff, +- 0x01e7f004, +- 0x1d0007f1, +- 0xd00003f0, +- 0x04bd000e, +-/* 0x0534: ih_no_fifo */ +- 0x010007f1, +- 0xd00003f0, +- 0x04bd000a, +- 0xe0fcf0fc, +- 0xb0fcd0fc, +- 0x90fca0fc, +- 0x88fe80fc, +- 0xf480fc00, +- 0x01f80032, +-/* 0x0558: hub_barrier_done */ +- 0x9801f7f0, +- 0xfebb040e, +- 0x02ffb904, +- 0x9418e7f1, +- 0xf440e3f0, +- 0x00f89d21, +-/* 0x0570: ctx_redswitch */ +- 0xf120f7f0, +- 0xf0850007, +- 0x0fd00103, +- 0xf004bd00, +-/* 0x0582: ctx_redswitch_delay */ +- 0xe2b608e7, +- 0xfd1bf401, +- 0x0800f5f1, +- 0x0200f5f1, +- 0x850007f1, +- 0xd00103f0, +- 0x04bd000f, +-/* 0x059e: ctx_xfer */ +- 0x07f100f8, +- 0x03f08100, +- 0x000fd002, +- 0x11f404bd, +- 0x7021f507, +-/* 0x05b1: ctx_xfer_not_load */ +- 0x6a21f505, +- 0xf124bd02, +- 0xf047fc07, +- 0x02d00203, +- 0xf004bd00, +- 0x20b6012c, +- 0xfc07f103, +- 0x0203f04a, +- 0xbd0002d0, +- 0x01acf004, +- 0xf102a5f0, +- 0xf00000b7, +- 0x0c9850b3, +- 0x0fc4b604, +- 0x9800bcbb, +- 0x0d98000c, +- 0x00e7f001, +- 0x016f21f5, +- 0xf001acf0, +- 0xb7f104a5, +- 0xb3f04000, +- 0x040c9850, +- 0xbb0fc4b6, +- 0x0c9800bc, +- 0x020d9801, +- 0xf1060f98, +- 0xf50800e7, +- 0xf5016f21, +- 0xf4025e21, +- 0x12f40601, +-/* 0x0629: ctx_xfer_post */ +- 0x7f21f507, +-/* 0x062d: ctx_xfer_done */ +- 0x5821f502, +- 0x0000f805, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc +deleted file mode 100644 +index c2f754ed..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 +- +-#define CHIPSET GF117 +-#include "macros.fuc" +- +-.section #nvd7_grgpc_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "gpc.fuc" +-#undef INCLUDE_DATA +- +-.section #nvd7_grgpc_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "gpc.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h +deleted file mode 100644 +index d1504a40..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvd7.fuc.h ++++ /dev/null +@@ -1,537 +0,0 @@ +-uint32_t nvd7_grgpc_data[] = { +-/* 0x0000: gpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0004: gpc_mmio_list_tail */ +-/* 0x0004: tpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0008: tpc_mmio_list_tail */ +-/* 0x0008: unk_mmio_list_head */ +- 0x0000006c, +-/* 0x000c: unk_mmio_list_tail */ +- 0x0000006c, +-/* 0x0010: gpc_id */ +- 0x00000000, +-/* 0x0014: tpc_count */ +- 0x00000000, +-/* 0x0018: tpc_mask */ +- 0x00000000, +-/* 0x001c: unk_count */ +- 0x00000000, +-/* 0x0020: unk_mask */ +- 0x00000000, +-/* 0x0024: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nvd7_grgpc_code[] = { +- 0x03a10ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0xe0f900f8, +- 0xf102ffb9, +- 0xf09814e7, +- 0x21f440e3, +- 0x01f7f09d, +- 0xf102ffb9, +- 0xf09c1ce7, +- 0x21f440e3, +- 0xf8e0fc9d, +-/* 0x03a1: init */ +- 0xf104bd00, +- 0xf0420017, +- 0x11cf0013, +- 0x0911e700, +- 0x0814b601, +- 0xf00014fe, +- 0x07f10227, +- 0x03f01200, +- 0x0002d000, +- 0x17f104bd, +- 0x10fe0530, +- 0x0007f100, +- 0x0003f007, +- 0xbd0000d0, +- 0x0427f004, +- 0x040007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0xf11031f4, +- 0xf0820027, +- 0x22cf0123, +- 0x0137f000, +- 0xbb1f24f0, +- 0x32b60432, +- 0x05028001, +- 0xf1060380, +- 0xf0860027, +- 0x22cf0123, +- 0x04028000, +- 0x0c30e7f1, +- 0xbd50e3f0, +- 0xbd34bd24, +-/* 0x0421: init_unk_loop */ +- 0x6821f444, +- 0xf400f6b0, +- 0xf7f00f0b, +- 0x04f2bb01, +- 0xb6054ffd, +-/* 0x0436: init_unk_next */ +- 0x20b60130, +- 0x04e0b601, +- 0xf40126b0, +-/* 0x0442: init_unk_done */ +- 0x0380e21b, +- 0x08048007, +- 0x010027f1, +- 0xcf0223f0, +- 0x34bd0022, +- 0xf1082595, +- 0xf0c00007, +- 0x05d00103, +- 0xf104bd00, +- 0xf0c10007, +- 0x05d00103, +- 0x9804bd00, +- 0x0f98000e, +- 0x5021f501, +- 0x002fbb01, +- 0x98003fbb, +- 0x0f98010e, +- 0x5021f502, +- 0x050e9801, +- 0xbb00effd, +- 0x3ebb002e, +- 0x020e9800, +- 0xf5030f98, +- 0x98015021, +- 0xeffd070e, +- 0x002ebb00, +- 0xb6003ebb, +- 0x07f10235, +- 0x03f0d300, +- 0x0003d001, +- 0x25b604bd, +- 0x0635b608, +- 0xb60120b6, +- 0x24b60130, +- 0x0834b608, +- 0xf5022fb9, +- 0xbb02d321, +- 0x07f1003f, +- 0x03f00100, +- 0x0003d002, +- 0x24bd04bd, +- 0xf11f29f0, +- 0xf0080007, +- 0x02d00203, +-/* 0x04f3: main */ +- 0xf404bd00, +- 0x28f40031, +- 0x24d7f000, +- 0xf43921f4, +- 0xe4b0f401, +- 0x1e18f404, +- 0xf00181fe, +- 0x20bd0627, +- 0xb60412fd, +- 0x1efd01e4, +- 0x0018fe05, +- 0x05e821f5, +-/* 0x0523: main_not_ctx_xfer */ +- 0x94d30ef4, +- 0xf5f010ef, +- 0x7e21f501, +- 0xc60ef403, +-/* 0x0530: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x24d7f02c, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xf00421f4, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x057e: ih_no_fifo */ +- 0x07f104bd, +- 0x03f00100, +- 0x000ad000, +- 0xf0fc04bd, +- 0xd0fce0fc, +- 0xa0fcb0fc, +- 0x80fc90fc, +- 0xfc0088fe, +- 0x0032f480, +-/* 0x05a2: hub_barrier_done */ +- 0xf7f001f8, +- 0x040e9801, +- 0xb904febb, +- 0xe7f102ff, +- 0xe3f09418, +- 0x9d21f440, +-/* 0x05ba: ctx_redswitch */ +- 0xf7f000f8, +- 0x0007f120, +- 0x0103f085, +- 0xbd000fd0, +- 0x08e7f004, +-/* 0x05cc: ctx_redswitch_delay */ +- 0xf401e2b6, +- 0xf5f1fd1b, +- 0xf5f10800, +- 0x07f10200, +- 0x03f08500, +- 0x000fd001, +- 0x00f804bd, +-/* 0x05e8: ctx_xfer */ +- 0x810007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0xf50711f4, +-/* 0x05fb: ctx_xfer_not_load */ +- 0xf505ba21, +- 0xbd026a21, +- 0xfc07f124, +- 0x0203f047, +- 0xbd0002d0, +- 0x012cf004, +- 0xf10320b6, +- 0xf04afc07, +- 0x02d00203, +- 0xf004bd00, +- 0xa5f001ac, +- 0x00b7f102, +- 0x50b3f000, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x000c9800, +- 0xf0010d98, +- 0x21f500e7, +- 0xacf0016f, +- 0x00b7f101, +- 0x50b3f040, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x010c9800, +- 0x98020d98, +- 0xe7f1060f, +- 0x21f50800, +- 0xacf0016f, +- 0x04a5f001, +- 0x3000b7f1, +- 0x9850b3f0, +- 0xc4b6040c, +- 0x00bcbb0f, +- 0x98020c98, +- 0x0f98030d, +- 0x00e7f108, +- 0x6f21f502, +- 0x5e21f501, +- 0x0601f402, +-/* 0x0697: ctx_xfer_post */ +- 0xf50712f4, +-/* 0x069b: ctx_xfer_done */ +- 0xf5027f21, +- 0xf805a221, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc +deleted file mode 100644 +index 6b906cd2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000001 +- +-#define CHIPSET GK100 +-#include "macros.fuc" +- +-.section #nve0_grgpc_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "gpc.fuc" +-#undef INCLUDE_DATA +- +-.section #nve0_grgpc_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "gpc.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h +deleted file mode 100644 +index 855b2203..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnve0.fuc.h ++++ /dev/null +@@ -1,537 +0,0 @@ +-uint32_t nve0_grgpc_data[] = { +-/* 0x0000: gpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0004: gpc_mmio_list_tail */ +-/* 0x0004: tpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0008: tpc_mmio_list_tail */ +-/* 0x0008: unk_mmio_list_head */ +- 0x0000006c, +-/* 0x000c: unk_mmio_list_tail */ +- 0x0000006c, +-/* 0x0010: gpc_id */ +- 0x00000000, +-/* 0x0014: tpc_count */ +- 0x00000000, +-/* 0x0018: tpc_mask */ +- 0x00000000, +-/* 0x001c: unk_count */ +- 0x00000000, +-/* 0x0020: unk_mask */ +- 0x00000000, +-/* 0x0024: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nve0_grgpc_code[] = { +- 0x03a10ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0xe0f900f8, +- 0xf102ffb9, +- 0xf09814e7, +- 0x21f440e3, +- 0x01f7f09d, +- 0xf102ffb9, +- 0xf09c1ce7, +- 0x21f440e3, +- 0xf8e0fc9d, +-/* 0x03a1: init */ +- 0xf104bd00, +- 0xf0420017, +- 0x11cf0013, +- 0x0911e700, +- 0x0814b601, +- 0xf00014fe, +- 0x07f10227, +- 0x03f01200, +- 0x0002d000, +- 0x17f104bd, +- 0x10fe0530, +- 0x0007f100, +- 0x0003f007, +- 0xbd0000d0, +- 0x0427f004, +- 0x040007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0xf11031f4, +- 0xf0820027, +- 0x22cf0123, +- 0x0137f000, +- 0xbb1f24f0, +- 0x32b60432, +- 0x05028001, +- 0xf1060380, +- 0xf0860027, +- 0x22cf0123, +- 0x04028000, +- 0x0c30e7f1, +- 0xbd50e3f0, +- 0xbd34bd24, +-/* 0x0421: init_unk_loop */ +- 0x6821f444, +- 0xf400f6b0, +- 0xf7f00f0b, +- 0x04f2bb01, +- 0xb6054ffd, +-/* 0x0436: init_unk_next */ +- 0x20b60130, +- 0x04e0b601, +- 0xf40126b0, +-/* 0x0442: init_unk_done */ +- 0x0380e21b, +- 0x08048007, +- 0x010027f1, +- 0xcf0223f0, +- 0x34bd0022, +- 0xf1082595, +- 0xf0c00007, +- 0x05d00103, +- 0xf104bd00, +- 0xf0c10007, +- 0x05d00103, +- 0x9804bd00, +- 0x0f98000e, +- 0x5021f501, +- 0x002fbb01, +- 0x98003fbb, +- 0x0f98010e, +- 0x5021f502, +- 0x050e9801, +- 0xbb00effd, +- 0x3ebb002e, +- 0x020e9800, +- 0xf5030f98, +- 0x98015021, +- 0xeffd070e, +- 0x002ebb00, +- 0xb6003ebb, +- 0x07f10235, +- 0x03f0d300, +- 0x0003d001, +- 0x25b604bd, +- 0x0635b608, +- 0xb60120b6, +- 0x24b60130, +- 0x0834b608, +- 0xf5022fb9, +- 0xbb02d321, +- 0x07f1003f, +- 0x03f00100, +- 0x0003d002, +- 0x24bd04bd, +- 0xf11f29f0, +- 0xf0080007, +- 0x02d00203, +-/* 0x04f3: main */ +- 0xf404bd00, +- 0x28f40031, +- 0x24d7f000, +- 0xf43921f4, +- 0xe4b0f401, +- 0x1e18f404, +- 0xf00181fe, +- 0x20bd0627, +- 0xb60412fd, +- 0x1efd01e4, +- 0x0018fe05, +- 0x05e821f5, +-/* 0x0523: main_not_ctx_xfer */ +- 0x94d30ef4, +- 0xf5f010ef, +- 0x7e21f501, +- 0xc60ef403, +-/* 0x0530: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x24d7f02c, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xf00421f4, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x057e: ih_no_fifo */ +- 0x07f104bd, +- 0x03f00100, +- 0x000ad000, +- 0xf0fc04bd, +- 0xd0fce0fc, +- 0xa0fcb0fc, +- 0x80fc90fc, +- 0xfc0088fe, +- 0x0032f480, +-/* 0x05a2: hub_barrier_done */ +- 0xf7f001f8, +- 0x040e9801, +- 0xb904febb, +- 0xe7f102ff, +- 0xe3f09418, +- 0x9d21f440, +-/* 0x05ba: ctx_redswitch */ +- 0xf7f000f8, +- 0x0007f120, +- 0x0103f085, +- 0xbd000fd0, +- 0x08e7f004, +-/* 0x05cc: ctx_redswitch_delay */ +- 0xf401e2b6, +- 0xf5f1fd1b, +- 0xf5f10800, +- 0x07f10200, +- 0x03f08500, +- 0x000fd001, +- 0x00f804bd, +-/* 0x05e8: ctx_xfer */ +- 0x810007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0xf50711f4, +-/* 0x05fb: ctx_xfer_not_load */ +- 0xf505ba21, +- 0xbd026a21, +- 0xfc07f124, +- 0x0203f047, +- 0xbd0002d0, +- 0x012cf004, +- 0xf10320b6, +- 0xf04afc07, +- 0x02d00203, +- 0xf004bd00, +- 0xa5f001ac, +- 0x00b7f102, +- 0x50b3f000, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x000c9800, +- 0xf0010d98, +- 0x21f500e7, +- 0xacf0016f, +- 0x00b7f101, +- 0x50b3f040, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x010c9800, +- 0x98020d98, +- 0xe7f1060f, +- 0x21f50800, +- 0xacf0016f, +- 0x04a5f001, +- 0x3000b7f1, +- 0x9850b3f0, +- 0xc4b6040c, +- 0x00bcbb0f, +- 0x98020c98, +- 0x0f98030d, +- 0x00e7f108, +- 0x6f21f502, +- 0x5e21f501, +- 0x0601f402, +-/* 0x0697: ctx_xfer_post */ +- 0xf50712f4, +-/* 0x069b: ctx_xfer_done */ +- 0xf5027f21, +- 0xf805a221, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc +deleted file mode 100644 +index 90bbe525..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc ++++ /dev/null +@@ -1,42 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NV_PGRAPH_GPCX_UNK__SIZE 0x00000002 +- +-#define CHIPSET GK110 +-#include "macros.fuc" +- +-.section #nvf0_grgpc_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "gpc.fuc" +-#undef INCLUDE_DATA +- +-.section #nvf0_grgpc_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "gpc.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h +deleted file mode 100644 +index 1b803197..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvf0.fuc.h ++++ /dev/null +@@ -1,537 +0,0 @@ +-uint32_t nvf0_grgpc_data[] = { +-/* 0x0000: gpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0004: gpc_mmio_list_tail */ +-/* 0x0004: tpc_mmio_list_head */ +- 0x0000006c, +-/* 0x0008: tpc_mmio_list_tail */ +-/* 0x0008: unk_mmio_list_head */ +- 0x0000006c, +-/* 0x000c: unk_mmio_list_tail */ +- 0x0000006c, +-/* 0x0010: gpc_id */ +- 0x00000000, +-/* 0x0014: tpc_count */ +- 0x00000000, +-/* 0x0018: tpc_mask */ +- 0x00000000, +-/* 0x001c: unk_count */ +- 0x00000000, +-/* 0x0020: unk_mask */ +- 0x00000000, +-/* 0x0024: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nvf0_grgpc_code[] = { +- 0x03a10ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f037, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f037, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x370007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x370007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0xe0f900f8, +- 0xf102ffb9, +- 0xf09814e7, +- 0x21f440e3, +- 0x01f7f09d, +- 0xf102ffb9, +- 0xf09c1ce7, +- 0x21f440e3, +- 0xf8e0fc9d, +-/* 0x03a1: init */ +- 0xf104bd00, +- 0xf0420017, +- 0x11cf0013, +- 0x0911e700, +- 0x0814b601, +- 0xf00014fe, +- 0x07f10227, +- 0x03f01200, +- 0x0002d000, +- 0x17f104bd, +- 0x10fe0530, +- 0x0007f100, +- 0x0003f007, +- 0xbd0000d0, +- 0x0427f004, +- 0x040007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0xf11031f4, +- 0xf0820027, +- 0x22cf0123, +- 0x0137f000, +- 0xbb1f24f0, +- 0x32b60432, +- 0x05028001, +- 0xf1060380, +- 0xf0860027, +- 0x22cf0123, +- 0x04028000, +- 0x0c30e7f1, +- 0xbd50e3f0, +- 0xbd34bd24, +-/* 0x0421: init_unk_loop */ +- 0x6821f444, +- 0xf400f6b0, +- 0xf7f00f0b, +- 0x04f2bb01, +- 0xb6054ffd, +-/* 0x0436: init_unk_next */ +- 0x20b60130, +- 0x04e0b601, +- 0xf40226b0, +-/* 0x0442: init_unk_done */ +- 0x0380e21b, +- 0x08048007, +- 0x010027f1, +- 0xcf0223f0, +- 0x34bd0022, +- 0xf1082595, +- 0xf0c00007, +- 0x05d00103, +- 0xf104bd00, +- 0xf0c10007, +- 0x05d00103, +- 0x9804bd00, +- 0x0f98000e, +- 0x5021f501, +- 0x002fbb01, +- 0x98003fbb, +- 0x0f98010e, +- 0x5021f502, +- 0x050e9801, +- 0xbb00effd, +- 0x3ebb002e, +- 0x020e9800, +- 0xf5030f98, +- 0x98015021, +- 0xeffd070e, +- 0x002ebb00, +- 0xb6003ebb, +- 0x07f10235, +- 0x03f0d300, +- 0x0003d001, +- 0x25b604bd, +- 0x0635b608, +- 0xb60120b6, +- 0x24b60130, +- 0x0834b608, +- 0xf5022fb9, +- 0xbb02d321, +- 0x07f1003f, +- 0x03f00100, +- 0x0003d002, +- 0x24bd04bd, +- 0xf11f29f0, +- 0xf0300007, +- 0x02d00203, +-/* 0x04f3: main */ +- 0xf404bd00, +- 0x28f40031, +- 0x24d7f000, +- 0xf43921f4, +- 0xe4b0f401, +- 0x1e18f404, +- 0xf00181fe, +- 0x20bd0627, +- 0xb60412fd, +- 0x1efd01e4, +- 0x0018fe05, +- 0x05e821f5, +-/* 0x0523: main_not_ctx_xfer */ +- 0x94d30ef4, +- 0xf5f010ef, +- 0x7e21f501, +- 0xc60ef403, +-/* 0x0530: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x24d7f02c, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xf00421f4, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x057e: ih_no_fifo */ +- 0x07f104bd, +- 0x03f00100, +- 0x000ad000, +- 0xf0fc04bd, +- 0xd0fce0fc, +- 0xa0fcb0fc, +- 0x80fc90fc, +- 0xfc0088fe, +- 0x0032f480, +-/* 0x05a2: hub_barrier_done */ +- 0xf7f001f8, +- 0x040e9801, +- 0xb904febb, +- 0xe7f102ff, +- 0xe3f09418, +- 0x9d21f440, +-/* 0x05ba: ctx_redswitch */ +- 0xf7f000f8, +- 0x0007f120, +- 0x0103f085, +- 0xbd000fd0, +- 0x08e7f004, +-/* 0x05cc: ctx_redswitch_delay */ +- 0xf401e2b6, +- 0xf5f1fd1b, +- 0xf5f10800, +- 0x07f10200, +- 0x03f08500, +- 0x000fd001, +- 0x00f804bd, +-/* 0x05e8: ctx_xfer */ +- 0x810007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0xf50711f4, +-/* 0x05fb: ctx_xfer_not_load */ +- 0xf505ba21, +- 0xbd026a21, +- 0xfc07f124, +- 0x0203f047, +- 0xbd0002d0, +- 0x012cf004, +- 0xf10320b6, +- 0xf04afc07, +- 0x02d00203, +- 0xf004bd00, +- 0xa5f001ac, +- 0x00b7f102, +- 0x50b3f000, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x000c9800, +- 0xf0010d98, +- 0x21f500e7, +- 0xacf0016f, +- 0x00b7f101, +- 0x50b3f040, +- 0xb6040c98, +- 0xbcbb0fc4, +- 0x010c9800, +- 0x98020d98, +- 0xe7f1060f, +- 0x21f50800, +- 0xacf0016f, +- 0x04a5f001, +- 0x3000b7f1, +- 0x9850b3f0, +- 0xc4b6040c, +- 0x00bcbb0f, +- 0x98020c98, +- 0x0f98030d, +- 0x00e7f108, +- 0x6f21f502, +- 0x5e21f501, +- 0x0601f402, +-/* 0x0697: ctx_xfer_post */ +- 0xf50712f4, +-/* 0x069b: ctx_xfer_done */ +- 0xf5027f21, +- 0xf805a221, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc +deleted file mode 100644 +index b4ad18bf..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hub.fuc ++++ /dev/null +@@ -1,696 +0,0 @@ +-/* fuc microcode for nvc0 PGRAPH/HUB +- * +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_DATA +-hub_mmio_list_head: .b32 #hub_mmio_list_base +-hub_mmio_list_tail: .b32 #hub_mmio_list_next +- +-gpc_count: .b32 0 +-rop_count: .b32 0 +-cmd_queue: queue_init +- +-ctx_current: .b32 0 +- +-.align 256 +-chan_data: +-chan_mmio_count: .b32 0 +-chan_mmio_address: .b32 0 +- +-.align 256 +-xfer_data: .skip 256 +- +-hub_mmio_list_base: +-.b32 0x0417e91c // 0x17e91c, 2 +-hub_mmio_list_next: +-#endif +- +-#ifdef INCLUDE_CODE +-// reports an exception to the host +-// +-// In: $r15 error code (see os.h) +-// +-error: +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(5), 0, $r15) +- mov $r15 1 +- nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r15) +- ret +- +-// HUB fuc initialisation, executed by triggering ucode start, will +-// fall through to main loop after completion. +-// +-// Output: +-// CC_SCRATCH[0]: +-// 31:31: set to signal completion +-// CC_SCRATCH[1]: +-// 31:0: total PGRAPH context size +-// +-init: +- clear b32 $r0 +- mov $xdbase $r0 +- +- // setup stack +- nv_iord($r1, NV_PGRAPH_FECS_CAPS, 0) +- extr $r1 $r1 9:17 +- shl b32 $r1 8 +- mov $sp $r1 +- +- // enable fifo access +- mov $r2 NV_PGRAPH_FECS_ACCESS_FIFO +- nv_iowr(NV_PGRAPH_FECS_ACCESS, 0, $r2) +- +- // setup i0 handler, and route all interrupts to it +- mov $r1 #ih +- mov $iv0 $r1 +- +- clear b32 $r2 +- nv_iowr(NV_PGRAPH_FECS_INTR_ROUTE, 0, $r2) +- +- // route HUB_CHSW_PULSE to fuc interrupt 8 +- mov $r2 0x2003 // { HUB_CHSW_PULSE, ZERO } -> intr 8 +- nv_iowr(NV_PGRAPH_FECS_IROUTE, 0, $r2) +- +- // not sure what these are, route them because NVIDIA does, and +- // the IRQ handler will signal the host if we ever get one.. we +- // may find out if/why we need to handle these if so.. +- // +- mov $r2 0x2004 // { 0x04, ZERO } -> intr 9 +- nv_iowr(NV_PGRAPH_FECS_IROUTE, 1, $r2) +- mov $r2 0x200b // { HUB_FIRMWARE_MTHD, ZERO } -> intr 10 +- nv_iowr(NV_PGRAPH_FECS_IROUTE, 2, $r2) +- mov $r2 0x200c // { 0x0c, ZERO } -> intr 15 +- nv_iowr(NV_PGRAPH_FECS_IROUTE, 7, $r2) +- +- // enable all INTR_UP interrupts +- sub b32 $r3 $r0 1 +- nv_iowr(NV_PGRAPH_FECS_INTR_UP_EN, 0, $r3) +- +- // enable fifo, ctxsw, 9, fwmthd, 15 interrupts +- imm32($r2, 0x8704) +- nv_iowr(NV_PGRAPH_FECS_INTR_EN_SET, 0, $r2) +- +- // fifo level triggered, rest edge +- mov $r2 NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL +- nv_iowr(NV_PGRAPH_FECS_INTR_MODE, 0, $r2) +- +- // enable interrupts +- bset $flags ie0 +- +- // fetch enabled GPC/ROP counts +- nv_rd32($r14, 0x409604) +- extr $r1 $r15 16:20 +- st b32 D[$r0 + #rop_count] $r1 +- and $r15 0x1f +- st b32 D[$r0 + #gpc_count] $r15 +- +- // set BAR_REQMASK to GPC mask +- mov $r1 1 +- shl b32 $r1 $r15 +- sub b32 $r1 1 +- nv_iowr(NV_PGRAPH_FECS_BAR_MASK0, 0, $r1) +- nv_iowr(NV_PGRAPH_FECS_BAR_MASK1, 0, $r1) +- +- // context size calculation, reserve first 256 bytes for use by fuc +- mov $r1 256 +- +- // +- mov $r15 2 +- call(ctx_4170s) +- call(ctx_4170w) +- mov $r15 0x10 +- call(ctx_86c) +- +- // calculate size of mmio context data +- ld b32 $r14 D[$r0 + #hub_mmio_list_head] +- ld b32 $r15 D[$r0 + #hub_mmio_list_tail] +- call(mmctx_size) +- +- // set mmctx base addresses now so we don't have to do it later, +- // they don't (currently) ever change +- shr b32 $r4 $r1 8 +- nv_iowr(NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE, 0, $r4) +- nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE, 0, $r4) +- add b32 $r3 0x1300 +- add b32 $r1 $r15 +- shr b32 $r15 2 +- nv_iowr(NV_PGRAPH_FECS_MMCTX_LOAD_COUNT, 0, $r15) // wtf?? +- +- // strands, base offset needs to be aligned to 256 bytes +- shr b32 $r1 8 +- add b32 $r1 1 +- shl b32 $r1 8 +- mov b32 $r15 $r1 +- call(strand_ctx_init) +- add b32 $r1 $r15 +- +- // initialise each GPC in sequence by passing in the offset of its +- // context data in GPCn_CC_SCRATCH[1], and starting its FUC (which +- // has previously been uploaded by the host) running. +- // +- // the GPC fuc init sequence will set GPCn_CC_SCRATCH[0] bit 31 +- // when it has completed, and return the size of its context data +- // in GPCn_CC_SCRATCH[1] +- // +- ld b32 $r3 D[$r0 + #gpc_count] +- imm32($r4, 0x502000) +- init_gpc: +- // setup, and start GPC ucode running +- add b32 $r14 $r4 0x804 +- mov b32 $r15 $r1 +- call(nv_wr32) // CC_SCRATCH[1] = ctx offset +- add b32 $r14 $r4 0x10c +- clear b32 $r15 +- call(nv_wr32) +- add b32 $r14 $r4 0x104 +- call(nv_wr32) // ENTRY +- add b32 $r14 $r4 0x100 +- mov $r15 2 // CTRL_START_TRIGGER +- call(nv_wr32) // CTRL +- +- // wait for it to complete, and adjust context size +- add b32 $r14 $r4 0x800 +- init_gpc_wait: +- call(nv_rd32) +- xbit $r15 $r15 31 +- bra e #init_gpc_wait +- add b32 $r14 $r4 0x804 +- call(nv_rd32) +- add b32 $r1 $r15 +- +- // next! +- add b32 $r4 0x8000 +- sub b32 $r3 1 +- bra ne #init_gpc +- +- // +- mov $r15 0 +- call(ctx_86c) +- mov $r15 0 +- call(ctx_4170s) +- +- // save context size, and tell host we're ready +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(1), 0, $r1) +- clear b32 $r1 +- bset $r1 31 +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r1) +- +-// Main program loop, very simple, sleeps until woken up by the interrupt +-// handler, pulls a command from the queue and executes its handler +-// +-main: +- // sleep until we have something to do +- bset $flags $p0 +- sleep $p0 +- mov $r13 #cmd_queue +- call(queue_get) +- bra $p1 #main +- +- // context switch, requested by GPU? +- cmpu b32 $r14 0x4001 +- bra ne #main_not_ctx_switch +- trace_set(T_AUTO) +- nv_iord($r1, NV_PGRAPH_FECS_CHAN_ADDR, 0) +- nv_iord($r2, NV_PGRAPH_FECS_CHAN_NEXT, 0) +- +- xbit $r3 $r1 31 +- bra e #chsw_no_prev +- xbit $r3 $r2 31 +- bra e #chsw_prev_no_next +- push $r2 +- mov b32 $r2 $r1 +- trace_set(T_SAVE) +- bclr $flags $p1 +- bset $flags $p2 +- call(ctx_xfer) +- trace_clr(T_SAVE); +- pop $r2 +- trace_set(T_LOAD); +- bset $flags $p1 +- call(ctx_xfer) +- trace_clr(T_LOAD); +- bra #chsw_done +- chsw_prev_no_next: +- push $r2 +- mov b32 $r2 $r1 +- bclr $flags $p1 +- bclr $flags $p2 +- call(ctx_xfer) +- pop $r2 +- nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) +- bra #chsw_done +- chsw_no_prev: +- xbit $r3 $r2 31 +- bra e #chsw_done +- bset $flags $p1 +- bclr $flags $p2 +- call(ctx_xfer) +- +- // ack the context switch request +- chsw_done: +- mov $r2 NV_PGRAPH_FECS_CHSW_ACK +- nv_iowr(NV_PGRAPH_FECS_CHSW, 0, $r2) +- trace_clr(T_AUTO) +- bra #main +- +- // request to set current channel? (*not* a context switch) +- main_not_ctx_switch: +- cmpu b32 $r14 0x0001 +- bra ne #main_not_ctx_chan +- mov b32 $r2 $r15 +- call(ctx_chan) +- bra #main_done +- +- // request to store current channel context? +- main_not_ctx_chan: +- cmpu b32 $r14 0x0002 +- bra ne #main_not_ctx_save +- trace_set(T_SAVE) +- bclr $flags $p1 +- bclr $flags $p2 +- call(ctx_xfer) +- trace_clr(T_SAVE) +- bra #main_done +- +- main_not_ctx_save: +- shl b32 $r15 $r14 16 +- or $r15 E_BAD_COMMAND +- call(error) +- bra #main +- +- main_done: +- clear b32 $r2 +- bset $r2 31 +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(0), 0, $r2) +- bra #main +- +-// interrupt handler +-ih: +- push $r8 +- mov $r8 $flags +- push $r8 +- push $r9 +- push $r10 +- push $r11 +- push $r13 +- push $r14 +- push $r15 +- clear b32 $r0 +- +- // incoming fifo command? +- nv_iord($r10, NV_PGRAPH_FECS_INTR, 0) +- and $r11 $r10 NV_PGRAPH_FECS_INTR_FIFO +- bra e #ih_no_fifo +- // queue incoming fifo command for later processing +- mov $r13 #cmd_queue +- nv_iord($r14, NV_PGRAPH_FECS_FIFO_CMD, 0) +- nv_iord($r15, NV_PGRAPH_FECS_FIFO_DATA, 0) +- call(queue_put) +- add b32 $r11 0x400 +- mov $r14 1 +- nv_iowr(NV_PGRAPH_FECS_FIFO_ACK, 0, $r14) +- +- // context switch request? +- ih_no_fifo: +- and $r11 $r10 NV_PGRAPH_FECS_INTR_CHSW +- bra e #ih_no_ctxsw +- // enqueue a context switch for later processing +- mov $r13 #cmd_queue +- mov $r14 0x4001 +- call(queue_put) +- +- // firmware method? +- ih_no_ctxsw: +- and $r11 $r10 NV_PGRAPH_FECS_INTR_FWMTHD +- bra e #ih_no_fwmthd +- // none we handle; report to host and ack +- nv_rd32($r15, NV_PGRAPH_TRAPPED_DATA_LO) +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(4), 0, $r15) +- nv_rd32($r15, NV_PGRAPH_TRAPPED_ADDR) +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(3), 0, $r15) +- extr $r14 $r15 16:18 +- shl b32 $r14 $r14 2 +- imm32($r15, NV_PGRAPH_FE_OBJECT_TABLE(0)) +- add b32 $r14 $r15 +- call(nv_rd32) +- nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_VAL(2), 0, $r15) +- mov $r15 E_BAD_FWMTHD +- call(error) +- mov $r11 0x100 +- nv_wr32(0x400144, $r11) +- +- // anything we didn't handle, bring it to the host's attention +- ih_no_fwmthd: +- mov $r11 0x504 // FIFO | CHSW | FWMTHD +- not b32 $r11 +- and $r11 $r10 $r11 +- bra e #ih_no_other +- nv_iowr(NV_PGRAPH_FECS_INTR_UP_SET, 0, $r11) +- +- // ack, and wake up main() +- ih_no_other: +- nv_iowr(NV_PGRAPH_FECS_INTR_ACK, 0, $r10) +- +- pop $r15 +- pop $r14 +- pop $r13 +- pop $r11 +- pop $r10 +- pop $r9 +- pop $r8 +- mov $flags $r8 +- pop $r8 +- bclr $flags $p0 +- iret +- +-#if CHIPSET < GK100 +-// Not real sure, but, MEM_CMD 7 will hang forever if this isn't done +-ctx_4160s: +- mov $r15 1 +- nv_wr32(0x404160, $r15) +- ctx_4160s_wait: +- nv_rd32($r15, 0x404160) +- xbit $r15 $r15 4 +- bra e #ctx_4160s_wait +- ret +- +-// Without clearing again at end of xfer, some things cause PGRAPH +-// to hang with STATUS=0x00000007 until it's cleared.. fbcon can +-// still function with it set however... +-ctx_4160c: +- clear b32 $r15 +- nv_wr32(0x404160, $r15) +- ret +-#endif +- +-// Again, not real sure +-// +-// In: $r15 value to set 0x404170 to +-// +-ctx_4170s: +- or $r15 0x10 +- nv_wr32(0x404170, $r15) +- ret +- +-// Waits for a ctx_4170s() call to complete +-// +-ctx_4170w: +- nv_rd32($r15, 0x404170) +- and $r15 0x10 +- bra ne #ctx_4170w +- ret +- +-// Disables various things, waits a bit, and re-enables them.. +-// +-// Not sure how exactly this helps, perhaps "ENABLE" is not such a +-// good description for the bits we turn off? Anyways, without this, +-// funny things happen. +-// +-ctx_redswitch: +- mov $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC +- or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP +- or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC +- or $r14 NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN +- nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) +- mov $r15 8 +- ctx_redswitch_delay: +- sub b32 $r15 1 +- bra ne #ctx_redswitch_delay +- or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP +- or $r14 NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN +- nv_iowr(NV_PGRAPH_FECS_RED_SWITCH, 0, $r14) +- ret +- +-// Not a clue what this is for, except that unless the value is 0x10, the +-// strand context is saved (and presumably restored) incorrectly.. +-// +-// In: $r15 value to set to (0x00/0x10 are used) +-// +-ctx_86c: +- nv_iowr(NV_PGRAPH_FECS_UNK86C, 0, $r15) +- nv_wr32(0x408a14, $r15) +- nv_wr32(NV_PGRAPH_GPCX_GPCCS_UNK86C, $r15) +- ret +- +-// In: $r15 NV_PGRAPH_FECS_MEM_CMD_* +-ctx_mem: +- nv_iowr(NV_PGRAPH_FECS_MEM_CMD, 0, $r15) +- ctx_mem_wait: +- nv_iord($r15, NV_PGRAPH_FECS_MEM_CMD, 0) +- or $r15 $r15 +- bra ne #ctx_mem_wait +- ret +- +-// ctx_load - load's a channel's ctxctl data, and selects its vm +-// +-// In: $r2 channel address +-// +-ctx_load: +- trace_set(T_CHAN) +- +- // switch to channel, somewhat magic in parts.. +- mov $r10 12 // DONE_UNK12 +- call(wait_donez) +- clear b32 $r15 +- nv_iowr(0x409a24, 0, $r15) +- nv_iowr(NV_PGRAPH_FECS_CHAN_NEXT, 0, $r2) +- nv_iowr(NV_PGRAPH_FECS_MEM_CHAN, 0, $r2) +- mov $r15 NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN +- call(ctx_mem) +- nv_iowr(NV_PGRAPH_FECS_CHAN_ADDR, 0, $r2) +- +- // load channel header, fetch PGRAPH context pointer +- mov $xtargets $r0 +- bclr $r2 31 +- shl b32 $r2 4 +- add b32 $r2 2 +- +- trace_set(T_LCHAN) +- nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r2) +- imm32($r2, NV_PGRAPH_FECS_MEM_TARGET_UNK31) +- or $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM +- nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) +- mov $r1 0x10 // chan + 0x0210 +- mov $r2 #xfer_data +- sethi $r2 0x00020000 // 16 bytes +- xdld $r1 $r2 +- xdwait +- trace_clr(T_LCHAN) +- +- // update current context +- ld b32 $r1 D[$r0 + #xfer_data + 4] +- shl b32 $r1 24 +- ld b32 $r2 D[$r0 + #xfer_data + 0] +- shr b32 $r2 8 +- or $r1 $r2 +- st b32 D[$r0 + #ctx_current] $r1 +- +- // set transfer base to start of context, and fetch context header +- trace_set(T_LCTXH) +- nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r1) +- mov $r2 NV_PGRAPH_FECS_MEM_TARGET_AS_VM +- nv_iowr(NV_PGRAPH_FECS_MEM_TARGET, 0, $r2) +- mov $r1 #chan_data +- sethi $r1 0x00060000 // 256 bytes +- xdld $r0 $r1 +- xdwait +- trace_clr(T_LCTXH) +- +- trace_clr(T_CHAN) +- ret +- +-// ctx_chan - handler for HUB_SET_CHAN command, will set a channel as +-// the active channel for ctxctl, but not actually transfer +-// any context data. intended for use only during initial +-// context construction. +-// +-// In: $r2 channel address +-// +-ctx_chan: +-#if CHIPSET < GK100 +- call(ctx_4160s) +-#endif +- call(ctx_load) +- mov $r10 12 // DONE_UNK12 +- call(wait_donez) +- mov $r15 5 // MEM_CMD 5 ??? +- call(ctx_mem) +-#if CHIPSET < GK100 +- call(ctx_4160c) +-#endif +- ret +- +-// Execute per-context state overrides list +-// +-// Only executed on the first load of a channel. Might want to look into +-// removing this and having the host directly modify the channel's context +-// to change this state... The nouveau DRM already builds this list as +-// it's definitely needed for NVIDIA's, so we may as well use it for now +-// +-// Input: $r1 mmio list length +-// +-ctx_mmio_exec: +- // set transfer base to be the mmio list +- ld b32 $r3 D[$r0 + #chan_mmio_address] +- nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) +- +- clear b32 $r3 +- ctx_mmio_loop: +- // fetch next 256 bytes of mmio list if necessary +- and $r4 $r3 0xff +- bra ne #ctx_mmio_pull +- mov $r5 #xfer_data +- sethi $r5 0x00060000 // 256 bytes +- xdld $r3 $r5 +- xdwait +- +- // execute a single list entry +- ctx_mmio_pull: +- ld b32 $r14 D[$r4 + #xfer_data + 0x00] +- ld b32 $r15 D[$r4 + #xfer_data + 0x04] +- call(nv_wr32) +- +- // next! +- add b32 $r3 8 +- sub b32 $r1 1 +- bra ne #ctx_mmio_loop +- +- // set transfer base back to the current context +- ctx_mmio_done: +- ld b32 $r3 D[$r0 + #ctx_current] +- nv_iowr(NV_PGRAPH_FECS_MEM_BASE, 0, $r3) +- +- // disable the mmio list now, we don't need/want to execute it again +- st b32 D[$r0 + #chan_mmio_count] $r0 +- mov $r1 #chan_data +- sethi $r1 0x00060000 // 256 bytes +- xdst $r0 $r1 +- xdwait +- ret +- +-// Transfer HUB context data between GPU and storage area +-// +-// In: $r2 channel address +-// $p1 clear on save, set on load +-// $p2 set if opposite direction done/will be done, so: +-// on save it means: "a load will follow this save" +-// on load it means: "a save preceeded this load" +-// +-ctx_xfer: +- // according to mwk, some kind of wait for idle +- mov $r14 4 +- nv_iowr(0x409c08, 0, $r14) +- ctx_xfer_idle: +- nv_iord($r14, 0x409c00, 0) +- and $r14 0x2000 +- bra ne #ctx_xfer_idle +- +- bra not $p1 #ctx_xfer_pre +- bra $p2 #ctx_xfer_pre_load +- ctx_xfer_pre: +- mov $r15 0x10 +- call(ctx_86c) +-#if CHIPSET < GK100 +- call(ctx_4160s) +-#endif +- bra not $p1 #ctx_xfer_exec +- +- ctx_xfer_pre_load: +- mov $r15 2 +- call(ctx_4170s) +- call(ctx_4170w) +- call(ctx_redswitch) +- clear b32 $r15 +- call(ctx_4170s) +- call(ctx_load) +- +- // fetch context pointer, and initiate xfer on all GPCs +- ctx_xfer_exec: +- ld b32 $r1 D[$r0 + #ctx_current] +- +- clear b32 $r2 +- nv_iowr(NV_PGRAPH_FECS_BAR, 0, $r2) +- +- nv_wr32(0x41a500, $r1) // GPC_BCAST_WRCMD_DATA = ctx pointer +- xbit $r15 $flags $p1 +- xbit $r2 $flags $p2 +- shl b32 $r2 1 +- or $r15 $r2 +- nv_wr32(0x41a504, $r15) // GPC_BCAST_WRCMD_CMD = GPC_XFER(type) +- +- // strands +- call(strand_pre) +- clear b32 $r2 +- nv_iowr(NV_PGRAPH_FECS_STRAND_SELECT, 0x3f, $r2) +- xbit $r2 $flags $p1 // SAVE/LOAD +- add b32 $r2 NV_PGRAPH_FECS_STRAND_CMD_SAVE +- nv_iowr(NV_PGRAPH_FECS_STRAND_CMD, 0x3f, $r2) +- +- // mmio context +- xbit $r10 $flags $p1 // direction +- or $r10 6 // first, last +- mov $r11 0 // base = 0 +- ld b32 $r12 D[$r0 + #hub_mmio_list_head] +- ld b32 $r13 D[$r0 + #hub_mmio_list_tail] +- mov $r14 0 // not multi +- call(mmctx_xfer) +- +- // wait for GPCs to all complete +- mov $r10 8 // DONE_BAR +- call(wait_doneo) +- +- // wait for strand xfer to complete +- call(strand_wait) +- +- // post-op +- bra $p1 #ctx_xfer_post +- mov $r10 12 // DONE_UNK12 +- call(wait_donez) +- mov $r15 5 // MEM_CMD 5 ??? +- call(ctx_mem) +- +- bra $p2 #ctx_xfer_done +- ctx_xfer_post: +- mov $r15 2 +- call(ctx_4170s) +- clear b32 $r15 +- call(ctx_86c) +- call(strand_post) +- call(ctx_4170w) +- clear b32 $r15 +- call(ctx_4170s) +- +- bra not $p1 #ctx_xfer_no_post_mmio +- ld b32 $r1 D[$r0 + #chan_mmio_count] +- or $r1 $r1 +- bra e #ctx_xfer_no_post_mmio +- call(ctx_mmio_exec) +- +- ctx_xfer_no_post_mmio: +-#if CHIPSET < GK100 +- call(ctx_4160c) +-#endif +- +- ctx_xfer_done: +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 +deleted file mode 100644 +index 27591b30..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5 ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define CHIPSET GK208 +-#include "macros.fuc" +- +-.section #gm107_grhub_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "hub.fuc" +-#undef INCLUDE_DATA +- +-.section #gm107_grhub_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "hub.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h +deleted file mode 100644 +index 5f953c5c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubgm107.fuc5.h ++++ /dev/null +@@ -1,916 +0,0 @@ +-uint32_t gm107_grhub_data[] = { +-/* 0x0000: hub_mmio_list_head */ +- 0x00000300, +-/* 0x0004: hub_mmio_list_tail */ +- 0x00000304, +-/* 0x0008: gpc_count */ +- 0x00000000, +-/* 0x000c: rop_count */ +- 0x00000000, +-/* 0x0010: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: ctx_current */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: chan_data */ +-/* 0x0100: chan_mmio_count */ +- 0x00000000, +-/* 0x0104: chan_mmio_address */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0200: xfer_data */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0300: hub_mmio_list_base */ +- 0x0417e91c, +-}; +- +-uint32_t gm107_grhub_code[] = { +- 0x030e0ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0xf489a408, +- 0x020f0b1b, +- 0x0002f87e, +-/* 0x001a: queue_put_next */ +- 0x98c400f8, +- 0x0384b607, +- 0xb6008dbb, +- 0x8eb50880, +- 0x018fb500, +- 0xf00190b6, +- 0xd9b50f94, +-/* 0x0037: queue_get */ +- 0xf400f801, +- 0xd8980131, +- 0x01d99800, +- 0x0bf489a4, +- 0x0789c421, +- 0xbb0394b6, +- 0x90b6009d, +- 0x009e9808, +- 0xb6019f98, +- 0x84f00180, +- 0x00d8b50f, +-/* 0x0063: queue_get_done */ +- 0xf80132f4, +-/* 0x0065: nv_rd32 */ +- 0xf0ecb200, +- 0x00801fc9, +- 0x0cf601ca, +-/* 0x0073: nv_rd32_wait */ +- 0x8c04bd00, +- 0xcf01ca00, +- 0xccc800cc, +- 0xf61bf41f, +- 0xec7e060a, +- 0x008f0000, +- 0xffcf01cb, +-/* 0x008f: nv_wr32 */ +- 0x8000f800, +- 0xf601cc00, +- 0x04bd000f, +- 0xc9f0ecb2, +- 0x1ec9f01f, +- 0x01ca0080, +- 0xbd000cf6, +-/* 0x00a9: nv_wr32_wait */ +- 0xca008c04, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f61b, +-/* 0x00b8: wait_donez */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x00cf: wait_donez_ne */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf61bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x00ec: wait_doneo */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x0103: wait_doneo_e */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf60bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x0120: mmctx_size */ +-/* 0x0122: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0x1bf4efa4, +- 0xf89fb2ec, +-/* 0x013d: mmctx_xfer */ +- 0xf094bd00, +- 0x00800199, +- 0x09f60237, +- 0xbd04bd00, +- 0x05bbfd94, +- 0x800f0bf4, +- 0xf601c400, +- 0x04bd000b, +-/* 0x015f: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0xc6008018, +- 0x000ef601, +- 0x008004bd, +- 0x0ff601c7, +- 0xf004bd00, +-/* 0x017a: mmctx_multi_disabled */ +- 0xabc80199, +- 0x10b4b600, +- 0xc80cb9f0, +- 0xe4b601ae, +- 0x05befd11, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x0195: mmctx_exec_loop */ +-/* 0x0195: mmctx_wait_free */ +- 0xc5008e04, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f60b, +- 0x05e9fd00, +- 0x01c80080, +- 0xbd000ef6, +- 0x04c0b604, +- 0x1bf4cda4, +- 0x02abc8df, +-/* 0x01bf: mmctx_fini_wait */ +- 0x8b1c1bf4, +- 0xcf01c500, +- 0xb4f000bb, +- 0x10b4b01f, +- 0x0af31bf4, +- 0x00b87e05, +- 0x250ef400, +-/* 0x01d8: mmctx_stop */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x12b9f00c, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x01ed: mmctx_stop_wait */ +- 0xc5008b04, +- 0x00bbcf01, +- 0xf412bbc8, +-/* 0x01fa: mmctx_done */ +- 0x94bdf61b, +- 0x800199f0, +- 0xf6021700, +- 0x04bd0009, +-/* 0x020a: strand_wait */ +- 0xa0f900f8, +- 0xb87e020a, +- 0xa0fc0000, +-/* 0x0216: strand_pre */ +- 0x0c0900f8, +- 0x024afc80, +- 0xbd0009f6, +- 0x020a7e04, +-/* 0x0227: strand_post */ +- 0x0900f800, +- 0x4afc800d, +- 0x0009f602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0238: strand_set */ +- 0xfc800f0c, +- 0x0cf6024f, +- 0x0c04bd00, +- 0x4afc800b, +- 0x000cf602, +- 0xfc8004bd, +- 0x0ef6024f, +- 0x0c04bd00, +- 0x4afc800a, +- 0x000cf602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0268: strand_ctx_init */ +- 0x99f094bd, +- 0x37008003, +- 0x0009f602, +- 0x167e04bd, +- 0x030e0002, +- 0x0002387e, +- 0xfc80c4bd, +- 0x0cf60247, +- 0x0c04bd00, +- 0x4afc8001, +- 0x000cf602, +- 0x0a7e04bd, +- 0x0c920002, +- 0x46fc8001, +- 0x000cf602, +- 0x020c04bd, +- 0x024afc80, +- 0xbd000cf6, +- 0x020a7e04, +- 0x02277e00, +- 0x42008800, +- 0x20008902, +- 0x0099cf02, +-/* 0x02c7: ctx_init_strand_loop */ +- 0xf608fe95, +- 0x8ef6008e, +- 0x808acf40, +- 0xb606a5b6, +- 0xeabb01a0, +- 0x0480b600, +- 0xf40192b6, +- 0xe4b6e81b, +- 0xf2efbc08, +- 0x99f094bd, +- 0x17008003, +- 0x0009f602, +- 0x00f804bd, +-/* 0x02f8: error */ +- 0x02050080, +- 0xbd000ff6, +- 0x80010f04, +- 0xf6030700, +- 0x04bd000f, +-/* 0x030e: init */ +- 0x04bd00f8, +- 0x410007fe, +- 0x11cf4200, +- 0x0911e700, +- 0x0814b601, +- 0x020014fe, +- 0x12004002, +- 0xbd0002f6, +- 0x05c94104, +- 0xbd0010fe, +- 0x07004024, +- 0xbd0002f6, +- 0x20034204, +- 0x01010080, +- 0xbd0002f6, +- 0x20044204, +- 0x01010480, +- 0xbd0002f6, +- 0x200b4204, +- 0x01010880, +- 0xbd0002f6, +- 0x200c4204, +- 0x01011c80, +- 0xbd0002f6, +- 0x01039204, +- 0x03090080, +- 0xbd0003f6, +- 0x87044204, +- 0xf6040040, +- 0x04bd0002, +- 0x00400402, +- 0x0002f603, +- 0x31f404bd, +- 0x96048e10, +- 0x00657e40, +- 0xc7feb200, +- 0x01b590f1, +- 0x1ff4f003, +- 0x01020fb5, +- 0x041fbb01, +- 0x800112b6, +- 0xf6010300, +- 0x04bd0001, +- 0x01040080, +- 0xbd0001f6, +- 0x01004104, +- 0xa87e020f, +- 0xb77e0006, +- 0x100f0006, +- 0x0006f97e, +- 0x98000e98, +- 0x207e010f, +- 0x14950001, +- 0xc0008008, +- 0x0004f601, +- 0x008004bd, +- 0x04f601c1, +- 0xb704bd00, +- 0xbb130030, +- 0xf5b6001f, +- 0xd3008002, +- 0x000ff601, +- 0x15b604bd, +- 0x0110b608, +- 0xb20814b6, +- 0x02687e1f, +- 0x001fbb00, +- 0x84020398, +-/* 0x041f: init_gpc */ +- 0xb8502000, +- 0x0008044e, +- 0x8f7e1fb2, +- 0x4eb80000, +- 0xbd00010c, +- 0x008f7ef4, +- 0x044eb800, +- 0x8f7e0001, +- 0x4eb80000, +- 0x0f000100, +- 0x008f7e02, +- 0x004eb800, +-/* 0x044e: init_gpc_wait */ +- 0x657e0008, +- 0xffc80000, +- 0xf90bf41f, +- 0x08044eb8, +- 0x00657e00, +- 0x001fbb00, +- 0x800040b7, +- 0xf40132b6, +- 0x000fb41b, +- 0x0006f97e, +- 0xa87e000f, +- 0x00800006, +- 0x01f60201, +- 0xbd04bd00, +- 0x1f19f014, +- 0x02300080, +- 0xbd0001f6, +-/* 0x0491: main */ +- 0x0031f404, +- 0x0d0028f4, +- 0x00377e10, +- 0xf401f400, +- 0x4001e4b1, +- 0x00c71bf5, +- 0x99f094bd, +- 0x37008004, +- 0x0009f602, +- 0x008104bd, +- 0x11cf02c0, +- 0xc1008200, +- 0x0022cf02, +- 0xf41f13c8, +- 0x23c8770b, +- 0x550bf41f, +- 0x12b220f9, +- 0x99f094bd, +- 0x37008007, +- 0x0009f602, +- 0x32f404bd, +- 0x0231f401, +- 0x00087c7e, +- 0x99f094bd, +- 0x17008007, +- 0x0009f602, +- 0x20fc04bd, +- 0x99f094bd, +- 0x37008006, +- 0x0009f602, +- 0x31f404bd, +- 0x087c7e01, +- 0xf094bd00, +- 0x00800699, +- 0x09f60217, +- 0xf404bd00, +-/* 0x0522: chsw_prev_no_next */ +- 0x20f92f0e, +- 0x32f412b2, +- 0x0232f401, +- 0x00087c7e, +- 0x008020fc, +- 0x02f602c0, +- 0xf404bd00, +-/* 0x053e: chsw_no_prev */ +- 0x23c8130e, +- 0x0d0bf41f, +- 0xf40131f4, +- 0x7c7e0232, +-/* 0x054e: chsw_done */ +- 0x01020008, +- 0x02c30080, +- 0xbd0002f6, +- 0xf094bd04, +- 0x00800499, +- 0x09f60217, +- 0xf504bd00, +-/* 0x056b: main_not_ctx_switch */ +- 0xb0ff2a0e, +- 0x1bf401e4, +- 0x7ef2b20c, +- 0xf400081c, +-/* 0x057a: main_not_ctx_chan */ +- 0xe4b0400e, +- 0x2c1bf402, +- 0x99f094bd, +- 0x37008007, +- 0x0009f602, +- 0x32f404bd, +- 0x0232f401, +- 0x00087c7e, +- 0x99f094bd, +- 0x17008007, +- 0x0009f602, +- 0x0ef404bd, +-/* 0x05a9: main_not_ctx_save */ +- 0x10ef9411, +- 0x7e01f5f0, +- 0xf50002f8, +-/* 0x05b7: main_done */ +- 0xbdfede0e, +- 0x1f29f024, +- 0x02300080, +- 0xbd0002f6, +- 0xcc0ef504, +-/* 0x05c9: ih */ +- 0xfe80f9fe, +- 0x80f90188, +- 0xa0f990f9, +- 0xd0f9b0f9, +- 0xf0f9e0f9, +- 0x004a04bd, +- 0x00aacf02, +- 0xf404abc4, +- 0x100d230b, +- 0xcf1a004e, +- 0x004f00ee, +- 0x00ffcf19, +- 0x0000047e, +- 0x0400b0b7, +- 0x0040010e, +- 0x000ef61d, +-/* 0x060a: ih_no_fifo */ +- 0xabe404bd, +- 0x0bf40100, +- 0x4e100d0c, +- 0x047e4001, +-/* 0x061a: ih_no_ctxsw */ +- 0xabe40000, +- 0x0bf40400, +- 0x07088e56, +- 0x00657e40, +- 0x80ffb200, +- 0xf6020400, +- 0x04bd000f, +- 0x4007048e, +- 0x0000657e, +- 0x0080ffb2, +- 0x0ff60203, +- 0xc704bd00, +- 0xee9450fe, +- 0x07008f02, +- 0x00efbb40, +- 0x0000657e, +- 0x02020080, +- 0xbd000ff6, +- 0x7e030f04, +- 0x4b0002f8, +- 0xbfb20100, +- 0x4001448e, +- 0x00008f7e, +-/* 0x0674: ih_no_fwmthd */ +- 0xbd05044b, +- 0xb4abffb0, +- 0x800c0bf4, +- 0xf6030700, +- 0x04bd000b, +-/* 0x0688: ih_no_other */ +- 0xf6010040, +- 0x04bd000a, +- 0xe0fcf0fc, +- 0xb0fcd0fc, +- 0x90fca0fc, +- 0x88fe80fc, +- 0xf480fc00, +- 0x01f80032, +-/* 0x06a8: ctx_4170s */ +- 0xb210f5f0, +- 0x41708eff, +- 0x008f7e40, +-/* 0x06b7: ctx_4170w */ +- 0x8e00f800, +- 0x7e404170, +- 0xb2000065, +- 0x10f4f0ff, +- 0xf8f31bf4, +-/* 0x06c9: ctx_redswitch */ +- 0x02004e00, +- 0xf040e5f0, +- 0xe5f020e5, +- 0x85008010, +- 0x000ef601, +- 0x080f04bd, +-/* 0x06e0: ctx_redswitch_delay */ +- 0xf401f2b6, +- 0xe5f1fd1b, +- 0xe5f10400, +- 0x00800100, +- 0x0ef60185, +- 0xf804bd00, +-/* 0x06f9: ctx_86c */ +- 0x23008000, +- 0x000ff602, +- 0xffb204bd, +- 0x408a148e, +- 0x00008f7e, +- 0x8c8effb2, +- 0x8f7e41a8, +- 0x00f80000, +-/* 0x0718: ctx_mem */ +- 0x02840080, +- 0xbd000ff6, +-/* 0x0721: ctx_mem_wait */ +- 0x84008f04, +- 0x00ffcf02, +- 0xf405fffd, +- 0x00f8f61b, +-/* 0x0730: ctx_load */ +- 0x99f094bd, +- 0x37008005, +- 0x0009f602, +- 0x0c0a04bd, +- 0x0000b87e, +- 0x0080f4bd, +- 0x0ff60289, +- 0x8004bd00, +- 0xf602c100, +- 0x04bd0002, +- 0x02830080, +- 0xbd0002f6, +- 0x7e070f04, +- 0x80000718, +- 0xf602c000, +- 0x04bd0002, +- 0xf0000bfe, +- 0x24b61f2a, +- 0x0220b604, +- 0x99f094bd, +- 0x37008008, +- 0x0009f602, +- 0x008004bd, +- 0x02f60281, +- 0xd204bd00, +- 0x80000000, +- 0x800225f0, +- 0xf6028800, +- 0x04bd0002, +- 0x00421001, +- 0x0223f002, +- 0xf80512fa, +- 0xf094bd03, +- 0x00800899, +- 0x09f60217, +- 0x9804bd00, +- 0x14b68101, +- 0x80029818, +- 0xfd0825b6, +- 0x01b50512, +- 0xf094bd16, +- 0x00800999, +- 0x09f60237, +- 0x8004bd00, +- 0xf6028100, +- 0x04bd0001, +- 0x00800102, +- 0x02f60288, +- 0x4104bd00, +- 0x13f00100, +- 0x0501fa06, +- 0x94bd03f8, +- 0x800999f0, +- 0xf6021700, +- 0x04bd0009, +- 0x99f094bd, +- 0x17008005, +- 0x0009f602, +- 0x00f804bd, +-/* 0x081c: ctx_chan */ +- 0x0007307e, +- 0xb87e0c0a, +- 0x050f0000, +- 0x0007187e, +-/* 0x082e: ctx_mmio_exec */ +- 0x039800f8, +- 0x81008041, +- 0x0003f602, +- 0x34bd04bd, +-/* 0x083c: ctx_mmio_loop */ +- 0xf4ff34c4, +- 0x00450e1b, +- 0x0653f002, +- 0xf80535fa, +-/* 0x084d: ctx_mmio_pull */ +- 0x804e9803, +- 0x7e814f98, +- 0xb600008f, +- 0x12b60830, +- 0xdf1bf401, +-/* 0x0860: ctx_mmio_done */ +- 0x80160398, +- 0xf6028100, +- 0x04bd0003, +- 0x414000b5, +- 0x13f00100, +- 0x0601fa06, +- 0x00f803f8, +-/* 0x087c: ctx_xfer */ +- 0x0080040e, +- 0x0ef60302, +-/* 0x0887: ctx_xfer_idle */ +- 0x8e04bd00, +- 0xcf030000, +- 0xe4f100ee, +- 0x1bf42000, +- 0x0611f4f5, +-/* 0x089b: ctx_xfer_pre */ +- 0x0f0c02f4, +- 0x06f97e10, +- 0x1b11f400, +-/* 0x08a4: ctx_xfer_pre_load */ +- 0xa87e020f, +- 0xb77e0006, +- 0xc97e0006, +- 0xf4bd0006, +- 0x0006a87e, +- 0x0007307e, +-/* 0x08bc: ctx_xfer_exec */ +- 0xbd160198, +- 0x05008024, +- 0x0002f601, +- 0x1fb204bd, +- 0x41a5008e, +- 0x00008f7e, +- 0xf001fcf0, +- 0x24b6022c, +- 0x05f2fd01, +- 0x048effb2, +- 0x8f7e41a5, +- 0x167e0000, +- 0x24bd0002, +- 0x0247fc80, +- 0xbd0002f6, +- 0x012cf004, +- 0x800320b6, +- 0xf6024afc, +- 0x04bd0002, +- 0xf001acf0, +- 0x000b06a5, +- 0x98000c98, +- 0x000e010d, +- 0x00013d7e, +- 0xec7e080a, +- 0x0a7e0000, +- 0x01f40002, +- 0x7e0c0a12, +- 0x0f0000b8, +- 0x07187e05, +- 0x2d02f400, +-/* 0x0938: ctx_xfer_post */ +- 0xa87e020f, +- 0xf4bd0006, +- 0x0006f97e, +- 0x0002277e, +- 0x0006b77e, +- 0xa87ef4bd, +- 0x11f40006, +- 0x40019810, +- 0xf40511fd, +- 0x2e7e070b, +-/* 0x0962: ctx_xfer_no_post_mmio */ +-/* 0x0962: ctx_xfer_done */ +- 0x00f80008, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 +deleted file mode 100644 +index 7c5d2563..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5 ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define CHIPSET GK208 +-#include "macros.fuc" +- +-.section #nv108_grhub_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "hub.fuc" +-#undef INCLUDE_DATA +- +-.section #nv108_grhub_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "hub.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h +deleted file mode 100644 +index e49b5a87..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnv108.fuc5.h ++++ /dev/null +@@ -1,916 +0,0 @@ +-uint32_t nv108_grhub_data[] = { +-/* 0x0000: hub_mmio_list_head */ +- 0x00000300, +-/* 0x0004: hub_mmio_list_tail */ +- 0x00000304, +-/* 0x0008: gpc_count */ +- 0x00000000, +-/* 0x000c: rop_count */ +- 0x00000000, +-/* 0x0010: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: ctx_current */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: chan_data */ +-/* 0x0100: chan_mmio_count */ +- 0x00000000, +-/* 0x0104: chan_mmio_address */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0200: xfer_data */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0300: hub_mmio_list_base */ +- 0x0417e91c, +-}; +- +-uint32_t nv108_grhub_code[] = { +- 0x030e0ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0xf489a408, +- 0x020f0b1b, +- 0x0002f87e, +-/* 0x001a: queue_put_next */ +- 0x98c400f8, +- 0x0384b607, +- 0xb6008dbb, +- 0x8eb50880, +- 0x018fb500, +- 0xf00190b6, +- 0xd9b50f94, +-/* 0x0037: queue_get */ +- 0xf400f801, +- 0xd8980131, +- 0x01d99800, +- 0x0bf489a4, +- 0x0789c421, +- 0xbb0394b6, +- 0x90b6009d, +- 0x009e9808, +- 0xb6019f98, +- 0x84f00180, +- 0x00d8b50f, +-/* 0x0063: queue_get_done */ +- 0xf80132f4, +-/* 0x0065: nv_rd32 */ +- 0xf0ecb200, +- 0x00801fc9, +- 0x0cf601ca, +-/* 0x0073: nv_rd32_wait */ +- 0x8c04bd00, +- 0xcf01ca00, +- 0xccc800cc, +- 0xf61bf41f, +- 0xec7e060a, +- 0x008f0000, +- 0xffcf01cb, +-/* 0x008f: nv_wr32 */ +- 0x8000f800, +- 0xf601cc00, +- 0x04bd000f, +- 0xc9f0ecb2, +- 0x1ec9f01f, +- 0x01ca0080, +- 0xbd000cf6, +-/* 0x00a9: nv_wr32_wait */ +- 0xca008c04, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f61b, +-/* 0x00b8: wait_donez */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x00cf: wait_donez_ne */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf61bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x00ec: wait_doneo */ +- 0x99f094bd, +- 0x37008000, +- 0x0009f602, +- 0x008004bd, +- 0x0af60206, +-/* 0x0103: wait_doneo_e */ +- 0x8804bd00, +- 0xcf010000, +- 0x8aff0088, +- 0xf60bf488, +- 0x99f094bd, +- 0x17008000, +- 0x0009f602, +- 0x00f804bd, +-/* 0x0120: mmctx_size */ +-/* 0x0122: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0x1bf4efa4, +- 0xf89fb2ec, +-/* 0x013d: mmctx_xfer */ +- 0xf094bd00, +- 0x00800199, +- 0x09f60237, +- 0xbd04bd00, +- 0x05bbfd94, +- 0x800f0bf4, +- 0xf601c400, +- 0x04bd000b, +-/* 0x015f: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0xc6008018, +- 0x000ef601, +- 0x008004bd, +- 0x0ff601c7, +- 0xf004bd00, +-/* 0x017a: mmctx_multi_disabled */ +- 0xabc80199, +- 0x10b4b600, +- 0xc80cb9f0, +- 0xe4b601ae, +- 0x05befd11, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x0195: mmctx_exec_loop */ +-/* 0x0195: mmctx_wait_free */ +- 0xc5008e04, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f60b, +- 0x05e9fd00, +- 0x01c80080, +- 0xbd000ef6, +- 0x04c0b604, +- 0x1bf4cda4, +- 0x02abc8df, +-/* 0x01bf: mmctx_fini_wait */ +- 0x8b1c1bf4, +- 0xcf01c500, +- 0xb4f000bb, +- 0x10b4b01f, +- 0x0af31bf4, +- 0x00b87e05, +- 0x250ef400, +-/* 0x01d8: mmctx_stop */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x12b9f00c, +- 0x01c50080, +- 0xbd000bf6, +-/* 0x01ed: mmctx_stop_wait */ +- 0xc5008b04, +- 0x00bbcf01, +- 0xf412bbc8, +-/* 0x01fa: mmctx_done */ +- 0x94bdf61b, +- 0x800199f0, +- 0xf6021700, +- 0x04bd0009, +-/* 0x020a: strand_wait */ +- 0xa0f900f8, +- 0xb87e020a, +- 0xa0fc0000, +-/* 0x0216: strand_pre */ +- 0x0c0900f8, +- 0x024afc80, +- 0xbd0009f6, +- 0x020a7e04, +-/* 0x0227: strand_post */ +- 0x0900f800, +- 0x4afc800d, +- 0x0009f602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0238: strand_set */ +- 0xfc800f0c, +- 0x0cf6024f, +- 0x0c04bd00, +- 0x4afc800b, +- 0x000cf602, +- 0xfc8004bd, +- 0x0ef6024f, +- 0x0c04bd00, +- 0x4afc800a, +- 0x000cf602, +- 0x0a7e04bd, +- 0x00f80002, +-/* 0x0268: strand_ctx_init */ +- 0x99f094bd, +- 0x37008003, +- 0x0009f602, +- 0x167e04bd, +- 0x030e0002, +- 0x0002387e, +- 0xfc80c4bd, +- 0x0cf60247, +- 0x0c04bd00, +- 0x4afc8001, +- 0x000cf602, +- 0x0a7e04bd, +- 0x0c920002, +- 0x46fc8001, +- 0x000cf602, +- 0x020c04bd, +- 0x024afc80, +- 0xbd000cf6, +- 0x020a7e04, +- 0x02277e00, +- 0x42008800, +- 0x20008902, +- 0x0099cf02, +-/* 0x02c7: ctx_init_strand_loop */ +- 0xf608fe95, +- 0x8ef6008e, +- 0x808acf40, +- 0xb606a5b6, +- 0xeabb01a0, +- 0x0480b600, +- 0xf40192b6, +- 0xe4b6e81b, +- 0xf2efbc08, +- 0x99f094bd, +- 0x17008003, +- 0x0009f602, +- 0x00f804bd, +-/* 0x02f8: error */ +- 0x02050080, +- 0xbd000ff6, +- 0x80010f04, +- 0xf6030700, +- 0x04bd000f, +-/* 0x030e: init */ +- 0x04bd00f8, +- 0x410007fe, +- 0x11cf4200, +- 0x0911e700, +- 0x0814b601, +- 0x020014fe, +- 0x12004002, +- 0xbd0002f6, +- 0x05c94104, +- 0xbd0010fe, +- 0x07004024, +- 0xbd0002f6, +- 0x20034204, +- 0x01010080, +- 0xbd0002f6, +- 0x20044204, +- 0x01010480, +- 0xbd0002f6, +- 0x200b4204, +- 0x01010880, +- 0xbd0002f6, +- 0x200c4204, +- 0x01011c80, +- 0xbd0002f6, +- 0x01039204, +- 0x03090080, +- 0xbd0003f6, +- 0x87044204, +- 0xf6040040, +- 0x04bd0002, +- 0x00400402, +- 0x0002f603, +- 0x31f404bd, +- 0x96048e10, +- 0x00657e40, +- 0xc7feb200, +- 0x01b590f1, +- 0x1ff4f003, +- 0x01020fb5, +- 0x041fbb01, +- 0x800112b6, +- 0xf6010300, +- 0x04bd0001, +- 0x01040080, +- 0xbd0001f6, +- 0x01004104, +- 0xa87e020f, +- 0xb77e0006, +- 0x100f0006, +- 0x0006f97e, +- 0x98000e98, +- 0x207e010f, +- 0x14950001, +- 0xc0008008, +- 0x0004f601, +- 0x008004bd, +- 0x04f601c1, +- 0xb704bd00, +- 0xbb130030, +- 0xf5b6001f, +- 0xd3008002, +- 0x000ff601, +- 0x15b604bd, +- 0x0110b608, +- 0xb20814b6, +- 0x02687e1f, +- 0x001fbb00, +- 0x84020398, +-/* 0x041f: init_gpc */ +- 0xb8502000, +- 0x0008044e, +- 0x8f7e1fb2, +- 0x4eb80000, +- 0xbd00010c, +- 0x008f7ef4, +- 0x044eb800, +- 0x8f7e0001, +- 0x4eb80000, +- 0x0f000100, +- 0x008f7e02, +- 0x004eb800, +-/* 0x044e: init_gpc_wait */ +- 0x657e0008, +- 0xffc80000, +- 0xf90bf41f, +- 0x08044eb8, +- 0x00657e00, +- 0x001fbb00, +- 0x800040b7, +- 0xf40132b6, +- 0x000fb41b, +- 0x0006f97e, +- 0xa87e000f, +- 0x00800006, +- 0x01f60201, +- 0xbd04bd00, +- 0x1f19f014, +- 0x02300080, +- 0xbd0001f6, +-/* 0x0491: main */ +- 0x0031f404, +- 0x0d0028f4, +- 0x00377e10, +- 0xf401f400, +- 0x4001e4b1, +- 0x00c71bf5, +- 0x99f094bd, +- 0x37008004, +- 0x0009f602, +- 0x008104bd, +- 0x11cf02c0, +- 0xc1008200, +- 0x0022cf02, +- 0xf41f13c8, +- 0x23c8770b, +- 0x550bf41f, +- 0x12b220f9, +- 0x99f094bd, +- 0x37008007, +- 0x0009f602, +- 0x32f404bd, +- 0x0231f401, +- 0x00087c7e, +- 0x99f094bd, +- 0x17008007, +- 0x0009f602, +- 0x20fc04bd, +- 0x99f094bd, +- 0x37008006, +- 0x0009f602, +- 0x31f404bd, +- 0x087c7e01, +- 0xf094bd00, +- 0x00800699, +- 0x09f60217, +- 0xf404bd00, +-/* 0x0522: chsw_prev_no_next */ +- 0x20f92f0e, +- 0x32f412b2, +- 0x0232f401, +- 0x00087c7e, +- 0x008020fc, +- 0x02f602c0, +- 0xf404bd00, +-/* 0x053e: chsw_no_prev */ +- 0x23c8130e, +- 0x0d0bf41f, +- 0xf40131f4, +- 0x7c7e0232, +-/* 0x054e: chsw_done */ +- 0x01020008, +- 0x02c30080, +- 0xbd0002f6, +- 0xf094bd04, +- 0x00800499, +- 0x09f60217, +- 0xf504bd00, +-/* 0x056b: main_not_ctx_switch */ +- 0xb0ff2a0e, +- 0x1bf401e4, +- 0x7ef2b20c, +- 0xf400081c, +-/* 0x057a: main_not_ctx_chan */ +- 0xe4b0400e, +- 0x2c1bf402, +- 0x99f094bd, +- 0x37008007, +- 0x0009f602, +- 0x32f404bd, +- 0x0232f401, +- 0x00087c7e, +- 0x99f094bd, +- 0x17008007, +- 0x0009f602, +- 0x0ef404bd, +-/* 0x05a9: main_not_ctx_save */ +- 0x10ef9411, +- 0x7e01f5f0, +- 0xf50002f8, +-/* 0x05b7: main_done */ +- 0xbdfede0e, +- 0x1f29f024, +- 0x02300080, +- 0xbd0002f6, +- 0xcc0ef504, +-/* 0x05c9: ih */ +- 0xfe80f9fe, +- 0x80f90188, +- 0xa0f990f9, +- 0xd0f9b0f9, +- 0xf0f9e0f9, +- 0x004a04bd, +- 0x00aacf02, +- 0xf404abc4, +- 0x100d230b, +- 0xcf1a004e, +- 0x004f00ee, +- 0x00ffcf19, +- 0x0000047e, +- 0x0400b0b7, +- 0x0040010e, +- 0x000ef61d, +-/* 0x060a: ih_no_fifo */ +- 0xabe404bd, +- 0x0bf40100, +- 0x4e100d0c, +- 0x047e4001, +-/* 0x061a: ih_no_ctxsw */ +- 0xabe40000, +- 0x0bf40400, +- 0x07088e56, +- 0x00657e40, +- 0x80ffb200, +- 0xf6020400, +- 0x04bd000f, +- 0x4007048e, +- 0x0000657e, +- 0x0080ffb2, +- 0x0ff60203, +- 0xc704bd00, +- 0xee9450fe, +- 0x07008f02, +- 0x00efbb40, +- 0x0000657e, +- 0x02020080, +- 0xbd000ff6, +- 0x7e030f04, +- 0x4b0002f8, +- 0xbfb20100, +- 0x4001448e, +- 0x00008f7e, +-/* 0x0674: ih_no_fwmthd */ +- 0xbd05044b, +- 0xb4abffb0, +- 0x800c0bf4, +- 0xf6030700, +- 0x04bd000b, +-/* 0x0688: ih_no_other */ +- 0xf6010040, +- 0x04bd000a, +- 0xe0fcf0fc, +- 0xb0fcd0fc, +- 0x90fca0fc, +- 0x88fe80fc, +- 0xf480fc00, +- 0x01f80032, +-/* 0x06a8: ctx_4170s */ +- 0xb210f5f0, +- 0x41708eff, +- 0x008f7e40, +-/* 0x06b7: ctx_4170w */ +- 0x8e00f800, +- 0x7e404170, +- 0xb2000065, +- 0x10f4f0ff, +- 0xf8f31bf4, +-/* 0x06c9: ctx_redswitch */ +- 0x02004e00, +- 0xf040e5f0, +- 0xe5f020e5, +- 0x85008010, +- 0x000ef601, +- 0x080f04bd, +-/* 0x06e0: ctx_redswitch_delay */ +- 0xf401f2b6, +- 0xe5f1fd1b, +- 0xe5f10400, +- 0x00800100, +- 0x0ef60185, +- 0xf804bd00, +-/* 0x06f9: ctx_86c */ +- 0x23008000, +- 0x000ff602, +- 0xffb204bd, +- 0x408a148e, +- 0x00008f7e, +- 0x8c8effb2, +- 0x8f7e41a8, +- 0x00f80000, +-/* 0x0718: ctx_mem */ +- 0x02840080, +- 0xbd000ff6, +-/* 0x0721: ctx_mem_wait */ +- 0x84008f04, +- 0x00ffcf02, +- 0xf405fffd, +- 0x00f8f61b, +-/* 0x0730: ctx_load */ +- 0x99f094bd, +- 0x37008005, +- 0x0009f602, +- 0x0c0a04bd, +- 0x0000b87e, +- 0x0080f4bd, +- 0x0ff60289, +- 0x8004bd00, +- 0xf602c100, +- 0x04bd0002, +- 0x02830080, +- 0xbd0002f6, +- 0x7e070f04, +- 0x80000718, +- 0xf602c000, +- 0x04bd0002, +- 0xf0000bfe, +- 0x24b61f2a, +- 0x0220b604, +- 0x99f094bd, +- 0x37008008, +- 0x0009f602, +- 0x008004bd, +- 0x02f60281, +- 0xd204bd00, +- 0x80000000, +- 0x800225f0, +- 0xf6028800, +- 0x04bd0002, +- 0x00421001, +- 0x0223f002, +- 0xf80512fa, +- 0xf094bd03, +- 0x00800899, +- 0x09f60217, +- 0x9804bd00, +- 0x14b68101, +- 0x80029818, +- 0xfd0825b6, +- 0x01b50512, +- 0xf094bd16, +- 0x00800999, +- 0x09f60237, +- 0x8004bd00, +- 0xf6028100, +- 0x04bd0001, +- 0x00800102, +- 0x02f60288, +- 0x4104bd00, +- 0x13f00100, +- 0x0501fa06, +- 0x94bd03f8, +- 0x800999f0, +- 0xf6021700, +- 0x04bd0009, +- 0x99f094bd, +- 0x17008005, +- 0x0009f602, +- 0x00f804bd, +-/* 0x081c: ctx_chan */ +- 0x0007307e, +- 0xb87e0c0a, +- 0x050f0000, +- 0x0007187e, +-/* 0x082e: ctx_mmio_exec */ +- 0x039800f8, +- 0x81008041, +- 0x0003f602, +- 0x34bd04bd, +-/* 0x083c: ctx_mmio_loop */ +- 0xf4ff34c4, +- 0x00450e1b, +- 0x0653f002, +- 0xf80535fa, +-/* 0x084d: ctx_mmio_pull */ +- 0x804e9803, +- 0x7e814f98, +- 0xb600008f, +- 0x12b60830, +- 0xdf1bf401, +-/* 0x0860: ctx_mmio_done */ +- 0x80160398, +- 0xf6028100, +- 0x04bd0003, +- 0x414000b5, +- 0x13f00100, +- 0x0601fa06, +- 0x00f803f8, +-/* 0x087c: ctx_xfer */ +- 0x0080040e, +- 0x0ef60302, +-/* 0x0887: ctx_xfer_idle */ +- 0x8e04bd00, +- 0xcf030000, +- 0xe4f100ee, +- 0x1bf42000, +- 0x0611f4f5, +-/* 0x089b: ctx_xfer_pre */ +- 0x0f0c02f4, +- 0x06f97e10, +- 0x1b11f400, +-/* 0x08a4: ctx_xfer_pre_load */ +- 0xa87e020f, +- 0xb77e0006, +- 0xc97e0006, +- 0xf4bd0006, +- 0x0006a87e, +- 0x0007307e, +-/* 0x08bc: ctx_xfer_exec */ +- 0xbd160198, +- 0x05008024, +- 0x0002f601, +- 0x1fb204bd, +- 0x41a5008e, +- 0x00008f7e, +- 0xf001fcf0, +- 0x24b6022c, +- 0x05f2fd01, +- 0x048effb2, +- 0x8f7e41a5, +- 0x167e0000, +- 0x24bd0002, +- 0x0247fc80, +- 0xbd0002f6, +- 0x012cf004, +- 0x800320b6, +- 0xf6024afc, +- 0x04bd0002, +- 0xf001acf0, +- 0x000b06a5, +- 0x98000c98, +- 0x000e010d, +- 0x00013d7e, +- 0xec7e080a, +- 0x0a7e0000, +- 0x01f40002, +- 0x7e0c0a12, +- 0x0f0000b8, +- 0x07187e05, +- 0x2d02f400, +-/* 0x0938: ctx_xfer_post */ +- 0xa87e020f, +- 0xf4bd0006, +- 0x0006f97e, +- 0x0002277e, +- 0x0006b77e, +- 0xa87ef4bd, +- 0x11f40006, +- 0x40019810, +- 0xf40511fd, +- 0x2e7e070b, +-/* 0x0962: ctx_xfer_no_post_mmio */ +-/* 0x0962: ctx_xfer_done */ +- 0x00f80008, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc +deleted file mode 100644 +index 3ff52bad..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define CHIPSET GF100 +-#include "macros.fuc" +- +-.section #nvc0_grhub_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "hub.fuc" +-#undef INCLUDE_DATA +- +-.section #nvc0_grhub_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "hub.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h +deleted file mode 100644 +index 92dfe6a4..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h ++++ /dev/null +@@ -1,1047 +0,0 @@ +-uint32_t nvc0_grhub_data[] = { +-/* 0x0000: hub_mmio_list_head */ +- 0x00000300, +-/* 0x0004: hub_mmio_list_tail */ +- 0x00000304, +-/* 0x0008: gpc_count */ +- 0x00000000, +-/* 0x000c: rop_count */ +- 0x00000000, +-/* 0x0010: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: ctx_current */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: chan_data */ +-/* 0x0100: chan_mmio_count */ +- 0x00000000, +-/* 0x0104: chan_mmio_address */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0200: xfer_data */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0300: hub_mmio_list_base */ +- 0x0417e91c, +-}; +- +-uint32_t nvc0_grhub_code[] = { +- 0x039b0ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0x07f100f8, +- 0x03f00500, +- 0x000fd002, +- 0xf7f004bd, +- 0x0007f101, +- 0x0303f007, +- 0xbd000fd0, +-/* 0x039b: init */ +- 0xbd00f804, +- 0x0007fe04, +- 0x420017f1, +- 0xcf0013f0, +- 0x11e70011, +- 0x14b60109, +- 0x0014fe08, +- 0xf10227f0, +- 0xf0120007, +- 0x02d00003, +- 0xf104bd00, +- 0xfe06c817, +- 0x24bd0010, +- 0x070007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0x200327f1, +- 0x010007f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200427f1, +- 0x010407f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200b27f1, +- 0x010807f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200c27f1, +- 0x011c07f1, +- 0xd00103f0, +- 0x04bd0002, +- 0xf1010392, +- 0xf0090007, +- 0x03d00303, +- 0xf104bd00, +- 0xf0870427, +- 0x07f10023, +- 0x03f00400, +- 0x0002d000, +- 0x27f004bd, +- 0x0007f104, +- 0x0003f003, +- 0xbd0002d0, +- 0x1031f404, +- 0x9604e7f1, +- 0xf440e3f0, +- 0xfeb96821, +- 0x90f1c702, +- 0xf0030180, +- 0x0f801ff4, +- 0x0117f002, +- 0xb6041fbb, +- 0x07f10112, +- 0x03f00300, +- 0x0001d001, +- 0x07f104bd, +- 0x03f00400, +- 0x0001d001, +- 0x17f104bd, +- 0xf7f00100, +- 0x0d21f502, +- 0x1f21f508, +- 0x10f7f008, +- 0x086c21f5, +- 0x98000e98, +- 0x21f5010f, +- 0x14950150, +- 0x0007f108, +- 0x0103f0c0, +- 0xbd0004d0, +- 0x0007f104, +- 0x0103f0c1, +- 0xbd0004d0, +- 0x0030b704, +- 0x001fbb13, +- 0xf102f5b6, +- 0xf0d30007, +- 0x0fd00103, +- 0xb604bd00, +- 0x10b60815, +- 0x0814b601, +- 0xf5021fb9, +- 0xbb02d321, +- 0x0398001f, +- 0x0047f102, +- 0x5043f020, +-/* 0x04f4: init_gpc */ +- 0x08044ea0, +- 0xf4021fb9, +- 0x4ea09d21, +- 0xf4bd010c, +- 0xa09d21f4, +- 0xf401044e, +- 0x4ea09d21, +- 0xf7f00100, +- 0x9d21f402, +- 0x08004ea0, +-/* 0x051c: init_gpc_wait */ +- 0xc86821f4, +- 0x0bf41fff, +- 0x044ea0fa, +- 0x6821f408, +- 0xb7001fbb, +- 0xb6800040, +- 0x1bf40132, +- 0x00f7f0be, +- 0x086c21f5, +- 0xf500f7f0, +- 0xf1080d21, +- 0xf0010007, +- 0x01d00203, +- 0xbd04bd00, +- 0x1f19f014, +- 0x080007f1, +- 0xd00203f0, +- 0x04bd0001, +-/* 0x0564: main */ +- 0xf40031f4, +- 0xd7f00028, +- 0x3921f410, +- 0xb1f401f4, +- 0xf54001e4, +- 0xbd00e91b, +- 0x0499f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xc00017f1, +- 0xcf0213f0, +- 0x27f10011, +- 0x23f0c100, +- 0x0022cf02, +- 0xf51f13c8, +- 0xc800890b, +- 0x0bf41f23, +- 0xb920f962, +- 0x94bd0212, +- 0xf10799f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf404bd00, +- 0x31f40132, +- 0x4021f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x20fc04bd, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0131f404, +- 0x0a4021f5, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f017, +- 0xbd0009d0, +- 0x330ef404, +-/* 0x060c: chsw_prev_no_next */ +- 0x12b920f9, +- 0x0132f402, +- 0xf50232f4, +- 0xfc0a4021, +- 0x0007f120, +- 0x0203f0c0, +- 0xbd0002d0, +- 0x130ef404, +-/* 0x062c: chsw_no_prev */ +- 0xf41f23c8, +- 0x31f40d0b, +- 0x0232f401, +- 0x0a4021f5, +-/* 0x063c: chsw_done */ +- 0xf10127f0, +- 0xf0c30007, +- 0x02d00203, +- 0xbd04bd00, +- 0x0499f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xff080ef5, +-/* 0x0660: main_not_ctx_switch */ +- 0xf401e4b0, +- 0xf2b90d1b, +- 0xd021f502, +- 0x460ef409, +-/* 0x0670: main_not_ctx_chan */ +- 0xf402e4b0, +- 0x94bd321b, +- 0xf10799f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf404bd00, +- 0x32f40132, +- 0x4021f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x0ef404bd, +-/* 0x06a5: main_not_ctx_save */ +- 0x10ef9411, +- 0xf501f5f0, +- 0xf5037e21, +-/* 0x06b3: main_done */ +- 0xbdfeb50e, +- 0x1f29f024, +- 0x080007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xfea00ef5, +-/* 0x06c8: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x10d7f030, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xb70421f4, +- 0xf00400b0, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x071a: ih_no_fifo */ +- 0xabe404bd, +- 0x0bf40100, +- 0x10d7f00d, +- 0x4001e7f1, +-/* 0x072b: ih_no_ctxsw */ +- 0xe40421f4, +- 0xf40400ab, +- 0xe7f16c0b, +- 0xe3f00708, +- 0x6821f440, +- 0xf102ffb9, +- 0xf0040007, +- 0x0fd00203, +- 0xf104bd00, +- 0xf00704e7, +- 0x21f440e3, +- 0x02ffb968, +- 0x030007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0x9450fec7, +- 0xf7f102ee, +- 0xf3f00700, +- 0x00efbb40, +- 0xf16821f4, +- 0xf0020007, +- 0x0fd00203, +- 0xf004bd00, +- 0x21f503f7, +- 0xb7f1037e, +- 0xbfb90100, +- 0x44e7f102, +- 0x40e3f001, +-/* 0x079b: ih_no_fwmthd */ +- 0xf19d21f4, +- 0xbd0504b7, +- 0xb4abffb0, +- 0xf10f0bf4, +- 0xf0070007, +- 0x0bd00303, +-/* 0x07b3: ih_no_other */ +- 0xf104bd00, +- 0xf0010007, +- 0x0ad00003, +- 0xfc04bd00, +- 0xfce0fcf0, +- 0xfcb0fcd0, +- 0xfc90fca0, +- 0x0088fe80, +- 0x32f480fc, +-/* 0x07d7: ctx_4160s */ +- 0xf001f800, +- 0xffb901f7, +- 0x60e7f102, +- 0x40e3f041, +-/* 0x07e7: ctx_4160s_wait */ +- 0xf19d21f4, +- 0xf04160e7, +- 0x21f440e3, +- 0x02ffb968, +- 0xf404ffc8, +- 0x00f8f00b, +-/* 0x07fc: ctx_4160c */ +- 0xffb9f4bd, +- 0x60e7f102, +- 0x40e3f041, +- 0xf89d21f4, +-/* 0x080d: ctx_4170s */ +- 0x10f5f000, +- 0xf102ffb9, +- 0xf04170e7, +- 0x21f440e3, +-/* 0x081f: ctx_4170w */ +- 0xf100f89d, +- 0xf04170e7, +- 0x21f440e3, +- 0x02ffb968, +- 0xf410f4f0, +- 0x00f8f01b, +-/* 0x0834: ctx_redswitch */ +- 0x0200e7f1, +- 0xf040e5f0, +- 0xe5f020e5, +- 0x0007f110, +- 0x0103f085, +- 0xbd000ed0, +- 0x08f7f004, +-/* 0x0850: ctx_redswitch_delay */ +- 0xf401f2b6, +- 0xe5f1fd1b, +- 0xe5f10400, +- 0x07f10100, +- 0x03f08500, +- 0x000ed001, +- 0x00f804bd, +-/* 0x086c: ctx_86c */ +- 0x1b0007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0xf102ffb9, +- 0xf08a14e7, +- 0x21f440e3, +- 0x02ffb99d, +- 0xa86ce7f1, +- 0xf441e3f0, +- 0x00f89d21, +-/* 0x0894: ctx_mem */ +- 0x840007f1, +- 0xd00203f0, +- 0x04bd000f, +-/* 0x08a0: ctx_mem_wait */ +- 0x8400f7f1, +- 0xcf02f3f0, +- 0xfffd00ff, +- 0xf31bf405, +-/* 0x08b2: ctx_load */ +- 0x94bd00f8, +- 0xf10599f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf004bd00, +- 0x21f40ca7, +- 0xf1f4bdd0, +- 0xf0890007, +- 0x0fd00203, +- 0xf104bd00, +- 0xf0c10007, +- 0x02d00203, +- 0xf104bd00, +- 0xf0830007, +- 0x02d00203, +- 0xf004bd00, +- 0x21f507f7, +- 0x07f10894, +- 0x03f0c000, +- 0x0002d002, +- 0x0bfe04bd, +- 0x1f2af000, +- 0xb60424b6, +- 0x94bd0220, +- 0xf10899f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf104bd00, +- 0xf0810007, +- 0x02d00203, +- 0xf104bd00, +- 0xf1000027, +- 0xf0800023, +- 0x07f10225, +- 0x03f08800, +- 0x0002d002, +- 0x17f004bd, +- 0x0027f110, +- 0x0223f002, +- 0xf80512fa, +- 0xf094bd03, +- 0x07f10899, +- 0x03f01700, +- 0x0009d002, +- 0x019804bd, +- 0x1814b681, +- 0xb6800298, +- 0x12fd0825, +- 0x16018005, +- 0x99f094bd, +- 0x0007f109, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f081, +- 0xbd0001d0, +- 0x0127f004, +- 0x880007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0x010017f1, +- 0xfa0613f0, +- 0x03f80501, +- 0x99f094bd, +- 0x0007f109, +- 0x0203f017, +- 0xbd0009d0, +- 0xf094bd04, +- 0x07f10599, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x09d0: ctx_chan */ +- 0x07d721f5, +- 0x08b221f5, +- 0xf40ca7f0, +- 0xf7f0d021, +- 0x9421f505, +- 0xfc21f508, +-/* 0x09eb: ctx_mmio_exec */ +- 0x9800f807, +- 0x07f14103, +- 0x03f08100, +- 0x0003d002, +- 0x34bd04bd, +-/* 0x09fc: ctx_mmio_loop */ +- 0xf4ff34c4, +- 0x57f10f1b, +- 0x53f00200, +- 0x0535fa06, +-/* 0x0a0e: ctx_mmio_pull */ +- 0x4e9803f8, +- 0x814f9880, +- 0xb69d21f4, +- 0x12b60830, +- 0xdf1bf401, +-/* 0x0a20: ctx_mmio_done */ +- 0xf1160398, +- 0xf0810007, +- 0x03d00203, +- 0x8004bd00, +- 0x17f14000, +- 0x13f00100, +- 0x0601fa06, +- 0x00f803f8, +-/* 0x0a40: ctx_xfer */ +- 0xf104e7f0, +- 0xf0020007, +- 0x0ed00303, +-/* 0x0a4f: ctx_xfer_idle */ +- 0xf104bd00, +- 0xf00000e7, +- 0xeecf03e3, +- 0x00e4f100, +- 0xf21bf420, +- 0xf40611f4, +-/* 0x0a66: ctx_xfer_pre */ +- 0xf7f01102, +- 0x6c21f510, +- 0xd721f508, +- 0x1c11f407, +-/* 0x0a74: ctx_xfer_pre_load */ +- 0xf502f7f0, +- 0xf5080d21, +- 0xf5081f21, +- 0xbd083421, +- 0x0d21f5f4, +- 0xb221f508, +-/* 0x0a8d: ctx_xfer_exec */ +- 0x16019808, +- 0x07f124bd, +- 0x03f00500, +- 0x0002d001, +- 0x1fb904bd, +- 0x00e7f102, +- 0x41e3f0a5, +- 0xf09d21f4, +- 0x2cf001fc, +- 0x0124b602, +- 0xb905f2fd, +- 0xe7f102ff, +- 0xe3f0a504, +- 0x9d21f441, +- 0x026a21f5, +- 0x07f124bd, +- 0x03f047fc, +- 0x0002d002, +- 0x2cf004bd, +- 0x0320b601, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xf001acf0, +- 0xb7f006a5, +- 0x000c9800, +- 0xf0010d98, +- 0x21f500e7, +- 0xa7f0016f, +- 0x1021f508, +- 0x5e21f501, +- 0x1301f402, +- 0xf40ca7f0, +- 0xf7f0d021, +- 0x9421f505, +- 0x3202f408, +-/* 0x0b1c: ctx_xfer_post */ +- 0xf502f7f0, +- 0xbd080d21, +- 0x6c21f5f4, +- 0x7f21f508, +- 0x1f21f502, +- 0xf5f4bd08, +- 0xf4080d21, +- 0x01981011, +- 0x0511fd40, +- 0xf5070bf4, +-/* 0x0b47: ctx_xfer_no_post_mmio */ +- 0xf509eb21, +-/* 0x0b4b: ctx_xfer_done */ +- 0xf807fc21, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc +deleted file mode 100644 +index afbe03ac..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define CHIPSET GF117 +-#include "macros.fuc" +- +-.section #nvd7_grhub_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "hub.fuc" +-#undef INCLUDE_DATA +- +-.section #nvd7_grhub_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "hub.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h +deleted file mode 100644 +index 62b0c760..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvd7.fuc.h ++++ /dev/null +@@ -1,1047 +0,0 @@ +-uint32_t nvd7_grhub_data[] = { +-/* 0x0000: hub_mmio_list_head */ +- 0x00000300, +-/* 0x0004: hub_mmio_list_tail */ +- 0x00000304, +-/* 0x0008: gpc_count */ +- 0x00000000, +-/* 0x000c: rop_count */ +- 0x00000000, +-/* 0x0010: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: ctx_current */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: chan_data */ +-/* 0x0100: chan_mmio_count */ +- 0x00000000, +-/* 0x0104: chan_mmio_address */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0200: xfer_data */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0300: hub_mmio_list_base */ +- 0x0417e91c, +-}; +- +-uint32_t nvd7_grhub_code[] = { +- 0x039b0ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0x07f100f8, +- 0x03f00500, +- 0x000fd002, +- 0xf7f004bd, +- 0x0007f101, +- 0x0303f007, +- 0xbd000fd0, +-/* 0x039b: init */ +- 0xbd00f804, +- 0x0007fe04, +- 0x420017f1, +- 0xcf0013f0, +- 0x11e70011, +- 0x14b60109, +- 0x0014fe08, +- 0xf10227f0, +- 0xf0120007, +- 0x02d00003, +- 0xf104bd00, +- 0xfe06c817, +- 0x24bd0010, +- 0x070007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0x200327f1, +- 0x010007f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200427f1, +- 0x010407f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200b27f1, +- 0x010807f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200c27f1, +- 0x011c07f1, +- 0xd00103f0, +- 0x04bd0002, +- 0xf1010392, +- 0xf0090007, +- 0x03d00303, +- 0xf104bd00, +- 0xf0870427, +- 0x07f10023, +- 0x03f00400, +- 0x0002d000, +- 0x27f004bd, +- 0x0007f104, +- 0x0003f003, +- 0xbd0002d0, +- 0x1031f404, +- 0x9604e7f1, +- 0xf440e3f0, +- 0xfeb96821, +- 0x90f1c702, +- 0xf0030180, +- 0x0f801ff4, +- 0x0117f002, +- 0xb6041fbb, +- 0x07f10112, +- 0x03f00300, +- 0x0001d001, +- 0x07f104bd, +- 0x03f00400, +- 0x0001d001, +- 0x17f104bd, +- 0xf7f00100, +- 0x0d21f502, +- 0x1f21f508, +- 0x10f7f008, +- 0x086c21f5, +- 0x98000e98, +- 0x21f5010f, +- 0x14950150, +- 0x0007f108, +- 0x0103f0c0, +- 0xbd0004d0, +- 0x0007f104, +- 0x0103f0c1, +- 0xbd0004d0, +- 0x0030b704, +- 0x001fbb13, +- 0xf102f5b6, +- 0xf0d30007, +- 0x0fd00103, +- 0xb604bd00, +- 0x10b60815, +- 0x0814b601, +- 0xf5021fb9, +- 0xbb02d321, +- 0x0398001f, +- 0x0047f102, +- 0x5043f020, +-/* 0x04f4: init_gpc */ +- 0x08044ea0, +- 0xf4021fb9, +- 0x4ea09d21, +- 0xf4bd010c, +- 0xa09d21f4, +- 0xf401044e, +- 0x4ea09d21, +- 0xf7f00100, +- 0x9d21f402, +- 0x08004ea0, +-/* 0x051c: init_gpc_wait */ +- 0xc86821f4, +- 0x0bf41fff, +- 0x044ea0fa, +- 0x6821f408, +- 0xb7001fbb, +- 0xb6800040, +- 0x1bf40132, +- 0x00f7f0be, +- 0x086c21f5, +- 0xf500f7f0, +- 0xf1080d21, +- 0xf0010007, +- 0x01d00203, +- 0xbd04bd00, +- 0x1f19f014, +- 0x080007f1, +- 0xd00203f0, +- 0x04bd0001, +-/* 0x0564: main */ +- 0xf40031f4, +- 0xd7f00028, +- 0x3921f410, +- 0xb1f401f4, +- 0xf54001e4, +- 0xbd00e91b, +- 0x0499f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xc00017f1, +- 0xcf0213f0, +- 0x27f10011, +- 0x23f0c100, +- 0x0022cf02, +- 0xf51f13c8, +- 0xc800890b, +- 0x0bf41f23, +- 0xb920f962, +- 0x94bd0212, +- 0xf10799f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf404bd00, +- 0x31f40132, +- 0x4021f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x20fc04bd, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0131f404, +- 0x0a4021f5, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f017, +- 0xbd0009d0, +- 0x330ef404, +-/* 0x060c: chsw_prev_no_next */ +- 0x12b920f9, +- 0x0132f402, +- 0xf50232f4, +- 0xfc0a4021, +- 0x0007f120, +- 0x0203f0c0, +- 0xbd0002d0, +- 0x130ef404, +-/* 0x062c: chsw_no_prev */ +- 0xf41f23c8, +- 0x31f40d0b, +- 0x0232f401, +- 0x0a4021f5, +-/* 0x063c: chsw_done */ +- 0xf10127f0, +- 0xf0c30007, +- 0x02d00203, +- 0xbd04bd00, +- 0x0499f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xff080ef5, +-/* 0x0660: main_not_ctx_switch */ +- 0xf401e4b0, +- 0xf2b90d1b, +- 0xd021f502, +- 0x460ef409, +-/* 0x0670: main_not_ctx_chan */ +- 0xf402e4b0, +- 0x94bd321b, +- 0xf10799f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf404bd00, +- 0x32f40132, +- 0x4021f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x0ef404bd, +-/* 0x06a5: main_not_ctx_save */ +- 0x10ef9411, +- 0xf501f5f0, +- 0xf5037e21, +-/* 0x06b3: main_done */ +- 0xbdfeb50e, +- 0x1f29f024, +- 0x080007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xfea00ef5, +-/* 0x06c8: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x10d7f030, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xb70421f4, +- 0xf00400b0, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x071a: ih_no_fifo */ +- 0xabe404bd, +- 0x0bf40100, +- 0x10d7f00d, +- 0x4001e7f1, +-/* 0x072b: ih_no_ctxsw */ +- 0xe40421f4, +- 0xf40400ab, +- 0xe7f16c0b, +- 0xe3f00708, +- 0x6821f440, +- 0xf102ffb9, +- 0xf0040007, +- 0x0fd00203, +- 0xf104bd00, +- 0xf00704e7, +- 0x21f440e3, +- 0x02ffb968, +- 0x030007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0x9450fec7, +- 0xf7f102ee, +- 0xf3f00700, +- 0x00efbb40, +- 0xf16821f4, +- 0xf0020007, +- 0x0fd00203, +- 0xf004bd00, +- 0x21f503f7, +- 0xb7f1037e, +- 0xbfb90100, +- 0x44e7f102, +- 0x40e3f001, +-/* 0x079b: ih_no_fwmthd */ +- 0xf19d21f4, +- 0xbd0504b7, +- 0xb4abffb0, +- 0xf10f0bf4, +- 0xf0070007, +- 0x0bd00303, +-/* 0x07b3: ih_no_other */ +- 0xf104bd00, +- 0xf0010007, +- 0x0ad00003, +- 0xfc04bd00, +- 0xfce0fcf0, +- 0xfcb0fcd0, +- 0xfc90fca0, +- 0x0088fe80, +- 0x32f480fc, +-/* 0x07d7: ctx_4160s */ +- 0xf001f800, +- 0xffb901f7, +- 0x60e7f102, +- 0x40e3f041, +-/* 0x07e7: ctx_4160s_wait */ +- 0xf19d21f4, +- 0xf04160e7, +- 0x21f440e3, +- 0x02ffb968, +- 0xf404ffc8, +- 0x00f8f00b, +-/* 0x07fc: ctx_4160c */ +- 0xffb9f4bd, +- 0x60e7f102, +- 0x40e3f041, +- 0xf89d21f4, +-/* 0x080d: ctx_4170s */ +- 0x10f5f000, +- 0xf102ffb9, +- 0xf04170e7, +- 0x21f440e3, +-/* 0x081f: ctx_4170w */ +- 0xf100f89d, +- 0xf04170e7, +- 0x21f440e3, +- 0x02ffb968, +- 0xf410f4f0, +- 0x00f8f01b, +-/* 0x0834: ctx_redswitch */ +- 0x0200e7f1, +- 0xf040e5f0, +- 0xe5f020e5, +- 0x0007f110, +- 0x0103f085, +- 0xbd000ed0, +- 0x08f7f004, +-/* 0x0850: ctx_redswitch_delay */ +- 0xf401f2b6, +- 0xe5f1fd1b, +- 0xe5f10400, +- 0x07f10100, +- 0x03f08500, +- 0x000ed001, +- 0x00f804bd, +-/* 0x086c: ctx_86c */ +- 0x1b0007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0xf102ffb9, +- 0xf08a14e7, +- 0x21f440e3, +- 0x02ffb99d, +- 0xa86ce7f1, +- 0xf441e3f0, +- 0x00f89d21, +-/* 0x0894: ctx_mem */ +- 0x840007f1, +- 0xd00203f0, +- 0x04bd000f, +-/* 0x08a0: ctx_mem_wait */ +- 0x8400f7f1, +- 0xcf02f3f0, +- 0xfffd00ff, +- 0xf31bf405, +-/* 0x08b2: ctx_load */ +- 0x94bd00f8, +- 0xf10599f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf004bd00, +- 0x21f40ca7, +- 0xf1f4bdd0, +- 0xf0890007, +- 0x0fd00203, +- 0xf104bd00, +- 0xf0c10007, +- 0x02d00203, +- 0xf104bd00, +- 0xf0830007, +- 0x02d00203, +- 0xf004bd00, +- 0x21f507f7, +- 0x07f10894, +- 0x03f0c000, +- 0x0002d002, +- 0x0bfe04bd, +- 0x1f2af000, +- 0xb60424b6, +- 0x94bd0220, +- 0xf10899f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf104bd00, +- 0xf0810007, +- 0x02d00203, +- 0xf104bd00, +- 0xf1000027, +- 0xf0800023, +- 0x07f10225, +- 0x03f08800, +- 0x0002d002, +- 0x17f004bd, +- 0x0027f110, +- 0x0223f002, +- 0xf80512fa, +- 0xf094bd03, +- 0x07f10899, +- 0x03f01700, +- 0x0009d002, +- 0x019804bd, +- 0x1814b681, +- 0xb6800298, +- 0x12fd0825, +- 0x16018005, +- 0x99f094bd, +- 0x0007f109, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f081, +- 0xbd0001d0, +- 0x0127f004, +- 0x880007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0x010017f1, +- 0xfa0613f0, +- 0x03f80501, +- 0x99f094bd, +- 0x0007f109, +- 0x0203f017, +- 0xbd0009d0, +- 0xf094bd04, +- 0x07f10599, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x09d0: ctx_chan */ +- 0x07d721f5, +- 0x08b221f5, +- 0xf40ca7f0, +- 0xf7f0d021, +- 0x9421f505, +- 0xfc21f508, +-/* 0x09eb: ctx_mmio_exec */ +- 0x9800f807, +- 0x07f14103, +- 0x03f08100, +- 0x0003d002, +- 0x34bd04bd, +-/* 0x09fc: ctx_mmio_loop */ +- 0xf4ff34c4, +- 0x57f10f1b, +- 0x53f00200, +- 0x0535fa06, +-/* 0x0a0e: ctx_mmio_pull */ +- 0x4e9803f8, +- 0x814f9880, +- 0xb69d21f4, +- 0x12b60830, +- 0xdf1bf401, +-/* 0x0a20: ctx_mmio_done */ +- 0xf1160398, +- 0xf0810007, +- 0x03d00203, +- 0x8004bd00, +- 0x17f14000, +- 0x13f00100, +- 0x0601fa06, +- 0x00f803f8, +-/* 0x0a40: ctx_xfer */ +- 0xf104e7f0, +- 0xf0020007, +- 0x0ed00303, +-/* 0x0a4f: ctx_xfer_idle */ +- 0xf104bd00, +- 0xf00000e7, +- 0xeecf03e3, +- 0x00e4f100, +- 0xf21bf420, +- 0xf40611f4, +-/* 0x0a66: ctx_xfer_pre */ +- 0xf7f01102, +- 0x6c21f510, +- 0xd721f508, +- 0x1c11f407, +-/* 0x0a74: ctx_xfer_pre_load */ +- 0xf502f7f0, +- 0xf5080d21, +- 0xf5081f21, +- 0xbd083421, +- 0x0d21f5f4, +- 0xb221f508, +-/* 0x0a8d: ctx_xfer_exec */ +- 0x16019808, +- 0x07f124bd, +- 0x03f00500, +- 0x0002d001, +- 0x1fb904bd, +- 0x00e7f102, +- 0x41e3f0a5, +- 0xf09d21f4, +- 0x2cf001fc, +- 0x0124b602, +- 0xb905f2fd, +- 0xe7f102ff, +- 0xe3f0a504, +- 0x9d21f441, +- 0x026a21f5, +- 0x07f124bd, +- 0x03f047fc, +- 0x0002d002, +- 0x2cf004bd, +- 0x0320b601, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xf001acf0, +- 0xb7f006a5, +- 0x000c9800, +- 0xf0010d98, +- 0x21f500e7, +- 0xa7f0016f, +- 0x1021f508, +- 0x5e21f501, +- 0x1301f402, +- 0xf40ca7f0, +- 0xf7f0d021, +- 0x9421f505, +- 0x3202f408, +-/* 0x0b1c: ctx_xfer_post */ +- 0xf502f7f0, +- 0xbd080d21, +- 0x6c21f5f4, +- 0x7f21f508, +- 0x1f21f502, +- 0xf5f4bd08, +- 0xf4080d21, +- 0x01981011, +- 0x0511fd40, +- 0xf5070bf4, +-/* 0x0b47: ctx_xfer_no_post_mmio */ +- 0xf509eb21, +-/* 0x0b4b: ctx_xfer_done */ +- 0xf807fc21, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc +deleted file mode 100644 +index d4840f18..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define CHIPSET GK100 +-#include "macros.fuc" +- +-.section #nve0_grhub_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "hub.fuc" +-#undef INCLUDE_DATA +- +-.section #nve0_grhub_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "hub.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h +deleted file mode 100644 +index 51c3797d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnve0.fuc.h ++++ /dev/null +@@ -1,1044 +0,0 @@ +-uint32_t nve0_grhub_data[] = { +-/* 0x0000: hub_mmio_list_head */ +- 0x00000300, +-/* 0x0004: hub_mmio_list_tail */ +- 0x00000304, +-/* 0x0008: gpc_count */ +- 0x00000000, +-/* 0x000c: rop_count */ +- 0x00000000, +-/* 0x0010: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: ctx_current */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: chan_data */ +-/* 0x0100: chan_mmio_count */ +- 0x00000000, +-/* 0x0104: chan_mmio_address */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0200: xfer_data */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0300: hub_mmio_list_base */ +- 0x0417e91c, +-}; +- +-uint32_t nve0_grhub_code[] = { +- 0x039b0ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0x07f100f8, +- 0x03f00500, +- 0x000fd002, +- 0xf7f004bd, +- 0x0007f101, +- 0x0303f007, +- 0xbd000fd0, +-/* 0x039b: init */ +- 0xbd00f804, +- 0x0007fe04, +- 0x420017f1, +- 0xcf0013f0, +- 0x11e70011, +- 0x14b60109, +- 0x0014fe08, +- 0xf10227f0, +- 0xf0120007, +- 0x02d00003, +- 0xf104bd00, +- 0xfe06c817, +- 0x24bd0010, +- 0x070007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0x200327f1, +- 0x010007f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200427f1, +- 0x010407f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200b27f1, +- 0x010807f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200c27f1, +- 0x011c07f1, +- 0xd00103f0, +- 0x04bd0002, +- 0xf1010392, +- 0xf0090007, +- 0x03d00303, +- 0xf104bd00, +- 0xf0870427, +- 0x07f10023, +- 0x03f00400, +- 0x0002d000, +- 0x27f004bd, +- 0x0007f104, +- 0x0003f003, +- 0xbd0002d0, +- 0x1031f404, +- 0x9604e7f1, +- 0xf440e3f0, +- 0xfeb96821, +- 0x90f1c702, +- 0xf0030180, +- 0x0f801ff4, +- 0x0117f002, +- 0xb6041fbb, +- 0x07f10112, +- 0x03f00300, +- 0x0001d001, +- 0x07f104bd, +- 0x03f00400, +- 0x0001d001, +- 0x17f104bd, +- 0xf7f00100, +- 0xd721f502, +- 0xe921f507, +- 0x10f7f007, +- 0x083621f5, +- 0x98000e98, +- 0x21f5010f, +- 0x14950150, +- 0x0007f108, +- 0x0103f0c0, +- 0xbd0004d0, +- 0x0007f104, +- 0x0103f0c1, +- 0xbd0004d0, +- 0x0030b704, +- 0x001fbb13, +- 0xf102f5b6, +- 0xf0d30007, +- 0x0fd00103, +- 0xb604bd00, +- 0x10b60815, +- 0x0814b601, +- 0xf5021fb9, +- 0xbb02d321, +- 0x0398001f, +- 0x0047f102, +- 0x5043f020, +-/* 0x04f4: init_gpc */ +- 0x08044ea0, +- 0xf4021fb9, +- 0x4ea09d21, +- 0xf4bd010c, +- 0xa09d21f4, +- 0xf401044e, +- 0x4ea09d21, +- 0xf7f00100, +- 0x9d21f402, +- 0x08004ea0, +-/* 0x051c: init_gpc_wait */ +- 0xc86821f4, +- 0x0bf41fff, +- 0x044ea0fa, +- 0x6821f408, +- 0xb7001fbb, +- 0xb6800040, +- 0x1bf40132, +- 0x00f7f0be, +- 0x083621f5, +- 0xf500f7f0, +- 0xf107d721, +- 0xf0010007, +- 0x01d00203, +- 0xbd04bd00, +- 0x1f19f014, +- 0x080007f1, +- 0xd00203f0, +- 0x04bd0001, +-/* 0x0564: main */ +- 0xf40031f4, +- 0xd7f00028, +- 0x3921f410, +- 0xb1f401f4, +- 0xf54001e4, +- 0xbd00e91b, +- 0x0499f094, +- 0x0f0007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xc00017f1, +- 0xcf0213f0, +- 0x27f10011, +- 0x23f0c100, +- 0x0022cf02, +- 0xf51f13c8, +- 0xc800890b, +- 0x0bf41f23, +- 0xb920f962, +- 0x94bd0212, +- 0xf10799f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf404bd00, +- 0x31f40132, +- 0x0221f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x20fc04bd, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0131f404, +- 0x0a0221f5, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f017, +- 0xbd0009d0, +- 0x330ef404, +-/* 0x060c: chsw_prev_no_next */ +- 0x12b920f9, +- 0x0132f402, +- 0xf50232f4, +- 0xfc0a0221, +- 0x0007f120, +- 0x0203f0c0, +- 0xbd0002d0, +- 0x130ef404, +-/* 0x062c: chsw_no_prev */ +- 0xf41f23c8, +- 0x31f40d0b, +- 0x0232f401, +- 0x0a0221f5, +-/* 0x063c: chsw_done */ +- 0xf10127f0, +- 0xf0c30007, +- 0x02d00203, +- 0xbd04bd00, +- 0x0499f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xff080ef5, +-/* 0x0660: main_not_ctx_switch */ +- 0xf401e4b0, +- 0xf2b90d1b, +- 0x9a21f502, +- 0x460ef409, +-/* 0x0670: main_not_ctx_chan */ +- 0xf402e4b0, +- 0x94bd321b, +- 0xf10799f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf404bd00, +- 0x32f40132, +- 0x0221f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x0ef404bd, +-/* 0x06a5: main_not_ctx_save */ +- 0x10ef9411, +- 0xf501f5f0, +- 0xf5037e21, +-/* 0x06b3: main_done */ +- 0xbdfeb50e, +- 0x1f29f024, +- 0x080007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xfea00ef5, +-/* 0x06c8: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x10d7f030, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xb70421f4, +- 0xf00400b0, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x071a: ih_no_fifo */ +- 0xabe404bd, +- 0x0bf40100, +- 0x10d7f00d, +- 0x4001e7f1, +-/* 0x072b: ih_no_ctxsw */ +- 0xe40421f4, +- 0xf40400ab, +- 0xe7f16c0b, +- 0xe3f00708, +- 0x6821f440, +- 0xf102ffb9, +- 0xf0040007, +- 0x0fd00203, +- 0xf104bd00, +- 0xf00704e7, +- 0x21f440e3, +- 0x02ffb968, +- 0x030007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0x9450fec7, +- 0xf7f102ee, +- 0xf3f00700, +- 0x00efbb40, +- 0xf16821f4, +- 0xf0020007, +- 0x0fd00203, +- 0xf004bd00, +- 0x21f503f7, +- 0xb7f1037e, +- 0xbfb90100, +- 0x44e7f102, +- 0x40e3f001, +-/* 0x079b: ih_no_fwmthd */ +- 0xf19d21f4, +- 0xbd0504b7, +- 0xb4abffb0, +- 0xf10f0bf4, +- 0xf0070007, +- 0x0bd00303, +-/* 0x07b3: ih_no_other */ +- 0xf104bd00, +- 0xf0010007, +- 0x0ad00003, +- 0xfc04bd00, +- 0xfce0fcf0, +- 0xfcb0fcd0, +- 0xfc90fca0, +- 0x0088fe80, +- 0x32f480fc, +-/* 0x07d7: ctx_4170s */ +- 0xf001f800, +- 0xffb910f5, +- 0x70e7f102, +- 0x40e3f041, +- 0xf89d21f4, +-/* 0x07e9: ctx_4170w */ +- 0x70e7f100, +- 0x40e3f041, +- 0xb96821f4, +- 0xf4f002ff, +- 0xf01bf410, +-/* 0x07fe: ctx_redswitch */ +- 0xe7f100f8, +- 0xe5f00200, +- 0x20e5f040, +- 0xf110e5f0, +- 0xf0850007, +- 0x0ed00103, +- 0xf004bd00, +-/* 0x081a: ctx_redswitch_delay */ +- 0xf2b608f7, +- 0xfd1bf401, +- 0x0400e5f1, +- 0x0100e5f1, +- 0x850007f1, +- 0xd00103f0, +- 0x04bd000e, +-/* 0x0836: ctx_86c */ +- 0x07f100f8, +- 0x03f01b00, +- 0x000fd002, +- 0xffb904bd, +- 0x14e7f102, +- 0x40e3f08a, +- 0xb99d21f4, +- 0xe7f102ff, +- 0xe3f0a86c, +- 0x9d21f441, +-/* 0x085e: ctx_mem */ +- 0x07f100f8, +- 0x03f08400, +- 0x000fd002, +-/* 0x086a: ctx_mem_wait */ +- 0xf7f104bd, +- 0xf3f08400, +- 0x00ffcf02, +- 0xf405fffd, +- 0x00f8f31b, +-/* 0x087c: ctx_load */ +- 0x99f094bd, +- 0x0007f105, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0ca7f004, +- 0xbdd021f4, +- 0x0007f1f4, +- 0x0203f089, +- 0xbd000fd0, +- 0x0007f104, +- 0x0203f0c1, +- 0xbd0002d0, +- 0x0007f104, +- 0x0203f083, +- 0xbd0002d0, +- 0x07f7f004, +- 0x085e21f5, +- 0xc00007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xf0000bfe, +- 0x24b61f2a, +- 0x0220b604, +- 0x99f094bd, +- 0x0007f108, +- 0x0203f00f, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f081, +- 0xbd0002d0, +- 0x0027f104, +- 0x0023f100, +- 0x0225f080, +- 0x880007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xf11017f0, +- 0xf0020027, +- 0x12fa0223, +- 0xbd03f805, +- 0x0899f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xb6810198, +- 0x02981814, +- 0x0825b680, +- 0x800512fd, +- 0x94bd1601, +- 0xf10999f0, +- 0xf00f0007, +- 0x09d00203, +- 0xf104bd00, +- 0xf0810007, +- 0x01d00203, +- 0xf004bd00, +- 0x07f10127, +- 0x03f08800, +- 0x0002d002, +- 0x17f104bd, +- 0x13f00100, +- 0x0501fa06, +- 0x94bd03f8, +- 0xf10999f0, +- 0xf0170007, +- 0x09d00203, +- 0xbd04bd00, +- 0x0599f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x099a: ctx_chan */ +- 0x21f500f8, +- 0xa7f0087c, +- 0xd021f40c, +- 0xf505f7f0, +- 0xf8085e21, +-/* 0x09ad: ctx_mmio_exec */ +- 0x41039800, +- 0x810007f1, +- 0xd00203f0, +- 0x04bd0003, +-/* 0x09be: ctx_mmio_loop */ +- 0x34c434bd, +- 0x0f1bf4ff, +- 0x020057f1, +- 0xfa0653f0, +- 0x03f80535, +-/* 0x09d0: ctx_mmio_pull */ +- 0x98804e98, +- 0x21f4814f, +- 0x0830b69d, +- 0xf40112b6, +-/* 0x09e2: ctx_mmio_done */ +- 0x0398df1b, +- 0x0007f116, +- 0x0203f081, +- 0xbd0003d0, +- 0x40008004, +- 0x010017f1, +- 0xfa0613f0, +- 0x03f80601, +-/* 0x0a02: ctx_xfer */ +- 0xe7f000f8, +- 0x0007f104, +- 0x0303f002, +- 0xbd000ed0, +-/* 0x0a11: ctx_xfer_idle */ +- 0x00e7f104, +- 0x03e3f000, +- 0xf100eecf, +- 0xf42000e4, +- 0x11f4f21b, +- 0x0d02f406, +-/* 0x0a28: ctx_xfer_pre */ +- 0xf510f7f0, +- 0xf4083621, +-/* 0x0a32: ctx_xfer_pre_load */ +- 0xf7f01c11, +- 0xd721f502, +- 0xe921f507, +- 0xfe21f507, +- 0xf5f4bd07, +- 0xf507d721, +-/* 0x0a4b: ctx_xfer_exec */ +- 0x98087c21, +- 0x24bd1601, +- 0x050007f1, +- 0xd00103f0, +- 0x04bd0002, +- 0xf1021fb9, +- 0xf0a500e7, +- 0x21f441e3, +- 0x01fcf09d, +- 0xb6022cf0, +- 0xf2fd0124, +- 0x02ffb905, +- 0xa504e7f1, +- 0xf441e3f0, +- 0x21f59d21, +- 0x24bd026a, +- 0x47fc07f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xb6012cf0, +- 0x07f10320, +- 0x03f04afc, +- 0x0002d002, +- 0xacf004bd, +- 0x06a5f001, +- 0x9800b7f0, +- 0x0d98000c, +- 0x00e7f001, +- 0x016f21f5, +- 0xf508a7f0, +- 0xf5011021, +- 0xf4025e21, +- 0xa7f01301, +- 0xd021f40c, +- 0xf505f7f0, +- 0xf4085e21, +-/* 0x0ada: ctx_xfer_post */ +- 0xf7f02e02, +- 0xd721f502, +- 0xf5f4bd07, +- 0xf5083621, +- 0xf5027f21, +- 0xbd07e921, +- 0xd721f5f4, +- 0x1011f407, +- 0xfd400198, +- 0x0bf40511, +- 0xad21f507, +-/* 0x0b05: ctx_xfer_no_post_mmio */ +-/* 0x0b05: ctx_xfer_done */ +- 0x0000f809, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc +deleted file mode 100644 +index ec42ed29..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define CHIPSET GK110 +-#include "macros.fuc" +- +-.section #nvf0_grhub_data +-#define INCLUDE_DATA +-#include "com.fuc" +-#include "hub.fuc" +-#undef INCLUDE_DATA +- +-.section #nvf0_grhub_code +-#define INCLUDE_CODE +-bra #init +-#include "com.fuc" +-#include "hub.fuc" +-.align 256 +-#undef INCLUDE_CODE +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h +deleted file mode 100644 +index a0af4b70..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvf0.fuc.h ++++ /dev/null +@@ -1,1044 +0,0 @@ +-uint32_t nvf0_grhub_data[] = { +-/* 0x0000: hub_mmio_list_head */ +- 0x00000300, +-/* 0x0004: hub_mmio_list_tail */ +- 0x00000304, +-/* 0x0008: gpc_count */ +- 0x00000000, +-/* 0x000c: rop_count */ +- 0x00000000, +-/* 0x0010: cmd_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: ctx_current */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0100: chan_data */ +-/* 0x0100: chan_mmio_count */ +- 0x00000000, +-/* 0x0104: chan_mmio_address */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0200: xfer_data */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0300: hub_mmio_list_base */ +- 0x0417e91c, +-}; +- +-uint32_t nvf0_grhub_code[] = { +- 0x039b0ef5, +-/* 0x0004: queue_put */ +- 0x9800d898, +- 0x86f001d9, +- 0x0489b808, +- 0xf00c1bf4, +- 0x21f502f7, +- 0x00f8037e, +-/* 0x001c: queue_put_next */ +- 0xb60798c4, +- 0x8dbb0384, +- 0x0880b600, +- 0x80008e80, +- 0x90b6018f, +- 0x0f94f001, +- 0xf801d980, +-/* 0x0039: queue_get */ +- 0x0131f400, +- 0x9800d898, +- 0x89b801d9, +- 0x210bf404, +- 0xb60789c4, +- 0x9dbb0394, +- 0x0890b600, +- 0x98009e98, +- 0x80b6019f, +- 0x0f84f001, +- 0xf400d880, +-/* 0x0066: queue_get_done */ +- 0x00f80132, +-/* 0x0068: nv_rd32 */ +- 0xf002ecb9, +- 0x07f11fc9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x007a: nv_rd32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0xa7f0f31b, +- 0x1021f506, +- 0x00f7f101, +- 0x01f3f0cb, +- 0xf800ffcf, +-/* 0x009d: nv_wr32 */ +- 0x0007f100, +- 0x0103f0cc, +- 0xbd000fd0, +- 0x02ecb904, +- 0xf01fc9f0, +- 0x07f11ec9, +- 0x03f0ca00, +- 0x000cd001, +-/* 0x00be: nv_wr32_wait */ +- 0xc7f104bd, +- 0xc3f0ca00, +- 0x00cccf01, +- 0xf41fccc8, +- 0x00f8f31b, +-/* 0x00d0: wait_donez */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f037, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x00ed: wait_donez_ne */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x1bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0110: wait_doneo */ +- 0x99f094bd, +- 0x0007f100, +- 0x0203f037, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f006, +- 0xbd000ad0, +-/* 0x012d: wait_doneo_e */ +- 0x0087f104, +- 0x0183f000, +- 0xff0088cf, +- 0x0bf4888a, +- 0xf094bdf3, +- 0x07f10099, +- 0x03f01700, +- 0x0009d002, +- 0x00f804bd, +-/* 0x0150: mmctx_size */ +-/* 0x0152: nv_mmctx_size_loop */ +- 0xe89894bd, +- 0x1a85b600, +- 0xb60180b6, +- 0x98bb0284, +- 0x04e0b600, +- 0xf404efb8, +- 0x9fb9eb1b, +-/* 0x016f: mmctx_xfer */ +- 0xbd00f802, +- 0x0199f094, +- 0x370007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xbbfd94bd, +- 0x120bf405, +- 0xc40007f1, +- 0xd00103f0, +- 0x04bd000b, +-/* 0x0197: mmctx_base_disabled */ +- 0xfd0099f0, +- 0x0bf405ee, +- 0x0007f11e, +- 0x0103f0c6, +- 0xbd000ed0, +- 0x0007f104, +- 0x0103f0c7, +- 0xbd000fd0, +- 0x0199f004, +-/* 0x01b8: mmctx_multi_disabled */ +- 0xb600abc8, +- 0xb9f010b4, +- 0x01aec80c, +- 0xfd11e4b6, +- 0x07f105be, +- 0x03f0c500, +- 0x000bd001, +-/* 0x01d6: mmctx_exec_loop */ +-/* 0x01d6: mmctx_wait_free */ +- 0xe7f104bd, +- 0xe3f0c500, +- 0x00eecf01, +- 0xf41fe4f0, +- 0xce98f30b, +- 0x05e9fd00, +- 0xc80007f1, +- 0xd00103f0, +- 0x04bd000e, +- 0xb804c0b6, +- 0x1bf404cd, +- 0x02abc8d8, +-/* 0x0207: mmctx_fini_wait */ +- 0xf11f1bf4, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x1fb4f000, +- 0xf410b4b0, +- 0xa7f0f01b, +- 0xd021f405, +-/* 0x0223: mmctx_stop */ +- 0xc82b0ef4, +- 0xb4b600ab, +- 0x0cb9f010, +- 0xf112b9f0, +- 0xf0c50007, +- 0x0bd00103, +-/* 0x023b: mmctx_stop_wait */ +- 0xf104bd00, +- 0xf0c500b7, +- 0xbbcf01b3, +- 0x12bbc800, +-/* 0x024b: mmctx_done */ +- 0xbdf31bf4, +- 0x0199f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x025e: strand_wait */ +- 0xa0f900f8, +- 0xf402a7f0, +- 0xa0fcd021, +-/* 0x026a: strand_pre */ +- 0x97f000f8, +- 0xfc07f10c, +- 0x0203f04a, +- 0xbd0009d0, +- 0x5e21f504, +-/* 0x027f: strand_post */ +- 0xf000f802, +- 0x07f10d97, +- 0x03f04afc, +- 0x0009d002, +- 0x21f504bd, +- 0x00f8025e, +-/* 0x0294: strand_set */ +- 0xf10fc7f0, +- 0xf04ffc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f10bc7, +- 0x03f04afc, +- 0x000cd002, +- 0x07f104bd, +- 0x03f04ffc, +- 0x000ed002, +- 0xc7f004bd, +- 0xfc07f10a, +- 0x0203f04a, +- 0xbd000cd0, +- 0x5e21f504, +-/* 0x02d3: strand_ctx_init */ +- 0xbd00f802, +- 0x0399f094, +- 0x370007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0x026a21f5, +- 0xf503e7f0, +- 0xbd029421, +- 0xfc07f1c4, +- 0x0203f047, +- 0xbd000cd0, +- 0x01c7f004, +- 0x4afc07f1, +- 0xd00203f0, +- 0x04bd000c, +- 0x025e21f5, +- 0xf1010c92, +- 0xf046fc07, +- 0x0cd00203, +- 0xf004bd00, +- 0x07f102c7, +- 0x03f04afc, +- 0x000cd002, +- 0x21f504bd, +- 0x21f5025e, +- 0x87f1027f, +- 0x83f04200, +- 0x0097f102, +- 0x0293f020, +- 0x950099cf, +-/* 0x034a: ctx_init_strand_loop */ +- 0x8ed008fe, +- 0x408ed000, +- 0xb6808acf, +- 0xa0b606a5, +- 0x00eabb01, +- 0xb60480b6, +- 0x1bf40192, +- 0x08e4b6e8, +- 0xbdf2efbc, +- 0x0399f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x037e: error */ +- 0x07f100f8, +- 0x03f00500, +- 0x000fd002, +- 0xf7f004bd, +- 0x0007f101, +- 0x0303f007, +- 0xbd000fd0, +-/* 0x039b: init */ +- 0xbd00f804, +- 0x0007fe04, +- 0x420017f1, +- 0xcf0013f0, +- 0x11e70011, +- 0x14b60109, +- 0x0014fe08, +- 0xf10227f0, +- 0xf0120007, +- 0x02d00003, +- 0xf104bd00, +- 0xfe06c817, +- 0x24bd0010, +- 0x070007f1, +- 0xd00003f0, +- 0x04bd0002, +- 0x200327f1, +- 0x010007f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200427f1, +- 0x010407f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200b27f1, +- 0x010807f1, +- 0xd00103f0, +- 0x04bd0002, +- 0x200c27f1, +- 0x011c07f1, +- 0xd00103f0, +- 0x04bd0002, +- 0xf1010392, +- 0xf0090007, +- 0x03d00303, +- 0xf104bd00, +- 0xf0870427, +- 0x07f10023, +- 0x03f00400, +- 0x0002d000, +- 0x27f004bd, +- 0x0007f104, +- 0x0003f003, +- 0xbd0002d0, +- 0x1031f404, +- 0x9604e7f1, +- 0xf440e3f0, +- 0xfeb96821, +- 0x90f1c702, +- 0xf0030180, +- 0x0f801ff4, +- 0x0117f002, +- 0xb6041fbb, +- 0x07f10112, +- 0x03f00300, +- 0x0001d001, +- 0x07f104bd, +- 0x03f00400, +- 0x0001d001, +- 0x17f104bd, +- 0xf7f00100, +- 0xd721f502, +- 0xe921f507, +- 0x10f7f007, +- 0x083621f5, +- 0x98000e98, +- 0x21f5010f, +- 0x14950150, +- 0x0007f108, +- 0x0103f0c0, +- 0xbd0004d0, +- 0x0007f104, +- 0x0103f0c1, +- 0xbd0004d0, +- 0x0030b704, +- 0x001fbb13, +- 0xf102f5b6, +- 0xf0d30007, +- 0x0fd00103, +- 0xb604bd00, +- 0x10b60815, +- 0x0814b601, +- 0xf5021fb9, +- 0xbb02d321, +- 0x0398001f, +- 0x0047f102, +- 0x5043f020, +-/* 0x04f4: init_gpc */ +- 0x08044ea0, +- 0xf4021fb9, +- 0x4ea09d21, +- 0xf4bd010c, +- 0xa09d21f4, +- 0xf401044e, +- 0x4ea09d21, +- 0xf7f00100, +- 0x9d21f402, +- 0x08004ea0, +-/* 0x051c: init_gpc_wait */ +- 0xc86821f4, +- 0x0bf41fff, +- 0x044ea0fa, +- 0x6821f408, +- 0xb7001fbb, +- 0xb6800040, +- 0x1bf40132, +- 0x00f7f0be, +- 0x083621f5, +- 0xf500f7f0, +- 0xf107d721, +- 0xf0010007, +- 0x01d00203, +- 0xbd04bd00, +- 0x1f19f014, +- 0x300007f1, +- 0xd00203f0, +- 0x04bd0001, +-/* 0x0564: main */ +- 0xf40031f4, +- 0xd7f00028, +- 0x3921f410, +- 0xb1f401f4, +- 0xf54001e4, +- 0xbd00e91b, +- 0x0499f094, +- 0x370007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xc00017f1, +- 0xcf0213f0, +- 0x27f10011, +- 0x23f0c100, +- 0x0022cf02, +- 0xf51f13c8, +- 0xc800890b, +- 0x0bf41f23, +- 0xb920f962, +- 0x94bd0212, +- 0xf10799f0, +- 0xf0370007, +- 0x09d00203, +- 0xf404bd00, +- 0x31f40132, +- 0x0221f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x20fc04bd, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f037, +- 0xbd0009d0, +- 0x0131f404, +- 0x0a0221f5, +- 0x99f094bd, +- 0x0007f106, +- 0x0203f017, +- 0xbd0009d0, +- 0x330ef404, +-/* 0x060c: chsw_prev_no_next */ +- 0x12b920f9, +- 0x0132f402, +- 0xf50232f4, +- 0xfc0a0221, +- 0x0007f120, +- 0x0203f0c0, +- 0xbd0002d0, +- 0x130ef404, +-/* 0x062c: chsw_no_prev */ +- 0xf41f23c8, +- 0x31f40d0b, +- 0x0232f401, +- 0x0a0221f5, +-/* 0x063c: chsw_done */ +- 0xf10127f0, +- 0xf0c30007, +- 0x02d00203, +- 0xbd04bd00, +- 0x0499f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xff080ef5, +-/* 0x0660: main_not_ctx_switch */ +- 0xf401e4b0, +- 0xf2b90d1b, +- 0x9a21f502, +- 0x460ef409, +-/* 0x0670: main_not_ctx_chan */ +- 0xf402e4b0, +- 0x94bd321b, +- 0xf10799f0, +- 0xf0370007, +- 0x09d00203, +- 0xf404bd00, +- 0x32f40132, +- 0x0221f502, +- 0xf094bd0a, +- 0x07f10799, +- 0x03f01700, +- 0x0009d002, +- 0x0ef404bd, +-/* 0x06a5: main_not_ctx_save */ +- 0x10ef9411, +- 0xf501f5f0, +- 0xf5037e21, +-/* 0x06b3: main_done */ +- 0xbdfeb50e, +- 0x1f29f024, +- 0x300007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xfea00ef5, +-/* 0x06c8: ih */ +- 0x88fe80f9, +- 0xf980f901, +- 0xf9a0f990, +- 0xf9d0f9b0, +- 0xbdf0f9e0, +- 0x00a7f104, +- 0x00a3f002, +- 0xc400aacf, +- 0x0bf404ab, +- 0x10d7f030, +- 0x1a00e7f1, +- 0xcf00e3f0, +- 0xf7f100ee, +- 0xf3f01900, +- 0x00ffcf00, +- 0xb70421f4, +- 0xf00400b0, +- 0x07f101e7, +- 0x03f01d00, +- 0x000ed000, +-/* 0x071a: ih_no_fifo */ +- 0xabe404bd, +- 0x0bf40100, +- 0x10d7f00d, +- 0x4001e7f1, +-/* 0x072b: ih_no_ctxsw */ +- 0xe40421f4, +- 0xf40400ab, +- 0xe7f16c0b, +- 0xe3f00708, +- 0x6821f440, +- 0xf102ffb9, +- 0xf0040007, +- 0x0fd00203, +- 0xf104bd00, +- 0xf00704e7, +- 0x21f440e3, +- 0x02ffb968, +- 0x030007f1, +- 0xd00203f0, +- 0x04bd000f, +- 0x9450fec7, +- 0xf7f102ee, +- 0xf3f00700, +- 0x00efbb40, +- 0xf16821f4, +- 0xf0020007, +- 0x0fd00203, +- 0xf004bd00, +- 0x21f503f7, +- 0xb7f1037e, +- 0xbfb90100, +- 0x44e7f102, +- 0x40e3f001, +-/* 0x079b: ih_no_fwmthd */ +- 0xf19d21f4, +- 0xbd0504b7, +- 0xb4abffb0, +- 0xf10f0bf4, +- 0xf0070007, +- 0x0bd00303, +-/* 0x07b3: ih_no_other */ +- 0xf104bd00, +- 0xf0010007, +- 0x0ad00003, +- 0xfc04bd00, +- 0xfce0fcf0, +- 0xfcb0fcd0, +- 0xfc90fca0, +- 0x0088fe80, +- 0x32f480fc, +-/* 0x07d7: ctx_4170s */ +- 0xf001f800, +- 0xffb910f5, +- 0x70e7f102, +- 0x40e3f041, +- 0xf89d21f4, +-/* 0x07e9: ctx_4170w */ +- 0x70e7f100, +- 0x40e3f041, +- 0xb96821f4, +- 0xf4f002ff, +- 0xf01bf410, +-/* 0x07fe: ctx_redswitch */ +- 0xe7f100f8, +- 0xe5f00200, +- 0x20e5f040, +- 0xf110e5f0, +- 0xf0850007, +- 0x0ed00103, +- 0xf004bd00, +-/* 0x081a: ctx_redswitch_delay */ +- 0xf2b608f7, +- 0xfd1bf401, +- 0x0400e5f1, +- 0x0100e5f1, +- 0x850007f1, +- 0xd00103f0, +- 0x04bd000e, +-/* 0x0836: ctx_86c */ +- 0x07f100f8, +- 0x03f02300, +- 0x000fd002, +- 0xffb904bd, +- 0x14e7f102, +- 0x40e3f08a, +- 0xb99d21f4, +- 0xe7f102ff, +- 0xe3f0a88c, +- 0x9d21f441, +-/* 0x085e: ctx_mem */ +- 0x07f100f8, +- 0x03f08400, +- 0x000fd002, +-/* 0x086a: ctx_mem_wait */ +- 0xf7f104bd, +- 0xf3f08400, +- 0x00ffcf02, +- 0xf405fffd, +- 0x00f8f31b, +-/* 0x087c: ctx_load */ +- 0x99f094bd, +- 0x0007f105, +- 0x0203f037, +- 0xbd0009d0, +- 0x0ca7f004, +- 0xbdd021f4, +- 0x0007f1f4, +- 0x0203f089, +- 0xbd000fd0, +- 0x0007f104, +- 0x0203f0c1, +- 0xbd0002d0, +- 0x0007f104, +- 0x0203f083, +- 0xbd0002d0, +- 0x07f7f004, +- 0x085e21f5, +- 0xc00007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xf0000bfe, +- 0x24b61f2a, +- 0x0220b604, +- 0x99f094bd, +- 0x0007f108, +- 0x0203f037, +- 0xbd0009d0, +- 0x0007f104, +- 0x0203f081, +- 0xbd0002d0, +- 0x0027f104, +- 0x0023f100, +- 0x0225f080, +- 0x880007f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xf11017f0, +- 0xf0020027, +- 0x12fa0223, +- 0xbd03f805, +- 0x0899f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +- 0xb6810198, +- 0x02981814, +- 0x0825b680, +- 0x800512fd, +- 0x94bd1601, +- 0xf10999f0, +- 0xf0370007, +- 0x09d00203, +- 0xf104bd00, +- 0xf0810007, +- 0x01d00203, +- 0xf004bd00, +- 0x07f10127, +- 0x03f08800, +- 0x0002d002, +- 0x17f104bd, +- 0x13f00100, +- 0x0501fa06, +- 0x94bd03f8, +- 0xf10999f0, +- 0xf0170007, +- 0x09d00203, +- 0xbd04bd00, +- 0x0599f094, +- 0x170007f1, +- 0xd00203f0, +- 0x04bd0009, +-/* 0x099a: ctx_chan */ +- 0x21f500f8, +- 0xa7f0087c, +- 0xd021f40c, +- 0xf505f7f0, +- 0xf8085e21, +-/* 0x09ad: ctx_mmio_exec */ +- 0x41039800, +- 0x810007f1, +- 0xd00203f0, +- 0x04bd0003, +-/* 0x09be: ctx_mmio_loop */ +- 0x34c434bd, +- 0x0f1bf4ff, +- 0x020057f1, +- 0xfa0653f0, +- 0x03f80535, +-/* 0x09d0: ctx_mmio_pull */ +- 0x98804e98, +- 0x21f4814f, +- 0x0830b69d, +- 0xf40112b6, +-/* 0x09e2: ctx_mmio_done */ +- 0x0398df1b, +- 0x0007f116, +- 0x0203f081, +- 0xbd0003d0, +- 0x40008004, +- 0x010017f1, +- 0xfa0613f0, +- 0x03f80601, +-/* 0x0a02: ctx_xfer */ +- 0xe7f000f8, +- 0x0007f104, +- 0x0303f002, +- 0xbd000ed0, +-/* 0x0a11: ctx_xfer_idle */ +- 0x00e7f104, +- 0x03e3f000, +- 0xf100eecf, +- 0xf42000e4, +- 0x11f4f21b, +- 0x0d02f406, +-/* 0x0a28: ctx_xfer_pre */ +- 0xf510f7f0, +- 0xf4083621, +-/* 0x0a32: ctx_xfer_pre_load */ +- 0xf7f01c11, +- 0xd721f502, +- 0xe921f507, +- 0xfe21f507, +- 0xf5f4bd07, +- 0xf507d721, +-/* 0x0a4b: ctx_xfer_exec */ +- 0x98087c21, +- 0x24bd1601, +- 0x050007f1, +- 0xd00103f0, +- 0x04bd0002, +- 0xf1021fb9, +- 0xf0a500e7, +- 0x21f441e3, +- 0x01fcf09d, +- 0xb6022cf0, +- 0xf2fd0124, +- 0x02ffb905, +- 0xa504e7f1, +- 0xf441e3f0, +- 0x21f59d21, +- 0x24bd026a, +- 0x47fc07f1, +- 0xd00203f0, +- 0x04bd0002, +- 0xb6012cf0, +- 0x07f10320, +- 0x03f04afc, +- 0x0002d002, +- 0xacf004bd, +- 0x06a5f001, +- 0x9800b7f0, +- 0x0d98000c, +- 0x00e7f001, +- 0x016f21f5, +- 0xf508a7f0, +- 0xf5011021, +- 0xf4025e21, +- 0xa7f01301, +- 0xd021f40c, +- 0xf505f7f0, +- 0xf4085e21, +-/* 0x0ada: ctx_xfer_post */ +- 0xf7f02e02, +- 0xd721f502, +- 0xf5f4bd07, +- 0xf5083621, +- 0xf5027f21, +- 0xbd07e921, +- 0xd721f5f4, +- 0x1011f407, +- 0xfd400198, +- 0x0bf40511, +- 0xad21f507, +-/* 0x0b05: ctx_xfer_no_post_mmio */ +-/* 0x0b05: ctx_xfer_done */ +- 0x0000f809, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc +deleted file mode 100644 +index 2a0b0f84..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/macros.fuc ++++ /dev/null +@@ -1,229 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "os.h" +- +-#define GF100 0xc0 +-#define GF117 0xd7 +-#define GK100 0xe0 +-#define GK110 0xf0 +-#define GK208 0x108 +- +-#define NV_PGRAPH_TRAPPED_ADDR 0x400704 +-#define NV_PGRAPH_TRAPPED_DATA_LO 0x400708 +-#define NV_PGRAPH_TRAPPED_DATA_HI 0x40070c +- +-#define NV_PGRAPH_FE_OBJECT_TABLE(n) ((n) * 4 + 0x400700) +- +-#define NV_PGRAPH_FECS_INTR_ACK 0x409004 +-#define NV_PGRAPH_FECS_INTR 0x409008 +-#define NV_PGRAPH_FECS_INTR_FWMTHD 0x00000400 +-#define NV_PGRAPH_FECS_INTR_CHSW 0x00000100 +-#define NV_PGRAPH_FECS_INTR_FIFO 0x00000004 +-#define NV_PGRAPH_FECS_INTR_MODE 0x40900c +-#define NV_PGRAPH_FECS_INTR_MODE_FIFO 0x00000004 +-#define NV_PGRAPH_FECS_INTR_MODE_FIFO_LEVEL 0x00000004 +-#define NV_PGRAPH_FECS_INTR_MODE_FIFO_EDGE 0x00000000 +-#define NV_PGRAPH_FECS_INTR_EN_SET 0x409010 +-#define NV_PGRAPH_FECS_INTR_EN_SET_FIFO 0x00000004 +-#define NV_PGRAPH_FECS_INTR_ROUTE 0x40901c +-#define NV_PGRAPH_FECS_ACCESS 0x409048 +-#define NV_PGRAPH_FECS_ACCESS_FIFO 0x00000002 +-#define NV_PGRAPH_FECS_FIFO_DATA 0x409064 +-#define NV_PGRAPH_FECS_FIFO_CMD 0x409068 +-#define NV_PGRAPH_FECS_FIFO_ACK 0x409074 +-#define NV_PGRAPH_FECS_CAPS 0x409108 +-#define NV_PGRAPH_FECS_SIGNAL 0x409400 +-#define NV_PGRAPH_FECS_IROUTE 0x409404 +-#define NV_PGRAPH_FECS_BAR_MASK0 0x40940c +-#define NV_PGRAPH_FECS_BAR_MASK1 0x409410 +-#define NV_PGRAPH_FECS_BAR 0x409414 +-#define NV_PGRAPH_FECS_BAR_SET 0x409418 +-#define NV_PGRAPH_FECS_RED_SWITCH 0x409614 +-#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_ROP 0x00000400 +-#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_GPC 0x00000200 +-#define NV_PGRAPH_FECS_RED_SWITCH_ENABLE_MAIN 0x00000100 +-#define NV_PGRAPH_FECS_RED_SWITCH_POWER_ROP 0x00000040 +-#define NV_PGRAPH_FECS_RED_SWITCH_POWER_GPC 0x00000020 +-#define NV_PGRAPH_FECS_RED_SWITCH_POWER_MAIN 0x00000010 +-#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_GPC 0x00000002 +-#define NV_PGRAPH_FECS_RED_SWITCH_PAUSE_MAIN 0x00000001 +-#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 +-#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 +-#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c +-#define NV_PGRAPH_FECS_MMCTX_SAVE_SWBASE 0x409700 +-#define NV_PGRAPH_FECS_MMCTX_LOAD_SWBASE 0x409704 +-#define NV_PGRAPH_FECS_MMCTX_BASE 0x409710 +-#define NV_PGRAPH_FECS_MMCTX_CTRL 0x409714 +-#define NV_PGRAPH_FECS_MMCTX_MULTI_STRIDE 0x409718 +-#define NV_PGRAPH_FECS_MMCTX_MULTI_MASK 0x40971c +-#define NV_PGRAPH_FECS_MMCTX_QUEUE 0x409720 +-#define NV_PGRAPH_FECS_MMIO_CTRL 0x409728 +-#define NV_PGRAPH_FECS_MMIO_RDVAL 0x40972c +-#define NV_PGRAPH_FECS_MMIO_WRVAL 0x409730 +-#define NV_PGRAPH_FECS_MMCTX_LOAD_COUNT 0x40974c +-#if CHIPSET < GK110 +-#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) +-#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x409820) +-#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) +-#define NV_PGRAPH_FECS_UNK86C 0x40986c +-#else +-#define NV_PGRAPH_FECS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x409800) +-#define NV_PGRAPH_FECS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x409840) +-#define NV_PGRAPH_FECS_UNK86C 0x40988c +-#define NV_PGRAPH_FECS_CC_SCRATCH_SET(n) ((n) * 4 + 0x4098c0) +-#endif +-#define NV_PGRAPH_FECS_STRANDS_CNT 0x409880 +-#define NV_PGRAPH_FECS_STRAND_SAVE_SWBASE 0x409908 +-#define NV_PGRAPH_FECS_STRAND_LOAD_SWBASE 0x40990c +-#define NV_PGRAPH_FECS_STRAND_WORDS 0x409910 +-#define NV_PGRAPH_FECS_STRAND_DATA 0x409918 +-#define NV_PGRAPH_FECS_STRAND_SELECT 0x40991c +-#define NV_PGRAPH_FECS_STRAND_CMD 0x409928 +-#define NV_PGRAPH_FECS_STRAND_CMD_SEEK 0x00000001 +-#define NV_PGRAPH_FECS_STRAND_CMD_GET_INFO 0x00000002 +-#define NV_PGRAPH_FECS_STRAND_CMD_SAVE 0x00000003 +-#define NV_PGRAPH_FECS_STRAND_CMD_LOAD 0x00000004 +-#define NV_PGRAPH_FECS_STRAND_CMD_ACTIVATE_FILTER 0x0000000a +-#define NV_PGRAPH_FECS_STRAND_CMD_DEACTIVATE_FILTER 0x0000000b +-#define NV_PGRAPH_FECS_STRAND_CMD_ENABLE 0x0000000c +-#define NV_PGRAPH_FECS_STRAND_CMD_DISABLE 0x0000000d +-#define NV_PGRAPH_FECS_STRAND_FILTER 0x40993c +-#define NV_PGRAPH_FECS_MEM_BASE 0x409a04 +-#define NV_PGRAPH_FECS_MEM_CHAN 0x409a0c +-#define NV_PGRAPH_FECS_MEM_CMD 0x409a10 +-#define NV_PGRAPH_FECS_MEM_CMD_LOAD_CHAN 0x00000007 +-#define NV_PGRAPH_FECS_MEM_TARGET 0x409a20 +-#define NV_PGRAPH_FECS_MEM_TARGET_UNK31 0x80000000 +-#define NV_PGRAPH_FECS_MEM_TARGET_AS 0x0000001f +-#define NV_PGRAPH_FECS_MEM_TARGET_AS_VM 0x00000001 +-#define NV_PGRAPH_FECS_MEM_TARGET_AS_VRAM 0x00000002 +-#define NV_PGRAPH_FECS_CHAN_ADDR 0x409b00 +-#define NV_PGRAPH_FECS_CHAN_NEXT 0x409b04 +-#define NV_PGRAPH_FECS_CHSW 0x409b0c +-#define NV_PGRAPH_FECS_CHSW_ACK 0x00000001 +-#define NV_PGRAPH_FECS_INTR_UP_SET 0x409c1c +-#define NV_PGRAPH_FECS_INTR_UP_EN 0x409c24 +- +-#define NV_PGRAPH_GPCX_GPCCS_INTR_ACK 0x41a004 +-#define NV_PGRAPH_GPCX_GPCCS_INTR 0x41a008 +-#define NV_PGRAPH_GPCX_GPCCS_INTR_FIFO 0x00000004 +-#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET 0x41a010 +-#define NV_PGRAPH_GPCX_GPCCS_INTR_EN_SET_FIFO 0x00000004 +-#define NV_PGRAPH_GPCX_GPCCS_INTR_ROUTE 0x41a01c +-#define NV_PGRAPH_GPCX_GPCCS_ACCESS 0x41a048 +-#define NV_PGRAPH_GPCX_GPCCS_ACCESS_FIFO 0x00000002 +-#define NV_PGRAPH_GPCX_GPCCS_FIFO_DATA 0x41a064 +-#define NV_PGRAPH_GPCX_GPCCS_FIFO_CMD 0x41a068 +-#define NV_PGRAPH_GPCX_GPCCS_FIFO_ACK 0x41a074 +-#define NV_PGRAPH_GPCX_GPCCS_UNITS 0x41a608 +-#define NV_PGRAPH_GPCX_GPCCS_CAPS 0x41a108 +-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH 0x41a614 +-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_UNK11 0x00000800 +-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_ENABLE 0x00000200 +-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_POWER 0x00000020 +-#define NV_PGRAPH_GPCX_GPCCS_RED_SWITCH_PAUSE 0x00000002 +-#define NV_PGRAPH_GPCX_GPCCS_MYINDEX 0x41a618 +-#define NV_PGRAPH_GPCX_GPCCS_MMCTX_SAVE_SWBASE 0x41a700 +-#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_SWBASE 0x41a704 +-#define NV_PGRAPH_GPCX_GPCCS_MMCTX_LOAD_COUNT 0x41a74c +-#if CHIPSET < GK110 +-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) +-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a820) +-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) +-#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a86c +-#else +-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_VAL(n) ((n) * 4 + 0x41a800) +-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_CLR(n) ((n) * 4 + 0x41a840) +-#define NV_PGRAPH_GPCX_GPCCS_UNK86C 0x41a88c +-#define NV_PGRAPH_GPCX_GPCCS_CC_SCRATCH_SET(n) ((n) * 4 + 0x41a8c0) +-#endif +-#define NV_PGRAPH_GPCX_GPCCS_STRAND_SELECT 0x41a91c +-#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD 0x41a928 +-#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_SAVE 0x00000003 +-#define NV_PGRAPH_GPCX_GPCCS_STRAND_CMD_LOAD 0x00000004 +-#define NV_PGRAPH_GPCX_GPCCS_MEM_BASE 0x41aa04 +- +-#define mmctx_data(r,c) .b32 (((c - 1) << 26) | r) +-#define queue_init .skip 72 // (2 * 4) + ((8 * 4) * 2) +- +-#define T_WAIT 0 +-#define T_MMCTX 1 +-#define T_STRWAIT 2 +-#define T_STRINIT 3 +-#define T_AUTO 4 +-#define T_CHAN 5 +-#define T_LOAD 6 +-#define T_SAVE 7 +-#define T_LCHAN 8 +-#define T_LCTXH 9 +- +-#if CHIPSET < GK208 +-#define imm32(reg,val) /* +-*/ movw reg ((val) & 0x0000ffff) /* +-*/ sethi reg ((val) & 0xffff0000) +-#else +-#define imm32(reg,val) /* +-*/ mov reg (val) +-#endif +- +-#define nv_mkio(rv,r,i) /* +-*/ imm32(rv, (((r) & 0xffc) << 6) | ((i) << 2)) +- +-#define hash # +-#define fn(a) a +-#if CHIPSET < GK208 +-#define call(a) call fn(hash)a +-#else +-#define call(a) lcall fn(hash)a +-#endif +- +-#define nv_iord(rv,r,i) /* +-*/ nv_mkio(rv,r,i) /* +-*/ iord rv I[rv] +- +-#define nv_iowr(r,i,rv) /* +-*/ nv_mkio($r0,r,i) /* +-*/ iowr I[$r0] rv /* +-*/ clear b32 $r0 +- +-#define nv_rd32(reg,addr) /* +-*/ imm32($r14, addr) /* +-*/ call(nv_rd32) /* +-*/ mov b32 reg $r15 +- +-#define nv_wr32(addr,reg) /* +-*/ mov b32 $r15 reg /* +-*/ imm32($r14, addr) /* +-*/ call(nv_wr32) +- +-#define trace_set(bit) /* +-*/ clear b32 $r9 /* +-*/ bset $r9 bit /* +-*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_SET(7), 0, $r9) +- +-#define trace_clr(bit) /* +-*/ clear b32 $r9 /* +-*/ bset $r9 bit /* +-*/ nv_iowr(NV_PGRAPH_FECS_CC_SCRATCH_CLR(7), 0, $r9) +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h +deleted file mode 100644 +index 1718ae4e..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/os.h ++++ /dev/null +@@ -1,8 +0,0 @@ +-#ifndef __NVKM_GRAPH_OS_H__ +-#define __NVKM_GRAPH_OS_H__ +- +-#define E_BAD_COMMAND 0x00000001 +-#define E_CMD_OVERFLOW 0x00000002 +-#define E_BAD_FWMTHD 0x00000003 +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c b/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c +deleted file mode 100644 +index d07b19dc..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/gk110b.c ++++ /dev/null +@@ -1,117 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-gk110b_graph_init_l1c_0[] = { +- { 0x419c98, 1, 0x04, 0x00000000 }, +- { 0x419ca8, 1, 0x04, 0x00000000 }, +- { 0x419cb0, 1, 0x04, 0x09000000 }, +- { 0x419cb4, 1, 0x04, 0x00000000 }, +- { 0x419cb8, 1, 0x04, 0x00b08bea }, +- { 0x419c84, 1, 0x04, 0x00010384 }, +- { 0x419cbc, 1, 0x04, 0x281b3646 }, +- { 0x419cc0, 2, 0x04, 0x00000000 }, +- { 0x419c80, 1, 0x04, 0x00020230 }, +- { 0x419ccc, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gk110b_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000080 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ee4, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x00000000 }, +- { 0x419eb4, 1, 0x04, 0x00000000 }, +- { 0x419ebc, 2, 0x04, 0x00000000 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419ed0, 1, 0x04, 0x00002616 }, +- { 0x419f74, 1, 0x04, 0x00015555 }, +- { 0x419f80, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gk110b_graph_pack_mmio[] = { +- { nve4_graph_init_main_0 }, +- { nvf0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvd9_graph_init_pd_0 }, +- { nvf0_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvf0_graph_init_sked_0 }, +- { nvf0_graph_init_cwd_0 }, +- { nvd9_graph_init_prop_0 }, +- { nvc1_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvd9_graph_init_gpm_0 }, +- { nvf0_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nve4_graph_init_tpccs_0 }, +- { nvf0_graph_init_tex_0 }, +- { nve4_graph_init_pe_0 }, +- { gk110b_graph_init_l1c_0 }, +- { nvc0_graph_init_mpc_0 }, +- { gk110b_graph_init_sm_0 }, +- { nvd7_graph_init_pes_0 }, +- { nvd7_graph_init_wwdx_0 }, +- { nvd7_graph_init_cbm_0 }, +- { nve4_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-struct nouveau_oclass * +-gk110b_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xf1), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nve4_graph_init, +- .fini = nvf0_graph_fini, +- }, +- .cclass = &gk110b_grctx_oclass, +- .sclass = nvf0_graph_sclass, +- .mmio = gk110b_graph_pack_mmio, +- .fecs.ucode = &nvf0_graph_fecs_ucode, +- .gpccs.ucode = &nvf0_graph_gpccs_ucode, +- .ppc_nr = 2, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c b/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c +deleted file mode 100644 +index 7d0abe9f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/gk20a.c ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-static struct nouveau_oclass +-gk20a_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0xa040, &nouveau_object_ofuncs }, +- { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-struct nouveau_oclass * +-gk20a_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xea), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nve4_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &gk20a_grctx_oclass, +- .sclass = gk20a_graph_sclass, +- .mmio = nve4_graph_pack_mmio, +- .ppc_nr = 1, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c b/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c +deleted file mode 100644 +index 4bdbdab2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/gm107.c ++++ /dev/null +@@ -1,469 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-gm107_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0xa140, &nouveau_object_ofuncs }, +- { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-gm107_graph_init_main_0[] = { +- { 0x400080, 1, 0x04, 0x003003c2 }, +- { 0x400088, 1, 0x04, 0x0001bfe7 }, +- { 0x40008c, 1, 0x04, 0x00060000 }, +- { 0x400090, 1, 0x04, 0x00000030 }, +- { 0x40013c, 1, 0x04, 0x003901f3 }, +- { 0x400140, 1, 0x04, 0x00000100 }, +- { 0x400144, 1, 0x04, 0x00000000 }, +- { 0x400148, 1, 0x04, 0x00000110 }, +- { 0x400138, 1, 0x04, 0x00000000 }, +- { 0x400130, 2, 0x04, 0x00000000 }, +- { 0x400124, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405900, 1, 0x04, 0x00000000 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_scc_0[] = { +- { 0x40803c, 1, 0x04, 0x00000010 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_sked_0[] = { +- { 0x407010, 1, 0x04, 0x00000000 }, +- { 0x407040, 1, 0x04, 0x40440424 }, +- { 0x407048, 1, 0x04, 0x0000000a }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_prop_0[] = { +- { 0x418408, 1, 0x04, 0x00000000 }, +- { 0x4184a0, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_setup_1[] = { +- { 0x4188c8, 2, 0x04, 0x00000000 }, +- { 0x4188d0, 1, 0x04, 0x00010000 }, +- { 0x4188d4, 1, 0x04, 0x00010201 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_zcull_0[] = { +- { 0x418910, 1, 0x04, 0x00010001 }, +- { 0x418914, 1, 0x04, 0x00000301 }, +- { 0x418918, 1, 0x04, 0x00800000 }, +- { 0x418930, 2, 0x04, 0x00000000 }, +- { 0x418980, 1, 0x04, 0x77777770 }, +- { 0x418984, 3, 0x04, 0x77777777 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_gpc_unk_1[] = { +- { 0x418d00, 1, 0x04, 0x00000000 }, +- { 0x418f00, 1, 0x04, 0x00000400 }, +- { 0x418f08, 1, 0x04, 0x00000000 }, +- { 0x418e08, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_tpccs_0[] = { +- { 0x419dc4, 1, 0x04, 0x00000000 }, +- { 0x419dc8, 1, 0x04, 0x00000501 }, +- { 0x419dd0, 1, 0x04, 0x00000000 }, +- { 0x419dd4, 1, 0x04, 0x00000100 }, +- { 0x419dd8, 1, 0x04, 0x00000001 }, +- { 0x419ddc, 1, 0x04, 0x00000002 }, +- { 0x419de0, 1, 0x04, 0x00000001 }, +- { 0x419d0c, 1, 0x04, 0x00000000 }, +- { 0x419d10, 1, 0x04, 0x00000014 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_tex_0[] = { +- { 0x419ab0, 1, 0x04, 0x00000000 }, +- { 0x419ab8, 1, 0x04, 0x000000e7 }, +- { 0x419abc, 1, 0x04, 0x00000000 }, +- { 0x419acc, 1, 0x04, 0x000000ff }, +- { 0x419ac0, 1, 0x04, 0x00000000 }, +- { 0x419aa8, 2, 0x04, 0x00000000 }, +- { 0x419ad0, 2, 0x04, 0x00000000 }, +- { 0x419ae0, 2, 0x04, 0x00000000 }, +- { 0x419af0, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_pe_0[] = { +- { 0x419900, 1, 0x04, 0x000000ff }, +- { 0x41980c, 1, 0x04, 0x00000010 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x419838, 1, 0x04, 0x000000ff }, +- { 0x419850, 1, 0x04, 0x00000004 }, +- { 0x419854, 2, 0x04, 0x00000000 }, +- { 0x419894, 3, 0x04, 0x00100401 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_l1c_0[] = { +- { 0x419c98, 1, 0x04, 0x00000000 }, +- { 0x419cc0, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_sm_0[] = { +- { 0x419e30, 1, 0x04, 0x000000ff }, +- { 0x419e00, 1, 0x04, 0x00000000 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ee4, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x01000000 }, +- { 0x419ee8, 1, 0x04, 0x00000091 }, +- { 0x419eb4, 1, 0x04, 0x00000000 }, +- { 0x419ebc, 2, 0x04, 0x00000000 }, +- { 0x419edc, 1, 0x04, 0x000c1810 }, +- { 0x419ed8, 1, 0x04, 0x00000000 }, +- { 0x419ee0, 1, 0x04, 0x00000000 }, +- { 0x419f74, 1, 0x04, 0x00005155 }, +- { 0x419f80, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_l1c_1[] = { +- { 0x419ccc, 2, 0x04, 0x00000000 }, +- { 0x419c80, 1, 0x04, 0x3f006022 }, +- { 0x419c88, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_pes_0[] = { +- { 0x41be50, 1, 0x04, 0x000000ff }, +- { 0x41be04, 1, 0x04, 0x00000000 }, +- { 0x41be08, 1, 0x04, 0x00000004 }, +- { 0x41be0c, 1, 0x04, 0x00000008 }, +- { 0x41be10, 1, 0x04, 0x0e3b8bc7 }, +- { 0x41be14, 2, 0x04, 0x00000000 }, +- { 0x41be3c, 5, 0x04, 0x00100401 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_wwdx_0[] = { +- { 0x41bfd4, 1, 0x04, 0x00800000 }, +- { 0x41bfdc, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_cbm_0[] = { +- { 0x41becc, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_be_0[] = { +- { 0x408890, 1, 0x04, 0x000000ff }, +- { 0x40880c, 1, 0x04, 0x00000000 }, +- { 0x408850, 1, 0x04, 0x00000004 }, +- { 0x408878, 1, 0x04, 0x00c81603 }, +- { 0x40887c, 1, 0x04, 0x80543432 }, +- { 0x408880, 1, 0x04, 0x0010581e }, +- { 0x408884, 1, 0x04, 0x00001205 }, +- { 0x408974, 1, 0x04, 0x000000ff }, +- { 0x408910, 9, 0x04, 0x00000000 }, +- { 0x408950, 1, 0x04, 0x00000000 }, +- { 0x408954, 1, 0x04, 0x0000ffff }, +- { 0x408958, 1, 0x04, 0x00000034 }, +- { 0x40895c, 1, 0x04, 0x8531a003 }, +- { 0x408960, 1, 0x04, 0x0561985a }, +- { 0x408964, 1, 0x04, 0x04e15c4f }, +- { 0x408968, 1, 0x04, 0x02808833 }, +- { 0x40896c, 1, 0x04, 0x01f02438 }, +- { 0x408970, 1, 0x04, 0x00012c00 }, +- { 0x408984, 1, 0x04, 0x00000000 }, +- { 0x408988, 1, 0x04, 0x08040201 }, +- { 0x40898c, 1, 0x04, 0x80402010 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-gm107_graph_init_sm_1[] = { +- { 0x419e5c, 1, 0x04, 0x00000000 }, +- { 0x419e58, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-gm107_graph_pack_mmio[] = { +- { gm107_graph_init_main_0 }, +- { nvf0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvc0_graph_init_pd_0 }, +- { gm107_graph_init_ds_0 }, +- { gm107_graph_init_scc_0 }, +- { gm107_graph_init_sked_0 }, +- { nvf0_graph_init_cwd_0 }, +- { gm107_graph_init_prop_0 }, +- { nv108_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { gm107_graph_init_setup_1 }, +- { gm107_graph_init_zcull_0 }, +- { nvc0_graph_init_gpm_0 }, +- { gm107_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { gm107_graph_init_tpccs_0 }, +- { gm107_graph_init_tex_0 }, +- { gm107_graph_init_pe_0 }, +- { gm107_graph_init_l1c_0 }, +- { nvc0_graph_init_mpc_0 }, +- { gm107_graph_init_sm_0 }, +- { gm107_graph_init_l1c_1 }, +- { gm107_graph_init_pes_0 }, +- { gm107_graph_init_wwdx_0 }, +- { gm107_graph_init_cbm_0 }, +- { gm107_graph_init_be_0 }, +- { gm107_graph_init_sm_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static void +-gm107_graph_init_bios(struct nvc0_graph_priv *priv) +-{ +- static const struct { +- u32 ctrl; +- u32 data; +- } regs[] = { +- { 0x419ed8, 0x419ee0 }, +- { 0x419ad0, 0x419ad4 }, +- { 0x419ae0, 0x419ae4 }, +- { 0x419af0, 0x419af4 }, +- { 0x419af8, 0x419afc }, +- }; +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_P0260E infoE; +- struct nvbios_P0260X infoX; +- int E = -1, X; +- u8 ver, hdr; +- +- while (nvbios_P0260Ep(bios, ++E, &ver, &hdr, &infoE)) { +- if (X = -1, E < ARRAY_SIZE(regs)) { +- nv_wr32(priv, regs[E].ctrl, infoE.data); +- while (nvbios_P0260Xp(bios, ++X, &ver, &hdr, &infoX)) +- nv_wr32(priv, regs[E].data, infoX.data); +- } +- } +-} +- +-int +-gm107_graph_init(struct nouveau_object *object) +-{ +- struct nvc0_graph_oclass *oclass = (void *)object->oclass; +- struct nvc0_graph_priv *priv = (void *)object; +- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); +- u32 data[TPC_MAX / 8] = {}; +- u8 tpcnr[GPC_MAX]; +- int gpc, tpc, ppc, rop; +- int ret, i; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); +- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); +- +- nvc0_graph_mmio(priv, oclass->mmio); +- +- gm107_graph_init_bios(priv); +- +- nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); +- +- memset(data, 0x00, sizeof(data)); +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- for (i = 0, gpc = -1; i < priv->tpc_total; i++) { +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; +- +- data[i / 8] |= tpc << ((i % 8) * 4); +- } +- +- nv_wr32(priv, GPC_BCAST(0x0980), data[0]); +- nv_wr32(priv, GPC_BCAST(0x0984), data[1]); +- nv_wr32(priv, GPC_BCAST(0x0988), data[2]); +- nv_wr32(priv, GPC_BCAST(0x098c), data[3]); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- nv_wr32(priv, GPC_UNIT(gpc, 0x0914), +- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | +- priv->tpc_total); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); +- } +- +- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); +- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); +- +- nv_wr32(priv, 0x400500, 0x00010001); +- +- nv_wr32(priv, 0x400100, 0xffffffff); +- nv_wr32(priv, 0x40013c, 0xffffffff); +- nv_wr32(priv, 0x400124, 0x00000002); +- nv_wr32(priv, 0x409c24, 0x000e0000); +- +- nv_wr32(priv, 0x404000, 0xc0000000); +- nv_wr32(priv, 0x404600, 0xc0000000); +- nv_wr32(priv, 0x408030, 0xc0000000); +- nv_wr32(priv, 0x404490, 0xc0000000); +- nv_wr32(priv, 0x406018, 0xc0000000); +- nv_wr32(priv, 0x407020, 0x40000000); +- nv_wr32(priv, 0x405840, 0xc0000000); +- nv_wr32(priv, 0x405844, 0x00ffffff); +- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- for (ppc = 0; ppc < 2 /* priv->ppc_nr[gpc] */; ppc++) +- nv_wr32(priv, PPC_UNIT(gpc, ppc, 0x038), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); +- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x430), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x00dffffe); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x00000005); +- } +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); +- } +- +- for (rop = 0; rop < priv->rop_nr; rop++) { +- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0x40000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0x40000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); +- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); +- } +- +- nv_wr32(priv, 0x400108, 0xffffffff); +- nv_wr32(priv, 0x400138, 0xffffffff); +- nv_wr32(priv, 0x400118, 0xffffffff); +- nv_wr32(priv, 0x400130, 0xffffffff); +- nv_wr32(priv, 0x40011c, 0xffffffff); +- nv_wr32(priv, 0x400134, 0xffffffff); +- +- nv_wr32(priv, 0x400054, 0x2c350f63); +- +- nvc0_graph_zbc_init(priv); +- +- return nvc0_graph_init_ctxctl(priv); +-} +- +-#include "fuc/hubgm107.fuc5.h" +- +-static struct nvc0_graph_ucode +-gm107_graph_fecs_ucode = { +- .code.data = gm107_grhub_code, +- .code.size = sizeof(gm107_grhub_code), +- .data.data = gm107_grhub_data, +- .data.size = sizeof(gm107_grhub_data), +-}; +- +-#include "fuc/gpcgm107.fuc5.h" +- +-static struct nvc0_graph_ucode +-gm107_graph_gpccs_ucode = { +- .code.data = gm107_grgpc_code, +- .code.size = sizeof(gm107_grgpc_code), +- .data.data = gm107_grgpc_data, +- .data.size = sizeof(gm107_grgpc_data), +-}; +- +-struct nouveau_oclass * +-gm107_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0x07), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = gm107_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &gm107_grctx_oclass, +- .sclass = gm107_graph_sclass, +- .mmio = gm107_graph_pack_mmio, +- .fecs.ucode = 0 ? &gm107_graph_fecs_ucode : NULL, +- .gpccs.ucode = &gm107_graph_gpccs_ucode, +- .ppc_nr = 2, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c +deleted file mode 100644 +index f70e2f67..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv04.c ++++ /dev/null +@@ -1,1388 +0,0 @@ +-/* +- * Copyright 2007 Stephane Marchesin +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +-#include +- +-#include "regs.h" +- +-static u32 +-nv04_graph_ctx_regs[] = { +- 0x0040053c, +- 0x00400544, +- 0x00400540, +- 0x00400548, +- NV04_PGRAPH_CTX_SWITCH1, +- NV04_PGRAPH_CTX_SWITCH2, +- NV04_PGRAPH_CTX_SWITCH3, +- NV04_PGRAPH_CTX_SWITCH4, +- NV04_PGRAPH_CTX_CACHE1, +- NV04_PGRAPH_CTX_CACHE2, +- NV04_PGRAPH_CTX_CACHE3, +- NV04_PGRAPH_CTX_CACHE4, +- 0x00400184, +- 0x004001a4, +- 0x004001c4, +- 0x004001e4, +- 0x00400188, +- 0x004001a8, +- 0x004001c8, +- 0x004001e8, +- 0x0040018c, +- 0x004001ac, +- 0x004001cc, +- 0x004001ec, +- 0x00400190, +- 0x004001b0, +- 0x004001d0, +- 0x004001f0, +- 0x00400194, +- 0x004001b4, +- 0x004001d4, +- 0x004001f4, +- 0x00400198, +- 0x004001b8, +- 0x004001d8, +- 0x004001f8, +- 0x0040019c, +- 0x004001bc, +- 0x004001dc, +- 0x004001fc, +- 0x00400174, +- NV04_PGRAPH_DMA_START_0, +- NV04_PGRAPH_DMA_START_1, +- NV04_PGRAPH_DMA_LENGTH, +- NV04_PGRAPH_DMA_MISC, +- NV04_PGRAPH_DMA_PITCH, +- NV04_PGRAPH_BOFFSET0, +- NV04_PGRAPH_BBASE0, +- NV04_PGRAPH_BLIMIT0, +- NV04_PGRAPH_BOFFSET1, +- NV04_PGRAPH_BBASE1, +- NV04_PGRAPH_BLIMIT1, +- NV04_PGRAPH_BOFFSET2, +- NV04_PGRAPH_BBASE2, +- NV04_PGRAPH_BLIMIT2, +- NV04_PGRAPH_BOFFSET3, +- NV04_PGRAPH_BBASE3, +- NV04_PGRAPH_BLIMIT3, +- NV04_PGRAPH_BOFFSET4, +- NV04_PGRAPH_BBASE4, +- NV04_PGRAPH_BLIMIT4, +- NV04_PGRAPH_BOFFSET5, +- NV04_PGRAPH_BBASE5, +- NV04_PGRAPH_BLIMIT5, +- NV04_PGRAPH_BPITCH0, +- NV04_PGRAPH_BPITCH1, +- NV04_PGRAPH_BPITCH2, +- NV04_PGRAPH_BPITCH3, +- NV04_PGRAPH_BPITCH4, +- NV04_PGRAPH_SURFACE, +- NV04_PGRAPH_STATE, +- NV04_PGRAPH_BSWIZZLE2, +- NV04_PGRAPH_BSWIZZLE5, +- NV04_PGRAPH_BPIXEL, +- NV04_PGRAPH_NOTIFY, +- NV04_PGRAPH_PATT_COLOR0, +- NV04_PGRAPH_PATT_COLOR1, +- NV04_PGRAPH_PATT_COLORRAM+0x00, +- NV04_PGRAPH_PATT_COLORRAM+0x04, +- NV04_PGRAPH_PATT_COLORRAM+0x08, +- NV04_PGRAPH_PATT_COLORRAM+0x0c, +- NV04_PGRAPH_PATT_COLORRAM+0x10, +- NV04_PGRAPH_PATT_COLORRAM+0x14, +- NV04_PGRAPH_PATT_COLORRAM+0x18, +- NV04_PGRAPH_PATT_COLORRAM+0x1c, +- NV04_PGRAPH_PATT_COLORRAM+0x20, +- NV04_PGRAPH_PATT_COLORRAM+0x24, +- NV04_PGRAPH_PATT_COLORRAM+0x28, +- NV04_PGRAPH_PATT_COLORRAM+0x2c, +- NV04_PGRAPH_PATT_COLORRAM+0x30, +- NV04_PGRAPH_PATT_COLORRAM+0x34, +- NV04_PGRAPH_PATT_COLORRAM+0x38, +- NV04_PGRAPH_PATT_COLORRAM+0x3c, +- NV04_PGRAPH_PATT_COLORRAM+0x40, +- NV04_PGRAPH_PATT_COLORRAM+0x44, +- NV04_PGRAPH_PATT_COLORRAM+0x48, +- NV04_PGRAPH_PATT_COLORRAM+0x4c, +- NV04_PGRAPH_PATT_COLORRAM+0x50, +- NV04_PGRAPH_PATT_COLORRAM+0x54, +- NV04_PGRAPH_PATT_COLORRAM+0x58, +- NV04_PGRAPH_PATT_COLORRAM+0x5c, +- NV04_PGRAPH_PATT_COLORRAM+0x60, +- NV04_PGRAPH_PATT_COLORRAM+0x64, +- NV04_PGRAPH_PATT_COLORRAM+0x68, +- NV04_PGRAPH_PATT_COLORRAM+0x6c, +- NV04_PGRAPH_PATT_COLORRAM+0x70, +- NV04_PGRAPH_PATT_COLORRAM+0x74, +- NV04_PGRAPH_PATT_COLORRAM+0x78, +- NV04_PGRAPH_PATT_COLORRAM+0x7c, +- NV04_PGRAPH_PATT_COLORRAM+0x80, +- NV04_PGRAPH_PATT_COLORRAM+0x84, +- NV04_PGRAPH_PATT_COLORRAM+0x88, +- NV04_PGRAPH_PATT_COLORRAM+0x8c, +- NV04_PGRAPH_PATT_COLORRAM+0x90, +- NV04_PGRAPH_PATT_COLORRAM+0x94, +- NV04_PGRAPH_PATT_COLORRAM+0x98, +- NV04_PGRAPH_PATT_COLORRAM+0x9c, +- NV04_PGRAPH_PATT_COLORRAM+0xa0, +- NV04_PGRAPH_PATT_COLORRAM+0xa4, +- NV04_PGRAPH_PATT_COLORRAM+0xa8, +- NV04_PGRAPH_PATT_COLORRAM+0xac, +- NV04_PGRAPH_PATT_COLORRAM+0xb0, +- NV04_PGRAPH_PATT_COLORRAM+0xb4, +- NV04_PGRAPH_PATT_COLORRAM+0xb8, +- NV04_PGRAPH_PATT_COLORRAM+0xbc, +- NV04_PGRAPH_PATT_COLORRAM+0xc0, +- NV04_PGRAPH_PATT_COLORRAM+0xc4, +- NV04_PGRAPH_PATT_COLORRAM+0xc8, +- NV04_PGRAPH_PATT_COLORRAM+0xcc, +- NV04_PGRAPH_PATT_COLORRAM+0xd0, +- NV04_PGRAPH_PATT_COLORRAM+0xd4, +- NV04_PGRAPH_PATT_COLORRAM+0xd8, +- NV04_PGRAPH_PATT_COLORRAM+0xdc, +- NV04_PGRAPH_PATT_COLORRAM+0xe0, +- NV04_PGRAPH_PATT_COLORRAM+0xe4, +- NV04_PGRAPH_PATT_COLORRAM+0xe8, +- NV04_PGRAPH_PATT_COLORRAM+0xec, +- NV04_PGRAPH_PATT_COLORRAM+0xf0, +- NV04_PGRAPH_PATT_COLORRAM+0xf4, +- NV04_PGRAPH_PATT_COLORRAM+0xf8, +- NV04_PGRAPH_PATT_COLORRAM+0xfc, +- NV04_PGRAPH_PATTERN, +- 0x0040080c, +- NV04_PGRAPH_PATTERN_SHAPE, +- 0x00400600, +- NV04_PGRAPH_ROP3, +- NV04_PGRAPH_CHROMA, +- NV04_PGRAPH_BETA_AND, +- NV04_PGRAPH_BETA_PREMULT, +- NV04_PGRAPH_CONTROL0, +- NV04_PGRAPH_CONTROL1, +- NV04_PGRAPH_CONTROL2, +- NV04_PGRAPH_BLEND, +- NV04_PGRAPH_STORED_FMT, +- NV04_PGRAPH_SOURCE_COLOR, +- 0x00400560, +- 0x00400568, +- 0x00400564, +- 0x0040056c, +- 0x00400400, +- 0x00400480, +- 0x00400404, +- 0x00400484, +- 0x00400408, +- 0x00400488, +- 0x0040040c, +- 0x0040048c, +- 0x00400410, +- 0x00400490, +- 0x00400414, +- 0x00400494, +- 0x00400418, +- 0x00400498, +- 0x0040041c, +- 0x0040049c, +- 0x00400420, +- 0x004004a0, +- 0x00400424, +- 0x004004a4, +- 0x00400428, +- 0x004004a8, +- 0x0040042c, +- 0x004004ac, +- 0x00400430, +- 0x004004b0, +- 0x00400434, +- 0x004004b4, +- 0x00400438, +- 0x004004b8, +- 0x0040043c, +- 0x004004bc, +- 0x00400440, +- 0x004004c0, +- 0x00400444, +- 0x004004c4, +- 0x00400448, +- 0x004004c8, +- 0x0040044c, +- 0x004004cc, +- 0x00400450, +- 0x004004d0, +- 0x00400454, +- 0x004004d4, +- 0x00400458, +- 0x004004d8, +- 0x0040045c, +- 0x004004dc, +- 0x00400460, +- 0x004004e0, +- 0x00400464, +- 0x004004e4, +- 0x00400468, +- 0x004004e8, +- 0x0040046c, +- 0x004004ec, +- 0x00400470, +- 0x004004f0, +- 0x00400474, +- 0x004004f4, +- 0x00400478, +- 0x004004f8, +- 0x0040047c, +- 0x004004fc, +- 0x00400534, +- 0x00400538, +- 0x00400514, +- 0x00400518, +- 0x0040051c, +- 0x00400520, +- 0x00400524, +- 0x00400528, +- 0x0040052c, +- 0x00400530, +- 0x00400d00, +- 0x00400d40, +- 0x00400d80, +- 0x00400d04, +- 0x00400d44, +- 0x00400d84, +- 0x00400d08, +- 0x00400d48, +- 0x00400d88, +- 0x00400d0c, +- 0x00400d4c, +- 0x00400d8c, +- 0x00400d10, +- 0x00400d50, +- 0x00400d90, +- 0x00400d14, +- 0x00400d54, +- 0x00400d94, +- 0x00400d18, +- 0x00400d58, +- 0x00400d98, +- 0x00400d1c, +- 0x00400d5c, +- 0x00400d9c, +- 0x00400d20, +- 0x00400d60, +- 0x00400da0, +- 0x00400d24, +- 0x00400d64, +- 0x00400da4, +- 0x00400d28, +- 0x00400d68, +- 0x00400da8, +- 0x00400d2c, +- 0x00400d6c, +- 0x00400dac, +- 0x00400d30, +- 0x00400d70, +- 0x00400db0, +- 0x00400d34, +- 0x00400d74, +- 0x00400db4, +- 0x00400d38, +- 0x00400d78, +- 0x00400db8, +- 0x00400d3c, +- 0x00400d7c, +- 0x00400dbc, +- 0x00400590, +- 0x00400594, +- 0x00400598, +- 0x0040059c, +- 0x004005a8, +- 0x004005ac, +- 0x004005b0, +- 0x004005b4, +- 0x004005c0, +- 0x004005c4, +- 0x004005c8, +- 0x004005cc, +- 0x004005d0, +- 0x004005d4, +- 0x004005d8, +- 0x004005dc, +- 0x004005e0, +- NV04_PGRAPH_PASSTHRU_0, +- NV04_PGRAPH_PASSTHRU_1, +- NV04_PGRAPH_PASSTHRU_2, +- NV04_PGRAPH_DVD_COLORFMT, +- NV04_PGRAPH_SCALED_FORMAT, +- NV04_PGRAPH_MISC24_0, +- NV04_PGRAPH_MISC24_1, +- NV04_PGRAPH_MISC24_2, +- 0x00400500, +- 0x00400504, +- NV04_PGRAPH_VALID1, +- NV04_PGRAPH_VALID2, +- NV04_PGRAPH_DEBUG_3 +-}; +- +-struct nv04_graph_priv { +- struct nouveau_graph base; +- struct nv04_graph_chan *chan[16]; +- spinlock_t lock; +-}; +- +-struct nv04_graph_chan { +- struct nouveau_object base; +- int chid; +- u32 nv04[ARRAY_SIZE(nv04_graph_ctx_regs)]; +-}; +- +- +-static inline struct nv04_graph_priv * +-nv04_graph_priv(struct nv04_graph_chan *chan) +-{ +- return (void *)nv_object(chan)->engine; +-} +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-/* +- * Software methods, why they are needed, and how they all work: +- * +- * NV04 and NV05 keep most of the state in PGRAPH context itself, but some +- * 2d engine settings are kept inside the grobjs themselves. The grobjs are +- * 3 words long on both. grobj format on NV04 is: +- * +- * word 0: +- * - bits 0-7: class +- * - bit 12: color key active +- * - bit 13: clip rect active +- * - bit 14: if set, destination surface is swizzled and taken from buffer 5 +- * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken +- * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or +- * NV03_CONTEXT_SURFACE_DST]. +- * - bits 15-17: 2d operation [aka patch config] +- * - bit 24: patch valid [enables rendering using this object] +- * - bit 25: surf3d valid [for tex_tri and multitex_tri only] +- * word 1: +- * - bits 0-1: mono format +- * - bits 8-13: color format +- * - bits 16-31: DMA_NOTIFY instance +- * word 2: +- * - bits 0-15: DMA_A instance +- * - bits 16-31: DMA_B instance +- * +- * On NV05 it's: +- * +- * word 0: +- * - bits 0-7: class +- * - bit 12: color key active +- * - bit 13: clip rect active +- * - bit 14: if set, destination surface is swizzled and taken from buffer 5 +- * [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken +- * from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or +- * NV03_CONTEXT_SURFACE_DST]. +- * - bits 15-17: 2d operation [aka patch config] +- * - bits 20-22: dither mode +- * - bit 24: patch valid [enables rendering using this object] +- * - bit 25: surface_dst/surface_color/surf2d/surf3d valid +- * - bit 26: surface_src/surface_zeta valid +- * - bit 27: pattern valid +- * - bit 28: rop valid +- * - bit 29: beta1 valid +- * - bit 30: beta4 valid +- * word 1: +- * - bits 0-1: mono format +- * - bits 8-13: color format +- * - bits 16-31: DMA_NOTIFY instance +- * word 2: +- * - bits 0-15: DMA_A instance +- * - bits 16-31: DMA_B instance +- * +- * NV05 will set/unset the relevant valid bits when you poke the relevant +- * object-binding methods with object of the proper type, or with the NULL +- * type. It'll only allow rendering using the grobj if all needed objects +- * are bound. The needed set of objects depends on selected operation: for +- * example rop object is needed by ROP_AND, but not by SRCCOPY_AND. +- * +- * NV04 doesn't have these methods implemented at all, and doesn't have the +- * relevant bits in grobj. Instead, it'll allow rendering whenever bit 24 +- * is set. So we have to emulate them in software, internally keeping the +- * same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04, +- * but the last word isn't actually used for anything, we abuse it for this +- * purpose. +- * +- * Actually, NV05 can optionally check bit 24 too, but we disable this since +- * there's no use for it. +- * +- * For unknown reasons, NV04 implements surf3d binding in hardware as an +- * exception. Also for unknown reasons, NV04 doesn't implement the clipping +- * methods on the surf3d object, so we have to emulate them too. +- */ +- +-static void +-nv04_graph_set_ctx1(struct nouveau_object *object, u32 mask, u32 value) +-{ +- struct nv04_graph_priv *priv = (void *)object->engine; +- int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7; +- u32 tmp; +- +- tmp = nv_ro32(object, 0x00); +- tmp &= ~mask; +- tmp |= value; +- nv_wo32(object, 0x00, tmp); +- +- nv_wr32(priv, NV04_PGRAPH_CTX_SWITCH1, tmp); +- nv_wr32(priv, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp); +-} +- +-static void +-nv04_graph_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value) +-{ +- int class, op, valid = 1; +- u32 tmp, ctx1; +- +- ctx1 = nv_ro32(object, 0x00); +- class = ctx1 & 0xff; +- op = (ctx1 >> 15) & 7; +- +- tmp = nv_ro32(object, 0x0c); +- tmp &= ~mask; +- tmp |= value; +- nv_wo32(object, 0x0c, tmp); +- +- /* check for valid surf2d/surf_dst/surf_color */ +- if (!(tmp & 0x02000000)) +- valid = 0; +- /* check for valid surf_src/surf_zeta */ +- if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000)) +- valid = 0; +- +- switch (op) { +- /* SRCCOPY_AND, SRCCOPY: no extra objects required */ +- case 0: +- case 3: +- break; +- /* ROP_AND: requires pattern and rop */ +- case 1: +- if (!(tmp & 0x18000000)) +- valid = 0; +- break; +- /* BLEND_AND: requires beta1 */ +- case 2: +- if (!(tmp & 0x20000000)) +- valid = 0; +- break; +- /* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */ +- case 4: +- case 5: +- if (!(tmp & 0x40000000)) +- valid = 0; +- break; +- } +- +- nv04_graph_set_ctx1(object, 0x01000000, valid << 24); +-} +- +-static int +-nv04_graph_mthd_set_operation(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- u32 class = nv_ro32(object, 0) & 0xff; +- u32 data = *(u32 *)args; +- if (data > 5) +- return 1; +- /* Old versions of the objects only accept first three operations. */ +- if (data > 2 && class < 0x40) +- return 1; +- nv04_graph_set_ctx1(object, 0x00038000, data << 15); +- /* changing operation changes set of objects needed for validation */ +- nv04_graph_set_ctx_val(object, 0, 0); +- return 0; +-} +- +-static int +-nv04_graph_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv04_graph_priv *priv = (void *)object->engine; +- u32 data = *(u32 *)args; +- u32 min = data & 0xffff, max; +- u32 w = data >> 16; +- if (min & 0x8000) +- /* too large */ +- return 1; +- if (w & 0x8000) +- /* yes, it accepts negative for some reason. */ +- w |= 0xffff0000; +- max = min + w; +- max &= 0x3ffff; +- nv_wr32(priv, 0x40053c, min); +- nv_wr32(priv, 0x400544, max); +- return 0; +-} +- +-static int +-nv04_graph_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv04_graph_priv *priv = (void *)object->engine; +- u32 data = *(u32 *)args; +- u32 min = data & 0xffff, max; +- u32 w = data >> 16; +- if (min & 0x8000) +- /* too large */ +- return 1; +- if (w & 0x8000) +- /* yes, it accepts negative for some reason. */ +- w |= 0xffff0000; +- max = min + w; +- max &= 0x3ffff; +- nv_wr32(priv, 0x400540, min); +- nv_wr32(priv, 0x400548, max); +- return 0; +-} +- +-static u16 +-nv04_graph_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size) +-{ +- struct nouveau_instmem *imem = nouveau_instmem(object); +- u32 inst = *(u32 *)args << 4; +- return nv_ro32(imem, inst); +-} +- +-static int +-nv04_graph_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx1(object, 0x00004000, 0); +- nv04_graph_set_ctx_val(object, 0x02000000, 0); +- return 0; +- case 0x42: +- nv04_graph_set_ctx1(object, 0x00004000, 0); +- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx1(object, 0x00004000, 0); +- nv04_graph_set_ctx_val(object, 0x02000000, 0); +- return 0; +- case 0x42: +- nv04_graph_set_ctx1(object, 0x00004000, 0); +- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); +- return 0; +- case 0x52: +- nv04_graph_set_ctx1(object, 0x00004000, 0x00004000); +- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv01_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x08000000, 0); +- return 0; +- case 0x18: +- nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_patt(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x08000000, 0); +- return 0; +- case 0x44: +- nv04_graph_set_ctx_val(object, 0x08000000, 0x08000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_rop(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x10000000, 0); +- return 0; +- case 0x43: +- nv04_graph_set_ctx_val(object, 0x10000000, 0x10000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_beta1(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x20000000, 0); +- return 0; +- case 0x12: +- nv04_graph_set_ctx_val(object, 0x20000000, 0x20000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_beta4(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x40000000, 0); +- return 0; +- case 0x72: +- nv04_graph_set_ctx_val(object, 0x40000000, 0x40000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x02000000, 0); +- return 0; +- case 0x58: +- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x04000000, 0); +- return 0; +- case 0x59: +- nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x02000000, 0); +- return 0; +- case 0x5a: +- nv04_graph_set_ctx_val(object, 0x02000000, 0x02000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv04_graph_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx_val(object, 0x04000000, 0); +- return 0; +- case 0x5b: +- nv04_graph_set_ctx_val(object, 0x04000000, 0x04000000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv01_graph_mthd_bind_clip(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx1(object, 0x2000, 0); +- return 0; +- case 0x19: +- nv04_graph_set_ctx1(object, 0x2000, 0x2000); +- return 0; +- } +- return 1; +-} +- +-static int +-nv01_graph_mthd_bind_chroma(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- switch (nv04_graph_mthd_bind_class(object, args, size)) { +- case 0x30: +- nv04_graph_set_ctx1(object, 0x1000, 0); +- return 0; +- /* Yes, for some reason even the old versions of objects +- * accept 0x57 and not 0x17. Consistency be damned. +- */ +- case 0x57: +- nv04_graph_set_ctx1(object, 0x1000, 0x1000); +- return 0; +- } +- return 1; +-} +- +-static struct nouveau_omthds +-nv03_graph_gdi_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_patt }, +- { 0x0188, 0x0188, nv04_graph_mthd_bind_rop }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_beta1 }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_dst }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_gdi_omthds[] = { +- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv01_graph_blit_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, +- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, +- { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, +- { 0x019c, 0x019c, nv04_graph_mthd_bind_surf_src }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_blit_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, +- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, +- { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_iifc_omthds[] = { +- { 0x0188, 0x0188, nv01_graph_mthd_bind_chroma }, +- { 0x018c, 0x018c, nv01_graph_mthd_bind_clip }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_patt }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_rop }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_beta1 }, +- { 0x019c, 0x019c, nv04_graph_mthd_bind_beta4 }, +- { 0x01a0, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf }, +- { 0x03e4, 0x03e4, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv01_graph_ifc_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, +- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, +- { 0x018c, 0x018c, nv01_graph_mthd_bind_patt }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf_dst }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_ifc_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, +- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_patt }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_rop }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta1 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_beta4 }, +- { 0x019c, 0x019c, nv04_graph_mthd_bind_surf2d }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv03_graph_sifc_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, +- { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_sifc_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_chroma }, +- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv03_graph_sifm_omthds[] = { +- { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, +- { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_sifm_omthds[] = { +- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, +- { 0x0304, 0x0304, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_surf3d_omthds[] = { +- { 0x02f8, 0x02f8, nv04_graph_mthd_surf3d_clip_h }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_surf3d_clip_v }, +- {} +-}; +- +-static struct nouveau_omthds +-nv03_graph_ttri_omthds[] = { +- { 0x0188, 0x0188, nv01_graph_mthd_bind_clip }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_surf_color }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_surf_zeta }, +- {} +-}; +- +-static struct nouveau_omthds +-nv01_graph_prim_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, +- { 0x0188, 0x0188, nv01_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_surf_dst }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static struct nouveau_omthds +-nv04_graph_prim_omthds[] = { +- { 0x0184, 0x0184, nv01_graph_mthd_bind_clip }, +- { 0x0188, 0x0188, nv04_graph_mthd_bind_patt }, +- { 0x018c, 0x018c, nv04_graph_mthd_bind_rop }, +- { 0x0190, 0x0190, nv04_graph_mthd_bind_beta1 }, +- { 0x0194, 0x0194, nv04_graph_mthd_bind_beta4 }, +- { 0x0198, 0x0198, nv04_graph_mthd_bind_surf2d }, +- { 0x02fc, 0x02fc, nv04_graph_mthd_set_operation }, +- {} +-}; +- +-static int +-nv04_graph_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj *obj; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, +- 16, 16, 0, &obj); +- *pobject = nv_object(obj); +- if (ret) +- return ret; +- +- nv_wo32(obj, 0x00, nv_mclass(obj)); +-#ifdef __BIG_ENDIAN +- nv_mo32(obj, 0x00, 0x00080000, 0x00080000); +-#endif +- nv_wo32(obj, 0x04, 0x00000000); +- nv_wo32(obj, 0x08, 0x00000000); +- nv_wo32(obj, 0x0c, 0x00000000); +- return 0; +-} +- +-struct nouveau_ofuncs +-nv04_graph_ofuncs = { +- .ctor = nv04_graph_object_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +-}; +- +-static struct nouveau_oclass +-nv04_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ +- { 0x0017, &nv04_graph_ofuncs }, /* chroma */ +- { 0x0018, &nv04_graph_ofuncs }, /* pattern (nv01) */ +- { 0x0019, &nv04_graph_ofuncs }, /* clip */ +- { 0x001c, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* line */ +- { 0x001d, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* tri */ +- { 0x001e, &nv04_graph_ofuncs, nv01_graph_prim_omthds }, /* rect */ +- { 0x001f, &nv04_graph_ofuncs, nv01_graph_blit_omthds }, +- { 0x0021, &nv04_graph_ofuncs, nv01_graph_ifc_omthds }, +- { 0x0030, &nv04_graph_ofuncs }, /* null */ +- { 0x0036, &nv04_graph_ofuncs, nv03_graph_sifc_omthds }, +- { 0x0037, &nv04_graph_ofuncs, nv03_graph_sifm_omthds }, +- { 0x0038, &nv04_graph_ofuncs }, /* dvd subpicture */ +- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ +- { 0x0042, &nv04_graph_ofuncs }, /* surf2d */ +- { 0x0043, &nv04_graph_ofuncs }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs }, /* pattern */ +- { 0x0048, &nv04_graph_ofuncs, nv03_graph_ttri_omthds }, +- { 0x004a, &nv04_graph_ofuncs, nv04_graph_gdi_omthds }, +- { 0x004b, &nv04_graph_ofuncs, nv03_graph_gdi_omthds }, +- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ +- { 0x0053, &nv04_graph_ofuncs, nv04_graph_surf3d_omthds }, +- { 0x0054, &nv04_graph_ofuncs }, /* ttri */ +- { 0x0055, &nv04_graph_ofuncs }, /* mtri */ +- { 0x0057, &nv04_graph_ofuncs }, /* chroma */ +- { 0x0058, &nv04_graph_ofuncs }, /* surf_dst */ +- { 0x0059, &nv04_graph_ofuncs }, /* surf_src */ +- { 0x005a, &nv04_graph_ofuncs }, /* surf_color */ +- { 0x005b, &nv04_graph_ofuncs }, /* surf_zeta */ +- { 0x005c, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* line */ +- { 0x005d, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* tri */ +- { 0x005e, &nv04_graph_ofuncs, nv04_graph_prim_omthds }, /* rect */ +- { 0x005f, &nv04_graph_ofuncs, nv04_graph_blit_omthds }, +- { 0x0060, &nv04_graph_ofuncs, nv04_graph_iifc_omthds }, +- { 0x0061, &nv04_graph_ofuncs, nv04_graph_ifc_omthds }, +- { 0x0064, &nv04_graph_ofuncs }, /* iifc (nv05) */ +- { 0x0065, &nv04_graph_ofuncs }, /* ifc (nv05) */ +- { 0x0066, &nv04_graph_ofuncs }, /* sifc (nv05) */ +- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ +- { 0x0076, &nv04_graph_ofuncs, nv04_graph_sifc_omthds }, +- { 0x0077, &nv04_graph_ofuncs, nv04_graph_sifm_omthds }, +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static struct nv04_graph_chan * +-nv04_graph_channel(struct nv04_graph_priv *priv) +-{ +- struct nv04_graph_chan *chan = NULL; +- if (nv_rd32(priv, NV04_PGRAPH_CTX_CONTROL) & 0x00010000) { +- int chid = nv_rd32(priv, NV04_PGRAPH_CTX_USER) >> 24; +- if (chid < ARRAY_SIZE(priv->chan)) +- chan = priv->chan[chid]; +- } +- return chan; +-} +- +-static int +-nv04_graph_load_context(struct nv04_graph_chan *chan, int chid) +-{ +- struct nv04_graph_priv *priv = nv04_graph_priv(chan); +- int i; +- +- for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) +- nv_wr32(priv, nv04_graph_ctx_regs[i], chan->nv04[i]); +- +- nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10010100); +- nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, chid << 24); +- nv_mask(priv, NV04_PGRAPH_FFINTFC_ST2, 0xfff00000, 0x00000000); +- return 0; +-} +- +-static int +-nv04_graph_unload_context(struct nv04_graph_chan *chan) +-{ +- struct nv04_graph_priv *priv = nv04_graph_priv(chan); +- int i; +- +- for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) +- chan->nv04[i] = nv_rd32(priv, nv04_graph_ctx_regs[i]); +- +- nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL, 0x10000000); +- nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); +- return 0; +-} +- +-static void +-nv04_graph_context_switch(struct nv04_graph_priv *priv) +-{ +- struct nv04_graph_chan *prev = NULL; +- struct nv04_graph_chan *next = NULL; +- unsigned long flags; +- int chid; +- +- spin_lock_irqsave(&priv->lock, flags); +- nv04_graph_idle(priv); +- +- /* If previous context is valid, we need to save it */ +- prev = nv04_graph_channel(priv); +- if (prev) +- nv04_graph_unload_context(prev); +- +- /* load context for next channel */ +- chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0x0f; +- next = priv->chan[chid]; +- if (next) +- nv04_graph_load_context(next, chid); +- +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-static u32 *ctx_reg(struct nv04_graph_chan *chan, u32 reg) +-{ +- int i; +- +- for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) { +- if (nv04_graph_ctx_regs[i] == reg) +- return &chan->nv04[i]; +- } +- +- return NULL; +-} +- +-static int +-nv04_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fifo_chan *fifo = (void *)parent; +- struct nv04_graph_priv *priv = (void *)engine; +- struct nv04_graph_chan *chan; +- unsigned long flags; +- int ret; +- +- ret = nouveau_object_create(parent, engine, oclass, 0, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- spin_lock_irqsave(&priv->lock, flags); +- if (priv->chan[fifo->chid]) { +- *pobject = nv_object(priv->chan[fifo->chid]); +- atomic_inc(&(*pobject)->refcount); +- spin_unlock_irqrestore(&priv->lock, flags); +- nouveau_object_destroy(&chan->base); +- return 1; +- } +- +- *ctx_reg(chan, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31; +- +- priv->chan[fifo->chid] = chan; +- chan->chid = fifo->chid; +- spin_unlock_irqrestore(&priv->lock, flags); +- return 0; +-} +- +-static void +-nv04_graph_context_dtor(struct nouveau_object *object) +-{ +- struct nv04_graph_priv *priv = (void *)object->engine; +- struct nv04_graph_chan *chan = (void *)object; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->lock, flags); +- priv->chan[chan->chid] = NULL; +- spin_unlock_irqrestore(&priv->lock, flags); +- +- nouveau_object_destroy(&chan->base); +-} +- +-static int +-nv04_graph_context_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv04_graph_priv *priv = (void *)object->engine; +- struct nv04_graph_chan *chan = (void *)object; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->lock, flags); +- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); +- if (nv04_graph_channel(priv) == chan) +- nv04_graph_unload_context(chan); +- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); +- spin_unlock_irqrestore(&priv->lock, flags); +- +- return nouveau_object_fini(&chan->base, suspend); +-} +- +-static struct nouveau_oclass +-nv04_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_graph_context_ctor, +- .dtor = nv04_graph_context_dtor, +- .init = nouveau_object_init, +- .fini = nv04_graph_context_fini, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-bool +-nv04_graph_idle(void *obj) +-{ +- struct nouveau_graph *graph = nouveau_graph(obj); +- u32 mask = 0xffffffff; +- +- if (nv_device(obj)->card_type == NV_40) +- mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; +- +- if (!nv_wait(graph, NV04_PGRAPH_STATUS, mask, 0)) { +- nv_error(graph, "idle timed out with status 0x%08x\n", +- nv_rd32(graph, NV04_PGRAPH_STATUS)); +- return false; +- } +- +- return true; +-} +- +-static const struct nouveau_bitfield +-nv04_graph_intr_name[] = { +- { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, +- {} +-}; +- +-static const struct nouveau_bitfield +-nv04_graph_nstatus[] = { +- { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, +- { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, +- { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, +- { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }, +- {} +-}; +- +-const struct nouveau_bitfield +-nv04_graph_nsource[] = { +- { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" }, +- { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" }, +- { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" }, +- { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" }, +- { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" }, +- { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" }, +- { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" }, +- { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" }, +- { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" }, +- { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" }, +- { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" }, +- { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" }, +- { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" }, +- { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" }, +- { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" }, +- { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" }, +- { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" }, +- { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" }, +- { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" }, +- {} +-}; +- +-static void +-nv04_graph_intr(struct nouveau_subdev *subdev) +-{ +- struct nv04_graph_priv *priv = (void *)subdev; +- struct nv04_graph_chan *chan = NULL; +- struct nouveau_namedb *namedb = NULL; +- struct nouveau_handle *handle = NULL; +- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); +- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); +- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); +- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); +- u32 chid = (addr & 0x0f000000) >> 24; +- u32 subc = (addr & 0x0000e000) >> 13; +- u32 mthd = (addr & 0x00001ffc); +- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); +- u32 class = nv_rd32(priv, 0x400180 + subc * 4) & 0xff; +- u32 inst = (nv_rd32(priv, 0x40016c) & 0xffff) << 4; +- u32 show = stat; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->lock, flags); +- chan = priv->chan[chid]; +- if (chan) +- namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); +- spin_unlock_irqrestore(&priv->lock, flags); +- +- if (stat & NV_PGRAPH_INTR_NOTIFY) { +- if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { +- handle = nouveau_namedb_get_vinst(namedb, inst); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~NV_PGRAPH_INTR_NOTIFY; +- } +- } +- +- if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { +- nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); +- stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; +- show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; +- nv04_graph_context_switch(priv); +- } +- +- nv_wr32(priv, NV03_PGRAPH_INTR, stat); +- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); +- +- if (show) { +- nv_error(priv, "%s", ""); +- nouveau_bitfield_print(nv04_graph_intr_name, show); +- pr_cont(" nsource:"); +- nouveau_bitfield_print(nv04_graph_nsource, nsource); +- pr_cont(" nstatus:"); +- nouveau_bitfield_print(nv04_graph_nstatus, nstatus); +- pr_cont("\n"); +- nv_error(priv, +- "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, nouveau_client_name(chan), subc, class, mthd, +- data); +- } +- +- nouveau_namedb_put(handle); +-} +- +-static int +-nv04_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv04_graph_intr; +- nv_engine(priv)->cclass = &nv04_graph_cclass; +- nv_engine(priv)->sclass = nv04_graph_sclass; +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-static int +-nv04_graph_init(struct nouveau_object *object) +-{ +- struct nouveau_engine *engine = nv_engine(object); +- struct nv04_graph_priv *priv = (void *)engine; +- int ret; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- /* Enable PGRAPH interrupts */ +- nv_wr32(priv, NV03_PGRAPH_INTR, 0xFFFFFFFF); +- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); +- +- nv_wr32(priv, NV04_PGRAPH_VALID1, 0); +- nv_wr32(priv, NV04_PGRAPH_VALID2, 0); +- /*nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x000001FF); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/ +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x1231c000); +- /*1231C000 blob, 001 haiku*/ +- /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/ +- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x72111100); +- /*0x72111100 blob , 01 haiku*/ +- /*nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/ +- nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x11d5f071); +- /*haiku same*/ +- +- /*nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/ +- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31); +- /*haiku and blob 10d4*/ +- +- nv_wr32(priv, NV04_PGRAPH_STATE , 0xFFFFFFFF); +- nv_wr32(priv, NV04_PGRAPH_CTX_CONTROL , 0x10000100); +- nv_mask(priv, NV04_PGRAPH_CTX_USER, 0xff000000, 0x0f000000); +- +- /* These don't belong here, they're part of a per-channel context */ +- nv_wr32(priv, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000); +- nv_wr32(priv, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF); +- return 0; +-} +- +-struct nouveau_oclass +-nv04_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_graph_ctor, +- .dtor = _nouveau_graph_dtor, +- .init = nv04_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c +deleted file mode 100644 +index 2b12b096..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv10.c ++++ /dev/null +@@ -1,1319 +0,0 @@ +-/* +- * Copyright 2007 Matthieu CASTET +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +- +-#include +- +-#include +-#include +- +-#include "regs.h" +- +-struct pipe_state { +- u32 pipe_0x0000[0x040/4]; +- u32 pipe_0x0040[0x010/4]; +- u32 pipe_0x0200[0x0c0/4]; +- u32 pipe_0x4400[0x080/4]; +- u32 pipe_0x6400[0x3b0/4]; +- u32 pipe_0x6800[0x2f0/4]; +- u32 pipe_0x6c00[0x030/4]; +- u32 pipe_0x7000[0x130/4]; +- u32 pipe_0x7400[0x0c0/4]; +- u32 pipe_0x7800[0x0c0/4]; +-}; +- +-static int nv10_graph_ctx_regs[] = { +- NV10_PGRAPH_CTX_SWITCH(0), +- NV10_PGRAPH_CTX_SWITCH(1), +- NV10_PGRAPH_CTX_SWITCH(2), +- NV10_PGRAPH_CTX_SWITCH(3), +- NV10_PGRAPH_CTX_SWITCH(4), +- NV10_PGRAPH_CTX_CACHE(0, 0), +- NV10_PGRAPH_CTX_CACHE(0, 1), +- NV10_PGRAPH_CTX_CACHE(0, 2), +- NV10_PGRAPH_CTX_CACHE(0, 3), +- NV10_PGRAPH_CTX_CACHE(0, 4), +- NV10_PGRAPH_CTX_CACHE(1, 0), +- NV10_PGRAPH_CTX_CACHE(1, 1), +- NV10_PGRAPH_CTX_CACHE(1, 2), +- NV10_PGRAPH_CTX_CACHE(1, 3), +- NV10_PGRAPH_CTX_CACHE(1, 4), +- NV10_PGRAPH_CTX_CACHE(2, 0), +- NV10_PGRAPH_CTX_CACHE(2, 1), +- NV10_PGRAPH_CTX_CACHE(2, 2), +- NV10_PGRAPH_CTX_CACHE(2, 3), +- NV10_PGRAPH_CTX_CACHE(2, 4), +- NV10_PGRAPH_CTX_CACHE(3, 0), +- NV10_PGRAPH_CTX_CACHE(3, 1), +- NV10_PGRAPH_CTX_CACHE(3, 2), +- NV10_PGRAPH_CTX_CACHE(3, 3), +- NV10_PGRAPH_CTX_CACHE(3, 4), +- NV10_PGRAPH_CTX_CACHE(4, 0), +- NV10_PGRAPH_CTX_CACHE(4, 1), +- NV10_PGRAPH_CTX_CACHE(4, 2), +- NV10_PGRAPH_CTX_CACHE(4, 3), +- NV10_PGRAPH_CTX_CACHE(4, 4), +- NV10_PGRAPH_CTX_CACHE(5, 0), +- NV10_PGRAPH_CTX_CACHE(5, 1), +- NV10_PGRAPH_CTX_CACHE(5, 2), +- NV10_PGRAPH_CTX_CACHE(5, 3), +- NV10_PGRAPH_CTX_CACHE(5, 4), +- NV10_PGRAPH_CTX_CACHE(6, 0), +- NV10_PGRAPH_CTX_CACHE(6, 1), +- NV10_PGRAPH_CTX_CACHE(6, 2), +- NV10_PGRAPH_CTX_CACHE(6, 3), +- NV10_PGRAPH_CTX_CACHE(6, 4), +- NV10_PGRAPH_CTX_CACHE(7, 0), +- NV10_PGRAPH_CTX_CACHE(7, 1), +- NV10_PGRAPH_CTX_CACHE(7, 2), +- NV10_PGRAPH_CTX_CACHE(7, 3), +- NV10_PGRAPH_CTX_CACHE(7, 4), +- NV10_PGRAPH_CTX_USER, +- NV04_PGRAPH_DMA_START_0, +- NV04_PGRAPH_DMA_START_1, +- NV04_PGRAPH_DMA_LENGTH, +- NV04_PGRAPH_DMA_MISC, +- NV10_PGRAPH_DMA_PITCH, +- NV04_PGRAPH_BOFFSET0, +- NV04_PGRAPH_BBASE0, +- NV04_PGRAPH_BLIMIT0, +- NV04_PGRAPH_BOFFSET1, +- NV04_PGRAPH_BBASE1, +- NV04_PGRAPH_BLIMIT1, +- NV04_PGRAPH_BOFFSET2, +- NV04_PGRAPH_BBASE2, +- NV04_PGRAPH_BLIMIT2, +- NV04_PGRAPH_BOFFSET3, +- NV04_PGRAPH_BBASE3, +- NV04_PGRAPH_BLIMIT3, +- NV04_PGRAPH_BOFFSET4, +- NV04_PGRAPH_BBASE4, +- NV04_PGRAPH_BLIMIT4, +- NV04_PGRAPH_BOFFSET5, +- NV04_PGRAPH_BBASE5, +- NV04_PGRAPH_BLIMIT5, +- NV04_PGRAPH_BPITCH0, +- NV04_PGRAPH_BPITCH1, +- NV04_PGRAPH_BPITCH2, +- NV04_PGRAPH_BPITCH3, +- NV04_PGRAPH_BPITCH4, +- NV10_PGRAPH_SURFACE, +- NV10_PGRAPH_STATE, +- NV04_PGRAPH_BSWIZZLE2, +- NV04_PGRAPH_BSWIZZLE5, +- NV04_PGRAPH_BPIXEL, +- NV10_PGRAPH_NOTIFY, +- NV04_PGRAPH_PATT_COLOR0, +- NV04_PGRAPH_PATT_COLOR1, +- NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */ +- 0x00400904, +- 0x00400908, +- 0x0040090c, +- 0x00400910, +- 0x00400914, +- 0x00400918, +- 0x0040091c, +- 0x00400920, +- 0x00400924, +- 0x00400928, +- 0x0040092c, +- 0x00400930, +- 0x00400934, +- 0x00400938, +- 0x0040093c, +- 0x00400940, +- 0x00400944, +- 0x00400948, +- 0x0040094c, +- 0x00400950, +- 0x00400954, +- 0x00400958, +- 0x0040095c, +- 0x00400960, +- 0x00400964, +- 0x00400968, +- 0x0040096c, +- 0x00400970, +- 0x00400974, +- 0x00400978, +- 0x0040097c, +- 0x00400980, +- 0x00400984, +- 0x00400988, +- 0x0040098c, +- 0x00400990, +- 0x00400994, +- 0x00400998, +- 0x0040099c, +- 0x004009a0, +- 0x004009a4, +- 0x004009a8, +- 0x004009ac, +- 0x004009b0, +- 0x004009b4, +- 0x004009b8, +- 0x004009bc, +- 0x004009c0, +- 0x004009c4, +- 0x004009c8, +- 0x004009cc, +- 0x004009d0, +- 0x004009d4, +- 0x004009d8, +- 0x004009dc, +- 0x004009e0, +- 0x004009e4, +- 0x004009e8, +- 0x004009ec, +- 0x004009f0, +- 0x004009f4, +- 0x004009f8, +- 0x004009fc, +- NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */ +- 0x0040080c, +- NV04_PGRAPH_PATTERN_SHAPE, +- NV03_PGRAPH_MONO_COLOR0, +- NV04_PGRAPH_ROP3, +- NV04_PGRAPH_CHROMA, +- NV04_PGRAPH_BETA_AND, +- NV04_PGRAPH_BETA_PREMULT, +- 0x00400e70, +- 0x00400e74, +- 0x00400e78, +- 0x00400e7c, +- 0x00400e80, +- 0x00400e84, +- 0x00400e88, +- 0x00400e8c, +- 0x00400ea0, +- 0x00400ea4, +- 0x00400ea8, +- 0x00400e90, +- 0x00400e94, +- 0x00400e98, +- 0x00400e9c, +- NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00-0x400f1c */ +- NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20-0x400f3c */ +- 0x00400f04, +- 0x00400f24, +- 0x00400f08, +- 0x00400f28, +- 0x00400f0c, +- 0x00400f2c, +- 0x00400f10, +- 0x00400f30, +- 0x00400f14, +- 0x00400f34, +- 0x00400f18, +- 0x00400f38, +- 0x00400f1c, +- 0x00400f3c, +- NV10_PGRAPH_XFMODE0, +- NV10_PGRAPH_XFMODE1, +- NV10_PGRAPH_GLOBALSTATE0, +- NV10_PGRAPH_GLOBALSTATE1, +- NV04_PGRAPH_STORED_FMT, +- NV04_PGRAPH_SOURCE_COLOR, +- NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */ +- NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */ +- 0x00400404, +- 0x00400484, +- 0x00400408, +- 0x00400488, +- 0x0040040c, +- 0x0040048c, +- 0x00400410, +- 0x00400490, +- 0x00400414, +- 0x00400494, +- 0x00400418, +- 0x00400498, +- 0x0040041c, +- 0x0040049c, +- 0x00400420, +- 0x004004a0, +- 0x00400424, +- 0x004004a4, +- 0x00400428, +- 0x004004a8, +- 0x0040042c, +- 0x004004ac, +- 0x00400430, +- 0x004004b0, +- 0x00400434, +- 0x004004b4, +- 0x00400438, +- 0x004004b8, +- 0x0040043c, +- 0x004004bc, +- 0x00400440, +- 0x004004c0, +- 0x00400444, +- 0x004004c4, +- 0x00400448, +- 0x004004c8, +- 0x0040044c, +- 0x004004cc, +- 0x00400450, +- 0x004004d0, +- 0x00400454, +- 0x004004d4, +- 0x00400458, +- 0x004004d8, +- 0x0040045c, +- 0x004004dc, +- 0x00400460, +- 0x004004e0, +- 0x00400464, +- 0x004004e4, +- 0x00400468, +- 0x004004e8, +- 0x0040046c, +- 0x004004ec, +- 0x00400470, +- 0x004004f0, +- 0x00400474, +- 0x004004f4, +- 0x00400478, +- 0x004004f8, +- 0x0040047c, +- 0x004004fc, +- NV03_PGRAPH_ABS_UCLIP_XMIN, +- NV03_PGRAPH_ABS_UCLIP_XMAX, +- NV03_PGRAPH_ABS_UCLIP_YMIN, +- NV03_PGRAPH_ABS_UCLIP_YMAX, +- 0x00400550, +- 0x00400558, +- 0x00400554, +- 0x0040055c, +- NV03_PGRAPH_ABS_UCLIPA_XMIN, +- NV03_PGRAPH_ABS_UCLIPA_XMAX, +- NV03_PGRAPH_ABS_UCLIPA_YMIN, +- NV03_PGRAPH_ABS_UCLIPA_YMAX, +- NV03_PGRAPH_ABS_ICLIP_XMAX, +- NV03_PGRAPH_ABS_ICLIP_YMAX, +- NV03_PGRAPH_XY_LOGIC_MISC0, +- NV03_PGRAPH_XY_LOGIC_MISC1, +- NV03_PGRAPH_XY_LOGIC_MISC2, +- NV03_PGRAPH_XY_LOGIC_MISC3, +- NV03_PGRAPH_CLIPX_0, +- NV03_PGRAPH_CLIPX_1, +- NV03_PGRAPH_CLIPY_0, +- NV03_PGRAPH_CLIPY_1, +- NV10_PGRAPH_COMBINER0_IN_ALPHA, +- NV10_PGRAPH_COMBINER1_IN_ALPHA, +- NV10_PGRAPH_COMBINER0_IN_RGB, +- NV10_PGRAPH_COMBINER1_IN_RGB, +- NV10_PGRAPH_COMBINER_COLOR0, +- NV10_PGRAPH_COMBINER_COLOR1, +- NV10_PGRAPH_COMBINER0_OUT_ALPHA, +- NV10_PGRAPH_COMBINER1_OUT_ALPHA, +- NV10_PGRAPH_COMBINER0_OUT_RGB, +- NV10_PGRAPH_COMBINER1_OUT_RGB, +- NV10_PGRAPH_COMBINER_FINAL0, +- NV10_PGRAPH_COMBINER_FINAL1, +- 0x00400e00, +- 0x00400e04, +- 0x00400e08, +- 0x00400e0c, +- 0x00400e10, +- 0x00400e14, +- 0x00400e18, +- 0x00400e1c, +- 0x00400e20, +- 0x00400e24, +- 0x00400e28, +- 0x00400e2c, +- 0x00400e30, +- 0x00400e34, +- 0x00400e38, +- 0x00400e3c, +- NV04_PGRAPH_PASSTHRU_0, +- NV04_PGRAPH_PASSTHRU_1, +- NV04_PGRAPH_PASSTHRU_2, +- NV10_PGRAPH_DIMX_TEXTURE, +- NV10_PGRAPH_WDIMX_TEXTURE, +- NV10_PGRAPH_DVD_COLORFMT, +- NV10_PGRAPH_SCALED_FORMAT, +- NV04_PGRAPH_MISC24_0, +- NV04_PGRAPH_MISC24_1, +- NV04_PGRAPH_MISC24_2, +- NV03_PGRAPH_X_MISC, +- NV03_PGRAPH_Y_MISC, +- NV04_PGRAPH_VALID1, +- NV04_PGRAPH_VALID2, +-}; +- +-static int nv17_graph_ctx_regs[] = { +- NV10_PGRAPH_DEBUG_4, +- 0x004006b0, +- 0x00400eac, +- 0x00400eb0, +- 0x00400eb4, +- 0x00400eb8, +- 0x00400ebc, +- 0x00400ec0, +- 0x00400ec4, +- 0x00400ec8, +- 0x00400ecc, +- 0x00400ed0, +- 0x00400ed4, +- 0x00400ed8, +- 0x00400edc, +- 0x00400ee0, +- 0x00400a00, +- 0x00400a04, +-}; +- +-struct nv10_graph_priv { +- struct nouveau_graph base; +- struct nv10_graph_chan *chan[32]; +- spinlock_t lock; +-}; +- +-struct nv10_graph_chan { +- struct nouveau_object base; +- int chid; +- int nv10[ARRAY_SIZE(nv10_graph_ctx_regs)]; +- int nv17[ARRAY_SIZE(nv17_graph_ctx_regs)]; +- struct pipe_state pipe_state; +- u32 lma_window[4]; +-}; +- +- +-static inline struct nv10_graph_priv * +-nv10_graph_priv(struct nv10_graph_chan *chan) +-{ +- return (void *)nv_object(chan)->engine; +-} +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-#define PIPE_SAVE(priv, state, addr) \ +- do { \ +- int __i; \ +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ +- for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ +- state[__i] = nv_rd32(priv, NV10_PGRAPH_PIPE_DATA); \ +- } while (0) +- +-#define PIPE_RESTORE(priv, state, addr) \ +- do { \ +- int __i; \ +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, addr); \ +- for (__i = 0; __i < ARRAY_SIZE(state); __i++) \ +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \ +- } while (0) +- +-static struct nouveau_oclass +-nv10_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs }, /* null */ +- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs }, /* pattern */ +- { 0x004a, &nv04_graph_ofuncs }, /* gdi */ +- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ +- { 0x005f, &nv04_graph_ofuncs }, /* blit */ +- { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs }, /* ifc */ +- { 0x009f, &nv04_graph_ofuncs }, /* blit */ +- { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ +- { 0x0094, &nv04_graph_ofuncs }, /* ttri */ +- { 0x0095, &nv04_graph_ofuncs }, /* mtri */ +- { 0x0056, &nv04_graph_ofuncs }, /* celcius */ +- {}, +-}; +- +-static struct nouveau_oclass +-nv15_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs }, /* null */ +- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs }, /* pattern */ +- { 0x004a, &nv04_graph_ofuncs }, /* gdi */ +- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ +- { 0x005f, &nv04_graph_ofuncs }, /* blit */ +- { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs }, /* ifc */ +- { 0x009f, &nv04_graph_ofuncs }, /* blit */ +- { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ +- { 0x0094, &nv04_graph_ofuncs }, /* ttri */ +- { 0x0095, &nv04_graph_ofuncs }, /* mtri */ +- { 0x0096, &nv04_graph_ofuncs }, /* celcius */ +- {}, +-}; +- +-static int +-nv17_graph_mthd_lma_window(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv10_graph_chan *chan = (void *)object->parent; +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- struct pipe_state *pipe = &chan->pipe_state; +- u32 pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3]; +- u32 xfmode0, xfmode1; +- u32 data = *(u32 *)args; +- int i; +- +- chan->lma_window[(mthd - 0x1638) / 4] = data; +- +- if (mthd != 0x1644) +- return 0; +- +- nv04_graph_idle(priv); +- +- PIPE_SAVE(priv, pipe_0x0040, 0x0040); +- PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); +- +- PIPE_RESTORE(priv, chan->lma_window, 0x6790); +- +- nv04_graph_idle(priv); +- +- xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); +- xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); +- +- PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); +- PIPE_SAVE(priv, pipe_0x64c0, 0x64c0); +- PIPE_SAVE(priv, pipe_0x6ab0, 0x6ab0); +- PIPE_SAVE(priv, pipe_0x6a80, 0x6a80); +- +- nv04_graph_idle(priv); +- +- nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); +- nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); +- for (i = 0; i < 4; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); +- for (i = 0; i < 4; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); +- for (i = 0; i < 3; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); +- for (i = 0; i < 3; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); +- +- PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); +- +- nv04_graph_idle(priv); +- +- PIPE_RESTORE(priv, pipe_0x0040, 0x0040); +- +- nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); +- nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); +- +- PIPE_RESTORE(priv, pipe_0x64c0, 0x64c0); +- PIPE_RESTORE(priv, pipe_0x6ab0, 0x6ab0); +- PIPE_RESTORE(priv, pipe_0x6a80, 0x6a80); +- PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000000c0); +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); +- +- nv04_graph_idle(priv); +- +- return 0; +-} +- +-static int +-nv17_graph_mthd_lma_enable(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv10_graph_chan *chan = (void *)object->parent; +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- +- nv04_graph_idle(priv); +- +- nv_mask(priv, NV10_PGRAPH_DEBUG_4, 0x00000100, 0x00000100); +- nv_mask(priv, 0x4006b0, 0x08000000, 0x08000000); +- return 0; +-} +- +-static struct nouveau_omthds +-nv17_celcius_omthds[] = { +- { 0x1638, 0x1638, nv17_graph_mthd_lma_window }, +- { 0x163c, 0x163c, nv17_graph_mthd_lma_window }, +- { 0x1640, 0x1640, nv17_graph_mthd_lma_window }, +- { 0x1644, 0x1644, nv17_graph_mthd_lma_window }, +- { 0x1658, 0x1658, nv17_graph_mthd_lma_enable }, +- {} +-}; +- +-static struct nouveau_oclass +-nv17_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs }, /* null */ +- { 0x0039, &nv04_graph_ofuncs }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs }, /* pattern */ +- { 0x004a, &nv04_graph_ofuncs }, /* gdi */ +- { 0x0052, &nv04_graph_ofuncs }, /* swzsurf */ +- { 0x005f, &nv04_graph_ofuncs }, /* blit */ +- { 0x0062, &nv04_graph_ofuncs }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs }, /* ifc */ +- { 0x009f, &nv04_graph_ofuncs }, /* blit */ +- { 0x0093, &nv04_graph_ofuncs }, /* surf3d */ +- { 0x0094, &nv04_graph_ofuncs }, /* ttri */ +- { 0x0095, &nv04_graph_ofuncs }, /* mtri */ +- { 0x0099, &nv04_graph_ofuncs, nv17_celcius_omthds }, +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static struct nv10_graph_chan * +-nv10_graph_channel(struct nv10_graph_priv *priv) +-{ +- struct nv10_graph_chan *chan = NULL; +- if (nv_rd32(priv, 0x400144) & 0x00010000) { +- int chid = nv_rd32(priv, 0x400148) >> 24; +- if (chid < ARRAY_SIZE(priv->chan)) +- chan = priv->chan[chid]; +- } +- return chan; +-} +- +-static void +-nv10_graph_save_pipe(struct nv10_graph_chan *chan) +-{ +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- struct pipe_state *pipe = &chan->pipe_state; +- +- PIPE_SAVE(priv, pipe->pipe_0x4400, 0x4400); +- PIPE_SAVE(priv, pipe->pipe_0x0200, 0x0200); +- PIPE_SAVE(priv, pipe->pipe_0x6400, 0x6400); +- PIPE_SAVE(priv, pipe->pipe_0x6800, 0x6800); +- PIPE_SAVE(priv, pipe->pipe_0x6c00, 0x6c00); +- PIPE_SAVE(priv, pipe->pipe_0x7000, 0x7000); +- PIPE_SAVE(priv, pipe->pipe_0x7400, 0x7400); +- PIPE_SAVE(priv, pipe->pipe_0x7800, 0x7800); +- PIPE_SAVE(priv, pipe->pipe_0x0040, 0x0040); +- PIPE_SAVE(priv, pipe->pipe_0x0000, 0x0000); +-} +- +-static void +-nv10_graph_load_pipe(struct nv10_graph_chan *chan) +-{ +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- struct pipe_state *pipe = &chan->pipe_state; +- u32 xfmode0, xfmode1; +- int i; +- +- nv04_graph_idle(priv); +- /* XXX check haiku comments */ +- xfmode0 = nv_rd32(priv, NV10_PGRAPH_XFMODE0); +- xfmode1 = nv_rd32(priv, NV10_PGRAPH_XFMODE1); +- nv_wr32(priv, NV10_PGRAPH_XFMODE0, 0x10000000); +- nv_wr32(priv, NV10_PGRAPH_XFMODE1, 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); +- for (i = 0; i < 4; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); +- for (i = 0; i < 4; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); +- for (i = 0; i < 3; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x3f800000); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80); +- for (i = 0; i < 3; i++) +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000000); +- +- nv_wr32(priv, NV10_PGRAPH_PIPE_ADDRESS, 0x00000040); +- nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, 0x00000008); +- +- +- PIPE_RESTORE(priv, pipe->pipe_0x0200, 0x0200); +- nv04_graph_idle(priv); +- +- /* restore XFMODE */ +- nv_wr32(priv, NV10_PGRAPH_XFMODE0, xfmode0); +- nv_wr32(priv, NV10_PGRAPH_XFMODE1, xfmode1); +- PIPE_RESTORE(priv, pipe->pipe_0x6400, 0x6400); +- PIPE_RESTORE(priv, pipe->pipe_0x6800, 0x6800); +- PIPE_RESTORE(priv, pipe->pipe_0x6c00, 0x6c00); +- PIPE_RESTORE(priv, pipe->pipe_0x7000, 0x7000); +- PIPE_RESTORE(priv, pipe->pipe_0x7400, 0x7400); +- PIPE_RESTORE(priv, pipe->pipe_0x7800, 0x7800); +- PIPE_RESTORE(priv, pipe->pipe_0x4400, 0x4400); +- PIPE_RESTORE(priv, pipe->pipe_0x0000, 0x0000); +- PIPE_RESTORE(priv, pipe->pipe_0x0040, 0x0040); +- nv04_graph_idle(priv); +-} +- +-static void +-nv10_graph_create_pipe(struct nv10_graph_chan *chan) +-{ +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- struct pipe_state *pipe_state = &chan->pipe_state; +- u32 *pipe_state_addr; +- int i; +-#define PIPE_INIT(addr) \ +- do { \ +- pipe_state_addr = pipe_state->pipe_##addr; \ +- } while (0) +-#define PIPE_INIT_END(addr) \ +- do { \ +- u32 *__end_addr = pipe_state->pipe_##addr + \ +- ARRAY_SIZE(pipe_state->pipe_##addr); \ +- if (pipe_state_addr != __end_addr) \ +- nv_error(priv, "incomplete pipe init for 0x%x : %p/%p\n", \ +- addr, pipe_state_addr, __end_addr); \ +- } while (0) +-#define NV_WRITE_PIPE_INIT(value) *(pipe_state_addr++) = value +- +- PIPE_INIT(0x0200); +- for (i = 0; i < 48; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x0200); +- +- PIPE_INIT(0x6400); +- for (i = 0; i < 211; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- NV_WRITE_PIPE_INIT(0x40000000); +- NV_WRITE_PIPE_INIT(0x40000000); +- NV_WRITE_PIPE_INIT(0x40000000); +- NV_WRITE_PIPE_INIT(0x40000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x3f000000); +- NV_WRITE_PIPE_INIT(0x3f000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- PIPE_INIT_END(0x6400); +- +- PIPE_INIT(0x6800); +- for (i = 0; i < 162; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x3f800000); +- for (i = 0; i < 25; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x6800); +- +- PIPE_INIT(0x6c00); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0xbf800000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x6c00); +- +- PIPE_INIT(0x7000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x00000000); +- NV_WRITE_PIPE_INIT(0x7149f2ca); +- for (i = 0; i < 35; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x7000); +- +- PIPE_INIT(0x7400); +- for (i = 0; i < 48; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x7400); +- +- PIPE_INIT(0x7800); +- for (i = 0; i < 48; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x7800); +- +- PIPE_INIT(0x4400); +- for (i = 0; i < 32; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x4400); +- +- PIPE_INIT(0x0000); +- for (i = 0; i < 16; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x0000); +- +- PIPE_INIT(0x0040); +- for (i = 0; i < 4; i++) +- NV_WRITE_PIPE_INIT(0x00000000); +- PIPE_INIT_END(0x0040); +- +-#undef PIPE_INIT +-#undef PIPE_INIT_END +-#undef NV_WRITE_PIPE_INIT +-} +- +-static int +-nv10_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) +-{ +- int i; +- for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) { +- if (nv10_graph_ctx_regs[i] == reg) +- return i; +- } +- nv_error(priv, "unknow offset nv10_ctx_regs %d\n", reg); +- return -1; +-} +- +-static int +-nv17_graph_ctx_regs_find_offset(struct nv10_graph_priv *priv, int reg) +-{ +- int i; +- for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) { +- if (nv17_graph_ctx_regs[i] == reg) +- return i; +- } +- nv_error(priv, "unknow offset nv17_ctx_regs %d\n", reg); +- return -1; +-} +- +-static void +-nv10_graph_load_dma_vtxbuf(struct nv10_graph_chan *chan, int chid, u32 inst) +-{ +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- u32 st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4]; +- u32 ctx_user, ctx_switch[5]; +- int i, subchan = -1; +- +- /* NV10TCL_DMA_VTXBUF (method 0x18c) modifies hidden state +- * that cannot be restored via MMIO. Do it through the FIFO +- * instead. +- */ +- +- /* Look for a celsius object */ +- for (i = 0; i < 8; i++) { +- int class = nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; +- +- if (class == 0x56 || class == 0x96 || class == 0x99) { +- subchan = i; +- break; +- } +- } +- +- if (subchan < 0 || !inst) +- return; +- +- /* Save the current ctx object */ +- ctx_user = nv_rd32(priv, NV10_PGRAPH_CTX_USER); +- for (i = 0; i < 5; i++) +- ctx_switch[i] = nv_rd32(priv, NV10_PGRAPH_CTX_SWITCH(i)); +- +- /* Save the FIFO state */ +- st2 = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2); +- st2_dl = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DL); +- st2_dh = nv_rd32(priv, NV10_PGRAPH_FFINTFC_ST2_DH); +- fifo_ptr = nv_rd32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR); +- +- for (i = 0; i < ARRAY_SIZE(fifo); i++) +- fifo[i] = nv_rd32(priv, 0x4007a0 + 4 * i); +- +- /* Switch to the celsius subchannel */ +- for (i = 0; i < 5; i++) +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), +- nv_rd32(priv, NV10_PGRAPH_CTX_CACHE(subchan, i))); +- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xe000, subchan << 13); +- +- /* Inject NV10TCL_DMA_VTXBUF */ +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, 0); +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, +- 0x2c000000 | chid << 20 | subchan << 16 | 0x18c); +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, inst); +- nv_mask(priv, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000); +- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); +- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); +- +- /* Restore the FIFO state */ +- for (i = 0; i < ARRAY_SIZE(fifo); i++) +- nv_wr32(priv, 0x4007a0 + 4 * i, fifo[i]); +- +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_FIFO_PTR, fifo_ptr); +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, st2); +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DL, st2_dl); +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2_DH, st2_dh); +- +- /* Restore the current ctx object */ +- for (i = 0; i < 5; i++) +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(i), ctx_switch[i]); +- nv_wr32(priv, NV10_PGRAPH_CTX_USER, ctx_user); +-} +- +-static int +-nv10_graph_load_context(struct nv10_graph_chan *chan, int chid) +-{ +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- u32 inst; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) +- nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]); +- +- if (nv_device(priv)->card_type >= NV_11 && +- nv_device(priv)->chipset >= 0x17) { +- for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) +- nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]); +- } +- +- nv10_graph_load_pipe(chan); +- +- inst = nv_rd32(priv, NV10_PGRAPH_GLOBALSTATE1) & 0xffff; +- nv10_graph_load_dma_vtxbuf(chan, chid, inst); +- +- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); +- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, chid << 24); +- nv_mask(priv, NV10_PGRAPH_FFINTFC_ST2, 0x30000000, 0x00000000); +- return 0; +-} +- +-static int +-nv10_graph_unload_context(struct nv10_graph_chan *chan) +-{ +- struct nv10_graph_priv *priv = nv10_graph_priv(chan); +- int i; +- +- for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++) +- chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]); +- +- if (nv_device(priv)->card_type >= NV_11 && +- nv_device(priv)->chipset >= 0x17) { +- for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++) +- chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]); +- } +- +- nv10_graph_save_pipe(chan); +- +- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000000); +- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); +- return 0; +-} +- +-static void +-nv10_graph_context_switch(struct nv10_graph_priv *priv) +-{ +- struct nv10_graph_chan *prev = NULL; +- struct nv10_graph_chan *next = NULL; +- unsigned long flags; +- int chid; +- +- spin_lock_irqsave(&priv->lock, flags); +- nv04_graph_idle(priv); +- +- /* If previous context is valid, we need to save it */ +- prev = nv10_graph_channel(priv); +- if (prev) +- nv10_graph_unload_context(prev); +- +- /* load context for next channel */ +- chid = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f; +- next = priv->chan[chid]; +- if (next) +- nv10_graph_load_context(next, chid); +- +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-#define NV_WRITE_CTX(reg, val) do { \ +- int offset = nv10_graph_ctx_regs_find_offset(priv, reg); \ +- if (offset > 0) \ +- chan->nv10[offset] = val; \ +- } while (0) +- +-#define NV17_WRITE_CTX(reg, val) do { \ +- int offset = nv17_graph_ctx_regs_find_offset(priv, reg); \ +- if (offset > 0) \ +- chan->nv17[offset] = val; \ +- } while (0) +- +-static int +-nv10_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fifo_chan *fifo = (void *)parent; +- struct nv10_graph_priv *priv = (void *)engine; +- struct nv10_graph_chan *chan; +- unsigned long flags; +- int ret; +- +- ret = nouveau_object_create(parent, engine, oclass, 0, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- spin_lock_irqsave(&priv->lock, flags); +- if (priv->chan[fifo->chid]) { +- *pobject = nv_object(priv->chan[fifo->chid]); +- atomic_inc(&(*pobject)->refcount); +- spin_unlock_irqrestore(&priv->lock, flags); +- nouveau_object_destroy(&chan->base); +- return 1; +- } +- +- NV_WRITE_CTX(0x00400e88, 0x08000000); +- NV_WRITE_CTX(0x00400e9c, 0x4b7fffff); +- NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff); +- NV_WRITE_CTX(0x00400e10, 0x00001000); +- NV_WRITE_CTX(0x00400e14, 0x00001000); +- NV_WRITE_CTX(0x00400e30, 0x00080008); +- NV_WRITE_CTX(0x00400e34, 0x00080008); +- if (nv_device(priv)->card_type >= NV_11 && +- nv_device(priv)->chipset >= 0x17) { +- /* is it really needed ??? */ +- NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4, +- nv_rd32(priv, NV10_PGRAPH_DEBUG_4)); +- NV17_WRITE_CTX(0x004006b0, nv_rd32(priv, 0x004006b0)); +- NV17_WRITE_CTX(0x00400eac, 0x0fff0000); +- NV17_WRITE_CTX(0x00400eb0, 0x0fff0000); +- NV17_WRITE_CTX(0x00400ec0, 0x00000080); +- NV17_WRITE_CTX(0x00400ed0, 0x00000080); +- } +- NV_WRITE_CTX(NV10_PGRAPH_CTX_USER, chan->chid << 24); +- +- nv10_graph_create_pipe(chan); +- +- priv->chan[fifo->chid] = chan; +- chan->chid = fifo->chid; +- spin_unlock_irqrestore(&priv->lock, flags); +- return 0; +-} +- +-static void +-nv10_graph_context_dtor(struct nouveau_object *object) +-{ +- struct nv10_graph_priv *priv = (void *)object->engine; +- struct nv10_graph_chan *chan = (void *)object; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->lock, flags); +- priv->chan[chan->chid] = NULL; +- spin_unlock_irqrestore(&priv->lock, flags); +- +- nouveau_object_destroy(&chan->base); +-} +- +-static int +-nv10_graph_context_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv10_graph_priv *priv = (void *)object->engine; +- struct nv10_graph_chan *chan = (void *)object; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->lock, flags); +- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000000); +- if (nv10_graph_channel(priv) == chan) +- nv10_graph_unload_context(chan); +- nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001); +- spin_unlock_irqrestore(&priv->lock, flags); +- +- return nouveau_object_fini(&chan->base, suspend); +-} +- +-static struct nouveau_oclass +-nv10_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x10), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv10_graph_context_ctor, +- .dtor = nv10_graph_context_dtor, +- .init = nouveau_object_init, +- .fini = nv10_graph_context_fini, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static void +-nv10_graph_tile_prog(struct nouveau_engine *engine, int i) +-{ +- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; +- struct nouveau_fifo *pfifo = nouveau_fifo(engine); +- struct nv10_graph_priv *priv = (void *)engine; +- unsigned long flags; +- +- pfifo->pause(pfifo, &flags); +- nv04_graph_idle(priv); +- +- nv_wr32(priv, NV10_PGRAPH_TLIMIT(i), tile->limit); +- nv_wr32(priv, NV10_PGRAPH_TSIZE(i), tile->pitch); +- nv_wr32(priv, NV10_PGRAPH_TILE(i), tile->addr); +- +- pfifo->start(pfifo, &flags); +-} +- +-const struct nouveau_bitfield nv10_graph_intr_name[] = { +- { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" }, +- { NV_PGRAPH_INTR_ERROR, "ERROR" }, +- {} +-}; +- +-const struct nouveau_bitfield nv10_graph_nstatus[] = { +- { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" }, +- { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" }, +- { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" }, +- { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" }, +- {} +-}; +- +-static void +-nv10_graph_intr(struct nouveau_subdev *subdev) +-{ +- struct nv10_graph_priv *priv = (void *)subdev; +- struct nv10_graph_chan *chan = NULL; +- struct nouveau_namedb *namedb = NULL; +- struct nouveau_handle *handle = NULL; +- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); +- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); +- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); +- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); +- u32 chid = (addr & 0x01f00000) >> 20; +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00001ffc); +- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); +- u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; +- u32 show = stat; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->lock, flags); +- chan = priv->chan[chid]; +- if (chan) +- namedb = (void *)nv_pclass(nv_object(chan), NV_NAMEDB_CLASS); +- spin_unlock_irqrestore(&priv->lock, flags); +- +- if (stat & NV_PGRAPH_INTR_ERROR) { +- if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) { +- handle = nouveau_namedb_get_class(namedb, class); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~NV_PGRAPH_INTR_ERROR; +- } +- } +- +- if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) { +- nv_wr32(priv, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH); +- stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; +- show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH; +- nv10_graph_context_switch(priv); +- } +- +- nv_wr32(priv, NV03_PGRAPH_INTR, stat); +- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); +- +- if (show) { +- nv_error(priv, "%s", ""); +- nouveau_bitfield_print(nv10_graph_intr_name, show); +- pr_cont(" nsource:"); +- nouveau_bitfield_print(nv04_graph_nsource, nsource); +- pr_cont(" nstatus:"); +- nouveau_bitfield_print(nv10_graph_nstatus, nstatus); +- pr_cont("\n"); +- nv_error(priv, +- "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, nouveau_client_name(chan), subc, class, mthd, +- data); +- } +- +- nouveau_namedb_put(handle); +-} +- +-static int +-nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv10_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv10_graph_intr; +- nv_engine(priv)->cclass = &nv10_graph_cclass; +- +- if (nv_device(priv)->chipset <= 0x10) +- nv_engine(priv)->sclass = nv10_graph_sclass; +- else +- if (nv_device(priv)->chipset < 0x17 || +- nv_device(priv)->card_type < NV_11) +- nv_engine(priv)->sclass = nv15_graph_sclass; +- else +- nv_engine(priv)->sclass = nv17_graph_sclass; +- +- nv_engine(priv)->tile_prog = nv10_graph_tile_prog; +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-static void +-nv10_graph_dtor(struct nouveau_object *object) +-{ +- struct nv10_graph_priv *priv = (void *)object; +- nouveau_graph_destroy(&priv->base); +-} +- +-static int +-nv10_graph_init(struct nouveau_object *object) +-{ +- struct nouveau_engine *engine = nv_engine(object); +- struct nouveau_fb *pfb = nouveau_fb(object); +- struct nv10_graph_priv *priv = (void *)engine; +- int ret, i; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); +- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); +- +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); +- /* nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x24E00810); */ /* 0x25f92ad9 */ +- nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31)); +- +- if (nv_device(priv)->card_type >= NV_11 && +- nv_device(priv)->chipset >= 0x17) { +- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000); +- nv_wr32(priv, 0x400a10, 0x03ff3fb6); +- nv_wr32(priv, 0x400838, 0x002f8684); +- nv_wr32(priv, 0x40083c, 0x00115f3f); +- nv_wr32(priv, 0x4006b0, 0x40000020); +- } else { +- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); +- } +- +- /* Turn all the tiling regions off. */ +- for (i = 0; i < pfb->tile.regions; i++) +- engine->tile_prog(engine, i); +- +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(0), 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(1), 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(2), 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(3), 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_CTX_SWITCH(4), 0x00000000); +- nv_wr32(priv, NV10_PGRAPH_STATE, 0xFFFFFFFF); +- +- nv_mask(priv, NV10_PGRAPH_CTX_USER, 0xff000000, 0x1f000000); +- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); +- nv_wr32(priv, NV10_PGRAPH_FFINTFC_ST2, 0x08000000); +- return 0; +-} +- +-static int +-nv10_graph_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv10_graph_priv *priv = (void *)object; +- return nouveau_graph_fini(&priv->base, suspend); +-} +- +-struct nouveau_oclass +-nv10_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x10), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv10_graph_ctor, +- .dtor = nv10_graph_dtor, +- .init = nv10_graph_init, +- .fini = nv10_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c +deleted file mode 100644 +index 2b0e8f48..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv108.c ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv108_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0xa140, &nouveau_object_ofuncs }, +- { KEPLER_B, &nvc0_fermi_ofuncs }, +- { 0xa1c0, &nouveau_object_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nv108_graph_init_main_0[] = { +- { 0x400080, 1, 0x04, 0x003083c2 }, +- { 0x400088, 1, 0x04, 0x0001bfe7 }, +- { 0x40008c, 1, 0x04, 0x00000000 }, +- { 0x400090, 1, 0x04, 0x00000030 }, +- { 0x40013c, 1, 0x04, 0x003901f7 }, +- { 0x400140, 1, 0x04, 0x00000100 }, +- { 0x400144, 1, 0x04, 0x00000000 }, +- { 0x400148, 1, 0x04, 0x00000110 }, +- { 0x400138, 1, 0x04, 0x00000000 }, +- { 0x400130, 2, 0x04, 0x00000000 }, +- { 0x400124, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405900, 1, 0x04, 0x00000000 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- { 0x405928, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nv108_graph_init_gpc_unk_0[] = { +- { 0x418604, 1, 0x04, 0x00000000 }, +- { 0x418680, 1, 0x04, 0x00000000 }, +- { 0x418714, 1, 0x04, 0x00000000 }, +- { 0x418384, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_graph_init_setup_1[] = { +- { 0x4188c8, 2, 0x04, 0x00000000 }, +- { 0x4188d0, 1, 0x04, 0x00010000 }, +- { 0x4188d4, 1, 0x04, 0x00000201 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_graph_init_tex_0[] = { +- { 0x419ab0, 1, 0x04, 0x00000000 }, +- { 0x419ac8, 1, 0x04, 0x00000000 }, +- { 0x419ab8, 1, 0x04, 0x000000e7 }, +- { 0x419abc, 2, 0x04, 0x00000000 }, +- { 0x419ab4, 1, 0x04, 0x00000000 }, +- { 0x419aa8, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nv108_graph_init_l1c_0[] = { +- { 0x419c98, 1, 0x04, 0x00000000 }, +- { 0x419ca8, 1, 0x04, 0x00000000 }, +- { 0x419cb0, 1, 0x04, 0x01000000 }, +- { 0x419cb4, 1, 0x04, 0x00000000 }, +- { 0x419cb8, 1, 0x04, 0x00b08bea }, +- { 0x419c84, 1, 0x04, 0x00010384 }, +- { 0x419cbc, 1, 0x04, 0x281b3646 }, +- { 0x419cc0, 2, 0x04, 0x00000000 }, +- { 0x419c80, 1, 0x04, 0x00000230 }, +- { 0x419ccc, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nv108_graph_pack_mmio[] = { +- { nv108_graph_init_main_0 }, +- { nvf0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvd9_graph_init_pd_0 }, +- { nv108_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvf0_graph_init_sked_0 }, +- { nvf0_graph_init_cwd_0 }, +- { nvd9_graph_init_prop_0 }, +- { nv108_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nv108_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvd9_graph_init_gpm_0 }, +- { nvf0_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nve4_graph_init_tpccs_0 }, +- { nv108_graph_init_tex_0 }, +- { nve4_graph_init_pe_0 }, +- { nv108_graph_init_l1c_0 }, +- { nvc0_graph_init_mpc_0 }, +- { nvf0_graph_init_sm_0 }, +- { nvd7_graph_init_pes_0 }, +- { nvd7_graph_init_wwdx_0 }, +- { nvd7_graph_init_cbm_0 }, +- { nve4_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv108_graph_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvc0_graph_priv *priv = (void *)object; +- static const struct { +- u32 addr; +- u32 data; +- } magic[] = { +- { 0x020520, 0xfffffffc }, +- { 0x020524, 0xfffffffe }, +- { 0x020524, 0xfffffffc }, +- { 0x020524, 0xfffffff8 }, +- { 0x020524, 0xffffffe0 }, +- { 0x020530, 0xfffffffe }, +- { 0x02052c, 0xfffffffa }, +- { 0x02052c, 0xfffffff0 }, +- { 0x02052c, 0xffffffc0 }, +- { 0x02052c, 0xffffff00 }, +- { 0x02052c, 0xfffffc00 }, +- { 0x02052c, 0xfffcfc00 }, +- { 0x02052c, 0xfff0fc00 }, +- { 0x02052c, 0xff80fc00 }, +- { 0x020528, 0xfffffffe }, +- { 0x020528, 0xfffffffc }, +- }; +- int i; +- +- nv_mask(priv, 0x000200, 0x08001000, 0x00000000); +- nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); +- for (i = 0; i < ARRAY_SIZE(magic); i++) { +- nv_wr32(priv, magic[i].addr, magic[i].data); +- nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); +- } +- +- return nouveau_graph_fini(&priv->base, suspend); +-} +- +-#include "fuc/hubnv108.fuc5.h" +- +-static struct nvc0_graph_ucode +-nv108_graph_fecs_ucode = { +- .code.data = nv108_grhub_code, +- .code.size = sizeof(nv108_grhub_code), +- .data.data = nv108_grhub_data, +- .data.size = sizeof(nv108_grhub_data), +-}; +- +-#include "fuc/gpcnv108.fuc5.h" +- +-static struct nvc0_graph_ucode +-nv108_graph_gpccs_ucode = { +- .code.data = nv108_grgpc_code, +- .code.size = sizeof(nv108_grgpc_code), +- .data.data = nv108_grgpc_data, +- .data.size = sizeof(nv108_grgpc_data), +-}; +- +-struct nouveau_oclass * +-nv108_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0x08), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nve4_graph_init, +- .fini = nv108_graph_fini, +- }, +- .cclass = &nv108_grctx_oclass, +- .sclass = nv108_graph_sclass, +- .mmio = nv108_graph_pack_mmio, +- .fecs.ucode = &nv108_graph_fecs_ucode, +- .gpccs.ucode = &nv108_graph_gpccs_ucode, +- .ppc_nr = 1, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c +deleted file mode 100644 +index ceb9c746..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.c ++++ /dev/null +@@ -1,383 +0,0 @@ +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +- +-#include "nv20.h" +-#include "regs.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv20_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ +- { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */ +- { 0x0097, &nv04_graph_ofuncs, NULL }, /* kelvin */ +- { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */ +- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv20_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_chan *chan; +- int ret, i; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, +- 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC, +- &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- chan->chid = nouveau_fifo_chan(parent)->chid; +- +- nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); +- nv_wo32(chan, 0x033c, 0xffff0000); +- nv_wo32(chan, 0x03a0, 0x0fff0000); +- nv_wo32(chan, 0x03a4, 0x0fff0000); +- nv_wo32(chan, 0x047c, 0x00000101); +- nv_wo32(chan, 0x0490, 0x00000111); +- nv_wo32(chan, 0x04a8, 0x44400000); +- for (i = 0x04d4; i <= 0x04e0; i += 4) +- nv_wo32(chan, i, 0x00030303); +- for (i = 0x04f4; i <= 0x0500; i += 4) +- nv_wo32(chan, i, 0x00080000); +- for (i = 0x050c; i <= 0x0518; i += 4) +- nv_wo32(chan, i, 0x01012000); +- for (i = 0x051c; i <= 0x0528; i += 4) +- nv_wo32(chan, i, 0x000105b8); +- for (i = 0x052c; i <= 0x0538; i += 4) +- nv_wo32(chan, i, 0x00080008); +- for (i = 0x055c; i <= 0x0598; i += 4) +- nv_wo32(chan, i, 0x07ff0000); +- nv_wo32(chan, 0x05a4, 0x4b7fffff); +- nv_wo32(chan, 0x05fc, 0x00000001); +- nv_wo32(chan, 0x0604, 0x00004000); +- nv_wo32(chan, 0x0610, 0x00000001); +- nv_wo32(chan, 0x0618, 0x00040000); +- nv_wo32(chan, 0x061c, 0x00010000); +- for (i = 0x1c1c; i <= 0x248c; i += 16) { +- nv_wo32(chan, (i + 0), 0x10700ff9); +- nv_wo32(chan, (i + 4), 0x0436086c); +- nv_wo32(chan, (i + 8), 0x000c001b); +- } +- nv_wo32(chan, 0x281c, 0x3f800000); +- nv_wo32(chan, 0x2830, 0x3f800000); +- nv_wo32(chan, 0x285c, 0x40000000); +- nv_wo32(chan, 0x2860, 0x3f800000); +- nv_wo32(chan, 0x2864, 0x3f000000); +- nv_wo32(chan, 0x286c, 0x40000000); +- nv_wo32(chan, 0x2870, 0x3f800000); +- nv_wo32(chan, 0x2878, 0xbf800000); +- nv_wo32(chan, 0x2880, 0xbf800000); +- nv_wo32(chan, 0x34a4, 0x000fe000); +- nv_wo32(chan, 0x3530, 0x000003f8); +- nv_wo32(chan, 0x3540, 0x002fe000); +- for (i = 0x355c; i <= 0x3578; i += 4) +- nv_wo32(chan, i, 0x001c527c); +- return 0; +-} +- +-int +-nv20_graph_context_init(struct nouveau_object *object) +-{ +- struct nv20_graph_priv *priv = (void *)object->engine; +- struct nv20_graph_chan *chan = (void *)object; +- int ret; +- +- ret = nouveau_graph_context_init(&chan->base); +- if (ret) +- return ret; +- +- nv_wo32(priv->ctxtab, chan->chid * 4, nv_gpuobj(chan)->addr >> 4); +- return 0; +-} +- +-int +-nv20_graph_context_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv20_graph_priv *priv = (void *)object->engine; +- struct nv20_graph_chan *chan = (void *)object; +- int chid = -1; +- +- nv_mask(priv, 0x400720, 0x00000001, 0x00000000); +- if (nv_rd32(priv, 0x400144) & 0x00010000) +- chid = (nv_rd32(priv, 0x400148) & 0x1f000000) >> 24; +- if (chan->chid == chid) { +- nv_wr32(priv, 0x400784, nv_gpuobj(chan)->addr >> 4); +- nv_wr32(priv, 0x400788, 0x00000002); +- nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); +- nv_wr32(priv, 0x400144, 0x10000000); +- nv_mask(priv, 0x400148, 0xff000000, 0x1f000000); +- } +- nv_mask(priv, 0x400720, 0x00000001, 0x00000001); +- +- nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000); +- return nouveau_graph_context_fini(&chan->base, suspend); +-} +- +-static struct nouveau_oclass +-nv20_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x20), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv20_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = nv20_graph_context_init, +- .fini = nv20_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-void +-nv20_graph_tile_prog(struct nouveau_engine *engine, int i) +-{ +- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; +- struct nouveau_fifo *pfifo = nouveau_fifo(engine); +- struct nv20_graph_priv *priv = (void *)engine; +- unsigned long flags; +- +- pfifo->pause(pfifo, &flags); +- nv04_graph_idle(priv); +- +- nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); +- nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); +- nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); +- +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->limit); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->pitch); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0010 + 4 * i); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->addr); +- +- if (nv_device(engine)->chipset != 0x34) { +- nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00ea0090 + 4 * i); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, tile->zcomp); +- } +- +- pfifo->start(pfifo, &flags); +-} +- +-void +-nv20_graph_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nouveau_handle *handle; +- struct nv20_graph_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); +- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); +- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); +- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); +- u32 chid = (addr & 0x01f00000) >> 20; +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00001ffc); +- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); +- u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff; +- u32 show = stat; +- +- engctx = nouveau_engctx_get(engine, chid); +- if (stat & NV_PGRAPH_INTR_ERROR) { +- if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { +- handle = nouveau_handle_get_class(engctx, class); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~NV_PGRAPH_INTR_ERROR; +- nouveau_handle_put(handle); +- } +- } +- +- nv_wr32(priv, NV03_PGRAPH_INTR, stat); +- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); +- +- if (show) { +- nv_error(priv, "%s", ""); +- nouveau_bitfield_print(nv10_graph_intr_name, show); +- pr_cont(" nsource:"); +- nouveau_bitfield_print(nv04_graph_nsource, nsource); +- pr_cont(" nstatus:"); +- nouveau_bitfield_print(nv10_graph_nstatus, nstatus); +- pr_cont("\n"); +- nv_error(priv, +- "ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, nouveau_client_name(engctx), subc, class, mthd, +- data); +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static int +-nv20_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv20_graph_intr; +- nv_engine(priv)->cclass = &nv20_graph_cclass; +- nv_engine(priv)->sclass = nv20_graph_sclass; +- nv_engine(priv)->tile_prog = nv20_graph_tile_prog; +- return 0; +-} +- +-void +-nv20_graph_dtor(struct nouveau_object *object) +-{ +- struct nv20_graph_priv *priv = (void *)object; +- nouveau_gpuobj_ref(NULL, &priv->ctxtab); +- nouveau_graph_destroy(&priv->base); +-} +- +-int +-nv20_graph_init(struct nouveau_object *object) +-{ +- struct nouveau_engine *engine = nv_engine(object); +- struct nv20_graph_priv *priv = (void *)engine; +- struct nouveau_fb *pfb = nouveau_fb(object); +- u32 tmp, vramsz; +- int ret, i; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); +- +- if (nv_device(priv)->chipset == 0x20) { +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x003d0000); +- for (i = 0; i < 15; i++) +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); +- nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); +- } else { +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x02c80000); +- for (i = 0; i < 32; i++) +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, 0x00000000); +- nv_wait(priv, 0x400700, 0xffffffff, 0x00000000); +- } +- +- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); +- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); +- +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x00118700); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xF3CE0475); /* 0x4 = auto ctx switch */ +- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00000000); +- nv_wr32(priv, 0x40009C , 0x00000040); +- +- if (nv_device(priv)->chipset >= 0x25) { +- nv_wr32(priv, 0x400890, 0x00a8cfff); +- nv_wr32(priv, 0x400610, 0x304B1FB6); +- nv_wr32(priv, 0x400B80, 0x1cbd3883); +- nv_wr32(priv, 0x400B84, 0x44000000); +- nv_wr32(priv, 0x400098, 0x40000080); +- nv_wr32(priv, 0x400B88, 0x000000ff); +- +- } else { +- nv_wr32(priv, 0x400880, 0x0008c7df); +- nv_wr32(priv, 0x400094, 0x00000005); +- nv_wr32(priv, 0x400B80, 0x45eae20e); +- nv_wr32(priv, 0x400B84, 0x24000000); +- nv_wr32(priv, 0x400098, 0x00000040); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00038); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E10038); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000030); +- } +- +- /* Turn all the tiling regions off. */ +- for (i = 0; i < pfb->tile.regions; i++) +- engine->tile_prog(engine, i); +- +- nv_wr32(priv, 0x4009a0, nv_rd32(priv, 0x100324)); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA000C); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA, nv_rd32(priv, 0x100324)); +- +- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); +- nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); +- +- tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) & 0x0007ff00; +- nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); +- tmp = nv_rd32(priv, NV10_PGRAPH_SURFACE) | 0x00020100; +- nv_wr32(priv, NV10_PGRAPH_SURFACE, tmp); +- +- /* begin RAM config */ +- vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; +- nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100200)); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , nv_rd32(priv, 0x100204)); +- nv_wr32(priv, 0x400820, 0); +- nv_wr32(priv, 0x400824, 0); +- nv_wr32(priv, 0x400864, vramsz - 1); +- nv_wr32(priv, 0x400868, vramsz - 1); +- +- /* interesting.. the below overwrites some of the tile setup above.. */ +- nv_wr32(priv, 0x400B20, 0x00000000); +- nv_wr32(priv, 0x400B04, 0xFFFFFFFF); +- +- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMIN, 0); +- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMIN, 0); +- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff); +- nv_wr32(priv, NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff); +- return 0; +-} +- +-struct nouveau_oclass +-nv20_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x20), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv20_graph_ctor, +- .dtor = nv20_graph_dtor, +- .init = nv20_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h +deleted file mode 100644 +index 2bea7313..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv20.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-#ifndef __NV20_GRAPH_H__ +-#define __NV20_GRAPH_H__ +- +-#include +- +-#include +-#include +- +-struct nv20_graph_priv { +- struct nouveau_graph base; +- struct nouveau_gpuobj *ctxtab; +-}; +- +-struct nv20_graph_chan { +- struct nouveau_graph_chan base; +- int chid; +-}; +- +-extern struct nouveau_oclass nv25_graph_sclass[]; +-int nv20_graph_context_init(struct nouveau_object *); +-int nv20_graph_context_fini(struct nouveau_object *, bool); +- +-void nv20_graph_tile_prog(struct nouveau_engine *, int); +-void nv20_graph_intr(struct nouveau_subdev *); +- +-void nv20_graph_dtor(struct nouveau_object *); +-int nv20_graph_init(struct nouveau_object *); +- +-int nv30_graph_init(struct nouveau_object *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c +deleted file mode 100644 +index f8a6fdd7..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv25.c ++++ /dev/null +@@ -1,166 +0,0 @@ +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include "nv20.h" +-#include "regs.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-struct nouveau_oclass +-nv25_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ +- { 0x0096, &nv04_graph_ofuncs, NULL }, /* celcius */ +- { 0x009e, &nv04_graph_ofuncs, NULL }, /* swzsurf */ +- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ +- { 0x0597, &nv04_graph_ofuncs, NULL }, /* kelvin */ +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv25_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_chan *chan; +- int ret, i; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x3724, +- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- chan->chid = nouveau_fifo_chan(parent)->chid; +- +- nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); +- nv_wo32(chan, 0x035c, 0xffff0000); +- nv_wo32(chan, 0x03c0, 0x0fff0000); +- nv_wo32(chan, 0x03c4, 0x0fff0000); +- nv_wo32(chan, 0x049c, 0x00000101); +- nv_wo32(chan, 0x04b0, 0x00000111); +- nv_wo32(chan, 0x04c8, 0x00000080); +- nv_wo32(chan, 0x04cc, 0xffff0000); +- nv_wo32(chan, 0x04d0, 0x00000001); +- nv_wo32(chan, 0x04e4, 0x44400000); +- nv_wo32(chan, 0x04fc, 0x4b800000); +- for (i = 0x0510; i <= 0x051c; i += 4) +- nv_wo32(chan, i, 0x00030303); +- for (i = 0x0530; i <= 0x053c; i += 4) +- nv_wo32(chan, i, 0x00080000); +- for (i = 0x0548; i <= 0x0554; i += 4) +- nv_wo32(chan, i, 0x01012000); +- for (i = 0x0558; i <= 0x0564; i += 4) +- nv_wo32(chan, i, 0x000105b8); +- for (i = 0x0568; i <= 0x0574; i += 4) +- nv_wo32(chan, i, 0x00080008); +- for (i = 0x0598; i <= 0x05d4; i += 4) +- nv_wo32(chan, i, 0x07ff0000); +- nv_wo32(chan, 0x05e0, 0x4b7fffff); +- nv_wo32(chan, 0x0620, 0x00000080); +- nv_wo32(chan, 0x0624, 0x30201000); +- nv_wo32(chan, 0x0628, 0x70605040); +- nv_wo32(chan, 0x062c, 0xb0a09080); +- nv_wo32(chan, 0x0630, 0xf0e0d0c0); +- nv_wo32(chan, 0x0664, 0x00000001); +- nv_wo32(chan, 0x066c, 0x00004000); +- nv_wo32(chan, 0x0678, 0x00000001); +- nv_wo32(chan, 0x0680, 0x00040000); +- nv_wo32(chan, 0x0684, 0x00010000); +- for (i = 0x1b04; i <= 0x2374; i += 16) { +- nv_wo32(chan, (i + 0), 0x10700ff9); +- nv_wo32(chan, (i + 4), 0x0436086c); +- nv_wo32(chan, (i + 8), 0x000c001b); +- } +- nv_wo32(chan, 0x2704, 0x3f800000); +- nv_wo32(chan, 0x2718, 0x3f800000); +- nv_wo32(chan, 0x2744, 0x40000000); +- nv_wo32(chan, 0x2748, 0x3f800000); +- nv_wo32(chan, 0x274c, 0x3f000000); +- nv_wo32(chan, 0x2754, 0x40000000); +- nv_wo32(chan, 0x2758, 0x3f800000); +- nv_wo32(chan, 0x2760, 0xbf800000); +- nv_wo32(chan, 0x2768, 0xbf800000); +- nv_wo32(chan, 0x308c, 0x000fe000); +- nv_wo32(chan, 0x3108, 0x000003f8); +- nv_wo32(chan, 0x3468, 0x002fe000); +- for (i = 0x3484; i <= 0x34a0; i += 4) +- nv_wo32(chan, i, 0x001c527c); +- return 0; +-} +- +-static struct nouveau_oclass +-nv25_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x25), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv25_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = nv20_graph_context_init, +- .fini = nv20_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv25_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv20_graph_intr; +- nv_engine(priv)->cclass = &nv25_graph_cclass; +- nv_engine(priv)->sclass = nv25_graph_sclass; +- nv_engine(priv)->tile_prog = nv20_graph_tile_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv25_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x25), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv25_graph_ctor, +- .dtor = nv20_graph_dtor, +- .init = nv20_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c +deleted file mode 100644 +index 5de9caa2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv2a.c ++++ /dev/null +@@ -1,133 +0,0 @@ +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include "nv20.h" +-#include "regs.h" +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv2a_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_chan *chan; +- int ret, i; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x36b0, +- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- chan->chid = nouveau_fifo_chan(parent)->chid; +- +- nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24)); +- nv_wo32(chan, 0x033c, 0xffff0000); +- nv_wo32(chan, 0x03a0, 0x0fff0000); +- nv_wo32(chan, 0x03a4, 0x0fff0000); +- nv_wo32(chan, 0x047c, 0x00000101); +- nv_wo32(chan, 0x0490, 0x00000111); +- nv_wo32(chan, 0x04a8, 0x44400000); +- for (i = 0x04d4; i <= 0x04e0; i += 4) +- nv_wo32(chan, i, 0x00030303); +- for (i = 0x04f4; i <= 0x0500; i += 4) +- nv_wo32(chan, i, 0x00080000); +- for (i = 0x050c; i <= 0x0518; i += 4) +- nv_wo32(chan, i, 0x01012000); +- for (i = 0x051c; i <= 0x0528; i += 4) +- nv_wo32(chan, i, 0x000105b8); +- for (i = 0x052c; i <= 0x0538; i += 4) +- nv_wo32(chan, i, 0x00080008); +- for (i = 0x055c; i <= 0x0598; i += 4) +- nv_wo32(chan, i, 0x07ff0000); +- nv_wo32(chan, 0x05a4, 0x4b7fffff); +- nv_wo32(chan, 0x05fc, 0x00000001); +- nv_wo32(chan, 0x0604, 0x00004000); +- nv_wo32(chan, 0x0610, 0x00000001); +- nv_wo32(chan, 0x0618, 0x00040000); +- nv_wo32(chan, 0x061c, 0x00010000); +- for (i = 0x1a9c; i <= 0x22fc; i += 16) { /*XXX: check!! */ +- nv_wo32(chan, (i + 0), 0x10700ff9); +- nv_wo32(chan, (i + 4), 0x0436086c); +- nv_wo32(chan, (i + 8), 0x000c001b); +- } +- nv_wo32(chan, 0x269c, 0x3f800000); +- nv_wo32(chan, 0x26b0, 0x3f800000); +- nv_wo32(chan, 0x26dc, 0x40000000); +- nv_wo32(chan, 0x26e0, 0x3f800000); +- nv_wo32(chan, 0x26e4, 0x3f000000); +- nv_wo32(chan, 0x26ec, 0x40000000); +- nv_wo32(chan, 0x26f0, 0x3f800000); +- nv_wo32(chan, 0x26f8, 0xbf800000); +- nv_wo32(chan, 0x2700, 0xbf800000); +- nv_wo32(chan, 0x3024, 0x000fe000); +- nv_wo32(chan, 0x30a0, 0x000003f8); +- nv_wo32(chan, 0x33fc, 0x002fe000); +- for (i = 0x341c; i <= 0x3438; i += 4) +- nv_wo32(chan, i, 0x001c527c); +- return 0; +-} +- +-static struct nouveau_oclass +-nv2a_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x2a), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv2a_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = nv20_graph_context_init, +- .fini = nv20_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv2a_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv20_graph_intr; +- nv_engine(priv)->cclass = &nv2a_graph_cclass; +- nv_engine(priv)->sclass = nv25_graph_sclass; +- nv_engine(priv)->tile_prog = nv20_graph_tile_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv2a_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x2a), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv2a_graph_ctor, +- .dtor = nv20_graph_dtor, +- .init = nv20_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c +deleted file mode 100644 +index 2f9dbc70..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv30.c ++++ /dev/null +@@ -1,237 +0,0 @@ +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include "nv20.h" +-#include "regs.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv30_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ +- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ +- { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ +- { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ +- { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ +- { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ +- { 0x0397, &nv04_graph_ofuncs, NULL }, /* rankine */ +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv30_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_chan *chan; +- int ret, i; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x5f48, +- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- chan->chid = nouveau_fifo_chan(parent)->chid; +- +- nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); +- nv_wo32(chan, 0x0410, 0x00000101); +- nv_wo32(chan, 0x0424, 0x00000111); +- nv_wo32(chan, 0x0428, 0x00000060); +- nv_wo32(chan, 0x0444, 0x00000080); +- nv_wo32(chan, 0x0448, 0xffff0000); +- nv_wo32(chan, 0x044c, 0x00000001); +- nv_wo32(chan, 0x0460, 0x44400000); +- nv_wo32(chan, 0x048c, 0xffff0000); +- for (i = 0x04e0; i < 0x04e8; i += 4) +- nv_wo32(chan, i, 0x0fff0000); +- nv_wo32(chan, 0x04ec, 0x00011100); +- for (i = 0x0508; i < 0x0548; i += 4) +- nv_wo32(chan, i, 0x07ff0000); +- nv_wo32(chan, 0x0550, 0x4b7fffff); +- nv_wo32(chan, 0x058c, 0x00000080); +- nv_wo32(chan, 0x0590, 0x30201000); +- nv_wo32(chan, 0x0594, 0x70605040); +- nv_wo32(chan, 0x0598, 0xb8a89888); +- nv_wo32(chan, 0x059c, 0xf8e8d8c8); +- nv_wo32(chan, 0x05b0, 0xb0000000); +- for (i = 0x0600; i < 0x0640; i += 4) +- nv_wo32(chan, i, 0x00010588); +- for (i = 0x0640; i < 0x0680; i += 4) +- nv_wo32(chan, i, 0x00030303); +- for (i = 0x06c0; i < 0x0700; i += 4) +- nv_wo32(chan, i, 0x0008aae4); +- for (i = 0x0700; i < 0x0740; i += 4) +- nv_wo32(chan, i, 0x01012000); +- for (i = 0x0740; i < 0x0780; i += 4) +- nv_wo32(chan, i, 0x00080008); +- nv_wo32(chan, 0x085c, 0x00040000); +- nv_wo32(chan, 0x0860, 0x00010000); +- for (i = 0x0864; i < 0x0874; i += 4) +- nv_wo32(chan, i, 0x00040004); +- for (i = 0x1f18; i <= 0x3088 ; i += 16) { +- nv_wo32(chan, i + 0, 0x10700ff9); +- nv_wo32(chan, i + 1, 0x0436086c); +- nv_wo32(chan, i + 2, 0x000c001b); +- } +- for (i = 0x30b8; i < 0x30c8; i += 4) +- nv_wo32(chan, i, 0x0000ffff); +- nv_wo32(chan, 0x344c, 0x3f800000); +- nv_wo32(chan, 0x3808, 0x3f800000); +- nv_wo32(chan, 0x381c, 0x3f800000); +- nv_wo32(chan, 0x3848, 0x40000000); +- nv_wo32(chan, 0x384c, 0x3f800000); +- nv_wo32(chan, 0x3850, 0x3f000000); +- nv_wo32(chan, 0x3858, 0x40000000); +- nv_wo32(chan, 0x385c, 0x3f800000); +- nv_wo32(chan, 0x3864, 0xbf800000); +- nv_wo32(chan, 0x386c, 0xbf800000); +- return 0; +-} +- +-static struct nouveau_oclass +-nv30_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x30), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv30_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = nv20_graph_context_init, +- .fini = nv20_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv30_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv20_graph_intr; +- nv_engine(priv)->cclass = &nv30_graph_cclass; +- nv_engine(priv)->sclass = nv30_graph_sclass; +- nv_engine(priv)->tile_prog = nv20_graph_tile_prog; +- return 0; +-} +- +-int +-nv30_graph_init(struct nouveau_object *object) +-{ +- struct nouveau_engine *engine = nv_engine(object); +- struct nv20_graph_priv *priv = (void *)engine; +- struct nouveau_fb *pfb = nouveau_fb(object); +- int ret, i; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, NV20_PGRAPH_CHANNEL_CTX_TABLE, priv->ctxtab->addr >> 4); +- +- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); +- nv_wr32(priv, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); +- +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); +- nv_wr32(priv, 0x400890, 0x01b463ff); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xf2de0475); +- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); +- nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); +- nv_wr32(priv, 0x400B80, 0x1003d888); +- nv_wr32(priv, 0x400B84, 0x0c000000); +- nv_wr32(priv, 0x400098, 0x00000000); +- nv_wr32(priv, 0x40009C, 0x0005ad00); +- nv_wr32(priv, 0x400B88, 0x62ff00ff); /* suspiciously like PGRAPH_DEBUG_2 */ +- nv_wr32(priv, 0x4000a0, 0x00000000); +- nv_wr32(priv, 0x4000a4, 0x00000008); +- nv_wr32(priv, 0x4008a8, 0xb784a400); +- nv_wr32(priv, 0x400ba0, 0x002f8685); +- nv_wr32(priv, 0x400ba4, 0x00231f3f); +- nv_wr32(priv, 0x4008a4, 0x40000020); +- +- if (nv_device(priv)->chipset == 0x34) { +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0004); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00200201); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0008); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000008); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00EA0000); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000032); +- nv_wr32(priv, NV10_PGRAPH_RDI_INDEX, 0x00E00004); +- nv_wr32(priv, NV10_PGRAPH_RDI_DATA , 0x00000002); +- } +- +- nv_wr32(priv, 0x4000c0, 0x00000016); +- +- /* Turn all the tiling regions off. */ +- for (i = 0; i < pfb->tile.regions; i++) +- engine->tile_prog(engine, i); +- +- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10000100); +- nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); +- nv_wr32(priv, 0x0040075c , 0x00000001); +- +- /* begin RAM config */ +- /* vramsz = pci_resource_len(priv->dev->pdev, 0) - 1; */ +- nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); +- if (nv_device(priv)->chipset != 0x34) { +- nv_wr32(priv, 0x400750, 0x00EA0000); +- nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x400750, 0x00EA0004); +- nv_wr32(priv, 0x400754, nv_rd32(priv, 0x100204)); +- } +- return 0; +-} +- +-struct nouveau_oclass +-nv30_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x30), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv30_graph_ctor, +- .dtor = nv20_graph_dtor, +- .init = nv30_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c +deleted file mode 100644 +index 34dd26c7..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv34.c ++++ /dev/null +@@ -1,167 +0,0 @@ +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include "nv20.h" +-#include "regs.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv34_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ +- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ +- { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ +- { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ +- { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ +- { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ +- { 0x0697, &nv04_graph_ofuncs, NULL }, /* rankine */ +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv34_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_chan *chan; +- int ret, i; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x46dc, +- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- chan->chid = nouveau_fifo_chan(parent)->chid; +- +- nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); +- nv_wo32(chan, 0x040c, 0x01000101); +- nv_wo32(chan, 0x0420, 0x00000111); +- nv_wo32(chan, 0x0424, 0x00000060); +- nv_wo32(chan, 0x0440, 0x00000080); +- nv_wo32(chan, 0x0444, 0xffff0000); +- nv_wo32(chan, 0x0448, 0x00000001); +- nv_wo32(chan, 0x045c, 0x44400000); +- nv_wo32(chan, 0x0480, 0xffff0000); +- for (i = 0x04d4; i < 0x04dc; i += 4) +- nv_wo32(chan, i, 0x0fff0000); +- nv_wo32(chan, 0x04e0, 0x00011100); +- for (i = 0x04fc; i < 0x053c; i += 4) +- nv_wo32(chan, i, 0x07ff0000); +- nv_wo32(chan, 0x0544, 0x4b7fffff); +- nv_wo32(chan, 0x057c, 0x00000080); +- nv_wo32(chan, 0x0580, 0x30201000); +- nv_wo32(chan, 0x0584, 0x70605040); +- nv_wo32(chan, 0x0588, 0xb8a89888); +- nv_wo32(chan, 0x058c, 0xf8e8d8c8); +- nv_wo32(chan, 0x05a0, 0xb0000000); +- for (i = 0x05f0; i < 0x0630; i += 4) +- nv_wo32(chan, i, 0x00010588); +- for (i = 0x0630; i < 0x0670; i += 4) +- nv_wo32(chan, i, 0x00030303); +- for (i = 0x06b0; i < 0x06f0; i += 4) +- nv_wo32(chan, i, 0x0008aae4); +- for (i = 0x06f0; i < 0x0730; i += 4) +- nv_wo32(chan, i, 0x01012000); +- for (i = 0x0730; i < 0x0770; i += 4) +- nv_wo32(chan, i, 0x00080008); +- nv_wo32(chan, 0x0850, 0x00040000); +- nv_wo32(chan, 0x0854, 0x00010000); +- for (i = 0x0858; i < 0x0868; i += 4) +- nv_wo32(chan, i, 0x00040004); +- for (i = 0x15ac; i <= 0x271c ; i += 16) { +- nv_wo32(chan, i + 0, 0x10700ff9); +- nv_wo32(chan, i + 1, 0x0436086c); +- nv_wo32(chan, i + 2, 0x000c001b); +- } +- for (i = 0x274c; i < 0x275c; i += 4) +- nv_wo32(chan, i, 0x0000ffff); +- nv_wo32(chan, 0x2ae0, 0x3f800000); +- nv_wo32(chan, 0x2e9c, 0x3f800000); +- nv_wo32(chan, 0x2eb0, 0x3f800000); +- nv_wo32(chan, 0x2edc, 0x40000000); +- nv_wo32(chan, 0x2ee0, 0x3f800000); +- nv_wo32(chan, 0x2ee4, 0x3f000000); +- nv_wo32(chan, 0x2eec, 0x40000000); +- nv_wo32(chan, 0x2ef0, 0x3f800000); +- nv_wo32(chan, 0x2ef8, 0xbf800000); +- nv_wo32(chan, 0x2f00, 0xbf800000); +- return 0; +-} +- +-static struct nouveau_oclass +-nv34_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x34), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv34_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = nv20_graph_context_init, +- .fini = nv20_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv34_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv20_graph_intr; +- nv_engine(priv)->cclass = &nv34_graph_cclass; +- nv_engine(priv)->sclass = nv34_graph_sclass; +- nv_engine(priv)->tile_prog = nv20_graph_tile_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv34_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x34), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv34_graph_ctor, +- .dtor = nv20_graph_dtor, +- .init = nv30_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c +deleted file mode 100644 +index 2fb5756d..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv35.c ++++ /dev/null +@@ -1,165 +0,0 @@ +-#include +-#include +-#include +- +-#include +-#include +- +-#include "nv20.h" +-#include "regs.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv35_graph_sclass[] = { +- { 0x0012, &nv04_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv04_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv04_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv04_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv04_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv04_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv04_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv04_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv04_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv04_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv04_graph_ofuncs, NULL }, /* ifc */ +- { 0x009f, &nv04_graph_ofuncs, NULL }, /* imageblit */ +- { 0x0362, &nv04_graph_ofuncs, NULL }, /* surf2d (nv30) */ +- { 0x0389, &nv04_graph_ofuncs, NULL }, /* sifm (nv30) */ +- { 0x038a, &nv04_graph_ofuncs, NULL }, /* ifc (nv30) */ +- { 0x039e, &nv04_graph_ofuncs, NULL }, /* swzsurf (nv30) */ +- { 0x0497, &nv04_graph_ofuncs, NULL }, /* rankine */ +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv35_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_chan *chan; +- int ret, i; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, 0x577c, +- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- chan->chid = nouveau_fifo_chan(parent)->chid; +- +- nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24)); +- nv_wo32(chan, 0x040c, 0x00000101); +- nv_wo32(chan, 0x0420, 0x00000111); +- nv_wo32(chan, 0x0424, 0x00000060); +- nv_wo32(chan, 0x0440, 0x00000080); +- nv_wo32(chan, 0x0444, 0xffff0000); +- nv_wo32(chan, 0x0448, 0x00000001); +- nv_wo32(chan, 0x045c, 0x44400000); +- nv_wo32(chan, 0x0488, 0xffff0000); +- for (i = 0x04dc; i < 0x04e4; i += 4) +- nv_wo32(chan, i, 0x0fff0000); +- nv_wo32(chan, 0x04e8, 0x00011100); +- for (i = 0x0504; i < 0x0544; i += 4) +- nv_wo32(chan, i, 0x07ff0000); +- nv_wo32(chan, 0x054c, 0x4b7fffff); +- nv_wo32(chan, 0x0588, 0x00000080); +- nv_wo32(chan, 0x058c, 0x30201000); +- nv_wo32(chan, 0x0590, 0x70605040); +- nv_wo32(chan, 0x0594, 0xb8a89888); +- nv_wo32(chan, 0x0598, 0xf8e8d8c8); +- nv_wo32(chan, 0x05ac, 0xb0000000); +- for (i = 0x0604; i < 0x0644; i += 4) +- nv_wo32(chan, i, 0x00010588); +- for (i = 0x0644; i < 0x0684; i += 4) +- nv_wo32(chan, i, 0x00030303); +- for (i = 0x06c4; i < 0x0704; i += 4) +- nv_wo32(chan, i, 0x0008aae4); +- for (i = 0x0704; i < 0x0744; i += 4) +- nv_wo32(chan, i, 0x01012000); +- for (i = 0x0744; i < 0x0784; i += 4) +- nv_wo32(chan, i, 0x00080008); +- nv_wo32(chan, 0x0860, 0x00040000); +- nv_wo32(chan, 0x0864, 0x00010000); +- for (i = 0x0868; i < 0x0878; i += 4) +- nv_wo32(chan, i, 0x00040004); +- for (i = 0x1f1c; i <= 0x308c ; i += 16) { +- nv_wo32(chan, i + 0, 0x10700ff9); +- nv_wo32(chan, i + 4, 0x0436086c); +- nv_wo32(chan, i + 8, 0x000c001b); +- } +- for (i = 0x30bc; i < 0x30cc; i += 4) +- nv_wo32(chan, i, 0x0000ffff); +- nv_wo32(chan, 0x3450, 0x3f800000); +- nv_wo32(chan, 0x380c, 0x3f800000); +- nv_wo32(chan, 0x3820, 0x3f800000); +- nv_wo32(chan, 0x384c, 0x40000000); +- nv_wo32(chan, 0x3850, 0x3f800000); +- nv_wo32(chan, 0x3854, 0x3f000000); +- nv_wo32(chan, 0x385c, 0x40000000); +- nv_wo32(chan, 0x3860, 0x3f800000); +- nv_wo32(chan, 0x3868, 0xbf800000); +- nv_wo32(chan, 0x3870, 0xbf800000); +- return 0; +-} +- +-static struct nouveau_oclass +-nv35_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x35), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv35_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = nv20_graph_context_init, +- .fini = nv20_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv35_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv20_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv20_graph_intr; +- nv_engine(priv)->cclass = &nv35_graph_cclass; +- nv_engine(priv)->sclass = nv35_graph_sclass; +- nv_engine(priv)->tile_prog = nv20_graph_tile_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv35_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x35), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv35_graph_ctor, +- .dtor = nv20_graph_dtor, +- .init = nv30_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c +deleted file mode 100644 +index 4f401174..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.c ++++ /dev/null +@@ -1,536 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +- +-#include "nv40.h" +-#include "regs.h" +- +-struct nv40_graph_priv { +- struct nouveau_graph base; +- u32 size; +-}; +- +-struct nv40_graph_chan { +- struct nouveau_graph_chan base; +-}; +- +-static u64 +-nv40_graph_units(struct nouveau_graph *graph) +-{ +- struct nv40_graph_priv *priv = (void *)graph; +- +- return nv_rd32(priv, 0x1540); +-} +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static int +-nv40_graph_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj *obj; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, +- 20, 16, 0, &obj); +- *pobject = nv_object(obj); +- if (ret) +- return ret; +- +- nv_wo32(obj, 0x00, nv_mclass(obj)); +- nv_wo32(obj, 0x04, 0x00000000); +- nv_wo32(obj, 0x08, 0x00000000); +-#ifdef __BIG_ENDIAN +- nv_mo32(obj, 0x08, 0x01000000, 0x01000000); +-#endif +- nv_wo32(obj, 0x0c, 0x00000000); +- nv_wo32(obj, 0x10, 0x00000000); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv40_graph_ofuncs = { +- .ctor = nv40_graph_object_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +-}; +- +-static struct nouveau_oclass +-nv40_graph_sclass[] = { +- { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */ +- { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */ +- { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */ +- { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */ +- { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */ +- { 0x4097, &nv40_graph_ofuncs, NULL }, /* curie */ +- {}, +-}; +- +-static struct nouveau_oclass +-nv44_graph_sclass[] = { +- { 0x0012, &nv40_graph_ofuncs, NULL }, /* beta1 */ +- { 0x0019, &nv40_graph_ofuncs, NULL }, /* clip */ +- { 0x0030, &nv40_graph_ofuncs, NULL }, /* null */ +- { 0x0039, &nv40_graph_ofuncs, NULL }, /* m2mf */ +- { 0x0043, &nv40_graph_ofuncs, NULL }, /* rop */ +- { 0x0044, &nv40_graph_ofuncs, NULL }, /* patt */ +- { 0x004a, &nv40_graph_ofuncs, NULL }, /* gdi */ +- { 0x0062, &nv40_graph_ofuncs, NULL }, /* surf2d */ +- { 0x0072, &nv40_graph_ofuncs, NULL }, /* beta4 */ +- { 0x0089, &nv40_graph_ofuncs, NULL }, /* sifm */ +- { 0x008a, &nv40_graph_ofuncs, NULL }, /* ifc */ +- { 0x009f, &nv40_graph_ofuncs, NULL }, /* imageblit */ +- { 0x3062, &nv40_graph_ofuncs, NULL }, /* surf2d (nv40) */ +- { 0x3089, &nv40_graph_ofuncs, NULL }, /* sifm (nv40) */ +- { 0x309e, &nv40_graph_ofuncs, NULL }, /* swzsurf (nv40) */ +- { 0x4497, &nv40_graph_ofuncs, NULL }, /* curie */ +- {}, +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv40_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv40_graph_priv *priv = (void *)engine; +- struct nv40_graph_chan *chan; +- int ret; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, +- priv->size, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- nv40_grctx_fill(nv_device(priv), nv_gpuobj(chan)); +- nv_wo32(chan, 0x00000, nv_gpuobj(chan)->addr >> 4); +- return 0; +-} +- +-static int +-nv40_graph_context_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv40_graph_priv *priv = (void *)object->engine; +- struct nv40_graph_chan *chan = (void *)object; +- u32 inst = 0x01000000 | nv_gpuobj(chan)->addr >> 4; +- int ret = 0; +- +- nv_mask(priv, 0x400720, 0x00000001, 0x00000000); +- +- if (nv_rd32(priv, 0x40032c) == inst) { +- if (suspend) { +- nv_wr32(priv, 0x400720, 0x00000000); +- nv_wr32(priv, 0x400784, inst); +- nv_mask(priv, 0x400310, 0x00000020, 0x00000020); +- nv_mask(priv, 0x400304, 0x00000001, 0x00000001); +- if (!nv_wait(priv, 0x400300, 0x00000001, 0x00000000)) { +- u32 insn = nv_rd32(priv, 0x400308); +- nv_warn(priv, "ctxprog timeout 0x%08x\n", insn); +- ret = -EBUSY; +- } +- } +- +- nv_mask(priv, 0x40032c, 0x01000000, 0x00000000); +- } +- +- if (nv_rd32(priv, 0x400330) == inst) +- nv_mask(priv, 0x400330, 0x01000000, 0x00000000); +- +- nv_mask(priv, 0x400720, 0x00000001, 0x00000001); +- return ret; +-} +- +-static struct nouveau_oclass +-nv40_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = nv40_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static void +-nv40_graph_tile_prog(struct nouveau_engine *engine, int i) +-{ +- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; +- struct nouveau_fifo *pfifo = nouveau_fifo(engine); +- struct nv40_graph_priv *priv = (void *)engine; +- unsigned long flags; +- +- pfifo->pause(pfifo, &flags); +- nv04_graph_idle(priv); +- +- switch (nv_device(priv)->chipset) { +- case 0x40: +- case 0x41: +- case 0x42: +- case 0x43: +- case 0x45: +- case 0x4e: +- nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); +- nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); +- nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); +- nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); +- nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); +- nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); +- switch (nv_device(priv)->chipset) { +- case 0x40: +- case 0x45: +- nv_wr32(priv, NV20_PGRAPH_ZCOMP(i), tile->zcomp); +- nv_wr32(priv, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); +- break; +- case 0x41: +- case 0x42: +- case 0x43: +- nv_wr32(priv, NV41_PGRAPH_ZCOMP0(i), tile->zcomp); +- nv_wr32(priv, NV41_PGRAPH_ZCOMP1(i), tile->zcomp); +- break; +- default: +- break; +- } +- break; +- case 0x44: +- case 0x4a: +- nv_wr32(priv, NV20_PGRAPH_TSIZE(i), tile->pitch); +- nv_wr32(priv, NV20_PGRAPH_TLIMIT(i), tile->limit); +- nv_wr32(priv, NV20_PGRAPH_TILE(i), tile->addr); +- break; +- case 0x46: +- case 0x4c: +- case 0x47: +- case 0x49: +- case 0x4b: +- case 0x63: +- case 0x67: +- case 0x68: +- nv_wr32(priv, NV47_PGRAPH_TSIZE(i), tile->pitch); +- nv_wr32(priv, NV47_PGRAPH_TLIMIT(i), tile->limit); +- nv_wr32(priv, NV47_PGRAPH_TILE(i), tile->addr); +- nv_wr32(priv, NV40_PGRAPH_TSIZE1(i), tile->pitch); +- nv_wr32(priv, NV40_PGRAPH_TLIMIT1(i), tile->limit); +- nv_wr32(priv, NV40_PGRAPH_TILE1(i), tile->addr); +- switch (nv_device(priv)->chipset) { +- case 0x47: +- case 0x49: +- case 0x4b: +- nv_wr32(priv, NV47_PGRAPH_ZCOMP0(i), tile->zcomp); +- nv_wr32(priv, NV47_PGRAPH_ZCOMP1(i), tile->zcomp); +- break; +- default: +- break; +- } +- break; +- default: +- break; +- } +- +- pfifo->start(pfifo, &flags); +-} +- +-static void +-nv40_graph_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nouveau_handle *handle = NULL; +- struct nv40_graph_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR); +- u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE); +- u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS); +- u32 inst = nv_rd32(priv, 0x40032c) & 0x000fffff; +- u32 addr = nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR); +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00001ffc); +- u32 data = nv_rd32(priv, NV04_PGRAPH_TRAPPED_DATA); +- u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xffff; +- u32 show = stat; +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat & NV_PGRAPH_INTR_ERROR) { +- if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) { +- handle = nouveau_handle_get_class(engctx, class); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~NV_PGRAPH_INTR_ERROR; +- nouveau_handle_put(handle); +- } +- +- if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) { +- nv_mask(priv, 0x402000, 0, 0); +- } +- } +- +- nv_wr32(priv, NV03_PGRAPH_INTR, stat); +- nv_wr32(priv, NV04_PGRAPH_FIFO, 0x00000001); +- +- if (show) { +- nv_error(priv, "%s", ""); +- nouveau_bitfield_print(nv10_graph_intr_name, show); +- pr_cont(" nsource:"); +- nouveau_bitfield_print(nv04_graph_nsource, nsource); +- pr_cont(" nstatus:"); +- nouveau_bitfield_print(nv10_graph_nstatus, nstatus); +- pr_cont("\n"); +- nv_error(priv, +- "ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, inst << 4, nouveau_client_name(engctx), subc, +- class, mthd, data); +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static int +-nv40_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv40_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00001000; +- nv_subdev(priv)->intr = nv40_graph_intr; +- nv_engine(priv)->cclass = &nv40_graph_cclass; +- if (nv44_graph_class(priv)) +- nv_engine(priv)->sclass = nv44_graph_sclass; +- else +- nv_engine(priv)->sclass = nv40_graph_sclass; +- nv_engine(priv)->tile_prog = nv40_graph_tile_prog; +- +- priv->base.units = nv40_graph_units; +- return 0; +-} +- +-static int +-nv40_graph_init(struct nouveau_object *object) +-{ +- struct nouveau_engine *engine = nv_engine(object); +- struct nouveau_fb *pfb = nouveau_fb(object); +- struct nv40_graph_priv *priv = (void *)engine; +- int ret, i, j; +- u32 vramsz; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- /* generate and upload context program */ +- ret = nv40_grctx_init(nv_device(priv), &priv->size); +- if (ret) +- return ret; +- +- /* No context present currently */ +- nv_wr32(priv, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); +- +- nv_wr32(priv, NV03_PGRAPH_INTR , 0xFFFFFFFF); +- nv_wr32(priv, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); +- +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_0, 0x00000000); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_1, 0x401287c0); +- nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0xe0de8055); +- nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x00008000); +- nv_wr32(priv, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); +- +- nv_wr32(priv, NV10_PGRAPH_CTX_CONTROL, 0x10010100); +- nv_wr32(priv, NV10_PGRAPH_STATE , 0xFFFFFFFF); +- +- j = nv_rd32(priv, 0x1540) & 0xff; +- if (j) { +- for (i = 0; !(j & 1); j >>= 1, i++) +- ; +- nv_wr32(priv, 0x405000, i); +- } +- +- if (nv_device(priv)->chipset == 0x40) { +- nv_wr32(priv, 0x4009b0, 0x83280fff); +- nv_wr32(priv, 0x4009b4, 0x000000a0); +- } else { +- nv_wr32(priv, 0x400820, 0x83280eff); +- nv_wr32(priv, 0x400824, 0x000000a0); +- } +- +- switch (nv_device(priv)->chipset) { +- case 0x40: +- case 0x45: +- nv_wr32(priv, 0x4009b8, 0x0078e366); +- nv_wr32(priv, 0x4009bc, 0x0000014c); +- break; +- case 0x41: +- case 0x42: /* pciid also 0x00Cx */ +- /* case 0x0120: XXX (pciid) */ +- nv_wr32(priv, 0x400828, 0x007596ff); +- nv_wr32(priv, 0x40082c, 0x00000108); +- break; +- case 0x43: +- nv_wr32(priv, 0x400828, 0x0072cb77); +- nv_wr32(priv, 0x40082c, 0x00000108); +- break; +- case 0x44: +- case 0x46: /* G72 */ +- case 0x4a: +- case 0x4c: /* G7x-based C51 */ +- case 0x4e: +- nv_wr32(priv, 0x400860, 0); +- nv_wr32(priv, 0x400864, 0); +- break; +- case 0x47: /* G70 */ +- case 0x49: /* G71 */ +- case 0x4b: /* G73 */ +- nv_wr32(priv, 0x400828, 0x07830610); +- nv_wr32(priv, 0x40082c, 0x0000016A); +- break; +- default: +- break; +- } +- +- nv_wr32(priv, 0x400b38, 0x2ffff800); +- nv_wr32(priv, 0x400b3c, 0x00006000); +- +- /* Tiling related stuff. */ +- switch (nv_device(priv)->chipset) { +- case 0x44: +- case 0x4a: +- nv_wr32(priv, 0x400bc4, 0x1003d888); +- nv_wr32(priv, 0x400bbc, 0xb7a7b500); +- break; +- case 0x46: +- nv_wr32(priv, 0x400bc4, 0x0000e024); +- nv_wr32(priv, 0x400bbc, 0xb7a7b520); +- break; +- case 0x4c: +- case 0x4e: +- case 0x67: +- nv_wr32(priv, 0x400bc4, 0x1003d888); +- nv_wr32(priv, 0x400bbc, 0xb7a7b540); +- break; +- default: +- break; +- } +- +- /* Turn all the tiling regions off. */ +- for (i = 0; i < pfb->tile.regions; i++) +- engine->tile_prog(engine, i); +- +- /* begin RAM config */ +- vramsz = nv_device_resource_len(nv_device(priv), 0) - 1; +- switch (nv_device(priv)->chipset) { +- case 0x40: +- nv_wr32(priv, 0x4009A4, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x4009A8, nv_rd32(priv, 0x100204)); +- nv_wr32(priv, 0x4069A4, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x4069A8, nv_rd32(priv, 0x100204)); +- nv_wr32(priv, 0x400820, 0); +- nv_wr32(priv, 0x400824, 0); +- nv_wr32(priv, 0x400864, vramsz); +- nv_wr32(priv, 0x400868, vramsz); +- break; +- default: +- switch (nv_device(priv)->chipset) { +- case 0x41: +- case 0x42: +- case 0x43: +- case 0x45: +- case 0x4e: +- case 0x44: +- case 0x4a: +- nv_wr32(priv, 0x4009F0, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x4009F4, nv_rd32(priv, 0x100204)); +- break; +- default: +- nv_wr32(priv, 0x400DF0, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x400DF4, nv_rd32(priv, 0x100204)); +- break; +- } +- nv_wr32(priv, 0x4069F0, nv_rd32(priv, 0x100200)); +- nv_wr32(priv, 0x4069F4, nv_rd32(priv, 0x100204)); +- nv_wr32(priv, 0x400840, 0); +- nv_wr32(priv, 0x400844, 0); +- nv_wr32(priv, 0x4008A0, vramsz); +- nv_wr32(priv, 0x4008A4, vramsz); +- break; +- } +- +- return 0; +-} +- +-struct nouveau_oclass +-nv40_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_graph_ctor, +- .dtor = _nouveau_graph_dtor, +- .init = nv40_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h +deleted file mode 100644 +index ad820937..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv40.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-#ifndef __NV40_GRAPH_H__ +-#define __NV40_GRAPH_H__ +- +-#include +-#include +- +-/* returns 1 if device is one of the nv4x using the 0x4497 object class, +- * helpful to determine a number of other hardware features +- */ +-static inline int +-nv44_graph_class(void *priv) +-{ +- struct nouveau_device *device = nv_device(priv); +- +- if ((device->chipset & 0xf0) == 0x60) +- return 1; +- +- return !(0x0baf & (1 << (device->chipset & 0x0f))); +-} +- +-int nv40_grctx_init(struct nouveau_device *, u32 *size); +-void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c +deleted file mode 100644 +index 38e0aa26..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.c ++++ /dev/null +@@ -1,1009 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +-#include +- +-#include "nv50.h" +- +-struct nv50_graph_priv { +- struct nouveau_graph base; +- spinlock_t lock; +- u32 size; +-}; +- +-struct nv50_graph_chan { +- struct nouveau_graph_chan base; +-}; +- +-static u64 +-nv50_graph_units(struct nouveau_graph *graph) +-{ +- struct nv50_graph_priv *priv = (void *)graph; +- +- return nv_rd32(priv, 0x1540); +-} +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static int +-nv50_graph_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj *obj; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, +- 16, 16, 0, &obj); +- *pobject = nv_object(obj); +- if (ret) +- return ret; +- +- nv_wo32(obj, 0x00, nv_mclass(obj)); +- nv_wo32(obj, 0x04, 0x00000000); +- nv_wo32(obj, 0x08, 0x00000000); +- nv_wo32(obj, 0x0c, 0x00000000); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nv50_graph_ofuncs = { +- .ctor = nv50_graph_object_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +-}; +- +-static struct nouveau_oclass +-nv50_graph_sclass[] = { +- { 0x0030, &nv50_graph_ofuncs }, +- { 0x502d, &nv50_graph_ofuncs }, +- { 0x5039, &nv50_graph_ofuncs }, +- { 0x5097, &nv50_graph_ofuncs }, +- { 0x50c0, &nv50_graph_ofuncs }, +- {} +-}; +- +-static struct nouveau_oclass +-nv84_graph_sclass[] = { +- { 0x0030, &nv50_graph_ofuncs }, +- { 0x502d, &nv50_graph_ofuncs }, +- { 0x5039, &nv50_graph_ofuncs }, +- { 0x50c0, &nv50_graph_ofuncs }, +- { 0x8297, &nv50_graph_ofuncs }, +- {} +-}; +- +-static struct nouveau_oclass +-nva0_graph_sclass[] = { +- { 0x0030, &nv50_graph_ofuncs }, +- { 0x502d, &nv50_graph_ofuncs }, +- { 0x5039, &nv50_graph_ofuncs }, +- { 0x50c0, &nv50_graph_ofuncs }, +- { 0x8397, &nv50_graph_ofuncs }, +- {} +-}; +- +-static struct nouveau_oclass +-nva3_graph_sclass[] = { +- { 0x0030, &nv50_graph_ofuncs }, +- { 0x502d, &nv50_graph_ofuncs }, +- { 0x5039, &nv50_graph_ofuncs }, +- { 0x50c0, &nv50_graph_ofuncs }, +- { 0x8597, &nv50_graph_ofuncs }, +- { 0x85c0, &nv50_graph_ofuncs }, +- {} +-}; +- +-static struct nouveau_oclass +-nvaf_graph_sclass[] = { +- { 0x0030, &nv50_graph_ofuncs }, +- { 0x502d, &nv50_graph_ofuncs }, +- { 0x5039, &nv50_graph_ofuncs }, +- { 0x50c0, &nv50_graph_ofuncs }, +- { 0x85c0, &nv50_graph_ofuncs }, +- { 0x8697, &nv50_graph_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-static int +-nv50_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_graph_priv *priv = (void *)engine; +- struct nv50_graph_chan *chan; +- int ret; +- +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, +- priv->size, 0, +- NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- nv50_grctx_fill(nv_device(priv), nv_gpuobj(chan)); +- return 0; +-} +- +-static struct nouveau_oclass +-nv50_graph_cclass = { +- .handle = NV_ENGCTX(GR, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_graph_context_ctor, +- .dtor = _nouveau_graph_context_dtor, +- .init = _nouveau_graph_context_init, +- .fini = _nouveau_graph_context_fini, +- .rd32 = _nouveau_graph_context_rd32, +- .wr32 = _nouveau_graph_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_bitfield nv50_pgraph_status[] = { +- { 0x00000001, "BUSY" }, /* set when any bit is set */ +- { 0x00000002, "DISPATCH" }, +- { 0x00000004, "UNK2" }, +- { 0x00000008, "UNK3" }, +- { 0x00000010, "UNK4" }, +- { 0x00000020, "UNK5" }, +- { 0x00000040, "M2MF" }, +- { 0x00000080, "UNK7" }, +- { 0x00000100, "CTXPROG" }, +- { 0x00000200, "VFETCH" }, +- { 0x00000400, "CCACHE_PREGEOM" }, +- { 0x00000800, "STRMOUT_VATTR_POSTGEOM" }, +- { 0x00001000, "VCLIP" }, +- { 0x00002000, "RATTR_APLANE" }, +- { 0x00004000, "TRAST" }, +- { 0x00008000, "CLIPID" }, +- { 0x00010000, "ZCULL" }, +- { 0x00020000, "ENG2D" }, +- { 0x00040000, "RMASK" }, +- { 0x00080000, "TPC_RAST" }, +- { 0x00100000, "TPC_PROP" }, +- { 0x00200000, "TPC_TEX" }, +- { 0x00400000, "TPC_GEOM" }, +- { 0x00800000, "TPC_MP" }, +- { 0x01000000, "ROP" }, +- {} +-}; +- +-static const char *const nv50_pgraph_vstatus_0[] = { +- "VFETCH", "CCACHE", "PREGEOM", "POSTGEOM", "VATTR", "STRMOUT", "VCLIP", +- NULL +-}; +- +-static const char *const nv50_pgraph_vstatus_1[] = { +- "TPC_RAST", "TPC_PROP", "TPC_TEX", "TPC_GEOM", "TPC_MP", NULL +-}; +- +-static const char *const nv50_pgraph_vstatus_2[] = { +- "RATTR", "APLANE", "TRAST", "CLIPID", "ZCULL", "ENG2D", "RMASK", +- "ROP", NULL +-}; +- +-static void nouveau_pgraph_vstatus_print(struct nv50_graph_priv *priv, int r, +- const char *const units[], u32 status) +-{ +- int i; +- +- nv_error(priv, "PGRAPH_VSTATUS%d: 0x%08x", r, status); +- +- for (i = 0; units[i] && status; i++) { +- if ((status & 7) == 1) +- pr_cont(" %s", units[i]); +- status >>= 3; +- } +- if (status) +- pr_cont(" (invalid: 0x%x)", status); +- pr_cont("\n"); +-} +- +-static int +-nv84_graph_tlb_flush(struct nouveau_engine *engine) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(engine); +- struct nv50_graph_priv *priv = (void *)engine; +- bool idle, timeout = false; +- unsigned long flags; +- u64 start; +- u32 tmp; +- +- spin_lock_irqsave(&priv->lock, flags); +- nv_mask(priv, 0x400500, 0x00000001, 0x00000000); +- +- start = ptimer->read(ptimer); +- do { +- idle = true; +- +- for (tmp = nv_rd32(priv, 0x400380); tmp && idle; tmp >>= 3) { +- if ((tmp & 7) == 1) +- idle = false; +- } +- +- for (tmp = nv_rd32(priv, 0x400384); tmp && idle; tmp >>= 3) { +- if ((tmp & 7) == 1) +- idle = false; +- } +- +- for (tmp = nv_rd32(priv, 0x400388); tmp && idle; tmp >>= 3) { +- if ((tmp & 7) == 1) +- idle = false; +- } +- } while (!idle && +- !(timeout = ptimer->read(ptimer) - start > 2000000000)); +- +- if (timeout) { +- nv_error(priv, "PGRAPH TLB flush idle timeout fail\n"); +- +- tmp = nv_rd32(priv, 0x400700); +- nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp); +- nouveau_bitfield_print(nv50_pgraph_status, tmp); +- pr_cont("\n"); +- +- nouveau_pgraph_vstatus_print(priv, 0, nv50_pgraph_vstatus_0, +- nv_rd32(priv, 0x400380)); +- nouveau_pgraph_vstatus_print(priv, 1, nv50_pgraph_vstatus_1, +- nv_rd32(priv, 0x400384)); +- nouveau_pgraph_vstatus_print(priv, 2, nv50_pgraph_vstatus_2, +- nv_rd32(priv, 0x400388)); +- } +- +- +- nv_wr32(priv, 0x100c80, 0x00000001); +- if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) +- nv_error(priv, "vm flush timeout\n"); +- nv_mask(priv, 0x400500, 0x00000001, 0x00000001); +- spin_unlock_irqrestore(&priv->lock, flags); +- return timeout ? -EBUSY : 0; +-} +- +-static const struct nouveau_bitfield nv50_mp_exec_errors[] = { +- { 0x01, "STACK_UNDERFLOW" }, +- { 0x02, "STACK_MISMATCH" }, +- { 0x04, "QUADON_ACTIVE" }, +- { 0x08, "TIMEOUT" }, +- { 0x10, "INVALID_OPCODE" }, +- { 0x20, "PM_OVERFLOW" }, +- { 0x40, "BREAKPOINT" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_mpc_traps[] = { +- { 0x0000001, "LOCAL_LIMIT_READ" }, +- { 0x0000010, "LOCAL_LIMIT_WRITE" }, +- { 0x0000040, "STACK_LIMIT" }, +- { 0x0000100, "GLOBAL_LIMIT_READ" }, +- { 0x0001000, "GLOBAL_LIMIT_WRITE" }, +- { 0x0010000, "MP0" }, +- { 0x0020000, "MP1" }, +- { 0x0040000, "GLOBAL_LIMIT_RED" }, +- { 0x0400000, "GLOBAL_LIMIT_ATOM" }, +- { 0x4000000, "MP2" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_tex_traps[] = { +- { 0x00000001, "" }, /* any bit set? */ +- { 0x00000002, "FAULT" }, +- { 0x00000004, "STORAGE_TYPE_MISMATCH" }, +- { 0x00000008, "LINEAR_MISMATCH" }, +- { 0x00000020, "WRONG_MEMTYPE" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_graph_trap_m2mf[] = { +- { 0x00000001, "NOTIFY" }, +- { 0x00000002, "IN" }, +- { 0x00000004, "OUT" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_graph_trap_vfetch[] = { +- { 0x00000001, "FAULT" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_graph_trap_strmout[] = { +- { 0x00000001, "FAULT" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_graph_trap_ccache[] = { +- { 0x00000001, "FAULT" }, +- {} +-}; +- +-/* There must be a *lot* of these. Will take some time to gather them up. */ +-const struct nouveau_enum nv50_data_error_names[] = { +- { 0x00000003, "INVALID_OPERATION", NULL }, +- { 0x00000004, "INVALID_VALUE", NULL }, +- { 0x00000005, "INVALID_ENUM", NULL }, +- { 0x00000008, "INVALID_OBJECT", NULL }, +- { 0x00000009, "READ_ONLY_OBJECT", NULL }, +- { 0x0000000a, "SUPERVISOR_OBJECT", NULL }, +- { 0x0000000b, "INVALID_ADDRESS_ALIGNMENT", NULL }, +- { 0x0000000c, "INVALID_BITFIELD", NULL }, +- { 0x0000000d, "BEGIN_END_ACTIVE", NULL }, +- { 0x0000000e, "SEMANTIC_COLOR_BACK_OVER_LIMIT", NULL }, +- { 0x0000000f, "VIEWPORT_ID_NEEDS_GP", NULL }, +- { 0x00000010, "RT_DOUBLE_BIND", NULL }, +- { 0x00000011, "RT_TYPES_MISMATCH", NULL }, +- { 0x00000012, "RT_LINEAR_WITH_ZETA", NULL }, +- { 0x00000015, "FP_TOO_FEW_REGS", NULL }, +- { 0x00000016, "ZETA_FORMAT_CSAA_MISMATCH", NULL }, +- { 0x00000017, "RT_LINEAR_WITH_MSAA", NULL }, +- { 0x00000018, "FP_INTERPOLANT_START_OVER_LIMIT", NULL }, +- { 0x00000019, "SEMANTIC_LAYER_OVER_LIMIT", NULL }, +- { 0x0000001a, "RT_INVALID_ALIGNMENT", NULL }, +- { 0x0000001b, "SAMPLER_OVER_LIMIT", NULL }, +- { 0x0000001c, "TEXTURE_OVER_LIMIT", NULL }, +- { 0x0000001e, "GP_TOO_MANY_OUTPUTS", NULL }, +- { 0x0000001f, "RT_BPP128_WITH_MS8", NULL }, +- { 0x00000021, "Z_OUT_OF_BOUNDS", NULL }, +- { 0x00000023, "XY_OUT_OF_BOUNDS", NULL }, +- { 0x00000024, "VP_ZERO_INPUTS", NULL }, +- { 0x00000027, "CP_MORE_PARAMS_THAN_SHARED", NULL }, +- { 0x00000028, "CP_NO_REG_SPACE_STRIPED", NULL }, +- { 0x00000029, "CP_NO_REG_SPACE_PACKED", NULL }, +- { 0x0000002a, "CP_NOT_ENOUGH_WARPS", NULL }, +- { 0x0000002b, "CP_BLOCK_SIZE_MISMATCH", NULL }, +- { 0x0000002c, "CP_NOT_ENOUGH_LOCAL_WARPS", NULL }, +- { 0x0000002d, "CP_NOT_ENOUGH_STACK_WARPS", NULL }, +- { 0x0000002e, "CP_NO_BLOCKDIM_LATCH", NULL }, +- { 0x00000031, "ENG2D_FORMAT_MISMATCH", NULL }, +- { 0x0000003f, "PRIMITIVE_ID_NEEDS_GP", NULL }, +- { 0x00000044, "SEMANTIC_VIEWPORT_OVER_LIMIT", NULL }, +- { 0x00000045, "SEMANTIC_COLOR_FRONT_OVER_LIMIT", NULL }, +- { 0x00000046, "LAYER_ID_NEEDS_GP", NULL }, +- { 0x00000047, "SEMANTIC_CLIP_OVER_LIMIT", NULL }, +- { 0x00000048, "SEMANTIC_PTSZ_OVER_LIMIT", NULL }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_graph_intr_name[] = { +- { 0x00000001, "NOTIFY" }, +- { 0x00000002, "COMPUTE_QUERY" }, +- { 0x00000010, "ILLEGAL_MTHD" }, +- { 0x00000020, "ILLEGAL_CLASS" }, +- { 0x00000040, "DOUBLE_NOTIFY" }, +- { 0x00001000, "CONTEXT_SWITCH" }, +- { 0x00010000, "BUFFER_NOTIFY" }, +- { 0x00100000, "DATA_ERROR" }, +- { 0x00200000, "TRAP" }, +- { 0x01000000, "SINGLE_STEP" }, +- {} +-}; +- +-static const struct nouveau_bitfield nv50_graph_trap_prop[] = { +- { 0x00000004, "SURF_WIDTH_OVERRUN" }, +- { 0x00000008, "SURF_HEIGHT_OVERRUN" }, +- { 0x00000010, "DST2D_FAULT" }, +- { 0x00000020, "ZETA_FAULT" }, +- { 0x00000040, "RT_FAULT" }, +- { 0x00000080, "CUDA_FAULT" }, +- { 0x00000100, "DST2D_STORAGE_TYPE_MISMATCH" }, +- { 0x00000200, "ZETA_STORAGE_TYPE_MISMATCH" }, +- { 0x00000400, "RT_STORAGE_TYPE_MISMATCH" }, +- { 0x00000800, "DST2D_LINEAR_MISMATCH" }, +- { 0x00001000, "RT_LINEAR_MISMATCH" }, +- {} +-}; +- +-static void +-nv50_priv_prop_trap(struct nv50_graph_priv *priv, +- u32 ustatus_addr, u32 ustatus, u32 tp) +-{ +- u32 e0c = nv_rd32(priv, ustatus_addr + 0x04); +- u32 e10 = nv_rd32(priv, ustatus_addr + 0x08); +- u32 e14 = nv_rd32(priv, ustatus_addr + 0x0c); +- u32 e18 = nv_rd32(priv, ustatus_addr + 0x10); +- u32 e1c = nv_rd32(priv, ustatus_addr + 0x14); +- u32 e20 = nv_rd32(priv, ustatus_addr + 0x18); +- u32 e24 = nv_rd32(priv, ustatus_addr + 0x1c); +- +- /* CUDA memory: l[], g[] or stack. */ +- if (ustatus & 0x00000080) { +- if (e18 & 0x80000000) { +- /* g[] read fault? */ +- nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global read fault at address %02x%08x\n", +- tp, e14, e10 | ((e18 >> 24) & 0x1f)); +- e18 &= ~0x1f000000; +- } else if (e18 & 0xc) { +- /* g[] write fault? */ +- nv_error(priv, "TRAP_PROP - TP %d - CUDA_FAULT - Global write fault at address %02x%08x\n", +- tp, e14, e10 | ((e18 >> 7) & 0x1f)); +- e18 &= ~0x00000f80; +- } else { +- nv_error(priv, "TRAP_PROP - TP %d - Unknown CUDA fault at address %02x%08x\n", +- tp, e14, e10); +- } +- ustatus &= ~0x00000080; +- } +- if (ustatus) { +- nv_error(priv, "TRAP_PROP - TP %d -", tp); +- nouveau_bitfield_print(nv50_graph_trap_prop, ustatus); +- pr_cont(" - Address %02x%08x\n", e14, e10); +- } +- nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n", +- tp, e0c, e18, e1c, e20, e24); +-} +- +-static void +-nv50_priv_mp_trap(struct nv50_graph_priv *priv, int tpid, int display) +-{ +- u32 units = nv_rd32(priv, 0x1540); +- u32 addr, mp10, status, pc, oplow, ophigh; +- int i; +- int mps = 0; +- for (i = 0; i < 4; i++) { +- if (!(units & 1 << (i+24))) +- continue; +- if (nv_device(priv)->chipset < 0xa0) +- addr = 0x408200 + (tpid << 12) + (i << 7); +- else +- addr = 0x408100 + (tpid << 11) + (i << 7); +- mp10 = nv_rd32(priv, addr + 0x10); +- status = nv_rd32(priv, addr + 0x14); +- if (!status) +- continue; +- if (display) { +- nv_rd32(priv, addr + 0x20); +- pc = nv_rd32(priv, addr + 0x24); +- oplow = nv_rd32(priv, addr + 0x70); +- ophigh = nv_rd32(priv, addr + 0x74); +- nv_error(priv, "TRAP_MP_EXEC - " +- "TP %d MP %d:", tpid, i); +- nouveau_bitfield_print(nv50_mp_exec_errors, status); +- pr_cont(" at %06x warp %d, opcode %08x %08x\n", +- pc&0xffffff, pc >> 24, +- oplow, ophigh); +- } +- nv_wr32(priv, addr + 0x10, mp10); +- nv_wr32(priv, addr + 0x14, 0); +- mps++; +- } +- if (!mps && display) +- nv_error(priv, "TRAP_MP_EXEC - TP %d: " +- "No MPs claiming errors?\n", tpid); +-} +- +-static void +-nv50_priv_tp_trap(struct nv50_graph_priv *priv, int type, u32 ustatus_old, +- u32 ustatus_new, int display, const char *name) +-{ +- int tps = 0; +- u32 units = nv_rd32(priv, 0x1540); +- int i, r; +- u32 ustatus_addr, ustatus; +- for (i = 0; i < 16; i++) { +- if (!(units & (1 << i))) +- continue; +- if (nv_device(priv)->chipset < 0xa0) +- ustatus_addr = ustatus_old + (i << 12); +- else +- ustatus_addr = ustatus_new + (i << 11); +- ustatus = nv_rd32(priv, ustatus_addr) & 0x7fffffff; +- if (!ustatus) +- continue; +- tps++; +- switch (type) { +- case 6: /* texture error... unknown for now */ +- if (display) { +- nv_error(priv, "magic set %d:\n", i); +- for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4) +- nv_error(priv, "\t0x%08x: 0x%08x\n", r, +- nv_rd32(priv, r)); +- if (ustatus) { +- nv_error(priv, "%s - TP%d:", name, i); +- nouveau_bitfield_print(nv50_tex_traps, +- ustatus); +- pr_cont("\n"); +- ustatus = 0; +- } +- } +- break; +- case 7: /* MP error */ +- if (ustatus & 0x04030000) { +- nv50_priv_mp_trap(priv, i, display); +- ustatus &= ~0x04030000; +- } +- if (ustatus && display) { +- nv_error(priv, "%s - TP%d:", name, i); +- nouveau_bitfield_print(nv50_mpc_traps, ustatus); +- pr_cont("\n"); +- ustatus = 0; +- } +- break; +- case 8: /* PROP error */ +- if (display) +- nv50_priv_prop_trap( +- priv, ustatus_addr, ustatus, i); +- ustatus = 0; +- break; +- } +- if (ustatus) { +- if (display) +- nv_error(priv, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus); +- } +- nv_wr32(priv, ustatus_addr, 0xc0000000); +- } +- +- if (!tps && display) +- nv_warn(priv, "%s - No TPs claiming errors?\n", name); +-} +- +-static int +-nv50_graph_trap_handler(struct nv50_graph_priv *priv, u32 display, +- int chid, u64 inst, struct nouveau_object *engctx) +-{ +- u32 status = nv_rd32(priv, 0x400108); +- u32 ustatus; +- +- if (!status && display) { +- nv_error(priv, "TRAP: no units reporting traps?\n"); +- return 1; +- } +- +- /* DISPATCH: Relays commands to other units and handles NOTIFY, +- * COND, QUERY. If you get a trap from it, the command is still stuck +- * in DISPATCH and you need to do something about it. */ +- if (status & 0x001) { +- ustatus = nv_rd32(priv, 0x400804) & 0x7fffffff; +- if (!ustatus && display) { +- nv_error(priv, "TRAP_DISPATCH - no ustatus?\n"); +- } +- +- nv_wr32(priv, 0x400500, 0x00000000); +- +- /* Known to be triggered by screwed up NOTIFY and COND... */ +- if (ustatus & 0x00000001) { +- u32 addr = nv_rd32(priv, 0x400808); +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00001ffc); +- u32 datal = nv_rd32(priv, 0x40080c); +- u32 datah = nv_rd32(priv, 0x400810); +- u32 class = nv_rd32(priv, 0x400814); +- u32 r848 = nv_rd32(priv, 0x400848); +- +- nv_error(priv, "TRAP DISPATCH_FAULT\n"); +- if (display && (addr & 0x80000000)) { +- nv_error(priv, +- "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n", +- chid, inst, +- nouveau_client_name(engctx), subc, +- class, mthd, datah, datal, addr, r848); +- } else +- if (display) { +- nv_error(priv, "no stuck command?\n"); +- } +- +- nv_wr32(priv, 0x400808, 0); +- nv_wr32(priv, 0x4008e8, nv_rd32(priv, 0x4008e8) & 3); +- nv_wr32(priv, 0x400848, 0); +- ustatus &= ~0x00000001; +- } +- +- if (ustatus & 0x00000002) { +- u32 addr = nv_rd32(priv, 0x40084c); +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00001ffc); +- u32 data = nv_rd32(priv, 0x40085c); +- u32 class = nv_rd32(priv, 0x400814); +- +- nv_error(priv, "TRAP DISPATCH_QUERY\n"); +- if (display && (addr & 0x80000000)) { +- nv_error(priv, +- "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n", +- chid, inst, +- nouveau_client_name(engctx), subc, +- class, mthd, data, addr); +- } else +- if (display) { +- nv_error(priv, "no stuck command?\n"); +- } +- +- nv_wr32(priv, 0x40084c, 0); +- ustatus &= ~0x00000002; +- } +- +- if (ustatus && display) { +- nv_error(priv, "TRAP_DISPATCH (unknown " +- "0x%08x)\n", ustatus); +- } +- +- nv_wr32(priv, 0x400804, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x001); +- status &= ~0x001; +- if (!status) +- return 0; +- } +- +- /* M2MF: Memory to memory copy engine. */ +- if (status & 0x002) { +- u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff; +- if (display) { +- nv_error(priv, "TRAP_M2MF"); +- nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus); +- pr_cont("\n"); +- nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n", +- nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808), +- nv_rd32(priv, 0x40680c), nv_rd32(priv, 0x406810)); +- +- } +- +- /* No sane way found yet -- just reset the bugger. */ +- nv_wr32(priv, 0x400040, 2); +- nv_wr32(priv, 0x400040, 0); +- nv_wr32(priv, 0x406800, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x002); +- status &= ~0x002; +- } +- +- /* VFETCH: Fetches data from vertex buffers. */ +- if (status & 0x004) { +- u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff; +- if (display) { +- nv_error(priv, "TRAP_VFETCH"); +- nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus); +- pr_cont("\n"); +- nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n", +- nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08), +- nv_rd32(priv, 0x400c0c), nv_rd32(priv, 0x400c10)); +- } +- +- nv_wr32(priv, 0x400c04, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x004); +- status &= ~0x004; +- } +- +- /* STRMOUT: DirectX streamout / OpenGL transform feedback. */ +- if (status & 0x008) { +- ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff; +- if (display) { +- nv_error(priv, "TRAP_STRMOUT"); +- nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus); +- pr_cont("\n"); +- nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n", +- nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808), +- nv_rd32(priv, 0x40180c), nv_rd32(priv, 0x401810)); +- +- } +- +- /* No sane way found yet -- just reset the bugger. */ +- nv_wr32(priv, 0x400040, 0x80); +- nv_wr32(priv, 0x400040, 0); +- nv_wr32(priv, 0x401800, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x008); +- status &= ~0x008; +- } +- +- /* CCACHE: Handles code and c[] caches and fills them. */ +- if (status & 0x010) { +- ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff; +- if (display) { +- nv_error(priv, "TRAP_CCACHE"); +- nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus); +- pr_cont("\n"); +- nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x" +- " %08x %08x %08x\n", +- nv_rd32(priv, 0x405000), nv_rd32(priv, 0x405004), +- nv_rd32(priv, 0x405008), nv_rd32(priv, 0x40500c), +- nv_rd32(priv, 0x405010), nv_rd32(priv, 0x405014), +- nv_rd32(priv, 0x40501c)); +- +- } +- +- nv_wr32(priv, 0x405018, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x010); +- status &= ~0x010; +- } +- +- /* Unknown, not seen yet... 0x402000 is the only trap status reg +- * remaining, so try to handle it anyway. Perhaps related to that +- * unknown DMA slot on tesla? */ +- if (status & 0x20) { +- ustatus = nv_rd32(priv, 0x402000) & 0x7fffffff; +- if (display) +- nv_error(priv, "TRAP_UNKC04 0x%08x\n", ustatus); +- nv_wr32(priv, 0x402000, 0xc0000000); +- /* no status modifiction on purpose */ +- } +- +- /* TEXTURE: CUDA texturing units */ +- if (status & 0x040) { +- nv50_priv_tp_trap(priv, 6, 0x408900, 0x408600, display, +- "TRAP_TEXTURE"); +- nv_wr32(priv, 0x400108, 0x040); +- status &= ~0x040; +- } +- +- /* MP: CUDA execution engines. */ +- if (status & 0x080) { +- nv50_priv_tp_trap(priv, 7, 0x408314, 0x40831c, display, +- "TRAP_MP"); +- nv_wr32(priv, 0x400108, 0x080); +- status &= ~0x080; +- } +- +- /* PROP: Handles TP-initiated uncached memory accesses: +- * l[], g[], stack, 2d surfaces, render targets. */ +- if (status & 0x100) { +- nv50_priv_tp_trap(priv, 8, 0x408e08, 0x408708, display, +- "TRAP_PROP"); +- nv_wr32(priv, 0x400108, 0x100); +- status &= ~0x100; +- } +- +- if (status) { +- if (display) +- nv_error(priv, "TRAP: unknown 0x%08x\n", status); +- nv_wr32(priv, 0x400108, status); +- } +- +- return 1; +-} +- +-static void +-nv50_graph_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nouveau_handle *handle = NULL; +- struct nv50_graph_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, 0x400100); +- u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff; +- u32 addr = nv_rd32(priv, 0x400704); +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00001ffc); +- u32 data = nv_rd32(priv, 0x400708); +- u32 class = nv_rd32(priv, 0x400814); +- u32 show = stat, show_bitfield = stat; +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat & 0x00000010) { +- handle = nouveau_handle_get_class(engctx, class); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~0x00000010; +- nouveau_handle_put(handle); +- } +- +- if (show & 0x00100000) { +- u32 ecode = nv_rd32(priv, 0x400110); +- nv_error(priv, "DATA_ERROR "); +- nouveau_enum_print(nv50_data_error_names, ecode); +- pr_cont("\n"); +- show_bitfield &= ~0x00100000; +- } +- +- if (stat & 0x00200000) { +- if (!nv50_graph_trap_handler(priv, show, chid, (u64)inst << 12, +- engctx)) +- show &= ~0x00200000; +- show_bitfield &= ~0x00200000; +- } +- +- nv_wr32(priv, 0x400100, stat); +- nv_wr32(priv, 0x400500, 0x00010001); +- +- if (show) { +- show &= show_bitfield; +- if (show) { +- nv_error(priv, "%s", ""); +- nouveau_bitfield_print(nv50_graph_intr_name, show); +- pr_cont("\n"); +- } +- nv_error(priv, +- "ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, (u64)inst << 12, nouveau_client_name(engctx), +- subc, class, mthd, data); +- } +- +- if (nv_rd32(priv, 0x400824) & (1 << 31)) +- nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31)); +- +- nouveau_engctx_put(engctx); +-} +- +-static int +-nv50_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_graph_priv *priv; +- int ret; +- +- ret = nouveau_graph_create(parent, engine, oclass, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00201000; +- nv_subdev(priv)->intr = nv50_graph_intr; +- nv_engine(priv)->cclass = &nv50_graph_cclass; +- +- priv->base.units = nv50_graph_units; +- +- switch (nv_device(priv)->chipset) { +- case 0x50: +- nv_engine(priv)->sclass = nv50_graph_sclass; +- break; +- case 0x84: +- case 0x86: +- case 0x92: +- case 0x94: +- case 0x96: +- case 0x98: +- nv_engine(priv)->sclass = nv84_graph_sclass; +- break; +- case 0xa0: +- case 0xaa: +- case 0xac: +- nv_engine(priv)->sclass = nva0_graph_sclass; +- break; +- case 0xa3: +- case 0xa5: +- case 0xa8: +- nv_engine(priv)->sclass = nva3_graph_sclass; +- break; +- case 0xaf: +- nv_engine(priv)->sclass = nvaf_graph_sclass; +- break; +- +- } +- +- /* unfortunate hw bug workaround... */ +- if (nv_device(priv)->chipset != 0x50 && +- nv_device(priv)->chipset != 0xac) +- nv_engine(priv)->tlb_flush = nv84_graph_tlb_flush; +- +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-static int +-nv50_graph_init(struct nouveau_object *object) +-{ +- struct nv50_graph_priv *priv = (void *)object; +- int ret, units, i; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- /* NV_PGRAPH_DEBUG_3_HW_CTX_SWITCH_ENABLED */ +- nv_wr32(priv, 0x40008c, 0x00000004); +- +- /* reset/enable traps and interrupts */ +- nv_wr32(priv, 0x400804, 0xc0000000); +- nv_wr32(priv, 0x406800, 0xc0000000); +- nv_wr32(priv, 0x400c04, 0xc0000000); +- nv_wr32(priv, 0x401800, 0xc0000000); +- nv_wr32(priv, 0x405018, 0xc0000000); +- nv_wr32(priv, 0x402000, 0xc0000000); +- +- units = nv_rd32(priv, 0x001540); +- for (i = 0; i < 16; i++) { +- if (!(units & (1 << i))) +- continue; +- +- if (nv_device(priv)->chipset < 0xa0) { +- nv_wr32(priv, 0x408900 + (i << 12), 0xc0000000); +- nv_wr32(priv, 0x408e08 + (i << 12), 0xc0000000); +- nv_wr32(priv, 0x408314 + (i << 12), 0xc0000000); +- } else { +- nv_wr32(priv, 0x408600 + (i << 11), 0xc0000000); +- nv_wr32(priv, 0x408708 + (i << 11), 0xc0000000); +- nv_wr32(priv, 0x40831c + (i << 11), 0xc0000000); +- } +- } +- +- nv_wr32(priv, 0x400108, 0xffffffff); +- nv_wr32(priv, 0x400138, 0xffffffff); +- nv_wr32(priv, 0x400100, 0xffffffff); +- nv_wr32(priv, 0x40013c, 0xffffffff); +- nv_wr32(priv, 0x400500, 0x00010001); +- +- /* upload context program, initialise ctxctl defaults */ +- ret = nv50_grctx_init(nv_device(priv), &priv->size); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x400824, 0x00000000); +- nv_wr32(priv, 0x400828, 0x00000000); +- nv_wr32(priv, 0x40082c, 0x00000000); +- nv_wr32(priv, 0x400830, 0x00000000); +- nv_wr32(priv, 0x40032c, 0x00000000); +- nv_wr32(priv, 0x400330, 0x00000000); +- +- /* some unknown zcull magic */ +- switch (nv_device(priv)->chipset & 0xf0) { +- case 0x50: +- case 0x80: +- case 0x90: +- nv_wr32(priv, 0x402ca8, 0x00000800); +- break; +- case 0xa0: +- default: +- if (nv_device(priv)->chipset == 0xa0 || +- nv_device(priv)->chipset == 0xaa || +- nv_device(priv)->chipset == 0xac) { +- nv_wr32(priv, 0x402ca8, 0x00000802); +- } else { +- nv_wr32(priv, 0x402cc0, 0x00000000); +- nv_wr32(priv, 0x402ca8, 0x00000002); +- } +- +- break; +- } +- +- /* zero out zcull regions */ +- for (i = 0; i < 8; i++) { +- nv_wr32(priv, 0x402c20 + (i * 0x10), 0x00000000); +- nv_wr32(priv, 0x402c24 + (i * 0x10), 0x00000000); +- nv_wr32(priv, 0x402c28 + (i * 0x10), 0x00000000); +- nv_wr32(priv, 0x402c2c + (i * 0x10), 0x00000000); +- } +- return 0; +-} +- +-struct nouveau_oclass +-nv50_graph_oclass = { +- .handle = NV_ENGINE(GR, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_graph_ctor, +- .dtor = _nouveau_graph_dtor, +- .init = nv50_graph_init, +- .fini = _nouveau_graph_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h b/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h +deleted file mode 100644 +index 0505fb41..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nv50.h ++++ /dev/null +@@ -1,7 +0,0 @@ +-#ifndef __NV50_GRAPH_H__ +-#define __NV50_GRAPH_H__ +- +-int nv50_grctx_init(struct nouveau_device *, u32 *size); +-void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +deleted file mode 100644 +index 30fd1dc6..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c ++++ /dev/null +@@ -1,1667 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Zero Bandwidth Clear +- ******************************************************************************/ +- +-static void +-nvc0_graph_zbc_clear_color(struct nvc0_graph_priv *priv, int zbc) +-{ +- if (priv->zbc_color[zbc].format) { +- nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]); +- nv_wr32(priv, 0x405808, priv->zbc_color[zbc].ds[1]); +- nv_wr32(priv, 0x40580c, priv->zbc_color[zbc].ds[2]); +- nv_wr32(priv, 0x405810, priv->zbc_color[zbc].ds[3]); +- } +- nv_wr32(priv, 0x405814, priv->zbc_color[zbc].format); +- nv_wr32(priv, 0x405820, zbc); +- nv_wr32(priv, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ +-} +- +-static int +-nvc0_graph_zbc_color_get(struct nvc0_graph_priv *priv, int format, +- const u32 ds[4], const u32 l2[4]) +-{ +- struct nouveau_ltc *ltc = nouveau_ltc(priv); +- int zbc = -ENOSPC, i; +- +- for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { +- if (priv->zbc_color[i].format) { +- if (priv->zbc_color[i].format != format) +- continue; +- if (memcmp(priv->zbc_color[i].ds, ds, sizeof( +- priv->zbc_color[i].ds))) +- continue; +- if (memcmp(priv->zbc_color[i].l2, l2, sizeof( +- priv->zbc_color[i].l2))) { +- WARN_ON(1); +- return -EINVAL; +- } +- return i; +- } else { +- zbc = (zbc < 0) ? i : zbc; +- } +- } +- +- if (zbc < 0) +- return zbc; +- +- memcpy(priv->zbc_color[zbc].ds, ds, sizeof(priv->zbc_color[zbc].ds)); +- memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2)); +- priv->zbc_color[zbc].format = format; +- ltc->zbc_color_get(ltc, zbc, l2); +- nvc0_graph_zbc_clear_color(priv, zbc); +- return zbc; +-} +- +-static void +-nvc0_graph_zbc_clear_depth(struct nvc0_graph_priv *priv, int zbc) +-{ +- if (priv->zbc_depth[zbc].format) +- nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds); +- nv_wr32(priv, 0x40581c, priv->zbc_depth[zbc].format); +- nv_wr32(priv, 0x405820, zbc); +- nv_wr32(priv, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */ +-} +- +-static int +-nvc0_graph_zbc_depth_get(struct nvc0_graph_priv *priv, int format, +- const u32 ds, const u32 l2) +-{ +- struct nouveau_ltc *ltc = nouveau_ltc(priv); +- int zbc = -ENOSPC, i; +- +- for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) { +- if (priv->zbc_depth[i].format) { +- if (priv->zbc_depth[i].format != format) +- continue; +- if (priv->zbc_depth[i].ds != ds) +- continue; +- if (priv->zbc_depth[i].l2 != l2) { +- WARN_ON(1); +- return -EINVAL; +- } +- return i; +- } else { +- zbc = (zbc < 0) ? i : zbc; +- } +- } +- +- if (zbc < 0) +- return zbc; +- +- priv->zbc_depth[zbc].format = format; +- priv->zbc_depth[zbc].ds = ds; +- priv->zbc_depth[zbc].l2 = l2; +- ltc->zbc_depth_get(ltc, zbc, l2); +- nvc0_graph_zbc_clear_depth(priv, zbc); +- return zbc; +-} +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static int +-nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size) +-{ +- struct nvc0_graph_priv *priv = (void *)object->engine; +- union { +- struct fermi_a_zbc_color_v0 v0; +- } *args = data; +- int ret; +- +- if (nvif_unpack(args->v0, 0, 0, false)) { +- switch (args->v0.format) { +- case FERMI_A_ZBC_COLOR_V0_FMT_ZERO: +- case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE: +- case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32: +- case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16: +- case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16: +- case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16: +- case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16: +- case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16: +- case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8: +- case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8: +- case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10: +- case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10: +- case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8: +- case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8: +- case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8: +- case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8: +- case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8: +- case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10: +- case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11: +- ret = nvc0_graph_zbc_color_get(priv, args->v0.format, +- args->v0.ds, +- args->v0.l2); +- if (ret >= 0) { +- args->v0.index = ret; +- return 0; +- } +- break; +- default: +- return -EINVAL; +- } +- } +- +- return ret; +-} +- +-static int +-nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size) +-{ +- struct nvc0_graph_priv *priv = (void *)object->engine; +- union { +- struct fermi_a_zbc_depth_v0 v0; +- } *args = data; +- int ret; +- +- if (nvif_unpack(args->v0, 0, 0, false)) { +- switch (args->v0.format) { +- case FERMI_A_ZBC_DEPTH_V0_FMT_FP32: +- ret = nvc0_graph_zbc_depth_get(priv, args->v0.format, +- args->v0.ds, +- args->v0.l2); +- return (ret >= 0) ? 0 : -ENOSPC; +- default: +- return -EINVAL; +- } +- } +- +- return ret; +-} +- +-static int +-nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size) +-{ +- switch (mthd) { +- case FERMI_A_ZBC_COLOR: +- return nvc0_fermi_mthd_zbc_color(object, data, size); +- case FERMI_A_ZBC_DEPTH: +- return nvc0_fermi_mthd_zbc_depth(object, data, size); +- default: +- break; +- } +- return -EINVAL; +-} +- +-struct nouveau_ofuncs +-nvc0_fermi_ofuncs = { +- .ctor = _nouveau_object_ctor, +- .dtor = nouveau_object_destroy, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- .mthd = nvc0_fermi_mthd, +-}; +- +-static int +-nvc0_graph_set_shader_exceptions(struct nouveau_object *object, u32 mthd, +- void *pdata, u32 size) +-{ +- struct nvc0_graph_priv *priv = (void *)nv_engine(object); +- if (size >= sizeof(u32)) { +- u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000; +- nv_wr32(priv, 0x419e44, data); +- nv_wr32(priv, 0x419e4c, data); +- return 0; +- } +- return -EINVAL; +-} +- +-struct nouveau_omthds +-nvc0_graph_9097_omthds[] = { +- { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions }, +- {} +-}; +- +-struct nouveau_omthds +-nvc0_graph_90c0_omthds[] = { +- { 0x1528, 0x1528, nvc0_graph_set_shader_exceptions }, +- {} +-}; +- +-struct nouveau_oclass +-nvc0_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0x9039, &nouveau_object_ofuncs }, +- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH context +- ******************************************************************************/ +- +-int +-nvc0_graph_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *args, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_vm *vm = nouveau_client(parent)->vm; +- struct nvc0_graph_priv *priv = (void *)engine; +- struct nvc0_graph_data *data = priv->mmio_data; +- struct nvc0_graph_mmio *mmio = priv->mmio_list; +- struct nvc0_graph_chan *chan; +- int ret, i; +- +- /* allocate memory for context, and fill with default values */ +- ret = nouveau_graph_context_create(parent, engine, oclass, NULL, +- priv->size, 0x100, +- NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- /* allocate memory for a "mmio list" buffer that's used by the HUB +- * fuc to modify some per-context register settings on first load +- * of the context. +- */ +- ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0, +- &chan->mmio); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm, +- NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS, +- &chan->mmio_vma); +- if (ret) +- return ret; +- +- /* allocate buffers referenced by mmio list */ +- for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) { +- ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size, +- data->align, 0, &chan->data[i].mem); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access, +- &chan->data[i].vma); +- if (ret) +- return ret; +- +- data++; +- } +- +- /* finally, fill in the mmio list and point the context at it */ +- for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) { +- u32 addr = mmio->addr; +- u32 data = mmio->data; +- +- if (mmio->buffer >= 0) { +- u64 info = chan->data[mmio->buffer].vma.offset; +- data |= info >> mmio->shift; +- } +- +- nv_wo32(chan->mmio, chan->mmio_nr++ * 4, addr); +- nv_wo32(chan->mmio, chan->mmio_nr++ * 4, data); +- mmio++; +- } +- +- for (i = 0; i < priv->size; i += 4) +- nv_wo32(chan, i, priv->data[i / 4]); +- +- if (!priv->firmware) { +- nv_wo32(chan, 0x00, chan->mmio_nr / 2); +- nv_wo32(chan, 0x04, chan->mmio_vma.offset >> 8); +- } else { +- nv_wo32(chan, 0xf4, 0); +- nv_wo32(chan, 0xf8, 0); +- nv_wo32(chan, 0x10, chan->mmio_nr / 2); +- nv_wo32(chan, 0x14, lower_32_bits(chan->mmio_vma.offset)); +- nv_wo32(chan, 0x18, upper_32_bits(chan->mmio_vma.offset)); +- nv_wo32(chan, 0x1c, 1); +- nv_wo32(chan, 0x20, 0); +- nv_wo32(chan, 0x28, 0); +- nv_wo32(chan, 0x2c, 0); +- } +- +- return 0; +-} +- +-void +-nvc0_graph_context_dtor(struct nouveau_object *object) +-{ +- struct nvc0_graph_chan *chan = (void *)object; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(chan->data); i++) { +- nouveau_gpuobj_unmap(&chan->data[i].vma); +- nouveau_gpuobj_ref(NULL, &chan->data[i].mem); +- } +- +- nouveau_gpuobj_unmap(&chan->mmio_vma); +- nouveau_gpuobj_ref(NULL, &chan->mmio); +- +- nouveau_graph_context_destroy(&chan->base); +-} +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nvc0_graph_init_main_0[] = { +- { 0x400080, 1, 0x04, 0x003083c2 }, +- { 0x400088, 1, 0x04, 0x00006fe7 }, +- { 0x40008c, 1, 0x04, 0x00000000 }, +- { 0x400090, 1, 0x04, 0x00000030 }, +- { 0x40013c, 1, 0x04, 0x013901f7 }, +- { 0x400140, 1, 0x04, 0x00000100 }, +- { 0x400144, 1, 0x04, 0x00000000 }, +- { 0x400148, 1, 0x04, 0x00000110 }, +- { 0x400138, 1, 0x04, 0x00000000 }, +- { 0x400130, 2, 0x04, 0x00000000 }, +- { 0x400124, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_fe_0[] = { +- { 0x40415c, 1, 0x04, 0x00000000 }, +- { 0x404170, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_pri_0[] = { +- { 0x404488, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_rstr2d_0[] = { +- { 0x407808, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_pd_0[] = { +- { 0x406024, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_scc_0[] = { +- { 0x40803c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_prop_0[] = { +- { 0x4184a0, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_gpc_unk_0[] = { +- { 0x418604, 1, 0x04, 0x00000000 }, +- { 0x418680, 1, 0x04, 0x00000000 }, +- { 0x418714, 1, 0x04, 0x80000000 }, +- { 0x418384, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_setup_0[] = { +- { 0x418814, 3, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_crstr_0[] = { +- { 0x418b04, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_setup_1[] = { +- { 0x4188c8, 1, 0x04, 0x80000000 }, +- { 0x4188cc, 1, 0x04, 0x00000000 }, +- { 0x4188d0, 1, 0x04, 0x00010000 }, +- { 0x4188d4, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_zcull_0[] = { +- { 0x418910, 1, 0x04, 0x00010001 }, +- { 0x418914, 1, 0x04, 0x00000301 }, +- { 0x418918, 1, 0x04, 0x00800000 }, +- { 0x418980, 1, 0x04, 0x77777770 }, +- { 0x418984, 3, 0x04, 0x77777777 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_gpm_0[] = { +- { 0x418c04, 1, 0x04, 0x00000000 }, +- { 0x418c88, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_gpc_unk_1[] = { +- { 0x418d00, 1, 0x04, 0x00000000 }, +- { 0x418f08, 1, 0x04, 0x00000000 }, +- { 0x418e00, 1, 0x04, 0x00000050 }, +- { 0x418e08, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_gcc_0[] = { +- { 0x41900c, 1, 0x04, 0x00000000 }, +- { 0x419018, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_tpccs_0[] = { +- { 0x419d08, 2, 0x04, 0x00000000 }, +- { 0x419d10, 1, 0x04, 0x00000014 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_tex_0[] = { +- { 0x419ab0, 1, 0x04, 0x00000000 }, +- { 0x419ab8, 1, 0x04, 0x000000e7 }, +- { 0x419abc, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_pe_0[] = { +- { 0x41980c, 3, 0x04, 0x00000000 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x41984c, 1, 0x04, 0x00005bc5 }, +- { 0x419850, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_l1c_0[] = { +- { 0x419c98, 1, 0x04, 0x00000000 }, +- { 0x419ca8, 1, 0x04, 0x80000000 }, +- { 0x419cb4, 1, 0x04, 0x00000000 }, +- { 0x419cb8, 1, 0x04, 0x00008bf4 }, +- { 0x419cbc, 1, 0x04, 0x28137606 }, +- { 0x419cc0, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_wwdx_0[] = { +- { 0x419bd4, 1, 0x04, 0x00800000 }, +- { 0x419bdc, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_tpccs_1[] = { +- { 0x419d2c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_mpc_0[] = { +- { 0x419c0c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc0_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000000 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x00001100 }, +- { 0x419eac, 1, 0x04, 0x11100702 }, +- { 0x419eb0, 1, 0x04, 0x00000003 }, +- { 0x419eb4, 4, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x06060618 }, +- { 0x419ed0, 1, 0x04, 0x0eff0e38 }, +- { 0x419ed4, 1, 0x04, 0x011104f1 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419f2c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_be_0[] = { +- { 0x40880c, 1, 0x04, 0x00000000 }, +- { 0x408910, 9, 0x04, 0x00000000 }, +- { 0x408950, 1, 0x04, 0x00000000 }, +- { 0x408954, 1, 0x04, 0x0000ffff }, +- { 0x408984, 1, 0x04, 0x00000000 }, +- { 0x408988, 1, 0x04, 0x08040201 }, +- { 0x40898c, 1, 0x04, 0x80402010 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_fe_1[] = { +- { 0x4040f0, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc0_graph_init_pe_1[] = { +- { 0x419880, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc0_graph_pack_mmio[] = { +- { nvc0_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvc0_graph_init_pd_0 }, +- { nvc0_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvc0_graph_init_prop_0 }, +- { nvc0_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc0_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvc0_graph_init_gpm_0 }, +- { nvc0_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nvc0_graph_init_tpccs_0 }, +- { nvc0_graph_init_tex_0 }, +- { nvc0_graph_init_pe_0 }, +- { nvc0_graph_init_l1c_0 }, +- { nvc0_graph_init_wwdx_0 }, +- { nvc0_graph_init_tpccs_1 }, +- { nvc0_graph_init_mpc_0 }, +- { nvc0_graph_init_sm_0 }, +- { nvc0_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- { nvc0_graph_init_pe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-void +-nvc0_graph_zbc_init(struct nvc0_graph_priv *priv) +-{ +- const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; +- const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, +- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff }; +- const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, +- 0x00000000, 0x00000000, 0x00000000, 0x00000000 }; +- const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, +- 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 }; +- struct nouveau_ltc *ltc = nouveau_ltc(priv); +- int index; +- +- if (!priv->zbc_color[0].format) { +- nvc0_graph_zbc_color_get(priv, 1, & zero[0], &zero[4]); +- nvc0_graph_zbc_color_get(priv, 2, & one[0], &one[4]); +- nvc0_graph_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]); +- nvc0_graph_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]); +- nvc0_graph_zbc_depth_get(priv, 1, 0x00000000, 0x00000000); +- nvc0_graph_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000); +- } +- +- for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) +- nvc0_graph_zbc_clear_color(priv, index); +- for (index = ltc->zbc_min; index <= ltc->zbc_max; index++) +- nvc0_graph_zbc_clear_depth(priv, index); +-} +- +-void +-nvc0_graph_mmio(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) +-{ +- const struct nvc0_graph_pack *pack; +- const struct nvc0_graph_init *init; +- +- pack_for_each_init(init, pack, p) { +- u32 next = init->addr + init->count * init->pitch; +- u32 addr = init->addr; +- while (addr < next) { +- nv_wr32(priv, addr, init->data); +- addr += init->pitch; +- } +- } +-} +- +-void +-nvc0_graph_icmd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) +-{ +- const struct nvc0_graph_pack *pack; +- const struct nvc0_graph_init *init; +- u32 data = 0; +- +- nv_wr32(priv, 0x400208, 0x80000000); +- +- pack_for_each_init(init, pack, p) { +- u32 next = init->addr + init->count * init->pitch; +- u32 addr = init->addr; +- +- if ((pack == p && init == p->init) || data != init->data) { +- nv_wr32(priv, 0x400204, init->data); +- data = init->data; +- } +- +- while (addr < next) { +- nv_wr32(priv, 0x400200, addr); +- nv_wait(priv, 0x400700, 0x00000002, 0x00000000); +- addr += init->pitch; +- } +- } +- +- nv_wr32(priv, 0x400208, 0x00000000); +-} +- +-void +-nvc0_graph_mthd(struct nvc0_graph_priv *priv, const struct nvc0_graph_pack *p) +-{ +- const struct nvc0_graph_pack *pack; +- const struct nvc0_graph_init *init; +- u32 data = 0; +- +- pack_for_each_init(init, pack, p) { +- u32 ctrl = 0x80000000 | pack->type; +- u32 next = init->addr + init->count * init->pitch; +- u32 addr = init->addr; +- +- if ((pack == p && init == p->init) || data != init->data) { +- nv_wr32(priv, 0x40448c, init->data); +- data = init->data; +- } +- +- while (addr < next) { +- nv_wr32(priv, 0x404488, ctrl | (addr << 14)); +- addr += init->pitch; +- } +- } +-} +- +-u64 +-nvc0_graph_units(struct nouveau_graph *graph) +-{ +- struct nvc0_graph_priv *priv = (void *)graph; +- u64 cfg; +- +- cfg = (u32)priv->gpc_nr; +- cfg |= (u32)priv->tpc_total << 8; +- cfg |= (u64)priv->rop_nr << 32; +- +- return cfg; +-} +- +-static const struct nouveau_enum nve0_sked_error[] = { +- { 7, "CONSTANT_BUFFER_SIZE" }, +- { 9, "LOCAL_MEMORY_SIZE_POS" }, +- { 10, "LOCAL_MEMORY_SIZE_NEG" }, +- { 11, "WARP_CSTACK_SIZE" }, +- { 12, "TOTAL_TEMP_SIZE" }, +- { 13, "REGISTER_COUNT" }, +- { 18, "TOTAL_THREADS" }, +- { 20, "PROGRAM_OFFSET" }, +- { 21, "SHARED_MEMORY_SIZE" }, +- { 25, "SHARED_CONFIG_TOO_SMALL" }, +- { 26, "TOTAL_REGISTER_COUNT" }, +- {} +-}; +- +-static const struct nouveau_enum nvc0_gpc_rop_error[] = { +- { 1, "RT_PITCH_OVERRUN" }, +- { 4, "RT_WIDTH_OVERRUN" }, +- { 5, "RT_HEIGHT_OVERRUN" }, +- { 7, "ZETA_STORAGE_TYPE_MISMATCH" }, +- { 8, "RT_STORAGE_TYPE_MISMATCH" }, +- { 10, "RT_LINEAR_MISMATCH" }, +- {} +-}; +- +-static void +-nvc0_graph_trap_gpc_rop(struct nvc0_graph_priv *priv, int gpc) +-{ +- u32 trap[4]; +- int i; +- +- trap[0] = nv_rd32(priv, GPC_UNIT(gpc, 0x0420)); +- trap[1] = nv_rd32(priv, GPC_UNIT(gpc, 0x0434)); +- trap[2] = nv_rd32(priv, GPC_UNIT(gpc, 0x0438)); +- trap[3] = nv_rd32(priv, GPC_UNIT(gpc, 0x043c)); +- +- nv_error(priv, "GPC%d/PROP trap:", gpc); +- for (i = 0; i <= 29; ++i) { +- if (!(trap[0] & (1 << i))) +- continue; +- pr_cont(" "); +- nouveau_enum_print(nvc0_gpc_rop_error, i); +- } +- pr_cont("\n"); +- +- nv_error(priv, "x = %u, y = %u, format = %x, storage type = %x\n", +- trap[1] & 0xffff, trap[1] >> 16, (trap[2] >> 8) & 0x3f, +- trap[3] & 0xff); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); +-} +- +-static const struct nouveau_enum nvc0_mp_warp_error[] = { +- { 0x00, "NO_ERROR" }, +- { 0x01, "STACK_MISMATCH" }, +- { 0x05, "MISALIGNED_PC" }, +- { 0x08, "MISALIGNED_GPR" }, +- { 0x09, "INVALID_OPCODE" }, +- { 0x0d, "GPR_OUT_OF_BOUNDS" }, +- { 0x0e, "MEM_OUT_OF_BOUNDS" }, +- { 0x0f, "UNALIGNED_MEM_ACCESS" }, +- { 0x11, "INVALID_PARAM" }, +- {} +-}; +- +-static const struct nouveau_bitfield nvc0_mp_global_error[] = { +- { 0x00000004, "MULTIPLE_WARP_ERRORS" }, +- { 0x00000008, "OUT_OF_STACK_SPACE" }, +- {} +-}; +- +-static void +-nvc0_graph_trap_mp(struct nvc0_graph_priv *priv, int gpc, int tpc) +-{ +- u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648)); +- u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650)); +- +- nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc); +- nouveau_bitfield_print(nvc0_mp_global_error, gerr); +- if (werr) { +- pr_cont(" "); +- nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff); +- } +- pr_cont("\n"); +- +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x648), 0x00000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x650), gerr); +-} +- +-static void +-nvc0_graph_trap_tpc(struct nvc0_graph_priv *priv, int gpc, int tpc) +-{ +- u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508)); +- +- if (stat & 0x00000001) { +- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0224)); +- nv_error(priv, "GPC%d/TPC%d/TEX: 0x%08x\n", gpc, tpc, trap); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000); +- stat &= ~0x00000001; +- } +- +- if (stat & 0x00000002) { +- nvc0_graph_trap_mp(priv, gpc, tpc); +- stat &= ~0x00000002; +- } +- +- if (stat & 0x00000004) { +- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0084)); +- nv_error(priv, "GPC%d/TPC%d/POLY: 0x%08x\n", gpc, tpc, trap); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000); +- stat &= ~0x00000004; +- } +- +- if (stat & 0x00000008) { +- u32 trap = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x048c)); +- nv_error(priv, "GPC%d/TPC%d/L1C: 0x%08x\n", gpc, tpc, trap); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000); +- stat &= ~0x00000008; +- } +- +- if (stat) { +- nv_error(priv, "GPC%d/TPC%d/0x%08x: unknown\n", gpc, tpc, stat); +- } +-} +- +-static void +-nvc0_graph_trap_gpc(struct nvc0_graph_priv *priv, int gpc) +-{ +- u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90)); +- int tpc; +- +- if (stat & 0x00000001) { +- nvc0_graph_trap_gpc_rop(priv, gpc); +- stat &= ~0x00000001; +- } +- +- if (stat & 0x00000002) { +- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0900)); +- nv_error(priv, "GPC%d/ZCULL: 0x%08x\n", gpc, trap); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); +- stat &= ~0x00000002; +- } +- +- if (stat & 0x00000004) { +- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x1028)); +- nv_error(priv, "GPC%d/CCACHE: 0x%08x\n", gpc, trap); +- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); +- stat &= ~0x00000004; +- } +- +- if (stat & 0x00000008) { +- u32 trap = nv_rd32(priv, GPC_UNIT(gpc, 0x0824)); +- nv_error(priv, "GPC%d/ESETUP: 0x%08x\n", gpc, trap); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); +- stat &= ~0x00000009; +- } +- +- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { +- u32 mask = 0x00010000 << tpc; +- if (stat & mask) { +- nvc0_graph_trap_tpc(priv, gpc, tpc); +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask); +- stat &= ~mask; +- } +- } +- +- if (stat) { +- nv_error(priv, "GPC%d/0x%08x: unknown\n", gpc, stat); +- } +-} +- +-static void +-nvc0_graph_trap_intr(struct nvc0_graph_priv *priv) +-{ +- u32 trap = nv_rd32(priv, 0x400108); +- int rop, gpc, i; +- +- if (trap & 0x00000001) { +- u32 stat = nv_rd32(priv, 0x404000); +- nv_error(priv, "DISPATCH 0x%08x\n", stat); +- nv_wr32(priv, 0x404000, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x00000001); +- trap &= ~0x00000001; +- } +- +- if (trap & 0x00000002) { +- u32 stat = nv_rd32(priv, 0x404600); +- nv_error(priv, "M2MF 0x%08x\n", stat); +- nv_wr32(priv, 0x404600, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x00000002); +- trap &= ~0x00000002; +- } +- +- if (trap & 0x00000008) { +- u32 stat = nv_rd32(priv, 0x408030); +- nv_error(priv, "CCACHE 0x%08x\n", stat); +- nv_wr32(priv, 0x408030, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x00000008); +- trap &= ~0x00000008; +- } +- +- if (trap & 0x00000010) { +- u32 stat = nv_rd32(priv, 0x405840); +- nv_error(priv, "SHADER 0x%08x\n", stat); +- nv_wr32(priv, 0x405840, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x00000010); +- trap &= ~0x00000010; +- } +- +- if (trap & 0x00000040) { +- u32 stat = nv_rd32(priv, 0x40601c); +- nv_error(priv, "UNK6 0x%08x\n", stat); +- nv_wr32(priv, 0x40601c, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x00000040); +- trap &= ~0x00000040; +- } +- +- if (trap & 0x00000080) { +- u32 stat = nv_rd32(priv, 0x404490); +- nv_error(priv, "MACRO 0x%08x\n", stat); +- nv_wr32(priv, 0x404490, 0xc0000000); +- nv_wr32(priv, 0x400108, 0x00000080); +- trap &= ~0x00000080; +- } +- +- if (trap & 0x00000100) { +- u32 stat = nv_rd32(priv, 0x407020); +- +- nv_error(priv, "SKED:"); +- for (i = 0; i <= 29; ++i) { +- if (!(stat & (1 << i))) +- continue; +- pr_cont(" "); +- nouveau_enum_print(nve0_sked_error, i); +- } +- pr_cont("\n"); +- +- if (stat & 0x3fffffff) +- nv_wr32(priv, 0x407020, 0x40000000); +- nv_wr32(priv, 0x400108, 0x00000100); +- trap &= ~0x00000100; +- } +- +- if (trap & 0x01000000) { +- u32 stat = nv_rd32(priv, 0x400118); +- for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) { +- u32 mask = 0x00000001 << gpc; +- if (stat & mask) { +- nvc0_graph_trap_gpc(priv, gpc); +- nv_wr32(priv, 0x400118, mask); +- stat &= ~mask; +- } +- } +- nv_wr32(priv, 0x400108, 0x01000000); +- trap &= ~0x01000000; +- } +- +- if (trap & 0x02000000) { +- for (rop = 0; rop < priv->rop_nr; rop++) { +- u32 statz = nv_rd32(priv, ROP_UNIT(rop, 0x070)); +- u32 statc = nv_rd32(priv, ROP_UNIT(rop, 0x144)); +- nv_error(priv, "ROP%d 0x%08x 0x%08x\n", +- rop, statz, statc); +- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); +- } +- nv_wr32(priv, 0x400108, 0x02000000); +- trap &= ~0x02000000; +- } +- +- if (trap) { +- nv_error(priv, "TRAP UNHANDLED 0x%08x\n", trap); +- nv_wr32(priv, 0x400108, trap); +- } +-} +- +-static void +-nvc0_graph_ctxctl_debug_unit(struct nvc0_graph_priv *priv, u32 base) +-{ +- nv_error(priv, "%06x - done 0x%08x\n", base, +- nv_rd32(priv, base + 0x400)); +- nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, +- nv_rd32(priv, base + 0x800), nv_rd32(priv, base + 0x804), +- nv_rd32(priv, base + 0x808), nv_rd32(priv, base + 0x80c)); +- nv_error(priv, "%06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base, +- nv_rd32(priv, base + 0x810), nv_rd32(priv, base + 0x814), +- nv_rd32(priv, base + 0x818), nv_rd32(priv, base + 0x81c)); +-} +- +-void +-nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *priv) +-{ +- u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff; +- u32 gpc; +- +- nvc0_graph_ctxctl_debug_unit(priv, 0x409000); +- for (gpc = 0; gpc < gpcnr; gpc++) +- nvc0_graph_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000)); +-} +- +-static void +-nvc0_graph_ctxctl_isr(struct nvc0_graph_priv *priv) +-{ +- u32 stat = nv_rd32(priv, 0x409c18); +- +- if (stat & 0x00000001) { +- u32 code = nv_rd32(priv, 0x409814); +- if (code == E_BAD_FWMTHD) { +- u32 class = nv_rd32(priv, 0x409808); +- u32 addr = nv_rd32(priv, 0x40980c); +- u32 subc = (addr & 0x00070000) >> 16; +- u32 mthd = (addr & 0x00003ffc); +- u32 data = nv_rd32(priv, 0x409810); +- +- nv_error(priv, "FECS MTHD subc %d class 0x%04x " +- "mthd 0x%04x data 0x%08x\n", +- subc, class, mthd, data); +- +- nv_wr32(priv, 0x409c20, 0x00000001); +- stat &= ~0x00000001; +- } else { +- nv_error(priv, "FECS ucode error %d\n", code); +- } +- } +- +- if (stat & 0x00080000) { +- nv_error(priv, "FECS watchdog timeout\n"); +- nvc0_graph_ctxctl_debug(priv); +- nv_wr32(priv, 0x409c20, 0x00080000); +- stat &= ~0x00080000; +- } +- +- if (stat) { +- nv_error(priv, "FECS 0x%08x\n", stat); +- nvc0_graph_ctxctl_debug(priv); +- nv_wr32(priv, 0x409c20, stat); +- } +-} +- +-static void +-nvc0_graph_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nouveau_handle *handle; +- struct nvc0_graph_priv *priv = (void *)subdev; +- u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff; +- u32 stat = nv_rd32(priv, 0x400100); +- u32 addr = nv_rd32(priv, 0x400704); +- u32 mthd = (addr & 0x00003ffc); +- u32 subc = (addr & 0x00070000) >> 16; +- u32 data = nv_rd32(priv, 0x400708); +- u32 code = nv_rd32(priv, 0x400110); +- u32 class = nv_rd32(priv, 0x404200 + (subc * 4)); +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat & 0x00000010) { +- handle = nouveau_handle_get_class(engctx, class); +- if (!handle || nv_call(handle->object, mthd, data)) { +- nv_error(priv, +- "ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, inst << 12, nouveau_client_name(engctx), +- subc, class, mthd, data); +- } +- nouveau_handle_put(handle); +- nv_wr32(priv, 0x400100, 0x00000010); +- stat &= ~0x00000010; +- } +- +- if (stat & 0x00000020) { +- nv_error(priv, +- "ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, inst << 12, nouveau_client_name(engctx), subc, +- class, mthd, data); +- nv_wr32(priv, 0x400100, 0x00000020); +- stat &= ~0x00000020; +- } +- +- if (stat & 0x00100000) { +- nv_error(priv, "DATA_ERROR ["); +- nouveau_enum_print(nv50_data_error_names, code); +- pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n", +- chid, inst << 12, nouveau_client_name(engctx), subc, +- class, mthd, data); +- nv_wr32(priv, 0x400100, 0x00100000); +- stat &= ~0x00100000; +- } +- +- if (stat & 0x00200000) { +- nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12, +- nouveau_client_name(engctx)); +- nvc0_graph_trap_intr(priv); +- nv_wr32(priv, 0x400100, 0x00200000); +- stat &= ~0x00200000; +- } +- +- if (stat & 0x00080000) { +- nvc0_graph_ctxctl_isr(priv); +- nv_wr32(priv, 0x400100, 0x00080000); +- stat &= ~0x00080000; +- } +- +- if (stat) { +- nv_error(priv, "unknown stat 0x%08x\n", stat); +- nv_wr32(priv, 0x400100, stat); +- } +- +- nv_wr32(priv, 0x400500, 0x00010001); +- nouveau_engctx_put(engctx); +-} +- +-void +-nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, +- struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data) +-{ +- int i; +- +- nv_wr32(priv, fuc_base + 0x01c0, 0x01000000); +- for (i = 0; i < data->size / 4; i++) +- nv_wr32(priv, fuc_base + 0x01c4, data->data[i]); +- +- nv_wr32(priv, fuc_base + 0x0180, 0x01000000); +- for (i = 0; i < code->size / 4; i++) { +- if ((i & 0x3f) == 0) +- nv_wr32(priv, fuc_base + 0x0188, i >> 6); +- nv_wr32(priv, fuc_base + 0x0184, code->data[i]); +- } +- +- /* code must be padded to 0x40 words */ +- for (; i & 0x3f; i++) +- nv_wr32(priv, fuc_base + 0x0184, 0); +-} +- +-static void +-nvc0_graph_init_csdata(struct nvc0_graph_priv *priv, +- const struct nvc0_graph_pack *pack, +- u32 falcon, u32 starstar, u32 base) +-{ +- const struct nvc0_graph_pack *iter; +- const struct nvc0_graph_init *init; +- u32 addr = ~0, prev = ~0, xfer = 0; +- u32 star, temp; +- +- nv_wr32(priv, falcon + 0x01c0, 0x02000000 + starstar); +- star = nv_rd32(priv, falcon + 0x01c4); +- temp = nv_rd32(priv, falcon + 0x01c4); +- if (temp > star) +- star = temp; +- nv_wr32(priv, falcon + 0x01c0, 0x01000000 + star); +- +- pack_for_each_init(init, iter, pack) { +- u32 head = init->addr - base; +- u32 tail = head + init->count * init->pitch; +- while (head < tail) { +- if (head != prev + 4 || xfer >= 32) { +- if (xfer) { +- u32 data = ((--xfer << 26) | addr); +- nv_wr32(priv, falcon + 0x01c4, data); +- star += 4; +- } +- addr = head; +- xfer = 0; +- } +- prev = head; +- xfer = xfer + 1; +- head = head + init->pitch; +- } +- } +- +- nv_wr32(priv, falcon + 0x01c4, (--xfer << 26) | addr); +- nv_wr32(priv, falcon + 0x01c0, 0x01000004 + starstar); +- nv_wr32(priv, falcon + 0x01c4, star + 4); +-} +- +-int +-nvc0_graph_init_ctxctl(struct nvc0_graph_priv *priv) +-{ +- struct nvc0_graph_oclass *oclass = (void *)nv_object(priv)->oclass; +- struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass; +- int i; +- +- if (priv->firmware) { +- /* load fuc microcode */ +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); +- nvc0_graph_init_fw(priv, 0x409000, &priv->fuc409c, +- &priv->fuc409d); +- nvc0_graph_init_fw(priv, 0x41a000, &priv->fuc41ac, +- &priv->fuc41ad); +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +- +- /* start both of them running */ +- nv_wr32(priv, 0x409840, 0xffffffff); +- nv_wr32(priv, 0x41a10c, 0x00000000); +- nv_wr32(priv, 0x40910c, 0x00000000); +- nv_wr32(priv, 0x41a100, 0x00000002); +- nv_wr32(priv, 0x409100, 0x00000002); +- if (!nv_wait(priv, 0x409800, 0x00000001, 0x00000001)) +- nv_warn(priv, "0x409800 wait failed\n"); +- +- nv_wr32(priv, 0x409840, 0xffffffff); +- nv_wr32(priv, 0x409500, 0x7fffffff); +- nv_wr32(priv, 0x409504, 0x00000021); +- +- nv_wr32(priv, 0x409840, 0xffffffff); +- nv_wr32(priv, 0x409500, 0x00000000); +- nv_wr32(priv, 0x409504, 0x00000010); +- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { +- nv_error(priv, "fuc09 req 0x10 timeout\n"); +- return -EBUSY; +- } +- priv->size = nv_rd32(priv, 0x409800); +- +- nv_wr32(priv, 0x409840, 0xffffffff); +- nv_wr32(priv, 0x409500, 0x00000000); +- nv_wr32(priv, 0x409504, 0x00000016); +- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { +- nv_error(priv, "fuc09 req 0x16 timeout\n"); +- return -EBUSY; +- } +- +- nv_wr32(priv, 0x409840, 0xffffffff); +- nv_wr32(priv, 0x409500, 0x00000000); +- nv_wr32(priv, 0x409504, 0x00000025); +- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { +- nv_error(priv, "fuc09 req 0x25 timeout\n"); +- return -EBUSY; +- } +- +- if (nv_device(priv)->chipset >= 0xe0) { +- nv_wr32(priv, 0x409800, 0x00000000); +- nv_wr32(priv, 0x409500, 0x00000001); +- nv_wr32(priv, 0x409504, 0x00000030); +- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { +- nv_error(priv, "fuc09 req 0x30 timeout\n"); +- return -EBUSY; +- } +- +- nv_wr32(priv, 0x409810, 0xb00095c8); +- nv_wr32(priv, 0x409800, 0x00000000); +- nv_wr32(priv, 0x409500, 0x00000001); +- nv_wr32(priv, 0x409504, 0x00000031); +- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { +- nv_error(priv, "fuc09 req 0x31 timeout\n"); +- return -EBUSY; +- } +- +- nv_wr32(priv, 0x409810, 0x00080420); +- nv_wr32(priv, 0x409800, 0x00000000); +- nv_wr32(priv, 0x409500, 0x00000001); +- nv_wr32(priv, 0x409504, 0x00000032); +- if (!nv_wait_ne(priv, 0x409800, 0xffffffff, 0x00000000)) { +- nv_error(priv, "fuc09 req 0x32 timeout\n"); +- return -EBUSY; +- } +- +- nv_wr32(priv, 0x409614, 0x00000070); +- nv_wr32(priv, 0x409614, 0x00000770); +- nv_wr32(priv, 0x40802c, 0x00000001); +- } +- +- if (priv->data == NULL) { +- int ret = nvc0_grctx_generate(priv); +- if (ret) { +- nv_error(priv, "failed to construct context\n"); +- return ret; +- } +- } +- +- return 0; +- } else +- if (!oclass->fecs.ucode) { +- return -ENOSYS; +- } +- +- /* load HUB microcode */ +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0); +- nv_wr32(priv, 0x4091c0, 0x01000000); +- for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++) +- nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]); +- +- nv_wr32(priv, 0x409180, 0x01000000); +- for (i = 0; i < oclass->fecs.ucode->code.size / 4; i++) { +- if ((i & 0x3f) == 0) +- nv_wr32(priv, 0x409188, i >> 6); +- nv_wr32(priv, 0x409184, oclass->fecs.ucode->code.data[i]); +- } +- +- /* load GPC microcode */ +- nv_wr32(priv, 0x41a1c0, 0x01000000); +- for (i = 0; i < oclass->gpccs.ucode->data.size / 4; i++) +- nv_wr32(priv, 0x41a1c4, oclass->gpccs.ucode->data.data[i]); +- +- nv_wr32(priv, 0x41a180, 0x01000000); +- for (i = 0; i < oclass->gpccs.ucode->code.size / 4; i++) { +- if ((i & 0x3f) == 0) +- nv_wr32(priv, 0x41a188, i >> 6); +- nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]); +- } +- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1); +- +- /* load register lists */ +- nvc0_graph_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000); +- nvc0_graph_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000); +- nvc0_graph_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800); +- nvc0_graph_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00); +- +- /* start HUB ucode running, it'll init the GPCs */ +- nv_wr32(priv, 0x40910c, 0x00000000); +- nv_wr32(priv, 0x409100, 0x00000002); +- if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) { +- nv_error(priv, "HUB_INIT timed out\n"); +- nvc0_graph_ctxctl_debug(priv); +- return -EBUSY; +- } +- +- priv->size = nv_rd32(priv, 0x409804); +- if (priv->data == NULL) { +- int ret = nvc0_grctx_generate(priv); +- if (ret) { +- nv_error(priv, "failed to construct context\n"); +- return ret; +- } +- } +- +- return 0; +-} +- +-int +-nvc0_graph_init(struct nouveau_object *object) +-{ +- struct nvc0_graph_oclass *oclass = (void *)object->oclass; +- struct nvc0_graph_priv *priv = (void *)object; +- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); +- u32 data[TPC_MAX / 8] = {}; +- u8 tpcnr[GPC_MAX]; +- int gpc, tpc, rop; +- int ret, i; +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); +- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); +- +- nvc0_graph_mmio(priv, oclass->mmio); +- +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- for (i = 0, gpc = -1; i < priv->tpc_total; i++) { +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; +- +- data[i / 8] |= tpc << ((i % 8) * 4); +- } +- +- nv_wr32(priv, GPC_BCAST(0x0980), data[0]); +- nv_wr32(priv, GPC_BCAST(0x0984), data[1]); +- nv_wr32(priv, GPC_BCAST(0x0988), data[2]); +- nv_wr32(priv, GPC_BCAST(0x098c), data[3]); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- nv_wr32(priv, GPC_UNIT(gpc, 0x0914), +- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | +- priv->tpc_total); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); +- } +- +- if (nv_device(priv)->chipset != 0xd7) +- nv_wr32(priv, GPC_BCAST(0x1bd4), magicgpc918); +- else +- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); +- +- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); +- +- nv_wr32(priv, 0x400500, 0x00010001); +- +- nv_wr32(priv, 0x400100, 0xffffffff); +- nv_wr32(priv, 0x40013c, 0xffffffff); +- +- nv_wr32(priv, 0x409c24, 0x000f0000); +- nv_wr32(priv, 0x404000, 0xc0000000); +- nv_wr32(priv, 0x404600, 0xc0000000); +- nv_wr32(priv, 0x408030, 0xc0000000); +- nv_wr32(priv, 0x40601c, 0xc0000000); +- nv_wr32(priv, 0x404490, 0xc0000000); +- nv_wr32(priv, 0x406018, 0xc0000000); +- nv_wr32(priv, 0x405840, 0xc0000000); +- nv_wr32(priv, 0x405844, 0x00ffffff); +- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); +- nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); +- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); +- } +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); +- } +- +- for (rop = 0; rop < priv->rop_nr; rop++) { +- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); +- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); +- } +- +- nv_wr32(priv, 0x400108, 0xffffffff); +- nv_wr32(priv, 0x400138, 0xffffffff); +- nv_wr32(priv, 0x400118, 0xffffffff); +- nv_wr32(priv, 0x400130, 0xffffffff); +- nv_wr32(priv, 0x40011c, 0xffffffff); +- nv_wr32(priv, 0x400134, 0xffffffff); +- +- nv_wr32(priv, 0x400054, 0x34ce3464); +- +- nvc0_graph_zbc_init(priv); +- +- return nvc0_graph_init_ctxctl(priv); +-} +- +-static void +-nvc0_graph_dtor_fw(struct nvc0_graph_fuc *fuc) +-{ +- kfree(fuc->data); +- fuc->data = NULL; +-} +- +-int +-nvc0_graph_ctor_fw(struct nvc0_graph_priv *priv, const char *fwname, +- struct nvc0_graph_fuc *fuc) +-{ +- struct nouveau_device *device = nv_device(priv); +- const struct firmware *fw; +- char f[32]; +- int ret; +- +- snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); +- ret = request_firmware(&fw, f, nv_device_base(device)); +- if (ret) { +- snprintf(f, sizeof(f), "nouveau/%s", fwname); +- ret = request_firmware(&fw, f, nv_device_base(device)); +- if (ret) { +- nv_error(priv, "failed to load %s\n", fwname); +- return ret; +- } +- } +- +- fuc->size = fw->size; +- fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL); +- release_firmware(fw); +- return (fuc->data != NULL) ? 0 : -ENOMEM; +-} +- +-void +-nvc0_graph_dtor(struct nouveau_object *object) +-{ +- struct nvc0_graph_priv *priv = (void *)object; +- +- kfree(priv->data); +- +- nvc0_graph_dtor_fw(&priv->fuc409c); +- nvc0_graph_dtor_fw(&priv->fuc409d); +- nvc0_graph_dtor_fw(&priv->fuc41ac); +- nvc0_graph_dtor_fw(&priv->fuc41ad); +- +- nouveau_gpuobj_ref(NULL, &priv->unk4188b8); +- nouveau_gpuobj_ref(NULL, &priv->unk4188b4); +- +- nouveau_graph_destroy(&priv->base); +-} +- +-int +-nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *bclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_graph_oclass *oclass = (void *)bclass; +- struct nouveau_device *device = nv_device(parent); +- struct nvc0_graph_priv *priv; +- bool use_ext_fw, enable; +- int ret, i, j; +- +- use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW", +- oclass->fecs.ucode == NULL); +- enable = use_ext_fw || oclass->fecs.ucode != NULL; +- +- ret = nouveau_graph_create(parent, engine, bclass, enable, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x08001000; +- nv_subdev(priv)->intr = nvc0_graph_intr; +- +- priv->base.units = nvc0_graph_units; +- +- if (use_ext_fw) { +- nv_info(priv, "using external firmware\n"); +- if (nvc0_graph_ctor_fw(priv, "fuc409c", &priv->fuc409c) || +- nvc0_graph_ctor_fw(priv, "fuc409d", &priv->fuc409d) || +- nvc0_graph_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || +- nvc0_graph_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) +- return -EINVAL; +- priv->firmware = true; +- } +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, +- &priv->unk4188b4); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0, +- &priv->unk4188b8); +- if (ret) +- return ret; +- +- for (i = 0; i < 0x1000; i += 4) { +- nv_wo32(priv->unk4188b4, i, 0x00000010); +- nv_wo32(priv->unk4188b8, i, 0x00000010); +- } +- +- priv->rop_nr = (nv_rd32(priv, 0x409604) & 0x001f0000) >> 16; +- priv->gpc_nr = nv_rd32(priv, 0x409604) & 0x0000001f; +- for (i = 0; i < priv->gpc_nr; i++) { +- priv->tpc_nr[i] = nv_rd32(priv, GPC_UNIT(i, 0x2608)); +- priv->tpc_total += priv->tpc_nr[i]; +- priv->ppc_nr[i] = oclass->ppc_nr; +- for (j = 0; j < priv->ppc_nr[i]; j++) { +- u8 mask = nv_rd32(priv, GPC_UNIT(i, 0x0c30 + (j * 4))); +- priv->ppc_tpc_nr[i][j] = hweight8(mask); +- } +- } +- +- /*XXX: these need figuring out... though it might not even matter */ +- switch (nv_device(priv)->chipset) { +- case 0xc0: +- if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */ +- priv->magic_not_rop_nr = 0x07; +- } else +- if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */ +- priv->magic_not_rop_nr = 0x05; +- } else +- if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */ +- priv->magic_not_rop_nr = 0x06; +- } +- break; +- case 0xc3: /* 450, 4/0/0/0, 2 */ +- priv->magic_not_rop_nr = 0x03; +- break; +- case 0xc4: /* 460, 3/4/0/0, 4 */ +- priv->magic_not_rop_nr = 0x01; +- break; +- case 0xc1: /* 2/0/0/0, 1 */ +- priv->magic_not_rop_nr = 0x01; +- break; +- case 0xc8: /* 4/4/3/4, 5 */ +- priv->magic_not_rop_nr = 0x06; +- break; +- case 0xce: /* 4/4/0/0, 4 */ +- priv->magic_not_rop_nr = 0x03; +- break; +- case 0xcf: /* 4/0/0/0, 3 */ +- priv->magic_not_rop_nr = 0x03; +- break; +- case 0xd7: +- case 0xd9: /* 1/0/0/0, 1 */ +- priv->magic_not_rop_nr = 0x01; +- break; +- } +- +- nv_engine(priv)->cclass = *oclass->cclass; +- nv_engine(priv)->sclass = oclass->sclass; +- return 0; +-} +- +-#include "fuc/hubnvc0.fuc.h" +- +-struct nvc0_graph_ucode +-nvc0_graph_fecs_ucode = { +- .code.data = nvc0_grhub_code, +- .code.size = sizeof(nvc0_grhub_code), +- .data.data = nvc0_grhub_data, +- .data.size = sizeof(nvc0_grhub_data), +-}; +- +-#include "fuc/gpcnvc0.fuc.h" +- +-struct nvc0_graph_ucode +-nvc0_graph_gpccs_ucode = { +- .code.data = nvc0_grgpc_code, +- .code.size = sizeof(nvc0_grgpc_code), +- .data.data = nvc0_grgpc_data, +- .data.size = sizeof(nvc0_grgpc_data), +-}; +- +-struct nouveau_oclass * +-nvc0_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nvc0_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nvc0_grctx_oclass, +- .sclass = nvc0_graph_sclass, +- .mmio = nvc0_graph_pack_mmio, +- .fecs.ucode = &nvc0_graph_fecs_ucode, +- .gpccs.ucode = &nvc0_graph_gpccs_ucode, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h +deleted file mode 100644 +index 7ed9e89c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h ++++ /dev/null +@@ -1,270 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifndef __NVC0_GRAPH_H__ +-#define __NVC0_GRAPH_H__ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include "fuc/os.h" +- +-#define GPC_MAX 32 +-#define TPC_MAX (GPC_MAX * 8) +- +-#define ROP_BCAST(r) (0x408800 + (r)) +-#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r)) +-#define GPC_BCAST(r) (0x418000 + (r)) +-#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r)) +-#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r)) +-#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r)) +- +-struct nvc0_graph_data { +- u32 size; +- u32 align; +- u32 access; +-}; +- +-struct nvc0_graph_mmio { +- u32 addr; +- u32 data; +- u32 shift; +- int buffer; +-}; +- +-struct nvc0_graph_fuc { +- u32 *data; +- u32 size; +-}; +- +-struct nvc0_graph_zbc_color { +- u32 format; +- u32 ds[4]; +- u32 l2[4]; +-}; +- +-struct nvc0_graph_zbc_depth { +- u32 format; +- u32 ds; +- u32 l2; +-}; +- +-struct nvc0_graph_priv { +- struct nouveau_graph base; +- +- struct nvc0_graph_fuc fuc409c; +- struct nvc0_graph_fuc fuc409d; +- struct nvc0_graph_fuc fuc41ac; +- struct nvc0_graph_fuc fuc41ad; +- bool firmware; +- +- struct nvc0_graph_zbc_color zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT]; +- struct nvc0_graph_zbc_depth zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; +- +- u8 rop_nr; +- u8 gpc_nr; +- u8 tpc_nr[GPC_MAX]; +- u8 tpc_total; +- u8 ppc_nr[GPC_MAX]; +- u8 ppc_tpc_nr[GPC_MAX][4]; +- +- struct nouveau_gpuobj *unk4188b4; +- struct nouveau_gpuobj *unk4188b8; +- +- struct nvc0_graph_data mmio_data[4]; +- struct nvc0_graph_mmio mmio_list[4096/8]; +- u32 size; +- u32 *data; +- +- u8 magic_not_rop_nr; +-}; +- +-struct nvc0_graph_chan { +- struct nouveau_graph_chan base; +- +- struct nouveau_gpuobj *mmio; +- struct nouveau_vma mmio_vma; +- int mmio_nr; +- struct { +- struct nouveau_gpuobj *mem; +- struct nouveau_vma vma; +- } data[4]; +-}; +- +-int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nvc0_graph_context_dtor(struct nouveau_object *); +- +-void nvc0_graph_ctxctl_debug(struct nvc0_graph_priv *); +- +-u64 nvc0_graph_units(struct nouveau_graph *); +-int nvc0_graph_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *data, u32 size, +- struct nouveau_object **); +-void nvc0_graph_dtor(struct nouveau_object *); +-int nvc0_graph_init(struct nouveau_object *); +-void nvc0_graph_zbc_init(struct nvc0_graph_priv *); +- +-int nve4_graph_fini(struct nouveau_object *, bool); +-int nve4_graph_init(struct nouveau_object *); +- +-int nvf0_graph_fini(struct nouveau_object *, bool); +- +-extern struct nouveau_ofuncs nvc0_fermi_ofuncs; +- +-extern struct nouveau_oclass nvc0_graph_sclass[]; +-extern struct nouveau_omthds nvc0_graph_9097_omthds[]; +-extern struct nouveau_omthds nvc0_graph_90c0_omthds[]; +-extern struct nouveau_oclass nvc8_graph_sclass[]; +-extern struct nouveau_oclass nvf0_graph_sclass[]; +- +-struct nvc0_graph_init { +- u32 addr; +- u8 count; +- u8 pitch; +- u32 data; +-}; +- +-struct nvc0_graph_pack { +- const struct nvc0_graph_init *init; +- u32 type; +-}; +- +-#define pack_for_each_init(init, pack, head) \ +- for (pack = head; pack && pack->init; pack++) \ +- for (init = pack->init; init && init->count; init++) +- +-struct nvc0_graph_ucode { +- struct nvc0_graph_fuc code; +- struct nvc0_graph_fuc data; +-}; +- +-extern struct nvc0_graph_ucode nvc0_graph_fecs_ucode; +-extern struct nvc0_graph_ucode nvc0_graph_gpccs_ucode; +- +-extern struct nvc0_graph_ucode nvf0_graph_fecs_ucode; +-extern struct nvc0_graph_ucode nvf0_graph_gpccs_ucode; +- +-struct nvc0_graph_oclass { +- struct nouveau_oclass base; +- struct nouveau_oclass **cclass; +- struct nouveau_oclass *sclass; +- const struct nvc0_graph_pack *mmio; +- struct { +- struct nvc0_graph_ucode *ucode; +- } fecs; +- struct { +- struct nvc0_graph_ucode *ucode; +- } gpccs; +- int ppc_nr; +-}; +- +-void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); +-void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); +-void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *); +-int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *); +- +-/* register init value lists */ +- +-extern const struct nvc0_graph_init nvc0_graph_init_main_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_fe_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_pri_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_pd_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_ds_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_scc_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_prop_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_setup_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_crstr_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_setup_1[]; +-extern const struct nvc0_graph_init nvc0_graph_init_zcull_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_gpm_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_gpc_unk_1[]; +-extern const struct nvc0_graph_init nvc0_graph_init_gcc_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_tex_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_pe_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_l1c_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_wwdx_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_tpccs_1[]; +-extern const struct nvc0_graph_init nvc0_graph_init_mpc_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_be_0[]; +-extern const struct nvc0_graph_init nvc0_graph_init_fe_1[]; +-extern const struct nvc0_graph_init nvc0_graph_init_pe_1[]; +- +-extern const struct nvc0_graph_init nvc4_graph_init_ds_0[]; +-extern const struct nvc0_graph_init nvc4_graph_init_tex_0[]; +-extern const struct nvc0_graph_init nvc4_graph_init_sm_0[]; +- +-extern const struct nvc0_graph_init nvc1_graph_init_gpc_unk_0[]; +-extern const struct nvc0_graph_init nvc1_graph_init_setup_1[]; +- +-extern const struct nvc0_graph_init nvd9_graph_init_pd_0[]; +-extern const struct nvc0_graph_init nvd9_graph_init_ds_0[]; +-extern const struct nvc0_graph_init nvd9_graph_init_prop_0[]; +-extern const struct nvc0_graph_init nvd9_graph_init_gpm_0[]; +-extern const struct nvc0_graph_init nvd9_graph_init_gpc_unk_1[]; +-extern const struct nvc0_graph_init nvd9_graph_init_tex_0[]; +-extern const struct nvc0_graph_init nvd9_graph_init_sm_0[]; +-extern const struct nvc0_graph_init nvd9_graph_init_fe_1[]; +- +-extern const struct nvc0_graph_init nvd7_graph_init_pes_0[]; +-extern const struct nvc0_graph_init nvd7_graph_init_wwdx_0[]; +-extern const struct nvc0_graph_init nvd7_graph_init_cbm_0[]; +- +-extern const struct nvc0_graph_init nve4_graph_init_main_0[]; +-extern const struct nvc0_graph_init nve4_graph_init_tpccs_0[]; +-extern const struct nvc0_graph_init nve4_graph_init_pe_0[]; +-extern const struct nvc0_graph_init nve4_graph_init_be_0[]; +-extern const struct nvc0_graph_pack nve4_graph_pack_mmio[]; +- +-extern const struct nvc0_graph_init nvf0_graph_init_fe_0[]; +-extern const struct nvc0_graph_init nvf0_graph_init_ds_0[]; +-extern const struct nvc0_graph_init nvf0_graph_init_sked_0[]; +-extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[]; +-extern const struct nvc0_graph_init nvf0_graph_init_gpc_unk_1[]; +-extern const struct nvc0_graph_init nvf0_graph_init_tex_0[]; +-extern const struct nvc0_graph_init nvf0_graph_init_sm_0[]; +- +-extern const struct nvc0_graph_init nv108_graph_init_gpc_unk_0[]; +- +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c +deleted file mode 100644 +index 93d58e5b..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c ++++ /dev/null +@@ -1,133 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc1_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0x9039, &nouveau_object_ofuncs }, +- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nvc1_graph_init_gpc_unk_0[] = { +- { 0x418604, 1, 0x04, 0x00000000 }, +- { 0x418680, 1, 0x04, 0x00000000 }, +- { 0x418714, 1, 0x04, 0x00000000 }, +- { 0x418384, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc1_graph_init_setup_1[] = { +- { 0x4188c8, 2, 0x04, 0x00000000 }, +- { 0x4188d0, 1, 0x04, 0x00010000 }, +- { 0x4188d4, 1, 0x04, 0x00000001 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_graph_init_gpc_unk_1[] = { +- { 0x418d00, 1, 0x04, 0x00000000 }, +- { 0x418f08, 1, 0x04, 0x00000000 }, +- { 0x418e00, 1, 0x04, 0x00000003 }, +- { 0x418e08, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc1_graph_init_pe_0[] = { +- { 0x41980c, 1, 0x04, 0x00000010 }, +- { 0x419810, 1, 0x04, 0x00000000 }, +- { 0x419814, 1, 0x04, 0x00000004 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x41984c, 1, 0x04, 0x00005bc5 }, +- { 0x419850, 4, 0x04, 0x00000000 }, +- { 0x419880, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc1_graph_pack_mmio[] = { +- { nvc0_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvc0_graph_init_pd_0 }, +- { nvc4_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvc0_graph_init_prop_0 }, +- { nvc1_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvc0_graph_init_gpm_0 }, +- { nvc1_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nvc0_graph_init_tpccs_0 }, +- { nvc4_graph_init_tex_0 }, +- { nvc1_graph_init_pe_0 }, +- { nvc0_graph_init_l1c_0 }, +- { nvc0_graph_init_wwdx_0 }, +- { nvc0_graph_init_tpccs_1 }, +- { nvc0_graph_init_mpc_0 }, +- { nvc4_graph_init_sm_0 }, +- { nvc0_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvc1_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xc1), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nvc0_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nvc1_grctx_oclass, +- .sclass = nvc1_graph_sclass, +- .mmio = nvc1_graph_pack_mmio, +- .fecs.ucode = &nvc0_graph_fecs_ucode, +- .gpccs.ucode = &nvc0_graph_gpccs_ucode, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c +deleted file mode 100644 +index e82e70c5..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c ++++ /dev/null +@@ -1,128 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nvc4_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405900, 1, 0x04, 0x00002834 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc4_graph_init_tex_0[] = { +- { 0x419ab0, 1, 0x04, 0x00000000 }, +- { 0x419ac8, 1, 0x04, 0x00000000 }, +- { 0x419ab8, 1, 0x04, 0x000000e7 }, +- { 0x419abc, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvc4_graph_init_pe_0[] = { +- { 0x41980c, 3, 0x04, 0x00000000 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x41984c, 1, 0x04, 0x00005bc5 }, +- { 0x419850, 4, 0x04, 0x00000000 }, +- { 0x419880, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvc4_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000000 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x00001100 }, +- { 0x419eac, 1, 0x04, 0x11100702 }, +- { 0x419eb0, 1, 0x04, 0x00000003 }, +- { 0x419eb4, 4, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x0e063818 }, +- { 0x419ecc, 1, 0x04, 0x0e060e06 }, +- { 0x419ed0, 1, 0x04, 0x00003818 }, +- { 0x419ed4, 1, 0x04, 0x011104f1 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419f2c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc4_graph_pack_mmio[] = { +- { nvc0_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvc0_graph_init_pd_0 }, +- { nvc4_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvc0_graph_init_prop_0 }, +- { nvc0_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc0_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvc0_graph_init_gpm_0 }, +- { nvc0_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nvc0_graph_init_tpccs_0 }, +- { nvc4_graph_init_tex_0 }, +- { nvc4_graph_init_pe_0 }, +- { nvc0_graph_init_l1c_0 }, +- { nvc0_graph_init_wwdx_0 }, +- { nvc0_graph_init_tpccs_1 }, +- { nvc0_graph_init_mpc_0 }, +- { nvc4_graph_init_sm_0 }, +- { nvc0_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvc4_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xc3), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nvc0_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nvc4_grctx_oclass, +- .sclass = nvc0_graph_sclass, +- .mmio = nvc4_graph_pack_mmio, +- .fecs.ucode = &nvc0_graph_fecs_ucode, +- .gpccs.ucode = &nvc0_graph_gpccs_ucode, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c +deleted file mode 100644 +index 692e1eda..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-struct nouveau_oclass +-nvc8_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0x9039, &nouveau_object_ofuncs }, +- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { FERMI_C, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvc8_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000000 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x00001100 }, +- { 0x419eac, 1, 0x04, 0x11100f02 }, +- { 0x419eb0, 1, 0x04, 0x00000003 }, +- { 0x419eb4, 4, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x06060618 }, +- { 0x419ed0, 1, 0x04, 0x0eff0e38 }, +- { 0x419ed4, 1, 0x04, 0x011104f1 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419f2c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvc8_graph_pack_mmio[] = { +- { nvc0_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvc0_graph_init_pd_0 }, +- { nvc0_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvc0_graph_init_prop_0 }, +- { nvc0_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvc0_graph_init_gpm_0 }, +- { nvc0_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nvc0_graph_init_tpccs_0 }, +- { nvc0_graph_init_tex_0 }, +- { nvc0_graph_init_pe_0 }, +- { nvc0_graph_init_l1c_0 }, +- { nvc0_graph_init_wwdx_0 }, +- { nvc0_graph_init_tpccs_1 }, +- { nvc0_graph_init_mpc_0 }, +- { nvc8_graph_init_sm_0 }, +- { nvc0_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- { nvc0_graph_init_pe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvc8_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xc8), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nvc0_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nvc8_grctx_oclass, +- .sclass = nvc8_graph_sclass, +- .mmio = nvc8_graph_pack_mmio, +- .fecs.ucode = &nvc0_graph_fecs_ucode, +- .gpccs.ucode = &nvc0_graph_gpccs_ucode, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c +deleted file mode 100644 +index 41e8445c..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-static const struct nvc0_graph_init +-nvd7_graph_init_pe_0[] = { +- { 0x41980c, 1, 0x04, 0x00000010 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x41984c, 1, 0x04, 0x00005bc8 }, +- { 0x419850, 3, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd7_graph_init_pes_0[] = { +- { 0x41be04, 1, 0x04, 0x00000000 }, +- { 0x41be08, 1, 0x04, 0x00000004 }, +- { 0x41be0c, 1, 0x04, 0x00000000 }, +- { 0x41be10, 1, 0x04, 0x003b8bc7 }, +- { 0x41be14, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd7_graph_init_wwdx_0[] = { +- { 0x41bfd4, 1, 0x04, 0x00800000 }, +- { 0x41bfdc, 1, 0x04, 0x00000000 }, +- { 0x41bff8, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd7_graph_init_cbm_0[] = { +- { 0x41becc, 1, 0x04, 0x00000000 }, +- { 0x41bee8, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd7_graph_pack_mmio[] = { +- { nvc0_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvd9_graph_init_pd_0 }, +- { nvd9_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvd9_graph_init_prop_0 }, +- { nvc1_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvd9_graph_init_gpm_0 }, +- { nvd9_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nvc0_graph_init_tpccs_0 }, +- { nvd9_graph_init_tex_0 }, +- { nvd7_graph_init_pe_0 }, +- { nvc0_graph_init_l1c_0 }, +- { nvc0_graph_init_mpc_0 }, +- { nvd9_graph_init_sm_0 }, +- { nvd7_graph_init_pes_0 }, +- { nvd7_graph_init_wwdx_0 }, +- { nvd7_graph_init_cbm_0 }, +- { nvc0_graph_init_be_0 }, +- { nvd9_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-#include "fuc/hubnvd7.fuc.h" +- +-struct nvc0_graph_ucode +-nvd7_graph_fecs_ucode = { +- .code.data = nvd7_grhub_code, +- .code.size = sizeof(nvd7_grhub_code), +- .data.data = nvd7_grhub_data, +- .data.size = sizeof(nvd7_grhub_data), +-}; +- +-#include "fuc/gpcnvd7.fuc.h" +- +-struct nvc0_graph_ucode +-nvd7_graph_gpccs_ucode = { +- .code.data = nvd7_grgpc_code, +- .code.size = sizeof(nvd7_grgpc_code), +- .data.data = nvd7_grgpc_data, +- .data.size = sizeof(nvd7_grgpc_data), +-}; +- +-struct nouveau_oclass * +-nvd7_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xd7), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nvc0_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nvd7_grctx_oclass, +- .sclass = nvc8_graph_sclass, +- .mmio = nvd7_graph_pack_mmio, +- .fecs.ucode = &nvd7_graph_fecs_ucode, +- .gpccs.ucode = &nvd7_graph_gpccs_ucode, +- .ppc_nr = 1, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c +deleted file mode 100644 +index 00fdf202..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c ++++ /dev/null +@@ -1,191 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nvd9_graph_init_pd_0[] = { +- { 0x406024, 1, 0x04, 0x00000000 }, +- { 0x4064f0, 3, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405900, 1, 0x04, 0x00002834 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- { 0x405928, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_prop_0[] = { +- { 0x418408, 1, 0x04, 0x00000000 }, +- { 0x4184a0, 3, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_gpm_0[] = { +- { 0x418c04, 1, 0x04, 0x00000000 }, +- { 0x418c64, 2, 0x04, 0x00000000 }, +- { 0x418c88, 1, 0x04, 0x00000000 }, +- { 0x418cb4, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_gpc_unk_1[] = { +- { 0x418d00, 1, 0x04, 0x00000000 }, +- { 0x418d28, 2, 0x04, 0x00000000 }, +- { 0x418f00, 1, 0x04, 0x00000000 }, +- { 0x418f08, 1, 0x04, 0x00000000 }, +- { 0x418f20, 2, 0x04, 0x00000000 }, +- { 0x418e00, 1, 0x04, 0x00000003 }, +- { 0x418e08, 1, 0x04, 0x00000000 }, +- { 0x418e1c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_tex_0[] = { +- { 0x419ab0, 1, 0x04, 0x00000000 }, +- { 0x419ac8, 1, 0x04, 0x00000000 }, +- { 0x419ab8, 1, 0x04, 0x000000e7 }, +- { 0x419abc, 2, 0x04, 0x00000000 }, +- { 0x419ab4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_graph_init_pe_0[] = { +- { 0x41980c, 1, 0x04, 0x00000010 }, +- { 0x419810, 1, 0x04, 0x00000000 }, +- { 0x419814, 1, 0x04, 0x00000004 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x41984c, 1, 0x04, 0x0000a918 }, +- { 0x419850, 4, 0x04, 0x00000000 }, +- { 0x419880, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_graph_init_wwdx_0[] = { +- { 0x419bd4, 1, 0x04, 0x00800000 }, +- { 0x419bdc, 1, 0x04, 0x00000000 }, +- { 0x419bf8, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvd9_graph_init_tpccs_1[] = { +- { 0x419d2c, 1, 0x04, 0x00000000 }, +- { 0x419d48, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000000 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x02001100 }, +- { 0x419eac, 1, 0x04, 0x11100702 }, +- { 0x419eb0, 1, 0x04, 0x00000003 }, +- { 0x419eb4, 4, 0x04, 0x00000000 }, +- { 0x419ec8, 1, 0x04, 0x0e063818 }, +- { 0x419ecc, 1, 0x04, 0x0e060e06 }, +- { 0x419ed0, 1, 0x04, 0x00003818 }, +- { 0x419ed4, 1, 0x04, 0x011104f1 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419f2c, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvd9_graph_init_fe_1[] = { +- { 0x40402c, 1, 0x04, 0x00000000 }, +- { 0x4040f0, 1, 0x04, 0x00000000 }, +- { 0x404174, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvd9_graph_pack_mmio[] = { +- { nvc0_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvd9_graph_init_pd_0 }, +- { nvd9_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvd9_graph_init_prop_0 }, +- { nvc1_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvd9_graph_init_gpm_0 }, +- { nvd9_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nvc0_graph_init_tpccs_0 }, +- { nvd9_graph_init_tex_0 }, +- { nvd9_graph_init_pe_0 }, +- { nvc0_graph_init_l1c_0 }, +- { nvd9_graph_init_wwdx_0 }, +- { nvd9_graph_init_tpccs_1 }, +- { nvc0_graph_init_mpc_0 }, +- { nvd9_graph_init_sm_0 }, +- { nvc0_graph_init_be_0 }, +- { nvd9_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvd9_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xd9), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nvc0_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nvd9_grctx_oclass, +- .sclass = nvc8_graph_sclass, +- .mmio = nvd9_graph_pack_mmio, +- .fecs.ucode = &nvc0_graph_fecs_ucode, +- .gpccs.ucode = &nvc0_graph_gpccs_ucode, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c b/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c +deleted file mode 100644 +index 0c71f5c6..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nve4.c ++++ /dev/null +@@ -1,347 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve4_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0xa040, &nouveau_object_ofuncs }, +- { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nve4_graph_init_main_0[] = { +- { 0x400080, 1, 0x04, 0x003083c2 }, +- { 0x400088, 1, 0x04, 0x0001ffe7 }, +- { 0x40008c, 1, 0x04, 0x00000000 }, +- { 0x400090, 1, 0x04, 0x00000030 }, +- { 0x40013c, 1, 0x04, 0x003901f7 }, +- { 0x400140, 1, 0x04, 0x00000100 }, +- { 0x400144, 1, 0x04, 0x00000000 }, +- { 0x400148, 1, 0x04, 0x00000110 }, +- { 0x400138, 1, 0x04, 0x00000000 }, +- { 0x400130, 2, 0x04, 0x00000000 }, +- { 0x400124, 1, 0x04, 0x00000002 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405900, 1, 0x04, 0x0000ff34 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- { 0x405928, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_graph_init_sked_0[] = { +- { 0x407010, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_graph_init_cwd_0[] = { +- { 0x405b50, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_graph_init_gpc_unk_1[] = { +- { 0x418d00, 1, 0x04, 0x00000000 }, +- { 0x418d28, 2, 0x04, 0x00000000 }, +- { 0x418f00, 1, 0x04, 0x00000000 }, +- { 0x418f08, 1, 0x04, 0x00000000 }, +- { 0x418f20, 2, 0x04, 0x00000000 }, +- { 0x418e00, 1, 0x04, 0x00000060 }, +- { 0x418e08, 1, 0x04, 0x00000000 }, +- { 0x418e1c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_graph_init_tpccs_0[] = { +- { 0x419d0c, 1, 0x04, 0x00000000 }, +- { 0x419d10, 1, 0x04, 0x00000014 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_graph_init_pe_0[] = { +- { 0x41980c, 1, 0x04, 0x00000010 }, +- { 0x419844, 1, 0x04, 0x00000000 }, +- { 0x419850, 1, 0x04, 0x00000004 }, +- { 0x419854, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_graph_init_l1c_0[] = { +- { 0x419c98, 1, 0x04, 0x00000000 }, +- { 0x419ca8, 1, 0x04, 0x00000000 }, +- { 0x419cb0, 1, 0x04, 0x01000000 }, +- { 0x419cb4, 1, 0x04, 0x00000000 }, +- { 0x419cb8, 1, 0x04, 0x00b08bea }, +- { 0x419c84, 1, 0x04, 0x00010384 }, +- { 0x419cbc, 1, 0x04, 0x28137646 }, +- { 0x419cc0, 2, 0x04, 0x00000000 }, +- { 0x419c80, 1, 0x04, 0x00020232 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nve4_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000000 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ee4, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x00000000 }, +- { 0x419eb4, 4, 0x04, 0x00000000 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419f74, 1, 0x04, 0x00000555 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nve4_graph_init_be_0[] = { +- { 0x40880c, 1, 0x04, 0x00000000 }, +- { 0x408850, 1, 0x04, 0x00000004 }, +- { 0x408910, 9, 0x04, 0x00000000 }, +- { 0x408950, 1, 0x04, 0x00000000 }, +- { 0x408954, 1, 0x04, 0x0000ffff }, +- { 0x408958, 1, 0x04, 0x00000034 }, +- { 0x408984, 1, 0x04, 0x00000000 }, +- { 0x408988, 1, 0x04, 0x08040201 }, +- { 0x40898c, 1, 0x04, 0x80402010 }, +- {} +-}; +- +-const struct nvc0_graph_pack +-nve4_graph_pack_mmio[] = { +- { nve4_graph_init_main_0 }, +- { nvc0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvd9_graph_init_pd_0 }, +- { nve4_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nve4_graph_init_sked_0 }, +- { nve4_graph_init_cwd_0 }, +- { nvd9_graph_init_prop_0 }, +- { nvc1_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvd9_graph_init_gpm_0 }, +- { nve4_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nve4_graph_init_tpccs_0 }, +- { nvd9_graph_init_tex_0 }, +- { nve4_graph_init_pe_0 }, +- { nve4_graph_init_l1c_0 }, +- { nvc0_graph_init_mpc_0 }, +- { nve4_graph_init_sm_0 }, +- { nvd7_graph_init_pes_0 }, +- { nvd7_graph_init_wwdx_0 }, +- { nvd7_graph_init_cbm_0 }, +- { nve4_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-int +-nve4_graph_init(struct nouveau_object *object) +-{ +- struct nvc0_graph_oclass *oclass = (void *)object->oclass; +- struct nvc0_graph_priv *priv = (void *)object; +- struct nouveau_pwr *ppwr = nouveau_pwr(priv); +- const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total); +- u32 data[TPC_MAX / 8] = {}; +- u8 tpcnr[GPC_MAX]; +- int gpc, tpc, rop; +- int ret, i; +- +- if (ppwr) +- ppwr->pgob(ppwr, false); +- +- ret = nouveau_graph_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, GPC_BCAST(0x0880), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x08a4), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0888), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x088c), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0890), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x0894), 0x00000000); +- nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8); +- nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8); +- +- nvc0_graph_mmio(priv, oclass->mmio); +- +- nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001); +- +- memset(data, 0x00, sizeof(data)); +- memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr)); +- for (i = 0, gpc = -1; i < priv->tpc_total; i++) { +- do { +- gpc = (gpc + 1) % priv->gpc_nr; +- } while (!tpcnr[gpc]); +- tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--; +- +- data[i / 8] |= tpc << ((i % 8) * 4); +- } +- +- nv_wr32(priv, GPC_BCAST(0x0980), data[0]); +- nv_wr32(priv, GPC_BCAST(0x0984), data[1]); +- nv_wr32(priv, GPC_BCAST(0x0988), data[2]); +- nv_wr32(priv, GPC_BCAST(0x098c), data[3]); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- nv_wr32(priv, GPC_UNIT(gpc, 0x0914), +- priv->magic_not_rop_nr << 8 | priv->tpc_nr[gpc]); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0910), 0x00040000 | +- priv->tpc_total); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0918), magicgpc918); +- } +- +- nv_wr32(priv, GPC_BCAST(0x3fd4), magicgpc918); +- nv_wr32(priv, GPC_BCAST(0x08ac), nv_rd32(priv, 0x100800)); +- +- nv_wr32(priv, 0x400500, 0x00010001); +- +- nv_wr32(priv, 0x400100, 0xffffffff); +- nv_wr32(priv, 0x40013c, 0xffffffff); +- +- nv_wr32(priv, 0x409ffc, 0x00000000); +- nv_wr32(priv, 0x409c14, 0x00003e3e); +- nv_wr32(priv, 0x409c24, 0x000f0001); +- nv_wr32(priv, 0x404000, 0xc0000000); +- nv_wr32(priv, 0x404600, 0xc0000000); +- nv_wr32(priv, 0x408030, 0xc0000000); +- nv_wr32(priv, 0x404490, 0xc0000000); +- nv_wr32(priv, 0x406018, 0xc0000000); +- nv_wr32(priv, 0x407020, 0x40000000); +- nv_wr32(priv, 0x405840, 0xc0000000); +- nv_wr32(priv, 0x405844, 0x00ffffff); +- nv_mask(priv, 0x419cc0, 0x00000008, 0x00000008); +- nv_mask(priv, 0x419eb4, 0x00001000, 0x00001000); +- +- for (gpc = 0; gpc < priv->gpc_nr; gpc++) { +- nv_wr32(priv, GPC_UNIT(gpc, 0x3038), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0900), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x1028), 0xc0000000); +- nv_wr32(priv, GPC_UNIT(gpc, 0x0824), 0xc0000000); +- for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) { +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe); +- nv_wr32(priv, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f); +- } +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), 0xffffffff); +- nv_wr32(priv, GPC_UNIT(gpc, 0x2c94), 0xffffffff); +- } +- +- for (rop = 0; rop < priv->rop_nr; rop++) { +- nv_wr32(priv, ROP_UNIT(rop, 0x144), 0xc0000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x070), 0xc0000000); +- nv_wr32(priv, ROP_UNIT(rop, 0x204), 0xffffffff); +- nv_wr32(priv, ROP_UNIT(rop, 0x208), 0xffffffff); +- } +- +- nv_wr32(priv, 0x400108, 0xffffffff); +- nv_wr32(priv, 0x400138, 0xffffffff); +- nv_wr32(priv, 0x400118, 0xffffffff); +- nv_wr32(priv, 0x400130, 0xffffffff); +- nv_wr32(priv, 0x40011c, 0xffffffff); +- nv_wr32(priv, 0x400134, 0xffffffff); +- +- nv_wr32(priv, 0x400054, 0x34ce3464); +- +- nvc0_graph_zbc_init(priv); +- +- return nvc0_graph_init_ctxctl(priv); +-} +- +-#include "fuc/hubnve0.fuc.h" +- +-static struct nvc0_graph_ucode +-nve4_graph_fecs_ucode = { +- .code.data = nve0_grhub_code, +- .code.size = sizeof(nve0_grhub_code), +- .data.data = nve0_grhub_data, +- .data.size = sizeof(nve0_grhub_data), +-}; +- +-#include "fuc/gpcnve0.fuc.h" +- +-static struct nvc0_graph_ucode +-nve4_graph_gpccs_ucode = { +- .code.data = nve0_grgpc_code, +- .code.size = sizeof(nve0_grgpc_code), +- .data.data = nve0_grgpc_data, +- .data.size = sizeof(nve0_grgpc_data), +-}; +- +-struct nouveau_oclass * +-nve4_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xe4), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nve4_graph_init, +- .fini = _nouveau_graph_fini, +- }, +- .cclass = &nve4_grctx_oclass, +- .sclass = nve4_graph_sclass, +- .mmio = nve4_graph_pack_mmio, +- .fecs.ucode = &nve4_graph_fecs_ucode, +- .gpccs.ucode = &nve4_graph_gpccs_ucode, +- .ppc_nr = 1, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c +deleted file mode 100644 +index c306c0f2..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvf0.c ++++ /dev/null +@@ -1,245 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +-#include "ctxnvc0.h" +- +-/******************************************************************************* +- * Graphics object classes +- ******************************************************************************/ +- +-struct nouveau_oclass +-nvf0_graph_sclass[] = { +- { 0x902d, &nouveau_object_ofuncs }, +- { 0xa140, &nouveau_object_ofuncs }, +- { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_graph_9097_omthds }, +- { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_graph_90c0_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH register lists +- ******************************************************************************/ +- +-const struct nvc0_graph_init +-nvf0_graph_init_fe_0[] = { +- { 0x40415c, 1, 0x04, 0x00000000 }, +- { 0x404170, 1, 0x04, 0x00000000 }, +- { 0x4041b4, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_graph_init_ds_0[] = { +- { 0x405844, 1, 0x04, 0x00ffffff }, +- { 0x405850, 1, 0x04, 0x00000000 }, +- { 0x405900, 1, 0x04, 0x0000ff00 }, +- { 0x405908, 1, 0x04, 0x00000000 }, +- { 0x405928, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_graph_init_sked_0[] = { +- { 0x407010, 1, 0x04, 0x00000000 }, +- { 0x407040, 1, 0x04, 0x80440424 }, +- { 0x407048, 1, 0x04, 0x0000000a }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_graph_init_cwd_0[] = { +- { 0x405b44, 1, 0x04, 0x00000000 }, +- { 0x405b50, 1, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_graph_init_gpc_unk_1[] = { +- { 0x418d00, 1, 0x04, 0x00000000 }, +- { 0x418d28, 2, 0x04, 0x00000000 }, +- { 0x418f00, 1, 0x04, 0x00000400 }, +- { 0x418f08, 1, 0x04, 0x00000000 }, +- { 0x418f20, 2, 0x04, 0x00000000 }, +- { 0x418e00, 1, 0x04, 0x00000000 }, +- { 0x418e08, 1, 0x04, 0x00000000 }, +- { 0x418e1c, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_graph_init_tex_0[] = { +- { 0x419ab0, 1, 0x04, 0x00000000 }, +- { 0x419ac8, 1, 0x04, 0x00000000 }, +- { 0x419ab8, 1, 0x04, 0x000000e7 }, +- { 0x419aec, 1, 0x04, 0x00000000 }, +- { 0x419abc, 2, 0x04, 0x00000000 }, +- { 0x419ab4, 1, 0x04, 0x00000000 }, +- { 0x419aa8, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_init +-nvf0_graph_init_l1c_0[] = { +- { 0x419c98, 1, 0x04, 0x00000000 }, +- { 0x419ca8, 1, 0x04, 0x00000000 }, +- { 0x419cb0, 1, 0x04, 0x01000000 }, +- { 0x419cb4, 1, 0x04, 0x00000000 }, +- { 0x419cb8, 1, 0x04, 0x00b08bea }, +- { 0x419c84, 1, 0x04, 0x00010384 }, +- { 0x419cbc, 1, 0x04, 0x281b3646 }, +- { 0x419cc0, 2, 0x04, 0x00000000 }, +- { 0x419c80, 1, 0x04, 0x00020230 }, +- { 0x419ccc, 2, 0x04, 0x00000000 }, +- {} +-}; +- +-const struct nvc0_graph_init +-nvf0_graph_init_sm_0[] = { +- { 0x419e00, 1, 0x04, 0x00000080 }, +- { 0x419ea0, 1, 0x04, 0x00000000 }, +- { 0x419ee4, 1, 0x04, 0x00000000 }, +- { 0x419ea4, 1, 0x04, 0x00000100 }, +- { 0x419ea8, 1, 0x04, 0x00000000 }, +- { 0x419eb4, 1, 0x04, 0x00000000 }, +- { 0x419ebc, 2, 0x04, 0x00000000 }, +- { 0x419edc, 1, 0x04, 0x00000000 }, +- { 0x419f00, 1, 0x04, 0x00000000 }, +- { 0x419ed0, 1, 0x04, 0x00003234 }, +- { 0x419f74, 1, 0x04, 0x00015555 }, +- { 0x419f80, 4, 0x04, 0x00000000 }, +- {} +-}; +- +-static const struct nvc0_graph_pack +-nvf0_graph_pack_mmio[] = { +- { nve4_graph_init_main_0 }, +- { nvf0_graph_init_fe_0 }, +- { nvc0_graph_init_pri_0 }, +- { nvc0_graph_init_rstr2d_0 }, +- { nvd9_graph_init_pd_0 }, +- { nvf0_graph_init_ds_0 }, +- { nvc0_graph_init_scc_0 }, +- { nvf0_graph_init_sked_0 }, +- { nvf0_graph_init_cwd_0 }, +- { nvd9_graph_init_prop_0 }, +- { nvc1_graph_init_gpc_unk_0 }, +- { nvc0_graph_init_setup_0 }, +- { nvc0_graph_init_crstr_0 }, +- { nvc1_graph_init_setup_1 }, +- { nvc0_graph_init_zcull_0 }, +- { nvd9_graph_init_gpm_0 }, +- { nvf0_graph_init_gpc_unk_1 }, +- { nvc0_graph_init_gcc_0 }, +- { nve4_graph_init_tpccs_0 }, +- { nvf0_graph_init_tex_0 }, +- { nve4_graph_init_pe_0 }, +- { nvf0_graph_init_l1c_0 }, +- { nvc0_graph_init_mpc_0 }, +- { nvf0_graph_init_sm_0 }, +- { nvd7_graph_init_pes_0 }, +- { nvd7_graph_init_wwdx_0 }, +- { nvd7_graph_init_cbm_0 }, +- { nve4_graph_init_be_0 }, +- { nvc0_graph_init_fe_1 }, +- {} +-}; +- +-/******************************************************************************* +- * PGRAPH engine/subdev functions +- ******************************************************************************/ +- +-int +-nvf0_graph_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvc0_graph_priv *priv = (void *)object; +- static const struct { +- u32 addr; +- u32 data; +- } magic[] = { +- { 0x020520, 0xfffffffc }, +- { 0x020524, 0xfffffffe }, +- { 0x020524, 0xfffffffc }, +- { 0x020524, 0xfffffff8 }, +- { 0x020524, 0xffffffe0 }, +- { 0x020530, 0xfffffffe }, +- { 0x02052c, 0xfffffffa }, +- { 0x02052c, 0xfffffff0 }, +- { 0x02052c, 0xffffffc0 }, +- { 0x02052c, 0xffffff00 }, +- { 0x02052c, 0xfffffc00 }, +- { 0x02052c, 0xfffcfc00 }, +- { 0x02052c, 0xfff0fc00 }, +- { 0x02052c, 0xff80fc00 }, +- { 0x020528, 0xfffffffe }, +- { 0x020528, 0xfffffffc }, +- }; +- int i; +- +- nv_mask(priv, 0x000200, 0x08001000, 0x00000000); +- nv_mask(priv, 0x0206b4, 0x00000000, 0x00000000); +- for (i = 0; i < ARRAY_SIZE(magic); i++) { +- nv_wr32(priv, magic[i].addr, magic[i].data); +- nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000); +- } +- +- return nouveau_graph_fini(&priv->base, suspend); +-} +- +-#include "fuc/hubnvf0.fuc.h" +- +-struct nvc0_graph_ucode +-nvf0_graph_fecs_ucode = { +- .code.data = nvf0_grhub_code, +- .code.size = sizeof(nvf0_grhub_code), +- .data.data = nvf0_grhub_data, +- .data.size = sizeof(nvf0_grhub_data), +-}; +- +-#include "fuc/gpcnvf0.fuc.h" +- +-struct nvc0_graph_ucode +-nvf0_graph_gpccs_ucode = { +- .code.data = nvf0_grgpc_code, +- .code.size = sizeof(nvf0_grgpc_code), +- .data.data = nvf0_grgpc_data, +- .data.size = sizeof(nvf0_grgpc_data), +-}; +- +-struct nouveau_oclass * +-nvf0_graph_oclass = &(struct nvc0_graph_oclass) { +- .base.handle = NV_ENGINE(GR, 0xf0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_graph_ctor, +- .dtor = nvc0_graph_dtor, +- .init = nve4_graph_init, +- .fini = nvf0_graph_fini, +- }, +- .cclass = &nvf0_grctx_oclass, +- .sclass = nvf0_graph_sclass, +- .mmio = nvf0_graph_pack_mmio, +- .fecs.ucode = &nvf0_graph_fecs_ucode, +- .gpccs.ucode = &nvf0_graph_gpccs_ucode, +- .ppc_nr = 2, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h b/drivers/gpu/drm/nouveau/core/engine/graph/regs.h +deleted file mode 100644 +index fde8e244..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/graph/regs.h ++++ /dev/null +@@ -1,274 +0,0 @@ +-#ifndef __NOUVEAU_GRAPH_REGS_H__ +-#define __NOUVEAU_GRAPH_REGS_H__ +- +-#define NV04_PGRAPH_DEBUG_0 0x00400080 +-#define NV04_PGRAPH_DEBUG_1 0x00400084 +-#define NV04_PGRAPH_DEBUG_2 0x00400088 +-#define NV04_PGRAPH_DEBUG_3 0x0040008c +-#define NV10_PGRAPH_DEBUG_4 0x00400090 +-#define NV03_PGRAPH_INTR 0x00400100 +-#define NV03_PGRAPH_NSTATUS 0x00400104 +-# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) +-# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) +-# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) +-# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) +-# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) +-# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) +-# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) +-# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) +-#define NV03_PGRAPH_NSOURCE 0x00400108 +-# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0) +-# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1) +-# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2) +-# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3) +-# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4) +-# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5) +-# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6) +-# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7) +-# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8) +-# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9) +-# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) +-# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) +-# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) +-# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) +-# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) +-# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) +-# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) +-# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) +-# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) +-#define NV03_PGRAPH_INTR_EN 0x00400140 +-#define NV40_PGRAPH_INTR_EN 0x0040013C +-# define NV_PGRAPH_INTR_NOTIFY (1<<0) +-# define NV_PGRAPH_INTR_MISSING_HW (1<<4) +-# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) +-# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) +-# define NV_PGRAPH_INTR_ERROR (1<<20) +-#define NV10_PGRAPH_CTX_CONTROL 0x00400144 +-#define NV10_PGRAPH_CTX_USER 0x00400148 +-#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i)) +-#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 +-#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \ +- + 0x4*(i) + 0x20*(j)) +-#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 +-#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 +-#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C +-#define NV04_PGRAPH_CTX_CONTROL 0x00400170 +-#define NV04_PGRAPH_CTX_USER 0x00400174 +-#define NV04_PGRAPH_CTX_CACHE1 0x00400180 +-#define NV03_PGRAPH_CTX_CONTROL 0x00400190 +-#define NV03_PGRAPH_CTX_USER 0x00400194 +-#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 +-#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 +-#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 +-#define NV40_PGRAPH_CTXCTL_0304 0x00400304 +-#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff +-#define NV40_PGRAPH_CTXCTL_0310 0x00400310 +-#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 +-#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 +-#define NV40_PGRAPH_CTXCTL_030C 0x0040030c +-#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 +-#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 +-#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c +-#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 +-#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF +-#define NV40_PGRAPH_CTXCTL_NEXT 0x00400330 +-#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff +-#define NV50_PGRAPH_CTXCTL_CUR 0x0040032c +-#define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000 +-#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff +-#define NV50_PGRAPH_CTXCTL_NEXT 0x00400330 +-#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff +-#define NV03_PGRAPH_ABS_X_RAM 0x00400400 +-#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 +-#define NV03_PGRAPH_X_MISC 0x00400500 +-#define NV03_PGRAPH_Y_MISC 0x00400504 +-#define NV04_PGRAPH_VALID1 0x00400508 +-#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C +-#define NV04_PGRAPH_MISC24_0 0x00400510 +-#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 +-#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 +-#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C +-#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 +-#define NV03_PGRAPH_CLIPX_0 0x00400524 +-#define NV03_PGRAPH_CLIPX_1 0x00400528 +-#define NV03_PGRAPH_CLIPY_0 0x0040052C +-#define NV03_PGRAPH_CLIPY_1 0x00400530 +-#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 +-#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 +-#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C +-#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 +-#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 +-#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 +-#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 +-#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 +-#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 +-#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C +-#define NV04_PGRAPH_MISC24_1 0x00400570 +-#define NV04_PGRAPH_MISC24_2 0x00400574 +-#define NV04_PGRAPH_VALID2 0x00400578 +-#define NV04_PGRAPH_PASSTHRU_0 0x0040057C +-#define NV04_PGRAPH_PASSTHRU_1 0x00400580 +-#define NV04_PGRAPH_PASSTHRU_2 0x00400584 +-#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 +-#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C +-#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 +-#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 +-#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 +-#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C +-#define NV04_PGRAPH_FORMAT_0 0x004005A8 +-#define NV04_PGRAPH_FORMAT_1 0x004005AC +-#define NV04_PGRAPH_FILTER_0 0x004005B0 +-#define NV04_PGRAPH_FILTER_1 0x004005B4 +-#define NV03_PGRAPH_MONO_COLOR0 0x00400600 +-#define NV04_PGRAPH_ROP3 0x00400604 +-#define NV04_PGRAPH_BETA_AND 0x00400608 +-#define NV04_PGRAPH_BETA_PREMULT 0x0040060C +-#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 +-#define NV04_PGRAPH_FORMATS 0x00400618 +-#define NV10_PGRAPH_DEBUG_2 0x00400620 +-#define NV04_PGRAPH_BOFFSET0 0x00400640 +-#define NV04_PGRAPH_BOFFSET1 0x00400644 +-#define NV04_PGRAPH_BOFFSET2 0x00400648 +-#define NV04_PGRAPH_BOFFSET3 0x0040064C +-#define NV04_PGRAPH_BOFFSET4 0x00400650 +-#define NV04_PGRAPH_BOFFSET5 0x00400654 +-#define NV04_PGRAPH_BBASE0 0x00400658 +-#define NV04_PGRAPH_BBASE1 0x0040065C +-#define NV04_PGRAPH_BBASE2 0x00400660 +-#define NV04_PGRAPH_BBASE3 0x00400664 +-#define NV04_PGRAPH_BBASE4 0x00400668 +-#define NV04_PGRAPH_BBASE5 0x0040066C +-#define NV04_PGRAPH_BPITCH0 0x00400670 +-#define NV04_PGRAPH_BPITCH1 0x00400674 +-#define NV04_PGRAPH_BPITCH2 0x00400678 +-#define NV04_PGRAPH_BPITCH3 0x0040067C +-#define NV04_PGRAPH_BPITCH4 0x00400680 +-#define NV04_PGRAPH_BLIMIT0 0x00400684 +-#define NV04_PGRAPH_BLIMIT1 0x00400688 +-#define NV04_PGRAPH_BLIMIT2 0x0040068C +-#define NV04_PGRAPH_BLIMIT3 0x00400690 +-#define NV04_PGRAPH_BLIMIT4 0x00400694 +-#define NV04_PGRAPH_BLIMIT5 0x00400698 +-#define NV04_PGRAPH_BSWIZZLE2 0x0040069C +-#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 +-#define NV03_PGRAPH_STATUS 0x004006B0 +-#define NV04_PGRAPH_STATUS 0x00400700 +-# define NV40_PGRAPH_STATUS_SYNC_STALL 0x00004000 +-#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 +-#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 +-#define NV04_PGRAPH_SURFACE 0x0040070C +-#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C +-#define NV04_PGRAPH_STATE 0x00400710 +-#define NV10_PGRAPH_SURFACE 0x00400710 +-#define NV04_PGRAPH_NOTIFY 0x00400714 +-#define NV10_PGRAPH_STATE 0x00400714 +-#define NV10_PGRAPH_NOTIFY 0x00400718 +- +-#define NV04_PGRAPH_FIFO 0x00400720 +- +-#define NV04_PGRAPH_BPIXEL 0x00400724 +-#define NV10_PGRAPH_RDI_INDEX 0x00400750 +-#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 +-#define NV10_PGRAPH_RDI_DATA 0x00400754 +-#define NV04_PGRAPH_DMA_PITCH 0x00400760 +-#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760 +-#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 +-#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 +-#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 +-#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768 +-#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c +-#define NV10_PGRAPH_DMA_PITCH 0x00400770 +-#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 +-#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 +-#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 +-#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 +-#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 +-#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 +-#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 +-#define NV04_PGRAPH_PATT_COLOR0 0x00400800 +-#define NV04_PGRAPH_PATT_COLOR1 0x00400804 +-#define NV04_PGRAPH_PATTERN 0x00400808 +-#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 +-#define NV04_PGRAPH_CHROMA 0x00400814 +-#define NV04_PGRAPH_CONTROL0 0x00400818 +-#define NV04_PGRAPH_CONTROL1 0x0040081C +-#define NV04_PGRAPH_CONTROL2 0x00400820 +-#define NV04_PGRAPH_BLEND 0x00400824 +-#define NV04_PGRAPH_STORED_FMT 0x00400830 +-#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 +-#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16)) +-#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16)) +-#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16)) +-#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16)) +-#define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i)) +-#define NV41_PGRAPH_ZCOMP0(i) (0x004009c0 + 4*(i)) +-#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) +-#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) +-#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) +-#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) +-#define NV04_PGRAPH_U_RAM 0x00400D00 +-#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16)) +-#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16)) +-#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16)) +-#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16)) +-#define NV04_PGRAPH_V_RAM 0x00400D40 +-#define NV04_PGRAPH_W_RAM 0x00400D80 +-#define NV47_PGRAPH_ZCOMP0(i) (0x00400e00 + 4*(i)) +-#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 +-#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 +-#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 +-#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C +-#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 +-#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 +-#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 +-#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C +-#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 +-#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 +-#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 +-#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C +-#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 +-#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 +-#define NV10_PGRAPH_XFMODE0 0x00400F40 +-#define NV10_PGRAPH_XFMODE1 0x00400F44 +-#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 +-#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C +-#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 +-#define NV10_PGRAPH_PIPE_DATA 0x00400F54 +-#define NV04_PGRAPH_DMA_START_0 0x00401000 +-#define NV04_PGRAPH_DMA_START_1 0x00401004 +-#define NV04_PGRAPH_DMA_LENGTH 0x00401008 +-#define NV04_PGRAPH_DMA_MISC 0x0040100C +-#define NV04_PGRAPH_DMA_DATA_0 0x00401020 +-#define NV04_PGRAPH_DMA_DATA_1 0x00401024 +-#define NV04_PGRAPH_DMA_RM 0x00401030 +-#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 +-#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 +-#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 +-#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C +-#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 +-#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 +-#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 +-#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C +-#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 +-#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 +-#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 +-#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 +-#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C +-#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 +-#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 +-#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 +-#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C +-#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 +-#define NV47_PGRAPH_ZCOMP1(i) (0x004068c0 + 4*(i)) +-#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) +-#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) +-#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) +-#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) +-#define NV40_PGRAPH_ZCOMP1(i) (0x00406980 + 4*(i)) +-#define NV41_PGRAPH_ZCOMP1(i) (0x004069c0 + 4*(i)) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c +deleted file mode 100644 +index d88c700b..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c ++++ /dev/null +@@ -1,309 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-/******************************************************************************* +- * MPEG object classes +- ******************************************************************************/ +- +-static int +-nv31_mpeg_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj *obj; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, +- 20, 16, 0, &obj); +- *pobject = nv_object(obj); +- if (ret) +- return ret; +- +- nv_wo32(obj, 0x00, nv_mclass(obj)); +- nv_wo32(obj, 0x04, 0x00000000); +- nv_wo32(obj, 0x08, 0x00000000); +- nv_wo32(obj, 0x0c, 0x00000000); +- return 0; +-} +- +-static int +-nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) +-{ +- struct nouveau_instmem *imem = nouveau_instmem(object); +- struct nv31_mpeg_priv *priv = (void *)object->engine; +- u32 inst = *(u32 *)arg << 4; +- u32 dma0 = nv_ro32(imem, inst + 0); +- u32 dma1 = nv_ro32(imem, inst + 4); +- u32 dma2 = nv_ro32(imem, inst + 8); +- u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); +- u32 size = dma1 + 1; +- +- /* only allow linear DMA objects */ +- if (!(dma0 & 0x00002000)) +- return -EINVAL; +- +- if (mthd == 0x0190) { +- /* DMA_CMD */ +- nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0); +- nv_wr32(priv, 0x00b334, base); +- nv_wr32(priv, 0x00b324, size); +- } else +- if (mthd == 0x01a0) { +- /* DMA_DATA */ +- nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0); +- nv_wr32(priv, 0x00b360, base); +- nv_wr32(priv, 0x00b364, size); +- } else { +- /* DMA_IMAGE, VRAM only */ +- if (dma0 & 0x00030000) +- return -EINVAL; +- +- nv_wr32(priv, 0x00b370, base); +- nv_wr32(priv, 0x00b374, size); +- } +- +- return 0; +-} +- +-struct nouveau_ofuncs +-nv31_mpeg_ofuncs = { +- .ctor = nv31_mpeg_object_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +-}; +- +-static struct nouveau_omthds +-nv31_mpeg_omthds[] = { +- { 0x0190, 0x0190, nv31_mpeg_mthd_dma }, +- { 0x01a0, 0x01a0, nv31_mpeg_mthd_dma }, +- { 0x01b0, 0x01b0, nv31_mpeg_mthd_dma }, +- {} +-}; +- +-struct nouveau_oclass +-nv31_mpeg_sclass[] = { +- { 0x3174, &nv31_mpeg_ofuncs, nv31_mpeg_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PMPEG context +- ******************************************************************************/ +- +-static int +-nv31_mpeg_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv31_mpeg_priv *priv = (void *)engine; +- struct nv31_mpeg_chan *chan; +- unsigned long flags; +- int ret; +- +- ret = nouveau_object_create(parent, engine, oclass, 0, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- spin_lock_irqsave(&nv_engine(priv)->lock, flags); +- if (priv->chan) { +- spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); +- nouveau_object_destroy(&chan->base); +- *pobject = NULL; +- return -EBUSY; +- } +- priv->chan = chan; +- spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); +- return 0; +-} +- +-static void +-nv31_mpeg_context_dtor(struct nouveau_object *object) +-{ +- struct nv31_mpeg_priv *priv = (void *)object->engine; +- struct nv31_mpeg_chan *chan = (void *)object; +- unsigned long flags; +- +- spin_lock_irqsave(&nv_engine(priv)->lock, flags); +- priv->chan = NULL; +- spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); +- nouveau_object_destroy(&chan->base); +-} +- +-struct nouveau_oclass +-nv31_mpeg_cclass = { +- .handle = NV_ENGCTX(MPEG, 0x31), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv31_mpeg_context_ctor, +- .dtor = nv31_mpeg_context_dtor, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- }, +-}; +- +-/******************************************************************************* +- * PMPEG engine/subdev functions +- ******************************************************************************/ +- +-void +-nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i) +-{ +- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i]; +- struct nv31_mpeg_priv *priv = (void *)engine; +- +- nv_wr32(priv, 0x00b008 + (i * 0x10), tile->pitch); +- nv_wr32(priv, 0x00b004 + (i * 0x10), tile->limit); +- nv_wr32(priv, 0x00b000 + (i * 0x10), tile->addr); +-} +- +-void +-nv31_mpeg_intr(struct nouveau_subdev *subdev) +-{ +- struct nv31_mpeg_priv *priv = (void *)subdev; +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_handle *handle; +- struct nouveau_object *engctx; +- u32 stat = nv_rd32(priv, 0x00b100); +- u32 type = nv_rd32(priv, 0x00b230); +- u32 mthd = nv_rd32(priv, 0x00b234); +- u32 data = nv_rd32(priv, 0x00b238); +- u32 show = stat; +- unsigned long flags; +- +- spin_lock_irqsave(&nv_engine(priv)->lock, flags); +- engctx = nv_object(priv->chan); +- +- if (stat & 0x01000000) { +- /* happens on initial binding of the object */ +- if (type == 0x00000020 && mthd == 0x0000) { +- nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); +- show &= ~0x01000000; +- } +- +- if (type == 0x00000010 && engctx) { +- handle = nouveau_handle_get_class(engctx, 0x3174); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~0x01000000; +- nouveau_handle_put(handle); +- } +- } +- +- nv_wr32(priv, 0x00b100, stat); +- nv_wr32(priv, 0x00b230, 0x00000001); +- +- if (show) { +- nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n", +- pfifo->chid(pfifo, engctx), +- nouveau_client_name(engctx), stat, type, mthd, data); +- } +- +- spin_unlock_irqrestore(&nv_engine(priv)->lock, flags); +-} +- +-static int +-nv31_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv31_mpeg_priv *priv; +- int ret; +- +- ret = nouveau_mpeg_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000002; +- nv_subdev(priv)->intr = nv31_mpeg_intr; +- nv_engine(priv)->cclass = &nv31_mpeg_cclass; +- nv_engine(priv)->sclass = nv31_mpeg_sclass; +- nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; +- return 0; +-} +- +-int +-nv31_mpeg_init(struct nouveau_object *object) +-{ +- struct nouveau_engine *engine = nv_engine(object); +- struct nv31_mpeg_priv *priv = (void *)object; +- struct nouveau_fb *pfb = nouveau_fb(object); +- int ret, i; +- +- ret = nouveau_mpeg_init(&priv->base); +- if (ret) +- return ret; +- +- /* VPE init */ +- nv_wr32(priv, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ +- nv_wr32(priv, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */ +- +- for (i = 0; i < pfb->tile.regions; i++) +- engine->tile_prog(engine, i); +- +- /* PMPEG init */ +- nv_wr32(priv, 0x00b32c, 0x00000000); +- nv_wr32(priv, 0x00b314, 0x00000100); +- nv_wr32(priv, 0x00b220, 0x00000031); +- nv_wr32(priv, 0x00b300, 0x02001ec1); +- nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); +- +- nv_wr32(priv, 0x00b100, 0xffffffff); +- nv_wr32(priv, 0x00b140, 0xffffffff); +- +- if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) { +- nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); +- return -EBUSY; +- } +- +- return 0; +-} +- +-struct nouveau_oclass +-nv31_mpeg_oclass = { +- .handle = NV_ENGINE(MPEG, 0x31), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv31_mpeg_ctor, +- .dtor = _nouveau_mpeg_dtor, +- .init = nv31_mpeg_init, +- .fini = _nouveau_mpeg_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h +deleted file mode 100644 +index d08629d0..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-#ifndef __NV31_MPEG_H__ +-#define __NV31_MPEG_H__ +- +-#include +- +-struct nv31_mpeg_chan { +- struct nouveau_object base; +-}; +- +-struct nv31_mpeg_priv { +- struct nouveau_mpeg base; +- struct nv31_mpeg_chan *chan; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c +deleted file mode 100644 +index bdb2f20f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +-#include +- +-#include +-#include +- +-/******************************************************************************* +- * MPEG object classes +- ******************************************************************************/ +- +-static int +-nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len) +-{ +- struct nouveau_instmem *imem = nouveau_instmem(object); +- struct nv31_mpeg_priv *priv = (void *)object->engine; +- u32 inst = *(u32 *)arg << 4; +- u32 dma0 = nv_ro32(imem, inst + 0); +- u32 dma1 = nv_ro32(imem, inst + 4); +- u32 dma2 = nv_ro32(imem, inst + 8); +- u32 base = (dma2 & 0xfffff000) | (dma0 >> 20); +- u32 size = dma1 + 1; +- +- /* only allow linear DMA objects */ +- if (!(dma0 & 0x00002000)) +- return -EINVAL; +- +- if (mthd == 0x0190) { +- /* DMA_CMD */ +- nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000)); +- nv_wr32(priv, 0x00b334, base); +- nv_wr32(priv, 0x00b324, size); +- } else +- if (mthd == 0x01a0) { +- /* DMA_DATA */ +- nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2); +- nv_wr32(priv, 0x00b360, base); +- nv_wr32(priv, 0x00b364, size); +- } else { +- /* DMA_IMAGE, VRAM only */ +- if (dma0 & 0x00030000) +- return -EINVAL; +- +- nv_wr32(priv, 0x00b370, base); +- nv_wr32(priv, 0x00b374, size); +- } +- +- return 0; +-} +- +-static struct nouveau_omthds +-nv40_mpeg_omthds[] = { +- { 0x0190, 0x0190, nv40_mpeg_mthd_dma }, +- { 0x01a0, 0x01a0, nv40_mpeg_mthd_dma }, +- { 0x01b0, 0x01b0, nv40_mpeg_mthd_dma }, +- {} +-}; +- +-struct nouveau_oclass +-nv40_mpeg_sclass[] = { +- { 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * PMPEG engine/subdev functions +- ******************************************************************************/ +- +-static void +-nv40_mpeg_intr(struct nouveau_subdev *subdev) +-{ +- struct nv31_mpeg_priv *priv = (void *)subdev; +- u32 stat; +- +- if ((stat = nv_rd32(priv, 0x00b100))) +- nv31_mpeg_intr(subdev); +- +- if ((stat = nv_rd32(priv, 0x00b800))) { +- nv_error(priv, "PMSRCH 0x%08x\n", stat); +- nv_wr32(priv, 0x00b800, stat); +- } +-} +- +-static int +-nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv31_mpeg_priv *priv; +- int ret; +- +- ret = nouveau_mpeg_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000002; +- nv_subdev(priv)->intr = nv40_mpeg_intr; +- nv_engine(priv)->cclass = &nv31_mpeg_cclass; +- nv_engine(priv)->sclass = nv40_mpeg_sclass; +- nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv40_mpeg_oclass = { +- .handle = NV_ENGINE(MPEG, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_mpeg_ctor, +- .dtor = _nouveau_mpeg_dtor, +- .init = nv31_mpeg_init, +- .fini = _nouveau_mpeg_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c +deleted file mode 100644 +index 72c7f33f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c ++++ /dev/null +@@ -1,193 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +-#include +- +-struct nv44_mpeg_priv { +- struct nouveau_mpeg base; +-}; +- +-struct nv44_mpeg_chan { +- struct nouveau_mpeg_chan base; +-}; +- +-/******************************************************************************* +- * PMPEG context +- ******************************************************************************/ +- +-static int +-nv44_mpeg_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv44_mpeg_chan *chan; +- int ret; +- +- ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL, +- 264 * 4, 16, +- NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- nv_wo32(&chan->base.base, 0x78, 0x02001ec1); +- return 0; +-} +- +-static int +-nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend) +-{ +- +- struct nv44_mpeg_priv *priv = (void *)object->engine; +- struct nv44_mpeg_chan *chan = (void *)object; +- u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4; +- +- nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000); +- if (nv_rd32(priv, 0x00b318) == inst) +- nv_mask(priv, 0x00b318, 0x80000000, 0x00000000); +- nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); +- return 0; +-} +- +-static struct nouveau_oclass +-nv44_mpeg_cclass = { +- .handle = NV_ENGCTX(MPEG, 0x44), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv44_mpeg_context_ctor, +- .dtor = _nouveau_mpeg_context_dtor, +- .init = _nouveau_mpeg_context_init, +- .fini = nv44_mpeg_context_fini, +- .rd32 = _nouveau_mpeg_context_rd32, +- .wr32 = _nouveau_mpeg_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PMPEG engine/subdev functions +- ******************************************************************************/ +- +-static void +-nv44_mpeg_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(subdev); +- struct nouveau_engine *engine = nv_engine(subdev); +- struct nouveau_object *engctx; +- struct nouveau_handle *handle; +- struct nv44_mpeg_priv *priv = (void *)subdev; +- u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff; +- u32 stat = nv_rd32(priv, 0x00b100); +- u32 type = nv_rd32(priv, 0x00b230); +- u32 mthd = nv_rd32(priv, 0x00b234); +- u32 data = nv_rd32(priv, 0x00b238); +- u32 show = stat; +- int chid; +- +- engctx = nouveau_engctx_get(engine, inst); +- chid = pfifo->chid(pfifo, engctx); +- +- if (stat & 0x01000000) { +- /* happens on initial binding of the object */ +- if (type == 0x00000020 && mthd == 0x0000) { +- nv_mask(priv, 0x00b308, 0x00000000, 0x00000000); +- show &= ~0x01000000; +- } +- +- if (type == 0x00000010) { +- handle = nouveau_handle_get_class(engctx, 0x3174); +- if (handle && !nv_call(handle->object, mthd, data)) +- show &= ~0x01000000; +- nouveau_handle_put(handle); +- } +- } +- +- nv_wr32(priv, 0x00b100, stat); +- nv_wr32(priv, 0x00b230, 0x00000001); +- +- if (show) { +- nv_error(priv, +- "ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n", +- chid, inst << 4, nouveau_client_name(engctx), stat, +- type, mthd, data); +- } +- +- nouveau_engctx_put(engctx); +-} +- +-static void +-nv44_mpeg_me_intr(struct nouveau_subdev *subdev) +-{ +- struct nv44_mpeg_priv *priv = (void *)subdev; +- u32 stat; +- +- if ((stat = nv_rd32(priv, 0x00b100))) +- nv44_mpeg_intr(subdev); +- +- if ((stat = nv_rd32(priv, 0x00b800))) { +- nv_error(priv, "PMSRCH 0x%08x\n", stat); +- nv_wr32(priv, 0x00b800, stat); +- } +-} +- +-static int +-nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv44_mpeg_priv *priv; +- int ret; +- +- ret = nouveau_mpeg_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000002; +- nv_subdev(priv)->intr = nv44_mpeg_me_intr; +- nv_engine(priv)->cclass = &nv44_mpeg_cclass; +- nv_engine(priv)->sclass = nv40_mpeg_sclass; +- nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv44_mpeg_oclass = { +- .handle = NV_ENGINE(MPEG, 0x44), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv44_mpeg_ctor, +- .dtor = _nouveau_mpeg_dtor, +- .init = nv31_mpeg_init, +- .fini = _nouveau_mpeg_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c +deleted file mode 100644 +index cae33f86..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv50.c ++++ /dev/null +@@ -1,230 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-struct nv50_mpeg_priv { +- struct nouveau_mpeg base; +-}; +- +-struct nv50_mpeg_chan { +- struct nouveau_mpeg_chan base; +-}; +- +-/******************************************************************************* +- * MPEG object classes +- ******************************************************************************/ +- +-static int +-nv50_mpeg_object_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpuobj *obj; +- int ret; +- +- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent, +- 16, 16, 0, &obj); +- *pobject = nv_object(obj); +- if (ret) +- return ret; +- +- nv_wo32(obj, 0x00, nv_mclass(obj)); +- nv_wo32(obj, 0x04, 0x00000000); +- nv_wo32(obj, 0x08, 0x00000000); +- nv_wo32(obj, 0x0c, 0x00000000); +- return 0; +-} +- +-struct nouveau_ofuncs +-nv50_mpeg_ofuncs = { +- .ctor = nv50_mpeg_object_ctor, +- .dtor = _nouveau_gpuobj_dtor, +- .init = _nouveau_gpuobj_init, +- .fini = _nouveau_gpuobj_fini, +- .rd32 = _nouveau_gpuobj_rd32, +- .wr32 = _nouveau_gpuobj_wr32, +-}; +- +-static struct nouveau_oclass +-nv50_mpeg_sclass[] = { +- { 0x3174, &nv50_mpeg_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * PMPEG context +- ******************************************************************************/ +- +-int +-nv50_mpeg_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_bar *bar = nouveau_bar(parent); +- struct nv50_mpeg_chan *chan; +- int ret; +- +- ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL, 128 * 4, +- 0, NVOBJ_FLAG_ZERO_ALLOC, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- nv_wo32(chan, 0x0070, 0x00801ec1); +- nv_wo32(chan, 0x007c, 0x0000037c); +- bar->flush(bar); +- return 0; +-} +- +-static struct nouveau_oclass +-nv50_mpeg_cclass = { +- .handle = NV_ENGCTX(MPEG, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_mpeg_context_ctor, +- .dtor = _nouveau_mpeg_context_dtor, +- .init = _nouveau_mpeg_context_init, +- .fini = _nouveau_mpeg_context_fini, +- .rd32 = _nouveau_mpeg_context_rd32, +- .wr32 = _nouveau_mpeg_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PMPEG engine/subdev functions +- ******************************************************************************/ +- +-void +-nv50_mpeg_intr(struct nouveau_subdev *subdev) +-{ +- struct nv50_mpeg_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, 0x00b100); +- u32 type = nv_rd32(priv, 0x00b230); +- u32 mthd = nv_rd32(priv, 0x00b234); +- u32 data = nv_rd32(priv, 0x00b238); +- u32 show = stat; +- +- if (stat & 0x01000000) { +- /* happens on initial binding of the object */ +- if (type == 0x00000020 && mthd == 0x0000) { +- nv_wr32(priv, 0x00b308, 0x00000100); +- show &= ~0x01000000; +- } +- } +- +- if (show) { +- nv_info(priv, "0x%08x 0x%08x 0x%08x 0x%08x\n", +- stat, type, mthd, data); +- } +- +- nv_wr32(priv, 0x00b100, stat); +- nv_wr32(priv, 0x00b230, 0x00000001); +-} +- +-static void +-nv50_vpe_intr(struct nouveau_subdev *subdev) +-{ +- struct nv50_mpeg_priv *priv = (void *)subdev; +- +- if (nv_rd32(priv, 0x00b100)) +- nv50_mpeg_intr(subdev); +- +- if (nv_rd32(priv, 0x00b800)) { +- u32 stat = nv_rd32(priv, 0x00b800); +- nv_info(priv, "PMSRCH: 0x%08x\n", stat); +- nv_wr32(priv, 0xb800, stat); +- } +-} +- +-static int +-nv50_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_mpeg_priv *priv; +- int ret; +- +- ret = nouveau_mpeg_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00400002; +- nv_subdev(priv)->intr = nv50_vpe_intr; +- nv_engine(priv)->cclass = &nv50_mpeg_cclass; +- nv_engine(priv)->sclass = nv50_mpeg_sclass; +- return 0; +-} +- +-int +-nv50_mpeg_init(struct nouveau_object *object) +-{ +- struct nv50_mpeg_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_mpeg_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x00b32c, 0x00000000); +- nv_wr32(priv, 0x00b314, 0x00000100); +- nv_wr32(priv, 0x00b0e0, 0x0000001a); +- +- nv_wr32(priv, 0x00b220, 0x00000044); +- nv_wr32(priv, 0x00b300, 0x00801ec1); +- nv_wr32(priv, 0x00b390, 0x00000000); +- nv_wr32(priv, 0x00b394, 0x00000000); +- nv_wr32(priv, 0x00b398, 0x00000000); +- nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001); +- +- nv_wr32(priv, 0x00b100, 0xffffffff); +- nv_wr32(priv, 0x00b140, 0xffffffff); +- +- if (!nv_wait(priv, 0x00b200, 0x00000001, 0x00000000)) { +- nv_error(priv, "timeout 0x%08x\n", nv_rd32(priv, 0x00b200)); +- return -EBUSY; +- } +- +- return 0; +-} +- +-struct nouveau_oclass +-nv50_mpeg_oclass = { +- .handle = NV_ENGINE(MPEG, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_mpeg_ctor, +- .dtor = _nouveau_mpeg_dtor, +- .init = nv50_mpeg_init, +- .fini = _nouveau_mpeg_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c +deleted file mode 100644 +index e9cc8b11..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv84.c ++++ /dev/null +@@ -1,102 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-struct nv84_mpeg_priv { +- struct nouveau_mpeg base; +-}; +- +-struct nv84_mpeg_chan { +- struct nouveau_mpeg_chan base; +-}; +- +-/******************************************************************************* +- * MPEG object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_mpeg_sclass[] = { +- { 0x8274, &nv50_mpeg_ofuncs }, +- {} +-}; +- +-/******************************************************************************* +- * PMPEG context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_mpeg_cclass = { +- .handle = NV_ENGCTX(MPEG, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_mpeg_context_ctor, +- .dtor = _nouveau_mpeg_context_dtor, +- .init = _nouveau_mpeg_context_init, +- .fini = _nouveau_mpeg_context_fini, +- .rd32 = _nouveau_mpeg_context_rd32, +- .wr32 = _nouveau_mpeg_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PMPEG engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv84_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv84_mpeg_priv *priv; +- int ret; +- +- ret = nouveau_mpeg_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000002; +- nv_subdev(priv)->intr = nv50_mpeg_intr; +- nv_engine(priv)->cclass = &nv84_mpeg_cclass; +- nv_engine(priv)->sclass = nv84_mpeg_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nv84_mpeg_oclass = { +- .handle = NV_ENGINE(MPEG, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_mpeg_ctor, +- .dtor = _nouveau_mpeg_dtor, +- .init = nv50_mpeg_init, +- .fini = _nouveau_mpeg_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c +deleted file mode 100644 +index 63013812..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/base.c ++++ /dev/null +@@ -1,483 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include "priv.h" +- +-#define QUAD_MASK 0x0f +-#define QUAD_FREE 0x01 +- +-static struct nouveau_perfsig * +-nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size) +-{ +- char path[64]; +- int i; +- +- if (name[0] != '/') { +- for (i = 0; i < dom->signal_nr; i++) { +- if ( dom->signal[i].name && +- !strncmp(name, dom->signal[i].name, size)) +- return &dom->signal[i]; +- } +- } else { +- for (i = 0; i < dom->signal_nr; i++) { +- snprintf(path, sizeof(path), "/%s/%02x", dom->name, i); +- if (!strncmp(name, path, size)) +- return &dom->signal[i]; +- } +- } +- +- return NULL; +-} +- +-struct nouveau_perfsig * +-nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size, +- struct nouveau_perfdom **pdom) +-{ +- struct nouveau_perfdom *dom = *pdom; +- struct nouveau_perfsig *sig; +- +- if (dom == NULL) { +- list_for_each_entry(dom, &ppm->domains, head) { +- sig = nouveau_perfsig_find_(dom, name, size); +- if (sig) { +- *pdom = dom; +- return sig; +- } +- } +- +- return NULL; +- } +- +- return nouveau_perfsig_find_(dom, name, size); +-} +- +-struct nouveau_perfctr * +-nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name, +- struct nouveau_perfdom **pdom) +-{ +- struct nouveau_perfsig *sig; +- struct nouveau_perfctr *ctr; +- +- sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom); +- if (!sig) +- return NULL; +- +- ctr = kzalloc(sizeof(*ctr), GFP_KERNEL); +- if (ctr) { +- ctr->signal[0] = sig; +- ctr->logic_op = 0xaaaa; +- } +- +- return ctr; +-} +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +-static int +-nouveau_perfctr_query(struct nouveau_object *object, void *data, u32 size) +-{ +- union { +- struct nvif_perfctr_query_v0 v0; +- } *args = data; +- struct nouveau_device *device = nv_device(object); +- struct nouveau_perfmon *ppm = (void *)object->engine; +- struct nouveau_perfdom *dom = NULL, *chk; +- const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false); +- const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all); +- const char *name; +- int tmp = 0, di, si; +- int ret; +- +- nv_ioctl(object, "perfctr query size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "perfctr query vers %d iter %08x\n", +- args->v0.version, args->v0.iter); +- di = (args->v0.iter & 0xff000000) >> 24; +- si = (args->v0.iter & 0x00ffffff) - 1; +- } else +- return ret; +- +- list_for_each_entry(chk, &ppm->domains, head) { +- if (tmp++ == di) { +- dom = chk; +- break; +- } +- } +- +- if (dom == NULL || si >= (int)dom->signal_nr) +- return -EINVAL; +- +- if (si >= 0) { +- if (raw || !(name = dom->signal[si].name)) { +- snprintf(args->v0.name, sizeof(args->v0.name), +- "/%s/%02x", dom->name, si); +- } else { +- strncpy(args->v0.name, name, sizeof(args->v0.name)); +- } +- } +- +- do { +- while (++si < dom->signal_nr) { +- if (all || dom->signal[si].name) { +- args->v0.iter = (di << 24) | ++si; +- return 0; +- } +- } +- si = -1; +- di = di + 1; +- dom = list_entry(dom->head.next, typeof(*dom), head); +- } while (&dom->head != &ppm->domains); +- +- args->v0.iter = 0xffffffff; +- return 0; +-} +- +-static int +-nouveau_perfctr_sample(struct nouveau_object *object, void *data, u32 size) +-{ +- union { +- struct nvif_perfctr_sample none; +- } *args = data; +- struct nouveau_perfmon *ppm = (void *)object->engine; +- struct nouveau_perfctr *ctr, *tmp; +- struct nouveau_perfdom *dom; +- int ret; +- +- nv_ioctl(object, "perfctr sample size %d\n", size); +- if (nvif_unvers(args->none)) { +- nv_ioctl(object, "perfctr sample\n"); +- } else +- return ret; +- ppm->sequence++; +- +- list_for_each_entry(dom, &ppm->domains, head) { +- /* sample previous batch of counters */ +- if (dom->quad != QUAD_MASK) { +- dom->func->next(ppm, dom); +- tmp = NULL; +- while (!list_empty(&dom->list)) { +- ctr = list_first_entry(&dom->list, +- typeof(*ctr), head); +- if (ctr->slot < 0) break; +- if ( tmp && tmp == ctr) break; +- if (!tmp) tmp = ctr; +- dom->func->read(ppm, dom, ctr); +- ctr->slot = -1; +- list_move_tail(&ctr->head, &dom->list); +- } +- } +- +- dom->quad = QUAD_MASK; +- +- /* setup next batch of counters for sampling */ +- list_for_each_entry(ctr, &dom->list, head) { +- ctr->slot = ffs(dom->quad) - 1; +- if (ctr->slot < 0) +- break; +- dom->quad &= ~(QUAD_FREE << ctr->slot); +- dom->func->init(ppm, dom, ctr); +- } +- +- if (dom->quad != QUAD_MASK) +- dom->func->next(ppm, dom); +- } +- +- return 0; +-} +- +-static int +-nouveau_perfctr_read(struct nouveau_object *object, void *data, u32 size) +-{ +- union { +- struct nvif_perfctr_read_v0 v0; +- } *args = data; +- struct nouveau_perfctr *ctr = (void *)object; +- int ret; +- +- nv_ioctl(object, "perfctr read size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(object, "perfctr read vers %d\n", args->v0.version); +- } else +- return ret; +- +- if (!ctr->clk) +- return -EAGAIN; +- +- args->v0.clk = ctr->clk; +- args->v0.ctr = ctr->ctr; +- return 0; +-} +- +-static int +-nouveau_perfctr_mthd(struct nouveau_object *object, u32 mthd, +- void *data, u32 size) +-{ +- switch (mthd) { +- case NVIF_PERFCTR_V0_QUERY: +- return nouveau_perfctr_query(object, data, size); +- case NVIF_PERFCTR_V0_SAMPLE: +- return nouveau_perfctr_sample(object, data, size); +- case NVIF_PERFCTR_V0_READ: +- return nouveau_perfctr_read(object, data, size); +- default: +- break; +- } +- return -EINVAL; +-} +- +-static void +-nouveau_perfctr_dtor(struct nouveau_object *object) +-{ +- struct nouveau_perfctr *ctr = (void *)object; +- if (ctr->head.next) +- list_del(&ctr->head); +- nouveau_object_destroy(&ctr->base); +-} +- +-static int +-nouveau_perfctr_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- union { +- struct nvif_perfctr_v0 v0; +- } *args = data; +- struct nouveau_perfmon *ppm = (void *)engine; +- struct nouveau_perfdom *dom = NULL; +- struct nouveau_perfsig *sig[4] = {}; +- struct nouveau_perfctr *ctr; +- int ret, i; +- +- nv_ioctl(parent, "create perfctr size %d\n", size); +- if (nvif_unpack(args->v0, 0, 0, false)) { +- nv_ioctl(parent, "create perfctr vers %d logic_op %04x\n", +- args->v0.version, args->v0.logic_op); +- } else +- return ret; +- +- for (i = 0; i < ARRAY_SIZE(args->v0.name) && args->v0.name[i][0]; i++) { +- sig[i] = nouveau_perfsig_find(ppm, args->v0.name[i], +- strnlen(args->v0.name[i], +- sizeof(args->v0.name[i])), +- &dom); +- if (!sig[i]) +- return -EINVAL; +- } +- +- ret = nouveau_object_create(parent, engine, oclass, 0, &ctr); +- *pobject = nv_object(ctr); +- if (ret) +- return ret; +- +- ctr->slot = -1; +- ctr->logic_op = args->v0.logic_op; +- ctr->signal[0] = sig[0]; +- ctr->signal[1] = sig[1]; +- ctr->signal[2] = sig[2]; +- ctr->signal[3] = sig[3]; +- if (dom) +- list_add_tail(&ctr->head, &dom->list); +- return 0; +-} +- +-static struct nouveau_ofuncs +-nouveau_perfctr_ofuncs = { +- .ctor = nouveau_perfctr_ctor, +- .dtor = nouveau_perfctr_dtor, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- .mthd = nouveau_perfctr_mthd, +-}; +- +-struct nouveau_oclass +-nouveau_perfmon_sclass[] = { +- { .handle = NVIF_IOCTL_NEW_V0_PERFCTR, +- .ofuncs = &nouveau_perfctr_ofuncs, +- }, +- {}, +-}; +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +-static void +-nouveau_perfctx_dtor(struct nouveau_object *object) +-{ +- struct nouveau_perfmon *ppm = (void *)object->engine; +- mutex_lock(&nv_subdev(ppm)->mutex); +- nouveau_engctx_destroy(&ppm->context->base); +- ppm->context = NULL; +- mutex_unlock(&nv_subdev(ppm)->mutex); +-} +- +-static int +-nouveau_perfctx_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_perfmon *ppm = (void *)engine; +- struct nouveau_perfctx *ctx; +- int ret; +- +- ret = nouveau_engctx_create(parent, engine, oclass, NULL, +- 0, 0, 0, &ctx); +- *pobject = nv_object(ctx); +- if (ret) +- return ret; +- +- mutex_lock(&nv_subdev(ppm)->mutex); +- if (ppm->context == NULL) +- ppm->context = ctx; +- mutex_unlock(&nv_subdev(ppm)->mutex); +- +- if (ctx != ppm->context) +- return -EBUSY; +- +- return 0; +-} +- +-struct nouveau_oclass +-nouveau_perfmon_cclass = { +- .handle = NV_ENGCTX(PERFMON, 0x00), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nouveau_perfctx_ctor, +- .dtor = nouveau_perfctx_dtor, +- .init = _nouveau_engctx_init, +- .fini = _nouveau_engctx_fini, +- }, +-}; +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +-int +-nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask, +- u32 base, u32 size_unit, u32 size_domain, +- const struct nouveau_specdom *spec) +-{ +- const struct nouveau_specdom *sdom; +- const struct nouveau_specsig *ssig; +- struct nouveau_perfdom *dom; +- int i; +- +- for (i = 0; i == 0 || mask; i++) { +- u32 addr = base + (i * size_unit); +- if (i && !(mask & (1 << i))) +- continue; +- +- sdom = spec; +- while (sdom->signal_nr) { +- dom = kzalloc(sizeof(*dom) + sdom->signal_nr * +- sizeof(*dom->signal), GFP_KERNEL); +- if (!dom) +- return -ENOMEM; +- +- if (mask) { +- snprintf(dom->name, sizeof(dom->name), +- "%s/%02x/%02x", name, i, +- (int)(sdom - spec)); +- } else { +- snprintf(dom->name, sizeof(dom->name), +- "%s/%02x", name, (int)(sdom - spec)); +- } +- +- list_add_tail(&dom->head, &ppm->domains); +- INIT_LIST_HEAD(&dom->list); +- dom->func = sdom->func; +- dom->addr = addr; +- dom->quad = QUAD_MASK; +- dom->signal_nr = sdom->signal_nr; +- +- ssig = (sdom++)->signal; +- while (ssig->name) { +- dom->signal[ssig->signal].name = ssig->name; +- ssig++; +- } +- +- addr += size_domain; +- } +- +- mask &= ~(1 << i); +- } +- +- return 0; +-} +- +-int +-_nouveau_perfmon_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_perfmon *ppm = (void *)object; +- return nouveau_engine_fini(&ppm->base, suspend); +-} +- +-int +-_nouveau_perfmon_init(struct nouveau_object *object) +-{ +- struct nouveau_perfmon *ppm = (void *)object; +- return nouveau_engine_init(&ppm->base); +-} +- +-void +-_nouveau_perfmon_dtor(struct nouveau_object *object) +-{ +- struct nouveau_perfmon *ppm = (void *)object; +- struct nouveau_perfdom *dom, *tmp; +- +- list_for_each_entry_safe(dom, tmp, &ppm->domains, head) { +- list_del(&dom->head); +- kfree(dom); +- } +- +- nouveau_engine_destroy(&ppm->base); +-} +- +-int +-nouveau_perfmon_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int length, void **pobject) +-{ +- struct nouveau_perfmon *ppm; +- int ret; +- +- ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM", +- "perfmon", length, pobject); +- ppm = *pobject; +- if (ret) +- return ret; +- +- INIT_LIST_HEAD(&ppm->domains); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c +deleted file mode 100644 +index 50696cc7..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/daemon.c ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static void +-pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, +- struct nouveau_perfctr *ctr) +-{ +- u32 mask = 0x00000000; +- u32 ctrl = 0x00000001; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++) +- mask |= 1 << (ctr->signal[i] - dom->signal); +- +- nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask); +- nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl); +- nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003); +-} +- +-static void +-pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, +- struct nouveau_perfctr *ctr) +-{ +- ctr->ctr = ppm->pwr[ctr->slot]; +- ctr->clk = ppm->pwr[ppm->last]; +-} +- +-static void +-pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) +-{ +- int i; +- +- for (i = 0; i <= ppm->last; i++) { +- ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10)); +- nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000); +- } +-} +- +-static const struct nouveau_funcdom +-pwr_perfctr_func = { +- .init = pwr_perfctr_init, +- .read = pwr_perfctr_read, +- .next = pwr_perfctr_next, +-}; +- +-const struct nouveau_specdom +-nva3_perfmon_pwr[] = { +- { 0x20, (const struct nouveau_specsig[]) { +- { 0x00, "pwr_gr_idle" }, +- { 0x04, "pwr_bsp_idle" }, +- { 0x05, "pwr_vp_idle" }, +- { 0x06, "pwr_ppp_idle" }, +- { 0x13, "pwr_ce0_idle" }, +- {} +- }, &pwr_perfctr_func }, +- {} +-}; +- +-const struct nouveau_specdom +-nvc0_perfmon_pwr[] = { +- { 0x20, (const struct nouveau_specsig[]) { +- { 0x00, "pwr_gr_idle" }, +- { 0x04, "pwr_bsp_idle" }, +- { 0x05, "pwr_vp_idle" }, +- { 0x06, "pwr_ppp_idle" }, +- { 0x13, "pwr_ce0_idle" }, +- { 0x14, "pwr_ce1_idle" }, +- {} +- }, &pwr_perfctr_func }, +- {} +-}; +- +-const struct nouveau_specdom +-nve0_perfmon_pwr[] = { +- { 0x20, (const struct nouveau_specsig[]) { +- { 0x00, "pwr_gr_idle" }, +- { 0x04, "pwr_bsp_idle" }, +- { 0x05, "pwr_vp_idle" }, +- { 0x06, "pwr_ppp_idle" }, +- { 0x13, "pwr_ce0_idle" }, +- { 0x14, "pwr_ce1_idle" }, +- { 0x15, "pwr_ce2_idle" }, +- {} +- }, &pwr_perfctr_func }, +- {} +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c +deleted file mode 100644 +index b2a10785..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c ++++ /dev/null +@@ -1,143 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static void +-nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, +- struct nouveau_perfctr *ctr) +-{ +- struct nv40_perfmon_priv *priv = (void *)ppm; +- struct nv40_perfmon_cntr *cntr = (void *)ctr; +- u32 log = ctr->logic_op; +- u32 src = 0x00000000; +- int i; +- +- for (i = 0; i < 4 && ctr->signal[i]; i++) +- src |= (ctr->signal[i] - dom->signal) << (i * 8); +- +- nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001); +- nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src); +- nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log); +-} +- +-static void +-nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, +- struct nouveau_perfctr *ctr) +-{ +- struct nv40_perfmon_priv *priv = (void *)ppm; +- struct nv40_perfmon_cntr *cntr = (void *)ctr; +- +- switch (cntr->base.slot) { +- case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break; +- case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break; +- case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break; +- case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break; +- } +- cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr); +-} +- +-static void +-nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) +-{ +- struct nv40_perfmon_priv *priv = (void *)ppm; +- if (priv->sequence != ppm->sequence) { +- nv_wr32(priv, 0x400084, 0x00000020); +- priv->sequence = ppm->sequence; +- } +-} +- +-const struct nouveau_funcdom +-nv40_perfctr_func = { +- .init = nv40_perfctr_init, +- .read = nv40_perfctr_read, +- .next = nv40_perfctr_next, +-}; +- +-static const struct nouveau_specdom +-nv40_perfmon[] = { +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- {} +-}; +- +-int +-nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv40_perfmon_oclass *mclass = (void *)oclass; +- struct nv40_perfmon_priv *priv; +- int ret; +- +- ret = nouveau_perfmon_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = &nouveau_perfmon_cclass; +- nv_engine(priv)->sclass = nouveau_perfmon_sclass; +- return 0; +-} +- +-struct nouveau_oclass * +-nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) { +- .base.handle = NV_ENGINE(PERFMON, 0x40), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = _nouveau_perfmon_fini, +- }, +- .doms = nv40_perfmon, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h +deleted file mode 100644 +index 1b5792d1..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-#ifndef __NVKM_PM_NV40_H__ +-#define __NVKM_PM_NV40_H__ +- +-#include "priv.h" +- +-struct nv40_perfmon_oclass { +- struct nouveau_oclass base; +- const struct nouveau_specdom *doms; +-}; +- +-struct nv40_perfmon_priv { +- struct nouveau_perfmon base; +- u32 sequence; +-}; +- +-int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *data, u32 size, +- struct nouveau_object **pobject); +- +-struct nv40_perfmon_cntr { +- struct nouveau_perfctr base; +-}; +- +-extern const struct nouveau_funcdom nv40_perfctr_func; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c +deleted file mode 100644 +index 94217691..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv50.c ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_specdom +-nv50_perfmon[] = { +- { 0x040, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x100, (const struct nouveau_specsig[]) { +- { 0xc8, "gr_idle" }, +- {} +- }, &nv40_perfctr_func }, +- { 0x100, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x020, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x040, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- {} +-}; +- +-struct nouveau_oclass * +-nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) { +- .base.handle = NV_ENGINE(PERFMON, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = _nouveau_perfmon_fini, +- }, +- .doms = nv50_perfmon, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c +deleted file mode 100644 +index 9232c7fc..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nv84.c ++++ /dev/null +@@ -1,78 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_specdom +-nv84_perfmon[] = { +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- {} +-}; +- +-struct nouveau_oclass * +-nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) { +- .base.handle = NV_ENGINE(PERFMON, 0x84), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = _nouveau_perfmon_fini, +- }, +- .doms = nv84_perfmon, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c +deleted file mode 100644 +index 6197ebde..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nva3.c ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_specdom +-nva3_perfmon[] = { +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- { 0x20, (const struct nouveau_specsig[]) { +- {} +- }, &nv40_perfctr_func }, +- {} +-}; +- +-static int +-nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **object) +-{ +- int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object); +- if (ret == 0) { +- struct nv40_perfmon_priv *priv = (void *)*object; +- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, +- nva3_perfmon_pwr); +- if (ret) +- return ret; +- +- priv->base.last = 3; +- } +- return ret; +-} +- +-struct nouveau_oclass * +-nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) { +- .base.handle = NV_ENGINE(PERFMON, 0xa3), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva3_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = _nouveau_perfmon_fini, +- }, +- .doms = nva3_perfmon, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c +deleted file mode 100644 +index 74b24104..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.c ++++ /dev/null +@@ -1,173 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_specdom +-nvc0_perfmon_hub[] = { +- {} +-}; +- +-static const struct nouveau_specdom +-nvc0_perfmon_gpc[] = { +- {} +-}; +- +-static const struct nouveau_specdom +-nvc0_perfmon_part[] = { +- {} +-}; +- +-static void +-nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, +- struct nouveau_perfctr *ctr) +-{ +- struct nvc0_perfmon_priv *priv = (void *)ppm; +- struct nvc0_perfmon_cntr *cntr = (void *)ctr; +- u32 log = ctr->logic_op; +- u32 src = 0x00000000; +- int i; +- +- for (i = 0; i < 4 && ctr->signal[i]; i++) +- src |= (ctr->signal[i] - dom->signal) << (i * 8); +- +- nv_wr32(priv, dom->addr + 0x09c, 0x00040002); +- nv_wr32(priv, dom->addr + 0x100, 0x00000000); +- nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src); +- nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log); +-} +- +-static void +-nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom, +- struct nouveau_perfctr *ctr) +-{ +- struct nvc0_perfmon_priv *priv = (void *)ppm; +- struct nvc0_perfmon_cntr *cntr = (void *)ctr; +- +- switch (cntr->base.slot) { +- case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break; +- case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break; +- case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break; +- case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break; +- } +- cntr->base.clk = nv_rd32(priv, dom->addr + 0x070); +-} +- +-static void +-nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom) +-{ +- struct nvc0_perfmon_priv *priv = (void *)ppm; +- nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); +- nv_wr32(priv, dom->addr + 0x0ec, 0x00000011); +-} +- +-const struct nouveau_funcdom +-nvc0_perfctr_func = { +- .init = nvc0_perfctr_init, +- .read = nvc0_perfctr_read, +- .next = nvc0_perfctr_next, +-}; +- +-int +-nvc0_perfmon_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvc0_perfmon_priv *priv = (void *)object; +- nv_mask(priv, 0x000200, 0x10000000, 0x00000000); +- nv_mask(priv, 0x000200, 0x10000000, 0x10000000); +- return nouveau_perfmon_fini(&priv->base, suspend); +-} +- +-static int +-nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_perfmon_priv *priv; +- u32 mask; +- int ret; +- +- ret = nouveau_perfmon_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, +- nvc0_perfmon_pwr); +- if (ret) +- return ret; +- +- /* HUB */ +- ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, +- nvc0_perfmon_hub); +- if (ret) +- return ret; +- +- /* GPC */ +- mask = (1 << nv_rd32(priv, 0x022430)) - 1; +- mask &= ~nv_rd32(priv, 0x022504); +- mask &= ~nv_rd32(priv, 0x022584); +- +- ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, +- 0x1000, 0x200, nvc0_perfmon_gpc); +- if (ret) +- return ret; +- +- /* PART */ +- mask = (1 << nv_rd32(priv, 0x022438)) - 1; +- mask &= ~nv_rd32(priv, 0x022548); +- mask &= ~nv_rd32(priv, 0x0225c8); +- +- ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, +- 0x1000, 0x200, nvc0_perfmon_part); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = &nouveau_perfmon_cclass; +- nv_engine(priv)->sclass = nouveau_perfmon_sclass; +- priv->base.last = 7; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_perfmon_oclass = { +- .handle = NV_ENGINE(PERFMON, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = nvc0_perfmon_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h +deleted file mode 100644 +index f66bca48..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvc0.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-#ifndef __NVKM_PM_NVC0_H__ +-#define __NVKM_PM_NVC0_H__ +- +-#include "priv.h" +- +-struct nvc0_perfmon_priv { +- struct nouveau_perfmon base; +-}; +- +-struct nvc0_perfmon_cntr { +- struct nouveau_perfctr base; +-}; +- +-extern const struct nouveau_funcdom nvc0_perfctr_func; +-int nvc0_perfmon_fini(struct nouveau_object *, bool); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c +deleted file mode 100644 +index 71d718c1..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nve0.c ++++ /dev/null +@@ -1,162 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static const struct nouveau_specdom +-nve0_perfmon_hub[] = { +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "hub00_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x40, (const struct nouveau_specsig[]) { +- { 0x27, "hub01_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "hub02_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "hub03_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x40, (const struct nouveau_specsig[]) { +- { 0x03, "host_mmio_rd" }, +- { 0x27, "hub04_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "hub05_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0xc0, (const struct nouveau_specsig[]) { +- { 0x74, "host_fb_rd3x" }, +- { 0x75, "host_fb_rd3x_2" }, +- { 0xa7, "hub06_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "hub07_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- {} +-}; +- +-static const struct nouveau_specdom +-nve0_perfmon_gpc[] = { +- { 0xe0, (const struct nouveau_specsig[]) { +- { 0xc7, "gpc00_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- {} +-}; +- +-static const struct nouveau_specdom +-nve0_perfmon_part[] = { +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "part00_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- { 0x60, (const struct nouveau_specsig[]) { +- { 0x47, "part01_user_0" }, +- {} +- }, &nvc0_perfctr_func }, +- {} +-}; +- +-static int +-nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_perfmon_priv *priv; +- u32 mask; +- int ret; +- +- ret = nouveau_perfmon_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- /* PDAEMON */ +- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, +- nve0_perfmon_pwr); +- if (ret) +- return ret; +- +- /* HUB */ +- ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200, +- nve0_perfmon_hub); +- if (ret) +- return ret; +- +- /* GPC */ +- mask = (1 << nv_rd32(priv, 0x022430)) - 1; +- mask &= ~nv_rd32(priv, 0x022504); +- mask &= ~nv_rd32(priv, 0x022584); +- +- ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000, +- 0x1000, 0x200, nve0_perfmon_gpc); +- if (ret) +- return ret; +- +- /* PART */ +- mask = (1 << nv_rd32(priv, 0x022438)) - 1; +- mask &= ~nv_rd32(priv, 0x022548); +- mask &= ~nv_rd32(priv, 0x0225c8); +- +- ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000, +- 0x1000, 0x200, nve0_perfmon_part); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = &nouveau_perfmon_cclass; +- nv_engine(priv)->sclass = nouveau_perfmon_sclass; +- priv->base.last = 7; +- return 0; +-} +- +-struct nouveau_oclass +-nve0_perfmon_oclass = { +- .handle = NV_ENGINE(PERFMON, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = nvc0_perfmon_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c b/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c +deleted file mode 100644 +index 47256f78..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/nvf0.c ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-/******************************************************************************* +- * Perfmon object classes +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM context +- ******************************************************************************/ +- +-/******************************************************************************* +- * PPM engine/subdev functions +- ******************************************************************************/ +- +-static int +-nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_perfmon_priv *priv; +- int ret; +- +- ret = nouveau_perfmon_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0, +- nve0_perfmon_pwr); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = &nouveau_perfmon_cclass; +- nv_engine(priv)->sclass = nouveau_perfmon_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nvf0_perfmon_oclass = { +- .handle = NV_ENGINE(PERFMON, 0xf0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvf0_perfmon_ctor, +- .dtor = _nouveau_perfmon_dtor, +- .init = _nouveau_perfmon_init, +- .fini = nvc0_perfmon_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h b/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h +deleted file mode 100644 +index 0ac8714f..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/perfmon/priv.h ++++ /dev/null +@@ -1,91 +0,0 @@ +-#ifndef __NVKM_PERFMON_PRIV_H__ +-#define __NVKM_PERFMON_PRIV_H__ +- +-#include +- +-struct nouveau_perfctr { +- struct nouveau_object base; +- struct list_head head; +- struct nouveau_perfsig *signal[4]; +- int slot; +- u32 logic_op; +- u32 clk; +- u32 ctr; +-}; +- +-extern struct nouveau_oclass nouveau_perfmon_sclass[]; +- +-struct nouveau_perfctx { +- struct nouveau_engctx base; +-}; +- +-extern struct nouveau_oclass nouveau_perfmon_cclass; +- +-struct nouveau_specsig { +- u8 signal; +- const char *name; +-}; +- +-struct nouveau_perfsig { +- const char *name; +-}; +- +-struct nouveau_perfdom; +-struct nouveau_perfctr * +-nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *, +- struct nouveau_perfdom **); +- +-struct nouveau_specdom { +- u16 signal_nr; +- const struct nouveau_specsig *signal; +- const struct nouveau_funcdom *func; +-}; +- +-extern const struct nouveau_specdom nva3_perfmon_pwr[]; +-extern const struct nouveau_specdom nvc0_perfmon_pwr[]; +-extern const struct nouveau_specdom nve0_perfmon_pwr[]; +- +-struct nouveau_perfdom { +- struct list_head head; +- struct list_head list; +- const struct nouveau_funcdom *func; +- char name[32]; +- u32 addr; +- u8 quad; +- u32 signal_nr; +- struct nouveau_perfsig signal[]; +-}; +- +-struct nouveau_funcdom { +- void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *, +- struct nouveau_perfctr *); +- void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *, +- struct nouveau_perfctr *); +- void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *); +-}; +- +-int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32, +- u32, u32, u32, const struct nouveau_specdom *); +- +-#define nouveau_perfmon_create(p,e,o,d) \ +- nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_perfmon_dtor(p) ({ \ +- struct nouveau_perfmon *c = (p); \ +- _nouveau_perfmon_dtor(nv_object(c)); \ +-}) +-#define nouveau_perfmon_init(p) ({ \ +- struct nouveau_perfmon *c = (p); \ +- _nouveau_perfmon_init(nv_object(c)); \ +-}) +-#define nouveau_perfmon_fini(p,s) ({ \ +- struct nouveau_perfmon *c = (p); \ +- _nouveau_perfmon_fini(nv_object(c), (s)); \ +-}) +- +-int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_perfmon_dtor(struct nouveau_object *); +-int _nouveau_perfmon_init(struct nouveau_object *); +-int _nouveau_perfmon_fini(struct nouveau_object *, bool); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c +deleted file mode 100644 +index 13bf31c4..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/ppp/nv98.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin +- */ +- +-#include +-#include +- +-struct nv98_ppp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * PPP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_ppp_sclass[] = { +- { 0x88b3, &nouveau_object_ofuncs }, +- { 0x85b3, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PPPP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_ppp_cclass = { +- .handle = NV_ENGCTX(PPP, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PPPP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv98_ppp_init(struct nouveau_object *object) +-{ +- struct nv98_ppp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x086010, 0x0000ffd2); +- nv_wr32(priv, 0x08601c, 0x0000fff2); +- return 0; +-} +- +-static int +-nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv98_ppp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, +- "PPPP", "ppp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00400002; +- nv_engine(priv)->cclass = &nv98_ppp_cclass; +- nv_engine(priv)->sclass = nv98_ppp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nv98_ppp_oclass = { +- .handle = NV_ENGINE(PPP, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv98_ppp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nv98_ppp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c +deleted file mode 100644 +index 73719aaa..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/ppp/nvc0.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Maarten Lankhorst +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Maarten Lankhorst +- */ +- +-#include +-#include +- +-struct nvc0_ppp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * PPP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_ppp_sclass[] = { +- { 0x90b3, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PPPP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_ppp_cclass = { +- .handle = NV_ENGCTX(PPP, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PPPP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nvc0_ppp_init(struct nouveau_object *object) +-{ +- struct nvc0_ppp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x086010, 0x0000fff2); +- nv_wr32(priv, 0x08601c, 0x0000fff2); +- return 0; +-} +- +-static int +-nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_ppp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true, +- "PPPP", "ppp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00000002; +- nv_subdev(priv)->intr = nouveau_falcon_intr; +- nv_engine(priv)->cclass = &nvc0_ppp_cclass; +- nv_engine(priv)->sclass = nvc0_ppp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_ppp_oclass = { +- .handle = NV_ENGINE(PPP, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_ppp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nvc0_ppp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c b/drivers/gpu/drm/nouveau/core/engine/software/nv04.c +deleted file mode 100644 +index 64df15c7..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/software/nv04.c ++++ /dev/null +@@ -1,146 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +- +-struct nv04_software_priv { +- struct nouveau_software base; +-}; +- +-struct nv04_software_chan { +- struct nouveau_software_chan base; +-}; +- +-/******************************************************************************* +- * software object classes +- ******************************************************************************/ +- +-static int +-nv04_software_set_ref(struct nouveau_object *object, u32 mthd, +- void *data, u32 size) +-{ +- struct nouveau_object *channel = (void *)nv_engctx(object->parent); +- struct nouveau_fifo_chan *fifo = (void *)channel->parent; +- atomic_set(&fifo->refcnt, *(u32*)data); +- return 0; +-} +- +-static int +-nv04_software_flip(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv04_software_chan *chan = (void *)nv_engctx(object->parent); +- if (chan->base.flip) +- return chan->base.flip(chan->base.flip_data); +- return -EINVAL; +-} +- +-static struct nouveau_omthds +-nv04_software_omthds[] = { +- { 0x0150, 0x0150, nv04_software_set_ref }, +- { 0x0500, 0x0500, nv04_software_flip }, +- {} +-}; +- +-static struct nouveau_oclass +-nv04_software_sclass[] = { +- { 0x006e, &nouveau_object_ofuncs, nv04_software_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * software context +- ******************************************************************************/ +- +-static int +-nv04_software_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_software_chan *chan; +- int ret; +- +- ret = nouveau_software_context_create(parent, engine, oclass, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static struct nouveau_oclass +-nv04_software_cclass = { +- .handle = NV_ENGCTX(SW, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_software_context_ctor, +- .dtor = _nouveau_software_context_dtor, +- .init = _nouveau_software_context_init, +- .fini = _nouveau_software_context_fini, +- }, +-}; +- +-/******************************************************************************* +- * software engine/subdev functions +- ******************************************************************************/ +- +-void +-nv04_software_intr(struct nouveau_subdev *subdev) +-{ +- nv_mask(subdev, 0x000100, 0x80000000, 0x00000000); +-} +- +-static int +-nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_software_priv *priv; +- int ret; +- +- ret = nouveau_software_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = &nv04_software_cclass; +- nv_engine(priv)->sclass = nv04_software_sclass; +- nv_subdev(priv)->intr = nv04_software_intr; +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_software_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(SW, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_software_ctor, +- .dtor = _nouveau_software_dtor, +- .init = _nouveau_software_init, +- .fini = _nouveau_software_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c b/drivers/gpu/drm/nouveau/core/engine/software/nv10.c +deleted file mode 100644 +index f54a2253..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/software/nv10.c ++++ /dev/null +@@ -1,128 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +- +-struct nv10_software_priv { +- struct nouveau_software base; +-}; +- +-struct nv10_software_chan { +- struct nouveau_software_chan base; +-}; +- +-/******************************************************************************* +- * software object classes +- ******************************************************************************/ +- +-static int +-nv10_software_flip(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv10_software_chan *chan = (void *)nv_engctx(object->parent); +- if (chan->base.flip) +- return chan->base.flip(chan->base.flip_data); +- return -EINVAL; +-} +- +-static struct nouveau_omthds +-nv10_software_omthds[] = { +- { 0x0500, 0x0500, nv10_software_flip }, +- {} +-}; +- +-static struct nouveau_oclass +-nv10_software_sclass[] = { +- { 0x016e, &nouveau_object_ofuncs, nv10_software_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * software context +- ******************************************************************************/ +- +-static int +-nv10_software_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv10_software_chan *chan; +- int ret; +- +- ret = nouveau_software_context_create(parent, engine, oclass, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- return 0; +-} +- +-static struct nouveau_oclass +-nv10_software_cclass = { +- .handle = NV_ENGCTX(SW, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv10_software_context_ctor, +- .dtor = _nouveau_software_context_dtor, +- .init = _nouveau_software_context_init, +- .fini = _nouveau_software_context_fini, +- }, +-}; +- +-/******************************************************************************* +- * software engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv10_software_priv *priv; +- int ret; +- +- ret = nouveau_software_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = &nv10_software_cclass; +- nv_engine(priv)->sclass = nv10_software_sclass; +- nv_subdev(priv)->intr = nv04_software_intr; +- return 0; +-} +- +-struct nouveau_oclass * +-nv10_software_oclass = &(struct nouveau_oclass) { +- .handle = NV_ENGINE(SW, 0x10), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv10_software_ctor, +- .dtor = _nouveau_software_dtor, +- .init = _nouveau_software_init, +- .fini = _nouveau_software_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c b/drivers/gpu/drm/nouveau/core/engine/software/nv50.c +deleted file mode 100644 +index a0fec205..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.c ++++ /dev/null +@@ -1,241 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * software object classes +- ******************************************************************************/ +- +-static int +-nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- struct nouveau_fifo_chan *fifo = (void *)nv_object(chan)->parent; +- struct nouveau_handle *handle; +- int ret = -EINVAL; +- +- handle = nouveau_namedb_get(nv_namedb(fifo), *(u32 *)args); +- if (!handle) +- return -ENOENT; +- +- if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) { +- struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object); +- chan->vblank.ctxdma = gpuobj->node->offset >> 4; +- ret = 0; +- } +- nouveau_namedb_put(handle); +- return ret; +-} +- +-static int +-nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- chan->vblank.offset = *(u32 *)args; +- return 0; +-} +- +-int +-nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- chan->vblank.value = *(u32 *)args; +- return 0; +-} +- +-int +-nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- u32 head = *(u32 *)args; +- if (head >= nouveau_disp(chan)->vblank.index_nr) +- return -EINVAL; +- +- nvkm_notify_get(&chan->vblank.notify[head]); +- return 0; +-} +- +-int +-nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- if (chan->base.flip) +- return chan->base.flip(chan->base.flip_data); +- return -EINVAL; +-} +- +-static struct nouveau_omthds +-nv50_software_omthds[] = { +- { 0x018c, 0x018c, nv50_software_mthd_dma_vblsem }, +- { 0x0400, 0x0400, nv50_software_mthd_vblsem_offset }, +- { 0x0404, 0x0404, nv50_software_mthd_vblsem_value }, +- { 0x0408, 0x0408, nv50_software_mthd_vblsem_release }, +- { 0x0500, 0x0500, nv50_software_mthd_flip }, +- {} +-}; +- +-static struct nouveau_oclass +-nv50_software_sclass[] = { +- { 0x506e, &nouveau_object_ofuncs, nv50_software_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * software context +- ******************************************************************************/ +- +-static int +-nv50_software_vblsem_release(struct nvkm_notify *notify) +-{ +- struct nv50_software_chan *chan = +- container_of(notify, typeof(*chan), vblank.notify[notify->index]); +- struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; +- struct nouveau_bar *bar = nouveau_bar(priv); +- +- nv_wr32(priv, 0x001704, chan->vblank.channel); +- nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma); +- bar->flush(bar); +- +- if (nv_device(priv)->chipset == 0x50) { +- nv_wr32(priv, 0x001570, chan->vblank.offset); +- nv_wr32(priv, 0x001574, chan->vblank.value); +- } else { +- nv_wr32(priv, 0x060010, chan->vblank.offset); +- nv_wr32(priv, 0x060014, chan->vblank.value); +- } +- +- return NVKM_NOTIFY_DROP; +-} +- +-void +-nv50_software_context_dtor(struct nouveau_object *object) +-{ +- struct nv50_software_chan *chan = (void *)object; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(chan->vblank.notify); i++) +- nvkm_notify_fini(&chan->vblank.notify[i]); +- +- nouveau_software_context_destroy(&chan->base); +-} +- +-int +-nv50_software_context_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_disp *pdisp = nouveau_disp(parent); +- struct nv50_software_cclass *pclass = (void *)oclass; +- struct nv50_software_chan *chan; +- int ret, i; +- +- ret = nouveau_software_context_create(parent, engine, oclass, &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) { +- ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank, +- false, +- &(struct nvif_notify_head_req_v0) { +- .head = i, +- }, +- sizeof(struct nvif_notify_head_req_v0), +- sizeof(struct nvif_notify_head_rep_v0), +- &chan->vblank.notify[i]); +- if (ret) +- return ret; +- } +- +- chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12; +- return 0; +-} +- +-static struct nv50_software_cclass +-nv50_software_cclass = { +- .base.handle = NV_ENGCTX(SW, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_software_context_ctor, +- .dtor = nv50_software_context_dtor, +- .init = _nouveau_software_context_init, +- .fini = _nouveau_software_context_fini, +- }, +- .vblank = nv50_software_vblsem_release, +-}; +- +-/******************************************************************************* +- * software engine/subdev functions +- ******************************************************************************/ +- +-int +-nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_software_oclass *pclass = (void *)oclass; +- struct nv50_software_priv *priv; +- int ret; +- +- ret = nouveau_software_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_engine(priv)->cclass = pclass->cclass; +- nv_engine(priv)->sclass = pclass->sclass; +- nv_subdev(priv)->intr = nv04_software_intr; +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_software_oclass = &(struct nv50_software_oclass) { +- .base.handle = NV_ENGINE(SW, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_software_ctor, +- .dtor = _nouveau_software_dtor, +- .init = _nouveau_software_init, +- .fini = _nouveau_software_fini, +- }, +- .cclass = &nv50_software_cclass.base, +- .sclass = nv50_software_sclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h b/drivers/gpu/drm/nouveau/core/engine/software/nv50.h +deleted file mode 100644 +index 41542e72..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/software/nv50.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-#ifndef __NVKM_SW_NV50_H__ +-#define __NVKM_SW_NV50_H__ +- +-#include +- +-struct nv50_software_oclass { +- struct nouveau_oclass base; +- struct nouveau_oclass *cclass; +- struct nouveau_oclass *sclass; +-}; +- +-struct nv50_software_priv { +- struct nouveau_software base; +-}; +- +-int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-struct nv50_software_cclass { +- struct nouveau_oclass base; +- int (*vblank)(struct nvkm_notify *); +-}; +- +-struct nv50_software_chan { +- struct nouveau_software_chan base; +- struct { +- struct nvkm_notify notify[4]; +- u32 channel; +- u32 ctxdma; +- u64 offset; +- u32 value; +- } vblank; +-}; +- +-int nv50_software_context_ctor(struct nouveau_object *, +- struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv50_software_context_dtor(struct nouveau_object *); +- +-int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32); +-int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32); +-int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c +deleted file mode 100644 +index 6af370d3..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/software/nvc0.c ++++ /dev/null +@@ -1,149 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +- +-#include +-#include +- +-#include "nv50.h" +- +-/******************************************************************************* +- * software object classes +- ******************************************************************************/ +- +-static int +-nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- u64 data = *(u32 *)args; +- if (mthd == 0x0400) { +- chan->vblank.offset &= 0x00ffffffffULL; +- chan->vblank.offset |= data << 32; +- } else { +- chan->vblank.offset &= 0xff00000000ULL; +- chan->vblank.offset |= data; +- } +- return 0; +-} +- +-static int +-nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd, +- void *args, u32 size) +-{ +- struct nv50_software_chan *chan = (void *)nv_engctx(object->parent); +- struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; +- u32 data = *(u32 *)args; +- +- switch (mthd) { +- case 0x600: +- nv_wr32(priv, 0x419e00, data); /* MP.PM_UNK000 */ +- break; +- case 0x644: +- if (data & ~0x1ffffe) +- return -EINVAL; +- nv_wr32(priv, 0x419e44, data); /* MP.TRAP_WARP_ERROR_EN */ +- break; +- case 0x6ac: +- nv_wr32(priv, 0x419eac, data); /* MP.PM_UNK0AC */ +- break; +- default: +- return -EINVAL; +- } +- return 0; +-} +- +-static struct nouveau_omthds +-nvc0_software_omthds[] = { +- { 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset }, +- { 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset }, +- { 0x0408, 0x0408, nv50_software_mthd_vblsem_value }, +- { 0x040c, 0x040c, nv50_software_mthd_vblsem_release }, +- { 0x0500, 0x0500, nv50_software_mthd_flip }, +- { 0x0600, 0x0600, nvc0_software_mthd_mp_control }, +- { 0x0644, 0x0644, nvc0_software_mthd_mp_control }, +- { 0x06ac, 0x06ac, nvc0_software_mthd_mp_control }, +- {} +-}; +- +-static struct nouveau_oclass +-nvc0_software_sclass[] = { +- { 0x906e, &nouveau_object_ofuncs, nvc0_software_omthds }, +- {} +-}; +- +-/******************************************************************************* +- * software context +- ******************************************************************************/ +- +-static int +-nvc0_software_vblsem_release(struct nvkm_notify *notify) +-{ +- struct nv50_software_chan *chan = +- container_of(notify, typeof(*chan), vblank.notify[notify->index]); +- struct nv50_software_priv *priv = (void *)nv_object(chan)->engine; +- struct nouveau_bar *bar = nouveau_bar(priv); +- +- nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel); +- bar->flush(bar); +- nv_wr32(priv, 0x06000c, upper_32_bits(chan->vblank.offset)); +- nv_wr32(priv, 0x060010, lower_32_bits(chan->vblank.offset)); +- nv_wr32(priv, 0x060014, chan->vblank.value); +- +- return NVKM_NOTIFY_DROP; +-} +- +-static struct nv50_software_cclass +-nvc0_software_cclass = { +- .base.handle = NV_ENGCTX(SW, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_software_context_ctor, +- .dtor = nv50_software_context_dtor, +- .init = _nouveau_software_context_init, +- .fini = _nouveau_software_context_fini, +- }, +- .vblank = nvc0_software_vblsem_release, +-}; +- +-/******************************************************************************* +- * software engine/subdev functions +- ******************************************************************************/ +- +-struct nouveau_oclass * +-nvc0_software_oclass = &(struct nv50_software_oclass) { +- .base.handle = NV_ENGINE(SW, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_software_ctor, +- .dtor = _nouveau_software_dtor, +- .init = _nouveau_software_init, +- .fini = _nouveau_software_fini, +- }, +- .cclass = &nvc0_software_cclass.base, +- .sclass = nvc0_software_sclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c +deleted file mode 100644 +index fd6272b8..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv84.c ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs, Ilia Mirkin +- */ +- +-#include +-#include +- +-/******************************************************************************* +- * VP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_vp_sclass[] = { +- { 0x7476, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PVP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv84_vp_cclass = { +- .handle = NV_ENGCTX(VP, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_xtensa_engctx_ctor, +- .dtor = _nouveau_engctx_dtor, +- .init = _nouveau_engctx_init, +- .fini = _nouveau_engctx_fini, +- .rd32 = _nouveau_engctx_rd32, +- .wr32 = _nouveau_engctx_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PVP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv84_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_xtensa *priv; +- int ret; +- +- ret = nouveau_xtensa_create(parent, engine, oclass, 0xf000, true, +- "PVP", "vp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x01020000; +- nv_engine(priv)->cclass = &nv84_vp_cclass; +- nv_engine(priv)->sclass = nv84_vp_sclass; +- priv->fifo_val = 0x111; +- priv->unkd28 = 0x9c544; +- return 0; +-} +- +-struct nouveau_oclass +-nv84_vp_oclass = { +- .handle = NV_ENGINE(VP, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_vp_ctor, +- .dtor = _nouveau_xtensa_dtor, +- .init = _nouveau_xtensa_init, +- .fini = _nouveau_xtensa_fini, +- .rd32 = _nouveau_xtensa_rd32, +- .wr32 = _nouveau_xtensa_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c b/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c +deleted file mode 100644 +index fc9ae0ff..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/vp/nv98.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin +- */ +- +-#include +-#include +- +-struct nv98_vp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * VP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_vp_sclass[] = { +- { 0x88b2, &nouveau_object_ofuncs }, +- { 0x85b2, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PVP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nv98_vp_cclass = { +- .handle = NV_ENGCTX(VP, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PVP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nv98_vp_init(struct nouveau_object *object) +-{ +- struct nv98_vp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x085010, 0x0000ffd2); +- nv_wr32(priv, 0x08501c, 0x0000fff2); +- return 0; +-} +- +-static int +-nv98_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv98_vp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true, +- "PVP", "vp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x01020000; +- nv_engine(priv)->cclass = &nv98_vp_cclass; +- nv_engine(priv)->sclass = nv98_vp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nv98_vp_oclass = { +- .handle = NV_ENGINE(VP, 0x98), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv98_vp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nv98_vp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c +deleted file mode 100644 +index ac1f62aa..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/vp/nvc0.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Maarten Lankhorst +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Maarten Lankhorst +- */ +- +-#include +-#include +- +-struct nvc0_vp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * VP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_vp_sclass[] = { +- { 0x90b2, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PVP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nvc0_vp_cclass = { +- .handle = NV_ENGCTX(VP, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PVP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nvc0_vp_init(struct nouveau_object *object) +-{ +- struct nvc0_vp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x085010, 0x0000fff2); +- nv_wr32(priv, 0x08501c, 0x0000fff2); +- return 0; +-} +- +-static int +-nvc0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_vp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true, +- "PVP", "vp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00020000; +- nv_subdev(priv)->intr = nouveau_falcon_intr; +- nv_engine(priv)->cclass = &nvc0_vp_cclass; +- nv_engine(priv)->sclass = nvc0_vp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_vp_oclass = { +- .handle = NV_ENGINE(VP, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_vp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nvc0_vp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c b/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c +deleted file mode 100644 +index d4c31084..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/vp/nve0.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-struct nve0_vp_priv { +- struct nouveau_falcon base; +-}; +- +-/******************************************************************************* +- * VP object classes +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve0_vp_sclass[] = { +- { 0x95b2, &nouveau_object_ofuncs }, +- {}, +-}; +- +-/******************************************************************************* +- * PVP context +- ******************************************************************************/ +- +-static struct nouveau_oclass +-nve0_vp_cclass = { +- .handle = NV_ENGCTX(VP, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_falcon_context_ctor, +- .dtor = _nouveau_falcon_context_dtor, +- .init = _nouveau_falcon_context_init, +- .fini = _nouveau_falcon_context_fini, +- .rd32 = _nouveau_falcon_context_rd32, +- .wr32 = _nouveau_falcon_context_wr32, +- }, +-}; +- +-/******************************************************************************* +- * PVP engine/subdev functions +- ******************************************************************************/ +- +-static int +-nve0_vp_init(struct nouveau_object *object) +-{ +- struct nve0_vp_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_falcon_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x085010, 0x0000fff2); +- nv_wr32(priv, 0x08501c, 0x0000fff2); +- return 0; +-} +- +-static int +-nve0_vp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_vp_priv *priv; +- int ret; +- +- ret = nouveau_falcon_create(parent, engine, oclass, 0x085000, true, +- "PVP", "vp", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->unit = 0x00020000; +- nv_subdev(priv)->intr = nouveau_falcon_intr; +- nv_engine(priv)->cclass = &nve0_vp_cclass; +- nv_engine(priv)->sclass = nve0_vp_sclass; +- return 0; +-} +- +-struct nouveau_oclass +-nve0_vp_oclass = { +- .handle = NV_ENGINE(VP, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_vp_ctor, +- .dtor = _nouveau_falcon_dtor, +- .init = nve0_vp_init, +- .fini = _nouveau_falcon_fini, +- .rd32 = _nouveau_falcon_rd32, +- .wr32 = _nouveau_falcon_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/engine/xtensa.c b/drivers/gpu/drm/nouveau/core/engine/xtensa.c +deleted file mode 100644 +index 92384759..00000000 +--- a/drivers/gpu/drm/nouveau/core/engine/xtensa.c ++++ /dev/null +@@ -1,176 +0,0 @@ +-/* +- * Copyright 2013 Ilia Mirkin +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-u32 +-_nouveau_xtensa_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_xtensa *xtensa = (void *)object; +- return nv_rd32(xtensa, xtensa->addr + addr); +-} +- +-void +-_nouveau_xtensa_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nouveau_xtensa *xtensa = (void *)object; +- nv_wr32(xtensa, xtensa->addr + addr, data); +-} +- +-int +-_nouveau_xtensa_engctx_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_engctx *engctx; +- int ret; +- +- ret = nouveau_engctx_create(parent, engine, oclass, NULL, +- 0x10000, 0x1000, +- NVOBJ_FLAG_ZERO_ALLOC, &engctx); +- *pobject = nv_object(engctx); +- return ret; +-} +- +-void +-_nouveau_xtensa_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_xtensa *xtensa = (void *)subdev; +- u32 unk104 = nv_ro32(xtensa, 0xd04); +- u32 intr = nv_ro32(xtensa, 0xc20); +- u32 chan = nv_ro32(xtensa, 0xc28); +- u32 unk10c = nv_ro32(xtensa, 0xd0c); +- +- if (intr & 0x10) +- nv_warn(xtensa, "Watchdog interrupt, engine hung.\n"); +- nv_wo32(xtensa, 0xc20, intr); +- intr = nv_ro32(xtensa, 0xc20); +- if (unk104 == 0x10001 && unk10c == 0x200 && chan && !intr) { +- nv_debug(xtensa, "Enabling FIFO_CTRL\n"); +- nv_mask(xtensa, xtensa->addr + 0xd94, 0, xtensa->fifo_val); +- } +-} +- +-int +-nouveau_xtensa_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 addr, bool enable, +- const char *iname, const char *fname, +- int length, void **pobject) +-{ +- struct nouveau_xtensa *xtensa; +- int ret; +- +- ret = nouveau_engine_create_(parent, engine, oclass, enable, iname, +- fname, length, pobject); +- xtensa = *pobject; +- if (ret) +- return ret; +- +- nv_subdev(xtensa)->intr = _nouveau_xtensa_intr; +- +- xtensa->addr = addr; +- +- return 0; +-} +- +-int +-_nouveau_xtensa_init(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nouveau_xtensa *xtensa = (void *)object; +- const struct firmware *fw; +- char name[32]; +- int i, ret; +- u32 tmp; +- +- ret = nouveau_engine_init(&xtensa->base); +- if (ret) +- return ret; +- +- if (!xtensa->gpu_fw) { +- snprintf(name, sizeof(name), "nouveau/nv84_xuc%03x", +- xtensa->addr >> 12); +- +- ret = request_firmware(&fw, name, nv_device_base(device)); +- if (ret) { +- nv_warn(xtensa, "unable to load firmware %s\n", name); +- return ret; +- } +- +- if (fw->size > 0x40000) { +- nv_warn(xtensa, "firmware %s too large\n", name); +- release_firmware(fw); +- return -EINVAL; +- } +- +- ret = nouveau_gpuobj_new(object, NULL, 0x40000, 0x1000, 0, +- &xtensa->gpu_fw); +- if (ret) { +- release_firmware(fw); +- return ret; +- } +- +- nv_debug(xtensa, "Loading firmware to address: 0x%llx\n", +- xtensa->gpu_fw->addr); +- +- for (i = 0; i < fw->size / 4; i++) +- nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); +- release_firmware(fw); +- } +- +- nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ +- nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ +- +- nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ +- nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ +- nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ +- +- nv_wo32(xtensa, 0xcc0, xtensa->gpu_fw->addr >> 8); /* XT_REGION_BASE */ +- nv_wo32(xtensa, 0xcc4, 0x1c); /* XT_REGION_SETUP */ +- nv_wo32(xtensa, 0xcc8, xtensa->gpu_fw->size >> 8); /* XT_REGION_LIMIT */ +- +- tmp = nv_rd32(xtensa, 0x0); +- nv_wo32(xtensa, 0xde0, tmp); /* SCRATCH_H2X */ +- +- nv_wo32(xtensa, 0xce8, 0xf); /* XT_REGION_SETUP */ +- +- nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ +- nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ +- +- return 0; +-} +- +-int +-_nouveau_xtensa_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_xtensa *xtensa = (void *)object; +- +- nv_wo32(xtensa, 0xd84, 0); /* INTR_EN */ +- nv_wo32(xtensa, 0xd94, 0); /* FIFO_CTRL */ +- +- if (!suspend) +- nouveau_gpuobj_ref(NULL, &xtensa->gpu_fw); +- +- return nouveau_engine_fini(&xtensa->base, suspend); +-} +diff --git a/drivers/gpu/drm/nouveau/core/include/core/client.h b/drivers/gpu/drm/nouveau/core/include/core/client.h +deleted file mode 100644 +index b0ce9f66..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/client.h ++++ /dev/null +@@ -1,57 +0,0 @@ +-#ifndef __NOUVEAU_CLIENT_H__ +-#define __NOUVEAU_CLIENT_H__ +- +-#include +- +-struct nouveau_client { +- struct nouveau_namedb base; +- struct nouveau_handle *root; +- struct nouveau_object *device; +- char name[32]; +- u32 debug; +- struct nouveau_vm *vm; +- bool super; +- void *data; +- +- int (*ntfy)(const void *, u32, const void *, u32); +- struct nvkm_client_notify *notify[16]; +-}; +- +-static inline struct nouveau_client * +-nv_client(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_CLIENT_CLASS))) +- nv_assert("BAD CAST -> NvClient, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-static inline struct nouveau_client * +-nouveau_client(void *obj) +-{ +- struct nouveau_object *client = nv_object(obj); +- while (client && !(nv_iclass(client, NV_CLIENT_CLASS))) +- client = client->parent; +- return (void *)client; +-} +- +-#define nouveau_client_create(n,c,oc,od,d) \ +- nouveau_client_create_((n), (c), (oc), (od), sizeof(**d), (void **)d) +- +-int nouveau_client_create_(const char *name, u64 device, const char *cfg, +- const char *dbg, int, void **); +-#define nouveau_client_destroy(p) \ +- nouveau_namedb_destroy(&(p)->base) +- +-int nouveau_client_init(struct nouveau_client *); +-int nouveau_client_fini(struct nouveau_client *, bool suspend); +-const char *nouveau_client_name(void *obj); +- +-int nvkm_client_notify_new(struct nouveau_object *, struct nvkm_event *, +- void *data, u32 size); +-int nvkm_client_notify_del(struct nouveau_client *, int index); +-int nvkm_client_notify_get(struct nouveau_client *, int index); +-int nvkm_client_notify_put(struct nouveau_client *, int index); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/debug.h b/drivers/gpu/drm/nouveau/core/include/core/debug.h +deleted file mode 100644 +index 8092e2e9..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/debug.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-#ifndef __NOUVEAU_DEBUG_H__ +-#define __NOUVEAU_DEBUG_H__ +- +-extern int nv_info_debug_level; +- +-#define NV_DBG_FATAL 0 +-#define NV_DBG_ERROR 1 +-#define NV_DBG_WARN 2 +-#define NV_DBG_INFO nv_info_debug_level +-#define NV_DBG_DEBUG 4 +-#define NV_DBG_TRACE 5 +-#define NV_DBG_PARANOIA 6 +-#define NV_DBG_SPAM 7 +- +-#define NV_DBG_INFO_NORMAL 3 +-#define NV_DBG_INFO_SILENT NV_DBG_DEBUG +- +-#define nv_debug_level(a) nv_info_debug_level = NV_DBG_INFO_##a +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/device.h b/drivers/gpu/drm/nouveau/core/include/core/device.h +deleted file mode 100644 +index 1d9d8939..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/device.h ++++ /dev/null +@@ -1,177 +0,0 @@ +-#ifndef __NOUVEAU_DEVICE_H__ +-#define __NOUVEAU_DEVICE_H__ +- +-#include +-#include +-#include +-#include +- +-enum nv_subdev_type { +- NVDEV_ENGINE_DEVICE, +- NVDEV_SUBDEV_VBIOS, +- +- /* All subdevs from DEVINIT to DEVINIT_LAST will be created before +- * *any* of them are initialised. This subdev category is used +- * for any subdevs that the VBIOS init table parsing may call out +- * to during POST. +- */ +- NVDEV_SUBDEV_DEVINIT, +- NVDEV_SUBDEV_GPIO, +- NVDEV_SUBDEV_I2C, +- NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C, +- +- /* This grouping of subdevs are initialised right after they've +- * been created, and are allowed to assume any subdevs in the +- * list above them exist and have been initialised. +- */ +- NVDEV_SUBDEV_FUSE, +- NVDEV_SUBDEV_MXM, +- NVDEV_SUBDEV_MC, +- NVDEV_SUBDEV_BUS, +- NVDEV_SUBDEV_TIMER, +- NVDEV_SUBDEV_FB, +- NVDEV_SUBDEV_LTC, +- NVDEV_SUBDEV_IBUS, +- NVDEV_SUBDEV_INSTMEM, +- NVDEV_SUBDEV_VM, +- NVDEV_SUBDEV_BAR, +- NVDEV_SUBDEV_PWR, +- NVDEV_SUBDEV_VOLT, +- NVDEV_SUBDEV_THERM, +- NVDEV_SUBDEV_CLOCK, +- +- NVDEV_ENGINE_FIRST, +- NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST, +- NVDEV_ENGINE_IFB, +- NVDEV_ENGINE_FIFO, +- NVDEV_ENGINE_SW, +- NVDEV_ENGINE_GR, +- NVDEV_ENGINE_MPEG, +- NVDEV_ENGINE_ME, +- NVDEV_ENGINE_VP, +- NVDEV_ENGINE_CRYPT, +- NVDEV_ENGINE_BSP, +- NVDEV_ENGINE_PPP, +- NVDEV_ENGINE_COPY0, +- NVDEV_ENGINE_COPY1, +- NVDEV_ENGINE_COPY2, +- NVDEV_ENGINE_VIC, +- NVDEV_ENGINE_VENC, +- NVDEV_ENGINE_DISP, +- NVDEV_ENGINE_PERFMON, +- +- NVDEV_SUBDEV_NR, +-}; +- +-struct nouveau_device { +- struct nouveau_engine base; +- struct list_head head; +- +- struct pci_dev *pdev; +- struct platform_device *platformdev; +- u64 handle; +- +- struct nvkm_event event; +- +- const char *cfgopt; +- const char *dbgopt; +- const char *name; +- const char *cname; +- u64 disable_mask; +- +- enum { +- NV_04 = 0x04, +- NV_10 = 0x10, +- NV_11 = 0x11, +- NV_20 = 0x20, +- NV_30 = 0x30, +- NV_40 = 0x40, +- NV_50 = 0x50, +- NV_C0 = 0xc0, +- NV_E0 = 0xe0, +- GM100 = 0x110, +- } card_type; +- u32 chipset; +- u32 crystal; +- +- struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR]; +- struct nouveau_object *subdev[NVDEV_SUBDEV_NR]; +- +- struct { +- struct notifier_block nb; +- } acpi; +-}; +- +-int nouveau_device_list(u64 *name, int size); +- +-static inline struct nouveau_device * +-nv_device(void *obj) +-{ +- struct nouveau_object *object = nv_object(obj); +- struct nouveau_object *device = object; +- +- if (device->engine) +- device = device->engine; +- if (device->parent) +- device = device->parent; +- +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) || +- (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) { +- nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x", +- nv_hclass(object), nv_hclass(device)); +- } +-#endif +- +- return (void *)device; +-} +- +-static inline struct nouveau_subdev * +-nouveau_subdev(void *obj, int sub) +-{ +- if (nv_device(obj)->subdev[sub]) +- return nv_subdev(nv_device(obj)->subdev[sub]); +- return NULL; +-} +- +-static inline struct nouveau_engine * +-nouveau_engine(void *obj, int sub) +-{ +- struct nouveau_subdev *subdev = nouveau_subdev(obj, sub); +- if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS)) +- return nv_engine(subdev); +- return NULL; +-} +- +-static inline bool +-nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub) +-{ +- struct nouveau_device *device = nv_device(object); +- return device->pdev->device == dev && +- device->pdev->subsystem_vendor == ven && +- device->pdev->subsystem_device == sub; +-} +- +-static inline bool +-nv_device_is_pci(struct nouveau_device *device) +-{ +- return device->pdev != NULL; +-} +- +-static inline struct device * +-nv_device_base(struct nouveau_device *device) +-{ +- return nv_device_is_pci(device) ? &device->pdev->dev : +- &device->platformdev->dev; +-} +- +-resource_size_t +-nv_device_resource_start(struct nouveau_device *device, unsigned int bar); +- +-resource_size_t +-nv_device_resource_len(struct nouveau_device *device, unsigned int bar); +- +-int +-nv_device_get_irq(struct nouveau_device *device, bool stall); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/engctx.h b/drivers/gpu/drm/nouveau/core/include/core/engctx.h +deleted file mode 100644 +index 2fd48b56..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/engctx.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-#ifndef __NOUVEAU_ENGCTX_H__ +-#define __NOUVEAU_ENGCTX_H__ +- +-#include +-#include +- +-#include +- +-#define NV_ENGCTX_(eng,var) (NV_ENGCTX_CLASS | ((var) << 8) | (eng)) +-#define NV_ENGCTX(name,var) NV_ENGCTX_(NVDEV_ENGINE_##name, (var)) +- +-struct nouveau_engctx { +- struct nouveau_gpuobj base; +- struct nouveau_vma vma; +- struct list_head head; +- unsigned long save; +- u64 addr; +-}; +- +-static inline struct nouveau_engctx * +-nv_engctx(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_ENGCTX_CLASS))) +- nv_assert("BAD CAST -> NvEngCtx, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-#define nouveau_engctx_create(p,e,c,g,s,a,f,d) \ +- nouveau_engctx_create_((p), (e), (c), (g), (s), (a), (f), \ +- sizeof(**d), (void **)d) +- +-int nouveau_engctx_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, struct nouveau_object *, +- u32 size, u32 align, u32 flags, +- int length, void **data); +-void nouveau_engctx_destroy(struct nouveau_engctx *); +-int nouveau_engctx_init(struct nouveau_engctx *); +-int nouveau_engctx_fini(struct nouveau_engctx *, bool suspend); +- +-int _nouveau_engctx_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void _nouveau_engctx_dtor(struct nouveau_object *); +-int _nouveau_engctx_init(struct nouveau_object *); +-int _nouveau_engctx_fini(struct nouveau_object *, bool suspend); +-#define _nouveau_engctx_rd32 _nouveau_gpuobj_rd32 +-#define _nouveau_engctx_wr32 _nouveau_gpuobj_wr32 +- +-struct nouveau_object *nouveau_engctx_get(struct nouveau_engine *, u64 addr); +-void nouveau_engctx_put(struct nouveau_object *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/engine.h b/drivers/gpu/drm/nouveau/core/include/core/engine.h +deleted file mode 100644 +index 666d06de..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/engine.h ++++ /dev/null +@@ -1,57 +0,0 @@ +-#ifndef __NOUVEAU_ENGINE_H__ +-#define __NOUVEAU_ENGINE_H__ +- +-#include +-#include +- +-#define NV_ENGINE_(eng,var) (NV_ENGINE_CLASS | ((var) << 8) | (eng)) +-#define NV_ENGINE(name,var) NV_ENGINE_(NVDEV_ENGINE_##name, (var)) +- +-struct nouveau_engine { +- struct nouveau_subdev base; +- struct nouveau_oclass *cclass; +- struct nouveau_oclass *sclass; +- +- struct list_head contexts; +- spinlock_t lock; +- +- void (*tile_prog)(struct nouveau_engine *, int region); +- int (*tlb_flush)(struct nouveau_engine *); +-}; +- +-static inline struct nouveau_engine * +-nv_engine(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_ENGINE_CLASS))) +- nv_assert("BAD CAST -> NvEngine, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-static inline int +-nv_engidx(struct nouveau_object *object) +-{ +- return nv_subidx(object); +-} +- +-#define nouveau_engine_create(p,e,c,d,i,f,r) \ +- nouveau_engine_create_((p), (e), (c), (d), (i), (f), \ +- sizeof(**r),(void **)r) +- +-#define nouveau_engine_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_engine_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_engine_fini(p,s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +- +-int nouveau_engine_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, bool, const char *, +- const char *, int, void **); +- +-#define _nouveau_engine_dtor _nouveau_subdev_dtor +-#define _nouveau_engine_init _nouveau_subdev_init +-#define _nouveau_engine_fini _nouveau_subdev_fini +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/enum.h b/drivers/gpu/drm/nouveau/core/include/core/enum.h +deleted file mode 100644 +index 4fc62bb8..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/enum.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-#ifndef __NOUVEAU_ENUM_H__ +-#define __NOUVEAU_ENUM_H__ +- +-struct nouveau_enum { +- u32 value; +- const char *name; +- const void *data; +- u32 data2; +-}; +- +-const struct nouveau_enum * +-nouveau_enum_find(const struct nouveau_enum *, u32 value); +- +-const struct nouveau_enum * +-nouveau_enum_print(const struct nouveau_enum *en, u32 value); +- +-struct nouveau_bitfield { +- u32 mask; +- const char *name; +-}; +- +-void nouveau_bitfield_print(const struct nouveau_bitfield *, u32 value); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/event.h b/drivers/gpu/drm/nouveau/core/include/core/event.h +deleted file mode 100644 +index 92876528..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/event.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-#ifndef __NVKM_EVENT_H__ +-#define __NVKM_EVENT_H__ +- +-#include +- +-struct nvkm_event_func { +- int (*ctor)(struct nouveau_object *, void *data, u32 size, +- struct nvkm_notify *); +- void (*send)(void *data, u32 size, struct nvkm_notify *); +- void (*init)(struct nvkm_event *, int type, int index); +- void (*fini)(struct nvkm_event *, int type, int index); +-}; +- +-struct nvkm_event { +- const struct nvkm_event_func *func; +- +- int types_nr; +- int index_nr; +- +- spinlock_t refs_lock; +- spinlock_t list_lock; +- struct list_head list; +- int *refs; +-}; +- +-int nvkm_event_init(const struct nvkm_event_func *func, +- int types_nr, int index_nr, +- struct nvkm_event *); +-void nvkm_event_fini(struct nvkm_event *); +-void nvkm_event_get(struct nvkm_event *, u32 types, int index); +-void nvkm_event_put(struct nvkm_event *, u32 types, int index); +-void nvkm_event_send(struct nvkm_event *, u32 types, int index, +- void *data, u32 size); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h b/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h +deleted file mode 100644 +index b3b9ce4e..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/gpuobj.h ++++ /dev/null +@@ -1,71 +0,0 @@ +-#ifndef __NOUVEAU_GPUOBJ_H__ +-#define __NOUVEAU_GPUOBJ_H__ +- +-#include +-#include +-#include +-#include +- +-struct nouveau_vma; +-struct nouveau_vm; +- +-#define NVOBJ_FLAG_ZERO_ALLOC 0x00000001 +-#define NVOBJ_FLAG_ZERO_FREE 0x00000002 +-#define NVOBJ_FLAG_HEAP 0x00000004 +- +-struct nouveau_gpuobj { +- struct nouveau_object base; +- struct nouveau_object *parent; +- struct nouveau_mm_node *node; +- struct nouveau_mm heap; +- +- u32 flags; +- u64 addr; +- u32 size; +-}; +- +-static inline struct nouveau_gpuobj * +-nv_gpuobj(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_GPUOBJ_CLASS))) +- nv_assert("BAD CAST -> NvGpuObj, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-#define nouveau_gpuobj_create(p,e,c,v,g,s,a,f,d) \ +- nouveau_gpuobj_create_((p), (e), (c), (v), (g), (s), (a), (f), \ +- sizeof(**d), (void **)d) +-#define nouveau_gpuobj_init(p) nouveau_object_init(&(p)->base) +-#define nouveau_gpuobj_fini(p,s) nouveau_object_fini(&(p)->base, (s)) +-int nouveau_gpuobj_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32 pclass, +- struct nouveau_object *, u32 size, u32 align, +- u32 flags, int length, void **); +-void nouveau_gpuobj_destroy(struct nouveau_gpuobj *); +- +-int nouveau_gpuobj_new(struct nouveau_object *, struct nouveau_object *, +- u32 size, u32 align, u32 flags, +- struct nouveau_gpuobj **); +-int nouveau_gpuobj_dup(struct nouveau_object *, struct nouveau_gpuobj *, +- struct nouveau_gpuobj **); +- +-int nouveau_gpuobj_map(struct nouveau_gpuobj *, u32 acc, struct nouveau_vma *); +-int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *, struct nouveau_vm *, +- u32 access, struct nouveau_vma *); +-void nouveau_gpuobj_unmap(struct nouveau_vma *); +- +-static inline void +-nouveau_gpuobj_ref(struct nouveau_gpuobj *obj, struct nouveau_gpuobj **ref) +-{ +- nouveau_object_ref(&obj->base, (struct nouveau_object **)ref); +-} +- +-void _nouveau_gpuobj_dtor(struct nouveau_object *); +-int _nouveau_gpuobj_init(struct nouveau_object *); +-int _nouveau_gpuobj_fini(struct nouveau_object *, bool); +-u32 _nouveau_gpuobj_rd32(struct nouveau_object *, u64); +-void _nouveau_gpuobj_wr32(struct nouveau_object *, u64, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/handle.h b/drivers/gpu/drm/nouveau/core/include/core/handle.h +deleted file mode 100644 +index ceb67d77..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/handle.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-#ifndef __NOUVEAU_HANDLE_H__ +-#define __NOUVEAU_HANDLE_H__ +- +-struct nouveau_handle { +- struct nouveau_namedb *namedb; +- struct list_head node; +- +- struct list_head head; +- struct list_head tree; +- u32 name; +- u32 priv; +- +- u8 route; +- u64 token; +- +- struct nouveau_handle *parent; +- struct nouveau_object *object; +-}; +- +-int nouveau_handle_create(struct nouveau_object *, u32 parent, u32 handle, +- struct nouveau_object *, struct nouveau_handle **); +-void nouveau_handle_destroy(struct nouveau_handle *); +-int nouveau_handle_init(struct nouveau_handle *); +-int nouveau_handle_fini(struct nouveau_handle *, bool suspend); +- +-int nouveau_handle_new(struct nouveau_object *, u32 parent, u32 handle, +- u16 oclass, void *data, u32 size, +- struct nouveau_object **); +-int nouveau_handle_del(struct nouveau_object *, u32 parent, u32 handle); +- +-struct nouveau_object * +-nouveau_handle_ref(struct nouveau_object *, u32 name); +- +-struct nouveau_handle *nouveau_handle_get_class(struct nouveau_object *, u16); +-struct nouveau_handle *nouveau_handle_get_vinst(struct nouveau_object *, u64); +-struct nouveau_handle *nouveau_handle_get_cinst(struct nouveau_object *, u32); +-void nouveau_handle_put(struct nouveau_handle *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h b/drivers/gpu/drm/nouveau/core/include/core/ioctl.h +deleted file mode 100644 +index ac7935c2..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/ioctl.h ++++ /dev/null +@@ -1,6 +0,0 @@ +-#ifndef __NVKM_IOCTL_H__ +-#define __NVKM_IOCTL_H__ +- +-int nvkm_ioctl(struct nouveau_client *, bool, void *, u32, void **); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/mm.h b/drivers/gpu/drm/nouveau/core/include/core/mm.h +deleted file mode 100644 +index bfe69315..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/mm.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-#ifndef __NOUVEAU_MM_H__ +-#define __NOUVEAU_MM_H__ +- +-struct nouveau_mm_node { +- struct list_head nl_entry; +- struct list_head fl_entry; +- struct list_head rl_entry; +- +-#define NVKM_MM_HEAP_ANY 0x00 +- u8 heap; +-#define NVKM_MM_TYPE_NONE 0x00 +-#define NVKM_MM_TYPE_HOLE 0xff +- u8 type; +- u32 offset; +- u32 length; +-}; +- +-struct nouveau_mm { +- struct list_head nodes; +- struct list_head free; +- +- u32 block_size; +- int heap_nodes; +-}; +- +-static inline bool +-nouveau_mm_initialised(struct nouveau_mm *mm) +-{ +- return mm->block_size != 0; +-} +- +-int nouveau_mm_init(struct nouveau_mm *, u32 offset, u32 length, u32 block); +-int nouveau_mm_fini(struct nouveau_mm *); +-int nouveau_mm_head(struct nouveau_mm *, u8 heap, u8 type, u32 size_max, +- u32 size_min, u32 align, struct nouveau_mm_node **); +-int nouveau_mm_tail(struct nouveau_mm *, u8 heap, u8 type, u32 size_max, +- u32 size_min, u32 align, struct nouveau_mm_node **); +-void nouveau_mm_free(struct nouveau_mm *, struct nouveau_mm_node **); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/namedb.h b/drivers/gpu/drm/nouveau/core/include/core/namedb.h +deleted file mode 100644 +index f5b5fd8e..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/namedb.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-#ifndef __NOUVEAU_NAMEDB_H__ +-#define __NOUVEAU_NAMEDB_H__ +- +-#include +- +-struct nouveau_handle; +- +-struct nouveau_namedb { +- struct nouveau_parent base; +- rwlock_t lock; +- struct list_head list; +-}; +- +-static inline struct nouveau_namedb * +-nv_namedb(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_NAMEDB_CLASS))) +- nv_assert("BAD CAST -> NvNameDB, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-#define nouveau_namedb_create(p,e,c,v,s,m,d) \ +- nouveau_namedb_create_((p), (e), (c), (v), (s), (m), \ +- sizeof(**d), (void **)d) +-#define nouveau_namedb_init(p) \ +- nouveau_parent_init(&(p)->base) +-#define nouveau_namedb_fini(p,s) \ +- nouveau_parent_fini(&(p)->base, (s)) +-#define nouveau_namedb_destroy(p) \ +- nouveau_parent_destroy(&(p)->base) +- +-int nouveau_namedb_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32 pclass, +- struct nouveau_oclass *, u64 engcls, +- int size, void **); +- +-int _nouveau_namedb_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-#define _nouveau_namedb_dtor _nouveau_parent_dtor +-#define _nouveau_namedb_init _nouveau_parent_init +-#define _nouveau_namedb_fini _nouveau_parent_fini +- +-int nouveau_namedb_insert(struct nouveau_namedb *, u32 name, +- struct nouveau_object *, struct nouveau_handle *); +-void nouveau_namedb_remove(struct nouveau_handle *); +- +-struct nouveau_handle *nouveau_namedb_get(struct nouveau_namedb *, u32); +-struct nouveau_handle *nouveau_namedb_get_class(struct nouveau_namedb *, u16); +-struct nouveau_handle *nouveau_namedb_get_vinst(struct nouveau_namedb *, u64); +-struct nouveau_handle *nouveau_namedb_get_cinst(struct nouveau_namedb *, u32); +-void nouveau_namedb_put(struct nouveau_handle *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/notify.h b/drivers/gpu/drm/nouveau/core/include/core/notify.h +deleted file mode 100644 +index a7c3c5f5..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/notify.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-#ifndef __NVKM_NOTIFY_H__ +-#define __NVKM_NOTIFY_H__ +- +-struct nvkm_notify { +- struct nvkm_event *event; +- struct list_head head; +-#define NVKM_NOTIFY_USER 0 +-#define NVKM_NOTIFY_WORK 1 +- unsigned long flags; +- int block; +-#define NVKM_NOTIFY_DROP 0 +-#define NVKM_NOTIFY_KEEP 1 +- int (*func)(struct nvkm_notify *); +- +- /* set by nvkm_event ctor */ +- u32 types; +- int index; +- u32 size; +- +- struct work_struct work; +- /* this is const for a *very* good reason - the data might be on the +- * stack from an irq handler. if you're not core/notify.c then you +- * should probably think twice before casting it away... +- */ +- const void *data; +-}; +- +-int nvkm_notify_init(struct nouveau_object *, struct nvkm_event *, +- int (*func)(struct nvkm_notify *), bool work, +- void *data, u32 size, u32 reply, +- struct nvkm_notify *); +-void nvkm_notify_fini(struct nvkm_notify *); +-void nvkm_notify_get(struct nvkm_notify *); +-void nvkm_notify_put(struct nvkm_notify *); +-void nvkm_notify_send(struct nvkm_notify *, void *data, u32 size); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/object.h b/drivers/gpu/drm/nouveau/core/include/core/object.h +deleted file mode 100644 +index d7039482..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/object.h ++++ /dev/null +@@ -1,223 +0,0 @@ +-#ifndef __NOUVEAU_OBJECT_H__ +-#define __NOUVEAU_OBJECT_H__ +- +-#include +-#include +- +-#define NV_PARENT_CLASS 0x80000000 +-#define NV_NAMEDB_CLASS 0x40000000 +-#define NV_CLIENT_CLASS 0x20000000 +-#define NV_SUBDEV_CLASS 0x10000000 +-#define NV_ENGINE_CLASS 0x08000000 +-#define NV_MEMOBJ_CLASS 0x04000000 +-#define NV_GPUOBJ_CLASS 0x02000000 +-#define NV_ENGCTX_CLASS 0x01000000 +-#define NV_OBJECT_CLASS 0x0000ffff +- +-struct nouveau_object { +- struct nouveau_oclass *oclass; +- struct nouveau_object *parent; +- struct nouveau_object *engine; +- atomic_t refcount; +- atomic_t usecount; +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +-#define NOUVEAU_OBJECT_MAGIC 0x75ef0bad +- struct list_head list; +- u32 _magic; +-#endif +-}; +- +-static inline struct nouveau_object * +-nv_object(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (likely(obj)) { +- struct nouveau_object *object = obj; +- if (unlikely(object->_magic != NOUVEAU_OBJECT_MAGIC)) +- nv_assert("BAD CAST -> NvObject, invalid magic"); +- } +-#endif +- return obj; +-} +- +-#define nouveau_object_create(p,e,c,s,d) \ +- nouveau_object_create_((p), (e), (c), (s), sizeof(**d), (void **)d) +-int nouveau_object_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32, int size, void **); +-void nouveau_object_destroy(struct nouveau_object *); +-int nouveau_object_init(struct nouveau_object *); +-int nouveau_object_fini(struct nouveau_object *, bool suspend); +- +-int _nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-extern struct nouveau_ofuncs nouveau_object_ofuncs; +- +-/* Don't allocate dynamically, because lockdep needs lock_class_keys to be in +- * ".data". */ +-struct nouveau_oclass { +- u32 handle; +- struct nouveau_ofuncs * const ofuncs; +- struct nouveau_omthds * const omthds; +- struct lock_class_key lock_class_key; +-}; +- +-#define nv_oclass(o) nv_object(o)->oclass +-#define nv_hclass(o) nv_oclass(o)->handle +-#define nv_iclass(o,i) (nv_hclass(o) & (i)) +-#define nv_mclass(o) nv_iclass(o, NV_OBJECT_CLASS) +- +-static inline struct nouveau_object * +-nv_pclass(struct nouveau_object *parent, u32 oclass) +-{ +- while (parent && !nv_iclass(parent, oclass)) +- parent = parent->parent; +- return parent; +-} +- +-struct nouveau_omthds { +- u32 start; +- u32 limit; +- int (*call)(struct nouveau_object *, u32, void *, u32); +-}; +- +-struct nvkm_event; +-struct nouveau_ofuncs { +- int (*ctor)(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *data, u32 size, +- struct nouveau_object **); +- void (*dtor)(struct nouveau_object *); +- int (*init)(struct nouveau_object *); +- int (*fini)(struct nouveau_object *, bool suspend); +- int (*mthd)(struct nouveau_object *, u32, void *, u32); +- int (*ntfy)(struct nouveau_object *, u32, struct nvkm_event **); +- int (* map)(struct nouveau_object *, u64 *, u32 *); +- u8 (*rd08)(struct nouveau_object *, u64 offset); +- u16 (*rd16)(struct nouveau_object *, u64 offset); +- u32 (*rd32)(struct nouveau_object *, u64 offset); +- void (*wr08)(struct nouveau_object *, u64 offset, u8 data); +- void (*wr16)(struct nouveau_object *, u64 offset, u16 data); +- void (*wr32)(struct nouveau_object *, u64 offset, u32 data); +-}; +- +-static inline struct nouveau_ofuncs * +-nv_ofuncs(void *obj) +-{ +- return nv_oclass(obj)->ofuncs; +-} +- +-int nouveau_object_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nouveau_object_ref(struct nouveau_object *, struct nouveau_object **); +-int nouveau_object_inc(struct nouveau_object *); +-int nouveau_object_dec(struct nouveau_object *, bool suspend); +- +-void nouveau_object_debug(void); +- +-static inline int +-nv_exec(void *obj, u32 mthd, void *data, u32 size) +-{ +- struct nouveau_omthds *method = nv_oclass(obj)->omthds; +- +- while (method && method->call) { +- if (mthd >= method->start && mthd <= method->limit) +- return method->call(obj, mthd, data, size); +- method++; +- } +- +- return -EINVAL; +-} +- +-static inline int +-nv_call(void *obj, u32 mthd, u32 data) +-{ +- return nv_exec(obj, mthd, &data, sizeof(data)); +-} +- +-static inline u8 +-nv_ro08(void *obj, u64 addr) +-{ +- u8 data = nv_ofuncs(obj)->rd08(obj, addr); +- nv_spam(obj, "nv_ro08 0x%08llx 0x%02x\n", addr, data); +- return data; +-} +- +-static inline u16 +-nv_ro16(void *obj, u64 addr) +-{ +- u16 data = nv_ofuncs(obj)->rd16(obj, addr); +- nv_spam(obj, "nv_ro16 0x%08llx 0x%04x\n", addr, data); +- return data; +-} +- +-static inline u32 +-nv_ro32(void *obj, u64 addr) +-{ +- u32 data = nv_ofuncs(obj)->rd32(obj, addr); +- nv_spam(obj, "nv_ro32 0x%08llx 0x%08x\n", addr, data); +- return data; +-} +- +-static inline void +-nv_wo08(void *obj, u64 addr, u8 data) +-{ +- nv_spam(obj, "nv_wo08 0x%08llx 0x%02x\n", addr, data); +- nv_ofuncs(obj)->wr08(obj, addr, data); +-} +- +-static inline void +-nv_wo16(void *obj, u64 addr, u16 data) +-{ +- nv_spam(obj, "nv_wo16 0x%08llx 0x%04x\n", addr, data); +- nv_ofuncs(obj)->wr16(obj, addr, data); +-} +- +-static inline void +-nv_wo32(void *obj, u64 addr, u32 data) +-{ +- nv_spam(obj, "nv_wo32 0x%08llx 0x%08x\n", addr, data); +- nv_ofuncs(obj)->wr32(obj, addr, data); +-} +- +-static inline u32 +-nv_mo32(void *obj, u64 addr, u32 mask, u32 data) +-{ +- u32 temp = nv_ro32(obj, addr); +- nv_wo32(obj, addr, (temp & ~mask) | data); +- return temp; +-} +- +-static inline int +-nv_memcmp(void *obj, u32 addr, const char *str, u32 len) +-{ +- unsigned char c1, c2; +- +- while (len--) { +- c1 = nv_ro08(obj, addr++); +- c2 = *(str++); +- if (c1 != c2) +- return c1 - c2; +- } +- return 0; +-} +- +-#include +- +-static inline int +-nouveau_object_new(struct nouveau_object *client, u32 parent, u32 handle, +- u16 oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- return nouveau_handle_new(client, parent, handle, oclass, +- data, size, pobject); +-} +- +-static inline int +-nouveau_object_del(struct nouveau_object *client, u32 parent, u32 handle) +-{ +- return nouveau_handle_del(client, parent, handle); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/option.h b/drivers/gpu/drm/nouveau/core/include/core/option.h +deleted file mode 100644 +index ed055847..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/option.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-#ifndef __NOUVEAU_OPTION_H__ +-#define __NOUVEAU_OPTION_H__ +- +-#include +- +-const char *nouveau_stropt(const char *optstr, const char *opt, int *len); +-bool nouveau_boolopt(const char *optstr, const char *opt, bool value); +- +-int nouveau_dbgopt(const char *optstr, const char *sub); +- +-/* compares unterminated string 'str' with zero-terminated string 'cmp' */ +-static inline int +-strncasecmpz(const char *str, const char *cmp, size_t len) +-{ +- if (strlen(cmp) != len) +- return len; +- return strncasecmp(str, cmp, len); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/parent.h b/drivers/gpu/drm/nouveau/core/include/core/parent.h +deleted file mode 100644 +index 12da418e..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/parent.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-#ifndef __NOUVEAU_PARENT_H__ +-#define __NOUVEAU_PARENT_H__ +- +-#include +-#include +- +-struct nouveau_sclass { +- struct nouveau_sclass *sclass; +- struct nouveau_engine *engine; +- struct nouveau_oclass *oclass; +-}; +- +-struct nouveau_parent { +- struct nouveau_object base; +- +- struct nouveau_sclass *sclass; +- u64 engine; +- +- int (*context_attach)(struct nouveau_object *, +- struct nouveau_object *); +- int (*context_detach)(struct nouveau_object *, bool suspend, +- struct nouveau_object *); +- +- int (*object_attach)(struct nouveau_object *parent, +- struct nouveau_object *object, u32 name); +- void (*object_detach)(struct nouveau_object *parent, int cookie); +-}; +- +-static inline struct nouveau_parent * +-nv_parent(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!(nv_iclass(obj, NV_PARENT_CLASS)))) +- nv_assert("BAD CAST -> NvParent, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-#define nouveau_parent_create(p,e,c,v,s,m,d) \ +- nouveau_parent_create_((p), (e), (c), (v), (s), (m), \ +- sizeof(**d), (void **)d) +-#define nouveau_parent_init(p) \ +- nouveau_object_init(&(p)->base) +-#define nouveau_parent_fini(p,s) \ +- nouveau_object_fini(&(p)->base, (s)) +- +-int nouveau_parent_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32 pclass, +- struct nouveau_oclass *, u64 engcls, +- int size, void **); +-void nouveau_parent_destroy(struct nouveau_parent *); +- +-void _nouveau_parent_dtor(struct nouveau_object *); +-#define _nouveau_parent_init nouveau_object_init +-#define _nouveau_parent_fini nouveau_object_fini +- +-int nouveau_parent_sclass(struct nouveau_object *, u16 handle, +- struct nouveau_object **pengine, +- struct nouveau_oclass **poclass); +-int nouveau_parent_lclass(struct nouveau_object *, u32 *, int); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/printk.h b/drivers/gpu/drm/nouveau/core/include/core/printk.h +deleted file mode 100644 +index 451b6ed2..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/printk.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-#ifndef __NOUVEAU_PRINTK_H__ +-#define __NOUVEAU_PRINTK_H__ +- +-#include +-#include +- +-struct nouveau_object; +- +-void __printf(3, 4) +-nv_printk_(struct nouveau_object *, int, const char *, ...); +- +-#define nv_printk(o,l,f,a...) do { \ +- if (NV_DBG_##l <= CONFIG_NOUVEAU_DEBUG) \ +- nv_printk_(nv_object(o), NV_DBG_##l, f, ##a); \ +-} while(0) +- +-#define nv_fatal(o,f,a...) nv_printk((o), FATAL, f, ##a) +-#define nv_error(o,f,a...) nv_printk((o), ERROR, f, ##a) +-#define nv_warn(o,f,a...) nv_printk((o), WARN, f, ##a) +-#define nv_info(o,f,a...) nv_printk((o), INFO, f, ##a) +-#define nv_debug(o,f,a...) nv_printk((o), DEBUG, f, ##a) +-#define nv_trace(o,f,a...) nv_printk((o), TRACE, f, ##a) +-#define nv_spam(o,f,a...) nv_printk((o), SPAM, f, ##a) +-#define nv_ioctl(o,f,a...) nv_trace(nouveau_client(o), "ioctl: "f, ##a) +- +-#define nv_assert(f,a...) do { \ +- if (NV_DBG_FATAL <= CONFIG_NOUVEAU_DEBUG) \ +- nv_printk_(NULL, NV_DBG_FATAL, f "\n", ##a); \ +- BUG_ON(1); \ +-} while(0) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/ramht.h b/drivers/gpu/drm/nouveau/core/include/core/ramht.h +deleted file mode 100644 +index 47e4cacb..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/ramht.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-#ifndef __NOUVEAU_RAMHT_H__ +-#define __NOUVEAU_RAMHT_H__ +- +-#include +- +-struct nouveau_ramht { +- struct nouveau_gpuobj base; +- int bits; +-}; +- +-int nouveau_ramht_insert(struct nouveau_ramht *, int chid, +- u32 handle, u32 context); +-void nouveau_ramht_remove(struct nouveau_ramht *, int cookie); +-int nouveau_ramht_new(struct nouveau_object *, struct nouveau_object *, +- u32 size, u32 align, struct nouveau_ramht **); +- +-static inline void +-nouveau_ramht_ref(struct nouveau_ramht *obj, struct nouveau_ramht **ref) +-{ +- nouveau_gpuobj_ref(&obj->base, (struct nouveau_gpuobj **)ref); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/core/subdev.h b/drivers/gpu/drm/nouveau/core/include/core/subdev.h +deleted file mode 100644 +index e9632e93..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/core/subdev.h ++++ /dev/null +@@ -1,118 +0,0 @@ +-#ifndef __NOUVEAU_SUBDEV_H__ +-#define __NOUVEAU_SUBDEV_H__ +- +-#include +- +-#define NV_SUBDEV_(sub,var) (NV_SUBDEV_CLASS | ((var) << 8) | (sub)) +-#define NV_SUBDEV(name,var) NV_SUBDEV_(NVDEV_SUBDEV_##name, (var)) +- +-struct nouveau_subdev { +- struct nouveau_object base; +- struct mutex mutex; +- const char *name; +- void __iomem *mmio; +- u32 debug; +- u32 unit; +- +- void (*intr)(struct nouveau_subdev *); +-}; +- +-static inline struct nouveau_subdev * +-nv_subdev(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_SUBDEV_CLASS))) +- nv_assert("BAD CAST -> NvSubDev, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-static inline int +-nv_subidx(struct nouveau_object *object) +-{ +- return nv_hclass(nv_subdev(object)) & 0xff; +-} +- +-#define nouveau_subdev_create(p,e,o,v,s,f,d) \ +- nouveau_subdev_create_((p), (e), (o), (v), (s), (f), \ +- sizeof(**d),(void **)d) +- +-int nouveau_subdev_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32 pclass, +- const char *sname, const char *fname, +- int size, void **); +-void nouveau_subdev_destroy(struct nouveau_subdev *); +-int nouveau_subdev_init(struct nouveau_subdev *); +-int nouveau_subdev_fini(struct nouveau_subdev *, bool suspend); +-void nouveau_subdev_reset(struct nouveau_object *); +- +-void _nouveau_subdev_dtor(struct nouveau_object *); +-int _nouveau_subdev_init(struct nouveau_object *); +-int _nouveau_subdev_fini(struct nouveau_object *, bool suspend); +- +-#define s_printk(s,l,f,a...) do { \ +- if ((s)->debug >= OS_DBG_##l) { \ +- nv_printk((s)->base.parent, (s)->name, l, f, ##a); \ +- } \ +-} while(0) +- +-static inline u8 +-nv_rd08(void *obj, u32 addr) +-{ +- struct nouveau_subdev *subdev = nv_subdev(obj); +- u8 data = ioread8(subdev->mmio + addr); +- nv_spam(subdev, "nv_rd08 0x%06x 0x%02x\n", addr, data); +- return data; +-} +- +-static inline u16 +-nv_rd16(void *obj, u32 addr) +-{ +- struct nouveau_subdev *subdev = nv_subdev(obj); +- u16 data = ioread16_native(subdev->mmio + addr); +- nv_spam(subdev, "nv_rd16 0x%06x 0x%04x\n", addr, data); +- return data; +-} +- +-static inline u32 +-nv_rd32(void *obj, u32 addr) +-{ +- struct nouveau_subdev *subdev = nv_subdev(obj); +- u32 data = ioread32_native(subdev->mmio + addr); +- nv_spam(subdev, "nv_rd32 0x%06x 0x%08x\n", addr, data); +- return data; +-} +- +-static inline void +-nv_wr08(void *obj, u32 addr, u8 data) +-{ +- struct nouveau_subdev *subdev = nv_subdev(obj); +- nv_spam(subdev, "nv_wr08 0x%06x 0x%02x\n", addr, data); +- iowrite8(data, subdev->mmio + addr); +-} +- +-static inline void +-nv_wr16(void *obj, u32 addr, u16 data) +-{ +- struct nouveau_subdev *subdev = nv_subdev(obj); +- nv_spam(subdev, "nv_wr16 0x%06x 0x%04x\n", addr, data); +- iowrite16_native(data, subdev->mmio + addr); +-} +- +-static inline void +-nv_wr32(void *obj, u32 addr, u32 data) +-{ +- struct nouveau_subdev *subdev = nv_subdev(obj); +- nv_spam(subdev, "nv_wr32 0x%06x 0x%08x\n", addr, data); +- iowrite32_native(data, subdev->mmio + addr); +-} +- +-static inline u32 +-nv_mask(void *obj, u32 addr, u32 mask, u32 data) +-{ +- u32 temp = nv_rd32(obj, addr); +- nv_wr32(obj, addr, (temp & ~mask) | data); +- return temp; +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h b/drivers/gpu/drm/nouveau/core/include/engine/bsp.h +deleted file mode 100644 +index 67662e2c..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/bsp.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NOUVEAU_BSP_H__ +-#define __NOUVEAU_BSP_H__ +- +-extern struct nouveau_oclass nv84_bsp_oclass; +-extern struct nouveau_oclass nv98_bsp_oclass; +-extern struct nouveau_oclass nvc0_bsp_oclass; +-extern struct nouveau_oclass nve0_bsp_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/copy.h b/drivers/gpu/drm/nouveau/core/include/engine/copy.h +deleted file mode 100644 +index 316a28ae..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/copy.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-#ifndef __NOUVEAU_COPY_H__ +-#define __NOUVEAU_COPY_H__ +- +-void nva3_copy_intr(struct nouveau_subdev *); +- +-extern struct nouveau_oclass nva3_copy_oclass; +-extern struct nouveau_oclass nvc0_copy0_oclass; +-extern struct nouveau_oclass nvc0_copy1_oclass; +-extern struct nouveau_oclass nve0_copy0_oclass; +-extern struct nouveau_oclass nve0_copy1_oclass; +-extern struct nouveau_oclass nve0_copy2_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h b/drivers/gpu/drm/nouveau/core/include/engine/crypt.h +deleted file mode 100644 +index db975618..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/crypt.h ++++ /dev/null +@@ -1,7 +0,0 @@ +-#ifndef __NOUVEAU_CRYPT_H__ +-#define __NOUVEAU_CRYPT_H__ +- +-extern struct nouveau_oclass nv84_crypt_oclass; +-extern struct nouveau_oclass nv98_crypt_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/device.h b/drivers/gpu/drm/nouveau/core/include/engine/device.h +deleted file mode 100644 +index 672d3c8f..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/device.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-#ifndef __NOUVEAU_SUBDEV_DEVICE_H__ +-#define __NOUVEAU_SUBDEV_DEVICE_H__ +- +-#include +- +-struct platform_device; +- +-enum nv_bus_type { +- NOUVEAU_BUS_PCI, +- NOUVEAU_BUS_PLATFORM, +-}; +- +-#define nouveau_device_create(p,t,n,s,c,d,u) \ +- nouveau_device_create_((void *)(p), (t), (n), (s), (c), (d), \ +- sizeof(**u), (void **)u) +- +-int nouveau_device_create_(void *, enum nv_bus_type type, u64 name, +- const char *sname, const char *cfg, const char *dbg, +- int, void **); +- +-int nv04_identify(struct nouveau_device *); +-int nv10_identify(struct nouveau_device *); +-int nv20_identify(struct nouveau_device *); +-int nv30_identify(struct nouveau_device *); +-int nv40_identify(struct nouveau_device *); +-int nv50_identify(struct nouveau_device *); +-int nvc0_identify(struct nouveau_device *); +-int nve0_identify(struct nouveau_device *); +-int gm100_identify(struct nouveau_device *); +- +-struct nouveau_device *nouveau_device_find(u64 name); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/disp.h b/drivers/gpu/drm/nouveau/core/include/engine/disp.h +deleted file mode 100644 +index 7a64f347..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/disp.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-#ifndef __NOUVEAU_DISP_H__ +-#define __NOUVEAU_DISP_H__ +- +-#include +-#include +-#include +-#include +- +-struct nouveau_disp { +- struct nouveau_engine base; +- +- struct list_head outp; +- +- struct nvkm_event hpd; +- struct nvkm_event vblank; +-}; +- +-static inline struct nouveau_disp * +-nouveau_disp(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_DISP]; +-} +- +-extern struct nouveau_oclass *nv04_disp_oclass; +-extern struct nouveau_oclass *nv50_disp_oclass; +-extern struct nouveau_oclass *nv84_disp_oclass; +-extern struct nouveau_oclass *nva0_disp_oclass; +-extern struct nouveau_oclass *nv94_disp_oclass; +-extern struct nouveau_oclass *nva3_disp_oclass; +-extern struct nouveau_oclass *nvd0_disp_oclass; +-extern struct nouveau_oclass *nve0_disp_oclass; +-extern struct nouveau_oclass *nvf0_disp_oclass; +-extern struct nouveau_oclass *gm107_disp_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h b/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h +deleted file mode 100644 +index 1b283a7b..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/dmaobj.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-#ifndef __NOUVEAU_DMAOBJ_H__ +-#define __NOUVEAU_DMAOBJ_H__ +- +-#include +-#include +- +-struct nouveau_gpuobj; +- +-struct nouveau_dmaobj { +- struct nouveau_object base; +- u32 target; +- u32 access; +- u64 start; +- u64 limit; +-}; +- +-struct nouveau_dmaeng { +- struct nouveau_engine base; +- +- /* creates a "physical" dma object from a struct nouveau_dmaobj */ +- int (*bind)(struct nouveau_dmaobj *dmaobj, +- struct nouveau_object *parent, +- struct nouveau_gpuobj **); +-}; +- +-extern struct nouveau_oclass *nv04_dmaeng_oclass; +-extern struct nouveau_oclass *nv50_dmaeng_oclass; +-extern struct nouveau_oclass *nvc0_dmaeng_oclass; +-extern struct nouveau_oclass *nvd0_dmaeng_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h b/drivers/gpu/drm/nouveau/core/include/engine/falcon.h +deleted file mode 100644 +index 181aa7da..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/falcon.h ++++ /dev/null +@@ -1,83 +0,0 @@ +-#ifndef __NOUVEAU_FALCON_H__ +-#define __NOUVEAU_FALCON_H__ +- +-#include +-#include +-#include +- +-struct nouveau_falcon_chan { +- struct nouveau_engctx base; +-}; +- +-#define nouveau_falcon_context_create(p,e,c,g,s,a,f,d) \ +- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +-#define nouveau_falcon_context_destroy(d) \ +- nouveau_engctx_destroy(&(d)->base) +-#define nouveau_falcon_context_init(d) \ +- nouveau_engctx_init(&(d)->base) +-#define nouveau_falcon_context_fini(d,s) \ +- nouveau_engctx_fini(&(d)->base, (s)) +- +-#define _nouveau_falcon_context_ctor _nouveau_engctx_ctor +-#define _nouveau_falcon_context_dtor _nouveau_engctx_dtor +-#define _nouveau_falcon_context_init _nouveau_engctx_init +-#define _nouveau_falcon_context_fini _nouveau_engctx_fini +-#define _nouveau_falcon_context_rd32 _nouveau_engctx_rd32 +-#define _nouveau_falcon_context_wr32 _nouveau_engctx_wr32 +- +-struct nouveau_falcon_data { +- bool external; +-}; +- +-struct nouveau_falcon { +- struct nouveau_engine base; +- +- u32 addr; +- u8 version; +- u8 secret; +- +- struct nouveau_gpuobj *core; +- bool external; +- +- struct { +- u32 limit; +- u32 *data; +- u32 size; +- } code; +- +- struct { +- u32 limit; +- u32 *data; +- u32 size; +- } data; +-}; +- +-#define nv_falcon(priv) (&(priv)->base) +- +-#define nouveau_falcon_create(p,e,c,b,d,i,f,r) \ +- nouveau_falcon_create_((p), (e), (c), (b), (d), (i), (f), \ +- sizeof(**r),(void **)r) +-#define nouveau_falcon_destroy(p) \ +- nouveau_engine_destroy(&(p)->base) +-#define nouveau_falcon_init(p) ({ \ +- struct nouveau_falcon *falcon = (p); \ +- _nouveau_falcon_init(nv_object(falcon)); \ +-}) +-#define nouveau_falcon_fini(p,s) ({ \ +- struct nouveau_falcon *falcon = (p); \ +- _nouveau_falcon_fini(nv_object(falcon), (s)); \ +-}) +- +-int nouveau_falcon_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32, bool, const char *, +- const char *, int, void **); +- +-void nouveau_falcon_intr(struct nouveau_subdev *subdev); +- +-#define _nouveau_falcon_dtor _nouveau_engine_dtor +-int _nouveau_falcon_init(struct nouveau_object *); +-int _nouveau_falcon_fini(struct nouveau_object *, bool); +-u32 _nouveau_falcon_rd32(struct nouveau_object *, u64); +-void _nouveau_falcon_wr32(struct nouveau_object *, u64, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h b/drivers/gpu/drm/nouveau/core/include/engine/fifo.h +deleted file mode 100644 +index 2007453f..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/fifo.h ++++ /dev/null +@@ -1,126 +0,0 @@ +-#ifndef __NOUVEAU_FIFO_H__ +-#define __NOUVEAU_FIFO_H__ +- +-#include +-#include +-#include +-#include +- +-struct nouveau_fifo_chan { +- struct nouveau_namedb base; +- struct nouveau_dmaobj *pushdma; +- struct nouveau_gpuobj *pushgpu; +- void __iomem *user; +- u64 addr; +- u32 size; +- u16 chid; +- atomic_t refcnt; /* NV04_NVSW_SET_REF */ +-}; +- +-static inline struct nouveau_fifo_chan * +-nouveau_fifo_chan(void *obj) +-{ +- return (void *)nv_namedb(obj); +-} +- +-#define nouveau_fifo_channel_create(p,e,c,b,a,s,n,m,d) \ +- nouveau_fifo_channel_create_((p), (e), (c), (b), (a), (s), (n), \ +- (m), sizeof(**d), (void **)d) +-#define nouveau_fifo_channel_init(p) \ +- nouveau_namedb_init(&(p)->base) +-#define nouveau_fifo_channel_fini(p,s) \ +- nouveau_namedb_fini(&(p)->base, (s)) +- +-int nouveau_fifo_channel_create_(struct nouveau_object *, +- struct nouveau_object *, +- struct nouveau_oclass *, +- int bar, u32 addr, u32 size, u32 push, +- u64 engmask, int len, void **); +-void nouveau_fifo_channel_destroy(struct nouveau_fifo_chan *); +- +-#define _nouveau_fifo_channel_init _nouveau_namedb_init +-#define _nouveau_fifo_channel_fini _nouveau_namedb_fini +- +-void _nouveau_fifo_channel_dtor(struct nouveau_object *); +-int _nouveau_fifo_channel_map(struct nouveau_object *, u64 *, u32 *); +-u32 _nouveau_fifo_channel_rd32(struct nouveau_object *, u64); +-void _nouveau_fifo_channel_wr32(struct nouveau_object *, u64, u32); +-int _nouveau_fifo_channel_ntfy(struct nouveau_object *, u32, struct nvkm_event **); +- +-struct nouveau_fifo_base { +- struct nouveau_gpuobj base; +-}; +- +-#define nouveau_fifo_context_create(p,e,c,g,s,a,f,d) \ +- nouveau_gpuobj_create((p), (e), (c), 0, (g), (s), (a), (f), (d)) +-#define nouveau_fifo_context_destroy(p) \ +- nouveau_gpuobj_destroy(&(p)->base) +-#define nouveau_fifo_context_init(p) \ +- nouveau_gpuobj_init(&(p)->base) +-#define nouveau_fifo_context_fini(p,s) \ +- nouveau_gpuobj_fini(&(p)->base, (s)) +- +-#define _nouveau_fifo_context_dtor _nouveau_gpuobj_dtor +-#define _nouveau_fifo_context_init _nouveau_gpuobj_init +-#define _nouveau_fifo_context_fini _nouveau_gpuobj_fini +-#define _nouveau_fifo_context_rd32 _nouveau_gpuobj_rd32 +-#define _nouveau_fifo_context_wr32 _nouveau_gpuobj_wr32 +- +-struct nouveau_fifo { +- struct nouveau_engine base; +- +- struct nvkm_event cevent; /* channel creation event */ +- struct nvkm_event uevent; /* async user trigger */ +- +- struct nouveau_object **channel; +- spinlock_t lock; +- u16 min; +- u16 max; +- +- int (*chid)(struct nouveau_fifo *, struct nouveau_object *); +- void (*pause)(struct nouveau_fifo *, unsigned long *); +- void (*start)(struct nouveau_fifo *, unsigned long *); +-}; +- +-static inline struct nouveau_fifo * +-nouveau_fifo(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_FIFO]; +-} +- +-#define nouveau_fifo_create(o,e,c,fc,lc,d) \ +- nouveau_fifo_create_((o), (e), (c), (fc), (lc), sizeof(**d), (void **)d) +-#define nouveau_fifo_init(p) \ +- nouveau_engine_init(&(p)->base) +-#define nouveau_fifo_fini(p,s) \ +- nouveau_engine_fini(&(p)->base, (s)) +- +-int nouveau_fifo_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int min, int max, +- int size, void **); +-void nouveau_fifo_destroy(struct nouveau_fifo *); +-const char * +-nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid); +- +-#define _nouveau_fifo_init _nouveau_engine_init +-#define _nouveau_fifo_fini _nouveau_engine_fini +- +-extern struct nouveau_oclass *nv04_fifo_oclass; +-extern struct nouveau_oclass *nv10_fifo_oclass; +-extern struct nouveau_oclass *nv17_fifo_oclass; +-extern struct nouveau_oclass *nv40_fifo_oclass; +-extern struct nouveau_oclass *nv50_fifo_oclass; +-extern struct nouveau_oclass *nv84_fifo_oclass; +-extern struct nouveau_oclass *nvc0_fifo_oclass; +-extern struct nouveau_oclass *nve0_fifo_oclass; +-extern struct nouveau_oclass *gk20a_fifo_oclass; +-extern struct nouveau_oclass *nv108_fifo_oclass; +- +-int nouveau_fifo_uevent_ctor(struct nouveau_object *, void *, u32, +- struct nvkm_notify *); +-void nouveau_fifo_uevent(struct nouveau_fifo *); +- +-void nv04_fifo_intr(struct nouveau_subdev *); +-int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/graph.h b/drivers/gpu/drm/nouveau/core/include/engine/graph.h +deleted file mode 100644 +index d5055570..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/graph.h ++++ /dev/null +@@ -1,86 +0,0 @@ +-#ifndef __NOUVEAU_GRAPH_H__ +-#define __NOUVEAU_GRAPH_H__ +- +-#include +-#include +-#include +- +-struct nouveau_graph_chan { +- struct nouveau_engctx base; +-}; +- +-#define nouveau_graph_context_create(p,e,c,g,s,a,f,d) \ +- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +-#define nouveau_graph_context_destroy(d) \ +- nouveau_engctx_destroy(&(d)->base) +-#define nouveau_graph_context_init(d) \ +- nouveau_engctx_init(&(d)->base) +-#define nouveau_graph_context_fini(d,s) \ +- nouveau_engctx_fini(&(d)->base, (s)) +- +-#define _nouveau_graph_context_dtor _nouveau_engctx_dtor +-#define _nouveau_graph_context_init _nouveau_engctx_init +-#define _nouveau_graph_context_fini _nouveau_engctx_fini +-#define _nouveau_graph_context_rd32 _nouveau_engctx_rd32 +-#define _nouveau_graph_context_wr32 _nouveau_engctx_wr32 +- +-struct nouveau_graph { +- struct nouveau_engine base; +- +- /* Returns chipset-specific counts of units packed into an u64. +- */ +- u64 (*units)(struct nouveau_graph *); +-}; +- +-static inline struct nouveau_graph * +-nouveau_graph(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_GR]; +-} +- +-#define nouveau_graph_create(p,e,c,y,d) \ +- nouveau_engine_create((p), (e), (c), (y), "PGRAPH", "graphics", (d)) +-#define nouveau_graph_destroy(d) \ +- nouveau_engine_destroy(&(d)->base) +-#define nouveau_graph_init(d) \ +- nouveau_engine_init(&(d)->base) +-#define nouveau_graph_fini(d,s) \ +- nouveau_engine_fini(&(d)->base, (s)) +- +-#define _nouveau_graph_dtor _nouveau_engine_dtor +-#define _nouveau_graph_init _nouveau_engine_init +-#define _nouveau_graph_fini _nouveau_engine_fini +- +-extern struct nouveau_oclass nv04_graph_oclass; +-extern struct nouveau_oclass nv10_graph_oclass; +-extern struct nouveau_oclass nv20_graph_oclass; +-extern struct nouveau_oclass nv25_graph_oclass; +-extern struct nouveau_oclass nv2a_graph_oclass; +-extern struct nouveau_oclass nv30_graph_oclass; +-extern struct nouveau_oclass nv34_graph_oclass; +-extern struct nouveau_oclass nv35_graph_oclass; +-extern struct nouveau_oclass nv40_graph_oclass; +-extern struct nouveau_oclass nv50_graph_oclass; +-extern struct nouveau_oclass *nvc0_graph_oclass; +-extern struct nouveau_oclass *nvc1_graph_oclass; +-extern struct nouveau_oclass *nvc4_graph_oclass; +-extern struct nouveau_oclass *nvc8_graph_oclass; +-extern struct nouveau_oclass *nvd7_graph_oclass; +-extern struct nouveau_oclass *nvd9_graph_oclass; +-extern struct nouveau_oclass *nve4_graph_oclass; +-extern struct nouveau_oclass *gk20a_graph_oclass; +-extern struct nouveau_oclass *nvf0_graph_oclass; +-extern struct nouveau_oclass *gk110b_graph_oclass; +-extern struct nouveau_oclass *nv108_graph_oclass; +-extern struct nouveau_oclass *gm107_graph_oclass; +- +-extern const struct nouveau_bitfield nv04_graph_nsource[]; +-extern struct nouveau_ofuncs nv04_graph_ofuncs; +-bool nv04_graph_idle(void *obj); +- +-extern const struct nouveau_bitfield nv10_graph_intr_name[]; +-extern const struct nouveau_bitfield nv10_graph_nstatus[]; +- +-extern const struct nouveau_enum nv50_data_error_names[]; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h b/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h +deleted file mode 100644 +index 9b0d9381..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/mpeg.h ++++ /dev/null +@@ -1,63 +0,0 @@ +-#ifndef __NOUVEAU_MPEG_H__ +-#define __NOUVEAU_MPEG_H__ +- +-#include +-#include +- +-struct nouveau_mpeg_chan { +- struct nouveau_engctx base; +-}; +- +-#define nouveau_mpeg_context_create(p,e,c,g,s,a,f,d) \ +- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d)) +-#define nouveau_mpeg_context_destroy(d) \ +- nouveau_engctx_destroy(&(d)->base) +-#define nouveau_mpeg_context_init(d) \ +- nouveau_engctx_init(&(d)->base) +-#define nouveau_mpeg_context_fini(d,s) \ +- nouveau_engctx_fini(&(d)->base, (s)) +- +-#define _nouveau_mpeg_context_dtor _nouveau_engctx_dtor +-#define _nouveau_mpeg_context_init _nouveau_engctx_init +-#define _nouveau_mpeg_context_fini _nouveau_engctx_fini +-#define _nouveau_mpeg_context_rd32 _nouveau_engctx_rd32 +-#define _nouveau_mpeg_context_wr32 _nouveau_engctx_wr32 +- +-struct nouveau_mpeg { +- struct nouveau_engine base; +-}; +- +-#define nouveau_mpeg_create(p,e,c,d) \ +- nouveau_engine_create((p), (e), (c), true, "PMPEG", "mpeg", (d)) +-#define nouveau_mpeg_destroy(d) \ +- nouveau_engine_destroy(&(d)->base) +-#define nouveau_mpeg_init(d) \ +- nouveau_engine_init(&(d)->base) +-#define nouveau_mpeg_fini(d,s) \ +- nouveau_engine_fini(&(d)->base, (s)) +- +-#define _nouveau_mpeg_dtor _nouveau_engine_dtor +-#define _nouveau_mpeg_init _nouveau_engine_init +-#define _nouveau_mpeg_fini _nouveau_engine_fini +- +-extern struct nouveau_oclass nv31_mpeg_oclass; +-extern struct nouveau_oclass nv40_mpeg_oclass; +-extern struct nouveau_oclass nv44_mpeg_oclass; +-extern struct nouveau_oclass nv50_mpeg_oclass; +-extern struct nouveau_oclass nv84_mpeg_oclass; +-extern struct nouveau_ofuncs nv31_mpeg_ofuncs; +-extern struct nouveau_oclass nv31_mpeg_cclass; +-extern struct nouveau_oclass nv31_mpeg_sclass[]; +-extern struct nouveau_oclass nv40_mpeg_sclass[]; +-void nv31_mpeg_intr(struct nouveau_subdev *); +-void nv31_mpeg_tile_prog(struct nouveau_engine *, int); +-int nv31_mpeg_init(struct nouveau_object *); +- +-extern struct nouveau_ofuncs nv50_mpeg_ofuncs; +-int nv50_mpeg_context_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv50_mpeg_intr(struct nouveau_subdev *); +-int nv50_mpeg_init(struct nouveau_object *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h b/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h +deleted file mode 100644 +index 88cc812b..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/perfmon.h ++++ /dev/null +@@ -1,38 +0,0 @@ +-#ifndef __NVKM_PERFMON_H__ +-#define __NVKM_PERFMON_H__ +- +-#include +-#include +-#include +- +-struct nouveau_perfdom; +-struct nouveau_perfctr; +-struct nouveau_perfmon { +- struct nouveau_engine base; +- +- struct nouveau_perfctx *context; +- void *profile_data; +- +- struct list_head domains; +- u32 sequence; +- +- /*XXX: temp for daemon backend */ +- u32 pwr[8]; +- u32 last; +-}; +- +-static inline struct nouveau_perfmon * +-nouveau_perfmon(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_PERFMON]; +-} +- +-extern struct nouveau_oclass *nv40_perfmon_oclass; +-extern struct nouveau_oclass *nv50_perfmon_oclass; +-extern struct nouveau_oclass *nv84_perfmon_oclass; +-extern struct nouveau_oclass *nva3_perfmon_oclass; +-extern struct nouveau_oclass nvc0_perfmon_oclass; +-extern struct nouveau_oclass nve0_perfmon_oclass; +-extern struct nouveau_oclass nvf0_perfmon_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h b/drivers/gpu/drm/nouveau/core/include/engine/ppp.h +deleted file mode 100644 +index 0a66781e..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/ppp.h ++++ /dev/null +@@ -1,7 +0,0 @@ +-#ifndef __NOUVEAU_PPP_H__ +-#define __NOUVEAU_PPP_H__ +- +-extern struct nouveau_oclass nv98_ppp_oclass; +-extern struct nouveau_oclass nvc0_ppp_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/software.h b/drivers/gpu/drm/nouveau/core/include/engine/software.h +deleted file mode 100644 +index 23a462b5..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/software.h ++++ /dev/null +@@ -1,51 +0,0 @@ +-#ifndef __NOUVEAU_SOFTWARE_H__ +-#define __NOUVEAU_SOFTWARE_H__ +- +-#include +-#include +- +-struct nouveau_software_chan { +- struct nouveau_engctx base; +- +- int (*flip)(void *); +- void *flip_data; +-}; +- +-#define nouveau_software_context_create(p,e,c,d) \ +- nouveau_engctx_create((p), (e), (c), (p), 0, 0, 0, (d)) +-#define nouveau_software_context_destroy(d) \ +- nouveau_engctx_destroy(&(d)->base) +-#define nouveau_software_context_init(d) \ +- nouveau_engctx_init(&(d)->base) +-#define nouveau_software_context_fini(d,s) \ +- nouveau_engctx_fini(&(d)->base, (s)) +- +-#define _nouveau_software_context_dtor _nouveau_engctx_dtor +-#define _nouveau_software_context_init _nouveau_engctx_init +-#define _nouveau_software_context_fini _nouveau_engctx_fini +- +-struct nouveau_software { +- struct nouveau_engine base; +-}; +- +-#define nouveau_software_create(p,e,c,d) \ +- nouveau_engine_create((p), (e), (c), true, "SW", "software", (d)) +-#define nouveau_software_destroy(d) \ +- nouveau_engine_destroy(&(d)->base) +-#define nouveau_software_init(d) \ +- nouveau_engine_init(&(d)->base) +-#define nouveau_software_fini(d,s) \ +- nouveau_engine_fini(&(d)->base, (s)) +- +-#define _nouveau_software_dtor _nouveau_engine_dtor +-#define _nouveau_software_init _nouveau_engine_init +-#define _nouveau_software_fini _nouveau_engine_fini +- +-extern struct nouveau_oclass *nv04_software_oclass; +-extern struct nouveau_oclass *nv10_software_oclass; +-extern struct nouveau_oclass *nv50_software_oclass; +-extern struct nouveau_oclass *nvc0_software_oclass; +- +-void nv04_software_intr(struct nouveau_subdev *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/vp.h b/drivers/gpu/drm/nouveau/core/include/engine/vp.h +deleted file mode 100644 +index 39baebec..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/vp.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NOUVEAU_VP_H__ +-#define __NOUVEAU_VP_H__ +- +-extern struct nouveau_oclass nv84_vp_oclass; +-extern struct nouveau_oclass nv98_vp_oclass; +-extern struct nouveau_oclass nvc0_vp_oclass; +-extern struct nouveau_oclass nve0_vp_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h b/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h +deleted file mode 100644 +index 306100f3..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/engine/xtensa.h ++++ /dev/null +@@ -1,38 +0,0 @@ +-#ifndef __NOUVEAU_XTENSA_H__ +-#define __NOUVEAU_XTENSA_H__ +- +-#include +-#include +-#include +- +-struct nouveau_xtensa { +- struct nouveau_engine base; +- +- u32 addr; +- struct nouveau_gpuobj *gpu_fw; +- u32 fifo_val; +- u32 unkd28; +-}; +- +-#define nouveau_xtensa_create(p,e,c,b,d,i,f,r) \ +- nouveau_xtensa_create_((p), (e), (c), (b), (d), (i), (f), \ +- sizeof(**r),(void **)r) +- +-int _nouveau_xtensa_engctx_ctor(struct nouveau_object *, +- struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-void _nouveau_xtensa_intr(struct nouveau_subdev *); +-int nouveau_xtensa_create_(struct nouveau_object *, +- struct nouveau_object *, +- struct nouveau_oclass *, u32, bool, +- const char *, const char *, +- int, void **); +-#define _nouveau_xtensa_dtor _nouveau_engine_dtor +-int _nouveau_xtensa_init(struct nouveau_object *); +-int _nouveau_xtensa_fini(struct nouveau_object *, bool); +-u32 _nouveau_xtensa_rd32(struct nouveau_object *, u64); +-void _nouveau_xtensa_wr32(struct nouveau_object *, u64, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/class.h b/drivers/gpu/drm/nouveau/core/include/nvif/class.h +deleted file mode 120000 +index f1ac4859..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/nvif/class.h ++++ /dev/null +@@ -1 +0,0 @@ +-../../../nvif/class.h +\ No newline at end of file +diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/event.h b/drivers/gpu/drm/nouveau/core/include/nvif/event.h +deleted file mode 120000 +index 1b798538..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/nvif/event.h ++++ /dev/null +@@ -1 +0,0 @@ +-../../../nvif/event.h +\ No newline at end of file +diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h b/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h +deleted file mode 120000 +index 8569c869..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/nvif/ioctl.h ++++ /dev/null +@@ -1 +0,0 @@ +-../../../nvif/ioctl.h +\ No newline at end of file +diff --git a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h b/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h +deleted file mode 120000 +index 69d99292..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/nvif/unpack.h ++++ /dev/null +@@ -1 +0,0 @@ +-../../../nvif/unpack.h +\ No newline at end of file +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h b/drivers/gpu/drm/nouveau/core/include/subdev/bar.h +deleted file mode 100644 +index 257ddf6d..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bar.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-#ifndef __NOUVEAU_BAR_H__ +-#define __NOUVEAU_BAR_H__ +- +-#include +-#include +- +-struct nouveau_mem; +-struct nouveau_vma; +- +-struct nouveau_bar { +- struct nouveau_subdev base; +- +- int (*alloc)(struct nouveau_bar *, struct nouveau_object *, +- struct nouveau_mem *, struct nouveau_object **); +- +- int (*kmap)(struct nouveau_bar *, struct nouveau_mem *, +- u32 flags, struct nouveau_vma *); +- int (*umap)(struct nouveau_bar *, struct nouveau_mem *, +- u32 flags, struct nouveau_vma *); +- void (*unmap)(struct nouveau_bar *, struct nouveau_vma *); +- void (*flush)(struct nouveau_bar *); +- +- /* whether the BAR supports to be ioremapped WC or should be uncached */ +- bool iomap_uncached; +-}; +- +-static inline struct nouveau_bar * +-nouveau_bar(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BAR]; +-} +- +-extern struct nouveau_oclass nv50_bar_oclass; +-extern struct nouveau_oclass nvc0_bar_oclass; +-extern struct nouveau_oclass gk20a_bar_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios.h +deleted file mode 100644 +index 5bd1ca8c..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-#ifndef __NOUVEAU_BIOS_H__ +-#define __NOUVEAU_BIOS_H__ +- +-#include +-#include +- +-struct nouveau_bios { +- struct nouveau_subdev base; +- u32 size; +- u8 *data; +- +- u32 bmp_offset; +- u32 bit_offset; +- +- struct { +- u8 major; +- u8 chip; +- u8 minor; +- u8 micro; +- u8 patch; +- } version; +-}; +- +-static inline struct nouveau_bios * +-nouveau_bios(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VBIOS]; +-} +- +-u8 nvbios_checksum(const u8 *data, int size); +-u16 nvbios_findstr(const u8 *data, int size, const char *str, int len); +- +-extern struct nouveau_oclass nouveau_bios_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h +deleted file mode 100644 +index e171120c..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0205.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-#ifndef __NVBIOS_M0205_H__ +-#define __NVBIOS_M0205_H__ +- +-struct nvbios_M0205T { +- u16 freq; +-}; +- +-u32 nvbios_M0205Te(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +-u32 nvbios_M0205Tp(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, +- struct nvbios_M0205T *); +- +-struct nvbios_M0205E { +- u8 type; +-}; +- +-u32 nvbios_M0205Ee(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u32 nvbios_M0205Ep(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_M0205E *); +- +-struct nvbios_M0205S { +- u8 data; +-}; +- +-u32 nvbios_M0205Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr); +-u32 nvbios_M0205Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr, +- struct nvbios_M0205S *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h +deleted file mode 100644 +index 67dc50d8..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/M0209.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-#ifndef __NVBIOS_M0209_H__ +-#define __NVBIOS_M0209_H__ +- +-u32 nvbios_M0209Te(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +- +-struct nvbios_M0209E { +- u8 v00_40; +- u8 bits; +- u8 modulo; +- u8 v02_40; +- u8 v02_07; +- u8 v03; +-}; +- +-u32 nvbios_M0209Ee(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u32 nvbios_M0209Ep(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_M0209E *); +- +-struct nvbios_M0209S { +- u32 data[0x200]; +-}; +- +-u32 nvbios_M0209Se(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr); +-u32 nvbios_M0209Sp(struct nouveau_bios *, int ent, int idx, u8 *ver, u8 *hdr, +- struct nvbios_M0209S *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h +deleted file mode 100644 +index bba01ab1..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/P0260.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-#ifndef __NVBIOS_P0260_H__ +-#define __NVBIOS_P0260_H__ +- +-u32 nvbios_P0260Te(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); +- +-struct nvbios_P0260E { +- u32 data; +-}; +- +-u32 nvbios_P0260Ee(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); +-u32 nvbios_P0260Ep(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, +- struct nvbios_P0260E *); +- +-struct nvbios_P0260X { +- u32 data; +-}; +- +-u32 nvbios_P0260Xe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); +-u32 nvbios_P0260Xp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, +- struct nvbios_P0260X *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h +deleted file mode 100644 +index 73f060b0..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bit.h ++++ /dev/null +@@ -1,13 +0,0 @@ +-#ifndef __NVBIOS_BIT_H__ +-#define __NVBIOS_BIT_H__ +- +-struct bit_entry { +- u8 id; +- u8 version; +- u16 length; +- u16 offset; +-}; +- +-int bit_entry(struct nouveau_bios *, u8 id, struct bit_entry *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h +deleted file mode 100644 +index 10e4dbca..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/bmp.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-#ifndef __NVBIOS_BMP_H__ +-#define __NVBIOS_BMP_H__ +- +-static inline u16 +-bmp_version(struct nouveau_bios *bios) +-{ +- if (bios->bmp_offset) { +- return nv_ro08(bios, bios->bmp_offset + 5) << 8 | +- nv_ro08(bios, bios->bmp_offset + 6); +- } +- +- return 0x0000; +-} +- +-static inline u16 +-bmp_mem_init_table(struct nouveau_bios *bios) +-{ +- if (bmp_version(bios) >= 0x0300) +- return nv_ro16(bios, bios->bmp_offset + 24); +- return 0x0000; +-} +- +-static inline u16 +-bmp_sdr_seq_table(struct nouveau_bios *bios) +-{ +- if (bmp_version(bios) >= 0x0300) +- return nv_ro16(bios, bios->bmp_offset + 26); +- return 0x0000; +-} +- +-static inline u16 +-bmp_ddr_seq_table(struct nouveau_bios *bios) +-{ +- if (bmp_version(bios) >= 0x0300) +- return nv_ro16(bios, bios->bmp_offset + 28); +- return 0x0000; +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h +deleted file mode 100644 +index 662b2072..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h ++++ /dev/null +@@ -1,29 +0,0 @@ +-#ifndef __NVBIOS_BOOST_H__ +-#define __NVBIOS_BOOST_H__ +- +-u16 nvbios_boostTe(struct nouveau_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *); +- +-struct nvbios_boostE { +- u8 pstate; +- u32 min; +- u32 max; +-}; +- +-u16 nvbios_boostEe(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *); +-u16 nvbios_boostEp(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *, +- struct nvbios_boostE *); +-u16 nvbios_boostEm(struct nouveau_bios *, u8, u8 *, u8 *, u8 *, u8 *, +- struct nvbios_boostE *); +- +-struct nvbios_boostS { +- u8 domain; +- u8 percent; +- u32 min; +- u32 max; +-}; +- +-u16 nvbios_boostSe(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8); +-u16 nvbios_boostSp(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8, +- struct nvbios_boostS *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h +deleted file mode 100644 +index f3930c27..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/conn.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-#ifndef __NVBIOS_CONN_H__ +-#define __NVBIOS_CONN_H__ +- +-enum dcb_connector_type { +- DCB_CONNECTOR_VGA = 0x00, +- DCB_CONNECTOR_TV_0 = 0x10, +- DCB_CONNECTOR_TV_1 = 0x11, +- DCB_CONNECTOR_TV_3 = 0x13, +- DCB_CONNECTOR_DVI_I = 0x30, +- DCB_CONNECTOR_DVI_D = 0x31, +- DCB_CONNECTOR_DMS59_0 = 0x38, +- DCB_CONNECTOR_DMS59_1 = 0x39, +- DCB_CONNECTOR_LVDS = 0x40, +- DCB_CONNECTOR_LVDS_SPWG = 0x41, +- DCB_CONNECTOR_DP = 0x46, +- DCB_CONNECTOR_eDP = 0x47, +- DCB_CONNECTOR_HDMI_0 = 0x60, +- DCB_CONNECTOR_HDMI_1 = 0x61, +- DCB_CONNECTOR_HDMI_C = 0x63, +- DCB_CONNECTOR_DMS59_DP0 = 0x64, +- DCB_CONNECTOR_DMS59_DP1 = 0x65, +- DCB_CONNECTOR_NONE = 0xff +-}; +- +-struct nvbios_connT { +-}; +- +-u32 nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u32 nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_connT *info); +- +-struct nvbios_connE { +- u8 type; +- u8 location; +- u8 hpd; +- u8 dp; +- u8 di; +- u8 sr; +- u8 lcdid; +-}; +- +-u32 nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr); +-u32 nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *hdr, +- struct nvbios_connE *info); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h +deleted file mode 100644 +index a80a4380..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-#ifndef __NVBIOS_CSTEP_H__ +-#define __NVBIOS_CSTEP_H__ +- +-u16 nvbios_cstepTe(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz); +- +-struct nvbios_cstepE { +- u8 pstate; +- u8 index; +-}; +- +-u16 nvbios_cstepEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); +-u16 nvbios_cstepEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, +- struct nvbios_cstepE *); +-u16 nvbios_cstepEm(struct nouveau_bios *, u8 pstate, u8 *ver, u8 *hdr, +- struct nvbios_cstepE *); +- +-struct nvbios_cstepX { +- u32 freq; +- u8 unkn[2]; +- u8 voltage; +-}; +- +-u16 nvbios_cstepXe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr); +-u16 nvbios_cstepXp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr, +- struct nvbios_cstepX *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h +deleted file mode 100644 +index 123270e9..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dcb.h ++++ /dev/null +@@ -1,69 +0,0 @@ +-#ifndef __NVBIOS_DCB_H__ +-#define __NVBIOS_DCB_H__ +- +-struct nouveau_bios; +- +-enum dcb_output_type { +- DCB_OUTPUT_ANALOG = 0x0, +- DCB_OUTPUT_TV = 0x1, +- DCB_OUTPUT_TMDS = 0x2, +- DCB_OUTPUT_LVDS = 0x3, +- DCB_OUTPUT_DP = 0x6, +- DCB_OUTPUT_EOL = 0xe, +- DCB_OUTPUT_UNUSED = 0xf, +- DCB_OUTPUT_ANY = -1, +-}; +- +-struct dcb_output { +- int index; /* may not be raw dcb index if merging has happened */ +- u16 hasht; +- u16 hashm; +- enum dcb_output_type type; +- uint8_t i2c_index; +- uint8_t heads; +- uint8_t connector; +- uint8_t bus; +- uint8_t location; +- uint8_t or; +- uint8_t link; +- bool duallink_possible; +- uint8_t extdev; +- union { +- struct sor_conf { +- int link; +- } sorconf; +- struct { +- int maxfreq; +- } crtconf; +- struct { +- struct sor_conf sor; +- bool use_straps_for_mode; +- bool use_acpi_for_edid; +- bool use_power_scripts; +- } lvdsconf; +- struct { +- bool has_component_output; +- } tvconf; +- struct { +- struct sor_conf sor; +- int link_nr; +- int link_bw; +- } dpconf; +- struct { +- struct sor_conf sor; +- int slave_addr; +- } tmdsconf; +- }; +- bool i2c_upper_default; +-}; +- +-u16 dcb_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *ent, u8 *len); +-u16 dcb_outp(struct nouveau_bios *, u8 idx, u8 *ver, u8 *len); +-u16 dcb_outp_parse(struct nouveau_bios *, u8 idx, u8 *, u8 *, +- struct dcb_output *); +-u16 dcb_outp_match(struct nouveau_bios *, u16 type, u16 mask, u8 *, u8 *, +- struct dcb_output *); +-int dcb_outp_foreach(struct nouveau_bios *, void *data, int (*exec) +- (struct nouveau_bios *, void *, int index, u16 entry)); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h +deleted file mode 100644 +index c35937e2..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/disp.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-#ifndef __NVBIOS_DISP_H__ +-#define __NVBIOS_DISP_H__ +- +-u16 nvbios_disp_table(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub); +- +-struct nvbios_disp { +- u16 data; +-}; +- +-u16 nvbios_disp_entry(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr__, u8 *sub); +-u16 nvbios_disp_parse(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr__, u8 *sub, +- struct nvbios_disp *); +- +-struct nvbios_outp { +- u16 type; +- u16 mask; +- u16 script[3]; +-}; +- +-u16 nvbios_outp_entry(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 nvbios_outp_parse(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_outp *); +-u16 nvbios_outp_match(struct nouveau_bios *, u16 type, u16 mask, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_outp *); +- +- +-struct nvbios_ocfg { +- u16 match; +- u16 clkcmp[2]; +-}; +- +-u16 nvbios_ocfg_entry(struct nouveau_bios *, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 nvbios_ocfg_parse(struct nouveau_bios *, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ocfg *); +-u16 nvbios_ocfg_match(struct nouveau_bios *, u16 outp, u16 type, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ocfg *); +-u16 nvbios_oclk_match(struct nouveau_bios *, u16 cmp, u32 khz); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h +deleted file mode 100644 +index 728206e2..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/dp.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-#ifndef __NVBIOS_DP_H__ +-#define __NVBIOS_DP_H__ +- +-struct nvbios_dpout { +- u16 type; +- u16 mask; +- u8 flags; +- u32 script[5]; +- u32 lnkcmp; +-}; +- +-u16 nvbios_dpout_parse(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpout *); +-u16 nvbios_dpout_match(struct nouveau_bios *, u16 type, u16 mask, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpout *); +- +-struct nvbios_dpcfg { +- u8 pc; +- u8 dc; +- u8 pe; +- u8 tx_pu; +-}; +- +-u16 +-nvbios_dpcfg_parse(struct nouveau_bios *, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpcfg *); +-u16 +-nvbios_dpcfg_match(struct nouveau_bios *, u16 outp, u8 pc, u8 vs, u8 pe, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpcfg *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h +deleted file mode 100644 +index 949fee3a..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/extdev.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-#ifndef __NVBIOS_EXTDEV_H__ +-#define __NVBIOS_EXTDEV_H__ +- +-struct nouveau_bios; +- +-enum nvbios_extdev_type { +- NVBIOS_EXTDEV_LM89 = 0x02, +- NVBIOS_EXTDEV_VT1103M = 0x40, +- NVBIOS_EXTDEV_PX3540 = 0x41, +- NVBIOS_EXTDEV_VT1105M = 0x42, /* or close enough... */ +- NVBIOS_EXTDEV_ADT7473 = 0x70, /* can also be a LM64 */ +- NVBIOS_EXTDEV_HDCP_EEPROM = 0x90, +- NVBIOS_EXTDEV_NONE = 0xff, +-}; +- +-struct nvbios_extdev_func { +- u8 type; +- u8 addr; +- u8 bus; +-}; +- +-int +-nvbios_extdev_parse(struct nouveau_bios *, int, struct nvbios_extdev_func *); +- +-int +-nvbios_extdev_find(struct nouveau_bios *, enum nvbios_extdev_type, +- struct nvbios_extdev_func *); +- +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h +deleted file mode 100644 +index 119d0874..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/fan.h ++++ /dev/null +@@ -1,8 +0,0 @@ +-#ifndef __NVBIOS_FAN_H__ +-#define __NVBIOS_FAN_H__ +- +-#include +- +-u16 nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h +deleted file mode 100644 +index c7b2e586..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-#ifndef __NVBIOS_GPIO_H__ +-#define __NVBIOS_GPIO_H__ +- +-enum dcb_gpio_func_name { +- DCB_GPIO_PANEL_POWER = 0x01, +- DCB_GPIO_TVDAC0 = 0x0c, +- DCB_GPIO_TVDAC1 = 0x2d, +- DCB_GPIO_FAN = 0x09, +- DCB_GPIO_FAN_SENSE = 0x3d, +- DCB_GPIO_UNUSED = 0xff, +- DCB_GPIO_VID0 = 0x04, +- DCB_GPIO_VID1 = 0x05, +- DCB_GPIO_VID2 = 0x06, +- DCB_GPIO_VID3 = 0x1a, +- DCB_GPIO_VID4 = 0x73, +- DCB_GPIO_VID5 = 0x74, +- DCB_GPIO_VID6 = 0x75, +- DCB_GPIO_VID7 = 0x76, +-}; +- +-#define DCB_GPIO_LOG_DIR 0x02 +-#define DCB_GPIO_LOG_DIR_OUT 0x00 +-#define DCB_GPIO_LOG_DIR_IN 0x02 +-#define DCB_GPIO_LOG_VAL 0x01 +-#define DCB_GPIO_LOG_VAL_LO 0x00 +-#define DCB_GPIO_LOG_VAL_HI 0x01 +- +-struct dcb_gpio_func { +- u8 func; +- u8 line; +- u8 log[2]; +- +- /* so far, "param" seems to only have an influence on PWM-related +- * GPIOs such as FAN_CONTROL and PANEL_BACKLIGHT_LEVEL. +- * if param equals 1, hardware PWM is available +- * if param equals 0, the host should toggle the GPIO itself +- */ +- u8 param; +-}; +- +-u16 dcb_gpio_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 dcb_gpio_entry(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len); +-u16 dcb_gpio_parse(struct nouveau_bios *, int idx, int ent, u8 *ver, u8 *len, +- struct dcb_gpio_func *); +-u16 dcb_gpio_match(struct nouveau_bios *, int idx, u8 func, u8 line, +- u8 *ver, u8 *len, struct dcb_gpio_func *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h +deleted file mode 100644 +index 10b57a19..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/i2c.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-#ifndef __NVBIOS_I2C_H__ +-#define __NVBIOS_I2C_H__ +- +-struct nouveau_bios; +- +-enum dcb_i2c_type { +- DCB_I2C_NV04_BIT = 0, +- DCB_I2C_NV4E_BIT = 4, +- DCB_I2C_NVIO_BIT = 5, +- DCB_I2C_NVIO_AUX = 6, +- DCB_I2C_UNUSED = 0xff +-}; +- +-struct dcb_i2c_entry { +- enum dcb_i2c_type type; +- u8 drive; +- u8 sense; +- u8 share; +-}; +- +-u16 dcb_i2c_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 dcb_i2c_entry(struct nouveau_bios *, u8 index, u8 *ver, u8 *len); +-int dcb_i2c_parse(struct nouveau_bios *, u8 index, struct dcb_i2c_entry *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h +deleted file mode 100644 +index ca2f6bf3..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/init.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-#ifndef __NVBIOS_INIT_H__ +-#define __NVBIOS_INIT_H__ +- +-struct nvbios_init { +- struct nouveau_subdev *subdev; +- struct nouveau_bios *bios; +- u16 offset; +- struct dcb_output *outp; +- int crtc; +- +- /* internal state used during parsing */ +- u8 execute; +- u32 nested; +- u16 repeat; +- u16 repend; +- u32 ramcfg; +-}; +- +-int nvbios_exec(struct nvbios_init *); +-int nvbios_init(struct nouveau_subdev *, bool execute); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h +deleted file mode 100644 +index 5572e604..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/mxm.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NVBIOS_MXM_H__ +-#define __NVBIOS_MXM_H__ +- +-u16 mxm_table(struct nouveau_bios *, u8 *ver, u8 *hdr); +- +-u8 mxm_sor_map(struct nouveau_bios *, u8 conn); +-u8 mxm_ddc_map(struct nouveau_bios *, u8 port); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h +deleted file mode 100644 +index 16ff06ec..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-#ifndef __NVBIOS_PERF_H__ +-#define __NVBIOS_PERF_H__ +- +-struct nouveau_bios; +- +-u16 nvbios_perf_table(struct nouveau_bios *, u8 *ver, u8 *hdr, +- u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +- +-struct nvbios_perfE { +- u8 pstate; +- u8 fanspeed; +- u8 voltage; +- u32 core; +- u32 shader; +- u32 memory; +- u32 vdec; +- u32 disp; +- u32 script; +-}; +- +-u16 nvbios_perf_entry(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 nvbios_perfEp(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *); +- +-struct nvbios_perfS { +- union { +- struct { +- u32 freq; +- } v40; +- }; +-}; +- +-u32 nvbios_perfSe(struct nouveau_bios *, u32 data, int idx, +- u8 *ver, u8 *hdr, u8 cnt, u8 len); +-u32 nvbios_perfSp(struct nouveau_bios *, u32 data, int idx, +- u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *); +- +-struct nvbios_perf_fan { +- u32 pwm_divisor; +-}; +- +-int +-nvbios_perf_fan_parse(struct nouveau_bios *, struct nvbios_perf_fan *); +- +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h +deleted file mode 100644 +index b2f3d4d0..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/pll.h ++++ /dev/null +@@ -1,79 +0,0 @@ +-#ifndef __NVBIOS_PLL_H__ +-#define __NVBIOS_PLL_H__ +- +-/*XXX: kill me */ +-struct nouveau_pll_vals { +- union { +- struct { +-#ifdef __BIG_ENDIAN +- uint8_t N1, M1, N2, M2; +-#else +- uint8_t M1, N1, M2, N2; +-#endif +- }; +- struct { +- uint16_t NM1, NM2; +- } __attribute__((packed)); +- }; +- int log2P; +- +- int refclk; +-}; +- +-struct nouveau_bios; +- +-/* these match types in pll limits table version 0x40, +- * nouveau uses them on all chipsets internally where a +- * specific pll needs to be referenced, but the exact +- * register isn't known. +- */ +-enum nvbios_pll_type { +- PLL_CORE = 0x01, +- PLL_SHADER = 0x02, +- PLL_UNK03 = 0x03, +- PLL_MEMORY = 0x04, +- PLL_VDEC = 0x05, +- PLL_UNK40 = 0x40, +- PLL_UNK41 = 0x41, +- PLL_UNK42 = 0x42, +- PLL_VPLL0 = 0x80, +- PLL_VPLL1 = 0x81, +- PLL_VPLL2 = 0x82, +- PLL_VPLL3 = 0x83, +- PLL_MAX = 0xff +-}; +- +-struct nvbios_pll { +- enum nvbios_pll_type type; +- u32 reg; +- u32 refclk; +- +- u8 min_p; +- u8 max_p; +- u8 bias_p; +- +- /* +- * for most pre nv50 cards setting a log2P of 7 (the common max_log2p +- * value) is no different to 6 (at least for vplls) so allowing the MNP +- * calc to use 7 causes the generated clock to be out by a factor of 2. +- * however, max_log2p cannot be fixed-up during parsing as the +- * unmodified max_log2p value is still needed for setting mplls, hence +- * an additional max_usable_log2p member +- */ +- u8 max_p_usable; +- +- struct { +- u32 min_freq; +- u32 max_freq; +- u32 min_inputfreq; +- u32 max_inputfreq; +- u8 min_m; +- u8 max_m; +- u8 min_n; +- u8 max_n; +- } vco1, vco2; +-}; +- +-int nvbios_pll_parse(struct nouveau_bios *, u32 type, struct nvbios_pll *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h +deleted file mode 100644 +index a685bbd0..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h ++++ /dev/null +@@ -1,124 +0,0 @@ +-#ifndef __NVBIOS_RAMCFG_H__ +-#define __NVBIOS_RAMCFG_H__ +- +-struct nouveau_bios; +- +-struct nvbios_ramcfg { +- unsigned rammap_ver; +- unsigned rammap_hdr; +- unsigned rammap_min; +- unsigned rammap_max; +- union { +- struct { +- unsigned rammap_10_04_02:1; +- unsigned rammap_10_04_08:1; +- }; +- struct { +- unsigned rammap_11_08_01:1; +- unsigned rammap_11_08_0c:2; +- unsigned rammap_11_08_10:1; +- unsigned rammap_11_09_01ff:9; +- unsigned rammap_11_0a_03fe:9; +- unsigned rammap_11_0a_0400:1; +- unsigned rammap_11_0a_0800:1; +- unsigned rammap_11_0b_01f0:5; +- unsigned rammap_11_0b_0200:1; +- unsigned rammap_11_0b_0400:1; +- unsigned rammap_11_0b_0800:1; +- unsigned rammap_11_0d:8; +- unsigned rammap_11_0e:8; +- unsigned rammap_11_0f:8; +- unsigned rammap_11_11_0c:2; +- }; +- }; +- +- unsigned ramcfg_ver; +- unsigned ramcfg_hdr; +- unsigned ramcfg_timing; +- union { +- struct { +- unsigned ramcfg_10_02_01:1; +- unsigned ramcfg_10_02_02:1; +- unsigned ramcfg_10_02_04:1; +- unsigned ramcfg_10_02_08:1; +- unsigned ramcfg_10_02_10:1; +- unsigned ramcfg_10_02_20:1; +- unsigned ramcfg_10_02_40:1; +- unsigned ramcfg_10_03_0f:4; +- unsigned ramcfg_10_05:8; +- unsigned ramcfg_10_06:8; +- unsigned ramcfg_10_07:8; +- unsigned ramcfg_10_08:8; +- unsigned ramcfg_10_09_0f:4; +- unsigned ramcfg_10_09_f0:4; +- }; +- struct { +- unsigned ramcfg_11_01_01:1; +- unsigned ramcfg_11_01_02:1; +- unsigned ramcfg_11_01_04:1; +- unsigned ramcfg_11_01_08:1; +- unsigned ramcfg_11_01_10:1; +- unsigned ramcfg_11_01_20:1; +- unsigned ramcfg_11_01_40:1; +- unsigned ramcfg_11_01_80:1; +- unsigned ramcfg_11_02_03:2; +- unsigned ramcfg_11_02_04:1; +- unsigned ramcfg_11_02_08:1; +- unsigned ramcfg_11_02_10:1; +- unsigned ramcfg_11_02_40:1; +- unsigned ramcfg_11_02_80:1; +- unsigned ramcfg_11_03_0f:4; +- unsigned ramcfg_11_03_30:2; +- unsigned ramcfg_11_03_c0:2; +- unsigned ramcfg_11_03_f0:4; +- unsigned ramcfg_11_04:8; +- unsigned ramcfg_11_06:8; +- unsigned ramcfg_11_07_02:1; +- unsigned ramcfg_11_07_04:1; +- unsigned ramcfg_11_07_08:1; +- unsigned ramcfg_11_07_10:1; +- unsigned ramcfg_11_07_40:1; +- unsigned ramcfg_11_07_80:1; +- unsigned ramcfg_11_08_01:1; +- unsigned ramcfg_11_08_02:1; +- unsigned ramcfg_11_08_04:1; +- unsigned ramcfg_11_08_08:1; +- unsigned ramcfg_11_08_10:1; +- unsigned ramcfg_11_08_20:1; +- unsigned ramcfg_11_09:8; +- }; +- }; +- +- unsigned timing_ver; +- unsigned timing_hdr; +- unsigned timing[11]; +- union { +- struct { +- unsigned timing_10_WR:8; +- unsigned timing_10_CL:8; +- unsigned timing_10_ODT:3; +- unsigned timing_10_CWL:8; +- }; +- struct { +- unsigned timing_20_2e_03:2; +- unsigned timing_20_2e_30:2; +- unsigned timing_20_2e_c0:2; +- unsigned timing_20_2f_03:2; +- unsigned timing_20_2c_003f:6; +- unsigned timing_20_2c_1fc0:7; +- unsigned timing_20_30_f8:5; +- unsigned timing_20_30_07:3; +- unsigned timing_20_31_0007:3; +- unsigned timing_20_31_0078:4; +- unsigned timing_20_31_0780:4; +- unsigned timing_20_31_0800:1; +- unsigned timing_20_31_7000:3; +- unsigned timing_20_31_8000:1; +- }; +- }; +-}; +- +-u8 nvbios_ramcfg_count(struct nouveau_bios *); +-u8 nvbios_ramcfg_index(struct nouveau_subdev *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h +deleted file mode 100644 +index 47e021d3..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-#ifndef __NVBIOS_RAMMAP_H__ +-#define __NVBIOS_RAMMAP_H__ +- +-struct nvbios_ramcfg; +- +-u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr, +- u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +- +-u32 nvbios_rammapEe(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u32 nvbios_rammapEp(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ramcfg *); +-u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ramcfg *); +- +-u32 nvbios_rammapSe(struct nouveau_bios *, u32 data, +- u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, +- u8 *ver, u8 *hdr); +-u32 nvbios_rammapSp(struct nouveau_bios *, u32 data, +- u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, +- u8 *ver, u8 *hdr, +- struct nvbios_ramcfg *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h +deleted file mode 100644 +index 295d093f..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/therm.h ++++ /dev/null +@@ -1,77 +0,0 @@ +-#ifndef __NVBIOS_THERM_H__ +-#define __NVBIOS_THERM_H__ +- +-struct nouveau_bios; +- +-struct nvbios_therm_threshold { +- u8 temp; +- u8 hysteresis; +-}; +- +-struct nvbios_therm_sensor { +- /* diode */ +- s16 slope_mult; +- s16 slope_div; +- s16 offset_num; +- s16 offset_den; +- s8 offset_constant; +- +- /* thresholds */ +- struct nvbios_therm_threshold thrs_fan_boost; +- struct nvbios_therm_threshold thrs_down_clock; +- struct nvbios_therm_threshold thrs_critical; +- struct nvbios_therm_threshold thrs_shutdown; +-}; +- +-enum nvbios_therm_fan_type { +- NVBIOS_THERM_FAN_UNK = 0, +- NVBIOS_THERM_FAN_TOGGLE = 1, +- NVBIOS_THERM_FAN_PWM = 2, +-}; +- +-/* no vbios have more than 6 */ +-#define NOUVEAU_TEMP_FAN_TRIP_MAX 10 +-struct nouveau_therm_trip_point { +- int fan_duty; +- int temp; +- int hysteresis; +-}; +- +-enum nvbios_therm_fan_mode { +- NVBIOS_THERM_FAN_TRIP = 0, +- NVBIOS_THERM_FAN_LINEAR = 1, +- NVBIOS_THERM_FAN_OTHER = 2, +-}; +- +-struct nvbios_therm_fan { +- enum nvbios_therm_fan_type type; +- +- u32 pwm_freq; +- +- u8 min_duty; +- u8 max_duty; +- +- u16 bump_period; +- u16 slow_down_period; +- +- enum nvbios_therm_fan_mode fan_mode; +- struct nouveau_therm_trip_point trip[NOUVEAU_TEMP_FAN_TRIP_MAX]; +- u8 nr_fan_trip; +- u8 linear_min_temp; +- u8 linear_max_temp; +-}; +- +-enum nvbios_therm_domain { +- NVBIOS_THERM_DOMAIN_CORE, +- NVBIOS_THERM_DOMAIN_AMBIENT, +-}; +- +-int +-nvbios_therm_sensor_parse(struct nouveau_bios *, enum nvbios_therm_domain, +- struct nvbios_therm_sensor *); +- +-int +-nvbios_therm_fan_parse(struct nouveau_bios *, struct nvbios_therm_fan *); +- +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h +deleted file mode 100644 +index 76d914b6..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h ++++ /dev/null +@@ -1,14 +0,0 @@ +-#ifndef __NVBIOS_TIMING_H__ +-#define __NVBIOS_TIMING_H__ +- +-struct nvbios_ramcfg; +- +-u16 nvbios_timingTe(struct nouveau_bios *, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz); +-u16 nvbios_timingEe(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 nvbios_timingEp(struct nouveau_bios *, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ramcfg *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h +deleted file mode 100644 +index ad5a8f20..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-#ifndef __NVBIOS_VMAP_H__ +-#define __NVBIOS_VMAP_H__ +- +-struct nouveau_bios; +- +-struct nvbios_vmap { +-}; +- +-u16 nvbios_vmap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 nvbios_vmap_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_vmap *); +- +-struct nvbios_vmap_entry { +- u8 unk0; +- u8 link; +- u32 min; +- u32 max; +- s32 arg[6]; +-}; +- +-u16 nvbios_vmap_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len); +-u16 nvbios_vmap_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len, +- struct nvbios_vmap_entry *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h +deleted file mode 100644 +index 6a11dcd5..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-#ifndef __NVBIOS_VOLT_H__ +-#define __NVBIOS_VOLT_H__ +- +-struct nouveau_bios; +- +-struct nvbios_volt { +- u8 vidmask; +- u32 min; +- u32 max; +- u32 base; +- s16 step; +-}; +- +-u16 nvbios_volt_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 nvbios_volt_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_volt *); +- +-struct nvbios_volt_entry { +- u32 voltage; +- u8 vid; +-}; +- +-u16 nvbios_volt_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len); +-u16 nvbios_volt_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len, +- struct nvbios_volt_entry *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h +deleted file mode 100644 +index 360baab5..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/xpio.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-#ifndef __NVBIOS_XPIO_H__ +-#define __NVBIOS_XPIO_H__ +- +-#define NVBIOS_XPIO_FLAG_AUX 0x10 +-#define NVBIOS_XPIO_FLAG_AUX0 0x00 +-#define NVBIOS_XPIO_FLAG_AUX1 0x10 +- +-struct nvbios_xpio { +- u8 type; +- u8 addr; +- u8 flags; +-}; +- +-u16 dcb_xpio_table(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len); +-u16 dcb_xpio_parse(struct nouveau_bios *, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_xpio *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h b/drivers/gpu/drm/nouveau/core/include/subdev/bus.h +deleted file mode 100644 +index 697f7ce7..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/bus.h ++++ /dev/null +@@ -1,53 +0,0 @@ +-#ifndef __NOUVEAU_BUS_H__ +-#define __NOUVEAU_BUS_H__ +- +-#include +-#include +- +-struct nouveau_bus_intr { +- u32 stat; +- u32 unit; +-}; +- +-struct nouveau_bus { +- struct nouveau_subdev base; +- int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32); +- u32 hwsq_size; +-}; +- +-static inline struct nouveau_bus * +-nouveau_bus(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_BUS]; +-} +- +-#define nouveau_bus_create(p, e, o, d) \ +- nouveau_subdev_create_((p), (e), (o), 0, "PBUS", "master", \ +- sizeof(**d), (void **)d) +-#define nouveau_bus_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_bus_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_bus_fini(p, s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +- +-#define _nouveau_bus_dtor _nouveau_subdev_dtor +-#define _nouveau_bus_init _nouveau_subdev_init +-#define _nouveau_bus_fini _nouveau_subdev_fini +- +-extern struct nouveau_oclass *nv04_bus_oclass; +-extern struct nouveau_oclass *nv31_bus_oclass; +-extern struct nouveau_oclass *nv50_bus_oclass; +-extern struct nouveau_oclass *nv94_bus_oclass; +-extern struct nouveau_oclass *nvc0_bus_oclass; +- +-/* interface to sequencer */ +-struct nouveau_hwsq; +-int nouveau_hwsq_init(struct nouveau_bus *, struct nouveau_hwsq **); +-int nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec); +-void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data); +-void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data); +-void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data); +-void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h b/drivers/gpu/drm/nouveau/core/include/subdev/clock.h +deleted file mode 100644 +index 36ed035d..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/clock.h ++++ /dev/null +@@ -1,166 +0,0 @@ +-#ifndef __NOUVEAU_CLOCK_H__ +-#define __NOUVEAU_CLOCK_H__ +- +-#include +-#include +- +-struct nouveau_pll_vals; +-struct nvbios_pll; +- +-enum nv_clk_src { +- nv_clk_src_crystal, +- nv_clk_src_href, +- +- nv_clk_src_hclk, +- nv_clk_src_hclkm3, +- nv_clk_src_hclkm3d2, +- nv_clk_src_hclkm2d3, /* NVAA */ +- nv_clk_src_hclkm4, /* NVAA */ +- nv_clk_src_cclk, /* NVAA */ +- +- nv_clk_src_host, +- +- nv_clk_src_sppll0, +- nv_clk_src_sppll1, +- +- nv_clk_src_mpllsrcref, +- nv_clk_src_mpllsrc, +- nv_clk_src_mpll, +- nv_clk_src_mdiv, +- +- nv_clk_src_core, +- nv_clk_src_core_intm, +- nv_clk_src_shader, +- +- nv_clk_src_mem, +- +- nv_clk_src_gpc, +- nv_clk_src_rop, +- nv_clk_src_hubk01, +- nv_clk_src_hubk06, +- nv_clk_src_hubk07, +- nv_clk_src_copy, +- nv_clk_src_daemon, +- nv_clk_src_disp, +- nv_clk_src_vdec, +- +- nv_clk_src_dom6, +- +- nv_clk_src_max, +-}; +- +-struct nouveau_cstate { +- struct list_head head; +- u8 voltage; +- u32 domain[nv_clk_src_max]; +-}; +- +-struct nouveau_pstate { +- struct list_head head; +- struct list_head list; /* c-states */ +- struct nouveau_cstate base; +- u8 pstate; +- u8 fanspeed; +-}; +- +-struct nouveau_clock { +- struct nouveau_subdev base; +- +- struct nouveau_clocks *domains; +- struct nouveau_pstate bstate; +- +- struct list_head states; +- int state_nr; +- +- struct work_struct work; +- wait_queue_head_t wait; +- atomic_t waiting; +- +- struct nvkm_notify pwrsrc_ntfy; +- int pwrsrc; +- int pstate; /* current */ +- int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ +- int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ +- int astate; /* perfmon adjustment (base) */ +- int tstate; /* thermal adjustment (max-) */ +- int dstate; /* display adjustment (min+) */ +- +- bool allow_reclock; +- +- int (*read)(struct nouveau_clock *, enum nv_clk_src); +- int (*calc)(struct nouveau_clock *, struct nouveau_cstate *); +- int (*prog)(struct nouveau_clock *); +- void (*tidy)(struct nouveau_clock *); +- +- /*XXX: die, these are here *only* to support the completely +- * bat-shit insane what-was-nouveau_hw.c code +- */ +- int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *, +- int clk, struct nouveau_pll_vals *pv); +- int (*pll_prog)(struct nouveau_clock *, u32 reg1, +- struct nouveau_pll_vals *pv); +-}; +- +-static inline struct nouveau_clock * +-nouveau_clock(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK]; +-} +- +-struct nouveau_clocks { +- enum nv_clk_src name; +- u8 bios; /* 0xff for none */ +-#define NVKM_CLK_DOM_FLAG_CORE 0x01 +- u8 flags; +- const char *mname; +- int mdiv; +-}; +- +-#define nouveau_clock_create(p,e,o,i,r,s,n,d) \ +- nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \ +- (void **)d) +-#define nouveau_clock_destroy(p) ({ \ +- struct nouveau_clock *clk = (p); \ +- _nouveau_clock_dtor(nv_object(clk)); \ +-}) +-#define nouveau_clock_init(p) ({ \ +- struct nouveau_clock *clk = (p); \ +- _nouveau_clock_init(nv_object(clk)); \ +-}) +-#define nouveau_clock_fini(p,s) ({ \ +- struct nouveau_clock *clk = (p); \ +- _nouveau_clock_fini(nv_object(clk), (s)); \ +-}) +- +-int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, +- struct nouveau_clocks *, struct nouveau_pstate *, +- int, bool, int, void **); +-void _nouveau_clock_dtor(struct nouveau_object *); +-int _nouveau_clock_init(struct nouveau_object *); +-int _nouveau_clock_fini(struct nouveau_object *, bool); +- +-extern struct nouveau_oclass nv04_clock_oclass; +-extern struct nouveau_oclass nv40_clock_oclass; +-extern struct nouveau_oclass *nv50_clock_oclass; +-extern struct nouveau_oclass *nv84_clock_oclass; +-extern struct nouveau_oclass *nvaa_clock_oclass; +-extern struct nouveau_oclass nva3_clock_oclass; +-extern struct nouveau_oclass nvc0_clock_oclass; +-extern struct nouveau_oclass nve0_clock_oclass; +-extern struct nouveau_oclass gk20a_clock_oclass; +- +-int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq); +-int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, +- int clk, struct nouveau_pll_vals *); +-int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1, +- struct nouveau_pll_vals *); +-int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *, +- int clk, struct nouveau_pll_vals *); +- +-int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr); +-int nouveau_clock_astate(struct nouveau_clock *, int req, int rel); +-int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel); +-int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h b/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h +deleted file mode 100644 +index e292271a..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/devinit.h ++++ /dev/null +@@ -1,34 +0,0 @@ +-#ifndef __NOUVEAU_DEVINIT_H__ +-#define __NOUVEAU_DEVINIT_H__ +- +-#include +-#include +- +-struct nouveau_devinit { +- struct nouveau_subdev base; +- bool post; +- void (*meminit)(struct nouveau_devinit *); +- int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); +- u32 (*mmio)(struct nouveau_devinit *, u32 addr); +-}; +- +-static inline struct nouveau_devinit * +-nouveau_devinit(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_DEVINIT]; +-} +- +-extern struct nouveau_oclass *nv04_devinit_oclass; +-extern struct nouveau_oclass *nv05_devinit_oclass; +-extern struct nouveau_oclass *nv10_devinit_oclass; +-extern struct nouveau_oclass *nv1a_devinit_oclass; +-extern struct nouveau_oclass *nv20_devinit_oclass; +-extern struct nouveau_oclass *nv50_devinit_oclass; +-extern struct nouveau_oclass *nv84_devinit_oclass; +-extern struct nouveau_oclass *nv98_devinit_oclass; +-extern struct nouveau_oclass *nva3_devinit_oclass; +-extern struct nouveau_oclass *nvaf_devinit_oclass; +-extern struct nouveau_oclass *nvc0_devinit_oclass; +-extern struct nouveau_oclass *gm107_devinit_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb.h +deleted file mode 100644 +index 8d0032f1..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb.h ++++ /dev/null +@@ -1,159 +0,0 @@ +-#ifndef __NOUVEAU_FB_H__ +-#define __NOUVEAU_FB_H__ +- +-#include +-#include +-#include +- +-#include +- +-/* memory type/access flags, do not match hardware values */ +-#define NV_MEM_ACCESS_RO 1 +-#define NV_MEM_ACCESS_WO 2 +-#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) +-#define NV_MEM_ACCESS_SYS 4 +-#define NV_MEM_ACCESS_VM 8 +-#define NV_MEM_ACCESS_NOSNOOP 16 +- +-#define NV_MEM_TARGET_VRAM 0 +-#define NV_MEM_TARGET_PCI 1 +-#define NV_MEM_TARGET_PCI_NOSNOOP 2 +-#define NV_MEM_TARGET_VM 3 +-#define NV_MEM_TARGET_GART 4 +- +-#define NV_MEM_TYPE_VM 0x7f +-#define NV_MEM_COMP_VM 0x03 +- +-struct nouveau_mem { +- struct drm_device *dev; +- +- struct nouveau_vma bar_vma; +- struct nouveau_vma vma[2]; +- u8 page_shift; +- +- struct nouveau_mm_node *tag; +- struct list_head regions; +- dma_addr_t *pages; +- u32 memtype; +- u64 offset; +- u64 size; +- struct sg_table *sg; +-}; +- +-struct nouveau_fb_tile { +- struct nouveau_mm_node *tag; +- u32 addr; +- u32 limit; +- u32 pitch; +- u32 zcomp; +-}; +- +-struct nouveau_fb { +- struct nouveau_subdev base; +- +- bool (*memtype_valid)(struct nouveau_fb *, u32 memtype); +- +- struct nouveau_ram *ram; +- +- struct nouveau_mm vram; +- struct nouveau_mm tags; +- +- struct { +- struct nouveau_fb_tile region[16]; +- int regions; +- void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size, +- u32 pitch, u32 flags, struct nouveau_fb_tile *); +- void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *); +- void (*fini)(struct nouveau_fb *, int i, +- struct nouveau_fb_tile *); +- void (*prog)(struct nouveau_fb *, int i, +- struct nouveau_fb_tile *); +- } tile; +-}; +- +-static inline struct nouveau_fb * +-nouveau_fb(void *obj) +-{ +- /* fbram uses this before device subdev pointer is valid */ +- if (nv_iclass(obj, NV_SUBDEV_CLASS) && +- nv_subidx(obj) == NVDEV_SUBDEV_FB) +- return obj; +- +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FB]; +-} +- +-extern struct nouveau_oclass *nv04_fb_oclass; +-extern struct nouveau_oclass *nv10_fb_oclass; +-extern struct nouveau_oclass *nv1a_fb_oclass; +-extern struct nouveau_oclass *nv20_fb_oclass; +-extern struct nouveau_oclass *nv25_fb_oclass; +-extern struct nouveau_oclass *nv30_fb_oclass; +-extern struct nouveau_oclass *nv35_fb_oclass; +-extern struct nouveau_oclass *nv36_fb_oclass; +-extern struct nouveau_oclass *nv40_fb_oclass; +-extern struct nouveau_oclass *nv41_fb_oclass; +-extern struct nouveau_oclass *nv44_fb_oclass; +-extern struct nouveau_oclass *nv46_fb_oclass; +-extern struct nouveau_oclass *nv47_fb_oclass; +-extern struct nouveau_oclass *nv49_fb_oclass; +-extern struct nouveau_oclass *nv4e_fb_oclass; +-extern struct nouveau_oclass *nv50_fb_oclass; +-extern struct nouveau_oclass *nv84_fb_oclass; +-extern struct nouveau_oclass *nva3_fb_oclass; +-extern struct nouveau_oclass *nvaa_fb_oclass; +-extern struct nouveau_oclass *nvaf_fb_oclass; +-extern struct nouveau_oclass *nvc0_fb_oclass; +-extern struct nouveau_oclass *nve0_fb_oclass; +-extern struct nouveau_oclass *gk20a_fb_oclass; +-extern struct nouveau_oclass *gm107_fb_oclass; +- +-#include +- +-struct nouveau_ram_data { +- struct list_head head; +- struct nvbios_ramcfg bios; +- u32 freq; +-}; +- +-struct nouveau_ram { +- struct nouveau_object base; +- enum { +- NV_MEM_TYPE_UNKNOWN = 0, +- NV_MEM_TYPE_STOLEN, +- NV_MEM_TYPE_SGRAM, +- NV_MEM_TYPE_SDRAM, +- NV_MEM_TYPE_DDR1, +- NV_MEM_TYPE_DDR2, +- NV_MEM_TYPE_DDR3, +- NV_MEM_TYPE_GDDR2, +- NV_MEM_TYPE_GDDR3, +- NV_MEM_TYPE_GDDR4, +- NV_MEM_TYPE_GDDR5 +- } type; +- u64 stolen; +- u64 size; +- u32 tags; +- +- int ranks; +- int parts; +- int part_mask; +- +- int (*get)(struct nouveau_fb *, u64 size, u32 align, +- u32 size_nc, u32 type, struct nouveau_mem **); +- void (*put)(struct nouveau_fb *, struct nouveau_mem **); +- +- int (*calc)(struct nouveau_fb *, u32 freq); +- int (*prog)(struct nouveau_fb *); +- void (*tidy)(struct nouveau_fb *); +- u32 freq; +- u32 mr[16]; +- u32 mr1_nuts; +- +- struct nouveau_ram_data *next; +- struct nouveau_ram_data former; +- struct nouveau_ram_data xition; +- struct nouveau_ram_data target; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h b/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h +deleted file mode 100644 +index 0f7fc0c5..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/fb/regsnv04.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-#ifndef __NOUVEAU_FB_REGS_04_H__ +-#define __NOUVEAU_FB_REGS_04_H__ +- +-#define NV04_PFB_BOOT_0 0x00100000 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 +-# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004 +-# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 +-# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 +-# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h b/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h +deleted file mode 100644 +index 2b1ddb2a..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/fuse.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-#ifndef __NOUVEAU_FUSE_H__ +-#define __NOUVEAU_FUSE_H__ +- +-#include +-#include +- +-struct nouveau_fuse { +- struct nouveau_subdev base; +-}; +- +-static inline struct nouveau_fuse * +-nouveau_fuse(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FUSE]; +-} +- +-#define nouveau_fuse_create(p, e, o, d) \ +- nouveau_fuse_create_((p), (e), (o), sizeof(**d), (void **)d) +- +-int nouveau_fuse_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_fuse_dtor(struct nouveau_object *); +-int _nouveau_fuse_init(struct nouveau_object *); +-#define _nouveau_fuse_fini _nouveau_subdev_fini +- +-extern struct nouveau_oclass g80_fuse_oclass; +-extern struct nouveau_oclass gf100_fuse_oclass; +-extern struct nouveau_oclass gm107_fuse_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h b/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h +deleted file mode 100644 +index f855140d..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/gpio.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-#ifndef __NOUVEAU_GPIO_H__ +-#define __NOUVEAU_GPIO_H__ +- +-#include +-#include +-#include +- +-#include +-#include +- +-struct nvkm_gpio_ntfy_req { +-#define NVKM_GPIO_HI 0x01 +-#define NVKM_GPIO_LO 0x02 +-#define NVKM_GPIO_TOGGLED 0x03 +- u8 mask; +- u8 line; +-}; +- +-struct nvkm_gpio_ntfy_rep { +- u8 mask; +-}; +- +-struct nouveau_gpio { +- struct nouveau_subdev base; +- +- struct nvkm_event event; +- +- void (*reset)(struct nouveau_gpio *, u8 func); +- int (*find)(struct nouveau_gpio *, int idx, u8 tag, u8 line, +- struct dcb_gpio_func *); +- int (*set)(struct nouveau_gpio *, int idx, u8 tag, u8 line, int state); +- int (*get)(struct nouveau_gpio *, int idx, u8 tag, u8 line); +-}; +- +-static inline struct nouveau_gpio * +-nouveau_gpio(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_GPIO]; +-} +- +-extern struct nouveau_oclass *nv10_gpio_oclass; +-extern struct nouveau_oclass *nv50_gpio_oclass; +-extern struct nouveau_oclass *nv94_gpio_oclass; +-extern struct nouveau_oclass *nvd0_gpio_oclass; +-extern struct nouveau_oclass *nve0_gpio_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h b/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h +deleted file mode 100644 +index 1b937c2c..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/i2c.h ++++ /dev/null +@@ -1,133 +0,0 @@ +-#ifndef __NOUVEAU_I2C_H__ +-#define __NOUVEAU_I2C_H__ +- +-#include +-#include +- +-#include +-#include +- +-#define NV_I2C_PORT(n) (0x00 + (n)) +-#define NV_I2C_DEFAULT(n) (0x80 + (n)) +- +-#define NV_I2C_TYPE_DCBI2C(n) (0x0000 | (n)) +-#define NV_I2C_TYPE_EXTDDC(e) (0x0005 | (e) << 8) +-#define NV_I2C_TYPE_EXTAUX(e) (0x0006 | (e) << 8) +- +-struct nvkm_i2c_ntfy_req { +-#define NVKM_I2C_PLUG 0x01 +-#define NVKM_I2C_UNPLUG 0x02 +-#define NVKM_I2C_IRQ 0x04 +-#define NVKM_I2C_DONE 0x08 +-#define NVKM_I2C_ANY 0x0f +- u8 mask; +- u8 port; +-}; +- +-struct nvkm_i2c_ntfy_rep { +- u8 mask; +-}; +- +-struct nouveau_i2c_port { +- struct nouveau_object base; +- struct i2c_adapter adapter; +- struct mutex mutex; +- +- struct list_head head; +- u8 index; +- int aux; +- +- const struct nouveau_i2c_func *func; +-}; +- +-struct nouveau_i2c_func { +- void (*drive_scl)(struct nouveau_i2c_port *, int); +- void (*drive_sda)(struct nouveau_i2c_port *, int); +- int (*sense_scl)(struct nouveau_i2c_port *); +- int (*sense_sda)(struct nouveau_i2c_port *); +- +- int (*aux)(struct nouveau_i2c_port *, bool, u8, u32, u8 *, u8); +- int (*pattern)(struct nouveau_i2c_port *, int pattern); +- int (*lnk_ctl)(struct nouveau_i2c_port *, int nr, int bw, bool enh); +- int (*drv_ctl)(struct nouveau_i2c_port *, int lane, int sw, int pe); +-}; +- +-struct nouveau_i2c_board_info { +- struct i2c_board_info dev; +- u8 udelay; /* set to 0 to use the standard delay */ +-}; +- +-struct nouveau_i2c { +- struct nouveau_subdev base; +- struct nvkm_event event; +- +- struct nouveau_i2c_port *(*find)(struct nouveau_i2c *, u8 index); +- struct nouveau_i2c_port *(*find_type)(struct nouveau_i2c *, u16 type); +- int (*acquire_pad)(struct nouveau_i2c_port *, unsigned long timeout); +- void (*release_pad)(struct nouveau_i2c_port *); +- int (*acquire)(struct nouveau_i2c_port *, unsigned long timeout); +- void (*release)(struct nouveau_i2c_port *); +- int (*identify)(struct nouveau_i2c *, int index, +- const char *what, struct nouveau_i2c_board_info *, +- bool (*match)(struct nouveau_i2c_port *, +- struct i2c_board_info *, void *), void *); +- +- wait_queue_head_t wait; +- struct list_head ports; +-}; +- +-static inline struct nouveau_i2c * +-nouveau_i2c(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_I2C]; +-} +- +-extern struct nouveau_oclass *nv04_i2c_oclass; +-extern struct nouveau_oclass *nv4e_i2c_oclass; +-extern struct nouveau_oclass *nv50_i2c_oclass; +-extern struct nouveau_oclass *nv94_i2c_oclass; +-extern struct nouveau_oclass *nvd0_i2c_oclass; +-extern struct nouveau_oclass *gf117_i2c_oclass; +-extern struct nouveau_oclass *nve0_i2c_oclass; +- +-static inline int +-nv_rdi2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg) +-{ +- u8 val; +- struct i2c_msg msgs[] = { +- { .addr = addr, .flags = 0, .len = 1, .buf = ® }, +- { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = &val }, +- }; +- +- int ret = i2c_transfer(&port->adapter, msgs, 2); +- if (ret != 2) +- return -EIO; +- +- return val; +-} +- +-static inline int +-nv_wri2cr(struct nouveau_i2c_port *port, u8 addr, u8 reg, u8 val) +-{ +- u8 buf[2] = { reg, val }; +- struct i2c_msg msgs[] = { +- { .addr = addr, .flags = 0, .len = 2, .buf = buf }, +- }; +- +- int ret = i2c_transfer(&port->adapter, msgs, 1); +- if (ret != 1) +- return -EIO; +- +- return 0; +-} +- +-static inline bool +-nv_probe_i2c(struct nouveau_i2c_port *port, u8 addr) +-{ +- return nv_rdi2cr(port, addr, 0) >= 0; +-} +- +-int nv_rdaux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size); +-int nv_wraux(struct nouveau_i2c_port *, u32 addr, u8 *data, u8 size); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h b/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h +deleted file mode 100644 +index 31df634c..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/ibus.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-#ifndef __NOUVEAU_IBUS_H__ +-#define __NOUVEAU_IBUS_H__ +- +-#include +-#include +- +-struct nouveau_ibus { +- struct nouveau_subdev base; +-}; +- +-static inline struct nouveau_ibus * +-nouveau_ibus(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_IBUS]; +-} +- +-#define nouveau_ibus_create(p,e,o,d) \ +- nouveau_subdev_create_((p), (e), (o), 0, "PIBUS", "ibus", \ +- sizeof(**d), (void **)d) +-#define nouveau_ibus_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_ibus_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_ibus_fini(p,s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +- +-#define _nouveau_ibus_dtor _nouveau_subdev_dtor +-#define _nouveau_ibus_init _nouveau_subdev_init +-#define _nouveau_ibus_fini _nouveau_subdev_fini +- +-extern struct nouveau_oclass nvc0_ibus_oclass; +-extern struct nouveau_oclass nve0_ibus_oclass; +-extern struct nouveau_oclass gk20a_ibus_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h b/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h +deleted file mode 100644 +index c1df26f3..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/instmem.h ++++ /dev/null +@@ -1,52 +0,0 @@ +-#ifndef __NOUVEAU_INSTMEM_H__ +-#define __NOUVEAU_INSTMEM_H__ +- +-#include +-#include +-#include +- +-struct nouveau_instobj { +- struct nouveau_object base; +- struct list_head head; +- u32 *suspend; +- u64 addr; +- u32 size; +-}; +- +-static inline struct nouveau_instobj * +-nv_memobj(void *obj) +-{ +-#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA +- if (unlikely(!nv_iclass(obj, NV_MEMOBJ_CLASS))) +- nv_assert("BAD CAST -> NvMemObj, %08x", nv_hclass(obj)); +-#endif +- return obj; +-} +- +-struct nouveau_instmem { +- struct nouveau_subdev base; +- struct list_head list; +- +- u32 reserved; +- int (*alloc)(struct nouveau_instmem *, struct nouveau_object *, +- u32 size, u32 align, struct nouveau_object **); +-}; +- +-static inline struct nouveau_instmem * +-nouveau_instmem(void *obj) +-{ +- /* nv04/nv40 impls need to create objects in their constructor, +- * which is before the subdev pointer is valid +- */ +- if (nv_iclass(obj, NV_SUBDEV_CLASS) && +- nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM) +- return obj; +- +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_INSTMEM]; +-} +- +-extern struct nouveau_oclass *nv04_instmem_oclass; +-extern struct nouveau_oclass *nv40_instmem_oclass; +-extern struct nouveau_oclass *nv50_instmem_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h b/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h +deleted file mode 100644 +index b909a736..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/ltc.h ++++ /dev/null +@@ -1,35 +0,0 @@ +-#ifndef __NOUVEAU_LTC_H__ +-#define __NOUVEAU_LTC_H__ +- +-#include +-#include +- +-#define NOUVEAU_LTC_MAX_ZBC_CNT 16 +- +-struct nouveau_mm_node; +- +-struct nouveau_ltc { +- struct nouveau_subdev base; +- +- int (*tags_alloc)(struct nouveau_ltc *, u32 count, +- struct nouveau_mm_node **); +- void (*tags_free)(struct nouveau_ltc *, struct nouveau_mm_node **); +- void (*tags_clear)(struct nouveau_ltc *, u32 first, u32 count); +- +- int zbc_min; +- int zbc_max; +- int (*zbc_color_get)(struct nouveau_ltc *, int index, const u32[4]); +- int (*zbc_depth_get)(struct nouveau_ltc *, int index, const u32); +-}; +- +-static inline struct nouveau_ltc * +-nouveau_ltc(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_LTC]; +-} +- +-extern struct nouveau_oclass *gf100_ltc_oclass; +-extern struct nouveau_oclass *gk104_ltc_oclass; +-extern struct nouveau_oclass *gm107_ltc_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h b/drivers/gpu/drm/nouveau/core/include/subdev/mc.h +deleted file mode 100644 +index 568e4dfc..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/mc.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-#ifndef __NOUVEAU_MC_H__ +-#define __NOUVEAU_MC_H__ +- +-#include +-#include +- +-struct nouveau_mc { +- struct nouveau_subdev base; +- bool use_msi; +- unsigned int irq; +- void (*unk260)(struct nouveau_mc *, u32); +-}; +- +-static inline struct nouveau_mc * +-nouveau_mc(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC]; +-} +- +-extern struct nouveau_oclass *nv04_mc_oclass; +-extern struct nouveau_oclass *nv40_mc_oclass; +-extern struct nouveau_oclass *nv44_mc_oclass; +-extern struct nouveau_oclass *nv4c_mc_oclass; +-extern struct nouveau_oclass *nv50_mc_oclass; +-extern struct nouveau_oclass *nv94_mc_oclass; +-extern struct nouveau_oclass *nv98_mc_oclass; +-extern struct nouveau_oclass *nvc0_mc_oclass; +-extern struct nouveau_oclass *nvc3_mc_oclass; +-extern struct nouveau_oclass *gk20a_mc_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h b/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h +deleted file mode 100644 +index b93b152c..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/mxm.h ++++ /dev/null +@@ -1,37 +0,0 @@ +-#ifndef __NOUVEAU_MXM_H__ +-#define __NOUVEAU_MXM_H__ +- +-#include +-#include +- +-#define MXM_SANITISE_DCB 0x00000001 +- +-struct nouveau_mxm { +- struct nouveau_subdev base; +- u32 action; +- u8 *mxms; +-}; +- +-static inline struct nouveau_mxm * +-nouveau_mxm(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MXM]; +-} +- +-#define nouveau_mxm_create(p,e,o,d) \ +- nouveau_mxm_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_mxm_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_mxm_fini(p,s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +-int nouveau_mxm_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void nouveau_mxm_destroy(struct nouveau_mxm *); +- +-#define _nouveau_mxm_dtor _nouveau_subdev_dtor +-#define _nouveau_mxm_init _nouveau_subdev_init +-#define _nouveau_mxm_fini _nouveau_subdev_fini +- +-extern struct nouveau_oclass nv50_mxm_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h b/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h +deleted file mode 100644 +index bf3d1f61..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/pwr.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-#ifndef __NOUVEAU_PWR_H__ +-#define __NOUVEAU_PWR_H__ +- +-#include +-#include +- +-struct nouveau_pwr { +- struct nouveau_subdev base; +- +- struct { +- u32 base; +- u32 size; +- } send; +- +- struct { +- u32 base; +- u32 size; +- +- struct work_struct work; +- wait_queue_head_t wait; +- u32 process; +- u32 message; +- u32 data[2]; +- } recv; +- +- int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32); +- void (*pgob)(struct nouveau_pwr *, bool); +-}; +- +-static inline struct nouveau_pwr * +-nouveau_pwr(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR]; +-} +- +-extern struct nouveau_oclass *nva3_pwr_oclass; +-extern struct nouveau_oclass *nvc0_pwr_oclass; +-extern struct nouveau_oclass *nvd0_pwr_oclass; +-extern struct nouveau_oclass *gk104_pwr_oclass; +-extern struct nouveau_oclass *nv108_pwr_oclass; +- +-/* interface to MEMX process running on PPWR */ +-struct nouveau_memx; +-int nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **); +-int nouveau_memx_fini(struct nouveau_memx **, bool exec); +-void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data); +-void nouveau_memx_wait(struct nouveau_memx *, +- u32 addr, u32 mask, u32 data, u32 nsec); +-void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec); +-void nouveau_memx_wait_vblank(struct nouveau_memx *); +-void nouveau_memx_block(struct nouveau_memx *); +-void nouveau_memx_unblock(struct nouveau_memx *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h b/drivers/gpu/drm/nouveau/core/include/subdev/therm.h +deleted file mode 100644 +index a437597d..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/therm.h ++++ /dev/null +@@ -1,83 +0,0 @@ +-#ifndef __NOUVEAU_THERM_H__ +-#define __NOUVEAU_THERM_H__ +- +-#include +-#include +- +-enum nouveau_therm_fan_mode { +- NOUVEAU_THERM_CTRL_NONE = 0, +- NOUVEAU_THERM_CTRL_MANUAL = 1, +- NOUVEAU_THERM_CTRL_AUTO = 2, +-}; +- +-enum nouveau_therm_attr_type { +- NOUVEAU_THERM_ATTR_FAN_MIN_DUTY = 0, +- NOUVEAU_THERM_ATTR_FAN_MAX_DUTY = 1, +- NOUVEAU_THERM_ATTR_FAN_MODE = 2, +- +- NOUVEAU_THERM_ATTR_THRS_FAN_BOOST = 10, +- NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST = 11, +- NOUVEAU_THERM_ATTR_THRS_DOWN_CLK = 12, +- NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST = 13, +- NOUVEAU_THERM_ATTR_THRS_CRITICAL = 14, +- NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST = 15, +- NOUVEAU_THERM_ATTR_THRS_SHUTDOWN = 16, +- NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST = 17, +-}; +- +-struct nouveau_therm { +- struct nouveau_subdev base; +- +- int (*pwm_ctrl)(struct nouveau_therm *, int line, bool); +- int (*pwm_get)(struct nouveau_therm *, int line, u32 *, u32 *); +- int (*pwm_set)(struct nouveau_therm *, int line, u32, u32); +- int (*pwm_clock)(struct nouveau_therm *, int line); +- +- int (*fan_get)(struct nouveau_therm *); +- int (*fan_set)(struct nouveau_therm *, int); +- int (*fan_sense)(struct nouveau_therm *); +- +- int (*temp_get)(struct nouveau_therm *); +- +- int (*attr_get)(struct nouveau_therm *, enum nouveau_therm_attr_type); +- int (*attr_set)(struct nouveau_therm *, +- enum nouveau_therm_attr_type, int); +-}; +- +-static inline struct nouveau_therm * +-nouveau_therm(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_THERM]; +-} +- +-#define nouveau_therm_create(p,e,o,d) \ +- nouveau_therm_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_therm_destroy(p) ({ \ +- struct nouveau_therm *therm = (p); \ +- _nouveau_therm_dtor(nv_object(therm)); \ +-}) +-#define nouveau_therm_init(p) ({ \ +- struct nouveau_therm *therm = (p); \ +- _nouveau_therm_init(nv_object(therm)); \ +-}) +-#define nouveau_therm_fini(p,s) ({ \ +- struct nouveau_therm *therm = (p); \ +- _nouveau_therm_init(nv_object(therm), (s)); \ +-}) +- +-int nouveau_therm_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_therm_dtor(struct nouveau_object *); +-int _nouveau_therm_init(struct nouveau_object *); +-int _nouveau_therm_fini(struct nouveau_object *, bool); +- +-int nouveau_therm_cstate(struct nouveau_therm *, int, int); +- +-extern struct nouveau_oclass nv40_therm_oclass; +-extern struct nouveau_oclass nv50_therm_oclass; +-extern struct nouveau_oclass nv84_therm_oclass; +-extern struct nouveau_oclass nva3_therm_oclass; +-extern struct nouveau_oclass nvd0_therm_oclass; +-extern struct nouveau_oclass gm107_therm_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h b/drivers/gpu/drm/nouveau/core/include/subdev/timer.h +deleted file mode 100644 +index db9be803..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/timer.h ++++ /dev/null +@@ -1,64 +0,0 @@ +-#ifndef __NOUVEAU_TIMER_H__ +-#define __NOUVEAU_TIMER_H__ +- +-#include +-#include +- +-struct nouveau_alarm { +- struct list_head head; +- u64 timestamp; +- void (*func)(struct nouveau_alarm *); +-}; +- +-static inline void +-nouveau_alarm_init(struct nouveau_alarm *alarm, +- void (*func)(struct nouveau_alarm *)) +-{ +- INIT_LIST_HEAD(&alarm->head); +- alarm->func = func; +-} +- +-bool nouveau_timer_wait_eq(void *, u64 nsec, u32 addr, u32 mask, u32 data); +-bool nouveau_timer_wait_ne(void *, u64 nsec, u32 addr, u32 mask, u32 data); +-bool nouveau_timer_wait_cb(void *, u64 nsec, bool (*func)(void *), void *data); +-void nouveau_timer_alarm(void *, u32 nsec, struct nouveau_alarm *); +-void nouveau_timer_alarm_cancel(void *, struct nouveau_alarm *); +- +-#define NV_WAIT_DEFAULT 2000000000ULL +-#define nv_wait(o,a,m,v) \ +- nouveau_timer_wait_eq((o), NV_WAIT_DEFAULT, (a), (m), (v)) +-#define nv_wait_ne(o,a,m,v) \ +- nouveau_timer_wait_ne((o), NV_WAIT_DEFAULT, (a), (m), (v)) +-#define nv_wait_cb(o,c,d) \ +- nouveau_timer_wait_cb((o), NV_WAIT_DEFAULT, (c), (d)) +- +-struct nouveau_timer { +- struct nouveau_subdev base; +- u64 (*read)(struct nouveau_timer *); +- void (*alarm)(struct nouveau_timer *, u64 time, struct nouveau_alarm *); +- void (*alarm_cancel)(struct nouveau_timer *, struct nouveau_alarm *); +-}; +- +-static inline struct nouveau_timer * +-nouveau_timer(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_TIMER]; +-} +- +-#define nouveau_timer_create(p,e,o,d) \ +- nouveau_subdev_create_((p), (e), (o), 0, "PTIMER", "timer", \ +- sizeof(**d), (void **)d) +-#define nouveau_timer_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_timer_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_timer_fini(p,s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +- +-int nouveau_timer_create_(struct nouveau_object *, struct nouveau_engine *, +- struct nouveau_oclass *, int size, void **); +- +-extern struct nouveau_oclass nv04_timer_oclass; +-extern struct nouveau_oclass gk20a_timer_oclass; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h b/drivers/gpu/drm/nouveau/core/include/subdev/vga.h +deleted file mode 100644 +index fee09ad8..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/vga.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-#ifndef __NOUVEAU_VGA_H__ +-#define __NOUVEAU_VGA_H__ +- +-#include +- +-/* access to various legacy io ports */ +-u8 nv_rdport(void *obj, int head, u16 port); +-void nv_wrport(void *obj, int head, u16 port, u8 value); +- +-/* VGA Sequencer */ +-u8 nv_rdvgas(void *obj, int head, u8 index); +-void nv_wrvgas(void *obj, int head, u8 index, u8 value); +- +-/* VGA Graphics */ +-u8 nv_rdvgag(void *obj, int head, u8 index); +-void nv_wrvgag(void *obj, int head, u8 index, u8 value); +- +-/* VGA CRTC */ +-u8 nv_rdvgac(void *obj, int head, u8 index); +-void nv_wrvgac(void *obj, int head, u8 index, u8 value); +- +-/* VGA indexed port access dispatcher */ +-u8 nv_rdvgai(void *obj, int head, u16 port, u8 index); +-void nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value); +- +-bool nv_lockvgac(void *obj, bool lock); +-u8 nv_rdvgaowner(void *obj); +-void nv_wrvgaowner(void *obj, u8); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h b/drivers/gpu/drm/nouveau/core/include/subdev/vm.h +deleted file mode 100644 +index c9509039..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/vm.h ++++ /dev/null +@@ -1,135 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifndef __NOUVEAU_VM_H__ +-#define __NOUVEAU_VM_H__ +- +-#include +-#include +-#include +-#include +- +-struct nouveau_vm_pgt { +- struct nouveau_gpuobj *obj[2]; +- u32 refcount[2]; +-}; +- +-struct nouveau_vm_pgd { +- struct list_head head; +- struct nouveau_gpuobj *obj; +-}; +- +-struct nouveau_gpuobj; +-struct nouveau_mem; +- +-struct nouveau_vma { +- struct list_head head; +- int refcount; +- struct nouveau_vm *vm; +- struct nouveau_mm_node *node; +- u64 offset; +- u32 access; +-}; +- +-struct nouveau_vm { +- struct nouveau_vmmgr *vmm; +- struct nouveau_mm mm; +- struct kref refcount; +- +- struct list_head pgd_list; +- atomic_t engref[NVDEV_SUBDEV_NR]; +- +- struct nouveau_vm_pgt *pgt; +- u32 fpde; +- u32 lpde; +-}; +- +-struct nouveau_vmmgr { +- struct nouveau_subdev base; +- +- u64 limit; +- u8 dma_bits; +- u32 pgt_bits; +- u8 spg_shift; +- u8 lpg_shift; +- +- int (*create)(struct nouveau_vmmgr *, u64 offset, u64 length, +- u64 mm_offset, struct nouveau_vm **); +- +- void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, +- struct nouveau_gpuobj *pgt[2]); +- void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, +- struct nouveau_mem *, u32 pte, u32 cnt, +- u64 phys, u64 delta); +- void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, +- struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); +- void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); +- void (*flush)(struct nouveau_vm *); +-}; +- +-static inline struct nouveau_vmmgr * +-nouveau_vmmgr(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VM]; +-} +- +-#define nouveau_vmmgr_create(p,e,o,i,f,d) \ +- nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) +-#define nouveau_vmmgr_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_vmmgr_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_vmmgr_fini(p,s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +- +-#define _nouveau_vmmgr_dtor _nouveau_subdev_dtor +-#define _nouveau_vmmgr_init _nouveau_subdev_init +-#define _nouveau_vmmgr_fini _nouveau_subdev_fini +- +-extern struct nouveau_oclass nv04_vmmgr_oclass; +-extern struct nouveau_oclass nv41_vmmgr_oclass; +-extern struct nouveau_oclass nv44_vmmgr_oclass; +-extern struct nouveau_oclass nv50_vmmgr_oclass; +-extern struct nouveau_oclass nvc0_vmmgr_oclass; +- +-int nv04_vm_create(struct nouveau_vmmgr *, u64, u64, u64, +- struct nouveau_vm **); +-void nv04_vmmgr_dtor(struct nouveau_object *); +- +-/* nouveau_vm.c */ +-int nouveau_vm_create(struct nouveau_vmmgr *, u64 offset, u64 length, +- u64 mm_offset, u32 block, struct nouveau_vm **); +-int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, +- u64 mm_offset, struct nouveau_vm **); +-int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, +- struct nouveau_gpuobj *pgd); +-int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, +- u32 access, struct nouveau_vma *); +-void nouveau_vm_put(struct nouveau_vma *); +-void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); +-void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); +-void nouveau_vm_unmap(struct nouveau_vma *); +-void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h b/drivers/gpu/drm/nouveau/core/include/subdev/volt.h +deleted file mode 100644 +index 820b62ff..00000000 +--- a/drivers/gpu/drm/nouveau/core/include/subdev/volt.h ++++ /dev/null +@@ -1,60 +0,0 @@ +-#ifndef __NOUVEAU_VOLT_H__ +-#define __NOUVEAU_VOLT_H__ +- +-#include +-#include +- +-struct nouveau_voltage { +- u32 uv; +- u8 id; +-}; +- +-struct nouveau_volt { +- struct nouveau_subdev base; +- +- int (*vid_get)(struct nouveau_volt *); +- int (*get)(struct nouveau_volt *); +- int (*vid_set)(struct nouveau_volt *, u8 vid); +- int (*set)(struct nouveau_volt *, u32 uv); +- int (*set_id)(struct nouveau_volt *, u8 id, int condition); +- +- u8 vid_mask; +- u8 vid_nr; +- struct { +- u32 uv; +- u8 vid; +- } vid[256]; +-}; +- +-static inline struct nouveau_volt * +-nouveau_volt(void *obj) +-{ +- return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VOLT]; +-} +- +-#define nouveau_volt_create(p, e, o, d) \ +- nouveau_volt_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_volt_destroy(p) ({ \ +- struct nouveau_volt *v = (p); \ +- _nouveau_volt_dtor(nv_object(v)); \ +-}) +-#define nouveau_volt_init(p) ({ \ +- struct nouveau_volt *v = (p); \ +- _nouveau_volt_init(nv_object(v)); \ +-}) +-#define nouveau_volt_fini(p,s) \ +- nouveau_subdev_fini((p), (s)) +- +-int nouveau_volt_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_volt_dtor(struct nouveau_object *); +-int _nouveau_volt_init(struct nouveau_object *); +-#define _nouveau_volt_fini _nouveau_subdev_fini +- +-extern struct nouveau_oclass nv40_volt_oclass; +- +-int nouveau_voltgpio_init(struct nouveau_volt *); +-int nouveau_voltgpio_get(struct nouveau_volt *); +-int nouveau_voltgpio_set(struct nouveau_volt *, u8); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/os.h b/drivers/gpu/drm/nouveau/core/os.h +deleted file mode 100644 +index ccfa21d7..00000000 +--- a/drivers/gpu/drm/nouveau/core/os.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-#ifndef __NOUVEAU_OS_H__ +-#define __NOUVEAU_OS_H__ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#ifndef ioread32_native +-#ifdef __BIG_ENDIAN +-#define ioread16_native ioread16be +-#define iowrite16_native iowrite16be +-#define ioread32_native ioread32be +-#define iowrite32_native iowrite32be +-#else /* def __BIG_ENDIAN */ +-#define ioread16_native ioread16 +-#define iowrite16_native iowrite16 +-#define ioread32_native ioread32 +-#define iowrite32_native iowrite32 +-#endif /* def __BIG_ENDIAN else */ +-#endif /* !ioread32_native */ +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c b/drivers/gpu/drm/nouveau/core/subdev/bar/base.c +deleted file mode 100644 +index b1adc69e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bar/base.c ++++ /dev/null +@@ -1,149 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +- +-#include "priv.h" +- +-struct nouveau_barobj { +- struct nouveau_object base; +- struct nouveau_vma vma; +- void __iomem *iomem; +-}; +- +-static int +-nouveau_barobj_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_bar *bar = (void *)engine; +- struct nouveau_mem *mem = data; +- struct nouveau_barobj *barobj; +- int ret; +- +- ret = nouveau_object_create(parent, engine, oclass, 0, &barobj); +- *pobject = nv_object(barobj); +- if (ret) +- return ret; +- +- ret = bar->kmap(bar, mem, NV_MEM_ACCESS_RW, &barobj->vma); +- if (ret) +- return ret; +- +- barobj->iomem = ioremap(nv_device_resource_start(device, 3) + +- (u32)barobj->vma.offset, mem->size << 12); +- if (!barobj->iomem) { +- nv_warn(bar, "PRAMIN ioremap failed\n"); +- return -ENOMEM; +- } +- +- return 0; +-} +- +-static void +-nouveau_barobj_dtor(struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = (void *)object->engine; +- struct nouveau_barobj *barobj = (void *)object; +- if (barobj->vma.node) { +- if (barobj->iomem) +- iounmap(barobj->iomem); +- bar->unmap(bar, &barobj->vma); +- } +- nouveau_object_destroy(&barobj->base); +-} +- +-static u32 +-nouveau_barobj_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_barobj *barobj = (void *)object; +- return ioread32_native(barobj->iomem + addr); +-} +- +-static void +-nouveau_barobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nouveau_barobj *barobj = (void *)object; +- iowrite32_native(data, barobj->iomem + addr); +-} +- +-static struct nouveau_oclass +-nouveau_barobj_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nouveau_barobj_ctor, +- .dtor = nouveau_barobj_dtor, +- .init = nouveau_object_init, +- .fini = nouveau_object_fini, +- .rd32 = nouveau_barobj_rd32, +- .wr32 = nouveau_barobj_wr32, +- }, +-}; +- +-int +-nouveau_bar_alloc(struct nouveau_bar *bar, struct nouveau_object *parent, +- struct nouveau_mem *mem, struct nouveau_object **pobject) +-{ +- struct nouveau_object *engine = nv_object(bar); +- struct nouveau_object *gpuobj; +- int ret = nouveau_object_ctor(parent, engine, &nouveau_barobj_oclass, +- mem, 0, &gpuobj); +- if (ret == 0) +- *pobject = gpuobj; +- return ret; +-} +- +-int +-nouveau_bar_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- struct nouveau_bar *bar; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "BARCTL", +- "bar", length, pobject); +- bar = *pobject; +- if (ret) +- return ret; +- +- return 0; +-} +- +-void +-nouveau_bar_destroy(struct nouveau_bar *bar) +-{ +- nouveau_subdev_destroy(&bar->base); +-} +- +-void +-_nouveau_bar_dtor(struct nouveau_object *object) +-{ +- struct nouveau_bar *bar = (void *)object; +- nouveau_bar_destroy(bar); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c +deleted file mode 100644 +index bf877af9..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bar/gk20a.c ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +- +-#include "priv.h" +- +-int +-gk20a_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_bar *bar; +- int ret; +- +- ret = nvc0_bar_ctor(parent, engine, oclass, data, size, pobject); +- if (ret) +- return ret; +- +- bar = (struct nouveau_bar *)*pobject; +- bar->iomap_uncached = true; +- +- return 0; +-} +- +-struct nouveau_oclass +-gk20a_bar_oclass = { +- .handle = NV_SUBDEV(BAR, 0xea), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gk20a_bar_ctor, +- .dtor = nvc0_bar_dtor, +- .init = nvc0_bar_init, +- .fini = _nouveau_bar_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c +deleted file mode 100644 +index f748ba49..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nv50.c ++++ /dev/null +@@ -1,273 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +- +-#include "priv.h" +- +-struct nv50_bar_priv { +- struct nouveau_bar base; +- spinlock_t lock; +- struct nouveau_gpuobj *mem; +- struct nouveau_gpuobj *pad; +- struct nouveau_gpuobj *pgd; +- struct nouveau_vm *bar1_vm; +- struct nouveau_gpuobj *bar1; +- struct nouveau_vm *bar3_vm; +- struct nouveau_gpuobj *bar3; +-}; +- +-static int +-nv50_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem, +- u32 flags, struct nouveau_vma *vma) +-{ +- struct nv50_bar_priv *priv = (void *)bar; +- int ret; +- +- ret = nouveau_vm_get(priv->bar3_vm, mem->size << 12, 12, flags, vma); +- if (ret) +- return ret; +- +- nouveau_vm_map(vma, mem); +- return 0; +-} +- +-static int +-nv50_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem, +- u32 flags, struct nouveau_vma *vma) +-{ +- struct nv50_bar_priv *priv = (void *)bar; +- int ret; +- +- ret = nouveau_vm_get(priv->bar1_vm, mem->size << 12, 12, flags, vma); +- if (ret) +- return ret; +- +- nouveau_vm_map(vma, mem); +- return 0; +-} +- +-static void +-nv50_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma) +-{ +- nouveau_vm_unmap(vma); +- nouveau_vm_put(vma); +-} +- +-static void +-nv50_bar_flush(struct nouveau_bar *bar) +-{ +- struct nv50_bar_priv *priv = (void *)bar; +- unsigned long flags; +- spin_lock_irqsave(&priv->lock, flags); +- nv_wr32(priv, 0x00330c, 0x00000001); +- if (!nv_wait(priv, 0x00330c, 0x00000002, 0x00000000)) +- nv_warn(priv, "flush timeout\n"); +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-void +-nv84_bar_flush(struct nouveau_bar *bar) +-{ +- struct nv50_bar_priv *priv = (void *)bar; +- unsigned long flags; +- spin_lock_irqsave(&priv->lock, flags); +- nv_wr32(bar, 0x070000, 0x00000001); +- if (!nv_wait(priv, 0x070000, 0x00000002, 0x00000000)) +- nv_warn(priv, "flush timeout\n"); +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-static int +-nv50_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_object *heap; +- struct nouveau_vm *vm; +- struct nv50_bar_priv *priv; +- u64 start, limit; +- int ret; +- +- ret = nouveau_bar_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, +- NVOBJ_FLAG_HEAP, &priv->mem); +- heap = nv_object(priv->mem); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), heap, +- (device->chipset == 0x50) ? 0x1400 : 0x0200, +- 0, 0, &priv->pad); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), heap, 0x4000, 0, +- 0, &priv->pgd); +- if (ret) +- return ret; +- +- /* BAR3 */ +- start = 0x0100000000ULL; +- limit = start + nv_device_resource_len(device, 3); +- +- ret = nouveau_vm_new(device, start, limit, start, &vm); +- if (ret) +- return ret; +- +- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); +- +- ret = nouveau_gpuobj_new(nv_object(priv), heap, +- ((limit-- - start) >> 12) * 8, 0x1000, +- NVOBJ_FLAG_ZERO_ALLOC, &vm->pgt[0].obj[0]); +- vm->pgt[0].refcount[0] = 1; +- if (ret) +- return ret; +- +- ret = nouveau_vm_ref(vm, &priv->bar3_vm, priv->pgd); +- nouveau_vm_ref(NULL, &vm, NULL); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar3); +- if (ret) +- return ret; +- +- nv_wo32(priv->bar3, 0x00, 0x7fc00000); +- nv_wo32(priv->bar3, 0x04, lower_32_bits(limit)); +- nv_wo32(priv->bar3, 0x08, lower_32_bits(start)); +- nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 | +- upper_32_bits(start)); +- nv_wo32(priv->bar3, 0x10, 0x00000000); +- nv_wo32(priv->bar3, 0x14, 0x00000000); +- +- /* BAR1 */ +- start = 0x0000000000ULL; +- limit = start + nv_device_resource_len(device, 1); +- +- ret = nouveau_vm_new(device, start, limit--, start, &vm); +- if (ret) +- return ret; +- +- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); +- +- ret = nouveau_vm_ref(vm, &priv->bar1_vm, priv->pgd); +- nouveau_vm_ref(NULL, &vm, NULL); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), heap, 24, 16, 0, &priv->bar1); +- if (ret) +- return ret; +- +- nv_wo32(priv->bar1, 0x00, 0x7fc00000); +- nv_wo32(priv->bar1, 0x04, lower_32_bits(limit)); +- nv_wo32(priv->bar1, 0x08, lower_32_bits(start)); +- nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 24 | +- upper_32_bits(start)); +- nv_wo32(priv->bar1, 0x10, 0x00000000); +- nv_wo32(priv->bar1, 0x14, 0x00000000); +- +- priv->base.alloc = nouveau_bar_alloc; +- priv->base.kmap = nv50_bar_kmap; +- priv->base.umap = nv50_bar_umap; +- priv->base.unmap = nv50_bar_unmap; +- if (device->chipset == 0x50) +- priv->base.flush = nv50_bar_flush; +- else +- priv->base.flush = nv84_bar_flush; +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-static void +-nv50_bar_dtor(struct nouveau_object *object) +-{ +- struct nv50_bar_priv *priv = (void *)object; +- nouveau_gpuobj_ref(NULL, &priv->bar1); +- nouveau_vm_ref(NULL, &priv->bar1_vm, priv->pgd); +- nouveau_gpuobj_ref(NULL, &priv->bar3); +- if (priv->bar3_vm) { +- nouveau_gpuobj_ref(NULL, &priv->bar3_vm->pgt[0].obj[0]); +- nouveau_vm_ref(NULL, &priv->bar3_vm, priv->pgd); +- } +- nouveau_gpuobj_ref(NULL, &priv->pgd); +- nouveau_gpuobj_ref(NULL, &priv->pad); +- nouveau_gpuobj_ref(NULL, &priv->mem); +- nouveau_bar_destroy(&priv->base); +-} +- +-static int +-nv50_bar_init(struct nouveau_object *object) +-{ +- struct nv50_bar_priv *priv = (void *)object; +- int ret, i; +- +- ret = nouveau_bar_init(&priv->base); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x000200, 0x00000100, 0x00000000); +- nv_mask(priv, 0x000200, 0x00000100, 0x00000100); +- nv_wr32(priv, 0x100c80, 0x00060001); +- if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) { +- nv_error(priv, "vm flush timeout\n"); +- return -EBUSY; +- } +- +- nv_wr32(priv, 0x001704, 0x00000000 | priv->mem->addr >> 12); +- nv_wr32(priv, 0x001704, 0x40000000 | priv->mem->addr >> 12); +- nv_wr32(priv, 0x001708, 0x80000000 | priv->bar1->node->offset >> 4); +- nv_wr32(priv, 0x00170c, 0x80000000 | priv->bar3->node->offset >> 4); +- for (i = 0; i < 8; i++) +- nv_wr32(priv, 0x001900 + (i * 4), 0x00000000); +- return 0; +-} +- +-static int +-nv50_bar_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_bar_priv *priv = (void *)object; +- return nouveau_bar_fini(&priv->base, suspend); +-} +- +-struct nouveau_oclass +-nv50_bar_oclass = { +- .handle = NV_SUBDEV(BAR, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_bar_ctor, +- .dtor = nv50_bar_dtor, +- .init = nv50_bar_init, +- .fini = nv50_bar_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c +deleted file mode 100644 +index 05a278ba..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bar/nvc0.c ++++ /dev/null +@@ -1,220 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +- +-#include "priv.h" +- +-struct nvc0_bar_priv_vm { +- struct nouveau_gpuobj *mem; +- struct nouveau_gpuobj *pgd; +- struct nouveau_vm *vm; +-}; +- +-struct nvc0_bar_priv { +- struct nouveau_bar base; +- spinlock_t lock; +- struct nvc0_bar_priv_vm bar[2]; +-}; +- +-static int +-nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem, +- u32 flags, struct nouveau_vma *vma) +-{ +- struct nvc0_bar_priv *priv = (void *)bar; +- int ret; +- +- ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma); +- if (ret) +- return ret; +- +- nouveau_vm_map(vma, mem); +- return 0; +-} +- +-static int +-nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem, +- u32 flags, struct nouveau_vma *vma) +-{ +- struct nvc0_bar_priv *priv = (void *)bar; +- int ret; +- +- ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12, +- mem->page_shift, flags, vma); +- if (ret) +- return ret; +- +- nouveau_vm_map(vma, mem); +- return 0; +-} +- +-static void +-nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma) +-{ +- nouveau_vm_unmap(vma); +- nouveau_vm_put(vma); +-} +- +-static int +-nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm, +- int bar_nr) +-{ +- struct nouveau_device *device = nv_device(&priv->base); +- struct nouveau_vm *vm; +- resource_size_t bar_len; +- int ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0, +- &bar_vm->mem); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0, +- &bar_vm->pgd); +- if (ret) +- return ret; +- +- bar_len = nv_device_resource_len(device, bar_nr); +- +- ret = nouveau_vm_new(device, 0, bar_len, 0, &vm); +- if (ret) +- return ret; +- +- atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]); +- +- /* +- * Bootstrap page table lookup. +- */ +- if (bar_nr == 3) { +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, +- (bar_len >> 12) * 8, 0x1000, +- NVOBJ_FLAG_ZERO_ALLOC, +- &vm->pgt[0].obj[0]); +- vm->pgt[0].refcount[0] = 1; +- if (ret) +- return ret; +- } +- +- ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd); +- nouveau_vm_ref(NULL, &vm, NULL); +- if (ret) +- return ret; +- +- nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr)); +- nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr)); +- nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1)); +- nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1)); +- +- return 0; +-} +- +-int +-nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nvc0_bar_priv *priv; +- bool has_bar3 = nv_device_resource_len(device, 3) != 0; +- int ret; +- +- ret = nouveau_bar_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- /* BAR3 */ +- if (has_bar3) { +- ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3); +- if (ret) +- return ret; +- priv->base.alloc = nouveau_bar_alloc; +- priv->base.kmap = nvc0_bar_kmap; +- } +- +- /* BAR1 */ +- ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1); +- if (ret) +- return ret; +- +- priv->base.umap = nvc0_bar_umap; +- priv->base.unmap = nvc0_bar_unmap; +- priv->base.flush = nv84_bar_flush; +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-void +-nvc0_bar_dtor(struct nouveau_object *object) +-{ +- struct nvc0_bar_priv *priv = (void *)object; +- +- nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd); +- nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd); +- nouveau_gpuobj_ref(NULL, &priv->bar[1].mem); +- +- if (priv->bar[0].vm) { +- nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]); +- nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd); +- } +- nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd); +- nouveau_gpuobj_ref(NULL, &priv->bar[0].mem); +- +- nouveau_bar_destroy(&priv->base); +-} +- +-int +-nvc0_bar_init(struct nouveau_object *object) +-{ +- struct nvc0_bar_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_bar_init(&priv->base); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x000200, 0x00000100, 0x00000000); +- nv_mask(priv, 0x000200, 0x00000100, 0x00000100); +- +- nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12); +- if (priv->bar[0].mem) +- nv_wr32(priv, 0x001714, +- 0xc0000000 | priv->bar[0].mem->addr >> 12); +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_bar_oclass = { +- .handle = NV_SUBDEV(BAR, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_bar_ctor, +- .dtor = nvc0_bar_dtor, +- .init = nvc0_bar_init, +- .fini = _nouveau_bar_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h b/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h +deleted file mode 100644 +index 3ee8b147..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bar/priv.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-#ifndef __NVKM_BAR_PRIV_H__ +-#define __NVKM_BAR_PRIV_H__ +- +-#include +- +-#define nouveau_bar_create(p,e,o,d) \ +- nouveau_bar_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_bar_init(p) \ +- nouveau_subdev_init(&(p)->base) +-#define nouveau_bar_fini(p,s) \ +- nouveau_subdev_fini(&(p)->base, (s)) +- +-int nouveau_bar_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void nouveau_bar_destroy(struct nouveau_bar *); +- +-void _nouveau_bar_dtor(struct nouveau_object *); +-#define _nouveau_bar_init _nouveau_subdev_init +-#define _nouveau_bar_fini _nouveau_subdev_fini +- +-int nouveau_bar_alloc(struct nouveau_bar *, struct nouveau_object *, +- struct nouveau_mem *, struct nouveau_object **); +- +-void nv84_bar_flush(struct nouveau_bar *); +- +-int nvc0_bar_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nvc0_bar_dtor(struct nouveau_object *); +-int nvc0_bar_init(struct nouveau_object *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c +deleted file mode 100644 +index ac9617c5..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0205.c ++++ /dev/null +@@ -1,136 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u32 +-nvbios_M0205Te(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +-{ +- struct bit_entry bit_M; +- u32 data = 0x00000000; +- +- if (!bit_entry(bios, 'M', &bit_M)) { +- if (bit_M.version == 2 && bit_M.length > 0x08) +- data = nv_ro32(bios, bit_M.offset + 0x05); +- if (data) { +- *ver = nv_ro08(bios, data + 0x00); +- switch (*ver) { +- case 0x10: +- *hdr = nv_ro08(bios, data + 0x01); +- *len = nv_ro08(bios, data + 0x02); +- *ssz = nv_ro08(bios, data + 0x03); +- *snr = nv_ro08(bios, data + 0x04); +- *cnt = nv_ro08(bios, data + 0x05); +- return data; +- default: +- break; +- } +- } +- } +- +- return 0x00000000; +-} +- +-u32 +-nvbios_M0205Tp(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz, +- struct nvbios_M0205T *info) +-{ +- u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, snr, ssz); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- info->freq = nv_ro16(bios, data + 0x06); +- break; +- default: +- break; +- } +- return data; +-} +- +-u32 +-nvbios_M0205Ee(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u8 snr, ssz; +- u32 data = nvbios_M0205Te(bios, ver, hdr, cnt, len, &snr, &ssz); +- if (data && idx < *cnt) { +- data = data + *hdr + idx * (*len + (snr * ssz)); +- *hdr = *len; +- *cnt = snr; +- *len = ssz; +- return data; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_M0205Ep(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_M0205E *info) +-{ +- u32 data = nvbios_M0205Ee(bios, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- info->type = nv_ro08(bios, data + 0x00) & 0x0f; +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_M0205Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) +-{ +- +- u8 cnt, len; +- u32 data = nvbios_M0205Ee(bios, ent, ver, hdr, &cnt, &len); +- if (data && idx < cnt) { +- data = data + *hdr + idx * len; +- *hdr = len; +- return data; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_M0205Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, +- struct nvbios_M0205S *info) +-{ +- u32 data = nvbios_M0205Se(bios, ent, idx, ver, hdr); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- info->data = nv_ro08(bios, data + 0x00); +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c b/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c +deleted file mode 100644 +index b142a510..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/M0209.c ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u32 +-nvbios_M0209Te(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +-{ +- struct bit_entry bit_M; +- u32 data = 0x00000000; +- +- if (!bit_entry(bios, 'M', &bit_M)) { +- if (bit_M.version == 2 && bit_M.length > 0x0c) +- data = nv_ro32(bios, bit_M.offset + 0x09); +- if (data) { +- *ver = nv_ro08(bios, data + 0x00); +- switch (*ver) { +- case 0x10: +- *hdr = nv_ro08(bios, data + 0x01); +- *len = nv_ro08(bios, data + 0x02); +- *ssz = nv_ro08(bios, data + 0x03); +- *snr = 1; +- *cnt = nv_ro08(bios, data + 0x04); +- return data; +- default: +- break; +- } +- } +- } +- +- return 0x00000000; +-} +- +-u32 +-nvbios_M0209Ee(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u8 snr, ssz; +- u32 data = nvbios_M0209Te(bios, ver, hdr, cnt, len, &snr, &ssz); +- if (data && idx < *cnt) { +- data = data + *hdr + idx * (*len + (snr * ssz)); +- *hdr = *len; +- *cnt = snr; +- *len = ssz; +- return data; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_M0209Ep(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_M0209E *info) +-{ +- u32 data = nvbios_M0209Ee(bios, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- info->v00_40 = (nv_ro08(bios, data + 0x00) & 0x40) >> 6; +- info->bits = nv_ro08(bios, data + 0x00) & 0x3f; +- info->modulo = nv_ro08(bios, data + 0x01); +- info->v02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; +- info->v02_07 = nv_ro08(bios, data + 0x02) & 0x07; +- info->v03 = nv_ro08(bios, data + 0x03); +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_M0209Se(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr) +-{ +- +- u8 cnt, len; +- u32 data = nvbios_M0209Ee(bios, ent, ver, hdr, &cnt, &len); +- if (data && idx < cnt) { +- data = data + *hdr + idx * len; +- *hdr = len; +- return data; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_M0209Sp(struct nouveau_bios *bios, int ent, int idx, u8 *ver, u8 *hdr, +- struct nvbios_M0209S *info) +-{ +- struct nvbios_M0209E M0209E; +- u8 cnt, len; +- u32 data = nvbios_M0209Ep(bios, ent, ver, hdr, &cnt, &len, &M0209E); +- if (data) { +- u32 i, data = nvbios_M0209Se(bios, ent, idx, ver, hdr); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- for (i = 0; i < ARRAY_SIZE(info->data); i++) { +- u32 bits = (i % M0209E.modulo) * M0209E.bits; +- u32 mask = (1ULL << M0209E.bits) - 1; +- u16 off = bits / 8; +- u8 mod = bits % 8; +- info->data[i] = nv_ro32(bios, data + off); +- info->data[i] = info->data[i] >> mod; +- info->data[i] = info->data[i] & mask; +- } +- return data; +- default: +- break; +- } +- } +- return 0x00000000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c b/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c +deleted file mode 100644 +index 199f4e5f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/P0260.c ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-u32 +-nvbios_P0260Te(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz) +-{ +- struct bit_entry bit_P; +- u32 data = 0x00000000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2 && bit_P.length > 0x63) +- data = nv_ro32(bios, bit_P.offset + 0x60); +- if (data) { +- *ver = nv_ro08(bios, data + 0); +- switch (*ver) { +- case 0x10: +- *hdr = nv_ro08(bios, data + 1); +- *cnt = nv_ro08(bios, data + 2); +- *len = 4; +- *xnr = nv_ro08(bios, data + 3); +- *xsz = 4; +- return data; +- default: +- break; +- } +- } +- } +- +- return 0x00000000; +-} +- +-u32 +-nvbios_P0260Ee(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt, xnr, xsz; +- u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, len, &xnr, &xsz); +- if (data && idx < cnt) +- return data + hdr + (idx * *len); +- return 0x00000000; +-} +- +-u32 +-nvbios_P0260Ep(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, +- struct nvbios_P0260E *info) +-{ +- u32 data = nvbios_P0260Ee(bios, idx, ver, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- info->data = nv_ro32(bios, data); +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_P0260Xe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *xsz) +-{ +- u8 hdr, cnt, len, xnr; +- u32 data = nvbios_P0260Te(bios, ver, &hdr, &cnt, &len, &xnr, xsz); +- if (data && idx < xnr) +- return data + hdr + (cnt * len) + (idx * *xsz); +- return 0x00000000; +-} +- +-u32 +-nvbios_P0260Xp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +- struct nvbios_P0260X *info) +-{ +- u32 data = nvbios_P0260Xe(bios, idx, ver, hdr); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x10: +- info->data = nv_ro32(bios, data); +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c b/drivers/gpu/drm/nouveau/core/subdev/bios/base.c +deleted file mode 100644 +index d45704a2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/base.c ++++ /dev/null +@@ -1,552 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-u8 +-nvbios_checksum(const u8 *data, int size) +-{ +- u8 sum = 0; +- while (size--) +- sum += *data++; +- return sum; +-} +- +-u16 +-nvbios_findstr(const u8 *data, int size, const char *str, int len) +-{ +- int i, j; +- +- for (i = 0; i <= (size - len); i++) { +- for (j = 0; j < len; j++) +- if ((char)data[i + j] != str[j]) +- break; +- if (j == len) +- return i; +- } +- +- return 0; +-} +- +-#if defined(__powerpc__) +-static void +-nouveau_bios_shadow_of(struct nouveau_bios *bios) +-{ +- struct pci_dev *pdev = nv_device(bios)->pdev; +- struct device_node *dn; +- const u32 *data; +- int size; +- +- dn = pci_device_to_OF_node(pdev); +- if (!dn) { +- nv_info(bios, "Unable to get the OF node\n"); +- return; +- } +- +- data = of_get_property(dn, "NVDA,BMP", &size); +- if (data && size) { +- bios->size = size; +- bios->data = kmalloc(bios->size, GFP_KERNEL); +- if (bios->data) +- memcpy(bios->data, data, size); +- } +-} +-#endif +- +-static void +-nouveau_bios_shadow_pramin(struct nouveau_bios *bios) +-{ +- struct nouveau_device *device = nv_device(bios); +- u64 addr = 0; +- u32 bar0 = 0; +- int i; +- +- if (device->card_type >= NV_50) { +- if (device->card_type >= NV_C0 && device->card_type < GM100) { +- if (nv_rd32(bios, 0x022500) & 0x00000001) +- return; +- } else +- if (device->card_type >= GM100) { +- if (nv_rd32(bios, 0x021c04) & 0x00000001) +- return; +- } +- +- addr = nv_rd32(bios, 0x619f04); +- if (!(addr & 0x00000008)) { +- nv_debug(bios, "... not enabled\n"); +- return; +- } +- if ( (addr & 0x00000003) != 1) { +- nv_debug(bios, "... not in vram\n"); +- return; +- } +- +- addr = (addr & 0xffffff00) << 8; +- if (!addr) { +- addr = (u64)nv_rd32(bios, 0x001700) << 16; +- addr += 0xf0000; +- } +- +- bar0 = nv_mask(bios, 0x001700, 0xffffffff, addr >> 16); +- } +- +- /* bail if no rom signature */ +- if (nv_rd08(bios, 0x700000) != 0x55 || +- nv_rd08(bios, 0x700001) != 0xaa) +- goto out; +- +- bios->size = nv_rd08(bios, 0x700002) * 512; +- if (!bios->size) +- goto out; +- +- bios->data = kmalloc(bios->size, GFP_KERNEL); +- if (bios->data) { +- for (i = 0; i < bios->size; i++) +- nv_wo08(bios, i, nv_rd08(bios, 0x700000 + i)); +- } +- +-out: +- if (device->card_type >= NV_50) +- nv_wr32(bios, 0x001700, bar0); +-} +- +-static void +-nouveau_bios_shadow_prom(struct nouveau_bios *bios) +-{ +- struct nouveau_device *device = nv_device(bios); +- u32 pcireg, access; +- u16 pcir; +- int i; +- +- /* there is no prom on nv4x IGP's */ +- if (device->card_type == NV_40 && device->chipset >= 0x4c) +- return; +- +- /* enable access to rom */ +- if (device->card_type >= NV_50) +- pcireg = 0x088050; +- else +- pcireg = 0x001850; +- access = nv_mask(bios, pcireg, 0x00000001, 0x00000000); +- +- /* WARNING: PROM accesses should always be 32-bits aligned. Other +- * accesses work on most chipset but do not on Kepler chipsets +- */ +- +- /* bail if no rom signature, with a workaround for a PROM reading +- * issue on some chipsets. the first read after a period of +- * inactivity returns the wrong result, so retry the first header +- * byte a few times before giving up as a workaround +- */ +- i = 16; +- do { +- u32 data = le32_to_cpu(nv_rd32(bios, 0x300000)) & 0xffff; +- if (data == 0xaa55) +- break; +- } while (i--); +- +- if (!i) +- goto out; +- +- /* read entire bios image to system memory */ +- bios->size = (le32_to_cpu(nv_rd32(bios, 0x300000)) >> 16) & 0xff; +- bios->size = bios->size * 512; +- if (!bios->size) +- goto out; +- +- bios->data = kmalloc(bios->size, GFP_KERNEL); +- if (!bios->data) +- goto out; +- +- for (i = 0; i < bios->size; i += 4) +- ((u32 *)bios->data)[i/4] = nv_rd32(bios, 0x300000 + i); +- +- /* check the PCI record header */ +- pcir = nv_ro16(bios, 0x0018); +- if (bios->data[pcir + 0] != 'P' || +- bios->data[pcir + 1] != 'C' || +- bios->data[pcir + 2] != 'I' || +- bios->data[pcir + 3] != 'R') { +- bios->size = 0; +- kfree(bios->data); +- } +- +-out: +- /* disable access to rom */ +- nv_wr32(bios, pcireg, access); +-} +- +-#if defined(CONFIG_ACPI) && defined(CONFIG_X86) +-int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); +-bool nouveau_acpi_rom_supported(struct pci_dev *pdev); +-#else +-static inline bool +-nouveau_acpi_rom_supported(struct pci_dev *pdev) { +- return false; +-} +- +-static inline int +-nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { +- return -EINVAL; +-} +-#endif +- +-static void +-nouveau_bios_shadow_acpi(struct nouveau_bios *bios) +-{ +- struct pci_dev *pdev = nv_device(bios)->pdev; +- int ret, cnt, i; +- +- if (!nouveau_acpi_rom_supported(pdev)) { +- bios->data = NULL; +- return; +- } +- +- bios->size = 0; +- bios->data = kmalloc(4096, GFP_KERNEL); +- if (bios->data) { +- if (nouveau_acpi_get_bios_chunk(bios->data, 0, 4096) == 4096) +- bios->size = bios->data[2] * 512; +- kfree(bios->data); +- } +- +- if (!bios->size) +- return; +- +- bios->data = kmalloc(bios->size, GFP_KERNEL); +- if (bios->data) { +- /* disobey the acpi spec - much faster on at least w530 ... */ +- ret = nouveau_acpi_get_bios_chunk(bios->data, 0, bios->size); +- if (ret != bios->size || +- nvbios_checksum(bios->data, bios->size)) { +- /* ... that didn't work, ok, i'll be good now */ +- for (i = 0; i < bios->size; i += cnt) { +- cnt = min((bios->size - i), (u32)4096); +- ret = nouveau_acpi_get_bios_chunk(bios->data, i, cnt); +- if (ret != cnt) +- break; +- } +- } +- } +-} +- +-static void +-nouveau_bios_shadow_pci(struct nouveau_bios *bios) +-{ +- struct pci_dev *pdev = nv_device(bios)->pdev; +- size_t size; +- +- if (!pci_enable_rom(pdev)) { +- void __iomem *rom = pci_map_rom(pdev, &size); +- if (rom && size) { +- bios->data = kmalloc(size, GFP_KERNEL); +- if (bios->data) { +- memcpy_fromio(bios->data, rom, size); +- bios->size = size; +- } +- } +- if (rom) +- pci_unmap_rom(pdev, rom); +- +- pci_disable_rom(pdev); +- } +-} +- +-static void +-nouveau_bios_shadow_platform(struct nouveau_bios *bios) +-{ +- struct pci_dev *pdev = nv_device(bios)->pdev; +- size_t size; +- +- void __iomem *rom = pci_platform_rom(pdev, &size); +- if (rom && size) { +- bios->data = kmalloc(size, GFP_KERNEL); +- if (bios->data) { +- memcpy_fromio(bios->data, rom, size); +- bios->size = size; +- } +- } +-} +- +-static int +-nouveau_bios_score(struct nouveau_bios *bios, const bool writeable) +-{ +- if (bios->size < 3 || !bios->data || bios->data[0] != 0x55 || +- bios->data[1] != 0xAA) { +- nv_info(bios, "... signature not found\n"); +- return 0; +- } +- +- if (nvbios_checksum(bios->data, +- min_t(u32, bios->data[2] * 512, bios->size))) { +- nv_info(bios, "... checksum invalid\n"); +- /* if a ro image is somewhat bad, it's probably all rubbish */ +- return writeable ? 2 : 1; +- } +- +- nv_info(bios, "... appears to be valid\n"); +- return 3; +-} +- +-struct methods { +- const char desc[16]; +- void (*shadow)(struct nouveau_bios *); +- const bool rw; +- int score; +- u32 size; +- u8 *data; +-}; +- +-static int +-nouveau_bios_shadow(struct nouveau_bios *bios) +-{ +- struct methods shadow_methods[] = { +-#if defined(__powerpc__) +- { "OpenFirmware", nouveau_bios_shadow_of, true, 0, 0, NULL }, +-#endif +- { "PRAMIN", nouveau_bios_shadow_pramin, true, 0, 0, NULL }, +- { "PROM", nouveau_bios_shadow_prom, false, 0, 0, NULL }, +- { "ACPI", nouveau_bios_shadow_acpi, true, 0, 0, NULL }, +- { "PCIROM", nouveau_bios_shadow_pci, true, 0, 0, NULL }, +- { "PLATFORM", nouveau_bios_shadow_platform, true, 0, 0, NULL }, +- {} +- }; +- struct methods *mthd, *best; +- const struct firmware *fw; +- const char *optarg; +- int optlen, ret; +- char *source; +- +- optarg = nouveau_stropt(nv_device(bios)->cfgopt, "NvBios", &optlen); +- source = optarg ? kstrndup(optarg, optlen, GFP_KERNEL) : NULL; +- if (source) { +- /* try to match one of the built-in methods */ +- mthd = shadow_methods; +- do { +- if (strcasecmp(source, mthd->desc)) +- continue; +- nv_info(bios, "source: %s\n", mthd->desc); +- +- mthd->shadow(bios); +- mthd->score = nouveau_bios_score(bios, mthd->rw); +- if (mthd->score) { +- kfree(source); +- return 0; +- } +- } while ((++mthd)->shadow); +- +- /* attempt to load firmware image */ +- ret = request_firmware(&fw, source, &nv_device(bios)->pdev->dev); +- if (ret == 0) { +- bios->size = fw->size; +- bios->data = kmemdup(fw->data, fw->size, GFP_KERNEL); +- release_firmware(fw); +- +- nv_info(bios, "image: %s\n", source); +- if (nouveau_bios_score(bios, 1)) { +- kfree(source); +- return 0; +- } +- +- kfree(bios->data); +- bios->data = NULL; +- } +- +- nv_error(bios, "source \'%s\' invalid\n", source); +- kfree(source); +- } +- +- mthd = shadow_methods; +- do { +- nv_info(bios, "checking %s for image...\n", mthd->desc); +- mthd->shadow(bios); +- mthd->score = nouveau_bios_score(bios, mthd->rw); +- mthd->size = bios->size; +- mthd->data = bios->data; +- bios->data = NULL; +- } while (mthd->score != 3 && (++mthd)->shadow); +- +- mthd = shadow_methods; +- best = mthd; +- do { +- if (mthd->score > best->score) { +- kfree(best->data); +- best = mthd; +- } +- } while ((++mthd)->shadow); +- +- if (best->score) { +- nv_info(bios, "using image from %s\n", best->desc); +- bios->size = best->size; +- bios->data = best->data; +- return 0; +- } +- +- nv_error(bios, "unable to locate usable image\n"); +- return -EINVAL; +-} +- +-static u8 +-nouveau_bios_rd08(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_bios *bios = (void *)object; +- return bios->data[addr]; +-} +- +-static u16 +-nouveau_bios_rd16(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_bios *bios = (void *)object; +- return get_unaligned_le16(&bios->data[addr]); +-} +- +-static u32 +-nouveau_bios_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nouveau_bios *bios = (void *)object; +- return get_unaligned_le32(&bios->data[addr]); +-} +- +-static void +-nouveau_bios_wr08(struct nouveau_object *object, u64 addr, u8 data) +-{ +- struct nouveau_bios *bios = (void *)object; +- bios->data[addr] = data; +-} +- +-static void +-nouveau_bios_wr16(struct nouveau_object *object, u64 addr, u16 data) +-{ +- struct nouveau_bios *bios = (void *)object; +- put_unaligned_le16(data, &bios->data[addr]); +-} +- +-static void +-nouveau_bios_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nouveau_bios *bios = (void *)object; +- put_unaligned_le32(data, &bios->data[addr]); +-} +- +-static int +-nouveau_bios_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_bios *bios; +- struct bit_entry bit_i; +- int ret; +- +- ret = nouveau_subdev_create(parent, engine, oclass, 0, +- "VBIOS", "bios", &bios); +- *pobject = nv_object(bios); +- if (ret) +- return ret; +- +- ret = nouveau_bios_shadow(bios); +- if (ret) +- return ret; +- +- /* detect type of vbios we're dealing with */ +- bios->bmp_offset = nvbios_findstr(bios->data, bios->size, +- "\xff\x7f""NV\0", 5); +- if (bios->bmp_offset) { +- nv_info(bios, "BMP version %x.%x\n", +- bmp_version(bios) >> 8, +- bmp_version(bios) & 0xff); +- } +- +- bios->bit_offset = nvbios_findstr(bios->data, bios->size, +- "\xff\xb8""BIT", 5); +- if (bios->bit_offset) +- nv_info(bios, "BIT signature found\n"); +- +- /* determine the vbios version number */ +- if (!bit_entry(bios, 'i', &bit_i) && bit_i.length >= 4) { +- bios->version.major = nv_ro08(bios, bit_i.offset + 3); +- bios->version.chip = nv_ro08(bios, bit_i.offset + 2); +- bios->version.minor = nv_ro08(bios, bit_i.offset + 1); +- bios->version.micro = nv_ro08(bios, bit_i.offset + 0); +- bios->version.patch = nv_ro08(bios, bit_i.offset + 4); +- } else +- if (bmp_version(bios)) { +- bios->version.major = nv_ro08(bios, bios->bmp_offset + 13); +- bios->version.chip = nv_ro08(bios, bios->bmp_offset + 12); +- bios->version.minor = nv_ro08(bios, bios->bmp_offset + 11); +- bios->version.micro = nv_ro08(bios, bios->bmp_offset + 10); +- } +- +- nv_info(bios, "version %02x.%02x.%02x.%02x.%02x\n", +- bios->version.major, bios->version.chip, +- bios->version.minor, bios->version.micro, bios->version.patch); +- +- return 0; +-} +- +-static void +-nouveau_bios_dtor(struct nouveau_object *object) +-{ +- struct nouveau_bios *bios = (void *)object; +- kfree(bios->data); +- nouveau_subdev_destroy(&bios->base); +-} +- +-static int +-nouveau_bios_init(struct nouveau_object *object) +-{ +- struct nouveau_bios *bios = (void *)object; +- return nouveau_subdev_init(&bios->base); +-} +- +-static int +-nouveau_bios_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_bios *bios = (void *)object; +- return nouveau_subdev_fini(&bios->base, suspend); +-} +- +-struct nouveau_oclass +-nouveau_bios_oclass = { +- .handle = NV_SUBDEV(VBIOS, 0x00), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nouveau_bios_ctor, +- .dtor = nouveau_bios_dtor, +- .init = nouveau_bios_init, +- .fini = nouveau_bios_fini, +- .rd08 = nouveau_bios_rd08, +- .rd16 = nouveau_bios_rd16, +- .rd32 = nouveau_bios_rd32, +- .wr08 = nouveau_bios_wr08, +- .wr16 = nouveau_bios_wr16, +- .wr32 = nouveau_bios_wr32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c b/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c +deleted file mode 100644 +index 1d03a3f2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/bit.c ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "core/object.h" +- +-#include "subdev/bios.h" +-#include "subdev/bios/bit.h" +- +-int +-bit_entry(struct nouveau_bios *bios, u8 id, struct bit_entry *bit) +-{ +- if (likely(bios->bit_offset)) { +- u8 entries = nv_ro08(bios, bios->bit_offset + 10); +- u32 entry = bios->bit_offset + 12; +- while (entries--) { +- if (nv_ro08(bios, entry + 0) == id) { +- bit->id = nv_ro08(bios, entry + 0); +- bit->version = nv_ro08(bios, entry + 1); +- bit->length = nv_ro16(bios, entry + 2); +- bit->offset = nv_ro16(bios, entry + 4); +- return 0; +- } +- +- entry += nv_ro08(bios, bios->bit_offset + 9); +- } +- +- return -ENOENT; +- } +- +- return -EINVAL; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c b/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c +deleted file mode 100644 +index c1835e59..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/boost.c ++++ /dev/null +@@ -1,127 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_boostTe(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +-{ +- struct bit_entry bit_P; +- u16 boost = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2) +- boost = nv_ro16(bios, bit_P.offset + 0x30); +- +- if (boost) { +- *ver = nv_ro08(bios, boost + 0); +- switch (*ver) { +- case 0x11: +- *hdr = nv_ro08(bios, boost + 1); +- *cnt = nv_ro08(bios, boost + 5); +- *len = nv_ro08(bios, boost + 2); +- *snr = nv_ro08(bios, boost + 4); +- *ssz = nv_ro08(bios, boost + 3); +- return boost; +- default: +- break; +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_boostEe(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u8 snr, ssz; +- u16 data = nvbios_boostTe(bios, ver, hdr, cnt, len, &snr, &ssz); +- if (data && idx < *cnt) { +- data = data + *hdr + (idx * (*len + (snr * ssz))); +- *hdr = *len; +- *cnt = snr; +- *len = ssz; +- return data; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_boostEp(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info) +-{ +- u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- if (data) { +- info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5; +- info->min = nv_ro16(bios, data + 0x02) * 1000; +- info->max = nv_ro16(bios, data + 0x04) * 1000; +- } +- return data; +-} +- +-u16 +-nvbios_boostEm(struct nouveau_bios *bios, u8 pstate, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info) +-{ +- u32 data, idx = 0; +- while ((data = nvbios_boostEp(bios, idx++, ver, hdr, cnt, len, info))) { +- if (info->pstate == pstate) +- break; +- } +- return data; +-} +- +-u16 +-nvbios_boostSe(struct nouveau_bios *bios, int idx, +- u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len) +-{ +- if (data && idx < cnt) { +- data = data + *hdr + (idx * len); +- *hdr = len; +- return data; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_boostSp(struct nouveau_bios *bios, int idx, +- u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len, +- struct nvbios_boostS *info) +-{ +- data = nvbios_boostSe(bios, idx, data, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- if (data) { +- info->domain = nv_ro08(bios, data + 0x00); +- info->percent = nv_ro08(bios, data + 0x01); +- info->min = nv_ro16(bios, data + 0x02) * 1000; +- info->max = nv_ro16(bios, data + 0x04) * 1000; +- } +- return data; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c b/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c +deleted file mode 100644 +index 2ede3bcd..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/conn.c ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +- +-u32 +-nvbios_connTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u32 dcb = dcb_table(bios, ver, hdr, cnt, len); +- if (dcb && *ver >= 0x30 && *hdr >= 0x16) { +- u32 data = nv_ro16(bios, dcb + 0x14); +- if (data) { +- *ver = nv_ro08(bios, data + 0); +- *hdr = nv_ro08(bios, data + 1); +- *cnt = nv_ro08(bios, data + 2); +- *len = nv_ro08(bios, data + 3); +- return data; +- } +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_connTp(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_connT *info) +-{ +- u32 data = nvbios_connTe(bios, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x30: +- case 0x40: +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +- +-u32 +-nvbios_connEe(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u32 data = nvbios_connTe(bios, ver, &hdr, &cnt, len); +- if (data && idx < cnt) +- return data + hdr + (idx * *len); +- return 0x00000000; +-} +- +-u32 +-nvbios_connEp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len, +- struct nvbios_connE *info) +-{ +- u32 data = nvbios_connEe(bios, idx, ver, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x30: +- case 0x40: +- info->type = nv_ro08(bios, data + 0x00); +- info->location = nv_ro08(bios, data + 0x01) & 0x0f; +- info->hpd = (nv_ro08(bios, data + 0x01) & 0x30) >> 4; +- info->dp = (nv_ro08(bios, data + 0x01) & 0xc0) >> 6; +- if (*len < 4) +- return data; +- info->hpd |= (nv_ro08(bios, data + 0x02) & 0x03) << 2; +- info->dp |= nv_ro08(bios, data + 0x02) & 0x0c; +- info->di = (nv_ro08(bios, data + 0x02) & 0xf0) >> 4; +- info->hpd |= (nv_ro08(bios, data + 0x03) & 0x07) << 4; +- info->sr = (nv_ro08(bios, data + 0x03) & 0x08) >> 3; +- info->lcdid = (nv_ro08(bios, data + 0x03) & 0x70) >> 4; +- return data; +- default: +- break; +- } +- return 0x00000000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c b/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c +deleted file mode 100644 +index d3b15327..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c ++++ /dev/null +@@ -1,123 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_cstepTe(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz) +-{ +- struct bit_entry bit_P; +- u16 cstep = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2) +- cstep = nv_ro16(bios, bit_P.offset + 0x34); +- +- if (cstep) { +- *ver = nv_ro08(bios, cstep + 0); +- switch (*ver) { +- case 0x10: +- *hdr = nv_ro08(bios, cstep + 1); +- *cnt = nv_ro08(bios, cstep + 3); +- *len = nv_ro08(bios, cstep + 2); +- *xnr = nv_ro08(bios, cstep + 5); +- *xsz = nv_ro08(bios, cstep + 4); +- return cstep; +- default: +- break; +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) +-{ +- u8 cnt, len, xnr, xsz; +- u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); +- if (data && idx < cnt) { +- data = data + *hdr + (idx * len); +- *hdr = len; +- return data; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +- struct nvbios_cstepE *info) +-{ +- u16 data = nvbios_cstepEe(bios, idx, ver, hdr); +- memset(info, 0x00, sizeof(*info)); +- if (data) { +- info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5; +- info->index = nv_ro08(bios, data + 0x03); +- } +- return data; +-} +- +-u16 +-nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr, +- struct nvbios_cstepE *info) +-{ +- u32 data, idx = 0; +- while ((data = nvbios_cstepEp(bios, idx++, ver, hdr, info))) { +- if (info->pstate == pstate) +- break; +- } +- return data; +-} +- +-u16 +-nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr) +-{ +- u8 cnt, len, xnr, xsz; +- u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz); +- if (data && idx < xnr) { +- data = data + *hdr + (cnt * len) + (idx * xsz); +- *hdr = xsz; +- return data; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_cstepXp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +- struct nvbios_cstepX *info) +-{ +- u16 data = nvbios_cstepXe(bios, idx, ver, hdr); +- memset(info, 0x00, sizeof(*info)); +- if (data) { +- info->freq = nv_ro16(bios, data + 0x00) * 1000; +- info->unkn[0] = nv_ro08(bios, data + 0x02); +- info->unkn[1] = nv_ro08(bios, data + 0x03); +- info->voltage = nv_ro08(bios, data + 0x04); +- } +- return data; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c +deleted file mode 100644 +index bd8d3483..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dcb.c ++++ /dev/null +@@ -1,232 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "core/device.h" +- +-#include "subdev/bios.h" +-#include "subdev/bios/dcb.h" +- +-u16 +-dcb_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct nouveau_device *device = nv_device(bios); +- u16 dcb = 0x0000; +- +- if (device->card_type > NV_04) +- dcb = nv_ro16(bios, 0x36); +- if (!dcb) { +- nv_warn(bios, "DCB table not found\n"); +- return dcb; +- } +- +- *ver = nv_ro08(bios, dcb); +- +- if (*ver >= 0x41) { +- nv_warn(bios, "DCB version 0x%02x unknown\n", *ver); +- return 0x0000; +- } else +- if (*ver >= 0x30) { +- if (nv_ro32(bios, dcb + 6) == 0x4edcbdcb) { +- *hdr = nv_ro08(bios, dcb + 1); +- *cnt = nv_ro08(bios, dcb + 2); +- *len = nv_ro08(bios, dcb + 3); +- return dcb; +- } +- } else +- if (*ver >= 0x20) { +- if (nv_ro32(bios, dcb + 4) == 0x4edcbdcb) { +- u16 i2c = nv_ro16(bios, dcb + 2); +- *hdr = 8; +- *cnt = (i2c - dcb) / 8; +- *len = 8; +- return dcb; +- } +- } else +- if (*ver >= 0x15) { +- if (!nv_memcmp(bios, dcb - 7, "DEV_REC", 7)) { +- u16 i2c = nv_ro16(bios, dcb + 2); +- *hdr = 4; +- *cnt = (i2c - dcb) / 10; +- *len = 10; +- return dcb; +- } +- } else { +- /* +- * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but +- * always has the same single (crt) entry, even when tv-out +- * present, so the conclusion is this version cannot really +- * be used. +- * +- * v1.2 tables (some NV6/10, and NV15+) normally have the +- * same 5 entries, which are not specific to the card and so +- * no use. +- * +- * v1.2 does have an I2C table that read_dcb_i2c_table can +- * handle, but cards exist (nv11 in #14821) with a bad i2c +- * table pointer, so use the indices parsed in +- * parse_bmp_structure. +- * +- * v1.1 (NV5+, maybe some NV4) is entirely unhelpful +- */ +- nv_warn(bios, "DCB contains no useful data\n"); +- return 0x0000; +- } +- +- nv_warn(bios, "DCB header validation failed\n"); +- return 0x0000; +-} +- +-u16 +-dcb_outp(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u16 dcb = dcb_table(bios, ver, &hdr, &cnt, len); +- if (dcb && idx < cnt) +- return dcb + hdr + (idx * *len); +- return 0x0000; +-} +- +-static inline u16 +-dcb_outp_hasht(struct dcb_output *outp) +-{ +- return (outp->extdev << 8) | (outp->location << 4) | outp->type; +-} +- +-static inline u16 +-dcb_outp_hashm(struct dcb_output *outp) +-{ +- return (outp->heads << 8) | (outp->link << 6) | outp->or; +-} +- +-u16 +-dcb_outp_parse(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len, +- struct dcb_output *outp) +-{ +- u16 dcb = dcb_outp(bios, idx, ver, len); +- memset(outp, 0x00, sizeof(*outp)); +- if (dcb) { +- if (*ver >= 0x20) { +- u32 conn = nv_ro32(bios, dcb + 0x00); +- outp->or = (conn & 0x0f000000) >> 24; +- outp->location = (conn & 0x00300000) >> 20; +- outp->bus = (conn & 0x000f0000) >> 16; +- outp->connector = (conn & 0x0000f000) >> 12; +- outp->heads = (conn & 0x00000f00) >> 8; +- outp->i2c_index = (conn & 0x000000f0) >> 4; +- outp->type = (conn & 0x0000000f); +- outp->link = 0; +- } else { +- dcb = 0x0000; +- } +- +- if (*ver >= 0x40) { +- u32 conf = nv_ro32(bios, dcb + 0x04); +- switch (outp->type) { +- case DCB_OUTPUT_DP: +- switch (conf & 0x00e00000) { +- case 0x00000000: +- outp->dpconf.link_bw = 0x06; +- break; +- case 0x00200000: +- outp->dpconf.link_bw = 0x0a; +- break; +- case 0x00400000: +- default: +- outp->dpconf.link_bw = 0x14; +- break; +- } +- +- switch (conf & 0x0f000000) { +- case 0x0f000000: +- outp->dpconf.link_nr = 4; +- break; +- case 0x03000000: +- outp->dpconf.link_nr = 2; +- break; +- case 0x01000000: +- default: +- outp->dpconf.link_nr = 1; +- break; +- } +- +- /* fall-through... */ +- case DCB_OUTPUT_TMDS: +- case DCB_OUTPUT_LVDS: +- outp->link = (conf & 0x00000030) >> 4; +- outp->sorconf.link = outp->link; /*XXX*/ +- outp->extdev = 0x00; +- if (outp->location != 0) +- outp->extdev = (conf & 0x0000ff00) >> 8; +- break; +- default: +- break; +- } +- } +- +- outp->hasht = dcb_outp_hasht(outp); +- outp->hashm = dcb_outp_hashm(outp); +- } +- return dcb; +-} +- +-u16 +-dcb_outp_match(struct nouveau_bios *bios, u16 type, u16 mask, +- u8 *ver, u8 *len, struct dcb_output *outp) +-{ +- u16 dcb, idx = 0; +- while ((dcb = dcb_outp_parse(bios, idx++, ver, len, outp))) { +- if ((dcb_outp_hasht(outp) & 0x00ff) == (type & 0x00ff)) { +- if ((dcb_outp_hashm(outp) & mask) == mask) +- break; +- } +- } +- return dcb; +-} +- +-int +-dcb_outp_foreach(struct nouveau_bios *bios, void *data, +- int (*exec)(struct nouveau_bios *, void *, int, u16)) +-{ +- int ret, idx = -1; +- u8 ver, len; +- u16 outp; +- +- while ((outp = dcb_outp(bios, ++idx, &ver, &len))) { +- if (nv_ro32(bios, outp) == 0x00000000) +- break; /* seen on an NV11 with DCB v1.5 */ +- if (nv_ro32(bios, outp) == 0xffffffff) +- break; /* seen on an NV17 with DCB v2.0 */ +- +- if (nv_ro08(bios, outp) == DCB_OUTPUT_UNUSED) +- continue; +- if (nv_ro08(bios, outp) == DCB_OUTPUT_EOL) +- break; +- +- ret = exec(bios, data, idx, outp); +- if (ret) +- return ret; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c b/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c +deleted file mode 100644 +index 7f16e52d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/disp.c ++++ /dev/null +@@ -1,178 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_disp_table(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *sub) +-{ +- struct bit_entry U; +- +- if (!bit_entry(bios, 'U', &U)) { +- if (U.version == 1) { +- u16 data = nv_ro16(bios, U.offset); +- if (data) { +- *ver = nv_ro08(bios, data + 0x00); +- switch (*ver) { +- case 0x20: +- case 0x21: +- *hdr = nv_ro08(bios, data + 0x01); +- *len = nv_ro08(bios, data + 0x02); +- *cnt = nv_ro08(bios, data + 0x03); +- *sub = nv_ro08(bios, data + 0x04); +- return data; +- default: +- break; +- } +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_disp_entry(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *len, u8 *sub) +-{ +- u8 hdr, cnt; +- u16 data = nvbios_disp_table(bios, ver, &hdr, &cnt, len, sub); +- if (data && idx < cnt) +- return data + hdr + (idx * *len); +- *ver = 0x00; +- return 0x0000; +-} +- +-u16 +-nvbios_disp_parse(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *len, u8 *sub, +- struct nvbios_disp *info) +-{ +- u16 data = nvbios_disp_entry(bios, idx, ver, len, sub); +- if (data && *len >= 2) { +- info->data = nv_ro16(bios, data + 0); +- return data; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_outp_entry(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct nvbios_disp info; +- u16 data = nvbios_disp_parse(bios, idx, ver, len, hdr, &info); +- if (data) { +- *cnt = nv_ro08(bios, info.data + 0x05); +- *len = 0x06; +- data = info.data; +- } +- return data; +-} +- +-u16 +-nvbios_outp_parse(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_outp *info) +-{ +- u16 data = nvbios_outp_entry(bios, idx, ver, hdr, cnt, len); +- if (data && *hdr >= 0x0a) { +- info->type = nv_ro16(bios, data + 0x00); +- info->mask = nv_ro32(bios, data + 0x02); +- if (*ver <= 0x20) /* match any link */ +- info->mask |= 0x00c0; +- info->script[0] = nv_ro16(bios, data + 0x06); +- info->script[1] = nv_ro16(bios, data + 0x08); +- info->script[2] = 0x0000; +- if (*hdr >= 0x0c) +- info->script[2] = nv_ro16(bios, data + 0x0a); +- return data; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_outp_match(struct nouveau_bios *bios, u16 type, u16 mask, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_outp *info) +-{ +- u16 data, idx = 0; +- while ((data = nvbios_outp_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) { +- if (data && info->type == type) { +- if ((info->mask & mask) == mask) +- break; +- } +- } +- return data; +-} +- +-u16 +-nvbios_ocfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- if (idx < *cnt) +- return outp + *hdr + (idx * *len); +- return 0x0000; +-} +- +-u16 +-nvbios_ocfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ocfg *info) +-{ +- u16 data = nvbios_ocfg_entry(bios, outp, idx, ver, hdr, cnt, len); +- if (data) { +- info->match = nv_ro16(bios, data + 0x00); +- info->clkcmp[0] = nv_ro16(bios, data + 0x02); +- info->clkcmp[1] = nv_ro16(bios, data + 0x04); +- } +- return data; +-} +- +-u16 +-nvbios_ocfg_match(struct nouveau_bios *bios, u16 outp, u16 type, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ocfg *info) +-{ +- u16 data, idx = 0; +- while ((data = nvbios_ocfg_parse(bios, outp, idx++, ver, hdr, cnt, len, info))) { +- if (info->match == type) +- break; +- } +- return data; +-} +- +-u16 +-nvbios_oclk_match(struct nouveau_bios *bios, u16 cmp, u32 khz) +-{ +- while (cmp) { +- if (khz / 10 >= nv_ro16(bios, cmp + 0x00)) +- return nv_ro16(bios, cmp + 0x02); +- cmp += 0x04; +- } +- return 0x0000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c b/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c +deleted file mode 100644 +index f309dd65..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/dp.c ++++ /dev/null +@@ -1,209 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +- +-#include "subdev/bios.h" +-#include "subdev/bios/bit.h" +-#include "subdev/bios/dp.h" +- +-static u16 +-nvbios_dp_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct bit_entry d; +- +- if (!bit_entry(bios, 'd', &d)) { +- if (d.version == 1 && d.length >= 2) { +- u16 data = nv_ro16(bios, d.offset); +- if (data) { +- *ver = nv_ro08(bios, data + 0x00); +- switch (*ver) { +- case 0x21: +- case 0x30: +- case 0x40: +- *hdr = nv_ro08(bios, data + 0x01); +- *len = nv_ro08(bios, data + 0x02); +- *cnt = nv_ro08(bios, data + 0x03); +- return data; +- default: +- break; +- } +- } +- } +- } +- +- return 0x0000; +-} +- +-static u16 +-nvbios_dpout_entry(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u16 data = nvbios_dp_table(bios, ver, hdr, cnt, len); +- if (data && idx < *cnt) { +- u16 outp = nv_ro16(bios, data + *hdr + idx * *len); +- switch (*ver * !!outp) { +- case 0x21: +- case 0x30: +- *hdr = nv_ro08(bios, data + 0x04); +- *len = nv_ro08(bios, data + 0x05); +- *cnt = nv_ro08(bios, outp + 0x04); +- break; +- case 0x40: +- *hdr = nv_ro08(bios, data + 0x04); +- *cnt = 0; +- *len = 0; +- break; +- default: +- break; +- } +- return outp; +- } +- *ver = 0x00; +- return 0x0000; +-} +- +-u16 +-nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpout *info) +-{ +- u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- if (data && *ver) { +- info->type = nv_ro16(bios, data + 0x00); +- info->mask = nv_ro16(bios, data + 0x02); +- switch (*ver) { +- case 0x21: +- case 0x30: +- info->flags = nv_ro08(bios, data + 0x05); +- info->script[0] = nv_ro16(bios, data + 0x06); +- info->script[1] = nv_ro16(bios, data + 0x08); +- info->lnkcmp = nv_ro16(bios, data + 0x0a); +- if (*len >= 0x0f) { +- info->script[2] = nv_ro16(bios, data + 0x0c); +- info->script[3] = nv_ro16(bios, data + 0x0e); +- } +- if (*len >= 0x11) +- info->script[4] = nv_ro16(bios, data + 0x10); +- break; +- case 0x40: +- info->flags = nv_ro08(bios, data + 0x04); +- info->script[0] = nv_ro16(bios, data + 0x05); +- info->script[1] = nv_ro16(bios, data + 0x07); +- info->lnkcmp = nv_ro16(bios, data + 0x09); +- info->script[2] = nv_ro16(bios, data + 0x0b); +- info->script[3] = nv_ro16(bios, data + 0x0d); +- info->script[4] = nv_ro16(bios, data + 0x0f); +- break; +- default: +- data = 0x0000; +- break; +- } +- } +- return data; +-} +- +-u16 +-nvbios_dpout_match(struct nouveau_bios *bios, u16 type, u16 mask, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpout *info) +-{ +- u16 data, idx = 0; +- while ((data = nvbios_dpout_parse(bios, idx++, ver, hdr, cnt, len, info)) || *ver) { +- if (data && info->type == type) { +- if ((info->mask & mask) == mask) +- break; +- } +- } +- return data; +-} +- +-static u16 +-nvbios_dpcfg_entry(struct nouveau_bios *bios, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- if (*ver >= 0x40) { +- outp = nvbios_dp_table(bios, ver, hdr, cnt, len); +- *hdr = *hdr + (*len * * cnt); +- *len = nv_ro08(bios, outp + 0x06); +- *cnt = nv_ro08(bios, outp + 0x07); +- } +- +- if (idx < *cnt) +- return outp + *hdr + (idx * *len); +- +- return 0x0000; +-} +- +-u16 +-nvbios_dpcfg_parse(struct nouveau_bios *bios, u16 outp, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpcfg *info) +-{ +- u16 data = nvbios_dpcfg_entry(bios, outp, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- if (data) { +- switch (*ver) { +- case 0x21: +- info->dc = nv_ro08(bios, data + 0x02); +- info->pe = nv_ro08(bios, data + 0x03); +- info->tx_pu = nv_ro08(bios, data + 0x04); +- break; +- case 0x30: +- case 0x40: +- info->pc = nv_ro08(bios, data + 0x00); +- info->dc = nv_ro08(bios, data + 0x01); +- info->pe = nv_ro08(bios, data + 0x02); +- info->tx_pu = nv_ro08(bios, data + 0x03); +- break; +- default: +- data = 0x0000; +- break; +- } +- } +- return data; +-} +- +-u16 +-nvbios_dpcfg_match(struct nouveau_bios *bios, u16 outp, u8 pc, u8 vs, u8 pe, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_dpcfg *info) +-{ +- u8 idx = 0xff; +- u16 data; +- +- if (*ver >= 0x30) { +- const u8 vsoff[] = { 0, 4, 7, 9 }; +- idx = (pc * 10) + vsoff[vs] + pe; +- } else { +- while ((data = nvbios_dpcfg_entry(bios, outp, ++idx, +- ver, hdr, cnt, len))) { +- if (nv_ro08(bios, data + 0x00) == vs && +- nv_ro08(bios, data + 0x01) == pe) +- break; +- } +- } +- +- return nvbios_dpcfg_parse(bios, outp, idx, ver, hdr, cnt, len, info); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c +deleted file mode 100644 +index b2a676e5..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/extdev.c ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +-#include +- +-static u16 +-extdev_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) +-{ +- u8 dcb_ver, dcb_hdr, dcb_cnt, dcb_len; +- u16 dcb, extdev = 0; +- +- dcb = dcb_table(bios, &dcb_ver, &dcb_hdr, &dcb_cnt, &dcb_len); +- if (!dcb || (dcb_ver != 0x30 && dcb_ver != 0x40)) +- return 0x0000; +- +- extdev = nv_ro16(bios, dcb + 18); +- if (!extdev) +- return 0x0000; +- +- *ver = nv_ro08(bios, extdev + 0); +- *hdr = nv_ro08(bios, extdev + 1); +- *cnt = nv_ro08(bios, extdev + 2); +- *len = nv_ro08(bios, extdev + 3); +- +- return extdev + *hdr; +-} +- +-static u16 +-nvbios_extdev_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u16 extdev = extdev_table(bios, ver, &hdr, len, &cnt); +- if (extdev && idx < cnt) +- return extdev + idx * *len; +- return 0x0000; +-} +- +-static void +-extdev_parse_entry(struct nouveau_bios *bios, u16 offset, +- struct nvbios_extdev_func *entry) +-{ +- entry->type = nv_ro08(bios, offset + 0); +- entry->addr = nv_ro08(bios, offset + 1); +- entry->bus = (nv_ro08(bios, offset + 2) >> 4) & 1; +-} +- +-int +-nvbios_extdev_parse(struct nouveau_bios *bios, int idx, +- struct nvbios_extdev_func *func) +-{ +- u8 ver, len; +- u16 entry; +- +- if (!(entry = nvbios_extdev_entry(bios, idx, &ver, &len))) +- return -EINVAL; +- +- extdev_parse_entry(bios, entry, func); +- +- return 0; +-} +- +-int +-nvbios_extdev_find(struct nouveau_bios *bios, enum nvbios_extdev_type type, +- struct nvbios_extdev_func *func) +-{ +- u8 ver, len, i; +- u16 entry; +- +- i = 0; +- while (!(entry = nvbios_extdev_entry(bios, i++, &ver, &len))) { +- extdev_parse_entry(bios, entry, func); +- if (func->type == type) +- return 0; +- } +- +- return -EINVAL; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c b/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c +deleted file mode 100644 +index e4198922..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/fan.c ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_fan_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct bit_entry bit_P; +- u16 fan = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2 && bit_P.length >= 0x5a) +- fan = nv_ro16(bios, bit_P.offset + 0x58); +- +- if (fan) { +- *ver = nv_ro08(bios, fan + 0); +- switch (*ver) { +- case 0x10: +- *hdr = nv_ro08(bios, fan + 1); +- *len = nv_ro08(bios, fan + 2); +- *cnt = nv_ro08(bios, fan + 3); +- return fan; +- default: +- break; +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_fan_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr, +- u8 *cnt, u8 *len) +-{ +- u16 data = nvbios_fan_table(bios, ver, hdr, cnt, len); +- if (data && idx < *cnt) +- return data + *hdr + (idx * (*len)); +- return 0x0000; +-} +- +-u16 +-nvbios_fan_parse(struct nouveau_bios *bios, struct nvbios_therm_fan *fan) +-{ +- u8 ver, hdr, cnt, len; +- +- u16 data = nvbios_fan_entry(bios, 0, &ver, &hdr, &cnt, &len); +- if (data) { +- u8 type = nv_ro08(bios, data + 0x00); +- switch (type) { +- case 0: +- fan->type = NVBIOS_THERM_FAN_TOGGLE; +- break; +- case 1: +- case 2: +- /* TODO: Understand the difference between the two! */ +- fan->type = NVBIOS_THERM_FAN_PWM; +- break; +- default: +- fan->type = NVBIOS_THERM_FAN_UNK; +- } +- +- fan->min_duty = nv_ro08(bios, data + 0x02); +- fan->max_duty = nv_ro08(bios, data + 0x03); +- +- fan->pwm_freq = nv_ro32(bios, data + 0x0b) & 0xffffff; +- } +- return data; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c b/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c +deleted file mode 100644 +index 172a4f99..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/gpio.c ++++ /dev/null +@@ -1,150 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-u16 +-dcb_gpio_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u16 data = 0x0000; +- u16 dcb = dcb_table(bios, ver, hdr, cnt, len); +- if (dcb) { +- if (*ver >= 0x30 && *hdr >= 0x0c) +- data = nv_ro16(bios, dcb + 0x0a); +- else +- if (*ver >= 0x22 && nv_ro08(bios, dcb - 1) >= 0x13) +- data = nv_ro16(bios, dcb - 0x0f); +- +- if (data) { +- *ver = nv_ro08(bios, data + 0x00); +- if (*ver < 0x30) { +- *hdr = 3; +- *cnt = nv_ro08(bios, data + 0x02); +- *len = nv_ro08(bios, data + 0x01); +- } else +- if (*ver <= 0x41) { +- *hdr = nv_ro08(bios, data + 0x01); +- *cnt = nv_ro08(bios, data + 0x02); +- *len = nv_ro08(bios, data + 0x03); +- } else { +- data = 0x0000; +- } +- } +- } +- return data; +-} +- +-u16 +-dcb_gpio_entry(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt, xver; /* use gpio version for xpio entry parsing */ +- u16 gpio; +- +- if (!idx--) +- gpio = dcb_gpio_table(bios, ver, &hdr, &cnt, len); +- else +- gpio = dcb_xpio_table(bios, idx, &xver, &hdr, &cnt, len); +- +- if (gpio && ent < cnt) +- return gpio + hdr + (ent * *len); +- return 0x0000; +-} +- +-u16 +-dcb_gpio_parse(struct nouveau_bios *bios, int idx, int ent, u8 *ver, u8 *len, +- struct dcb_gpio_func *gpio) +-{ +- u16 data = dcb_gpio_entry(bios, idx, ent, ver, len); +- if (data) { +- if (*ver < 0x40) { +- u16 info = nv_ro16(bios, data); +- *gpio = (struct dcb_gpio_func) { +- .line = (info & 0x001f) >> 0, +- .func = (info & 0x07e0) >> 5, +- .log[0] = (info & 0x1800) >> 11, +- .log[1] = (info & 0x6000) >> 13, +- .param = !!(info & 0x8000), +- }; +- } else +- if (*ver < 0x41) { +- u32 info = nv_ro32(bios, data); +- *gpio = (struct dcb_gpio_func) { +- .line = (info & 0x0000001f) >> 0, +- .func = (info & 0x0000ff00) >> 8, +- .log[0] = (info & 0x18000000) >> 27, +- .log[1] = (info & 0x60000000) >> 29, +- .param = !!(info & 0x80000000), +- }; +- } else { +- u32 info = nv_ro32(bios, data + 0); +- u8 info1 = nv_ro32(bios, data + 4); +- *gpio = (struct dcb_gpio_func) { +- .line = (info & 0x0000003f) >> 0, +- .func = (info & 0x0000ff00) >> 8, +- .log[0] = (info1 & 0x30) >> 4, +- .log[1] = (info1 & 0xc0) >> 6, +- .param = !!(info & 0x80000000), +- }; +- } +- } +- +- return data; +-} +- +-u16 +-dcb_gpio_match(struct nouveau_bios *bios, int idx, u8 func, u8 line, +- u8 *ver, u8 *len, struct dcb_gpio_func *gpio) +-{ +- u8 hdr, cnt, i = 0; +- u16 data; +- +- while ((data = dcb_gpio_parse(bios, idx, i++, ver, len, gpio))) { +- if ((line == 0xff || line == gpio->line) && +- (func == 0xff || func == gpio->func)) +- return data; +- } +- +- /* DCB 2.2, fixed TVDAC GPIO data */ +- if ((data = dcb_table(bios, ver, &hdr, &cnt, len))) { +- if (*ver >= 0x22 && *ver < 0x30 && func == DCB_GPIO_TVDAC0) { +- u8 conf = nv_ro08(bios, data - 5); +- u8 addr = nv_ro08(bios, data - 4); +- if (conf & 0x01) { +- *gpio = (struct dcb_gpio_func) { +- .func = DCB_GPIO_TVDAC0, +- .line = addr >> 4, +- .log[0] = !!(conf & 0x02), +- .log[1] = !(conf & 0x02), +- }; +- *ver = 0x00; +- return data; +- } +- } +- } +- +- return 0x0000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c b/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c +deleted file mode 100644 +index cfb9288c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/i2c.c ++++ /dev/null +@@ -1,134 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +- +-#include "subdev/bios.h" +-#include "subdev/bios/dcb.h" +-#include "subdev/bios/i2c.h" +- +-u16 +-dcb_i2c_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u16 i2c = 0x0000; +- u16 dcb = dcb_table(bios, ver, hdr, cnt, len); +- if (dcb) { +- if (*ver >= 0x15) +- i2c = nv_ro16(bios, dcb + 2); +- if (*ver >= 0x30) +- i2c = nv_ro16(bios, dcb + 4); +- } +- +- if (i2c && *ver >= 0x30) { +- *ver = nv_ro08(bios, i2c + 0); +- *hdr = nv_ro08(bios, i2c + 1); +- *cnt = nv_ro08(bios, i2c + 2); +- *len = nv_ro08(bios, i2c + 3); +- } else { +- *ver = *ver; /* use DCB version */ +- *hdr = 0; +- *cnt = 16; +- *len = 4; +- } +- +- return i2c; +-} +- +-u16 +-dcb_i2c_entry(struct nouveau_bios *bios, u8 idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u16 i2c = dcb_i2c_table(bios, ver, &hdr, &cnt, len); +- if (i2c && idx < cnt) +- return i2c + hdr + (idx * *len); +- return 0x0000; +-} +- +-int +-dcb_i2c_parse(struct nouveau_bios *bios, u8 idx, struct dcb_i2c_entry *info) +-{ +- u8 ver, len; +- u16 ent = dcb_i2c_entry(bios, idx, &ver, &len); +- if (ent) { +- info->type = nv_ro08(bios, ent + 3); +- info->share = DCB_I2C_UNUSED; +- if (ver < 0x30) { +- info->type &= 0x07; +- if (info->type == 0x07) +- info->type = DCB_I2C_UNUSED; +- } +- +- switch (info->type) { +- case DCB_I2C_NV04_BIT: +- info->drive = nv_ro08(bios, ent + 0); +- info->sense = nv_ro08(bios, ent + 1); +- return 0; +- case DCB_I2C_NV4E_BIT: +- info->drive = nv_ro08(bios, ent + 1); +- return 0; +- case DCB_I2C_NVIO_BIT: +- case DCB_I2C_NVIO_AUX: +- info->drive = nv_ro08(bios, ent + 0) & 0x0f; +- if (nv_ro08(bios, ent + 1) & 0x01) { +- info->share = nv_ro08(bios, ent + 1) >> 1; +- info->share &= 0x0f; +- } +- return 0; +- case DCB_I2C_UNUSED: +- return 0; +- default: +- nv_warn(bios, "unknown i2c type %d\n", info->type); +- info->type = DCB_I2C_UNUSED; +- return 0; +- } +- } +- +- if (bios->bmp_offset && idx < 2) { +- /* BMP (from v4.0 has i2c info in the structure, it's in a +- * fixed location on earlier VBIOS +- */ +- if (nv_ro08(bios, bios->bmp_offset + 5) < 4) +- ent = 0x0048; +- else +- ent = 0x0036 + bios->bmp_offset; +- +- if (idx == 0) { +- info->drive = nv_ro08(bios, ent + 4); +- if (!info->drive) info->drive = 0x3f; +- info->sense = nv_ro08(bios, ent + 5); +- if (!info->sense) info->sense = 0x3e; +- } else +- if (idx == 1) { +- info->drive = nv_ro08(bios, ent + 6); +- if (!info->drive) info->drive = 0x37; +- info->sense = nv_ro08(bios, ent + 7); +- if (!info->sense) info->sense = 0x36; +- } +- +- info->type = DCB_I2C_NV04_BIT; +- info->share = DCB_I2C_UNUSED; +- return 0; +- } +- +- return -ENOENT; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c b/drivers/gpu/drm/nouveau/core/subdev/bios/init.c +deleted file mode 100644 +index 626380f9..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/init.c ++++ /dev/null +@@ -1,2185 +0,0 @@ +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define bioslog(lvl, fmt, args...) do { \ +- nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \ +- init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \ +-} while(0) +-#define cont(fmt, args...) do { \ +- if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \ +- printk(fmt, ##args); \ +-} while(0) +-#define trace(fmt, args...) bioslog(TRACE, fmt, ##args) +-#define warn(fmt, args...) bioslog(WARN, fmt, ##args) +-#define error(fmt, args...) bioslog(ERROR, fmt, ##args) +- +-/****************************************************************************** +- * init parser control flow helpers +- *****************************************************************************/ +- +-static inline bool +-init_exec(struct nvbios_init *init) +-{ +- return (init->execute == 1) || ((init->execute & 5) == 5); +-} +- +-static inline void +-init_exec_set(struct nvbios_init *init, bool exec) +-{ +- if (exec) init->execute &= 0xfd; +- else init->execute |= 0x02; +-} +- +-static inline void +-init_exec_inv(struct nvbios_init *init) +-{ +- init->execute ^= 0x02; +-} +- +-static inline void +-init_exec_force(struct nvbios_init *init, bool exec) +-{ +- if (exec) init->execute |= 0x04; +- else init->execute &= 0xfb; +-} +- +-/****************************************************************************** +- * init parser wrappers for normal register/i2c/whatever accessors +- *****************************************************************************/ +- +-static inline int +-init_or(struct nvbios_init *init) +-{ +- if (init_exec(init)) { +- if (init->outp) +- return ffs(init->outp->or) - 1; +- error("script needs OR!!\n"); +- } +- return 0; +-} +- +-static inline int +-init_link(struct nvbios_init *init) +-{ +- if (init_exec(init)) { +- if (init->outp) +- return !(init->outp->sorconf.link & 1); +- error("script needs OR link\n"); +- } +- return 0; +-} +- +-static inline int +-init_crtc(struct nvbios_init *init) +-{ +- if (init_exec(init)) { +- if (init->crtc >= 0) +- return init->crtc; +- error("script needs crtc\n"); +- } +- return 0; +-} +- +-static u8 +-init_conn(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- struct nvbios_connE connE; +- u8 ver, hdr; +- u32 conn; +- +- if (init_exec(init)) { +- if (init->outp) { +- conn = init->outp->connector; +- conn = nvbios_connEp(bios, conn, &ver, &hdr, &connE); +- if (conn) +- return connE.type; +- } +- +- error("script needs connector type\n"); +- } +- +- return 0xff; +-} +- +-static inline u32 +-init_nvreg(struct nvbios_init *init, u32 reg) +-{ +- struct nouveau_devinit *devinit = nouveau_devinit(init->bios); +- +- /* C51 (at least) sometimes has the lower bits set which the VBIOS +- * interprets to mean that access needs to go through certain IO +- * ports instead. The NVIDIA binary driver has been seen to access +- * these through the NV register address, so lets assume we can +- * do the same +- */ +- reg &= ~0x00000003; +- +- /* GF8+ display scripts need register addresses mangled a bit to +- * select a specific CRTC/OR +- */ +- if (nv_device(init->bios)->card_type >= NV_50) { +- if (reg & 0x80000000) { +- reg += init_crtc(init) * 0x800; +- reg &= ~0x80000000; +- } +- +- if (reg & 0x40000000) { +- reg += init_or(init) * 0x800; +- reg &= ~0x40000000; +- if (reg & 0x20000000) { +- reg += init_link(init) * 0x80; +- reg &= ~0x20000000; +- } +- } +- } +- +- if (reg & ~0x00fffffc) +- warn("unknown bits in register 0x%08x\n", reg); +- +- if (devinit->mmio) +- reg = devinit->mmio(devinit, reg); +- return reg; +-} +- +-static u32 +-init_rd32(struct nvbios_init *init, u32 reg) +-{ +- reg = init_nvreg(init, reg); +- if (reg != ~0 && init_exec(init)) +- return nv_rd32(init->subdev, reg); +- return 0x00000000; +-} +- +-static void +-init_wr32(struct nvbios_init *init, u32 reg, u32 val) +-{ +- reg = init_nvreg(init, reg); +- if (reg != ~0 && init_exec(init)) +- nv_wr32(init->subdev, reg, val); +-} +- +-static u32 +-init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val) +-{ +- reg = init_nvreg(init, reg); +- if (reg != ~0 && init_exec(init)) { +- u32 tmp = nv_rd32(init->subdev, reg); +- nv_wr32(init->subdev, reg, (tmp & ~mask) | val); +- return tmp; +- } +- return 0x00000000; +-} +- +-static u8 +-init_rdport(struct nvbios_init *init, u16 port) +-{ +- if (init_exec(init)) +- return nv_rdport(init->subdev, init->crtc, port); +- return 0x00; +-} +- +-static void +-init_wrport(struct nvbios_init *init, u16 port, u8 value) +-{ +- if (init_exec(init)) +- nv_wrport(init->subdev, init->crtc, port, value); +-} +- +-static u8 +-init_rdvgai(struct nvbios_init *init, u16 port, u8 index) +-{ +- struct nouveau_subdev *subdev = init->subdev; +- if (init_exec(init)) { +- int head = init->crtc < 0 ? 0 : init->crtc; +- return nv_rdvgai(subdev, head, port, index); +- } +- return 0x00; +-} +- +-static void +-init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value) +-{ +- /* force head 0 for updates to cr44, it only exists on first head */ +- if (nv_device(init->subdev)->card_type < NV_50) { +- if (port == 0x03d4 && index == 0x44) +- init->crtc = 0; +- } +- +- if (init_exec(init)) { +- int head = init->crtc < 0 ? 0 : init->crtc; +- nv_wrvgai(init->subdev, head, port, index, value); +- } +- +- /* select head 1 if cr44 write selected it */ +- if (nv_device(init->subdev)->card_type < NV_50) { +- if (port == 0x03d4 && index == 0x44 && value == 3) +- init->crtc = 1; +- } +-} +- +-static struct nouveau_i2c_port * +-init_i2c(struct nvbios_init *init, int index) +-{ +- struct nouveau_i2c *i2c = nouveau_i2c(init->bios); +- +- if (index == 0xff) { +- index = NV_I2C_DEFAULT(0); +- if (init->outp && init->outp->i2c_upper_default) +- index = NV_I2C_DEFAULT(1); +- } else +- if (index < 0) { +- if (!init->outp) { +- if (init_exec(init)) +- error("script needs output for i2c\n"); +- return NULL; +- } +- +- if (index == -2 && init->outp->location) { +- index = NV_I2C_TYPE_EXTAUX(init->outp->extdev); +- return i2c->find_type(i2c, index); +- } +- +- index = init->outp->i2c_index; +- } +- +- return i2c->find(i2c, index); +-} +- +-static int +-init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg) +-{ +- struct nouveau_i2c_port *port = init_i2c(init, index); +- if (port && init_exec(init)) +- return nv_rdi2cr(port, addr, reg); +- return -ENODEV; +-} +- +-static int +-init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val) +-{ +- struct nouveau_i2c_port *port = init_i2c(init, index); +- if (port && init_exec(init)) +- return nv_wri2cr(port, addr, reg, val); +- return -ENODEV; +-} +- +-static int +-init_rdauxr(struct nvbios_init *init, u32 addr) +-{ +- struct nouveau_i2c_port *port = init_i2c(init, -2); +- u8 data; +- +- if (port && init_exec(init)) { +- int ret = nv_rdaux(port, addr, &data, 1); +- if (ret) +- return ret; +- return data; +- } +- +- return -ENODEV; +-} +- +-static int +-init_wrauxr(struct nvbios_init *init, u32 addr, u8 data) +-{ +- struct nouveau_i2c_port *port = init_i2c(init, -2); +- if (port && init_exec(init)) +- return nv_wraux(port, addr, &data, 1); +- return -ENODEV; +-} +- +-static void +-init_prog_pll(struct nvbios_init *init, u32 id, u32 freq) +-{ +- struct nouveau_devinit *devinit = nouveau_devinit(init->bios); +- if (devinit->pll_set && init_exec(init)) { +- int ret = devinit->pll_set(devinit, id, freq); +- if (ret) +- warn("failed to prog pll 0x%08x to %dkHz\n", id, freq); +- } +-} +- +-/****************************************************************************** +- * parsing of bios structures that are required to execute init tables +- *****************************************************************************/ +- +-static u16 +-init_table(struct nouveau_bios *bios, u16 *len) +-{ +- struct bit_entry bit_I; +- +- if (!bit_entry(bios, 'I', &bit_I)) { +- *len = bit_I.length; +- return bit_I.offset; +- } +- +- if (bmp_version(bios) >= 0x0510) { +- *len = 14; +- return bios->bmp_offset + 75; +- } +- +- return 0x0000; +-} +- +-static u16 +-init_table_(struct nvbios_init *init, u16 offset, const char *name) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 len, data = init_table(bios, &len); +- if (data) { +- if (len >= offset + 2) { +- data = nv_ro16(bios, data + offset); +- if (data) +- return data; +- +- warn("%s pointer invalid\n", name); +- return 0x0000; +- } +- +- warn("init data too short for %s pointer", name); +- return 0x0000; +- } +- +- warn("init data not found\n"); +- return 0x0000; +-} +- +-#define init_script_table(b) init_table_((b), 0x00, "script table") +-#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table") +-#define init_macro_table(b) init_table_((b), 0x04, "macro table") +-#define init_condition_table(b) init_table_((b), 0x06, "condition table") +-#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table") +-#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table") +-#define init_function_table(b) init_table_((b), 0x0c, "function table") +-#define init_xlat_table(b) init_table_((b), 0x10, "xlat table"); +- +-static u16 +-init_script(struct nouveau_bios *bios, int index) +-{ +- struct nvbios_init init = { .bios = bios }; +- u16 bmp_ver = bmp_version(bios), data; +- +- if (bmp_ver && bmp_ver < 0x0510) { +- if (index > 1 || bmp_ver < 0x0100) +- return 0x0000; +- +- data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18); +- return nv_ro16(bios, data + (index * 2)); +- } +- +- data = init_script_table(&init); +- if (data) +- return nv_ro16(bios, data + (index * 2)); +- +- return 0x0000; +-} +- +-static u16 +-init_unknown_script(struct nouveau_bios *bios) +-{ +- u16 len, data = init_table(bios, &len); +- if (data && len >= 16) +- return nv_ro16(bios, data + 14); +- return 0x0000; +-} +- +-static u8 +-init_ram_restrict_group_count(struct nvbios_init *init) +-{ +- return nvbios_ramcfg_count(init->bios); +-} +- +-static u8 +-init_ram_restrict(struct nvbios_init *init) +-{ +- /* This appears to be the behaviour of the VBIOS parser, and *is* +- * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to +- * avoid fucking up the memory controller (somehow) by reading it +- * on every INIT_RAM_RESTRICT_ZM_GROUP opcode. +- * +- * Preserving the non-caching behaviour on earlier chipsets just +- * in case *not* re-reading the strap causes similar breakage. +- */ +- if (!init->ramcfg || init->bios->version.major < 0x70) +- init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev); +- return (init->ramcfg & 0x7fffffff); +-} +- +-static u8 +-init_xlat_(struct nvbios_init *init, u8 index, u8 offset) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 table = init_xlat_table(init); +- if (table) { +- u16 data = nv_ro16(bios, table + (index * 2)); +- if (data) +- return nv_ro08(bios, data + offset); +- warn("xlat table pointer %d invalid\n", index); +- } +- return 0x00; +-} +- +-/****************************************************************************** +- * utility functions used by various init opcode handlers +- *****************************************************************************/ +- +-static bool +-init_condition_met(struct nvbios_init *init, u8 cond) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 table = init_condition_table(init); +- if (table) { +- u32 reg = nv_ro32(bios, table + (cond * 12) + 0); +- u32 msk = nv_ro32(bios, table + (cond * 12) + 4); +- u32 val = nv_ro32(bios, table + (cond * 12) + 8); +- trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n", +- cond, reg, msk, val); +- return (init_rd32(init, reg) & msk) == val; +- } +- return false; +-} +- +-static bool +-init_io_condition_met(struct nvbios_init *init, u8 cond) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 table = init_io_condition_table(init); +- if (table) { +- u16 port = nv_ro16(bios, table + (cond * 5) + 0); +- u8 index = nv_ro08(bios, table + (cond * 5) + 2); +- u8 mask = nv_ro08(bios, table + (cond * 5) + 3); +- u8 value = nv_ro08(bios, table + (cond * 5) + 4); +- trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n", +- cond, port, index, mask, value); +- return (init_rdvgai(init, port, index) & mask) == value; +- } +- return false; +-} +- +-static bool +-init_io_flag_condition_met(struct nvbios_init *init, u8 cond) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 table = init_io_flag_condition_table(init); +- if (table) { +- u16 port = nv_ro16(bios, table + (cond * 9) + 0); +- u8 index = nv_ro08(bios, table + (cond * 9) + 2); +- u8 mask = nv_ro08(bios, table + (cond * 9) + 3); +- u8 shift = nv_ro08(bios, table + (cond * 9) + 4); +- u16 data = nv_ro16(bios, table + (cond * 9) + 5); +- u8 dmask = nv_ro08(bios, table + (cond * 9) + 7); +- u8 value = nv_ro08(bios, table + (cond * 9) + 8); +- u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift; +- return (nv_ro08(bios, data + ioval) & dmask) == value; +- } +- return false; +-} +- +-static inline u32 +-init_shift(u32 data, u8 shift) +-{ +- if (shift < 0x80) +- return data >> shift; +- return data << (0x100 - shift); +-} +- +-static u32 +-init_tmds_reg(struct nvbios_init *init, u8 tmds) +-{ +- /* For mlv < 0x80, it is an index into a table of TMDS base addresses. +- * For mlv == 0x80 use the "or" value of the dcb_entry indexed by +- * CR58 for CR57 = 0 to index a table of offsets to the basic +- * 0x6808b0 address. +- * For mlv == 0x81 use the "or" value of the dcb_entry indexed by +- * CR58 for CR57 = 0 to index a table of offsets to the basic +- * 0x6808b0 address, and then flip the offset by 8. +- */ +- +- const int pramdac_offset[13] = { +- 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 }; +- const u32 pramdac_table[4] = { +- 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 }; +- +- if (tmds >= 0x80) { +- if (init->outp) { +- u32 dacoffset = pramdac_offset[init->outp->or]; +- if (tmds == 0x81) +- dacoffset ^= 8; +- return 0x6808b0 + dacoffset; +- } +- +- if (init_exec(init)) +- error("tmds opcodes need dcb\n"); +- } else { +- if (tmds < ARRAY_SIZE(pramdac_table)) +- return pramdac_table[tmds]; +- +- error("tmds selector 0x%02x unknown\n", tmds); +- } +- +- return 0; +-} +- +-/****************************************************************************** +- * init opcode handlers +- *****************************************************************************/ +- +-/** +- * init_reserved - stub for various unknown/unused single-byte opcodes +- * +- */ +-static void +-init_reserved(struct nvbios_init *init) +-{ +- u8 opcode = nv_ro08(init->bios, init->offset); +- u8 length, i; +- +- switch (opcode) { +- case 0xaa: +- length = 4; +- break; +- default: +- length = 1; +- break; +- } +- +- trace("RESERVED 0x%02x\t", opcode); +- for (i = 1; i < length; i++) +- cont(" 0x%02x", nv_ro08(init->bios, init->offset + i)); +- cont("\n"); +- init->offset += length; +-} +- +-/** +- * INIT_DONE - opcode 0x71 +- * +- */ +-static void +-init_done(struct nvbios_init *init) +-{ +- trace("DONE\n"); +- init->offset = 0x0000; +-} +- +-/** +- * INIT_IO_RESTRICT_PROG - opcode 0x32 +- * +- */ +-static void +-init_io_restrict_prog(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 port = nv_ro16(bios, init->offset + 1); +- u8 index = nv_ro08(bios, init->offset + 3); +- u8 mask = nv_ro08(bios, init->offset + 4); +- u8 shift = nv_ro08(bios, init->offset + 5); +- u8 count = nv_ro08(bios, init->offset + 6); +- u32 reg = nv_ro32(bios, init->offset + 7); +- u8 conf, i; +- +- trace("IO_RESTRICT_PROG\tR[0x%06x] = " +- "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n", +- reg, port, index, mask, shift); +- init->offset += 11; +- +- conf = (init_rdvgai(init, port, index) & mask) >> shift; +- for (i = 0; i < count; i++) { +- u32 data = nv_ro32(bios, init->offset); +- +- if (i == conf) { +- trace("\t0x%08x *\n", data); +- init_wr32(init, reg, data); +- } else { +- trace("\t0x%08x\n", data); +- } +- +- init->offset += 4; +- } +- trace("}]\n"); +-} +- +-/** +- * INIT_REPEAT - opcode 0x33 +- * +- */ +-static void +-init_repeat(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 count = nv_ro08(bios, init->offset + 1); +- u16 repeat = init->repeat; +- +- trace("REPEAT\t0x%02x\n", count); +- init->offset += 2; +- +- init->repeat = init->offset; +- init->repend = init->offset; +- while (count--) { +- init->offset = init->repeat; +- nvbios_exec(init); +- if (count) +- trace("REPEAT\t0x%02x\n", count); +- } +- init->offset = init->repend; +- init->repeat = repeat; +-} +- +-/** +- * INIT_IO_RESTRICT_PLL - opcode 0x34 +- * +- */ +-static void +-init_io_restrict_pll(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 port = nv_ro16(bios, init->offset + 1); +- u8 index = nv_ro08(bios, init->offset + 3); +- u8 mask = nv_ro08(bios, init->offset + 4); +- u8 shift = nv_ro08(bios, init->offset + 5); +- s8 iofc = nv_ro08(bios, init->offset + 6); +- u8 count = nv_ro08(bios, init->offset + 7); +- u32 reg = nv_ro32(bios, init->offset + 8); +- u8 conf, i; +- +- trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= " +- "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n", +- reg, port, index, mask, shift, iofc); +- init->offset += 12; +- +- conf = (init_rdvgai(init, port, index) & mask) >> shift; +- for (i = 0; i < count; i++) { +- u32 freq = nv_ro16(bios, init->offset) * 10; +- +- if (i == conf) { +- trace("\t%dkHz *\n", freq); +- if (iofc > 0 && init_io_flag_condition_met(init, iofc)) +- freq *= 2; +- init_prog_pll(init, reg, freq); +- } else { +- trace("\t%dkHz\n", freq); +- } +- +- init->offset += 2; +- } +- trace("}]\n"); +-} +- +-/** +- * INIT_END_REPEAT - opcode 0x36 +- * +- */ +-static void +-init_end_repeat(struct nvbios_init *init) +-{ +- trace("END_REPEAT\n"); +- init->offset += 1; +- +- if (init->repeat) { +- init->repend = init->offset; +- init->offset = 0; +- } +-} +- +-/** +- * INIT_COPY - opcode 0x37 +- * +- */ +-static void +-init_copy(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 reg = nv_ro32(bios, init->offset + 1); +- u8 shift = nv_ro08(bios, init->offset + 5); +- u8 smask = nv_ro08(bios, init->offset + 6); +- u16 port = nv_ro16(bios, init->offset + 7); +- u8 index = nv_ro08(bios, init->offset + 9); +- u8 mask = nv_ro08(bios, init->offset + 10); +- u8 data; +- +- trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= " +- "((R[0x%06x] %s 0x%02x) & 0x%02x)\n", +- port, index, mask, reg, (shift & 0x80) ? "<<" : ">>", +- (shift & 0x80) ? (0x100 - shift) : shift, smask); +- init->offset += 11; +- +- data = init_rdvgai(init, port, index) & mask; +- data |= init_shift(init_rd32(init, reg), shift) & smask; +- init_wrvgai(init, port, index, data); +-} +- +-/** +- * INIT_NOT - opcode 0x38 +- * +- */ +-static void +-init_not(struct nvbios_init *init) +-{ +- trace("NOT\n"); +- init->offset += 1; +- init_exec_inv(init); +-} +- +-/** +- * INIT_IO_FLAG_CONDITION - opcode 0x39 +- * +- */ +-static void +-init_io_flag_condition(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 cond = nv_ro08(bios, init->offset + 1); +- +- trace("IO_FLAG_CONDITION\t0x%02x\n", cond); +- init->offset += 2; +- +- if (!init_io_flag_condition_met(init, cond)) +- init_exec_set(init, false); +-} +- +-/** +- * INIT_DP_CONDITION - opcode 0x3a +- * +- */ +-static void +-init_dp_condition(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- struct nvbios_dpout info; +- u8 cond = nv_ro08(bios, init->offset + 1); +- u8 unkn = nv_ro08(bios, init->offset + 2); +- u8 ver, hdr, cnt, len; +- u16 data; +- +- trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn); +- init->offset += 3; +- +- switch (cond) { +- case 0: +- if (init_conn(init) != DCB_CONNECTOR_eDP) +- init_exec_set(init, false); +- break; +- case 1: +- case 2: +- if ( init->outp && +- (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP, +- (init->outp->or << 0) | +- (init->outp->sorconf.link << 6), +- &ver, &hdr, &cnt, &len, &info))) +- { +- if (!(info.flags & cond)) +- init_exec_set(init, false); +- break; +- } +- +- if (init_exec(init)) +- warn("script needs dp output table data\n"); +- break; +- case 5: +- if (!(init_rdauxr(init, 0x0d) & 1)) +- init_exec_set(init, false); +- break; +- default: +- warn("unknown dp condition 0x%02x\n", cond); +- break; +- } +-} +- +-/** +- * INIT_IO_MASK_OR - opcode 0x3b +- * +- */ +-static void +-init_io_mask_or(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 or = init_or(init); +- u8 data; +- +- trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or); +- init->offset += 2; +- +- data = init_rdvgai(init, 0x03d4, index); +- init_wrvgai(init, 0x03d4, index, data &= ~(1 << or)); +-} +- +-/** +- * INIT_IO_OR - opcode 0x3c +- * +- */ +-static void +-init_io_or(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 or = init_or(init); +- u8 data; +- +- trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or); +- init->offset += 2; +- +- data = init_rdvgai(init, 0x03d4, index); +- init_wrvgai(init, 0x03d4, index, data | (1 << or)); +-} +- +-/** +- * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49 +- * +- */ +-static void +-init_idx_addr_latched(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 creg = nv_ro32(bios, init->offset + 1); +- u32 dreg = nv_ro32(bios, init->offset + 5); +- u32 mask = nv_ro32(bios, init->offset + 9); +- u32 data = nv_ro32(bios, init->offset + 13); +- u8 count = nv_ro08(bios, init->offset + 17); +- +- trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg); +- trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data); +- init->offset += 18; +- +- while (count--) { +- u8 iaddr = nv_ro08(bios, init->offset + 0); +- u8 idata = nv_ro08(bios, init->offset + 1); +- +- trace("\t[0x%02x] = 0x%02x\n", iaddr, idata); +- init->offset += 2; +- +- init_wr32(init, dreg, idata); +- init_mask(init, creg, ~mask, data | iaddr); +- } +-} +- +-/** +- * INIT_IO_RESTRICT_PLL2 - opcode 0x4a +- * +- */ +-static void +-init_io_restrict_pll2(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 port = nv_ro16(bios, init->offset + 1); +- u8 index = nv_ro08(bios, init->offset + 3); +- u8 mask = nv_ro08(bios, init->offset + 4); +- u8 shift = nv_ro08(bios, init->offset + 5); +- u8 count = nv_ro08(bios, init->offset + 6); +- u32 reg = nv_ro32(bios, init->offset + 7); +- u8 conf, i; +- +- trace("IO_RESTRICT_PLL2\t" +- "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n", +- reg, port, index, mask, shift); +- init->offset += 11; +- +- conf = (init_rdvgai(init, port, index) & mask) >> shift; +- for (i = 0; i < count; i++) { +- u32 freq = nv_ro32(bios, init->offset); +- if (i == conf) { +- trace("\t%dkHz *\n", freq); +- init_prog_pll(init, reg, freq); +- } else { +- trace("\t%dkHz\n", freq); +- } +- init->offset += 4; +- } +- trace("}]\n"); +-} +- +-/** +- * INIT_PLL2 - opcode 0x4b +- * +- */ +-static void +-init_pll2(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 reg = nv_ro32(bios, init->offset + 1); +- u32 freq = nv_ro32(bios, init->offset + 5); +- +- trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq); +- init->offset += 9; +- +- init_prog_pll(init, reg, freq); +-} +- +-/** +- * INIT_I2C_BYTE - opcode 0x4c +- * +- */ +-static void +-init_i2c_byte(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 addr = nv_ro08(bios, init->offset + 2) >> 1; +- u8 count = nv_ro08(bios, init->offset + 3); +- +- trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); +- init->offset += 4; +- +- while (count--) { +- u8 reg = nv_ro08(bios, init->offset + 0); +- u8 mask = nv_ro08(bios, init->offset + 1); +- u8 data = nv_ro08(bios, init->offset + 2); +- int val; +- +- trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data); +- init->offset += 3; +- +- val = init_rdi2cr(init, index, addr, reg); +- if (val < 0) +- continue; +- init_wri2cr(init, index, addr, reg, (val & mask) | data); +- } +-} +- +-/** +- * INIT_ZM_I2C_BYTE - opcode 0x4d +- * +- */ +-static void +-init_zm_i2c_byte(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 addr = nv_ro08(bios, init->offset + 2) >> 1; +- u8 count = nv_ro08(bios, init->offset + 3); +- +- trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr); +- init->offset += 4; +- +- while (count--) { +- u8 reg = nv_ro08(bios, init->offset + 0); +- u8 data = nv_ro08(bios, init->offset + 1); +- +- trace("\t[0x%02x] = 0x%02x\n", reg, data); +- init->offset += 2; +- +- init_wri2cr(init, index, addr, reg, data); +- } +- +-} +- +-/** +- * INIT_ZM_I2C - opcode 0x4e +- * +- */ +-static void +-init_zm_i2c(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 addr = nv_ro08(bios, init->offset + 2) >> 1; +- u8 count = nv_ro08(bios, init->offset + 3); +- u8 data[256], i; +- +- trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr); +- init->offset += 4; +- +- for (i = 0; i < count; i++) { +- data[i] = nv_ro08(bios, init->offset); +- trace("\t0x%02x\n", data[i]); +- init->offset++; +- } +- +- if (init_exec(init)) { +- struct nouveau_i2c_port *port = init_i2c(init, index); +- struct i2c_msg msg = { +- .addr = addr, .flags = 0, .len = count, .buf = data, +- }; +- int ret; +- +- if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1) +- warn("i2c wr failed, %d\n", ret); +- } +-} +- +-/** +- * INIT_TMDS - opcode 0x4f +- * +- */ +-static void +-init_tmds(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 tmds = nv_ro08(bios, init->offset + 1); +- u8 addr = nv_ro08(bios, init->offset + 2); +- u8 mask = nv_ro08(bios, init->offset + 3); +- u8 data = nv_ro08(bios, init->offset + 4); +- u32 reg = init_tmds_reg(init, tmds); +- +- trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n", +- tmds, addr, mask, data); +- init->offset += 5; +- +- if (reg == 0) +- return; +- +- init_wr32(init, reg + 0, addr | 0x00010000); +- init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask)); +- init_wr32(init, reg + 0, addr); +-} +- +-/** +- * INIT_ZM_TMDS_GROUP - opcode 0x50 +- * +- */ +-static void +-init_zm_tmds_group(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 tmds = nv_ro08(bios, init->offset + 1); +- u8 count = nv_ro08(bios, init->offset + 2); +- u32 reg = init_tmds_reg(init, tmds); +- +- trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds); +- init->offset += 3; +- +- while (count--) { +- u8 addr = nv_ro08(bios, init->offset + 0); +- u8 data = nv_ro08(bios, init->offset + 1); +- +- trace("\t[0x%02x] = 0x%02x\n", addr, data); +- init->offset += 2; +- +- init_wr32(init, reg + 4, data); +- init_wr32(init, reg + 0, addr); +- } +-} +- +-/** +- * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51 +- * +- */ +-static void +-init_cr_idx_adr_latch(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 addr0 = nv_ro08(bios, init->offset + 1); +- u8 addr1 = nv_ro08(bios, init->offset + 2); +- u8 base = nv_ro08(bios, init->offset + 3); +- u8 count = nv_ro08(bios, init->offset + 4); +- u8 save0; +- +- trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1); +- init->offset += 5; +- +- save0 = init_rdvgai(init, 0x03d4, addr0); +- while (count--) { +- u8 data = nv_ro08(bios, init->offset); +- +- trace("\t\t[0x%02x] = 0x%02x\n", base, data); +- init->offset += 1; +- +- init_wrvgai(init, 0x03d4, addr0, base++); +- init_wrvgai(init, 0x03d4, addr1, data); +- } +- init_wrvgai(init, 0x03d4, addr0, save0); +-} +- +-/** +- * INIT_CR - opcode 0x52 +- * +- */ +-static void +-init_cr(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 addr = nv_ro08(bios, init->offset + 1); +- u8 mask = nv_ro08(bios, init->offset + 2); +- u8 data = nv_ro08(bios, init->offset + 3); +- u8 val; +- +- trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data); +- init->offset += 4; +- +- val = init_rdvgai(init, 0x03d4, addr) & mask; +- init_wrvgai(init, 0x03d4, addr, val | data); +-} +- +-/** +- * INIT_ZM_CR - opcode 0x53 +- * +- */ +-static void +-init_zm_cr(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 addr = nv_ro08(bios, init->offset + 1); +- u8 data = nv_ro08(bios, init->offset + 2); +- +- trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data); +- init->offset += 3; +- +- init_wrvgai(init, 0x03d4, addr, data); +-} +- +-/** +- * INIT_ZM_CR_GROUP - opcode 0x54 +- * +- */ +-static void +-init_zm_cr_group(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 count = nv_ro08(bios, init->offset + 1); +- +- trace("ZM_CR_GROUP\n"); +- init->offset += 2; +- +- while (count--) { +- u8 addr = nv_ro08(bios, init->offset + 0); +- u8 data = nv_ro08(bios, init->offset + 1); +- +- trace("\t\tC[0x%02x] = 0x%02x\n", addr, data); +- init->offset += 2; +- +- init_wrvgai(init, 0x03d4, addr, data); +- } +-} +- +-/** +- * INIT_CONDITION_TIME - opcode 0x56 +- * +- */ +-static void +-init_condition_time(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 cond = nv_ro08(bios, init->offset + 1); +- u8 retry = nv_ro08(bios, init->offset + 2); +- u8 wait = min((u16)retry * 50, 100); +- +- trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry); +- init->offset += 3; +- +- if (!init_exec(init)) +- return; +- +- while (wait--) { +- if (init_condition_met(init, cond)) +- return; +- mdelay(20); +- } +- +- init_exec_set(init, false); +-} +- +-/** +- * INIT_LTIME - opcode 0x57 +- * +- */ +-static void +-init_ltime(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 msec = nv_ro16(bios, init->offset + 1); +- +- trace("LTIME\t0x%04x\n", msec); +- init->offset += 3; +- +- if (init_exec(init)) +- mdelay(msec); +-} +- +-/** +- * INIT_ZM_REG_SEQUENCE - opcode 0x58 +- * +- */ +-static void +-init_zm_reg_sequence(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 base = nv_ro32(bios, init->offset + 1); +- u8 count = nv_ro08(bios, init->offset + 5); +- +- trace("ZM_REG_SEQUENCE\t0x%02x\n", count); +- init->offset += 6; +- +- while (count--) { +- u32 data = nv_ro32(bios, init->offset); +- +- trace("\t\tR[0x%06x] = 0x%08x\n", base, data); +- init->offset += 4; +- +- init_wr32(init, base, data); +- base += 4; +- } +-} +- +-/** +- * INIT_SUB_DIRECT - opcode 0x5b +- * +- */ +-static void +-init_sub_direct(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 addr = nv_ro16(bios, init->offset + 1); +- u16 save; +- +- trace("SUB_DIRECT\t0x%04x\n", addr); +- +- if (init_exec(init)) { +- save = init->offset; +- init->offset = addr; +- if (nvbios_exec(init)) { +- error("error parsing sub-table\n"); +- return; +- } +- init->offset = save; +- } +- +- init->offset += 3; +-} +- +-/** +- * INIT_JUMP - opcode 0x5c +- * +- */ +-static void +-init_jump(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 offset = nv_ro16(bios, init->offset + 1); +- +- trace("JUMP\t0x%04x\n", offset); +- +- if (init_exec(init)) +- init->offset = offset; +- else +- init->offset += 3; +-} +- +-/** +- * INIT_I2C_IF - opcode 0x5e +- * +- */ +-static void +-init_i2c_if(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 addr = nv_ro08(bios, init->offset + 2); +- u8 reg = nv_ro08(bios, init->offset + 3); +- u8 mask = nv_ro08(bios, init->offset + 4); +- u8 data = nv_ro08(bios, init->offset + 5); +- u8 value; +- +- trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n", +- index, addr, reg, mask, data); +- init->offset += 6; +- init_exec_force(init, true); +- +- value = init_rdi2cr(init, index, addr, reg); +- if ((value & mask) != data) +- init_exec_set(init, false); +- +- init_exec_force(init, false); +-} +- +-/** +- * INIT_COPY_NV_REG - opcode 0x5f +- * +- */ +-static void +-init_copy_nv_reg(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 sreg = nv_ro32(bios, init->offset + 1); +- u8 shift = nv_ro08(bios, init->offset + 5); +- u32 smask = nv_ro32(bios, init->offset + 6); +- u32 sxor = nv_ro32(bios, init->offset + 10); +- u32 dreg = nv_ro32(bios, init->offset + 14); +- u32 dmask = nv_ro32(bios, init->offset + 18); +- u32 data; +- +- trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= " +- "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n", +- dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>", +- (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor); +- init->offset += 22; +- +- data = init_shift(init_rd32(init, sreg), shift); +- init_mask(init, dreg, ~dmask, (data & smask) ^ sxor); +-} +- +-/** +- * INIT_ZM_INDEX_IO - opcode 0x62 +- * +- */ +-static void +-init_zm_index_io(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 port = nv_ro16(bios, init->offset + 1); +- u8 index = nv_ro08(bios, init->offset + 3); +- u8 data = nv_ro08(bios, init->offset + 4); +- +- trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data); +- init->offset += 5; +- +- init_wrvgai(init, port, index, data); +-} +- +-/** +- * INIT_COMPUTE_MEM - opcode 0x63 +- * +- */ +-static void +-init_compute_mem(struct nvbios_init *init) +-{ +- struct nouveau_devinit *devinit = nouveau_devinit(init->bios); +- +- trace("COMPUTE_MEM\n"); +- init->offset += 1; +- +- init_exec_force(init, true); +- if (init_exec(init) && devinit->meminit) +- devinit->meminit(devinit); +- init_exec_force(init, false); +-} +- +-/** +- * INIT_RESET - opcode 0x65 +- * +- */ +-static void +-init_reset(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 reg = nv_ro32(bios, init->offset + 1); +- u32 data1 = nv_ro32(bios, init->offset + 5); +- u32 data2 = nv_ro32(bios, init->offset + 9); +- u32 savepci19; +- +- trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2); +- init->offset += 13; +- init_exec_force(init, true); +- +- savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000); +- init_wr32(init, reg, data1); +- udelay(10); +- init_wr32(init, reg, data2); +- init_wr32(init, 0x00184c, savepci19); +- init_mask(init, 0x001850, 0x00000001, 0x00000000); +- +- init_exec_force(init, false); +-} +- +-/** +- * INIT_CONFIGURE_MEM - opcode 0x66 +- * +- */ +-static u16 +-init_configure_mem_clk(struct nvbios_init *init) +-{ +- u16 mdata = bmp_mem_init_table(init->bios); +- if (mdata) +- mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66; +- return mdata; +-} +- +-static void +-init_configure_mem(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 mdata, sdata; +- u32 addr, data; +- +- trace("CONFIGURE_MEM\n"); +- init->offset += 1; +- +- if (bios->version.major > 2) { +- init_done(init); +- return; +- } +- init_exec_force(init, true); +- +- mdata = init_configure_mem_clk(init); +- sdata = bmp_sdr_seq_table(bios); +- if (nv_ro08(bios, mdata) & 0x01) +- sdata = bmp_ddr_seq_table(bios); +- mdata += 6; /* skip to data */ +- +- data = init_rdvgai(init, 0x03c4, 0x01); +- init_wrvgai(init, 0x03c4, 0x01, data | 0x20); +- +- for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) { +- switch (addr) { +- case 0x10021c: /* CKE_NORMAL */ +- case 0x1002d0: /* CMD_REFRESH */ +- case 0x1002d4: /* CMD_PRECHARGE */ +- data = 0x00000001; +- break; +- default: +- data = nv_ro32(bios, mdata); +- mdata += 4; +- if (data == 0xffffffff) +- continue; +- break; +- } +- +- init_wr32(init, addr, data); +- } +- +- init_exec_force(init, false); +-} +- +-/** +- * INIT_CONFIGURE_CLK - opcode 0x67 +- * +- */ +-static void +-init_configure_clk(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 mdata, clock; +- +- trace("CONFIGURE_CLK\n"); +- init->offset += 1; +- +- if (bios->version.major > 2) { +- init_done(init); +- return; +- } +- init_exec_force(init, true); +- +- mdata = init_configure_mem_clk(init); +- +- /* NVPLL */ +- clock = nv_ro16(bios, mdata + 4) * 10; +- init_prog_pll(init, 0x680500, clock); +- +- /* MPLL */ +- clock = nv_ro16(bios, mdata + 2) * 10; +- if (nv_ro08(bios, mdata) & 0x01) +- clock *= 2; +- init_prog_pll(init, 0x680504, clock); +- +- init_exec_force(init, false); +-} +- +-/** +- * INIT_CONFIGURE_PREINIT - opcode 0x68 +- * +- */ +-static void +-init_configure_preinit(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 strap; +- +- trace("CONFIGURE_PREINIT\n"); +- init->offset += 1; +- +- if (bios->version.major > 2) { +- init_done(init); +- return; +- } +- init_exec_force(init, true); +- +- strap = init_rd32(init, 0x101000); +- strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6); +- init_wrvgai(init, 0x03d4, 0x3c, strap); +- +- init_exec_force(init, false); +-} +- +-/** +- * INIT_IO - opcode 0x69 +- * +- */ +-static void +-init_io(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 port = nv_ro16(bios, init->offset + 1); +- u8 mask = nv_ro16(bios, init->offset + 3); +- u8 data = nv_ro16(bios, init->offset + 4); +- u8 value; +- +- trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data); +- init->offset += 5; +- +- /* ummm.. yes.. should really figure out wtf this is and why it's +- * needed some day.. it's almost certainly wrong, but, it also +- * somehow makes things work... +- */ +- if (nv_device(init->bios)->card_type >= NV_50 && +- port == 0x03c3 && data == 0x01) { +- init_mask(init, 0x614100, 0xf0800000, 0x00800000); +- init_mask(init, 0x00e18c, 0x00020000, 0x00020000); +- init_mask(init, 0x614900, 0xf0800000, 0x00800000); +- init_mask(init, 0x000200, 0x40000000, 0x00000000); +- mdelay(10); +- init_mask(init, 0x00e18c, 0x00020000, 0x00000000); +- init_mask(init, 0x000200, 0x40000000, 0x40000000); +- init_wr32(init, 0x614100, 0x00800018); +- init_wr32(init, 0x614900, 0x00800018); +- mdelay(10); +- init_wr32(init, 0x614100, 0x10000018); +- init_wr32(init, 0x614900, 0x10000018); +- } +- +- value = init_rdport(init, port) & mask; +- init_wrport(init, port, data | value); +-} +- +-/** +- * INIT_SUB - opcode 0x6b +- * +- */ +-static void +-init_sub(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u16 addr, save; +- +- trace("SUB\t0x%02x\n", index); +- +- addr = init_script(bios, index); +- if (addr && init_exec(init)) { +- save = init->offset; +- init->offset = addr; +- if (nvbios_exec(init)) { +- error("error parsing sub-table\n"); +- return; +- } +- init->offset = save; +- } +- +- init->offset += 2; +-} +- +-/** +- * INIT_RAM_CONDITION - opcode 0x6d +- * +- */ +-static void +-init_ram_condition(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 mask = nv_ro08(bios, init->offset + 1); +- u8 value = nv_ro08(bios, init->offset + 2); +- +- trace("RAM_CONDITION\t" +- "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value); +- init->offset += 3; +- +- if ((init_rd32(init, 0x100000) & mask) != value) +- init_exec_set(init, false); +-} +- +-/** +- * INIT_NV_REG - opcode 0x6e +- * +- */ +-static void +-init_nv_reg(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 reg = nv_ro32(bios, init->offset + 1); +- u32 mask = nv_ro32(bios, init->offset + 5); +- u32 data = nv_ro32(bios, init->offset + 9); +- +- trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data); +- init->offset += 13; +- +- init_mask(init, reg, ~mask, data); +-} +- +-/** +- * INIT_MACRO - opcode 0x6f +- * +- */ +-static void +-init_macro(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 macro = nv_ro08(bios, init->offset + 1); +- u16 table; +- +- trace("MACRO\t0x%02x\n", macro); +- +- table = init_macro_table(init); +- if (table) { +- u32 addr = nv_ro32(bios, table + (macro * 8) + 0); +- u32 data = nv_ro32(bios, table + (macro * 8) + 4); +- trace("\t\tR[0x%06x] = 0x%08x\n", addr, data); +- init_wr32(init, addr, data); +- } +- +- init->offset += 2; +-} +- +-/** +- * INIT_RESUME - opcode 0x72 +- * +- */ +-static void +-init_resume(struct nvbios_init *init) +-{ +- trace("RESUME\n"); +- init->offset += 1; +- init_exec_set(init, true); +-} +- +-/** +- * INIT_TIME - opcode 0x74 +- * +- */ +-static void +-init_time(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 usec = nv_ro16(bios, init->offset + 1); +- +- trace("TIME\t0x%04x\n", usec); +- init->offset += 3; +- +- if (init_exec(init)) { +- if (usec < 1000) +- udelay(usec); +- else +- mdelay((usec + 900) / 1000); +- } +-} +- +-/** +- * INIT_CONDITION - opcode 0x75 +- * +- */ +-static void +-init_condition(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 cond = nv_ro08(bios, init->offset + 1); +- +- trace("CONDITION\t0x%02x\n", cond); +- init->offset += 2; +- +- if (!init_condition_met(init, cond)) +- init_exec_set(init, false); +-} +- +-/** +- * INIT_IO_CONDITION - opcode 0x76 +- * +- */ +-static void +-init_io_condition(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 cond = nv_ro08(bios, init->offset + 1); +- +- trace("IO_CONDITION\t0x%02x\n", cond); +- init->offset += 2; +- +- if (!init_io_condition_met(init, cond)) +- init_exec_set(init, false); +-} +- +-/** +- * INIT_INDEX_IO - opcode 0x78 +- * +- */ +-static void +-init_index_io(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u16 port = nv_ro16(bios, init->offset + 1); +- u8 index = nv_ro16(bios, init->offset + 3); +- u8 mask = nv_ro08(bios, init->offset + 4); +- u8 data = nv_ro08(bios, init->offset + 5); +- u8 value; +- +- trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n", +- port, index, mask, data); +- init->offset += 6; +- +- value = init_rdvgai(init, port, index) & mask; +- init_wrvgai(init, port, index, data | value); +-} +- +-/** +- * INIT_PLL - opcode 0x79 +- * +- */ +-static void +-init_pll(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 reg = nv_ro32(bios, init->offset + 1); +- u32 freq = nv_ro16(bios, init->offset + 5) * 10; +- +- trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq); +- init->offset += 7; +- +- init_prog_pll(init, reg, freq); +-} +- +-/** +- * INIT_ZM_REG - opcode 0x7a +- * +- */ +-static void +-init_zm_reg(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 addr = nv_ro32(bios, init->offset + 1); +- u32 data = nv_ro32(bios, init->offset + 5); +- +- trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data); +- init->offset += 9; +- +- if (addr == 0x000200) +- data |= 0x00000001; +- +- init_wr32(init, addr, data); +-} +- +-/** +- * INIT_RAM_RESTRICT_PLL - opcde 0x87 +- * +- */ +-static void +-init_ram_restrict_pll(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 type = nv_ro08(bios, init->offset + 1); +- u8 count = init_ram_restrict_group_count(init); +- u8 strap = init_ram_restrict(init); +- u8 cconf; +- +- trace("RAM_RESTRICT_PLL\t0x%02x\n", type); +- init->offset += 2; +- +- for (cconf = 0; cconf < count; cconf++) { +- u32 freq = nv_ro32(bios, init->offset); +- +- if (cconf == strap) { +- trace("%dkHz *\n", freq); +- init_prog_pll(init, type, freq); +- } else { +- trace("%dkHz\n", freq); +- } +- +- init->offset += 4; +- } +-} +- +-/** +- * INIT_GPIO - opcode 0x8e +- * +- */ +-static void +-init_gpio(struct nvbios_init *init) +-{ +- struct nouveau_gpio *gpio = nouveau_gpio(init->bios); +- +- trace("GPIO\n"); +- init->offset += 1; +- +- if (init_exec(init) && gpio && gpio->reset) +- gpio->reset(gpio, DCB_GPIO_UNUSED); +-} +- +-/** +- * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f +- * +- */ +-static void +-init_ram_restrict_zm_reg_group(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 addr = nv_ro32(bios, init->offset + 1); +- u8 incr = nv_ro08(bios, init->offset + 5); +- u8 num = nv_ro08(bios, init->offset + 6); +- u8 count = init_ram_restrict_group_count(init); +- u8 index = init_ram_restrict(init); +- u8 i, j; +- +- trace("RAM_RESTRICT_ZM_REG_GROUP\t" +- "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num); +- init->offset += 7; +- +- for (i = 0; i < num; i++) { +- trace("\tR[0x%06x] = {\n", addr); +- for (j = 0; j < count; j++) { +- u32 data = nv_ro32(bios, init->offset); +- +- if (j == index) { +- trace("\t\t0x%08x *\n", data); +- init_wr32(init, addr, data); +- } else { +- trace("\t\t0x%08x\n", data); +- } +- +- init->offset += 4; +- } +- trace("\t}\n"); +- addr += incr; +- } +-} +- +-/** +- * INIT_COPY_ZM_REG - opcode 0x90 +- * +- */ +-static void +-init_copy_zm_reg(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 sreg = nv_ro32(bios, init->offset + 1); +- u32 dreg = nv_ro32(bios, init->offset + 5); +- +- trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg); +- init->offset += 9; +- +- init_wr32(init, dreg, init_rd32(init, sreg)); +-} +- +-/** +- * INIT_ZM_REG_GROUP - opcode 0x91 +- * +- */ +-static void +-init_zm_reg_group(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 addr = nv_ro32(bios, init->offset + 1); +- u8 count = nv_ro08(bios, init->offset + 5); +- +- trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr); +- init->offset += 6; +- +- while (count--) { +- u32 data = nv_ro32(bios, init->offset); +- trace("\t0x%08x\n", data); +- init_wr32(init, addr, data); +- init->offset += 4; +- } +-} +- +-/** +- * INIT_XLAT - opcode 0x96 +- * +- */ +-static void +-init_xlat(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 saddr = nv_ro32(bios, init->offset + 1); +- u8 sshift = nv_ro08(bios, init->offset + 5); +- u8 smask = nv_ro08(bios, init->offset + 6); +- u8 index = nv_ro08(bios, init->offset + 7); +- u32 daddr = nv_ro32(bios, init->offset + 8); +- u32 dmask = nv_ro32(bios, init->offset + 12); +- u8 shift = nv_ro08(bios, init->offset + 16); +- u32 data; +- +- trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= " +- "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n", +- daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>", +- (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift); +- init->offset += 17; +- +- data = init_shift(init_rd32(init, saddr), sshift) & smask; +- data = init_xlat_(init, index, data) << shift; +- init_mask(init, daddr, ~dmask, data); +-} +- +-/** +- * INIT_ZM_MASK_ADD - opcode 0x97 +- * +- */ +-static void +-init_zm_mask_add(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 addr = nv_ro32(bios, init->offset + 1); +- u32 mask = nv_ro32(bios, init->offset + 5); +- u32 add = nv_ro32(bios, init->offset + 9); +- u32 data; +- +- trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add); +- init->offset += 13; +- +- data = init_rd32(init, addr); +- data = (data & mask) | ((data + add) & ~mask); +- init_wr32(init, addr, data); +-} +- +-/** +- * INIT_AUXCH - opcode 0x98 +- * +- */ +-static void +-init_auxch(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 addr = nv_ro32(bios, init->offset + 1); +- u8 count = nv_ro08(bios, init->offset + 5); +- +- trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); +- init->offset += 6; +- +- while (count--) { +- u8 mask = nv_ro08(bios, init->offset + 0); +- u8 data = nv_ro08(bios, init->offset + 1); +- trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data); +- mask = init_rdauxr(init, addr) & mask; +- init_wrauxr(init, addr, mask | data); +- init->offset += 2; +- } +-} +- +-/** +- * INIT_AUXCH - opcode 0x99 +- * +- */ +-static void +-init_zm_auxch(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u32 addr = nv_ro32(bios, init->offset + 1); +- u8 count = nv_ro08(bios, init->offset + 5); +- +- trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count); +- init->offset += 6; +- +- while (count--) { +- u8 data = nv_ro08(bios, init->offset + 0); +- trace("\tAUX[0x%08x] = 0x%02x\n", addr, data); +- init_wrauxr(init, addr, data); +- init->offset += 1; +- } +-} +- +-/** +- * INIT_I2C_LONG_IF - opcode 0x9a +- * +- */ +-static void +-init_i2c_long_if(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- u8 index = nv_ro08(bios, init->offset + 1); +- u8 addr = nv_ro08(bios, init->offset + 2) >> 1; +- u8 reglo = nv_ro08(bios, init->offset + 3); +- u8 reghi = nv_ro08(bios, init->offset + 4); +- u8 mask = nv_ro08(bios, init->offset + 5); +- u8 data = nv_ro08(bios, init->offset + 6); +- struct nouveau_i2c_port *port; +- +- trace("I2C_LONG_IF\t" +- "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n", +- index, addr, reglo, reghi, mask, data); +- init->offset += 7; +- +- port = init_i2c(init, index); +- if (port) { +- u8 i[2] = { reghi, reglo }; +- u8 o[1] = {}; +- struct i2c_msg msg[] = { +- { .addr = addr, .flags = 0, .len = 2, .buf = i }, +- { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o } +- }; +- int ret; +- +- ret = i2c_transfer(&port->adapter, msg, 2); +- if (ret == 2 && ((o[0] & mask) == data)) +- return; +- } +- +- init_exec_set(init, false); +-} +- +-/** +- * INIT_GPIO_NE - opcode 0xa9 +- * +- */ +-static void +-init_gpio_ne(struct nvbios_init *init) +-{ +- struct nouveau_bios *bios = init->bios; +- struct nouveau_gpio *gpio = nouveau_gpio(bios); +- struct dcb_gpio_func func; +- u8 count = nv_ro08(bios, init->offset + 1); +- u8 idx = 0, ver, len; +- u16 data, i; +- +- trace("GPIO_NE\t"); +- init->offset += 2; +- +- for (i = init->offset; i < init->offset + count; i++) +- cont("0x%02x ", nv_ro08(bios, i)); +- cont("\n"); +- +- while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) { +- if (func.func != DCB_GPIO_UNUSED) { +- for (i = init->offset; i < init->offset + count; i++) { +- if (func.func == nv_ro08(bios, i)) +- break; +- } +- +- trace("\tFUNC[0x%02x]", func.func); +- if (i == (init->offset + count)) { +- cont(" *"); +- if (init_exec(init) && gpio && gpio->reset) +- gpio->reset(gpio, func.func); +- } +- cont("\n"); +- } +- } +- +- init->offset += count; +-} +- +-static struct nvbios_init_opcode { +- void (*exec)(struct nvbios_init *); +-} init_opcode[] = { +- [0x32] = { init_io_restrict_prog }, +- [0x33] = { init_repeat }, +- [0x34] = { init_io_restrict_pll }, +- [0x36] = { init_end_repeat }, +- [0x37] = { init_copy }, +- [0x38] = { init_not }, +- [0x39] = { init_io_flag_condition }, +- [0x3a] = { init_dp_condition }, +- [0x3b] = { init_io_mask_or }, +- [0x3c] = { init_io_or }, +- [0x49] = { init_idx_addr_latched }, +- [0x4a] = { init_io_restrict_pll2 }, +- [0x4b] = { init_pll2 }, +- [0x4c] = { init_i2c_byte }, +- [0x4d] = { init_zm_i2c_byte }, +- [0x4e] = { init_zm_i2c }, +- [0x4f] = { init_tmds }, +- [0x50] = { init_zm_tmds_group }, +- [0x51] = { init_cr_idx_adr_latch }, +- [0x52] = { init_cr }, +- [0x53] = { init_zm_cr }, +- [0x54] = { init_zm_cr_group }, +- [0x56] = { init_condition_time }, +- [0x57] = { init_ltime }, +- [0x58] = { init_zm_reg_sequence }, +- [0x5b] = { init_sub_direct }, +- [0x5c] = { init_jump }, +- [0x5e] = { init_i2c_if }, +- [0x5f] = { init_copy_nv_reg }, +- [0x62] = { init_zm_index_io }, +- [0x63] = { init_compute_mem }, +- [0x65] = { init_reset }, +- [0x66] = { init_configure_mem }, +- [0x67] = { init_configure_clk }, +- [0x68] = { init_configure_preinit }, +- [0x69] = { init_io }, +- [0x6b] = { init_sub }, +- [0x6d] = { init_ram_condition }, +- [0x6e] = { init_nv_reg }, +- [0x6f] = { init_macro }, +- [0x71] = { init_done }, +- [0x72] = { init_resume }, +- [0x74] = { init_time }, +- [0x75] = { init_condition }, +- [0x76] = { init_io_condition }, +- [0x78] = { init_index_io }, +- [0x79] = { init_pll }, +- [0x7a] = { init_zm_reg }, +- [0x87] = { init_ram_restrict_pll }, +- [0x8c] = { init_reserved }, +- [0x8d] = { init_reserved }, +- [0x8e] = { init_gpio }, +- [0x8f] = { init_ram_restrict_zm_reg_group }, +- [0x90] = { init_copy_zm_reg }, +- [0x91] = { init_zm_reg_group }, +- [0x92] = { init_reserved }, +- [0x96] = { init_xlat }, +- [0x97] = { init_zm_mask_add }, +- [0x98] = { init_auxch }, +- [0x99] = { init_zm_auxch }, +- [0x9a] = { init_i2c_long_if }, +- [0xa9] = { init_gpio_ne }, +- [0xaa] = { init_reserved }, +-}; +- +-#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0])) +- +-int +-nvbios_exec(struct nvbios_init *init) +-{ +- init->nested++; +- while (init->offset) { +- u8 opcode = nv_ro08(init->bios, init->offset); +- if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) { +- error("unknown opcode 0x%02x\n", opcode); +- return -EINVAL; +- } +- +- init_opcode[opcode].exec(init); +- } +- init->nested--; +- return 0; +-} +- +-int +-nvbios_init(struct nouveau_subdev *subdev, bool execute) +-{ +- struct nouveau_bios *bios = nouveau_bios(subdev); +- int ret = 0; +- int i = -1; +- u16 data; +- +- if (execute) +- nv_info(bios, "running init tables\n"); +- while (!ret && (data = (init_script(bios, ++i)))) { +- struct nvbios_init init = { +- .subdev = subdev, +- .bios = bios, +- .offset = data, +- .outp = NULL, +- .crtc = -1, +- .execute = execute ? 1 : 0, +- }; +- +- ret = nvbios_exec(&init); +- } +- +- /* the vbios parser will run this right after the normal init +- * tables, whereas the binary driver appears to run it later. +- */ +- if (!ret && (data = init_unknown_script(bios))) { +- struct nvbios_init init = { +- .subdev = subdev, +- .bios = bios, +- .offset = data, +- .outp = NULL, +- .crtc = -1, +- .execute = execute ? 1 : 0, +- }; +- +- ret = nvbios_exec(&init); +- } +- +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c b/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c +deleted file mode 100644 +index 2610b11a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/mxm.c ++++ /dev/null +@@ -1,135 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-u16 +-mxm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr) +-{ +- struct bit_entry x; +- +- if (bit_entry(bios, 'x', &x)) { +- nv_debug(bios, "BIT 'x' table not present\n"); +- return 0x0000; +- } +- +- *ver = x.version; +- *hdr = x.length; +- if (*ver != 1 || *hdr < 3) { +- nv_warn(bios, "BIT 'x' table %d/%d unknown\n", *ver, *hdr); +- return 0x0000; +- } +- +- return x.offset; +-} +- +-/* These map MXM v2.x digital connection values to the appropriate SOR/link, +- * hopefully they're correct for all boards within the same chipset... +- * +- * MXM v3.x VBIOS are nicer and provide pointers to these tables. +- */ +-static u8 nv84_sor_map[16] = { +- 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, +- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +-}; +- +-static u8 nv92_sor_map[16] = { +- 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, +- 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +-}; +- +-static u8 nv94_sor_map[16] = { +- 0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31, +- 0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00 +-}; +- +-static u8 nv98_sor_map[16] = { +- 0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31, +- 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +-}; +- +-u8 +-mxm_sor_map(struct nouveau_bios *bios, u8 conn) +-{ +- u8 ver, hdr; +- u16 mxm = mxm_table(bios, &ver, &hdr); +- if (mxm && hdr >= 6) { +- u16 map = nv_ro16(bios, mxm + 4); +- if (map) { +- ver = nv_ro08(bios, map); +- if (ver == 0x10) { +- if (conn < nv_ro08(bios, map + 3)) { +- map += nv_ro08(bios, map + 1); +- map += conn; +- return nv_ro08(bios, map); +- } +- +- return 0x00; +- } +- +- nv_warn(bios, "unknown sor map v%02x\n", ver); +- } +- } +- +- if (bios->version.chip == 0x84 || bios->version.chip == 0x86) +- return nv84_sor_map[conn]; +- if (bios->version.chip == 0x92) +- return nv92_sor_map[conn]; +- if (bios->version.chip == 0x94 || bios->version.chip == 0x96) +- return nv94_sor_map[conn]; +- if (bios->version.chip == 0x98) +- return nv98_sor_map[conn]; +- +- nv_warn(bios, "missing sor map\n"); +- return 0x00; +-} +- +-u8 +-mxm_ddc_map(struct nouveau_bios *bios, u8 port) +-{ +- u8 ver, hdr; +- u16 mxm = mxm_table(bios, &ver, &hdr); +- if (mxm && hdr >= 8) { +- u16 map = nv_ro16(bios, mxm + 6); +- if (map) { +- ver = nv_ro08(bios, map); +- if (ver == 0x10) { +- if (port < nv_ro08(bios, map + 3)) { +- map += nv_ro08(bios, map + 1); +- map += port; +- return nv_ro08(bios, map); +- } +- +- return 0x00; +- } +- +- nv_warn(bios, "unknown ddc map v%02x\n", ver); +- } +- } +- +- /* v2.x: directly write port as dcb i2cidx */ +- return (port << 4) | port; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c b/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c +deleted file mode 100644 +index 675e2216..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/perf.c ++++ /dev/null +@@ -1,201 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, +- u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +-{ +- struct bit_entry bit_P; +- u16 perf = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version <= 2) { +- perf = nv_ro16(bios, bit_P.offset + 0); +- if (perf) { +- *ver = nv_ro08(bios, perf + 0); +- *hdr = nv_ro08(bios, perf + 1); +- if (*ver >= 0x40 && *ver < 0x41) { +- *cnt = nv_ro08(bios, perf + 5); +- *len = nv_ro08(bios, perf + 2); +- *snr = nv_ro08(bios, perf + 4); +- *ssz = nv_ro08(bios, perf + 3); +- return perf; +- } else +- if (*ver >= 0x20 && *ver < 0x40) { +- *cnt = nv_ro08(bios, perf + 2); +- *len = nv_ro08(bios, perf + 3); +- *snr = nv_ro08(bios, perf + 4); +- *ssz = nv_ro08(bios, perf + 5); +- return perf; +- } +- } +- } +- } +- +- if (bios->bmp_offset) { +- if (nv_ro08(bios, bios->bmp_offset + 6) >= 0x25) { +- perf = nv_ro16(bios, bios->bmp_offset + 0x94); +- if (perf) { +- *hdr = nv_ro08(bios, perf + 0); +- *ver = nv_ro08(bios, perf + 1); +- *cnt = nv_ro08(bios, perf + 2); +- *len = nv_ro08(bios, perf + 3); +- *snr = 0; +- *ssz = 0; +- return perf; +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_perf_entry(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u8 snr, ssz; +- u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz); +- if (perf && idx < *cnt) { +- perf = perf + *hdr + (idx * (*len + (snr * ssz))); +- *hdr = *len; +- *cnt = snr; +- *len = ssz; +- return perf; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_perfEp(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_perfE *info) +-{ +- u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- info->pstate = nv_ro08(bios, perf + 0x00); +- switch (!!perf * *ver) { +- case 0x12: +- case 0x13: +- case 0x14: +- info->core = nv_ro32(bios, perf + 0x01) * 10; +- info->memory = nv_ro32(bios, perf + 0x05) * 20; +- info->fanspeed = nv_ro08(bios, perf + 0x37); +- if (*hdr > 0x38) +- info->voltage = nv_ro08(bios, perf + 0x38); +- break; +- case 0x21: +- case 0x23: +- case 0x24: +- info->fanspeed = nv_ro08(bios, perf + 0x04); +- info->voltage = nv_ro08(bios, perf + 0x05); +- info->shader = nv_ro16(bios, perf + 0x06) * 1000; +- info->core = info->shader + (signed char) +- nv_ro08(bios, perf + 0x08) * 1000; +- switch (nv_device(bios)->chipset) { +- case 0x49: +- case 0x4b: +- info->memory = nv_ro16(bios, perf + 0x0b) * 1000; +- break; +- default: +- info->memory = nv_ro16(bios, perf + 0x0b) * 2000; +- break; +- } +- break; +- case 0x25: +- info->fanspeed = nv_ro08(bios, perf + 0x04); +- info->voltage = nv_ro08(bios, perf + 0x05); +- info->core = nv_ro16(bios, perf + 0x06) * 1000; +- info->shader = nv_ro16(bios, perf + 0x0a) * 1000; +- info->memory = nv_ro16(bios, perf + 0x0c) * 1000; +- break; +- case 0x30: +- info->script = nv_ro16(bios, perf + 0x02); +- case 0x35: +- info->fanspeed = nv_ro08(bios, perf + 0x06); +- info->voltage = nv_ro08(bios, perf + 0x07); +- info->core = nv_ro16(bios, perf + 0x08) * 1000; +- info->shader = nv_ro16(bios, perf + 0x0a) * 1000; +- info->memory = nv_ro16(bios, perf + 0x0c) * 1000; +- info->vdec = nv_ro16(bios, perf + 0x10) * 1000; +- info->disp = nv_ro16(bios, perf + 0x14) * 1000; +- break; +- case 0x40: +- info->voltage = nv_ro08(bios, perf + 0x02); +- break; +- default: +- return 0x0000; +- } +- return perf; +-} +- +-u32 +-nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx, +- u8 *ver, u8 *hdr, u8 cnt, u8 len) +-{ +- u32 data = 0x00000000; +- if (idx < cnt) { +- data = perfE + *hdr + (idx * len); +- *hdr = len; +- } +- return data; +-} +- +-u32 +-nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx, +- u8 *ver, u8 *hdr, u8 cnt, u8 len, +- struct nvbios_perfS *info) +-{ +- u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!data * *ver) { +- case 0x40: +- info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000; +- break; +- default: +- break; +- } +- return data; +-} +- +-int +-nvbios_perf_fan_parse(struct nouveau_bios *bios, +- struct nvbios_perf_fan *fan) +-{ +- u8 ver, hdr, cnt, len, snr, ssz; +- u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); +- if (!perf) +- return -ENODEV; +- +- if (ver >= 0x20 && ver < 0x40 && hdr > 6) +- fan->pwm_divisor = nv_ro16(bios, perf + 6); +- else +- fan->pwm_divisor = 0; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c b/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c +deleted file mode 100644 +index 1f76de59..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/pll.c ++++ /dev/null +@@ -1,416 +0,0 @@ +-/* +- * Copyright 2005-2006 Erik Waling +- * Copyright 2006 Stephane Marchesin +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-struct pll_mapping { +- u8 type; +- u32 reg; +-}; +- +-static struct pll_mapping +-nv04_pll_mapping[] = { +- { PLL_CORE , 0x680500 }, +- { PLL_MEMORY, 0x680504 }, +- { PLL_VPLL0 , 0x680508 }, +- { PLL_VPLL1 , 0x680520 }, +- {} +-}; +- +-static struct pll_mapping +-nv40_pll_mapping[] = { +- { PLL_CORE , 0x004000 }, +- { PLL_MEMORY, 0x004020 }, +- { PLL_VPLL0 , 0x680508 }, +- { PLL_VPLL1 , 0x680520 }, +- {} +-}; +- +-static struct pll_mapping +-nv50_pll_mapping[] = { +- { PLL_CORE , 0x004028 }, +- { PLL_SHADER, 0x004020 }, +- { PLL_UNK03 , 0x004000 }, +- { PLL_MEMORY, 0x004008 }, +- { PLL_UNK40 , 0x00e810 }, +- { PLL_UNK41 , 0x00e818 }, +- { PLL_UNK42 , 0x00e824 }, +- { PLL_VPLL0 , 0x614100 }, +- { PLL_VPLL1 , 0x614900 }, +- {} +-}; +- +-static struct pll_mapping +-nv84_pll_mapping[] = { +- { PLL_CORE , 0x004028 }, +- { PLL_SHADER, 0x004020 }, +- { PLL_MEMORY, 0x004008 }, +- { PLL_VDEC , 0x004030 }, +- { PLL_UNK41 , 0x00e818 }, +- { PLL_VPLL0 , 0x614100 }, +- { PLL_VPLL1 , 0x614900 }, +- {} +-}; +- +-static u16 +-pll_limits_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct bit_entry bit_C; +- +- if (!bit_entry(bios, 'C', &bit_C) && bit_C.length >= 10) { +- u16 data = nv_ro16(bios, bit_C.offset + 8); +- if (data) { +- *ver = nv_ro08(bios, data + 0); +- *hdr = nv_ro08(bios, data + 1); +- *len = nv_ro08(bios, data + 2); +- *cnt = nv_ro08(bios, data + 3); +- return data; +- } +- } +- +- if (bmp_version(bios) >= 0x0524) { +- u16 data = nv_ro16(bios, bios->bmp_offset + 142); +- if (data) { +- *ver = nv_ro08(bios, data + 0); +- *hdr = 1; +- *cnt = 1; +- *len = 0x18; +- return data; +- } +- } +- +- *ver = 0x00; +- return 0x0000; +-} +- +-static struct pll_mapping * +-pll_map(struct nouveau_bios *bios) +-{ +- switch (nv_device(bios)->card_type) { +- case NV_04: +- case NV_10: +- case NV_11: +- case NV_20: +- case NV_30: +- return nv04_pll_mapping; +- break; +- case NV_40: +- return nv40_pll_mapping; +- case NV_50: +- if (nv_device(bios)->chipset == 0x50) +- return nv50_pll_mapping; +- else +- if (nv_device(bios)->chipset < 0xa3 || +- nv_device(bios)->chipset == 0xaa || +- nv_device(bios)->chipset == 0xac) +- return nv84_pll_mapping; +- default: +- return NULL; +- } +-} +- +-static u16 +-pll_map_reg(struct nouveau_bios *bios, u32 reg, u32 *type, u8 *ver, u8 *len) +-{ +- struct pll_mapping *map; +- u8 hdr, cnt; +- u16 data; +- +- data = pll_limits_table(bios, ver, &hdr, &cnt, len); +- if (data && *ver >= 0x30) { +- data += hdr; +- while (cnt--) { +- if (nv_ro32(bios, data + 3) == reg) { +- *type = nv_ro08(bios, data + 0); +- return data; +- } +- data += *len; +- } +- return 0x0000; +- } +- +- map = pll_map(bios); +- while (map->reg) { +- if (map->reg == reg && *ver >= 0x20) { +- u16 addr = (data += hdr); +- *type = map->type; +- while (cnt--) { +- if (nv_ro32(bios, data) == map->reg) +- return data; +- data += *len; +- } +- return addr; +- } else +- if (map->reg == reg) { +- *type = map->type; +- return data + 1; +- } +- map++; +- } +- +- return 0x0000; +-} +- +-static u16 +-pll_map_type(struct nouveau_bios *bios, u8 type, u32 *reg, u8 *ver, u8 *len) +-{ +- struct pll_mapping *map; +- u8 hdr, cnt; +- u16 data; +- +- data = pll_limits_table(bios, ver, &hdr, &cnt, len); +- if (data && *ver >= 0x30) { +- data += hdr; +- while (cnt--) { +- if (nv_ro08(bios, data + 0) == type) { +- *reg = nv_ro32(bios, data + 3); +- return data; +- } +- data += *len; +- } +- return 0x0000; +- } +- +- map = pll_map(bios); +- while (map->reg) { +- if (map->type == type && *ver >= 0x20) { +- u16 addr = (data += hdr); +- *reg = map->reg; +- while (cnt--) { +- if (nv_ro32(bios, data) == map->reg) +- return data; +- data += *len; +- } +- return addr; +- } else +- if (map->type == type) { +- *reg = map->reg; +- return data + 1; +- } +- map++; +- } +- +- return 0x0000; +-} +- +-int +-nvbios_pll_parse(struct nouveau_bios *bios, u32 type, struct nvbios_pll *info) +-{ +- u8 ver, len; +- u32 reg = type; +- u16 data; +- +- if (type > PLL_MAX) { +- reg = type; +- data = pll_map_reg(bios, reg, &type, &ver, &len); +- } else { +- data = pll_map_type(bios, type, ®, &ver, &len); +- } +- +- if (ver && !data) +- return -ENOENT; +- +- memset(info, 0, sizeof(*info)); +- info->type = type; +- info->reg = reg; +- +- switch (ver) { +- case 0x00: +- break; +- case 0x10: +- case 0x11: +- info->vco1.min_freq = nv_ro32(bios, data + 0); +- info->vco1.max_freq = nv_ro32(bios, data + 4); +- info->vco2.min_freq = nv_ro32(bios, data + 8); +- info->vco2.max_freq = nv_ro32(bios, data + 12); +- info->vco1.min_inputfreq = nv_ro32(bios, data + 16); +- info->vco2.min_inputfreq = nv_ro32(bios, data + 20); +- info->vco1.max_inputfreq = INT_MAX; +- info->vco2.max_inputfreq = INT_MAX; +- +- info->max_p = 0x7; +- info->max_p_usable = 0x6; +- +- /* these values taken from nv30/31/36 */ +- switch (bios->version.chip) { +- case 0x36: +- info->vco1.min_n = 0x5; +- break; +- default: +- info->vco1.min_n = 0x1; +- break; +- } +- info->vco1.max_n = 0xff; +- info->vco1.min_m = 0x1; +- info->vco1.max_m = 0xd; +- +- /* +- * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this +- * table version (apart from nv35)), N2 is compared to +- * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and +- * save a comparison +- */ +- info->vco2.min_n = 0x4; +- switch (bios->version.chip) { +- case 0x30: +- case 0x35: +- info->vco2.max_n = 0x1f; +- break; +- default: +- info->vco2.max_n = 0x28; +- break; +- } +- info->vco2.min_m = 0x1; +- info->vco2.max_m = 0x4; +- break; +- case 0x20: +- case 0x21: +- info->vco1.min_freq = nv_ro16(bios, data + 4) * 1000; +- info->vco1.max_freq = nv_ro16(bios, data + 6) * 1000; +- info->vco2.min_freq = nv_ro16(bios, data + 8) * 1000; +- info->vco2.max_freq = nv_ro16(bios, data + 10) * 1000; +- info->vco1.min_inputfreq = nv_ro16(bios, data + 12) * 1000; +- info->vco2.min_inputfreq = nv_ro16(bios, data + 14) * 1000; +- info->vco1.max_inputfreq = nv_ro16(bios, data + 16) * 1000; +- info->vco2.max_inputfreq = nv_ro16(bios, data + 18) * 1000; +- info->vco1.min_n = nv_ro08(bios, data + 20); +- info->vco1.max_n = nv_ro08(bios, data + 21); +- info->vco1.min_m = nv_ro08(bios, data + 22); +- info->vco1.max_m = nv_ro08(bios, data + 23); +- info->vco2.min_n = nv_ro08(bios, data + 24); +- info->vco2.max_n = nv_ro08(bios, data + 25); +- info->vco2.min_m = nv_ro08(bios, data + 26); +- info->vco2.max_m = nv_ro08(bios, data + 27); +- +- info->max_p = nv_ro08(bios, data + 29); +- info->max_p_usable = info->max_p; +- if (bios->version.chip < 0x60) +- info->max_p_usable = 0x6; +- info->bias_p = nv_ro08(bios, data + 30); +- +- if (len > 0x22) +- info->refclk = nv_ro32(bios, data + 31); +- break; +- case 0x30: +- data = nv_ro16(bios, data + 1); +- +- info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; +- info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; +- info->vco2.min_freq = nv_ro16(bios, data + 4) * 1000; +- info->vco2.max_freq = nv_ro16(bios, data + 6) * 1000; +- info->vco1.min_inputfreq = nv_ro16(bios, data + 8) * 1000; +- info->vco2.min_inputfreq = nv_ro16(bios, data + 10) * 1000; +- info->vco1.max_inputfreq = nv_ro16(bios, data + 12) * 1000; +- info->vco2.max_inputfreq = nv_ro16(bios, data + 14) * 1000; +- info->vco1.min_n = nv_ro08(bios, data + 16); +- info->vco1.max_n = nv_ro08(bios, data + 17); +- info->vco1.min_m = nv_ro08(bios, data + 18); +- info->vco1.max_m = nv_ro08(bios, data + 19); +- info->vco2.min_n = nv_ro08(bios, data + 20); +- info->vco2.max_n = nv_ro08(bios, data + 21); +- info->vco2.min_m = nv_ro08(bios, data + 22); +- info->vco2.max_m = nv_ro08(bios, data + 23); +- info->max_p_usable = info->max_p = nv_ro08(bios, data + 25); +- info->bias_p = nv_ro08(bios, data + 27); +- info->refclk = nv_ro32(bios, data + 28); +- break; +- case 0x40: +- info->refclk = nv_ro16(bios, data + 9) * 1000; +- data = nv_ro16(bios, data + 1); +- +- info->vco1.min_freq = nv_ro16(bios, data + 0) * 1000; +- info->vco1.max_freq = nv_ro16(bios, data + 2) * 1000; +- info->vco1.min_inputfreq = nv_ro16(bios, data + 4) * 1000; +- info->vco1.max_inputfreq = nv_ro16(bios, data + 6) * 1000; +- info->vco1.min_m = nv_ro08(bios, data + 8); +- info->vco1.max_m = nv_ro08(bios, data + 9); +- info->vco1.min_n = nv_ro08(bios, data + 10); +- info->vco1.max_n = nv_ro08(bios, data + 11); +- info->min_p = nv_ro08(bios, data + 12); +- info->max_p = nv_ro08(bios, data + 13); +- break; +- default: +- nv_error(bios, "unknown pll limits version 0x%02x\n", ver); +- return -EINVAL; +- } +- +- if (!info->refclk) { +- info->refclk = nv_device(bios)->crystal; +- if (bios->version.chip == 0x51) { +- u32 sel_clk = nv_rd32(bios, 0x680524); +- if ((info->reg == 0x680508 && sel_clk & 0x20) || +- (info->reg == 0x680520 && sel_clk & 0x80)) { +- if (nv_rdvgac(bios, 0, 0x27) < 0xa3) +- info->refclk = 200000; +- else +- info->refclk = 25000; +- } +- } +- } +- +- /* +- * By now any valid limit table ought to have set a max frequency for +- * vco1, so if it's zero it's either a pre limit table bios, or one +- * with an empty limit table (seen on nv18) +- */ +- if (!info->vco1.max_freq) { +- info->vco1.max_freq = nv_ro32(bios, bios->bmp_offset + 67); +- info->vco1.min_freq = nv_ro32(bios, bios->bmp_offset + 71); +- if (bmp_version(bios) < 0x0506) { +- info->vco1.max_freq = 256000; +- info->vco1.min_freq = 128000; +- } +- +- info->vco1.min_inputfreq = 0; +- info->vco1.max_inputfreq = INT_MAX; +- info->vco1.min_n = 0x1; +- info->vco1.max_n = 0xff; +- info->vco1.min_m = 0x1; +- +- if (nv_device(bios)->crystal == 13500) { +- /* nv05 does this, nv11 doesn't, nv10 unknown */ +- if (bios->version.chip < 0x11) +- info->vco1.min_m = 0x7; +- info->vco1.max_m = 0xd; +- } else { +- if (bios->version.chip < 0x11) +- info->vco1.min_m = 0x8; +- info->vco1.max_m = 0xe; +- } +- +- if (bios->version.chip < 0x17 || +- bios->version.chip == 0x1a || +- bios->version.chip == 0x20) +- info->max_p = 4; +- else +- info->max_p = 5; +- info->max_p_usable = info->max_p; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c b/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c +deleted file mode 100644 +index 6c401f70..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/ramcfg.c ++++ /dev/null +@@ -1,68 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-static u8 +-nvbios_ramcfg_strap(struct nouveau_subdev *subdev) +-{ +- return (nv_rd32(subdev, 0x101000) & 0x0000003c) >> 2; +-} +- +-u8 +-nvbios_ramcfg_count(struct nouveau_bios *bios) +-{ +- struct bit_entry bit_M; +- +- if (!bit_entry(bios, 'M', &bit_M)) { +- if (bit_M.version == 1 && bit_M.length >= 5) +- return nv_ro08(bios, bit_M.offset + 2); +- if (bit_M.version == 2 && bit_M.length >= 3) +- return nv_ro08(bios, bit_M.offset + 0); +- } +- +- return 0x00; +-} +- +-u8 +-nvbios_ramcfg_index(struct nouveau_subdev *subdev) +-{ +- struct nouveau_bios *bios = nouveau_bios(subdev); +- u8 strap = nvbios_ramcfg_strap(subdev); +- u32 xlat = 0x00000000; +- struct bit_entry bit_M; +- +- if (!bit_entry(bios, 'M', &bit_M)) { +- if (bit_M.version == 1 && bit_M.length >= 5) +- xlat = nv_ro16(bios, bit_M.offset + 3); +- if (bit_M.version == 2 && bit_M.length >= 3) +- xlat = nv_ro16(bios, bit_M.offset + 1); +- } +- +- if (xlat) +- strap = nv_ro08(bios, xlat + strap); +- return strap; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c +deleted file mode 100644 +index 585e6933..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c ++++ /dev/null +@@ -1,215 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-u32 +-nvbios_rammapTe(struct nouveau_bios *bios, u8 *ver, u8 *hdr, +- u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +-{ +- struct bit_entry bit_P; +- u16 rammap = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2) +- rammap = nv_ro16(bios, bit_P.offset + 4); +- +- if (rammap) { +- *ver = nv_ro08(bios, rammap + 0); +- switch (*ver) { +- case 0x10: +- case 0x11: +- *hdr = nv_ro08(bios, rammap + 1); +- *cnt = nv_ro08(bios, rammap + 5); +- *len = nv_ro08(bios, rammap + 2); +- *snr = nv_ro08(bios, rammap + 4); +- *ssz = nv_ro08(bios, rammap + 3); +- return rammap; +- default: +- break; +- } +- } +- } +- +- return 0x0000; +-} +- +-u32 +-nvbios_rammapEe(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u8 snr, ssz; +- u16 rammap = nvbios_rammapTe(bios, ver, hdr, cnt, len, &snr, &ssz); +- if (rammap && idx < *cnt) { +- rammap = rammap + *hdr + (idx * (*len + (snr * ssz))); +- *hdr = *len; +- *cnt = snr; +- *len = ssz; +- return rammap; +- } +- return 0x0000; +-} +- +-u32 +-nvbios_rammapEp(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ramcfg *p) +-{ +- u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len), temp; +- memset(p, 0x00, sizeof(*p)); +- p->rammap_ver = *ver; +- p->rammap_hdr = *hdr; +- switch (!!data * *ver) { +- case 0x10: +- p->rammap_min = nv_ro16(bios, data + 0x00); +- p->rammap_max = nv_ro16(bios, data + 0x02); +- p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1; +- p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3; +- break; +- case 0x11: +- p->rammap_min = nv_ro16(bios, data + 0x00); +- p->rammap_max = nv_ro16(bios, data + 0x02); +- p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; +- p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; +- p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; +- temp = nv_ro32(bios, data + 0x09); +- p->rammap_11_09_01ff = (temp & 0x000001ff) >> 0; +- p->rammap_11_0a_03fe = (temp & 0x0003fe00) >> 9; +- p->rammap_11_0a_0400 = (temp & 0x00040000) >> 18; +- p->rammap_11_0a_0800 = (temp & 0x00080000) >> 19; +- p->rammap_11_0b_01f0 = (temp & 0x01f00000) >> 20; +- p->rammap_11_0b_0200 = (temp & 0x02000000) >> 25; +- p->rammap_11_0b_0400 = (temp & 0x04000000) >> 26; +- p->rammap_11_0b_0800 = (temp & 0x08000000) >> 27; +- p->rammap_11_0d = nv_ro08(bios, data + 0x0d); +- p->rammap_11_0e = nv_ro08(bios, data + 0x0e); +- p->rammap_11_0f = nv_ro08(bios, data + 0x0f); +- p->rammap_11_11_0c = (nv_ro08(bios, data + 0x11) & 0x0c) >> 2; +- break; +- default: +- data = 0; +- break; +- } +- return data; +-} +- +-u32 +-nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ramcfg *info) +-{ +- int idx = 0; +- u32 data; +- while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) { +- if (mhz >= info->rammap_min && mhz <= info->rammap_max) +- break; +- } +- return data; +-} +- +-u32 +-nvbios_rammapSe(struct nouveau_bios *bios, u32 data, +- u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, +- u8 *ver, u8 *hdr) +-{ +- if (idx < ecnt) { +- data = data + ehdr + (idx * elen); +- *ver = ever; +- *hdr = elen; +- return data; +- } +- return 0; +-} +- +-u32 +-nvbios_rammapSp(struct nouveau_bios *bios, u32 data, +- u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, +- u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) +-{ +- data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); +- p->ramcfg_ver = *ver; +- p->ramcfg_hdr = *hdr; +- switch (!!data * *ver) { +- case 0x10: +- p->ramcfg_timing = nv_ro08(bios, data + 0x01); +- p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0; +- p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1; +- p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; +- p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; +- p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; +- p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5; +- p->ramcfg_10_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; +- p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; +- p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0; +- p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; +- p->ramcfg_10_07 = (nv_ro08(bios, data + 0x07) & 0xff) >> 0; +- p->ramcfg_10_08 = (nv_ro08(bios, data + 0x08) & 0xff) >> 0; +- p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0; +- p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4; +- break; +- case 0x11: +- p->ramcfg_timing = nv_ro08(bios, data + 0x00); +- p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; +- p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; +- p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; +- p->ramcfg_11_01_08 = (nv_ro08(bios, data + 0x01) & 0x08) >> 3; +- p->ramcfg_11_01_10 = (nv_ro08(bios, data + 0x01) & 0x10) >> 4; +- p->ramcfg_11_01_20 = (nv_ro08(bios, data + 0x01) & 0x20) >> 5; +- p->ramcfg_11_01_40 = (nv_ro08(bios, data + 0x01) & 0x40) >> 6; +- p->ramcfg_11_01_80 = (nv_ro08(bios, data + 0x01) & 0x80) >> 7; +- p->ramcfg_11_02_03 = (nv_ro08(bios, data + 0x02) & 0x03) >> 0; +- p->ramcfg_11_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2; +- p->ramcfg_11_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3; +- p->ramcfg_11_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4; +- p->ramcfg_11_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6; +- p->ramcfg_11_02_80 = (nv_ro08(bios, data + 0x02) & 0x80) >> 7; +- p->ramcfg_11_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0; +- p->ramcfg_11_03_30 = (nv_ro08(bios, data + 0x03) & 0x30) >> 4; +- p->ramcfg_11_03_c0 = (nv_ro08(bios, data + 0x03) & 0xc0) >> 6; +- p->ramcfg_11_03_f0 = (nv_ro08(bios, data + 0x03) & 0xf0) >> 4; +- p->ramcfg_11_04 = (nv_ro08(bios, data + 0x04) & 0xff) >> 0; +- p->ramcfg_11_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0; +- p->ramcfg_11_07_02 = (nv_ro08(bios, data + 0x07) & 0x02) >> 1; +- p->ramcfg_11_07_04 = (nv_ro08(bios, data + 0x07) & 0x04) >> 2; +- p->ramcfg_11_07_08 = (nv_ro08(bios, data + 0x07) & 0x08) >> 3; +- p->ramcfg_11_07_10 = (nv_ro08(bios, data + 0x07) & 0x10) >> 4; +- p->ramcfg_11_07_40 = (nv_ro08(bios, data + 0x07) & 0x40) >> 6; +- p->ramcfg_11_07_80 = (nv_ro08(bios, data + 0x07) & 0x80) >> 7; +- p->ramcfg_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; +- p->ramcfg_11_08_02 = (nv_ro08(bios, data + 0x08) & 0x02) >> 1; +- p->ramcfg_11_08_04 = (nv_ro08(bios, data + 0x08) & 0x04) >> 2; +- p->ramcfg_11_08_08 = (nv_ro08(bios, data + 0x08) & 0x08) >> 3; +- p->ramcfg_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; +- p->ramcfg_11_08_20 = (nv_ro08(bios, data + 0x08) & 0x20) >> 5; +- p->ramcfg_11_09 = (nv_ro08(bios, data + 0x09) & 0xff) >> 0; +- break; +- default: +- data = 0; +- break; +- } +- return data; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c b/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c +deleted file mode 100644 +index d1585409..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/therm.c ++++ /dev/null +@@ -1,215 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +-#include +- +-static u16 +-therm_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) +-{ +- struct bit_entry bit_P; +- u16 therm = 0; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 1) +- therm = nv_ro16(bios, bit_P.offset + 12); +- else if (bit_P.version == 2) +- therm = nv_ro16(bios, bit_P.offset + 16); +- else +- nv_error(bios, +- "unknown offset for thermal in BIT P %d\n", +- bit_P.version); +- } +- +- /* exit now if we haven't found the thermal table */ +- if (!therm) +- return 0x0000; +- +- *ver = nv_ro08(bios, therm + 0); +- *hdr = nv_ro08(bios, therm + 1); +- *len = nv_ro08(bios, therm + 2); +- *cnt = nv_ro08(bios, therm + 3); +- +- return therm + nv_ro08(bios, therm + 1); +-} +- +-static u16 +-nvbios_therm_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u16 therm = therm_table(bios, ver, &hdr, len, &cnt); +- if (therm && idx < cnt) +- return therm + idx * *len; +- return 0x0000; +-} +- +-int +-nvbios_therm_sensor_parse(struct nouveau_bios *bios, +- enum nvbios_therm_domain domain, +- struct nvbios_therm_sensor *sensor) +-{ +- s8 thrs_section, sensor_section, offset; +- u8 ver, len, i; +- u16 entry; +- +- /* we only support the core domain for now */ +- if (domain != NVBIOS_THERM_DOMAIN_CORE) +- return -EINVAL; +- +- /* Read the entries from the table */ +- thrs_section = 0; +- sensor_section = -1; +- i = 0; +- while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) { +- s16 value = nv_ro16(bios, entry + 1); +- +- switch (nv_ro08(bios, entry + 0)) { +- case 0x0: +- thrs_section = value; +- if (value > 0) +- return 0; /* we do not try to support ambient */ +- break; +- case 0x01: +- sensor_section++; +- if (sensor_section == 0) { +- offset = ((s8) nv_ro08(bios, entry + 2)) / 2; +- sensor->offset_constant = offset; +- } +- break; +- +- case 0x04: +- if (thrs_section == 0) { +- sensor->thrs_critical.temp = (value & 0xff0) >> 4; +- sensor->thrs_critical.hysteresis = value & 0xf; +- } +- break; +- +- case 0x07: +- if (thrs_section == 0) { +- sensor->thrs_down_clock.temp = (value & 0xff0) >> 4; +- sensor->thrs_down_clock.hysteresis = value & 0xf; +- } +- break; +- +- case 0x08: +- if (thrs_section == 0) { +- sensor->thrs_fan_boost.temp = (value & 0xff0) >> 4; +- sensor->thrs_fan_boost.hysteresis = value & 0xf; +- } +- break; +- +- case 0x10: +- if (sensor_section == 0) +- sensor->offset_num = value; +- break; +- +- case 0x11: +- if (sensor_section == 0) +- sensor->offset_den = value; +- break; +- +- case 0x12: +- if (sensor_section == 0) +- sensor->slope_mult = value; +- break; +- +- case 0x13: +- if (sensor_section == 0) +- sensor->slope_div = value; +- break; +- case 0x32: +- if (thrs_section == 0) { +- sensor->thrs_shutdown.temp = (value & 0xff0) >> 4; +- sensor->thrs_shutdown.hysteresis = value & 0xf; +- } +- break; +- } +- } +- +- return 0; +-} +- +-int +-nvbios_therm_fan_parse(struct nouveau_bios *bios, +- struct nvbios_therm_fan *fan) +-{ +- struct nouveau_therm_trip_point *cur_trip = NULL; +- u8 ver, len, i; +- u16 entry; +- +- uint8_t duty_lut[] = { 0, 0, 25, 0, 40, 0, 50, 0, +- 75, 0, 85, 0, 100, 0, 100, 0 }; +- +- i = 0; +- fan->nr_fan_trip = 0; +- fan->fan_mode = NVBIOS_THERM_FAN_OTHER; +- while ((entry = nvbios_therm_entry(bios, i++, &ver, &len))) { +- s16 value = nv_ro16(bios, entry + 1); +- +- switch (nv_ro08(bios, entry + 0)) { +- case 0x22: +- fan->min_duty = value & 0xff; +- fan->max_duty = (value & 0xff00) >> 8; +- break; +- case 0x24: +- fan->nr_fan_trip++; +- if (fan->fan_mode > NVBIOS_THERM_FAN_TRIP) +- fan->fan_mode = NVBIOS_THERM_FAN_TRIP; +- cur_trip = &fan->trip[fan->nr_fan_trip - 1]; +- cur_trip->hysteresis = value & 0xf; +- cur_trip->temp = (value & 0xff0) >> 4; +- cur_trip->fan_duty = duty_lut[(value & 0xf000) >> 12]; +- break; +- case 0x25: +- cur_trip = &fan->trip[fan->nr_fan_trip - 1]; +- cur_trip->fan_duty = value; +- break; +- case 0x26: +- if (!fan->pwm_freq) +- fan->pwm_freq = value; +- break; +- case 0x3b: +- fan->bump_period = value; +- break; +- case 0x3c: +- fan->slow_down_period = value; +- break; +- case 0x46: +- if (fan->fan_mode > NVBIOS_THERM_FAN_LINEAR) +- fan->fan_mode = NVBIOS_THERM_FAN_LINEAR; +- fan->linear_min_temp = nv_ro08(bios, entry + 1); +- fan->linear_max_temp = nv_ro08(bios, entry + 2); +- break; +- } +- } +- +- /* starting from fermi, fan management is always linear */ +- if (nv_device(bios)->card_type >= NV_C0 && +- fan->fan_mode == NVBIOS_THERM_FAN_OTHER) { +- fan->fan_mode = NVBIOS_THERM_FAN_LINEAR; +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +deleted file mode 100644 +index 46d955eb..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c ++++ /dev/null +@@ -1,135 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-u16 +-nvbios_timingTe(struct nouveau_bios *bios, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz) +-{ +- struct bit_entry bit_P; +- u16 timing = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 1) +- timing = nv_ro16(bios, bit_P.offset + 4); +- else +- if (bit_P.version == 2) +- timing = nv_ro16(bios, bit_P.offset + 8); +- +- if (timing) { +- *ver = nv_ro08(bios, timing + 0); +- switch (*ver) { +- case 0x10: +- *hdr = nv_ro08(bios, timing + 1); +- *cnt = nv_ro08(bios, timing + 2); +- *len = nv_ro08(bios, timing + 3); +- *snr = 0; +- *ssz = 0; +- return timing; +- case 0x20: +- *hdr = nv_ro08(bios, timing + 1); +- *cnt = nv_ro08(bios, timing + 5); +- *len = nv_ro08(bios, timing + 2); +- *snr = nv_ro08(bios, timing + 4); +- *ssz = nv_ro08(bios, timing + 3); +- return timing; +- default: +- break; +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_timingEe(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u8 snr, ssz; +- u16 timing = nvbios_timingTe(bios, ver, hdr, cnt, len, &snr, &ssz); +- if (timing && idx < *cnt) { +- timing += *hdr + idx * (*len + (snr * ssz)); +- *hdr = *len; +- *cnt = snr; +- *len = ssz; +- return timing; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_timingEp(struct nouveau_bios *bios, int idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_ramcfg *p) +-{ +- u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; +- p->timing_ver = *ver; +- p->timing_hdr = *hdr; +- switch (!!data * *ver) { +- case 0x10: +- p->timing_10_WR = nv_ro08(bios, data + 0x00); +- p->timing_10_CL = nv_ro08(bios, data + 0x02); +- p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07; +- p->timing_10_CWL = nv_ro08(bios, data + 0x13); +- break; +- case 0x20: +- p->timing[0] = nv_ro32(bios, data + 0x00); +- p->timing[1] = nv_ro32(bios, data + 0x04); +- p->timing[2] = nv_ro32(bios, data + 0x08); +- p->timing[3] = nv_ro32(bios, data + 0x0c); +- p->timing[4] = nv_ro32(bios, data + 0x10); +- p->timing[5] = nv_ro32(bios, data + 0x14); +- p->timing[6] = nv_ro32(bios, data + 0x18); +- p->timing[7] = nv_ro32(bios, data + 0x1c); +- p->timing[8] = nv_ro32(bios, data + 0x20); +- p->timing[9] = nv_ro32(bios, data + 0x24); +- p->timing[10] = nv_ro32(bios, data + 0x28); +- p->timing_20_2e_03 = (nv_ro08(bios, data + 0x2e) & 0x03) >> 0; +- p->timing_20_2e_30 = (nv_ro08(bios, data + 0x2e) & 0x30) >> 4; +- p->timing_20_2e_c0 = (nv_ro08(bios, data + 0x2e) & 0xc0) >> 6; +- p->timing_20_2f_03 = (nv_ro08(bios, data + 0x2f) & 0x03) >> 0; +- temp = nv_ro16(bios, data + 0x2c); +- p->timing_20_2c_003f = (temp & 0x003f) >> 0; +- p->timing_20_2c_1fc0 = (temp & 0x1fc0) >> 6; +- p->timing_20_30_07 = (nv_ro08(bios, data + 0x30) & 0x07) >> 0; +- p->timing_20_30_f8 = (nv_ro08(bios, data + 0x30) & 0xf8) >> 3; +- temp = nv_ro16(bios, data + 0x31); +- p->timing_20_31_0007 = (temp & 0x0007) >> 0; +- p->timing_20_31_0078 = (temp & 0x0078) >> 3; +- p->timing_20_31_0780 = (temp & 0x0780) >> 7; +- p->timing_20_31_0800 = (temp & 0x0800) >> 11; +- p->timing_20_31_7000 = (temp & 0x7000) >> 12; +- p->timing_20_31_8000 = (temp & 0x8000) >> 15; +- break; +- default: +- data = 0; +- break; +- } +- return data; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c +deleted file mode 100644 +index f343a1b0..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct bit_entry bit_P; +- u16 vmap = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2) { +- vmap = nv_ro16(bios, bit_P.offset + 0x20); +- if (vmap) { +- *ver = nv_ro08(bios, vmap + 0); +- switch (*ver) { +- case 0x10: +- case 0x20: +- *hdr = nv_ro08(bios, vmap + 1); +- *cnt = nv_ro08(bios, vmap + 3); +- *len = nv_ro08(bios, vmap + 2); +- return vmap; +- default: +- break; +- } +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_vmap *info) +-{ +- u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!vmap * *ver) { +- case 0x10: +- case 0x20: +- break; +- } +- return vmap; +-} +- +-u16 +-nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len); +- if (vmap && idx < cnt) { +- vmap = vmap + hdr + (idx * *len); +- return vmap; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, +- struct nvbios_vmap_entry *info) +-{ +- u16 vmap = nvbios_vmap_entry(bios, idx, ver, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!vmap * *ver) { +- case 0x10: +- info->link = 0xff; +- info->min = nv_ro32(bios, vmap + 0x00); +- info->max = nv_ro32(bios, vmap + 0x04); +- info->arg[0] = nv_ro32(bios, vmap + 0x08); +- info->arg[1] = nv_ro32(bios, vmap + 0x0c); +- info->arg[2] = nv_ro32(bios, vmap + 0x10); +- break; +- case 0x20: +- info->unk0 = nv_ro08(bios, vmap + 0x00); +- info->link = nv_ro08(bios, vmap + 0x01); +- info->min = nv_ro32(bios, vmap + 0x02); +- info->max = nv_ro32(bios, vmap + 0x06); +- info->arg[0] = nv_ro32(bios, vmap + 0x0a); +- info->arg[1] = nv_ro32(bios, vmap + 0x0e); +- info->arg[2] = nv_ro32(bios, vmap + 0x12); +- info->arg[3] = nv_ro32(bios, vmap + 0x16); +- info->arg[4] = nv_ro32(bios, vmap + 0x1a); +- info->arg[5] = nv_ro32(bios, vmap + 0x1e); +- break; +- } +- return vmap; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c +deleted file mode 100644 +index bb590de4..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/volt.c ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +-#include +- +-u16 +-nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- struct bit_entry bit_P; +- u16 volt = 0x0000; +- +- if (!bit_entry(bios, 'P', &bit_P)) { +- if (bit_P.version == 2) +- volt = nv_ro16(bios, bit_P.offset + 0x0c); +- else +- if (bit_P.version == 1) +- volt = nv_ro16(bios, bit_P.offset + 0x10); +- +- if (volt) { +- *ver = nv_ro08(bios, volt + 0); +- switch (*ver) { +- case 0x12: +- *hdr = 5; +- *cnt = nv_ro08(bios, volt + 2); +- *len = nv_ro08(bios, volt + 1); +- return volt; +- case 0x20: +- *hdr = nv_ro08(bios, volt + 1); +- *cnt = nv_ro08(bios, volt + 2); +- *len = nv_ro08(bios, volt + 3); +- return volt; +- case 0x30: +- case 0x40: +- case 0x50: +- *hdr = nv_ro08(bios, volt + 1); +- *cnt = nv_ro08(bios, volt + 3); +- *len = nv_ro08(bios, volt + 2); +- return volt; +- } +- } +- } +- +- return 0x0000; +-} +- +-u16 +-nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_volt *info) +-{ +- u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!volt * *ver) { +- case 0x12: +- info->vidmask = nv_ro08(bios, volt + 0x04); +- break; +- case 0x20: +- info->vidmask = nv_ro08(bios, volt + 0x05); +- break; +- case 0x30: +- info->vidmask = nv_ro08(bios, volt + 0x04); +- break; +- case 0x40: +- info->base = nv_ro32(bios, volt + 0x04); +- info->step = nv_ro16(bios, volt + 0x08); +- info->vidmask = nv_ro08(bios, volt + 0x0b); +- /*XXX*/ +- info->min = 0; +- info->max = info->base; +- break; +- case 0x50: +- info->vidmask = nv_ro08(bios, volt + 0x06); +- info->min = nv_ro32(bios, volt + 0x0a); +- info->max = nv_ro32(bios, volt + 0x0e); +- info->base = nv_ro32(bios, volt + 0x12) & 0x00ffffff; +- info->step = nv_ro16(bios, volt + 0x16); +- break; +- } +- return volt; +-} +- +-u16 +-nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len) +-{ +- u8 hdr, cnt; +- u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len); +- if (volt && idx < cnt) { +- volt = volt + hdr + (idx * *len); +- return volt; +- } +- return 0x0000; +-} +- +-u16 +-nvbios_volt_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len, +- struct nvbios_volt_entry *info) +-{ +- u16 volt = nvbios_volt_entry(bios, idx, ver, len); +- memset(info, 0x00, sizeof(*info)); +- switch (!!volt * *ver) { +- case 0x12: +- case 0x20: +- info->voltage = nv_ro08(bios, volt + 0x00) * 10000; +- info->vid = nv_ro08(bios, volt + 0x01); +- break; +- case 0x30: +- info->voltage = nv_ro08(bios, volt + 0x00) * 10000; +- info->vid = nv_ro08(bios, volt + 0x01) >> 2; +- break; +- case 0x40: +- case 0x50: +- break; +- } +- return volt; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c b/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c +deleted file mode 100644 +index e9b8e5d3..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bios/xpio.c ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-static u16 +-dcb_xpiod_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u16 data = dcb_gpio_table(bios, ver, hdr, cnt, len); +- if (data && *ver >= 0x40 && *hdr >= 0x06) { +- u16 xpio = nv_ro16(bios, data + 0x04); +- if (xpio) { +- *ver = nv_ro08(bios, data + 0x00); +- *hdr = nv_ro08(bios, data + 0x01); +- *cnt = nv_ro08(bios, data + 0x02); +- *len = nv_ro08(bios, data + 0x03); +- return xpio; +- } +- } +- return 0x0000; +-} +- +-u16 +-dcb_xpio_table(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len) +-{ +- u16 data = dcb_xpiod_table(bios, ver, hdr, cnt, len); +- if (data && idx < *cnt) { +- u16 xpio = nv_ro16(bios, data + *hdr + (idx * *len)); +- if (xpio) { +- *ver = nv_ro08(bios, data + 0x00); +- *hdr = nv_ro08(bios, data + 0x01); +- *cnt = nv_ro08(bios, data + 0x02); +- *len = nv_ro08(bios, data + 0x03); +- return xpio; +- } +- } +- return 0x0000; +-} +- +-u16 +-dcb_xpio_parse(struct nouveau_bios *bios, u8 idx, +- u8 *ver, u8 *hdr, u8 *cnt, u8 *len, +- struct nvbios_xpio *info) +-{ +- u16 data = dcb_xpio_table(bios, idx, ver, hdr, cnt, len); +- if (data && *len >= 6) { +- info->type = nv_ro08(bios, data + 0x04); +- info->addr = nv_ro08(bios, data + 0x05); +- info->flags = nv_ro08(bios, data + 0x06); +- } +- return 0x0000; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c +deleted file mode 100644 +index f757470e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c ++++ /dev/null +@@ -1,145 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-struct nouveau_hwsq { +- struct nouveau_bus *pbus; +- u32 addr; +- u32 data; +- struct { +- u8 data[512]; +- u8 size; +- } c; +-}; +- +-static void +-hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[]) +-{ +- memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0])); +- hwsq->c.size += size; +-} +- +-int +-nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq) +-{ +- struct nouveau_hwsq *hwsq; +- +- hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL); +- if (hwsq) { +- hwsq->pbus = pbus; +- hwsq->addr = ~0; +- hwsq->data = ~0; +- memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data)); +- hwsq->c.size = 0; +- } +- +- return hwsq ? 0 : -ENOMEM; +-} +- +-int +-nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec) +-{ +- struct nouveau_hwsq *hwsq = *phwsq; +- int ret = 0, i; +- if (hwsq) { +- struct nouveau_bus *pbus = hwsq->pbus; +- hwsq->c.size = (hwsq->c.size + 4) / 4; +- if (hwsq->c.size <= pbus->hwsq_size) { +- if (exec) +- ret = pbus->hwsq_exec(pbus, (u32 *)hwsq->c.data, +- hwsq->c.size); +- if (ret) +- nv_error(pbus, "hwsq exec failed: %d\n", ret); +- } else { +- nv_error(pbus, "hwsq ucode too large\n"); +- ret = -ENOSPC; +- } +- +- for (i = 0; ret && i < hwsq->c.size; i++) +- nv_error(pbus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]); +- +- *phwsq = NULL; +- kfree(hwsq); +- } +- return ret; +-} +- +-void +-nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data) +-{ +- nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data); +- +- if (hwsq->data != data) { +- if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) { +- hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8, +- data >> 16, data >> 24 }); +- } else { +- hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 }); +- } +- } +- +- if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) { +- hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8, +- addr >> 16, addr >> 24 }); +- } else { +- hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 }); +- } +- +- hwsq->addr = addr; +- hwsq->data = data; +-} +- +-void +-nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data) +-{ +- nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data); +- flag += 0x80; +- if (data >= 0) +- flag += 0x20; +- if (data >= 1) +- flag += 0x20; +- hwsq_cmd(hwsq, 1, (u8[]){ flag }); +-} +- +-void +-nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data) +-{ +- nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data); +- hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data }); +-} +- +-void +-nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec) +-{ +- u8 shift = 0, usec = nsec / 1000; +- while (usec & ~3) { +- usec >>= 2; +- shift++; +- } +- +- nv_debug(hwsq->pbus, " DELAY = %d ns\n", nsec); +- hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec }); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h +deleted file mode 100644 +index 12176f9c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h ++++ /dev/null +@@ -1,113 +0,0 @@ +-#ifndef __NVKM_BUS_HWSQ_H__ +-#define __NVKM_BUS_HWSQ_H__ +- +-#include +- +-struct hwsq { +- struct nouveau_subdev *subdev; +- struct nouveau_hwsq *hwsq; +- int sequence; +-}; +- +-struct hwsq_reg { +- int sequence; +- bool force; +- u32 addr[2]; +- u32 data; +-}; +- +-static inline struct hwsq_reg +-hwsq_reg2(u32 addr1, u32 addr2) +-{ +- return (struct hwsq_reg) { +- .sequence = 0, +- .force = 0, +- .addr = { addr1, addr2 }, +- .data = 0xdeadbeef, +- }; +-} +- +-static inline struct hwsq_reg +-hwsq_reg(u32 addr) +-{ +- return hwsq_reg2(addr, addr); +-} +- +-static inline int +-hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev) +-{ +- struct nouveau_bus *pbus = nouveau_bus(subdev); +- int ret; +- +- ret = nouveau_hwsq_init(pbus, &ram->hwsq); +- if (ret) +- return ret; +- +- ram->sequence++; +- ram->subdev = subdev; +- return 0; +-} +- +-static inline int +-hwsq_exec(struct hwsq *ram, bool exec) +-{ +- int ret = 0; +- if (ram->subdev) { +- ret = nouveau_hwsq_fini(&ram->hwsq, exec); +- ram->subdev = NULL; +- } +- return ret; +-} +- +-static inline u32 +-hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg) +-{ +- if (reg->sequence != ram->sequence) +- reg->data = nv_rd32(ram->subdev, reg->addr[0]); +- return reg->data; +-} +- +-static inline void +-hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data) +-{ +- reg->sequence = ram->sequence; +- reg->data = data; +- if (reg->addr[0] != reg->addr[1]) +- nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data); +- nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data); +-} +- +-static inline void +-hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg) +-{ +- reg->force = true; +-} +- +-static inline u32 +-hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data) +-{ +- u32 temp = hwsq_rd32(ram, reg); +- if (temp != ((temp & ~mask) | data) || reg->force) +- hwsq_wr32(ram, reg, (temp & ~mask) | data); +- return temp; +-} +- +-static inline void +-hwsq_setf(struct hwsq *ram, u8 flag, int data) +-{ +- nouveau_hwsq_setf(ram->hwsq, flag, data); +-} +- +-static inline void +-hwsq_wait(struct hwsq *ram, u8 flag, u8 data) +-{ +- nouveau_hwsq_wait(ram->hwsq, flag, data); +-} +- +-static inline void +-hwsq_nsec(struct hwsq *ram, u32 nsec) +-{ +- nouveau_hwsq_nsec(ram->hwsq, nsec); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c +deleted file mode 100644 +index 23921b53..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- * Ben Skeggs +- */ +- +-#include "nv04.h" +- +-static void +-nv04_bus_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_bus *pbus = nouveau_bus(subdev); +- u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); +- +- if (stat & 0x00000001) { +- nv_error(pbus, "BUS ERROR\n"); +- stat &= ~0x00000001; +- nv_wr32(pbus, 0x001100, 0x00000001); +- } +- +- if (stat & 0x00000110) { +- subdev = nouveau_subdev(subdev, NVDEV_SUBDEV_GPIO); +- if (subdev && subdev->intr) +- subdev->intr(subdev); +- stat &= ~0x00000110; +- nv_wr32(pbus, 0x001100, 0x00000110); +- } +- +- if (stat) { +- nv_error(pbus, "unknown intr 0x%08x\n", stat); +- nv_mask(pbus, 0x001140, stat, 0x00000000); +- } +-} +- +-static int +-nv04_bus_init(struct nouveau_object *object) +-{ +- struct nv04_bus_priv *priv = (void *)object; +- +- nv_wr32(priv, 0x001100, 0xffffffff); +- nv_wr32(priv, 0x001140, 0x00000111); +- +- return nouveau_bus_init(&priv->base); +-} +- +-int +-nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_bus_impl *impl = (void *)oclass; +- struct nv04_bus_priv *priv; +- int ret; +- +- ret = nouveau_bus_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->intr = impl->intr; +- priv->base.hwsq_exec = impl->hwsq_exec; +- priv->base.hwsq_size = impl->hwsq_size; +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_bus_oclass = &(struct nv04_bus_impl) { +- .base.handle = NV_SUBDEV(BUS, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_bus_ctor, +- .dtor = _nouveau_bus_dtor, +- .init = nv04_bus_init, +- .fini = _nouveau_bus_fini, +- }, +- .intr = nv04_bus_intr, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h +deleted file mode 100644 +index 4d760245..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-#ifndef __NVKM_BUS_NV04_H__ +-#define __NVKM_BUS_NV04_H__ +- +-#include +- +-struct nv04_bus_priv { +- struct nouveau_bus base; +-}; +- +-int nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-int nv50_bus_init(struct nouveau_object *); +-void nv50_bus_intr(struct nouveau_subdev *); +- +-struct nv04_bus_impl { +- struct nouveau_oclass base; +- void (*intr)(struct nouveau_subdev *); +- int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32); +- u32 hwsq_size; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c +deleted file mode 100644 +index 94da46f6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- * Ben Skeggs +- */ +- +-#include "nv04.h" +- +-static void +-nv31_bus_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_bus *pbus = nouveau_bus(subdev); +- u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); +- u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144); +- +- if (gpio) { +- subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_GPIO); +- if (subdev && subdev->intr) +- subdev->intr(subdev); +- } +- +- if (stat & 0x00000008) { /* NV41- */ +- u32 addr = nv_rd32(pbus, 0x009084); +- u32 data = nv_rd32(pbus, 0x009088); +- +- nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n", +- (addr & 0x00000002) ? "write" : "read", data, +- (addr & 0x00fffffc)); +- +- stat &= ~0x00000008; +- nv_wr32(pbus, 0x001100, 0x00000008); +- } +- +- if (stat & 0x00070000) { +- subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM); +- if (subdev && subdev->intr) +- subdev->intr(subdev); +- stat &= ~0x00070000; +- nv_wr32(pbus, 0x001100, 0x00070000); +- } +- +- if (stat) { +- nv_error(pbus, "unknown intr 0x%08x\n", stat); +- nv_mask(pbus, 0x001140, stat, 0x00000000); +- } +-} +- +-static int +-nv31_bus_init(struct nouveau_object *object) +-{ +- struct nv04_bus_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_bus_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x001100, 0xffffffff); +- nv_wr32(priv, 0x001140, 0x00070008); +- return 0; +-} +- +-struct nouveau_oclass * +-nv31_bus_oclass = &(struct nv04_bus_impl) { +- .base.handle = NV_SUBDEV(BUS, 0x31), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_bus_ctor, +- .dtor = _nouveau_bus_dtor, +- .init = nv31_bus_init, +- .fini = _nouveau_bus_fini, +- }, +- .intr = nv31_bus_intr, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c +deleted file mode 100644 +index 11918f7e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- * Ben Skeggs +- */ +- +-#include +- +-#include "nv04.h" +- +-static int +-nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size) +-{ +- struct nv50_bus_priv *priv = (void *)pbus; +- int i; +- +- nv_mask(pbus, 0x001098, 0x00000008, 0x00000000); +- nv_wr32(pbus, 0x001304, 0x00000000); +- for (i = 0; i < size; i++) +- nv_wr32(priv, 0x001400 + (i * 4), data[i]); +- nv_mask(pbus, 0x001098, 0x00000018, 0x00000018); +- nv_wr32(pbus, 0x00130c, 0x00000003); +- +- return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT; +-} +- +-void +-nv50_bus_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_bus *pbus = nouveau_bus(subdev); +- u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); +- +- if (stat & 0x00000008) { +- u32 addr = nv_rd32(pbus, 0x009084); +- u32 data = nv_rd32(pbus, 0x009088); +- +- nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n", +- (addr & 0x00000002) ? "write" : "read", data, +- (addr & 0x00fffffc)); +- +- stat &= ~0x00000008; +- nv_wr32(pbus, 0x001100, 0x00000008); +- } +- +- if (stat & 0x00010000) { +- subdev = nouveau_subdev(pbus, NVDEV_SUBDEV_THERM); +- if (subdev && subdev->intr) +- subdev->intr(subdev); +- stat &= ~0x00010000; +- nv_wr32(pbus, 0x001100, 0x00010000); +- } +- +- if (stat) { +- nv_error(pbus, "unknown intr 0x%08x\n", stat); +- nv_mask(pbus, 0x001140, stat, 0); +- } +-} +- +-int +-nv50_bus_init(struct nouveau_object *object) +-{ +- struct nv04_bus_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_bus_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x001100, 0xffffffff); +- nv_wr32(priv, 0x001140, 0x00010008); +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_bus_oclass = &(struct nv04_bus_impl) { +- .base.handle = NV_SUBDEV(BUS, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_bus_ctor, +- .dtor = _nouveau_bus_dtor, +- .init = nv50_bus_init, +- .fini = _nouveau_bus_fini, +- }, +- .intr = nv50_bus_intr, +- .hwsq_exec = nv50_bus_hwsq_exec, +- .hwsq_size = 64, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c +deleted file mode 100644 +index d3659055..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- * Ben Skeggs +- */ +- +-#include +- +-#include "nv04.h" +- +-static int +-nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size) +-{ +- struct nv50_bus_priv *priv = (void *)pbus; +- int i; +- +- nv_mask(pbus, 0x001098, 0x00000008, 0x00000000); +- nv_wr32(pbus, 0x001304, 0x00000000); +- nv_wr32(pbus, 0x001318, 0x00000000); +- for (i = 0; i < size; i++) +- nv_wr32(priv, 0x080000 + (i * 4), data[i]); +- nv_mask(pbus, 0x001098, 0x00000018, 0x00000018); +- nv_wr32(pbus, 0x00130c, 0x00000001); +- +- return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT; +-} +- +-struct nouveau_oclass * +-nv94_bus_oclass = &(struct nv04_bus_impl) { +- .base.handle = NV_SUBDEV(BUS, 0x94), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_bus_ctor, +- .dtor = _nouveau_bus_dtor, +- .init = nv50_bus_init, +- .fini = _nouveau_bus_fini, +- }, +- .intr = nv50_bus_intr, +- .hwsq_exec = nv94_bus_hwsq_exec, +- .hwsq_size = 128, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c +deleted file mode 100644 +index 73839d71..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c ++++ /dev/null +@@ -1,81 +0,0 @@ +-/* +- * Copyright 2012 Nouveau Community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- * Ben Skeggs +- */ +- +-#include "nv04.h" +- +-static void +-nvc0_bus_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_bus *pbus = nouveau_bus(subdev); +- u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140); +- +- if (stat & 0x0000000e) { +- u32 addr = nv_rd32(pbus, 0x009084); +- u32 data = nv_rd32(pbus, 0x009088); +- +- nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n", +- (addr & 0x00000002) ? "write" : "read", data, +- (addr & 0x00fffffc), +- (stat & 0x00000002) ? "!ENGINE " : "", +- (stat & 0x00000004) ? "IBUS " : "", +- (stat & 0x00000008) ? "TIMEOUT " : ""); +- +- nv_wr32(pbus, 0x009084, 0x00000000); +- nv_wr32(pbus, 0x001100, (stat & 0x0000000e)); +- stat &= ~0x0000000e; +- } +- +- if (stat) { +- nv_error(pbus, "unknown intr 0x%08x\n", stat); +- nv_mask(pbus, 0x001140, stat, 0x00000000); +- } +-} +- +-static int +-nvc0_bus_init(struct nouveau_object *object) +-{ +- struct nv04_bus_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_bus_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x001100, 0xffffffff); +- nv_wr32(priv, 0x001140, 0x0000000e); +- return 0; +-} +- +-struct nouveau_oclass * +-nvc0_bus_oclass = &(struct nv04_bus_impl) { +- .base.handle = NV_SUBDEV(BUS, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_bus_ctor, +- .dtor = _nouveau_bus_dtor, +- .init = nvc0_bus_init, +- .fini = _nouveau_bus_fini, +- }, +- .intr = nvc0_bus_intr, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c b/drivers/gpu/drm/nouveau/core/subdev/clock/base.c +deleted file mode 100644 +index e51b72d4..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/base.c ++++ /dev/null +@@ -1,597 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-/****************************************************************************** +- * misc +- *****************************************************************************/ +-static u32 +-nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust, +- u8 pstate, u8 domain, u32 input) +-{ +- struct nouveau_bios *bios = nouveau_bios(clk); +- struct nvbios_boostE boostE; +- u8 ver, hdr, cnt, len; +- u16 data; +- +- data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE); +- if (data) { +- struct nvbios_boostS boostS; +- u8 idx = 0, sver, shdr; +- u16 subd; +- +- input = max(boostE.min, input); +- input = min(boostE.max, input); +- do { +- sver = ver; +- shdr = hdr; +- subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr, +- cnt, len, &boostS); +- if (subd && boostS.domain == domain) { +- if (adjust) +- input = input * boostS.percent / 100; +- input = max(boostS.min, input); +- input = min(boostS.max, input); +- break; +- } +- } while (subd); +- } +- +- return input; +-} +- +-/****************************************************************************** +- * C-States +- *****************************************************************************/ +-static int +-nouveau_cstate_prog(struct nouveau_clock *clk, +- struct nouveau_pstate *pstate, int cstatei) +-{ +- struct nouveau_therm *ptherm = nouveau_therm(clk); +- struct nouveau_volt *volt = nouveau_volt(clk); +- struct nouveau_cstate *cstate; +- int ret; +- +- if (!list_empty(&pstate->list)) { +- cstate = list_entry(pstate->list.prev, typeof(*cstate), head); +- } else { +- cstate = &pstate->base; +- } +- +- if (ptherm) { +- ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1); +- if (ret && ret != -ENODEV) { +- nv_error(clk, "failed to raise fan speed: %d\n", ret); +- return ret; +- } +- } +- +- if (volt) { +- ret = volt->set_id(volt, cstate->voltage, +1); +- if (ret && ret != -ENODEV) { +- nv_error(clk, "failed to raise voltage: %d\n", ret); +- return ret; +- } +- } +- +- ret = clk->calc(clk, cstate); +- if (ret == 0) { +- ret = clk->prog(clk); +- clk->tidy(clk); +- } +- +- if (volt) { +- ret = volt->set_id(volt, cstate->voltage, -1); +- if (ret && ret != -ENODEV) +- nv_error(clk, "failed to lower voltage: %d\n", ret); +- } +- +- if (ptherm) { +- ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1); +- if (ret && ret != -ENODEV) +- nv_error(clk, "failed to lower fan speed: %d\n", ret); +- } +- +- return 0; +-} +- +-static void +-nouveau_cstate_del(struct nouveau_cstate *cstate) +-{ +- list_del(&cstate->head); +- kfree(cstate); +-} +- +-static int +-nouveau_cstate_new(struct nouveau_clock *clk, int idx, +- struct nouveau_pstate *pstate) +-{ +- struct nouveau_bios *bios = nouveau_bios(clk); +- struct nouveau_clocks *domain = clk->domains; +- struct nouveau_cstate *cstate = NULL; +- struct nvbios_cstepX cstepX; +- u8 ver, hdr; +- u16 data; +- +- data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX); +- if (!data) +- return -ENOENT; +- +- cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); +- if (!cstate) +- return -ENOMEM; +- +- *cstate = pstate->base; +- cstate->voltage = cstepX.voltage; +- +- while (domain && domain->name != nv_clk_src_max) { +- if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { +- u32 freq = nouveau_clock_adjust(clk, true, +- pstate->pstate, +- domain->bios, +- cstepX.freq); +- cstate->domain[domain->name] = freq; +- } +- domain++; +- } +- +- list_add(&cstate->head, &pstate->list); +- return 0; +-} +- +-/****************************************************************************** +- * P-States +- *****************************************************************************/ +-static int +-nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei) +-{ +- struct nouveau_fb *pfb = nouveau_fb(clk); +- struct nouveau_pstate *pstate; +- int ret, idx = 0; +- +- list_for_each_entry(pstate, &clk->states, head) { +- if (idx++ == pstatei) +- break; +- } +- +- nv_debug(clk, "setting performance state %d\n", pstatei); +- clk->pstate = pstatei; +- +- if (pfb->ram->calc) { +- int khz = pstate->base.domain[nv_clk_src_mem]; +- do { +- ret = pfb->ram->calc(pfb, khz); +- if (ret == 0) +- ret = pfb->ram->prog(pfb); +- } while (ret > 0); +- pfb->ram->tidy(pfb); +- } +- +- return nouveau_cstate_prog(clk, pstate, 0); +-} +- +-static void +-nouveau_pstate_work(struct work_struct *work) +-{ +- struct nouveau_clock *clk = container_of(work, typeof(*clk), work); +- int pstate; +- +- if (!atomic_xchg(&clk->waiting, 0)) +- return; +- clk->pwrsrc = power_supply_is_system_supplied(); +- +- nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n", +- clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, +- clk->astate, clk->tstate, clk->dstate); +- +- pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; +- if (clk->state_nr && pstate != -1) { +- pstate = (pstate < 0) ? clk->astate : pstate; +- pstate = min(pstate, clk->state_nr - 1 - clk->tstate); +- pstate = max(pstate, clk->dstate); +- } else { +- pstate = clk->pstate = -1; +- } +- +- nv_trace(clk, "-> %d\n", pstate); +- if (pstate != clk->pstate) { +- int ret = nouveau_pstate_prog(clk, pstate); +- if (ret) { +- nv_error(clk, "error setting pstate %d: %d\n", +- pstate, ret); +- } +- } +- +- wake_up_all(&clk->wait); +- nvkm_notify_get(&clk->pwrsrc_ntfy); +-} +- +-static int +-nouveau_pstate_calc(struct nouveau_clock *clk, bool wait) +-{ +- atomic_set(&clk->waiting, 1); +- schedule_work(&clk->work); +- if (wait) +- wait_event(clk->wait, !atomic_read(&clk->waiting)); +- return 0; +-} +- +-static void +-nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate) +-{ +- struct nouveau_clocks *clock = clk->domains - 1; +- struct nouveau_cstate *cstate; +- char info[3][32] = { "", "", "" }; +- char name[4] = "--"; +- int i = -1; +- +- if (pstate->pstate != 0xff) +- snprintf(name, sizeof(name), "%02x", pstate->pstate); +- +- while ((++clock)->name != nv_clk_src_max) { +- u32 lo = pstate->base.domain[clock->name]; +- u32 hi = lo; +- if (hi == 0) +- continue; +- +- nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo); +- list_for_each_entry(cstate, &pstate->list, head) { +- u32 freq = cstate->domain[clock->name]; +- lo = min(lo, freq); +- hi = max(hi, freq); +- nv_debug(clk, "%10d KHz\n", freq); +- } +- +- if (clock->mname && ++i < ARRAY_SIZE(info)) { +- lo /= clock->mdiv; +- hi /= clock->mdiv; +- if (lo == hi) { +- snprintf(info[i], sizeof(info[i]), "%s %d MHz", +- clock->mname, lo); +- } else { +- snprintf(info[i], sizeof(info[i]), +- "%s %d-%d MHz", clock->mname, lo, hi); +- } +- } +- } +- +- nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]); +-} +- +-static void +-nouveau_pstate_del(struct nouveau_pstate *pstate) +-{ +- struct nouveau_cstate *cstate, *temp; +- +- list_for_each_entry_safe(cstate, temp, &pstate->list, head) { +- nouveau_cstate_del(cstate); +- } +- +- list_del(&pstate->head); +- kfree(pstate); +-} +- +-static int +-nouveau_pstate_new(struct nouveau_clock *clk, int idx) +-{ +- struct nouveau_bios *bios = nouveau_bios(clk); +- struct nouveau_clocks *domain = clk->domains - 1; +- struct nouveau_pstate *pstate; +- struct nouveau_cstate *cstate; +- struct nvbios_cstepE cstepE; +- struct nvbios_perfE perfE; +- u8 ver, hdr, cnt, len; +- u16 data; +- +- data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE); +- if (!data) +- return -EINVAL; +- if (perfE.pstate == 0xff) +- return 0; +- +- pstate = kzalloc(sizeof(*pstate), GFP_KERNEL); +- cstate = &pstate->base; +- if (!pstate) +- return -ENOMEM; +- +- INIT_LIST_HEAD(&pstate->list); +- +- pstate->pstate = perfE.pstate; +- pstate->fanspeed = perfE.fanspeed; +- cstate->voltage = perfE.voltage; +- cstate->domain[nv_clk_src_core] = perfE.core; +- cstate->domain[nv_clk_src_shader] = perfE.shader; +- cstate->domain[nv_clk_src_mem] = perfE.memory; +- cstate->domain[nv_clk_src_vdec] = perfE.vdec; +- cstate->domain[nv_clk_src_dom6] = perfE.disp; +- +- while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) { +- struct nvbios_perfS perfS; +- u8 sver = ver, shdr = hdr; +- u32 perfSe = nvbios_perfSp(bios, data, domain->bios, +- &sver, &shdr, cnt, len, &perfS); +- if (perfSe == 0 || sver != 0x40) +- continue; +- +- if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) { +- perfS.v40.freq = nouveau_clock_adjust(clk, false, +- pstate->pstate, +- domain->bios, +- perfS.v40.freq); +- } +- +- cstate->domain[domain->name] = perfS.v40.freq; +- } +- +- data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE); +- if (data) { +- int idx = cstepE.index; +- do { +- nouveau_cstate_new(clk, idx, pstate); +- } while(idx--); +- } +- +- nouveau_pstate_info(clk, pstate); +- list_add_tail(&pstate->head, &clk->states); +- clk->state_nr++; +- return 0; +-} +- +-/****************************************************************************** +- * Adjustment triggers +- *****************************************************************************/ +-static int +-nouveau_clock_ustate_update(struct nouveau_clock *clk, int req) +-{ +- struct nouveau_pstate *pstate; +- int i = 0; +- +- if (!clk->allow_reclock) +- return -ENOSYS; +- +- if (req != -1 && req != -2) { +- list_for_each_entry(pstate, &clk->states, head) { +- if (pstate->pstate == req) +- break; +- i++; +- } +- +- if (pstate->pstate != req) +- return -EINVAL; +- req = i; +- } +- +- return req + 2; +-} +- +-static int +-nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen) +-{ +- int ret = 1; +- +- if (strncasecmpz(mode, "disabled", arglen)) { +- char save = mode[arglen]; +- long v; +- +- ((char *)mode)[arglen] = '\0'; +- if (!kstrtol(mode, 0, &v)) { +- ret = nouveau_clock_ustate_update(clk, v); +- if (ret < 0) +- ret = 1; +- } +- ((char *)mode)[arglen] = save; +- } +- +- return ret - 2; +-} +- +-int +-nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr) +-{ +- int ret = nouveau_clock_ustate_update(clk, req); +- if (ret >= 0) { +- if (ret -= 2, pwr) clk->ustate_ac = ret; +- else clk->ustate_dc = ret; +- return nouveau_pstate_calc(clk, true); +- } +- return ret; +-} +- +-int +-nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel) +-{ +- if (!rel) clk->astate = req; +- if ( rel) clk->astate += rel; +- clk->astate = min(clk->astate, clk->state_nr - 1); +- clk->astate = max(clk->astate, 0); +- return nouveau_pstate_calc(clk, true); +-} +- +-int +-nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel) +-{ +- if (!rel) clk->tstate = req; +- if ( rel) clk->tstate += rel; +- clk->tstate = min(clk->tstate, 0); +- clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); +- return nouveau_pstate_calc(clk, true); +-} +- +-int +-nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel) +-{ +- if (!rel) clk->dstate = req; +- if ( rel) clk->dstate += rel; +- clk->dstate = min(clk->dstate, clk->state_nr - 1); +- clk->dstate = max(clk->dstate, 0); +- return nouveau_pstate_calc(clk, true); +-} +- +-static int +-nouveau_clock_pwrsrc(struct nvkm_notify *notify) +-{ +- struct nouveau_clock *clk = +- container_of(notify, typeof(*clk), pwrsrc_ntfy); +- nouveau_pstate_calc(clk, false); +- return NVKM_NOTIFY_DROP; +-} +- +-/****************************************************************************** +- * subdev base class implementation +- *****************************************************************************/ +- +-int +-_nouveau_clock_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_clock *clk = (void *)object; +- nvkm_notify_put(&clk->pwrsrc_ntfy); +- return nouveau_subdev_fini(&clk->base, suspend); +-} +- +-int +-_nouveau_clock_init(struct nouveau_object *object) +-{ +- struct nouveau_clock *clk = (void *)object; +- struct nouveau_clocks *clock = clk->domains; +- int ret; +- +- ret = nouveau_subdev_init(&clk->base); +- if (ret) +- return ret; +- +- memset(&clk->bstate, 0x00, sizeof(clk->bstate)); +- INIT_LIST_HEAD(&clk->bstate.list); +- clk->bstate.pstate = 0xff; +- +- while (clock->name != nv_clk_src_max) { +- ret = clk->read(clk, clock->name); +- if (ret < 0) { +- nv_error(clk, "%02x freq unknown\n", clock->name); +- return ret; +- } +- clk->bstate.base.domain[clock->name] = ret; +- clock++; +- } +- +- nouveau_pstate_info(clk, &clk->bstate); +- +- clk->astate = clk->state_nr - 1; +- clk->tstate = 0; +- clk->dstate = 0; +- clk->pstate = -1; +- nouveau_pstate_calc(clk, true); +- return 0; +-} +- +-void +-_nouveau_clock_dtor(struct nouveau_object *object) +-{ +- struct nouveau_clock *clk = (void *)object; +- struct nouveau_pstate *pstate, *temp; +- +- nvkm_notify_fini(&clk->pwrsrc_ntfy); +- +- list_for_each_entry_safe(pstate, temp, &clk->states, head) { +- nouveau_pstate_del(pstate); +- } +- +- nouveau_subdev_destroy(&clk->base); +-} +- +-int +-nouveau_clock_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- struct nouveau_clocks *clocks, +- struct nouveau_pstate *pstates, int nb_pstates, +- bool allow_reclock, +- int length, void **object) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_clock *clk; +- int ret, idx, arglen; +- const char *mode; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK", +- "clock", length, object); +- clk = *object; +- if (ret) +- return ret; +- +- INIT_LIST_HEAD(&clk->states); +- clk->domains = clocks; +- clk->ustate_ac = -1; +- clk->ustate_dc = -1; +- +- INIT_WORK(&clk->work, nouveau_pstate_work); +- init_waitqueue_head(&clk->wait); +- atomic_set(&clk->waiting, 0); +- +- /* If no pstates are provided, try and fetch them from the BIOS */ +- if (!pstates) { +- idx = 0; +- do { +- ret = nouveau_pstate_new(clk, idx++); +- } while (ret == 0); +- } else { +- for (idx = 0; idx < nb_pstates; idx++) +- list_add_tail(&pstates[idx].head, &clk->states); +- clk->state_nr = nb_pstates; +- } +- +- clk->allow_reclock = allow_reclock; +- +- ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true, +- NULL, 0, 0, &clk->pwrsrc_ntfy); +- if (ret) +- return ret; +- +- mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen); +- if (mode) { +- clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); +- clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); +- } +- +- mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen); +- if (mode) +- clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen); +- +- mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen); +- if (mode) +- clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen); +- +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c +deleted file mode 100644 +index 425a8d5e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c ++++ /dev/null +@@ -1,665 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- * +- * Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c +- * +- */ +- +-#define MHZ (1000 * 1000) +- +-#define MASK(w) ((1 << w) - 1) +- +-#define SYS_GPCPLL_CFG_BASE 0x00137000 +-#define GPC_BCASE_GPCPLL_CFG_BASE 0x00132800 +- +-#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0) +-#define GPCPLL_CFG_ENABLE BIT(0) +-#define GPCPLL_CFG_IDDQ BIT(1) +-#define GPCPLL_CFG_LOCK_DET_OFF BIT(4) +-#define GPCPLL_CFG_LOCK BIT(17) +- +-#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4) +-#define GPCPLL_COEFF_M_SHIFT 0 +-#define GPCPLL_COEFF_M_WIDTH 8 +-#define GPCPLL_COEFF_N_SHIFT 8 +-#define GPCPLL_COEFF_N_WIDTH 8 +-#define GPCPLL_COEFF_P_SHIFT 16 +-#define GPCPLL_COEFF_P_WIDTH 6 +- +-#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc) +-#define GPCPLL_CFG2_SETUP2_SHIFT 16 +-#define GPCPLL_CFG2_PLL_STEPA_SHIFT 24 +- +-#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18) +-#define GPCPLL_CFG3_PLL_STEPB_SHIFT 16 +- +-#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c) +-#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 0 +-#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 8 +-#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 16 +-#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 22 +-#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 31 +- +-#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100) +-#define SEL_VCO_GPC2CLK_OUT_SHIFT 0 +- +-#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250) +-#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 1 +-#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 31 +-#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 1 +-#define GPC2CLK_OUT_VCODIV_WIDTH 6 +-#define GPC2CLK_OUT_VCODIV_SHIFT 8 +-#define GPC2CLK_OUT_VCODIV1 0 +-#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \ +- GPC2CLK_OUT_VCODIV_SHIFT) +-#define GPC2CLK_OUT_BYPDIV_WIDTH 6 +-#define GPC2CLK_OUT_BYPDIV_SHIFT 0 +-#define GPC2CLK_OUT_BYPDIV31 0x3c +-#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \ +- GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\ +- | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\ +- | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT)) +-#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \ +- GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \ +- | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \ +- | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT)) +- +-#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCASE_GPCPLL_CFG_BASE + 0xa0) +-#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 24 +-#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \ +- (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT) +- +-#include +-#include +- +-#ifdef __KERNEL__ +-#include +-#endif +- +-static const u8 pl_to_div[] = { +-/* PL: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 */ +-/* p: */ 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 12, 16, 20, 24, 32, +-}; +- +-/* All frequencies in Mhz */ +-struct gk20a_clk_pllg_params { +- u32 min_vco, max_vco; +- u32 min_u, max_u; +- u32 min_m, max_m; +- u32 min_n, max_n; +- u32 min_pl, max_pl; +-}; +- +-static const struct gk20a_clk_pllg_params gk20a_pllg_params = { +- .min_vco = 1000, .max_vco = 1700, +- .min_u = 12, .max_u = 38, +- .min_m = 1, .max_m = 255, +- .min_n = 8, .max_n = 255, +- .min_pl = 1, .max_pl = 32, +-}; +- +-struct gk20a_clock_priv { +- struct nouveau_clock base; +- const struct gk20a_clk_pllg_params *params; +- u32 m, n, pl; +- u32 parent_rate; +-}; +-#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base) +- +-static void +-gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv) +-{ +- u32 val; +- +- val = nv_rd32(priv, GPCPLL_COEFF); +- priv->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); +- priv->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); +- priv->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); +-} +- +-static u32 +-gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv) +-{ +- u32 rate; +- u32 divider; +- +- rate = priv->parent_rate * priv->n; +- divider = priv->m * pl_to_div[priv->pl]; +- do_div(rate, divider); +- +- return rate / 2; +-} +- +-static int +-gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate) +-{ +- u32 target_clk_f, ref_clk_f, target_freq; +- u32 min_vco_f, max_vco_f; +- u32 low_pl, high_pl, best_pl; +- u32 target_vco_f, vco_f; +- u32 best_m, best_n; +- u32 u_f; +- u32 m, n, n2; +- u32 delta, lwv, best_delta = ~0; +- u32 pl; +- +- target_clk_f = rate * 2 / MHZ; +- ref_clk_f = priv->parent_rate / MHZ; +- +- max_vco_f = priv->params->max_vco; +- min_vco_f = priv->params->min_vco; +- best_m = priv->params->max_m; +- best_n = priv->params->min_n; +- best_pl = priv->params->min_pl; +- +- target_vco_f = target_clk_f + target_clk_f / 50; +- if (max_vco_f < target_vco_f) +- max_vco_f = target_vco_f; +- +- /* min_pl <= high_pl <= max_pl */ +- high_pl = (max_vco_f + target_vco_f - 1) / target_vco_f; +- high_pl = min(high_pl, priv->params->max_pl); +- high_pl = max(high_pl, priv->params->min_pl); +- +- /* min_pl <= low_pl <= max_pl */ +- low_pl = min_vco_f / target_vco_f; +- low_pl = min(low_pl, priv->params->max_pl); +- low_pl = max(low_pl, priv->params->min_pl); +- +- /* Find Indices of high_pl and low_pl */ +- for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { +- if (pl_to_div[pl] >= low_pl) { +- low_pl = pl; +- break; +- } +- } +- for (pl = 0; pl < ARRAY_SIZE(pl_to_div) - 1; pl++) { +- if (pl_to_div[pl] >= high_pl) { +- high_pl = pl; +- break; +- } +- } +- +- nv_debug(priv, "low_PL %d(div%d), high_PL %d(div%d)", low_pl, +- pl_to_div[low_pl], high_pl, pl_to_div[high_pl]); +- +- /* Select lowest possible VCO */ +- for (pl = low_pl; pl <= high_pl; pl++) { +- target_vco_f = target_clk_f * pl_to_div[pl]; +- for (m = priv->params->min_m; m <= priv->params->max_m; m++) { +- u_f = ref_clk_f / m; +- +- if (u_f < priv->params->min_u) +- break; +- if (u_f > priv->params->max_u) +- continue; +- +- n = (target_vco_f * m) / ref_clk_f; +- n2 = ((target_vco_f * m) + (ref_clk_f - 1)) / ref_clk_f; +- +- if (n > priv->params->max_n) +- break; +- +- for (; n <= n2; n++) { +- if (n < priv->params->min_n) +- continue; +- if (n > priv->params->max_n) +- break; +- +- vco_f = ref_clk_f * n / m; +- +- if (vco_f >= min_vco_f && vco_f <= max_vco_f) { +- lwv = (vco_f + (pl_to_div[pl] / 2)) +- / pl_to_div[pl]; +- delta = abs(lwv - target_clk_f); +- +- if (delta < best_delta) { +- best_delta = delta; +- best_m = m; +- best_n = n; +- best_pl = pl; +- +- if (best_delta == 0) +- goto found_match; +- } +- } +- } +- } +- } +- +-found_match: +- WARN_ON(best_delta == ~0); +- +- if (best_delta != 0) +- nv_debug(priv, "no best match for target @ %dMHz on gpc_pll", +- target_clk_f); +- +- priv->m = best_m; +- priv->n = best_n; +- priv->pl = best_pl; +- +- target_freq = gk20a_pllg_calc_rate(priv) / MHZ; +- +- nv_debug(priv, "actual target freq %d MHz, M %d, N %d, PL %d(div%d)\n", +- target_freq, priv->m, priv->n, priv->pl, pl_to_div[priv->pl]); +- +- return 0; +-} +- +-static int +-gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n) +-{ +- u32 val; +- int ramp_timeout; +- +- /* get old coefficients */ +- val = nv_rd32(priv, GPCPLL_COEFF); +- /* do nothing if NDIV is the same */ +- if (n == ((val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH))) +- return 0; +- +- /* setup */ +- nv_mask(priv, GPCPLL_CFG2, 0xff << GPCPLL_CFG2_PLL_STEPA_SHIFT, +- 0x2b << GPCPLL_CFG2_PLL_STEPA_SHIFT); +- nv_mask(priv, GPCPLL_CFG3, 0xff << GPCPLL_CFG3_PLL_STEPB_SHIFT, +- 0xb << GPCPLL_CFG3_PLL_STEPB_SHIFT); +- +- /* pll slowdown mode */ +- nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, +- BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT), +- BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT)); +- +- /* new ndiv ready for ramp */ +- val = nv_rd32(priv, GPCPLL_COEFF); +- val &= ~(MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT); +- val |= (n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; +- udelay(1); +- nv_wr32(priv, GPCPLL_COEFF, val); +- +- /* dynamic ramp to new ndiv */ +- val = nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); +- val |= 0x1 << GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT; +- udelay(1); +- nv_wr32(priv, GPCPLL_NDIV_SLOWDOWN, val); +- +- for (ramp_timeout = 500; ramp_timeout > 0; ramp_timeout--) { +- udelay(1); +- val = nv_rd32(priv, GPC_BCAST_NDIV_SLOWDOWN_DEBUG); +- if (val & GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK) +- break; +- } +- +- /* exit slowdown mode */ +- nv_mask(priv, GPCPLL_NDIV_SLOWDOWN, +- BIT(GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT) | +- BIT(GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT), 0); +- nv_rd32(priv, GPCPLL_NDIV_SLOWDOWN); +- +- if (ramp_timeout <= 0) { +- nv_error(priv, "gpcpll dynamic ramp timeout\n"); +- return -ETIMEDOUT; +- } +- +- return 0; +-} +- +-static void +-_gk20a_pllg_enable(struct gk20a_clock_priv *priv) +-{ +- nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE); +- nv_rd32(priv, GPCPLL_CFG); +-} +- +-static void +-_gk20a_pllg_disable(struct gk20a_clock_priv *priv) +-{ +- nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0); +- nv_rd32(priv, GPCPLL_CFG); +-} +- +-static int +-_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide) +-{ +- u32 val, cfg; +- u32 m_old, pl_old, n_lo; +- +- /* get old coefficients */ +- val = nv_rd32(priv, GPCPLL_COEFF); +- m_old = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); +- pl_old = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); +- +- /* do NDIV slide if there is no change in M and PL */ +- cfg = nv_rd32(priv, GPCPLL_CFG); +- if (allow_slide && priv->m == m_old && priv->pl == pl_old && +- (cfg & GPCPLL_CFG_ENABLE)) { +- return gk20a_pllg_slide(priv, priv->n); +- } +- +- /* slide down to NDIV_LO */ +- n_lo = DIV_ROUND_UP(m_old * priv->params->min_vco, +- priv->parent_rate / MHZ); +- if (allow_slide && (cfg & GPCPLL_CFG_ENABLE)) { +- int ret = gk20a_pllg_slide(priv, n_lo); +- +- if (ret) +- return ret; +- } +- +- /* split FO-to-bypass jump in halfs by setting out divider 1:2 */ +- nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_VCODIV_MASK, +- 0x2 << GPC2CLK_OUT_VCODIV_SHIFT); +- +- /* put PLL in bypass before programming it */ +- val = nv_rd32(priv, SEL_VCO); +- val &= ~(BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); +- udelay(2); +- nv_wr32(priv, SEL_VCO, val); +- +- /* get out from IDDQ */ +- val = nv_rd32(priv, GPCPLL_CFG); +- if (val & GPCPLL_CFG_IDDQ) { +- val &= ~GPCPLL_CFG_IDDQ; +- nv_wr32(priv, GPCPLL_CFG, val); +- nv_rd32(priv, GPCPLL_CFG); +- udelay(2); +- } +- +- _gk20a_pllg_disable(priv); +- +- nv_debug(priv, "%s: m=%d n=%d pl=%d\n", __func__, priv->m, priv->n, +- priv->pl); +- +- n_lo = DIV_ROUND_UP(priv->m * priv->params->min_vco, +- priv->parent_rate / MHZ); +- val = priv->m << GPCPLL_COEFF_M_SHIFT; +- val |= (allow_slide ? n_lo : priv->n) << GPCPLL_COEFF_N_SHIFT; +- val |= priv->pl << GPCPLL_COEFF_P_SHIFT; +- nv_wr32(priv, GPCPLL_COEFF, val); +- +- _gk20a_pllg_enable(priv); +- +- val = nv_rd32(priv, GPCPLL_CFG); +- if (val & GPCPLL_CFG_LOCK_DET_OFF) { +- val &= ~GPCPLL_CFG_LOCK_DET_OFF; +- nv_wr32(priv, GPCPLL_CFG, val); +- } +- +- if (!nouveau_timer_wait_eq(priv, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, +- GPCPLL_CFG_LOCK)) { +- nv_error(priv, "%s: timeout waiting for pllg lock\n", __func__); +- return -ETIMEDOUT; +- } +- +- /* switch to VCO mode */ +- nv_mask(priv, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); +- +- /* restore out divider 1:1 */ +- val = nv_rd32(priv, GPC2CLK_OUT); +- val &= ~GPC2CLK_OUT_VCODIV_MASK; +- udelay(2); +- nv_wr32(priv, GPC2CLK_OUT, val); +- +- /* slide up to new NDIV */ +- return allow_slide ? gk20a_pllg_slide(priv, priv->n) : 0; +-} +- +-static int +-gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv) +-{ +- int err; +- +- err = _gk20a_pllg_program_mnp(priv, true); +- if (err) +- err = _gk20a_pllg_program_mnp(priv, false); +- +- return err; +-} +- +-static void +-gk20a_pllg_disable(struct gk20a_clock_priv *priv) +-{ +- u32 val; +- +- /* slide to VCO min */ +- val = nv_rd32(priv, GPCPLL_CFG); +- if (val & GPCPLL_CFG_ENABLE) { +- u32 coeff, m, n_lo; +- +- coeff = nv_rd32(priv, GPCPLL_COEFF); +- m = (coeff >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); +- n_lo = DIV_ROUND_UP(m * priv->params->min_vco, +- priv->parent_rate / MHZ); +- gk20a_pllg_slide(priv, n_lo); +- } +- +- /* put PLL in bypass before disabling it */ +- nv_mask(priv, SEL_VCO, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT), 0); +- +- _gk20a_pllg_disable(priv); +-} +- +-#define GK20A_CLK_GPC_MDIV 1000 +- +-static struct nouveau_clocks +-gk20a_domains[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV }, +- { nv_clk_src_max } +-}; +- +-static struct nouveau_pstate +-gk20a_pstates[] = { +- { +- .base = { +- .domain[nv_clk_src_gpc] = 72000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 108000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 180000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 252000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 324000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 396000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 468000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 540000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 612000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 648000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 684000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 708000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 756000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 804000, +- }, +- }, +- { +- .base = { +- .domain[nv_clk_src_gpc] = 852000, +- }, +- }, +-}; +- +-static int +-gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct gk20a_clock_priv *priv = (void *)clk; +- +- switch (src) { +- case nv_clk_src_crystal: +- return nv_device(clk)->crystal; +- case nv_clk_src_gpc: +- gk20a_pllg_read_mnp(priv); +- return gk20a_pllg_calc_rate(priv) / GK20A_CLK_GPC_MDIV; +- default: +- nv_error(clk, "invalid clock source %d\n", src); +- return -EINVAL; +- } +-} +- +-static int +-gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct gk20a_clock_priv *priv = (void *)clk; +- +- return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] * +- GK20A_CLK_GPC_MDIV); +-} +- +-static int +-gk20a_clock_prog(struct nouveau_clock *clk) +-{ +- struct gk20a_clock_priv *priv = (void *)clk; +- +- return gk20a_pllg_program_mnp(priv); +-} +- +-static void +-gk20a_clock_tidy(struct nouveau_clock *clk) +-{ +-} +- +-static int +-gk20a_clock_fini(struct nouveau_object *object, bool suspend) +-{ +- struct gk20a_clock_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_clock_fini(&priv->base, false); +- +- gk20a_pllg_disable(priv); +- +- return ret; +-} +- +-static int +-gk20a_clock_init(struct nouveau_object *object) +-{ +- struct gk20a_clock_priv *priv = (void *)object; +- int ret; +- +- nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL); +- +- ret = nouveau_clock_init(&priv->base); +- if (ret) +- return ret; +- +- ret = gk20a_clock_prog(&priv->base); +- if (ret) { +- nv_error(priv, "cannot initialize clock\n"); +- return ret; +- } +- +- return 0; +-} +- +-static int +-gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gk20a_clock_priv *priv; +- struct nouveau_platform_device *plat; +- int ret; +- int i; +- +- /* Finish initializing the pstates */ +- for (i = 0; i < ARRAY_SIZE(gk20a_pstates); i++) { +- INIT_LIST_HEAD(&gk20a_pstates[i].list); +- gk20a_pstates[i].pstate = i + 1; +- } +- +- ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains, +- gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->params = &gk20a_pllg_params; +- +- plat = nv_device_to_platform(nv_device(parent)); +- priv->parent_rate = clk_get_rate(plat->gpu->clk); +- nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ); +- +- priv->base.read = gk20a_clock_read; +- priv->base.calc = gk20a_clock_calc; +- priv->base.prog = gk20a_clock_prog; +- priv->base.tidy = gk20a_clock_tidy; +- +- return 0; +-} +- +-struct nouveau_oclass +-gk20a_clock_oclass = { +- .handle = NV_SUBDEV(CLOCK, 0xea), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gk20a_clock_ctor, +- .dtor = _nouveau_subdev_dtor, +- .init = gk20a_clock_init, +- .fini = gk20a_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c +deleted file mode 100644 +index 4c482326..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c ++++ /dev/null +@@ -1,105 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include "pll.h" +- +-struct nv04_clock_priv { +- struct nouveau_clock base; +-}; +- +-int +-nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info, +- int clk, struct nouveau_pll_vals *pv) +-{ +- int N1, M1, N2, M2, P; +- int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P); +- if (ret) { +- pv->refclk = info->refclk; +- pv->N1 = N1; +- pv->M1 = M1; +- pv->N2 = N2; +- pv->M2 = M2; +- pv->log2P = P; +- } +- return ret; +-} +- +-int +-nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1, +- struct nouveau_pll_vals *pv) +-{ +- struct nouveau_devinit *devinit = nouveau_devinit(clk); +- int cv = nouveau_bios(clk)->version.chip; +- +- if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || +- cv >= 0x40) { +- if (reg1 > 0x405c) +- setPLL_double_highregs(devinit, reg1, pv); +- else +- setPLL_double_lowregs(devinit, reg1, pv); +- } else +- setPLL_single(devinit, reg1, pv); +- +- return 0; +-} +- +-static struct nouveau_clocks +-nv04_domain[] = { +- { nv_clk_src_max } +-}; +- +-static int +-nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0, +- false, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.pll_calc = nv04_clock_pll_calc; +- priv->base.pll_prog = nv04_clock_pll_prog; +- return 0; +-} +- +-struct nouveau_oclass +-nv04_clock_oclass = { +- .handle = NV_SUBDEV(CLOCK, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c +deleted file mode 100644 +index 08368fe9..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv40.c ++++ /dev/null +@@ -1,240 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "pll.h" +- +-struct nv40_clock_priv { +- struct nouveau_clock base; +- u32 ctrl; +- u32 npll_ctrl; +- u32 npll_coef; +- u32 spll; +-}; +- +-static struct nouveau_clocks +-nv40_domain[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_href , 0xff }, +- { nv_clk_src_core , 0xff, 0, "core", 1000 }, +- { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, +- { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, +- { nv_clk_src_max } +-}; +- +-static u32 +-read_pll_1(struct nv40_clock_priv *priv, u32 reg) +-{ +- u32 ctrl = nv_rd32(priv, reg + 0x00); +- int P = (ctrl & 0x00070000) >> 16; +- int N = (ctrl & 0x0000ff00) >> 8; +- int M = (ctrl & 0x000000ff) >> 0; +- u32 ref = 27000, clk = 0; +- +- if (ctrl & 0x80000000) +- clk = ref * N / M; +- +- return clk >> P; +-} +- +-static u32 +-read_pll_2(struct nv40_clock_priv *priv, u32 reg) +-{ +- u32 ctrl = nv_rd32(priv, reg + 0x00); +- u32 coef = nv_rd32(priv, reg + 0x04); +- int N2 = (coef & 0xff000000) >> 24; +- int M2 = (coef & 0x00ff0000) >> 16; +- int N1 = (coef & 0x0000ff00) >> 8; +- int M1 = (coef & 0x000000ff) >> 0; +- int P = (ctrl & 0x00070000) >> 16; +- u32 ref = 27000, clk = 0; +- +- if ((ctrl & 0x80000000) && M1) { +- clk = ref * N1 / M1; +- if ((ctrl & 0x40000100) == 0x40000000) { +- if (M2) +- clk = clk * N2 / M2; +- else +- clk = 0; +- } +- } +- +- return clk >> P; +-} +- +-static u32 +-read_clk(struct nv40_clock_priv *priv, u32 src) +-{ +- switch (src) { +- case 3: +- return read_pll_2(priv, 0x004000); +- case 2: +- return read_pll_1(priv, 0x004008); +- default: +- break; +- } +- +- return 0; +-} +- +-static int +-nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct nv40_clock_priv *priv = (void *)clk; +- u32 mast = nv_rd32(priv, 0x00c040); +- +- switch (src) { +- case nv_clk_src_crystal: +- return nv_device(priv)->crystal; +- case nv_clk_src_href: +- return 100000; /*XXX: PCIE/AGP differ*/ +- case nv_clk_src_core: +- return read_clk(priv, (mast & 0x00000003) >> 0); +- case nv_clk_src_shader: +- return read_clk(priv, (mast & 0x00000030) >> 4); +- case nv_clk_src_mem: +- return read_pll_2(priv, 0x4020); +- default: +- break; +- } +- +- nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); +- return -EINVAL; +-} +- +-static int +-nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk, +- int *N1, int *M1, int *N2, int *M2, int *log2P) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll pll; +- int ret; +- +- ret = nvbios_pll_parse(bios, reg, &pll); +- if (ret) +- return ret; +- +- if (clk < pll.vco1.max_freq) +- pll.vco2.max_freq = 0; +- +- ret = nv04_pll_calc(nv_subdev(priv), &pll, clk, N1, M1, N2, M2, log2P); +- if (ret == 0) +- return -ERANGE; +- return ret; +-} +- +-static int +-nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct nv40_clock_priv *priv = (void *)clk; +- int gclk = cstate->domain[nv_clk_src_core]; +- int sclk = cstate->domain[nv_clk_src_shader]; +- int N1, M1, N2, M2, log2P; +- int ret; +- +- /* core/geometric clock */ +- ret = nv40_clock_calc_pll(priv, 0x004000, gclk, +- &N1, &M1, &N2, &M2, &log2P); +- if (ret < 0) +- return ret; +- +- if (N2 == M2) { +- priv->npll_ctrl = 0x80000100 | (log2P << 16); +- priv->npll_coef = (N1 << 8) | M1; +- } else { +- priv->npll_ctrl = 0xc0000000 | (log2P << 16); +- priv->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; +- } +- +- /* use the second pll for shader/rop clock, if it differs from core */ +- if (sclk && sclk != gclk) { +- ret = nv40_clock_calc_pll(priv, 0x004008, sclk, +- &N1, &M1, NULL, NULL, &log2P); +- if (ret < 0) +- return ret; +- +- priv->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; +- priv->ctrl = 0x00000223; +- } else { +- priv->spll = 0x00000000; +- priv->ctrl = 0x00000333; +- } +- +- return 0; +-} +- +-static int +-nv40_clock_prog(struct nouveau_clock *clk) +-{ +- struct nv40_clock_priv *priv = (void *)clk; +- nv_mask(priv, 0x00c040, 0x00000333, 0x00000000); +- nv_wr32(priv, 0x004004, priv->npll_coef); +- nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl); +- nv_mask(priv, 0x004008, 0xc007ffff, priv->spll); +- mdelay(5); +- nv_mask(priv, 0x00c040, 0x00000333, priv->ctrl); +- return 0; +-} +- +-static void +-nv40_clock_tidy(struct nouveau_clock *clk) +-{ +-} +- +-static int +-nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv40_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0, +- true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.pll_calc = nv04_clock_pll_calc; +- priv->base.pll_prog = nv04_clock_pll_prog; +- priv->base.read = nv40_clock_read; +- priv->base.calc = nv40_clock_calc; +- priv->base.prog = nv40_clock_prog; +- priv->base.tidy = nv40_clock_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nv40_clock_oclass = { +- .handle = NV_SUBDEV(CLOCK, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c +deleted file mode 100644 +index 5070ebc2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.c ++++ /dev/null +@@ -1,559 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "nv50.h" +-#include "pll.h" +-#include "seq.h" +- +-static u32 +-read_div(struct nv50_clock_priv *priv) +-{ +- switch (nv_device(priv)->chipset) { +- case 0x50: /* it exists, but only has bit 31, not the dividers.. */ +- case 0x84: +- case 0x86: +- case 0x98: +- case 0xa0: +- return nv_rd32(priv, 0x004700); +- case 0x92: +- case 0x94: +- case 0x96: +- return nv_rd32(priv, 0x004800); +- default: +- return 0x00000000; +- } +-} +- +-static u32 +-read_pll_src(struct nv50_clock_priv *priv, u32 base) +-{ +- struct nouveau_clock *clk = &priv->base; +- u32 coef, ref = clk->read(clk, nv_clk_src_crystal); +- u32 rsel = nv_rd32(priv, 0x00e18c); +- int P, N, M, id; +- +- switch (nv_device(priv)->chipset) { +- case 0x50: +- case 0xa0: +- switch (base) { +- case 0x4020: +- case 0x4028: id = !!(rsel & 0x00000004); break; +- case 0x4008: id = !!(rsel & 0x00000008); break; +- case 0x4030: id = 0; break; +- default: +- nv_error(priv, "ref: bad pll 0x%06x\n", base); +- return 0; +- } +- +- coef = nv_rd32(priv, 0x00e81c + (id * 0x0c)); +- ref *= (coef & 0x01000000) ? 2 : 4; +- P = (coef & 0x00070000) >> 16; +- N = ((coef & 0x0000ff00) >> 8) + 1; +- M = ((coef & 0x000000ff) >> 0) + 1; +- break; +- case 0x84: +- case 0x86: +- case 0x92: +- coef = nv_rd32(priv, 0x00e81c); +- P = (coef & 0x00070000) >> 16; +- N = (coef & 0x0000ff00) >> 8; +- M = (coef & 0x000000ff) >> 0; +- break; +- case 0x94: +- case 0x96: +- case 0x98: +- rsel = nv_rd32(priv, 0x00c050); +- switch (base) { +- case 0x4020: rsel = (rsel & 0x00000003) >> 0; break; +- case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break; +- case 0x4028: rsel = (rsel & 0x00001800) >> 11; break; +- case 0x4030: rsel = 3; break; +- default: +- nv_error(priv, "ref: bad pll 0x%06x\n", base); +- return 0; +- } +- +- switch (rsel) { +- case 0: id = 1; break; +- case 1: return clk->read(clk, nv_clk_src_crystal); +- case 2: return clk->read(clk, nv_clk_src_href); +- case 3: id = 0; break; +- } +- +- coef = nv_rd32(priv, 0x00e81c + (id * 0x28)); +- P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7; +- P += (coef & 0x00070000) >> 16; +- N = (coef & 0x0000ff00) >> 8; +- M = (coef & 0x000000ff) >> 0; +- break; +- default: +- BUG_ON(1); +- } +- +- if (M) +- return (ref * N / M) >> P; +- return 0; +-} +- +-static u32 +-read_pll_ref(struct nv50_clock_priv *priv, u32 base) +-{ +- struct nouveau_clock *clk = &priv->base; +- u32 src, mast = nv_rd32(priv, 0x00c040); +- +- switch (base) { +- case 0x004028: +- src = !!(mast & 0x00200000); +- break; +- case 0x004020: +- src = !!(mast & 0x00400000); +- break; +- case 0x004008: +- src = !!(mast & 0x00010000); +- break; +- case 0x004030: +- src = !!(mast & 0x02000000); +- break; +- case 0x00e810: +- return clk->read(clk, nv_clk_src_crystal); +- default: +- nv_error(priv, "bad pll 0x%06x\n", base); +- return 0; +- } +- +- if (src) +- return clk->read(clk, nv_clk_src_href); +- return read_pll_src(priv, base); +-} +- +-static u32 +-read_pll(struct nv50_clock_priv *priv, u32 base) +-{ +- struct nouveau_clock *clk = &priv->base; +- u32 mast = nv_rd32(priv, 0x00c040); +- u32 ctrl = nv_rd32(priv, base + 0); +- u32 coef = nv_rd32(priv, base + 4); +- u32 ref = read_pll_ref(priv, base); +- u32 freq = 0; +- int N1, N2, M1, M2; +- +- if (base == 0x004028 && (mast & 0x00100000)) { +- /* wtf, appears to only disable post-divider on nva0 */ +- if (nv_device(priv)->chipset != 0xa0) +- return clk->read(clk, nv_clk_src_dom6); +- } +- +- N2 = (coef & 0xff000000) >> 24; +- M2 = (coef & 0x00ff0000) >> 16; +- N1 = (coef & 0x0000ff00) >> 8; +- M1 = (coef & 0x000000ff); +- if ((ctrl & 0x80000000) && M1) { +- freq = ref * N1 / M1; +- if ((ctrl & 0x40000100) == 0x40000000) { +- if (M2) +- freq = freq * N2 / M2; +- else +- freq = 0; +- } +- } +- +- return freq; +-} +- +-static int +-nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct nv50_clock_priv *priv = (void *)clk; +- u32 mast = nv_rd32(priv, 0x00c040); +- u32 P = 0; +- +- switch (src) { +- case nv_clk_src_crystal: +- return nv_device(priv)->crystal; +- case nv_clk_src_href: +- return 100000; /* PCIE reference clock */ +- case nv_clk_src_hclk: +- return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000); +- case nv_clk_src_hclkm3: +- return clk->read(clk, nv_clk_src_hclk) * 3; +- case nv_clk_src_hclkm3d2: +- return clk->read(clk, nv_clk_src_hclk) * 3 / 2; +- case nv_clk_src_host: +- switch (mast & 0x30000000) { +- case 0x00000000: return clk->read(clk, nv_clk_src_href); +- case 0x10000000: break; +- case 0x20000000: /* !0x50 */ +- case 0x30000000: return clk->read(clk, nv_clk_src_hclk); +- } +- break; +- case nv_clk_src_core: +- if (!(mast & 0x00100000)) +- P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16; +- switch (mast & 0x00000003) { +- case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; +- case 0x00000001: return clk->read(clk, nv_clk_src_dom6); +- case 0x00000002: return read_pll(priv, 0x004020) >> P; +- case 0x00000003: return read_pll(priv, 0x004028) >> P; +- } +- break; +- case nv_clk_src_shader: +- P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16; +- switch (mast & 0x00000030) { +- case 0x00000000: +- if (mast & 0x00000080) +- return clk->read(clk, nv_clk_src_host) >> P; +- return clk->read(clk, nv_clk_src_crystal) >> P; +- case 0x00000010: break; +- case 0x00000020: return read_pll(priv, 0x004028) >> P; +- case 0x00000030: return read_pll(priv, 0x004020) >> P; +- } +- break; +- case nv_clk_src_mem: +- P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16; +- if (nv_rd32(priv, 0x004008) & 0x00000200) { +- switch (mast & 0x0000c000) { +- case 0x00000000: +- return clk->read(clk, nv_clk_src_crystal) >> P; +- case 0x00008000: +- case 0x0000c000: +- return clk->read(clk, nv_clk_src_href) >> P; +- } +- } else { +- return read_pll(priv, 0x004008) >> P; +- } +- break; +- case nv_clk_src_vdec: +- P = (read_div(priv) & 0x00000700) >> 8; +- switch (nv_device(priv)->chipset) { +- case 0x84: +- case 0x86: +- case 0x92: +- case 0x94: +- case 0x96: +- case 0xa0: +- switch (mast & 0x00000c00) { +- case 0x00000000: +- if (nv_device(priv)->chipset == 0xa0) /* wtf?? */ +- return clk->read(clk, nv_clk_src_core) >> P; +- return clk->read(clk, nv_clk_src_crystal) >> P; +- case 0x00000400: +- return 0; +- case 0x00000800: +- if (mast & 0x01000000) +- return read_pll(priv, 0x004028) >> P; +- return read_pll(priv, 0x004030) >> P; +- case 0x00000c00: +- return clk->read(clk, nv_clk_src_core) >> P; +- } +- break; +- case 0x98: +- switch (mast & 0x00000c00) { +- case 0x00000000: +- return clk->read(clk, nv_clk_src_core) >> P; +- case 0x00000400: +- return 0; +- case 0x00000800: +- return clk->read(clk, nv_clk_src_hclkm3d2) >> P; +- case 0x00000c00: +- return clk->read(clk, nv_clk_src_mem) >> P; +- } +- break; +- } +- break; +- case nv_clk_src_dom6: +- switch (nv_device(priv)->chipset) { +- case 0x50: +- case 0xa0: +- return read_pll(priv, 0x00e810) >> 2; +- case 0x84: +- case 0x86: +- case 0x92: +- case 0x94: +- case 0x96: +- case 0x98: +- P = (read_div(priv) & 0x00000007) >> 0; +- switch (mast & 0x0c000000) { +- case 0x00000000: return clk->read(clk, nv_clk_src_href); +- case 0x04000000: break; +- case 0x08000000: return clk->read(clk, nv_clk_src_hclk); +- case 0x0c000000: +- return clk->read(clk, nv_clk_src_hclkm3) >> P; +- } +- break; +- default: +- break; +- } +- default: +- break; +- } +- +- nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); +- return -EINVAL; +-} +- +-static u32 +-calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll pll; +- int ret; +- +- ret = nvbios_pll_parse(bios, reg, &pll); +- if (ret) +- return 0; +- +- pll.vco2.max_freq = 0; +- pll.refclk = read_pll_ref(priv, reg); +- if (!pll.refclk) +- return 0; +- +- return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P); +-} +- +-static inline u32 +-calc_div(u32 src, u32 target, int *div) +-{ +- u32 clk0 = src, clk1 = src; +- for (*div = 0; *div <= 7; (*div)++) { +- if (clk0 <= target) { +- clk1 = clk0 << (*div ? 1 : 0); +- break; +- } +- clk0 >>= 1; +- } +- +- if (target - clk0 <= clk1 - target) +- return clk0; +- (*div)--; +- return clk1; +-} +- +-static inline u32 +-clk_same(u32 a, u32 b) +-{ +- return ((a / 1000) == (b / 1000)); +-} +- +-static int +-nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct nv50_clock_priv *priv = (void *)clk; +- struct nv50_clock_hwsq *hwsq = &priv->hwsq; +- const int shader = cstate->domain[nv_clk_src_shader]; +- const int core = cstate->domain[nv_clk_src_core]; +- const int vdec = cstate->domain[nv_clk_src_vdec]; +- const int dom6 = cstate->domain[nv_clk_src_dom6]; +- u32 mastm = 0, mastv = 0; +- u32 divsm = 0, divsv = 0; +- int N, M, P1, P2; +- int freq, out; +- +- /* prepare a hwsq script from which we'll perform the reclock */ +- out = clk_init(hwsq, nv_subdev(clk)); +- if (out) +- return out; +- +- clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */ +- clk_nsec(hwsq, 8000); +- clk_setf(hwsq, 0x10, 0x00); /* disable fb */ +- clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ +- +- /* vdec: avoid modifying xpll until we know exactly how the other +- * clock domains work, i suspect at least some of them can also be +- * tied to xpll... +- */ +- if (vdec) { +- /* see how close we can get using nvclk as a source */ +- freq = calc_div(core, vdec, &P1); +- +- /* see how close we can get using xpll/hclk as a source */ +- if (nv_device(priv)->chipset != 0x98) +- out = read_pll(priv, 0x004030); +- else +- out = clk->read(clk, nv_clk_src_hclkm3d2); +- out = calc_div(out, vdec, &P2); +- +- /* select whichever gets us closest */ +- if (abs(vdec - freq) <= abs(vdec - out)) { +- if (nv_device(priv)->chipset != 0x98) +- mastv |= 0x00000c00; +- divsv |= P1 << 8; +- } else { +- mastv |= 0x00000800; +- divsv |= P2 << 8; +- } +- +- mastm |= 0x00000c00; +- divsm |= 0x00000700; +- } +- +- /* dom6: nfi what this is, but we're limited to various combinations +- * of the host clock frequency +- */ +- if (dom6) { +- if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) { +- mastv |= 0x00000000; +- } else +- if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) { +- mastv |= 0x08000000; +- } else { +- freq = clk->read(clk, nv_clk_src_hclk) * 3; +- freq = calc_div(freq, dom6, &P1); +- +- mastv |= 0x0c000000; +- divsv |= P1; +- } +- +- mastm |= 0x0c000000; +- divsm |= 0x00000007; +- } +- +- /* vdec/dom6: switch to "safe" clocks temporarily, update dividers +- * and then switch to target clocks +- */ +- clk_mask(hwsq, mast, mastm, 0x00000000); +- clk_mask(hwsq, divs, divsm, divsv); +- clk_mask(hwsq, mast, mastm, mastv); +- +- /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6, +- * sclk to hclk) before reprogramming +- */ +- if (nv_device(priv)->chipset < 0x92) +- clk_mask(hwsq, mast, 0x001000b0, 0x00100080); +- else +- clk_mask(hwsq, mast, 0x000000b3, 0x00000081); +- +- /* core: for the moment at least, always use nvpll */ +- freq = calc_pll(priv, 0x4028, core, &N, &M, &P1); +- if (freq == 0) +- return -ERANGE; +- +- clk_mask(hwsq, nvpll[0], 0xc03f0100, +- 0x80000000 | (P1 << 19) | (P1 << 16)); +- clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); +- +- /* shader: tie to nvclk if possible, otherwise use spll. have to be +- * very careful that the shader clock is at least twice the core, or +- * some chipsets will be very unhappy. i expect most or all of these +- * cases will be handled by tying to nvclk, but it's possible there's +- * corners +- */ +- if (P1-- && shader == (core << 1)) { +- clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); +- clk_mask(hwsq, mast, 0x00100033, 0x00000023); +- } else { +- freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1); +- if (freq == 0) +- return -ERANGE; +- +- clk_mask(hwsq, spll[0], 0xc03f0100, +- 0x80000000 | (P1 << 19) | (P1 << 16)); +- clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); +- clk_mask(hwsq, mast, 0x00100033, 0x00000033); +- } +- +- /* restore normal operation */ +- clk_setf(hwsq, 0x10, 0x01); /* enable fb */ +- clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ +- clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */ +- return 0; +-} +- +-static int +-nv50_clock_prog(struct nouveau_clock *clk) +-{ +- struct nv50_clock_priv *priv = (void *)clk; +- return clk_exec(&priv->hwsq, true); +-} +- +-static void +-nv50_clock_tidy(struct nouveau_clock *clk) +-{ +- struct nv50_clock_priv *priv = (void *)clk; +- clk_exec(&priv->hwsq, false); +-} +- +-int +-nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_clock_oclass *pclass = (void *)oclass; +- struct nv50_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, pclass->domains, +- NULL, 0, false, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->hwsq.r_fifo = hwsq_reg(0x002504); +- priv->hwsq.r_spll[0] = hwsq_reg(0x004020); +- priv->hwsq.r_spll[1] = hwsq_reg(0x004024); +- priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028); +- priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); +- switch (nv_device(priv)->chipset) { +- case 0x92: +- case 0x94: +- case 0x96: +- priv->hwsq.r_divs = hwsq_reg(0x004800); +- break; +- default: +- priv->hwsq.r_divs = hwsq_reg(0x004700); +- break; +- } +- priv->hwsq.r_mast = hwsq_reg(0x00c040); +- +- priv->base.read = nv50_clock_read; +- priv->base.calc = nv50_clock_calc; +- priv->base.prog = nv50_clock_prog; +- priv->base.tidy = nv50_clock_tidy; +- return 0; +-} +- +-static struct nouveau_clocks +-nv50_domains[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_href , 0xff }, +- { nv_clk_src_core , 0xff, 0, "core", 1000 }, +- { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, +- { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, +- { nv_clk_src_max } +-}; +- +-struct nouveau_oclass * +-nv50_clock_oclass = &(struct nv50_clock_oclass) { +- .base.handle = NV_SUBDEV(CLOCK, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +- .domains = nv50_domains, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h +deleted file mode 100644 +index f10917d7..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv50.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-#ifndef __NVKM_CLK_NV50_H__ +-#define __NVKM_CLK_NV50_H__ +- +-#include +-#include +-#include +- +-struct nv50_clock_hwsq { +- struct hwsq base; +- struct hwsq_reg r_fifo; +- struct hwsq_reg r_spll[2]; +- struct hwsq_reg r_nvpll[2]; +- struct hwsq_reg r_divs; +- struct hwsq_reg r_mast; +-}; +- +-struct nv50_clock_priv { +- struct nouveau_clock base; +- struct nv50_clock_hwsq hwsq; +-}; +- +-int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-struct nv50_clock_oclass { +- struct nouveau_oclass base; +- struct nouveau_clocks *domains; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c +deleted file mode 100644 +index b0b7c143..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nv84.c ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static struct nouveau_clocks +-nv84_domains[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_href , 0xff }, +- { nv_clk_src_core , 0xff, 0, "core", 1000 }, +- { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, +- { nv_clk_src_mem , 0xff, 0, "memory", 1000 }, +- { nv_clk_src_vdec , 0xff }, +- { nv_clk_src_max } +-}; +- +-struct nouveau_oclass * +-nv84_clock_oclass = &(struct nv50_clock_oclass) { +- .base.handle = NV_SUBDEV(CLOCK, 0x84), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +- .domains = nv84_domains, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c +deleted file mode 100644 +index 094551d8..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.c ++++ /dev/null +@@ -1,534 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Roy Spliet +- */ +- +-#include +-#include +-#include +-#include +- +-#include "pll.h" +- +-#include "nva3.h" +- +-struct nva3_clock_priv { +- struct nouveau_clock base; +- struct nva3_clock_info eng[nv_clk_src_max]; +-}; +- +-static u32 read_clk(struct nva3_clock_priv *, int, bool); +-static u32 read_pll(struct nva3_clock_priv *, int, u32); +- +-static u32 +-read_vco(struct nva3_clock_priv *priv, int clk) +-{ +- u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); +- +- switch (sctl & 0x00000030) { +- case 0x00000000: +- return nv_device(priv)->crystal; +- case 0x00000020: +- return read_pll(priv, 0x41, 0x00e820); +- case 0x00000030: +- return read_pll(priv, 0x42, 0x00e8a0); +- default: +- return 0; +- } +-} +- +-static u32 +-read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) +-{ +- u32 sctl, sdiv, sclk; +- +- /* refclk for the 0xe8xx plls is a fixed frequency */ +- if (clk >= 0x40) { +- if (nv_device(priv)->chipset == 0xaf) { +- /* no joke.. seriously.. sigh.. */ +- return nv_rd32(priv, 0x00471c) * 1000; +- } +- +- return nv_device(priv)->crystal; +- } +- +- sctl = nv_rd32(priv, 0x4120 + (clk * 4)); +- if (!ignore_en && !(sctl & 0x00000100)) +- return 0; +- +- /* out_alt */ +- if (sctl & 0x00000400) +- return 108000; +- +- /* vco_out */ +- switch (sctl & 0x00003000) { +- case 0x00000000: +- if (!(sctl & 0x00000200)) +- return nv_device(priv)->crystal; +- return 0; +- case 0x00002000: +- if (sctl & 0x00000040) +- return 108000; +- return 100000; +- case 0x00003000: +- /* vco_enable */ +- if (!(sctl & 0x00000001)) +- return 0; +- +- sclk = read_vco(priv, clk); +- sdiv = ((sctl & 0x003f0000) >> 16) + 2; +- return (sclk * 2) / sdiv; +- default: +- return 0; +- } +-} +- +-static u32 +-read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) +-{ +- u32 ctrl = nv_rd32(priv, pll + 0); +- u32 sclk = 0, P = 1, N = 1, M = 1; +- +- if (!(ctrl & 0x00000008)) { +- if (ctrl & 0x00000001) { +- u32 coef = nv_rd32(priv, pll + 4); +- M = (coef & 0x000000ff) >> 0; +- N = (coef & 0x0000ff00) >> 8; +- P = (coef & 0x003f0000) >> 16; +- +- /* no post-divider on these.. +- * XXX: it looks more like two post-"dividers" that +- * cross each other out in the default RPLL config */ +- if ((pll & 0x00ff00) == 0x00e800) +- P = 1; +- +- sclk = read_clk(priv, 0x00 + clk, false); +- } +- } else { +- sclk = read_clk(priv, 0x10 + clk, false); +- } +- +- if (M * P) +- return sclk * N / (M * P); +- return 0; +-} +- +-static int +-nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct nva3_clock_priv *priv = (void *)clk; +- u32 hsrc; +- +- switch (src) { +- case nv_clk_src_crystal: +- return nv_device(priv)->crystal; +- case nv_clk_src_core: +- case nv_clk_src_core_intm: +- return read_pll(priv, 0x00, 0x4200); +- case nv_clk_src_shader: +- return read_pll(priv, 0x01, 0x4220); +- case nv_clk_src_mem: +- return read_pll(priv, 0x02, 0x4000); +- case nv_clk_src_disp: +- return read_clk(priv, 0x20, false); +- case nv_clk_src_vdec: +- return read_clk(priv, 0x21, false); +- case nv_clk_src_daemon: +- return read_clk(priv, 0x25, false); +- case nv_clk_src_host: +- hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28; +- switch (hsrc) { +- case 0: +- return read_clk(priv, 0x1d, false); +- case 2: +- case 3: +- return 277000; +- default: +- nv_error(clk, "unknown HOST clock source %d\n", hsrc); +- return -EINVAL; +- } +- default: +- nv_error(clk, "invalid clock source %d\n", src); +- return -EINVAL; +- } +- +- return 0; +-} +- +-int +-nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, +- struct nva3_clock_info *info) +-{ +- struct nva3_clock_priv *priv = (void *)clock; +- u32 oclk, sclk, sdiv, diff; +- +- info->clk = 0; +- +- switch (khz) { +- case 27000: +- info->clk = 0x00000100; +- return khz; +- case 100000: +- info->clk = 0x00002100; +- return khz; +- case 108000: +- info->clk = 0x00002140; +- return khz; +- default: +- sclk = read_vco(priv, clk); +- sdiv = min((sclk * 2) / khz, (u32)65); +- oclk = (sclk * 2) / sdiv; +- diff = ((khz + 3000) - oclk); +- +- /* When imprecise, play it safe and aim for a clock lower than +- * desired rather than higher */ +- if (diff < 0) { +- sdiv++; +- oclk = (sclk * 2) / sdiv; +- } +- +- /* divider can go as low as 2, limited here because NVIDIA +- * and the VBIOS on my NVA8 seem to prefer using the PLL +- * for 810MHz - is there a good reason? +- * XXX: PLLs with refclk 810MHz? */ +- if (sdiv > 4) { +- info->clk = (((sdiv - 2) << 16) | 0x00003100); +- return oclk; +- } +- +- break; +- } +- +- return -ERANGE; +-} +- +-int +-nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, +- struct nva3_clock_info *info) +-{ +- struct nouveau_bios *bios = nouveau_bios(clock); +- struct nva3_clock_priv *priv = (void *)clock; +- struct nvbios_pll limits; +- int P, N, M, diff; +- int ret; +- +- info->pll = 0; +- +- /* If we can get a within [-2, 3) MHz of a divider, we'll disable the +- * PLL and use the divider instead. */ +- ret = nva3_clk_info(clock, clk, khz, info); +- diff = khz - ret; +- if (!pll || (diff >= -2000 && diff < 3000)) { +- goto out; +- } +- +- /* Try with PLL */ +- ret = nvbios_pll_parse(bios, pll, &limits); +- if (ret) +- return ret; +- +- ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); +- if (ret != limits.refclk) +- return -EINVAL; +- +- ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); +- if (ret >= 0) { +- info->pll = (P << 16) | (N << 8) | M; +- } +- +-out: +- info->fb_delay = max(((khz + 7566) / 15133), (u32) 18); +- +- return ret ? ret : -ERANGE; +-} +- +-static int +-calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, +- int clk, u32 pll, int idx) +-{ +- int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], +- &priv->eng[idx]); +- if (ret >= 0) +- return 0; +- return ret; +-} +- +-static int +-calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate) +-{ +- int ret = 0; +- u32 kHz = cstate->domain[nv_clk_src_host]; +- struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; +- +- if (kHz == 277000) { +- info->clk = 0; +- info->host_out = NVA3_HOST_277; +- return 0; +- } +- +- info->host_out = NVA3_HOST_CLK; +- +- ret = nva3_clk_info(&priv->base, 0x1d, kHz, info); +- if (ret >= 0) +- return 0; +- return ret; +-} +- +-int +-nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(clk); +- +- /* halt and idle execution engines */ +- nv_mask(clk, 0x020060, 0x00070000, 0x00000000); +- nv_mask(clk, 0x002504, 0x00000001, 0x00000001); +- /* Wait until the interrupt handler is finished */ +- if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) +- return -EBUSY; +- +- if (pfifo) +- pfifo->pause(pfifo, flags); +- +- if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) +- return -EIO; +- if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) +- return -EIO; +- +- return 0; +-} +- +-void +-nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags) +-{ +- struct nouveau_fifo *pfifo = nouveau_fifo(clk); +- +- if (pfifo && flags) +- pfifo->start(pfifo, flags); +- +- nv_mask(clk, 0x002504, 0x00000001, 0x00000000); +- nv_mask(clk, 0x020060, 0x00070000, 0x00040000); +-} +- +-static void +-disable_clk_src(struct nva3_clock_priv *priv, u32 src) +-{ +- nv_mask(priv, src, 0x00000100, 0x00000000); +- nv_mask(priv, src, 0x00000001, 0x00000000); +-} +- +-static void +-prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) +-{ +- struct nva3_clock_info *info = &priv->eng[idx]; +- const u32 src0 = 0x004120 + (clk * 4); +- const u32 src1 = 0x004160 + (clk * 4); +- const u32 ctrl = pll + 0; +- const u32 coef = pll + 4; +- u32 bypass; +- +- if (info->pll) { +- /* Always start from a non-PLL clock */ +- bypass = nv_rd32(priv, ctrl) & 0x00000008; +- if (!bypass) { +- nv_mask(priv, src1, 0x00000101, 0x00000101); +- nv_mask(priv, ctrl, 0x00000008, 0x00000008); +- udelay(20); +- } +- +- nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); +- nv_wr32(priv, coef, info->pll); +- nv_mask(priv, ctrl, 0x00000015, 0x00000015); +- nv_mask(priv, ctrl, 0x00000010, 0x00000000); +- if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) { +- nv_mask(priv, ctrl, 0x00000010, 0x00000010); +- nv_mask(priv, src0, 0x00000101, 0x00000000); +- return; +- } +- nv_mask(priv, ctrl, 0x00000010, 0x00000010); +- nv_mask(priv, ctrl, 0x00000008, 0x00000000); +- disable_clk_src(priv, src1); +- } else { +- nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); +- nv_mask(priv, ctrl, 0x00000018, 0x00000018); +- udelay(20); +- nv_mask(priv, ctrl, 0x00000001, 0x00000000); +- disable_clk_src(priv, src0); +- } +-} +- +-static void +-prog_clk(struct nva3_clock_priv *priv, int clk, int idx) +-{ +- struct nva3_clock_info *info = &priv->eng[idx]; +- nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); +-} +- +-static void +-prog_host(struct nva3_clock_priv *priv) +-{ +- struct nva3_clock_info *info = &priv->eng[nv_clk_src_host]; +- u32 hsrc = (nv_rd32(priv, 0xc040)); +- +- switch (info->host_out) { +- case NVA3_HOST_277: +- if ((hsrc & 0x30000000) == 0) { +- nv_wr32(priv, 0xc040, hsrc | 0x20000000); +- disable_clk_src(priv, 0x4194); +- } +- break; +- case NVA3_HOST_CLK: +- prog_clk(priv, 0x1d, nv_clk_src_host); +- if ((hsrc & 0x30000000) >= 0x20000000) { +- nv_wr32(priv, 0xc040, hsrc & ~0x30000000); +- } +- break; +- default: +- break; +- } +- +- /* This seems to be a clock gating factor on idle, always set to 64 */ +- nv_wr32(priv, 0xc044, 0x3e); +-} +- +-static void +-prog_core(struct nva3_clock_priv *priv, int idx) +-{ +- struct nva3_clock_info *info = &priv->eng[idx]; +- u32 fb_delay = nv_rd32(priv, 0x10002c); +- +- if (fb_delay < info->fb_delay) +- nv_wr32(priv, 0x10002c, info->fb_delay); +- +- prog_pll(priv, 0x00, 0x004200, idx); +- +- if (fb_delay > info->fb_delay) +- nv_wr32(priv, 0x10002c, info->fb_delay); +-} +- +-static int +-nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct nva3_clock_priv *priv = (void *)clk; +- struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; +- int ret; +- +- if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || +- (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || +- (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || +- (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || +- (ret = calc_host(priv, cstate))) +- return ret; +- +- /* XXX: Should be reading the highest bit in the VBIOS clock to decide +- * whether to use a PLL or not... but using a PLL defeats the purpose */ +- if (core->pll) { +- ret = nva3_clk_info(clk, 0x10, +- cstate->domain[nv_clk_src_core_intm], +- &priv->eng[nv_clk_src_core_intm]); +- if (ret < 0) +- return ret; +- } +- +- return 0; +-} +- +-static int +-nva3_clock_prog(struct nouveau_clock *clk) +-{ +- struct nva3_clock_priv *priv = (void *)clk; +- struct nva3_clock_info *core = &priv->eng[nv_clk_src_core]; +- int ret = 0; +- unsigned long flags; +- unsigned long *f = &flags; +- +- ret = nva3_clock_pre(clk, f); +- if (ret) +- goto out; +- +- if (core->pll) +- prog_core(priv, nv_clk_src_core_intm); +- +- prog_core(priv, nv_clk_src_core); +- prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); +- prog_clk(priv, 0x20, nv_clk_src_disp); +- prog_clk(priv, 0x21, nv_clk_src_vdec); +- prog_host(priv); +- +-out: +- if (ret == -EBUSY) +- f = NULL; +- +- nva3_clock_post(clk, f); +- +- return ret; +-} +- +-static void +-nva3_clock_tidy(struct nouveau_clock *clk) +-{ +-} +- +-static struct nouveau_clocks +-nva3_domain[] = { +- { nv_clk_src_crystal , 0xff }, +- { nv_clk_src_core , 0x00, 0, "core", 1000 }, +- { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, +- { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, +- { nv_clk_src_vdec , 0x03 }, +- { nv_clk_src_disp , 0x04 }, +- { nv_clk_src_host , 0x05 }, +- { nv_clk_src_core_intm, 0x06 }, +- { nv_clk_src_max } +-}; +- +-static int +-nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nva3_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0, +- false, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.read = nva3_clock_read; +- priv->base.calc = nva3_clock_calc; +- priv->base.prog = nva3_clock_prog; +- priv->base.tidy = nva3_clock_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nva3_clock_oclass = { +- .handle = NV_SUBDEV(CLOCK, 0xa3), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva3_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h +deleted file mode 100644 +index a45a1038..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nva3.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-#ifndef __NVKM_CLK_NVA3_H__ +-#define __NVKM_CLK_NVA3_H__ +- +-#include +- +-struct nva3_clock_info { +- u32 clk; +- u32 pll; +- enum { +- NVA3_HOST_277, +- NVA3_HOST_CLK, +- } host_out; +- u32 fb_delay; +-}; +- +-int nva3_pll_info(struct nouveau_clock *, int, u32, u32, +- struct nva3_clock_info *); +-int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags); +-void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags); +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c +deleted file mode 100644 +index 54aeab80..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c ++++ /dev/null +@@ -1,435 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "nva3.h" +-#include "pll.h" +- +-struct nvaa_clock_priv { +- struct nouveau_clock base; +- enum nv_clk_src csrc, ssrc, vsrc; +- u32 cctrl, sctrl; +- u32 ccoef, scoef; +- u32 cpost, spost; +- u32 vdiv; +-}; +- +-static u32 +-read_div(struct nouveau_clock *clk) +-{ +- return nv_rd32(clk, 0x004600); +-} +- +-static u32 +-read_pll(struct nouveau_clock *clk, u32 base) +-{ +- u32 ctrl = nv_rd32(clk, base + 0); +- u32 coef = nv_rd32(clk, base + 4); +- u32 ref = clk->read(clk, nv_clk_src_href); +- u32 post_div = 0; +- u32 clock = 0; +- int N1, M1; +- +- switch (base){ +- case 0x4020: +- post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); +- break; +- case 0x4028: +- post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; +- break; +- default: +- break; +- } +- +- N1 = (coef & 0x0000ff00) >> 8; +- M1 = (coef & 0x000000ff); +- if ((ctrl & 0x80000000) && M1) { +- clock = ref * N1 / M1; +- clock = clock / post_div; +- } +- +- return clock; +-} +- +-static int +-nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct nvaa_clock_priv *priv = (void *)clk; +- u32 mast = nv_rd32(clk, 0x00c054); +- u32 P = 0; +- +- switch (src) { +- case nv_clk_src_crystal: +- return nv_device(priv)->crystal; +- case nv_clk_src_href: +- return 100000; /* PCIE reference clock */ +- case nv_clk_src_hclkm4: +- return clk->read(clk, nv_clk_src_href) * 4; +- case nv_clk_src_hclkm2d3: +- return clk->read(clk, nv_clk_src_href) * 2 / 3; +- case nv_clk_src_host: +- switch (mast & 0x000c0000) { +- case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3); +- case 0x00040000: break; +- case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4); +- case 0x000c0000: return clk->read(clk, nv_clk_src_cclk); +- } +- break; +- case nv_clk_src_core: +- P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; +- +- switch (mast & 0x00000003) { +- case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; +- case 0x00000001: return 0; +- case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P; +- case 0x00000003: return read_pll(clk, 0x004028) >> P; +- } +- break; +- case nv_clk_src_cclk: +- if ((mast & 0x03000000) != 0x03000000) +- return clk->read(clk, nv_clk_src_core); +- +- if ((mast & 0x00000200) == 0x00000000) +- return clk->read(clk, nv_clk_src_core); +- +- switch (mast & 0x00000c00) { +- case 0x00000000: return clk->read(clk, nv_clk_src_href); +- case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4); +- case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3); +- default: return 0; +- } +- case nv_clk_src_shader: +- P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; +- switch (mast & 0x00000030) { +- case 0x00000000: +- if (mast & 0x00000040) +- return clk->read(clk, nv_clk_src_href) >> P; +- return clk->read(clk, nv_clk_src_crystal) >> P; +- case 0x00000010: break; +- case 0x00000020: return read_pll(clk, 0x004028) >> P; +- case 0x00000030: return read_pll(clk, 0x004020) >> P; +- } +- break; +- case nv_clk_src_mem: +- return 0; +- break; +- case nv_clk_src_vdec: +- P = (read_div(clk) & 0x00000700) >> 8; +- +- switch (mast & 0x00400000) { +- case 0x00400000: +- return clk->read(clk, nv_clk_src_core) >> P; +- break; +- default: +- return 500000 >> P; +- break; +- } +- break; +- default: +- break; +- } +- +- nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); +- return 0; +-} +- +-static u32 +-calc_pll(struct nvaa_clock_priv *priv, u32 reg, +- u32 clock, int *N, int *M, int *P) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll pll; +- struct nouveau_clock *clk = &priv->base; +- int ret; +- +- ret = nvbios_pll_parse(bios, reg, &pll); +- if (ret) +- return 0; +- +- pll.vco2.max_freq = 0; +- pll.refclk = clk->read(clk, nv_clk_src_href); +- if (!pll.refclk) +- return 0; +- +- return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); +-} +- +-static inline u32 +-calc_P(u32 src, u32 target, int *div) +-{ +- u32 clk0 = src, clk1 = src; +- for (*div = 0; *div <= 7; (*div)++) { +- if (clk0 <= target) { +- clk1 = clk0 << (*div ? 1 : 0); +- break; +- } +- clk0 >>= 1; +- } +- +- if (target - clk0 <= clk1 - target) +- return clk0; +- (*div)--; +- return clk1; +-} +- +-static int +-nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct nvaa_clock_priv *priv = (void *)clk; +- const int shader = cstate->domain[nv_clk_src_shader]; +- const int core = cstate->domain[nv_clk_src_core]; +- const int vdec = cstate->domain[nv_clk_src_vdec]; +- u32 out = 0, clock = 0; +- int N, M, P1, P2 = 0; +- int divs = 0; +- +- /* cclk: find suitable source, disable PLL if we can */ +- if (core < clk->read(clk, nv_clk_src_hclkm4)) +- out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs); +- +- /* Calculate clock * 2, so shader clock can use it too */ +- clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1); +- +- if (abs(core - out) <= +- abs(core - (clock >> 1))) { +- priv->csrc = nv_clk_src_hclkm4; +- priv->cctrl = divs << 16; +- } else { +- /* NVCTRL is actually used _after_ NVPOST, and after what we +- * call NVPLL. To make matters worse, NVPOST is an integer +- * divider instead of a right-shift number. */ +- if(P1 > 2) { +- P2 = P1 - 2; +- P1 = 2; +- } +- +- priv->csrc = nv_clk_src_core; +- priv->ccoef = (N << 8) | M; +- +- priv->cctrl = (P2 + 1) << 16; +- priv->cpost = (1 << P1) << 16; +- } +- +- /* sclk: nvpll + divisor, href or spll */ +- out = 0; +- if (shader == clk->read(clk, nv_clk_src_href)) { +- priv->ssrc = nv_clk_src_href; +- } else { +- clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1); +- if (priv->csrc == nv_clk_src_core) { +- out = calc_P((core << 1), shader, &divs); +- } +- +- if (abs(shader - out) <= +- abs(shader - clock) && +- (divs + P2) <= 7) { +- priv->ssrc = nv_clk_src_core; +- priv->sctrl = (divs + P2) << 16; +- } else { +- priv->ssrc = nv_clk_src_shader; +- priv->scoef = (N << 8) | M; +- priv->sctrl = P1 << 16; +- } +- } +- +- /* vclk */ +- out = calc_P(core, vdec, &divs); +- clock = calc_P(500000, vdec, &P1); +- if(abs(vdec - out) <= +- abs(vdec - clock)) { +- priv->vsrc = nv_clk_src_cclk; +- priv->vdiv = divs << 16; +- } else { +- priv->vsrc = nv_clk_src_vdec; +- priv->vdiv = P1 << 16; +- } +- +- /* Print strategy! */ +- nv_debug(priv, "nvpll: %08x %08x %08x\n", +- priv->ccoef, priv->cpost, priv->cctrl); +- nv_debug(priv, " spll: %08x %08x %08x\n", +- priv->scoef, priv->spost, priv->sctrl); +- nv_debug(priv, " vdiv: %08x\n", priv->vdiv); +- if (priv->csrc == nv_clk_src_hclkm4) +- nv_debug(priv, "core: hrefm4\n"); +- else +- nv_debug(priv, "core: nvpll\n"); +- +- if (priv->ssrc == nv_clk_src_hclkm4) +- nv_debug(priv, "shader: hrefm4\n"); +- else if (priv->ssrc == nv_clk_src_core) +- nv_debug(priv, "shader: nvpll\n"); +- else +- nv_debug(priv, "shader: spll\n"); +- +- if (priv->vsrc == nv_clk_src_hclkm4) +- nv_debug(priv, "vdec: 500MHz\n"); +- else +- nv_debug(priv, "vdec: core\n"); +- +- return 0; +-} +- +-static int +-nvaa_clock_prog(struct nouveau_clock *clk) +-{ +- struct nvaa_clock_priv *priv = (void *)clk; +- u32 pllmask = 0, mast; +- unsigned long flags; +- unsigned long *f = &flags; +- int ret = 0; +- +- ret = nva3_clock_pre(clk, f); +- if (ret) +- goto out; +- +- /* First switch to safe clocks: href */ +- mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); +- mast &= ~0x00400e73; +- mast |= 0x03000000; +- +- switch (priv->csrc) { +- case nv_clk_src_hclkm4: +- nv_mask(clk, 0x4028, 0x00070000, priv->cctrl); +- mast |= 0x00000002; +- break; +- case nv_clk_src_core: +- nv_wr32(clk, 0x402c, priv->ccoef); +- nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl); +- nv_wr32(clk, 0x4040, priv->cpost); +- pllmask |= (0x3 << 8); +- mast |= 0x00000003; +- break; +- default: +- nv_warn(priv,"Reclocking failed: unknown core clock\n"); +- goto resume; +- } +- +- switch (priv->ssrc) { +- case nv_clk_src_href: +- nv_mask(clk, 0x4020, 0x00070000, 0x00000000); +- /* mast |= 0x00000000; */ +- break; +- case nv_clk_src_core: +- nv_mask(clk, 0x4020, 0x00070000, priv->sctrl); +- mast |= 0x00000020; +- break; +- case nv_clk_src_shader: +- nv_wr32(clk, 0x4024, priv->scoef); +- nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl); +- nv_wr32(clk, 0x4070, priv->spost); +- pllmask |= (0x3 << 12); +- mast |= 0x00000030; +- break; +- default: +- nv_warn(priv,"Reclocking failed: unknown sclk clock\n"); +- goto resume; +- } +- +- if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { +- nv_warn(priv,"Reclocking failed: unstable PLLs\n"); +- goto resume; +- } +- +- switch (priv->vsrc) { +- case nv_clk_src_cclk: +- mast |= 0x00400000; +- default: +- nv_wr32(clk, 0x4600, priv->vdiv); +- } +- +- nv_wr32(clk, 0xc054, mast); +- +-resume: +- /* Disable some PLLs and dividers when unused */ +- if (priv->csrc != nv_clk_src_core) { +- nv_wr32(clk, 0x4040, 0x00000000); +- nv_mask(clk, 0x4028, 0x80000000, 0x00000000); +- } +- +- if (priv->ssrc != nv_clk_src_shader) { +- nv_wr32(clk, 0x4070, 0x00000000); +- nv_mask(clk, 0x4020, 0x80000000, 0x00000000); +- } +- +-out: +- if (ret == -EBUSY) +- f = NULL; +- +- nva3_clock_post(clk, f); +- +- return ret; +-} +- +-static void +-nvaa_clock_tidy(struct nouveau_clock *clk) +-{ +-} +- +-static struct nouveau_clocks +-nvaa_domains[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_href , 0xff }, +- { nv_clk_src_core , 0xff, 0, "core", 1000 }, +- { nv_clk_src_shader , 0xff, 0, "shader", 1000 }, +- { nv_clk_src_vdec , 0xff, 0, "vdec", 1000 }, +- { nv_clk_src_max } +-}; +- +-static int +-nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvaa_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL, +- 0, true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.read = nvaa_clock_read; +- priv->base.calc = nvaa_clock_calc; +- priv->base.prog = nvaa_clock_prog; +- priv->base.tidy = nvaa_clock_tidy; +- return 0; +-} +- +-struct nouveau_oclass * +-nvaa_clock_oclass = &(struct nouveau_oclass) { +- .handle = NV_SUBDEV(CLOCK, 0xaa), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvaa_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c +deleted file mode 100644 +index 1234abaa..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nvc0.c ++++ /dev/null +@@ -1,462 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include "pll.h" +- +-struct nvc0_clock_info { +- u32 freq; +- u32 ssel; +- u32 mdiv; +- u32 dsrc; +- u32 ddiv; +- u32 coef; +-}; +- +-struct nvc0_clock_priv { +- struct nouveau_clock base; +- struct nvc0_clock_info eng[16]; +-}; +- +-static u32 read_div(struct nvc0_clock_priv *, int, u32, u32); +- +-static u32 +-read_vco(struct nvc0_clock_priv *priv, u32 dsrc) +-{ +- struct nouveau_clock *clk = &priv->base; +- u32 ssrc = nv_rd32(priv, dsrc); +- if (!(ssrc & 0x00000100)) +- return clk->read(clk, nv_clk_src_sppll0); +- return clk->read(clk, nv_clk_src_sppll1); +-} +- +-static u32 +-read_pll(struct nvc0_clock_priv *priv, u32 pll) +-{ +- struct nouveau_clock *clk = &priv->base; +- u32 ctrl = nv_rd32(priv, pll + 0x00); +- u32 coef = nv_rd32(priv, pll + 0x04); +- u32 P = (coef & 0x003f0000) >> 16; +- u32 N = (coef & 0x0000ff00) >> 8; +- u32 M = (coef & 0x000000ff) >> 0; +- u32 sclk; +- +- if (!(ctrl & 0x00000001)) +- return 0; +- +- switch (pll) { +- case 0x00e800: +- case 0x00e820: +- sclk = nv_device(priv)->crystal; +- P = 1; +- break; +- case 0x132000: +- sclk = clk->read(clk, nv_clk_src_mpllsrc); +- break; +- case 0x132020: +- sclk = clk->read(clk, nv_clk_src_mpllsrcref); +- break; +- case 0x137000: +- case 0x137020: +- case 0x137040: +- case 0x1370e0: +- sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); +- break; +- default: +- return 0; +- } +- +- return sclk * N / M / P; +-} +- +-static u32 +-read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) +-{ +- u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); +- u32 sctl = nv_rd32(priv, dctl + (doff * 4)); +- +- switch (ssrc & 0x00000003) { +- case 0: +- if ((ssrc & 0x00030000) != 0x00030000) +- return nv_device(priv)->crystal; +- return 108000; +- case 2: +- return 100000; +- case 3: +- if (sctl & 0x80000000) { +- u32 sclk = read_vco(priv, dsrc + (doff * 4)); +- u32 sdiv = (sctl & 0x0000003f) + 2; +- return (sclk * 2) / sdiv; +- } +- +- return read_vco(priv, dsrc + (doff * 4)); +- default: +- return 0; +- } +-} +- +-static u32 +-read_clk(struct nvc0_clock_priv *priv, int clk) +-{ +- u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); +- u32 ssel = nv_rd32(priv, 0x137100); +- u32 sclk, sdiv; +- +- if (ssel & (1 << clk)) { +- if (clk < 7) +- sclk = read_pll(priv, 0x137000 + (clk * 0x20)); +- else +- sclk = read_pll(priv, 0x1370e0); +- sdiv = ((sctl & 0x00003f00) >> 8) + 2; +- } else { +- sclk = read_div(priv, clk, 0x137160, 0x1371d0); +- sdiv = ((sctl & 0x0000003f) >> 0) + 2; +- } +- +- if (sctl & 0x80000000) +- return (sclk * 2) / sdiv; +- +- return sclk; +-} +- +-static int +-nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct nouveau_device *device = nv_device(clk); +- struct nvc0_clock_priv *priv = (void *)clk; +- +- switch (src) { +- case nv_clk_src_crystal: +- return device->crystal; +- case nv_clk_src_href: +- return 100000; +- case nv_clk_src_sppll0: +- return read_pll(priv, 0x00e800); +- case nv_clk_src_sppll1: +- return read_pll(priv, 0x00e820); +- +- case nv_clk_src_mpllsrcref: +- return read_div(priv, 0, 0x137320, 0x137330); +- case nv_clk_src_mpllsrc: +- return read_pll(priv, 0x132020); +- case nv_clk_src_mpll: +- return read_pll(priv, 0x132000); +- case nv_clk_src_mdiv: +- return read_div(priv, 0, 0x137300, 0x137310); +- case nv_clk_src_mem: +- if (nv_rd32(priv, 0x1373f0) & 0x00000002) +- return clk->read(clk, nv_clk_src_mpll); +- return clk->read(clk, nv_clk_src_mdiv); +- +- case nv_clk_src_gpc: +- return read_clk(priv, 0x00); +- case nv_clk_src_rop: +- return read_clk(priv, 0x01); +- case nv_clk_src_hubk07: +- return read_clk(priv, 0x02); +- case nv_clk_src_hubk06: +- return read_clk(priv, 0x07); +- case nv_clk_src_hubk01: +- return read_clk(priv, 0x08); +- case nv_clk_src_copy: +- return read_clk(priv, 0x09); +- case nv_clk_src_daemon: +- return read_clk(priv, 0x0c); +- case nv_clk_src_vdec: +- return read_clk(priv, 0x0e); +- default: +- nv_error(clk, "invalid clock source %d\n", src); +- return -EINVAL; +- } +-} +- +-static u32 +-calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) +-{ +- u32 div = min((ref * 2) / freq, (u32)65); +- if (div < 2) +- div = 2; +- +- *ddiv = div - 2; +- return (ref * 2) / div; +-} +- +-static u32 +-calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) +-{ +- u32 sclk; +- +- /* use one of the fixed frequencies if possible */ +- *ddiv = 0x00000000; +- switch (freq) { +- case 27000: +- case 108000: +- *dsrc = 0x00000000; +- if (freq == 108000) +- *dsrc |= 0x00030000; +- return freq; +- case 100000: +- *dsrc = 0x00000002; +- return freq; +- default: +- *dsrc = 0x00000003; +- break; +- } +- +- /* otherwise, calculate the closest divider */ +- sclk = read_vco(priv, 0x137160 + (clk * 4)); +- if (clk < 7) +- sclk = calc_div(priv, clk, sclk, freq, ddiv); +- return sclk; +-} +- +-static u32 +-calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll limits; +- int N, M, P, ret; +- +- ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); +- if (ret) +- return 0; +- +- limits.refclk = read_div(priv, clk, 0x137120, 0x137140); +- if (!limits.refclk) +- return 0; +- +- ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); +- if (ret <= 0) +- return 0; +- +- *coef = (P << 16) | (N << 8) | M; +- return ret; +-} +- +-static int +-calc_clk(struct nvc0_clock_priv *priv, +- struct nouveau_cstate *cstate, int clk, int dom) +-{ +- struct nvc0_clock_info *info = &priv->eng[clk]; +- u32 freq = cstate->domain[dom]; +- u32 src0, div0, div1D, div1P = 0; +- u32 clk0, clk1 = 0; +- +- /* invalid clock domain */ +- if (!freq) +- return 0; +- +- /* first possible path, using only dividers */ +- clk0 = calc_src(priv, clk, freq, &src0, &div0); +- clk0 = calc_div(priv, clk, clk0, freq, &div1D); +- +- /* see if we can get any closer using PLLs */ +- if (clk0 != freq && (0x00004387 & (1 << clk))) { +- if (clk <= 7) +- clk1 = calc_pll(priv, clk, freq, &info->coef); +- else +- clk1 = cstate->domain[nv_clk_src_hubk06]; +- clk1 = calc_div(priv, clk, clk1, freq, &div1P); +- } +- +- /* select the method which gets closest to target freq */ +- if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { +- info->dsrc = src0; +- if (div0) { +- info->ddiv |= 0x80000000; +- info->ddiv |= div0 << 8; +- info->ddiv |= div0; +- } +- if (div1D) { +- info->mdiv |= 0x80000000; +- info->mdiv |= div1D; +- } +- info->ssel = info->coef = 0; +- info->freq = clk0; +- } else { +- if (div1P) { +- info->mdiv |= 0x80000000; +- info->mdiv |= div1P << 8; +- } +- info->ssel = (1 << clk); +- info->freq = clk1; +- } +- +- return 0; +-} +- +-static int +-nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct nvc0_clock_priv *priv = (void *)clk; +- int ret; +- +- if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || +- (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || +- (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || +- (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || +- (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || +- (ret = calc_clk(priv, cstate, 0x09, nv_clk_src_copy)) || +- (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || +- (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) +- return ret; +- +- return 0; +-} +- +-static void +-nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk) +-{ +- struct nvc0_clock_info *info = &priv->eng[clk]; +- if (clk < 7 && !info->ssel) { +- nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv); +- nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); +- } +-} +- +-static void +-nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk) +-{ +- nv_mask(priv, 0x137100, (1 << clk), 0x00000000); +- nv_wait(priv, 0x137100, (1 << clk), 0x00000000); +-} +- +-static void +-nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk) +-{ +- struct nvc0_clock_info *info = &priv->eng[clk]; +- const u32 addr = 0x137000 + (clk * 0x20); +- if (clk <= 7) { +- nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); +- nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); +- if (info->coef) { +- nv_wr32(priv, addr + 0x04, info->coef); +- nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); +- nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); +- nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); +- } +- } +-} +- +-static void +-nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk) +-{ +- struct nvc0_clock_info *info = &priv->eng[clk]; +- if (info->ssel) { +- nv_mask(priv, 0x137100, (1 << clk), info->ssel); +- nv_wait(priv, 0x137100, (1 << clk), info->ssel); +- } +-} +- +-static void +-nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk) +-{ +- struct nvc0_clock_info *info = &priv->eng[clk]; +- nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv); +-} +- +-static int +-nvc0_clock_prog(struct nouveau_clock *clk) +-{ +- struct nvc0_clock_priv *priv = (void *)clk; +- struct { +- void (*exec)(struct nvc0_clock_priv *, int); +- } stage[] = { +- { nvc0_clock_prog_0 }, /* div programming */ +- { nvc0_clock_prog_1 }, /* select div mode */ +- { nvc0_clock_prog_2 }, /* (maybe) program pll */ +- { nvc0_clock_prog_3 }, /* (maybe) select pll mode */ +- { nvc0_clock_prog_4 }, /* final divider */ +- }; +- int i, j; +- +- for (i = 0; i < ARRAY_SIZE(stage); i++) { +- for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { +- if (!priv->eng[j].freq) +- continue; +- stage[i].exec(priv, j); +- } +- } +- +- return 0; +-} +- +-static void +-nvc0_clock_tidy(struct nouveau_clock *clk) +-{ +- struct nvc0_clock_priv *priv = (void *)clk; +- memset(priv->eng, 0x00, sizeof(priv->eng)); +-} +- +-static struct nouveau_clocks +-nvc0_domain[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_href , 0xff }, +- { nv_clk_src_hubk06 , 0x00 }, +- { nv_clk_src_hubk01 , 0x01 }, +- { nv_clk_src_copy , 0x02 }, +- { nv_clk_src_gpc , 0x03, 0, "core", 2000 }, +- { nv_clk_src_rop , 0x04 }, +- { nv_clk_src_mem , 0x05, 0, "memory", 1000 }, +- { nv_clk_src_vdec , 0x06 }, +- { nv_clk_src_daemon , 0x0a }, +- { nv_clk_src_hubk07 , 0x0b }, +- { nv_clk_src_max } +-}; +- +-static int +-nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0, +- false, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.read = nvc0_clock_read; +- priv->base.calc = nvc0_clock_calc; +- priv->base.prog = nvc0_clock_prog; +- priv->base.tidy = nvc0_clock_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_clock_oclass = { +- .handle = NV_SUBDEV(CLOCK, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c +deleted file mode 100644 +index 7eccad57..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/nve0.c ++++ /dev/null +@@ -1,500 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include "pll.h" +- +-struct nve0_clock_info { +- u32 freq; +- u32 ssel; +- u32 mdiv; +- u32 dsrc; +- u32 ddiv; +- u32 coef; +-}; +- +-struct nve0_clock_priv { +- struct nouveau_clock base; +- struct nve0_clock_info eng[16]; +-}; +- +-static u32 read_div(struct nve0_clock_priv *, int, u32, u32); +-static u32 read_pll(struct nve0_clock_priv *, u32); +- +-static u32 +-read_vco(struct nve0_clock_priv *priv, u32 dsrc) +-{ +- u32 ssrc = nv_rd32(priv, dsrc); +- if (!(ssrc & 0x00000100)) +- return read_pll(priv, 0x00e800); +- return read_pll(priv, 0x00e820); +-} +- +-static u32 +-read_pll(struct nve0_clock_priv *priv, u32 pll) +-{ +- u32 ctrl = nv_rd32(priv, pll + 0x00); +- u32 coef = nv_rd32(priv, pll + 0x04); +- u32 P = (coef & 0x003f0000) >> 16; +- u32 N = (coef & 0x0000ff00) >> 8; +- u32 M = (coef & 0x000000ff) >> 0; +- u32 sclk; +- u16 fN = 0xf000; +- +- if (!(ctrl & 0x00000001)) +- return 0; +- +- switch (pll) { +- case 0x00e800: +- case 0x00e820: +- sclk = nv_device(priv)->crystal; +- P = 1; +- break; +- case 0x132000: +- sclk = read_pll(priv, 0x132020); +- P = (coef & 0x10000000) ? 2 : 1; +- break; +- case 0x132020: +- sclk = read_div(priv, 0, 0x137320, 0x137330); +- fN = nv_rd32(priv, pll + 0x10) >> 16; +- break; +- case 0x137000: +- case 0x137020: +- case 0x137040: +- case 0x1370e0: +- sclk = read_div(priv, (pll & 0xff) / 0x20, 0x137120, 0x137140); +- break; +- default: +- return 0; +- } +- +- if (P == 0) +- P = 1; +- +- sclk = (sclk * N) + (((u16)(fN + 4096) * sclk) >> 13); +- return sclk / (M * P); +-} +- +-static u32 +-read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl) +-{ +- u32 ssrc = nv_rd32(priv, dsrc + (doff * 4)); +- u32 sctl = nv_rd32(priv, dctl + (doff * 4)); +- +- switch (ssrc & 0x00000003) { +- case 0: +- if ((ssrc & 0x00030000) != 0x00030000) +- return nv_device(priv)->crystal; +- return 108000; +- case 2: +- return 100000; +- case 3: +- if (sctl & 0x80000000) { +- u32 sclk = read_vco(priv, dsrc + (doff * 4)); +- u32 sdiv = (sctl & 0x0000003f) + 2; +- return (sclk * 2) / sdiv; +- } +- +- return read_vco(priv, dsrc + (doff * 4)); +- default: +- return 0; +- } +-} +- +-static u32 +-read_mem(struct nve0_clock_priv *priv) +-{ +- switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) { +- case 1: return read_pll(priv, 0x132020); +- case 2: return read_pll(priv, 0x132000); +- default: +- return 0; +- } +-} +- +-static u32 +-read_clk(struct nve0_clock_priv *priv, int clk) +-{ +- u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4)); +- u32 sclk, sdiv; +- +- if (clk < 7) { +- u32 ssel = nv_rd32(priv, 0x137100); +- if (ssel & (1 << clk)) { +- sclk = read_pll(priv, 0x137000 + (clk * 0x20)); +- sdiv = 1; +- } else { +- sclk = read_div(priv, clk, 0x137160, 0x1371d0); +- sdiv = 0; +- } +- } else { +- u32 ssrc = nv_rd32(priv, 0x137160 + (clk * 0x04)); +- if ((ssrc & 0x00000003) == 0x00000003) { +- sclk = read_div(priv, clk, 0x137160, 0x1371d0); +- if (ssrc & 0x00000100) { +- if (ssrc & 0x40000000) +- sclk = read_pll(priv, 0x1370e0); +- sdiv = 1; +- } else { +- sdiv = 0; +- } +- } else { +- sclk = read_div(priv, clk, 0x137160, 0x1371d0); +- sdiv = 0; +- } +- } +- +- if (sctl & 0x80000000) { +- if (sdiv) +- sdiv = ((sctl & 0x00003f00) >> 8) + 2; +- else +- sdiv = ((sctl & 0x0000003f) >> 0) + 2; +- return (sclk * 2) / sdiv; +- } +- +- return sclk; +-} +- +-static int +-nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) +-{ +- struct nouveau_device *device = nv_device(clk); +- struct nve0_clock_priv *priv = (void *)clk; +- +- switch (src) { +- case nv_clk_src_crystal: +- return device->crystal; +- case nv_clk_src_href: +- return 100000; +- case nv_clk_src_mem: +- return read_mem(priv); +- case nv_clk_src_gpc: +- return read_clk(priv, 0x00); +- case nv_clk_src_rop: +- return read_clk(priv, 0x01); +- case nv_clk_src_hubk07: +- return read_clk(priv, 0x02); +- case nv_clk_src_hubk06: +- return read_clk(priv, 0x07); +- case nv_clk_src_hubk01: +- return read_clk(priv, 0x08); +- case nv_clk_src_daemon: +- return read_clk(priv, 0x0c); +- case nv_clk_src_vdec: +- return read_clk(priv, 0x0e); +- default: +- nv_error(clk, "invalid clock source %d\n", src); +- return -EINVAL; +- } +-} +- +-static u32 +-calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv) +-{ +- u32 div = min((ref * 2) / freq, (u32)65); +- if (div < 2) +- div = 2; +- +- *ddiv = div - 2; +- return (ref * 2) / div; +-} +- +-static u32 +-calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv) +-{ +- u32 sclk; +- +- /* use one of the fixed frequencies if possible */ +- *ddiv = 0x00000000; +- switch (freq) { +- case 27000: +- case 108000: +- *dsrc = 0x00000000; +- if (freq == 108000) +- *dsrc |= 0x00030000; +- return freq; +- case 100000: +- *dsrc = 0x00000002; +- return freq; +- default: +- *dsrc = 0x00000003; +- break; +- } +- +- /* otherwise, calculate the closest divider */ +- sclk = read_vco(priv, 0x137160 + (clk * 4)); +- if (clk < 7) +- sclk = calc_div(priv, clk, sclk, freq, ddiv); +- return sclk; +-} +- +-static u32 +-calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef) +-{ +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll limits; +- int N, M, P, ret; +- +- ret = nvbios_pll_parse(bios, 0x137000 + (clk * 0x20), &limits); +- if (ret) +- return 0; +- +- limits.refclk = read_div(priv, clk, 0x137120, 0x137140); +- if (!limits.refclk) +- return 0; +- +- ret = nva3_pll_calc(nv_subdev(priv), &limits, freq, &N, NULL, &M, &P); +- if (ret <= 0) +- return 0; +- +- *coef = (P << 16) | (N << 8) | M; +- return ret; +-} +- +-static int +-calc_clk(struct nve0_clock_priv *priv, +- struct nouveau_cstate *cstate, int clk, int dom) +-{ +- struct nve0_clock_info *info = &priv->eng[clk]; +- u32 freq = cstate->domain[dom]; +- u32 src0, div0, div1D, div1P = 0; +- u32 clk0, clk1 = 0; +- +- /* invalid clock domain */ +- if (!freq) +- return 0; +- +- /* first possible path, using only dividers */ +- clk0 = calc_src(priv, clk, freq, &src0, &div0); +- clk0 = calc_div(priv, clk, clk0, freq, &div1D); +- +- /* see if we can get any closer using PLLs */ +- if (clk0 != freq && (0x0000ff87 & (1 << clk))) { +- if (clk <= 7) +- clk1 = calc_pll(priv, clk, freq, &info->coef); +- else +- clk1 = cstate->domain[nv_clk_src_hubk06]; +- clk1 = calc_div(priv, clk, clk1, freq, &div1P); +- } +- +- /* select the method which gets closest to target freq */ +- if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { +- info->dsrc = src0; +- if (div0) { +- info->ddiv |= 0x80000000; +- info->ddiv |= div0; +- } +- if (div1D) { +- info->mdiv |= 0x80000000; +- info->mdiv |= div1D; +- } +- info->ssel = 0; +- info->freq = clk0; +- } else { +- if (div1P) { +- info->mdiv |= 0x80000000; +- info->mdiv |= div1P << 8; +- } +- info->ssel = (1 << clk); +- info->dsrc = 0x40000100; +- info->freq = clk1; +- } +- +- return 0; +-} +- +-static int +-nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) +-{ +- struct nve0_clock_priv *priv = (void *)clk; +- int ret; +- +- if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) || +- (ret = calc_clk(priv, cstate, 0x01, nv_clk_src_rop)) || +- (ret = calc_clk(priv, cstate, 0x02, nv_clk_src_hubk07)) || +- (ret = calc_clk(priv, cstate, 0x07, nv_clk_src_hubk06)) || +- (ret = calc_clk(priv, cstate, 0x08, nv_clk_src_hubk01)) || +- (ret = calc_clk(priv, cstate, 0x0c, nv_clk_src_daemon)) || +- (ret = calc_clk(priv, cstate, 0x0e, nv_clk_src_vdec))) +- return ret; +- +- return 0; +-} +- +-static void +-nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk) +-{ +- struct nve0_clock_info *info = &priv->eng[clk]; +- if (!info->ssel) { +- nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv); +- nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc); +- } +-} +- +-static void +-nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk) +-{ +- nv_mask(priv, 0x137100, (1 << clk), 0x00000000); +- nv_wait(priv, 0x137100, (1 << clk), 0x00000000); +-} +- +-static void +-nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk) +-{ +- nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000); +-} +- +-static void +-nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk) +-{ +- struct nve0_clock_info *info = &priv->eng[clk]; +- const u32 addr = 0x137000 + (clk * 0x20); +- nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000); +- nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000); +- if (info->coef) { +- nv_wr32(priv, addr + 0x04, info->coef); +- nv_mask(priv, addr + 0x00, 0x00000001, 0x00000001); +- nv_wait(priv, addr + 0x00, 0x00020000, 0x00020000); +- nv_mask(priv, addr + 0x00, 0x00020004, 0x00000004); +- } +-} +- +-static void +-nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk) +-{ +- struct nve0_clock_info *info = &priv->eng[clk]; +- if (info->ssel) +- nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv); +- else +- nv_mask(priv, 0x137250 + (clk * 0x04), 0x0000003f, info->mdiv); +-} +- +-static void +-nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk) +-{ +- struct nve0_clock_info *info = &priv->eng[clk]; +- if (info->ssel) { +- nv_mask(priv, 0x137100, (1 << clk), info->ssel); +- nv_wait(priv, 0x137100, (1 << clk), info->ssel); +- } +-} +- +-static void +-nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk) +-{ +- struct nve0_clock_info *info = &priv->eng[clk]; +- if (info->ssel) { +- nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000); +- nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100); +- } +-} +- +-static int +-nve0_clock_prog(struct nouveau_clock *clk) +-{ +- struct nve0_clock_priv *priv = (void *)clk; +- struct { +- u32 mask; +- void (*exec)(struct nve0_clock_priv *, int); +- } stage[] = { +- { 0x007f, nve0_clock_prog_0 }, /* div programming */ +- { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */ +- { 0xff80, nve0_clock_prog_1_1 }, +- { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */ +- { 0xff80, nve0_clock_prog_3 }, /* final divider */ +- { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */ +- { 0xff80, nve0_clock_prog_4_1 }, +- }; +- int i, j; +- +- for (i = 0; i < ARRAY_SIZE(stage); i++) { +- for (j = 0; j < ARRAY_SIZE(priv->eng); j++) { +- if (!(stage[i].mask & (1 << j))) +- continue; +- if (!priv->eng[j].freq) +- continue; +- stage[i].exec(priv, j); +- } +- } +- +- return 0; +-} +- +-static void +-nve0_clock_tidy(struct nouveau_clock *clk) +-{ +- struct nve0_clock_priv *priv = (void *)clk; +- memset(priv->eng, 0x00, sizeof(priv->eng)); +-} +- +-static struct nouveau_clocks +-nve0_domain[] = { +- { nv_clk_src_crystal, 0xff }, +- { nv_clk_src_href , 0xff }, +- { nv_clk_src_gpc , 0x00, NVKM_CLK_DOM_FLAG_CORE, "core", 2000 }, +- { nv_clk_src_hubk07 , 0x01, NVKM_CLK_DOM_FLAG_CORE }, +- { nv_clk_src_rop , 0x02, NVKM_CLK_DOM_FLAG_CORE }, +- { nv_clk_src_mem , 0x03, 0, "memory", 500 }, +- { nv_clk_src_hubk06 , 0x04, NVKM_CLK_DOM_FLAG_CORE }, +- { nv_clk_src_hubk01 , 0x05 }, +- { nv_clk_src_vdec , 0x06 }, +- { nv_clk_src_daemon , 0x07 }, +- { nv_clk_src_max } +-}; +- +-static int +-nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_clock_priv *priv; +- int ret; +- +- ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0, +- true, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.read = nve0_clock_read; +- priv->base.calc = nve0_clock_calc; +- priv->base.prog = nve0_clock_prog; +- priv->base.tidy = nve0_clock_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nve0_clock_oclass = { +- .handle = NV_SUBDEV(CLOCK, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_clock_ctor, +- .dtor = _nouveau_clock_dtor, +- .init = _nouveau_clock_init, +- .fini = _nouveau_clock_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h +deleted file mode 100644 +index 445b14c3..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pll.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NOUVEAU_PLL_H__ +-#define __NOUVEAU_PLL_H__ +- +-int nv04_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, +- int *N1, int *M1, int *N2, int *M2, int *P); +-int nva3_pll_calc(struct nouveau_subdev *, struct nvbios_pll *, u32 freq, +- int *N, int *fN, int *M, int *P); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c +deleted file mode 100644 +index b47d543a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnv04.c ++++ /dev/null +@@ -1,246 +0,0 @@ +-/* +- * Copyright 1993-2003 NVIDIA, Corporation +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#include +-#include +- +-#include "pll.h" +- +-static int +-getMNP_single(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, +- int *pN, int *pM, int *pP) +-{ +- /* Find M, N and P for a single stage PLL +- * +- * Note that some bioses (NV3x) have lookup tables of precomputed MNP +- * values, but we're too lazy to use those atm +- * +- * "clk" parameter in kHz +- * returns calculated clock +- */ +- struct nouveau_bios *bios = nouveau_bios(subdev); +- int minvco = info->vco1.min_freq, maxvco = info->vco1.max_freq; +- int minM = info->vco1.min_m, maxM = info->vco1.max_m; +- int minN = info->vco1.min_n, maxN = info->vco1.max_n; +- int minU = info->vco1.min_inputfreq; +- int maxU = info->vco1.max_inputfreq; +- int minP = info->min_p; +- int maxP = info->max_p_usable; +- int crystal = info->refclk; +- int M, N, thisP, P; +- int clkP, calcclk; +- int delta, bestdelta = INT_MAX; +- int bestclk = 0; +- +- /* this division verified for nv20, nv18, nv28 (Haiku), and nv34 */ +- /* possibly correlated with introduction of 27MHz crystal */ +- if (bios->version.major < 0x60) { +- int cv = bios->version.chip; +- if (cv < 0x17 || cv == 0x1a || cv == 0x20) { +- if (clk > 250000) +- maxM = 6; +- if (clk > 340000) +- maxM = 2; +- } else if (cv < 0x40) { +- if (clk > 150000) +- maxM = 6; +- if (clk > 200000) +- maxM = 4; +- if (clk > 340000) +- maxM = 2; +- } +- } +- +- P = 1 << maxP; +- if ((clk * P) < minvco) { +- minvco = clk * maxP; +- maxvco = minvco * 2; +- } +- +- if (clk + clk/200 > maxvco) /* +0.5% */ +- maxvco = clk + clk/200; +- +- /* NV34 goes maxlog2P->0, NV20 goes 0->maxlog2P */ +- for (thisP = minP; thisP <= maxP; thisP++) { +- P = 1 << thisP; +- clkP = clk * P; +- +- if (clkP < minvco) +- continue; +- if (clkP > maxvco) +- return bestclk; +- +- for (M = minM; M <= maxM; M++) { +- if (crystal/M < minU) +- return bestclk; +- if (crystal/M > maxU) +- continue; +- +- /* add crystal/2 to round better */ +- N = (clkP * M + crystal/2) / crystal; +- +- if (N < minN) +- continue; +- if (N > maxN) +- break; +- +- /* more rounding additions */ +- calcclk = ((N * crystal + P/2) / P + M/2) / M; +- delta = abs(calcclk - clk); +- /* we do an exhaustive search rather than terminating +- * on an optimality condition... +- */ +- if (delta < bestdelta) { +- bestdelta = delta; +- bestclk = calcclk; +- *pN = N; +- *pM = M; +- *pP = thisP; +- if (delta == 0) /* except this one */ +- return bestclk; +- } +- } +- } +- +- return bestclk; +-} +- +-static int +-getMNP_double(struct nouveau_subdev *subdev, struct nvbios_pll *info, int clk, +- int *pN1, int *pM1, int *pN2, int *pM2, int *pP) +-{ +- /* Find M, N and P for a two stage PLL +- * +- * Note that some bioses (NV30+) have lookup tables of precomputed MNP +- * values, but we're too lazy to use those atm +- * +- * "clk" parameter in kHz +- * returns calculated clock +- */ +- int chip_version = nouveau_bios(subdev)->version.chip; +- int minvco1 = info->vco1.min_freq, maxvco1 = info->vco1.max_freq; +- int minvco2 = info->vco2.min_freq, maxvco2 = info->vco2.max_freq; +- int minU1 = info->vco1.min_inputfreq, minU2 = info->vco2.min_inputfreq; +- int maxU1 = info->vco1.max_inputfreq, maxU2 = info->vco2.max_inputfreq; +- int minM1 = info->vco1.min_m, maxM1 = info->vco1.max_m; +- int minN1 = info->vco1.min_n, maxN1 = info->vco1.max_n; +- int minM2 = info->vco2.min_m, maxM2 = info->vco2.max_m; +- int minN2 = info->vco2.min_n, maxN2 = info->vco2.max_n; +- int maxlog2P = info->max_p_usable; +- int crystal = info->refclk; +- bool fixedgain2 = (minM2 == maxM2 && minN2 == maxN2); +- int M1, N1, M2, N2, log2P; +- int clkP, calcclk1, calcclk2, calcclkout; +- int delta, bestdelta = INT_MAX; +- int bestclk = 0; +- +- int vco2 = (maxvco2 - maxvco2/200) / 2; +- for (log2P = 0; clk && log2P < maxlog2P && clk <= (vco2 >> log2P); log2P++) +- ; +- clkP = clk << log2P; +- +- if (maxvco2 < clk + clk/200) /* +0.5% */ +- maxvco2 = clk + clk/200; +- +- for (M1 = minM1; M1 <= maxM1; M1++) { +- if (crystal/M1 < minU1) +- return bestclk; +- if (crystal/M1 > maxU1) +- continue; +- +- for (N1 = minN1; N1 <= maxN1; N1++) { +- calcclk1 = crystal * N1 / M1; +- if (calcclk1 < minvco1) +- continue; +- if (calcclk1 > maxvco1) +- break; +- +- for (M2 = minM2; M2 <= maxM2; M2++) { +- if (calcclk1/M2 < minU2) +- break; +- if (calcclk1/M2 > maxU2) +- continue; +- +- /* add calcclk1/2 to round better */ +- N2 = (clkP * M2 + calcclk1/2) / calcclk1; +- if (N2 < minN2) +- continue; +- if (N2 > maxN2) +- break; +- +- if (!fixedgain2) { +- if (chip_version < 0x60) +- if (N2/M2 < 4 || N2/M2 > 10) +- continue; +- +- calcclk2 = calcclk1 * N2 / M2; +- if (calcclk2 < minvco2) +- break; +- if (calcclk2 > maxvco2) +- continue; +- } else +- calcclk2 = calcclk1; +- +- calcclkout = calcclk2 >> log2P; +- delta = abs(calcclkout - clk); +- /* we do an exhaustive search rather than terminating +- * on an optimality condition... +- */ +- if (delta < bestdelta) { +- bestdelta = delta; +- bestclk = calcclkout; +- *pN1 = N1; +- *pM1 = M1; +- *pN2 = N2; +- *pM2 = M2; +- *pP = log2P; +- if (delta == 0) /* except this one */ +- return bestclk; +- } +- } +- } +- } +- +- return bestclk; +-} +- +-int +-nv04_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, u32 freq, +- int *N1, int *M1, int *N2, int *M2, int *P) +-{ +- int ret; +- +- if (!info->vco2.max_freq || !N2) { +- ret = getMNP_single(subdev, info, freq, N1, M1, P); +- if (N2) { +- *N2 = 1; +- *M2 = 1; +- } +- } else { +- ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); +- } +- +- if (!ret) +- nv_error(subdev, "unable to compute acceptable pll values\n"); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c +deleted file mode 100644 +index 8eca457c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/pllnva3.c ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "pll.h" +- +-int +-nva3_pll_calc(struct nouveau_subdev *subdev, struct nvbios_pll *info, +- u32 freq, int *pN, int *pfN, int *pM, int *P) +-{ +- u32 best_err = ~0, err; +- int M, lM, hM, N, fN; +- +- *P = info->vco1.max_freq / freq; +- if (*P > info->max_p) +- *P = info->max_p; +- if (*P < info->min_p) +- *P = info->min_p; +- +- lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; +- lM = max(lM, (int)info->vco1.min_m); +- hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; +- hM = min(hM, (int)info->vco1.max_m); +- lM = min(lM, hM); +- +- for (M = lM; M <= hM; M++) { +- u32 tmp = freq * *P * M; +- N = tmp / info->refclk; +- fN = tmp % info->refclk; +- +- if (!pfN) { +- if (fN >= info->refclk / 2) +- N++; +- } else { +- if (fN < info->refclk / 2) +- N--; +- fN = tmp - (N * info->refclk); +- } +- +- if (N < info->vco1.min_n) +- continue; +- if (N > info->vco1.max_n) +- break; +- +- err = abs(freq - (info->refclk * N / M / *P)); +- if (err < best_err) { +- best_err = err; +- *pN = N; +- *pM = M; +- } +- +- if (pfN) { +- *pfN = ((fN << 13) + info->refclk / 2) / info->refclk; +- *pfN = (*pfN - 4096) & 0xffff; +- return freq; +- } +- } +- +- if (unlikely(best_err == ~0)) { +- nv_error(subdev, "unable to find matching pll values\n"); +- return -EINVAL; +- } +- +- return info->refclk * *pN / *pM / *P; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h +deleted file mode 100644 +index fb33f06e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/clock/seq.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-#ifndef __NVKM_CLK_SEQ_H__ +-#define __NVKM_CLK_SEQ_H__ +- +-#include +-#include +- +-#define clk_init(s,p) hwsq_init(&(s)->base, (p)) +-#define clk_exec(s,e) hwsq_exec(&(s)->base, (e)) +-#define clk_have(s,r) ((s)->r_##r.addr != 0x000000) +-#define clk_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) +-#define clk_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) +-#define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) +-#define clk_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) +-#define clk_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) +-#define clk_nsec(s,n) hwsq_nsec(&(s)->base, (n)) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c +deleted file mode 100644 +index 239acfe8..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/base.c ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +- +-#include "priv.h" +- +-int +-_nouveau_devinit_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_devinit *devinit = (void *)object; +- +- /* force full reinit on resume */ +- if (suspend) +- devinit->post = true; +- +- /* unlock the extended vga crtc regs */ +- nv_lockvgac(devinit, false); +- +- return nouveau_subdev_fini(&devinit->base, suspend); +-} +- +-int +-_nouveau_devinit_init(struct nouveau_object *object) +-{ +- struct nouveau_devinit_impl *impl = (void *)object->oclass; +- struct nouveau_devinit *devinit = (void *)object; +- int ret; +- +- ret = nouveau_subdev_init(&devinit->base); +- if (ret) +- return ret; +- +- ret = nvbios_init(&devinit->base, devinit->post); +- if (ret) +- return ret; +- +- if (impl->disable) +- nv_device(devinit)->disable_mask |= impl->disable(devinit); +- return 0; +-} +- +-void +-_nouveau_devinit_dtor(struct nouveau_object *object) +-{ +- struct nouveau_devinit *devinit = (void *)object; +- +- /* lock crtc regs */ +- nv_lockvgac(devinit, true); +- +- nouveau_subdev_destroy(&devinit->base); +-} +- +-int +-nouveau_devinit_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int size, void **pobject) +-{ +- struct nouveau_devinit_impl *impl = (void *)oclass; +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_devinit *devinit; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "DEVINIT", +- "init", size, pobject); +- devinit = *pobject; +- if (ret) +- return ret; +- +- devinit->post = nouveau_boolopt(device->cfgopt, "NvForcePost", false); +- devinit->meminit = impl->meminit; +- devinit->pll_set = impl->pll_set; +- devinit->mmio = impl->mmio; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h +deleted file mode 100644 +index 6103484f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/fbmem.h ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +- +-#include +- +-#define NV04_PFB_DEBUG_0 0x00100080 +-# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001 +-# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010 +-# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00 +-# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000 +-# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000 +-# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000 +-# define NV04_PFB_DEBUG_0_CASOE 0x00100000 +-# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000 +-# define NV04_PFB_DEBUG_0_REFINC 0x20000000 +-# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000 +-#define NV04_PFB_CFG0 0x00100200 +-# define NV04_PFB_CFG0_SCRAMBLE 0x20000000 +-#define NV04_PFB_CFG1 0x00100204 +-#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i)) +- +-#define NV10_PFB_REFCTRL 0x00100210 +-# define NV10_PFB_REFCTRL_VALID_1 (1 << 31) +- +-static inline struct io_mapping * +-fbmem_init(struct nouveau_device *dev) +-{ +- return io_mapping_create_wc(nv_device_resource_start(dev, 1), +- nv_device_resource_len(dev, 1)); +-} +- +-static inline void +-fbmem_fini(struct io_mapping *fb) +-{ +- io_mapping_free(fb); +-} +- +-static inline u32 +-fbmem_peek(struct io_mapping *fb, u32 off) +-{ +- u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK); +- u32 val = ioread32(p + (off & ~PAGE_MASK)); +- io_mapping_unmap_atomic(p); +- return val; +-} +- +-static inline void +-fbmem_poke(struct io_mapping *fb, u32 off, u32 val) +-{ +- u8 __iomem *p = io_mapping_map_atomic_wc(fb, off & PAGE_MASK); +- iowrite32(val, p + (off & ~PAGE_MASK)); +- wmb(); +- io_mapping_unmap_atomic(p); +-} +- +-static inline bool +-fbmem_readback(struct io_mapping *fb, u32 off, u32 val) +-{ +- fbmem_poke(fb, off, val); +- return val == fbmem_peek(fb, off); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c +deleted file mode 100644 +index c69bc7f5..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/gm107.c ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static u64 +-gm107_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r021c00 = nv_rd32(priv, 0x021c00); +- u32 r021c04 = nv_rd32(priv, 0x021c04); +- u64 disable = 0ULL; +- +- if (r021c00 & 0x00000001) +- disable |= (1ULL << NVDEV_ENGINE_COPY0); +- if (r021c00 & 0x00000004) +- disable |= (1ULL << NVDEV_ENGINE_COPY2); +- if (r021c04 & 0x00000001) +- disable |= (1ULL << NVDEV_ENGINE_DISP); +- +- return disable; +-} +- +-struct nouveau_oclass * +-gm107_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x07), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nvc0_devinit_pll_set, +- .disable = gm107_devinit_disable, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c +deleted file mode 100644 +index 052ad690..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.c ++++ /dev/null +@@ -1,467 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +- +-#include "fbmem.h" +-#include "nv04.h" +- +-static void +-nv04_devinit_meminit(struct nouveau_devinit *devinit) +-{ +- struct nv04_devinit_priv *priv = (void *)devinit; +- u32 patt = 0xdeadbeef; +- struct io_mapping *fb; +- int i; +- +- /* Map the framebuffer aperture */ +- fb = fbmem_init(nv_device(priv)); +- if (!fb) { +- nv_error(priv, "failed to map fb\n"); +- return; +- } +- +- /* Sequencer and refresh off */ +- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20); +- nv_mask(priv, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF); +- +- nv_mask(priv, NV04_PFB_BOOT_0, ~0, +- NV04_PFB_BOOT_0_RAM_AMOUNT_16MB | +- NV04_PFB_BOOT_0_RAM_WIDTH_128 | +- NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT); +- +- for (i = 0; i < 4; i++) +- fbmem_poke(fb, 4 * i, patt); +- +- fbmem_poke(fb, 0x400000, patt + 1); +- +- if (fbmem_peek(fb, 0) == patt + 1) { +- nv_mask(priv, NV04_PFB_BOOT_0, +- NV04_PFB_BOOT_0_RAM_TYPE, +- NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT); +- nv_mask(priv, NV04_PFB_DEBUG_0, +- NV04_PFB_DEBUG_0_REFRESH_OFF, 0); +- +- for (i = 0; i < 4; i++) +- fbmem_poke(fb, 4 * i, patt); +- +- if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff)) +- nv_mask(priv, NV04_PFB_BOOT_0, +- NV04_PFB_BOOT_0_RAM_WIDTH_128 | +- NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); +- } else +- if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) { +- nv_mask(priv, NV04_PFB_BOOT_0, +- NV04_PFB_BOOT_0_RAM_WIDTH_128 | +- NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); +- } else +- if (fbmem_peek(fb, 0) != patt) { +- if (fbmem_readback(fb, 0x800000, patt)) +- nv_mask(priv, NV04_PFB_BOOT_0, +- NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); +- else +- nv_mask(priv, NV04_PFB_BOOT_0, +- NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); +- +- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE, +- NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT); +- } else +- if (!fbmem_readback(fb, 0x800000, patt)) { +- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); +- +- } +- +- /* Refresh on, sequencer on */ +- nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); +- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20); +- fbmem_fini(fb); +-} +- +-static int +-powerctrl_1_shift(int chip_version, int reg) +-{ +- int shift = -4; +- +- if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20) +- return shift; +- +- switch (reg) { +- case 0x680520: +- shift += 4; +- case 0x680508: +- shift += 4; +- case 0x680504: +- shift += 4; +- case 0x680500: +- shift += 4; +- } +- +- /* +- * the shift for vpll regs is only used for nv3x chips with a single +- * stage pll +- */ +- if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 || +- chip_version == 0x36 || chip_version >= 0x40)) +- shift = -4; +- +- return shift; +-} +- +-void +-setPLL_single(struct nouveau_devinit *devinit, u32 reg, +- struct nouveau_pll_vals *pv) +-{ +- int chip_version = nouveau_bios(devinit)->version.chip; +- uint32_t oldpll = nv_rd32(devinit, reg); +- int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff; +- uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1; +- uint32_t saved_powerctrl_1 = 0; +- int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg); +- +- if (oldpll == pll) +- return; /* already set */ +- +- if (shift_powerctrl_1 >= 0) { +- saved_powerctrl_1 = nv_rd32(devinit, 0x001584); +- nv_wr32(devinit, 0x001584, +- (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | +- 1 << shift_powerctrl_1); +- } +- +- if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) +- /* upclock -- write new post divider first */ +- nv_wr32(devinit, reg, pv->log2P << 16 | (oldpll & 0xffff)); +- else +- /* downclock -- write new NM first */ +- nv_wr32(devinit, reg, (oldpll & 0xffff0000) | pv->NM1); +- +- if ((chip_version < 0x17 || chip_version == 0x1a) && +- chip_version != 0x11) +- /* wait a bit on older chips */ +- msleep(64); +- nv_rd32(devinit, reg); +- +- /* then write the other half as well */ +- nv_wr32(devinit, reg, pll); +- +- if (shift_powerctrl_1 >= 0) +- nv_wr32(devinit, 0x001584, saved_powerctrl_1); +-} +- +-static uint32_t +-new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) +-{ +- bool head_a = (reg1 == 0x680508); +- +- if (ss) /* single stage pll mode */ +- ramdac580 |= head_a ? 0x00000100 : 0x10000000; +- else +- ramdac580 &= head_a ? 0xfffffeff : 0xefffffff; +- +- return ramdac580; +-} +- +-void +-setPLL_double_highregs(struct nouveau_devinit *devinit, u32 reg1, +- struct nouveau_pll_vals *pv) +-{ +- int chip_version = nouveau_bios(devinit)->version.chip; +- bool nv3035 = chip_version == 0x30 || chip_version == 0x35; +- uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); +- uint32_t oldpll1 = nv_rd32(devinit, reg1); +- uint32_t oldpll2 = !nv3035 ? nv_rd32(devinit, reg2) : 0; +- uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1; +- uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; +- uint32_t oldramdac580 = 0, ramdac580 = 0; +- bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */ +- uint32_t saved_powerctrl_1 = 0, savedc040 = 0; +- int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); +- +- /* model specific additions to generic pll1 and pll2 set up above */ +- if (nv3035) { +- pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 | +- (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4; +- pll2 = 0; +- } +- if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ +- oldramdac580 = nv_rd32(devinit, 0x680580); +- ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); +- if (oldramdac580 != ramdac580) +- oldpll1 = ~0; /* force mismatch */ +- if (single_stage) +- /* magic value used by nvidia in single stage mode */ +- pll2 |= 0x011f; +- } +- if (chip_version > 0x70) +- /* magic bits set by the blob (but not the bios) on g71-73 */ +- pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28; +- +- if (oldpll1 == pll1 && oldpll2 == pll2) +- return; /* already set */ +- +- if (shift_powerctrl_1 >= 0) { +- saved_powerctrl_1 = nv_rd32(devinit, 0x001584); +- nv_wr32(devinit, 0x001584, +- (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) | +- 1 << shift_powerctrl_1); +- } +- +- if (chip_version >= 0x40) { +- int shift_c040 = 14; +- +- switch (reg1) { +- case 0x680504: +- shift_c040 += 2; +- case 0x680500: +- shift_c040 += 2; +- case 0x680520: +- shift_c040 += 2; +- case 0x680508: +- shift_c040 += 2; +- } +- +- savedc040 = nv_rd32(devinit, 0xc040); +- if (shift_c040 != 14) +- nv_wr32(devinit, 0xc040, savedc040 & ~(3 << shift_c040)); +- } +- +- if (oldramdac580 != ramdac580) +- nv_wr32(devinit, 0x680580, ramdac580); +- +- if (!nv3035) +- nv_wr32(devinit, reg2, pll2); +- nv_wr32(devinit, reg1, pll1); +- +- if (shift_powerctrl_1 >= 0) +- nv_wr32(devinit, 0x001584, saved_powerctrl_1); +- if (chip_version >= 0x40) +- nv_wr32(devinit, 0xc040, savedc040); +-} +- +-void +-setPLL_double_lowregs(struct nouveau_devinit *devinit, u32 NMNMreg, +- struct nouveau_pll_vals *pv) +-{ +- /* When setting PLLs, there is a merry game of disabling and enabling +- * various bits of hardware during the process. This function is a +- * synthesis of six nv4x traces, nearly each card doing a subtly +- * different thing. With luck all the necessary bits for each card are +- * combined herein. Without luck it deviates from each card's formula +- * so as to not work on any :) +- */ +- +- uint32_t Preg = NMNMreg - 4; +- bool mpll = Preg == 0x4020; +- uint32_t oldPval = nv_rd32(devinit, Preg); +- uint32_t NMNM = pv->NM2 << 16 | pv->NM1; +- uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | +- 0xc << 28 | pv->log2P << 16; +- uint32_t saved4600 = 0; +- /* some cards have different maskc040s */ +- uint32_t maskc040 = ~(3 << 14), savedc040; +- bool single_stage = !pv->NM2 || pv->N2 == pv->M2; +- +- if (nv_rd32(devinit, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval) +- return; +- +- if (Preg == 0x4000) +- maskc040 = ~0x333; +- if (Preg == 0x4058) +- maskc040 = ~(0xc << 24); +- +- if (mpll) { +- struct nvbios_pll info; +- uint8_t Pval2; +- +- if (nvbios_pll_parse(nouveau_bios(devinit), Preg, &info)) +- return; +- +- Pval2 = pv->log2P + info.bias_p; +- if (Pval2 > info.max_p) +- Pval2 = info.max_p; +- Pval |= 1 << 28 | Pval2 << 20; +- +- saved4600 = nv_rd32(devinit, 0x4600); +- nv_wr32(devinit, 0x4600, saved4600 | 8 << 28); +- } +- if (single_stage) +- Pval |= mpll ? 1 << 12 : 1 << 8; +- +- nv_wr32(devinit, Preg, oldPval | 1 << 28); +- nv_wr32(devinit, Preg, Pval & ~(4 << 28)); +- if (mpll) { +- Pval |= 8 << 20; +- nv_wr32(devinit, 0x4020, Pval & ~(0xc << 28)); +- nv_wr32(devinit, 0x4038, Pval & ~(0xc << 28)); +- } +- +- savedc040 = nv_rd32(devinit, 0xc040); +- nv_wr32(devinit, 0xc040, savedc040 & maskc040); +- +- nv_wr32(devinit, NMNMreg, NMNM); +- if (NMNMreg == 0x4024) +- nv_wr32(devinit, 0x403c, NMNM); +- +- nv_wr32(devinit, Preg, Pval); +- if (mpll) { +- Pval &= ~(8 << 20); +- nv_wr32(devinit, 0x4020, Pval); +- nv_wr32(devinit, 0x4038, Pval); +- nv_wr32(devinit, 0x4600, saved4600); +- } +- +- nv_wr32(devinit, 0xc040, savedc040); +- +- if (mpll) { +- nv_wr32(devinit, 0x4020, Pval & ~(1 << 28)); +- nv_wr32(devinit, 0x4038, Pval & ~(1 << 28)); +- } +-} +- +-int +-nv04_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +-{ +- struct nouveau_bios *bios = nouveau_bios(devinit); +- struct nouveau_pll_vals pv; +- struct nvbios_pll info; +- int cv = bios->version.chip; +- int N1, M1, N2, M2, P; +- int ret; +- +- ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info); +- if (ret) +- return ret; +- +- ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, +- &N1, &M1, &N2, &M2, &P); +- if (!ret) +- return -EINVAL; +- +- pv.refclk = info.refclk; +- pv.N1 = N1; +- pv.M1 = M1; +- pv.N2 = N2; +- pv.M2 = M2; +- pv.log2P = P; +- +- if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 || +- cv >= 0x40) { +- if (type > 0x405c) +- setPLL_double_highregs(devinit, type, &pv); +- else +- setPLL_double_lowregs(devinit, type, &pv); +- } else +- setPLL_single(devinit, type, &pv); +- +- return 0; +-} +- +-int +-nv04_devinit_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv04_devinit_priv *priv = (void *)object; +- int ret; +- +- /* make i2c busses accessible */ +- nv_mask(priv, 0x000200, 0x00000001, 0x00000001); +- +- ret = nouveau_devinit_fini(&priv->base, suspend); +- if (ret) +- return ret; +- +- /* unslave crtcs */ +- if (priv->owner < 0) +- priv->owner = nv_rdvgaowner(priv); +- nv_wrvgaowner(priv, 0); +- +- return 0; +-} +- +-int +-nv04_devinit_init(struct nouveau_object *object) +-{ +- struct nv04_devinit_priv *priv = (void *)object; +- +- if (!priv->base.post) { +- u32 htotal = nv_rdvgac(priv, 0, 0x06); +- htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x01) << 8; +- htotal |= (nv_rdvgac(priv, 0, 0x07) & 0x20) << 4; +- htotal |= (nv_rdvgac(priv, 0, 0x25) & 0x01) << 10; +- htotal |= (nv_rdvgac(priv, 0, 0x41) & 0x01) << 11; +- if (!htotal) { +- nv_info(priv, "adaptor not initialised\n"); +- priv->base.post = true; +- } +- } +- +- return nouveau_devinit_init(&priv->base); +-} +- +-void +-nv04_devinit_dtor(struct nouveau_object *object) +-{ +- struct nv04_devinit_priv *priv = (void *)object; +- +- /* restore vga owner saved at first init */ +- nv_wrvgaowner(priv, priv->owner); +- +- nouveau_devinit_destroy(&priv->base); +-} +- +-int +-nv04_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_devinit_priv *priv; +- int ret; +- +- ret = nouveau_devinit_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->owner = -1; +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_devinit_ctor, +- .dtor = nv04_devinit_dtor, +- .init = nv04_devinit_init, +- .fini = nv04_devinit_fini, +- }, +- .meminit = nv04_devinit_meminit, +- .pll_set = nv04_devinit_pll_set, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h +deleted file mode 100644 +index 23470a57..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv04.h ++++ /dev/null +@@ -1,23 +0,0 @@ +-#ifndef __NVKM_DEVINIT_NV04_H__ +-#define __NVKM_DEVINIT_NV04_H__ +- +-#include "priv.h" +- +-struct nv04_devinit_priv { +- struct nouveau_devinit base; +- u8 owner; +-}; +- +-int nv04_devinit_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv04_devinit_dtor(struct nouveau_object *); +-int nv04_devinit_init(struct nouveau_object *); +-int nv04_devinit_fini(struct nouveau_object *, bool); +-int nv04_devinit_pll_set(struct nouveau_devinit *, u32, u32); +- +-void setPLL_single(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); +-void setPLL_double_highregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); +-void setPLL_double_lowregs(struct nouveau_devinit *, u32, struct nouveau_pll_vals *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c +deleted file mode 100644 +index 4a19c10e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv05.c ++++ /dev/null +@@ -1,139 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include +-#include +- +-#include "fbmem.h" +-#include "nv04.h" +- +-static void +-nv05_devinit_meminit(struct nouveau_devinit *devinit) +-{ +- static const u8 default_config_tab[][2] = { +- { 0x24, 0x00 }, +- { 0x28, 0x00 }, +- { 0x24, 0x01 }, +- { 0x1f, 0x00 }, +- { 0x0f, 0x00 }, +- { 0x17, 0x00 }, +- { 0x06, 0x00 }, +- { 0x00, 0x00 } +- }; +- struct nv04_devinit_priv *priv = (void *)devinit; +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct io_mapping *fb; +- u32 patt = 0xdeadbeef; +- u16 data; +- u8 strap, ramcfg[2]; +- int i, v; +- +- /* Map the framebuffer aperture */ +- fb = fbmem_init(nv_device(priv)); +- if (!fb) { +- nv_error(priv, "failed to map fb\n"); +- return; +- } +- +- strap = (nv_rd32(priv, 0x101000) & 0x0000003c) >> 2; +- if ((data = bmp_mem_init_table(bios))) { +- ramcfg[0] = nv_ro08(bios, data + 2 * strap + 0); +- ramcfg[1] = nv_ro08(bios, data + 2 * strap + 1); +- } else { +- ramcfg[0] = default_config_tab[strap][0]; +- ramcfg[1] = default_config_tab[strap][1]; +- } +- +- /* Sequencer off */ +- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) | 0x20); +- +- if (nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE) +- goto out; +- +- nv_mask(priv, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0); +- +- /* If present load the hardcoded scrambling table */ +- if (data) { +- for (i = 0, data += 0x10; i < 8; i++, data += 4) { +- u32 scramble = nv_ro32(bios, data); +- nv_wr32(priv, NV04_PFB_SCRAMBLE(i), scramble); +- } +- } +- +- /* Set memory type/width/length defaults depending on the straps */ +- nv_mask(priv, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]); +- +- if (ramcfg[1] & 0x80) +- nv_mask(priv, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE); +- +- nv_mask(priv, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20); +- nv_mask(priv, NV04_PFB_CFG1, 0, 1); +- +- /* Probe memory bus width */ +- for (i = 0; i < 4; i++) +- fbmem_poke(fb, 4 * i, patt); +- +- if (fbmem_peek(fb, 0xc) != patt) +- nv_mask(priv, NV04_PFB_BOOT_0, +- NV04_PFB_BOOT_0_RAM_WIDTH_128, 0); +- +- /* Probe memory length */ +- v = nv_rd32(priv, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT; +- +- if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB && +- (!fbmem_readback(fb, 0x1000000, ++patt) || +- !fbmem_readback(fb, 0, ++patt))) +- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_16MB); +- +- if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB && +- !fbmem_readback(fb, 0x800000, ++patt)) +- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_8MB); +- +- if (!fbmem_readback(fb, 0x400000, ++patt)) +- nv_mask(priv, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT, +- NV04_PFB_BOOT_0_RAM_AMOUNT_4MB); +- +-out: +- /* Sequencer on */ +- nv_wrvgas(priv, 0, 1, nv_rdvgas(priv, 0, 1) & ~0x20); +- fbmem_fini(fb); +-} +- +-struct nouveau_oclass * +-nv05_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x05), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_devinit_ctor, +- .dtor = nv04_devinit_dtor, +- .init = nv04_devinit_init, +- .fini = nv04_devinit_fini, +- }, +- .meminit = nv05_devinit_meminit, +- .pll_set = nv04_devinit_pll_set, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c +deleted file mode 100644 +index 3b8d657d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv10.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +- +-#include "fbmem.h" +-#include "nv04.h" +- +-static void +-nv10_devinit_meminit(struct nouveau_devinit *devinit) +-{ +- struct nv04_devinit_priv *priv = (void *)devinit; +- static const int mem_width[] = { 0x10, 0x00, 0x20 }; +- int mem_width_count; +- uint32_t patt = 0xdeadbeef; +- struct io_mapping *fb; +- int i, j, k; +- +- if (nv_device(priv)->card_type >= NV_11 && +- nv_device(priv)->chipset >= 0x17) +- mem_width_count = 3; +- else +- mem_width_count = 2; +- +- /* Map the framebuffer aperture */ +- fb = fbmem_init(nv_device(priv)); +- if (!fb) { +- nv_error(priv, "failed to map fb\n"); +- return; +- } +- +- nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); +- +- /* Probe memory bus width */ +- for (i = 0; i < mem_width_count; i++) { +- nv_mask(priv, NV04_PFB_CFG0, 0x30, mem_width[i]); +- +- for (j = 0; j < 4; j++) { +- for (k = 0; k < 4; k++) +- fbmem_poke(fb, 0x1c, 0); +- +- fbmem_poke(fb, 0x1c, patt); +- fbmem_poke(fb, 0x3c, 0); +- +- if (fbmem_peek(fb, 0x1c) == patt) +- goto mem_width_found; +- } +- } +- +-mem_width_found: +- patt <<= 1; +- +- /* Probe amount of installed memory */ +- for (i = 0; i < 4; i++) { +- int off = nv_rd32(priv, 0x10020c) - 0x100000; +- +- fbmem_poke(fb, off, patt); +- fbmem_poke(fb, 0, 0); +- +- fbmem_peek(fb, 0); +- fbmem_peek(fb, 0); +- fbmem_peek(fb, 0); +- fbmem_peek(fb, 0); +- +- if (fbmem_peek(fb, off) == patt) +- goto amount_found; +- } +- +- /* IC missing - disable the upper half memory space. */ +- nv_mask(priv, NV04_PFB_CFG0, 0x1000, 0); +- +-amount_found: +- fbmem_fini(fb); +-} +- +-struct nouveau_oclass * +-nv10_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x10), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_devinit_ctor, +- .dtor = nv04_devinit_dtor, +- .init = nv04_devinit_init, +- .fini = nv04_devinit_fini, +- }, +- .meminit = nv10_devinit_meminit, +- .pll_set = nv04_devinit_pll_set, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c +deleted file mode 100644 +index 526d0c6f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv1a.c ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv1a_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x1a), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_devinit_ctor, +- .dtor = nv04_devinit_dtor, +- .init = nv04_devinit_init, +- .fini = nv04_devinit_fini, +- }, +- .pll_set = nv04_devinit_pll_set, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c +deleted file mode 100644 +index 04bc9732..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv20.c ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +-#include "fbmem.h" +- +-static void +-nv20_devinit_meminit(struct nouveau_devinit *devinit) +-{ +- struct nv04_devinit_priv *priv = (void *)devinit; +- struct nouveau_device *device = nv_device(priv); +- uint32_t mask = (device->chipset >= 0x25 ? 0x300 : 0x900); +- uint32_t amount, off; +- struct io_mapping *fb; +- +- /* Map the framebuffer aperture */ +- fb = fbmem_init(nv_device(priv)); +- if (!fb) { +- nv_error(priv, "failed to map fb\n"); +- return; +- } +- +- nv_wr32(priv, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); +- +- /* Allow full addressing */ +- nv_mask(priv, NV04_PFB_CFG0, 0, mask); +- +- amount = nv_rd32(priv, 0x10020c); +- for (off = amount; off > 0x2000000; off -= 0x2000000) +- fbmem_poke(fb, off - 4, off); +- +- amount = nv_rd32(priv, 0x10020c); +- if (amount != fbmem_peek(fb, amount - 4)) +- /* IC missing - disable the upper half memory space. */ +- nv_mask(priv, NV04_PFB_CFG0, mask, 0); +- +- fbmem_fini(fb); +-} +- +-struct nouveau_oclass * +-nv20_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x20), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_devinit_ctor, +- .dtor = nv04_devinit_dtor, +- .init = nv04_devinit_init, +- .fini = nv04_devinit_fini, +- }, +- .meminit = nv20_devinit_meminit, +- .pll_set = nv04_devinit_pll_set, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c +deleted file mode 100644 +index b46c62a1..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.c ++++ /dev/null +@@ -1,163 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "nv50.h" +- +-int +-nv50_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll info; +- int N1, M1, N2, M2, P; +- int ret; +- +- ret = nvbios_pll_parse(bios, type, &info); +- if (ret) { +- nv_error(devinit, "failed to retrieve pll data, %d\n", ret); +- return ret; +- } +- +- ret = nv04_pll_calc(nv_subdev(devinit), &info, freq, &N1, &M1, &N2, &M2, &P); +- if (!ret) { +- nv_error(devinit, "failed pll calculation\n"); +- return ret; +- } +- +- switch (info.type) { +- case PLL_VPLL0: +- case PLL_VPLL1: +- nv_wr32(priv, info.reg + 0, 0x10000611); +- nv_mask(priv, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); +- nv_mask(priv, info.reg + 8, 0x7fff00ff, (P << 28) | +- (M2 << 16) | N2); +- break; +- case PLL_MEMORY: +- nv_mask(priv, info.reg + 0, 0x01ff0000, (P << 22) | +- (info.bias_p << 19) | +- (P << 16)); +- nv_wr32(priv, info.reg + 4, (N1 << 8) | M1); +- break; +- default: +- nv_mask(priv, info.reg + 0, 0x00070000, (P << 16)); +- nv_wr32(priv, info.reg + 4, (N1 << 8) | M1); +- break; +- } +- +- return 0; +-} +- +-static u64 +-nv50_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r001540 = nv_rd32(priv, 0x001540); +- u64 disable = 0ULL; +- +- if (!(r001540 & 0x40000000)) +- disable |= (1ULL << NVDEV_ENGINE_MPEG); +- +- return disable; +-} +- +-int +-nv50_devinit_init(struct nouveau_object *object) +-{ +- struct nouveau_bios *bios = nouveau_bios(object); +- struct nv50_devinit_priv *priv = (void *)object; +- struct nvbios_outp info; +- struct dcb_output outp; +- u8 ver = 0xff, hdr, cnt, len; +- int ret, i = 0; +- +- if (!priv->base.post) { +- if (!nv_rdvgac(priv, 0, 0x00) && +- !nv_rdvgac(priv, 0, 0x1a)) { +- nv_info(priv, "adaptor not initialised\n"); +- priv->base.post = true; +- } +- } +- +- ret = nouveau_devinit_init(&priv->base); +- if (ret) +- return ret; +- +- /* if we ran the init tables, we have to execute the first script +- * pointer of each dcb entry's display encoder table in order +- * to properly initialise each encoder. +- */ +- while (priv->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { +- if (nvbios_outp_match(bios, outp.hasht, outp.hashm, +- &ver, &hdr, &cnt, &len, &info)) { +- struct nvbios_init init = { +- .subdev = nv_subdev(priv), +- .bios = bios, +- .offset = info.script[0], +- .outp = &outp, +- .crtc = -1, +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- } +- i++; +- } +- +- return 0; +-} +- +-int +-nv50_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_devinit_priv *priv; +- int ret; +- +- ret = nouveau_devinit_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nv50_devinit_pll_set, +- .disable = nv50_devinit_disable, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h +deleted file mode 100644 +index 51d50763..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv50.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-#ifndef __NVKM_DEVINIT_NV50_H__ +-#define __NVKM_DEVINIT_NV50_H__ +- +-#include "priv.h" +- +-struct nv50_devinit_priv { +- struct nouveau_devinit base; +- u32 r001540; +-}; +- +-int nv50_devinit_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-int nv50_devinit_init(struct nouveau_object *); +-int nv50_devinit_pll_set(struct nouveau_devinit *, u32, u32); +- +-int nva3_devinit_pll_set(struct nouveau_devinit *, u32, u32); +- +-int nvc0_devinit_pll_set(struct nouveau_devinit *, u32, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c +deleted file mode 100644 +index 78742250..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv84.c ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static u64 +-nv84_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r001540 = nv_rd32(priv, 0x001540); +- u32 r00154c = nv_rd32(priv, 0x00154c); +- u64 disable = 0ULL; +- +- if (!(r001540 & 0x40000000)) { +- disable |= (1ULL << NVDEV_ENGINE_MPEG); +- disable |= (1ULL << NVDEV_ENGINE_VP); +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- disable |= (1ULL << NVDEV_ENGINE_CRYPT); +- } +- +- if (!(r00154c & 0x00000004)) +- disable |= (1ULL << NVDEV_ENGINE_DISP); +- if (!(r00154c & 0x00000020)) +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- if (!(r00154c & 0x00000040)) +- disable |= (1ULL << NVDEV_ENGINE_CRYPT); +- +- return disable; +-} +- +-struct nouveau_oclass * +-nv84_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x84), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nv50_devinit_pll_set, +- .disable = nv84_devinit_disable, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c +deleted file mode 100644 +index 2b0e963f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nv98.c ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static u64 +-nv98_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r001540 = nv_rd32(priv, 0x001540); +- u32 r00154c = nv_rd32(priv, 0x00154c); +- u64 disable = 0ULL; +- +- if (!(r001540 & 0x40000000)) { +- disable |= (1ULL << NVDEV_ENGINE_VP); +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- disable |= (1ULL << NVDEV_ENGINE_PPP); +- } +- +- if (!(r00154c & 0x00000004)) +- disable |= (1ULL << NVDEV_ENGINE_DISP); +- if (!(r00154c & 0x00000020)) +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- if (!(r00154c & 0x00000040)) +- disable |= (1ULL << NVDEV_ENGINE_CRYPT); +- +- return disable; +-} +- +-struct nouveau_oclass * +-nv98_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0x98), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nv50_devinit_pll_set, +- .disable = nv98_devinit_disable, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c +deleted file mode 100644 +index 006cf348..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nva3.c ++++ /dev/null +@@ -1,145 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-int +-nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll info; +- int N, fN, M, P; +- int ret; +- +- ret = nvbios_pll_parse(bios, type, &info); +- if (ret) +- return ret; +- +- ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); +- if (ret < 0) +- return ret; +- +- switch (info.type) { +- case PLL_VPLL0: +- case PLL_VPLL1: +- nv_wr32(priv, info.reg + 0, 0x50000610); +- nv_mask(priv, info.reg + 4, 0x003fffff, +- (P << 16) | (M << 8) | N); +- nv_wr32(priv, info.reg + 8, fN); +- break; +- default: +- nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); +- ret = -EINVAL; +- break; +- } +- +- return ret; +-} +- +-static u64 +-nva3_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r001540 = nv_rd32(priv, 0x001540); +- u32 r00154c = nv_rd32(priv, 0x00154c); +- u64 disable = 0ULL; +- +- if (!(r001540 & 0x40000000)) { +- disable |= (1ULL << NVDEV_ENGINE_VP); +- disable |= (1ULL << NVDEV_ENGINE_PPP); +- } +- +- if (!(r00154c & 0x00000004)) +- disable |= (1ULL << NVDEV_ENGINE_DISP); +- if (!(r00154c & 0x00000020)) +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- if (!(r00154c & 0x00000200)) +- disable |= (1ULL << NVDEV_ENGINE_COPY0); +- +- return disable; +-} +- +-static u32 +-nva3_devinit_mmio_part[] = { +- 0x100720, 0x1008bc, 4, +- 0x100a20, 0x100adc, 4, +- 0x100d80, 0x100ddc, 4, +- 0x110000, 0x110f9c, 4, +- 0x111000, 0x11103c, 8, +- 0x111080, 0x1110fc, 4, +- 0x111120, 0x1111fc, 4, +- 0x111300, 0x1114bc, 4, +- 0, +-}; +- +-static u32 +-nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 *mmio = nva3_devinit_mmio_part; +- +- /* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP +- * instructions which touch registers that may not even exist on +- * some configurations (Quadro 400), which causes the register +- * interface to screw up for some amount of time after attempting to +- * write to one of these, and results in all sorts of things going +- * horribly wrong. +- * +- * the binary driver avoids touching these registers at all, however, +- * the video bios doesn't care and does what the scripts say. it's +- * presumed that the io-port access to priv registers isn't effected +- * by the screw-up bug mentioned above. +- * +- * really, a new opcode should've been invented to handle these +- * requirements, but whatever, it's too late for that now. +- */ +- while (mmio[0]) { +- if (addr >= mmio[0] && addr <= mmio[1]) { +- u32 part = (addr / mmio[2]) & 7; +- if (!priv->r001540) +- priv->r001540 = nv_rd32(priv, 0x001540); +- if (part >= hweight8((priv->r001540 >> 16) & 0xff)) +- return ~0; +- return addr; +- } +- mmio += 3; +- } +- +- return addr; +-} +- +-struct nouveau_oclass * +-nva3_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0xa3), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nva3_devinit_pll_set, +- .disable = nva3_devinit_disable, +- .mmio = nva3_devinit_mmio, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c +deleted file mode 100644 +index 4fc68d27..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvaf.c ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static u64 +-nvaf_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r001540 = nv_rd32(priv, 0x001540); +- u32 r00154c = nv_rd32(priv, 0x00154c); +- u64 disable = 0; +- +- if (!(r001540 & 0x40000000)) { +- disable |= (1ULL << NVDEV_ENGINE_VP); +- disable |= (1ULL << NVDEV_ENGINE_PPP); +- } +- +- if (!(r00154c & 0x00000004)) +- disable |= (1ULL << NVDEV_ENGINE_DISP); +- if (!(r00154c & 0x00000020)) +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- if (!(r00154c & 0x00000040)) +- disable |= (1ULL << NVDEV_ENGINE_VIC); +- if (!(r00154c & 0x00000200)) +- disable |= (1ULL << NVDEV_ENGINE_COPY0); +- +- return disable; +-} +- +-struct nouveau_oclass * +-nvaf_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0xaf), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nva3_devinit_pll_set, +- .disable = nvaf_devinit_disable, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c +deleted file mode 100644 +index 30c76574..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/nvc0.c ++++ /dev/null +@@ -1,118 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-int +-nvc0_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- struct nouveau_bios *bios = nouveau_bios(priv); +- struct nvbios_pll info; +- int N, fN, M, P; +- int ret; +- +- ret = nvbios_pll_parse(bios, type, &info); +- if (ret) +- return ret; +- +- ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); +- if (ret < 0) +- return ret; +- +- switch (info.type) { +- case PLL_VPLL0: +- case PLL_VPLL1: +- case PLL_VPLL2: +- case PLL_VPLL3: +- nv_mask(priv, info.reg + 0x0c, 0x00000000, 0x00000100); +- nv_wr32(priv, info.reg + 0x04, (P << 16) | (N << 8) | M); +- nv_wr32(priv, info.reg + 0x10, fN << 16); +- break; +- default: +- nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); +- ret = -EINVAL; +- break; +- } +- +- return ret; +-} +- +-static u64 +-nvc0_devinit_disable(struct nouveau_devinit *devinit) +-{ +- struct nv50_devinit_priv *priv = (void *)devinit; +- u32 r022500 = nv_rd32(priv, 0x022500); +- u64 disable = 0ULL; +- +- if (r022500 & 0x00000001) +- disable |= (1ULL << NVDEV_ENGINE_DISP); +- +- if (r022500 & 0x00000002) { +- disable |= (1ULL << NVDEV_ENGINE_VP); +- disable |= (1ULL << NVDEV_ENGINE_PPP); +- } +- +- if (r022500 & 0x00000004) +- disable |= (1ULL << NVDEV_ENGINE_BSP); +- if (r022500 & 0x00000008) +- disable |= (1ULL << NVDEV_ENGINE_VENC); +- if (r022500 & 0x00000100) +- disable |= (1ULL << NVDEV_ENGINE_COPY0); +- if (r022500 & 0x00000200) +- disable |= (1ULL << NVDEV_ENGINE_COPY1); +- +- return disable; +-} +- +-static int +-nvc0_devinit_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_devinit_priv *priv; +- int ret; +- +- ret = nouveau_devinit_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- if (nv_rd32(priv, 0x022500) & 0x00000001) +- priv->base.post = true; +- return 0; +-} +- +-struct nouveau_oclass * +-nvc0_devinit_oclass = &(struct nouveau_devinit_impl) { +- .base.handle = NV_SUBDEV(DEVINIT, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_devinit_ctor, +- .dtor = _nouveau_devinit_dtor, +- .init = nv50_devinit_init, +- .fini = _nouveau_devinit_fini, +- }, +- .pll_set = nvc0_devinit_pll_set, +- .disable = nvc0_devinit_disable, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h +deleted file mode 100644 +index f0e8683a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/devinit/priv.h ++++ /dev/null +@@ -1,38 +0,0 @@ +-#ifndef __NVKM_DEVINIT_PRIV_H__ +-#define __NVKM_DEVINIT_PRIV_H__ +- +-#include +-#include +-#include +-#include +- +-struct nouveau_devinit_impl { +- struct nouveau_oclass base; +- void (*meminit)(struct nouveau_devinit *); +- int (*pll_set)(struct nouveau_devinit *, u32 type, u32 freq); +- u64 (*disable)(struct nouveau_devinit *); +- u32 (*mmio)(struct nouveau_devinit *, u32); +-}; +- +-#define nouveau_devinit_create(p,e,o,d) \ +- nouveau_devinit_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_devinit_destroy(p) ({ \ +- struct nouveau_devinit *d = (p); \ +- _nouveau_devinit_dtor(nv_object(d)); \ +-}) +-#define nouveau_devinit_init(p) ({ \ +- struct nouveau_devinit *d = (p); \ +- _nouveau_devinit_init(nv_object(d)); \ +-}) +-#define nouveau_devinit_fini(p,s) ({ \ +- struct nouveau_devinit *d = (p); \ +- _nouveau_devinit_fini(nv_object(d), (s)); \ +-}) +- +-int nouveau_devinit_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_devinit_dtor(struct nouveau_object *); +-int _nouveau_devinit_init(struct nouveau_object *); +-int _nouveau_devinit_fini(struct nouveau_object *, bool suspend); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c b/drivers/gpu/drm/nouveau/core/subdev/fb/base.c +deleted file mode 100644 +index f009d8a3..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/base.c ++++ /dev/null +@@ -1,166 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "priv.h" +- +-int +-nouveau_fb_bios_memtype(struct nouveau_bios *bios) +-{ +- struct bit_entry M; +- u8 ramcfg; +- +- ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2; +- if (!bit_entry(bios, 'M', &M) && M.version == 2 && M.length >= 5) { +- u16 table = nv_ro16(bios, M.offset + 3); +- u8 version = nv_ro08(bios, table + 0); +- u8 header = nv_ro08(bios, table + 1); +- u8 record = nv_ro08(bios, table + 2); +- u8 entries = nv_ro08(bios, table + 3); +- if (table && version == 0x10 && ramcfg < entries) { +- u16 entry = table + header + (ramcfg * record); +- switch (nv_ro08(bios, entry) & 0x0f) { +- case 0: return NV_MEM_TYPE_DDR2; +- case 1: return NV_MEM_TYPE_DDR3; +- case 2: return NV_MEM_TYPE_GDDR3; +- case 3: return NV_MEM_TYPE_GDDR5; +- default: +- break; +- } +- +- } +- } +- +- return NV_MEM_TYPE_UNKNOWN; +-} +- +-int +-_nouveau_fb_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_fb *pfb = (void *)object; +- int ret; +- +- ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend); +- if (ret && suspend) +- return ret; +- +- return nouveau_subdev_fini(&pfb->base, suspend); +-} +- +-int +-_nouveau_fb_init(struct nouveau_object *object) +-{ +- struct nouveau_fb *pfb = (void *)object; +- int ret, i; +- +- ret = nouveau_subdev_init(&pfb->base); +- if (ret) +- return ret; +- +- ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram)); +- if (ret) +- return ret; +- +- for (i = 0; i < pfb->tile.regions; i++) +- pfb->tile.prog(pfb, i, &pfb->tile.region[i]); +- +- return 0; +-} +- +-void +-_nouveau_fb_dtor(struct nouveau_object *object) +-{ +- struct nouveau_fb *pfb = (void *)object; +- int i; +- +- for (i = 0; i < pfb->tile.regions; i++) +- pfb->tile.fini(pfb, i, &pfb->tile.region[i]); +- nouveau_mm_fini(&pfb->tags); +- nouveau_mm_fini(&pfb->vram); +- +- nouveau_object_ref(NULL, (struct nouveau_object **)&pfb->ram); +- nouveau_subdev_destroy(&pfb->base); +-} +- +-int +-nouveau_fb_create_(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- struct nouveau_fb_impl *impl = (void *)oclass; +- static const char *name[] = { +- [NV_MEM_TYPE_UNKNOWN] = "unknown", +- [NV_MEM_TYPE_STOLEN ] = "stolen system memory", +- [NV_MEM_TYPE_SGRAM ] = "SGRAM", +- [NV_MEM_TYPE_SDRAM ] = "SDRAM", +- [NV_MEM_TYPE_DDR1 ] = "DDR1", +- [NV_MEM_TYPE_DDR2 ] = "DDR2", +- [NV_MEM_TYPE_DDR3 ] = "DDR3", +- [NV_MEM_TYPE_GDDR2 ] = "GDDR2", +- [NV_MEM_TYPE_GDDR3 ] = "GDDR3", +- [NV_MEM_TYPE_GDDR4 ] = "GDDR4", +- [NV_MEM_TYPE_GDDR5 ] = "GDDR5", +- }; +- struct nouveau_object *ram; +- struct nouveau_fb *pfb; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PFB", "fb", +- length, pobject); +- pfb = *pobject; +- if (ret) +- return ret; +- +- pfb->memtype_valid = impl->memtype; +- +- ret = nouveau_object_ctor(nv_object(pfb), nv_object(pfb), +- impl->ram, NULL, 0, &ram); +- if (ret) { +- nv_fatal(pfb, "error detecting memory configuration!!\n"); +- return ret; +- } +- +- atomic_dec(&ram->parent->refcount); +- atomic_dec(&ram->engine->refcount); +- pfb->ram = (void *)ram; +- +- if (!nouveau_mm_initialised(&pfb->vram)) { +- ret = nouveau_mm_init(&pfb->vram, 0, pfb->ram->size >> 12, 1); +- if (ret) +- return ret; +- } +- +- if (!nouveau_mm_initialised(&pfb->tags)) { +- ret = nouveau_mm_init(&pfb->tags, 0, pfb->ram->tags ? +- ++pfb->ram->tags : 0, 1); +- if (ret) +- return ret; +- } +- +- nv_info(pfb, "RAM type: %s\n", name[pfb->ram->type]); +- nv_info(pfb, "RAM size: %d MiB\n", (int)(pfb->ram->size >> 20)); +- nv_info(pfb, " ZCOMP: %d tags\n", pfb->ram->tags); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c +deleted file mode 100644 +index 7fbbe05d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gddr5.c ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include "priv.h" +- +-/* binary driver only executes this path if the condition (a) is true +- * for any configuration (combination of rammap+ramcfg+timing) that +- * can be reached on a given card. for now, we will execute the branch +- * unconditionally in the hope that a "false everywhere" in the bios +- * tables doesn't actually mean "don't touch this". +- */ +-#define NOTE00(a) 1 +- +-int +-nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts) +-{ +- int pd, lf, xd, vh, vr, vo, l3; +- int WL, CL, WR, at[2], dt, ds; +- int rq = ram->freq < 1000000; /* XXX */ +- +- switch (ram->next->bios.ramcfg_ver) { +- case 0x11: +- pd = ram->next->bios.ramcfg_11_01_80; +- lf = ram->next->bios.ramcfg_11_01_40; +- xd = !ram->next->bios.ramcfg_11_01_20; +- vh = ram->next->bios.ramcfg_11_02_10; +- vr = ram->next->bios.ramcfg_11_02_04; +- vo = ram->next->bios.ramcfg_11_06; +- l3 = !ram->next->bios.ramcfg_11_07_02; +- break; +- default: +- return -ENOSYS; +- } +- +- switch (ram->next->bios.timing_ver) { +- case 0x20: +- WL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; +- CL = (ram->next->bios.timing[1] & 0x0000001f); +- WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; +- at[0] = ram->next->bios.timing_20_2e_c0; +- at[1] = ram->next->bios.timing_20_2e_30; +- dt = ram->next->bios.timing_20_2e_03; +- ds = ram->next->bios.timing_20_2f_03; +- break; +- default: +- return -ENOSYS; +- } +- +- if (WL < 1 || WL > 7 || CL < 5 || CL > 36 || WR < 4 || WR > 35) +- return -EINVAL; +- CL -= 5; +- WR -= 4; +- +- ram->mr[0] &= ~0xf7f; +- ram->mr[0] |= (WR & 0x0f) << 8; +- ram->mr[0] |= (CL & 0x0f) << 3; +- ram->mr[0] |= (WL & 0x07) << 0; +- +- ram->mr[1] &= ~0x0bf; +- ram->mr[1] |= (xd & 0x01) << 7; +- ram->mr[1] |= (at[0] & 0x03) << 4; +- ram->mr[1] |= (dt & 0x03) << 2; +- ram->mr[1] |= (ds & 0x03) << 0; +- +- /* this seems wrong, alternate field used for the broadcast +- * on nuts vs non-nuts configs.. meh, it matches for now. +- */ +- ram->mr1_nuts = ram->mr[1]; +- if (nuts) { +- ram->mr[1] &= ~0x030; +- ram->mr[1] |= (at[1] & 0x03) << 4; +- } +- +- ram->mr[3] &= ~0x020; +- ram->mr[3] |= (rq & 0x01) << 5; +- +- ram->mr[5] &= ~0x004; +- ram->mr[5] |= (l3 << 2); +- +- if (!vo) +- vo = (ram->mr[6] & 0xff0) >> 4; +- if (ram->mr[6] & 0x001) +- pd = 1; /* binary driver does this.. bug? */ +- ram->mr[6] &= ~0xff1; +- ram->mr[6] |= (vo & 0xff) << 4; +- ram->mr[6] |= (pd & 0x01) << 0; +- +- if (NOTE00(vr)) { +- ram->mr[7] &= ~0x300; +- ram->mr[7] |= (vr & 0x03) << 8; +- } +- ram->mr[7] &= ~0x088; +- ram->mr[7] |= (vh & 0x01) << 7; +- ram->mr[7] |= (lf & 0x01) << 3; +- +- ram->mr[8] &= ~0x003; +- ram->mr[8] |= (WR & 0x10) >> 3; +- ram->mr[8] |= (CL & 0x10) >> 4; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c +deleted file mode 100644 +index fde42e4d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gk20a.c ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include "nvc0.h" +- +-struct gk20a_fb_priv { +- struct nouveau_fb base; +-}; +- +-static int +-gk20a_fb_init(struct nouveau_object *object) +-{ +- struct gk20a_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ +- return 0; +-} +- +-static int +-gk20a_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gk20a_fb_priv *priv; +- int ret; +- +- ret = nouveau_fb_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-gk20a_fb_oclass = &(struct nouveau_fb_impl) { +- .base.handle = NV_SUBDEV(FB, 0xea), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gk20a_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = gk20a_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .memtype = nvc0_fb_memtype_valid, +- .ram = &gk20a_ram_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c +deleted file mode 100644 +index c4840aed..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/gm107.c ++++ /dev/null +@@ -1,38 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-struct nouveau_oclass * +-gm107_fb_oclass = &(struct nouveau_fb_impl) { +- .base.handle = NV_SUBDEV(FB, 0x07), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_fb_ctor, +- .dtor = nvc0_fb_dtor, +- .init = nvc0_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .memtype = nvc0_fb_memtype_valid, +- .ram = &gm107_ram_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c +deleted file mode 100644 +index 8309fe33..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.c ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-#define NV04_PFB_CFG0 0x00100200 +- +-bool +-nv04_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) +-{ +- if (!(tile_flags & 0xff00)) +- return true; +- +- return false; +-} +- +-static int +-nv04_fb_init(struct nouveau_object *object) +-{ +- struct nv04_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows +- * nvidia reading PFB_CFG_0, then writing back its original value. +- * (which was 0x701114 in this case) +- */ +- nv_wr32(priv, NV04_PFB_CFG0, 0x1114); +- return 0; +-} +- +-int +-nv04_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_fb_impl *impl = (void *)oclass; +- struct nv04_fb_priv *priv; +- int ret; +- +- ret = nouveau_fb_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.tile.regions = impl->tile.regions; +- priv->base.tile.init = impl->tile.init; +- priv->base.tile.comp = impl->tile.comp; +- priv->base.tile.fini = impl->tile.fini; +- priv->base.tile.prog = impl->tile.prog; +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x04), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv04_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv04_ram_oclass, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h +deleted file mode 100644 +index 06ce71f8..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv04.h ++++ /dev/null +@@ -1,55 +0,0 @@ +-#ifndef __NVKM_FB_NV04_H__ +-#define __NVKM_FB_NV04_H__ +- +-#include "priv.h" +- +-struct nv04_fb_priv { +- struct nouveau_fb base; +-}; +- +-int nv04_fb_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-struct nv04_fb_impl { +- struct nouveau_fb_impl base; +- struct { +- int regions; +- void (*init)(struct nouveau_fb *, int i, u32 addr, u32 size, +- u32 pitch, u32 flags, struct nouveau_fb_tile *); +- void (*comp)(struct nouveau_fb *, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *); +- void (*fini)(struct nouveau_fb *, int i, +- struct nouveau_fb_tile *); +- void (*prog)(struct nouveau_fb *, int i, +- struct nouveau_fb_tile *); +- } tile; +-}; +- +-void nv10_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, +- u32 pitch, u32 flags, struct nouveau_fb_tile *); +-void nv10_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *); +-void nv10_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +- +-void nv20_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, +- u32 pitch, u32 flags, struct nouveau_fb_tile *); +-void nv20_fb_tile_fini(struct nouveau_fb *, int i, struct nouveau_fb_tile *); +-void nv20_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +- +-int nv30_fb_init(struct nouveau_object *); +-void nv30_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, +- u32 pitch, u32 flags, struct nouveau_fb_tile *); +- +-void nv40_fb_tile_comp(struct nouveau_fb *, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *); +- +-int nv41_fb_init(struct nouveau_object *); +-void nv41_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +- +-int nv44_fb_init(struct nouveau_object *); +-void nv44_fb_tile_prog(struct nouveau_fb *, int, struct nouveau_fb_tile *); +- +-void nv46_fb_tile_init(struct nouveau_fb *, int i, u32 addr, u32 size, +- u32 pitch, u32 flags, struct nouveau_fb_tile *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c +deleted file mode 100644 +index ffb7ec6d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv10.c ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-void +-nv10_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +- u32 flags, struct nouveau_fb_tile *tile) +-{ +- tile->addr = 0x80000000 | addr; +- tile->limit = max(1u, addr + size) - 1; +- tile->pitch = pitch; +-} +- +-void +-nv10_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +-{ +- tile->addr = 0; +- tile->limit = 0; +- tile->pitch = 0; +- tile->zcomp = 0; +-} +- +-void +-nv10_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +-{ +- nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); +- nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); +- nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); +- nv_rd32(pfb, 0x100240 + (i * 0x10)); +-} +- +-struct nouveau_oclass * +-nv10_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x10), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = _nouveau_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv10_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv10_fb_tile_init, +- .tile.fini = nv10_fb_tile_fini, +- .tile.prog = nv10_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c +deleted file mode 100644 +index 265d1253..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv1a.c ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv1a_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x1a), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = _nouveau_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv1a_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv10_fb_tile_init, +- .tile.fini = nv10_fb_tile_fini, +- .tile.prog = nv10_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c +deleted file mode 100644 +index 2209ade6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv20.c ++++ /dev/null +@@ -1,95 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-void +-nv20_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +- u32 flags, struct nouveau_fb_tile *tile) +-{ +- tile->addr = 0x00000001 | addr; +- tile->limit = max(1u, addr + size) - 1; +- tile->pitch = pitch; +- if (flags & 4) { +- pfb->tile.comp(pfb, i, size, flags, tile); +- tile->addr |= 2; +- } +-} +- +-static void +-nv20_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *tile) +-{ +- u32 tiles = DIV_ROUND_UP(size, 0x40); +- u32 tags = round_up(tiles / pfb->ram->parts, 0x40); +- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { +- if (!(flags & 2)) tile->zcomp = 0x00000000; /* Z16 */ +- else tile->zcomp = 0x04000000; /* Z24S8 */ +- tile->zcomp |= tile->tag->offset; +- tile->zcomp |= 0x80000000; /* enable */ +-#ifdef __BIG_ENDIAN +- tile->zcomp |= 0x08000000; +-#endif +- } +-} +- +-void +-nv20_fb_tile_fini(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +-{ +- tile->addr = 0; +- tile->limit = 0; +- tile->pitch = 0; +- tile->zcomp = 0; +- nouveau_mm_free(&pfb->tags, &tile->tag); +-} +- +-void +-nv20_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +-{ +- nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit); +- nv_wr32(pfb, 0x100248 + (i * 0x10), tile->pitch); +- nv_wr32(pfb, 0x100240 + (i * 0x10), tile->addr); +- nv_rd32(pfb, 0x100240 + (i * 0x10)); +- nv_wr32(pfb, 0x100300 + (i * 0x04), tile->zcomp); +-} +- +-struct nouveau_oclass * +-nv20_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x20), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = _nouveau_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv20_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv20_fb_tile_init, +- .tile.comp = nv20_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv20_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c +deleted file mode 100644 +index e2a66c35..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv25.c ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-static void +-nv25_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *tile) +-{ +- u32 tiles = DIV_ROUND_UP(size, 0x40); +- u32 tags = round_up(tiles / pfb->ram->parts, 0x40); +- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { +- if (!(flags & 2)) tile->zcomp = 0x00100000; /* Z16 */ +- else tile->zcomp = 0x00200000; /* Z24S8 */ +- tile->zcomp |= tile->tag->offset; +-#ifdef __BIG_ENDIAN +- tile->zcomp |= 0x01000000; +-#endif +- } +-} +- +-struct nouveau_oclass * +-nv25_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x25), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = _nouveau_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv20_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv20_fb_tile_init, +- .tile.comp = nv25_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv20_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c +deleted file mode 100644 +index cbec402b..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv30.c ++++ /dev/null +@@ -1,139 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-void +-nv30_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +- u32 flags, struct nouveau_fb_tile *tile) +-{ +- /* for performance, select alternate bank offset for zeta */ +- if (!(flags & 4)) { +- tile->addr = (0 << 4); +- } else { +- if (pfb->tile.comp) /* z compression */ +- pfb->tile.comp(pfb, i, size, flags, tile); +- tile->addr = (1 << 4); +- } +- +- tile->addr |= 0x00000001; /* enable */ +- tile->addr |= addr; +- tile->limit = max(1u, addr + size) - 1; +- tile->pitch = pitch; +-} +- +-static void +-nv30_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *tile) +-{ +- u32 tiles = DIV_ROUND_UP(size, 0x40); +- u32 tags = round_up(tiles / pfb->ram->parts, 0x40); +- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { +- if (flags & 2) tile->zcomp |= 0x01000000; /* Z16 */ +- else tile->zcomp |= 0x02000000; /* Z24S8 */ +- tile->zcomp |= ((tile->tag->offset ) >> 6); +- tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 12; +-#ifdef __BIG_ENDIAN +- tile->zcomp |= 0x10000000; +-#endif +- } +-} +- +-static int +-calc_bias(struct nv04_fb_priv *priv, int k, int i, int j) +-{ +- struct nouveau_device *device = nv_device(priv); +- int b = (device->chipset > 0x30 ? +- nv_rd32(priv, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) : +- 0) & 0xf; +- +- return 2 * (b & 0x8 ? b - 0x10 : b); +-} +- +-static int +-calc_ref(struct nv04_fb_priv *priv, int l, int k, int i) +-{ +- int j, x = 0; +- +- for (j = 0; j < 4; j++) { +- int m = (l >> (8 * i) & 0xff) + calc_bias(priv, k, i, j); +- +- x |= (0x80 | clamp(m, 0, 0x1f)) << (8 * j); +- } +- +- return x; +-} +- +-int +-nv30_fb_init(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nv04_fb_priv *priv = (void *)object; +- int ret, i, j; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- /* Init the memory timing regs at 0x10037c/0x1003ac */ +- if (device->chipset == 0x30 || +- device->chipset == 0x31 || +- device->chipset == 0x35) { +- /* Related to ROP count */ +- int n = (device->chipset == 0x31 ? 2 : 4); +- int l = nv_rd32(priv, 0x1003d0); +- +- for (i = 0; i < n; i++) { +- for (j = 0; j < 3; j++) +- nv_wr32(priv, 0x10037c + 0xc * i + 0x4 * j, +- calc_ref(priv, l, 0, j)); +- +- for (j = 0; j < 2; j++) +- nv_wr32(priv, 0x1003ac + 0x8 * i + 0x4 * j, +- calc_ref(priv, l, 1, j)); +- } +- } +- +- return 0; +-} +- +-struct nouveau_oclass * +-nv30_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x30), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv30_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv20_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv30_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv20_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c +deleted file mode 100644 +index b2cf8c69..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv35.c ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-static void +-nv35_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *tile) +-{ +- u32 tiles = DIV_ROUND_UP(size, 0x40); +- u32 tags = round_up(tiles / pfb->ram->parts, 0x40); +- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { +- if (flags & 2) tile->zcomp |= 0x04000000; /* Z16 */ +- else tile->zcomp |= 0x08000000; /* Z24S8 */ +- tile->zcomp |= ((tile->tag->offset ) >> 6); +- tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 13; +-#ifdef __BIG_ENDIAN +- tile->zcomp |= 0x40000000; +-#endif +- } +-} +- +-struct nouveau_oclass * +-nv35_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x35), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv30_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv20_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv35_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv20_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c +deleted file mode 100644 +index b4cdae2a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv36.c ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-static void +-nv36_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *tile) +-{ +- u32 tiles = DIV_ROUND_UP(size, 0x40); +- u32 tags = round_up(tiles / pfb->ram->parts, 0x40); +- if (!nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { +- if (flags & 2) tile->zcomp |= 0x10000000; /* Z16 */ +- else tile->zcomp |= 0x20000000; /* Z24S8 */ +- tile->zcomp |= ((tile->tag->offset ) >> 6); +- tile->zcomp |= ((tile->tag->offset + tags - 1) >> 6) << 14; +-#ifdef __BIG_ENDIAN +- tile->zcomp |= 0x80000000; +-#endif +- } +-} +- +-struct nouveau_oclass * +-nv36_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x36), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv30_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv20_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv36_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv20_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c +deleted file mode 100644 +index 52814258..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.c ++++ /dev/null +@@ -1,76 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-void +-nv40_fb_tile_comp(struct nouveau_fb *pfb, int i, u32 size, u32 flags, +- struct nouveau_fb_tile *tile) +-{ +- u32 tiles = DIV_ROUND_UP(size, 0x80); +- u32 tags = round_up(tiles / pfb->ram->parts, 0x100); +- if ( (flags & 2) && +- !nouveau_mm_head(&pfb->tags, 0, 1, tags, tags, 1, &tile->tag)) { +- tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ +- tile->zcomp |= ((tile->tag->offset ) >> 8); +- tile->zcomp |= ((tile->tag->offset + tags - 1) >> 8) << 13; +-#ifdef __BIG_ENDIAN +- tile->zcomp |= 0x40000000; +-#endif +- } +-} +- +-static int +-nv40_fb_init(struct nouveau_object *object) +-{ +- struct nv04_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x10033c, 0x00008000, 0x00000000); +- return 0; +-} +- +-struct nouveau_oclass * +-nv40_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x40), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv40_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv40_ram_oclass, +- .tile.regions = 8, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv40_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv20_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h +deleted file mode 100644 +index 581f8085..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv40.h ++++ /dev/null +@@ -1,17 +0,0 @@ +-#ifndef __NVKM_FB_NV40_H__ +-#define __NVKM_FB_NV40_H__ +- +-#include "priv.h" +- +-struct nv40_ram { +- struct nouveau_ram base; +- u32 ctrl; +- u32 coef; +-}; +- +- +-int nv40_ram_calc(struct nouveau_fb *, u32); +-int nv40_ram_prog(struct nouveau_fb *); +-void nv40_ram_tidy(struct nouveau_fb *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c +deleted file mode 100644 +index b239a861..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv41.c ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-void +-nv41_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +-{ +- nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); +- nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); +- nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); +- nv_rd32(pfb, 0x100600 + (i * 0x10)); +- nv_wr32(pfb, 0x100700 + (i * 0x04), tile->zcomp); +-} +- +-int +-nv41_fb_init(struct nouveau_object *object) +-{ +- struct nv04_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x100800, 0x00000001); +- return 0; +-} +- +-struct nouveau_oclass * +-nv41_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x41), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv41_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv41_ram_oclass, +- .tile.regions = 12, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv40_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv41_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c +deleted file mode 100644 +index d8478208..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv44.c ++++ /dev/null +@@ -1,78 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-static void +-nv44_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +- u32 flags, struct nouveau_fb_tile *tile) +-{ +- tile->addr = 0x00000001; /* mode = vram */ +- tile->addr |= addr; +- tile->limit = max(1u, addr + size) - 1; +- tile->pitch = pitch; +-} +- +-void +-nv44_fb_tile_prog(struct nouveau_fb *pfb, int i, struct nouveau_fb_tile *tile) +-{ +- nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit); +- nv_wr32(pfb, 0x100608 + (i * 0x10), tile->pitch); +- nv_wr32(pfb, 0x100600 + (i * 0x10), tile->addr); +- nv_rd32(pfb, 0x100600 + (i * 0x10)); +-} +- +-int +-nv44_fb_init(struct nouveau_object *object) +-{ +- struct nv04_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x100850, 0x80000000); +- nv_wr32(priv, 0x100800, 0x00000001); +- return 0; +-} +- +-struct nouveau_oclass * +-nv44_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x44), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv44_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv44_ram_oclass, +- .tile.regions = 12, +- .tile.init = nv44_fb_tile_init, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv44_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c +deleted file mode 100644 +index a5b77514..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv46.c ++++ /dev/null +@@ -1,58 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-void +-nv46_fb_tile_init(struct nouveau_fb *pfb, int i, u32 addr, u32 size, u32 pitch, +- u32 flags, struct nouveau_fb_tile *tile) +-{ +- /* for performance, select alternate bank offset for zeta */ +- if (!(flags & 4)) tile->addr = (0 << 3); +- else tile->addr = (1 << 3); +- +- tile->addr |= 0x00000001; /* mode = vram */ +- tile->addr |= addr; +- tile->limit = max(1u, addr + size) - 1; +- tile->pitch = pitch; +-} +- +-struct nouveau_oclass * +-nv46_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x46), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv44_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv44_ram_oclass, +- .tile.regions = 15, +- .tile.init = nv46_fb_tile_init, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv44_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c +deleted file mode 100644 +index 3bea1423..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv47.c ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv47_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x47), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv41_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv41_ram_oclass, +- .tile.regions = 15, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv40_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv41_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c +deleted file mode 100644 +index 666cbd5d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv49.c ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv49_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x49), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv41_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv49_ram_oclass, +- .tile.regions = 15, +- .tile.init = nv30_fb_tile_init, +- .tile.comp = nv40_fb_tile_comp, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv41_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c +deleted file mode 100644 +index 42e64f36..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv4e.c ++++ /dev/null +@@ -1,44 +0,0 @@ +-/* +- * Copyright (C) 2010 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv4e_fb_oclass = &(struct nv04_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x4e), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_fb_ctor, +- .dtor = _nouveau_fb_dtor, +- .init = nv44_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv04_fb_memtype_valid, +- .base.ram = &nv4e_ram_oclass, +- .tile.regions = 12, +- .tile.init = nv46_fb_tile_init, +- .tile.fini = nv20_fb_tile_fini, +- .tile.prog = nv44_fb_tile_prog, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c +deleted file mode 100644 +index 4150b0d1..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c ++++ /dev/null +@@ -1,316 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +- +-#include +- +-#include "nv50.h" +- +-int +-nv50_fb_memtype[0x80] = { +- 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0, +- 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0, +- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0, +- 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, +- 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2, +- 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0 +-}; +- +-bool +-nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype) +-{ +- return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0; +-} +- +-static const struct nouveau_enum vm_dispatch_subclients[] = { +- { 0x00000000, "GRCTX", NULL }, +- { 0x00000001, "NOTIFY", NULL }, +- { 0x00000002, "QUERY", NULL }, +- { 0x00000003, "COND", NULL }, +- { 0x00000004, "M2M_IN", NULL }, +- { 0x00000005, "M2M_OUT", NULL }, +- { 0x00000006, "M2M_NOTIFY", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_ccache_subclients[] = { +- { 0x00000000, "CB", NULL }, +- { 0x00000001, "TIC", NULL }, +- { 0x00000002, "TSC", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_prop_subclients[] = { +- { 0x00000000, "RT0", NULL }, +- { 0x00000001, "RT1", NULL }, +- { 0x00000002, "RT2", NULL }, +- { 0x00000003, "RT3", NULL }, +- { 0x00000004, "RT4", NULL }, +- { 0x00000005, "RT5", NULL }, +- { 0x00000006, "RT6", NULL }, +- { 0x00000007, "RT7", NULL }, +- { 0x00000008, "ZETA", NULL }, +- { 0x00000009, "LOCAL", NULL }, +- { 0x0000000a, "GLOBAL", NULL }, +- { 0x0000000b, "STACK", NULL }, +- { 0x0000000c, "DST2D", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_pfifo_subclients[] = { +- { 0x00000000, "PUSHBUF", NULL }, +- { 0x00000001, "SEMAPHORE", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_bar_subclients[] = { +- { 0x00000000, "FB", NULL }, +- { 0x00000001, "IN", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_client[] = { +- { 0x00000000, "STRMOUT", NULL }, +- { 0x00000003, "DISPATCH", vm_dispatch_subclients }, +- { 0x00000004, "PFIFO_WRITE", NULL }, +- { 0x00000005, "CCACHE", vm_ccache_subclients }, +- { 0x00000006, "PPPP", NULL }, +- { 0x00000007, "CLIPID", NULL }, +- { 0x00000008, "PFIFO_READ", NULL }, +- { 0x00000009, "VFETCH", NULL }, +- { 0x0000000a, "TEXTURE", NULL }, +- { 0x0000000b, "PROP", vm_prop_subclients }, +- { 0x0000000c, "PVP", NULL }, +- { 0x0000000d, "PBSP", NULL }, +- { 0x0000000e, "PCRYPT", NULL }, +- { 0x0000000f, "PCOUNTER", NULL }, +- { 0x00000011, "PDAEMON", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_engine[] = { +- { 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR }, +- { 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP }, +- { 0x00000004, "PEEPHOLE", NULL }, +- { 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO }, +- { 0x00000006, "BAR", vm_bar_subclients }, +- { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP }, +- { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG }, +- { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP }, +- { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT }, +- { 0x0000000b, "PCOUNTER", NULL }, +- { 0x0000000c, "SEMAPHORE_BG", NULL }, +- { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 }, +- { 0x0000000e, "PDAEMON", NULL }, +- {} +-}; +- +-static const struct nouveau_enum vm_fault[] = { +- { 0x00000000, "PT_NOT_PRESENT", NULL }, +- { 0x00000001, "PT_TOO_SHORT", NULL }, +- { 0x00000002, "PAGE_NOT_PRESENT", NULL }, +- { 0x00000003, "PAGE_SYSTEM_ONLY", NULL }, +- { 0x00000004, "PAGE_READ_ONLY", NULL }, +- { 0x00000006, "NULL_DMAOBJ", NULL }, +- { 0x00000007, "WRONG_MEMTYPE", NULL }, +- { 0x0000000b, "VRAM_LIMIT", NULL }, +- { 0x0000000f, "DMAOBJ_LIMIT", NULL }, +- {} +-}; +- +-static void +-nv50_fb_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_device *device = nv_device(subdev); +- struct nouveau_engine *engine; +- struct nv50_fb_priv *priv = (void *)subdev; +- const struct nouveau_enum *en, *cl; +- struct nouveau_object *engctx = NULL; +- u32 trap[6], idx, chan; +- u8 st0, st1, st2, st3; +- int i; +- +- idx = nv_rd32(priv, 0x100c90); +- if (!(idx & 0x80000000)) +- return; +- idx &= 0x00ffffff; +- +- for (i = 0; i < 6; i++) { +- nv_wr32(priv, 0x100c90, idx | i << 24); +- trap[i] = nv_rd32(priv, 0x100c94); +- } +- nv_wr32(priv, 0x100c90, idx | 0x80000000); +- +- /* decode status bits into something more useful */ +- if (device->chipset < 0xa3 || +- device->chipset == 0xaa || device->chipset == 0xac) { +- st0 = (trap[0] & 0x0000000f) >> 0; +- st1 = (trap[0] & 0x000000f0) >> 4; +- st2 = (trap[0] & 0x00000f00) >> 8; +- st3 = (trap[0] & 0x0000f000) >> 12; +- } else { +- st0 = (trap[0] & 0x000000ff) >> 0; +- st1 = (trap[0] & 0x0000ff00) >> 8; +- st2 = (trap[0] & 0x00ff0000) >> 16; +- st3 = (trap[0] & 0xff000000) >> 24; +- } +- chan = (trap[2] << 16) | trap[1]; +- +- en = nouveau_enum_find(vm_engine, st0); +- +- if (en && en->data2) { +- const struct nouveau_enum *orig_en = en; +- while (en->name && en->value == st0 && en->data2) { +- engine = nouveau_engine(subdev, en->data2); +- if (engine) { +- engctx = nouveau_engctx_get(engine, chan); +- if (engctx) +- break; +- } +- en++; +- } +- if (!engctx) +- en = orig_en; +- } +- +- nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ", +- (trap[5] & 0x00000100) ? "read" : "write", +- trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan, +- nouveau_client_name(engctx)); +- +- nouveau_engctx_put(engctx); +- +- if (en) +- pr_cont("%s/", en->name); +- else +- pr_cont("%02x/", st0); +- +- cl = nouveau_enum_find(vm_client, st2); +- if (cl) +- pr_cont("%s/", cl->name); +- else +- pr_cont("%02x/", st2); +- +- if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3); +- else if (en && en->data) cl = nouveau_enum_find(en->data, st3); +- else cl = NULL; +- if (cl) +- pr_cont("%s", cl->name); +- else +- pr_cont("%02x", st3); +- +- pr_cont(" reason: "); +- en = nouveau_enum_find(vm_fault, st1); +- if (en) +- pr_cont("%s\n", en->name); +- else +- pr_cont("0x%08x\n", st1); +-} +- +-int +-nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nv50_fb_priv *priv; +- int ret; +- +- ret = nouveau_fb_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO); +- if (priv->r100c08_page) { +- priv->r100c08 = dma_map_page(nv_device_base(device), +- priv->r100c08_page, 0, PAGE_SIZE, +- DMA_BIDIRECTIONAL); +- if (dma_mapping_error(nv_device_base(device), priv->r100c08)) +- return -EFAULT; +- } else { +- nv_warn(priv, "failed 0x100c08 page alloc\n"); +- } +- +- nv_subdev(priv)->intr = nv50_fb_intr; +- return 0; +-} +- +-void +-nv50_fb_dtor(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nv50_fb_priv *priv = (void *)object; +- +- if (priv->r100c08_page) { +- dma_unmap_page(nv_device_base(device), priv->r100c08, PAGE_SIZE, +- DMA_BIDIRECTIONAL); +- __free_page(priv->r100c08_page); +- } +- +- nouveau_fb_destroy(&priv->base); +-} +- +-int +-nv50_fb_init(struct nouveau_object *object) +-{ +- struct nv50_fb_impl *impl = (void *)object->oclass; +- struct nv50_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- /* Not a clue what this is exactly. Without pointing it at a +- * scratch page, VRAM->GART blits with M2MF (as in DDX DFS) +- * cause IOMMU "read from address 0" errors (rh#561267) +- */ +- nv_wr32(priv, 0x100c08, priv->r100c08 >> 8); +- +- /* This is needed to get meaningful information from 100c90 +- * on traps. No idea what these values mean exactly. */ +- nv_wr32(priv, 0x100c90, impl->trap); +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_fb_oclass = &(struct nv50_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x50), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fb_ctor, +- .dtor = nv50_fb_dtor, +- .init = nv50_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv50_fb_memtype_valid, +- .base.ram = &nv50_ram_oclass, +- .trap = 0x000707ff, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h +deleted file mode 100644 +index c5e5a888..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-#ifndef __NVKM_FB_NV50_H__ +-#define __NVKM_FB_NV50_H__ +- +-#include "priv.h" +- +-struct nv50_fb_priv { +- struct nouveau_fb base; +- struct page *r100c08_page; +- dma_addr_t r100c08; +-}; +- +-int nv50_fb_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv50_fb_dtor(struct nouveau_object *); +-int nv50_fb_init(struct nouveau_object *); +- +-struct nv50_fb_impl { +- struct nouveau_fb_impl base; +- u32 trap; +-}; +- +-#define nv50_ram_create(p,e,o,d) \ +- nv50_ram_create_((p), (e), (o), sizeof(**d), (void **)d) +-int nv50_ram_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-int nv50_ram_get(struct nouveau_fb *, u64 size, u32 align, u32 ncmin, +- u32 memtype, struct nouveau_mem **); +-void nv50_ram_put(struct nouveau_fb *, struct nouveau_mem **); +-void __nv50_ram_put(struct nouveau_fb *, struct nouveau_mem *); +-extern int nv50_fb_memtype[0x80]; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c +deleted file mode 100644 +index cf0e767d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv84.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-struct nouveau_oclass * +-nv84_fb_oclass = &(struct nv50_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0x84), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fb_ctor, +- .dtor = nv50_fb_dtor, +- .init = nv50_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv50_fb_memtype_valid, +- .base.ram = &nv50_ram_oclass, +- .trap = 0x001d07ff, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c +deleted file mode 100644 +index dab6e1c6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nva3.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-struct nouveau_oclass * +-nva3_fb_oclass = &(struct nv50_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0xa3), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fb_ctor, +- .dtor = nv50_fb_dtor, +- .init = nv50_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv50_fb_memtype_valid, +- .base.ram = &nva3_ram_oclass, +- .trap = 0x000d0fff, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c +deleted file mode 100644 +index cba8e681..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaa.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-struct nouveau_oclass * +-nvaa_fb_oclass = &(struct nv50_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0xaa), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fb_ctor, +- .dtor = nv50_fb_dtor, +- .init = nv50_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv50_fb_memtype_valid, +- .base.ram = &nvaa_ram_oclass, +- .trap = 0x001d07ff, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c +deleted file mode 100644 +index 5423faa2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvaf.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-struct nouveau_oclass * +-nvaf_fb_oclass = &(struct nv50_fb_impl) { +- .base.base.handle = NV_SUBDEV(FB, 0xaf), +- .base.base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_fb_ctor, +- .dtor = nv50_fb_dtor, +- .init = nv50_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .base.memtype = nv50_fb_memtype_valid, +- .base.ram = &nvaa_ram_oclass, +- .trap = 0x089d1fff, +-}.base.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c +deleted file mode 100644 +index 32f28dc7..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.c ++++ /dev/null +@@ -1,120 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-extern const u8 nvc0_pte_storage_type_map[256]; +- +-bool +-nvc0_fb_memtype_valid(struct nouveau_fb *pfb, u32 tile_flags) +-{ +- u8 memtype = (tile_flags & 0x0000ff00) >> 8; +- return likely((nvc0_pte_storage_type_map[memtype] != 0xff)); +-} +- +-static void +-nvc0_fb_intr(struct nouveau_subdev *subdev) +-{ +- struct nvc0_fb_priv *priv = (void *)subdev; +- u32 intr = nv_rd32(priv, 0x000100); +- if (intr & 0x08000000) { +- nv_debug(priv, "PFFB intr\n"); +- intr &= ~0x08000000; +- } +- if (intr & 0x00002000) { +- nv_debug(priv, "PBFB intr\n"); +- intr &= ~0x00002000; +- } +-} +- +-int +-nvc0_fb_init(struct nouveau_object *object) +-{ +- struct nvc0_fb_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_fb_init(&priv->base); +- if (ret) +- return ret; +- +- if (priv->r100c10_page) +- nv_wr32(priv, 0x100c10, priv->r100c10 >> 8); +- nv_mask(priv, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */ +- return 0; +-} +- +-void +-nvc0_fb_dtor(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nvc0_fb_priv *priv = (void *)object; +- +- if (priv->r100c10_page) { +- dma_unmap_page(nv_device_base(device), priv->r100c10, PAGE_SIZE, +- DMA_BIDIRECTIONAL); +- __free_page(priv->r100c10_page); +- } +- +- nouveau_fb_destroy(&priv->base); +-} +- +-int +-nvc0_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nvc0_fb_priv *priv; +- int ret; +- +- ret = nouveau_fb_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->r100c10_page = alloc_page(GFP_KERNEL | __GFP_ZERO); +- if (priv->r100c10_page) { +- priv->r100c10 = dma_map_page(nv_device_base(device), +- priv->r100c10_page, 0, PAGE_SIZE, +- DMA_BIDIRECTIONAL); +- if (dma_mapping_error(nv_device_base(device), priv->r100c10)) +- return -EFAULT; +- } +- +- nv_subdev(priv)->intr = nvc0_fb_intr; +- return 0; +-} +- +-struct nouveau_oclass * +-nvc0_fb_oclass = &(struct nouveau_fb_impl) { +- .base.handle = NV_SUBDEV(FB, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_fb_ctor, +- .dtor = nvc0_fb_dtor, +- .init = nvc0_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .memtype = nvc0_fb_memtype_valid, +- .ram = &nvc0_ram_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h b/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h +deleted file mode 100644 +index 705a06d7..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nvc0.h ++++ /dev/null +@@ -1,31 +0,0 @@ +-#ifndef __NVKM_RAM_NVC0_H__ +-#define __NVKM_RAM_NVC0_H__ +- +-#include "priv.h" +-#include "nv50.h" +- +-struct nvc0_fb_priv { +- struct nouveau_fb base; +- struct page *r100c10_page; +- dma_addr_t r100c10; +-}; +- +-int nvc0_fb_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nvc0_fb_dtor(struct nouveau_object *); +-int nvc0_fb_init(struct nouveau_object *); +-bool nvc0_fb_memtype_valid(struct nouveau_fb *, u32); +- +- +-#define nvc0_ram_create(p,e,o,m,d) \ +- nvc0_ram_create_((p), (e), (o), (m), sizeof(**d), (void **)d) +-int nvc0_ram_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u32, int, void **); +-int nvc0_ram_get(struct nouveau_fb *, u64, u32, u32, u32, +- struct nouveau_mem **); +-void nvc0_ram_put(struct nouveau_fb *, struct nouveau_mem **); +- +-int nve0_ram_init(struct nouveau_object*); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c +deleted file mode 100644 +index 595db50c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nve0.c ++++ /dev/null +@@ -1,38 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-struct nouveau_oclass * +-nve0_fb_oclass = &(struct nouveau_fb_impl) { +- .base.handle = NV_SUBDEV(FB, 0xe0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_fb_ctor, +- .dtor = nvc0_fb_dtor, +- .init = nvc0_fb_init, +- .fini = _nouveau_fb_fini, +- }, +- .memtype = nvc0_fb_memtype_valid, +- .ram = &nve0_ram_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h +deleted file mode 100644 +index 60322e90..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/priv.h ++++ /dev/null +@@ -1,75 +0,0 @@ +-#ifndef __NVKM_FB_PRIV_H__ +-#define __NVKM_FB_PRIV_H__ +- +-#include +- +-#define nouveau_ram_create(p,e,o,d) \ +- nouveau_object_create_((p), (e), (o), 0, sizeof(**d), (void **)d) +-#define nouveau_ram_destroy(p) \ +- nouveau_object_destroy(&(p)->base) +-#define nouveau_ram_init(p) \ +- nouveau_object_init(&(p)->base) +-#define nouveau_ram_fini(p,s) \ +- nouveau_object_fini(&(p)->base, (s)) +- +-#define nouveau_ram_create_(p,e,o,s,d) \ +- nouveau_object_create_((p), (e), (o), 0, (s), (void **)d) +-#define _nouveau_ram_dtor nouveau_object_destroy +-#define _nouveau_ram_init nouveau_object_init +-#define _nouveau_ram_fini nouveau_object_fini +- +-extern struct nouveau_oclass nv04_ram_oclass; +-extern struct nouveau_oclass nv10_ram_oclass; +-extern struct nouveau_oclass nv1a_ram_oclass; +-extern struct nouveau_oclass nv20_ram_oclass; +-extern struct nouveau_oclass nv40_ram_oclass; +-extern struct nouveau_oclass nv41_ram_oclass; +-extern struct nouveau_oclass nv44_ram_oclass; +-extern struct nouveau_oclass nv49_ram_oclass; +-extern struct nouveau_oclass nv4e_ram_oclass; +-extern struct nouveau_oclass nv50_ram_oclass; +-extern struct nouveau_oclass nva3_ram_oclass; +-extern struct nouveau_oclass nvaa_ram_oclass; +-extern struct nouveau_oclass nvc0_ram_oclass; +-extern struct nouveau_oclass nve0_ram_oclass; +-extern struct nouveau_oclass gk20a_ram_oclass; +-extern struct nouveau_oclass gm107_ram_oclass; +- +-int nouveau_sddr2_calc(struct nouveau_ram *ram); +-int nouveau_sddr3_calc(struct nouveau_ram *ram); +-int nouveau_gddr5_calc(struct nouveau_ram *ram, bool nuts); +- +-#define nouveau_fb_create(p,e,c,d) \ +- nouveau_fb_create_((p), (e), (c), sizeof(**d), (void **)d) +-#define nouveau_fb_destroy(p) ({ \ +- struct nouveau_fb *pfb = (p); \ +- _nouveau_fb_dtor(nv_object(pfb)); \ +-}) +-#define nouveau_fb_init(p) ({ \ +- struct nouveau_fb *pfb = (p); \ +- _nouveau_fb_init(nv_object(pfb)); \ +-}) +-#define nouveau_fb_fini(p,s) ({ \ +- struct nouveau_fb *pfb = (p); \ +- _nouveau_fb_fini(nv_object(pfb), (s)); \ +-}) +- +-int nouveau_fb_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_fb_dtor(struct nouveau_object *); +-int _nouveau_fb_init(struct nouveau_object *); +-int _nouveau_fb_fini(struct nouveau_object *, bool); +- +-struct nouveau_fb_impl { +- struct nouveau_oclass base; +- struct nouveau_oclass *ram; +- bool (*memtype)(struct nouveau_fb *, u32); +-}; +- +-bool nv04_fb_memtype_valid(struct nouveau_fb *, u32 memtype); +-bool nv50_fb_memtype_valid(struct nouveau_fb *, u32 memtype); +- +-struct nouveau_bios; +-int nouveau_fb_bios_memtype(struct nouveau_bios *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h +deleted file mode 100644 +index d1fbbe4b..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramfuc.h ++++ /dev/null +@@ -1,168 +0,0 @@ +-#ifndef __NVKM_FBRAM_FUC_H__ +-#define __NVKM_FBRAM_FUC_H__ +- +-#include +- +-struct ramfuc { +- struct nouveau_memx *memx; +- struct nouveau_fb *pfb; +- int sequence; +-}; +- +-struct ramfuc_reg { +- int sequence; +- bool force; +- u32 addr; +- u32 stride; /* in bytes */ +- u32 mask; +- u32 data; +-}; +- +-static inline struct ramfuc_reg +-ramfuc_stride(u32 addr, u32 stride, u32 mask) +-{ +- return (struct ramfuc_reg) { +- .sequence = 0, +- .addr = addr, +- .stride = stride, +- .mask = mask, +- .data = 0xdeadbeef, +- }; +-} +- +-static inline struct ramfuc_reg +-ramfuc_reg2(u32 addr1, u32 addr2) +-{ +- return (struct ramfuc_reg) { +- .sequence = 0, +- .addr = addr1, +- .stride = addr2 - addr1, +- .mask = 0x3, +- .data = 0xdeadbeef, +- }; +-} +- +-static noinline struct ramfuc_reg +-ramfuc_reg(u32 addr) +-{ +- return (struct ramfuc_reg) { +- .sequence = 0, +- .addr = addr, +- .stride = 0, +- .mask = 0x1, +- .data = 0xdeadbeef, +- }; +-} +- +-static inline int +-ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb) +-{ +- struct nouveau_pwr *ppwr = nouveau_pwr(pfb); +- int ret; +- +- ret = nouveau_memx_init(ppwr, &ram->memx); +- if (ret) +- return ret; +- +- ram->sequence++; +- ram->pfb = pfb; +- return 0; +-} +- +-static inline int +-ramfuc_exec(struct ramfuc *ram, bool exec) +-{ +- int ret = 0; +- if (ram->pfb) { +- ret = nouveau_memx_fini(&ram->memx, exec); +- ram->pfb = NULL; +- } +- return ret; +-} +- +-static inline u32 +-ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) +-{ +- if (reg->sequence != ram->sequence) +- reg->data = nv_rd32(ram->pfb, reg->addr); +- return reg->data; +-} +- +-static inline void +-ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) +-{ +- unsigned int mask, off = 0; +- +- reg->sequence = ram->sequence; +- reg->data = data; +- +- for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { +- if (mask & 1) { +- nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data); +- } +- +- off += reg->stride; +- } +-} +- +-static inline void +-ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg) +-{ +- reg->force = true; +-} +- +-static inline u32 +-ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) +-{ +- u32 temp = ramfuc_rd32(ram, reg); +- if (temp != ((temp & ~mask) | data) || reg->force) { +- ramfuc_wr32(ram, reg, (temp & ~mask) | data); +- reg->force = false; +- } +- return temp; +-} +- +-static inline void +-ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) +-{ +- nouveau_memx_wait(ram->memx, addr, mask, data, nsec); +-} +- +-static inline void +-ramfuc_nsec(struct ramfuc *ram, u32 nsec) +-{ +- nouveau_memx_nsec(ram->memx, nsec); +-} +- +-static inline void +-ramfuc_wait_vblank(struct ramfuc *ram) +-{ +- nouveau_memx_wait_vblank(ram->memx); +-} +- +-static inline void +-ramfuc_block(struct ramfuc *ram) +-{ +- nouveau_memx_block(ram->memx); +-} +- +-static inline void +-ramfuc_unblock(struct ramfuc *ram) +-{ +- nouveau_memx_unblock(ram->memx); +-} +- +-#define ram_init(s,p) ramfuc_init(&(s)->base, (p)) +-#define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) +-#define ram_have(s,r) ((s)->r_##r.addr != 0x000000) +-#define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) +-#define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) +-#define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) +-#define ram_mask(s,r,m,d) ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d)) +-#define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) +-#define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) +-#define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) +-#define ram_block(s) ramfuc_block(&(s)->base) +-#define ram_unblock(s) ramfuc_unblock(&(s)->base) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c +deleted file mode 100644 +index 4d77d75e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgk20a.c ++++ /dev/null +@@ -1,152 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include "priv.h" +- +-#include +- +-struct gk20a_mem { +- struct nouveau_mem base; +- void *cpuaddr; +- dma_addr_t handle; +-}; +-#define to_gk20a_mem(m) container_of(m, struct gk20a_mem, base) +- +-static void +-gk20a_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +-{ +- struct device *dev = nv_device_base(nv_device(pfb)); +- struct gk20a_mem *mem = to_gk20a_mem(*pmem); +- +- *pmem = NULL; +- if (unlikely(mem == NULL)) +- return; +- +- if (likely(mem->cpuaddr)) +- dma_free_coherent(dev, mem->base.size << PAGE_SHIFT, +- mem->cpuaddr, mem->handle); +- +- kfree(mem->base.pages); +- kfree(mem); +-} +- +-static int +-gk20a_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, +- u32 memtype, struct nouveau_mem **pmem) +-{ +- struct device *dev = nv_device_base(nv_device(pfb)); +- struct gk20a_mem *mem; +- u32 type = memtype & 0xff; +- u32 npages, order; +- int i; +- +- nv_debug(pfb, "%s: size: %llx align: %x, ncmin: %x\n", __func__, size, +- align, ncmin); +- +- npages = size >> PAGE_SHIFT; +- if (npages == 0) +- npages = 1; +- +- if (align == 0) +- align = PAGE_SIZE; +- align >>= PAGE_SHIFT; +- +- /* round alignment to the next power of 2, if needed */ +- order = fls(align); +- if ((align & (align - 1)) == 0) +- order--; +- align = BIT(order); +- +- /* ensure returned address is correctly aligned */ +- npages = max(align, npages); +- +- mem = kzalloc(sizeof(*mem), GFP_KERNEL); +- if (!mem) +- return -ENOMEM; +- +- mem->base.size = npages; +- mem->base.memtype = type; +- +- mem->base.pages = kzalloc(sizeof(dma_addr_t) * npages, GFP_KERNEL); +- if (!mem->base.pages) { +- kfree(mem); +- return -ENOMEM; +- } +- +- *pmem = &mem->base; +- +- mem->cpuaddr = dma_alloc_coherent(dev, npages << PAGE_SHIFT, +- &mem->handle, GFP_KERNEL); +- if (!mem->cpuaddr) { +- nv_error(pfb, "%s: cannot allocate memory!\n", __func__); +- gk20a_ram_put(pfb, pmem); +- return -ENOMEM; +- } +- +- align <<= PAGE_SHIFT; +- +- /* alignment check */ +- if (unlikely(mem->handle & (align - 1))) +- nv_warn(pfb, "memory not aligned as requested: %pad (0x%x)\n", +- &mem->handle, align); +- +- nv_debug(pfb, "alloc size: 0x%x, align: 0x%x, paddr: %pad, vaddr: %p\n", +- npages << PAGE_SHIFT, align, &mem->handle, mem->cpuaddr); +- +- for (i = 0; i < npages; i++) +- mem->base.pages[i] = mem->handle + (PAGE_SIZE * i); +- +- mem->base.offset = (u64)mem->base.pages[0]; +- +- return 0; +-} +- +-static int +-gk20a_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 datasize, +- struct nouveau_object **pobject) +-{ +- struct nouveau_ram *ram; +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- ram->type = NV_MEM_TYPE_STOLEN; +- ram->size = get_num_physpages() << PAGE_SHIFT; +- +- ram->get = gk20a_ram_get; +- ram->put = gk20a_ram_put; +- +- return 0; +-} +- +-struct nouveau_oclass +-gk20a_ram_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gk20a_ram_ctor, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c +deleted file mode 100644 +index 4c636359..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramgm107.c ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nvc0.h" +- +-struct gm107_ram { +- struct nouveau_ram base; +-}; +- +-static int +-gm107_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gm107_ram *ram; +- int ret; +- +- ret = nvc0_ram_create(parent, engine, oclass, 0x021c14, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass +-gm107_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gm107_ram_ctor, +- .dtor = _nouveau_ram_dtor, +- .init = nve0_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c +deleted file mode 100644 +index 1972268d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv04.c ++++ /dev/null +@@ -1,80 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "priv.h" +- +-static int +-nv04_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- u32 boot0 = nv_rd32(pfb, NV04_PFB_BOOT_0); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- if (boot0 & 0x00000100) { +- ram->size = ((boot0 >> 12) & 0xf) * 2 + 2; +- ram->size *= 1024 * 1024; +- } else { +- switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { +- case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: +- ram->size = 32 * 1024 * 1024; +- break; +- case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: +- ram->size = 16 * 1024 * 1024; +- break; +- case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: +- ram->size = 8 * 1024 * 1024; +- break; +- case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: +- ram->size = 4 * 1024 * 1024; +- break; +- } +- } +- +- if ((boot0 & 0x00000038) <= 0x10) +- ram->type = NV_MEM_TYPE_SGRAM; +- else +- ram->type = NV_MEM_TYPE_SDRAM; +- return 0; +-} +- +-struct nouveau_oclass +-nv04_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c +deleted file mode 100644 +index 8311f377..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv10.c ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-nv10_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- u32 cfg0 = nv_rd32(pfb, 0x100200); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- if (cfg0 & 0x00000001) +- ram->type = NV_MEM_TYPE_DDR1; +- else +- ram->type = NV_MEM_TYPE_SDRAM; +- +- ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; +- return 0; +-} +- +- +-struct nouveau_oclass +-nv10_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv10_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c +deleted file mode 100644 +index d0caddfb..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv1a.c ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-nv1a_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- struct pci_dev *bridge; +- u32 mem, mib; +- int ret; +- +- bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); +- if (!bridge) { +- nv_fatal(pfb, "no bridge device\n"); +- return -ENODEV; +- } +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- if (nv_device(pfb)->chipset == 0x1a) { +- pci_read_config_dword(bridge, 0x7c, &mem); +- mib = ((mem >> 6) & 31) + 1; +- } else { +- pci_read_config_dword(bridge, 0x84, &mem); +- mib = ((mem >> 4) & 127) + 1; +- } +- +- ram->type = NV_MEM_TYPE_STOLEN; +- ram->size = mib * 1024 * 1024; +- return 0; +-} +- +-struct nouveau_oclass +-nv1a_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv1a_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c +deleted file mode 100644 +index fdc11bba..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv20.c ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-nv20_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- u32 pbus1218 = nv_rd32(pfb, 0x001218); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- switch (pbus1218 & 0x00000300) { +- case 0x00000000: ram->type = NV_MEM_TYPE_SDRAM; break; +- case 0x00000100: ram->type = NV_MEM_TYPE_DDR1; break; +- case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break; +- case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break; +- } +- ram->size = (nv_rd32(pfb, 0x10020c) & 0xff000000); +- ram->parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; +- ram->tags = nv_rd32(pfb, 0x100320); +- return 0; +-} +- +-struct nouveau_oclass +-nv20_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv20_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c +deleted file mode 100644 +index 7648beb1..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv40.c ++++ /dev/null +@@ -1,215 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +- +-#include "nv40.h" +- +-int +-nv40_ram_calc(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nv40_ram *ram = (void *)pfb->ram; +- struct nvbios_pll pll; +- int N1, M1, N2, M2; +- int log2P, ret; +- +- ret = nvbios_pll_parse(bios, 0x04, &pll); +- if (ret) { +- nv_error(pfb, "mclk pll data not found\n"); +- return ret; +- } +- +- ret = nv04_pll_calc(nv_subdev(pfb), &pll, freq, +- &N1, &M1, &N2, &M2, &log2P); +- if (ret < 0) +- return ret; +- +- ram->ctrl = 0x80000000 | (log2P << 16); +- ram->ctrl |= min(pll.bias_p + log2P, (int)pll.max_p) << 20; +- if (N2 == M2) { +- ram->ctrl |= 0x00000100; +- ram->coef = (N1 << 8) | M1; +- } else { +- ram->ctrl |= 0x40000000; +- ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; +- } +- +- return 0; +-} +- +-int +-nv40_ram_prog(struct nouveau_fb *pfb) +-{ +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nv40_ram *ram = (void *)pfb->ram; +- struct bit_entry M; +- u32 crtc_mask = 0; +- u8 sr1[2]; +- int i; +- +- /* determine which CRTCs are active, fetch VGA_SR1 for each */ +- for (i = 0; i < 2; i++) { +- u32 vbl = nv_rd32(pfb, 0x600808 + (i * 0x2000)); +- u32 cnt = 0; +- do { +- if (vbl != nv_rd32(pfb, 0x600808 + (i * 0x2000))) { +- nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01); +- sr1[i] = nv_rd08(pfb, 0x0c03c5 + (i * 0x2000)); +- if (!(sr1[i] & 0x20)) +- crtc_mask |= (1 << i); +- break; +- } +- udelay(1); +- } while (cnt++ < 32); +- } +- +- /* wait for vblank start on active crtcs, disable memory access */ +- for (i = 0; i < 2; i++) { +- if (!(crtc_mask & (1 << i))) +- continue; +- nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000); +- nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); +- nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01); +- nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); +- } +- +- /* prepare ram for reclocking */ +- nv_wr32(pfb, 0x1002d4, 0x00000001); /* precharge */ +- nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */ +- nv_wr32(pfb, 0x1002d0, 0x00000001); /* refresh */ +- nv_mask(pfb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ +- nv_wr32(pfb, 0x1002dc, 0x00000001); /* enable self-refresh */ +- +- /* change the PLL of each memory partition */ +- nv_mask(pfb, 0x00c040, 0x0000c000, 0x00000000); +- switch (nv_device(pfb)->chipset) { +- case 0x40: +- case 0x45: +- case 0x41: +- case 0x42: +- case 0x47: +- nv_mask(pfb, 0x004044, 0xc0771100, ram->ctrl); +- nv_mask(pfb, 0x00402c, 0xc0771100, ram->ctrl); +- nv_wr32(pfb, 0x004048, ram->coef); +- nv_wr32(pfb, 0x004030, ram->coef); +- case 0x43: +- case 0x49: +- case 0x4b: +- nv_mask(pfb, 0x004038, 0xc0771100, ram->ctrl); +- nv_wr32(pfb, 0x00403c, ram->coef); +- default: +- nv_mask(pfb, 0x004020, 0xc0771100, ram->ctrl); +- nv_wr32(pfb, 0x004024, ram->coef); +- break; +- } +- udelay(100); +- nv_mask(pfb, 0x00c040, 0x0000c000, 0x0000c000); +- +- /* re-enable normal operation of memory controller */ +- nv_wr32(pfb, 0x1002dc, 0x00000000); +- nv_mask(pfb, 0x100210, 0x80000000, 0x80000000); +- udelay(100); +- +- /* execute memory reset script from vbios */ +- if (!bit_entry(bios, 'M', &M)) { +- struct nvbios_init init = { +- .subdev = nv_subdev(pfb), +- .bios = bios, +- .offset = nv_ro16(bios, M.offset + 0x00), +- .execute = 1, +- }; +- +- nvbios_exec(&init); +- } +- +- /* make sure we're in vblank (hopefully the same one as before), and +- * then re-enable crtc memory access +- */ +- for (i = 0; i < 2; i++) { +- if (!(crtc_mask & (1 << i))) +- continue; +- nv_wait(pfb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); +- nv_wr08(pfb, 0x0c03c4 + (i * 0x2000), 0x01); +- nv_wr08(pfb, 0x0c03c5 + (i * 0x2000), sr1[i]); +- } +- +- return 0; +-} +- +-void +-nv40_ram_tidy(struct nouveau_fb *pfb) +-{ +-} +- +-static int +-nv40_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nv40_ram *ram; +- u32 pbus1218 = nv_rd32(pfb, 0x001218); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- switch (pbus1218 & 0x00000300) { +- case 0x00000000: ram->base.type = NV_MEM_TYPE_SDRAM; break; +- case 0x00000100: ram->base.type = NV_MEM_TYPE_DDR1; break; +- case 0x00000200: ram->base.type = NV_MEM_TYPE_GDDR3; break; +- case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break; +- } +- +- ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; +- ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; +- ram->base.tags = nv_rd32(pfb, 0x100320); +- ram->base.calc = nv40_ram_calc; +- ram->base.prog = nv40_ram_prog; +- ram->base.tidy = nv40_ram_tidy; +- return 0; +-} +- +- +-struct nouveau_oclass +-nv40_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c +deleted file mode 100644 +index d64498a4..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv41.c ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-static int +-nv41_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nv40_ram *ram; +- u32 pfb474 = nv_rd32(pfb, 0x100474); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- if (pfb474 & 0x00000004) +- ram->base.type = NV_MEM_TYPE_GDDR3; +- if (pfb474 & 0x00000002) +- ram->base.type = NV_MEM_TYPE_DDR2; +- if (pfb474 & 0x00000001) +- ram->base.type = NV_MEM_TYPE_DDR1; +- +- ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; +- ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; +- ram->base.tags = nv_rd32(pfb, 0x100320); +- ram->base.calc = nv40_ram_calc; +- ram->base.prog = nv40_ram_prog; +- ram->base.tidy = nv40_ram_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nv41_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv41_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c +deleted file mode 100644 +index 089acac8..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv44.c ++++ /dev/null +@@ -1,65 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-static int +-nv44_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nv40_ram *ram; +- u32 pfb474 = nv_rd32(pfb, 0x100474); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- if (pfb474 & 0x00000004) +- ram->base.type = NV_MEM_TYPE_GDDR3; +- if (pfb474 & 0x00000002) +- ram->base.type = NV_MEM_TYPE_DDR2; +- if (pfb474 & 0x00000001) +- ram->base.type = NV_MEM_TYPE_DDR1; +- +- ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; +- ram->base.calc = nv40_ram_calc; +- ram->base.prog = nv40_ram_prog; +- ram->base.tidy = nv40_ram_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nv44_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv44_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c +deleted file mode 100644 +index baa013af..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv49.c ++++ /dev/null +@@ -1,67 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv40.h" +- +-static int +-nv49_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nv40_ram *ram; +- u32 pfb914 = nv_rd32(pfb, 0x100914); +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- switch (pfb914 & 0x00000003) { +- case 0x00000000: ram->base.type = NV_MEM_TYPE_DDR1; break; +- case 0x00000001: ram->base.type = NV_MEM_TYPE_DDR2; break; +- case 0x00000002: ram->base.type = NV_MEM_TYPE_GDDR3; break; +- case 0x00000003: break; +- } +- +- ram->base.size = nv_rd32(pfb, 0x10020c) & 0xff000000; +- ram->base.parts = (nv_rd32(pfb, 0x100200) & 0x00000003) + 1; +- ram->base.tags = nv_rd32(pfb, 0x100320); +- ram->base.calc = nv40_ram_calc; +- ram->base.prog = nv40_ram_prog; +- ram->base.tidy = nv40_ram_tidy; +- return 0; +-} +- +-struct nouveau_oclass +-nv49_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv49_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c +deleted file mode 100644 +index 63a6aab8..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv4e.c ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-nv4e_ram_create(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- ram->size = nv_rd32(pfb, 0x10020c) & 0xff000000; +- ram->type = NV_MEM_TYPE_STOLEN; +- return 0; +-} +- +-struct nouveau_oclass +-nv4e_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv4e_ram_create, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c +deleted file mode 100644 +index 64a983c9..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnv50.c ++++ /dev/null +@@ -1,470 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include "ramseq.h" +- +-#include "nv50.h" +- +-struct nv50_ramseq { +- struct hwsq base; +- struct hwsq_reg r_0x002504; +- struct hwsq_reg r_0x004008; +- struct hwsq_reg r_0x00400c; +- struct hwsq_reg r_0x00c040; +- struct hwsq_reg r_0x100210; +- struct hwsq_reg r_0x1002d0; +- struct hwsq_reg r_0x1002d4; +- struct hwsq_reg r_0x1002dc; +- struct hwsq_reg r_0x100da0[8]; +- struct hwsq_reg r_0x100e20; +- struct hwsq_reg r_0x100e24; +- struct hwsq_reg r_0x611200; +- struct hwsq_reg r_timing[9]; +- struct hwsq_reg r_mr[4]; +-}; +- +-struct nv50_ram { +- struct nouveau_ram base; +- struct nv50_ramseq hwsq; +-}; +- +-#define QFX5800NVA0 1 +- +-static int +-nv50_ram_calc(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nv50_ram *ram = (void *)pfb->ram; +- struct nv50_ramseq *hwsq = &ram->hwsq; +- struct nvbios_perfE perfE; +- struct nvbios_pll mpll; +- struct { +- u32 data; +- u8 size; +- } ramcfg, timing; +- u8 ver, hdr, cnt, len, strap; +- int N1, M1, N2, M2, P; +- int ret, i; +- +- /* lookup closest matching performance table entry for frequency */ +- i = 0; +- do { +- ramcfg.data = nvbios_perfEp(bios, i++, &ver, &hdr, &cnt, +- &ramcfg.size, &perfE); +- if (!ramcfg.data || (ver < 0x25 || ver >= 0x40) || +- (ramcfg.size < 2)) { +- nv_error(pfb, "invalid/missing perftab entry\n"); +- return -EINVAL; +- } +- } while (perfE.memory < freq); +- +- /* locate specific data set for the attached memory */ +- strap = nvbios_ramcfg_index(nv_subdev(pfb)); +- if (strap >= cnt) { +- nv_error(pfb, "invalid ramcfg strap\n"); +- return -EINVAL; +- } +- +- ramcfg.data += hdr + (strap * ramcfg.size); +- +- /* lookup memory timings, if bios says they're present */ +- strap = nv_ro08(bios, ramcfg.data + 0x01); +- if (strap != 0xff) { +- timing.data = nvbios_timingEe(bios, strap, &ver, &hdr, +- &cnt, &len); +- if (!timing.data || ver != 0x10 || hdr < 0x12) { +- nv_error(pfb, "invalid/missing timing entry " +- "%02x %04x %02x %02x\n", +- strap, timing.data, ver, hdr); +- return -EINVAL; +- } +- } else { +- timing.data = 0; +- } +- +- ret = ram_init(hwsq, nv_subdev(pfb)); +- if (ret) +- return ret; +- +- ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */ +- ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */ +- ram_wr32(hwsq, 0x611200, 0x00003300); +- ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ +- ram_nsec(hwsq, 8000); +- ram_setf(hwsq, 0x10, 0x00); /* disable fb */ +- ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ +- +- ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ +- ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ +- ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ +- ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */ +- ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */ +- +- ret = nvbios_pll_parse(bios, 0x004008, &mpll); +- mpll.vco2.max_freq = 0; +- if (ret == 0) { +- ret = nv04_pll_calc(nv_subdev(pfb), &mpll, freq, +- &N1, &M1, &N2, &M2, &P); +- if (ret == 0) +- ret = -EINVAL; +- } +- +- if (ret < 0) +- return ret; +- +- ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000); +- ram_mask(hwsq, 0x004008, 0x00000200, 0x00000200); +- ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); +- ram_mask(hwsq, 0x004008, 0x81ff0000, 0x80000000 | (mpll.bias_p << 19) | +- (P << 22) | (P << 16)); +-#if QFX5800NVA0 +- for (i = 0; i < 8; i++) +- ram_mask(hwsq, 0x100da0[i], 0x00000000, 0x00000000); /*XXX*/ +-#endif +- ram_nsec(hwsq, 96000); /*XXX*/ +- ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000); +- +- ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */ +- ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */ +- +- ram_nsec(hwsq, 12000); +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_DDR2: +- ram_nuke(hwsq, mr[0]); /* force update */ +- ram_mask(hwsq, mr[0], 0x000, 0x000); +- break; +- case NV_MEM_TYPE_GDDR3: +- ram_mask(hwsq, mr[2], 0x000, 0x000); +- ram_nuke(hwsq, mr[0]); /* force update */ +- ram_mask(hwsq, mr[0], 0x000, 0x000); +- break; +- default: +- break; +- } +- +- ram_mask(hwsq, timing[3], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[1], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[6], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[7], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[8], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[2], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[4], 0x00000000, 0x00000000); /*XXX*/ +- ram_mask(hwsq, timing[5], 0x00000000, 0x00000000); /*XXX*/ +- +- ram_mask(hwsq, timing[0], 0x00000000, 0x00000000); /*XXX*/ +- +-#if QFX5800NVA0 +- ram_nuke(hwsq, 0x100e24); +- ram_mask(hwsq, 0x100e24, 0x00000000, 0x00000000); +- ram_nuke(hwsq, 0x100e20); +- ram_mask(hwsq, 0x100e20, 0x00000000, 0x00000000); +-#endif +- +- ram_mask(hwsq, mr[0], 0x100, 0x100); +- ram_mask(hwsq, mr[0], 0x100, 0x000); +- +- ram_setf(hwsq, 0x10, 0x01); /* enable fb */ +- ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ +- ram_wr32(hwsq, 0x611200, 0x00003330); +- ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */ +- return 0; +-} +- +-static int +-nv50_ram_prog(struct nouveau_fb *pfb) +-{ +- struct nouveau_device *device = nv_device(pfb); +- struct nv50_ram *ram = (void *)pfb->ram; +- struct nv50_ramseq *hwsq = &ram->hwsq; +- +- ram_exec(hwsq, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); +- return 0; +-} +- +-static void +-nv50_ram_tidy(struct nouveau_fb *pfb) +-{ +- struct nv50_ram *ram = (void *)pfb->ram; +- struct nv50_ramseq *hwsq = &ram->hwsq; +- ram_exec(hwsq, false); +-} +- +-void +-__nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem *mem) +-{ +- struct nouveau_mm_node *this; +- +- while (!list_empty(&mem->regions)) { +- this = list_first_entry(&mem->regions, typeof(*this), rl_entry); +- +- list_del(&this->rl_entry); +- nouveau_mm_free(&pfb->vram, &this); +- } +- +- nouveau_mm_free(&pfb->tags, &mem->tag); +-} +- +-void +-nv50_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +-{ +- struct nouveau_mem *mem = *pmem; +- +- *pmem = NULL; +- if (unlikely(mem == NULL)) +- return; +- +- mutex_lock(&pfb->base.mutex); +- __nv50_ram_put(pfb, mem); +- mutex_unlock(&pfb->base.mutex); +- +- kfree(mem); +-} +- +-int +-nv50_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, +- u32 memtype, struct nouveau_mem **pmem) +-{ +- struct nouveau_mm *heap = &pfb->vram; +- struct nouveau_mm *tags = &pfb->tags; +- struct nouveau_mm_node *r; +- struct nouveau_mem *mem; +- int comp = (memtype & 0x300) >> 8; +- int type = (memtype & 0x07f); +- int back = (memtype & 0x800); +- int min, max, ret; +- +- max = (size >> 12); +- min = ncmin ? (ncmin >> 12) : max; +- align >>= 12; +- +- mem = kzalloc(sizeof(*mem), GFP_KERNEL); +- if (!mem) +- return -ENOMEM; +- +- mutex_lock(&pfb->base.mutex); +- if (comp) { +- if (align == 16) { +- int n = (max >> 4) * comp; +- +- ret = nouveau_mm_head(tags, 0, 1, n, n, 1, &mem->tag); +- if (ret) +- mem->tag = NULL; +- } +- +- if (unlikely(!mem->tag)) +- comp = 0; +- } +- +- INIT_LIST_HEAD(&mem->regions); +- mem->memtype = (comp << 7) | type; +- mem->size = max; +- +- type = nv50_fb_memtype[type]; +- do { +- if (back) +- ret = nouveau_mm_tail(heap, 0, type, max, min, align, &r); +- else +- ret = nouveau_mm_head(heap, 0, type, max, min, align, &r); +- if (ret) { +- mutex_unlock(&pfb->base.mutex); +- pfb->ram->put(pfb, &mem); +- return ret; +- } +- +- list_add_tail(&r->rl_entry, &mem->regions); +- max -= r->length; +- } while (max); +- mutex_unlock(&pfb->base.mutex); +- +- r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); +- mem->offset = (u64)r->offset << 12; +- *pmem = mem; +- return 0; +-} +- +-static u32 +-nv50_fb_vram_rblock(struct nouveau_fb *pfb, struct nouveau_ram *ram) +-{ +- int colbits, rowbitsa, rowbitsb, banks; +- u64 rowsize, predicted; +- u32 r0, r4, rt, rblock_size; +- +- r0 = nv_rd32(pfb, 0x100200); +- r4 = nv_rd32(pfb, 0x100204); +- rt = nv_rd32(pfb, 0x100250); +- nv_debug(pfb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, +- nv_rd32(pfb, 0x001540)); +- +- colbits = (r4 & 0x0000f000) >> 12; +- rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; +- rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; +- banks = 1 << (((r4 & 0x03000000) >> 24) + 2); +- +- rowsize = ram->parts * banks * (1 << colbits) * 8; +- predicted = rowsize << rowbitsa; +- if (r0 & 0x00000004) +- predicted += rowsize << rowbitsb; +- +- if (predicted != ram->size) { +- nv_warn(pfb, "memory controller reports %d MiB VRAM\n", +- (u32)(ram->size >> 20)); +- } +- +- rblock_size = rowsize; +- if (rt & 1) +- rblock_size *= 3; +- +- nv_debug(pfb, "rblock %d bytes\n", rblock_size); +- return rblock_size; +-} +- +-int +-nv50_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ +- const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ +- struct nouveau_bios *bios = nouveau_bios(parent); +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- int ret; +- +- ret = nouveau_ram_create_(parent, engine, oclass, length, pobject); +- ram = *pobject; +- if (ret) +- return ret; +- +- ram->size = nv_rd32(pfb, 0x10020c); +- ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); +- +- ram->part_mask = (nv_rd32(pfb, 0x001540) & 0x00ff0000) >> 16; +- ram->parts = hweight8(ram->part_mask); +- +- switch (nv_rd32(pfb, 0x100714) & 0x00000007) { +- case 0: ram->type = NV_MEM_TYPE_DDR1; break; +- case 1: +- if (nouveau_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3) +- ram->type = NV_MEM_TYPE_DDR3; +- else +- ram->type = NV_MEM_TYPE_DDR2; +- break; +- case 2: ram->type = NV_MEM_TYPE_GDDR3; break; +- case 3: ram->type = NV_MEM_TYPE_GDDR4; break; +- case 4: ram->type = NV_MEM_TYPE_GDDR5; break; +- default: +- break; +- } +- +- ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - +- (rsvd_head + rsvd_tail), +- nv50_fb_vram_rblock(pfb, ram) >> 12); +- if (ret) +- return ret; +- +- ram->ranks = (nv_rd32(pfb, 0x100200) & 0x4) ? 2 : 1; +- ram->tags = nv_rd32(pfb, 0x100320); +- ram->get = nv50_ram_get; +- ram->put = nv50_ram_put; +- return 0; +-} +- +-static int +-nv50_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 datasize, +- struct nouveau_object **pobject) +-{ +- struct nv50_ram *ram; +- int ret, i; +- +- ret = nv50_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_DDR2: +- case NV_MEM_TYPE_GDDR3: +- ram->base.calc = nv50_ram_calc; +- ram->base.prog = nv50_ram_prog; +- ram->base.tidy = nv50_ram_tidy; +- break; +- default: +- nv_warn(ram, "reclocking of this ram type unsupported\n"); +- return 0; +- } +- +- ram->hwsq.r_0x002504 = hwsq_reg(0x002504); +- ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); +- ram->hwsq.r_0x004008 = hwsq_reg(0x004008); +- ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); +- ram->hwsq.r_0x100210 = hwsq_reg(0x100210); +- ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); +- ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); +- ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); +- for (i = 0; i < 8; i++) +- ram->hwsq.r_0x100da0[i] = hwsq_reg(0x100da0 + (i * 0x04)); +- ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); +- ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); +- ram->hwsq.r_0x611200 = hwsq_reg(0x611200); +- +- for (i = 0; i < 9; i++) +- ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); +- +- if (ram->base.ranks > 1) { +- ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8); +- ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc); +- ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8); +- ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec); +- } else { +- ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); +- ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); +- ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); +- ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); +- } +- +- return 0; +-} +- +-struct nouveau_oclass +-nv50_ram_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_ram_ctor, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c +deleted file mode 100644 +index 3601deca..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c ++++ /dev/null +@@ -1,443 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include "ramfuc.h" +- +-#include "nv50.h" +- +-struct nva3_ramfuc { +- struct ramfuc base; +- struct ramfuc_reg r_0x004000; +- struct ramfuc_reg r_0x004004; +- struct ramfuc_reg r_0x004018; +- struct ramfuc_reg r_0x004128; +- struct ramfuc_reg r_0x004168; +- struct ramfuc_reg r_0x100200; +- struct ramfuc_reg r_0x100210; +- struct ramfuc_reg r_0x100220[9]; +- struct ramfuc_reg r_0x1002d0; +- struct ramfuc_reg r_0x1002d4; +- struct ramfuc_reg r_0x1002dc; +- struct ramfuc_reg r_0x10053c; +- struct ramfuc_reg r_0x1005a0; +- struct ramfuc_reg r_0x1005a4; +- struct ramfuc_reg r_0x100714; +- struct ramfuc_reg r_0x100718; +- struct ramfuc_reg r_0x10071c; +- struct ramfuc_reg r_0x100760; +- struct ramfuc_reg r_0x1007a0; +- struct ramfuc_reg r_0x1007e0; +- struct ramfuc_reg r_0x10f804; +- struct ramfuc_reg r_0x1110e0; +- struct ramfuc_reg r_0x111100; +- struct ramfuc_reg r_0x111104; +- struct ramfuc_reg r_0x611200; +- struct ramfuc_reg r_mr[4]; +-}; +- +-struct nva3_ram { +- struct nouveau_ram base; +- struct nva3_ramfuc fuc; +-}; +- +-static int +-nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nva3_ram *ram = (void *)pfb->ram; +- struct nva3_ramfuc *fuc = &ram->fuc; +- struct nva3_clock_info mclk; +- struct nouveau_ram_data *next; +- u8 ver, hdr, cnt, len, strap; +- u32 data; +- u32 r004018, r100760, ctrl; +- u32 unk714, unk718, unk71c; +- int ret, i; +- +- next = &ram->base.target; +- next->freq = freq; +- ram->base.next = next; +- +- /* lookup memory config data relevant to the target frequency */ +- i = 0; +- while ((data = nvbios_rammapEp(bios, i++, &ver, &hdr, &cnt, &len, +- &next->bios))) { +- if (freq / 1000 >= next->bios.rammap_min && +- freq / 1000 <= next->bios.rammap_max) +- break; +- } +- +- if (!data || ver != 0x10 || hdr < 0x0e) { +- nv_error(pfb, "invalid/missing rammap entry\n"); +- return -EINVAL; +- } +- +- /* locate specific data set for the attached memory */ +- strap = nvbios_ramcfg_index(nv_subdev(pfb)); +- if (strap >= cnt) { +- nv_error(pfb, "invalid ramcfg strap\n"); +- return -EINVAL; +- } +- +- data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap, +- &ver, &hdr, &next->bios); +- if (!data || ver != 0x10 || hdr < 0x0e) { +- nv_error(pfb, "invalid/missing ramcfg entry\n"); +- return -EINVAL; +- } +- +- /* lookup memory timings, if bios says they're present */ +- if (next->bios.ramcfg_timing != 0xff) { +- data = nvbios_timingEp(bios, next->bios.ramcfg_timing, +- &ver, &hdr, &cnt, &len, +- &next->bios); +- if (!data || ver != 0x10 || hdr < 0x19) { +- nv_error(pfb, "invalid/missing timing entry\n"); +- return -EINVAL; +- } +- } +- +- ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk); +- if (ret < 0) { +- nv_error(pfb, "failed mclk calculation\n"); +- return ret; +- } +- +- ret = ram_init(fuc, pfb); +- if (ret) +- return ret; +- +- /* XXX: where the fuck does 750MHz come from? */ +- if (freq <= 750000) { +- r004018 = 0x10000000; +- r100760 = 0x22222222; +- } else { +- r004018 = 0x00000000; +- r100760 = 0x00000000; +- } +- +- ctrl = ram_rd32(fuc, 0x004000); +- if (ctrl & 0x00000008) { +- if (mclk.pll) { +- ram_mask(fuc, 0x004128, 0x00000101, 0x00000101); +- ram_wr32(fuc, 0x004004, mclk.pll); +- ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001)); +- ram_wr32(fuc, 0x004000, (ctrl &= 0xffffffef)); +- ram_wait(fuc, 0x004000, 0x00020000, 0x00020000, 64000); +- ram_wr32(fuc, 0x004000, (ctrl |= 0x00000010)); +- ram_wr32(fuc, 0x004018, 0x00005000 | r004018); +- ram_wr32(fuc, 0x004000, (ctrl |= 0x00000004)); +- } +- } else { +- u32 ssel = 0x00000101; +- if (mclk.clk) +- ssel |= mclk.clk; +- else +- ssel |= 0x00080000; /* 324MHz, shouldn't matter... */ +- ram_mask(fuc, 0x004168, 0x003f3141, ctrl); +- } +- +- if (next->bios.ramcfg_10_02_10) { +- ram_mask(fuc, 0x111104, 0x00000600, 0x00000000); +- } else { +- ram_mask(fuc, 0x111100, 0x40000000, 0x40000000); +- ram_mask(fuc, 0x111104, 0x00000180, 0x00000000); +- } +- +- if (!next->bios.rammap_10_04_02) +- ram_mask(fuc, 0x100200, 0x00000800, 0x00000000); +- ram_wr32(fuc, 0x611200, 0x00003300); +- if (!next->bios.ramcfg_10_02_10) +- ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/ +- +- ram_wr32(fuc, 0x1002d4, 0x00000001); +- ram_wr32(fuc, 0x1002d0, 0x00000001); +- ram_wr32(fuc, 0x1002d0, 0x00000001); +- ram_wr32(fuc, 0x100210, 0x00000000); +- ram_wr32(fuc, 0x1002dc, 0x00000001); +- ram_nsec(fuc, 2000); +- +- ctrl = ram_rd32(fuc, 0x004000); +- if (!(ctrl & 0x00000008) && mclk.pll) { +- ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008)); +- ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); +- ram_wr32(fuc, 0x004018, 0x00001000); +- ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000001)); +- ram_wr32(fuc, 0x004004, mclk.pll); +- ram_wr32(fuc, 0x004000, (ctrl |= 0x00000001)); +- udelay(64); +- ram_wr32(fuc, 0x004018, 0x00005000 | r004018); +- udelay(20); +- } else +- if (!mclk.pll) { +- ram_mask(fuc, 0x004168, 0x003f3040, mclk.clk); +- ram_wr32(fuc, 0x004000, (ctrl |= 0x00000008)); +- ram_mask(fuc, 0x1110e0, 0x00088000, 0x00088000); +- ram_wr32(fuc, 0x004018, 0x0000d000 | r004018); +- } +- +- if (next->bios.rammap_10_04_08) { +- ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 | +- next->bios.ramcfg_10_05 << 8 | +- next->bios.ramcfg_10_05); +- ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 | +- next->bios.ramcfg_10_07); +- ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 | +- next->bios.ramcfg_10_03_0f << 16 | +- next->bios.ramcfg_10_09_0f | +- 0x80000000); +- ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000); +- } else { +- ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000); +- ram_mask(fuc, 0x10f804, 0x80000000, 0x00000000); +- ram_mask(fuc, 0x100760, 0x22222222, r100760); +- ram_mask(fuc, 0x1007a0, 0x22222222, r100760); +- ram_mask(fuc, 0x1007e0, 0x22222222, r100760); +- } +- +- if (mclk.pll) { +- ram_mask(fuc, 0x1110e0, 0x00088000, 0x00011000); +- ram_wr32(fuc, 0x004000, (ctrl &= ~0x00000008)); +- } +- +- /*XXX: LEAVE */ +- ram_wr32(fuc, 0x1002dc, 0x00000000); +- ram_wr32(fuc, 0x1002d4, 0x00000001); +- ram_wr32(fuc, 0x100210, 0x80000000); +- ram_nsec(fuc, 1000); +- ram_nsec(fuc, 1000); +- +- ram_mask(fuc, mr[2], 0x00000000, 0x00000000); +- ram_nsec(fuc, 1000); +- ram_nuke(fuc, mr[0]); +- ram_mask(fuc, mr[0], 0x00000000, 0x00000000); +- ram_nsec(fuc, 1000); +- +- ram_mask(fuc, 0x100220[3], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[1], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[6], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[7], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[2], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[4], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[5], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000); +- ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000); +- +- ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12); +- +- unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010; +- unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100; +- unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100; +- if (next->bios.ramcfg_10_02_20) +- unk714 |= 0xf0000000; +- if (!next->bios.ramcfg_10_02_04) +- unk714 |= 0x00000010; +- ram_wr32(fuc, 0x100714, unk714); +- +- if (next->bios.ramcfg_10_02_01) +- unk71c |= 0x00000100; +- ram_wr32(fuc, 0x10071c, unk71c); +- +- if (next->bios.ramcfg_10_02_02) +- unk718 |= 0x00000100; +- ram_wr32(fuc, 0x100718, unk718); +- +- if (next->bios.ramcfg_10_02_10) +- ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/ +- +- ram_mask(fuc, mr[0], 0x100, 0x100); +- ram_nsec(fuc, 1000); +- ram_mask(fuc, mr[0], 0x100, 0x000); +- ram_nsec(fuc, 1000); +- +- ram_nsec(fuc, 2000); +- ram_nsec(fuc, 12000); +- +- ram_wr32(fuc, 0x611200, 0x00003330); +- if (next->bios.rammap_10_04_02) +- ram_mask(fuc, 0x100200, 0x00000800, 0x00000800); +- if (next->bios.ramcfg_10_02_10) { +- ram_mask(fuc, 0x111104, 0x00000180, 0x00000180); +- ram_mask(fuc, 0x111100, 0x40000000, 0x00000000); +- } else { +- ram_mask(fuc, 0x111104, 0x00000600, 0x00000600); +- } +- +- if (mclk.pll) { +- ram_mask(fuc, 0x004168, 0x00000001, 0x00000000); +- ram_mask(fuc, 0x004168, 0x00000100, 0x00000000); +- } else { +- ram_mask(fuc, 0x004000, 0x00000001, 0x00000000); +- ram_mask(fuc, 0x004128, 0x00000001, 0x00000000); +- ram_mask(fuc, 0x004128, 0x00000100, 0x00000000); +- } +- +- return 0; +-} +- +-static int +-nva3_ram_prog(struct nouveau_fb *pfb) +-{ +- struct nouveau_device *device = nv_device(pfb); +- struct nva3_ram *ram = (void *)pfb->ram; +- struct nva3_ramfuc *fuc = &ram->fuc; +- ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); +- return 0; +-} +- +-static void +-nva3_ram_tidy(struct nouveau_fb *pfb) +-{ +- struct nva3_ram *ram = (void *)pfb->ram; +- struct nva3_ramfuc *fuc = &ram->fuc; +- ram_exec(fuc, false); +-} +- +-static int +-nva3_ram_init(struct nouveau_object *object) +-{ +- struct nouveau_fb *pfb = (void *)object->parent; +- struct nva3_ram *ram = (void *)object; +- int ret, i; +- +- ret = nouveau_ram_init(&ram->base); +- if (ret) +- return ret; +- +- /* prepare for ddr link training, and load training patterns */ +- switch (ram->base.type) { +- case NV_MEM_TYPE_DDR3: { +- if (nv_device(pfb)->chipset == 0xa8) { +- static const u32 pattern[16] = { +- 0xaaaaaaaa, 0xcccccccc, 0xdddddddd, 0xeeeeeeee, +- 0x00000000, 0x11111111, 0x44444444, 0xdddddddd, +- 0x33333333, 0x55555555, 0x77777777, 0x66666666, +- 0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb, +- }; +- +- nv_wr32(pfb, 0x100538, 0x10001ff6); /*XXX*/ +- nv_wr32(pfb, 0x1005a8, 0x0000ffff); +- nv_mask(pfb, 0x10f800, 0x00000001, 0x00000001); +- for (i = 0; i < 0x30; i++) { +- nv_wr32(pfb, 0x10f8c0, (i << 8) | i); +- nv_wr32(pfb, 0x10f8e0, (i << 8) | i); +- nv_wr32(pfb, 0x10f900, pattern[i % 16]); +- nv_wr32(pfb, 0x10f920, pattern[i % 16]); +- } +- } +- } +- break; +- default: +- break; +- } +- +- return 0; +-} +- +-static int +-nva3_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 datasize, +- struct nouveau_object **pobject) +-{ +- struct nva3_ram *ram; +- int ret, i; +- +- ret = nv50_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_DDR3: +- ram->base.calc = nva3_ram_calc; +- ram->base.prog = nva3_ram_prog; +- ram->base.tidy = nva3_ram_tidy; +- break; +- default: +- nv_warn(ram, "reclocking of this ram type unsupported\n"); +- return 0; +- } +- +- ram->fuc.r_0x004000 = ramfuc_reg(0x004000); +- ram->fuc.r_0x004004 = ramfuc_reg(0x004004); +- ram->fuc.r_0x004018 = ramfuc_reg(0x004018); +- ram->fuc.r_0x004128 = ramfuc_reg(0x004128); +- ram->fuc.r_0x004168 = ramfuc_reg(0x004168); +- ram->fuc.r_0x100200 = ramfuc_reg(0x100200); +- ram->fuc.r_0x100210 = ramfuc_reg(0x100210); +- for (i = 0; i < 9; i++) +- ram->fuc.r_0x100220[i] = ramfuc_reg(0x100220 + (i * 4)); +- ram->fuc.r_0x1002d0 = ramfuc_reg(0x1002d0); +- ram->fuc.r_0x1002d4 = ramfuc_reg(0x1002d4); +- ram->fuc.r_0x1002dc = ramfuc_reg(0x1002dc); +- ram->fuc.r_0x10053c = ramfuc_reg(0x10053c); +- ram->fuc.r_0x1005a0 = ramfuc_reg(0x1005a0); +- ram->fuc.r_0x1005a4 = ramfuc_reg(0x1005a4); +- ram->fuc.r_0x100714 = ramfuc_reg(0x100714); +- ram->fuc.r_0x100718 = ramfuc_reg(0x100718); +- ram->fuc.r_0x10071c = ramfuc_reg(0x10071c); +- ram->fuc.r_0x100760 = ramfuc_stride(0x100760, 4, ram->base.part_mask); +- ram->fuc.r_0x1007a0 = ramfuc_stride(0x1007a0, 4, ram->base.part_mask); +- ram->fuc.r_0x1007e0 = ramfuc_stride(0x1007e0, 4, ram->base.part_mask); +- ram->fuc.r_0x10f804 = ramfuc_reg(0x10f804); +- ram->fuc.r_0x1110e0 = ramfuc_stride(0x1110e0, 4, ram->base.part_mask); +- ram->fuc.r_0x111100 = ramfuc_reg(0x111100); +- ram->fuc.r_0x111104 = ramfuc_reg(0x111104); +- ram->fuc.r_0x611200 = ramfuc_reg(0x611200); +- +- if (ram->base.ranks > 1) { +- ram->fuc.r_mr[0] = ramfuc_reg2(0x1002c0, 0x1002c8); +- ram->fuc.r_mr[1] = ramfuc_reg2(0x1002c4, 0x1002cc); +- ram->fuc.r_mr[2] = ramfuc_reg2(0x1002e0, 0x1002e8); +- ram->fuc.r_mr[3] = ramfuc_reg2(0x1002e4, 0x1002ec); +- } else { +- ram->fuc.r_mr[0] = ramfuc_reg(0x1002c0); +- ram->fuc.r_mr[1] = ramfuc_reg(0x1002c4); +- ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0); +- ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4); +- } +- +- return 0; +-} +- +-struct nouveau_oclass +-nva3_ram_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva3_ram_ctor, +- .dtor = _nouveau_ram_dtor, +- .init = nva3_ram_init, +- .fini = _nouveau_ram_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c +deleted file mode 100644 +index 00f2ca7e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvaa.c ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static int +-nvaa_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 datasize, +- struct nouveau_object **pobject) +-{ +- const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ +- const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_ram *ram; +- int ret; +- +- ret = nouveau_ram_create(parent, engine, oclass, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- ram->size = nv_rd32(pfb, 0x10020c); +- ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32); +- +- ret = nouveau_mm_init(&pfb->vram, rsvd_head, (ram->size >> 12) - +- (rsvd_head + rsvd_tail), 1); +- if (ret) +- return ret; +- +- ram->type = NV_MEM_TYPE_STOLEN; +- ram->stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; +- ram->get = nv50_ram_get; +- ram->put = nv50_ram_put; +- return 0; +-} +- +-struct nouveau_oclass +-nvaa_ram_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvaa_ram_ctor, +- .dtor = _nouveau_ram_dtor, +- .init = _nouveau_ram_init, +- .fini = _nouveau_ram_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c +deleted file mode 100644 +index 735cb958..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c ++++ /dev/null +@@ -1,733 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include "ramfuc.h" +- +-#include "nvc0.h" +- +-struct nvc0_ramfuc { +- struct ramfuc base; +- +- struct ramfuc_reg r_0x10fe20; +- struct ramfuc_reg r_0x10fe24; +- struct ramfuc_reg r_0x137320; +- struct ramfuc_reg r_0x137330; +- +- struct ramfuc_reg r_0x132000; +- struct ramfuc_reg r_0x132004; +- struct ramfuc_reg r_0x132100; +- +- struct ramfuc_reg r_0x137390; +- +- struct ramfuc_reg r_0x10f290; +- struct ramfuc_reg r_0x10f294; +- struct ramfuc_reg r_0x10f298; +- struct ramfuc_reg r_0x10f29c; +- struct ramfuc_reg r_0x10f2a0; +- +- struct ramfuc_reg r_0x10f300; +- struct ramfuc_reg r_0x10f338; +- struct ramfuc_reg r_0x10f340; +- struct ramfuc_reg r_0x10f344; +- struct ramfuc_reg r_0x10f348; +- +- struct ramfuc_reg r_0x10f910; +- struct ramfuc_reg r_0x10f914; +- +- struct ramfuc_reg r_0x100b0c; +- struct ramfuc_reg r_0x10f050; +- struct ramfuc_reg r_0x10f090; +- struct ramfuc_reg r_0x10f200; +- struct ramfuc_reg r_0x10f210; +- struct ramfuc_reg r_0x10f310; +- struct ramfuc_reg r_0x10f314; +- struct ramfuc_reg r_0x10f610; +- struct ramfuc_reg r_0x10f614; +- struct ramfuc_reg r_0x10f800; +- struct ramfuc_reg r_0x10f808; +- struct ramfuc_reg r_0x10f824; +- struct ramfuc_reg r_0x10f830; +- struct ramfuc_reg r_0x10f988; +- struct ramfuc_reg r_0x10f98c; +- struct ramfuc_reg r_0x10f990; +- struct ramfuc_reg r_0x10f998; +- struct ramfuc_reg r_0x10f9b0; +- struct ramfuc_reg r_0x10f9b4; +- struct ramfuc_reg r_0x10fb04; +- struct ramfuc_reg r_0x10fb08; +- struct ramfuc_reg r_0x137300; +- struct ramfuc_reg r_0x137310; +- struct ramfuc_reg r_0x137360; +- struct ramfuc_reg r_0x1373ec; +- struct ramfuc_reg r_0x1373f0; +- struct ramfuc_reg r_0x1373f8; +- +- struct ramfuc_reg r_0x61c140; +- struct ramfuc_reg r_0x611200; +- +- struct ramfuc_reg r_0x13d8f4; +-}; +- +-struct nvc0_ram { +- struct nouveau_ram base; +- struct nvc0_ramfuc fuc; +- struct nvbios_pll refpll; +- struct nvbios_pll mempll; +-}; +- +-static void +-nvc0_ram_train(struct nvc0_ramfuc *fuc, u32 magic) +-{ +- struct nvc0_ram *ram = container_of(fuc, typeof(*ram), fuc); +- struct nouveau_fb *pfb = nouveau_fb(ram); +- u32 part = nv_rd32(pfb, 0x022438), i; +- u32 mask = nv_rd32(pfb, 0x022554); +- u32 addr = 0x110974; +- +- ram_wr32(fuc, 0x10f910, magic); +- ram_wr32(fuc, 0x10f914, magic); +- +- for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) { +- if (mask & (1 << i)) +- continue; +- ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); +- } +-} +- +-static int +-nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nouveau_clock *clk = nouveau_clock(pfb); +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nvc0_ram *ram = (void *)pfb->ram; +- struct nvc0_ramfuc *fuc = &ram->fuc; +- struct nvbios_ramcfg cfg; +- u8 ver, cnt, len, strap; +- struct { +- u32 data; +- u8 size; +- } rammap, ramcfg, timing; +- int ref, div, out; +- int from, mode; +- int N1, M1, P; +- int ret; +- +- /* lookup memory config data relevant to the target frequency */ +- rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, +- &cnt, &ramcfg.size, &cfg); +- if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { +- nv_error(pfb, "invalid/missing rammap entry\n"); +- return -EINVAL; +- } +- +- /* locate specific data set for the attached memory */ +- strap = nvbios_ramcfg_index(nv_subdev(pfb)); +- if (strap >= cnt) { +- nv_error(pfb, "invalid ramcfg strap\n"); +- return -EINVAL; +- } +- +- ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size); +- if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) { +- nv_error(pfb, "invalid/missing ramcfg entry\n"); +- return -EINVAL; +- } +- +- /* lookup memory timings, if bios says they're present */ +- strap = nv_ro08(bios, ramcfg.data + 0x01); +- if (strap != 0xff) { +- timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size, +- &cnt, &len); +- if (!timing.data || ver != 0x10 || timing.size < 0x19) { +- nv_error(pfb, "invalid/missing timing entry\n"); +- return -EINVAL; +- } +- } else { +- timing.data = 0; +- } +- +- ret = ram_init(fuc, pfb); +- if (ret) +- return ret; +- +- /* determine current mclk configuration */ +- from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */ +- +- /* determine target mclk configuration */ +- if (!(ram_rd32(fuc, 0x137300) & 0x00000100)) +- ref = clk->read(clk, nv_clk_src_sppll0); +- else +- ref = clk->read(clk, nv_clk_src_sppll1); +- div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2; +- out = (ref * 2) / (div + 2); +- mode = freq != out; +- +- ram_mask(fuc, 0x137360, 0x00000002, 0x00000000); +- +- if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) { +- ram_nuke(fuc, 0x132000); +- ram_mask(fuc, 0x132000, 0x00000002, 0x00000002); +- ram_mask(fuc, 0x132000, 0x00000002, 0x00000000); +- } +- +- if (mode == 1) { +- ram_nuke(fuc, 0x10fe20); +- ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002); +- ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000); +- } +- +-// 0x00020034 // 0x0000000a +- ram_wr32(fuc, 0x132100, 0x00000001); +- +- if (mode == 1 && from == 0) { +- /* calculate refpll */ +- ret = nva3_pll_calc(nv_subdev(pfb), &ram->refpll, +- ram->mempll.refclk, &N1, NULL, &M1, &P); +- if (ret <= 0) { +- nv_error(pfb, "unable to calc refpll\n"); +- return ret ? ret : -ERANGE; +- } +- +- ram_wr32(fuc, 0x10fe20, 0x20010000); +- ram_wr32(fuc, 0x137320, 0x00000003); +- ram_wr32(fuc, 0x137330, 0x81200006); +- ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1); +- ram_wr32(fuc, 0x10fe20, 0x20010001); +- ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); +- +- /* calculate mempll */ +- ret = nva3_pll_calc(nv_subdev(pfb), &ram->mempll, freq, +- &N1, NULL, &M1, &P); +- if (ret <= 0) { +- nv_error(pfb, "unable to calc refpll\n"); +- return ret ? ret : -ERANGE; +- } +- +- ram_wr32(fuc, 0x10fe20, 0x20010005); +- ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1); +- ram_wr32(fuc, 0x132000, 0x18010101); +- ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000); +- } else +- if (mode == 0) { +- ram_wr32(fuc, 0x137300, 0x00000003); +- } +- +- if (from == 0) { +- ram_nuke(fuc, 0x10fb04); +- ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000); +- ram_nuke(fuc, 0x10fb08); +- ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000); +- ram_wr32(fuc, 0x10f988, 0x2004ff00); +- ram_wr32(fuc, 0x10f98c, 0x003fc040); +- ram_wr32(fuc, 0x10f990, 0x20012001); +- ram_wr32(fuc, 0x10f998, 0x00011a00); +- ram_wr32(fuc, 0x13d8f4, 0x00000000); +- } else { +- ram_wr32(fuc, 0x10f988, 0x20010000); +- ram_wr32(fuc, 0x10f98c, 0x00000000); +- ram_wr32(fuc, 0x10f990, 0x20012001); +- ram_wr32(fuc, 0x10f998, 0x00010a00); +- } +- +- if (from == 0) { +-// 0x00020039 // 0x000000ba +- } +- +-// 0x0002003a // 0x00000002 +- ram_wr32(fuc, 0x100b0c, 0x00080012); +-// 0x00030014 // 0x00000000 // 0x02b5f070 +-// 0x00030014 // 0x00010000 // 0x02b5f070 +- ram_wr32(fuc, 0x611200, 0x00003300); +-// 0x00020034 // 0x0000000a +-// 0x00030020 // 0x00000001 // 0x00000000 +- +- ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); +- ram_wr32(fuc, 0x10f210, 0x00000000); +- ram_nsec(fuc, 1000); +- if (mode == 0) +- nvc0_ram_train(fuc, 0x000c1001); +- ram_wr32(fuc, 0x10f310, 0x00000001); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f090, 0x00000061); +- ram_wr32(fuc, 0x10f090, 0xc000007f); +- ram_nsec(fuc, 1000); +- +- if (from == 0) { +- ram_wr32(fuc, 0x10f824, 0x00007fd4); +- } else { +- ram_wr32(fuc, 0x1373ec, 0x00020404); +- } +- +- if (mode == 0) { +- ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); +- ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000); +- ram_wr32(fuc, 0x10f830, 0x41500010); +- ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); +- ram_mask(fuc, 0x132100, 0x00000100, 0x00000100); +- ram_wr32(fuc, 0x10f050, 0xff000090); +- ram_wr32(fuc, 0x1373ec, 0x00020f0f); +- ram_wr32(fuc, 0x1373f0, 0x00000003); +- ram_wr32(fuc, 0x137310, 0x81201616); +- ram_wr32(fuc, 0x132100, 0x00000001); +-// 0x00020039 // 0x000000ba +- ram_wr32(fuc, 0x10f830, 0x00300017); +- ram_wr32(fuc, 0x1373f0, 0x00000001); +- ram_wr32(fuc, 0x10f824, 0x00007e77); +- ram_wr32(fuc, 0x132000, 0x18030001); +- ram_wr32(fuc, 0x10f090, 0x4000007e); +- ram_nsec(fuc, 2000); +- ram_wr32(fuc, 0x10f314, 0x00000001); +- ram_wr32(fuc, 0x10f210, 0x80000000); +- ram_wr32(fuc, 0x10f338, 0x00300220); +- ram_wr32(fuc, 0x10f300, 0x0000011d); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f290, 0x02060505); +- ram_wr32(fuc, 0x10f294, 0x34208288); +- ram_wr32(fuc, 0x10f298, 0x44050411); +- ram_wr32(fuc, 0x10f29c, 0x0000114c); +- ram_wr32(fuc, 0x10f2a0, 0x42e10069); +- ram_wr32(fuc, 0x10f614, 0x40044f77); +- ram_wr32(fuc, 0x10f610, 0x40044f77); +- ram_wr32(fuc, 0x10f344, 0x00600009); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f348, 0x00700008); +- ram_wr32(fuc, 0x61c140, 0x19240000); +- ram_wr32(fuc, 0x10f830, 0x00300017); +- nvc0_ram_train(fuc, 0x80021001); +- nvc0_ram_train(fuc, 0x80081001); +- ram_wr32(fuc, 0x10f340, 0x00500004); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f830, 0x01300017); +- ram_wr32(fuc, 0x10f830, 0x00300017); +-// 0x00030020 // 0x00000000 // 0x00000000 +-// 0x00020034 // 0x0000000b +- ram_wr32(fuc, 0x100b0c, 0x00080028); +- ram_wr32(fuc, 0x611200, 0x00003330); +- } else { +- ram_wr32(fuc, 0x10f800, 0x00001800); +- ram_wr32(fuc, 0x13d8f4, 0x00000000); +- ram_wr32(fuc, 0x1373ec, 0x00020404); +- ram_wr32(fuc, 0x1373f0, 0x00000003); +- ram_wr32(fuc, 0x10f830, 0x40700010); +- ram_wr32(fuc, 0x10f830, 0x40500010); +- ram_wr32(fuc, 0x13d8f4, 0x00000000); +- ram_wr32(fuc, 0x1373f8, 0x00000000); +- ram_wr32(fuc, 0x132100, 0x00000101); +- ram_wr32(fuc, 0x137310, 0x89201616); +- ram_wr32(fuc, 0x10f050, 0xff000090); +- ram_wr32(fuc, 0x1373ec, 0x00030404); +- ram_wr32(fuc, 0x1373f0, 0x00000002); +- // 0x00020039 // 0x00000011 +- ram_wr32(fuc, 0x132100, 0x00000001); +- ram_wr32(fuc, 0x1373f8, 0x00002000); +- ram_nsec(fuc, 2000); +- ram_wr32(fuc, 0x10f808, 0x7aaa0050); +- ram_wr32(fuc, 0x10f830, 0x00500010); +- ram_wr32(fuc, 0x10f200, 0x00ce1000); +- ram_wr32(fuc, 0x10f090, 0x4000007e); +- ram_nsec(fuc, 2000); +- ram_wr32(fuc, 0x10f314, 0x00000001); +- ram_wr32(fuc, 0x10f210, 0x80000000); +- ram_wr32(fuc, 0x10f338, 0x00300200); +- ram_wr32(fuc, 0x10f300, 0x0000084d); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f290, 0x0b343825); +- ram_wr32(fuc, 0x10f294, 0x3483028e); +- ram_wr32(fuc, 0x10f298, 0x440c0600); +- ram_wr32(fuc, 0x10f29c, 0x0000214c); +- ram_wr32(fuc, 0x10f2a0, 0x42e20069); +- ram_wr32(fuc, 0x10f200, 0x00ce0000); +- ram_wr32(fuc, 0x10f614, 0x60044e77); +- ram_wr32(fuc, 0x10f610, 0x60044e77); +- ram_wr32(fuc, 0x10f340, 0x00500000); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f344, 0x00600228); +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f348, 0x00700000); +- ram_wr32(fuc, 0x13d8f4, 0x00000000); +- ram_wr32(fuc, 0x61c140, 0x09a40000); +- +- nvc0_ram_train(fuc, 0x800e1008); +- +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f800, 0x00001804); +- // 0x00030020 // 0x00000000 // 0x00000000 +- // 0x00020034 // 0x0000000b +- ram_wr32(fuc, 0x13d8f4, 0x00000000); +- ram_wr32(fuc, 0x100b0c, 0x00080028); +- ram_wr32(fuc, 0x611200, 0x00003330); +- ram_nsec(fuc, 100000); +- ram_wr32(fuc, 0x10f9b0, 0x05313f41); +- ram_wr32(fuc, 0x10f9b4, 0x00002f50); +- +- nvc0_ram_train(fuc, 0x010c1001); +- } +- +- ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800); +-// 0x00020016 // 0x00000000 +- +- if (mode == 0) +- ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); +- return 0; +-} +- +-static int +-nvc0_ram_prog(struct nouveau_fb *pfb) +-{ +- struct nouveau_device *device = nv_device(pfb); +- struct nvc0_ram *ram = (void *)pfb->ram; +- struct nvc0_ramfuc *fuc = &ram->fuc; +- ram_exec(fuc, nouveau_boolopt(device->cfgopt, "NvMemExec", true)); +- return 0; +-} +- +-static void +-nvc0_ram_tidy(struct nouveau_fb *pfb) +-{ +- struct nvc0_ram *ram = (void *)pfb->ram; +- struct nvc0_ramfuc *fuc = &ram->fuc; +- ram_exec(fuc, false); +-} +- +-extern const u8 nvc0_pte_storage_type_map[256]; +- +-void +-nvc0_ram_put(struct nouveau_fb *pfb, struct nouveau_mem **pmem) +-{ +- struct nouveau_ltc *ltc = nouveau_ltc(pfb); +- struct nouveau_mem *mem = *pmem; +- +- *pmem = NULL; +- if (unlikely(mem == NULL)) +- return; +- +- mutex_lock(&pfb->base.mutex); +- if (mem->tag) +- ltc->tags_free(ltc, &mem->tag); +- __nv50_ram_put(pfb, mem); +- mutex_unlock(&pfb->base.mutex); +- +- kfree(mem); +-} +- +-int +-nvc0_ram_get(struct nouveau_fb *pfb, u64 size, u32 align, u32 ncmin, +- u32 memtype, struct nouveau_mem **pmem) +-{ +- struct nouveau_mm *mm = &pfb->vram; +- struct nouveau_mm_node *r; +- struct nouveau_mem *mem; +- int type = (memtype & 0x0ff); +- int back = (memtype & 0x800); +- const bool comp = nvc0_pte_storage_type_map[type] != type; +- int ret; +- +- size >>= 12; +- align >>= 12; +- ncmin >>= 12; +- if (!ncmin) +- ncmin = size; +- +- mem = kzalloc(sizeof(*mem), GFP_KERNEL); +- if (!mem) +- return -ENOMEM; +- +- INIT_LIST_HEAD(&mem->regions); +- mem->size = size; +- +- mutex_lock(&pfb->base.mutex); +- if (comp) { +- struct nouveau_ltc *ltc = nouveau_ltc(pfb); +- +- /* compression only works with lpages */ +- if (align == (1 << (17 - 12))) { +- int n = size >> 5; +- ltc->tags_alloc(ltc, n, &mem->tag); +- } +- +- if (unlikely(!mem->tag)) +- type = nvc0_pte_storage_type_map[type]; +- } +- mem->memtype = type; +- +- do { +- if (back) +- ret = nouveau_mm_tail(mm, 0, 1, size, ncmin, align, &r); +- else +- ret = nouveau_mm_head(mm, 0, 1, size, ncmin, align, &r); +- if (ret) { +- mutex_unlock(&pfb->base.mutex); +- pfb->ram->put(pfb, &mem); +- return ret; +- } +- +- list_add_tail(&r->rl_entry, &mem->regions); +- size -= r->length; +- } while (size); +- mutex_unlock(&pfb->base.mutex); +- +- r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); +- mem->offset = (u64)r->offset << 12; +- *pmem = mem; +- return 0; +-} +- +-int +-nvc0_ram_create_(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u32 maskaddr, int size, +- void **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nouveau_ram *ram; +- const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ +- const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ +- u32 parts = nv_rd32(pfb, 0x022438); +- u32 pmask = nv_rd32(pfb, maskaddr); +- u32 bsize = nv_rd32(pfb, 0x10f20c); +- u32 offset, length; +- bool uniform = true; +- int ret, part; +- +- ret = nouveau_ram_create_(parent, engine, oclass, size, pobject); +- ram = *pobject; +- if (ret) +- return ret; +- +- nv_debug(pfb, "0x100800: 0x%08x\n", nv_rd32(pfb, 0x100800)); +- nv_debug(pfb, "parts 0x%08x mask 0x%08x\n", parts, pmask); +- +- ram->type = nouveau_fb_bios_memtype(bios); +- ram->ranks = (nv_rd32(pfb, 0x10f200) & 0x00000004) ? 2 : 1; +- +- /* read amount of vram attached to each memory controller */ +- for (part = 0; part < parts; part++) { +- if (!(pmask & (1 << part))) { +- u32 psize = nv_rd32(pfb, 0x11020c + (part * 0x1000)); +- if (psize != bsize) { +- if (psize < bsize) +- bsize = psize; +- uniform = false; +- } +- +- nv_debug(pfb, "%d: mem_amount 0x%08x\n", part, psize); +- ram->size += (u64)psize << 20; +- } +- } +- +- /* if all controllers have the same amount attached, there's no holes */ +- if (uniform) { +- offset = rsvd_head; +- length = (ram->size >> 12) - rsvd_head - rsvd_tail; +- ret = nouveau_mm_init(&pfb->vram, offset, length, 1); +- } else { +- /* otherwise, address lowest common amount from 0GiB */ +- ret = nouveau_mm_init(&pfb->vram, rsvd_head, +- (bsize << 8) * parts - rsvd_head, 1); +- if (ret) +- return ret; +- +- /* and the rest starting from (8GiB + common_size) */ +- offset = (0x0200000000ULL >> 12) + (bsize << 8); +- length = (ram->size >> 12) - ((bsize * parts) << 8) - rsvd_tail; +- +- ret = nouveau_mm_init(&pfb->vram, offset, length, 1); +- if (ret) +- nouveau_mm_fini(&pfb->vram); +- } +- +- if (ret) +- return ret; +- +- ram->get = nvc0_ram_get; +- ram->put = nvc0_ram_put; +- return 0; +-} +- +-static int +-nvc0_ram_init(struct nouveau_object *object) +-{ +- struct nouveau_fb *pfb = (void *)object->parent; +- struct nvc0_ram *ram = (void *)object; +- int ret, i; +- +- ret = nouveau_ram_init(&ram->base); +- if (ret) +- return ret; +- +- /* prepare for ddr link training, and load training patterns */ +- switch (ram->base.type) { +- case NV_MEM_TYPE_GDDR5: { +- static const u8 train0[] = { +- 0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc, +- 0x00, 0xff, 0xff, 0x00, 0xff, 0x00, +- }; +- static const u32 train1[] = { +- 0x00000000, 0xffffffff, +- 0x55555555, 0xaaaaaaaa, +- 0x33333333, 0xcccccccc, +- 0xf0f0f0f0, 0x0f0f0f0f, +- 0x00ff00ff, 0xff00ff00, +- 0x0000ffff, 0xffff0000, +- }; +- +- for (i = 0; i < 0x30; i++) { +- nv_wr32(pfb, 0x10f968, 0x00000000 | (i << 8)); +- nv_wr32(pfb, 0x10f96c, 0x00000000 | (i << 8)); +- nv_wr32(pfb, 0x10f920, 0x00000100 | train0[i % 12]); +- nv_wr32(pfb, 0x10f924, 0x00000100 | train0[i % 12]); +- nv_wr32(pfb, 0x10f918, train1[i % 12]); +- nv_wr32(pfb, 0x10f91c, train1[i % 12]); +- nv_wr32(pfb, 0x10f920, 0x00000000 | train0[i % 12]); +- nv_wr32(pfb, 0x10f924, 0x00000000 | train0[i % 12]); +- nv_wr32(pfb, 0x10f918, train1[i % 12]); +- nv_wr32(pfb, 0x10f91c, train1[i % 12]); +- } +- } break; +- default: +- break; +- } +- +- return 0; +-} +- +-static int +-nvc0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_bios *bios = nouveau_bios(parent); +- struct nvc0_ram *ram; +- int ret; +- +- ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll); +- if (ret) { +- nv_error(ram, "mclk refpll data not found\n"); +- return ret; +- } +- +- ret = nvbios_pll_parse(bios, 0x04, &ram->mempll); +- if (ret) { +- nv_error(ram, "mclk pll data not found\n"); +- return ret; +- } +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_GDDR5: +- ram->base.calc = nvc0_ram_calc; +- ram->base.prog = nvc0_ram_prog; +- ram->base.tidy = nvc0_ram_tidy; +- break; +- default: +- nv_warn(ram, "reclocking of this ram type unsupported\n"); +- return 0; +- } +- +- ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20); +- ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24); +- ram->fuc.r_0x137320 = ramfuc_reg(0x137320); +- ram->fuc.r_0x137330 = ramfuc_reg(0x137330); +- +- ram->fuc.r_0x132000 = ramfuc_reg(0x132000); +- ram->fuc.r_0x132004 = ramfuc_reg(0x132004); +- ram->fuc.r_0x132100 = ramfuc_reg(0x132100); +- +- ram->fuc.r_0x137390 = ramfuc_reg(0x137390); +- +- ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290); +- ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294); +- ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298); +- ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c); +- ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0); +- +- ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300); +- ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338); +- ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340); +- ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344); +- ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348); +- +- ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910); +- ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); +- +- ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c); +- ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050); +- ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090); +- ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200); +- ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210); +- ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310); +- ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314); +- ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610); +- ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614); +- ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800); +- ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808); +- ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824); +- ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830); +- ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988); +- ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c); +- ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990); +- ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998); +- ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0); +- ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4); +- ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04); +- ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08); +- ram->fuc.r_0x137310 = ramfuc_reg(0x137300); +- ram->fuc.r_0x137310 = ramfuc_reg(0x137310); +- ram->fuc.r_0x137360 = ramfuc_reg(0x137360); +- ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec); +- ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0); +- ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8); +- +- ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140); +- ram->fuc.r_0x611200 = ramfuc_reg(0x611200); +- +- ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4); +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_ram_ctor, +- .dtor = _nouveau_ram_dtor, +- .init = nvc0_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +deleted file mode 100644 +index 6bae474a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c ++++ /dev/null +@@ -1,1646 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +- +-#include +- +-#include +- +-#include "nvc0.h" +- +-#include "ramfuc.h" +- +-struct nve0_ramfuc { +- struct ramfuc base; +- +- struct nvbios_pll refpll; +- struct nvbios_pll mempll; +- +- struct ramfuc_reg r_gpioMV; +- u32 r_funcMV[2]; +- struct ramfuc_reg r_gpio2E; +- u32 r_func2E[2]; +- struct ramfuc_reg r_gpiotrig; +- +- struct ramfuc_reg r_0x132020; +- struct ramfuc_reg r_0x132028; +- struct ramfuc_reg r_0x132024; +- struct ramfuc_reg r_0x132030; +- struct ramfuc_reg r_0x132034; +- struct ramfuc_reg r_0x132000; +- struct ramfuc_reg r_0x132004; +- struct ramfuc_reg r_0x132040; +- +- struct ramfuc_reg r_0x10f248; +- struct ramfuc_reg r_0x10f290; +- struct ramfuc_reg r_0x10f294; +- struct ramfuc_reg r_0x10f298; +- struct ramfuc_reg r_0x10f29c; +- struct ramfuc_reg r_0x10f2a0; +- struct ramfuc_reg r_0x10f2a4; +- struct ramfuc_reg r_0x10f2a8; +- struct ramfuc_reg r_0x10f2ac; +- struct ramfuc_reg r_0x10f2cc; +- struct ramfuc_reg r_0x10f2e8; +- struct ramfuc_reg r_0x10f250; +- struct ramfuc_reg r_0x10f24c; +- struct ramfuc_reg r_0x10fec4; +- struct ramfuc_reg r_0x10fec8; +- struct ramfuc_reg r_0x10f604; +- struct ramfuc_reg r_0x10f614; +- struct ramfuc_reg r_0x10f610; +- struct ramfuc_reg r_0x100770; +- struct ramfuc_reg r_0x100778; +- struct ramfuc_reg r_0x10f224; +- +- struct ramfuc_reg r_0x10f870; +- struct ramfuc_reg r_0x10f698; +- struct ramfuc_reg r_0x10f694; +- struct ramfuc_reg r_0x10f6b8; +- struct ramfuc_reg r_0x10f808; +- struct ramfuc_reg r_0x10f670; +- struct ramfuc_reg r_0x10f60c; +- struct ramfuc_reg r_0x10f830; +- struct ramfuc_reg r_0x1373ec; +- struct ramfuc_reg r_0x10f800; +- struct ramfuc_reg r_0x10f82c; +- +- struct ramfuc_reg r_0x10f978; +- struct ramfuc_reg r_0x10f910; +- struct ramfuc_reg r_0x10f914; +- +- struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */ +- +- struct ramfuc_reg r_0x62c000; +- +- struct ramfuc_reg r_0x10f200; +- +- struct ramfuc_reg r_0x10f210; +- struct ramfuc_reg r_0x10f310; +- struct ramfuc_reg r_0x10f314; +- struct ramfuc_reg r_0x10f318; +- struct ramfuc_reg r_0x10f090; +- struct ramfuc_reg r_0x10f69c; +- struct ramfuc_reg r_0x10f824; +- struct ramfuc_reg r_0x1373f0; +- struct ramfuc_reg r_0x1373f4; +- struct ramfuc_reg r_0x137320; +- struct ramfuc_reg r_0x10f65c; +- struct ramfuc_reg r_0x10f6bc; +- struct ramfuc_reg r_0x100710; +- struct ramfuc_reg r_0x100750; +-}; +- +-struct nve0_ram { +- struct nouveau_ram base; +- struct nve0_ramfuc fuc; +- +- struct list_head cfg; +- u32 parts; +- u32 pmask; +- u32 pnuts; +- +- struct nvbios_ramcfg diff; +- int from; +- int mode; +- int N1, fN1, M1, P1; +- int N2, M2, P2; +-}; +- +-/******************************************************************************* +- * GDDR5 +- ******************************************************************************/ +-static void +-nve0_ram_train(struct nve0_ramfuc *fuc, u32 mask, u32 data) +-{ +- struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); +- u32 addr = 0x110974, i; +- +- ram_mask(fuc, 0x10f910, mask, data); +- ram_mask(fuc, 0x10f914, mask, data); +- +- for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) { +- if (ram->pmask & (1 << i)) +- continue; +- ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000); +- } +-} +- +-static void +-r1373f4_init(struct nve0_ramfuc *fuc) +-{ +- struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); +- const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2); +- const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); +- const u32 runk0 = ram->fN1 << 16; +- const u32 runk1 = ram->fN1; +- +- if (ram->from == 2) { +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); +- } else { +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); +- } +- +- ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); +- ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); +- +- /* (re)program refpll, if required */ +- if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || +- (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { +- ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); +- ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); +- ram_wr32(fuc, 0x137320, 0x00000000); +- ram_mask(fuc, 0x132030, 0xffff0000, runk0); +- ram_mask(fuc, 0x132034, 0x0000ffff, runk1); +- ram_wr32(fuc, 0x132024, rcoef); +- ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); +- ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); +- ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); +- ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); +- } +- +- /* (re)program mempll, if required */ +- if (ram->mode == 2) { +- ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); +- ram_mask(fuc, 0x132000, 0x80000000, 0x80000000); +- ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); +- ram_mask(fuc, 0x132004, 0x103fffff, mcoef); +- ram_mask(fuc, 0x132000, 0x00000001, 0x00000001); +- ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000); +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100); +- } else { +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100); +- } +- +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010); +-} +- +-static void +-r1373f4_fini(struct nve0_ramfuc *fuc) +-{ +- struct nve0_ram *ram = container_of(fuc, typeof(*ram), fuc); +- struct nouveau_ram_data *next = ram->base.next; +- u8 v0 = next->bios.ramcfg_11_03_c0; +- u8 v1 = next->bios.ramcfg_11_03_30; +- u32 tmp; +- +- tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000; +- ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16)); +- ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000); +- if (ram->mode == 2) { +- ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002); +- ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000); +- } else { +- ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001); +- ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000); +- } +- ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4); +-} +- +-static void +-nve0_ram_nuts(struct nve0_ram *ram, struct ramfuc_reg *reg, +- u32 _mask, u32 _data, u32 _copy) +-{ +- struct nve0_fb_priv *priv = (void *)nouveau_fb(ram); +- struct ramfuc *fuc = &ram->fuc.base; +- u32 addr = 0x110000 + (reg->addr & 0xfff); +- u32 mask = _mask | _copy; +- u32 data = (_data & _mask) | (reg->data & _copy); +- u32 i; +- +- for (i = 0; i < 16; i++, addr += 0x1000) { +- if (ram->pnuts & (1 << i)) { +- u32 prev = nv_rd32(priv, addr); +- u32 next = (prev & ~mask) | data; +- nouveau_memx_wr32(fuc->memx, addr, next); +- } +- } +-} +-#define ram_nuts(s,r,m,d,c) \ +- nve0_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c)) +- +-static int +-nve0_ram_calc_gddr5(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nve0_ramfuc *fuc = &ram->fuc; +- struct nouveau_ram_data *next = ram->base.next; +- int vc = !next->bios.ramcfg_11_02_08; +- int mv = !next->bios.ramcfg_11_02_04; +- u32 mask, data; +- +- ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); +- ram_block(fuc); +- ram_wr32(fuc, 0x62c000, 0x0f0f0000); +- +- /* MR1: turn termination on early, for some reason.. */ +- if ((ram->base.mr[1] & 0x03c) != 0x030) { +- ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c); +- ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000); +- } +- +- if (vc == 1 && ram_have(fuc, gpio2E)) { +- u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); +- if (temp != ram_rd32(fuc, gpio2E)) { +- ram_wr32(fuc, gpiotrig, 1); +- ram_nsec(fuc, 20000); +- } +- } +- +- ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); +- +- nve0_ram_train(fuc, 0x01020000, 0x000c0000); +- +- ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ +- ram_nsec(fuc, 1000); +- +- ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); +- ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ +- ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); +- ram_wr32(fuc, 0x10f090, 0x00000061); +- ram_wr32(fuc, 0x10f090, 0xc000007f); +- ram_nsec(fuc, 1000); +- +- ram_wr32(fuc, 0x10f698, 0x00000000); +- ram_wr32(fuc, 0x10f69c, 0x00000000); +- +- /*XXX: there does appear to be some kind of condition here, simply +- * modifying these bits in the vbios from the default pl0 +- * entries shows no change. however, the data does appear to +- * be correct and may be required for the transition back +- */ +- mask = 0x800f07e0; +- data = 0x00030000; +- if (ram_rd32(fuc, 0x10f978) & 0x00800000) +- data |= 0x00040000; +- +- if (1) { +- data |= 0x800807e0; +- switch (next->bios.ramcfg_11_03_c0) { +- case 3: data &= ~0x00000040; break; +- case 2: data &= ~0x00000100; break; +- case 1: data &= ~0x80000000; break; +- case 0: data &= ~0x00000400; break; +- } +- +- switch (next->bios.ramcfg_11_03_30) { +- case 3: data &= ~0x00000020; break; +- case 2: data &= ~0x00000080; break; +- case 1: data &= ~0x00080000; break; +- case 0: data &= ~0x00000200; break; +- } +- } +- +- if (next->bios.ramcfg_11_02_80) +- mask |= 0x03000000; +- if (next->bios.ramcfg_11_02_40) +- mask |= 0x00002000; +- if (next->bios.ramcfg_11_07_10) +- mask |= 0x00004000; +- if (next->bios.ramcfg_11_07_08) +- mask |= 0x00000003; +- else { +- mask |= 0x34000000; +- if (ram_rd32(fuc, 0x10f978) & 0x00800000) +- mask |= 0x40000000; +- } +- ram_mask(fuc, 0x10f824, mask, data); +- +- ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); +- +- if (ram->from == 2 && ram->mode != 2) { +- ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000); +- ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000); +- ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004); +- ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010); +- ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); +- r1373f4_init(fuc); +- ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001); +- r1373f4_fini(fuc); +- ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001); +- } else +- if (ram->from != 2 && ram->mode != 2) { +- r1373f4_init(fuc); +- r1373f4_fini(fuc); +- } +- +- if (ram_have(fuc, gpioMV)) { +- u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); +- if (temp != ram_rd32(fuc, gpioMV)) { +- ram_wr32(fuc, gpiotrig, 1); +- ram_nsec(fuc, 64000); +- } +- } +- +- if (next->bios.ramcfg_11_02_40 || +- next->bios.ramcfg_11_07_10) { +- ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); +- ram_nsec(fuc, 20000); +- } +- +- if (ram->from != 2 && ram->mode == 2) { +- if (0 /*XXX: Titan */) +- ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000); +- ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); +- ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002); +- ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010); +- r1373f4_init(fuc); +- r1373f4_fini(fuc); +- ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000); +- ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000); +- } else +- if (ram->from == 2 && ram->mode == 2) { +- ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000); +- r1373f4_init(fuc); +- r1373f4_fini(fuc); +- } +- +- if (ram->mode != 2) /*XXX*/ { +- if (next->bios.ramcfg_11_07_40) +- ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); +- } +- +- ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); +- ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); +- ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); +- +- if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) { +- ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04); +- ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04); +- } else +- if (!next->bios.ramcfg_11_07_08) { +- ram_wr32(fuc, 0x10f698, 0x00000000); +- ram_wr32(fuc, 0x10f69c, 0x00000000); +- } +- +- if (ram->mode != 2) { +- u32 data = 0x01000100 * next->bios.ramcfg_11_04; +- ram_nuke(fuc, 0x10f694); +- ram_mask(fuc, 0x10f694, 0xff00ff00, data); +- } +- +- if (ram->mode == 2 && next->bios.ramcfg_11_08_10) +- data = 0x00000080; +- else +- data = 0x00000000; +- ram_mask(fuc, 0x10f60c, 0x00000080, data); +- +- mask = 0x00070000; +- data = 0x00000000; +- if (!next->bios.ramcfg_11_02_80) +- data |= 0x03000000; +- if (!next->bios.ramcfg_11_02_40) +- data |= 0x00002000; +- if (!next->bios.ramcfg_11_07_10) +- data |= 0x00004000; +- if (!next->bios.ramcfg_11_07_08) +- data |= 0x00000003; +- else +- data |= 0x74000000; +- ram_mask(fuc, 0x10f824, mask, data); +- +- if (next->bios.ramcfg_11_01_08) +- data = 0x00000000; +- else +- data = 0x00001000; +- ram_mask(fuc, 0x10f200, 0x00001000, data); +- +- if (ram_rd32(fuc, 0x10f670) & 0x80000000) { +- ram_nsec(fuc, 10000); +- ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000); +- } +- +- if (next->bios.ramcfg_11_08_01) +- data = 0x00100000; +- else +- data = 0x00000000; +- ram_mask(fuc, 0x10f82c, 0x00100000, data); +- +- data = 0x00000000; +- if (next->bios.ramcfg_11_08_08) +- data |= 0x00002000; +- if (next->bios.ramcfg_11_08_04) +- data |= 0x00001000; +- if (next->bios.ramcfg_11_08_02) +- data |= 0x00004000; +- ram_mask(fuc, 0x10f830, 0x00007000, data); +- +- /* PFB timing */ +- ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); +- ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); +- ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); +- ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); +- ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); +- ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); +- ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); +- ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); +- ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); +- ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); +- ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); +- +- data = mask = 0x00000000; +- if (ram->diff.ramcfg_11_08_20) { +- if (next->bios.ramcfg_11_08_20) +- data |= 0x01000000; +- mask |= 0x01000000; +- } +- ram_mask(fuc, 0x10f200, mask, data); +- +- data = mask = 0x00000000; +- if (ram->diff.ramcfg_11_02_03) { +- data |= next->bios.ramcfg_11_02_03 << 8; +- mask |= 0x00000300; +- } +- if (ram->diff.ramcfg_11_01_10) { +- if (next->bios.ramcfg_11_01_10) +- data |= 0x70000000; +- mask |= 0x70000000; +- } +- ram_mask(fuc, 0x10f604, mask, data); +- +- data = mask = 0x00000000; +- if (ram->diff.timing_20_30_07) { +- data |= next->bios.timing_20_30_07 << 28; +- mask |= 0x70000000; +- } +- if (ram->diff.ramcfg_11_01_01) { +- if (next->bios.ramcfg_11_01_01) +- data |= 0x00000100; +- mask |= 0x00000100; +- } +- ram_mask(fuc, 0x10f614, mask, data); +- +- data = mask = 0x00000000; +- if (ram->diff.timing_20_30_07) { +- data |= next->bios.timing_20_30_07 << 28; +- mask |= 0x70000000; +- } +- if (ram->diff.ramcfg_11_01_02) { +- if (next->bios.ramcfg_11_01_02) +- data |= 0x00000100; +- mask |= 0x00000100; +- } +- ram_mask(fuc, 0x10f610, mask, data); +- +- mask = 0x33f00000; +- data = 0x00000000; +- if (!next->bios.ramcfg_11_01_04) +- data |= 0x20200000; +- if (!next->bios.ramcfg_11_07_80) +- data |= 0x12800000; +- /*XXX: see note above about there probably being some condition +- * for the 10f824 stuff that uses ramcfg 3... +- */ +- if (next->bios.ramcfg_11_03_f0) { +- if (next->bios.rammap_11_08_0c) { +- if (!next->bios.ramcfg_11_07_80) +- mask |= 0x00000020; +- else +- data |= 0x00000020; +- mask |= 0x00000004; +- } +- } else { +- mask |= 0x40000020; +- data |= 0x00000004; +- } +- +- ram_mask(fuc, 0x10f808, mask, data); +- +- ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); +- +- data = mask = 0x00000000; +- if (ram->diff.ramcfg_11_02_03) { +- data |= next->bios.ramcfg_11_02_03; +- mask |= 0x00000003; +- } +- if (ram->diff.ramcfg_11_01_10) { +- if (next->bios.ramcfg_11_01_10) +- data |= 0x00000004; +- mask |= 0x00000004; +- } +- +- if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) { +- ram_mask(fuc, 0x100750, 0x00000008, 0x00000008); +- ram_wr32(fuc, 0x100710, 0x00000000); +- ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000); +- } +- +- data = next->bios.timing_20_30_07 << 8; +- if (next->bios.ramcfg_11_01_01) +- data |= 0x80000000; +- ram_mask(fuc, 0x100778, 0x00000700, data); +- +- ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); +- data = (next->bios.timing[10] & 0x7f000000) >> 24; +- if (data < next->bios.timing_20_2c_1fc0) +- data = next->bios.timing_20_2c_1fc0; +- ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); +- ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); +- +- ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 | +- next->bios.timing_20_31_0780 << 17 | +- next->bios.timing_20_31_0078 << 8 | +- next->bios.timing_20_31_0007); +- ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 | +- next->bios.timing_20_31_7000); +- +- ram_wr32(fuc, 0x10f090, 0x4000007e); +- ram_nsec(fuc, 2000); +- ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ +- ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ +- ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ +- +- if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) { +- u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000); +- nve0_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/ +- ram_nsec(fuc, 1000); +- ram_wr32(fuc, 0x10f294, temp); +- } +- +- ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]); +- ram_wr32(fuc, mr[0], ram->base.mr[0]); +- ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]); +- ram_nsec(fuc, 1000); +- ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]); +- ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */ +- ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]); +- ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]); +- +- if (vc == 0 && ram_have(fuc, gpio2E)) { +- u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); +- if (temp != ram_rd32(fuc, gpio2E)) { +- ram_wr32(fuc, gpiotrig, 1); +- ram_nsec(fuc, 20000); +- } +- } +- +- ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); +- ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ +- ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); +- ram_nsec(fuc, 1000); +- ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800); +- +- data = ram_rd32(fuc, 0x10f978); +- data &= ~0x00046144; +- data |= 0x0000000b; +- if (!next->bios.ramcfg_11_07_08) { +- if (!next->bios.ramcfg_11_07_04) +- data |= 0x0000200c; +- else +- data |= 0x00000000; +- } else { +- data |= 0x00040044; +- } +- ram_wr32(fuc, 0x10f978, data); +- +- if (ram->mode == 1) { +- data = ram_rd32(fuc, 0x10f830) | 0x00000001; +- ram_wr32(fuc, 0x10f830, data); +- } +- +- if (!next->bios.ramcfg_11_07_08) { +- data = 0x88020000; +- if ( next->bios.ramcfg_11_07_04) +- data |= 0x10000000; +- if (!next->bios.rammap_11_08_10) +- data |= 0x00080000; +- } else { +- data = 0xa40e0000; +- } +- nve0_ram_train(fuc, 0xbc0f0000, data); +- if (1) /* XXX: not always? */ +- ram_nsec(fuc, 1000); +- +- if (ram->mode == 2) { /*XXX*/ +- ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004); +- } +- +- /* LP3 */ +- if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5]) +- ram_nsec(fuc, 1000); +- +- if (ram->mode != 2) { +- ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); +- ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); +- } +- +- if (next->bios.ramcfg_11_07_02) +- nve0_ram_train(fuc, 0x80020000, 0x01000000); +- +- ram_unblock(fuc); +- ram_wr32(fuc, 0x62c000, 0x0f0f0f00); +- +- if (next->bios.rammap_11_08_01) +- data = 0x00000800; +- else +- data = 0x00000000; +- ram_mask(fuc, 0x10f200, 0x00000800, data); +- ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800); +- return 0; +-} +- +-/******************************************************************************* +- * DDR3 +- ******************************************************************************/ +- +-static int +-nve0_ram_calc_sddr3(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nve0_ramfuc *fuc = &ram->fuc; +- const u32 rcoef = (( ram->P1 << 16) | (ram->N1 << 8) | ram->M1); +- const u32 runk0 = ram->fN1 << 16; +- const u32 runk1 = ram->fN1; +- struct nouveau_ram_data *next = ram->base.next; +- int vc = !next->bios.ramcfg_11_02_08; +- int mv = !next->bios.ramcfg_11_02_04; +- u32 mask, data; +- +- ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000); +- ram_block(fuc); +- ram_wr32(fuc, 0x62c000, 0x0f0f0000); +- +- if (vc == 1 && ram_have(fuc, gpio2E)) { +- u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]); +- if (temp != ram_rd32(fuc, gpio2E)) { +- ram_wr32(fuc, gpiotrig, 1); +- ram_nsec(fuc, 20000); +- } +- } +- +- ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000); +- if (next->bios.ramcfg_11_03_f0) +- ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); +- +- ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ +- ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ +- ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ +- ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); +- ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ +- ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); +- ram_nsec(fuc, 1000); +- +- ram_wr32(fuc, 0x10f090, 0x00000060); +- ram_wr32(fuc, 0x10f090, 0xc000007e); +- +- /*XXX: there does appear to be some kind of condition here, simply +- * modifying these bits in the vbios from the default pl0 +- * entries shows no change. however, the data does appear to +- * be correct and may be required for the transition back +- */ +- mask = 0x00010000; +- data = 0x00010000; +- +- if (1) { +- mask |= 0x800807e0; +- data |= 0x800807e0; +- switch (next->bios.ramcfg_11_03_c0) { +- case 3: data &= ~0x00000040; break; +- case 2: data &= ~0x00000100; break; +- case 1: data &= ~0x80000000; break; +- case 0: data &= ~0x00000400; break; +- } +- +- switch (next->bios.ramcfg_11_03_30) { +- case 3: data &= ~0x00000020; break; +- case 2: data &= ~0x00000080; break; +- case 1: data &= ~0x00080000; break; +- case 0: data &= ~0x00000200; break; +- } +- } +- +- if (next->bios.ramcfg_11_02_80) +- mask |= 0x03000000; +- if (next->bios.ramcfg_11_02_40) +- mask |= 0x00002000; +- if (next->bios.ramcfg_11_07_10) +- mask |= 0x00004000; +- if (next->bios.ramcfg_11_07_08) +- mask |= 0x00000003; +- else +- mask |= 0x14000000; +- ram_mask(fuc, 0x10f824, mask, data); +- +- ram_mask(fuc, 0x132040, 0x00010000, 0x00000000); +- +- ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010); +- data = ram_rd32(fuc, 0x1373ec) & ~0x00030000; +- data |= next->bios.ramcfg_11_03_30 << 16; +- ram_wr32(fuc, 0x1373ec, data); +- ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000); +- ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000); +- +- /* (re)program refpll, if required */ +- if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef || +- (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) { +- ram_mask(fuc, 0x132000, 0x00000001, 0x00000000); +- ram_mask(fuc, 0x132020, 0x00000001, 0x00000000); +- ram_wr32(fuc, 0x137320, 0x00000000); +- ram_mask(fuc, 0x132030, 0xffff0000, runk0); +- ram_mask(fuc, 0x132034, 0x0000ffff, runk1); +- ram_wr32(fuc, 0x132024, rcoef); +- ram_mask(fuc, 0x132028, 0x00080000, 0x00080000); +- ram_mask(fuc, 0x132020, 0x00000001, 0x00000001); +- ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000); +- ram_mask(fuc, 0x132028, 0x00080000, 0x00000000); +- } +- +- ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010); +- ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001); +- ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000); +- +- if (ram_have(fuc, gpioMV)) { +- u32 temp = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]); +- if (temp != ram_rd32(fuc, gpioMV)) { +- ram_wr32(fuc, gpiotrig, 1); +- ram_nsec(fuc, 64000); +- } +- } +- +- if (next->bios.ramcfg_11_02_40 || +- next->bios.ramcfg_11_07_10) { +- ram_mask(fuc, 0x132040, 0x00010000, 0x00010000); +- ram_nsec(fuc, 20000); +- } +- +- if (ram->mode != 2) /*XXX*/ { +- if (next->bios.ramcfg_11_07_40) +- ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000); +- } +- +- ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c); +- ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09); +- ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09); +- +- mask = 0x00010000; +- data = 0x00000000; +- if (!next->bios.ramcfg_11_02_80) +- data |= 0x03000000; +- if (!next->bios.ramcfg_11_02_40) +- data |= 0x00002000; +- if (!next->bios.ramcfg_11_07_10) +- data |= 0x00004000; +- if (!next->bios.ramcfg_11_07_08) +- data |= 0x00000003; +- else +- data |= 0x14000000; +- ram_mask(fuc, 0x10f824, mask, data); +- ram_nsec(fuc, 1000); +- +- if (next->bios.ramcfg_11_08_01) +- data = 0x00100000; +- else +- data = 0x00000000; +- ram_mask(fuc, 0x10f82c, 0x00100000, data); +- +- /* PFB timing */ +- ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]); +- ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]); +- ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]); +- ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]); +- ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]); +- ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]); +- ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]); +- ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]); +- ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]); +- ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]); +- ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]); +- +- mask = 0x33f00000; +- data = 0x00000000; +- if (!next->bios.ramcfg_11_01_04) +- data |= 0x20200000; +- if (!next->bios.ramcfg_11_07_80) +- data |= 0x12800000; +- /*XXX: see note above about there probably being some condition +- * for the 10f824 stuff that uses ramcfg 3... +- */ +- if (next->bios.ramcfg_11_03_f0) { +- if (next->bios.rammap_11_08_0c) { +- if (!next->bios.ramcfg_11_07_80) +- mask |= 0x00000020; +- else +- data |= 0x00000020; +- mask |= 0x08000004; +- } +- data |= 0x04000000; +- } else { +- mask |= 0x44000020; +- data |= 0x08000004; +- } +- +- ram_mask(fuc, 0x10f808, mask, data); +- +- ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f); +- +- ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4); +- +- data = (next->bios.timing[10] & 0x7f000000) >> 24; +- if (data < next->bios.timing_20_2c_1fc0) +- data = next->bios.timing_20_2c_1fc0; +- ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24); +- +- ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16); +- +- ram_wr32(fuc, 0x10f090, 0x4000007f); +- ram_nsec(fuc, 1000); +- +- ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ +- ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ +- ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ +- ram_nsec(fuc, 1000); +- +- ram_nuke(fuc, mr[0]); +- ram_mask(fuc, mr[0], 0x100, 0x100); +- ram_mask(fuc, mr[0], 0x100, 0x000); +- +- ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]); +- ram_wr32(fuc, mr[0], ram->base.mr[0]); +- ram_nsec(fuc, 1000); +- +- ram_nuke(fuc, mr[0]); +- ram_mask(fuc, mr[0], 0x100, 0x100); +- ram_mask(fuc, mr[0], 0x100, 0x000); +- +- if (vc == 0 && ram_have(fuc, gpio2E)) { +- u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); +- if (temp != ram_rd32(fuc, gpio2E)) { +- ram_wr32(fuc, gpiotrig, 1); +- ram_nsec(fuc, 20000); +- } +- } +- +- if (ram->mode != 2) { +- ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000); +- ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000); +- } +- +- ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); +- ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */ +- ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000); +- ram_nsec(fuc, 1000); +- +- ram_unblock(fuc); +- ram_wr32(fuc, 0x62c000, 0x0f0f0f00); +- +- if (next->bios.rammap_11_08_01) +- data = 0x00000800; +- else +- data = 0x00000000; +- ram_mask(fuc, 0x10f200, 0x00000800, data); +- return 0; +-} +- +-/******************************************************************************* +- * main hooks +- ******************************************************************************/ +- +-static int +-nve0_ram_calc_data(struct nouveau_fb *pfb, u32 khz, +- struct nouveau_ram_data *data) +-{ +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nouveau_ram_data *cfg; +- u32 mhz = khz / 1000; +- +- list_for_each_entry(cfg, &ram->cfg, head) { +- if (mhz >= cfg->bios.rammap_min && +- mhz <= cfg->bios.rammap_max) { +- *data = *cfg; +- data->freq = khz; +- return 0; +- } +- } +- +- nv_error(ram, "ramcfg data for %dMHz not found\n", mhz); +- return -EINVAL; +-} +- +-static int +-nve0_ram_calc_xits(struct nouveau_fb *pfb, struct nouveau_ram_data *next) +-{ +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nve0_ramfuc *fuc = &ram->fuc; +- int refclk, i; +- int ret; +- +- ret = ram_init(fuc, pfb); +- if (ret) +- return ret; +- +- ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1; +- ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f; +- +- /* XXX: this is *not* what nvidia do. on fermi nvidia generally +- * select, based on some unknown condition, one of the two possible +- * reference frequencies listed in the vbios table for mempll and +- * program refpll to that frequency. +- * +- * so far, i've seen very weird values being chosen by nvidia on +- * kepler boards, no idea how/why they're chosen. +- */ +- refclk = next->freq; +- if (ram->mode == 2) +- refclk = fuc->mempll.refclk; +- +- /* calculate refpll coefficients */ +- ret = nva3_pll_calc(nv_subdev(pfb), &fuc->refpll, refclk, &ram->N1, +- &ram->fN1, &ram->M1, &ram->P1); +- fuc->mempll.refclk = ret; +- if (ret <= 0) { +- nv_error(pfb, "unable to calc refpll\n"); +- return -EINVAL; +- } +- +- /* calculate mempll coefficients, if we're using it */ +- if (ram->mode == 2) { +- /* post-divider doesn't work... the reg takes the values but +- * appears to completely ignore it. there *is* a bit at +- * bit 28 that appears to divide the clock by 2 if set. +- */ +- fuc->mempll.min_p = 1; +- fuc->mempll.max_p = 2; +- +- ret = nva3_pll_calc(nv_subdev(pfb), &fuc->mempll, next->freq, +- &ram->N2, NULL, &ram->M2, &ram->P2); +- if (ret <= 0) { +- nv_error(pfb, "unable to calc mempll\n"); +- return -EINVAL; +- } +- } +- +- for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) { +- if (ram_have(fuc, mr[i])) +- ram->base.mr[i] = ram_rd32(fuc, mr[i]); +- } +- ram->base.freq = next->freq; +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_DDR3: +- ret = nouveau_sddr3_calc(&ram->base); +- if (ret == 0) +- ret = nve0_ram_calc_sddr3(pfb, next->freq); +- break; +- case NV_MEM_TYPE_GDDR5: +- ret = nouveau_gddr5_calc(&ram->base, ram->pnuts != 0); +- if (ret == 0) +- ret = nve0_ram_calc_gddr5(pfb, next->freq); +- break; +- default: +- ret = -ENOSYS; +- break; +- } +- +- return ret; +-} +- +-static int +-nve0_ram_calc(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nouveau_clock *clk = nouveau_clock(pfb); +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nouveau_ram_data *xits = &ram->base.xition; +- struct nouveau_ram_data *copy; +- int ret; +- +- if (ram->base.next == NULL) { +- ret = nve0_ram_calc_data(pfb, clk->read(clk, nv_clk_src_mem), +- &ram->base.former); +- if (ret) +- return ret; +- +- ret = nve0_ram_calc_data(pfb, freq, &ram->base.target); +- if (ret) +- return ret; +- +- if (ram->base.target.freq < ram->base.former.freq) { +- *xits = ram->base.target; +- copy = &ram->base.former; +- } else { +- *xits = ram->base.former; +- copy = &ram->base.target; +- } +- +- xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04; +- xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03; +- xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07; +- +- ram->base.next = &ram->base.target; +- if (memcmp(xits, &ram->base.former, sizeof(xits->bios))) +- ram->base.next = &ram->base.xition; +- } else { +- BUG_ON(ram->base.next != &ram->base.xition); +- ram->base.next = &ram->base.target; +- } +- +- return nve0_ram_calc_xits(pfb, ram->base.next); +-} +- +-static void +-nve0_ram_prog_0(struct nouveau_fb *pfb, u32 freq) +-{ +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nouveau_ram_data *cfg; +- u32 mhz = freq / 1000; +- u32 mask, data; +- +- list_for_each_entry(cfg, &ram->cfg, head) { +- if (mhz >= cfg->bios.rammap_min && +- mhz <= cfg->bios.rammap_max) +- break; +- } +- +- if (&cfg->head == &ram->cfg) +- return; +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) { +- data |= cfg->bios.rammap_11_0a_03fe << 12; +- mask |= 0x001ff000; +- } +- if (ram->diff.rammap_11_09_01ff) { +- data |= cfg->bios.rammap_11_09_01ff; +- mask |= 0x000001ff; +- } +- nv_mask(pfb, 0x10f468, mask, data); +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) { +- data |= cfg->bios.rammap_11_0a_0400; +- mask |= 0x00000001; +- } +- nv_mask(pfb, 0x10f420, mask, data); +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) { +- data |= cfg->bios.rammap_11_0a_0800; +- mask |= 0x00000001; +- } +- nv_mask(pfb, 0x10f430, mask, data); +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) { +- data |= cfg->bios.rammap_11_0b_01f0; +- mask |= 0x0000001f; +- } +- nv_mask(pfb, 0x10f400, mask, data); +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) { +- data |= cfg->bios.rammap_11_0b_0200 << 9; +- mask |= 0x00000200; +- } +- nv_mask(pfb, 0x10f410, mask, data); +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0d) { +- data |= cfg->bios.rammap_11_0d << 16; +- mask |= 0x00ff0000; +- } +- if (ram->diff.rammap_11_0f) { +- data |= cfg->bios.rammap_11_0f << 8; +- mask |= 0x0000ff00; +- } +- nv_mask(pfb, 0x10f440, mask, data); +- +- if (mask = 0, data = 0, ram->diff.rammap_11_0e) { +- data |= cfg->bios.rammap_11_0e << 8; +- mask |= 0x0000ff00; +- } +- if (ram->diff.rammap_11_0b_0800) { +- data |= cfg->bios.rammap_11_0b_0800 << 7; +- mask |= 0x00000080; +- } +- if (ram->diff.rammap_11_0b_0400) { +- data |= cfg->bios.rammap_11_0b_0400 << 5; +- mask |= 0x00000020; +- } +- nv_mask(pfb, 0x10f444, mask, data); +-} +- +-static int +-nve0_ram_prog(struct nouveau_fb *pfb) +-{ +- struct nouveau_device *device = nv_device(pfb); +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nve0_ramfuc *fuc = &ram->fuc; +- struct nouveau_ram_data *next = ram->base.next; +- +- if (!nouveau_boolopt(device->cfgopt, "NvMemExec", true)) { +- ram_exec(fuc, false); +- return (ram->base.next == &ram->base.xition); +- } +- +- nve0_ram_prog_0(pfb, 1000); +- ram_exec(fuc, true); +- nve0_ram_prog_0(pfb, next->freq); +- +- return (ram->base.next == &ram->base.xition); +-} +- +-static void +-nve0_ram_tidy(struct nouveau_fb *pfb) +-{ +- struct nve0_ram *ram = (void *)pfb->ram; +- struct nve0_ramfuc *fuc = &ram->fuc; +- ram->base.next = NULL; +- ram_exec(fuc, false); +-} +- +-struct nve0_ram_train { +- u16 mask; +- struct nvbios_M0209S remap; +- struct nvbios_M0209S type00; +- struct nvbios_M0209S type01; +- struct nvbios_M0209S type04; +- struct nvbios_M0209S type06; +- struct nvbios_M0209S type07; +- struct nvbios_M0209S type08; +- struct nvbios_M0209S type09; +-}; +- +-static int +-nve0_ram_train_type(struct nouveau_fb *pfb, int i, u8 ramcfg, +- struct nve0_ram_train *train) +-{ +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nvbios_M0205E M0205E; +- struct nvbios_M0205S M0205S; +- struct nvbios_M0209E M0209E; +- struct nvbios_M0209S *remap = &train->remap; +- struct nvbios_M0209S *value; +- u8 ver, hdr, cnt, len; +- u32 data; +- +- /* determine type of data for this index */ +- if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E))) +- return -ENOENT; +- +- switch (M0205E.type) { +- case 0x00: value = &train->type00; break; +- case 0x01: value = &train->type01; break; +- case 0x04: value = &train->type04; break; +- case 0x06: value = &train->type06; break; +- case 0x07: value = &train->type07; break; +- case 0x08: value = &train->type08; break; +- case 0x09: value = &train->type09; break; +- default: +- return 0; +- } +- +- /* training data index determined by ramcfg strap */ +- if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S))) +- return -EINVAL; +- i = M0205S.data; +- +- /* training data format information */ +- if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E))) +- return -EINVAL; +- +- /* ... and the raw data */ +- if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value))) +- return -EINVAL; +- +- if (M0209E.v02_07 == 2) { +- /* of course! why wouldn't we have a pointer to another entry +- * in the same table, and use the first one as an array of +- * remap indices... +- */ +- if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr, +- remap))) +- return -EINVAL; +- +- for (i = 0; i < ARRAY_SIZE(value->data); i++) +- value->data[i] = remap->data[value->data[i]]; +- } else +- if (M0209E.v02_07 != 1) +- return -EINVAL; +- +- train->mask |= 1 << M0205E.type; +- return 0; +-} +- +-static int +-nve0_ram_train_init_0(struct nouveau_fb *pfb, struct nve0_ram_train *train) +-{ +- int i, j; +- +- if ((train->mask & 0x03d3) != 0x03d3) { +- nv_warn(pfb, "missing link training data\n"); +- return -EINVAL; +- } +- +- for (i = 0; i < 0x30; i++) { +- for (j = 0; j < 8; j += 4) { +- nv_wr32(pfb, 0x10f968 + j, 0x00000000 | (i << 8)); +- nv_wr32(pfb, 0x10f920 + j, 0x00000000 | +- train->type08.data[i] << 4 | +- train->type06.data[i]); +- nv_wr32(pfb, 0x10f918 + j, train->type00.data[i]); +- nv_wr32(pfb, 0x10f920 + j, 0x00000100 | +- train->type09.data[i] << 4 | +- train->type07.data[i]); +- nv_wr32(pfb, 0x10f918 + j, train->type01.data[i]); +- } +- } +- +- for (j = 0; j < 8; j += 4) { +- for (i = 0; i < 0x100; i++) { +- nv_wr32(pfb, 0x10f968 + j, i); +- nv_wr32(pfb, 0x10f900 + j, train->type04.data[i]); +- } +- } +- +- return 0; +-} +- +-static int +-nve0_ram_train_init(struct nouveau_fb *pfb) +-{ +- u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); +- struct nve0_ram_train *train; +- int ret = -ENOMEM, i; +- +- if ((train = kzalloc(sizeof(*train), GFP_KERNEL))) { +- for (i = 0; i < 0x100; i++) { +- ret = nve0_ram_train_type(pfb, i, ramcfg, train); +- if (ret && ret != -ENOENT) +- break; +- } +- } +- +- switch (pfb->ram->type) { +- case NV_MEM_TYPE_GDDR5: +- ret = nve0_ram_train_init_0(pfb, train); +- break; +- default: +- ret = 0; +- break; +- } +- +- kfree(train); +- return ret; +-} +- +-int +-nve0_ram_init(struct nouveau_object *object) +-{ +- struct nouveau_fb *pfb = (void *)object->parent; +- struct nve0_ram *ram = (void *)object; +- struct nouveau_bios *bios = nouveau_bios(pfb); +- u8 ver, hdr, cnt, len, snr, ssz; +- u32 data, save; +- int ret, i; +- +- ret = nouveau_ram_init(&ram->base); +- if (ret) +- return ret; +- +- /* run a bunch of tables from rammap table. there's actually +- * individual pointers for each rammap entry too, but, nvidia +- * seem to just run the last two entries' scripts early on in +- * their init, and never again.. we'll just run 'em all once +- * for now. +- * +- * i strongly suspect that each script is for a separate mode +- * (likely selected by 0x10f65c's lower bits?), and the +- * binary driver skips the one that's already been setup by +- * the init tables. +- */ +- data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz); +- if (!data || hdr < 0x15) +- return -EINVAL; +- +- cnt = nv_ro08(bios, data + 0x14); /* guess at count */ +- data = nv_ro32(bios, data + 0x10); /* guess u32... */ +- save = nv_rd32(pfb, 0x10f65c) & 0x000000f0; +- for (i = 0; i < cnt; i++, data += 4) { +- if (i != save >> 4) { +- nv_mask(pfb, 0x10f65c, 0x000000f0, i << 4); +- nvbios_exec(&(struct nvbios_init) { +- .subdev = nv_subdev(pfb), +- .bios = bios, +- .offset = nv_ro32(bios, data), +- .execute = 1, +- }); +- } +- } +- nv_mask(pfb, 0x10f65c, 0x000000f0, save); +- nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); +- nv_wr32(pfb, 0x10ecc0, 0xffffffff); +- nv_mask(pfb, 0x10f160, 0x00000010, 0x00000010); +- +- return nve0_ram_train_init(pfb); +-} +- +-static int +-nve0_ram_ctor_data(struct nve0_ram *ram, u8 ramcfg, int i) +-{ +- struct nouveau_fb *pfb = (void *)nv_object(ram)->parent; +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nouveau_ram_data *cfg; +- struct nvbios_ramcfg *d = &ram->diff; +- struct nvbios_ramcfg *p, *n; +- u8 ver, hdr, cnt, len; +- u32 data; +- int ret; +- +- if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL))) +- return -ENOMEM; +- p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios; +- n = &cfg->bios; +- +- /* memory config data for a range of target frequencies */ +- data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios); +- if (ret = -ENOENT, !data) +- goto done; +- if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12) +- goto done; +- +- /* ... and a portion specific to the attached memory */ +- data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg, +- &ver, &hdr, &cfg->bios); +- if (ret = -EINVAL, !data) +- goto done; +- if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a) +- goto done; +- +- /* lookup memory timings, if bios says they're present */ +- if (cfg->bios.ramcfg_timing != 0xff) { +- data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing, +- &ver, &hdr, &cnt, &len, +- &cfg->bios); +- if (ret = -EINVAL, !data) +- goto done; +- if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33) +- goto done; +- } +- +- list_add_tail(&cfg->head, &ram->cfg); +- if (ret = 0, i == 0) +- goto done; +- +- d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe; +- d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff; +- d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400; +- d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800; +- d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0; +- d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200; +- d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d; +- d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f; +- d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e; +- d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800; +- d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400; +- d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01; +- d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02; +- d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10; +- d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03; +- d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20; +- d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07; +-done: +- if (ret) +- kfree(cfg); +- return ret; +-} +- +-static void +-nve0_ram_dtor(struct nouveau_object *object) +-{ +- struct nve0_ram *ram = (void *)object; +- struct nouveau_ram_data *cfg, *tmp; +- +- list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) { +- kfree(cfg); +- } +- +- nouveau_ram_destroy(&ram->base); +-} +- +-static int +-nve0_ram_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_bios *bios = nouveau_bios(pfb); +- struct nouveau_gpio *gpio = nouveau_gpio(pfb); +- struct dcb_gpio_func func; +- struct nve0_ram *ram; +- int ret, i; +- u8 ramcfg = nvbios_ramcfg_index(nv_subdev(pfb)); +- u32 tmp; +- +- ret = nvc0_ram_create(parent, engine, oclass, 0x022554, &ram); +- *pobject = nv_object(ram); +- if (ret) +- return ret; +- +- INIT_LIST_HEAD(&ram->cfg); +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_DDR3: +- case NV_MEM_TYPE_GDDR5: +- ram->base.calc = nve0_ram_calc; +- ram->base.prog = nve0_ram_prog; +- ram->base.tidy = nve0_ram_tidy; +- break; +- default: +- nv_warn(pfb, "reclocking of this RAM type is unsupported\n"); +- break; +- } +- +- /* calculate a mask of differently configured memory partitions, +- * because, of course reclocking wasn't complicated enough +- * already without having to treat some of them differently to +- * the others.... +- */ +- ram->parts = nv_rd32(pfb, 0x022438); +- ram->pmask = nv_rd32(pfb, 0x022554); +- ram->pnuts = 0; +- for (i = 0, tmp = 0; i < ram->parts; i++) { +- if (!(ram->pmask & (1 << i))) { +- u32 cfg1 = nv_rd32(pfb, 0x110204 + (i * 0x1000)); +- if (tmp && tmp != cfg1) { +- ram->pnuts |= (1 << i); +- continue; +- } +- tmp = cfg1; +- } +- } +- +- /* parse bios data for all rammap table entries up-front, and +- * build information on whether certain fields differ between +- * any of the entries. +- * +- * the binary driver appears to completely ignore some fields +- * when all entries contain the same value. at first, it was +- * hoped that these were mere optimisations and the bios init +- * tables had configured as per the values here, but there is +- * evidence now to suggest that this isn't the case and we do +- * need to treat this condition as a "don't touch" indicator. +- */ +- for (i = 0; !ret; i++) { +- ret = nve0_ram_ctor_data(ram, ramcfg, i); +- if (ret && ret != -ENOENT) { +- nv_error(pfb, "failed to parse ramcfg data\n"); +- return ret; +- } +- } +- +- /* parse bios data for both pll's */ +- ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll); +- if (ret) { +- nv_error(pfb, "mclk refpll data not found\n"); +- return ret; +- } +- +- ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll); +- if (ret) { +- nv_error(pfb, "mclk pll data not found\n"); +- return ret; +- } +- +- /* lookup memory voltage gpios */ +- ret = gpio->find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func); +- if (ret == 0) { +- ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04)); +- ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12; +- ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12; +- } +- +- ret = gpio->find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); +- if (ret == 0) { +- ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04)); +- ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12; +- ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12; +- } +- +- ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604); +- +- ram->fuc.r_0x132020 = ramfuc_reg(0x132020); +- ram->fuc.r_0x132028 = ramfuc_reg(0x132028); +- ram->fuc.r_0x132024 = ramfuc_reg(0x132024); +- ram->fuc.r_0x132030 = ramfuc_reg(0x132030); +- ram->fuc.r_0x132034 = ramfuc_reg(0x132034); +- ram->fuc.r_0x132000 = ramfuc_reg(0x132000); +- ram->fuc.r_0x132004 = ramfuc_reg(0x132004); +- ram->fuc.r_0x132040 = ramfuc_reg(0x132040); +- +- ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248); +- ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290); +- ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294); +- ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298); +- ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c); +- ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0); +- ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4); +- ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8); +- ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac); +- ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc); +- ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8); +- ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250); +- ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c); +- ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4); +- ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8); +- ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604); +- ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614); +- ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610); +- ram->fuc.r_0x100770 = ramfuc_reg(0x100770); +- ram->fuc.r_0x100778 = ramfuc_reg(0x100778); +- ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224); +- +- ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870); +- ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698); +- ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694); +- ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8); +- ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808); +- ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670); +- ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c); +- ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830); +- ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec); +- ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800); +- ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c); +- +- ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978); +- ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910); +- ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914); +- +- switch (ram->base.type) { +- case NV_MEM_TYPE_GDDR5: +- ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); +- ram->fuc.r_mr[1] = ramfuc_reg(0x10f330); +- ram->fuc.r_mr[2] = ramfuc_reg(0x10f334); +- ram->fuc.r_mr[3] = ramfuc_reg(0x10f338); +- ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c); +- ram->fuc.r_mr[5] = ramfuc_reg(0x10f340); +- ram->fuc.r_mr[6] = ramfuc_reg(0x10f344); +- ram->fuc.r_mr[7] = ramfuc_reg(0x10f348); +- ram->fuc.r_mr[8] = ramfuc_reg(0x10f354); +- ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c); +- break; +- case NV_MEM_TYPE_DDR3: +- ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); +- ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); +- break; +- default: +- break; +- } +- +- ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000); +- ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200); +- ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210); +- ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310); +- ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314); +- ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318); +- ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090); +- ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c); +- ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824); +- ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0); +- ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4); +- ram->fuc.r_0x137320 = ramfuc_reg(0x137320); +- ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c); +- ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc); +- ram->fuc.r_0x100710 = ramfuc_reg(0x100710); +- ram->fuc.r_0x100750 = ramfuc_reg(0x100750); +- return 0; +-} +- +-struct nouveau_oclass +-nve0_ram_oclass = { +- .handle = 0, +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_ram_ctor, +- .dtor = nve0_ram_dtor, +- .init = nve0_ram_init, +- .fini = _nouveau_ram_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h +deleted file mode 100644 +index 571077e3..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramseq.h ++++ /dev/null +@@ -1,18 +0,0 @@ +-#ifndef __NVKM_FBRAM_SEQ_H__ +-#define __NVKM_FBRAM_SEQ_H__ +- +-#include +-#include +- +-#define ram_init(s,p) hwsq_init(&(s)->base, (p)) +-#define ram_exec(s,e) hwsq_exec(&(s)->base, (e)) +-#define ram_have(s,r) ((s)->r_##r.addr != 0x000000) +-#define ram_rd32(s,r) hwsq_rd32(&(s)->base, &(s)->r_##r) +-#define ram_wr32(s,r,d) hwsq_wr32(&(s)->base, &(s)->r_##r, (d)) +-#define ram_nuke(s,r) hwsq_nuke(&(s)->base, &(s)->r_##r) +-#define ram_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) +-#define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) +-#define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) +-#define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n)) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c +deleted file mode 100644 +index bb1eb8f3..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr2.c ++++ /dev/null +@@ -1,94 +0,0 @@ +-/* +- * Copyright 2014 Roy Spliet +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Roy Spliet +- * Ben Skeggs +- */ +- +-#include "priv.h" +- +-struct ramxlat { +- int id; +- u8 enc; +-}; +- +-static inline int +-ramxlat(const struct ramxlat *xlat, int id) +-{ +- while (xlat->id >= 0) { +- if (xlat->id == id) +- return xlat->enc; +- xlat++; +- } +- return -EINVAL; +-} +- +-static const struct ramxlat +-ramddr2_cl[] = { +- { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, +- /* The following are available in some, but not all DDR2 docs */ +- { 7, 7 }, +- { -1 } +-}; +- +-static const struct ramxlat +-ramddr2_wr[] = { +- { 2, 1 }, { 3, 2 }, { 4, 3 }, { 5, 4 }, { 6, 5 }, +- /* The following are available in some, but not all DDR2 docs */ +- { 7, 6 }, +- { -1 } +-}; +- +-int +-nouveau_sddr2_calc(struct nouveau_ram *ram) +-{ +- int CL, WR, DLL = 0, ODT = 0; +- +- switch (ram->next->bios.timing_ver) { +- case 0x10: +- CL = ram->next->bios.timing_10_CL; +- WR = ram->next->bios.timing_10_WR; +- DLL = !ram->next->bios.ramcfg_10_02_40; +- ODT = ram->next->bios.timing_10_ODT & 3; +- break; +- case 0x20: +- CL = (ram->next->bios.timing[1] & 0x0000001f); +- WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; +- break; +- default: +- return -ENOSYS; +- } +- +- CL = ramxlat(ramddr2_cl, CL); +- WR = ramxlat(ramddr2_wr, WR); +- if (CL < 0 || WR < 0) +- return -EINVAL; +- +- ram->mr[0] &= ~0xf70; +- ram->mr[0] |= (WR & 0x07) << 9; +- ram->mr[0] |= (CL & 0x07) << 4; +- +- ram->mr[1] &= ~0x045; +- ram->mr[1] |= (ODT & 0x1) << 2; +- ram->mr[1] |= (ODT & 0x2) << 5; +- ram->mr[1] |= !DLL; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c +deleted file mode 100644 +index 83949b11..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fb/sddr3.c ++++ /dev/null +@@ -1,120 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Roy Spliet +- */ +- +-#include "priv.h" +- +-struct ramxlat { +- int id; +- u8 enc; +-}; +- +-static inline int +-ramxlat(const struct ramxlat *xlat, int id) +-{ +- while (xlat->id >= 0) { +- if (xlat->id == id) +- return xlat->enc; +- xlat++; +- } +- return -EINVAL; +-} +- +-static const struct ramxlat +-ramddr3_cl[] = { +- { 5, 2 }, { 6, 4 }, { 7, 6 }, { 8, 8 }, { 9, 10 }, { 10, 12 }, +- { 11, 14 }, +- /* the below are mentioned in some, but not all, ddr3 docs */ +- { 12, 1 }, { 13, 3 }, { 14, 5 }, +- { -1 } +-}; +- +-static const struct ramxlat +-ramddr3_wr[] = { +- { 5, 1 }, { 6, 2 }, { 7, 3 }, { 8, 4 }, { 10, 5 }, { 12, 6 }, +- /* the below are mentioned in some, but not all, ddr3 docs */ +- { 14, 7 }, { 16, 0 }, +- { -1 } +-}; +- +-static const struct ramxlat +-ramddr3_cwl[] = { +- { 5, 0 }, { 6, 1 }, { 7, 2 }, { 8, 3 }, +- /* the below are mentioned in some, but not all, ddr3 docs */ +- { 9, 4 }, +- { -1 } +-}; +- +-int +-nouveau_sddr3_calc(struct nouveau_ram *ram) +-{ +- int CWL, CL, WR, DLL = 0, ODT = 0; +- +- switch (ram->next->bios.timing_ver) { +- case 0x10: +- if (ram->next->bios.timing_hdr < 0x17) { +- /* XXX: NV50: Get CWL from the timing register */ +- return -ENOSYS; +- } +- CWL = ram->next->bios.timing_10_CWL; +- CL = ram->next->bios.timing_10_CL; +- WR = ram->next->bios.timing_10_WR; +- DLL = !ram->next->bios.ramcfg_10_02_40; +- ODT = ram->next->bios.timing_10_ODT; +- break; +- case 0x20: +- CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; +- CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; +- WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; +- /* XXX: Get these values from the VBIOS instead */ +- DLL = !(ram->mr[1] & 0x1); +- ODT = (ram->mr[1] & 0x004) >> 2 | +- (ram->mr[1] & 0x040) >> 5 | +- (ram->mr[1] & 0x200) >> 7; +- break; +- default: +- return -ENOSYS; +- } +- +- CWL = ramxlat(ramddr3_cwl, CWL); +- CL = ramxlat(ramddr3_cl, CL); +- WR = ramxlat(ramddr3_wr, WR); +- if (CL < 0 || CWL < 0 || WR < 0) +- return -EINVAL; +- +- ram->mr[0] &= ~0xf74; +- ram->mr[0] |= (WR & 0x07) << 9; +- ram->mr[0] |= (CL & 0x0e) << 3; +- ram->mr[0] |= (CL & 0x01) << 2; +- +- ram->mr[1] &= ~0x245; +- ram->mr[1] |= (ODT & 0x1) << 2; +- ram->mr[1] |= (ODT & 0x2) << 5; +- ram->mr[1] |= (ODT & 0x4) << 7; +- ram->mr[1] |= !DLL; +- +- ram->mr[2] &= ~0x038; +- ram->mr[2] |= (CWL & 0x07) << 3; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c +deleted file mode 100644 +index 9e8e9212..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/base.c ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +- +-int +-_nouveau_fuse_init(struct nouveau_object *object) +-{ +- struct nouveau_fuse *fuse = (void *)object; +- return nouveau_subdev_init(&fuse->base); +-} +- +-void +-_nouveau_fuse_dtor(struct nouveau_object *object) +-{ +- struct nouveau_fuse *fuse = (void *)object; +- nouveau_subdev_destroy(&fuse->base); +-} +- +-int +-nouveau_fuse_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- struct nouveau_fuse *fuse; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "FUSE", +- "fuse", length, pobject); +- fuse = *pobject; +- +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c +deleted file mode 100644 +index a374ade4..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/g80.c ++++ /dev/null +@@ -1,81 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-struct g80_fuse_priv { +- struct nouveau_fuse base; +- +- spinlock_t fuse_enable_lock; +-}; +- +-static u32 +-g80_fuse_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct g80_fuse_priv *priv = (void *)object; +- unsigned long flags; +- u32 fuse_enable, val; +- +- spin_lock_irqsave(&priv->fuse_enable_lock, flags); +- +- /* racy if another part of nouveau start writing to this reg */ +- fuse_enable = nv_mask(priv, 0x1084, 0x800, 0x800); +- val = nv_rd32(priv, 0x21000 + addr); +- nv_wr32(priv, 0x1084, fuse_enable); +- +- spin_unlock_irqrestore(&priv->fuse_enable_lock, flags); +- +- return val; +-} +- +- +-static int +-g80_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct g80_fuse_priv *priv; +- int ret; +- +- ret = nouveau_fuse_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- spin_lock_init(&priv->fuse_enable_lock); +- +- return 0; +-} +- +-struct nouveau_oclass +-g80_fuse_oclass = { +- .handle = NV_SUBDEV(FUSE, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = g80_fuse_ctor, +- .dtor = _nouveau_fuse_dtor, +- .init = _nouveau_fuse_init, +- .fini = _nouveau_fuse_fini, +- .rd32 = g80_fuse_rd32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c +deleted file mode 100644 +index 5ed03f54..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/gf100.c ++++ /dev/null +@@ -1,83 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-struct gf100_fuse_priv { +- struct nouveau_fuse base; +- +- spinlock_t fuse_enable_lock; +-}; +- +-static u32 +-gf100_fuse_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct gf100_fuse_priv *priv = (void *)object; +- unsigned long flags; +- u32 fuse_enable, unk, val; +- +- spin_lock_irqsave(&priv->fuse_enable_lock, flags); +- +- /* racy if another part of nouveau start writing to these regs */ +- fuse_enable = nv_mask(priv, 0x22400, 0x800, 0x800); +- unk = nv_mask(priv, 0x21000, 0x1, 0x1); +- val = nv_rd32(priv, 0x21100 + addr); +- nv_wr32(priv, 0x21000, unk); +- nv_wr32(priv, 0x22400, fuse_enable); +- +- spin_unlock_irqrestore(&priv->fuse_enable_lock, flags); +- +- return val; +-} +- +- +-static int +-gf100_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gf100_fuse_priv *priv; +- int ret; +- +- ret = nouveau_fuse_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- spin_lock_init(&priv->fuse_enable_lock); +- +- return 0; +-} +- +-struct nouveau_oclass +-gf100_fuse_oclass = { +- .handle = NV_SUBDEV(FUSE, 0xC0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gf100_fuse_ctor, +- .dtor = _nouveau_fuse_dtor, +- .init = _nouveau_fuse_init, +- .fini = _nouveau_fuse_fini, +- .rd32 = gf100_fuse_rd32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c +deleted file mode 100644 +index 4f1a636c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/gm107.c ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-struct gm107_fuse_priv { +- struct nouveau_fuse base; +-}; +- +-static u32 +-gm107_fuse_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct gf100_fuse_priv *priv = (void *)object; +- +- return nv_rd32(priv, 0x21100 + addr); +-} +- +- +-static int +-gm107_fuse_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gm107_fuse_priv *priv; +- int ret; +- +- ret = nouveau_fuse_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass +-gm107_fuse_oclass = { +- .handle = NV_SUBDEV(FUSE, 0x117), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gm107_fuse_ctor, +- .dtor = _nouveau_fuse_dtor, +- .init = _nouveau_fuse_init, +- .fini = _nouveau_fuse_fini, +- .rd32 = gm107_fuse_rd32, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h b/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h +deleted file mode 100644 +index d2085411..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/fuse/priv.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NVKM_FUSE_PRIV_H__ +-#define __NVKM_FUSE_PRIV_H__ +- +-#include +- +-int _nouveau_fuse_init(struct nouveau_object *object); +-void _nouveau_fuse_dtor(struct nouveau_object *object); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c +deleted file mode 100644 +index 7ad99b76..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/base.c ++++ /dev/null +@@ -1,255 +0,0 @@ +-/* +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "priv.h" +- +-static int +-nouveau_gpio_drive(struct nouveau_gpio *gpio, +- int idx, int line, int dir, int out) +-{ +- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; +- return impl->drive ? impl->drive(gpio, line, dir, out) : -ENODEV; +-} +- +-static int +-nouveau_gpio_sense(struct nouveau_gpio *gpio, int idx, int line) +-{ +- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; +- return impl->sense ? impl->sense(gpio, line) : -ENODEV; +-} +- +-static int +-nouveau_gpio_find(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, +- struct dcb_gpio_func *func) +-{ +- struct nouveau_bios *bios = nouveau_bios(gpio); +- u8 ver, len; +- u16 data; +- +- if (line == 0xff && tag == 0xff) +- return -EINVAL; +- +- data = dcb_gpio_match(bios, idx, tag, line, &ver, &len, func); +- if (data) +- return 0; +- +- /* Apple iMac G4 NV18 */ +- if (nv_device_match(nv_object(gpio), 0x0189, 0x10de, 0x0010)) { +- if (tag == DCB_GPIO_TVDAC0) { +- *func = (struct dcb_gpio_func) { +- .func = DCB_GPIO_TVDAC0, +- .line = 4, +- .log[0] = 0, +- .log[1] = 1, +- }; +- return 0; +- } +- } +- +- return -ENOENT; +-} +- +-static int +-nouveau_gpio_set(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line, int state) +-{ +- struct dcb_gpio_func func; +- int ret; +- +- ret = nouveau_gpio_find(gpio, idx, tag, line, &func); +- if (ret == 0) { +- int dir = !!(func.log[state] & 0x02); +- int out = !!(func.log[state] & 0x01); +- ret = nouveau_gpio_drive(gpio, idx, func.line, dir, out); +- } +- +- return ret; +-} +- +-static int +-nouveau_gpio_get(struct nouveau_gpio *gpio, int idx, u8 tag, u8 line) +-{ +- struct dcb_gpio_func func; +- int ret; +- +- ret = nouveau_gpio_find(gpio, idx, tag, line, &func); +- if (ret == 0) { +- ret = nouveau_gpio_sense(gpio, idx, func.line); +- if (ret >= 0) +- ret = (ret == (func.log[1] & 1)); +- } +- +- return ret; +-} +- +-static void +-nouveau_gpio_intr_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event); +- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; +- impl->intr_mask(gpio, type, 1 << index, 0); +-} +- +-static void +-nouveau_gpio_intr_init(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_gpio *gpio = container_of(event, typeof(*gpio), event); +- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; +- impl->intr_mask(gpio, type, 1 << index, 1 << index); +-} +- +-static int +-nouveau_gpio_intr_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- struct nvkm_gpio_ntfy_req *req = data; +- if (!WARN_ON(size != sizeof(*req))) { +- notify->size = sizeof(struct nvkm_gpio_ntfy_rep); +- notify->types = req->mask; +- notify->index = req->line; +- return 0; +- } +- return -EINVAL; +-} +- +-static void +-nouveau_gpio_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_gpio *gpio = nouveau_gpio(subdev); +- const struct nouveau_gpio_impl *impl = (void *)nv_object(gpio)->oclass; +- u32 hi, lo, i; +- +- impl->intr_stat(gpio, &hi, &lo); +- +- for (i = 0; (hi | lo) && i < impl->lines; i++) { +- struct nvkm_gpio_ntfy_rep rep = { +- .mask = (NVKM_GPIO_HI * !!(hi & (1 << i))) | +- (NVKM_GPIO_LO * !!(lo & (1 << i))), +- }; +- nvkm_event_send(&gpio->event, rep.mask, i, &rep, sizeof(rep)); +- } +-} +- +-static const struct nvkm_event_func +-nouveau_gpio_intr_func = { +- .ctor = nouveau_gpio_intr_ctor, +- .init = nouveau_gpio_intr_init, +- .fini = nouveau_gpio_intr_fini, +-}; +- +-int +-_nouveau_gpio_fini(struct nouveau_object *object, bool suspend) +-{ +- const struct nouveau_gpio_impl *impl = (void *)object->oclass; +- struct nouveau_gpio *gpio = nouveau_gpio(object); +- u32 mask = (1 << impl->lines) - 1; +- +- impl->intr_mask(gpio, NVKM_GPIO_TOGGLED, mask, 0); +- impl->intr_stat(gpio, &mask, &mask); +- +- return nouveau_subdev_fini(&gpio->base, suspend); +-} +- +-static struct dmi_system_id gpio_reset_ids[] = { +- { +- .ident = "Apple Macbook 10,1", +- .matches = { +- DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), +- DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro10,1"), +- } +- }, +- { } +-}; +- +-int +-_nouveau_gpio_init(struct nouveau_object *object) +-{ +- struct nouveau_gpio *gpio = nouveau_gpio(object); +- int ret; +- +- ret = nouveau_subdev_init(&gpio->base); +- if (ret) +- return ret; +- +- if (gpio->reset && dmi_check_system(gpio_reset_ids)) +- gpio->reset(gpio, DCB_GPIO_UNUSED); +- +- return ret; +-} +- +-void +-_nouveau_gpio_dtor(struct nouveau_object *object) +-{ +- struct nouveau_gpio *gpio = (void *)object; +- nvkm_event_fini(&gpio->event); +- nouveau_subdev_destroy(&gpio->base); +-} +- +-int +-nouveau_gpio_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int length, void **pobject) +-{ +- const struct nouveau_gpio_impl *impl = (void *)oclass; +- struct nouveau_gpio *gpio; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "GPIO", "gpio", +- length, pobject); +- gpio = *pobject; +- if (ret) +- return ret; +- +- gpio->find = nouveau_gpio_find; +- gpio->set = nouveau_gpio_set; +- gpio->get = nouveau_gpio_get; +- gpio->reset = impl->reset; +- +- ret = nvkm_event_init(&nouveau_gpio_intr_func, 2, impl->lines, +- &gpio->event); +- if (ret) +- return ret; +- +- nv_subdev(gpio)->intr = nouveau_gpio_intr; +- return 0; +-} +- +-int +-_nouveau_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_gpio *gpio; +- int ret; +- +- ret = nouveau_gpio_create(parent, engine, oclass, &gpio); +- *pobject = nv_object(gpio); +- if (ret) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c +deleted file mode 100644 +index 27ad23ea..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv10.c ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* +- * Copyright (C) 2009 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "priv.h" +- +-static int +-nv10_gpio_sense(struct nouveau_gpio *gpio, int line) +-{ +- if (line < 2) { +- line = line * 16; +- line = nv_rd32(gpio, 0x600818) >> line; +- return !!(line & 0x0100); +- } else +- if (line < 10) { +- line = (line - 2) * 4; +- line = nv_rd32(gpio, 0x60081c) >> line; +- return !!(line & 0x04); +- } else +- if (line < 14) { +- line = (line - 10) * 4; +- line = nv_rd32(gpio, 0x600850) >> line; +- return !!(line & 0x04); +- } +- +- return -EINVAL; +-} +- +-static int +-nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) +-{ +- u32 reg, mask, data; +- +- if (line < 2) { +- line = line * 16; +- reg = 0x600818; +- mask = 0x00000011; +- data = (dir << 4) | out; +- } else +- if (line < 10) { +- line = (line - 2) * 4; +- reg = 0x60081c; +- mask = 0x00000003; +- data = (dir << 1) | out; +- } else +- if (line < 14) { +- line = (line - 10) * 4; +- reg = 0x600850; +- mask = 0x00000003; +- data = (dir << 1) | out; +- } else { +- return -EINVAL; +- } +- +- nv_mask(gpio, reg, mask << line, data << line); +- return 0; +-} +- +-static void +-nv10_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +-{ +- u32 intr = nv_rd32(gpio, 0x001104); +- u32 stat = nv_rd32(gpio, 0x001144) & intr; +- *lo = (stat & 0xffff0000) >> 16; +- *hi = (stat & 0x0000ffff); +- nv_wr32(gpio, 0x001104, intr); +-} +- +-static void +-nv10_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +-{ +- u32 inte = nv_rd32(gpio, 0x001144); +- if (type & NVKM_GPIO_LO) +- inte = (inte & ~(mask << 16)) | (data << 16); +- if (type & NVKM_GPIO_HI) +- inte = (inte & ~mask) | data; +- nv_wr32(gpio, 0x001144, inte); +-} +- +-struct nouveau_oclass * +-nv10_gpio_oclass = &(struct nouveau_gpio_impl) { +- .base.handle = NV_SUBDEV(GPIO, 0x10), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_gpio_ctor, +- .dtor = _nouveau_gpio_dtor, +- .init = _nouveau_gpio_init, +- .fini = _nouveau_gpio_fini, +- }, +- .lines = 16, +- .intr_stat = nv10_gpio_intr_stat, +- .intr_mask = nv10_gpio_intr_mask, +- .drive = nv10_gpio_drive, +- .sense = nv10_gpio_sense, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c +deleted file mode 100644 +index 1864fa98..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv50.c ++++ /dev/null +@@ -1,129 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-void +-nv50_gpio_reset(struct nouveau_gpio *gpio, u8 match) +-{ +- struct nouveau_bios *bios = nouveau_bios(gpio); +- u8 ver, len; +- u16 entry; +- int ent = -1; +- +- while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { +- static const u32 regs[] = { 0xe100, 0xe28c }; +- u32 data = nv_ro32(bios, entry); +- u8 line = (data & 0x0000001f); +- u8 func = (data & 0x0000ff00) >> 8; +- u8 defs = !!(data & 0x01000000); +- u8 unk0 = !!(data & 0x02000000); +- u8 unk1 = !!(data & 0x04000000); +- u32 val = (unk1 << 16) | unk0; +- u32 reg = regs[line >> 4]; +- u32 lsh = line & 0x0f; +- +- if ( func == DCB_GPIO_UNUSED || +- (match != DCB_GPIO_UNUSED && match != func)) +- continue; +- +- gpio->set(gpio, 0, func, line, defs); +- +- nv_mask(gpio, reg, 0x00010001 << lsh, val << lsh); +- } +-} +- +-static int +-nv50_gpio_location(int line, u32 *reg, u32 *shift) +-{ +- const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; +- +- if (line >= 32) +- return -EINVAL; +- +- *reg = nv50_gpio_reg[line >> 3]; +- *shift = (line & 7) << 2; +- return 0; +-} +- +-int +-nv50_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) +-{ +- u32 reg, shift; +- +- if (nv50_gpio_location(line, ®, &shift)) +- return -EINVAL; +- +- nv_mask(gpio, reg, 3 << shift, (((dir ^ 1) << 1) | out) << shift); +- return 0; +-} +- +-int +-nv50_gpio_sense(struct nouveau_gpio *gpio, int line) +-{ +- u32 reg, shift; +- +- if (nv50_gpio_location(line, ®, &shift)) +- return -EINVAL; +- +- return !!(nv_rd32(gpio, reg) & (4 << shift)); +-} +- +-static void +-nv50_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +-{ +- u32 intr = nv_rd32(gpio, 0x00e054); +- u32 stat = nv_rd32(gpio, 0x00e050) & intr; +- *lo = (stat & 0xffff0000) >> 16; +- *hi = (stat & 0x0000ffff); +- nv_wr32(gpio, 0x00e054, intr); +-} +- +-static void +-nv50_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +-{ +- u32 inte = nv_rd32(gpio, 0x00e050); +- if (type & NVKM_GPIO_LO) +- inte = (inte & ~(mask << 16)) | (data << 16); +- if (type & NVKM_GPIO_HI) +- inte = (inte & ~mask) | data; +- nv_wr32(gpio, 0x00e050, inte); +-} +- +-struct nouveau_oclass * +-nv50_gpio_oclass = &(struct nouveau_gpio_impl) { +- .base.handle = NV_SUBDEV(GPIO, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_gpio_ctor, +- .dtor = _nouveau_gpio_dtor, +- .init = _nouveau_gpio_init, +- .fini = _nouveau_gpio_fini, +- }, +- .lines = 16, +- .intr_stat = nv50_gpio_intr_stat, +- .intr_mask = nv50_gpio_intr_mask, +- .drive = nv50_gpio_drive, +- .sense = nv50_gpio_sense, +- .reset = nv50_gpio_reset, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c +deleted file mode 100644 +index cae404cc..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nv94.c ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-void +-nv94_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +-{ +- u32 intr0 = nv_rd32(gpio, 0x00e054); +- u32 intr1 = nv_rd32(gpio, 0x00e074); +- u32 stat0 = nv_rd32(gpio, 0x00e050) & intr0; +- u32 stat1 = nv_rd32(gpio, 0x00e070) & intr1; +- *lo = (stat1 & 0xffff0000) | (stat0 >> 16); +- *hi = (stat1 << 16) | (stat0 & 0x0000ffff); +- nv_wr32(gpio, 0x00e054, intr0); +- nv_wr32(gpio, 0x00e074, intr1); +-} +- +-void +-nv94_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +-{ +- u32 inte0 = nv_rd32(gpio, 0x00e050); +- u32 inte1 = nv_rd32(gpio, 0x00e070); +- if (type & NVKM_GPIO_LO) +- inte0 = (inte0 & ~(mask << 16)) | (data << 16); +- if (type & NVKM_GPIO_HI) +- inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); +- mask >>= 16; +- data >>= 16; +- if (type & NVKM_GPIO_LO) +- inte1 = (inte1 & ~(mask << 16)) | (data << 16); +- if (type & NVKM_GPIO_HI) +- inte1 = (inte1 & ~mask) | data; +- nv_wr32(gpio, 0x00e050, inte0); +- nv_wr32(gpio, 0x00e070, inte1); +-} +- +-struct nouveau_oclass * +-nv94_gpio_oclass = &(struct nouveau_gpio_impl) { +- .base.handle = NV_SUBDEV(GPIO, 0x94), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_gpio_ctor, +- .dtor = _nouveau_gpio_dtor, +- .init = _nouveau_gpio_init, +- .fini = _nouveau_gpio_fini, +- }, +- .lines = 32, +- .intr_stat = nv94_gpio_intr_stat, +- .intr_mask = nv94_gpio_intr_mask, +- .drive = nv50_gpio_drive, +- .sense = nv50_gpio_sense, +- .reset = nv50_gpio_reset, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c +deleted file mode 100644 +index 480d6d2a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nvd0.c ++++ /dev/null +@@ -1,85 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-void +-nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match) +-{ +- struct nouveau_bios *bios = nouveau_bios(gpio); +- u8 ver, len; +- u16 entry; +- int ent = -1; +- +- while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) { +- u32 data = nv_ro32(bios, entry); +- u8 line = (data & 0x0000003f); +- u8 defs = !!(data & 0x00000080); +- u8 func = (data & 0x0000ff00) >> 8; +- u8 unk0 = (data & 0x00ff0000) >> 16; +- u8 unk1 = (data & 0x1f000000) >> 24; +- +- if ( func == DCB_GPIO_UNUSED || +- (match != DCB_GPIO_UNUSED && match != func)) +- continue; +- +- gpio->set(gpio, 0, func, line, defs); +- +- nv_mask(gpio, 0x00d610 + (line * 4), 0xff, unk0); +- if (unk1--) +- nv_mask(gpio, 0x00d740 + (unk1 * 4), 0xff, line); +- } +-} +- +-int +-nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) +-{ +- u32 data = ((dir ^ 1) << 13) | (out << 12); +- nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data); +- nv_mask(gpio, 0x00d604, 0x00000001, 0x00000001); /* update? */ +- return 0; +-} +- +-int +-nvd0_gpio_sense(struct nouveau_gpio *gpio, int line) +-{ +- return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000); +-} +- +-struct nouveau_oclass * +-nvd0_gpio_oclass = &(struct nouveau_gpio_impl) { +- .base.handle = NV_SUBDEV(GPIO, 0xd0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_gpio_ctor, +- .dtor = _nouveau_gpio_dtor, +- .init = _nouveau_gpio_init, +- .fini = _nouveau_gpio_fini, +- }, +- .lines = 32, +- .intr_stat = nv94_gpio_intr_stat, +- .intr_mask = nv94_gpio_intr_mask, +- .drive = nvd0_gpio_drive, +- .sense = nvd0_gpio_sense, +- .reset = nvd0_gpio_reset, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c +deleted file mode 100644 +index e1145b48..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/nve0.c ++++ /dev/null +@@ -1,74 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static void +-nve0_gpio_intr_stat(struct nouveau_gpio *gpio, u32 *hi, u32 *lo) +-{ +- u32 intr0 = nv_rd32(gpio, 0x00dc00); +- u32 intr1 = nv_rd32(gpio, 0x00dc80); +- u32 stat0 = nv_rd32(gpio, 0x00dc08) & intr0; +- u32 stat1 = nv_rd32(gpio, 0x00dc88) & intr1; +- *lo = (stat1 & 0xffff0000) | (stat0 >> 16); +- *hi = (stat1 << 16) | (stat0 & 0x0000ffff); +- nv_wr32(gpio, 0x00dc00, intr0); +- nv_wr32(gpio, 0x00dc80, intr1); +-} +- +-void +-nve0_gpio_intr_mask(struct nouveau_gpio *gpio, u32 type, u32 mask, u32 data) +-{ +- u32 inte0 = nv_rd32(gpio, 0x00dc08); +- u32 inte1 = nv_rd32(gpio, 0x00dc88); +- if (type & NVKM_GPIO_LO) +- inte0 = (inte0 & ~(mask << 16)) | (data << 16); +- if (type & NVKM_GPIO_HI) +- inte0 = (inte0 & ~(mask & 0xffff)) | (data & 0xffff); +- mask >>= 16; +- data >>= 16; +- if (type & NVKM_GPIO_LO) +- inte1 = (inte1 & ~(mask << 16)) | (data << 16); +- if (type & NVKM_GPIO_HI) +- inte1 = (inte1 & ~mask) | data; +- nv_wr32(gpio, 0x00dc08, inte0); +- nv_wr32(gpio, 0x00dc88, inte1); +-} +- +-struct nouveau_oclass * +-nve0_gpio_oclass = &(struct nouveau_gpio_impl) { +- .base.handle = NV_SUBDEV(GPIO, 0xe0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_gpio_ctor, +- .dtor = _nouveau_gpio_dtor, +- .init = _nouveau_gpio_init, +- .fini = _nouveau_gpio_fini, +- }, +- .lines = 32, +- .intr_stat = nve0_gpio_intr_stat, +- .intr_mask = nve0_gpio_intr_mask, +- .drive = nvd0_gpio_drive, +- .sense = nvd0_gpio_sense, +- .reset = nvd0_gpio_reset, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h b/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h +deleted file mode 100644 +index bff98b86..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/gpio/priv.h ++++ /dev/null +@@ -1,67 +0,0 @@ +-#ifndef __NVKM_GPIO_H__ +-#define __NVKM_GPIO_H__ +- +-#include +- +-#define nouveau_gpio_create(p,e,o,d) \ +- nouveau_gpio_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_gpio_destroy(p) ({ \ +- struct nouveau_gpio *gpio = (p); \ +- _nouveau_gpio_dtor(nv_object(gpio)); \ +-}) +-#define nouveau_gpio_init(p) ({ \ +- struct nouveau_gpio *gpio = (p); \ +- _nouveau_gpio_init(nv_object(gpio)); \ +-}) +-#define nouveau_gpio_fini(p,s) ({ \ +- struct nouveau_gpio *gpio = (p); \ +- _nouveau_gpio_fini(nv_object(gpio), (s)); \ +-}) +- +-int nouveau_gpio_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-int _nouveau_gpio_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void _nouveau_gpio_dtor(struct nouveau_object *); +-int _nouveau_gpio_init(struct nouveau_object *); +-int _nouveau_gpio_fini(struct nouveau_object *, bool); +- +-struct nouveau_gpio_impl { +- struct nouveau_oclass base; +- int lines; +- +- /* read and ack pending interrupts, returning only data +- * for lines that have not been masked off, while still +- * performing the ack for anything that was pending. +- */ +- void (*intr_stat)(struct nouveau_gpio *, u32 *, u32 *); +- +- /* mask on/off interrupts for hi/lo transitions on a +- * given set of gpio lines +- */ +- void (*intr_mask)(struct nouveau_gpio *, u32, u32, u32); +- +- /* configure gpio direction and output value */ +- int (*drive)(struct nouveau_gpio *, int line, int dir, int out); +- +- /* sense current state of given gpio line */ +- int (*sense)(struct nouveau_gpio *, int line); +- +- /*XXX*/ +- void (*reset)(struct nouveau_gpio *, u8); +-}; +- +-void nv50_gpio_reset(struct nouveau_gpio *, u8); +-int nv50_gpio_drive(struct nouveau_gpio *, int, int, int); +-int nv50_gpio_sense(struct nouveau_gpio *, int); +- +-void nv94_gpio_intr_stat(struct nouveau_gpio *, u32 *, u32 *); +-void nv94_gpio_intr_mask(struct nouveau_gpio *, u32, u32, u32); +- +-void nvd0_gpio_reset(struct nouveau_gpio *, u8); +-int nvd0_gpio_drive(struct nouveau_gpio *, int, int, int); +-int nvd0_gpio_sense(struct nouveau_gpio *, int); +- +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c +deleted file mode 100644 +index 2c2731a6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/anx9805.c ++++ /dev/null +@@ -1,292 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "port.h" +- +-struct anx9805_i2c_port { +- struct nouveau_i2c_port base; +- u32 addr; +- u32 ctrl; +-}; +- +-static int +-anx9805_train(struct nouveau_i2c_port *port, int link_nr, int link_bw, bool enh) +-{ +- struct anx9805_i2c_port *chan = (void *)port; +- struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; +- u8 tmp, i; +- +- DBG("ANX9805 train %d 0x%02x %d\n", link_nr, link_bw, enh); +- +- nv_wri2cr(mast, chan->addr, 0xa0, link_bw); +- nv_wri2cr(mast, chan->addr, 0xa1, link_nr | (enh ? 0x80 : 0x00)); +- nv_wri2cr(mast, chan->addr, 0xa2, 0x01); +- nv_wri2cr(mast, chan->addr, 0xa8, 0x01); +- +- i = 0; +- while ((tmp = nv_rdi2cr(mast, chan->addr, 0xa8)) & 0x01) { +- mdelay(5); +- if (i++ == 100) { +- nv_error(port, "link training timed out\n"); +- return -ETIMEDOUT; +- } +- } +- +- if (tmp & 0x70) { +- nv_error(port, "link training failed: 0x%02x\n", tmp); +- return -EIO; +- } +- +- return 1; +-} +- +-static int +-anx9805_aux(struct nouveau_i2c_port *port, bool retry, +- u8 type, u32 addr, u8 *data, u8 size) +-{ +- struct anx9805_i2c_port *chan = (void *)port; +- struct nouveau_i2c_port *mast = (void *)nv_object(chan)->parent; +- int i, ret = -ETIMEDOUT; +- u8 buf[16] = {}; +- u8 tmp; +- +- DBG("%02x %05x %d\n", type, addr, size); +- +- tmp = nv_rdi2cr(mast, chan->ctrl, 0x07) & ~0x04; +- nv_wri2cr(mast, chan->ctrl, 0x07, tmp | 0x04); +- nv_wri2cr(mast, chan->ctrl, 0x07, tmp); +- nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01); +- +- nv_wri2cr(mast, chan->addr, 0xe4, 0x80); +- if (!(type & 1)) { +- memcpy(buf, data, size); +- DBG("%16ph", buf); +- for (i = 0; i < size; i++) +- nv_wri2cr(mast, chan->addr, 0xf0 + i, buf[i]); +- } +- nv_wri2cr(mast, chan->addr, 0xe5, ((size - 1) << 4) | type); +- nv_wri2cr(mast, chan->addr, 0xe6, (addr & 0x000ff) >> 0); +- nv_wri2cr(mast, chan->addr, 0xe7, (addr & 0x0ff00) >> 8); +- nv_wri2cr(mast, chan->addr, 0xe8, (addr & 0xf0000) >> 16); +- nv_wri2cr(mast, chan->addr, 0xe9, 0x01); +- +- i = 0; +- while ((tmp = nv_rdi2cr(mast, chan->addr, 0xe9)) & 0x01) { +- mdelay(5); +- if (i++ == 32) +- goto done; +- } +- +- if ((tmp = nv_rdi2cr(mast, chan->ctrl, 0xf7)) & 0x01) { +- ret = -EIO; +- goto done; +- } +- +- if (type & 1) { +- for (i = 0; i < size; i++) +- buf[i] = nv_rdi2cr(mast, chan->addr, 0xf0 + i); +- DBG("%16ph", buf); +- memcpy(data, buf, size); +- } +- +- ret = 0; +-done: +- nv_wri2cr(mast, chan->ctrl, 0xf7, 0x01); +- return ret; +-} +- +-static const struct nouveau_i2c_func +-anx9805_aux_func = { +- .aux = anx9805_aux, +- .lnk_ctl = anx9805_train, +-}; +- +-static int +-anx9805_aux_chan_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nouveau_i2c_port *mast = (void *)parent; +- struct anx9805_i2c_port *chan; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_aux_algo, &anx9805_aux_func, +- &chan); +- *pobject = nv_object(chan); +- if (ret) +- return ret; +- +- switch ((oclass->handle & 0xff00) >> 8) { +- case 0x0d: +- chan->addr = 0x38; +- chan->ctrl = 0x39; +- break; +- case 0x0e: +- chan->addr = 0x3c; +- chan->ctrl = 0x3b; +- break; +- default: +- BUG_ON(1); +- } +- +- if (mast->adapter.algo == &i2c_bit_algo) { +- struct i2c_algo_bit_data *algo = mast->adapter.algo_data; +- algo->udelay = max(algo->udelay, 40); +- } +- return 0; +-} +- +-static struct nouveau_ofuncs +-anx9805_aux_ofuncs = { +- .ctor = anx9805_aux_chan_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = _nouveau_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +-}; +- +-static int +-anx9805_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +-{ +- struct anx9805_i2c_port *port = adap->algo_data; +- struct nouveau_i2c_port *mast = (void *)nv_object(port)->parent; +- struct i2c_msg *msg = msgs; +- int ret = -ETIMEDOUT; +- int i, j, cnt = num; +- u8 seg = 0x00, off = 0x00, tmp; +- +- tmp = nv_rdi2cr(mast, port->ctrl, 0x07) & ~0x10; +- nv_wri2cr(mast, port->ctrl, 0x07, tmp | 0x10); +- nv_wri2cr(mast, port->ctrl, 0x07, tmp); +- nv_wri2cr(mast, port->addr, 0x43, 0x05); +- mdelay(5); +- +- while (cnt--) { +- if ( (msg->flags & I2C_M_RD) && msg->addr == 0x50) { +- nv_wri2cr(mast, port->addr, 0x40, msg->addr << 1); +- nv_wri2cr(mast, port->addr, 0x41, seg); +- nv_wri2cr(mast, port->addr, 0x42, off); +- nv_wri2cr(mast, port->addr, 0x44, msg->len); +- nv_wri2cr(mast, port->addr, 0x45, 0x00); +- nv_wri2cr(mast, port->addr, 0x43, 0x01); +- for (i = 0; i < msg->len; i++) { +- j = 0; +- while (nv_rdi2cr(mast, port->addr, 0x46) & 0x10) { +- mdelay(5); +- if (j++ == 32) +- goto done; +- } +- msg->buf[i] = nv_rdi2cr(mast, port->addr, 0x47); +- } +- } else +- if (!(msg->flags & I2C_M_RD)) { +- if (msg->addr == 0x50 && msg->len == 0x01) { +- off = msg->buf[0]; +- } else +- if (msg->addr == 0x30 && msg->len == 0x01) { +- seg = msg->buf[0]; +- } else +- goto done; +- } else { +- goto done; +- } +- msg++; +- } +- +- ret = num; +-done: +- nv_wri2cr(mast, port->addr, 0x43, 0x00); +- return ret; +-} +- +-static u32 +-anx9805_func(struct i2c_adapter *adap) +-{ +- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +-} +- +-static const struct i2c_algorithm +-anx9805_i2c_algo = { +- .master_xfer = anx9805_xfer, +- .functionality = anx9805_func +-}; +- +-static const struct nouveau_i2c_func +-anx9805_i2c_func = { +-}; +- +-static int +-anx9805_ddc_port_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nouveau_i2c_port *mast = (void *)parent; +- struct anx9805_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &anx9805_i2c_algo, &anx9805_i2c_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- switch ((oclass->handle & 0xff00) >> 8) { +- case 0x0d: +- port->addr = 0x3d; +- port->ctrl = 0x39; +- break; +- case 0x0e: +- port->addr = 0x3f; +- port->ctrl = 0x3b; +- break; +- default: +- BUG_ON(1); +- } +- +- if (mast->adapter.algo == &i2c_bit_algo) { +- struct i2c_algo_bit_data *algo = mast->adapter.algo_data; +- algo->udelay = max(algo->udelay, 40); +- } +- return 0; +-} +- +-static struct nouveau_ofuncs +-anx9805_ddc_ofuncs = { +- .ctor = anx9805_ddc_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = _nouveau_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +-}; +- +-struct nouveau_oclass +-nouveau_anx9805_sclass[] = { +- { .handle = NV_I2C_TYPE_EXTDDC(0x0d), .ofuncs = &anx9805_ddc_ofuncs }, +- { .handle = NV_I2C_TYPE_EXTAUX(0x0d), .ofuncs = &anx9805_aux_ofuncs }, +- { .handle = NV_I2C_TYPE_EXTDDC(0x0e), .ofuncs = &anx9805_ddc_ofuncs }, +- { .handle = NV_I2C_TYPE_EXTAUX(0x0e), .ofuncs = &anx9805_aux_ofuncs }, +- {} +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c +deleted file mode 100644 +index 02eb42be..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/aux.c ++++ /dev/null +@@ -1,114 +0,0 @@ +-/* +- * Copyright 2009 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-int +-nv_rdaux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size) +-{ +- struct nouveau_i2c *i2c = nouveau_i2c(port); +- if (port->func->aux) { +- int ret = i2c->acquire(port, 0); +- if (ret == 0) { +- ret = port->func->aux(port, true, 9, addr, data, size); +- i2c->release(port); +- } +- return ret; +- } +- return -ENODEV; +-} +- +-int +-nv_wraux(struct nouveau_i2c_port *port, u32 addr, u8 *data, u8 size) +-{ +- struct nouveau_i2c *i2c = nouveau_i2c(port); +- if (port->func->aux) { +- int ret = i2c->acquire(port, 0); +- if (ret == 0) { +- ret = port->func->aux(port, true, 8, addr, data, size); +- i2c->release(port); +- } +- return ret; +- } +- return -ENODEV; +-} +- +-static int +-aux_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +-{ +- struct nouveau_i2c_port *port = adap->algo_data; +- struct nouveau_i2c *i2c = nouveau_i2c(port); +- struct i2c_msg *msg = msgs; +- int ret, mcnt = num; +- +- if (!port->func->aux) +- return -ENODEV; +- +- ret = i2c->acquire(port, 0); +- if (ret) +- return ret; +- +- while (mcnt--) { +- u8 remaining = msg->len; +- u8 *ptr = msg->buf; +- +- while (remaining) { +- u8 cnt = (remaining > 16) ? 16 : remaining; +- u8 cmd; +- +- if (msg->flags & I2C_M_RD) +- cmd = 1; +- else +- cmd = 0; +- +- if (mcnt || remaining > 16) +- cmd |= 4; /* MOT */ +- +- ret = port->func->aux(port, true, cmd, msg->addr, ptr, cnt); +- if (ret < 0) { +- i2c->release(port); +- return ret; +- } +- +- ptr += cnt; +- remaining -= cnt; +- } +- +- msg++; +- } +- +- i2c->release(port); +- return num; +-} +- +-static u32 +-aux_func(struct i2c_adapter *adap) +-{ +- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +-} +- +-const struct i2c_algorithm nouveau_i2c_aux_algo = { +- .master_xfer = aux_xfer, +- .functionality = aux_func +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c +deleted file mode 100644 +index 2b1bf545..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/base.c ++++ /dev/null +@@ -1,599 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-#include "priv.h" +-#include "pad.h" +- +-/****************************************************************************** +- * interface to linux i2c bit-banging algorithm +- *****************************************************************************/ +- +-#ifdef CONFIG_NOUVEAU_I2C_INTERNAL_DEFAULT +-#define CSTMSEL true +-#else +-#define CSTMSEL false +-#endif +- +-static int +-nouveau_i2c_pre_xfer(struct i2c_adapter *adap) +-{ +- struct i2c_algo_bit_data *bit = adap->algo_data; +- struct nouveau_i2c_port *port = bit->data; +- return nouveau_i2c(port)->acquire(port, bit->timeout); +-} +- +-static void +-nouveau_i2c_post_xfer(struct i2c_adapter *adap) +-{ +- struct i2c_algo_bit_data *bit = adap->algo_data; +- struct nouveau_i2c_port *port = bit->data; +- return nouveau_i2c(port)->release(port); +-} +- +-static void +-nouveau_i2c_setscl(void *data, int state) +-{ +- struct nouveau_i2c_port *port = data; +- port->func->drive_scl(port, state); +-} +- +-static void +-nouveau_i2c_setsda(void *data, int state) +-{ +- struct nouveau_i2c_port *port = data; +- port->func->drive_sda(port, state); +-} +- +-static int +-nouveau_i2c_getscl(void *data) +-{ +- struct nouveau_i2c_port *port = data; +- return port->func->sense_scl(port); +-} +- +-static int +-nouveau_i2c_getsda(void *data) +-{ +- struct nouveau_i2c_port *port = data; +- return port->func->sense_sda(port); +-} +- +-/****************************************************************************** +- * base i2c "port" class implementation +- *****************************************************************************/ +- +-int +-_nouveau_i2c_port_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_i2c_port *port = (void *)object; +- struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port); +- nv_ofuncs(pad)->fini(nv_object(pad), suspend); +- return nouveau_object_fini(&port->base, suspend); +-} +- +-void +-_nouveau_i2c_port_dtor(struct nouveau_object *object) +-{ +- struct nouveau_i2c_port *port = (void *)object; +- i2c_del_adapter(&port->adapter); +- nouveau_object_destroy(&port->base); +-} +- +-int +-nouveau_i2c_port_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, u8 index, +- const struct i2c_algorithm *algo, +- const struct nouveau_i2c_func *func, +- int size, void **pobject) +-{ +- struct nouveau_device *device = nv_device(engine); +- struct nouveau_i2c *i2c = (void *)engine; +- struct nouveau_i2c_port *port; +- int ret; +- +- ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject); +- port = *pobject; +- if (ret) +- return ret; +- +- snprintf(port->adapter.name, sizeof(port->adapter.name), +- "nouveau-%s-%d", device->name, index); +- port->adapter.owner = THIS_MODULE; +- port->adapter.dev.parent = nv_device_base(device); +- port->index = index; +- port->aux = -1; +- port->func = func; +- mutex_init(&port->mutex); +- +- if ( algo == &nouveau_i2c_bit_algo && +- !nouveau_boolopt(device->cfgopt, "NvI2C", CSTMSEL)) { +- struct i2c_algo_bit_data *bit; +- +- bit = kzalloc(sizeof(*bit), GFP_KERNEL); +- if (!bit) +- return -ENOMEM; +- +- bit->udelay = 10; +- bit->timeout = usecs_to_jiffies(2200); +- bit->data = port; +- bit->pre_xfer = nouveau_i2c_pre_xfer; +- bit->post_xfer = nouveau_i2c_post_xfer; +- bit->setsda = nouveau_i2c_setsda; +- bit->setscl = nouveau_i2c_setscl; +- bit->getsda = nouveau_i2c_getsda; +- bit->getscl = nouveau_i2c_getscl; +- +- port->adapter.algo_data = bit; +- ret = i2c_bit_add_bus(&port->adapter); +- } else { +- port->adapter.algo_data = port; +- port->adapter.algo = algo; +- ret = i2c_add_adapter(&port->adapter); +- } +- +- if (ret == 0) +- list_add_tail(&port->head, &i2c->ports); +- return ret; +-} +- +-/****************************************************************************** +- * base i2c subdev class implementation +- *****************************************************************************/ +- +-static struct nouveau_i2c_port * +-nouveau_i2c_find(struct nouveau_i2c *i2c, u8 index) +-{ +- struct nouveau_bios *bios = nouveau_bios(i2c); +- struct nouveau_i2c_port *port; +- +- if (index == NV_I2C_DEFAULT(0) || +- index == NV_I2C_DEFAULT(1)) { +- u8 ver, hdr, cnt, len; +- u16 i2c = dcb_i2c_table(bios, &ver, &hdr, &cnt, &len); +- if (i2c && ver >= 0x30) { +- u8 auxidx = nv_ro08(bios, i2c + 4); +- if (index == NV_I2C_DEFAULT(0)) +- index = (auxidx & 0x0f) >> 0; +- else +- index = (auxidx & 0xf0) >> 4; +- } else { +- index = 2; +- } +- } +- +- list_for_each_entry(port, &i2c->ports, head) { +- if (port->index == index) +- return port; +- } +- +- return NULL; +-} +- +-static struct nouveau_i2c_port * +-nouveau_i2c_find_type(struct nouveau_i2c *i2c, u16 type) +-{ +- struct nouveau_i2c_port *port; +- +- list_for_each_entry(port, &i2c->ports, head) { +- if (nv_hclass(port) == type) +- return port; +- } +- +- return NULL; +-} +- +-static void +-nouveau_i2c_release_pad(struct nouveau_i2c_port *port) +-{ +- struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port); +- struct nouveau_i2c *i2c = nouveau_i2c(port); +- +- if (atomic_dec_and_test(&nv_object(pad)->usecount)) { +- nv_ofuncs(pad)->fini(nv_object(pad), false); +- wake_up_all(&i2c->wait); +- } +-} +- +-static int +-nouveau_i2c_try_acquire_pad(struct nouveau_i2c_port *port) +-{ +- struct nvkm_i2c_pad *pad = nvkm_i2c_pad(port); +- +- if (atomic_add_return(1, &nv_object(pad)->usecount) != 1) { +- struct nouveau_object *owner = (void *)pad->port; +- do { +- if (owner == (void *)port) +- return 0; +- owner = owner->parent; +- } while(owner); +- nouveau_i2c_release_pad(port); +- return -EBUSY; +- } +- +- pad->next = port; +- nv_ofuncs(pad)->init(nv_object(pad)); +- return 0; +-} +- +-static int +-nouveau_i2c_acquire_pad(struct nouveau_i2c_port *port, unsigned long timeout) +-{ +- struct nouveau_i2c *i2c = nouveau_i2c(port); +- +- if (timeout) { +- if (wait_event_timeout(i2c->wait, +- nouveau_i2c_try_acquire_pad(port) == 0, +- timeout) == 0) +- return -EBUSY; +- } else { +- wait_event(i2c->wait, nouveau_i2c_try_acquire_pad(port) == 0); +- } +- +- return 0; +-} +- +-static void +-nouveau_i2c_release(struct nouveau_i2c_port *port) +-__releases(pad->mutex) +-{ +- nouveau_i2c(port)->release_pad(port); +- mutex_unlock(&port->mutex); +-} +- +-static int +-nouveau_i2c_acquire(struct nouveau_i2c_port *port, unsigned long timeout) +-__acquires(pad->mutex) +-{ +- int ret; +- mutex_lock(&port->mutex); +- if ((ret = nouveau_i2c(port)->acquire_pad(port, timeout))) +- mutex_unlock(&port->mutex); +- return ret; +-} +- +-static int +-nouveau_i2c_identify(struct nouveau_i2c *i2c, int index, const char *what, +- struct nouveau_i2c_board_info *info, +- bool (*match)(struct nouveau_i2c_port *, +- struct i2c_board_info *, void *), void *data) +-{ +- struct nouveau_i2c_port *port = nouveau_i2c_find(i2c, index); +- int i; +- +- if (!port) { +- nv_debug(i2c, "no bus when probing %s on %d\n", what, index); +- return -ENODEV; +- } +- +- nv_debug(i2c, "probing %ss on bus: %d\n", what, port->index); +- for (i = 0; info[i].dev.addr; i++) { +- u8 orig_udelay = 0; +- +- if ((port->adapter.algo == &i2c_bit_algo) && +- (info[i].udelay != 0)) { +- struct i2c_algo_bit_data *algo = port->adapter.algo_data; +- nv_debug(i2c, "using custom udelay %d instead of %d\n", +- info[i].udelay, algo->udelay); +- orig_udelay = algo->udelay; +- algo->udelay = info[i].udelay; +- } +- +- if (nv_probe_i2c(port, info[i].dev.addr) && +- (!match || match(port, &info[i].dev, data))) { +- nv_info(i2c, "detected %s: %s\n", what, +- info[i].dev.type); +- return i; +- } +- +- if (orig_udelay) { +- struct i2c_algo_bit_data *algo = port->adapter.algo_data; +- algo->udelay = orig_udelay; +- } +- } +- +- nv_debug(i2c, "no devices found.\n"); +- return -ENODEV; +-} +- +-static void +-nouveau_i2c_intr_fini(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event); +- struct nouveau_i2c_port *port = i2c->find(i2c, index); +- const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; +- if (port && port->aux >= 0) +- impl->aux_mask(i2c, type, 1 << port->aux, 0); +-} +- +-static void +-nouveau_i2c_intr_init(struct nvkm_event *event, int type, int index) +-{ +- struct nouveau_i2c *i2c = container_of(event, typeof(*i2c), event); +- struct nouveau_i2c_port *port = i2c->find(i2c, index); +- const struct nouveau_i2c_impl *impl = (void *)nv_object(i2c)->oclass; +- if (port && port->aux >= 0) +- impl->aux_mask(i2c, type, 1 << port->aux, 1 << port->aux); +-} +- +-static int +-nouveau_i2c_intr_ctor(struct nouveau_object *object, void *data, u32 size, +- struct nvkm_notify *notify) +-{ +- struct nvkm_i2c_ntfy_req *req = data; +- if (!WARN_ON(size != sizeof(*req))) { +- notify->size = sizeof(struct nvkm_i2c_ntfy_rep); +- notify->types = req->mask; +- notify->index = req->port; +- return 0; +- } +- return -EINVAL; +-} +- +-static void +-nouveau_i2c_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_i2c_impl *impl = (void *)nv_oclass(subdev); +- struct nouveau_i2c *i2c = nouveau_i2c(subdev); +- struct nouveau_i2c_port *port; +- u32 hi, lo, rq, tx, e; +- +- if (impl->aux_stat) { +- impl->aux_stat(i2c, &hi, &lo, &rq, &tx); +- if (hi || lo || rq || tx) { +- list_for_each_entry(port, &i2c->ports, head) { +- if (e = 0, port->aux < 0) +- continue; +- +- if (hi & (1 << port->aux)) e |= NVKM_I2C_PLUG; +- if (lo & (1 << port->aux)) e |= NVKM_I2C_UNPLUG; +- if (rq & (1 << port->aux)) e |= NVKM_I2C_IRQ; +- if (tx & (1 << port->aux)) e |= NVKM_I2C_DONE; +- if (e) { +- struct nvkm_i2c_ntfy_rep rep = { +- .mask = e, +- }; +- nvkm_event_send(&i2c->event, rep.mask, +- port->index, &rep, +- sizeof(rep)); +- } +- } +- } +- } +-} +- +-static const struct nvkm_event_func +-nouveau_i2c_intr_func = { +- .ctor = nouveau_i2c_intr_ctor, +- .init = nouveau_i2c_intr_init, +- .fini = nouveau_i2c_intr_fini, +-}; +- +-int +-_nouveau_i2c_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_i2c_impl *impl = (void *)nv_oclass(object); +- struct nouveau_i2c *i2c = (void *)object; +- struct nouveau_i2c_port *port; +- u32 mask; +- int ret; +- +- list_for_each_entry(port, &i2c->ports, head) { +- ret = nv_ofuncs(port)->fini(nv_object(port), suspend); +- if (ret && suspend) +- goto fail; +- } +- +- if ((mask = (1 << impl->aux) - 1), impl->aux_stat) { +- impl->aux_mask(i2c, NVKM_I2C_ANY, mask, 0); +- impl->aux_stat(i2c, &mask, &mask, &mask, &mask); +- } +- +- return nouveau_subdev_fini(&i2c->base, suspend); +-fail: +- list_for_each_entry_continue_reverse(port, &i2c->ports, head) { +- nv_ofuncs(port)->init(nv_object(port)); +- } +- +- return ret; +-} +- +-int +-_nouveau_i2c_init(struct nouveau_object *object) +-{ +- struct nouveau_i2c *i2c = (void *)object; +- struct nouveau_i2c_port *port; +- int ret; +- +- ret = nouveau_subdev_init(&i2c->base); +- if (ret == 0) { +- list_for_each_entry(port, &i2c->ports, head) { +- ret = nv_ofuncs(port)->init(nv_object(port)); +- if (ret) +- goto fail; +- } +- } +- +- return ret; +-fail: +- list_for_each_entry_continue_reverse(port, &i2c->ports, head) { +- nv_ofuncs(port)->fini(nv_object(port), false); +- } +- +- return ret; +-} +- +-void +-_nouveau_i2c_dtor(struct nouveau_object *object) +-{ +- struct nouveau_i2c *i2c = (void *)object; +- struct nouveau_i2c_port *port, *temp; +- +- nvkm_event_fini(&i2c->event); +- +- list_for_each_entry_safe(port, temp, &i2c->ports, head) { +- nouveau_object_ref(NULL, (struct nouveau_object **)&port); +- } +- +- nouveau_subdev_destroy(&i2c->base); +-} +- +-static struct nouveau_oclass * +-nouveau_i2c_extdev_sclass[] = { +- nouveau_anx9805_sclass, +-}; +- +-int +-nouveau_i2c_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int length, void **pobject) +-{ +- const struct nouveau_i2c_impl *impl = (void *)oclass; +- struct nouveau_bios *bios = nouveau_bios(parent); +- struct nouveau_i2c *i2c; +- struct nouveau_object *object; +- struct dcb_i2c_entry info; +- int ret, i, j, index = -1, pad; +- struct dcb_output outp; +- u8 ver, hdr; +- u32 data; +- +- ret = nouveau_subdev_create(parent, engine, oclass, 0, +- "I2C", "i2c", &i2c); +- *pobject = nv_object(i2c); +- if (ret) +- return ret; +- +- nv_subdev(i2c)->intr = nouveau_i2c_intr; +- i2c->find = nouveau_i2c_find; +- i2c->find_type = nouveau_i2c_find_type; +- i2c->acquire_pad = nouveau_i2c_acquire_pad; +- i2c->release_pad = nouveau_i2c_release_pad; +- i2c->acquire = nouveau_i2c_acquire; +- i2c->release = nouveau_i2c_release; +- i2c->identify = nouveau_i2c_identify; +- init_waitqueue_head(&i2c->wait); +- INIT_LIST_HEAD(&i2c->ports); +- +- while (!dcb_i2c_parse(bios, ++index, &info)) { +- if (info.type == DCB_I2C_UNUSED) +- continue; +- +- if (info.share != DCB_I2C_UNUSED) { +- if (info.type == DCB_I2C_NVIO_AUX) +- pad = info.drive; +- else +- pad = info.share; +- oclass = impl->pad_s; +- } else { +- pad = 0x100 + info.drive; +- oclass = impl->pad_x; +- } +- +- ret = nouveau_object_ctor(NULL, *pobject, oclass, +- NULL, pad, &parent); +- if (ret < 0) +- continue; +- +- oclass = impl->sclass; +- do { +- ret = -EINVAL; +- if (oclass->handle == info.type) { +- ret = nouveau_object_ctor(parent, *pobject, +- oclass, &info, +- index, &object); +- } +- } while (ret && (++oclass)->handle); +- +- nouveau_object_ref(NULL, &parent); +- } +- +- /* in addition to the busses specified in the i2c table, there +- * may be ddc/aux channels hiding behind external tmds/dp/etc +- * transmitters. +- */ +- index = ((index + 0x0f) / 0x10) * 0x10; +- i = -1; +- while ((data = dcb_outp_parse(bios, ++i, &ver, &hdr, &outp))) { +- if (!outp.location || !outp.extdev) +- continue; +- +- switch (outp.type) { +- case DCB_OUTPUT_TMDS: +- info.type = NV_I2C_TYPE_EXTDDC(outp.extdev); +- break; +- case DCB_OUTPUT_DP: +- info.type = NV_I2C_TYPE_EXTAUX(outp.extdev); +- break; +- default: +- continue; +- } +- +- ret = -ENODEV; +- j = -1; +- while (ret && ++j < ARRAY_SIZE(nouveau_i2c_extdev_sclass)) { +- parent = nv_object(i2c->find(i2c, outp.i2c_index)); +- oclass = nouveau_i2c_extdev_sclass[j]; +- do { +- if (oclass->handle != info.type) +- continue; +- ret = nouveau_object_ctor(parent, *pobject, +- oclass, NULL, +- index++, &object); +- } while (ret && (++oclass)->handle); +- } +- } +- +- ret = nvkm_event_init(&nouveau_i2c_intr_func, 4, index, &i2c->event); +- if (ret) +- return ret; +- +- return 0; +-} +- +-int +-_nouveau_i2c_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_i2c *i2c; +- int ret; +- +- ret = nouveau_i2c_create(parent, engine, oclass, &i2c); +- *pobject = nv_object(i2c); +- if (ret) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c +deleted file mode 100644 +index 813ffc96..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/bit.c ++++ /dev/null +@@ -1,234 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-#ifdef CONFIG_NOUVEAU_I2C_INTERNAL +-#define T_TIMEOUT 2200000 +-#define T_RISEFALL 1000 +-#define T_HOLD 5000 +- +-static inline void +-i2c_drive_scl(struct nouveau_i2c_port *port, int state) +-{ +- port->func->drive_scl(port, state); +-} +- +-static inline void +-i2c_drive_sda(struct nouveau_i2c_port *port, int state) +-{ +- port->func->drive_sda(port, state); +-} +- +-static inline int +-i2c_sense_scl(struct nouveau_i2c_port *port) +-{ +- return port->func->sense_scl(port); +-} +- +-static inline int +-i2c_sense_sda(struct nouveau_i2c_port *port) +-{ +- return port->func->sense_sda(port); +-} +- +-static void +-i2c_delay(struct nouveau_i2c_port *port, u32 nsec) +-{ +- udelay((nsec + 500) / 1000); +-} +- +-static bool +-i2c_raise_scl(struct nouveau_i2c_port *port) +-{ +- u32 timeout = T_TIMEOUT / T_RISEFALL; +- +- i2c_drive_scl(port, 1); +- do { +- i2c_delay(port, T_RISEFALL); +- } while (!i2c_sense_scl(port) && --timeout); +- +- return timeout != 0; +-} +- +-static int +-i2c_start(struct nouveau_i2c_port *port) +-{ +- int ret = 0; +- +- if (!i2c_sense_scl(port) || +- !i2c_sense_sda(port)) { +- i2c_drive_scl(port, 0); +- i2c_drive_sda(port, 1); +- if (!i2c_raise_scl(port)) +- ret = -EBUSY; +- } +- +- i2c_drive_sda(port, 0); +- i2c_delay(port, T_HOLD); +- i2c_drive_scl(port, 0); +- i2c_delay(port, T_HOLD); +- return ret; +-} +- +-static void +-i2c_stop(struct nouveau_i2c_port *port) +-{ +- i2c_drive_scl(port, 0); +- i2c_drive_sda(port, 0); +- i2c_delay(port, T_RISEFALL); +- +- i2c_drive_scl(port, 1); +- i2c_delay(port, T_HOLD); +- i2c_drive_sda(port, 1); +- i2c_delay(port, T_HOLD); +-} +- +-static int +-i2c_bitw(struct nouveau_i2c_port *port, int sda) +-{ +- i2c_drive_sda(port, sda); +- i2c_delay(port, T_RISEFALL); +- +- if (!i2c_raise_scl(port)) +- return -ETIMEDOUT; +- i2c_delay(port, T_HOLD); +- +- i2c_drive_scl(port, 0); +- i2c_delay(port, T_HOLD); +- return 0; +-} +- +-static int +-i2c_bitr(struct nouveau_i2c_port *port) +-{ +- int sda; +- +- i2c_drive_sda(port, 1); +- i2c_delay(port, T_RISEFALL); +- +- if (!i2c_raise_scl(port)) +- return -ETIMEDOUT; +- i2c_delay(port, T_HOLD); +- +- sda = i2c_sense_sda(port); +- +- i2c_drive_scl(port, 0); +- i2c_delay(port, T_HOLD); +- return sda; +-} +- +-static int +-i2c_get_byte(struct nouveau_i2c_port *port, u8 *byte, bool last) +-{ +- int i, bit; +- +- *byte = 0; +- for (i = 7; i >= 0; i--) { +- bit = i2c_bitr(port); +- if (bit < 0) +- return bit; +- *byte |= bit << i; +- } +- +- return i2c_bitw(port, last ? 1 : 0); +-} +- +-static int +-i2c_put_byte(struct nouveau_i2c_port *port, u8 byte) +-{ +- int i, ret; +- for (i = 7; i >= 0; i--) { +- ret = i2c_bitw(port, !!(byte & (1 << i))); +- if (ret < 0) +- return ret; +- } +- +- ret = i2c_bitr(port); +- if (ret == 1) /* nack */ +- ret = -EIO; +- return ret; +-} +- +-static int +-i2c_addr(struct nouveau_i2c_port *port, struct i2c_msg *msg) +-{ +- u32 addr = msg->addr << 1; +- if (msg->flags & I2C_M_RD) +- addr |= 1; +- return i2c_put_byte(port, addr); +-} +- +-static int +-i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +-{ +- struct nouveau_i2c_port *port = adap->algo_data; +- struct i2c_msg *msg = msgs; +- int ret = 0, mcnt = num; +- +- ret = nouveau_i2c(port)->acquire(port, nsecs_to_jiffies(T_TIMEOUT)); +- if (ret) +- return ret; +- +- while (!ret && mcnt--) { +- u8 remaining = msg->len; +- u8 *ptr = msg->buf; +- +- ret = i2c_start(port); +- if (ret == 0) +- ret = i2c_addr(port, msg); +- +- if (msg->flags & I2C_M_RD) { +- while (!ret && remaining--) +- ret = i2c_get_byte(port, ptr++, !remaining); +- } else { +- while (!ret && remaining--) +- ret = i2c_put_byte(port, *ptr++); +- } +- +- msg++; +- } +- +- i2c_stop(port); +- nouveau_i2c(port)->release(port); +- return (ret < 0) ? ret : num; +-} +-#else +-static int +-i2c_bit_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) +-{ +- return -ENODEV; +-} +-#endif +- +-static u32 +-i2c_bit_func(struct i2c_adapter *adap) +-{ +- return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +-} +- +-const struct i2c_algorithm nouveau_i2c_bit_algo = { +- .master_xfer = i2c_bit_xfer, +- .functionality = i2c_bit_func +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c +deleted file mode 100644 +index fa891c39..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/gf117.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-struct nouveau_oclass * +-gf117_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0xd7), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nvd0_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +- .pad_s = &nv04_i2c_pad_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c +deleted file mode 100644 +index b1725bde..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv04.c ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "priv.h" +- +-struct nv04_i2c_priv { +- struct nouveau_i2c base; +-}; +- +-struct nv04_i2c_port { +- struct nouveau_i2c_port base; +- u8 drive; +- u8 sense; +-}; +- +-static void +-nv04_i2c_drive_scl(struct nouveau_i2c_port *base, int state) +-{ +- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv04_i2c_port *port = (void *)base; +- u8 val = nv_rdvgac(priv, 0, port->drive); +- if (state) val |= 0x20; +- else val &= 0xdf; +- nv_wrvgac(priv, 0, port->drive, val | 0x01); +-} +- +-static void +-nv04_i2c_drive_sda(struct nouveau_i2c_port *base, int state) +-{ +- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv04_i2c_port *port = (void *)base; +- u8 val = nv_rdvgac(priv, 0, port->drive); +- if (state) val |= 0x10; +- else val &= 0xef; +- nv_wrvgac(priv, 0, port->drive, val | 0x01); +-} +- +-static int +-nv04_i2c_sense_scl(struct nouveau_i2c_port *base) +-{ +- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv04_i2c_port *port = (void *)base; +- return !!(nv_rdvgac(priv, 0, port->sense) & 0x04); +-} +- +-static int +-nv04_i2c_sense_sda(struct nouveau_i2c_port *base) +-{ +- struct nv04_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv04_i2c_port *port = (void *)base; +- return !!(nv_rdvgac(priv, 0, port->sense) & 0x08); +-} +- +-static const struct nouveau_i2c_func +-nv04_i2c_func = { +- .drive_scl = nv04_i2c_drive_scl, +- .drive_sda = nv04_i2c_drive_sda, +- .sense_scl = nv04_i2c_sense_scl, +- .sense_sda = nv04_i2c_sense_sda, +-}; +- +-static int +-nv04_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct dcb_i2c_entry *info = data; +- struct nv04_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_bit_algo, &nv04_i2c_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- port->drive = info->drive; +- port->sense = info->sense; +- return 0; +-} +- +-static struct nouveau_oclass +-nv04_i2c_sclass[] = { +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV04_BIT), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_i2c_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = _nouveau_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- {} +-}; +- +-struct nouveau_oclass * +-nv04_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nv04_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c +deleted file mode 100644 +index f16c87ce..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv4e.c ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "priv.h" +- +-struct nv4e_i2c_priv { +- struct nouveau_i2c base; +-}; +- +-struct nv4e_i2c_port { +- struct nouveau_i2c_port base; +- u32 addr; +-}; +- +-static void +-nv4e_i2c_drive_scl(struct nouveau_i2c_port *base, int state) +-{ +- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv4e_i2c_port *port = (void *)base; +- nv_mask(priv, port->addr, 0x2f, state ? 0x21 : 0x01); +-} +- +-static void +-nv4e_i2c_drive_sda(struct nouveau_i2c_port *base, int state) +-{ +- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv4e_i2c_port *port = (void *)base; +- nv_mask(priv, port->addr, 0x1f, state ? 0x11 : 0x01); +-} +- +-static int +-nv4e_i2c_sense_scl(struct nouveau_i2c_port *base) +-{ +- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv4e_i2c_port *port = (void *)base; +- return !!(nv_rd32(priv, port->addr) & 0x00040000); +-} +- +-static int +-nv4e_i2c_sense_sda(struct nouveau_i2c_port *base) +-{ +- struct nv4e_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv4e_i2c_port *port = (void *)base; +- return !!(nv_rd32(priv, port->addr) & 0x00080000); +-} +- +-static const struct nouveau_i2c_func +-nv4e_i2c_func = { +- .drive_scl = nv4e_i2c_drive_scl, +- .drive_sda = nv4e_i2c_drive_sda, +- .sense_scl = nv4e_i2c_sense_scl, +- .sense_sda = nv4e_i2c_sense_sda, +-}; +- +-static int +-nv4e_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct dcb_i2c_entry *info = data; +- struct nv4e_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_bit_algo, &nv4e_i2c_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- port->addr = 0x600800 + info->drive; +- return 0; +-} +- +-static struct nouveau_oclass +-nv4e_i2c_sclass[] = { +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NV4E_BIT), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv4e_i2c_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = _nouveau_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- {} +-}; +- +-struct nouveau_oclass * +-nv4e_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0x4e), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nv4e_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c +deleted file mode 100644 +index 7b8756d4..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.c ++++ /dev/null +@@ -1,135 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-void +-nv50_i2c_drive_scl(struct nouveau_i2c_port *base, int state) +-{ +- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv50_i2c_port *port = (void *)base; +- if (state) port->state |= 0x01; +- else port->state &= 0xfe; +- nv_wr32(priv, port->addr, port->state); +-} +- +-void +-nv50_i2c_drive_sda(struct nouveau_i2c_port *base, int state) +-{ +- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv50_i2c_port *port = (void *)base; +- if (state) port->state |= 0x02; +- else port->state &= 0xfd; +- nv_wr32(priv, port->addr, port->state); +-} +- +-int +-nv50_i2c_sense_scl(struct nouveau_i2c_port *base) +-{ +- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv50_i2c_port *port = (void *)base; +- return !!(nv_rd32(priv, port->addr) & 0x00000001); +-} +- +-int +-nv50_i2c_sense_sda(struct nouveau_i2c_port *base) +-{ +- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv50_i2c_port *port = (void *)base; +- return !!(nv_rd32(priv, port->addr) & 0x00000002); +-} +- +-static const struct nouveau_i2c_func +-nv50_i2c_func = { +- .drive_scl = nv50_i2c_drive_scl, +- .drive_sda = nv50_i2c_drive_sda, +- .sense_scl = nv50_i2c_sense_scl, +- .sense_sda = nv50_i2c_sense_sda, +-}; +- +-const u32 nv50_i2c_addr[] = { +- 0x00e138, 0x00e150, 0x00e168, 0x00e180, +- 0x00e254, 0x00e274, 0x00e764, 0x00e780, +- 0x00e79c, 0x00e7b8 +-}; +-const int nv50_i2c_addr_nr = ARRAY_SIZE(nv50_i2c_addr); +- +-static int +-nv50_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct dcb_i2c_entry *info = data; +- struct nv50_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_bit_algo, &nv50_i2c_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- if (info->drive >= nv50_i2c_addr_nr) +- return -EINVAL; +- +- port->state = 0x00000007; +- port->addr = nv50_i2c_addr[info->drive]; +- return 0; +-} +- +-int +-nv50_i2c_port_init(struct nouveau_object *object) +-{ +- struct nv50_i2c_priv *priv = (void *)object->engine; +- struct nv50_i2c_port *port = (void *)object; +- nv_wr32(priv, port->addr, port->state); +- return nouveau_i2c_port_init(&port->base); +-} +- +-static struct nouveau_oclass +-nv50_i2c_sclass[] = { +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_i2c_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = nv50_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- {} +-}; +- +-struct nouveau_oclass * +-nv50_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nv50_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h +deleted file mode 100644 +index 5d2a7742..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv50.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-#ifndef __NV50_I2C_H__ +-#define __NV50_I2C_H__ +- +-#include "priv.h" +- +-struct nv50_i2c_priv { +- struct nouveau_i2c base; +-}; +- +-struct nv50_i2c_port { +- struct nouveau_i2c_port base; +- u32 addr; +- u32 ctrl; +- u32 data; +- u32 state; +-}; +- +-extern const u32 nv50_i2c_addr[]; +-extern const int nv50_i2c_addr_nr; +-int nv50_i2c_port_init(struct nouveau_object *); +-int nv50_i2c_sense_scl(struct nouveau_i2c_port *); +-int nv50_i2c_sense_sda(struct nouveau_i2c_port *); +-void nv50_i2c_drive_scl(struct nouveau_i2c_port *, int state); +-void nv50_i2c_drive_sda(struct nouveau_i2c_port *, int state); +- +-int nv94_aux_port_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv94_i2c_acquire(struct nouveau_i2c_port *); +-void nv94_i2c_release(struct nouveau_i2c_port *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c +deleted file mode 100644 +index f59c3a25..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nv94.c ++++ /dev/null +@@ -1,291 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-void +-nv94_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) +-{ +- u32 intr = nv_rd32(i2c, 0x00e06c); +- u32 stat = nv_rd32(i2c, 0x00e068) & intr, i; +- for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) { +- if ((stat & (1 << (i * 4)))) *hi |= 1 << i; +- if ((stat & (2 << (i * 4)))) *lo |= 1 << i; +- if ((stat & (4 << (i * 4)))) *rq |= 1 << i; +- if ((stat & (8 << (i * 4)))) *tx |= 1 << i; +- } +- nv_wr32(i2c, 0x00e06c, intr); +-} +- +-void +-nv94_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) +-{ +- u32 temp = nv_rd32(i2c, 0x00e068), i; +- for (i = 0; i < 8; i++) { +- if (mask & (1 << i)) { +- if (!(data & (1 << i))) { +- temp &= ~(type << (i * 4)); +- continue; +- } +- temp |= type << (i * 4); +- } +- } +- nv_wr32(i2c, 0x00e068, temp); +-} +- +-#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args) +-#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args) +- +-static void +-auxch_fini(struct nouveau_i2c *aux, int ch) +-{ +- nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000); +-} +- +-static int +-auxch_init(struct nouveau_i2c *aux, int ch) +-{ +- const u32 unksel = 1; /* nfi which to use, or if it matters.. */ +- const u32 ureq = unksel ? 0x00100000 : 0x00200000; +- const u32 urep = unksel ? 0x01000000 : 0x02000000; +- u32 ctrl, timeout; +- +- /* wait up to 1ms for any previous transaction to be done... */ +- timeout = 1000; +- do { +- ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); +- udelay(1); +- if (!timeout--) { +- AUX_ERR("begin idle timeout 0x%08x\n", ctrl); +- return -EBUSY; +- } +- } while (ctrl & 0x03010000); +- +- /* set some magic, and wait up to 1ms for it to appear */ +- nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq); +- timeout = 1000; +- do { +- ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); +- udelay(1); +- if (!timeout--) { +- AUX_ERR("magic wait 0x%08x\n", ctrl); +- auxch_fini(aux, ch); +- return -EBUSY; +- } +- } while ((ctrl & 0x03000000) != urep); +- +- return 0; +-} +- +-int +-nv94_aux(struct nouveau_i2c_port *base, bool retry, +- u8 type, u32 addr, u8 *data, u8 size) +-{ +- struct nouveau_i2c *aux = nouveau_i2c(base); +- struct nv50_i2c_port *port = (void *)base; +- u32 ctrl, stat, timeout, retries; +- u32 xbuf[4] = {}; +- int ch = port->addr; +- int ret, i; +- +- AUX_DBG("%d: 0x%08x %d\n", type, addr, size); +- +- ret = auxch_init(aux, ch); +- if (ret) +- goto out; +- +- stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50)); +- if (!(stat & 0x10000000)) { +- AUX_DBG("sink not detected\n"); +- ret = -ENXIO; +- goto out; +- } +- +- if (!(type & 1)) { +- memcpy(xbuf, data, size); +- for (i = 0; i < 16; i += 4) { +- AUX_DBG("wr 0x%08x\n", xbuf[i / 4]); +- nv_wr32(aux, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]); +- } +- } +- +- ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); +- ctrl &= ~0x0001f0ff; +- ctrl |= type << 12; +- ctrl |= size - 1; +- nv_wr32(aux, 0x00e4e0 + (ch * 0x50), addr); +- +- /* (maybe) retry transaction a number of times on failure... */ +- for (retries = 0; !ret && retries < 32; retries++) { +- /* reset, and delay a while if this is a retry */ +- nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl); +- nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl); +- if (retries) +- udelay(400); +- +- /* transaction request, wait up to 1ms for it to complete */ +- nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl); +- +- timeout = 1000; +- do { +- ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50)); +- udelay(1); +- if (!timeout--) { +- AUX_ERR("tx req timeout 0x%08x\n", ctrl); +- ret = -EIO; +- goto out; +- } +- } while (ctrl & 0x00010000); +- ret = 1; +- +- /* read status, and check if transaction completed ok */ +- stat = nv_mask(aux, 0x00e4e8 + (ch * 0x50), 0, 0); +- if ((stat & 0x000f0000) == 0x00080000 || +- (stat & 0x000f0000) == 0x00020000) +- ret = retry ? 0 : 1; +- if ((stat & 0x00000100)) +- ret = -ETIMEDOUT; +- if ((stat & 0x00000e00)) +- ret = -EIO; +- +- AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat); +- } +- +- if (type & 1) { +- for (i = 0; i < 16; i += 4) { +- xbuf[i / 4] = nv_rd32(aux, 0x00e4d0 + (ch * 0x50) + i); +- AUX_DBG("rd 0x%08x\n", xbuf[i / 4]); +- } +- memcpy(data, xbuf, size); +- } +- +-out: +- auxch_fini(aux, ch); +- return ret < 0 ? ret : (stat & 0x000f0000) >> 16; +-} +- +-static const struct nouveau_i2c_func +-nv94_i2c_func = { +- .drive_scl = nv50_i2c_drive_scl, +- .drive_sda = nv50_i2c_drive_sda, +- .sense_scl = nv50_i2c_sense_scl, +- .sense_sda = nv50_i2c_sense_sda, +-}; +- +-static int +-nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct dcb_i2c_entry *info = data; +- struct nv50_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_bit_algo, &nv94_i2c_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- if (info->drive >= nv50_i2c_addr_nr) +- return -EINVAL; +- +- port->state = 7; +- port->addr = nv50_i2c_addr[info->drive]; +- if (info->share != DCB_I2C_UNUSED) { +- port->ctrl = 0x00e500 + (info->share * 0x50); +- port->data = 0x0000e001; +- } +- return 0; +-} +- +-static const struct nouveau_i2c_func +-nv94_aux_func = { +- .aux = nv94_aux, +-}; +- +-int +-nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct dcb_i2c_entry *info = data; +- struct nv50_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_aux_algo, &nv94_aux_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- port->base.aux = info->drive; +- port->addr = info->drive; +- if (info->share != DCB_I2C_UNUSED) { +- port->ctrl = 0x00e500 + (info->drive * 0x50); +- port->data = 0x00002002; +- } +- +- return 0; +-} +- +-static struct nouveau_oclass +-nv94_i2c_sclass[] = { +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv94_i2c_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = nv50_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv94_aux_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = _nouveau_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- {} +-}; +- +-struct nouveau_oclass * +-nv94_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0x94), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nv94_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +- .pad_s = &nv94_i2c_pad_oclass, +- .aux = 4, +- .aux_stat = nv94_aux_stat, +- .aux_mask = nv94_aux_mask, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c +deleted file mode 100644 +index 364ddb1c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nvd0.c ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static int +-nvd0_i2c_sense_scl(struct nouveau_i2c_port *base) +-{ +- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv50_i2c_port *port = (void *)base; +- return !!(nv_rd32(priv, port->addr) & 0x00000010); +-} +- +-static int +-nvd0_i2c_sense_sda(struct nouveau_i2c_port *base) +-{ +- struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine; +- struct nv50_i2c_port *port = (void *)base; +- return !!(nv_rd32(priv, port->addr) & 0x00000020); +-} +- +-static const struct nouveau_i2c_func +-nvd0_i2c_func = { +- .drive_scl = nv50_i2c_drive_scl, +- .drive_sda = nv50_i2c_drive_sda, +- .sense_scl = nvd0_i2c_sense_scl, +- .sense_sda = nvd0_i2c_sense_sda, +-}; +- +-static int +-nvd0_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct dcb_i2c_entry *info = data; +- struct nv50_i2c_port *port; +- int ret; +- +- ret = nouveau_i2c_port_create(parent, engine, oclass, index, +- &nouveau_i2c_bit_algo, &nvd0_i2c_func, +- &port); +- *pobject = nv_object(port); +- if (ret) +- return ret; +- +- port->state = 0x00000007; +- port->addr = 0x00d014 + (info->drive * 0x20); +- if (info->share != DCB_I2C_UNUSED) { +- port->ctrl = 0x00e500 + (info->share * 0x50); +- port->data = 0x0000e001; +- } +- return 0; +-} +- +-struct nouveau_oclass +-nvd0_i2c_sclass[] = { +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvd0_i2c_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = nv50_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- { .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv94_aux_port_ctor, +- .dtor = _nouveau_i2c_port_dtor, +- .init = _nouveau_i2c_port_init, +- .fini = _nouveau_i2c_port_fini, +- }, +- }, +- {} +-}; +- +-struct nouveau_oclass * +-nvd0_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0xd0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nvd0_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +- .pad_s = &nv94_i2c_pad_oclass, +- .aux = 4, +- .aux_stat = nv94_aux_stat, +- .aux_mask = nv94_aux_mask, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c +deleted file mode 100644 +index cae77e1a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/nve0.c ++++ /dev/null +@@ -1,72 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv50.h" +- +-static void +-nve0_aux_stat(struct nouveau_i2c *i2c, u32 *hi, u32 *lo, u32 *rq, u32 *tx) +-{ +- u32 intr = nv_rd32(i2c, 0x00dc60); +- u32 stat = nv_rd32(i2c, 0x00dc68) & intr, i; +- for (i = 0, *hi = *lo = *rq = *tx = 0; i < 8; i++) { +- if ((stat & (1 << (i * 4)))) *hi |= 1 << i; +- if ((stat & (2 << (i * 4)))) *lo |= 1 << i; +- if ((stat & (4 << (i * 4)))) *rq |= 1 << i; +- if ((stat & (8 << (i * 4)))) *tx |= 1 << i; +- } +- nv_wr32(i2c, 0x00dc60, intr); +-} +- +-static void +-nve0_aux_mask(struct nouveau_i2c *i2c, u32 type, u32 mask, u32 data) +-{ +- u32 temp = nv_rd32(i2c, 0x00dc68), i; +- for (i = 0; i < 8; i++) { +- if (mask & (1 << i)) { +- if (!(data & (1 << i))) { +- temp &= ~(type << (i * 4)); +- continue; +- } +- temp |= type << (i * 4); +- } +- } +- nv_wr32(i2c, 0x00dc68, temp); +-} +- +-struct nouveau_oclass * +-nve0_i2c_oclass = &(struct nouveau_i2c_impl) { +- .base.handle = NV_SUBDEV(I2C, 0xe0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_i2c_ctor, +- .dtor = _nouveau_i2c_dtor, +- .init = _nouveau_i2c_init, +- .fini = _nouveau_i2c_fini, +- }, +- .sclass = nvd0_i2c_sclass, +- .pad_x = &nv04_i2c_pad_oclass, +- .pad_s = &nv94_i2c_pad_oclass, +- .aux = 4, +- .aux_stat = nve0_aux_stat, +- .aux_mask = nve0_aux_mask, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c +deleted file mode 100644 +index e9e41247..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.c ++++ /dev/null +@@ -1,84 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "pad.h" +- +-int +-_nvkm_i2c_pad_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nvkm_i2c_pad *pad = (void *)object; +- DBG("-> NULL\n"); +- pad->port = NULL; +- return nouveau_object_fini(&pad->base, suspend); +-} +- +-int +-_nvkm_i2c_pad_init(struct nouveau_object *object) +-{ +- struct nvkm_i2c_pad *pad = (void *)object; +- DBG("-> PORT:%02x\n", pad->next->index); +- pad->port = pad->next; +- return nouveau_object_init(&pad->base); +-} +- +-int +-nvkm_i2c_pad_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int index, +- int size, void **pobject) +-{ +- struct nouveau_i2c *i2c = (void *)engine; +- struct nouveau_i2c_port *port; +- struct nvkm_i2c_pad *pad; +- int ret; +- +- list_for_each_entry(port, &i2c->ports, head) { +- pad = nvkm_i2c_pad(port); +- if (pad->index == index) { +- atomic_inc(&nv_object(pad)->refcount); +- *pobject = pad; +- return 1; +- } +- } +- +- ret = nouveau_object_create_(parent, engine, oclass, 0, size, pobject); +- pad = *pobject; +- if (ret) +- return ret; +- +- pad->index = index; +- return 0; +-} +- +-int +-_nvkm_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nvkm_i2c_pad *pad; +- int ret; +- ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); +- *pobject = nv_object(pad); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h +deleted file mode 100644 +index 452ac10c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/pad.h ++++ /dev/null +@@ -1,58 +0,0 @@ +-#ifndef __NVKM_I2C_PAD_H__ +-#define __NVKM_I2C_PAD_H__ +- +-#include "priv.h" +- +-struct nvkm_i2c_pad { +- struct nouveau_object base; +- int index; +- struct nouveau_i2c_port *port; +- struct nouveau_i2c_port *next; +-}; +- +-static inline struct nvkm_i2c_pad * +-nvkm_i2c_pad(struct nouveau_i2c_port *port) +-{ +- struct nouveau_object *pad = nv_object(port); +- while (pad->parent) +- pad = pad->parent; +- return (void *)pad; +-} +- +-#define nvkm_i2c_pad_create(p,e,o,i,d) \ +- nvkm_i2c_pad_create_((p), (e), (o), (i), sizeof(**d), (void **)d) +-#define nvkm_i2c_pad_destroy(p) ({ \ +- struct nvkm_i2c_pad *_p = (p); \ +- _nvkm_i2c_pad_dtor(nv_object(_p)); \ +-}) +-#define nvkm_i2c_pad_init(p) ({ \ +- struct nvkm_i2c_pad *_p = (p); \ +- _nvkm_i2c_pad_init(nv_object(_p)); \ +-}) +-#define nvkm_i2c_pad_fini(p,s) ({ \ +- struct nvkm_i2c_pad *_p = (p); \ +- _nvkm_i2c_pad_fini(nv_object(_p), (s)); \ +-}) +- +-int nvkm_i2c_pad_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int index, int, void **); +- +-int _nvkm_i2c_pad_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-#define _nvkm_i2c_pad_dtor nouveau_object_destroy +-int _nvkm_i2c_pad_init(struct nouveau_object *); +-int _nvkm_i2c_pad_fini(struct nouveau_object *, bool); +- +-#ifndef MSG +-#define MSG(l,f,a...) do { \ +- struct nvkm_i2c_pad *_pad = (void *)pad; \ +- nv_##l(nv_object(_pad)->engine, "PAD:%c:%02x: "f, \ +- _pad->index >= 0x100 ? 'X' : 'S', \ +- _pad->index >= 0x100 ? _pad->index - 0x100 : _pad->index, ##a); \ +-} while(0) +-#define DBG(f,a...) MSG(debug, f, ##a) +-#define ERR(f,a...) MSG(error, f, ##a) +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c +deleted file mode 100644 +index 2c4b6129..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv04.c ++++ /dev/null +@@ -1,35 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "pad.h" +- +-struct nouveau_oclass +-nv04_i2c_pad_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nvkm_i2c_pad_ctor, +- .dtor = _nvkm_i2c_pad_dtor, +- .init = _nvkm_i2c_pad_init, +- .fini = _nvkm_i2c_pad_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c b/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c +deleted file mode 100644 +index 0dc67530..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/padnv94.c ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "pad.h" +- +-struct nv94_i2c_pad { +- struct nvkm_i2c_pad base; +- int addr; +-}; +- +-static int +-nv94_i2c_pad_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_i2c *i2c = (void *)object->engine; +- struct nv94_i2c_pad *pad = (void *)object; +- nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000001); +- return nvkm_i2c_pad_fini(&pad->base, suspend); +-} +- +-static int +-nv94_i2c_pad_init(struct nouveau_object *object) +-{ +- struct nouveau_i2c *i2c = (void *)object->engine; +- struct nv94_i2c_pad *pad = (void *)object; +- +- switch (nv_oclass(pad->base.next)->handle) { +- case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX): +- nv_mask(i2c, 0x00e500 + pad->addr, 0x0000c003, 0x00000002); +- break; +- case NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT): +- default: +- nv_mask(i2c, 0x00e500 + pad->addr, 0x0000c003, 0x0000c001); +- break; +- } +- +- nv_mask(i2c, 0x00e50c + pad->addr, 0x00000001, 0x00000000); +- return nvkm_i2c_pad_init(&pad->base); +-} +- +-static int +-nv94_i2c_pad_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 index, +- struct nouveau_object **pobject) +-{ +- struct nv94_i2c_pad *pad; +- int ret; +- +- ret = nvkm_i2c_pad_create(parent, engine, oclass, index, &pad); +- *pobject = nv_object(pad); +- if (ret) +- return ret; +- +- pad->addr = index * 0x50;; +- return 0; +-} +- +-struct nouveau_oclass +-nv94_i2c_pad_oclass = { +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv94_i2c_pad_ctor, +- .dtor = _nvkm_i2c_pad_dtor, +- .init = nv94_i2c_pad_init, +- .fini = nv94_i2c_pad_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h +deleted file mode 100644 +index a8ff6e07..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/port.h ++++ /dev/null +@@ -1,15 +0,0 @@ +-#ifndef __NVKM_I2C_PORT_H__ +-#define __NVKM_I2C_PORT_H__ +- +-#include "priv.h" +- +-#ifndef MSG +-#define MSG(l,f,a...) do { \ +- struct nouveau_i2c_port *_port = (void *)port; \ +- nv_##l(nv_object(_port)->engine, "PORT:%02x: "f, _port->index, ##a); \ +-} while(0) +-#define DBG(f,a...) MSG(debug, f, ##a) +-#define ERR(f,a...) MSG(error, f, ##a) +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h b/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h +deleted file mode 100644 +index 780090b6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/i2c/priv.h ++++ /dev/null +@@ -1,85 +0,0 @@ +-#ifndef __NVKM_I2C_H__ +-#define __NVKM_I2C_H__ +- +-#include +- +-extern struct nouveau_oclass nv04_i2c_pad_oclass; +-extern struct nouveau_oclass nv94_i2c_pad_oclass; +- +-#define nouveau_i2c_port_create(p,e,o,i,a,f,d) \ +- nouveau_i2c_port_create_((p), (e), (o), (i), (a), (f), \ +- sizeof(**d), (void **)d) +-#define nouveau_i2c_port_destroy(p) ({ \ +- struct nouveau_i2c_port *port = (p); \ +- _nouveau_i2c_port_dtor(nv_object(i2c)); \ +-}) +-#define nouveau_i2c_port_init(p) \ +- nouveau_object_init(&(p)->base) +-#define nouveau_i2c_port_fini(p,s) \ +- nouveau_object_fini(&(p)->base, (s)) +- +-int nouveau_i2c_port_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, u8, +- const struct i2c_algorithm *, +- const struct nouveau_i2c_func *, +- int, void **); +-void _nouveau_i2c_port_dtor(struct nouveau_object *); +-#define _nouveau_i2c_port_init nouveau_object_init +-int _nouveau_i2c_port_fini(struct nouveau_object *, bool); +- +-#define nouveau_i2c_create(p,e,o,d) \ +- nouveau_i2c_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_i2c_destroy(p) ({ \ +- struct nouveau_i2c *i2c = (p); \ +- _nouveau_i2c_dtor(nv_object(i2c)); \ +-}) +-#define nouveau_i2c_init(p) ({ \ +- struct nouveau_i2c *i2c = (p); \ +- _nouveau_i2c_init(nv_object(i2c)); \ +-}) +-#define nouveau_i2c_fini(p,s) ({ \ +- struct nouveau_i2c *i2c = (p); \ +- _nouveau_i2c_fini(nv_object(i2c), (s)); \ +-}) +- +-int nouveau_i2c_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-int _nouveau_i2c_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void _nouveau_i2c_dtor(struct nouveau_object *); +-int _nouveau_i2c_init(struct nouveau_object *); +-int _nouveau_i2c_fini(struct nouveau_object *, bool); +- +-extern struct nouveau_oclass nouveau_anx9805_sclass[]; +-extern struct nouveau_oclass nvd0_i2c_sclass[]; +- +-extern const struct i2c_algorithm nouveau_i2c_bit_algo; +-extern const struct i2c_algorithm nouveau_i2c_aux_algo; +- +-struct nouveau_i2c_impl { +- struct nouveau_oclass base; +- +- /* supported i2c port classes */ +- struct nouveau_oclass *sclass; +- struct nouveau_oclass *pad_x; +- struct nouveau_oclass *pad_s; +- +- /* number of native dp aux channels present */ +- int aux; +- +- /* read and ack pending interrupts, returning only data +- * for ports that have not been masked off, while still +- * performing the ack for anything that was pending. +- */ +- void (*aux_stat)(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *); +- +- /* mask on/off interrupt types for a given set of auxch +- */ +- void (*aux_mask)(struct nouveau_i2c *, u32, u32, u32); +-}; +- +-void nv94_aux_stat(struct nouveau_i2c *, u32 *, u32 *, u32 *, u32 *); +-void nv94_aux_mask(struct nouveau_i2c *, u32, u32, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c +deleted file mode 100644 +index 245f0eba..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/gk20a.c ++++ /dev/null +@@ -1,103 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-struct gk20a_ibus_priv { +- struct nouveau_ibus base; +-}; +- +-static void +-gk20a_ibus_init_priv_ring(struct gk20a_ibus_priv *priv) +-{ +- nv_mask(priv, 0x137250, 0x3f, 0); +- +- nv_mask(priv, 0x000200, 0x20, 0); +- usleep_range(20, 30); +- nv_mask(priv, 0x000200, 0x20, 0x20); +- +- nv_wr32(priv, 0x12004c, 0x4); +- nv_wr32(priv, 0x122204, 0x2); +- nv_rd32(priv, 0x122204); +-} +- +-static void +-gk20a_ibus_intr(struct nouveau_subdev *subdev) +-{ +- struct gk20a_ibus_priv *priv = (void *)subdev; +- u32 status0 = nv_rd32(priv, 0x120058); +- +- if (status0 & 0x7) { +- nv_debug(priv, "resetting priv ring\n"); +- gk20a_ibus_init_priv_ring(priv); +- } +- +- /* Acknowledge interrupt */ +- nv_mask(priv, 0x12004c, 0x2, 0x2); +- +- if (!nv_wait(subdev, 0x12004c, 0x3f, 0x00)) +- nv_warn(priv, "timeout waiting for ringmaster ack\n"); +-} +- +-static int +-gk20a_ibus_init(struct nouveau_object *object) +-{ +- struct gk20a_ibus_priv *priv = (void *)object; +- int ret; +- +- ret = _nouveau_ibus_init(object); +- if (ret) +- return ret; +- +- gk20a_ibus_init_priv_ring(priv); +- +- return 0; +-} +- +-static int +-gk20a_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gk20a_ibus_priv *priv; +- int ret; +- +- ret = nouveau_ibus_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->intr = gk20a_ibus_intr; +- return 0; +-} +- +-struct nouveau_oclass +-gk20a_ibus_oclass = { +- .handle = NV_SUBDEV(IBUS, 0xea), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gk20a_ibus_ctor, +- .dtor = _nouveau_ibus_dtor, +- .init = gk20a_ibus_init, +- .fini = _nouveau_ibus_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c +deleted file mode 100644 +index 4e977ff2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nvc0.c ++++ /dev/null +@@ -1,123 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-struct nvc0_ibus_priv { +- struct nouveau_ibus base; +-}; +- +-static void +-nvc0_ibus_intr_hub(struct nvc0_ibus_priv *priv, int i) +-{ +- u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0400)); +- u32 data = nv_rd32(priv, 0x122124 + (i * 0x0400)); +- u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0400)); +- nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat); +- nv_mask(priv, 0x122128 + (i * 0x0400), 0x00000200, 0x00000000); +-} +- +-static void +-nvc0_ibus_intr_rop(struct nvc0_ibus_priv *priv, int i) +-{ +- u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0400)); +- u32 data = nv_rd32(priv, 0x124124 + (i * 0x0400)); +- u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0400)); +- nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat); +- nv_mask(priv, 0x124128 + (i * 0x0400), 0x00000200, 0x00000000); +-} +- +-static void +-nvc0_ibus_intr_gpc(struct nvc0_ibus_priv *priv, int i) +-{ +- u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0400)); +- u32 data = nv_rd32(priv, 0x128124 + (i * 0x0400)); +- u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0400)); +- nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat); +- nv_mask(priv, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000); +-} +- +-static void +-nvc0_ibus_intr(struct nouveau_subdev *subdev) +-{ +- struct nvc0_ibus_priv *priv = (void *)subdev; +- u32 intr0 = nv_rd32(priv, 0x121c58); +- u32 intr1 = nv_rd32(priv, 0x121c5c); +- u32 hubnr = nv_rd32(priv, 0x121c70); +- u32 ropnr = nv_rd32(priv, 0x121c74); +- u32 gpcnr = nv_rd32(priv, 0x121c78); +- u32 i; +- +- for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { +- u32 stat = 0x00000100 << i; +- if (intr0 & stat) { +- nvc0_ibus_intr_hub(priv, i); +- intr0 &= ~stat; +- } +- } +- +- for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { +- u32 stat = 0x00010000 << i; +- if (intr0 & stat) { +- nvc0_ibus_intr_rop(priv, i); +- intr0 &= ~stat; +- } +- } +- +- for (i = 0; intr1 && i < gpcnr; i++) { +- u32 stat = 0x00000001 << i; +- if (intr1 & stat) { +- nvc0_ibus_intr_gpc(priv, i); +- intr1 &= ~stat; +- } +- } +-} +- +-static int +-nvc0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_ibus_priv *priv; +- int ret; +- +- ret = nouveau_ibus_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->intr = nvc0_ibus_intr; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_ibus_oclass = { +- .handle = NV_SUBDEV(IBUS, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_ibus_ctor, +- .dtor = _nouveau_ibus_dtor, +- .init = _nouveau_ibus_init, +- .fini = _nouveau_ibus_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c b/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c +deleted file mode 100644 +index ebef970a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ibus/nve0.c ++++ /dev/null +@@ -1,140 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-struct nve0_ibus_priv { +- struct nouveau_ibus base; +-}; +- +-static void +-nve0_ibus_intr_hub(struct nve0_ibus_priv *priv, int i) +-{ +- u32 addr = nv_rd32(priv, 0x122120 + (i * 0x0800)); +- u32 data = nv_rd32(priv, 0x122124 + (i * 0x0800)); +- u32 stat = nv_rd32(priv, 0x122128 + (i * 0x0800)); +- nv_error(priv, "HUB%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat); +- nv_mask(priv, 0x122128 + (i * 0x0800), 0x00000200, 0x00000000); +-} +- +-static void +-nve0_ibus_intr_rop(struct nve0_ibus_priv *priv, int i) +-{ +- u32 addr = nv_rd32(priv, 0x124120 + (i * 0x0800)); +- u32 data = nv_rd32(priv, 0x124124 + (i * 0x0800)); +- u32 stat = nv_rd32(priv, 0x124128 + (i * 0x0800)); +- nv_error(priv, "ROP%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat); +- nv_mask(priv, 0x124128 + (i * 0x0800), 0x00000200, 0x00000000); +-} +- +-static void +-nve0_ibus_intr_gpc(struct nve0_ibus_priv *priv, int i) +-{ +- u32 addr = nv_rd32(priv, 0x128120 + (i * 0x0800)); +- u32 data = nv_rd32(priv, 0x128124 + (i * 0x0800)); +- u32 stat = nv_rd32(priv, 0x128128 + (i * 0x0800)); +- nv_error(priv, "GPC%d: 0x%06x 0x%08x (0x%08x)\n", i, addr, data, stat); +- nv_mask(priv, 0x128128 + (i * 0x0800), 0x00000200, 0x00000000); +-} +- +-static void +-nve0_ibus_intr(struct nouveau_subdev *subdev) +-{ +- struct nve0_ibus_priv *priv = (void *)subdev; +- u32 intr0 = nv_rd32(priv, 0x120058); +- u32 intr1 = nv_rd32(priv, 0x12005c); +- u32 hubnr = nv_rd32(priv, 0x120070); +- u32 ropnr = nv_rd32(priv, 0x120074); +- u32 gpcnr = nv_rd32(priv, 0x120078); +- u32 i; +- +- for (i = 0; (intr0 & 0x0000ff00) && i < hubnr; i++) { +- u32 stat = 0x00000100 << i; +- if (intr0 & stat) { +- nve0_ibus_intr_hub(priv, i); +- intr0 &= ~stat; +- } +- } +- +- for (i = 0; (intr0 & 0xffff0000) && i < ropnr; i++) { +- u32 stat = 0x00010000 << i; +- if (intr0 & stat) { +- nve0_ibus_intr_rop(priv, i); +- intr0 &= ~stat; +- } +- } +- +- for (i = 0; intr1 && i < gpcnr; i++) { +- u32 stat = 0x00000001 << i; +- if (intr1 & stat) { +- nve0_ibus_intr_gpc(priv, i); +- intr1 &= ~stat; +- } +- } +-} +- +-static int +-nve0_ibus_init(struct nouveau_object *object) +-{ +- struct nve0_ibus_priv *priv = (void *)object; +- int ret = nouveau_ibus_init(&priv->base); +- if (ret == 0) { +- nv_mask(priv, 0x122318, 0x0003ffff, 0x00001000); +- nv_mask(priv, 0x12231c, 0x0003ffff, 0x00000200); +- nv_mask(priv, 0x122310, 0x0003ffff, 0x00000800); +- nv_mask(priv, 0x122348, 0x0003ffff, 0x00000100); +- nv_mask(priv, 0x1223b0, 0x0003ffff, 0x00000fff); +- nv_mask(priv, 0x122348, 0x0003ffff, 0x00000200); +- nv_mask(priv, 0x122358, 0x0003ffff, 0x00002880); +- } +- return ret; +-} +- +-static int +-nve0_ibus_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nve0_ibus_priv *priv; +- int ret; +- +- ret = nouveau_ibus_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->intr = nve0_ibus_intr; +- return 0; +-} +- +-struct nouveau_oclass +-nve0_ibus_oclass = { +- .handle = NV_SUBDEV(IBUS, 0xe0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nve0_ibus_ctor, +- .dtor = _nouveau_ibus_dtor, +- .init = nve0_ibus_init, +- .fini = _nouveau_ibus_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c +deleted file mode 100644 +index 14706d98..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/base.c ++++ /dev/null +@@ -1,157 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-/****************************************************************************** +- * instmem object base implementation +- *****************************************************************************/ +- +-void +-_nouveau_instobj_dtor(struct nouveau_object *object) +-{ +- struct nouveau_instmem *imem = (void *)object->engine; +- struct nouveau_instobj *iobj = (void *)object; +- +- mutex_lock(&nv_subdev(imem)->mutex); +- list_del(&iobj->head); +- mutex_unlock(&nv_subdev(imem)->mutex); +- +- return nouveau_object_destroy(&iobj->base); +-} +- +-int +-nouveau_instobj_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int length, void **pobject) +-{ +- struct nouveau_instmem *imem = (void *)engine; +- struct nouveau_instobj *iobj; +- int ret; +- +- ret = nouveau_object_create_(parent, engine, oclass, NV_MEMOBJ_CLASS, +- length, pobject); +- iobj = *pobject; +- if (ret) +- return ret; +- +- mutex_lock(&imem->base.mutex); +- list_add(&iobj->head, &imem->list); +- mutex_unlock(&imem->base.mutex); +- return 0; +-} +- +-/****************************************************************************** +- * instmem subdev base implementation +- *****************************************************************************/ +- +-static int +-nouveau_instmem_alloc(struct nouveau_instmem *imem, +- struct nouveau_object *parent, u32 size, u32 align, +- struct nouveau_object **pobject) +-{ +- struct nouveau_object *engine = nv_object(imem); +- struct nouveau_instmem_impl *impl = (void *)engine->oclass; +- struct nouveau_instobj_args args = { .size = size, .align = align }; +- return nouveau_object_ctor(parent, engine, impl->instobj, &args, +- sizeof(args), pobject); +-} +- +-int +-_nouveau_instmem_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_instmem *imem = (void *)object; +- struct nouveau_instobj *iobj; +- int i, ret = 0; +- +- if (suspend) { +- mutex_lock(&imem->base.mutex); +- +- list_for_each_entry(iobj, &imem->list, head) { +- iobj->suspend = vmalloc(iobj->size); +- if (!iobj->suspend) { +- ret = -ENOMEM; +- break; +- } +- +- for (i = 0; i < iobj->size; i += 4) +- iobj->suspend[i / 4] = nv_ro32(iobj, i); +- } +- +- mutex_unlock(&imem->base.mutex); +- +- if (ret) +- return ret; +- } +- +- return nouveau_subdev_fini(&imem->base, suspend); +-} +- +-int +-_nouveau_instmem_init(struct nouveau_object *object) +-{ +- struct nouveau_instmem *imem = (void *)object; +- struct nouveau_instobj *iobj; +- int ret, i; +- +- ret = nouveau_subdev_init(&imem->base); +- if (ret) +- return ret; +- +- mutex_lock(&imem->base.mutex); +- +- list_for_each_entry(iobj, &imem->list, head) { +- if (iobj->suspend) { +- for (i = 0; i < iobj->size; i += 4) +- nv_wo32(iobj, i, iobj->suspend[i / 4]); +- vfree(iobj->suspend); +- iobj->suspend = NULL; +- } +- } +- +- mutex_unlock(&imem->base.mutex); +- +- return 0; +-} +- +-int +-nouveau_instmem_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int length, void **pobject) +-{ +- struct nouveau_instmem *imem; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, +- "INSTMEM", "instmem", length, pobject); +- imem = *pobject; +- if (ret) +- return ret; +- +- INIT_LIST_HEAD(&imem->list); +- imem->alloc = nouveau_instmem_alloc; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c +deleted file mode 100644 +index e8b1401c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.c ++++ /dev/null +@@ -1,182 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-/****************************************************************************** +- * instmem object implementation +- *****************************************************************************/ +- +-static u32 +-nv04_instobj_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nv04_instobj_priv *node = (void *)object; +- return nv_ro32(object->engine, node->mem->offset + addr); +-} +- +-static void +-nv04_instobj_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nv04_instobj_priv *node = (void *)object; +- nv_wo32(object->engine, node->mem->offset + addr, data); +-} +- +-static void +-nv04_instobj_dtor(struct nouveau_object *object) +-{ +- struct nv04_instmem_priv *priv = (void *)object->engine; +- struct nv04_instobj_priv *node = (void *)object; +- nouveau_mm_free(&priv->heap, &node->mem); +- nouveau_instobj_destroy(&node->base); +-} +- +-static int +-nv04_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_instmem_priv *priv = (void *)engine; +- struct nv04_instobj_priv *node; +- struct nouveau_instobj_args *args = data; +- int ret; +- +- if (!args->align) +- args->align = 1; +- +- ret = nouveau_instobj_create(parent, engine, oclass, &node); +- *pobject = nv_object(node); +- if (ret) +- return ret; +- +- ret = nouveau_mm_head(&priv->heap, 0, 1, args->size, args->size, +- args->align, &node->mem); +- if (ret) +- return ret; +- +- node->base.addr = node->mem->offset; +- node->base.size = node->mem->length; +- return 0; +-} +- +-struct nouveau_instobj_impl +-nv04_instobj_oclass = { +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_instobj_ctor, +- .dtor = nv04_instobj_dtor, +- .init = _nouveau_instobj_init, +- .fini = _nouveau_instobj_fini, +- .rd32 = nv04_instobj_rd32, +- .wr32 = nv04_instobj_wr32, +- }, +-}; +- +-/****************************************************************************** +- * instmem subdev implementation +- *****************************************************************************/ +- +-static u32 +-nv04_instmem_rd32(struct nouveau_object *object, u64 addr) +-{ +- return nv_rd32(object, 0x700000 + addr); +-} +- +-static void +-nv04_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- return nv_wr32(object, 0x700000 + addr, data); +-} +- +-void +-nv04_instmem_dtor(struct nouveau_object *object) +-{ +- struct nv04_instmem_priv *priv = (void *)object; +- nouveau_gpuobj_ref(NULL, &priv->ramfc); +- nouveau_gpuobj_ref(NULL, &priv->ramro); +- nouveau_ramht_ref(NULL, &priv->ramht); +- nouveau_gpuobj_ref(NULL, &priv->vbios); +- nouveau_mm_fini(&priv->heap); +- if (priv->iomem) +- iounmap(priv->iomem); +- nouveau_instmem_destroy(&priv->base); +-} +- +-static int +-nv04_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_instmem_priv *priv; +- int ret; +- +- ret = nouveau_instmem_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- /* PRAMIN aperture maps over the end of VRAM, reserve it */ +- priv->base.reserved = 512 * 1024; +- +- ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); +- if (ret) +- return ret; +- +- /* 0x00000-0x10000: reserve for probable vbios image */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, +- &priv->vbios); +- if (ret) +- return ret; +- +- /* 0x10000-0x18000: reserve for RAMHT */ +- ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, &priv->ramht); +- if (ret) +- return ret; +- +- /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00800, 0, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); +- if (ret) +- return ret; +- +- /* 0x18800-0x18a00: reserve for RAMRO */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x00200, 0, 0, +- &priv->ramro); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_instmem_oclass = &(struct nouveau_instmem_impl) { +- .base.handle = NV_SUBDEV(INSTMEM, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_instmem_ctor, +- .dtor = nv04_instmem_dtor, +- .init = _nouveau_instmem_init, +- .fini = _nouveau_instmem_fini, +- .rd32 = nv04_instmem_rd32, +- .wr32 = nv04_instmem_wr32, +- }, +- .instobj = &nv04_instobj_oclass.base, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h +deleted file mode 100644 +index 095fbc6f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv04.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-#ifndef __NV04_INSTMEM_H__ +-#define __NV04_INSTMEM_H__ +- +-#include +-#include +-#include +- +-#include "priv.h" +- +-extern struct nouveau_instobj_impl nv04_instobj_oclass; +- +-struct nv04_instmem_priv { +- struct nouveau_instmem base; +- +- void __iomem *iomem; +- struct nouveau_mm heap; +- +- struct nouveau_gpuobj *vbios; +- struct nouveau_ramht *ramht; +- struct nouveau_gpuobj *ramro; +- struct nouveau_gpuobj *ramfc; +-}; +- +-static inline struct nv04_instmem_priv * +-nv04_instmem(void *obj) +-{ +- return (void *)nouveau_instmem(obj); +-} +- +-struct nv04_instobj_priv { +- struct nouveau_instobj base; +- struct nouveau_mm_node *mem; +-}; +- +-void nv04_instmem_dtor(struct nouveau_object *); +- +-int nv04_instmem_alloc(struct nouveau_instmem *, struct nouveau_object *, +- u32 size, u32 align, struct nouveau_object **pobject); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c +deleted file mode 100644 +index 8803809f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv40.c ++++ /dev/null +@@ -1,137 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "nv04.h" +- +-/****************************************************************************** +- * instmem subdev implementation +- *****************************************************************************/ +- +-static u32 +-nv40_instmem_rd32(struct nouveau_object *object, u64 addr) +-{ +- struct nv04_instmem_priv *priv = (void *)object; +- return ioread32_native(priv->iomem + addr); +-} +- +-static void +-nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data) +-{ +- struct nv04_instmem_priv *priv = (void *)object; +- iowrite32_native(data, priv->iomem + addr); +-} +- +-static int +-nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nv04_instmem_priv *priv; +- int ret, bar, vs; +- +- ret = nouveau_instmem_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- /* map bar */ +- if (nv_device_resource_len(device, 2)) +- bar = 2; +- else +- bar = 3; +- +- priv->iomem = ioremap(nv_device_resource_start(device, bar), +- nv_device_resource_len(device, bar)); +- if (!priv->iomem) { +- nv_error(priv, "unable to map PRAMIN BAR\n"); +- return -EFAULT; +- } +- +- /* PRAMIN aperture maps over the end of vram, reserve enough space +- * to fit graphics contexts for every channel, the magics come +- * from engine/graph/nv40.c +- */ +- vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8); +- if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs; +- else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs; +- else if (nv44_graph_class(priv)) priv->base.reserved = 0x4980 * vs; +- else priv->base.reserved = 0x4a40 * vs; +- priv->base.reserved += 16 * 1024; +- priv->base.reserved *= 32; /* per-channel */ +- priv->base.reserved += 512 * 1024; /* pci(e)gart table */ +- priv->base.reserved += 512 * 1024; /* object storage */ +- +- priv->base.reserved = round_up(priv->base.reserved, 4096); +- +- ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1); +- if (ret) +- return ret; +- +- /* 0x00000-0x10000: reserve for probable vbios image */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0, +- &priv->vbios); +- if (ret) +- return ret; +- +- /* 0x10000-0x18000: reserve for RAMHT */ +- ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0, +- &priv->ramht); +- if (ret) +- return ret; +- +- /* 0x18000-0x18200: reserve for RAMRO +- * 0x18200-0x20000: padding +- */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0, +- &priv->ramro); +- if (ret) +- return ret; +- +- /* 0x20000-0x21000: reserve for RAMFC +- * 0x21000-0x40000: padding and some unknown crap +- */ +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0, +- NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-nv40_instmem_oclass = &(struct nouveau_instmem_impl) { +- .base.handle = NV_SUBDEV(INSTMEM, 0x40), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_instmem_ctor, +- .dtor = nv04_instmem_dtor, +- .init = _nouveau_instmem_init, +- .fini = _nouveau_instmem_fini, +- .rd32 = nv40_instmem_rd32, +- .wr32 = nv40_instmem_wr32, +- }, +- .instobj = &nv04_instobj_oclass.base, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c +deleted file mode 100644 +index 7cb3b098..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/nv50.c ++++ /dev/null +@@ -1,171 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "priv.h" +- +-struct nv50_instmem_priv { +- struct nouveau_instmem base; +- spinlock_t lock; +- u64 addr; +-}; +- +-struct nv50_instobj_priv { +- struct nouveau_instobj base; +- struct nouveau_mem *mem; +-}; +- +-/****************************************************************************** +- * instmem object implementation +- *****************************************************************************/ +- +-static u32 +-nv50_instobj_rd32(struct nouveau_object *object, u64 offset) +-{ +- struct nv50_instmem_priv *priv = (void *)object->engine; +- struct nv50_instobj_priv *node = (void *)object; +- unsigned long flags; +- u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; +- u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; +- u32 data; +- +- spin_lock_irqsave(&priv->lock, flags); +- if (unlikely(priv->addr != base)) { +- nv_wr32(priv, 0x001700, base >> 16); +- priv->addr = base; +- } +- data = nv_rd32(priv, 0x700000 + addr); +- spin_unlock_irqrestore(&priv->lock, flags); +- return data; +-} +- +-static void +-nv50_instobj_wr32(struct nouveau_object *object, u64 offset, u32 data) +-{ +- struct nv50_instmem_priv *priv = (void *)object->engine; +- struct nv50_instobj_priv *node = (void *)object; +- unsigned long flags; +- u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; +- u64 addr = (node->mem->offset + offset) & 0x000000fffffULL; +- +- spin_lock_irqsave(&priv->lock, flags); +- if (unlikely(priv->addr != base)) { +- nv_wr32(priv, 0x001700, base >> 16); +- priv->addr = base; +- } +- nv_wr32(priv, 0x700000 + addr, data); +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-static void +-nv50_instobj_dtor(struct nouveau_object *object) +-{ +- struct nv50_instobj_priv *node = (void *)object; +- struct nouveau_fb *pfb = nouveau_fb(object); +- pfb->ram->put(pfb, &node->mem); +- nouveau_instobj_destroy(&node->base); +-} +- +-static int +-nv50_instobj_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nouveau_instobj_args *args = data; +- struct nv50_instobj_priv *node; +- int ret; +- +- args->size = max((args->size + 4095) & ~4095, (u32)4096); +- args->align = max((args->align + 4095) & ~4095, (u32)4096); +- +- ret = nouveau_instobj_create(parent, engine, oclass, &node); +- *pobject = nv_object(node); +- if (ret) +- return ret; +- +- ret = pfb->ram->get(pfb, args->size, args->align, 0, 0x800, &node->mem); +- if (ret) +- return ret; +- +- node->base.addr = node->mem->offset; +- node->base.size = node->mem->size << 12; +- node->mem->page_shift = 12; +- return 0; +-} +- +-static struct nouveau_instobj_impl +-nv50_instobj_oclass = { +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_instobj_ctor, +- .dtor = nv50_instobj_dtor, +- .init = _nouveau_instobj_init, +- .fini = _nouveau_instobj_fini, +- .rd32 = nv50_instobj_rd32, +- .wr32 = nv50_instobj_wr32, +- }, +-}; +- +-/****************************************************************************** +- * instmem subdev implementation +- *****************************************************************************/ +- +-static int +-nv50_instmem_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv50_instmem_priv *priv = (void *)object; +- priv->addr = ~0ULL; +- return nouveau_instmem_fini(&priv->base, suspend); +-} +- +-static int +-nv50_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_instmem_priv *priv; +- int ret; +- +- ret = nouveau_instmem_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-struct nouveau_oclass * +-nv50_instmem_oclass = &(struct nouveau_instmem_impl) { +- .base.handle = NV_SUBDEV(INSTMEM, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_instmem_ctor, +- .dtor = _nouveau_instmem_dtor, +- .init = _nouveau_instmem_init, +- .fini = nv50_instmem_fini, +- }, +- .instobj = &nv50_instobj_oclass.base, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h b/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h +deleted file mode 100644 +index 8d67dedc..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/instmem/priv.h ++++ /dev/null +@@ -1,56 +0,0 @@ +-#ifndef __NVKM_INSTMEM_PRIV_H__ +-#define __NVKM_INSTMEM_PRIV_H__ +- +-#include +- +-struct nouveau_instobj_impl { +- struct nouveau_oclass base; +-}; +- +-struct nouveau_instobj_args { +- u32 size; +- u32 align; +-}; +- +-#define nouveau_instobj_create(p,e,o,d) \ +- nouveau_instobj_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_instobj_destroy(p) ({ \ +- struct nouveau_instobj *iobj = (p); \ +- _nouveau_instobj_dtor(nv_object(iobj)); \ +-}) +-#define nouveau_instobj_init(p) \ +- nouveau_object_init(&(p)->base) +-#define nouveau_instobj_fini(p,s) \ +- nouveau_object_fini(&(p)->base, (s)) +- +-int nouveau_instobj_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_instobj_dtor(struct nouveau_object *); +-#define _nouveau_instobj_init nouveau_object_init +-#define _nouveau_instobj_fini nouveau_object_fini +- +-struct nouveau_instmem_impl { +- struct nouveau_oclass base; +- struct nouveau_oclass *instobj; +-}; +- +-#define nouveau_instmem_create(p,e,o,d) \ +- nouveau_instmem_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_instmem_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_instmem_init(p) ({ \ +- struct nouveau_instmem *imem = (p); \ +- _nouveau_instmem_init(nv_object(imem)); \ +-}) +-#define nouveau_instmem_fini(p,s) ({ \ +- struct nouveau_instmem *imem = (p); \ +- _nouveau_instmem_fini(nv_object(imem), (s)); \ +-}) +- +-int nouveau_instmem_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-#define _nouveau_instmem_dtor _nouveau_subdev_dtor +-int _nouveau_instmem_init(struct nouveau_object *); +-int _nouveau_instmem_fini(struct nouveau_object *, bool); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c +deleted file mode 100644 +index 7fa33151..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/base.c ++++ /dev/null +@@ -1,126 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-nvkm_ltc_tags_alloc(struct nouveau_ltc *ltc, u32 n, +- struct nouveau_mm_node **pnode) +-{ +- struct nvkm_ltc_priv *priv = (void *)ltc; +- int ret; +- +- ret = nouveau_mm_head(&priv->tags, 0, 1, n, n, 1, pnode); +- if (ret) +- *pnode = NULL; +- +- return ret; +-} +- +-static void +-nvkm_ltc_tags_free(struct nouveau_ltc *ltc, struct nouveau_mm_node **pnode) +-{ +- struct nvkm_ltc_priv *priv = (void *)ltc; +- nouveau_mm_free(&priv->tags, pnode); +-} +- +-static void +-nvkm_ltc_tags_clear(struct nouveau_ltc *ltc, u32 first, u32 count) +-{ +- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); +- struct nvkm_ltc_priv *priv = (void *)ltc; +- const u32 limit = first + count - 1; +- +- BUG_ON((first > limit) || (limit >= priv->num_tags)); +- +- impl->cbc_clear(priv, first, limit); +- impl->cbc_wait(priv); +-} +- +-static int +-nvkm_ltc_zbc_color_get(struct nouveau_ltc *ltc, int index, const u32 color[4]) +-{ +- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); +- struct nvkm_ltc_priv *priv = (void *)ltc; +- memcpy(priv->zbc_color[index], color, sizeof(priv->zbc_color[index])); +- impl->zbc_clear_color(priv, index, color); +- return index; +-} +- +-static int +-nvkm_ltc_zbc_depth_get(struct nouveau_ltc *ltc, int index, const u32 depth) +-{ +- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(ltc); +- struct nvkm_ltc_priv *priv = (void *)ltc; +- priv->zbc_depth[index] = depth; +- impl->zbc_clear_depth(priv, index, depth); +- return index; +-} +- +-int +-_nvkm_ltc_init(struct nouveau_object *object) +-{ +- const struct nvkm_ltc_impl *impl = (void *)nv_oclass(object); +- struct nvkm_ltc_priv *priv = (void *)object; +- int ret, i; +- +- ret = nouveau_subdev_init(&priv->base.base); +- if (ret) +- return ret; +- +- for (i = priv->base.zbc_min; i <= priv->base.zbc_max; i++) { +- impl->zbc_clear_color(priv, i, priv->zbc_color[i]); +- impl->zbc_clear_depth(priv, i, priv->zbc_depth[i]); +- } +- +- return 0; +-} +- +-int +-nvkm_ltc_create_(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- const struct nvkm_ltc_impl *impl = (void *)oclass; +- struct nvkm_ltc_priv *priv; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PLTCG", +- "l2c", length, pobject); +- priv = *pobject; +- if (ret) +- return ret; +- +- memset(priv->zbc_color, 0x00, sizeof(priv->zbc_color)); +- memset(priv->zbc_depth, 0x00, sizeof(priv->zbc_depth)); +- +- priv->base.base.intr = impl->intr; +- priv->base.tags_alloc = nvkm_ltc_tags_alloc; +- priv->base.tags_free = nvkm_ltc_tags_free; +- priv->base.tags_clear = nvkm_ltc_tags_clear; +- priv->base.zbc_min = 1; /* reserve 0 for disabled */ +- priv->base.zbc_max = min(impl->zbc, NOUVEAU_LTC_MAX_ZBC_CNT) - 1; +- priv->base.zbc_color_get = nvkm_ltc_zbc_color_get; +- priv->base.zbc_depth_get = nvkm_ltc_zbc_depth_get; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c +deleted file mode 100644 +index 2db09772..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gf100.c ++++ /dev/null +@@ -1,236 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "priv.h" +- +-void +-gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) +-{ +- nv_wr32(priv, 0x17e8cc, start); +- nv_wr32(priv, 0x17e8d0, limit); +- nv_wr32(priv, 0x17e8c8, 0x00000004); +-} +- +-void +-gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv) +-{ +- int c, s; +- for (c = 0; c < priv->ltc_nr; c++) { +- for (s = 0; s < priv->lts_nr; s++) +- nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0); +- } +-} +- +-void +-gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) +-{ +- nv_mask(priv, 0x17ea44, 0x0000000f, i); +- nv_wr32(priv, 0x17ea48, color[0]); +- nv_wr32(priv, 0x17ea4c, color[1]); +- nv_wr32(priv, 0x17ea50, color[2]); +- nv_wr32(priv, 0x17ea54, color[3]); +-} +- +-void +-gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) +-{ +- nv_mask(priv, 0x17ea44, 0x0000000f, i); +- nv_wr32(priv, 0x17ea58, depth); +-} +- +-static const struct nouveau_bitfield +-gf100_ltc_lts_intr_name[] = { +- { 0x00000001, "IDLE_ERROR_IQ" }, +- { 0x00000002, "IDLE_ERROR_CBC" }, +- { 0x00000004, "IDLE_ERROR_TSTG" }, +- { 0x00000008, "IDLE_ERROR_DSTG" }, +- { 0x00000010, "EVICTED_CB" }, +- { 0x00000020, "ILLEGAL_COMPSTAT" }, +- { 0x00000040, "BLOCKLINEAR_CB" }, +- { 0x00000100, "ECC_SEC_ERROR" }, +- { 0x00000200, "ECC_DED_ERROR" }, +- { 0x00000400, "DEBUG" }, +- { 0x00000800, "ATOMIC_TO_Z" }, +- { 0x00001000, "ILLEGAL_ATOMIC" }, +- { 0x00002000, "BLKACTIVITY_ERR" }, +- {} +-}; +- +-static void +-gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts) +-{ +- u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400); +- u32 intr = nv_rd32(priv, base + 0x020); +- u32 stat = intr & 0x0000ffff; +- +- if (stat) { +- nv_info(priv, "LTC%d_LTS%d:", ltc, lts); +- nouveau_bitfield_print(gf100_ltc_lts_intr_name, stat); +- pr_cont("\n"); +- } +- +- nv_wr32(priv, base + 0x020, intr); +-} +- +-void +-gf100_ltc_intr(struct nouveau_subdev *subdev) +-{ +- struct nvkm_ltc_priv *priv = (void *)subdev; +- u32 mask; +- +- mask = nv_rd32(priv, 0x00017c); +- while (mask) { +- u32 lts, ltc = __ffs(mask); +- for (lts = 0; lts < priv->lts_nr; lts++) +- gf100_ltc_lts_intr(priv, ltc, lts); +- mask &= ~(1 << ltc); +- } +-} +- +-static int +-gf100_ltc_init(struct nouveau_object *object) +-{ +- struct nvkm_ltc_priv *priv = (void *)object; +- u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); +- int ret; +- +- ret = nvkm_ltc_init(priv); +- if (ret) +- return ret; +- +- nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ +- nv_wr32(priv, 0x17e8d8, priv->ltc_nr); +- nv_wr32(priv, 0x17e8d4, priv->tag_base); +- nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); +- return 0; +-} +- +-void +-gf100_ltc_dtor(struct nouveau_object *object) +-{ +- struct nouveau_fb *pfb = nouveau_fb(object); +- struct nvkm_ltc_priv *priv = (void *)object; +- +- nouveau_mm_fini(&priv->tags); +- nouveau_mm_free(&pfb->vram, &priv->tag_ram); +- +- nvkm_ltc_destroy(priv); +-} +- +-/* TODO: Figure out tag memory details and drop the over-cautious allocation. +- */ +-int +-gf100_ltc_init_tag_ram(struct nouveau_fb *pfb, struct nvkm_ltc_priv *priv) +-{ +- u32 tag_size, tag_margin, tag_align; +- int ret; +- +- /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ +- priv->num_tags = (pfb->ram->size >> 17) / 4; +- if (priv->num_tags > (1 << 17)) +- priv->num_tags = 1 << 17; /* we have 17 bits in PTE */ +- priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */ +- +- tag_align = priv->ltc_nr * 0x800; +- tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align; +- +- /* 4 part 4 sub: 0x2000 bytes for 56 tags */ +- /* 3 part 4 sub: 0x6000 bytes for 168 tags */ +- /* +- * About 147 bytes per tag. Let's be safe and allocate x2, which makes +- * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags. +- * +- * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %. +- */ +- tag_size = (priv->num_tags / 64) * 0x6000 + tag_margin; +- tag_size += tag_align; +- tag_size = (tag_size + 0xfff) >> 12; /* round up */ +- +- ret = nouveau_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, +- &priv->tag_ram); +- if (ret) { +- priv->num_tags = 0; +- } else { +- u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin; +- +- tag_base += tag_align - 1; +- ret = do_div(tag_base, tag_align); +- +- priv->tag_base = tag_base; +- } +- +- ret = nouveau_mm_init(&priv->tags, 0, priv->num_tags, 1); +- return ret; +-} +- +-int +-gf100_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nvkm_ltc_priv *priv; +- u32 parts, mask; +- int ret, i; +- +- ret = nvkm_ltc_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- parts = nv_rd32(priv, 0x022438); +- mask = nv_rd32(priv, 0x022554); +- for (i = 0; i < parts; i++) { +- if (!(mask & (1 << i))) +- priv->ltc_nr++; +- } +- priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; +- +- ret = gf100_ltc_init_tag_ram(pfb, priv); +- if (ret) +- return ret; +- +- nv_subdev(priv)->intr = gf100_ltc_intr; +- return 0; +-} +- +-struct nouveau_oclass * +-gf100_ltc_oclass = &(struct nvkm_ltc_impl) { +- .base.handle = NV_SUBDEV(LTC, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gf100_ltc_ctor, +- .dtor = gf100_ltc_dtor, +- .init = gf100_ltc_init, +- .fini = _nvkm_ltc_fini, +- }, +- .intr = gf100_ltc_intr, +- .cbc_clear = gf100_ltc_cbc_clear, +- .cbc_wait = gf100_ltc_cbc_wait, +- .zbc = 16, +- .zbc_clear_color = gf100_ltc_zbc_clear_color, +- .zbc_clear_depth = gf100_ltc_zbc_clear_depth, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c +deleted file mode 100644 +index b39b5d0e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gk104.c ++++ /dev/null +@@ -1,60 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-gk104_ltc_init(struct nouveau_object *object) +-{ +- struct nvkm_ltc_priv *priv = (void *)object; +- u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); +- int ret; +- +- ret = nvkm_ltc_init(priv); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x17e8d8, priv->ltc_nr); +- nv_wr32(priv, 0x17e000, priv->ltc_nr); +- nv_wr32(priv, 0x17e8d4, priv->tag_base); +- nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); +- return 0; +-} +- +-struct nouveau_oclass * +-gk104_ltc_oclass = &(struct nvkm_ltc_impl) { +- .base.handle = NV_SUBDEV(LTC, 0xe4), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gf100_ltc_ctor, +- .dtor = gf100_ltc_dtor, +- .init = gk104_ltc_init, +- .fini = _nvkm_ltc_fini, +- }, +- .intr = gf100_ltc_intr, +- .cbc_clear = gf100_ltc_cbc_clear, +- .cbc_wait = gf100_ltc_cbc_wait, +- .zbc = 16, +- .zbc_clear_color = gf100_ltc_zbc_clear_color, +- .zbc_clear_depth = gf100_ltc_zbc_clear_depth, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c +deleted file mode 100644 +index 89fc4238..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/gm107.c ++++ /dev/null +@@ -1,154 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "priv.h" +- +-static void +-gm107_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) +-{ +- nv_wr32(priv, 0x17e270, start); +- nv_wr32(priv, 0x17e274, limit); +- nv_wr32(priv, 0x17e26c, 0x00000004); +-} +- +-static void +-gm107_ltc_cbc_wait(struct nvkm_ltc_priv *priv) +-{ +- int c, s; +- for (c = 0; c < priv->ltc_nr; c++) { +- for (s = 0; s < priv->lts_nr; s++) +- nv_wait(priv, 0x14046c + c * 0x2000 + s * 0x200, ~0, 0); +- } +-} +- +-static void +-gm107_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) +-{ +- nv_mask(priv, 0x17e338, 0x0000000f, i); +- nv_wr32(priv, 0x17e33c, color[0]); +- nv_wr32(priv, 0x17e340, color[1]); +- nv_wr32(priv, 0x17e344, color[2]); +- nv_wr32(priv, 0x17e348, color[3]); +-} +- +-static void +-gm107_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) +-{ +- nv_mask(priv, 0x17e338, 0x0000000f, i); +- nv_wr32(priv, 0x17e34c, depth); +-} +- +-static void +-gm107_ltc_lts_isr(struct nvkm_ltc_priv *priv, int ltc, int lts) +-{ +- u32 base = 0x140000 + (ltc * 0x2000) + (lts * 0x400); +- u32 stat = nv_rd32(priv, base + 0x00c); +- +- if (stat) { +- nv_info(priv, "LTC%d_LTS%d: 0x%08x\n", ltc, lts, stat); +- nv_wr32(priv, base + 0x00c, stat); +- } +-} +- +-static void +-gm107_ltc_intr(struct nouveau_subdev *subdev) +-{ +- struct nvkm_ltc_priv *priv = (void *)subdev; +- u32 mask; +- +- mask = nv_rd32(priv, 0x00017c); +- while (mask) { +- u32 lts, ltc = __ffs(mask); +- for (lts = 0; lts < priv->lts_nr; lts++) +- gm107_ltc_lts_isr(priv, ltc, lts); +- mask &= ~(1 << ltc); +- } +-} +- +-static int +-gm107_ltc_init(struct nouveau_object *object) +-{ +- struct nvkm_ltc_priv *priv = (void *)object; +- u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); +- int ret; +- +- ret = nvkm_ltc_init(priv); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x17e27c, priv->ltc_nr); +- nv_wr32(priv, 0x17e278, priv->tag_base); +- nv_mask(priv, 0x17e264, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); +- return 0; +-} +- +-static int +-gm107_ltc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_fb *pfb = nouveau_fb(parent); +- struct nvkm_ltc_priv *priv; +- u32 parts, mask; +- int ret, i; +- +- ret = nvkm_ltc_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- parts = nv_rd32(priv, 0x022438); +- mask = nv_rd32(priv, 0x021c14); +- for (i = 0; i < parts; i++) { +- if (!(mask & (1 << i))) +- priv->ltc_nr++; +- } +- priv->lts_nr = nv_rd32(priv, 0x17e280) >> 28; +- +- ret = gf100_ltc_init_tag_ram(pfb, priv); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-gm107_ltc_oclass = &(struct nvkm_ltc_impl) { +- .base.handle = NV_SUBDEV(LTC, 0xff), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gm107_ltc_ctor, +- .dtor = gf100_ltc_dtor, +- .init = gm107_ltc_init, +- .fini = _nvkm_ltc_fini, +- }, +- .intr = gm107_ltc_intr, +- .cbc_clear = gm107_ltc_cbc_clear, +- .cbc_wait = gm107_ltc_cbc_wait, +- .zbc = 16, +- .zbc_clear_color = gm107_ltc_zbc_clear_color, +- .zbc_clear_depth = gm107_ltc_zbc_clear_depth, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h +deleted file mode 100644 +index 41f179d9..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/ltc/priv.h ++++ /dev/null +@@ -1,71 +0,0 @@ +-#ifndef __NVKM_LTC_PRIV_H__ +-#define __NVKM_LTC_PRIV_H__ +- +-#include +-#include +- +-#include +- +-struct nvkm_ltc_priv { +- struct nouveau_ltc base; +- u32 ltc_nr; +- u32 lts_nr; +- +- u32 num_tags; +- u32 tag_base; +- struct nouveau_mm tags; +- struct nouveau_mm_node *tag_ram; +- +- u32 zbc_color[NOUVEAU_LTC_MAX_ZBC_CNT][4]; +- u32 zbc_depth[NOUVEAU_LTC_MAX_ZBC_CNT]; +-}; +- +-#define nvkm_ltc_create(p,e,o,d) \ +- nvkm_ltc_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nvkm_ltc_destroy(p) ({ \ +- struct nvkm_ltc_priv *_priv = (p); \ +- _nvkm_ltc_dtor(nv_object(_priv)); \ +-}) +-#define nvkm_ltc_init(p) ({ \ +- struct nvkm_ltc_priv *_priv = (p); \ +- _nvkm_ltc_init(nv_object(_priv)); \ +-}) +-#define nvkm_ltc_fini(p,s) ({ \ +- struct nvkm_ltc_priv *_priv = (p); \ +- _nvkm_ltc_fini(nv_object(_priv), (s)); \ +-}) +- +-int nvkm_ltc_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +- +-#define _nvkm_ltc_dtor _nouveau_subdev_dtor +-int _nvkm_ltc_init(struct nouveau_object *); +-#define _nvkm_ltc_fini _nouveau_subdev_fini +- +-int gf100_ltc_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void gf100_ltc_dtor(struct nouveau_object *); +-int gf100_ltc_init_tag_ram(struct nouveau_fb *, struct nvkm_ltc_priv *); +-int gf100_ltc_tags_alloc(struct nouveau_ltc *, u32, struct nouveau_mm_node **); +-void gf100_ltc_tags_free(struct nouveau_ltc *, struct nouveau_mm_node **); +- +-struct nvkm_ltc_impl { +- struct nouveau_oclass base; +- void (*intr)(struct nouveau_subdev *); +- +- void (*cbc_clear)(struct nvkm_ltc_priv *, u32 start, u32 limit); +- void (*cbc_wait)(struct nvkm_ltc_priv *); +- +- int zbc; +- void (*zbc_clear_color)(struct nvkm_ltc_priv *, int, const u32[4]); +- void (*zbc_clear_depth)(struct nvkm_ltc_priv *, int, const u32); +-}; +- +-void gf100_ltc_intr(struct nouveau_subdev *); +-void gf100_ltc_cbc_clear(struct nvkm_ltc_priv *, u32, u32); +-void gf100_ltc_cbc_wait(struct nvkm_ltc_priv *); +-void gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *, int, const u32[4]); +-void gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *, int, const u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c b/drivers/gpu/drm/nouveau/core/subdev/mc/base.c +deleted file mode 100644 +index ca7cee3a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/base.c ++++ /dev/null +@@ -1,169 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +-#include +- +-static inline void +-nouveau_mc_unk260(struct nouveau_mc *pmc, u32 data) +-{ +- const struct nouveau_mc_oclass *impl = (void *)nv_oclass(pmc); +- if (impl->unk260) +- impl->unk260(pmc, data); +-} +- +-static inline u32 +-nouveau_mc_intr_mask(struct nouveau_mc *pmc) +-{ +- u32 intr = nv_rd32(pmc, 0x000100); +- if (intr == 0xffffffff) /* likely fallen off the bus */ +- intr = 0x00000000; +- return intr; +-} +- +-static irqreturn_t +-nouveau_mc_intr(int irq, void *arg) +-{ +- struct nouveau_mc *pmc = arg; +- const struct nouveau_mc_oclass *oclass = (void *)nv_object(pmc)->oclass; +- const struct nouveau_mc_intr *map = oclass->intr; +- struct nouveau_subdev *unit; +- u32 intr; +- +- nv_wr32(pmc, 0x000140, 0x00000000); +- nv_rd32(pmc, 0x000140); +- intr = nouveau_mc_intr_mask(pmc); +- if (pmc->use_msi) +- oclass->msi_rearm(pmc); +- +- if (intr) { +- u32 stat = intr = nouveau_mc_intr_mask(pmc); +- while (map->stat) { +- if (intr & map->stat) { +- unit = nouveau_subdev(pmc, map->unit); +- if (unit && unit->intr) +- unit->intr(unit); +- stat &= ~map->stat; +- } +- map++; +- } +- +- if (stat) +- nv_error(pmc, "unknown intr 0x%08x\n", stat); +- } +- +- nv_wr32(pmc, 0x000140, 0x00000001); +- return intr ? IRQ_HANDLED : IRQ_NONE; +-} +- +-int +-_nouveau_mc_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_mc *pmc = (void *)object; +- nv_wr32(pmc, 0x000140, 0x00000000); +- return nouveau_subdev_fini(&pmc->base, suspend); +-} +- +-int +-_nouveau_mc_init(struct nouveau_object *object) +-{ +- struct nouveau_mc *pmc = (void *)object; +- int ret = nouveau_subdev_init(&pmc->base); +- if (ret) +- return ret; +- nv_wr32(pmc, 0x000140, 0x00000001); +- return 0; +-} +- +-void +-_nouveau_mc_dtor(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nouveau_mc *pmc = (void *)object; +- free_irq(pmc->irq, pmc); +- if (pmc->use_msi) +- pci_disable_msi(device->pdev); +- nouveau_subdev_destroy(&pmc->base); +-} +- +-int +-nouveau_mc_create_(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *bclass, int length, void **pobject) +-{ +- const struct nouveau_mc_oclass *oclass = (void *)bclass; +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_mc *pmc; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, bclass, 0, "PMC", +- "master", length, pobject); +- pmc = *pobject; +- if (ret) +- return ret; +- +- pmc->unk260 = nouveau_mc_unk260; +- +- if (nv_device_is_pci(device)) +- switch (device->pdev->device & 0x0ff0) { +- case 0x00f0: +- case 0x02e0: +- /* BR02? NFI how these would be handled yet exactly */ +- break; +- default: +- switch (device->chipset) { +- case 0xaa: +- /* reported broken, nv also disable it */ +- break; +- default: +- pmc->use_msi = true; +- break; +- } +- +- pmc->use_msi = nouveau_boolopt(device->cfgopt, "NvMSI", +- pmc->use_msi); +- +- if (pmc->use_msi && oclass->msi_rearm) { +- pmc->use_msi = pci_enable_msi(device->pdev) == 0; +- if (pmc->use_msi) { +- nv_info(pmc, "MSI interrupts enabled\n"); +- oclass->msi_rearm(pmc); +- } +- } else { +- pmc->use_msi = false; +- } +- } +- +- ret = nv_device_get_irq(device, true); +- if (ret < 0) +- return ret; +- pmc->irq = ret; +- +- ret = request_irq(pmc->irq, nouveau_mc_intr, IRQF_SHARED, "nouveau", +- pmc); +- +- if (ret < 0) +- return ret; +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c +deleted file mode 100644 +index b8d6cb43..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/gk20a.c ++++ /dev/null +@@ -1,38 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-gk20a_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0xea), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv50_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nvc0_mc_intr, +- .msi_rearm = nv40_mc_msi_rearm, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c +deleted file mode 100644 +index 2d787e4d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.c ++++ /dev/null +@@ -1,79 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-const struct nouveau_mc_intr +-nv04_mc_intr[] = { +- { 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */ +- { 0x00000100, NVDEV_ENGINE_FIFO }, +- { 0x00001000, NVDEV_ENGINE_GR }, +- { 0x00010000, NVDEV_ENGINE_DISP }, +- { 0x00020000, NVDEV_ENGINE_VP }, /* NV40- */ +- { 0x00100000, NVDEV_SUBDEV_TIMER }, +- { 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */ +- { 0x02000000, NVDEV_ENGINE_DISP }, /* NV11- PCRTC1 */ +- { 0x10000000, NVDEV_SUBDEV_BUS }, +- { 0x80000000, NVDEV_ENGINE_SW }, +- {} +-}; +- +-int +-nv04_mc_init(struct nouveau_object *object) +-{ +- struct nv04_mc_priv *priv = (void *)object; +- +- nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ +- nv_wr32(priv, 0x001850, 0x00000001); /* disable rom access */ +- +- return nouveau_mc_init(&priv->base); +-} +- +-int +-nv04_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_mc_priv *priv; +- int ret; +- +- ret = nouveau_mc_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass * +-nv04_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x04), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv04_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv04_mc_intr, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h +deleted file mode 100644 +index 4d9ea46c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv04.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-#ifndef __NVKM_MC_NV04_H__ +-#define __NVKM_MC_NV04_H__ +- +-#include "priv.h" +- +-struct nv04_mc_priv { +- struct nouveau_mc base; +-}; +- +-int nv04_mc_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +- +-extern const struct nouveau_mc_intr nv04_mc_intr[]; +-int nv04_mc_init(struct nouveau_object *); +-void nv40_mc_msi_rearm(struct nouveau_mc *); +-int nv44_mc_init(struct nouveau_object *object); +-int nv50_mc_init(struct nouveau_object *); +-extern const struct nouveau_mc_intr nv50_mc_intr[]; +-extern const struct nouveau_mc_intr nvc0_mc_intr[]; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c +deleted file mode 100644 +index 5b1faecf..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv40.c ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-void +-nv40_mc_msi_rearm(struct nouveau_mc *pmc) +-{ +- struct nv04_mc_priv *priv = (void *)pmc; +- nv_wr08(priv, 0x088068, 0xff); +-} +- +-struct nouveau_oclass * +-nv40_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x40), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv04_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv04_mc_intr, +- .msi_rearm = nv40_mc_msi_rearm, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c +deleted file mode 100644 +index cc4d0d2d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv44.c ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-int +-nv44_mc_init(struct nouveau_object *object) +-{ +- struct nv04_mc_priv *priv = (void *)object; +- u32 tmp = nv_rd32(priv, 0x10020c); +- +- nv_wr32(priv, 0x000200, 0xffffffff); /* everything enabled */ +- +- nv_wr32(priv, 0x001700, tmp); +- nv_wr32(priv, 0x001704, 0); +- nv_wr32(priv, 0x001708, 0); +- nv_wr32(priv, 0x00170c, tmp); +- +- return nouveau_mc_init(&priv->base); +-} +- +-struct nouveau_oclass * +-nv44_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x44), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv44_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv04_mc_intr, +- .msi_rearm = nv40_mc_msi_rearm, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c +deleted file mode 100644 +index 165401c4..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv4c.c ++++ /dev/null +@@ -1,37 +0,0 @@ +-/* +- * Copyright 2014 Ilia Mirkin +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ilia Mirkin +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv4c_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x4c), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv44_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv04_mc_intr, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c +deleted file mode 100644 +index 9ca93e27..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv50.c ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-const struct nouveau_mc_intr +-nv50_mc_intr[] = { +- { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP before FIFO, so pageflip-timestamping works! */ +- { 0x00000001, NVDEV_ENGINE_MPEG }, +- { 0x00000100, NVDEV_ENGINE_FIFO }, +- { 0x00001000, NVDEV_ENGINE_GR }, +- { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84- */ +- { 0x00008000, NVDEV_ENGINE_BSP }, /* NV84- */ +- { 0x00020000, NVDEV_ENGINE_VP }, /* NV84- */ +- { 0x00100000, NVDEV_SUBDEV_TIMER }, +- { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ +- { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ +- { 0x10000000, NVDEV_SUBDEV_BUS }, +- { 0x80000000, NVDEV_ENGINE_SW }, +- { 0x0002d101, NVDEV_SUBDEV_FB }, +- {}, +-}; +- +-static void +-nv50_mc_msi_rearm(struct nouveau_mc *pmc) +-{ +- struct nouveau_device *device = nv_device(pmc); +- pci_write_config_byte(device->pdev, 0x68, 0xff); +-} +- +-int +-nv50_mc_init(struct nouveau_object *object) +-{ +- struct nv04_mc_priv *priv = (void *)object; +- nv_wr32(priv, 0x000200, 0xffffffff); /* everything on */ +- return nouveau_mc_init(&priv->base); +-} +- +-struct nouveau_oclass * +-nv50_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x50), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv50_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv50_mc_intr, +- .msi_rearm = nv50_mc_msi_rearm, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c +deleted file mode 100644 +index 5f454110..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv94.c ++++ /dev/null +@@ -1,38 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nv94_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x94), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv50_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv50_mc_intr, +- .msi_rearm = nv40_mc_msi_rearm, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c +deleted file mode 100644 +index 3c76d903..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nv98.c ++++ /dev/null +@@ -1,59 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-static const struct nouveau_mc_intr +-nv98_mc_intr[] = { +- { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work */ +- { 0x00000001, NVDEV_ENGINE_PPP }, +- { 0x00000100, NVDEV_ENGINE_FIFO }, +- { 0x00001000, NVDEV_ENGINE_GR }, +- { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */ +- { 0x00008000, NVDEV_ENGINE_BSP }, +- { 0x00020000, NVDEV_ENGINE_VP }, +- { 0x00040000, NVDEV_SUBDEV_PWR }, /* NVA3:NVC0 */ +- { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */ +- { 0x00100000, NVDEV_SUBDEV_TIMER }, +- { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ +- { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ +- { 0x00400000, NVDEV_ENGINE_COPY0 }, /* NVA3- */ +- { 0x10000000, NVDEV_SUBDEV_BUS }, +- { 0x80000000, NVDEV_ENGINE_SW }, +- { 0x0042d101, NVDEV_SUBDEV_FB }, +- {}, +-}; +- +-struct nouveau_oclass * +-nv98_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0x98), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv50_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nv98_mc_intr, +- .msi_rearm = nv40_mc_msi_rearm, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c +deleted file mode 100644 +index 15d41dc1..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc0.c ++++ /dev/null +@@ -1,77 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-const struct nouveau_mc_intr +-nvc0_mc_intr[] = { +- { 0x04000000, NVDEV_ENGINE_DISP }, /* DISP first, so pageflip timestamps work. */ +- { 0x00000001, NVDEV_ENGINE_PPP }, +- { 0x00000020, NVDEV_ENGINE_COPY0 }, +- { 0x00000040, NVDEV_ENGINE_COPY1 }, +- { 0x00000080, NVDEV_ENGINE_COPY2 }, +- { 0x00000100, NVDEV_ENGINE_FIFO }, +- { 0x00001000, NVDEV_ENGINE_GR }, +- { 0x00002000, NVDEV_SUBDEV_FB }, +- { 0x00008000, NVDEV_ENGINE_BSP }, +- { 0x00040000, NVDEV_SUBDEV_THERM }, +- { 0x00020000, NVDEV_ENGINE_VP }, +- { 0x00100000, NVDEV_SUBDEV_TIMER }, +- { 0x00200000, NVDEV_SUBDEV_GPIO }, /* PMGR->GPIO */ +- { 0x00200000, NVDEV_SUBDEV_I2C }, /* PMGR->I2C/AUX */ +- { 0x01000000, NVDEV_SUBDEV_PWR }, +- { 0x02000000, NVDEV_SUBDEV_LTC }, +- { 0x08000000, NVDEV_SUBDEV_FB }, +- { 0x10000000, NVDEV_SUBDEV_BUS }, +- { 0x40000000, NVDEV_SUBDEV_IBUS }, +- { 0x80000000, NVDEV_ENGINE_SW }, +- {}, +-}; +- +-static void +-nvc0_mc_msi_rearm(struct nouveau_mc *pmc) +-{ +- struct nv04_mc_priv *priv = (void *)pmc; +- nv_wr32(priv, 0x088704, 0x00000000); +-} +- +-void +-nvc0_mc_unk260(struct nouveau_mc *pmc, u32 data) +-{ +- nv_wr32(pmc, 0x000260, data); +-} +- +-struct nouveau_oclass * +-nvc0_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv50_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nvc0_mc_intr, +- .msi_rearm = nvc0_mc_msi_rearm, +- .unk260 = nvc0_mc_unk260, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c b/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c +deleted file mode 100644 +index 68b5f61a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/nvc3.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-struct nouveau_oclass * +-nvc3_mc_oclass = &(struct nouveau_mc_oclass) { +- .base.handle = NV_SUBDEV(MC, 0xc3), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_mc_ctor, +- .dtor = _nouveau_mc_dtor, +- .init = nv50_mc_init, +- .fini = _nouveau_mc_fini, +- }, +- .intr = nvc0_mc_intr, +- .msi_rearm = nv40_mc_msi_rearm, +- .unk260 = nvc0_mc_unk260, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h b/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h +deleted file mode 100644 +index 911e6639..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mc/priv.h ++++ /dev/null +@@ -1,38 +0,0 @@ +-#ifndef __NVKM_MC_PRIV_H__ +-#define __NVKM_MC_PRIV_H__ +- +-#include +- +-#define nouveau_mc_create(p,e,o,d) \ +- nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_mc_destroy(p) ({ \ +- struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \ +-}) +-#define nouveau_mc_init(p) ({ \ +- struct nouveau_mc *pmc = (p); _nouveau_mc_init(nv_object(pmc)); \ +-}) +-#define nouveau_mc_fini(p,s) ({ \ +- struct nouveau_mc *pmc = (p); _nouveau_mc_fini(nv_object(pmc), (s)); \ +-}) +- +-int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +-void _nouveau_mc_dtor(struct nouveau_object *); +-int _nouveau_mc_init(struct nouveau_object *); +-int _nouveau_mc_fini(struct nouveau_object *, bool); +- +-struct nouveau_mc_intr { +- u32 stat; +- u32 unit; +-}; +- +-struct nouveau_mc_oclass { +- struct nouveau_oclass base; +- const struct nouveau_mc_intr *intr; +- void (*msi_rearm)(struct nouveau_mc *); +- void (*unk260)(struct nouveau_mc *, u32); +-}; +- +-void nvc0_mc_unk260(struct nouveau_mc *, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c +deleted file mode 100644 +index 51fcf796..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/base.c ++++ /dev/null +@@ -1,274 +0,0 @@ +-/* +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +-#include +- +-#include "mxms.h" +- +-static bool +-mxm_shadow_rom_fetch(struct nouveau_i2c_port *i2c, u8 addr, +- u8 offset, u8 size, u8 *data) +-{ +- struct i2c_msg msgs[] = { +- { .addr = addr, .flags = 0, .len = 1, .buf = &offset }, +- { .addr = addr, .flags = I2C_M_RD, .len = size, .buf = data, }, +- }; +- +- return i2c_transfer(&i2c->adapter, msgs, 2) == 2; +-} +- +-static bool +-mxm_shadow_rom(struct nouveau_mxm *mxm, u8 version) +-{ +- struct nouveau_bios *bios = nouveau_bios(mxm); +- struct nouveau_i2c *i2c = nouveau_i2c(mxm); +- struct nouveau_i2c_port *port = NULL; +- u8 i2cidx, mxms[6], addr, size; +- +- i2cidx = mxm_ddc_map(bios, 1 /* LVDS_DDC */) & 0x0f; +- if (i2cidx < 0x0f) +- port = i2c->find(i2c, i2cidx); +- if (!port) +- return false; +- +- addr = 0x54; +- if (!mxm_shadow_rom_fetch(port, addr, 0, 6, mxms)) { +- addr = 0x56; +- if (!mxm_shadow_rom_fetch(port, addr, 0, 6, mxms)) +- return false; +- } +- +- mxm->mxms = mxms; +- size = mxms_headerlen(mxm) + mxms_structlen(mxm); +- mxm->mxms = kmalloc(size, GFP_KERNEL); +- +- if (mxm->mxms && +- mxm_shadow_rom_fetch(port, addr, 0, size, mxm->mxms)) +- return true; +- +- kfree(mxm->mxms); +- mxm->mxms = NULL; +- return false; +-} +- +-#if defined(CONFIG_ACPI) +-static bool +-mxm_shadow_dsm(struct nouveau_mxm *mxm, u8 version) +-{ +- struct nouveau_device *device = nv_device(mxm); +- static char muid[] = { +- 0x00, 0xA4, 0x04, 0x40, 0x7D, 0x91, 0xF2, 0x4C, +- 0xB8, 0x9C, 0x79, 0xB6, 0x2F, 0xD5, 0x56, 0x65 +- }; +- u32 mxms_args[] = { 0x00000000 }; +- union acpi_object argv4 = { +- .buffer.type = ACPI_TYPE_BUFFER, +- .buffer.length = sizeof(mxms_args), +- .buffer.pointer = (char *)mxms_args, +- }; +- union acpi_object *obj; +- acpi_handle handle; +- int rev; +- +- handle = ACPI_HANDLE(nv_device_base(device)); +- if (!handle) +- return false; +- +- /* +- * spec says this can be zero to mean "highest revision", but +- * of course there's at least one bios out there which fails +- * unless you pass in exactly the version it supports.. +- */ +- rev = (version & 0xf0) << 4 | (version & 0x0f); +- obj = acpi_evaluate_dsm(handle, muid, rev, 0x00000010, &argv4); +- if (!obj) { +- nv_debug(mxm, "DSM MXMS failed\n"); +- return false; +- } +- +- if (obj->type == ACPI_TYPE_BUFFER) { +- mxm->mxms = kmemdup(obj->buffer.pointer, +- obj->buffer.length, GFP_KERNEL); +- } else if (obj->type == ACPI_TYPE_INTEGER) { +- nv_debug(mxm, "DSM MXMS returned 0x%llx\n", obj->integer.value); +- } +- +- ACPI_FREE(obj); +- return mxm->mxms != NULL; +-} +-#endif +- +-#if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE) +- +-#define WMI_WMMX_GUID "F6CB5C3C-9CAE-4EBD-B577-931EA32A2CC0" +- +-static u8 +-wmi_wmmx_mxmi(struct nouveau_mxm *mxm, u8 version) +-{ +- u32 mxmi_args[] = { 0x494D584D /* MXMI */, version, 0 }; +- struct acpi_buffer args = { sizeof(mxmi_args), mxmi_args }; +- struct acpi_buffer retn = { ACPI_ALLOCATE_BUFFER, NULL }; +- union acpi_object *obj; +- acpi_status status; +- +- status = wmi_evaluate_method(WMI_WMMX_GUID, 0, 0, &args, &retn); +- if (ACPI_FAILURE(status)) { +- nv_debug(mxm, "WMMX MXMI returned %d\n", status); +- return 0x00; +- } +- +- obj = retn.pointer; +- if (obj->type == ACPI_TYPE_INTEGER) { +- version = obj->integer.value; +- nv_debug(mxm, "WMMX MXMI version %d.%d\n", +- (version >> 4), version & 0x0f); +- } else { +- version = 0; +- nv_debug(mxm, "WMMX MXMI returned non-integer\n"); +- } +- +- kfree(obj); +- return version; +-} +- +-static bool +-mxm_shadow_wmi(struct nouveau_mxm *mxm, u8 version) +-{ +- u32 mxms_args[] = { 0x534D584D /* MXMS */, version, 0 }; +- struct acpi_buffer args = { sizeof(mxms_args), mxms_args }; +- struct acpi_buffer retn = { ACPI_ALLOCATE_BUFFER, NULL }; +- union acpi_object *obj; +- acpi_status status; +- +- if (!wmi_has_guid(WMI_WMMX_GUID)) { +- nv_debug(mxm, "WMMX GUID not found\n"); +- return false; +- } +- +- mxms_args[1] = wmi_wmmx_mxmi(mxm, 0x00); +- if (!mxms_args[1]) +- mxms_args[1] = wmi_wmmx_mxmi(mxm, version); +- if (!mxms_args[1]) +- return false; +- +- status = wmi_evaluate_method(WMI_WMMX_GUID, 0, 0, &args, &retn); +- if (ACPI_FAILURE(status)) { +- nv_debug(mxm, "WMMX MXMS returned %d\n", status); +- return false; +- } +- +- obj = retn.pointer; +- if (obj->type == ACPI_TYPE_BUFFER) { +- mxm->mxms = kmemdup(obj->buffer.pointer, +- obj->buffer.length, GFP_KERNEL); +- } +- +- kfree(obj); +- return mxm->mxms != NULL; +-} +-#endif +- +-static struct mxm_shadow_h { +- const char *name; +- bool (*exec)(struct nouveau_mxm *, u8 version); +-} _mxm_shadow[] = { +- { "ROM", mxm_shadow_rom }, +-#if defined(CONFIG_ACPI) +- { "DSM", mxm_shadow_dsm }, +-#endif +-#if defined(CONFIG_ACPI_WMI) || defined(CONFIG_ACPI_WMI_MODULE) +- { "WMI", mxm_shadow_wmi }, +-#endif +- {} +-}; +- +-static int +-mxm_shadow(struct nouveau_mxm *mxm, u8 version) +-{ +- struct mxm_shadow_h *shadow = _mxm_shadow; +- do { +- nv_debug(mxm, "checking %s\n", shadow->name); +- if (shadow->exec(mxm, version)) { +- if (mxms_valid(mxm)) +- return 0; +- kfree(mxm->mxms); +- mxm->mxms = NULL; +- } +- } while ((++shadow)->name); +- return -ENOENT; +-} +- +-int +-nouveau_mxm_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nouveau_bios *bios = nouveau_bios(device); +- struct nouveau_mxm *mxm; +- u8 ver, len; +- u16 data; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "MXM", "mxm", +- length, pobject); +- mxm = *pobject; +- if (ret) +- return ret; +- +- data = mxm_table(bios, &ver, &len); +- if (!data || !(ver = nv_ro08(bios, data))) { +- nv_debug(mxm, "no VBIOS data, nothing to do\n"); +- return 0; +- } +- +- nv_info(mxm, "BIOS version %d.%d\n", ver >> 4, ver & 0x0f); +- +- if (mxm_shadow(mxm, ver)) { +- nv_info(mxm, "failed to locate valid SIS\n"); +-#if 0 +- /* we should, perhaps, fall back to some kind of limited +- * mode here if the x86 vbios hasn't already done the +- * work for us (so we prevent loading with completely +- * whacked vbios tables). +- */ +- return -EINVAL; +-#else +- return 0; +-#endif +- } +- +- nv_info(mxm, "MXMS Version %d.%d\n", +- mxms_version(mxm) >> 8, mxms_version(mxm) & 0xff); +- mxms_foreach(mxm, 0, NULL, NULL); +- +- if (nouveau_boolopt(device->cfgopt, "NvMXMDCB", true)) +- mxm->action |= MXM_SANITISE_DCB; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c +deleted file mode 100644 +index 4bde7f7f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.c ++++ /dev/null +@@ -1,193 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include "mxms.h" +- +-#define ROM16(x) le16_to_cpu(*(u16 *)&(x)) +-#define ROM32(x) le32_to_cpu(*(u32 *)&(x)) +- +-static u8 * +-mxms_data(struct nouveau_mxm *mxm) +-{ +- return mxm->mxms; +- +-} +- +-u16 +-mxms_version(struct nouveau_mxm *mxm) +-{ +- u8 *mxms = mxms_data(mxm); +- u16 version = (mxms[4] << 8) | mxms[5]; +- switch (version ) { +- case 0x0200: +- case 0x0201: +- case 0x0300: +- return version; +- default: +- break; +- } +- +- nv_debug(mxm, "unknown version %d.%d\n", mxms[4], mxms[5]); +- return 0x0000; +-} +- +-u16 +-mxms_headerlen(struct nouveau_mxm *mxm) +-{ +- return 8; +-} +- +-u16 +-mxms_structlen(struct nouveau_mxm *mxm) +-{ +- return *(u16 *)&mxms_data(mxm)[6]; +-} +- +-bool +-mxms_checksum(struct nouveau_mxm *mxm) +-{ +- u16 size = mxms_headerlen(mxm) + mxms_structlen(mxm); +- u8 *mxms = mxms_data(mxm), sum = 0; +- while (size--) +- sum += *mxms++; +- if (sum) { +- nv_debug(mxm, "checksum invalid\n"); +- return false; +- } +- return true; +-} +- +-bool +-mxms_valid(struct nouveau_mxm *mxm) +-{ +- u8 *mxms = mxms_data(mxm); +- if (*(u32 *)mxms != 0x5f4d584d) { +- nv_debug(mxm, "signature invalid\n"); +- return false; +- } +- +- if (!mxms_version(mxm) || !mxms_checksum(mxm)) +- return false; +- +- return true; +-} +- +-bool +-mxms_foreach(struct nouveau_mxm *mxm, u8 types, +- bool (*exec)(struct nouveau_mxm *, u8 *, void *), void *info) +-{ +- u8 *mxms = mxms_data(mxm); +- u8 *desc = mxms + mxms_headerlen(mxm); +- u8 *fini = desc + mxms_structlen(mxm) - 1; +- while (desc < fini) { +- u8 type = desc[0] & 0x0f; +- u8 headerlen = 0; +- u8 recordlen = 0; +- u8 entries = 0; +- +- switch (type) { +- case 0: /* Output Device Structure */ +- if (mxms_version(mxm) >= 0x0300) +- headerlen = 8; +- else +- headerlen = 6; +- break; +- case 1: /* System Cooling Capability Structure */ +- case 2: /* Thermal Structure */ +- case 3: /* Input Power Structure */ +- headerlen = 4; +- break; +- case 4: /* GPIO Device Structure */ +- headerlen = 4; +- recordlen = 2; +- entries = (ROM32(desc[0]) & 0x01f00000) >> 20; +- break; +- case 5: /* Vendor Specific Structure */ +- headerlen = 8; +- break; +- case 6: /* Backlight Control Structure */ +- if (mxms_version(mxm) >= 0x0300) { +- headerlen = 4; +- recordlen = 8; +- entries = (desc[1] & 0xf0) >> 4; +- } else { +- headerlen = 8; +- } +- break; +- case 7: /* Fan Control Structure */ +- headerlen = 8; +- recordlen = 4; +- entries = desc[1] & 0x07; +- break; +- default: +- nv_debug(mxm, "unknown descriptor type %d\n", type); +- return false; +- } +- +- if (nv_subdev(mxm)->debug >= NV_DBG_DEBUG && (exec == NULL)) { +- static const char * mxms_desc_name[] = { +- "ODS", "SCCS", "TS", "IPS", +- "GSD", "VSS", "BCS", "FCS", +- }; +- u8 *dump = desc; +- int i, j; +- +- nv_debug(mxm, "%4s: ", mxms_desc_name[type]); +- for (j = headerlen - 1; j >= 0; j--) +- pr_cont("%02x", dump[j]); +- pr_cont("\n"); +- dump += headerlen; +- +- for (i = 0; i < entries; i++, dump += recordlen) { +- nv_debug(mxm, " "); +- for (j = recordlen - 1; j >= 0; j--) +- pr_cont("%02x", dump[j]); +- pr_cont("\n"); +- } +- } +- +- if (types & (1 << type)) { +- if (!exec(mxm, desc, info)) +- return false; +- } +- +- desc += headerlen + (entries * recordlen); +- } +- +- return true; +-} +- +-void +-mxms_output_device(struct nouveau_mxm *mxm, u8 *pdata, struct mxms_odev *desc) +-{ +- u64 data = ROM32(pdata[0]); +- if (mxms_version(mxm) >= 0x0300) +- data |= (u64)ROM16(pdata[4]) << 32; +- +- desc->outp_type = (data & 0x00000000000000f0ULL) >> 4; +- desc->ddc_port = (data & 0x0000000000000f00ULL) >> 8; +- desc->conn_type = (data & 0x000000000001f000ULL) >> 12; +- desc->dig_conn = (data & 0x0000000000780000ULL) >> 19; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h b/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h +deleted file mode 100644 +index 5e0be0c5..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/mxms.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-#ifndef __NVMXM_MXMS_H__ +-#define __NVMXM_MXMS_H__ +- +-struct mxms_odev { +- u8 outp_type; +- u8 conn_type; +- u8 ddc_port; +- u8 dig_conn; +-}; +- +-void mxms_output_device(struct nouveau_mxm *, u8 *, struct mxms_odev *); +- +-u16 mxms_version(struct nouveau_mxm *); +-u16 mxms_headerlen(struct nouveau_mxm *); +-u16 mxms_structlen(struct nouveau_mxm *); +-bool mxms_checksum(struct nouveau_mxm *); +-bool mxms_valid(struct nouveau_mxm *); +- +-bool mxms_foreach(struct nouveau_mxm *, u8, +- bool (*)(struct nouveau_mxm *, u8 *, void *), void *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c +deleted file mode 100644 +index fcaabe84..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/mxm/nv50.c ++++ /dev/null +@@ -1,233 +0,0 @@ +-/* +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "mxms.h" +- +-struct nv50_mxm_priv { +- struct nouveau_mxm base; +-}; +- +-struct context { +- u32 *outp; +- struct mxms_odev desc; +-}; +- +-static bool +-mxm_match_tmds_partner(struct nouveau_mxm *mxm, u8 *data, void *info) +-{ +- struct context *ctx = info; +- struct mxms_odev desc; +- +- mxms_output_device(mxm, data, &desc); +- if (desc.outp_type == 2 && +- desc.dig_conn == ctx->desc.dig_conn) +- return false; +- return true; +-} +- +-static bool +-mxm_match_dcb(struct nouveau_mxm *mxm, u8 *data, void *info) +-{ +- struct nouveau_bios *bios = nouveau_bios(mxm); +- struct context *ctx = info; +- u64 desc = *(u64 *)data; +- +- mxms_output_device(mxm, data, &ctx->desc); +- +- /* match dcb encoder type to mxm-ods device type */ +- if ((ctx->outp[0] & 0x0000000f) != ctx->desc.outp_type) +- return true; +- +- /* digital output, have some extra stuff to match here, there's a +- * table in the vbios that provides a mapping from the mxm digital +- * connection enum values to SOR/link +- */ +- if ((desc & 0x00000000000000f0) >= 0x20) { +- /* check against sor index */ +- u8 link = mxm_sor_map(bios, ctx->desc.dig_conn); +- if ((ctx->outp[0] & 0x0f000000) != (link & 0x0f) << 24) +- return true; +- +- /* check dcb entry has a compatible link field */ +- link = (link & 0x30) >> 4; +- if ((link & ((ctx->outp[1] & 0x00000030) >> 4)) != link) +- return true; +- } +- +- /* mark this descriptor accounted for by setting invalid device type, +- * except of course some manufactures don't follow specs properly and +- * we need to avoid killing off the TMDS function on DP connectors +- * if MXM-SIS is missing an entry for it. +- */ +- data[0] &= ~0xf0; +- if (ctx->desc.outp_type == 6 && ctx->desc.conn_type == 6 && +- mxms_foreach(mxm, 0x01, mxm_match_tmds_partner, ctx)) { +- data[0] |= 0x20; /* modify descriptor to match TMDS now */ +- } else { +- data[0] |= 0xf0; +- } +- +- return false; +-} +- +-static int +-mxm_dcb_sanitise_entry(struct nouveau_bios *bios, void *data, int idx, u16 pdcb) +-{ +- struct nouveau_mxm *mxm = data; +- struct context ctx = { .outp = (u32 *)(bios->data + pdcb) }; +- u8 type, i2cidx, link, ver, len; +- u8 *conn; +- +- /* look for an output device structure that matches this dcb entry. +- * if one isn't found, disable it. +- */ +- if (mxms_foreach(mxm, 0x01, mxm_match_dcb, &ctx)) { +- nv_debug(mxm, "disable %d: 0x%08x 0x%08x\n", +- idx, ctx.outp[0], ctx.outp[1]); +- ctx.outp[0] |= 0x0000000f; +- return 0; +- } +- +- /* modify the output's ddc/aux port, there's a pointer to a table +- * with the mapping from mxm ddc/aux port to dcb i2c_index in the +- * vbios mxm table +- */ +- i2cidx = mxm_ddc_map(bios, ctx.desc.ddc_port); +- if ((ctx.outp[0] & 0x0000000f) != DCB_OUTPUT_DP) +- i2cidx = (i2cidx & 0x0f) << 4; +- else +- i2cidx = (i2cidx & 0xf0); +- +- if (i2cidx != 0xf0) { +- ctx.outp[0] &= ~0x000000f0; +- ctx.outp[0] |= i2cidx; +- } +- +- /* override dcb sorconf.link, based on what mxm data says */ +- switch (ctx.desc.outp_type) { +- case 0x00: /* Analog CRT */ +- case 0x01: /* Analog TV/HDTV */ +- break; +- default: +- link = mxm_sor_map(bios, ctx.desc.dig_conn) & 0x30; +- ctx.outp[1] &= ~0x00000030; +- ctx.outp[1] |= link; +- break; +- } +- +- /* we may need to fixup various other vbios tables based on what +- * the descriptor says the connector type should be. +- * +- * in a lot of cases, the vbios tables will claim DVI-I is possible, +- * and the mxm data says the connector is really HDMI. another +- * common example is DP->eDP. +- */ +- conn = bios->data; +- conn += nvbios_connEe(bios, (ctx.outp[0] & 0x0000f000) >> 12, &ver, &len); +- type = conn[0]; +- switch (ctx.desc.conn_type) { +- case 0x01: /* LVDS */ +- ctx.outp[1] |= 0x00000004; /* use_power_scripts */ +- /* XXX: modify default link width in LVDS table */ +- break; +- case 0x02: /* HDMI */ +- type = DCB_CONNECTOR_HDMI_1; +- break; +- case 0x03: /* DVI-D */ +- type = DCB_CONNECTOR_DVI_D; +- break; +- case 0x0e: /* eDP, falls through to DPint */ +- ctx.outp[1] |= 0x00010000; +- case 0x07: /* DP internal, wtf is this?? HP8670w */ +- ctx.outp[1] |= 0x00000004; /* use_power_scripts? */ +- type = DCB_CONNECTOR_eDP; +- break; +- default: +- break; +- } +- +- if (mxms_version(mxm) >= 0x0300) +- conn[0] = type; +- +- return 0; +-} +- +-static bool +-mxm_show_unmatched(struct nouveau_mxm *mxm, u8 *data, void *info) +-{ +- u64 desc = *(u64 *)data; +- if ((desc & 0xf0) != 0xf0) +- nv_info(mxm, "unmatched output device 0x%016llx\n", desc); +- return true; +-} +- +-static void +-mxm_dcb_sanitise(struct nouveau_mxm *mxm) +-{ +- struct nouveau_bios *bios = nouveau_bios(mxm); +- u8 ver, hdr, cnt, len; +- u16 dcb = dcb_table(bios, &ver, &hdr, &cnt, &len); +- if (dcb == 0x0000 || ver != 0x40) { +- nv_debug(mxm, "unsupported DCB version\n"); +- return; +- } +- +- dcb_outp_foreach(bios, mxm, mxm_dcb_sanitise_entry); +- mxms_foreach(mxm, 0x01, mxm_show_unmatched, NULL); +-} +- +-static int +-nv50_mxm_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_mxm_priv *priv; +- int ret; +- +- ret = nouveau_mxm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- if (priv->base.action & MXM_SANITISE_DCB) +- mxm_dcb_sanitise(&priv->base); +- return 0; +-} +- +-struct nouveau_oclass +-nv50_mxm_oclass = { +- .handle = NV_SUBDEV(MXM, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_mxm_ctor, +- .dtor = _nouveau_mxm_dtor, +- .init = _nouveau_mxm_init, +- .fini = _nouveau_mxm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c +deleted file mode 100644 +index 0ab55f27..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/base.c ++++ /dev/null +@@ -1,272 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "priv.h" +- +-static void +-nouveau_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) +-{ +- const struct nvkm_pwr_impl *impl = (void *)nv_oclass(ppwr); +- if (impl->pgob) +- impl->pgob(ppwr, enable); +-} +- +-static int +-nouveau_pwr_send(struct nouveau_pwr *ppwr, u32 reply[2], +- u32 process, u32 message, u32 data0, u32 data1) +-{ +- struct nouveau_subdev *subdev = nv_subdev(ppwr); +- u32 addr; +- +- /* wait for a free slot in the fifo */ +- addr = nv_rd32(ppwr, 0x10a4a0); +- if (!nv_wait_ne(ppwr, 0x10a4b0, 0xffffffff, addr ^ 8)) +- return -EBUSY; +- +- /* we currently only support a single process at a time waiting +- * on a synchronous reply, take the PPWR mutex and tell the +- * receive handler what we're waiting for +- */ +- if (reply) { +- mutex_lock(&subdev->mutex); +- ppwr->recv.message = message; +- ppwr->recv.process = process; +- } +- +- /* acquire data segment access */ +- do { +- nv_wr32(ppwr, 0x10a580, 0x00000001); +- } while (nv_rd32(ppwr, 0x10a580) != 0x00000001); +- +- /* write the packet */ +- nv_wr32(ppwr, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + +- ppwr->send.base)); +- nv_wr32(ppwr, 0x10a1c4, process); +- nv_wr32(ppwr, 0x10a1c4, message); +- nv_wr32(ppwr, 0x10a1c4, data0); +- nv_wr32(ppwr, 0x10a1c4, data1); +- nv_wr32(ppwr, 0x10a4a0, (addr + 1) & 0x0f); +- +- /* release data segment access */ +- nv_wr32(ppwr, 0x10a580, 0x00000000); +- +- /* wait for reply, if requested */ +- if (reply) { +- wait_event(ppwr->recv.wait, (ppwr->recv.process == 0)); +- reply[0] = ppwr->recv.data[0]; +- reply[1] = ppwr->recv.data[1]; +- mutex_unlock(&subdev->mutex); +- } +- +- return 0; +-} +- +-static void +-nouveau_pwr_recv(struct work_struct *work) +-{ +- struct nouveau_pwr *ppwr = +- container_of(work, struct nouveau_pwr, recv.work); +- u32 process, message, data0, data1; +- +- /* nothing to do if GET == PUT */ +- u32 addr = nv_rd32(ppwr, 0x10a4cc); +- if (addr == nv_rd32(ppwr, 0x10a4c8)) +- return; +- +- /* acquire data segment access */ +- do { +- nv_wr32(ppwr, 0x10a580, 0x00000002); +- } while (nv_rd32(ppwr, 0x10a580) != 0x00000002); +- +- /* read the packet */ +- nv_wr32(ppwr, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + +- ppwr->recv.base)); +- process = nv_rd32(ppwr, 0x10a1c4); +- message = nv_rd32(ppwr, 0x10a1c4); +- data0 = nv_rd32(ppwr, 0x10a1c4); +- data1 = nv_rd32(ppwr, 0x10a1c4); +- nv_wr32(ppwr, 0x10a4cc, (addr + 1) & 0x0f); +- +- /* release data segment access */ +- nv_wr32(ppwr, 0x10a580, 0x00000000); +- +- /* wake process if it's waiting on a synchronous reply */ +- if (ppwr->recv.process) { +- if (process == ppwr->recv.process && +- message == ppwr->recv.message) { +- ppwr->recv.data[0] = data0; +- ppwr->recv.data[1] = data1; +- ppwr->recv.process = 0; +- wake_up(&ppwr->recv.wait); +- return; +- } +- } +- +- /* right now there's no other expected responses from the engine, +- * so assume that any unexpected message is an error. +- */ +- nv_warn(ppwr, "%c%c%c%c 0x%08x 0x%08x 0x%08x 0x%08x\n", +- (char)((process & 0x000000ff) >> 0), +- (char)((process & 0x0000ff00) >> 8), +- (char)((process & 0x00ff0000) >> 16), +- (char)((process & 0xff000000) >> 24), +- process, message, data0, data1); +-} +- +-static void +-nouveau_pwr_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_pwr *ppwr = (void *)subdev; +- u32 disp = nv_rd32(ppwr, 0x10a01c); +- u32 intr = nv_rd32(ppwr, 0x10a008) & disp & ~(disp >> 16); +- +- if (intr & 0x00000020) { +- u32 stat = nv_rd32(ppwr, 0x10a16c); +- if (stat & 0x80000000) { +- nv_error(ppwr, "UAS fault at 0x%06x addr 0x%08x\n", +- stat & 0x00ffffff, nv_rd32(ppwr, 0x10a168)); +- nv_wr32(ppwr, 0x10a16c, 0x00000000); +- intr &= ~0x00000020; +- } +- } +- +- if (intr & 0x00000040) { +- schedule_work(&ppwr->recv.work); +- nv_wr32(ppwr, 0x10a004, 0x00000040); +- intr &= ~0x00000040; +- } +- +- if (intr & 0x00000080) { +- nv_info(ppwr, "wr32 0x%06x 0x%08x\n", nv_rd32(ppwr, 0x10a7a0), +- nv_rd32(ppwr, 0x10a7a4)); +- nv_wr32(ppwr, 0x10a004, 0x00000080); +- intr &= ~0x00000080; +- } +- +- if (intr) { +- nv_error(ppwr, "intr 0x%08x\n", intr); +- nv_wr32(ppwr, 0x10a004, intr); +- } +-} +- +-int +-_nouveau_pwr_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_pwr *ppwr = (void *)object; +- +- nv_wr32(ppwr, 0x10a014, 0x00000060); +- flush_work(&ppwr->recv.work); +- +- return nouveau_subdev_fini(&ppwr->base, suspend); +-} +- +-int +-_nouveau_pwr_init(struct nouveau_object *object) +-{ +- const struct nvkm_pwr_impl *impl = (void *)object->oclass; +- struct nouveau_pwr *ppwr = (void *)object; +- int ret, i; +- +- ret = nouveau_subdev_init(&ppwr->base); +- if (ret) +- return ret; +- +- nv_subdev(ppwr)->intr = nouveau_pwr_intr; +- ppwr->message = nouveau_pwr_send; +- ppwr->pgob = nouveau_pwr_pgob; +- +- /* prevent previous ucode from running, wait for idle, reset */ +- nv_wr32(ppwr, 0x10a014, 0x0000ffff); /* INTR_EN_CLR = ALL */ +- nv_wait(ppwr, 0x10a04c, 0xffffffff, 0x00000000); +- nv_mask(ppwr, 0x000200, 0x00002000, 0x00000000); +- nv_mask(ppwr, 0x000200, 0x00002000, 0x00002000); +- nv_rd32(ppwr, 0x000200); +- nv_wait(ppwr, 0x10a10c, 0x00000006, 0x00000000); +- +- /* upload data segment */ +- nv_wr32(ppwr, 0x10a1c0, 0x01000000); +- for (i = 0; i < impl->data.size / 4; i++) +- nv_wr32(ppwr, 0x10a1c4, impl->data.data[i]); +- +- /* upload code segment */ +- nv_wr32(ppwr, 0x10a180, 0x01000000); +- for (i = 0; i < impl->code.size / 4; i++) { +- if ((i & 0x3f) == 0) +- nv_wr32(ppwr, 0x10a188, i >> 6); +- nv_wr32(ppwr, 0x10a184, impl->code.data[i]); +- } +- +- /* start it running */ +- nv_wr32(ppwr, 0x10a10c, 0x00000000); +- nv_wr32(ppwr, 0x10a104, 0x00000000); +- nv_wr32(ppwr, 0x10a100, 0x00000002); +- +- /* wait for valid host->pwr ring configuration */ +- if (!nv_wait_ne(ppwr, 0x10a4d0, 0xffffffff, 0x00000000)) +- return -EBUSY; +- ppwr->send.base = nv_rd32(ppwr, 0x10a4d0) & 0x0000ffff; +- ppwr->send.size = nv_rd32(ppwr, 0x10a4d0) >> 16; +- +- /* wait for valid pwr->host ring configuration */ +- if (!nv_wait_ne(ppwr, 0x10a4dc, 0xffffffff, 0x00000000)) +- return -EBUSY; +- ppwr->recv.base = nv_rd32(ppwr, 0x10a4dc) & 0x0000ffff; +- ppwr->recv.size = nv_rd32(ppwr, 0x10a4dc) >> 16; +- +- nv_wr32(ppwr, 0x10a010, 0x000000e0); +- return 0; +-} +- +-int +-nouveau_pwr_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- struct nouveau_pwr *ppwr; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PPWR", +- "pwr", length, pobject); +- ppwr = *pobject; +- if (ret) +- return ret; +- +- INIT_WORK(&ppwr->recv.work, nouveau_pwr_recv); +- init_waitqueue_head(&ppwr->recv.wait); +- return 0; +-} +- +-int +-_nouveau_pwr_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_pwr *ppwr; +- int ret = nouveau_pwr_create(parent, engine, oclass, &ppwr); +- *pobject = nv_object(ppwr); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc +deleted file mode 100644 +index 214a6d9e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/arith.fuc ++++ /dev/null +@@ -1,94 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the folloing conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-/****************************************************************************** +- * arith data segment +- *****************************************************************************/ +-#ifdef INCLUDE_PROC +-#endif +- +-#ifdef INCLUDE_DATA +-#endif +- +-/****************************************************************************** +- * arith code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +- +-// does a 32x32 -> 64 multiplication +-// +-// A * B = A_lo * B_lo +-// + ( A_hi * B_lo ) << 16 +-// + ( A_lo * B_hi ) << 16 +-// + ( A_hi * B_hi ) << 32 +-// +-// $r15 - current +-// $r14 - A +-// $r13 - B +-// $r12 - mul_lo (return) +-// $r11 - mul_hi (return) +-// $r0 - zero +-mulu32_32_64: +- push $r1 // A_hi +- push $r2 // B_hi +- push $r3 // tmp0 +- push $r4 // tmp1 +- +- shr b32 $r1 $r14 16 +- shr b32 $r2 $r13 16 +- +- clear b32 $r12 +- clear b32 $r11 +- +- // A_lo * B_lo +- mulu $r12 $r14 $r13 +- +- // ( A_hi * B_lo ) << 16 +- mulu $r3 $r1 $r13 // tmp0 = A_hi * B_lo +- mov b32 $r4 $r3 +- and $r3 0xffff // tmp0 = tmp0_lo +- shl b32 $r3 16 +- shr b32 $r4 16 // tmp1 = tmp0_hi +- add b32 $r12 $r3 +- adc b32 $r11 $r4 +- +- // ( A_lo * B_hi ) << 16 +- mulu $r3 $r14 $r2 // tmp0 = A_lo * B_hi +- mov b32 $r4 $r3 +- and $r3 0xffff // tmp0 = tmp0_lo +- shl b32 $r3 16 +- shr b32 $r4 16 // tmp1 = tmp0_hi +- add b32 $r12 $r3 +- adc b32 $r11 $r4 +- +- // ( A_hi * B_hi ) << 32 +- mulu $r3 $r1 $r2 // tmp0 = A_hi * B_hi +- add b32 $r11 $r3 +- +- pop $r4 +- pop $r3 +- pop $r2 +- pop $r1 +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc +deleted file mode 100644 +index c2bb616a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/host.fuc ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_PROC +-process(PROC_HOST, #host_init, #host_recv) +-#endif +- +-/****************************************************************************** +- * HOST data segment +- *****************************************************************************/ +-#ifdef INCLUDE_DATA +-// HOST (R)FIFO packet format +-.equ #fifo_process 0x00 +-.equ #fifo_message 0x04 +-.equ #fifo_data0 0x08 +-.equ #fifo_data1 0x0c +- +-// HOST HOST->PWR queue description +-.equ #fifo_qlen 4 // log2(size of queue entry in bytes) +-.equ #fifo_qnum 3 // log2(max number of entries in queue) +-.equ #fifo_qmaskb (1 << #fifo_qnum) // max number of entries in queue +-.equ #fifo_qmaskp (#fifo_qmaskb - 1) +-.equ #fifo_qmaskf ((#fifo_qmaskb << 1) - 1) +-.equ #fifo_qsize (1 << (#fifo_qlen + #fifo_qnum)) +-fifo_queue: .skip 128 // #fifo_qsize +- +-// HOST PWR->HOST queue description +-.equ #rfifo_qlen 4 // log2(size of queue entry in bytes) +-.equ #rfifo_qnum 3 // log2(max number of entries in queue) +-.equ #rfifo_qmaskb (1 << #rfifo_qnum) // max number of entries in queue +-.equ #rfifo_qmaskp (#rfifo_qmaskb - 1) +-.equ #rfifo_qmaskf ((#rfifo_qmaskb << 1) - 1) +-.equ #rfifo_qsize (1 << (#rfifo_qlen + #rfifo_qnum)) +-rfifo_queue: .skip 128 // #rfifo_qsize +-#endif +- +-/****************************************************************************** +- * HOST code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +-// HOST->PWR comms - dequeue message(s) for process(es) from FIFO +-// +-// $r15 - current (host) +-// $r0 - zero +-host_send: +- nv_iord($r1, NV_PPWR_FIFO_GET(0)) +- nv_iord($r2, NV_PPWR_FIFO_PUT(0)) +- cmp b32 $r1 $r2 +- bra e #host_send_done +- // calculate address of message +- and $r14 $r1 #fifo_qmaskp +- shl b32 $r14 $r14 #fifo_qlen +- add b32 $r14 #fifo_queue +- +- // read message data, and pass to appropriate process +- ld b32 $r11 D[$r14 + #fifo_data1] +- ld b32 $r12 D[$r14 + #fifo_data0] +- ld b32 $r13 D[$r14 + #fifo_message] +- ld b32 $r14 D[$r14 + #fifo_process] +- call(send) +- +- // increment GET +- add b32 $r1 0x1 +- and $r14 $r1 #fifo_qmaskf +- nv_iowr(NV_PPWR_FIFO_GET(0), $r14) +- bra #host_send +- host_send_done: +- ret +- +-// PWR->HOST comms - enqueue message for HOST to RFIFO +-// +-// $r15 - current (host) +-// $r14 - process +-// $r13 - message +-// $r12 - message data 0 +-// $r11 - message data 1 +-// $r0 - zero +-host_recv: +- // message from intr handler == HOST->PWR comms pending +- mov $r1 (PROC_KERN & 0x0000ffff) +- sethi $r1 (PROC_KERN & 0xffff0000) +- cmp b32 $r14 $r1 +- bra e #host_send +- +- // wait for space in RFIFO +- host_recv_wait: +- nv_iord($r1, NV_PPWR_RFIFO_GET) +- nv_iord($r2, NV_PPWR_RFIFO_PUT) +- xor $r1 #rfifo_qmaskb +- cmp b32 $r1 $r2 +- bra e #host_recv_wait +- +- and $r3 $r2 #rfifo_qmaskp +- shl b32 $r3 #rfifo_qlen +- add b32 $r3 #rfifo_queue +- +- // enqueue message +- st b32 D[$r3 + #fifo_data1] $r11 +- st b32 D[$r3 + #fifo_data0] $r12 +- st b32 D[$r3 + #fifo_message] $r13 +- st b32 D[$r3 + #fifo_process] $r14 +- +- add b32 $r2 0x1 +- and $r2 #rfifo_qmaskf +- nv_iowr(NV_PPWR_RFIFO_PUT, $r2) +- +- // notify host of pending message +- mov $r2 NV_PPWR_INTR_TRIGGER_USER0 +- nv_iowr(NV_PPWR_INTR_TRIGGER, $r2) +- ret +- +-// $r15 - current (host) +-// $r0 - zero +-host_init: +- // store each fifo's base/size in H2D/D2H scratch regs +- mov $r1 #fifo_qsize +- shl b32 $r1 16 +- or $r1 #fifo_queue +- nv_iowr(NV_PPWR_H2D, $r1); +- +- mov $r1 #rfifo_qsize +- shl b32 $r1 16 +- or $r1 #rfifo_queue +- nv_iowr(NV_PPWR_D2H, $r1); +- +- // enable fifo subintr for first fifo +- mov $r1 1 +- nv_iowr(NV_PPWR_FIFO_INTR_EN, $r1) +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc +deleted file mode 100644 +index 757dda70..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/i2c_.fuc ++++ /dev/null +@@ -1,393 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define T_TIMEOUT 2200000 +-#define T_RISEFALL 1000 +-#define T_HOLD 5000 +- +-#ifdef INCLUDE_PROC +-process(PROC_I2C_, #i2c_init, #i2c_recv) +-#endif +- +-/****************************************************************************** +- * I2C_ data segment +- *****************************************************************************/ +-#ifdef INCLUDE_DATA +-i2c_scl_map: +-.b32 NV_PPWR_OUTPUT_I2C_0_SCL +-.b32 NV_PPWR_OUTPUT_I2C_1_SCL +-.b32 NV_PPWR_OUTPUT_I2C_2_SCL +-.b32 NV_PPWR_OUTPUT_I2C_3_SCL +-.b32 NV_PPWR_OUTPUT_I2C_4_SCL +-.b32 NV_PPWR_OUTPUT_I2C_5_SCL +-.b32 NV_PPWR_OUTPUT_I2C_6_SCL +-.b32 NV_PPWR_OUTPUT_I2C_7_SCL +-.b32 NV_PPWR_OUTPUT_I2C_8_SCL +-.b32 NV_PPWR_OUTPUT_I2C_9_SCL +-i2c_sda_map: +-.b32 NV_PPWR_OUTPUT_I2C_0_SDA +-.b32 NV_PPWR_OUTPUT_I2C_1_SDA +-.b32 NV_PPWR_OUTPUT_I2C_2_SDA +-.b32 NV_PPWR_OUTPUT_I2C_3_SDA +-.b32 NV_PPWR_OUTPUT_I2C_4_SDA +-.b32 NV_PPWR_OUTPUT_I2C_5_SDA +-.b32 NV_PPWR_OUTPUT_I2C_6_SDA +-.b32 NV_PPWR_OUTPUT_I2C_7_SDA +-.b32 NV_PPWR_OUTPUT_I2C_8_SDA +-.b32 NV_PPWR_OUTPUT_I2C_9_SDA +-#if NVKM_PPWR_CHIPSET < GF119 +-i2c_ctrl: +-.b32 0x00e138 +-.b32 0x00e150 +-.b32 0x00e168 +-.b32 0x00e180 +-.b32 0x00e254 +-.b32 0x00e274 +-.b32 0x00e764 +-.b32 0x00e780 +-.b32 0x00e79c +-.b32 0x00e7b8 +-#endif +-#endif +- +-/****************************************************************************** +- * I2C_ code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +- +-// $r3 - value +-// $r2 - sda line +-// $r1 - scl line +-// $r0 - zero +-i2c_drive_scl: +- cmp b32 $r3 0 +- bra e #i2c_drive_scl_lo +- nv_iowr(NV_PPWR_OUTPUT_SET, $r1) +- ret +- i2c_drive_scl_lo: +- nv_iowr(NV_PPWR_OUTPUT_CLR, $r1) +- ret +- +-i2c_drive_sda: +- cmp b32 $r3 0 +- bra e #i2c_drive_sda_lo +- nv_iowr(NV_PPWR_OUTPUT_SET, $r2) +- ret +- i2c_drive_sda_lo: +- nv_iowr(NV_PPWR_OUTPUT_CLR, $r2) +- ret +- +-i2c_sense_scl: +- bclr $flags $p1 +- nv_iord($r3, NV_PPWR_INPUT) +- and $r3 $r1 +- bra z #i2c_sense_scl_done +- bset $flags $p1 +- i2c_sense_scl_done: +- ret +- +-i2c_sense_sda: +- bclr $flags $p1 +- nv_iord($r3, NV_PPWR_INPUT) +- and $r3 $r2 +- bra z #i2c_sense_sda_done +- bset $flags $p1 +- i2c_sense_sda_done: +- ret +- +-#define i2c_drive_scl(v) /* +-*/ mov $r3 (v) /* +-*/ call(i2c_drive_scl) +-#define i2c_drive_sda(v) /* +-*/ mov $r3 (v) /* +-*/ call(i2c_drive_sda) +-#define i2c_sense_scl() /* +-*/ call(i2c_sense_scl) +-#define i2c_sense_sda() /* +-*/ call(i2c_sense_sda) +-#define i2c_delay(v) /* +-*/ mov $r14 (v) /* +-*/ call(nsec) +- +-#define i2c_trace_init() /* +-*/ imm32($r6, 0x10000000) /* +-*/ sub b32 $r7 $r6 1 /* +-*/ +-#define i2c_trace_down() /* +-*/ shr b32 $r6 4 /* +-*/ push $r5 /* +-*/ shl b32 $r5 $r6 4 /* +-*/ sub b32 $r5 $r6 /* +-*/ not b32 $r5 /* +-*/ and $r7 $r5 /* +-*/ pop $r5 /* +-*/ +-#define i2c_trace_exit() /* +-*/ shl b32 $r6 4 /* +-*/ +-#define i2c_trace_next() /* +-*/ add b32 $r7 $r6 /* +-*/ +-#define i2c_trace_call(func) /* +-*/ i2c_trace_next() /* +-*/ i2c_trace_down() /* +-*/ call(func) /* +-*/ i2c_trace_exit() /* +-*/ +- +-i2c_raise_scl: +- push $r4 +- mov $r4 (T_TIMEOUT / T_RISEFALL) +- i2c_drive_scl(1) +- i2c_raise_scl_wait: +- i2c_delay(T_RISEFALL) +- i2c_sense_scl() +- bra $p1 #i2c_raise_scl_done +- sub b32 $r4 1 +- bra nz #i2c_raise_scl_wait +- i2c_raise_scl_done: +- pop $r4 +- ret +- +-i2c_start: +- i2c_sense_scl() +- bra not $p1 #i2c_start_rep +- i2c_sense_sda() +- bra not $p1 #i2c_start_rep +- bra #i2c_start_send +- i2c_start_rep: +- i2c_drive_scl(0) +- i2c_drive_sda(1) +- i2c_trace_call(i2c_raise_scl) +- bra not $p1 #i2c_start_out +- i2c_start_send: +- i2c_drive_sda(0) +- i2c_delay(T_HOLD) +- i2c_drive_scl(0) +- i2c_delay(T_HOLD) +- i2c_start_out: +- ret +- +-i2c_stop: +- i2c_drive_scl(0) +- i2c_drive_sda(0) +- i2c_delay(T_RISEFALL) +- i2c_drive_scl(1) +- i2c_delay(T_HOLD) +- i2c_drive_sda(1) +- i2c_delay(T_HOLD) +- ret +- +-// $r3 - value +-// $r2 - sda line +-// $r1 - scl line +-// $r0 - zero +-i2c_bitw: +- call(i2c_drive_sda) +- i2c_delay(T_RISEFALL) +- i2c_trace_call(i2c_raise_scl) +- bra not $p1 #i2c_bitw_out +- i2c_delay(T_HOLD) +- i2c_drive_scl(0) +- i2c_delay(T_HOLD) +- i2c_bitw_out: +- ret +- +-// $r3 - value (out) +-// $r2 - sda line +-// $r1 - scl line +-// $r0 - zero +-i2c_bitr: +- i2c_drive_sda(1) +- i2c_delay(T_RISEFALL) +- i2c_trace_call(i2c_raise_scl) +- bra not $p1 #i2c_bitr_done +- i2c_sense_sda() +- i2c_drive_scl(0) +- i2c_delay(T_HOLD) +- xbit $r3 $flags $p1 +- bset $flags $p1 +- i2c_bitr_done: +- ret +- +-i2c_get_byte: +- mov $r5 0 +- mov $r4 8 +- i2c_get_byte_next: +- shl b32 $r5 1 +- i2c_trace_call(i2c_bitr) +- bra not $p1 #i2c_get_byte_done +- or $r5 $r3 +- sub b32 $r4 1 +- bra nz #i2c_get_byte_next +- mov $r3 1 +- i2c_trace_call(i2c_bitw) +- i2c_get_byte_done: +- ret +- +-i2c_put_byte: +- mov $r4 8 +- i2c_put_byte_next: +- sub b32 $r4 1 +- xbit $r3 $r5 $r4 +- i2c_trace_call(i2c_bitw) +- bra not $p1 #i2c_put_byte_done +- cmp b32 $r4 0 +- bra ne #i2c_put_byte_next +- i2c_trace_call(i2c_bitr) +- bra not $p1 #i2c_put_byte_done +- i2c_trace_next() +- cmp b32 $r3 1 +- bra ne #i2c_put_byte_done +- bclr $flags $p1 // nack +- i2c_put_byte_done: +- ret +- +-i2c_addr: +- i2c_trace_call(i2c_start) +- bra not $p1 #i2c_addr_done +- extr $r3 $r12 I2C__MSG_DATA0_ADDR +- shl b32 $r3 1 +- or $r5 $r3 +- i2c_trace_call(i2c_put_byte) +- i2c_addr_done: +- ret +- +-i2c_acquire_addr: +- extr $r14 $r12 I2C__MSG_DATA0_PORT +-#if NVKM_PPWR_CHIPSET < GF119 +- shl b32 $r14 2 +- add b32 $r14 #i2c_ctrl +- ld b32 $r14 D[$r14] +-#else +- shl b32 $r14 5 +- add b32 $r14 0x00d014 +-#endif +- ret +- +-i2c_acquire: +- call(i2c_acquire_addr) +- call(rd32) +- bset $r13 3 +- call(wr32) +- ret +- +-i2c_release: +- call(i2c_acquire_addr) +- call(rd32) +- bclr $r13 3 +- call(wr32) +- ret +- +-// description +-// +-// $r15 - current (i2c) +-// $r14 - sender process name +-// $r13 - message +-// $r12 - data0 +-// $r11 - data1 +-// $r0 - zero +-i2c_recv: +- bclr $flags $p1 +- extr $r1 $r12 I2C__MSG_DATA0_PORT +- shl b32 $r1 2 +- cmp b32 $r1 (#i2c_sda_map - #i2c_scl_map) +- bra ge #i2c_recv_done +- add b32 $r3 $r1 #i2c_sda_map +- ld b32 $r2 D[$r3] +- add b32 $r3 $r1 #i2c_scl_map +- ld b32 $r1 D[$r3] +- +- bset $flags $p2 +- push $r13 +- push $r14 +- +- push $r13 +- i2c_trace_init() +- i2c_trace_call(i2c_acquire) +- pop $r13 +- +- cmp b32 $r13 I2C__MSG_RD08 +- bra ne #i2c_recv_not_rd08 +- mov $r5 0 +- i2c_trace_call(i2c_addr) +- bra not $p1 #i2c_recv_done +- extr $r5 $r12 I2C__MSG_DATA0_RD08_REG +- i2c_trace_call(i2c_put_byte) +- bra not $p1 #i2c_recv_done +- mov $r5 1 +- i2c_trace_call(i2c_addr) +- bra not $p1 #i2c_recv_done +- i2c_trace_call(i2c_get_byte) +- bra not $p1 #i2c_recv_done +- ins $r11 $r5 I2C__MSG_DATA1_RD08_VAL +- i2c_trace_call(i2c_stop) +- mov b32 $r11 $r5 +- clear b32 $r7 +- bra #i2c_recv_done +- +- i2c_recv_not_rd08: +- cmp b32 $r13 I2C__MSG_WR08 +- bra ne #i2c_recv_not_wr08 +- mov $r5 0 +- call(i2c_addr) +- bra not $p1 #i2c_recv_done +- extr $r5 $r12 I2C__MSG_DATA0_WR08_REG +- call(i2c_put_byte) +- bra not $p1 #i2c_recv_done +- mov $r5 0 +- call(i2c_addr) +- bra not $p1 #i2c_recv_done +- extr $r5 $r11 I2C__MSG_DATA1_WR08_VAL +- call(i2c_put_byte) +- bra not $p1 #i2c_recv_done +- call(i2c_stop) +- clear b32 $r7 +- extr $r5 $r12 I2C__MSG_DATA0_WR08_SYNC +- bra nz #i2c_recv_done +- bclr $flags $p2 +- bra #i2c_recv_done +- +- i2c_recv_not_wr08: +- +- i2c_recv_done: +- extr $r14 $r12 I2C__MSG_DATA0_PORT +- call(i2c_release) +- +- pop $r14 +- pop $r13 +- bra not $p2 #i2c_recv_exit +- mov b32 $r12 $r7 +- call(send) +- +- i2c_recv_exit: +- ret +- +-// description +-// +-// $r15 - current (i2c) +-// $r0 - zero +-i2c_init: +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc +deleted file mode 100644 +index 98f1c373..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/idle.fuc ++++ /dev/null +@@ -1,84 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_PROC +-process(PROC_IDLE, #idle, #idle_recv) +-#endif +- +-/****************************************************************************** +- * IDLE data segment +- *****************************************************************************/ +-#ifdef INCLUDE_DATA +-#endif +- +-/****************************************************************************** +- * IDLE code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +-// description +-// +-// $r15 - current (idle) +-// $r14 - message +-// $r0 - zero +-idle_recv: +- ret +- +-// description +-// +-// $r15 - current (idle) +-// $r0 - zero +-idle: +- // set our "no interrupt has occurred during our execution" flag +- bset $flags $p0 +- +- // count IDLE invocations for debugging purposes +- nv_iord($r1, NV_PPWR_DSCRATCH(1)) +- add b32 $r1 1 +- nv_iowr(NV_PPWR_DSCRATCH(1), $r1) +- +- // keep looping while there's pending messages for any process +- idle_loop: +- mov $r1 #proc_list_head +- bclr $flags $p2 +- idle_proc: +- // process the process' messages until there's none left +- idle_proc_exec: +- push $r1 +- mov b32 $r14 $r1 +- call(recv) +- pop $r1 +- bra not $p1 #idle_proc_next +- bset $flags $p2 +- bra #idle_proc_exec +- // next process! +- idle_proc_next: +- add b32 $r1 #proc_size +- cmp b32 $r1 $r15 +- bra ne #idle_proc +- bra $p2 #idle_loop +- +- // sleep if no interrupts have occurred +- sleep $p0 +- bra #idle +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc +deleted file mode 100644 +index 5cf5be63..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/kernel.fuc ++++ /dev/null +@@ -1,556 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-/****************************************************************************** +- * kernel data segment +- *****************************************************************************/ +-#ifdef INCLUDE_PROC +-proc_kern: +-process(PROC_KERN, 0, 0) +-proc_list_head: +-#endif +- +-#ifdef INCLUDE_DATA +-proc_list_tail: +-time_prev: .b32 0 +-time_next: .b32 0 +-#endif +- +-/****************************************************************************** +- * kernel code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +- bra #init +- +-// read nv register +-// +-// $r15 - current +-// $r14 - addr +-// $r13 - data (return) +-// $r0 - zero +-rd32: +- nv_iowr(NV_PPWR_MMIO_ADDR, $r14) +- mov $r13 NV_PPWR_MMIO_CTRL_OP_RD +- sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER +- nv_iowr(NV_PPWR_MMIO_CTRL, $r13) +- rd32_wait: +- nv_iord($r13, NV_PPWR_MMIO_CTRL) +- and $r13 NV_PPWR_MMIO_CTRL_STATUS +- bra nz #rd32_wait +- nv_iord($r13, NV_PPWR_MMIO_DATA) +- ret +- +-// write nv register +-// +-// $r15 - current +-// $r14 - addr +-// $r13 - data +-// $r0 - zero +-wr32: +- nv_iowr(NV_PPWR_MMIO_ADDR, $r14) +- nv_iowr(NV_PPWR_MMIO_DATA, $r13) +- mov $r13 NV_PPWR_MMIO_CTRL_OP_WR +- or $r13 NV_PPWR_MMIO_CTRL_MASK_B32_0 +- sethi $r13 NV_PPWR_MMIO_CTRL_TRIGGER +- +-#ifdef NVKM_FALCON_MMIO_TRAP +- push $r13 +- mov $r13 NV_PPWR_INTR_TRIGGER_USER1 +- nv_iowr(NV_PPWR_INTR_TRIGGER, $r13) +- wr32_host: +- nv_iord($r13, NV_PPWR_INTR) +- and $r13 NV_PPWR_INTR_USER1 +- bra nz #wr32_host +- pop $r13 +-#endif +- +- nv_iowr(NV_PPWR_MMIO_CTRL, $r13) +- wr32_wait: +- nv_iord($r13, NV_PPWR_MMIO_CTRL) +- and $r13 NV_PPWR_MMIO_CTRL_STATUS +- bra nz #wr32_wait +- ret +- +-// busy-wait for a period of time +-// +-// $r15 - current +-// $r14 - ns +-// $r0 - zero +-nsec: +- push $r9 +- push $r8 +- nv_iord($r8, NV_PPWR_TIMER_LOW) +- nsec_loop: +- nv_iord($r9, NV_PPWR_TIMER_LOW) +- sub b32 $r9 $r8 +- cmp b32 $r9 $r14 +- bra l #nsec_loop +- pop $r8 +- pop $r9 +- ret +- +-// busy-wait for a period of time +-// +-// $r15 - current +-// $r14 - addr +-// $r13 - mask +-// $r12 - data +-// $r11 - timeout (ns) +-// $r0 - zero +-wait: +- push $r9 +- push $r8 +- nv_iord($r8, NV_PPWR_TIMER_LOW) +- wait_loop: +- nv_rd32($r10, $r14) +- and $r10 $r13 +- cmp b32 $r10 $r12 +- bra e #wait_done +- nv_iord($r9, NV_PPWR_TIMER_LOW) +- sub b32 $r9 $r8 +- cmp b32 $r9 $r11 +- bra l #wait_loop +- wait_done: +- pop $r8 +- pop $r9 +- ret +- +-// $r15 - current (kern) +-// $r14 - process +-// $r8 - NV_PPWR_INTR +-intr_watchdog: +- // read process' timer status, skip if not enabled +- ld b32 $r9 D[$r14 + #proc_time] +- cmp b32 $r9 0 +- bra z #intr_watchdog_next_proc +- +- // subtract last timer's value from process' timer, +- // if it's <= 0 then the timer has expired +- ld b32 $r10 D[$r0 + #time_prev] +- sub b32 $r9 $r10 +- bra g #intr_watchdog_next_time +- mov $r13 KMSG_ALARM +- call(send_proc) +- clear b32 $r9 +- bra #intr_watchdog_next_proc +- +- // otherwise, update the next timer's value if this +- // process' timer is the soonest +- intr_watchdog_next_time: +- // ... or if there's no next timer yet +- ld b32 $r10 D[$r0 + #time_next] +- cmp b32 $r10 0 +- bra z #intr_watchdog_next_time_set +- +- cmp b32 $r9 $r10 +- bra g #intr_watchdog_next_proc +- intr_watchdog_next_time_set: +- st b32 D[$r0 + #time_next] $r9 +- +- // update process' timer status, and advance +- intr_watchdog_next_proc: +- st b32 D[$r14 + #proc_time] $r9 +- add b32 $r14 #proc_size +- cmp b32 $r14 #proc_list_tail +- bra ne #intr_watchdog +- ret +- +-intr: +- push $r0 +- clear b32 $r0 +- push $r8 +- push $r9 +- push $r10 +- push $r11 +- push $r12 +- push $r13 +- push $r14 +- push $r15 +- mov $r15 #proc_kern +- mov $r8 $flags +- push $r8 +- +- nv_iord($r8, NV_PPWR_DSCRATCH(0)) +- add b32 $r8 1 +- nv_iowr(NV_PPWR_DSCRATCH(0), $r8) +- +- nv_iord($r8, NV_PPWR_INTR) +- and $r9 $r8 NV_PPWR_INTR_WATCHDOG +- bra z #intr_skip_watchdog +- st b32 D[$r0 + #time_next] $r0 +- mov $r14 #proc_list_head +- call(intr_watchdog) +- ld b32 $r9 D[$r0 + #time_next] +- cmp b32 $r9 0 +- bra z #intr_skip_watchdog +- nv_iowr(NV_PPWR_WATCHDOG_TIME, $r9) +- st b32 D[$r0 + #time_prev] $r9 +- +- intr_skip_watchdog: +- and $r9 $r8 NV_PPWR_INTR_SUBINTR +- bra z #intr_skip_subintr +- nv_iord($r9, NV_PPWR_SUBINTR) +- and $r10 $r9 NV_PPWR_SUBINTR_FIFO +- bra z #intr_subintr_skip_fifo +- nv_iord($r12, NV_PPWR_FIFO_INTR) +- push $r12 +- mov $r14 (PROC_HOST & 0x0000ffff) +- sethi $r14 (PROC_HOST & 0xffff0000) +- mov $r13 KMSG_FIFO +- call(send) +- pop $r12 +- nv_iowr(NV_PPWR_FIFO_INTR, $r12) +- intr_subintr_skip_fifo: +- nv_iowr(NV_PPWR_SUBINTR, $r9) +- +- intr_skip_subintr: +- and $r9 $r8 NV_PPWR_INTR_PAUSE +- bra z #intr_skip_pause +- and $r10 0xffbf +- +- intr_skip_pause: +- and $r9 $r8 NV_PPWR_INTR_USER0 +- bra z #intr_skip_user0 +- and $r10 0xffbf +- +- intr_skip_user0: +- nv_iowr(NV_PPWR_INTR_ACK, $r8) +- pop $r8 +- mov $flags $r8 +- pop $r15 +- pop $r14 +- pop $r13 +- pop $r12 +- pop $r11 +- pop $r10 +- pop $r9 +- pop $r8 +- pop $r0 +- bclr $flags $p0 +- iret +- +-// calculate the number of ticks in the specified nanoseconds delay +-// +-// $r15 - current +-// $r14 - ns +-// $r14 - ticks (return) +-// $r0 - zero +-ticks_from_ns: +- push $r12 +- push $r11 +- +- /* try not losing precision (multiply then divide) */ +- imm32($r13, HW_TICKS_PER_US) +- call #mulu32_32_64 +- +- /* use an immeditate, it's ok because HW_TICKS_PER_US < 16 bits */ +- div $r12 $r12 1000 +- +- /* check if there wasn't any overflow */ +- cmpu b32 $r11 0 +- bra e #ticks_from_ns_quit +- +- /* let's divide then multiply, too bad for the precision! */ +- div $r14 $r14 1000 +- imm32($r13, HW_TICKS_PER_US) +- call #mulu32_32_64 +- +- /* this cannot overflow as long as HW_TICKS_PER_US < 1000 */ +- +-ticks_from_ns_quit: +- mov b32 $r14 $r12 +- pop $r11 +- pop $r12 +- ret +- +-// calculate the number of ticks in the specified microsecond delay +-// +-// $r15 - current +-// $r14 - us +-// $r14 - ticks (return) +-// $r0 - zero +-ticks_from_us: +- push $r12 +- push $r11 +- +- /* simply multiply $us by HW_TICKS_PER_US */ +- imm32($r13, HW_TICKS_PER_US) +- call #mulu32_32_64 +- mov b32 $r14 $r12 +- +- /* check if there wasn't any overflow */ +- cmpu b32 $r11 0 +- bra e #ticks_from_us_quit +- +- /* Overflow! */ +- clear b32 $r14 +- +-ticks_from_us_quit: +- pop $r11 +- pop $r12 +- ret +- +-// calculate the number of ticks in the specified microsecond delay +-// +-// $r15 - current +-// $r14 - ticks +-// $r14 - us (return) +-// $r0 - zero +-ticks_to_us: +- /* simply divide $ticks by HW_TICKS_PER_US */ +- imm32($r13, HW_TICKS_PER_US) +- div $r14 $r14 $r13 +- +- ret +- +-// request the current process be sent a message after a timeout expires +-// +-// $r15 - current +-// $r14 - ticks (make sure it is < 2^31 to avoid any possible overflow) +-// $r0 - zero +-timer: +- push $r9 +- push $r8 +- +- // interrupts off to prevent racing with timer isr +- bclr $flags ie0 +- +- // if current process already has a timer set, bail +- ld b32 $r8 D[$r15 + #proc_time] +- cmp b32 $r8 0 +- bra g #timer_done +- +- // halt watchdog timer temporarily +- clear b32 $r8 +- nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8) +- +- // find out how much time elapsed since the last update +- // of the watchdog and add this time to the wanted ticks +- nv_iord($r8, NV_PPWR_WATCHDOG_TIME) +- ld b32 $r9 D[$r0 + #time_prev] +- sub b32 $r9 $r8 +- add b32 $r14 $r9 +- st b32 D[$r15 + #proc_time] $r14 +- +- // check for a pending interrupt. if there's one already +- // pending, we can just bail since the timer isr will +- // queue the next soonest right after it's done +- nv_iord($r8, NV_PPWR_INTR) +- and $r8 NV_PPWR_INTR_WATCHDOG +- bra nz #timer_enable +- +- // update the watchdog if this timer should expire first, +- // or if there's no timeout already set +- nv_iord($r8, NV_PPWR_WATCHDOG_TIME) +- cmp b32 $r14 $r0 +- bra e #timer_reset +- cmp b32 $r14 $r8 +- bra g #timer_enable +- timer_reset: +- nv_iowr(NV_PPWR_WATCHDOG_TIME, $r14) +- st b32 D[$r0 + #time_prev] $r14 +- +- // re-enable the watchdog timer +- timer_enable: +- mov $r8 1 +- nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r8) +- +- // interrupts back on +- timer_done: +- bset $flags ie0 +- +- pop $r8 +- pop $r9 +- ret +- +-// send message to another process +-// +-// $r15 - current +-// $r14 - process +-// $r13 - message +-// $r12 - message data 0 +-// $r11 - message data 1 +-// $r0 - zero +-send_proc: +- push $r8 +- push $r9 +- // check for space in queue +- ld b32 $r8 D[$r14 + #proc_qget] +- ld b32 $r9 D[$r14 + #proc_qput] +- xor $r8 #proc_qmaskb +- cmp b32 $r8 $r9 +- bra e #send_done +- +- // enqueue message +- and $r8 $r9 #proc_qmaskp +- shl b32 $r8 $r8 #proc_qlen +- add b32 $r8 #proc_queue +- add b32 $r8 $r14 +- +- ld b32 $r10 D[$r15 + #proc_id] +- st b32 D[$r8 + #msg_process] $r10 +- st b32 D[$r8 + #msg_message] $r13 +- st b32 D[$r8 + #msg_data0] $r12 +- st b32 D[$r8 + #msg_data1] $r11 +- +- // increment PUT +- add b32 $r9 1 +- and $r9 #proc_qmaskf +- st b32 D[$r14 + #proc_qput] $r9 +- bset $flags $p2 +- send_done: +- pop $r9 +- pop $r8 +- ret +- +-// lookup process structure by its name +-// +-// $r15 - current +-// $r14 - process name +-// $r0 - zero +-// +-// $r14 - process +-// $p1 - success +-find: +- push $r8 +- mov $r8 #proc_list_head +- bset $flags $p1 +- find_loop: +- ld b32 $r10 D[$r8 + #proc_id] +- cmp b32 $r10 $r14 +- bra e #find_done +- add b32 $r8 #proc_size +- cmp b32 $r8 #proc_list_tail +- bra ne #find_loop +- bclr $flags $p1 +- find_done: +- mov b32 $r14 $r8 +- pop $r8 +- ret +- +-// send message to another process +-// +-// $r15 - current +-// $r14 - process id +-// $r13 - message +-// $r12 - message data 0 +-// $r11 - message data 1 +-// $r0 - zero +-send: +- call(find) +- bra $p1 #send_proc +- ret +- +-// process single message for a given process +-// +-// $r15 - current +-// $r14 - process +-// $r0 - zero +-recv: +- push $r9 +- push $r8 +- +- ld b32 $r8 D[$r14 + #proc_qget] +- ld b32 $r9 D[$r14 + #proc_qput] +- bclr $flags $p1 +- cmp b32 $r8 $r9 +- bra e #recv_done +- // dequeue message +- and $r9 $r8 #proc_qmaskp +- add b32 $r8 1 +- and $r8 #proc_qmaskf +- st b32 D[$r14 + #proc_qget] $r8 +- ld b32 $r10 D[$r14 + #proc_recv] +- +- push $r15 +- mov $r15 $flags +- push $r15 +- mov b32 $r15 $r14 +- +- shl b32 $r9 $r9 #proc_qlen +- add b32 $r14 $r9 +- add b32 $r14 #proc_queue +- ld b32 $r11 D[$r14 + #msg_data1] +- ld b32 $r12 D[$r14 + #msg_data0] +- ld b32 $r13 D[$r14 + #msg_message] +- ld b32 $r14 D[$r14 + #msg_process] +- +- // process it +- call $r10 +- pop $r15 +- mov $flags $r15 +- bset $flags $p1 +- pop $r15 +- recv_done: +- pop $r8 +- pop $r9 +- ret +- +-init: +- // setup stack +- nv_iord($r1, NV_PPWR_CAPS) +- extr $r1 $r1 9:17 +- shl b32 $r1 8 +- mov $sp $r1 +- +-#ifdef NVKM_FALCON_MMIO_UAS +- // somehow allows the magic "access mmio via D[]" stuff that's +- // used by the nv_rd32/nv_wr32 macros to work +- mov $r1 0x0010 +- sethi $r1 NV_PPWR_UAS_CONFIG_ENABLE +- nv_iowrs(NV_PPWR_UAS_CONFIG, $r1) +-#endif +- +- // route all interrupts except user0/1 and pause to fuc +- mov $r1 0x00e0 +- sethi $r1 0x00000000 +- nv_iowr(NV_PPWR_INTR_ROUTE, $r1) +- +- // enable watchdog and subintr intrs +- mov $r1 NV_PPWR_INTR_EN_CLR_MASK +- nv_iowr(NV_PPWR_INTR_EN_CLR, $r1) +- mov $r1 NV_PPWR_INTR_EN_SET_WATCHDOG +- or $r1 NV_PPWR_INTR_EN_SET_SUBINTR +- nv_iowr(NV_PPWR_INTR_EN_SET, $r1) +- +- // enable interrupts globally +- mov $r1 #intr +- sethi $r1 0x00000000 +- mov $iv0 $r1 +- bset $flags ie0 +- +- // enable watchdog timer +- mov $r1 1 +- nv_iowr(NV_PPWR_WATCHDOG_ENABLE, $r1) +- +- // bootstrap processes, idle process will be last, and not return +- mov $r15 #proc_list_head +- init_proc: +- ld b32 $r1 D[$r15 + #proc_init] +- cmp b32 $r1 0 +- bra z #init_proc +- call $r1 +- add b32 $r15 #proc_size +- bra #init_proc +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc +deleted file mode 100644 +index 96fc984d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc ++++ /dev/null +@@ -1,272 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define GT215 0xa3 +-#define GF100 0xc0 +-#define GF119 0xd9 +-#define GK208 0x108 +- +-#include "os.h" +- +-// IO addresses +-#define NV_PPWR_INTR_TRIGGER 0x0000 +-#define NV_PPWR_INTR_TRIGGER_USER1 0x00000080 +-#define NV_PPWR_INTR_TRIGGER_USER0 0x00000040 +-#define NV_PPWR_INTR_ACK 0x0004 +-#define NV_PPWR_INTR_ACK_SUBINTR 0x00000800 +-#define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002 +-#define NV_PPWR_INTR 0x0008 +-#define NV_PPWR_INTR_SUBINTR 0x00000800 +-#define NV_PPWR_INTR_USER1 0x00000080 +-#define NV_PPWR_INTR_USER0 0x00000040 +-#define NV_PPWR_INTR_PAUSE 0x00000020 +-#define NV_PPWR_INTR_WATCHDOG 0x00000002 +-#define NV_PPWR_INTR_EN_SET 0x0010 +-#define NV_PPWR_INTR_EN_SET_SUBINTR 0x00000800 +-#define NV_PPWR_INTR_EN_SET_WATCHDOG 0x00000002 +-#define NV_PPWR_INTR_EN_CLR 0x0014 +-#define NV_PPWR_INTR_EN_CLR_MASK /* fuck i hate envyas */ -1 +-#define NV_PPWR_INTR_ROUTE 0x001c +-#define NV_PPWR_TIMER_LOW 0x002c +-#define NV_PPWR_WATCHDOG_TIME 0x0034 +-#define NV_PPWR_WATCHDOG_ENABLE 0x0038 +-#define NV_PPWR_CAPS 0x0108 +-#define NV_PPWR_UAS_CONFIG 0x0164 +-#define NV_PPWR_UAS_CONFIG_ENABLE 0x00010000 +-#if NVKM_PPWR_CHIPSET >= GK208 +-#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x0450) +-#endif +-#define NV_PPWR_FIFO_PUT(i) (4 * (i) + 0x04a0) +-#define NV_PPWR_FIFO_GET(i) (4 * (i) + 0x04b0) +-#define NV_PPWR_FIFO_INTR 0x04c0 +-#define NV_PPWR_FIFO_INTR_EN 0x04c4 +-#define NV_PPWR_RFIFO_PUT 0x04c8 +-#define NV_PPWR_RFIFO_GET 0x04cc +-#define NV_PPWR_H2D 0x04d0 +-#define NV_PPWR_D2H 0x04dc +-#if NVKM_PPWR_CHIPSET < GK208 +-#define NV_PPWR_DSCRATCH(i) (4 * (i) + 0x05d0) +-#endif +-#define NV_PPWR_SUBINTR 0x0688 +-#define NV_PPWR_SUBINTR_FIFO 0x00000002 +-#define NV_PPWR_MMIO_ADDR 0x07a0 +-#define NV_PPWR_MMIO_DATA 0x07a4 +-#define NV_PPWR_MMIO_CTRL 0x07ac +-#define NV_PPWR_MMIO_CTRL_TRIGGER 0x00010000 +-#define NV_PPWR_MMIO_CTRL_STATUS 0x00007000 +-#define NV_PPWR_MMIO_CTRL_STATUS_IDLE 0x00000000 +-#define NV_PPWR_MMIO_CTRL_MASK 0x000000f0 +-#define NV_PPWR_MMIO_CTRL_MASK_B32_0 0x000000f0 +-#define NV_PPWR_MMIO_CTRL_OP 0x00000003 +-#define NV_PPWR_MMIO_CTRL_OP_RD 0x00000001 +-#define NV_PPWR_MMIO_CTRL_OP_WR 0x00000002 +-#define NV_PPWR_OUTPUT 0x07c0 +-#define NV_PPWR_OUTPUT_FB_PAUSE 0x00000004 +-#if NVKM_PPWR_CHIPSET < GF119 +-#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00000100 +-#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00000200 +-#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00001000 +-#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00002000 +-#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00004000 +-#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00008000 +-#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00010000 +-#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00020000 +-#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00040000 +-#define NV_PPWR_OUTPUT_I2C_4_SDA 0x00080000 +-#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00100000 +-#define NV_PPWR_OUTPUT_I2C_5_SDA 0x00200000 +-#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00400000 +-#define NV_PPWR_OUTPUT_I2C_6_SDA 0x00800000 +-#define NV_PPWR_OUTPUT_I2C_7_SCL 0x01000000 +-#define NV_PPWR_OUTPUT_I2C_7_SDA 0x02000000 +-#define NV_PPWR_OUTPUT_I2C_8_SCL 0x04000000 +-#define NV_PPWR_OUTPUT_I2C_8_SDA 0x08000000 +-#define NV_PPWR_OUTPUT_I2C_9_SCL 0x10000000 +-#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000 +-#else +-#define NV_PPWR_OUTPUT_I2C_0_SCL 0x00000400 +-#define NV_PPWR_OUTPUT_I2C_1_SCL 0x00000800 +-#define NV_PPWR_OUTPUT_I2C_2_SCL 0x00001000 +-#define NV_PPWR_OUTPUT_I2C_3_SCL 0x00002000 +-#define NV_PPWR_OUTPUT_I2C_4_SCL 0x00004000 +-#define NV_PPWR_OUTPUT_I2C_5_SCL 0x00008000 +-#define NV_PPWR_OUTPUT_I2C_6_SCL 0x00010000 +-#define NV_PPWR_OUTPUT_I2C_7_SCL 0x00020000 +-#define NV_PPWR_OUTPUT_I2C_8_SCL 0x00040000 +-#define NV_PPWR_OUTPUT_I2C_9_SCL 0x00080000 +-#define NV_PPWR_OUTPUT_I2C_0_SDA 0x00100000 +-#define NV_PPWR_OUTPUT_I2C_1_SDA 0x00200000 +-#define NV_PPWR_OUTPUT_I2C_2_SDA 0x00400000 +-#define NV_PPWR_OUTPUT_I2C_3_SDA 0x00800000 +-#define NV_PPWR_OUTPUT_I2C_4_SDA 0x01000000 +-#define NV_PPWR_OUTPUT_I2C_5_SDA 0x02000000 +-#define NV_PPWR_OUTPUT_I2C_6_SDA 0x04000000 +-#define NV_PPWR_OUTPUT_I2C_7_SDA 0x08000000 +-#define NV_PPWR_OUTPUT_I2C_8_SDA 0x10000000 +-#define NV_PPWR_OUTPUT_I2C_9_SDA 0x20000000 +-#endif +-#define NV_PPWR_INPUT 0x07c4 +-#define NV_PPWR_OUTPUT_SET 0x07e0 +-#define NV_PPWR_OUTPUT_SET_FB_PAUSE 0x00000004 +-#define NV_PPWR_OUTPUT_CLR 0x07e4 +-#define NV_PPWR_OUTPUT_CLR_FB_PAUSE 0x00000004 +- +-// Inter-process message format +-.equ #msg_process 0x00 /* send() target, recv() sender */ +-.equ #msg_message 0x04 +-.equ #msg_data0 0x08 +-.equ #msg_data1 0x0c +- +-// Kernel message IDs +-#define KMSG_FIFO 0x00000000 +-#define KMSG_ALARM 0x00000001 +- +-// Process message queue description +-.equ #proc_qlen 4 // log2(size of queue entry in bytes) +-.equ #proc_qnum 2 // log2(max number of entries in queue) +-.equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue +-.equ #proc_qmaskp (#proc_qmaskb - 1) +-.equ #proc_qmaskf ((#proc_qmaskb << 1) - 1) +-.equ #proc_qsize (1 << (#proc_qlen + #proc_qnum)) +- +-// Process table entry +-.equ #proc_id 0x00 +-.equ #proc_init 0x04 +-.equ #proc_recv 0x08 +-.equ #proc_time 0x0c +-.equ #proc_qput 0x10 +-.equ #proc_qget 0x14 +-.equ #proc_queue 0x18 +-.equ #proc_size (0x18 + #proc_qsize) +- +-#define process(id,init,recv) /* +-*/ .b32 id /* +-*/ .b32 init /* +-*/ .b32 recv /* +-*/ .b32 0 /* +-*/ .b32 0 /* +-*/ .b32 0 /* +-*/ .skip 64 +- +-#if NV_PPWR_CHIPSET < GK208 +-#define imm32(reg,val) /* +-*/ movw reg ((val) & 0x0000ffff) /* +-*/ sethi reg ((val) & 0xffff0000) +-#else +-#define imm32(reg,val) /* +-*/ mov reg (val) +-#endif +- +-#ifndef NVKM_FALCON_UNSHIFTED_IO +-#define nv_iord(reg,ior) /* +-*/ mov reg ior /* +-*/ shl b32 reg 6 /* +-*/ iord reg I[reg + 0x000] +-#else +-#define nv_iord(reg,ior) /* +-*/ mov reg ior /* +-*/ iord reg I[reg + 0x000] +-#endif +- +-#ifndef NVKM_FALCON_UNSHIFTED_IO +-#define nv_iowr(ior,reg) /* +-*/ mov $r0 ior /* +-*/ shl b32 $r0 6 /* +-*/ iowr I[$r0 + 0x000] reg /* +-*/ clear b32 $r0 +-#else +-#define nv_iowr(ior,reg) /* +-*/ mov $r0 ior /* +-*/ iowr I[$r0 + 0x000] reg /* +-*/ clear b32 $r0 +-#endif +- +-#ifndef NVKM_FALCON_UNSHIFTED_IO +-#define nv_iowrs(ior,reg) /* +-*/ mov $r0 ior /* +-*/ shl b32 $r0 6 /* +-*/ iowrs I[$r0 + 0x000] reg /* +-*/ clear b32 $r0 +-#else +-#define nv_iowrs(ior,reg) /* +-*/ mov $r0 ior /* +-*/ iowrs I[$r0 + 0x000] reg /* +-*/ clear b32 $r0 +-#endif +- +-#define hash # +-#define fn(a) a +-#ifndef NVKM_FALCON_PC24 +-#define call(a) call fn(hash)a +-#else +-#define call(a) lcall fn(hash)a +-#endif +- +-#ifndef NVKM_FALCON_MMIO_UAS +-#define nv_rd32(reg,addr) /* +-*/ mov b32 $r14 addr /* +-*/ call(rd32) /* +-*/ mov b32 reg $r13 +-#else +-#define nv_rd32(reg,addr) /* +-*/ sethi $r0 0x14000000 /* +-*/ or $r0 addr /* +-*/ ld b32 reg D[$r0] /* +-*/ clear b32 $r0 +-#endif +- +-#if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP) +-#define nv_wr32(addr,reg) /* +-*/ push addr /* +-*/ push reg /* +-*/ pop $r13 /* +-*/ pop $r14 /* +-*/ call(wr32) +-#else +-#define nv_wr32(addr,reg) /* +-*/ sethi $r0 0x14000000 /* +-*/ or $r0 addr /* +-*/ st b32 D[$r0] reg /* +-*/ clear b32 $r0 +-#endif +- +-#define st(size, addr, reg) /* +-*/ movw $r0 addr /* +-*/ st size D[$r0] reg /* +-*/ clear b32 $r0 +- +-#define ld(size, reg, addr) /* +-*/ movw $r0 addr /* +-*/ ld size reg D[$r0] /* +-*/ clear b32 $r0 +- +-// does a 64+64 -> 64 unsigned addition (C = A + B) +-#define addu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /* +-*/ add b32 reg_a_c_lo b_lo /* +-*/ adc b32 reg_a_c_hi b_hi +- +-// does a 64+64 -> 64 substraction (C = A - B) +-#define subu64(reg_a_c_hi, reg_a_c_lo, b_hi, b_lo) /* +-*/ sub b32 reg_a_c_lo b_lo /* +-*/ sbb b32 reg_a_c_hi b_hi +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc +deleted file mode 100644 +index e89789a5..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/memx.fuc ++++ /dev/null +@@ -1,336 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_PROC +-process(PROC_MEMX, #memx_init, #memx_recv) +-#endif +- +-/****************************************************************************** +- * MEMX data segment +- *****************************************************************************/ +-#ifdef INCLUDE_DATA +-.equ #memx_opcode 0 +-.equ #memx_header 2 +-.equ #memx_length 4 +-.equ #memx_func 8 +- +-#define handler(cmd,hdr,len,func) /* +-*/ .b16 MEMX_##cmd /* +-*/ .b16 hdr /* +-*/ .b16 len /* +-*/ .b16 0 /* +-*/ .b32 func +- +-memx_func_head: +-handler(ENTER , 0x0000, 0x0000, #memx_func_enter) +-memx_func_next: +-handler(LEAVE , 0x0000, 0x0000, #memx_func_leave) +-handler(WR32 , 0x0000, 0x0002, #memx_func_wr32) +-handler(WAIT , 0x0004, 0x0000, #memx_func_wait) +-handler(DELAY , 0x0001, 0x0000, #memx_func_delay) +-handler(VBLANK, 0x0001, 0x0000, #memx_func_wait_vblank) +-memx_func_tail: +- +-.equ #memx_func_size #memx_func_next - #memx_func_head +-.equ #memx_func_num (#memx_func_tail - #memx_func_head) / #memx_func_size +- +-memx_ts_start: +-.b32 0 +-memx_ts_end: +-.b32 0 +- +-memx_data_head: +-.skip 0x0800 +-memx_data_tail: +-#endif +- +-/****************************************************************************** +- * MEMX code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +-// description +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_enter: +-#if NVKM_PPWR_CHIPSET == GT215 +- movw $r8 0x1610 +- nv_rd32($r7, $r8) +- imm32($r6, 0xfffffffc) +- and $r7 $r6 +- movw $r6 0x2 +- or $r7 $r6 +- nv_wr32($r8, $r7) +-#else +- movw $r6 0x001620 +- imm32($r7, ~0x00000aa2); +- nv_rd32($r8, $r6) +- and $r8 $r7 +- nv_wr32($r6, $r8) +- +- imm32($r7, ~0x00000001) +- nv_rd32($r8, $r6) +- and $r8 $r7 +- nv_wr32($r6, $r8) +- +- movw $r6 0x0026f0 +- nv_rd32($r8, $r6) +- and $r8 $r7 +- nv_wr32($r6, $r8) +-#endif +- +- mov $r6 NV_PPWR_OUTPUT_SET_FB_PAUSE +- nv_iowr(NV_PPWR_OUTPUT_SET, $r6) +- memx_func_enter_wait: +- nv_iord($r6, NV_PPWR_OUTPUT) +- and $r6 NV_PPWR_OUTPUT_FB_PAUSE +- bra z #memx_func_enter_wait +- +- nv_iord($r6, NV_PPWR_TIMER_LOW) +- st b32 D[$r0 + #memx_ts_start] $r6 +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_leave: +- nv_iord($r6, NV_PPWR_TIMER_LOW) +- st b32 D[$r0 + #memx_ts_end] $r6 +- +- mov $r6 NV_PPWR_OUTPUT_CLR_FB_PAUSE +- nv_iowr(NV_PPWR_OUTPUT_CLR, $r6) +- memx_func_leave_wait: +- nv_iord($r6, NV_PPWR_OUTPUT) +- and $r6 NV_PPWR_OUTPUT_FB_PAUSE +- bra nz #memx_func_leave_wait +- +-#if NVKM_PPWR_CHIPSET == GT215 +- movw $r8 0x1610 +- nv_rd32($r7, $r8) +- imm32($r6, 0xffffffcc) +- and $r7 $r6 +- nv_wr32($r8, $r7) +-#else +- movw $r6 0x0026f0 +- imm32($r7, 0x00000001) +- nv_rd32($r8, $r6) +- or $r8 $r7 +- nv_wr32($r6, $r8) +- +- movw $r6 0x001620 +- nv_rd32($r8, $r6) +- or $r8 $r7 +- nv_wr32($r6, $r8) +- +- imm32($r7, 0x00000aa2); +- nv_rd32($r8, $r6) +- or $r8 $r7 +- nv_wr32($r6, $r8) +-#endif +- ret +- +-#if NVKM_PPWR_CHIPSET < GF119 +-// description +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// +00: head to wait for vblank on +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_wait_vblank: +- ld b32 $r6 D[$r1 + 0x00] +- cmp b32 $r6 0x0 +- bra z #memx_func_wait_vblank_head0 +- cmp b32 $r6 0x1 +- bra z #memx_func_wait_vblank_head1 +- bra #memx_func_wait_vblank_fini +- +- memx_func_wait_vblank_head1: +- movw $r7 0x20 +- bra #memx_func_wait_vblank_0 +- +- memx_func_wait_vblank_head0: +- movw $r7 0x8 +- +- memx_func_wait_vblank_0: +- nv_iord($r6, NV_PPWR_INPUT) +- and $r6 $r7 +- bra nz #memx_func_wait_vblank_0 +- +- memx_func_wait_vblank_1: +- nv_iord($r6, NV_PPWR_INPUT) +- and $r6 $r7 +- bra z #memx_func_wait_vblank_1 +- +- memx_func_wait_vblank_fini: +- add b32 $r1 0x4 +- ret +- +-#else +- +-// XXX: currently no-op +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// +00: head to wait for vblank on +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_wait_vblank: +- add b32 $r1 0x4 +- ret +- +-#endif +- +-// description +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// +00*n: addr +-// +04*n: data +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_wr32: +- ld b32 $r6 D[$r1 + 0x00] +- ld b32 $r5 D[$r1 + 0x04] +- add b32 $r1 0x08 +- nv_wr32($r6, $r5) +- sub b32 $r4 0x02 +- bra nz #memx_func_wr32 +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// +00: addr +-// +04: mask +-// +08: data +-// +0c: timeout (ns) +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_wait: +- nv_iord($r8, NV_PPWR_TIMER_LOW) +- ld b32 $r14 D[$r1 + 0x00] +- ld b32 $r13 D[$r1 + 0x04] +- ld b32 $r12 D[$r1 + 0x08] +- ld b32 $r11 D[$r1 + 0x0c] +- add b32 $r1 0x10 +- call(wait) +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r4 - packet length +-// +00: time (ns) +-// $r3 - opcode desciption +-// $r0 - zero +-memx_func_delay: +- ld b32 $r14 D[$r1 + 0x00] +- add b32 $r1 0x04 +- call(nsec) +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r14 - sender process name +-// $r13 - message (exec) +-// $r12 - head of script +-// $r11 - tail of script +-// $r0 - zero +-memx_exec: +- push $r14 +- push $r13 +- mov b32 $r1 $r12 +- mov b32 $r2 $r11 +- +- memx_exec_next: +- // fetch the packet header +- ld b32 $r3 D[$r1] +- add b32 $r1 4 +- extr $r4 $r3 16:31 +- extr $r3 $r3 0:15 +- +- // execute the opcode handler +- sub b32 $r3 1 +- mulu $r3 #memx_func_size +- ld b32 $r5 D[$r3 + #memx_func_head + #memx_func] +- call $r5 +- +- // keep going, if we haven't reached the end +- cmp b32 $r1 $r2 +- bra l #memx_exec_next +- +- // send completion reply +- ld b32 $r11 D[$r0 + #memx_ts_start] +- ld b32 $r12 D[$r0 + #memx_ts_end] +- sub b32 $r12 $r11 +- nv_iord($r11, NV_PPWR_INPUT) +- pop $r13 +- pop $r14 +- call(send) +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r14 - sender process name +-// $r13 - message +-// $r12 - data0 +-// $r11 - data1 +-// $r0 - zero +-memx_info: +- mov $r12 #memx_data_head +- mov $r11 #memx_data_tail - #memx_data_head +- call(send) +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r14 - sender process name +-// $r13 - message +-// $r12 - data0 +-// $r11 - data1 +-// $r0 - zero +-memx_recv: +- cmp b32 $r13 MEMX_MSG_EXEC +- bra e #memx_exec +- cmp b32 $r13 MEMX_MSG_INFO +- bra e #memx_info +- ret +- +-// description +-// +-// $r15 - current (memx) +-// $r0 - zero +-memx_init: +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc +deleted file mode 100644 +index b439519e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NVKM_PPWR_CHIPSET GK208 +-#define HW_TICKS_PER_US 324 +- +-#define NVKM_FALCON_PC24 +-#define NVKM_FALCON_UNSHIFTED_IO +-//#define NVKM_FALCON_MMIO_UAS +-//#define NVKM_FALCON_MMIO_TRAP +- +-#include "macros.fuc" +- +-.section #nv108_pwr_data +-#define INCLUDE_PROC +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_PROC +- +-#define INCLUDE_DATA +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_DATA +-.align 256 +- +-.section #nv108_pwr_code +-#define INCLUDE_CODE +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_CODE +-.align 256 +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h +deleted file mode 100644 +index 4d278a96..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nv108.fuc.h ++++ /dev/null +@@ -1,1661 +0,0 @@ +-uint32_t nv108_pwr_data[] = { +-/* 0x0000: proc_kern */ +- 0x52544e49, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: proc_list_head */ +- 0x54534f48, +- 0x00000453, +- 0x00000404, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x584d454d, +- 0x0000061c, +- 0x0000060e, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x46524550, +- 0x00000620, +- 0x0000061e, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x5f433249, +- 0x00000a24, +- 0x000008cb, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x54534554, +- 0x00000a45, +- 0x00000a26, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x454c4449, +- 0x00000a50, +- 0x00000a4e, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0268: proc_list_tail */ +-/* 0x0268: time_prev */ +- 0x00000000, +-/* 0x026c: time_next */ +- 0x00000000, +-/* 0x0270: fifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x02f0: rfifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0370: memx_func_head */ +- 0x00000001, +- 0x00000000, +- 0x00000483, +-/* 0x037c: memx_func_next */ +- 0x00000002, +- 0x00000000, +- 0x00000500, +- 0x00000003, +- 0x00000002, +- 0x00000580, +- 0x00040004, +- 0x00000000, +- 0x0000059d, +- 0x00010005, +- 0x00000000, +- 0x000005b7, +- 0x00010006, +- 0x00000000, +- 0x0000057b, +-/* 0x03b8: memx_func_tail */ +-/* 0x03b8: memx_ts_start */ +- 0x00000000, +-/* 0x03bc: memx_ts_end */ +- 0x00000000, +-/* 0x03c0: memx_data_head */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 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0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0bc0: memx_data_tail */ +-/* 0x0bc0: i2c_scl_map */ +- 0x00000400, +- 0x00000800, +- 0x00001000, +- 0x00002000, +- 0x00004000, +- 0x00008000, +- 0x00010000, +- 0x00020000, +- 0x00040000, +- 0x00080000, +-/* 0x0be8: i2c_sda_map */ +- 0x00100000, +- 0x00200000, +- 0x00400000, +- 0x00800000, +- 0x01000000, +- 0x02000000, +- 0x04000000, +- 0x08000000, +- 0x10000000, +- 0x20000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nv108_pwr_code[] = { +- 0x031c0ef5, +-/* 0x0004: rd32 */ +- 0xf607a040, +- 0x04bd000e, +- 0xd3f0010d, +- 0x07ac4001, +- 0xbd000df6, +-/* 0x0019: rd32_wait */ +- 0x07ac4d04, +- 0xf100ddcf, +- 0xf47000d4, +- 0xa44df61b, +- 0x00ddcf07, +-/* 0x002e: wr32 */ +- 0xa04000f8, +- 0x000ef607, +- 0xa44004bd, +- 0x000df607, +- 0x020d04bd, +- 0xf0f0d5f0, +- 0xac4001d3, +- 0x000df607, +-/* 0x004e: wr32_wait */ +- 0xac4d04bd, +- 0x00ddcf07, +- 0x7000d4f1, +- 0xf8f61bf4, +-/* 0x005d: nsec */ +- 0xf990f900, +- 0xcf2c0880, +-/* 0x0066: nsec_loop */ +- 0x2c090088, +- 0xbb0099cf, +- 0x9ea60298, +- 0xfcf61ef4, +- 0xf890fc80, +-/* 0x0079: wait */ +- 0xf990f900, +- 0xcf2c0880, +-/* 0x0082: wait_loop */ +- 0xeeb20088, +- 0x0000047e, +- 0xadfddab2, +- 0xf4aca604, +- 0x2c09100b, +- 0xbb0099cf, +- 0x9ba60298, +-/* 0x009f: wait_done */ +- 0xfce61ef4, +- 0xf890fc80, +-/* 0x00a5: intr_watchdog */ +- 0x03e99800, +- 0xf40096b0, +- 0x0a98280b, +- 0x029abb9a, +- 0x0d0e1cf4, +- 0x02617e01, +- 0xf494bd00, +-/* 0x00c2: intr_watchdog_next_time */ +- 0x0a98140e, +- 0x00a6b09b, +- 0xa6080bf4, +- 0x061cf49a, +-/* 0x00d0: intr_watchdog_next_time_set */ +-/* 0x00d3: intr_watchdog_next_proc */ +- 0xb59b09b5, +- 0xe0b603e9, +- 0x68e6b158, +- 0xc81bf402, +-/* 0x00e2: intr */ +- 0x00f900f8, +- 0x80f904bd, +- 0xa0f990f9, +- 0xc0f9b0f9, +- 0xe0f9d0f9, +- 0x000ff0f9, +- 0xf90188fe, +- 0x04504880, +- 0xb60088cf, +- 0x50400180, +- 0x0008f604, +- 0x080804bd, +- 0xc40088cf, +- 0x0bf40289, +- 0x9b00b51f, +- 0xa57e580e, +- 0x09980000, +- 0x0096b09b, +- 0x000d0bf4, +- 0x0009f634, +- 0x09b504bd, +-/* 0x0135: intr_skip_watchdog */ +- 0x0089e49a, +- 0x360bf408, +- 0xcf068849, +- 0x9ac40099, +- 0x220bf402, +- 0xcf04c04c, +- 0xc0f900cc, +- 0xf14f484e, +- 0x0d5453e3, +- 0x02c27e00, +- 0x40c0fc00, +- 0x0cf604c0, +-/* 0x0167: intr_subintr_skip_fifo */ +- 0x4004bd00, +- 0x09f60688, +-/* 0x016f: intr_skip_subintr */ +- 0xc404bd00, +- 0x0bf42089, +- 0xbfa4f107, +-/* 0x0179: intr_skip_pause */ +- 0x4089c4ff, +- 0xf1070bf4, +-/* 0x0183: intr_skip_user0 */ +- 0x00ffbfa4, +- 0x0008f604, +- 0x80fc04bd, +- 0xfc0088fe, +- 0xfce0fcf0, +- 0xfcc0fcd0, +- 0xfca0fcb0, +- 0xfc80fc90, +- 0x0032f400, +-/* 0x01a6: ticks_from_ns */ +- 0xc0f901f8, +- 0xd7f1b0f9, +- 0xd3f00144, +- 0x7721f500, +- 0xe8ccec03, +- 0x00b4b003, +- 0xec120bf4, +- 0xf103e8ee, +- 0xf00144d7, +- 0x21f500d3, +-/* 0x01ce: ticks_from_ns_quit */ +- 0xceb20377, +- 0xc0fcb0fc, +-/* 0x01d6: ticks_from_us */ +- 0xc0f900f8, +- 0xd7f1b0f9, +- 0xd3f00144, +- 0x7721f500, +- 0xb0ceb203, +- 0x0bf400b4, +-/* 0x01ef: ticks_from_us_quit */ +- 0xfce4bd05, +- 0xf8c0fcb0, +-/* 0x01f5: ticks_to_us */ +- 0x44d7f100, +- 0x00d3f001, +- 0xf8ecedff, +-/* 0x0201: timer */ +- 0xf990f900, +- 0x1032f480, +- 0xb003f898, +- 0x1cf40086, +- 0x0084bd4a, +- 0x0008f638, +- 0x340804bd, +- 0x980088cf, +- 0x98bb9a09, +- 0x00e9bb02, +- 0x0803feb5, +- 0x0088cf08, +- 0xf40284f0, +- 0x34081c1b, +- 0xa60088cf, +- 0x080bf4e0, +- 0x1cf4e8a6, +-/* 0x0245: timer_reset */ +- 0xf634000d, +- 0x04bd000e, +-/* 0x024f: timer_enable */ +- 0x089a0eb5, +- 0xf6380001, +- 0x04bd0008, +-/* 0x0258: timer_done */ +- 0xfc1031f4, +- 0xf890fc80, +-/* 0x0261: send_proc */ +- 0xf980f900, +- 0x05e89890, +- 0xf004e998, +- 0x89a60486, +- 0xc42a0bf4, +- 0x88940398, +- 0x1880b604, +- 0x98008ebb, +- 0x8ab500fa, +- 0x018db500, +- 0xb5028cb5, +- 0x90b6038b, +- 0x0794f001, +- 0xf404e9b5, +-/* 0x029a: send_done */ +- 0x90fc0231, +- 0x00f880fc, +-/* 0x02a0: find */ +- 0x580880f9, +-/* 0x02a7: find_loop */ +- 0x980131f4, +- 0xaea6008a, +- 0xb6100bf4, +- 0x86b15880, +- 0x1bf40268, +- 0x0132f4f1, +-/* 0x02bc: find_done */ +- 0x80fc8eb2, +-/* 0x02c2: send */ +- 0xa07e00f8, +- 0x01f40002, +-/* 0x02cb: recv */ +- 0xf900f89b, +- 0x9880f990, +- 0xe99805e8, +- 0x0132f404, +- 0x0bf489a6, +- 0x0389c43c, +- 0xf00180b6, +- 0xe8b50784, +- 0x02ea9805, +- 0x8ffef0f9, +- 0xb2f0f901, +- 0x049994ef, +- 0xb600e9bb, +- 0xeb9818e0, +- 0x02ec9803, +- 0x9801ed98, +- 0xa5f900ee, +- 0xf8fef0fc, +- 0x0131f400, +-/* 0x0316: recv_done */ +- 0x80fcf0fc, +- 0x00f890fc, +-/* 0x031c: init */ +- 0xcf010841, +- 0x11e70011, +- 0x14b60109, +- 0x0014fe08, +- 0xf000e041, +- 0x1c000013, +- 0xbd0001f6, +- 0x00ff0104, +- 0x0001f614, +- 0x020104bd, +- 0x080015f1, +- 0x01f61000, +- 0x4104bd00, +- 0x13f000e2, +- 0x0010fe00, +- 0x011031f4, +- 0xf6380001, +- 0x04bd0001, +-/* 0x0366: init_proc */ +- 0xf198580f, +- 0x0016b001, +- 0xf9fa0bf4, +- 0x58f0b615, +-/* 0x0377: mulu32_32_64 */ +- 0xf9f20ef4, +- 0xf920f910, +- 0x9540f930, +- 0xd29510e1, +- 0xbdc4bd10, +- 0xc0edffb4, +- 0xb2301dff, +- 0xff34f134, +- 0x1034b6ff, +- 0xbb1045b6, +- 0xb4bb00c3, +- 0x30e2ff01, +- 0x34f134b2, +- 0x34b6ffff, +- 0x1045b610, +- 0xbb00c3bb, +- 0x12ff01b4, +- 0x00b3bb30, +- 0x30fc40fc, +- 0x10fc20fc, +-/* 0x03c6: host_send */ +- 0xb04100f8, +- 0x0011cf04, +- 0xcf04a042, +- 0x12a60022, +- 0xc42e0bf4, +- 0xee94071e, +- 0x70e0b704, +- 0x03eb9802, +- 0x9802ec98, +- 0xee9801ed, +- 0x02c27e00, +- 0x0110b600, +- 0x400f1ec4, +- 0x0ef604b0, +- 0xf404bd00, +-/* 0x0402: host_send_done */ +- 0x00f8c70e, +-/* 0x0404: host_recv */ +- 0xf14e4941, +- 0xa6525413, +- 0xb90bf4e1, +-/* 0x0410: host_recv_wait */ +- 0xcf04cc41, +- 0xc8420011, +- 0x0022cf04, +- 0xa60816f0, +- 0xef0bf412, +- 0xb60723c4, +- 0x30b70434, +- 0x3bb502f0, +- 0x023cb503, +- 0xb5013db5, +- 0x20b6003e, +- 0x0f24f001, +- 0xf604c840, +- 0x04bd0002, +- 0x00004002, +- 0xbd0002f6, +-/* 0x0453: host_init */ +- 0x4100f804, +- 0x14b60080, +- 0x7015f110, +- 0x04d04002, +- 0xbd0001f6, +- 0x00804104, +- 0xf11014b6, +- 0x4002f015, +- 0x01f604dc, +- 0x0104bd00, +- 0x04c44001, +- 0xbd0001f6, +-/* 0x0483: memx_func_enter */ +- 0xf100f804, +- 0xf1162067, +- 0xf1f55d77, +- 0xb2ffff73, +- 0x00047e6e, +- 0xfdd8b200, +- 0x60f90487, +- 0xd0fc80f9, +- 0x2e7ee0fc, +- 0x77f10000, +- 0x73f1fffe, +- 0x6eb2ffff, +- 0x0000047e, +- 0x87fdd8b2, +- 0xf960f904, +- 0xfcd0fc80, +- 0x002e7ee0, +- 0xf067f100, +- 0x7e6eb226, +- 0xb2000004, +- 0x0487fdd8, +- 0x80f960f9, +- 0xe0fcd0fc, +- 0x00002e7e, +- 0xe0400406, +- 0x0006f607, +-/* 0x04ea: memx_func_enter_wait */ +- 0xc04604bd, +- 0x0066cf07, +- 0xf40464f0, +- 0x2c06f70b, +- 0xb50066cf, +- 0x00f8ee06, +-/* 0x0500: memx_func_leave */ +- 0x66cf2c06, +- 0xef06b500, +- 0xe4400406, +- 0x0006f607, +-/* 0x0512: memx_func_leave_wait */ +- 0xc04604bd, +- 0x0066cf07, +- 0xf40464f0, +- 0x67f1f71b, +- 0x77f126f0, +- 0x73f00001, +- 0x7e6eb200, +- 0xb2000004, +- 0x0587fdd8, +- 0x80f960f9, +- 0xe0fcd0fc, +- 0x00002e7e, +- 0x162067f1, +- 0x047e6eb2, +- 0xd8b20000, +- 0xf90587fd, +- 0xfc80f960, +- 0x7ee0fcd0, +- 0xf100002e, +- 0xf00aa277, +- 0x6eb20073, +- 0x0000047e, +- 0x87fdd8b2, +- 0xf960f905, +- 0xfcd0fc80, +- 0x002e7ee0, +-/* 0x057b: memx_func_wait_vblank */ +- 0xb600f800, +- 0x00f80410, +-/* 0x0580: memx_func_wr32 */ +- 0x98001698, +- 0x10b60115, +- 0xf960f908, +- 0xfcd0fc50, +- 0x002e7ee0, +- 0x0242b600, +- 0xf8e81bf4, +-/* 0x059d: memx_func_wait */ +- 0xcf2c0800, +- 0x1e980088, +- 0x011d9800, +- 0x98021c98, +- 0x10b6031b, +- 0x00797e10, +-/* 0x05b7: memx_func_delay */ +- 0x9800f800, +- 0x10b6001e, +- 0x005d7e04, +-/* 0x05c3: memx_exec */ +- 0xf900f800, +- 0xb2d0f9e0, +-/* 0x05cb: memx_exec_next */ +- 0x98b2b2c1, +- 0x10b60013, +- 0xf034e704, +- 0xe033e701, +- 0x0132b601, +- 0x980c30f0, +- 0x55f9de35, +- 0x1ef412a6, +- 0xee0b98e5, +- 0xbbef0c98, +- 0xc44b02cb, +- 0x00bbcf07, +- 0xe0fcd0fc, +- 0x0002c27e, +-/* 0x0602: memx_info */ +- 0xc04c00f8, +- 0x08004b03, +- 0x0002c27e, +-/* 0x060e: memx_recv */ +- 0xd6b000f8, +- 0xb20bf401, +- 0xf400d6b0, +- 0x00f8eb0b, +-/* 0x061c: memx_init */ +-/* 0x061e: perf_recv */ +- 0x00f800f8, +-/* 0x0620: perf_init */ +-/* 0x0622: i2c_drive_scl */ +- 0x36b000f8, +- 0x0d0bf400, +- 0xf607e040, +- 0x04bd0001, +-/* 0x0632: i2c_drive_scl_lo */ +- 0xe44000f8, +- 0x0001f607, +- 0x00f804bd, +-/* 0x063c: i2c_drive_sda */ +- 0xf40036b0, +- 0xe0400d0b, +- 0x0002f607, +- 0x00f804bd, +-/* 0x064c: i2c_drive_sda_lo */ +- 0xf607e440, +- 0x04bd0002, +-/* 0x0656: i2c_sense_scl */ +- 0x32f400f8, +- 0x07c44301, +- 0xfd0033cf, +- 0x0bf40431, +- 0x0131f406, +-/* 0x0668: i2c_sense_scl_done */ +-/* 0x066a: i2c_sense_sda */ +- 0x32f400f8, +- 0x07c44301, +- 0xfd0033cf, +- 0x0bf40432, +- 0x0131f406, +-/* 0x067c: i2c_sense_sda_done */ +-/* 0x067e: i2c_raise_scl */ +- 0x40f900f8, +- 0x03089844, +- 0x06227e01, +-/* 0x0689: i2c_raise_scl_wait */ +- 0x03e84e00, +- 0x00005d7e, +- 0x0006567e, +- 0xb60901f4, +- 0x1bf40142, +-/* 0x069d: i2c_raise_scl_done */ +- 0xf840fcef, +-/* 0x06a1: i2c_start */ +- 0x06567e00, +- 0x0d11f400, +- 0x00066a7e, +- 0xf40611f4, +-/* 0x06b2: i2c_start_rep */ +- 0x00032e0e, +- 0x0006227e, +- 0x3c7e0103, +- 0x76bb0006, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0x7e50fc04, +- 0xb600067e, +- 0x11f40464, +-/* 0x06dd: i2c_start_send */ +- 0x7e00031d, +- 0x4e00063c, +- 0x5d7e1388, +- 0x00030000, +- 0x0006227e, +- 0x7e13884e, +-/* 0x06f7: i2c_start_out */ +- 0xf800005d, +-/* 0x06f9: i2c_stop */ +- 0x7e000300, +- 0x03000622, +- 0x063c7e00, +- 0x03e84e00, +- 0x00005d7e, +- 0x227e0103, +- 0x884e0006, +- 0x005d7e13, +- 0x7e010300, +- 0x4e00063c, +- 0x5d7e1388, +- 0x00f80000, +-/* 0x0728: i2c_bitw */ +- 0x00063c7e, +- 0x7e03e84e, +- 0xbb00005d, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x00067e7e, +- 0xf40464b6, +- 0x884e1711, +- 0x005d7e13, +- 0x7e000300, +- 0x4e000622, +- 0x5d7e1388, +-/* 0x0766: i2c_bitw_out */ +- 0x00f80000, +-/* 0x0768: i2c_bitr */ +- 0x3c7e0103, +- 0xe84e0006, +- 0x005d7e03, +- 0x0076bb00, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x7e7e50fc, +- 0x64b60006, +- 0x1a11f404, +- 0x00066a7e, +- 0x227e0003, +- 0x884e0006, +- 0x005d7e13, +- 0x013cf000, +-/* 0x07ab: i2c_bitr_done */ +- 0xf80131f4, +-/* 0x07ad: i2c_get_byte */ +- 0x04000500, +-/* 0x07b1: i2c_get_byte_next */ +- 0x0154b608, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x07687e50, +- 0x0464b600, +- 0xfd2a11f4, +- 0x42b60553, +- 0xd81bf401, +- 0x76bb0103, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0x7e50fc04, +- 0xb6000728, +-/* 0x07fa: i2c_get_byte_done */ +- 0x00f80464, +-/* 0x07fc: i2c_put_byte */ +-/* 0x07fe: i2c_put_byte_next */ +- 0x42b60804, +- 0x3854ff01, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x07287e50, +- 0x0464b600, +- 0xb03411f4, +- 0x1bf40046, +- 0x0076bbd8, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x687e50fc, +- 0x64b60007, +- 0x0f11f404, +- 0xb00076bb, +- 0x1bf40136, +- 0x0132f406, +-/* 0x0854: i2c_put_byte_done */ +-/* 0x0856: i2c_addr */ +- 0x76bb00f8, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0x7e50fc04, +- 0xb60006a1, +- 0x11f40464, +- 0x2ec3e729, +- 0x0134b601, +- 0xbb0553fd, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x0007fc7e, +-/* 0x089b: i2c_addr_done */ +- 0xf80464b6, +-/* 0x089d: i2c_acquire_addr */ +- 0xf8cec700, +- 0xb705e4b6, +- 0xf8d014e0, +-/* 0x08a9: i2c_acquire */ +- 0x089d7e00, +- 0x00047e00, +- 0x03d9f000, +- 0x00002e7e, +-/* 0x08ba: i2c_release */ +- 0x9d7e00f8, +- 0x047e0008, +- 0xdaf00000, +- 0x002e7e03, +-/* 0x08cb: i2c_recv */ +- 0xf400f800, +- 0xc1c70132, +- 0x0214b6f8, +- 0xf52816b0, +- 0xb801371f, +- 0x000be813, +- 0xb8003298, +- 0x000bc013, +- 0xf4003198, +- 0xd0f90231, +- 0xd0f9e0f9, +- 0x000067f1, +- 0x100063f1, +- 0xbb016792, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x0008a97e, +- 0xfc0464b6, +- 0x00d6b0d0, +- 0x00b01bf5, +- 0x76bb0005, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0x7e50fc04, +- 0xb6000856, +- 0x11f50464, +- 0xc5c700cc, +- 0x0076bbe0, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0xfc7e50fc, +- 0x64b60007, +- 0xa911f504, +- 0xbb010500, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x0008567e, +- 0xf50464b6, +- 0xbb008711, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x0007ad7e, +- 0xf40464b6, +- 0x5bcb6711, +- 0x0076bbe0, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0xf97e50fc, +- 0x64b60006, +- 0xbd5bb204, +- 0x410ef474, +-/* 0x09d0: i2c_recv_not_rd08 */ +- 0xf401d6b0, +- 0x00053b1b, +- 0x0008567e, +- 0xc73211f4, +- 0xfc7ee0c5, +- 0x11f40007, +- 0x7e000528, +- 0xf4000856, +- 0xb5c71f11, +- 0x07fc7ee0, +- 0x1511f400, +- 0x0006f97e, +- 0xc5c774bd, +- 0x091bf408, +- 0xf40232f4, +-/* 0x0a0e: i2c_recv_not_wr08 */ +-/* 0x0a0e: i2c_recv_done */ +- 0xcec7030e, +- 0x08ba7ef8, +- 0xfce0fc00, +- 0x0912f4d0, +- 0xc27e7cb2, +-/* 0x0a22: i2c_recv_exit */ +- 0x00f80002, +-/* 0x0a24: i2c_init */ +-/* 0x0a26: test_recv */ +- 0x584100f8, +- 0x0011cf04, +- 0x400110b6, +- 0x01f60458, +- 0xf104bd00, +- 0xf1d900e7, +- 0x7e134fe3, +- 0xf8000201, +-/* 0x0a45: test_init */ +- 0x08004e00, +- 0x0002017e, +-/* 0x0a4e: idle_recv */ +- 0x00f800f8, +-/* 0x0a50: idle */ +- 0x410031f4, +- 0x11cf0454, +- 0x0110b600, +- 0xf6045440, +- 0x04bd0001, +-/* 0x0a64: idle_loop */ +- 0x32f45801, +-/* 0x0a69: idle_proc */ +-/* 0x0a69: idle_proc_exec */ +- 0xb210f902, +- 0x02cb7e1e, +- 0xf410fc00, +- 0x31f40911, +- 0xf00ef402, +-/* 0x0a7c: idle_proc_next */ +- 0xa65810b6, +- 0xe81bf41f, +- 0xf4e002f4, +- 0x0ef40028, +- 0x000000c6, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc +deleted file mode 100644 +index daa06c1c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NVKM_PPWR_CHIPSET GT215 +-#define HW_TICKS_PER_US 203 // should be 202.5 +- +-//#define NVKM_FALCON_PC24 +-//#define NVKM_FALCON_UNSHIFTED_IO +-//#define NVKM_FALCON_MMIO_UAS +-//#define NVKM_FALCON_MMIO_TRAP +- +-#include "macros.fuc" +- +-.section #nva3_pwr_data +-#define INCLUDE_PROC +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_PROC +- +-#define INCLUDE_DATA +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_DATA +-.align 256 +- +-.section #nva3_pwr_code +-#define INCLUDE_CODE +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_CODE +-.align 256 +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h +deleted file mode 100644 +index 64e97baa..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nva3.fuc.h ++++ /dev/null +@@ -1,1731 +0,0 @@ +-uint32_t nva3_pwr_data[] = { +-/* 0x0000: proc_kern */ +- 0x52544e49, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: proc_list_head */ +- 0x54534f48, +- 0x00000512, +- 0x000004af, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x584d454d, +- 0x000006e0, +- 0x000006d2, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x46524550, +- 0x000006e4, +- 0x000006e2, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x5f433249, +- 0x00000b14, +- 0x000009b7, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x54534554, +- 0x00000b3d, +- 0x00000b16, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x454c4449, +- 0x00000b49, +- 0x00000b47, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0268: proc_list_tail */ +-/* 0x0268: time_prev */ +- 0x00000000, +-/* 0x026c: time_next */ +- 0x00000000, +-/* 0x0270: fifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x02f0: rfifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0370: memx_func_head */ +- 0x00000001, +- 0x00000000, +- 0x00000551, +-/* 0x037c: memx_func_next */ +- 0x00000002, +- 0x00000000, +- 0x000005a8, +- 0x00000003, +- 0x00000002, +- 0x0000063a, +- 0x00040004, +- 0x00000000, +- 0x00000656, +- 0x00010005, +- 0x00000000, +- 0x00000673, +- 0x00010006, +- 0x00000000, +- 0x000005f8, +-/* 0x03b8: memx_func_tail */ +-/* 0x03b8: memx_ts_start */ +- 0x00000000, +-/* 0x03bc: memx_ts_end */ +- 0x00000000, +-/* 0x03c0: memx_data_head */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0bc0: memx_data_tail */ +-/* 0x0bc0: i2c_scl_map */ +- 0x00001000, +- 0x00004000, +- 0x00010000, +- 0x00000100, +- 0x00040000, +- 0x00100000, +- 0x00400000, +- 0x01000000, +- 0x04000000, +- 0x10000000, +-/* 0x0be8: i2c_sda_map */ +- 0x00002000, +- 0x00008000, +- 0x00020000, +- 0x00000200, +- 0x00080000, +- 0x00200000, +- 0x00800000, +- 0x02000000, +- 0x08000000, +- 0x20000000, +-/* 0x0c10: i2c_ctrl */ +- 0x0000e138, +- 0x0000e150, +- 0x0000e168, +- 0x0000e180, +- 0x0000e254, +- 0x0000e274, +- 0x0000e764, +- 0x0000e780, +- 0x0000e79c, +- 0x0000e7b8, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nva3_pwr_code[] = { +- 0x039e0ef5, +-/* 0x0004: rd32 */ +- 0x07a007f1, +- 0xd00604b6, +- 0x04bd000e, +- 0xf001d7f0, +- 0x07f101d3, +- 0x04b607ac, +- 0x000dd006, +-/* 0x0022: rd32_wait */ +- 0xd7f104bd, +- 0xd4b607ac, +- 0x00ddcf06, +- 0x7000d4f1, +- 0xf1f21bf4, +- 0xb607a4d7, +- 0xddcf06d4, +-/* 0x003f: wr32 */ +- 0xf100f800, +- 0xb607a007, +- 0x0ed00604, +- 0xf104bd00, +- 0xb607a407, +- 0x0dd00604, +- 0xf004bd00, +- 0xd5f002d7, +- 0x01d3f0f0, +- 0x07ac07f1, +- 0xd00604b6, +- 0x04bd000d, +-/* 0x006c: wr32_wait */ +- 0x07acd7f1, +- 0xcf06d4b6, +- 0xd4f100dd, +- 0x1bf47000, +-/* 0x007f: nsec */ +- 0xf900f8f2, +- 0xf080f990, +- 0x84b62c87, +- 0x0088cf06, +-/* 0x008c: nsec_loop */ +- 0xb62c97f0, +- 0x99cf0694, +- 0x0298bb00, +- 0xf4069eb8, +- 0x80fcf11e, +- 0x00f890fc, +-/* 0x00a4: wait */ +- 0x80f990f9, +- 0xb62c87f0, +- 0x88cf0684, +-/* 0x00b1: wait_loop */ +- 0x02eeb900, +- 0xb90421f4, +- 0xadfd02da, +- 0x06acb804, +- 0xf0150bf4, +- 0x94b62c97, +- 0x0099cf06, +- 0xb80298bb, +- 0x1ef4069b, +-/* 0x00d5: wait_done */ +- 0xfc80fcdf, +-/* 0x00db: intr_watchdog */ +- 0x9800f890, +- 0x96b003e9, +- 0x2a0bf400, +- 0xbb9a0a98, +- 0x1cf4029a, +- 0x01d7f00f, +- 0x02dd21f5, +- 0x0ef494bd, +-/* 0x00f9: intr_watchdog_next_time */ +- 0x9b0a9815, +- 0xf400a6b0, +- 0x9ab8090b, +- 0x061cf406, +-/* 0x0108: intr_watchdog_next_time_set */ +-/* 0x010b: intr_watchdog_next_proc */ +- 0x809b0980, +- 0xe0b603e9, +- 0x68e6b158, +- 0xc61bf402, +-/* 0x011a: intr */ +- 0x00f900f8, +- 0x80f904bd, +- 0xa0f990f9, +- 0xc0f9b0f9, +- 0xe0f9d0f9, +- 0xf7f0f0f9, +- 0x0188fe00, +- 0x87f180f9, +- 0x84b605d0, +- 0x0088cf06, +- 0xf10180b6, +- 0xb605d007, +- 0x08d00604, +- 0xf004bd00, +- 0x84b60887, +- 0x0088cf06, +- 0xf40289c4, +- 0x0080230b, +- 0x58e7f09b, +- 0x98db21f4, +- 0x96b09b09, +- 0x110bf400, +- 0xb63407f0, +- 0x09d00604, +- 0x8004bd00, +-/* 0x017e: intr_skip_watchdog */ +- 0x89e49a09, +- 0x0bf40800, +- 0x8897f148, +- 0x0694b606, +- 0xc40099cf, +- 0x0bf4029a, +- 0xc0c7f12c, +- 0x06c4b604, +- 0xf900cccf, +- 0x48e7f1c0, +- 0x53e3f14f, +- 0x00d7f054, +- 0x034221f5, +- 0x07f1c0fc, +- 0x04b604c0, +- 0x000cd006, +-/* 0x01be: intr_subintr_skip_fifo */ +- 0x07f104bd, +- 0x04b60688, +- 0x0009d006, +-/* 0x01ca: intr_skip_subintr */ +- 0x89c404bd, +- 0x070bf420, +- 0xffbfa4f1, +-/* 0x01d4: intr_skip_pause */ +- 0xf44089c4, +- 0xa4f1070b, +-/* 0x01de: intr_skip_user0 */ +- 0x07f0ffbf, +- 0x0604b604, +- 0xbd0008d0, +- 0xfe80fc04, +- 0xf0fc0088, +- 0xd0fce0fc, +- 0xb0fcc0fc, +- 0x90fca0fc, +- 0x00fc80fc, +- 0xf80032f4, +-/* 0x0205: ticks_from_ns */ +- 0xf9c0f901, +- 0xcbd7f1b0, +- 0x00d3f000, +- 0x041321f5, +- 0x03e8ccec, +- 0xf400b4b0, +- 0xeeec120b, +- 0xd7f103e8, +- 0xd3f000cb, +- 0x1321f500, +-/* 0x022d: ticks_from_ns_quit */ +- 0x02ceb904, +- 0xc0fcb0fc, +-/* 0x0236: ticks_from_us */ +- 0xc0f900f8, +- 0xd7f1b0f9, +- 0xd3f000cb, +- 0x1321f500, +- 0x02ceb904, +- 0xf400b4b0, +- 0xe4bd050b, +-/* 0x0250: ticks_from_us_quit */ +- 0xc0fcb0fc, +-/* 0x0256: ticks_to_us */ +- 0xd7f100f8, +- 0xd3f000cb, +- 0xecedff00, +-/* 0x0262: timer */ +- 0x90f900f8, +- 0x32f480f9, +- 0x03f89810, +- 0xf40086b0, +- 0x84bd651c, +- 0xb63807f0, +- 0x08d00604, +- 0xf004bd00, +- 0x84b63487, +- 0x0088cf06, +- 0xbb9a0998, +- 0xe9bb0298, +- 0x03fe8000, +- 0xb60887f0, +- 0x88cf0684, +- 0x0284f000, +- 0xf0261bf4, +- 0x84b63487, +- 0x0088cf06, +- 0xf406e0b8, +- 0xe8b8090b, +- 0x111cf406, +-/* 0x02b8: timer_reset */ +- 0xb63407f0, +- 0x0ed00604, +- 0x8004bd00, +-/* 0x02c6: timer_enable */ +- 0x87f09a0e, +- 0x3807f001, +- 0xd00604b6, +- 0x04bd0008, +-/* 0x02d4: timer_done */ +- 0xfc1031f4, +- 0xf890fc80, +-/* 0x02dd: send_proc */ +- 0xf980f900, +- 0x05e89890, +- 0xf004e998, +- 0x89b80486, +- 0x2a0bf406, +- 0x940398c4, +- 0x80b60488, +- 0x008ebb18, +- 0x8000fa98, +- 0x8d80008a, +- 0x028c8001, +- 0xb6038b80, +- 0x94f00190, +- 0x04e98007, +-/* 0x0317: send_done */ +- 0xfc0231f4, +- 0xf880fc90, +-/* 0x031d: find */ +- 0xf080f900, +- 0x31f45887, +-/* 0x0325: find_loop */ +- 0x008a9801, +- 0xf406aeb8, +- 0x80b6100b, +- 0x6886b158, +- 0xf01bf402, +-/* 0x033b: find_done */ +- 0xb90132f4, +- 0x80fc028e, +-/* 0x0342: send */ +- 0x21f500f8, +- 0x01f4031d, +-/* 0x034b: recv */ +- 0xf900f897, +- 0x9880f990, +- 0xe99805e8, +- 0x0132f404, +- 0xf40689b8, +- 0x89c43d0b, +- 0x0180b603, +- 0x800784f0, +- 0xea9805e8, +- 0xfef0f902, +- 0xf0f9018f, +- 0x9402efb9, +- 0xe9bb0499, +- 0x18e0b600, +- 0x9803eb98, +- 0xed9802ec, +- 0x00ee9801, +- 0xf0fca5f9, +- 0xf400f8fe, +- 0xf0fc0131, +-/* 0x0398: recv_done */ +- 0x90fc80fc, +-/* 0x039e: init */ +- 0x17f100f8, +- 0x14b60108, +- 0x0011cf06, +- 0x010911e7, +- 0xfe0814b6, +- 0x17f10014, +- 0x13f000e0, +- 0x1c07f000, +- 0xd00604b6, +- 0x04bd0001, +- 0xf0ff17f0, +- 0x04b61407, +- 0x0001d006, +- 0x17f004bd, +- 0x0015f102, +- 0x1007f008, +- 0xd00604b6, +- 0x04bd0001, +- 0x011a17f1, +- 0xfe0013f0, +- 0x31f40010, +- 0x0117f010, +- 0xb63807f0, +- 0x01d00604, +- 0xf004bd00, +-/* 0x0402: init_proc */ +- 0xf19858f7, +- 0x0016b001, +- 0xf9fa0bf4, +- 0x58f0b615, +-/* 0x0413: mulu32_32_64 */ +- 0xf9f20ef4, +- 0xf920f910, +- 0x9540f930, +- 0xd29510e1, +- 0xbdc4bd10, +- 0xc0edffb4, +- 0xb9301dff, +- 0x34f10234, +- 0x34b6ffff, +- 0x1045b610, +- 0xbb00c3bb, +- 0xe2ff01b4, +- 0x0234b930, +- 0xffff34f1, +- 0xb61034b6, +- 0xc3bb1045, +- 0x01b4bb00, +- 0xbb3012ff, +- 0x40fc00b3, +- 0x20fc30fc, +- 0x00f810fc, +-/* 0x0464: host_send */ +- 0x04b017f1, +- 0xcf0614b6, +- 0x27f10011, +- 0x24b604a0, +- 0x0022cf06, +- 0xf40612b8, +- 0x1ec4320b, +- 0x04ee9407, +- 0x0270e0b7, +- 0x9803eb98, +- 0xed9802ec, +- 0x00ee9801, +- 0x034221f5, +- 0xc40110b6, +- 0x07f10f1e, +- 0x04b604b0, +- 0x000ed006, +- 0x0ef404bd, +-/* 0x04ad: host_send_done */ +-/* 0x04af: host_recv */ +- 0xf100f8ba, +- 0xf14e4917, +- 0xb8525413, +- 0x0bf406e1, +-/* 0x04bd: host_recv_wait */ +- 0xcc17f1aa, +- 0x0614b604, +- 0xf10011cf, +- 0xb604c827, +- 0x22cf0624, +- 0x0816f000, +- 0xf40612b8, +- 0x23c4e60b, +- 0x0434b607, +- 0x02f030b7, +- 0x80033b80, +- 0x3d80023c, +- 0x003e8001, +- 0xf00120b6, +- 0x07f10f24, +- 0x04b604c8, +- 0x0002d006, +- 0x27f004bd, +- 0x0007f040, +- 0xd00604b6, +- 0x04bd0002, +-/* 0x0512: host_init */ +- 0x17f100f8, +- 0x14b60080, +- 0x7015f110, +- 0xd007f102, +- 0x0604b604, +- 0xbd0001d0, +- 0x8017f104, +- 0x1014b600, +- 0x02f015f1, +- 0x04dc07f1, +- 0xd00604b6, +- 0x04bd0001, +- 0xf10117f0, +- 0xb604c407, +- 0x01d00604, +- 0xf804bd00, +-/* 0x0551: memx_func_enter */ +- 0x1087f100, +- 0x028eb916, +- 0xb90421f4, +- 0x67f102d7, +- 0x63f1fffc, +- 0x76fdffff, +- 0x0267f104, +- 0x0576fd00, +- 0x70f980f9, +- 0xe0fcd0fc, +- 0xf03f21f4, +- 0x07f10467, +- 0x04b607e0, +- 0x0006d006, +-/* 0x058a: memx_func_enter_wait */ +- 0x67f104bd, +- 0x64b607c0, +- 0x0066cf06, +- 0xf40464f0, +- 0x67f0f30b, +- 0x0664b62c, +- 0x800066cf, +- 0x00f8ee06, +-/* 0x05a8: memx_func_leave */ +- 0xb62c67f0, +- 0x66cf0664, +- 0xef068000, +- 0xf10467f0, +- 0xb607e407, +- 0x06d00604, +-/* 0x05c3: memx_func_leave_wait */ +- 0xf104bd00, +- 0xb607c067, +- 0x66cf0664, +- 0x0464f000, +- 0xf1f31bf4, +- 0xb9161087, +- 0x21f4028e, +- 0x02d7b904, +- 0xffcc67f1, +- 0xffff63f1, +- 0xf90476fd, +- 0xfc70f980, +- 0xf4e0fcd0, +- 0x00f83f21, +-/* 0x05f8: memx_func_wait_vblank */ +- 0xb0001698, +- 0x0bf40066, +- 0x0166b013, +- 0xf4060bf4, +-/* 0x060a: memx_func_wait_vblank_head1 */ +- 0x77f12e0e, +- 0x0ef40020, +-/* 0x0611: memx_func_wait_vblank_head0 */ +- 0x0877f107, +-/* 0x0615: memx_func_wait_vblank_0 */ +- 0xc467f100, +- 0x0664b607, +- 0xfd0066cf, +- 0x1bf40467, +-/* 0x0625: memx_func_wait_vblank_1 */ +- 0xc467f1f3, +- 0x0664b607, +- 0xfd0066cf, +- 0x0bf40467, +-/* 0x0635: memx_func_wait_vblank_fini */ +- 0x0410b6f3, +-/* 0x063a: memx_func_wr32 */ +- 0x169800f8, +- 0x01159800, +- 0xf90810b6, +- 0xfc50f960, +- 0xf4e0fcd0, +- 0x42b63f21, +- 0xe91bf402, +-/* 0x0656: memx_func_wait */ +- 0x87f000f8, +- 0x0684b62c, +- 0x980088cf, +- 0x1d98001e, +- 0x021c9801, +- 0xb6031b98, +- 0x21f41010, +-/* 0x0673: memx_func_delay */ +- 0x9800f8a4, +- 0x10b6001e, +- 0x7f21f404, +-/* 0x067e: memx_exec */ +- 0xe0f900f8, +- 0xc1b9d0f9, +- 0x02b2b902, +-/* 0x0688: memx_exec_next */ +- 0xb6001398, +- 0x34e70410, +- 0x33e701f0, +- 0x32b601e0, +- 0x0c30f001, +- 0xf9de3598, +- 0x0612b855, +- 0x98e41ef4, +- 0x0c98ee0b, +- 0x02cbbbef, +- 0x07c4b7f1, +- 0xcf06b4b6, +- 0xd0fc00bb, +- 0x21f5e0fc, +- 0x00f80342, +-/* 0x06c4: memx_info */ +- 0x03c0c7f1, +- 0x0800b7f1, +- 0x034221f5, +-/* 0x06d2: memx_recv */ +- 0xd6b000f8, +- 0xa90bf401, +- 0xf400d6b0, +- 0x00f8e90b, +-/* 0x06e0: memx_init */ +-/* 0x06e2: perf_recv */ +- 0x00f800f8, +-/* 0x06e4: perf_init */ +-/* 0x06e6: i2c_drive_scl */ +- 0x36b000f8, +- 0x110bf400, +- 0x07e007f1, +- 0xd00604b6, +- 0x04bd0001, +-/* 0x06fa: i2c_drive_scl_lo */ +- 0x07f100f8, +- 0x04b607e4, +- 0x0001d006, +- 0x00f804bd, +-/* 0x0708: i2c_drive_sda */ +- 0xf40036b0, +- 0x07f1110b, +- 0x04b607e0, +- 0x0002d006, +- 0x00f804bd, +-/* 0x071c: i2c_drive_sda_lo */ +- 0x07e407f1, +- 0xd00604b6, +- 0x04bd0002, +-/* 0x072a: i2c_sense_scl */ +- 0x32f400f8, +- 0xc437f101, +- 0x0634b607, +- 0xfd0033cf, +- 0x0bf40431, +- 0x0131f406, +-/* 0x0740: i2c_sense_scl_done */ +-/* 0x0742: i2c_sense_sda */ +- 0x32f400f8, +- 0xc437f101, +- 0x0634b607, +- 0xfd0033cf, +- 0x0bf40432, +- 0x0131f406, +-/* 0x0758: i2c_sense_sda_done */ +-/* 0x075a: i2c_raise_scl */ +- 0x40f900f8, +- 0x089847f1, +- 0xf50137f0, +-/* 0x0767: i2c_raise_scl_wait */ +- 0xf106e621, +- 0xf403e8e7, +- 0x21f57f21, +- 0x01f4072a, +- 0x0142b609, +-/* 0x077b: i2c_raise_scl_done */ +- 0xfcef1bf4, +-/* 0x077f: i2c_start */ +- 0xf500f840, +- 0xf4072a21, +- 0x21f50d11, +- 0x11f40742, +- 0x300ef406, +-/* 0x0790: i2c_start_rep */ +- 0xf50037f0, +- 0xf006e621, +- 0x21f50137, +- 0x76bb0708, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb6075a21, +- 0x11f40464, +-/* 0x07bd: i2c_start_send */ +- 0x0037f01f, +- 0x070821f5, +- 0x1388e7f1, +- 0xf07f21f4, +- 0x21f50037, +- 0xe7f106e6, +- 0x21f41388, +-/* 0x07d9: i2c_start_out */ +-/* 0x07db: i2c_stop */ +- 0xf000f87f, +- 0x21f50037, +- 0x37f006e6, +- 0x0821f500, +- 0xe8e7f107, +- 0x7f21f403, +- 0xf50137f0, +- 0xf106e621, +- 0xf41388e7, +- 0x37f07f21, +- 0x0821f501, +- 0x88e7f107, +- 0x7f21f413, +-/* 0x080e: i2c_bitw */ +- 0x21f500f8, +- 0xe7f10708, +- 0x21f403e8, +- 0x0076bb7f, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b6075a, +- 0x1811f404, +- 0x1388e7f1, +- 0xf07f21f4, +- 0x21f50037, +- 0xe7f106e6, +- 0x21f41388, +-/* 0x084d: i2c_bitw_out */ +-/* 0x084f: i2c_bitr */ +- 0xf000f87f, +- 0x21f50137, +- 0xe7f10708, +- 0x21f403e8, +- 0x0076bb7f, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b6075a, +- 0x1b11f404, +- 0x074221f5, +- 0xf50037f0, +- 0xf106e621, +- 0xf41388e7, +- 0x3cf07f21, +- 0x0131f401, +-/* 0x0894: i2c_bitr_done */ +-/* 0x0896: i2c_get_byte */ +- 0x57f000f8, +- 0x0847f000, +-/* 0x089c: i2c_get_byte_next */ +- 0xbb0154b6, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x084f21f5, +- 0xf40464b6, +- 0x53fd2b11, +- 0x0142b605, +- 0xf0d81bf4, +- 0x76bb0137, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb6080e21, +-/* 0x08e6: i2c_get_byte_done */ +- 0x00f80464, +-/* 0x08e8: i2c_put_byte */ +-/* 0x08eb: i2c_put_byte_next */ +- 0xb60847f0, +- 0x54ff0142, +- 0x0076bb38, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b6080e, +- 0x3411f404, +- 0xf40046b0, +- 0x76bbd81b, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb6084f21, +- 0x11f40464, +- 0x0076bb0f, +- 0xf40136b0, +- 0x32f4061b, +-/* 0x0941: i2c_put_byte_done */ +-/* 0x0943: i2c_addr */ +- 0xbb00f801, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x077f21f5, +- 0xf40464b6, +- 0xc3e72911, +- 0x34b6012e, +- 0x0553fd01, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xe821f550, +- 0x0464b608, +-/* 0x0988: i2c_addr_done */ +-/* 0x098a: i2c_acquire_addr */ +- 0xcec700f8, +- 0x02e4b6f8, +- 0x0c10e0b7, +- 0xf800ee98, +-/* 0x0999: i2c_acquire */ +- 0x8a21f500, +- 0x0421f409, +- 0xf403d9f0, +- 0x00f83f21, +-/* 0x09a8: i2c_release */ +- 0x098a21f5, +- 0xf00421f4, +- 0x21f403da, +-/* 0x09b7: i2c_recv */ +- 0xf400f83f, +- 0xc1c70132, +- 0x0214b6f8, +- 0xf52816b0, +- 0xa0013a1f, +- 0x980be813, +- 0x13a00032, +- 0x31980bc0, +- 0x0231f400, +- 0xe0f9d0f9, +- 0x67f1d0f9, +- 0x63f10000, +- 0x67921000, +- 0x0076bb01, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b60999, +- 0xb0d0fc04, +- 0x1bf500d6, +- 0x57f000b3, +- 0x0076bb00, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b60943, +- 0xd011f504, +- 0xe0c5c700, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xe821f550, +- 0x0464b608, +- 0x00ad11f5, +- 0xbb0157f0, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x094321f5, +- 0xf50464b6, +- 0xbb008a11, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x089621f5, +- 0xf40464b6, +- 0x5bcb6a11, +- 0x0076bbe0, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b607db, +- 0x025bb904, +- 0x0ef474bd, +-/* 0x0abd: i2c_recv_not_rd08 */ +- 0x01d6b043, +- 0xf03d1bf4, +- 0x21f50057, +- 0x11f40943, +- 0xe0c5c733, +- 0x08e821f5, +- 0xf02911f4, +- 0x21f50057, +- 0x11f40943, +- 0xe0b5c71f, +- 0x08e821f5, +- 0xf51511f4, +- 0xbd07db21, +- 0x08c5c774, +- 0xf4091bf4, +- 0x0ef40232, +-/* 0x0afd: i2c_recv_not_wr08 */ +-/* 0x0afd: i2c_recv_done */ +- 0xf8cec703, +- 0x09a821f5, +- 0xd0fce0fc, +- 0xb90a12f4, +- 0x21f5027c, +-/* 0x0b12: i2c_recv_exit */ +- 0x00f80342, +-/* 0x0b14: i2c_init */ +-/* 0x0b16: test_recv */ +- 0x17f100f8, +- 0x14b605d8, +- 0x0011cf06, +- 0xf10110b6, +- 0xb605d807, +- 0x01d00604, +- 0xf104bd00, +- 0xf1d900e7, +- 0xf5134fe3, +- 0xf8026221, +-/* 0x0b3d: test_init */ +- 0x00e7f100, +- 0x6221f508, +-/* 0x0b47: idle_recv */ +- 0xf800f802, +-/* 0x0b49: idle */ +- 0x0031f400, +- 0x05d417f1, +- 0xcf0614b6, +- 0x10b60011, +- 0xd407f101, +- 0x0604b605, +- 0xbd0001d0, +-/* 0x0b65: idle_loop */ +- 0x5817f004, +-/* 0x0b6b: idle_proc */ +-/* 0x0b6b: idle_proc_exec */ +- 0xf90232f4, +- 0x021eb910, +- 0x034b21f5, +- 0x11f410fc, +- 0x0231f409, +-/* 0x0b7f: idle_proc_next */ +- 0xb6ef0ef4, +- 0x1fb85810, +- 0xe61bf406, +- 0xf4dd02f4, +- 0x0ef40028, +- 0x000000bb, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc +deleted file mode 100644 +index 21bf8cc7..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NVKM_PPWR_CHIPSET GF100 +-#define HW_TICKS_PER_US 203 // should be 202.5 +- +-//#define NVKM_FALCON_PC24 +-//#define NVKM_FALCON_UNSHIFTED_IO +-//#define NVKM_FALCON_MMIO_UAS +-//#define NVKM_FALCON_MMIO_TRAP +- +-#include "macros.fuc" +- +-.section #nvc0_pwr_data +-#define INCLUDE_PROC +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_PROC +- +-#define INCLUDE_DATA +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_DATA +-.align 256 +- +-.section #nvc0_pwr_code +-#define INCLUDE_CODE +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_CODE +-.align 256 +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h +deleted file mode 100644 +index ca30fa40..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvc0.fuc.h ++++ /dev/null +@@ -1,1731 +0,0 @@ +-uint32_t nvc0_pwr_data[] = { +-/* 0x0000: proc_kern */ +- 0x52544e49, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: proc_list_head */ +- 0x54534f48, +- 0x00000512, +- 0x000004af, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x584d454d, +- 0x0000074b, +- 0x0000073d, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x46524550, +- 0x0000074f, +- 0x0000074d, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x5f433249, +- 0x00000b7f, +- 0x00000a22, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x54534554, +- 0x00000ba8, +- 0x00000b81, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x454c4449, +- 0x00000bb4, +- 0x00000bb2, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0268: proc_list_tail */ +-/* 0x0268: time_prev */ +- 0x00000000, +-/* 0x026c: time_next */ +- 0x00000000, +-/* 0x0270: fifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x02f0: rfifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0370: memx_func_head */ +- 0x00000001, +- 0x00000000, +- 0x00000551, +-/* 0x037c: memx_func_next */ +- 0x00000002, +- 0x00000000, +- 0x000005db, +- 0x00000003, +- 0x00000002, +- 0x000006a5, +- 0x00040004, +- 0x00000000, +- 0x000006c1, +- 0x00010005, +- 0x00000000, +- 0x000006de, +- 0x00010006, +- 0x00000000, +- 0x00000663, +-/* 0x03b8: memx_func_tail */ +-/* 0x03b8: memx_ts_start */ +- 0x00000000, +-/* 0x03bc: memx_ts_end */ +- 0x00000000, +-/* 0x03c0: memx_data_head */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0bc0: memx_data_tail */ +-/* 0x0bc0: i2c_scl_map */ +- 0x00001000, +- 0x00004000, +- 0x00010000, +- 0x00000100, +- 0x00040000, +- 0x00100000, +- 0x00400000, +- 0x01000000, +- 0x04000000, +- 0x10000000, +-/* 0x0be8: i2c_sda_map */ +- 0x00002000, +- 0x00008000, +- 0x00020000, +- 0x00000200, +- 0x00080000, +- 0x00200000, +- 0x00800000, +- 0x02000000, +- 0x08000000, +- 0x20000000, +-/* 0x0c10: i2c_ctrl */ +- 0x0000e138, +- 0x0000e150, +- 0x0000e168, +- 0x0000e180, +- 0x0000e254, +- 0x0000e274, +- 0x0000e764, +- 0x0000e780, +- 0x0000e79c, +- 0x0000e7b8, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nvc0_pwr_code[] = { +- 0x039e0ef5, +-/* 0x0004: rd32 */ +- 0x07a007f1, +- 0xd00604b6, +- 0x04bd000e, +- 0xf001d7f0, +- 0x07f101d3, +- 0x04b607ac, +- 0x000dd006, +-/* 0x0022: rd32_wait */ +- 0xd7f104bd, +- 0xd4b607ac, +- 0x00ddcf06, +- 0x7000d4f1, +- 0xf1f21bf4, +- 0xb607a4d7, +- 0xddcf06d4, +-/* 0x003f: wr32 */ +- 0xf100f800, +- 0xb607a007, +- 0x0ed00604, +- 0xf104bd00, +- 0xb607a407, +- 0x0dd00604, +- 0xf004bd00, +- 0xd5f002d7, +- 0x01d3f0f0, +- 0x07ac07f1, +- 0xd00604b6, +- 0x04bd000d, +-/* 0x006c: wr32_wait */ +- 0x07acd7f1, +- 0xcf06d4b6, +- 0xd4f100dd, +- 0x1bf47000, +-/* 0x007f: nsec */ +- 0xf900f8f2, +- 0xf080f990, +- 0x84b62c87, +- 0x0088cf06, +-/* 0x008c: nsec_loop */ +- 0xb62c97f0, +- 0x99cf0694, +- 0x0298bb00, +- 0xf4069eb8, +- 0x80fcf11e, +- 0x00f890fc, +-/* 0x00a4: wait */ +- 0x80f990f9, +- 0xb62c87f0, +- 0x88cf0684, +-/* 0x00b1: wait_loop */ +- 0x02eeb900, +- 0xb90421f4, +- 0xadfd02da, +- 0x06acb804, +- 0xf0150bf4, +- 0x94b62c97, +- 0x0099cf06, +- 0xb80298bb, +- 0x1ef4069b, +-/* 0x00d5: wait_done */ +- 0xfc80fcdf, +-/* 0x00db: intr_watchdog */ +- 0x9800f890, +- 0x96b003e9, +- 0x2a0bf400, +- 0xbb9a0a98, +- 0x1cf4029a, +- 0x01d7f00f, +- 0x02dd21f5, +- 0x0ef494bd, +-/* 0x00f9: intr_watchdog_next_time */ +- 0x9b0a9815, +- 0xf400a6b0, +- 0x9ab8090b, +- 0x061cf406, +-/* 0x0108: intr_watchdog_next_time_set */ +-/* 0x010b: intr_watchdog_next_proc */ +- 0x809b0980, +- 0xe0b603e9, +- 0x68e6b158, +- 0xc61bf402, +-/* 0x011a: intr */ +- 0x00f900f8, +- 0x80f904bd, +- 0xa0f990f9, +- 0xc0f9b0f9, +- 0xe0f9d0f9, +- 0xf7f0f0f9, +- 0x0188fe00, +- 0x87f180f9, +- 0x84b605d0, +- 0x0088cf06, +- 0xf10180b6, +- 0xb605d007, +- 0x08d00604, +- 0xf004bd00, +- 0x84b60887, +- 0x0088cf06, +- 0xf40289c4, +- 0x0080230b, +- 0x58e7f09b, +- 0x98db21f4, +- 0x96b09b09, +- 0x110bf400, +- 0xb63407f0, +- 0x09d00604, +- 0x8004bd00, +-/* 0x017e: intr_skip_watchdog */ +- 0x89e49a09, +- 0x0bf40800, +- 0x8897f148, +- 0x0694b606, +- 0xc40099cf, +- 0x0bf4029a, +- 0xc0c7f12c, +- 0x06c4b604, +- 0xf900cccf, +- 0x48e7f1c0, +- 0x53e3f14f, +- 0x00d7f054, +- 0x034221f5, +- 0x07f1c0fc, +- 0x04b604c0, +- 0x000cd006, +-/* 0x01be: intr_subintr_skip_fifo */ +- 0x07f104bd, +- 0x04b60688, +- 0x0009d006, +-/* 0x01ca: intr_skip_subintr */ +- 0x89c404bd, +- 0x070bf420, +- 0xffbfa4f1, +-/* 0x01d4: intr_skip_pause */ +- 0xf44089c4, +- 0xa4f1070b, +-/* 0x01de: intr_skip_user0 */ +- 0x07f0ffbf, +- 0x0604b604, +- 0xbd0008d0, +- 0xfe80fc04, +- 0xf0fc0088, +- 0xd0fce0fc, +- 0xb0fcc0fc, +- 0x90fca0fc, +- 0x00fc80fc, +- 0xf80032f4, +-/* 0x0205: ticks_from_ns */ +- 0xf9c0f901, +- 0xcbd7f1b0, +- 0x00d3f000, +- 0x041321f5, +- 0x03e8ccec, +- 0xf400b4b0, +- 0xeeec120b, +- 0xd7f103e8, +- 0xd3f000cb, +- 0x1321f500, +-/* 0x022d: ticks_from_ns_quit */ +- 0x02ceb904, +- 0xc0fcb0fc, +-/* 0x0236: ticks_from_us */ +- 0xc0f900f8, +- 0xd7f1b0f9, +- 0xd3f000cb, +- 0x1321f500, +- 0x02ceb904, +- 0xf400b4b0, +- 0xe4bd050b, +-/* 0x0250: ticks_from_us_quit */ +- 0xc0fcb0fc, +-/* 0x0256: ticks_to_us */ +- 0xd7f100f8, +- 0xd3f000cb, +- 0xecedff00, +-/* 0x0262: timer */ +- 0x90f900f8, +- 0x32f480f9, +- 0x03f89810, +- 0xf40086b0, +- 0x84bd651c, +- 0xb63807f0, +- 0x08d00604, +- 0xf004bd00, +- 0x84b63487, +- 0x0088cf06, +- 0xbb9a0998, +- 0xe9bb0298, +- 0x03fe8000, +- 0xb60887f0, +- 0x88cf0684, +- 0x0284f000, +- 0xf0261bf4, +- 0x84b63487, +- 0x0088cf06, +- 0xf406e0b8, +- 0xe8b8090b, +- 0x111cf406, +-/* 0x02b8: timer_reset */ +- 0xb63407f0, +- 0x0ed00604, +- 0x8004bd00, +-/* 0x02c6: timer_enable */ +- 0x87f09a0e, +- 0x3807f001, +- 0xd00604b6, +- 0x04bd0008, +-/* 0x02d4: timer_done */ +- 0xfc1031f4, +- 0xf890fc80, +-/* 0x02dd: send_proc */ +- 0xf980f900, +- 0x05e89890, +- 0xf004e998, +- 0x89b80486, +- 0x2a0bf406, +- 0x940398c4, +- 0x80b60488, +- 0x008ebb18, +- 0x8000fa98, +- 0x8d80008a, +- 0x028c8001, +- 0xb6038b80, +- 0x94f00190, +- 0x04e98007, +-/* 0x0317: send_done */ +- 0xfc0231f4, +- 0xf880fc90, +-/* 0x031d: find */ +- 0xf080f900, +- 0x31f45887, +-/* 0x0325: find_loop */ +- 0x008a9801, +- 0xf406aeb8, +- 0x80b6100b, +- 0x6886b158, +- 0xf01bf402, +-/* 0x033b: find_done */ +- 0xb90132f4, +- 0x80fc028e, +-/* 0x0342: send */ +- 0x21f500f8, +- 0x01f4031d, +-/* 0x034b: recv */ +- 0xf900f897, +- 0x9880f990, +- 0xe99805e8, +- 0x0132f404, +- 0xf40689b8, +- 0x89c43d0b, +- 0x0180b603, +- 0x800784f0, +- 0xea9805e8, +- 0xfef0f902, +- 0xf0f9018f, +- 0x9402efb9, +- 0xe9bb0499, +- 0x18e0b600, +- 0x9803eb98, +- 0xed9802ec, +- 0x00ee9801, +- 0xf0fca5f9, +- 0xf400f8fe, +- 0xf0fc0131, +-/* 0x0398: recv_done */ +- 0x90fc80fc, +-/* 0x039e: init */ +- 0x17f100f8, +- 0x14b60108, +- 0x0011cf06, +- 0x010911e7, +- 0xfe0814b6, +- 0x17f10014, +- 0x13f000e0, +- 0x1c07f000, +- 0xd00604b6, +- 0x04bd0001, +- 0xf0ff17f0, +- 0x04b61407, +- 0x0001d006, +- 0x17f004bd, +- 0x0015f102, +- 0x1007f008, +- 0xd00604b6, +- 0x04bd0001, +- 0x011a17f1, +- 0xfe0013f0, +- 0x31f40010, +- 0x0117f010, +- 0xb63807f0, +- 0x01d00604, +- 0xf004bd00, +-/* 0x0402: init_proc */ +- 0xf19858f7, +- 0x0016b001, +- 0xf9fa0bf4, +- 0x58f0b615, +-/* 0x0413: mulu32_32_64 */ +- 0xf9f20ef4, +- 0xf920f910, +- 0x9540f930, +- 0xd29510e1, +- 0xbdc4bd10, +- 0xc0edffb4, +- 0xb9301dff, +- 0x34f10234, +- 0x34b6ffff, +- 0x1045b610, +- 0xbb00c3bb, +- 0xe2ff01b4, +- 0x0234b930, +- 0xffff34f1, +- 0xb61034b6, +- 0xc3bb1045, +- 0x01b4bb00, +- 0xbb3012ff, +- 0x40fc00b3, +- 0x20fc30fc, +- 0x00f810fc, +-/* 0x0464: host_send */ +- 0x04b017f1, +- 0xcf0614b6, +- 0x27f10011, +- 0x24b604a0, +- 0x0022cf06, +- 0xf40612b8, +- 0x1ec4320b, +- 0x04ee9407, +- 0x0270e0b7, +- 0x9803eb98, +- 0xed9802ec, +- 0x00ee9801, +- 0x034221f5, +- 0xc40110b6, +- 0x07f10f1e, +- 0x04b604b0, +- 0x000ed006, +- 0x0ef404bd, +-/* 0x04ad: host_send_done */ +-/* 0x04af: host_recv */ +- 0xf100f8ba, +- 0xf14e4917, +- 0xb8525413, +- 0x0bf406e1, +-/* 0x04bd: host_recv_wait */ +- 0xcc17f1aa, +- 0x0614b604, +- 0xf10011cf, +- 0xb604c827, +- 0x22cf0624, +- 0x0816f000, +- 0xf40612b8, +- 0x23c4e60b, +- 0x0434b607, +- 0x02f030b7, +- 0x80033b80, +- 0x3d80023c, +- 0x003e8001, +- 0xf00120b6, +- 0x07f10f24, +- 0x04b604c8, +- 0x0002d006, +- 0x27f004bd, +- 0x0007f040, +- 0xd00604b6, +- 0x04bd0002, +-/* 0x0512: host_init */ +- 0x17f100f8, +- 0x14b60080, +- 0x7015f110, +- 0xd007f102, +- 0x0604b604, +- 0xbd0001d0, +- 0x8017f104, +- 0x1014b600, +- 0x02f015f1, +- 0x04dc07f1, +- 0xd00604b6, +- 0x04bd0001, +- 0xf10117f0, +- 0xb604c407, +- 0x01d00604, +- 0xf804bd00, +-/* 0x0551: memx_func_enter */ +- 0x2067f100, +- 0x5d77f116, +- 0xff73f1f5, +- 0x026eb9ff, +- 0xb90421f4, +- 0x87fd02d8, +- 0xf960f904, +- 0xfcd0fc80, +- 0x3f21f4e0, +- 0xfffe77f1, +- 0xffff73f1, +- 0xf4026eb9, +- 0xd8b90421, +- 0x0487fd02, +- 0x80f960f9, +- 0xe0fcd0fc, +- 0xf13f21f4, +- 0xb926f067, +- 0x21f4026e, +- 0x02d8b904, +- 0xf90487fd, +- 0xfc80f960, +- 0xf4e0fcd0, +- 0x67f03f21, +- 0xe007f104, +- 0x0604b607, +- 0xbd0006d0, +-/* 0x05bd: memx_func_enter_wait */ +- 0xc067f104, +- 0x0664b607, +- 0xf00066cf, +- 0x0bf40464, +- 0x2c67f0f3, +- 0xcf0664b6, +- 0x06800066, +-/* 0x05db: memx_func_leave */ +- 0xf000f8ee, +- 0x64b62c67, +- 0x0066cf06, +- 0xf0ef0680, +- 0x07f10467, +- 0x04b607e4, +- 0x0006d006, +-/* 0x05f6: memx_func_leave_wait */ +- 0x67f104bd, +- 0x64b607c0, +- 0x0066cf06, +- 0xf40464f0, +- 0x67f1f31b, +- 0x77f126f0, +- 0x73f00001, +- 0x026eb900, +- 0xb90421f4, +- 0x87fd02d8, +- 0xf960f905, +- 0xfcd0fc80, +- 0x3f21f4e0, +- 0x162067f1, +- 0xf4026eb9, +- 0xd8b90421, +- 0x0587fd02, +- 0x80f960f9, +- 0xe0fcd0fc, +- 0xf13f21f4, +- 0xf00aa277, +- 0x6eb90073, +- 0x0421f402, +- 0xfd02d8b9, +- 0x60f90587, +- 0xd0fc80f9, +- 0x21f4e0fc, +-/* 0x0663: memx_func_wait_vblank */ +- 0x9800f83f, +- 0x66b00016, +- 0x130bf400, +- 0xf40166b0, +- 0x0ef4060b, +-/* 0x0675: memx_func_wait_vblank_head1 */ +- 0x2077f12e, +- 0x070ef400, +-/* 0x067c: memx_func_wait_vblank_head0 */ +- 0x000877f1, +-/* 0x0680: memx_func_wait_vblank_0 */ +- 0x07c467f1, +- 0xcf0664b6, +- 0x67fd0066, +- 0xf31bf404, +-/* 0x0690: memx_func_wait_vblank_1 */ +- 0x07c467f1, +- 0xcf0664b6, +- 0x67fd0066, +- 0xf30bf404, +-/* 0x06a0: memx_func_wait_vblank_fini */ +- 0xf80410b6, +-/* 0x06a5: memx_func_wr32 */ +- 0x00169800, +- 0xb6011598, +- 0x60f90810, +- 0xd0fc50f9, +- 0x21f4e0fc, +- 0x0242b63f, +- 0xf8e91bf4, +-/* 0x06c1: memx_func_wait */ +- 0x2c87f000, +- 0xcf0684b6, +- 0x1e980088, +- 0x011d9800, +- 0x98021c98, +- 0x10b6031b, +- 0xa421f410, +-/* 0x06de: memx_func_delay */ +- 0x1e9800f8, +- 0x0410b600, +- 0xf87f21f4, +-/* 0x06e9: memx_exec */ +- 0xf9e0f900, +- 0x02c1b9d0, +-/* 0x06f3: memx_exec_next */ +- 0x9802b2b9, +- 0x10b60013, +- 0xf034e704, +- 0xe033e701, +- 0x0132b601, +- 0x980c30f0, +- 0x55f9de35, +- 0xf40612b8, +- 0x0b98e41e, +- 0xef0c98ee, +- 0xf102cbbb, +- 0xb607c4b7, +- 0xbbcf06b4, +- 0xfcd0fc00, +- 0x4221f5e0, +-/* 0x072f: memx_info */ +- 0xf100f803, +- 0xf103c0c7, +- 0xf50800b7, +- 0xf8034221, +-/* 0x073d: memx_recv */ +- 0x01d6b000, +- 0xb0a90bf4, +- 0x0bf400d6, +-/* 0x074b: memx_init */ +- 0xf800f8e9, +-/* 0x074d: perf_recv */ +-/* 0x074f: perf_init */ +- 0xf800f800, +-/* 0x0751: i2c_drive_scl */ +- 0x0036b000, +- 0xf1110bf4, +- 0xb607e007, +- 0x01d00604, +- 0xf804bd00, +-/* 0x0765: i2c_drive_scl_lo */ +- 0xe407f100, +- 0x0604b607, +- 0xbd0001d0, +-/* 0x0773: i2c_drive_sda */ +- 0xb000f804, +- 0x0bf40036, +- 0xe007f111, +- 0x0604b607, +- 0xbd0002d0, +-/* 0x0787: i2c_drive_sda_lo */ +- 0xf100f804, +- 0xb607e407, +- 0x02d00604, +- 0xf804bd00, +-/* 0x0795: i2c_sense_scl */ +- 0x0132f400, +- 0x07c437f1, +- 0xcf0634b6, +- 0x31fd0033, +- 0x060bf404, +-/* 0x07ab: i2c_sense_scl_done */ +- 0xf80131f4, +-/* 0x07ad: i2c_sense_sda */ +- 0x0132f400, +- 0x07c437f1, +- 0xcf0634b6, +- 0x32fd0033, +- 0x060bf404, +-/* 0x07c3: i2c_sense_sda_done */ +- 0xf80131f4, +-/* 0x07c5: i2c_raise_scl */ +- 0xf140f900, +- 0xf0089847, +- 0x21f50137, +-/* 0x07d2: i2c_raise_scl_wait */ +- 0xe7f10751, +- 0x21f403e8, +- 0x9521f57f, +- 0x0901f407, +- 0xf40142b6, +-/* 0x07e6: i2c_raise_scl_done */ +- 0x40fcef1b, +-/* 0x07ea: i2c_start */ +- 0x21f500f8, +- 0x11f40795, +- 0xad21f50d, +- 0x0611f407, +-/* 0x07fb: i2c_start_rep */ +- 0xf0300ef4, +- 0x21f50037, +- 0x37f00751, +- 0x7321f501, +- 0x0076bb07, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b607c5, +- 0x1f11f404, +-/* 0x0828: i2c_start_send */ +- 0xf50037f0, +- 0xf1077321, +- 0xf41388e7, +- 0x37f07f21, +- 0x5121f500, +- 0x88e7f107, +- 0x7f21f413, +-/* 0x0844: i2c_start_out */ +-/* 0x0846: i2c_stop */ +- 0x37f000f8, +- 0x5121f500, +- 0x0037f007, +- 0x077321f5, +- 0x03e8e7f1, +- 0xf07f21f4, +- 0x21f50137, +- 0xe7f10751, +- 0x21f41388, +- 0x0137f07f, +- 0x077321f5, +- 0x1388e7f1, +- 0xf87f21f4, +-/* 0x0879: i2c_bitw */ +- 0x7321f500, +- 0xe8e7f107, +- 0x7f21f403, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xc521f550, +- 0x0464b607, +- 0xf11811f4, +- 0xf41388e7, +- 0x37f07f21, +- 0x5121f500, +- 0x88e7f107, +- 0x7f21f413, +-/* 0x08b8: i2c_bitw_out */ +-/* 0x08ba: i2c_bitr */ +- 0x37f000f8, +- 0x7321f501, +- 0xe8e7f107, +- 0x7f21f403, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xc521f550, +- 0x0464b607, +- 0xf51b11f4, +- 0xf007ad21, +- 0x21f50037, +- 0xe7f10751, +- 0x21f41388, +- 0x013cf07f, +-/* 0x08ff: i2c_bitr_done */ +- 0xf80131f4, +-/* 0x0901: i2c_get_byte */ +- 0x0057f000, +-/* 0x0907: i2c_get_byte_next */ +- 0xb60847f0, +- 0x76bb0154, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb608ba21, +- 0x11f40464, +- 0x0553fd2b, +- 0xf40142b6, +- 0x37f0d81b, +- 0x0076bb01, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b60879, +-/* 0x0951: i2c_get_byte_done */ +-/* 0x0953: i2c_put_byte */ +- 0xf000f804, +-/* 0x0956: i2c_put_byte_next */ +- 0x42b60847, +- 0x3854ff01, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x7921f550, +- 0x0464b608, +- 0xb03411f4, +- 0x1bf40046, +- 0x0076bbd8, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b608ba, +- 0x0f11f404, +- 0xb00076bb, +- 0x1bf40136, +- 0x0132f406, +-/* 0x09ac: i2c_put_byte_done */ +-/* 0x09ae: i2c_addr */ +- 0x76bb00f8, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb607ea21, +- 0x11f40464, +- 0x2ec3e729, +- 0x0134b601, +- 0xbb0553fd, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x095321f5, +-/* 0x09f3: i2c_addr_done */ +- 0xf80464b6, +-/* 0x09f5: i2c_acquire_addr */ +- 0xf8cec700, +- 0xb702e4b6, +- 0x980c10e0, +- 0x00f800ee, +-/* 0x0a04: i2c_acquire */ +- 0x09f521f5, +- 0xf00421f4, +- 0x21f403d9, +-/* 0x0a13: i2c_release */ +- 0xf500f83f, +- 0xf409f521, +- 0xdaf00421, +- 0x3f21f403, +-/* 0x0a22: i2c_recv */ +- 0x32f400f8, +- 0xf8c1c701, +- 0xb00214b6, +- 0x1ff52816, +- 0x13a0013a, +- 0x32980be8, +- 0xc013a000, +- 0x0031980b, +- 0xf90231f4, +- 0xf9e0f9d0, +- 0x0067f1d0, +- 0x0063f100, +- 0x01679210, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x0421f550, +- 0x0464b60a, +- 0xd6b0d0fc, +- 0xb31bf500, +- 0x0057f000, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xae21f550, +- 0x0464b609, +- 0x00d011f5, +- 0xbbe0c5c7, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x095321f5, +- 0xf50464b6, +- 0xf000ad11, +- 0x76bb0157, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb609ae21, +- 0x11f50464, +- 0x76bb008a, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb6090121, +- 0x11f40464, +- 0xe05bcb6a, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x4621f550, +- 0x0464b608, +- 0xbd025bb9, +- 0x430ef474, +-/* 0x0b28: i2c_recv_not_rd08 */ +- 0xf401d6b0, +- 0x57f03d1b, +- 0xae21f500, +- 0x3311f409, +- 0xf5e0c5c7, +- 0xf4095321, +- 0x57f02911, +- 0xae21f500, +- 0x1f11f409, +- 0xf5e0b5c7, +- 0xf4095321, +- 0x21f51511, +- 0x74bd0846, +- 0xf408c5c7, +- 0x32f4091b, +- 0x030ef402, +-/* 0x0b68: i2c_recv_not_wr08 */ +-/* 0x0b68: i2c_recv_done */ +- 0xf5f8cec7, +- 0xfc0a1321, +- 0xf4d0fce0, +- 0x7cb90a12, +- 0x4221f502, +-/* 0x0b7d: i2c_recv_exit */ +-/* 0x0b7f: i2c_init */ +- 0xf800f803, +-/* 0x0b81: test_recv */ +- 0xd817f100, +- 0x0614b605, +- 0xb60011cf, +- 0x07f10110, +- 0x04b605d8, +- 0x0001d006, +- 0xe7f104bd, +- 0xe3f1d900, +- 0x21f5134f, +- 0x00f80262, +-/* 0x0ba8: test_init */ +- 0x0800e7f1, +- 0x026221f5, +-/* 0x0bb2: idle_recv */ +- 0x00f800f8, +-/* 0x0bb4: idle */ +- 0xf10031f4, +- 0xb605d417, +- 0x11cf0614, +- 0x0110b600, +- 0x05d407f1, +- 0xd00604b6, +- 0x04bd0001, +-/* 0x0bd0: idle_loop */ +- 0xf45817f0, +-/* 0x0bd6: idle_proc */ +-/* 0x0bd6: idle_proc_exec */ +- 0x10f90232, +- 0xf5021eb9, +- 0xfc034b21, +- 0x0911f410, +- 0xf40231f4, +-/* 0x0bea: idle_proc_next */ +- 0x10b6ef0e, +- 0x061fb858, +- 0xf4e61bf4, +- 0x28f4dd02, +- 0xbb0ef400, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc +deleted file mode 100644 +index b8544326..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#define NVKM_PPWR_CHIPSET GF119 +-#define HW_TICKS_PER_US 324 +- +-//#define NVKM_FALCON_PC24 +-#define NVKM_FALCON_UNSHIFTED_IO +-//#define NVKM_FALCON_MMIO_UAS +-//#define NVKM_FALCON_MMIO_TRAP +- +-#include "macros.fuc" +- +-.section #nvd0_pwr_data +-#define INCLUDE_PROC +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_PROC +- +-#define INCLUDE_DATA +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_DATA +-.align 256 +- +-.section #nvd0_pwr_code +-#define INCLUDE_CODE +-#include "kernel.fuc" +-#include "arith.fuc" +-#include "host.fuc" +-#include "memx.fuc" +-#include "perf.fuc" +-#include "i2c_.fuc" +-#include "test.fuc" +-#include "idle.fuc" +-#undef INCLUDE_CODE +-.align 256 +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h +deleted file mode 100644 +index 12d86f72..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/nvd0.fuc.h ++++ /dev/null +@@ -1,1725 +0,0 @@ +-uint32_t nvd0_pwr_data[] = { +-/* 0x0000: proc_kern */ +- 0x52544e49, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0058: proc_list_head */ +- 0x54534f48, +- 0x0000049d, +- 0x00000446, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x584d454d, +- 0x00000678, +- 0x0000066a, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x46524550, +- 0x0000067c, +- 0x0000067a, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x5f433249, +- 0x00000a97, +- 0x0000093a, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x54534554, +- 0x00000aba, +- 0x00000a99, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x454c4449, +- 0x00000ac6, +- 0x00000ac4, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0268: proc_list_tail */ +-/* 0x0268: time_prev */ +- 0x00000000, +-/* 0x026c: time_next */ +- 0x00000000, +-/* 0x0270: fifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x02f0: rfifo_queue */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0370: memx_func_head */ +- 0x00000001, +- 0x00000000, +- 0x000004d3, +-/* 0x037c: memx_func_next */ +- 0x00000002, +- 0x00000000, +- 0x00000554, +- 0x00000003, +- 0x00000002, +- 0x000005d8, +- 0x00040004, +- 0x00000000, +- 0x000005f4, +- 0x00010005, +- 0x00000000, +- 0x0000060e, +- 0x00010006, +- 0x00000000, +- 0x000005d3, +-/* 0x03b8: memx_func_tail */ +-/* 0x03b8: memx_ts_start */ +- 0x00000000, +-/* 0x03bc: memx_ts_end */ +- 0x00000000, +-/* 0x03c0: memx_data_head */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-/* 0x0bc0: memx_data_tail */ +-/* 0x0bc0: i2c_scl_map */ +- 0x00000400, +- 0x00000800, +- 0x00001000, +- 0x00002000, +- 0x00004000, +- 0x00008000, +- 0x00010000, +- 0x00020000, +- 0x00040000, +- 0x00080000, +-/* 0x0be8: i2c_sda_map */ +- 0x00100000, +- 0x00200000, +- 0x00400000, +- 0x00800000, +- 0x01000000, +- 0x02000000, +- 0x04000000, +- 0x08000000, +- 0x10000000, +- 0x20000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +- +-uint32_t nvd0_pwr_code[] = { +- 0x034d0ef5, +-/* 0x0004: rd32 */ +- 0x07a007f1, +- 0xbd000ed0, +- 0x01d7f004, +- 0xf101d3f0, +- 0xd007ac07, +- 0x04bd000d, +-/* 0x001c: rd32_wait */ +- 0x07acd7f1, +- 0xf100ddcf, +- 0xf47000d4, +- 0xd7f1f51b, +- 0xddcf07a4, +-/* 0x0033: wr32 */ +- 0xf100f800, +- 0xd007a007, +- 0x04bd000e, +- 0x07a407f1, +- 0xbd000dd0, +- 0x02d7f004, +- 0xf0f0d5f0, +- 0x07f101d3, +- 0x0dd007ac, +-/* 0x0057: wr32_wait */ +- 0xf104bd00, +- 0xcf07acd7, +- 0xd4f100dd, +- 0x1bf47000, +-/* 0x0067: nsec */ +- 0xf900f8f5, +- 0xf080f990, +- 0x88cf2c87, +-/* 0x0071: nsec_loop */ +- 0x2c97f000, +- 0xbb0099cf, +- 0x9eb80298, +- 0xf41ef406, +- 0x90fc80fc, +-/* 0x0086: wait */ +- 0x90f900f8, +- 0x87f080f9, +- 0x0088cf2c, +-/* 0x0090: wait_loop */ +- 0xf402eeb9, +- 0xdab90421, +- 0x04adfd02, +- 0xf406acb8, +- 0x97f0120b, +- 0x0099cf2c, +- 0xb80298bb, +- 0x1ef4069b, +-/* 0x00b1: wait_done */ +- 0xfc80fce2, +-/* 0x00b7: intr_watchdog */ +- 0x9800f890, +- 0x96b003e9, +- 0x2a0bf400, +- 0xbb9a0a98, +- 0x1cf4029a, +- 0x01d7f00f, +- 0x028c21f5, +- 0x0ef494bd, +-/* 0x00d5: intr_watchdog_next_time */ +- 0x9b0a9815, +- 0xf400a6b0, +- 0x9ab8090b, +- 0x061cf406, +-/* 0x00e4: intr_watchdog_next_time_set */ +-/* 0x00e7: intr_watchdog_next_proc */ +- 0x809b0980, +- 0xe0b603e9, +- 0x68e6b158, +- 0xc61bf402, +-/* 0x00f6: intr */ +- 0x00f900f8, +- 0x80f904bd, +- 0xa0f990f9, +- 0xc0f9b0f9, +- 0xe0f9d0f9, +- 0xf7f0f0f9, +- 0x0188fe00, +- 0x87f180f9, +- 0x88cf05d0, +- 0x0180b600, +- 0x05d007f1, +- 0xbd0008d0, +- 0x0887f004, +- 0xc40088cf, +- 0x0bf40289, +- 0x9b008020, +- 0xf458e7f0, +- 0x0998b721, +- 0x0096b09b, +- 0xf00e0bf4, +- 0x09d03407, +- 0x8004bd00, +-/* 0x014e: intr_skip_watchdog */ +- 0x89e49a09, +- 0x0bf40800, +- 0x8897f13c, +- 0x0099cf06, +- 0xf4029ac4, +- 0xc7f1260b, +- 0xcccf04c0, +- 0xf1c0f900, +- 0xf14f48e7, +- 0xf05453e3, +- 0x21f500d7, +- 0xc0fc02f1, +- 0x04c007f1, +- 0xbd000cd0, +-/* 0x0185: intr_subintr_skip_fifo */ +- 0x8807f104, +- 0x0009d006, +-/* 0x018e: intr_skip_subintr */ +- 0x89c404bd, +- 0x070bf420, +- 0xffbfa4f1, +-/* 0x0198: intr_skip_pause */ +- 0xf44089c4, +- 0xa4f1070b, +-/* 0x01a2: intr_skip_user0 */ +- 0x07f0ffbf, +- 0x0008d004, +- 0x80fc04bd, +- 0xfc0088fe, +- 0xfce0fcf0, +- 0xfcc0fcd0, +- 0xfca0fcb0, +- 0xfc80fc90, +- 0x0032f400, +-/* 0x01c6: ticks_from_ns */ +- 0xc0f901f8, +- 0xd7f1b0f9, +- 0xd3f00144, +- 0xb321f500, +- 0xe8ccec03, +- 0x00b4b003, +- 0xec120bf4, +- 0xf103e8ee, +- 0xf00144d7, +- 0x21f500d3, +-/* 0x01ee: ticks_from_ns_quit */ +- 0xceb903b3, +- 0xfcb0fc02, +-/* 0x01f7: ticks_from_us */ +- 0xf900f8c0, +- 0xf1b0f9c0, +- 0xf00144d7, +- 0x21f500d3, +- 0xceb903b3, +- 0x00b4b002, +- 0xbd050bf4, +-/* 0x0211: ticks_from_us_quit */ +- 0xfcb0fce4, +-/* 0x0217: ticks_to_us */ +- 0xf100f8c0, +- 0xf00144d7, +- 0xedff00d3, +-/* 0x0223: timer */ +- 0xf900f8ec, +- 0xf480f990, +- 0xf8981032, +- 0x0086b003, +- 0xbd531cf4, +- 0x3807f084, +- 0xbd0008d0, +- 0x3487f004, +- 0x980088cf, +- 0x98bb9a09, +- 0x00e9bb02, +- 0xf003fe80, +- 0x88cf0887, +- 0x0284f000, +- 0xf0201bf4, +- 0x88cf3487, +- 0x06e0b800, +- 0xb8090bf4, +- 0x1cf406e8, +-/* 0x026d: timer_reset */ +- 0x3407f00e, +- 0xbd000ed0, +- 0x9a0e8004, +-/* 0x0278: timer_enable */ +- 0xf00187f0, +- 0x08d03807, +-/* 0x0283: timer_done */ +- 0xf404bd00, +- 0x80fc1031, +- 0x00f890fc, +-/* 0x028c: send_proc */ +- 0x90f980f9, +- 0x9805e898, +- 0x86f004e9, +- 0x0689b804, +- 0xc42a0bf4, +- 0x88940398, +- 0x1880b604, +- 0x98008ebb, +- 0x8a8000fa, +- 0x018d8000, +- 0x80028c80, +- 0x90b6038b, +- 0x0794f001, +- 0xf404e980, +-/* 0x02c6: send_done */ +- 0x90fc0231, +- 0x00f880fc, +-/* 0x02cc: find */ +- 0x87f080f9, +- 0x0131f458, +-/* 0x02d4: find_loop */ +- 0xb8008a98, +- 0x0bf406ae, +- 0x5880b610, +- 0x026886b1, +- 0xf4f01bf4, +-/* 0x02ea: find_done */ +- 0x8eb90132, +- 0xf880fc02, +-/* 0x02f1: send */ +- 0xcc21f500, +- 0x9701f402, +-/* 0x02fa: recv */ +- 0x90f900f8, +- 0xe89880f9, +- 0x04e99805, +- 0xb80132f4, +- 0x0bf40689, +- 0x0389c43d, +- 0xf00180b6, +- 0xe8800784, +- 0x02ea9805, +- 0x8ffef0f9, +- 0xb9f0f901, +- 0x999402ef, +- 0x00e9bb04, +- 0x9818e0b6, +- 0xec9803eb, +- 0x01ed9802, +- 0xf900ee98, +- 0xfef0fca5, +- 0x31f400f8, +-/* 0x0347: recv_done */ +- 0xfcf0fc01, +- 0xf890fc80, +-/* 0x034d: init */ +- 0x0817f100, +- 0x0011cf01, +- 0x010911e7, +- 0xfe0814b6, +- 0x17f10014, +- 0x13f000e0, +- 0x1c07f000, +- 0xbd0001d0, +- 0xff17f004, +- 0xd01407f0, +- 0x04bd0001, +- 0xf10217f0, +- 0xf0080015, +- 0x01d01007, +- 0xf104bd00, +- 0xf000f617, +- 0x10fe0013, +- 0x1031f400, +- 0xf00117f0, +- 0x01d03807, +- 0xf004bd00, +-/* 0x03a2: init_proc */ +- 0xf19858f7, +- 0x0016b001, +- 0xf9fa0bf4, +- 0x58f0b615, +-/* 0x03b3: mulu32_32_64 */ +- 0xf9f20ef4, +- 0xf920f910, +- 0x9540f930, +- 0xd29510e1, +- 0xbdc4bd10, +- 0xc0edffb4, +- 0xb9301dff, +- 0x34f10234, +- 0x34b6ffff, +- 0x1045b610, +- 0xbb00c3bb, +- 0xe2ff01b4, +- 0x0234b930, +- 0xffff34f1, +- 0xb61034b6, +- 0xc3bb1045, +- 0x01b4bb00, +- 0xbb3012ff, +- 0x40fc00b3, +- 0x20fc30fc, +- 0x00f810fc, +-/* 0x0404: host_send */ +- 0x04b017f1, +- 0xf10011cf, +- 0xcf04a027, +- 0x12b80022, +- 0x2f0bf406, +- 0x94071ec4, +- 0xe0b704ee, +- 0xeb980270, +- 0x02ec9803, +- 0x9801ed98, +- 0x21f500ee, +- 0x10b602f1, +- 0x0f1ec401, +- 0x04b007f1, +- 0xbd000ed0, +- 0xc30ef404, +-/* 0x0444: host_send_done */ +-/* 0x0446: host_recv */ +- 0x17f100f8, +- 0x13f14e49, +- 0xe1b85254, +- 0xb30bf406, +-/* 0x0454: host_recv_wait */ +- 0x04cc17f1, +- 0xf10011cf, +- 0xcf04c827, +- 0x16f00022, +- 0x0612b808, +- 0xc4ec0bf4, +- 0x34b60723, +- 0xf030b704, +- 0x033b8002, +- 0x80023c80, +- 0x3e80013d, +- 0x0120b600, +- 0xf10f24f0, +- 0xd004c807, +- 0x04bd0002, +- 0xf04027f0, +- 0x02d00007, +- 0xf804bd00, +-/* 0x049d: host_init */ +- 0x8017f100, +- 0x1014b600, +- 0x027015f1, +- 0x04d007f1, +- 0xbd0001d0, +- 0x8017f104, +- 0x1014b600, +- 0x02f015f1, +- 0x04dc07f1, +- 0xbd0001d0, +- 0x0117f004, +- 0x04c407f1, +- 0xbd0001d0, +-/* 0x04d3: memx_func_enter */ +- 0xf100f804, +- 0xf1162067, +- 0xf1f55d77, +- 0xb9ffff73, +- 0x21f4026e, +- 0x02d8b904, +- 0xf90487fd, +- 0xfc80f960, +- 0xf4e0fcd0, +- 0x77f13321, +- 0x73f1fffe, +- 0x6eb9ffff, +- 0x0421f402, +- 0xfd02d8b9, +- 0x60f90487, +- 0xd0fc80f9, +- 0x21f4e0fc, +- 0xf067f133, +- 0x026eb926, +- 0xb90421f4, +- 0x87fd02d8, +- 0xf960f904, +- 0xfcd0fc80, +- 0x3321f4e0, +- 0xf10467f0, +- 0xd007e007, +- 0x04bd0006, +-/* 0x053c: memx_func_enter_wait */ +- 0x07c067f1, +- 0xf00066cf, +- 0x0bf40464, +- 0x2c67f0f6, +- 0x800066cf, +- 0x00f8ee06, +-/* 0x0554: memx_func_leave */ +- 0xcf2c67f0, +- 0x06800066, +- 0x0467f0ef, +- 0x07e407f1, +- 0xbd0006d0, +-/* 0x0569: memx_func_leave_wait */ +- 0xc067f104, +- 0x0066cf07, +- 0xf40464f0, +- 0x67f1f61b, +- 0x77f126f0, +- 0x73f00001, +- 0x026eb900, +- 0xb90421f4, +- 0x87fd02d8, +- 0xf960f905, +- 0xfcd0fc80, +- 0x3321f4e0, +- 0x162067f1, +- 0xf4026eb9, +- 0xd8b90421, +- 0x0587fd02, +- 0x80f960f9, +- 0xe0fcd0fc, +- 0xf13321f4, +- 0xf00aa277, +- 0x6eb90073, +- 0x0421f402, +- 0xfd02d8b9, +- 0x60f90587, +- 0xd0fc80f9, +- 0x21f4e0fc, +-/* 0x05d3: memx_func_wait_vblank */ +- 0xb600f833, +- 0x00f80410, +-/* 0x05d8: memx_func_wr32 */ +- 0x98001698, +- 0x10b60115, +- 0xf960f908, +- 0xfcd0fc50, +- 0x3321f4e0, +- 0xf40242b6, +- 0x00f8e91b, +-/* 0x05f4: memx_func_wait */ +- 0xcf2c87f0, +- 0x1e980088, +- 0x011d9800, +- 0x98021c98, +- 0x10b6031b, +- 0x8621f410, +-/* 0x060e: memx_func_delay */ +- 0x1e9800f8, +- 0x0410b600, +- 0xf86721f4, +-/* 0x0619: memx_exec */ +- 0xf9e0f900, +- 0x02c1b9d0, +-/* 0x0623: memx_exec_next */ +- 0x9802b2b9, +- 0x10b60013, +- 0xf034e704, +- 0xe033e701, +- 0x0132b601, +- 0x980c30f0, +- 0x55f9de35, +- 0xf40612b8, +- 0x0b98e41e, +- 0xef0c98ee, +- 0xf102cbbb, +- 0xcf07c4b7, +- 0xd0fc00bb, +- 0x21f5e0fc, +- 0x00f802f1, +-/* 0x065c: memx_info */ +- 0x03c0c7f1, +- 0x0800b7f1, +- 0x02f121f5, +-/* 0x066a: memx_recv */ +- 0xd6b000f8, +- 0xac0bf401, +- 0xf400d6b0, +- 0x00f8e90b, +-/* 0x0678: memx_init */ +-/* 0x067a: perf_recv */ +- 0x00f800f8, +-/* 0x067c: perf_init */ +-/* 0x067e: i2c_drive_scl */ +- 0x36b000f8, +- 0x0e0bf400, +- 0x07e007f1, +- 0xbd0001d0, +-/* 0x068f: i2c_drive_scl_lo */ +- 0xf100f804, +- 0xd007e407, +- 0x04bd0001, +-/* 0x069a: i2c_drive_sda */ +- 0x36b000f8, +- 0x0e0bf400, +- 0x07e007f1, +- 0xbd0002d0, +-/* 0x06ab: i2c_drive_sda_lo */ +- 0xf100f804, +- 0xd007e407, +- 0x04bd0002, +-/* 0x06b6: i2c_sense_scl */ +- 0x32f400f8, +- 0xc437f101, +- 0x0033cf07, +- 0xf40431fd, +- 0x31f4060b, +-/* 0x06c9: i2c_sense_scl_done */ +-/* 0x06cb: i2c_sense_sda */ +- 0xf400f801, +- 0x37f10132, +- 0x33cf07c4, +- 0x0432fd00, +- 0xf4060bf4, +-/* 0x06de: i2c_sense_sda_done */ +- 0x00f80131, +-/* 0x06e0: i2c_raise_scl */ +- 0x47f140f9, +- 0x37f00898, +- 0x7e21f501, +-/* 0x06ed: i2c_raise_scl_wait */ +- 0xe8e7f106, +- 0x6721f403, +- 0x06b621f5, +- 0xb60901f4, +- 0x1bf40142, +-/* 0x0701: i2c_raise_scl_done */ +- 0xf840fcef, +-/* 0x0705: i2c_start */ +- 0xb621f500, +- 0x0d11f406, +- 0x06cb21f5, +- 0xf40611f4, +-/* 0x0716: i2c_start_rep */ +- 0x37f0300e, +- 0x7e21f500, +- 0x0137f006, +- 0x069a21f5, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xe021f550, +- 0x0464b606, +-/* 0x0743: i2c_start_send */ +- 0xf01f11f4, +- 0x21f50037, +- 0xe7f1069a, +- 0x21f41388, +- 0x0037f067, +- 0x067e21f5, +- 0x1388e7f1, +-/* 0x075f: i2c_start_out */ +- 0xf86721f4, +-/* 0x0761: i2c_stop */ +- 0x0037f000, +- 0x067e21f5, +- 0xf50037f0, +- 0xf1069a21, +- 0xf403e8e7, +- 0x37f06721, +- 0x7e21f501, +- 0x88e7f106, +- 0x6721f413, +- 0xf50137f0, +- 0xf1069a21, +- 0xf41388e7, +- 0x00f86721, +-/* 0x0794: i2c_bitw */ +- 0x069a21f5, +- 0x03e8e7f1, +- 0xbb6721f4, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x06e021f5, +- 0xf40464b6, +- 0xe7f11811, +- 0x21f41388, +- 0x0037f067, +- 0x067e21f5, +- 0x1388e7f1, +-/* 0x07d3: i2c_bitw_out */ +- 0xf86721f4, +-/* 0x07d5: i2c_bitr */ +- 0x0137f000, +- 0x069a21f5, +- 0x03e8e7f1, +- 0xbb6721f4, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x06e021f5, +- 0xf40464b6, +- 0x21f51b11, +- 0x37f006cb, +- 0x7e21f500, +- 0x88e7f106, +- 0x6721f413, +- 0xf4013cf0, +-/* 0x081a: i2c_bitr_done */ +- 0x00f80131, +-/* 0x081c: i2c_get_byte */ +- 0xf00057f0, +-/* 0x0822: i2c_get_byte_next */ +- 0x54b60847, +- 0x0076bb01, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b607d5, +- 0x2b11f404, +- 0xb60553fd, +- 0x1bf40142, +- 0x0137f0d8, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x9421f550, +- 0x0464b607, +-/* 0x086c: i2c_get_byte_done */ +-/* 0x086e: i2c_put_byte */ +- 0x47f000f8, +-/* 0x0871: i2c_put_byte_next */ +- 0x0142b608, +- 0xbb3854ff, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x079421f5, +- 0xf40464b6, +- 0x46b03411, +- 0xd81bf400, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xd521f550, +- 0x0464b607, +- 0xbb0f11f4, +- 0x36b00076, +- 0x061bf401, +-/* 0x08c7: i2c_put_byte_done */ +- 0xf80132f4, +-/* 0x08c9: i2c_addr */ +- 0x0076bb00, +- 0xf90465b6, +- 0x04659450, +- 0xbd0256bb, +- 0x0475fd50, +- 0x21f550fc, +- 0x64b60705, +- 0x2911f404, +- 0x012ec3e7, +- 0xfd0134b6, +- 0x76bb0553, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb6086e21, +-/* 0x090e: i2c_addr_done */ +- 0x00f80464, +-/* 0x0910: i2c_acquire_addr */ +- 0xb6f8cec7, +- 0xe0b705e4, +- 0x00f8d014, +-/* 0x091c: i2c_acquire */ +- 0x091021f5, +- 0xf00421f4, +- 0x21f403d9, +-/* 0x092b: i2c_release */ +- 0xf500f833, +- 0xf4091021, +- 0xdaf00421, +- 0x3321f403, +-/* 0x093a: i2c_recv */ +- 0x32f400f8, +- 0xf8c1c701, +- 0xb00214b6, +- 0x1ff52816, +- 0x13a0013a, +- 0x32980be8, +- 0xc013a000, +- 0x0031980b, +- 0xf90231f4, +- 0xf9e0f9d0, +- 0x0067f1d0, +- 0x0063f100, +- 0x01679210, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x1c21f550, +- 0x0464b609, +- 0xd6b0d0fc, +- 0xb31bf500, +- 0x0057f000, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0xc921f550, +- 0x0464b608, +- 0x00d011f5, +- 0xbbe0c5c7, +- 0x65b60076, +- 0x9450f904, +- 0x56bb0465, +- 0xfd50bd02, +- 0x50fc0475, +- 0x086e21f5, +- 0xf50464b6, +- 0xf000ad11, +- 0x76bb0157, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb608c921, +- 0x11f50464, +- 0x76bb008a, +- 0x0465b600, +- 0x659450f9, +- 0x0256bb04, +- 0x75fd50bd, +- 0xf550fc04, +- 0xb6081c21, +- 0x11f40464, +- 0xe05bcb6a, +- 0xb60076bb, +- 0x50f90465, +- 0xbb046594, +- 0x50bd0256, +- 0xfc0475fd, +- 0x6121f550, +- 0x0464b607, +- 0xbd025bb9, +- 0x430ef474, +-/* 0x0a40: i2c_recv_not_rd08 */ +- 0xf401d6b0, +- 0x57f03d1b, +- 0xc921f500, +- 0x3311f408, +- 0xf5e0c5c7, +- 0xf4086e21, +- 0x57f02911, +- 0xc921f500, +- 0x1f11f408, +- 0xf5e0b5c7, +- 0xf4086e21, +- 0x21f51511, +- 0x74bd0761, +- 0xf408c5c7, +- 0x32f4091b, +- 0x030ef402, +-/* 0x0a80: i2c_recv_not_wr08 */ +-/* 0x0a80: i2c_recv_done */ +- 0xf5f8cec7, +- 0xfc092b21, +- 0xf4d0fce0, +- 0x7cb90a12, +- 0xf121f502, +-/* 0x0a95: i2c_recv_exit */ +-/* 0x0a97: i2c_init */ +- 0xf800f802, +-/* 0x0a99: test_recv */ +- 0xd817f100, +- 0x0011cf05, +- 0xf10110b6, +- 0xd005d807, +- 0x04bd0001, +- 0xd900e7f1, +- 0x134fe3f1, +- 0x022321f5, +-/* 0x0aba: test_init */ +- 0xe7f100f8, +- 0x21f50800, +- 0x00f80223, +-/* 0x0ac4: idle_recv */ +-/* 0x0ac6: idle */ +- 0x31f400f8, +- 0xd417f100, +- 0x0011cf05, +- 0xf10110b6, +- 0xd005d407, +- 0x04bd0001, +-/* 0x0adc: idle_loop */ +- 0xf45817f0, +-/* 0x0ae2: idle_proc */ +-/* 0x0ae2: idle_proc_exec */ +- 0x10f90232, +- 0xf5021eb9, +- 0xfc02fa21, +- 0x0911f410, +- 0xf40231f4, +-/* 0x0af6: idle_proc_next */ +- 0x10b6ef0e, +- 0x061fb858, +- 0xf4e61bf4, +- 0x28f4dd02, +- 0xc10ef400, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h +deleted file mode 100644 +index 522e3079..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/os.h ++++ /dev/null +@@ -1,47 +0,0 @@ +-#ifndef __NVKM_PWR_OS_H__ +-#define __NVKM_PWR_OS_H__ +- +-/* Process names */ +-#define PROC_KERN 0x52544e49 +-#define PROC_IDLE 0x454c4449 +-#define PROC_HOST 0x54534f48 +-#define PROC_MEMX 0x584d454d +-#define PROC_PERF 0x46524550 +-#define PROC_I2C_ 0x5f433249 +-#define PROC_TEST 0x54534554 +- +-/* KERN: message identifiers */ +-#define KMSG_FIFO 0x00000000 +-#define KMSG_ALARM 0x00000001 +- +-/* MEMX: message identifiers */ +-#define MEMX_MSG_INFO 0 +-#define MEMX_MSG_EXEC 1 +- +-/* MEMX: script opcode definitions */ +-#define MEMX_ENTER 1 +-#define MEMX_LEAVE 2 +-#define MEMX_WR32 3 +-#define MEMX_WAIT 4 +-#define MEMX_DELAY 5 +-#define MEMX_VBLANK 6 +- +-/* I2C_: message identifiers */ +-#define I2C__MSG_RD08 0 +-#define I2C__MSG_WR08 1 +- +-#define I2C__MSG_DATA0_PORT 24:31 +-#define I2C__MSG_DATA0_ADDR 14:23 +- +-#define I2C__MSG_DATA0_RD08_PORT I2C__MSG_DATA0_PORT +-#define I2C__MSG_DATA0_RD08_ADDR I2C__MSG_DATA0_ADDR +-#define I2C__MSG_DATA0_RD08_REG 0:7 +-#define I2C__MSG_DATA1_RD08_VAL 0:7 +- +-#define I2C__MSG_DATA0_WR08_PORT I2C__MSG_DATA0_PORT +-#define I2C__MSG_DATA0_WR08_ADDR I2C__MSG_DATA0_ADDR +-#define I2C__MSG_DATA0_WR08_SYNC 8:8 +-#define I2C__MSG_DATA0_WR08_REG 0:7 +-#define I2C__MSG_DATA1_WR08_VAL 0:7 +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc +deleted file mode 100644 +index 38eadf70..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/perf.fuc ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_PROC +-process(PROC_PERF, #perf_init, #perf_recv) +-#endif +- +-/****************************************************************************** +- * PERF data segment +- *****************************************************************************/ +-#ifdef INCLUDE_DATA +-#endif +- +-/****************************************************************************** +- * PERF code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +- +-// description +-// +-// $r15 - current (perf) +-// $r14 - sender process name +-// $r13 - message +-// $r12 - data0 +-// $r11 - data1 +-// $r0 - zero +-perf_recv: +- ret +- +-// description +-// +-// $r15 - current (perf) +-// $r0 - zero +-perf_init: +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc b/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc +deleted file mode 100644 +index 0c3a71bf..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/test.fuc ++++ /dev/null +@@ -1,64 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef INCLUDE_PROC +-process(PROC_TEST, #test_init, #test_recv) +-#endif +- +-/****************************************************************************** +- * TEST data segment +- *****************************************************************************/ +-#ifdef INCLUDE_DATA +-#endif +- +-/****************************************************************************** +- * TEST code segment +- *****************************************************************************/ +-#ifdef INCLUDE_CODE +-// description +-// +-// $r15 - current (test) +-// $r14 - sender process name +-// $r13 - message +-// $r12 - data0 +-// $r11 - data1 +-// $r0 - zero +-test_recv: +- nv_iord($r1, NV_PPWR_DSCRATCH(2)) +- add b32 $r1 1 +- nv_iowr(NV_PPWR_DSCRATCH(2), $r1) +- mov $r14 -0x2700 /* 0xd900, envyas grrr! */ +- sethi $r14 0x134f0000 +- call(timer) +- ret +- +-// description +-// +-// $r15 - current (test) +-// $r0 - zero +-test_init: +- mov $r14 0x800 +- call(timer) +- ret +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c +deleted file mode 100644 +index d7661299..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/gk104.c ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-#define nvd0_pwr_code gk104_pwr_code +-#define nvd0_pwr_data gk104_pwr_data +-#include "fuc/nvd0.fuc.h" +- +-static void +-gk104_pwr_pgob(struct nouveau_pwr *ppwr, bool enable) +-{ +- nv_mask(ppwr, 0x000200, 0x00001000, 0x00000000); +- nv_rd32(ppwr, 0x000200); +- nv_mask(ppwr, 0x000200, 0x08000000, 0x08000000); +- msleep(50); +- +- nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000002); +- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); +- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); +- +- nv_mask(ppwr, 0x020004, 0xc0000000, enable ? 0xc0000000 : 0x40000000); +- msleep(50); +- +- nv_mask(ppwr, 0x10a78c, 0x00000002, 0x00000000); +- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000001); +- nv_mask(ppwr, 0x10a78c, 0x00000001, 0x00000000); +- +- nv_mask(ppwr, 0x000200, 0x08000000, 0x00000000); +- nv_mask(ppwr, 0x000200, 0x00001000, 0x00001000); +- nv_rd32(ppwr, 0x000200); +-} +- +-struct nouveau_oclass * +-gk104_pwr_oclass = &(struct nvkm_pwr_impl) { +- .base.handle = NV_SUBDEV(PWR, 0xe4), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_pwr_ctor, +- .dtor = _nouveau_pwr_dtor, +- .init = _nouveau_pwr_init, +- .fini = _nouveau_pwr_fini, +- }, +- .code.data = gk104_pwr_code, +- .code.size = sizeof(gk104_pwr_code), +- .data.data = gk104_pwr_data, +- .data.size = sizeof(gk104_pwr_data), +- .pgob = gk104_pwr_pgob, +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c +deleted file mode 100644 +index 65eaa254..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/memx.c ++++ /dev/null +@@ -1,168 +0,0 @@ +-#ifndef __NVKM_PWR_MEMX_H__ +-#define __NVKM_PWR_MEMX_H__ +- +-#include "priv.h" +- +-struct nouveau_memx { +- struct nouveau_pwr *ppwr; +- u32 base; +- u32 size; +- struct { +- u32 mthd; +- u32 size; +- u32 data[64]; +- } c; +-}; +- +-static void +-memx_out(struct nouveau_memx *memx) +-{ +- struct nouveau_pwr *ppwr = memx->ppwr; +- int i; +- +- if (memx->c.mthd) { +- nv_wr32(ppwr, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); +- for (i = 0; i < memx->c.size; i++) +- nv_wr32(ppwr, 0x10a1c4, memx->c.data[i]); +- memx->c.mthd = 0; +- memx->c.size = 0; +- } +-} +- +-static void +-memx_cmd(struct nouveau_memx *memx, u32 mthd, u32 size, u32 data[]) +-{ +- if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) || +- (memx->c.mthd && memx->c.mthd != mthd)) +- memx_out(memx); +- memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0])); +- memx->c.size += size; +- memx->c.mthd = mthd; +-} +- +-int +-nouveau_memx_init(struct nouveau_pwr *ppwr, struct nouveau_memx **pmemx) +-{ +- struct nouveau_memx *memx; +- u32 reply[2]; +- int ret; +- +- ret = ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_INFO, 0, 0); +- if (ret) +- return ret; +- +- memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL); +- if (!memx) +- return -ENOMEM; +- memx->ppwr = ppwr; +- memx->base = reply[0]; +- memx->size = reply[1]; +- +- /* acquire data segment access */ +- do { +- nv_wr32(ppwr, 0x10a580, 0x00000003); +- } while (nv_rd32(ppwr, 0x10a580) != 0x00000003); +- nv_wr32(ppwr, 0x10a1c0, 0x01000000 | memx->base); +- +- return 0; +-} +- +-int +-nouveau_memx_fini(struct nouveau_memx **pmemx, bool exec) +-{ +- struct nouveau_memx *memx = *pmemx; +- struct nouveau_pwr *ppwr = memx->ppwr; +- u32 finish, reply[2]; +- +- /* flush the cache... */ +- memx_out(memx); +- +- /* release data segment access */ +- finish = nv_rd32(ppwr, 0x10a1c0) & 0x00ffffff; +- nv_wr32(ppwr, 0x10a580, 0x00000000); +- +- /* call MEMX process to execute the script, and wait for reply */ +- if (exec) { +- ppwr->message(ppwr, reply, PROC_MEMX, MEMX_MSG_EXEC, +- memx->base, finish); +- } +- +- nv_debug(memx->ppwr, "Exec took %uns, PPWR_IN %08x\n", +- reply[0], reply[1]); +- kfree(memx); +- return 0; +-} +- +-void +-nouveau_memx_wr32(struct nouveau_memx *memx, u32 addr, u32 data) +-{ +- nv_debug(memx->ppwr, "R[%06x] = 0x%08x\n", addr, data); +- memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data }); +-} +- +-void +-nouveau_memx_wait(struct nouveau_memx *memx, +- u32 addr, u32 mask, u32 data, u32 nsec) +-{ +- nv_debug(memx->ppwr, "R[%06x] & 0x%08x == 0x%08x, %d us\n", +- addr, mask, data, nsec); +- memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, ~mask, data, nsec }); +- memx_out(memx); /* fuc can't handle multiple */ +-} +- +-void +-nouveau_memx_nsec(struct nouveau_memx *memx, u32 nsec) +-{ +- nv_debug(memx->ppwr, " DELAY = %d ns\n", nsec); +- memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec }); +- memx_out(memx); /* fuc can't handle multiple */ +-} +- +-void +-nouveau_memx_wait_vblank(struct nouveau_memx *memx) +-{ +- struct nouveau_pwr *ppwr = memx->ppwr; +- u32 heads, x, y, px = 0; +- int i, head_sync; +- +- if (nv_device(ppwr)->chipset < 0xd0) { +- heads = nv_rd32(ppwr, 0x610050); +- for (i = 0; i < 2; i++) { +- /* Heuristic: sync to head with biggest resolution */ +- if (heads & (2 << (i << 3))) { +- x = nv_rd32(ppwr, 0x610b40 + (0x540 * i)); +- y = (x & 0xffff0000) >> 16; +- x &= 0x0000ffff; +- if ((x * y) > px) { +- px = (x * y); +- head_sync = i; +- } +- } +- } +- } +- +- if (px == 0) { +- nv_debug(memx->ppwr, "WAIT VBLANK !NO ACTIVE HEAD\n"); +- return; +- } +- +- nv_debug(memx->ppwr, "WAIT VBLANK HEAD%d\n", head_sync); +- memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync }); +- memx_out(memx); /* fuc can't handle multiple */ +-} +- +-void +-nouveau_memx_block(struct nouveau_memx *memx) +-{ +- nv_debug(memx->ppwr, " HOST BLOCKED\n"); +- memx_cmd(memx, MEMX_ENTER, 0, NULL); +-} +- +-void +-nouveau_memx_unblock(struct nouveau_memx *memx) +-{ +- nv_debug(memx->ppwr, " HOST UNBLOCKED\n"); +- memx_cmd(memx, MEMX_LEAVE, 0, NULL); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c +deleted file mode 100644 +index 04ff7c3c..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nv108.c ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +-#include "fuc/nv108.fuc.h" +- +-struct nouveau_oclass * +-nv108_pwr_oclass = &(struct nvkm_pwr_impl) { +- .base.handle = NV_SUBDEV(PWR, 0x00), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_pwr_ctor, +- .dtor = _nouveau_pwr_dtor, +- .init = _nouveau_pwr_init, +- .fini = _nouveau_pwr_fini, +- }, +- .code.data = nv108_pwr_code, +- .code.size = sizeof(nv108_pwr_code), +- .data.data = nv108_pwr_data, +- .data.size = sizeof(nv108_pwr_data), +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c +deleted file mode 100644 +index 998d5307..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nva3.c ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +-#include "fuc/nva3.fuc.h" +- +-static int +-nva3_pwr_init(struct nouveau_object *object) +-{ +- struct nouveau_pwr *ppwr = (void *)object; +- nv_mask(ppwr, 0x022210, 0x00000001, 0x00000000); +- nv_mask(ppwr, 0x022210, 0x00000001, 0x00000001); +- return nouveau_pwr_init(ppwr); +-} +- +-struct nouveau_oclass * +-nva3_pwr_oclass = &(struct nvkm_pwr_impl) { +- .base.handle = NV_SUBDEV(PWR, 0xa3), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_pwr_ctor, +- .dtor = _nouveau_pwr_dtor, +- .init = nva3_pwr_init, +- .fini = _nouveau_pwr_fini, +- }, +- .code.data = nva3_pwr_code, +- .code.size = sizeof(nva3_pwr_code), +- .data.data = nva3_pwr_data, +- .data.size = sizeof(nva3_pwr_data), +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c +deleted file mode 100644 +index 9a773e66..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvc0.c ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +-#include "fuc/nvc0.fuc.h" +- +-struct nouveau_oclass * +-nvc0_pwr_oclass = &(struct nvkm_pwr_impl) { +- .base.handle = NV_SUBDEV(PWR, 0xc0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_pwr_ctor, +- .dtor = _nouveau_pwr_dtor, +- .init = _nouveau_pwr_init, +- .fini = _nouveau_pwr_fini, +- }, +- .code.data = nvc0_pwr_code, +- .code.size = sizeof(nvc0_pwr_code), +- .data.data = nvc0_pwr_data, +- .data.size = sizeof(nvc0_pwr_data), +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c +deleted file mode 100644 +index 2b29be5d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/nvd0.c ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +-#include "fuc/nvd0.fuc.h" +- +-struct nouveau_oclass * +-nvd0_pwr_oclass = &(struct nvkm_pwr_impl) { +- .base.handle = NV_SUBDEV(PWR, 0xd0), +- .base.ofuncs = &(struct nouveau_ofuncs) { +- .ctor = _nouveau_pwr_ctor, +- .dtor = _nouveau_pwr_dtor, +- .init = _nouveau_pwr_init, +- .fini = _nouveau_pwr_fini, +- }, +- .code.data = nvd0_pwr_code, +- .code.size = sizeof(nvd0_pwr_code), +- .data.data = nvd0_pwr_data, +- .data.size = sizeof(nvd0_pwr_data), +-}.base; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h b/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h +deleted file mode 100644 +index 3814a341..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/pwr/priv.h ++++ /dev/null +@@ -1,44 +0,0 @@ +-#ifndef __NVKM_PWR_PRIV_H__ +-#define __NVKM_PWR_PRIV_H__ +- +-#include +-#include +- +-#define nouveau_pwr_create(p, e, o, d) \ +- nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d) +-#define nouveau_pwr_destroy(p) \ +- nouveau_subdev_destroy(&(p)->base) +-#define nouveau_pwr_init(p) ({ \ +- struct nouveau_pwr *_ppwr = (p); \ +- _nouveau_pwr_init(nv_object(_ppwr)); \ +-}) +-#define nouveau_pwr_fini(p,s) ({ \ +- struct nouveau_pwr *_ppwr = (p); \ +- _nouveau_pwr_fini(nv_object(_ppwr), (s)); \ +-}) +- +-int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, int, void **); +- +-int _nouveau_pwr_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-#define _nouveau_pwr_dtor _nouveau_subdev_dtor +-int _nouveau_pwr_init(struct nouveau_object *); +-int _nouveau_pwr_fini(struct nouveau_object *, bool); +- +-struct nvkm_pwr_impl { +- struct nouveau_oclass base; +- struct { +- u32 *data; +- u32 size; +- } code; +- struct { +- u32 *data; +- u32 size; +- } data; +- +- void (*pgob)(struct nouveau_pwr *, bool); +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c b/drivers/gpu/drm/nouveau/core/subdev/therm/base.c +deleted file mode 100644 +index 9ad01da6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/base.c ++++ /dev/null +@@ -1,374 +0,0 @@ +-/* +- * Copyright 2012 The Nouveau community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +-#include +- +-#include +- +-#include "priv.h" +- +-static int +-nouveau_therm_update_trip(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_therm_trip_point *trip = priv->fan->bios.trip, +- *cur_trip = NULL, +- *last_trip = priv->last_trip; +- u8 temp = therm->temp_get(therm); +- u16 duty, i; +- +- /* look for the trip point corresponding to the current temperature */ +- cur_trip = NULL; +- for (i = 0; i < priv->fan->bios.nr_fan_trip; i++) { +- if (temp >= trip[i].temp) +- cur_trip = &trip[i]; +- } +- +- /* account for the hysteresis cycle */ +- if (last_trip && temp <= (last_trip->temp) && +- temp > (last_trip->temp - last_trip->hysteresis)) +- cur_trip = last_trip; +- +- if (cur_trip) { +- duty = cur_trip->fan_duty; +- priv->last_trip = cur_trip; +- } else { +- duty = 0; +- priv->last_trip = NULL; +- } +- +- return duty; +-} +- +-static int +-nouveau_therm_update_linear(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- u8 linear_min_temp = priv->fan->bios.linear_min_temp; +- u8 linear_max_temp = priv->fan->bios.linear_max_temp; +- u8 temp = therm->temp_get(therm); +- u16 duty; +- +- /* handle the non-linear part first */ +- if (temp < linear_min_temp) +- return priv->fan->bios.min_duty; +- else if (temp > linear_max_temp) +- return priv->fan->bios.max_duty; +- +- /* we are in the linear zone */ +- duty = (temp - linear_min_temp); +- duty *= (priv->fan->bios.max_duty - priv->fan->bios.min_duty); +- duty /= (linear_max_temp - linear_min_temp); +- duty += priv->fan->bios.min_duty; +- +- return duty; +-} +- +-static void +-nouveau_therm_update(struct nouveau_therm *therm, int mode) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(therm); +- struct nouveau_therm_priv *priv = (void *)therm; +- unsigned long flags; +- bool immd = true; +- bool poll = true; +- int duty = -1; +- +- spin_lock_irqsave(&priv->lock, flags); +- if (mode < 0) +- mode = priv->mode; +- priv->mode = mode; +- +- switch (mode) { +- case NOUVEAU_THERM_CTRL_MANUAL: +- ptimer->alarm_cancel(ptimer, &priv->alarm); +- duty = nouveau_therm_fan_get(therm); +- if (duty < 0) +- duty = 100; +- poll = false; +- break; +- case NOUVEAU_THERM_CTRL_AUTO: +- switch(priv->fan->bios.fan_mode) { +- case NVBIOS_THERM_FAN_TRIP: +- duty = nouveau_therm_update_trip(therm); +- break; +- case NVBIOS_THERM_FAN_LINEAR: +- duty = nouveau_therm_update_linear(therm); +- break; +- case NVBIOS_THERM_FAN_OTHER: +- if (priv->cstate) +- duty = priv->cstate; +- poll = false; +- break; +- } +- immd = false; +- break; +- case NOUVEAU_THERM_CTRL_NONE: +- default: +- ptimer->alarm_cancel(ptimer, &priv->alarm); +- poll = false; +- } +- +- if (list_empty(&priv->alarm.head) && poll) +- ptimer->alarm(ptimer, 1000000000ULL, &priv->alarm); +- spin_unlock_irqrestore(&priv->lock, flags); +- +- if (duty >= 0) { +- nv_debug(therm, "FAN target request: %d%%\n", duty); +- nouveau_therm_fan_set(therm, immd, duty); +- } +-} +- +-int +-nouveau_therm_cstate(struct nouveau_therm *ptherm, int fan, int dir) +-{ +- struct nouveau_therm_priv *priv = (void *)ptherm; +- if (!dir || (dir < 0 && fan < priv->cstate) || +- (dir > 0 && fan > priv->cstate)) { +- nv_debug(ptherm, "default fan speed -> %d%%\n", fan); +- priv->cstate = fan; +- nouveau_therm_update(ptherm, -1); +- } +- return 0; +-} +- +-static void +-nouveau_therm_alarm(struct nouveau_alarm *alarm) +-{ +- struct nouveau_therm_priv *priv = +- container_of(alarm, struct nouveau_therm_priv, alarm); +- nouveau_therm_update(&priv->base, -1); +-} +- +-int +-nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_device *device = nv_device(therm); +- static const char *name[] = { +- "disabled", +- "manual", +- "automatic" +- }; +- +- /* The default PPWR ucode on fermi interferes with fan management */ +- if ((mode >= ARRAY_SIZE(name)) || +- (mode != NOUVEAU_THERM_CTRL_NONE && device->card_type >= NV_C0 && +- !nouveau_subdev(device, NVDEV_SUBDEV_PWR))) +- return -EINVAL; +- +- /* do not allow automatic fan management if the thermal sensor is +- * not available */ +- if (mode == NOUVEAU_THERM_CTRL_AUTO && therm->temp_get(therm) < 0) +- return -EINVAL; +- +- if (priv->mode == mode) +- return 0; +- +- nv_info(therm, "fan management: %s\n", name[mode]); +- nouveau_therm_update(therm, mode); +- return 0; +-} +- +-int +-nouveau_therm_attr_get(struct nouveau_therm *therm, +- enum nouveau_therm_attr_type type) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- +- switch (type) { +- case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY: +- return priv->fan->bios.min_duty; +- case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY: +- return priv->fan->bios.max_duty; +- case NOUVEAU_THERM_ATTR_FAN_MODE: +- return priv->mode; +- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST: +- return priv->bios_sensor.thrs_fan_boost.temp; +- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST: +- return priv->bios_sensor.thrs_fan_boost.hysteresis; +- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK: +- return priv->bios_sensor.thrs_down_clock.temp; +- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST: +- return priv->bios_sensor.thrs_down_clock.hysteresis; +- case NOUVEAU_THERM_ATTR_THRS_CRITICAL: +- return priv->bios_sensor.thrs_critical.temp; +- case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST: +- return priv->bios_sensor.thrs_critical.hysteresis; +- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN: +- return priv->bios_sensor.thrs_shutdown.temp; +- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST: +- return priv->bios_sensor.thrs_shutdown.hysteresis; +- } +- +- return -EINVAL; +-} +- +-int +-nouveau_therm_attr_set(struct nouveau_therm *therm, +- enum nouveau_therm_attr_type type, int value) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- +- switch (type) { +- case NOUVEAU_THERM_ATTR_FAN_MIN_DUTY: +- if (value < 0) +- value = 0; +- if (value > priv->fan->bios.max_duty) +- value = priv->fan->bios.max_duty; +- priv->fan->bios.min_duty = value; +- return 0; +- case NOUVEAU_THERM_ATTR_FAN_MAX_DUTY: +- if (value < 0) +- value = 0; +- if (value < priv->fan->bios.min_duty) +- value = priv->fan->bios.min_duty; +- priv->fan->bios.max_duty = value; +- return 0; +- case NOUVEAU_THERM_ATTR_FAN_MODE: +- return nouveau_therm_fan_mode(therm, value); +- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST: +- priv->bios_sensor.thrs_fan_boost.temp = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST: +- priv->bios_sensor.thrs_fan_boost.hysteresis = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK: +- priv->bios_sensor.thrs_down_clock.temp = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST: +- priv->bios_sensor.thrs_down_clock.hysteresis = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_CRITICAL: +- priv->bios_sensor.thrs_critical.temp = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST: +- priv->bios_sensor.thrs_critical.hysteresis = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN: +- priv->bios_sensor.thrs_shutdown.temp = value; +- priv->sensor.program_alarms(therm); +- return 0; +- case NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST: +- priv->bios_sensor.thrs_shutdown.hysteresis = value; +- priv->sensor.program_alarms(therm); +- return 0; +- } +- +- return -EINVAL; +-} +- +-int +-_nouveau_therm_init(struct nouveau_object *object) +-{ +- struct nouveau_therm *therm = (void *)object; +- struct nouveau_therm_priv *priv = (void *)therm; +- int ret; +- +- ret = nouveau_subdev_init(&therm->base); +- if (ret) +- return ret; +- +- if (priv->suspend >= 0) { +- /* restore the pwm value only when on manual or auto mode */ +- if (priv->suspend > 0) +- nouveau_therm_fan_set(therm, true, priv->fan->percent); +- +- nouveau_therm_fan_mode(therm, priv->suspend); +- } +- nouveau_therm_sensor_init(therm); +- nouveau_therm_fan_init(therm); +- return 0; +-} +- +-int +-_nouveau_therm_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nouveau_therm *therm = (void *)object; +- struct nouveau_therm_priv *priv = (void *)therm; +- +- nouveau_therm_fan_fini(therm, suspend); +- nouveau_therm_sensor_fini(therm, suspend); +- if (suspend) { +- priv->suspend = priv->mode; +- priv->mode = NOUVEAU_THERM_CTRL_NONE; +- } +- +- return nouveau_subdev_fini(&therm->base, suspend); +-} +- +-int +-nouveau_therm_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, +- int length, void **pobject) +-{ +- struct nouveau_therm_priv *priv; +- int ret; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "PTHERM", +- "therm", length, pobject); +- priv = *pobject; +- if (ret) +- return ret; +- +- nouveau_alarm_init(&priv->alarm, nouveau_therm_alarm); +- spin_lock_init(&priv->lock); +- spin_lock_init(&priv->sensor.alarm_program_lock); +- +- priv->base.fan_get = nouveau_therm_fan_user_get; +- priv->base.fan_set = nouveau_therm_fan_user_set; +- priv->base.fan_sense = nouveau_therm_fan_sense; +- priv->base.attr_get = nouveau_therm_attr_get; +- priv->base.attr_set = nouveau_therm_attr_set; +- priv->mode = priv->suspend = -1; /* undefined */ +- return 0; +-} +- +-int +-nouveau_therm_preinit(struct nouveau_therm *therm) +-{ +- nouveau_therm_sensor_ctor(therm); +- nouveau_therm_ic_ctor(therm); +- nouveau_therm_fan_ctor(therm); +- +- nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO); +- nouveau_therm_sensor_preinit(therm); +- return 0; +-} +- +-void +-_nouveau_therm_dtor(struct nouveau_object *object) +-{ +- struct nouveau_therm_priv *priv = (void *)object; +- kfree(priv->fan); +- nouveau_subdev_destroy(&priv->base.base); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c +deleted file mode 100644 +index 3656d605..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fan.c ++++ /dev/null +@@ -1,287 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Martin Peres +- */ +- +-#include "priv.h" +- +-#include +-#include +- +-#include +-#include +- +-#include +- +-static int +-nouveau_fan_update(struct nouveau_fan *fan, bool immediate, int target) +-{ +- struct nouveau_therm *therm = fan->parent; +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_timer *ptimer = nouveau_timer(priv); +- unsigned long flags; +- int ret = 0; +- int duty; +- +- /* update target fan speed, restricting to allowed range */ +- spin_lock_irqsave(&fan->lock, flags); +- if (target < 0) +- target = fan->percent; +- target = max_t(u8, target, fan->bios.min_duty); +- target = min_t(u8, target, fan->bios.max_duty); +- if (fan->percent != target) { +- nv_debug(therm, "FAN target: %d\n", target); +- fan->percent = target; +- } +- +- /* check that we're not already at the target duty cycle */ +- duty = fan->get(therm); +- if (duty == target) { +- spin_unlock_irqrestore(&fan->lock, flags); +- return 0; +- } +- +- /* smooth out the fanspeed increase/decrease */ +- if (!immediate && duty >= 0) { +- /* the constant "3" is a rough approximation taken from +- * nvidia's behaviour. +- * it is meant to bump the fan speed more incrementally +- */ +- if (duty < target) +- duty = min(duty + 3, target); +- else if (duty > target) +- duty = max(duty - 3, target); +- } else { +- duty = target; +- } +- +- nv_debug(therm, "FAN update: %d\n", duty); +- ret = fan->set(therm, duty); +- if (ret) { +- spin_unlock_irqrestore(&fan->lock, flags); +- return ret; +- } +- +- /* fan speed updated, drop the fan lock before grabbing the +- * alarm-scheduling lock and risking a deadlock +- */ +- spin_unlock_irqrestore(&fan->lock, flags); +- +- /* schedule next fan update, if not at target speed already */ +- if (list_empty(&fan->alarm.head) && target != duty) { +- u16 bump_period = fan->bios.bump_period; +- u16 slow_down_period = fan->bios.slow_down_period; +- u64 delay; +- +- if (duty > target) +- delay = slow_down_period; +- else if (duty == target) +- delay = min(bump_period, slow_down_period) ; +- else +- delay = bump_period; +- +- ptimer->alarm(ptimer, delay * 1000 * 1000, &fan->alarm); +- } +- +- return ret; +-} +- +-static void +-nouveau_fan_alarm(struct nouveau_alarm *alarm) +-{ +- struct nouveau_fan *fan = container_of(alarm, struct nouveau_fan, alarm); +- nouveau_fan_update(fan, false, -1); +-} +- +-int +-nouveau_therm_fan_get(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- return priv->fan->get(therm); +-} +- +-int +-nouveau_therm_fan_set(struct nouveau_therm *therm, bool immediate, int percent) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- return nouveau_fan_update(priv->fan, immediate, percent); +-} +- +-int +-nouveau_therm_fan_sense(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_timer *ptimer = nouveau_timer(therm); +- struct nouveau_gpio *gpio = nouveau_gpio(therm); +- u32 cycles, cur, prev; +- u64 start, end, tach; +- +- if (priv->fan->tach.func == DCB_GPIO_UNUSED) +- return -ENODEV; +- +- /* Time a complete rotation and extrapolate to RPM: +- * When the fan spins, it changes the value of GPIO FAN_SENSE. +- * We get 4 changes (0 -> 1 -> 0 -> 1) per complete rotation. +- */ +- start = ptimer->read(ptimer); +- prev = gpio->get(gpio, 0, priv->fan->tach.func, priv->fan->tach.line); +- cycles = 0; +- do { +- usleep_range(500, 1000); /* supports 0 < rpm < 7500 */ +- +- cur = gpio->get(gpio, 0, priv->fan->tach.func, priv->fan->tach.line); +- if (prev != cur) { +- if (!start) +- start = ptimer->read(ptimer); +- cycles++; +- prev = cur; +- } +- } while (cycles < 5 && ptimer->read(ptimer) - start < 250000000); +- end = ptimer->read(ptimer); +- +- if (cycles == 5) { +- tach = (u64)60000000000ULL; +- do_div(tach, (end - start)); +- return tach; +- } else +- return 0; +-} +- +-int +-nouveau_therm_fan_user_get(struct nouveau_therm *therm) +-{ +- return nouveau_therm_fan_get(therm); +-} +- +-int +-nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- +- if (priv->mode != NOUVEAU_THERM_CTRL_MANUAL) +- return -EINVAL; +- +- return nouveau_therm_fan_set(therm, true, percent); +-} +- +-static void +-nouveau_therm_fan_set_defaults(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- +- priv->fan->bios.pwm_freq = 0; +- priv->fan->bios.min_duty = 0; +- priv->fan->bios.max_duty = 100; +- priv->fan->bios.bump_period = 500; +- priv->fan->bios.slow_down_period = 2000; +- priv->fan->bios.linear_min_temp = 40; +- priv->fan->bios.linear_max_temp = 85; +-} +- +-static void +-nouveau_therm_fan_safety_checks(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- +- if (priv->fan->bios.min_duty > 100) +- priv->fan->bios.min_duty = 100; +- if (priv->fan->bios.max_duty > 100) +- priv->fan->bios.max_duty = 100; +- +- if (priv->fan->bios.min_duty > priv->fan->bios.max_duty) +- priv->fan->bios.min_duty = priv->fan->bios.max_duty; +-} +- +-int +-nouveau_therm_fan_init(struct nouveau_therm *therm) +-{ +- return 0; +-} +- +-int +-nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_timer *ptimer = nouveau_timer(therm); +- +- if (suspend) +- ptimer->alarm_cancel(ptimer, &priv->fan->alarm); +- return 0; +-} +- +-int +-nouveau_therm_fan_ctor(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_gpio *gpio = nouveau_gpio(therm); +- struct nouveau_bios *bios = nouveau_bios(therm); +- struct dcb_gpio_func func; +- int ret; +- +- /* attempt to locate a drivable fan, and determine control method */ +- ret = gpio->find(gpio, 0, DCB_GPIO_FAN, 0xff, &func); +- if (ret == 0) { +- /* FIXME: is this really the place to perform such checks ? */ +- if (func.line != 16 && func.log[0] & DCB_GPIO_LOG_DIR_IN) { +- nv_debug(therm, "GPIO_FAN is in input mode\n"); +- ret = -EINVAL; +- } else { +- ret = nouveau_fanpwm_create(therm, &func); +- if (ret != 0) +- ret = nouveau_fantog_create(therm, &func); +- } +- } +- +- /* no controllable fan found, create a dummy fan module */ +- if (ret != 0) { +- ret = nouveau_fannil_create(therm); +- if (ret) +- return ret; +- } +- +- nv_info(therm, "FAN control: %s\n", priv->fan->type); +- +- /* read the current speed, it is useful when resuming */ +- priv->fan->percent = nouveau_therm_fan_get(therm); +- +- /* attempt to detect a tachometer connection */ +- ret = gpio->find(gpio, 0, DCB_GPIO_FAN_SENSE, 0xff, &priv->fan->tach); +- if (ret) +- priv->fan->tach.func = DCB_GPIO_UNUSED; +- +- /* initialise fan bump/slow update handling */ +- priv->fan->parent = therm; +- nouveau_alarm_init(&priv->fan->alarm, nouveau_fan_alarm); +- spin_lock_init(&priv->fan->lock); +- +- /* other random init... */ +- nouveau_therm_fan_set_defaults(therm); +- nvbios_perf_fan_parse(bios, &priv->fan->perf); +- if (!nvbios_fan_parse(bios, &priv->fan->bios)) { +- nv_debug(therm, "parsing the fan table failed\n"); +- if (nvbios_therm_fan_parse(bios, &priv->fan->bios)) +- nv_error(therm, "parsing both fan tables failed\n"); +- } +- nouveau_therm_fan_safety_checks(therm); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c +deleted file mode 100644 +index b78c182e..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fannil.c ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-static int +-nouveau_fannil_get(struct nouveau_therm *therm) +-{ +- return -ENODEV; +-} +- +-static int +-nouveau_fannil_set(struct nouveau_therm *therm, int percent) +-{ +- return -ENODEV; +-} +- +-int +-nouveau_fannil_create(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_fan *priv; +- +- priv = kzalloc(sizeof(*priv), GFP_KERNEL); +- tpriv->fan = priv; +- if (!priv) +- return -ENOMEM; +- +- priv->type = "none / external"; +- priv->get = nouveau_fannil_get; +- priv->set = nouveau_fannil_set; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c +deleted file mode 100644 +index c629d7f2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fanpwm.c ++++ /dev/null +@@ -1,113 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Martin Peres +- */ +- +-#include +-#include +-#include +-#include +- +-#include "priv.h" +- +-struct nouveau_fanpwm_priv { +- struct nouveau_fan base; +- struct dcb_gpio_func func; +-}; +- +-static int +-nouveau_fanpwm_get(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan; +- struct nouveau_gpio *gpio = nouveau_gpio(therm); +- int card_type = nv_device(therm)->card_type; +- u32 divs, duty; +- int ret; +- +- ret = therm->pwm_get(therm, priv->func.line, &divs, &duty); +- if (ret == 0 && divs) { +- divs = max(divs, duty); +- if (card_type <= NV_40 || (priv->func.log[0] & 1)) +- duty = divs - duty; +- return (duty * 100) / divs; +- } +- +- return gpio->get(gpio, 0, priv->func.func, priv->func.line) * 100; +-} +- +-static int +-nouveau_fanpwm_set(struct nouveau_therm *therm, int percent) +-{ +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_fanpwm_priv *priv = (void *)tpriv->fan; +- int card_type = nv_device(therm)->card_type; +- u32 divs, duty; +- int ret; +- +- divs = priv->base.perf.pwm_divisor; +- if (priv->base.bios.pwm_freq) { +- divs = 1; +- if (therm->pwm_clock) +- divs = therm->pwm_clock(therm, priv->func.line); +- divs /= priv->base.bios.pwm_freq; +- } +- +- duty = ((divs * percent) + 99) / 100; +- if (card_type <= NV_40 || (priv->func.log[0] & 1)) +- duty = divs - duty; +- +- ret = therm->pwm_set(therm, priv->func.line, divs, duty); +- if (ret == 0) +- ret = therm->pwm_ctrl(therm, priv->func.line, true); +- return ret; +-} +- +-int +-nouveau_fanpwm_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) +-{ +- struct nouveau_device *device = nv_device(therm); +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_bios *bios = nouveau_bios(therm); +- struct nouveau_fanpwm_priv *priv; +- struct nvbios_therm_fan fan; +- u32 divs, duty; +- +- nvbios_fan_parse(bios, &fan); +- +- if (!nouveau_boolopt(device->cfgopt, "NvFanPWM", func->param) || +- !therm->pwm_ctrl || fan.type == NVBIOS_THERM_FAN_TOGGLE || +- therm->pwm_get(therm, func->line, &divs, &duty) == -ENODEV) +- return -ENODEV; +- +- priv = kzalloc(sizeof(*priv), GFP_KERNEL); +- tpriv->fan = &priv->base; +- if (!priv) +- return -ENOMEM; +- +- priv->base.type = "PWM"; +- priv->base.get = nouveau_fanpwm_get; +- priv->base.set = nouveau_fanpwm_set; +- priv->func = *func; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c b/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c +deleted file mode 100644 +index f69dab11..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/fantog.c ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * Copyright 2012 The Nouveau community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-#include +-#include +- +-#include +-#include +- +-struct nouveau_fantog_priv { +- struct nouveau_fan base; +- struct nouveau_alarm alarm; +- spinlock_t lock; +- u32 period_us; +- u32 percent; +- struct dcb_gpio_func func; +-}; +- +-static void +-nouveau_fantog_update(struct nouveau_fantog_priv *priv, int percent) +-{ +- struct nouveau_therm_priv *tpriv = (void *)priv->base.parent; +- struct nouveau_timer *ptimer = nouveau_timer(tpriv); +- struct nouveau_gpio *gpio = nouveau_gpio(tpriv); +- unsigned long flags; +- int duty; +- +- spin_lock_irqsave(&priv->lock, flags); +- if (percent < 0) +- percent = priv->percent; +- priv->percent = percent; +- +- duty = !gpio->get(gpio, 0, DCB_GPIO_FAN, 0xff); +- gpio->set(gpio, 0, DCB_GPIO_FAN, 0xff, duty); +- +- if (list_empty(&priv->alarm.head) && percent != (duty * 100)) { +- u64 next_change = (percent * priv->period_us) / 100; +- if (!duty) +- next_change = priv->period_us - next_change; +- ptimer->alarm(ptimer, next_change * 1000, &priv->alarm); +- } +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-static void +-nouveau_fantog_alarm(struct nouveau_alarm *alarm) +-{ +- struct nouveau_fantog_priv *priv = +- container_of(alarm, struct nouveau_fantog_priv, alarm); +- nouveau_fantog_update(priv, -1); +-} +- +-static int +-nouveau_fantog_get(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_fantog_priv *priv = (void *)tpriv->fan; +- return priv->percent; +-} +- +-static int +-nouveau_fantog_set(struct nouveau_therm *therm, int percent) +-{ +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_fantog_priv *priv = (void *)tpriv->fan; +- if (therm->pwm_ctrl) +- therm->pwm_ctrl(therm, priv->func.line, false); +- nouveau_fantog_update(priv, percent); +- return 0; +-} +- +-int +-nouveau_fantog_create(struct nouveau_therm *therm, struct dcb_gpio_func *func) +-{ +- struct nouveau_therm_priv *tpriv = (void *)therm; +- struct nouveau_fantog_priv *priv; +- int ret; +- +- if (therm->pwm_ctrl) { +- ret = therm->pwm_ctrl(therm, func->line, false); +- if (ret) +- return ret; +- } +- +- priv = kzalloc(sizeof(*priv), GFP_KERNEL); +- tpriv->fan = &priv->base; +- if (!priv) +- return -ENOMEM; +- +- priv->base.type = "toggle"; +- priv->base.get = nouveau_fantog_get; +- priv->base.set = nouveau_fantog_set; +- nouveau_alarm_init(&priv->alarm, nouveau_fantog_alarm); +- priv->period_us = 100000; /* 10Hz */ +- priv->percent = 100; +- priv->func = *func; +- spin_lock_init(&priv->lock); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c b/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c +deleted file mode 100644 +index 668cf332..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/gm107.c ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* +- * Copyright 2014 Martin Peres +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-struct gm107_therm_priv { +- struct nouveau_therm_priv base; +-}; +- +-static int +-gm107_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +-{ +- /* nothing to do, it seems hardwired */ +- return 0; +-} +- +-static int +-gm107_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +-{ +- *divs = nv_rd32(therm, 0x10eb20) & 0x1fff; +- *duty = nv_rd32(therm, 0x10eb24) & 0x1fff; +- return 0; +-} +- +-static int +-gm107_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +-{ +- nv_mask(therm, 0x10eb10, 0x1fff, divs); /* keep the high bits */ +- nv_wr32(therm, 0x10eb14, duty | 0x80000000); +- return 0; +-} +- +-static int +-gm107_fan_pwm_clock(struct nouveau_therm *therm, int line) +-{ +- return nv_device(therm)->crystal * 1000; +-} +- +-static int +-gm107_therm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct gm107_therm_priv *priv; +- int ret; +- +- ret = nouveau_therm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.base.pwm_ctrl = gm107_fan_pwm_ctrl; +- priv->base.base.pwm_get = gm107_fan_pwm_get; +- priv->base.base.pwm_set = gm107_fan_pwm_set; +- priv->base.base.pwm_clock = gm107_fan_pwm_clock; +- priv->base.base.temp_get = nv84_temp_get; +- priv->base.base.fan_sense = nva3_therm_fan_sense; +- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; +- return nouveau_therm_preinit(&priv->base.base); +-} +- +-struct nouveau_oclass +-gm107_therm_oclass = { +- .handle = NV_SUBDEV(THERM, 0x117), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = gm107_therm_ctor, +- .dtor = _nouveau_therm_dtor, +- .init = nvd0_therm_init, +- .fini = nv84_therm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c +deleted file mode 100644 +index ca9ad9fd..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/ic.c ++++ /dev/null +@@ -1,121 +0,0 @@ +-/* +- * Copyright 2012 Nouveau community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-#include +-#include +- +-static bool +-probe_monitoring_device(struct nouveau_i2c_port *i2c, +- struct i2c_board_info *info, void *data) +-{ +- struct nouveau_therm_priv *priv = data; +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- struct i2c_client *client; +- +- request_module("%s%s", I2C_MODULE_PREFIX, info->type); +- +- client = i2c_new_device(&i2c->adapter, info); +- if (!client) +- return false; +- +- if (!client->dev.driver || +- to_i2c_driver(client->dev.driver)->detect(client, info)) { +- i2c_unregister_device(client); +- return false; +- } +- +- nv_info(priv, +- "Found an %s at address 0x%x (controlled by lm_sensors, " +- "temp offset %+i C)\n", +- info->type, info->addr, sensor->offset_constant); +- priv->ic = client; +- +- return true; +-} +- +-static struct nouveau_i2c_board_info +-nv_board_infos[] = { +- { { I2C_BOARD_INFO("w83l785ts", 0x2d) }, 0 }, +- { { I2C_BOARD_INFO("w83781d", 0x2d) }, 0 }, +- { { I2C_BOARD_INFO("adt7473", 0x2e) }, 40 }, +- { { I2C_BOARD_INFO("adt7473", 0x2d) }, 40 }, +- { { I2C_BOARD_INFO("adt7473", 0x2c) }, 40 }, +- { { I2C_BOARD_INFO("f75375", 0x2e) }, 0 }, +- { { I2C_BOARD_INFO("lm99", 0x4c) }, 0 }, +- { { I2C_BOARD_INFO("lm90", 0x4c) }, 0 }, +- { { I2C_BOARD_INFO("lm90", 0x4d) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x18) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x19) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x1a) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x29) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x2a) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x2b) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x4c) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x4d) }, 0 }, +- { { I2C_BOARD_INFO("adm1021", 0x4e) }, 0 }, +- { { I2C_BOARD_INFO("lm63", 0x18) }, 0 }, +- { { I2C_BOARD_INFO("lm63", 0x4e) }, 0 }, +- { } +-}; +- +-void +-nouveau_therm_ic_ctor(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_bios *bios = nouveau_bios(therm); +- struct nouveau_i2c *i2c = nouveau_i2c(therm); +- struct nvbios_extdev_func extdev_entry; +- +- if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_LM89, &extdev_entry)) { +- struct nouveau_i2c_board_info board[] = { +- { { I2C_BOARD_INFO("lm90", extdev_entry.addr >> 1) }, 0}, +- { } +- }; +- +- i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device", +- board, probe_monitoring_device, therm); +- if (priv->ic) +- return; +- } +- +- if (!nvbios_extdev_find(bios, NVBIOS_EXTDEV_ADT7473, &extdev_entry)) { +- struct nouveau_i2c_board_info board[] = { +- { { I2C_BOARD_INFO("adt7473", extdev_entry.addr >> 1) }, 20 }, +- { } +- }; +- +- i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device", +- board, probe_monitoring_device, therm); +- if (priv->ic) +- return; +- } +- +- /* The vbios doesn't provide the address of an exisiting monitoring +- device. Let's try our static list. +- */ +- i2c->identify(i2c, NV_I2C_DEFAULT(0), "monitoring device", +- nv_board_infos, probe_monitoring_device, therm); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c +deleted file mode 100644 +index 002e51b3..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv40.c ++++ /dev/null +@@ -1,224 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Martin Peres +- */ +- +-#include "priv.h" +- +-struct nv40_therm_priv { +- struct nouveau_therm_priv base; +-}; +- +-enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 }; +- +-static enum nv40_sensor_style +-nv40_sensor_style(struct nouveau_therm *therm) +-{ +- struct nouveau_device *device = nv_device(therm); +- +- switch (device->chipset) { +- case 0x43: +- case 0x44: +- case 0x4a: +- case 0x47: +- return OLD_STYLE; +- +- case 0x46: +- case 0x49: +- case 0x4b: +- case 0x4e: +- case 0x4c: +- case 0x67: +- case 0x68: +- case 0x63: +- return NEW_STYLE; +- default: +- return INVALID_STYLE; +- } +-} +- +-static int +-nv40_sensor_setup(struct nouveau_therm *therm) +-{ +- enum nv40_sensor_style style = nv40_sensor_style(therm); +- +- /* enable ADC readout and disable the ALARM threshold */ +- if (style == NEW_STYLE) { +- nv_mask(therm, 0x15b8, 0x80000000, 0); +- nv_wr32(therm, 0x15b0, 0x80003fff); +- mdelay(20); /* wait for the temperature to stabilize */ +- return nv_rd32(therm, 0x15b4) & 0x3fff; +- } else if (style == OLD_STYLE) { +- nv_wr32(therm, 0x15b0, 0xff); +- mdelay(20); /* wait for the temperature to stabilize */ +- return nv_rd32(therm, 0x15b4) & 0xff; +- } else +- return -ENODEV; +-} +- +-static int +-nv40_temp_get(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- enum nv40_sensor_style style = nv40_sensor_style(therm); +- int core_temp; +- +- if (style == NEW_STYLE) { +- nv_wr32(therm, 0x15b0, 0x80003fff); +- core_temp = nv_rd32(therm, 0x15b4) & 0x3fff; +- } else if (style == OLD_STYLE) { +- nv_wr32(therm, 0x15b0, 0xff); +- core_temp = nv_rd32(therm, 0x15b4) & 0xff; +- } else +- return -ENODEV; +- +- /* if the slope or the offset is unset, do no use the sensor */ +- if (!sensor->slope_div || !sensor->slope_mult || +- !sensor->offset_num || !sensor->offset_den) +- return -ENODEV; +- +- core_temp = core_temp * sensor->slope_mult / sensor->slope_div; +- core_temp = core_temp + sensor->offset_num / sensor->offset_den; +- core_temp = core_temp + sensor->offset_constant - 8; +- +- /* reserve negative temperatures for errors */ +- if (core_temp < 0) +- core_temp = 0; +- +- return core_temp; +-} +- +-static int +-nv40_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +-{ +- u32 mask = enable ? 0x80000000 : 0x0000000; +- if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask); +- else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask); +- else { +- nv_error(therm, "unknown pwm ctrl for gpio %d\n", line); +- return -ENODEV; +- } +- return 0; +-} +- +-static int +-nv40_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +-{ +- if (line == 2) { +- u32 reg = nv_rd32(therm, 0x0010f0); +- if (reg & 0x80000000) { +- *duty = (reg & 0x7fff0000) >> 16; +- *divs = (reg & 0x00007fff); +- return 0; +- } +- } else +- if (line == 9) { +- u32 reg = nv_rd32(therm, 0x0015f4); +- if (reg & 0x80000000) { +- *divs = nv_rd32(therm, 0x0015f8); +- *duty = (reg & 0x7fffffff); +- return 0; +- } +- } else { +- nv_error(therm, "unknown pwm ctrl for gpio %d\n", line); +- return -ENODEV; +- } +- +- return -EINVAL; +-} +- +-static int +-nv40_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +-{ +- if (line == 2) { +- nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); +- } else +- if (line == 9) { +- nv_wr32(therm, 0x0015f8, divs); +- nv_mask(therm, 0x0015f4, 0x7fffffff, duty); +- } else { +- nv_error(therm, "unknown pwm ctrl for gpio %d\n", line); +- return -ENODEV; +- } +- +- return 0; +-} +- +-void +-nv40_therm_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_therm *therm = nouveau_therm(subdev); +- uint32_t stat = nv_rd32(therm, 0x1100); +- +- /* traitement */ +- +- /* ack all IRQs */ +- nv_wr32(therm, 0x1100, 0x70000); +- +- nv_error(therm, "THERM received an IRQ: stat = %x\n", stat); +-} +- +-static int +-nv40_therm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv40_therm_priv *priv; +- int ret; +- +- ret = nouveau_therm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl; +- priv->base.base.pwm_get = nv40_fan_pwm_get; +- priv->base.base.pwm_set = nv40_fan_pwm_set; +- priv->base.base.temp_get = nv40_temp_get; +- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; +- nv_subdev(priv)->intr = nv40_therm_intr; +- return nouveau_therm_preinit(&priv->base.base); +-} +- +-static int +-nv40_therm_init(struct nouveau_object *object) +-{ +- struct nouveau_therm *therm = (void *)object; +- +- nv40_sensor_setup(therm); +- +- return _nouveau_therm_init(object); +-} +- +-struct nouveau_oclass +-nv40_therm_oclass = { +- .handle = NV_SUBDEV(THERM, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_therm_ctor, +- .dtor = _nouveau_therm_dtor, +- .init = nv40_therm_init, +- .fini = _nouveau_therm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c +deleted file mode 100644 +index 321db927..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv50.c ++++ /dev/null +@@ -1,197 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Martin Peres +- */ +- +-#include "priv.h" +- +-struct nv50_therm_priv { +- struct nouveau_therm_priv base; +-}; +- +-static int +-pwm_info(struct nouveau_therm *therm, int *line, int *ctrl, int *indx) +-{ +- if (*line == 0x04) { +- *ctrl = 0x00e100; +- *line = 4; +- *indx = 0; +- } else +- if (*line == 0x09) { +- *ctrl = 0x00e100; +- *line = 9; +- *indx = 1; +- } else +- if (*line == 0x10) { +- *ctrl = 0x00e28c; +- *line = 0; +- *indx = 0; +- } else { +- nv_error(therm, "unknown pwm ctrl for gpio %d\n", *line); +- return -ENODEV; +- } +- +- return 0; +-} +- +-int +-nv50_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +-{ +- u32 data = enable ? 0x00000001 : 0x00000000; +- int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); +- if (ret == 0) +- nv_mask(therm, ctrl, 0x00010001 << line, data << line); +- return ret; +-} +- +-int +-nv50_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +-{ +- int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); +- if (ret) +- return ret; +- +- if (nv_rd32(therm, ctrl) & (1 << line)) { +- *divs = nv_rd32(therm, 0x00e114 + (id * 8)); +- *duty = nv_rd32(therm, 0x00e118 + (id * 8)); +- return 0; +- } +- +- return -EINVAL; +-} +- +-int +-nv50_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +-{ +- int ctrl, id, ret = pwm_info(therm, &line, &ctrl, &id); +- if (ret) +- return ret; +- +- nv_wr32(therm, 0x00e114 + (id * 8), divs); +- nv_wr32(therm, 0x00e118 + (id * 8), duty | 0x80000000); +- return 0; +-} +- +-int +-nv50_fan_pwm_clock(struct nouveau_therm *therm, int line) +-{ +- int chipset = nv_device(therm)->chipset; +- int crystal = nv_device(therm)->crystal; +- int pwm_clock; +- +- /* determine the PWM source clock */ +- if (chipset > 0x50 && chipset < 0x94) { +- u8 pwm_div = nv_rd32(therm, 0x410c); +- if (nv_rd32(therm, 0xc040) & 0x800000) { +- /* Use the HOST clock (100 MHz) +- * Where does this constant(2.4) comes from? */ +- pwm_clock = (100000000 >> pwm_div) * 10 / 24; +- } else { +- /* Where does this constant(20) comes from? */ +- pwm_clock = (crystal * 1000) >> pwm_div; +- pwm_clock /= 20; +- } +- } else { +- pwm_clock = (crystal * 1000) / 20; +- } +- +- return pwm_clock; +-} +- +-static void +-nv50_sensor_setup(struct nouveau_therm *therm) +-{ +- nv_mask(therm, 0x20010, 0x40000000, 0x0); +- mdelay(20); /* wait for the temperature to stabilize */ +-} +- +-static int +-nv50_temp_get(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- int core_temp; +- +- core_temp = nv_rd32(therm, 0x20014) & 0x3fff; +- +- /* if the slope or the offset is unset, do no use the sensor */ +- if (!sensor->slope_div || !sensor->slope_mult || +- !sensor->offset_num || !sensor->offset_den) +- return -ENODEV; +- +- core_temp = core_temp * sensor->slope_mult / sensor->slope_div; +- core_temp = core_temp + sensor->offset_num / sensor->offset_den; +- core_temp = core_temp + sensor->offset_constant - 8; +- +- /* reserve negative temperatures for errors */ +- if (core_temp < 0) +- core_temp = 0; +- +- return core_temp; +-} +- +-static int +-nv50_therm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_therm_priv *priv; +- int ret; +- +- ret = nouveau_therm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl; +- priv->base.base.pwm_get = nv50_fan_pwm_get; +- priv->base.base.pwm_set = nv50_fan_pwm_set; +- priv->base.base.pwm_clock = nv50_fan_pwm_clock; +- priv->base.base.temp_get = nv50_temp_get; +- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; +- nv_subdev(priv)->intr = nv40_therm_intr; +- +- return nouveau_therm_preinit(&priv->base.base); +-} +- +-static int +-nv50_therm_init(struct nouveau_object *object) +-{ +- struct nouveau_therm *therm = (void *)object; +- +- nv50_sensor_setup(therm); +- +- return _nouveau_therm_init(object); +-} +- +-struct nouveau_oclass +-nv50_therm_oclass = { +- .handle = NV_SUBDEV(THERM, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_therm_ctor, +- .dtor = _nouveau_therm_dtor, +- .init = nv50_therm_init, +- .fini = _nouveau_therm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c +deleted file mode 100644 +index 14e2e09b..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nv84.c ++++ /dev/null +@@ -1,268 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- * Martin Peres +- */ +- +-#include "priv.h" +-#include +- +-struct nv84_therm_priv { +- struct nouveau_therm_priv base; +-}; +- +-int +-nv84_temp_get(struct nouveau_therm *therm) +-{ +- struct nouveau_fuse *fuse = nouveau_fuse(therm); +- +- if (nv_ro32(fuse, 0x1a8) == 1) +- return nv_rd32(therm, 0x20400); +- else +- return -ENODEV; +-} +- +-void +-nv84_sensor_setup(struct nouveau_therm *therm) +-{ +- struct nouveau_fuse *fuse = nouveau_fuse(therm); +- +- /* enable temperature reading for cards with insane defaults */ +- if (nv_ro32(fuse, 0x1a8) == 1) { +- nv_mask(therm, 0x20008, 0x80008000, 0x80000000); +- nv_mask(therm, 0x2000c, 0x80000003, 0x00000000); +- mdelay(20); /* wait for the temperature to stabilize */ +- } +-} +- +-static void +-nv84_therm_program_alarms(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags); +- +- /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ +- nv_wr32(therm, 0x20000, 0x000003ff); +- +- /* shutdown: The computer should be shutdown when reached */ +- nv_wr32(therm, 0x20484, sensor->thrs_shutdown.hysteresis); +- nv_wr32(therm, 0x20480, sensor->thrs_shutdown.temp); +- +- /* THRS_1 : fan boost*/ +- nv_wr32(therm, 0x204c4, sensor->thrs_fan_boost.temp); +- +- /* THRS_2 : critical */ +- nv_wr32(therm, 0x204c0, sensor->thrs_critical.temp); +- +- /* THRS_4 : down clock */ +- nv_wr32(therm, 0x20414, sensor->thrs_down_clock.temp); +- spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags); +- +- nv_debug(therm, +- "Programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n", +- sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis, +- sensor->thrs_down_clock.temp, +- sensor->thrs_down_clock.hysteresis, +- sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis, +- sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis); +- +-} +- +-/* must be called with alarm_program_lock taken ! */ +-static void +-nv84_therm_threshold_hyst_emulation(struct nouveau_therm *therm, +- uint32_t thrs_reg, u8 status_bit, +- const struct nvbios_therm_threshold *thrs, +- enum nouveau_therm_thrs thrs_name) +-{ +- enum nouveau_therm_thrs_direction direction; +- enum nouveau_therm_thrs_state prev_state, new_state; +- int temp, cur; +- +- prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name); +- temp = nv_rd32(therm, thrs_reg); +- +- /* program the next threshold */ +- if (temp == thrs->temp) { +- nv_wr32(therm, thrs_reg, thrs->temp - thrs->hysteresis); +- new_state = NOUVEAU_THERM_THRS_HIGHER; +- } else { +- nv_wr32(therm, thrs_reg, thrs->temp); +- new_state = NOUVEAU_THERM_THRS_LOWER; +- } +- +- /* fix the state (in case someone reprogrammed the alarms) */ +- cur = therm->temp_get(therm); +- if (new_state == NOUVEAU_THERM_THRS_LOWER && cur > thrs->temp) +- new_state = NOUVEAU_THERM_THRS_HIGHER; +- else if (new_state == NOUVEAU_THERM_THRS_HIGHER && +- cur < thrs->temp - thrs->hysteresis) +- new_state = NOUVEAU_THERM_THRS_LOWER; +- nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state); +- +- /* find the direction */ +- if (prev_state < new_state) +- direction = NOUVEAU_THERM_THRS_RISING; +- else if (prev_state > new_state) +- direction = NOUVEAU_THERM_THRS_FALLING; +- else +- return; +- +- /* advertise a change in direction */ +- nouveau_therm_sensor_event(therm, thrs_name, direction); +-} +- +-static void +-nv84_therm_intr(struct nouveau_subdev *subdev) +-{ +- struct nouveau_therm *therm = nouveau_therm(subdev); +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- unsigned long flags; +- uint32_t intr; +- +- spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags); +- +- intr = nv_rd32(therm, 0x20100) & 0x3ff; +- +- /* THRS_4: downclock */ +- if (intr & 0x002) { +- nv84_therm_threshold_hyst_emulation(therm, 0x20414, 24, +- &sensor->thrs_down_clock, +- NOUVEAU_THERM_THRS_DOWNCLOCK); +- intr &= ~0x002; +- } +- +- /* shutdown */ +- if (intr & 0x004) { +- nv84_therm_threshold_hyst_emulation(therm, 0x20480, 20, +- &sensor->thrs_shutdown, +- NOUVEAU_THERM_THRS_SHUTDOWN); +- intr &= ~0x004; +- } +- +- /* THRS_1 : fan boost */ +- if (intr & 0x008) { +- nv84_therm_threshold_hyst_emulation(therm, 0x204c4, 21, +- &sensor->thrs_fan_boost, +- NOUVEAU_THERM_THRS_FANBOOST); +- intr &= ~0x008; +- } +- +- /* THRS_2 : critical */ +- if (intr & 0x010) { +- nv84_therm_threshold_hyst_emulation(therm, 0x204c0, 22, +- &sensor->thrs_critical, +- NOUVEAU_THERM_THRS_CRITICAL); +- intr &= ~0x010; +- } +- +- if (intr) +- nv_error(therm, "unhandled intr 0x%08x\n", intr); +- +- /* ACK everything */ +- nv_wr32(therm, 0x20100, 0xffffffff); +- nv_wr32(therm, 0x1100, 0x10000); /* PBUS */ +- +- spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags); +-} +- +-static int +-nv84_therm_init(struct nouveau_object *object) +-{ +- struct nv84_therm_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_therm_init(&priv->base.base); +- if (ret) +- return ret; +- +- nv84_sensor_setup(&priv->base.base); +- +- return 0; +-} +- +-static int +-nv84_therm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv84_therm_priv *priv; +- int ret; +- +- ret = nouveau_therm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl; +- priv->base.base.pwm_get = nv50_fan_pwm_get; +- priv->base.base.pwm_set = nv50_fan_pwm_set; +- priv->base.base.pwm_clock = nv50_fan_pwm_clock; +- priv->base.base.temp_get = nv84_temp_get; +- priv->base.sensor.program_alarms = nv84_therm_program_alarms; +- nv_subdev(priv)->intr = nv84_therm_intr; +- +- /* init the thresholds */ +- nouveau_therm_sensor_set_threshold_state(&priv->base.base, +- NOUVEAU_THERM_THRS_SHUTDOWN, +- NOUVEAU_THERM_THRS_LOWER); +- nouveau_therm_sensor_set_threshold_state(&priv->base.base, +- NOUVEAU_THERM_THRS_FANBOOST, +- NOUVEAU_THERM_THRS_LOWER); +- nouveau_therm_sensor_set_threshold_state(&priv->base.base, +- NOUVEAU_THERM_THRS_CRITICAL, +- NOUVEAU_THERM_THRS_LOWER); +- nouveau_therm_sensor_set_threshold_state(&priv->base.base, +- NOUVEAU_THERM_THRS_DOWNCLOCK, +- NOUVEAU_THERM_THRS_LOWER); +- +- return nouveau_therm_preinit(&priv->base.base); +-} +- +-int +-nv84_therm_fini(struct nouveau_object *object, bool suspend) +-{ +- /* Disable PTherm IRQs */ +- nv_wr32(object, 0x20000, 0x00000000); +- +- /* ACK all PTherm IRQs */ +- nv_wr32(object, 0x20100, 0xffffffff); +- nv_wr32(object, 0x1100, 0x10000); /* PBUS */ +- +- return _nouveau_therm_fini(object, suspend); +-} +- +-struct nouveau_oclass +-nv84_therm_oclass = { +- .handle = NV_SUBDEV(THERM, 0x84), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv84_therm_ctor, +- .dtor = _nouveau_therm_dtor, +- .init = nv84_therm_init, +- .fini = nv84_therm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c +deleted file mode 100644 +index 7893357a..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nva3.c ++++ /dev/null +@@ -1,101 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "priv.h" +- +-struct nva3_therm_priv { +- struct nouveau_therm_priv base; +-}; +- +-int +-nva3_therm_fan_sense(struct nouveau_therm *therm) +-{ +- u32 tach = nv_rd32(therm, 0x00e728) & 0x0000ffff; +- u32 ctrl = nv_rd32(therm, 0x00e720); +- if (ctrl & 0x00000001) +- return tach * 60 / 2; +- return -ENODEV; +-} +- +-static int +-nva3_therm_init(struct nouveau_object *object) +-{ +- struct nva3_therm_priv *priv = (void *)object; +- struct dcb_gpio_func *tach = &priv->base.fan->tach; +- int ret; +- +- ret = nouveau_therm_init(&priv->base.base); +- if (ret) +- return ret; +- +- nv84_sensor_setup(&priv->base.base); +- +- /* enable fan tach, count revolutions per-second */ +- nv_mask(priv, 0x00e720, 0x00000003, 0x00000002); +- if (tach->func != DCB_GPIO_UNUSED) { +- nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000); +- nv_mask(priv, 0x00e720, 0x001f0000, tach->line << 16); +- nv_mask(priv, 0x00e720, 0x00000001, 0x00000001); +- } +- nv_mask(priv, 0x00e720, 0x00000002, 0x00000000); +- +- return 0; +-} +- +-static int +-nva3_therm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nva3_therm_priv *priv; +- int ret; +- +- ret = nouveau_therm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl; +- priv->base.base.pwm_get = nv50_fan_pwm_get; +- priv->base.base.pwm_set = nv50_fan_pwm_set; +- priv->base.base.pwm_clock = nv50_fan_pwm_clock; +- priv->base.base.temp_get = nv84_temp_get; +- priv->base.base.fan_sense = nva3_therm_fan_sense; +- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; +- return nouveau_therm_preinit(&priv->base.base); +-} +- +-struct nouveau_oclass +-nva3_therm_oclass = { +- .handle = NV_SUBDEV(THERM, 0xa3), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nva3_therm_ctor, +- .dtor = _nouveau_therm_dtor, +- .init = nva3_therm_init, +- .fini = nv84_therm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c b/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c +deleted file mode 100644 +index b70f7cc6..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/nvd0.c ++++ /dev/null +@@ -1,174 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "priv.h" +- +-struct nvd0_therm_priv { +- struct nouveau_therm_priv base; +-}; +- +-static int +-pwm_info(struct nouveau_therm *therm, int line) +-{ +- u32 gpio = nv_rd32(therm, 0x00d610 + (line * 0x04)); +- +- switch (gpio & 0x000000c0) { +- case 0x00000000: /* normal mode, possibly pwm forced off by us */ +- case 0x00000040: /* nvio special */ +- switch (gpio & 0x0000001f) { +- case 0x00: return 2; +- case 0x19: return 1; +- case 0x1c: return 0; +- case 0x1e: return 2; +- default: +- break; +- } +- default: +- break; +- } +- +- nv_error(therm, "GPIO %d unknown PWM: 0x%08x\n", line, gpio); +- return -ENODEV; +-} +- +-static int +-nvd0_fan_pwm_ctrl(struct nouveau_therm *therm, int line, bool enable) +-{ +- u32 data = enable ? 0x00000040 : 0x00000000; +- int indx = pwm_info(therm, line); +- if (indx < 0) +- return indx; +- else if (indx < 2) +- nv_mask(therm, 0x00d610 + (line * 0x04), 0x000000c0, data); +- /* nothing to do for indx == 2, it seems hardwired to PTHERM */ +- return 0; +-} +- +-static int +-nvd0_fan_pwm_get(struct nouveau_therm *therm, int line, u32 *divs, u32 *duty) +-{ +- int indx = pwm_info(therm, line); +- if (indx < 0) +- return indx; +- else if (indx < 2) { +- if (nv_rd32(therm, 0x00d610 + (line * 0x04)) & 0x00000040) { +- *divs = nv_rd32(therm, 0x00e114 + (indx * 8)); +- *duty = nv_rd32(therm, 0x00e118 + (indx * 8)); +- return 0; +- } +- } else if (indx == 2) { +- *divs = nv_rd32(therm, 0x0200d8) & 0x1fff; +- *duty = nv_rd32(therm, 0x0200dc) & 0x1fff; +- return 0; +- } +- +- return -EINVAL; +-} +- +-static int +-nvd0_fan_pwm_set(struct nouveau_therm *therm, int line, u32 divs, u32 duty) +-{ +- int indx = pwm_info(therm, line); +- if (indx < 0) +- return indx; +- else if (indx < 2) { +- nv_wr32(therm, 0x00e114 + (indx * 8), divs); +- nv_wr32(therm, 0x00e118 + (indx * 8), duty | 0x80000000); +- } else if (indx == 2) { +- nv_mask(therm, 0x0200d8, 0x1fff, divs); /* keep the high bits */ +- nv_wr32(therm, 0x0200dc, duty | 0x40000000); +- } +- return 0; +-} +- +-static int +-nvd0_fan_pwm_clock(struct nouveau_therm *therm, int line) +-{ +- int indx = pwm_info(therm, line); +- if (indx < 0) +- return 0; +- else if (indx < 2) +- return (nv_device(therm)->crystal * 1000) / 20; +- else +- return nv_device(therm)->crystal * 1000 / 10; +-} +- +-int +-nvd0_therm_init(struct nouveau_object *object) +-{ +- struct nvd0_therm_priv *priv = (void *)object; +- int ret; +- +- ret = nouveau_therm_init(&priv->base.base); +- if (ret) +- return ret; +- +- /* enable fan tach, count revolutions per-second */ +- nv_mask(priv, 0x00e720, 0x00000003, 0x00000002); +- if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) { +- nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line); +- nv_wr32(priv, 0x00e724, nv_device(priv)->crystal * 1000); +- nv_mask(priv, 0x00e720, 0x00000001, 0x00000001); +- } +- nv_mask(priv, 0x00e720, 0x00000002, 0x00000000); +- +- return 0; +-} +- +-static int +-nvd0_therm_ctor(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvd0_therm_priv *priv; +- int ret; +- +- ret = nouveau_therm_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- nv84_sensor_setup(&priv->base.base); +- +- priv->base.base.pwm_ctrl = nvd0_fan_pwm_ctrl; +- priv->base.base.pwm_get = nvd0_fan_pwm_get; +- priv->base.base.pwm_set = nvd0_fan_pwm_set; +- priv->base.base.pwm_clock = nvd0_fan_pwm_clock; +- priv->base.base.temp_get = nv84_temp_get; +- priv->base.base.fan_sense = nva3_therm_fan_sense; +- priv->base.sensor.program_alarms = nouveau_therm_program_alarms_polling; +- return nouveau_therm_preinit(&priv->base.base); +-} +- +-struct nouveau_oclass +-nvd0_therm_oclass = { +- .handle = NV_SUBDEV(THERM, 0xd0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvd0_therm_ctor, +- .dtor = _nouveau_therm_dtor, +- .init = nvd0_therm_init, +- .fini = nv84_therm_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h b/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h +deleted file mode 100644 +index 7dba8c28..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/priv.h ++++ /dev/null +@@ -1,159 +0,0 @@ +-#ifndef __NVTHERM_PRIV_H__ +-#define __NVTHERM_PRIV_H__ +- +-/* +- * Copyright 2012 The Nouveau community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include +- +-#include +-#include +-#include +-#include +-#include +- +-struct nouveau_fan { +- struct nouveau_therm *parent; +- const char *type; +- +- struct nvbios_therm_fan bios; +- struct nvbios_perf_fan perf; +- +- struct nouveau_alarm alarm; +- spinlock_t lock; +- int percent; +- +- int (*get)(struct nouveau_therm *therm); +- int (*set)(struct nouveau_therm *therm, int percent); +- +- struct dcb_gpio_func tach; +-}; +- +-enum nouveau_therm_thrs_direction { +- NOUVEAU_THERM_THRS_FALLING = 0, +- NOUVEAU_THERM_THRS_RISING = 1 +-}; +- +-enum nouveau_therm_thrs_state { +- NOUVEAU_THERM_THRS_LOWER = 0, +- NOUVEAU_THERM_THRS_HIGHER = 1 +-}; +- +-enum nouveau_therm_thrs { +- NOUVEAU_THERM_THRS_FANBOOST = 0, +- NOUVEAU_THERM_THRS_DOWNCLOCK = 1, +- NOUVEAU_THERM_THRS_CRITICAL = 2, +- NOUVEAU_THERM_THRS_SHUTDOWN = 3, +- NOUVEAU_THERM_THRS_NR +-}; +- +-struct nouveau_therm_priv { +- struct nouveau_therm base; +- +- /* automatic thermal management */ +- struct nouveau_alarm alarm; +- spinlock_t lock; +- struct nouveau_therm_trip_point *last_trip; +- int mode; +- int cstate; +- int suspend; +- +- /* bios */ +- struct nvbios_therm_sensor bios_sensor; +- +- /* fan priv */ +- struct nouveau_fan *fan; +- +- /* alarms priv */ +- struct { +- spinlock_t alarm_program_lock; +- struct nouveau_alarm therm_poll_alarm; +- enum nouveau_therm_thrs_state alarm_state[NOUVEAU_THERM_THRS_NR]; +- void (*program_alarms)(struct nouveau_therm *); +- } sensor; +- +- /* what should be done if the card overheats */ +- struct { +- void (*downclock)(struct nouveau_therm *, bool active); +- void (*pause)(struct nouveau_therm *, bool active); +- } emergency; +- +- /* ic */ +- struct i2c_client *ic; +-}; +- +-int nouveau_therm_fan_mode(struct nouveau_therm *therm, int mode); +-int nouveau_therm_attr_get(struct nouveau_therm *therm, +- enum nouveau_therm_attr_type type); +-int nouveau_therm_attr_set(struct nouveau_therm *therm, +- enum nouveau_therm_attr_type type, int value); +- +-void nouveau_therm_ic_ctor(struct nouveau_therm *therm); +- +-int nouveau_therm_sensor_ctor(struct nouveau_therm *therm); +- +-int nouveau_therm_fan_ctor(struct nouveau_therm *therm); +-int nouveau_therm_fan_init(struct nouveau_therm *therm); +-int nouveau_therm_fan_fini(struct nouveau_therm *therm, bool suspend); +-int nouveau_therm_fan_get(struct nouveau_therm *therm); +-int nouveau_therm_fan_set(struct nouveau_therm *therm, bool now, int percent); +-int nouveau_therm_fan_user_get(struct nouveau_therm *therm); +-int nouveau_therm_fan_user_set(struct nouveau_therm *therm, int percent); +- +-int nouveau_therm_fan_sense(struct nouveau_therm *therm); +- +-int nouveau_therm_preinit(struct nouveau_therm *); +- +-int nouveau_therm_sensor_init(struct nouveau_therm *therm); +-int nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend); +-void nouveau_therm_sensor_preinit(struct nouveau_therm *); +-void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm, +- enum nouveau_therm_thrs thrs, +- enum nouveau_therm_thrs_state st); +-enum nouveau_therm_thrs_state +-nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm, +- enum nouveau_therm_thrs thrs); +-void nouveau_therm_sensor_event(struct nouveau_therm *therm, +- enum nouveau_therm_thrs thrs, +- enum nouveau_therm_thrs_direction dir); +-void nouveau_therm_program_alarms_polling(struct nouveau_therm *therm); +- +-void nv40_therm_intr(struct nouveau_subdev *); +-int nv50_fan_pwm_ctrl(struct nouveau_therm *, int, bool); +-int nv50_fan_pwm_get(struct nouveau_therm *, int, u32 *, u32 *); +-int nv50_fan_pwm_set(struct nouveau_therm *, int, u32, u32); +-int nv50_fan_pwm_clock(struct nouveau_therm *, int); +-int nv84_temp_get(struct nouveau_therm *therm); +-void nv84_sensor_setup(struct nouveau_therm *therm); +-int nv84_therm_fini(struct nouveau_object *object, bool suspend); +- +-int nva3_therm_fan_sense(struct nouveau_therm *); +- +-int nvd0_therm_init(struct nouveau_object *object); +- +-int nouveau_fanpwm_create(struct nouveau_therm *, struct dcb_gpio_func *); +-int nouveau_fantog_create(struct nouveau_therm *, struct dcb_gpio_func *); +-int nouveau_fannil_create(struct nouveau_therm *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c b/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c +deleted file mode 100644 +index 6212537b..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/therm/temp.c ++++ /dev/null +@@ -1,264 +0,0 @@ +-/* +- * Copyright 2012 The Nouveau community +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Martin Peres +- */ +- +-#include "priv.h" +- +-#include +-#include +- +-#include +- +-static void +-nouveau_therm_temp_set_defaults(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- +- priv->bios_sensor.offset_constant = 0; +- +- priv->bios_sensor.thrs_fan_boost.temp = 90; +- priv->bios_sensor.thrs_fan_boost.hysteresis = 3; +- +- priv->bios_sensor.thrs_down_clock.temp = 95; +- priv->bios_sensor.thrs_down_clock.hysteresis = 3; +- +- priv->bios_sensor.thrs_critical.temp = 105; +- priv->bios_sensor.thrs_critical.hysteresis = 5; +- +- priv->bios_sensor.thrs_shutdown.temp = 135; +- priv->bios_sensor.thrs_shutdown.hysteresis = 5; /*not that it matters */ +-} +- +- +-static void +-nouveau_therm_temp_safety_checks(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nvbios_therm_sensor *s = &priv->bios_sensor; +- +- /* enforce a minimum hysteresis on thresholds */ +- s->thrs_fan_boost.hysteresis = max_t(u8, s->thrs_fan_boost.hysteresis, 2); +- s->thrs_down_clock.hysteresis = max_t(u8, s->thrs_down_clock.hysteresis, 2); +- s->thrs_critical.hysteresis = max_t(u8, s->thrs_critical.hysteresis, 2); +- s->thrs_shutdown.hysteresis = max_t(u8, s->thrs_shutdown.hysteresis, 2); +-} +- +-/* must be called with alarm_program_lock taken ! */ +-void nouveau_therm_sensor_set_threshold_state(struct nouveau_therm *therm, +- enum nouveau_therm_thrs thrs, +- enum nouveau_therm_thrs_state st) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- priv->sensor.alarm_state[thrs] = st; +-} +- +-/* must be called with alarm_program_lock taken ! */ +-enum nouveau_therm_thrs_state +-nouveau_therm_sensor_get_threshold_state(struct nouveau_therm *therm, +- enum nouveau_therm_thrs thrs) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- return priv->sensor.alarm_state[thrs]; +-} +- +-static void +-nv_poweroff_work(struct work_struct *work) +-{ +- orderly_poweroff(true); +- kfree(work); +-} +- +-void nouveau_therm_sensor_event(struct nouveau_therm *therm, +- enum nouveau_therm_thrs thrs, +- enum nouveau_therm_thrs_direction dir) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- bool active; +- const char *thresolds[] = { +- "fanboost", "downclock", "critical", "shutdown" +- }; +- int temperature = therm->temp_get(therm); +- +- if (thrs < 0 || thrs > 3) +- return; +- +- if (dir == NOUVEAU_THERM_THRS_FALLING) +- nv_info(therm, "temperature (%i C) went below the '%s' threshold\n", +- temperature, thresolds[thrs]); +- else +- nv_info(therm, "temperature (%i C) hit the '%s' threshold\n", +- temperature, thresolds[thrs]); +- +- active = (dir == NOUVEAU_THERM_THRS_RISING); +- switch (thrs) { +- case NOUVEAU_THERM_THRS_FANBOOST: +- if (active) { +- nouveau_therm_fan_set(therm, true, 100); +- nouveau_therm_fan_mode(therm, NOUVEAU_THERM_CTRL_AUTO); +- } +- break; +- case NOUVEAU_THERM_THRS_DOWNCLOCK: +- if (priv->emergency.downclock) +- priv->emergency.downclock(therm, active); +- break; +- case NOUVEAU_THERM_THRS_CRITICAL: +- if (priv->emergency.pause) +- priv->emergency.pause(therm, active); +- break; +- case NOUVEAU_THERM_THRS_SHUTDOWN: +- if (active) { +- struct work_struct *work; +- +- work = kmalloc(sizeof(*work), GFP_ATOMIC); +- if (work) { +- INIT_WORK(work, nv_poweroff_work); +- schedule_work(work); +- } +- } +- break; +- case NOUVEAU_THERM_THRS_NR: +- break; +- } +- +-} +- +-/* must be called with alarm_program_lock taken ! */ +-static void +-nouveau_therm_threshold_hyst_polling(struct nouveau_therm *therm, +- const struct nvbios_therm_threshold *thrs, +- enum nouveau_therm_thrs thrs_name) +-{ +- enum nouveau_therm_thrs_direction direction; +- enum nouveau_therm_thrs_state prev_state, new_state; +- int temp = therm->temp_get(therm); +- +- prev_state = nouveau_therm_sensor_get_threshold_state(therm, thrs_name); +- +- if (temp >= thrs->temp && prev_state == NOUVEAU_THERM_THRS_LOWER) { +- direction = NOUVEAU_THERM_THRS_RISING; +- new_state = NOUVEAU_THERM_THRS_HIGHER; +- } else if (temp <= thrs->temp - thrs->hysteresis && +- prev_state == NOUVEAU_THERM_THRS_HIGHER) { +- direction = NOUVEAU_THERM_THRS_FALLING; +- new_state = NOUVEAU_THERM_THRS_LOWER; +- } else +- return; /* nothing to do */ +- +- nouveau_therm_sensor_set_threshold_state(therm, thrs_name, new_state); +- nouveau_therm_sensor_event(therm, thrs_name, direction); +-} +- +-static void +-alarm_timer_callback(struct nouveau_alarm *alarm) +-{ +- struct nouveau_therm_priv *priv = +- container_of(alarm, struct nouveau_therm_priv, sensor.therm_poll_alarm); +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- struct nouveau_timer *ptimer = nouveau_timer(priv); +- struct nouveau_therm *therm = &priv->base; +- unsigned long flags; +- +- spin_lock_irqsave(&priv->sensor.alarm_program_lock, flags); +- +- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_fan_boost, +- NOUVEAU_THERM_THRS_FANBOOST); +- +- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_down_clock, +- NOUVEAU_THERM_THRS_DOWNCLOCK); +- +- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_critical, +- NOUVEAU_THERM_THRS_CRITICAL); +- +- nouveau_therm_threshold_hyst_polling(therm, &sensor->thrs_shutdown, +- NOUVEAU_THERM_THRS_SHUTDOWN); +- +- spin_unlock_irqrestore(&priv->sensor.alarm_program_lock, flags); +- +- /* schedule the next poll in one second */ +- if (therm->temp_get(therm) >= 0 && list_empty(&alarm->head)) +- ptimer->alarm(ptimer, 1000000000ULL, alarm); +-} +- +-void +-nouveau_therm_program_alarms_polling(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nvbios_therm_sensor *sensor = &priv->bios_sensor; +- +- nv_debug(therm, +- "programmed thresholds [ %d(%d), %d(%d), %d(%d), %d(%d) ]\n", +- sensor->thrs_fan_boost.temp, sensor->thrs_fan_boost.hysteresis, +- sensor->thrs_down_clock.temp, +- sensor->thrs_down_clock.hysteresis, +- sensor->thrs_critical.temp, sensor->thrs_critical.hysteresis, +- sensor->thrs_shutdown.temp, sensor->thrs_shutdown.hysteresis); +- +- alarm_timer_callback(&priv->sensor.therm_poll_alarm); +-} +- +-int +-nouveau_therm_sensor_init(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- priv->sensor.program_alarms(therm); +- return 0; +-} +- +-int +-nouveau_therm_sensor_fini(struct nouveau_therm *therm, bool suspend) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_timer *ptimer = nouveau_timer(therm); +- +- if (suspend) +- ptimer->alarm_cancel(ptimer, &priv->sensor.therm_poll_alarm); +- return 0; +-} +- +-void +-nouveau_therm_sensor_preinit(struct nouveau_therm *therm) +-{ +- const char *sensor_avail = "yes"; +- +- if (therm->temp_get(therm) < 0) +- sensor_avail = "no"; +- +- nv_info(therm, "internal sensor: %s\n", sensor_avail); +-} +- +-int +-nouveau_therm_sensor_ctor(struct nouveau_therm *therm) +-{ +- struct nouveau_therm_priv *priv = (void *)therm; +- struct nouveau_bios *bios = nouveau_bios(therm); +- +- nouveau_alarm_init(&priv->sensor.therm_poll_alarm, alarm_timer_callback); +- +- nouveau_therm_temp_set_defaults(therm); +- if (nvbios_therm_sensor_parse(bios, NVBIOS_THERM_DOMAIN_CORE, +- &priv->bios_sensor)) +- nv_error(therm, "nvbios_therm_sensor_parse failed\n"); +- nouveau_therm_temp_safety_checks(therm); +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c b/drivers/gpu/drm/nouveau/core/subdev/timer/base.c +deleted file mode 100644 +index cf8a0e0f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/timer/base.c ++++ /dev/null +@@ -1,94 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "subdev/timer.h" +- +-bool +-nouveau_timer_wait_eq(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(obj); +- u64 time0; +- +- time0 = ptimer->read(ptimer); +- do { +- if (nv_iclass(obj, NV_SUBDEV_CLASS)) { +- if ((nv_rd32(obj, addr) & mask) == data) +- return true; +- } else { +- if ((nv_ro32(obj, addr) & mask) == data) +- return true; +- } +- } while (ptimer->read(ptimer) - time0 < nsec); +- +- return false; +-} +- +-bool +-nouveau_timer_wait_ne(void *obj, u64 nsec, u32 addr, u32 mask, u32 data) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(obj); +- u64 time0; +- +- time0 = ptimer->read(ptimer); +- do { +- if (nv_iclass(obj, NV_SUBDEV_CLASS)) { +- if ((nv_rd32(obj, addr) & mask) != data) +- return true; +- } else { +- if ((nv_ro32(obj, addr) & mask) != data) +- return true; +- } +- } while (ptimer->read(ptimer) - time0 < nsec); +- +- return false; +-} +- +-bool +-nouveau_timer_wait_cb(void *obj, u64 nsec, bool (*func)(void *), void *data) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(obj); +- u64 time0; +- +- time0 = ptimer->read(ptimer); +- do { +- if (func(data) == true) +- return true; +- } while (ptimer->read(ptimer) - time0 < nsec); +- +- return false; +-} +- +-void +-nouveau_timer_alarm(void *obj, u32 nsec, struct nouveau_alarm *alarm) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(obj); +- ptimer->alarm(ptimer, nsec, alarm); +-} +- +-void +-nouveau_timer_alarm_cancel(void *obj, struct nouveau_alarm *alarm) +-{ +- struct nouveau_timer *ptimer = nouveau_timer(obj); +- ptimer->alarm_cancel(ptimer, alarm); +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c b/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c +deleted file mode 100644 +index 37484db1..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/timer/gk20a.c ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-static int +-gk20a_timer_init(struct nouveau_object *object) +-{ +- struct nv04_timer_priv *priv = (void *)object; +- u32 hi = upper_32_bits(priv->suspend_time); +- u32 lo = lower_32_bits(priv->suspend_time); +- int ret; +- +- ret = nouveau_timer_init(&priv->base); +- if (ret) +- return ret; +- +- nv_debug(priv, "time low : 0x%08x\n", lo); +- nv_debug(priv, "time high : 0x%08x\n", hi); +- +- /* restore the time before suspend */ +- nv_wr32(priv, NV04_PTIMER_TIME_1, hi); +- nv_wr32(priv, NV04_PTIMER_TIME_0, lo); +- return 0; +-} +- +-struct nouveau_oclass +-gk20a_timer_oclass = { +- .handle = NV_SUBDEV(TIMER, 0xff), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_timer_ctor, +- .dtor = nv04_timer_dtor, +- .init = gk20a_timer_init, +- .fini = nv04_timer_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c +deleted file mode 100644 +index 240ed0b9..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.c ++++ /dev/null +@@ -1,264 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nv04.h" +- +-static u64 +-nv04_timer_read(struct nouveau_timer *ptimer) +-{ +- struct nv04_timer_priv *priv = (void *)ptimer; +- u32 hi, lo; +- +- do { +- hi = nv_rd32(priv, NV04_PTIMER_TIME_1); +- lo = nv_rd32(priv, NV04_PTIMER_TIME_0); +- } while (hi != nv_rd32(priv, NV04_PTIMER_TIME_1)); +- +- return ((u64)hi << 32 | lo); +-} +- +-static void +-nv04_timer_alarm_trigger(struct nouveau_timer *ptimer) +-{ +- struct nv04_timer_priv *priv = (void *)ptimer; +- struct nouveau_alarm *alarm, *atemp; +- unsigned long flags; +- LIST_HEAD(exec); +- +- /* move any due alarms off the pending list */ +- spin_lock_irqsave(&priv->lock, flags); +- list_for_each_entry_safe(alarm, atemp, &priv->alarms, head) { +- if (alarm->timestamp <= ptimer->read(ptimer)) +- list_move_tail(&alarm->head, &exec); +- } +- +- /* reschedule interrupt for next alarm time */ +- if (!list_empty(&priv->alarms)) { +- alarm = list_first_entry(&priv->alarms, typeof(*alarm), head); +- nv_wr32(priv, NV04_PTIMER_ALARM_0, alarm->timestamp); +- nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000001); +- } else { +- nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); +- } +- spin_unlock_irqrestore(&priv->lock, flags); +- +- /* execute any pending alarm handlers */ +- list_for_each_entry_safe(alarm, atemp, &exec, head) { +- list_del_init(&alarm->head); +- alarm->func(alarm); +- } +-} +- +-static void +-nv04_timer_alarm(struct nouveau_timer *ptimer, u64 time, +- struct nouveau_alarm *alarm) +-{ +- struct nv04_timer_priv *priv = (void *)ptimer; +- struct nouveau_alarm *list; +- unsigned long flags; +- +- alarm->timestamp = ptimer->read(ptimer) + time; +- +- /* append new alarm to list, in soonest-alarm-first order */ +- spin_lock_irqsave(&priv->lock, flags); +- if (!time) { +- if (!list_empty(&alarm->head)) +- list_del(&alarm->head); +- } else { +- list_for_each_entry(list, &priv->alarms, head) { +- if (list->timestamp > alarm->timestamp) +- break; +- } +- list_add_tail(&alarm->head, &list->head); +- } +- spin_unlock_irqrestore(&priv->lock, flags); +- +- /* process pending alarms */ +- nv04_timer_alarm_trigger(ptimer); +-} +- +-static void +-nv04_timer_alarm_cancel(struct nouveau_timer *ptimer, +- struct nouveau_alarm *alarm) +-{ +- struct nv04_timer_priv *priv = (void *)ptimer; +- unsigned long flags; +- spin_lock_irqsave(&priv->lock, flags); +- list_del_init(&alarm->head); +- spin_unlock_irqrestore(&priv->lock, flags); +-} +- +-static void +-nv04_timer_intr(struct nouveau_subdev *subdev) +-{ +- struct nv04_timer_priv *priv = (void *)subdev; +- u32 stat = nv_rd32(priv, NV04_PTIMER_INTR_0); +- +- if (stat & 0x00000001) { +- nv04_timer_alarm_trigger(&priv->base); +- nv_wr32(priv, NV04_PTIMER_INTR_0, 0x00000001); +- stat &= ~0x00000001; +- } +- +- if (stat) { +- nv_error(priv, "unknown stat 0x%08x\n", stat); +- nv_wr32(priv, NV04_PTIMER_INTR_0, stat); +- } +-} +- +-int +-nv04_timer_fini(struct nouveau_object *object, bool suspend) +-{ +- struct nv04_timer_priv *priv = (void *)object; +- if (suspend) +- priv->suspend_time = nv04_timer_read(&priv->base); +- nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); +- return nouveau_timer_fini(&priv->base, suspend); +-} +- +-static int +-nv04_timer_init(struct nouveau_object *object) +-{ +- struct nouveau_device *device = nv_device(object); +- struct nv04_timer_priv *priv = (void *)object; +- u32 m = 1, f, n, d, lo, hi; +- int ret; +- +- ret = nouveau_timer_init(&priv->base); +- if (ret) +- return ret; +- +- /* aim for 31.25MHz, which gives us nanosecond timestamps */ +- d = 1000000 / 32; +- +- /* determine base clock for timer source */ +-#if 0 /*XXX*/ +- if (device->chipset < 0x40) { +- n = nouveau_hw_get_clock(device, PLL_CORE); +- } else +-#endif +- if (device->chipset <= 0x40) { +- /*XXX: figure this out */ +- f = -1; +- n = 0; +- } else { +- f = device->crystal; +- n = f; +- while (n < (d * 2)) { +- n += (n / m); +- m++; +- } +- +- nv_wr32(priv, 0x009220, m - 1); +- } +- +- if (!n) { +- nv_warn(priv, "unknown input clock freq\n"); +- if (!nv_rd32(priv, NV04_PTIMER_NUMERATOR) || +- !nv_rd32(priv, NV04_PTIMER_DENOMINATOR)) { +- nv_wr32(priv, NV04_PTIMER_NUMERATOR, 1); +- nv_wr32(priv, NV04_PTIMER_DENOMINATOR, 1); +- } +- return 0; +- } +- +- /* reduce ratio to acceptable values */ +- while (((n % 5) == 0) && ((d % 5) == 0)) { +- n /= 5; +- d /= 5; +- } +- +- while (((n % 2) == 0) && ((d % 2) == 0)) { +- n /= 2; +- d /= 2; +- } +- +- while (n > 0xffff || d > 0xffff) { +- n >>= 1; +- d >>= 1; +- } +- +- /* restore the time before suspend */ +- lo = priv->suspend_time; +- hi = (priv->suspend_time >> 32); +- +- nv_debug(priv, "input frequency : %dHz\n", f); +- nv_debug(priv, "input multiplier: %d\n", m); +- nv_debug(priv, "numerator : 0x%08x\n", n); +- nv_debug(priv, "denominator : 0x%08x\n", d); +- nv_debug(priv, "timer frequency : %dHz\n", (f * m) * d / n); +- nv_debug(priv, "time low : 0x%08x\n", lo); +- nv_debug(priv, "time high : 0x%08x\n", hi); +- +- nv_wr32(priv, NV04_PTIMER_NUMERATOR, n); +- nv_wr32(priv, NV04_PTIMER_DENOMINATOR, d); +- nv_wr32(priv, NV04_PTIMER_INTR_0, 0xffffffff); +- nv_wr32(priv, NV04_PTIMER_INTR_EN_0, 0x00000000); +- nv_wr32(priv, NV04_PTIMER_TIME_1, hi); +- nv_wr32(priv, NV04_PTIMER_TIME_0, lo); +- +- return 0; +-} +- +-void +-nv04_timer_dtor(struct nouveau_object *object) +-{ +- struct nv04_timer_priv *priv = (void *)object; +- return nouveau_timer_destroy(&priv->base); +-} +- +-int +-nv04_timer_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_timer_priv *priv; +- int ret; +- +- ret = nouveau_timer_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.base.intr = nv04_timer_intr; +- priv->base.read = nv04_timer_read; +- priv->base.alarm = nv04_timer_alarm; +- priv->base.alarm_cancel = nv04_timer_alarm_cancel; +- priv->suspend_time = 0; +- +- INIT_LIST_HEAD(&priv->alarms); +- spin_lock_init(&priv->lock); +- return 0; +-} +- +-struct nouveau_oclass +-nv04_timer_oclass = { +- .handle = NV_SUBDEV(TIMER, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_timer_ctor, +- .dtor = nv04_timer_dtor, +- .init = nv04_timer_init, +- .fini = nv04_timer_fini, +- } +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h +deleted file mode 100644 +index 4bc15269..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/timer/nv04.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-#ifndef __NVKM_TIMER_NV04_H__ +-#define __NVKM_TIMER_NV04_H__ +- +-#include "priv.h" +- +-#define NV04_PTIMER_INTR_0 0x009100 +-#define NV04_PTIMER_INTR_EN_0 0x009140 +-#define NV04_PTIMER_NUMERATOR 0x009200 +-#define NV04_PTIMER_DENOMINATOR 0x009210 +-#define NV04_PTIMER_TIME_0 0x009400 +-#define NV04_PTIMER_TIME_1 0x009410 +-#define NV04_PTIMER_ALARM_0 0x009420 +- +-struct nv04_timer_priv { +- struct nouveau_timer base; +- struct list_head alarms; +- spinlock_t lock; +- u64 suspend_time; +-}; +- +-int nv04_timer_ctor(struct nouveau_object *, struct nouveau_object *, +- struct nouveau_oclass *, void *, u32, +- struct nouveau_object **); +-void nv04_timer_dtor(struct nouveau_object *); +-int nv04_timer_fini(struct nouveau_object *, bool); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h b/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h +deleted file mode 100644 +index 799dae3f..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/timer/priv.h ++++ /dev/null +@@ -1,6 +0,0 @@ +-#ifndef __NVKM_TIMER_PRIV_H__ +-#define __NVKM_TIMER_PRIV_H__ +- +-#include +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c b/drivers/gpu/drm/nouveau/core/subdev/vm/base.c +deleted file mode 100644 +index f75a683b..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/base.c ++++ /dev/null +@@ -1,483 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +- +-void +-nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) +-{ +- struct nouveau_vm *vm = vma->vm; +- struct nouveau_vmmgr *vmm = vm->vmm; +- struct nouveau_mm_node *r; +- int big = vma->node->type != vmm->spg_shift; +- u32 offset = vma->node->offset + (delta >> 12); +- u32 bits = vma->node->type - 12; +- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; +- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; +- u32 max = 1 << (vmm->pgt_bits - bits); +- u32 end, len; +- +- delta = 0; +- list_for_each_entry(r, &node->regions, rl_entry) { +- u64 phys = (u64)r->offset << 12; +- u32 num = r->length >> bits; +- +- while (num) { +- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; +- +- end = (pte + num); +- if (unlikely(end >= max)) +- end = max; +- len = end - pte; +- +- vmm->map(vma, pgt, node, pte, len, phys, delta); +- +- num -= len; +- pte += len; +- if (unlikely(end >= max)) { +- phys += len << (bits + 12); +- pde++; +- pte = 0; +- } +- +- delta += (u64)len << vma->node->type; +- } +- } +- +- vmm->flush(vm); +-} +- +-static void +-nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, +- struct nouveau_mem *mem) +-{ +- struct nouveau_vm *vm = vma->vm; +- struct nouveau_vmmgr *vmm = vm->vmm; +- int big = vma->node->type != vmm->spg_shift; +- u32 offset = vma->node->offset + (delta >> 12); +- u32 bits = vma->node->type - 12; +- u32 num = length >> vma->node->type; +- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; +- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; +- u32 max = 1 << (vmm->pgt_bits - bits); +- unsigned m, sglen; +- u32 end, len; +- int i; +- struct scatterlist *sg; +- +- for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { +- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; +- sglen = sg_dma_len(sg) >> PAGE_SHIFT; +- +- end = pte + sglen; +- if (unlikely(end >= max)) +- end = max; +- len = end - pte; +- +- for (m = 0; m < len; m++) { +- dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); +- +- vmm->map_sg(vma, pgt, mem, pte, 1, &addr); +- num--; +- pte++; +- +- if (num == 0) +- goto finish; +- } +- if (unlikely(end >= max)) { +- pde++; +- pte = 0; +- } +- if (m < sglen) { +- for (; m < sglen; m++) { +- dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); +- +- vmm->map_sg(vma, pgt, mem, pte, 1, &addr); +- num--; +- pte++; +- if (num == 0) +- goto finish; +- } +- } +- +- } +-finish: +- vmm->flush(vm); +-} +- +-static void +-nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, +- struct nouveau_mem *mem) +-{ +- struct nouveau_vm *vm = vma->vm; +- struct nouveau_vmmgr *vmm = vm->vmm; +- dma_addr_t *list = mem->pages; +- int big = vma->node->type != vmm->spg_shift; +- u32 offset = vma->node->offset + (delta >> 12); +- u32 bits = vma->node->type - 12; +- u32 num = length >> vma->node->type; +- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; +- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; +- u32 max = 1 << (vmm->pgt_bits - bits); +- u32 end, len; +- +- while (num) { +- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; +- +- end = (pte + num); +- if (unlikely(end >= max)) +- end = max; +- len = end - pte; +- +- vmm->map_sg(vma, pgt, mem, pte, len, list); +- +- num -= len; +- pte += len; +- list += len; +- if (unlikely(end >= max)) { +- pde++; +- pte = 0; +- } +- } +- +- vmm->flush(vm); +-} +- +-void +-nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) +-{ +- if (node->sg) +- nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); +- else +- if (node->pages) +- nouveau_vm_map_sg(vma, 0, node->size << 12, node); +- else +- nouveau_vm_map_at(vma, 0, node); +-} +- +-void +-nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) +-{ +- struct nouveau_vm *vm = vma->vm; +- struct nouveau_vmmgr *vmm = vm->vmm; +- int big = vma->node->type != vmm->spg_shift; +- u32 offset = vma->node->offset + (delta >> 12); +- u32 bits = vma->node->type - 12; +- u32 num = length >> vma->node->type; +- u32 pde = (offset >> vmm->pgt_bits) - vm->fpde; +- u32 pte = (offset & ((1 << vmm->pgt_bits) - 1)) >> bits; +- u32 max = 1 << (vmm->pgt_bits - bits); +- u32 end, len; +- +- while (num) { +- struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; +- +- end = (pte + num); +- if (unlikely(end >= max)) +- end = max; +- len = end - pte; +- +- vmm->unmap(pgt, pte, len); +- +- num -= len; +- pte += len; +- if (unlikely(end >= max)) { +- pde++; +- pte = 0; +- } +- } +- +- vmm->flush(vm); +-} +- +-void +-nouveau_vm_unmap(struct nouveau_vma *vma) +-{ +- nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); +-} +- +-static void +-nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) +-{ +- struct nouveau_vmmgr *vmm = vm->vmm; +- struct nouveau_vm_pgd *vpgd; +- struct nouveau_vm_pgt *vpgt; +- struct nouveau_gpuobj *pgt; +- u32 pde; +- +- for (pde = fpde; pde <= lpde; pde++) { +- vpgt = &vm->pgt[pde - vm->fpde]; +- if (--vpgt->refcount[big]) +- continue; +- +- pgt = vpgt->obj[big]; +- vpgt->obj[big] = NULL; +- +- list_for_each_entry(vpgd, &vm->pgd_list, head) { +- vmm->map_pgt(vpgd->obj, pde, vpgt->obj); +- } +- +- mutex_unlock(&nv_subdev(vmm)->mutex); +- nouveau_gpuobj_ref(NULL, &pgt); +- mutex_lock(&nv_subdev(vmm)->mutex); +- } +-} +- +-static int +-nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) +-{ +- struct nouveau_vmmgr *vmm = vm->vmm; +- struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; +- struct nouveau_vm_pgd *vpgd; +- struct nouveau_gpuobj *pgt; +- int big = (type != vmm->spg_shift); +- u32 pgt_size; +- int ret; +- +- pgt_size = (1 << (vmm->pgt_bits + 12)) >> type; +- pgt_size *= 8; +- +- mutex_unlock(&nv_subdev(vmm)->mutex); +- ret = nouveau_gpuobj_new(nv_object(vm->vmm), NULL, pgt_size, 0x1000, +- NVOBJ_FLAG_ZERO_ALLOC, &pgt); +- mutex_lock(&nv_subdev(vmm)->mutex); +- if (unlikely(ret)) +- return ret; +- +- /* someone beat us to filling the PDE while we didn't have the lock */ +- if (unlikely(vpgt->refcount[big]++)) { +- mutex_unlock(&nv_subdev(vmm)->mutex); +- nouveau_gpuobj_ref(NULL, &pgt); +- mutex_lock(&nv_subdev(vmm)->mutex); +- return 0; +- } +- +- vpgt->obj[big] = pgt; +- list_for_each_entry(vpgd, &vm->pgd_list, head) { +- vmm->map_pgt(vpgd->obj, pde, vpgt->obj); +- } +- +- return 0; +-} +- +-int +-nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, +- u32 access, struct nouveau_vma *vma) +-{ +- struct nouveau_vmmgr *vmm = vm->vmm; +- u32 align = (1 << page_shift) >> 12; +- u32 msize = size >> 12; +- u32 fpde, lpde, pde; +- int ret; +- +- mutex_lock(&nv_subdev(vmm)->mutex); +- ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, +- &vma->node); +- if (unlikely(ret != 0)) { +- mutex_unlock(&nv_subdev(vmm)->mutex); +- return ret; +- } +- +- fpde = (vma->node->offset >> vmm->pgt_bits); +- lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; +- +- for (pde = fpde; pde <= lpde; pde++) { +- struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; +- int big = (vma->node->type != vmm->spg_shift); +- +- if (likely(vpgt->refcount[big])) { +- vpgt->refcount[big]++; +- continue; +- } +- +- ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); +- if (ret) { +- if (pde != fpde) +- nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); +- nouveau_mm_free(&vm->mm, &vma->node); +- mutex_unlock(&nv_subdev(vmm)->mutex); +- return ret; +- } +- } +- mutex_unlock(&nv_subdev(vmm)->mutex); +- +- vma->vm = NULL; +- nouveau_vm_ref(vm, &vma->vm, NULL); +- vma->offset = (u64)vma->node->offset << 12; +- vma->access = access; +- return 0; +-} +- +-void +-nouveau_vm_put(struct nouveau_vma *vma) +-{ +- struct nouveau_vm *vm = vma->vm; +- struct nouveau_vmmgr *vmm = vm->vmm; +- u32 fpde, lpde; +- +- if (unlikely(vma->node == NULL)) +- return; +- fpde = (vma->node->offset >> vmm->pgt_bits); +- lpde = (vma->node->offset + vma->node->length - 1) >> vmm->pgt_bits; +- +- mutex_lock(&nv_subdev(vmm)->mutex); +- nouveau_vm_unmap_pgt(vm, vma->node->type != vmm->spg_shift, fpde, lpde); +- nouveau_mm_free(&vm->mm, &vma->node); +- mutex_unlock(&nv_subdev(vmm)->mutex); +- +- nouveau_vm_ref(NULL, &vma->vm, NULL); +-} +- +-int +-nouveau_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, +- u64 mm_offset, u32 block, struct nouveau_vm **pvm) +-{ +- struct nouveau_vm *vm; +- u64 mm_length = (offset + length) - mm_offset; +- int ret; +- +- vm = kzalloc(sizeof(*vm), GFP_KERNEL); +- if (!vm) +- return -ENOMEM; +- +- INIT_LIST_HEAD(&vm->pgd_list); +- vm->vmm = vmm; +- kref_init(&vm->refcount); +- vm->fpde = offset >> (vmm->pgt_bits + 12); +- vm->lpde = (offset + length - 1) >> (vmm->pgt_bits + 12); +- +- vm->pgt = vzalloc((vm->lpde - vm->fpde + 1) * sizeof(*vm->pgt)); +- if (!vm->pgt) { +- kfree(vm); +- return -ENOMEM; +- } +- +- ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, +- block >> 12); +- if (ret) { +- vfree(vm->pgt); +- kfree(vm); +- return ret; +- } +- +- *pvm = vm; +- +- return 0; +-} +- +-int +-nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, +- u64 mm_offset, struct nouveau_vm **pvm) +-{ +- struct nouveau_vmmgr *vmm = nouveau_vmmgr(device); +- return vmm->create(vmm, offset, length, mm_offset, pvm); +-} +- +-static int +-nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) +-{ +- struct nouveau_vmmgr *vmm = vm->vmm; +- struct nouveau_vm_pgd *vpgd; +- int i; +- +- if (!pgd) +- return 0; +- +- vpgd = kzalloc(sizeof(*vpgd), GFP_KERNEL); +- if (!vpgd) +- return -ENOMEM; +- +- nouveau_gpuobj_ref(pgd, &vpgd->obj); +- +- mutex_lock(&nv_subdev(vmm)->mutex); +- for (i = vm->fpde; i <= vm->lpde; i++) +- vmm->map_pgt(pgd, i, vm->pgt[i - vm->fpde].obj); +- list_add(&vpgd->head, &vm->pgd_list); +- mutex_unlock(&nv_subdev(vmm)->mutex); +- return 0; +-} +- +-static void +-nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) +-{ +- struct nouveau_vmmgr *vmm = vm->vmm; +- struct nouveau_vm_pgd *vpgd, *tmp; +- struct nouveau_gpuobj *pgd = NULL; +- +- if (!mpgd) +- return; +- +- mutex_lock(&nv_subdev(vmm)->mutex); +- list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { +- if (vpgd->obj == mpgd) { +- pgd = vpgd->obj; +- list_del(&vpgd->head); +- kfree(vpgd); +- break; +- } +- } +- mutex_unlock(&nv_subdev(vmm)->mutex); +- +- nouveau_gpuobj_ref(NULL, &pgd); +-} +- +-static void +-nouveau_vm_del(struct kref *kref) +-{ +- struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount); +- struct nouveau_vm_pgd *vpgd, *tmp; +- +- list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { +- nouveau_vm_unlink(vm, vpgd->obj); +- } +- +- nouveau_mm_fini(&vm->mm); +- vfree(vm->pgt); +- kfree(vm); +-} +- +-int +-nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, +- struct nouveau_gpuobj *pgd) +-{ +- if (ref) { +- int ret = nouveau_vm_link(ref, pgd); +- if (ret) +- return ret; +- +- kref_get(&ref->refcount); +- } +- +- if (*ptr) { +- nouveau_vm_unlink(*ptr, pgd); +- kref_put(&(*ptr)->refcount, nouveau_vm_del); +- } +- +- *ptr = ref; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c +deleted file mode 100644 +index ed454371..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.c ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include "nv04.h" +- +-#define NV04_PDMA_SIZE (128 * 1024 * 1024) +-#define NV04_PDMA_PAGE ( 4 * 1024) +- +-/******************************************************************************* +- * VM map/unmap callbacks +- ******************************************************************************/ +- +-static void +-nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +-{ +- pte = 0x00008 + (pte * 4); +- while (cnt) { +- u32 page = PAGE_SIZE / NV04_PDMA_PAGE; +- u32 phys = (u32)*list++; +- while (cnt && page--) { +- nv_wo32(pgt, pte, phys | 3); +- phys += NV04_PDMA_PAGE; +- pte += 4; +- cnt -= 1; +- } +- } +-} +- +-static void +-nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +-{ +- pte = 0x00008 + (pte * 4); +- while (cnt--) { +- nv_wo32(pgt, pte, 0x00000000); +- pte += 4; +- } +-} +- +-static void +-nv04_vm_flush(struct nouveau_vm *vm) +-{ +-} +- +-/******************************************************************************* +- * VM object +- ******************************************************************************/ +- +-int +-nv04_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, u64 mmstart, +- struct nouveau_vm **pvm) +-{ +- return -EINVAL; +-} +- +-/******************************************************************************* +- * VMMGR subdev +- ******************************************************************************/ +- +-static int +-nv04_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv04_vmmgr_priv *priv; +- struct nouveau_gpuobj *dma; +- int ret; +- +- ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIGART", +- "pcigart", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.create = nv04_vm_create; +- priv->base.limit = NV04_PDMA_SIZE; +- priv->base.dma_bits = 32; +- priv->base.pgt_bits = 32 - 12; +- priv->base.spg_shift = 12; +- priv->base.lpg_shift = 12; +- priv->base.map_sg = nv04_vm_map_sg; +- priv->base.unmap = nv04_vm_unmap; +- priv->base.flush = nv04_vm_flush; +- +- ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, +- &priv->vm); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, +- (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + +- 8, 16, NVOBJ_FLAG_ZERO_ALLOC, +- &priv->vm->pgt[0].obj[0]); +- dma = priv->vm->pgt[0].obj[0]; +- priv->vm->pgt[0].refcount[0] = 1; +- if (ret) +- return ret; +- +- nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */ +- nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1); +- return 0; +-} +- +-void +-nv04_vmmgr_dtor(struct nouveau_object *object) +-{ +- struct nv04_vmmgr_priv *priv = (void *)object; +- if (priv->vm) { +- nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); +- nouveau_vm_ref(NULL, &priv->vm, NULL); +- } +- if (priv->nullp) { +- pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, +- priv->nullp, priv->null); +- } +- nouveau_vmmgr_destroy(&priv->base); +-} +- +-struct nouveau_oclass +-nv04_vmmgr_oclass = { +- .handle = NV_SUBDEV(VM, 0x04), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv04_vmmgr_ctor, +- .dtor = nv04_vmmgr_dtor, +- .init = _nouveau_vmmgr_init, +- .fini = _nouveau_vmmgr_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h b/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h +deleted file mode 100644 +index ec42d4bc..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv04.h ++++ /dev/null +@@ -1,19 +0,0 @@ +-#ifndef __NV04_VMMGR_PRIV__ +-#define __NV04_VMMGR_PRIV__ +- +-#include +- +-struct nv04_vmmgr_priv { +- struct nouveau_vmmgr base; +- struct nouveau_vm *vm; +- dma_addr_t null; +- void *nullp; +-}; +- +-static inline struct nv04_vmmgr_priv * +-nv04_vmmgr(void *obj) +-{ +- return (void *)nouveau_vmmgr(obj); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c +deleted file mode 100644 +index 064c7626..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv41.c ++++ /dev/null +@@ -1,159 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +- +-#include "nv04.h" +- +-#define NV41_GART_SIZE (512 * 1024 * 1024) +-#define NV41_GART_PAGE ( 4 * 1024) +- +-/******************************************************************************* +- * VM map/unmap callbacks +- ******************************************************************************/ +- +-static void +-nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +-{ +- pte = pte * 4; +- while (cnt) { +- u32 page = PAGE_SIZE / NV41_GART_PAGE; +- u64 phys = (u64)*list++; +- while (cnt && page--) { +- nv_wo32(pgt, pte, (phys >> 7) | 1); +- phys += NV41_GART_PAGE; +- pte += 4; +- cnt -= 1; +- } +- } +-} +- +-static void +-nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +-{ +- pte = pte * 4; +- while (cnt--) { +- nv_wo32(pgt, pte, 0x00000000); +- pte += 4; +- } +-} +- +-static void +-nv41_vm_flush(struct nouveau_vm *vm) +-{ +- struct nv04_vmmgr_priv *priv = (void *)vm->vmm; +- +- mutex_lock(&nv_subdev(priv)->mutex); +- nv_wr32(priv, 0x100810, 0x00000022); +- if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) { +- nv_warn(priv, "flush timeout, 0x%08x\n", +- nv_rd32(priv, 0x100810)); +- } +- nv_wr32(priv, 0x100810, 0x00000000); +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-/******************************************************************************* +- * VMMGR subdev +- ******************************************************************************/ +- +-static int +-nv41_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nv04_vmmgr_priv *priv; +- int ret; +- +- if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || +- !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { +- return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, +- data, size, pobject); +- } +- +- ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", +- "pciegart", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.create = nv04_vm_create; +- priv->base.limit = NV41_GART_SIZE; +- priv->base.dma_bits = 39; +- priv->base.pgt_bits = 32 - 12; +- priv->base.spg_shift = 12; +- priv->base.lpg_shift = 12; +- priv->base.map_sg = nv41_vm_map_sg; +- priv->base.unmap = nv41_vm_unmap; +- priv->base.flush = nv41_vm_flush; +- +- ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, +- &priv->vm); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, +- (NV41_GART_SIZE / NV41_GART_PAGE) * 4, +- 16, NVOBJ_FLAG_ZERO_ALLOC, +- &priv->vm->pgt[0].obj[0]); +- priv->vm->pgt[0].refcount[0] = 1; +- if (ret) +- return ret; +- +- return 0; +-} +- +-static int +-nv41_vmmgr_init(struct nouveau_object *object) +-{ +- struct nv04_vmmgr_priv *priv = (void *)object; +- struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; +- int ret; +- +- ret = nouveau_vmmgr_init(&priv->base); +- if (ret) +- return ret; +- +- nv_wr32(priv, 0x100800, dma->addr | 0x00000002); +- nv_mask(priv, 0x10008c, 0x00000100, 0x00000100); +- nv_wr32(priv, 0x100820, 0x00000000); +- return 0; +-} +- +-struct nouveau_oclass +-nv41_vmmgr_oclass = { +- .handle = NV_SUBDEV(VM, 0x41), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv41_vmmgr_ctor, +- .dtor = nv04_vmmgr_dtor, +- .init = nv41_vmmgr_init, +- .fini = _nouveau_vmmgr_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c +deleted file mode 100644 +index fae1f67d..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv44.c ++++ /dev/null +@@ -1,249 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +- +-#include "nv04.h" +- +-#define NV44_GART_SIZE (512 * 1024 * 1024) +-#define NV44_GART_PAGE ( 4 * 1024) +- +-/******************************************************************************* +- * VM map/unmap callbacks +- ******************************************************************************/ +- +-static void +-nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, +- dma_addr_t *list, u32 pte, u32 cnt) +-{ +- u32 base = (pte << 2) & ~0x0000000f; +- u32 tmp[4]; +- +- tmp[0] = nv_ro32(pgt, base + 0x0); +- tmp[1] = nv_ro32(pgt, base + 0x4); +- tmp[2] = nv_ro32(pgt, base + 0x8); +- tmp[3] = nv_ro32(pgt, base + 0xc); +- +- while (cnt--) { +- u32 addr = list ? (*list++ >> 12) : (null >> 12); +- switch (pte++ & 0x3) { +- case 0: +- tmp[0] &= ~0x07ffffff; +- tmp[0] |= addr; +- break; +- case 1: +- tmp[0] &= ~0xf8000000; +- tmp[0] |= addr << 27; +- tmp[1] &= ~0x003fffff; +- tmp[1] |= addr >> 5; +- break; +- case 2: +- tmp[1] &= ~0xffc00000; +- tmp[1] |= addr << 22; +- tmp[2] &= ~0x0001ffff; +- tmp[2] |= addr >> 10; +- break; +- case 3: +- tmp[2] &= ~0xfffe0000; +- tmp[2] |= addr << 17; +- tmp[3] &= ~0x00000fff; +- tmp[3] |= addr >> 15; +- break; +- } +- } +- +- nv_wo32(pgt, base + 0x0, tmp[0]); +- nv_wo32(pgt, base + 0x4, tmp[1]); +- nv_wo32(pgt, base + 0x8, tmp[2]); +- nv_wo32(pgt, base + 0xc, tmp[3] | 0x40000000); +-} +- +-static void +-nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +-{ +- struct nv04_vmmgr_priv *priv = (void *)vma->vm->vmm; +- u32 tmp[4]; +- int i; +- +- if (pte & 3) { +- u32 max = 4 - (pte & 3); +- u32 part = (cnt > max) ? max : cnt; +- nv44_vm_fill(pgt, priv->null, list, pte, part); +- pte += part; +- list += part; +- cnt -= part; +- } +- +- while (cnt >= 4) { +- for (i = 0; i < 4; i++) +- tmp[i] = *list++ >> 12; +- nv_wo32(pgt, pte++ * 4, tmp[0] >> 0 | tmp[1] << 27); +- nv_wo32(pgt, pte++ * 4, tmp[1] >> 5 | tmp[2] << 22); +- nv_wo32(pgt, pte++ * 4, tmp[2] >> 10 | tmp[3] << 17); +- nv_wo32(pgt, pte++ * 4, tmp[3] >> 15 | 0x40000000); +- cnt -= 4; +- } +- +- if (cnt) +- nv44_vm_fill(pgt, priv->null, list, pte, cnt); +-} +- +-static void +-nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +-{ +- struct nv04_vmmgr_priv *priv = (void *)nouveau_vmmgr(pgt); +- +- if (pte & 3) { +- u32 max = 4 - (pte & 3); +- u32 part = (cnt > max) ? max : cnt; +- nv44_vm_fill(pgt, priv->null, NULL, pte, part); +- pte += part; +- cnt -= part; +- } +- +- while (cnt >= 4) { +- nv_wo32(pgt, pte++ * 4, 0x00000000); +- nv_wo32(pgt, pte++ * 4, 0x00000000); +- nv_wo32(pgt, pte++ * 4, 0x00000000); +- nv_wo32(pgt, pte++ * 4, 0x00000000); +- cnt -= 4; +- } +- +- if (cnt) +- nv44_vm_fill(pgt, priv->null, NULL, pte, cnt); +-} +- +-static void +-nv44_vm_flush(struct nouveau_vm *vm) +-{ +- struct nv04_vmmgr_priv *priv = (void *)vm->vmm; +- nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); +- nv_wr32(priv, 0x100808, 0x00000020); +- if (!nv_wait(priv, 0x100808, 0x00000001, 0x00000001)) +- nv_error(priv, "timeout: 0x%08x\n", nv_rd32(priv, 0x100808)); +- nv_wr32(priv, 0x100808, 0x00000000); +-} +- +-/******************************************************************************* +- * VMMGR subdev +- ******************************************************************************/ +- +-static int +-nv44_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nouveau_device *device = nv_device(parent); +- struct nv04_vmmgr_priv *priv; +- int ret; +- +- if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || +- !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { +- return nouveau_object_ctor(parent, engine, &nv04_vmmgr_oclass, +- data, size, pobject); +- } +- +- ret = nouveau_vmmgr_create(parent, engine, oclass, "PCIEGART", +- "pciegart", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.create = nv04_vm_create; +- priv->base.limit = NV44_GART_SIZE; +- priv->base.dma_bits = 39; +- priv->base.pgt_bits = 32 - 12; +- priv->base.spg_shift = 12; +- priv->base.lpg_shift = 12; +- priv->base.map_sg = nv44_vm_map_sg; +- priv->base.unmap = nv44_vm_unmap; +- priv->base.flush = nv44_vm_flush; +- +- priv->nullp = pci_alloc_consistent(device->pdev, 16 * 1024, &priv->null); +- if (!priv->nullp) { +- nv_error(priv, "unable to allocate dummy pages\n"); +- return -ENOMEM; +- } +- +- ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, +- &priv->vm); +- if (ret) +- return ret; +- +- ret = nouveau_gpuobj_new(nv_object(priv), NULL, +- (NV44_GART_SIZE / NV44_GART_PAGE) * 4, +- 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, +- &priv->vm->pgt[0].obj[0]); +- priv->vm->pgt[0].refcount[0] = 1; +- if (ret) +- return ret; +- +- return 0; +-} +- +-static int +-nv44_vmmgr_init(struct nouveau_object *object) +-{ +- struct nv04_vmmgr_priv *priv = (void *)object; +- struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; +- u32 addr; +- int ret; +- +- ret = nouveau_vmmgr_init(&priv->base); +- if (ret) +- return ret; +- +- /* calculate vram address of this PRAMIN block, object must be +- * allocated on 512KiB alignment, and not exceed a total size +- * of 512KiB for this to work correctly +- */ +- addr = nv_rd32(priv, 0x10020c); +- addr -= ((gart->addr >> 19) + 1) << 19; +- +- nv_wr32(priv, 0x100850, 0x80000000); +- nv_wr32(priv, 0x100818, priv->null); +- nv_wr32(priv, 0x100804, NV44_GART_SIZE); +- nv_wr32(priv, 0x100850, 0x00008000); +- nv_mask(priv, 0x10008c, 0x00000200, 0x00000200); +- nv_wr32(priv, 0x100820, 0x00000000); +- nv_wr32(priv, 0x10082c, 0x00000001); +- nv_wr32(priv, 0x100800, addr | 0x00000010); +- return 0; +-} +- +-struct nouveau_oclass +-nv44_vmmgr_oclass = { +- .handle = NV_SUBDEV(VM, 0x44), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv44_vmmgr_ctor, +- .dtor = nv04_vmmgr_dtor, +- .init = nv44_vmmgr_init, +- .fini = _nouveau_vmmgr_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c +deleted file mode 100644 +index a4aa81a2..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nv50.c ++++ /dev/null +@@ -1,240 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-struct nv50_vmmgr_priv { +- struct nouveau_vmmgr base; +-}; +- +-static void +-nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, +- struct nouveau_gpuobj *pgt[2]) +-{ +- u64 phys = 0xdeadcafe00000000ULL; +- u32 coverage = 0; +- +- if (pgt[0]) { +- phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ +- coverage = (pgt[0]->size >> 3) << 12; +- } else +- if (pgt[1]) { +- phys = 0x00000001 | pgt[1]->addr; /* present */ +- coverage = (pgt[1]->size >> 3) << 16; +- } +- +- if (phys & 1) { +- if (coverage <= 32 * 1024 * 1024) +- phys |= 0x60; +- else if (coverage <= 64 * 1024 * 1024) +- phys |= 0x40; +- else if (coverage <= 128 * 1024 * 1024) +- phys |= 0x20; +- } +- +- nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); +- nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); +-} +- +-static inline u64 +-vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +-{ +- phys |= 1; /* present */ +- phys |= (u64)memtype << 40; +- phys |= target << 4; +- if (vma->access & NV_MEM_ACCESS_SYS) +- phys |= (1 << 6); +- if (!(vma->access & NV_MEM_ACCESS_WO)) +- phys |= (1 << 3); +- return phys; +-} +- +-static void +-nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +-{ +- u32 comp = (mem->memtype & 0x180) >> 7; +- u32 block, target; +- int i; +- +- /* IGPs don't have real VRAM, re-target to stolen system memory */ +- target = 0; +- if (nouveau_fb(vma->vm->vmm)->ram->stolen) { +- phys += nouveau_fb(vma->vm->vmm)->ram->stolen; +- target = 3; +- } +- +- phys = vm_addr(vma, phys, mem->memtype, target); +- pte <<= 3; +- cnt <<= 3; +- +- while (cnt) { +- u32 offset_h = upper_32_bits(phys); +- u32 offset_l = lower_32_bits(phys); +- +- for (i = 7; i >= 0; i--) { +- block = 1 << (i + 3); +- if (cnt >= block && !(pte & (block - 1))) +- break; +- } +- offset_l |= (i << 7); +- +- phys += block << (vma->node->type - 3); +- cnt -= block; +- if (comp) { +- u32 tag = mem->tag->offset + ((delta >> 16) * comp); +- offset_h |= (tag << 17); +- delta += block << (vma->node->type - 3); +- } +- +- while (block) { +- nv_wo32(pgt, pte + 0, offset_l); +- nv_wo32(pgt, pte + 4, offset_h); +- pte += 8; +- block -= 8; +- } +- } +-} +- +-static void +-nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +-{ +- u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; +- pte <<= 3; +- while (cnt--) { +- u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); +- nv_wo32(pgt, pte + 0, lower_32_bits(phys)); +- nv_wo32(pgt, pte + 4, upper_32_bits(phys)); +- pte += 8; +- } +-} +- +-static void +-nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +-{ +- pte <<= 3; +- while (cnt--) { +- nv_wo32(pgt, pte + 0, 0x00000000); +- nv_wo32(pgt, pte + 4, 0x00000000); +- pte += 8; +- } +-} +- +-static void +-nv50_vm_flush(struct nouveau_vm *vm) +-{ +- struct nv50_vmmgr_priv *priv = (void *)vm->vmm; +- struct nouveau_bar *bar = nouveau_bar(priv); +- struct nouveau_engine *engine; +- int i, vme; +- +- bar->flush(bar); +- +- mutex_lock(&nv_subdev(priv)->mutex); +- for (i = 0; i < NVDEV_SUBDEV_NR; i++) { +- if (!atomic_read(&vm->engref[i])) +- continue; +- +- /* unfortunate hw bug workaround... */ +- engine = nouveau_engine(priv, i); +- if (engine && engine->tlb_flush) { +- engine->tlb_flush(engine); +- continue; +- } +- +- switch (i) { +- case NVDEV_ENGINE_GR : vme = 0x00; break; +- case NVDEV_ENGINE_VP : vme = 0x01; break; +- case NVDEV_SUBDEV_BAR : vme = 0x06; break; +- case NVDEV_ENGINE_PPP : +- case NVDEV_ENGINE_MPEG : vme = 0x08; break; +- case NVDEV_ENGINE_BSP : vme = 0x09; break; +- case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; +- case NVDEV_ENGINE_COPY0: vme = 0x0d; break; +- default: +- continue; +- } +- +- nv_wr32(priv, 0x100c80, (vme << 16) | 1); +- if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000)) +- nv_error(priv, "vm flush timeout: engine %d\n", vme); +- } +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-static int +-nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, +- u64 mm_offset, struct nouveau_vm **pvm) +-{ +- u32 block = (1 << (vmm->pgt_bits + 12)); +- if (block > length) +- block = length; +- +- return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm); +-} +- +-static int +-nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv50_vmmgr_priv *priv; +- int ret; +- +- ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.limit = 1ULL << 40; +- priv->base.dma_bits = 40; +- priv->base.pgt_bits = 29 - 12; +- priv->base.spg_shift = 12; +- priv->base.lpg_shift = 16; +- priv->base.create = nv50_vm_create; +- priv->base.map_pgt = nv50_vm_map_pgt; +- priv->base.map = nv50_vm_map; +- priv->base.map_sg = nv50_vm_map_sg; +- priv->base.unmap = nv50_vm_unmap; +- priv->base.flush = nv50_vm_flush; +- return 0; +-} +- +-struct nouveau_oclass +-nv50_vmmgr_oclass = { +- .handle = NV_SUBDEV(VM, 0x50), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv50_vmmgr_ctor, +- .dtor = _nouveau_vmmgr_dtor, +- .init = _nouveau_vmmgr_init, +- .fini = _nouveau_vmmgr_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c b/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c +deleted file mode 100644 +index 2d098875..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/vm/nvc0.c ++++ /dev/null +@@ -1,242 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +- +-struct nvc0_vmmgr_priv { +- struct nouveau_vmmgr base; +-}; +- +- +-/* Map from compressed to corresponding uncompressed storage type. +- * The value 0xff represents an invalid storage type. +- */ +-const u8 nvc0_pte_storage_type_map[256] = +-{ +- 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ +- 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, 0x11, /* 0x10 */ +- 0x11, 0x11, 0x11, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x26, 0x27, /* 0x20 */ +- 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x30 */ +- 0xff, 0xff, 0x26, 0x27, 0x28, 0x29, 0x26, 0x27, +- 0x28, 0x29, 0xff, 0xff, 0xff, 0xff, 0x46, 0xff, /* 0x40 */ +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0x46, 0x46, 0x46, 0x46, 0xff, 0xff, 0xff, /* 0x50 */ +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x60 */ +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x70 */ +- 0xff, 0xff, 0xff, 0x7b, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x7b, 0x7b, /* 0x80 */ +- 0x7b, 0x7b, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x90 */ +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0x8b, 0x8c, 0x8d, 0x8e, 0xa7, /* 0xa0 */ +- 0xa8, 0xa9, 0xaa, 0xff, 0xff, 0xff, 0xff, 0xff, +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xb0 */ +- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa7, +- 0xa8, 0xa9, 0xaa, 0xc3, 0xff, 0xff, 0xff, 0xff, /* 0xc0 */ +- 0xff, 0xff, 0xff, 0xff, 0xfe, 0xfe, 0xc3, 0xc3, +- 0xc3, 0xc3, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0xd0 */ +- 0xfe, 0xff, 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, +- 0xfe, 0xff, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xff, /* 0xe0 */ +- 0xff, 0xfe, 0xff, 0xfe, 0xff, 0xfe, 0xfe, 0xff, +- 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, /* 0xf0 */ +- 0xfe, 0xfe, 0xfe, 0xfe, 0xff, 0xfd, 0xfe, 0xff +-}; +- +- +-static void +-nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, +- struct nouveau_gpuobj *pgt[2]) +-{ +- u32 pde[2] = { 0, 0 }; +- +- if (pgt[0]) +- pde[1] = 0x00000001 | (pgt[0]->addr >> 8); +- if (pgt[1]) +- pde[0] = 0x00000001 | (pgt[1]->addr >> 8); +- +- nv_wo32(pgd, (index * 8) + 0, pde[0]); +- nv_wo32(pgd, (index * 8) + 4, pde[1]); +-} +- +-static inline u64 +-nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +-{ +- phys >>= 8; +- +- phys |= 0x00000001; /* present */ +- if (vma->access & NV_MEM_ACCESS_SYS) +- phys |= 0x00000002; +- +- phys |= ((u64)target << 32); +- phys |= ((u64)memtype << 36); +- +- return phys; +-} +- +-static void +-nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +-{ +- u64 next = 1 << (vma->node->type - 8); +- +- phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); +- pte <<= 3; +- +- if (mem->tag) { +- struct nouveau_ltc *ltc = +- nouveau_ltc(vma->vm->vmm->base.base.parent); +- u32 tag = mem->tag->offset + (delta >> 17); +- phys |= (u64)tag << (32 + 12); +- next |= (u64)1 << (32 + 12); +- ltc->tags_clear(ltc, tag, cnt); +- } +- +- while (cnt--) { +- nv_wo32(pgt, pte + 0, lower_32_bits(phys)); +- nv_wo32(pgt, pte + 4, upper_32_bits(phys)); +- phys += next; +- pte += 8; +- } +-} +- +-static void +-nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, +- struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +-{ +- u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; +- /* compressed storage types are invalid for system memory */ +- u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; +- +- pte <<= 3; +- while (cnt--) { +- u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); +- nv_wo32(pgt, pte + 0, lower_32_bits(phys)); +- nv_wo32(pgt, pte + 4, upper_32_bits(phys)); +- pte += 8; +- } +-} +- +-static void +-nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +-{ +- pte <<= 3; +- while (cnt--) { +- nv_wo32(pgt, pte + 0, 0x00000000); +- nv_wo32(pgt, pte + 4, 0x00000000); +- pte += 8; +- } +-} +- +-static void +-nvc0_vm_flush(struct nouveau_vm *vm) +-{ +- struct nvc0_vmmgr_priv *priv = (void *)vm->vmm; +- struct nouveau_bar *bar = nouveau_bar(priv); +- struct nouveau_vm_pgd *vpgd; +- u32 type; +- +- bar->flush(bar); +- +- type = 0x00000001; /* PAGE_ALL */ +- if (atomic_read(&vm->engref[NVDEV_SUBDEV_BAR])) +- type |= 0x00000004; /* HUB_ONLY */ +- +- mutex_lock(&nv_subdev(priv)->mutex); +- list_for_each_entry(vpgd, &vm->pgd_list, head) { +- /* looks like maybe a "free flush slots" counter, the +- * faster you write to 0x100cbc to more it decreases +- */ +- if (!nv_wait_ne(priv, 0x100c80, 0x00ff0000, 0x00000000)) { +- nv_error(priv, "vm timeout 0: 0x%08x %d\n", +- nv_rd32(priv, 0x100c80), type); +- } +- +- nv_wr32(priv, 0x100cb8, vpgd->obj->addr >> 8); +- nv_wr32(priv, 0x100cbc, 0x80000000 | type); +- +- /* wait for flush to be queued? */ +- if (!nv_wait(priv, 0x100c80, 0x00008000, 0x00008000)) { +- nv_error(priv, "vm timeout 1: 0x%08x %d\n", +- nv_rd32(priv, 0x100c80), type); +- } +- } +- mutex_unlock(&nv_subdev(priv)->mutex); +-} +- +-static int +-nvc0_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, +- u64 mm_offset, struct nouveau_vm **pvm) +-{ +- return nouveau_vm_create(vmm, offset, length, mm_offset, 4096, pvm); +-} +- +-static int +-nvc0_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nvc0_vmmgr_priv *priv; +- int ret; +- +- ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- priv->base.limit = 1ULL << 40; +- priv->base.dma_bits = 40; +- priv->base.pgt_bits = 27 - 12; +- priv->base.spg_shift = 12; +- priv->base.lpg_shift = 17; +- priv->base.create = nvc0_vm_create; +- priv->base.map_pgt = nvc0_vm_map_pgt; +- priv->base.map = nvc0_vm_map; +- priv->base.map_sg = nvc0_vm_map_sg; +- priv->base.unmap = nvc0_vm_unmap; +- priv->base.flush = nvc0_vm_flush; +- return 0; +-} +- +-struct nouveau_oclass +-nvc0_vmmgr_oclass = { +- .handle = NV_SUBDEV(VM, 0xc0), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nvc0_vmmgr_ctor, +- .dtor = _nouveau_vmmgr_dtor, +- .init = _nouveau_vmmgr_init, +- .fini = _nouveau_vmmgr_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c b/drivers/gpu/drm/nouveau/core/subdev/volt/base.c +deleted file mode 100644 +index 32794a99..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/volt/base.c ++++ /dev/null +@@ -1,198 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +- +-static int +-nouveau_volt_get(struct nouveau_volt *volt) +-{ +- if (volt->vid_get) { +- int ret = volt->vid_get(volt), i; +- if (ret >= 0) { +- for (i = 0; i < volt->vid_nr; i++) { +- if (volt->vid[i].vid == ret) +- return volt->vid[i].uv; +- } +- ret = -EINVAL; +- } +- return ret; +- } +- return -ENODEV; +-} +- +-static int +-nouveau_volt_set(struct nouveau_volt *volt, u32 uv) +-{ +- if (volt->vid_set) { +- int i, ret = -EINVAL; +- for (i = 0; i < volt->vid_nr; i++) { +- if (volt->vid[i].uv == uv) { +- ret = volt->vid_set(volt, volt->vid[i].vid); +- nv_debug(volt, "set %duv: %d\n", uv, ret); +- break; +- } +- } +- return ret; +- } +- return -ENODEV; +-} +- +-static int +-nouveau_volt_map(struct nouveau_volt *volt, u8 id) +-{ +- struct nouveau_bios *bios = nouveau_bios(volt); +- struct nvbios_vmap_entry info; +- u8 ver, len; +- u16 vmap; +- +- vmap = nvbios_vmap_entry_parse(bios, id, &ver, &len, &info); +- if (vmap) { +- if (info.link != 0xff) { +- int ret = nouveau_volt_map(volt, info.link); +- if (ret < 0) +- return ret; +- info.min += ret; +- } +- return info.min; +- } +- +- return id ? id * 10000 : -ENODEV; +-} +- +-static int +-nouveau_volt_set_id(struct nouveau_volt *volt, u8 id, int condition) +-{ +- int ret = nouveau_volt_map(volt, id); +- if (ret >= 0) { +- int prev = nouveau_volt_get(volt); +- if (!condition || prev < 0 || +- (condition < 0 && ret < prev) || +- (condition > 0 && ret > prev)) { +- ret = nouveau_volt_set(volt, ret); +- } else { +- ret = 0; +- } +- } +- return ret; +-} +- +-int +-_nouveau_volt_init(struct nouveau_object *object) +-{ +- struct nouveau_volt *volt = (void *)object; +- int ret; +- +- ret = nouveau_subdev_init(&volt->base); +- if (ret) +- return ret; +- +- ret = volt->get(volt); +- if (ret < 0) { +- if (ret != -ENODEV) +- nv_debug(volt, "current voltage unknown\n"); +- return 0; +- } +- +- nv_info(volt, "GPU voltage: %duv\n", ret); +- return 0; +-} +- +-void +-_nouveau_volt_dtor(struct nouveau_object *object) +-{ +- struct nouveau_volt *volt = (void *)object; +- nouveau_subdev_destroy(&volt->base); +-} +- +-int +-nouveau_volt_create_(struct nouveau_object *parent, +- struct nouveau_object *engine, +- struct nouveau_oclass *oclass, int length, void **pobject) +-{ +- struct nouveau_bios *bios = nouveau_bios(parent); +- struct nouveau_volt *volt; +- struct nvbios_volt_entry ivid; +- struct nvbios_volt info; +- u8 ver, hdr, cnt, len; +- u16 data; +- int ret, i; +- +- ret = nouveau_subdev_create_(parent, engine, oclass, 0, "VOLT", +- "voltage", length, pobject); +- volt = *pobject; +- if (ret) +- return ret; +- +- volt->get = nouveau_volt_get; +- volt->set = nouveau_volt_set; +- volt->set_id = nouveau_volt_set_id; +- +- data = nvbios_volt_parse(bios, &ver, &hdr, &cnt, &len, &info); +- if (data && info.vidmask && info.base && info.step) { +- for (i = 0; i < info.vidmask + 1; i++) { +- if (info.base >= info.min && +- info.base <= info.max) { +- volt->vid[volt->vid_nr].uv = info.base; +- volt->vid[volt->vid_nr].vid = i; +- volt->vid_nr++; +- } +- info.base += info.step; +- } +- volt->vid_mask = info.vidmask; +- } else +- if (data && info.vidmask) { +- for (i = 0; i < cnt; i++) { +- data = nvbios_volt_entry_parse(bios, i, &ver, &hdr, +- &ivid); +- if (data) { +- volt->vid[volt->vid_nr].uv = ivid.voltage; +- volt->vid[volt->vid_nr].vid = ivid.vid; +- volt->vid_nr++; +- } +- } +- volt->vid_mask = info.vidmask; +- } +- +- if (volt->vid_nr) { +- for (i = 0; i < volt->vid_nr; i++) { +- nv_debug(volt, "VID %02x: %duv\n", +- volt->vid[i].vid, volt->vid[i].uv); +- } +- +- /*XXX: this is an assumption.. there probably exists boards +- * out there with i2c-connected voltage controllers too.. +- */ +- ret = nouveau_voltgpio_init(volt); +- if (ret == 0) { +- volt->vid_get = nouveau_voltgpio_get; +- volt->vid_set = nouveau_voltgpio_set; +- } +- } +- +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c b/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c +deleted file mode 100644 +index 755fa91b..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/volt/gpio.c ++++ /dev/null +@@ -1,96 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-static const u8 tags[] = { +- DCB_GPIO_VID0, DCB_GPIO_VID1, DCB_GPIO_VID2, DCB_GPIO_VID3, +- DCB_GPIO_VID4, DCB_GPIO_VID5, DCB_GPIO_VID6, DCB_GPIO_VID7, +-}; +- +-int +-nouveau_voltgpio_get(struct nouveau_volt *volt) +-{ +- struct nouveau_gpio *gpio = nouveau_gpio(volt); +- u8 vid = 0; +- int i; +- +- for (i = 0; i < ARRAY_SIZE(tags); i++) { +- if (volt->vid_mask & (1 << i)) { +- int ret = gpio->get(gpio, 0, tags[i], 0xff); +- if (ret < 0) +- return ret; +- vid |= ret << i; +- } +- } +- +- return vid; +-} +- +-int +-nouveau_voltgpio_set(struct nouveau_volt *volt, u8 vid) +-{ +- struct nouveau_gpio *gpio = nouveau_gpio(volt); +- int i; +- +- for (i = 0; i < ARRAY_SIZE(tags); i++, vid >>= 1) { +- if (volt->vid_mask & (1 << i)) { +- int ret = gpio->set(gpio, 0, tags[i], 0xff, vid & 1); +- if (ret < 0) +- return ret; +- } +- } +- +- return 0; +-} +- +-int +-nouveau_voltgpio_init(struct nouveau_volt *volt) +-{ +- struct nouveau_gpio *gpio = nouveau_gpio(volt); +- struct dcb_gpio_func func; +- int i; +- +- /* check we have gpio function info for each vid bit. on some +- * boards (ie. nvs295) the vid mask has more bits than there +- * are valid gpio functions... from traces, nvidia appear to +- * just touch the existing ones, so let's mask off the invalid +- * bits and continue with life +- */ +- for (i = 0; i < ARRAY_SIZE(tags); i++) { +- if (volt->vid_mask & (1 << i)) { +- int ret = gpio->find(gpio, 0, tags[i], 0xff, &func); +- if (ret) { +- if (ret != -ENOENT) +- return ret; +- nv_debug(volt, "VID bit %d has no GPIO\n", i); +- volt->vid_mask &= ~(1 << i); +- } +- } +- } +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c b/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c +deleted file mode 100644 +index 87d53583..00000000 +--- a/drivers/gpu/drm/nouveau/core/subdev/volt/nv40.c ++++ /dev/null +@@ -1,56 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-struct nv40_volt_priv { +- struct nouveau_volt base; +-}; +- +-static int +-nv40_volt_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +- struct nouveau_oclass *oclass, void *data, u32 size, +- struct nouveau_object **pobject) +-{ +- struct nv40_volt_priv *priv; +- int ret; +- +- ret = nouveau_volt_create(parent, engine, oclass, &priv); +- *pobject = nv_object(priv); +- if (ret) +- return ret; +- +- return 0; +-} +- +-struct nouveau_oclass +-nv40_volt_oclass = { +- .handle = NV_SUBDEV(VOLT, 0x40), +- .ofuncs = &(struct nouveau_ofuncs) { +- .ctor = nv40_volt_ctor, +- .dtor = _nouveau_volt_dtor, +- .init = _nouveau_volt_init, +- .fini = _nouveau_volt_fini, +- }, +-}; +diff --git a/drivers/gpu/drm/nouveau/dispnv04/Makefile b/drivers/gpu/drm/nouveau/dispnv04/Makefile +deleted file mode 100644 +index 424a489d..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/Makefile ++++ /dev/null +@@ -1,11 +0,0 @@ +-nouveau-y += dispnv04/arb.o +-nouveau-y += dispnv04/crtc.o +-nouveau-y += dispnv04/cursor.o +-nouveau-y += dispnv04/dac.o +-nouveau-y += dispnv04/dfp.o +-nouveau-y += dispnv04/disp.o +-nouveau-y += dispnv04/hw.o +-nouveau-y += dispnv04/overlay.o +-nouveau-y += dispnv04/tvmodesnv17.o +-nouveau-y += dispnv04/tvnv04.o +-nouveau-y += dispnv04/tvnv17.o +diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c +deleted file mode 100644 +index c6361422..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/arb.c ++++ /dev/null +@@ -1,265 +0,0 @@ +-/* +- * Copyright 1993-2003 NVIDIA, Corporation +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "hw.h" +- +-/****************************************************************************\ +-* * +-* The video arbitration routines calculate some "magic" numbers. Fixes * +-* the snow seen when accessing the framebuffer without it. * +-* It just works (I hope). * +-* * +-\****************************************************************************/ +- +-struct nv_fifo_info { +- int lwm; +- int burst; +-}; +- +-struct nv_sim_state { +- int pclk_khz; +- int mclk_khz; +- int nvclk_khz; +- int bpp; +- int mem_page_miss; +- int mem_latency; +- int memory_type; +- int memory_width; +- int two_heads; +-}; +- +-static void +-nv04_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb) +-{ +- int pagemiss, cas, width, bpp; +- int nvclks, mclks, pclks, crtpagemiss; +- int found, mclk_extra, mclk_loop, cbs, m1, p1; +- int mclk_freq, pclk_freq, nvclk_freq; +- int us_m, us_n, us_p, crtc_drain_rate; +- int cpm_us, us_crt, clwm; +- +- pclk_freq = arb->pclk_khz; +- mclk_freq = arb->mclk_khz; +- nvclk_freq = arb->nvclk_khz; +- pagemiss = arb->mem_page_miss; +- cas = arb->mem_latency; +- width = arb->memory_width >> 6; +- bpp = arb->bpp; +- cbs = 128; +- +- pclks = 2; +- nvclks = 10; +- mclks = 13 + cas; +- mclk_extra = 3; +- found = 0; +- +- while (!found) { +- found = 1; +- +- mclk_loop = mclks + mclk_extra; +- us_m = mclk_loop * 1000 * 1000 / mclk_freq; +- us_n = nvclks * 1000 * 1000 / nvclk_freq; +- us_p = nvclks * 1000 * 1000 / pclk_freq; +- +- crtc_drain_rate = pclk_freq * bpp / 8; +- crtpagemiss = 2; +- crtpagemiss += 1; +- cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; +- us_crt = cpm_us + us_m + us_n + us_p; +- clwm = us_crt * crtc_drain_rate / (1000 * 1000); +- clwm++; +- +- m1 = clwm + cbs - 512; +- p1 = m1 * pclk_freq / mclk_freq; +- p1 = p1 * bpp / 8; +- if ((p1 < m1 && m1 > 0) || clwm > 519) { +- found = !mclk_extra; +- mclk_extra--; +- } +- if (clwm < 384) +- clwm = 384; +- +- fifo->lwm = clwm; +- fifo->burst = cbs; +- } +-} +- +-static void +-nv10_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb) +-{ +- int fill_rate, drain_rate; +- int pclks, nvclks, mclks, xclks; +- int pclk_freq, nvclk_freq, mclk_freq; +- int fill_lat, extra_lat; +- int max_burst_o, max_burst_l; +- int fifo_len, min_lwm, max_lwm; +- const int burst_lat = 80; /* Maximum allowable latency due +- * to the CRTC FIFO burst. (ns) */ +- +- pclk_freq = arb->pclk_khz; +- nvclk_freq = arb->nvclk_khz; +- mclk_freq = arb->mclk_khz; +- +- fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */ +- drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */ +- +- fifo_len = arb->two_heads ? 1536 : 1024; /* B */ +- +- /* Fixed FIFO refill latency. */ +- +- pclks = 4; /* lwm detect. */ +- +- nvclks = 3 /* lwm -> sync. */ +- + 2 /* fbi bus cycles (1 req + 1 busy) */ +- + 1 /* 2 edge sync. may be very close to edge so +- * just put one. */ +- + 1 /* fbi_d_rdv_n */ +- + 1 /* Fbi_d_rdata */ +- + 1; /* crtfifo load */ +- +- mclks = 1 /* 2 edge sync. may be very close to edge so +- * just put one. */ +- + 1 /* arb_hp_req */ +- + 5 /* tiling pipeline */ +- + 2 /* latency fifo */ +- + 2 /* memory request to fbio block */ +- + 7; /* data returned from fbio block */ +- +- /* Need to accumulate 256 bits for read */ +- mclks += (arb->memory_type == 0 ? 2 : 1) +- * arb->memory_width / 32; +- +- fill_lat = mclks * 1000 * 1000 / mclk_freq /* minimum mclk latency */ +- + nvclks * 1000 * 1000 / nvclk_freq /* nvclk latency */ +- + pclks * 1000 * 1000 / pclk_freq; /* pclk latency */ +- +- /* Conditional FIFO refill latency. */ +- +- xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to +- * the overlay. */ +- + 2 * arb->mem_page_miss /* Extra pagemiss latency. */ +- + (arb->bpp == 32 ? 8 : 4); /* Margin of error. */ +- +- extra_lat = xclks * 1000 * 1000 / mclk_freq; +- +- if (arb->two_heads) +- /* Account for another CRTC. */ +- extra_lat += fill_lat + extra_lat + burst_lat; +- +- /* FIFO burst */ +- +- /* Max burst not leading to overflows. */ +- max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000)) +- * (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000); +- fifo->burst = min(max_burst_o, 1024); +- +- /* Max burst value with an acceptable latency. */ +- max_burst_l = burst_lat * fill_rate / (1000 * 1000); +- fifo->burst = min(max_burst_l, fifo->burst); +- +- fifo->burst = rounddown_pow_of_two(fifo->burst); +- +- /* FIFO low watermark */ +- +- min_lwm = (fill_lat + extra_lat) * drain_rate / (1000 * 1000) + 1; +- max_lwm = fifo_len - fifo->burst +- + fill_lat * drain_rate / (1000 * 1000) +- + fifo->burst * drain_rate / fill_rate; +- +- fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */ +-} +- +-static void +-nv04_update_arb(struct drm_device *dev, int VClk, int bpp, +- int *burst, int *lwm) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nv_fifo_info fifo_data; +- struct nv_sim_state sim_data; +- int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); +- int NVClk = nouveau_hw_get_clock(dev, PLL_CORE); +- uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); +- +- sim_data.pclk_khz = VClk; +- sim_data.mclk_khz = MClk; +- sim_data.nvclk_khz = NVClk; +- sim_data.bpp = bpp; +- sim_data.two_heads = nv_two_heads(dev); +- if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ || +- (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) { +- uint32_t type; +- +- pci_read_config_dword(pci_get_bus_and_slot(0, 1), 0x7c, &type); +- +- sim_data.memory_type = (type >> 12) & 1; +- sim_data.memory_width = 64; +- sim_data.mem_latency = 3; +- sim_data.mem_page_miss = 10; +- } else { +- sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; +- sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; +- sim_data.mem_latency = cfg1 & 0xf; +- sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); +- } +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) +- nv04_calc_arb(&fifo_data, &sim_data); +- else +- nv10_calc_arb(&fifo_data, &sim_data); +- +- *burst = ilog2(fifo_data.burst >> 4); +- *lwm = fifo_data.lwm >> 3; +-} +- +-static void +-nv20_update_arb(int *burst, int *lwm) +-{ +- unsigned int fifo_size, burst_size, graphics_lwm; +- +- fifo_size = 2048; +- burst_size = 512; +- graphics_lwm = fifo_size - burst_size; +- +- *burst = ilog2(burst_size >> 5); +- *lwm = graphics_lwm >> 3; +-} +- +-void +-nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) +- nv04_update_arb(dev, vclk, bpp, burst, lwm); +- else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || +- (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { +- *burst = 128; +- *lwm = 0x0480; +- } else +- nv20_update_arb(burst, lwm); +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c +deleted file mode 100644 +index fca6a1f9..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c ++++ /dev/null +@@ -1,1145 +0,0 @@ +-/* +- * Copyright 1993-2003 NVIDIA, Corporation +- * Copyright 2006 Dave Airlie +- * Copyright 2007 Maarten Maathuis +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +-#include +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "nouveau_bo.h" +-#include "nouveau_gem.h" +-#include "nouveau_encoder.h" +-#include "nouveau_connector.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +-#include "nvreg.h" +-#include "nouveau_fbcon.h" +-#include "disp.h" +- +-#include +-#include +- +-static int +-nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, +- struct drm_framebuffer *old_fb); +- +-static void +-crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) +-{ +- NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, +- crtcstate->CRTC[index]); +-} +- +-static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- +- regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; +- if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { +- regp->CRTC[NV_CIO_CRE_CSB] = 0x80; +- regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); +- } +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); +-} +- +-static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- +- nv_crtc->sharpness = level; +- if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ +- level += 0x40; +- regp->ramdac_634 = level; +- NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); +-} +- +-#define PLLSEL_VPLL1_MASK \ +- (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) +-#define PLLSEL_VPLL2_MASK \ +- (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) +-#define PLLSEL_TV_MASK \ +- (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) +- +-/* NV4x 0x40.. pll notes: +- * gpu pll: 0x4000 + 0x4004 +- * ?gpu? pll: 0x4008 + 0x400c +- * vpll1: 0x4010 + 0x4014 +- * vpll2: 0x4018 + 0x401c +- * mpll: 0x4020 + 0x4024 +- * mpll: 0x4038 + 0x403c +- * +- * the first register of each pair has some unknown details: +- * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) +- * bits 20-23: (mpll) something to do with post divider? +- * bits 28-31: related to single stage mode? (bit 8/12) +- */ +- +-static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) +-{ +- struct drm_device *dev = crtc->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_bios *bios = nvkm_bios(&drm->device); +- struct nouveau_clock *clk = nvkm_clock(&drm->device); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; +- struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; +- struct nouveau_pll_vals *pv = ®p->pllvals; +- struct nvbios_pll pll_lim; +- +- if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, +- &pll_lim)) +- return; +- +- /* NM2 == 0 is used to determine single stage mode on two stage plls */ +- pv->NM2 = 0; +- +- /* for newer nv4x the blob uses only the first stage of the vpll below a +- * certain clock. for a certain nv4b this is 150MHz. since the max +- * output frequency of the first stage for this card is 300MHz, it is +- * assumed the threshold is given by vco1 maxfreq/2 +- */ +- /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, +- * not 8, others unknown), the blob always uses both plls. no problem +- * has yet been observed in allowing the use a single stage pll on all +- * nv43 however. the behaviour of single stage use is untested on nv40 +- */ +- if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) +- memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); +- +- +- if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) +- return; +- +- state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; +- +- /* The blob uses this always, so let's do the same */ +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; +- /* again nv40 and some nv43 act more like nv3x as described above */ +- if (drm->device.info.chipset < 0x41) +- state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | +- NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; +- state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; +- +- if (pv->NM2) +- NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", +- pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); +- else +- NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", +- pv->N1, pv->M1, pv->log2P); +- +- nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); +-} +- +-static void +-nv_crtc_dpms(struct drm_crtc *crtc, int mode) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- unsigned char seq1 = 0, crtc17 = 0; +- unsigned char crtc1A; +- +- NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, +- nv_crtc->index); +- +- if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ +- return; +- +- nv_crtc->last_dpms = mode; +- +- if (nv_two_heads(dev)) +- NVSetOwner(dev, nv_crtc->index); +- +- /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ +- crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, +- NV_CIO_CRE_RPC1_INDEX) & ~0xC0; +- switch (mode) { +- case DRM_MODE_DPMS_STANDBY: +- /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ +- seq1 = 0x20; +- crtc17 = 0x80; +- crtc1A |= 0x80; +- break; +- case DRM_MODE_DPMS_SUSPEND: +- /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ +- seq1 = 0x20; +- crtc17 = 0x80; +- crtc1A |= 0x40; +- break; +- case DRM_MODE_DPMS_OFF: +- /* Screen: Off; HSync: Off, VSync: Off */ +- seq1 = 0x20; +- crtc17 = 0x00; +- crtc1A |= 0xC0; +- break; +- case DRM_MODE_DPMS_ON: +- default: +- /* Screen: On; HSync: On, VSync: On */ +- seq1 = 0x00; +- crtc17 = 0x80; +- break; +- } +- +- NVVgaSeqReset(dev, nv_crtc->index, true); +- /* Each head has it's own sequencer, so we can turn it off when we want */ +- seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); +- NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); +- crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); +- mdelay(10); +- NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); +- NVVgaSeqReset(dev, nv_crtc->index, false); +- +- NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); +-} +- +-static bool +-nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- return true; +-} +- +-static void +-nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) +-{ +- struct drm_device *dev = crtc->dev; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- struct drm_framebuffer *fb = crtc->primary->fb; +- +- /* Calculate our timings */ +- int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; +- int horizStart = (mode->crtc_hsync_start >> 3) + 1; +- int horizEnd = (mode->crtc_hsync_end >> 3) + 1; +- int horizTotal = (mode->crtc_htotal >> 3) - 5; +- int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; +- int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; +- int vertDisplay = mode->crtc_vdisplay - 1; +- int vertStart = mode->crtc_vsync_start - 1; +- int vertEnd = mode->crtc_vsync_end - 1; +- int vertTotal = mode->crtc_vtotal - 2; +- int vertBlankStart = mode->crtc_vdisplay - 1; +- int vertBlankEnd = mode->crtc_vtotal - 1; +- +- struct drm_encoder *encoder; +- bool fp_output = false; +- +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- +- if (encoder->crtc == crtc && +- (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || +- nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) +- fp_output = true; +- } +- +- if (fp_output) { +- vertStart = vertTotal - 3; +- vertEnd = vertTotal - 2; +- vertBlankStart = vertStart; +- horizStart = horizTotal - 5; +- horizEnd = horizTotal - 2; +- horizBlankEnd = horizTotal + 4; +-#if 0 +- if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) +- /* This reportedly works around some video overlay bandwidth problems */ +- horizTotal += 2; +-#endif +- } +- +- if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- vertTotal |= 1; +- +-#if 0 +- ErrorF("horizDisplay: 0x%X \n", horizDisplay); +- ErrorF("horizStart: 0x%X \n", horizStart); +- ErrorF("horizEnd: 0x%X \n", horizEnd); +- ErrorF("horizTotal: 0x%X \n", horizTotal); +- ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); +- ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); +- ErrorF("vertDisplay: 0x%X \n", vertDisplay); +- ErrorF("vertStart: 0x%X \n", vertStart); +- ErrorF("vertEnd: 0x%X \n", vertEnd); +- ErrorF("vertTotal: 0x%X \n", vertTotal); +- ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); +- ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); +-#endif +- +- /* +- * compute correct Hsync & Vsync polarity +- */ +- if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) +- && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { +- +- regp->MiscOutReg = 0x23; +- if (mode->flags & DRM_MODE_FLAG_NHSYNC) +- regp->MiscOutReg |= 0x40; +- if (mode->flags & DRM_MODE_FLAG_NVSYNC) +- regp->MiscOutReg |= 0x80; +- } else { +- int vdisplay = mode->vdisplay; +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- vdisplay *= 2; +- if (mode->vscan > 1) +- vdisplay *= mode->vscan; +- if (vdisplay < 400) +- regp->MiscOutReg = 0xA3; /* +hsync -vsync */ +- else if (vdisplay < 480) +- regp->MiscOutReg = 0x63; /* -hsync +vsync */ +- else if (vdisplay < 768) +- regp->MiscOutReg = 0xE3; /* -hsync -vsync */ +- else +- regp->MiscOutReg = 0x23; /* +hsync +vsync */ +- } +- +- /* +- * Time Sequencer +- */ +- regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; +- /* 0x20 disables the sequencer */ +- if (mode->flags & DRM_MODE_FLAG_CLKDIV2) +- regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; +- else +- regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; +- regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; +- regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; +- regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; +- +- /* +- * CRTC +- */ +- regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; +- regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; +- regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; +- regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | +- XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); +- regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; +- regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | +- XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); +- regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; +- regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | +- XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | +- XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | +- (1 << 4) | +- XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | +- XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | +- XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | +- XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); +- regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | +- 1 << 6 | +- XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); +- regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; +- regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); +- regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; +- /* framebuffer can be larger than crtc scanout area. */ +- regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; +- regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; +- regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; +- regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; +- regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; +- regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; +- +- /* +- * Some extended CRTC registers (they are not saved with the rest of the vga regs). +- */ +- +- /* framebuffer can be larger than crtc scanout area. */ +- regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = +- XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); +- regp->CRTC[NV_CIO_CRE_42] = +- XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); +- regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? +- MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; +- regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | +- XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | +- XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | +- XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | +- XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); +- regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | +- XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | +- XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | +- XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); +- regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | +- XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | +- XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | +- XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); +- +- if (mode->flags & DRM_MODE_FLAG_INTERLACE) { +- horizTotal = (horizTotal >> 1) & ~1; +- regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; +- regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); +- } else +- regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ +- +- /* +- * Graphics Display Controller +- */ +- regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; +- regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; +- regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; +- regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; +- regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; +- regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ +- regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ +- regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; +- regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; +- +- regp->Attribute[0] = 0x00; /* standard colormap translation */ +- regp->Attribute[1] = 0x01; +- regp->Attribute[2] = 0x02; +- regp->Attribute[3] = 0x03; +- regp->Attribute[4] = 0x04; +- regp->Attribute[5] = 0x05; +- regp->Attribute[6] = 0x06; +- regp->Attribute[7] = 0x07; +- regp->Attribute[8] = 0x08; +- regp->Attribute[9] = 0x09; +- regp->Attribute[10] = 0x0A; +- regp->Attribute[11] = 0x0B; +- regp->Attribute[12] = 0x0C; +- regp->Attribute[13] = 0x0D; +- regp->Attribute[14] = 0x0E; +- regp->Attribute[15] = 0x0F; +- regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ +- /* Non-vga */ +- regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; +- regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ +- regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; +- regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; +-} +- +-/** +- * Sets up registers for the given mode/adjusted_mode pair. +- * +- * The clocks, CRTCs and outputs attached to this CRTC must be off. +- * +- * This shouldn't enable any clocks, CRTCs, or outputs, but they should +- * be easily turned on/off after this. +- */ +-static void +-nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) +-{ +- struct drm_device *dev = crtc->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; +- struct drm_encoder *encoder; +- bool lvds_output = false, tmds_output = false, tv_output = false, +- off_chip_digital = false; +- +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- bool digital = false; +- +- if (encoder->crtc != crtc) +- continue; +- +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) +- digital = lvds_output = true; +- if (nv_encoder->dcb->type == DCB_OUTPUT_TV) +- tv_output = true; +- if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) +- digital = tmds_output = true; +- if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) +- off_chip_digital = true; +- } +- +- /* Registers not directly related to the (s)vga mode */ +- +- /* What is the meaning of this register? */ +- /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ +- regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); +- +- regp->crtc_eng_ctrl = 0; +- /* Except for rare conditions I2C is enabled on the primary crtc */ +- if (nv_crtc->index == 0) +- regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; +-#if 0 +- /* Set overlay to desired crtc. */ +- if (dev->overlayAdaptor) { +- NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); +- if (pPriv->overlayCRTC == nv_crtc->index) +- regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; +- } +-#endif +- +- /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ +- regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | +- NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | +- NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; +- if (drm->device.info.chipset >= 0x11) +- regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; +- +- /* Unblock some timings */ +- regp->CRTC[NV_CIO_CRE_53] = 0; +- regp->CRTC[NV_CIO_CRE_54] = 0; +- +- /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ +- if (lvds_output) +- regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; +- else if (tmds_output) +- regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; +- else +- regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; +- +- /* These values seem to vary */ +- /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ +- regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; +- +- nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); +- +- /* probably a scratch reg, but kept for cargo-cult purposes: +- * bit0: crtc0?, head A +- * bit6: lvds, head A +- * bit7: (only in X), head A +- */ +- if (nv_crtc->index == 0) +- regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; +- +- /* The blob seems to take the current value from crtc 0, add 4 to that +- * and reuse the old value for crtc 1 */ +- regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; +- if (!nv_crtc->index) +- regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; +- +- /* the blob sometimes sets |= 0x10 (which is the same as setting |= +- * 1 << 30 on 0x60.830), for no apparent reason */ +- regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) +- regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; +- +- regp->crtc_830 = mode->crtc_vdisplay - 3; +- regp->crtc_834 = mode->crtc_vdisplay - 1; +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- /* This is what the blob does */ +- regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) +- regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) +- regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; +- else +- regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; +- +- /* Some misc regs */ +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { +- regp->CRTC[NV_CIO_CRE_85] = 0xFF; +- regp->CRTC[NV_CIO_CRE_86] = 0x1; +- } +- +- regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8; +- /* Enable slaved mode (called MODE_TV in nv4ref.h) */ +- if (lvds_output || tmds_output || tv_output) +- regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); +- +- /* Generic PRAMDAC regs */ +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) +- /* Only bit that bios and blob set. */ +- regp->nv10_cursync = (1 << 25); +- +- regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | +- NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | +- NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; +- if (crtc->primary->fb->depth == 16) +- regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; +- if (drm->device.info.chipset >= 0x11) +- regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; +- +- regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ +- regp->tv_setup = 0; +- +- nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); +- +- /* Some values the blob sets */ +- regp->ramdac_8c0 = 0x100; +- regp->ramdac_a20 = 0x0; +- regp->ramdac_a24 = 0xfffff; +- regp->ramdac_a34 = 0x1; +-} +- +-static int +-nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) +-{ +- struct nv04_display *disp = nv04_display(crtc->dev); +- struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- int ret; +- +- ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); +- if (ret == 0) { +- if (disp->image[nv_crtc->index]) +- nouveau_bo_unpin(disp->image[nv_crtc->index]); +- nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); +- } +- +- return ret; +-} +- +-/** +- * Sets up registers for the given mode/adjusted_mode pair. +- * +- * The clocks, CRTCs and outputs attached to this CRTC must be off. +- * +- * This shouldn't enable any clocks, CRTCs, or outputs, but they should +- * be easily turned on/off after this. +- */ +-static int +-nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode, +- int x, int y, struct drm_framebuffer *old_fb) +-{ +- struct drm_device *dev = crtc->dev; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nouveau_drm *drm = nouveau_drm(dev); +- int ret; +- +- NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); +- drm_mode_debug_printmodeline(adjusted_mode); +- +- ret = nv_crtc_swap_fbs(crtc, old_fb); +- if (ret) +- return ret; +- +- /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ +- nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); +- +- nv_crtc_mode_set_vga(crtc, adjusted_mode); +- /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); +- nv_crtc_mode_set_regs(crtc, adjusted_mode); +- nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); +- return 0; +-} +- +-static void nv_crtc_save(struct drm_crtc *crtc) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; +- struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; +- struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; +- struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; +- +- if (nv_two_heads(crtc->dev)) +- NVSetOwner(crtc->dev, nv_crtc->index); +- +- nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); +- +- /* init some state to saved value */ +- state->sel_clk = saved->sel_clk & ~(0x5 << 16); +- crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; +- state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); +- crtc_state->gpio_ext = crtc_saved->gpio_ext; +-} +- +-static void nv_crtc_restore(struct drm_crtc *crtc) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- int head = nv_crtc->index; +- uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; +- +- if (nv_two_heads(crtc->dev)) +- NVSetOwner(crtc->dev, head); +- +- nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); +- nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); +- +- nv_crtc->last_dpms = NV_DPMS_CLEARED; +-} +- +-static void nv_crtc_prepare(struct drm_crtc *crtc) +-{ +- struct drm_device *dev = crtc->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_crtc_helper_funcs *funcs = crtc->helper_private; +- +- if (nv_two_heads(dev)) +- NVSetOwner(dev, nv_crtc->index); +- +- drm_vblank_pre_modeset(dev, nv_crtc->index); +- funcs->dpms(crtc, DRM_MODE_DPMS_OFF); +- +- NVBlankScreen(dev, nv_crtc->index, true); +- +- /* Some more preparation. */ +- NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { +- uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); +- NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); +- } +-} +- +-static void nv_crtc_commit(struct drm_crtc *crtc) +-{ +- struct drm_device *dev = crtc->dev; +- struct drm_crtc_helper_funcs *funcs = crtc->helper_private; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); +- nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); +- +-#ifdef __BIG_ENDIAN +- /* turn on LFB swapping */ +- { +- uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); +- tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); +- NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); +- } +-#endif +- +- funcs->dpms(crtc, DRM_MODE_DPMS_ON); +- drm_vblank_post_modeset(dev, nv_crtc->index); +-} +- +-static void nv_crtc_destroy(struct drm_crtc *crtc) +-{ +- struct nv04_display *disp = nv04_display(crtc->dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- if (!nv_crtc) +- return; +- +- drm_crtc_cleanup(crtc); +- +- if (disp->image[nv_crtc->index]) +- nouveau_bo_unpin(disp->image[nv_crtc->index]); +- nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); +- +- nouveau_bo_unmap(nv_crtc->cursor.nvbo); +- nouveau_bo_unpin(nv_crtc->cursor.nvbo); +- nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); +- kfree(nv_crtc); +-} +- +-static void +-nv_crtc_gamma_load(struct drm_crtc *crtc) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = nv_crtc->base.dev; +- struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; +- int i; +- +- rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; +- for (i = 0; i < 256; i++) { +- rgbs[i].r = nv_crtc->lut.r[i] >> 8; +- rgbs[i].g = nv_crtc->lut.g[i] >> 8; +- rgbs[i].b = nv_crtc->lut.b[i] >> 8; +- } +- +- nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); +-} +- +-static void +-nv_crtc_disable(struct drm_crtc *crtc) +-{ +- struct nv04_display *disp = nv04_display(crtc->dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- if (disp->image[nv_crtc->index]) +- nouveau_bo_unpin(disp->image[nv_crtc->index]); +- nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); +-} +- +-static void +-nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start, +- uint32_t size) +-{ +- int end = (start + size > 256) ? 256 : start + size, i; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- for (i = start; i < end; i++) { +- nv_crtc->lut.r[i] = r[i]; +- nv_crtc->lut.g[i] = g[i]; +- nv_crtc->lut.b[i] = b[i]; +- } +- +- /* We need to know the depth before we upload, but it's possible to +- * get called before a framebuffer is bound. If this is the case, +- * mark the lut values as dirty by setting depth==0, and it'll be +- * uploaded on the first mode_set_base() +- */ +- if (!nv_crtc->base.primary->fb) { +- nv_crtc->lut.depth = 0; +- return; +- } +- +- nv_crtc_gamma_load(crtc); +-} +- +-static int +-nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, +- struct drm_framebuffer *passed_fb, +- int x, int y, bool atomic) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- struct drm_framebuffer *drm_fb; +- struct nouveau_framebuffer *fb; +- int arb_burst, arb_lwm; +- +- NV_DEBUG(drm, "index %d\n", nv_crtc->index); +- +- /* no fb bound */ +- if (!atomic && !crtc->primary->fb) { +- NV_DEBUG(drm, "No FB bound\n"); +- return 0; +- } +- +- /* If atomic, we want to switch to the fb we were passed, so +- * now we update pointers to do that. +- */ +- if (atomic) { +- drm_fb = passed_fb; +- fb = nouveau_framebuffer(passed_fb); +- } else { +- drm_fb = crtc->primary->fb; +- fb = nouveau_framebuffer(crtc->primary->fb); +- } +- +- nv_crtc->fb.offset = fb->nvbo->bo.offset; +- +- if (nv_crtc->lut.depth != drm_fb->depth) { +- nv_crtc->lut.depth = drm_fb->depth; +- nv_crtc_gamma_load(crtc); +- } +- +- /* Update the framebuffer format. */ +- regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; +- regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8; +- regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; +- if (crtc->primary->fb->depth == 16) +- regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); +- NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, +- regp->ramdac_gen_ctrl); +- +- regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; +- regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = +- XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); +- regp->CRTC[NV_CIO_CRE_42] = +- XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); +- crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); +- +- /* Update the framebuffer location. */ +- regp->fb_start = nv_crtc->fb.offset & ~3; +- regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8); +- nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); +- +- /* Update the arbitration parameters. */ +- nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel, +- &arb_burst, &arb_lwm); +- +- regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; +- regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { +- regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); +- } +- +- return 0; +-} +- +-static int +-nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, +- struct drm_framebuffer *old_fb) +-{ +- int ret = nv_crtc_swap_fbs(crtc, old_fb); +- if (ret) +- return ret; +- return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); +-} +- +-static int +-nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, +- struct drm_framebuffer *fb, +- int x, int y, enum mode_set_atomic state) +-{ +- struct nouveau_drm *drm = nouveau_drm(crtc->dev); +- struct drm_device *dev = drm->dev; +- +- if (state == ENTER_ATOMIC_MODE_SET) +- nouveau_fbcon_accel_save_disable(dev); +- else +- nouveau_fbcon_accel_restore(dev); +- +- return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); +-} +- +-static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, +- struct nouveau_bo *dst) +-{ +- int width = nv_cursor_width(dev); +- uint32_t pixel; +- int i, j; +- +- for (i = 0; i < width; i++) { +- for (j = 0; j < width; j++) { +- pixel = nouveau_bo_rd32(src, i*64 + j); +- +- nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 +- | (pixel & 0xf80000) >> 9 +- | (pixel & 0xf800) >> 6 +- | (pixel & 0xf8) >> 3); +- } +- } +-} +- +-static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, +- struct nouveau_bo *dst) +-{ +- uint32_t pixel; +- int alpha, i; +- +- /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha +- * cursors (though NPM in combination with fp dithering may not work on +- * nv11, from "nv" driver history) +- * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the +- * blob uses, however we get given PM cursors so we use PM mode +- */ +- for (i = 0; i < 64 * 64; i++) { +- pixel = nouveau_bo_rd32(src, i); +- +- /* hw gets unhappy if alpha <= rgb values. for a PM image "less +- * than" shouldn't happen; fix "equal to" case by adding one to +- * alpha channel (slightly inaccurate, but so is attempting to +- * get back to NPM images, due to limits of integer precision) +- */ +- alpha = pixel >> 24; +- if (alpha > 0 && alpha < 255) +- pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); +- +-#ifdef __BIG_ENDIAN +- { +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (drm->device.info.chipset == 0x11) { +- pixel = ((pixel & 0x000000ff) << 24) | +- ((pixel & 0x0000ff00) << 8) | +- ((pixel & 0x00ff0000) >> 8) | +- ((pixel & 0xff000000) >> 24); +- } +- } +-#endif +- +- nouveau_bo_wr32(dst, i, pixel); +- } +-} +- +-static int +-nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, +- uint32_t buffer_handle, uint32_t width, uint32_t height) +-{ +- struct nouveau_drm *drm = nouveau_drm(crtc->dev); +- struct drm_device *dev = drm->dev; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nouveau_bo *cursor = NULL; +- struct drm_gem_object *gem; +- int ret = 0; +- +- if (!buffer_handle) { +- nv_crtc->cursor.hide(nv_crtc, true); +- return 0; +- } +- +- if (width != 64 || height != 64) +- return -EINVAL; +- +- gem = drm_gem_object_lookup(dev, file_priv, buffer_handle); +- if (!gem) +- return -ENOENT; +- cursor = nouveau_gem_object(gem); +- +- ret = nouveau_bo_map(cursor); +- if (ret) +- goto out; +- +- if (drm->device.info.chipset >= 0x11) +- nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); +- else +- nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); +- +- nouveau_bo_unmap(cursor); +- nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; +- nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); +- nv_crtc->cursor.show(nv_crtc, true); +-out: +- drm_gem_object_unreference_unlocked(gem); +- return ret; +-} +- +-static int +-nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- nv_crtc->cursor.set_pos(nv_crtc, x, y); +- return 0; +-} +- +-int +-nouveau_crtc_set_config(struct drm_mode_set *set) +-{ +- struct drm_device *dev; +- struct nouveau_drm *drm; +- int ret; +- struct drm_crtc *crtc; +- bool active = false; +- if (!set || !set->crtc) +- return -EINVAL; +- +- dev = set->crtc->dev; +- +- /* get a pm reference here */ +- ret = pm_runtime_get_sync(dev->dev); +- if (ret < 0 && ret != -EACCES) +- return ret; +- +- ret = drm_crtc_helper_set_config(set); +- +- drm = nouveau_drm(dev); +- +- /* if we get here with no crtcs active then we can drop a reference */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- if (crtc->enabled) +- active = true; +- } +- +- pm_runtime_mark_last_busy(dev->dev); +- /* if we have active crtcs and we don't have a power ref, +- take the current one */ +- if (active && !drm->have_disp_power_ref) { +- drm->have_disp_power_ref = true; +- return ret; +- } +- /* if we have no active crtcs, then drop the power ref +- we got before */ +- if (!active && drm->have_disp_power_ref) { +- pm_runtime_put_autosuspend(dev->dev); +- drm->have_disp_power_ref = false; +- } +- /* drop the power reference we got coming in here */ +- pm_runtime_put_autosuspend(dev->dev); +- return ret; +-} +- +-static const struct drm_crtc_funcs nv04_crtc_funcs = { +- .save = nv_crtc_save, +- .restore = nv_crtc_restore, +- .cursor_set = nv04_crtc_cursor_set, +- .cursor_move = nv04_crtc_cursor_move, +- .gamma_set = nv_crtc_gamma_set, +- .set_config = nouveau_crtc_set_config, +- .page_flip = nouveau_crtc_page_flip, +- .destroy = nv_crtc_destroy, +-}; +- +-static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { +- .dpms = nv_crtc_dpms, +- .prepare = nv_crtc_prepare, +- .commit = nv_crtc_commit, +- .mode_fixup = nv_crtc_mode_fixup, +- .mode_set = nv_crtc_mode_set, +- .mode_set_base = nv04_crtc_mode_set_base, +- .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, +- .load_lut = nv_crtc_gamma_load, +- .disable = nv_crtc_disable, +-}; +- +-int +-nv04_crtc_create(struct drm_device *dev, int crtc_num) +-{ +- struct nouveau_crtc *nv_crtc; +- int ret, i; +- +- nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); +- if (!nv_crtc) +- return -ENOMEM; +- +- for (i = 0; i < 256; i++) { +- nv_crtc->lut.r[i] = i << 8; +- nv_crtc->lut.g[i] = i << 8; +- nv_crtc->lut.b[i] = i << 8; +- } +- nv_crtc->lut.depth = 0; +- +- nv_crtc->index = crtc_num; +- nv_crtc->last_dpms = NV_DPMS_CLEARED; +- +- drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs); +- drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); +- drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); +- +- ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM, +- 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo); +- if (!ret) { +- ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); +- if (!ret) { +- ret = nouveau_bo_map(nv_crtc->cursor.nvbo); +- if (ret) +- nouveau_bo_unpin(nv_crtc->cursor.nvbo); +- } +- if (ret) +- nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); +- } +- +- nv04_cursor_init(nv_crtc); +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/cursor.c b/drivers/gpu/drm/nouveau/dispnv04/cursor.c +deleted file mode 100644 +index 4e61173c..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/cursor.c ++++ /dev/null +@@ -1,70 +0,0 @@ +-#include +-#include +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +- +-static void +-nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) +-{ +- nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); +-} +- +-static void +-nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) +-{ +- nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); +-} +- +-static void +-nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) +-{ +- nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; +- NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, +- NV_PRAMDAC_CU_START_POS, +- XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | +- XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); +-} +- +-static void +-crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) +-{ +- NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, +- crtcstate->CRTC[index]); +-} +- +-static void +-nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) +-{ +- struct drm_device *dev = nv_crtc->base.dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- struct drm_crtc *crtc = &nv_crtc->base; +- +- regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = +- MASK(NV_CIO_CRE_HCUR_ASI) | +- XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); +- regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = +- XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); +- if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) +- regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= +- MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); +- regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; +- +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); +- crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- nv_fix_nv40_hw_cursor(dev, nv_crtc->index); +-} +- +-int +-nv04_cursor_init(struct nouveau_crtc *crtc) +-{ +- crtc->cursor.set_offset = nv04_cursor_set_offset; +- crtc->cursor.set_pos = nv04_cursor_set_pos; +- crtc->cursor.hide = nv04_cursor_hide; +- crtc->cursor.show = nv04_cursor_show; +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c +deleted file mode 100644 +index 2d8056cd..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/dac.c ++++ /dev/null +@@ -1,556 +0,0 @@ +-/* +- * Copyright 2003 NVIDIA, Corporation +- * Copyright 2006 Dave Airlie +- * Copyright 2007 Maarten Maathuis +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_encoder.h" +-#include "nouveau_connector.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +-#include "nvreg.h" +- +-#include +-#include +-#include +- +-int nv04_dac_output_offset(struct drm_encoder *encoder) +-{ +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- int offset = 0; +- +- if (dcb->or & (8 | DCB_OUTPUT_C)) +- offset += 0x68; +- if (dcb->or & (8 | DCB_OUTPUT_B)) +- offset += 0x2000; +- +- return offset; +-} +- +-/* +- * arbitrary limit to number of sense oscillations tolerated in one sample +- * period (observed to be at least 13 in "nvidia") +- */ +-#define MAX_HBLANK_OSC 20 +- +-/* +- * arbitrary limit to number of conflicting sample pairs to tolerate at a +- * voltage step (observed to be at least 5 in "nvidia") +- */ +-#define MAX_SAMPLE_PAIRS 10 +- +-static int sample_load_twice(struct drm_device *dev, bool sense[2]) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_timer *ptimer = nvkm_timer(device); +- int i; +- +- for (i = 0; i < 2; i++) { +- bool sense_a, sense_b, sense_b_prime; +- int j = 0; +- +- /* +- * wait for bit 0 clear -- out of hblank -- (say reg value 0x4), +- * then wait for transition 0x4->0x5->0x4: enter hblank, leave +- * hblank again +- * use a 10ms timeout (guards against crtc being inactive, in +- * which case blank state would never change) +- */ +- if (!nouveau_timer_wait_eq(ptimer, 10000000, +- NV_PRMCIO_INP0__COLOR, +- 0x00000001, 0x00000000)) +- return -EBUSY; +- if (!nouveau_timer_wait_eq(ptimer, 10000000, +- NV_PRMCIO_INP0__COLOR, +- 0x00000001, 0x00000001)) +- return -EBUSY; +- if (!nouveau_timer_wait_eq(ptimer, 10000000, +- NV_PRMCIO_INP0__COLOR, +- 0x00000001, 0x00000000)) +- return -EBUSY; +- +- udelay(100); +- /* when level triggers, sense is _LO_ */ +- sense_a = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10; +- +- /* take another reading until it agrees with sense_a... */ +- do { +- udelay(100); +- sense_b = nvif_rd08(device, NV_PRMCIO_INP0) & 0x10; +- if (sense_a != sense_b) { +- sense_b_prime = +- nvif_rd08(device, NV_PRMCIO_INP0) & 0x10; +- if (sense_b == sense_b_prime) { +- /* ... unless two consecutive subsequent +- * samples agree; sense_a is replaced */ +- sense_a = sense_b; +- /* force mis-match so we loop */ +- sense_b = !sense_a; +- } +- } +- } while ((sense_a != sense_b) && ++j < MAX_HBLANK_OSC); +- +- if (j == MAX_HBLANK_OSC) +- /* with so much oscillation, default to sense:LO */ +- sense[i] = false; +- else +- sense[i] = sense_a; +- } +- +- return 0; +-} +- +-static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder, +- struct drm_connector *connector) +-{ +- struct drm_device *dev = encoder->dev; +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode; +- uint8_t saved_palette0[3], saved_palette_mask; +- uint32_t saved_rtest_ctrl, saved_rgen_ctrl; +- int i; +- uint8_t blue; +- bool sense = true; +- +- /* +- * for this detection to work, there needs to be a mode set up on the +- * CRTC. this is presumed to be the case +- */ +- +- if (nv_two_heads(dev)) +- /* only implemented for head A for now */ +- NVSetOwner(dev, 0); +- +- saved_cr_mode = NVReadVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode | 0x80); +- +- saved_seq1 = NVReadVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX); +- NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1 & ~0x20); +- +- saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, +- saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF); +- +- msleep(10); +- +- saved_pi = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, +- saved_pi & ~(0x80 | MASK(NV_CIO_CRE_PIXEL_FORMAT))); +- saved_rpc1 = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1 & ~0xc0); +- +- nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS, 0x0); +- for (i = 0; i < 3; i++) +- saved_palette0[i] = nvif_rd08(device, NV_PRMDIO_PALETTE_DATA); +- saved_palette_mask = nvif_rd08(device, NV_PRMDIO_PIXEL_MASK); +- nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, 0); +- +- saved_rgen_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, +- (saved_rgen_ctrl & ~(NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | +- NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM)) | +- NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON); +- +- blue = 8; /* start of test range */ +- +- do { +- bool sense_pair[2]; +- +- nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); +- nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0); +- nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, 0); +- /* testing blue won't find monochrome monitors. I don't care */ +- nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, blue); +- +- i = 0; +- /* take sample pairs until both samples in the pair agree */ +- do { +- if (sample_load_twice(dev, sense_pair)) +- goto out; +- } while ((sense_pair[0] != sense_pair[1]) && +- ++i < MAX_SAMPLE_PAIRS); +- +- if (i == MAX_SAMPLE_PAIRS) +- /* too much oscillation defaults to LO */ +- sense = false; +- else +- sense = sense_pair[0]; +- +- /* +- * if sense goes LO before blue ramps to 0x18, monitor is not connected. +- * ergo, if blue gets to 0x18, monitor must be connected +- */ +- } while (++blue < 0x18 && sense); +- +-out: +- nvif_wr08(device, NV_PRMDIO_PIXEL_MASK, saved_palette_mask); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_GENERAL_CONTROL, saved_rgen_ctrl); +- nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS, 0); +- for (i = 0; i < 3; i++) +- nvif_wr08(device, NV_PRMDIO_PALETTE_DATA, saved_palette0[i]); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL, saved_rtest_ctrl); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_PIXEL_INDEX, saved_pi); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_RPC1_INDEX, saved_rpc1); +- NVWriteVgaSeq(dev, 0, NV_VIO_SR_CLOCK_INDEX, saved_seq1); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CR_MODE_INDEX, saved_cr_mode); +- +- if (blue == 0x18) { +- NV_DEBUG(drm, "Load detected on head A\n"); +- return connector_status_connected; +- } +- +- return connector_status_disconnected; +-} +- +-uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_gpio *gpio = nvkm_gpio(device); +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); +- uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, +- saved_rtest_ctrl, saved_gpio0 = 0, saved_gpio1 = 0, temp, routput; +- int head; +- +-#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) +- if (dcb->type == DCB_OUTPUT_TV) { +- testval = RGB_TEST_DATA(0xa0, 0xa0, 0xa0); +- +- if (drm->vbios.tvdactestval) +- testval = drm->vbios.tvdactestval; +- } else { +- testval = RGB_TEST_DATA(0x140, 0x140, 0x140); /* 0x94050140 */ +- +- if (drm->vbios.dactestval) +- testval = drm->vbios.dactestval; +- } +- +- saved_rtest_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, +- saved_rtest_ctrl & ~NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF); +- +- saved_powerctrl_2 = nvif_rd32(device, NV_PBUS_POWERCTRL_2); +- +- nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2 & 0xd7ffffff); +- if (regoffset == 0x68) { +- saved_powerctrl_4 = nvif_rd32(device, NV_PBUS_POWERCTRL_4); +- nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); +- } +- +- if (gpio) { +- saved_gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff); +- saved_gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, dcb->type == DCB_OUTPUT_TV); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, dcb->type == DCB_OUTPUT_TV); +- } +- +- msleep(4); +- +- saved_routput = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); +- head = (saved_routput & 0x100) >> 8; +- +- /* if there's a spare crtc, using it will minimise flicker */ +- if (!(NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX) & 0xC0)) +- head ^= 1; +- +- /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */ +- routput = (saved_routput & 0xfffffece) | head << 8; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE) { +- if (dcb->type == DCB_OUTPUT_TV) +- routput |= 0x1a << 16; +- else +- routput &= ~(0x1a << 16); +- } +- +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, routput); +- msleep(1); +- +- temp = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, temp | 1); +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA, +- NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK | testval); +- temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL, +- temp | NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED); +- msleep(5); +- +- sample = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); +- /* do it again just in case it's a residual current */ +- sample &= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); +- +- temp = NVReadRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TEST_CONTROL, +- temp & ~NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TESTPOINT_DATA, 0); +- +- /* bios does something more complex for restoring, but I think this is good enough */ +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, saved_routput); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, saved_rtest_ctrl); +- if (regoffset == 0x68) +- nvif_wr32(device, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); +- nvif_wr32(device, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); +- +- if (gpio) { +- gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, saved_gpio1); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, saved_gpio0); +- } +- +- return sample; +-} +- +-static enum drm_connector_status +-nv17_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) +-{ +- struct nouveau_drm *drm = nouveau_drm(encoder->dev); +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- +- if (nv04_dac_in_use(encoder)) +- return connector_status_disconnected; +- +- if (nv17_dac_sample_load(encoder) & +- NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI) { +- NV_DEBUG(drm, "Load detected on output %c\n", +- '@' + ffs(dcb->or)); +- return connector_status_connected; +- } else { +- return connector_status_disconnected; +- } +-} +- +-static bool nv04_dac_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- if (nv04_dac_in_use(encoder)) +- return false; +- +- return true; +-} +- +-static void nv04_dac_prepare(struct drm_encoder *encoder) +-{ +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- struct drm_device *dev = encoder->dev; +- int head = nouveau_crtc(encoder->crtc)->index; +- +- helper->dpms(encoder, DRM_MODE_DPMS_OFF); +- +- nv04_dfp_disable(dev, head); +-} +- +-static void nv04_dac_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- int head = nouveau_crtc(encoder->crtc)->index; +- +- if (nv_gf4_disp_arch(dev)) { +- struct drm_encoder *rebind; +- uint32_t dac_offset = nv04_dac_output_offset(encoder); +- uint32_t otherdac; +- +- /* bit 16-19 are bits that are set on some G70 cards, +- * but don't seem to have much effect */ +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset, +- head << 8 | NV_PRAMDAC_DACCLK_SEL_DACCLK); +- /* force any other vga encoders to bind to the other crtc */ +- list_for_each_entry(rebind, &dev->mode_config.encoder_list, head) { +- if (rebind == encoder +- || nouveau_encoder(rebind)->dcb->type != DCB_OUTPUT_ANALOG) +- continue; +- +- dac_offset = nv04_dac_output_offset(rebind); +- otherdac = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + dac_offset, +- (otherdac & ~0x0100) | (head ^ 1) << 8); +- } +- } +- +- /* This could use refinement for flatpanels, but it should work this way */ +- if (drm->device.info.chipset < 0x44) +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); +- else +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); +-} +- +-static void nv04_dac_commit(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_drm *drm = nouveau_drm(encoder->dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- +- helper->dpms(encoder, DRM_MODE_DPMS_ON); +- +- NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", +- nouveau_encoder_connector_get(nv_encoder)->base.name, +- nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); +-} +- +-void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable) +-{ +- struct drm_device *dev = encoder->dev; +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- +- if (nv_gf4_disp_arch(dev)) { +- uint32_t *dac_users = &nv04_display(dev)->dac_users[ffs(dcb->or) - 1]; +- int dacclk_off = NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder); +- uint32_t dacclk = NVReadRAMDAC(dev, 0, dacclk_off); +- +- if (enable) { +- *dac_users |= 1 << dcb->index; +- NVWriteRAMDAC(dev, 0, dacclk_off, dacclk | NV_PRAMDAC_DACCLK_SEL_DACCLK); +- +- } else { +- *dac_users &= ~(1 << dcb->index); +- if (!*dac_users) +- NVWriteRAMDAC(dev, 0, dacclk_off, +- dacclk & ~NV_PRAMDAC_DACCLK_SEL_DACCLK); +- } +- } +-} +- +-/* Check if the DAC corresponding to 'encoder' is being used by +- * someone else. */ +-bool nv04_dac_in_use(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- +- return nv_gf4_disp_arch(encoder->dev) && +- (nv04_display(dev)->dac_users[ffs(dcb->or) - 1] & ~(1 << dcb->index)); +-} +- +-static void nv04_dac_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_drm *drm = nouveau_drm(encoder->dev); +- +- if (nv_encoder->last_dpms == mode) +- return; +- nv_encoder->last_dpms = mode; +- +- NV_DEBUG(drm, "Setting dpms mode %d on vga encoder (output %d)\n", +- mode, nv_encoder->dcb->index); +- +- nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); +-} +- +-static void nv04_dac_save(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_device *dev = encoder->dev; +- +- if (nv_gf4_disp_arch(dev)) +- nv_encoder->restore.output = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + +- nv04_dac_output_offset(encoder)); +-} +- +-static void nv04_dac_restore(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_device *dev = encoder->dev; +- +- if (nv_gf4_disp_arch(dev)) +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder), +- nv_encoder->restore.output); +- +- nv_encoder->last_dpms = NV_DPMS_CLEARED; +-} +- +-static void nv04_dac_destroy(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- +- drm_encoder_cleanup(encoder); +- kfree(nv_encoder); +-} +- +-static const struct drm_encoder_helper_funcs nv04_dac_helper_funcs = { +- .dpms = nv04_dac_dpms, +- .save = nv04_dac_save, +- .restore = nv04_dac_restore, +- .mode_fixup = nv04_dac_mode_fixup, +- .prepare = nv04_dac_prepare, +- .commit = nv04_dac_commit, +- .mode_set = nv04_dac_mode_set, +- .detect = nv04_dac_detect +-}; +- +-static const struct drm_encoder_helper_funcs nv17_dac_helper_funcs = { +- .dpms = nv04_dac_dpms, +- .save = nv04_dac_save, +- .restore = nv04_dac_restore, +- .mode_fixup = nv04_dac_mode_fixup, +- .prepare = nv04_dac_prepare, +- .commit = nv04_dac_commit, +- .mode_set = nv04_dac_mode_set, +- .detect = nv17_dac_detect +-}; +- +-static const struct drm_encoder_funcs nv04_dac_funcs = { +- .destroy = nv04_dac_destroy, +-}; +- +-int +-nv04_dac_create(struct drm_connector *connector, struct dcb_output *entry) +-{ +- const struct drm_encoder_helper_funcs *helper; +- struct nouveau_encoder *nv_encoder = NULL; +- struct drm_device *dev = connector->dev; +- struct drm_encoder *encoder; +- +- nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); +- if (!nv_encoder) +- return -ENOMEM; +- +- encoder = to_drm_encoder(nv_encoder); +- +- nv_encoder->dcb = entry; +- nv_encoder->or = ffs(entry->or) - 1; +- +- if (nv_gf4_disp_arch(dev)) +- helper = &nv17_dac_helper_funcs; +- else +- helper = &nv04_dac_helper_funcs; +- +- drm_encoder_init(dev, encoder, &nv04_dac_funcs, DRM_MODE_ENCODER_DAC); +- drm_encoder_helper_add(encoder, helper); +- +- encoder->possible_crtcs = entry->heads; +- encoder->possible_clones = 0; +- +- drm_mode_connector_attach_encoder(connector, encoder); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c +deleted file mode 100644 +index 42a54352..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c ++++ /dev/null +@@ -1,722 +0,0 @@ +-/* +- * Copyright 2003 NVIDIA, Corporation +- * Copyright 2006 Dave Airlie +- * Copyright 2007 Maarten Maathuis +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "nouveau_encoder.h" +-#include "nouveau_connector.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +-#include "nvreg.h" +- +-#include +- +-#include +- +-#define FP_TG_CONTROL_ON (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | \ +- NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | \ +- NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS) +-#define FP_TG_CONTROL_OFF (NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE | \ +- NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE | \ +- NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE) +- +-static inline bool is_fpc_off(uint32_t fpc) +-{ +- return ((fpc & (FP_TG_CONTROL_ON | FP_TG_CONTROL_OFF)) == +- FP_TG_CONTROL_OFF); +-} +- +-int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent) +-{ +- /* special case of nv_read_tmds to find crtc associated with an output. +- * this does not give a correct answer for off-chip dvi, but there's no +- * use for such an answer anyway +- */ +- int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; +- +- NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL, +- NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | 0x4); +- return ((NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA) & 0x8) >> 3) ^ ramdac; +-} +- +-void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent, +- int head, bool dl) +-{ +- /* The BIOS scripts don't do this for us, sadly +- * Luckily we do know the values ;-) +- * +- * head < 0 indicates we wish to force a setting with the overrideval +- * (for VT restore etc.) +- */ +- +- int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; +- uint8_t tmds04 = 0x80; +- +- if (head != ramdac) +- tmds04 = 0x88; +- +- if (dcbent->type == DCB_OUTPUT_LVDS) +- tmds04 |= 0x01; +- +- nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); +- +- if (dl) /* dual link */ +- nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); +-} +- +-void nv04_dfp_disable(struct drm_device *dev, int head) +-{ +- struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; +- +- if (NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL) & +- FP_TG_CONTROL_ON) { +- /* digital remnants must be cleaned before new crtc +- * values programmed. delay is time for the vga stuff +- * to realise it's in control again +- */ +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, +- FP_TG_CONTROL_OFF); +- msleep(50); +- } +- /* don't inadvertently turn it on when state written later */ +- crtcstate[head].fp_control = FP_TG_CONTROL_OFF; +- crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX] &= +- ~NV_CIO_CRE_LCD_ROUTE_MASK; +-} +- +-void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct drm_crtc *crtc; +- struct nouveau_crtc *nv_crtc; +- uint32_t *fpc; +- +- if (mode == DRM_MODE_DPMS_ON) { +- nv_crtc = nouveau_crtc(encoder->crtc); +- fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; +- +- if (is_fpc_off(*fpc)) { +- /* using saved value is ok, as (is_digital && dpms_on && +- * fp_control==OFF) is (at present) *only* true when +- * fpc's most recent change was by below "off" code +- */ +- *fpc = nv_crtc->dpms_saved_fp_control; +- } +- +- nv_crtc->fp_users |= 1 << nouveau_encoder(encoder)->dcb->index; +- NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_FP_TG_CONTROL, *fpc); +- } else { +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- nv_crtc = nouveau_crtc(crtc); +- fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; +- +- nv_crtc->fp_users &= ~(1 << nouveau_encoder(encoder)->dcb->index); +- if (!is_fpc_off(*fpc) && !nv_crtc->fp_users) { +- nv_crtc->dpms_saved_fp_control = *fpc; +- /* cut the FP output */ +- *fpc &= ~FP_TG_CONTROL_ON; +- *fpc |= FP_TG_CONTROL_OFF; +- NVWriteRAMDAC(dev, nv_crtc->index, +- NV_PRAMDAC_FP_TG_CONTROL, *fpc); +- } +- } +- } +-} +- +-static struct drm_encoder *get_tmds_slave(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- struct drm_encoder *slave; +- +- if (dcb->type != DCB_OUTPUT_TMDS || dcb->location == DCB_LOC_ON_CHIP) +- return NULL; +- +- /* Some BIOSes (e.g. the one in a Quadro FX1000) report several +- * TMDS transmitters at the same I2C address, in the same I2C +- * bus. This can still work because in that case one of them is +- * always hard-wired to a reasonable configuration using straps, +- * and the other one needs to be programmed. +- * +- * I don't think there's a way to know which is which, even the +- * blob programs the one exposed via I2C for *both* heads, so +- * let's do the same. +- */ +- list_for_each_entry(slave, &dev->mode_config.encoder_list, head) { +- struct dcb_output *slave_dcb = nouveau_encoder(slave)->dcb; +- +- if (slave_dcb->type == DCB_OUTPUT_TMDS && get_slave_funcs(slave) && +- slave_dcb->tmdsconf.slave_addr == dcb->tmdsconf.slave_addr) +- return slave; +- } +- +- return NULL; +-} +- +-static bool nv04_dfp_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder); +- +- if (!nv_connector->native_mode || +- nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || +- mode->hdisplay > nv_connector->native_mode->hdisplay || +- mode->vdisplay > nv_connector->native_mode->vdisplay) { +- nv_encoder->mode = *adjusted_mode; +- +- } else { +- nv_encoder->mode = *nv_connector->native_mode; +- adjusted_mode->clock = nv_connector->native_mode->clock; +- } +- +- return true; +-} +- +-static void nv04_dfp_prepare_sel_clk(struct drm_device *dev, +- struct nouveau_encoder *nv_encoder, int head) +-{ +- struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; +- uint32_t bits1618 = nv_encoder->dcb->or & DCB_OUTPUT_A ? 0x10000 : 0x40000; +- +- if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP) +- return; +- +- /* SEL_CLK is only used on the primary ramdac +- * It toggles spread spectrum PLL output and sets the bindings of PLLs +- * to heads on digital outputs +- */ +- if (head) +- state->sel_clk |= bits1618; +- else +- state->sel_clk &= ~bits1618; +- +- /* nv30: +- * bit 0 NVClk spread spectrum on/off +- * bit 2 MemClk spread spectrum on/off +- * bit 4 PixClk1 spread spectrum on/off toggle +- * bit 6 PixClk2 spread spectrum on/off toggle +- * +- * nv40 (observations from bios behaviour and mmio traces): +- * bits 4&6 as for nv30 +- * bits 5&7 head dependent as for bits 4&6, but do not appear with 4&6; +- * maybe a different spread mode +- * bits 8&10 seen on dual-link dvi outputs, purpose unknown (set by POST scripts) +- * The logic behind turning spread spectrum on/off in the first place, +- * and which bit-pair to use, is unclear on nv40 (for earlier cards, the fp table +- * entry has the necessary info) +- */ +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && nv04_display(dev)->saved_reg.sel_clk & 0xf0) { +- int shift = (nv04_display(dev)->saved_reg.sel_clk & 0x50) ? 0 : 1; +- +- state->sel_clk &= ~0xf0; +- state->sel_clk |= (head ? 0x40 : 0x10) << shift; +- } +-} +- +-static void nv04_dfp_prepare(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- struct drm_device *dev = encoder->dev; +- int head = nouveau_crtc(encoder->crtc)->index; +- struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; +- uint8_t *cr_lcd = &crtcstate[head].CRTC[NV_CIO_CRE_LCD__INDEX]; +- uint8_t *cr_lcd_oth = &crtcstate[head ^ 1].CRTC[NV_CIO_CRE_LCD__INDEX]; +- +- helper->dpms(encoder, DRM_MODE_DPMS_OFF); +- +- nv04_dfp_prepare_sel_clk(dev, nv_encoder, head); +- +- *cr_lcd = (*cr_lcd & ~NV_CIO_CRE_LCD_ROUTE_MASK) | 0x3; +- +- if (nv_two_heads(dev)) { +- if (nv_encoder->dcb->location == DCB_LOC_ON_CHIP) +- *cr_lcd |= head ? 0x0 : 0x8; +- else { +- *cr_lcd |= (nv_encoder->dcb->or << 4) & 0x30; +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) +- *cr_lcd |= 0x30; +- if ((*cr_lcd & 0x30) == (*cr_lcd_oth & 0x30)) { +- /* avoid being connected to both crtcs */ +- *cr_lcd_oth &= ~0x30; +- NVWriteVgaCrtc(dev, head ^ 1, +- NV_CIO_CRE_LCD__INDEX, +- *cr_lcd_oth); +- } +- } +- } +-} +- +- +-static void nv04_dfp_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; +- struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_display_mode *output_mode = &nv_encoder->mode; +- struct drm_connector *connector = &nv_connector->base; +- uint32_t mode_ratio, panel_ratio; +- +- NV_DEBUG(drm, "Output mode on CRTC %d:\n", nv_crtc->index); +- drm_mode_debug_printmodeline(output_mode); +- +- /* Initialize the FP registers in this CRTC. */ +- regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; +- regp->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; +- if (!nv_gf4_disp_arch(dev) || +- (output_mode->hsync_start - output_mode->hdisplay) >= +- drm->vbios.digital_min_front_porch) +- regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; +- else +- regp->fp_horiz_regs[FP_CRTC] = output_mode->hsync_start - drm->vbios.digital_min_front_porch - 1; +- regp->fp_horiz_regs[FP_SYNC_START] = output_mode->hsync_start - 1; +- regp->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; +- regp->fp_horiz_regs[FP_VALID_START] = output_mode->hskew; +- regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; +- +- regp->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; +- regp->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; +- regp->fp_vert_regs[FP_CRTC] = output_mode->vtotal - 5 - 1; +- regp->fp_vert_regs[FP_SYNC_START] = output_mode->vsync_start - 1; +- regp->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; +- regp->fp_vert_regs[FP_VALID_START] = 0; +- regp->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - 1; +- +- /* bit26: a bit seen on some g7x, no as yet discernable purpose */ +- regp->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | +- (savep->fp_control & (1 << 26 | NV_PRAMDAC_FP_TG_CONTROL_READ_PROG)); +- /* Deal with vsync/hsync polarity */ +- /* LVDS screens do set this, but modes with +ve syncs are very rare */ +- if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) +- regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; +- if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) +- regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; +- /* panel scaling first, as native would get set otherwise */ +- if (nv_connector->scaling_mode == DRM_MODE_SCALE_NONE || +- nv_connector->scaling_mode == DRM_MODE_SCALE_CENTER) /* panel handles it */ +- regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER; +- else if (adjusted_mode->hdisplay == output_mode->hdisplay && +- adjusted_mode->vdisplay == output_mode->vdisplay) /* native mode */ +- regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE; +- else /* gpu needs to scale */ +- regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE; +- if (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT) +- regp->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; +- if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && +- output_mode->clock > 165000) +- regp->fp_control |= (2 << 24); +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) { +- bool duallink = false, dummy; +- if (nv_connector->edid && +- nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { +- duallink = (((u8 *)nv_connector->edid)[121] == 2); +- } else { +- nouveau_bios_parse_lvds_table(dev, output_mode->clock, +- &duallink, &dummy); +- } +- +- if (duallink) +- regp->fp_control |= (8 << 28); +- } else +- if (output_mode->clock > 165000) +- regp->fp_control |= (8 << 28); +- +- regp->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | +- NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | +- NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | +- NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | +- NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | +- NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | +- NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; +- +- /* We want automatic scaling */ +- regp->fp_debug_1 = 0; +- /* This can override HTOTAL and VTOTAL */ +- regp->fp_debug_2 = 0; +- +- /* Use 20.12 fixed point format to avoid floats */ +- mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; +- panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; +- /* if ratios are equal, SCALE_ASPECT will automatically (and correctly) +- * get treated the same as SCALE_FULLSCREEN */ +- if (nv_connector->scaling_mode == DRM_MODE_SCALE_ASPECT && +- mode_ratio != panel_ratio) { +- uint32_t diff, scale; +- bool divide_by_2 = nv_gf4_disp_arch(dev); +- +- if (mode_ratio < panel_ratio) { +- /* vertical needs to expand to glass size (automatic) +- * horizontal needs to be scaled at vertical scale factor +- * to maintain aspect */ +- +- scale = (1 << 12) * adjusted_mode->vdisplay / output_mode->vdisplay; +- regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE | +- XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE); +- +- /* restrict area of screen used, horizontally */ +- diff = output_mode->hdisplay - +- output_mode->vdisplay * mode_ratio / (1 << 12); +- regp->fp_horiz_regs[FP_VALID_START] += diff / 2; +- regp->fp_horiz_regs[FP_VALID_END] -= diff / 2; +- } +- +- if (mode_ratio > panel_ratio) { +- /* horizontal needs to expand to glass size (automatic) +- * vertical needs to be scaled at horizontal scale factor +- * to maintain aspect */ +- +- scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; +- regp->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE | +- XLATE(scale, divide_by_2, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE); +- +- /* restrict area of screen used, vertically */ +- diff = output_mode->vdisplay - +- (1 << 12) * output_mode->hdisplay / mode_ratio; +- regp->fp_vert_regs[FP_VALID_START] += diff / 2; +- regp->fp_vert_regs[FP_VALID_END] -= diff / 2; +- } +- } +- +- /* Output property. */ +- if ((nv_connector->dithering_mode == DITHERING_MODE_ON) || +- (nv_connector->dithering_mode == DITHERING_MODE_AUTO && +- encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) { +- if (drm->device.info.chipset == 0x11) +- regp->dither = savep->dither | 0x00010000; +- else { +- int i; +- regp->dither = savep->dither | 0x00000001; +- for (i = 0; i < 3; i++) { +- regp->dither_regs[i] = 0xe4e4e4e4; +- regp->dither_regs[i + 3] = 0x44444444; +- } +- } +- } else { +- if (drm->device.info.chipset != 0x11) { +- /* reset them */ +- int i; +- for (i = 0; i < 3; i++) { +- regp->dither_regs[i] = savep->dither_regs[i]; +- regp->dither_regs[i + 3] = savep->dither_regs[i + 3]; +- } +- } +- regp->dither = savep->dither; +- } +- +- regp->fp_margin_color = 0; +-} +- +-static void nv04_dfp_commit(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct dcb_output *dcbe = nv_encoder->dcb; +- int head = nouveau_crtc(encoder->crtc)->index; +- struct drm_encoder *slave_encoder; +- +- if (dcbe->type == DCB_OUTPUT_TMDS) +- run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); +- else if (dcbe->type == DCB_OUTPUT_LVDS) +- call_lvds_script(dev, dcbe, head, LVDS_RESET, nv_encoder->mode.clock); +- +- /* update fp_control state for any changes made by scripts, +- * so correct value is written at DPMS on */ +- nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = +- NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); +- +- /* This could use refinement for flatpanels, but it should work this way */ +- if (drm->device.info.chipset < 0x44) +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000); +- else +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); +- +- /* Init external transmitters */ +- slave_encoder = get_tmds_slave(encoder); +- if (slave_encoder) +- get_slave_funcs(slave_encoder)->mode_set( +- slave_encoder, &nv_encoder->mode, &nv_encoder->mode); +- +- helper->dpms(encoder, DRM_MODE_DPMS_ON); +- +- NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", +- nouveau_encoder_connector_get(nv_encoder)->base.name, +- nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); +-} +- +-static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode) +-{ +-#ifdef __powerpc__ +- struct drm_device *dev = encoder->dev; +- struct nvif_device *device = &nouveau_drm(dev)->device; +- +- /* BIOS scripts usually take care of the backlight, thanks +- * Apple for your consistency. +- */ +- if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 || +- dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) { +- if (mode == DRM_MODE_DPMS_ON) { +- nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31); +- nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 1); +- } else { +- nv_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0); +- nv_mask(device, NV_PCRTC_GPIO_EXT, 3, 0); +- } +- } +-#endif +-} +- +-static inline bool is_powersaving_dpms(int mode) +-{ +- return mode != DRM_MODE_DPMS_ON && mode != NV_DPMS_CLEARED; +-} +- +-static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct drm_crtc *crtc = encoder->crtc; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- bool was_powersaving = is_powersaving_dpms(nv_encoder->last_dpms); +- +- if (nv_encoder->last_dpms == mode) +- return; +- nv_encoder->last_dpms = mode; +- +- NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n", +- mode, nv_encoder->dcb->index); +- +- if (was_powersaving && is_powersaving_dpms(mode)) +- return; +- +- if (nv_encoder->dcb->lvdsconf.use_power_scripts) { +- /* when removing an output, crtc may not be set, but PANEL_OFF +- * must still be run +- */ +- int head = crtc ? nouveau_crtc(crtc)->index : +- nv04_dfp_get_bound_head(dev, nv_encoder->dcb); +- +- if (mode == DRM_MODE_DPMS_ON) { +- call_lvds_script(dev, nv_encoder->dcb, head, +- LVDS_PANEL_ON, nv_encoder->mode.clock); +- } else +- /* pxclk of 0 is fine for PANEL_OFF, and for a +- * disconnected LVDS encoder there is no native_mode +- */ +- call_lvds_script(dev, nv_encoder->dcb, head, +- LVDS_PANEL_OFF, 0); +- } +- +- nv04_dfp_update_backlight(encoder, mode); +- nv04_dfp_update_fp_control(encoder, mode); +- +- if (mode == DRM_MODE_DPMS_ON) +- nv04_dfp_prepare_sel_clk(dev, nv_encoder, nouveau_crtc(crtc)->index); +- else { +- nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); +- nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; +- } +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); +-} +- +-static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct nouveau_drm *drm = nouveau_drm(encoder->dev); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- +- if (nv_encoder->last_dpms == mode) +- return; +- nv_encoder->last_dpms = mode; +- +- NV_DEBUG(drm, "Setting dpms mode %d on tmds encoder (output %d)\n", +- mode, nv_encoder->dcb->index); +- +- nv04_dfp_update_backlight(encoder, mode); +- nv04_dfp_update_fp_control(encoder, mode); +-} +- +-static void nv04_dfp_save(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_device *dev = encoder->dev; +- +- if (nv_two_heads(dev)) +- nv_encoder->restore.head = +- nv04_dfp_get_bound_head(dev, nv_encoder->dcb); +-} +- +-static void nv04_dfp_restore(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_device *dev = encoder->dev; +- int head = nv_encoder->restore.head; +- +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) { +- struct nouveau_connector *connector = +- nouveau_encoder_connector_get(nv_encoder); +- +- if (connector && connector->native_mode) +- call_lvds_script(dev, nv_encoder->dcb, head, +- LVDS_PANEL_ON, +- connector->native_mode->clock); +- +- } else if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) { +- int clock = nouveau_hw_pllvals_to_clk +- (&nv04_display(dev)->saved_reg.crtc_reg[head].pllvals); +- +- run_tmds_table(dev, nv_encoder->dcb, head, clock); +- } +- +- nv_encoder->last_dpms = NV_DPMS_CLEARED; +-} +- +-static void nv04_dfp_destroy(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- +- if (get_slave_funcs(encoder)) +- get_slave_funcs(encoder)->destroy(encoder); +- +- drm_encoder_cleanup(encoder); +- kfree(nv_encoder); +-} +- +-static void nv04_tmds_slave_init(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- struct nouveau_i2c_port *port = i2c->find(i2c, 2); +- struct nouveau_i2c_board_info info[] = { +- { +- { +- .type = "sil164", +- .addr = (dcb->tmdsconf.slave_addr == 0x7 ? 0x3a : 0x38), +- .platform_data = &(struct sil164_encoder_params) { +- SIL164_INPUT_EDGE_RISING +- } +- }, 0 +- }, +- { } +- }; +- int type; +- +- if (!nv_gf4_disp_arch(dev) || !port || +- get_tmds_slave(encoder)) +- return; +- +- type = i2c->identify(i2c, 2, "TMDS transmitter", info, NULL, NULL); +- if (type < 0) +- return; +- +- drm_i2c_encoder_init(dev, to_encoder_slave(encoder), +- &port->adapter, &info[type].dev); +-} +- +-static const struct drm_encoder_helper_funcs nv04_lvds_helper_funcs = { +- .dpms = nv04_lvds_dpms, +- .save = nv04_dfp_save, +- .restore = nv04_dfp_restore, +- .mode_fixup = nv04_dfp_mode_fixup, +- .prepare = nv04_dfp_prepare, +- .commit = nv04_dfp_commit, +- .mode_set = nv04_dfp_mode_set, +- .detect = NULL, +-}; +- +-static const struct drm_encoder_helper_funcs nv04_tmds_helper_funcs = { +- .dpms = nv04_tmds_dpms, +- .save = nv04_dfp_save, +- .restore = nv04_dfp_restore, +- .mode_fixup = nv04_dfp_mode_fixup, +- .prepare = nv04_dfp_prepare, +- .commit = nv04_dfp_commit, +- .mode_set = nv04_dfp_mode_set, +- .detect = NULL, +-}; +- +-static const struct drm_encoder_funcs nv04_dfp_funcs = { +- .destroy = nv04_dfp_destroy, +-}; +- +-int +-nv04_dfp_create(struct drm_connector *connector, struct dcb_output *entry) +-{ +- const struct drm_encoder_helper_funcs *helper; +- struct nouveau_encoder *nv_encoder = NULL; +- struct drm_encoder *encoder; +- int type; +- +- switch (entry->type) { +- case DCB_OUTPUT_TMDS: +- type = DRM_MODE_ENCODER_TMDS; +- helper = &nv04_tmds_helper_funcs; +- break; +- case DCB_OUTPUT_LVDS: +- type = DRM_MODE_ENCODER_LVDS; +- helper = &nv04_lvds_helper_funcs; +- break; +- default: +- return -EINVAL; +- } +- +- nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); +- if (!nv_encoder) +- return -ENOMEM; +- +- encoder = to_drm_encoder(nv_encoder); +- +- nv_encoder->dcb = entry; +- nv_encoder->or = ffs(entry->or) - 1; +- +- drm_encoder_init(connector->dev, encoder, &nv04_dfp_funcs, type); +- drm_encoder_helper_add(encoder, helper); +- +- encoder->possible_crtcs = entry->heads; +- encoder->possible_clones = 0; +- +- if (entry->type == DCB_OUTPUT_TMDS && +- entry->location != DCB_LOC_ON_CHIP) +- nv04_tmds_slave_init(encoder); +- +- drm_mode_connector_attach_encoder(connector, encoder); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c +deleted file mode 100644 +index 3d0afa1c..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c ++++ /dev/null +@@ -1,208 +0,0 @@ +-/* +- * Copyright 2009 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Author: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "hw.h" +-#include "nouveau_encoder.h" +-#include "nouveau_connector.h" +- +-int +-nv04_display_early_init(struct drm_device *dev) +-{ +- /* ensure vblank interrupts are off, they can't be enabled until +- * drm_vblank has been initialised +- */ +- NVWriteCRTC(dev, 0, NV_PCRTC_INTR_EN_0, 0); +- if (nv_two_heads(dev)) +- NVWriteCRTC(dev, 1, NV_PCRTC_INTR_EN_0, 0); +- +- return 0; +-} +- +-void +-nv04_display_late_takedown(struct drm_device *dev) +-{ +-} +- +-int +-nv04_display_create(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- struct dcb_table *dcb = &drm->vbios.dcb; +- struct drm_connector *connector, *ct; +- struct drm_encoder *encoder; +- struct drm_crtc *crtc; +- struct nv04_display *disp; +- int i, ret; +- +- disp = kzalloc(sizeof(*disp), GFP_KERNEL); +- if (!disp) +- return -ENOMEM; +- +- nvif_object_map(nvif_object(&drm->device)); +- +- nouveau_display(dev)->priv = disp; +- nouveau_display(dev)->dtor = nv04_display_destroy; +- nouveau_display(dev)->init = nv04_display_init; +- nouveau_display(dev)->fini = nv04_display_fini; +- +- nouveau_hw_save_vga_fonts(dev, 1); +- +- nv04_crtc_create(dev, 0); +- if (nv_two_heads(dev)) +- nv04_crtc_create(dev, 1); +- +- for (i = 0; i < dcb->entries; i++) { +- struct dcb_output *dcbent = &dcb->entry[i]; +- +- connector = nouveau_connector_create(dev, dcbent->connector); +- if (IS_ERR(connector)) +- continue; +- +- switch (dcbent->type) { +- case DCB_OUTPUT_ANALOG: +- ret = nv04_dac_create(connector, dcbent); +- break; +- case DCB_OUTPUT_LVDS: +- case DCB_OUTPUT_TMDS: +- ret = nv04_dfp_create(connector, dcbent); +- break; +- case DCB_OUTPUT_TV: +- if (dcbent->location == DCB_LOC_ON_CHIP) +- ret = nv17_tv_create(connector, dcbent); +- else +- ret = nv04_tv_create(connector, dcbent); +- break; +- default: +- NV_WARN(drm, "DCB type %d not known\n", dcbent->type); +- continue; +- } +- +- if (ret) +- continue; +- } +- +- list_for_each_entry_safe(connector, ct, +- &dev->mode_config.connector_list, head) { +- if (!connector->encoder_ids[0]) { +- NV_WARN(drm, "%s has no encoders, removing\n", +- connector->name); +- connector->funcs->destroy(connector); +- } +- } +- +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- nv_encoder->i2c = i2c->find(i2c, nv_encoder->dcb->i2c_index); +- } +- +- /* Save previous state */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) +- crtc->funcs->save(crtc); +- +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- struct drm_encoder_helper_funcs *func = encoder->helper_private; +- +- func->save(encoder); +- } +- +- nouveau_overlay_init(dev); +- +- return 0; +-} +- +-void +-nv04_display_destroy(struct drm_device *dev) +-{ +- struct nv04_display *disp = nv04_display(dev); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_encoder *encoder; +- struct drm_crtc *crtc; +- +- /* Turn every CRTC off. */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct drm_mode_set modeset = { +- .crtc = crtc, +- }; +- +- drm_mode_set_config_internal(&modeset); +- } +- +- /* Restore state */ +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- struct drm_encoder_helper_funcs *func = encoder->helper_private; +- +- func->restore(encoder); +- } +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) +- crtc->funcs->restore(crtc); +- +- nouveau_hw_save_vga_fonts(dev, 0); +- +- nouveau_display(dev)->priv = NULL; +- kfree(disp); +- +- nvif_object_unmap(nvif_object(&drm->device)); +-} +- +-int +-nv04_display_init(struct drm_device *dev) +-{ +- struct drm_encoder *encoder; +- struct drm_crtc *crtc; +- +- /* meh.. modeset apparently doesn't setup all the regs and depends +- * on pre-existing state, for now load the state of the card *before* +- * nouveau was loaded, and then do a modeset. +- * +- * best thing to do probably is to make save/restore routines not +- * save/restore "pre-load" state, but more general so we can save +- * on suspend too. +- */ +- list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { +- struct drm_encoder_helper_funcs *func = encoder->helper_private; +- +- func->restore(encoder); +- } +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) +- crtc->funcs->restore(crtc); +- +- return 0; +-} +- +-void +-nv04_display_fini(struct drm_device *dev) +-{ +- /* disable vblank interrupts */ +- NVWriteCRTC(dev, 0, NV_PCRTC_INTR_EN_0, 0); +- if (nv_two_heads(dev)) +- NVWriteCRTC(dev, 1, NV_PCRTC_INTR_EN_0, 0); +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h +deleted file mode 100644 +index 17b899d9..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h ++++ /dev/null +@@ -1,188 +0,0 @@ +-#ifndef __NV04_DISPLAY_H__ +-#define __NV04_DISPLAY_H__ +- +-#include +- +-#include "nouveau_display.h" +- +-enum nv04_fp_display_regs { +- FP_DISPLAY_END, +- FP_TOTAL, +- FP_CRTC, +- FP_SYNC_START, +- FP_SYNC_END, +- FP_VALID_START, +- FP_VALID_END +-}; +- +-struct nv04_crtc_reg { +- unsigned char MiscOutReg; +- uint8_t CRTC[0xa0]; +- uint8_t CR58[0x10]; +- uint8_t Sequencer[5]; +- uint8_t Graphics[9]; +- uint8_t Attribute[21]; +- unsigned char DAC[768]; +- +- /* PCRTC regs */ +- uint32_t fb_start; +- uint32_t crtc_cfg; +- uint32_t cursor_cfg; +- uint32_t gpio_ext; +- uint32_t crtc_830; +- uint32_t crtc_834; +- uint32_t crtc_850; +- uint32_t crtc_eng_ctrl; +- +- /* PRAMDAC regs */ +- uint32_t nv10_cursync; +- struct nouveau_pll_vals pllvals; +- uint32_t ramdac_gen_ctrl; +- uint32_t ramdac_630; +- uint32_t ramdac_634; +- uint32_t tv_setup; +- uint32_t tv_vtotal; +- uint32_t tv_vskew; +- uint32_t tv_vsync_delay; +- uint32_t tv_htotal; +- uint32_t tv_hskew; +- uint32_t tv_hsync_delay; +- uint32_t tv_hsync_delay2; +- uint32_t fp_horiz_regs[7]; +- uint32_t fp_vert_regs[7]; +- uint32_t dither; +- uint32_t fp_control; +- uint32_t dither_regs[6]; +- uint32_t fp_debug_0; +- uint32_t fp_debug_1; +- uint32_t fp_debug_2; +- uint32_t fp_margin_color; +- uint32_t ramdac_8c0; +- uint32_t ramdac_a20; +- uint32_t ramdac_a24; +- uint32_t ramdac_a34; +- uint32_t ctv_regs[38]; +-}; +- +-struct nv04_output_reg { +- uint32_t output; +- int head; +-}; +- +-struct nv04_mode_state { +- struct nv04_crtc_reg crtc_reg[2]; +- uint32_t pllsel; +- uint32_t sel_clk; +-}; +- +-struct nv04_display { +- struct nv04_mode_state mode_reg; +- struct nv04_mode_state saved_reg; +- uint32_t saved_vga_font[4][16384]; +- uint32_t dac_users[4]; +- struct nouveau_bo *image[2]; +-}; +- +-static inline struct nv04_display * +-nv04_display(struct drm_device *dev) +-{ +- return nouveau_display(dev)->priv; +-} +- +-/* nv04_display.c */ +-int nv04_display_early_init(struct drm_device *); +-void nv04_display_late_takedown(struct drm_device *); +-int nv04_display_create(struct drm_device *); +-void nv04_display_destroy(struct drm_device *); +-int nv04_display_init(struct drm_device *); +-void nv04_display_fini(struct drm_device *); +- +-/* nv04_crtc.c */ +-int nv04_crtc_create(struct drm_device *, int index); +- +-/* nv04_dac.c */ +-int nv04_dac_create(struct drm_connector *, struct dcb_output *); +-uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); +-int nv04_dac_output_offset(struct drm_encoder *encoder); +-void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); +-bool nv04_dac_in_use(struct drm_encoder *encoder); +- +-/* nv04_dfp.c */ +-int nv04_dfp_create(struct drm_connector *, struct dcb_output *); +-int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_output *dcbent); +-void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_output *dcbent, +- int head, bool dl); +-void nv04_dfp_disable(struct drm_device *dev, int head); +-void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); +- +-/* nv04_tv.c */ +-int nv04_tv_identify(struct drm_device *dev, int i2c_index); +-int nv04_tv_create(struct drm_connector *, struct dcb_output *); +- +-/* nv17_tv.c */ +-int nv17_tv_create(struct drm_connector *, struct dcb_output *); +- +-/* overlay.c */ +-void nouveau_overlay_init(struct drm_device *dev); +- +-static inline bool +-nv_two_heads(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- const int impl = dev->pdev->device & 0x0ff0; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 && +- impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) +- return true; +- +- return false; +-} +- +-static inline bool +-nv_gf4_disp_arch(struct drm_device *dev) +-{ +- return nv_two_heads(dev) && (dev->pdev->device & 0x0ff0) != 0x0110; +-} +- +-static inline bool +-nv_two_reg_pll(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- const int impl = dev->pdev->device & 0x0ff0; +- +- if (impl == 0x0310 || impl == 0x0340 || drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE) +- return true; +- return false; +-} +- +-static inline bool +-nv_match_device(struct drm_device *dev, unsigned device, +- unsigned sub_vendor, unsigned sub_device) +-{ +- return dev->pdev->device == device && +- dev->pdev->subsystem_vendor == sub_vendor && +- dev->pdev->subsystem_device == sub_device; +-} +- +-#include +-#include +- +-static inline void +-nouveau_bios_run_init_table(struct drm_device *dev, u16 table, +- struct dcb_output *outp, int crtc) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_bios *bios = nvkm_bios(&drm->device); +- struct nvbios_init init = { +- .subdev = nv_subdev(bios), +- .bios = bios, +- .offset = table, +- .outp = outp, +- .crtc = crtc, +- .execute = 1, +- }; +- +- nvbios_exec(&init); +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c +deleted file mode 100644 +index 3d4c1930..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c ++++ /dev/null +@@ -1,825 +0,0 @@ +-/* +- * Copyright 2006 Dave Airlie +- * Copyright 2007 Maarten Maathuis +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#include +-#include "nouveau_drm.h" +-#include "hw.h" +- +-#include +- +-#define CHIPSET_NFORCE 0x01a0 +-#define CHIPSET_NFORCE2 0x01f0 +- +-/* +- * misc hw access wrappers/control functions +- */ +- +-void +-NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value) +-{ +- NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); +- NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value); +-} +- +-uint8_t +-NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index) +-{ +- NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index); +- return NVReadPRMVIO(dev, head, NV_PRMVIO_SR); +-} +- +-void +-NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value) +-{ +- NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); +- NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value); +-} +- +-uint8_t +-NVReadVgaGr(struct drm_device *dev, int head, uint8_t index) +-{ +- NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index); +- return NVReadPRMVIO(dev, head, NV_PRMVIO_GX); +-} +- +-/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied) +- * it affects only the 8 bit vga io regs, which we access using mmio at +- * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d* +- * in general, the set value of cr44 does not matter: reg access works as +- * expected and values can be set for the appropriate head by using a 0x2000 +- * offset as required +- * however: +- * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and +- * cr44 must be set to 0 or 3 for accessing values on the correct head +- * through the common 0xc03c* addresses +- * b) in tied mode (4) head B is programmed to the values set on head A, and +- * access using the head B addresses can have strange results, ergo we leave +- * tied mode in init once we know to what cr44 should be restored on exit +- * +- * the owner parameter is slightly abused: +- * 0 and 1 are treated as head values and so the set value is (owner * 3) +- * other values are treated as literal values to set +- */ +-void +-NVSetOwner(struct drm_device *dev, int owner) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (owner == 1) +- owner *= 3; +- +- if (drm->device.info.chipset == 0x11) { +- /* This might seem stupid, but the blob does it and +- * omitting it often locks the system up. +- */ +- NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); +- NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX); +- } +- +- /* CR44 is always changed on CRTC0 */ +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner); +- +- if (drm->device.info.chipset == 0x11) { /* set me harder */ +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner); +- } +-} +- +-void +-NVBlankScreen(struct drm_device *dev, int head, bool blank) +-{ +- unsigned char seq1; +- +- if (nv_two_heads(dev)) +- NVSetOwner(dev, head); +- +- seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); +- +- NVVgaSeqReset(dev, head, true); +- if (blank) +- NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); +- else +- NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); +- NVVgaSeqReset(dev, head, false); +-} +- +-/* +- * PLL getting +- */ +- +-static void +-nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, +- uint32_t pll2, struct nouveau_pll_vals *pllvals) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */ +- +- /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */ +- pllvals->log2P = (pll1 >> 16) & 0x7; +- pllvals->N2 = pllvals->M2 = 1; +- +- if (reg1 <= 0x405c) { +- pllvals->NM1 = pll2 & 0xffff; +- /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */ +- if (!(pll1 & 0x1100)) +- pllvals->NM2 = pll2 >> 16; +- } else { +- pllvals->NM1 = pll1 & 0xffff; +- if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) +- pllvals->NM2 = pll2 & 0xffff; +- else if (drm->device.info.chipset == 0x30 || drm->device.info.chipset == 0x35) { +- pllvals->M1 &= 0xf; /* only 4 bits */ +- if (pll1 & NV30_RAMDAC_ENABLE_VCO2) { +- pllvals->M2 = (pll1 >> 4) & 0x7; +- pllvals->N2 = ((pll1 >> 21) & 0x18) | +- ((pll1 >> 19) & 0x7); +- } +- } +- } +-} +- +-int +-nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype, +- struct nouveau_pll_vals *pllvals) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nouveau_bios *bios = nvkm_bios(device); +- uint32_t reg1, pll1, pll2 = 0; +- struct nvbios_pll pll_lim; +- int ret; +- +- ret = nvbios_pll_parse(bios, plltype, &pll_lim); +- if (ret || !(reg1 = pll_lim.reg)) +- return -ENOENT; +- +- pll1 = nvif_rd32(device, reg1); +- if (reg1 <= 0x405c) +- pll2 = nvif_rd32(device, reg1 + 4); +- else if (nv_two_reg_pll(dev)) { +- uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); +- +- pll2 = nvif_rd32(device, reg2); +- } +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { +- uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580); +- +- /* check whether vpll has been forced into single stage mode */ +- if (reg1 == NV_PRAMDAC_VPLL_COEFF) { +- if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE) +- pll2 = 0; +- } else +- if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE) +- pll2 = 0; +- } +- +- nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); +- pllvals->refclk = pll_lim.refclk; +- return 0; +-} +- +-int +-nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv) +-{ +- /* Avoid divide by zero if called at an inappropriate time */ +- if (!pv->M1 || !pv->M2) +- return 0; +- +- return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P; +-} +- +-int +-nouveau_hw_get_clock(struct drm_device *dev, enum nvbios_pll_type plltype) +-{ +- struct nouveau_pll_vals pllvals; +- int ret; +- +- if (plltype == PLL_MEMORY && +- (dev->pdev->device & 0x0ff0) == CHIPSET_NFORCE) { +- uint32_t mpllP; +- +- pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); +- if (!mpllP) +- mpllP = 4; +- +- return 400000 / mpllP; +- } else +- if (plltype == PLL_MEMORY && +- (dev->pdev->device & 0xff0) == CHIPSET_NFORCE2) { +- uint32_t clock; +- +- pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); +- return clock; +- } +- +- ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); +- if (ret) +- return ret; +- +- return nouveau_hw_pllvals_to_clk(&pllvals); +-} +- +-static void +-nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head) +-{ +- /* the vpll on an unused head can come up with a random value, way +- * beyond the pll limits. for some reason this causes the chip to +- * lock up when reading the dac palette regs, so set a valid pll here +- * when such a condition detected. only seen on nv11 to date +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nouveau_clock *clk = nvkm_clock(device); +- struct nouveau_bios *bios = nvkm_bios(device); +- struct nvbios_pll pll_lim; +- struct nouveau_pll_vals pv; +- enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; +- +- if (nvbios_pll_parse(bios, pll, &pll_lim)) +- return; +- nouveau_hw_get_pllvals(dev, pll, &pv); +- +- if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m && +- pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n && +- pv.log2P <= pll_lim.max_p) +- return; +- +- NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); +- +- /* set lowest clock within static limits */ +- pv.M1 = pll_lim.vco1.max_m; +- pv.N1 = pll_lim.vco1.min_n; +- pv.log2P = pll_lim.max_p_usable; +- clk->pll_prog(clk, pll_lim.reg, &pv); +-} +- +-/* +- * vga font save/restore +- */ +- +-static void nouveau_vga_font_io(struct drm_device *dev, +- void __iomem *iovram, +- bool save, unsigned plane) +-{ +- unsigned i; +- +- NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane); +- NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane); +- for (i = 0; i < 16384; i++) { +- if (save) { +- nv04_display(dev)->saved_vga_font[plane][i] = +- ioread32_native(iovram + i * 4); +- } else { +- iowrite32_native(nv04_display(dev)->saved_vga_font[plane][i], +- iovram + i * 4); +- } +- } +-} +- +-void +-nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t misc, gr4, gr5, gr6, seq2, seq4; +- bool graphicsmode; +- unsigned plane; +- void __iomem *iovram; +- +- if (nv_two_heads(dev)) +- NVSetOwner(dev, 0); +- +- NVSetEnablePalette(dev, 0, true); +- graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1; +- NVSetEnablePalette(dev, 0, false); +- +- if (graphicsmode) /* graphics mode => framebuffer => no need to save */ +- return; +- +- NV_INFO(drm, "%sing VGA fonts\n", save ? "Sav" : "Restor"); +- +- /* map first 64KiB of VRAM, holds VGA fonts etc */ +- iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536); +- if (!iovram) { +- NV_ERROR(drm, "Failed to map VRAM, " +- "cannot save/restore VGA fonts.\n"); +- return; +- } +- +- if (nv_two_heads(dev)) +- NVBlankScreen(dev, 1, true); +- NVBlankScreen(dev, 0, true); +- +- /* save control regs */ +- misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ); +- seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX); +- seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX); +- gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX); +- gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX); +- gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX); +- +- NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67); +- NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6); +- NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0); +- NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5); +- +- /* store font in planes 0..3 */ +- for (plane = 0; plane < 4; plane++) +- nouveau_vga_font_io(dev, iovram, save, plane); +- +- /* restore control regs */ +- NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc); +- NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4); +- NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5); +- NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6); +- NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2); +- NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4); +- +- if (nv_two_heads(dev)) +- NVBlankScreen(dev, 1, false); +- NVBlankScreen(dev, 0, false); +- +- iounmap(iovram); +-} +- +-/* +- * mode state save/load +- */ +- +-static void +-rd_cio_state(struct drm_device *dev, int head, +- struct nv04_crtc_reg *crtcstate, int index) +-{ +- crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index); +-} +- +-static void +-wr_cio_state(struct drm_device *dev, int head, +- struct nv04_crtc_reg *crtcstate, int index) +-{ +- NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]); +-} +- +-static void +-nv_save_state_ramdac(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nv04_crtc_reg *regp = &state->crtc_reg[head]; +- int i; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) +- regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC); +- +- nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals); +- state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT); +- if (nv_two_heads(dev)) +- state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); +- if (drm->device.info.chipset == 0x11) +- regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11); +- +- regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL); +- +- if (nv_gf4_disp_arch(dev)) +- regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630); +- if (drm->device.info.chipset >= 0x30) +- regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634); +- +- regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP); +- regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL); +- regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW); +- regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY); +- regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL); +- regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW); +- regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY); +- regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2); +- +- for (i = 0; i < 7; i++) { +- uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); +- regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg); +- regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20); +- } +- +- if (nv_gf4_disp_arch(dev)) { +- regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER); +- for (i = 0; i < 3; i++) { +- regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4); +- regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4); +- } +- } +- +- regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); +- regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0); +- if (!nv_gf4_disp_arch(dev) && head == 0) { +- /* early chips don't allow access to PRAMDAC_TMDS_* without +- * the head A FPCLK on (nv11 even locks up) */ +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 & +- ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK); +- } +- regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1); +- regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2); +- +- regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR); +- +- if (nv_gf4_disp_arch(dev)) +- regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0); +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { +- regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20); +- regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24); +- regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34); +- +- for (i = 0; i < 38; i++) +- regp->ctv_regs[i] = NVReadRAMDAC(dev, head, +- NV_PRAMDAC_CTV + 4*i); +- } +-} +- +-static void +-nv_load_state_ramdac(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_clock *clk = nvkm_clock(&drm->device); +- struct nv04_crtc_reg *regp = &state->crtc_reg[head]; +- uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; +- int i; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) +- NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync); +- +- clk->pll_prog(clk, pllreg, ®p->pllvals); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); +- if (nv_two_heads(dev)) +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk); +- if (drm->device.info.chipset == 0x11) +- NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither); +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); +- +- if (nv_gf4_disp_arch(dev)) +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630); +- if (drm->device.info.chipset >= 0x30) +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634); +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2); +- +- for (i = 0; i < 7; i++) { +- uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4); +- +- NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]); +- NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]); +- } +- +- if (nv_gf4_disp_arch(dev)) { +- NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither); +- for (i = 0; i < 3; i++) { +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]); +- } +- } +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2); +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color); +- +- if (nv_gf4_disp_arch(dev)) +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0); +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34); +- +- for (i = 0; i < 38; i++) +- NVWriteRAMDAC(dev, head, +- NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]); +- } +-} +- +-static void +-nv_save_state_vga(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nv04_crtc_reg *regp = &state->crtc_reg[head]; +- int i; +- +- regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ); +- +- for (i = 0; i < 25; i++) +- rd_cio_state(dev, head, regp, i); +- +- NVSetEnablePalette(dev, head, true); +- for (i = 0; i < 21; i++) +- regp->Attribute[i] = NVReadVgaAttr(dev, head, i); +- NVSetEnablePalette(dev, head, false); +- +- for (i = 0; i < 9; i++) +- regp->Graphics[i] = NVReadVgaGr(dev, head, i); +- +- for (i = 0; i < 5; i++) +- regp->Sequencer[i] = NVReadVgaSeq(dev, head, i); +-} +- +-static void +-nv_load_state_vga(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nv04_crtc_reg *regp = &state->crtc_reg[head]; +- int i; +- +- NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg); +- +- for (i = 0; i < 5; i++) +- NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]); +- +- nv_lock_vga_crtc_base(dev, head, false); +- for (i = 0; i < 25; i++) +- wr_cio_state(dev, head, regp, i); +- nv_lock_vga_crtc_base(dev, head, true); +- +- for (i = 0; i < 9; i++) +- NVWriteVgaGr(dev, head, i, regp->Graphics[i]); +- +- NVSetEnablePalette(dev, head, true); +- for (i = 0; i < 21; i++) +- NVWriteVgaAttr(dev, head, i, regp->Attribute[i]); +- NVSetEnablePalette(dev, head, false); +-} +- +-static void +-nv_save_state_ext(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nv04_crtc_reg *regp = &state->crtc_reg[head]; +- int i; +- +- rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); +- +- rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_21); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) +- rd_cio_state(dev, head, regp, NV_CIO_CRE_47); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) +- rd_cio_state(dev, head, regp, 0x9f); +- +- rd_cio_state(dev, head, regp, NV_CIO_CRE_49); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { +- regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830); +- regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) +- regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT); +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850); +- +- if (nv_two_heads(dev)) +- regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL); +- regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG); +- } +- +- regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG); +- +- rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { +- rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_4B); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); +- } +- /* NV11 and NV20 don't have this, they stop at 0x52. */ +- if (nv_gf4_disp_arch(dev)) { +- rd_cio_state(dev, head, regp, NV_CIO_CRE_42); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_53); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_54); +- +- for (i = 0; i < 0x10; i++) +- regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_59); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_5B); +- +- rd_cio_state(dev, head, regp, NV_CIO_CRE_85); +- rd_cio_state(dev, head, regp, NV_CIO_CRE_86); +- } +- +- regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START); +-} +- +-static void +-nv_load_state_ext(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nouveau_timer *ptimer = nvkm_timer(device); +- struct nv04_crtc_reg *regp = &state->crtc_reg[head]; +- uint32_t reg900; +- int i; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { +- if (nv_two_heads(dev)) +- /* setting ENGINE_CTRL (EC) *must* come before +- * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in +- * EC that should not be overwritten by writing stale EC +- */ +- NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl); +- +- nvif_wr32(device, NV_PVIDEO_STOP, 1); +- nvif_wr32(device, NV_PVIDEO_INTR_EN, 0); +- nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0); +- nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0); +- nvif_wr32(device, NV_PVIDEO_LIMIT(0), device->info.ram_size - 1); +- nvif_wr32(device, NV_PVIDEO_LIMIT(1), device->info.ram_size - 1); +- nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), device->info.ram_size - 1); +- nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), device->info.ram_size - 1); +- nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); +- +- NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg); +- NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830); +- NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) +- NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext); +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) { +- NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850); +- +- reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900); +- if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC) +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000); +- else +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000); +- } +- } +- +- NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg); +- +- wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) +- wr_cio_state(dev, head, regp, NV_CIO_CRE_47); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) +- wr_cio_state(dev, head, regp, 0x9f); +- +- wr_cio_state(dev, head, regp, NV_CIO_CRE_49); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- nv_fix_nv40_hw_cursor(dev, head); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX); +- +- wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX); +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { +- wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); +- } +- /* NV11 and NV20 stop at 0x52. */ +- if (nv_gf4_disp_arch(dev)) { +- if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { +- /* Not waiting for vertical retrace before modifying +- CRE_53/CRE_54 causes lockups. */ +- nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); +- nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); +- } +- +- wr_cio_state(dev, head, regp, NV_CIO_CRE_42); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_53); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_54); +- +- for (i = 0; i < 0x10; i++) +- NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_59); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_5B); +- +- wr_cio_state(dev, head, regp, NV_CIO_CRE_85); +- wr_cio_state(dev, head, regp, NV_CIO_CRE_86); +- } +- +- NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start); +-} +- +-static void +-nv_save_state_palette(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- int head_offset = head * NV_PRMDIO_SIZE, i; +- +- nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, +- NV_PRMDIO_PIXEL_MASK_MASK); +- nvif_wr08(device, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0); +- +- for (i = 0; i < 768; i++) { +- state->crtc_reg[head].DAC[i] = nvif_rd08(device, +- NV_PRMDIO_PALETTE_DATA + head_offset); +- } +- +- NVSetEnablePalette(dev, head, false); +-} +- +-void +-nouveau_hw_load_state_palette(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- int head_offset = head * NV_PRMDIO_SIZE, i; +- +- nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset, +- NV_PRMDIO_PIXEL_MASK_MASK); +- nvif_wr08(device, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0); +- +- for (i = 0; i < 768; i++) { +- nvif_wr08(device, NV_PRMDIO_PALETTE_DATA + head_offset, +- state->crtc_reg[head].DAC[i]); +- } +- +- NVSetEnablePalette(dev, head, false); +-} +- +-void nouveau_hw_save_state(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (drm->device.info.chipset == 0x11) +- /* NB: no attempt is made to restore the bad pll later on */ +- nouveau_hw_fix_bad_vpll(dev, head); +- nv_save_state_ramdac(dev, head, state); +- nv_save_state_vga(dev, head, state); +- nv_save_state_palette(dev, head, state); +- nv_save_state_ext(dev, head, state); +-} +- +-void nouveau_hw_load_state(struct drm_device *dev, int head, +- struct nv04_mode_state *state) +-{ +- NVVgaProtect(dev, head, true); +- nv_load_state_ramdac(dev, head, state); +- nv_load_state_ext(dev, head, state); +- nouveau_hw_load_state_palette(dev, head, state); +- nv_load_state_vga(dev, head, state); +- NVVgaProtect(dev, head, false); +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.h b/drivers/gpu/drm/nouveau/dispnv04/hw.h +deleted file mode 100644 +index 7f53c571..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/hw.h ++++ /dev/null +@@ -1,409 +0,0 @@ +-/* +- * Copyright 2008 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#ifndef __NOUVEAU_HW_H__ +-#define __NOUVEAU_HW_H__ +- +-#include +-#include "disp.h" +-#include "nvreg.h" +- +-#include +- +-#define MASK(field) ( \ +- (0xffffffff >> (31 - ((1 ? field) - (0 ? field)))) << (0 ? field)) +- +-#define XLATE(src, srclowbit, outfield) ( \ +- (((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield)) +- +-void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value); +-uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index); +-void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value); +-uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index); +-void NVSetOwner(struct drm_device *, int owner); +-void NVBlankScreen(struct drm_device *, int head, bool blank); +-int nouveau_hw_get_pllvals(struct drm_device *, enum nvbios_pll_type plltype, +- struct nouveau_pll_vals *pllvals); +-int nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pllvals); +-int nouveau_hw_get_clock(struct drm_device *, enum nvbios_pll_type plltype); +-void nouveau_hw_save_vga_fonts(struct drm_device *, bool save); +-void nouveau_hw_save_state(struct drm_device *, int head, +- struct nv04_mode_state *state); +-void nouveau_hw_load_state(struct drm_device *, int head, +- struct nv04_mode_state *state); +-void nouveau_hw_load_state_palette(struct drm_device *, int head, +- struct nv04_mode_state *state); +- +-/* nouveau_calc.c */ +-extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp, +- int *burst, int *lwm); +- +-static inline uint32_t NVReadCRTC(struct drm_device *dev, +- int head, uint32_t reg) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- uint32_t val; +- if (head) +- reg += NV_PCRTC0_SIZE; +- val = nvif_rd32(device, reg); +- return val; +-} +- +-static inline void NVWriteCRTC(struct drm_device *dev, +- int head, uint32_t reg, uint32_t val) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- if (head) +- reg += NV_PCRTC0_SIZE; +- nvif_wr32(device, reg, val); +-} +- +-static inline uint32_t NVReadRAMDAC(struct drm_device *dev, +- int head, uint32_t reg) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- uint32_t val; +- if (head) +- reg += NV_PRAMDAC0_SIZE; +- val = nvif_rd32(device, reg); +- return val; +-} +- +-static inline void NVWriteRAMDAC(struct drm_device *dev, +- int head, uint32_t reg, uint32_t val) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- if (head) +- reg += NV_PRAMDAC0_SIZE; +- nvif_wr32(device, reg, val); +-} +- +-static inline uint8_t nv_read_tmds(struct drm_device *dev, +- int or, int dl, uint8_t address) +-{ +- int ramdac = (or & DCB_OUTPUT_C) >> 2; +- +- NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, +- NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address); +- return NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8); +-} +- +-static inline void nv_write_tmds(struct drm_device *dev, +- int or, int dl, uint8_t address, +- uint8_t data) +-{ +- int ramdac = (or & DCB_OUTPUT_C) >> 2; +- +- NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data); +- NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address); +-} +- +-static inline void NVWriteVgaCrtc(struct drm_device *dev, +- int head, uint8_t index, uint8_t value) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); +- nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value); +-} +- +-static inline uint8_t NVReadVgaCrtc(struct drm_device *dev, +- int head, uint8_t index) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- uint8_t val; +- nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index); +- val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE); +- return val; +-} +- +-/* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58 +- * I suspect they in fact do nothing, but are merely a way to carry useful +- * per-head variables around +- * +- * Known uses: +- * CR57 CR58 +- * 0x00 index to the appropriate dcb entry (or 7f for inactive) +- * 0x02 dcb entry's "or" value (or 00 for inactive) +- * 0x03 bit0 set for dual link (LVDS, possibly elsewhere too) +- * 0x08 or 0x09 pxclk in MHz +- * 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap +- * high nibble for xlat strap value +- */ +- +-static inline void +-NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value) +-{ +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value); +-} +- +-static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index) +-{ +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index); +- return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58); +-} +- +-static inline uint8_t NVReadPRMVIO(struct drm_device *dev, +- int head, uint32_t reg) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t val; +- +- /* Only NV4x have two pvio ranges; other twoHeads cards MUST call +- * NVSetOwner for the relevant head to be programmed */ +- if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- reg += NV_PRMVIO_SIZE; +- +- val = nvif_rd08(device, reg); +- return val; +-} +- +-static inline void NVWritePRMVIO(struct drm_device *dev, +- int head, uint32_t reg, uint8_t value) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- /* Only NV4x have two pvio ranges; other twoHeads cards MUST call +- * NVSetOwner for the relevant head to be programmed */ +- if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- reg += NV_PRMVIO_SIZE; +- +- nvif_wr08(device, reg, value); +-} +- +-static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); +- nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20); +-} +- +-static inline bool NVGetEnablePalette(struct drm_device *dev, int head) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); +- return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20); +-} +- +-static inline void NVWriteVgaAttr(struct drm_device *dev, +- int head, uint8_t index, uint8_t value) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- if (NVGetEnablePalette(dev, head)) +- index &= ~0x20; +- else +- index |= 0x20; +- +- nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); +- nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index); +- nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value); +-} +- +-static inline uint8_t NVReadVgaAttr(struct drm_device *dev, +- int head, uint8_t index) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- uint8_t val; +- if (NVGetEnablePalette(dev, head)) +- index &= ~0x20; +- else +- index |= 0x20; +- +- nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE); +- nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index); +- val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE); +- return val; +-} +- +-static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start) +-{ +- NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3); +-} +- +-static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect) +-{ +- uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX); +- +- if (protect) { +- NVVgaSeqReset(dev, head, true); +- NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20); +- } else { +- /* Reenable sequencer, then turn on screen */ +- NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */ +- NVVgaSeqReset(dev, head, false); +- } +- NVSetEnablePalette(dev, head, protect); +-} +- +-static inline bool +-nv_heads_tied(struct drm_device *dev) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (drm->device.info.chipset == 0x11) +- return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28)); +- +- return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4; +-} +- +-/* makes cr0-7 on the specified head read-only */ +-static inline bool +-nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock) +-{ +- uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX); +- bool waslocked = cr11 & 0x80; +- +- if (lock) +- cr11 |= 0x80; +- else +- cr11 &= ~0x80; +- NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11); +- +- return waslocked; +-} +- +-static inline void +-nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock) +-{ +- /* shadow lock: connects 0x60?3d? regs to "real" 0x3d? regs +- * bit7: unlocks HDT, HBS, HBE, HRS, HRE, HEB +- * bit6: seems to have some effect on CR09 (double scan, VBS_9) +- * bit5: unlocks HDE +- * bit4: unlocks VDE +- * bit3: unlocks VDT, OVL, VRS, ?VRE?, VBS, VBE, LSR, EBR +- * bit2: same as bit 1 of 0x60?804 +- * bit0: same as bit 0 of 0x60?804 +- */ +- +- uint8_t cr21 = lock; +- +- if (lock < 0) +- /* 0xfa is generic "unlock all" mask */ +- cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa; +- +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21); +-} +- +-/* renders the extended crtc regs (cr19+) on all crtcs impervious: +- * immutable and unreadable +- */ +-static inline bool +-NVLockVgaCrtcs(struct drm_device *dev, bool lock) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX); +- +- NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX, +- lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE); +- /* NV11 has independently lockable extended crtcs, except when tied */ +- if (drm->device.info.chipset == 0x11 && !nv_heads_tied(dev)) +- NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX, +- lock ? NV_CIO_SR_LOCK_VALUE : +- NV_CIO_SR_UNLOCK_RW_VALUE); +- +- return waslocked; +-} +- +-/* nv04 cursor max dimensions of 32x32 (A1R5G5B5) */ +-#define NV04_CURSOR_SIZE 32 +-/* limit nv10 cursors to 64x64 (ARGB8) (we could go to 64x255) */ +-#define NV10_CURSOR_SIZE 64 +- +-static inline int nv_cursor_width(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- return drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE; +-} +- +-static inline void +-nv_fix_nv40_hw_cursor(struct drm_device *dev, int head) +-{ +- /* on some nv40 (such as the "true" (in the NV_PFB_BOOT_0 sense) nv40, +- * the gf6800gt) a hardware bug requires a write to PRAMDAC_CURSOR_POS +- * for changes to the CRTC CURCTL regs to take effect, whether changing +- * the pixmap location, or just showing/hiding the cursor +- */ +- uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos); +-} +- +-static inline void +-nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- NVWriteCRTC(dev, head, NV_PCRTC_START, offset); +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) { +- /* +- * Hilarious, the 24th bit doesn't want to stick to +- * PCRTC_START... +- */ +- int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX); +- +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX, +- (cre_heb & ~0x40) | ((offset >> 18) & 0x40)); +- } +-} +- +-static inline void +-nv_show_cursor(struct drm_device *dev, int head, bool show) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t *curctl1 = +- &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; +- +- if (show) +- *curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); +- else +- *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE); +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1); +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- nv_fix_nv40_hw_cursor(dev, head); +-} +- +-static inline uint32_t +-nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- int mask; +- +- if (bpp == 15) +- bpp = 16; +- if (bpp == 24) +- bpp = 8; +- +- /* Alignment requirements taken from the Haiku driver */ +- if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) +- mask = 128 / bpp - 1; +- else +- mask = 512 / bpp - 1; +- +- return (width + mask) & ~mask; +-} +- +-#endif /* __NOUVEAU_HW_H__ */ +diff --git a/drivers/gpu/drm/nouveau/dispnv04/nvreg.h b/drivers/gpu/drm/nouveau/dispnv04/nvreg.h +deleted file mode 100644 +index bbfb1a68..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/nvreg.h ++++ /dev/null +@@ -1,517 +0,0 @@ +-/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */ +-/* +- * Copyright 1996-1997 David J. McKay +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */ +- +-#ifndef __NVREG_H_ +-#define __NVREG_H_ +- +-#define NV_PMC_OFFSET 0x00000000 +-#define NV_PMC_SIZE 0x00001000 +- +-#define NV_PBUS_OFFSET 0x00001000 +-#define NV_PBUS_SIZE 0x00001000 +- +-#define NV_PFIFO_OFFSET 0x00002000 +-#define NV_PFIFO_SIZE 0x00002000 +- +-#define NV_HDIAG_OFFSET 0x00005000 +-#define NV_HDIAG_SIZE 0x00001000 +- +-#define NV_PRAM_OFFSET 0x00006000 +-#define NV_PRAM_SIZE 0x00001000 +- +-#define NV_PVIDEO_OFFSET 0x00008000 +-#define NV_PVIDEO_SIZE 0x00001000 +- +-#define NV_PTIMER_OFFSET 0x00009000 +-#define NV_PTIMER_SIZE 0x00001000 +- +-#define NV_PPM_OFFSET 0x0000A000 +-#define NV_PPM_SIZE 0x00001000 +- +-#define NV_PTV_OFFSET 0x0000D000 +-#define NV_PTV_SIZE 0x00001000 +- +-#define NV_PRMVGA_OFFSET 0x000A0000 +-#define NV_PRMVGA_SIZE 0x00020000 +- +-#define NV_PRMVIO0_OFFSET 0x000C0000 +-#define NV_PRMVIO_SIZE 0x00002000 +-#define NV_PRMVIO1_OFFSET 0x000C2000 +- +-#define NV_PFB_OFFSET 0x00100000 +-#define NV_PFB_SIZE 0x00001000 +- +-#define NV_PEXTDEV_OFFSET 0x00101000 +-#define NV_PEXTDEV_SIZE 0x00001000 +- +-#define NV_PME_OFFSET 0x00200000 +-#define NV_PME_SIZE 0x00001000 +- +-#define NV_PROM_OFFSET 0x00300000 +-#define NV_PROM_SIZE 0x00010000 +- +-#define NV_PGRAPH_OFFSET 0x00400000 +-#define NV_PGRAPH_SIZE 0x00010000 +- +-#define NV_PCRTC0_OFFSET 0x00600000 +-#define NV_PCRTC0_SIZE 0x00002000 /* empirical */ +- +-#define NV_PRMCIO0_OFFSET 0x00601000 +-#define NV_PRMCIO_SIZE 0x00002000 +-#define NV_PRMCIO1_OFFSET 0x00603000 +- +-#define NV50_DISPLAY_OFFSET 0x00610000 +-#define NV50_DISPLAY_SIZE 0x0000FFFF +- +-#define NV_PRAMDAC0_OFFSET 0x00680000 +-#define NV_PRAMDAC0_SIZE 0x00002000 +- +-#define NV_PRMDIO0_OFFSET 0x00681000 +-#define NV_PRMDIO_SIZE 0x00002000 +-#define NV_PRMDIO1_OFFSET 0x00683000 +- +-#define NV_PRAMIN_OFFSET 0x00700000 +-#define NV_PRAMIN_SIZE 0x00100000 +- +-#define NV_FIFO_OFFSET 0x00800000 +-#define NV_FIFO_SIZE 0x00800000 +- +-#define NV_PMC_BOOT_0 0x00000000 +-#define NV_PMC_ENABLE 0x00000200 +- +-#define NV_VIO_VSE2 0x000003c3 +-#define NV_VIO_SRX 0x000003c4 +- +-#define NV_CIO_CRX__COLOR 0x000003d4 +-#define NV_CIO_CR__COLOR 0x000003d5 +- +-#define NV_PBUS_DEBUG_1 0x00001084 +-#define NV_PBUS_DEBUG_4 0x00001098 +-#define NV_PBUS_DEBUG_DUALHEAD_CTL 0x000010f0 +-#define NV_PBUS_POWERCTRL_1 0x00001584 +-#define NV_PBUS_POWERCTRL_2 0x00001588 +-#define NV_PBUS_POWERCTRL_4 0x00001590 +-#define NV_PBUS_PCI_NV_19 0x0000184C +-#define NV_PBUS_PCI_NV_20 0x00001850 +-# define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) +-# define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) +- +-#define NV_PFIFO_RAMHT 0x00002210 +- +-#define NV_PTV_TV_INDEX 0x0000d220 +-#define NV_PTV_TV_DATA 0x0000d224 +-#define NV_PTV_HFILTER 0x0000d310 +-#define NV_PTV_HFILTER2 0x0000d390 +-#define NV_PTV_VFILTER 0x0000d510 +- +-#define NV_PRMVIO_MISC__WRITE 0x000c03c2 +-#define NV_PRMVIO_SRX 0x000c03c4 +-#define NV_PRMVIO_SR 0x000c03c5 +-# define NV_VIO_SR_RESET_INDEX 0x00 +-# define NV_VIO_SR_CLOCK_INDEX 0x01 +-# define NV_VIO_SR_PLANE_MASK_INDEX 0x02 +-# define NV_VIO_SR_CHAR_MAP_INDEX 0x03 +-# define NV_VIO_SR_MEM_MODE_INDEX 0x04 +-#define NV_PRMVIO_MISC__READ 0x000c03cc +-#define NV_PRMVIO_GRX 0x000c03ce +-#define NV_PRMVIO_GX 0x000c03cf +-# define NV_VIO_GX_SR_INDEX 0x00 +-# define NV_VIO_GX_SREN_INDEX 0x01 +-# define NV_VIO_GX_CCOMP_INDEX 0x02 +-# define NV_VIO_GX_ROP_INDEX 0x03 +-# define NV_VIO_GX_READ_MAP_INDEX 0x04 +-# define NV_VIO_GX_MODE_INDEX 0x05 +-# define NV_VIO_GX_MISC_INDEX 0x06 +-# define NV_VIO_GX_DONT_CARE_INDEX 0x07 +-# define NV_VIO_GX_BIT_MASK_INDEX 0x08 +- +-#define NV_PCRTC_INTR_0 0x00600100 +-# define NV_PCRTC_INTR_0_VBLANK (1 << 0) +-#define NV_PCRTC_INTR_EN_0 0x00600140 +-#define NV_PCRTC_START 0x00600800 +-#define NV_PCRTC_CONFIG 0x00600804 +-# define NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA (1 << 0) +-# define NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC (4 << 0) +-# define NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC (2 << 0) +-#define NV_PCRTC_CURSOR_CONFIG 0x00600810 +-# define NV_PCRTC_CURSOR_CONFIG_ENABLE_ENABLE (1 << 0) +-# define NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE (1 << 4) +-# define NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM (1 << 8) +-# define NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32 (1 << 12) +-# define NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 (1 << 16) +-# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_32 (2 << 24) +-# define NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 (4 << 24) +-# define NV_PCRTC_CURSOR_CONFIG_CUR_BLEND_ALPHA (1 << 28) +- +-/* note: PCRTC_GPIO is not available on nv10, and in fact aliases 0x600810 */ +-#define NV_PCRTC_GPIO 0x00600818 +-#define NV_PCRTC_GPIO_EXT 0x0060081c +-#define NV_PCRTC_830 0x00600830 +-#define NV_PCRTC_834 0x00600834 +-#define NV_PCRTC_850 0x00600850 +-#define NV_PCRTC_ENGINE_CTRL 0x00600860 +-# define NV_CRTC_FSEL_I2C (1 << 4) +-# define NV_CRTC_FSEL_OVERLAY (1 << 12) +- +-#define NV_PRMCIO_ARX 0x006013c0 +-#define NV_PRMCIO_AR__WRITE 0x006013c0 +-#define NV_PRMCIO_AR__READ 0x006013c1 +-# define NV_CIO_AR_MODE_INDEX 0x10 +-# define NV_CIO_AR_OSCAN_INDEX 0x11 +-# define NV_CIO_AR_PLANE_INDEX 0x12 +-# define NV_CIO_AR_HPP_INDEX 0x13 +-# define NV_CIO_AR_CSEL_INDEX 0x14 +-#define NV_PRMCIO_INP0 0x006013c2 +-#define NV_PRMCIO_CRX__COLOR 0x006013d4 +-#define NV_PRMCIO_CR__COLOR 0x006013d5 +- /* Standard VGA CRTC registers */ +-# define NV_CIO_CR_HDT_INDEX 0x00 /* horizontal display total */ +-# define NV_CIO_CR_HDE_INDEX 0x01 /* horizontal display end */ +-# define NV_CIO_CR_HBS_INDEX 0x02 /* horizontal blanking start */ +-# define NV_CIO_CR_HBE_INDEX 0x03 /* horizontal blanking end */ +-# define NV_CIO_CR_HBE_4_0 4:0 +-# define NV_CIO_CR_HRS_INDEX 0x04 /* horizontal retrace start */ +-# define NV_CIO_CR_HRE_INDEX 0x05 /* horizontal retrace end */ +-# define NV_CIO_CR_HRE_4_0 4:0 +-# define NV_CIO_CR_HRE_HBE_5 7:7 +-# define NV_CIO_CR_VDT_INDEX 0x06 /* vertical display total */ +-# define NV_CIO_CR_OVL_INDEX 0x07 /* overflow bits */ +-# define NV_CIO_CR_OVL_VDT_8 0:0 +-# define NV_CIO_CR_OVL_VDE_8 1:1 +-# define NV_CIO_CR_OVL_VRS_8 2:2 +-# define NV_CIO_CR_OVL_VBS_8 3:3 +-# define NV_CIO_CR_OVL_VDT_9 5:5 +-# define NV_CIO_CR_OVL_VDE_9 6:6 +-# define NV_CIO_CR_OVL_VRS_9 7:7 +-# define NV_CIO_CR_RSAL_INDEX 0x08 /* normally "preset row scan" */ +-# define NV_CIO_CR_CELL_HT_INDEX 0x09 /* cell height?! normally "max scan line" */ +-# define NV_CIO_CR_CELL_HT_VBS_9 5:5 +-# define NV_CIO_CR_CELL_HT_SCANDBL 7:7 +-# define NV_CIO_CR_CURS_ST_INDEX 0x0a /* cursor start */ +-# define NV_CIO_CR_CURS_END_INDEX 0x0b /* cursor end */ +-# define NV_CIO_CR_SA_HI_INDEX 0x0c /* screen start address high */ +-# define NV_CIO_CR_SA_LO_INDEX 0x0d /* screen start address low */ +-# define NV_CIO_CR_TCOFF_HI_INDEX 0x0e /* cursor offset high */ +-# define NV_CIO_CR_TCOFF_LO_INDEX 0x0f /* cursor offset low */ +-# define NV_CIO_CR_VRS_INDEX 0x10 /* vertical retrace start */ +-# define NV_CIO_CR_VRE_INDEX 0x11 /* vertical retrace end */ +-# define NV_CIO_CR_VRE_3_0 3:0 +-# define NV_CIO_CR_VDE_INDEX 0x12 /* vertical display end */ +-# define NV_CIO_CR_OFFSET_INDEX 0x13 /* sets screen pitch */ +-# define NV_CIO_CR_ULINE_INDEX 0x14 /* underline location */ +-# define NV_CIO_CR_VBS_INDEX 0x15 /* vertical blank start */ +-# define NV_CIO_CR_VBE_INDEX 0x16 /* vertical blank end */ +-# define NV_CIO_CR_MODE_INDEX 0x17 /* crtc mode control */ +-# define NV_CIO_CR_LCOMP_INDEX 0x18 /* line compare */ +- /* Extended VGA CRTC registers */ +-# define NV_CIO_CRE_RPC0_INDEX 0x19 /* repaint control 0 */ +-# define NV_CIO_CRE_RPC0_OFFSET_10_8 7:5 +-# define NV_CIO_CRE_RPC1_INDEX 0x1a /* repaint control 1 */ +-# define NV_CIO_CRE_RPC1_LARGE 2:2 +-# define NV_CIO_CRE_FF_INDEX 0x1b /* fifo control */ +-# define NV_CIO_CRE_ENH_INDEX 0x1c /* enhanced? */ +-# define NV_CIO_SR_LOCK_INDEX 0x1f /* crtc lock */ +-# define NV_CIO_SR_UNLOCK_RW_VALUE 0x57 +-# define NV_CIO_SR_LOCK_VALUE 0x99 +-# define NV_CIO_CRE_FFLWM__INDEX 0x20 /* fifo low water mark */ +-# define NV_CIO_CRE_21 0x21 /* vga shadow crtc lock */ +-# define NV_CIO_CRE_LSR_INDEX 0x25 /* ? */ +-# define NV_CIO_CRE_LSR_VDT_10 0:0 +-# define NV_CIO_CRE_LSR_VDE_10 1:1 +-# define NV_CIO_CRE_LSR_VRS_10 2:2 +-# define NV_CIO_CRE_LSR_VBS_10 3:3 +-# define NV_CIO_CRE_LSR_HBE_6 4:4 +-# define NV_CIO_CR_ARX_INDEX 0x26 /* attribute index -- ro copy of 0x60.3c0 */ +-# define NV_CIO_CRE_CHIP_ID_INDEX 0x27 /* chip revision */ +-# define NV_CIO_CRE_PIXEL_INDEX 0x28 +-# define NV_CIO_CRE_PIXEL_FORMAT 1:0 +-# define NV_CIO_CRE_HEB__INDEX 0x2d /* horizontal extra bits? */ +-# define NV_CIO_CRE_HEB_HDT_8 0:0 +-# define NV_CIO_CRE_HEB_HDE_8 1:1 +-# define NV_CIO_CRE_HEB_HBS_8 2:2 +-# define NV_CIO_CRE_HEB_HRS_8 3:3 +-# define NV_CIO_CRE_HEB_ILC_8 4:4 +-# define NV_CIO_CRE_2E 0x2e /* some scratch or dummy reg to force writes to sink in */ +-# define NV_CIO_CRE_HCUR_ADDR2_INDEX 0x2f /* cursor */ +-# define NV_CIO_CRE_HCUR_ADDR0_INDEX 0x30 /* pixmap */ +-# define NV_CIO_CRE_HCUR_ADDR0_ADR 6:0 +-# define NV_CIO_CRE_HCUR_ASI 7:7 +-# define NV_CIO_CRE_HCUR_ADDR1_INDEX 0x31 /* address */ +-# define NV_CIO_CRE_HCUR_ADDR1_ENABLE 0:0 +-# define NV_CIO_CRE_HCUR_ADDR1_CUR_DBL 1:1 +-# define NV_CIO_CRE_HCUR_ADDR1_ADR 7:2 +-# define NV_CIO_CRE_LCD__INDEX 0x33 +-# define NV_CIO_CRE_LCD_LCD_SELECT 0:0 +-# define NV_CIO_CRE_LCD_ROUTE_MASK 0x3b +-# define NV_CIO_CRE_DDC0_STATUS__INDEX 0x36 +-# define NV_CIO_CRE_DDC0_WR__INDEX 0x37 +-# define NV_CIO_CRE_ILACE__INDEX 0x39 /* interlace */ +-# define NV_CIO_CRE_SCRATCH3__INDEX 0x3b +-# define NV_CIO_CRE_SCRATCH4__INDEX 0x3c +-# define NV_CIO_CRE_DDC_STATUS__INDEX 0x3e +-# define NV_CIO_CRE_DDC_WR__INDEX 0x3f +-# define NV_CIO_CRE_EBR_INDEX 0x41 /* extra bits ? (vertical) */ +-# define NV_CIO_CRE_EBR_VDT_11 0:0 +-# define NV_CIO_CRE_EBR_VDE_11 2:2 +-# define NV_CIO_CRE_EBR_VRS_11 4:4 +-# define NV_CIO_CRE_EBR_VBS_11 6:6 +-# define NV_CIO_CRE_42 0x42 +-# define NV_CIO_CRE_42_OFFSET_11 6:6 +-# define NV_CIO_CRE_43 0x43 +-# define NV_CIO_CRE_44 0x44 /* head control */ +-# define NV_CIO_CRE_CSB 0x45 /* colour saturation boost */ +-# define NV_CIO_CRE_RCR 0x46 +-# define NV_CIO_CRE_RCR_ENDIAN_BIG 7:7 +-# define NV_CIO_CRE_47 0x47 /* extended fifo lwm, used on nv30+ */ +-# define NV_CIO_CRE_49 0x49 +-# define NV_CIO_CRE_4B 0x4b /* given patterns in 0x[2-3][a-c] regs, probably scratch 6 */ +-# define NV_CIO_CRE_TVOUT_LATENCY 0x52 +-# define NV_CIO_CRE_53 0x53 /* `fp_htiming' according to Haiku */ +-# define NV_CIO_CRE_54 0x54 /* `fp_vtiming' according to Haiku */ +-# define NV_CIO_CRE_57 0x57 /* index reg for cr58 */ +-# define NV_CIO_CRE_58 0x58 /* data reg for cr57 */ +-# define NV_CIO_CRE_59 0x59 /* related to on/off-chip-ness of digital outputs */ +-# define NV_CIO_CRE_5B 0x5B /* newer colour saturation reg */ +-# define NV_CIO_CRE_85 0x85 +-# define NV_CIO_CRE_86 0x86 +-#define NV_PRMCIO_INP0__COLOR 0x006013da +- +-#define NV_PRAMDAC_CU_START_POS 0x00680300 +-# define NV_PRAMDAC_CU_START_POS_X 15:0 +-# define NV_PRAMDAC_CU_START_POS_Y 31:16 +-#define NV_RAMDAC_NV10_CURSYNC 0x00680404 +- +-#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 +-#define NV_PRAMDAC_MPLL_COEFF 0x00680504 +-#define NV_PRAMDAC_VPLL_COEFF 0x00680508 +-# define NV30_RAMDAC_ENABLE_VCO2 (8 << 4) +- +-#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050c +-# define NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE (4 << 0) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL (1 << 8) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL (2 << 8) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL (4 << 8) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 (8 << 8) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 (1 << 16) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 (2 << 16) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 (4 << 16) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2 (8 << 16) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_TV_CLK_SOURCE_VIP (1 << 20) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 (1 << 28) +-# define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2 (2 << 28) +- +-#define NV_PRAMDAC_PLL_SETUP_CONTROL 0x00680510 +-#define NV_RAMDAC_VPLL2 0x00680520 +-#define NV_PRAMDAC_SEL_CLK 0x00680524 +-#define NV_RAMDAC_DITHER_NV11 0x00680528 +-#define NV_PRAMDAC_DACCLK 0x0068052c +-# define NV_PRAMDAC_DACCLK_SEL_DACCLK (1 << 0) +- +-#define NV_RAMDAC_NVPLL_B 0x00680570 +-#define NV_RAMDAC_MPLL_B 0x00680574 +-#define NV_RAMDAC_VPLL_B 0x00680578 +-#define NV_RAMDAC_VPLL2_B 0x0068057c +-# define NV31_RAMDAC_ENABLE_VCO2 (8 << 28) +-#define NV_PRAMDAC_580 0x00680580 +-# define NV_RAMDAC_580_VPLL1_ACTIVE (1 << 8) +-# define NV_RAMDAC_580_VPLL2_ACTIVE (1 << 28) +- +-#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 +-# define NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON (3 << 4) +-# define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL (1 << 8) +-# define NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL (1 << 12) +-# define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM (2 << 16) +-# define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS (1 << 20) +-# define NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG (2 << 28) +-#define NV_PRAMDAC_TEST_CONTROL 0x00680608 +-# define NV_PRAMDAC_TEST_CONTROL_TP_INS_EN_ASSERTED (1 << 12) +-# define NV_PRAMDAC_TEST_CONTROL_PWRDWN_DAC_OFF (1 << 16) +-# define NV_PRAMDAC_TEST_CONTROL_SENSEB_ALLHI (1 << 28) +-#define NV_PRAMDAC_TESTPOINT_DATA 0x00680610 +-# define NV_PRAMDAC_TESTPOINT_DATA_NOTBLANK (8 << 28) +-#define NV_PRAMDAC_630 0x00680630 +-#define NV_PRAMDAC_634 0x00680634 +- +-#define NV_PRAMDAC_TV_SETUP 0x00680700 +-#define NV_PRAMDAC_TV_VTOTAL 0x00680720 +-#define NV_PRAMDAC_TV_VSKEW 0x00680724 +-#define NV_PRAMDAC_TV_VSYNC_DELAY 0x00680728 +-#define NV_PRAMDAC_TV_HTOTAL 0x0068072c +-#define NV_PRAMDAC_TV_HSKEW 0x00680730 +-#define NV_PRAMDAC_TV_HSYNC_DELAY 0x00680734 +-#define NV_PRAMDAC_TV_HSYNC_DELAY2 0x00680738 +- +-#define NV_PRAMDAC_TV_SETUP 0x00680700 +- +-#define NV_PRAMDAC_FP_VDISPLAY_END 0x00680800 +-#define NV_PRAMDAC_FP_VTOTAL 0x00680804 +-#define NV_PRAMDAC_FP_VCRTC 0x00680808 +-#define NV_PRAMDAC_FP_VSYNC_START 0x0068080c +-#define NV_PRAMDAC_FP_VSYNC_END 0x00680810 +-#define NV_PRAMDAC_FP_VVALID_START 0x00680814 +-#define NV_PRAMDAC_FP_VVALID_END 0x00680818 +-#define NV_PRAMDAC_FP_HDISPLAY_END 0x00680820 +-#define NV_PRAMDAC_FP_HTOTAL 0x00680824 +-#define NV_PRAMDAC_FP_HCRTC 0x00680828 +-#define NV_PRAMDAC_FP_HSYNC_START 0x0068082c +-#define NV_PRAMDAC_FP_HSYNC_END 0x00680830 +-#define NV_PRAMDAC_FP_HVALID_START 0x00680834 +-#define NV_PRAMDAC_FP_HVALID_END 0x00680838 +- +-#define NV_RAMDAC_FP_DITHER 0x0068083c +-#define NV_PRAMDAC_FP_TG_CONTROL 0x00680848 +-# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS (1 << 0) +-# define NV_PRAMDAC_FP_TG_CONTROL_VSYNC_DISABLE (2 << 0) +-# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS (1 << 4) +-# define NV_PRAMDAC_FP_TG_CONTROL_HSYNC_DISABLE (2 << 4) +-# define NV_PRAMDAC_FP_TG_CONTROL_MODE_SCALE (0 << 8) +-# define NV_PRAMDAC_FP_TG_CONTROL_MODE_CENTER (1 << 8) +-# define NV_PRAMDAC_FP_TG_CONTROL_MODE_NATIVE (2 << 8) +-# define NV_PRAMDAC_FP_TG_CONTROL_READ_PROG (1 << 20) +-# define NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 (1 << 24) +-# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS (1 << 28) +-# define NV_PRAMDAC_FP_TG_CONTROL_DISPEN_DISABLE (2 << 28) +-#define NV_PRAMDAC_FP_MARGIN_COLOR 0x0068084c +-#define NV_PRAMDAC_850 0x00680850 +-#define NV_PRAMDAC_85C 0x0068085c +-#define NV_PRAMDAC_FP_DEBUG_0 0x00680880 +-# define NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE (1 << 0) +-# define NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE (1 << 4) +-/* This doesn't seem to be essential for tmds, but still often set */ +-# define NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED (8 << 4) +-# define NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR (1 << 8) +-# define NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR (1 << 12) +-# define NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND (1 << 20) +-# define NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND (1 << 24) +-# define NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK (1 << 28) +-#define NV_PRAMDAC_FP_DEBUG_1 0x00680884 +-# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE 11:0 +-# define NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE (1 << 12) +-# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE 27:16 +-# define NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE (1 << 28) +-#define NV_PRAMDAC_FP_DEBUG_2 0x00680888 +-#define NV_PRAMDAC_FP_DEBUG_3 0x0068088C +- +-/* see NV_PRAMDAC_INDIR_TMDS in rules.xml */ +-#define NV_PRAMDAC_FP_TMDS_CONTROL 0x006808b0 +-# define NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE (1 << 16) +-#define NV_PRAMDAC_FP_TMDS_DATA 0x006808b4 +- +-#define NV_PRAMDAC_8C0 0x006808c0 +- +-/* Some kind of switch */ +-#define NV_PRAMDAC_900 0x00680900 +-#define NV_PRAMDAC_A20 0x00680A20 +-#define NV_PRAMDAC_A24 0x00680A24 +-#define NV_PRAMDAC_A34 0x00680A34 +- +-#define NV_PRAMDAC_CTV 0x00680c00 +- +-/* names fabricated from NV_USER_DAC info */ +-#define NV_PRMDIO_PIXEL_MASK 0x006813c6 +-# define NV_PRMDIO_PIXEL_MASK_MASK 0xff +-#define NV_PRMDIO_READ_MODE_ADDRESS 0x006813c7 +-#define NV_PRMDIO_WRITE_MODE_ADDRESS 0x006813c8 +-#define NV_PRMDIO_PALETTE_DATA 0x006813c9 +- +-#define NV_PGRAPH_DEBUG_0 0x00400080 +-#define NV_PGRAPH_DEBUG_1 0x00400084 +-#define NV_PGRAPH_DEBUG_2_NV04 0x00400088 +-#define NV_PGRAPH_DEBUG_2 0x00400620 +-#define NV_PGRAPH_DEBUG_3 0x0040008c +-#define NV_PGRAPH_DEBUG_4 0x00400090 +-#define NV_PGRAPH_INTR 0x00400100 +-#define NV_PGRAPH_INTR_EN 0x00400140 +-#define NV_PGRAPH_CTX_CONTROL 0x00400144 +-#define NV_PGRAPH_CTX_CONTROL_NV04 0x00400170 +-#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C +-#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 +-#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 +-#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 +-#define NV_PGRAPH_BETA_AND 0x00400608 +-#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 +-#define NV_PGRAPH_BOFFSET0 0x00400640 +-#define NV_PGRAPH_BOFFSET1 0x00400644 +-#define NV_PGRAPH_BOFFSET2 0x00400648 +-#define NV_PGRAPH_BLIMIT0 0x00400684 +-#define NV_PGRAPH_BLIMIT1 0x00400688 +-#define NV_PGRAPH_BLIMIT2 0x0040068c +-#define NV_PGRAPH_STATUS 0x00400700 +-#define NV_PGRAPH_SURFACE 0x00400710 +-#define NV_PGRAPH_STATE 0x00400714 +-#define NV_PGRAPH_FIFO 0x00400720 +-#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 +-#define NV_PGRAPH_TILE 0x00400b00 +- +-#define NV_PVIDEO_INTR_EN 0x00008140 +-#define NV_PVIDEO_BUFFER 0x00008700 +-#define NV_PVIDEO_STOP 0x00008704 +-#define NV_PVIDEO_UVPLANE_BASE(buff) (0x00008800+(buff)*4) +-#define NV_PVIDEO_UVPLANE_LIMIT(buff) (0x00008808+(buff)*4) +-#define NV_PVIDEO_UVPLANE_OFFSET_BUFF(buff) (0x00008820+(buff)*4) +-#define NV_PVIDEO_BASE(buff) (0x00008900+(buff)*4) +-#define NV_PVIDEO_LIMIT(buff) (0x00008908+(buff)*4) +-#define NV_PVIDEO_LUMINANCE(buff) (0x00008910+(buff)*4) +-#define NV_PVIDEO_CHROMINANCE(buff) (0x00008918+(buff)*4) +-#define NV_PVIDEO_OFFSET_BUFF(buff) (0x00008920+(buff)*4) +-#define NV_PVIDEO_SIZE_IN(buff) (0x00008928+(buff)*4) +-#define NV_PVIDEO_POINT_IN(buff) (0x00008930+(buff)*4) +-#define NV_PVIDEO_DS_DX(buff) (0x00008938+(buff)*4) +-#define NV_PVIDEO_DT_DY(buff) (0x00008940+(buff)*4) +-#define NV_PVIDEO_POINT_OUT(buff) (0x00008948+(buff)*4) +-#define NV_PVIDEO_SIZE_OUT(buff) (0x00008950+(buff)*4) +-#define NV_PVIDEO_FORMAT(buff) (0x00008958+(buff)*4) +-# define NV_PVIDEO_FORMAT_PLANAR (1 << 0) +-# define NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8 (1 << 16) +-# define NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY (1 << 20) +-# define NV_PVIDEO_FORMAT_MATRIX_ITURBT709 (1 << 24) +-#define NV_PVIDEO_COLOR_KEY 0x00008B00 +- +-/* NV04 overlay defines from VIDIX & Haiku */ +-#define NV_PVIDEO_INTR_EN_0 0x00680140 +-#define NV_PVIDEO_STEP_SIZE 0x00680200 +-#define NV_PVIDEO_CONTROL_Y 0x00680204 +-#define NV_PVIDEO_CONTROL_X 0x00680208 +-#define NV_PVIDEO_BUFF0_START_ADDRESS 0x0068020c +-#define NV_PVIDEO_BUFF0_PITCH_LENGTH 0x00680214 +-#define NV_PVIDEO_BUFF0_OFFSET 0x0068021c +-#define NV_PVIDEO_BUFF1_START_ADDRESS 0x00680210 +-#define NV_PVIDEO_BUFF1_PITCH_LENGTH 0x00680218 +-#define NV_PVIDEO_BUFF1_OFFSET 0x00680220 +-#define NV_PVIDEO_OE_STATE 0x00680224 +-#define NV_PVIDEO_SU_STATE 0x00680228 +-#define NV_PVIDEO_RM_STATE 0x0068022c +-#define NV_PVIDEO_WINDOW_START 0x00680230 +-#define NV_PVIDEO_WINDOW_SIZE 0x00680234 +-#define NV_PVIDEO_FIFO_THRES_SIZE 0x00680238 +-#define NV_PVIDEO_FIFO_BURST_LENGTH 0x0068023c +-#define NV_PVIDEO_KEY 0x00680240 +-#define NV_PVIDEO_OVERLAY 0x00680244 +-#define NV_PVIDEO_RED_CSC_OFFSET 0x00680280 +-#define NV_PVIDEO_GREEN_CSC_OFFSET 0x00680284 +-#define NV_PVIDEO_BLUE_CSC_OFFSET 0x00680288 +-#define NV_PVIDEO_CSC_ADJUST 0x0068028c +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c +deleted file mode 100644 +index 1e9056a8..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c ++++ /dev/null +@@ -1,502 +0,0 @@ +-/* +- * Copyright 2013 Ilia Mirkin +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- * +- * Implementation based on the pre-KMS implementation in xf86-video-nouveau, +- * written by Arthur Huillet. +- */ +- +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +- +-#include "nouveau_bo.h" +-#include "nouveau_connector.h" +-#include "nouveau_display.h" +-#include "nvreg.h" +- +- +-struct nouveau_plane { +- struct drm_plane base; +- bool flip; +- struct nouveau_bo *cur; +- +- struct { +- struct drm_property *colorkey; +- struct drm_property *contrast; +- struct drm_property *brightness; +- struct drm_property *hue; +- struct drm_property *saturation; +- struct drm_property *iturbt_709; +- } props; +- +- int colorkey; +- int contrast; +- int brightness; +- int hue; +- int saturation; +- int iturbt_709; +- +- void (*set_params)(struct nouveau_plane *); +-}; +- +-static uint32_t formats[] = { +- DRM_FORMAT_YUYV, +- DRM_FORMAT_UYVY, +- DRM_FORMAT_NV12, +-}; +- +-/* Sine can be approximated with +- * http://en.wikipedia.org/wiki/Bhaskara_I's_sine_approximation_formula +- * sin(x degrees) ~= 4 x (180 - x) / (40500 - x (180 - x) ) +- * Note that this only works for the range [0, 180]. +- * Also note that sin(x) == -sin(x - 180) +- */ +-static inline int +-sin_mul(int degrees, int factor) +-{ +- if (degrees > 180) { +- degrees -= 180; +- factor *= -1; +- } +- return factor * 4 * degrees * (180 - degrees) / +- (40500 - degrees * (180 - degrees)); +-} +- +-/* cos(x) = sin(x + 90) */ +-static inline int +-cos_mul(int degrees, int factor) +-{ +- return sin_mul((degrees + 90) % 360, factor); +-} +- +-static int +-nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, +- struct drm_framebuffer *fb, int crtc_x, int crtc_y, +- unsigned int crtc_w, unsigned int crtc_h, +- uint32_t src_x, uint32_t src_y, +- uint32_t src_w, uint32_t src_h) +-{ +- struct nvif_device *dev = &nouveau_drm(plane->dev)->device; +- struct nouveau_plane *nv_plane = +- container_of(plane, struct nouveau_plane, base); +- struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nouveau_bo *cur = nv_plane->cur; +- bool flip = nv_plane->flip; +- int soff = NV_PCRTC0_SIZE * nv_crtc->index; +- int soff2 = NV_PCRTC0_SIZE * !nv_crtc->index; +- int format, ret; +- +- /* Source parameters given in 16.16 fixed point, ignore fractional. */ +- src_x >>= 16; +- src_y >>= 16; +- src_w >>= 16; +- src_h >>= 16; +- +- format = ALIGN(src_w * 4, 0x100); +- +- if (format > 0xffff) +- return -ERANGE; +- +- if (dev->info.chipset >= 0x30) { +- if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1)) +- return -ERANGE; +- } else { +- if (crtc_w < (src_w >> 3) || crtc_h < (src_h >> 3)) +- return -ERANGE; +- } +- +- ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM); +- if (ret) +- return ret; +- +- nv_plane->cur = nv_fb->nvbo; +- +- nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff, NV_CRTC_FSEL_OVERLAY, NV_CRTC_FSEL_OVERLAY); +- nvif_mask(dev, NV_PCRTC_ENGINE_CTRL + soff2, NV_CRTC_FSEL_OVERLAY, 0); +- +- nvif_wr32(dev, NV_PVIDEO_BASE(flip), 0); +- nvif_wr32(dev, NV_PVIDEO_OFFSET_BUFF(flip), nv_fb->nvbo->bo.offset); +- nvif_wr32(dev, NV_PVIDEO_SIZE_IN(flip), src_h << 16 | src_w); +- nvif_wr32(dev, NV_PVIDEO_POINT_IN(flip), src_y << 16 | src_x); +- nvif_wr32(dev, NV_PVIDEO_DS_DX(flip), (src_w << 20) / crtc_w); +- nvif_wr32(dev, NV_PVIDEO_DT_DY(flip), (src_h << 20) / crtc_h); +- nvif_wr32(dev, NV_PVIDEO_POINT_OUT(flip), crtc_y << 16 | crtc_x); +- nvif_wr32(dev, NV_PVIDEO_SIZE_OUT(flip), crtc_h << 16 | crtc_w); +- +- if (fb->pixel_format != DRM_FORMAT_UYVY) +- format |= NV_PVIDEO_FORMAT_COLOR_LE_CR8YB8CB8YA8; +- if (fb->pixel_format == DRM_FORMAT_NV12) +- format |= NV_PVIDEO_FORMAT_PLANAR; +- if (nv_plane->iturbt_709) +- format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; +- if (nv_plane->colorkey & (1 << 24)) +- format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; +- +- if (fb->pixel_format == DRM_FORMAT_NV12) { +- nvif_wr32(dev, NV_PVIDEO_UVPLANE_BASE(flip), 0); +- nvif_wr32(dev, NV_PVIDEO_UVPLANE_OFFSET_BUFF(flip), +- nv_fb->nvbo->bo.offset + fb->offsets[1]); +- } +- nvif_wr32(dev, NV_PVIDEO_FORMAT(flip), format); +- nvif_wr32(dev, NV_PVIDEO_STOP, 0); +- /* TODO: wait for vblank? */ +- nvif_wr32(dev, NV_PVIDEO_BUFFER, flip ? 0x10 : 0x1); +- nv_plane->flip = !flip; +- +- if (cur) +- nouveau_bo_unpin(cur); +- +- return 0; +-} +- +-static int +-nv10_disable_plane(struct drm_plane *plane) +-{ +- struct nvif_device *dev = &nouveau_drm(plane->dev)->device; +- struct nouveau_plane *nv_plane = +- container_of(plane, struct nouveau_plane, base); +- +- nvif_wr32(dev, NV_PVIDEO_STOP, 1); +- if (nv_plane->cur) { +- nouveau_bo_unpin(nv_plane->cur); +- nv_plane->cur = NULL; +- } +- +- return 0; +-} +- +-static void +-nv_destroy_plane(struct drm_plane *plane) +-{ +- plane->funcs->disable_plane(plane); +- drm_plane_cleanup(plane); +- kfree(plane); +-} +- +-static void +-nv10_set_params(struct nouveau_plane *plane) +-{ +- struct nvif_device *dev = &nouveau_drm(plane->base.dev)->device; +- u32 luma = (plane->brightness - 512) << 16 | plane->contrast; +- u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) | +- (cos_mul(plane->hue, plane->saturation) & 0xffff); +- u32 format = 0; +- +- nvif_wr32(dev, NV_PVIDEO_LUMINANCE(0), luma); +- nvif_wr32(dev, NV_PVIDEO_LUMINANCE(1), luma); +- nvif_wr32(dev, NV_PVIDEO_CHROMINANCE(0), chroma); +- nvif_wr32(dev, NV_PVIDEO_CHROMINANCE(1), chroma); +- nvif_wr32(dev, NV_PVIDEO_COLOR_KEY, plane->colorkey & 0xffffff); +- +- if (plane->cur) { +- if (plane->iturbt_709) +- format |= NV_PVIDEO_FORMAT_MATRIX_ITURBT709; +- if (plane->colorkey & (1 << 24)) +- format |= NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY; +- nvif_mask(dev, NV_PVIDEO_FORMAT(plane->flip), +- NV_PVIDEO_FORMAT_MATRIX_ITURBT709 | +- NV_PVIDEO_FORMAT_DISPLAY_COLOR_KEY, +- format); +- } +-} +- +-static int +-nv_set_property(struct drm_plane *plane, +- struct drm_property *property, +- uint64_t value) +-{ +- struct nouveau_plane *nv_plane = +- container_of(plane, struct nouveau_plane, base); +- +- if (property == nv_plane->props.colorkey) +- nv_plane->colorkey = value; +- else if (property == nv_plane->props.contrast) +- nv_plane->contrast = value; +- else if (property == nv_plane->props.brightness) +- nv_plane->brightness = value; +- else if (property == nv_plane->props.hue) +- nv_plane->hue = value; +- else if (property == nv_plane->props.saturation) +- nv_plane->saturation = value; +- else if (property == nv_plane->props.iturbt_709) +- nv_plane->iturbt_709 = value; +- else +- return -EINVAL; +- +- if (nv_plane->set_params) +- nv_plane->set_params(nv_plane); +- return 0; +-} +- +-static const struct drm_plane_funcs nv10_plane_funcs = { +- .update_plane = nv10_update_plane, +- .disable_plane = nv10_disable_plane, +- .set_property = nv_set_property, +- .destroy = nv_destroy_plane, +-}; +- +-static void +-nv10_overlay_init(struct drm_device *device) +-{ +- struct nouveau_drm *drm = nouveau_drm(device); +- struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL); +- int num_formats = ARRAY_SIZE(formats); +- int ret; +- +- if (!plane) +- return; +- +- switch (drm->device.info.chipset) { +- case 0x10: +- case 0x11: +- case 0x15: +- case 0x1a: +- case 0x20: +- num_formats = 2; +- break; +- } +- +- ret = drm_plane_init(device, &plane->base, 3 /* both crtc's */, +- &nv10_plane_funcs, +- formats, num_formats, false); +- if (ret) +- goto err; +- +- /* Set up the plane properties */ +- plane->props.colorkey = drm_property_create_range( +- device, 0, "colorkey", 0, 0x01ffffff); +- plane->props.contrast = drm_property_create_range( +- device, 0, "contrast", 0, 8192 - 1); +- plane->props.brightness = drm_property_create_range( +- device, 0, "brightness", 0, 1024); +- plane->props.hue = drm_property_create_range( +- device, 0, "hue", 0, 359); +- plane->props.saturation = drm_property_create_range( +- device, 0, "saturation", 0, 8192 - 1); +- plane->props.iturbt_709 = drm_property_create_range( +- device, 0, "iturbt_709", 0, 1); +- if (!plane->props.colorkey || +- !plane->props.contrast || +- !plane->props.brightness || +- !plane->props.hue || +- !plane->props.saturation || +- !plane->props.iturbt_709) +- goto cleanup; +- +- plane->colorkey = 0; +- drm_object_attach_property(&plane->base.base, +- plane->props.colorkey, plane->colorkey); +- +- plane->contrast = 0x1000; +- drm_object_attach_property(&plane->base.base, +- plane->props.contrast, plane->contrast); +- +- plane->brightness = 512; +- drm_object_attach_property(&plane->base.base, +- plane->props.brightness, plane->brightness); +- +- plane->hue = 0; +- drm_object_attach_property(&plane->base.base, +- plane->props.hue, plane->hue); +- +- plane->saturation = 0x1000; +- drm_object_attach_property(&plane->base.base, +- plane->props.saturation, plane->saturation); +- +- plane->iturbt_709 = 0; +- drm_object_attach_property(&plane->base.base, +- plane->props.iturbt_709, plane->iturbt_709); +- +- plane->set_params = nv10_set_params; +- nv10_set_params(plane); +- nv10_disable_plane(&plane->base); +- return; +-cleanup: +- drm_plane_cleanup(&plane->base); +-err: +- kfree(plane); +- NV_ERROR(drm, "Failed to create plane\n"); +-} +- +-static int +-nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, +- struct drm_framebuffer *fb, int crtc_x, int crtc_y, +- unsigned int crtc_w, unsigned int crtc_h, +- uint32_t src_x, uint32_t src_y, +- uint32_t src_w, uint32_t src_h) +-{ +- struct nvif_device *dev = &nouveau_drm(plane->dev)->device; +- struct nouveau_plane *nv_plane = +- container_of(plane, struct nouveau_plane, base); +- struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); +- struct nouveau_bo *cur = nv_plane->cur; +- uint32_t overlay = 1; +- int brightness = (nv_plane->brightness - 512) * 62 / 512; +- int pitch, ret, i; +- +- /* Source parameters given in 16.16 fixed point, ignore fractional. */ +- src_x >>= 16; +- src_y >>= 16; +- src_w >>= 16; +- src_h >>= 16; +- +- pitch = ALIGN(src_w * 4, 0x100); +- +- if (pitch > 0xffff) +- return -ERANGE; +- +- /* TODO: Compute an offset? Not sure how to do this for YUYV. */ +- if (src_x != 0 || src_y != 0) +- return -ERANGE; +- +- if (crtc_w < src_w || crtc_h < src_h) +- return -ERANGE; +- +- ret = nouveau_bo_pin(nv_fb->nvbo, TTM_PL_FLAG_VRAM); +- if (ret) +- return ret; +- +- nv_plane->cur = nv_fb->nvbo; +- +- nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0); +- nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0); +- nvif_wr32(dev, NV_PVIDEO_RM_STATE, 0); +- +- for (i = 0; i < 2; i++) { +- nvif_wr32(dev, NV_PVIDEO_BUFF0_START_ADDRESS + 4 * i, +- nv_fb->nvbo->bo.offset); +- nvif_wr32(dev, NV_PVIDEO_BUFF0_PITCH_LENGTH + 4 * i, pitch); +- nvif_wr32(dev, NV_PVIDEO_BUFF0_OFFSET + 4 * i, 0); +- } +- nvif_wr32(dev, NV_PVIDEO_WINDOW_START, crtc_y << 16 | crtc_x); +- nvif_wr32(dev, NV_PVIDEO_WINDOW_SIZE, crtc_h << 16 | crtc_w); +- nvif_wr32(dev, NV_PVIDEO_STEP_SIZE, +- (uint32_t)(((src_h - 1) << 11) / (crtc_h - 1)) << 16 | (uint32_t)(((src_w - 1) << 11) / (crtc_w - 1))); +- +- /* It should be possible to convert hue/contrast to this */ +- nvif_wr32(dev, NV_PVIDEO_RED_CSC_OFFSET, 0x69 - brightness); +- nvif_wr32(dev, NV_PVIDEO_GREEN_CSC_OFFSET, 0x3e + brightness); +- nvif_wr32(dev, NV_PVIDEO_BLUE_CSC_OFFSET, 0x89 - brightness); +- nvif_wr32(dev, NV_PVIDEO_CSC_ADJUST, 0); +- +- nvif_wr32(dev, NV_PVIDEO_CONTROL_Y, 0x001); /* (BLUR_ON, LINE_HALF) */ +- nvif_wr32(dev, NV_PVIDEO_CONTROL_X, 0x111); /* (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ +- +- nvif_wr32(dev, NV_PVIDEO_FIFO_BURST_LENGTH, 0x03); +- nvif_wr32(dev, NV_PVIDEO_FIFO_THRES_SIZE, 0x38); +- +- nvif_wr32(dev, NV_PVIDEO_KEY, nv_plane->colorkey); +- +- if (nv_plane->colorkey & (1 << 24)) +- overlay |= 0x10; +- if (fb->pixel_format == DRM_FORMAT_YUYV) +- overlay |= 0x100; +- +- nvif_wr32(dev, NV_PVIDEO_OVERLAY, overlay); +- +- nvif_wr32(dev, NV_PVIDEO_SU_STATE, nvif_rd32(dev, NV_PVIDEO_SU_STATE) ^ (1 << 16)); +- +- if (cur) +- nouveau_bo_unpin(cur); +- +- return 0; +-} +- +-static int +-nv04_disable_plane(struct drm_plane *plane) +-{ +- struct nvif_device *dev = &nouveau_drm(plane->dev)->device; +- struct nouveau_plane *nv_plane = +- container_of(plane, struct nouveau_plane, base); +- +- nvif_mask(dev, NV_PVIDEO_OVERLAY, 1, 0); +- nvif_wr32(dev, NV_PVIDEO_OE_STATE, 0); +- nvif_wr32(dev, NV_PVIDEO_SU_STATE, 0); +- nvif_wr32(dev, NV_PVIDEO_RM_STATE, 0); +- if (nv_plane->cur) { +- nouveau_bo_unpin(nv_plane->cur); +- nv_plane->cur = NULL; +- } +- +- return 0; +-} +- +-static const struct drm_plane_funcs nv04_plane_funcs = { +- .update_plane = nv04_update_plane, +- .disable_plane = nv04_disable_plane, +- .set_property = nv_set_property, +- .destroy = nv_destroy_plane, +-}; +- +-static void +-nv04_overlay_init(struct drm_device *device) +-{ +- struct nouveau_drm *drm = nouveau_drm(device); +- struct nouveau_plane *plane = kzalloc(sizeof(struct nouveau_plane), GFP_KERNEL); +- int ret; +- +- if (!plane) +- return; +- +- ret = drm_plane_init(device, &plane->base, 1 /* single crtc */, +- &nv04_plane_funcs, +- formats, 2, false); +- if (ret) +- goto err; +- +- /* Set up the plane properties */ +- plane->props.colorkey = drm_property_create_range( +- device, 0, "colorkey", 0, 0x01ffffff); +- plane->props.brightness = drm_property_create_range( +- device, 0, "brightness", 0, 1024); +- if (!plane->props.colorkey || +- !plane->props.brightness) +- goto cleanup; +- +- plane->colorkey = 0; +- drm_object_attach_property(&plane->base.base, +- plane->props.colorkey, plane->colorkey); +- +- plane->brightness = 512; +- drm_object_attach_property(&plane->base.base, +- plane->props.brightness, plane->brightness); +- +- nv04_disable_plane(&plane->base); +- return; +-cleanup: +- drm_plane_cleanup(&plane->base); +-err: +- kfree(plane); +- NV_ERROR(drm, "Failed to create plane\n"); +-} +- +-void +-nouveau_overlay_init(struct drm_device *device) +-{ +- struct nvif_device *dev = &nouveau_drm(device)->device; +- if (dev->info.chipset < 0x10) +- nv04_overlay_init(device); +- else if (dev->info.chipset <= 0x40) +- nv10_overlay_init(device); +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c +deleted file mode 100644 +index 08c6f5e5..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c ++++ /dev/null +@@ -1,592 +0,0 @@ +-/* +- * Copyright (C) 2009 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include +-#include "nouveau_drm.h" +-#include "nouveau_encoder.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +-#include "tvnv17.h" +- +-char *nv17_tv_norm_names[NUM_TV_NORMS] = { +- [TV_NORM_PAL] = "PAL", +- [TV_NORM_PAL_M] = "PAL-M", +- [TV_NORM_PAL_N] = "PAL-N", +- [TV_NORM_PAL_NC] = "PAL-Nc", +- [TV_NORM_NTSC_M] = "NTSC-M", +- [TV_NORM_NTSC_J] = "NTSC-J", +- [TV_NORM_HD480I] = "hd480i", +- [TV_NORM_HD480P] = "hd480p", +- [TV_NORM_HD576I] = "hd576i", +- [TV_NORM_HD576P] = "hd576p", +- [TV_NORM_HD720P] = "hd720p", +- [TV_NORM_HD1080I] = "hd1080i" +-}; +- +-/* TV standard specific parameters */ +- +-struct nv17_tv_norm_params nv17_tv_norms[NUM_TV_NORMS] = { +- [TV_NORM_PAL] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 576, 50000, { +- 0x2a, 0x9, 0x8a, 0xcb, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x40, 0x8a, 0x35, 0x27, 0x0, 0x34, 0x3, +- 0x3e, 0x3, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x9c, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x3, +- 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x1a, 0xff, 0x3, 0x18, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x49, 0x10, 0x0, 0x9b, +- 0xbd, 0x15, 0x5, 0x15, 0x3e, 0x3, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_PAL_M] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 480, 59940, { +- 0x21, 0xe6, 0xef, 0xe3, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x44, 0x76, 0x32, 0x25, 0x0, 0x3c, 0x0, +- 0x3c, 0x0, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x83, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x1, +- 0xc5, 0x4, 0xc5, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x18, 0xff, 0x3, 0x20, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x40, 0x10, 0x0, 0x9c, +- 0xc8, 0x15, 0x5, 0x15, 0x3c, 0x0, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_PAL_N] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 576, 50000, { +- 0x2a, 0x9, 0x8a, 0xcb, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x40, 0x8a, 0x32, 0x25, 0x0, 0x3c, 0x0, +- 0x3c, 0x0, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x9c, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x1, +- 0xc5, 0x4, 0xc5, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x1a, 0xff, 0x3, 0x18, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x49, 0x10, 0x0, 0x9b, +- 0xbd, 0x15, 0x5, 0x15, 0x3c, 0x0, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_PAL_NC] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 576, 50000, { +- 0x21, 0xf6, 0x94, 0x46, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x44, 0x8a, 0x35, 0x27, 0x0, 0x34, 0x3, +- 0x3e, 0x3, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x9c, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x3, +- 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x1a, 0xff, 0x3, 0x18, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x49, 0x10, 0x0, 0x9b, +- 0xbd, 0x15, 0x5, 0x15, 0x3e, 0x3, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_NTSC_M] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 480, 59940, { +- 0x21, 0xf0, 0x7c, 0x1f, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x44, 0x76, 0x48, 0x0, 0x0, 0x3c, 0x0, +- 0x3c, 0x0, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x83, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x1, +- 0xc5, 0x4, 0xc5, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x16, 0xff, 0x3, 0x20, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x4, 0x10, 0x0, 0x9c, +- 0xc8, 0x15, 0x5, 0x15, 0x3c, 0x0, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_NTSC_J] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 480, 59940, { +- 0x21, 0xf0, 0x7c, 0x1f, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x44, 0x76, 0x48, 0x0, 0x0, 0x32, 0x0, +- 0x3c, 0x0, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x83, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x1, +- 0xcf, 0x4, 0xcf, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x16, 0xff, 0x3, 0x20, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x4, 0x10, 0x0, 0xa4, +- 0xc8, 0x15, 0x5, 0x15, 0x3c, 0x0, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_HD480I] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 480, 59940, { +- 0x21, 0xf0, 0x7c, 0x1f, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x44, 0x76, 0x48, 0x0, 0x0, 0x32, 0x0, +- 0x3c, 0x0, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x83, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x1, +- 0xcf, 0x4, 0xcf, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x16, 0xff, 0x3, 0x20, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x4, 0x10, 0x0, 0xa4, +- 0xc8, 0x15, 0x5, 0x15, 0x3c, 0x0, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_HD576I] = { TV_ENC_MODE, { +- .tv_enc_mode = { 720, 576, 50000, { +- 0x2a, 0x9, 0x8a, 0xcb, 0x0, 0x0, 0xb, 0x18, +- 0x7e, 0x40, 0x8a, 0x35, 0x27, 0x0, 0x34, 0x3, +- 0x3e, 0x3, 0x17, 0x21, 0x1b, 0x1b, 0x24, 0x9c, +- 0x1, 0x0, 0xf, 0xf, 0x60, 0x5, 0xd3, 0x3, +- 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5, +- 0x0, 0x1a, 0xff, 0x3, 0x18, 0xf, 0x78, 0x0, +- 0x0, 0xb4, 0x0, 0x15, 0x49, 0x10, 0x0, 0x9b, +- 0xbd, 0x15, 0x5, 0x15, 0x3e, 0x3, 0x0, 0x0 +- } } } }, +- +- +- [TV_NORM_HD480P] = { CTV_ENC_MODE, { +- .ctv_enc_mode = { +- .mode = { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, +- 720, 735, 743, 858, 0, 480, 490, 494, 525, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, +- .ctv_regs = { 0x3540000, 0x0, 0x0, 0x314, +- 0x354003a, 0x40000, 0x6f0344, 0x18100000, +- 0x10160004, 0x10060005, 0x1006000c, 0x10060020, +- 0x10060021, 0x140e0022, 0x10060202, 0x1802020a, +- 0x1810020b, 0x10000fff, 0x10000fff, 0x10000fff, +- 0x10000fff, 0x10000fff, 0x10000fff, 0x70, +- 0x3ff0000, 0x57, 0x2e001e, 0x258012c, +- 0xa0aa04ec, 0x30, 0x80960019, 0x12c0300, +- 0x2019, 0x600, 0x32060019, 0x0, 0x0, 0x400 +- } } } }, +- +- [TV_NORM_HD576P] = { CTV_ENC_MODE, { +- .ctv_enc_mode = { +- .mode = { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, +- 720, 730, 738, 864, 0, 576, 581, 585, 625, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, +- .ctv_regs = { 0x3540000, 0x0, 0x0, 0x314, +- 0x354003a, 0x40000, 0x6f0344, 0x18100000, +- 0x10060001, 0x10060009, 0x10060026, 0x10060027, +- 0x140e0028, 0x10060268, 0x1810026d, 0x10000fff, +- 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, +- 0x10000fff, 0x10000fff, 0x10000fff, 0x69, +- 0x3ff0000, 0x57, 0x2e001e, 0x258012c, +- 0xa0aa04ec, 0x30, 0x80960019, 0x12c0300, +- 0x2019, 0x600, 0x32060019, 0x0, 0x0, 0x400 +- } } } }, +- +- [TV_NORM_HD720P] = { CTV_ENC_MODE, { +- .ctv_enc_mode = { +- .mode = { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, +- 1280, 1349, 1357, 1650, 0, 720, 725, 730, 750, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, +- .ctv_regs = { 0x1260394, 0x0, 0x0, 0x622, +- 0x66b0021, 0x6004a, 0x1210626, 0x8170000, +- 0x70004, 0x70016, 0x70017, 0x40f0018, +- 0x702e8, 0x81702ed, 0xfff, 0xfff, +- 0xfff, 0xfff, 0xfff, 0xfff, +- 0xfff, 0xfff, 0xfff, 0x0, +- 0x2e40001, 0x58, 0x2e001e, 0x258012c, +- 0xa0aa04ec, 0x30, 0x810c0039, 0x12c0300, +- 0xc0002039, 0x600, 0x32060039, 0x0, 0x0, 0x0 +- } } } }, +- +- [TV_NORM_HD1080I] = { CTV_ENC_MODE, { +- .ctv_enc_mode = { +- .mode = { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, +- 1920, 1961, 2049, 2200, 0, 1080, 1084, 1088, 1125, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC +- | DRM_MODE_FLAG_INTERLACE) }, +- .ctv_regs = { 0xac0420, 0x44c0478, 0x4a4, 0x4fc0868, +- 0x8940028, 0x60054, 0xe80870, 0xbf70000, +- 0xbc70004, 0x70005, 0x70012, 0x70013, +- 0x40f0014, 0x70230, 0xbf70232, 0xbf70233, +- 0x1c70237, 0x70238, 0x70244, 0x70245, +- 0x40f0246, 0x70462, 0x1f70464, 0x0, +- 0x2e40001, 0x58, 0x2e001e, 0x258012c, +- 0xa0aa04ec, 0x30, 0x815f004c, 0x12c0300, +- 0xc000204c, 0x600, 0x3206004c, 0x0, 0x0, 0x0 +- } } } } +-}; +- +-/* +- * The following is some guesswork on how the TV encoder flicker +- * filter/rescaler works: +- * +- * It seems to use some sort of resampling filter, it is controlled +- * through the registers at NV_PTV_HFILTER and NV_PTV_VFILTER, they +- * control the horizontal and vertical stage respectively, there is +- * also NV_PTV_HFILTER2 the blob fills identically to NV_PTV_HFILTER, +- * but they seem to do nothing. A rough guess might be that they could +- * be used to independently control the filtering of each interlaced +- * field, but I don't know how they are enabled. The whole filtering +- * process seems to be disabled with bits 26:27 of PTV_200, but we +- * aren't doing that. +- * +- * The layout of both register sets is the same: +- * +- * A: [BASE+0x18]...[BASE+0x0] [BASE+0x58]..[BASE+0x40] +- * B: [BASE+0x34]...[BASE+0x1c] [BASE+0x74]..[BASE+0x5c] +- * +- * Each coefficient is stored in bits [31],[15:9] in two's complement +- * format. They seem to be some kind of weights used in a low-pass +- * filter. Both A and B coefficients are applied to the 14 nearest +- * samples on each side (Listed from nearest to furthermost. They +- * roughly cover 2 framebuffer pixels on each side). They are +- * probably multiplied with some more hardwired weights before being +- * used: B-coefficients are applied the same on both sides, +- * A-coefficients are inverted before being applied to the opposite +- * side. +- * +- * After all the hassle, I got the following formula by empirical +- * means... +- */ +- +-#define calc_overscan(o) interpolate(0x100, 0xe1, 0xc1, o) +- +-#define id1 (1LL << 8) +-#define id2 (1LL << 16) +-#define id3 (1LL << 24) +-#define id4 (1LL << 32) +-#define id5 (1LL << 48) +- +-static struct filter_params{ +- int64_t k1; +- int64_t ki; +- int64_t ki2; +- int64_t ki3; +- int64_t kr; +- int64_t kir; +- int64_t ki2r; +- int64_t ki3r; +- int64_t kf; +- int64_t kif; +- int64_t ki2f; +- int64_t ki3f; +- int64_t krf; +- int64_t kirf; +- int64_t ki2rf; +- int64_t ki3rf; +-} fparams[2][4] = { +- /* Horizontal filter parameters */ +- { +- {64.311690 * id5, -39.516924 * id5, 6.586143 * id5, 0.000002 * id5, +- 0.051285 * id4, 26.168746 * id4, -4.361449 * id4, -0.000001 * id4, +- 9.308169 * id3, 78.180965 * id3, -13.030158 * id3, -0.000001 * id3, +- -8.801540 * id1, -46.572890 * id1, 7.762145 * id1, -0.000000 * id1}, +- {-44.565569 * id5, -68.081246 * id5, 39.812074 * id5, -4.009316 * id5, +- 29.832207 * id4, 50.047322 * id4, -25.380017 * id4, 2.546422 * id4, +- 104.605622 * id3, 141.908641 * id3, -74.322319 * id3, 7.484316 * id3, +- -37.081621 * id1, -90.397510 * id1, 42.784229 * id1, -4.289952 * id1}, +- {-56.793244 * id5, 31.153584 * id5, -5.192247 * id5, -0.000003 * id5, +- 33.541131 * id4, -34.149302 * id4, 5.691537 * id4, 0.000002 * id4, +- 87.196610 * id3, -88.995169 * id3, 14.832456 * id3, 0.000012 * id3, +- 17.288138 * id1, 71.864786 * id1, -11.977408 * id1, -0.000009 * id1}, +- {51.787796 * id5, 21.211771 * id5, -18.993730 * id5, 1.853310 * id5, +- -41.470726 * id4, -17.775823 * id4, 13.057821 * id4, -1.15823 * id4, +- -154.235673 * id3, -44.878641 * id3, 40.656077 * id3, -3.695595 * id3, +- 112.201065 * id1, 39.992155 * id1, -25.155714 * id1, 2.113984 * id1}, +- }, +- +- /* Vertical filter parameters */ +- { +- {67.601979 * id5, 0.428319 * id5, -0.071318 * id5, -0.000012 * id5, +- -3.402339 * id4, 0.000209 * id4, -0.000092 * id4, 0.000010 * id4, +- -9.180996 * id3, 6.111270 * id3, -1.024457 * id3, 0.001043 * id3, +- 6.060315 * id1, -0.017425 * id1, 0.007830 * id1, -0.000869 * id1}, +- {6.755647 * id5, 5.841348 * id5, 1.469734 * id5, -0.149656 * id5, +- 8.293120 * id4, -1.192888 * id4, -0.947652 * id4, 0.094507 * id4, +- 37.526655 * id3, 10.257875 * id3, -10.823275 * id3, 1.081497 * id3, +- -2.361928 * id1, -2.059432 * id1, 1.840671 * id1, -0.168100 * id1}, +- {-14.780391 * id5, -16.042148 * id5, 2.673692 * id5, -0.000000 * id5, +- 39.541978 * id4, 5.680053 * id4, -0.946676 * id4, 0.000000 * id4, +- 152.994486 * id3, 12.625439 * id3, -2.119579 * id3, 0.002708 * id3, +- -38.125089 * id1, -0.855880 * id1, 0.155359 * id1, -0.002245 * id1}, +- {-27.476193 * id5, -1.454976 * id5, 1.286557 * id5, 0.025346 * id5, +- 20.687300 * id4, 3.014003 * id4, -0.557786 * id4, -0.01311 * id4, +- 60.008737 * id3, -0.738273 * id3, 5.408217 * id3, -0.796798 * id3, +- -17.296835 * id1, 4.438577 * id1, -2.809420 * id1, 0.385491 * id1}, +- } +-}; +- +-static void tv_setup_filter(struct drm_encoder *encoder) +-{ +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- struct drm_display_mode *mode = &encoder->crtc->mode; +- uint32_t (*filters[])[4][7] = {&tv_enc->state.hfilter, +- &tv_enc->state.vfilter}; +- int i, j, k; +- int32_t overscan = calc_overscan(tv_enc->overscan); +- int64_t flicker = (tv_enc->flicker - 50) * (id3 / 100); +- uint64_t rs[] = {mode->hdisplay * id3, +- mode->vdisplay * id3}; +- +- do_div(rs[0], overscan * tv_norm->tv_enc_mode.hdisplay); +- do_div(rs[1], overscan * tv_norm->tv_enc_mode.vdisplay); +- +- for (k = 0; k < 2; k++) { +- rs[k] = max((int64_t)rs[k], id2); +- +- for (j = 0; j < 4; j++) { +- struct filter_params *p = &fparams[k][j]; +- +- for (i = 0; i < 7; i++) { +- int64_t c = (p->k1 + p->ki*i + p->ki2*i*i + +- p->ki3*i*i*i) +- + (p->kr + p->kir*i + p->ki2r*i*i + +- p->ki3r*i*i*i) * rs[k] +- + (p->kf + p->kif*i + p->ki2f*i*i + +- p->ki3f*i*i*i) * flicker +- + (p->krf + p->kirf*i + p->ki2rf*i*i + +- p->ki3rf*i*i*i) * flicker * rs[k]; +- +- (*filters[k])[j][i] = (c + id5/2) >> 39 +- & (0x1 << 31 | 0x7f << 9); +- } +- } +- } +-} +- +-/* Hardware state saving/restoring */ +- +-static void tv_save_filter(struct drm_device *dev, uint32_t base, +- uint32_t regs[4][7]) +-{ +- int i, j; +- uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; +- +- for (i = 0; i < 4; i++) { +- for (j = 0; j < 7; j++) +- regs[i][j] = nv_read_ptv(dev, offsets[i]+4*j); +- } +-} +- +-static void tv_load_filter(struct drm_device *dev, uint32_t base, +- uint32_t regs[4][7]) +-{ +- int i, j; +- uint32_t offsets[] = { base, base + 0x1c, base + 0x40, base + 0x5c }; +- +- for (i = 0; i < 4; i++) { +- for (j = 0; j < 7; j++) +- nv_write_ptv(dev, offsets[i]+4*j, regs[i][j]); +- } +-} +- +-void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state) +-{ +- int i; +- +- for (i = 0; i < 0x40; i++) +- state->tv_enc[i] = nv_read_tv_enc(dev, i); +- +- tv_save_filter(dev, NV_PTV_HFILTER, state->hfilter); +- tv_save_filter(dev, NV_PTV_HFILTER2, state->hfilter2); +- tv_save_filter(dev, NV_PTV_VFILTER, state->vfilter); +- +- nv_save_ptv(dev, state, 200); +- nv_save_ptv(dev, state, 204); +- nv_save_ptv(dev, state, 208); +- nv_save_ptv(dev, state, 20c); +- nv_save_ptv(dev, state, 304); +- nv_save_ptv(dev, state, 500); +- nv_save_ptv(dev, state, 504); +- nv_save_ptv(dev, state, 508); +- nv_save_ptv(dev, state, 600); +- nv_save_ptv(dev, state, 604); +- nv_save_ptv(dev, state, 608); +- nv_save_ptv(dev, state, 60c); +- nv_save_ptv(dev, state, 610); +- nv_save_ptv(dev, state, 614); +-} +- +-void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state) +-{ +- int i; +- +- for (i = 0; i < 0x40; i++) +- nv_write_tv_enc(dev, i, state->tv_enc[i]); +- +- tv_load_filter(dev, NV_PTV_HFILTER, state->hfilter); +- tv_load_filter(dev, NV_PTV_HFILTER2, state->hfilter2); +- tv_load_filter(dev, NV_PTV_VFILTER, state->vfilter); +- +- nv_load_ptv(dev, state, 200); +- nv_load_ptv(dev, state, 204); +- nv_load_ptv(dev, state, 208); +- nv_load_ptv(dev, state, 20c); +- nv_load_ptv(dev, state, 304); +- nv_load_ptv(dev, state, 500); +- nv_load_ptv(dev, state, 504); +- nv_load_ptv(dev, state, 508); +- nv_load_ptv(dev, state, 600); +- nv_load_ptv(dev, state, 604); +- nv_load_ptv(dev, state, 608); +- nv_load_ptv(dev, state, 60c); +- nv_load_ptv(dev, state, 610); +- nv_load_ptv(dev, state, 614); +- +- /* This is required for some settings to kick in. */ +- nv_write_tv_enc(dev, 0x3e, 1); +- nv_write_tv_enc(dev, 0x3e, 0); +-} +- +-/* Timings similar to the ones the blob sets */ +- +-const struct drm_display_mode nv17_tv_modes[] = { +- { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 0, +- 320, 344, 392, 560, 0, 200, 200, 202, 220, 0, +- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC +- | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CLKDIV2) }, +- { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 0, +- 320, 344, 392, 560, 0, 240, 240, 246, 263, 0, +- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC +- | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CLKDIV2) }, +- { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 0, +- 400, 432, 496, 640, 0, 300, 300, 303, 314, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC +- | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CLKDIV2) }, +- { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 0, +- 640, 672, 768, 880, 0, 480, 480, 492, 525, 0, +- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, +- { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 0, +- 720, 752, 872, 960, 0, 480, 480, 493, 525, 0, +- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, +- { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 0, +- 720, 776, 856, 960, 0, 576, 576, 588, 597, 0, +- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, +- { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 0, +- 800, 840, 920, 1040, 0, 600, 600, 604, 618, 0, +- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, +- { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 0, +- 1024, 1064, 1200, 1344, 0, 768, 768, 777, 806, 0, +- DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, +- {} +-}; +- +-void nv17_tv_update_properties(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- struct nv17_tv_state *regs = &tv_enc->state; +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- int subconnector = tv_enc->select_subconnector ? +- tv_enc->select_subconnector : +- tv_enc->subconnector; +- +- switch (subconnector) { +- case DRM_MODE_SUBCONNECTOR_Composite: +- { +- regs->ptv_204 = 0x2; +- +- /* The composite connector may be found on either pin. */ +- if (tv_enc->pin_mask & 0x4) +- regs->ptv_204 |= 0x010000; +- else if (tv_enc->pin_mask & 0x2) +- regs->ptv_204 |= 0x100000; +- else +- regs->ptv_204 |= 0x110000; +- +- regs->tv_enc[0x7] = 0x10; +- break; +- } +- case DRM_MODE_SUBCONNECTOR_SVIDEO: +- regs->ptv_204 = 0x11012; +- regs->tv_enc[0x7] = 0x18; +- break; +- +- case DRM_MODE_SUBCONNECTOR_Component: +- regs->ptv_204 = 0x111333; +- regs->tv_enc[0x7] = 0x14; +- break; +- +- case DRM_MODE_SUBCONNECTOR_SCART: +- regs->ptv_204 = 0x111012; +- regs->tv_enc[0x7] = 0x18; +- break; +- } +- +- regs->tv_enc[0x20] = interpolate(0, tv_norm->tv_enc_mode.tv_enc[0x20], +- 255, tv_enc->saturation); +- regs->tv_enc[0x22] = interpolate(0, tv_norm->tv_enc_mode.tv_enc[0x22], +- 255, tv_enc->saturation); +- regs->tv_enc[0x25] = tv_enc->hue * 255 / 100; +- +- nv_load_ptv(dev, regs, 204); +- nv_load_tv_enc(dev, regs, 7); +- nv_load_tv_enc(dev, regs, 20); +- nv_load_tv_enc(dev, regs, 22); +- nv_load_tv_enc(dev, regs, 25); +-} +- +-void nv17_tv_update_rescaler(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- struct nv17_tv_state *regs = &tv_enc->state; +- +- regs->ptv_208 = 0x40 | (calc_overscan(tv_enc->overscan) << 8); +- +- tv_setup_filter(encoder); +- +- nv_load_ptv(dev, regs, 208); +- tv_load_filter(dev, NV_PTV_HFILTER, regs->hfilter); +- tv_load_filter(dev, NV_PTV_HFILTER2, regs->hfilter2); +- tv_load_filter(dev, NV_PTV_VFILTER, regs->vfilter); +-} +- +-void nv17_ctv_update_rescaler(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- int head = nouveau_crtc(encoder->crtc)->index; +- struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; +- struct drm_display_mode *crtc_mode = &encoder->crtc->mode; +- struct drm_display_mode *output_mode = +- &get_tv_norm(encoder)->ctv_enc_mode.mode; +- int overscan, hmargin, vmargin, hratio, vratio; +- +- /* The rescaler doesn't do the right thing for interlaced modes. */ +- if (output_mode->flags & DRM_MODE_FLAG_INTERLACE) +- overscan = 100; +- else +- overscan = tv_enc->overscan; +- +- hmargin = (output_mode->hdisplay - crtc_mode->hdisplay) / 2; +- vmargin = (output_mode->vdisplay - crtc_mode->vdisplay) / 2; +- +- hmargin = interpolate(0, min(hmargin, output_mode->hdisplay/20), +- hmargin, overscan); +- vmargin = interpolate(0, min(vmargin, output_mode->vdisplay/20), +- vmargin, overscan); +- +- hratio = crtc_mode->hdisplay * 0x800 / +- (output_mode->hdisplay - 2*hmargin); +- vratio = crtc_mode->vdisplay * 0x800 / +- (output_mode->vdisplay - 2*vmargin) & ~3; +- +- regs->fp_horiz_regs[FP_VALID_START] = hmargin; +- regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1; +- regs->fp_vert_regs[FP_VALID_START] = vmargin; +- regs->fp_vert_regs[FP_VALID_END] = output_mode->vdisplay - vmargin - 1; +- +- regs->fp_debug_1 = NV_PRAMDAC_FP_DEBUG_1_YSCALE_TESTMODE_ENABLE | +- XLATE(vratio, 0, NV_PRAMDAC_FP_DEBUG_1_YSCALE_VALUE) | +- NV_PRAMDAC_FP_DEBUG_1_XSCALE_TESTMODE_ENABLE | +- XLATE(hratio, 0, NV_PRAMDAC_FP_DEBUG_1_XSCALE_VALUE); +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HVALID_START, +- regs->fp_horiz_regs[FP_VALID_START]); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HVALID_END, +- regs->fp_horiz_regs[FP_VALID_END]); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_VVALID_START, +- regs->fp_vert_regs[FP_VALID_START]); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_VVALID_END, +- regs->fp_vert_regs[FP_VALID_END]); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regs->fp_debug_1); +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c +deleted file mode 100644 +index 8061d8d0..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c ++++ /dev/null +@@ -1,249 +0,0 @@ +-/* +- * Copyright (C) 2009 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "nouveau_encoder.h" +-#include "nouveau_connector.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +-#include +- +-#include +- +-static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = { +- { +- { +- I2C_BOARD_INFO("ch7006", 0x75), +- .platform_data = &(struct ch7006_encoder_params) { +- CH7006_FORMAT_RGB24m12I, CH7006_CLOCK_MASTER, +- 0, 0, 0, +- CH7006_SYNC_SLAVE, CH7006_SYNC_SEPARATED, +- CH7006_POUT_3_3V, CH7006_ACTIVE_HSYNC +- } +- }, +- 0 +- }, +- { } +-}; +- +-int nv04_tv_identify(struct drm_device *dev, int i2c_index) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- +- return i2c->identify(i2c, i2c_index, "TV encoder", +- nv04_tv_encoder_info, NULL, NULL); +-} +- +- +-#define PLLSEL_TV_CRTC1_MASK \ +- (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1) +-#define PLLSEL_TV_CRTC2_MASK \ +- (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ +- | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) +- +-static void nv04_tv_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; +- uint8_t crtc1A; +- +- NV_DEBUG(drm, "Setting dpms mode %d on TV encoder (output %d)\n", +- mode, nv_encoder->dcb->index); +- +- state->pllsel &= ~(PLLSEL_TV_CRTC1_MASK | PLLSEL_TV_CRTC2_MASK); +- +- if (mode == DRM_MODE_DPMS_ON) { +- int head = nouveau_crtc(encoder->crtc)->index; +- crtc1A = NVReadVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX); +- +- state->pllsel |= head ? PLLSEL_TV_CRTC2_MASK : +- PLLSEL_TV_CRTC1_MASK; +- +- /* Inhibit hsync */ +- crtc1A |= 0x80; +- +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_RPC1_INDEX, crtc1A); +- } +- +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel); +- +- get_slave_funcs(encoder)->dpms(encoder, mode); +-} +- +-static void nv04_tv_bind(struct drm_device *dev, int head, bool bind) +-{ +- struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; +- +- state->tv_setup = 0; +- +- if (bind) +- state->CRTC[NV_CIO_CRE_49] |= 0x10; +- else +- state->CRTC[NV_CIO_CRE_49] &= ~0x10; +- +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_LCD__INDEX, +- state->CRTC[NV_CIO_CRE_LCD__INDEX]); +- NVWriteVgaCrtc(dev, head, NV_CIO_CRE_49, +- state->CRTC[NV_CIO_CRE_49]); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, +- state->tv_setup); +-} +- +-static void nv04_tv_prepare(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- int head = nouveau_crtc(encoder->crtc)->index; +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- +- helper->dpms(encoder, DRM_MODE_DPMS_OFF); +- +- nv04_dfp_disable(dev, head); +- +- if (nv_two_heads(dev)) +- nv04_tv_bind(dev, head ^ 1, false); +- +- nv04_tv_bind(dev, head, true); +-} +- +-static void nv04_tv_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; +- +- regp->tv_htotal = adjusted_mode->htotal; +- regp->tv_vtotal = adjusted_mode->vtotal; +- +- /* These delay the TV signals with respect to the VGA port, +- * they might be useful if we ever allow a CRTC to drive +- * multiple outputs. +- */ +- regp->tv_hskew = 1; +- regp->tv_hsync_delay = 1; +- regp->tv_hsync_delay2 = 64; +- regp->tv_vskew = 1; +- regp->tv_vsync_delay = 1; +- +- get_slave_funcs(encoder)->mode_set(encoder, mode, adjusted_mode); +-} +- +-static void nv04_tv_commit(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- +- helper->dpms(encoder, DRM_MODE_DPMS_ON); +- +- NV_DEBUG(drm, "Output %s is running on CRTC %d using output %c\n", +- nouveau_encoder_connector_get(nv_encoder)->base.name, +- nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); +-} +- +-static void nv04_tv_destroy(struct drm_encoder *encoder) +-{ +- get_slave_funcs(encoder)->destroy(encoder); +- drm_encoder_cleanup(encoder); +- +- kfree(encoder->helper_private); +- kfree(nouveau_encoder(encoder)); +-} +- +-static const struct drm_encoder_funcs nv04_tv_funcs = { +- .destroy = nv04_tv_destroy, +-}; +- +-static const struct drm_encoder_helper_funcs nv04_tv_helper_funcs = { +- .dpms = nv04_tv_dpms, +- .save = drm_i2c_encoder_save, +- .restore = drm_i2c_encoder_restore, +- .mode_fixup = drm_i2c_encoder_mode_fixup, +- .prepare = nv04_tv_prepare, +- .commit = nv04_tv_commit, +- .mode_set = nv04_tv_mode_set, +- .detect = drm_i2c_encoder_detect, +-}; +- +-int +-nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry) +-{ +- struct nouveau_encoder *nv_encoder; +- struct drm_encoder *encoder; +- struct drm_device *dev = connector->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- struct nouveau_i2c_port *port = i2c->find(i2c, entry->i2c_index); +- int type, ret; +- +- /* Ensure that we can talk to this encoder */ +- type = nv04_tv_identify(dev, entry->i2c_index); +- if (type < 0) +- return type; +- +- /* Allocate the necessary memory */ +- nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); +- if (!nv_encoder) +- return -ENOMEM; +- +- /* Initialize the common members */ +- encoder = to_drm_encoder(nv_encoder); +- +- drm_encoder_init(dev, encoder, &nv04_tv_funcs, DRM_MODE_ENCODER_TVDAC); +- drm_encoder_helper_add(encoder, &nv04_tv_helper_funcs); +- +- encoder->possible_crtcs = entry->heads; +- encoder->possible_clones = 0; +- nv_encoder->dcb = entry; +- nv_encoder->or = ffs(entry->or) - 1; +- +- /* Run the slave-specific initialization */ +- ret = drm_i2c_encoder_init(dev, to_encoder_slave(encoder), +- &port->adapter, +- &nv04_tv_encoder_info[type].dev); +- if (ret < 0) +- goto fail_cleanup; +- +- /* Attach it to the specified connector. */ +- get_slave_funcs(encoder)->create_resources(encoder, connector); +- drm_mode_connector_attach_encoder(connector, encoder); +- +- return 0; +- +-fail_cleanup: +- drm_encoder_cleanup(encoder); +- kfree(nv_encoder); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c +deleted file mode 100644 +index 72d2ab04..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c ++++ /dev/null +@@ -1,837 +0,0 @@ +-/* +- * Copyright (C) 2009 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "nouveau_encoder.h" +-#include "nouveau_connector.h" +-#include "nouveau_crtc.h" +-#include "hw.h" +-#include "tvnv17.h" +- +-MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" +- "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" +- "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" +- "\t\tDefault: PAL\n" +- "\t\t*NOTE* Ignored for cards with external TV encoders."); +-static char *nouveau_tv_norm; +-module_param_named(tv_norm, nouveau_tv_norm, charp, 0400); +- +-static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_gpio *gpio = nvkm_gpio(&drm->device); +- uint32_t testval, regoffset = nv04_dac_output_offset(encoder); +- uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, +- fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; +- uint32_t sample = 0; +- int head; +- +-#define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20) +- testval = RGB_TEST_DATA(0x82, 0xeb, 0x82); +- if (drm->vbios.tvdactestval) +- testval = drm->vbios.tvdactestval; +- +- dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset); +- head = (dacclk & 0x100) >> 8; +- +- /* Save the previous state. */ +- gpio1 = gpio->get(gpio, 0, DCB_GPIO_TVDAC1, 0xff); +- gpio0 = gpio->get(gpio, 0, DCB_GPIO_TVDAC0, 0xff); +- fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); +- fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); +- fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); +- fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL); +- test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset); +- ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c); +- ctv_14 = NVReadRAMDAC(dev, head, 0x680c14); +- ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); +- +- /* Prepare the DAC for load detection. */ +- gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, true); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, true); +- +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, +- NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | +- NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 | +- NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | +- NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS | +- NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS); +- +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0); +- +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, +- (dacclk & ~0xff) | 0x22); +- msleep(1); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, +- (dacclk & ~0xff) | 0x21); +- +- NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20); +- NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16); +- +- /* Sample pin 0x4 (usually S-video luma). */ +- NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff); +- msleep(20); +- sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) +- & 0x4 << 28; +- +- /* Sample the remaining pins. */ +- NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff); +- msleep(20); +- sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset) +- & 0xa << 28; +- +- /* Restore the previous state. */ +- NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c); +- NVWriteRAMDAC(dev, head, 0x680c14, ctv_14); +- NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk); +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); +- NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, gpio1); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, gpio0); +- +- return sample; +-} +- +-static bool +-get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- +- /* Zotac FX5200 */ +- if (nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x1035) || +- nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x2035)) { +- *pin_mask = 0xc; +- return false; +- } +- +- /* MSI nForce2 IGP */ +- if (nv_device_match(nvkm_object(device), 0x01f0, 0x1462, 0x5710)) { +- *pin_mask = 0xc; +- return false; +- } +- +- return true; +-} +- +-static enum drm_connector_status +-nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_mode_config *conf = &dev->mode_config; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- struct dcb_output *dcb = tv_enc->base.dcb; +- bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask); +- +- if (nv04_dac_in_use(encoder)) +- return connector_status_disconnected; +- +- if (reliable) { +- if (drm->device.info.chipset == 0x42 || +- drm->device.info.chipset == 0x43) +- tv_enc->pin_mask = +- nv42_tv_sample_load(encoder) >> 28 & 0xe; +- else +- tv_enc->pin_mask = +- nv17_dac_sample_load(encoder) >> 28 & 0xe; +- } +- +- switch (tv_enc->pin_mask) { +- case 0x2: +- case 0x4: +- tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite; +- break; +- case 0xc: +- tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO; +- break; +- case 0xe: +- if (dcb->tvconf.has_component_output) +- tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component; +- else +- tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART; +- break; +- default: +- tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; +- break; +- } +- +- drm_object_property_set_value(&connector->base, +- conf->tv_subconnector_property, +- tv_enc->subconnector); +- +- if (!reliable) { +- return connector_status_unknown; +- } else if (tv_enc->subconnector) { +- NV_INFO(drm, "Load detected on output %c\n", +- '@' + ffs(dcb->or)); +- return connector_status_connected; +- } else { +- return connector_status_disconnected; +- } +-} +- +-static int nv17_tv_get_ld_modes(struct drm_encoder *encoder, +- struct drm_connector *connector) +-{ +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- const struct drm_display_mode *tv_mode; +- int n = 0; +- +- for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { +- struct drm_display_mode *mode; +- +- mode = drm_mode_duplicate(encoder->dev, tv_mode); +- +- mode->clock = tv_norm->tv_enc_mode.vrefresh * +- mode->htotal / 1000 * +- mode->vtotal / 1000; +- +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- mode->clock *= 2; +- +- if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && +- mode->vdisplay == tv_norm->tv_enc_mode.vdisplay) +- mode->type |= DRM_MODE_TYPE_PREFERRED; +- +- drm_mode_probed_add(connector, mode); +- n++; +- } +- +- return n; +-} +- +-static int nv17_tv_get_hd_modes(struct drm_encoder *encoder, +- struct drm_connector *connector) +-{ +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode; +- struct drm_display_mode *mode; +- const struct { +- int hdisplay; +- int vdisplay; +- } modes[] = { +- { 640, 400 }, +- { 640, 480 }, +- { 720, 480 }, +- { 720, 576 }, +- { 800, 600 }, +- { 1024, 768 }, +- { 1280, 720 }, +- { 1280, 1024 }, +- { 1920, 1080 } +- }; +- int i, n = 0; +- +- for (i = 0; i < ARRAY_SIZE(modes); i++) { +- if (modes[i].hdisplay > output_mode->hdisplay || +- modes[i].vdisplay > output_mode->vdisplay) +- continue; +- +- if (modes[i].hdisplay == output_mode->hdisplay && +- modes[i].vdisplay == output_mode->vdisplay) { +- mode = drm_mode_duplicate(encoder->dev, output_mode); +- mode->type |= DRM_MODE_TYPE_PREFERRED; +- +- } else { +- mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, +- modes[i].vdisplay, 60, false, +- (output_mode->flags & +- DRM_MODE_FLAG_INTERLACE), false); +- } +- +- /* CVT modes are sometimes unsuitable... */ +- if (output_mode->hdisplay <= 720 +- || output_mode->hdisplay >= 1920) { +- mode->htotal = output_mode->htotal; +- mode->hsync_start = (mode->hdisplay + (mode->htotal +- - mode->hdisplay) * 9 / 10) & ~7; +- mode->hsync_end = mode->hsync_start + 8; +- } +- +- if (output_mode->vdisplay >= 1024) { +- mode->vtotal = output_mode->vtotal; +- mode->vsync_start = output_mode->vsync_start; +- mode->vsync_end = output_mode->vsync_end; +- } +- +- mode->type |= DRM_MODE_TYPE_DRIVER; +- drm_mode_probed_add(connector, mode); +- n++; +- } +- +- return n; +-} +- +-static int nv17_tv_get_modes(struct drm_encoder *encoder, +- struct drm_connector *connector) +-{ +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- +- if (tv_norm->kind == CTV_ENC_MODE) +- return nv17_tv_get_hd_modes(encoder, connector); +- else +- return nv17_tv_get_ld_modes(encoder, connector); +-} +- +-static int nv17_tv_mode_valid(struct drm_encoder *encoder, +- struct drm_display_mode *mode) +-{ +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- +- if (tv_norm->kind == CTV_ENC_MODE) { +- struct drm_display_mode *output_mode = +- &tv_norm->ctv_enc_mode.mode; +- +- if (mode->clock > 400000) +- return MODE_CLOCK_HIGH; +- +- if (mode->hdisplay > output_mode->hdisplay || +- mode->vdisplay > output_mode->vdisplay) +- return MODE_BAD; +- +- if ((mode->flags & DRM_MODE_FLAG_INTERLACE) != +- (output_mode->flags & DRM_MODE_FLAG_INTERLACE)) +- return MODE_NO_INTERLACE; +- +- if (mode->flags & DRM_MODE_FLAG_DBLSCAN) +- return MODE_NO_DBLESCAN; +- +- } else { +- const int vsync_tolerance = 600; +- +- if (mode->clock > 70000) +- return MODE_CLOCK_HIGH; +- +- if (abs(drm_mode_vrefresh(mode) * 1000 - +- tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance) +- return MODE_VSYNC; +- +- /* The encoder takes care of the actual interlacing */ +- if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- return MODE_NO_INTERLACE; +- } +- +- return MODE_OK; +-} +- +-static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- +- if (nv04_dac_in_use(encoder)) +- return false; +- +- if (tv_norm->kind == CTV_ENC_MODE) +- adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock; +- else +- adjusted_mode->clock = 90000; +- +- return true; +-} +- +-static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_gpio *gpio = nvkm_gpio(&drm->device); +- struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- +- if (nouveau_encoder(encoder)->last_dpms == mode) +- return; +- nouveau_encoder(encoder)->last_dpms = mode; +- +- NV_INFO(drm, "Setting dpms mode %d on TV encoder (output %d)\n", +- mode, nouveau_encoder(encoder)->dcb->index); +- +- regs->ptv_200 &= ~1; +- +- if (tv_norm->kind == CTV_ENC_MODE) { +- nv04_dfp_update_fp_control(encoder, mode); +- +- } else { +- nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF); +- +- if (mode == DRM_MODE_DPMS_ON) +- regs->ptv_200 |= 1; +- } +- +- nv_load_ptv(dev, regs, 200); +- +- gpio->set(gpio, 0, DCB_GPIO_TVDAC1, 0xff, mode == DRM_MODE_DPMS_ON); +- gpio->set(gpio, 0, DCB_GPIO_TVDAC0, 0xff, mode == DRM_MODE_DPMS_ON); +- +- nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); +-} +- +-static void nv17_tv_prepare(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- int head = nouveau_crtc(encoder->crtc)->index; +- uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ +- NV_CIO_CRE_LCD__INDEX]; +- uint32_t dacclk_off = NV_PRAMDAC_DACCLK + +- nv04_dac_output_offset(encoder); +- uint32_t dacclk; +- +- helper->dpms(encoder, DRM_MODE_DPMS_OFF); +- +- nv04_dfp_disable(dev, head); +- +- /* Unbind any FP encoders from this head if we need the FP +- * stuff enabled. */ +- if (tv_norm->kind == CTV_ENC_MODE) { +- struct drm_encoder *enc; +- +- list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { +- struct dcb_output *dcb = nouveau_encoder(enc)->dcb; +- +- if ((dcb->type == DCB_OUTPUT_TMDS || +- dcb->type == DCB_OUTPUT_LVDS) && +- !enc->crtc && +- nv04_dfp_get_bound_head(dev, dcb) == head) { +- nv04_dfp_bind_head(dev, dcb, head ^ 1, +- drm->vbios.fp.dual_link); +- } +- } +- +- } +- +- if (tv_norm->kind == CTV_ENC_MODE) +- *cr_lcd |= 0x1 | (head ? 0x0 : 0x8); +- +- /* Set the DACCLK register */ +- dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1; +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) +- dacclk |= 0x1a << 16; +- +- if (tv_norm->kind == CTV_ENC_MODE) { +- dacclk |= 0x20; +- +- if (head) +- dacclk |= 0x100; +- else +- dacclk &= ~0x100; +- +- } else { +- dacclk |= 0x10; +- +- } +- +- NVWriteRAMDAC(dev, 0, dacclk_off, dacclk); +-} +- +-static void nv17_tv_mode_set(struct drm_encoder *encoder, +- struct drm_display_mode *drm_mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- int head = nouveau_crtc(encoder->crtc)->index; +- struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; +- struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state; +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- int i; +- +- regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */ +- regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */ +- regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */ +- regs->tv_setup = 1; +- regs->ramdac_8c0 = 0x0; +- +- if (tv_norm->kind == TV_ENC_MODE) { +- tv_regs->ptv_200 = 0x13111100; +- if (head) +- tv_regs->ptv_200 |= 0x10; +- +- tv_regs->ptv_20c = 0x808010; +- tv_regs->ptv_304 = 0x2d00000; +- tv_regs->ptv_600 = 0x0; +- tv_regs->ptv_60c = 0x0; +- tv_regs->ptv_610 = 0x1e00000; +- +- if (tv_norm->tv_enc_mode.vdisplay == 576) { +- tv_regs->ptv_508 = 0x1200000; +- tv_regs->ptv_614 = 0x33; +- +- } else if (tv_norm->tv_enc_mode.vdisplay == 480) { +- tv_regs->ptv_508 = 0xf00000; +- tv_regs->ptv_614 = 0x13; +- } +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) { +- tv_regs->ptv_500 = 0xe8e0; +- tv_regs->ptv_504 = 0x1710; +- tv_regs->ptv_604 = 0x0; +- tv_regs->ptv_608 = 0x0; +- } else { +- if (tv_norm->tv_enc_mode.vdisplay == 576) { +- tv_regs->ptv_604 = 0x20; +- tv_regs->ptv_608 = 0x10; +- tv_regs->ptv_500 = 0x19710; +- tv_regs->ptv_504 = 0x68f0; +- +- } else if (tv_norm->tv_enc_mode.vdisplay == 480) { +- tv_regs->ptv_604 = 0x10; +- tv_regs->ptv_608 = 0x20; +- tv_regs->ptv_500 = 0x4b90; +- tv_regs->ptv_504 = 0x1b480; +- } +- } +- +- for (i = 0; i < 0x40; i++) +- tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i]; +- +- } else { +- struct drm_display_mode *output_mode = +- &tv_norm->ctv_enc_mode.mode; +- +- /* The registers in PRAMDAC+0xc00 control some timings and CSC +- * parameters for the CTV encoder (It's only used for "HD" TV +- * modes, I don't think I have enough working to guess what +- * they exactly mean...), it's probably connected at the +- * output of the FP encoder, but it also needs the analog +- * encoder in its OR enabled and routed to the head it's +- * using. It's enabled with the DACCLK register, bits [5:4]. +- */ +- for (i = 0; i < 38; i++) +- regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i]; +- +- regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; +- regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1; +- regs->fp_horiz_regs[FP_SYNC_START] = +- output_mode->hsync_start - 1; +- regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1; +- regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay + +- max((output_mode->hdisplay-600)/40 - 1, 1); +- +- regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1; +- regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1; +- regs->fp_vert_regs[FP_SYNC_START] = +- output_mode->vsync_start - 1; +- regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1; +- regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1; +- +- regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS | +- NV_PRAMDAC_FP_TG_CONTROL_READ_PROG | +- NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12; +- +- if (output_mode->flags & DRM_MODE_FLAG_PVSYNC) +- regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS; +- if (output_mode->flags & DRM_MODE_FLAG_PHSYNC) +- regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS; +- +- regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND | +- NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND | +- NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR | +- NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR | +- NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED | +- NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE | +- NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE; +- +- regs->fp_debug_2 = 0; +- +- regs->fp_margin_color = 0x801080; +- +- } +-} +- +-static void nv17_tv_commit(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct drm_encoder_helper_funcs *helper = encoder->helper_private; +- +- if (get_tv_norm(encoder)->kind == TV_ENC_MODE) { +- nv17_tv_update_rescaler(encoder); +- nv17_tv_update_properties(encoder); +- } else { +- nv17_ctv_update_rescaler(encoder); +- } +- +- nv17_tv_state_load(dev, &to_tv_enc(encoder)->state); +- +- /* This could use refinement for flatpanels, but it should work */ +- if (drm->device.info.chipset < 0x44) +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + +- nv04_dac_output_offset(encoder), +- 0xf0000000); +- else +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + +- nv04_dac_output_offset(encoder), +- 0x00100000); +- +- helper->dpms(encoder, DRM_MODE_DPMS_ON); +- +- NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n", +- nouveau_encoder_connector_get(nv_encoder)->base.name, +- nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); +-} +- +-static void nv17_tv_save(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- +- nouveau_encoder(encoder)->restore.output = +- NVReadRAMDAC(dev, 0, +- NV_PRAMDAC_DACCLK + +- nv04_dac_output_offset(encoder)); +- +- nv17_tv_state_save(dev, &tv_enc->saved_state); +- +- tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200; +-} +- +-static void nv17_tv_restore(struct drm_encoder *encoder) +-{ +- struct drm_device *dev = encoder->dev; +- +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + +- nv04_dac_output_offset(encoder), +- nouveau_encoder(encoder)->restore.output); +- +- nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state); +- +- nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED; +-} +- +-static int nv17_tv_create_resources(struct drm_encoder *encoder, +- struct drm_connector *connector) +-{ +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_mode_config *conf = &dev->mode_config; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- struct dcb_output *dcb = nouveau_encoder(encoder)->dcb; +- int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS : +- NUM_LD_TV_NORMS; +- int i; +- +- if (nouveau_tv_norm) { +- for (i = 0; i < num_tv_norms; i++) { +- if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) { +- tv_enc->tv_norm = i; +- break; +- } +- } +- +- if (i == num_tv_norms) +- NV_WARN(drm, "Invalid TV norm setting \"%s\"\n", +- nouveau_tv_norm); +- } +- +- drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names); +- +- drm_object_attach_property(&connector->base, +- conf->tv_select_subconnector_property, +- tv_enc->select_subconnector); +- drm_object_attach_property(&connector->base, +- conf->tv_subconnector_property, +- tv_enc->subconnector); +- drm_object_attach_property(&connector->base, +- conf->tv_mode_property, +- tv_enc->tv_norm); +- drm_object_attach_property(&connector->base, +- conf->tv_flicker_reduction_property, +- tv_enc->flicker); +- drm_object_attach_property(&connector->base, +- conf->tv_saturation_property, +- tv_enc->saturation); +- drm_object_attach_property(&connector->base, +- conf->tv_hue_property, +- tv_enc->hue); +- drm_object_attach_property(&connector->base, +- conf->tv_overscan_property, +- tv_enc->overscan); +- +- return 0; +-} +- +-static int nv17_tv_set_property(struct drm_encoder *encoder, +- struct drm_connector *connector, +- struct drm_property *property, +- uint64_t val) +-{ +- struct drm_mode_config *conf = &encoder->dev->mode_config; +- struct drm_crtc *crtc = encoder->crtc; +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); +- bool modes_changed = false; +- +- if (property == conf->tv_overscan_property) { +- tv_enc->overscan = val; +- if (encoder->crtc) { +- if (tv_norm->kind == CTV_ENC_MODE) +- nv17_ctv_update_rescaler(encoder); +- else +- nv17_tv_update_rescaler(encoder); +- } +- +- } else if (property == conf->tv_saturation_property) { +- if (tv_norm->kind != TV_ENC_MODE) +- return -EINVAL; +- +- tv_enc->saturation = val; +- nv17_tv_update_properties(encoder); +- +- } else if (property == conf->tv_hue_property) { +- if (tv_norm->kind != TV_ENC_MODE) +- return -EINVAL; +- +- tv_enc->hue = val; +- nv17_tv_update_properties(encoder); +- +- } else if (property == conf->tv_flicker_reduction_property) { +- if (tv_norm->kind != TV_ENC_MODE) +- return -EINVAL; +- +- tv_enc->flicker = val; +- if (encoder->crtc) +- nv17_tv_update_rescaler(encoder); +- +- } else if (property == conf->tv_mode_property) { +- if (connector->dpms != DRM_MODE_DPMS_OFF) +- return -EINVAL; +- +- tv_enc->tv_norm = val; +- +- modes_changed = true; +- +- } else if (property == conf->tv_select_subconnector_property) { +- if (tv_norm->kind != TV_ENC_MODE) +- return -EINVAL; +- +- tv_enc->select_subconnector = val; +- nv17_tv_update_properties(encoder); +- +- } else { +- return -EINVAL; +- } +- +- if (modes_changed) { +- drm_helper_probe_single_connector_modes(connector, 0, 0); +- +- /* Disable the crtc to ensure a full modeset is +- * performed whenever it's turned on again. */ +- if (crtc) { +- struct drm_mode_set modeset = { +- .crtc = crtc, +- }; +- +- drm_mode_set_config_internal(&modeset); +- } +- } +- +- return 0; +-} +- +-static void nv17_tv_destroy(struct drm_encoder *encoder) +-{ +- struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder); +- +- drm_encoder_cleanup(encoder); +- kfree(tv_enc); +-} +- +-static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = { +- .dpms = nv17_tv_dpms, +- .save = nv17_tv_save, +- .restore = nv17_tv_restore, +- .mode_fixup = nv17_tv_mode_fixup, +- .prepare = nv17_tv_prepare, +- .commit = nv17_tv_commit, +- .mode_set = nv17_tv_mode_set, +- .detect = nv17_tv_detect, +-}; +- +-static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = { +- .get_modes = nv17_tv_get_modes, +- .mode_valid = nv17_tv_mode_valid, +- .create_resources = nv17_tv_create_resources, +- .set_property = nv17_tv_set_property, +-}; +- +-static struct drm_encoder_funcs nv17_tv_funcs = { +- .destroy = nv17_tv_destroy, +-}; +- +-int +-nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry) +-{ +- struct drm_device *dev = connector->dev; +- struct drm_encoder *encoder; +- struct nv17_tv_encoder *tv_enc = NULL; +- +- tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL); +- if (!tv_enc) +- return -ENOMEM; +- +- tv_enc->overscan = 50; +- tv_enc->flicker = 50; +- tv_enc->saturation = 50; +- tv_enc->hue = 0; +- tv_enc->tv_norm = TV_NORM_PAL; +- tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown; +- tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic; +- tv_enc->pin_mask = 0; +- +- encoder = to_drm_encoder(&tv_enc->base); +- +- tv_enc->base.dcb = entry; +- tv_enc->base.or = ffs(entry->or) - 1; +- +- drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC); +- drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs); +- to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs; +- +- encoder->possible_crtcs = entry->heads; +- encoder->possible_clones = 0; +- +- nv17_tv_create_resources(encoder, connector); +- drm_mode_connector_attach_encoder(connector, encoder); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h +deleted file mode 100644 +index 225894cd..00000000 +--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h ++++ /dev/null +@@ -1,163 +0,0 @@ +-/* +- * Copyright (C) 2009 Francisco Jerez. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NV17_TV_H__ +-#define __NV17_TV_H__ +- +-struct nv17_tv_state { +- uint8_t tv_enc[0x40]; +- +- uint32_t hfilter[4][7]; +- uint32_t hfilter2[4][7]; +- uint32_t vfilter[4][7]; +- +- uint32_t ptv_200; +- uint32_t ptv_204; +- uint32_t ptv_208; +- uint32_t ptv_20c; +- uint32_t ptv_304; +- uint32_t ptv_500; +- uint32_t ptv_504; +- uint32_t ptv_508; +- uint32_t ptv_600; +- uint32_t ptv_604; +- uint32_t ptv_608; +- uint32_t ptv_60c; +- uint32_t ptv_610; +- uint32_t ptv_614; +-}; +- +-enum nv17_tv_norm{ +- TV_NORM_PAL, +- TV_NORM_PAL_M, +- TV_NORM_PAL_N, +- TV_NORM_PAL_NC, +- TV_NORM_NTSC_M, +- TV_NORM_NTSC_J, +- NUM_LD_TV_NORMS, +- TV_NORM_HD480I = NUM_LD_TV_NORMS, +- TV_NORM_HD480P, +- TV_NORM_HD576I, +- TV_NORM_HD576P, +- TV_NORM_HD720P, +- TV_NORM_HD1080I, +- NUM_TV_NORMS +-}; +- +-struct nv17_tv_encoder { +- struct nouveau_encoder base; +- +- struct nv17_tv_state state; +- struct nv17_tv_state saved_state; +- +- int overscan; +- int flicker; +- int saturation; +- int hue; +- enum nv17_tv_norm tv_norm; +- int subconnector; +- int select_subconnector; +- uint32_t pin_mask; +-}; +-#define to_tv_enc(x) container_of(nouveau_encoder(x), \ +- struct nv17_tv_encoder, base) +- +-extern char *nv17_tv_norm_names[NUM_TV_NORMS]; +- +-extern struct nv17_tv_norm_params { +- enum { +- TV_ENC_MODE, +- CTV_ENC_MODE, +- } kind; +- +- union { +- struct { +- int hdisplay; +- int vdisplay; +- int vrefresh; /* mHz */ +- +- uint8_t tv_enc[0x40]; +- } tv_enc_mode; +- +- struct { +- struct drm_display_mode mode; +- +- uint32_t ctv_regs[38]; +- } ctv_enc_mode; +- }; +- +-} nv17_tv_norms[NUM_TV_NORMS]; +-#define get_tv_norm(enc) (&nv17_tv_norms[to_tv_enc(enc)->tv_norm]) +- +-extern const struct drm_display_mode nv17_tv_modes[]; +- +-static inline int interpolate(int y0, int y1, int y2, int x) +-{ +- return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50; +-} +- +-void nv17_tv_state_save(struct drm_device *dev, struct nv17_tv_state *state); +-void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state); +-void nv17_tv_update_properties(struct drm_encoder *encoder); +-void nv17_tv_update_rescaler(struct drm_encoder *encoder); +-void nv17_ctv_update_rescaler(struct drm_encoder *encoder); +- +-/* TV hardware access functions */ +- +-static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg, +- uint32_t val) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- nvif_wr32(device, reg, val); +-} +- +-static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- return nvif_rd32(device, reg); +-} +- +-static inline void nv_write_tv_enc(struct drm_device *dev, uint8_t reg, +- uint8_t val) +-{ +- nv_write_ptv(dev, NV_PTV_TV_INDEX, reg); +- nv_write_ptv(dev, NV_PTV_TV_DATA, val); +-} +- +-static inline uint8_t nv_read_tv_enc(struct drm_device *dev, uint8_t reg) +-{ +- nv_write_ptv(dev, NV_PTV_TV_INDEX, reg); +- return nv_read_ptv(dev, NV_PTV_TV_DATA); +-} +- +-#define nv_load_ptv(dev, state, reg) \ +- nv_write_ptv(dev, NV_PTV_OFFSET + 0x##reg, state->ptv_##reg) +-#define nv_save_ptv(dev, state, reg) \ +- state->ptv_##reg = nv_read_ptv(dev, NV_PTV_OFFSET + 0x##reg) +-#define nv_load_tv_enc(dev, state, reg) \ +- nv_write_tv_enc(dev, 0x##reg, state->tv_enc[0x##reg]) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c +deleted file mode 100644 +index a24faa5e..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c ++++ /dev/null +@@ -1,537 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_gem.h" +-#include "nouveau_chan.h" +-#include "nouveau_abi16.h" +- +-struct nouveau_abi16 * +-nouveau_abi16_get(struct drm_file *file_priv, struct drm_device *dev) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- mutex_lock(&cli->mutex); +- if (!cli->abi16) { +- struct nouveau_abi16 *abi16; +- cli->abi16 = abi16 = kzalloc(sizeof(*abi16), GFP_KERNEL); +- if (cli->abi16) { +- struct nv_device_v0 args = { +- .device = ~0ULL, +- }; +- +- INIT_LIST_HEAD(&abi16->channels); +- +- /* allocate device object targeting client's default +- * device (ie. the one that belongs to the fd it +- * opened) +- */ +- if (nvif_device_init(&cli->base.base, NULL, +- NOUVEAU_ABI16_DEVICE, NV_DEVICE, +- &args, sizeof(args), +- &abi16->device) == 0) +- return cli->abi16; +- +- kfree(cli->abi16); +- cli->abi16 = NULL; +- } +- +- mutex_unlock(&cli->mutex); +- } +- return cli->abi16; +-} +- +-int +-nouveau_abi16_put(struct nouveau_abi16 *abi16, int ret) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&abi16->device.base); +- mutex_unlock(&cli->mutex); +- return ret; +-} +- +-u16 +-nouveau_abi16_swclass(struct nouveau_drm *drm) +-{ +- switch (drm->device.info.family) { +- case NV_DEVICE_INFO_V0_TNT: +- return 0x006e; +- case NV_DEVICE_INFO_V0_CELSIUS: +- case NV_DEVICE_INFO_V0_KELVIN: +- case NV_DEVICE_INFO_V0_RANKINE: +- case NV_DEVICE_INFO_V0_CURIE: +- return 0x016e; +- case NV_DEVICE_INFO_V0_TESLA: +- return 0x506e; +- case NV_DEVICE_INFO_V0_FERMI: +- case NV_DEVICE_INFO_V0_KEPLER: +- case NV_DEVICE_INFO_V0_MAXWELL: +- return 0x906e; +- } +- +- return 0x0000; +-} +- +-static void +-nouveau_abi16_ntfy_fini(struct nouveau_abi16_chan *chan, +- struct nouveau_abi16_ntfy *ntfy) +-{ +- nouveau_mm_free(&chan->heap, &ntfy->node); +- list_del(&ntfy->head); +- kfree(ntfy); +-} +- +-static void +-nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16, +- struct nouveau_abi16_chan *chan) +-{ +- struct nouveau_abi16_ntfy *ntfy, *temp; +- +- /* wait for all activity to stop before releasing notify object, which +- * may be still in use */ +- if (chan->chan && chan->ntfy) +- nouveau_channel_idle(chan->chan); +- +- /* cleanup notifier state */ +- list_for_each_entry_safe(ntfy, temp, &chan->notifiers, head) { +- nouveau_abi16_ntfy_fini(chan, ntfy); +- } +- +- if (chan->ntfy) { +- nouveau_bo_vma_del(chan->ntfy, &chan->ntfy_vma); +- nouveau_bo_unpin(chan->ntfy); +- drm_gem_object_unreference_unlocked(&chan->ntfy->gem); +- } +- +- if (chan->heap.block_size) +- nouveau_mm_fini(&chan->heap); +- +- /* destroy channel object, all children will be killed too */ +- if (chan->chan) { +- abi16->handles &= ~(1ULL << (chan->chan->object->handle & 0xffff)); +- nouveau_channel_del(&chan->chan); +- } +- +- list_del(&chan->head); +- kfree(chan); +-} +- +-void +-nouveau_abi16_fini(struct nouveau_abi16 *abi16) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&abi16->device.base); +- struct nouveau_abi16_chan *chan, *temp; +- +- /* cleanup channels */ +- list_for_each_entry_safe(chan, temp, &abi16->channels, head) { +- nouveau_abi16_chan_fini(abi16, chan); +- } +- +- /* destroy the device object */ +- nvif_device_fini(&abi16->device); +- +- kfree(cli->abi16); +- cli->abi16 = NULL; +-} +- +-int +-nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nouveau_timer *ptimer = nvkm_timer(device); +- struct nouveau_graph *graph = nvkm_gr(device); +- struct drm_nouveau_getparam *getparam = data; +- +- switch (getparam->param) { +- case NOUVEAU_GETPARAM_CHIPSET_ID: +- getparam->value = device->info.chipset; +- break; +- case NOUVEAU_GETPARAM_PCI_VENDOR: +- if (nv_device_is_pci(nvkm_device(device))) +- getparam->value = dev->pdev->vendor; +- else +- getparam->value = 0; +- break; +- case NOUVEAU_GETPARAM_PCI_DEVICE: +- if (nv_device_is_pci(nvkm_device(device))) +- getparam->value = dev->pdev->device; +- else +- getparam->value = 0; +- break; +- case NOUVEAU_GETPARAM_BUS_TYPE: +- if (!nv_device_is_pci(nvkm_device(device))) +- getparam->value = 3; +- else +- if (drm_pci_device_is_agp(dev)) +- getparam->value = 0; +- else +- if (!pci_is_pcie(dev->pdev)) +- getparam->value = 1; +- else +- getparam->value = 2; +- break; +- case NOUVEAU_GETPARAM_FB_SIZE: +- getparam->value = drm->gem.vram_available; +- break; +- case NOUVEAU_GETPARAM_AGP_SIZE: +- getparam->value = drm->gem.gart_available; +- break; +- case NOUVEAU_GETPARAM_VM_VRAM_BASE: +- getparam->value = 0; /* deprecated */ +- break; +- case NOUVEAU_GETPARAM_PTIMER_TIME: +- getparam->value = ptimer->read(ptimer); +- break; +- case NOUVEAU_GETPARAM_HAS_BO_USAGE: +- getparam->value = 1; +- break; +- case NOUVEAU_GETPARAM_HAS_PAGEFLIP: +- getparam->value = 1; +- break; +- case NOUVEAU_GETPARAM_GRAPH_UNITS: +- getparam->value = graph->units ? graph->units(graph) : 0; +- break; +- default: +- NV_PRINTK(debug, cli, "unknown parameter %lld\n", getparam->param); +- return -EINVAL; +- } +- +- return 0; +-} +- +-int +-nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS) +-{ +- return -EINVAL; +-} +- +-int +-nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) +-{ +- struct drm_nouveau_channel_alloc *init = data; +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); +- struct nouveau_abi16_chan *chan; +- struct nvif_device *device; +- int ret; +- +- if (unlikely(!abi16)) +- return -ENOMEM; +- +- if (!drm->channel) +- return nouveau_abi16_put(abi16, -ENODEV); +- +- device = &abi16->device; +- +- /* hack to allow channel engine type specification on kepler */ +- if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { +- if (init->fb_ctxdma_handle != ~0) +- init->fb_ctxdma_handle = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR; +- else +- init->fb_ctxdma_handle = init->tt_ctxdma_handle; +- +- /* allow flips to be executed if this is a graphics channel */ +- init->tt_ctxdma_handle = 0; +- if (init->fb_ctxdma_handle == KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR) +- init->tt_ctxdma_handle = 1; +- } +- +- if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0) +- return nouveau_abi16_put(abi16, -EINVAL); +- +- /* allocate "abi16 channel" data and make up a handle for it */ +- init->channel = __ffs64(~abi16->handles); +- if (~abi16->handles == 0) +- return nouveau_abi16_put(abi16, -ENOSPC); +- +- chan = kzalloc(sizeof(*chan), GFP_KERNEL); +- if (!chan) +- return nouveau_abi16_put(abi16, -ENOMEM); +- +- INIT_LIST_HEAD(&chan->notifiers); +- list_add(&chan->head, &abi16->channels); +- abi16->handles |= (1ULL << init->channel); +- +- /* create channel object and initialise dma and fence management */ +- ret = nouveau_channel_new(drm, device, +- NOUVEAU_ABI16_CHAN(init->channel), +- init->fb_ctxdma_handle, +- init->tt_ctxdma_handle, &chan->chan); +- if (ret) +- goto done; +- +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) +- init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | +- NOUVEAU_GEM_DOMAIN_GART; +- else +- if (chan->chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) +- init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM; +- else +- init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_GART; +- +- if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { +- init->subchan[0].handle = 0x00000000; +- init->subchan[0].grclass = 0x0000; +- init->subchan[1].handle = chan->chan->nvsw.handle; +- init->subchan[1].grclass = 0x506e; +- init->nr_subchan = 2; +- } +- +- /* Named memory object area */ +- ret = nouveau_gem_new(dev, PAGE_SIZE, 0, NOUVEAU_GEM_DOMAIN_GART, +- 0, 0, &chan->ntfy); +- if (ret == 0) +- ret = nouveau_bo_pin(chan->ntfy, TTM_PL_FLAG_TT); +- if (ret) +- goto done; +- +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_bo_vma_add(chan->ntfy, cli->vm, +- &chan->ntfy_vma); +- if (ret) +- goto done; +- } +- +- ret = drm_gem_handle_create(file_priv, &chan->ntfy->gem, +- &init->notifier_handle); +- if (ret) +- goto done; +- +- ret = nouveau_mm_init(&chan->heap, 0, PAGE_SIZE, 1); +-done: +- if (ret) +- nouveau_abi16_chan_fini(abi16, chan); +- return nouveau_abi16_put(abi16, ret); +-} +- +-static struct nouveau_abi16_chan * +-nouveau_abi16_chan(struct nouveau_abi16 *abi16, int channel) +-{ +- struct nouveau_abi16_chan *chan; +- +- list_for_each_entry(chan, &abi16->channels, head) { +- if (chan->chan->object->handle == NOUVEAU_ABI16_CHAN(channel)) +- return chan; +- } +- +- return NULL; +-} +- +-int +-nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS) +-{ +- struct drm_nouveau_channel_free *req = data; +- struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); +- struct nouveau_abi16_chan *chan; +- +- if (unlikely(!abi16)) +- return -ENOMEM; +- +- chan = nouveau_abi16_chan(abi16, req->channel); +- if (!chan) +- return nouveau_abi16_put(abi16, -ENOENT); +- nouveau_abi16_chan_fini(abi16, chan); +- return nouveau_abi16_put(abi16, 0); +-} +- +-int +-nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS) +-{ +- struct drm_nouveau_grobj_alloc *init = data; +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_new_v0 new; +- } args = { +- .ioctl.owner = NVIF_IOCTL_V0_OWNER_ANY, +- .ioctl.type = NVIF_IOCTL_V0_NEW, +- .ioctl.path_nr = 3, +- .ioctl.path[2] = NOUVEAU_ABI16_CLIENT, +- .ioctl.path[1] = NOUVEAU_ABI16_DEVICE, +- .ioctl.path[0] = NOUVEAU_ABI16_CHAN(init->channel), +- .new.route = NVDRM_OBJECT_ABI16, +- .new.handle = init->handle, +- .new.oclass = init->class, +- }; +- struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_client *client; +- int ret; +- +- if (unlikely(!abi16)) +- return -ENOMEM; +- +- if (init->handle == ~0) +- return nouveau_abi16_put(abi16, -EINVAL); +- client = nvif_client(nvif_object(&abi16->device)); +- +- /* compatibility with userspace that assumes 506e for all chipsets */ +- if (init->class == 0x506e) { +- init->class = nouveau_abi16_swclass(drm); +- if (init->class == 0x906e) +- return nouveau_abi16_put(abi16, 0); +- } +- +- ret = nvif_client_ioctl(client, &args, sizeof(args)); +- return nouveau_abi16_put(abi16, ret); +-} +- +-int +-nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) +-{ +- struct drm_nouveau_notifierobj_alloc *info = data; +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_new_v0 new; +- struct nv_dma_v0 ctxdma; +- } args = { +- .ioctl.owner = NVIF_IOCTL_V0_OWNER_ANY, +- .ioctl.type = NVIF_IOCTL_V0_NEW, +- .ioctl.path_nr = 3, +- .ioctl.path[2] = NOUVEAU_ABI16_CLIENT, +- .ioctl.path[1] = NOUVEAU_ABI16_DEVICE, +- .ioctl.path[0] = NOUVEAU_ABI16_CHAN(info->channel), +- .new.route = NVDRM_OBJECT_ABI16, +- .new.handle = info->handle, +- .new.oclass = NV_DMA_IN_MEMORY, +- }; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); +- struct nouveau_abi16_chan *chan; +- struct nouveau_abi16_ntfy *ntfy; +- struct nvif_device *device = &abi16->device; +- struct nvif_client *client; +- int ret; +- +- if (unlikely(!abi16)) +- return -ENOMEM; +- +- /* completely unnecessary for these chipsets... */ +- if (unlikely(device->info.family >= NV_DEVICE_INFO_V0_FERMI)) +- return nouveau_abi16_put(abi16, -EINVAL); +- client = nvif_client(nvif_object(&abi16->device)); +- +- chan = nouveau_abi16_chan(abi16, info->channel); +- if (!chan) +- return nouveau_abi16_put(abi16, -ENOENT); +- +- ntfy = kzalloc(sizeof(*ntfy), GFP_KERNEL); +- if (!ntfy) +- return nouveau_abi16_put(abi16, -ENOMEM); +- +- list_add(&ntfy->head, &chan->notifiers); +- ntfy->handle = info->handle; +- +- ret = nouveau_mm_head(&chan->heap, 0, 1, info->size, info->size, 1, +- &ntfy->node); +- if (ret) +- goto done; +- +- args.ctxdma.start = ntfy->node->offset; +- args.ctxdma.limit = ntfy->node->offset + ntfy->node->length - 1; +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { +- args.ctxdma.target = NV_DMA_V0_TARGET_VM; +- args.ctxdma.access = NV_DMA_V0_ACCESS_VM; +- args.ctxdma.start += chan->ntfy_vma.offset; +- args.ctxdma.limit += chan->ntfy_vma.offset; +- } else +- if (drm->agp.stat == ENABLED) { +- args.ctxdma.target = NV_DMA_V0_TARGET_AGP; +- args.ctxdma.access = NV_DMA_V0_ACCESS_RDWR; +- args.ctxdma.start += drm->agp.base + chan->ntfy->bo.offset; +- args.ctxdma.limit += drm->agp.base + chan->ntfy->bo.offset; +- client->super = true; +- } else { +- args.ctxdma.target = NV_DMA_V0_TARGET_VM; +- args.ctxdma.access = NV_DMA_V0_ACCESS_RDWR; +- args.ctxdma.start += chan->ntfy->bo.offset; +- args.ctxdma.limit += chan->ntfy->bo.offset; +- } +- +- ret = nvif_client_ioctl(client, &args, sizeof(args)); +- client->super = false; +- if (ret) +- goto done; +- +- info->offset = ntfy->node->offset; +- +-done: +- if (ret) +- nouveau_abi16_ntfy_fini(chan, ntfy); +- return nouveau_abi16_put(abi16, ret); +-} +- +-int +-nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS) +-{ +- struct drm_nouveau_gpuobj_free *fini = data; +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_del del; +- } args = { +- .ioctl.owner = NVDRM_OBJECT_ABI16, +- .ioctl.type = NVIF_IOCTL_V0_DEL, +- .ioctl.path_nr = 4, +- .ioctl.path[3] = NOUVEAU_ABI16_CLIENT, +- .ioctl.path[2] = NOUVEAU_ABI16_DEVICE, +- .ioctl.path[1] = NOUVEAU_ABI16_CHAN(fini->channel), +- .ioctl.path[0] = fini->handle, +- }; +- struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); +- struct nouveau_abi16_chan *chan; +- struct nouveau_abi16_ntfy *ntfy; +- struct nvif_client *client; +- int ret; +- +- if (unlikely(!abi16)) +- return -ENOMEM; +- +- chan = nouveau_abi16_chan(abi16, fini->channel); +- if (!chan) +- return nouveau_abi16_put(abi16, -ENOENT); +- client = nvif_client(nvif_object(&abi16->device)); +- +- /* synchronize with the user channel and destroy the gpu object */ +- nouveau_channel_idle(chan->chan); +- +- ret = nvif_client_ioctl(client, &args, sizeof(args)); +- if (ret) +- return nouveau_abi16_put(abi16, ret); +- +- /* cleanup extra state if this object was a notifier */ +- list_for_each_entry(ntfy, &chan->notifiers, head) { +- if (ntfy->handle == fini->handle) { +- nouveau_mm_free(&chan->heap, &ntfy->node); +- list_del(&ntfy->head); +- break; +- } +- } +- +- return nouveau_abi16_put(abi16, 0); +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h +deleted file mode 100644 +index 39844e6b..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_abi16.h ++++ /dev/null +@@ -1,114 +0,0 @@ +-#ifndef __NOUVEAU_ABI16_H__ +-#define __NOUVEAU_ABI16_H__ +- +-#define ABI16_IOCTL_ARGS \ +- struct drm_device *dev, void *data, struct drm_file *file_priv +- +-int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS); +-int nouveau_abi16_ioctl_setparam(ABI16_IOCTL_ARGS); +-int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS); +-int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS); +-int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS); +-int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS); +-int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS); +- +-struct nouveau_abi16_ntfy { +- struct list_head head; +- struct nouveau_mm_node *node; +- u32 handle; +-}; +- +-struct nouveau_abi16_chan { +- struct list_head head; +- struct nouveau_channel *chan; +- struct list_head notifiers; +- struct nouveau_bo *ntfy; +- struct nouveau_vma ntfy_vma; +- struct nouveau_mm heap; +-}; +- +-struct nouveau_abi16 { +- struct nvif_device device; +- struct list_head channels; +- u64 handles; +-}; +- +-struct nouveau_drm; +-struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *, struct drm_device *); +-int nouveau_abi16_put(struct nouveau_abi16 *, int); +-void nouveau_abi16_fini(struct nouveau_abi16 *); +-u16 nouveau_abi16_swclass(struct nouveau_drm *); +- +-#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) +-#define NOUVEAU_GEM_DOMAIN_GART (1 << 2) +- +-struct drm_nouveau_channel_alloc { +- uint32_t fb_ctxdma_handle; +- uint32_t tt_ctxdma_handle; +- +- int channel; +- uint32_t pushbuf_domains; +- +- /* Notifier memory */ +- uint32_t notifier_handle; +- +- /* DRM-enforced subchannel assignments */ +- struct { +- uint32_t handle; +- uint32_t grclass; +- } subchan[8]; +- uint32_t nr_subchan; +-}; +- +-struct drm_nouveau_channel_free { +- int channel; +-}; +- +-struct drm_nouveau_grobj_alloc { +- int channel; +- uint32_t handle; +- int class; +-}; +- +-struct drm_nouveau_notifierobj_alloc { +- uint32_t channel; +- uint32_t handle; +- uint32_t size; +- uint32_t offset; +-}; +- +-struct drm_nouveau_gpuobj_free { +- int channel; +- uint32_t handle; +-}; +- +-#define NOUVEAU_GETPARAM_PCI_VENDOR 3 +-#define NOUVEAU_GETPARAM_PCI_DEVICE 4 +-#define NOUVEAU_GETPARAM_BUS_TYPE 5 +-#define NOUVEAU_GETPARAM_FB_SIZE 8 +-#define NOUVEAU_GETPARAM_AGP_SIZE 9 +-#define NOUVEAU_GETPARAM_CHIPSET_ID 11 +-#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12 +-#define NOUVEAU_GETPARAM_GRAPH_UNITS 13 +-#define NOUVEAU_GETPARAM_PTIMER_TIME 14 +-#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15 +-#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16 +-struct drm_nouveau_getparam { +- uint64_t param; +- uint64_t value; +-}; +- +-struct drm_nouveau_setparam { +- uint64_t param; +- uint64_t value; +-}; +- +-#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam) +-#define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam) +-#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc) +-#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free) +-#define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc) +-#define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc) +-#define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c +deleted file mode 100644 +index 62242469..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c ++++ /dev/null +@@ -1,427 +0,0 @@ +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_acpi.h" +- +-#define NOUVEAU_DSM_LED 0x02 +-#define NOUVEAU_DSM_LED_STATE 0x00 +-#define NOUVEAU_DSM_LED_OFF 0x10 +-#define NOUVEAU_DSM_LED_STAMINA 0x11 +-#define NOUVEAU_DSM_LED_SPEED 0x12 +- +-#define NOUVEAU_DSM_POWER 0x03 +-#define NOUVEAU_DSM_POWER_STATE 0x00 +-#define NOUVEAU_DSM_POWER_SPEED 0x01 +-#define NOUVEAU_DSM_POWER_STAMINA 0x02 +- +-#define NOUVEAU_DSM_OPTIMUS_CAPS 0x1A +-#define NOUVEAU_DSM_OPTIMUS_FLAGS 0x1B +- +-#define NOUVEAU_DSM_OPTIMUS_POWERDOWN_PS3 (3 << 24) +-#define NOUVEAU_DSM_OPTIMUS_NO_POWERDOWN_PS3 (2 << 24) +-#define NOUVEAU_DSM_OPTIMUS_FLAGS_CHANGED (1) +- +-#define NOUVEAU_DSM_OPTIMUS_SET_POWERDOWN (NOUVEAU_DSM_OPTIMUS_POWERDOWN_PS3 | NOUVEAU_DSM_OPTIMUS_FLAGS_CHANGED) +- +-/* result of the optimus caps function */ +-#define OPTIMUS_ENABLED (1 << 0) +-#define OPTIMUS_STATUS_MASK (3 << 3) +-#define OPTIMUS_STATUS_OFF (0 << 3) +-#define OPTIMUS_STATUS_ON_ENABLED (1 << 3) +-#define OPTIMUS_STATUS_PWR_STABLE (3 << 3) +-#define OPTIMUS_DISPLAY_HOTPLUG (1 << 6) +-#define OPTIMUS_CAPS_MASK (7 << 24) +-#define OPTIMUS_DYNAMIC_PWR_CAP (1 << 24) +- +-#define OPTIMUS_AUDIO_CAPS_MASK (3 << 27) +-#define OPTIMUS_HDA_CODEC_MASK (2 << 27) /* hda bios control */ +- +-static struct nouveau_dsm_priv { +- bool dsm_detected; +- bool optimus_detected; +- acpi_handle dhandle; +- acpi_handle rom_handle; +-} nouveau_dsm_priv; +- +-bool nouveau_is_optimus(void) { +- return nouveau_dsm_priv.optimus_detected; +-} +- +-bool nouveau_is_v1_dsm(void) { +- return nouveau_dsm_priv.dsm_detected; +-} +- +-#define NOUVEAU_DSM_HAS_MUX 0x1 +-#define NOUVEAU_DSM_HAS_OPT 0x2 +- +-#ifdef CONFIG_VGA_SWITCHEROO +-static const char nouveau_dsm_muid[] = { +- 0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4D, +- 0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4, +-}; +- +-static const char nouveau_op_dsm_muid[] = { +- 0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47, +- 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0, +-}; +- +-static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t *result) +-{ +- int i; +- union acpi_object *obj; +- char args_buff[4]; +- union acpi_object argv4 = { +- .buffer.type = ACPI_TYPE_BUFFER, +- .buffer.length = 4, +- .buffer.pointer = args_buff +- }; +- +- /* ACPI is little endian, AABBCCDD becomes {DD,CC,BB,AA} */ +- for (i = 0; i < 4; i++) +- args_buff[i] = (arg >> i * 8) & 0xFF; +- +- *result = 0; +- obj = acpi_evaluate_dsm_typed(handle, nouveau_op_dsm_muid, 0x00000100, +- func, &argv4, ACPI_TYPE_BUFFER); +- if (!obj) { +- acpi_handle_info(handle, "failed to evaluate _DSM\n"); +- return AE_ERROR; +- } else { +- if (obj->buffer.length == 4) { +- *result |= obj->buffer.pointer[0]; +- *result |= (obj->buffer.pointer[1] << 8); +- *result |= (obj->buffer.pointer[2] << 16); +- *result |= (obj->buffer.pointer[3] << 24); +- } +- ACPI_FREE(obj); +- } +- +- return 0; +-} +- +-/* +- * On some platforms, _DSM(nouveau_op_dsm_muid, func0) has special +- * requirements on the fourth parameter, so a private implementation +- * instead of using acpi_check_dsm(). +- */ +-static int nouveau_check_optimus_dsm(acpi_handle handle) +-{ +- int result; +- +- /* +- * Function 0 returns a Buffer containing available functions. +- * The args parameter is ignored for function 0, so just put 0 in it +- */ +- if (nouveau_optimus_dsm(handle, 0, 0, &result)) +- return 0; +- +- /* +- * ACPI Spec v4 9.14.1: if bit 0 is zero, no function is supported. +- * If the n-th bit is enabled, function n is supported +- */ +- return result & 1 && result & (1 << NOUVEAU_DSM_OPTIMUS_CAPS); +-} +- +-static int nouveau_dsm(acpi_handle handle, int func, int arg) +-{ +- int ret = 0; +- union acpi_object *obj; +- union acpi_object argv4 = { +- .integer.type = ACPI_TYPE_INTEGER, +- .integer.value = arg, +- }; +- +- obj = acpi_evaluate_dsm_typed(handle, nouveau_dsm_muid, 0x00000102, +- func, &argv4, ACPI_TYPE_INTEGER); +- if (!obj) { +- acpi_handle_info(handle, "failed to evaluate _DSM\n"); +- return AE_ERROR; +- } else { +- if (obj->integer.value == 0x80000002) +- ret = -ENODEV; +- ACPI_FREE(obj); +- } +- +- return ret; +-} +- +-static int nouveau_dsm_switch_mux(acpi_handle handle, int mux_id) +-{ +- mxm_wmi_call_mxmx(mux_id == NOUVEAU_DSM_LED_STAMINA ? MXM_MXDS_ADAPTER_IGD : MXM_MXDS_ADAPTER_0); +- mxm_wmi_call_mxds(mux_id == NOUVEAU_DSM_LED_STAMINA ? MXM_MXDS_ADAPTER_IGD : MXM_MXDS_ADAPTER_0); +- return nouveau_dsm(handle, NOUVEAU_DSM_LED, mux_id); +-} +- +-static int nouveau_dsm_set_discrete_state(acpi_handle handle, enum vga_switcheroo_state state) +-{ +- int arg; +- if (state == VGA_SWITCHEROO_ON) +- arg = NOUVEAU_DSM_POWER_SPEED; +- else +- arg = NOUVEAU_DSM_POWER_STAMINA; +- nouveau_dsm(handle, NOUVEAU_DSM_POWER, arg); +- return 0; +-} +- +-static int nouveau_dsm_switchto(enum vga_switcheroo_client_id id) +-{ +- if (!nouveau_dsm_priv.dsm_detected) +- return 0; +- if (id == VGA_SWITCHEROO_IGD) +- return nouveau_dsm_switch_mux(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_LED_STAMINA); +- else +- return nouveau_dsm_switch_mux(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_LED_SPEED); +-} +- +-static int nouveau_dsm_power_state(enum vga_switcheroo_client_id id, +- enum vga_switcheroo_state state) +-{ +- if (id == VGA_SWITCHEROO_IGD) +- return 0; +- +- /* Optimus laptops have the card already disabled in +- * nouveau_switcheroo_set_state */ +- if (!nouveau_dsm_priv.dsm_detected) +- return 0; +- +- return nouveau_dsm_set_discrete_state(nouveau_dsm_priv.dhandle, state); +-} +- +-static int nouveau_dsm_get_client_id(struct pci_dev *pdev) +-{ +- /* easy option one - intel vendor ID means Integrated */ +- if (pdev->vendor == PCI_VENDOR_ID_INTEL) +- return VGA_SWITCHEROO_IGD; +- +- /* is this device on Bus 0? - this may need improving */ +- if (pdev->bus->number == 0) +- return VGA_SWITCHEROO_IGD; +- +- return VGA_SWITCHEROO_DIS; +-} +- +-static struct vga_switcheroo_handler nouveau_dsm_handler = { +- .switchto = nouveau_dsm_switchto, +- .power_state = nouveau_dsm_power_state, +- .get_client_id = nouveau_dsm_get_client_id, +-}; +- +-static int nouveau_dsm_pci_probe(struct pci_dev *pdev) +-{ +- acpi_handle dhandle; +- int retval = 0; +- +- dhandle = ACPI_HANDLE(&pdev->dev); +- if (!dhandle) +- return false; +- +- if (!acpi_has_method(dhandle, "_DSM")) +- return false; +- +- if (acpi_check_dsm(dhandle, nouveau_dsm_muid, 0x00000102, +- 1 << NOUVEAU_DSM_POWER)) +- retval |= NOUVEAU_DSM_HAS_MUX; +- +- if (nouveau_check_optimus_dsm(dhandle)) +- retval |= NOUVEAU_DSM_HAS_OPT; +- +- if (retval & NOUVEAU_DSM_HAS_OPT) { +- uint32_t result; +- nouveau_optimus_dsm(dhandle, NOUVEAU_DSM_OPTIMUS_CAPS, 0, +- &result); +- dev_info(&pdev->dev, "optimus capabilities: %s, status %s%s\n", +- (result & OPTIMUS_ENABLED) ? "enabled" : "disabled", +- (result & OPTIMUS_DYNAMIC_PWR_CAP) ? "dynamic power, " : "", +- (result & OPTIMUS_HDA_CODEC_MASK) ? "hda bios codec supported" : ""); +- } +- if (retval) +- nouveau_dsm_priv.dhandle = dhandle; +- +- return retval; +-} +- +-static bool nouveau_dsm_detect(void) +-{ +- char acpi_method_name[255] = { 0 }; +- struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name}; +- struct pci_dev *pdev = NULL; +- int has_dsm = 0; +- int has_optimus = 0; +- int vga_count = 0; +- bool guid_valid; +- int retval; +- bool ret = false; +- +- /* lookup the MXM GUID */ +- guid_valid = mxm_wmi_supported(); +- +- if (guid_valid) +- printk("MXM: GUID detected in BIOS\n"); +- +- /* now do DSM detection */ +- while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { +- vga_count++; +- +- retval = nouveau_dsm_pci_probe(pdev); +- if (retval & NOUVEAU_DSM_HAS_MUX) +- has_dsm |= 1; +- if (retval & NOUVEAU_DSM_HAS_OPT) +- has_optimus = 1; +- } +- +- while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_3D << 8, pdev)) != NULL) { +- vga_count++; +- +- retval = nouveau_dsm_pci_probe(pdev); +- if (retval & NOUVEAU_DSM_HAS_MUX) +- has_dsm |= 1; +- if (retval & NOUVEAU_DSM_HAS_OPT) +- has_optimus = 1; +- } +- +- /* find the optimus DSM or the old v1 DSM */ +- if (has_optimus == 1) { +- acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME, +- &buffer); +- printk(KERN_INFO "VGA switcheroo: detected Optimus DSM method %s handle\n", +- acpi_method_name); +- nouveau_dsm_priv.optimus_detected = true; +- ret = true; +- } else if (vga_count == 2 && has_dsm && guid_valid) { +- acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME, +- &buffer); +- printk(KERN_INFO "VGA switcheroo: detected DSM switching method %s handle\n", +- acpi_method_name); +- nouveau_dsm_priv.dsm_detected = true; +- ret = true; +- } +- +- +- return ret; +-} +- +-void nouveau_register_dsm_handler(void) +-{ +- bool r; +- +- r = nouveau_dsm_detect(); +- if (!r) +- return; +- +- vga_switcheroo_register_handler(&nouveau_dsm_handler); +-} +- +-/* Must be called for Optimus models before the card can be turned off */ +-void nouveau_switcheroo_optimus_dsm(void) +-{ +- u32 result = 0; +- if (!nouveau_dsm_priv.optimus_detected) +- return; +- +- nouveau_optimus_dsm(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_OPTIMUS_FLAGS, +- 0x3, &result); +- +- nouveau_optimus_dsm(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_OPTIMUS_CAPS, +- NOUVEAU_DSM_OPTIMUS_SET_POWERDOWN, &result); +- +-} +- +-void nouveau_unregister_dsm_handler(void) +-{ +- if (nouveau_dsm_priv.optimus_detected || nouveau_dsm_priv.dsm_detected) +- vga_switcheroo_unregister_handler(); +-} +-#else +-void nouveau_register_dsm_handler(void) {} +-void nouveau_unregister_dsm_handler(void) {} +-void nouveau_switcheroo_optimus_dsm(void) {} +-#endif +- +-/* retrieve the ROM in 4k blocks */ +-static int nouveau_rom_call(acpi_handle rom_handle, uint8_t *bios, +- int offset, int len) +-{ +- acpi_status status; +- union acpi_object rom_arg_elements[2], *obj; +- struct acpi_object_list rom_arg; +- struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL}; +- +- rom_arg.count = 2; +- rom_arg.pointer = &rom_arg_elements[0]; +- +- rom_arg_elements[0].type = ACPI_TYPE_INTEGER; +- rom_arg_elements[0].integer.value = offset; +- +- rom_arg_elements[1].type = ACPI_TYPE_INTEGER; +- rom_arg_elements[1].integer.value = len; +- +- status = acpi_evaluate_object(rom_handle, NULL, &rom_arg, &buffer); +- if (ACPI_FAILURE(status)) { +- printk(KERN_INFO "failed to evaluate ROM got %s\n", acpi_format_exception(status)); +- return -ENODEV; +- } +- obj = (union acpi_object *)buffer.pointer; +- memcpy(bios+offset, obj->buffer.pointer, len); +- kfree(buffer.pointer); +- return len; +-} +- +-bool nouveau_acpi_rom_supported(struct pci_dev *pdev) +-{ +- acpi_status status; +- acpi_handle dhandle, rom_handle; +- +- dhandle = ACPI_HANDLE(&pdev->dev); +- if (!dhandle) +- return false; +- +- status = acpi_get_handle(dhandle, "_ROM", &rom_handle); +- if (ACPI_FAILURE(status)) +- return false; +- +- nouveau_dsm_priv.rom_handle = rom_handle; +- return true; +-} +- +-int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) +-{ +- return nouveau_rom_call(nouveau_dsm_priv.rom_handle, bios, offset, len); +-} +- +-void * +-nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) +-{ +- struct acpi_device *acpidev; +- acpi_handle handle; +- int type, ret; +- void *edid; +- +- switch (connector->connector_type) { +- case DRM_MODE_CONNECTOR_LVDS: +- case DRM_MODE_CONNECTOR_eDP: +- type = ACPI_VIDEO_DISPLAY_LCD; +- break; +- default: +- return NULL; +- } +- +- handle = ACPI_HANDLE(&dev->pdev->dev); +- if (!handle) +- return NULL; +- +- ret = acpi_bus_get_device(handle, &acpidev); +- if (ret) +- return NULL; +- +- ret = acpi_video_get_edid(acpidev, type, -1, &edid); +- if (ret < 0) +- return NULL; +- +- return kmemdup(edid, EDID_LENGTH, GFP_KERNEL); +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.h b/drivers/gpu/drm/nouveau/nouveau_acpi.h +deleted file mode 100644 +index 74acf0f8..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_acpi.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-#ifndef __NOUVEAU_ACPI_H__ +-#define __NOUVEAU_ACPI_H__ +- +-#define ROM_BIOS_PAGE 4096 +- +-#if defined(CONFIG_ACPI) && defined(CONFIG_X86) +-bool nouveau_is_optimus(void); +-bool nouveau_is_v1_dsm(void); +-void nouveau_register_dsm_handler(void); +-void nouveau_unregister_dsm_handler(void); +-void nouveau_switcheroo_optimus_dsm(void); +-int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); +-bool nouveau_acpi_rom_supported(struct pci_dev *pdev); +-void *nouveau_acpi_edid(struct drm_device *, struct drm_connector *); +-#else +-static inline bool nouveau_is_optimus(void) { return false; }; +-static inline bool nouveau_is_v1_dsm(void) { return false; }; +-static inline void nouveau_register_dsm_handler(void) {} +-static inline void nouveau_unregister_dsm_handler(void) {} +-static inline void nouveau_switcheroo_optimus_dsm(void) {} +-static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } +-static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } +-static inline void *nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return NULL; } +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.c b/drivers/gpu/drm/nouveau/nouveau_agp.c +deleted file mode 100644 +index 1f6f6ba6..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_agp.c ++++ /dev/null +@@ -1,195 +0,0 @@ +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_agp.h" +-#include "nouveau_reg.h" +- +-#if __OS_HAS_AGP +-MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)"); +-static int nouveau_agpmode = -1; +-module_param_named(agpmode, nouveau_agpmode, int, 0400); +- +-struct nouveau_agpmode_quirk { +- u16 hostbridge_vendor; +- u16 hostbridge_device; +- u16 chip_vendor; +- u16 chip_device; +- int mode; +-}; +- +-static struct nouveau_agpmode_quirk nouveau_agpmode_quirk_list[] = { +- /* VIA Apollo PRO133x / GeForce FX 5600 Ultra, max agpmode 2, fdo #20341 */ +- { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_NVIDIA, 0x0311, 2 }, +- +- {}, +-}; +- +-static unsigned long +-get_agp_mode(struct nouveau_drm *drm, const struct drm_agp_info *info) +-{ +- struct nvif_device *device = &drm->device; +- struct nouveau_agpmode_quirk *quirk = nouveau_agpmode_quirk_list; +- int agpmode = nouveau_agpmode; +- unsigned long mode = info->mode; +- +- /* +- * FW seems to be broken on nv18, it makes the card lock up +- * randomly. +- */ +- if (device->info.chipset == 0x18) +- mode &= ~PCI_AGP_COMMAND_FW; +- +- /* +- * Go through the quirks list and adjust the agpmode accordingly. +- */ +- while (agpmode == -1 && quirk->hostbridge_vendor) { +- if (info->id_vendor == quirk->hostbridge_vendor && +- info->id_device == quirk->hostbridge_device && +- nvkm_device(device)->pdev->vendor == quirk->chip_vendor && +- nvkm_device(device)->pdev->device == quirk->chip_device) { +- agpmode = quirk->mode; +- NV_INFO(drm, "Forcing agp mode to %dX. Use agpmode to override.\n", +- agpmode); +- break; +- } +- ++quirk; +- } +- +- /* +- * AGP mode set in the command line. +- */ +- if (agpmode > 0) { +- bool agpv3 = mode & 0x8; +- int rate = agpv3 ? agpmode / 4 : agpmode; +- +- mode = (mode & ~0x7) | (rate & 0x7); +- } +- +- return mode; +-} +- +-static bool +-nouveau_agp_enabled(struct nouveau_drm *drm) +-{ +- struct drm_device *dev = drm->dev; +- +- if (!dev->pdev || !drm_pci_device_is_agp(dev) || !dev->agp) +- return false; +- +- if (drm->agp.stat == UNKNOWN) { +- if (!nouveau_agpmode) +- return false; +-#ifdef __powerpc__ +- /* Disable AGP by default on all PowerPC machines for +- * now -- At least some UniNorth-2 AGP bridges are +- * known to be broken: DMA from the host to the card +- * works just fine, but writeback from the card to the +- * host goes straight to memory untranslated bypassing +- * the GATT somehow, making them quite painful to deal +- * with... +- */ +- if (nouveau_agpmode == -1) +- return false; +-#endif +- return true; +- } +- +- return (drm->agp.stat == ENABLED); +-} +-#endif +- +-void +-nouveau_agp_reset(struct nouveau_drm *drm) +-{ +-#if __OS_HAS_AGP +- struct nvif_device *device = &drm->device; +- struct drm_device *dev = drm->dev; +- u32 save[2]; +- int ret; +- +- if (!nouveau_agp_enabled(drm)) +- return; +- +- /* First of all, disable fast writes, otherwise if it's +- * already enabled in the AGP bridge and we disable the card's +- * AGP controller we might be locking ourselves out of it. */ +- if ((nvif_rd32(device, NV04_PBUS_PCI_NV_19) | +- dev->agp->mode) & PCI_AGP_COMMAND_FW) { +- struct drm_agp_info info; +- struct drm_agp_mode mode; +- +- ret = drm_agp_info(dev, &info); +- if (ret) +- return; +- +- mode.mode = get_agp_mode(drm, &info); +- mode.mode &= ~PCI_AGP_COMMAND_FW; +- +- ret = drm_agp_enable(dev, mode); +- if (ret) +- return; +- } +- +- +- /* clear busmaster bit, and disable AGP */ +- save[0] = nvif_mask(device, NV04_PBUS_PCI_NV_1, 0x00000004, 0x00000000); +- nvif_wr32(device, NV04_PBUS_PCI_NV_19, 0); +- +- /* reset PGRAPH, PFIFO and PTIMER */ +- save[1] = nvif_mask(device, 0x000200, 0x00011100, 0x00000000); +- nvif_mask(device, 0x000200, 0x00011100, save[1]); +- +- /* and restore bustmaster bit (gives effect of resetting AGP) */ +- nvif_wr32(device, NV04_PBUS_PCI_NV_1, save[0]); +-#endif +-} +- +-void +-nouveau_agp_init(struct nouveau_drm *drm) +-{ +-#if __OS_HAS_AGP +- struct drm_device *dev = drm->dev; +- struct drm_agp_info info; +- struct drm_agp_mode mode; +- int ret; +- +- if (!nouveau_agp_enabled(drm)) +- return; +- drm->agp.stat = DISABLE; +- +- ret = drm_agp_acquire(dev); +- if (ret) { +- NV_ERROR(drm, "unable to acquire AGP: %d\n", ret); +- return; +- } +- +- ret = drm_agp_info(dev, &info); +- if (ret) { +- NV_ERROR(drm, "unable to get AGP info: %d\n", ret); +- return; +- } +- +- /* see agp.h for the AGPSTAT_* modes available */ +- mode.mode = get_agp_mode(drm, &info); +- +- ret = drm_agp_enable(dev, mode); +- if (ret) { +- NV_ERROR(drm, "unable to enable AGP: %d\n", ret); +- return; +- } +- +- drm->agp.stat = ENABLED; +- drm->agp.base = info.aperture_base; +- drm->agp.size = info.aperture_size; +-#endif +-} +- +-void +-nouveau_agp_fini(struct nouveau_drm *drm) +-{ +-#if __OS_HAS_AGP +- struct drm_device *dev = drm->dev; +- if (dev->agp && dev->agp->acquired) +- drm_agp_release(dev); +-#endif +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_agp.h b/drivers/gpu/drm/nouveau/nouveau_agp.h +deleted file mode 100644 +index b55c0865..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_agp.h ++++ /dev/null +@@ -1,10 +0,0 @@ +-#ifndef __NOUVEAU_AGP_H__ +-#define __NOUVEAU_AGP_H__ +- +-struct nouveau_drm; +- +-void nouveau_agp_reset(struct nouveau_drm *); +-void nouveau_agp_init(struct nouveau_drm *); +-void nouveau_agp_fini(struct nouveau_drm *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c +deleted file mode 100644 +index e566c5b5..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c ++++ /dev/null +@@ -1,254 +0,0 @@ +-/* +- * Copyright (C) 2009 Red Hat +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-/* +- * Authors: +- * Matthew Garrett +- * +- * Register locations derived from NVClock by Roderick Colenbrander +- */ +- +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "nouveau_encoder.h" +- +-static int +-nv40_get_intensity(struct backlight_device *bd) +-{ +- struct nouveau_drm *drm = bl_get_data(bd); +- struct nvif_device *device = &drm->device; +- int val = (nvif_rd32(device, NV40_PMC_BACKLIGHT) & +- NV40_PMC_BACKLIGHT_MASK) >> 16; +- +- return val; +-} +- +-static int +-nv40_set_intensity(struct backlight_device *bd) +-{ +- struct nouveau_drm *drm = bl_get_data(bd); +- struct nvif_device *device = &drm->device; +- int val = bd->props.brightness; +- int reg = nvif_rd32(device, NV40_PMC_BACKLIGHT); +- +- nvif_wr32(device, NV40_PMC_BACKLIGHT, +- (val << 16) | (reg & ~NV40_PMC_BACKLIGHT_MASK)); +- +- return 0; +-} +- +-static const struct backlight_ops nv40_bl_ops = { +- .options = BL_CORE_SUSPENDRESUME, +- .get_brightness = nv40_get_intensity, +- .update_status = nv40_set_intensity, +-}; +- +-static int +-nv40_backlight_init(struct drm_connector *connector) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nvif_device *device = &drm->device; +- struct backlight_properties props; +- struct backlight_device *bd; +- +- if (!(nvif_rd32(device, NV40_PMC_BACKLIGHT) & NV40_PMC_BACKLIGHT_MASK)) +- return 0; +- +- memset(&props, 0, sizeof(struct backlight_properties)); +- props.type = BACKLIGHT_RAW; +- props.max_brightness = 31; +- bd = backlight_device_register("nv_backlight", connector->kdev, drm, +- &nv40_bl_ops, &props); +- if (IS_ERR(bd)) +- return PTR_ERR(bd); +- drm->backlight = bd; +- bd->props.brightness = nv40_get_intensity(bd); +- backlight_update_status(bd); +- +- return 0; +-} +- +-static int +-nv50_get_intensity(struct backlight_device *bd) +-{ +- struct nouveau_encoder *nv_encoder = bl_get_data(bd); +- struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); +- struct nvif_device *device = &drm->device; +- int or = nv_encoder->or; +- u32 div = 1025; +- u32 val; +- +- val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); +- val &= NV50_PDISP_SOR_PWM_CTL_VAL; +- return ((val * 100) + (div / 2)) / div; +-} +- +-static int +-nv50_set_intensity(struct backlight_device *bd) +-{ +- struct nouveau_encoder *nv_encoder = bl_get_data(bd); +- struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); +- struct nvif_device *device = &drm->device; +- int or = nv_encoder->or; +- u32 div = 1025; +- u32 val = (bd->props.brightness * div) / 100; +- +- nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), +- NV50_PDISP_SOR_PWM_CTL_NEW | val); +- return 0; +-} +- +-static const struct backlight_ops nv50_bl_ops = { +- .options = BL_CORE_SUSPENDRESUME, +- .get_brightness = nv50_get_intensity, +- .update_status = nv50_set_intensity, +-}; +- +-static int +-nva3_get_intensity(struct backlight_device *bd) +-{ +- struct nouveau_encoder *nv_encoder = bl_get_data(bd); +- struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); +- struct nvif_device *device = &drm->device; +- int or = nv_encoder->or; +- u32 div, val; +- +- div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); +- val = nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(or)); +- val &= NVA3_PDISP_SOR_PWM_CTL_VAL; +- if (div && div >= val) +- return ((val * 100) + (div / 2)) / div; +- +- return 100; +-} +- +-static int +-nva3_set_intensity(struct backlight_device *bd) +-{ +- struct nouveau_encoder *nv_encoder = bl_get_data(bd); +- struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev); +- struct nvif_device *device = &drm->device; +- int or = nv_encoder->or; +- u32 div, val; +- +- div = nvif_rd32(device, NV50_PDISP_SOR_PWM_DIV(or)); +- val = (bd->props.brightness * div) / 100; +- if (div) { +- nvif_wr32(device, NV50_PDISP_SOR_PWM_CTL(or), val | +- NV50_PDISP_SOR_PWM_CTL_NEW | +- NVA3_PDISP_SOR_PWM_CTL_UNK); +- return 0; +- } +- +- return -EINVAL; +-} +- +-static const struct backlight_ops nva3_bl_ops = { +- .options = BL_CORE_SUSPENDRESUME, +- .get_brightness = nva3_get_intensity, +- .update_status = nva3_set_intensity, +-}; +- +-static int +-nv50_backlight_init(struct drm_connector *connector) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nvif_device *device = &drm->device; +- struct nouveau_encoder *nv_encoder; +- struct backlight_properties props; +- struct backlight_device *bd; +- const struct backlight_ops *ops; +- +- nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS); +- if (!nv_encoder) { +- nv_encoder = find_encoder(connector, DCB_OUTPUT_DP); +- if (!nv_encoder) +- return -ENODEV; +- } +- +- if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(nv_encoder->or))) +- return 0; +- +- if (device->info.chipset <= 0xa0 || +- device->info.chipset == 0xaa || +- device->info.chipset == 0xac) +- ops = &nv50_bl_ops; +- else +- ops = &nva3_bl_ops; +- +- memset(&props, 0, sizeof(struct backlight_properties)); +- props.type = BACKLIGHT_RAW; +- props.max_brightness = 100; +- bd = backlight_device_register("nv_backlight", connector->kdev, +- nv_encoder, ops, &props); +- if (IS_ERR(bd)) +- return PTR_ERR(bd); +- +- drm->backlight = bd; +- bd->props.brightness = bd->ops->get_brightness(bd); +- backlight_update_status(bd); +- return 0; +-} +- +-int +-nouveau_backlight_init(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct drm_connector *connector; +- +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS && +- connector->connector_type != DRM_MODE_CONNECTOR_eDP) +- continue; +- +- switch (device->info.family) { +- case NV_DEVICE_INFO_V0_CURIE: +- return nv40_backlight_init(connector); +- case NV_DEVICE_INFO_V0_TESLA: +- case NV_DEVICE_INFO_V0_FERMI: +- case NV_DEVICE_INFO_V0_KEPLER: +- return nv50_backlight_init(connector); +- default: +- break; +- } +- } +- +- +- return 0; +-} +- +-void +-nouveau_backlight_exit(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (drm->backlight) { +- backlight_device_unregister(drm->backlight); +- drm->backlight = NULL; +- } +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c +deleted file mode 100644 +index dae2c96d..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_bios.c ++++ /dev/null +@@ -1,2123 +0,0 @@ +-/* +- * Copyright 2005-2006 Erik Waling +- * Copyright 2006 Stephane Marchesin +- * Copyright 2007-2009 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +- * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +- * SOFTWARE. +- */ +- +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_reg.h" +-#include "dispnv04/hw.h" +-#include "nouveau_encoder.h" +- +-#include +-#include +- +-/* these defines are made up */ +-#define NV_CIO_CRE_44_HEADA 0x0 +-#define NV_CIO_CRE_44_HEADB 0x3 +-#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */ +- +-#define EDID1_LEN 128 +- +-#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) +-#define LOG_OLD_VALUE(x) +- +-struct init_exec { +- bool execute; +- bool repeat; +-}; +- +-static bool nv_cksum(const uint8_t *data, unsigned int length) +-{ +- /* +- * There's a few checksums in the BIOS, so here's a generic checking +- * function. +- */ +- int i; +- uint8_t sum = 0; +- +- for (i = 0; i < length; i++) +- sum += data[i]; +- +- if (sum) +- return true; +- +- return false; +-} +- +-static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk) +-{ +- int compare_record_len, i = 0; +- uint16_t compareclk, scriptptr = 0; +- +- if (bios->major_version < 5) /* pre BIT */ +- compare_record_len = 3; +- else +- compare_record_len = 4; +- +- do { +- compareclk = ROM16(bios->data[clktable + compare_record_len * i]); +- if (pxclk >= compareclk * 10) { +- if (bios->major_version < 5) { +- uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i]; +- scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]); +- } else +- scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]); +- break; +- } +- i++; +- } while (compareclk); +- +- return scriptptr; +-} +- +-static void +-run_digital_op_script(struct drm_device *dev, uint16_t scriptptr, +- struct dcb_output *dcbent, int head, bool dl) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- NV_INFO(drm, "0x%04X: Parsing digital output script table\n", +- scriptptr); +- NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, head ? NV_CIO_CRE_44_HEADB : +- NV_CIO_CRE_44_HEADA); +- nouveau_bios_run_init_table(dev, scriptptr, dcbent, head); +- +- nv04_dfp_bind_head(dev, dcbent, head, dl); +-} +- +-static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & DCB_OUTPUT_C ? 1 : 0); +- uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]); +- +- if (!bios->fp.xlated_entry || !sub || !scriptofs) +- return -EINVAL; +- +- run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link); +- +- if (script == LVDS_PANEL_OFF) { +- /* off-on delay in ms */ +- mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7])); +- } +-#ifdef __powerpc__ +- /* Powerbook specific quirks */ +- if (script == LVDS_RESET && +- (dev->pdev->device == 0x0179 || dev->pdev->device == 0x0189 || +- dev->pdev->device == 0x0329)) +- nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72); +-#endif +- +- return 0; +-} +- +-static int run_lvds_table(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script, int pxclk) +-{ +- /* +- * The BIT LVDS table's header has the information to setup the +- * necessary registers. Following the standard 4 byte header are: +- * A bitmask byte and a dual-link transition pxclk value for use in +- * selecting the init script when not using straps; 4 script pointers +- * for panel power, selected by output and on/off; and 8 table pointers +- * for panel init, the needed one determined by output, and bits in the +- * conf byte. These tables are similar to the TMDS tables, consisting +- * of a list of pxclks and script pointers. +- */ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- unsigned int outputset = (dcbent->or == 4) ? 1 : 0; +- uint16_t scriptptr = 0, clktable; +- +- /* +- * For now we assume version 3.0 table - g80 support will need some +- * changes +- */ +- +- switch (script) { +- case LVDS_INIT: +- return -ENOSYS; +- case LVDS_BACKLIGHT_ON: +- case LVDS_PANEL_ON: +- scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]); +- break; +- case LVDS_BACKLIGHT_OFF: +- case LVDS_PANEL_OFF: +- scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]); +- break; +- case LVDS_RESET: +- clktable = bios->fp.lvdsmanufacturerpointer + 15; +- if (dcbent->or == 4) +- clktable += 8; +- +- if (dcbent->lvdsconf.use_straps_for_mode) { +- if (bios->fp.dual_link) +- clktable += 4; +- if (bios->fp.if_is_24bit) +- clktable += 2; +- } else { +- /* using EDID */ +- int cmpval_24bit = (dcbent->or == 4) ? 4 : 1; +- +- if (bios->fp.dual_link) { +- clktable += 4; +- cmpval_24bit <<= 1; +- } +- +- if (bios->fp.strapless_is_24bit & cmpval_24bit) +- clktable += 2; +- } +- +- clktable = ROM16(bios->data[clktable]); +- if (!clktable) { +- NV_ERROR(drm, "Pixel clock comparison table not found\n"); +- return -ENOENT; +- } +- scriptptr = clkcmptable(bios, clktable, pxclk); +- } +- +- if (!scriptptr) { +- NV_ERROR(drm, "LVDS output init script not found\n"); +- return -ENOENT; +- } +- run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link); +- +- return 0; +-} +- +-int call_lvds_script(struct drm_device *dev, struct dcb_output *dcbent, int head, enum LVDS_script script, int pxclk) +-{ +- /* +- * LVDS operations are multiplexed in an effort to present a single API +- * which works with two vastly differing underlying structures. +- * This acts as the demux +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nvbios *bios = &drm->vbios; +- uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; +- uint32_t sel_clk_binding, sel_clk; +- int ret; +- +- if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver || +- (lvds_ver >= 0x30 && script == LVDS_INIT)) +- return 0; +- +- if (!bios->fp.lvds_init_run) { +- bios->fp.lvds_init_run = true; +- call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk); +- } +- +- if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change) +- call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk); +- if (script == LVDS_RESET && bios->fp.power_off_for_reset) +- call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk); +- +- NV_INFO(drm, "Calling LVDS script %d:\n", script); +- +- /* don't let script change pll->head binding */ +- sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; +- +- if (lvds_ver < 0x30) +- ret = call_lvds_manufacturer_script(dev, dcbent, head, script); +- else +- ret = run_lvds_table(dev, dcbent, head, script, pxclk); +- +- bios->fp.last_script_invoc = (script << 1 | head); +- +- sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); +- /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */ +- nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0); +- +- return ret; +-} +- +-struct lvdstableheader { +- uint8_t lvds_ver, headerlen, recordlen; +-}; +- +-static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth) +-{ +- /* +- * BMP version (0xa) LVDS table has a simple header of version and +- * record length. The BIT LVDS table has the typical BIT table header: +- * version byte, header length byte, record length byte, and a byte for +- * the maximum number of records that can be held in the table. +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t lvds_ver, headerlen, recordlen; +- +- memset(lth, 0, sizeof(struct lvdstableheader)); +- +- if (bios->fp.lvdsmanufacturerpointer == 0x0) { +- NV_ERROR(drm, "Pointer to LVDS manufacturer table invalid\n"); +- return -EINVAL; +- } +- +- lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer]; +- +- switch (lvds_ver) { +- case 0x0a: /* pre NV40 */ +- headerlen = 2; +- recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; +- break; +- case 0x30: /* NV4x */ +- headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; +- if (headerlen < 0x1f) { +- NV_ERROR(drm, "LVDS table header not understood\n"); +- return -EINVAL; +- } +- recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; +- break; +- case 0x40: /* G80/G90 */ +- headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1]; +- if (headerlen < 0x7) { +- NV_ERROR(drm, "LVDS table header not understood\n"); +- return -EINVAL; +- } +- recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2]; +- break; +- default: +- NV_ERROR(drm, +- "LVDS table revision %d.%d not currently supported\n", +- lvds_ver >> 4, lvds_ver & 0xf); +- return -ENOSYS; +- } +- +- lth->lvds_ver = lvds_ver; +- lth->headerlen = headerlen; +- lth->recordlen = recordlen; +- +- return 0; +-} +- +-static int +-get_fp_strap(struct drm_device *dev, struct nvbios *bios) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- +- /* +- * The fp strap is normally dictated by the "User Strap" in +- * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the +- * Internal_Flags struct at 0x48 is set, the user strap gets overriden +- * by the PCI subsystem ID during POST, but not before the previous user +- * strap has been committed to CR58 for CR57=0xf on head A, which may be +- * read and used instead +- */ +- +- if (bios->major_version < 5 && bios->data[0x48] & 0x4) +- return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf; +- +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) +- return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 24) & 0xf; +- else +- return (nvif_rd32(device, NV_PEXTDEV_BOOT_0) >> 16) & 0xf; +-} +- +-static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t *fptable; +- uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex; +- int ret, ofs, fpstrapping; +- struct lvdstableheader lth; +- +- if (bios->fp.fptablepointer == 0x0) { +- /* Apple cards don't have the fp table; the laptops use DDC */ +- /* The table is also missing on some x86 IGPs */ +-#ifndef __powerpc__ +- NV_ERROR(drm, "Pointer to flat panel table invalid\n"); +-#endif +- bios->digital_min_front_porch = 0x4b; +- return 0; +- } +- +- fptable = &bios->data[bios->fp.fptablepointer]; +- fptable_ver = fptable[0]; +- +- switch (fptable_ver) { +- /* +- * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no +- * version field, and miss one of the spread spectrum/PWM bytes. +- * This could affect early GF2Go parts (not seen any appropriate ROMs +- * though). Here we assume that a version of 0x05 matches this case +- * (combining with a BMP version check would be better), as the +- * common case for the panel type field is 0x0005, and that is in +- * fact what we are reading the first byte of. +- */ +- case 0x05: /* some NV10, 11, 15, 16 */ +- recordlen = 42; +- ofs = -1; +- break; +- case 0x10: /* some NV15/16, and NV11+ */ +- recordlen = 44; +- ofs = 0; +- break; +- case 0x20: /* NV40+ */ +- headerlen = fptable[1]; +- recordlen = fptable[2]; +- fpentries = fptable[3]; +- /* +- * fptable[4] is the minimum +- * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap +- */ +- bios->digital_min_front_porch = fptable[4]; +- ofs = -7; +- break; +- default: +- NV_ERROR(drm, +- "FP table revision %d.%d not currently supported\n", +- fptable_ver >> 4, fptable_ver & 0xf); +- return -ENOSYS; +- } +- +- if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */ +- return 0; +- +- ret = parse_lvds_manufacturer_table_header(dev, bios, <h); +- if (ret) +- return ret; +- +- if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) { +- bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer + +- lth.headerlen + 1; +- bios->fp.xlatwidth = lth.recordlen; +- } +- if (bios->fp.fpxlatetableptr == 0x0) { +- NV_ERROR(drm, "Pointer to flat panel xlat table invalid\n"); +- return -EINVAL; +- } +- +- fpstrapping = get_fp_strap(dev, bios); +- +- fpindex = bios->data[bios->fp.fpxlatetableptr + +- fpstrapping * bios->fp.xlatwidth]; +- +- if (fpindex > fpentries) { +- NV_ERROR(drm, "Bad flat panel table index\n"); +- return -ENOENT; +- } +- +- /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */ +- if (lth.lvds_ver > 0x10) +- bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf; +- +- /* +- * If either the strap or xlated fpindex value are 0xf there is no +- * panel using a strap-derived bios mode present. this condition +- * includes, but is different from, the DDC panel indicator above +- */ +- if (fpstrapping == 0xf || fpindex == 0xf) +- return 0; +- +- bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen + +- recordlen * fpindex + ofs; +- +- NV_INFO(drm, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n", +- ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1, +- ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1, +- ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10); +- +- return 0; +-} +- +-bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr]; +- +- if (!mode) /* just checking whether we can produce a mode */ +- return bios->fp.mode_ptr; +- +- memset(mode, 0, sizeof(struct drm_display_mode)); +- /* +- * For version 1.0 (version in byte 0): +- * bytes 1-2 are "panel type", including bits on whether Colour/mono, +- * single/dual link, and type (TFT etc.) +- * bytes 3-6 are bits per colour in RGBX +- */ +- mode->clock = ROM16(mode_entry[7]) * 10; +- /* bytes 9-10 is HActive */ +- mode->hdisplay = ROM16(mode_entry[11]) + 1; +- /* +- * bytes 13-14 is HValid Start +- * bytes 15-16 is HValid End +- */ +- mode->hsync_start = ROM16(mode_entry[17]) + 1; +- mode->hsync_end = ROM16(mode_entry[19]) + 1; +- mode->htotal = ROM16(mode_entry[21]) + 1; +- /* bytes 23-24, 27-30 similarly, but vertical */ +- mode->vdisplay = ROM16(mode_entry[25]) + 1; +- mode->vsync_start = ROM16(mode_entry[31]) + 1; +- mode->vsync_end = ROM16(mode_entry[33]) + 1; +- mode->vtotal = ROM16(mode_entry[35]) + 1; +- mode->flags |= (mode_entry[37] & 0x10) ? +- DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; +- mode->flags |= (mode_entry[37] & 0x1) ? +- DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; +- /* +- * bytes 38-39 relate to spread spectrum settings +- * bytes 40-43 are something to do with PWM +- */ +- +- mode->status = MODE_OK; +- mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; +- drm_mode_set_name(mode); +- return bios->fp.mode_ptr; +-} +- +-int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit) +-{ +- /* +- * The LVDS table header is (mostly) described in +- * parse_lvds_manufacturer_table_header(): the BIT header additionally +- * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if +- * straps are not being used for the panel, this specifies the frequency +- * at which modes should be set up in the dual link style. +- * +- * Following the header, the BMP (ver 0xa) table has several records, +- * indexed by a separate xlat table, indexed in turn by the fp strap in +- * EXTDEV_BOOT. Each record had a config byte, followed by 6 script +- * numbers for use by INIT_SUB which controlled panel init and power, +- * and finally a dword of ms to sleep between power off and on +- * operations. +- * +- * In the BIT versions, the table following the header serves as an +- * integrated config and xlat table: the records in the table are +- * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has +- * two bytes - the first as a config byte, the second for indexing the +- * fp mode table pointed to by the BIT 'D' table +- * +- * DDC is not used until after card init, so selecting the correct table +- * entry and setting the dual link flag for EDID equipped panels, +- * requiring tests against the native-mode pixel clock, cannot be done +- * until later, when this function should be called with non-zero pxclk +- */ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0; +- struct lvdstableheader lth; +- uint16_t lvdsofs; +- int ret, chip_version = bios->chip_version; +- +- ret = parse_lvds_manufacturer_table_header(dev, bios, <h); +- if (ret) +- return ret; +- +- switch (lth.lvds_ver) { +- case 0x0a: /* pre NV40 */ +- lvdsmanufacturerindex = bios->data[ +- bios->fp.fpxlatemanufacturertableptr + +- fpstrapping]; +- +- /* we're done if this isn't the EDID panel case */ +- if (!pxclk) +- break; +- +- if (chip_version < 0x25) { +- /* nv17 behaviour +- * +- * It seems the old style lvds script pointer is reused +- * to select 18/24 bit colour depth for EDID panels. +- */ +- lvdsmanufacturerindex = +- (bios->legacy.lvds_single_a_script_ptr & 1) ? +- 2 : 0; +- if (pxclk >= bios->fp.duallink_transition_clk) +- lvdsmanufacturerindex++; +- } else if (chip_version < 0x30) { +- /* nv28 behaviour (off-chip encoder) +- * +- * nv28 does a complex dance of first using byte 121 of +- * the EDID to choose the lvdsmanufacturerindex, then +- * later attempting to match the EDID manufacturer and +- * product IDs in a table (signature 'pidt' (panel id +- * table?)), setting an lvdsmanufacturerindex of 0 and +- * an fp strap of the match index (or 0xf if none) +- */ +- lvdsmanufacturerindex = 0; +- } else { +- /* nv31, nv34 behaviour */ +- lvdsmanufacturerindex = 0; +- if (pxclk >= bios->fp.duallink_transition_clk) +- lvdsmanufacturerindex = 2; +- if (pxclk >= 140000) +- lvdsmanufacturerindex = 3; +- } +- +- /* +- * nvidia set the high nibble of (cr57=f, cr58) to +- * lvdsmanufacturerindex in this case; we don't +- */ +- break; +- case 0x30: /* NV4x */ +- case 0x40: /* G80/G90 */ +- lvdsmanufacturerindex = fpstrapping; +- break; +- default: +- NV_ERROR(drm, "LVDS table revision not currently supported\n"); +- return -ENOSYS; +- } +- +- lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex; +- switch (lth.lvds_ver) { +- case 0x0a: +- bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1; +- bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2; +- bios->fp.dual_link = bios->data[lvdsofs] & 4; +- bios->fp.link_c_increment = bios->data[lvdsofs] & 8; +- *if_is_24bit = bios->data[lvdsofs] & 16; +- break; +- case 0x30: +- case 0x40: +- /* +- * No sign of the "power off for reset" or "reset for panel +- * on" bits, but it's safer to assume we should +- */ +- bios->fp.power_off_for_reset = true; +- bios->fp.reset_after_pclk_change = true; +- +- /* +- * It's ok lvdsofs is wrong for nv4x edid case; dual_link is +- * over-written, and if_is_24bit isn't used +- */ +- bios->fp.dual_link = bios->data[lvdsofs] & 1; +- bios->fp.if_is_24bit = bios->data[lvdsofs] & 2; +- bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4]; +- bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10; +- break; +- } +- +- /* set dual_link flag for EDID case */ +- if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) +- bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); +- +- *dl = bios->fp.dual_link; +- +- return 0; +-} +- +-int run_tmds_table(struct drm_device *dev, struct dcb_output *dcbent, int head, int pxclk) +-{ +- /* +- * the pxclk parameter is in kHz +- * +- * This runs the TMDS regs setting code found on BIT bios cards +- * +- * For ffs(or) == 1 use the first table, for ffs(or) == 2 and +- * ffs(or) == 3, use the second. +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nvbios *bios = &drm->vbios; +- int cv = bios->chip_version; +- uint16_t clktable = 0, scriptptr; +- uint32_t sel_clk_binding, sel_clk; +- +- /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */ +- if (cv >= 0x17 && cv != 0x1a && cv != 0x20 && +- dcbent->location != DCB_LOC_ON_CHIP) +- return 0; +- +- switch (ffs(dcbent->or)) { +- case 1: +- clktable = bios->tmds.output0_script_ptr; +- break; +- case 2: +- case 3: +- clktable = bios->tmds.output1_script_ptr; +- break; +- } +- +- if (!clktable) { +- NV_ERROR(drm, "Pixel clock comparison table not found\n"); +- return -EINVAL; +- } +- +- scriptptr = clkcmptable(bios, clktable, pxclk); +- +- if (!scriptptr) { +- NV_ERROR(drm, "TMDS output init script not found\n"); +- return -ENOENT; +- } +- +- /* don't let script change pll->head binding */ +- sel_clk_binding = nvif_rd32(device, NV_PRAMDAC_SEL_CLK) & 0x50000; +- run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000); +- sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000; +- NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding); +- +- return 0; +-} +- +-static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset) +-{ +- /* +- * Parses the init table segment for pointers used in script execution. +- * +- * offset + 0 (16 bits): init script tables pointer +- * offset + 2 (16 bits): macro index table pointer +- * offset + 4 (16 bits): macro table pointer +- * offset + 6 (16 bits): condition table pointer +- * offset + 8 (16 bits): io condition table pointer +- * offset + 10 (16 bits): io flag condition table pointer +- * offset + 12 (16 bits): init function table pointer +- */ +- +- bios->init_script_tbls_ptr = ROM16(bios->data[offset]); +-} +- +-static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) +-{ +- /* +- * Parses the load detect values for g80 cards. +- * +- * offset + 0 (16 bits): loadval table pointer +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint16_t load_table_ptr; +- uint8_t version, headerlen, entrylen, num_entries; +- +- if (bitentry->length != 3) { +- NV_ERROR(drm, "Do not understand BIT A table\n"); +- return -EINVAL; +- } +- +- load_table_ptr = ROM16(bios->data[bitentry->offset]); +- +- if (load_table_ptr == 0x0) { +- NV_DEBUG(drm, "Pointer to BIT loadval table invalid\n"); +- return -EINVAL; +- } +- +- version = bios->data[load_table_ptr]; +- +- if (version != 0x10) { +- NV_ERROR(drm, "BIT loadval table version %d.%d not supported\n", +- version >> 4, version & 0xF); +- return -ENOSYS; +- } +- +- headerlen = bios->data[load_table_ptr + 1]; +- entrylen = bios->data[load_table_ptr + 2]; +- num_entries = bios->data[load_table_ptr + 3]; +- +- if (headerlen != 4 || entrylen != 4 || num_entries != 2) { +- NV_ERROR(drm, "Do not understand BIT loadval table\n"); +- return -EINVAL; +- } +- +- /* First entry is normal dac, 2nd tv-out perhaps? */ +- bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff; +- +- return 0; +-} +- +-static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) +-{ +- /* +- * Parses the flat panel table segment that the bit entry points to. +- * Starting at bitentry->offset: +- * +- * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte +- * records beginning with a freq. +- * offset + 2 (16 bits): mode table pointer +- */ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (bitentry->length != 4) { +- NV_ERROR(drm, "Do not understand BIT display table\n"); +- return -EINVAL; +- } +- +- bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]); +- +- return 0; +-} +- +-static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) +-{ +- /* +- * Parses the init table segment that the bit entry points to. +- * +- * See parse_script_table_pointers for layout +- */ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (bitentry->length < 14) { +- NV_ERROR(drm, "Do not understand init table\n"); +- return -EINVAL; +- } +- +- parse_script_table_pointers(bios, bitentry->offset); +- return 0; +-} +- +-static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) +-{ +- /* +- * BIT 'i' (info?) table +- * +- * offset + 0 (32 bits): BIOS version dword (as in B table) +- * offset + 5 (8 bits): BIOS feature byte (same as for BMP?) +- * offset + 13 (16 bits): pointer to table containing DAC load +- * detection comparison values +- * +- * There's other things in the table, purpose unknown +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint16_t daccmpoffset; +- uint8_t dacver, dacheaderlen; +- +- if (bitentry->length < 6) { +- NV_ERROR(drm, "BIT i table too short for needed information\n"); +- return -EINVAL; +- } +- +- /* +- * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's +- * Quadro identity crisis), other bits possibly as for BMP feature byte +- */ +- bios->feature_byte = bios->data[bitentry->offset + 5]; +- bios->is_mobile = bios->feature_byte & FEATURE_MOBILE; +- +- if (bitentry->length < 15) { +- NV_WARN(drm, "BIT i table not long enough for DAC load " +- "detection comparison table\n"); +- return -EINVAL; +- } +- +- daccmpoffset = ROM16(bios->data[bitentry->offset + 13]); +- +- /* doesn't exist on g80 */ +- if (!daccmpoffset) +- return 0; +- +- /* +- * The first value in the table, following the header, is the +- * comparison value, the second entry is a comparison value for +- * TV load detection. +- */ +- +- dacver = bios->data[daccmpoffset]; +- dacheaderlen = bios->data[daccmpoffset + 1]; +- +- if (dacver != 0x00 && dacver != 0x10) { +- NV_WARN(drm, "DAC load detection comparison table version " +- "%d.%d not known\n", dacver >> 4, dacver & 0xf); +- return -ENOSYS; +- } +- +- bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]); +- bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]); +- +- return 0; +-} +- +-static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) +-{ +- /* +- * Parses the LVDS table segment that the bit entry points to. +- * Starting at bitentry->offset: +- * +- * offset + 0 (16 bits): LVDS strap xlate table pointer +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (bitentry->length != 2) { +- NV_ERROR(drm, "Do not understand BIT LVDS table\n"); +- return -EINVAL; +- } +- +- /* +- * No idea if it's still called the LVDS manufacturer table, but +- * the concept's close enough. +- */ +- bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]); +- +- return 0; +-} +- +-static int +-parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, +- struct bit_entry *bitentry) +-{ +- /* +- * offset + 2 (8 bits): number of options in an +- * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set +- * offset + 3 (16 bits): pointer to strap xlate table for RAM +- * restrict option selection +- * +- * There's a bunch of bits in this table other than the RAM restrict +- * stuff that we don't use - their use currently unknown +- */ +- +- /* +- * Older bios versions don't have a sufficiently long table for +- * what we want +- */ +- if (bitentry->length < 0x5) +- return 0; +- +- if (bitentry->version < 2) { +- bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; +- bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); +- } else { +- bios->ram_restrict_group_count = bios->data[bitentry->offset + 0]; +- bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]); +- } +- +- return 0; +-} +- +-static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry) +-{ +- /* +- * Parses the pointer to the TMDS table +- * +- * Starting at bitentry->offset: +- * +- * offset + 0 (16 bits): TMDS table pointer +- * +- * The TMDS table is typically found just before the DCB table, with a +- * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being +- * length?) +- * +- * At offset +7 is a pointer to a script, which I don't know how to +- * run yet. +- * At offset +9 is a pointer to another script, likewise +- * Offset +11 has a pointer to a table where the first word is a pxclk +- * frequency and the second word a pointer to a script, which should be +- * run if the comparison pxclk frequency is less than the pxclk desired. +- * This repeats for decreasing comparison frequencies +- * Offset +13 has a pointer to a similar table +- * The selection of table (and possibly +7/+9 script) is dictated by +- * "or" from the DCB. +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint16_t tmdstableptr, script1, script2; +- +- if (bitentry->length != 2) { +- NV_ERROR(drm, "Do not understand BIT TMDS table\n"); +- return -EINVAL; +- } +- +- tmdstableptr = ROM16(bios->data[bitentry->offset]); +- if (!tmdstableptr) { +- NV_ERROR(drm, "Pointer to TMDS table invalid\n"); +- return -EINVAL; +- } +- +- NV_INFO(drm, "TMDS table version %d.%d\n", +- bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf); +- +- /* nv50+ has v2.0, but we don't parse it atm */ +- if (bios->data[tmdstableptr] != 0x11) +- return -ENOSYS; +- +- /* +- * These two scripts are odd: they don't seem to get run even when +- * they are not stubbed. +- */ +- script1 = ROM16(bios->data[tmdstableptr + 7]); +- script2 = ROM16(bios->data[tmdstableptr + 9]); +- if (bios->data[script1] != 'q' || bios->data[script2] != 'q') +- NV_WARN(drm, "TMDS table script pointers not stubbed\n"); +- +- bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]); +- bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]); +- +- return 0; +-} +- +-struct bit_table { +- const char id; +- int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *); +-}; +- +-#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) +- +-int +-bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- u8 entries, *entry; +- +- if (bios->type != NVBIOS_BIT) +- return -ENODEV; +- +- entries = bios->data[bios->offset + 10]; +- entry = &bios->data[bios->offset + 12]; +- while (entries--) { +- if (entry[0] == id) { +- bit->id = entry[0]; +- bit->version = entry[1]; +- bit->length = ROM16(entry[2]); +- bit->offset = ROM16(entry[4]); +- bit->data = ROMPTR(dev, entry[4]); +- return 0; +- } +- +- entry += bios->data[bios->offset + 9]; +- } +- +- return -ENOENT; +-} +- +-static int +-parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, +- struct bit_table *table) +-{ +- struct drm_device *dev = bios->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct bit_entry bitentry; +- +- if (bit_table(dev, table->id, &bitentry) == 0) +- return table->parse_fn(dev, bios, &bitentry); +- +- NV_INFO(drm, "BIT table '%c' not found\n", table->id); +- return -ENOSYS; +-} +- +-static int +-parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset) +-{ +- int ret; +- +- /* +- * The only restriction on parsing order currently is having 'i' first +- * for use of bios->*_version or bios->feature_byte while parsing; +- * functions shouldn't be actually *doing* anything apart from pulling +- * data from the image into the bios struct, thus no interdependencies +- */ +- ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i)); +- if (ret) /* info? */ +- return ret; +- if (bios->major_version >= 0x60) /* g80+ */ +- parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A)); +- parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display)); +- ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init)); +- if (ret) +- return ret; +- parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */ +- parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); +- parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds)); +- +- return 0; +-} +- +-static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset) +-{ +- /* +- * Parses the BMP structure for useful things, but does not act on them +- * +- * offset + 5: BMP major version +- * offset + 6: BMP minor version +- * offset + 9: BMP feature byte +- * offset + 10: BCD encoded BIOS version +- * +- * offset + 18: init script table pointer (for bios versions < 5.10h) +- * offset + 20: extra init script table pointer (for bios +- * versions < 5.10h) +- * +- * offset + 24: memory init table pointer (used on early bios versions) +- * offset + 26: SDR memory sequencing setup data table +- * offset + 28: DDR memory sequencing setup data table +- * +- * offset + 54: index of I2C CRTC pair to use for CRT output +- * offset + 55: index of I2C CRTC pair to use for TV output +- * offset + 56: index of I2C CRTC pair to use for flat panel output +- * offset + 58: write CRTC index for I2C pair 0 +- * offset + 59: read CRTC index for I2C pair 0 +- * offset + 60: write CRTC index for I2C pair 1 +- * offset + 61: read CRTC index for I2C pair 1 +- * +- * offset + 67: maximum internal PLL frequency (single stage PLL) +- * offset + 71: minimum internal PLL frequency (single stage PLL) +- * +- * offset + 75: script table pointers, as described in +- * parse_script_table_pointers +- * +- * offset + 89: TMDS single link output A table pointer +- * offset + 91: TMDS single link output B table pointer +- * offset + 95: LVDS single link output A table pointer +- * offset + 105: flat panel timings table pointer +- * offset + 107: flat panel strapping translation table pointer +- * offset + 117: LVDS manufacturer panel config table pointer +- * offset + 119: LVDS manufacturer strapping translation table pointer +- * +- * offset + 142: PLL limits table pointer +- * +- * offset + 156: minimum pixel clock for LVDS dual link +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor; +- uint16_t bmplength; +- uint16_t legacy_scripts_offset, legacy_i2c_offset; +- +- /* load needed defaults in case we can't parse this info */ +- bios->digital_min_front_porch = 0x4b; +- bios->fmaxvco = 256000; +- bios->fminvco = 128000; +- bios->fp.duallink_transition_clk = 90000; +- +- bmp_version_major = bmp[5]; +- bmp_version_minor = bmp[6]; +- +- NV_INFO(drm, "BMP version %d.%d\n", +- bmp_version_major, bmp_version_minor); +- +- /* +- * Make sure that 0x36 is blank and can't be mistaken for a DCB +- * pointer on early versions +- */ +- if (bmp_version_major < 5) +- *(uint16_t *)&bios->data[0x36] = 0; +- +- /* +- * Seems that the minor version was 1 for all major versions prior +- * to 5. Version 6 could theoretically exist, but I suspect BIT +- * happened instead. +- */ +- if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) { +- NV_ERROR(drm, "You have an unsupported BMP version. " +- "Please send in your bios\n"); +- return -ENOSYS; +- } +- +- if (bmp_version_major == 0) +- /* nothing that's currently useful in this version */ +- return 0; +- else if (bmp_version_major == 1) +- bmplength = 44; /* exact for 1.01 */ +- else if (bmp_version_major == 2) +- bmplength = 48; /* exact for 2.01 */ +- else if (bmp_version_major == 3) +- bmplength = 54; +- /* guessed - mem init tables added in this version */ +- else if (bmp_version_major == 4 || bmp_version_minor < 0x1) +- /* don't know if 5.0 exists... */ +- bmplength = 62; +- /* guessed - BMP I2C indices added in version 4*/ +- else if (bmp_version_minor < 0x6) +- bmplength = 67; /* exact for 5.01 */ +- else if (bmp_version_minor < 0x10) +- bmplength = 75; /* exact for 5.06 */ +- else if (bmp_version_minor == 0x10) +- bmplength = 89; /* exact for 5.10h */ +- else if (bmp_version_minor < 0x14) +- bmplength = 118; /* exact for 5.11h */ +- else if (bmp_version_minor < 0x24) +- /* +- * Not sure of version where pll limits came in; +- * certainly exist by 0x24 though. +- */ +- /* length not exact: this is long enough to get lvds members */ +- bmplength = 123; +- else if (bmp_version_minor < 0x27) +- /* +- * Length not exact: this is long enough to get pll limit +- * member +- */ +- bmplength = 144; +- else +- /* +- * Length not exact: this is long enough to get dual link +- * transition clock. +- */ +- bmplength = 158; +- +- /* checksum */ +- if (nv_cksum(bmp, 8)) { +- NV_ERROR(drm, "Bad BMP checksum\n"); +- return -EINVAL; +- } +- +- /* +- * Bit 4 seems to indicate either a mobile bios or a quadro card -- +- * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl +- * (not nv10gl), bit 5 that the flat panel tables are present, and +- * bit 6 a tv bios. +- */ +- bios->feature_byte = bmp[9]; +- +- if (bmp_version_major < 5 || bmp_version_minor < 0x10) +- bios->old_style_init = true; +- legacy_scripts_offset = 18; +- if (bmp_version_major < 2) +- legacy_scripts_offset -= 4; +- bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]); +- bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]); +- +- if (bmp_version_major > 2) { /* appears in BMP 3 */ +- bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]); +- bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]); +- bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]); +- } +- +- legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */ +- if (bmplength > 61) +- legacy_i2c_offset = offset + 54; +- bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; +- bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; +- bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; +- +- if (bmplength > 74) { +- bios->fmaxvco = ROM32(bmp[67]); +- bios->fminvco = ROM32(bmp[71]); +- } +- if (bmplength > 88) +- parse_script_table_pointers(bios, offset + 75); +- if (bmplength > 94) { +- bios->tmds.output0_script_ptr = ROM16(bmp[89]); +- bios->tmds.output1_script_ptr = ROM16(bmp[91]); +- /* +- * Never observed in use with lvds scripts, but is reused for +- * 18/24 bit panel interface default for EDID equipped panels +- * (if_is_24bit not set directly to avoid any oscillation). +- */ +- bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]); +- } +- if (bmplength > 108) { +- bios->fp.fptablepointer = ROM16(bmp[105]); +- bios->fp.fpxlatetableptr = ROM16(bmp[107]); +- bios->fp.xlatwidth = 1; +- } +- if (bmplength > 120) { +- bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]); +- bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]); +- } +-#if 0 +- if (bmplength > 143) +- bios->pll_limit_tbl_ptr = ROM16(bmp[142]); +-#endif +- +- if (bmplength > 157) +- bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10; +- +- return 0; +-} +- +-static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) +-{ +- int i, j; +- +- for (i = 0; i <= (n - len); i++) { +- for (j = 0; j < len; j++) +- if (data[i + j] != str[j]) +- break; +- if (j == len) +- return i; +- } +- +- return 0; +-} +- +-void * +-olddcb_table(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- u8 *dcb = NULL; +- +- if (drm->device.info.family > NV_DEVICE_INFO_V0_TNT) +- dcb = ROMPTR(dev, drm->vbios.data[0x36]); +- if (!dcb) { +- NV_WARN(drm, "No DCB data found in VBIOS\n"); +- return NULL; +- } +- +- if (dcb[0] >= 0x41) { +- NV_WARN(drm, "DCB version 0x%02x unknown\n", dcb[0]); +- return NULL; +- } else +- if (dcb[0] >= 0x30) { +- if (ROM32(dcb[6]) == 0x4edcbdcb) +- return dcb; +- } else +- if (dcb[0] >= 0x20) { +- if (ROM32(dcb[4]) == 0x4edcbdcb) +- return dcb; +- } else +- if (dcb[0] >= 0x15) { +- if (!memcmp(&dcb[-7], "DEV_REC", 7)) +- return dcb; +- } else { +- /* +- * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but +- * always has the same single (crt) entry, even when tv-out +- * present, so the conclusion is this version cannot really +- * be used. +- * +- * v1.2 tables (some NV6/10, and NV15+) normally have the +- * same 5 entries, which are not specific to the card and so +- * no use. +- * +- * v1.2 does have an I2C table that read_dcb_i2c_table can +- * handle, but cards exist (nv11 in #14821) with a bad i2c +- * table pointer, so use the indices parsed in +- * parse_bmp_structure. +- * +- * v1.1 (NV5+, maybe some NV4) is entirely unhelpful +- */ +- NV_WARN(drm, "No useful DCB data in VBIOS\n"); +- return NULL; +- } +- +- NV_WARN(drm, "DCB header validation failed\n"); +- return NULL; +-} +- +-void * +-olddcb_outp(struct drm_device *dev, u8 idx) +-{ +- u8 *dcb = olddcb_table(dev); +- if (dcb && dcb[0] >= 0x30) { +- if (idx < dcb[2]) +- return dcb + dcb[1] + (idx * dcb[3]); +- } else +- if (dcb && dcb[0] >= 0x20) { +- u8 *i2c = ROMPTR(dev, dcb[2]); +- u8 *ent = dcb + 8 + (idx * 8); +- if (i2c && ent < i2c) +- return ent; +- } else +- if (dcb && dcb[0] >= 0x15) { +- u8 *i2c = ROMPTR(dev, dcb[2]); +- u8 *ent = dcb + 4 + (idx * 10); +- if (i2c && ent < i2c) +- return ent; +- } +- +- return NULL; +-} +- +-int +-olddcb_outp_foreach(struct drm_device *dev, void *data, +- int (*exec)(struct drm_device *, void *, int idx, u8 *outp)) +-{ +- int ret, idx = -1; +- u8 *outp = NULL; +- while ((outp = olddcb_outp(dev, ++idx))) { +- if (ROM32(outp[0]) == 0x00000000) +- break; /* seen on an NV11 with DCB v1.5 */ +- if (ROM32(outp[0]) == 0xffffffff) +- break; /* seen on an NV17 with DCB v2.0 */ +- +- if ((outp[0] & 0x0f) == DCB_OUTPUT_UNUSED) +- continue; +- if ((outp[0] & 0x0f) == DCB_OUTPUT_EOL) +- break; +- +- ret = exec(dev, data, idx, outp); +- if (ret) +- return ret; +- } +- +- return 0; +-} +- +-u8 * +-olddcb_conntab(struct drm_device *dev) +-{ +- u8 *dcb = olddcb_table(dev); +- if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) { +- u8 *conntab = ROMPTR(dev, dcb[0x14]); +- if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40) +- return conntab; +- } +- return NULL; +-} +- +-u8 * +-olddcb_conn(struct drm_device *dev, u8 idx) +-{ +- u8 *conntab = olddcb_conntab(dev); +- if (conntab && idx < conntab[2]) +- return conntab + conntab[1] + (idx * conntab[3]); +- return NULL; +-} +- +-static struct dcb_output *new_dcb_entry(struct dcb_table *dcb) +-{ +- struct dcb_output *entry = &dcb->entry[dcb->entries]; +- +- memset(entry, 0, sizeof(struct dcb_output)); +- entry->index = dcb->entries++; +- +- return entry; +-} +- +-static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c, +- int heads, int or) +-{ +- struct dcb_output *entry = new_dcb_entry(dcb); +- +- entry->type = type; +- entry->i2c_index = i2c; +- entry->heads = heads; +- if (type != DCB_OUTPUT_ANALOG) +- entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */ +- entry->or = or; +-} +- +-static bool +-parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, +- uint32_t conn, uint32_t conf, struct dcb_output *entry) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- int link = 0; +- +- entry->type = conn & 0xf; +- entry->i2c_index = (conn >> 4) & 0xf; +- entry->heads = (conn >> 8) & 0xf; +- entry->connector = (conn >> 12) & 0xf; +- entry->bus = (conn >> 16) & 0xf; +- entry->location = (conn >> 20) & 0x3; +- entry->or = (conn >> 24) & 0xf; +- +- switch (entry->type) { +- case DCB_OUTPUT_ANALOG: +- /* +- * Although the rest of a CRT conf dword is usually +- * zeros, mac biosen have stuff there so we must mask +- */ +- entry->crtconf.maxfreq = (dcb->version < 0x30) ? +- (conf & 0xffff) * 10 : +- (conf & 0xff) * 10000; +- break; +- case DCB_OUTPUT_LVDS: +- { +- uint32_t mask; +- if (conf & 0x1) +- entry->lvdsconf.use_straps_for_mode = true; +- if (dcb->version < 0x22) { +- mask = ~0xd; +- /* +- * The laptop in bug 14567 lies and claims to not use +- * straps when it does, so assume all DCB 2.0 laptops +- * use straps, until a broken EDID using one is produced +- */ +- entry->lvdsconf.use_straps_for_mode = true; +- /* +- * Both 0x4 and 0x8 show up in v2.0 tables; assume they +- * mean the same thing (probably wrong, but might work) +- */ +- if (conf & 0x4 || conf & 0x8) +- entry->lvdsconf.use_power_scripts = true; +- } else { +- mask = ~0x7; +- if (conf & 0x2) +- entry->lvdsconf.use_acpi_for_edid = true; +- if (conf & 0x4) +- entry->lvdsconf.use_power_scripts = true; +- entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4; +- link = entry->lvdsconf.sor.link; +- } +- if (conf & mask) { +- /* +- * Until we even try to use these on G8x, it's +- * useless reporting unknown bits. They all are. +- */ +- if (dcb->version >= 0x40) +- break; +- +- NV_ERROR(drm, "Unknown LVDS configuration bits, " +- "please report\n"); +- } +- break; +- } +- case DCB_OUTPUT_TV: +- { +- if (dcb->version >= 0x30) +- entry->tvconf.has_component_output = conf & (0x8 << 4); +- else +- entry->tvconf.has_component_output = false; +- +- break; +- } +- case DCB_OUTPUT_DP: +- entry->dpconf.sor.link = (conf & 0x00000030) >> 4; +- entry->extdev = (conf & 0x0000ff00) >> 8; +- switch ((conf & 0x00e00000) >> 21) { +- case 0: +- entry->dpconf.link_bw = 162000; +- break; +- case 1: +- entry->dpconf.link_bw = 270000; +- break; +- default: +- entry->dpconf.link_bw = 540000; +- break; +- } +- switch ((conf & 0x0f000000) >> 24) { +- case 0xf: +- entry->dpconf.link_nr = 4; +- break; +- case 0x3: +- entry->dpconf.link_nr = 2; +- break; +- default: +- entry->dpconf.link_nr = 1; +- break; +- } +- link = entry->dpconf.sor.link; +- break; +- case DCB_OUTPUT_TMDS: +- if (dcb->version >= 0x40) { +- entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4; +- entry->extdev = (conf & 0x0000ff00) >> 8; +- link = entry->tmdsconf.sor.link; +- } +- else if (dcb->version >= 0x30) +- entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8; +- else if (dcb->version >= 0x22) +- entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; +- break; +- case DCB_OUTPUT_EOL: +- /* weird g80 mobile type that "nv" treats as a terminator */ +- dcb->entries--; +- return false; +- default: +- break; +- } +- +- if (dcb->version < 0x40) { +- /* Normal entries consist of a single bit, but dual link has +- * the next most significant bit set too +- */ +- entry->duallink_possible = +- ((1 << (ffs(entry->or) - 1)) * 3 == entry->or); +- } else { +- entry->duallink_possible = (entry->sorconf.link == 3); +- } +- +- /* unsure what DCB version introduces this, 3.0? */ +- if (conf & 0x100000) +- entry->i2c_upper_default = true; +- +- entry->hasht = (entry->location << 4) | entry->type; +- entry->hashm = (entry->heads << 8) | (link << 6) | entry->or; +- return true; +-} +- +-static bool +-parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, +- uint32_t conn, uint32_t conf, struct dcb_output *entry) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- switch (conn & 0x0000000f) { +- case 0: +- entry->type = DCB_OUTPUT_ANALOG; +- break; +- case 1: +- entry->type = DCB_OUTPUT_TV; +- break; +- case 2: +- case 4: +- if (conn & 0x10) +- entry->type = DCB_OUTPUT_LVDS; +- else +- entry->type = DCB_OUTPUT_TMDS; +- break; +- case 3: +- entry->type = DCB_OUTPUT_LVDS; +- break; +- default: +- NV_ERROR(drm, "Unknown DCB type %d\n", conn & 0x0000000f); +- return false; +- } +- +- entry->i2c_index = (conn & 0x0003c000) >> 14; +- entry->heads = ((conn & 0x001c0000) >> 18) + 1; +- entry->or = entry->heads; /* same as heads, hopefully safe enough */ +- entry->location = (conn & 0x01e00000) >> 21; +- entry->bus = (conn & 0x0e000000) >> 25; +- entry->duallink_possible = false; +- +- switch (entry->type) { +- case DCB_OUTPUT_ANALOG: +- entry->crtconf.maxfreq = (conf & 0xffff) * 10; +- break; +- case DCB_OUTPUT_TV: +- entry->tvconf.has_component_output = false; +- break; +- case DCB_OUTPUT_LVDS: +- if ((conn & 0x00003f00) >> 8 != 0x10) +- entry->lvdsconf.use_straps_for_mode = true; +- entry->lvdsconf.use_power_scripts = true; +- break; +- default: +- break; +- } +- +- return true; +-} +- +-static +-void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) +-{ +- /* +- * DCB v2.0 lists each output combination separately. +- * Here we merge compatible entries to have fewer outputs, with +- * more options +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- int i, newentries = 0; +- +- for (i = 0; i < dcb->entries; i++) { +- struct dcb_output *ient = &dcb->entry[i]; +- int j; +- +- for (j = i + 1; j < dcb->entries; j++) { +- struct dcb_output *jent = &dcb->entry[j]; +- +- if (jent->type == 100) /* already merged entry */ +- continue; +- +- /* merge heads field when all other fields the same */ +- if (jent->i2c_index == ient->i2c_index && +- jent->type == ient->type && +- jent->location == ient->location && +- jent->or == ient->or) { +- NV_INFO(drm, "Merging DCB entries %d and %d\n", +- i, j); +- ient->heads |= jent->heads; +- jent->type = 100; /* dummy value */ +- } +- } +- } +- +- /* Compact entries merged into others out of dcb */ +- for (i = 0; i < dcb->entries; i++) { +- if (dcb->entry[i].type == 100) +- continue; +- +- if (newentries != i) { +- dcb->entry[newentries] = dcb->entry[i]; +- dcb->entry[newentries].index = newentries; +- } +- newentries++; +- } +- +- dcb->entries = newentries; +-} +- +-static bool +-apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct dcb_table *dcb = &drm->vbios.dcb; +- +- /* Dell Precision M6300 +- * DCB entry 2: 02025312 00000010 +- * DCB entry 3: 02026312 00000020 +- * +- * Identical, except apparently a different connector on a +- * different SOR link. Not a clue how we're supposed to know +- * which one is in use if it even shares an i2c line... +- * +- * Ignore the connector on the second SOR link to prevent +- * nasty problems until this is sorted (assuming it's not a +- * VBIOS bug). +- */ +- if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) { +- if (*conn == 0x02026312 && *conf == 0x00000020) +- return false; +- } +- +- /* GeForce3 Ti 200 +- * +- * DCB reports an LVDS output that should be TMDS: +- * DCB entry 1: f2005014 ffffffff +- */ +- if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) { +- if (*conn == 0xf2005014 && *conf == 0xffffffff) { +- fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS, 1, 1, 1); +- return false; +- } +- } +- +- /* XFX GT-240X-YA +- * +- * So many things wrong here, replace the entire encoder table.. +- */ +- if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) { +- if (idx == 0) { +- *conn = 0x02001300; /* VGA, connector 1 */ +- *conf = 0x00000028; +- } else +- if (idx == 1) { +- *conn = 0x01010312; /* DVI, connector 0 */ +- *conf = 0x00020030; +- } else +- if (idx == 2) { +- *conn = 0x01010310; /* VGA, connector 0 */ +- *conf = 0x00000028; +- } else +- if (idx == 3) { +- *conn = 0x02022362; /* HDMI, connector 2 */ +- *conf = 0x00020010; +- } else { +- *conn = 0x0000000e; /* EOL */ +- *conf = 0x00000000; +- } +- } +- +- /* Some other twisted XFX board (rhbz#694914) +- * +- * The DVI/VGA encoder combo that's supposed to represent the +- * DVI-I connector actually point at two different ones, and +- * the HDMI connector ends up paired with the VGA instead. +- * +- * Connector table is missing anything for VGA at all, pointing it +- * an invalid conntab entry 2 so we figure it out ourself. +- */ +- if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) { +- if (idx == 0) { +- *conn = 0x02002300; /* VGA, connector 2 */ +- *conf = 0x00000028; +- } else +- if (idx == 1) { +- *conn = 0x01010312; /* DVI, connector 0 */ +- *conf = 0x00020030; +- } else +- if (idx == 2) { +- *conn = 0x04020310; /* VGA, connector 0 */ +- *conf = 0x00000028; +- } else +- if (idx == 3) { +- *conn = 0x02021322; /* HDMI, connector 1 */ +- *conf = 0x00020010; +- } else { +- *conn = 0x0000000e; /* EOL */ +- *conf = 0x00000000; +- } +- } +- +- /* fdo#50830: connector indices for VGA and DVI-I are backwards */ +- if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) { +- if (idx == 0 && *conn == 0x02000300) +- *conn = 0x02011300; +- else +- if (idx == 1 && *conn == 0x04011310) +- *conn = 0x04000310; +- else +- if (idx == 2 && *conn == 0x02011312) +- *conn = 0x02000312; +- } +- +- return true; +-} +- +-static void +-fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios) +-{ +- struct dcb_table *dcb = &bios->dcb; +- int all_heads = (nv_two_heads(dev) ? 3 : 1); +- +-#ifdef __powerpc__ +- /* Apple iMac G4 NV17 */ +- if (of_machine_is_compatible("PowerMac4,5")) { +- fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS, 0, all_heads, 1); +- fabricate_dcb_output(dcb, DCB_OUTPUT_ANALOG, 1, all_heads, 2); +- return; +- } +-#endif +- +- /* Make up some sane defaults */ +- fabricate_dcb_output(dcb, DCB_OUTPUT_ANALOG, +- bios->legacy.i2c_indices.crt, 1, 1); +- +- if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0) +- fabricate_dcb_output(dcb, DCB_OUTPUT_TV, +- bios->legacy.i2c_indices.tv, +- all_heads, 0); +- +- else if (bios->tmds.output0_script_ptr || +- bios->tmds.output1_script_ptr) +- fabricate_dcb_output(dcb, DCB_OUTPUT_TMDS, +- bios->legacy.i2c_indices.panel, +- all_heads, 1); +-} +- +-static int +-parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct dcb_table *dcb = &drm->vbios.dcb; +- u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); +- u32 conn = ROM32(outp[0]); +- bool ret; +- +- if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { +- struct dcb_output *entry = new_dcb_entry(dcb); +- +- NV_INFO(drm, "DCB outp %02d: %08x %08x\n", idx, conn, conf); +- +- if (dcb->version >= 0x20) +- ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); +- else +- ret = parse_dcb15_entry(dev, dcb, conn, conf, entry); +- if (!ret) +- return 1; /* stop parsing */ +- +- /* Ignore the I2C index for on-chip TV-out, as there +- * are cards with bogus values (nv31m in bug 23212), +- * and it's otherwise useless. +- */ +- if (entry->type == DCB_OUTPUT_TV && +- entry->location == DCB_LOC_ON_CHIP) +- entry->i2c_index = 0x0f; +- } +- +- return 0; +-} +- +-static void +-dcb_fake_connectors(struct nvbios *bios) +-{ +- struct dcb_table *dcbt = &bios->dcb; +- u8 map[16] = { }; +- int i, idx = 0; +- +- /* heuristic: if we ever get a non-zero connector field, assume +- * that all the indices are valid and we don't need fake them. +- * +- * and, as usual, a blacklist of boards with bad bios data.. +- */ +- if (!nv_match_device(bios->dev, 0x0392, 0x107d, 0x20a2)) { +- for (i = 0; i < dcbt->entries; i++) { +- if (dcbt->entry[i].connector) +- return; +- } +- } +- +- /* no useful connector info available, we need to make it up +- * ourselves. the rule here is: anything on the same i2c bus +- * is considered to be on the same connector. any output +- * without an associated i2c bus is assigned its own unique +- * connector index. +- */ +- for (i = 0; i < dcbt->entries; i++) { +- u8 i2c = dcbt->entry[i].i2c_index; +- if (i2c == 0x0f) { +- dcbt->entry[i].connector = idx++; +- } else { +- if (!map[i2c]) +- map[i2c] = ++idx; +- dcbt->entry[i].connector = map[i2c] - 1; +- } +- } +- +- /* if we created more than one connector, destroy the connector +- * table - just in case it has random, rather than stub, entries. +- */ +- if (i > 1) { +- u8 *conntab = olddcb_conntab(bios->dev); +- if (conntab) +- conntab[0] = 0x00; +- } +-} +- +-static int +-parse_dcb_table(struct drm_device *dev, struct nvbios *bios) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct dcb_table *dcb = &bios->dcb; +- u8 *dcbt, *conn; +- int idx; +- +- dcbt = olddcb_table(dev); +- if (!dcbt) { +- /* handle pre-DCB boards */ +- if (bios->type == NVBIOS_BMP) { +- fabricate_dcb_encoder_table(dev, bios); +- return 0; +- } +- +- return -EINVAL; +- } +- +- NV_INFO(drm, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf); +- +- dcb->version = dcbt[0]; +- olddcb_outp_foreach(dev, NULL, parse_dcb_entry); +- +- /* +- * apart for v2.1+ not being known for requiring merging, this +- * guarantees dcbent->index is the index of the entry in the rom image +- */ +- if (dcb->version < 0x21) +- merge_like_dcb_entries(dev, dcb); +- +- /* dump connector table entries to log, if any exist */ +- idx = -1; +- while ((conn = olddcb_conn(dev, ++idx))) { +- if (conn[0] != 0xff) { +- NV_INFO(drm, "DCB conn %02d: ", idx); +- if (olddcb_conntab(dev)[3] < 4) +- pr_cont("%04x\n", ROM16(conn[0])); +- else +- pr_cont("%08x\n", ROM32(conn[0])); +- } +- } +- dcb_fake_connectors(bios); +- return 0; +-} +- +-static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) +-{ +- /* +- * The header following the "HWSQ" signature has the number of entries, +- * and the entry size +- * +- * An entry consists of a dword to write to the sequencer control reg +- * (0x00001304), followed by the ucode bytes, written sequentially, +- * starting at reg 0x00001400 +- */ +- +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- uint8_t bytes_to_write; +- uint16_t hwsq_entry_offset; +- int i; +- +- if (bios->data[hwsq_offset] <= entry) { +- NV_ERROR(drm, "Too few entries in HW sequencer table for " +- "requested entry\n"); +- return -ENOENT; +- } +- +- bytes_to_write = bios->data[hwsq_offset + 1]; +- +- if (bytes_to_write != 36) { +- NV_ERROR(drm, "Unknown HW sequencer entry size\n"); +- return -EINVAL; +- } +- +- NV_INFO(drm, "Loading NV17 power sequencing microcode\n"); +- +- hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write; +- +- /* set sequencer control */ +- nvif_wr32(device, 0x00001304, ROM32(bios->data[hwsq_entry_offset])); +- bytes_to_write -= 4; +- +- /* write ucode */ +- for (i = 0; i < bytes_to_write; i += 4) +- nvif_wr32(device, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4])); +- +- /* twiddle NV_PBUS_DEBUG_4 */ +- nvif_wr32(device, NV_PBUS_DEBUG_4, nvif_rd32(device, NV_PBUS_DEBUG_4) | 0x18); +- +- return 0; +-} +- +-static int load_nv17_hw_sequencer_ucode(struct drm_device *dev, +- struct nvbios *bios) +-{ +- /* +- * BMP based cards, from NV17, need a microcode loading to correctly +- * control the GPIO etc for LVDS panels +- * +- * BIT based cards seem to do this directly in the init scripts +- * +- * The microcode entries are found by the "HWSQ" signature. +- */ +- +- const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' }; +- const int sz = sizeof(hwsq_signature); +- int hwsq_offset; +- +- hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz); +- if (!hwsq_offset) +- return 0; +- +- /* always use entry 0? */ +- return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0); +-} +- +-uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- const uint8_t edid_sig[] = { +- 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 }; +- uint16_t offset = 0; +- uint16_t newoffset; +- int searchlen = NV_PROM_SIZE; +- +- if (bios->fp.edid) +- return bios->fp.edid; +- +- while (searchlen) { +- newoffset = findstr(&bios->data[offset], searchlen, +- edid_sig, 8); +- if (!newoffset) +- return NULL; +- offset += newoffset; +- if (!nv_cksum(&bios->data[offset], EDID1_LEN)) +- break; +- +- searchlen -= offset; +- offset++; +- } +- +- NV_INFO(drm, "Found EDID in BIOS\n"); +- +- return bios->fp.edid = &bios->data[offset]; +-} +- +-static bool NVInitVBIOS(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_bios *bios = nvkm_bios(&drm->device); +- struct nvbios *legacy = &drm->vbios; +- +- memset(legacy, 0, sizeof(struct nvbios)); +- spin_lock_init(&legacy->lock); +- legacy->dev = dev; +- +- legacy->data = bios->data; +- legacy->length = bios->size; +- legacy->major_version = bios->version.major; +- legacy->chip_version = bios->version.chip; +- if (bios->bit_offset) { +- legacy->type = NVBIOS_BIT; +- legacy->offset = bios->bit_offset; +- return !parse_bit_structure(legacy, legacy->offset + 6); +- } else +- if (bios->bmp_offset) { +- legacy->type = NVBIOS_BMP; +- legacy->offset = bios->bmp_offset; +- return !parse_bmp_structure(dev, legacy, legacy->offset); +- } +- +- return false; +-} +- +-int +-nouveau_run_vbios_init(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- int ret = 0; +- +- /* Reset the BIOS head to 0. */ +- bios->state.crtchead = 0; +- +- if (bios->major_version < 5) /* BMP only */ +- load_nv17_hw_sequencer_ucode(dev, bios); +- +- if (bios->execute) { +- bios->fp.last_script_invoc = 0; +- bios->fp.lvds_init_run = false; +- } +- +- return ret; +-} +- +-static bool +-nouveau_bios_posted(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- unsigned htotal; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) +- return true; +- +- htotal = NVReadVgaCrtc(dev, 0, 0x06); +- htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8; +- htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4; +- htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10; +- htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11; +- return (htotal != 0); +-} +- +-int +-nouveau_bios_init(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvbios *bios = &drm->vbios; +- int ret; +- +- /* only relevant for PCI devices */ +- if (!dev->pdev) +- return 0; +- +- if (!NVInitVBIOS(dev)) +- return -ENODEV; +- +- ret = parse_dcb_table(dev, bios); +- if (ret) +- return ret; +- +- if (!bios->major_version) /* we don't run version 0 bios */ +- return 0; +- +- /* init script execution disabled */ +- bios->execute = false; +- +- /* ... unless card isn't POSTed already */ +- if (!nouveau_bios_posted(dev)) { +- NV_INFO(drm, "Adaptor not initialised, " +- "running VBIOS init tables.\n"); +- bios->execute = true; +- } +- +- ret = nouveau_run_vbios_init(dev); +- if (ret) +- return ret; +- +- /* feature_byte on BMP is poor, but init always sets CR4B */ +- if (bios->major_version < 5) +- bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40; +- +- /* all BIT systems need p_f_m_t for digital_min_front_porch */ +- if (bios->is_mobile || bios->major_version >= 5) +- ret = parse_fp_mode_table(dev, bios); +- +- /* allow subsequent scripts to execute */ +- bios->execute = true; +- +- return 0; +-} +- +-void +-nouveau_bios_takedown(struct drm_device *dev) +-{ +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h +deleted file mode 100644 +index 0067586e..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_bios.h ++++ /dev/null +@@ -1,179 +0,0 @@ +-/* +- * Copyright 2007-2008 Nouveau Project +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef __NOUVEAU_DISPBIOS_H__ +-#define __NOUVEAU_DISPBIOS_H__ +- +-#define DCB_MAX_NUM_ENTRIES 16 +-#define DCB_MAX_NUM_I2C_ENTRIES 16 +-#define DCB_MAX_NUM_GPIO_ENTRIES 32 +-#define DCB_MAX_NUM_CONNECTOR_ENTRIES 16 +- +-#define DCB_LOC_ON_CHIP 0 +- +-#define ROM16(x) le16_to_cpu(*(u16 *)&(x)) +-#define ROM32(x) le32_to_cpu(*(u32 *)&(x)) +-#define ROM48(x) ({ u8 *p = &(x); (u64)ROM16(p[4]) << 32 | ROM32(p[0]); }) +-#define ROM64(x) le64_to_cpu(*(u64 *)&(x)) +-#define ROMPTR(d,x) ({ \ +- struct nouveau_drm *drm = nouveau_drm((d)); \ +- ROM16(x) ? &drm->vbios.data[ROM16(x)] : NULL; \ +-}) +- +-struct bit_entry { +- uint8_t id; +- uint8_t version; +- uint16_t length; +- uint16_t offset; +- uint8_t *data; +-}; +- +-int bit_table(struct drm_device *, u8 id, struct bit_entry *); +- +-#include +-#include +- +-struct dcb_table { +- uint8_t version; +- int entries; +- struct dcb_output entry[DCB_MAX_NUM_ENTRIES]; +-}; +- +-enum nouveau_or { +- DCB_OUTPUT_A = (1 << 0), +- DCB_OUTPUT_B = (1 << 1), +- DCB_OUTPUT_C = (1 << 2) +-}; +- +-enum LVDS_script { +- /* Order *does* matter here */ +- LVDS_INIT = 1, +- LVDS_RESET, +- LVDS_BACKLIGHT_ON, +- LVDS_BACKLIGHT_OFF, +- LVDS_PANEL_ON, +- LVDS_PANEL_OFF +-}; +- +-struct nvbios { +- struct drm_device *dev; +- enum { +- NVBIOS_BMP, +- NVBIOS_BIT +- } type; +- uint16_t offset; +- uint32_t length; +- uint8_t *data; +- +- uint8_t chip_version; +- +- uint32_t dactestval; +- uint32_t tvdactestval; +- uint8_t digital_min_front_porch; +- bool fp_no_ddc; +- +- spinlock_t lock; +- +- bool execute; +- +- uint8_t major_version; +- uint8_t feature_byte; +- bool is_mobile; +- +- uint32_t fmaxvco, fminvco; +- +- bool old_style_init; +- uint16_t init_script_tbls_ptr; +- uint16_t extra_init_script_tbl_ptr; +- +- uint16_t ram_restrict_tbl_ptr; +- uint8_t ram_restrict_group_count; +- +- struct dcb_table dcb; +- +- struct { +- int crtchead; +- } state; +- +- struct { +- uint16_t fptablepointer; /* also used by tmds */ +- uint16_t fpxlatetableptr; +- int xlatwidth; +- uint16_t lvdsmanufacturerpointer; +- uint16_t fpxlatemanufacturertableptr; +- uint16_t mode_ptr; +- uint16_t xlated_entry; +- bool power_off_for_reset; +- bool reset_after_pclk_change; +- bool dual_link; +- bool link_c_increment; +- bool if_is_24bit; +- int duallink_transition_clk; +- uint8_t strapless_is_24bit; +- uint8_t *edid; +- +- /* will need resetting after suspend */ +- int last_script_invoc; +- bool lvds_init_run; +- } fp; +- +- struct { +- uint16_t output0_script_ptr; +- uint16_t output1_script_ptr; +- } tmds; +- +- struct { +- uint16_t mem_init_tbl_ptr; +- uint16_t sdr_seq_tbl_ptr; +- uint16_t ddr_seq_tbl_ptr; +- +- struct { +- uint8_t crt, tv, panel; +- } i2c_indices; +- +- uint16_t lvds_single_a_script_ptr; +- } legacy; +-}; +- +-void *olddcb_table(struct drm_device *); +-void *olddcb_outp(struct drm_device *, u8 idx); +-int olddcb_outp_foreach(struct drm_device *, void *data, +- int (*)(struct drm_device *, void *, int idx, u8 *outp)); +-u8 *olddcb_conntab(struct drm_device *); +-u8 *olddcb_conn(struct drm_device *, u8 idx); +- +-int nouveau_bios_init(struct drm_device *); +-void nouveau_bios_takedown(struct drm_device *dev); +-int nouveau_run_vbios_init(struct drm_device *); +-struct dcb_connector_table_entry * +-nouveau_bios_connector_entry(struct drm_device *, int index); +-bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); +-uint8_t *nouveau_bios_embedded_edid(struct drm_device *); +-int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, +- bool *dl, bool *if_is_24bit); +-int run_tmds_table(struct drm_device *, struct dcb_output *, +- int head, int pxclk); +-int call_lvds_script(struct drm_device *, struct dcb_output *, int head, +- enum LVDS_script, int pxclk); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c +deleted file mode 100644 +index 3d474ac0..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_bo.c ++++ /dev/null +@@ -1,1529 +0,0 @@ +-/* +- * Copyright 2007 Dave Airlied +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- */ +-/* +- * Authors: Dave Airlied +- * Ben Skeggs +- * Jeremy Kolb +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fence.h" +- +-#include "nouveau_bo.h" +-#include "nouveau_ttm.h" +-#include "nouveau_gem.h" +- +-/* +- * NV10-NV40 tiling helpers +- */ +- +-static void +-nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, +- u32 addr, u32 size, u32 pitch, u32 flags) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- int i = reg - drm->tile.reg; +- struct nouveau_fb *pfb = nvkm_fb(&drm->device); +- struct nouveau_fb_tile *tile = &pfb->tile.region[i]; +- struct nouveau_engine *engine; +- +- nouveau_fence_unref(®->fence); +- +- if (tile->pitch) +- pfb->tile.fini(pfb, i, tile); +- +- if (pitch) +- pfb->tile.init(pfb, i, addr, size, pitch, flags, tile); +- +- pfb->tile.prog(pfb, i, tile); +- +- if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR))) +- engine->tile_prog(engine, i); +- if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG))) +- engine->tile_prog(engine, i); +-} +- +-static struct nouveau_drm_tile * +-nv10_bo_get_tile_region(struct drm_device *dev, int i) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_drm_tile *tile = &drm->tile.reg[i]; +- +- spin_lock(&drm->tile.lock); +- +- if (!tile->used && +- (!tile->fence || nouveau_fence_done(tile->fence))) +- tile->used = true; +- else +- tile = NULL; +- +- spin_unlock(&drm->tile.lock); +- return tile; +-} +- +-static void +-nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, +- struct fence *fence) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (tile) { +- spin_lock(&drm->tile.lock); +- tile->fence = (struct nouveau_fence *)fence_get(fence); +- tile->used = false; +- spin_unlock(&drm->tile.lock); +- } +-} +- +-static struct nouveau_drm_tile * +-nv10_bo_set_tiling(struct drm_device *dev, u32 addr, +- u32 size, u32 pitch, u32 flags) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_fb *pfb = nvkm_fb(&drm->device); +- struct nouveau_drm_tile *tile, *found = NULL; +- int i; +- +- for (i = 0; i < pfb->tile.regions; i++) { +- tile = nv10_bo_get_tile_region(dev, i); +- +- if (pitch && !found) { +- found = tile; +- continue; +- +- } else if (tile && pfb->tile.region[i].pitch) { +- /* Kill an unused tile region. */ +- nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); +- } +- +- nv10_bo_put_tile_region(dev, tile, NULL); +- } +- +- if (found) +- nv10_bo_update_tile_region(dev, found, addr, size, +- pitch, flags); +- return found; +-} +- +-static void +-nouveau_bo_del_ttm(struct ttm_buffer_object *bo) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct drm_device *dev = drm->dev; +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- +- if (unlikely(nvbo->gem.filp)) +- DRM_ERROR("bo %p still attached to GEM object\n", bo); +- WARN_ON(nvbo->pin_refcnt > 0); +- nv10_bo_put_tile_region(dev, nvbo->tile, NULL); +- kfree(nvbo); +-} +- +-static void +-nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, +- int *align, int *size) +-{ +- struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); +- struct nvif_device *device = &drm->device; +- +- if (device->info.family < NV_DEVICE_INFO_V0_TESLA) { +- if (nvbo->tile_mode) { +- if (device->info.chipset >= 0x40) { +- *align = 65536; +- *size = roundup(*size, 64 * nvbo->tile_mode); +- +- } else if (device->info.chipset >= 0x30) { +- *align = 32768; +- *size = roundup(*size, 64 * nvbo->tile_mode); +- +- } else if (device->info.chipset >= 0x20) { +- *align = 16384; +- *size = roundup(*size, 64 * nvbo->tile_mode); +- +- } else if (device->info.chipset >= 0x10) { +- *align = 16384; +- *size = roundup(*size, 32 * nvbo->tile_mode); +- } +- } +- } else { +- *size = roundup(*size, (1 << nvbo->page_shift)); +- *align = max((1 << nvbo->page_shift), *align); +- } +- +- *size = roundup(*size, PAGE_SIZE); +-} +- +-int +-nouveau_bo_new(struct drm_device *dev, int size, int align, +- uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, +- struct sg_table *sg, struct reservation_object *robj, +- struct nouveau_bo **pnvbo) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_bo *nvbo; +- size_t acc_size; +- int ret; +- int type = ttm_bo_type_device; +- int lpg_shift = 12; +- int max_size; +- +- if (drm->client.vm) +- lpg_shift = drm->client.vm->vmm->lpg_shift; +- max_size = INT_MAX & ~((1 << lpg_shift) - 1); +- +- if (size <= 0 || size > max_size) { +- NV_WARN(drm, "skipped size %x\n", (u32)size); +- return -EINVAL; +- } +- +- if (sg) +- type = ttm_bo_type_sg; +- +- nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); +- if (!nvbo) +- return -ENOMEM; +- INIT_LIST_HEAD(&nvbo->head); +- INIT_LIST_HEAD(&nvbo->entry); +- INIT_LIST_HEAD(&nvbo->vma_list); +- nvbo->tile_mode = tile_mode; +- nvbo->tile_flags = tile_flags; +- nvbo->bo.bdev = &drm->ttm.bdev; +- +- nvbo->page_shift = 12; +- if (drm->client.vm) { +- if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) +- nvbo->page_shift = drm->client.vm->vmm->lpg_shift; +- } +- +- nouveau_bo_fixup_align(nvbo, flags, &align, &size); +- nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; +- nouveau_bo_placement_set(nvbo, flags, 0); +- +- acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, +- sizeof(struct nouveau_bo)); +- +- ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, +- type, &nvbo->placement, +- align >> PAGE_SHIFT, false, NULL, acc_size, sg, +- robj, nouveau_bo_del_ttm); +- if (ret) { +- /* ttm will call nouveau_bo_del_ttm if it fails.. */ +- return ret; +- } +- +- *pnvbo = nvbo; +- return 0; +-} +- +-static void +-set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags) +-{ +- *n = 0; +- +- if (type & TTM_PL_FLAG_VRAM) +- pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags; +- if (type & TTM_PL_FLAG_TT) +- pl[(*n)++].flags = TTM_PL_FLAG_TT | flags; +- if (type & TTM_PL_FLAG_SYSTEM) +- pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags; +-} +- +-static void +-set_placement_range(struct nouveau_bo *nvbo, uint32_t type) +-{ +- struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); +- u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT; +- unsigned i, fpfn, lpfn; +- +- if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && +- nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) && +- nvbo->bo.mem.num_pages < vram_pages / 4) { +- /* +- * Make sure that the color and depth buffers are handled +- * by independent memory controller units. Up to a 9x +- * speed up when alpha-blending and depth-test are enabled +- * at the same time. +- */ +- if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { +- fpfn = vram_pages / 2; +- lpfn = ~0; +- } else { +- fpfn = 0; +- lpfn = vram_pages / 2; +- } +- for (i = 0; i < nvbo->placement.num_placement; ++i) { +- nvbo->placements[i].fpfn = fpfn; +- nvbo->placements[i].lpfn = lpfn; +- } +- for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { +- nvbo->busy_placements[i].fpfn = fpfn; +- nvbo->busy_placements[i].lpfn = lpfn; +- } +- } +-} +- +-void +-nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) +-{ +- struct ttm_placement *pl = &nvbo->placement; +- uint32_t flags = TTM_PL_MASK_CACHING | +- (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); +- +- pl->placement = nvbo->placements; +- set_placement_list(nvbo->placements, &pl->num_placement, +- type, flags); +- +- pl->busy_placement = nvbo->busy_placements; +- set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, +- type | busy, flags); +- +- set_placement_range(nvbo, type); +-} +- +-int +-nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) +-{ +- struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); +- struct ttm_buffer_object *bo = &nvbo->bo; +- int ret; +- +- ret = ttm_bo_reserve(bo, false, false, false, NULL); +- if (ret) +- goto out; +- +- if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { +- NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, +- 1 << bo->mem.mem_type, memtype); +- ret = -EINVAL; +- goto out; +- } +- +- if (nvbo->pin_refcnt++) +- goto out; +- +- nouveau_bo_placement_set(nvbo, memtype, 0); +- +- ret = nouveau_bo_validate(nvbo, false, false); +- if (ret == 0) { +- switch (bo->mem.mem_type) { +- case TTM_PL_VRAM: +- drm->gem.vram_available -= bo->mem.size; +- break; +- case TTM_PL_TT: +- drm->gem.gart_available -= bo->mem.size; +- break; +- default: +- break; +- } +- } +-out: +- ttm_bo_unreserve(bo); +- return ret; +-} +- +-int +-nouveau_bo_unpin(struct nouveau_bo *nvbo) +-{ +- struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); +- struct ttm_buffer_object *bo = &nvbo->bo; +- int ret, ref; +- +- ret = ttm_bo_reserve(bo, false, false, false, NULL); +- if (ret) +- return ret; +- +- ref = --nvbo->pin_refcnt; +- WARN_ON_ONCE(ref < 0); +- if (ref) +- goto out; +- +- nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); +- +- ret = nouveau_bo_validate(nvbo, false, false); +- if (ret == 0) { +- switch (bo->mem.mem_type) { +- case TTM_PL_VRAM: +- drm->gem.vram_available += bo->mem.size; +- break; +- case TTM_PL_TT: +- drm->gem.gart_available += bo->mem.size; +- break; +- default: +- break; +- } +- } +- +-out: +- ttm_bo_unreserve(bo); +- return ret; +-} +- +-int +-nouveau_bo_map(struct nouveau_bo *nvbo) +-{ +- int ret; +- +- ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL); +- if (ret) +- return ret; +- +- ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); +- ttm_bo_unreserve(&nvbo->bo); +- return ret; +-} +- +-void +-nouveau_bo_unmap(struct nouveau_bo *nvbo) +-{ +- if (nvbo) +- ttm_bo_kunmap(&nvbo->kmap); +-} +- +-int +-nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, +- bool no_wait_gpu) +-{ +- int ret; +- +- ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, +- interruptible, no_wait_gpu); +- if (ret) +- return ret; +- +- return 0; +-} +- +-u16 +-nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) +-{ +- bool is_iomem; +- u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); +- mem = &mem[index]; +- if (is_iomem) +- return ioread16_native((void __force __iomem *)mem); +- else +- return *mem; +-} +- +-void +-nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) +-{ +- bool is_iomem; +- u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); +- mem = &mem[index]; +- if (is_iomem) +- iowrite16_native(val, (void __force __iomem *)mem); +- else +- *mem = val; +-} +- +-u32 +-nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) +-{ +- bool is_iomem; +- u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); +- mem = &mem[index]; +- if (is_iomem) +- return ioread32_native((void __force __iomem *)mem); +- else +- return *mem; +-} +- +-void +-nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) +-{ +- bool is_iomem; +- u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); +- mem = &mem[index]; +- if (is_iomem) +- iowrite32_native(val, (void __force __iomem *)mem); +- else +- *mem = val; +-} +- +-static struct ttm_tt * +-nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, +- uint32_t page_flags, struct page *dummy_read) +-{ +-#if __OS_HAS_AGP +- struct nouveau_drm *drm = nouveau_bdev(bdev); +- struct drm_device *dev = drm->dev; +- +- if (drm->agp.stat == ENABLED) { +- return ttm_agp_tt_create(bdev, dev->agp->bridge, size, +- page_flags, dummy_read); +- } +-#endif +- +- return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); +-} +- +-static int +-nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) +-{ +- /* We'll do this from user space. */ +- return 0; +-} +- +-static int +-nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, +- struct ttm_mem_type_manager *man) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bdev); +- +- switch (type) { +- case TTM_PL_SYSTEM: +- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; +- man->available_caching = TTM_PL_MASK_CACHING; +- man->default_caching = TTM_PL_FLAG_CACHED; +- break; +- case TTM_PL_VRAM: +- man->flags = TTM_MEMTYPE_FLAG_FIXED | +- TTM_MEMTYPE_FLAG_MAPPABLE; +- man->available_caching = TTM_PL_FLAG_UNCACHED | +- TTM_PL_FLAG_WC; +- man->default_caching = TTM_PL_FLAG_WC; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- /* Some BARs do not support being ioremapped WC */ +- if (nvkm_bar(&drm->device)->iomap_uncached) { +- man->available_caching = TTM_PL_FLAG_UNCACHED; +- man->default_caching = TTM_PL_FLAG_UNCACHED; +- } +- +- man->func = &nouveau_vram_manager; +- man->io_reserve_fastpath = false; +- man->use_io_reserve_lru = true; +- } else { +- man->func = &ttm_bo_manager_func; +- } +- break; +- case TTM_PL_TT: +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) +- man->func = &nouveau_gart_manager; +- else +- if (drm->agp.stat != ENABLED) +- man->func = &nv04_gart_manager; +- else +- man->func = &ttm_bo_manager_func; +- +- if (drm->agp.stat == ENABLED) { +- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; +- man->available_caching = TTM_PL_FLAG_UNCACHED | +- TTM_PL_FLAG_WC; +- man->default_caching = TTM_PL_FLAG_WC; +- } else { +- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | +- TTM_MEMTYPE_FLAG_CMA; +- man->available_caching = TTM_PL_MASK_CACHING; +- man->default_caching = TTM_PL_FLAG_CACHED; +- } +- +- break; +- default: +- return -EINVAL; +- } +- return 0; +-} +- +-static void +-nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) +-{ +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- +- switch (bo->mem.mem_type) { +- case TTM_PL_VRAM: +- nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, +- TTM_PL_FLAG_SYSTEM); +- break; +- default: +- nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); +- break; +- } +- +- *pl = nvbo->placement; +-} +- +- +-static int +-nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) +-{ +- int ret = RING_SPACE(chan, 2); +- if (ret == 0) { +- BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); +- OUT_RING (chan, handle & 0x0000ffff); +- FIRE_RING (chan); +- } +- return ret; +-} +- +-static int +-nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- int ret = RING_SPACE(chan, 10); +- if (ret == 0) { +- BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); +- OUT_RING (chan, upper_32_bits(node->vma[0].offset)); +- OUT_RING (chan, lower_32_bits(node->vma[0].offset)); +- OUT_RING (chan, upper_32_bits(node->vma[1].offset)); +- OUT_RING (chan, lower_32_bits(node->vma[1].offset)); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, new_mem->num_pages); +- BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); +- } +- return ret; +-} +- +-static int +-nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) +-{ +- int ret = RING_SPACE(chan, 2); +- if (ret == 0) { +- BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); +- OUT_RING (chan, handle); +- } +- return ret; +-} +- +-static int +-nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- u64 src_offset = node->vma[0].offset; +- u64 dst_offset = node->vma[1].offset; +- u32 page_count = new_mem->num_pages; +- int ret; +- +- page_count = new_mem->num_pages; +- while (page_count) { +- int line_count = (page_count > 8191) ? 8191 : page_count; +- +- ret = RING_SPACE(chan, 11); +- if (ret) +- return ret; +- +- BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); +- OUT_RING (chan, upper_32_bits(src_offset)); +- OUT_RING (chan, lower_32_bits(src_offset)); +- OUT_RING (chan, upper_32_bits(dst_offset)); +- OUT_RING (chan, lower_32_bits(dst_offset)); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, line_count); +- BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); +- OUT_RING (chan, 0x00000110); +- +- page_count -= line_count; +- src_offset += (PAGE_SIZE * line_count); +- dst_offset += (PAGE_SIZE * line_count); +- } +- +- return 0; +-} +- +-static int +-nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- u64 src_offset = node->vma[0].offset; +- u64 dst_offset = node->vma[1].offset; +- u32 page_count = new_mem->num_pages; +- int ret; +- +- page_count = new_mem->num_pages; +- while (page_count) { +- int line_count = (page_count > 2047) ? 2047 : page_count; +- +- ret = RING_SPACE(chan, 12); +- if (ret) +- return ret; +- +- BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); +- OUT_RING (chan, upper_32_bits(dst_offset)); +- OUT_RING (chan, lower_32_bits(dst_offset)); +- BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); +- OUT_RING (chan, upper_32_bits(src_offset)); +- OUT_RING (chan, lower_32_bits(src_offset)); +- OUT_RING (chan, PAGE_SIZE); /* src_pitch */ +- OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ +- OUT_RING (chan, PAGE_SIZE); /* line_length */ +- OUT_RING (chan, line_count); +- BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); +- OUT_RING (chan, 0x00100110); +- +- page_count -= line_count; +- src_offset += (PAGE_SIZE * line_count); +- dst_offset += (PAGE_SIZE * line_count); +- } +- +- return 0; +-} +- +-static int +-nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- u64 src_offset = node->vma[0].offset; +- u64 dst_offset = node->vma[1].offset; +- u32 page_count = new_mem->num_pages; +- int ret; +- +- page_count = new_mem->num_pages; +- while (page_count) { +- int line_count = (page_count > 8191) ? 8191 : page_count; +- +- ret = RING_SPACE(chan, 11); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); +- OUT_RING (chan, upper_32_bits(src_offset)); +- OUT_RING (chan, lower_32_bits(src_offset)); +- OUT_RING (chan, upper_32_bits(dst_offset)); +- OUT_RING (chan, lower_32_bits(dst_offset)); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, PAGE_SIZE); +- OUT_RING (chan, line_count); +- BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); +- OUT_RING (chan, 0x00000110); +- +- page_count -= line_count; +- src_offset += (PAGE_SIZE * line_count); +- dst_offset += (PAGE_SIZE * line_count); +- } +- +- return 0; +-} +- +-static int +-nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- int ret = RING_SPACE(chan, 7); +- if (ret == 0) { +- BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); +- OUT_RING (chan, upper_32_bits(node->vma[0].offset)); +- OUT_RING (chan, lower_32_bits(node->vma[0].offset)); +- OUT_RING (chan, upper_32_bits(node->vma[1].offset)); +- OUT_RING (chan, lower_32_bits(node->vma[1].offset)); +- OUT_RING (chan, 0x00000000 /* COPY */); +- OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); +- } +- return ret; +-} +- +-static int +-nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- int ret = RING_SPACE(chan, 7); +- if (ret == 0) { +- BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); +- OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); +- OUT_RING (chan, upper_32_bits(node->vma[0].offset)); +- OUT_RING (chan, lower_32_bits(node->vma[0].offset)); +- OUT_RING (chan, upper_32_bits(node->vma[1].offset)); +- OUT_RING (chan, lower_32_bits(node->vma[1].offset)); +- OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); +- } +- return ret; +-} +- +-static int +-nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) +-{ +- int ret = RING_SPACE(chan, 6); +- if (ret == 0) { +- BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); +- OUT_RING (chan, handle); +- BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); +- OUT_RING (chan, chan->drm->ntfy.handle); +- OUT_RING (chan, chan->vram.handle); +- OUT_RING (chan, chan->vram.handle); +- } +- +- return ret; +-} +- +-static int +-nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_mem *node = old_mem->mm_node; +- u64 length = (new_mem->num_pages << PAGE_SHIFT); +- u64 src_offset = node->vma[0].offset; +- u64 dst_offset = node->vma[1].offset; +- int src_tiled = !!node->memtype; +- int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype; +- int ret; +- +- while (length) { +- u32 amount, stride, height; +- +- ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled)); +- if (ret) +- return ret; +- +- amount = min(length, (u64)(4 * 1024 * 1024)); +- stride = 16 * 4; +- height = amount / stride; +- +- if (src_tiled) { +- BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); +- OUT_RING (chan, 0); +- OUT_RING (chan, 0); +- OUT_RING (chan, stride); +- OUT_RING (chan, height); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, 0); +- } else { +- BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); +- OUT_RING (chan, 1); +- } +- if (dst_tiled) { +- BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); +- OUT_RING (chan, 0); +- OUT_RING (chan, 0); +- OUT_RING (chan, stride); +- OUT_RING (chan, height); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, 0); +- } else { +- BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); +- OUT_RING (chan, 1); +- } +- +- BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); +- OUT_RING (chan, upper_32_bits(src_offset)); +- OUT_RING (chan, upper_32_bits(dst_offset)); +- BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); +- OUT_RING (chan, lower_32_bits(src_offset)); +- OUT_RING (chan, lower_32_bits(dst_offset)); +- OUT_RING (chan, stride); +- OUT_RING (chan, stride); +- OUT_RING (chan, stride); +- OUT_RING (chan, height); +- OUT_RING (chan, 0x00000101); +- OUT_RING (chan, 0x00000000); +- BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); +- OUT_RING (chan, 0); +- +- length -= amount; +- src_offset += amount; +- dst_offset += amount; +- } +- +- return 0; +-} +- +-static int +-nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) +-{ +- int ret = RING_SPACE(chan, 4); +- if (ret == 0) { +- BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); +- OUT_RING (chan, handle); +- BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); +- OUT_RING (chan, chan->drm->ntfy.handle); +- } +- +- return ret; +-} +- +-static inline uint32_t +-nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, +- struct nouveau_channel *chan, struct ttm_mem_reg *mem) +-{ +- if (mem->mem_type == TTM_PL_TT) +- return NvDmaTT; +- return chan->vram.handle; +-} +- +-static int +-nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) +-{ +- u32 src_offset = old_mem->start << PAGE_SHIFT; +- u32 dst_offset = new_mem->start << PAGE_SHIFT; +- u32 page_count = new_mem->num_pages; +- int ret; +- +- ret = RING_SPACE(chan, 3); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); +- OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); +- OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); +- +- page_count = new_mem->num_pages; +- while (page_count) { +- int line_count = (page_count > 2047) ? 2047 : page_count; +- +- ret = RING_SPACE(chan, 11); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubCopy, +- NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); +- OUT_RING (chan, src_offset); +- OUT_RING (chan, dst_offset); +- OUT_RING (chan, PAGE_SIZE); /* src_pitch */ +- OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ +- OUT_RING (chan, PAGE_SIZE); /* line_length */ +- OUT_RING (chan, line_count); +- OUT_RING (chan, 0x00000101); +- OUT_RING (chan, 0x00000000); +- BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); +- OUT_RING (chan, 0); +- +- page_count -= line_count; +- src_offset += (PAGE_SIZE * line_count); +- dst_offset += (PAGE_SIZE * line_count); +- } +- +- return 0; +-} +- +-static int +-nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo, +- struct ttm_mem_reg *mem) +-{ +- struct nouveau_mem *old_node = bo->mem.mm_node; +- struct nouveau_mem *new_node = mem->mm_node; +- u64 size = (u64)mem->num_pages << PAGE_SHIFT; +- int ret; +- +- ret = nouveau_vm_get(drm->client.vm, size, old_node->page_shift, +- NV_MEM_ACCESS_RW, &old_node->vma[0]); +- if (ret) +- return ret; +- +- ret = nouveau_vm_get(drm->client.vm, size, new_node->page_shift, +- NV_MEM_ACCESS_RW, &old_node->vma[1]); +- if (ret) { +- nouveau_vm_put(&old_node->vma[0]); +- return ret; +- } +- +- nouveau_vm_map(&old_node->vma[0], old_node); +- nouveau_vm_map(&old_node->vma[1], new_node); +- return 0; +-} +- +-static int +-nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, +- bool no_wait_gpu, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct nouveau_channel *chan = drm->ttm.chan; +- struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); +- struct nouveau_fence *fence; +- int ret; +- +- /* create temporary vmas for the transfer and attach them to the +- * old nouveau_mem node, these will get cleaned up after ttm has +- * destroyed the ttm_mem_reg +- */ +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_bo_move_prep(drm, bo, new_mem); +- if (ret) +- return ret; +- } +- +- mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING); +- ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr); +- if (ret == 0) { +- ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); +- if (ret == 0) { +- ret = nouveau_fence_new(chan, false, &fence); +- if (ret == 0) { +- ret = ttm_bo_move_accel_cleanup(bo, +- &fence->base, +- evict, +- no_wait_gpu, +- new_mem); +- nouveau_fence_unref(&fence); +- } +- } +- } +- mutex_unlock(&cli->mutex); +- return ret; +-} +- +-void +-nouveau_bo_move_init(struct nouveau_drm *drm) +-{ +- static const struct { +- const char *name; +- int engine; +- u32 oclass; +- int (*exec)(struct nouveau_channel *, +- struct ttm_buffer_object *, +- struct ttm_mem_reg *, struct ttm_mem_reg *); +- int (*init)(struct nouveau_channel *, u32 handle); +- } _methods[] = { +- { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, +- { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, +- { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, +- { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, +- { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, +- { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, +- { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, +- { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, +- { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, +- {}, +- { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, +- }, *mthd = _methods; +- const char *name = "CPU"; +- int ret; +- +- do { +- struct nouveau_channel *chan; +- +- if (mthd->engine) +- chan = drm->cechan; +- else +- chan = drm->channel; +- if (chan == NULL) +- continue; +- +- ret = nvif_object_init(chan->object, NULL, +- mthd->oclass | (mthd->engine << 16), +- mthd->oclass, NULL, 0, +- &drm->ttm.copy); +- if (ret == 0) { +- ret = mthd->init(chan, drm->ttm.copy.handle); +- if (ret) { +- nvif_object_fini(&drm->ttm.copy); +- continue; +- } +- +- drm->ttm.move = mthd->exec; +- drm->ttm.chan = chan; +- name = mthd->name; +- break; +- } +- } while ((++mthd)->exec); +- +- NV_INFO(drm, "MM: using %s for buffer copies\n", name); +-} +- +-static int +-nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, +- bool no_wait_gpu, struct ttm_mem_reg *new_mem) +-{ +- struct ttm_place placement_memtype = { +- .fpfn = 0, +- .lpfn = 0, +- .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING +- }; +- struct ttm_placement placement; +- struct ttm_mem_reg tmp_mem; +- int ret; +- +- placement.num_placement = placement.num_busy_placement = 1; +- placement.placement = placement.busy_placement = &placement_memtype; +- +- tmp_mem = *new_mem; +- tmp_mem.mm_node = NULL; +- ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); +- if (ret) +- return ret; +- +- ret = ttm_tt_bind(bo->ttm, &tmp_mem); +- if (ret) +- goto out; +- +- ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem); +- if (ret) +- goto out; +- +- ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); +-out: +- ttm_bo_mem_put(bo, &tmp_mem); +- return ret; +-} +- +-static int +-nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, +- bool no_wait_gpu, struct ttm_mem_reg *new_mem) +-{ +- struct ttm_place placement_memtype = { +- .fpfn = 0, +- .lpfn = 0, +- .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING +- }; +- struct ttm_placement placement; +- struct ttm_mem_reg tmp_mem; +- int ret; +- +- placement.num_placement = placement.num_busy_placement = 1; +- placement.placement = placement.busy_placement = &placement_memtype; +- +- tmp_mem = *new_mem; +- tmp_mem.mm_node = NULL; +- ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); +- if (ret) +- return ret; +- +- ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); +- if (ret) +- goto out; +- +- ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem); +- if (ret) +- goto out; +- +-out: +- ttm_bo_mem_put(bo, &tmp_mem); +- return ret; +-} +- +-static void +-nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- struct nouveau_vma *vma; +- +- /* ttm can now (stupidly) pass the driver bos it didn't create... */ +- if (bo->destroy != nouveau_bo_del_ttm) +- return; +- +- list_for_each_entry(vma, &nvbo->vma_list, head) { +- if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM && +- (new_mem->mem_type == TTM_PL_VRAM || +- nvbo->page_shift != vma->vm->vmm->lpg_shift)) { +- nouveau_vm_map(vma, new_mem->mm_node); +- } else { +- nouveau_vm_unmap(vma); +- } +- } +-} +- +-static int +-nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, +- struct nouveau_drm_tile **new_tile) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct drm_device *dev = drm->dev; +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- u64 offset = new_mem->start << PAGE_SHIFT; +- +- *new_tile = NULL; +- if (new_mem->mem_type != TTM_PL_VRAM) +- return 0; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { +- *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size, +- nvbo->tile_mode, +- nvbo->tile_flags); +- } +- +- return 0; +-} +- +-static void +-nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, +- struct nouveau_drm_tile *new_tile, +- struct nouveau_drm_tile **old_tile) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct drm_device *dev = drm->dev; +- struct fence *fence = reservation_object_get_excl(bo->resv); +- +- nv10_bo_put_tile_region(dev, *old_tile, fence); +- *old_tile = new_tile; +-} +- +-static int +-nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, +- bool no_wait_gpu, struct ttm_mem_reg *new_mem) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- struct ttm_mem_reg *old_mem = &bo->mem; +- struct nouveau_drm_tile *new_tile = NULL; +- int ret = 0; +- +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); +- if (ret) +- return ret; +- } +- +- /* Fake bo copy. */ +- if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { +- BUG_ON(bo->mem.mm_node != NULL); +- bo->mem = *new_mem; +- new_mem->mm_node = NULL; +- goto out; +- } +- +- /* Hardware assisted copy. */ +- if (drm->ttm.move) { +- if (new_mem->mem_type == TTM_PL_SYSTEM) +- ret = nouveau_bo_move_flipd(bo, evict, intr, +- no_wait_gpu, new_mem); +- else if (old_mem->mem_type == TTM_PL_SYSTEM) +- ret = nouveau_bo_move_flips(bo, evict, intr, +- no_wait_gpu, new_mem); +- else +- ret = nouveau_bo_move_m2mf(bo, evict, intr, +- no_wait_gpu, new_mem); +- if (!ret) +- goto out; +- } +- +- /* Fallback to software copy. */ +- ret = ttm_bo_wait(bo, true, intr, no_wait_gpu); +- if (ret == 0) +- ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); +- +-out: +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { +- if (ret) +- nouveau_bo_vm_cleanup(bo, NULL, &new_tile); +- else +- nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); +- } +- +- return ret; +-} +- +-static int +-nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) +-{ +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- +- return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp); +-} +- +-static int +-nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +-{ +- struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; +- struct nouveau_drm *drm = nouveau_bdev(bdev); +- struct nouveau_mem *node = mem->mm_node; +- int ret; +- +- mem->bus.addr = NULL; +- mem->bus.offset = 0; +- mem->bus.size = mem->num_pages << PAGE_SHIFT; +- mem->bus.base = 0; +- mem->bus.is_iomem = false; +- if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) +- return -EINVAL; +- switch (mem->mem_type) { +- case TTM_PL_SYSTEM: +- /* System memory */ +- return 0; +- case TTM_PL_TT: +-#if __OS_HAS_AGP +- if (drm->agp.stat == ENABLED) { +- mem->bus.offset = mem->start << PAGE_SHIFT; +- mem->bus.base = drm->agp.base; +- mem->bus.is_iomem = !drm->dev->agp->cant_use_aperture; +- } +-#endif +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype) +- /* untiled */ +- break; +- /* fallthrough, tiled memory */ +- case TTM_PL_VRAM: +- mem->bus.offset = mem->start << PAGE_SHIFT; +- mem->bus.base = nv_device_resource_start(nvkm_device(&drm->device), 1); +- mem->bus.is_iomem = true; +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- struct nouveau_bar *bar = nvkm_bar(&drm->device); +- +- ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, +- &node->bar_vma); +- if (ret) +- return ret; +- +- mem->bus.offset = node->bar_vma.offset; +- } +- break; +- default: +- return -EINVAL; +- } +- return 0; +-} +- +-static void +-nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bdev); +- struct nouveau_bar *bar = nvkm_bar(&drm->device); +- struct nouveau_mem *node = mem->mm_node; +- +- if (!node->bar_vma.node) +- return; +- +- bar->unmap(bar, &node->bar_vma); +-} +- +-static int +-nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- struct nvif_device *device = &drm->device; +- u32 mappable = nv_device_resource_len(nvkm_device(device), 1) >> PAGE_SHIFT; +- int i, ret; +- +- /* as long as the bo isn't in vram, and isn't tiled, we've got +- * nothing to do here. +- */ +- if (bo->mem.mem_type != TTM_PL_VRAM) { +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || +- !nouveau_bo_tile_layout(nvbo)) +- return 0; +- +- if (bo->mem.mem_type == TTM_PL_SYSTEM) { +- nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0); +- +- ret = nouveau_bo_validate(nvbo, false, false); +- if (ret) +- return ret; +- } +- return 0; +- } +- +- /* make sure bo is in mappable vram */ +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA || +- bo->mem.start + bo->mem.num_pages < mappable) +- return 0; +- +- for (i = 0; i < nvbo->placement.num_placement; ++i) { +- nvbo->placements[i].fpfn = 0; +- nvbo->placements[i].lpfn = mappable; +- } +- +- for (i = 0; i < nvbo->placement.num_busy_placement; ++i) { +- nvbo->busy_placements[i].fpfn = 0; +- nvbo->busy_placements[i].lpfn = mappable; +- } +- +- nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); +- return nouveau_bo_validate(nvbo, false, false); +-} +- +-static int +-nouveau_ttm_tt_populate(struct ttm_tt *ttm) +-{ +- struct ttm_dma_tt *ttm_dma = (void *)ttm; +- struct nouveau_drm *drm; +- struct nouveau_device *device; +- struct drm_device *dev; +- struct device *pdev; +- unsigned i; +- int r; +- bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); +- +- if (ttm->state != tt_unpopulated) +- return 0; +- +- if (slave && ttm->sg) { +- /* make userspace faulting work */ +- drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, +- ttm_dma->dma_address, ttm->num_pages); +- ttm->state = tt_unbound; +- return 0; +- } +- +- drm = nouveau_bdev(ttm->bdev); +- device = nvkm_device(&drm->device); +- dev = drm->dev; +- pdev = nv_device_base(device); +- +-#if __OS_HAS_AGP +- if (drm->agp.stat == ENABLED) { +- return ttm_agp_tt_populate(ttm); +- } +-#endif +- +-#ifdef CONFIG_SWIOTLB +- if (swiotlb_nr_tbl()) { +- return ttm_dma_populate((void *)ttm, dev->dev); +- } +-#endif +- +- r = ttm_pool_populate(ttm); +- if (r) { +- return r; +- } +- +- for (i = 0; i < ttm->num_pages; i++) { +- dma_addr_t addr; +- +- addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE, +- DMA_BIDIRECTIONAL); +- +- if (dma_mapping_error(pdev, addr)) { +- while (--i) { +- dma_unmap_page(pdev, ttm_dma->dma_address[i], +- PAGE_SIZE, DMA_BIDIRECTIONAL); +- ttm_dma->dma_address[i] = 0; +- } +- ttm_pool_unpopulate(ttm); +- return -EFAULT; +- } +- +- ttm_dma->dma_address[i] = addr; +- } +- return 0; +-} +- +-static void +-nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) +-{ +- struct ttm_dma_tt *ttm_dma = (void *)ttm; +- struct nouveau_drm *drm; +- struct nouveau_device *device; +- struct drm_device *dev; +- struct device *pdev; +- unsigned i; +- bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); +- +- if (slave) +- return; +- +- drm = nouveau_bdev(ttm->bdev); +- device = nvkm_device(&drm->device); +- dev = drm->dev; +- pdev = nv_device_base(device); +- +-#if __OS_HAS_AGP +- if (drm->agp.stat == ENABLED) { +- ttm_agp_tt_unpopulate(ttm); +- return; +- } +-#endif +- +-#ifdef CONFIG_SWIOTLB +- if (swiotlb_nr_tbl()) { +- ttm_dma_unpopulate((void *)ttm, dev->dev); +- return; +- } +-#endif +- +- for (i = 0; i < ttm->num_pages; i++) { +- if (ttm_dma->dma_address[i]) { +- dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE, +- DMA_BIDIRECTIONAL); +- } +- } +- +- ttm_pool_unpopulate(ttm); +-} +- +-void +-nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive) +-{ +- struct reservation_object *resv = nvbo->bo.resv; +- +- if (exclusive) +- reservation_object_add_excl_fence(resv, &fence->base); +- else if (fence) +- reservation_object_add_shared_fence(resv, &fence->base); +-} +- +-struct ttm_bo_driver nouveau_bo_driver = { +- .ttm_tt_create = &nouveau_ttm_tt_create, +- .ttm_tt_populate = &nouveau_ttm_tt_populate, +- .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, +- .invalidate_caches = nouveau_bo_invalidate_caches, +- .init_mem_type = nouveau_bo_init_mem_type, +- .evict_flags = nouveau_bo_evict_flags, +- .move_notify = nouveau_bo_move_ntfy, +- .move = nouveau_bo_move, +- .verify_access = nouveau_bo_verify_access, +- .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, +- .io_mem_reserve = &nouveau_ttm_io_mem_reserve, +- .io_mem_free = &nouveau_ttm_io_mem_free, +-}; +- +-struct nouveau_vma * +-nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm) +-{ +- struct nouveau_vma *vma; +- list_for_each_entry(vma, &nvbo->vma_list, head) { +- if (vma->vm == vm) +- return vma; +- } +- +- return NULL; +-} +- +-int +-nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, +- struct nouveau_vma *vma) +-{ +- const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; +- int ret; +- +- ret = nouveau_vm_get(vm, size, nvbo->page_shift, +- NV_MEM_ACCESS_RW, vma); +- if (ret) +- return ret; +- +- if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM && +- (nvbo->bo.mem.mem_type == TTM_PL_VRAM || +- nvbo->page_shift != vma->vm->vmm->lpg_shift)) +- nouveau_vm_map(vma, nvbo->bo.mem.mm_node); +- +- list_add_tail(&vma->head, &nvbo->vma_list); +- vma->refcount = 1; +- return 0; +-} +- +-void +-nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma) +-{ +- if (vma->node) { +- if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) +- nouveau_vm_unmap(vma); +- nouveau_vm_put(vma); +- list_del(&vma->head); +- } +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.h b/drivers/gpu/drm/nouveau/nouveau_bo.h +deleted file mode 100644 +index 22d2c764..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_bo.h ++++ /dev/null +@@ -1,106 +0,0 @@ +-#ifndef __NOUVEAU_BO_H__ +-#define __NOUVEAU_BO_H__ +- +-#include +- +-struct nouveau_channel; +-struct nouveau_fence; +-struct nouveau_vma; +- +-struct nouveau_bo { +- struct ttm_buffer_object bo; +- struct ttm_placement placement; +- u32 valid_domains; +- struct ttm_place placements[3]; +- struct ttm_place busy_placements[3]; +- struct ttm_bo_kmap_obj kmap; +- struct list_head head; +- +- /* protected by ttm_bo_reserve() */ +- struct drm_file *reserved_by; +- struct list_head entry; +- int pbbo_index; +- bool validate_mapped; +- +- struct list_head vma_list; +- unsigned page_shift; +- +- u32 tile_mode; +- u32 tile_flags; +- struct nouveau_drm_tile *tile; +- +- /* Only valid if allocated via nouveau_gem_new() and iff you hold a +- * gem reference to it! For debugging, use gem.filp != NULL to test +- * whether it is valid. */ +- struct drm_gem_object gem; +- +- /* protect by the ttm reservation lock */ +- int pin_refcnt; +- +- struct ttm_bo_kmap_obj dma_buf_vmap; +-}; +- +-static inline struct nouveau_bo * +-nouveau_bo(struct ttm_buffer_object *bo) +-{ +- return container_of(bo, struct nouveau_bo, bo); +-} +- +-static inline int +-nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) +-{ +- struct nouveau_bo *prev; +- +- if (!pnvbo) +- return -EINVAL; +- prev = *pnvbo; +- +- *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; +- if (prev) { +- struct ttm_buffer_object *bo = &prev->bo; +- +- ttm_bo_unref(&bo); +- } +- +- return 0; +-} +- +-extern struct ttm_bo_driver nouveau_bo_driver; +- +-void nouveau_bo_move_init(struct nouveau_drm *); +-int nouveau_bo_new(struct drm_device *, int size, int align, u32 flags, +- u32 tile_mode, u32 tile_flags, struct sg_table *sg, +- struct reservation_object *robj, +- struct nouveau_bo **); +-int nouveau_bo_pin(struct nouveau_bo *, u32 flags); +-int nouveau_bo_unpin(struct nouveau_bo *); +-int nouveau_bo_map(struct nouveau_bo *); +-void nouveau_bo_unmap(struct nouveau_bo *); +-void nouveau_bo_placement_set(struct nouveau_bo *, u32 type, u32 busy); +-u16 nouveau_bo_rd16(struct nouveau_bo *, unsigned index); +-void nouveau_bo_wr16(struct nouveau_bo *, unsigned index, u16 val); +-u32 nouveau_bo_rd32(struct nouveau_bo *, unsigned index); +-void nouveau_bo_wr32(struct nouveau_bo *, unsigned index, u32 val); +-void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *, bool exclusive); +-int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, +- bool no_wait_gpu); +- +-struct nouveau_vma * +-nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); +- +-int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, +- struct nouveau_vma *); +-void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); +- +-/* TODO: submit equivalent to TTM generic API upstream? */ +-static inline void __iomem * +-nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) +-{ +- bool is_iomem; +- void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( +- &nvbo->kmap, &is_iomem); +- WARN_ON_ONCE(ioptr && !is_iomem); +- return ioptr; +-} +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c +deleted file mode 100644 +index fd3dbd59..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_chan.c ++++ /dev/null +@@ -1,429 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-/*XXX*/ +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_bo.h" +-#include "nouveau_chan.h" +-#include "nouveau_fence.h" +-#include "nouveau_abi16.h" +- +-MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM"); +-int nouveau_vram_pushbuf; +-module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); +- +-int +-nouveau_channel_idle(struct nouveau_channel *chan) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(chan->object); +- struct nouveau_fence *fence = NULL; +- int ret; +- +- ret = nouveau_fence_new(chan, false, &fence); +- if (!ret) { +- ret = nouveau_fence_wait(fence, false, false); +- nouveau_fence_unref(&fence); +- } +- +- if (ret) +- NV_PRINTK(error, cli, "failed to idle channel 0x%08x [%s]\n", +- chan->object->handle, nvkm_client(&cli->base)->name); +- return ret; +-} +- +-void +-nouveau_channel_del(struct nouveau_channel **pchan) +-{ +- struct nouveau_channel *chan = *pchan; +- if (chan) { +- if (chan->fence) { +- nouveau_channel_idle(chan); +- nouveau_fence(chan->drm)->context_del(chan); +- } +- nvif_object_fini(&chan->nvsw); +- nvif_object_fini(&chan->gart); +- nvif_object_fini(&chan->vram); +- nvif_object_ref(NULL, &chan->object); +- nvif_object_fini(&chan->push.ctxdma); +- nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma); +- nouveau_bo_unmap(chan->push.buffer); +- if (chan->push.buffer && chan->push.buffer->pin_refcnt) +- nouveau_bo_unpin(chan->push.buffer); +- nouveau_bo_ref(NULL, &chan->push.buffer); +- nvif_device_ref(NULL, &chan->device); +- kfree(chan); +- } +- *pchan = NULL; +-} +- +-static int +-nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, +- u32 handle, u32 size, struct nouveau_channel **pchan) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&device->base); +- struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); +- struct nv_dma_v0 args = {}; +- struct nouveau_channel *chan; +- u32 target; +- int ret; +- +- chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL); +- if (!chan) +- return -ENOMEM; +- +- nvif_device_ref(device, &chan->device); +- chan->drm = drm; +- +- /* allocate memory for dma push buffer */ +- target = TTM_PL_FLAG_TT; +- if (nouveau_vram_pushbuf) +- target = TTM_PL_FLAG_VRAM; +- +- ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL, +- &chan->push.buffer); +- if (ret == 0) { +- ret = nouveau_bo_pin(chan->push.buffer, target); +- if (ret == 0) +- ret = nouveau_bo_map(chan->push.buffer); +- } +- +- if (ret) { +- nouveau_channel_del(pchan); +- return ret; +- } +- +- /* create dma object covering the *entire* memory space that the +- * pushbuf lives in, this is because the GEM code requires that +- * we be able to call out to other (indirect) push buffers +- */ +- chan->push.vma.offset = chan->push.buffer->bo.offset; +- +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm, +- &chan->push.vma); +- if (ret) { +- nouveau_channel_del(pchan); +- return ret; +- } +- +- args.target = NV_DMA_V0_TARGET_VM; +- args.access = NV_DMA_V0_ACCESS_VM; +- args.start = 0; +- args.limit = cli->vm->vmm->limit - 1; +- } else +- if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) { +- if (device->info.family == NV_DEVICE_INFO_V0_TNT) { +- /* nv04 vram pushbuf hack, retarget to its location in +- * the framebuffer bar rather than direct vram access.. +- * nfi why this exists, it came from the -nv ddx. +- */ +- args.target = NV_DMA_V0_TARGET_PCI; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = nv_device_resource_start(nvkm_device(device), 1); +- args.limit = args.start + device->info.ram_user - 1; +- } else { +- args.target = NV_DMA_V0_TARGET_VRAM; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = 0; +- args.limit = device->info.ram_user - 1; +- } +- } else { +- if (chan->drm->agp.stat == ENABLED) { +- args.target = NV_DMA_V0_TARGET_AGP; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = chan->drm->agp.base; +- args.limit = chan->drm->agp.base + +- chan->drm->agp.size - 1; +- } else { +- args.target = NV_DMA_V0_TARGET_VM; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = 0; +- args.limit = vmm->limit - 1; +- } +- } +- +- ret = nvif_object_init(nvif_object(device), NULL, NVDRM_PUSH | +- (handle & 0xffff), NV_DMA_FROM_MEMORY, +- &args, sizeof(args), &chan->push.ctxdma); +- if (ret) { +- nouveau_channel_del(pchan); +- return ret; +- } +- +- return 0; +-} +- +-static int +-nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, +- u32 handle, u32 engine, struct nouveau_channel **pchan) +-{ +- static const u16 oclasses[] = { KEPLER_CHANNEL_GPFIFO_A, +- FERMI_CHANNEL_GPFIFO, +- G82_CHANNEL_GPFIFO, +- NV50_CHANNEL_GPFIFO, +- 0 }; +- const u16 *oclass = oclasses; +- union { +- struct nv50_channel_gpfifo_v0 nv50; +- struct kepler_channel_gpfifo_a_v0 kepler; +- } args, *retn; +- struct nouveau_channel *chan; +- u32 size; +- int ret; +- +- /* allocate dma push buffer */ +- ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan); +- *pchan = chan; +- if (ret) +- return ret; +- +- /* create channel object */ +- do { +- if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) { +- args.kepler.version = 0; +- args.kepler.engine = engine; +- args.kepler.pushbuf = chan->push.ctxdma.handle; +- args.kepler.ilength = 0x02000; +- args.kepler.ioffset = 0x10000 + chan->push.vma.offset; +- size = sizeof(args.kepler); +- } else { +- args.nv50.version = 0; +- args.nv50.pushbuf = chan->push.ctxdma.handle; +- args.nv50.ilength = 0x02000; +- args.nv50.ioffset = 0x10000 + chan->push.vma.offset; +- size = sizeof(args.nv50); +- } +- +- ret = nvif_object_new(nvif_object(device), handle, *oclass++, +- &args, size, &chan->object); +- if (ret == 0) { +- retn = chan->object->data; +- if (chan->object->oclass >= KEPLER_CHANNEL_GPFIFO_A) +- chan->chid = retn->kepler.chid; +- else +- chan->chid = retn->nv50.chid; +- return ret; +- } +- } while (*oclass); +- +- nouveau_channel_del(pchan); +- return ret; +-} +- +-static int +-nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, +- u32 handle, struct nouveau_channel **pchan) +-{ +- static const u16 oclasses[] = { NV40_CHANNEL_DMA, +- NV17_CHANNEL_DMA, +- NV10_CHANNEL_DMA, +- NV03_CHANNEL_DMA, +- 0 }; +- const u16 *oclass = oclasses; +- struct nv03_channel_dma_v0 args, *retn; +- struct nouveau_channel *chan; +- int ret; +- +- /* allocate dma push buffer */ +- ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan); +- *pchan = chan; +- if (ret) +- return ret; +- +- /* create channel object */ +- args.version = 0; +- args.pushbuf = chan->push.ctxdma.handle; +- args.offset = chan->push.vma.offset; +- +- do { +- ret = nvif_object_new(nvif_object(device), handle, *oclass++, +- &args, sizeof(args), &chan->object); +- if (ret == 0) { +- retn = chan->object->data; +- chan->chid = retn->chid; +- return ret; +- } +- } while (ret && *oclass); +- +- nouveau_channel_del(pchan); +- return ret; +-} +- +-static int +-nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) +-{ +- struct nvif_device *device = chan->device; +- struct nouveau_cli *cli = (void *)nvif_client(&device->base); +- struct nouveau_vmmgr *vmm = nvkm_vmmgr(device); +- struct nouveau_software_chan *swch; +- struct nv_dma_v0 args = {}; +- int ret, i; +- bool save; +- +- nvif_object_map(chan->object); +- +- /* allocate dma objects to cover all allowed vram, and gart */ +- if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { +- args.target = NV_DMA_V0_TARGET_VM; +- args.access = NV_DMA_V0_ACCESS_VM; +- args.start = 0; +- args.limit = cli->vm->vmm->limit - 1; +- } else { +- args.target = NV_DMA_V0_TARGET_VRAM; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = 0; +- args.limit = device->info.ram_user - 1; +- } +- +- ret = nvif_object_init(chan->object, NULL, vram, +- NV_DMA_IN_MEMORY, &args, +- sizeof(args), &chan->vram); +- if (ret) +- return ret; +- +- if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) { +- args.target = NV_DMA_V0_TARGET_VM; +- args.access = NV_DMA_V0_ACCESS_VM; +- args.start = 0; +- args.limit = cli->vm->vmm->limit - 1; +- } else +- if (chan->drm->agp.stat == ENABLED) { +- args.target = NV_DMA_V0_TARGET_AGP; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = chan->drm->agp.base; +- args.limit = chan->drm->agp.base + +- chan->drm->agp.size - 1; +- } else { +- args.target = NV_DMA_V0_TARGET_VM; +- args.access = NV_DMA_V0_ACCESS_RDWR; +- args.start = 0; +- args.limit = vmm->limit - 1; +- } +- +- ret = nvif_object_init(chan->object, NULL, gart, +- NV_DMA_IN_MEMORY, &args, +- sizeof(args), &chan->gart); +- if (ret) +- return ret; +- } +- +- /* initialise dma tracking parameters */ +- switch (chan->object->oclass & 0x00ff) { +- case 0x006b: +- case 0x006e: +- chan->user_put = 0x40; +- chan->user_get = 0x44; +- chan->dma.max = (0x10000 / 4) - 2; +- break; +- default: +- chan->user_put = 0x40; +- chan->user_get = 0x44; +- chan->user_get_hi = 0x60; +- chan->dma.ib_base = 0x10000 / 4; +- chan->dma.ib_max = (0x02000 / 8) - 1; +- chan->dma.ib_put = 0; +- chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put; +- chan->dma.max = chan->dma.ib_base; +- break; +- } +- +- chan->dma.put = 0; +- chan->dma.cur = chan->dma.put; +- chan->dma.free = chan->dma.max - chan->dma.cur; +- +- ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS); +- if (ret) +- return ret; +- +- for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) +- OUT_RING(chan, 0x00000000); +- +- /* allocate software object class (used for fences on <= nv05) */ +- if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) { +- ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e, +- NULL, 0, &chan->nvsw); +- if (ret) +- return ret; +- +- swch = (void *)nvkm_object(&chan->nvsw)->parent; +- swch->flip = nouveau_flip_complete; +- swch->flip_data = chan; +- +- ret = RING_SPACE(chan, 2); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubSw, 0x0000, 1); +- OUT_RING (chan, chan->nvsw.handle); +- FIRE_RING (chan); +- } +- +- /* initialise synchronisation */ +- save = cli->base.super; +- cli->base.super = true; /* hack until fencenv50 fixed */ +- ret = nouveau_fence(chan->drm)->context_new(chan); +- cli->base.super = save; +- return ret; +-} +- +-int +-nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, +- u32 handle, u32 arg0, u32 arg1, +- struct nouveau_channel **pchan) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&device->base); +- bool super; +- int ret; +- +- /* hack until fencenv50 is fixed, and agp access relaxed */ +- super = cli->base.super; +- cli->base.super = true; +- +- ret = nouveau_channel_ind(drm, device, handle, arg0, pchan); +- if (ret) { +- NV_PRINTK(debug, cli, "ib channel create, %d\n", ret); +- ret = nouveau_channel_dma(drm, device, handle, pchan); +- if (ret) { +- NV_PRINTK(debug, cli, "dma channel create, %d\n", ret); +- goto done; +- } +- } +- +- ret = nouveau_channel_init(*pchan, arg0, arg1); +- if (ret) { +- NV_PRINTK(error, cli, "channel failed to initialise, %d\n", ret); +- nouveau_channel_del(pchan); +- } +- +-done: +- cli->base.super = super; +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h +deleted file mode 100644 +index 8309c24e..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_chan.h ++++ /dev/null +@@ -1,52 +0,0 @@ +-#ifndef __NOUVEAU_CHAN_H__ +-#define __NOUVEAU_CHAN_H__ +- +-#include +-struct nvif_device; +- +-struct nouveau_channel { +- struct nvif_device *device; +- struct nouveau_drm *drm; +- +- int chid; +- +- struct nvif_object vram; +- struct nvif_object gart; +- struct nvif_object nvsw; +- +- struct { +- struct nouveau_bo *buffer; +- struct nouveau_vma vma; +- struct nvif_object ctxdma; +- } push; +- +- /* TODO: this will be reworked in the near future */ +- bool accel_done; +- void *fence; +- struct { +- int max; +- int free; +- int cur; +- int put; +- int ib_base; +- int ib_max; +- int ib_free; +- int ib_put; +- } dma; +- u32 user_get_hi; +- u32 user_get; +- u32 user_put; +- +- struct nvif_object *object; +-}; +- +- +-int nouveau_channel_new(struct nouveau_drm *, struct nvif_device *, +- u32 handle, u32 arg0, u32 arg1, +- struct nouveau_channel **); +-void nouveau_channel_del(struct nouveau_channel **); +-int nouveau_channel_idle(struct nouveau_channel *); +- +-extern int nouveau_vram_pushbuf; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c +deleted file mode 100644 +index a088c96d..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_connector.c ++++ /dev/null +@@ -1,1236 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +- +-#include +- +-#include +-#include +-#include +- +-#include "nouveau_reg.h" +-#include "nouveau_drm.h" +-#include "dispnv04/hw.h" +-#include "nouveau_acpi.h" +- +-#include "nouveau_display.h" +-#include "nouveau_connector.h" +-#include "nouveau_encoder.h" +-#include "nouveau_crtc.h" +- +-#include +- +-MODULE_PARM_DESC(tv_disable, "Disable TV-out detection"); +-int nouveau_tv_disable = 0; +-module_param_named(tv_disable, nouveau_tv_disable, int, 0400); +- +-MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status"); +-int nouveau_ignorelid = 0; +-module_param_named(ignorelid, nouveau_ignorelid, int, 0400); +- +-MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (default: enabled)"); +-int nouveau_duallink = 1; +-module_param_named(duallink, nouveau_duallink, int, 0400); +- +-struct nouveau_encoder * +-find_encoder(struct drm_connector *connector, int type) +-{ +- struct drm_device *dev = connector->dev; +- struct nouveau_encoder *nv_encoder; +- struct drm_encoder *enc; +- int i, id; +- +- for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { +- id = connector->encoder_ids[i]; +- if (!id) +- break; +- +- enc = drm_encoder_find(dev, id); +- if (!enc) +- continue; +- nv_encoder = nouveau_encoder(enc); +- +- if (type == DCB_OUTPUT_ANY || +- (nv_encoder->dcb && nv_encoder->dcb->type == type)) +- return nv_encoder; +- } +- +- return NULL; +-} +- +-struct nouveau_connector * +-nouveau_encoder_connector_get(struct nouveau_encoder *encoder) +-{ +- struct drm_device *dev = to_drm_encoder(encoder)->dev; +- struct drm_connector *drm_connector; +- +- list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head) { +- if (drm_connector->encoder == to_drm_encoder(encoder)) +- return nouveau_connector(drm_connector); +- } +- +- return NULL; +-} +- +-static void +-nouveau_connector_destroy(struct drm_connector *connector) +-{ +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- nvif_notify_fini(&nv_connector->hpd); +- kfree(nv_connector->edid); +- drm_connector_unregister(connector); +- drm_connector_cleanup(connector); +- if (nv_connector->aux.transfer) +- drm_dp_aux_unregister(&nv_connector->aux); +- kfree(connector); +-} +- +-static struct nouveau_encoder * +-nouveau_connector_ddc_detect(struct drm_connector *connector) +-{ +- struct drm_device *dev = connector->dev; +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_gpio *gpio = nvkm_gpio(&drm->device); +- struct nouveau_encoder *nv_encoder; +- struct drm_encoder *encoder; +- int i, panel = -ENODEV; +- +- /* eDP panels need powering on by us (if the VBIOS doesn't default it +- * to on) before doing any AUX channel transactions. LVDS panel power +- * is handled by the SOR itself, and not required for LVDS DDC. +- */ +- if (nv_connector->type == DCB_CONNECTOR_eDP) { +- panel = gpio->get(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff); +- if (panel == 0) { +- gpio->set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, 1); +- msleep(300); +- } +- } +- +- for (i = 0; nv_encoder = NULL, i < DRM_CONNECTOR_MAX_ENCODER; i++) { +- int id = connector->encoder_ids[i]; +- if (id == 0) +- break; +- +- encoder = drm_encoder_find(dev, id); +- if (!encoder) +- continue; +- nv_encoder = nouveau_encoder(encoder); +- +- if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { +- int ret = nouveau_dp_detect(nv_encoder); +- if (ret == 0) +- break; +- } else +- if (nv_encoder->i2c) { +- if (nv_probe_i2c(nv_encoder->i2c, 0x50)) +- break; +- } +- } +- +- /* eDP panel not detected, restore panel power GPIO to previous +- * state to avoid confusing the SOR for other output types. +- */ +- if (!nv_encoder && panel == 0) +- gpio->set(gpio, 0, DCB_GPIO_PANEL_POWER, 0xff, panel); +- +- return nv_encoder; +-} +- +-static struct nouveau_encoder * +-nouveau_connector_of_detect(struct drm_connector *connector) +-{ +-#ifdef __powerpc__ +- struct drm_device *dev = connector->dev; +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder; +- struct device_node *cn, *dn = pci_device_to_OF_node(dev->pdev); +- +- if (!dn || +- !((nv_encoder = find_encoder(connector, DCB_OUTPUT_TMDS)) || +- (nv_encoder = find_encoder(connector, DCB_OUTPUT_ANALOG)))) +- return NULL; +- +- for_each_child_of_node(dn, cn) { +- const char *name = of_get_property(cn, "name", NULL); +- const void *edid = of_get_property(cn, "EDID", NULL); +- int idx = name ? name[strlen(name) - 1] - 'A' : 0; +- +- if (nv_encoder->dcb->i2c_index == idx && edid) { +- nv_connector->edid = +- kmemdup(edid, EDID_LENGTH, GFP_KERNEL); +- of_node_put(cn); +- return nv_encoder; +- } +- } +-#endif +- return NULL; +-} +- +-static void +-nouveau_connector_set_encoder(struct drm_connector *connector, +- struct nouveau_encoder *nv_encoder) +-{ +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct drm_device *dev = connector->dev; +- +- if (nv_connector->detected_encoder == nv_encoder) +- return; +- nv_connector->detected_encoder = nv_encoder; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- connector->interlace_allowed = true; +- connector->doublescan_allowed = true; +- } else +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || +- nv_encoder->dcb->type == DCB_OUTPUT_TMDS) { +- connector->doublescan_allowed = false; +- connector->interlace_allowed = false; +- } else { +- connector->doublescan_allowed = true; +- if (drm->device.info.family == NV_DEVICE_INFO_V0_KELVIN || +- (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && +- (dev->pdev->device & 0x0ff0) != 0x0100 && +- (dev->pdev->device & 0x0ff0) != 0x0150)) +- /* HW is broken */ +- connector->interlace_allowed = false; +- else +- connector->interlace_allowed = true; +- } +- +- if (nv_connector->type == DCB_CONNECTOR_DVI_I) { +- drm_object_property_set_value(&connector->base, +- dev->mode_config.dvi_i_subconnector_property, +- nv_encoder->dcb->type == DCB_OUTPUT_TMDS ? +- DRM_MODE_SUBCONNECTOR_DVID : +- DRM_MODE_SUBCONNECTOR_DVIA); +- } +-} +- +-static enum drm_connector_status +-nouveau_connector_detect(struct drm_connector *connector, bool force) +-{ +- struct drm_device *dev = connector->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder = NULL; +- struct nouveau_encoder *nv_partner; +- struct nouveau_i2c_port *i2c; +- int type; +- int ret; +- enum drm_connector_status conn_status = connector_status_disconnected; +- +- /* Cleanup the previous EDID block. */ +- if (nv_connector->edid) { +- drm_mode_connector_update_edid_property(connector, NULL); +- kfree(nv_connector->edid); +- nv_connector->edid = NULL; +- } +- +- ret = pm_runtime_get_sync(connector->dev->dev); +- if (ret < 0 && ret != -EACCES) +- return conn_status; +- +- nv_encoder = nouveau_connector_ddc_detect(connector); +- if (nv_encoder && (i2c = nv_encoder->i2c) != NULL) { +- nv_connector->edid = drm_get_edid(connector, &i2c->adapter); +- drm_mode_connector_update_edid_property(connector, +- nv_connector->edid); +- if (!nv_connector->edid) { +- NV_ERROR(drm, "DDC responded, but no EDID for %s\n", +- connector->name); +- goto detect_analog; +- } +- +- /* Override encoder type for DVI-I based on whether EDID +- * says the display is digital or analog, both use the +- * same i2c channel so the value returned from ddc_detect +- * isn't necessarily correct. +- */ +- nv_partner = NULL; +- if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) +- nv_partner = find_encoder(connector, DCB_OUTPUT_ANALOG); +- if (nv_encoder->dcb->type == DCB_OUTPUT_ANALOG) +- nv_partner = find_encoder(connector, DCB_OUTPUT_TMDS); +- +- if (nv_partner && ((nv_encoder->dcb->type == DCB_OUTPUT_ANALOG && +- nv_partner->dcb->type == DCB_OUTPUT_TMDS) || +- (nv_encoder->dcb->type == DCB_OUTPUT_TMDS && +- nv_partner->dcb->type == DCB_OUTPUT_ANALOG))) { +- if (nv_connector->edid->input & DRM_EDID_INPUT_DIGITAL) +- type = DCB_OUTPUT_TMDS; +- else +- type = DCB_OUTPUT_ANALOG; +- +- nv_encoder = find_encoder(connector, type); +- } +- +- nouveau_connector_set_encoder(connector, nv_encoder); +- conn_status = connector_status_connected; +- goto out; +- } +- +- nv_encoder = nouveau_connector_of_detect(connector); +- if (nv_encoder) { +- nouveau_connector_set_encoder(connector, nv_encoder); +- conn_status = connector_status_connected; +- goto out; +- } +- +-detect_analog: +- nv_encoder = find_encoder(connector, DCB_OUTPUT_ANALOG); +- if (!nv_encoder && !nouveau_tv_disable) +- nv_encoder = find_encoder(connector, DCB_OUTPUT_TV); +- if (nv_encoder && force) { +- struct drm_encoder *encoder = to_drm_encoder(nv_encoder); +- struct drm_encoder_helper_funcs *helper = +- encoder->helper_private; +- +- if (helper->detect(encoder, connector) == +- connector_status_connected) { +- nouveau_connector_set_encoder(connector, nv_encoder); +- conn_status = connector_status_connected; +- goto out; +- } +- +- } +- +- out: +- +- pm_runtime_mark_last_busy(connector->dev->dev); +- pm_runtime_put_autosuspend(connector->dev->dev); +- +- return conn_status; +-} +- +-static enum drm_connector_status +-nouveau_connector_detect_lvds(struct drm_connector *connector, bool force) +-{ +- struct drm_device *dev = connector->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder = NULL; +- enum drm_connector_status status = connector_status_disconnected; +- +- /* Cleanup the previous EDID block. */ +- if (nv_connector->edid) { +- drm_mode_connector_update_edid_property(connector, NULL); +- kfree(nv_connector->edid); +- nv_connector->edid = NULL; +- } +- +- nv_encoder = find_encoder(connector, DCB_OUTPUT_LVDS); +- if (!nv_encoder) +- return connector_status_disconnected; +- +- /* Try retrieving EDID via DDC */ +- if (!drm->vbios.fp_no_ddc) { +- status = nouveau_connector_detect(connector, force); +- if (status == connector_status_connected) +- goto out; +- } +- +- /* On some laptops (Sony, i'm looking at you) there appears to +- * be no direct way of accessing the panel's EDID. The only +- * option available to us appears to be to ask ACPI for help.. +- * +- * It's important this check's before trying straps, one of the +- * said manufacturer's laptops are configured in such a way +- * the nouveau decides an entry in the VBIOS FP mode table is +- * valid - it's not (rh#613284) +- */ +- if (nv_encoder->dcb->lvdsconf.use_acpi_for_edid) { +- if ((nv_connector->edid = nouveau_acpi_edid(dev, connector))) { +- status = connector_status_connected; +- goto out; +- } +- } +- +- /* If no EDID found above, and the VBIOS indicates a hardcoded +- * modeline is avalilable for the panel, set it as the panel's +- * native mode and exit. +- */ +- if (nouveau_bios_fp_mode(dev, NULL) && (drm->vbios.fp_no_ddc || +- nv_encoder->dcb->lvdsconf.use_straps_for_mode)) { +- status = connector_status_connected; +- goto out; +- } +- +- /* Still nothing, some VBIOS images have a hardcoded EDID block +- * stored for the panel stored in them. +- */ +- if (!drm->vbios.fp_no_ddc) { +- struct edid *edid = +- (struct edid *)nouveau_bios_embedded_edid(dev); +- if (edid) { +- nv_connector->edid = +- kmemdup(edid, EDID_LENGTH, GFP_KERNEL); +- if (nv_connector->edid) +- status = connector_status_connected; +- } +- } +- +-out: +-#if defined(CONFIG_ACPI_BUTTON) || \ +- (defined(CONFIG_ACPI_BUTTON_MODULE) && defined(MODULE)) +- if (status == connector_status_connected && +- !nouveau_ignorelid && !acpi_lid_open()) +- status = connector_status_unknown; +-#endif +- +- drm_mode_connector_update_edid_property(connector, nv_connector->edid); +- nouveau_connector_set_encoder(connector, nv_encoder); +- return status; +-} +- +-static void +-nouveau_connector_force(struct drm_connector *connector) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder; +- int type; +- +- if (nv_connector->type == DCB_CONNECTOR_DVI_I) { +- if (connector->force == DRM_FORCE_ON_DIGITAL) +- type = DCB_OUTPUT_TMDS; +- else +- type = DCB_OUTPUT_ANALOG; +- } else +- type = DCB_OUTPUT_ANY; +- +- nv_encoder = find_encoder(connector, type); +- if (!nv_encoder) { +- NV_ERROR(drm, "can't find encoder to force %s on!\n", +- connector->name); +- connector->status = connector_status_disconnected; +- return; +- } +- +- nouveau_connector_set_encoder(connector, nv_encoder); +-} +- +-static int +-nouveau_connector_set_property(struct drm_connector *connector, +- struct drm_property *property, uint64_t value) +-{ +- struct nouveau_display *disp = nouveau_display(connector->dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; +- struct drm_encoder *encoder = to_drm_encoder(nv_encoder); +- struct drm_device *dev = connector->dev; +- struct nouveau_crtc *nv_crtc; +- int ret; +- +- nv_crtc = NULL; +- if (connector->encoder && connector->encoder->crtc) +- nv_crtc = nouveau_crtc(connector->encoder->crtc); +- +- /* Scaling mode */ +- if (property == dev->mode_config.scaling_mode_property) { +- bool modeset = false; +- +- switch (value) { +- case DRM_MODE_SCALE_NONE: +- case DRM_MODE_SCALE_FULLSCREEN: +- case DRM_MODE_SCALE_CENTER: +- case DRM_MODE_SCALE_ASPECT: +- break; +- default: +- return -EINVAL; +- } +- +- /* LVDS always needs gpu scaling */ +- if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS && +- value == DRM_MODE_SCALE_NONE) +- return -EINVAL; +- +- /* Changing between GPU and panel scaling requires a full +- * modeset +- */ +- if ((nv_connector->scaling_mode == DRM_MODE_SCALE_NONE) || +- (value == DRM_MODE_SCALE_NONE)) +- modeset = true; +- nv_connector->scaling_mode = value; +- +- if (!nv_crtc) +- return 0; +- +- if (modeset || !nv_crtc->set_scale) { +- ret = drm_crtc_helper_set_mode(&nv_crtc->base, +- &nv_crtc->base.mode, +- nv_crtc->base.x, +- nv_crtc->base.y, NULL); +- if (!ret) +- return -EINVAL; +- } else { +- ret = nv_crtc->set_scale(nv_crtc, true); +- if (ret) +- return ret; +- } +- +- return 0; +- } +- +- /* Underscan */ +- if (property == disp->underscan_property) { +- if (nv_connector->underscan != value) { +- nv_connector->underscan = value; +- if (!nv_crtc || !nv_crtc->set_scale) +- return 0; +- +- return nv_crtc->set_scale(nv_crtc, true); +- } +- +- return 0; +- } +- +- if (property == disp->underscan_hborder_property) { +- if (nv_connector->underscan_hborder != value) { +- nv_connector->underscan_hborder = value; +- if (!nv_crtc || !nv_crtc->set_scale) +- return 0; +- +- return nv_crtc->set_scale(nv_crtc, true); +- } +- +- return 0; +- } +- +- if (property == disp->underscan_vborder_property) { +- if (nv_connector->underscan_vborder != value) { +- nv_connector->underscan_vborder = value; +- if (!nv_crtc || !nv_crtc->set_scale) +- return 0; +- +- return nv_crtc->set_scale(nv_crtc, true); +- } +- +- return 0; +- } +- +- /* Dithering */ +- if (property == disp->dithering_mode) { +- nv_connector->dithering_mode = value; +- if (!nv_crtc || !nv_crtc->set_dither) +- return 0; +- +- return nv_crtc->set_dither(nv_crtc, true); +- } +- +- if (property == disp->dithering_depth) { +- nv_connector->dithering_depth = value; +- if (!nv_crtc || !nv_crtc->set_dither) +- return 0; +- +- return nv_crtc->set_dither(nv_crtc, true); +- } +- +- if (nv_crtc && nv_crtc->set_color_vibrance) { +- /* Hue */ +- if (property == disp->vibrant_hue_property) { +- nv_crtc->vibrant_hue = value - 90; +- return nv_crtc->set_color_vibrance(nv_crtc, true); +- } +- /* Saturation */ +- if (property == disp->color_vibrance_property) { +- nv_crtc->color_vibrance = value - 100; +- return nv_crtc->set_color_vibrance(nv_crtc, true); +- } +- } +- +- if (nv_encoder && nv_encoder->dcb->type == DCB_OUTPUT_TV) +- return get_slave_funcs(encoder)->set_property( +- encoder, connector, property, value); +- +- return -EINVAL; +-} +- +-static struct drm_display_mode * +-nouveau_connector_native_mode(struct drm_connector *connector) +-{ +- struct drm_connector_helper_funcs *helper = connector->helper_private; +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct drm_device *dev = connector->dev; +- struct drm_display_mode *mode, *largest = NULL; +- int high_w = 0, high_h = 0, high_v = 0; +- +- list_for_each_entry(mode, &nv_connector->base.probed_modes, head) { +- mode->vrefresh = drm_mode_vrefresh(mode); +- if (helper->mode_valid(connector, mode) != MODE_OK || +- (mode->flags & DRM_MODE_FLAG_INTERLACE)) +- continue; +- +- /* Use preferred mode if there is one.. */ +- if (mode->type & DRM_MODE_TYPE_PREFERRED) { +- NV_DEBUG(drm, "native mode from preferred\n"); +- return drm_mode_duplicate(dev, mode); +- } +- +- /* Otherwise, take the resolution with the largest width, then +- * height, then vertical refresh +- */ +- if (mode->hdisplay < high_w) +- continue; +- +- if (mode->hdisplay == high_w && mode->vdisplay < high_h) +- continue; +- +- if (mode->hdisplay == high_w && mode->vdisplay == high_h && +- mode->vrefresh < high_v) +- continue; +- +- high_w = mode->hdisplay; +- high_h = mode->vdisplay; +- high_v = mode->vrefresh; +- largest = mode; +- } +- +- NV_DEBUG(drm, "native mode from largest: %dx%d@%d\n", +- high_w, high_h, high_v); +- return largest ? drm_mode_duplicate(dev, largest) : NULL; +-} +- +-struct moderec { +- int hdisplay; +- int vdisplay; +-}; +- +-static struct moderec scaler_modes[] = { +- { 1920, 1200 }, +- { 1920, 1080 }, +- { 1680, 1050 }, +- { 1600, 1200 }, +- { 1400, 1050 }, +- { 1280, 1024 }, +- { 1280, 960 }, +- { 1152, 864 }, +- { 1024, 768 }, +- { 800, 600 }, +- { 720, 400 }, +- { 640, 480 }, +- { 640, 400 }, +- { 640, 350 }, +- {} +-}; +- +-static int +-nouveau_connector_scaler_modes_add(struct drm_connector *connector) +-{ +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct drm_display_mode *native = nv_connector->native_mode, *m; +- struct drm_device *dev = connector->dev; +- struct moderec *mode = &scaler_modes[0]; +- int modes = 0; +- +- if (!native) +- return 0; +- +- while (mode->hdisplay) { +- if (mode->hdisplay <= native->hdisplay && +- mode->vdisplay <= native->vdisplay) { +- m = drm_cvt_mode(dev, mode->hdisplay, mode->vdisplay, +- drm_mode_vrefresh(native), false, +- false, false); +- if (!m) +- continue; +- +- m->type |= DRM_MODE_TYPE_DRIVER; +- +- drm_mode_probed_add(connector, m); +- modes++; +- } +- +- mode++; +- } +- +- return modes; +-} +- +-static void +-nouveau_connector_detect_depth(struct drm_connector *connector) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; +- struct nvbios *bios = &drm->vbios; +- struct drm_display_mode *mode = nv_connector->native_mode; +- bool duallink; +- +- /* if the edid is feeling nice enough to provide this info, use it */ +- if (nv_connector->edid && connector->display_info.bpc) +- return; +- +- /* EDID 1.4 is *supposed* to be supported on eDP, but, Apple... */ +- if (nv_connector->type == DCB_CONNECTOR_eDP) { +- connector->display_info.bpc = 6; +- return; +- } +- +- /* we're out of options unless we're LVDS, default to 8bpc */ +- if (nv_encoder->dcb->type != DCB_OUTPUT_LVDS) { +- connector->display_info.bpc = 8; +- return; +- } +- +- connector->display_info.bpc = 6; +- +- /* LVDS: panel straps */ +- if (bios->fp_no_ddc) { +- if (bios->fp.if_is_24bit) +- connector->display_info.bpc = 8; +- return; +- } +- +- /* LVDS: DDC panel, need to first determine the number of links to +- * know which if_is_24bit flag to check... +- */ +- if (nv_connector->edid && +- nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) +- duallink = ((u8 *)nv_connector->edid)[121] == 2; +- else +- duallink = mode->clock >= bios->fp.duallink_transition_clk; +- +- if ((!duallink && (bios->fp.strapless_is_24bit & 1)) || +- ( duallink && (bios->fp.strapless_is_24bit & 2))) +- connector->display_info.bpc = 8; +-} +- +-static int +-nouveau_connector_get_modes(struct drm_connector *connector) +-{ +- struct drm_device *dev = connector->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; +- struct drm_encoder *encoder = to_drm_encoder(nv_encoder); +- int ret = 0; +- +- /* destroy the native mode, the attached monitor could have changed. +- */ +- if (nv_connector->native_mode) { +- drm_mode_destroy(dev, nv_connector->native_mode); +- nv_connector->native_mode = NULL; +- } +- +- if (nv_connector->edid) +- ret = drm_add_edid_modes(connector, nv_connector->edid); +- else +- if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS && +- (nv_encoder->dcb->lvdsconf.use_straps_for_mode || +- drm->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) { +- struct drm_display_mode mode; +- +- nouveau_bios_fp_mode(dev, &mode); +- nv_connector->native_mode = drm_mode_duplicate(dev, &mode); +- } +- +- /* Determine display colour depth for everything except LVDS now, +- * DP requires this before mode_valid() is called. +- */ +- if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS) +- nouveau_connector_detect_depth(connector); +- +- /* Find the native mode if this is a digital panel, if we didn't +- * find any modes through DDC previously add the native mode to +- * the list of modes. +- */ +- if (!nv_connector->native_mode) +- nv_connector->native_mode = +- nouveau_connector_native_mode(connector); +- if (ret == 0 && nv_connector->native_mode) { +- struct drm_display_mode *mode; +- +- mode = drm_mode_duplicate(dev, nv_connector->native_mode); +- drm_mode_probed_add(connector, mode); +- ret = 1; +- } +- +- /* Determine LVDS colour depth, must happen after determining +- * "native" mode as some VBIOS tables require us to use the +- * pixel clock as part of the lookup... +- */ +- if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) +- nouveau_connector_detect_depth(connector); +- +- if (nv_encoder->dcb->type == DCB_OUTPUT_TV) +- ret = get_slave_funcs(encoder)->get_modes(encoder, connector); +- +- if (nv_connector->type == DCB_CONNECTOR_LVDS || +- nv_connector->type == DCB_CONNECTOR_LVDS_SPWG || +- nv_connector->type == DCB_CONNECTOR_eDP) +- ret += nouveau_connector_scaler_modes_add(connector); +- +- return ret; +-} +- +-static unsigned +-get_tmds_link_bandwidth(struct drm_connector *connector) +-{ +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct dcb_output *dcb = nv_connector->detected_encoder->dcb; +- +- if (dcb->location != DCB_LOC_ON_CHIP || +- drm->device.info.chipset >= 0x46) +- return 165000; +- else if (drm->device.info.chipset >= 0x40) +- return 155000; +- else if (drm->device.info.chipset >= 0x18) +- return 135000; +- else +- return 112000; +-} +- +-static int +-nouveau_connector_mode_valid(struct drm_connector *connector, +- struct drm_display_mode *mode) +-{ +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder; +- struct drm_encoder *encoder = to_drm_encoder(nv_encoder); +- unsigned min_clock = 25000, max_clock = min_clock; +- unsigned clock = mode->clock; +- +- switch (nv_encoder->dcb->type) { +- case DCB_OUTPUT_LVDS: +- if (nv_connector->native_mode && +- (mode->hdisplay > nv_connector->native_mode->hdisplay || +- mode->vdisplay > nv_connector->native_mode->vdisplay)) +- return MODE_PANEL; +- +- min_clock = 0; +- max_clock = 400000; +- break; +- case DCB_OUTPUT_TMDS: +- max_clock = get_tmds_link_bandwidth(connector); +- if (nouveau_duallink && nv_encoder->dcb->duallink_possible) +- max_clock *= 2; +- break; +- case DCB_OUTPUT_ANALOG: +- max_clock = nv_encoder->dcb->crtconf.maxfreq; +- if (!max_clock) +- max_clock = 350000; +- break; +- case DCB_OUTPUT_TV: +- return get_slave_funcs(encoder)->mode_valid(encoder, mode); +- case DCB_OUTPUT_DP: +- max_clock = nv_encoder->dp.link_nr; +- max_clock *= nv_encoder->dp.link_bw; +- clock = clock * (connector->display_info.bpc * 3) / 10; +- break; +- default: +- BUG_ON(1); +- return MODE_BAD; +- } +- +- if (clock < min_clock) +- return MODE_CLOCK_LOW; +- +- if (clock > max_clock) +- return MODE_CLOCK_HIGH; +- +- return MODE_OK; +-} +- +-static struct drm_encoder * +-nouveau_connector_best_encoder(struct drm_connector *connector) +-{ +- struct nouveau_connector *nv_connector = nouveau_connector(connector); +- +- if (nv_connector->detected_encoder) +- return to_drm_encoder(nv_connector->detected_encoder); +- +- return NULL; +-} +- +-static const struct drm_connector_helper_funcs +-nouveau_connector_helper_funcs = { +- .get_modes = nouveau_connector_get_modes, +- .mode_valid = nouveau_connector_mode_valid, +- .best_encoder = nouveau_connector_best_encoder, +-}; +- +-static const struct drm_connector_funcs +-nouveau_connector_funcs = { +- .dpms = drm_helper_connector_dpms, +- .save = NULL, +- .restore = NULL, +- .detect = nouveau_connector_detect, +- .destroy = nouveau_connector_destroy, +- .fill_modes = drm_helper_probe_single_connector_modes, +- .set_property = nouveau_connector_set_property, +- .force = nouveau_connector_force +-}; +- +-static const struct drm_connector_funcs +-nouveau_connector_funcs_lvds = { +- .dpms = drm_helper_connector_dpms, +- .save = NULL, +- .restore = NULL, +- .detect = nouveau_connector_detect_lvds, +- .destroy = nouveau_connector_destroy, +- .fill_modes = drm_helper_probe_single_connector_modes, +- .set_property = nouveau_connector_set_property, +- .force = nouveau_connector_force +-}; +- +-static void +-nouveau_connector_dp_dpms(struct drm_connector *connector, int mode) +-{ +- struct nouveau_encoder *nv_encoder = NULL; +- +- if (connector->encoder) +- nv_encoder = nouveau_encoder(connector->encoder); +- if (nv_encoder && nv_encoder->dcb && +- nv_encoder->dcb->type == DCB_OUTPUT_DP) { +- if (mode == DRM_MODE_DPMS_ON) { +- u8 data = DP_SET_POWER_D0; +- nv_wraux(nv_encoder->i2c, DP_SET_POWER, &data, 1); +- usleep_range(1000, 2000); +- } else { +- u8 data = DP_SET_POWER_D3; +- nv_wraux(nv_encoder->i2c, DP_SET_POWER, &data, 1); +- } +- } +- +- drm_helper_connector_dpms(connector, mode); +-} +- +-static const struct drm_connector_funcs +-nouveau_connector_funcs_dp = { +- .dpms = nouveau_connector_dp_dpms, +- .save = NULL, +- .restore = NULL, +- .detect = nouveau_connector_detect, +- .destroy = nouveau_connector_destroy, +- .fill_modes = drm_helper_probe_single_connector_modes, +- .set_property = nouveau_connector_set_property, +- .force = nouveau_connector_force +-}; +- +-static int +-nouveau_connector_hotplug(struct nvif_notify *notify) +-{ +- struct nouveau_connector *nv_connector = +- container_of(notify, typeof(*nv_connector), hpd); +- struct drm_connector *connector = &nv_connector->base; +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- const struct nvif_notify_conn_rep_v0 *rep = notify->data; +- const char *name = connector->name; +- +- if (rep->mask & NVIF_NOTIFY_CONN_V0_IRQ) { +- } else { +- bool plugged = (rep->mask != NVIF_NOTIFY_CONN_V0_UNPLUG); +- +- NV_DEBUG(drm, "%splugged %s\n", plugged ? "" : "un", name); +- +- mutex_lock(&drm->dev->mode_config.mutex); +- if (plugged) +- drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); +- else +- drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); +- mutex_unlock(&drm->dev->mode_config.mutex); +- +- drm_helper_hpd_irq_event(connector->dev); +- } +- +- return NVIF_NOTIFY_KEEP; +-} +- +-static ssize_t +-nouveau_connector_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) +-{ +- struct nouveau_connector *nv_connector = +- container_of(aux, typeof(*nv_connector), aux); +- struct nouveau_encoder *nv_encoder; +- struct nouveau_i2c_port *port; +- int ret; +- +- nv_encoder = find_encoder(&nv_connector->base, DCB_OUTPUT_DP); +- if (!nv_encoder || !(port = nv_encoder->i2c)) +- return -ENODEV; +- if (WARN_ON(msg->size > 16)) +- return -E2BIG; +- if (msg->size == 0) +- return msg->size; +- +- ret = nouveau_i2c(port)->acquire(port, 0); +- if (ret) +- return ret; +- +- ret = port->func->aux(port, false, msg->request, msg->address, +- msg->buffer, msg->size); +- nouveau_i2c(port)->release(port); +- if (ret >= 0) { +- msg->reply = ret; +- return msg->size; +- } +- +- return ret; +-} +- +-static int +-drm_conntype_from_dcb(enum dcb_connector_type dcb) +-{ +- switch (dcb) { +- case DCB_CONNECTOR_VGA : return DRM_MODE_CONNECTOR_VGA; +- case DCB_CONNECTOR_TV_0 : +- case DCB_CONNECTOR_TV_1 : +- case DCB_CONNECTOR_TV_3 : return DRM_MODE_CONNECTOR_TV; +- case DCB_CONNECTOR_DMS59_0 : +- case DCB_CONNECTOR_DMS59_1 : +- case DCB_CONNECTOR_DVI_I : return DRM_MODE_CONNECTOR_DVII; +- case DCB_CONNECTOR_DVI_D : return DRM_MODE_CONNECTOR_DVID; +- case DCB_CONNECTOR_LVDS : +- case DCB_CONNECTOR_LVDS_SPWG: return DRM_MODE_CONNECTOR_LVDS; +- case DCB_CONNECTOR_DMS59_DP0: +- case DCB_CONNECTOR_DMS59_DP1: +- case DCB_CONNECTOR_DP : return DRM_MODE_CONNECTOR_DisplayPort; +- case DCB_CONNECTOR_eDP : return DRM_MODE_CONNECTOR_eDP; +- case DCB_CONNECTOR_HDMI_0 : +- case DCB_CONNECTOR_HDMI_1 : +- case DCB_CONNECTOR_HDMI_C : return DRM_MODE_CONNECTOR_HDMIA; +- default: +- break; +- } +- +- return DRM_MODE_CONNECTOR_Unknown; +-} +- +-struct drm_connector * +-nouveau_connector_create(struct drm_device *dev, int index) +-{ +- const struct drm_connector_funcs *funcs = &nouveau_connector_funcs; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_display *disp = nouveau_display(dev); +- struct nouveau_connector *nv_connector = NULL; +- struct drm_connector *connector; +- int type, ret = 0; +- bool dummy; +- +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- nv_connector = nouveau_connector(connector); +- if (nv_connector->index == index) +- return connector; +- } +- +- nv_connector = kzalloc(sizeof(*nv_connector), GFP_KERNEL); +- if (!nv_connector) +- return ERR_PTR(-ENOMEM); +- +- connector = &nv_connector->base; +- nv_connector->index = index; +- +- /* attempt to parse vbios connector type and hotplug gpio */ +- nv_connector->dcb = olddcb_conn(dev, index); +- if (nv_connector->dcb) { +- u32 entry = ROM16(nv_connector->dcb[0]); +- if (olddcb_conntab(dev)[3] >= 4) +- entry |= (u32)ROM16(nv_connector->dcb[2]) << 16; +- +- nv_connector->type = nv_connector->dcb[0]; +- if (drm_conntype_from_dcb(nv_connector->type) == +- DRM_MODE_CONNECTOR_Unknown) { +- NV_WARN(drm, "unknown connector type %02x\n", +- nv_connector->type); +- nv_connector->type = DCB_CONNECTOR_NONE; +- } +- +- /* Gigabyte NX85T */ +- if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) { +- if (nv_connector->type == DCB_CONNECTOR_HDMI_1) +- nv_connector->type = DCB_CONNECTOR_DVI_I; +- } +- +- /* Gigabyte GV-NX86T512H */ +- if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) { +- if (nv_connector->type == DCB_CONNECTOR_HDMI_1) +- nv_connector->type = DCB_CONNECTOR_DVI_I; +- } +- } else { +- nv_connector->type = DCB_CONNECTOR_NONE; +- } +- +- /* no vbios data, or an unknown dcb connector type - attempt to +- * figure out something suitable ourselves +- */ +- if (nv_connector->type == DCB_CONNECTOR_NONE) { +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct dcb_table *dcbt = &drm->vbios.dcb; +- u32 encoders = 0; +- int i; +- +- for (i = 0; i < dcbt->entries; i++) { +- if (dcbt->entry[i].connector == nv_connector->index) +- encoders |= (1 << dcbt->entry[i].type); +- } +- +- if (encoders & (1 << DCB_OUTPUT_DP)) { +- if (encoders & (1 << DCB_OUTPUT_TMDS)) +- nv_connector->type = DCB_CONNECTOR_DP; +- else +- nv_connector->type = DCB_CONNECTOR_eDP; +- } else +- if (encoders & (1 << DCB_OUTPUT_TMDS)) { +- if (encoders & (1 << DCB_OUTPUT_ANALOG)) +- nv_connector->type = DCB_CONNECTOR_DVI_I; +- else +- nv_connector->type = DCB_CONNECTOR_DVI_D; +- } else +- if (encoders & (1 << DCB_OUTPUT_ANALOG)) { +- nv_connector->type = DCB_CONNECTOR_VGA; +- } else +- if (encoders & (1 << DCB_OUTPUT_LVDS)) { +- nv_connector->type = DCB_CONNECTOR_LVDS; +- } else +- if (encoders & (1 << DCB_OUTPUT_TV)) { +- nv_connector->type = DCB_CONNECTOR_TV_0; +- } +- } +- +- switch ((type = drm_conntype_from_dcb(nv_connector->type))) { +- case DRM_MODE_CONNECTOR_LVDS: +- ret = nouveau_bios_parse_lvds_table(dev, 0, &dummy, &dummy); +- if (ret) { +- NV_ERROR(drm, "Error parsing LVDS table, disabling\n"); +- kfree(nv_connector); +- return ERR_PTR(ret); +- } +- +- funcs = &nouveau_connector_funcs_lvds; +- break; +- case DRM_MODE_CONNECTOR_DisplayPort: +- case DRM_MODE_CONNECTOR_eDP: +- nv_connector->aux.dev = dev->dev; +- nv_connector->aux.transfer = nouveau_connector_aux_xfer; +- ret = drm_dp_aux_register(&nv_connector->aux); +- if (ret) { +- NV_ERROR(drm, "failed to register aux channel\n"); +- kfree(nv_connector); +- return ERR_PTR(ret); +- } +- +- funcs = &nouveau_connector_funcs_dp; +- break; +- default: +- funcs = &nouveau_connector_funcs; +- break; +- } +- +- /* defaults, will get overridden in detect() */ +- connector->interlace_allowed = false; +- connector->doublescan_allowed = false; +- +- drm_connector_init(dev, connector, funcs, type); +- drm_connector_helper_add(connector, &nouveau_connector_helper_funcs); +- +- /* Init DVI-I specific properties */ +- if (nv_connector->type == DCB_CONNECTOR_DVI_I) +- drm_object_attach_property(&connector->base, dev->mode_config.dvi_i_subconnector_property, 0); +- +- /* Add overscan compensation options to digital outputs */ +- if (disp->underscan_property && +- (type == DRM_MODE_CONNECTOR_DVID || +- type == DRM_MODE_CONNECTOR_DVII || +- type == DRM_MODE_CONNECTOR_HDMIA || +- type == DRM_MODE_CONNECTOR_DisplayPort)) { +- drm_object_attach_property(&connector->base, +- disp->underscan_property, +- UNDERSCAN_OFF); +- drm_object_attach_property(&connector->base, +- disp->underscan_hborder_property, +- 0); +- drm_object_attach_property(&connector->base, +- disp->underscan_vborder_property, +- 0); +- } +- +- /* Add hue and saturation options */ +- if (disp->vibrant_hue_property) +- drm_object_attach_property(&connector->base, +- disp->vibrant_hue_property, +- 90); +- if (disp->color_vibrance_property) +- drm_object_attach_property(&connector->base, +- disp->color_vibrance_property, +- 150); +- +- switch (nv_connector->type) { +- case DCB_CONNECTOR_VGA: +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- drm_object_attach_property(&connector->base, +- dev->mode_config.scaling_mode_property, +- nv_connector->scaling_mode); +- } +- /* fall-through */ +- case DCB_CONNECTOR_TV_0: +- case DCB_CONNECTOR_TV_1: +- case DCB_CONNECTOR_TV_3: +- nv_connector->scaling_mode = DRM_MODE_SCALE_NONE; +- break; +- default: +- nv_connector->scaling_mode = DRM_MODE_SCALE_FULLSCREEN; +- +- drm_object_attach_property(&connector->base, +- dev->mode_config.scaling_mode_property, +- nv_connector->scaling_mode); +- if (disp->dithering_mode) { +- nv_connector->dithering_mode = DITHERING_MODE_AUTO; +- drm_object_attach_property(&connector->base, +- disp->dithering_mode, +- nv_connector->dithering_mode); +- } +- if (disp->dithering_depth) { +- nv_connector->dithering_depth = DITHERING_DEPTH_AUTO; +- drm_object_attach_property(&connector->base, +- disp->dithering_depth, +- nv_connector->dithering_depth); +- } +- break; +- } +- +- ret = nvif_notify_init(&disp->disp, NULL, nouveau_connector_hotplug, +- true, NV04_DISP_NTFY_CONN, +- &(struct nvif_notify_conn_req_v0) { +- .mask = NVIF_NOTIFY_CONN_V0_ANY, +- .conn = index, +- }, +- sizeof(struct nvif_notify_conn_req_v0), +- sizeof(struct nvif_notify_conn_rep_v0), +- &nv_connector->hpd); +- if (ret) +- connector->polled = DRM_CONNECTOR_POLL_CONNECT; +- else +- connector->polled = DRM_CONNECTOR_POLL_HPD; +- +- drm_connector_register(connector); +- return connector; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h +deleted file mode 100644 +index 629a380c..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_connector.h ++++ /dev/null +@@ -1,112 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NOUVEAU_CONNECTOR_H__ +-#define __NOUVEAU_CONNECTOR_H__ +- +-#include +- +-#include +-#include +-#include "nouveau_crtc.h" +- +-struct nouveau_i2c_port; +- +-enum nouveau_underscan_type { +- UNDERSCAN_OFF, +- UNDERSCAN_ON, +- UNDERSCAN_AUTO, +-}; +- +-/* the enum values specifically defined here match nv50/nvd0 hw values, and +- * the code relies on this +- */ +-enum nouveau_dithering_mode { +- DITHERING_MODE_OFF = 0x00, +- DITHERING_MODE_ON = 0x01, +- DITHERING_MODE_DYNAMIC2X2 = 0x10 | DITHERING_MODE_ON, +- DITHERING_MODE_STATIC2X2 = 0x18 | DITHERING_MODE_ON, +- DITHERING_MODE_TEMPORAL = 0x20 | DITHERING_MODE_ON, +- DITHERING_MODE_AUTO +-}; +- +-enum nouveau_dithering_depth { +- DITHERING_DEPTH_6BPC = 0x00, +- DITHERING_DEPTH_8BPC = 0x02, +- DITHERING_DEPTH_AUTO +-}; +- +-struct nouveau_connector { +- struct drm_connector base; +- enum dcb_connector_type type; +- u8 index; +- u8 *dcb; +- +- struct nvif_notify hpd; +- +- struct drm_dp_aux aux; +- +- int dithering_mode; +- int dithering_depth; +- int scaling_mode; +- enum nouveau_underscan_type underscan; +- u32 underscan_hborder; +- u32 underscan_vborder; +- +- struct nouveau_encoder *detected_encoder; +- struct edid *edid; +- struct drm_display_mode *native_mode; +-}; +- +-static inline struct nouveau_connector *nouveau_connector( +- struct drm_connector *con) +-{ +- return container_of(con, struct nouveau_connector, base); +-} +- +-static inline struct nouveau_connector * +-nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) +-{ +- struct drm_device *dev = nv_crtc->base.dev; +- struct drm_connector *connector; +- struct drm_crtc *crtc = to_drm_crtc(nv_crtc); +- +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- if (connector->encoder && connector->encoder->crtc == crtc) +- return nouveau_connector(connector); +- } +- +- return NULL; +-} +- +-struct drm_connector * +-nouveau_connector_create(struct drm_device *, int index); +- +-extern int nouveau_tv_disable; +-extern int nouveau_ignorelid; +-extern int nouveau_duallink; +- +-#endif /* __NOUVEAU_CONNECTOR_H__ */ +diff --git a/drivers/gpu/drm/nouveau/nouveau_crtc.h b/drivers/gpu/drm/nouveau/nouveau_crtc.h +deleted file mode 100644 +index f19cb1c5..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_crtc.h ++++ /dev/null +@@ -1,90 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NOUVEAU_CRTC_H__ +-#define __NOUVEAU_CRTC_H__ +- +-#include +- +-struct nouveau_crtc { +- struct drm_crtc base; +- +- int index; +- struct nvif_notify vblank; +- +- uint32_t dpms_saved_fp_control; +- uint32_t fp_users; +- int saturation; +- int color_vibrance; +- int vibrant_hue; +- int sharpness; +- int last_dpms; +- +- int cursor_saved_x, cursor_saved_y; +- +- struct { +- int cpp; +- bool blanked; +- uint32_t offset; +- uint32_t handle; +- } fb; +- +- struct { +- struct nouveau_bo *nvbo; +- bool visible; +- uint32_t offset; +- void (*set_offset)(struct nouveau_crtc *, uint32_t offset); +- void (*set_pos)(struct nouveau_crtc *, int x, int y); +- void (*hide)(struct nouveau_crtc *, bool update); +- void (*show)(struct nouveau_crtc *, bool update); +- } cursor; +- +- struct { +- struct nouveau_bo *nvbo; +- uint16_t r[256]; +- uint16_t g[256]; +- uint16_t b[256]; +- int depth; +- } lut; +- +- int (*set_dither)(struct nouveau_crtc *crtc, bool update); +- int (*set_scale)(struct nouveau_crtc *crtc, bool update); +- int (*set_color_vibrance)(struct nouveau_crtc *crtc, bool update); +-}; +- +-static inline struct nouveau_crtc *nouveau_crtc(struct drm_crtc *crtc) +-{ +- return crtc ? container_of(crtc, struct nouveau_crtc, base) : NULL; +-} +- +-static inline struct drm_crtc *to_drm_crtc(struct nouveau_crtc *crtc) +-{ +- return &crtc->base; +-} +- +-int nv04_cursor_init(struct nouveau_crtc *); +- +-#endif /* __NOUVEAU_CRTC_H__ */ +diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c +deleted file mode 100644 +index 5392e07e..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c ++++ /dev/null +@@ -1,64 +0,0 @@ +-/* +- * Copyright (C) 2009 Red Hat +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-/* +- * Authors: +- * Ben Skeggs +- */ +- +-#include "nouveau_debugfs.h" +-#include "nouveau_drm.h" +- +-static int +-nouveau_debugfs_vbios_image(struct seq_file *m, void *data) +-{ +- struct drm_info_node *node = (struct drm_info_node *) m->private; +- struct nouveau_drm *drm = nouveau_drm(node->minor->dev); +- int i; +- +- for (i = 0; i < drm->vbios.length; i++) +- seq_printf(m, "%c", drm->vbios.data[i]); +- return 0; +-} +- +-static struct drm_info_list nouveau_debugfs_list[] = { +- { "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL }, +-}; +-#define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list) +- +-int +-nouveau_debugfs_init(struct drm_minor *minor) +-{ +- drm_debugfs_create_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES, +- minor->debugfs_root, minor); +- return 0; +-} +- +-void +-nouveau_debugfs_takedown(struct drm_minor *minor) +-{ +- drm_debugfs_remove_files(nouveau_debugfs_list, NOUVEAU_DEBUGFS_ENTRIES, +- minor); +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.h b/drivers/gpu/drm/nouveau/nouveau_debugfs.h +deleted file mode 100644 +index a62af6fb..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_debugfs.h ++++ /dev/null +@@ -1,22 +0,0 @@ +-#ifndef __NOUVEAU_DEBUGFS_H__ +-#define __NOUVEAU_DEBUGFS_H__ +- +-#include +- +-#if defined(CONFIG_DEBUG_FS) +-extern int nouveau_debugfs_init(struct drm_minor *); +-extern void nouveau_debugfs_takedown(struct drm_minor *); +-#else +-static inline int +-nouveau_debugfs_init(struct drm_minor *minor) +-{ +- return 0; +-} +- +-static inline void nouveau_debugfs_takedown(struct drm_minor *minor) +-{ +-} +- +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c +deleted file mode 100644 +index a88e6927..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_display.c ++++ /dev/null +@@ -1,895 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +-#include +- +-#include +- +-#include "nouveau_fbcon.h" +-#include "dispnv04/hw.h" +-#include "nouveau_crtc.h" +-#include "nouveau_dma.h" +-#include "nouveau_gem.h" +-#include "nouveau_connector.h" +-#include "nv50_display.h" +- +-#include "nouveau_fence.h" +- +-#include +- +-static int +-nouveau_display_vblank_handler(struct nvif_notify *notify) +-{ +- struct nouveau_crtc *nv_crtc = +- container_of(notify, typeof(*nv_crtc), vblank); +- drm_handle_vblank(nv_crtc->base.dev, nv_crtc->index); +- return NVIF_NOTIFY_KEEP; +-} +- +-int +-nouveau_display_vblank_enable(struct drm_device *dev, int head) +-{ +- struct drm_crtc *crtc; +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- if (nv_crtc->index == head) { +- nvif_notify_get(&nv_crtc->vblank); +- return 0; +- } +- } +- return -EINVAL; +-} +- +-void +-nouveau_display_vblank_disable(struct drm_device *dev, int head) +-{ +- struct drm_crtc *crtc; +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- if (nv_crtc->index == head) { +- nvif_notify_put(&nv_crtc->vblank); +- return; +- } +- } +-} +- +-static inline int +-calc(int blanks, int blanke, int total, int line) +-{ +- if (blanke >= blanks) { +- if (line >= blanks) +- line -= total; +- } else { +- if (line >= blanks) +- line -= total; +- line -= blanke + 1; +- } +- return line; +-} +- +-int +-nouveau_display_scanoutpos_head(struct drm_crtc *crtc, int *vpos, int *hpos, +- ktime_t *stime, ktime_t *etime) +-{ +- struct { +- struct nv04_disp_mthd_v0 base; +- struct nv04_disp_scanoutpos_v0 scan; +- } args = { +- .base.method = NV04_DISP_SCANOUTPOS, +- .base.head = nouveau_crtc(crtc)->index, +- }; +- struct nouveau_display *disp = nouveau_display(crtc->dev); +- int ret, retry = 1; +- +- do { +- ret = nvif_mthd(&disp->disp, 0, &args, sizeof(args)); +- if (ret != 0) +- return 0; +- +- if (args.scan.vline) { +- ret |= DRM_SCANOUTPOS_ACCURATE; +- ret |= DRM_SCANOUTPOS_VALID; +- break; +- } +- +- if (retry) ndelay(crtc->linedur_ns); +- } while (retry--); +- +- *hpos = args.scan.hline; +- *vpos = calc(args.scan.vblanks, args.scan.vblanke, +- args.scan.vtotal, args.scan.vline); +- if (stime) *stime = ns_to_ktime(args.scan.time[0]); +- if (etime) *etime = ns_to_ktime(args.scan.time[1]); +- +- if (*vpos < 0) +- ret |= DRM_SCANOUTPOS_IN_VBLANK; +- return ret; +-} +- +-int +-nouveau_display_scanoutpos(struct drm_device *dev, int head, unsigned int flags, +- int *vpos, int *hpos, ktime_t *stime, ktime_t *etime) +-{ +- struct drm_crtc *crtc; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- if (nouveau_crtc(crtc)->index == head) { +- return nouveau_display_scanoutpos_head(crtc, vpos, hpos, +- stime, etime); +- } +- } +- +- return 0; +-} +- +-int +-nouveau_display_vblstamp(struct drm_device *dev, int head, int *max_error, +- struct timeval *time, unsigned flags) +-{ +- struct drm_crtc *crtc; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- if (nouveau_crtc(crtc)->index == head) { +- return drm_calc_vbltimestamp_from_scanoutpos(dev, +- head, max_error, time, flags, crtc, +- &crtc->hwmode); +- } +- } +- +- return -EINVAL; +-} +- +-static void +-nouveau_display_vblank_fini(struct drm_device *dev) +-{ +- struct drm_crtc *crtc; +- +- drm_vblank_cleanup(dev); +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- nvif_notify_fini(&nv_crtc->vblank); +- } +-} +- +-static int +-nouveau_display_vblank_init(struct drm_device *dev) +-{ +- struct nouveau_display *disp = nouveau_display(dev); +- struct drm_crtc *crtc; +- int ret; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- ret = nvif_notify_init(&disp->disp, NULL, +- nouveau_display_vblank_handler, false, +- NV04_DISP_NTFY_VBLANK, +- &(struct nvif_notify_head_req_v0) { +- .head = nv_crtc->index, +- }, +- sizeof(struct nvif_notify_head_req_v0), +- sizeof(struct nvif_notify_head_rep_v0), +- &nv_crtc->vblank); +- if (ret) { +- nouveau_display_vblank_fini(dev); +- return ret; +- } +- } +- +- ret = drm_vblank_init(dev, dev->mode_config.num_crtc); +- if (ret) { +- nouveau_display_vblank_fini(dev); +- return ret; +- } +- +- return 0; +-} +- +-static void +-nouveau_user_framebuffer_destroy(struct drm_framebuffer *drm_fb) +-{ +- struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); +- struct nouveau_display *disp = nouveau_display(drm_fb->dev); +- +- if (disp->fb_dtor) +- disp->fb_dtor(drm_fb); +- +- if (fb->nvbo) +- drm_gem_object_unreference_unlocked(&fb->nvbo->gem); +- +- drm_framebuffer_cleanup(drm_fb); +- kfree(fb); +-} +- +-static int +-nouveau_user_framebuffer_create_handle(struct drm_framebuffer *drm_fb, +- struct drm_file *file_priv, +- unsigned int *handle) +-{ +- struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb); +- +- return drm_gem_handle_create(file_priv, &fb->nvbo->gem, handle); +-} +- +-static const struct drm_framebuffer_funcs nouveau_framebuffer_funcs = { +- .destroy = nouveau_user_framebuffer_destroy, +- .create_handle = nouveau_user_framebuffer_create_handle, +-}; +- +-int +-nouveau_framebuffer_init(struct drm_device *dev, +- struct nouveau_framebuffer *nv_fb, +- struct drm_mode_fb_cmd2 *mode_cmd, +- struct nouveau_bo *nvbo) +-{ +- struct nouveau_display *disp = nouveau_display(dev); +- struct drm_framebuffer *fb = &nv_fb->base; +- int ret; +- +- drm_helper_mode_fill_fb_struct(fb, mode_cmd); +- nv_fb->nvbo = nvbo; +- +- ret = drm_framebuffer_init(dev, fb, &nouveau_framebuffer_funcs); +- if (ret) +- return ret; +- +- if (disp->fb_ctor) { +- ret = disp->fb_ctor(fb); +- if (ret) +- disp->fb_dtor(fb); +- } +- +- return ret; +-} +- +-static struct drm_framebuffer * +-nouveau_user_framebuffer_create(struct drm_device *dev, +- struct drm_file *file_priv, +- struct drm_mode_fb_cmd2 *mode_cmd) +-{ +- struct nouveau_framebuffer *nouveau_fb; +- struct drm_gem_object *gem; +- int ret = -ENOMEM; +- +- gem = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); +- if (!gem) +- return ERR_PTR(-ENOENT); +- +- nouveau_fb = kzalloc(sizeof(struct nouveau_framebuffer), GFP_KERNEL); +- if (!nouveau_fb) +- goto err_unref; +- +- ret = nouveau_framebuffer_init(dev, nouveau_fb, mode_cmd, nouveau_gem_object(gem)); +- if (ret) +- goto err; +- +- return &nouveau_fb->base; +- +-err: +- kfree(nouveau_fb); +-err_unref: +- drm_gem_object_unreference(gem); +- return ERR_PTR(ret); +-} +- +-static const struct drm_mode_config_funcs nouveau_mode_config_funcs = { +- .fb_create = nouveau_user_framebuffer_create, +- .output_poll_changed = nouveau_fbcon_output_poll_changed, +-}; +- +- +-struct nouveau_drm_prop_enum_list { +- u8 gen_mask; +- int type; +- char *name; +-}; +- +-static struct nouveau_drm_prop_enum_list underscan[] = { +- { 6, UNDERSCAN_AUTO, "auto" }, +- { 6, UNDERSCAN_OFF, "off" }, +- { 6, UNDERSCAN_ON, "on" }, +- {} +-}; +- +-static struct nouveau_drm_prop_enum_list dither_mode[] = { +- { 7, DITHERING_MODE_AUTO, "auto" }, +- { 7, DITHERING_MODE_OFF, "off" }, +- { 1, DITHERING_MODE_ON, "on" }, +- { 6, DITHERING_MODE_STATIC2X2, "static 2x2" }, +- { 6, DITHERING_MODE_DYNAMIC2X2, "dynamic 2x2" }, +- { 4, DITHERING_MODE_TEMPORAL, "temporal" }, +- {} +-}; +- +-static struct nouveau_drm_prop_enum_list dither_depth[] = { +- { 6, DITHERING_DEPTH_AUTO, "auto" }, +- { 6, DITHERING_DEPTH_6BPC, "6 bpc" }, +- { 6, DITHERING_DEPTH_8BPC, "8 bpc" }, +- {} +-}; +- +-#define PROP_ENUM(p,gen,n,list) do { \ +- struct nouveau_drm_prop_enum_list *l = (list); \ +- int c = 0; \ +- while (l->gen_mask) { \ +- if (l->gen_mask & (1 << (gen))) \ +- c++; \ +- l++; \ +- } \ +- if (c) { \ +- p = drm_property_create(dev, DRM_MODE_PROP_ENUM, n, c); \ +- l = (list); \ +- c = 0; \ +- while (p && l->gen_mask) { \ +- if (l->gen_mask & (1 << (gen))) { \ +- drm_property_add_enum(p, c, l->type, l->name); \ +- c++; \ +- } \ +- l++; \ +- } \ +- } \ +-} while(0) +- +-int +-nouveau_display_init(struct drm_device *dev) +-{ +- struct nouveau_display *disp = nouveau_display(dev); +- struct drm_connector *connector; +- int ret; +- +- ret = disp->init(dev); +- if (ret) +- return ret; +- +- /* enable polling for external displays */ +- drm_kms_helper_poll_enable(dev); +- +- /* enable hotplug interrupts */ +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- struct nouveau_connector *conn = nouveau_connector(connector); +- nvif_notify_get(&conn->hpd); +- } +- +- return ret; +-} +- +-void +-nouveau_display_fini(struct drm_device *dev) +-{ +- struct nouveau_display *disp = nouveau_display(dev); +- struct drm_connector *connector; +- int head; +- +- /* Make sure that drm and hw vblank irqs get properly disabled. */ +- for (head = 0; head < dev->mode_config.num_crtc; head++) +- drm_vblank_off(dev, head); +- +- /* disable hotplug interrupts */ +- list_for_each_entry(connector, &dev->mode_config.connector_list, head) { +- struct nouveau_connector *conn = nouveau_connector(connector); +- nvif_notify_put(&conn->hpd); +- } +- +- drm_kms_helper_poll_disable(dev); +- disp->fini(dev); +-} +- +-static void +-nouveau_display_create_properties(struct drm_device *dev) +-{ +- struct nouveau_display *disp = nouveau_display(dev); +- int gen; +- +- if (disp->disp.oclass < NV50_DISP) +- gen = 0; +- else +- if (disp->disp.oclass < GF110_DISP) +- gen = 1; +- else +- gen = 2; +- +- PROP_ENUM(disp->dithering_mode, gen, "dithering mode", dither_mode); +- PROP_ENUM(disp->dithering_depth, gen, "dithering depth", dither_depth); +- PROP_ENUM(disp->underscan_property, gen, "underscan", underscan); +- +- disp->underscan_hborder_property = +- drm_property_create_range(dev, 0, "underscan hborder", 0, 128); +- +- disp->underscan_vborder_property = +- drm_property_create_range(dev, 0, "underscan vborder", 0, 128); +- +- if (gen < 1) +- return; +- +- /* -90..+90 */ +- disp->vibrant_hue_property = +- drm_property_create_range(dev, 0, "vibrant hue", 0, 180); +- +- /* -100..+100 */ +- disp->color_vibrance_property = +- drm_property_create_range(dev, 0, "color vibrance", 0, 200); +-} +- +-int +-nouveau_display_create(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_display *disp; +- int ret; +- +- disp = drm->display = kzalloc(sizeof(*disp), GFP_KERNEL); +- if (!disp) +- return -ENOMEM; +- +- drm_mode_config_init(dev); +- drm_mode_create_scaling_mode_property(dev); +- drm_mode_create_dvi_i_properties(dev); +- +- dev->mode_config.funcs = &nouveau_mode_config_funcs; +- dev->mode_config.fb_base = nv_device_resource_start(nvkm_device(&drm->device), 1); +- +- dev->mode_config.min_width = 0; +- dev->mode_config.min_height = 0; +- if (drm->device.info.family < NV_DEVICE_INFO_V0_CELSIUS) { +- dev->mode_config.max_width = 2048; +- dev->mode_config.max_height = 2048; +- } else +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { +- dev->mode_config.max_width = 4096; +- dev->mode_config.max_height = 4096; +- } else { +- dev->mode_config.max_width = 8192; +- dev->mode_config.max_height = 8192; +- } +- +- dev->mode_config.preferred_depth = 24; +- dev->mode_config.prefer_shadow = 1; +- +- if (drm->device.info.chipset < 0x11) +- dev->mode_config.async_page_flip = false; +- else +- dev->mode_config.async_page_flip = true; +- +- drm_kms_helper_poll_init(dev); +- drm_kms_helper_poll_disable(dev); +- +- if (nouveau_modeset != 2 && drm->vbios.dcb.entries) { +- static const u16 oclass[] = { +- GM107_DISP, +- GK110_DISP, +- GK104_DISP, +- GF110_DISP, +- GT214_DISP, +- GT206_DISP, +- GT200_DISP, +- G82_DISP, +- NV50_DISP, +- NV04_DISP, +- }; +- int i; +- +- for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { +- ret = nvif_object_init(nvif_object(&drm->device), NULL, +- NVDRM_DISPLAY, oclass[i], +- NULL, 0, &disp->disp); +- } +- +- if (ret == 0) { +- nouveau_display_create_properties(dev); +- if (disp->disp.oclass < NV50_DISP) +- ret = nv04_display_create(dev); +- else +- ret = nv50_display_create(dev); +- } +- } else { +- ret = 0; +- } +- +- if (ret) +- goto disp_create_err; +- +- if (dev->mode_config.num_crtc) { +- ret = nouveau_display_vblank_init(dev); +- if (ret) +- goto vblank_err; +- } +- +- nouveau_backlight_init(dev); +- return 0; +- +-vblank_err: +- disp->dtor(dev); +-disp_create_err: +- drm_kms_helper_poll_fini(dev); +- drm_mode_config_cleanup(dev); +- return ret; +-} +- +-void +-nouveau_display_destroy(struct drm_device *dev) +-{ +- struct nouveau_display *disp = nouveau_display(dev); +- +- nouveau_backlight_exit(dev); +- nouveau_display_vblank_fini(dev); +- +- drm_kms_helper_poll_fini(dev); +- drm_mode_config_cleanup(dev); +- +- if (disp->dtor) +- disp->dtor(dev); +- +- nvif_object_fini(&disp->disp); +- +- nouveau_drm(dev)->display = NULL; +- kfree(disp); +-} +- +-int +-nouveau_display_suspend(struct drm_device *dev, bool runtime) +-{ +- struct drm_crtc *crtc; +- +- nouveau_display_fini(dev); +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_framebuffer *nouveau_fb; +- +- nouveau_fb = nouveau_framebuffer(crtc->primary->fb); +- if (!nouveau_fb || !nouveau_fb->nvbo) +- continue; +- +- nouveau_bo_unpin(nouveau_fb->nvbo); +- } +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- nouveau_bo_unmap(nv_crtc->cursor.nvbo); +- nouveau_bo_unpin(nv_crtc->cursor.nvbo); +- } +- +- return 0; +-} +- +-void +-nouveau_display_resume(struct drm_device *dev, bool runtime) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_crtc *crtc; +- int ret, head; +- +- /* re-pin fb/cursors */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_framebuffer *nouveau_fb; +- +- nouveau_fb = nouveau_framebuffer(crtc->primary->fb); +- if (!nouveau_fb || !nouveau_fb->nvbo) +- continue; +- +- ret = nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM); +- if (ret) +- NV_ERROR(drm, "Could not pin framebuffer\n"); +- } +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); +- if (!ret) +- ret = nouveau_bo_map(nv_crtc->cursor.nvbo); +- if (ret) +- NV_ERROR(drm, "Could not pin/map cursor.\n"); +- } +- +- nouveau_display_init(dev); +- +- /* Force CLUT to get re-loaded during modeset */ +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- nv_crtc->lut.depth = 0; +- } +- +- /* Make sure that drm and hw vblank irqs get resumed if needed. */ +- for (head = 0; head < dev->mode_config.num_crtc; head++) +- drm_vblank_on(dev, head); +- +- /* This should ensure we don't hit a locking problem when someone +- * wakes us up via a connector. We should never go into suspend +- * while the display is on anyways. +- */ +- if (runtime) +- return; +- +- drm_helper_resume_force_mode(dev); +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- u32 offset = nv_crtc->cursor.nvbo->bo.offset; +- +- nv_crtc->cursor.set_offset(nv_crtc, offset); +- nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, +- nv_crtc->cursor_saved_y); +- } +-} +- +-static int +-nouveau_page_flip_emit(struct nouveau_channel *chan, +- struct nouveau_bo *old_bo, +- struct nouveau_bo *new_bo, +- struct nouveau_page_flip_state *s, +- struct nouveau_fence **pfence) +-{ +- struct nouveau_fence_chan *fctx = chan->fence; +- struct nouveau_drm *drm = chan->drm; +- struct drm_device *dev = drm->dev; +- unsigned long flags; +- int ret; +- +- /* Queue it to the pending list */ +- spin_lock_irqsave(&dev->event_lock, flags); +- list_add_tail(&s->head, &fctx->flip); +- spin_unlock_irqrestore(&dev->event_lock, flags); +- +- /* Synchronize with the old framebuffer */ +- ret = nouveau_fence_sync(old_bo, chan, false, false); +- if (ret) +- goto fail; +- +- /* Emit the pageflip */ +- ret = RING_SPACE(chan, 2); +- if (ret) +- goto fail; +- +- if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI) +- BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); +- else +- BEGIN_NVC0(chan, FermiSw, NV_SW_PAGE_FLIP, 1); +- OUT_RING (chan, 0x00000000); +- FIRE_RING (chan); +- +- ret = nouveau_fence_new(chan, false, pfence); +- if (ret) +- goto fail; +- +- return 0; +-fail: +- spin_lock_irqsave(&dev->event_lock, flags); +- list_del(&s->head); +- spin_unlock_irqrestore(&dev->event_lock, flags); +- return ret; +-} +- +-int +-nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, +- struct drm_pending_vblank_event *event, u32 flags) +-{ +- const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; +- struct drm_device *dev = crtc->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo; +- struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; +- struct nouveau_page_flip_state *s; +- struct nouveau_channel *chan; +- struct nouveau_cli *cli; +- struct nouveau_fence *fence; +- int ret; +- +- chan = drm->channel; +- if (!chan) +- return -ENODEV; +- cli = (void *)nvif_client(&chan->device->base); +- +- s = kzalloc(sizeof(*s), GFP_KERNEL); +- if (!s) +- return -ENOMEM; +- +- if (new_bo != old_bo) { +- ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM); +- if (ret) +- goto fail_free; +- } +- +- mutex_lock(&cli->mutex); +- ret = ttm_bo_reserve(&new_bo->bo, true, false, false, NULL); +- if (ret) +- goto fail_unpin; +- +- /* synchronise rendering channel with the kernel's channel */ +- ret = nouveau_fence_sync(new_bo, chan, false, true); +- if (ret) { +- ttm_bo_unreserve(&new_bo->bo); +- goto fail_unpin; +- } +- +- if (new_bo != old_bo) { +- ttm_bo_unreserve(&new_bo->bo); +- +- ret = ttm_bo_reserve(&old_bo->bo, true, false, false, NULL); +- if (ret) +- goto fail_unpin; +- } +- +- /* Initialize a page flip struct */ +- *s = (struct nouveau_page_flip_state) +- { { }, event, nouveau_crtc(crtc)->index, +- fb->bits_per_pixel, fb->pitches[0], crtc->x, crtc->y, +- new_bo->bo.offset }; +- +- /* Keep vblanks on during flip, for the target crtc of this flip */ +- drm_vblank_get(dev, nouveau_crtc(crtc)->index); +- +- /* Emit a page flip */ +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nv50_display_flip_next(crtc, fb, chan, swap_interval); +- if (ret) +- goto fail_unreserve; +- } else { +- struct nv04_display *dispnv04 = nv04_display(dev); +- int head = nouveau_crtc(crtc)->index; +- +- if (swap_interval) { +- ret = RING_SPACE(chan, 8); +- if (ret) +- goto fail_unreserve; +- +- BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); +- OUT_RING (chan, 0); +- BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); +- OUT_RING (chan, head); +- BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); +- OUT_RING (chan, 0); +- BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); +- OUT_RING (chan, 0); +- } +- +- nouveau_bo_ref(new_bo, &dispnv04->image[head]); +- } +- +- ret = nouveau_page_flip_emit(chan, old_bo, new_bo, s, &fence); +- if (ret) +- goto fail_unreserve; +- mutex_unlock(&cli->mutex); +- +- /* Update the crtc struct and cleanup */ +- crtc->primary->fb = fb; +- +- nouveau_bo_fence(old_bo, fence, false); +- ttm_bo_unreserve(&old_bo->bo); +- if (old_bo != new_bo) +- nouveau_bo_unpin(old_bo); +- nouveau_fence_unref(&fence); +- return 0; +- +-fail_unreserve: +- drm_vblank_put(dev, nouveau_crtc(crtc)->index); +- ttm_bo_unreserve(&old_bo->bo); +-fail_unpin: +- mutex_unlock(&cli->mutex); +- if (old_bo != new_bo) +- nouveau_bo_unpin(new_bo); +-fail_free: +- kfree(s); +- return ret; +-} +- +-int +-nouveau_finish_page_flip(struct nouveau_channel *chan, +- struct nouveau_page_flip_state *ps) +-{ +- struct nouveau_fence_chan *fctx = chan->fence; +- struct nouveau_drm *drm = chan->drm; +- struct drm_device *dev = drm->dev; +- struct nouveau_page_flip_state *s; +- unsigned long flags; +- int crtcid = -1; +- +- spin_lock_irqsave(&dev->event_lock, flags); +- +- if (list_empty(&fctx->flip)) { +- NV_ERROR(drm, "unexpected pageflip\n"); +- spin_unlock_irqrestore(&dev->event_lock, flags); +- return -EINVAL; +- } +- +- s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head); +- if (s->event) { +- /* Vblank timestamps/counts are only correct on >= NV-50 */ +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) +- crtcid = s->crtc; +- +- drm_send_vblank_event(dev, crtcid, s->event); +- } +- +- /* Give up ownership of vblank for page-flipped crtc */ +- drm_vblank_put(dev, s->crtc); +- +- list_del(&s->head); +- if (ps) +- *ps = *s; +- kfree(s); +- +- spin_unlock_irqrestore(&dev->event_lock, flags); +- return 0; +-} +- +-int +-nouveau_flip_complete(void *data) +-{ +- struct nouveau_channel *chan = data; +- struct nouveau_drm *drm = chan->drm; +- struct nouveau_page_flip_state state; +- +- if (!nouveau_finish_page_flip(chan, &state)) { +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { +- nv_set_crtc_base(drm->dev, state.crtc, state.offset + +- state.y * state.pitch + +- state.x * state.bpp / 8); +- } +- } +- +- return 0; +-} +- +-int +-nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev, +- struct drm_mode_create_dumb *args) +-{ +- struct nouveau_bo *bo; +- int ret; +- +- args->pitch = roundup(args->width * (args->bpp / 8), 256); +- args->size = args->pitch * args->height; +- args->size = roundup(args->size, PAGE_SIZE); +- +- ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo); +- if (ret) +- return ret; +- +- ret = drm_gem_handle_create(file_priv, &bo->gem, &args->handle); +- drm_gem_object_unreference_unlocked(&bo->gem); +- return ret; +-} +- +-int +-nouveau_display_dumb_map_offset(struct drm_file *file_priv, +- struct drm_device *dev, +- uint32_t handle, uint64_t *poffset) +-{ +- struct drm_gem_object *gem; +- +- gem = drm_gem_object_lookup(dev, file_priv, handle); +- if (gem) { +- struct nouveau_bo *bo = nouveau_gem_object(gem); +- *poffset = drm_vma_node_offset_addr(&bo->bo.vma_node); +- drm_gem_object_unreference_unlocked(gem); +- return 0; +- } +- +- return -ENOENT; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h +deleted file mode 100644 +index be3d5947..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_display.h ++++ /dev/null +@@ -1,104 +0,0 @@ +-#ifndef __NOUVEAU_DISPLAY_H__ +-#define __NOUVEAU_DISPLAY_H__ +- +-#include +- +-#include "nouveau_drm.h" +- +-struct nouveau_framebuffer { +- struct drm_framebuffer base; +- struct nouveau_bo *nvbo; +- struct nouveau_vma vma; +- u32 r_handle; +- u32 r_format; +- u32 r_pitch; +- struct nvif_object h_base[4]; +- struct nvif_object h_core; +-}; +- +-static inline struct nouveau_framebuffer * +-nouveau_framebuffer(struct drm_framebuffer *fb) +-{ +- return container_of(fb, struct nouveau_framebuffer, base); +-} +- +-int nouveau_framebuffer_init(struct drm_device *, struct nouveau_framebuffer *, +- struct drm_mode_fb_cmd2 *, struct nouveau_bo *); +- +-struct nouveau_page_flip_state { +- struct list_head head; +- struct drm_pending_vblank_event *event; +- int crtc, bpp, pitch, x, y; +- u64 offset; +-}; +- +-struct nouveau_display { +- void *priv; +- void (*dtor)(struct drm_device *); +- int (*init)(struct drm_device *); +- void (*fini)(struct drm_device *); +- +- int (*fb_ctor)(struct drm_framebuffer *); +- void (*fb_dtor)(struct drm_framebuffer *); +- +- struct nvif_object disp; +- +- struct drm_property *dithering_mode; +- struct drm_property *dithering_depth; +- struct drm_property *underscan_property; +- struct drm_property *underscan_hborder_property; +- struct drm_property *underscan_vborder_property; +- /* not really hue and saturation: */ +- struct drm_property *vibrant_hue_property; +- struct drm_property *color_vibrance_property; +-}; +- +-static inline struct nouveau_display * +-nouveau_display(struct drm_device *dev) +-{ +- return nouveau_drm(dev)->display; +-} +- +-int nouveau_display_create(struct drm_device *dev); +-void nouveau_display_destroy(struct drm_device *dev); +-int nouveau_display_init(struct drm_device *dev); +-void nouveau_display_fini(struct drm_device *dev); +-int nouveau_display_suspend(struct drm_device *dev, bool runtime); +-void nouveau_display_resume(struct drm_device *dev, bool runtime); +-int nouveau_display_vblank_enable(struct drm_device *, int); +-void nouveau_display_vblank_disable(struct drm_device *, int); +-int nouveau_display_scanoutpos(struct drm_device *, int, unsigned int, +- int *, int *, ktime_t *, ktime_t *); +-int nouveau_display_vblstamp(struct drm_device *, int, int *, +- struct timeval *, unsigned); +- +-int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, +- struct drm_pending_vblank_event *event, +- uint32_t page_flip_flags); +-int nouveau_finish_page_flip(struct nouveau_channel *, +- struct nouveau_page_flip_state *); +- +-int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, +- struct drm_mode_create_dumb *args); +-int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, +- u32 handle, u64 *offset); +- +-void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); +- +-int nouveau_crtc_set_config(struct drm_mode_set *set); +-#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT +-extern int nouveau_backlight_init(struct drm_device *); +-extern void nouveau_backlight_exit(struct drm_device *); +-#else +-static inline int +-nouveau_backlight_init(struct drm_device *dev) +-{ +- return 0; +-} +- +-static inline void +-nouveau_backlight_exit(struct drm_device *dev) { +-} +-#endif +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c +deleted file mode 100644 +index 8508603c..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_dma.c ++++ /dev/null +@@ -1,261 +0,0 @@ +-/* +- * Copyright (C) 2007 Ben Skeggs. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +- +-void +-OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords) +-{ +- bool is_iomem; +- u32 *mem = ttm_kmap_obj_virtual(&chan->push.buffer->kmap, &is_iomem); +- mem = &mem[chan->dma.cur]; +- if (is_iomem) +- memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4); +- else +- memcpy(mem, data, nr_dwords * 4); +- chan->dma.cur += nr_dwords; +-} +- +-/* Fetch and adjust GPU GET pointer +- * +- * Returns: +- * value >= 0, the adjusted GET pointer +- * -EINVAL if GET pointer currently outside main push buffer +- * -EBUSY if timeout exceeded +- */ +-static inline int +-READ_GET(struct nouveau_channel *chan, uint64_t *prev_get, int *timeout) +-{ +- uint64_t val; +- +- val = nvif_rd32(chan, chan->user_get); +- if (chan->user_get_hi) +- val |= (uint64_t)nvif_rd32(chan, chan->user_get_hi) << 32; +- +- /* reset counter as long as GET is still advancing, this is +- * to avoid misdetecting a GPU lockup if the GPU happens to +- * just be processing an operation that takes a long time +- */ +- if (val != *prev_get) { +- *prev_get = val; +- *timeout = 0; +- } +- +- if ((++*timeout & 0xff) == 0) { +- udelay(1); +- if (*timeout > 100000) +- return -EBUSY; +- } +- +- if (val < chan->push.vma.offset || +- val > chan->push.vma.offset + (chan->dma.max << 2)) +- return -EINVAL; +- +- return (val - chan->push.vma.offset) >> 2; +-} +- +-void +-nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo, +- int delta, int length) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); +- struct nouveau_bo *pb = chan->push.buffer; +- struct nouveau_vma *vma; +- int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base; +- u64 offset; +- +- vma = nouveau_bo_vma_find(bo, cli->vm); +- BUG_ON(!vma); +- offset = vma->offset + delta; +- +- BUG_ON(chan->dma.ib_free < 1); +- +- nouveau_bo_wr32(pb, ip++, lower_32_bits(offset)); +- nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8); +- +- chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max; +- +- mb(); +- /* Flush writes. */ +- nouveau_bo_rd32(pb, 0); +- +- nvif_wr32(chan, 0x8c, chan->dma.ib_put); +- chan->dma.ib_free--; +-} +- +-static int +-nv50_dma_push_wait(struct nouveau_channel *chan, int count) +-{ +- uint32_t cnt = 0, prev_get = 0; +- +- while (chan->dma.ib_free < count) { +- uint32_t get = nvif_rd32(chan, 0x88); +- if (get != prev_get) { +- prev_get = get; +- cnt = 0; +- } +- +- if ((++cnt & 0xff) == 0) { +- DRM_UDELAY(1); +- if (cnt > 100000) +- return -EBUSY; +- } +- +- chan->dma.ib_free = get - chan->dma.ib_put; +- if (chan->dma.ib_free <= 0) +- chan->dma.ib_free += chan->dma.ib_max; +- } +- +- return 0; +-} +- +-static int +-nv50_dma_wait(struct nouveau_channel *chan, int slots, int count) +-{ +- uint64_t prev_get = 0; +- int ret, cnt = 0; +- +- ret = nv50_dma_push_wait(chan, slots + 1); +- if (unlikely(ret)) +- return ret; +- +- while (chan->dma.free < count) { +- int get = READ_GET(chan, &prev_get, &cnt); +- if (unlikely(get < 0)) { +- if (get == -EINVAL) +- continue; +- +- return get; +- } +- +- if (get <= chan->dma.cur) { +- chan->dma.free = chan->dma.max - chan->dma.cur; +- if (chan->dma.free >= count) +- break; +- +- FIRE_RING(chan); +- do { +- get = READ_GET(chan, &prev_get, &cnt); +- if (unlikely(get < 0)) { +- if (get == -EINVAL) +- continue; +- return get; +- } +- } while (get == 0); +- chan->dma.cur = 0; +- chan->dma.put = 0; +- } +- +- chan->dma.free = get - chan->dma.cur - 1; +- } +- +- return 0; +-} +- +-int +-nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size) +-{ +- uint64_t prev_get = 0; +- int cnt = 0, get; +- +- if (chan->dma.ib_max) +- return nv50_dma_wait(chan, slots, size); +- +- while (chan->dma.free < size) { +- get = READ_GET(chan, &prev_get, &cnt); +- if (unlikely(get == -EBUSY)) +- return -EBUSY; +- +- /* loop until we have a usable GET pointer. the value +- * we read from the GPU may be outside the main ring if +- * PFIFO is processing a buffer called from the main ring, +- * discard these values until something sensible is seen. +- * +- * the other case we discard GET is while the GPU is fetching +- * from the SKIPS area, so the code below doesn't have to deal +- * with some fun corner cases. +- */ +- if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS) +- continue; +- +- if (get <= chan->dma.cur) { +- /* engine is fetching behind us, or is completely +- * idle (GET == PUT) so we have free space up until +- * the end of the push buffer +- * +- * we can only hit that path once per call due to +- * looping back to the beginning of the push buffer, +- * we'll hit the fetching-ahead-of-us path from that +- * point on. +- * +- * the *one* exception to that rule is if we read +- * GET==PUT, in which case the below conditional will +- * always succeed and break us out of the wait loop. +- */ +- chan->dma.free = chan->dma.max - chan->dma.cur; +- if (chan->dma.free >= size) +- break; +- +- /* not enough space left at the end of the push buffer, +- * instruct the GPU to jump back to the start right +- * after processing the currently pending commands. +- */ +- OUT_RING(chan, chan->push.vma.offset | 0x20000000); +- +- /* wait for GET to depart from the skips area. +- * prevents writing GET==PUT and causing a race +- * condition that causes us to think the GPU is +- * idle when it's not. +- */ +- do { +- get = READ_GET(chan, &prev_get, &cnt); +- if (unlikely(get == -EBUSY)) +- return -EBUSY; +- if (unlikely(get == -EINVAL)) +- continue; +- } while (get <= NOUVEAU_DMA_SKIPS); +- WRITE_PUT(NOUVEAU_DMA_SKIPS); +- +- /* we're now submitting commands at the start of +- * the push buffer. +- */ +- chan->dma.cur = +- chan->dma.put = NOUVEAU_DMA_SKIPS; +- } +- +- /* engine fetching ahead of us, we have space up until the +- * current GET pointer. the "- 1" is to ensure there's +- * space left to emit a jump back to the beginning of the +- * push buffer if we require it. we can never get GET == PUT +- * here, so this is safe. +- */ +- chan->dma.free = get - chan->dma.cur - 1; +- } +- +- return 0; +-} +- +diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h +deleted file mode 100644 +index 8da0a272..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_dma.h ++++ /dev/null +@@ -1,195 +0,0 @@ +-/* +- * Copyright (C) 2007 Ben Skeggs. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NOUVEAU_DMA_H__ +-#define __NOUVEAU_DMA_H__ +- +-#include "nouveau_bo.h" +-#include "nouveau_chan.h" +- +-int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); +-void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *, +- int delta, int length); +- +-/* +- * There's a hw race condition where you can't jump to your PUT offset, +- * to avoid this we jump to offset + SKIPS and fill the difference with +- * NOPs. +- * +- * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses +- * a SKIPS value of 8. Lets assume that the race condition is to do +- * with writing into the fetch area, we configure a fetch size of 128 +- * bytes so we need a larger SKIPS value. +- */ +-#define NOUVEAU_DMA_SKIPS (128 / 4) +- +-/* Hardcoded object assignments to subchannels (subchannel id). */ +-enum { +- NvSubCtxSurf2D = 0, +- NvSubSw = 1, +- NvSubImageBlit = 2, +- NvSubGdiRect = 3, +- +- NvSub2D = 3, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ +- NvSubCopy = 4, /* DO NOT CHANGE - hardcoded for kepler gr fifo */ +- FermiSw = 5, /* DO NOT CHANGE (well.. 6/7 will work...) */ +-}; +- +-/* Object handles - for stuff that's doesn't use handle == oclass. */ +-enum { +- NvDmaFB = 0x80000002, +- NvDmaTT = 0x80000003, +- NvNotify0 = 0x80000006, +- NvSema = 0x8000000f, +- NvEvoSema0 = 0x80000010, +- NvEvoSema1 = 0x80000011, +-}; +- +-#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039 +-#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000 +-#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050 +-#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100 +-#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 +-#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000 +-#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001 +-#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180 +-#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184 +-#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c +- +-#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039 +-#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200 +-#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c +-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238 +-#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c +- +-static __must_check inline int +-RING_SPACE(struct nouveau_channel *chan, int size) +-{ +- int ret; +- +- ret = nouveau_dma_wait(chan, 1, size); +- if (ret) +- return ret; +- +- chan->dma.free -= size; +- return 0; +-} +- +-static inline void +-OUT_RING(struct nouveau_channel *chan, int data) +-{ +- nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data); +-} +- +-extern void +-OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords); +- +-static inline void +-BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size) +-{ +- OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd); +-} +- +-static inline void +-BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size) +-{ +- OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd); +-} +- +-static inline void +-BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size) +-{ +- OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2)); +-} +- +-static inline void +-BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size) +-{ +- OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2)); +-} +- +-static inline void +-BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data) +-{ +- OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2)); +-} +- +-#define WRITE_PUT(val) do { \ +- mb(); \ +- nouveau_bo_rd32(chan->push.buffer, 0); \ +- nvif_wr32(chan, chan->user_put, ((val) << 2) + chan->push.vma.offset); \ +-} while (0) +- +-static inline void +-FIRE_RING(struct nouveau_channel *chan) +-{ +- if (chan->dma.cur == chan->dma.put) +- return; +- chan->accel_done = true; +- +- if (chan->dma.ib_max) { +- nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2, +- (chan->dma.cur - chan->dma.put) << 2); +- } else { +- WRITE_PUT(chan->dma.cur); +- } +- +- chan->dma.put = chan->dma.cur; +-} +- +-static inline void +-WIND_RING(struct nouveau_channel *chan) +-{ +- chan->dma.cur = chan->dma.put; +-} +- +-/* FIFO methods */ +-#define NV01_SUBCHAN_OBJECT 0x00000000 +-#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 +-#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 +-#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 +-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c +-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 +-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 +-#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 +-#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 +-#define NV84_SUBCHAN_UEVENT 0x00000020 +-#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 +-#define NV10_SUBCHAN_REF_CNT 0x00000050 +-#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 +-#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 +-#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 +-#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c +-#define NV40_SUBCHAN_YIELD 0x00000080 +- +-/* NV_SW object class */ +-#define NV_SW_DMA_VBLSEM 0x0000018c +-#define NV_SW_VBLSEM_OFFSET 0x00000400 +-#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 +-#define NV_SW_VBLSEM_RELEASE 0x00000408 +-#define NV_SW_PAGE_FLIP 0x00000500 +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c +deleted file mode 100644 +index c5137ccc..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_dp.c ++++ /dev/null +@@ -1,89 +0,0 @@ +-/* +- * Copyright 2009 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_connector.h" +-#include "nouveau_encoder.h" +-#include "nouveau_crtc.h" +- +-static void +-nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch, +- u8 *dpcd) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- u8 buf[3]; +- +- if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) +- return; +- +- if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3)) +- NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n", +- buf[0], buf[1], buf[2]); +- +- if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3)) +- NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n", +- buf[0], buf[1], buf[2]); +- +-} +- +-int +-nouveau_dp_detect(struct nouveau_encoder *nv_encoder) +-{ +- struct drm_device *dev = nv_encoder->base.base.dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_i2c_port *auxch; +- u8 *dpcd = nv_encoder->dp.dpcd; +- int ret; +- +- auxch = nv_encoder->i2c; +- if (!auxch) +- return -ENODEV; +- +- ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8); +- if (ret) +- return ret; +- +- nv_encoder->dp.link_bw = 27000 * dpcd[1]; +- nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK; +- +- NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n", +- nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]); +- NV_DEBUG(drm, "encoder: %dx%d\n", +- nv_encoder->dcb->dpconf.link_nr, +- nv_encoder->dcb->dpconf.link_bw); +- +- if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr) +- nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr; +- if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw) +- nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw; +- +- NV_DEBUG(drm, "maximum: %dx%d\n", +- nv_encoder->dp.link_nr, nv_encoder->dp.link_bw); +- +- nouveau_dp_probe_oui(dev, auxch, dpcd); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c +deleted file mode 100644 +index 62b97c4e..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_drm.c ++++ /dev/null +@@ -1,1122 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#include "drmP.h" +-#include "drm_crtc_helper.h" +- +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_ttm.h" +-#include "nouveau_gem.h" +-#include "nouveau_agp.h" +-#include "nouveau_vga.h" +-#include "nouveau_sysfs.h" +-#include "nouveau_hwmon.h" +-#include "nouveau_acpi.h" +-#include "nouveau_bios.h" +-#include "nouveau_ioctl.h" +-#include "nouveau_abi16.h" +-#include "nouveau_fbcon.h" +-#include "nouveau_fence.h" +-#include "nouveau_debugfs.h" +-#include "nouveau_usif.h" +-#include "nouveau_connector.h" +- +-MODULE_PARM_DESC(config, "option string to pass to driver core"); +-static char *nouveau_config; +-module_param_named(config, nouveau_config, charp, 0400); +- +-MODULE_PARM_DESC(debug, "debug string to pass to driver core"); +-static char *nouveau_debug; +-module_param_named(debug, nouveau_debug, charp, 0400); +- +-MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration"); +-static int nouveau_noaccel = 0; +-module_param_named(noaccel, nouveau_noaccel, int, 0400); +- +-MODULE_PARM_DESC(modeset, "enable driver (default: auto, " +- "0 = disabled, 1 = enabled, 2 = headless)"); +-int nouveau_modeset = -1; +-module_param_named(modeset, nouveau_modeset, int, 0400); +- +-MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)"); +-int nouveau_runtime_pm = -1; +-module_param_named(runpm, nouveau_runtime_pm, int, 0400); +- +-static struct drm_driver driver_stub; +-static struct drm_driver driver_pci; +-static struct drm_driver driver_platform; +- +-static u64 +-nouveau_pci_name(struct pci_dev *pdev) +-{ +- u64 name = (u64)pci_domain_nr(pdev->bus) << 32; +- name |= pdev->bus->number << 16; +- name |= PCI_SLOT(pdev->devfn) << 8; +- return name | PCI_FUNC(pdev->devfn); +-} +- +-static u64 +-nouveau_platform_name(struct platform_device *platformdev) +-{ +- return platformdev->id; +-} +- +-static u64 +-nouveau_name(struct drm_device *dev) +-{ +- if (dev->pdev) +- return nouveau_pci_name(dev->pdev); +- else +- return nouveau_platform_name(dev->platformdev); +-} +- +-static int +-nouveau_cli_create(u64 name, const char *sname, +- int size, void **pcli) +-{ +- struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL); +- if (cli) { +- int ret = nvif_client_init(NULL, NULL, sname, name, +- nouveau_config, nouveau_debug, +- &cli->base); +- if (ret == 0) { +- mutex_init(&cli->mutex); +- usif_client_init(cli); +- } +- return ret; +- } +- return -ENOMEM; +-} +- +-static void +-nouveau_cli_destroy(struct nouveau_cli *cli) +-{ +- nouveau_vm_ref(NULL, &nvkm_client(&cli->base)->vm, NULL); +- nvif_client_fini(&cli->base); +- usif_client_fini(cli); +-} +- +-static void +-nouveau_accel_fini(struct nouveau_drm *drm) +-{ +- nouveau_channel_del(&drm->channel); +- nvif_object_fini(&drm->ntfy); +- nouveau_gpuobj_ref(NULL, &drm->notify); +- nvif_object_fini(&drm->nvsw); +- nouveau_channel_del(&drm->cechan); +- nvif_object_fini(&drm->ttm.copy); +- if (drm->fence) +- nouveau_fence(drm)->dtor(drm); +-} +- +-static void +-nouveau_accel_init(struct nouveau_drm *drm) +-{ +- struct nvif_device *device = &drm->device; +- u32 arg0, arg1; +- u32 sclass[16]; +- int ret, i; +- +- if (nouveau_noaccel) +- return; +- +- /* initialise synchronisation routines */ +- /*XXX: this is crap, but the fence/channel stuff is a little +- * backwards in some places. this will be fixed. +- */ +- ret = nvif_object_sclass(&device->base, sclass, ARRAY_SIZE(sclass)); +- if (ret < 0) +- return; +- +- for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) { +- switch (sclass[i]) { +- case NV03_CHANNEL_DMA: +- ret = nv04_fence_create(drm); +- break; +- case NV10_CHANNEL_DMA: +- ret = nv10_fence_create(drm); +- break; +- case NV17_CHANNEL_DMA: +- case NV40_CHANNEL_DMA: +- ret = nv17_fence_create(drm); +- break; +- case NV50_CHANNEL_GPFIFO: +- ret = nv50_fence_create(drm); +- break; +- case G82_CHANNEL_GPFIFO: +- ret = nv84_fence_create(drm); +- break; +- case FERMI_CHANNEL_GPFIFO: +- case KEPLER_CHANNEL_GPFIFO_A: +- ret = nvc0_fence_create(drm); +- break; +- default: +- break; +- } +- } +- +- if (ret) { +- NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret); +- nouveau_accel_fini(drm); +- return; +- } +- +- if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { +- ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, +- KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0| +- KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1, +- 0, &drm->cechan); +- if (ret) +- NV_ERROR(drm, "failed to create ce channel, %d\n", ret); +- +- arg0 = KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR; +- arg1 = 1; +- } else +- if (device->info.chipset >= 0xa3 && +- device->info.chipset != 0xaa && +- device->info.chipset != 0xac) { +- ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, +- NvDmaFB, NvDmaTT, &drm->cechan); +- if (ret) +- NV_ERROR(drm, "failed to create ce channel, %d\n", ret); +- +- arg0 = NvDmaFB; +- arg1 = NvDmaTT; +- } else { +- arg0 = NvDmaFB; +- arg1 = NvDmaTT; +- } +- +- ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1, +- &drm->channel); +- if (ret) { +- NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); +- nouveau_accel_fini(drm); +- return; +- } +- +- ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW, +- nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw); +- if (ret == 0) { +- struct nouveau_software_chan *swch; +- ret = RING_SPACE(drm->channel, 2); +- if (ret == 0) { +- if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { +- BEGIN_NV04(drm->channel, NvSubSw, 0, 1); +- OUT_RING (drm->channel, NVDRM_NVSW); +- } else +- if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) { +- BEGIN_NVC0(drm->channel, FermiSw, 0, 1); +- OUT_RING (drm->channel, 0x001f0000); +- } +- } +- swch = (void *)nvkm_object(&drm->nvsw)->parent; +- swch->flip = nouveau_flip_complete; +- swch->flip_data = drm->channel; +- } +- +- if (ret) { +- NV_ERROR(drm, "failed to allocate software object, %d\n", ret); +- nouveau_accel_fini(drm); +- return; +- } +- +- if (device->info.family < NV_DEVICE_INFO_V0_FERMI) { +- ret = nouveau_gpuobj_new(nvkm_object(&drm->device), NULL, 32, +- 0, 0, &drm->notify); +- if (ret) { +- NV_ERROR(drm, "failed to allocate notifier, %d\n", ret); +- nouveau_accel_fini(drm); +- return; +- } +- +- ret = nvif_object_init(drm->channel->object, NULL, NvNotify0, +- NV_DMA_IN_MEMORY, +- &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_VRAM, +- .access = NV_DMA_V0_ACCESS_RDWR, +- .start = drm->notify->addr, +- .limit = drm->notify->addr + 31 +- }, sizeof(struct nv_dma_v0), +- &drm->ntfy); +- if (ret) { +- nouveau_accel_fini(drm); +- return; +- } +- } +- +- +- nouveau_bo_move_init(drm); +-} +- +-static int nouveau_drm_probe(struct pci_dev *pdev, +- const struct pci_device_id *pent) +-{ +- struct nouveau_device *device; +- struct apertures_struct *aper; +- bool boot = false; +- int ret; +- +- /* remove conflicting drivers (vesafb, efifb etc) */ +- aper = alloc_apertures(3); +- if (!aper) +- return -ENOMEM; +- +- aper->ranges[0].base = pci_resource_start(pdev, 1); +- aper->ranges[0].size = pci_resource_len(pdev, 1); +- aper->count = 1; +- +- if (pci_resource_len(pdev, 2)) { +- aper->ranges[aper->count].base = pci_resource_start(pdev, 2); +- aper->ranges[aper->count].size = pci_resource_len(pdev, 2); +- aper->count++; +- } +- +- if (pci_resource_len(pdev, 3)) { +- aper->ranges[aper->count].base = pci_resource_start(pdev, 3); +- aper->ranges[aper->count].size = pci_resource_len(pdev, 3); +- aper->count++; +- } +- +-#ifdef CONFIG_X86 +- boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; +-#endif +- if (nouveau_modeset != 2) +- remove_conflicting_framebuffers(aper, "nouveaufb", boot); +- kfree(aper); +- +- ret = nouveau_device_create(pdev, NOUVEAU_BUS_PCI, +- nouveau_pci_name(pdev), pci_name(pdev), +- nouveau_config, nouveau_debug, &device); +- if (ret) +- return ret; +- +- pci_set_master(pdev); +- +- ret = drm_get_pci_dev(pdev, pent, &driver_pci); +- if (ret) { +- nouveau_object_ref(NULL, (struct nouveau_object **)&device); +- return ret; +- } +- +- return 0; +-} +- +-#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 +- +-static void +-nouveau_get_hdmi_dev(struct nouveau_drm *drm) +-{ +- struct pci_dev *pdev = drm->dev->pdev; +- +- if (!pdev) { +- DRM_INFO("not a PCI device; no HDMI\n"); +- drm->hdmi_device = NULL; +- return; +- } +- +- /* subfunction one is a hdmi audio device? */ +- drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number, +- PCI_DEVFN(PCI_SLOT(pdev->devfn), 1)); +- +- if (!drm->hdmi_device) { +- NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1); +- return; +- } +- +- if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) { +- NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class); +- pci_dev_put(drm->hdmi_device); +- drm->hdmi_device = NULL; +- return; +- } +-} +- +-static int +-nouveau_drm_load(struct drm_device *dev, unsigned long flags) +-{ +- struct pci_dev *pdev = dev->pdev; +- struct nouveau_drm *drm; +- int ret; +- +- ret = nouveau_cli_create(nouveau_name(dev), "DRM", sizeof(*drm), +- (void **)&drm); +- if (ret) +- return ret; +- +- dev->dev_private = drm; +- drm->dev = dev; +- nvkm_client(&drm->client.base)->debug = +- nouveau_dbgopt(nouveau_debug, "DRM"); +- +- INIT_LIST_HEAD(&drm->clients); +- spin_lock_init(&drm->tile.lock); +- +- nouveau_get_hdmi_dev(drm); +- +- /* make sure AGP controller is in a consistent state before we +- * (possibly) execute vbios init tables (see nouveau_agp.h) +- */ +- if (pdev && drm_pci_device_is_agp(dev) && dev->agp) { +- const u64 enables = NV_DEVICE_V0_DISABLE_IDENTIFY | +- NV_DEVICE_V0_DISABLE_MMIO; +- /* dummy device object, doesn't init anything, but allows +- * agp code access to registers +- */ +- ret = nvif_device_init(&drm->client.base.base, NULL, +- NVDRM_DEVICE, NV_DEVICE, +- &(struct nv_device_v0) { +- .device = ~0, +- .disable = ~enables, +- .debug0 = ~0, +- }, sizeof(struct nv_device_v0), +- &drm->device); +- if (ret) +- goto fail_device; +- +- nouveau_agp_reset(drm); +- nvif_device_fini(&drm->device); +- } +- +- ret = nvif_device_init(&drm->client.base.base, NULL, NVDRM_DEVICE, +- NV_DEVICE, +- &(struct nv_device_v0) { +- .device = ~0, +- .disable = 0, +- .debug0 = 0, +- }, sizeof(struct nv_device_v0), +- &drm->device); +- if (ret) +- goto fail_device; +- +- dev->irq_enabled = true; +- +- /* workaround an odd issue on nvc1 by disabling the device's +- * nosnoop capability. hopefully won't cause issues until a +- * better fix is found - assuming there is one... +- */ +- if (drm->device.info.chipset == 0xc1) +- nvif_mask(&drm->device, 0x00088080, 0x00000800, 0x00000000); +- +- nouveau_vga_init(drm); +- nouveau_agp_init(drm); +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40), +- 0x1000, &drm->client.vm); +- if (ret) +- goto fail_device; +- +- nvkm_client(&drm->client.base)->vm = drm->client.vm; +- } +- +- ret = nouveau_ttm_init(drm); +- if (ret) +- goto fail_ttm; +- +- ret = nouveau_bios_init(dev); +- if (ret) +- goto fail_bios; +- +- ret = nouveau_display_create(dev); +- if (ret) +- goto fail_dispctor; +- +- if (dev->mode_config.num_crtc) { +- ret = nouveau_display_init(dev); +- if (ret) +- goto fail_dispinit; +- } +- +- nouveau_sysfs_init(dev); +- nouveau_hwmon_init(dev); +- nouveau_accel_init(drm); +- nouveau_fbcon_init(dev); +- +- if (nouveau_runtime_pm != 0) { +- pm_runtime_use_autosuspend(dev->dev); +- pm_runtime_set_autosuspend_delay(dev->dev, 5000); +- pm_runtime_set_active(dev->dev); +- pm_runtime_allow(dev->dev); +- pm_runtime_mark_last_busy(dev->dev); +- pm_runtime_put(dev->dev); +- } +- return 0; +- +-fail_dispinit: +- nouveau_display_destroy(dev); +-fail_dispctor: +- nouveau_bios_takedown(dev); +-fail_bios: +- nouveau_ttm_fini(drm); +-fail_ttm: +- nouveau_agp_fini(drm); +- nouveau_vga_fini(drm); +-fail_device: +- nvif_device_fini(&drm->device); +- nouveau_cli_destroy(&drm->client); +- return ret; +-} +- +-static int +-nouveau_drm_unload(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- pm_runtime_get_sync(dev->dev); +- nouveau_fbcon_fini(dev); +- nouveau_accel_fini(drm); +- nouveau_hwmon_fini(dev); +- nouveau_sysfs_fini(dev); +- +- if (dev->mode_config.num_crtc) +- nouveau_display_fini(dev); +- nouveau_display_destroy(dev); +- +- nouveau_bios_takedown(dev); +- +- nouveau_ttm_fini(drm); +- nouveau_agp_fini(drm); +- nouveau_vga_fini(drm); +- +- nvif_device_fini(&drm->device); +- if (drm->hdmi_device) +- pci_dev_put(drm->hdmi_device); +- nouveau_cli_destroy(&drm->client); +- return 0; +-} +- +-void +-nouveau_drm_device_remove(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_client *client; +- struct nouveau_object *device; +- +- dev->irq_enabled = false; +- client = nvkm_client(&drm->client.base); +- device = client->device; +- drm_put_dev(dev); +- +- nouveau_object_ref(NULL, &device); +- nouveau_object_debug(); +-} +-EXPORT_SYMBOL(nouveau_drm_device_remove); +- +-static void +-nouveau_drm_remove(struct pci_dev *pdev) +-{ +- struct drm_device *dev = pci_get_drvdata(pdev); +- +- nouveau_drm_device_remove(dev); +-} +- +-static int +-nouveau_do_suspend(struct drm_device *dev, bool runtime) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_cli *cli; +- int ret; +- +- if (dev->mode_config.num_crtc) { +- NV_INFO(drm, "suspending console...\n"); +- nouveau_fbcon_set_suspend(dev, 1); +- NV_INFO(drm, "suspending display...\n"); +- ret = nouveau_display_suspend(dev, runtime); +- if (ret) +- return ret; +- } +- +- NV_INFO(drm, "evicting buffers...\n"); +- ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM); +- +- NV_INFO(drm, "waiting for kernel channels to go idle...\n"); +- if (drm->cechan) { +- ret = nouveau_channel_idle(drm->cechan); +- if (ret) +- goto fail_display; +- } +- +- if (drm->channel) { +- ret = nouveau_channel_idle(drm->channel); +- if (ret) +- goto fail_display; +- } +- +- NV_INFO(drm, "suspending client object trees...\n"); +- if (drm->fence && nouveau_fence(drm)->suspend) { +- if (!nouveau_fence(drm)->suspend(drm)) { +- ret = -ENOMEM; +- goto fail_display; +- } +- } +- +- list_for_each_entry(cli, &drm->clients, head) { +- ret = nvif_client_suspend(&cli->base); +- if (ret) +- goto fail_client; +- } +- +- NV_INFO(drm, "suspending kernel object tree...\n"); +- ret = nvif_client_suspend(&drm->client.base); +- if (ret) +- goto fail_client; +- +- nouveau_agp_fini(drm); +- return 0; +- +-fail_client: +- list_for_each_entry_continue_reverse(cli, &drm->clients, head) { +- nvif_client_resume(&cli->base); +- } +- +- if (drm->fence && nouveau_fence(drm)->resume) +- nouveau_fence(drm)->resume(drm); +- +-fail_display: +- if (dev->mode_config.num_crtc) { +- NV_INFO(drm, "resuming display...\n"); +- nouveau_display_resume(dev, runtime); +- } +- return ret; +-} +- +-int nouveau_pmops_suspend(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- int ret; +- +- if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || +- drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) +- return 0; +- +- ret = nouveau_do_suspend(drm_dev, false); +- if (ret) +- return ret; +- +- pci_save_state(pdev); +- pci_disable_device(pdev); +- pci_set_power_state(pdev, PCI_D3hot); +- return 0; +-} +- +-static int +-nouveau_do_resume(struct drm_device *dev, bool runtime) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_cli *cli; +- +- NV_INFO(drm, "re-enabling device...\n"); +- +- nouveau_agp_reset(drm); +- +- NV_INFO(drm, "resuming kernel object tree...\n"); +- nvif_client_resume(&drm->client.base); +- nouveau_agp_init(drm); +- +- NV_INFO(drm, "resuming client object trees...\n"); +- if (drm->fence && nouveau_fence(drm)->resume) +- nouveau_fence(drm)->resume(drm); +- +- list_for_each_entry(cli, &drm->clients, head) { +- nvif_client_resume(&cli->base); +- } +- +- nouveau_run_vbios_init(dev); +- +- if (dev->mode_config.num_crtc) { +- NV_INFO(drm, "resuming display...\n"); +- nouveau_display_resume(dev, runtime); +- NV_INFO(drm, "resuming console...\n"); +- nouveau_fbcon_set_suspend(dev, 0); +- } +- +- return 0; +-} +- +-int nouveau_pmops_resume(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- int ret; +- +- if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF || +- drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF) +- return 0; +- +- pci_set_power_state(pdev, PCI_D0); +- pci_restore_state(pdev); +- ret = pci_enable_device(pdev); +- if (ret) +- return ret; +- pci_set_master(pdev); +- +- return nouveau_do_resume(drm_dev, false); +-} +- +-static int nouveau_pmops_freeze(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- return nouveau_do_suspend(drm_dev, false); +-} +- +-static int nouveau_pmops_thaw(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- return nouveau_do_resume(drm_dev, false); +-} +- +- +-static int +-nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_cli *cli; +- char name[32], tmpname[TASK_COMM_LEN]; +- int ret; +- +- /* need to bring up power immediately if opening device */ +- ret = pm_runtime_get_sync(dev->dev); +- if (ret < 0 && ret != -EACCES) +- return ret; +- +- get_task_comm(tmpname, current); +- snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid)); +- +- ret = nouveau_cli_create(nouveau_name(dev), name, sizeof(*cli), +- (void **)&cli); +- +- if (ret) +- goto out_suspend; +- +- cli->base.super = false; +- +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40), +- 0x1000, &cli->vm); +- if (ret) { +- nouveau_cli_destroy(cli); +- goto out_suspend; +- } +- +- nvkm_client(&cli->base)->vm = cli->vm; +- } +- +- fpriv->driver_priv = cli; +- +- mutex_lock(&drm->client.mutex); +- list_add(&cli->head, &drm->clients); +- mutex_unlock(&drm->client.mutex); +- +-out_suspend: +- pm_runtime_mark_last_busy(dev->dev); +- pm_runtime_put_autosuspend(dev->dev); +- +- return ret; +-} +- +-static void +-nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv) +-{ +- struct nouveau_cli *cli = nouveau_cli(fpriv); +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- pm_runtime_get_sync(dev->dev); +- +- if (cli->abi16) +- nouveau_abi16_fini(cli->abi16); +- +- mutex_lock(&drm->client.mutex); +- list_del(&cli->head); +- mutex_unlock(&drm->client.mutex); +- +-} +- +-static void +-nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) +-{ +- struct nouveau_cli *cli = nouveau_cli(fpriv); +- nouveau_cli_destroy(cli); +- pm_runtime_mark_last_busy(dev->dev); +- pm_runtime_put_autosuspend(dev->dev); +-} +- +-static const struct drm_ioctl_desc +-nouveau_ioctls[] = { +- DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), +- DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +- DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), +-}; +- +-long +-nouveau_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +-{ +- struct drm_file *filp = file->private_data; +- struct drm_device *dev = filp->minor->dev; +- long ret; +- +- ret = pm_runtime_get_sync(dev->dev); +- if (ret < 0 && ret != -EACCES) +- return ret; +- +- switch (_IOC_NR(cmd) - DRM_COMMAND_BASE) { +- case DRM_NOUVEAU_NVIF: +- ret = usif_ioctl(filp, (void __user *)arg, _IOC_SIZE(cmd)); +- break; +- default: +- ret = drm_ioctl(file, cmd, arg); +- break; +- } +- +- pm_runtime_mark_last_busy(dev->dev); +- pm_runtime_put_autosuspend(dev->dev); +- return ret; +-} +- +-static const struct file_operations +-nouveau_driver_fops = { +- .owner = THIS_MODULE, +- .open = drm_open, +- .release = drm_release, +- .unlocked_ioctl = nouveau_drm_ioctl, +- .mmap = nouveau_ttm_mmap, +- .poll = drm_poll, +- .read = drm_read, +-#if defined(CONFIG_COMPAT) +- .compat_ioctl = nouveau_compat_ioctl, +-#endif +- .llseek = noop_llseek, +-}; +- +-static struct drm_driver +-driver_stub = { +- .driver_features = +- DRIVER_USE_AGP | +- DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, +- +- .load = nouveau_drm_load, +- .unload = nouveau_drm_unload, +- .open = nouveau_drm_open, +- .preclose = nouveau_drm_preclose, +- .postclose = nouveau_drm_postclose, +- .lastclose = nouveau_vga_lastclose, +- +-#if defined(CONFIG_DEBUG_FS) +- .debugfs_init = nouveau_debugfs_init, +- .debugfs_cleanup = nouveau_debugfs_takedown, +-#endif +- +- .get_vblank_counter = drm_vblank_count, +- .enable_vblank = nouveau_display_vblank_enable, +- .disable_vblank = nouveau_display_vblank_disable, +- .get_scanout_position = nouveau_display_scanoutpos, +- .get_vblank_timestamp = nouveau_display_vblstamp, +- +- .ioctls = nouveau_ioctls, +- .num_ioctls = ARRAY_SIZE(nouveau_ioctls), +- .fops = &nouveau_driver_fops, +- +- .prime_handle_to_fd = drm_gem_prime_handle_to_fd, +- .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +- .gem_prime_export = drm_gem_prime_export, +- .gem_prime_import = drm_gem_prime_import, +- .gem_prime_pin = nouveau_gem_prime_pin, +- .gem_prime_res_obj = nouveau_gem_prime_res_obj, +- .gem_prime_unpin = nouveau_gem_prime_unpin, +- .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table, +- .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table, +- .gem_prime_vmap = nouveau_gem_prime_vmap, +- .gem_prime_vunmap = nouveau_gem_prime_vunmap, +- +- .gem_free_object = nouveau_gem_object_del, +- .gem_open_object = nouveau_gem_object_open, +- .gem_close_object = nouveau_gem_object_close, +- +- .dumb_create = nouveau_display_dumb_create, +- .dumb_map_offset = nouveau_display_dumb_map_offset, +- .dumb_destroy = drm_gem_dumb_destroy, +- +- .name = DRIVER_NAME, +- .desc = DRIVER_DESC, +-#ifdef GIT_REVISION +- .date = GIT_REVISION, +-#else +- .date = DRIVER_DATE, +-#endif +- .major = DRIVER_MAJOR, +- .minor = DRIVER_MINOR, +- .patchlevel = DRIVER_PATCHLEVEL, +-}; +- +-static struct pci_device_id +-nouveau_drm_pci_table[] = { +- { +- PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), +- .class = PCI_BASE_CLASS_DISPLAY << 16, +- .class_mask = 0xff << 16, +- }, +- { +- PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), +- .class = PCI_BASE_CLASS_DISPLAY << 16, +- .class_mask = 0xff << 16, +- }, +- {} +-}; +- +-static int nouveau_pmops_runtime_suspend(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- int ret; +- +- if (nouveau_runtime_pm == 0) { +- pm_runtime_forbid(dev); +- return -EBUSY; +- } +- +- /* are we optimus enabled? */ +- if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) { +- DRM_DEBUG_DRIVER("failing to power off - not optimus\n"); +- pm_runtime_forbid(dev); +- return -EBUSY; +- } +- +- nv_debug_level(SILENT); +- drm_kms_helper_poll_disable(drm_dev); +- vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); +- nouveau_switcheroo_optimus_dsm(); +- ret = nouveau_do_suspend(drm_dev, true); +- pci_save_state(pdev); +- pci_disable_device(pdev); +- pci_ignore_hotplug(pdev); +- pci_set_power_state(pdev, PCI_D3cold); +- drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; +- return ret; +-} +- +-static int nouveau_pmops_runtime_resume(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- struct nvif_device *device = &nouveau_drm(drm_dev)->device; +- int ret; +- +- if (nouveau_runtime_pm == 0) +- return -EINVAL; +- +- pci_set_power_state(pdev, PCI_D0); +- pci_restore_state(pdev); +- ret = pci_enable_device(pdev); +- if (ret) +- return ret; +- pci_set_master(pdev); +- +- ret = nouveau_do_resume(drm_dev, true); +- drm_kms_helper_poll_enable(drm_dev); +- /* do magic */ +- nvif_mask(device, 0x88488, (1 << 25), (1 << 25)); +- vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); +- drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; +- nv_debug_level(NORMAL); +- return ret; +-} +- +-static int nouveau_pmops_runtime_idle(struct device *dev) +-{ +- struct pci_dev *pdev = to_pci_dev(dev); +- struct drm_device *drm_dev = pci_get_drvdata(pdev); +- struct nouveau_drm *drm = nouveau_drm(drm_dev); +- struct drm_crtc *crtc; +- +- if (nouveau_runtime_pm == 0) { +- pm_runtime_forbid(dev); +- return -EBUSY; +- } +- +- /* are we optimus enabled? */ +- if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) { +- DRM_DEBUG_DRIVER("failing to power off - not optimus\n"); +- pm_runtime_forbid(dev); +- return -EBUSY; +- } +- +- /* if we have a hdmi audio device - make sure it has a driver loaded */ +- if (drm->hdmi_device) { +- if (!drm->hdmi_device->driver) { +- DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n"); +- pm_runtime_mark_last_busy(dev); +- return -EBUSY; +- } +- } +- +- list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) { +- if (crtc->enabled) { +- DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); +- return -EBUSY; +- } +- } +- pm_runtime_mark_last_busy(dev); +- pm_runtime_autosuspend(dev); +- /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ +- return 1; +-} +- +-static void nouveau_display_options(void) +-{ +- DRM_DEBUG_DRIVER("Loading Nouveau with parameters:\n"); +- +- DRM_DEBUG_DRIVER("... tv_disable : %d\n", nouveau_tv_disable); +- DRM_DEBUG_DRIVER("... ignorelid : %d\n", nouveau_ignorelid); +- DRM_DEBUG_DRIVER("... duallink : %d\n", nouveau_duallink); +- DRM_DEBUG_DRIVER("... nofbaccel : %d\n", nouveau_nofbaccel); +- DRM_DEBUG_DRIVER("... config : %s\n", nouveau_config); +- DRM_DEBUG_DRIVER("... debug : %s\n", nouveau_debug); +- DRM_DEBUG_DRIVER("... noaccel : %d\n", nouveau_noaccel); +- DRM_DEBUG_DRIVER("... modeset : %d\n", nouveau_modeset); +- DRM_DEBUG_DRIVER("... runpm : %d\n", nouveau_runtime_pm); +- DRM_DEBUG_DRIVER("... vram_pushbuf : %d\n", nouveau_vram_pushbuf); +- DRM_DEBUG_DRIVER("... pstate : %d\n", nouveau_pstate); +-} +- +-static const struct dev_pm_ops nouveau_pm_ops = { +- .suspend = nouveau_pmops_suspend, +- .resume = nouveau_pmops_resume, +- .freeze = nouveau_pmops_freeze, +- .thaw = nouveau_pmops_thaw, +- .poweroff = nouveau_pmops_freeze, +- .restore = nouveau_pmops_resume, +- .runtime_suspend = nouveau_pmops_runtime_suspend, +- .runtime_resume = nouveau_pmops_runtime_resume, +- .runtime_idle = nouveau_pmops_runtime_idle, +-}; +- +-static struct pci_driver +-nouveau_drm_pci_driver = { +- .name = "nouveau", +- .id_table = nouveau_drm_pci_table, +- .probe = nouveau_drm_probe, +- .remove = nouveau_drm_remove, +- .driver.pm = &nouveau_pm_ops, +-}; +- +-struct drm_device * +-nouveau_platform_device_create_(struct platform_device *pdev, int size, +- void **pobject) +-{ +- struct drm_device *drm; +- int err; +- +- err = nouveau_device_create_(pdev, NOUVEAU_BUS_PLATFORM, +- nouveau_platform_name(pdev), +- dev_name(&pdev->dev), nouveau_config, +- nouveau_debug, size, pobject); +- if (err) +- return ERR_PTR(err); +- +- drm = drm_dev_alloc(&driver_platform, &pdev->dev); +- if (!drm) { +- err = -ENOMEM; +- goto err_free; +- } +- +- err = drm_dev_set_unique(drm, "%s", dev_name(&pdev->dev)); +- if (err < 0) +- goto err_free; +- +- drm->platformdev = pdev; +- platform_set_drvdata(pdev, drm); +- +- return drm; +- +-err_free: +- nouveau_object_ref(NULL, (struct nouveau_object **)pobject); +- +- return ERR_PTR(err); +-} +-EXPORT_SYMBOL(nouveau_platform_device_create_); +- +-static int __init +-nouveau_drm_init(void) +-{ +- driver_pci = driver_stub; +- driver_pci.set_busid = drm_pci_set_busid; +- driver_platform = driver_stub; +- driver_platform.set_busid = drm_platform_set_busid; +- +- nouveau_display_options(); +- +- if (nouveau_modeset == -1) { +-#ifdef CONFIG_VGA_CONSOLE +- if (vgacon_text_force()) +- nouveau_modeset = 0; +-#endif +- } +- +- if (!nouveau_modeset) +- return 0; +- +- nouveau_register_dsm_handler(); +- return drm_pci_init(&driver_pci, &nouveau_drm_pci_driver); +-} +- +-static void __exit +-nouveau_drm_exit(void) +-{ +- if (!nouveau_modeset) +- return; +- +- drm_pci_exit(&driver_pci, &nouveau_drm_pci_driver); +- nouveau_unregister_dsm_handler(); +-} +- +-module_init(nouveau_drm_init); +-module_exit(nouveau_drm_exit); +- +-MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table); +-MODULE_AUTHOR(DRIVER_AUTHOR); +-MODULE_DESCRIPTION(DRIVER_DESC); +-MODULE_LICENSE("GPL and additional rights"); +diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h +deleted file mode 100644 +index 8ae36f26..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_drm.h ++++ /dev/null +@@ -1,200 +0,0 @@ +-#ifndef __NOUVEAU_DRMCLI_H__ +-#define __NOUVEAU_DRMCLI_H__ +- +-#define DRIVER_AUTHOR "Nouveau Project" +-#define DRIVER_EMAIL "nouveau@lists.freedesktop.org" +- +-#define DRIVER_NAME "nouveau" +-#define DRIVER_DESC "nVidia Riva/TNT/GeForce/Quadro/Tesla" +-#define DRIVER_DATE "20120801" +- +-#define DRIVER_MAJOR 1 +-#define DRIVER_MINOR 2 +-#define DRIVER_PATCHLEVEL 1 +- +-/* +- * 1.1.1: +- * - added support for tiled system memory buffer objects +- * - added support for NOUVEAU_GETPARAM_GRAPH_UNITS on [nvc0,nve0]. +- * - added support for compressed memory storage types on [nvc0,nve0]. +- * - added support for software methods 0x600,0x644,0x6ac on nvc0 +- * to control registers on the MPs to enable performance counters, +- * and to control the warp error enable mask (OpenGL requires out of +- * bounds access to local memory to be silently ignored / return 0). +- * 1.1.2: +- * - fixes multiple bugs in flip completion events and timestamping +- * 1.2.0: +- * - object api exposed to userspace +- * - fermi,kepler,maxwell zbc +- * 1.2.1: +- * - allow concurrent access to bo's mapped read/write. +- */ +- +-#include +-#include +- +-#include +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "uapi/drm/nouveau_drm.h" +- +-struct nouveau_channel; +-struct platform_device; +- +-#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) +- +-#include "nouveau_fence.h" +-#include "nouveau_bios.h" +- +-struct nouveau_drm_tile { +- struct nouveau_fence *fence; +- bool used; +-}; +- +-enum nouveau_drm_object_route { +- NVDRM_OBJECT_NVIF = 0, +- NVDRM_OBJECT_USIF, +- NVDRM_OBJECT_ABI16, +-}; +- +-enum nouveau_drm_notify_route { +- NVDRM_NOTIFY_NVIF = 0, +- NVDRM_NOTIFY_USIF +-}; +- +-enum nouveau_drm_handle { +- NVDRM_CLIENT = 0xffffffff, +- NVDRM_DEVICE = 0xdddddddd, +- NVDRM_CONTROL = 0xdddddddc, +- NVDRM_DISPLAY = 0xd1500000, +- NVDRM_PUSH = 0xbbbb0000, /* |= client chid */ +- NVDRM_CHAN = 0xcccc0000, /* |= client chid */ +- NVDRM_NVSW = 0x55550000, +-}; +- +-struct nouveau_cli { +- struct nvif_client base; +- struct nouveau_vm *vm; /*XXX*/ +- struct list_head head; +- struct mutex mutex; +- void *abi16; +- struct list_head objects; +- struct list_head notifys; +-}; +- +-static inline struct nouveau_cli * +-nouveau_cli(struct drm_file *fpriv) +-{ +- return fpriv ? fpriv->driver_priv : NULL; +-} +- +-#include +-#include +- +-extern int nouveau_runtime_pm; +- +-struct nouveau_drm { +- struct nouveau_cli client; +- struct drm_device *dev; +- +- struct nvif_device device; +- struct list_head clients; +- +- struct { +- enum { +- UNKNOWN = 0, +- DISABLE = 1, +- ENABLED = 2 +- } stat; +- u32 base; +- u32 size; +- } agp; +- +- /* TTM interface support */ +- struct { +- struct drm_global_reference mem_global_ref; +- struct ttm_bo_global_ref bo_global_ref; +- struct ttm_bo_device bdev; +- atomic_t validate_sequence; +- int (*move)(struct nouveau_channel *, +- struct ttm_buffer_object *, +- struct ttm_mem_reg *, struct ttm_mem_reg *); +- struct nouveau_channel *chan; +- struct nvif_object copy; +- int mtrr; +- } ttm; +- +- /* GEM interface support */ +- struct { +- u64 vram_available; +- u64 gart_available; +- } gem; +- +- /* synchronisation */ +- void *fence; +- +- /* context for accelerated drm-internal operations */ +- struct nouveau_channel *cechan; +- struct nouveau_channel *channel; +- struct nouveau_gpuobj *notify; +- struct nouveau_fbdev *fbcon; +- struct nvif_object nvsw; +- struct nvif_object ntfy; +- +- /* nv10-nv40 tiling regions */ +- struct { +- struct nouveau_drm_tile reg[15]; +- spinlock_t lock; +- } tile; +- +- /* modesetting */ +- struct nvbios vbios; +- struct nouveau_display *display; +- struct backlight_device *backlight; +- +- /* power management */ +- struct nouveau_hwmon *hwmon; +- struct nouveau_sysfs *sysfs; +- +- /* display power reference */ +- bool have_disp_power_ref; +- +- struct dev_pm_domain vga_pm_domain; +- struct pci_dev *hdmi_device; +-}; +- +-static inline struct nouveau_drm * +-nouveau_drm(struct drm_device *dev) +-{ +- return dev->dev_private; +-} +- +-int nouveau_pmops_suspend(struct device *); +-int nouveau_pmops_resume(struct device *); +- +-#define nouveau_platform_device_create(p, u) \ +- nouveau_platform_device_create_(p, sizeof(**u), (void **)u) +-struct drm_device * +-nouveau_platform_device_create_(struct platform_device *pdev, +- int size, void **pobject); +-void nouveau_drm_device_remove(struct drm_device *dev); +- +-#define NV_PRINTK(l,c,f,a...) do { \ +- struct nouveau_cli *_cli = (c); \ +- nv_##l(_cli->base.base.priv, f, ##a); \ +-} while(0) +-#define NV_FATAL(drm,f,a...) NV_PRINTK(fatal, &(drm)->client, f, ##a) +-#define NV_ERROR(drm,f,a...) NV_PRINTK(error, &(drm)->client, f, ##a) +-#define NV_WARN(drm,f,a...) NV_PRINTK(warn, &(drm)->client, f, ##a) +-#define NV_INFO(drm,f,a...) NV_PRINTK(info, &(drm)->client, f, ##a) +-#define NV_DEBUG(drm,f,a...) NV_PRINTK(debug, &(drm)->client, f, ##a) +- +-extern int nouveau_modeset; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h +deleted file mode 100644 +index 5f0e37fc..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NOUVEAU_ENCODER_H__ +-#define __NOUVEAU_ENCODER_H__ +- +-#include +- +-#include +-#include "dispnv04/disp.h" +- +-#define NV_DPMS_CLEARED 0x80 +- +-struct nouveau_i2c_port; +- +-struct nouveau_encoder { +- struct drm_encoder_slave base; +- +- struct dcb_output *dcb; +- int or; +- struct nouveau_i2c_port *i2c; +- +- /* different to drm_encoder.crtc, this reflects what's +- * actually programmed on the hw, not the proposed crtc */ +- struct drm_crtc *crtc; +- u32 ctrl; +- +- struct drm_display_mode mode; +- int last_dpms; +- +- struct nv04_output_reg restore; +- +- union { +- struct { +- u8 dpcd[8]; +- int link_nr; +- int link_bw; +- u32 datarate; +- } dp; +- }; +-}; +- +-struct nouveau_encoder * +-find_encoder(struct drm_connector *connector, int type); +- +-static inline struct nouveau_encoder *nouveau_encoder(struct drm_encoder *enc) +-{ +- struct drm_encoder_slave *slave = to_encoder_slave(enc); +- +- return container_of(slave, struct nouveau_encoder, base); +-} +- +-static inline struct drm_encoder *to_drm_encoder(struct nouveau_encoder *enc) +-{ +- return &enc->base.base; +-} +- +-static inline struct drm_encoder_slave_funcs * +-get_slave_funcs(struct drm_encoder *enc) +-{ +- return to_encoder_slave(enc)->slave_funcs; +-} +- +-/* nouveau_dp.c */ +-int nouveau_dp_detect(struct nouveau_encoder *); +- +-struct nouveau_connector * +-nouveau_encoder_connector_get(struct nouveau_encoder *encoder); +- +-#endif /* __NOUVEAU_ENCODER_H__ */ +diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c +deleted file mode 100644 +index ddcfc1d2..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c ++++ /dev/null +@@ -1,600 +0,0 @@ +-/* +- * Copyright © 2007 David Airlie +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- * +- * Authors: +- * David Airlie +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_gem.h" +-#include "nouveau_bo.h" +-#include "nouveau_fbcon.h" +-#include "nouveau_chan.h" +- +-#include "nouveau_crtc.h" +- +-MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration"); +-int nouveau_nofbaccel = 0; +-module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400); +- +-static void +-nouveau_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- struct nvif_device *device = &drm->device; +- int ret; +- +- if (info->state != FBINFO_STATE_RUNNING) +- return; +- +- ret = -ENODEV; +- if (!in_interrupt() && !(info->flags & FBINFO_HWACCEL_DISABLED) && +- mutex_trylock(&drm->client.mutex)) { +- if (device->info.family < NV_DEVICE_INFO_V0_TESLA) +- ret = nv04_fbcon_fillrect(info, rect); +- else +- if (device->info.family < NV_DEVICE_INFO_V0_FERMI) +- ret = nv50_fbcon_fillrect(info, rect); +- else +- ret = nvc0_fbcon_fillrect(info, rect); +- mutex_unlock(&drm->client.mutex); +- } +- +- if (ret == 0) +- return; +- +- if (ret != -ENODEV) +- nouveau_fbcon_gpu_lockup(info); +- cfb_fillrect(info, rect); +-} +- +-static void +-nouveau_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *image) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- struct nvif_device *device = &drm->device; +- int ret; +- +- if (info->state != FBINFO_STATE_RUNNING) +- return; +- +- ret = -ENODEV; +- if (!in_interrupt() && !(info->flags & FBINFO_HWACCEL_DISABLED) && +- mutex_trylock(&drm->client.mutex)) { +- if (device->info.family < NV_DEVICE_INFO_V0_TESLA) +- ret = nv04_fbcon_copyarea(info, image); +- else +- if (device->info.family < NV_DEVICE_INFO_V0_FERMI) +- ret = nv50_fbcon_copyarea(info, image); +- else +- ret = nvc0_fbcon_copyarea(info, image); +- mutex_unlock(&drm->client.mutex); +- } +- +- if (ret == 0) +- return; +- +- if (ret != -ENODEV) +- nouveau_fbcon_gpu_lockup(info); +- cfb_copyarea(info, image); +-} +- +-static void +-nouveau_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- struct nvif_device *device = &drm->device; +- int ret; +- +- if (info->state != FBINFO_STATE_RUNNING) +- return; +- +- ret = -ENODEV; +- if (!in_interrupt() && !(info->flags & FBINFO_HWACCEL_DISABLED) && +- mutex_trylock(&drm->client.mutex)) { +- if (device->info.family < NV_DEVICE_INFO_V0_TESLA) +- ret = nv04_fbcon_imageblit(info, image); +- else +- if (device->info.family < NV_DEVICE_INFO_V0_FERMI) +- ret = nv50_fbcon_imageblit(info, image); +- else +- ret = nvc0_fbcon_imageblit(info, image); +- mutex_unlock(&drm->client.mutex); +- } +- +- if (ret == 0) +- return; +- +- if (ret != -ENODEV) +- nouveau_fbcon_gpu_lockup(info); +- cfb_imageblit(info, image); +-} +- +-static int +-nouveau_fbcon_sync(struct fb_info *info) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- if (!chan || !chan->accel_done || in_interrupt() || +- info->state != FBINFO_STATE_RUNNING || +- info->flags & FBINFO_HWACCEL_DISABLED) +- return 0; +- +- if (!mutex_trylock(&drm->client.mutex)) +- return 0; +- +- ret = nouveau_channel_idle(chan); +- mutex_unlock(&drm->client.mutex); +- if (ret) { +- nouveau_fbcon_gpu_lockup(info); +- return 0; +- } +- +- chan->accel_done = false; +- return 0; +-} +- +-static int +-nouveau_fbcon_open(struct fb_info *info, int user) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- int ret = pm_runtime_get_sync(drm->dev->dev); +- if (ret < 0 && ret != -EACCES) +- return ret; +- return 0; +-} +- +-static int +-nouveau_fbcon_release(struct fb_info *info, int user) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- pm_runtime_put(drm->dev->dev); +- return 0; +-} +- +-static struct fb_ops nouveau_fbcon_ops = { +- .owner = THIS_MODULE, +- .fb_open = nouveau_fbcon_open, +- .fb_release = nouveau_fbcon_release, +- .fb_check_var = drm_fb_helper_check_var, +- .fb_set_par = drm_fb_helper_set_par, +- .fb_fillrect = nouveau_fbcon_fillrect, +- .fb_copyarea = nouveau_fbcon_copyarea, +- .fb_imageblit = nouveau_fbcon_imageblit, +- .fb_sync = nouveau_fbcon_sync, +- .fb_pan_display = drm_fb_helper_pan_display, +- .fb_blank = drm_fb_helper_blank, +- .fb_setcmap = drm_fb_helper_setcmap, +- .fb_debug_enter = drm_fb_helper_debug_enter, +- .fb_debug_leave = drm_fb_helper_debug_leave, +-}; +- +-static struct fb_ops nouveau_fbcon_sw_ops = { +- .owner = THIS_MODULE, +- .fb_open = nouveau_fbcon_open, +- .fb_release = nouveau_fbcon_release, +- .fb_check_var = drm_fb_helper_check_var, +- .fb_set_par = drm_fb_helper_set_par, +- .fb_fillrect = cfb_fillrect, +- .fb_copyarea = cfb_copyarea, +- .fb_imageblit = cfb_imageblit, +- .fb_pan_display = drm_fb_helper_pan_display, +- .fb_blank = drm_fb_helper_blank, +- .fb_setcmap = drm_fb_helper_setcmap, +- .fb_debug_enter = drm_fb_helper_debug_enter, +- .fb_debug_leave = drm_fb_helper_debug_leave, +-}; +- +-void +-nouveau_fbcon_accel_save_disable(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- if (drm->fbcon) { +- drm->fbcon->saved_flags = drm->fbcon->helper.fbdev->flags; +- drm->fbcon->helper.fbdev->flags |= FBINFO_HWACCEL_DISABLED; +- } +-} +- +-void +-nouveau_fbcon_accel_restore(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- if (drm->fbcon) { +- drm->fbcon->helper.fbdev->flags = drm->fbcon->saved_flags; +- } +-} +- +-static void +-nouveau_fbcon_accel_fini(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_fbdev *fbcon = drm->fbcon; +- if (fbcon && drm->channel) { +- console_lock(); +- fbcon->helper.fbdev->flags |= FBINFO_HWACCEL_DISABLED; +- console_unlock(); +- nouveau_channel_idle(drm->channel); +- nvif_object_fini(&fbcon->twod); +- nvif_object_fini(&fbcon->blit); +- nvif_object_fini(&fbcon->gdi); +- nvif_object_fini(&fbcon->patt); +- nvif_object_fini(&fbcon->rop); +- nvif_object_fini(&fbcon->clip); +- nvif_object_fini(&fbcon->surf2d); +- } +-} +- +-static void +-nouveau_fbcon_accel_init(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_fbdev *fbcon = drm->fbcon; +- struct fb_info *info = fbcon->helper.fbdev; +- int ret; +- +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) +- ret = nv04_fbcon_accel_init(info); +- else +- if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI) +- ret = nv50_fbcon_accel_init(info); +- else +- ret = nvc0_fbcon_accel_init(info); +- +- if (ret == 0) +- info->fbops = &nouveau_fbcon_ops; +-} +- +-static void nouveau_fbcon_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, +- u16 blue, int regno) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- nv_crtc->lut.r[regno] = red; +- nv_crtc->lut.g[regno] = green; +- nv_crtc->lut.b[regno] = blue; +-} +- +-static void nouveau_fbcon_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, +- u16 *blue, int regno) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- +- *red = nv_crtc->lut.r[regno]; +- *green = nv_crtc->lut.g[regno]; +- *blue = nv_crtc->lut.b[regno]; +-} +- +-static void +-nouveau_fbcon_zfill(struct drm_device *dev, struct nouveau_fbdev *fbcon) +-{ +- struct fb_info *info = fbcon->helper.fbdev; +- struct fb_fillrect rect; +- +- /* Clear the entire fbcon. The drm will program every connector +- * with it's preferred mode. If the sizes differ, one display will +- * quite likely have garbage around the console. +- */ +- rect.dx = rect.dy = 0; +- rect.width = info->var.xres_virtual; +- rect.height = info->var.yres_virtual; +- rect.color = 0; +- rect.rop = ROP_COPY; +- info->fbops->fb_fillrect(info, &rect); +-} +- +-static int +-nouveau_fbcon_create(struct drm_fb_helper *helper, +- struct drm_fb_helper_surface_size *sizes) +-{ +- struct nouveau_fbdev *fbcon = +- container_of(helper, struct nouveau_fbdev, helper); +- struct drm_device *dev = fbcon->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct fb_info *info; +- struct drm_framebuffer *fb; +- struct nouveau_framebuffer *nouveau_fb; +- struct nouveau_channel *chan; +- struct nouveau_bo *nvbo; +- struct drm_mode_fb_cmd2 mode_cmd; +- struct pci_dev *pdev = dev->pdev; +- int size, ret; +- +- mode_cmd.width = sizes->surface_width; +- mode_cmd.height = sizes->surface_height; +- +- mode_cmd.pitches[0] = mode_cmd.width * (sizes->surface_bpp >> 3); +- mode_cmd.pitches[0] = roundup(mode_cmd.pitches[0], 256); +- +- mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, +- sizes->surface_depth); +- +- size = mode_cmd.pitches[0] * mode_cmd.height; +- size = roundup(size, PAGE_SIZE); +- +- ret = nouveau_gem_new(dev, size, 0, NOUVEAU_GEM_DOMAIN_VRAM, +- 0, 0x0000, &nvbo); +- if (ret) { +- NV_ERROR(drm, "failed to allocate framebuffer\n"); +- goto out; +- } +- +- ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_VRAM); +- if (ret) { +- NV_ERROR(drm, "failed to pin fb: %d\n", ret); +- goto out_unref; +- } +- +- ret = nouveau_bo_map(nvbo); +- if (ret) { +- NV_ERROR(drm, "failed to map fb: %d\n", ret); +- goto out_unpin; +- } +- +- chan = nouveau_nofbaccel ? NULL : drm->channel; +- if (chan && device->info.family >= NV_DEVICE_INFO_V0_TESLA) { +- ret = nouveau_bo_vma_add(nvbo, drm->client.vm, +- &fbcon->nouveau_fb.vma); +- if (ret) { +- NV_ERROR(drm, "failed to map fb into chan: %d\n", ret); +- chan = NULL; +- } +- } +- +- mutex_lock(&dev->struct_mutex); +- +- info = framebuffer_alloc(0, &pdev->dev); +- if (!info) { +- ret = -ENOMEM; +- goto out_unlock; +- } +- +- ret = fb_alloc_cmap(&info->cmap, 256, 0); +- if (ret) { +- ret = -ENOMEM; +- framebuffer_release(info); +- goto out_unlock; +- } +- +- info->par = fbcon; +- +- nouveau_framebuffer_init(dev, &fbcon->nouveau_fb, &mode_cmd, nvbo); +- +- nouveau_fb = &fbcon->nouveau_fb; +- fb = &nouveau_fb->base; +- +- /* setup helper */ +- fbcon->helper.fb = fb; +- fbcon->helper.fbdev = info; +- +- strcpy(info->fix.id, "nouveaufb"); +- if (!chan) +- info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_DISABLED; +- else +- info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA | +- FBINFO_HWACCEL_FILLRECT | +- FBINFO_HWACCEL_IMAGEBLIT; +- info->flags |= FBINFO_CAN_FORCE_OUTPUT; +- info->fbops = &nouveau_fbcon_sw_ops; +- info->fix.smem_start = nvbo->bo.mem.bus.base + +- nvbo->bo.mem.bus.offset; +- info->fix.smem_len = size; +- +- info->screen_base = nvbo_kmap_obj_iovirtual(nouveau_fb->nvbo); +- info->screen_size = size; +- +- drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); +- drm_fb_helper_fill_var(info, &fbcon->helper, sizes->fb_width, sizes->fb_height); +- +- /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ +- +- mutex_unlock(&dev->struct_mutex); +- +- if (chan) +- nouveau_fbcon_accel_init(dev); +- nouveau_fbcon_zfill(dev, fbcon); +- +- /* To allow resizeing without swapping buffers */ +- NV_INFO(drm, "allocated %dx%d fb: 0x%lx, bo %p\n", +- nouveau_fb->base.width, nouveau_fb->base.height, +- nvbo->bo.offset, nvbo); +- +- vga_switcheroo_client_fb_set(dev->pdev, info); +- return 0; +- +-out_unlock: +- mutex_unlock(&dev->struct_mutex); +- if (chan) +- nouveau_bo_vma_del(nvbo, &fbcon->nouveau_fb.vma); +- nouveau_bo_unmap(nvbo); +-out_unpin: +- nouveau_bo_unpin(nvbo); +-out_unref: +- nouveau_bo_ref(NULL, &nvbo); +-out: +- return ret; +-} +- +-void +-nouveau_fbcon_output_poll_changed(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- if (drm->fbcon) +- drm_fb_helper_hotplug_event(&drm->fbcon->helper); +-} +- +-static int +-nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *fbcon) +-{ +- struct nouveau_framebuffer *nouveau_fb = &fbcon->nouveau_fb; +- struct fb_info *info; +- +- if (fbcon->helper.fbdev) { +- info = fbcon->helper.fbdev; +- unregister_framebuffer(info); +- if (info->cmap.len) +- fb_dealloc_cmap(&info->cmap); +- framebuffer_release(info); +- } +- +- if (nouveau_fb->nvbo) { +- nouveau_bo_unmap(nouveau_fb->nvbo); +- nouveau_bo_vma_del(nouveau_fb->nvbo, &nouveau_fb->vma); +- nouveau_bo_unpin(nouveau_fb->nvbo); +- drm_gem_object_unreference_unlocked(&nouveau_fb->nvbo->gem); +- nouveau_fb->nvbo = NULL; +- } +- drm_fb_helper_fini(&fbcon->helper); +- drm_framebuffer_unregister_private(&nouveau_fb->base); +- drm_framebuffer_cleanup(&nouveau_fb->base); +- return 0; +-} +- +-void nouveau_fbcon_gpu_lockup(struct fb_info *info) +-{ +- struct nouveau_fbdev *fbcon = info->par; +- struct nouveau_drm *drm = nouveau_drm(fbcon->dev); +- +- NV_ERROR(drm, "GPU lockup - switching to software fbcon\n"); +- info->flags |= FBINFO_HWACCEL_DISABLED; +-} +- +-static const struct drm_fb_helper_funcs nouveau_fbcon_helper_funcs = { +- .gamma_set = nouveau_fbcon_gamma_set, +- .gamma_get = nouveau_fbcon_gamma_get, +- .fb_probe = nouveau_fbcon_create, +-}; +- +-static void +-nouveau_fbcon_set_suspend_work(struct work_struct *work) +-{ +- struct nouveau_fbdev *fbcon = container_of(work, typeof(*fbcon), work); +- console_lock(); +- nouveau_fbcon_accel_restore(fbcon->dev); +- nouveau_fbcon_zfill(fbcon->dev, fbcon); +- fb_set_suspend(fbcon->helper.fbdev, FBINFO_STATE_RUNNING); +- console_unlock(); +-} +- +-int +-nouveau_fbcon_init(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_fbdev *fbcon; +- int preferred_bpp; +- int ret; +- +- if (!dev->mode_config.num_crtc || +- (dev->pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA) +- return 0; +- +- fbcon = kzalloc(sizeof(struct nouveau_fbdev), GFP_KERNEL); +- if (!fbcon) +- return -ENOMEM; +- +- INIT_WORK(&fbcon->work, nouveau_fbcon_set_suspend_work); +- fbcon->dev = dev; +- drm->fbcon = fbcon; +- +- drm_fb_helper_prepare(dev, &fbcon->helper, &nouveau_fbcon_helper_funcs); +- +- ret = drm_fb_helper_init(dev, &fbcon->helper, +- dev->mode_config.num_crtc, 4); +- if (ret) { +- kfree(fbcon); +- return ret; +- } +- +- drm_fb_helper_single_add_all_connectors(&fbcon->helper); +- +- if (drm->device.info.ram_size <= 32 * 1024 * 1024) +- preferred_bpp = 8; +- else +- if (drm->device.info.ram_size <= 64 * 1024 * 1024) +- preferred_bpp = 16; +- else +- preferred_bpp = 32; +- +- /* disable all the possible outputs/crtcs before entering KMS mode */ +- drm_helper_disable_unused_functions(dev); +- +- drm_fb_helper_initial_config(&fbcon->helper, preferred_bpp); +- return 0; +-} +- +-void +-nouveau_fbcon_fini(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- +- if (!drm->fbcon) +- return; +- +- nouveau_fbcon_accel_fini(dev); +- nouveau_fbcon_destroy(dev, drm->fbcon); +- kfree(drm->fbcon); +- drm->fbcon = NULL; +-} +- +-void +-nouveau_fbcon_set_suspend(struct drm_device *dev, int state) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- if (drm->fbcon) { +- if (state == FBINFO_STATE_RUNNING) { +- schedule_work(&drm->fbcon->work); +- return; +- } +- flush_work(&drm->fbcon->work); +- console_lock(); +- fb_set_suspend(drm->fbcon->helper.fbdev, state); +- nouveau_fbcon_accel_save_disable(dev); +- console_unlock(); +- } +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.h b/drivers/gpu/drm/nouveau/nouveau_fbcon.h +deleted file mode 100644 +index 6208e70e..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.h ++++ /dev/null +@@ -1,80 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NOUVEAU_FBCON_H__ +-#define __NOUVEAU_FBCON_H__ +- +-#include +- +-#include "nouveau_display.h" +- +-struct nouveau_fbdev { +- struct drm_fb_helper helper; +- struct nouveau_framebuffer nouveau_fb; +- struct list_head fbdev_list; +- struct drm_device *dev; +- struct work_struct work; +- unsigned int saved_flags; +- struct nvif_object surf2d; +- struct nvif_object clip; +- struct nvif_object rop; +- struct nvif_object patt; +- struct nvif_object gdi; +- struct nvif_object blit; +- struct nvif_object twod; +-}; +- +-void nouveau_fbcon_restore(void); +- +-int nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region); +-int nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); +-int nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); +-int nv04_fbcon_accel_init(struct fb_info *info); +- +-int nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); +-int nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region); +-int nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); +-int nv50_fbcon_accel_init(struct fb_info *info); +- +-int nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect); +-int nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region); +-int nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image); +-int nvc0_fbcon_accel_init(struct fb_info *info); +- +-void nouveau_fbcon_gpu_lockup(struct fb_info *info); +- +-int nouveau_fbcon_init(struct drm_device *dev); +-void nouveau_fbcon_fini(struct drm_device *dev); +-void nouveau_fbcon_set_suspend(struct drm_device *dev, int state); +-void nouveau_fbcon_accel_save_disable(struct drm_device *dev); +-void nouveau_fbcon_accel_restore(struct drm_device *dev); +- +-void nouveau_fbcon_output_poll_changed(struct drm_device *dev); +- +-extern int nouveau_nofbaccel; +- +-#endif /* __NV50_FBCON_H__ */ +- +diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c +deleted file mode 100644 +index f32a4347..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_fence.c ++++ /dev/null +@@ -1,590 +0,0 @@ +-/* +- * Copyright (C) 2007 Ben Skeggs. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include +- +-#include +-#include +-#include +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fence.h" +- +-static const struct fence_ops nouveau_fence_ops_uevent; +-static const struct fence_ops nouveau_fence_ops_legacy; +- +-static inline struct nouveau_fence * +-from_fence(struct fence *fence) +-{ +- return container_of(fence, struct nouveau_fence, base); +-} +- +-static inline struct nouveau_fence_chan * +-nouveau_fctx(struct nouveau_fence *fence) +-{ +- return container_of(fence->base.lock, struct nouveau_fence_chan, lock); +-} +- +-static int +-nouveau_fence_signal(struct nouveau_fence *fence) +-{ +- int drop = 0; +- +- fence_signal_locked(&fence->base); +- list_del(&fence->head); +- rcu_assign_pointer(fence->channel, NULL); +- +- if (test_bit(FENCE_FLAG_USER_BITS, &fence->base.flags)) { +- struct nouveau_fence_chan *fctx = nouveau_fctx(fence); +- +- if (!--fctx->notify_ref) +- drop = 1; +- } +- +- fence_put(&fence->base); +- return drop; +-} +- +-static struct nouveau_fence * +-nouveau_local_fence(struct fence *fence, struct nouveau_drm *drm) { +- struct nouveau_fence_priv *priv = (void*)drm->fence; +- +- if (fence->ops != &nouveau_fence_ops_legacy && +- fence->ops != &nouveau_fence_ops_uevent) +- return NULL; +- +- if (fence->context < priv->context_base || +- fence->context >= priv->context_base + priv->contexts) +- return NULL; +- +- return from_fence(fence); +-} +- +-void +-nouveau_fence_context_del(struct nouveau_fence_chan *fctx) +-{ +- struct nouveau_fence *fence; +- +- spin_lock_irq(&fctx->lock); +- while (!list_empty(&fctx->pending)) { +- fence = list_entry(fctx->pending.next, typeof(*fence), head); +- +- if (nouveau_fence_signal(fence)) +- nvif_notify_put(&fctx->notify); +- } +- spin_unlock_irq(&fctx->lock); +- +- nvif_notify_fini(&fctx->notify); +- fctx->dead = 1; +- +- /* +- * Ensure that all accesses to fence->channel complete before freeing +- * the channel. +- */ +- synchronize_rcu(); +-} +- +-static void +-nouveau_fence_context_put(struct kref *fence_ref) +-{ +- kfree(container_of(fence_ref, struct nouveau_fence_chan, fence_ref)); +-} +- +-void +-nouveau_fence_context_free(struct nouveau_fence_chan *fctx) +-{ +- kref_put(&fctx->fence_ref, nouveau_fence_context_put); +-} +- +-static int +-nouveau_fence_update(struct nouveau_channel *chan, struct nouveau_fence_chan *fctx) +-{ +- struct nouveau_fence *fence; +- int drop = 0; +- u32 seq = fctx->read(chan); +- +- while (!list_empty(&fctx->pending)) { +- fence = list_entry(fctx->pending.next, typeof(*fence), head); +- +- if ((int)(seq - fence->base.seqno) < 0) +- break; +- +- drop |= nouveau_fence_signal(fence); +- } +- +- return drop; +-} +- +-static int +-nouveau_fence_wait_uevent_handler(struct nvif_notify *notify) +-{ +- struct nouveau_fence_chan *fctx = +- container_of(notify, typeof(*fctx), notify); +- unsigned long flags; +- int ret = NVIF_NOTIFY_KEEP; +- +- spin_lock_irqsave(&fctx->lock, flags); +- if (!list_empty(&fctx->pending)) { +- struct nouveau_fence *fence; +- struct nouveau_channel *chan; +- +- fence = list_entry(fctx->pending.next, typeof(*fence), head); +- chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock)); +- if (nouveau_fence_update(fence->channel, fctx)) +- ret = NVIF_NOTIFY_DROP; +- } +- spin_unlock_irqrestore(&fctx->lock, flags); +- +- return ret; +-} +- +-void +-nouveau_fence_context_new(struct nouveau_channel *chan, struct nouveau_fence_chan *fctx) +-{ +- struct nouveau_fence_priv *priv = (void*)chan->drm->fence; +- struct nouveau_cli *cli = (void *)nvif_client(chan->object); +- int ret; +- +- INIT_LIST_HEAD(&fctx->flip); +- INIT_LIST_HEAD(&fctx->pending); +- spin_lock_init(&fctx->lock); +- fctx->context = priv->context_base + chan->chid; +- +- if (chan == chan->drm->cechan) +- strcpy(fctx->name, "copy engine channel"); +- else if (chan == chan->drm->channel) +- strcpy(fctx->name, "generic kernel channel"); +- else +- strcpy(fctx->name, nvkm_client(&cli->base)->name); +- +- kref_init(&fctx->fence_ref); +- if (!priv->uevent) +- return; +- +- ret = nvif_notify_init(chan->object, NULL, +- nouveau_fence_wait_uevent_handler, false, +- G82_CHANNEL_DMA_V0_NTFY_UEVENT, +- &(struct nvif_notify_uevent_req) { }, +- sizeof(struct nvif_notify_uevent_req), +- sizeof(struct nvif_notify_uevent_rep), +- &fctx->notify); +- +- WARN_ON(ret); +-} +- +-struct nouveau_fence_work { +- struct work_struct work; +- struct fence_cb cb; +- void (*func)(void *); +- void *data; +-}; +- +-static void +-nouveau_fence_work_handler(struct work_struct *kwork) +-{ +- struct nouveau_fence_work *work = container_of(kwork, typeof(*work), work); +- work->func(work->data); +- kfree(work); +-} +- +-static void nouveau_fence_work_cb(struct fence *fence, struct fence_cb *cb) +-{ +- struct nouveau_fence_work *work = container_of(cb, typeof(*work), cb); +- +- schedule_work(&work->work); +-} +- +-void +-nouveau_fence_work(struct fence *fence, +- void (*func)(void *), void *data) +-{ +- struct nouveau_fence_work *work; +- +- if (fence_is_signaled(fence)) +- goto err; +- +- work = kmalloc(sizeof(*work), GFP_KERNEL); +- if (!work) { +- /* +- * this might not be a nouveau fence any more, +- * so force a lazy wait here +- */ +- WARN_ON(nouveau_fence_wait((struct nouveau_fence *)fence, +- true, false)); +- goto err; +- } +- +- INIT_WORK(&work->work, nouveau_fence_work_handler); +- work->func = func; +- work->data = data; +- +- if (fence_add_callback(fence, &work->cb, nouveau_fence_work_cb) < 0) +- goto err_free; +- return; +- +-err_free: +- kfree(work); +-err: +- func(data); +-} +- +-int +-nouveau_fence_emit(struct nouveau_fence *fence, struct nouveau_channel *chan) +-{ +- struct nouveau_fence_chan *fctx = chan->fence; +- struct nouveau_fence_priv *priv = (void*)chan->drm->fence; +- int ret; +- +- fence->channel = chan; +- fence->timeout = jiffies + (15 * HZ); +- +- if (priv->uevent) +- fence_init(&fence->base, &nouveau_fence_ops_uevent, +- &fctx->lock, fctx->context, ++fctx->sequence); +- else +- fence_init(&fence->base, &nouveau_fence_ops_legacy, +- &fctx->lock, fctx->context, ++fctx->sequence); +- kref_get(&fctx->fence_ref); +- +- trace_fence_emit(&fence->base); +- ret = fctx->emit(fence); +- if (!ret) { +- fence_get(&fence->base); +- spin_lock_irq(&fctx->lock); +- +- if (nouveau_fence_update(chan, fctx)) +- nvif_notify_put(&fctx->notify); +- +- list_add_tail(&fence->head, &fctx->pending); +- spin_unlock_irq(&fctx->lock); +- } +- +- return ret; +-} +- +-bool +-nouveau_fence_done(struct nouveau_fence *fence) +-{ +- if (fence->base.ops == &nouveau_fence_ops_legacy || +- fence->base.ops == &nouveau_fence_ops_uevent) { +- struct nouveau_fence_chan *fctx = nouveau_fctx(fence); +- struct nouveau_channel *chan; +- unsigned long flags; +- +- if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags)) +- return true; +- +- spin_lock_irqsave(&fctx->lock, flags); +- chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock)); +- if (chan && nouveau_fence_update(chan, fctx)) +- nvif_notify_put(&fctx->notify); +- spin_unlock_irqrestore(&fctx->lock, flags); +- } +- return fence_is_signaled(&fence->base); +-} +- +-static long +-nouveau_fence_wait_legacy(struct fence *f, bool intr, long wait) +-{ +- struct nouveau_fence *fence = from_fence(f); +- unsigned long sleep_time = NSEC_PER_MSEC / 1000; +- unsigned long t = jiffies, timeout = t + wait; +- +- while (!nouveau_fence_done(fence)) { +- ktime_t kt; +- +- t = jiffies; +- +- if (wait != MAX_SCHEDULE_TIMEOUT && time_after_eq(t, timeout)) { +- __set_current_state(TASK_RUNNING); +- return 0; +- } +- +- __set_current_state(intr ? TASK_INTERRUPTIBLE : +- TASK_UNINTERRUPTIBLE); +- +- kt = ktime_set(0, sleep_time); +- schedule_hrtimeout(&kt, HRTIMER_MODE_REL); +- sleep_time *= 2; +- if (sleep_time > NSEC_PER_MSEC) +- sleep_time = NSEC_PER_MSEC; +- +- if (intr && signal_pending(current)) +- return -ERESTARTSYS; +- } +- +- __set_current_state(TASK_RUNNING); +- +- return timeout - t; +-} +- +-static int +-nouveau_fence_wait_busy(struct nouveau_fence *fence, bool intr) +-{ +- int ret = 0; +- +- while (!nouveau_fence_done(fence)) { +- if (time_after_eq(jiffies, fence->timeout)) { +- ret = -EBUSY; +- break; +- } +- +- __set_current_state(intr ? +- TASK_INTERRUPTIBLE : +- TASK_UNINTERRUPTIBLE); +- +- if (intr && signal_pending(current)) { +- ret = -ERESTARTSYS; +- break; +- } +- } +- +- __set_current_state(TASK_RUNNING); +- return ret; +-} +- +-int +-nouveau_fence_wait(struct nouveau_fence *fence, bool lazy, bool intr) +-{ +- long ret; +- +- if (!lazy) +- return nouveau_fence_wait_busy(fence, intr); +- +- ret = fence_wait_timeout(&fence->base, intr, 15 * HZ); +- if (ret < 0) +- return ret; +- else if (!ret) +- return -EBUSY; +- else +- return 0; +-} +- +-int +-nouveau_fence_sync(struct nouveau_bo *nvbo, struct nouveau_channel *chan, bool exclusive, bool intr) +-{ +- struct nouveau_fence_chan *fctx = chan->fence; +- struct fence *fence; +- struct reservation_object *resv = nvbo->bo.resv; +- struct reservation_object_list *fobj; +- struct nouveau_fence *f; +- int ret = 0, i; +- +- if (!exclusive) { +- ret = reservation_object_reserve_shared(resv); +- +- if (ret) +- return ret; +- } +- +- fobj = reservation_object_get_list(resv); +- fence = reservation_object_get_excl(resv); +- +- if (fence && (!exclusive || !fobj || !fobj->shared_count)) { +- struct nouveau_channel *prev = NULL; +- bool must_wait = true; +- +- f = nouveau_local_fence(fence, chan->drm); +- if (f) { +- rcu_read_lock(); +- prev = rcu_dereference(f->channel); +- if (prev && (prev == chan || fctx->sync(f, prev, chan) == 0)) +- must_wait = false; +- rcu_read_unlock(); +- } +- +- if (must_wait) +- ret = fence_wait(fence, intr); +- +- return ret; +- } +- +- if (!exclusive || !fobj) +- return ret; +- +- for (i = 0; i < fobj->shared_count && !ret; ++i) { +- struct nouveau_channel *prev = NULL; +- bool must_wait = true; +- +- fence = rcu_dereference_protected(fobj->shared[i], +- reservation_object_held(resv)); +- +- f = nouveau_local_fence(fence, chan->drm); +- if (f) { +- rcu_read_lock(); +- prev = rcu_dereference(f->channel); +- if (prev && (prev == chan || fctx->sync(f, prev, chan) == 0)) +- must_wait = false; +- rcu_read_unlock(); +- } +- +- if (must_wait) +- ret = fence_wait(fence, intr); +- } +- +- return ret; +-} +- +-void +-nouveau_fence_unref(struct nouveau_fence **pfence) +-{ +- if (*pfence) +- fence_put(&(*pfence)->base); +- *pfence = NULL; +-} +- +-int +-nouveau_fence_new(struct nouveau_channel *chan, bool sysmem, +- struct nouveau_fence **pfence) +-{ +- struct nouveau_fence *fence; +- int ret = 0; +- +- if (unlikely(!chan->fence)) +- return -ENODEV; +- +- fence = kzalloc(sizeof(*fence), GFP_KERNEL); +- if (!fence) +- return -ENOMEM; +- +- fence->sysmem = sysmem; +- +- ret = nouveau_fence_emit(fence, chan); +- if (ret) +- nouveau_fence_unref(&fence); +- +- *pfence = fence; +- return ret; +-} +- +-static const char *nouveau_fence_get_get_driver_name(struct fence *fence) +-{ +- return "nouveau"; +-} +- +-static const char *nouveau_fence_get_timeline_name(struct fence *f) +-{ +- struct nouveau_fence *fence = from_fence(f); +- struct nouveau_fence_chan *fctx = nouveau_fctx(fence); +- +- return !fctx->dead ? fctx->name : "dead channel"; +-} +- +-/* +- * In an ideal world, read would not assume the channel context is still alive. +- * This function may be called from another device, running into free memory as a +- * result. The drm node should still be there, so we can derive the index from +- * the fence context. +- */ +-static bool nouveau_fence_is_signaled(struct fence *f) +-{ +- struct nouveau_fence *fence = from_fence(f); +- struct nouveau_fence_chan *fctx = nouveau_fctx(fence); +- struct nouveau_channel *chan; +- bool ret = false; +- +- rcu_read_lock(); +- chan = rcu_dereference(fence->channel); +- if (chan) +- ret = (int)(fctx->read(chan) - fence->base.seqno) >= 0; +- rcu_read_unlock(); +- +- return ret; +-} +- +-static bool nouveau_fence_no_signaling(struct fence *f) +-{ +- struct nouveau_fence *fence = from_fence(f); +- +- /* +- * caller should have a reference on the fence, +- * else fence could get freed here +- */ +- WARN_ON(atomic_read(&fence->base.refcount.refcount) <= 1); +- +- /* +- * This needs uevents to work correctly, but fence_add_callback relies on +- * being able to enable signaling. It will still get signaled eventually, +- * just not right away. +- */ +- if (nouveau_fence_is_signaled(f)) { +- list_del(&fence->head); +- +- fence_put(&fence->base); +- return false; +- } +- +- return true; +-} +- +-static void nouveau_fence_release(struct fence *f) +-{ +- struct nouveau_fence *fence = from_fence(f); +- struct nouveau_fence_chan *fctx = nouveau_fctx(fence); +- +- kref_put(&fctx->fence_ref, nouveau_fence_context_put); +- fence_free(&fence->base); +-} +- +-static const struct fence_ops nouveau_fence_ops_legacy = { +- .get_driver_name = nouveau_fence_get_get_driver_name, +- .get_timeline_name = nouveau_fence_get_timeline_name, +- .enable_signaling = nouveau_fence_no_signaling, +- .signaled = nouveau_fence_is_signaled, +- .wait = nouveau_fence_wait_legacy, +- .release = nouveau_fence_release +-}; +- +-static bool nouveau_fence_enable_signaling(struct fence *f) +-{ +- struct nouveau_fence *fence = from_fence(f); +- struct nouveau_fence_chan *fctx = nouveau_fctx(fence); +- bool ret; +- +- if (!fctx->notify_ref++) +- nvif_notify_get(&fctx->notify); +- +- ret = nouveau_fence_no_signaling(f); +- if (ret) +- set_bit(FENCE_FLAG_USER_BITS, &fence->base.flags); +- else if (!--fctx->notify_ref) +- nvif_notify_put(&fctx->notify); +- +- return ret; +-} +- +-static const struct fence_ops nouveau_fence_ops_uevent = { +- .get_driver_name = nouveau_fence_get_get_driver_name, +- .get_timeline_name = nouveau_fence_get_timeline_name, +- .enable_signaling = nouveau_fence_enable_signaling, +- .signaled = nouveau_fence_is_signaled, +- .wait = fence_default_wait, +- .release = NULL +-}; +diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.h b/drivers/gpu/drm/nouveau/nouveau_fence.h +deleted file mode 100644 +index 96e461c6..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_fence.h ++++ /dev/null +@@ -1,107 +0,0 @@ +-#ifndef __NOUVEAU_FENCE_H__ +-#define __NOUVEAU_FENCE_H__ +- +-#include +-#include +- +-struct nouveau_drm; +-struct nouveau_bo; +- +-struct nouveau_fence { +- struct fence base; +- +- struct list_head head; +- +- bool sysmem; +- +- struct nouveau_channel __rcu *channel; +- unsigned long timeout; +-}; +- +-int nouveau_fence_new(struct nouveau_channel *, bool sysmem, +- struct nouveau_fence **); +-void nouveau_fence_unref(struct nouveau_fence **); +- +-int nouveau_fence_emit(struct nouveau_fence *, struct nouveau_channel *); +-bool nouveau_fence_done(struct nouveau_fence *); +-void nouveau_fence_work(struct fence *, void (*)(void *), void *); +-int nouveau_fence_wait(struct nouveau_fence *, bool lazy, bool intr); +-int nouveau_fence_sync(struct nouveau_bo *, struct nouveau_channel *, bool exclusive, bool intr); +- +-struct nouveau_fence_chan { +- spinlock_t lock; +- struct kref fence_ref; +- +- struct list_head pending; +- struct list_head flip; +- +- int (*emit)(struct nouveau_fence *); +- int (*sync)(struct nouveau_fence *, struct nouveau_channel *, +- struct nouveau_channel *); +- u32 (*read)(struct nouveau_channel *); +- int (*emit32)(struct nouveau_channel *, u64, u32); +- int (*sync32)(struct nouveau_channel *, u64, u32); +- +- u32 sequence; +- u32 context; +- char name[32]; +- +- struct nvif_notify notify; +- int notify_ref, dead; +-}; +- +-struct nouveau_fence_priv { +- void (*dtor)(struct nouveau_drm *); +- bool (*suspend)(struct nouveau_drm *); +- void (*resume)(struct nouveau_drm *); +- int (*context_new)(struct nouveau_channel *); +- void (*context_del)(struct nouveau_channel *); +- +- u32 contexts, context_base; +- bool uevent; +-}; +- +-#define nouveau_fence(drm) ((struct nouveau_fence_priv *)(drm)->fence) +- +-void nouveau_fence_context_new(struct nouveau_channel *, struct nouveau_fence_chan *); +-void nouveau_fence_context_del(struct nouveau_fence_chan *); +-void nouveau_fence_context_free(struct nouveau_fence_chan *); +- +-int nv04_fence_create(struct nouveau_drm *); +-int nv04_fence_mthd(struct nouveau_channel *, u32, u32, u32); +- +-int nv10_fence_emit(struct nouveau_fence *); +-int nv17_fence_sync(struct nouveau_fence *, struct nouveau_channel *, +- struct nouveau_channel *); +-u32 nv10_fence_read(struct nouveau_channel *); +-void nv10_fence_context_del(struct nouveau_channel *); +-void nv10_fence_destroy(struct nouveau_drm *); +-int nv10_fence_create(struct nouveau_drm *); +- +-int nv17_fence_create(struct nouveau_drm *); +-void nv17_fence_resume(struct nouveau_drm *drm); +- +-int nv50_fence_create(struct nouveau_drm *); +-int nv84_fence_create(struct nouveau_drm *); +-int nvc0_fence_create(struct nouveau_drm *); +- +-int nouveau_flip_complete(void *chan); +- +-struct nv84_fence_chan { +- struct nouveau_fence_chan base; +- struct nouveau_vma vma; +- struct nouveau_vma vma_gart; +- struct nouveau_vma dispc_vma[4]; +-}; +- +-struct nv84_fence_priv { +- struct nouveau_fence_priv base; +- struct nouveau_bo *bo; +- struct nouveau_bo *bo_gart; +- u32 *suspend; +-}; +- +-u64 nv84_fence_crtc(struct nouveau_channel *, int); +-int nv84_fence_context_new(struct nouveau_channel *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c +deleted file mode 100644 +index 9fcc77d5..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_gem.c ++++ /dev/null +@@ -1,899 +0,0 @@ +-/* +- * Copyright (C) 2008 Ben Skeggs. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fence.h" +-#include "nouveau_abi16.h" +- +-#include "nouveau_ttm.h" +-#include "nouveau_gem.h" +- +-void +-nouveau_gem_object_del(struct drm_gem_object *gem) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(gem); +- struct ttm_buffer_object *bo = &nvbo->bo; +- +- if (gem->import_attach) +- drm_prime_gem_destroy(gem, nvbo->bo.sg); +- +- drm_gem_object_release(gem); +- +- /* reset filp so nouveau_bo_del_ttm() can test for it */ +- gem->filp = NULL; +- ttm_bo_unref(&bo); +-} +- +-int +-nouveau_gem_object_open(struct drm_gem_object *gem, struct drm_file *file_priv) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_bo *nvbo = nouveau_gem_object(gem); +- struct nouveau_vma *vma; +- int ret; +- +- if (!cli->vm) +- return 0; +- +- ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL); +- if (ret) +- return ret; +- +- vma = nouveau_bo_vma_find(nvbo, cli->vm); +- if (!vma) { +- vma = kzalloc(sizeof(*vma), GFP_KERNEL); +- if (!vma) { +- ret = -ENOMEM; +- goto out; +- } +- +- ret = nouveau_bo_vma_add(nvbo, cli->vm, vma); +- if (ret) { +- kfree(vma); +- goto out; +- } +- } else { +- vma->refcount++; +- } +- +-out: +- ttm_bo_unreserve(&nvbo->bo); +- return ret; +-} +- +-static void +-nouveau_gem_object_delete(void *data) +-{ +- struct nouveau_vma *vma = data; +- nouveau_vm_unmap(vma); +- nouveau_vm_put(vma); +- kfree(vma); +-} +- +-static void +-nouveau_gem_object_unmap(struct nouveau_bo *nvbo, struct nouveau_vma *vma) +-{ +- const bool mapped = nvbo->bo.mem.mem_type != TTM_PL_SYSTEM; +- struct reservation_object *resv = nvbo->bo.resv; +- struct reservation_object_list *fobj; +- struct fence *fence = NULL; +- +- fobj = reservation_object_get_list(resv); +- +- list_del(&vma->head); +- +- if (fobj && fobj->shared_count > 1) +- ttm_bo_wait(&nvbo->bo, true, false, false); +- else if (fobj && fobj->shared_count == 1) +- fence = rcu_dereference_protected(fobj->shared[0], +- reservation_object_held(resv)); +- else +- fence = reservation_object_get_excl(nvbo->bo.resv); +- +- if (fence && mapped) { +- nouveau_fence_work(fence, nouveau_gem_object_delete, vma); +- } else { +- if (mapped) +- nouveau_vm_unmap(vma); +- nouveau_vm_put(vma); +- kfree(vma); +- } +-} +- +-void +-nouveau_gem_object_close(struct drm_gem_object *gem, struct drm_file *file_priv) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_bo *nvbo = nouveau_gem_object(gem); +- struct nouveau_vma *vma; +- int ret; +- +- if (!cli->vm) +- return; +- +- ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL); +- if (ret) +- return; +- +- vma = nouveau_bo_vma_find(nvbo, cli->vm); +- if (vma) { +- if (--vma->refcount == 0) +- nouveau_gem_object_unmap(nvbo, vma); +- } +- ttm_bo_unreserve(&nvbo->bo); +-} +- +-int +-nouveau_gem_new(struct drm_device *dev, int size, int align, uint32_t domain, +- uint32_t tile_mode, uint32_t tile_flags, +- struct nouveau_bo **pnvbo) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_bo *nvbo; +- u32 flags = 0; +- int ret; +- +- if (domain & NOUVEAU_GEM_DOMAIN_VRAM) +- flags |= TTM_PL_FLAG_VRAM; +- if (domain & NOUVEAU_GEM_DOMAIN_GART) +- flags |= TTM_PL_FLAG_TT; +- if (!flags || domain & NOUVEAU_GEM_DOMAIN_CPU) +- flags |= TTM_PL_FLAG_SYSTEM; +- +- ret = nouveau_bo_new(dev, size, align, flags, tile_mode, +- tile_flags, NULL, NULL, pnvbo); +- if (ret) +- return ret; +- nvbo = *pnvbo; +- +- /* we restrict allowed domains on nv50+ to only the types +- * that were requested at creation time. not possibly on +- * earlier chips without busting the ABI. +- */ +- nvbo->valid_domains = NOUVEAU_GEM_DOMAIN_VRAM | +- NOUVEAU_GEM_DOMAIN_GART; +- if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) +- nvbo->valid_domains &= domain; +- +- /* Initialize the embedded gem-object. We return a single gem-reference +- * to the caller, instead of a normal nouveau_bo ttm reference. */ +- ret = drm_gem_object_init(dev, &nvbo->gem, nvbo->bo.mem.size); +- if (ret) { +- nouveau_bo_ref(NULL, pnvbo); +- return -ENOMEM; +- } +- +- nvbo->bo.persistent_swap_storage = nvbo->gem.filp; +- return 0; +-} +- +-static int +-nouveau_gem_info(struct drm_file *file_priv, struct drm_gem_object *gem, +- struct drm_nouveau_gem_info *rep) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_bo *nvbo = nouveau_gem_object(gem); +- struct nouveau_vma *vma; +- +- if (is_power_of_2(nvbo->valid_domains)) +- rep->domain = nvbo->valid_domains; +- else if (nvbo->bo.mem.mem_type == TTM_PL_TT) +- rep->domain = NOUVEAU_GEM_DOMAIN_GART; +- else +- rep->domain = NOUVEAU_GEM_DOMAIN_VRAM; +- rep->offset = nvbo->bo.offset; +- if (cli->vm) { +- vma = nouveau_bo_vma_find(nvbo, cli->vm); +- if (!vma) +- return -EINVAL; +- +- rep->offset = vma->offset; +- } +- +- rep->size = nvbo->bo.mem.num_pages << PAGE_SHIFT; +- rep->map_handle = drm_vma_node_offset_addr(&nvbo->bo.vma_node); +- rep->tile_mode = nvbo->tile_mode; +- rep->tile_flags = nvbo->tile_flags; +- return 0; +-} +- +-int +-nouveau_gem_ioctl_new(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_fb *pfb = nvkm_fb(&drm->device); +- struct drm_nouveau_gem_new *req = data; +- struct nouveau_bo *nvbo = NULL; +- int ret = 0; +- +- if (!pfb->memtype_valid(pfb, req->info.tile_flags)) { +- NV_PRINTK(error, cli, "bad page flags: 0x%08x\n", req->info.tile_flags); +- return -EINVAL; +- } +- +- ret = nouveau_gem_new(dev, req->info.size, req->align, +- req->info.domain, req->info.tile_mode, +- req->info.tile_flags, &nvbo); +- if (ret) +- return ret; +- +- ret = drm_gem_handle_create(file_priv, &nvbo->gem, &req->info.handle); +- if (ret == 0) { +- ret = nouveau_gem_info(file_priv, &nvbo->gem, &req->info); +- if (ret) +- drm_gem_handle_delete(file_priv, req->info.handle); +- } +- +- /* drop reference from allocate - handle holds it now */ +- drm_gem_object_unreference_unlocked(&nvbo->gem); +- return ret; +-} +- +-static int +-nouveau_gem_set_domain(struct drm_gem_object *gem, uint32_t read_domains, +- uint32_t write_domains, uint32_t valid_domains) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(gem); +- struct ttm_buffer_object *bo = &nvbo->bo; +- uint32_t domains = valid_domains & nvbo->valid_domains & +- (write_domains ? write_domains : read_domains); +- uint32_t pref_flags = 0, valid_flags = 0; +- +- if (!domains) +- return -EINVAL; +- +- if (valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) +- valid_flags |= TTM_PL_FLAG_VRAM; +- +- if (valid_domains & NOUVEAU_GEM_DOMAIN_GART) +- valid_flags |= TTM_PL_FLAG_TT; +- +- if ((domains & NOUVEAU_GEM_DOMAIN_VRAM) && +- bo->mem.mem_type == TTM_PL_VRAM) +- pref_flags |= TTM_PL_FLAG_VRAM; +- +- else if ((domains & NOUVEAU_GEM_DOMAIN_GART) && +- bo->mem.mem_type == TTM_PL_TT) +- pref_flags |= TTM_PL_FLAG_TT; +- +- else if (domains & NOUVEAU_GEM_DOMAIN_VRAM) +- pref_flags |= TTM_PL_FLAG_VRAM; +- +- else +- pref_flags |= TTM_PL_FLAG_TT; +- +- nouveau_bo_placement_set(nvbo, pref_flags, valid_flags); +- +- return 0; +-} +- +-struct validate_op { +- struct list_head list; +- struct ww_acquire_ctx ticket; +-}; +- +-static void +-validate_fini_no_ticket(struct validate_op *op, struct nouveau_fence *fence, +- struct drm_nouveau_gem_pushbuf_bo *pbbo) +-{ +- struct nouveau_bo *nvbo; +- struct drm_nouveau_gem_pushbuf_bo *b; +- +- while (!list_empty(&op->list)) { +- nvbo = list_entry(op->list.next, struct nouveau_bo, entry); +- b = &pbbo[nvbo->pbbo_index]; +- +- if (likely(fence)) +- nouveau_bo_fence(nvbo, fence, !!b->write_domains); +- +- if (unlikely(nvbo->validate_mapped)) { +- ttm_bo_kunmap(&nvbo->kmap); +- nvbo->validate_mapped = false; +- } +- +- list_del(&nvbo->entry); +- nvbo->reserved_by = NULL; +- ttm_bo_unreserve_ticket(&nvbo->bo, &op->ticket); +- drm_gem_object_unreference_unlocked(&nvbo->gem); +- } +-} +- +-static void +-validate_fini(struct validate_op *op, struct nouveau_fence *fence, +- struct drm_nouveau_gem_pushbuf_bo *pbbo) +-{ +- validate_fini_no_ticket(op, fence, pbbo); +- ww_acquire_fini(&op->ticket); +-} +- +-static int +-validate_init(struct nouveau_channel *chan, struct drm_file *file_priv, +- struct drm_nouveau_gem_pushbuf_bo *pbbo, +- int nr_buffers, struct validate_op *op) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct drm_device *dev = chan->drm->dev; +- int trycnt = 0; +- int ret, i; +- struct nouveau_bo *res_bo = NULL; +- LIST_HEAD(gart_list); +- LIST_HEAD(vram_list); +- LIST_HEAD(both_list); +- +- ww_acquire_init(&op->ticket, &reservation_ww_class); +-retry: +- if (++trycnt > 100000) { +- NV_PRINTK(error, cli, "%s failed and gave up.\n", __func__); +- return -EINVAL; +- } +- +- for (i = 0; i < nr_buffers; i++) { +- struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[i]; +- struct drm_gem_object *gem; +- struct nouveau_bo *nvbo; +- +- gem = drm_gem_object_lookup(dev, file_priv, b->handle); +- if (!gem) { +- NV_PRINTK(error, cli, "Unknown handle 0x%08x\n", b->handle); +- ret = -ENOENT; +- break; +- } +- nvbo = nouveau_gem_object(gem); +- if (nvbo == res_bo) { +- res_bo = NULL; +- drm_gem_object_unreference_unlocked(gem); +- continue; +- } +- +- if (nvbo->reserved_by && nvbo->reserved_by == file_priv) { +- NV_PRINTK(error, cli, "multiple instances of buffer %d on " +- "validation list\n", b->handle); +- drm_gem_object_unreference_unlocked(gem); +- ret = -EINVAL; +- break; +- } +- +- ret = ttm_bo_reserve(&nvbo->bo, true, false, true, &op->ticket); +- if (ret) { +- list_splice_tail_init(&vram_list, &op->list); +- list_splice_tail_init(&gart_list, &op->list); +- list_splice_tail_init(&both_list, &op->list); +- validate_fini_no_ticket(op, NULL, NULL); +- if (unlikely(ret == -EDEADLK)) { +- ret = ttm_bo_reserve_slowpath(&nvbo->bo, true, +- &op->ticket); +- if (!ret) +- res_bo = nvbo; +- } +- if (unlikely(ret)) { +- if (ret != -ERESTARTSYS) +- NV_PRINTK(error, cli, "fail reserve\n"); +- break; +- } +- } +- +- b->user_priv = (uint64_t)(unsigned long)nvbo; +- nvbo->reserved_by = file_priv; +- nvbo->pbbo_index = i; +- if ((b->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) && +- (b->valid_domains & NOUVEAU_GEM_DOMAIN_GART)) +- list_add_tail(&nvbo->entry, &both_list); +- else +- if (b->valid_domains & NOUVEAU_GEM_DOMAIN_VRAM) +- list_add_tail(&nvbo->entry, &vram_list); +- else +- if (b->valid_domains & NOUVEAU_GEM_DOMAIN_GART) +- list_add_tail(&nvbo->entry, &gart_list); +- else { +- NV_PRINTK(error, cli, "invalid valid domains: 0x%08x\n", +- b->valid_domains); +- list_add_tail(&nvbo->entry, &both_list); +- ret = -EINVAL; +- break; +- } +- if (nvbo == res_bo) +- goto retry; +- } +- +- ww_acquire_done(&op->ticket); +- list_splice_tail(&vram_list, &op->list); +- list_splice_tail(&gart_list, &op->list); +- list_splice_tail(&both_list, &op->list); +- if (ret) +- validate_fini(op, NULL, NULL); +- return ret; +- +-} +- +-static int +-validate_list(struct nouveau_channel *chan, struct nouveau_cli *cli, +- struct list_head *list, struct drm_nouveau_gem_pushbuf_bo *pbbo, +- uint64_t user_pbbo_ptr) +-{ +- struct nouveau_drm *drm = chan->drm; +- struct drm_nouveau_gem_pushbuf_bo __user *upbbo = +- (void __force __user *)(uintptr_t)user_pbbo_ptr; +- struct nouveau_bo *nvbo; +- int ret, relocs = 0; +- +- list_for_each_entry(nvbo, list, entry) { +- struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index]; +- +- ret = nouveau_gem_set_domain(&nvbo->gem, b->read_domains, +- b->write_domains, +- b->valid_domains); +- if (unlikely(ret)) { +- NV_PRINTK(error, cli, "fail set_domain\n"); +- return ret; +- } +- +- ret = nouveau_bo_validate(nvbo, true, false); +- if (unlikely(ret)) { +- if (ret != -ERESTARTSYS) +- NV_PRINTK(error, cli, "fail ttm_validate\n"); +- return ret; +- } +- +- ret = nouveau_fence_sync(nvbo, chan, !!b->write_domains, true); +- if (unlikely(ret)) { +- if (ret != -ERESTARTSYS) +- NV_PRINTK(error, cli, "fail post-validate sync\n"); +- return ret; +- } +- +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { +- if (nvbo->bo.offset == b->presumed.offset && +- ((nvbo->bo.mem.mem_type == TTM_PL_VRAM && +- b->presumed.domain & NOUVEAU_GEM_DOMAIN_VRAM) || +- (nvbo->bo.mem.mem_type == TTM_PL_TT && +- b->presumed.domain & NOUVEAU_GEM_DOMAIN_GART))) +- continue; +- +- if (nvbo->bo.mem.mem_type == TTM_PL_TT) +- b->presumed.domain = NOUVEAU_GEM_DOMAIN_GART; +- else +- b->presumed.domain = NOUVEAU_GEM_DOMAIN_VRAM; +- b->presumed.offset = nvbo->bo.offset; +- b->presumed.valid = 0; +- relocs++; +- +- if (copy_to_user(&upbbo[nvbo->pbbo_index].presumed, +- &b->presumed, sizeof(b->presumed))) +- return -EFAULT; +- } +- } +- +- return relocs; +-} +- +-static int +-nouveau_gem_pushbuf_validate(struct nouveau_channel *chan, +- struct drm_file *file_priv, +- struct drm_nouveau_gem_pushbuf_bo *pbbo, +- uint64_t user_buffers, int nr_buffers, +- struct validate_op *op, int *apply_relocs) +-{ +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- int ret; +- +- INIT_LIST_HEAD(&op->list); +- +- if (nr_buffers == 0) +- return 0; +- +- ret = validate_init(chan, file_priv, pbbo, nr_buffers, op); +- if (unlikely(ret)) { +- if (ret != -ERESTARTSYS) +- NV_PRINTK(error, cli, "validate_init\n"); +- return ret; +- } +- +- ret = validate_list(chan, cli, &op->list, pbbo, user_buffers); +- if (unlikely(ret < 0)) { +- if (ret != -ERESTARTSYS) +- NV_PRINTK(error, cli, "validating bo list\n"); +- validate_fini(op, NULL, NULL); +- return ret; +- } +- *apply_relocs = ret; +- return 0; +-} +- +-static inline void +-u_free(void *addr) +-{ +- if (!is_vmalloc_addr(addr)) +- kfree(addr); +- else +- vfree(addr); +-} +- +-static inline void * +-u_memcpya(uint64_t user, unsigned nmemb, unsigned size) +-{ +- void *mem; +- void __user *userptr = (void __force __user *)(uintptr_t)user; +- +- size *= nmemb; +- +- mem = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); +- if (!mem) +- mem = vmalloc(size); +- if (!mem) +- return ERR_PTR(-ENOMEM); +- +- if (copy_from_user(mem, userptr, size)) { +- u_free(mem); +- return ERR_PTR(-EFAULT); +- } +- +- return mem; +-} +- +-static int +-nouveau_gem_pushbuf_reloc_apply(struct nouveau_cli *cli, +- struct drm_nouveau_gem_pushbuf *req, +- struct drm_nouveau_gem_pushbuf_bo *bo) +-{ +- struct drm_nouveau_gem_pushbuf_reloc *reloc = NULL; +- int ret = 0; +- unsigned i; +- +- reloc = u_memcpya(req->relocs, req->nr_relocs, sizeof(*reloc)); +- if (IS_ERR(reloc)) +- return PTR_ERR(reloc); +- +- for (i = 0; i < req->nr_relocs; i++) { +- struct drm_nouveau_gem_pushbuf_reloc *r = &reloc[i]; +- struct drm_nouveau_gem_pushbuf_bo *b; +- struct nouveau_bo *nvbo; +- uint32_t data; +- +- if (unlikely(r->bo_index > req->nr_buffers)) { +- NV_PRINTK(error, cli, "reloc bo index invalid\n"); +- ret = -EINVAL; +- break; +- } +- +- b = &bo[r->bo_index]; +- if (b->presumed.valid) +- continue; +- +- if (unlikely(r->reloc_bo_index > req->nr_buffers)) { +- NV_PRINTK(error, cli, "reloc container bo index invalid\n"); +- ret = -EINVAL; +- break; +- } +- nvbo = (void *)(unsigned long)bo[r->reloc_bo_index].user_priv; +- +- if (unlikely(r->reloc_bo_offset + 4 > +- nvbo->bo.mem.num_pages << PAGE_SHIFT)) { +- NV_PRINTK(error, cli, "reloc outside of bo\n"); +- ret = -EINVAL; +- break; +- } +- +- if (!nvbo->kmap.virtual) { +- ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, +- &nvbo->kmap); +- if (ret) { +- NV_PRINTK(error, cli, "failed kmap for reloc\n"); +- break; +- } +- nvbo->validate_mapped = true; +- } +- +- if (r->flags & NOUVEAU_GEM_RELOC_LOW) +- data = b->presumed.offset + r->data; +- else +- if (r->flags & NOUVEAU_GEM_RELOC_HIGH) +- data = (b->presumed.offset + r->data) >> 32; +- else +- data = r->data; +- +- if (r->flags & NOUVEAU_GEM_RELOC_OR) { +- if (b->presumed.domain == NOUVEAU_GEM_DOMAIN_GART) +- data |= r->tor; +- else +- data |= r->vor; +- } +- +- ret = ttm_bo_wait(&nvbo->bo, true, false, false); +- if (ret) { +- NV_PRINTK(error, cli, "reloc wait_idle failed: %d\n", ret); +- break; +- } +- +- nouveau_bo_wr32(nvbo, r->reloc_bo_offset >> 2, data); +- } +- +- u_free(reloc); +- return ret; +-} +- +-int +-nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); +- struct nouveau_cli *cli = nouveau_cli(file_priv); +- struct nouveau_abi16_chan *temp; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct drm_nouveau_gem_pushbuf *req = data; +- struct drm_nouveau_gem_pushbuf_push *push; +- struct drm_nouveau_gem_pushbuf_bo *bo; +- struct nouveau_channel *chan = NULL; +- struct validate_op op; +- struct nouveau_fence *fence = NULL; +- int i, j, ret = 0, do_reloc = 0; +- +- if (unlikely(!abi16)) +- return -ENOMEM; +- +- list_for_each_entry(temp, &abi16->channels, head) { +- if (temp->chan->object->handle == (NVDRM_CHAN | req->channel)) { +- chan = temp->chan; +- break; +- } +- } +- +- if (!chan) +- return nouveau_abi16_put(abi16, -ENOENT); +- +- req->vram_available = drm->gem.vram_available; +- req->gart_available = drm->gem.gart_available; +- if (unlikely(req->nr_push == 0)) +- goto out_next; +- +- if (unlikely(req->nr_push > NOUVEAU_GEM_MAX_PUSH)) { +- NV_PRINTK(error, cli, "pushbuf push count exceeds limit: %d max %d\n", +- req->nr_push, NOUVEAU_GEM_MAX_PUSH); +- return nouveau_abi16_put(abi16, -EINVAL); +- } +- +- if (unlikely(req->nr_buffers > NOUVEAU_GEM_MAX_BUFFERS)) { +- NV_PRINTK(error, cli, "pushbuf bo count exceeds limit: %d max %d\n", +- req->nr_buffers, NOUVEAU_GEM_MAX_BUFFERS); +- return nouveau_abi16_put(abi16, -EINVAL); +- } +- +- if (unlikely(req->nr_relocs > NOUVEAU_GEM_MAX_RELOCS)) { +- NV_PRINTK(error, cli, "pushbuf reloc count exceeds limit: %d max %d\n", +- req->nr_relocs, NOUVEAU_GEM_MAX_RELOCS); +- return nouveau_abi16_put(abi16, -EINVAL); +- } +- +- push = u_memcpya(req->push, req->nr_push, sizeof(*push)); +- if (IS_ERR(push)) +- return nouveau_abi16_put(abi16, PTR_ERR(push)); +- +- bo = u_memcpya(req->buffers, req->nr_buffers, sizeof(*bo)); +- if (IS_ERR(bo)) { +- u_free(push); +- return nouveau_abi16_put(abi16, PTR_ERR(bo)); +- } +- +- /* Ensure all push buffers are on validate list */ +- for (i = 0; i < req->nr_push; i++) { +- if (push[i].bo_index >= req->nr_buffers) { +- NV_PRINTK(error, cli, "push %d buffer not in list\n", i); +- ret = -EINVAL; +- goto out_prevalid; +- } +- } +- +- /* Validate buffer list */ +- ret = nouveau_gem_pushbuf_validate(chan, file_priv, bo, req->buffers, +- req->nr_buffers, &op, &do_reloc); +- if (ret) { +- if (ret != -ERESTARTSYS) +- NV_PRINTK(error, cli, "validate: %d\n", ret); +- goto out_prevalid; +- } +- +- /* Apply any relocations that are required */ +- if (do_reloc) { +- ret = nouveau_gem_pushbuf_reloc_apply(cli, req, bo); +- if (ret) { +- NV_PRINTK(error, cli, "reloc apply: %d\n", ret); +- goto out; +- } +- } +- +- if (chan->dma.ib_max) { +- ret = nouveau_dma_wait(chan, req->nr_push + 1, 16); +- if (ret) { +- NV_PRINTK(error, cli, "nv50cal_space: %d\n", ret); +- goto out; +- } +- +- for (i = 0; i < req->nr_push; i++) { +- struct nouveau_bo *nvbo = (void *)(unsigned long) +- bo[push[i].bo_index].user_priv; +- +- nv50_dma_push(chan, nvbo, push[i].offset, +- push[i].length); +- } +- } else +- if (drm->device.info.chipset >= 0x25) { +- ret = RING_SPACE(chan, req->nr_push * 2); +- if (ret) { +- NV_PRINTK(error, cli, "cal_space: %d\n", ret); +- goto out; +- } +- +- for (i = 0; i < req->nr_push; i++) { +- struct nouveau_bo *nvbo = (void *)(unsigned long) +- bo[push[i].bo_index].user_priv; +- +- OUT_RING(chan, (nvbo->bo.offset + push[i].offset) | 2); +- OUT_RING(chan, 0); +- } +- } else { +- ret = RING_SPACE(chan, req->nr_push * (2 + NOUVEAU_DMA_SKIPS)); +- if (ret) { +- NV_PRINTK(error, cli, "jmp_space: %d\n", ret); +- goto out; +- } +- +- for (i = 0; i < req->nr_push; i++) { +- struct nouveau_bo *nvbo = (void *)(unsigned long) +- bo[push[i].bo_index].user_priv; +- uint32_t cmd; +- +- cmd = chan->push.vma.offset + ((chan->dma.cur + 2) << 2); +- cmd |= 0x20000000; +- if (unlikely(cmd != req->suffix0)) { +- if (!nvbo->kmap.virtual) { +- ret = ttm_bo_kmap(&nvbo->bo, 0, +- nvbo->bo.mem. +- num_pages, +- &nvbo->kmap); +- if (ret) { +- WIND_RING(chan); +- goto out; +- } +- nvbo->validate_mapped = true; +- } +- +- nouveau_bo_wr32(nvbo, (push[i].offset + +- push[i].length - 8) / 4, cmd); +- } +- +- OUT_RING(chan, 0x20000000 | +- (nvbo->bo.offset + push[i].offset)); +- OUT_RING(chan, 0); +- for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) +- OUT_RING(chan, 0); +- } +- } +- +- ret = nouveau_fence_new(chan, false, &fence); +- if (ret) { +- NV_PRINTK(error, cli, "error fencing pushbuf: %d\n", ret); +- WIND_RING(chan); +- goto out; +- } +- +-out: +- validate_fini(&op, fence, bo); +- nouveau_fence_unref(&fence); +- +-out_prevalid: +- u_free(bo); +- u_free(push); +- +-out_next: +- if (chan->dma.ib_max) { +- req->suffix0 = 0x00000000; +- req->suffix1 = 0x00000000; +- } else +- if (drm->device.info.chipset >= 0x25) { +- req->suffix0 = 0x00020000; +- req->suffix1 = 0x00000000; +- } else { +- req->suffix0 = 0x20000000 | +- (chan->push.vma.offset + ((chan->dma.cur + 2) << 2)); +- req->suffix1 = 0x00000000; +- } +- +- return nouveau_abi16_put(abi16, ret); +-} +- +-static inline uint32_t +-domain_to_ttm(struct nouveau_bo *nvbo, uint32_t domain) +-{ +- uint32_t flags = 0; +- +- if (domain & NOUVEAU_GEM_DOMAIN_VRAM) +- flags |= TTM_PL_FLAG_VRAM; +- if (domain & NOUVEAU_GEM_DOMAIN_GART) +- flags |= TTM_PL_FLAG_TT; +- +- return flags; +-} +- +-int +-nouveau_gem_ioctl_cpu_prep(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- struct drm_nouveau_gem_cpu_prep *req = data; +- struct drm_gem_object *gem; +- struct nouveau_bo *nvbo; +- bool no_wait = !!(req->flags & NOUVEAU_GEM_CPU_PREP_NOWAIT); +- bool write = !!(req->flags & NOUVEAU_GEM_CPU_PREP_WRITE); +- int ret; +- +- gem = drm_gem_object_lookup(dev, file_priv, req->handle); +- if (!gem) +- return -ENOENT; +- nvbo = nouveau_gem_object(gem); +- +- if (no_wait) +- ret = reservation_object_test_signaled_rcu(nvbo->bo.resv, write) ? 0 : -EBUSY; +- else { +- long lret; +- +- lret = reservation_object_wait_timeout_rcu(nvbo->bo.resv, write, true, 30 * HZ); +- if (!lret) +- ret = -EBUSY; +- else if (lret > 0) +- ret = 0; +- else +- ret = lret; +- } +- drm_gem_object_unreference_unlocked(gem); +- +- return ret; +-} +- +-int +-nouveau_gem_ioctl_cpu_fini(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- return 0; +-} +- +-int +-nouveau_gem_ioctl_info(struct drm_device *dev, void *data, +- struct drm_file *file_priv) +-{ +- struct drm_nouveau_gem_info *req = data; +- struct drm_gem_object *gem; +- int ret; +- +- gem = drm_gem_object_lookup(dev, file_priv, req->handle); +- if (!gem) +- return -ENOENT; +- +- ret = nouveau_gem_info(file_priv, gem, req); +- drm_gem_object_unreference_unlocked(gem); +- return ret; +-} +- +diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h +deleted file mode 100644 +index e4049fac..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_gem.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-#ifndef __NOUVEAU_GEM_H__ +-#define __NOUVEAU_GEM_H__ +- +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_bo.h" +- +-#define nouveau_bo_tile_layout(nvbo) \ +- ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) +- +-static inline struct nouveau_bo * +-nouveau_gem_object(struct drm_gem_object *gem) +-{ +- return gem ? container_of(gem, struct nouveau_bo, gem) : NULL; +-} +- +-/* nouveau_gem.c */ +-extern int nouveau_gem_new(struct drm_device *, int size, int align, +- uint32_t domain, uint32_t tile_mode, +- uint32_t tile_flags, struct nouveau_bo **); +-extern void nouveau_gem_object_del(struct drm_gem_object *); +-extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); +-extern void nouveau_gem_object_close(struct drm_gem_object *, +- struct drm_file *); +-extern int nouveau_gem_ioctl_new(struct drm_device *, void *, +- struct drm_file *); +-extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, +- struct drm_file *); +-extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, +- struct drm_file *); +-extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, +- struct drm_file *); +-extern int nouveau_gem_ioctl_info(struct drm_device *, void *, +- struct drm_file *); +- +-extern int nouveau_gem_prime_pin(struct drm_gem_object *); +-struct reservation_object *nouveau_gem_prime_res_obj(struct drm_gem_object *); +-extern void nouveau_gem_prime_unpin(struct drm_gem_object *); +-extern struct sg_table *nouveau_gem_prime_get_sg_table(struct drm_gem_object *); +-extern struct drm_gem_object *nouveau_gem_prime_import_sg_table( +- struct drm_device *, struct dma_buf_attachment *, struct sg_table *); +-extern void *nouveau_gem_prime_vmap(struct drm_gem_object *); +-extern void nouveau_gem_prime_vunmap(struct drm_gem_object *, void *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c +deleted file mode 100644 +index afb36d66..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c ++++ /dev/null +@@ -1,648 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifdef CONFIG_ACPI +-#include +-#endif +-#include +-#include +-#include +- +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_hwmon.h" +- +-#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) +-static ssize_t +-nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- int temp = therm->temp_get(therm); +- +- if (temp < 0) +- return temp; +- +- return snprintf(buf, PAGE_SIZE, "%d\n", temp * 1000); +-} +-static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, nouveau_hwmon_show_temp, +- NULL, 0); +- +-static ssize_t +-nouveau_hwmon_show_temp1_auto_point1_pwm(struct device *d, +- struct device_attribute *a, char *buf) +-{ +- return snprintf(buf, PAGE_SIZE, "%d\n", 100); +-} +-static SENSOR_DEVICE_ATTR(temp1_auto_point1_pwm, S_IRUGO, +- nouveau_hwmon_show_temp1_auto_point1_pwm, NULL, 0); +- +-static ssize_t +-nouveau_hwmon_temp1_auto_point1_temp(struct device *d, +- struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_temp1_auto_point1_temp(struct device *d, +- struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST, +- value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_auto_point1_temp, S_IRUGO | S_IWUSR, +- nouveau_hwmon_temp1_auto_point1_temp, +- nouveau_hwmon_set_temp1_auto_point1_temp, 0); +- +-static ssize_t +-nouveau_hwmon_temp1_auto_point1_temp_hyst(struct device *d, +- struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_temp1_auto_point1_temp_hyst(struct device *d, +- struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_FAN_BOOST_HYST, +- value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR, +- nouveau_hwmon_temp1_auto_point1_temp_hyst, +- nouveau_hwmon_set_temp1_auto_point1_temp_hyst, 0); +- +-static ssize_t +-nouveau_hwmon_max_temp(struct device *d, struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK, value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO | S_IWUSR, nouveau_hwmon_max_temp, +- nouveau_hwmon_set_max_temp, +- 0); +- +-static ssize_t +-nouveau_hwmon_max_temp_hyst(struct device *d, struct device_attribute *a, +- char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_max_temp_hyst(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_DOWN_CLK_HYST, +- value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO | S_IWUSR, +- nouveau_hwmon_max_temp_hyst, +- nouveau_hwmon_set_max_temp_hyst, 0); +- +-static ssize_t +-nouveau_hwmon_critical_temp(struct device *d, struct device_attribute *a, +- char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, +- const char *buf, +- size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL, value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO | S_IWUSR, +- nouveau_hwmon_critical_temp, +- nouveau_hwmon_set_critical_temp, +- 0); +- +-static ssize_t +-nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a, +- char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_critical_temp_hyst(struct device *d, +- struct device_attribute *a, +- const char *buf, +- size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_CRITICAL_HYST, +- value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO | S_IWUSR, +- nouveau_hwmon_critical_temp_hyst, +- nouveau_hwmon_set_critical_temp_hyst, 0); +-static ssize_t +-nouveau_hwmon_emergency_temp(struct device *d, struct device_attribute *a, +- char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_emergency_temp(struct device *d, struct device_attribute *a, +- const char *buf, +- size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN, value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO | S_IWUSR, +- nouveau_hwmon_emergency_temp, +- nouveau_hwmon_set_emergency_temp, +- 0); +- +-static ssize_t +-nouveau_hwmon_emergency_temp_hyst(struct device *d, struct device_attribute *a, +- char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", +- therm->attr_get(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST) * 1000); +-} +-static ssize_t +-nouveau_hwmon_set_emergency_temp_hyst(struct device *d, +- struct device_attribute *a, +- const char *buf, +- size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return count; +- +- therm->attr_set(therm, NOUVEAU_THERM_ATTR_THRS_SHUTDOWN_HYST, +- value / 1000); +- +- return count; +-} +-static SENSOR_DEVICE_ATTR(temp1_emergency_hyst, S_IRUGO | S_IWUSR, +- nouveau_hwmon_emergency_temp_hyst, +- nouveau_hwmon_set_emergency_temp_hyst, +- 0); +- +-static ssize_t nouveau_hwmon_show_name(struct device *dev, +- struct device_attribute *attr, +- char *buf) +-{ +- return sprintf(buf, "nouveau\n"); +-} +-static SENSOR_DEVICE_ATTR(name, S_IRUGO, nouveau_hwmon_show_name, NULL, 0); +- +-static ssize_t nouveau_hwmon_show_update_rate(struct device *dev, +- struct device_attribute *attr, +- char *buf) +-{ +- return sprintf(buf, "1000\n"); +-} +-static SENSOR_DEVICE_ATTR(update_rate, S_IRUGO, +- nouveau_hwmon_show_update_rate, +- NULL, 0); +- +-static ssize_t +-nouveau_hwmon_show_fan1_input(struct device *d, struct device_attribute *attr, +- char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- +- return snprintf(buf, PAGE_SIZE, "%d\n", therm->fan_sense(therm)); +-} +-static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, nouveau_hwmon_show_fan1_input, +- NULL, 0); +- +- static ssize_t +-nouveau_hwmon_get_pwm1_enable(struct device *d, +- struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- int ret; +- +- ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MODE); +- if (ret < 0) +- return ret; +- +- return sprintf(buf, "%i\n", ret); +-} +- +-static ssize_t +-nouveau_hwmon_set_pwm1_enable(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- int ret; +- +- ret = kstrtol(buf, 10, &value); +- if (ret) +- return ret; +- +- ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MODE, value); +- if (ret) +- return ret; +- else +- return count; +-} +-static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, +- nouveau_hwmon_get_pwm1_enable, +- nouveau_hwmon_set_pwm1_enable, 0); +- +-static ssize_t +-nouveau_hwmon_get_pwm1(struct device *d, struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- int ret; +- +- ret = therm->fan_get(therm); +- if (ret < 0) +- return ret; +- +- return sprintf(buf, "%i\n", ret); +-} +- +-static ssize_t +-nouveau_hwmon_set_pwm1(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- int ret = -ENODEV; +- long value; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return -EINVAL; +- +- ret = therm->fan_set(therm, value); +- if (ret) +- return ret; +- +- return count; +-} +- +-static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, +- nouveau_hwmon_get_pwm1, +- nouveau_hwmon_set_pwm1, 0); +- +-static ssize_t +-nouveau_hwmon_get_pwm1_min(struct device *d, +- struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- int ret; +- +- ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY); +- if (ret < 0) +- return ret; +- +- return sprintf(buf, "%i\n", ret); +-} +- +-static ssize_t +-nouveau_hwmon_set_pwm1_min(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- int ret; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return -EINVAL; +- +- ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MIN_DUTY, value); +- if (ret < 0) +- return ret; +- +- return count; +-} +- +-static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO | S_IWUSR, +- nouveau_hwmon_get_pwm1_min, +- nouveau_hwmon_set_pwm1_min, 0); +- +-static ssize_t +-nouveau_hwmon_get_pwm1_max(struct device *d, +- struct device_attribute *a, char *buf) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- int ret; +- +- ret = therm->attr_get(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY); +- if (ret < 0) +- return ret; +- +- return sprintf(buf, "%i\n", ret); +-} +- +-static ssize_t +-nouveau_hwmon_set_pwm1_max(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct drm_device *dev = dev_get_drvdata(d); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- long value; +- int ret; +- +- if (kstrtol(buf, 10, &value) == -EINVAL) +- return -EINVAL; +- +- ret = therm->attr_set(therm, NOUVEAU_THERM_ATTR_FAN_MAX_DUTY, value); +- if (ret < 0) +- return ret; +- +- return count; +-} +- +-static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO | S_IWUSR, +- nouveau_hwmon_get_pwm1_max, +- nouveau_hwmon_set_pwm1_max, 0); +- +-static struct attribute *hwmon_default_attributes[] = { +- &sensor_dev_attr_name.dev_attr.attr, +- &sensor_dev_attr_update_rate.dev_attr.attr, +- NULL +-}; +-static struct attribute *hwmon_temp_attributes[] = { +- &sensor_dev_attr_temp1_input.dev_attr.attr, +- &sensor_dev_attr_temp1_auto_point1_pwm.dev_attr.attr, +- &sensor_dev_attr_temp1_auto_point1_temp.dev_attr.attr, +- &sensor_dev_attr_temp1_auto_point1_temp_hyst.dev_attr.attr, +- &sensor_dev_attr_temp1_max.dev_attr.attr, +- &sensor_dev_attr_temp1_max_hyst.dev_attr.attr, +- &sensor_dev_attr_temp1_crit.dev_attr.attr, +- &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, +- &sensor_dev_attr_temp1_emergency.dev_attr.attr, +- &sensor_dev_attr_temp1_emergency_hyst.dev_attr.attr, +- NULL +-}; +-static struct attribute *hwmon_fan_rpm_attributes[] = { +- &sensor_dev_attr_fan1_input.dev_attr.attr, +- NULL +-}; +-static struct attribute *hwmon_pwm_fan_attributes[] = { +- &sensor_dev_attr_pwm1_enable.dev_attr.attr, +- &sensor_dev_attr_pwm1.dev_attr.attr, +- &sensor_dev_attr_pwm1_min.dev_attr.attr, +- &sensor_dev_attr_pwm1_max.dev_attr.attr, +- NULL +-}; +- +-static const struct attribute_group hwmon_default_attrgroup = { +- .attrs = hwmon_default_attributes, +-}; +-static const struct attribute_group hwmon_temp_attrgroup = { +- .attrs = hwmon_temp_attributes, +-}; +-static const struct attribute_group hwmon_fan_rpm_attrgroup = { +- .attrs = hwmon_fan_rpm_attributes, +-}; +-static const struct attribute_group hwmon_pwm_fan_attrgroup = { +- .attrs = hwmon_pwm_fan_attributes, +-}; +-#endif +- +-int +-nouveau_hwmon_init(struct drm_device *dev) +-{ +-#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_therm *therm = nvkm_therm(&drm->device); +- struct nouveau_hwmon *hwmon; +- struct device *hwmon_dev; +- int ret = 0; +- +- hwmon = drm->hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL); +- if (!hwmon) +- return -ENOMEM; +- hwmon->dev = dev; +- +- if (!therm || !therm->temp_get || !therm->attr_get || !therm->attr_set) +- return -ENODEV; +- +- hwmon_dev = hwmon_device_register(&dev->pdev->dev); +- if (IS_ERR(hwmon_dev)) { +- ret = PTR_ERR(hwmon_dev); +- NV_ERROR(drm, "Unable to register hwmon device: %d\n", ret); +- return ret; +- } +- dev_set_drvdata(hwmon_dev, dev); +- +- /* set the default attributes */ +- ret = sysfs_create_group(&hwmon_dev->kobj, &hwmon_default_attrgroup); +- if (ret) +- goto error; +- +- /* if the card has a working thermal sensor */ +- if (therm->temp_get(therm) >= 0) { +- ret = sysfs_create_group(&hwmon_dev->kobj, &hwmon_temp_attrgroup); +- if (ret) +- goto error; +- } +- +- /* if the card has a pwm fan */ +- /*XXX: incorrect, need better detection for this, some boards have +- * the gpio entries for pwm fan control even when there's no +- * actual fan connected to it... therm table? */ +- if (therm->fan_get && therm->fan_get(therm) >= 0) { +- ret = sysfs_create_group(&hwmon_dev->kobj, +- &hwmon_pwm_fan_attrgroup); +- if (ret) +- goto error; +- } +- +- /* if the card can read the fan rpm */ +- if (therm->fan_sense(therm) >= 0) { +- ret = sysfs_create_group(&hwmon_dev->kobj, +- &hwmon_fan_rpm_attrgroup); +- if (ret) +- goto error; +- } +- +- hwmon->hwmon = hwmon_dev; +- +- return 0; +- +-error: +- NV_ERROR(drm, "Unable to create some hwmon sysfs files: %d\n", ret); +- hwmon_device_unregister(hwmon_dev); +- hwmon->hwmon = NULL; +- return ret; +-#else +- return 0; +-#endif +-} +- +-void +-nouveau_hwmon_fini(struct drm_device *dev) +-{ +-#if defined(CONFIG_HWMON) || (defined(MODULE) && defined(CONFIG_HWMON_MODULE)) +- struct nouveau_hwmon *hwmon = nouveau_hwmon(dev); +- +- if (hwmon->hwmon) { +- sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_default_attrgroup); +- sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_temp_attrgroup); +- sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_pwm_fan_attrgroup); +- sysfs_remove_group(&hwmon->hwmon->kobj, &hwmon_fan_rpm_attrgroup); +- +- hwmon_device_unregister(hwmon->hwmon); +- } +- +- nouveau_drm(dev)->hwmon = NULL; +- kfree(hwmon); +-#endif +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.h b/drivers/gpu/drm/nouveau/nouveau_hwmon.h +deleted file mode 100644 +index 62ccbb39..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_hwmon.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#ifndef __NOUVEAU_PM_H__ +-#define __NOUVEAU_PM_H__ +- +-struct nouveau_hwmon { +- struct drm_device *dev; +- struct device *hwmon; +-}; +- +-static inline struct nouveau_hwmon * +-nouveau_hwmon(struct drm_device *dev) +-{ +- return nouveau_drm(dev)->hwmon; +-} +- +-/* nouveau_hwmon.c */ +-int nouveau_hwmon_init(struct drm_device *dev); +-void nouveau_hwmon_fini(struct drm_device *dev); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_ioc32.c b/drivers/gpu/drm/nouveau/nouveau_ioc32.c +deleted file mode 100644 +index 462679a8..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_ioc32.c ++++ /dev/null +@@ -1,69 +0,0 @@ +-/** +- * \file mga_ioc32.c +- * +- * 32-bit ioctl compatibility routines for the MGA DRM. +- * +- * \author Dave Airlie with code from patches by Egbert Eich +- * +- * +- * Copyright (C) Paul Mackerras 2005 +- * Copyright (C) Egbert Eich 2003,2004 +- * Copyright (C) Dave Airlie 2005 +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +- * IN THE SOFTWARE. +- */ +- +-#include +- +-#include +- +-#include "nouveau_ioctl.h" +- +-/** +- * Called whenever a 32-bit process running under a 64-bit kernel +- * performs an ioctl on /dev/dri/card. +- * +- * \param filp file pointer. +- * \param cmd command. +- * \param arg user argument. +- * \return zero on success or negative number on failure. +- */ +-long nouveau_compat_ioctl(struct file *filp, unsigned int cmd, +- unsigned long arg) +-{ +- unsigned int nr = DRM_IOCTL_NR(cmd); +- drm_ioctl_compat_t *fn = NULL; +- int ret; +- +- if (nr < DRM_COMMAND_BASE) +- return drm_compat_ioctl(filp, cmd, arg); +- +-#if 0 +- if (nr < DRM_COMMAND_BASE + ARRAY_SIZE(mga_compat_ioctls)) +- fn = nouveau_compat_ioctls[nr - DRM_COMMAND_BASE]; +-#endif +- if (fn != NULL) +- ret = (*fn)(filp, cmd, arg); +- else +- ret = nouveau_drm_ioctl(filp, cmd, arg); +- +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_ioctl.h b/drivers/gpu/drm/nouveau/nouveau_ioctl.h +deleted file mode 100644 +index 3b9f2e54..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_ioctl.h ++++ /dev/null +@@ -1,7 +0,0 @@ +-#ifndef __NOUVEAU_IOCTL_H__ +-#define __NOUVEAU_IOCTL_H__ +- +-long nouveau_compat_ioctl(struct file *, unsigned int cmd, unsigned long arg); +-long nouveau_drm_ioctl(struct file *, unsigned int cmd, unsigned long arg); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_nvif.c b/drivers/gpu/drm/nouveau/nouveau_nvif.c +deleted file mode 100644 +index 6544b84f..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_nvif.c ++++ /dev/null +@@ -1,136 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-/******************************************************************************* +- * NVIF client driver - NVKM directly linked +- ******************************************************************************/ +- +-#include +-#include +-#include +- +-#include +-#include +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_usif.h" +- +-static void +-nvkm_client_unmap(void *priv, void __iomem *ptr, u32 size) +-{ +- iounmap(ptr); +-} +- +-static void __iomem * +-nvkm_client_map(void *priv, u64 handle, u32 size) +-{ +- return ioremap(handle, size); +-} +- +-static int +-nvkm_client_ioctl(void *priv, bool super, void *data, u32 size, void **hack) +-{ +- return nvkm_ioctl(priv, super, data, size, hack); +-} +- +-static int +-nvkm_client_resume(void *priv) +-{ +- return nouveau_client_init(priv); +-} +- +-static int +-nvkm_client_suspend(void *priv) +-{ +- return nouveau_client_fini(priv, true); +-} +- +-static void +-nvkm_client_fini(void *priv) +-{ +- struct nouveau_object *client = priv; +- nouveau_client_fini(nv_client(client), false); +- atomic_set(&client->refcount, 1); +- nouveau_object_ref(NULL, &client); +-} +- +-static int +-nvkm_client_ntfy(const void *header, u32 length, const void *data, u32 size) +-{ +- const union { +- struct nvif_notify_req_v0 v0; +- } *args = header; +- u8 route; +- +- if (length == sizeof(args->v0) && args->v0.version == 0) { +- route = args->v0.route; +- } else { +- WARN_ON(1); +- return NVKM_NOTIFY_DROP; +- } +- +- switch (route) { +- case NVDRM_NOTIFY_NVIF: +- return nvif_notify(header, length, data, size); +- case NVDRM_NOTIFY_USIF: +- return usif_notify(header, length, data, size); +- default: +- WARN_ON(1); +- break; +- } +- +- return NVKM_NOTIFY_DROP; +-} +- +-static int +-nvkm_client_init(const char *name, u64 device, const char *cfg, +- const char *dbg, void **ppriv) +-{ +- struct nouveau_client *client; +- int ret; +- +- ret = nouveau_client_create(name, device, cfg, dbg, &client); +- *ppriv = client; +- if (ret) +- return ret; +- +- client->ntfy = nvkm_client_ntfy; +- return 0; +-} +- +-const struct nvif_driver +-nvif_driver_nvkm = { +- .name = "nvkm", +- .init = nvkm_client_init, +- .fini = nvkm_client_fini, +- .suspend = nvkm_client_suspend, +- .resume = nvkm_client_resume, +- .ioctl = nvkm_client_ioctl, +- .map = nvkm_client_map, +- .unmap = nvkm_client_unmap, +- .keep = false, +-}; +diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c +deleted file mode 100644 +index 246a824c..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_platform.c ++++ /dev/null +@@ -1,183 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_platform.h" +- +-static int nouveau_platform_power_up(struct nouveau_platform_gpu *gpu) +-{ +- int err; +- +- err = regulator_enable(gpu->vdd); +- if (err) +- goto err_power; +- +- err = clk_prepare_enable(gpu->clk); +- if (err) +- goto err_clk; +- err = clk_prepare_enable(gpu->clk_pwr); +- if (err) +- goto err_clk_pwr; +- clk_set_rate(gpu->clk_pwr, 204000000); +- udelay(10); +- +- reset_control_assert(gpu->rst); +- udelay(10); +- +- err = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); +- if (err) +- goto err_clamp; +- udelay(10); +- +- reset_control_deassert(gpu->rst); +- udelay(10); +- +- return 0; +- +-err_clamp: +- clk_disable_unprepare(gpu->clk_pwr); +-err_clk_pwr: +- clk_disable_unprepare(gpu->clk); +-err_clk: +- regulator_disable(gpu->vdd); +-err_power: +- return err; +-} +- +-static int nouveau_platform_power_down(struct nouveau_platform_gpu *gpu) +-{ +- int err; +- +- reset_control_assert(gpu->rst); +- udelay(10); +- +- clk_disable_unprepare(gpu->clk_pwr); +- clk_disable_unprepare(gpu->clk); +- udelay(10); +- +- err = regulator_disable(gpu->vdd); +- if (err) +- return err; +- +- return 0; +-} +- +-static int nouveau_platform_probe(struct platform_device *pdev) +-{ +- struct nouveau_platform_gpu *gpu; +- struct nouveau_platform_device *device; +- struct drm_device *drm; +- int err; +- +- gpu = devm_kzalloc(&pdev->dev, sizeof(*gpu), GFP_KERNEL); +- if (!gpu) +- return -ENOMEM; +- +- gpu->vdd = devm_regulator_get(&pdev->dev, "vdd"); +- if (IS_ERR(gpu->vdd)) +- return PTR_ERR(gpu->vdd); +- +- gpu->rst = devm_reset_control_get(&pdev->dev, "gpu"); +- if (IS_ERR(gpu->rst)) +- return PTR_ERR(gpu->rst); +- +- gpu->clk = devm_clk_get(&pdev->dev, "gpu"); +- if (IS_ERR(gpu->clk)) +- return PTR_ERR(gpu->clk); +- +- gpu->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); +- if (IS_ERR(gpu->clk_pwr)) +- return PTR_ERR(gpu->clk_pwr); +- +- err = nouveau_platform_power_up(gpu); +- if (err) +- return err; +- +- drm = nouveau_platform_device_create(pdev, &device); +- if (IS_ERR(drm)) { +- err = PTR_ERR(drm); +- goto power_down; +- } +- +- device->gpu = gpu; +- +- err = drm_dev_register(drm, 0); +- if (err < 0) +- goto err_unref; +- +- return 0; +- +-err_unref: +- drm_dev_unref(drm); +- +- return 0; +- +-power_down: +- nouveau_platform_power_down(gpu); +- +- return err; +-} +- +-static int nouveau_platform_remove(struct platform_device *pdev) +-{ +- struct drm_device *drm_dev = platform_get_drvdata(pdev); +- struct nouveau_drm *drm = nouveau_drm(drm_dev); +- struct nouveau_device *device = nvkm_device(&drm->device); +- struct nouveau_platform_gpu *gpu = nv_device_to_platform(device)->gpu; +- +- nouveau_drm_device_remove(drm_dev); +- +- return nouveau_platform_power_down(gpu); +-} +- +-#if IS_ENABLED(CONFIG_OF) +-static const struct of_device_id nouveau_platform_match[] = { +- { .compatible = "nvidia,gk20a" }, +- { } +-}; +- +-MODULE_DEVICE_TABLE(of, nouveau_platform_match); +-#endif +- +-struct platform_driver nouveau_platform_driver = { +- .driver = { +- .name = "nouveau", +- .of_match_table = of_match_ptr(nouveau_platform_match), +- }, +- .probe = nouveau_platform_probe, +- .remove = nouveau_platform_remove, +-}; +- +-module_platform_driver(nouveau_platform_driver); +- +-MODULE_AUTHOR(DRIVER_AUTHOR); +-MODULE_DESCRIPTION(DRIVER_DESC); +-MODULE_LICENSE("GPL and additional rights"); +diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.h b/drivers/gpu/drm/nouveau/nouveau_platform.h +deleted file mode 100644 +index 91f66504..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_platform.h ++++ /dev/null +@@ -1,49 +0,0 @@ +-/* +- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#ifndef __NOUVEAU_PLATFORM_H__ +-#define __NOUVEAU_PLATFORM_H__ +- +-#include "core/device.h" +- +-struct reset_control; +-struct clk; +-struct regulator; +- +-struct nouveau_platform_gpu { +- struct reset_control *rst; +- struct clk *clk; +- struct clk *clk_pwr; +- +- struct regulator *vdd; +-}; +- +-struct nouveau_platform_device { +- struct nouveau_device device; +- +- struct nouveau_platform_gpu *gpu; +-}; +- +-#define nv_device_to_platform(d) \ +- container_of(d, struct nouveau_platform_device, device) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c +deleted file mode 100644 +index 228226ab..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_prime.c ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Dave Airlie +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_gem.h" +- +-struct sg_table *nouveau_gem_prime_get_sg_table(struct drm_gem_object *obj) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(obj); +- int npages = nvbo->bo.num_pages; +- +- return drm_prime_pages_to_sg(nvbo->bo.ttm->pages, npages); +-} +- +-void *nouveau_gem_prime_vmap(struct drm_gem_object *obj) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(obj); +- int ret; +- +- ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.num_pages, +- &nvbo->dma_buf_vmap); +- if (ret) +- return ERR_PTR(ret); +- +- return nvbo->dma_buf_vmap.virtual; +-} +- +-void nouveau_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(obj); +- +- ttm_bo_kunmap(&nvbo->dma_buf_vmap); +-} +- +-struct drm_gem_object *nouveau_gem_prime_import_sg_table(struct drm_device *dev, +- struct dma_buf_attachment *attach, +- struct sg_table *sg) +-{ +- struct nouveau_bo *nvbo; +- struct reservation_object *robj = attach->dmabuf->resv; +- u32 flags = 0; +- int ret; +- +- flags = TTM_PL_FLAG_TT; +- +- ww_mutex_lock(&robj->lock, NULL); +- ret = nouveau_bo_new(dev, attach->dmabuf->size, 0, flags, 0, 0, +- sg, robj, &nvbo); +- ww_mutex_unlock(&robj->lock); +- if (ret) +- return ERR_PTR(ret); +- +- nvbo->valid_domains = NOUVEAU_GEM_DOMAIN_GART; +- +- /* Initialize the embedded gem-object. We return a single gem-reference +- * to the caller, instead of a normal nouveau_bo ttm reference. */ +- ret = drm_gem_object_init(dev, &nvbo->gem, nvbo->bo.mem.size); +- if (ret) { +- nouveau_bo_ref(NULL, &nvbo); +- return ERR_PTR(-ENOMEM); +- } +- +- return &nvbo->gem; +-} +- +-int nouveau_gem_prime_pin(struct drm_gem_object *obj) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(obj); +- int ret; +- +- /* pin buffer into GTT */ +- ret = nouveau_bo_pin(nvbo, TTM_PL_FLAG_TT); +- if (ret) +- return -EINVAL; +- +- return 0; +-} +- +-void nouveau_gem_prime_unpin(struct drm_gem_object *obj) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(obj); +- +- nouveau_bo_unpin(nvbo); +-} +- +-struct reservation_object *nouveau_gem_prime_res_obj(struct drm_gem_object *obj) +-{ +- struct nouveau_bo *nvbo = nouveau_gem_object(obj); +- +- return nvbo->bo.resv; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h +deleted file mode 100644 +index 43a96b99..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_reg.h ++++ /dev/null +@@ -1,858 +0,0 @@ +- +-#define NV04_PFB_BOOT_0 0x00100000 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 +-# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 +-# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004 +-# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020 +-# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028 +-# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100 +-# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000 +-#define NV04_PFB_DEBUG_0 0x00100080 +-# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001 +-# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010 +-# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00 +-# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000 +-# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000 +-# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000 +-# define NV04_PFB_DEBUG_0_CASOE 0x00100000 +-# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000 +-# define NV04_PFB_DEBUG_0_REFINC 0x20000000 +-# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000 +-#define NV04_PFB_CFG0 0x00100200 +-# define NV04_PFB_CFG0_SCRAMBLE 0x20000000 +-#define NV04_PFB_CFG1 0x00100204 +-#define NV04_PFB_FIFO_DATA 0x0010020c +-# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000 +-# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20 +-#define NV10_PFB_REFCTRL 0x00100210 +-# define NV10_PFB_REFCTRL_VALID_1 (1 << 31) +-#define NV04_PFB_PAD 0x0010021c +-# define NV04_PFB_PAD_CKE_NORMAL (1 << 0) +-#define NV10_PFB_TILE(i) (0x00100240 + (i*16)) +-#define NV10_PFB_TILE__SIZE 8 +-#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16)) +-#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16)) +-#define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16)) +-#define NV04_PFB_REF 0x001002d0 +-# define NV04_PFB_REF_CMD_REFRESH (1 << 0) +-#define NV04_PFB_PRE 0x001002d4 +-# define NV04_PFB_PRE_CMD_PRECHARGE (1 << 0) +-#define NV20_PFB_ZCOMP(i) (0x00100300 + 4*(i)) +-# define NV20_PFB_ZCOMP_MODE_32 (4 << 24) +-# define NV20_PFB_ZCOMP_EN (1 << 31) +-# define NV25_PFB_ZCOMP_MODE_16 (1 << 20) +-# define NV25_PFB_ZCOMP_MODE_32 (2 << 20) +-#define NV10_PFB_CLOSE_PAGE2 0x0010033c +-#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i)) +-#define NV40_PFB_TILE(i) (0x00100600 + (i*16)) +-#define NV40_PFB_TILE__SIZE_0 12 +-#define NV40_PFB_TILE__SIZE_1 15 +-#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16)) +-#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16)) +-#define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16)) +-#define NV40_PFB_UNK_800 0x00100800 +- +-#define NV_PEXTDEV_BOOT_0 0x00101000 +-#define NV_PEXTDEV_BOOT_0_RAMCFG 0x0000003c +-# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12) +-#define NV_PEXTDEV_BOOT_3 0x0010100c +- +-#define NV_RAMIN 0x00700000 +- +-#define NV_RAMHT_HANDLE_OFFSET 0 +-#define NV_RAMHT_CONTEXT_OFFSET 4 +-# define NV_RAMHT_CONTEXT_VALID (1<<31) +-# define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24 +-# define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16 +-# define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0 +-# define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1 +-# define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0 +-# define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23 +-# define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20 +-# define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0 +- +-/* Some object classes we care about in the drm */ +-#define NV_CLASS_DMA_FROM_MEMORY 0x00000002 +-#define NV_CLASS_DMA_TO_MEMORY 0x00000003 +-#define NV_CLASS_NULL 0x00000030 +-#define NV_CLASS_DMA_IN_MEMORY 0x0000003D +- +-#define NV03_USER(i) (0x00800000+(i*NV03_USER_SIZE)) +-#define NV03_USER__SIZE 16 +-#define NV10_USER__SIZE 32 +-#define NV03_USER_SIZE 0x00010000 +-#define NV03_USER_DMA_PUT(i) (0x00800040+(i*NV03_USER_SIZE)) +-#define NV03_USER_DMA_PUT__SIZE 16 +-#define NV10_USER_DMA_PUT__SIZE 32 +-#define NV03_USER_DMA_GET(i) (0x00800044+(i*NV03_USER_SIZE)) +-#define NV03_USER_DMA_GET__SIZE 16 +-#define NV10_USER_DMA_GET__SIZE 32 +-#define NV03_USER_REF_CNT(i) (0x00800048+(i*NV03_USER_SIZE)) +-#define NV03_USER_REF_CNT__SIZE 16 +-#define NV10_USER_REF_CNT__SIZE 32 +- +-#define NV40_USER(i) (0x00c00000+(i*NV40_USER_SIZE)) +-#define NV40_USER_SIZE 0x00001000 +-#define NV40_USER_DMA_PUT(i) (0x00c00040+(i*NV40_USER_SIZE)) +-#define NV40_USER_DMA_PUT__SIZE 32 +-#define NV40_USER_DMA_GET(i) (0x00c00044+(i*NV40_USER_SIZE)) +-#define NV40_USER_DMA_GET__SIZE 32 +-#define NV40_USER_REF_CNT(i) (0x00c00048+(i*NV40_USER_SIZE)) +-#define NV40_USER_REF_CNT__SIZE 32 +- +-#define NV50_USER(i) (0x00c00000+(i*NV50_USER_SIZE)) +-#define NV50_USER_SIZE 0x00002000 +-#define NV50_USER_DMA_PUT(i) (0x00c00040+(i*NV50_USER_SIZE)) +-#define NV50_USER_DMA_PUT__SIZE 128 +-#define NV50_USER_DMA_GET(i) (0x00c00044+(i*NV50_USER_SIZE)) +-#define NV50_USER_DMA_GET__SIZE 128 +-#define NV50_USER_REF_CNT(i) (0x00c00048+(i*NV50_USER_SIZE)) +-#define NV50_USER_REF_CNT__SIZE 128 +- +-#define NV03_FIFO_SIZE 0x8000UL +- +-#define NV03_PMC_BOOT_0 0x00000000 +-#define NV03_PMC_BOOT_1 0x00000004 +-#define NV03_PMC_INTR_0 0x00000100 +-# define NV_PMC_INTR_0_PFIFO_PENDING (1<<8) +-# define NV_PMC_INTR_0_PGRAPH_PENDING (1<<12) +-# define NV_PMC_INTR_0_NV50_I2C_PENDING (1<<21) +-# define NV_PMC_INTR_0_CRTC0_PENDING (1<<24) +-# define NV_PMC_INTR_0_CRTC1_PENDING (1<<25) +-# define NV_PMC_INTR_0_NV50_DISPLAY_PENDING (1<<26) +-# define NV_PMC_INTR_0_CRTCn_PENDING (3<<24) +-#define NV03_PMC_INTR_EN_0 0x00000140 +-# define NV_PMC_INTR_EN_0_MASTER_ENABLE (1<<0) +-#define NV03_PMC_ENABLE 0x00000200 +-# define NV_PMC_ENABLE_PFIFO (1<<8) +-# define NV_PMC_ENABLE_PGRAPH (1<<12) +-/* Disabling the below bit breaks newer (G7X only?) mobile chipsets, +- * the card will hang early on in the X init process. +- */ +-# define NV_PMC_ENABLE_UNK13 (1<<13) +-#define NV40_PMC_GRAPH_UNITS 0x00001540 +-#define NV40_PMC_BACKLIGHT 0x000015f0 +-# define NV40_PMC_BACKLIGHT_MASK 0x001f0000 +-#define NV40_PMC_1700 0x00001700 +-#define NV40_PMC_1704 0x00001704 +-#define NV40_PMC_1708 0x00001708 +-#define NV40_PMC_170C 0x0000170C +- +-/* probably PMC ? */ +-#define NV50_PUNK_BAR0_PRAMIN 0x00001700 +-#define NV50_PUNK_BAR_CFG_BASE 0x00001704 +-#define NV50_PUNK_BAR_CFG_BASE_VALID (1<<30) +-#define NV50_PUNK_BAR1_CTXDMA 0x00001708 +-#define NV50_PUNK_BAR1_CTXDMA_VALID (1<<31) +-#define NV50_PUNK_BAR3_CTXDMA 0x0000170C +-#define NV50_PUNK_BAR3_CTXDMA_VALID (1<<31) +-#define NV50_PUNK_UNK1710 0x00001710 +- +-#define NV04_PBUS_PCI_NV_1 0x00001804 +-#define NV04_PBUS_PCI_NV_19 0x0000184C +-#define NV04_PBUS_PCI_NV_20 0x00001850 +-# define NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED (0 << 0) +-# define NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED (1 << 0) +- +-#define NV04_PTIMER_INTR_0 0x00009100 +-#define NV04_PTIMER_INTR_EN_0 0x00009140 +-#define NV04_PTIMER_NUMERATOR 0x00009200 +-#define NV04_PTIMER_DENOMINATOR 0x00009210 +-#define NV04_PTIMER_TIME_0 0x00009400 +-#define NV04_PTIMER_TIME_1 0x00009410 +-#define NV04_PTIMER_ALARM_0 0x00009420 +- +-#define NV04_PGRAPH_DEBUG_0 0x00400080 +-#define NV04_PGRAPH_DEBUG_1 0x00400084 +-#define NV04_PGRAPH_DEBUG_2 0x00400088 +-#define NV04_PGRAPH_DEBUG_3 0x0040008c +-#define NV10_PGRAPH_DEBUG_4 0x00400090 +-#define NV03_PGRAPH_INTR 0x00400100 +-#define NV03_PGRAPH_NSTATUS 0x00400104 +-# define NV04_PGRAPH_NSTATUS_STATE_IN_USE (1<<11) +-# define NV04_PGRAPH_NSTATUS_INVALID_STATE (1<<12) +-# define NV04_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<13) +-# define NV04_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<14) +-# define NV10_PGRAPH_NSTATUS_STATE_IN_USE (1<<23) +-# define NV10_PGRAPH_NSTATUS_INVALID_STATE (1<<24) +-# define NV10_PGRAPH_NSTATUS_BAD_ARGUMENT (1<<25) +-# define NV10_PGRAPH_NSTATUS_PROTECTION_FAULT (1<<26) +-#define NV03_PGRAPH_NSOURCE 0x00400108 +-# define NV03_PGRAPH_NSOURCE_NOTIFICATION (1<<0) +-# define NV03_PGRAPH_NSOURCE_DATA_ERROR (1<<1) +-# define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR (1<<2) +-# define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION (1<<3) +-# define NV03_PGRAPH_NSOURCE_LIMIT_COLOR (1<<4) +-# define NV03_PGRAPH_NSOURCE_LIMIT_ZETA (1<<5) +-# define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD (1<<6) +-# define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION (1<<7) +-# define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION (1<<8) +-# define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION (1<<9) +-# define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION (1<<10) +-# define NV03_PGRAPH_NSOURCE_STATE_INVALID (1<<11) +-# define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY (1<<12) +-# define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE (1<<13) +-# define NV03_PGRAPH_NSOURCE_METHOD_CNT (1<<14) +-# define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION (1<<15) +-# define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION (1<<16) +-# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A (1<<17) +-# define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B (1<<18) +-#define NV03_PGRAPH_INTR_EN 0x00400140 +-#define NV40_PGRAPH_INTR_EN 0x0040013C +-# define NV_PGRAPH_INTR_NOTIFY (1<<0) +-# define NV_PGRAPH_INTR_MISSING_HW (1<<4) +-# define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12) +-# define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16) +-# define NV_PGRAPH_INTR_ERROR (1<<20) +-#define NV10_PGRAPH_CTX_CONTROL 0x00400144 +-#define NV10_PGRAPH_CTX_USER 0x00400148 +-#define NV10_PGRAPH_CTX_SWITCH(i) (0x0040014C + 0x4*(i)) +-#define NV04_PGRAPH_CTX_SWITCH1 0x00400160 +-#define NV10_PGRAPH_CTX_CACHE(i, j) (0x00400160 \ +- + 0x4*(i) + 0x20*(j)) +-#define NV04_PGRAPH_CTX_SWITCH2 0x00400164 +-#define NV04_PGRAPH_CTX_SWITCH3 0x00400168 +-#define NV04_PGRAPH_CTX_SWITCH4 0x0040016C +-#define NV04_PGRAPH_CTX_CONTROL 0x00400170 +-#define NV04_PGRAPH_CTX_USER 0x00400174 +-#define NV04_PGRAPH_CTX_CACHE1 0x00400180 +-#define NV03_PGRAPH_CTX_CONTROL 0x00400190 +-#define NV03_PGRAPH_CTX_USER 0x00400194 +-#define NV04_PGRAPH_CTX_CACHE2 0x004001A0 +-#define NV04_PGRAPH_CTX_CACHE3 0x004001C0 +-#define NV04_PGRAPH_CTX_CACHE4 0x004001E0 +-#define NV40_PGRAPH_CTXCTL_0304 0x00400304 +-#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT 0x00400308 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK 0xff000000 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT 24 +-#define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK 0x00ffffff +-#define NV40_PGRAPH_CTXCTL_0310 0x00400310 +-#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020 +-#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040 +-#define NV40_PGRAPH_CTXCTL_030C 0x0040030c +-#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324 +-#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328 +-#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c +-#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000 +-#define NV40_PGRAPH_CTXCTL_CUR_INSTANCE 0x000FFFFF +-#define NV40_PGRAPH_CTXCTL_NEXT 0x00400330 +-#define NV40_PGRAPH_CTXCTL_NEXT_INSTANCE 0x000fffff +-#define NV50_PGRAPH_CTXCTL_CUR 0x0040032c +-#define NV50_PGRAPH_CTXCTL_CUR_LOADED 0x80000000 +-#define NV50_PGRAPH_CTXCTL_CUR_INSTANCE 0x00ffffff +-#define NV50_PGRAPH_CTXCTL_NEXT 0x00400330 +-#define NV50_PGRAPH_CTXCTL_NEXT_INSTANCE 0x00ffffff +-#define NV03_PGRAPH_ABS_X_RAM 0x00400400 +-#define NV03_PGRAPH_ABS_Y_RAM 0x00400480 +-#define NV03_PGRAPH_X_MISC 0x00400500 +-#define NV03_PGRAPH_Y_MISC 0x00400504 +-#define NV04_PGRAPH_VALID1 0x00400508 +-#define NV04_PGRAPH_SOURCE_COLOR 0x0040050C +-#define NV04_PGRAPH_MISC24_0 0x00400510 +-#define NV03_PGRAPH_XY_LOGIC_MISC0 0x00400514 +-#define NV03_PGRAPH_XY_LOGIC_MISC1 0x00400518 +-#define NV03_PGRAPH_XY_LOGIC_MISC2 0x0040051C +-#define NV03_PGRAPH_XY_LOGIC_MISC3 0x00400520 +-#define NV03_PGRAPH_CLIPX_0 0x00400524 +-#define NV03_PGRAPH_CLIPX_1 0x00400528 +-#define NV03_PGRAPH_CLIPY_0 0x0040052C +-#define NV03_PGRAPH_CLIPY_1 0x00400530 +-#define NV03_PGRAPH_ABS_ICLIP_XMAX 0x00400534 +-#define NV03_PGRAPH_ABS_ICLIP_YMAX 0x00400538 +-#define NV03_PGRAPH_ABS_UCLIP_XMIN 0x0040053C +-#define NV03_PGRAPH_ABS_UCLIP_YMIN 0x00400540 +-#define NV03_PGRAPH_ABS_UCLIP_XMAX 0x00400544 +-#define NV03_PGRAPH_ABS_UCLIP_YMAX 0x00400548 +-#define NV03_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 +-#define NV03_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 +-#define NV03_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 +-#define NV03_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C +-#define NV04_PGRAPH_MISC24_1 0x00400570 +-#define NV04_PGRAPH_MISC24_2 0x00400574 +-#define NV04_PGRAPH_VALID2 0x00400578 +-#define NV04_PGRAPH_PASSTHRU_0 0x0040057C +-#define NV04_PGRAPH_PASSTHRU_1 0x00400580 +-#define NV04_PGRAPH_PASSTHRU_2 0x00400584 +-#define NV10_PGRAPH_DIMX_TEXTURE 0x00400588 +-#define NV10_PGRAPH_WDIMX_TEXTURE 0x0040058C +-#define NV04_PGRAPH_COMBINE_0_ALPHA 0x00400590 +-#define NV04_PGRAPH_COMBINE_0_COLOR 0x00400594 +-#define NV04_PGRAPH_COMBINE_1_ALPHA 0x00400598 +-#define NV04_PGRAPH_COMBINE_1_COLOR 0x0040059C +-#define NV04_PGRAPH_FORMAT_0 0x004005A8 +-#define NV04_PGRAPH_FORMAT_1 0x004005AC +-#define NV04_PGRAPH_FILTER_0 0x004005B0 +-#define NV04_PGRAPH_FILTER_1 0x004005B4 +-#define NV03_PGRAPH_MONO_COLOR0 0x00400600 +-#define NV04_PGRAPH_ROP3 0x00400604 +-#define NV04_PGRAPH_BETA_AND 0x00400608 +-#define NV04_PGRAPH_BETA_PREMULT 0x0040060C +-#define NV04_PGRAPH_LIMIT_VIOL_PIX 0x00400610 +-#define NV04_PGRAPH_FORMATS 0x00400618 +-#define NV10_PGRAPH_DEBUG_2 0x00400620 +-#define NV04_PGRAPH_BOFFSET0 0x00400640 +-#define NV04_PGRAPH_BOFFSET1 0x00400644 +-#define NV04_PGRAPH_BOFFSET2 0x00400648 +-#define NV04_PGRAPH_BOFFSET3 0x0040064C +-#define NV04_PGRAPH_BOFFSET4 0x00400650 +-#define NV04_PGRAPH_BOFFSET5 0x00400654 +-#define NV04_PGRAPH_BBASE0 0x00400658 +-#define NV04_PGRAPH_BBASE1 0x0040065C +-#define NV04_PGRAPH_BBASE2 0x00400660 +-#define NV04_PGRAPH_BBASE3 0x00400664 +-#define NV04_PGRAPH_BBASE4 0x00400668 +-#define NV04_PGRAPH_BBASE5 0x0040066C +-#define NV04_PGRAPH_BPITCH0 0x00400670 +-#define NV04_PGRAPH_BPITCH1 0x00400674 +-#define NV04_PGRAPH_BPITCH2 0x00400678 +-#define NV04_PGRAPH_BPITCH3 0x0040067C +-#define NV04_PGRAPH_BPITCH4 0x00400680 +-#define NV04_PGRAPH_BLIMIT0 0x00400684 +-#define NV04_PGRAPH_BLIMIT1 0x00400688 +-#define NV04_PGRAPH_BLIMIT2 0x0040068C +-#define NV04_PGRAPH_BLIMIT3 0x00400690 +-#define NV04_PGRAPH_BLIMIT4 0x00400694 +-#define NV04_PGRAPH_BLIMIT5 0x00400698 +-#define NV04_PGRAPH_BSWIZZLE2 0x0040069C +-#define NV04_PGRAPH_BSWIZZLE5 0x004006A0 +-#define NV03_PGRAPH_STATUS 0x004006B0 +-#define NV04_PGRAPH_STATUS 0x00400700 +-# define NV40_PGRAPH_STATUS_SYNC_STALL 0x00004000 +-#define NV04_PGRAPH_TRAPPED_ADDR 0x00400704 +-#define NV04_PGRAPH_TRAPPED_DATA 0x00400708 +-#define NV04_PGRAPH_SURFACE 0x0040070C +-#define NV10_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C +-#define NV04_PGRAPH_STATE 0x00400710 +-#define NV10_PGRAPH_SURFACE 0x00400710 +-#define NV04_PGRAPH_NOTIFY 0x00400714 +-#define NV10_PGRAPH_STATE 0x00400714 +-#define NV10_PGRAPH_NOTIFY 0x00400718 +- +-#define NV04_PGRAPH_FIFO 0x00400720 +- +-#define NV04_PGRAPH_BPIXEL 0x00400724 +-#define NV10_PGRAPH_RDI_INDEX 0x00400750 +-#define NV04_PGRAPH_FFINTFC_ST2 0x00400754 +-#define NV10_PGRAPH_RDI_DATA 0x00400754 +-#define NV04_PGRAPH_DMA_PITCH 0x00400760 +-#define NV10_PGRAPH_FFINTFC_FIFO_PTR 0x00400760 +-#define NV04_PGRAPH_DVD_COLORFMT 0x00400764 +-#define NV10_PGRAPH_FFINTFC_ST2 0x00400764 +-#define NV04_PGRAPH_SCALED_FORMAT 0x00400768 +-#define NV10_PGRAPH_FFINTFC_ST2_DL 0x00400768 +-#define NV10_PGRAPH_FFINTFC_ST2_DH 0x0040076c +-#define NV10_PGRAPH_DMA_PITCH 0x00400770 +-#define NV10_PGRAPH_DVD_COLORFMT 0x00400774 +-#define NV10_PGRAPH_SCALED_FORMAT 0x00400778 +-#define NV20_PGRAPH_CHANNEL_CTX_TABLE 0x00400780 +-#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784 +-#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788 +-#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001 +-#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002 +-#define NV04_PGRAPH_PATT_COLOR0 0x00400800 +-#define NV04_PGRAPH_PATT_COLOR1 0x00400804 +-#define NV04_PGRAPH_PATTERN 0x00400808 +-#define NV04_PGRAPH_PATTERN_SHAPE 0x00400810 +-#define NV04_PGRAPH_CHROMA 0x00400814 +-#define NV04_PGRAPH_CONTROL0 0x00400818 +-#define NV04_PGRAPH_CONTROL1 0x0040081C +-#define NV04_PGRAPH_CONTROL2 0x00400820 +-#define NV04_PGRAPH_BLEND 0x00400824 +-#define NV04_PGRAPH_STORED_FMT 0x00400830 +-#define NV04_PGRAPH_PATT_COLORRAM 0x00400900 +-#define NV20_PGRAPH_TILE(i) (0x00400900 + (i*16)) +-#define NV20_PGRAPH_TLIMIT(i) (0x00400904 + (i*16)) +-#define NV20_PGRAPH_TSIZE(i) (0x00400908 + (i*16)) +-#define NV20_PGRAPH_TSTATUS(i) (0x0040090C + (i*16)) +-#define NV20_PGRAPH_ZCOMP(i) (0x00400980 + 4*(i)) +-#define NV10_PGRAPH_TILE(i) (0x00400B00 + (i*16)) +-#define NV10_PGRAPH_TLIMIT(i) (0x00400B04 + (i*16)) +-#define NV10_PGRAPH_TSIZE(i) (0x00400B08 + (i*16)) +-#define NV10_PGRAPH_TSTATUS(i) (0x00400B0C + (i*16)) +-#define NV04_PGRAPH_U_RAM 0x00400D00 +-#define NV47_PGRAPH_TILE(i) (0x00400D00 + (i*16)) +-#define NV47_PGRAPH_TLIMIT(i) (0x00400D04 + (i*16)) +-#define NV47_PGRAPH_TSIZE(i) (0x00400D08 + (i*16)) +-#define NV47_PGRAPH_TSTATUS(i) (0x00400D0C + (i*16)) +-#define NV04_PGRAPH_V_RAM 0x00400D40 +-#define NV04_PGRAPH_W_RAM 0x00400D80 +-#define NV10_PGRAPH_COMBINER0_IN_ALPHA 0x00400E40 +-#define NV10_PGRAPH_COMBINER1_IN_ALPHA 0x00400E44 +-#define NV10_PGRAPH_COMBINER0_IN_RGB 0x00400E48 +-#define NV10_PGRAPH_COMBINER1_IN_RGB 0x00400E4C +-#define NV10_PGRAPH_COMBINER_COLOR0 0x00400E50 +-#define NV10_PGRAPH_COMBINER_COLOR1 0x00400E54 +-#define NV10_PGRAPH_COMBINER0_OUT_ALPHA 0x00400E58 +-#define NV10_PGRAPH_COMBINER1_OUT_ALPHA 0x00400E5C +-#define NV10_PGRAPH_COMBINER0_OUT_RGB 0x00400E60 +-#define NV10_PGRAPH_COMBINER1_OUT_RGB 0x00400E64 +-#define NV10_PGRAPH_COMBINER_FINAL0 0x00400E68 +-#define NV10_PGRAPH_COMBINER_FINAL1 0x00400E6C +-#define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL 0x00400F00 +-#define NV10_PGRAPH_WINDOWCLIP_VERTICAL 0x00400F20 +-#define NV10_PGRAPH_XFMODE0 0x00400F40 +-#define NV10_PGRAPH_XFMODE1 0x00400F44 +-#define NV10_PGRAPH_GLOBALSTATE0 0x00400F48 +-#define NV10_PGRAPH_GLOBALSTATE1 0x00400F4C +-#define NV10_PGRAPH_PIPE_ADDRESS 0x00400F50 +-#define NV10_PGRAPH_PIPE_DATA 0x00400F54 +-#define NV04_PGRAPH_DMA_START_0 0x00401000 +-#define NV04_PGRAPH_DMA_START_1 0x00401004 +-#define NV04_PGRAPH_DMA_LENGTH 0x00401008 +-#define NV04_PGRAPH_DMA_MISC 0x0040100C +-#define NV04_PGRAPH_DMA_DATA_0 0x00401020 +-#define NV04_PGRAPH_DMA_DATA_1 0x00401024 +-#define NV04_PGRAPH_DMA_RM 0x00401030 +-#define NV04_PGRAPH_DMA_A_XLATE_INST 0x00401040 +-#define NV04_PGRAPH_DMA_A_CONTROL 0x00401044 +-#define NV04_PGRAPH_DMA_A_LIMIT 0x00401048 +-#define NV04_PGRAPH_DMA_A_TLB_PTE 0x0040104C +-#define NV04_PGRAPH_DMA_A_TLB_TAG 0x00401050 +-#define NV04_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 +-#define NV04_PGRAPH_DMA_A_OFFSET 0x00401058 +-#define NV04_PGRAPH_DMA_A_SIZE 0x0040105C +-#define NV04_PGRAPH_DMA_A_Y_SIZE 0x00401060 +-#define NV04_PGRAPH_DMA_B_XLATE_INST 0x00401080 +-#define NV04_PGRAPH_DMA_B_CONTROL 0x00401084 +-#define NV04_PGRAPH_DMA_B_LIMIT 0x00401088 +-#define NV04_PGRAPH_DMA_B_TLB_PTE 0x0040108C +-#define NV04_PGRAPH_DMA_B_TLB_TAG 0x00401090 +-#define NV04_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 +-#define NV04_PGRAPH_DMA_B_OFFSET 0x00401098 +-#define NV04_PGRAPH_DMA_B_SIZE 0x0040109C +-#define NV04_PGRAPH_DMA_B_Y_SIZE 0x004010A0 +-#define NV40_PGRAPH_TILE1(i) (0x00406900 + (i*16)) +-#define NV40_PGRAPH_TLIMIT1(i) (0x00406904 + (i*16)) +-#define NV40_PGRAPH_TSIZE1(i) (0x00406908 + (i*16)) +-#define NV40_PGRAPH_TSTATUS1(i) (0x0040690C + (i*16)) +- +- +-/* It's a guess that this works on NV03. Confirmed on NV04, though */ +-#define NV04_PFIFO_DELAY_0 0x00002040 +-#define NV04_PFIFO_DMA_TIMESLICE 0x00002044 +-#define NV04_PFIFO_NEXT_CHANNEL 0x00002050 +-#define NV03_PFIFO_INTR_0 0x00002100 +-#define NV03_PFIFO_INTR_EN_0 0x00002140 +-# define NV_PFIFO_INTR_CACHE_ERROR (1<<0) +-# define NV_PFIFO_INTR_RUNOUT (1<<4) +-# define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<<8) +-# define NV_PFIFO_INTR_DMA_PUSHER (1<<12) +-# define NV_PFIFO_INTR_DMA_PT (1<<16) +-# define NV_PFIFO_INTR_SEMAPHORE (1<<20) +-# define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24) +-#define NV03_PFIFO_RAMHT 0x00002210 +-#define NV03_PFIFO_RAMFC 0x00002214 +-#define NV03_PFIFO_RAMRO 0x00002218 +-#define NV40_PFIFO_RAMFC 0x00002220 +-#define NV03_PFIFO_CACHES 0x00002500 +-#define NV04_PFIFO_MODE 0x00002504 +-#define NV04_PFIFO_DMA 0x00002508 +-#define NV04_PFIFO_SIZE 0x0000250c +-#define NV50_PFIFO_CTX_TABLE(c) (0x2600+(c)*4) +-#define NV50_PFIFO_CTX_TABLE__SIZE 128 +-#define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED (1<<31) +-#define NV50_PFIFO_CTX_TABLE_UNK30_BAD (1<<30) +-#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80 0x0FFFFFFF +-#define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84 0x00FFFFFF +-#define NV03_PFIFO_CACHE0_PUSH0 0x00003000 +-#define NV03_PFIFO_CACHE0_PULL0 0x00003040 +-#define NV04_PFIFO_CACHE0_PULL0 0x00003050 +-#define NV04_PFIFO_CACHE0_PULL1 0x00003054 +-#define NV03_PFIFO_CACHE1_PUSH0 0x00003200 +-#define NV03_PFIFO_CACHE1_PUSH1 0x00003204 +-#define NV03_PFIFO_CACHE1_PUSH1_DMA (1<<8) +-#define NV40_PFIFO_CACHE1_PUSH1_DMA (1<<16) +-#define NV03_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000000f +-#define NV10_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000001f +-#define NV50_PFIFO_CACHE1_PUSH1_CHID_MASK 0x0000007f +-#define NV03_PFIFO_CACHE1_PUT 0x00003210 +-#define NV04_PFIFO_CACHE1_DMA_PUSH 0x00003220 +-#define NV04_PFIFO_CACHE1_DMA_FETCH 0x00003224 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000008 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000010 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000018 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000020 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000028 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000030 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000038 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000040 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000048 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x00000050 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x00000058 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x00000060 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x00000068 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x00000070 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x00000078 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000080 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000088 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000090 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000098 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x000000A0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x000000A8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x000000B0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x000000B8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x000000C0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x000000C8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x000000D0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x000000D8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x000000E0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x000000E8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x000000F0 +-# define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x000000F8 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 0x0000E000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00002000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00004000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00006000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00008000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x0000A000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x0000C000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x0000E000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 0x001F0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00010000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00020000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00030000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00040000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00050000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00060000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00070000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00080000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00090000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x000A0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x000B0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x000C0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x000D0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x000E0000 +-# define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x000F0000 +-# define NV_PFIFO_CACHE1_ENDIAN 0x80000000 +-# define NV_PFIFO_CACHE1_LITTLE_ENDIAN 0x7FFFFFFF +-# define NV_PFIFO_CACHE1_BIG_ENDIAN 0x80000000 +-#define NV04_PFIFO_CACHE1_DMA_STATE 0x00003228 +-#define NV04_PFIFO_CACHE1_DMA_INSTANCE 0x0000322c +-#define NV04_PFIFO_CACHE1_DMA_CTL 0x00003230 +-#define NV04_PFIFO_CACHE1_DMA_PUT 0x00003240 +-#define NV04_PFIFO_CACHE1_DMA_GET 0x00003244 +-#define NV10_PFIFO_CACHE1_REF_CNT 0x00003248 +-#define NV10_PFIFO_CACHE1_DMA_SUBROUTINE 0x0000324C +-#define NV03_PFIFO_CACHE1_PULL0 0x00003240 +-#define NV04_PFIFO_CACHE1_PULL0 0x00003250 +-# define NV04_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000010 +-# define NV04_PFIFO_CACHE1_PULL0_HASH_BUSY 0x00001000 +-#define NV03_PFIFO_CACHE1_PULL1 0x00003250 +-#define NV04_PFIFO_CACHE1_PULL1 0x00003254 +-#define NV04_PFIFO_CACHE1_HASH 0x00003258 +-#define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT 0x00003260 +-#define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP 0x00003264 +-#define NV10_PFIFO_CACHE1_ACQUIRE_VALUE 0x00003268 +-#define NV10_PFIFO_CACHE1_SEMAPHORE 0x0000326C +-#define NV03_PFIFO_CACHE1_GET 0x00003270 +-#define NV04_PFIFO_CACHE1_ENGINE 0x00003280 +-#define NV04_PFIFO_CACHE1_DMA_DCOUNT 0x000032A0 +-#define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0 +-#define NV40_PFIFO_UNK32E4 0x000032E4 +-#define NV04_PFIFO_CACHE1_METHOD(i) (0x00003800+(i*8)) +-#define NV04_PFIFO_CACHE1_DATA(i) (0x00003804+(i*8)) +-#define NV40_PFIFO_CACHE1_METHOD(i) (0x00090000+(i*8)) +-#define NV40_PFIFO_CACHE1_DATA(i) (0x00090004+(i*8)) +- +-#define NV_CRTC0_INTSTAT 0x00600100 +-#define NV_CRTC0_INTEN 0x00600140 +-#define NV_CRTC1_INTSTAT 0x00602100 +-#define NV_CRTC1_INTEN 0x00602140 +-# define NV_CRTC_INTR_VBLANK (1<<0) +- +-#define NV04_PRAMIN 0x00700000 +- +-/* Fifo commands. These are not regs, neither masks */ +-#define NV03_FIFO_CMD_JUMP 0x20000000 +-#define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc +-#define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK)) +- +-/* This is a partial import from rules-ng, a few things may be duplicated. +- * Eventually we should completely import everything from rules-ng. +- * For the moment check rules-ng for docs. +- */ +- +-#define NV50_PMC 0x00000000 +-#define NV50_PMC__LEN 0x1 +-#define NV50_PMC__ESIZE 0x2000 +-# define NV50_PMC_BOOT_0 0x00000000 +-# define NV50_PMC_BOOT_0_REVISION 0x000000ff +-# define NV50_PMC_BOOT_0_REVISION__SHIFT 0 +-# define NV50_PMC_BOOT_0_ARCH 0x0ff00000 +-# define NV50_PMC_BOOT_0_ARCH__SHIFT 20 +-# define NV50_PMC_INTR_0 0x00000100 +-# define NV50_PMC_INTR_0_PFIFO (1<<8) +-# define NV50_PMC_INTR_0_PGRAPH (1<<12) +-# define NV50_PMC_INTR_0_PTIMER (1<<20) +-# define NV50_PMC_INTR_0_HOTPLUG (1<<21) +-# define NV50_PMC_INTR_0_DISPLAY (1<<26) +-# define NV50_PMC_INTR_EN_0 0x00000140 +-# define NV50_PMC_INTR_EN_0_MASTER (1<<0) +-# define NV50_PMC_INTR_EN_0_MASTER_DISABLED (0<<0) +-# define NV50_PMC_INTR_EN_0_MASTER_ENABLED (1<<0) +-# define NV50_PMC_ENABLE 0x00000200 +-# define NV50_PMC_ENABLE_PFIFO (1<<8) +-# define NV50_PMC_ENABLE_PGRAPH (1<<12) +- +-#define NV50_PCONNECTOR 0x0000e000 +-#define NV50_PCONNECTOR__LEN 0x1 +-#define NV50_PCONNECTOR__ESIZE 0x1000 +-# define NV50_PCONNECTOR_HOTPLUG_INTR 0x0000e050 +-# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C0 (1<<0) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C1 (1<<1) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C2 (1<<2) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_PLUG_I2C3 (1<<3) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C0 (1<<16) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C1 (1<<17) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C2 (1<<18) +-# define NV50_PCONNECTOR_HOTPLUG_INTR_UNPLUG_I2C3 (1<<19) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL 0x0000e054 +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C0 (1<<0) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C1 (1<<1) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C2 (1<<2) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_PLUG_I2C3 (1<<3) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C0 (1<<16) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C1 (1<<17) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C2 (1<<18) +-# define NV50_PCONNECTOR_HOTPLUG_CTRL_UNPLUG_I2C3 (1<<19) +-# define NV50_PCONNECTOR_HOTPLUG_STATE 0x0000e104 +-# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C0 (1<<2) +-# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C1 (1<<6) +-# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C2 (1<<10) +-# define NV50_PCONNECTOR_HOTPLUG_STATE_PIN_CONNECTED_I2C3 (1<<14) +-# define NV50_PCONNECTOR_I2C_PORT_0 0x0000e138 +-# define NV50_PCONNECTOR_I2C_PORT_1 0x0000e150 +-# define NV50_PCONNECTOR_I2C_PORT_2 0x0000e168 +-# define NV50_PCONNECTOR_I2C_PORT_3 0x0000e180 +-# define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240 +-# define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258 +- +-#define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0) +-#define NV50_AUXCH_DATA_OUT__SIZE 4 +-#define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0) +-#define NV50_AUXCH_DATA_IN__SIZE 4 +-#define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0) +-#define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4) +-#define NV50_AUXCH_CTRL_LINKSTAT 0x01000000 +-#define NV50_AUXCH_CTRL_LINKSTAT_NOT_READY 0x00000000 +-#define NV50_AUXCH_CTRL_LINKSTAT_READY 0x01000000 +-#define NV50_AUXCH_CTRL_LINKEN 0x00100000 +-#define NV50_AUXCH_CTRL_LINKEN_DISABLED 0x00000000 +-#define NV50_AUXCH_CTRL_LINKEN_ENABLED 0x00100000 +-#define NV50_AUXCH_CTRL_EXEC 0x00010000 +-#define NV50_AUXCH_CTRL_EXEC_COMPLETE 0x00000000 +-#define NV50_AUXCH_CTRL_EXEC_IN_PROCESS 0x00010000 +-#define NV50_AUXCH_CTRL_CMD 0x0000f000 +-#define NV50_AUXCH_CTRL_CMD_SHIFT 12 +-#define NV50_AUXCH_CTRL_LEN 0x0000000f +-#define NV50_AUXCH_CTRL_LEN_SHIFT 0 +-#define NV50_AUXCH_STAT(i) ((i) * 0x50 + 0x0000e4e8) +-#define NV50_AUXCH_STAT_STATE 0x10000000 +-#define NV50_AUXCH_STAT_STATE_NOT_READY 0x00000000 +-#define NV50_AUXCH_STAT_STATE_READY 0x10000000 +-#define NV50_AUXCH_STAT_REPLY 0x000f0000 +-#define NV50_AUXCH_STAT_REPLY_AUX 0x00030000 +-#define NV50_AUXCH_STAT_REPLY_AUX_ACK 0x00000000 +-#define NV50_AUXCH_STAT_REPLY_AUX_NACK 0x00010000 +-#define NV50_AUXCH_STAT_REPLY_AUX_DEFER 0x00020000 +-#define NV50_AUXCH_STAT_REPLY_I2C 0x000c0000 +-#define NV50_AUXCH_STAT_REPLY_I2C_ACK 0x00000000 +-#define NV50_AUXCH_STAT_REPLY_I2C_NACK 0x00040000 +-#define NV50_AUXCH_STAT_REPLY_I2C_DEFER 0x00080000 +-#define NV50_AUXCH_STAT_COUNT 0x0000001f +- +-#define NV50_PBUS 0x00088000 +-#define NV50_PBUS__LEN 0x1 +-#define NV50_PBUS__ESIZE 0x1000 +-# define NV50_PBUS_PCI_ID 0x00088000 +-# define NV50_PBUS_PCI_ID_VENDOR_ID 0x0000ffff +-# define NV50_PBUS_PCI_ID_VENDOR_ID__SHIFT 0 +-# define NV50_PBUS_PCI_ID_DEVICE_ID 0xffff0000 +-# define NV50_PBUS_PCI_ID_DEVICE_ID__SHIFT 16 +- +-#define NV50_PFB 0x00100000 +-#define NV50_PFB__LEN 0x1 +-#define NV50_PFB__ESIZE 0x1000 +- +-#define NV50_PEXTDEV 0x00101000 +-#define NV50_PEXTDEV__LEN 0x1 +-#define NV50_PEXTDEV__ESIZE 0x1000 +- +-#define NV50_PROM 0x00300000 +-#define NV50_PROM__LEN 0x1 +-#define NV50_PROM__ESIZE 0x10000 +- +-#define NV50_PGRAPH 0x00400000 +-#define NV50_PGRAPH__LEN 0x1 +-#define NV50_PGRAPH__ESIZE 0x10000 +- +-#define NV50_PDISPLAY 0x00610000 +-#define NV50_PDISPLAY_OBJECTS 0x00610010 +-#define NV50_PDISPLAY_INTR_0 0x00610020 +-#define NV50_PDISPLAY_INTR_1 0x00610024 +-#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC 0x0000000c +-#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_SHIFT 2 +-#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(n) (1 << ((n) + 2)) +-#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0 0x00000004 +-#define NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1 0x00000008 +-#define NV50_PDISPLAY_INTR_1_CLK_UNK10 0x00000010 +-#define NV50_PDISPLAY_INTR_1_CLK_UNK20 0x00000020 +-#define NV50_PDISPLAY_INTR_1_CLK_UNK40 0x00000040 +-#define NV50_PDISPLAY_INTR_EN_0 0x00610028 +-#define NV50_PDISPLAY_INTR_EN_1 0x0061002c +-#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC 0x0000000c +-#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_(n) (1 << ((n) + 2)) +-#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_0 0x00000004 +-#define NV50_PDISPLAY_INTR_EN_1_VBLANK_CRTC_1 0x00000008 +-#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 0x00000010 +-#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 0x00000020 +-#define NV50_PDISPLAY_INTR_EN_1_CLK_UNK40 0x00000040 +-#define NV50_PDISPLAY_UNK30_CTRL 0x00610030 +-#define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK0 0x00000200 +-#define NV50_PDISPLAY_UNK30_CTRL_UPDATE_VCLK1 0x00000400 +-#define NV50_PDISPLAY_UNK30_CTRL_PENDING 0x80000000 +-#define NV50_PDISPLAY_TRAPPED_ADDR(i) ((i) * 0x08 + 0x00610080) +-#define NV50_PDISPLAY_TRAPPED_DATA(i) ((i) * 0x08 + 0x00610084) +-#define NV50_PDISPLAY_EVO_CTRL(i) ((i) * 0x10 + 0x00610200) +-#define NV50_PDISPLAY_EVO_CTRL_DMA 0x00000010 +-#define NV50_PDISPLAY_EVO_CTRL_DMA_DISABLED 0x00000000 +-#define NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED 0x00000010 +-#define NV50_PDISPLAY_EVO_DMA_CB(i) ((i) * 0x10 + 0x00610204) +-#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION 0x00000002 +-#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM 0x00000000 +-#define NV50_PDISPLAY_EVO_DMA_CB_LOCATION_SYSTEM 0x00000002 +-#define NV50_PDISPLAY_EVO_DMA_CB_VALID 0x00000001 +-#define NV50_PDISPLAY_EVO_UNK2(i) ((i) * 0x10 + 0x00610208) +-#define NV50_PDISPLAY_EVO_HASH_TAG(i) ((i) * 0x10 + 0x0061020c) +- +-#define NV50_PDISPLAY_CURSOR 0x00610270 +-#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i) ((i) * 0x10 + 0x00610270) +-#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON 0x00000001 +-#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS 0x00030000 +-#define NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE 0x00010000 +- +-#define NV50_PDISPLAY_PIO_CTRL 0x00610300 +-#define NV50_PDISPLAY_PIO_CTRL_PENDING 0x80000000 +-#define NV50_PDISPLAY_PIO_CTRL_MTHD 0x00001ffc +-#define NV50_PDISPLAY_PIO_CTRL_ENABLED 0x00000001 +-#define NV50_PDISPLAY_PIO_DATA 0x00610304 +- +-#define NV50_PDISPLAY_CRTC_P(i, r) ((i) * 0x540 + NV50_PDISPLAY_CRTC_##r) +-#define NV50_PDISPLAY_CRTC_C(i, r) (4 + (i) * 0x540 + NV50_PDISPLAY_CRTC_##r) +-#define NV50_PDISPLAY_CRTC_UNK_0A18 /* mthd 0x0900 */ 0x00610a18 +-#define NV50_PDISPLAY_CRTC_CLUT_MODE 0x00610a24 +-#define NV50_PDISPLAY_CRTC_INTERLACE 0x00610a48 +-#define NV50_PDISPLAY_CRTC_SCALE_CTRL 0x00610a50 +-#define NV50_PDISPLAY_CRTC_CURSOR_CTRL 0x00610a58 +-#define NV50_PDISPLAY_CRTC_UNK0A78 /* mthd 0x0904 */ 0x00610a78 +-#define NV50_PDISPLAY_CRTC_UNK0AB8 0x00610ab8 +-#define NV50_PDISPLAY_CRTC_DEPTH 0x00610ac8 +-#define NV50_PDISPLAY_CRTC_CLOCK 0x00610ad0 +-#define NV50_PDISPLAY_CRTC_COLOR_CTRL 0x00610ae0 +-#define NV50_PDISPLAY_CRTC_SYNC_START_TO_BLANK_END 0x00610ae8 +-#define NV50_PDISPLAY_CRTC_MODE_UNK1 0x00610af0 +-#define NV50_PDISPLAY_CRTC_DISPLAY_TOTAL 0x00610af8 +-#define NV50_PDISPLAY_CRTC_SYNC_DURATION 0x00610b00 +-#define NV50_PDISPLAY_CRTC_MODE_UNK2 0x00610b08 +-#define NV50_PDISPLAY_CRTC_UNK_0B10 /* mthd 0x0828 */ 0x00610b10 +-#define NV50_PDISPLAY_CRTC_FB_SIZE 0x00610b18 +-#define NV50_PDISPLAY_CRTC_FB_PITCH 0x00610b20 +-#define NV50_PDISPLAY_CRTC_FB_PITCH_LINEAR 0x00100000 +-#define NV50_PDISPLAY_CRTC_FB_POS 0x00610b28 +-#define NV50_PDISPLAY_CRTC_SCALE_CENTER_OFFSET 0x00610b38 +-#define NV50_PDISPLAY_CRTC_REAL_RES 0x00610b40 +-#define NV50_PDISPLAY_CRTC_SCALE_RES1 0x00610b48 +-#define NV50_PDISPLAY_CRTC_SCALE_RES2 0x00610b50 +- +-#define NV50_PDISPLAY_DAC_MODE_CTRL_P(i) (0x00610b58 + (i) * 0x8) +-#define NV50_PDISPLAY_DAC_MODE_CTRL_C(i) (0x00610b5c + (i) * 0x8) +-#define NV50_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610b70 + (i) * 0x8) +-#define NV50_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610b74 + (i) * 0x8) +-#define NV50_PDISPLAY_EXT_MODE_CTRL_P(i) (0x00610b80 + (i) * 0x8) +-#define NV50_PDISPLAY_EXT_MODE_CTRL_C(i) (0x00610b84 + (i) * 0x8) +-#define NV50_PDISPLAY_DAC_MODE_CTRL2_P(i) (0x00610bdc + (i) * 0x8) +-#define NV50_PDISPLAY_DAC_MODE_CTRL2_C(i) (0x00610be0 + (i) * 0x8) +-#define NV90_PDISPLAY_SOR_MODE_CTRL_P(i) (0x00610794 + (i) * 0x8) +-#define NV90_PDISPLAY_SOR_MODE_CTRL_C(i) (0x00610798 + (i) * 0x8) +- +-#define NV50_PDISPLAY_CRTC_CLK 0x00614000 +-#define NV50_PDISPLAY_CRTC_CLK_CTRL1(i) ((i) * 0x800 + 0x614100) +-#define NV50_PDISPLAY_CRTC_CLK_CTRL1_CONNECTED 0x00000600 +-#define NV50_PDISPLAY_CRTC_CLK_VPLL_A(i) ((i) * 0x800 + 0x614104) +-#define NV50_PDISPLAY_CRTC_CLK_VPLL_B(i) ((i) * 0x800 + 0x614108) +-#define NV50_PDISPLAY_CRTC_CLK_CTRL2(i) ((i) * 0x800 + 0x614200) +- +-#define NV50_PDISPLAY_DAC_CLK 0x00614000 +-#define NV50_PDISPLAY_DAC_CLK_CTRL2(i) ((i) * 0x800 + 0x614280) +- +-#define NV50_PDISPLAY_SOR_CLK 0x00614000 +-#define NV50_PDISPLAY_SOR_CLK_CTRL2(i) ((i) * 0x800 + 0x614300) +- +-#define NV50_PDISPLAY_VGACRTC(r) ((r) + 0x619400) +- +-#define NV50_PDISPLAY_DAC 0x0061a000 +-#define NV50_PDISPLAY_DAC_DPMS_CTRL(i) (0x0061a004 + (i) * 0x800) +-#define NV50_PDISPLAY_DAC_DPMS_CTRL_HSYNC_OFF 0x00000001 +-#define NV50_PDISPLAY_DAC_DPMS_CTRL_VSYNC_OFF 0x00000004 +-#define NV50_PDISPLAY_DAC_DPMS_CTRL_BLANKED 0x00000010 +-#define NV50_PDISPLAY_DAC_DPMS_CTRL_OFF 0x00000040 +-#define NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING 0x80000000 +-#define NV50_PDISPLAY_DAC_LOAD_CTRL(i) (0x0061a00c + (i) * 0x800) +-#define NV50_PDISPLAY_DAC_LOAD_CTRL_ACTIVE 0x00100000 +-#define NV50_PDISPLAY_DAC_LOAD_CTRL_PRESENT 0x38000000 +-#define NV50_PDISPLAY_DAC_LOAD_CTRL_DONE 0x80000000 +-#define NV50_PDISPLAY_DAC_CLK_CTRL1(i) (0x0061a010 + (i) * 0x800) +-#define NV50_PDISPLAY_DAC_CLK_CTRL1_CONNECTED 0x00000600 +- +-#define NV50_PDISPLAY_SOR 0x0061c000 +-#define NV50_PDISPLAY_SOR_DPMS_CTRL(i) (0x0061c004 + (i) * 0x800) +-#define NV50_PDISPLAY_SOR_DPMS_CTRL_PENDING 0x80000000 +-#define NV50_PDISPLAY_SOR_DPMS_CTRL_ON 0x00000001 +-#define NV50_PDISPLAY_SOR_CLK_CTRL1(i) (0x0061c008 + (i) * 0x800) +-#define NV50_PDISPLAY_SOR_CLK_CTRL1_CONNECTED 0x00000600 +-#define NV50_PDISPLAY_SOR_DPMS_STATE(i) (0x0061c030 + (i) * 0x800) +-#define NV50_PDISPLAY_SOR_DPMS_STATE_ACTIVE 0x00030000 +-#define NV50_PDISPLAY_SOR_DPMS_STATE_BLANKED 0x00080000 +-#define NV50_PDISPLAY_SOR_DPMS_STATE_WAIT 0x10000000 +-#define NV50_PDISP_SOR_PWM_DIV(i) (0x0061c080 + (i) * 0x800) +-#define NV50_PDISP_SOR_PWM_CTL(i) (0x0061c084 + (i) * 0x800) +-#define NV50_PDISP_SOR_PWM_CTL_NEW 0x80000000 +-#define NVA3_PDISP_SOR_PWM_CTL_UNK 0x40000000 +-#define NV50_PDISP_SOR_PWM_CTL_VAL 0x000007ff +-#define NVA3_PDISP_SOR_PWM_CTL_VAL 0x00ffffff +-#define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80) +-#define NV50_SOR_DP_CTRL_ENABLED 0x00000001 +-#define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000 +-#define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000 +-#define NV50_SOR_DP_CTRL_LANE_0_ENABLED 0x00010000 +-#define NV50_SOR_DP_CTRL_LANE_1_ENABLED 0x00020000 +-#define NV50_SOR_DP_CTRL_LANE_2_ENABLED 0x00040000 +-#define NV50_SOR_DP_CTRL_LANE_3_ENABLED 0x00080000 +-#define NV50_SOR_DP_CTRL_TRAINING_PATTERN 0x0f000000 +-#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000 +-#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000 +-#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000 +-#define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80) +-#define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80) +-#define NV50_SOR_DP_SCFG(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80) +-#define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80) +- +-#define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000) +-#define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000) +-#define NV50_PDISPLAY_USER_GET(i) ((i) * 0x1000 + 0x00640004) +- +-#define NV50_PDISPLAY_CURSOR_USER 0x00647000 +-#define NV50_PDISPLAY_CURSOR_USER_POS_CTRL(i) ((i) * 0x1000 + 0x00647080) +-#define NV50_PDISPLAY_CURSOR_USER_POS(i) ((i) * 0x1000 + 0x00647084) +diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c +deleted file mode 100644 +index 01707e7d..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c ++++ /dev/null +@@ -1,113 +0,0 @@ +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_ttm.h" +- +-struct nouveau_sgdma_be { +- /* this has to be the first field so populate/unpopulated in +- * nouve_bo.c works properly, otherwise have to move them here +- */ +- struct ttm_dma_tt ttm; +- struct drm_device *dev; +- struct nouveau_mem *node; +-}; +- +-static void +-nouveau_sgdma_destroy(struct ttm_tt *ttm) +-{ +- struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; +- +- if (ttm) { +- ttm_dma_tt_fini(&nvbe->ttm); +- kfree(nvbe); +- } +-} +- +-static int +-nv04_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) +-{ +- struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; +- struct nouveau_mem *node = mem->mm_node; +- +- if (ttm->sg) { +- node->sg = ttm->sg; +- node->pages = NULL; +- } else { +- node->sg = NULL; +- node->pages = nvbe->ttm.dma_address; +- } +- node->size = (mem->num_pages << PAGE_SHIFT) >> 12; +- +- nouveau_vm_map(&node->vma[0], node); +- nvbe->node = node; +- return 0; +-} +- +-static int +-nv04_sgdma_unbind(struct ttm_tt *ttm) +-{ +- struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; +- nouveau_vm_unmap(&nvbe->node->vma[0]); +- return 0; +-} +- +-static struct ttm_backend_func nv04_sgdma_backend = { +- .bind = nv04_sgdma_bind, +- .unbind = nv04_sgdma_unbind, +- .destroy = nouveau_sgdma_destroy +-}; +- +-static int +-nv50_sgdma_bind(struct ttm_tt *ttm, struct ttm_mem_reg *mem) +-{ +- struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; +- struct nouveau_mem *node = mem->mm_node; +- +- /* noop: bound in move_notify() */ +- if (ttm->sg) { +- node->sg = ttm->sg; +- node->pages = NULL; +- } else { +- node->sg = NULL; +- node->pages = nvbe->ttm.dma_address; +- } +- node->size = (mem->num_pages << PAGE_SHIFT) >> 12; +- return 0; +-} +- +-static int +-nv50_sgdma_unbind(struct ttm_tt *ttm) +-{ +- /* noop: unbound in move_notify() */ +- return 0; +-} +- +-static struct ttm_backend_func nv50_sgdma_backend = { +- .bind = nv50_sgdma_bind, +- .unbind = nv50_sgdma_unbind, +- .destroy = nouveau_sgdma_destroy +-}; +- +-struct ttm_tt * +-nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, +- unsigned long size, uint32_t page_flags, +- struct page *dummy_read_page) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bdev); +- struct nouveau_sgdma_be *nvbe; +- +- nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL); +- if (!nvbe) +- return NULL; +- +- nvbe->dev = drm->dev; +- if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) +- nvbe->ttm.ttm.func = &nv04_sgdma_backend; +- else +- nvbe->ttm.ttm.func = &nv50_sgdma_backend; +- +- if (ttm_dma_tt_init(&nvbe->ttm, bdev, size, page_flags, dummy_read_page)) +- return NULL; +- return &nvbe->ttm.ttm; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c +deleted file mode 100644 +index 8fbbf309..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c ++++ /dev/null +@@ -1,198 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +- +-#include "nouveau_sysfs.h" +- +-MODULE_PARM_DESC(pstate, "enable sysfs pstate file, which will be moved in the future"); +-int nouveau_pstate; +-module_param_named(pstate, nouveau_pstate, int, 0400); +- +-static inline struct drm_device * +-drm_device(struct device *d) +-{ +- return dev_get_drvdata(d); +-} +- +-#define snappendf(p,r,f,a...) do { \ +- snprintf(p, r, f, ##a); \ +- r -= strlen(p); \ +- p += strlen(p); \ +-} while(0) +- +-static ssize_t +-nouveau_sysfs_pstate_get(struct device *d, struct device_attribute *a, char *b) +-{ +- struct nouveau_sysfs *sysfs = nouveau_sysfs(drm_device(d)); +- struct nvif_control_pstate_info_v0 info = {}; +- size_t cnt = PAGE_SIZE; +- char *buf = b; +- int ret, i; +- +- ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_INFO, +- &info, sizeof(info)); +- if (ret) +- return ret; +- +- for (i = 0; i < info.count + 1; i++) { +- const s32 state = i < info.count ? i : +- NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT; +- struct nvif_control_pstate_attr_v0 attr = { +- .state = state, +- .index = 0, +- }; +- +- ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_ATTR, +- &attr, sizeof(attr)); +- if (ret) +- return ret; +- +- if (i < info.count) +- snappendf(buf, cnt, "%02x:", attr.state); +- else +- snappendf(buf, cnt, "%s:", info.pwrsrc == 0 ? "DC" : +- info.pwrsrc == 1 ? "AC" : +- "--"); +- +- attr.index = 0; +- do { +- attr.state = state; +- ret = nvif_mthd(&sysfs->ctrl, +- NVIF_CONTROL_PSTATE_ATTR, +- &attr, sizeof(attr)); +- if (ret) +- return ret; +- +- snappendf(buf, cnt, " %s %d", attr.name, attr.min); +- if (attr.min != attr.max) +- snappendf(buf, cnt, "-%d", attr.max); +- snappendf(buf, cnt, " %s", attr.unit); +- } while (attr.index); +- +- if (state >= 0) { +- if (info.ustate_ac == state) +- snappendf(buf, cnt, " AC"); +- if (info.ustate_dc == state) +- snappendf(buf, cnt, " DC"); +- if (info.pstate == state) +- snappendf(buf, cnt, " *"); +- } else { +- if (info.ustate_ac < -1) +- snappendf(buf, cnt, " AC"); +- if (info.ustate_dc < -1) +- snappendf(buf, cnt, " DC"); +- } +- +- snappendf(buf, cnt, "\n"); +- } +- +- return strlen(b); +-} +- +-static ssize_t +-nouveau_sysfs_pstate_set(struct device *d, struct device_attribute *a, +- const char *buf, size_t count) +-{ +- struct nouveau_sysfs *sysfs = nouveau_sysfs(drm_device(d)); +- struct nvif_control_pstate_user_v0 args = { .pwrsrc = -EINVAL }; +- long value, ret; +- char *tmp; +- +- if ((tmp = strchr(buf, '\n'))) +- *tmp = '\0'; +- +- if (!strncasecmp(buf, "dc:", 3)) { +- args.pwrsrc = 0; +- buf += 3; +- } else +- if (!strncasecmp(buf, "ac:", 3)) { +- args.pwrsrc = 1; +- buf += 3; +- } +- +- if (!strcasecmp(buf, "none")) +- args.ustate = NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN; +- else +- if (!strcasecmp(buf, "auto")) +- args.ustate = NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON; +- else { +- ret = kstrtol(buf, 16, &value); +- if (ret) +- return ret; +- args.ustate = value; +- } +- +- ret = nvif_mthd(&sysfs->ctrl, NVIF_CONTROL_PSTATE_USER, +- &args, sizeof(args)); +- if (ret < 0) +- return ret; +- +- return count; +-} +- +-static DEVICE_ATTR(pstate, S_IRUGO | S_IWUSR, +- nouveau_sysfs_pstate_get, nouveau_sysfs_pstate_set); +- +-void +-nouveau_sysfs_fini(struct drm_device *dev) +-{ +- struct nouveau_sysfs *sysfs = nouveau_sysfs(dev); +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- +- if (sysfs && sysfs->ctrl.priv) { +- device_remove_file(nv_device_base(nvkm_device(device)), &dev_attr_pstate); +- nvif_object_fini(&sysfs->ctrl); +- } +- +- drm->sysfs = NULL; +- kfree(sysfs); +-} +- +-int +-nouveau_sysfs_init(struct drm_device *dev) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nvif_device *device = &drm->device; +- struct nouveau_sysfs *sysfs; +- int ret; +- +- if (!nouveau_pstate) +- return 0; +- +- sysfs = drm->sysfs = kzalloc(sizeof(*sysfs), GFP_KERNEL); +- if (!sysfs) +- return -ENOMEM; +- +- ret = nvif_object_init(nvif_object(device), NULL, NVDRM_CONTROL, +- NVIF_IOCTL_NEW_V0_CONTROL, NULL, 0, +- &sysfs->ctrl); +- if (ret == 0) +- device_create_file(nv_device_base(nvkm_device(device)), &dev_attr_pstate); +- +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.h b/drivers/gpu/drm/nouveau/nouveau_sysfs.h +deleted file mode 100644 +index 4e5ea924..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_sysfs.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-#ifndef __NOUVEAU_SYSFS_H__ +-#define __NOUVEAU_SYSFS_H__ +- +-#include "nouveau_drm.h" +- +-struct nouveau_sysfs { +- struct nvif_object ctrl; +-}; +- +-static inline struct nouveau_sysfs * +-nouveau_sysfs(struct drm_device *dev) +-{ +- return nouveau_drm(dev)->sysfs; +-} +- +-int nouveau_sysfs_init(struct drm_device *); +-void nouveau_sysfs_fini(struct drm_device *); +- +-extern int nouveau_pstate; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c +deleted file mode 100644 +index 3d1cfcb9..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_ttm.c ++++ /dev/null +@@ -1,435 +0,0 @@ +-/* +- * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA, +- * All Rights Reserved. +- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA, +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sub license, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial portions +- * of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, +- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR +- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE +- * USE OR OTHER DEALINGS IN THE SOFTWARE. +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_ttm.h" +-#include "nouveau_gem.h" +- +-#include "drm_legacy.h" +-static int +-nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) +-{ +- struct nouveau_drm *drm = nouveau_bdev(man->bdev); +- struct nouveau_fb *pfb = nvkm_fb(&drm->device); +- man->priv = pfb; +- return 0; +-} +- +-static int +-nouveau_vram_manager_fini(struct ttm_mem_type_manager *man) +-{ +- man->priv = NULL; +- return 0; +-} +- +-static inline void +-nouveau_mem_node_cleanup(struct nouveau_mem *node) +-{ +- if (node->vma[0].node) { +- nouveau_vm_unmap(&node->vma[0]); +- nouveau_vm_put(&node->vma[0]); +- } +- +- if (node->vma[1].node) { +- nouveau_vm_unmap(&node->vma[1]); +- nouveau_vm_put(&node->vma[1]); +- } +-} +- +-static void +-nouveau_vram_manager_del(struct ttm_mem_type_manager *man, +- struct ttm_mem_reg *mem) +-{ +- struct nouveau_drm *drm = nouveau_bdev(man->bdev); +- struct nouveau_fb *pfb = nvkm_fb(&drm->device); +- nouveau_mem_node_cleanup(mem->mm_node); +- pfb->ram->put(pfb, (struct nouveau_mem **)&mem->mm_node); +-} +- +-static int +-nouveau_vram_manager_new(struct ttm_mem_type_manager *man, +- struct ttm_buffer_object *bo, +- const struct ttm_place *place, +- struct ttm_mem_reg *mem) +-{ +- struct nouveau_drm *drm = nouveau_bdev(man->bdev); +- struct nouveau_fb *pfb = nvkm_fb(&drm->device); +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- struct nouveau_mem *node; +- u32 size_nc = 0; +- int ret; +- +- if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) +- size_nc = 1 << nvbo->page_shift; +- +- ret = pfb->ram->get(pfb, mem->num_pages << PAGE_SHIFT, +- mem->page_alignment << PAGE_SHIFT, size_nc, +- (nvbo->tile_flags >> 8) & 0x3ff, &node); +- if (ret) { +- mem->mm_node = NULL; +- return (ret == -ENOSPC) ? 0 : ret; +- } +- +- node->page_shift = nvbo->page_shift; +- +- mem->mm_node = node; +- mem->start = node->offset >> PAGE_SHIFT; +- return 0; +-} +- +-static void +-nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +-{ +- struct nouveau_fb *pfb = man->priv; +- struct nouveau_mm *mm = &pfb->vram; +- struct nouveau_mm_node *r; +- u32 total = 0, free = 0; +- +- mutex_lock(&nv_subdev(pfb)->mutex); +- list_for_each_entry(r, &mm->nodes, nl_entry) { +- printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n", +- prefix, r->type, ((u64)r->offset << 12), +- (((u64)r->offset + r->length) << 12)); +- +- total += r->length; +- if (!r->type) +- free += r->length; +- } +- mutex_unlock(&nv_subdev(pfb)->mutex); +- +- printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n", +- prefix, (u64)total << 12, (u64)free << 12); +- printk(KERN_DEBUG "%s block: 0x%08x\n", +- prefix, mm->block_size << 12); +-} +- +-const struct ttm_mem_type_manager_func nouveau_vram_manager = { +- nouveau_vram_manager_init, +- nouveau_vram_manager_fini, +- nouveau_vram_manager_new, +- nouveau_vram_manager_del, +- nouveau_vram_manager_debug +-}; +- +-static int +-nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) +-{ +- return 0; +-} +- +-static int +-nouveau_gart_manager_fini(struct ttm_mem_type_manager *man) +-{ +- return 0; +-} +- +-static void +-nouveau_gart_manager_del(struct ttm_mem_type_manager *man, +- struct ttm_mem_reg *mem) +-{ +- nouveau_mem_node_cleanup(mem->mm_node); +- kfree(mem->mm_node); +- mem->mm_node = NULL; +-} +- +-static int +-nouveau_gart_manager_new(struct ttm_mem_type_manager *man, +- struct ttm_buffer_object *bo, +- const struct ttm_place *place, +- struct ttm_mem_reg *mem) +-{ +- struct nouveau_drm *drm = nouveau_bdev(bo->bdev); +- struct nouveau_bo *nvbo = nouveau_bo(bo); +- struct nouveau_mem *node; +- +- node = kzalloc(sizeof(*node), GFP_KERNEL); +- if (!node) +- return -ENOMEM; +- +- node->page_shift = 12; +- +- switch (drm->device.info.family) { +- case NV_DEVICE_INFO_V0_TESLA: +- if (drm->device.info.chipset != 0x50) +- node->memtype = (nvbo->tile_flags & 0x7f00) >> 8; +- break; +- case NV_DEVICE_INFO_V0_FERMI: +- case NV_DEVICE_INFO_V0_KEPLER: +- node->memtype = (nvbo->tile_flags & 0xff00) >> 8; +- break; +- default: +- break; +- } +- +- mem->mm_node = node; +- mem->start = 0; +- return 0; +-} +- +-static void +-nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +-{ +-} +- +-const struct ttm_mem_type_manager_func nouveau_gart_manager = { +- nouveau_gart_manager_init, +- nouveau_gart_manager_fini, +- nouveau_gart_manager_new, +- nouveau_gart_manager_del, +- nouveau_gart_manager_debug +-}; +- +-/*XXX*/ +-#include +-static int +-nv04_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) +-{ +- struct nouveau_drm *drm = nouveau_bdev(man->bdev); +- struct nouveau_vmmgr *vmm = nvkm_vmmgr(&drm->device); +- struct nv04_vmmgr_priv *priv = (void *)vmm; +- struct nouveau_vm *vm = NULL; +- nouveau_vm_ref(priv->vm, &vm, NULL); +- man->priv = vm; +- return 0; +-} +- +-static int +-nv04_gart_manager_fini(struct ttm_mem_type_manager *man) +-{ +- struct nouveau_vm *vm = man->priv; +- nouveau_vm_ref(NULL, &vm, NULL); +- man->priv = NULL; +- return 0; +-} +- +-static void +-nv04_gart_manager_del(struct ttm_mem_type_manager *man, struct ttm_mem_reg *mem) +-{ +- struct nouveau_mem *node = mem->mm_node; +- if (node->vma[0].node) +- nouveau_vm_put(&node->vma[0]); +- kfree(mem->mm_node); +- mem->mm_node = NULL; +-} +- +-static int +-nv04_gart_manager_new(struct ttm_mem_type_manager *man, +- struct ttm_buffer_object *bo, +- const struct ttm_place *place, +- struct ttm_mem_reg *mem) +-{ +- struct nouveau_mem *node; +- int ret; +- +- node = kzalloc(sizeof(*node), GFP_KERNEL); +- if (!node) +- return -ENOMEM; +- +- node->page_shift = 12; +- +- ret = nouveau_vm_get(man->priv, mem->num_pages << 12, node->page_shift, +- NV_MEM_ACCESS_RW, &node->vma[0]); +- if (ret) { +- kfree(node); +- return ret; +- } +- +- mem->mm_node = node; +- mem->start = node->vma[0].offset >> PAGE_SHIFT; +- return 0; +-} +- +-static void +-nv04_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix) +-{ +-} +- +-const struct ttm_mem_type_manager_func nv04_gart_manager = { +- nv04_gart_manager_init, +- nv04_gart_manager_fini, +- nv04_gart_manager_new, +- nv04_gart_manager_del, +- nv04_gart_manager_debug +-}; +- +-int +-nouveau_ttm_mmap(struct file *filp, struct vm_area_struct *vma) +-{ +- struct drm_file *file_priv = filp->private_data; +- struct nouveau_drm *drm = nouveau_drm(file_priv->minor->dev); +- +- if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) +- return drm_legacy_mmap(filp, vma); +- +- return ttm_bo_mmap(filp, vma, &drm->ttm.bdev); +-} +- +-static int +-nouveau_ttm_mem_global_init(struct drm_global_reference *ref) +-{ +- return ttm_mem_global_init(ref->object); +-} +- +-static void +-nouveau_ttm_mem_global_release(struct drm_global_reference *ref) +-{ +- ttm_mem_global_release(ref->object); +-} +- +-int +-nouveau_ttm_global_init(struct nouveau_drm *drm) +-{ +- struct drm_global_reference *global_ref; +- int ret; +- +- global_ref = &drm->ttm.mem_global_ref; +- global_ref->global_type = DRM_GLOBAL_TTM_MEM; +- global_ref->size = sizeof(struct ttm_mem_global); +- global_ref->init = &nouveau_ttm_mem_global_init; +- global_ref->release = &nouveau_ttm_mem_global_release; +- +- ret = drm_global_item_ref(global_ref); +- if (unlikely(ret != 0)) { +- DRM_ERROR("Failed setting up TTM memory accounting\n"); +- drm->ttm.mem_global_ref.release = NULL; +- return ret; +- } +- +- drm->ttm.bo_global_ref.mem_glob = global_ref->object; +- global_ref = &drm->ttm.bo_global_ref.ref; +- global_ref->global_type = DRM_GLOBAL_TTM_BO; +- global_ref->size = sizeof(struct ttm_bo_global); +- global_ref->init = &ttm_bo_global_init; +- global_ref->release = &ttm_bo_global_release; +- +- ret = drm_global_item_ref(global_ref); +- if (unlikely(ret != 0)) { +- DRM_ERROR("Failed setting up TTM BO subsystem\n"); +- drm_global_item_unref(&drm->ttm.mem_global_ref); +- drm->ttm.mem_global_ref.release = NULL; +- return ret; +- } +- +- return 0; +-} +- +-void +-nouveau_ttm_global_release(struct nouveau_drm *drm) +-{ +- if (drm->ttm.mem_global_ref.release == NULL) +- return; +- +- drm_global_item_unref(&drm->ttm.bo_global_ref.ref); +- drm_global_item_unref(&drm->ttm.mem_global_ref); +- drm->ttm.mem_global_ref.release = NULL; +-} +- +-int +-nouveau_ttm_init(struct nouveau_drm *drm) +-{ +- struct drm_device *dev = drm->dev; +- u32 bits; +- int ret; +- +- bits = nvkm_vmmgr(&drm->device)->dma_bits; +- if (nv_device_is_pci(nvkm_device(&drm->device))) { +- if (drm->agp.stat == ENABLED || +- !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) +- bits = 32; +- +- ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); +- if (ret) +- return ret; +- +- ret = pci_set_consistent_dma_mask(dev->pdev, +- DMA_BIT_MASK(bits)); +- if (ret) +- pci_set_consistent_dma_mask(dev->pdev, +- DMA_BIT_MASK(32)); +- } +- +- ret = nouveau_ttm_global_init(drm); +- if (ret) +- return ret; +- +- ret = ttm_bo_device_init(&drm->ttm.bdev, +- drm->ttm.bo_global_ref.ref.object, +- &nouveau_bo_driver, +- dev->anon_inode->i_mapping, +- DRM_FILE_PAGE_OFFSET, +- bits <= 32 ? true : false); +- if (ret) { +- NV_ERROR(drm, "error initialising bo driver, %d\n", ret); +- return ret; +- } +- +- /* VRAM init */ +- drm->gem.vram_available = drm->device.info.ram_user; +- +- ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_VRAM, +- drm->gem.vram_available >> PAGE_SHIFT); +- if (ret) { +- NV_ERROR(drm, "VRAM mm init failed, %d\n", ret); +- return ret; +- } +- +- drm->ttm.mtrr = arch_phys_wc_add(nv_device_resource_start(nvkm_device(&drm->device), 1), +- nv_device_resource_len(nvkm_device(&drm->device), 1)); +- +- /* GART init */ +- if (drm->agp.stat != ENABLED) { +- drm->gem.gart_available = nvkm_vmmgr(&drm->device)->limit; +- } else { +- drm->gem.gart_available = drm->agp.size; +- } +- +- ret = ttm_bo_init_mm(&drm->ttm.bdev, TTM_PL_TT, +- drm->gem.gart_available >> PAGE_SHIFT); +- if (ret) { +- NV_ERROR(drm, "GART mm init failed, %d\n", ret); +- return ret; +- } +- +- NV_INFO(drm, "VRAM: %d MiB\n", (u32)(drm->gem.vram_available >> 20)); +- NV_INFO(drm, "GART: %d MiB\n", (u32)(drm->gem.gart_available >> 20)); +- return 0; +-} +- +-void +-nouveau_ttm_fini(struct nouveau_drm *drm) +-{ +- mutex_lock(&drm->dev->struct_mutex); +- ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_VRAM); +- ttm_bo_clean_mm(&drm->ttm.bdev, TTM_PL_TT); +- mutex_unlock(&drm->dev->struct_mutex); +- +- ttm_bo_device_release(&drm->ttm.bdev); +- +- nouveau_ttm_global_release(drm); +- +- arch_phys_wc_del(drm->ttm.mtrr); +- drm->ttm.mtrr = 0; +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.h b/drivers/gpu/drm/nouveau/nouveau_ttm.h +deleted file mode 100644 +index 25b0de41..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_ttm.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-#ifndef __NOUVEAU_TTM_H__ +-#define __NOUVEAU_TTM_H__ +- +-static inline struct nouveau_drm * +-nouveau_bdev(struct ttm_bo_device *bd) +-{ +- return container_of(bd, struct nouveau_drm, ttm.bdev); +-} +- +-extern const struct ttm_mem_type_manager_func nouveau_vram_manager; +-extern const struct ttm_mem_type_manager_func nouveau_gart_manager; +-extern const struct ttm_mem_type_manager_func nv04_gart_manager; +- +-struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *, +- unsigned long size, u32 page_flags, +- struct page *dummy_read_page); +- +-int nouveau_ttm_init(struct nouveau_drm *drm); +-void nouveau_ttm_fini(struct nouveau_drm *drm); +-int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); +- +-int nouveau_ttm_global_init(struct nouveau_drm *); +-void nouveau_ttm_global_release(struct nouveau_drm *); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c +deleted file mode 100644 +index cb1182d7..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_usif.c ++++ /dev/null +@@ -1,384 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_usif.h" +- +-#include +-#include +-#include +-#include +-#include +- +-struct usif_notify_p { +- struct drm_pending_event base; +- struct { +- struct drm_event base; +- u8 data[]; +- } e; +-}; +- +-struct usif_notify { +- struct list_head head; +- atomic_t enabled; +- u32 handle; +- u16 reply; +- u8 route; +- u64 token; +- struct usif_notify_p *p; +-}; +- +-static inline struct usif_notify * +-usif_notify_find(struct drm_file *filp, u32 handle) +-{ +- struct nouveau_cli *cli = nouveau_cli(filp); +- struct usif_notify *ntfy; +- list_for_each_entry(ntfy, &cli->notifys, head) { +- if (ntfy->handle == handle) +- return ntfy; +- } +- return NULL; +-} +- +-static inline void +-usif_notify_dtor(struct usif_notify *ntfy) +-{ +- list_del(&ntfy->head); +- kfree(ntfy); +-} +- +-int +-usif_notify(const void *header, u32 length, const void *data, u32 size) +-{ +- struct usif_notify *ntfy = NULL; +- const union { +- struct nvif_notify_rep_v0 v0; +- } *rep = header; +- struct drm_device *dev; +- struct drm_file *filp; +- unsigned long flags; +- +- if (length == sizeof(rep->v0) && rep->v0.version == 0) { +- if (WARN_ON(!(ntfy = (void *)(unsigned long)rep->v0.token))) +- return NVIF_NOTIFY_DROP; +- BUG_ON(rep->v0.route != NVDRM_NOTIFY_USIF); +- } else +- if (WARN_ON(1)) +- return NVIF_NOTIFY_DROP; +- +- if (WARN_ON(!ntfy->p || ntfy->reply != (length + size))) +- return NVIF_NOTIFY_DROP; +- filp = ntfy->p->base.file_priv; +- dev = filp->minor->dev; +- +- memcpy(&ntfy->p->e.data[0], header, length); +- memcpy(&ntfy->p->e.data[length], data, size); +- switch (rep->v0.version) { +- case 0: { +- struct nvif_notify_rep_v0 *rep = (void *)ntfy->p->e.data; +- rep->route = ntfy->route; +- rep->token = ntfy->token; +- } +- break; +- default: +- BUG_ON(1); +- break; +- } +- +- spin_lock_irqsave(&dev->event_lock, flags); +- if (!WARN_ON(filp->event_space < ntfy->p->e.base.length)) { +- list_add_tail(&ntfy->p->base.link, &filp->event_list); +- filp->event_space -= ntfy->p->e.base.length; +- } +- wake_up_interruptible(&filp->event_wait); +- spin_unlock_irqrestore(&dev->event_lock, flags); +- atomic_set(&ntfy->enabled, 0); +- return NVIF_NOTIFY_DROP; +-} +- +-static int +-usif_notify_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) +-{ +- struct nouveau_cli *cli = nouveau_cli(f); +- struct nvif_client *client = &cli->base; +- union { +- struct nvif_ioctl_ntfy_new_v0 v0; +- } *args = data; +- union { +- struct nvif_notify_req_v0 v0; +- } *req; +- struct usif_notify *ntfy; +- int ret; +- +- if (nvif_unpack(args->v0, 0, 0, true)) { +- if (usif_notify_find(f, args->v0.index)) +- return -EEXIST; +- } else +- return ret; +- req = data; +- +- if (!(ntfy = kmalloc(sizeof(*ntfy), GFP_KERNEL))) +- return -ENOMEM; +- atomic_set(&ntfy->enabled, 0); +- +- if (nvif_unpack(req->v0, 0, 0, true)) { +- ntfy->reply = sizeof(struct nvif_notify_rep_v0) + req->v0.reply; +- ntfy->route = req->v0.route; +- ntfy->token = req->v0.token; +- req->v0.route = NVDRM_NOTIFY_USIF; +- req->v0.token = (unsigned long)(void *)ntfy; +- ret = nvif_client_ioctl(client, argv, argc); +- req->v0.token = ntfy->token; +- req->v0.route = ntfy->route; +- ntfy->handle = args->v0.index; +- } +- +- if (ret == 0) +- list_add(&ntfy->head, &cli->notifys); +- if (ret) +- kfree(ntfy); +- return ret; +-} +- +-static int +-usif_notify_del(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) +-{ +- struct nouveau_cli *cli = nouveau_cli(f); +- struct nvif_client *client = &cli->base; +- union { +- struct nvif_ioctl_ntfy_del_v0 v0; +- } *args = data; +- struct usif_notify *ntfy; +- int ret; +- +- if (nvif_unpack(args->v0, 0, 0, true)) { +- if (!(ntfy = usif_notify_find(f, args->v0.index))) +- return -ENOENT; +- } else +- return ret; +- +- ret = nvif_client_ioctl(client, argv, argc); +- if (ret == 0) +- usif_notify_dtor(ntfy); +- return ret; +-} +- +-static int +-usif_notify_get(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) +-{ +- struct nouveau_cli *cli = nouveau_cli(f); +- struct nvif_client *client = &cli->base; +- union { +- struct nvif_ioctl_ntfy_del_v0 v0; +- } *args = data; +- struct usif_notify *ntfy; +- int ret; +- +- if (nvif_unpack(args->v0, 0, 0, true)) { +- if (!(ntfy = usif_notify_find(f, args->v0.index))) +- return -ENOENT; +- } else +- return ret; +- +- if (atomic_xchg(&ntfy->enabled, 1)) +- return 0; +- +- ntfy->p = kmalloc(sizeof(*ntfy->p) + ntfy->reply, GFP_KERNEL); +- if (ret = -ENOMEM, !ntfy->p) +- goto done; +- ntfy->p->base.event = &ntfy->p->e.base; +- ntfy->p->base.file_priv = f; +- ntfy->p->base.pid = current->pid; +- ntfy->p->base.destroy =(void(*)(struct drm_pending_event *))kfree; +- ntfy->p->e.base.type = DRM_NOUVEAU_EVENT_NVIF; +- ntfy->p->e.base.length = sizeof(ntfy->p->e.base) + ntfy->reply; +- +- ret = nvif_client_ioctl(client, argv, argc); +-done: +- if (ret) { +- atomic_set(&ntfy->enabled, 0); +- kfree(ntfy->p); +- } +- return ret; +-} +- +-static int +-usif_notify_put(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) +-{ +- struct nouveau_cli *cli = nouveau_cli(f); +- struct nvif_client *client = &cli->base; +- union { +- struct nvif_ioctl_ntfy_put_v0 v0; +- } *args = data; +- struct usif_notify *ntfy; +- int ret; +- +- if (nvif_unpack(args->v0, 0, 0, true)) { +- if (!(ntfy = usif_notify_find(f, args->v0.index))) +- return -ENOENT; +- } else +- return ret; +- +- ret = nvif_client_ioctl(client, argv, argc); +- if (ret == 0 && atomic_xchg(&ntfy->enabled, 0)) +- kfree(ntfy->p); +- return ret; +-} +- +-struct usif_object { +- struct list_head head; +- struct list_head ntfy; +- u8 route; +- u64 token; +-}; +- +-static void +-usif_object_dtor(struct usif_object *object) +-{ +- list_del(&object->head); +- kfree(object); +-} +- +-static int +-usif_object_new(struct drm_file *f, void *data, u32 size, void *argv, u32 argc) +-{ +- struct nouveau_cli *cli = nouveau_cli(f); +- struct nvif_client *client = &cli->base; +- union { +- struct nvif_ioctl_new_v0 v0; +- } *args = data; +- struct usif_object *object; +- int ret; +- +- if (!(object = kmalloc(sizeof(*object), GFP_KERNEL))) +- return -ENOMEM; +- list_add(&object->head, &cli->objects); +- +- if (nvif_unpack(args->v0, 0, 0, true)) { +- object->route = args->v0.route; +- object->token = args->v0.token; +- args->v0.route = NVDRM_OBJECT_USIF; +- args->v0.token = (unsigned long)(void *)object; +- ret = nvif_client_ioctl(client, argv, argc); +- args->v0.token = object->token; +- args->v0.route = object->route; +- } +- +- if (ret) +- usif_object_dtor(object); +- return ret; +-} +- +-int +-usif_ioctl(struct drm_file *filp, void __user *user, u32 argc) +-{ +- struct nouveau_cli *cli = nouveau_cli(filp); +- struct nvif_client *client = &cli->base; +- void *data = kmalloc(argc, GFP_KERNEL); +- u32 size = argc; +- union { +- struct nvif_ioctl_v0 v0; +- } *argv = data; +- struct usif_object *object; +- u8 owner; +- int ret; +- +- if (ret = -ENOMEM, !argv) +- goto done; +- if (ret = -EFAULT, copy_from_user(argv, user, size)) +- goto done; +- +- if (nvif_unpack(argv->v0, 0, 0, true)) { +- /* block access to objects not created via this interface */ +- owner = argv->v0.owner; +- argv->v0.owner = NVDRM_OBJECT_USIF; +- } else +- goto done; +- +- mutex_lock(&cli->mutex); +- switch (argv->v0.type) { +- case NVIF_IOCTL_V0_NEW: +- /* ... except if we're creating children */ +- argv->v0.owner = NVIF_IOCTL_V0_OWNER_ANY; +- ret = usif_object_new(filp, data, size, argv, argc); +- break; +- case NVIF_IOCTL_V0_NTFY_NEW: +- ret = usif_notify_new(filp, data, size, argv, argc); +- break; +- case NVIF_IOCTL_V0_NTFY_DEL: +- ret = usif_notify_del(filp, data, size, argv, argc); +- break; +- case NVIF_IOCTL_V0_NTFY_GET: +- ret = usif_notify_get(filp, data, size, argv, argc); +- break; +- case NVIF_IOCTL_V0_NTFY_PUT: +- ret = usif_notify_put(filp, data, size, argv, argc); +- break; +- default: +- ret = nvif_client_ioctl(client, argv, argc); +- break; +- } +- if (argv->v0.route == NVDRM_OBJECT_USIF) { +- object = (void *)(unsigned long)argv->v0.token; +- argv->v0.route = object->route; +- argv->v0.token = object->token; +- if (ret == 0 && argv->v0.type == NVIF_IOCTL_V0_DEL) { +- list_del(&object->head); +- kfree(object); +- } +- } else { +- argv->v0.route = NVIF_IOCTL_V0_ROUTE_HIDDEN; +- argv->v0.token = 0; +- } +- argv->v0.owner = owner; +- mutex_unlock(&cli->mutex); +- +- if (copy_to_user(user, argv, argc)) +- ret = -EFAULT; +-done: +- kfree(argv); +- return ret; +-} +- +-void +-usif_client_fini(struct nouveau_cli *cli) +-{ +- struct usif_object *object, *otemp; +- struct usif_notify *notify, *ntemp; +- +- list_for_each_entry_safe(notify, ntemp, &cli->notifys, head) { +- usif_notify_dtor(notify); +- } +- +- list_for_each_entry_safe(object, otemp, &cli->objects, head) { +- usif_object_dtor(object); +- } +-} +- +-void +-usif_client_init(struct nouveau_cli *cli) +-{ +- INIT_LIST_HEAD(&cli->objects); +- INIT_LIST_HEAD(&cli->notifys); +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.h b/drivers/gpu/drm/nouveau/nouveau_usif.h +deleted file mode 100644 +index c037e3ae..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_usif.h ++++ /dev/null +@@ -1,9 +0,0 @@ +-#ifndef __NOUVEAU_USIF_H__ +-#define __NOUVEAU_USIF_H__ +- +-void usif_client_init(struct nouveau_cli *); +-void usif_client_fini(struct nouveau_cli *); +-int usif_ioctl(struct drm_file *, void __user *, u32); +-int usif_notify(const void *, u32, const void *, u32); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c +deleted file mode 100644 +index c7592ec8..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_vga.c ++++ /dev/null +@@ -1,129 +0,0 @@ +-#include +-#include +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_acpi.h" +-#include "nouveau_fbcon.h" +-#include "nouveau_vga.h" +- +-static unsigned int +-nouveau_vga_set_decode(void *priv, bool state) +-{ +- struct nvif_device *device = &nouveau_drm(priv)->device; +- +- if (device->info.family == NV_DEVICE_INFO_V0_CURIE && +- device->info.chipset >= 0x4c) +- nvif_wr32(device, 0x088060, state); +- else +- if (device->info.chipset >= 0x40) +- nvif_wr32(device, 0x088054, state); +- else +- nvif_wr32(device, 0x001854, state); +- +- if (state) +- return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | +- VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; +- else +- return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; +-} +- +-static void +-nouveau_switcheroo_set_state(struct pci_dev *pdev, +- enum vga_switcheroo_state state) +-{ +- struct drm_device *dev = pci_get_drvdata(pdev); +- +- if ((nouveau_is_optimus() || nouveau_is_v1_dsm()) && state == VGA_SWITCHEROO_OFF) +- return; +- +- if (state == VGA_SWITCHEROO_ON) { +- printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); +- dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; +- nouveau_pmops_resume(&pdev->dev); +- drm_kms_helper_poll_enable(dev); +- dev->switch_power_state = DRM_SWITCH_POWER_ON; +- } else { +- printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); +- dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; +- drm_kms_helper_poll_disable(dev); +- nouveau_switcheroo_optimus_dsm(); +- nouveau_pmops_suspend(&pdev->dev); +- dev->switch_power_state = DRM_SWITCH_POWER_OFF; +- } +-} +- +-static void +-nouveau_switcheroo_reprobe(struct pci_dev *pdev) +-{ +- struct drm_device *dev = pci_get_drvdata(pdev); +- nouveau_fbcon_output_poll_changed(dev); +-} +- +-static bool +-nouveau_switcheroo_can_switch(struct pci_dev *pdev) +-{ +- struct drm_device *dev = pci_get_drvdata(pdev); +- +- /* +- * FIXME: open_count is protected by drm_global_mutex but that would lead to +- * locking inversion with the driver load path. And the access here is +- * completely racy anyway. So don't bother with locking for now. +- */ +- return dev->open_count == 0; +-} +- +-static const struct vga_switcheroo_client_ops +-nouveau_switcheroo_ops = { +- .set_gpu_state = nouveau_switcheroo_set_state, +- .reprobe = nouveau_switcheroo_reprobe, +- .can_switch = nouveau_switcheroo_can_switch, +-}; +- +-void +-nouveau_vga_init(struct nouveau_drm *drm) +-{ +- struct drm_device *dev = drm->dev; +- bool runtime = false; +- +- /* only relevant for PCI devices */ +- if (!dev->pdev) +- return; +- +- vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); +- +- if (nouveau_runtime_pm == 1) +- runtime = true; +- if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm())) +- runtime = true; +- vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops, runtime); +- +- if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus()) +- vga_switcheroo_init_domain_pm_ops(drm->dev->dev, &drm->vga_pm_domain); +-} +- +-void +-nouveau_vga_fini(struct nouveau_drm *drm) +-{ +- struct drm_device *dev = drm->dev; +- bool runtime = false; +- +- if (nouveau_runtime_pm == 1) +- runtime = true; +- if ((nouveau_runtime_pm == -1) && (nouveau_is_optimus() || nouveau_is_v1_dsm())) +- runtime = true; +- +- vga_switcheroo_unregister_client(dev->pdev); +- if (runtime && nouveau_is_v1_dsm() && !nouveau_is_optimus()) +- vga_switcheroo_fini_domain_pm_ops(drm->dev->dev); +- vga_client_register(dev->pdev, NULL, NULL, NULL); +-} +- +- +-void +-nouveau_vga_lastclose(struct drm_device *dev) +-{ +- vga_switcheroo_process_delayed_switch(); +-} +diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.h b/drivers/gpu/drm/nouveau/nouveau_vga.h +deleted file mode 100644 +index ea3ad697..00000000 +--- a/drivers/gpu/drm/nouveau/nouveau_vga.h ++++ /dev/null +@@ -1,8 +0,0 @@ +-#ifndef __NOUVEAU_VGA_H__ +-#define __NOUVEAU_VGA_H__ +- +-void nouveau_vga_init(struct nouveau_drm *); +-void nouveau_vga_fini(struct nouveau_drm *); +-void nouveau_vga_lastclose(struct drm_device *dev); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c +deleted file mode 100644 +index 4ef602c5..00000000 +--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c ++++ /dev/null +@@ -1,280 +0,0 @@ +-/* +- * Copyright 2009 Ben Skeggs +- * Copyright 2008 Stuart Bennett +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +- * DEALINGS IN THE SOFTWARE. +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fbcon.h" +- +-int +-nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- ret = RING_SPACE(chan, 4); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubImageBlit, 0x0300, 3); +- OUT_RING(chan, (region->sy << 16) | region->sx); +- OUT_RING(chan, (region->dy << 16) | region->dx); +- OUT_RING(chan, (region->height << 16) | region->width); +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- ret = RING_SPACE(chan, 7); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); +- OUT_RING(chan, (rect->rop != ROP_COPY) ? 1 : 3); +- BEGIN_NV04(chan, NvSubGdiRect, 0x03fc, 1); +- if (info->fix.visual == FB_VISUAL_TRUECOLOR || +- info->fix.visual == FB_VISUAL_DIRECTCOLOR) +- OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); +- else +- OUT_RING(chan, rect->color); +- BEGIN_NV04(chan, NvSubGdiRect, 0x0400, 2); +- OUT_RING(chan, (rect->dx << 16) | rect->dy); +- OUT_RING(chan, (rect->width << 16) | rect->height); +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- uint32_t fg; +- uint32_t bg; +- uint32_t dsize; +- uint32_t width; +- uint32_t *data = (uint32_t *)image->data; +- int ret; +- +- if (image->depth != 1) +- return -ENODEV; +- +- ret = RING_SPACE(chan, 8); +- if (ret) +- return ret; +- +- width = ALIGN(image->width, 8); +- dsize = ALIGN(width * image->height, 32) >> 5; +- +- if (info->fix.visual == FB_VISUAL_TRUECOLOR || +- info->fix.visual == FB_VISUAL_DIRECTCOLOR) { +- fg = ((uint32_t *) info->pseudo_palette)[image->fg_color]; +- bg = ((uint32_t *) info->pseudo_palette)[image->bg_color]; +- } else { +- fg = image->fg_color; +- bg = image->bg_color; +- } +- +- BEGIN_NV04(chan, NvSubGdiRect, 0x0be4, 7); +- OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); +- OUT_RING(chan, ((image->dy + image->height) << 16) | +- ((image->dx + image->width) & 0xffff)); +- OUT_RING(chan, bg); +- OUT_RING(chan, fg); +- OUT_RING(chan, (image->height << 16) | width); +- OUT_RING(chan, (image->height << 16) | image->width); +- OUT_RING(chan, (image->dy << 16) | (image->dx & 0xffff)); +- +- while (dsize) { +- int iter_len = dsize > 128 ? 128 : dsize; +- +- ret = RING_SPACE(chan, iter_len + 1); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSubGdiRect, 0x0c00, iter_len); +- OUT_RINGp(chan, data, iter_len); +- data += iter_len; +- dsize -= iter_len; +- } +- +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nv04_fbcon_accel_init(struct fb_info *info) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct drm_device *dev = nfbdev->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_channel *chan = drm->channel; +- struct nvif_device *device = &drm->device; +- int surface_fmt, pattern_fmt, rect_fmt; +- int ret; +- +- switch (info->var.bits_per_pixel) { +- case 8: +- surface_fmt = 1; +- pattern_fmt = 3; +- rect_fmt = 3; +- break; +- case 16: +- surface_fmt = 4; +- pattern_fmt = 1; +- rect_fmt = 1; +- break; +- case 32: +- switch (info->var.transp.length) { +- case 0: /* depth 24 */ +- case 8: /* depth 32 */ +- break; +- default: +- return -EINVAL; +- } +- +- surface_fmt = 6; +- pattern_fmt = 3; +- rect_fmt = 3; +- break; +- default: +- return -EINVAL; +- } +- +- ret = nvif_object_init(chan->object, NULL, 0x0062, +- device->info.family >= NV_DEVICE_INFO_V0_CELSIUS ? +- 0x0062 : 0x0042, NULL, 0, &nfbdev->surf2d); +- if (ret) +- return ret; +- +- ret = nvif_object_init(chan->object, NULL, 0x0019, 0x0019, NULL, 0, +- &nfbdev->clip); +- if (ret) +- return ret; +- +- ret = nvif_object_init(chan->object, NULL, 0x0043, 0x0043, NULL, 0, +- &nfbdev->rop); +- if (ret) +- return ret; +- +- ret = nvif_object_init(chan->object, NULL, 0x0044, 0x0044, NULL, 0, +- &nfbdev->patt); +- if (ret) +- return ret; +- +- ret = nvif_object_init(chan->object, NULL, 0x004a, 0x004a, NULL, 0, +- &nfbdev->gdi); +- if (ret) +- return ret; +- +- ret = nvif_object_init(chan->object, NULL, 0x005f, +- device->info.chipset >= 0x11 ? 0x009f : 0x005f, +- NULL, 0, &nfbdev->blit); +- if (ret) +- return ret; +- +- if (RING_SPACE(chan, 49)) { +- nouveau_fbcon_gpu_lockup(info); +- return 0; +- } +- +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); +- OUT_RING(chan, nfbdev->surf2d.handle); +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2); +- OUT_RING(chan, chan->vram.handle); +- OUT_RING(chan, chan->vram.handle); +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4); +- OUT_RING(chan, surface_fmt); +- OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); +- OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); +- OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); +- +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); +- OUT_RING(chan, nfbdev->rop.handle); +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1); +- OUT_RING(chan, 0x55); +- +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); +- OUT_RING(chan, nfbdev->patt.handle); +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8); +- OUT_RING(chan, pattern_fmt); +-#ifdef __BIG_ENDIAN +- OUT_RING(chan, 2); +-#else +- OUT_RING(chan, 1); +-#endif +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- OUT_RING(chan, ~0); +- OUT_RING(chan, ~0); +- OUT_RING(chan, ~0); +- OUT_RING(chan, ~0); +- +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1); +- OUT_RING(chan, nfbdev->clip.handle); +- BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2); +- OUT_RING(chan, 0); +- OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); +- +- BEGIN_NV04(chan, NvSubImageBlit, 0x0000, 1); +- OUT_RING(chan, nfbdev->blit.handle); +- BEGIN_NV04(chan, NvSubImageBlit, 0x019c, 1); +- OUT_RING(chan, nfbdev->surf2d.handle); +- BEGIN_NV04(chan, NvSubImageBlit, 0x02fc, 1); +- OUT_RING(chan, 3); +- if (device->info.chipset >= 0x11 /*XXX: oclass == 0x009f*/) { +- BEGIN_NV04(chan, NvSubImageBlit, 0x0120, 3); +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- OUT_RING(chan, 2); +- } +- +- BEGIN_NV04(chan, NvSubGdiRect, 0x0000, 1); +- OUT_RING(chan, nfbdev->gdi.handle); +- BEGIN_NV04(chan, NvSubGdiRect, 0x0198, 1); +- OUT_RING(chan, nfbdev->surf2d.handle); +- BEGIN_NV04(chan, NvSubGdiRect, 0x0188, 2); +- OUT_RING(chan, nfbdev->patt.handle); +- OUT_RING(chan, nfbdev->rop.handle); +- BEGIN_NV04(chan, NvSubGdiRect, 0x0304, 1); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSubGdiRect, 0x0300, 1); +- OUT_RING(chan, rect_fmt); +- BEGIN_NV04(chan, NvSubGdiRect, 0x02fc, 1); +- OUT_RING(chan, 3); +- +- FIRE_RING(chan); +- +- return 0; +-} +- +diff --git a/drivers/gpu/drm/nouveau/nv04_fence.c b/drivers/gpu/drm/nouveau/nv04_fence.c +deleted file mode 100644 +index f9859deb..00000000 +--- a/drivers/gpu/drm/nouveau/nv04_fence.c ++++ /dev/null +@@ -1,111 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fence.h" +- +-struct nv04_fence_chan { +- struct nouveau_fence_chan base; +-}; +- +-struct nv04_fence_priv { +- struct nouveau_fence_priv base; +-}; +- +-static int +-nv04_fence_emit(struct nouveau_fence *fence) +-{ +- struct nouveau_channel *chan = fence->channel; +- int ret = RING_SPACE(chan, 2); +- if (ret == 0) { +- BEGIN_NV04(chan, NvSubSw, 0x0150, 1); +- OUT_RING (chan, fence->base.seqno); +- FIRE_RING (chan); +- } +- return ret; +-} +- +-static int +-nv04_fence_sync(struct nouveau_fence *fence, +- struct nouveau_channel *prev, struct nouveau_channel *chan) +-{ +- return -ENODEV; +-} +- +-static u32 +-nv04_fence_read(struct nouveau_channel *chan) +-{ +- struct nouveau_fifo_chan *fifo = nvkm_fifo_chan(chan);; +- return atomic_read(&fifo->refcnt); +-} +- +-static void +-nv04_fence_context_del(struct nouveau_channel *chan) +-{ +- struct nv04_fence_chan *fctx = chan->fence; +- nouveau_fence_context_del(&fctx->base); +- chan->fence = NULL; +- nouveau_fence_context_free(&fctx->base); +-} +- +-static int +-nv04_fence_context_new(struct nouveau_channel *chan) +-{ +- struct nv04_fence_chan *fctx = kzalloc(sizeof(*fctx), GFP_KERNEL); +- if (fctx) { +- nouveau_fence_context_new(chan, &fctx->base); +- fctx->base.emit = nv04_fence_emit; +- fctx->base.sync = nv04_fence_sync; +- fctx->base.read = nv04_fence_read; +- chan->fence = fctx; +- return 0; +- } +- return -ENOMEM; +-} +- +-static void +-nv04_fence_destroy(struct nouveau_drm *drm) +-{ +- struct nv04_fence_priv *priv = drm->fence; +- drm->fence = NULL; +- kfree(priv); +-} +- +-int +-nv04_fence_create(struct nouveau_drm *drm) +-{ +- struct nv04_fence_priv *priv; +- +- priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->base.dtor = nv04_fence_destroy; +- priv->base.context_new = nv04_fence_context_new; +- priv->base.context_del = nv04_fence_context_del; +- priv->base.contexts = 15; +- priv->base.context_base = fence_context_alloc(priv->base.contexts); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c +deleted file mode 100644 +index 5e1ea1cd..00000000 +--- a/drivers/gpu/drm/nouveau/nv10_fence.c ++++ /dev/null +@@ -1,113 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nv10_fence.h" +- +-int +-nv10_fence_emit(struct nouveau_fence *fence) +-{ +- struct nouveau_channel *chan = fence->channel; +- int ret = RING_SPACE(chan, 2); +- if (ret == 0) { +- BEGIN_NV04(chan, 0, NV10_SUBCHAN_REF_CNT, 1); +- OUT_RING (chan, fence->base.seqno); +- FIRE_RING (chan); +- } +- return ret; +-} +- +- +-static int +-nv10_fence_sync(struct nouveau_fence *fence, +- struct nouveau_channel *prev, struct nouveau_channel *chan) +-{ +- return -ENODEV; +-} +- +-u32 +-nv10_fence_read(struct nouveau_channel *chan) +-{ +- return nvif_rd32(chan, 0x0048); +-} +- +-void +-nv10_fence_context_del(struct nouveau_channel *chan) +-{ +- struct nv10_fence_chan *fctx = chan->fence; +- int i; +- nouveau_fence_context_del(&fctx->base); +- for (i = 0; i < ARRAY_SIZE(fctx->head); i++) +- nvif_object_fini(&fctx->head[i]); +- nvif_object_fini(&fctx->sema); +- chan->fence = NULL; +- nouveau_fence_context_free(&fctx->base); +-} +- +-int +-nv10_fence_context_new(struct nouveau_channel *chan) +-{ +- struct nv10_fence_chan *fctx; +- +- fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); +- if (!fctx) +- return -ENOMEM; +- +- nouveau_fence_context_new(chan, &fctx->base); +- fctx->base.emit = nv10_fence_emit; +- fctx->base.read = nv10_fence_read; +- fctx->base.sync = nv10_fence_sync; +- return 0; +-} +- +-void +-nv10_fence_destroy(struct nouveau_drm *drm) +-{ +- struct nv10_fence_priv *priv = drm->fence; +- nouveau_bo_unmap(priv->bo); +- if (priv->bo) +- nouveau_bo_unpin(priv->bo); +- nouveau_bo_ref(NULL, &priv->bo); +- drm->fence = NULL; +- kfree(priv); +-} +- +-int +-nv10_fence_create(struct nouveau_drm *drm) +-{ +- struct nv10_fence_priv *priv; +- +- priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->base.dtor = nv10_fence_destroy; +- priv->base.context_new = nv10_fence_context_new; +- priv->base.context_del = nv10_fence_context_del; +- priv->base.contexts = 31; +- priv->base.context_base = fence_context_alloc(priv->base.contexts); +- spin_lock_init(&priv->lock); +- return 0; +-} +diff --git a/drivers/gpu/drm/nouveau/nv10_fence.h b/drivers/gpu/drm/nouveau/nv10_fence.h +deleted file mode 100644 +index a87259f3..00000000 +--- a/drivers/gpu/drm/nouveau/nv10_fence.h ++++ /dev/null +@@ -1,20 +0,0 @@ +-#ifndef __NV10_FENCE_H_ +-#define __NV10_FENCE_H_ +- +-#include "nouveau_fence.h" +-#include "nouveau_bo.h" +- +-struct nv10_fence_chan { +- struct nouveau_fence_chan base; +- struct nvif_object sema; +- struct nvif_object head[4]; +-}; +- +-struct nv10_fence_priv { +- struct nouveau_fence_priv base; +- struct nouveau_bo *bo; +- spinlock_t lock; +- u32 sequence; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c +deleted file mode 100644 +index 40b461c7..00000000 +--- a/drivers/gpu/drm/nouveau/nv17_fence.c ++++ /dev/null +@@ -1,151 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nv10_fence.h" +- +-int +-nv17_fence_sync(struct nouveau_fence *fence, +- struct nouveau_channel *prev, struct nouveau_channel *chan) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&prev->device->base); +- struct nv10_fence_priv *priv = chan->drm->fence; +- struct nv10_fence_chan *fctx = chan->fence; +- u32 value; +- int ret; +- +- if (!mutex_trylock(&cli->mutex)) +- return -EBUSY; +- +- spin_lock(&priv->lock); +- value = priv->sequence; +- priv->sequence += 2; +- spin_unlock(&priv->lock); +- +- ret = RING_SPACE(prev, 5); +- if (!ret) { +- BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); +- OUT_RING (prev, fctx->sema.handle); +- OUT_RING (prev, 0); +- OUT_RING (prev, value + 0); +- OUT_RING (prev, value + 1); +- FIRE_RING (prev); +- } +- +- if (!ret && !(ret = RING_SPACE(chan, 5))) { +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); +- OUT_RING (chan, fctx->sema.handle); +- OUT_RING (chan, 0); +- OUT_RING (chan, value + 1); +- OUT_RING (chan, value + 2); +- FIRE_RING (chan); +- } +- +- mutex_unlock(&cli->mutex); +- return 0; +-} +- +-static int +-nv17_fence_context_new(struct nouveau_channel *chan) +-{ +- struct nv10_fence_priv *priv = chan->drm->fence; +- struct nv10_fence_chan *fctx; +- struct ttm_mem_reg *mem = &priv->bo->bo.mem; +- u32 start = mem->start * PAGE_SIZE; +- u32 limit = start + mem->size - 1; +- int ret = 0; +- +- fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); +- if (!fctx) +- return -ENOMEM; +- +- nouveau_fence_context_new(chan, &fctx->base); +- fctx->base.emit = nv10_fence_emit; +- fctx->base.read = nv10_fence_read; +- fctx->base.sync = nv17_fence_sync; +- +- ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_FROM_MEMORY, +- &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_VRAM, +- .access = NV_DMA_V0_ACCESS_RDWR, +- .start = start, +- .limit = limit, +- }, sizeof(struct nv_dma_v0), +- &fctx->sema); +- if (ret) +- nv10_fence_context_del(chan); +- return ret; +-} +- +-void +-nv17_fence_resume(struct nouveau_drm *drm) +-{ +- struct nv10_fence_priv *priv = drm->fence; +- +- nouveau_bo_wr32(priv->bo, 0, priv->sequence); +-} +- +-int +-nv17_fence_create(struct nouveau_drm *drm) +-{ +- struct nv10_fence_priv *priv; +- int ret = 0; +- +- priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->base.dtor = nv10_fence_destroy; +- priv->base.resume = nv17_fence_resume; +- priv->base.context_new = nv17_fence_context_new; +- priv->base.context_del = nv10_fence_context_del; +- priv->base.contexts = 31; +- priv->base.context_base = fence_context_alloc(priv->base.contexts); +- spin_lock_init(&priv->lock); +- +- ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, +- 0, 0x0000, NULL, NULL, &priv->bo); +- if (!ret) { +- ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); +- if (!ret) { +- ret = nouveau_bo_map(priv->bo); +- if (ret) +- nouveau_bo_unpin(priv->bo); +- } +- if (ret) +- nouveau_bo_ref(NULL, &priv->bo); +- } +- +- if (ret) { +- nv10_fence_destroy(drm); +- return ret; +- } +- +- nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c +deleted file mode 100644 +index eb8b3671..00000000 +--- a/drivers/gpu/drm/nouveau/nv50_display.c ++++ /dev/null +@@ -1,2571 +0,0 @@ +-/* +- * Copyright 2011 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +- +-#include +-#include +-#include +- +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_gem.h" +-#include "nouveau_connector.h" +-#include "nouveau_encoder.h" +-#include "nouveau_crtc.h" +-#include "nouveau_fence.h" +-#include "nv50_display.h" +- +-#define EVO_DMA_NR 9 +- +-#define EVO_MASTER (0x00) +-#define EVO_FLIP(c) (0x01 + (c)) +-#define EVO_OVLY(c) (0x05 + (c)) +-#define EVO_OIMM(c) (0x09 + (c)) +-#define EVO_CURS(c) (0x0d + (c)) +- +-/* offsets in shared sync bo of various structures */ +-#define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) +-#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) +-#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) +-#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) +- +-/****************************************************************************** +- * EVO channel +- *****************************************************************************/ +- +-struct nv50_chan { +- struct nvif_object user; +-}; +- +-static int +-nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head, +- void *data, u32 size, struct nv50_chan *chan) +-{ +- while (oclass[0]) { +- int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head, +- oclass[0], data, size, +- &chan->user); +- if (oclass++, ret == 0) { +- nvif_object_map(&chan->user); +- return ret; +- } +- } +- return -ENOSYS; +-} +- +-static void +-nv50_chan_destroy(struct nv50_chan *chan) +-{ +- nvif_object_fini(&chan->user); +-} +- +-/****************************************************************************** +- * PIO EVO channel +- *****************************************************************************/ +- +-struct nv50_pioc { +- struct nv50_chan base; +-}; +- +-static void +-nv50_pioc_destroy(struct nv50_pioc *pioc) +-{ +- nv50_chan_destroy(&pioc->base); +-} +- +-static int +-nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head, +- void *data, u32 size, struct nv50_pioc *pioc) +-{ +- return nv50_chan_create(disp, oclass, head, data, size, &pioc->base); +-} +- +-/****************************************************************************** +- * Cursor Immediate +- *****************************************************************************/ +- +-struct nv50_curs { +- struct nv50_pioc base; +-}; +- +-static int +-nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs) +-{ +- struct nv50_disp_cursor_v0 args = { +- .head = head, +- }; +- static const u32 oclass[] = { +- GK104_DISP_CURSOR, +- GF110_DISP_CURSOR, +- GT214_DISP_CURSOR, +- G82_DISP_CURSOR, +- NV50_DISP_CURSOR, +- 0 +- }; +- +- return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), +- &curs->base); +-} +- +-/****************************************************************************** +- * Overlay Immediate +- *****************************************************************************/ +- +-struct nv50_oimm { +- struct nv50_pioc base; +-}; +- +-static int +-nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm) +-{ +- struct nv50_disp_cursor_v0 args = { +- .head = head, +- }; +- static const u32 oclass[] = { +- GK104_DISP_OVERLAY, +- GF110_DISP_OVERLAY, +- GT214_DISP_OVERLAY, +- G82_DISP_OVERLAY, +- NV50_DISP_OVERLAY, +- 0 +- }; +- +- return nv50_pioc_create(disp, oclass, head, &args, sizeof(args), +- &oimm->base); +-} +- +-/****************************************************************************** +- * DMA EVO channel +- *****************************************************************************/ +- +-struct nv50_dmac { +- struct nv50_chan base; +- dma_addr_t handle; +- u32 *ptr; +- +- struct nvif_object sync; +- struct nvif_object vram; +- +- /* Protects against concurrent pushbuf access to this channel, lock is +- * grabbed by evo_wait (if the pushbuf reservation is successful) and +- * dropped again by evo_kick. */ +- struct mutex lock; +-}; +- +-static void +-nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp) +-{ +- nvif_object_fini(&dmac->vram); +- nvif_object_fini(&dmac->sync); +- +- nv50_chan_destroy(&dmac->base); +- +- if (dmac->ptr) { +- struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev; +- pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); +- } +-} +- +-static int +-nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head, +- void *data, u32 size, u64 syncbuf, +- struct nv50_dmac *dmac) +-{ +- struct nvif_device *device = nvif_device(disp); +- struct nv50_disp_core_channel_dma_v0 *args = data; +- struct nvif_object pushbuf; +- int ret; +- +- mutex_init(&dmac->lock); +- +- dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev, +- PAGE_SIZE, &dmac->handle); +- if (!dmac->ptr) +- return -ENOMEM; +- +- ret = nvif_object_init(nvif_object(device), NULL, +- args->pushbuf, NV_DMA_FROM_MEMORY, +- &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_PCI_US, +- .access = NV_DMA_V0_ACCESS_RD, +- .start = dmac->handle + 0x0000, +- .limit = dmac->handle + 0x0fff, +- }, sizeof(struct nv_dma_v0), &pushbuf); +- if (ret) +- return ret; +- +- ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base); +- nvif_object_fini(&pushbuf); +- if (ret) +- return ret; +- +- ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000, +- NV_DMA_IN_MEMORY, +- &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_VRAM, +- .access = NV_DMA_V0_ACCESS_RDWR, +- .start = syncbuf + 0x0000, +- .limit = syncbuf + 0x0fff, +- }, sizeof(struct nv_dma_v0), +- &dmac->sync); +- if (ret) +- return ret; +- +- ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001, +- NV_DMA_IN_MEMORY, +- &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_VRAM, +- .access = NV_DMA_V0_ACCESS_RDWR, +- .start = 0, +- .limit = device->info.ram_user - 1, +- }, sizeof(struct nv_dma_v0), +- &dmac->vram); +- if (ret) +- return ret; +- +- return ret; +-} +- +-/****************************************************************************** +- * Core +- *****************************************************************************/ +- +-struct nv50_mast { +- struct nv50_dmac base; +-}; +- +-static int +-nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core) +-{ +- struct nv50_disp_core_channel_dma_v0 args = { +- .pushbuf = 0xb0007d00, +- }; +- static const u32 oclass[] = { +- GM107_DISP_CORE_CHANNEL_DMA, +- GK110_DISP_CORE_CHANNEL_DMA, +- GK104_DISP_CORE_CHANNEL_DMA, +- GF110_DISP_CORE_CHANNEL_DMA, +- GT214_DISP_CORE_CHANNEL_DMA, +- GT206_DISP_CORE_CHANNEL_DMA, +- GT200_DISP_CORE_CHANNEL_DMA, +- G82_DISP_CORE_CHANNEL_DMA, +- NV50_DISP_CORE_CHANNEL_DMA, +- 0 +- }; +- +- return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf, +- &core->base); +-} +- +-/****************************************************************************** +- * Base +- *****************************************************************************/ +- +-struct nv50_sync { +- struct nv50_dmac base; +- u32 addr; +- u32 data; +-}; +- +-static int +-nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf, +- struct nv50_sync *base) +-{ +- struct nv50_disp_base_channel_dma_v0 args = { +- .pushbuf = 0xb0007c00 | head, +- .head = head, +- }; +- static const u32 oclass[] = { +- GK110_DISP_BASE_CHANNEL_DMA, +- GK104_DISP_BASE_CHANNEL_DMA, +- GF110_DISP_BASE_CHANNEL_DMA, +- GT214_DISP_BASE_CHANNEL_DMA, +- GT200_DISP_BASE_CHANNEL_DMA, +- G82_DISP_BASE_CHANNEL_DMA, +- NV50_DISP_BASE_CHANNEL_DMA, +- 0 +- }; +- +- return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), +- syncbuf, &base->base); +-} +- +-/****************************************************************************** +- * Overlay +- *****************************************************************************/ +- +-struct nv50_ovly { +- struct nv50_dmac base; +-}; +- +-static int +-nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf, +- struct nv50_ovly *ovly) +-{ +- struct nv50_disp_overlay_channel_dma_v0 args = { +- .pushbuf = 0xb0007e00 | head, +- .head = head, +- }; +- static const u32 oclass[] = { +- GK104_DISP_OVERLAY_CONTROL_DMA, +- GF110_DISP_OVERLAY_CONTROL_DMA, +- GT214_DISP_OVERLAY_CHANNEL_DMA, +- GT200_DISP_OVERLAY_CHANNEL_DMA, +- G82_DISP_OVERLAY_CHANNEL_DMA, +- NV50_DISP_OVERLAY_CHANNEL_DMA, +- 0 +- }; +- +- return nv50_dmac_create(disp, oclass, head, &args, sizeof(args), +- syncbuf, &ovly->base); +-} +- +-struct nv50_head { +- struct nouveau_crtc base; +- struct nouveau_bo *image; +- struct nv50_curs curs; +- struct nv50_sync sync; +- struct nv50_ovly ovly; +- struct nv50_oimm oimm; +-}; +- +-#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) +-#define nv50_curs(c) (&nv50_head(c)->curs) +-#define nv50_sync(c) (&nv50_head(c)->sync) +-#define nv50_ovly(c) (&nv50_head(c)->ovly) +-#define nv50_oimm(c) (&nv50_head(c)->oimm) +-#define nv50_chan(c) (&(c)->base.base) +-#define nv50_vers(c) nv50_chan(c)->user.oclass +- +-struct nv50_fbdma { +- struct list_head head; +- struct nvif_object core; +- struct nvif_object base[4]; +-}; +- +-struct nv50_disp { +- struct nvif_object *disp; +- struct nv50_mast mast; +- +- struct list_head fbdma; +- +- struct nouveau_bo *sync; +-}; +- +-static struct nv50_disp * +-nv50_disp(struct drm_device *dev) +-{ +- return nouveau_display(dev)->priv; +-} +- +-#define nv50_mast(d) (&nv50_disp(d)->mast) +- +-static struct drm_crtc * +-nv50_display_crtc_get(struct drm_encoder *encoder) +-{ +- return nouveau_encoder(encoder)->crtc; +-} +- +-/****************************************************************************** +- * EVO channel helpers +- *****************************************************************************/ +-static u32 * +-evo_wait(void *evoc, int nr) +-{ +- struct nv50_dmac *dmac = evoc; +- u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4; +- +- mutex_lock(&dmac->lock); +- if (put + nr >= (PAGE_SIZE / 4) - 8) { +- dmac->ptr[put] = 0x20000000; +- +- nvif_wr32(&dmac->base.user, 0x0000, 0x00000000); +- if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) { +- mutex_unlock(&dmac->lock); +- nv_error(nvkm_object(&dmac->base.user), "channel stalled\n"); +- return NULL; +- } +- +- put = 0; +- } +- +- return dmac->ptr + put; +-} +- +-static void +-evo_kick(u32 *push, void *evoc) +-{ +- struct nv50_dmac *dmac = evoc; +- nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2); +- mutex_unlock(&dmac->lock); +-} +- +-#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) +-#define evo_data(p,d) *((p)++) = (d) +- +-static bool +-evo_sync_wait(void *data) +-{ +- if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) +- return true; +- usleep_range(1, 2); +- return false; +-} +- +-static int +-evo_sync(struct drm_device *dev) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nv50_disp *disp = nv50_disp(dev); +- struct nv50_mast *mast = nv50_mast(dev); +- u32 *push = evo_wait(mast, 8); +- if (push) { +- nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); +- evo_mthd(push, 0x0084, 1); +- evo_data(push, 0x80000000 | EVO_MAST_NTFY); +- evo_mthd(push, 0x0080, 2); +- evo_data(push, 0x00000000); +- evo_data(push, 0x00000000); +- evo_kick(push, mast); +- if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync)) +- return 0; +- } +- +- return -EBUSY; +-} +- +-/****************************************************************************** +- * Page flipping channel +- *****************************************************************************/ +-struct nouveau_bo * +-nv50_display_crtc_sema(struct drm_device *dev, int crtc) +-{ +- return nv50_disp(dev)->sync; +-} +- +-struct nv50_display_flip { +- struct nv50_disp *disp; +- struct nv50_sync *chan; +-}; +- +-static bool +-nv50_display_flip_wait(void *data) +-{ +- struct nv50_display_flip *flip = data; +- if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == +- flip->chan->data) +- return true; +- usleep_range(1, 2); +- return false; +-} +- +-void +-nv50_display_flip_stop(struct drm_crtc *crtc) +-{ +- struct nvif_device *device = &nouveau_drm(crtc->dev)->device; +- struct nv50_display_flip flip = { +- .disp = nv50_disp(crtc->dev), +- .chan = nv50_sync(crtc), +- }; +- u32 *push; +- +- push = evo_wait(flip.chan, 8); +- if (push) { +- evo_mthd(push, 0x0084, 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x0094, 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x00c0, 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x0080, 1); +- evo_data(push, 0x00000000); +- evo_kick(push, flip.chan); +- } +- +- nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip); +-} +- +-int +-nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, +- struct nouveau_channel *chan, u32 swap_interval) +-{ +- struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv50_head *head = nv50_head(crtc); +- struct nv50_sync *sync = nv50_sync(crtc); +- u32 *push; +- int ret; +- +- swap_interval <<= 4; +- if (swap_interval == 0) +- swap_interval |= 0x100; +- if (chan == NULL) +- evo_sync(crtc->dev); +- +- push = evo_wait(sync, 128); +- if (unlikely(push == NULL)) +- return -EBUSY; +- +- if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) { +- ret = RING_SPACE(chan, 8); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); +- OUT_RING (chan, NvEvoSema0 + nv_crtc->index); +- OUT_RING (chan, sync->addr ^ 0x10); +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); +- OUT_RING (chan, sync->data + 1); +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); +- OUT_RING (chan, sync->addr); +- OUT_RING (chan, sync->data); +- } else +- if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) { +- u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; +- ret = RING_SPACE(chan, 12); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); +- OUT_RING (chan, chan->vram.handle); +- BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); +- OUT_RING (chan, upper_32_bits(addr ^ 0x10)); +- OUT_RING (chan, lower_32_bits(addr ^ 0x10)); +- OUT_RING (chan, sync->data + 1); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); +- BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); +- OUT_RING (chan, upper_32_bits(addr)); +- OUT_RING (chan, lower_32_bits(addr)); +- OUT_RING (chan, sync->data); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); +- } else +- if (chan) { +- u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; +- ret = RING_SPACE(chan, 10); +- if (ret) +- return ret; +- +- BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); +- OUT_RING (chan, upper_32_bits(addr ^ 0x10)); +- OUT_RING (chan, lower_32_bits(addr ^ 0x10)); +- OUT_RING (chan, sync->data + 1); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | +- NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); +- BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); +- OUT_RING (chan, upper_32_bits(addr)); +- OUT_RING (chan, lower_32_bits(addr)); +- OUT_RING (chan, sync->data); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | +- NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); +- } +- +- if (chan) { +- sync->addr ^= 0x10; +- sync->data++; +- FIRE_RING (chan); +- } +- +- /* queue the flip */ +- evo_mthd(push, 0x0100, 1); +- evo_data(push, 0xfffe0000); +- evo_mthd(push, 0x0084, 1); +- evo_data(push, swap_interval); +- if (!(swap_interval & 0x00000100)) { +- evo_mthd(push, 0x00e0, 1); +- evo_data(push, 0x40000000); +- } +- evo_mthd(push, 0x0088, 4); +- evo_data(push, sync->addr); +- evo_data(push, sync->data++); +- evo_data(push, sync->data); +- evo_data(push, sync->base.sync.handle); +- evo_mthd(push, 0x00a0, 2); +- evo_data(push, 0x00000000); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x00c0, 1); +- evo_data(push, nv_fb->r_handle); +- evo_mthd(push, 0x0110, 2); +- evo_data(push, 0x00000000); +- evo_data(push, 0x00000000); +- if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) { +- evo_mthd(push, 0x0800, 5); +- evo_data(push, nv_fb->nvbo->bo.offset >> 8); +- evo_data(push, 0); +- evo_data(push, (fb->height << 16) | fb->width); +- evo_data(push, nv_fb->r_pitch); +- evo_data(push, nv_fb->r_format); +- } else { +- evo_mthd(push, 0x0400, 5); +- evo_data(push, nv_fb->nvbo->bo.offset >> 8); +- evo_data(push, 0); +- evo_data(push, (fb->height << 16) | fb->width); +- evo_data(push, nv_fb->r_pitch); +- evo_data(push, nv_fb->r_format); +- } +- evo_mthd(push, 0x0080, 1); +- evo_data(push, 0x00000000); +- evo_kick(push, sync); +- +- nouveau_bo_ref(nv_fb->nvbo, &head->image); +- return 0; +-} +- +-/****************************************************************************** +- * CRTC +- *****************************************************************************/ +-static int +-nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- struct nouveau_connector *nv_connector; +- struct drm_connector *connector; +- u32 *push, mode = 0x00; +- +- nv_connector = nouveau_crtc_connector_get(nv_crtc); +- connector = &nv_connector->base; +- if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { +- if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3) +- mode = DITHERING_MODE_DYNAMIC2X2; +- } else { +- mode = nv_connector->dithering_mode; +- } +- +- if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { +- if (connector->display_info.bpc >= 8) +- mode |= DITHERING_DEPTH_8BPC; +- } else { +- mode |= nv_connector->dithering_depth; +- } +- +- push = evo_wait(mast, 4); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); +- evo_data(push, mode); +- } else +- if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); +- evo_data(push, mode); +- } else { +- evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); +- evo_data(push, mode); +- } +- +- if (update) { +- evo_mthd(push, 0x0080, 1); +- evo_data(push, 0x00000000); +- } +- evo_kick(push, mast); +- } +- +- return 0; +-} +- +-static int +-nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; +- struct drm_crtc *crtc = &nv_crtc->base; +- struct nouveau_connector *nv_connector; +- int mode = DRM_MODE_SCALE_NONE; +- u32 oX, oY, *push; +- +- /* start off at the resolution we programmed the crtc for, this +- * effectively handles NONE/FULL scaling +- */ +- nv_connector = nouveau_crtc_connector_get(nv_crtc); +- if (nv_connector && nv_connector->native_mode) +- mode = nv_connector->scaling_mode; +- +- if (mode != DRM_MODE_SCALE_NONE) +- omode = nv_connector->native_mode; +- else +- omode = umode; +- +- oX = omode->hdisplay; +- oY = omode->vdisplay; +- if (omode->flags & DRM_MODE_FLAG_DBLSCAN) +- oY *= 2; +- +- /* add overscan compensation if necessary, will keep the aspect +- * ratio the same as the backend mode unless overridden by the +- * user setting both hborder and vborder properties. +- */ +- if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || +- (nv_connector->underscan == UNDERSCAN_AUTO && +- nv_connector->edid && +- drm_detect_hdmi_monitor(nv_connector->edid)))) { +- u32 bX = nv_connector->underscan_hborder; +- u32 bY = nv_connector->underscan_vborder; +- u32 aspect = (oY << 19) / oX; +- +- if (bX) { +- oX -= (bX * 2); +- if (bY) oY -= (bY * 2); +- else oY = ((oX * aspect) + (aspect / 2)) >> 19; +- } else { +- oX -= (oX >> 4) + 32; +- if (bY) oY -= (bY * 2); +- else oY = ((oX * aspect) + (aspect / 2)) >> 19; +- } +- } +- +- /* handle CENTER/ASPECT scaling, taking into account the areas +- * removed already for overscan compensation +- */ +- switch (mode) { +- case DRM_MODE_SCALE_CENTER: +- oX = min((u32)umode->hdisplay, oX); +- oY = min((u32)umode->vdisplay, oY); +- /* fall-through */ +- case DRM_MODE_SCALE_ASPECT: +- if (oY < oX) { +- u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; +- oX = ((oY * aspect) + (aspect / 2)) >> 19; +- } else { +- u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; +- oY = ((oX * aspect) + (aspect / 2)) >> 19; +- } +- break; +- default: +- break; +- } +- +- push = evo_wait(mast, 8); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- /*XXX: SCALE_CTRL_ACTIVE??? */ +- evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); +- evo_data(push, (oY << 16) | oX); +- evo_data(push, (oY << 16) | oX); +- evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); +- evo_data(push, umode->vdisplay << 16 | umode->hdisplay); +- } else { +- evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); +- evo_data(push, (oY << 16) | oX); +- evo_data(push, (oY << 16) | oX); +- evo_data(push, (oY << 16) | oX); +- evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); +- evo_data(push, umode->vdisplay << 16 | umode->hdisplay); +- } +- +- evo_kick(push, mast); +- +- if (update) { +- nv50_display_flip_stop(crtc); +- nv50_display_flip_next(crtc, crtc->primary->fb, +- NULL, 1); +- } +- } +- +- return 0; +-} +- +-static int +-nv50_crtc_set_raster_vblank_dmi(struct nouveau_crtc *nv_crtc, u32 usec) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- u32 *push; +- +- push = evo_wait(mast, 8); +- if (!push) +- return -ENOMEM; +- +- evo_mthd(push, 0x0828 + (nv_crtc->index * 0x400), 1); +- evo_data(push, usec); +- evo_kick(push, mast); +- return 0; +-} +- +-static int +-nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- u32 *push, hue, vib; +- int adj; +- +- adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; +- vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; +- hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; +- +- push = evo_wait(mast, 16); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); +- evo_data(push, (hue << 20) | (vib << 8)); +- } else { +- evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); +- evo_data(push, (hue << 20) | (vib << 8)); +- } +- +- if (update) { +- evo_mthd(push, 0x0080, 1); +- evo_data(push, 0x00000000); +- } +- evo_kick(push, mast); +- } +- +- return 0; +-} +- +-static int +-nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, +- int x, int y, bool update) +-{ +- struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- u32 *push; +- +- push = evo_wait(mast, 16); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); +- evo_data(push, nvfb->nvbo->bo.offset >> 8); +- evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); +- evo_data(push, (fb->height << 16) | fb->width); +- evo_data(push, nvfb->r_pitch); +- evo_data(push, nvfb->r_format); +- evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); +- evo_data(push, (y << 16) | x); +- if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); +- evo_data(push, nvfb->r_handle); +- } +- } else { +- evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); +- evo_data(push, nvfb->nvbo->bo.offset >> 8); +- evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); +- evo_data(push, (fb->height << 16) | fb->width); +- evo_data(push, nvfb->r_pitch); +- evo_data(push, nvfb->r_format); +- evo_data(push, nvfb->r_handle); +- evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); +- evo_data(push, (y << 16) | x); +- } +- +- if (update) { +- evo_mthd(push, 0x0080, 1); +- evo_data(push, 0x00000000); +- } +- evo_kick(push, mast); +- } +- +- nv_crtc->fb.handle = nvfb->r_handle; +- return 0; +-} +- +-static void +-nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- u32 *push = evo_wait(mast, 16); +- if (push) { +- if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); +- evo_data(push, 0x85000000); +- evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); +- } else +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); +- evo_data(push, 0x85000000); +- evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); +- evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); +- evo_data(push, mast->base.vram.handle); +- } else { +- evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); +- evo_data(push, 0x85000000); +- evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); +- evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); +- evo_data(push, mast->base.vram.handle); +- } +- evo_kick(push, mast); +- } +-} +- +-static void +-nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- u32 *push = evo_wait(mast, 16); +- if (push) { +- if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x05000000); +- } else +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x05000000); +- evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x00000000); +- } else { +- evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x05000000); +- evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x00000000); +- } +- evo_kick(push, mast); +- } +-} +- +-static void +-nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) +-{ +- struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); +- +- if (show) +- nv50_crtc_cursor_show(nv_crtc); +- else +- nv50_crtc_cursor_hide(nv_crtc); +- +- if (update) { +- u32 *push = evo_wait(mast, 2); +- if (push) { +- evo_mthd(push, 0x0080, 1); +- evo_data(push, 0x00000000); +- evo_kick(push, mast); +- } +- } +-} +- +-static void +-nv50_crtc_dpms(struct drm_crtc *crtc, int mode) +-{ +-} +- +-static void +-nv50_crtc_prepare(struct drm_crtc *crtc) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv50_mast *mast = nv50_mast(crtc->dev); +- u32 *push; +- +- nv50_display_flip_stop(crtc); +- +- push = evo_wait(mast, 6); +- if (push) { +- if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x40000000); +- } else +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x40000000); +- evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x00000000); +- } else { +- evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x03000000); +- evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x00000000); +- } +- +- evo_kick(push, mast); +- } +- +- nv50_crtc_cursor_show_hide(nv_crtc, false, false); +-} +- +-static void +-nv50_crtc_commit(struct drm_crtc *crtc) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv50_mast *mast = nv50_mast(crtc->dev); +- u32 *push; +- +- push = evo_wait(mast, 32); +- if (push) { +- if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); +- evo_data(push, nv_crtc->fb.handle); +- evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); +- evo_data(push, 0xc0000000); +- evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); +- } else +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); +- evo_data(push, nv_crtc->fb.handle); +- evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); +- evo_data(push, 0xc0000000); +- evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); +- evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); +- evo_data(push, mast->base.vram.handle); +- } else { +- evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); +- evo_data(push, nv_crtc->fb.handle); +- evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); +- evo_data(push, 0x83000000); +- evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); +- evo_data(push, 0x00000000); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); +- evo_data(push, mast->base.vram.handle); +- evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0xffffff00); +- } +- +- evo_kick(push, mast); +- } +- +- nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); +- nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); +-} +- +-static bool +-nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); +- return true; +-} +- +-static int +-nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) +-{ +- struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); +- struct nv50_head *head = nv50_head(crtc); +- int ret; +- +- ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); +- if (ret == 0) { +- if (head->image) +- nouveau_bo_unpin(head->image); +- nouveau_bo_ref(nvfb->nvbo, &head->image); +- } +- +- return ret; +-} +- +-static int +-nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, +- struct drm_display_mode *mode, int x, int y, +- struct drm_framebuffer *old_fb) +-{ +- struct nv50_mast *mast = nv50_mast(crtc->dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nouveau_connector *nv_connector; +- u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; +- u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; +- u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; +- u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; +- u32 vblan2e = 0, vblan2s = 1, vblankus = 0; +- u32 *push; +- int ret; +- +- hactive = mode->htotal; +- hsynce = mode->hsync_end - mode->hsync_start - 1; +- hbackp = mode->htotal - mode->hsync_end; +- hblanke = hsynce + hbackp; +- hfrontp = mode->hsync_start - mode->hdisplay; +- hblanks = mode->htotal - hfrontp - 1; +- +- vactive = mode->vtotal * vscan / ilace; +- vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; +- vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; +- vblanke = vsynce + vbackp; +- vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; +- vblanks = vactive - vfrontp - 1; +- /* XXX: Safe underestimate, even "0" works */ +- vblankus = (vactive - mode->vdisplay - 2) * hactive; +- vblankus *= 1000; +- vblankus /= mode->clock; +- +- if (mode->flags & DRM_MODE_FLAG_INTERLACE) { +- vblan2e = vactive + vsynce + vbackp; +- vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); +- vactive = (vactive * 2) + 1; +- } +- +- ret = nv50_crtc_swap_fbs(crtc, old_fb); +- if (ret) +- return ret; +- +- push = evo_wait(mast, 64); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); +- evo_data(push, 0x00800000 | mode->clock); +- evo_data(push, (ilace == 2) ? 2 : 0); +- evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); +- evo_data(push, 0x00000000); +- evo_data(push, (vactive << 16) | hactive); +- evo_data(push, ( vsynce << 16) | hsynce); +- evo_data(push, (vblanke << 16) | hblanke); +- evo_data(push, (vblanks << 16) | hblanks); +- evo_data(push, (vblan2e << 16) | vblan2s); +- evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); +- evo_data(push, 0x00000000); +- evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); +- evo_data(push, 0x00000311); +- evo_data(push, 0x00000100); +- } else { +- evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); +- evo_data(push, 0x00000000); +- evo_data(push, (vactive << 16) | hactive); +- evo_data(push, ( vsynce << 16) | hsynce); +- evo_data(push, (vblanke << 16) | hblanke); +- evo_data(push, (vblanks << 16) | hblanks); +- evo_data(push, (vblan2e << 16) | vblan2s); +- evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); +- evo_data(push, 0x00000000); /* ??? */ +- evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); +- evo_data(push, mode->clock * 1000); +- evo_data(push, 0x00200000); /* ??? */ +- evo_data(push, mode->clock * 1000); +- evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); +- evo_data(push, 0x00000311); +- evo_data(push, 0x00000100); +- } +- +- evo_kick(push, mast); +- } +- +- nv_connector = nouveau_crtc_connector_get(nv_crtc); +- nv50_crtc_set_dither(nv_crtc, false); +- nv50_crtc_set_scale(nv_crtc, false); +- +- /* G94 only accepts this after setting scale */ +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) +- nv50_crtc_set_raster_vblank_dmi(nv_crtc, vblankus); +- +- nv50_crtc_set_color_vibrance(nv_crtc, false); +- nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false); +- return 0; +-} +- +-static int +-nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, +- struct drm_framebuffer *old_fb) +-{ +- struct nouveau_drm *drm = nouveau_drm(crtc->dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- int ret; +- +- if (!crtc->primary->fb) { +- NV_DEBUG(drm, "No FB bound\n"); +- return 0; +- } +- +- ret = nv50_crtc_swap_fbs(crtc, old_fb); +- if (ret) +- return ret; +- +- nv50_display_flip_stop(crtc); +- nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true); +- nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1); +- return 0; +-} +- +-static int +-nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, +- struct drm_framebuffer *fb, int x, int y, +- enum mode_set_atomic state) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- nv50_display_flip_stop(crtc); +- nv50_crtc_set_image(nv_crtc, fb, x, y, true); +- return 0; +-} +- +-static void +-nv50_crtc_lut_load(struct drm_crtc *crtc) +-{ +- struct nv50_disp *disp = nv50_disp(crtc->dev); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); +- int i; +- +- for (i = 0; i < 256; i++) { +- u16 r = nv_crtc->lut.r[i] >> 2; +- u16 g = nv_crtc->lut.g[i] >> 2; +- u16 b = nv_crtc->lut.b[i] >> 2; +- +- if (disp->disp->oclass < GF110_DISP) { +- writew(r + 0x0000, lut + (i * 0x08) + 0); +- writew(g + 0x0000, lut + (i * 0x08) + 2); +- writew(b + 0x0000, lut + (i * 0x08) + 4); +- } else { +- writew(r + 0x6000, lut + (i * 0x20) + 0); +- writew(g + 0x6000, lut + (i * 0x20) + 2); +- writew(b + 0x6000, lut + (i * 0x20) + 4); +- } +- } +-} +- +-static void +-nv50_crtc_disable(struct drm_crtc *crtc) +-{ +- struct nv50_head *head = nv50_head(crtc); +- evo_sync(crtc->dev); +- if (head->image) +- nouveau_bo_unpin(head->image); +- nouveau_bo_ref(NULL, &head->image); +-} +- +-static int +-nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, +- uint32_t handle, uint32_t width, uint32_t height) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct drm_device *dev = crtc->dev; +- struct drm_gem_object *gem; +- struct nouveau_bo *nvbo; +- bool visible = (handle != 0); +- int i, ret = 0; +- +- if (visible) { +- if (width != 64 || height != 64) +- return -EINVAL; +- +- gem = drm_gem_object_lookup(dev, file_priv, handle); +- if (unlikely(!gem)) +- return -ENOENT; +- nvbo = nouveau_gem_object(gem); +- +- ret = nouveau_bo_map(nvbo); +- if (ret == 0) { +- for (i = 0; i < 64 * 64; i++) { +- u32 v = nouveau_bo_rd32(nvbo, i); +- nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); +- } +- nouveau_bo_unmap(nvbo); +- } +- +- drm_gem_object_unreference_unlocked(gem); +- } +- +- if (visible != nv_crtc->cursor.visible) { +- nv50_crtc_cursor_show_hide(nv_crtc, visible, true); +- nv_crtc->cursor.visible = visible; +- } +- +- return ret; +-} +- +-static int +-nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) +-{ +- struct nv50_curs *curs = nv50_curs(crtc); +- struct nv50_chan *chan = nv50_chan(curs); +- nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff)); +- nvif_wr32(&chan->user, 0x0080, 0x00000000); +- return 0; +-} +- +-static void +-nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +- uint32_t start, uint32_t size) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- u32 end = min_t(u32, start + size, 256); +- u32 i; +- +- for (i = start; i < end; i++) { +- nv_crtc->lut.r[i] = r[i]; +- nv_crtc->lut.g[i] = g[i]; +- nv_crtc->lut.b[i] = b[i]; +- } +- +- nv50_crtc_lut_load(crtc); +-} +- +-static void +-nv50_crtc_destroy(struct drm_crtc *crtc) +-{ +- struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); +- struct nv50_disp *disp = nv50_disp(crtc->dev); +- struct nv50_head *head = nv50_head(crtc); +- struct nv50_fbdma *fbdma; +- +- list_for_each_entry(fbdma, &disp->fbdma, head) { +- nvif_object_fini(&fbdma->base[nv_crtc->index]); +- } +- +- nv50_dmac_destroy(&head->ovly.base, disp->disp); +- nv50_pioc_destroy(&head->oimm.base); +- nv50_dmac_destroy(&head->sync.base, disp->disp); +- nv50_pioc_destroy(&head->curs.base); +- +- /*XXX: this shouldn't be necessary, but the core doesn't call +- * disconnect() during the cleanup paths +- */ +- if (head->image) +- nouveau_bo_unpin(head->image); +- nouveau_bo_ref(NULL, &head->image); +- +- nouveau_bo_unmap(nv_crtc->cursor.nvbo); +- if (nv_crtc->cursor.nvbo) +- nouveau_bo_unpin(nv_crtc->cursor.nvbo); +- nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); +- +- nouveau_bo_unmap(nv_crtc->lut.nvbo); +- if (nv_crtc->lut.nvbo) +- nouveau_bo_unpin(nv_crtc->lut.nvbo); +- nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); +- +- drm_crtc_cleanup(crtc); +- kfree(crtc); +-} +- +-static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { +- .dpms = nv50_crtc_dpms, +- .prepare = nv50_crtc_prepare, +- .commit = nv50_crtc_commit, +- .mode_fixup = nv50_crtc_mode_fixup, +- .mode_set = nv50_crtc_mode_set, +- .mode_set_base = nv50_crtc_mode_set_base, +- .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, +- .load_lut = nv50_crtc_lut_load, +- .disable = nv50_crtc_disable, +-}; +- +-static const struct drm_crtc_funcs nv50_crtc_func = { +- .cursor_set = nv50_crtc_cursor_set, +- .cursor_move = nv50_crtc_cursor_move, +- .gamma_set = nv50_crtc_gamma_set, +- .set_config = nouveau_crtc_set_config, +- .destroy = nv50_crtc_destroy, +- .page_flip = nouveau_crtc_page_flip, +-}; +- +-static void +-nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) +-{ +-} +- +-static void +-nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) +-{ +-} +- +-static int +-nv50_crtc_create(struct drm_device *dev, int index) +-{ +- struct nv50_disp *disp = nv50_disp(dev); +- struct nv50_head *head; +- struct drm_crtc *crtc; +- int ret, i; +- +- head = kzalloc(sizeof(*head), GFP_KERNEL); +- if (!head) +- return -ENOMEM; +- +- head->base.index = index; +- head->base.set_dither = nv50_crtc_set_dither; +- head->base.set_scale = nv50_crtc_set_scale; +- head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; +- head->base.color_vibrance = 50; +- head->base.vibrant_hue = 0; +- head->base.cursor.set_offset = nv50_cursor_set_offset; +- head->base.cursor.set_pos = nv50_cursor_set_pos; +- for (i = 0; i < 256; i++) { +- head->base.lut.r[i] = i << 8; +- head->base.lut.g[i] = i << 8; +- head->base.lut.b[i] = i << 8; +- } +- +- crtc = &head->base.base; +- drm_crtc_init(dev, crtc, &nv50_crtc_func); +- drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); +- drm_mode_crtc_set_gamma_size(crtc, 256); +- +- ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, +- 0, 0x0000, NULL, NULL, &head->base.lut.nvbo); +- if (!ret) { +- ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM); +- if (!ret) { +- ret = nouveau_bo_map(head->base.lut.nvbo); +- if (ret) +- nouveau_bo_unpin(head->base.lut.nvbo); +- } +- if (ret) +- nouveau_bo_ref(NULL, &head->base.lut.nvbo); +- } +- +- if (ret) +- goto out; +- +- nv50_crtc_lut_load(crtc); +- +- /* allocate cursor resources */ +- ret = nv50_curs_create(disp->disp, index, &head->curs); +- if (ret) +- goto out; +- +- ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, +- 0, 0x0000, NULL, NULL, &head->base.cursor.nvbo); +- if (!ret) { +- ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM); +- if (!ret) { +- ret = nouveau_bo_map(head->base.cursor.nvbo); +- if (ret) +- nouveau_bo_unpin(head->base.lut.nvbo); +- } +- if (ret) +- nouveau_bo_ref(NULL, &head->base.cursor.nvbo); +- } +- +- if (ret) +- goto out; +- +- /* allocate page flip / sync resources */ +- ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset, +- &head->sync); +- if (ret) +- goto out; +- +- head->sync.addr = EVO_FLIP_SEM0(index); +- head->sync.data = 0x00000000; +- +- /* allocate overlay resources */ +- ret = nv50_oimm_create(disp->disp, index, &head->oimm); +- if (ret) +- goto out; +- +- ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset, +- &head->ovly); +- if (ret) +- goto out; +- +-out: +- if (ret) +- nv50_crtc_destroy(crtc); +- return ret; +-} +- +-/****************************************************************************** +- * DAC +- *****************************************************************************/ +-static void +-nv50_dac_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_dac_pwr_v0 pwr; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_DAC_PWR, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = nv_encoder->dcb->hashm, +- .pwr.state = 1, +- .pwr.data = 1, +- .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND && +- mode != DRM_MODE_DPMS_OFF), +- .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY && +- mode != DRM_MODE_DPMS_OFF), +- }; +- +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +-} +- +-static bool +-nv50_dac_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_connector *nv_connector; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- if (nv_connector && nv_connector->native_mode) { +- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { +- int id = adjusted_mode->base.id; +- *adjusted_mode = *nv_connector->native_mode; +- adjusted_mode->base.id = id; +- } +- } +- +- return true; +-} +- +-static void +-nv50_dac_commit(struct drm_encoder *encoder) +-{ +-} +- +-static void +-nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nv50_mast *mast = nv50_mast(encoder->dev); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- u32 *push; +- +- nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); +- +- push = evo_wait(mast, 8); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- u32 syncs = 0x00000000; +- +- if (mode->flags & DRM_MODE_FLAG_NHSYNC) +- syncs |= 0x00000001; +- if (mode->flags & DRM_MODE_FLAG_NVSYNC) +- syncs |= 0x00000002; +- +- evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); +- evo_data(push, 1 << nv_crtc->index); +- evo_data(push, syncs); +- } else { +- u32 magic = 0x31ec6000 | (nv_crtc->index << 25); +- u32 syncs = 0x00000001; +- +- if (mode->flags & DRM_MODE_FLAG_NHSYNC) +- syncs |= 0x00000008; +- if (mode->flags & DRM_MODE_FLAG_NVSYNC) +- syncs |= 0x00000010; +- +- if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- magic |= 0x00000001; +- +- evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); +- evo_data(push, syncs); +- evo_data(push, magic); +- evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); +- evo_data(push, 1 << nv_crtc->index); +- } +- +- evo_kick(push, mast); +- } +- +- nv_encoder->crtc = encoder->crtc; +-} +- +-static void +-nv50_dac_disconnect(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_mast *mast = nv50_mast(encoder->dev); +- const int or = nv_encoder->or; +- u32 *push; +- +- if (nv_encoder->crtc) { +- nv50_crtc_prepare(nv_encoder->crtc); +- +- push = evo_wait(mast, 4); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0400 + (or * 0x080), 1); +- evo_data(push, 0x00000000); +- } else { +- evo_mthd(push, 0x0180 + (or * 0x020), 1); +- evo_data(push, 0x00000000); +- } +- evo_kick(push, mast); +- } +- } +- +- nv_encoder->crtc = NULL; +-} +- +-static enum drm_connector_status +-nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_dac_load_v0 load; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_DAC_LOAD, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = nv_encoder->dcb->hashm, +- }; +- int ret; +- +- args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval; +- if (args.load.data == 0) +- args.load.data = 340; +- +- ret = nvif_mthd(disp->disp, 0, &args, sizeof(args)); +- if (ret || !args.load.load) +- return connector_status_disconnected; +- +- return connector_status_connected; +-} +- +-static void +-nv50_dac_destroy(struct drm_encoder *encoder) +-{ +- drm_encoder_cleanup(encoder); +- kfree(encoder); +-} +- +-static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { +- .dpms = nv50_dac_dpms, +- .mode_fixup = nv50_dac_mode_fixup, +- .prepare = nv50_dac_disconnect, +- .commit = nv50_dac_commit, +- .mode_set = nv50_dac_mode_set, +- .disable = nv50_dac_disconnect, +- .get_crtc = nv50_display_crtc_get, +- .detect = nv50_dac_detect +-}; +- +-static const struct drm_encoder_funcs nv50_dac_func = { +- .destroy = nv50_dac_destroy, +-}; +- +-static int +-nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- struct nouveau_encoder *nv_encoder; +- struct drm_encoder *encoder; +- int type = DRM_MODE_ENCODER_DAC; +- +- nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); +- if (!nv_encoder) +- return -ENOMEM; +- nv_encoder->dcb = dcbe; +- nv_encoder->or = ffs(dcbe->or) - 1; +- nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); +- +- encoder = to_drm_encoder(nv_encoder); +- encoder->possible_crtcs = dcbe->heads; +- encoder->possible_clones = 0; +- drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); +- drm_encoder_helper_add(encoder, &nv50_dac_hfunc); +- +- drm_mode_connector_attach_encoder(connector, encoder); +- return 0; +-} +- +-/****************************************************************************** +- * Audio +- *****************************************************************************/ +-static void +-nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nouveau_connector *nv_connector; +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct __packed { +- struct { +- struct nv50_disp_mthd_v1 mthd; +- struct nv50_disp_sor_hda_eld_v0 eld; +- } base; +- u8 data[sizeof(nv_connector->base.eld)]; +- } args = { +- .base.mthd.version = 1, +- .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, +- .base.mthd.hasht = nv_encoder->dcb->hasht, +- .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) | +- (0x0100 << nv_crtc->index), +- }; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- if (!drm_detect_monitor_audio(nv_connector->edid)) +- return; +- +- drm_edid_to_eld(&nv_connector->base, nv_connector->edid); +- memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); +- +- nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4); +-} +- +-static void +-nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_sor_hda_eld_v0 eld; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | +- (0x0100 << nv_crtc->index), +- }; +- +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +-} +- +-/****************************************************************************** +- * HDMI +- *****************************************************************************/ +-static void +-nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_sor_hdmi_pwr_v0 pwr; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | +- (0x0100 << nv_crtc->index), +- .pwr.state = 1, +- .pwr.rekey = 56, /* binary driver, and tegra, constant */ +- }; +- struct nouveau_connector *nv_connector; +- u32 max_ac_packet; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- if (!drm_detect_hdmi_monitor(nv_connector->edid)) +- return; +- +- max_ac_packet = mode->htotal - mode->hdisplay; +- max_ac_packet -= args.pwr.rekey; +- max_ac_packet -= 18; /* constant from tegra */ +- args.pwr.max_ac_packet = max_ac_packet / 32; +- +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +- nv50_audio_mode_set(encoder, mode); +-} +- +-static void +-nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_sor_hdmi_pwr_v0 pwr; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) | +- (0x0100 << nv_crtc->index), +- }; +- +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +-} +- +-/****************************************************************************** +- * SOR +- *****************************************************************************/ +-static void +-nv50_sor_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_sor_pwr_v0 pwr; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_SOR_PWR, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = nv_encoder->dcb->hashm, +- .pwr.state = mode == DRM_MODE_DPMS_ON, +- }; +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_sor_dp_pwr_v0 pwr; +- } link = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = nv_encoder->dcb->hashm, +- .pwr.state = mode == DRM_MODE_DPMS_ON, +- }; +- struct drm_device *dev = encoder->dev; +- struct drm_encoder *partner; +- +- nv_encoder->last_dpms = mode; +- +- list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { +- struct nouveau_encoder *nv_partner = nouveau_encoder(partner); +- +- if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) +- continue; +- +- if (nv_partner != nv_encoder && +- nv_partner->dcb->or == nv_encoder->dcb->or) { +- if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) +- return; +- break; +- } +- } +- +- if (nv_encoder->dcb->type == DCB_OUTPUT_DP) { +- args.pwr.state = 1; +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +- nvif_mthd(disp->disp, 0, &link, sizeof(link)); +- } else { +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +- } +-} +- +-static bool +-nv50_sor_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_connector *nv_connector; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- if (nv_connector && nv_connector->native_mode) { +- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { +- int id = adjusted_mode->base.id; +- *adjusted_mode = *nv_connector->native_mode; +- adjusted_mode->base.id = id; +- } +- } +- +- return true; +-} +- +-static void +-nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data) +-{ +- struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev); +- u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push; +- if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1); +- evo_data(push, (nv_encoder->ctrl = temp)); +- } else { +- evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1); +- evo_data(push, (nv_encoder->ctrl = temp)); +- } +- evo_kick(push, mast); +- } +-} +- +-static void +-nv50_sor_disconnect(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); +- +- nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; +- nv_encoder->crtc = NULL; +- +- if (nv_crtc) { +- nv50_crtc_prepare(&nv_crtc->base); +- nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0); +- nv50_audio_disconnect(encoder, nv_crtc); +- nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc); +- } +-} +- +-static void +-nv50_sor_commit(struct drm_encoder *encoder) +-{ +-} +- +-static void +-nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, +- struct drm_display_mode *mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_sor_lvds_script_v0 lvds; +- } lvds = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = nv_encoder->dcb->hashm, +- }; +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct nv50_mast *mast = nv50_mast(encoder->dev); +- struct drm_device *dev = encoder->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_connector *nv_connector; +- struct nvbios *bios = &drm->vbios; +- u32 mask, ctrl; +- u8 owner = 1 << nv_crtc->index; +- u8 proto = 0xf; +- u8 depth = 0x0; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- nv_encoder->crtc = encoder->crtc; +- +- switch (nv_encoder->dcb->type) { +- case DCB_OUTPUT_TMDS: +- if (nv_encoder->dcb->sorconf.link & 1) { +- if (mode->clock < 165000) +- proto = 0x1; +- else +- proto = 0x5; +- } else { +- proto = 0x2; +- } +- +- nv50_hdmi_mode_set(&nv_encoder->base.base, mode); +- break; +- case DCB_OUTPUT_LVDS: +- proto = 0x0; +- +- if (bios->fp_no_ddc) { +- if (bios->fp.dual_link) +- lvds.lvds.script |= 0x0100; +- if (bios->fp.if_is_24bit) +- lvds.lvds.script |= 0x0200; +- } else { +- if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { +- if (((u8 *)nv_connector->edid)[121] == 2) +- lvds.lvds.script |= 0x0100; +- } else +- if (mode->clock >= bios->fp.duallink_transition_clk) { +- lvds.lvds.script |= 0x0100; +- } +- +- if (lvds.lvds.script & 0x0100) { +- if (bios->fp.strapless_is_24bit & 2) +- lvds.lvds.script |= 0x0200; +- } else { +- if (bios->fp.strapless_is_24bit & 1) +- lvds.lvds.script |= 0x0200; +- } +- +- if (nv_connector->base.display_info.bpc == 8) +- lvds.lvds.script |= 0x0200; +- } +- +- nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); +- break; +- case DCB_OUTPUT_DP: +- if (nv_connector->base.display_info.bpc == 6) { +- nv_encoder->dp.datarate = mode->clock * 18 / 8; +- depth = 0x2; +- } else +- if (nv_connector->base.display_info.bpc == 8) { +- nv_encoder->dp.datarate = mode->clock * 24 / 8; +- depth = 0x5; +- } else { +- nv_encoder->dp.datarate = mode->clock * 30 / 8; +- depth = 0x6; +- } +- +- if (nv_encoder->dcb->sorconf.link & 1) +- proto = 0x8; +- else +- proto = 0x9; +- nv50_audio_mode_set(encoder, mode); +- break; +- default: +- BUG_ON(1); +- break; +- } +- +- nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON); +- +- if (nv50_vers(mast) >= GF110_DISP) { +- u32 *push = evo_wait(mast, 3); +- if (push) { +- u32 magic = 0x31ec6000 | (nv_crtc->index << 25); +- u32 syncs = 0x00000001; +- +- if (mode->flags & DRM_MODE_FLAG_NHSYNC) +- syncs |= 0x00000008; +- if (mode->flags & DRM_MODE_FLAG_NVSYNC) +- syncs |= 0x00000010; +- +- if (mode->flags & DRM_MODE_FLAG_INTERLACE) +- magic |= 0x00000001; +- +- evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); +- evo_data(push, syncs | (depth << 6)); +- evo_data(push, magic); +- evo_kick(push, mast); +- } +- +- ctrl = proto << 8; +- mask = 0x00000f00; +- } else { +- ctrl = (depth << 16) | (proto << 8); +- if (mode->flags & DRM_MODE_FLAG_NHSYNC) +- ctrl |= 0x00001000; +- if (mode->flags & DRM_MODE_FLAG_NVSYNC) +- ctrl |= 0x00002000; +- mask = 0x000f3f00; +- } +- +- nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner); +-} +- +-static void +-nv50_sor_destroy(struct drm_encoder *encoder) +-{ +- drm_encoder_cleanup(encoder); +- kfree(encoder); +-} +- +-static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { +- .dpms = nv50_sor_dpms, +- .mode_fixup = nv50_sor_mode_fixup, +- .prepare = nv50_sor_disconnect, +- .commit = nv50_sor_commit, +- .mode_set = nv50_sor_mode_set, +- .disable = nv50_sor_disconnect, +- .get_crtc = nv50_display_crtc_get, +-}; +- +-static const struct drm_encoder_funcs nv50_sor_func = { +- .destroy = nv50_sor_destroy, +-}; +- +-static int +-nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- struct nouveau_encoder *nv_encoder; +- struct drm_encoder *encoder; +- int type; +- +- switch (dcbe->type) { +- case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; +- case DCB_OUTPUT_TMDS: +- case DCB_OUTPUT_DP: +- default: +- type = DRM_MODE_ENCODER_TMDS; +- break; +- } +- +- nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); +- if (!nv_encoder) +- return -ENOMEM; +- nv_encoder->dcb = dcbe; +- nv_encoder->or = ffs(dcbe->or) - 1; +- nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); +- nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; +- +- encoder = to_drm_encoder(nv_encoder); +- encoder->possible_crtcs = dcbe->heads; +- encoder->possible_clones = 0; +- drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); +- drm_encoder_helper_add(encoder, &nv50_sor_hfunc); +- +- drm_mode_connector_attach_encoder(connector, encoder); +- return 0; +-} +- +-/****************************************************************************** +- * PIOR +- *****************************************************************************/ +- +-static void +-nv50_pior_dpms(struct drm_encoder *encoder, int mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_disp *disp = nv50_disp(encoder->dev); +- struct { +- struct nv50_disp_mthd_v1 base; +- struct nv50_disp_pior_pwr_v0 pwr; +- } args = { +- .base.version = 1, +- .base.method = NV50_DISP_MTHD_V1_PIOR_PWR, +- .base.hasht = nv_encoder->dcb->hasht, +- .base.hashm = nv_encoder->dcb->hashm, +- .pwr.state = mode == DRM_MODE_DPMS_ON, +- .pwr.type = nv_encoder->dcb->type, +- }; +- +- nvif_mthd(disp->disp, 0, &args, sizeof(args)); +-} +- +-static bool +-nv50_pior_mode_fixup(struct drm_encoder *encoder, +- const struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_connector *nv_connector; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- if (nv_connector && nv_connector->native_mode) { +- if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { +- int id = adjusted_mode->base.id; +- *adjusted_mode = *nv_connector->native_mode; +- adjusted_mode->base.id = id; +- } +- } +- +- adjusted_mode->clock *= 2; +- return true; +-} +- +-static void +-nv50_pior_commit(struct drm_encoder *encoder) +-{ +-} +- +-static void +-nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, +- struct drm_display_mode *adjusted_mode) +-{ +- struct nv50_mast *mast = nv50_mast(encoder->dev); +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); +- struct nouveau_connector *nv_connector; +- u8 owner = 1 << nv_crtc->index; +- u8 proto, depth; +- u32 *push; +- +- nv_connector = nouveau_encoder_connector_get(nv_encoder); +- switch (nv_connector->base.display_info.bpc) { +- case 10: depth = 0x6; break; +- case 8: depth = 0x5; break; +- case 6: depth = 0x2; break; +- default: depth = 0x0; break; +- } +- +- switch (nv_encoder->dcb->type) { +- case DCB_OUTPUT_TMDS: +- case DCB_OUTPUT_DP: +- proto = 0x0; +- break; +- default: +- BUG_ON(1); +- break; +- } +- +- nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); +- +- push = evo_wait(mast, 8); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- u32 ctrl = (depth << 16) | (proto << 8) | owner; +- if (mode->flags & DRM_MODE_FLAG_NHSYNC) +- ctrl |= 0x00001000; +- if (mode->flags & DRM_MODE_FLAG_NVSYNC) +- ctrl |= 0x00002000; +- evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); +- evo_data(push, ctrl); +- } +- +- evo_kick(push, mast); +- } +- +- nv_encoder->crtc = encoder->crtc; +-} +- +-static void +-nv50_pior_disconnect(struct drm_encoder *encoder) +-{ +- struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); +- struct nv50_mast *mast = nv50_mast(encoder->dev); +- const int or = nv_encoder->or; +- u32 *push; +- +- if (nv_encoder->crtc) { +- nv50_crtc_prepare(nv_encoder->crtc); +- +- push = evo_wait(mast, 4); +- if (push) { +- if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) { +- evo_mthd(push, 0x0700 + (or * 0x040), 1); +- evo_data(push, 0x00000000); +- } +- evo_kick(push, mast); +- } +- } +- +- nv_encoder->crtc = NULL; +-} +- +-static void +-nv50_pior_destroy(struct drm_encoder *encoder) +-{ +- drm_encoder_cleanup(encoder); +- kfree(encoder); +-} +- +-static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { +- .dpms = nv50_pior_dpms, +- .mode_fixup = nv50_pior_mode_fixup, +- .prepare = nv50_pior_disconnect, +- .commit = nv50_pior_commit, +- .mode_set = nv50_pior_mode_set, +- .disable = nv50_pior_disconnect, +- .get_crtc = nv50_display_crtc_get, +-}; +- +-static const struct drm_encoder_funcs nv50_pior_func = { +- .destroy = nv50_pior_destroy, +-}; +- +-static int +-nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) +-{ +- struct nouveau_drm *drm = nouveau_drm(connector->dev); +- struct nouveau_i2c *i2c = nvkm_i2c(&drm->device); +- struct nouveau_i2c_port *ddc = NULL; +- struct nouveau_encoder *nv_encoder; +- struct drm_encoder *encoder; +- int type; +- +- switch (dcbe->type) { +- case DCB_OUTPUT_TMDS: +- ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); +- type = DRM_MODE_ENCODER_TMDS; +- break; +- case DCB_OUTPUT_DP: +- ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); +- type = DRM_MODE_ENCODER_TMDS; +- break; +- default: +- return -ENODEV; +- } +- +- nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); +- if (!nv_encoder) +- return -ENOMEM; +- nv_encoder->dcb = dcbe; +- nv_encoder->or = ffs(dcbe->or) - 1; +- nv_encoder->i2c = ddc; +- +- encoder = to_drm_encoder(nv_encoder); +- encoder->possible_crtcs = dcbe->heads; +- encoder->possible_clones = 0; +- drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); +- drm_encoder_helper_add(encoder, &nv50_pior_hfunc); +- +- drm_mode_connector_attach_encoder(connector, encoder); +- return 0; +-} +- +-/****************************************************************************** +- * Framebuffer +- *****************************************************************************/ +- +-static void +-nv50_fbdma_fini(struct nv50_fbdma *fbdma) +-{ +- int i; +- for (i = 0; i < ARRAY_SIZE(fbdma->base); i++) +- nvif_object_fini(&fbdma->base[i]); +- nvif_object_fini(&fbdma->core); +- list_del(&fbdma->head); +- kfree(fbdma); +-} +- +-static int +-nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind) +-{ +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nv50_disp *disp = nv50_disp(dev); +- struct nv50_mast *mast = nv50_mast(dev); +- struct __attribute__ ((packed)) { +- struct nv_dma_v0 base; +- union { +- struct nv50_dma_v0 nv50; +- struct gf100_dma_v0 gf100; +- struct gf110_dma_v0 gf110; +- }; +- } args = {}; +- struct nv50_fbdma *fbdma; +- struct drm_crtc *crtc; +- u32 size = sizeof(args.base); +- int ret; +- +- list_for_each_entry(fbdma, &disp->fbdma, head) { +- if (fbdma->core.handle == name) +- return 0; +- } +- +- fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL); +- if (!fbdma) +- return -ENOMEM; +- list_add(&fbdma->head, &disp->fbdma); +- +- args.base.target = NV_DMA_V0_TARGET_VRAM; +- args.base.access = NV_DMA_V0_ACCESS_RDWR; +- args.base.start = offset; +- args.base.limit = offset + length - 1; +- +- if (drm->device.info.chipset < 0x80) { +- args.nv50.part = NV50_DMA_V0_PART_256; +- size += sizeof(args.nv50); +- } else +- if (drm->device.info.chipset < 0xc0) { +- args.nv50.part = NV50_DMA_V0_PART_256; +- args.nv50.kind = kind; +- size += sizeof(args.nv50); +- } else +- if (drm->device.info.chipset < 0xd0) { +- args.gf100.kind = kind; +- size += sizeof(args.gf100); +- } else { +- args.gf110.page = GF110_DMA_V0_PAGE_LP; +- args.gf110.kind = kind; +- size += sizeof(args.gf110); +- } +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nv50_head *head = nv50_head(crtc); +- int ret = nvif_object_init(&head->sync.base.base.user, NULL, +- name, NV_DMA_IN_MEMORY, &args, size, +- &fbdma->base[head->base.index]); +- if (ret) { +- nv50_fbdma_fini(fbdma); +- return ret; +- } +- } +- +- ret = nvif_object_init(&mast->base.base.user, NULL, name, +- NV_DMA_IN_MEMORY, &args, size, +- &fbdma->core); +- if (ret) { +- nv50_fbdma_fini(fbdma); +- return ret; +- } +- +- return 0; +-} +- +-static void +-nv50_fb_dtor(struct drm_framebuffer *fb) +-{ +-} +- +-static int +-nv50_fb_ctor(struct drm_framebuffer *fb) +-{ +- struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); +- struct nouveau_drm *drm = nouveau_drm(fb->dev); +- struct nouveau_bo *nvbo = nv_fb->nvbo; +- struct nv50_disp *disp = nv50_disp(fb->dev); +- u8 kind = nouveau_bo_tile_layout(nvbo) >> 8; +- u8 tile = nvbo->tile_mode; +- +- if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) { +- NV_ERROR(drm, "framebuffer requires contiguous bo\n"); +- return -EINVAL; +- } +- +- if (drm->device.info.chipset >= 0xc0) +- tile >>= 4; /* yep.. */ +- +- switch (fb->depth) { +- case 8: nv_fb->r_format = 0x1e00; break; +- case 15: nv_fb->r_format = 0xe900; break; +- case 16: nv_fb->r_format = 0xe800; break; +- case 24: +- case 32: nv_fb->r_format = 0xcf00; break; +- case 30: nv_fb->r_format = 0xd100; break; +- default: +- NV_ERROR(drm, "unknown depth %d\n", fb->depth); +- return -EINVAL; +- } +- +- if (disp->disp->oclass < G82_DISP) { +- nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : +- (fb->pitches[0] | 0x00100000); +- nv_fb->r_format |= kind << 16; +- } else +- if (disp->disp->oclass < GF110_DISP) { +- nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : +- (fb->pitches[0] | 0x00100000); +- } else { +- nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) : +- (fb->pitches[0] | 0x01000000); +- } +- nv_fb->r_handle = 0xffff0000 | kind; +- +- return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0, +- drm->device.info.ram_user, kind); +-} +- +-/****************************************************************************** +- * Init +- *****************************************************************************/ +- +-void +-nv50_display_fini(struct drm_device *dev) +-{ +-} +- +-int +-nv50_display_init(struct drm_device *dev) +-{ +- struct nv50_disp *disp = nv50_disp(dev); +- struct drm_crtc *crtc; +- u32 *push; +- +- push = evo_wait(nv50_mast(dev), 32); +- if (!push) +- return -EBUSY; +- +- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { +- struct nv50_sync *sync = nv50_sync(crtc); +- nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); +- } +- +- evo_mthd(push, 0x0088, 1); +- evo_data(push, nv50_mast(dev)->base.sync.handle); +- evo_kick(push, nv50_mast(dev)); +- return 0; +-} +- +-void +-nv50_display_destroy(struct drm_device *dev) +-{ +- struct nv50_disp *disp = nv50_disp(dev); +- struct nv50_fbdma *fbdma, *fbtmp; +- +- list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) { +- nv50_fbdma_fini(fbdma); +- } +- +- nv50_dmac_destroy(&disp->mast.base, disp->disp); +- +- nouveau_bo_unmap(disp->sync); +- if (disp->sync) +- nouveau_bo_unpin(disp->sync); +- nouveau_bo_ref(NULL, &disp->sync); +- +- nouveau_display(dev)->priv = NULL; +- kfree(disp); +-} +- +-int +-nv50_display_create(struct drm_device *dev) +-{ +- struct nvif_device *device = &nouveau_drm(dev)->device; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct dcb_table *dcb = &drm->vbios.dcb; +- struct drm_connector *connector, *tmp; +- struct nv50_disp *disp; +- struct dcb_output *dcbe; +- int crtcs, ret, i; +- +- disp = kzalloc(sizeof(*disp), GFP_KERNEL); +- if (!disp) +- return -ENOMEM; +- INIT_LIST_HEAD(&disp->fbdma); +- +- nouveau_display(dev)->priv = disp; +- nouveau_display(dev)->dtor = nv50_display_destroy; +- nouveau_display(dev)->init = nv50_display_init; +- nouveau_display(dev)->fini = nv50_display_fini; +- nouveau_display(dev)->fb_ctor = nv50_fb_ctor; +- nouveau_display(dev)->fb_dtor = nv50_fb_dtor; +- disp->disp = &nouveau_display(dev)->disp; +- +- /* small shared memory area we use for notifiers and semaphores */ +- ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, +- 0, 0x0000, NULL, NULL, &disp->sync); +- if (!ret) { +- ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); +- if (!ret) { +- ret = nouveau_bo_map(disp->sync); +- if (ret) +- nouveau_bo_unpin(disp->sync); +- } +- if (ret) +- nouveau_bo_ref(NULL, &disp->sync); +- } +- +- if (ret) +- goto out; +- +- /* allocate master evo channel */ +- ret = nv50_core_create(disp->disp, disp->sync->bo.offset, +- &disp->mast); +- if (ret) +- goto out; +- +- /* create crtc objects to represent the hw heads */ +- if (disp->disp->oclass >= GF110_DISP) +- crtcs = nvif_rd32(device, 0x022448); +- else +- crtcs = 2; +- +- for (i = 0; i < crtcs; i++) { +- ret = nv50_crtc_create(dev, i); +- if (ret) +- goto out; +- } +- +- /* create encoder/connector objects based on VBIOS DCB table */ +- for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { +- connector = nouveau_connector_create(dev, dcbe->connector); +- if (IS_ERR(connector)) +- continue; +- +- if (dcbe->location == DCB_LOC_ON_CHIP) { +- switch (dcbe->type) { +- case DCB_OUTPUT_TMDS: +- case DCB_OUTPUT_LVDS: +- case DCB_OUTPUT_DP: +- ret = nv50_sor_create(connector, dcbe); +- break; +- case DCB_OUTPUT_ANALOG: +- ret = nv50_dac_create(connector, dcbe); +- break; +- default: +- ret = -ENODEV; +- break; +- } +- } else { +- ret = nv50_pior_create(connector, dcbe); +- } +- +- if (ret) { +- NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", +- dcbe->location, dcbe->type, +- ffs(dcbe->or) - 1, ret); +- ret = 0; +- } +- } +- +- /* cull any connectors we created that don't have an encoder */ +- list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { +- if (connector->encoder_ids[0]) +- continue; +- +- NV_WARN(drm, "%s has no encoders, removing\n", +- connector->name); +- connector->funcs->destroy(connector); +- } +- +-out: +- if (ret) +- nv50_display_destroy(dev); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h +deleted file mode 100644 +index 70da347a..00000000 +--- a/drivers/gpu/drm/nouveau/nv50_display.h ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright (C) 2008 Maarten Maathuis. +- * All Rights Reserved. +- * +- * Permission is hereby granted, free of charge, to any person obtaining +- * a copy of this software and associated documentation files (the +- * "Software"), to deal in the Software without restriction, including +- * without limitation the rights to use, copy, modify, merge, publish, +- * distribute, sublicense, and/or sell copies of the Software, and to +- * permit persons to whom the Software is furnished to do so, subject to +- * the following conditions: +- * +- * The above copyright notice and this permission notice (including the +- * next paragraph) shall be included in all copies or substantial +- * portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +- * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE +- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +- * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +- * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +- * +- */ +- +-#ifndef __NV50_DISPLAY_H__ +-#define __NV50_DISPLAY_H__ +- +-#include "nouveau_display.h" +-#include "nouveau_crtc.h" +-#include "nouveau_reg.h" +- +-int nv50_display_create(struct drm_device *); +-void nv50_display_destroy(struct drm_device *); +-int nv50_display_init(struct drm_device *); +-void nv50_display_fini(struct drm_device *); +- +-void nv50_display_flip_stop(struct drm_crtc *); +-int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, +- struct nouveau_channel *, u32 swap_interval); +- +-struct nouveau_bo *nv50_display_crtc_sema(struct drm_device *, int head); +- +-#endif /* __NV50_DISPLAY_H__ */ +diff --git a/drivers/gpu/drm/nouveau/nv50_fbcon.c b/drivers/gpu/drm/nouveau/nv50_fbcon.c +deleted file mode 100644 +index 394c89ab..00000000 +--- a/drivers/gpu/drm/nouveau/nv50_fbcon.c ++++ /dev/null +@@ -1,258 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fbcon.h" +- +-int +-nv50_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); +- if (ret) +- return ret; +- +- if (rect->rop != ROP_COPY) { +- BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); +- OUT_RING(chan, 1); +- } +- BEGIN_NV04(chan, NvSub2D, 0x0588, 1); +- if (info->fix.visual == FB_VISUAL_TRUECOLOR || +- info->fix.visual == FB_VISUAL_DIRECTCOLOR) +- OUT_RING(chan, ((uint32_t *)info->pseudo_palette)[rect->color]); +- else +- OUT_RING(chan, rect->color); +- BEGIN_NV04(chan, NvSub2D, 0x0600, 4); +- OUT_RING(chan, rect->dx); +- OUT_RING(chan, rect->dy); +- OUT_RING(chan, rect->dx + rect->width); +- OUT_RING(chan, rect->dy + rect->height); +- if (rect->rop != ROP_COPY) { +- BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); +- OUT_RING(chan, 3); +- } +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nv50_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- ret = RING_SPACE(chan, 12); +- if (ret) +- return ret; +- +- BEGIN_NV04(chan, NvSub2D, 0x0110, 1); +- OUT_RING(chan, 0); +- BEGIN_NV04(chan, NvSub2D, 0x08b0, 4); +- OUT_RING(chan, region->dx); +- OUT_RING(chan, region->dy); +- OUT_RING(chan, region->width); +- OUT_RING(chan, region->height); +- BEGIN_NV04(chan, NvSub2D, 0x08d0, 4); +- OUT_RING(chan, 0); +- OUT_RING(chan, region->sx); +- OUT_RING(chan, 0); +- OUT_RING(chan, region->sy); +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nv50_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- uint32_t width, dwords, *data = (uint32_t *)image->data; +- uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); +- uint32_t *palette = info->pseudo_palette; +- int ret; +- +- if (image->depth != 1) +- return -ENODEV; +- +- ret = RING_SPACE(chan, 11); +- if (ret) +- return ret; +- +- width = ALIGN(image->width, 32); +- dwords = (width * image->height) >> 5; +- +- BEGIN_NV04(chan, NvSub2D, 0x0814, 2); +- if (info->fix.visual == FB_VISUAL_TRUECOLOR || +- info->fix.visual == FB_VISUAL_DIRECTCOLOR) { +- OUT_RING(chan, palette[image->bg_color] | mask); +- OUT_RING(chan, palette[image->fg_color] | mask); +- } else { +- OUT_RING(chan, image->bg_color); +- OUT_RING(chan, image->fg_color); +- } +- BEGIN_NV04(chan, NvSub2D, 0x0838, 2); +- OUT_RING(chan, image->width); +- OUT_RING(chan, image->height); +- BEGIN_NV04(chan, NvSub2D, 0x0850, 4); +- OUT_RING(chan, 0); +- OUT_RING(chan, image->dx); +- OUT_RING(chan, 0); +- OUT_RING(chan, image->dy); +- +- while (dwords) { +- int push = dwords > 2047 ? 2047 : dwords; +- +- ret = RING_SPACE(chan, push + 1); +- if (ret) +- return ret; +- +- dwords -= push; +- +- BEGIN_NI04(chan, NvSub2D, 0x0860, push); +- OUT_RINGp(chan, data, push); +- data += push; +- } +- +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nv50_fbcon_accel_init(struct fb_info *info) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb; +- struct drm_device *dev = nfbdev->dev; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_channel *chan = drm->channel; +- int ret, format; +- +- switch (info->var.bits_per_pixel) { +- case 8: +- format = 0xf3; +- break; +- case 15: +- format = 0xf8; +- break; +- case 16: +- format = 0xe8; +- break; +- case 32: +- switch (info->var.transp.length) { +- case 0: /* depth 24 */ +- case 8: /* depth 32, just use 24.. */ +- format = 0xe6; +- break; +- case 2: /* depth 30 */ +- format = 0xd1; +- break; +- default: +- return -EINVAL; +- } +- break; +- default: +- return -EINVAL; +- } +- +- ret = nvif_object_init(chan->object, NULL, 0x502d, 0x502d, NULL, 0, +- &nfbdev->twod); +- if (ret) +- return ret; +- +- ret = RING_SPACE(chan, 59); +- if (ret) { +- nouveau_fbcon_gpu_lockup(info); +- return ret; +- } +- +- BEGIN_NV04(chan, NvSub2D, 0x0000, 1); +- OUT_RING(chan, nfbdev->twod.handle); +- BEGIN_NV04(chan, NvSub2D, 0x0184, 3); +- OUT_RING(chan, chan->vram.handle); +- OUT_RING(chan, chan->vram.handle); +- OUT_RING(chan, chan->vram.handle); +- BEGIN_NV04(chan, NvSub2D, 0x0290, 1); +- OUT_RING(chan, 0); +- BEGIN_NV04(chan, NvSub2D, 0x0888, 1); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x02ac, 1); +- OUT_RING(chan, 3); +- BEGIN_NV04(chan, NvSub2D, 0x02a0, 1); +- OUT_RING(chan, 0x55); +- BEGIN_NV04(chan, NvSub2D, 0x08c0, 4); +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0580, 2); +- OUT_RING(chan, 4); +- OUT_RING(chan, format); +- BEGIN_NV04(chan, NvSub2D, 0x02e8, 2); +- OUT_RING(chan, 2); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0804, 1); +- OUT_RING(chan, format); +- BEGIN_NV04(chan, NvSub2D, 0x0800, 1); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0808, 3); +- OUT_RING(chan, 0); +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x081c, 1); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0840, 4); +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- OUT_RING(chan, 0); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0200, 2); +- OUT_RING(chan, format); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0214, 5); +- OUT_RING(chan, info->fix.line_length); +- OUT_RING(chan, info->var.xres_virtual); +- OUT_RING(chan, info->var.yres_virtual); +- OUT_RING(chan, upper_32_bits(fb->vma.offset)); +- OUT_RING(chan, lower_32_bits(fb->vma.offset)); +- BEGIN_NV04(chan, NvSub2D, 0x0230, 2); +- OUT_RING(chan, format); +- OUT_RING(chan, 1); +- BEGIN_NV04(chan, NvSub2D, 0x0244, 5); +- OUT_RING(chan, info->fix.line_length); +- OUT_RING(chan, info->var.xres_virtual); +- OUT_RING(chan, info->var.yres_virtual); +- OUT_RING(chan, upper_32_bits(fb->vma.offset)); +- OUT_RING(chan, lower_32_bits(fb->vma.offset)); +- +- return 0; +-} +- +diff --git a/drivers/gpu/drm/nouveau/nv50_fence.c b/drivers/gpu/drm/nouveau/nv50_fence.c +deleted file mode 100644 +index 22d242b3..00000000 +--- a/drivers/gpu/drm/nouveau/nv50_fence.c ++++ /dev/null +@@ -1,122 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nv10_fence.h" +- +-#include "nv50_display.h" +- +-static int +-nv50_fence_context_new(struct nouveau_channel *chan) +-{ +- struct drm_device *dev = chan->drm->dev; +- struct nv10_fence_priv *priv = chan->drm->fence; +- struct nv10_fence_chan *fctx; +- struct ttm_mem_reg *mem = &priv->bo->bo.mem; +- u32 start = mem->start * PAGE_SIZE; +- u32 limit = start + mem->size - 1; +- int ret, i; +- +- fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); +- if (!fctx) +- return -ENOMEM; +- +- nouveau_fence_context_new(chan, &fctx->base); +- fctx->base.emit = nv10_fence_emit; +- fctx->base.read = nv10_fence_read; +- fctx->base.sync = nv17_fence_sync; +- +- ret = nvif_object_init(chan->object, NULL, NvSema, NV_DMA_IN_MEMORY, +- &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_VRAM, +- .access = NV_DMA_V0_ACCESS_RDWR, +- .start = start, +- .limit = limit, +- }, sizeof(struct nv_dma_v0), +- &fctx->sema); +- +- /* dma objects for display sync channel semaphore blocks */ +- for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { +- struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); +- u32 start = bo->bo.mem.start * PAGE_SIZE; +- u32 limit = start + bo->bo.mem.size - 1; +- +- ret = nvif_object_init(chan->object, NULL, NvEvoSema0 + i, +- NV_DMA_IN_MEMORY, &(struct nv_dma_v0) { +- .target = NV_DMA_V0_TARGET_VRAM, +- .access = NV_DMA_V0_ACCESS_RDWR, +- .start = start, +- .limit = limit, +- }, sizeof(struct nv_dma_v0), +- &fctx->head[i]); +- } +- +- if (ret) +- nv10_fence_context_del(chan); +- return ret; +-} +- +-int +-nv50_fence_create(struct nouveau_drm *drm) +-{ +- struct nv10_fence_priv *priv; +- int ret = 0; +- +- priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->base.dtor = nv10_fence_destroy; +- priv->base.resume = nv17_fence_resume; +- priv->base.context_new = nv50_fence_context_new; +- priv->base.context_del = nv10_fence_context_del; +- priv->base.contexts = 127; +- priv->base.context_base = fence_context_alloc(priv->base.contexts); +- spin_lock_init(&priv->lock); +- +- ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, +- 0, 0x0000, NULL, NULL, &priv->bo); +- if (!ret) { +- ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); +- if (!ret) { +- ret = nouveau_bo_map(priv->bo); +- if (ret) +- nouveau_bo_unpin(priv->bo); +- } +- if (ret) +- nouveau_bo_ref(NULL, &priv->bo); +- } +- +- if (ret) { +- nv10_fence_destroy(drm); +- return ret; +- } +- +- nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c +deleted file mode 100644 +index d6c6c87c..00000000 +--- a/drivers/gpu/drm/nouveau/nv84_fence.c ++++ /dev/null +@@ -1,265 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fence.h" +- +-#include "nv50_display.h" +- +-u64 +-nv84_fence_crtc(struct nouveau_channel *chan, int crtc) +-{ +- struct nv84_fence_chan *fctx = chan->fence; +- return fctx->dispc_vma[crtc].offset; +-} +- +-static int +-nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) +-{ +- int ret = RING_SPACE(chan, 8); +- if (ret == 0) { +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); +- OUT_RING (chan, chan->vram.handle); +- BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); +- OUT_RING (chan, upper_32_bits(virtual)); +- OUT_RING (chan, lower_32_bits(virtual)); +- OUT_RING (chan, sequence); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); +- OUT_RING (chan, 0x00000000); +- FIRE_RING (chan); +- } +- return ret; +-} +- +-static int +-nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) +-{ +- int ret = RING_SPACE(chan, 7); +- if (ret == 0) { +- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); +- OUT_RING (chan, chan->vram.handle); +- BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); +- OUT_RING (chan, upper_32_bits(virtual)); +- OUT_RING (chan, lower_32_bits(virtual)); +- OUT_RING (chan, sequence); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL); +- FIRE_RING (chan); +- } +- return ret; +-} +- +-static int +-nv84_fence_emit(struct nouveau_fence *fence) +-{ +- struct nouveau_channel *chan = fence->channel; +- struct nv84_fence_chan *fctx = chan->fence; +- u64 addr = chan->chid * 16; +- +- if (fence->sysmem) +- addr += fctx->vma_gart.offset; +- else +- addr += fctx->vma.offset; +- +- return fctx->base.emit32(chan, addr, fence->base.seqno); +-} +- +-static int +-nv84_fence_sync(struct nouveau_fence *fence, +- struct nouveau_channel *prev, struct nouveau_channel *chan) +-{ +- struct nv84_fence_chan *fctx = chan->fence; +- u64 addr = prev->chid * 16; +- +- if (fence->sysmem) +- addr += fctx->vma_gart.offset; +- else +- addr += fctx->vma.offset; +- +- return fctx->base.sync32(chan, addr, fence->base.seqno); +-} +- +-static u32 +-nv84_fence_read(struct nouveau_channel *chan) +-{ +- struct nv84_fence_priv *priv = chan->drm->fence; +- return nouveau_bo_rd32(priv->bo, chan->chid * 16/4); +-} +- +-static void +-nv84_fence_context_del(struct nouveau_channel *chan) +-{ +- struct drm_device *dev = chan->drm->dev; +- struct nv84_fence_priv *priv = chan->drm->fence; +- struct nv84_fence_chan *fctx = chan->fence; +- int i; +- +- for (i = 0; i < dev->mode_config.num_crtc; i++) { +- struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); +- nouveau_bo_vma_del(bo, &fctx->dispc_vma[i]); +- } +- +- nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); +- nouveau_bo_vma_del(priv->bo, &fctx->vma_gart); +- nouveau_bo_vma_del(priv->bo, &fctx->vma); +- nouveau_fence_context_del(&fctx->base); +- chan->fence = NULL; +- nouveau_fence_context_free(&fctx->base); +-} +- +-int +-nv84_fence_context_new(struct nouveau_channel *chan) +-{ +- struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base); +- struct nv84_fence_priv *priv = chan->drm->fence; +- struct nv84_fence_chan *fctx; +- int ret, i; +- +- fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); +- if (!fctx) +- return -ENOMEM; +- +- nouveau_fence_context_new(chan, &fctx->base); +- fctx->base.emit = nv84_fence_emit; +- fctx->base.sync = nv84_fence_sync; +- fctx->base.read = nv84_fence_read; +- fctx->base.emit32 = nv84_fence_emit32; +- fctx->base.sync32 = nv84_fence_sync32; +- fctx->base.sequence = nv84_fence_read(chan); +- +- ret = nouveau_bo_vma_add(priv->bo, cli->vm, &fctx->vma); +- if (ret == 0) { +- ret = nouveau_bo_vma_add(priv->bo_gart, cli->vm, +- &fctx->vma_gart); +- } +- +- /* map display semaphore buffers into channel's vm */ +- for (i = 0; !ret && i < chan->drm->dev->mode_config.num_crtc; i++) { +- struct nouveau_bo *bo = nv50_display_crtc_sema(chan->drm->dev, i); +- ret = nouveau_bo_vma_add(bo, cli->vm, &fctx->dispc_vma[i]); +- } +- +- if (ret) +- nv84_fence_context_del(chan); +- return ret; +-} +- +-static bool +-nv84_fence_suspend(struct nouveau_drm *drm) +-{ +- struct nv84_fence_priv *priv = drm->fence; +- int i; +- +- priv->suspend = vmalloc(priv->base.contexts * sizeof(u32)); +- if (priv->suspend) { +- for (i = 0; i < priv->base.contexts; i++) +- priv->suspend[i] = nouveau_bo_rd32(priv->bo, i*4); +- } +- +- return priv->suspend != NULL; +-} +- +-static void +-nv84_fence_resume(struct nouveau_drm *drm) +-{ +- struct nv84_fence_priv *priv = drm->fence; +- int i; +- +- if (priv->suspend) { +- for (i = 0; i < priv->base.contexts; i++) +- nouveau_bo_wr32(priv->bo, i*4, priv->suspend[i]); +- vfree(priv->suspend); +- priv->suspend = NULL; +- } +-} +- +-static void +-nv84_fence_destroy(struct nouveau_drm *drm) +-{ +- struct nv84_fence_priv *priv = drm->fence; +- nouveau_bo_unmap(priv->bo_gart); +- if (priv->bo_gart) +- nouveau_bo_unpin(priv->bo_gart); +- nouveau_bo_ref(NULL, &priv->bo_gart); +- nouveau_bo_unmap(priv->bo); +- if (priv->bo) +- nouveau_bo_unpin(priv->bo); +- nouveau_bo_ref(NULL, &priv->bo); +- drm->fence = NULL; +- kfree(priv); +-} +- +-int +-nv84_fence_create(struct nouveau_drm *drm) +-{ +- struct nouveau_fifo *pfifo = nvkm_fifo(&drm->device); +- struct nv84_fence_priv *priv; +- int ret; +- +- priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- +- priv->base.dtor = nv84_fence_destroy; +- priv->base.suspend = nv84_fence_suspend; +- priv->base.resume = nv84_fence_resume; +- priv->base.context_new = nv84_fence_context_new; +- priv->base.context_del = nv84_fence_context_del; +- +- priv->base.contexts = pfifo->max + 1; +- priv->base.context_base = fence_context_alloc(priv->base.contexts); +- priv->base.uevent = true; +- +- ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, +- TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL, &priv->bo); +- if (ret == 0) { +- ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); +- if (ret == 0) { +- ret = nouveau_bo_map(priv->bo); +- if (ret) +- nouveau_bo_unpin(priv->bo); +- } +- if (ret) +- nouveau_bo_ref(NULL, &priv->bo); +- } +- +- if (ret == 0) +- ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, +- TTM_PL_FLAG_TT, 0, 0, NULL, NULL, +- &priv->bo_gart); +- if (ret == 0) { +- ret = nouveau_bo_pin(priv->bo_gart, TTM_PL_FLAG_TT); +- if (ret == 0) { +- ret = nouveau_bo_map(priv->bo_gart); +- if (ret) +- nouveau_bo_unpin(priv->bo_gart); +- } +- if (ret) +- nouveau_bo_ref(NULL, &priv->bo_gart); +- } +- +- if (ret) +- nv84_fence_destroy(drm); +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nvc0_fbcon.c b/drivers/gpu/drm/nouveau/nvc0_fbcon.c +deleted file mode 100644 +index 61246677..00000000 +--- a/drivers/gpu/drm/nouveau/nvc0_fbcon.c ++++ /dev/null +@@ -1,261 +0,0 @@ +-/* +- * Copyright 2010 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fbcon.h" +- +-int +-nvc0_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- ret = RING_SPACE(chan, rect->rop == ROP_COPY ? 7 : 11); +- if (ret) +- return ret; +- +- if (rect->rop != ROP_COPY) { +- BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); +- OUT_RING (chan, 1); +- } +- BEGIN_NVC0(chan, NvSub2D, 0x0588, 1); +- if (info->fix.visual == FB_VISUAL_TRUECOLOR || +- info->fix.visual == FB_VISUAL_DIRECTCOLOR) +- OUT_RING (chan, ((uint32_t *)info->pseudo_palette)[rect->color]); +- else +- OUT_RING (chan, rect->color); +- BEGIN_NVC0(chan, NvSub2D, 0x0600, 4); +- OUT_RING (chan, rect->dx); +- OUT_RING (chan, rect->dy); +- OUT_RING (chan, rect->dx + rect->width); +- OUT_RING (chan, rect->dy + rect->height); +- if (rect->rop != ROP_COPY) { +- BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); +- OUT_RING (chan, 3); +- } +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nvc0_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- int ret; +- +- ret = RING_SPACE(chan, 12); +- if (ret) +- return ret; +- +- BEGIN_NVC0(chan, NvSub2D, 0x0110, 1); +- OUT_RING (chan, 0); +- BEGIN_NVC0(chan, NvSub2D, 0x08b0, 4); +- OUT_RING (chan, region->dx); +- OUT_RING (chan, region->dy); +- OUT_RING (chan, region->width); +- OUT_RING (chan, region->height); +- BEGIN_NVC0(chan, NvSub2D, 0x08d0, 4); +- OUT_RING (chan, 0); +- OUT_RING (chan, region->sx); +- OUT_RING (chan, 0); +- OUT_RING (chan, region->sy); +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nvc0_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct nouveau_drm *drm = nouveau_drm(nfbdev->dev); +- struct nouveau_channel *chan = drm->channel; +- uint32_t width, dwords, *data = (uint32_t *)image->data; +- uint32_t mask = ~(~0 >> (32 - info->var.bits_per_pixel)); +- uint32_t *palette = info->pseudo_palette; +- int ret; +- +- if (image->depth != 1) +- return -ENODEV; +- +- ret = RING_SPACE(chan, 11); +- if (ret) +- return ret; +- +- width = ALIGN(image->width, 32); +- dwords = (width * image->height) >> 5; +- +- BEGIN_NVC0(chan, NvSub2D, 0x0814, 2); +- if (info->fix.visual == FB_VISUAL_TRUECOLOR || +- info->fix.visual == FB_VISUAL_DIRECTCOLOR) { +- OUT_RING (chan, palette[image->bg_color] | mask); +- OUT_RING (chan, palette[image->fg_color] | mask); +- } else { +- OUT_RING (chan, image->bg_color); +- OUT_RING (chan, image->fg_color); +- } +- BEGIN_NVC0(chan, NvSub2D, 0x0838, 2); +- OUT_RING (chan, image->width); +- OUT_RING (chan, image->height); +- BEGIN_NVC0(chan, NvSub2D, 0x0850, 4); +- OUT_RING (chan, 0); +- OUT_RING (chan, image->dx); +- OUT_RING (chan, 0); +- OUT_RING (chan, image->dy); +- +- while (dwords) { +- int push = dwords > 2047 ? 2047 : dwords; +- +- ret = RING_SPACE(chan, push + 1); +- if (ret) +- return ret; +- +- dwords -= push; +- +- BEGIN_NIC0(chan, NvSub2D, 0x0860, push); +- OUT_RINGp(chan, data, push); +- data += push; +- } +- +- FIRE_RING(chan); +- return 0; +-} +- +-int +-nvc0_fbcon_accel_init(struct fb_info *info) +-{ +- struct nouveau_fbdev *nfbdev = info->par; +- struct drm_device *dev = nfbdev->dev; +- struct nouveau_framebuffer *fb = &nfbdev->nouveau_fb; +- struct nouveau_drm *drm = nouveau_drm(dev); +- struct nouveau_channel *chan = drm->channel; +- int ret, format; +- +- ret = nvif_object_init(chan->object, NULL, 0x902d, 0x902d, NULL, 0, +- &nfbdev->twod); +- if (ret) +- return ret; +- +- switch (info->var.bits_per_pixel) { +- case 8: +- format = 0xf3; +- break; +- case 15: +- format = 0xf8; +- break; +- case 16: +- format = 0xe8; +- break; +- case 32: +- switch (info->var.transp.length) { +- case 0: /* depth 24 */ +- case 8: /* depth 32, just use 24.. */ +- format = 0xe6; +- break; +- case 2: /* depth 30 */ +- format = 0xd1; +- break; +- default: +- return -EINVAL; +- } +- break; +- default: +- return -EINVAL; +- } +- +- ret = RING_SPACE(chan, 60); +- if (ret) { +- WARN_ON(1); +- nouveau_fbcon_gpu_lockup(info); +- return ret; +- } +- +- BEGIN_NVC0(chan, NvSub2D, 0x0000, 1); +- OUT_RING (chan, nfbdev->twod.handle); +- BEGIN_NVC0(chan, NvSub2D, 0x0290, 1); +- OUT_RING (chan, 0); +- BEGIN_NVC0(chan, NvSub2D, 0x0888, 1); +- OUT_RING (chan, 1); +- BEGIN_NVC0(chan, NvSub2D, 0x02ac, 1); +- OUT_RING (chan, 3); +- BEGIN_NVC0(chan, NvSub2D, 0x02a0, 1); +- OUT_RING (chan, 0x55); +- BEGIN_NVC0(chan, NvSub2D, 0x08c0, 4); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- BEGIN_NVC0(chan, NvSub2D, 0x0580, 2); +- OUT_RING (chan, 4); +- OUT_RING (chan, format); +- BEGIN_NVC0(chan, NvSub2D, 0x02e8, 2); +- OUT_RING (chan, 2); +- OUT_RING (chan, 1); +- +- BEGIN_NVC0(chan, NvSub2D, 0x0804, 1); +- OUT_RING (chan, format); +- BEGIN_NVC0(chan, NvSub2D, 0x0800, 1); +- OUT_RING (chan, 1); +- BEGIN_NVC0(chan, NvSub2D, 0x0808, 3); +- OUT_RING (chan, 0); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- BEGIN_NVC0(chan, NvSub2D, 0x081c, 1); +- OUT_RING (chan, 1); +- BEGIN_NVC0(chan, NvSub2D, 0x0840, 4); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- BEGIN_NVC0(chan, NvSub2D, 0x0200, 10); +- OUT_RING (chan, format); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, info->fix.line_length); +- OUT_RING (chan, info->var.xres_virtual); +- OUT_RING (chan, info->var.yres_virtual); +- OUT_RING (chan, upper_32_bits(fb->vma.offset)); +- OUT_RING (chan, lower_32_bits(fb->vma.offset)); +- BEGIN_NVC0(chan, NvSub2D, 0x0230, 10); +- OUT_RING (chan, format); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, 1); +- OUT_RING (chan, 0); +- OUT_RING (chan, info->fix.line_length); +- OUT_RING (chan, info->var.xres_virtual); +- OUT_RING (chan, info->var.yres_virtual); +- OUT_RING (chan, upper_32_bits(fb->vma.offset)); +- OUT_RING (chan, lower_32_bits(fb->vma.offset)); +- FIRE_RING (chan); +- +- return 0; +-} +- +diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c +deleted file mode 100644 +index becf19ab..00000000 +--- a/drivers/gpu/drm/nouveau/nvc0_fence.c ++++ /dev/null +@@ -1,84 +0,0 @@ +-/* +- * Copyright 2012 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "nouveau_drm.h" +-#include "nouveau_dma.h" +-#include "nouveau_fence.h" +- +-#include "nv50_display.h" +- +-static int +-nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence) +-{ +- int ret = RING_SPACE(chan, 6); +- if (ret == 0) { +- BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 5); +- OUT_RING (chan, upper_32_bits(virtual)); +- OUT_RING (chan, lower_32_bits(virtual)); +- OUT_RING (chan, sequence); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); +- OUT_RING (chan, 0x00000000); +- FIRE_RING (chan); +- } +- return ret; +-} +- +-static int +-nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence) +-{ +- int ret = RING_SPACE(chan, 5); +- if (ret == 0) { +- BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); +- OUT_RING (chan, upper_32_bits(virtual)); +- OUT_RING (chan, lower_32_bits(virtual)); +- OUT_RING (chan, sequence); +- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL | +- NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); +- FIRE_RING (chan); +- } +- return ret; +-} +- +-static int +-nvc0_fence_context_new(struct nouveau_channel *chan) +-{ +- int ret = nv84_fence_context_new(chan); +- if (ret == 0) { +- struct nv84_fence_chan *fctx = chan->fence; +- fctx->base.emit32 = nvc0_fence_emit32; +- fctx->base.sync32 = nvc0_fence_sync32; +- } +- return ret; +-} +- +-int +-nvc0_fence_create(struct nouveau_drm *drm) +-{ +- int ret = nv84_fence_create(drm); +- if (ret == 0) { +- struct nv84_fence_priv *priv = drm->fence; +- priv->base.context_new = nvc0_fence_context_new; +- } +- return ret; +-} +diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h +deleted file mode 100644 +index e5a27df0..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/class.h ++++ /dev/null +@@ -1,567 +0,0 @@ +-#ifndef __NVIF_CLASS_H__ +-#define __NVIF_CLASS_H__ +- +-/******************************************************************************* +- * class identifiers +- ******************************************************************************/ +- +-/* the below match nvidia-assigned (either in hw, or sw) class numbers */ +-#define NV_DEVICE 0x00000080 +- +-#define NV_DMA_FROM_MEMORY 0x00000002 +-#define NV_DMA_TO_MEMORY 0x00000003 +-#define NV_DMA_IN_MEMORY 0x0000003d +- +-#define NV04_DISP 0x00000046 +- +-#define NV03_CHANNEL_DMA 0x0000006b +-#define NV10_CHANNEL_DMA 0x0000006e +-#define NV17_CHANNEL_DMA 0x0000176e +-#define NV40_CHANNEL_DMA 0x0000406e +-#define NV50_CHANNEL_DMA 0x0000506e +-#define G82_CHANNEL_DMA 0x0000826e +- +-#define NV50_CHANNEL_GPFIFO 0x0000506f +-#define G82_CHANNEL_GPFIFO 0x0000826f +-#define FERMI_CHANNEL_GPFIFO 0x0000906f +-#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f +- +-#define NV50_DISP 0x00005070 +-#define G82_DISP 0x00008270 +-#define GT200_DISP 0x00008370 +-#define GT214_DISP 0x00008570 +-#define GT206_DISP 0x00008870 +-#define GF110_DISP 0x00009070 +-#define GK104_DISP 0x00009170 +-#define GK110_DISP 0x00009270 +-#define GM107_DISP 0x00009470 +- +-#define NV50_DISP_CURSOR 0x0000507a +-#define G82_DISP_CURSOR 0x0000827a +-#define GT214_DISP_CURSOR 0x0000857a +-#define GF110_DISP_CURSOR 0x0000907a +-#define GK104_DISP_CURSOR 0x0000917a +- +-#define NV50_DISP_OVERLAY 0x0000507b +-#define G82_DISP_OVERLAY 0x0000827b +-#define GT214_DISP_OVERLAY 0x0000857b +-#define GF110_DISP_OVERLAY 0x0000907b +-#define GK104_DISP_OVERLAY 0x0000917b +- +-#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c +-#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c +-#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c +-#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c +-#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c +-#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c +-#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c +- +-#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d +-#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d +-#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d +-#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d +-#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d +-#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d +-#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d +-#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d +-#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d +- +-#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e +-#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e +-#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e +-#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e +-#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e +-#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e +- +-#define FERMI_A 0x00009097 +-#define FERMI_B 0x00009197 +-#define FERMI_C 0x00009297 +- +-#define KEPLER_A 0x0000a097 +-#define KEPLER_B 0x0000a197 +-#define KEPLER_C 0x0000a297 +- +-#define MAXWELL_A 0x0000b097 +- +-#define FERMI_COMPUTE_A 0x000090c0 +-#define FERMI_COMPUTE_B 0x000091c0 +- +-#define KEPLER_COMPUTE_A 0x0000a0c0 +-#define KEPLER_COMPUTE_B 0x0000a1c0 +- +-#define MAXWELL_COMPUTE_A 0x0000b0c0 +- +- +-/******************************************************************************* +- * client +- ******************************************************************************/ +- +-#define NV_CLIENT_DEVLIST 0x00 +- +-struct nv_client_devlist_v0 { +- __u8 version; +- __u8 count; +- __u8 pad02[6]; +- __u64 device[]; +-}; +- +- +-/******************************************************************************* +- * device +- ******************************************************************************/ +- +-struct nv_device_v0 { +- __u8 version; +- __u8 pad01[7]; +- __u64 device; /* device identifier, ~0 for client default */ +-#define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL +-#define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL +-#define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL +-#define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL +-#define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL +-#define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL +-#define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL +-#define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL +-#define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL +-#define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL +-#define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL +-#define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL +-#define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL +-#define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL +-#define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL +-#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL +-#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL +- __u64 disable; /* disable particular subsystems */ +- __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ +-}; +- +-#define NV_DEVICE_V0_INFO 0x00 +- +-struct nv_device_info_v0 { +- __u8 version; +-#define NV_DEVICE_INFO_V0_IGP 0x00 +-#define NV_DEVICE_INFO_V0_PCI 0x01 +-#define NV_DEVICE_INFO_V0_AGP 0x02 +-#define NV_DEVICE_INFO_V0_PCIE 0x03 +-#define NV_DEVICE_INFO_V0_SOC 0x04 +- __u8 platform; +- __u16 chipset; /* from NV_PMC_BOOT_0 */ +- __u8 revision; /* from NV_PMC_BOOT_0 */ +-#define NV_DEVICE_INFO_V0_TNT 0x01 +-#define NV_DEVICE_INFO_V0_CELSIUS 0x02 +-#define NV_DEVICE_INFO_V0_KELVIN 0x03 +-#define NV_DEVICE_INFO_V0_RANKINE 0x04 +-#define NV_DEVICE_INFO_V0_CURIE 0x05 +-#define NV_DEVICE_INFO_V0_TESLA 0x06 +-#define NV_DEVICE_INFO_V0_FERMI 0x07 +-#define NV_DEVICE_INFO_V0_KEPLER 0x08 +-#define NV_DEVICE_INFO_V0_MAXWELL 0x09 +- __u8 family; +- __u8 pad06[2]; +- __u64 ram_size; +- __u64 ram_user; +-}; +- +- +-/******************************************************************************* +- * context dma +- ******************************************************************************/ +- +-struct nv_dma_v0 { +- __u8 version; +-#define NV_DMA_V0_TARGET_VM 0x00 +-#define NV_DMA_V0_TARGET_VRAM 0x01 +-#define NV_DMA_V0_TARGET_PCI 0x02 +-#define NV_DMA_V0_TARGET_PCI_US 0x03 +-#define NV_DMA_V0_TARGET_AGP 0x04 +- __u8 target; +-#define NV_DMA_V0_ACCESS_VM 0x00 +-#define NV_DMA_V0_ACCESS_RD 0x01 +-#define NV_DMA_V0_ACCESS_WR 0x02 +-#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR) +- __u8 access; +- __u8 pad03[5]; +- __u64 start; +- __u64 limit; +- /* ... chipset-specific class data */ +-}; +- +-struct nv50_dma_v0 { +- __u8 version; +-#define NV50_DMA_V0_PRIV_VM 0x00 +-#define NV50_DMA_V0_PRIV_US 0x01 +-#define NV50_DMA_V0_PRIV__S 0x02 +- __u8 priv; +-#define NV50_DMA_V0_PART_VM 0x00 +-#define NV50_DMA_V0_PART_256 0x01 +-#define NV50_DMA_V0_PART_1KB 0x02 +- __u8 part; +-#define NV50_DMA_V0_COMP_NONE 0x00 +-#define NV50_DMA_V0_COMP_1 0x01 +-#define NV50_DMA_V0_COMP_2 0x02 +-#define NV50_DMA_V0_COMP_VM 0x03 +- __u8 comp; +-#define NV50_DMA_V0_KIND_PITCH 0x00 +-#define NV50_DMA_V0_KIND_VM 0x7f +- __u8 kind; +- __u8 pad05[3]; +-}; +- +-struct gf100_dma_v0 { +- __u8 version; +-#define GF100_DMA_V0_PRIV_VM 0x00 +-#define GF100_DMA_V0_PRIV_US 0x01 +-#define GF100_DMA_V0_PRIV__S 0x02 +- __u8 priv; +-#define GF100_DMA_V0_KIND_PITCH 0x00 +-#define GF100_DMA_V0_KIND_VM 0xff +- __u8 kind; +- __u8 pad03[5]; +-}; +- +-struct gf110_dma_v0 { +- __u8 version; +-#define GF110_DMA_V0_PAGE_LP 0x00 +-#define GF110_DMA_V0_PAGE_SP 0x01 +- __u8 page; +-#define GF110_DMA_V0_KIND_PITCH 0x00 +-#define GF110_DMA_V0_KIND_VM 0xff +- __u8 kind; +- __u8 pad03[5]; +-}; +- +- +-/******************************************************************************* +- * perfmon +- ******************************************************************************/ +- +-struct nvif_perfctr_v0 { +- __u8 version; +- __u8 pad01[1]; +- __u16 logic_op; +- __u8 pad04[4]; +- char name[4][64]; +-}; +- +-#define NVIF_PERFCTR_V0_QUERY 0x00 +-#define NVIF_PERFCTR_V0_SAMPLE 0x01 +-#define NVIF_PERFCTR_V0_READ 0x02 +- +-struct nvif_perfctr_query_v0 { +- __u8 version; +- __u8 pad01[3]; +- __u32 iter; +- char name[64]; +-}; +- +-struct nvif_perfctr_sample { +-}; +- +-struct nvif_perfctr_read_v0 { +- __u8 version; +- __u8 pad01[7]; +- __u32 ctr; +- __u32 clk; +-}; +- +- +-/******************************************************************************* +- * device control +- ******************************************************************************/ +- +-#define NVIF_CONTROL_PSTATE_INFO 0x00 +-#define NVIF_CONTROL_PSTATE_ATTR 0x01 +-#define NVIF_CONTROL_PSTATE_USER 0x02 +- +-struct nvif_control_pstate_info_v0 { +- __u8 version; +- __u8 count; /* out: number of power states */ +-#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1) +-#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2) +- __s8 ustate_ac; /* out: target pstate index */ +- __s8 ustate_dc; /* out: target pstate index */ +- __s8 pwrsrc; /* out: current power source */ +-#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1) +-#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2) +- __s8 pstate; /* out: current pstate index */ +- __u8 pad06[2]; +-}; +- +-struct nvif_control_pstate_attr_v0 { +- __u8 version; +-#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1) +- __s8 state; /* in: index of pstate to query +- * out: pstate identifier +- */ +- __u8 index; /* in: index of attribute to query +- * out: index of next attribute, or 0 if no more +- */ +- __u8 pad03[5]; +- __u32 min; +- __u32 max; +- char name[32]; +- char unit[16]; +-}; +- +-struct nvif_control_pstate_user_v0 { +- __u8 version; +-#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1) +-#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2) +- __s8 ustate; /* in: pstate identifier */ +- __s8 pwrsrc; /* in: target power source */ +- __u8 pad03[5]; +-}; +- +- +-/******************************************************************************* +- * DMA FIFO channels +- ******************************************************************************/ +- +-struct nv03_channel_dma_v0 { +- __u8 version; +- __u8 chid; +- __u8 pad02[2]; +- __u32 pushbuf; +- __u64 offset; +-}; +- +-#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +- +-/******************************************************************************* +- * GPFIFO channels +- ******************************************************************************/ +- +-struct nv50_channel_gpfifo_v0 { +- __u8 version; +- __u8 chid; +- __u8 pad01[6]; +- __u32 pushbuf; +- __u32 ilength; +- __u64 ioffset; +-}; +- +-struct kepler_channel_gpfifo_a_v0 { +- __u8 version; +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02 +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04 +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08 +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 +-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 +- __u8 engine; +- __u16 chid; +- __u8 pad04[4]; +- __u32 pushbuf; +- __u32 ilength; +- __u64 ioffset; +-}; +- +-/******************************************************************************* +- * legacy display +- ******************************************************************************/ +- +-#define NV04_DISP_NTFY_VBLANK 0x00 +-#define NV04_DISP_NTFY_CONN 0x01 +- +-struct nv04_disp_mthd_v0 { +- __u8 version; +-#define NV04_DISP_SCANOUTPOS 0x00 +- __u8 method; +- __u8 head; +- __u8 pad03[5]; +-}; +- +-struct nv04_disp_scanoutpos_v0 { +- __u8 version; +- __u8 pad01[7]; +- __s64 time[2]; +- __u16 vblanks; +- __u16 vblanke; +- __u16 vtotal; +- __u16 vline; +- __u16 hblanks; +- __u16 hblanke; +- __u16 htotal; +- __u16 hline; +-}; +- +-/******************************************************************************* +- * display +- ******************************************************************************/ +- +-#define NV50_DISP_MTHD 0x00 +- +-struct nv50_disp_mthd_v0 { +- __u8 version; +-#define NV50_DISP_SCANOUTPOS 0x00 +- __u8 method; +- __u8 head; +- __u8 pad03[5]; +-}; +- +-struct nv50_disp_mthd_v1 { +- __u8 version; +-#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 +-#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 +-#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 +-#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 +-#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 +-#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 +-#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 +-#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 +- __u8 method; +- __u16 hasht; +- __u16 hashm; +- __u8 pad06[2]; +-}; +- +-struct nv50_disp_dac_pwr_v0 { +- __u8 version; +- __u8 state; +- __u8 data; +- __u8 vsync; +- __u8 hsync; +- __u8 pad05[3]; +-}; +- +-struct nv50_disp_dac_load_v0 { +- __u8 version; +- __u8 load; +- __u8 pad02[2]; +- __u32 data; +-}; +- +-struct nv50_disp_sor_pwr_v0 { +- __u8 version; +- __u8 state; +- __u8 pad02[6]; +-}; +- +-struct nv50_disp_sor_hda_eld_v0 { +- __u8 version; +- __u8 pad01[7]; +- __u8 data[]; +-}; +- +-struct nv50_disp_sor_hdmi_pwr_v0 { +- __u8 version; +- __u8 state; +- __u8 max_ac_packet; +- __u8 rekey; +- __u8 pad04[4]; +-}; +- +-struct nv50_disp_sor_lvds_script_v0 { +- __u8 version; +- __u8 pad01[1]; +- __u16 script; +- __u8 pad04[4]; +-}; +- +-struct nv50_disp_sor_dp_pwr_v0 { +- __u8 version; +- __u8 state; +- __u8 pad02[6]; +-}; +- +-struct nv50_disp_pior_pwr_v0 { +- __u8 version; +- __u8 state; +- __u8 type; +- __u8 pad03[5]; +-}; +- +-/* core */ +-struct nv50_disp_core_channel_dma_v0 { +- __u8 version; +- __u8 pad01[3]; +- __u32 pushbuf; +-}; +- +-#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +- +-/* cursor immediate */ +-struct nv50_disp_cursor_v0 { +- __u8 version; +- __u8 head; +- __u8 pad02[6]; +-}; +- +-#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00 +- +-/* base */ +-struct nv50_disp_base_channel_dma_v0 { +- __u8 version; +- __u8 pad01[2]; +- __u8 head; +- __u32 pushbuf; +-}; +- +-#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +- +-/* overlay */ +-struct nv50_disp_overlay_channel_dma_v0 { +- __u8 version; +- __u8 pad01[2]; +- __u8 head; +- __u32 pushbuf; +-}; +- +-#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00 +- +-/* overlay immediate */ +-struct nv50_disp_overlay_v0 { +- __u8 version; +- __u8 head; +- __u8 pad02[6]; +-}; +- +-#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00 +- +-/******************************************************************************* +- * fermi +- ******************************************************************************/ +- +-#define FERMI_A_ZBC_COLOR 0x00 +-#define FERMI_A_ZBC_DEPTH 0x01 +- +-struct fermi_a_zbc_color_v0 { +- __u8 version; +-#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01 +-#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02 +-#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04 +-#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08 +-#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c +-#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10 +-#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14 +-#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16 +-#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18 +-#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c +-#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20 +-#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24 +-#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28 +-#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c +-#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30 +-#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34 +-#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38 +-#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c +-#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40 +- __u8 format; +- __u8 index; +- __u8 pad03[5]; +- __u32 ds[4]; +- __u32 l2[4]; +-}; +- +-struct fermi_a_zbc_depth_v0 { +- __u8 version; +-#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01 +- __u8 format; +- __u8 index; +- __u8 pad03[5]; +- __u32 ds; +- __u32 l2; +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/client.c b/drivers/gpu/drm/nouveau/nvif/client.c +deleted file mode 100644 +index 3c4df1fc..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/client.c ++++ /dev/null +@@ -1,129 +0,0 @@ +-/* +- * Copyright 2013 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "client.h" +-#include "driver.h" +-#include "ioctl.h" +- +-int +-nvif_client_ioctl(struct nvif_client *client, void *data, u32 size) +-{ +- return client->driver->ioctl(client->base.priv, client->super, data, size, NULL); +-} +- +-int +-nvif_client_suspend(struct nvif_client *client) +-{ +- return client->driver->suspend(client->base.priv); +-} +- +-int +-nvif_client_resume(struct nvif_client *client) +-{ +- return client->driver->resume(client->base.priv); +-} +- +-void +-nvif_client_fini(struct nvif_client *client) +-{ +- if (client->driver) { +- client->driver->fini(client->base.priv); +- client->driver = NULL; +- client->base.parent = NULL; +- nvif_object_fini(&client->base); +- } +-} +- +-const struct nvif_driver * +-nvif_drivers[] = { +-#ifdef __KERNEL__ +- &nvif_driver_nvkm, +-#else +- &nvif_driver_drm, +- &nvif_driver_lib, +-#endif +- NULL +-}; +- +-int +-nvif_client_init(void (*dtor)(struct nvif_client *), const char *driver, +- const char *name, u64 device, const char *cfg, const char *dbg, +- struct nvif_client *client) +-{ +- int ret, i; +- +- ret = nvif_object_init(NULL, (void*)dtor, 0, 0, NULL, 0, &client->base); +- if (ret) +- return ret; +- +- client->base.parent = &client->base; +- client->base.handle = ~0; +- client->object = &client->base; +- client->super = true; +- +- for (i = 0, ret = -EINVAL; (client->driver = nvif_drivers[i]); i++) { +- if (!driver || !strcmp(client->driver->name, driver)) { +- ret = client->driver->init(name, device, cfg, dbg, +- &client->base.priv); +- if (!ret || driver) +- break; +- } +- } +- +- if (ret) +- nvif_client_fini(client); +- return ret; +-} +- +-static void +-nvif_client_del(struct nvif_client *client) +-{ +- nvif_client_fini(client); +- kfree(client); +-} +- +-int +-nvif_client_new(const char *driver, const char *name, u64 device, +- const char *cfg, const char *dbg, +- struct nvif_client **pclient) +-{ +- struct nvif_client *client = kzalloc(sizeof(*client), GFP_KERNEL); +- if (client) { +- int ret = nvif_client_init(nvif_client_del, driver, name, +- device, cfg, dbg, client); +- if (ret) { +- kfree(client); +- client = NULL; +- } +- *pclient = client; +- return ret; +- } +- return -ENOMEM; +-} +- +-void +-nvif_client_ref(struct nvif_client *client, struct nvif_client **pclient) +-{ +- nvif_object_ref(&client->base, (struct nvif_object **)pclient); +-} +diff --git a/drivers/gpu/drm/nouveau/nvif/client.h b/drivers/gpu/drm/nouveau/nvif/client.h +deleted file mode 100644 +index 28352f08..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/client.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-#ifndef __NVIF_CLIENT_H__ +-#define __NVIF_CLIENT_H__ +- +-#include "object.h" +- +-struct nvif_client { +- struct nvif_object base; +- struct nvif_object *object; /*XXX: hack for nvif_object() */ +- const struct nvif_driver *driver; +- bool super; +-}; +- +-static inline struct nvif_client * +-nvif_client(struct nvif_object *object) +-{ +- while (object && object->parent != object) +- object = object->parent; +- return (void *)object; +-} +- +-int nvif_client_init(void (*dtor)(struct nvif_client *), const char *, +- const char *, u64, const char *, const char *, +- struct nvif_client *); +-void nvif_client_fini(struct nvif_client *); +-int nvif_client_new(const char *, const char *, u64, const char *, +- const char *, struct nvif_client **); +-void nvif_client_ref(struct nvif_client *, struct nvif_client **); +-int nvif_client_ioctl(struct nvif_client *, void *, u32); +-int nvif_client_suspend(struct nvif_client *); +-int nvif_client_resume(struct nvif_client *); +- +-/*XXX*/ +-#include +-#define nvkm_client(a) ({ \ +- struct nvif_client *_client = nvif_client(nvif_object(a)); \ +- nouveau_client(_client->base.priv); \ +-}) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/device.c b/drivers/gpu/drm/nouveau/nvif/device.c +deleted file mode 100644 +index f4775797..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/device.c ++++ /dev/null +@@ -1,78 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "device.h" +- +-void +-nvif_device_fini(struct nvif_device *device) +-{ +- nvif_object_fini(&device->base); +-} +- +-int +-nvif_device_init(struct nvif_object *parent, void (*dtor)(struct nvif_device *), +- u32 handle, u32 oclass, void *data, u32 size, +- struct nvif_device *device) +-{ +- int ret = nvif_object_init(parent, (void *)dtor, handle, oclass, +- data, size, &device->base); +- if (ret == 0) { +- device->object = &device->base; +- device->info.version = 0; +- ret = nvif_object_mthd(&device->base, NV_DEVICE_V0_INFO, +- &device->info, sizeof(device->info)); +- } +- return ret; +-} +- +-static void +-nvif_device_del(struct nvif_device *device) +-{ +- nvif_device_fini(device); +- kfree(device); +-} +- +-int +-nvif_device_new(struct nvif_object *parent, u32 handle, u32 oclass, +- void *data, u32 size, struct nvif_device **pdevice) +-{ +- struct nvif_device *device = kzalloc(sizeof(*device), GFP_KERNEL); +- if (device) { +- int ret = nvif_device_init(parent, nvif_device_del, handle, +- oclass, data, size, device); +- if (ret) { +- kfree(device); +- device = NULL; +- } +- *pdevice = device; +- return ret; +- } +- return -ENOMEM; +-} +- +-void +-nvif_device_ref(struct nvif_device *device, struct nvif_device **pdevice) +-{ +- nvif_object_ref(&device->base, (struct nvif_object **)pdevice); +-} +diff --git a/drivers/gpu/drm/nouveau/nvif/device.h b/drivers/gpu/drm/nouveau/nvif/device.h +deleted file mode 100644 +index 43180f9f..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/device.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-#ifndef __NVIF_DEVICE_H__ +-#define __NVIF_DEVICE_H__ +- +-#include "object.h" +-#include "class.h" +- +-struct nvif_device { +- struct nvif_object base; +- struct nvif_object *object; /*XXX: hack for nvif_object() */ +- struct nv_device_info_v0 info; +-}; +- +-static inline struct nvif_device * +-nvif_device(struct nvif_object *object) +-{ +- while (object && object->oclass != 0x0080 /*XXX: NV_DEVICE_CLASS*/ ) +- object = object->parent; +- return (void *)object; +-} +- +-int nvif_device_init(struct nvif_object *, void (*dtor)(struct nvif_device *), +- u32 handle, u32 oclass, void *, u32, +- struct nvif_device *); +-void nvif_device_fini(struct nvif_device *); +-int nvif_device_new(struct nvif_object *, u32 handle, u32 oclass, +- void *, u32, struct nvif_device **); +-void nvif_device_ref(struct nvif_device *, struct nvif_device **); +- +-/*XXX*/ +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#define nvkm_device(a) nv_device(nvkm_object((a))) +-#define nvkm_bios(a) nouveau_bios(nvkm_device(a)) +-#define nvkm_fb(a) nouveau_fb(nvkm_device(a)) +-#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a)) +-#define nvkm_bar(a) nouveau_bar(nvkm_device(a)) +-#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a)) +-#define nvkm_clock(a) nouveau_clock(nvkm_device(a)) +-#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a)) +-#define nvkm_timer(a) nouveau_timer(nvkm_device(a)) +-#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d)) +-#define nvkm_wait_cb(a,b,c) nv_wait_cb(nvkm_timer(a), (b), (c)) +-#define nvkm_therm(a) nouveau_therm(nvkm_device(a)) +- +-#include +-#include +-#include +-#include +- +-#define nvkm_fifo(a) nouveau_fifo(nvkm_device(a)) +-#define nvkm_fifo_chan(a) ((struct nouveau_fifo_chan *)nvkm_object(a)) +-#define nvkm_gr(a) ((struct nouveau_graph *)nouveau_engine(nvkm_object(a), NVDEV_ENGINE_GR)) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/driver.h b/drivers/gpu/drm/nouveau/nvif/driver.h +deleted file mode 100644 +index ac4bdb3e..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/driver.h ++++ /dev/null +@@ -1,21 +0,0 @@ +-#ifndef __NVIF_DRIVER_H__ +-#define __NVIF_DRIVER_H__ +- +-struct nvif_driver { +- const char *name; +- int (*init)(const char *name, u64 device, const char *cfg, +- const char *dbg, void **priv); +- void (*fini)(void *priv); +- int (*suspend)(void *priv); +- int (*resume)(void *priv); +- int (*ioctl)(void *priv, bool super, void *data, u32 size, void **hack); +- void __iomem *(*map)(void *priv, u64 handle, u32 size); +- void (*unmap)(void *priv, void __iomem *ptr, u32 size); +- bool keep; +-}; +- +-extern const struct nvif_driver nvif_driver_nvkm; +-extern const struct nvif_driver nvif_driver_drm; +-extern const struct nvif_driver nvif_driver_lib; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/event.h b/drivers/gpu/drm/nouveau/nvif/event.h +deleted file mode 100644 +index 21764499..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/event.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-#ifndef __NVIF_EVENT_H__ +-#define __NVIF_EVENT_H__ +- +-struct nvif_notify_req_v0 { +- __u8 version; +- __u8 reply; +- __u8 pad02[5]; +-#define NVIF_NOTIFY_V0_ROUTE_NVIF 0x00 +- __u8 route; +- __u64 token; /* must be unique */ +- __u8 data[]; /* request data (below) */ +-}; +- +-struct nvif_notify_rep_v0 { +- __u8 version; +- __u8 pad01[6]; +- __u8 route; +- __u64 token; +- __u8 data[]; /* reply data (below) */ +-}; +- +-struct nvif_notify_head_req_v0 { +- /* nvif_notify_req ... */ +- __u8 version; +- __u8 head; +- __u8 pad02[6]; +-}; +- +-struct nvif_notify_head_rep_v0 { +- /* nvif_notify_rep ... */ +- __u8 version; +- __u8 pad01[7]; +-}; +- +-struct nvif_notify_conn_req_v0 { +- /* nvif_notify_req ... */ +- __u8 version; +-#define NVIF_NOTIFY_CONN_V0_PLUG 0x01 +-#define NVIF_NOTIFY_CONN_V0_UNPLUG 0x02 +-#define NVIF_NOTIFY_CONN_V0_IRQ 0x04 +-#define NVIF_NOTIFY_CONN_V0_ANY 0x07 +- __u8 mask; +- __u8 conn; +- __u8 pad03[5]; +-}; +- +-struct nvif_notify_conn_rep_v0 { +- /* nvif_notify_rep ... */ +- __u8 version; +- __u8 mask; +- __u8 pad02[6]; +-}; +- +-struct nvif_notify_uevent_req { +- /* nvif_notify_req ... */ +-}; +- +-struct nvif_notify_uevent_rep { +- /* nvif_notify_rep ... */ +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/ioctl.h b/drivers/gpu/drm/nouveau/nvif/ioctl.h +deleted file mode 100644 +index 4cd8e323..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/ioctl.h ++++ /dev/null +@@ -1,128 +0,0 @@ +-#ifndef __NVIF_IOCTL_H__ +-#define __NVIF_IOCTL_H__ +- +-struct nvif_ioctl_v0 { +- __u8 version; +-#define NVIF_IOCTL_V0_OWNER_NVIF 0x00 +-#define NVIF_IOCTL_V0_OWNER_ANY 0xff +- __u8 owner; +-#define NVIF_IOCTL_V0_NOP 0x00 +-#define NVIF_IOCTL_V0_SCLASS 0x01 +-#define NVIF_IOCTL_V0_NEW 0x02 +-#define NVIF_IOCTL_V0_DEL 0x03 +-#define NVIF_IOCTL_V0_MTHD 0x04 +-#define NVIF_IOCTL_V0_RD 0x05 +-#define NVIF_IOCTL_V0_WR 0x06 +-#define NVIF_IOCTL_V0_MAP 0x07 +-#define NVIF_IOCTL_V0_UNMAP 0x08 +-#define NVIF_IOCTL_V0_NTFY_NEW 0x09 +-#define NVIF_IOCTL_V0_NTFY_DEL 0x0a +-#define NVIF_IOCTL_V0_NTFY_GET 0x0b +-#define NVIF_IOCTL_V0_NTFY_PUT 0x0c +- __u8 type; +- __u8 path_nr; +-#define NVIF_IOCTL_V0_ROUTE_NVIF 0x00 +-#define NVIF_IOCTL_V0_ROUTE_HIDDEN 0xff +- __u8 pad04[3]; +- __u8 route; +- __u64 token; +- __u32 path[8]; /* in reverse */ +- __u8 data[]; /* ioctl data (below) */ +-}; +- +-struct nvif_ioctl_nop { +-}; +- +-struct nvif_ioctl_sclass_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 count; +- __u8 pad02[6]; +- __u32 oclass[]; +-}; +- +-struct nvif_ioctl_new_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 pad01[6]; +- __u8 route; +- __u64 token; +- __u32 handle; +-/* these class numbers are made up by us, and not nvidia-assigned */ +-#define NVIF_IOCTL_NEW_V0_PERFCTR 0x0000ffff +-#define NVIF_IOCTL_NEW_V0_CONTROL 0x0000fffe +- __u32 oclass; +- __u8 data[]; /* class data (class.h) */ +-}; +- +-struct nvif_ioctl_del { +-}; +- +-struct nvif_ioctl_rd_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 size; +- __u8 pad02[2]; +- __u32 data; +- __u64 addr; +-}; +- +-struct nvif_ioctl_wr_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 size; +- __u8 pad02[2]; +- __u32 data; +- __u64 addr; +-}; +- +-struct nvif_ioctl_map_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 pad01[3]; +- __u32 length; +- __u64 handle; +-}; +- +-struct nvif_ioctl_unmap { +-}; +- +-struct nvif_ioctl_ntfy_new_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 event; +- __u8 index; +- __u8 pad03[5]; +- __u8 data[]; /* event request data (event.h) */ +-}; +- +-struct nvif_ioctl_ntfy_del_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 index; +- __u8 pad02[6]; +-}; +- +-struct nvif_ioctl_ntfy_get_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 index; +- __u8 pad02[6]; +-}; +- +-struct nvif_ioctl_ntfy_put_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 index; +- __u8 pad02[6]; +-}; +- +-struct nvif_ioctl_mthd_v0 { +- /* nvif_ioctl ... */ +- __u8 version; +- __u8 method; +- __u8 pad02[6]; +- __u8 data[]; /* method data (class.h) */ +-}; +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/list.h b/drivers/gpu/drm/nouveau/nvif/list.h +deleted file mode 100644 +index 8af5d144..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/list.h ++++ /dev/null +@@ -1,353 +0,0 @@ +-/* +- * Copyright © 2010 Intel Corporation +- * Copyright © 2010 Francisco Jerez +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice (including the next +- * paragraph) shall be included in all copies or substantial portions of the +- * Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +- * IN THE SOFTWARE. +- * +- */ +- +-/* Modified by Ben Skeggs to match kernel list APIs */ +- +-#ifndef _XORG_LIST_H_ +-#define _XORG_LIST_H_ +- +-/** +- * @file Classic doubly-link circular list implementation. +- * For real usage examples of the linked list, see the file test/list.c +- * +- * Example: +- * We need to keep a list of struct foo in the parent struct bar, i.e. what +- * we want is something like this. +- * +- * struct bar { +- * ... +- * struct foo *list_of_foos; -----> struct foo {}, struct foo {}, struct foo{} +- * ... +- * } +- * +- * We need one list head in bar and a list element in all list_of_foos (both are of +- * data type 'struct list_head'). +- * +- * struct bar { +- * ... +- * struct list_head list_of_foos; +- * ... +- * } +- * +- * struct foo { +- * ... +- * struct list_head entry; +- * ... +- * } +- * +- * Now we initialize the list head: +- * +- * struct bar bar; +- * ... +- * INIT_LIST_HEAD(&bar.list_of_foos); +- * +- * Then we create the first element and add it to this list: +- * +- * struct foo *foo = malloc(...); +- * .... +- * list_add(&foo->entry, &bar.list_of_foos); +- * +- * Repeat the above for each element you want to add to the list. Deleting +- * works with the element itself. +- * list_del(&foo->entry); +- * free(foo); +- * +- * Note: calling list_del(&bar.list_of_foos) will set bar.list_of_foos to an empty +- * list again. +- * +- * Looping through the list requires a 'struct foo' as iterator and the +- * name of the field the subnodes use. +- * +- * struct foo *iterator; +- * list_for_each_entry(iterator, &bar.list_of_foos, entry) { +- * if (iterator->something == ...) +- * ... +- * } +- * +- * Note: You must not call list_del() on the iterator if you continue the +- * loop. You need to run the safe for-each loop instead: +- * +- * struct foo *iterator, *next; +- * list_for_each_entry_safe(iterator, next, &bar.list_of_foos, entry) { +- * if (...) +- * list_del(&iterator->entry); +- * } +- * +- */ +- +-/** +- * The linkage struct for list nodes. This struct must be part of your +- * to-be-linked struct. struct list_head is required for both the head of the +- * list and for each list node. +- * +- * Position and name of the struct list_head field is irrelevant. +- * There are no requirements that elements of a list are of the same type. +- * There are no requirements for a list head, any struct list_head can be a list +- * head. +- */ +-struct list_head { +- struct list_head *next, *prev; +-}; +- +-/** +- * Initialize the list as an empty list. +- * +- * Example: +- * INIT_LIST_HEAD(&bar->list_of_foos); +- * +- * @param The list to initialized. +- */ +-#define LIST_HEAD_INIT(name) { &(name), &(name) } +- +-#define LIST_HEAD(name) \ +- struct list_head name = LIST_HEAD_INIT(name) +- +-static inline void +-INIT_LIST_HEAD(struct list_head *list) +-{ +- list->next = list->prev = list; +-} +- +-static inline void +-__list_add(struct list_head *entry, +- struct list_head *prev, struct list_head *next) +-{ +- next->prev = entry; +- entry->next = next; +- entry->prev = prev; +- prev->next = entry; +-} +- +-/** +- * Insert a new element after the given list head. The new element does not +- * need to be initialised as empty list. +- * The list changes from: +- * head → some element → ... +- * to +- * head → new element → older element → ... +- * +- * Example: +- * struct foo *newfoo = malloc(...); +- * list_add(&newfoo->entry, &bar->list_of_foos); +- * +- * @param entry The new element to prepend to the list. +- * @param head The existing list. +- */ +-static inline void +-list_add(struct list_head *entry, struct list_head *head) +-{ +- __list_add(entry, head, head->next); +-} +- +-/** +- * Append a new element to the end of the list given with this list head. +- * +- * The list changes from: +- * head → some element → ... → lastelement +- * to +- * head → some element → ... → lastelement → new element +- * +- * Example: +- * struct foo *newfoo = malloc(...); +- * list_add_tail(&newfoo->entry, &bar->list_of_foos); +- * +- * @param entry The new element to prepend to the list. +- * @param head The existing list. +- */ +-static inline void +-list_add_tail(struct list_head *entry, struct list_head *head) +-{ +- __list_add(entry, head->prev, head); +-} +- +-static inline void +-__list_del(struct list_head *prev, struct list_head *next) +-{ +- next->prev = prev; +- prev->next = next; +-} +- +-/** +- * Remove the element from the list it is in. Using this function will reset +- * the pointers to/from this element so it is removed from the list. It does +- * NOT free the element itself or manipulate it otherwise. +- * +- * Using list_del on a pure list head (like in the example at the top of +- * this file) will NOT remove the first element from +- * the list but rather reset the list as empty list. +- * +- * Example: +- * list_del(&foo->entry); +- * +- * @param entry The element to remove. +- */ +-static inline void +-list_del(struct list_head *entry) +-{ +- __list_del(entry->prev, entry->next); +-} +- +-static inline void +-list_del_init(struct list_head *entry) +-{ +- __list_del(entry->prev, entry->next); +- INIT_LIST_HEAD(entry); +-} +- +-static inline void list_move_tail(struct list_head *list, +- struct list_head *head) +-{ +- __list_del(list->prev, list->next); +- list_add_tail(list, head); +-} +- +-/** +- * Check if the list is empty. +- * +- * Example: +- * list_empty(&bar->list_of_foos); +- * +- * @return True if the list contains one or more elements or False otherwise. +- */ +-static inline bool +-list_empty(struct list_head *head) +-{ +- return head->next == head; +-} +- +-/** +- * Returns a pointer to the container of this list element. +- * +- * Example: +- * struct foo* f; +- * f = container_of(&foo->entry, struct foo, entry); +- * assert(f == foo); +- * +- * @param ptr Pointer to the struct list_head. +- * @param type Data type of the list element. +- * @param member Member name of the struct list_head field in the list element. +- * @return A pointer to the data struct containing the list head. +- */ +-#ifndef container_of +-#define container_of(ptr, type, member) \ +- (type *)((char *)(ptr) - (char *) &((type *)0)->member) +-#endif +- +-/** +- * Alias of container_of +- */ +-#define list_entry(ptr, type, member) \ +- container_of(ptr, type, member) +- +-/** +- * Retrieve the first list entry for the given list pointer. +- * +- * Example: +- * struct foo *first; +- * first = list_first_entry(&bar->list_of_foos, struct foo, list_of_foos); +- * +- * @param ptr The list head +- * @param type Data type of the list element to retrieve +- * @param member Member name of the struct list_head field in the list element. +- * @return A pointer to the first list element. +- */ +-#define list_first_entry(ptr, type, member) \ +- list_entry((ptr)->next, type, member) +- +-/** +- * Retrieve the last list entry for the given listpointer. +- * +- * Example: +- * struct foo *first; +- * first = list_last_entry(&bar->list_of_foos, struct foo, list_of_foos); +- * +- * @param ptr The list head +- * @param type Data type of the list element to retrieve +- * @param member Member name of the struct list_head field in the list element. +- * @return A pointer to the last list element. +- */ +-#define list_last_entry(ptr, type, member) \ +- list_entry((ptr)->prev, type, member) +- +-#define __container_of(ptr, sample, member) \ +- (void *)container_of((ptr), typeof(*(sample)), member) +- +-/** +- * Loop through the list given by head and set pos to struct in the list. +- * +- * Example: +- * struct foo *iterator; +- * list_for_each_entry(iterator, &bar->list_of_foos, entry) { +- * [modify iterator] +- * } +- * +- * This macro is not safe for node deletion. Use list_for_each_entry_safe +- * instead. +- * +- * @param pos Iterator variable of the type of the list elements. +- * @param head List head +- * @param member Member name of the struct list_head in the list elements. +- * +- */ +-#define list_for_each_entry(pos, head, member) \ +- for (pos = __container_of((head)->next, pos, member); \ +- &pos->member != (head); \ +- pos = __container_of(pos->member.next, pos, member)) +- +-/** +- * Loop through the list, keeping a backup pointer to the element. This +- * macro allows for the deletion of a list element while looping through the +- * list. +- * +- * See list_for_each_entry for more details. +- */ +-#define list_for_each_entry_safe(pos, tmp, head, member) \ +- for (pos = __container_of((head)->next, pos, member), \ +- tmp = __container_of(pos->member.next, pos, member); \ +- &pos->member != (head); \ +- pos = tmp, tmp = __container_of(pos->member.next, tmp, member)) +- +- +-#define list_for_each_entry_reverse(pos, head, member) \ +- for (pos = __container_of((head)->prev, pos, member); \ +- &pos->member != (head); \ +- pos = __container_of(pos->member.prev, pos, member)) +- +-#define list_for_each_entry_continue(pos, head, member) \ +- for (pos = __container_of(pos->member.next, pos, member); \ +- &pos->member != (head); \ +- pos = __container_of(pos->member.next, pos, member)) +- +-#define list_for_each_entry_continue_reverse(pos, head, member) \ +- for (pos = __container_of(pos->member.prev, pos, member); \ +- &pos->member != (head); \ +- pos = __container_of(pos->member.prev, pos, member)) +- +-#define list_for_each_entry_from(pos, head, member) \ +- for (; \ +- &pos->member != (head); \ +- pos = __container_of(pos->member.next, pos, member)) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/notify.c b/drivers/gpu/drm/nouveau/nvif/notify.c +deleted file mode 100644 +index 0898c315..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/notify.c ++++ /dev/null +@@ -1,248 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include +-#include +-#include +-#include +-#include +-#include +- +-static inline int +-nvif_notify_put_(struct nvif_notify *notify) +-{ +- struct nvif_object *object = notify->object; +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_ntfy_put_v0 ntfy; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_NTFY_PUT, +- .ntfy.index = notify->index, +- }; +- +- if (atomic_inc_return(¬ify->putcnt) != 1) +- return 0; +- +- return nvif_object_ioctl(object, &args, sizeof(args), NULL); +-} +- +-int +-nvif_notify_put(struct nvif_notify *notify) +-{ +- if (likely(notify->object) && +- test_and_clear_bit(NVIF_NOTIFY_USER, ¬ify->flags)) { +- int ret = nvif_notify_put_(notify); +- if (test_bit(NVIF_NOTIFY_WORK, ¬ify->flags)) +- flush_work(¬ify->work); +- return ret; +- } +- return 0; +-} +- +-static inline int +-nvif_notify_get_(struct nvif_notify *notify) +-{ +- struct nvif_object *object = notify->object; +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_ntfy_get_v0 ntfy; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_NTFY_GET, +- .ntfy.index = notify->index, +- }; +- +- if (atomic_dec_return(¬ify->putcnt) != 0) +- return 0; +- +- return nvif_object_ioctl(object, &args, sizeof(args), NULL); +-} +- +-int +-nvif_notify_get(struct nvif_notify *notify) +-{ +- if (likely(notify->object) && +- !test_and_set_bit(NVIF_NOTIFY_USER, ¬ify->flags)) +- return nvif_notify_get_(notify); +- return 0; +-} +- +-static inline int +-nvif_notify_func(struct nvif_notify *notify, bool keep) +-{ +- int ret = notify->func(notify); +- if (ret == NVIF_NOTIFY_KEEP || +- !test_and_clear_bit(NVKM_NOTIFY_USER, ¬ify->flags)) { +- if (!keep) +- atomic_dec(¬ify->putcnt); +- else +- nvif_notify_get_(notify); +- } +- return ret; +-} +- +-static void +-nvif_notify_work(struct work_struct *work) +-{ +- struct nvif_notify *notify = container_of(work, typeof(*notify), work); +- nvif_notify_func(notify, true); +-} +- +-int +-nvif_notify(const void *header, u32 length, const void *data, u32 size) +-{ +- struct nvif_notify *notify = NULL; +- const union { +- struct nvif_notify_rep_v0 v0; +- } *args = header; +- int ret = NVIF_NOTIFY_DROP; +- +- if (length == sizeof(args->v0) && args->v0.version == 0) { +- if (WARN_ON(args->v0.route)) +- return NVIF_NOTIFY_DROP; +- notify = (void *)(unsigned long)args->v0.token; +- } +- +- if (!WARN_ON(notify == NULL)) { +- struct nvif_client *client = nvif_client(notify->object); +- if (!WARN_ON(notify->size != size)) { +- atomic_inc(¬ify->putcnt); +- if (test_bit(NVIF_NOTIFY_WORK, ¬ify->flags)) { +- memcpy((void *)notify->data, data, size); +- schedule_work(¬ify->work); +- return NVIF_NOTIFY_DROP; +- } +- notify->data = data; +- ret = nvif_notify_func(notify, client->driver->keep); +- notify->data = NULL; +- } +- } +- +- return ret; +-} +- +-int +-nvif_notify_fini(struct nvif_notify *notify) +-{ +- struct nvif_object *object = notify->object; +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_ntfy_del_v0 ntfy; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_NTFY_DEL, +- .ntfy.index = notify->index, +- }; +- int ret = nvif_notify_put(notify); +- if (ret >= 0 && object) { +- ret = nvif_object_ioctl(object, &args, sizeof(args), NULL); +- if (ret == 0) { +- nvif_object_ref(NULL, ¬ify->object); +- kfree((void *)notify->data); +- } +- } +- return ret; +-} +- +-int +-nvif_notify_init(struct nvif_object *object, void (*dtor)(struct nvif_notify *), +- int (*func)(struct nvif_notify *), bool work, u8 event, +- void *data, u32 size, u32 reply, struct nvif_notify *notify) +-{ +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_ntfy_new_v0 ntfy; +- struct nvif_notify_req_v0 req; +- } *args; +- int ret = -ENOMEM; +- +- notify->object = NULL; +- nvif_object_ref(object, ¬ify->object); +- notify->flags = 0; +- atomic_set(¬ify->putcnt, 1); +- notify->dtor = dtor; +- notify->func = func; +- notify->data = NULL; +- notify->size = reply; +- if (work) { +- INIT_WORK(¬ify->work, nvif_notify_work); +- set_bit(NVIF_NOTIFY_WORK, ¬ify->flags); +- notify->data = kmalloc(notify->size, GFP_KERNEL); +- if (!notify->data) +- goto done; +- } +- +- if (!(args = kmalloc(sizeof(*args) + size, GFP_KERNEL))) +- goto done; +- args->ioctl.version = 0; +- args->ioctl.type = NVIF_IOCTL_V0_NTFY_NEW; +- args->ntfy.version = 0; +- args->ntfy.event = event; +- args->req.version = 0; +- args->req.reply = notify->size; +- args->req.route = 0; +- args->req.token = (unsigned long)(void *)notify; +- +- memcpy(args->req.data, data, size); +- ret = nvif_object_ioctl(object, args, sizeof(*args) + size, NULL); +- notify->index = args->ntfy.index; +- kfree(args); +-done: +- if (ret) +- nvif_notify_fini(notify); +- return ret; +-} +- +-static void +-nvif_notify_del(struct nvif_notify *notify) +-{ +- nvif_notify_fini(notify); +- kfree(notify); +-} +- +-void +-nvif_notify_ref(struct nvif_notify *notify, struct nvif_notify **pnotify) +-{ +- BUG_ON(notify != NULL); +- if (*pnotify) +- (*pnotify)->dtor(*pnotify); +- *pnotify = notify; +-} +- +-int +-nvif_notify_new(struct nvif_object *object, int (*func)(struct nvif_notify *), +- bool work, u8 type, void *data, u32 size, u32 reply, +- struct nvif_notify **pnotify) +-{ +- struct nvif_notify *notify = kzalloc(sizeof(*notify), GFP_KERNEL); +- if (notify) { +- int ret = nvif_notify_init(object, nvif_notify_del, func, work, +- type, data, size, reply, notify); +- if (ret) { +- kfree(notify); +- notify = NULL; +- } +- *pnotify = notify; +- return ret; +- } +- return -ENOMEM; +-} +diff --git a/drivers/gpu/drm/nouveau/nvif/notify.h b/drivers/gpu/drm/nouveau/nvif/notify.h +deleted file mode 100644 +index 9ebfa3b4..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/notify.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-#ifndef __NVIF_NOTIFY_H__ +-#define __NVIF_NOTIFY_H__ +- +-struct nvif_notify { +- struct nvif_object *object; +- int index; +- +-#define NVIF_NOTIFY_USER 0 +-#define NVIF_NOTIFY_WORK 1 +- unsigned long flags; +- atomic_t putcnt; +- void (*dtor)(struct nvif_notify *); +-#define NVIF_NOTIFY_DROP 0 +-#define NVIF_NOTIFY_KEEP 1 +- int (*func)(struct nvif_notify *); +- +- /* this is const for a *very* good reason - the data might be on the +- * stack from an irq handler. if you're not nvif/notify.c then you +- * should probably think twice before casting it away... +- */ +- const void *data; +- u32 size; +- struct work_struct work; +-}; +- +-int nvif_notify_init(struct nvif_object *, void (*dtor)(struct nvif_notify *), +- int (*func)(struct nvif_notify *), bool work, u8 type, +- void *data, u32 size, u32 reply, struct nvif_notify *); +-int nvif_notify_fini(struct nvif_notify *); +-int nvif_notify_get(struct nvif_notify *); +-int nvif_notify_put(struct nvif_notify *); +-int nvif_notify(const void *, u32, const void *, u32); +- +-int nvif_notify_new(struct nvif_object *, int (*func)(struct nvif_notify *), +- bool work, u8 type, void *data, u32 size, u32 reply, +- struct nvif_notify **); +-void nvif_notify_ref(struct nvif_notify *, struct nvif_notify **); +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/object.c b/drivers/gpu/drm/nouveau/nvif/object.c +deleted file mode 100644 +index dd85b56f..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/object.c ++++ /dev/null +@@ -1,304 +0,0 @@ +-/* +- * Copyright 2014 Red Hat Inc. +- * +- * Permission is hereby granted, free of charge, to any person obtaining a +- * copy of this software and associated documentation files (the "Software"), +- * to deal in the Software without restriction, including without limitation +- * the rights to use, copy, modify, merge, publish, distribute, sublicense, +- * and/or sell copies of the Software, and to permit persons to whom the +- * Software is furnished to do so, subject to the following conditions: +- * +- * The above copyright notice and this permission notice shall be included in +- * all copies or substantial portions of the Software. +- * +- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR +- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +- * OTHER DEALINGS IN THE SOFTWARE. +- * +- * Authors: Ben Skeggs +- */ +- +-#include "object.h" +-#include "client.h" +-#include "driver.h" +-#include "ioctl.h" +- +-int +-nvif_object_ioctl(struct nvif_object *object, void *data, u32 size, void **hack) +-{ +- struct nvif_client *client = nvif_client(object); +- union { +- struct nvif_ioctl_v0 v0; +- } *args = data; +- +- if (size >= sizeof(*args) && args->v0.version == 0) { +- args->v0.owner = NVIF_IOCTL_V0_OWNER_ANY; +- args->v0.path_nr = 0; +- while (args->v0.path_nr < ARRAY_SIZE(args->v0.path)) { +- args->v0.path[args->v0.path_nr++] = object->handle; +- if (object->parent == object) +- break; +- object = object->parent; +- } +- } else +- return -ENOSYS; +- +- return client->driver->ioctl(client->base.priv, client->super, data, size, hack); +-} +- +-int +-nvif_object_sclass(struct nvif_object *object, u32 *oclass, int count) +-{ +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_sclass_v0 sclass; +- } *args; +- u32 size = count * sizeof(args->sclass.oclass[0]); +- int ret; +- +- if (!(args = kmalloc(sizeof(*args) + size, GFP_KERNEL))) +- return -ENOMEM; +- args->ioctl.version = 0; +- args->ioctl.type = NVIF_IOCTL_V0_SCLASS; +- args->sclass.version = 0; +- args->sclass.count = count; +- +- memcpy(args->sclass.oclass, oclass, size); +- ret = nvif_object_ioctl(object, args, sizeof(*args) + size, NULL); +- ret = ret ? ret : args->sclass.count; +- memcpy(oclass, args->sclass.oclass, size); +- kfree(args); +- return ret; +-} +- +-u32 +-nvif_object_rd(struct nvif_object *object, int size, u64 addr) +-{ +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_rd_v0 rd; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_RD, +- .rd.size = size, +- .rd.addr = addr, +- }; +- int ret = nvif_object_ioctl(object, &args, sizeof(args), NULL); +- if (ret) { +- /*XXX: warn? */ +- return 0; +- } +- return args.rd.data; +-} +- +-void +-nvif_object_wr(struct nvif_object *object, int size, u64 addr, u32 data) +-{ +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_wr_v0 wr; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_WR, +- .wr.size = size, +- .wr.addr = addr, +- .wr.data = data, +- }; +- int ret = nvif_object_ioctl(object, &args, sizeof(args), NULL); +- if (ret) { +- /*XXX: warn? */ +- } +-} +- +-int +-nvif_object_mthd(struct nvif_object *object, u32 mthd, void *data, u32 size) +-{ +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_mthd_v0 mthd; +- } *args; +- u8 stack[128]; +- int ret; +- +- if (sizeof(*args) + size > sizeof(stack)) { +- if (!(args = kmalloc(sizeof(*args) + size, GFP_KERNEL))) +- return -ENOMEM; +- } else { +- args = (void *)stack; +- } +- args->ioctl.version = 0; +- args->ioctl.type = NVIF_IOCTL_V0_MTHD; +- args->mthd.version = 0; +- args->mthd.method = mthd; +- +- memcpy(args->mthd.data, data, size); +- ret = nvif_object_ioctl(object, args, sizeof(*args) + size, NULL); +- memcpy(data, args->mthd.data, size); +- if (args != (void *)stack) +- kfree(args); +- return ret; +-} +- +-void +-nvif_object_unmap(struct nvif_object *object) +-{ +- if (object->map.size) { +- struct nvif_client *client = nvif_client(object); +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_unmap unmap; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_UNMAP, +- }; +- +- if (object->map.ptr) { +- client->driver->unmap(client, object->map.ptr, +- object->map.size); +- object->map.ptr = NULL; +- } +- +- nvif_object_ioctl(object, &args, sizeof(args), NULL); +- object->map.size = 0; +- } +-} +- +-int +-nvif_object_map(struct nvif_object *object) +-{ +- struct nvif_client *client = nvif_client(object); +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_map_v0 map; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_MAP, +- }; +- int ret = nvif_object_ioctl(object, &args, sizeof(args), NULL); +- if (ret == 0) { +- object->map.size = args.map.length; +- object->map.ptr = client->driver->map(client, args.map.handle, +- object->map.size); +- if (ret = -ENOMEM, object->map.ptr) +- return 0; +- nvif_object_unmap(object); +- } +- return ret; +-} +- +-struct ctor { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_new_v0 new; +-}; +- +-void +-nvif_object_fini(struct nvif_object *object) +-{ +- struct ctor *ctor = container_of(object->data, typeof(*ctor), new.data); +- if (object->parent) { +- struct { +- struct nvif_ioctl_v0 ioctl; +- struct nvif_ioctl_del del; +- } args = { +- .ioctl.type = NVIF_IOCTL_V0_DEL, +- }; +- +- nvif_object_unmap(object); +- nvif_object_ioctl(object, &args, sizeof(args), NULL); +- if (object->data) { +- object->size = 0; +- object->data = NULL; +- kfree(ctor); +- } +- nvif_object_ref(NULL, &object->parent); +- } +-} +- +-int +-nvif_object_init(struct nvif_object *parent, void (*dtor)(struct nvif_object *), +- u32 handle, u32 oclass, void *data, u32 size, +- struct nvif_object *object) +-{ +- struct ctor *ctor; +- int ret = 0; +- +- object->parent = NULL; +- object->object = object; +- nvif_object_ref(parent, &object->parent); +- kref_init(&object->refcount); +- object->handle = handle; +- object->oclass = oclass; +- object->data = NULL; +- object->size = 0; +- object->dtor = dtor; +- object->map.ptr = NULL; +- object->map.size = 0; +- +- if (object->parent) { +- if (!(ctor = kmalloc(sizeof(*ctor) + size, GFP_KERNEL))) { +- nvif_object_fini(object); +- return -ENOMEM; +- } +- object->data = ctor->new.data; +- object->size = size; +- memcpy(object->data, data, size); +- +- ctor->ioctl.version = 0; +- ctor->ioctl.type = NVIF_IOCTL_V0_NEW; +- ctor->new.version = 0; +- ctor->new.route = NVIF_IOCTL_V0_ROUTE_NVIF; +- ctor->new.token = (unsigned long)(void *)object; +- ctor->new.handle = handle; +- ctor->new.oclass = oclass; +- +- ret = nvif_object_ioctl(parent, ctor, sizeof(*ctor) + +- object->size, &object->priv); +- } +- +- if (ret) +- nvif_object_fini(object); +- return ret; +-} +- +-static void +-nvif_object_del(struct nvif_object *object) +-{ +- nvif_object_fini(object); +- kfree(object); +-} +- +-int +-nvif_object_new(struct nvif_object *parent, u32 handle, u32 oclass, +- void *data, u32 size, struct nvif_object **pobject) +-{ +- struct nvif_object *object = kzalloc(sizeof(*object), GFP_KERNEL); +- if (object) { +- int ret = nvif_object_init(parent, nvif_object_del, handle, +- oclass, data, size, object); +- if (ret) { +- kfree(object); +- object = NULL; +- } +- *pobject = object; +- return ret; +- } +- return -ENOMEM; +-} +- +-static void +-nvif_object_put(struct kref *kref) +-{ +- struct nvif_object *object = +- container_of(kref, typeof(*object), refcount); +- object->dtor(object); +-} +- +-void +-nvif_object_ref(struct nvif_object *object, struct nvif_object **pobject) +-{ +- if (object) +- kref_get(&object->refcount); +- if (*pobject) +- kref_put(&(*pobject)->refcount, nvif_object_put); +- *pobject = object; +-} +diff --git a/drivers/gpu/drm/nouveau/nvif/object.h b/drivers/gpu/drm/nouveau/nvif/object.h +deleted file mode 100644 +index fe519179..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/object.h ++++ /dev/null +@@ -1,75 +0,0 @@ +-#ifndef __NVIF_OBJECT_H__ +-#define __NVIF_OBJECT_H__ +- +-#include +- +-struct nvif_object { +- struct nvif_object *parent; +- struct nvif_object *object; /*XXX: hack for nvif_object() */ +- struct kref refcount; +- u32 handle; +- u32 oclass; +- void *data; +- u32 size; +- void *priv; /*XXX: hack */ +- void (*dtor)(struct nvif_object *); +- struct { +- void __iomem *ptr; +- u32 size; +- } map; +-}; +- +-int nvif_object_init(struct nvif_object *, void (*dtor)(struct nvif_object *), +- u32 handle, u32 oclass, void *, u32, +- struct nvif_object *); +-void nvif_object_fini(struct nvif_object *); +-int nvif_object_new(struct nvif_object *, u32 handle, u32 oclass, +- void *, u32, struct nvif_object **); +-void nvif_object_ref(struct nvif_object *, struct nvif_object **); +-int nvif_object_ioctl(struct nvif_object *, void *, u32, void **); +-int nvif_object_sclass(struct nvif_object *, u32 *, int); +-u32 nvif_object_rd(struct nvif_object *, int, u64); +-void nvif_object_wr(struct nvif_object *, int, u64, u32); +-int nvif_object_mthd(struct nvif_object *, u32, void *, u32); +-int nvif_object_map(struct nvif_object *); +-void nvif_object_unmap(struct nvif_object *); +- +-#define nvif_object(a) (a)->object +- +-#define ioread8_native ioread8 +-#define iowrite8_native iowrite8 +-#define nvif_rd(a,b,c) ({ \ +- struct nvif_object *_object = nvif_object(a); \ +- u32 _data; \ +- if (likely(_object->map.ptr)) \ +- _data = ioread##b##_native((u8 __iomem *)_object->map.ptr + (c)); \ +- else \ +- _data = nvif_object_rd(_object, (b) / 8, (c)); \ +- _data; \ +-}) +-#define nvif_wr(a,b,c,d) ({ \ +- struct nvif_object *_object = nvif_object(a); \ +- if (likely(_object->map.ptr)) \ +- iowrite##b##_native((d), (u8 __iomem *)_object->map.ptr + (c)); \ +- else \ +- nvif_object_wr(_object, (b) / 8, (c), (d)); \ +-}) +-#define nvif_rd08(a,b) ({ u8 _v = nvif_rd((a), 8, (b)); _v; }) +-#define nvif_rd16(a,b) ({ u16 _v = nvif_rd((a), 16, (b)); _v; }) +-#define nvif_rd32(a,b) ({ u32 _v = nvif_rd((a), 32, (b)); _v; }) +-#define nvif_wr08(a,b,c) nvif_wr((a), 8, (b), (u8)(c)) +-#define nvif_wr16(a,b,c) nvif_wr((a), 16, (b), (u16)(c)) +-#define nvif_wr32(a,b,c) nvif_wr((a), 32, (b), (u32)(c)) +-#define nvif_mask(a,b,c,d) ({ \ +- u32 _v = nvif_rd32(nvif_object(a), (b)); \ +- nvif_wr32(nvif_object(a), (b), (_v & ~(c)) | (d)); \ +- _v; \ +-}) +- +-#define nvif_mthd(a,b,c,d) nvif_object_mthd(nvif_object(a), (b), (c), (d)) +- +-/*XXX*/ +-#include +-#define nvkm_object(a) ((struct nouveau_object *)nvif_object(a)->priv) +- +-#endif +diff --git a/drivers/gpu/drm/nouveau/nvif/os.h b/drivers/gpu/drm/nouveau/nvif/os.h +deleted file mode 120000 +index bd744b2c..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/os.h ++++ /dev/null +@@ -1 +0,0 @@ +-../core/os.h +\ No newline at end of file +diff --git a/drivers/gpu/drm/nouveau/nvif/unpack.h b/drivers/gpu/drm/nouveau/nvif/unpack.h +deleted file mode 100644 +index 5933188b..00000000 +--- a/drivers/gpu/drm/nouveau/nvif/unpack.h ++++ /dev/null +@@ -1,24 +0,0 @@ +-#ifndef __NVIF_UNPACK_H__ +-#define __NVIF_UNPACK_H__ +- +-#define nvif_unvers(d) ({ \ +- ret = (size == sizeof(d)) ? 0 : -ENOSYS; \ +- (ret == 0); \ +-}) +- +-#define nvif_unpack(d,vl,vh,m) ({ \ +- if ((vl) == 0 || ret == -ENOSYS) { \ +- int _size = sizeof(d); \ +- if (_size <= size && (d).version >= (vl) && \ +- (d).version <= (vh)) { \ +- data = (u8 *)data + _size; \ +- size = size - _size; \ +- ret = ((m) || !size) ? 0 : -E2BIG; \ +- } else { \ +- ret = -ENOSYS; \ +- } \ +- } \ +- (ret == 0); \ +-}) +- +-#endif +diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c +index 38493ff2..67283b72 100644 +--- a/drivers/irqchip/irq-gic.c ++++ b/drivers/irqchip/irq-gic.c +@@ -93,6 +93,8 @@ struct irq_chip gic_arch_extn = { + .irq_set_wake = NULL, + }; + ++EXPORT_SYMBOL(gic_arch_extn); ++ + #ifndef MAX_GIC_NR + #define MAX_GIC_NR 1 + #endif +@@ -192,9 +194,13 @@ static int gic_set_type(struct irq_data *d, unsigned int type) + /* Interrupt configuration for SGIs can't be changed */ + if (gicirq < 16) + return -EINVAL; +- ++#if !(defined(CONFIG_ARCH_INFINITY) || defined(CONFIG_ARCH_INFINITY3)) + if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) + return -EINVAL; ++#else ++ if (gicirq < 64 && type != IRQ_TYPE_LEVEL_HIGH) ++ return -EINVAL; ++#endif + + raw_spin_lock(&irq_controller_lock); + +@@ -346,9 +352,10 @@ static u8 gic_get_cpumask(struct gic_chip_data *gic) + break; + } + ++#if !(defined(CONFIG_ARCH_INFINITY) || defined(CONFIG_ARCH_INFINITY3)) + if (!mask) + pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); +- ++#endif + return mask; + } + +@@ -1040,6 +1047,7 @@ gic_of_init(struct device_node *node, struct device_node *parent) + gic_cnt++; + return 0; + } ++ + IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); + IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); + IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); +diff --git a/drivers/media/rc/keymaps/rc-mstar-tv.c b/drivers/media/rc/keymaps/rc-mstar-tv.c +new file mode 100644 +index 00000000..a1b91635 +--- /dev/null ++++ b/drivers/media/rc/keymaps/rc-mstar-tv.c +@@ -0,0 +1,115 @@ ++/* mstar-tv.h - Keytable for mstar_tv Remote Controller ++ * ++ * keymap imported from ir-keymaps.c ++ * ++ * Copyright (c) 2010 by Mauro Carvalho Chehab ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#include ++#include ++ ++/* ++ * Jimmy Hsu ++ * this is the remote control that comes with the mstar smart tv ++ * which based on STAOS standard. ++ */ ++static struct rc_map_table mstar_tv[] = { ++ { 0x0046, KEY_POWER }, ++ { 0x0050, KEY_0 }, ++ { 0x0049, KEY_1 }, ++ { 0x0055, KEY_2 }, ++ { 0x0059, KEY_3 }, ++ { 0x004D, KEY_4 }, ++ { 0x0051, KEY_5 }, ++ { 0x005D, KEY_6 }, ++ { 0x0048, KEY_7 }, ++ { 0x0054, KEY_8 }, ++ { 0x0058, KEY_9 }, ++ { 0x0047, KEY_RED }, ++ { 0x004B, KEY_GREEN }, ++ { 0x0057, KEY_YELLOW }, ++ { 0x005B, KEY_BLUE }, ++ { 0x0052, KEY_UP }, ++ { 0x0013, KEY_DOWN }, ++ { 0x0006, KEY_LEFT }, ++ { 0x001A, KEY_RIGHT }, ++ { 0x000F, KEY_ENTER }, ++ { 0x001F, KEY_CHANNELUP }, ++ { 0x0019, KEY_CHANNELDOWN }, ++ { 0x0016, KEY_VOLUMEUP }, ++ { 0x0015, KEY_VOLUMEDOWN }, ++ { 0x0003, KEY_PAGEUP }, ++ { 0x0005, KEY_PAGEDOWN }, ++ { 0x0017, KEY_HOME}, ++ { 0x0007, KEY_MENU }, ++ { 0x001B, KEY_BACK }, ++ { 0x005A, KEY_MUTE }, ++ { 0x000D, KEY_RECORD }, // DVR ++ { 0x0042, KEY_HELP }, // GUIDE ++ { 0x0014, KEY_INFO }, ++ { 0x0040, KEY_KP0 }, // WINDOW ++ { 0x0004, KEY_KP1 }, // TV_INPUT ++ { 0x000E, KEY_REWIND }, ++ { 0x0012, KEY_FORWARD }, ++ { 0x0002, KEY_PREVIOUSSONG }, ++ { 0x001E, KEY_NEXTSONG }, ++ { 0x0001, KEY_PLAY }, ++ { 0x001D, KEY_PAUSE }, ++ { 0x0011, KEY_STOP }, ++ { 0x0044, KEY_AUDIO }, // (C)SOUND_MODE ++ { 0x0056, KEY_CAMERA }, // (C)PICTURE_MODE ++ { 0x004C, KEY_ZOOM }, // (C)ASPECT_RATIO ++ { 0x005C, KEY_CHANNEL }, // (C)CHANNEL_RETURN ++ { 0x0045, KEY_SLEEP }, // (C)SLEEP ++ { 0x004A, KEY_EPG }, // (C)EPG ++ { 0x0010, KEY_LIST }, // (C)LIST ++ { 0x0053, KEY_SUBTITLE }, // (C)SUBTITLE ++ { 0x0041, KEY_FN_F1 }, // (C)MTS ++ { 0x004E, KEY_FN_F2 }, // (C)FREEZE ++ { 0x000A, KEY_FN_F3 }, // (C)TTX ++ { 0x0009, KEY_FN_F4 }, // (C)CC ++ { 0x001C, KEY_FN_F5 }, // (C)TV_SETTING ++ { 0x0008, KEY_FN_F6 }, // (C)SCREENSHOT ++ { 0x000B, KEY_F1 }, // MSTAR_BALANCE ++ { 0x0018, KEY_F2 }, // MSTAR_INDEX ++ { 0x0000, KEY_F3 }, // MSTAR_HOLD ++ { 0x000C, KEY_F4 }, // MSTAR_UPDATE ++ { 0x004F, KEY_F5 }, // MSTAR_REVEAL ++ { 0x005E, KEY_F6 }, // MSTAR_SUBCODE ++ { 0x0043, KEY_F7 }, // MSTAR_SIZE ++ { 0x005F, KEY_F8 }, // MSTAR_CLOCK ++ { 0x00FE, KEY_POWER2 }, // FAKE_POWER ++ { 0x00FF, KEY_OK }, // KEY_OK ++ ++ // 2nd IR controller. ++}; ++ ++static struct rc_map_list mstar_tv_map = { ++ .map = { ++ .scan = mstar_tv, ++ .size = ARRAY_SIZE(mstar_tv), ++ .rc_type = RC_TYPE_UNKNOWN, /* Legacy IR type */ ++ .name = RC_MAP_MSTAR_TV, ++ } ++}; ++ ++static int __init init_rc_map_mstar_tv(void) ++{ ++ return rc_map_register(&mstar_tv_map); ++} ++ ++static void __exit exit_rc_map_mstar_tv(void) ++{ ++ rc_map_unregister(&mstar_tv_map); ++} ++ ++module_init(init_rc_map_mstar_tv); ++module_exit(exit_rc_map_mstar_tv); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Mauro Carvalho Chehab "); +diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c +index d87f77f7..17847e74 100644 +--- a/drivers/misc/eeprom/at24.c ++++ b/drivers/misc/eeprom/at24.c +@@ -665,7 +665,7 @@ static int at24_remove(struct i2c_client *client) + + static struct i2c_driver at24_driver = { + .driver = { +- .name = "at24", ++ .name = "24c512", + .owner = THIS_MODULE, + }, + .probe = at24_probe, +diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c +index 10ecc0a0..c8fad920 100644 +--- a/drivers/mmc/card/block.c ++++ b/drivers/mmc/card/block.c +@@ -2114,7 +2114,14 @@ static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card, + * index anymore so we keep track of a name index. + */ + if (!subname) { ++ ++#if defined (CONFIG_MS_SDMMC) || defined(CONFIG_MS_SDMMC_MODULE) ++ // Not good way someone modified code to reference ms_sdmmc_lnx.c data to lock the device name for Android disk, ++ // So I replace the way. Also I replace mmc device because they must lock mmc0 ++ md->name_idx = (unsigned int)card->host->index; ++#else + md->name_idx = find_first_zero_bit(name_use, max_devices); ++#endif + __set_bit(md->name_idx, name_use); + } else + md->name_idx = ((struct mmc_blk_data *) +@@ -2602,6 +2609,20 @@ static void __exit mmc_blk_exit(void) + unregister_blkdev(MMC_BLOCK_MAJOR, "mmc"); + } + ++struct mmc_card *mmc_blkdev_to_card(struct block_device *blkdev) ++{ ++ struct mmc_blk_data *md; ++ md = (struct mmc_blk_data *)(blkdev->bd_disk->private_data); ++ if(md) ++ { ++ return md->queue.card; ++ } ++ ++ return NULL; ++} ++ ++EXPORT_SYMBOL(mmc_blkdev_to_card); ++ + module_init(mmc_blk_init); + module_exit(mmc_blk_exit); + +diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c +index 01315db9..7dae33c7 100644 +--- a/drivers/mmc/core/core.c ++++ b/drivers/mmc/core/core.c +@@ -2369,8 +2369,16 @@ int _mmc_detect_card_removed(struct mmc_host *host) + { + int ret; + +- if (host->caps & MMC_CAP_NONREMOVABLE) ++ if ( ++#if defined (CONFIG_MS_SDMMC) || defined(CONFIG_MS_SDMMC_MODULE) ++#else ++ (host->caps & MMC_CAP_NONREMOVABLE) || ++#endif ++ !host->bus_ops->alive ++ ) ++ { + return 0; ++ } + + if (!host->card || mmc_card_removed(host->card)) + return 1; +@@ -2446,11 +2454,13 @@ void mmc_rescan(struct work_struct *work) + if (host->rescan_disable) + return; + ++#if defined (CONFIG_MS_SDMMC) || defined(CONFIG_MS_SDMMC_MODULE) ++#else + /* If there is a non-removable card registered, only scan once */ + if ((host->caps & MMC_CAP_NONREMOVABLE) && host->rescan_entered) + return; + host->rescan_entered = 1; +- ++#endif + mmc_bus_get(host); + + /* +@@ -2458,7 +2468,11 @@ void mmc_rescan(struct work_struct *work) + * still present + */ + if (host->bus_ops && !host->bus_dead +- && !(host->caps & MMC_CAP_NONREMOVABLE)) ++#if defined (CONFIG_MS_SDMMC) || defined(CONFIG_MS_SDMMC_MODULE) ++#else ++ && !(host->caps & MMC_CAP_NONREMOVABLE) ++#endif ++ ) + host->bus_ops->detect(host); + + host->detect_change = 0; +@@ -2482,7 +2496,12 @@ void mmc_rescan(struct work_struct *work) + */ + mmc_bus_put(host); + +- if (!(host->caps & MMC_CAP_NONREMOVABLE) && host->ops->get_cd && ++ if ( ++#if defined (CONFIG_MS_SDMMC) || defined(CONFIG_MS_SDMMC_MODULE) ++#else ++ !(host->caps & MMC_CAP_NONREMOVABLE) && ++#endif ++ host->ops->get_cd && + host->ops->get_cd(host) == 0) { + mmc_claim_host(host); + mmc_power_off(host); +diff --git a/drivers/mmc/core/sdio_ops.c b/drivers/mmc/core/sdio_ops.c +index 62508b45..df47d4d6 100644 +--- a/drivers/mmc/core/sdio_ops.c ++++ b/drivers/mmc/core/sdio_ops.c +@@ -216,7 +216,16 @@ int sdio_reset(struct mmc_host *host) + abort = 0x08; + else + abort |= 0x08; +- ++#ifdef CONFIG_MS_SDMMC ++ // Fixed Issue: One Special SD Card will always status busy at SD ACMD cmd of SD initial flow, but not error return. ++ // Linux initial CMD set contain SD/SD/SDIO command to check which type, ++ // Normally SD will ignore and return no resp from SDIO cmd CMD52, ++ // Although SD don't resp err, but I found this card must reamin a long gap time between first CMD 52 and second CMD52 ? ++ // I really don't know why? After the experiments, 10ms is a safe time to avoid this Special Card inner Issue. ++ // (P.S.) CMD52/CMD52 -> SD CMD0 reset don't help this card really reset the inner error. ++ // This patch is a workaround solution ++ mmc_delay(10); ++#endif + ret = mmc_io_rw_direct_host(host, 1, 0, SDIO_CCCR_ABORT, abort, NULL); + return ret; + } +diff --git a/drivers/mstar/Kconfig b/drivers/mstar/Kconfig +new file mode 100644 +index 00000000..913eb0bb +--- /dev/null ++++ b/drivers/mstar/Kconfig +@@ -0,0 +1,141 @@ ++source "drivers/mstar/irqchip/Kconfig" ++source "drivers/mstar/clocksource/Kconfig" ++source "drivers/mstar/msys/Kconfig" ++source "drivers/mstar/serial/Kconfig" ++source "drivers/mstar/clk/Kconfig" ++ ++ ++if (ARCH_INFINITY) || (ARCH_CEDRIC) || (ARCH_INFINITY3) ++source "drivers/mstar/isp/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/unfd/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_CHICAGO) || (ARCH_INFINITY3) ++source "drivers/mstar/emmc/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_CHICAGO) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/sdmmc/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_CHICAGO) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/sound/Kconfig" ++endif ++ ++ ++if (ARCH_CEDRIC) || (ARCH_CHICAGO) || (ARCH_INFINITY) ++source "drivers/mstar/usb/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) ++source "drivers/mstar/dip/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) ++source "drivers/mstar/mfe/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_CHICAGO) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/fb/Kconfig" ++endif ++ ++if (ARCH_INFINITY3) ++source "drivers/mstar/fb1/Kconfig" ++endif ++ ++if (ARCH_INFINITY3) ++source "drivers/mstar/fb2/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/scl/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/emac/Kconfig" ++endif ++ ++ ++if (ARCH_CEDRIC) || (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/ir/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/i2c/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/gpio/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/watchdog/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/sar/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/ircut/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/vhe/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/mfev5/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/rtc/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/jpe/Kconfig" ++endif ++ ++if (ARCH_CEDRIC) || (ARCH_CHICAGO) || (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/flash_isp/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/xpm/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/crypto/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/cpufreq/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/pwm/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/spinand/Kconfig" ++endif ++ ++if (ARCH_INFINITY)|| (ARCH_INFINITY3) ++source "drivers/mstar/spi/Kconfig" ++endif ++ ++if (ARCH_INFINITY) || (ARCH_INFINITY3) ++source "drivers/mstar/pm/Kconfig" ++endif ++ ++if (ARCH_INFINITY3) ++source "drivers/mstar/ive/Kconfig" ++endif ++ ++if (ARCH_INFINITY3) ++source "drivers/mstar/notify/Kconfig" ++endif ++ +diff --git a/drivers/mstar/Makefile b/drivers/mstar/Makefile +new file mode 100644 +index 00000000..3dfa96da +--- /dev/null ++++ b/drivers/mstar/Makefile +@@ -0,0 +1,39 @@ ++obj-y += irqchip/ ++obj-y += clocksource/ ++obj-y += serial/ ++obj-y += clk/ ++obj-y += msys/ ++obj-$(CONFIG_MS_NAND) += unfd/ ++obj-$(CONFIG_MS_EMMC) += emmc/ ++obj-$(CONFIG_MS_SDMMC) += sdmmc/ ++obj-$(CONFIG_MS_SOUND) += sound/ ++obj-$(CONFIG_USB_SUPPORT) += usb/ ++obj-$(CONFIG_MS_DIP) += dip/ ++obj-$(CONFIG_MS_MFE) += mfe/ ++obj-$(CONFIG_MS_FB) += fb/ ++obj-$(CONFIG_MS_FB) += fb1/ ++obj-$(CONFIG_MS_FB) += fb2/ ++obj-$(CONFIG_MS_EMAC) += emac/ ++obj-$(CONFIG_MS_SCL) += scl/ ++obj-$(CONFIG_MS_ISP) += isp/ ++obj-$(CONFIG_MS_IR) += ir/ ++obj-$(CONFIG_MS_VHE) += vhe/ ++obj-$(CONFIG_MS_MFEV5) += mfev5/ ++obj-$(CONFIG_MS_RTC) += rtc/ ++obj-$(CONFIG_MS_GPIO) += gpio/ ++obj-$(CONFIG_MS_WATCHDOG) += watchdog/ ++obj-$(CONFIG_MS_SAR) += sar/ ++obj-$(CONFIG_MS_IRCUT) += ircut/ ++obj-$(CONFIG_MS_I2C) += i2c/ ++obj-$(CONFIG_MS_JPE) += jpe2/ ++obj-$(CONFIG_MS_FLASH_ISP) += flash_isp/ ++obj-$(CONFIG_MS_XPM) += xpm/ ++obj-$(CONFIG_MS_CRYPTO) += crypto/ ++obj-$(CONFIG_MS_CPU_FREQ) += cpufreq/ ++obj-$(CONFIG_MS_PWM) += pwm/ ++obj-$(CONFIG_MS_SPINAND) += spinand/ ++obj-$(CONFIG_MS_SPI_INFINITY) += spi/ ++obj-$(CONFIG_MS_PM) += pm/ ++obj-$(CONFIG_MS_IVE) += ive/ ++obj-$(CONFIG_MS_PWM) += pwm/ ++obj-$(CONFIG_MS_NOTIFY) += notify/ +diff --git a/drivers/mstar/cam_os_wrapper/Makefile b/drivers/mstar/cam_os_wrapper/Makefile +new file mode 100644 +index 00000000..ea015f65 +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/Makefile +@@ -0,0 +1,88 @@ ++CROSS_COMPILE ?=arm-linux-gnueabihf- ++CC = $(CROSS_COMPILE)gcc ++STRIP = $(CROSS_COMPILE)strip ++BUILD_DIR := .build ++LIB_NAME=cam_os_wrapper ++BRANCH_ID := $(shell git rev-parse --abbrev-ref HEAD 2> /dev/null | sed -e 's/\//_/g') ++ ++#LINUX_KERNEL_PATH ?= ../../../linux-3.18 ++LINUX_KERNEL_PATH ?= ../../kernel/API ++KL_API_INCLUDE ?= $(LINUX_KERNEL_PATH)/drivers/mstar/include ++ ++ccflags-$(CONFIG_MS_JPE) := -Wall -Werror -g -O2 -ffunction-sections -funwind-tables -fstack-protector ++ccflags-$(CONFIG_MS_JPE) += -fPIC -DPIC -DOMXILCOMPONENTSPATH=\"/system/lib\" -DCONFIG_DEBUG_LEVEL=32 ++ ++ccflags-$(CONFIG_MS_JPE) += -DTEST_THREAD_ID_DETECTION ++ccflags-$(CONFIG_MS_JPE) += -DCAM_OS_LINUX_USER ++#CFLAGS += -D__USE_GNU ++LDFLAGS += -O2 -Bdirect -Wl,--hash-style=gnu ++LIBS := -ldl -lpthread ++ ++OMX_CORE_LIB_C_SRCS := \ ++ ./src/cam_os_wrapper.c \ ++ ++CINCLUDES := \ ++ -I$(KL_API_INCLUDE) \ ++ -I./pub \ ++ -I./inc \ ++ ++LIB_HEADERS := \ ++ ./pub/cam_os_wrapper.h \ ++ ./pub/cam_os_util_list.h \ ++ ++OMX_CORE_LIB_C_OBJS := $(patsubst %.c, %.c.so.o, $(OMX_CORE_LIB_C_SRCS)) ++ ++.PHONY: clean prepare lib$(LIB_NAME) ++ ++all: prepare lib$(LIB_NAME) ++ ++prepare: ++ @echo ++ @echo ">>>>========================================================" ++ @echo ++ @echo " LIB_NAME = ${LIB_NAME}" ++ @echo " PWD = $(shell pwd)" ++ @echo " CC = $(CC)" ++ @echo " BRANCH_ID = $(BRANCH_ID)" ++ @echo ++ @mkdir -p $(BUILD_DIR) ++ @echo " Copying headers to '$(BUILD_DIR)/include'..." ++ @echo ++ @mkdir -p $(BUILD_DIR)/include ++ @cp -f $(LIB_HEADERS) $(BUILD_DIR)/include ++ ++install: ++ @echo " INSTALL $(LIB_NAME) to $(INSTALLDIR)" ++ @rm -Rf $(INSTALLDIR) ++ @mkdir -p $(INSTALLDIR) ++ @cp -Rf $(BUILD_DIR)/lib $(INSTALLDIR) ++ @cp -Rf $(BUILD_DIR)/include $(INSTALLDIR) ++ ++clean: ++ @rm -Rf $(OMX_CORE_LIB_C_OBJS) ++ @rm -Rf $(BUILD_DIR) ++ ++lib$(LIB_NAME): prepare $(OMX_CORE_LIB_C_OBJS) ++ @mkdir -p $(BUILD_DIR)/lib ++ @echo " LD $(BUILD_DIR)/lib/$@.so" ++ @$(CC) -shared $(LDFLAGS) -o $(BUILD_DIR)/lib/$@.so $(OMX_CORE_LIB_C_OBJS) ${LIBS} ++ @echo ++ @echo "<<<<========================================================" ++ @echo ++ ++%.c.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ ++%.c.test.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++ @$(CC) $(CFLAGS) $(TEST_CINCLUDES) -c $< -o $@ ++ ++%.c.so.o : %.c ++ @mkdir -p $(dir $@) ++ @echo " CC $<" ++# @echo $(CFLAGS) $(CINCLUDES) -c $< -o $@ ++ @$(CC) $(CFLAGS) $(CINCLUDES) -c $< -o $@ +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/cam_os_wrapper.mak b/drivers/mstar/cam_os_wrapper/cam_os_wrapper.mak +new file mode 100644 +index 00000000..e806fcb9 +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/cam_os_wrapper.mak +@@ -0,0 +1,19 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_cam_os_wrapper)/src \ ++ $(PATH_cam_os_wrapper)/test ++ ++PATH_H +=\ ++ $(PATH_cam_os_wrapper)/pub \ ++ $(PATH_cam_os_wrapper)/inc \ ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ cam_os_wrapper.c \ ++ cam_os_wrapper_test.c \ +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/pub/cam_os_util_list.h b/drivers/mstar/cam_os_wrapper/pub/cam_os_util_list.h +new file mode 100644 +index 00000000..6110f320 +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/pub/cam_os_util_list.h +@@ -0,0 +1,81 @@ ++#ifndef __CAM_OS_UTIL_LIST_H__ ++#define __CAM_OS_UTIL_LIST_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++ ++ ++struct CamOsListHead_t ++{ ++ struct CamOsListHead_t *pNext, *pPrev; ++}; ++ ++#ifndef offsetof ++#ifdef __compiler_offsetof ++#define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) ++#else ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++#endif ++#endif ++ ++ ++#define CAM_OS_POISON_POINTER_DELTA 0 ++#define CAM_OS_LIST_POISON1 ((void *) 0x00100100 + CAM_OS_POISON_POINTER_DELTA) ++#define CAM_OS_LIST_POISON2 ((void *) 0x00200200 + CAM_OS_POISON_POINTER_DELTA) ++ ++ ++#define CAM_OS_CONTAINER_OF(ptr, type, member) ({ \ ++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \ ++ (type *)( (char *)__mptr - offsetof(type,member) );}) ++ ++#define CAM_OS_LIST_HEAD_INIT(name) { &(name), &(name) } ++ ++#define CAM_OS_LIST_ENTRY(ptr, type, member) \ ++ CAM_OS_CONTAINER_OF(ptr, type, member) ++ ++#define CAM_OS_LIST_FOR_EACH_SAFE(pos, n, head) \ ++ for (pos = (head)->pNext, n = pos->pNext; pos != (head); \ ++ pos = n, n = pos->pNext) ++ ++static inline void _ListDel(struct CamOsListHead_t * pPrev, struct CamOsListHead_t * pNext) ++{ ++ pNext->pPrev = pPrev; ++ pPrev->pNext = pNext; ++} ++ ++static inline void CAM_OS_LIST_DEL(struct CamOsListHead_t *pEntry) ++{ ++ _ListDel(pEntry->pPrev, pEntry->pNext); ++ pEntry->pNext = CAM_OS_LIST_POISON1; ++ pEntry->pPrev = CAM_OS_LIST_POISON2; ++} ++ ++static inline void CAM_OS_INIT_LIST_HEAD(struct CamOsListHead_t *pList) ++{ ++ pList->pNext = pList; ++ pList->pPrev = pList; ++} ++ ++static inline void _ListAdd(struct CamOsListHead_t *new, ++ struct CamOsListHead_t *pPrev, ++ struct CamOsListHead_t *pNext) ++{ ++ pNext->pPrev = new; ++ new->pNext = pNext; ++ new->pPrev = pPrev; ++ pPrev->pNext = new; ++} ++ ++static inline void CAM_OS_LIST_ADD_TAIL(struct CamOsListHead_t *new, struct CamOsListHead_t *head) ++{ ++ _ListAdd(new, head->pPrev, head); ++} ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_LIST_H__ +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/pub/cam_os_wrapper.h b/drivers/mstar/cam_os_wrapper/pub/cam_os_wrapper.h +new file mode 100644 +index 00000000..a1dcbe2b +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/pub/cam_os_wrapper.h +@@ -0,0 +1,593 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.h ++/// @brief Cam OS Wrapper Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_OS_WRAPPER_H__ ++#define __CAM_OS_WRAPPER_H__ ++ ++#if !defined(__KERNEL__) && !defined(_LINUX_TYPES_H) ++typedef unsigned char bool; ++#endif ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++typedef enum ++{ ++ CAM_OS_OK = 0, ++ CAM_OS_FAIL = -1, ++ CAM_OS_PARAM_ERR = -2, ++ CAM_OS_ALLOCMEM_FAIL = -3, ++ CAM_OS_TIMEOUT = -4, ++} CamOsRet_e; ++ ++typedef enum ++{ ++ CAM_OS_MEM_1MB = 0, ++ CAM_OS_MEM_2MB = 1, ++ CAM_OS_MEM_4MB = 2, ++ CAM_OS_MEM_8MB = 3, ++ CAM_OS_MEM_16MB = 4, ++ CAM_OS_MEM_32MB = 5, ++ CAM_OS_MEM_64MB = 6, ++ CAM_OS_MEM_128MB = 7, ++ CAM_OS_MEM_256MB = 8, ++ CAM_OS_MEM_512MB = 9, ++ CAM_OS_MEM_1024MB = 10, ++ CAM_OS_MEM_UNKNOWN = 99, ++} CamOsMemSize_e; ++ ++typedef struct ++{ ++ u8 nPriv[40]; ++} CamOsMutex_t; ++ ++typedef struct ++{ ++ u8 nPriv[80]; ++} CamOsTsem_t; ++ ++typedef struct ++{ ++ u32 nSec; ++ u32 nNanoSec; ++} CamOsTimespec_t; ++ ++typedef struct ++{ ++ u32 nPriority; /* From 1(lowest) to 99(highest), use OS default priority if set 0 */ ++ u32 nStackSize; /* If nStackSize is zero, use OS default value */ ++ char *szName; /* Name of Thread */ ++} CamOsThreadAttrb_t, *pCamOsThreadAttrb; ++ ++typedef void * CamOsThread; ++ ++//============================================================================= ++// Description: ++// Writes the C string pointed by format to the standard output. ++// Parameters: ++// [in] szFmt: C string that contains the text to be written, it can ++// optionally contain embedded format specifiers. ++// Return: ++// N/A ++//============================================================================= ++void CamOsDebug(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Reads data from stdin and stores them according to the parameter format ++// into the locations pointed by the additional arguments. ++// Parameters: ++// [in] szFmt: C string that contains the text to be parsing, it can ++// optionally contain embedded format specifiers. ++// Return: ++// The number of items of the argument list successfully filled. ++//============================================================================= ++s32 CamOsScanf(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Returns the next character from the standard input. ++// Parameters: ++// N/A ++// Return: ++// the character read is returned. ++//============================================================================= ++s32 CamOsGetChar(void); ++ ++//============================================================================= ++// Description: ++// Suspend execution for millisecond intervals. ++// Parameters: ++// [in] nMsec: Millisecond to suspend. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMsSleep(u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Get the number of seconds and nanoseconds since the Epoch. ++// Parameters: ++// [out] ptRes: A pointer to a CamOsTimespec_t structure where ++// CamOsGetTimeOfDay() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetTimeOfDay(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Set the number of seconds and nanoseconds since the Epoch. ++// Parameters: ++// [in] ptRes: A pointer to a CamOsTimespec_t structure. ++// Return: ++// N/A ++//============================================================================= ++void CamOsSetTimeOfDay(const CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// Gets the current time of the clock specified, and puts it into the ++// buffer pointed to by ptRes. ++// Parameters: ++// [out] ptRes: A pointer to a CamOsTimespec_t structure where ++// CamOsGetMonotonicTime() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// The CamOsThreadCreate() function is used to create a new thread/task, ++// with attributes specified by ptAttrb. If ptAttrb is NULL, the default ++// attributes are used. ++// Parameters: ++// [out] pThread: A successful call to CamOsThreadCreate() stores the handle ++// of the new thread in the buffer pointed to by pThread. ++// [in] ptAttrb: Argument points to a CamOsThreadAttrb_t structure whose ++// contents are used at thread creation time to determine ++// thread priority, stack size and thread name. Thread ++// priority range from 1(lowest) to 99(highest), use OS ++// default priority if set 0. ++// [in] pfnStartRoutine(): The new thread starts execution by invoking it. ++// [in] pArg: It is passed as the sole argument of pfnStartRoutine(). ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadCreate(CamOsThread *pThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg); ++ ++//============================================================================= ++// Description: ++// Waits for the thread specified by pThread to terminate. If that thread ++// has already terminated, then CamOsThreadJoin() returns immediately. This ++// function is not applicable to Linux kernel space. ++// Parameters: ++// [in] thread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadJoin(CamOsThread thread); ++ ++//============================================================================= ++// Description: ++// Stop a thread created by CamOsThreadCreate in Linux kernel space. This ++// function is not applicable to RTK and Linux user space. ++// Parameters: ++// [in] thread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadStop(CamOsThread thread); ++ ++//============================================================================= ++// Description: ++// When someone calls CamOsThreadStop, it will be woken and this will ++// return true. You should then return from the thread. This function is ++// not applicable to RTK and Linux user space. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadShouldStop(void); ++ ++//============================================================================= ++// Description: ++// Set the name of a thread. The thread name is a meaningful C language ++// string, whose length is restricted to 16 characters, including the ++// terminating null byte ('\0'). ++// Parameters: ++// [in] thread: Handle of target thread. ++// [in] szName: specifies the new name. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadSetName(CamOsThread thread, const char *szName); ++ ++//============================================================================= ++// Description: ++// Get the name of a thread. The buffer specified by name should be at ++// least 16 characters in length. ++// Parameters: ++// [in] thread: Handle of target thread. ++// [out] szName: Buffer used to return the thread name. ++// [in] nLen: Specifies the number of bytes available in szName ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadGetName(CamOsThread thread, const char *szName, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Get thread identification. ++// Parameters: ++// N/A ++// Return: ++// On success, returns the thread ID of the calling process. ++//============================================================================= ++u32 CamOsThreadGetID(void); ++ ++//============================================================================= ++// Description: ++// Initializes the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Destroys the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Lock the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Unlock the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Initializes the semaphore at a given value. ++// Parameters: ++// [in] ptTsem: The semaphore to initialize. ++// [in] nVal: the initial value of the semaphore. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal); ++ ++//============================================================================= ++// Description: ++// Destroy the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Increases the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to increase. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemUp(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemDown(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if down successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Signal the condition, if waiting. ++// Parameters: ++// [in] ptTsem: The semaphore to signal ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemSignal(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTsem: The semaphore to wait. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemWait(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTsem: The semaphore to wait. ++// [in] nMsec: The value of delay for the timeout. ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if wait successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTimedWait(CamOsTsem_t *ptTsem, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Get the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to reset. ++// Return: ++// The value of the semaphore. ++//============================================================================= ++u32 CamOsTsemGetValue(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Reset the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to reset. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemReset(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of memory, returning a pointer to the ++// beginning of the block. ++// Parameters: ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemAlloc(u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of memory for an array of nNum elements, each of them ++// nSize bytes long, and initializes all its bits to zero. ++// Parameters: ++// [in] nNum: Number of elements to allocate. ++// [in] nSize: Size of each element. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemCalloc(u32 nNum, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Changes the size of the memory block pointed to by pPtr. The function ++// may move the memory block to a new location (whose address is returned ++// by the function). ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// [in] nSize: New size for the memory block, in bytes. ++// Return: ++// A pointer to the reallocated memory block, which may be either the same ++// as pPtr or a new location. ++//============================================================================= ++void* CamOsMemRealloc(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsMemAlloc, ++// CamOsMemCalloc or CamOsMemRealloc is deallocated, making it available ++// again for further allocations. If pPtr is a null pointer, the function ++// does nothing. ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemRelease(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of direct memory (non-cached memory), ++// returning three pointer for different address domain to the beginning ++// of the block. ++// Parameters: ++// [in] szName: Name of the memory block, whose length is restricted to ++// 16 characters. ++// [in] nSize: Size of the memory block, in bytes. ++// [out] ppUserPtr: Virtual address pointer to the memory block. ++// [out] pMiuAddr: Memory Interface Unit address pointer to the memory block. ++// [out] lpPhysAddr: Physical address pointer to the memory block. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppUserPtr, ++ u64 *pMiuAddr, ++ u64 *lpPhysAddr); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsDirectMemAlloc, ++// is deallocated, making it available again for further allocations. ++// Parameters: ++// [in] pUserPtr: Virtual address pointer to a memory block previously allocated with ++// CamOsDirectMemAlloc. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemRelease(void* pUserPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Print all allocated direct memory information to the standard output. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemStat(void); ++ ++//============================================================================= ++// Description: ++// Transfer Physical address to MIU address. ++// Parameters: ++// [in] nAddr: Physical address. ++// Return: ++// MIU address. ++//============================================================================= ++u64 CamOsDirectMemPhysToMiu(u64 nAddr); ++ ++//============================================================================= ++// Description: ++// Transfer MIU address to Physical address. ++// Parameters: ++// [in] nAddr: MIU address. ++// Return: ++// Physical address. ++//============================================================================= ++u64 CamOsDirectMemMiuToPhys(u64 nAddr); ++ ++//============================================================================= ++// Description: ++// Set property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [in] szValue: Value if property. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue); ++ ++//============================================================================= ++// Description: ++// Get property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [out] szValue: Value if property. ++// [in] szDefaultValue: If the property read fails or returns an empty ++// value, the default value is used ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertyGet(const char *szkey, char *szValue, const char *szDefaultValue); ++ ++//============================================================================= ++// Description: ++// Unsigned 64bit divide with Unsigned 64bit divisor with remainder. ++// Parameters: ++// [in] nDividend: Dividend. ++// [in] nDivisor: Divisor. ++// [out] pRemainder: Pointer to the remainder. ++// Return: ++// Quotient of division. ++//============================================================================= ++u64 CamOsMathDivU64(u64 nDividend, u64 nDivisor, u64 *pRemainder); ++ ++//============================================================================= ++// Description: ++// Signed 64bit divide with signed 64bit divisor with remainder. ++// Parameters: ++// [in] nDividend: Dividend. ++// [in] nDivisor: Divisor. ++// [out] pRemainder: Pointer to the remainder. ++// Return: ++// Quotient of division. ++//============================================================================= ++s64 CamOsMathDivS64(s64 nDividend, s64 nDivisor, s64 *pRemainder); ++ ++//============================================================================= ++// Description: ++// Get physical memory size of system. ++// Parameters: ++// N/A ++// Return: ++// Enumeration of memory size. ++//============================================================================= ++CamOsMemSize_e CamOsPhysMemSize(void); ++ ++//============================================================================= ++// Description: ++// Get Chip ID. ++// Parameters: ++// N/A ++// Return: ++// Chip ID. ++//============================================================================= ++u32 CamOsChipId(void); ++ ++#endif /* __CAM_OS_WRAPPER_H__ */ +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/src/cam_os_wrapper.c b/drivers/mstar/cam_os_wrapper/src/cam_os_wrapper.c +new file mode 100644 +index 00000000..e99c0974 +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/src/cam_os_wrapper.c +@@ -0,0 +1,2229 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.c ++/// @brief Cam OS Wrapper Source File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#ifdef CAM_OS_RTK ++#include ++#include ++#include ++#include "time.h" ++#include "sys_sys.h" ++#include "sys_sys_math64.h" ++#include "sys_sys_tools.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#include "sys_MsWrapper_cus_os_util.h" ++#include "sys_sys_isw_uart.h" ++#include "sys_rtk_hp.h" ++#include "hal_drv_util.h" ++#include "sys_time.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++ ++//#define __RTK_US_RESOLUTION_TIMER__ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef void *CamOsThreadEntry_t(void *); ++ ++typedef struct ++{ ++ MsTaskId_e eHandleObj; ++ CamOsThreadEntry_t *ptEntry; ++ void *pArg; ++ Ms_Flag_t tExitFlag; ++ void *pStack; ++} CamOsThreadHandleRtk_t, *pCamOsThreadHandleRtk; ++ ++typedef struct ++{ ++ Ms_Flag_t tFlag; /* or semaphore if supported */ ++ Ms_Mutex_t tMutex; ++ u32 nSemval; ++} CamOsTsemRtk_t, *pCamOsTsemRtk; ++ ++static Ms_Mutex_t _gtMemLock; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(Ms_Flag_t), "CamOsMutex_t size define not enough!"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemRtk_t), "CamOsTsem_t size define not enough!"); ++ ++#elif defined(CAM_OS_LINUX_USER) ++#define _GNU_SOURCE ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_verchk.h" ++#include ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++typedef struct ++{ ++ pthread_cond_t tCondition; ++ pthread_mutex_t tMutex; ++ u32 nSemval; ++} CamOsTsemLU_t, *pCamOsTsemLU; ++ ++// TODO remove extern pthread_setname_np and pthread_getname_np ++extern int pthread_setname_np(pthread_t tTargetThread, const char *szTargetName); ++extern int pthread_getname_np(pthread_t tThread, char *szName, size_t nLen); ++ ++static pthread_mutex_t _gtMemLock = PTHREAD_MUTEX_INITIALIZER; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(pthread_mutex_t), "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLU_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef struct ++{ ++ struct semaphore tSem; ++ struct mutex tMutex; ++ u32 nSemval; ++} CamOsTsemLK_t, *pCamOsTsemLK; ++ ++typedef s32 CamOsThreadEntry_t(void *); ++ ++struct mutex _gtMemLock; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(struct mutex), "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLK_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++ ++#endif ++ ++#define RIU_BASE_ADDR 0x1F000000 ++#define RIU_MEM_SIZE_OFFSET 0x2025A4 ++#define RIU_CHIP_ID_OFFSET 0x003C00 ++ ++typedef struct MemoryList_t ++{ ++ struct CamOsListHead_t tList; ++ void *pPtr; ++ void *pMemifoPtr; ++} MemoryList_t; ++ ++static MemoryList_t _gtMemList; ++ ++static s32 _gnDmemDbgListInited = 0; ++ ++void CamOsDebug(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ va_list tArgs; ++ char nLineStr[256]; ++ ++ va_start(tArgs, szFmt); ++ vsprintf(nLineStr, szFmt, tArgs); ++ send_msg(nLineStr); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_USER) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vfprintf(stderr, szFmt, tArgs); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vprintk(szFmt, tArgs); ++ va_end(tArgs); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static char* _CamOsAdvance(char* pBuf) { ++ ++ char* pNewBuf = pBuf; ++ ++ /* Skip over nonwhite space */ ++ while ((*pNewBuf != ' ') && (*pNewBuf != '\t') && ++ (*pNewBuf != '\n') && (*pNewBuf != '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ /* Skip white space */ ++ while ((*pNewBuf == ' ') || (*pNewBuf == '\t') || ++ (*pNewBuf == '\n') || (*pNewBuf == '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ return pNewBuf; ++} ++ ++static s32 _CamOsVsscanf(char* szBuf, char* szFmt, va_list tArgp) ++{ ++ char* pFmt; ++ char* pBuf; ++ char* pnSval; ++ u32* pnU32Val; ++ s32* pnS32Val; ++ u64* pnU64Val; ++ s64* pnS64Val; ++ double* pdbDval; ++ float* pfFval; ++ s32 nCount = 0; ++ ++ pBuf = szBuf; ++ ++ for (pFmt = szFmt; *pFmt; pFmt++) ++ { ++ if (*pFmt == '%') ++ { ++ pFmt++; ++ if (strncmp (pFmt, "u", 1) == 0) ++ { ++ pnU32Val = va_arg(tArgp, u32 *); ++ sscanf(pBuf, "%u", pnU32Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if (strncmp (pFmt, "d", 1) == 0) ++ { ++ pnS32Val = va_arg(tArgp, s32 *); ++ sscanf(pBuf, "%d", pnS32Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if (strncmp (pFmt, "llu", 3) == 0) ++ { ++ pnU64Val = va_arg(tArgp, u64 *); ++ sscanf(pBuf, "%llu", pnU64Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if (strncmp (pFmt, "lld", 3) == 0) ++ { ++ pnS64Val = va_arg(tArgp, s64 *); ++ sscanf(pBuf, "%lld", pnS64Val); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if (strncmp (pFmt, "f", 1) == 0) ++ { ++ pfFval = va_arg(tArgp, float *); ++ sscanf(pBuf, "%f", pfFval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if (strncmp (pFmt, "lf", 2) == 0) ++ { ++ pdbDval = va_arg(tArgp, double *); ++ sscanf(pBuf, "%lf", pdbDval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else if (strncmp (pFmt, "s", 1) == 0) ++ { ++ pnSval = va_arg(tArgp, char *); ++ sscanf(pBuf, "%s", pnSval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ } ++ else ++ { ++ CamOsDebug("_CamOsVsscanf error: unsupported format (\%%s)\n", pFmt); ++ } ++ } ++ } ++ ++ return nCount; ++} ++ ++static s32 _CamOsGetString(char* szBuf, s32 nMaxLen, s32 nEcho) ++{ ++ s32 nLen; ++ static char ch = '\0'; ++ ++ nLen = 0; ++ while (1) ++ { ++ szBuf[nLen] = get_char(); ++ ++ // To ignore one for (\r,\n) or (\n, \r) pair ++ if ((szBuf[nLen]=='\n' && ch=='\r') || (szBuf[nLen]=='\r' && ch=='\n')) ++ { ++ ch = '\0'; ++ continue; ++ } ++ ch = szBuf[nLen]; ++ if (ch=='\n' || ch=='\r') ++ { ++ if (nEcho) ++ CamOsDebug("\n"); ++ break; ++ } ++ if (nLen < (nMaxLen - 1)) ++ { ++ if (ch == '\b') /* Backspace? */ ++ { ++ if (nLen <= 0) ++ CamOsDebug("\007"); ++ else ++ { ++ CamOsDebug("\b \b"); ++ nLen --; ++ } ++ continue; ++ } ++ nLen++; ++ } ++ if (nEcho) ++ CamOsDebug("%c", ch); ++ } ++ szBuf[nLen] = '\0'; ++ return nLen; ++} ++ ++static s32 _CamOsVfscanf(const char *szFmt, va_list tArgp) ++{ ++ s32 nCount; ++ char szCommandBuf[128]; ++ ++ _CamOsGetString(szCommandBuf, sizeof(szCommandBuf), 1); ++ ++ nCount = _CamOsVsscanf(szCommandBuf, (char *)szFmt, tArgp); ++ return nCount; ++} ++#endif ++ ++s32 CamOsScanf(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start (tArgp, szFmt); ++ nCount = _CamOsVfscanf (szFmt, tArgp); ++ va_end (tArgp); ++ return nCount; ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start (tArgp, szFmt); ++ nCount = vfscanf (stdin, szFmt, tArgp); ++ va_end (tArgp); ++ return nCount; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++} ++ ++s32 CamOsGetChar(void) ++{ ++#ifdef CAM_OS_RTK ++ s32 Ret; ++ Ret = get_char(); ++ CamOsDebug("\n"); ++ return Ret; ++#elif defined(CAM_OS_LINUX_USER) ++ return getchar(); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++} ++ ++void CamOsMsSleep(u32 nMsec) ++{ ++#ifdef CAM_OS_RTK ++ MsSleep(RTK_MS_TO_TICK(nMsec)); ++#elif defined(CAM_OS_LINUX_USER) ++ usleep((useconds_t)nMsec * 1000); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ msleep(nMsec); ++#endif ++} ++ ++void CamOsGetTimeOfDay(CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ if (ptRes) ++ { ++ SysTimeGetUTCSeconds(&ptRes->nSec); ++ ptRes->nNanoSec = 0; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ struct timeval tTV; ++ if (ptRes) ++ { ++ gettimeofday(&tTV, NULL); ++ ptRes->nSec = tTV.tv_sec; ++ ptRes->nNanoSec = tTV.tv_usec*1000; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct timeval tTv; ++ if (ptRes) ++ { ++ do_gettimeofday(&tTv); ++ ptRes->nSec = tTv.tv_sec; ++ ptRes->nNanoSec = tTv.tv_usec*1000; ++ } ++#endif ++} ++ ++void CamOsSetTimeOfDay(const CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ struct tm * tTm; ++ vm_rtcTimeFormat_t tLocalTime; ++ if (ptRes) ++ { ++ tTm = localtime ((time_t *)&ptRes->nSec); ++ ++ tLocalTime.Year = tTm->tm_year; ++ tLocalTime.Month = tTm->tm_mon+1; ++ tLocalTime.Day = tTm->tm_mday; ++ tLocalTime.DayOfWeek = tTm->tm_wday? tTm->tm_wday : 7; ++ tLocalTime.Hour = tTm->tm_hour; ++ tLocalTime.Minute = tTm->tm_min; ++ tLocalTime.Second = tTm->tm_sec; ++ ++ SysTimeSetTime(&tLocalTime); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ struct timeval tTV; ++ if (ptRes) ++ { ++ tTV.tv_sec = ptRes->nSec; ++ tTV.tv_usec = ptRes->nNanoSec/1000; ++ settimeofday(&tTV, NULL); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct timespec tTs; ++ if (ptRes) ++ { ++ tTs.tv_sec = ptRes->nSec; ++ tTs.tv_nsec = ptRes->nNanoSec; ++ do_settimeofday(&tTs); ++ } ++#endif ++} ++ ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++#ifdef __RTK_US_RESOLUTION_TIMER__ ++ u64 nUs; ++ if (ptRes) ++ { ++ nUs = DrvTimerStdaTimerTick2UsEx(RtkGetOsTickExt()); ++ ptRes->nSec = nUs / 1000000; ++ ptRes->nNanoSec = (nUs % 1000000) * 1000; ++ } ++#else ++ u32 nMs; ++ if (ptRes) ++ { ++ nMs = VM_RTK_TICK_TO_MS(MsGetOsTick()); ++ ptRes->nSec = nMs / 1000; ++ ptRes->nNanoSec = (nMs % 1000) * 1000000; ++ } ++#endif ++#elif defined(CAM_OS_LINUX_USER) ++ clock_gettime(CLOCK_MONOTONIC, (struct timespec *)ptRes); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ getrawmonotonic((struct timespec *)ptRes); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static void _CamOSThreadEntry(void *pEntryData) ++{ ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)pEntryData; ++ ++ ptTaskHandle->ptEntry(ptTaskHandle->pArg); ++ ++ MsFlagSetbits(&ptTaskHandle->tExitFlag, 0x00000001); ++} ++ ++static void _CamOsThreadEmptyParser(vm_msg_t *ptMessage) ++{ ++ ++} ++#endif ++ ++CamOsRet_e CamOsThreadCreate(CamOsThread *pThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = NULL; ++ MsTaskCreateArgs_t tTaskArgs = {0}; ++ u32 nPrio = 100; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ char *szName = NULL; ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority > 0) && (ptAttrb->nPriority < 100)) ++ { ++ nPrio = ptAttrb->nPriority * 2; ++ } ++ nStkSz = (ptAttrb->nStackSize)? ptAttrb->nStackSize : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ szName = ptAttrb->szName; ++ } ++ ++ *pThread = (void*) - 1; ++ do ++ { ++ if(!(ptTaskHandle = MsCallocateMem(sizeof(CamOsThreadHandleRtk_t)))) ++ { ++ CamOsDebug("%s : Allocate ptHandle fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ ptTaskHandle->ptEntry = pfnStartRoutine; ++ ptTaskHandle->pArg = pArg; ++ if(!(ptTaskHandle->pStack = MsAllocateMem((nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT))) ++ { ++ CamOsDebug("%s : Allocate stack fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ memset(&ptTaskHandle->tExitFlag, 0, sizeof(Ms_Flag_t)); ++ MsFlagInit(&ptTaskHandle->tExitFlag); ++ //VEN_TEST_CHECK_RESULT((pTaskHandle->exit_flag.FlagId >> 0) && (pTaskHandle->exit_flag.FlagState == RTK_FLAG_INITIALIZED)); ++ ++ tTaskArgs.Priority = (nPrio >= 0 && nPrio <= 200) ? nPrio : 100; ++ tTaskArgs.StackSize = (nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ tTaskArgs.pStackTop = (u32*)ptTaskHandle->pStack; ++ tTaskArgs.AppliInit = &_CamOSThreadEntry; ++ tTaskArgs.AppliParser = _CamOsThreadEmptyParser; ++ tTaskArgs.pInitArgs = ptTaskHandle; ++ tTaskArgs.TaskId = &ptTaskHandle->eHandleObj; ++ tTaskArgs.ImmediatelyStart = TRUE; ++ tTaskArgs.TimeSliceMax = 10; ++ tTaskArgs.TimeSliceLeft = 10; ++ if (szName && strlen(szName)) ++ strncpy(tTaskArgs.TaskName, szName, sizeof(tTaskArgs.TaskName)); ++ else ++ strncpy(tTaskArgs.TaskName, "CamOsWrp", sizeof(tTaskArgs.TaskName)); ++ ++ ++ if(MS_OK != MsCreateTask(&tTaskArgs)) ++ { ++ CamOsDebug("%s : Create task fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *pThread = ptTaskHandle; ++ } ++ while(0); ++ ++ if(!*pThread) ++ { ++ if(ptTaskHandle) ++ { ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsReleaseMemory(ptTaskHandle); ++ } ++ } ++ ++ //CamOsDebug("%s get taskid: %d(%s) priority: %d\n\r", __FUNCTION__, (u32)ptTaskHandle->eHandleObj, tTaskArgs.TaskName, tTaskArgs.Priority); ++#elif defined(CAM_OS_LINUX_USER) ++ struct sched_param tSched; ++ pthread_t tThreadHandle = NULL; ++ pthread_attr_t tAttr; ++ if(ptAttrb != NULL) ++ { ++ pthread_attr_init(&tAttr); ++ ++ if((ptAttrb->nPriority > 0) && (ptAttrb->nPriority < 100)) ++ { ++ pthread_attr_getschedparam(&tAttr, &tSched); ++ pthread_attr_setinheritsched(&tAttr, PTHREAD_EXPLICIT_SCHED); ++ pthread_attr_setschedpolicy(&tAttr, SCHED_RR); ++ tSched.sched_priority = ptAttrb->nPriority; ++ pthread_attr_setschedparam(&tAttr, &tSched); ++ } ++ ++ if(0 != ptAttrb->nStackSize) ++ { ++ pthread_attr_setstacksize(&tAttr, (size_t) ptAttrb->nStackSize); ++ eRet = CAM_OS_FAIL; ++ } ++ pthread_create(&tThreadHandle, &tAttr, pfnStartRoutine, pArg); ++ pthread_attr_destroy(&tAttr); ++ ++ pthread_setname_np(tThreadHandle, ptAttrb->szName); ++ } ++ else ++ { ++ pthread_create(&tThreadHandle, NULL, pfnStartRoutine, pArg); ++ } ++ ++ *pThread = (CamOsThread *)tThreadHandle; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle; ++ struct sched_param tSche = { .sched_priority = 0 }; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority > 0) && (ptAttrb->nPriority < 100)) ++ { ++ tSche.sched_priority = ptAttrb->nPriority; ++ } ++ nStkSz = ptAttrb->nStackSize; ++ } ++ tpThreadHandle = kthread_run((CamOsThreadEntry_t *)pfnStartRoutine, pArg, "CAMOS"); ++ sched_setscheduler(tpThreadHandle, SCHED_RR, &tSche); ++ *pThread = (CamOsThread *)tpThreadHandle; ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadJoin(CamOsThread thread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)thread; ++ if(ptTaskHandle) ++ { ++ MsFlagWait(&ptTaskHandle->tExitFlag, 0x00000001, RTK_FLAG_WAITMODE_AND | RTK_FLAG_WAITMODE_CLR); ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsDeleteTask(ptTaskHandle->eHandleObj); ++ ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsReleaseMemory(ptTaskHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_join(tThreadHandle, NULL); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadStop(CamOsThread thread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle = (struct task_struct *)thread; ++ if(tpThreadHandle) ++ { ++ if(0 != kthread_stop((struct task_struct *)thread)) ++ { ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadShouldStop(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(kthread_should_stop()) ++ { ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_FAIL; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadSetName(CamOsThread thread, const char *szName) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ // TODO RTK not support set task name dynamic. ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_setname_np(tThreadHandle, szName); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadGetName(CamOsThread thread, const char *szName, u32 nLen) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_getname_np(tThreadHandle, (char *)szName, nLen); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++u32 CamOsThreadGetID() ++{ ++#ifdef CAM_OS_RTK ++ return MsCurrTask(); ++#elif defined(CAM_OS_LINUX_USER) ++ return (u32)syscall(__NR_gettid); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return current->tgid; ++#endif ++} ++ ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsInitMutex(ptHandle)) ++ { ++ CamOsDebug("%s : Init mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != pthread_mutex_init(ptHandle, NULL)) ++ { ++ fprintf(stderr, "%s : Init mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_init(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ // Do Nothing in RTK ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ pthread_mutex_destroy(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsMutexLock(ptHandle)) ++ { ++ CamOsDebug("%s : Lock mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != (nErr = pthread_mutex_lock(ptHandle))) ++ { ++ fprintf(stderr, "%s : Lock mutex fail, err %d\n\r", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_lock(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsMutexUnlock(ptHandle)) ++ { ++ CamOsDebug("%s : Unlock mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != (nErr = pthread_mutex_unlock(ptHandle))) ++ { ++ fprintf(stderr, "%s : Unlock mutex fail, err %d\n\r", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_unlock(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagInit(&ptHandle->tFlag); ++ MsInitMutex(&ptHandle->tMutex); ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(0 != pthread_cond_init(&ptHandle->tCondition, NULL)) ++ { ++ return CAM_OS_FAIL; ++ } ++ if(0 != pthread_mutex_init(&ptHandle->tMutex, NULL)) ++ { ++ return CAM_OS_FAIL; ++ } ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ sema_init(&ptHandle->tSem, nVal); ++ mutex_init(&ptHandle->tMutex); ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagDestroy(&ptHandle->tFlag); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_cond_destroy(&ptHandle->tCondition); ++ pthread_mutex_destroy(&ptHandle->tMutex); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++void CamOsTsemUp(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ MsMutexUnlock(&ptHandle->tMutex); ++ MsFlagSetbits(&ptHandle->tFlag, 0x00000001); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ mutex_unlock(&ptHandle->tMutex); ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemDown(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ MsMutexUnlock(&ptHandle->tMutex); ++ MsFlagWait(&ptHandle->tFlag, 0x00000001, MS_FLAG_WAITMODE_OR); ++ MsMutexLock(&ptHandle->tMutex); ++ } ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ MsMutexUnlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ } ++ ptHandle->nSemval--; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ down(&ptHandle->tSem); ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval--; ++ mutex_unlock(&ptHandle->tMutex); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ MsMutexUnlock(&ptHandle->tMutex); ++ nErr = MsFlagTimedWait(&ptHandle->tFlag, 1, (MS_FLAG_WAITMODE_OR), RTK_MS_TO_TICK(nMsec)); ++ /*time out*/ ++ MsMutexLock(&ptHandle->tMutex); ++ if(!nErr) ++ { ++ break; ++ } ++ } ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ MsMutexUnlock(&ptHandle->tMutex); ++ if(!nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ struct timeval tCurrTime; ++ u32 nMicDelay; ++ ++ if(ptHandle) ++ { ++ gettimeofday(&tCurrTime, NULL); ++ /** convert timeval to timespec and add delay in milliseconds for the timeout */ ++ nMicDelay = ((nMsec * 1000 + tCurrTime.tv_usec)); ++ tFinalTime.tv_sec = tCurrTime.tv_sec + (nMicDelay / 1000000); ++ tFinalTime.tv_nsec = (nMicDelay % 1000000) * 1000; ++ pthread_mutex_lock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ if(nErr != 0) ++ { ++ ptHandle->nSemval--; ++ } ++ } ++ ptHandle->nSemval--; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ eRet = CAM_OS_OK; ++ else if(nErr == ETIMEDOUT) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec)); ++ mutex_lock(&ptHandle->tMutex); ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ mutex_unlock(&ptHandle->tMutex); ++ if(nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemSignal(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagSetbits(&ptHandle->tFlag, 0x00000001); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemWait(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagWait(&ptHandle->tFlag, 0x00000001, MS_FLAG_WAITMODE_OR); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ down(&ptHandle->tSem); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemTimedWait(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = MsFlagTimedWait(&ptHandle->tFlag, 1, (MS_FLAG_WAITMODE_OR), RTK_MS_TO_TICK(nMsec)); ++ if(!nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ struct timespec tCurrTime; ++ s64 nNanoDelay = 0; ++ ++ if(ptHandle) ++ { ++ clock_gettime(CLOCK_MONOTONIC, &tCurrTime); ++ ++ nNanoDelay = (nMsec * 1000000LL) + tCurrTime.tv_nsec; ++ tFinalTime.tv_sec = tCurrTime.tv_sec + (nNanoDelay / 1000000000LL); ++ tFinalTime.tv_nsec = nNanoDelay % 1000000000LL; ++ ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ eRet = CAM_OS_OK; ++ else if(nErr == ETIMEDOUT) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec)); ++ if(nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++u32 CamOsTsemGetValue(CamOsTsem_t *ptTsem) ++{ ++ s32 eRet = 0; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemReset(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ MsMutexUnlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ sema_init(&ptHandle->tSem, 0); ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ mutex_unlock(&ptHandle->tMutex); ++ } ++#endif ++} ++ ++void* CamOsMemAlloc(u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsAllocateMem(nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return malloc(nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return kzalloc(nSize, GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemCalloc(u32 nNum, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsCallocateMem(nNum * nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return calloc(nNum, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return kzalloc(nSize, GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemRealloc(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsMemoryReAllocate(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return realloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ void *pAddr = kzalloc(nSize, GFP_KERNEL); ++ if(pPtr && pAddr) ++ { ++ memcpy(pAddr, pPtr, nSize); ++ kfree(pPtr); ++ } ++ return pAddr; ++#endif ++} ++ ++void CamOsMemRelease(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ if(pPtr) ++ { ++ MsReleaseMemory(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(pPtr) ++ { ++ free(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(pPtr) ++ { ++ kfree(pPtr); ++ } ++#endif ++} ++ ++static s32 _CheckDmemInfoListInited(void) ++{ ++#ifdef CAM_OS_RTK ++ if(!_gnDmemDbgListInited) ++ { ++ if(CUS_OS_OK != MsInitMutex(&_gtMemLock)) ++ { ++ CamOsDebug("%s : Init mutex fail\n\r", __FUNCTION__); ++ } ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(!_gnDmemDbgListInited) ++ { ++ pthread_mutex_init(&_gtMemLock, NULL); ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(!_gnDmemDbgListInited) ++ { ++ mutex_init(&_gtMemLock); ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#endif ++ ++ return 0; ++} ++ ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppUserPtr, ++ u64 *pMiuAddr, ++ u64 *lpPhysAddr) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ u8 nAllocSucc = TRUE; ++ *ppUserPtr = MsAllocateNonCacheMemExt(nSize, 12); ++ nAllocSucc &= MsIsHeapMemory(*ppUserPtr); ++ ++ if((u32)*ppUserPtr & ((1 << 6) - 1)) ++ { ++ nAllocSucc &= FALSE; ++ MsReleaseMemory(*ppUserPtr); ++ } ++ ++ if(nAllocSucc == TRUE) ++ { ++ *lpPhysAddr = (u32)MsVA2PA(*ppUserPtr); ++ *pMiuAddr = HalUtilPHY2MIUAddr((u32)*lpPhysAddr); ++ } ++ else ++ { ++ *ppUserPtr = 0; ++ *lpPhysAddr = (u64)0; ++ *pMiuAddr = 0; ++ eRet = CAM_OS_FAIL; ++ } ++ ++ /*CamOsDebug("%s 0x%08X 0x%08X 0x%08X\r\n", ++ __FUNCTION__, ++ (u32)*ppUserPtr, ++ (u32)*lpPhysAddr, ++ (u32)*pMiuAddr);*/ ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ MemoryList_t* ptNewEntry = (MemoryList_t*) MsAllocateMem(sizeof(MemoryList_t)); ++ ptNewEntry->pPtr = *ppUserPtr; ++ ptNewEntry->pMemifoPtr = NULL; ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysFd = -1; ++ s32 nMemFd = -1; ++ MSYS_DMEM_INFO * ptMsysMem = NULL; ++ unsigned char* pMmapPtr = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ fprintf(stderr, "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ break; ++ } ++ ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/mem failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ ptMsysMem = (MSYS_DMEM_INFO *) malloc(sizeof(MSYS_DMEM_INFO)); ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ FILL_VERCHK_TYPE(*ptMsysMem, ptMsysMem->VerChk_Version, ++ ptMsysMem->VerChk_Size, IOCTL_MSYS_VERSION); ++ ++ ptMsysMem->length = nSize; ++ snprintf(ptMsysMem->name, sizeof(ptMsysMem->name), "%s", szName); ++ ++ if(ioctl(nMsysFd, IOCTL_MSYS_REQUEST_DMEM, ptMsysMem)) ++ { ++ ptMsysMem->length = 0; ++ fprintf(stderr, "%s [%s][%d]Request Direct Memory Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ tAddrInfo.addr = ptMsysMem->phys; ++ *lpPhysAddr = ptMsysMem->phys; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s [%s][%d]IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ *pMiuAddr = tAddrInfo.addr; ++ pMmapPtr = mmap(0, ptMsysMem->length, PROT_READ | PROT_WRITE, MAP_SHARED, ++ nMemFd, ptMsysMem->phys); ++ if(pMmapPtr == (void *) - 1) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s failed!! physAddr<0x%x> size<0x%x> errno<%d, %s> \r\n", ++ __FUNCTION__, ++ (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length, errno, strerror(errno)); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ *ppUserPtr = pMmapPtr; ++ ++ fprintf(stderr, "%s <%s> physAddr<0x%x> size<%d> \r\n", ++ __FUNCTION__, ++ szName, (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ MemoryList_t* tpNewEntry = (MemoryList_t*) malloc(sizeof(MemoryList_t)); ++ tpNewEntry->pPtr = pMmapPtr; ++ tpNewEntry->pMemifoPtr = (void *) ptMsysMem; ++ tpNewEntry->szName = strdup(szName); ++ CAM_OS_LIST_ADD_TAIL(&(tpNewEntry->tList), &_gtMemList.tList); ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++ if(nMemFd >= 0) ++ { ++ close(nMemFd); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *ptDmem = NULL; ++ MSYS_DMEM_INFO *ptDmemSearch = NULL; ++ MemoryList_t* ptNewEntry = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ ptDmemSearch = ptTmp->pMemifoPtr; ++ if(ptTmp->pPtr && ptDmemSearch && 0 == strcmp(szName, ptDmemSearch->name)) ++ { ++ printk(KERN_WARNING "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ break; ++ } ++ ++ if(0 == (ptDmem = (MSYS_DMEM_INFO *)kzalloc(sizeof(MSYS_DMEM_INFO), GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s kzalloc MSYS_DMEM_INFO fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ snprintf(ptDmem->name, sizeof(ptDmem->name), "%s", szName); ++ ptDmem->length = nSize; ++ ++ if(0 != msys_request_dmem(ptDmem)) ++ { ++ printk(KERN_WARNING "%s msys_request_dmem fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *ppUserPtr = (void *)(u32)ptDmem->phys; ++ *pMiuAddr = Chip_Phys_to_MIU(ptDmem->phys); ++ *lpPhysAddr = ptDmem->phys; ++ ++ printk(KERN_INFO "%s <%s> physAddr<0x%08X> size<%d> \r\n", ++ __FUNCTION__, ++ szName, (u32)ptDmem->phys, ++ (u32)ptDmem->length); ++ ++ mutex_lock(&_gtMemLock); ++ if(0 == (ptNewEntry = (MemoryList_t*) kzalloc(sizeof(MemoryList_t), GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s kzalloc MemoryList_t fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ptNewEntry->pPtr = (void *)(u32)ptDmem->phys; ++ ptNewEntry->pMemifoPtr = (void *) ptDmem; ++ ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if (eRet == CAM_OS_FAIL) ++ { ++ if (ptDmem) ++ { ++ if (ptDmem->phys) ++ { ++ msys_release_dmem(ptDmem); ++ } ++ kfree(ptDmem); ++ } ++ } ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemRelease(void* pUserPtr, u32 nSize) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++#ifdef CAM_OS_RTK ++ if(pUserPtr) ++ { ++ MsReleaseMemory(pUserPtr); ++ CamOsDebug("%s do release\n\r", __FUNCTION__); ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ MsReleaseMemory(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ MsReleaseMemory(ptTmp); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysfd = -1; ++ s32 nErr = 0; ++ MSYS_DMEM_INFO *pMsysMem = NULL; ++ ++ do ++ { ++ if(0 > (nMsysfd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ nErr = munmap(pUserPtr, nSize); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <%p> size<%d> err<%d> errno<%d, %s> \r\n", ++ __FUNCTION__, ++ pUserPtr, (u32)nSize, nErr, errno, strerror(errno)); ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ pMsysMem = (MSYS_DMEM_INFO *) ptTmp->pMemifoPtr; ++ break; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(pMsysMem == NULL) ++ { ++ fprintf(stderr, "%s find Msys_DMEM_Info node failed!! <%p> \r\n", __FUNCTION__, pUserPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(ioctl(nMsysfd, IOCTL_MSYS_RELEASE_DMEM, pMsysMem)) ++ { ++ fprintf(stderr, "%s : IOCTL_MSYS_RELEASE_DMEM error physAddr<0x%x>\n", __FUNCTION__, (u32)pMsysMem->phys); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ if(pMsysMem) ++ { ++ free(pMsysMem); ++ pMsysMem = NULL; ++ } ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ free(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ free(ptTmp); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysfd >= 0) ++ { ++ close(nMsysfd); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *tpDmem = NULL; ++ ++ do ++ { ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ //printk("search tmp->ptr: %08X %s\n", (u32)ptTmp->pPtr, ptTmp->szName); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ tpDmem = ptTmp->pMemifoPtr; ++ //printk("search(2) pdmem->name: %s\n", tpDmem->name); ++ break; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(tpDmem == NULL) ++ { ++ printk(KERN_WARNING "%s find Msys_DMEM_Info node failed!! <%p> \r\n", __FUNCTION__, pUserPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ msys_release_dmem(tpDmem); ++ ++ if(tpDmem) ++ { ++ kfree(tpDmem); ++ tpDmem = NULL; ++ } ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ CAM_OS_LIST_DEL(ptPos); ++ kfree(ptTmp); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemStat(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ MSYS_DMEM_INFO *ptDmemSearch = NULL; ++#ifdef CAM_OS_RTK ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ CamOsDebug("%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ fprintf(stderr, "%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ ptDmemSearch = ptTmp->pMemifoPtr; ++ if(ptTmp->pPtr && ptDmemSearch) ++ { ++ printk(KERN_WARNING "%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptDmemSearch->name); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++#endif ++ return eRet; ++} ++ ++u64 CamOsDirectMemPhysToMiu(u64 nAddr) ++{ ++#ifdef CAM_OS_RTK ++ return HalUtilPHY2MIUAddr(nAddr); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysFd = -1; ++ u32 nMiuAddr = 0; ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ ++ do ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ ++ tAddrInfo.addr = nAddr; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__); ++ break; ++ } ++ nMiuAddr = (u32)tAddrInfo.addr; ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++ ++ return nMiuAddr; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return Chip_Phys_to_MIU(nAddr); ++#endif ++} ++ ++u64 CamOsDirectMemMiuToPhys(u64 nAddr) ++{ ++#ifdef CAM_OS_RTK ++ return HalUtilMIU2PHYAddr(nAddr); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysFd = -1; ++ u32 nPhysAddr = 0; ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ ++ do ++ { ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ ++ tAddrInfo.addr = nAddr; ++ if(ioctl(nMsysFd, IOCTL_MSYS_MIU_TO_PHYS, &tAddrInfo)) ++ { ++ fprintf(stderr, "%s IOCTL_MSYS_MIU_TO_PHYS Failed!!\n", __FUNCTION__); ++ break; ++ } ++ nPhysAddr = (u32)tAddrInfo.addr; ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++ ++ return nPhysAddr; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return Chip_MIU_to_Phys(nAddr); ++#endif ++} ++ ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_set)(const char *szKey, const char *szValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error \n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set = dlsym(pLibHandle, "property_set"); ++ if(NULL == dlsym_property_set) ++ { ++ fprintf(stderr, "%s : dlsym property_set failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set(szKey, szValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsPropertyGet(const char *szKey, char *szValue, const char *szDefaultValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_get)(const char *szKey, char *szValue, const char *szDefaultValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error \n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ dlsym_property_get = dlsym(pLibHandle, "property_get"); ++ if(NULL == dlsym_property_get) ++ { ++ fprintf(stderr, "%s : dlsym property_get failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_get(szKey, szValue, szDefaultValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++u64 CamOsMathDivU64(u64 nDividend, u64 nDivisor, u64 *pRemainder) ++{ ++#ifdef CAM_OS_RTK ++ return div64_u64_rem(nDividend, nDivisor, pRemainder); ++#elif defined(CAM_OS_LINUX_USER) ++ *pRemainder = nDividend % nDivisor; ++ return nDividend / nDivisor; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return div64_u64_rem(nDividend, nDivisor, pRemainder); ++#endif ++} ++ ++s64 CamOsMathDivS64(s64 nDividend, s64 nDivisor, s64 *pRemainder) ++{ ++#ifdef CAM_OS_RTK ++ s64 nQuotient = div64_s64(nDividend, nDivisor); ++ *pRemainder = nDividend - nDivisor * nQuotient; ++ return nQuotient; ++#elif defined(CAM_OS_LINUX_USER) ++ *pRemainder = nDividend % nDivisor; ++ return nDividend / nDivisor; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ s64 nQuotient = div64_s64(nDividend, nDivisor); ++ *pRemainder = nDividend - nDivisor * nQuotient; ++ return nQuotient; ++#endif ++} ++ ++CamOsMemSize_e CamOsPhysMemSize(void) ++{ ++#ifdef CAM_OS_RTK ++ return (CamOsMemSize_e)((*(volatile u32 *)(RIU_BASE_ADDR + RIU_MEM_SIZE_OFFSET) & 0xF000) >> 12); ++#elif defined(CAM_OS_LINUX_USER) ++ void *map_addr = 0; ++ s32 nMemFd = -1; ++ u32 nRegs = 0; ++ u32 nPageSize; ++ ++ nPageSize = getpagesize(); ++ ++ do ++ { ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ CamOsDebug("%s open /dev/mem failed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ map_addr = mmap(0, nPageSize, PROT_READ|PROT_WRITE, MAP_SHARED , nMemFd, (RIU_BASE_ADDR + RIU_MEM_SIZE_OFFSET) & ~(nPageSize - 1)); ++ ++ if(map_addr == MAP_FAILED) ++ { ++ CamOsDebug("%s mmap failed!!\n", __FUNCTION__); ++ break; ++ } ++ else ++ { ++ nRegs = *(u32 *)(map_addr + RIU_MEM_SIZE_OFFSET%nPageSize); ++ if (munmap(map_addr, nPageSize)) ++ { ++ CamOsDebug("%s: mumap %p is error(%s)\n", __func__, map_addr, strerror(errno)); ++ } ++ } ++ } ++ while(0); ++ ++ if(nMemFd >= 0) ++ { ++ close(nMemFd); ++ } ++ ++ CamOsDebug("CamOsPhysMemSize: %d\n", (nRegs & 0xF000) >> 12); ++ ++ return (CamOsMemSize_e)((nRegs & 0xF000) >> 12); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsMemSize_e eMemSize; ++ void *pRegs; ++ ++ pRegs = ioremap(RIU_BASE_ADDR + RIU_MEM_SIZE_OFFSET, 4); ++ eMemSize = (CamOsMemSize_e)((readl(pRegs) & 0xF000)>>12); ++ iounmap(pRegs); ++ ++ return eMemSize; ++#endif ++} ++ ++u32 CamOsChipId(void) ++{ ++#ifdef CAM_OS_RTK ++ return *(volatile u32 *)(RIU_BASE_ADDR + RIU_CHIP_ID_OFFSET) & 0x3FFFFF; ++#elif defined(CAM_OS_LINUX_USER) ++ void *map_addr = 0; ++ s32 nMemFd = -1; ++ u32 nRegs = 0; ++ u32 nPageSize; ++ ++ nPageSize = getpagesize(); ++ ++ do ++ { ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ CamOsDebug("%s open /dev/mem failed!!\n", __FUNCTION__); ++ break; ++ } ++ ++ map_addr = mmap(0, nPageSize, PROT_READ|PROT_WRITE, MAP_SHARED , nMemFd, (RIU_BASE_ADDR + RIU_CHIP_ID_OFFSET) & ~(nPageSize - 1)); ++ ++ if(map_addr == MAP_FAILED) ++ { ++ CamOsDebug("%s mmap failed!!\n", __FUNCTION__); ++ break; ++ } ++ else ++ { ++ nRegs = *(u32 *)(map_addr + RIU_CHIP_ID_OFFSET%nPageSize); ++ if (munmap(map_addr, nPageSize)) ++ { ++ CamOsDebug("%s: mumap %p is error(%s)\n", __func__, map_addr, strerror(errno)); ++ } ++ } ++ } ++ while(0); ++ ++ if(nMemFd >= 0) ++ { ++ close(nMemFd); ++ } ++ ++ CamOsDebug("CamOsPhysMemSize: %d\n", nRegs & 0x3FFFFF); ++ ++ return nRegs & 0x3FFFFF; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ u32 nId; ++ void *pRegs; ++ ++ pRegs = ioremap(RIU_BASE_ADDR + RIU_CHIP_ID_OFFSET, 4); ++ nId = readl(pRegs) & 0x3FFFFF; ++ iounmap(pRegs); ++ ++ return nId; ++#endif ++} +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/test/Makefile b/drivers/mstar/cam_os_wrapper/test/Makefile +new file mode 100644 +index 00000000..21df00b8 +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/test/Makefile +@@ -0,0 +1,19 @@ ++obj-m := linux_ktest.o ++linux_ktest-objs := ../src/cam_os_wrapper.o cam_os_wrapper_linux_kernel_test.o ++ ++export ARCH=arm ++export CROSS_COMPILE=arm-linux-gnueabihf- ++ ++KERNEL = ../../../../ ++CC = $(CROSS_COMPILE)gcc ++APP = cam_os_wrapper_linux_ktest ++EXTRA_CFLAGS := -Idrivers/mstar/cam_os_wrapper/pub -Idrivers/mstar/include/ ++ ++all: ++ make modules -C $(KERNEL) M=`pwd` ++ #$(CROSS_COMPILE)strip -g cam_os_wrapper_linux_ktest.ko ++ #$(CC) $(APP).c -o $(APP) ++ ++clean: ++ make modules clean -C $(KERNEL) M=`pwd` ++ rm -rf $(APP) +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/test/cam_os_wrapper_linux_kernel_test.c b/drivers/mstar/cam_os_wrapper/test/cam_os_wrapper_linux_kernel_test.c +new file mode 100644 +index 00000000..e67a18a1 +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/test/cam_os_wrapper_linux_kernel_test.c +@@ -0,0 +1,392 @@ ++/* ++ * cam_os_wrapper_linux_kernel_test.c ++ * ++ * Created on: Apr. 5, 2017 ++ * Author: jeff-cl.lin ++ */ ++#include ++#include ++#include "cam_os_wrapper.h" ++#include ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("MStar Kernel Wrapper Test"); ++MODULE_LICENSE("GPL"); ++ ++#define TEST_TIME_AND_SLEEP ++#define TEST_DIRECT_MEMORY ++#define TEST_SEMAPHORE ++#define TEST_MUTEX ++#define TEST_DIV64 ++#define TEST_SYSTEM_TIME ++#define TEST_MEM_SIZE ++#define TEST_CHIP_ID ++ ++#ifdef TEST_TIME_AND_SLEEP ++static CamOsThread tThread0; ++static int ThreadTestTimeMsleep(void *pArg) ++{ ++ CamOsTimespec_t tTime; ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ ++ CamOsGetMonotonicTime(&tTime); ++ CamOsDebug("%s time: %lu.%06lu\n", __FUNCTION__, tTime.nSec, tTime.nNanoSec); ++ CamOsMsSleep(1000); ++ } ++ CamOsDebug("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_SEMAPHORE ++static CamOsThread tThread1, tThread2; ++CamOsTsem_t tSem; ++static int ThreadTestTsem1(void *pArg) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pArg; ++ CamOsRet_e eRet; ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsDebug("%s TsemWait start\n", __FUNCTION__); ++ CamOsTsemWait(pSem); ++ CamOsDebug("%s TsemWait end\n", __FUNCTION__); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s Tsem Value: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ ++ CamOsMsSleep(14000); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(1000); ++ ++ CamOsDebug("%s TsemTimedWait start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedWait(pSem, 3000); ++ CamOsDebug("%s TsemTimedWait end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ CamOsDebug("%s TsemTimedWait start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedWait(pSem, 10000); ++ CamOsDebug("%s TsemTimedWait end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ CamOsDebug("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static int ThreadTestTsem2(void *pArg) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pArg; ++ CamOsRet_e eRet; ++ ++ CamOsDebug("%s TsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemDown end\n", __FUNCTION__); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemSignal\n", __FUNCTION__); ++ CamOsTsemSignal(pSem); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemDown\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemDown\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemDown\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s Tsem Value: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s Tsem Value: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ CamOsDebug("%s TsemReset\n", __FUNCTION__); ++ CamOsTsemReset(pSem); ++ CamOsDebug("%s Tsem Value: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsDebug("%s TsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ CamOsDebug("%s TsemTimedDown start\n", __FUNCTION__); ++ eRet = CamOsTsemTimedDown(pSem, 10000); ++ CamOsDebug("%s TsemTimedDown end (%s)\n", __FUNCTION__, (eRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ CamOsMsSleep(6000); ++ ++ CamOsDebug("%s TsemSignal\n", __FUNCTION__); ++ CamOsTsemSignal(pSem); ++ ++ for(;;) ++ { ++ if(CAM_OS_OK == CamOsThreadShouldStop()) break; ++ CamOsMsSleep(100); ++ } ++ CamOsDebug("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++#ifdef TEST_MUTEX ++CamOsThread tTaskHandle0, tTaskHandle1, tTaskHandle2; ++CamOsThreadAttrb_t tAttr; ++CamOsMutex_t tCamOsMutex; ++static u32 nMutexTestCnt = 0; ++ ++static void CamOsMutexTestEntry0(void *pUserData) ++{ ++ CamOsMutex_t *tpMutex = (CamOsMutex_t *)pUserData; ++ unsigned int i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ CamOsMutexLock(tpMutex); ++ nMutexTestCnt++; ++ CamOsDebug("%s start count: %d\n\r", __FUNCTION__, nMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsDebug("%s end count: %d\n\r", __FUNCTION__, nMutexTestCnt); ++ CamOsMutexUnlock(tpMutex); ++ } ++} ++ ++static void CamOsMutexTestEntry1(void *pUserData) ++{ ++ CamOsMutex_t *tpMutex = (CamOsMutex_t *)pUserData; ++ unsigned int i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ CamOsMutexLock(tpMutex); ++ nMutexTestCnt++; ++ CamOsDebug("%s start count: %d\n\r", __FUNCTION__, nMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsDebug("%s end count: %d\n\r", __FUNCTION__, nMutexTestCnt); ++ CamOsMutexUnlock(tpMutex); ++ } ++} ++ ++static void CamOsMutexTestEntry2(void *pUserData) ++{ ++ CamOsMutex_t *tpMutex = (CamOsMutex_t *)pUserData; ++ unsigned int i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ CamOsMutexLock(tpMutex); ++ nMutexTestCnt++; ++ CamOsDebug("%s start count: %d\n\r", __FUNCTION__, nMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsDebug("%s end count: %d\n\r", __FUNCTION__, nMutexTestCnt); ++ CamOsMutexUnlock(tpMutex); ++ } ++} ++ ++#endif ++ ++static int __init KernelTestInit(void) ++{ ++#ifdef TEST_DIV64 ++ u64 nDividendU64 = 0, nDivisorU64 = 0, nResultU64 = 0, nRemainderU64 = 0; ++ s64 nDividendS64 = 0, nDivisorS64 = 0, nResultS64 = 0, nRemainderS64 = 0; ++#endif ++#ifdef TEST_SYSTEM_TIME ++ s32 nCnt = 0; ++ CamOsTimespec_t tTs; ++ struct rtc_time tTm; ++#endif ++#ifdef TEST_MEM_SIZE ++ CamOsMemSize_e eMemSize; ++#endif ++ ++#ifdef TEST_DIRECT_MEMORY ++ void *pUserPtr1 = 0, *pUserPtr2 = 0, *pUserPtr3 = 0; ++ u64 nMiuAddr = 0; ++ u64 nPhysAddr = 0; ++ ++ CamOsDebug(KERN_INFO "Test DirectMem start\n"); ++ CamOsDirectMemAlloc("AAAAA", 1024, &pUserPtr1, &nMiuAddr, &nPhysAddr); ++ CamOsDebug(KERN_INFO " UserAddr: 0x%08X\n", (u32)pUserPtr1); ++ CamOsDebug(KERN_INFO " MiuAddr: 0x%08X\n", (u32)CamOsDirectMemPhysToMiu(nPhysAddr)); ++ CamOsDebug(KERN_INFO " PhysAddr: 0x%08X\n", (u32)CamOsDirectMemMiuToPhys(nMiuAddr)); ++ ++ CamOsDirectMemAlloc("BBBBB", 2048, &pUserPtr2, &nMiuAddr, &nPhysAddr); ++ CamOsDebug(KERN_INFO " UserAddr: 0x%08X\n", (u32)pUserPtr2); ++ CamOsDebug(KERN_INFO " MiuAddr: 0x%08X\n", (u32)CamOsDirectMemPhysToMiu(nPhysAddr)); ++ CamOsDebug(KERN_INFO " PhysAddr: 0x%08X\n", (u32)CamOsDirectMemMiuToPhys(nMiuAddr)); ++ ++ CamOsDirectMemAlloc("CCCCC", 2048, &pUserPtr3, &nMiuAddr, &nPhysAddr); ++ CamOsDebug(KERN_INFO " UserAddr: 0x%08X\n", (u32)pUserPtr3); ++ CamOsDebug(KERN_INFO " MiuAddr: 0x%08X\n", (u32)CamOsDirectMemPhysToMiu(nPhysAddr)); ++ CamOsDebug(KERN_INFO " PhysAddr: 0x%08X\n", (u32)CamOsDirectMemMiuToPhys(nMiuAddr)); ++ ++ CamOsDebug(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsDebug(KERN_INFO "Release DMEM BBBBB\n"); ++ CamOsDirectMemRelease(pUserPtr2, 2048); ++ ++ CamOsDebug(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsDebug(KERN_INFO "Release DMEM AAAAA\n"); ++ CamOsDirectMemRelease(pUserPtr1, 1024); ++ ++ CamOsDebug(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsDebug(KERN_INFO "Release DMEM CCCCC\n"); ++ CamOsDirectMemRelease(pUserPtr3, 2048); ++ ++ CamOsDebug(KERN_INFO "List DMEM Status\n"); ++ CamOsDirectMemStat(); ++ ++ CamOsDebug(KERN_INFO "Test DirectMem end\n"); ++#endif ++ ++#ifdef TEST_TIME_AND_SLEEP ++ CamOsThreadCreate(&tThread0, NULL, (void *)ThreadTestTimeMsleep, NULL); ++ CamOsMsSleep(10000); ++ CamOsThreadStop(tThread0); ++#endif ++ ++#ifdef TEST_SEMAPHORE ++ CamOsTsemInit(&tSem, 0); ++ CamOsThreadCreate(&tThread1, NULL, (void *)ThreadTestTsem1, &tSem); ++ CamOsThreadCreate(&tThread2, NULL, (void *)ThreadTestTsem2, &tSem); ++#endif ++ ++#ifdef TEST_MUTEX ++ CamOsMutexInit(&tCamOsMutex); ++ tAttr.nPriority = 1; ++ tAttr.nStackSize = 3072; ++ CamOsThreadCreate(&tTaskHandle0, &tAttr, (void *)CamOsMutexTestEntry0, &tCamOsMutex); ++ tAttr.nPriority = 10; ++ tAttr.nStackSize = 3072; ++ CamOsThreadCreate(&tTaskHandle1, &tAttr, (void *)CamOsMutexTestEntry1, &tCamOsMutex); ++ tAttr.nPriority = 20; ++ tAttr.nStackSize = 3072; ++ CamOsThreadCreate(&tTaskHandle2, &tAttr, (void *)CamOsMutexTestEntry2, &tCamOsMutex); ++ CamOsMutexDestroy(&tCamOsMutex); ++#endif ++ ++#ifdef TEST_DIV64 ++ nDividendU64 = 858993459978593; ++ nDivisorU64 = 34358634759; ++ nResultU64 = CamOsMathDivU64(nDividendU64, nDivisorU64, &nRemainderU64); ++ CamOsDebug("Dividend: %llu Divisor: %llu Result: %llu Remainder: %llu\n", ++ nDividendU64, nDivisorU64, nResultU64, nRemainderU64); ++ ++ nDividendS64 = -858993459978593; ++ nDivisorS64 = 34358634759; ++ nResultS64 = CamOsMathDivS64(nDividendS64, nDivisorS64, &nRemainderS64); ++ CamOsDebug("Dividend: %lld Divisor: %lld Result: %lld Remainder: %lld\n", ++ nDividendS64, nDivisorS64, nResultS64, nRemainderS64); ++ ++ nDividendS64 = 858993459978593; ++ nDivisorS64 = -34358634759; ++ nResultS64 = CamOsMathDivS64(nDividendS64, nDivisorS64, &nRemainderS64); ++ CamOsDebug("Dividend: %lld Divisor: %lld Result: %lld Remainder: %lld\n", ++ nDividendS64, nDivisorS64, nResultS64, nRemainderS64); ++ ++ nDividendS64 = -858993459978593; ++ nDivisorS64 = -34358634759; ++ nResultS64 = CamOsMathDivS64(nDividendS64, nDivisorS64, &nRemainderS64); ++ CamOsDebug("Dividend: %lld Divisor: %lld Result: %lld Remainder: %lld\n", ++ nDividendS64, nDivisorS64, nResultS64, nRemainderS64); ++#endif ++ ++#ifdef TEST_SYSTEM_TIME ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ rtc_time_to_tm(tTs.nSec, &tTm); ++ CamOsDebug("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm.tm_year+1900, ++ tTm.tm_mon+1, ++ tTm.tm_mday, ++ tTm.tm_wday, ++ tTm.tm_hour, ++ tTm.tm_min, ++ tTm.tm_sec); ++ ++ tTs.nSec += 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++ ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ rtc_time_to_tm(tTs.nSec, &tTm); ++ CamOsDebug("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm.tm_year+1900, ++ tTm.tm_mon+1, ++ tTm.tm_mday, ++ tTm.tm_wday, ++ tTm.tm_hour, ++ tTm.tm_min, ++ tTm.tm_sec); ++ ++ tTs.nSec -= 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++#endif ++ ++#ifdef TEST_MEM_SIZE ++ eMemSize = CamOsPhysMemSize(); ++ CamOsDebug("System has %dMB physical memory\n", 1<<(u32)eMemSize); ++#endif ++ ++#ifdef TEST_CHIP_ID ++ CamOsDebug("Chip ID: 0x%X\n", CamOsChipId()); ++#endif ++ ++ return 0; ++} ++ ++static void __exit KernelTestExit(void) ++{ ++#ifdef TEST_SEMAPHORE ++ CamOsThreadStop(tThread1); ++ CamOsThreadStop(tThread2); ++#endif ++ ++#ifdef TEST_MUTEX ++ CamOsThreadStop(tTaskHandle0); ++ CamOsThreadStop(tTaskHandle1); ++ CamOsThreadStop(tTaskHandle2); ++#endif ++ CamOsDebug(KERN_INFO "Goodbye\n"); ++} ++ ++module_init(KernelTestInit); ++module_exit(KernelTestExit); +\ No newline at end of file +diff --git a/drivers/mstar/cam_os_wrapper/test/cam_os_wrapper_test.c b/drivers/mstar/cam_os_wrapper/test/cam_os_wrapper_test.c +new file mode 100644 +index 00000000..5fbdfdcf +--- /dev/null ++++ b/drivers/mstar/cam_os_wrapper/test/cam_os_wrapper_test.c +@@ -0,0 +1,492 @@ ++/* ++ * cam_os_wrapper_test.c ++ * ++ * Created on: Mar 20, 2017 ++ * Author: giggs.huang ++ */ ++ ++#include ++#include ++#include "sys_sys_core.h" ++#include "sys_sys_isw_cli.h" ++#include "cam_os_wrapper.h" ++#include ++ ++static u32 _gMutexTestCnt = 0; ++ ++static void _TestCamOsThread(void); ++static void _TestCamOsMutex(void); ++static void _TestCamOsDmem(void); ++static void _TestCamOsMem(void); ++static void _TestCamOsTimer(void); ++static void _TestCamOsTsem(void); ++static void _TestCamOsDiv64(void); ++static void _TestCamOsSystemTime(void); ++static void _TestCamOsPhysMemSize(void); ++static void _TestCamOsChipId(void); ++ ++s32 CamOsWrapperTest(CLI_t *pCli, char *p) ++{ ++ s32 i, nParamCnt, nRet = -1; ++ u32 nCaseNum = 0; ++ char *pEnd; ++ ++ ++ nParamCnt = CliTokenCount(pCli); ++ ++ if(nParamCnt < 1) ++ { ++ return eCLI_PARSE_INPUT_ERROR; ++ } ++ ++ for(i = 0; i < nParamCnt; i++) ++ { ++ pCli->tokenLvl++; ++ p = CliTokenPop(pCli); ++ if(i == 0) ++ { ++ //CLIDEBUG(("p: %s, len: %d\n", p, strlen(p))); ++ //*pV = _strtoul(p, &pEnd, base); ++ nCaseNum = strtoul(p, &pEnd, 10); ++ //CLIDEBUG(("*pEnd = %d\n", *pEnd)); ++ if(p == pEnd || *pEnd) ++ { ++ CamOsDebug("Invalid input\n"); ++ return eCLI_PARSE_ERROR; ++ } ++ } ++ } ++ ++ switch(nCaseNum) ++ { ++ case 1: ++ _TestCamOsThread(); ++ break; ++ case 2: ++ _TestCamOsMutex(); ++ break; ++ case 3: ++ _TestCamOsDmem(); ++ break; ++ case 4: ++ _TestCamOsMem(); ++ break; ++ case 5: ++ _TestCamOsTimer(); ++ break; ++ case 6: ++ _TestCamOsTsem(); ++ break; ++ case 7: ++ _TestCamOsDiv64(); ++ break; ++ case 8: ++ _TestCamOsSystemTime(); ++ break; ++ case 9: ++ _TestCamOsPhysMemSize(); ++ break; ++ case 10: ++ _TestCamOsChipId(); ++ break; ++ default: ++ nRet = -1; ++ } ++ ++ if(nRet < 0) ++ return eCLI_PARSE_ERROR; ++ ++ return eCLI_PARSE_OK; ++} ++ ++static void _CamOsThreadTestEntry0(void *pUserdata) ++{ ++ s32 *pnArg = (s32 *)pUserdata; ++ s32 i = 0; ++ ++ for(i = 0; i < 5; i++) ++ { ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry0 (sleep %dms) count: %d\n", __LINE__, *pnArg, i); ++ CamOsMsSleep(*pnArg); ++ } ++} ++ ++static void _TestCamOsThread(void) ++{ ++ CamOsThread TaskHandle0, TaskHandle1; ++ CamOsThreadAttrb_t tAttr; ++ s32 nTaskArg0 = 1000, nTaskArg1 = 1500; ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle0, &tAttr, (void *)_CamOsThreadTestEntry0, (void *)&nTaskArg0); ++ //CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread get taskid: %d\n", __LINE__, TaskHandle0.eHandleObj); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle1, &tAttr, (void *)_CamOsThreadTestEntry0, (void *)&nTaskArg1); ++ //CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread get taskid: %d\n", __LINE__, TaskHandle1.eHandleObj); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread delete task\n", __LINE__); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsThread test end!!!\n", __LINE__); ++} ++ ++static void _CamOsMutexTestEntry0(void *pUserdata) ++{ ++ CamOsMutex_t *ptMutex = (CamOsMutex_t *)pUserdata; ++ u32 i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ CamOsMutexLock(ptMutex); ++ _gMutexTestCnt++; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry0 start count: %d\n", __LINE__, _gMutexTestCnt); ++ CamOsMsSleep(3); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry0 end count: %d%s\n", __LINE__, _gMutexTestCnt); ++ CamOsMutexUnlock(ptMutex); ++ } ++} ++ ++static void _CamOsMutexTestEntry1(void *pUserdata) ++{ ++ CamOsMutex_t *ptMutex = (CamOsMutex_t *)pUserdata; ++ u32 i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ CamOsMutexLock(ptMutex); ++ _gMutexTestCnt++; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry1 start count: %d\n", __LINE__, _gMutexTestCnt); ++ CamOsMsSleep(2); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry1 end count: %d\n", __LINE__, _gMutexTestCnt); ++ CamOsMutexUnlock(ptMutex); ++ } ++} ++ ++static void _CamOsMutexTestEntry2(void *pUserdata) ++{ ++ CamOsMutex_t *ptMutex = (CamOsMutex_t *)pUserdata; ++ u32 i = 0; ++ ++ for(i = 0; i < 100; i++) ++ { ++ CamOsMutexLock(ptMutex); ++ _gMutexTestCnt++; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry2 start count: %d\n", __LINE__, _gMutexTestCnt); ++ CamOsMsSleep(5); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _CamOsThreadTestEntry2 end count: %d\n", __LINE__, _gMutexTestCnt); ++ CamOsMutexUnlock(ptMutex); ++ } ++} ++ ++static void _TestCamOsMutex(void) ++{ ++ CamOsThread TaskHandle0, TaskHandle1, TaskHandle2; ++ CamOsThreadAttrb_t tAttr; ++ CamOsMutex_t tCamOsMutex; ++ ++ CamOsMutexInit(&tCamOsMutex); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle0, &tAttr, (void *)_CamOsMutexTestEntry0, &tCamOsMutex); ++ ++ tAttr.nPriority = 50; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle1, &tAttr, (void *)_CamOsMutexTestEntry1, &tCamOsMutex); ++ ++ tAttr.nPriority = 100; ++ tAttr.nStackSize = 0; ++ CamOsThreadCreate(&TaskHandle2, &tAttr, (void *)_CamOsMutexTestEntry2, &tCamOsMutex); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++ CamOsThreadJoin(TaskHandle2); ++ ++ CamOsMutexDestroy(&tCamOsMutex); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsMutex delete task\n", __LINE__); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsMutex test end!!!\n", __LINE__); ++} ++ ++static void _TestCamOsDmem(void) ++{ ++ void *pUserPtr = NULL; ++ u64 nMiuAddr = 0; ++ u64 nPhysAddr = 0; ++ ++ CamOsDirectMemAlloc("TESTDMEM", 1025, &pUserPtr, &nMiuAddr, &nPhysAddr); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsDirectMemAlloc get addr: pUserPtr 0x%08X nMiuAddr 0x%08X nPhysAddr 0x%08X\n", ++ __LINE__, (u32)pUserPtr, (u32)nMiuAddr, (u32)nPhysAddr); ++ ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: write cached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)nPhysAddr, 0x12345678); ++ *(u32 *)(u32)nPhysAddr = 0x12345678; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read cached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)nPhysAddr, *(u32 *)(u32)nPhysAddr); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: write uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pUserPtr, 0x87654321); ++ *(u32 *)pUserPtr = 0x87654321; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read cached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)nPhysAddr, *(u32 *)(u32)nPhysAddr); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: flush cached ptr=0x%x\n", __LINE__, (u32)nPhysAddr); ++ sys_flush_data_cache_buffer((u32)nPhysAddr, 1025); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read cached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)nPhysAddr, *(u32 *)(u32)nPhysAddr); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsDmem: read uncached ptr=0x%x, value = 0x%x\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsDirectMemRelease((u8 *)pUserPtr, 1025); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d]_TestCamOsDmem test end!!!\n", __LINE__); ++} ++ ++static void _TestCamOsMem(void) ++{ ++ void *pUserPtr = NULL; ++ ++ // test CamOsMemAlloc ++ pUserPtr = CamOsMemAlloc(2048); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsMemAlloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ memset(pUserPtr, 0x5A, 2048); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] value in address 0x%08X is 0x%08X\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsMemRelease(pUserPtr); ++ pUserPtr = NULL; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRelease free buffer\n", __LINE__); ++ ++ // test CamOsMemCalloc ++ pUserPtr = CamOsMemCalloc(2048, 1); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsMemCalloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] value in address 0x%08X is 0x%08X\n", __LINE__, (u32)pUserPtr, *(u32 *)pUserPtr); ++ ++ CamOsMemRelease(pUserPtr); ++ pUserPtr = NULL; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRelease free buffer\n", __LINE__); ++ ++ // test CamOsMemRealloc ++ pUserPtr = CamOsMemAlloc(2048); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CAM_OS_MemMalloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ pUserPtr = CamOsMemRealloc(pUserPtr, 4096); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRealloc get addr: pUserPtr 0x%08X\n", __LINE__, (u32)pUserPtr); ++ ++ CamOsMemRelease(pUserPtr); ++ pUserPtr = NULL; ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] CamOsMemRelease free buffer\n", __LINE__); ++ ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] _TestCamOsMem test end!!!\n", __LINE__); ++} ++ ++static void _TestCamOsTimer(void) ++{ ++ s32 nCnt = 0; ++ CamOsTimespec_t tTv = {0}, tTv_prev = {0}; ++ ++ for(nCnt = 0; nCnt <= 10; nCnt++) ++ { ++ CamOsGetMonotonicTime(&tTv); ++ CamOsDebug("[CAM_OS_WRAPPER_TEST:%d] rtk_os_time: %d.%09d diff: %d\n", __LINE__, tTv.nSec, tTv.nNanoSec, ++ (tTv.nSec - tTv_prev.nSec)*1000000+((s32)tTv.nNanoSec - (s32)tTv_prev.nNanoSec)/1000); ++ memcpy((void *)&tTv_prev, (void *)&tTv, sizeof(tTv)); ++ CamOsMsSleep(1000); ++ } ++} ++ ++static s32 _CamOsTsemTestEntry0(void *pArg) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pArg; ++ CamOsRet_e nRet; ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsDebug("%s TsemWait start\n", __FUNCTION__); ++ CamOsTsemWait(pSem); ++ CamOsDebug("%s TsemWait end\n", __FUNCTION__); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemValue: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ ++ CamOsMsSleep(14000); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ ++ CamOsMsSleep(1000); ++ ++ CamOsDebug("%s TsemTimedWait start\n", __FUNCTION__); ++ nRet = CamOsTsemTimedWait(pSem, 3000); ++ CamOsDebug("%s TsemTimedWait end (%s)\n", __FUNCTION__, (nRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ CamOsDebug("%s TsemTimedWait start\n", __FUNCTION__); ++ nRet = CamOsTsemTimedWait(pSem, 10000); ++ CamOsDebug("%s TsemTimedWait end (%s)\n", __FUNCTION__, (nRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ ++ CamOsDebug("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static s32 _CamOsTsemTestEntry1(void *pArg) ++{ ++ CamOsTsem_t *pSem = (CamOsTsem_t *)pArg; ++ CamOsRet_e nRet; ++ ++ CamOsDebug("%s TsemDown start\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemDown end\n", __FUNCTION__); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemSignal\n", __FUNCTION__); ++ CamOsTsemSignal(pSem); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemDown\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemDown\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemDown\n", __FUNCTION__); ++ CamOsTsemDown(pSem); ++ CamOsDebug("%s TsemValue: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemUp\n", __FUNCTION__); ++ CamOsTsemUp(pSem); ++ CamOsDebug("%s TsemValue: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ CamOsDebug("%s TsemReset\n", __FUNCTION__); ++ CamOsTsemReset(pSem); ++ CamOsDebug("%s TsemValue: %d\n", __FUNCTION__, CamOsTsemGetValue(pSem)); ++ ++ CamOsMsSleep(3000); ++ ++ CamOsDebug("%s TsemTimedDown start\n", __FUNCTION__); ++ nRet = CamOsTsemTimedDown(pSem, 3000); ++ CamOsDebug("%s TsemTimedDown end (%s)\n", __FUNCTION__, (nRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ CamOsDebug("%s TsemTimedDown start\n", __FUNCTION__); ++ nRet = CamOsTsemTimedDown(pSem, 10000); ++ CamOsDebug("%s TsemTimedDown end (%s)\n", __FUNCTION__, (nRet == CAM_OS_OK) ? "wakened" : "timeout"); ++ ++ CamOsMsSleep(6000); ++ ++ CamOsDebug("%s TsemSignal\n", __FUNCTION__); ++ CamOsTsemSignal(pSem); ++ ++ ++ CamOsDebug("%s break\n", __FUNCTION__); ++ ++ return 0; ++} ++ ++static void _TestCamOsTsem(void) ++{ ++ static CamOsThread TaskHandle0, TaskHandle1; ++ CamOsTsem_t tSem; ++ ++ CamOsTsemInit(&tSem, 0); ++ CamOsThreadCreate(&TaskHandle0, NULL, (void *)_CamOsTsemTestEntry0, &tSem); ++ CamOsThreadCreate(&TaskHandle1, NULL, (void *)_CamOsTsemTestEntry1, &tSem); ++ ++ CamOsThreadJoin(TaskHandle0); ++ CamOsThreadJoin(TaskHandle1); ++} ++ ++static void _TestCamOsDiv64(void) ++{ ++ u64 nDividendU64 = 0, nDivisorU64 = 0, nResultU64 = 0, nRemainderU64 = 0; ++ s64 nDividendS64 = 0, nDivisorS64 = 0, nResultS64 = 0, nRemainderS64 = 0; ++ ++ CamOsDebug("Unsigned 64 bit dividend:"); ++ CamOsScanf("%llu", &nDividendU64); ++ CamOsDebug("Unsigned 64 bit divisor:"); ++ CamOsScanf("%llu", &nDivisorU64); ++ ++ CamOsDebug("Directly: %llu / %llu = %llu remaind %llu\n", nDividendU64, nDivisorU64, nDividendU64 / nDivisorU64, nDividendU64 % nDivisorU64); ++ nResultU64 = CamOsMathDivU64(nDividendU64, nDivisorU64, &nRemainderU64); ++ CamOsDebug("By Div64: %llu / %llu = %llu remaind %llu\n", nDividendU64, nDivisorU64, nResultU64, nRemainderU64); ++ ++ ++ CamOsDebug("Signed 64 bit dividend:"); ++ CamOsScanf("%lld", &nDividendS64); ++ CamOsDebug("Signed 64 bit divisor:"); ++ CamOsScanf("%lld", &nDivisorS64); ++ ++ CamOsDebug("Directly: %lld / %lld = %lld remaind %lld\n", nDividendS64, nDivisorS64, nDividendS64 / nDivisorS64, nDividendS64 % nDivisorS64); ++ nResultS64 = CamOsMathDivS64(nDividendS64, nDivisorS64, &nRemainderS64); ++ CamOsDebug("By Div64: %lld / %lld = %lld remaind %lld\n", nDividendS64, nDivisorS64, nResultS64, nRemainderS64); ++} ++ ++static void _TestCamOsSystemTime(void) ++{ ++ s32 nCnt = 0; ++ CamOsTimespec_t tTs; ++ struct tm * tTm; ++ ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ tTm = localtime ((time_t *)&tTs.nSec); ++ CamOsDebug("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm->tm_year+1900, ++ tTm->tm_mon+1, ++ tTm->tm_mday, ++ tTm->tm_wday, ++ tTm->tm_hour, ++ tTm->tm_min, ++ tTm->tm_sec); ++ ++ tTs.nSec += 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++ ++ for(nCnt = 0; nCnt < 10; nCnt++) ++ { ++ CamOsGetTimeOfDay(&tTs); ++ tTm = localtime ((time_t *)&tTs.nSec); ++ CamOsDebug("RawSecond: %d -> %d/%02d/%02d [%d] %02d:%02d:%02d\n", ++ tTs.nSec, ++ tTm->tm_year+1900, ++ tTm->tm_mon+1, ++ tTm->tm_mday, ++ tTm->tm_wday, ++ tTm->tm_hour, ++ tTm->tm_min, ++ tTm->tm_sec); ++ ++ tTs.nSec -= 90000; ++ CamOsSetTimeOfDay(&tTs); ++ ++ CamOsMsSleep(3000); ++ } ++} ++ ++static void _TestCamOsPhysMemSize(void) ++{ ++ CamOsMemSize_e eMemSize; ++ eMemSize = CamOsPhysMemSize(); ++ CamOsDebug("System has %dMB physical memory\n", 1<<(u32)eMemSize); ++} ++ ++static void _TestCamOsChipId(void) ++{ ++ CamOsDebug("Chip ID: 0x%X\n", CamOsChipId()); ++} +\ No newline at end of file +diff --git a/drivers/mstar/clk/Kconfig b/drivers/mstar/clk/Kconfig +new file mode 100644 +index 00000000..92e78adf +--- /dev/null ++++ b/drivers/mstar/clk/Kconfig +@@ -0,0 +1,2 @@ ++config MS_USCLK ++ tristate "MS_USCLK extended sysfs interfaces for CLKs" +\ No newline at end of file +diff --git a/drivers/mstar/clk/Makefile b/drivers/mstar/clk/Makefile +new file mode 100644 +index 00000000..e7bef82e +--- /dev/null ++++ b/drivers/mstar/clk/Makefile +@@ -0,0 +1,7 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++obj-y += ms_composite_clk.o ++obj-$(CONFIG_MS_USCLK)=ms_usclk.o ++obj-$(CONFIG_ARCH_CEDRIC) += cedric/ ++obj-$(CONFIG_ARCH_INFINITY) += infinity/ ++obj-$(CONFIG_ARCH_INFINITY3) += infinity3/ +diff --git a/drivers/mstar/clk/cedric/Makefile b/drivers/mstar/clk/cedric/Makefile +new file mode 100644 +index 00000000..b1e0fa84 +--- /dev/null ++++ b/drivers/mstar/clk/cedric/Makefile +@@ -0,0 +1,5 @@ ++ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += clk.o +diff --git a/drivers/mstar/clk/cedric/clk.c b/drivers/mstar/clk/cedric/clk.c +new file mode 100644 +index 00000000..dcf1f99b +--- /dev/null ++++ b/drivers/mstar/clk/cedric/clk.c +@@ -0,0 +1,181 @@ ++/* ++ * ms_clk-cedric.c ++ * ++ * Created on: 2015�~5��4�� ++ * Author: Administrator ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cedric/irqs.h" ++#include "ms_platform.h" ++ ++ ++ ++#define PERI_PHYS 0x16000000 ++ ++ ++ ++static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) ++{ ++ ++ return (parent_rate>>1)*ms_readl(0x1F22184C); ++} ++ ++static const struct clk_ops clk_cpu_ops = { ++ .recalc_rate = clk_cpu_recalc_rate, ++// .round_rate = clk_cpu_round_rate, ++// .set_rate = clk_cpu_set_rate, ++}; ++ ++ ++ ++ ++#if defined(CONFIG_HAVE_ARM_TWD) ++#include ++DEFINE_TWD_LOCAL_TIMER(twd_local_timer, (PERI_PHYS+0x0600), GIC_ID_LOCAL_TIMER_IRQ); ++#endif ++ ++ ++static struct clk_onecell_data clk_cpu_data; ++static struct clk_hw clk_cpu_hw; ++static void __init ms_clk_cpu_of_init(struct device_node *node) ++{ ++ ++ struct clk_init_data init; ++ const char *parent_name; ++ ++ clk_cpu_data.clk_num=2; ++ clk_cpu_data.clks = kzalloc(clk_cpu_data.clk_num*sizeof(struct clk *),GFP_KERNEL); ++ BUG_ON(!clk_cpu_data.clks); ++ ++ parent_name = of_clk_get_parent_name(node, 0); ++ ++ clk_cpu_hw.init = &init; ++ init.ops = &clk_cpu_ops; ++ init.name=node->name; ++ init.parent_names = parent_name ? &parent_name : NULL; ++ init.num_parents = parent_name ? 1 : 0; ++ init.flags = (parent_name)? 0 : CLK_IS_ROOT; ++ ++ ++ clk_cpu_data.clks[0]=clk_register(NULL, &clk_cpu_hw);; ++ BUG_ON(IS_ERR(clk_cpu_data.clks[0])); ++ ++ ++ clk_cpu_data.clks[1]=clk_register_fixed_factor(NULL, "periclk", node->name, 0, 1, 2); ++ BUG_ON(IS_ERR(clk_cpu_data.clks[1])); ++ ++ ++ of_clk_add_provider(node, of_clk_src_onecell_get, &clk_cpu_data); ++ ++ ++// since we are not using GIC, need to register TWD manually ++#if defined(CONFIG_HAVE_ARM_TWD) ++ { ++ clk_register_clkdev(clk_cpu_data.clks[1], NULL, "smp_twd"); ++ ++ if (twd_local_timer_register(&twd_local_timer)) ++ { ++ pr_err("twd_local_timer_register failed!!!\n"); ++ } ++ else ++ { ++ pr_err("twd_local_timer_register success... \n"); ++ } ++ } ++ ++#endif ++} ++ ++static void __init ms_clk_uart_of_init(struct device_node *node) ++{ ++ struct clk *clk; ++ const char *clk_name = node->name; ++ int num_parents; ++ const char **parent_names; ++ struct clk_mux *mux = NULL; ++ struct clk_gate *gate = NULL; ++ void __iomem *reg; ++ unsigned int mux_width; ++ int i = 0; ++ ++ pr_info("%s: %s", __func__, clk_name); ++ ++ num_parents = of_clk_get_parent_count(node); ++ if (num_parents < 2) { ++ pr_err("%s: %s must have at least 2 parents\n", __func__, node->name); ++ return; ++ } ++ ++ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); ++ mux = kzalloc(sizeof(*mux), GFP_KERNEL); ++ gate = kzalloc(sizeof(*gate), GFP_KERNEL); ++ ++ if (!parent_names || !mux || !gate) ++ { ++ pr_err("%s: failed to allocate memory\n", __func__); ++ goto fail; ++ } ++ ++ for (i = 0; i < num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ reg = of_iomap(node, 0); ++ if (!reg) { ++ pr_err("%s: could not map region\n", __func__); ++ goto fail; ++ } ++ ++ mux->reg = reg; ++ if(of_property_read_u32(node, "mux-shift", (unsigned int *)&mux->shift)) ++ { ++ pr_err("%s: failed to read mux-shift\n", __func__); ++ mux->shift = 0; ++ } ++ if(of_property_read_u32(node, "mux-width", &mux_width)) ++ { ++ pr_err("%s: failed to read mux-width\n", __func__); ++ mux_width = 3; ++ } ++ mux->mask = BIT(mux_width) - 1; ++ //mux->flags = CLK_SET_RATE_PARENT; ++ ++ gate->reg = reg; ++ if(of_property_read_u32(node, "gate-shift", (unsigned int *)&gate->bit_idx)) ++ { ++ pr_err("%s: failed to read gate-shift\n", __func__); ++ gate->bit_idx = 0; ++ } ++ ++ pr_debug("%s: mux->reg=0x%08X\nmux->shift=%d\nmux->mask=0x%08X\n", __func__, (unsigned int)mux->reg, mux->shift, mux->mask); ++ ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ &mux->hw, &clk_mux_ops, ++ NULL, NULL, ++ &gate->hw, &clk_gate_ops, ++ 0); ++ ++ if (IS_ERR(clk)) ++ { ++ pr_err("%s: failed to register clock %s\n", __func__, clk_name); ++ goto fail; ++ } ++ ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, clk_name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(mux); ++ kfree(gate); ++ return; ++} ++ ++CLK_OF_DECLARE(cedric_uart_clk, "mstar,cedric-uartclk", ms_clk_uart_of_init); ++CLK_OF_DECLARE(cedric_cpu_clk, "mstar,cedric-cpuclk",ms_clk_cpu_of_init); +diff --git a/drivers/mstar/clk/infinity/Makefile b/drivers/mstar/clk/infinity/Makefile +new file mode 100644 +index 00000000..03b12f5d +--- /dev/null ++++ b/drivers/mstar/clk/infinity/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/mstar/clk/infinity/ms_complex_clk.c b/drivers/mstar/clk/infinity/ms_complex_clk.c +new file mode 100644 +index 00000000..8d6d1bf3 +--- /dev/null ++++ b/drivers/mstar/clk/infinity/ms_complex_clk.c +@@ -0,0 +1,467 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity/registers.h" ++ ++#if defined (CONFIG_MS_CPU_FREQ) && defined (CONFIG_MS_GPIO) ++extern u8 enable_scaling_voltage; ++#include "infinity/gpio.h" ++#include "../../gpio/mdrv_gpio.h" ++int bga_vid_0 = PAD_PM_GPIO7; ++int bga_vid_1 = PAD_PM_GPIO8; ++int qfp_vid_0 = PAD_SAR_GPIO3; ++/* */ ++/* for CUSTOMER */ ++/* _ _ _ _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | BGA(MHz)| VID_1 | VID_0 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 400-500 | 0 | 0 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 500-700 | 0 | 1 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 700-800 | 1 | 0 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | 800-1000| 1 | 1 | */ ++/* |_ _ _ _ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++#else ++u8 enable_scaling_voltage=0; ++#define MDrv_GPIO_Set_High(x) {} ++#define MDrv_GPIO_Set_Low(x) {} ++#define MDrv_GPIO_Pad_Set(x) {} ++int bga_vid_0 = -1; ++int bga_vid_1 = -1; ++int qfp_vid_0 = -1; ++#endif ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++static unsigned int ms_get_ddr_scl(void) ++{ ++ CLK_DBG("ms_get_ddr_scl = (0x%04X,0x%04X)\n", INREG16(0x1F206580), INREG16(0x1F206584)); ++ return (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate <= 500000000) //request 400M-500M=400M ++ return 400000000; ++ else if(rate <= 700000000) //request 500M-700M=600M ++ return 600000000; ++ else if(rate <= 800000000) //request 700M-800M=800M ++ return 800000000; ++ else //request 800M-1000M=1000M ++ return 1000000000; ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) * 12 * 524288; ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu\n", rate); ++ ++ return rate; ++} ++ ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ MS_PACKAGE_TYPE package = Chip_Get_Package_Type(); ++ ++// if(abs(rate - __clk_get_rate(clk_hw->clk)) < 100000000) //if it's the same setting, just return to save time ++// return 0; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ if(rate == 400000000) ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_Low(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_Low(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_Low(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0xAE14); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0067); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0xAE14); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0067); ++ } ++ else if(rate == 600000000) ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_High(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_Low(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_Low(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0x1EB8); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0045); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0x1EB8); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0045); ++ ++ } ++ else if(rate == 800000000) ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_Low(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_High(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_High(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0xD70A); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0033); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0xD70A); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0033); ++ ++ } ++ else ++ { ++ if(enable_scaling_voltage) ++ { ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_High(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_High(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_High(qfp_vid_0); ++ } ++ } ++ } ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), 0x78D4); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), 0x0029); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))) ); //polling done ++ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), 0x78D4); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), 0x0029); ++ ++ } ++ ++ return ret; ++} ++ ++void ms_cpuclk_dvfs_disable(void) ++{ ++ MS_PACKAGE_TYPE package = Chip_Get_Package_Type(); ++ ++ if(package == MS_PACKAGE_BGA || package == MS_PACKAGE_BGA_256M) ++ { ++ if(bga_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_0); ++ MDrv_GPIO_Set_Low(bga_vid_0); ++ } ++ if(bga_vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(bga_vid_1); ++ MDrv_GPIO_Set_Low(bga_vid_1); ++ } ++ } ++ else if(package == MS_PACKAGE_QFP || package == MS_PACKAGE_QFN) ++ { ++ if(qfp_vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(qfp_vid_0); ++ MDrv_GPIO_Set_Low(qfp_vid_0); ++ } ++ } ++} ++EXPORT_SYMBOL(ms_cpuclk_dvfs_disable); ++ ++struct clk_ops ms_cpuclk_ops = { ++ .round_rate = ms_cpuclk_round_rate, ++ .recalc_rate = ms_cpuclk_recalc_rate, ++ .set_rate = ms_cpuclk_set_rate, ++}; ++ ++static int ms_upll_utmi_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_enable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x00C0); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x01); ++ ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=0 ++ CLRREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=0 ++ return 0; ++} ++ ++static void ms_upll_utmi_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_disable\n\n"); ++ OUTREG16(BASE_REG_UPLL0_PA + REG_ID_00, 0x01B2); ++ OUTREG8(BASE_REG_UPLL0_PA + REG_ID_07, 0x02); ++ ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_00, BIT15); //reg_pdn=1 ++ SETREG16(BASE_REG_UTMI0_PA + REG_ID_04, BIT7); //pd_bg_current=1 ++} ++ ++static int ms_upll_utmi_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_upll_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UPLL0_PA + REG_ID_07) & BIT0); ++} ++ ++static unsigned long ms_upll_utmi_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ CLK_DBG("\nms_upll_utmi_recalc_rate, parent_rate=%d\n\n", parent_rate); ++ return (parent_rate * 40); ++} ++ ++ ++struct clk_ops ms_upll_utmi_ops = { ++ .enable = ms_upll_utmi_enable, ++ .disable = ms_upll_utmi_disable, ++ .is_enabled = ms_upll_utmi_is_enabled, ++ .recalc_rate = ms_upll_utmi_recalc_rate, ++}; ++ ++static int ms_usb_enable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_enable\n\n"); ++ ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0C2F); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x040F); //utmi0 ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x7F05); ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x0A); //Disable MAC initial suspend, Reset UHC ++ OUTREG8(BASE_REG_USB0_PA + REG_ID_00, 0x28); //Release UHC reset, enable UHC and OTG XIU function ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_11, 0x2088); //PLL_TEST[30:28]: 3'b101 for IBIAS current select ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_10, 0x8051); //PLL_TEST[15]: Bypass 480MHz clock divider ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_01, 0x2084); //Enable CLK12_SEL bit <2> for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s must have at least one parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register successfully\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "mstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/mstar/clk/infinity3/Makefile b/drivers/mstar/clk/infinity3/Makefile +new file mode 100644 +index 00000000..03b12f5d +--- /dev/null ++++ b/drivers/mstar/clk/infinity3/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/clk ++ ++obj-y += ms_complex_clk.o +diff --git a/drivers/mstar/clk/infinity3/ms_complex_clk.c b/drivers/mstar/clk/infinity3/ms_complex_clk.c +new file mode 100644 +index 00000000..931e1153 +--- /dev/null ++++ b/drivers/mstar/clk/infinity3/ms_complex_clk.c +@@ -0,0 +1,425 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity3/registers.h" ++ ++#if defined (CONFIG_MS_CPU_FREQ) && defined (CONFIG_MS_GPIO) ++extern u8 enable_scaling_voltage; ++#include "infinity3/gpio.h" ++#include "../../gpio/mdrv_gpio.h" ++int vid_0 = -1; ++int vid_1 = -1; ++#else ++u8 enable_scaling_voltage=0; ++#define MDrv_GPIO_Set_High(x) {} ++#define MDrv_GPIO_Set_Low(x) {} ++#define MDrv_GPIO_Pad_Set(x) {} ++int vid_0 = -1; ++int vid_1 = -1; ++#endif ++ ++#define CLK_DEBUG 0 ++ ++#if CLK_DEBUG ++#define CLK_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define CLK_DBG(fmt, arg...) ++#endif ++#define CLK_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++static unsigned int ms_get_ddr_scl(void) ++{ ++ unsigned int factor = INREG16(BASE_REG_RIU_PA + (0x1032A0 << 1)) | (((INREG16(BASE_REG_RIU_PA + (0x1032A2 << 1)) & 0xFF) <<16)); ++ ++ if(!factor) ++ factor = (INREG16(0x1F206580) | ((INREG16(0x1F206584) & 0xFF) << 16)); ++ ++ CLK_DBG("ms_get_ddr_scl = 0x%X\n", factor); ++ return factor; ++} ++ ++static long ms_cpuclk_round_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long *parent_rate) ++{ ++ //CLK_DBG("ms_cpuclk_round_rate = %lu\n", rate); ++ ++ if(rate <= 450000000) //request 400M-450M=400M ++ { ++ return 400000000; ++ } ++ else if(rate <= 650000000) //request 450M-650M=600M ++ { ++ return 600000000; ++ } ++ else if(rate <= 850000000) //request 650M-850M=800M ++ { ++ return 800000000; ++ } ++ else //request 850M-1000M=1000M ++ { ++ return 1000000000; ++ } ++} ++ ++static unsigned long ms_cpuclk_recalc_rate(struct clk_hw *clk_hw, unsigned long parent_rate) ++{ ++ unsigned long rate; ++ ++ rate = (parent_rate / ms_get_ddr_scl()) << 23; ++ ++ CLK_DBG("ms_cpuclk_recalc_rate = %lu, prate=%lu\n", rate, parent_rate); ++ ++ return rate; ++} ++ ++void cpu_dvfs(U32 u32TargetSet) ++{ ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A4 << 1), u32TargetSet&0xFFFF); //set target freq to LPF high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A6 << 1), (u32TargetSet>>16)&0xFFFF); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032B0 << 1), 0x0001); //switch to LPF control ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AA << 1), 0x0006); //mu[2:0] ++ OUTREG16(BASE_REG_RIU_PA + (0x1032AE << 1), 0x0008); //lpf_update_cnt[7:0] ++ SETREG16(BASE_REG_RIU_PA + (0x1032B2 << 1), BIT12); //from low to high ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); //toggle LPF enable ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0001); ++ while( !(INREG16(BASE_REG_RIU_PA + (0x1032BA << 1))&BIT0) ); //polling done ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A8 << 1), 0x0000); ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), u32TargetSet&0xFFFF); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), (u32TargetSet>>16)&0xFFFF); ++} ++ ++ ++ ++#define VOLTAGE_CORE_850 850 ++#define VOLTAGE_CORE_900 900 ++#define VOLTAGE_CORE_950 950 ++#define VOLTAGE_CORE_1000 1000 ++int g_sCurrentTemp = 35; ++int g_sCurrentTempThreshLo=35; ++int g_sCurrentTempThreshHi=50; ++int g_sCurrentVoltageCore=VOLTAGE_CORE_1000; ++void set_core_voltage (int vcore) ++{ ++ if(enable_scaling_voltage) ++ { ++ switch (vcore) ++ { ++ case VOLTAGE_CORE_850: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_850; ++ break; ++ ++ case VOLTAGE_CORE_900: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_Low(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_900; ++ break; ++ ++ case VOLTAGE_CORE_950: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_Low(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_950; ++ break; ++ ++ case VOLTAGE_CORE_1000: ++ if(vid_0 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_0); ++ MDrv_GPIO_Set_High(vid_0); ++ } ++ if(vid_1 != -1) ++ { ++ MDrv_GPIO_Pad_Set(vid_1); ++ MDrv_GPIO_Set_High(vid_1); ++ } ++ g_sCurrentVoltageCore = VOLTAGE_CORE_1000; ++ break; ++ ++ } ++ } ++ CLK_DBG("CurrentVoltageCore = %d\n", g_sCurrentVoltageCore); ++} ++static int ms_cpuclk_set_rate(struct clk_hw *clk_hw, unsigned long rate, unsigned long parent_rate) ++{ ++ int ret = 0; ++ ++// if(abs(rate - __clk_get_rate(clk_hw->clk)) < 100000000) //if it's the same setting, just return to save time ++// return 0; ++ ++ CLK_DBG("ms_cpuclk_set_rate = %lu\n", rate); ++ ++ if(rate == 1000000000) ++ { ++ set_core_voltage(VOLTAGE_CORE_1000); ++ cpu_dvfs(0x374BC7); ++ } ++ else ++ { ++ CLK_DBG("ms_get_temp = %d\n", g_sCurrentTemp); ++ #if 0 ++ if(g_sCurrentVoltageCore==VOLTAGE_CORE_1000 && g_sCurrentTemp>g_sCurrentTempThreshHi ) ++ set_core_voltage(VOLTAGE_CORE_900); ++ if(g_sCurrentVoltageCore==VOLTAGE_CORE_900 && g_sCurrentTemp for select low voltage crystal clock ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_04, 0x0426); //bit<7>: Power down UTMI port-0 bandgap current ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x6BC3); //reg_pdn: bit<15>, bit <2> ref_pdn # Turn on reference voltage and regulator ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x69C3); //Turn on UPLL, reg_pdn: bit<9> ++ //loop_delay_timer(TIMER_DELAY_100us); ++ OUTREG16(BASE_REG_UTMI0_PA + REG_ID_00, 0x0001); //Turn all (including hs_current) use override mode ++ return 0; ++} ++ ++static void ms_usb_disable(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_disable\n\n"); ++} ++ ++static int ms_usb_is_enabled(struct clk_hw *hw) ++{ ++ CLK_DBG("\nms_usb_is_enabled\n\n"); ++ return (INREG8(BASE_REG_UTMI0_PA + REG_ID_00) == 0x0001); ++} ++ ++struct clk_ops ms_usb_ops = { ++ .enable = ms_usb_enable, ++ .disable = ms_usb_disable, ++ .is_enabled = ms_usb_is_enabled, ++}; ++ ++ ++static void __init ms_clk_complex_init(struct device_node *node) ++{ ++ struct clk *clk; ++ struct clk_hw *clk_hw = NULL; ++ struct clk_init_data *init = NULL; ++ struct clk_ops *clk_ops =NULL; ++ const char **parent_names = NULL; ++ u32 i; ++ ++ clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); ++ init = kzalloc(sizeof(*init), GFP_KERNEL); ++ clk_ops = kzalloc(sizeof(*clk_ops), GFP_KERNEL); ++ if (!clk_hw || !init || !clk_ops) ++ goto fail; ++ ++ clk_hw->init = init; ++ init->name = node->name; ++ init->ops = clk_ops; ++ ++ //hook callback ops for cpuclk ++ if(!strcmp(node->name, "CLK_cpupll_clk")) ++ { ++ CLK_ERR("Find %s, hook ms_cpuclk_ops\n", node->name); ++ init->ops = &ms_cpuclk_ops; ++ } ++ else if(!strcmp(node->name, "CLK_utmi")) ++ { ++ CLK_ERR("Find %s, hook ms_upll_ops\n", node->name); ++ init->ops = &ms_upll_utmi_ops; ++ } ++ else if(!strcmp(node->name, "CLK_usb")) ++ { ++ CLK_ERR("Find %s, hook ms_usb_ops\n", node->name); ++ init->ops = &ms_usb_ops; ++ } ++ else ++ { ++ CLK_DBG("Find %s, but no ops\n", node->name); ++ } ++ ++ init->num_parents = of_clk_get_parent_count(node); ++ if (init->num_parents < 1) ++ { ++ CLK_ERR("[%s] %s must have at least one parent\n", __func__, node->name); ++ goto fail; ++ } ++ ++ parent_names = kzalloc(sizeof(char *) * init->num_parents, GFP_KERNEL); ++ if (!parent_names) ++ goto fail; ++ ++ for (i = 0; i < init->num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ init->parent_names = parent_names; ++ clk = clk_register(NULL, clk_hw); ++ if(IS_ERR(clk)) ++ { ++ CLK_ERR("[%s] Fail to register %s\n", __func__, node->name); ++ goto fail; ++ } ++ else ++ { ++ CLK_DBG("[%s] %s register successfully\n", __func__, node->name); ++ } ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, node->name, NULL); ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(clk_ops); ++ kfree(init); ++ kfree(clk_hw); ++} ++ ++CLK_OF_DECLARE(ms_clk_complex, "mstar,complex-clock", ms_clk_complex_init); +diff --git a/drivers/mstar/clk/ms_composite_clk.c b/drivers/mstar/clk/ms_composite_clk.c +new file mode 100644 +index 00000000..15eef8a7 +--- /dev/null ++++ b/drivers/mstar/clk/ms_composite_clk.c +@@ -0,0 +1,253 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_types.h" ++#include "ms_platform.h" ++ ++ ++struct ms_clk_mux { ++ struct clk_hw hw; ++ void __iomem *reg; ++ u32 *table; ++ u32 mask; ++ u8 shift; ++ u8 flags; ++ u8 glitch; //this is specific usage for MSTAR ++ spinlock_t *lock; ++}; ++ ++#define to_ms_clk_mux(_hw) container_of(_hw, struct ms_clk_mux, hw) ++ ++static u8 ms_clk_mux_get_parent(struct clk_hw *hw) ++{ ++ struct ms_clk_mux *mux = to_ms_clk_mux(hw); ++ int num_parents = __clk_get_num_parents(hw->clk); ++ u32 val; ++ ++ val = clk_readl(mux->reg) >> mux->shift; ++ val &= mux->mask; ++ ++ if (val >= num_parents) ++ return -EINVAL; ++ ++ return val; ++} ++ ++static int ms_clk_mux_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct ms_clk_mux *mux = to_ms_clk_mux(hw); ++ u32 val; ++ unsigned long flags = 0; ++ ++ if (mux->table) ++ index = mux->table[index]; ++ else ++ { ++ if (mux->flags & CLK_MUX_INDEX_BIT) ++ index = (1 << ffs(index)); ++ ++ if (mux->flags & CLK_MUX_INDEX_ONE) ++ index++; ++ } ++ ++ if (mux->lock) ++ spin_lock_irqsave(mux->lock, flags); ++ ++ if (mux->flags & CLK_MUX_HIWORD_MASK) ++ { ++ val = mux->mask << (mux->shift + 16); ++ } ++ else ++ { ++ val = clk_readl(mux->reg); ++ val &= ~(mux->mask << mux->shift); ++ } ++ ++ //switch to glitch-free mux(set 0) ++ if (mux->glitch) ++ { ++ val &= ~(1 << mux->glitch); ++ clk_writel(val, mux->reg); ++ } ++ ++ val |= index << mux->shift; ++ clk_writel(val, mux->reg); ++ ++ //switch back to original mux(set 1) ++ if (mux->glitch) ++ { ++ val |= 1 << mux->glitch; ++ clk_writel(val, mux->reg); ++ } ++ ++ if (mux->lock) ++ spin_unlock_irqrestore(mux->lock, flags); ++ ++ return 0; ++} ++ ++static unsigned long ms_clk_mux_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ struct ms_clk_mux *mux = to_ms_clk_mux(hw); ++ ++ if (mux->glitch) ++ { ++ if(clk_readl(mux->reg) & (1 << mux->glitch)) ++ { ++ pr_debug("\n <%s> parent_rate=%lu, glitch-mux=1\n\n", hw->init->name, parent_rate); ++ return parent_rate; ++ } ++ else ++ { ++ pr_debug("\n <%s> parent_rate=%lu, glitch-mux=0\n\n", hw->init->name, parent_rate); ++ return 12000000; ++ } ++ } ++ ++ pr_debug("\n <%s> parent_rate=%lu, no glitch-mux\n\n", hw->init->name, parent_rate); ++ return parent_rate; ++ ++} ++ ++struct clk_ops ms_clk_mux_ops = { ++ .get_parent = ms_clk_mux_get_parent, ++ .set_parent = ms_clk_mux_set_parent, ++ .determine_rate = __clk_mux_determine_rate, ++ .recalc_rate = ms_clk_mux_recalc_rate, ++}; ++ ++ ++static void __init ms_clk_composite_init(struct device_node *node) ++{ ++ const char *clk_name = node->name; ++ int num_parents; ++ const char **parent_names; ++ struct ms_clk_mux *mux = NULL; ++ struct clk_gate *gate = NULL; ++ void __iomem *reg; ++ u32 i, mux_shift, mux_width, mux_glitch, bit_idx; ++ struct clk *clk; ++ unsigned int flag = 0; ++ ++ num_parents = of_clk_get_parent_count(node); ++ if(num_parents<0) ++ num_parents = 0; ++ parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL); ++ mux = kzalloc(sizeof(*mux), GFP_KERNEL); ++ gate = kzalloc(sizeof(*gate), GFP_KERNEL); ++ ++ if (!parent_names || !mux || !gate) ++ { ++ pr_err("<%s> failed to allocate memory\n", clk_name); ++ goto fail; ++ } ++ ++ reg = of_iomap(node, 0); ++ if (!reg) ++ { ++ pr_err("<%s> could not map region\n", clk_name); ++ goto fail; ++ } ++ ++ for (i = 0; i < num_parents; i++) ++ parent_names[i] = of_clk_get_parent_name(node, i); ++ ++ mux->reg = reg; ++ gate->reg = reg; ++ gate->flags = CLK_GATE_SET_TO_DISABLE; ++ ++ //flag = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED; //remove ignore_unused flag when all drivers use clk framework, so some clks will be gated ++ ++ if(of_property_read_u32(node, "mux-shift", &mux_shift)) ++ { ++ pr_debug("<%s> no mux-shift, treat as gate clock\n", clk_name); ++ mux->shift = 0xFF; ++ } ++ else ++ mux->shift = (u8)mux_shift; ++ ++ if(of_property_read_u32(node, "mux-width", &mux_width)) ++ { ++ pr_debug("<%s> no mux-width, set to default 2 bits\n", clk_name); ++ mux->mask = BIT(2) - 1; ++ } ++ else ++ mux->mask = BIT((u8)mux_width) - 1; ++ ++ if(of_property_read_u32(node, "glitch-shift", &mux_glitch)) ++ { ++ mux->glitch = 0; ++ } ++ else ++ mux->glitch = (u8)mux_glitch; ++ ++ if(of_property_read_u32(node, "gate-shift", &bit_idx)) ++ { ++ pr_debug("<%s> no gate-shift, can not be gated\n", clk_name); ++ gate->bit_idx = 0xFF; ++ } ++ else ++ gate->bit_idx = (u8)bit_idx; ++ ++ pr_debug("[%s]\nmux->reg=0x%08X\nmux->shift=%d\nmux->width=%d\nmux->glitch=%d\ngate->bit_idx=%d\n", ++ clk_name, (unsigned int)mux->reg, mux->shift, mux_width, mux->glitch, gate->bit_idx); ++ ++ if(mux->shift != 0xFF && gate->bit_idx != 0xFF) ++ { ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ &mux->hw, &ms_clk_mux_ops, ++ &mux->hw, &ms_clk_mux_ops, ++ &gate->hw, &clk_gate_ops, flag); ++ } ++ else if(mux->shift != 0xFF) ++ { ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ &mux->hw, &ms_clk_mux_ops, ++ &mux->hw, &ms_clk_mux_ops, ++ NULL, NULL, flag); ++ kfree(gate); ++ } ++ else if(gate->bit_idx != 0xFF) ++ { ++ clk = clk_register_composite(NULL, clk_name, parent_names, num_parents, ++ NULL, NULL, ++ NULL, NULL, ++ &gate->hw, &clk_gate_ops, flag); ++ kfree(mux); ++ } ++ else ++ { ++ pr_err("clock <%s> info. error!\n", clk_name); ++ goto fail; ++ } ++ ++ if (IS_ERR(clk)) ++ { ++ pr_err("%s: failed to register clock <%s>\n", __func__, clk_name); ++ goto fail; ++ } ++ ++ of_clk_add_provider(node, of_clk_src_simple_get, clk); ++ clk_register_clkdev(clk, clk_name, NULL); ++ ++ if(of_property_read_bool(node, "auto-enable")) ++ { ++ clk_prepare_enable(clk); ++ pr_debug("clk_prepare_enable <%s>\n", clk_name); ++ } ++ ++ return; ++ ++fail: ++ kfree(parent_names); ++ kfree(mux); ++ kfree(gate); ++ return; ++} ++ ++CLK_OF_DECLARE(ms_clk_composite, "mstar,composite-clock", ms_clk_composite_init); +\ No newline at end of file +diff --git a/drivers/mstar/clk/ms_usclk.c b/drivers/mstar/clk/ms_usclk.c +new file mode 100644 +index 00000000..5e94e79a +--- /dev/null ++++ b/drivers/mstar/clk/ms_usclk.c +@@ -0,0 +1,222 @@ ++/* ++ * /sys/class/clk ++ * usclk: usclk { ++ compatible = "usclk"; ++ clocks = <&foo 15>, <&bar>; ++ clock-count = <2>; ++ }; ++*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "usclk" ++ ++struct usclk_data { ++ struct clk_hw *hw; ++ int enabled; ++}; ++ ++struct usclk_data *g_pdata; ++struct class *g_clk_class; ++struct device **g_dev; ++u32 g_clock_count; ++ ++static ssize_t enable_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ if(!pdata->hw->init->ops->is_enabled) ++ return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->enabled); ++ else ++ return scnprintf(buf, PAGE_SIZE, "%u\n", pdata->hw->init->ops->is_enabled(pdata->hw)); ++} ++ ++static ssize_t enable_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long enable; ++ int ret; ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &enable); ++ if (ret) ++ return -EINVAL; ++ ++ enable = !!enable; ++ ++ if (enable) ++ pdata->hw->init->ops->enable(pdata->hw); ++ else ++ pdata->hw->init->ops->disable(pdata->hw); ++ ++ pdata->enabled = enable; ++ ++ return count; ++} ++ ++static DEVICE_ATTR(enable, 0644, enable_show, enable_store); ++ ++static ssize_t set_rate_show(struct device *dev, struct device_attribute *attr, ++ char *buf) ++{ ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ return scnprintf(buf, PAGE_SIZE, "%lu\n", clk_get_rate(pdata->hw->clk)); ++} ++ ++static ssize_t set_rate_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ int ret = 0; ++ unsigned long rate; ++ struct usclk_data *pdata = dev_get_drvdata(dev); ++ ++ ret = kstrtoul(buf, 0, &rate); ++ if (ret) ++ { ++ return -EINVAL; ++ } ++ ++ rate = clk_round_rate(pdata->hw->clk, rate); ++ ret = clk_set_rate(pdata->hw->clk, rate); ++ if (ret) ++ { ++ return -EBUSY; ++ } ++ else ++ { ++ pr_info("round rate to %lu\n", rate); ++ } ++ ++ return count; ++} ++ ++static DEVICE_ATTR(rate, 0644, set_rate_show, set_rate_store); ++ ++static const struct attribute *usclk_attrs[] = { ++ &dev_attr_enable.attr, ++ &dev_attr_rate.attr, ++ NULL ++}; ++ ++static const struct attribute_group usclk_attr_grp = { ++ .attrs = (struct attribute **)usclk_attrs, ++}; ++ ++static int usclk_setup(void) ++{ ++ int ret; ++ int i; ++ struct device_node *np = of_find_compatible_node(NULL, NULL, "usclk"); ++ ++ ++// printk(KERN_INFO"setup ms_usclk interface\n"); ++ ret = of_property_read_u32(np, "clock-count", &g_clock_count); ++ if (ret || !g_clock_count) ++ return ret; ++ ++ g_pdata = kzalloc(g_clock_count * sizeof(*g_pdata), GFP_KERNEL); ++ if (!g_pdata) ++ return -ENOMEM; ++ ++ g_dev = kzalloc(g_clock_count * sizeof(struct dev*), GFP_KERNEL); ++ if (!g_dev) ++ return -ENOMEM; ++ ++ g_clk_class = class_create(THIS_MODULE, "usclk"); ++ if (!g_clk_class) { ++ pr_err("unable to create class\n"); ++ goto err_free; ++ } ++ ++ ++ ++ for (i = 0; i < g_clock_count; i++) { ++ g_pdata[i].hw = __clk_get_hw(of_clk_get(np, i)); ++ if (IS_ERR(g_pdata[i].hw)) { ++ pr_warn("input clock #%u not found\n", i); ++ continue; ++ } ++ ++ g_dev[i] = device_create(g_clk_class, NULL, MKDEV(0, 0), NULL, ++ of_clk_get_parent_name(np, i)); ++ ++ if (!g_dev[i]) { ++ pr_warn("unable to create device #%d\n", i); ++ continue; ++ } ++ ++ dev_set_drvdata(g_dev[i], &g_pdata[i]); ++ if(0!=sysfs_create_group(&g_dev[i]->kobj, &usclk_attr_grp)) ++ { ++ pr_warn("create device #%d failed...\n", i); ++ } ++ } ++ ++ printk(KERN_WARNING "ms_usclk: initialized\n"); ++ return 0; ++ ++err_free: ++ if(g_pdata) ++ kfree(g_pdata); ++ ++ if(g_dev) ++ kfree(g_dev); ++ ++ return ret; ++} ++// ++ ++#ifdef CONFIG_MS_USCLK_MODULE ++ ++static int __init ms_usclk_module_init(void) ++{ ++// int retval=0; ++// retval = platform_driver_register(&ms_ir_driver); ++ ++ return usclk_setup(); ++// return retval; ++} ++ ++static void __exit ms_usclk_module_exit(void) ++{ ++ int i; ++// platform_driver_unregis.ter(&ms_ir_driver); ++ for (i = 0; i < g_clock_count; i++) { ++ ++ if(g_dev[i]) ++ { ++ sysfs_remove_group(&g_dev[i]->kobj, &usclk_attr_grp); ++ device_destroy(g_clk_class, g_dev[i]->devt); ++ } ++ } ++ ++ if(g_clk_class) ++ class_destroy(g_clk_class); ++ ++ if(g_pdata) ++ kfree(g_pdata); ++ ++ if(g_dev) ++ kfree(g_dev); ++ ++} ++ ++ ++module_init(ms_usclk_module_init); ++module_exit(ms_usclk_module_exit); ++ ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("usclk driver"); ++MODULE_LICENSE("GPL"); ++ ++#else ++late_initcall(usclk_setup); ++#endif +diff --git a/drivers/mstar/clocksource/Kconfig b/drivers/mstar/clocksource/Kconfig +new file mode 100644 +index 00000000..d773bdc2 +--- /dev/null ++++ b/drivers/mstar/clocksource/Kconfig +@@ -0,0 +1,7 @@ ++config MS_CA9_GT_CLOCKSOURCE ++ bool "ARM CA9 GT Timer for clocksource" ++ depends on ARCH_CEDRIC ++ depends on ARM_GLOBAL_TIMER ++ ++config MS_PIU_TIMER ++ bool "PIU Timer driver" +\ No newline at end of file +diff --git a/drivers/mstar/clocksource/Makefile b/drivers/mstar/clocksource/Makefile +new file mode 100644 +index 00000000..ebecfb28 +--- /dev/null ++++ b/drivers/mstar/clocksource/Makefile +@@ -0,0 +1,5 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/clocksource ++ ++obj-$(CONFIG_MS_CA9_GT_CLOCKSOURCE) += ms_arm_gt_clocksource.o ++obj-$(CONFIG_MS_PIU_TIMER) += ms_piu_timer.o +\ No newline at end of file +diff --git a/drivers/mstar/clocksource/ms_arm_gt_clocksource.c b/drivers/mstar/clocksource/ms_arm_gt_clocksource.c +new file mode 100644 +index 00000000..94cfd5ac +--- /dev/null ++++ b/drivers/mstar/clocksource/ms_arm_gt_clocksource.c +@@ -0,0 +1,163 @@ ++/* ++ * drivers/clocksource/arm_global_timer.c ++ * ++ * Copyright (C) 2013 STMicroelectronics (R&D) Limited. ++ * Author: Stuart Menefy ++ * Author: Srinivas Kandagatla ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define GT_COUNTER0 0x00 ++#define GT_COUNTER1 0x04 ++ ++#define GT_CONTROL 0x08 ++#define GT_CONTROL_TIMER_ENABLE BIT(0) /* this bit is NOT banked */ ++#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */ ++#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */ ++#define GT_CONTROL_AUTO_INC BIT(3) /* banked */ ++ ++#define GT_INT_STATUS 0x0c ++#define GT_INT_STATUS_EVENT_FLAG BIT(0) ++ ++#define GT_COMP0 0x10 ++#define GT_COMP1 0x14 ++#define GT_AUTO_INC 0x18 ++ ++/* ++ * We are expecting to be clocked by the ARM peripheral clock. ++ * ++ * Note: it is assumed we are using a prescaler value of zero, so this is ++ * the units for all operations. ++ */ ++static void __iomem *gt_base; ++static unsigned long gt_clk_rate; ++ ++ ++/* ++ * To get the value from the Global Timer Counter register proceed as follows: ++ * 1. Read the upper 32-bit timer counter register ++ * 2. Read the lower 32-bit timer counter register ++ * 3. Read the upper 32-bit timer counter register again. If the value is ++ * different to the 32-bit upper value read previously, go back to step 2. ++ * Otherwise the 64-bit timer counter value is correct. ++ */ ++static u64 gt_counter_read(void) ++{ ++ u64 counter; ++ u32 lower; ++ u32 upper, old_upper; ++ ++ upper = readl_relaxed(gt_base + GT_COUNTER1); ++ do { ++ old_upper = upper; ++ lower = readl_relaxed(gt_base + GT_COUNTER0); ++ upper = readl_relaxed(gt_base + GT_COUNTER1); ++ } while (upper != old_upper); ++ ++ counter = upper; ++ counter <<= 32; ++ counter |= lower; ++ return counter; ++} ++ ++ ++static cycle_t gt_clocksource_read(struct clocksource *cs) ++{ ++ return gt_counter_read(); ++} ++ ++static struct clocksource gt_clocksource = { ++ .name = "arm_global_timer", ++ .rating = 300, ++ .read = gt_clocksource_read, ++ .mask = CLOCKSOURCE_MASK(64), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++#if 1//def CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK ++static u64 notrace gt_sched_clock_read(void) ++{ ++ return gt_counter_read(); ++} ++#endif ++ ++static void __init gt_clocksource_init(void) ++{ ++ writel(0, gt_base + GT_CONTROL); ++ writel(0, gt_base + GT_COUNTER0); ++ writel(0, gt_base + GT_COUNTER1); ++ /* enables timer on all the cores */ ++ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); ++ ++#if 1//def CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK ++ sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate); ++#endif ++ clocksource_register_hz(>_clocksource, gt_clk_rate); ++} ++ ++ ++static void __init ms_gt_clocksource_of_init(struct device_node *np) ++{ ++ struct clk *gt_clk; ++ int err = 0; ++ ++ /* ++ * In A9 r2p0 the comparators for each processor with the global timer ++ * fire when the timer value is greater than or equal to. In previous ++ * revisions the comparators fired when the timer value was equal to. ++ */ ++ if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9 ++ && (read_cpuid_id() & 0xf0000f) < 0x200000) { ++ pr_warn("global-timer: non support for this cpu version.\n"); ++ return; ++ } ++ ++ gt_base = of_iomap(np, 0); ++ if (!gt_base) { ++ pr_warn("global-timer: invalid base address\n"); ++ return; ++ } ++ ++ gt_clk = of_clk_get(np, 0); ++ if (!IS_ERR(gt_clk)) { ++ err = clk_prepare_enable(gt_clk); ++ if (err) ++ goto out_unmap; ++ } else { ++ pr_warn("global-timer: clk not found\n"); ++ err = -EINVAL; ++ goto out_unmap; ++ } ++ ++ gt_clk_rate = clk_get_rate(gt_clk); ++ ++ /* Immediately configure the timer on the boot CPU */ ++ gt_clocksource_init(); ++ ++ return; ++ ++out_unmap: ++ iounmap(gt_base); ++ WARN(err, "ARM Global timer register failed (%d)\n", err); ++} ++ ++/* Only tested on r2p2 and r3p0 */ ++CLOCKSOURCE_OF_DECLARE(arm_gt_clocksource, "mstar,arm-gt-clocksource", ms_gt_clocksource_of_init); +diff --git a/drivers/mstar/clocksource/ms_piu_timer.c b/drivers/mstar/clocksource/ms_piu_timer.c +new file mode 100644 +index 00000000..3ce9893e +--- /dev/null ++++ b/drivers/mstar/clocksource/ms_piu_timer.c +@@ -0,0 +1,384 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++ ++#include "ms_platform.h" ++ ++ ++//------------------------------------------------------------------------------ ++// Macros ++//------------------------------------------------------------------------------ ++#define COPY_RTC_CNT 0 ++#define USE_ARM_GT 0 //# for better schedule resolution ++ ++#if COPY_RTC_CNT ++ ++#define TIMER_RTC_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x000900) ++#define CHIPTOP_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x080F00) ++#define CPY_RTC_TIMER_INTERVAL 1000 / HZ ++ ++//volatile PREG_TIMER_st g_pTimer2Regs = NULL; ++volatile PREG_CHIPTOP_st g_pCHIPTOPReg = NULL; ++volatile PREG_RTC_st g_pRTCReg = NULL; ++ ++struct timer_list cpy_rtc_timer; ++ ++extern DEVINFO_RTK_FLAG ms_devinfo_rtk_flag(void); ++#endif ++ ++ ++extern unsigned long XTAL_CLK; ++ ++#ifdef __arm__ ++void cap_delay_t(u32 tick) ++{ ++ __asm__ __volatile__( ++"1: nop\n" ++" subs %0, %0, #1\n" ++" bne 1b" ++ : ++ : "r" (tick)); ++} ++#endif ++ ++#define TIMER_ENABLE (0x1) ++#define TIMER_TRIG (0x2) ++#define TIMER_INTERRUPT (0x100) ++#define TIMER_CLEAR (0x4) ++#define TIMER_CAPTURE (0x8) ++#define ADDR_TIMER_MAX_LOW (0x2<<2) ++#define ADDR_TIMER_MAX_HIGH (0x3<<2) ++ ++ ++struct ms_piu_timer { ++ void __iomem *base; ++ unsigned long freq; ++ int irq; ++}; ++ ++struct ms_piu_timer_clockevent { ++ struct clock_event_device event; ++ struct ms_piu_timer timer; ++ struct irqaction irqaction; ++}; ++ ++struct ms_piu_timer_clocksource { ++ struct ms_piu_timer timer; ++ struct clocksource source; ++}; ++ ++ ++static int timer_set_next_event(unsigned long next, struct clock_event_device *evt); ++static void timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt); ++ ++static inline struct ms_piu_timer_clockevent *to_ms_clockevent(struct clock_event_device *evt) ++{ ++ return container_of(evt, struct ms_piu_timer_clockevent, event); ++} ++ ++static inline struct ms_piu_timer_clocksource *to_ms_clocksource(struct clocksource *cs) ++{ ++ return container_of(cs, struct ms_piu_timer_clocksource, source); ++} ++ ++ ++static cycle_t timer_read(struct clocksource *cs) ++{ ++ ++ struct ms_piu_timer_clocksource *ms_cs=to_ms_clocksource(cs); ++#if 0 ++ unsigned int high=INREG16(ms_cs->timer.base+(0x5<<2)); ++ unsigned int low0=INREG16(ms_cs->timer.base+(0x4<<2)); ++ unsigned int low1=INREG16(ms_cs->timer.base+(0x4<<2)); ++ if(low0>low1) ++ { ++ high=INREG16(ms_cs->timer.base+(0x5<<2)); ++ } ++#else ++ //hardware capture ++ unsigned int low0=INREG16(ms_cs->timer.base+(0x4<<2)); ++ unsigned int high=INREG16(ms_cs->timer.base+(0x5<<2)); ++#endif ++ return ((high&0xffff)<<16) + (low0&0xffff) ; ++ ++} ++ ++ ++ ++static struct ms_piu_timer_clocksource* sched_clocksource=NULL; ++static u64 notrace timer_read_sched_clock(void) ++{ ++ if(sched_clocksource) ++ { ++ return timer_read(&sched_clocksource->source); ++ } ++ return 0; ++} ++ ++static void __init ms_piu_timer_clocksource_of_init(struct device_node *np) ++{ ++ ++ struct clk *clk; ++ struct resource res; ++ ++ struct ms_piu_timer_clocksource *ms_cs = kzalloc(sizeof(*ms_cs), GFP_KERNEL); ++ BUG_ON(ms_cs==NULL); ++ BUG_ON(of_address_to_resource(np, 0, &res)); ++ ++ clk = of_clk_get(np, 0); ++ BUG_ON(IS_ERR(clk)); ++ ++ ++ ms_cs->timer.base=(void *)res.start; ++ ++ ms_cs->timer.freq=clk_get_rate(clk); ++ ++ ms_cs->source.name = "timer_clksrc"; ++ ms_cs->source.rating = 200; ++ ms_cs->source.read = timer_read; ++ ms_cs->source.mask = CLOCKSOURCE_MASK(32); ++ ms_cs->source.flags = CLOCK_SOURCE_IS_CONTINUOUS; ++ ++ ++ /* setup timer 2 as free-running clocksource */ ++ //make sure timer 2 is disable ++ CLRREG16(ms_cs->timer.base, TIMER_ENABLE); ++ ++ //set max period ++ OUTREG16(ms_cs->timer.base+(0x2<<2),0xffff); ++ OUTREG16(ms_cs->timer.base+(0x3<<2),0xffff); ++ ++ //enable timer 2 ++ SETREG16(ms_cs->timer.base, TIMER_ENABLE); ++ ++ ++ clocksource_register_hz(&ms_cs->source, ms_cs->timer.freq); ++ ++ sched_clocksource=ms_cs; ++ sched_clock_register(timer_read_sched_clock, 32, ms_cs->timer.freq); ++ ++ return; ++ ++ ++} ++ ++ ++ ++static void timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) ++{ ++ unsigned short ctl=TIMER_INTERRUPT; ++ unsigned long interval; ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ ++ switch (mode) ++ { ++ case CLOCK_EVT_MODE_PERIODIC: ++ interval = (ms_ce->timer.freq / HZ) ; ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_LOW, (interval &0xffff)); ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_HIGH, (interval >>16)); ++ ctl|=TIMER_ENABLE; ++ SETREG16(ms_ce->timer.base, ctl); ++ break; ++ ++ case CLOCK_EVT_MODE_ONESHOT: ++ /* period set, and timer enabled in 'next_event' hook */ ++ ctl|=TIMER_TRIG; ++ SETREG16(ms_ce->timer.base, ctl); ++ break; ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ ctl|=TIMER_ENABLE; ++ CLRREG16(ms_ce->timer.base, ctl); ++ break; ++ case CLOCK_EVT_MODE_UNUSED: ++ default: ++ break; ++ } ++} ++ ++static int timer_set_next_event(unsigned long next, struct clock_event_device *evt) ++{ ++ ++ struct ms_piu_timer_clockevent *ms_ce=to_ms_clockevent(evt); ++ //stop timer ++ //OUTREG16(clkevt_base, 0x0); ++ ++ //set period ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_LOW, (next &0xffff)); ++ OUTREG16(ms_ce->timer.base + ADDR_TIMER_MAX_HIGH, (next >>16)); ++ ++ //enable timer ++ SETREG16(ms_ce->timer.base, TIMER_TRIG|TIMER_INTERRUPT);//default ++ ++ return 0; ++} ++ ++ ++//static DEFINE_SPINLOCK(hw_sys_timer_lock); ++#if COPY_RTC_CNT ++ ++#define RTC_FREQ 32768 ++static void ms_copy_rtc_cnt(unsigned long dummy) ++{ ++ u32 rtc0, rtc1, secl, sech; ++ u32 u32RTCCounts; ++ static u32 dtmr = 0, drtc = 0; ++ ++ //rtc freq 32k ++ rtc0 = INREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_H) << 16; ++ rtc0 += INREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_L); ++ rtc0 = rtc0 * RTC_FREQ + INREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT); ++ ++ secl = INREG16(&g_pRTCReg->RTC_RAW_SEC_CNT_L); ++ sech = INREG16(&g_pRTCReg->RTC_RAW_SEC_CNT_H); ++ u32RTCCounts = INREG16(&g_pRTCReg->RTC_RAW_SUB_CNT); ++ ++ // Lock mutex ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT, 0x8000); ++ ++ // Update RTC sec in CHIPTOP dummy register for GPS ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_L, secl); ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_H, sech); ++ ++ // Reset Timer2 ++ //OUTREG16(&g_pTimer2Regs->TIMER_MAX_L, 0x0); ++ ++ // Update RTC sub cnt in CHIPTOP dummy register for GPS ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT, u32RTCCounts); ++ ++ // Calculate tmr to rtc ratio ++ rtc1 = (sech << 16) + secl; ++ rtc1 = rtc1 * RTC_FREQ + u32RTCCounts; ++ drtc += (rtc1 - rtc0); ++ dtmr += timer_read(&clocksource_timer) - dtmr; ++ ++ if (drtc > RTC_FREQ) // accumulate for 1 sec ++ { ++ OUTREG16(&g_pCHIPTOPReg->REG_CHIPTOP_1F, (dtmr / drtc)); ++ dtmr = drtc = 0; ++ } ++ ++ cpy_rtc_timer.expires = jiffies + msecs_to_jiffies(CPY_RTC_TIMER_INTERVAL); ++ add_timer(&cpy_rtc_timer); ++} ++ ++static void ms_copy_rtc_cnt_init(void) ++{ ++ g_pRTCReg = (PREG_RTC_st)(TIMER_RTC_BASE); ++ //g_pTimer2Regs = (PREG_TIMER_st)(TIMER_CLKSRC_BASE); ++ g_pCHIPTOPReg = (PREG_CHIPTOP_st)(CHIPTOP_BASE); ++ ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_L, INREG16(&g_pRTCReg->RTC_SECOND_CNT_L)); ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SECOND_CNT_H, INREG16(&g_pRTCReg->RTC_SECOND_CNT_H)); ++ OUTREG16(&g_pCHIPTOPReg->u16DUMMY_RTC_SUB_CNT, INREG16(&g_pRTCReg->RTC_SUB_CNT)); ++ ++ init_timer(&cpy_rtc_timer); ++ cpy_rtc_timer.expires = jiffies + msecs_to_jiffies(CPY_RTC_TIMER_INTERVAL); ++ cpy_rtc_timer.data = 0; ++ cpy_rtc_timer.function = ms_copy_rtc_cnt; ++ add_timer(&cpy_rtc_timer); ++ ++ //call right now here ++ ms_copy_rtc_cnt(0); ++} ++#endif ++ ++static irqreturn_t ms_timer_interrupt(int irq, void *dev_id) ++{ ++ ++ struct clock_event_device *evt = dev_id; ++#if defined(CONFIG_MSTAR_CEDRIC) && defined(CONFIG_PROFILING) && defined(CONFIG_OPROFILE) ++ int cpu = smp_processor_id(); ++ extern u32 armpmu_enable_flag[]; ++#endif ++ ++ evt->event_handler(evt); ++ ++/* Mantis 212633 oprofile can't work */ ++#if defined(CONFIG_MSTAR_CEDRIC) && defined(CONFIG_PROFILING) && defined(CONFIG_OPROFILE) ++ /* local_timer call pmu_handle_irq instead of PMU interrupt can't raise by itself. */ ++ if (armpmu_enable_flag[cpu]) { ++ extern irqreturn_t armpmu_handle_irq(int irq_num, void *dev); ++ armpmu_handle_irq(cpu, NULL); ++ } ++#endif ++ ++ ++ return IRQ_HANDLED; ++ ++} ++ ++ ++ ++static void __init ms_piu_timer_clockevent_of_init(struct device_node *np) ++{ ++ struct ms_piu_timer_clockevent *ms_ce = kzalloc(sizeof(*ms_ce), GFP_KERNEL); ++ ++ struct clk *clk; ++ struct resource res; ++ ++ BUG_ON(ms_ce==NULL); ++ BUG_ON(of_address_to_resource(np, 0, &res)); ++ ++ clk = of_clk_get(np, 0); ++ BUG_ON(IS_ERR(clk)); ++ ++ ms_ce->timer.base=(void *)res.start; ++ ++ ms_ce->timer.freq=clk_get_rate(clk); ++ ++ ms_ce->timer.irq =irq_of_parse_and_map(np, 0); ++ if (ms_ce->timer.irq == 0) ++ { ++ panic("No IRQ for clock event timer"); ++ } ++ ++ ms_ce->event.name = "timer_clkevt"; ++ ms_ce->event.shift = 32; ++ ms_ce->event.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; ++ ms_ce->event.set_mode = timer_set_mode; ++ ms_ce->event.set_next_event = timer_set_next_event; ++ ms_ce->event.rating = 200; ++ ms_ce->event.cpumask = cpu_all_mask; ++ ms_ce->event.irq=ms_ce->timer.irq; ++ ++ ms_ce->irqaction.name = "MS Timer Tick"; ++ ms_ce->irqaction.flags = IRQF_TIMER | IRQF_IRQPOLL; ++ ms_ce->irqaction.handler = ms_timer_interrupt; ++ ms_ce->irqaction.dev_id = &ms_ce->event; ++ ++ ++ ++ ++ clockevents_calc_mult_shift(&ms_ce->event,ms_ce->timer.freq,5); ++ ms_ce->event.max_delta_ns = clockevent_delta2ns(0xffffffff, &ms_ce->event); ++ ms_ce->event.min_delta_ns = clockevent_delta2ns(0xf, &ms_ce->event); ++ BUG_ON( setup_irq(ms_ce->event.irq, &ms_ce->irqaction) ); ++ ++ clockevents_register_device( &ms_ce->event); ++ ++ ++#if COPY_RTC_CNT ++ //put it last, because it will use the clock event device ++ if (DEVINFO_RTK_FLAG_1 == ms_devinfo_rtk_flag()) ++ ms_copy_rtc_cnt_init(); ++#endif ++ ++ ++ ++} ++ ++ ++CLOCKSOURCE_OF_DECLARE(ms_piu_timer_cs, "mstar,piu-clocksource", ms_piu_timer_clocksource_of_init); ++CLOCKSOURCE_OF_DECLARE(ms_piu_timer_ce, "mstar,piu-clockevent", ms_piu_timer_clockevent_of_init); +diff --git a/drivers/mstar/cpufreq/Kconfig b/drivers/mstar/cpufreq/Kconfig +new file mode 100644 +index 00000000..1533bbb5 +--- /dev/null ++++ b/drivers/mstar/cpufreq/Kconfig +@@ -0,0 +1,7 @@ ++config MS_CPU_FREQ ++ tristate "Mstar CPU frequency scaling driver" ++ select CPU_FREQ ++ select CPU_FREQ_STAT_DETAILS ++ select CPU_FREQ_GOV_POWERSAVE ++ select CPU_FREQ_GOV_ONDEMAND ++ select CPU_FREQ_GOV_USERSPACE +\ No newline at end of file +diff --git a/drivers/mstar/cpufreq/Makefile b/drivers/mstar/cpufreq/Makefile +new file mode 100644 +index 00000000..f9add868 +--- /dev/null ++++ b/drivers/mstar/cpufreq/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++obj-$(CONFIG_ARCH_INFINITY) += infinity-cpufreq.o ++obj-$(CONFIG_ARCH_INFINITY3) += infinity3-cpufreq.o +diff --git a/drivers/mstar/cpufreq/infinity-cpufreq.c b/drivers/mstar/cpufreq/infinity-cpufreq.c +new file mode 100644 +index 00000000..005975c1 +--- /dev/null ++++ b/drivers/mstar/cpufreq/infinity-cpufreq.c +@@ -0,0 +1,206 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity/registers.h" ++ ++u8 enable_scaling_voltage = 1; ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++ ++extern void ms_cpuclk_dvfs_disable(void); ++extern int bga_vid_0; ++extern int bga_vid_1; ++extern int qfp_vid_0; ++ ++static int ms_cpufreq_verify(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu) ++ return -EINVAL; ++ ++ cpufreq_verify_within_cpu_limits(policy); ++ return 0; ++} ++ ++static int ms_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++{ ++ struct cpufreq_freqs freqs; ++ int ret; ++ ++ freqs.old = policy->cur; ++ freqs.new = target_freq; ++ ++ if (freqs.old == freqs.new) ++ return 0; ++ ++ cpufreq_freq_transition_begin(policy, &freqs); ++ ret = clk_set_rate(policy->clk, target_freq * 1000); ++ cpufreq_freq_transition_end(policy, &freqs, ret); ++ ++ return ret; ++} ++ ++static ssize_t show_scaling_voltage(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", enable_scaling_voltage); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_scaling_voltage(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ sscanf(buf, "%d", &enable); ++ if(enable) ++ { ++ enable_scaling_voltage=1; ++ pr_info("[CPUFREQ] Enable voltage-scaling\n"); ++ } ++ else ++ { ++ enable_scaling_voltage=0; ++ pr_info("[CPUFREQ] Disable voltage-scaling\n"); ++ } ++ return count; ++} ++define_one_global_rw(scaling_voltage); ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ freq = (reg_value * 4000)/83333; ++ ++ str += scnprintf(str, end - str, "CPU freq = %d MHz\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ sscanf(buf, "%d", &enable); ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Enable CPU freq testout\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++ ++static ssize_t show_vid_gpio_map(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "\nBGA_VID_0=%d, BGA_VID_1=%d, QFP_VID_0=%d\n", bga_vid_0, bga_vid_1, qfp_vid_0); ++ ++ return (str - buf); ++} ++define_one_global_ro(vid_gpio_map); ++ ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ int reg, sidd; ++ MS_PACKAGE_TYPE package; ++ ++ package = Chip_Get_Package_Type(); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ ++ policy->min = 400000; ++ policy->max = 800000; ++ policy->cpuinfo.min_freq = 400000; ++ policy->cpuinfo.max_freq = 1000000; ++ policy->cpuinfo.transition_latency = 100000; ++ policy->clk = of_clk_get(of_find_node_by_type(NULL, "cpu"), 0); ++ ++ //2016.08.09: use LPF to scale freq. ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A0 << 1), INREG16(BASE_REG_RIU_PA + (0x1032C0 << 1))); //store freq to LPF low ++ OUTREG16(BASE_REG_RIU_PA + (0x1032A2 << 1), INREG16(BASE_REG_RIU_PA + (0x1032C2 << 1))); ++ ++ reg = (INREG16(BASE_REG_EFUSE_PA + REG_ID_06) >> 12) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_07) & 0x3F) << 4); ++ sidd = reg * 20; // sidd = reg / 5 => multiplied by 100 => sidd_100x = reg * 20 ++ if(sidd >= sidd_th_100x) ++ { ++ enable_scaling_voltage=0; ++ pr_info("Disable CPU voltage-scaling\n"); ++ ms_cpuclk_dvfs_disable(); ++ } ++ ++ pr_info("[%s] cpu current clk=%lu, sidd_100x=%d, th_100x=%d\n", __func__, __clk_get_rate(policy->clk), sidd, sidd_th_100x); ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = ms_cpufreq_verify, ++ .target = ms_cpufreq_target, ++ .get = cpufreq_generic_get, ++ .init = ms_cpufreq_init, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = cpufreq_sysfs_create_file(&scaling_voltage.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&vid_gpio_map.attr); ++ ++ ++ if (ret) ++ { ++ pr_err("[%s] cpufreq_sysfs_create_file failed\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "mstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/mstar/cpufreq/infinity3-cpufreq.c b/drivers/mstar/cpufreq/infinity3-cpufreq.c +new file mode 100644 +index 00000000..b4565b56 +--- /dev/null ++++ b/drivers/mstar/cpufreq/infinity3-cpufreq.c +@@ -0,0 +1,327 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_types.h" ++#include "ms_platform.h" ++#include "infinity3/registers.h" ++ ++u8 enable_scaling_voltage = 1; ++u32 sidd_th_100x = 1243; //sidd threshold=12.74mA ++extern int g_sCurrentTemp; ++extern int g_sCurrentTempThreshLo; ++extern int g_sCurrentTempThreshHi; ++struct timer_list timer_temp; ++extern int Chip_Get_Package_Type(void); ++ ++extern void ms_cpuclk_dvfs_disable(void); ++extern int vid_0; ++extern int vid_1; ++ ++static int ms_cpufreq_verify(struct cpufreq_policy *policy) ++{ ++ if (policy->cpu) ++ return -EINVAL; ++ ++ cpufreq_verify_within_cpu_limits(policy); ++ return 0; ++} ++ ++static int ms_cpufreq_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++{ ++ struct cpufreq_freqs freqs; ++ int ret; ++ ++ freqs.old = policy->cur; ++ freqs.new = target_freq; ++ ++ if (freqs.old == freqs.new) ++ return 0; ++ ++ cpufreq_freq_transition_begin(policy, &freqs); ++ ret = clk_set_rate(policy->clk, target_freq * 1000); ++ cpufreq_freq_transition_end(policy, &freqs, ret); ++ ++ return ret; ++} ++ ++static ssize_t show_scaling_voltage(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", enable_scaling_voltage); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_scaling_voltage(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ enable_scaling_voltage=1; ++ pr_info("[CPUFREQ] Enable voltage-scaling\n"); ++ } ++ else ++ { ++ enable_scaling_voltage=0; ++ pr_info("[CPUFREQ] Disable voltage-scaling\n"); ++ } ++ return count; ++} ++define_one_global_rw(scaling_voltage); ++ ++static ssize_t show_cpufreq_testout(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ u16 reg_value = 0; ++ u32 freq = 0; ++ ++ if( (INREG8(BASE_REG_RIU_PA + (0x102216 << 1))&BIT0) != BIT0) ++ { ++ pr_info("[CPUFREQ] Enable CPU freq testout\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ udelay(100); ++ } ++ reg_value = (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)) | (INREG8(BASE_REG_RIU_PA + (0x101EE2 << 1)+1)<<8)); ++ freq = (reg_value * 4000)/83333; ++ ++ str += scnprintf(str, end - str, "CPU freq = %d MHz\n", freq); ++ ++ return (str - buf); ++} ++ ++static ssize_t store_cpufreq_testout(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 enable; ++ if (sscanf(buf, "%d", &enable)<=0) ++ return 0; ++ ++ if(enable) ++ { ++ pr_info("[CPUFREQ] Enable CPU freq testout\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x04); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x40); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x01); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x80); ++ }else ++ { ++ pr_info("[CPUFREQ] Disable CPU freq testout\n"); ++ OUTREG8(BASE_REG_RIU_PA + (0x102216 << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEE << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEA << 1)+1, 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EEC << 1), 0x00); ++ OUTREG8(BASE_REG_RIU_PA + (0x101EE0 << 1)+1, 0x00); ++ } ++ ++ return count; ++} ++define_one_global_rw(cpufreq_testout); ++ ++ ++static ssize_t show_vid_gpio_map(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "\nvid_0=%d, vid_1=%d\n", vid_0, vid_1); ++ ++ return (str - buf); ++} ++define_one_global_ro(vid_gpio_map); ++ ++static ssize_t show_temp_out(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "Temp=%d\n", g_sCurrentTemp); ++ ++ return (str - buf); ++} ++define_one_global_ro(temp_out); ++ ++ ++static ssize_t show_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshLo); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_lo(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshLo = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_lo); ++ ++static ssize_t show_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", g_sCurrentTempThreshHi); ++ ++ return (str - buf); ++} ++static ssize_t store_temp_adjust_threshold_hi(struct kobject *kobj, struct attribute *attr, const char *buf, size_t count) ++{ ++ u32 value; ++ if (sscanf(buf, "%d", &value)<=0) ++ return 0; ++ g_sCurrentTempThreshHi = value; ++ return count; ++} ++define_one_global_rw(temp_adjust_threshold_hi); ++ ++int ms_get_temp(void) ++{ ++ int temp; ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_19, BIT6); //ch7 reference voltage select to 2.0V ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_10, BIT0); //reg_pm_dmy ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_64, BIT10); ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_2F, BIT2); ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT4); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT5); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT9); ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT8); ++ mdelay(1); ++ CLRREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT6); ++ mdelay(1); ++ SETREG16(BASE_REG_PMSAR_PA + REG_ID_00, BIT14); ++ temp = INREG16(BASE_REG_PMSAR_PA + REG_ID_46); ++ //GF28LP equation to calculate temperature ++ temp = (1220 * (400 - temp) + 25000)/1000; ++ return temp; ++} ++ ++void monitor_temp_timer_handler(unsigned long value) ++{ ++ g_sCurrentTemp = ms_get_temp(); ++ mod_timer(&timer_temp, jiffies + HZ); ++} ++ ++static int ms_cpufreq_init(struct cpufreq_policy *policy) ++{ ++ //int reg, sidd; ++ int package = Chip_Get_Package_Type(); ++ ++ if (policy->cpu != 0) ++ return -EINVAL; ++ if(package >= MS_I3_PACKAGE_EXTENDED) ++ { ++ policy->min = 400000; ++ policy->max = 1000000; ++ ++ } ++ else ++ { ++ policy->min = 400000; ++ policy->max = 800000; ++ } ++ policy->cpuinfo.min_freq = 400000; ++ policy->cpuinfo.max_freq = 1000000; ++ policy->cpuinfo.transition_latency = 100000; ++ policy->clk = of_clk_get(of_find_node_by_type(NULL, "cpu"), 0); ++ ++ /* ++ reg = (INREG16(BASE_REG_EFUSE_PA + REG_ID_06) >> 12) | ((INREG16(BASE_REG_EFUSE_PA + REG_ID_07) & 0x3F) << 4); ++ sidd = reg * 20; // sidd = reg / 5 => multiplied by 100 => sidd_100x = reg * 20 ++ if(sidd >= sidd_th_100x) ++ { ++ enable_scaling_voltage=0; ++ pr_info("Disable CPU voltage-scaling\n"); ++ ms_cpuclk_dvfs_disable(); ++ } ++ pr_info("[%s] sidd_100x=%d, th_100x=%d\n", __func__, sidd, sidd_th_100x); ++ */ ++ ++ //create a timer for monitor temperature ++ init_timer(&timer_temp); ++ timer_temp.function = monitor_temp_timer_handler; ++ timer_temp.expires = jiffies + HZ/10; ++ add_timer(&timer_temp); ++ ++ pr_info("[%s] cpu current clk=%lu\n", __func__, __clk_get_rate(policy->clk)); ++ ++ ++ return 0; ++} ++ ++static struct cpufreq_driver ms_cpufreq_driver = { ++ .verify = ms_cpufreq_verify, ++ .target = ms_cpufreq_target, ++ .get = cpufreq_generic_get, ++ .init = ms_cpufreq_init, ++ .name = "Mstar cpufreq", ++}; ++ ++static int ms_cpufreq_probe(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = cpufreq_sysfs_create_file(&scaling_voltage.attr); ++ ret |= cpufreq_sysfs_create_file(&cpufreq_testout.attr); ++ ret |= cpufreq_sysfs_create_file(&vid_gpio_map.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_lo.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_adjust_threshold_hi.attr); ++ ret |= cpufreq_sysfs_create_file(&temp_out.attr); ++ ++ ++ if (ret) ++ { ++ pr_err("[%s] cpufreq_sysfs_create_file failed\n", __func__); ++ } ++ ++ return cpufreq_register_driver(&ms_cpufreq_driver); ++} ++ ++static int ms_cpufreq_remove(struct platform_device *pdev) ++{ ++ return cpufreq_unregister_driver(&ms_cpufreq_driver); ++} ++ ++static const struct of_device_id ms_cpufreq_of_match_table[] = { ++ { .compatible = "mstar,infinity-cpufreq" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_cpufreq_of_match_table); ++ ++static struct platform_driver ms_cpufreq_platdrv = { ++ .driver = { ++ .name = "ms_cpufreq", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_cpufreq_of_match_table, ++ }, ++ .probe = ms_cpufreq_probe, ++ .remove = ms_cpufreq_remove, ++}; ++ ++module_platform_driver(ms_cpufreq_platdrv); +diff --git a/drivers/mstar/crypto/Kconfig b/drivers/mstar/crypto/Kconfig +new file mode 100644 +index 00000000..5ecc2fcc +--- /dev/null ++++ b/drivers/mstar/crypto/Kconfig +@@ -0,0 +1,19 @@ ++config MS_CRYPTO ++ tristate "Support for the iNfinity AES engine" ++ select CRYPTO_AES ++ select CRYPTO_ECB ++ select CRYPTO_CBC ++ select CRYPTO_SHA256 ++ select CRYPTO_CTR ++ select CRYPTO_ALGAPI ++ help ++ Say 'Y' here to use the iNfinity AES ++ engine for the CryptoAPI AES algorithm. ++ ++ To compile this driver as a module, choose M here: the module ++ will be called infinity-aes. ++ ++#config MS_CRYPTO_INFINITY ++# tristate "CRYPTO driver support for iNfinity" ++# depends on MS_CRYPTO ++# depends on ARCH_INFINITY +\ No newline at end of file +diff --git a/drivers/mstar/crypto/Makefile b/drivers/mstar/crypto/Makefile +new file mode 100644 +index 00000000..b9128732 +--- /dev/null ++++ b/drivers/mstar/crypto/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MS_CRYPTO) += infinity/ +\ No newline at end of file +diff --git a/drivers/mstar/crypto/infinity/Makefile b/drivers/mstar/crypto/infinity/Makefile +new file mode 100644 +index 00000000..3248151b +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/Makefile +@@ -0,0 +1,22 @@ ++obj-$(CONFIG_MS_CRYPTO) += mdrv_crypto.o ++obj-$(CONFIG_MS_CRYPTO) += mdrv_cryptodev.o ++#obj-$(CONFIG_MS_CRYPTO) += mdrv_rsaioctl.o ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/mstar/crypto ++EXTRA_CFLAGS += -Idrivers/mstar/crypto/infinity/cryptodev ++mdrv_crypto-objs := mdrv_aes.o \ ++ mdrv_sha.o \ ++ mdrv_rsa.o \ ++ halAESDMA.o ++ ++mdrv_cryptodev-objs := \ ++ cryptodev/mdrv_cryptioctl.o \ ++ cryptodev/mdrv_cryptmain.o \ ++ cryptodev/mdrv_cryptlib.o \ ++ cryptodev/mdrv_cryptzc.o \ ++ cryptodev/mdrv_cryptutil.o ++ ++#mdrv_rsaioctl-objs := \ ++# mdrv_rsa.o \ ++# halAESDMA.o +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptioctl.c b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptioctl.c +new file mode 100644 +index 00000000..398e498c +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptioctl.c +@@ -0,0 +1,756 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_cryptodev_int.h" ++#include "mdrv_cryptzc.h" ++#include "mdrv_cryptversion.h" ++#include ++#include ++MODULE_AUTHOR("MS Comp."); ++MODULE_DESCRIPTION("CryptoDev driver"); ++MODULE_LICENSE("GPL"); ++ ++/* ====== Compile-time config ====== */ ++ ++/* Default (pre-allocated) and maximum size of the job queue. ++ * These are free, pending and done items all together. */ ++#define DEF_COP_RINGSIZE 2 ++#define MAX_COP_RINGSIZE 8 ++ ++/* ====== Module parameters ====== */ ++ ++int cryptodev_verbosity=2; ++module_param(cryptodev_verbosity, int, 0644); ++ ++MODULE_PARM_DESC(cryptodev_verbosity, "0: normal, 1: verbose, 2: debug"); ++ ++/* ====== CryptoAPI ====== */ ++struct todo_list_item { ++ struct list_head __hook; ++ struct kernel_crypt_op kcop; ++ int result; ++}; ++ ++struct locked_list { ++ struct list_head list; ++ struct mutex lock; ++}; ++ ++struct crypt_priv { ++ struct fcrypt fcrypt; ++ struct locked_list free, todo, done; ++ int itemcount; ++ struct work_struct cryptask; ++ wait_queue_head_t user_waiter; ++}; ++ ++#define FILL_SG(sg, ptr, len) \ ++ do { \ ++ (sg)->page = virt_to_page(ptr); \ ++ (sg)->offset = offset_in_page(ptr); \ ++ (sg)->length = len; \ ++ (sg)->dma_address = 0; \ ++ } while (0) ++ ++/* cryptodev's own workqueue, keeps crypto tasks from disturbing the force */ ++static struct workqueue_struct *cryptodev_wq; ++ ++/* Prepare session for future use. */ ++static int ++crypto_create_session(struct fcrypt *fcr, struct session_op *sop) ++{ ++ struct csession *ses_new = NULL, *ses_ptr; ++ int ret = 0; ++ const char *alg_name = NULL; ++ const char *hash_name = NULL; ++ int hmac_mode = 1, stream = 0, aead = 0; ++ /* ++ * With composite aead ciphers, only ckey is used and it can cover all the ++ * structure space; otherwise both keys may be used simultaneously but they ++ * are confined to their spaces ++ */ ++ struct { ++ uint8_t ckey[CRYPTO_CIPHER_MAX_KEY_LEN]; ++ uint8_t mkey[CRYPTO_HMAC_MAX_KEY_LEN]; ++ /* padding space for aead keys */ ++ uint8_t pad[RTA_SPACE(sizeof(struct crypto_authenc_key_param))]; ++ } keys; ++ /* Does the request make sense? */ ++ if (unlikely(!sop->cipher && !sop->mac)) { ++ return -EINVAL; ++ } ++ switch (sop->cipher) { ++ case 0: ++ break; ++ case CRYPTO_AES_CBC: ++ alg_name = "cbc(aes)"; ++ break; ++ case CRYPTO_AES_ECB: ++ alg_name = "ecb(aes)"; ++ break; ++ case CRYPTO_AES_CTR: ++ alg_name = "ctr(aes)"; ++ stream = 1; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ switch (sop->mac) { ++ case 0: ++ break; ++ case CRYPTO_SHA2_256: ++ hash_name = "sha256"; ++ hmac_mode = 0; ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ /* Create a session and put it to the list. */ ++ ses_new = kzalloc(sizeof(*ses_new), GFP_KERNEL); ++ if (!ses_new) ++ {return -ENOMEM; ++ } ++ /* Set-up crypto transform. */ ++ if (alg_name) { ++ unsigned int keylen; ++ ret = cryptodev_get_cipher_keylen(&keylen, sop, aead); ++ if (unlikely(ret < 0)) { ++ goto error_cipher; ++ } ++ ++ ret = cryptodev_get_cipher_key(keys.ckey, sop, aead); ++ if (unlikely(ret < 0)) ++ goto error_cipher; ++ ++ ret = cryptodev_cipher_init(&ses_new->cdata, alg_name, keys.ckey, ++ keylen, stream, aead); ++ if (ret < 0) { ++ ret = -EINVAL; ++ goto error_cipher; ++ } ++ } ++ ++ if (hash_name && aead == 0) { ++ if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) { ++ ret = -EINVAL; ++ goto error_hash; ++ } ++ ++ if (sop->mackey && unlikely(copy_from_user(keys.mkey, sop->mackey, ++ sop->mackeylen))) { ++ ret = -EFAULT; ++ goto error_hash; ++ } ++ ret = cryptodev_hash_init(&ses_new->hdata, hash_name, hmac_mode, ++ keys.mkey, sop->mackeylen); ++ if (ret != 0) { ++ ret = -EINVAL; ++ goto error_hash; ++ } ++ } ++ ses_new->alignmask = max(ses_new->cdata.alignmask, ++ ses_new->hdata.alignmask); ++ ses_new->array_size = DEFAULT_PREALLOC_PAGES; ++ ses_new->pages = kzalloc(ses_new->array_size * ++ sizeof(struct page *), GFP_KERNEL); ++ ses_new->sg = kzalloc(ses_new->array_size * ++ sizeof(struct scatterlist), GFP_KERNEL); ++ if (ses_new->sg == NULL || ses_new->pages == NULL) { ++ ret = -ENOMEM; ++ goto error_hash_kfree; ++ } ++ ++ /* put the new session to the list */ ++ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); ++ mutex_init(&ses_new->sem); ++ ++ mutex_lock(&fcr->sem); ++restart: ++ list_for_each_entry(ses_ptr, &fcr->list, entry) { ++ /* Check for duplicate SID */ ++ if (unlikely(ses_new->sid == ses_ptr->sid)) { ++ get_random_bytes(&ses_new->sid, sizeof(ses_new->sid)); ++ /* Unless we have a broken RNG this ++ shouldn't loop forever... ;-) */ ++ goto restart; ++ } ++ } ++ ++ list_add(&ses_new->entry, &fcr->list); ++ mutex_unlock(&fcr->sem); ++ ++ /* Fill in some values for the user. */ ++ sop->ses = ses_new->sid; ++ ++ return 0; ++ ++error_hash: ++ cryptodev_cipher_deinit(&ses_new->cdata); ++ kfree(ses_new); ++ return ret; ++error_hash_kfree: ++ kfree(ses_new->sg); ++ kfree(ses_new->pages); ++error_cipher: ++ kfree(ses_new); ++ ++ return ret; ++ ++} ++ ++/* Everything that needs to be done when remowing a session. */ ++static inline void ++crypto_destroy_session(struct csession *ses_ptr) ++{ ++ if (!mutex_trylock(&ses_ptr->sem)) { ++ mutex_lock(&ses_ptr->sem); ++ } ++ cryptodev_cipher_deinit(&ses_ptr->cdata); ++ cryptodev_hash_deinit(&ses_ptr->hdata); ++ kfree(ses_ptr->pages); ++ kfree(ses_ptr->sg); ++ mutex_unlock(&ses_ptr->sem); ++ mutex_destroy(&ses_ptr->sem); ++ kfree(ses_ptr); ++} ++ ++/* Look up a session by ID and remove. */ ++static int ++crypto_finish_session(struct fcrypt *fcr, uint32_t sid) ++{ ++ struct csession *tmp, *ses_ptr; ++ struct list_head *head; ++ int ret = 0; ++ ++ mutex_lock(&fcr->sem); ++ head = &fcr->list; ++ list_for_each_entry_safe(ses_ptr, tmp, head, entry) { ++ if (ses_ptr->sid == sid) { ++ list_del(&ses_ptr->entry); ++ crypto_destroy_session(ses_ptr); ++ break; ++ } ++ } ++ ++ if (unlikely(!ses_ptr)) { ++ ret = -ENOENT; ++ } ++ mutex_unlock(&fcr->sem); ++ ++ return ret; ++} ++ ++/* Remove all sessions when closing the file */ ++static int ++crypto_finish_all_sessions(struct fcrypt *fcr) ++{ ++ struct csession *tmp, *ses_ptr; ++ struct list_head *head; ++ ++ mutex_lock(&fcr->sem); ++ ++ head = &fcr->list; ++ list_for_each_entry_safe(ses_ptr, tmp, head, entry) { ++ list_del(&ses_ptr->entry); ++ crypto_destroy_session(ses_ptr); ++ } ++ mutex_unlock(&fcr->sem); ++ ++ return 0; ++} ++ ++/* Look up session by session ID. The returned session is locked. */ ++struct csession * ++crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid) ++{ ++ struct csession *ses_ptr, *retval = NULL; ++ ++ if (unlikely(fcr == NULL)) ++ return NULL; ++ ++ mutex_lock(&fcr->sem); ++ list_for_each_entry(ses_ptr, &fcr->list, entry) { ++ if (ses_ptr->sid == sid) { ++ mutex_lock(&ses_ptr->sem); ++ retval = ses_ptr; ++ break; ++ } ++ } ++ mutex_unlock(&fcr->sem); ++ ++ return retval; ++} ++ ++static void cryptask_routine(struct work_struct *work) ++{ ++ struct crypt_priv *pcr = container_of(work, struct crypt_priv, cryptask); ++ struct todo_list_item *item; ++ LIST_HEAD(tmp); ++ ++ /* fetch all pending jobs into the temporary list */ ++ mutex_lock(&pcr->todo.lock); ++ list_cut_position(&tmp, &pcr->todo.list, pcr->todo.list.prev); ++ mutex_unlock(&pcr->todo.lock); ++ ++ /* handle each job locklessly */ ++ list_for_each_entry(item, &tmp, __hook) { ++ item->result = crypto_run(&pcr->fcrypt, &item->kcop); ++ if (unlikely(item->result)) ++ printk("crypto_run() failed: %d\n", item->result); ++// derr(0, "crypto_run() failed: %d", item->result); ++ } ++ ++ /* push all handled jobs to the done list at once */ ++ mutex_lock(&pcr->done.lock); ++ list_splice_tail(&tmp, &pcr->done.list); ++ mutex_unlock(&pcr->done.lock); ++ ++ /* wake for POLLIN */ ++ wake_up_interruptible(&pcr->user_waiter); ++} ++ ++/* ====== /dev/crypto ====== */ ++ ++static int ++cryptodev_open(struct inode *inode, struct file *filp) ++{ ++ struct todo_list_item *tmp[DEF_COP_RINGSIZE], *tmp_next; ++ struct crypt_priv *pcr; ++ int i; ++ pcr = kzalloc(sizeof(*pcr), GFP_KERNEL); ++ if (!pcr) ++ return -ENOMEM; ++ filp->private_data = pcr; ++ mutex_init(&pcr->fcrypt.sem); ++ mutex_init(&pcr->free.lock); ++ mutex_init(&pcr->todo.lock); ++ mutex_init(&pcr->done.lock); ++ INIT_LIST_HEAD(&pcr->fcrypt.list); ++ INIT_LIST_HEAD(&pcr->free.list); ++ INIT_LIST_HEAD(&pcr->todo.list); ++ INIT_LIST_HEAD(&pcr->done.list); ++ INIT_WORK(&pcr->cryptask, cryptask_routine); ++ init_waitqueue_head(&pcr->user_waiter); ++ for (i = 0; i < DEF_COP_RINGSIZE; i++) { ++ tmp[i] = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL); ++ if (!tmp[i]) ++ goto err_ringalloc; ++ pcr->itemcount++; ++ list_add(&tmp[i]->__hook, &pcr->free.list); ++ } ++ return 0; ++ ++/* In case of errors, free any memory allocated so far */ ++err_ringalloc: ++ list_for_each_entry_safe(tmp[i], tmp_next, &pcr->free.list, __hook) { ++ list_del(&tmp[i]->__hook); ++ kfree(tmp[i]); ++ } ++ ++ mutex_destroy(&pcr->done.lock); ++ mutex_destroy(&pcr->todo.lock); ++ mutex_destroy(&pcr->free.lock); ++ mutex_destroy(&pcr->fcrypt.sem); ++ kfree(pcr); ++ filp->private_data = NULL; ++ return -ENOMEM; ++} ++ ++static int ++cryptodev_release(struct inode *inode, struct file *filp) ++{ ++ struct crypt_priv *pcr = filp->private_data; ++ struct todo_list_item *item, *item_safe; ++ int items_freed = 0; ++ if (!pcr) ++ return 0; ++ ++ cancel_work_sync(&pcr->cryptask); ++ ++ list_splice_tail(&pcr->todo.list, &pcr->free.list); ++ list_splice_tail(&pcr->done.list, &pcr->free.list); ++ ++ list_for_each_entry_safe(item, item_safe, &pcr->free.list, __hook) { ++ list_del(&item->__hook); ++ kfree(item); ++ items_freed++; ++ } ++ ++ if (items_freed != pcr->itemcount) { ++ } ++ ++ crypto_finish_all_sessions(&pcr->fcrypt); ++ ++ mutex_destroy(&pcr->done.lock); ++ mutex_destroy(&pcr->todo.lock); ++ mutex_destroy(&pcr->free.lock); ++ mutex_destroy(&pcr->fcrypt.sem); ++ ++ kfree(pcr); ++ filp->private_data = NULL; ++ ++ return 0; ++} ++ ++#ifdef ENABLE_ASYNC ++/* enqueue a job for asynchronous completion ++ * ++ * returns: ++ * -EBUSY when there are no free queue slots left ++ * (and the number of slots has reached it MAX_COP_RINGSIZE) ++ * -EFAULT when there was a memory allocation error ++ * 0 on success */ ++static int crypto_async_run(struct crypt_priv *pcr, struct kernel_crypt_op *kcop) ++{ ++ struct todo_list_item *item = NULL; ++ if (unlikely(kcop->cop.flags & COP_FLAG_NO_ZC)) ++ return -EINVAL; ++ mutex_lock(&pcr->free.lock); ++ if (likely(!list_empty(&pcr->free.list))) { ++ item = list_first_entry(&pcr->free.list, ++ struct todo_list_item, __hook); ++ list_del(&item->__hook); ++ } else if (pcr->itemcount < MAX_COP_RINGSIZE) { ++ pcr->itemcount++; ++ } else { ++ mutex_unlock(&pcr->free.lock); ++ return -EBUSY; ++ } ++ mutex_unlock(&pcr->free.lock); ++ ++ if (unlikely(!item)) { ++ item = kzalloc(sizeof(struct todo_list_item), GFP_KERNEL); ++ if (unlikely(!item)) ++ return -EFAULT; ++ } ++ ++ memcpy(&item->kcop, kcop, sizeof(struct kernel_crypt_op)); ++ ++ mutex_lock(&pcr->todo.lock); ++ list_add_tail(&item->__hook, &pcr->todo.list); ++ mutex_unlock(&pcr->todo.lock); ++ ++ queue_work(cryptodev_wq, &pcr->cryptask); ++ return 0; ++} ++ ++/* get the first completed job from the "done" queue ++ * ++ * returns: ++ * -EBUSY if no completed jobs are ready (yet) ++ * the return value of crypto_run() otherwise */ ++static int crypto_async_fetch(struct crypt_priv *pcr, ++ struct kernel_crypt_op *kcop) ++{ ++ struct todo_list_item *item; ++ int retval; ++ ++ mutex_lock(&pcr->done.lock); ++ if (list_empty(&pcr->done.list)) { ++ mutex_unlock(&pcr->done.lock); ++ return -EBUSY; ++ } ++ item = list_first_entry(&pcr->done.list, struct todo_list_item, __hook); ++ list_del(&item->__hook); ++ mutex_unlock(&pcr->done.lock); ++ ++ memcpy(kcop, &item->kcop, sizeof(struct kernel_crypt_op)); ++ retval = item->result; ++ ++ mutex_lock(&pcr->free.lock); ++ list_add_tail(&item->__hook, &pcr->free.list); ++ mutex_unlock(&pcr->free.lock); ++ ++ /* wake for POLLOUT */ ++ wake_up_interruptible(&pcr->user_waiter); ++ ++ return retval; ++} ++#endif ++ ++/* this function has to be called from process context */ ++static int fill_kcop_from_cop(struct kernel_crypt_op *kcop, struct fcrypt *fcr) ++{ ++ struct crypt_op *cop = &kcop->cop; ++ struct csession *ses_ptr; ++ int rc; ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); ++ if (unlikely(!ses_ptr)) { ++ return -EINVAL; ++ } ++ kcop->ivlen = cop->iv ? ses_ptr->cdata.ivsize : 0; ++ kcop->digestsize = 0; /* will be updated during operation */ ++ ++ crypto_put_session(ses_ptr); ++ ++ kcop->task = current; ++ kcop->mm = current->mm; ++ ++ if (cop->iv) { ++ rc = copy_from_user(kcop->iv, cop->iv, kcop->ivlen); ++ if (unlikely(rc)) { ++ return -EFAULT; ++ } ++ } ++ return 0; ++} ++ ++/* this function has to be called from process context */ ++static int fill_cop_from_kcop(struct kernel_crypt_op *kcop, struct fcrypt *fcr) ++{ ++ int ret; ++ if (kcop->digestsize) { ++ ret = copy_to_user(kcop->cop.mac, ++ kcop->hash_output, kcop->digestsize); ++ if (unlikely(ret)) ++ return -EFAULT; ++ } ++ if (kcop->ivlen && kcop->cop.flags & COP_FLAG_WRITE_IV) { ++ ret = copy_to_user(kcop->cop.iv, ++ kcop->iv, kcop->ivlen); ++ if (unlikely(ret)) ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static int kcop_from_user(struct kernel_crypt_op *kcop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ if (unlikely(copy_from_user(&kcop->cop, arg, sizeof(kcop->cop)))) ++ return -EFAULT; ++ return fill_kcop_from_cop(kcop, fcr); ++} ++ ++static int kcop_to_user(struct kernel_crypt_op *kcop, ++ struct fcrypt *fcr, void __user *arg) ++{ ++ int ret; ++ ++ ret = fill_cop_from_kcop(kcop, fcr); ++ if (unlikely(ret)) { ++ return ret; ++ } ++ ++ if (unlikely(copy_to_user(arg, &kcop->cop, sizeof(kcop->cop)))) { ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static inline void tfm_info_to_alg_info(struct alg_info *dst, struct crypto_tfm *tfm) ++{ ++ snprintf(dst->cra_name, CRYPTODEV_MAX_ALG_NAME, ++ "%s", crypto_tfm_alg_name(tfm)); ++ snprintf(dst->cra_driver_name, CRYPTODEV_MAX_ALG_NAME, ++ "%s", crypto_tfm_alg_driver_name(tfm)); ++} ++ ++#ifndef CRYPTO_ALG_KERN_DRIVER_ONLY ++static unsigned int is_known_accelerated(struct crypto_tfm *tfm) ++{ ++ const char *name = crypto_tfm_alg_driver_name(tfm); ++ ++ if (name == NULL) ++ return 1; /* assume accelerated */ ++ ++ /* look for known crypto engine names */ ++ if (strstr(name, "-talitos") || ++ !strncmp(name, "mv-", 3) || ++ !strncmp(name, "atmel-", 6) || ++ strstr(name, "geode") || ++ strstr(name, "hifn") || ++ strstr(name, "-ixp4xx") || ++ strstr(name, "-omap") || ++ strstr(name, "-picoxcell") || ++ strstr(name, "-s5p") || ++ strstr(name, "-ppc4xx") || ++ strstr(name, "-caam") || ++ strstr(name, "-n2")) ++ return 1; ++ ++ return 0; ++} ++#endif ++ ++static long ++cryptodev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg_) ++{ ++ void __user *arg = (void __user *)arg_; ++ struct session_op sop; ++ struct kernel_crypt_op kcop; ++ struct crypt_priv *pcr = filp->private_data; ++ struct fcrypt *fcr; ++ uint32_t ses; ++ int ret; ++ if (unlikely(!pcr)) ++ BUG(); ++ ++ fcr = &pcr->fcrypt; ++ ++ switch (cmd) { ++ case CIOCGSESSION: ++ if (unlikely(copy_from_user(&sop, arg, sizeof(sop)))) ++ return -EFAULT; ++ ret = crypto_create_session(fcr, &sop); ++ if (unlikely(ret)) ++ return ret; ++ ret = copy_to_user(arg, &sop, sizeof(sop)); ++ if (unlikely(ret)) { ++ crypto_finish_session(fcr, sop.ses); ++ return -EFAULT; ++ } ++ return ret; ++ case CIOCFSESSION: ++ ret = get_user(ses, (uint32_t __user *)arg); ++ if (unlikely(ret)) ++ return ret; ++ ret = crypto_finish_session(fcr, ses); ++ return ret; ++ case CIOCCRYPT: ++ if (unlikely(ret = kcop_from_user(&kcop, fcr, arg))) { ++// dwarning(1, "Error copying from user"); ++ return ret; ++ } ++ ret = crypto_run(fcr, &kcop); ++ if (unlikely(ret)) { ++// dwarning(1, "Error in crypto_run"); ++ return ret; ++ } ++ return kcop_to_user(&kcop, fcr, arg); ++ ++ default: ++ return -ENOTTY; ++ } ++} ++ ++ ++static unsigned int cryptodev_poll(struct file *file, poll_table *wait) ++{ ++ struct crypt_priv *pcr = file->private_data; ++ int ret = 0; ++ poll_wait(file, &pcr->user_waiter, wait); ++ if (!list_empty_careful(&pcr->done.list)) ++ ret |= POLLIN | POLLRDNORM; ++ if (!list_empty_careful(&pcr->free.list) || pcr->itemcount < MAX_COP_RINGSIZE) ++ ret |= POLLOUT | POLLWRNORM; ++ return ret; ++} ++ ++static const struct file_operations cryptodev_fops = { ++ .owner = THIS_MODULE, ++ .open = cryptodev_open, ++ .release = cryptodev_release, ++ .unlocked_ioctl = cryptodev_ioctl, ++#ifdef CONFIG_COMPAT ++ .compat_ioctl = cryptodev_compat_ioctl, ++#endif /* CONFIG_COMPAT */ ++ .poll = cryptodev_poll, ++}; ++ ++static struct miscdevice cryptodev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "crypto", ++ .fops = &cryptodev_fops, ++ .mode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH, ++}; ++ ++static int __init ++cryptodev_register(void) ++{ ++ int rc; ++ rc = misc_register(&cryptodev); ++ if (unlikely(rc)) { ++ pr_err(PFX "registration of /dev/crypto failed\n"); ++ return rc; ++ } ++ ++ return 0; ++} ++ ++static void __exit ++cryptodev_deregister(void) ++{ ++ misc_deregister(&cryptodev); ++} ++ ++/* ====== Module init/exit ====== */ ++static struct ctl_table verbosity_ctl_dir[] = { ++ { ++ .procname = "cryptodev_verbosity", ++ .data = &cryptodev_verbosity, ++ .maxlen = sizeof(int), ++ .mode = 0644, ++ .proc_handler = proc_dointvec, ++ }, ++ {0, }, ++}; ++ ++static struct ctl_table verbosity_ctl_root[] = { ++ { ++ .procname = "ioctl", ++ .mode = 0555, ++ .child = verbosity_ctl_dir, ++ }, ++ {0, }, ++}; ++static struct ctl_table_header *verbosity_sysctl_header; ++static int __init init_cryptodev(void) ++{ ++ int rc; ++ cryptodev_wq = create_workqueue("cryptodev_queue"); ++ if (unlikely(!cryptodev_wq)) { ++ pr_err(PFX "failed to allocate the cryptodev workqueue\n"); ++ return -EFAULT; ++ } ++ rc = cryptodev_register(); ++ if (unlikely(rc)) { ++ destroy_workqueue(cryptodev_wq); ++ return rc; ++ } ++ verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root); ++ pr_info(PFX "driver %s loaded.\n", VERSION); ++ return 0; ++} ++ ++static void __exit exit_cryptodev(void) ++{ ++ flush_workqueue(cryptodev_wq); ++ destroy_workqueue(cryptodev_wq); ++ if (verbosity_sysctl_header) ++ unregister_sysctl_table(verbosity_sysctl_header); ++ cryptodev_deregister(); ++ pr_info(PFX "driver unloaded.\n"); ++} ++module_init(init_cryptodev); ++module_exit(exit_cryptodev); +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptlib.c b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptlib.c +new file mode 100644 +index 00000000..9d2287f3 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptlib.c +@@ -0,0 +1,351 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_cryptodev_int.h" ++#include "mdrv_crypto_io_st.h" ++#include "mdrv_crypto_io.h" ++struct cryptodev_result { ++ struct completion completion; ++ int err; ++}; ++ ++static void cryptodev_complete(struct crypto_async_request *req, int err) ++{ ++ struct cryptodev_result *res = req->data; ++ ++ if (err == -EINPROGRESS) ++ return; ++ ++ res->err = err; ++ complete(&res->completion); ++} ++ ++int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop, ++ int aead) ++{ ++ /* ++ * For blockciphers (AES-CBC) or non-composite aead ciphers (like AES-GCM), ++ * the key length is simply the cipher keylen obtained from userspace. If ++ * the cipher is composite aead, the keylen is the sum of cipher keylen, ++ * hmac keylen and a key header length. This key format is the one used in ++ * Linux kernel for composite aead ciphers (crypto/authenc.c) ++ */ ++ unsigned int klen = sop->keylen; ++ ++ if (unlikely(sop->keylen > CRYPTO_CIPHER_MAX_KEY_LEN)) ++ return -EINVAL; ++ ++ if (aead && sop->mackeylen) { ++ if (unlikely(sop->mackeylen > CRYPTO_HMAC_MAX_KEY_LEN)) ++ return -EINVAL; ++ klen += sop->mackeylen; ++ klen += RTA_SPACE(sizeof(struct crypto_authenc_key_param)); ++ } ++ ++ *keylen = klen; ++ return 0; ++} ++ ++int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead) ++{ ++ /* ++ * Get cipher key from user-space. For blockciphers just copy it from ++ * user-space. For composite aead ciphers combine it with the hmac key in ++ * the format used by Linux kernel in crypto/authenc.c: ++ * ++ * [[AUTHENC_KEY_HEADER + CIPHER_KEYLEN] [AUTHENTICATION KEY] [CIPHER KEY]] ++ */ ++ struct crypto_authenc_key_param *param; ++ struct rtattr *rta; ++ int ret = 0; ++ ++ if (aead && sop->mackeylen) { ++ /* ++ * Composite aead ciphers. The first four bytes are the header type and ++ * header length for aead keys ++ */ ++ rta = (void *)key; ++ rta->rta_type = CRYPTO_AUTHENC_KEYA_PARAM; ++ rta->rta_len = RTA_LENGTH(sizeof(*param)); ++ ++ /* ++ * The next four bytes hold the length of the encryption key ++ */ ++ param = RTA_DATA(rta); ++ param->enckeylen = cpu_to_be32(sop->keylen); ++ ++ /* Advance key pointer eight bytes and copy the hmac key */ ++ key += RTA_SPACE(sizeof(*param)); ++ if (unlikely(copy_from_user(key, sop->mackey, sop->mackeylen))) { ++ ret = -EFAULT; ++ goto error; ++ } ++ /* Advance key pointer past the hmac key */ ++ key += sop->mackeylen; ++ } ++ /* now copy the blockcipher key */ ++ if (unlikely(copy_from_user(key, sop->key, sop->keylen))) ++ ret = -EFAULT; ++error: ++ return ret; ++} ++ ++int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name, ++ uint8_t *keyp, size_t keylen, int stream, int aead) ++{ ++ int ret = 0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ if (aead == 0) { ++ struct ablkcipher_alg *alg; ++ out->async.s = crypto_alloc_ablkcipher(alg_name, 0, 0); ++ if (unlikely(IS_ERR(out->async.s))) { ++ return -EINVAL; ++ } ++ alg = crypto_ablkcipher_alg(out->async.s); ++ if (alg != NULL) { ++ /* Was correct key length supplied? */ ++ if (alg->max_keysize > 0 && ++ unlikely((keylen < alg->min_keysize) || ++ (keylen > alg->max_keysize))) { ++ ret = -EINVAL; ++ goto error; ++ } ++ } ++ ++ out->blocksize = crypto_ablkcipher_blocksize(out->async.s); ++ out->ivsize = crypto_ablkcipher_ivsize(out->async.s); ++ out->alignmask = crypto_ablkcipher_alignmask(out->async.s); ++ ret = crypto_ablkcipher_setkey(out->async.s, keyp, keylen); ++ } else { ++ printk("Doesn't support crypto_alloc_aead \n"); ++ } ++ ++ if (unlikely(ret)) { ++ ret = -EINVAL; ++ goto error; ++ } ++ out->stream = stream; ++ out->aead = aead; ++ out->async.result = kzalloc(sizeof(*out->async.result), GFP_KERNEL); ++ if (unlikely(!out->async.result)) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ init_completion(&out->async.result->completion); ++ ++ if (aead == 0) { ++ out->async.request = ablkcipher_request_alloc(out->async.s, GFP_KERNEL); ++ if (unlikely(!out->async.request)) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ablkcipher_request_set_callback(out->async.request, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, ++ cryptodev_complete, out->async.result); ++ } else { ++ printk("Doesn't support crypto_alloc_aead \n"); ++ } ++ out->init = 1; ++ return 0; ++error: ++ if (aead == 0) { ++ if (out->async.request) ++ ablkcipher_request_free(out->async.request); ++ if (out->async.s) ++ crypto_free_ablkcipher(out->async.s); ++ } ++ ++ kfree(out->async.result); ++ ++ return ret; ++} ++ ++void cryptodev_cipher_deinit(struct cipher_data *cdata) ++{ ++ if (cdata->init) { ++ if (cdata->aead == 0) { ++ if (cdata->async.request) ++ ablkcipher_request_free(cdata->async.request); ++ if (cdata->async.s) ++ crypto_free_ablkcipher(cdata->async.s); ++ } ++ kfree(cdata->async.result); ++ cdata->init = 0; ++ } ++} ++ ++static inline int waitfor(struct cryptodev_result *cr, ssize_t ret) ++{ ++ if (ret == -EINPROGRESS || ret == -EBUSY) { ++ ret = wait_for_completion_interruptible(&cr->completion); ++ if (!ret) ++ ret = cr->err; ++ reinit_completion(&cr->completion); ++ } ++ return ret; ++} ++ ++ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata, ++ const struct scatterlist *src, struct scatterlist *dst, ++ size_t len) ++{ ++ int ret = 0; ++ reinit_completion(&cdata->async.result->completion); ++ ++ if (cdata->aead == 0) { ++ ablkcipher_request_set_crypt(cdata->async.request, ++ (struct scatterlist *)src, dst, ++ len, cdata->async.iv); ++ ret = crypto_ablkcipher_encrypt(cdata->async.request); ++ ++ } ++ ++ ++ return waitfor(cdata->async.result, ret); ++} ++ ++ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata, ++ const struct scatterlist *src, struct scatterlist *dst, ++ size_t len) ++{ ++ int ret = 0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ reinit_completion(&cdata->async.result->completion); ++ if (cdata->aead == 0) { ++ ablkcipher_request_set_crypt(cdata->async.request, ++ (struct scatterlist *)src, dst, ++ len, cdata->async.iv); ++ ret = crypto_ablkcipher_decrypt(cdata->async.request); ++ } ++ ++ return waitfor(cdata->async.result, ret); ++} ++ ++/* Hash functions */ ++ ++int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name, ++ int hmac_mode, void *mackey, size_t mackeylen) ++{ ++ int ret = 0; ++ hdata->async.s = crypto_alloc_ahash(alg_name, 0, 0); ++ if (unlikely(IS_ERR(hdata->async.s))) { ++ return -EINVAL; ++ } ++ ++ /* Copy the key from user and set to TFM. */ ++ if (hmac_mode != 0) { ++ ret = crypto_ahash_setkey(hdata->async.s, mackey, mackeylen); ++ if (unlikely(ret)) { ++ ret = -EINVAL; ++ goto error; ++ } ++ } ++ ++ hdata->digestsize = crypto_ahash_digestsize(hdata->async.s); ++ hdata->alignmask = crypto_ahash_alignmask(hdata->async.s); ++ ++ hdata->async.result = kzalloc(sizeof(*hdata->async.result), GFP_KERNEL); ++ if (unlikely(!hdata->async.result)) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ init_completion(&hdata->async.result->completion); ++ ++ hdata->async.request = ahash_request_alloc(hdata->async.s, GFP_KERNEL); ++ if (unlikely(!hdata->async.request)) { ++ ret = -ENOMEM; ++ goto error; ++ } ++ ++ ahash_request_set_callback(hdata->async.request, ++ CRYPTO_TFM_REQ_MAY_BACKLOG, ++ cryptodev_complete, hdata->async.result); ++ ++ ret = crypto_ahash_init(hdata->async.request); ++ if (unlikely(ret)) { ++ goto error_request; ++ } ++ ++ hdata->init = 1; ++ return 0; ++ ++error_request: ++ ahash_request_free(hdata->async.request); ++error: ++ kfree(hdata->async.result); ++ crypto_free_ahash(hdata->async.s); ++ return ret; ++} ++ ++void cryptodev_hash_deinit(struct hash_data *hdata) ++{ ++ if (hdata->init) { ++ if (hdata->async.request) ++ ahash_request_free(hdata->async.request); ++ kfree(hdata->async.result); ++ if (hdata->async.s) ++ crypto_free_ahash(hdata->async.s); ++ hdata->init = 0; ++ } ++} ++ ++int cryptodev_hash_reset(struct hash_data *hdata) ++{ ++ int ret = 0; ++ ret = crypto_ahash_init(hdata->async.request); ++ if (unlikely(ret)) { ++ return ret; ++ } ++ ++ return 0; ++ ++} ++ ++ssize_t cryptodev_hash_update(struct hash_data *hdata, ++ struct scatterlist *sg, size_t len) ++{ ++ int ret = 0; ++ ++ reinit_completion(&hdata->async.result->completion); ++ ahash_request_set_crypt(hdata->async.request, sg, NULL, len); ++ ++ ret = crypto_ahash_update(hdata->async.request); ++ ++ return waitfor(hdata->async.result, ret); ++} ++ ++int cryptodev_hash_final(struct hash_data *hdata, void *output) ++{ ++ int ret = 0; ++ reinit_completion(&hdata->async.result->completion); ++ ahash_request_set_crypt(hdata->async.request, NULL, output, 0); ++ ret = crypto_ahash_final(hdata->async.request); ++ return waitfor(hdata->async.result, ret); ++} +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptlib.h b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptlib.h +new file mode 100644 +index 00000000..7325fe80 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptlib.h +@@ -0,0 +1,66 @@ ++#ifndef CRYPTLIB_H ++# define CRYPTLIB_H ++ ++struct cipher_data { ++ int init; /* 0 uninitialized */ ++ int blocksize; ++ int aead; ++ int stream; ++ int ivsize; ++ int alignmask; ++ struct { ++ /* block ciphers */ ++ struct crypto_ablkcipher *s; ++ struct ablkcipher_request *request; ++ struct cryptodev_result *result; ++ uint8_t iv[EALG_MAX_BLOCK_LEN]; ++ } async; ++}; ++ ++int cryptodev_cipher_init(struct cipher_data *out, const char *alg_name, ++ uint8_t *key, size_t keylen, int stream, int aead); ++void cryptodev_cipher_deinit(struct cipher_data *cdata); ++int cryptodev_get_cipher_key(uint8_t *key, struct session_op *sop, int aead); ++int cryptodev_get_cipher_keylen(unsigned int *keylen, struct session_op *sop, ++ int aead); ++ssize_t cryptodev_cipher_decrypt(struct cipher_data *cdata, ++ const struct scatterlist *sg1, ++ struct scatterlist *sg2, size_t len); ++ssize_t cryptodev_cipher_encrypt(struct cipher_data *cdata, ++ const struct scatterlist *sg1, ++ struct scatterlist *sg2, size_t len); ++ ++static inline void cryptodev_cipher_set_iv(struct cipher_data *cdata, ++ void *iv, size_t iv_size) ++{ ++ memcpy(cdata->async.iv, iv, min(iv_size, sizeof(cdata->async.iv))); ++} ++ ++static inline void cryptodev_cipher_get_iv(struct cipher_data *cdata, ++ void *iv, size_t iv_size) ++{ ++ memcpy(iv, cdata->async.iv, min(iv_size, sizeof(cdata->async.iv))); ++} ++ ++/* Hash */ ++struct hash_data { ++ int init; /* 0 uninitialized */ ++ int digestsize; ++ int alignmask; ++ struct { ++ struct crypto_ahash *s; ++ struct cryptodev_result *result; ++ struct ahash_request *request; ++ } async; ++}; ++ ++int cryptodev_hash_final(struct hash_data *hdata, void *output); ++ssize_t cryptodev_hash_update(struct hash_data *hdata, ++ struct scatterlist *sg, size_t len); ++int cryptodev_hash_reset(struct hash_data *hdata); ++void cryptodev_hash_deinit(struct hash_data *hdata); ++int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name, ++ int hmac_mode, void *mackey, size_t mackeylen); ++ ++ ++#endif +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptmain.c b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptmain.c +new file mode 100644 +index 00000000..8337800b +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptmain.c +@@ -0,0 +1,238 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_cryptodev_int.h" ++#include "mdrv_cryptzc.h" ++#include "mdrv_cryptlib.h" ++#include "mdrv_cryptversion.h" ++ ++/* This file contains the traditional operations of encryption ++ * and hashing of /dev/crypto. ++ */ ++ ++static int hash_n_crypt(struct csession *ses_ptr, struct crypt_op *cop, ++ struct scatterlist *src_sg, struct scatterlist *dst_sg, ++ uint32_t len) ++{ ++ int ret; ++ /* Always hash before encryption and after decryption. Maybe ++ * we should introduce a flag to switch... TBD later on. ++ */ ++ if (cop->op == COP_ENCRYPT) { ++ if (ses_ptr->hdata.init != 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ src_sg, len); ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_encrypt(&ses_ptr->cdata, ++ src_sg, dst_sg, len); ++ ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ } else { ++ if (ses_ptr->cdata.init != 0) { ++ ret = cryptodev_cipher_decrypt(&ses_ptr->cdata, ++ src_sg, dst_sg, len); ++ ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ ++ if (ses_ptr->hdata.init != 0) { ++ ret = cryptodev_hash_update(&ses_ptr->hdata, ++ dst_sg, len); ++ if (unlikely(ret)) ++ goto out_err; ++ } ++ } ++ return 0; ++out_err: ++// derr(0, "CryptoAPI failure: %d", ret); ++ return ret; ++} ++ ++/* This is the main crypto function - feed it with plaintext ++ and get a ciphertext (or vice versa ) */ ++static int ++__crypto_run_std(struct csession *ses_ptr, struct crypt_op *cop) ++{ char *data; ++ char __user *src, *dst; ++ struct scatterlist sg; ++ size_t nbytes, bufsize; ++ int ret = 0; ++ ++ nbytes = cop->len; ++ data = (char *)__get_free_page(GFP_KERNEL); ++ ++ if (unlikely(!data)) { ++ return -ENOMEM; ++ } ++ ++ bufsize = PAGE_SIZE < nbytes ? PAGE_SIZE : nbytes; ++ ++ src = cop->src; ++ dst = cop->dst; ++ ++ while (nbytes > 0) { ++ size_t current_len = nbytes > bufsize ? bufsize : nbytes; ++ ++ if (unlikely(copy_from_user(data, src, current_len))) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ sg_init_one(&sg, data, current_len); ++ ret = hash_n_crypt(ses_ptr, cop, &sg, &sg, current_len); ++ if (unlikely(ret)) { ++ break; ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ if (unlikely(copy_to_user(dst, data, current_len))) { ++// derr(1, "could not copy to user."); ++ ret = -EFAULT; ++ break; ++ } ++ } ++ ++ dst += current_len; ++ nbytes -= current_len; ++ src += current_len; ++ } ++ ++ free_page((unsigned long)data); ++ return ret; ++} ++ ++ ++ ++/* This is the main crypto function - zero-copy edition */ ++static int ++__crypto_run_zc(struct csession *ses_ptr, struct kernel_crypt_op *kcop) ++{ ++ struct scatterlist *src_sg, *dst_sg; ++ struct crypt_op *cop = &kcop->cop; ++ int ret = 0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ AESDMA_DBG("%s %d\n",__FUNCTION__,cop->len); ++ ret = get_userbuf(ses_ptr, cop->src, cop->len, cop->dst, cop->len, ++ kcop->task, kcop->mm, &src_sg, &dst_sg); ++ if (unlikely(ret)) { ++// derr(1, "Error getting user pages. Falling back to non zero copy."); ++ return __crypto_run_std(ses_ptr, cop); ++ } ++ ++ ret = hash_n_crypt(ses_ptr, cop, src_sg, dst_sg, cop->len); ++ ++ release_user_pages(ses_ptr); ++ return ret; ++} ++ ++int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop) ++{ ++ struct csession *ses_ptr; ++ struct crypt_op *cop = &kcop->cop; ++ int ret = 0; ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ if (unlikely(cop->op != COP_ENCRYPT && cop->op != COP_DECRYPT)) { ++ return -EINVAL; ++ } ++ ++ /* this also enters ses_ptr->sem */ ++ ses_ptr = crypto_get_session_by_sid(fcr, cop->ses); ++ if (unlikely(!ses_ptr)) { ++// derr(1, "invalid session ID=0x%08X", cop->ses); ++ return -EINVAL; ++ } ++ if (ses_ptr->hdata.init != 0 && (cop->flags == 0 || cop->flags & COP_FLAG_RESET)) { ++ ret = cryptodev_hash_reset(&ses_ptr->hdata); ++ if (unlikely(ret)) { ++// derr(1, "error in cryptodev_hash_reset()"); ++ goto out_unlock; ++ } ++ } ++ if (ses_ptr->cdata.init != 0) { ++ int blocksize = ses_ptr->cdata.blocksize; ++ ++ if (unlikely(cop->len % blocksize)) { ++// derr(1, "data size (%u) isn't a multiple of block size (%u)", ++// cop->len, blocksize); ++ ret = -EINVAL; ++ goto out_unlock; ++ } ++ ++ cryptodev_cipher_set_iv(&ses_ptr->cdata, kcop->iv, ++ min(ses_ptr->cdata.ivsize, kcop->ivlen)); ++ } ++ ++ if (likely(cop->len)) { ++ if (cop->flags & COP_FLAG_NO_ZC) { ++ if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->src, ses_ptr->alignmask))) { ++ ++ cop->flags &= ~COP_FLAG_NO_ZC; ++ } ++ ++ if (unlikely(ses_ptr->alignmask && !IS_ALIGNED((unsigned long)cop->dst, ses_ptr->alignmask))) { ++ ++ cop->flags &= ~COP_FLAG_NO_ZC; ++ } ++ } ++ ++ if (cop->flags & COP_FLAG_NO_ZC) ++ ret = __crypto_run_std(ses_ptr, &kcop->cop); ++ else ++ ret = __crypto_run_zc(ses_ptr, kcop); ++ if (unlikely(ret)) ++ goto out_unlock; ++ } ++ ++ if (ses_ptr->cdata.init != 0) { ++ cryptodev_cipher_get_iv(&ses_ptr->cdata, kcop->iv, ++ min(ses_ptr->cdata.ivsize, kcop->ivlen)); ++ } ++ ++ if (ses_ptr->hdata.init != 0 && ++ ((cop->flags & COP_FLAG_FINAL) || ++ (!(cop->flags & COP_FLAG_UPDATE) || cop->len == 0))) { ++ ret = cryptodev_hash_final(&ses_ptr->hdata, kcop->hash_output); ++ if (unlikely(ret)) { ++// derr(0, "CryptoAPI failure: %d", ret); ++ goto out_unlock; ++ } ++ kcop->digestsize = ses_ptr->hdata.digestsize; ++ } ++ ++out_unlock: ++ crypto_put_session(ses_ptr); ++ return ret; ++} +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptodev_int.h b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptodev_int.h +new file mode 100644 +index 00000000..073adef6 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptodev_int.h +@@ -0,0 +1,79 @@ ++/* cipher stuff */ ++#ifndef CRYPTODEV_INT_H ++# define CRYPTODEV_INT_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#define PFX "cryptodev: " ++ ++extern int cryptodev_verbosity; ++ ++#define AESDMA_DEBUG (1) ++#if (AESDMA_DEBUG == 1) ++#define AESDMA_DBG(fmt, arg...) printk(KERN_DEBUG fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define AESDMA_DBG(fmt, arg...) ++#endif ++ ++struct fcrypt { ++ struct list_head list; ++ struct mutex sem; ++}; ++ ++/* kernel-internal extension to struct crypt_op */ ++struct kernel_crypt_op { ++ struct crypt_op cop; ++ ++ int ivlen; ++ __u8 iv[EALG_MAX_BLOCK_LEN]; ++ ++ int digestsize; ++ uint8_t hash_output[AALG_MAX_RESULT_LEN]; ++ ++ struct task_struct *task; ++ struct mm_struct *mm; ++}; ++ ++int crypto_run(struct fcrypt *fcr, struct kernel_crypt_op *kcop); ++ ++#include ++ ++/* other internal structs */ ++struct csession { ++ struct list_head entry; ++ struct mutex sem; ++ struct cipher_data cdata; ++ struct hash_data hdata; ++ uint32_t sid; ++ uint32_t alignmask; ++ ++ unsigned int array_size; ++ unsigned int used_pages; /* the number of pages that are used */ ++ /* the number of pages marked as NOT-writable; they preceed writeables */ ++ unsigned int readonly_pages; ++ struct page **pages; ++ struct scatterlist *sg; ++}; ++ ++struct csession *crypto_get_session_by_sid(struct fcrypt *fcr, uint32_t sid); ++ ++static inline void crypto_put_session(struct csession *ses_ptr) ++{ ++ mutex_unlock(&ses_ptr->sem); ++} ++int adjust_sg_array(struct csession *ses, int pagecount); ++ ++#endif /* CRYPTODEV_INT_H */ +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptutil.c b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptutil.c +new file mode 100644 +index 00000000..a670eaff +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptutil.c +@@ -0,0 +1,75 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include "mdrv_cryptutil.h" ++ ++/* These were taken from Maxim Levitsky's patch to lkml. ++ */ ++struct scatterlist *sg_advance(struct scatterlist *sg, int consumed) ++{ ++ while (consumed >= sg->length) { ++ consumed -= sg->length; ++ ++ sg = sg_next(sg); ++ if (!sg) ++ break; ++ } ++ ++ WARN_ON(!sg && consumed); ++ ++ if (!sg) ++ return NULL; ++ ++ sg->offset += consumed; ++ sg->length -= consumed; ++ ++ if (sg->offset >= PAGE_SIZE) { ++ struct page *page = ++ nth_page(sg_page(sg), sg->offset / PAGE_SIZE); ++ sg_set_page(sg, page, sg->length, sg->offset % PAGE_SIZE); ++ } ++ ++ return sg; ++} ++ ++/** ++ * sg_copy - copies sg entries from sg_from to sg_to, such ++ * as sg_to covers first 'len' bytes from sg_from. ++ */ ++int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len) ++{ ++ while (len > sg_from->length) { ++ len -= sg_from->length; ++ ++ sg_set_page(sg_to, sg_page(sg_from), ++ sg_from->length, sg_from->offset); ++ ++ sg_to = sg_next(sg_to); ++ sg_from = sg_next(sg_from); ++ ++ if (len || (!sg_from || !sg_to)) ++ return -ENOMEM; ++ } ++ ++ if (len) ++ sg_set_page(sg_to, sg_page(sg_from), ++ len, sg_from->offset); ++ sg_mark_end(sg_to); ++ return 0; ++} +\ No newline at end of file +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptutil.h b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptutil.h +new file mode 100644 +index 00000000..204de758 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptutil.h +@@ -0,0 +1,2 @@ ++int sg_copy(struct scatterlist *sg_from, struct scatterlist *sg_to, int len); ++struct scatterlist *sg_advance(struct scatterlist *sg, int consumed); +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptversion.h b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptversion.h +new file mode 100644 +index 00000000..b4680e12 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptversion.h +@@ -0,0 +1 @@ ++#define VERSION "aesdmadev" +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptzc.c b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptzc.c +new file mode 100644 +index 00000000..d5d434e6 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptzc.c +@@ -0,0 +1,199 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_cryptodev_int.h" ++#include "mdrv_cryptzc.h" ++#include "mdrv_cryptversion.h" ++ ++/* Helper functions to assist zero copy. ++ * This needs to be redesigned and moved out of the session. --nmav ++ */ ++ ++/* offset of buf in it's first page */ ++#define PAGEOFFSET(buf) ((unsigned long)buf & ~PAGE_MASK) ++ ++/* fetch the pages addr resides in into pg and initialise sg with them */ ++int __get_userbuf(uint8_t __user *addr, uint32_t len, int write, ++ unsigned int pgcount, struct page **pg, struct scatterlist *sg, ++ struct task_struct *task, struct mm_struct *mm) ++{ ++ int ret, pglen, i = 0; ++ struct scatterlist *sgp; ++ ++ if (unlikely(!pgcount || !len || !addr)) { ++ sg_mark_end(sg); ++ return 0; ++ } ++ ++ down_read(&mm->mmap_sem); ++ ret = get_user_pages(task, mm, ++ (unsigned long)addr, pgcount, write, 0, pg, NULL); ++ up_read(&mm->mmap_sem); ++ if (ret != pgcount) ++ return -EINVAL; ++ ++ sg_init_table(sg, pgcount); ++ ++ pglen = min((ptrdiff_t)(PAGE_SIZE - PAGEOFFSET(addr)), (ptrdiff_t)len); ++ sg_set_page(sg, pg[i++], pglen, PAGEOFFSET(addr)); ++ ++ len -= pglen; ++ for (sgp = sg_next(sg); len; sgp = sg_next(sgp)) { ++ pglen = min((uint32_t)PAGE_SIZE, len); ++ sg_set_page(sgp, pg[i++], pglen, 0); ++ len -= pglen; ++ } ++ sg_mark_end(sg_last(sg, pgcount)); ++ return 0; ++} ++ ++int adjust_sg_array(struct csession *ses, int pagecount) ++{ ++ struct scatterlist *sg; ++ struct page **pages; ++ int array_size; ++ ++ for (array_size = ses->array_size; array_size < pagecount; ++ array_size *= 2) ++ ; ++// ddebug(0, "reallocating from %d to %d pages", ++// ses->array_size, array_size); ++ pages = krealloc(ses->pages, array_size * sizeof(struct page *), ++ GFP_KERNEL); ++ if (unlikely(!pages)) ++ return -ENOMEM; ++ ses->pages = pages; ++ sg = krealloc(ses->sg, array_size * sizeof(struct scatterlist), ++ GFP_KERNEL); ++ if (unlikely(!sg)) ++ return -ENOMEM; ++ ses->sg = sg; ++ ses->array_size = array_size; ++ ++ return 0; ++} ++ ++void release_user_pages(struct csession *ses) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ses->used_pages; i++) { ++ if (!PageReserved(ses->pages[i])) ++ SetPageDirty(ses->pages[i]); ++ ++ if (ses->readonly_pages == 0) ++ flush_dcache_page(ses->pages[i]); ++ else ++ ses->readonly_pages--; ++ ++ page_cache_release(ses->pages[i]); ++ } ++ ses->used_pages = 0; ++} ++ ++/* make src and dst available in scatterlists. ++ * dst might be the same as src. ++ */ ++int get_userbuf(struct csession *ses, ++ void *__user src, unsigned int src_len, ++ void *__user dst, unsigned int dst_len, ++ struct task_struct *task, struct mm_struct *mm, ++ struct scatterlist **src_sg, ++ struct scatterlist **dst_sg) ++{ ++ int src_pagecount, dst_pagecount; ++ int rc; ++ ++ /* Empty input is a valid option to many algorithms & is tested by NIST/FIPS */ ++ /* Make sure NULL input has 0 length */ ++ if (!src && src_len) ++ src_len = 0; ++ ++ /* I don't know that null output is ever useful, but we can handle it gracefully */ ++ /* Make sure NULL output has 0 length */ ++ if (!dst && dst_len) ++ dst_len = 0; ++ ++ src_pagecount = PAGECOUNT(src, src_len); ++ dst_pagecount = PAGECOUNT(dst, dst_len); ++ ++ ses->used_pages = (src == dst) ? max(src_pagecount, dst_pagecount) ++ : src_pagecount + dst_pagecount; ++ ++ ses->readonly_pages = (src == dst) ? 0 : src_pagecount; ++ ++ if (ses->used_pages > ses->array_size) { ++ rc = adjust_sg_array(ses, ses->used_pages); ++ if (rc) ++ return rc; ++ } ++ ++ if (src == dst) { /* inplace operation */ ++ /* When we encrypt for authenc modes we need to write ++ * more data than the ones we read. */ ++ if (src_len < dst_len) ++ src_len = dst_len; ++ rc = __get_userbuf(src, src_len, 1, ses->used_pages, ++ ses->pages, ses->sg, task, mm); ++ if (unlikely(rc)) { ++// derr(1, "failed to get user pages for data IO"); ++ return rc; ++ } ++ (*src_sg) = (*dst_sg) = ses->sg; ++ return 0; ++ } ++ ++ *src_sg = NULL; /* default to no input */ ++ *dst_sg = NULL; /* default to ignore output */ ++ ++ if (likely(src)) { ++ rc = __get_userbuf(src, src_len, 0, ses->readonly_pages, ++ ses->pages, ses->sg, task, mm); ++ if (unlikely(rc)) { ++// derr(1, "failed to get user pages for data input"); ++ return rc; ++ } ++ *src_sg = ses->sg; ++ } ++ ++ if (likely(dst)) { ++ const unsigned int writable_pages = ++ ses->used_pages - ses->readonly_pages; ++ struct page **dst_pages = ses->pages + ses->readonly_pages; ++ *dst_sg = ses->sg + ses->readonly_pages; ++ ++ rc = __get_userbuf(dst, dst_len, 1, writable_pages, ++ dst_pages, *dst_sg, task, mm); ++ if (unlikely(rc)) { ++// derr(1, "failed to get user pages for data output"); ++ release_user_pages(ses); /* FIXME: use __release_userbuf(src, ...) */ ++ return rc; ++ } ++ } ++ return 0; ++} +\ No newline at end of file +diff --git a/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptzc.h b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptzc.h +new file mode 100644 +index 00000000..c0dfd9ce +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/cryptodev/mdrv_cryptzc.h +@@ -0,0 +1,27 @@ ++#ifndef ZC_H ++# define ZC_H ++ ++#include "mdrv_cryptodev_int.h" ++ ++/* For zero copy */ ++int __get_userbuf(uint8_t __user *addr, uint32_t len, int write, ++ unsigned int pgcount, struct page **pg, struct scatterlist *sg, ++ struct task_struct *task, struct mm_struct *mm); ++void release_user_pages(struct csession *ses); ++ ++int get_userbuf(struct csession *ses, ++ void *__user src, unsigned int src_len, ++ void *__user dst, unsigned int dst_len, ++ struct task_struct *task, struct mm_struct *mm, ++ struct scatterlist **src_sg, ++ struct scatterlist **dst_sg); ++ ++/* buflen ? (last page - first page + 1) : 0 */ ++#define PAGECOUNT(buf, buflen) ((buflen) \ ++ ? ((((unsigned long)(buf + buflen - 1)) >> PAGE_SHIFT) - \ ++ (((unsigned long)(buf )) >> PAGE_SHIFT) + 1) \ ++ : 0) ++ ++#define DEFAULT_PREALLOC_PAGES 32 ++ ++#endif +diff --git a/drivers/mstar/crypto/infinity/halAESDMA.c b/drivers/mstar/crypto/infinity/halAESDMA.c +new file mode 100644 +index 00000000..9f7a5d76 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/halAESDMA.c +@@ -0,0 +1,546 @@ ++/* ++ *############################################################################# ++ * ++ * Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++ * All rights reserved. ++ * ++ * Unless otherwise stipulated in writing, any and all information contained ++ * herein regardless in any format shall remain the sole proprietary of ++ * MStar Semiconductor Inc. and be kept in strict confidence ++ * (¡§MStar Confidential Information¡¨) by the recipient. ++ * Any unauthorized act including without limitation unauthorized disclosure, ++ * copying, use, reproduction, sale, distribution, modification, disassembling, ++ * reverse engineering and compiling of the contents of MStar Confidential ++ * Information is unlawful and strictly prohibited. MStar hereby reserves the ++ * rights to any and all damages, losses, costs and expenses resulting therefrom. ++ * ++ *############################################################################# ++ */ ++ ++#ifndef _HAL_AESDMA_H_ ++#include "halAESDMA.h" ++#endif ++#include ++#if 0 ++void HAL_AESDMA_DisableXIUSelectCA9(void) ++{ ++ //disable AESDMA XIU select CA9 ++ RIU[(AESDMA_BASE_ADDR+(0x5F<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5F<<1))])&(~AESDMA_CTRL_XIU_SEL_CA9)); ++} ++ ++void HAL_AESDMA_WB2DMADisable(void) ++{ ++ // WB2DMA read & write disable ++ RIU[(DMA_SECURE_BASE_ADDR+(0x79<<1))]= ((RIU[(DMA_SECURE_BASE_ADDR+(0x79<<1))])&(~(DMA_SECURE_CTRL_WB2DMA_R_EN|DMA_SECURE_CTRL_WB2DMA_W_EN))); ++} ++ ++void HAL_AESDMA_ShaFromOutput(void) ++{ ++ // SHA from AESDMA output(XIU) ++ RIU[(AESDMA_BASE_ADDR+(0x5F<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5F<<1))])|(AESDMA_CTRL_SHA_FROM_OUT)); ++} ++ ++void HAL_AESDMA_ShaFromInput(void) ++{ ++ // SHA from AESDMA input(XIU) ++ RIU[(AESDMA_BASE_ADDR+(0x5F<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5F<<1))])|(AESDMA_CTRL_SHA_FROM_IN)); ++} ++#endif ++void HAL_AESDMA_INTMASK(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]) | (1<<7)); ++} ++ ++void HAL_AESDMA_INTDISABLE(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x5e<<1))]) & ~(1<<7)); ++} ++ ++ ++void HAL_AESDMA_SetXIULength(U32 u32Size) ++{ ++ // AESDMA XIU length (byte):54~55 ++ RIU[(AESDMA_BASE_ADDR+(0x54<<1))]= (U16)((0x0000ffff)&(u32Size)); ++ RIU[(AESDMA_BASE_ADDR+(0x55<<1))]= (U16)(((0xffff0000)&(u32Size))>>16); ++} ++ ++void HAL_AESDMA_UseHwKey(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))]= (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_HW_KEY); ++} ++ ++void HAL_AESDMA_UseEfuseKey(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))]= (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_EFUSE_KEY); ++} ++ ++void HAL_AESDMA_UseCipherKey(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))]= (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_CIPHER_KEY); ++} ++ ++void HAL_AESDMA_CipherEncrypt(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))]) & (~AESDMA_CTRL_CIPHER_DECRYPT)); ++} ++ ++void HAL_AESDMA_CipherDecrypt(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))])|(AESDMA_CTRL_CIPHER_DECRYPT)); ++} ++ ++void HAL_AESDMA_Enable(U16 u16engine) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))]) | u16engine); ++} ++ ++void HAL_AESDMA_Disable(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x51<<1))])&(~AESDMA_CTRL_AES_EN)); ++} ++ ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable) ++{ ++ // AESDMA fout_en ++ if(u8FileOutEnable==1) ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))]) | AESDMA_CTRL_FOUT_EN); ++ /*MCM*/ ++ //RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))]) | 0x1000); ++ //RIU[(AESDMA_BASE_ADDR+(0x77<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x77<<1))]) | 0x003F); ++ } ++ else ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])&(~AESDMA_CTRL_FOUT_EN)); ++ } ++} ++ ++void HAL_AESDMA_SetFileinAddr(U32 u32addr) ++{ ++ u32addr = u32addr & (~0xF0000000); //mask bit to avoid MIU/IMI wrap ++ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(AESDMA_BASE_ADDR+(0x52<<1))]= (U16)((0x0000ffff)&(u32addr)); ++ RIU[(AESDMA_BASE_ADDR+(0x53<<1))]= (U16)(((0xffff0000)&(u32addr))>>16); ++} ++ ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size) ++{ ++ u32addr = u32addr & (~0xF0000000); //mask bit to avoid MIU/IMI wrap ++ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(AESDMA_BASE_ADDR+(0x56<<1))]= (U16)((0x0000ffff)&(u32addr)); ++ RIU[(AESDMA_BASE_ADDR+(0x57<<1))]= (U16)(((0xffff0000)&(u32addr))>>16); ++ ++ RIU[(AESDMA_BASE_ADDR+(0x58<<1))]= (U16)((0x0000ffff)&(u32addr+u32Size-1)); ++ RIU[(AESDMA_BASE_ADDR+(0x59<<1))]= (U16)(((0xffff0000)&(u32addr+u32Size-1))>>16); ++} ++ ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key) ++{ ++ int i; ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] =((pu16Key[i] & 0x00FF)<<8)|((pu16Key[i] & 0xFF00)>>8); ++ } ++} ++ ++void HAL_AESDMA_SetIV(U16 *pu16IV) ++{ ++ int i; ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x6F-i)<<1))] = ((pu16IV[i] & 0x00FF)<<8)|((pu16IV[i] & 0xFF00)>>8); ++ } ++} ++ ++void HAL_AESDMA_SetChainModeECB(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = (RIU[(AESDMA_BASE_ADDR+(0x51<<1))] & AESDMA_CTRL_CHAINMODE_CLEAR) | AESDMA_CTRL_CHAINMODE_ECB; ++} ++ ++void HAL_AESDMA_SetChainModeCTR(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = (RIU[(AESDMA_BASE_ADDR+(0x51<<1))] & AESDMA_CTRL_CHAINMODE_CLEAR) | AESDMA_CTRL_CHAINMODE_CTR; ++} ++ ++void HAL_AESDMA_SetChainModeCBC(void) ++{ ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = (RIU[(AESDMA_BASE_ADDR+(0x51<<1))] & AESDMA_CTRL_CHAINMODE_CLEAR) | AESDMA_CTRL_CHAINMODE_CBC; ++} ++ ++void HAL_AESDMA_Reset(void) ++{ ++ int i; ++ ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))] = AESDMA_CTRL_SW_RST; ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x51<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x52<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x53<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x54<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x55<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x56<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x57<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x58<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x59<<1))] = 0; ++ RIU[(AESDMA_BASE_ADDR+(0x79<<1))] = (((RIU[(AESDMA_BASE_ADDR+(0x79<<1))]) & (~AESDMA_USE_SECRET_KEY_MASK)) | AESDMA_USE_CIPHER_KEY); ++ ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x67-i)<<1))] = 0; ++ } ++ for(i=0;i<8;i++) ++ { ++ RIU[(AESDMA_BASE_ADDR+((0x6F-i)<<1))] = 0; ++ } ++} ++ ++void HAL_AESDMA_Start(U8 u8AESDMAStart) ++{ ++ // AESDMA file start ++ if(u8AESDMAStart==1) ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])|(AESDMA_CTRL_FILE_ST)); ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])&(~AESDMA_CTRL_FILE_ST)); ++ } ++ else ++ { ++ RIU[(AESDMA_BASE_ADDR+(0x50<<1))]= ((RIU[(AESDMA_BASE_ADDR+(0x50<<1))])&(~AESDMA_CTRL_FILE_ST)); ++ } ++} ++ ++U16 HAL_AESDMA_GetStatus(void) ++{ ++ return RIU[(AESDMA_BASE_ADDR+(0x7F<<1))]; ++} ++ ++void HAL_RSA_ClearInt(void) ++{ ++ //RSA interrupt clear ++ RIU[(RSA_BASE_ADDR+(0x27<<1))]= ((RIU[(RSA_BASE_ADDR+(0x27<<1))])|(RSA_INT_CLR)); ++} ++ ++void HAL_RSA_Reset(void) ++{ ++ //RSA Rst ++ RIU[(RSA_BASE_ADDR+(0x28<<1))]= ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(RSA_CTRL_RSA_RST)); ++ RIU[(RSA_BASE_ADDR+(0x28<<1))]= ((RIU[(RSA_BASE_ADDR+(0x28<<1))])&(~RSA_CTRL_RSA_RST)); ++} ++ ++void HAL_RSA_Ind32Ctrl(U8 u8dirction) ++{ ++ //[1] reg_ind32_direction 0: Read. 1: Write ++ if(u8dirction==1) ++ { ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])|(RSA_IND32_CTRL_DIRECTION_WRITE)); ++ } ++ else ++ { ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])&(~RSA_IND32_CTRL_DIRECTION_WRITE)); ++ } ++ //[2] reg_addr_auto_inc : Set 1 to enable address auto-increment after finishing read/write ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])|(RSA_IND32_CTRL_ADDR_AUTO_INC)); ++ ++ //[3] Set 1 to enable access auto-start after writing Data[31:16] ++ RIU[(RSA_BASE_ADDR+(0x21<<1))]= ((RIU[(RSA_BASE_ADDR+(0x21<<1))])|(RSA_IND32_CTRL_ACCESS_AUTO_START)); ++} ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh) ++{ ++ // RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_E+i))>>8)&0xFF00)|(((*(ptr_E+i))>>24)&0xFF); ++ // RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_E+i))>>8)&0xFF)|(((*(ptr_E+i))<<8)&0xFF00); ++ U32 i; ++ U8 lentgh = u8Signlentgh; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_A_BASE_ADDR; //RSA A addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ for( i = 0; i < lentgh ; i++ ) ++ { ++ //RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_Sign+63-i))>>8)&0xFF00)|(((*(ptr_Sign+63-i))>>24)&0xFF); ++ //RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_Sign+63-i))>>8)&0xFF)|(((*(ptr_Sign+63-i))<<8)&0xFF00); ++ ++// RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_Sign + i))>>8)&0xFF00)|(((*(ptr_Sign + i))>>24)&0xFF); ++// RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_Sign + i))>>8)&0xFF)|(((*(ptr_Sign + i))<<8)&0xFF00); ++ ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_Sign + (lentgh-1) - i))>>8)&0xFF00)|(((*(ptr_Sign + (lentgh-1) - i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_Sign + (lentgh-1) - i))>>8)&0xFF)|(((*(ptr_Sign + (lentgh-1) - i))<<8)&0xFF00); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++/* ++void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign) ++{ ++ ++ S32 i; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_A_BASE_ADDR; //RSA A addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ for( i = 127; i >= 0; i -= 2 ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)( ((*(ptr_Sign+i) << 8) & 0xFF00) | ((*(ptr_Sign+i) >> 8) & 0xFF) ); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)( ((*(ptr_Sign+i-1) << 8) & 0xFF00) | ((*(ptr_Sign+i-1) >> 8) & 0xFF) ); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++}*/ ++ ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh) ++{ ++ U32 i; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_E_BASE_ADDR; //RSA E addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xA<<1))]=(U16)((0x0000ffff)&(U32)(ptr_E)); //write ptr_E addr to por_status(0x10050A) ++ ++ for( i = 0; i < u8Elentgh ; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_E + i))>>8)&0xFF00)|(((*(ptr_E + i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_E + i))>>8)&0xFF)|(((*(ptr_E + i))<<8)&0xFF00); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++ ++void HAL_RSA_LoadKeyN(U32 *ptr_N ,U8 u8Nlentgh) ++{ ++ U32 i; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_N_BASE_ADDR; //RSA N addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xB<<1))]=(U16)((0x0000ffff)&(U32)(ptr_N)); //write ptr_N addr to por_status(0x10050B) ++ ++ for( i = 0; i < u8Nlentgh; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_N+i))>>8)&0xFF00)|(((*(ptr_N+i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_N+i))>>8)&0xFF)|(((*(ptr_N+i))<<8)&0xFF00); ++ } ++ ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++ ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N,U8 u8Nlentgh) ++{ ++ U32 i; ++ U8 lentgh = u8Nlentgh; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_N_BASE_ADDR; //RSA N addr ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xB<<1))]=(U16)((0x0000ffff)&(U32)(ptr_N)); //write ptr_N addr to por_status(0x10050B) ++ ++ for( i = 0; i < lentgh; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_N + (lentgh-1) - i))>>8)&0xFF00)|(((*(ptr_N + (lentgh-1) - i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_N + (lentgh-1) - i))>>8)&0xFF)|(((*(ptr_N + (lentgh-1) - i))<<8)&0xFF00); ++ } ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++} ++ ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_E,U8 u8Elentgh) ++{ ++ U32 i; ++ U8 lentgh = u8Elentgh; ++ ++ RIU[(RSA_BASE_ADDR+(0x22<<1))]= RSA_E_BASE_ADDR; ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); //RSA start ++ ++ //RIU[(POR_STATUS_BASE_ADDR+(0xB<<1))]=(U16)((0x0000ffff)&(U32)(ptr_N)); //write ptr_N addr to por_status(0x10050B) ++ ++ for( i = 0; i < lentgh; i++ ) ++ { ++ RIU[(RSA_BASE_ADDR+(0x23<<1))]= (U16)(((*(ptr_E + (lentgh-1) - i))>>8)&0xFF00)|(((*(ptr_E + (lentgh-1) - i))>>24)&0xFF); ++ RIU[(RSA_BASE_ADDR+(0x24<<1))]= (U16)(((*(ptr_E + (lentgh-1) - i))>>8)&0xFF)|(((*(ptr_E + (lentgh-1) - i))<<8)&0xFF00); ++ } ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); //RSA stop ++ ++} ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen) ++{ ++ //[13:8] n_len_e: key length, if hardware key set, this register is ignored and hardware internal using 3f ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(u16keylen<<8)); ++} ++ ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey) ++{ ++ //[1] hw_key_e : 0 : software key, 1: hardware key ++ //[2] e_pub_e : 0: pvivate key, 1: public key ++ if(u8hwkey==1) ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(RSA_SEL_HW_KEY)); ++ } ++ else ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])&(~RSA_SEL_HW_KEY)); ++ } ++ ++ if(u8pubkey==1) ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])|(RSA_SEL_PUBLIC_KEY)); ++ } ++ else ++ { ++ RIU[(RSA_BASE_ADDR+(0x28<<1))] = ((RIU[(RSA_BASE_ADDR+(0x28<<1))])&(~RSA_SEL_PUBLIC_KEY)); ++ } ++ ++} ++ ++void HAL_RSA_ExponetialStart(void) ++{ ++ //RSA exp start ++ RIU[(RSA_BASE_ADDR+(0x27<<1))] = ((RIU[(RSA_BASE_ADDR+(0x27<<1))])|(RSA_EXP_START)); ++} ++ ++U16 HAL_RSA_GetStatus(void) ++{ ++ return RIU[(RSA_BASE_ADDR+(0x29<<1))]; ++} ++ ++void HAL_RSA_FileOutStart(void) ++{ ++ //RSA ind32_start ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])|(RSA_IND32_START)); ++} ++ ++void HAL_RSA_FileOutEnd(void) ++{ ++ //RSA ind32_start ++ RIU[(RSA_BASE_ADDR+(0x20<<1))]= ((RIU[(RSA_BASE_ADDR+(0x20<<1))])&(~RSA_IND32_START)); ++} ++ ++void HAL_RSA_SetFileOutAddr(U32 u32offset) ++{ ++ //RSA ind32_addr ++ RIU[(RSA_BASE_ADDR+(0x22<<1))] = (U16)(RSA_Z_BASE_ADDR + u32offset); ++} ++ ++U32 HAL_RSA_FileOut(void) ++{ ++ U32 output; ++ output = (U16)(((RIU[(RSA_BASE_ADDR+(0x26<<1))] >>8 )& 0xff )|((RIU[(RSA_BASE_ADDR+(0x26<<1))] << 8 )& 0xff00 )) ; ++ output = output | ((((RIU[(RSA_BASE_ADDR+(0x25<<1))]>>8)& 0xff)|((RIU[(RSA_BASE_ADDR+(0x25<<1))]<<8)& 0xff00)) << 16); ++ ++ return output; ++} ++ ++void HAL_SHA_Reset(void) ++{ ++ //SHA_Reset ++ RIU[SHARNG_BASE_ADDR+(0x08<<1)]= (RIU[SHARNG_BASE_ADDR+(0x08<<1)]|(SHARNG_CTRL_SHA_RST)); ++ RIU[SHARNG_BASE_ADDR+(0x08<<1)]= (RIU[SHARNG_BASE_ADDR+(0x08<<1)]&(~SHARNG_CTRL_SHA_RST)); ++ ++ //Clear reg_dma4_ctrl_s ++ RIU[SHARNG_BASE_ADDR+(0x5d<<1)]= 0; ++} ++ ++void HAL_SHA_SetAddress(U32 u32Address) ++{ ++ /**/ ++ // u32Address = u32Address & (~0xF0000000); //mask bit to avoid MIU/IMI wrap ++ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(SHARNG_BASE_ADDR+(0x0A<<1))]= (U16)((0x0000ffff)&(u32Address)); ++ RIU[(SHARNG_BASE_ADDR+(0x0B<<1))]= (U16)(((0xffff0000)&(u32Address))>>16); ++ ++ // Bypass scatter & gather address ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(1<<11)); ++} ++ ++void HAL_SHA_SetLength(U32 u32Size) ++{ ++ //SHA_SetLength:5c~5d(sha_message_length) ++ RIU[(SHARNG_BASE_ADDR+(0x0C<<1))]= (U16)((0x0000ffff)&(u32Size)); ++ RIU[(SHARNG_BASE_ADDR+(0x0D<<1))]= (U16)(((0xffff0000)&(u32Size))>>16); ++} ++ ++void HAL_SHA_SelMode(U8 u8sha256) ++{ ++ //SHA_SelMode:58~59(sha_ctrl & sha_scattergather_size) ++ if(u8sha256==1) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_SEL_SHA256)); ++ } ++ else ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_SEL_SHA256)); ++ } ++} ++ ++void HAL_SHA_ManualMode(U8 bManualMode) ++{ ++ if(bManualMode==1) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_WORK_MODE_MANUAL)); ++ } ++ else ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_WORK_MODE_MANUAL)); ++ } ++} ++ ++U16 HAL_SHA_GetStatus(void) ++{ ++ return (RIU[(SHARNG_BASE_ADDR+(0x0F<<1))]); ++} ++ ++void HAL_SHA_Clear(void) ++{ ++ //Set "1" to idle state after reg_read_sha_ready = 1 ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_CLR)); ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_CLR)); ++} ++ ++void HAL_SHA_Start(void) ++{ ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])|(SHARNG_CTRL_SHA_FIRE_ONCE)); ++ RIU[(SHARNG_BASE_ADDR+(0x08<<1))]= ((RIU[(SHARNG_BASE_ADDR+(0x08<<1))])&(~SHARNG_CTRL_SHA_FIRE_ONCE)); ++} ++ ++void HAL_SHA_Out(U32 u32Buf) ++{ ++ U32 index; ++ ++// output = (U16)(((RIU[(RSA_BASE_ADDR+(0x26<<1))] >>8 )& 0xff )|((RIU[(RSA_BASE_ADDR+(0x26<<1))] << 8 )& 0xff00 )) ; ++// output = output | ((((RIU[(RSA_BASE_ADDR+(0x25<<1))]>>8)& 0xff)|((RIU[(RSA_BASE_ADDR+(0x25<<1))]<<8)& 0xff00)) << 16); ++ ++ //SHA_Out ++ for( index = 0; index < 16; index++ ) ++ { ++ *((U16 *)u32Buf +(15-index)) = (U16)(RIU[(SHARNG_BASE_ADDR + (0x10<<1) + index*2)]>>8&0xff)|(U16)(RIU[(SHARNG_BASE_ADDR + (0x10<<1) + index*2)]<<8&0xff00); ++ } ++} ++ ++void HAL_SHA_Write_InitValue(U32 u32Buf) ++{ ++ U32 index; ++ ++ //SHA_Out ++ for( index = 0; index < 16; index++ ) ++ { ++ RIU[(SHARNG_BASE_ADDR+(0x10<<1)+index*2)] = *((U16 *)u32Buf + index); ++ } ++} ++ ++U32 HAL_SHA_ReadWordCnt(void) ++{ ++ return RIU[(SHARNG_BASE_ADDR+(0x2E<<1))] | (RIU[(SHARNG_BASE_ADDR+(0x2F<<1))] << 16); ++} ++ ++void HAL_SHA_WriteWordCnt(U32 u32Val) ++{ ++ RIU[(SHARNG_BASE_ADDR+(0x40<<1))] = (U16)(u32Val & 0xFFFF); ++ RIU[(SHARNG_BASE_ADDR+(0x41<<1))] = (U16)(u32Val >> 16); ++} ++void HAL_MCM(U32 u32Val) ++{ ++ RIU[(0x113200+(0x01<<1))]= (U16)u32Val; ++} +diff --git a/drivers/mstar/crypto/infinity/halAESDMA.h b/drivers/mstar/crypto/infinity/halAESDMA.h +new file mode 100644 +index 00000000..13659f90 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/halAESDMA.h +@@ -0,0 +1,208 @@ ++/* ++ *############################################################################# ++ * ++ * Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++ * All rights reserved. ++ * ++ * Unless otherwise stipulated in writing, any and all information contained ++ * herein regardless in any format shall remain the sole proprietary of ++ * MStar Semiconductor Inc. and be kept in strict confidence ++ * (¡§MStar Confidential Information¡¨) by the recipient. ++ * Any unauthorized act including without limitation unauthorized disclosure, ++ * copying, use, reproduction, sale, distribution, modification, disassembling, ++ * reverse engineering and compiling of the contents of MStar Confidential ++ * Information is unlawful and strictly prohibited. MStar hereby reserves the ++ * rights to any and all damages, losses, costs and expenses resulting therefrom. ++ * ++ *############################################################################# ++ */ ++ ++#ifndef _HAL_AESDMA_H_ ++#define _HAL_AESDMA_H_ ++ ++ ++#define CONFIG_RIU_BASE_ADDRESS 0xFD000000 ++#define CONFIG_XIU_BASE_ADDRESS 0x1F600000 ++#define CONFIG_EMMC_BASE_ADDRESS 0x1FC00000 ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#define REG(Reg_Addr) (*(volatile unsigned short *)(Reg_Addr)) ++#define SECURE_DEBUG(reg_addr, val) REG((reg_addr)) = (val) ++#define SECURE_DEBUG_REG (CONFIG_RIU_BASE_ADDRESS + (0x100518 << 1)) ++#define ROM_AUTHEN_REG (CONFIG_RIU_BASE_ADDRESS + (0x0038E0 << 1)) ++ ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define RIU ((unsigned short volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define RIU8 ((unsigned char volatile *) CONFIG_RIU_BASE_ADDRESS) ++#define XIU ((unsigned int volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define XIU8 ((unsigned char volatile *) CONFIG_XIU_BASE_ADDRESS) ++#define MIU_BASE (0x40000000) ++#define VIR_TO_PHY(x) ((u32)(x) - MIU_BASE) ++#define AESDMA_BASE_ADDR (0x112200) ++#define SHARNG_BASE_ADDR (0x112200) ++#define RSA_BASE_ADDR (0x112200) ++//#define DMA_SECURE_BASE_ADDR (0x113D00) ++//#define MAILBOX_BASE_ADDR (0x103380) ++//#define POR_STATUS_BASE_ADDR (0x100500) ++ ++#define RSA_SIGNATURE_LEN (256) ++//#define SHA256_DIGEST_SIZE (32) ++ ++#define RSA_A_BASE_ADDR (0x80) ++#define RSA_E_BASE_ADDR (0x00) ++#define RSA_N_BASE_ADDR (0x40) ++#define RSA_Z_BASE_ADDR (0xC0) ++ ++#define SECURE_RSA_OUT_DRAM_ADDRESS (0x20109000) ++#define SECURE_SHA_OUT_DRAM_ADDRESS (0x20109100) ++#define SECURE_RSA_OUT_SRAM_ADDRESS (0x1FC03600) ++#define SECURE_SHA_OUT_SRAM_ADDRESS (0x1FC03680) ++#define SECURE_WB_FIFO_OUT_ADDRESS (0x1FC01C00) ++ ++#define SHARNG_CTRL_SHA_SEL_SHA256 0x0200 ++#define SHARNG_CTRL_SHA_CLR 0x0040 ++#define SHARNG_CTRL_SHA_MSG_BLOCK_NUM 0x0001 ++#define SHARNG_CTRL_SHA_FIRE_ONCE 0x0001 ++#define SHARNG_CTRL_SHA_READY 0x0001 ++#define SHARNG_CTRL_SHA_RST 0x0080 ++#define SHARNG_CTRL_SHA_BUSY 0x0002 ++#define SHARNG_CTRL_WORK_MODE_MANUAL 0x4000 ++ ++#define RSA_INT_CLR 0x0002 ++#define RSA_CTRL_RSA_RST 0x0001 ++#define RSA_IND32_START 0x0001 ++#define RSA_IND32_CTRL_DIRECTION_WRITE 0x0002 ++#define RSA_IND32_CTRL_ADDR_AUTO_INC 0x0004 ++#define RSA_IND32_CTRL_ACCESS_AUTO_START 0x0008 ++#define RSA_EXP_START 0x0001 ++#define RSA_STATUS_RSA_BUSY 0x0001 ++#define RSA_STATUS_RSA_DONE 0x0002 ++#define RSA_SEL_HW_KEY 0x0002 ++#define RSA_SEL_PUBLIC_KEY 0x0004 ++ ++#define DMA_SECURE_CTRL_AES_SECURE_PROTECT 0x0001 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY1 0x0020 ++#define DMA_SECURE_CTRL_AES_SECRET_KEY2 0x0040 ++#define DMA_SECURE_CTRL_WB2DMA_R_EN 0x0200 ++#define DMA_SECURE_CTRL_WB2DMA_W_EN 0x0100 ++ ++#define AESDMA_CTRL_XIU_SEL_CA9 0x1000 ++#define AESDMA_CTRL_MIU_SEL_12M 0x8000 ++#define AESDMA_CTRL_SHA_FROM_IN 0x0100 ++#define AESDMA_CTRL_SHA_FROM_OUT 0x0200 ++#define AESDMA_CTRL_DMA_DONE 0x0001 ++ ++#define AESDMA_CTRL_FILE_ST 0x0001 ++#define AESDMA_CTRL_FOUT_EN 0x0100 ++#define AESDMA_CTRL_CBC_MODE 0x2000 ++#define AESDMA_CTRL_CIPHER_DECRYPT 0x0200 ++#define AESDMA_CTRL_AES_EN 0x0100 ++#define AESDMA_CTRL_DES_EN 0x0004 ++#define AESDMA_CTRL_TDES_EN 0x0008 ++#define AESDMA_CTRL_CHAINMODE_ECB 0x0000 ++#define AESDMA_CTRL_CHAINMODE_CTR (0x0001<<12) ++#define AESDMA_CTRL_CHAINMODE_CBC (0x0001<<13) ++#define AESDMA_CTRL_CHAINMODE_CLEAR (~(AESDMA_CTRL_CHAINMODE_ECB|AESDMA_CTRL_CHAINMODE_CTR|AESDMA_CTRL_CHAINMODE_CBC)) ++#define AESDMA_CTRL_SW_RST (0x0001<<7) ++//#define AESDMA_CTRL_USE_SECRET_KEY 0x1000 ++#define AESDMA_USE_SECRET_KEY_MASK (0x0003<<5) ++#define AESDMA_USE_CIPHER_KEY 0x0000 ++#define AESDMA_USE_EFUSE_KEY (0x0001<<5) ++#define AESDMA_USE_HW_KEY (0x0002<<5) ++ ++#define XIU_STATUS_W_RDY 0x0001 ++#define XIU_STATUS_W_ERR 0x0008 ++#define XIU_STATUS_W_LEN 0x00F0 ++#define XIU_STATUS_R_RDY 0x0100 ++#define XIU_STATUS_R_ERR 0x0800 ++#define XIU_STATUS_R_LEN 0xF000 ++ ++ ++void HAL_AESDMA_DisableXIUSelectCA9(void); ++void HAL_AESDMA_WB2DMADisable(void); ++void HAL_AESDMA_ShaFromOutput(void); ++void HAL_AESDMA_ShaFromInput(void); ++void HAL_AESDMA_SetXIULength(U32 u32Size); ++void HAL_AESDMA_UseHwKey(void); ++void HAL_AESDMA_UseEfuseKey(void); ++void HAL_AESDMA_UseCipherKey(void); ++void HAL_AESDMA_CipherEncrypt(void); ++void HAL_AESDMA_CipherDecrypt(void); ++void HAL_AESDMA_Enable(U16 engine); ++void HAL_AESDMA_Disable(void); ++void HAL_AESDMA_FileOutEnable(U8 u8FileOutEnable); ++void HAL_AESDMA_SetFileinAddr(U32 u32addr); ++void HAL_AESDMA_SetFileoutAddr(U32 u32addr, U32 u32Size); ++void HAL_AESDMA_SetCipherKey(U16 *pu16Key); ++void HAL_AESDMA_SetIV(U16 *pu16IV); ++void HAL_AESDMA_SetChainModeECB(void); ++void HAL_AESDMA_SetChainModeCTR(void); ++void HAL_AESDMA_SetChainModeCBC(void); ++void HAL_AESDMA_Reset(void); ++void HAL_AESDMA_Start(U8 u8AESDMAStart); ++U16 HAL_AESDMA_GetStatus(void); ++void HAL_AESDMA_INTMASK(void); ++void HAL_AESDMA_INTDISABLE(void); ++ ++void HAL_RSA_ClearInt(void); ++void HAL_RSA_Reset(void); ++void HAL_RSA_Ind32Ctrl(U8 u8dirction); ++ ++void HAL_RSA_LoadSignInverse(U32 *ptr_Sign, U8 u8Signlentgh); ++//void HAL_RSA_LoadSignInverse_2byte(U16 *ptr_Sign); ++void HAL_RSA_LoadKeyE(U32 *ptr_E, U8 u8Elentgh); ++void HAL_RSA_LoadKeyN(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyNInverse(U32 *ptr_N, U8 u8Nlentgh); ++void HAL_RSA_LoadKeyEInverse(U32 *ptr_A, U8 u8Alentgh); ++ ++void HAL_RSA_SetKeyLength(U16 u16keylen); ++void HAL_RSA_SetKeyType(U8 u8hwkey, U8 u8pubkey); ++void HAL_RSA_ExponetialStart(void); ++U16 HAL_RSA_GetStatus(void); ++void HAL_RSA_FileOutStart(void); ++void HAL_RSA_FileOutEnd(void); ++void HAL_RSA_SetFileOutAddr(U32 u32offset); ++U32 HAL_RSA_FileOut(void); ++void HAL_SHA_Reset(void); ++void HAL_SHA_SetAddress(U32 u32Address); ++void HAL_SHA_SetLength(U32 u32Size); ++void HAL_SHA_SelMode(U8 u8sha256); ++void HAL_SHA_ManualMode(U8 bManualMode); ++U16 HAL_SHA_GetStatus(void); ++void HAL_SHA_Clear(void); ++void HAL_SHA_Start(void); ++void HAL_SHA_Out(U32 u32Buf); ++void HAL_SHA_Write_InitValue(U32 u32Buf); ++U32 HAL_SHA_ReadWordCnt(void); ++void HAL_SHA_WriteWordCnt(U32 u32Val); ++void HAL_MCM(U32 u32Val); ++ ++ ++ ++#endif +diff --git a/drivers/mstar/crypto/infinity/mdrv_aes.c b/drivers/mstar/crypto/infinity/mdrv_aes.c +new file mode 100644 +index 00000000..577c28ad +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/mdrv_aes.c +@@ -0,0 +1,1183 @@ ++/* ++ *############################################################################# ++ * ++ * Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++ * All rights reserved. ++ * ++ * Unless otherwise stipulated in writing, any and all information contained ++ * herein regardless in any format shall remain the sole proprietary of ++ * MStar Semiconductor Inc. and be kept in strict confidence ++ * (!¡±MStar Confidential Information!¡L) by the recipient. ++ * Any unauthorized act including without limitation unauthorized disclosure, ++ * copying, use, reproduction, sale, distribution, modification, disassembling, ++ * reverse engineering and compiling of the contents of MStar Confidential ++ * Information is unlawful and strictly prohibited. MStar hereby reserves the ++ * rights to any and all damages, losses, costs and expenses resulting therefrom. ++ * ++ *############################################################################# ++ */ ++#if 1 ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "halAESDMA.h" ++#include "mdrv_aes.h" ++#include ++ ++#else ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#define AESDMA_DEBUG (0) ++#if (AESDMA_DEBUG == 1) ++#define AESDMA_DBG(fmt, arg...) printk(KERN_ALERT fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define AESDMA_DBG(fmt, arg...) ++#endif ++ ++ ++#define AESDMA_DES (0) ++ ++#define LOOP_CNT 100000 //100ms ++ ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++#define MS_ASSERT(a) ++#define CRYPTO_MUTEX_WAIT_TIME 3000 ++ ++struct mutex _mtcrypto_lock; ++ ++extern int infinity_sha_create(void); ++extern int infinity_sha_destroy(void); ++extern struct miscdevice rsadev; ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr ) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++void _ms_aes_mem_free(void) ++{ ++ //aesdma_vir_SHABuf_addr ++ if(ALLOC_DMEM.aesdma_vir_addr != 0){ ++ //printk( "%s mem free \n",ALLOC_DMEM.DMEM_AES_ENG_INPUT); ++ free_dmem(ALLOC_DMEM.DMEM_AES_ENG_INPUT,AESDMA_ALLOC_MEMSIZE,ALLOC_DMEM.aesdma_vir_addr,ALLOC_DMEM.aesdma_phy_addr); ++ ALLOC_DMEM.aesdma_vir_addr = 0; ++ ALLOC_DMEM.aesdma_phy_addr = 0; ++ } ++ if(ALLOC_DMEM.aesdma_vir_SHABuf_addr != 0){ ++ //printk( "%s mem free \n",ALLOC_DMEM.DMEM_AES_ENG_SHABUF); ++ free_dmem(ALLOC_DMEM.DMEM_AES_ENG_SHABUF,AESDMA_ALLOC_MEMSIZE_TEMP,ALLOC_DMEM.aesdma_vir_SHABuf_addr,ALLOC_DMEM.aesdma_phy_SHABuf_addr); ++ ALLOC_DMEM.aesdma_vir_SHABuf_addr = 0; ++ ALLOC_DMEM.aesdma_phy_SHABuf_addr = 0; ++ } ++} ++ ++void enableClock(void) ++{ ++ int num_parents = 0, i = 0; ++ struct clk **aesdma_clks; ++ ++ num_parents = of_clk_get_parent_count(psg_mdrv_aesdma->dev.of_node); ++ ++ if(num_parents > 0) ++ { ++ aesdma_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if (aesdma_clks == NULL) ++ { ++ printk( "[AESDMA] -ENOMEM\n" ); ++ return; ++ } ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ aesdma_clks[i] = of_clk_get(psg_mdrv_aesdma->dev.of_node, i); ++ ++ if (IS_ERR(aesdma_clks[i])) ++ { ++ printk( "[AESDMA] Fail to get clk!\n" ); ++ kfree(aesdma_clks); ++ return; ++ } ++ else ++ { ++ clk_prepare_enable(aesdma_clks[i]); ++ } ++ } ++ kfree(aesdma_clks); ++ } ++} ++ ++void disableClock(void) ++{ ++ int num_parents = 0, i = 0; ++ ++ struct clk **aesdma_clks; ++ ++ num_parents = of_clk_get_parent_count(psg_mdrv_aesdma->dev.of_node); ++ if(num_parents > 0) ++ { ++ aesdma_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ if (aesdma_clks == NULL) ++ { ++ printk( "[AESDMA] -ENOMEM\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ aesdma_clks[i] = of_clk_get(psg_mdrv_aesdma->dev.of_node, i); ++ if (IS_ERR(aesdma_clks[i])) ++ { ++ printk( "[AESDMA] Fail to get clk!\n" ); ++ kfree(aesdma_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(aesdma_clks[i]); ++ } ++ } ++ kfree(aesdma_clks); ++ } ++} ++ ++void allocMem(U32 len) ++{ ++ if (!(ALLOC_DMEM.aesdma_vir_addr = alloc_dmem(ALLOC_DMEM.DMEM_AES_ENG_INPUT, ++ len,//AESDMA_ALLOC_MEMSIZE, ++ &ALLOC_DMEM.aesdma_phy_addr))){ ++ printk("[input]unable to allocate aesdma memory\n"); ++ } ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, len);//AESDMA_ALLOC_MEMSIZE); ++} ++ ++extern void do_gettimeofday(struct timeval *tv); ++ ++static unsigned int infinity_aes_crypt(struct infinity_aes_op *op, int engine) ++{ ++// int bUseHwKey = false; ++ struct timeval now; ++ suseconds_t start = 0; ++ suseconds_t end = 0; ++ ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, op->len);//AESDMA_ALLOC_MEMSIZE ++ memcpy(ALLOC_DMEM.aesdma_vir_addr,op->src,op->len); ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ Chip_Flush_MIU_Pipe(); ++ HAL_AESDMA_Reset(); ++ ++ HAL_AESDMA_SetFileinAddr(Chip_Phys_to_MIU(ALLOC_DMEM.aesdma_phy_addr)); ++ HAL_AESDMA_SetXIULength(op->len); ++ HAL_AESDMA_SetFileoutAddr(Chip_Phys_to_MIU(ALLOC_DMEM.aesdma_phy_addr),(op->len)); ++// for(i=0;ikey[i] != 0) ++// { ++// bUseHwKey = false; ++// break; ++// } ++// } ++ ++// if(bUseHwKey) ++// { ++// HAL_AESDMA_UseHwKey(); ++// } ++// else ++// { ++ HAL_AESDMA_UseCipherKey(); ++ HAL_AESDMA_SetCipherKey((U16*)op->key); ++// } ++ ++ if ((op->mode == AES_MODE_CBC) || (op->mode == AES_MODE_CTR)) ++ { ++ HAL_AESDMA_SetIV((U16*)op->iv); ++ } ++ ++ HAL_AESDMA_Enable(engine); ++ switch(op->mode) ++ { ++ case AES_MODE_ECB: ++ HAL_AESDMA_SetChainModeECB(); ++ break; ++ ++ case AES_MODE_CBC: ++ HAL_AESDMA_SetChainModeCBC(); ++ break; ++ ++ case AES_MODE_CTR: ++ HAL_AESDMA_SetChainModeCTR(); ++ break; ++ ++ default: ++ return -1; ++ } ++ ++ if(op->dir == AES_DIR_DECRYPT) ++ { ++ HAL_AESDMA_CipherDecrypt(); ++ } ++ ++ HAL_AESDMA_FileOutEnable(1); ++ HAL_AESDMA_Start(1); ++ ++ // Wait for ready. ++ do_gettimeofday(&now); ++ start = now.tv_usec; /* microseconds */ ++ ++ while(((HAL_AESDMA_GetStatus() & AESDMA_CTRL_DMA_DONE) != AESDMA_CTRL_DMA_DONE) && end < 1000) ++ { ++ do_gettimeofday(&now); ++ end = now.tv_usec - start; ++ } ++ AESDMA_DBG("Elapsed time: %lu s %lu us\n", now.tv_sec ,end); ++ ++ if (end >= LOOP_CNT){ ++ printk("Time out %d us\n", LOOP_CNT); ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, op->len); ++ memcpy(op->dst, ALLOC_DMEM.aesdma_vir_addr, op->len); ++ return -1; ++ } ++ else ++ { ++ memcpy(op->dst, ALLOC_DMEM.aesdma_vir_addr, op->len); ++ } ++ ++ Chip_Flush_MIU_Pipe(); ++ HAL_AESDMA_Reset(); ++ return op->len ; ++} ++ ++/* CRYPTO-API Functions */ ++ ++static int infinity_setkey_cip(struct crypto_tfm *tfm, const u8 *key, unsigned int len) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ unsigned int ret = 0; ++ ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ op->keylen = len; ++ if (len == AES_KEYSIZE_128) { ++ memcpy(op->key, key, len); ++ return 0; ++ } ++ ++ if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) { ++ /* not supported at all */ ++ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; ++ return -EINVAL; ++ } ++ ++ /* ++ * The requested key size is not supported by HW, do a fallback ++ */ ++ op->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; ++ op->fallback.cip->base.crt_flags |= (tfm->crt_flags & CRYPTO_TFM_REQ_MASK); ++ ++ ret = crypto_cipher_setkey(op->fallback.cip, key, len); ++ if (ret) { ++ tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; ++ tfm->crt_flags |= (op->fallback.cip->base.crt_flags & CRYPTO_TFM_RES_MASK); ++ } ++ return ret; ++} ++ ++static int infinity_setkey_blk(struct crypto_tfm *tfm, const u8 *key, unsigned int len) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ unsigned int ret = 0; ++ ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ ++ op->keylen = len; ++ ++ if (len == AES_KEYSIZE_128) { ++ memcpy(op->key, key, len); ++ return 0; ++ } ++ ++ if (len != AES_KEYSIZE_192 && len != AES_KEYSIZE_256) { ++ /* not supported at all */ ++ tfm->crt_flags |= CRYPTO_TFM_RES_BAD_KEY_LEN; ++ return -EINVAL; ++ } ++ ++ /* ++ * The requested key size is not supported by HW, do a fallback ++ */ ++ op->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK; ++ op->fallback.blk->base.crt_flags |= (tfm->crt_flags & CRYPTO_TFM_REQ_MASK); ++ ++ ret = crypto_blkcipher_setkey(op->fallback.blk, key, len); ++ if (ret) { ++ tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK; ++ tfm->crt_flags |= (op->fallback.blk->base.crt_flags & CRYPTO_TFM_RES_MASK); ++ } ++ return ret; ++} ++ ++static int fallback_blk_dec(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ unsigned int ret = 0; ++ struct crypto_blkcipher *tfm; ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ ++ tfm = desc->tfm; ++ desc->tfm = op->fallback.blk; ++ ++ ret = crypto_blkcipher_decrypt_iv(desc, dst, src, nbytes); ++ ++ desc->tfm = tfm; ++ return ret; ++} ++static int fallback_blk_enc(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ unsigned int ret = 0; ++ struct crypto_blkcipher *tfm; ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ ++ tfm = desc->tfm; ++ desc->tfm = op->fallback.blk; ++ ++ ret = crypto_blkcipher_encrypt_iv(desc, dst, src, nbytes); ++ ++ desc->tfm = tfm; ++ return ret; ++} ++ ++static void infinity_encrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++// enableClock(); ++// allocMem(16); ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) { ++ crypto_cipher_encrypt_one(op->fallback.cip, out, in); ++ return; ++ } ++ ++ op->src = (void *) in; ++ op->dst = (void *) out; ++ op->mode = AES_MODE_ECB; ++ op->flags = 0; ++ op->len = AES_BLOCK_SIZE; ++ op->dir = AES_DIR_ENCRYPT; ++ infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++} ++ ++ ++static void infinity_decrypt(struct crypto_tfm *tfm, u8 *out, const u8 *in) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) { ++ crypto_cipher_decrypt_one(op->fallback.cip, out, in); ++ return; ++ } ++ op->src = (void *) in; ++ op->dst = (void *) out; ++ op->mode = AES_MODE_ECB; ++ op->flags = 0; ++ op->len = AES_BLOCK_SIZE; ++ op->dir = AES_DIR_DECRYPT; ++ infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++} ++ ++static int fallback_init_cip(struct crypto_tfm *tfm) ++{ ++ const char *name = crypto_tfm_alg_name(tfm); ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ op->fallback.cip = crypto_alloc_cipher(name, 0, ++ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); ++ ++ if (IS_ERR(op->fallback.cip)) { ++ return PTR_ERR(op->fallback.cip); ++ } ++ return 0; ++} ++static void fallback_exit_cip(struct crypto_tfm *tfm) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ ++ crypto_free_cipher(op->fallback.cip); ++ op->fallback.cip = NULL; ++} ++ ++static int fallback_init_blk(struct crypto_tfm *tfm) ++{ ++ const char *name = crypto_tfm_alg_name(tfm); ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ op->fallback.blk = crypto_alloc_blkcipher(name, 0, ++ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK); ++ ++ if (IS_ERR(op->fallback.blk)) { ++ return PTR_ERR(op->fallback.blk); ++ } ++ return 0; ++} ++ ++static void fallback_exit_blk(struct crypto_tfm *tfm) ++{ ++ struct infinity_aes_op *op = crypto_tfm_ctx(tfm); ++ ++ crypto_free_blkcipher(op->fallback.blk); ++ op->fallback.blk = NULL; ++} ++ ++static int infinity_cbc_decrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0, ret = 0; ++ U8 ivTemp[16]={0}; ++ ++ mutex_lock(&_mtcrypto_lock); ++// enableClock(); ++// allocMem(4096); ++ memset(&walk, 0, sizeof(walk)); ++ ++ AESDMA_DBG("%s %d\n",__FUNCTION__,__LINE__); ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++ op->iv = walk.iv; ++// AESDMA_DBG(" 1%s %d\n",__FUNCTION__,nbytes); ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CBC; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ memcpy(ivTemp, op->src+(op->len)-16, 16); ++ op->dir = AES_DIR_DECRYPT; ++ ret = infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA] ERR blkcipher_walk_done %s!\n", __FUNCTION__); ++ goto finish; ++ } ++ memcpy(walk.iv, ivTemp, 16); ++ } ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++static int infinity_cbc_encrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0, ret = 0; ++ memset(&walk, 0, sizeof(walk)); ++ ++ mutex_lock(&_mtcrypto_lock); ++ ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++ op->iv = walk.iv; ++// AESDMA_DBG(" 1%s %d\n",__FUNCTION__,nbytes); ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CBC; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA] ERR blkcipher_walk_done %s!\n", __FUNCTION__); ++ goto finish; ++ } ++ ++ if (walk.nbytes > 0) ++ memcpy(walk.iv,(op->dst+(op->len)-16),16); ++ } ++ ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++static int infinity_ecb_decrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0 , ret = 0; ++ memset(&walk, 0, sizeof(walk)); ++ ++ mutex_lock(&_mtcrypto_lock); ++ ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_ECB; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_DECRYPT; ++ ret = infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA] ERR blkcipher_walk_done %s!\n", __FUNCTION__); ++ goto finish; ++ } ++ } ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++static int infinity_ecb_encrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err = 0, ret = 0; ++ memset(&walk, 0, sizeof(walk)); ++ ++ mutex_lock(&_mtcrypto_lock); ++ ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) ++ return fallback_blk_enc(desc, dst, src, nbytes); ++ ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ while ((nbytes = walk.nbytes)) { ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_ECB; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++ nbytes -= ret; ++ ret = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (ret != 0) ++ { ++ printk("[AESDMA] ERR blkcipher_walk_done %s!\n", __FUNCTION__); ++ goto finish; ++ } ++ } ++ ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++ ++} ++ ++/*ctr decrypt=encrypt*/ ++static int infinity_ctr_encrypt(struct blkcipher_desc *desc, ++ struct scatterlist *dst, struct scatterlist *src, ++ unsigned int nbytes) ++{ ++ struct infinity_aes_op *op = crypto_blkcipher_ctx(desc->tfm); ++ struct blkcipher_walk walk; ++ int err=0, ret=0, counter=0, n = 0; ++ U32 *tempIV=NULL; ++ memset(&walk, 0, sizeof(walk)); ++ ++ mutex_lock(&_mtcrypto_lock); ++// enableClock(); ++// allocMem(4096); ++ AESDMA_DBG("%s name %s\n",__FUNCTION__,desc->tfm->base.__crt_alg->cra_name); ++ ++ ++ if (unlikely(op->keylen != AES_KEYSIZE_128)) ++ return fallback_blk_dec(desc, dst, src, nbytes); ++ blkcipher_walk_init(&walk, dst, src, nbytes); ++ err = blkcipher_walk_virt(desc, &walk); ++ ++ while ((nbytes = walk.nbytes)) { ++// AESDMA_DBG(" 1%s %d\n",__FUNCTION__,nbytes); ++ op->iv = walk.iv; ++ op->src = walk.src.virt.addr, ++ op->dst = walk.dst.virt.addr; ++ op->mode = AES_MODE_CTR; ++ op->len = nbytes - (nbytes % AES_BLOCK_SIZE); ++ op->dir = AES_DIR_ENCRYPT; ++ ret = infinity_aes_crypt(op, AESDMA_CTRL_AES_EN); ++ nbytes -= ret; ++ err = blkcipher_walk_done(desc, &walk, nbytes); ++ ++ if (err != 0) ++ { ++ printk("[AESDMA] ERR blkcipher_walk_done %s!\n", __FUNCTION__); ++ goto finish; ++ } ++ ++ if (walk.nbytes > 0) ++ { ++ tempIV=(U32* )op->iv; ++ counter = op->len >> 4; ++ ++ for (n = 0; n <= 3; n++) ++ { ++ (tempIV[n]) = be32_to_cpu(tempIV[n]); ++ } ++ // iv=iv+1; ++ while(counter) ++ { ++ tempIV[3] = tempIV[3] + 1; ++ if (tempIV[3]==0x0) ++ { ++ tempIV[2] = tempIV[2] + 1; ++ if (tempIV[2]==0x0) ++ { ++ tempIV[1] = tempIV[1] + 1; ++ if (tempIV[1]==0x0) ++ { ++ tempIV[0] = tempIV[0] + 1; ++ if (tempIV[1]==0x0) ++ AESDMA_DBG("IV counter overflow! %s %d\n",__FUNCTION__,__LINE__); ++ } ++ } ++ } ++ counter--; ++ } ++ ++ for (n=0; n <= 3; n++) ++ { ++ (tempIV[n]) = cpu_to_be32(tempIV[n]); ++ } ++ } ++ } ++finish: ++ mutex_unlock(&_mtcrypto_lock); ++ return err; ++} ++ ++#if 0 ++static struct crypto_alg infinity_tdes_alg = { ++ .cra_name = "tdes", ++ .cra_driver_name = "tdes-generic", ++ .cra_priority = 400, ++ .cra_alignmask = 15, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_cip, ++ .cra_exit = fallback_exit_cip, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = infinity_setkey_cip, ++ .cia_encrypt = infinity_encrypt, ++ .cia_decrypt = infinity_decrypt ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_des_alg = { ++ .cra_name = "des", ++ .cra_driver_name = "infinity-des", ++ .cra_priority = 50, ++ .cra_alignmask = 15, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_cip, ++ .cra_exit = fallback_exit_cip, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = infinity_setkey_cip, ++ .cia_encrypt = infinity_encrypt, ++ .cia_decrypt = infinity_decrypt ++ } ++ } ++}; ++#endif ++ ++static struct crypto_alg infinity_alg = { ++ .cra_name = "aes", ++ .cra_driver_name = "infinity-aes", ++ .cra_priority = 300, ++ .cra_alignmask = 15, ++ .cra_flags = CRYPTO_ALG_TYPE_CIPHER | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_cip, ++ .cra_exit = fallback_exit_cip, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .cipher = { ++ .cia_min_keysize = AES_MIN_KEY_SIZE, ++ .cia_max_keysize = AES_MAX_KEY_SIZE, ++ .cia_setkey = infinity_setkey_cip, ++ .cia_encrypt = infinity_encrypt, ++ .cia_decrypt = infinity_decrypt ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_cbc_alg = { ++ .cra_name = "cbc(aes)", ++ .cra_driver_name = "cbc-aes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_cbc_encrypt, ++ .decrypt = infinity_cbc_decrypt, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_ecb_alg = { ++ .cra_name = "ecb(aes)", ++ .cra_driver_name = "ecb-aes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ecb_encrypt, ++ .decrypt = infinity_ecb_decrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_ctr_alg = { ++ .cra_name = "ctr(aes)", ++ .cra_driver_name = "ctr-aes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ctr_encrypt, ++ .decrypt = infinity_ctr_encrypt, ++ } ++ } ++}; ++ ++#if 0 ++static struct crypto_alg infinity_des_cbc_alg = { ++ .cra_name = "cbc(des)12", ++ .cra_driver_name = "cbc-des-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_cbc_encrypt, ++ .decrypt = infinity_cbc_decrypt, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_des_ecb_alg = { ++ .cra_name = "ecb(des)12", ++ .cra_driver_name = "ecb-des-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ecb_encrypt, ++ .decrypt = infinity_ecb_decrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_des_ctr_alg = { ++ .cra_name = "ctr(des)12", ++ .cra_driver_name = "ctr-des-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ctr_encrypt, ++ .decrypt = infinity_ctr_encrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_tdes_cbc_alg = { ++ .cra_name = "cbc(tdes)", ++ .cra_driver_name = "cbc(tdes-generic)", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_cbc_encrypt, ++ .decrypt = infinity_cbc_decrypt, ++ .ivsize = AES_BLOCK_SIZE, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_tdes_ecb_alg = { ++ .cra_name = "ecb(tdes)", ++ .cra_driver_name = "ecb-tdes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ecb_encrypt, ++ .decrypt = infinity_ecb_decrypt, ++ } ++ } ++}; ++ ++static struct crypto_alg infinity_tdes_ctr_alg = { ++ .cra_name = "ctr(tdes)", ++ .cra_driver_name = "ctr-tdes-infinity", ++ .cra_priority = 400, ++ .cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER | ++ CRYPTO_ALG_KERN_DRIVER_ONLY | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_init = fallback_init_blk, ++ .cra_exit = fallback_exit_blk, ++ .cra_blocksize = AES_BLOCK_SIZE, ++ .cra_ctxsize = sizeof(struct infinity_aes_op), ++ .cra_alignmask = 15, ++ .cra_type = &crypto_blkcipher_type, ++ .cra_module = THIS_MODULE, ++ .cra_u = { ++ .blkcipher = { ++ .min_keysize = AES_MIN_KEY_SIZE, ++ .max_keysize = AES_MAX_KEY_SIZE, ++ .ivsize = AES_BLOCK_SIZE, ++ .setkey = infinity_setkey_blk, ++ .encrypt = infinity_ctr_encrypt, ++ .decrypt = infinity_ctr_encrypt, ++ } ++ } ++}; ++#endif ++ ++static int infinity_aes_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static int infinity_aes_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int infinity_aes_remove(struct platform_device *pdev) ++{ ++ crypto_unregister_alg(&infinity_alg); ++ crypto_unregister_alg(&infinity_ecb_alg); ++ crypto_unregister_alg(&infinity_cbc_alg); ++ disableClock(); ++ infinity_sha_destroy(); ++ misc_deregister(&rsadev); ++ _ms_aes_mem_free(); ++ return 0; ++} ++ ++static int infinity_aes_probe(struct platform_device *pdev) ++{ ++ ++ int ret = 0; ++ ++ mutex_init(&_mtcrypto_lock); ++ allocMem(4096); ++#if 0 ++ ret = crypto_register_alg(&infinity_des_alg); ++ if (ret) ++ goto eiomap; ++ ret = crypto_register_alg(&infinity_tdes_alg); ++ if (ret) ++ goto eiomap; ++#endif ++ ret = crypto_register_alg(&infinity_alg); ++ if (ret) ++ goto eiomap; ++ ++ ret = crypto_register_alg(&infinity_ecb_alg); ++ if (ret) ++ goto eecb; ++ ++ ret = crypto_register_alg(&infinity_cbc_alg); ++ if (ret) ++ goto ecbc; ++ ++ ret = crypto_register_alg(&infinity_ctr_alg); ++ if (ret) ++ goto ectr; ++#if 0 ++ ret = crypto_register_alg(&infinity_des_ecb_alg); ++ if (ret) ++ goto edesecb; ++ ++ ret = crypto_register_alg(&infinity_des_cbc_alg); ++ if (ret) ++ goto edescbc; ++ ++ ret = crypto_register_alg(&infinity_des_ctr_alg); ++ if (ret) ++ goto edesctr; ++ ++ ret = crypto_register_alg(&infinity_tdes_ecb_alg); ++ if (ret) ++ goto etdesecb; ++ ++ ret = crypto_register_alg(&infinity_tdes_cbc_alg); ++ if (ret) ++ goto etdescbc; ++ ++ ret = crypto_register_alg(&infinity_tdes_ctr_alg); ++ if (ret) ++ goto etdesctr; ++#endif ++ ++ infinity_sha_create(); ++ misc_register(&rsadev); ++ dev_notice(&pdev->dev, "MSTAR AES engine enabled.\n"); ++ psg_mdrv_aesdma = pdev; ++ enableClock(); ++ return 0; ++ eecb: ++ crypto_unregister_alg(&infinity_ecb_alg); ++ ecbc: ++ crypto_unregister_alg(&infinity_cbc_alg); ++ ectr: ++ crypto_unregister_alg(&infinity_ctr_alg); ++#if 0 ++ edesecb: ++ crypto_unregister_alg(&infinity_des_ecb_alg); ++ edescbc: ++ crypto_unregister_alg(&infinity_des_cbc_alg); ++ edesctr: ++ crypto_unregister_alg(&infinity_des_ctr_alg); ++ etdesecb: ++ printk("!!!infinity_tdes_ecb_alg initialization failed.\n"); ++ crypto_unregister_alg(&infinity_tdes_ecb_alg); ++ etdescbc: ++ printk("!!!infinity_tdes_cbc_alg initialization failed.\n"); ++ crypto_unregister_alg(&infinity_tdes_cbc_alg); ++ etdesctr: ++ printk("!!!infinity_tdes_ctr_alg initialization failed.\n"); ++ crypto_unregister_alg(&infinity_tdes_ctr_alg); ++#endif ++ eiomap: ++ crypto_unregister_alg(&infinity_alg); ++ ++ dev_err(&pdev->dev, "MSTAR AES initialization failed.\n"); ++ return ret; ++} ++ ++static const struct of_device_id infinity_aes_dt_ids[] = ++{ ++ { .compatible = "mstar,infinity-aes" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, infinity_aes_dt_ids); ++ ++static struct platform_driver infinity_aes_driver = { ++ .probe = infinity_aes_probe, ++ .remove = infinity_aes_remove, ++ .suspend = infinity_aes_suspend, ++ .resume = infinity_aes_resume, ++ .driver = { ++ .name = "infinity_aes", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(infinity_aes_dt_ids), ++ }, ++}; ++ ++ ++module_platform_driver(infinity_aes_driver); ++ ++ ++MODULE_DESCRIPTION("iNfinity AES hw acceleration support."); ++ ++// // MODULE_ALIAS_CRYPTO("ctr(des)"); ++// MODULE_ALIAS_CRYPTO("tdes"); ++// MODULE_ALIAS_CRYPTO("tdes-generic"); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("MS Comp."); +diff --git a/drivers/mstar/crypto/infinity/mdrv_aes.h b/drivers/mstar/crypto/infinity/mdrv_aes.h +new file mode 100644 +index 00000000..af000f3e +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/mdrv_aes.h +@@ -0,0 +1,61 @@ ++/* Copyright (C) 2003-2006, Advanced Micro Devices, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef _MSTAR_AES_H_ ++#define _MSTAR_AES_H_ ++ ++/* driver logic flags */ ++#define AES_MODE_ECB 0 ++#define AES_MODE_CBC 1 ++#define AES_MODE_CTR 2 ++#define AES_DIR_DECRYPT 0 ++#define AES_DIR_ENCRYPT 1 ++#define AESDMA_ALLOC_MEMSIZE (16) //1MB 1024*1024 ++#define AESDMA_ALLOC_MEMSIZE_TEMP (16) //64byte for SHA ++ ++struct infinity_aes_op ++{ ++ void *src; ++ void *dst;//16 ++ u32 mode; ++ u32 dir; ++ u32 flags; ++ u32 keylen;//24 ++ int len; ++ u8 *iv;//8 ++ u8 key[AES_KEYSIZE_128];//16 ++ union { ++ struct crypto_blkcipher *blk; ++ struct crypto_cipher *cip; ++ } fallback; ++ u16 engine; ++ ++}; ++ ++ ++struct aesdma_alloc_dmem ++{ ++ dma_addr_t aesdma_phy_addr ; ++ dma_addr_t aesdma_phy_SHABuf_addr; ++ const char* DMEM_AES_ENG_INPUT; ++ const char* DMEM_AES_ENG_SHABUF; ++ u8 *aesdma_vir_addr; ++ u8 *aesdma_vir_SHABuf_addr; ++}ALLOC_DMEM = {0, 0, "AESDMA_ENG", "AESDMA_ENG1", 0, 0}; ++ ++struct platform_device *psg_mdrv_aesdma; ++ ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++ ++ ++#endif +diff --git a/drivers/mstar/crypto/infinity/mdrv_rsa.c b/drivers/mstar/crypto/infinity/mdrv_rsa.c +new file mode 100644 +index 00000000..4b787447 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/mdrv_rsa.c +@@ -0,0 +1,314 @@ ++/* ++ *############################################################################# ++ * ++ * Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++ * All rights reserved. ++ * ++ * Unless otherwise stipulated in writing, any and all information contained ++ * herein regardless in any format shall remain the sole proprietary of ++ * MStar Semiconductor Inc. and be kept in strict confidence ++ * (!¡±MStar Confidential Information!¡L) by the recipient. ++ * Any unauthorized act including without limitation unauthorized disclosure, ++ * copying, use, reproduction, sale, distribution, modification, disassembling, ++ * reverse engineering and compiling of the contents of MStar Confidential ++ * Information is unlawful and strictly prohibited. MStar hereby reserves the ++ * rights to any and all damages, losses, costs and expenses resulting therefrom. ++ * ++ *############################################################################# ++ */ ++#include ++#include ++#include ++#include ++#include ++#include <../drivers/mstar/include/ms_msys.h> ++#include <../drivers/mstar/include/ms_platform.h> ++#include <../drivers/mstar/include/mdrv_hvsp_io_st.h> ++#include <../drivers/mstar/include/mdrv_hvsp_io.h> ++#include ++#include "mdrv_rsa.h" ++#include "halAESDMA.h" ++#include ++#include ++#include ++ ++#define DRIVER_NAME "rsa" ++//static unsigned int test_ioctl_major = 0; ++//static unsigned int num_of_dev = 1; ++//static struct cdev test_ioctl_cdev; ++//static int ioctl_num = 0; ++ ++ ++//static const char* DMEM_RSA_ENG_INPUT="RSA_ENG_IN"; ++ ++struct rsaConfig{ ++ U32 *pu32RSA_Sig; ++ U32 *pu32RSA_KeyN; ++ U32 *pu32RSA_KeyE; ++ U32 *pu32RSA_Output; ++ U8 u8RSA_KeyNLen; ++ U8 u8RSA_SigLen; ++ U8 u8RSA_KeyELen; ++ U8 u8RSAPublicKey; ++}; ++ ++static long rsa_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ struct rsaConfig *ioctl_data = filp->private_data; ++ int retval = 0; ++ struct rsa_config data; ++ int nOutSize = 0; ++ int i = 0; ++ bool bRSAHwKey = FALSE; ++ ++// unsigned char* val; ++ memset(&data, 0, sizeof(data)); ++ ++ switch (cmd) { ++ ++ case MDrv_RSA_Reset: ++ HAL_RSA_Reset(); ++ goto done; ++ break; ++ ++ case MDrv_RSA_Setmode: ++ memset(&data, 0, sizeof(data)); ++ if (copy_from_user(&data, (int __user *)arg, sizeof(data))) { ++ retval = -EFAULT; ++ goto done; ++ } ++// write_lock(&ioctl_data->lock); ++ ioctl_data->u8RSA_KeyNLen = data.u32RSA_KeyNLen; ++// write_unlock(&ioctl_data->lock); ++ if (ioctl_data->u8RSA_KeyNLen != 0x10 && ioctl_data->u8RSA_KeyNLen != 0x20 && ioctl_data->u8RSA_KeyNLen != 0x40){ ++ retval = -EFAULT; ++ printk("[RSAERR] Mode error\n"); ++ printk("[RSAERR] KenNLen != 0x10 or 0x20 or 0x40\n"); ++ goto done; ++ } ++ ++ HAL_RSA_SetKeyLength(((ioctl_data->u8RSA_KeyNLen)-1) & 0x3F); ++ HAL_RSA_SetKeyType(bRSAHwKey, FALSE); ++ break; ++ ++ case MDrv_RSA_Calculate: ++ memset(&data, 0, sizeof(data)); ++ if (copy_from_user(&data, (int __user *)arg, sizeof(data))) { ++ retval = -EFAULT; ++ goto done; ++ } ++// write_lock(&ioctl_data->lock); ++ ioctl_data->pu32RSA_Sig = (U32 *)data.pu32RSA_Sig; ++ ioctl_data->pu32RSA_Output = (U32 *)data.pu32RSA_Output; ++ ioctl_data->pu32RSA_KeyN = (U32 *)data.pu32RSA_KeyN; ++ ioctl_data->pu32RSA_KeyE = (U32 *)data.pu32RSA_KeyE; ++ ioctl_data->u8RSA_KeyELen = (U8)(data.u32RSA_KeyELen & 0xFF); ++ ioctl_data->u8RSA_KeyNLen = (U8)(data.u32RSA_KeyNLen & 0xFF); ++ ioctl_data->u8RSA_SigLen = (U8)(data.u32RSA_SigLen & 0xFF); ++// write_unlock(&ioctl_data->lock); ++ ++ if ((ioctl_data->u8RSA_SigLen < 1) || (ioctl_data->u8RSA_SigLen > 0xFF)) { ++ retval = -EFAULT; ++ printk("[RSAERR] SigLen is invalid\n"); ++ goto done; ++ } ++ ++ if ((ioctl_data->u8RSA_KeyELen < 1) || (ioctl_data->u8RSA_KeyELen > 0xFF)) ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] KeyELen is invalid\n"); ++ goto done; ++ } ++ ++ if ((ioctl_data->u8RSA_KeyNLen < 1) || (ioctl_data->u8RSA_KeyNLen > 0xFF)) ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] KeyNLen is invalid\n"); ++ goto done; ++ } ++ ++ if (!((ioctl_data->pu32RSA_Sig) && (ioctl_data->pu32RSA_Output) && (ioctl_data->pu32RSA_KeyN))) { ++ retval = -EFAULT; ++ printk("[RSAERR] null pointer = 0 \n"); ++ goto done; ++ } ++ ++ HAL_RSA_Ind32Ctrl(1);//1:write ++ ++ if((!bRSAHwKey) && (ioctl_data->pu32RSA_Sig)) ++ { ++ HAL_RSA_LoadSignInverse(ioctl_data->pu32RSA_Sig, ioctl_data->u8RSA_SigLen); ++ } ++ else ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] RSA_Sig = NULL\n"); ++ goto done; ++ } ++ ++ if((!bRSAHwKey) && (ioctl_data->pu32RSA_KeyN)) ++ { ++ ++ HAL_RSA_LoadKeyNInverse(ioctl_data->pu32RSA_KeyN, ioctl_data->u8RSA_KeyNLen); ++ } ++ else ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] RSA_KeyN = NULL\n"); ++ goto done; ++ } ++ ++ if((!bRSAHwKey) && (ioctl_data->pu32RSA_KeyE)) ++ { ++ HAL_RSA_LoadKeyEInverse(ioctl_data->pu32RSA_KeyE, ioctl_data->u8RSA_KeyELen); //65535 ++ ++ } ++ else ++ { ++ retval = -EFAULT; ++ printk("[RSAERR] RSA_KeyE = NULL\n"); ++ goto done; ++ } ++ ++ HAL_RSA_ExponetialStart(); ++ ++ while((HAL_RSA_GetStatus() & RSA_STATUS_RSA_DONE) != RSA_STATUS_RSA_DONE); ++ ++ if((bRSAHwKey) || (ioctl_data->u8RSA_KeyNLen == 64)) ++ { ++ nOutSize = 64; ++ } ++ else ++ { ++ nOutSize = 32; ++ } ++ ++ HAL_RSA_Ind32Ctrl(0); ++ ++ for( i = 0; ipu32RSA_Output + (nOutSize-1) - i) = HAL_RSA_FileOut(); ++ ++ } ++ ++ HAL_RSA_FileOutEnd(); ++ HAL_RSA_Reset(); ++ ++// read_lock(&ioctl_data->lock); ++ ++ data.pu32RSA_Output = (unsigned int*)ioctl_data->pu32RSA_Output; ++ ++// read_unlock(&ioctl_data->lock); ++ ++ if (copy_to_user((int __user *)arg, &data, sizeof(data)) ) { ++ retval = -EFAULT; ++ goto done; ++ } ++ break; ++ ++ default: ++ retval = -ENOTTY; ++ ++ } ++ ++ done: ++ ++ return retval; ++} ++ ++//ssize_t test_ioctl_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos) ++//{ ++// struct rsaConfig *ioctl_data = filp->private_data; ++// unsigned char val; ++// int retval; ++// int i = 0; ++ ++// read_lock(&ioctl_data->lock); ++// val = ioctl_data->val; ++// read_unlock(&ioctl_data->lock); ++ ++// for (;i < count ;i++) { ++// if (copy_to_user(&buf[i], &val, 1)) { ++// retval = -EFAULT; ++// goto out; ++// } ++// } ++ ++// retval = count; ++ ++//out: ++// return retval; ++//} ++ ++static int rsa_ioctl_close(struct inode *inode, struct file *filp) ++{ ++// printk(KERN_ALERT "%s call.\n", __func__); ++ if (filp->private_data) { ++ kfree(filp->private_data); ++ filp->private_data = NULL; ++ } ++ ++ return 0; ++} ++ ++static int rsa_ioctl_open(struct inode *inode, struct file *filp) ++{ ++ ++ struct rsaConfig *ioctl_data; ++// printk(KERN_ALERT "%s call.\n", __func__); ++ ++ ioctl_data = kmalloc(sizeof(struct rsaConfig), GFP_KERNEL); ++ if (ioctl_data == NULL) ++ return -ENOMEM; ++ ++// rwlock_init(&ioctl_data->lock); ++ ++ ++ filp->private_data = ioctl_data; ++ ++ return 0; ++} ++ ++struct file_operations rsa_fops = { ++ .owner = THIS_MODULE, ++ .open = rsa_ioctl_open, ++ .release = rsa_ioctl_close, ++ .unlocked_ioctl = rsa_ioctl, ++}; ++ ++struct miscdevice rsadev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "rsa", ++ .fops = &rsa_fops, ++ .mode = S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH, ++}; ++ ++//#define PFX "rsadev: " ++ ++//static int __init rsa_ioctl_init(void) ++//{ ++ ++//int rc; ++// rc = misc_register(&rsadev); ++// if (unlikely(rc)) { ++// pr_err(PFX "registration of /dev/crypto failed\n"); ++// return rc; ++// } ++ ++// return 0; ++//} ++ ++//static void __exit rsa_ioctl_exit(void) ++//{ ++// misc_deregister(&rsadev); ++//} ++ ++//module_init(rsa_ioctl_init); ++//module_exit(rsa_ioctl_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("mstar"); ++MODULE_DESCRIPTION("This is test_ioctl module."); +diff --git a/drivers/mstar/crypto/infinity/mdrv_rsa.h b/drivers/mstar/crypto/infinity/mdrv_rsa.h +new file mode 100644 +index 00000000..b045306d +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/mdrv_rsa.h +@@ -0,0 +1,46 @@ ++/* ++ *############################################################################# ++ * ++ * Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++ * All rights reserved. ++ * ++ * Unless otherwise stipulated in writing, any and all information contained ++ * herein regardless in any format shall remain the sole proprietary of ++ * MStar Semiconductor Inc. and be kept in strict confidence ++ * (¡§MStar Confidential Information¡¨) by the recipient. ++ * Any unauthorized act including without limitation unauthorized disclosure, ++ * copying, use, reproduction, sale, distribution, modification, disassembling, ++ * reverse engineering and compiling of the contents of MStar Confidential ++ * Information is unlawful and strictly prohibited. MStar hereby reserves the ++ * rights to any and all damages, losses, costs and expenses resulting therefrom. ++ * ++ *############################################################################# ++*/ ++ ++ ++#ifndef _IOCTL_TEST_H ++#define _IOCTL_TEST_H ++ ++#include ++ ++struct rsa_config { ++unsigned int *pu32RSA_Sig; ++unsigned int *pu32RSA_KeyN; ++unsigned int *pu32RSA_KeyE; ++unsigned int *pu32RSA_Output; ++unsigned int u32RSA_KeyNLen; ++unsigned int u32RSA_KeyELen; ++unsigned int u32RSA_SigLen; ++}; ++ ++ ++ ++ ++/* ocumentation/ioctl/ioctl-number.txt */ ++#define IOC_MAGIC '\x66' ++ ++#define MDrv_RSA_Reset _IO(IOC_MAGIC, 0x92) ++#define MDrv_RSA_Setmode _IO(IOC_MAGIC, 0x93) ++#define MDrv_RSA_Calculate _IO(IOC_MAGIC, 0x94) ++ ++#endif +\ No newline at end of file +diff --git a/drivers/mstar/crypto/infinity/mdrv_sha.c b/drivers/mstar/crypto/infinity/mdrv_sha.c +new file mode 100644 +index 00000000..65203754 +--- /dev/null ++++ b/drivers/mstar/crypto/infinity/mdrv_sha.c +@@ -0,0 +1,387 @@ ++/* ++ *############################################################################# ++ * ++ * Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++ * All rights reserved. ++ * ++ * Unless otherwise stipulated in writing, any and all information contained ++ * herein regardless in any format shall remain the sole proprietary of ++ * MStar Semiconductor Inc. and be kept in strict confidence ++ * (!¡±MStar Confidential Information!¡L) by the recipient. ++ * Any unauthorized act including without limitation unauthorized disclosure, ++ * copying, use, reproduction, sale, distribution, modification, disassembling, ++ * reverse engineering and compiling of the contents of MStar Confidential ++ * Information is unlawful and strictly prohibited. MStar hereby reserves the ++ * rights to any and all damages, losses, costs and expenses resulting therefrom. ++ * ++ *############################################################################# ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "halAESDMA.h" ++#include ++ ++#define LOOP_CNT 100 ++#define INFINITY_SHA_BUFFER_SIZE 1024 ++ ++#define SHA_DEBUG_FLAG (1) ++#if (SHA_DEBUG_FLAG == 1) ++#define SHA_DBG(fmt, arg...) printk(KERN_DEBUG fmt, ##arg)//KERN_DEBUG KERN_ALERT KERN_WARNING ++#else ++#define SHA_DBG(fmt, arg...) ++#endif ++ ++//memory probe from aes.c ++extern struct aesdma_alloc_dmem ++{ ++ dma_addr_t aesdma_phy_addr ; ++ dma_addr_t aesdma_phy_SHABuf_addr; ++ const char* DMEM_AES_ENG_INPUT; ++ const char* DMEM_AES_ENG_SHABUF; ++ u8 *aesdma_vir_addr; ++ u8 *aesdma_vir_SHABuf_addr; ++}ALLOC_DMEM; ++ ++extern struct platform_device *psg_mdrv_aesdma; ++extern void enableClock(void); ++extern void disableClock(void); ++extern void allocMem(U32 len); ++extern void _ms_aes_mem_free(void); ++ ++extern void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr ); ++static u8 gu8WorkMode=0; ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++void allocTempMem(U32 len) ++{ ++ if (!(ALLOC_DMEM.aesdma_vir_SHABuf_addr = alloc_dmem(ALLOC_DMEM.DMEM_AES_ENG_SHABUF, ++ len, ++ &ALLOC_DMEM.aesdma_phy_SHABuf_addr))){ ++ printk("[input]unable to allocate aesdma memory\n"); ++ } ++ memset(ALLOC_DMEM.aesdma_vir_SHABuf_addr, 0, len); ++} ++ ++struct infinity_sha256_ctx ++{ ++ u8 digest[SHA256_DIGEST_SIZE]; ++ u32 u32digest_len; ++}; ++ ++static void __BeforeStart(void) ++{ ++ u32 u32Val=0; ++ switch(gu8WorkMode) ++ { ++ case 0: ++ SHA_DBG(" %s_info: case = %d\n",__FUNCTION__,gu8WorkMode); ++ HAL_SHA_ManualMode(0); ++ gu8WorkMode++; ++ break; ++ case 1: ++ SHA_DBG(" %s_info: case = %d\n",__FUNCTION__,gu8WorkMode); ++ HAL_SHA_ManualMode(1); ++ HAL_SHA_Out((U32)ALLOC_DMEM.aesdma_vir_SHABuf_addr); ++ HAL_SHA_Write_InitValue((U32)ALLOC_DMEM.aesdma_vir_SHABuf_addr); ++ u32Val = HAL_SHA_ReadWordCnt(); ++ HAL_SHA_WriteWordCnt(u32Val); ++ gu8WorkMode++; ++ break; ++ default: ++ SHA_DBG(" %s_info: case = %d\n",__FUNCTION__,gu8WorkMode); ++ HAL_SHA_Out((U32)ALLOC_DMEM.aesdma_vir_SHABuf_addr); ++ HAL_SHA_Write_InitValue((U32)ALLOC_DMEM.aesdma_vir_SHABuf_addr); ++ u32Val = HAL_SHA_ReadWordCnt(); ++ HAL_SHA_WriteWordCnt(u32Val); ++ break; ++ } ++} ++ ++static int infinity_sha256_init(struct shash_desc *desc) ++{ ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++// struct sha256_state *sctx = shash_desc_ctx(desc); ++ ++ ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ SHA_DBG(" %s %d \n","infinity_ctx->u32digest_len", infinity_ctx->u32digest_len); ++// infinity_ctx->u32digest_len = 3; ++// enableClock(); ++// if(infinity_ctx->u32digest_len) ++// { ++// allocMem(4096); ++// allocMem(0x20); ++// allocTempMem(4096); ++// } ++// else ++// { ++// return -EINVAL; ++// } ++ ++ HAL_SHA_Reset(); ++ HAL_SHA_SetAddress(Chip_Phys_to_MIU(ALLOC_DMEM.aesdma_phy_addr)); ++ HAL_SHA_SelMode(1); ++ gu8WorkMode = 0; ++ memset(infinity_ctx, 0, sizeof(struct infinity_sha256_ctx)); ++ return 0; ++} ++ ++static int infinity_sha256_update(struct shash_desc *desc, const u8 *data, unsigned int len) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ u64 leftover= 0; ++ u64 total= 0; ++ u32 u32InputCopied = 0; ++ u32 u32loopCnt; ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ ++ ++ sctx->count = 0; ++ total = sctx->count + len; ++ if (total < SHA256_BLOCK_SIZE) { ++ memcpy(sctx->buf + sctx->count, data, len); ++ sctx->count += len; ++ return 0; ++ } ++ ++ SHA_DBG(" %s sctx->count %lld \n",__FUNCTION__,sctx->count); ++ if(sctx->count) ++ { ++ memcpy(ALLOC_DMEM.aesdma_vir_addr, sctx->buf, sctx->count); ++ Chip_Flush_MIU_Pipe(); ++ } ++ ++ leftover = total; ++ if(leftover >= INFINITY_SHA_BUFFER_SIZE) ++ { ++ SHA_DBG("INFINITY_SHA_BUFFER_SIZE-sctx->count %lld \n",INFINITY_SHA_BUFFER_SIZE-sctx->count); ++ memcpy(ALLOC_DMEM.aesdma_vir_addr+sctx->count, data, INFINITY_SHA_BUFFER_SIZE-sctx->count); ++ Chip_Flush_MIU_Pipe(); ++ u32InputCopied = INFINITY_SHA_BUFFER_SIZE-sctx->count; ++ HAL_SHA_SetLength(INFINITY_SHA_BUFFER_SIZE); ++ while(leftover >= INFINITY_SHA_BUFFER_SIZE) ++ { ++ __BeforeStart(); ++ HAL_SHA_Start(); ++ u32loopCnt = 0; ++ while(((HAL_SHA_GetStatus() & SHARNG_CTRL_SHA_READY) != SHARNG_CTRL_SHA_READY) && ++ (u32loopCnt= INFINITY_SHA_BUFFER_SIZE) ++ { ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ memcpy(ALLOC_DMEM.aesdma_vir_addr, data+u32InputCopied, INFINITY_SHA_BUFFER_SIZE); ++ Chip_Flush_MIU_Pipe(); ++ u32InputCopied += INFINITY_SHA_BUFFER_SIZE; ++ } ++ } ++ } ++ else ++ { ++ SHA_DBG(" %s line224 %d \n",__FUNCTION__,len); ++ memcpy(ALLOC_DMEM.aesdma_vir_addr+sctx->count, data, len); ++ Chip_Flush_MIU_Pipe(); ++ } ++ ++ if(leftover >= SHA256_BLOCK_SIZE) ++ { ++ SHA_DBG(" %s line232 %d \n",__FUNCTION__,SHA256_BLOCK_SIZE); ++ memcpy(ALLOC_DMEM.aesdma_vir_addr, data+u32InputCopied, SHA256_BLOCK_SIZE); ++ Chip_Flush_MIU_Pipe(); ++ u32InputCopied += SHA256_BLOCK_SIZE; ++ HAL_SHA_SetLength(total); ++ while(leftover >= SHA256_BLOCK_SIZE) ++ { ++ __BeforeStart(); ++ HAL_SHA_Start(); ++ u32loopCnt = 0; ++ while(((HAL_SHA_GetStatus() & SHARNG_CTRL_SHA_READY) != SHARNG_CTRL_SHA_READY) && ++ (u32loopCnt= SHA256_BLOCK_SIZE) ++ { ++ memcpy(ALLOC_DMEM.aesdma_vir_addr, data+u32InputCopied, SHA256_BLOCK_SIZE); ++ Chip_Flush_MIU_Pipe(); ++ u32InputCopied += SHA256_BLOCK_SIZE; ++ } ++ } ++ } ++ ++ if (leftover) ++ { ++ memcpy(sctx->buf, data+u32InputCopied, leftover); ++ } ++ sctx->count = leftover; ++ HAL_SHA_Out((U32)infinity_ctx->digest); ++ infinity_ctx->u32digest_len += HAL_SHA_ReadWordCnt(); ++ return 0; ++} ++ ++static int infinity_sha256_final(struct shash_desc *desc, u8 *out) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ u32 u32loopCnt; ++ ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ if(sctx->count) ++ { ++ memset(ALLOC_DMEM.aesdma_vir_addr, 0, SHA256_BLOCK_SIZE); ++ /*Need to check the value*/ ++ while (memcmp(ALLOC_DMEM.aesdma_vir_addr, sctx->buf, ++ sctx->count)!= 0 ){ ++ memcpy(ALLOC_DMEM.aesdma_vir_addr, sctx->buf, SHA256_BLOCK_SIZE); ++ ++ } ++// memcpy(ALLOC_DMEM.aesdma_vir_addr, sctx->buf, SHA256_BLOCK_SIZE); ++// Chip_Flush_MIU_Pipe(); ++ HAL_SHA_SetLength(sctx->count); ++ __BeforeStart(); ++ HAL_SHA_Start(); ++ u32loopCnt = 0; ++ while(((HAL_SHA_GetStatus() & SHARNG_CTRL_SHA_READY) != SHARNG_CTRL_SHA_READY) && ++ (u32loopCntdigest); ++ infinity_ctx->u32digest_len += sctx->count; ++ sctx->count = 0; ++ } ++ HAL_SHA_Reset(); ++ ++ memcpy(out, infinity_ctx->digest, SHA256_DIGEST_SIZE); ++ ++// _ms_aes_mem_free(); ++// disableClock(); ++// printk(KERN_ALERT " %s \n",__FUNCTION__); ++ return 0; ++} ++ ++static int infinity_sha256_export(struct shash_desc *desc, void *out) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ struct sha256_state *octx = out; ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ octx->count = sctx->count + infinity_ctx->u32digest_len; ++ memcpy(octx->buf, sctx->buf, sizeof(octx->buf)); ++ /* if no data has been processed yet, we need to export SHA256's ++ * initial data, in case this context gets imported into a software ++ * context */ ++ if(infinity_ctx->u32digest_len) ++ { ++ memcpy(octx->state, infinity_ctx->digest, SHA256_DIGEST_SIZE); ++ } ++ else ++ { ++ memset(octx->state, 0, SHA256_DIGEST_SIZE); ++ } ++ ++ return 0; ++} ++ ++static int infinity_sha256_import(struct shash_desc *desc, const void *in) ++{ ++ struct sha256_state *sctx = shash_desc_ctx(desc); ++ struct infinity_sha256_ctx *infinity_ctx = crypto_tfm_ctx(&desc->tfm->base); ++ const struct sha256_state *ictx = in; ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++ memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf)); ++ sctx->count = ictx->count & 0x3f; ++ infinity_ctx->u32digest_len = sctx->count; ++ if (infinity_ctx->u32digest_len) { ++ memcpy(infinity_ctx->digest, ictx->state, SHA256_DIGEST_SIZE); ++ } ++ return 0; ++} ++ ++struct shash_alg infinity_shash_sha256_alg = { ++ .digestsize = SHA256_DIGEST_SIZE, ++ .init = infinity_sha256_init, ++ .update = infinity_sha256_update, ++ .final = infinity_sha256_final, ++ .export = infinity_sha256_export, ++ .import = infinity_sha256_import, ++ .descsize = sizeof(struct sha256_state), ++ .statesize = sizeof(struct sha256_state), ++ .base = { ++ .cra_name = "sha256", ++ .cra_driver_name = "sha256-infinity", ++ .cra_priority = 00, ++ .cra_flags = CRYPTO_ALG_TYPE_SHASH | ++ CRYPTO_ALG_NEED_FALLBACK, ++ .cra_blocksize = SHA256_BLOCK_SIZE, ++ .cra_module = THIS_MODULE, ++ .cra_ctxsize = sizeof(struct infinity_sha256_ctx), ++ } ++}; ++ ++ ++ ++int infinity_sha_create(void) ++{ ++ int ret = -1; ++ SHA_DBG(" %s %d \n",__FUNCTION__,__LINE__); ++// SHA_DBG(" %s %d \n",__FUNCTION__,SHA256_DIGEST_SIZE); ++ ret = crypto_register_shash(&infinity_shash_sha256_alg); ++// allocMem(4096); ++ allocTempMem(4096); ++ ++ return ret; ++} ++ ++int infinity_sha_destroy(void) ++{ ++ _ms_aes_mem_free(); ++ ++// crypto_unregister_alg(&infinity_shash_sha256_alg); ++ return 0; ++} +diff --git a/drivers/mstar/dip/Kconfig b/drivers/mstar/dip/Kconfig +new file mode 100644 +index 00000000..767dc1ac +--- /dev/null ++++ b/drivers/mstar/dip/Kconfig +@@ -0,0 +1,3 @@ ++config MS_DIP ++ tristate "DIP driver" ++ help +diff --git a/drivers/mstar/dip/Makefile b/drivers/mstar/dip/Makefile +new file mode 100644 +index 00000000..537c4204 +--- /dev/null ++++ b/drivers/mstar/dip/Makefile +@@ -0,0 +1,31 @@ ++# ++# Makefile for MStar gop device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/cedric ++ ++#-------------- msos -------------- ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/include ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/msos ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/drv/irq ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/hal/c3/irq ++ ++#-------------- XC -------------- ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/api/xc ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/drv/xc ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/drv/xc/include ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/hal/c3/xc ++EXTRA_CFLAGS += -Idrivers/mstar/sca/drv/hal/c3/xc/include ++ ++# specific options ++EXTRA_CFLAGS += ++ ++ ++ccflags-y += -DMSOS_TYPE_LINUX_KERNEL ++ccflags-y += -DCHIP_C3 ++ccflags-y += -DMULTI_SCALER_SUPPORTED ++ ++ ++# files ++obj-$(CONFIG_MS_DIP) += mdrv_dip_io.o +diff --git a/drivers/mstar/dip/mdrv_dip.h b/drivers/mstar/dip/mdrv_dip.h +new file mode 100644 +index 00000000..fb5c66c6 +--- /dev/null ++++ b/drivers/mstar/dip/mdrv_dip.h +@@ -0,0 +1,67 @@ ++ ++ ++#include ++#include "ms_platform.h" ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++ ++ ++#define DIP_DEBUG 0 ++ ++#if (DIP_DEBUG==1) ++#define DIPDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define DIPDBG(fmt, arg...) ++#endif ++ ++ ++//#define DIPIO_DEBUG_ENABLE ++ ++#define DIP_DBG_LV_IOCTL 0 ++#define DIP_DBG_LV_0 1 ++ ++ ++#ifdef DIPIO_DEBUG_ENABLE ++#define DIPIO_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define DIP_DBG(dbglv, _fmt, _args...) \ ++ do \ ++ if(dbglv) \ ++ { \ ++ printk(KERN_WARNING _fmt, ## _args); \ ++ }while(0) ++ ++#else ++#define DIPIO_ASSERT(arg) ++#define DIP_DBG(dbglv, _fmt, _args...) ++ ++#endif ++ ++ ++ ++ ++ ++ +diff --git a/drivers/mstar/dip/mdrv_dip_io.c b/drivers/mstar/dip/mdrv_dip_io.c +new file mode 100644 +index 00000000..42c21e9a +--- /dev/null ++++ b/drivers/mstar/dip/mdrv_dip_io.c +@@ -0,0 +1,572 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "irqs.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++ ++#include "mdrv_dip.h" ++#include "mdrv_dip_io_st.h" ++#include "mdrv_dip_io.h" ++#include "MsTypes.h" ++#include "drvXC_IOPort.h" ++#include "apiXC.h" ++#include "drv_sc_isr.h" ++ ++#define MDRV_DIP_DEVICE_COUNT 1 ++#define MDRV_DIP_NAME "mdip" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_DIP "mdip" ++#define MDRV_MAJOR_DIP 0xea ++#define MDRV_MINOR_DIP 0x02 ++ ++ ++#define CMD_PARSING(x) (x==IOCTL_DIP_SET_INTERRUPT ? "IOCTL_DIP_SET_INTERRUPT" : \ ++ x==IOCTL_DIP_SET_CONFIG ? "IOCTL_DIP_SET_CONFIG" : \ ++ x==IOCTL_DIP_SET_WONCE_BASE_CONFIG ? "IOCTL_DIP_SET_WONCE_BASE_CONFIG" : \ ++ x==IOCTL_DIP_GET_INTERRUPT_STATUS ? "IOCTL_DIP_GET_INTERRUPT_STATUS" : \ ++ "unknown") ++ ++ ++int mstar_dip_drv_open(struct inode *inode, struct file *filp); ++int mstar_dip_drv_release(struct inode *inode, struct file *filp); ++long mstar_dip_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mstar_dip_drv_probe(struct platform_device *pdev); ++static int mstar_dip_drv_remove(struct platform_device *pdev); ++static int mstar_dip_drv_suspend(struct platform_device *dev, pm_message_t state); ++static int mstar_dip_drv_resume(struct platform_device *dev); ++static void mstar_dip_drv_platfrom_release(struct device *device); ++static unsigned int mstar_dipw_drv_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++extern atomic_t DIPW_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++}DIP_DEV; ++ ++static DIP_DEV _devDIP = ++{ ++ .s32Major = MDRV_MAJOR_DIP, ++ .s32Minor = MDRV_MINOR_DIP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_DIP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mstar_dip_drv_open, ++ .release = mstar_dip_drv_release, ++ .unlocked_ioctl = mstar_dip_drv_ioctl, ++ .poll = mstar_dipw_drv_poll, ++ } ++}; ++ ++static struct class * dip_class; ++static char * dip_classname = "mstar_dip_class"; ++ ++static struct platform_driver Mstar_dip_driver = { ++ .probe = mstar_dip_drv_probe, ++ .remove = mstar_dip_drv_remove, ++ .suspend = mstar_dip_drv_suspend, ++ .resume = mstar_dip_drv_resume, ++ ++ .driver = { ++ .name = "mdip", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static u64 sg_mstar_device_dip_dmamask = 0xffffffffUL; ++ ++static struct platform_device sg_mdrv_dip_device = ++{ ++ .name = "mdip", ++ .id = 0, ++ .dev = ++ { ++ .release = mstar_dip_drv_platfrom_release, ++ .dma_mask = &sg_mstar_device_dip_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++ ++MS_BOOL DIP_Set_Config(PDIP_CONFIG pCfg) ++{ ++ MS_BOOL bret = TRUE; ++ XC_DIP_CONFIG_t stDipConfig; ++ ++ if(pCfg->bTriggle == FALSE) ++ { ++ ++ if(pCfg->enTrigMode == DIP_TRIGGER_LOOP) ++ { ++ MApi_XC_Set_Dip_Trig(FALSE); ++ } ++ else ++ { ++ MApi_XC_DIP_Set_Dwin_Wt_Once(FALSE); ++ } ++ } ++ else ++ { ++ ++ memset(&stDipConfig, 0, sizeof(XC_DIP_CONFIG_t)); ++ ++ // clip window ++ stDipConfig.bClipEn = pCfg->bClipEn; ++ stDipConfig.stClipWin.x = pCfg->stClipWin.x < 1 ? 1 : pCfg->stClipWin.x; ++ stDipConfig.stClipWin.y = pCfg->stClipWin.y < 1 ? 1 : pCfg->stClipWin.y; ++ stDipConfig.stClipWin.width = pCfg->stClipWin.width > pCfg->u16Width ? pCfg->u16Width : pCfg->stClipWin.width; ++ stDipConfig.stClipWin.height = pCfg->stClipWin.height > pCfg->u16Height ? pCfg->u16Height : pCfg->stClipWin.height; ++ ++ ++ // pitch ++ stDipConfig.u16Pitch = pCfg->u16Width; ++ ++ // width/height ++ stDipConfig.u16Width = pCfg->u16Width; ++ stDipConfig.u16Height = pCfg->u16Height; ++ ++ // frame number ++ stDipConfig.u8FrameNum = pCfg->u8FrameNum; ++ ++ // base address & offset ++ stDipConfig.u32BaseAddr = pCfg->u32BuffAddress; ++ stDipConfig.u32BaseSize = pCfg->u32BuffSize; ++ ++ // C base address & offset ++ if(pCfg->enDestFmtType == DIP_DEST_FMT_YC420_MVOP || ++ pCfg->enDestFmtType == DIP_DEST_FMT_YC420_MFE ) ++ { ++ stDipConfig.u32C_BaseAddr = pCfg->u32C_BuffAddress; ++ stDipConfig.u32C_BaseSize = pCfg->u32C_BuffSize; ++ stDipConfig.bSrc422 = TRUE; ++ stDipConfig.b444To422 = TRUE; ++ ++ } ++ else if(DIP_DEST_FMT_YC422==pCfg->enDestFmtType) ++ { ++ stDipConfig.bSrc422 = TRUE; ++ stDipConfig.b444To422 = TRUE; ++ } ++ else ++ { ++ stDipConfig.bSrc422 = FALSE; ++ stDipConfig.b444To422 = FALSE; ++ } ++ ++ stDipConfig.eDstFMT = pCfg->enDestFmtType == DIP_DEST_FMT_YC422 ? DIP_DST_FMT_YC422 : ++ pCfg->enDestFmtType == DIP_DEST_FMT_ARGB8888 ? DIP_DST_FMT_ARGB8888: ++ pCfg->enDestFmtType == DIP_DEST_FMT_RGB565 ? DIP_DST_FMT_RGB565: ++ pCfg->enDestFmtType == DIP_DEST_FMT_YC420_MVOP ? DIP_DST_FMT_YC420_MVOP : ++ DIP_DST_FMT_YC420_MFE; ++ stDipConfig.eSrcFMT = DIP_SRC_FMT_OP; ++ stDipConfig.bSrcYUV = TRUE; ++ stDipConfig.bWOnce = pCfg->enTrigMode == DIP_TRIGGER_ONCE ? TRUE : FALSE; ++ ++ DIP_DBG(DIP_DBG_LV_0, "SetDip: clip(%d, %d, %d, %d), w=%d, h:%d, FBnum:%d, Base:%x, Size:%x, CBase:%x, CSize:%x\n", ++ stDipConfig.stClipWin.x, stDipConfig.stClipWin.y, stDipConfig.stClipWin.width, stDipConfig.stClipWin.height, ++ stDipConfig.u16Width, stDipConfig.u16Height, stDipConfig.u8FrameNum, ++ (int)stDipConfig.u32BaseAddr, (int)stDipConfig.u32BaseSize, ++ (int)stDipConfig.u32C_BaseAddr, (int)stDipConfig.u32C_BaseSize); ++ ++ if(MApi_XC_Set_Dip_Config(stDipConfig) == E_APIXC_RET_FAIL) ++ { ++ bret = FALSE; ++ } ++ else ++ { ++ if(pCfg->enTrigMode == DIP_TRIGGER_LOOP) ++ { ++ MApi_XC_Set_Dip_Trig(TRUE); ++ } ++ else ++ { ++ DIP_DBG(DIP_DBG_LV_0, "Wonce On \n"); ++ MApi_XC_DIP_Set_Dwin_Wt_Once(TRUE); ++ MApi_XC_DIP_Set_Dwin_Wt_Once_Trig(TRUE); ++ } ++ } ++ } ++ ++ return bret; ++} ++ ++ ++MS_BOOL Dip_Set_WOnce_Base(PDIP_WONCE_BASE_CONFIG pCfg) ++{ ++ MS_BOOL bret = TRUE; ++ ++ if(pCfg->bTrig) ++ { ++ if(MApi_XC_DIP_Set_Base(pCfg->u32BuffAddress, pCfg->u32C_BuffAddress)) ++ { ++ MApi_XC_DIP_Set_Dwin_Wt_Once_Trig(TRUE); ++ } ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ ++ return bret; ++} ++ ++ ++ ++int _MDrv_DIPIO_IOC_Set_Interrupt(struct file *filp, unsigned long arg) ++{ ++ DIP_INTERRUPT_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (DIP_INTERRUPT_CONFIG __user *)arg, sizeof(DIP_INTERRUPT_CONFIG))) ++ { ++ printk("SCA FAIL %d ...\n",__LINE__); ++ return -EFAULT; ++ } ++ ++ ++ if(stCfg.bEn == true && MDrv_DIPW_InterruptIsAttached(0, NULL, NULL) == false ) ++ { ++ MDrv_DIPW_InterruptAttach(0, NULL, NULL); ++ } ++ else if(stCfg.bEn == false && MDrv_DIPW_InterruptIsAttached(0, NULL ,NULL) == true ) ++ { ++ MDrv_DIPW_InterruptDeAttach(0, NULL, NULL); ++ } ++ ++ if(stCfg.u32DIPW_Signal_PID) ++ { ++ MDrv_DIPW_Set_Signal_PID(stCfg.u32DIPW_Signal_PID); ++ } ++ ++ return 0; ++} ++ ++int _MDrv_DIPIO_IOC_Set_Dip_Config(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ DIP_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (DIP_CONFIG __user *)arg, sizeof(DIP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ if(!DIP_Set_Config(&stCfg)) ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++int _MDrv_DIPIO_IOC_Set_Dip_WOnce_Base(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ DIP_WONCE_BASE_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (DIP_WONCE_BASE_CONFIG __user *)arg, sizeof(DIP_WONCE_BASE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ if(!Dip_Set_WOnce_Base(&stCfg)) ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int _MDrv_DIPIO_IO_Get_Interrupt_Status(struct file *filp, unsigned long arg) ++{ ++ DIP_INTR_STATUS stIntrStatus; ++ ++ memset(&stIntrStatus, 0, sizeof(DIP_INTR_STATUS)); ++ stIntrStatus.u8DIPW_Status = MDrv_DIPW_Get_ISR_RecFlag(); ++ ++ if(copy_to_user((DIP_INTR_STATUS __user *)arg, &stIntrStatus, sizeof(DIP_INTR_STATUS))) ++ { ++ printk("SCA FAIL : %d \n",__LINE__); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++//============================================================================== ++long mstar_dip_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_devDIP.refCnt <= 0) ++ { ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] DIPIO_IOCTL refCnt =%d!!! \n", _devDIP.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_DIP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_DIP_MAX_NR) ++ { ++ DIP_DBG(DIP_DBG_LV_0, "[DIP] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ DIP_DBG(DIP_DBG_LV_0, "[DIP] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[SCA] SCAIO_IOCTL %s!!! \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_DIP_SET_INTERRUPT: ++ retval = _MDrv_DIPIO_IOC_Set_Interrupt(filp, u32Arg); ++ break; ++ ++ case IOCTL_DIP_SET_CONFIG: ++ retval = _MDrv_DIPIO_IOC_Set_Dip_Config(filp, u32Arg); ++ break; ++ ++ case IOCTL_DIP_SET_WONCE_BASE_CONFIG: ++ retval = _MDrv_DIPIO_IOC_Set_Dip_WOnce_Base(filp, u32Arg); ++ break; ++ ++ case IOCTL_DIP_GET_INTERRUPT_STATUS: ++ retval = _MDrv_DIPIO_IO_Get_Interrupt_Status(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ DIP_DBG(DIP_DBG_LV_0, "[DIP] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mstar_dipw_drv_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ if (atomic_read(&DIPW_intr_count) > 0) ++ { ++ atomic_set(&DIPW_intr_count,0); ++ return POLLIN | POLLRDNORM; /* readable */ ++ } ++ ++ return 0; ++} ++ ++static int mstar_dip_drv_probe(struct platform_device *pdev) ++{ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] mstar_dip_drv_probe\n"); ++ ++ ++ if(request_irq(INT_IRQ_DIPW, MDrv_DIPW_isr, 0, "DIPW_INTR ", NULL)) ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] request irq for dipw fail!\n"); ++ ++ return 0; ++} ++ ++static int mstar_dip_drv_remove(struct platform_device *pdev) ++{ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] mstar_dip_drv_remove\n"); ++ ++ return 0; ++} ++ ++ ++static int mstar_dip_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] mstar_dip_drv_suspend\n"); ++ ++ ++ return 0; ++} ++ ++ ++static int mstar_dip_drv_resume(struct platform_device *dev) ++{ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] mstar_dip_drv_resume\n"); ++ ++ ++ return 0; ++} ++ ++static void mstar_dip_drv_platfrom_release(struct device *device) ++{ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] mstar_dip_drv_platfrom_release\n"); ++ ++} ++ ++ ++int mstar_dip_drv_open(struct inode *inode, struct file *filp) ++{ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] DIP DRIVER OPEN\n"); ++ ++ DIPIO_ASSERT(_devDIP.refCnt>=0); ++ _devDIP.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mstar_dip_drv_release(struct inode *inode, struct file *filp) ++{ ++ ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] DIP DRIVER RELEASE\n"); ++ _devDIP.refCnt--; ++ DIPIO_ASSERT(_devDIP.refCnt>=0); ++ ++ free_irq(INT_IRQ_DIPW, MDrv_DIPW_isr); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_DIPIO_ModuleInit(void) ++{ ++ int ret = 0; ++ dev_t dev; ++ int s32Ret; ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIPIO]_Init \n"); ++ ++ if(_devDIP.s32Major) ++ { ++ dev = MKDEV(_devDIP.s32Major, _devDIP.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_DIP_DEVICE_COUNT, MDRV_DIP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _devDIP.s32Minor, MDRV_DIP_DEVICE_COUNT, MDRV_DIP_NAME); ++ _devDIP.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ DIP_DBG(DIP_DBG_LV_0, "[DIP] Unable to get major %d\n", _devDIP.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_devDIP.cdev, &_devDIP.fops); ++ if (0 != (s32Ret= cdev_add(&_devDIP.cdev, dev, MDRV_DIP_DEVICE_COUNT))) ++ { ++ DIP_DBG(DIP_DBG_LV_0, "[DIP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_DIP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ dip_class = class_create(THIS_MODULE, dip_classname); ++ if(IS_ERR(dip_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(dip_class, NULL, dev,NULL, "mdip"); ++ } ++ /* initial the whole DIP Driver */ ++ ret = platform_driver_register(&Mstar_dip_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&sg_mdrv_dip_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&Mstar_dip_driver); ++ DIP_DBG(DIP_DBG_LV_0, "[DIP] register failed\n"); ++ ++ } ++ else ++ { ++ DIP_DBG(DIP_DBG_LV_IOCTL, "[DIP] register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _MDrv_DIPIO_ModuleExit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ DIP_DBG(DIP_DBG_LV_0, "[DIPIO]_Exit \n"); ++ cdev_del(&_devDIP.cdev); ++ device_destroy(dip_class, MKDEV(_devDIP.s32Major, _devDIP.s32Minor)); ++ class_destroy(dip_class); ++ unregister_chrdev_region(MKDEV(_devDIP.s32Major, _devDIP.s32Minor), MDRV_DIP_DEVICE_COUNT); ++ platform_driver_unregister(&Mstar_dip_driver); ++} ++ ++ ++module_init(_MDrv_DIPIO_ModuleInit); ++module_exit(_MDrv_DIPIO_ModuleExit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("DIPioctrl driver"); ++MODULE_LICENSE("DIP"); ++ ++ +diff --git a/drivers/mstar/emac/Kconfig b/drivers/mstar/emac/Kconfig +new file mode 100644 +index 00000000..52ccf70c +--- /dev/null ++++ b/drivers/mstar/emac/Kconfig +@@ -0,0 +1,52 @@ ++config MS_EMAC ++select NET ++select NET_ETHERNET ++select MII ++select PACKET ++select USE_POLICY_FWD ++select INET ++select NETDEVICES ++ ++tristate "EMAC" ++default n ++ ++---help--- ++Enable compilation option for driver EMAC ++ ++if MS_EMAC ++config EMAC_SUPPLY_RNG ++bool "Supply to random number generator device" ++default n ++help ++ Supply to random number generator device ++ ++config ETHERNET_ALBANY ++bool "Supply to internel PHY" ++default n ++help ++ Supply to internel PHY ++ ++config MSTAR_HW_TX_CHECKSUM ++bool "Supply to hardware TX checksum" ++default n ++help ++ Supply to hardware TX checksum ++ ++config K3_RX_SWPATCH ++bool "Supply to K3 RX SW Patch" ++default n ++help ++ Supply to K3 RX frame drop due to padding 4 bytes issue ++ ++config DISCONNECT_DELAY_S ++int "Disconnect delay in second" ++default 1 ++help ++ Disconnect delay in second ++ ++config MSTAR_EEE ++bool "Supply to EEE function" ++default n ++help ++ Supply to EEE function ++endif +diff --git a/drivers/mstar/emac/Makefile b/drivers/mstar/emac/Makefile +new file mode 100644 +index 00000000..25aa5480 +--- /dev/null ++++ b/drivers/mstar/emac/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for MStar EMAC device drivers. ++# ++ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/mstar/emac ++EXTRA_CFLAGS += -Idrivers/mstar/emac/hal/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Iinclude/linux ++ ++# specific options ++# EXTRA_CFLAGS += -DRED_LION ++# files ++obj-$(CONFIG_MS_EMAC) := kdrv_emac.o ++kdrv_emac-y := mdrv_emac.o ++kdrv_emac-y += hal/$(CONFIG_MSTAR_CHIP_NAME)/mhal_emac.o +\ No newline at end of file +diff --git a/drivers/mstar/emac/hal/infinity/mhal_emac.c b/drivers/mstar/emac/hal/infinity/mhal_emac.c +new file mode 100644 +index 00000000..4761b01d +--- /dev/null ++++ b/drivers/mstar/emac/hal/infinity/mhal_emac.c +@@ -0,0 +1,1401 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_emac.c ++/// @brief EMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++///////////////////////////////////////////////////// ++// sync 2015.9.25 ++// CL1408633 //THEALE/RedLion/mstar2/drv/emac/ ++// CL1317815 //THEALE/RedLion/mstar2/hal/clippers/emac/ ++///////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++ ++extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct _MHalBasicConfigEMAC ++{ ++ u8 connected; // 0:No, 1:Yes ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _MHalBasicConfigEMAC MHalBasicConfigEMAC; ++ ++struct _MHalUtilityVarsEMAC ++{ ++ u32 cntChkCableConnect; ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ u8 flagISR_INT_DONE; ++}; ++typedef struct _MHalUtilityVarsEMAC MHalUtilityVarsEMAC; ++ ++MHalBasicConfigEMAC MHalThisBCE; ++MHalUtilityVarsEMAC MHalThisUVE; ++ ++#define MHal_MAX_INT_COUNTER 100 ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u8* ) address ) = val; ++} ++u32 MHal_EMAC_ReadReg32( u32 xoffset ) ++{ ++ u32 address = REG_ADDR_BASE + xoffset*2; ++ ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++} ++ ++void MHal_EMAC_WritReg32( u32 xoffset, u32 xval ) ++{ ++ u32 address = REG_ADDR_BASE + xoffset*2; ++ ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++} ++ ++u32 MHal_EMAC_ReadRam32( u32 uRamAddr, u32 xoffset) ++{ ++ return (*( u32 * ) ( ( char * ) uRamAddr + xoffset ) ); ++} ++ ++void MHal_EMAC_WritRam32( u32 uRamAddr, u32 xoffset, u32 xval ) ++{ ++ *( ( u32 * ) ( ( char * ) uRamAddr + xoffset ) ) = xval; ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA1L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA1H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32( REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_CTL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_CTL, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_CFG ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_CFG, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_RSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++ ++u32 MHal_EMAC_Read_ISR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ISR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_IER ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_IER, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_IDR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_IDR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_IMR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_MAN, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFF, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_FRA ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_MCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_OK ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SEQE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ALE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_LCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ECOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TUE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_CSE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ROVR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ELR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RJB ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SQEE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0100( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0100 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0100, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0108 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0108, xval ); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++ ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(0x134) & 0x00f00000) >> 20; ++} ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void) ++{ ++ return (MHal_EMAC_ReadReg32(0x134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(0x100); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(0x100, value); ++} ++ ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(0x100) & 0x00080000) >> 19; ++} ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(0x11c); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(0x11c, value); ++ ++ value = MHal_EMAC_ReadReg32(0x120); ++ value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(0x120, value); ++ ++ value = MHal_EMAC_ReadReg32(0x124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(0x124, value); ++} ++ ++void MHal_EMAC_Set_Miu_Highway(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(0x134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_HW_init(void) ++{ ++ MHal_EMAC_Set_Miu_Priority(1); ++ MHal_EMAC_Set_Tx_JULIAN_T(4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(2); ++ #endif ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_write_phy( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++#ifdef CONFIG_ETHERNET_ALBANY ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ ++ phy_addr =0; ++ ++ *(volatile unsigned int *)(uRegBase + address*4) = value; ++ udelay( 1 ); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(); ++ MHal_EMAC_enable_mdi(); ++ ++ MHal_EMAC_Write_MAN( uRegVal ); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & EMAC_IDLE ) ) ++ { ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(uCTL); ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_read_phy( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++#ifdef CONFIG_ETHERNET_ALBANY ++ ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(); ++ MHal_EMAC_enable_mdi(); ++ MHal_EMAC_Write_MAN(uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & EMAC_IDLE ) ) ++ { ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); ++ barrier(); ++ } ++ *value = ( MHal_EMAC_Read_MAN() & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(uCTL); ++#endif ++} ++ ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32( REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( uspeed == SPEED_100 ) ++ { ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32( REG_ETH_CFG, xval ); ++} ++ ++u8 MHal_EMAC_CalcMACHash( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq( void ) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ u8 uRegVal; ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA1H ); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA1L ); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA2H ); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA2L ); ++} ++ ++void MHal_EMAC_Write_SA1H( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA1H, xval ); ++} ++ ++void MHal_EMAC_Write_SA1L( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA1L, xval ); ++} ++ ++void MHal_EMAC_Write_SA2H( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA2H, xval ); ++} ++ ++void MHal_EMAC_Write_SA2L( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA2L, xval ); ++} ++ ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Check INT Done ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_CheckINTDone( void ) ++{ ++ u32 retIntStatus; ++ retIntStatus = MHal_EMAC_Read_ISR(); ++ MHalThisUVE.cntChkINTCounter = ( MHalThisUVE.cntChkINTCounter % ++ MHal_MAX_INT_COUNTER ); ++ MHalThisUVE.cntChkINTCounter ++; ++ if ( ( retIntStatus & EMAC_INT_DONE ) || ++ ( MHalThisUVE.cntChkINTCounter == ( MHal_MAX_INT_COUNTER - 1 ) ) ) ++ { ++ MHalThisUVE.flagISR_INT_DONE = 0x01; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++extern unsigned char phyaddr; ++//------------------------------------------------------------------------------------------------- ++// MAC cable connection detection ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_CableConnection( void ) ++{ ++ u32 retValue = 0; ++ u32 word_ETH_MAN = 0x00000000; ++ u32 word_ETH_CTL = MHal_EMAC_Read_CTL(); ++ ++ MHal_EMAC_Write_CTL( 0x00000010 | word_ETH_CTL ); ++ MHalThisUVE.flagISR_INT_DONE = 0x00; ++ MHalThisUVE.cntChkINTCounter = 0; ++ MHal_EMAC_read_phy(phyaddr, MII_BMSR, &word_ETH_MAN); ++ ++ if ( word_ETH_MAN & BMSR_LSTATUS ) ++ { ++ retValue = 1; ++ } ++ else ++ { ++ retValue = 0; ++ } ++ MHal_EMAC_Write_CTL( word_ETH_CTL ); ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Negotiation PHY ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_NegotiationPHY( void ) ++{ ++ // Set PHY -------------------------------------------------------------- ++ u32 retValue = 0; ++ u32 bmsr; ++ ++ // IMPORTANT: Get real duplex by negotiation with peer. ++ u32 word_ETH_CTL = MHal_EMAC_Read_CTL(); ++ MHal_EMAC_Write_CTL( 0x0000001C | word_ETH_CTL ); ++ ++ MHalThisBCE.duplex = 1; // Set default as Half-duplex if negotiation fails. ++ retValue = 1; ++ ++ MHalThisUVE.flagISR_INT_DONE = 0x00; ++ MHalThisUVE.cntChkINTCounter = 0; ++ MHalThisUVE.cntChkCableConnect = 0; ++ ++ ++ MHal_EMAC_read_phy(phyaddr, MII_BMSR, &bmsr); ++ if ( (bmsr & BMSR_100FULL) || (bmsr & BMSR_10FULL) ) ++ { ++ MHalThisBCE.duplex = 2; ++ retValue = 2; ++ } ++ else ++ { ++ MHalThisBCE.duplex = 1; ++ retValue = 1; ++ } ++ ++ // NOTE: REG_ETH_CFG must be set according to new ThisBCE.duplex. ++ ++ MHal_EMAC_Write_CTL( word_ETH_CTL ); ++ // Set PHY -------------------------------------------------------------- ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_timer_callback( unsigned long value ) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_EMAC_Read_IER(); ++ uRegVal |= ( EMAC_INT_RCOM ); ++ MHal_EMAC_Write_IER( uRegVal ); ++} ++ ++void MHal_EMAC_trim_phy( void ) ++{ ++ u8 uRegVal; ++ u8 uEfuVal0; ++ u8 uEfuVal1; ++ u8 uEfuVal2; ++ ++ //efuse read ++ MHal_EMAC_WritReg8(REG_BANK_EFUSE, 0x4e, 0x25); ++ MHal_EMAC_WritReg8(REG_BANK_EFUSE, 0x4f, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_EFUSE, 0x4c, 0x01); ++ ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_EFUSE, 0x4c); ++ ++ while((uRegVal & 0x00) != 0) ++ { ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_EFUSE, 0x4c); ++ } ++ ++ uEfuVal0 = MHal_EMAC_ReadReg8(REG_BANK_EFUSE, 0x84); ++ uEfuVal1 = MHal_EMAC_ReadReg8(REG_BANK_EFUSE, 0x85); ++ uEfuVal2 = MHal_EMAC_ReadReg8(REG_BANK_EFUSE, 0x86); ++ ++ //write efuse into phy trim register ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY2, 0x60); ++ uRegVal |= 0x04; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x60, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY2, 0x69); ++ uRegVal |= 0x80; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x69, uRegVal); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x68, uEfuVal0); ++ ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY2, 0x69); ++ uRegVal &= 0xc0; ++ uRegVal |= (uEfuVal1 & 0x3f); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x69, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY2, 0x61); ++ uRegVal &= 0xf0; ++ uRegVal |= (uEfuVal1 >> 6); ++ uRegVal |= (uEfuVal2 & 0x03) << 2 ; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x61, uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk( struct device dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ ++ num_parents = of_clk_get_parent_count(dev.of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev.of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_prepare_enable(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //emac_clk gen ++#ifdef CONFIG_ETHERNET_ALBANY ++/* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++*/ ++ ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0x84, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x44, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x46, 0x00); ++ ++ /* eth_link_sar*/ ++ ++ //gain shift ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xb7, 0x17); // Power-on ADC** ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcb, 0x11); // Power-on BGAP ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcc, 0x20); // Power-on ADCPL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcd, 0xd0); // Power-on ADCPL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xd4, 0x00); // Power-on LPF_OP ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xb9, 0x40); // Power-on LPF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xbb, 0x05); // Power-on REF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x3a, 0x03); // PD_TX_IDAC, PD_TX_LD = 0 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x3b, 0x00); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x3b, 0x01); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xa1, 0xc0); // PD_SADC, EN_SAR_LOGIC** ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x8a, 0x01); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xc4, 0x44); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x80, 0x30); ++ ++ //100 gat ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++ ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(REG_BANK_PMSLEEP, 0x50, uRegVal); ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#else ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc0, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc1, 0x04); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc2, 0x04); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc3, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc4, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc5, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x47, 0x00); ++#endif ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //chiptop :et_mode ++#ifdef CONFIG_ETHERNET_ALBANY ++ //uRegVal = MHal_EMAC_ReadReg8(REG_BANK_CHIPTOP, 0xdf); ++ //uRegVal &= 0xfe; ++ //MHal_EMAC_WritReg8(REG_BANK_CHIPTOP, 0xdf, uRegVal); ++#else ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#endif ++ ++ ++ ++} ++ ++void MHal_EMAC_Power_Off_Clk( struct device dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++ u8 uRegVal; ++ ++ num_parents = of_clk_get_parent_count(dev.of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev.of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++ ++#ifdef CONFIG_ETHERNET_ALBANY ++ //Power Down EMAC phy ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfd, 0x01); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xb7, 0x17); // Power-on ADC** ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcb, 0x13); // Power-on BGAP ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcc, 0x30); // Power-on ADCPL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcd, 0xd8); // Power-on ADCPL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xd4, 0x20); // Power-on LPF_OP ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xb9, 0x41); // Power-on LPF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xbb, 0x84); // Power-on REF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x3a, 0xf3); // PD_TX_IDAC, PD_TX_LD = 0 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x3b, 0x03); ++ ++// MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x3b, 0x01); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xa1, 0x20); // PD_SADC, EN_SAR_LOGIC** ++// MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x8a, 0x01); ++// MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xc4, 0x44); ++// MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x80, 0x30); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xc5, 0x40); //100 gat ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x30, 0x53); //200 gat ++ ++ ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(REG_BANK_PMSLEEP, 0x50, uRegVal); ++ ++#endif ++} ++ ++void MHal_EMAC_Set_Reverse_LED(u32 xval) ++{ ++ u8 u8Reg; ++ ++ u8Reg = MHal_EMAC_ReadReg8( REG_BANK_ALBANY0, 0xf7 ); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++u8 MHal_EMAC_Get_Reverse_LED(void) ++{ ++ return (MHal_EMAC_ReadReg8( REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} +diff --git a/drivers/mstar/emac/hal/infinity/mhal_emac.h b/drivers/mstar/emac/hal/infinity/mhal_emac.h +new file mode 100644 +index 00000000..bf0492f2 +--- /dev/null ++++ b/drivers/mstar/emac/hal/infinity/mhal_emac.h +@@ -0,0 +1,421 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ( "MStar Confidential Information" ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file EMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief EMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_EMAC__ ++#define __DRV_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM ++#define INT_JULIAN_D ++#define CHIP_FLUSH_READ ++#define TX_QUEUE_4 ++//#define ISR_BOTTOM_HALF //for RX ++//#define TX_SOFTWARE_QUEUE //for TX ++#define TX_SKB_PTR ++//#define TX_SW_QUEUE ++#define MSTAR_EMAC_NAPI ++#define RX_ZERO_COPY ++//#define LAN_ESD_CARRIER_INTERRUPT ++ ++#ifdef TX_SW_QUEUE ++#define TX_SW_QUEUE_SIZE (1024) //effected size = TX_RING_SIZE - 1 ++#define TX_DESC_CLEARED 0 ++#define TX_DESC_WROTE 1 ++#define TX_DESC_READ 2 ++#define TX_FIFO_SIZE 4 //HW FIFO size ++#endif ++ ++#ifdef TX_QUEUE_4 ++#define TX_RING_SIZE (4) //effected size = TX_RING_SIZE - 1 ++#define EMAC_TX_COUNT (14) //offset of TX counter in TSR ++#else ++#define TX_RING_SIZE (2) //effected size = TX_RING_SIZE - 1 ++#endif ++ ++ ++#ifdef TX_QUEUE_4 ++#define EMAC_INT_MASK (0xdff) ++#else ++#define EMAC_INT_MASK (0xdff) ++#endif ++ ++// Compiler Switches ++#define REG_BIT_MAP ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#define REG_BANK_PMSLEEP 0x000E ++ ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++#define EMAC_SPEED_10 10 ++#define EMAC_SPEED_100 100 ++ ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++#define EMAC_MAX_TX_QUEUE 1000 ++ ++// Base address here: ++#define MIU0_BUS_BASE 0x20000000 ++#define REG_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#define RBQP_LENG 0x80 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/mstar/emac/hal/infinity3/mhal_emac.c b/drivers/mstar/emac/hal/infinity3/mhal_emac.c +new file mode 100644 +index 00000000..bd2ffce0 +--- /dev/null ++++ b/drivers/mstar/emac/hal/infinity3/mhal_emac.c +@@ -0,0 +1,1503 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file Mhal_emac.c ++/// @brief EMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++///////////////////////////////////////////////////// ++// sync 2015.9.25 ++// CL1408633 //THEALE/RedLion/mstar2/drv/emac/ ++// CL1317815 //THEALE/RedLion/mstar2/hal/clippers/emac/ ++///////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mhal_emac.h" ++#include "mdrv_types.h" ++#include "ms_platform.h" ++#include "infinity3/registers.h" ++ ++extern unsigned char phyaddr; ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct _MHalBasicConfigEMAC ++{ ++ u8 connected; // 0:No, 1:Yes ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _MHalBasicConfigEMAC MHalBasicConfigEMAC; ++ ++struct _MHalUtilityVarsEMAC ++{ ++ u32 cntChkCableConnect; ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ u8 flagISR_INT_DONE; ++}; ++typedef struct _MHalUtilityVarsEMAC MHalUtilityVarsEMAC; ++ ++MHalBasicConfigEMAC MHalThisBCE; ++MHalUtilityVarsEMAC MHalThisUVE; ++ ++#define MHal_MAX_INT_COUNTER 100 ++//------------------------------------------------------------------------------------------------- ++// EMAC hardware for Titania ++//------------------------------------------------------------------------------------------------- ++ ++/*8-bit RIU address*/ ++u8 MHal_EMAC_ReadReg8( u32 bank, u32 reg ) ++{ ++ u8 val; ++ u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ val = *( ( volatile u8* ) address ); ++ return val; ++} ++ ++void MHal_EMAC_WritReg8( u32 bank, u32 reg, u8 val ) ++{ ++ u32 address = EMAC_RIU_REG_BASE + bank*0x100*2; ++ address = address + (reg << 1) - (reg & 1); ++ ++ *( ( volatile u8* ) address ) = val; ++} ++ ++/* Read/WriteReg32 access two continuous 16bit-width register for EMAC0. ++EMAC0 bank is 32bit register, that must write low 16bit-width address then high 16bit-width address. */ ++u32 MHal_EMAC_ReadReg32( u32 xoffset ) ++{ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ u32 address = EMAC_RIU_REG_BASE + REG_BANK_EMAC0*0x200 + xoffset*2; ++ u32 xoffsetValueL = *( ( volatile u32* ) address ) & 0x0000FFFF; ++ u32 xoffsetValueH = *( ( volatile u32* ) ( address + 4) ) << 0x10; ++ return( xoffsetValueH | xoffsetValueL ); ++ } ++ else ++ { ++ u32 address = EMAC_RIU_REG_BASE + REG_BANK_X32_EMAC0*0x200 + xoffset*2; ++ return *( ( volatile u32* ) address ); ++ } ++} ++ ++void MHal_EMAC_WritReg32( u32 xoffset, u32 xval ) ++{ ++ if(xoffset>=REG_EMAC_JULIAN_0100) ++ { ++ u32 address = EMAC_RIU_REG_BASE + REG_BANK_EMAC0*0x200 + xoffset*2; ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval & 0x0000FFFF ); ++ *( ( volatile u32 * ) ( address + 4 ) ) = ( u32 ) ( xval >> 0x10 ); ++ } ++ else ++ { ++ u32 address = EMAC_RIU_REG_BASE + REG_BANK_X32_EMAC0*0x200 + xoffset*2; ++ *( ( volatile u32 * ) address ) = ( u32 ) ( xval ); ++ } ++} ++ ++u32 MHal_EMAC_ReadRam32( u32 uRamAddr, u32 xoffset) ++{ ++ return (*( u32 * ) ( ( char * ) uRamAddr + xoffset ) ); ++} ++ ++void MHal_EMAC_WritRam32( u32 uRamAddr, u32 xoffset, u32 xval ) ++{ ++ *( ( u32 * ) ( ( char * ) uRamAddr + xoffset ) ) = xval; ++} ++ ++void MHal_EMAC_Write_SA1_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA1L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA1H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA2_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA2L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA2H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA3_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA3L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA3H, w1 ); ++} ++ ++void MHal_EMAC_Write_SA4_MAC_Address( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u32 w0 = ( u32 ) m3 << 24 | m2 << 16 | m1 << 8 | m0; ++ u32 w1 = ( u32 ) m5 << 8 | m4; ++ MHal_EMAC_WritReg32( REG_ETH_SA4L, w0 ); ++ MHal_EMAC_WritReg32( REG_ETH_SA4H, w1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// R/W EMAC register for Titania ++//------------------------------------------------------------------------------------------------- ++ ++void MHal_EMAC_update_HSH(u32 mc0, u32 mc1) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_HSL, mc0 ); ++ MHal_EMAC_WritReg32( REG_ETH_HSH, mc1 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read control register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CTL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_CTL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CTL( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_CTL, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Network configuration register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CFG( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_CFG ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Network configuration register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_CFG( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_CFG, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RBQP( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RBQP ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write RBQP ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RBQP( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_RBQP, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Address register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TAR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TAR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read RBQP ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TCR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TCR); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Transmit Control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TCR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TCR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit Status Register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_TSR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_TSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_TSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TSR ); ++} ++ ++void MHal_EMAC_Write_RSR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_RSR, xval ); ++} ++ ++u32 MHal_EMAC_Read_RSR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RSR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt status register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_ISR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_ISR, xval ); ++} ++ ++u32 MHal_EMAC_Read_ISR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ISR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IER( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_IER ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt enable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IER( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_IER, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IDR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_IDR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Interrupt disable register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_IDR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_IDR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Interrupt mask register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_IMR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_IMR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MAN( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_MAN ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write PHY maintenance register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_MAN( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_MAN, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_BUFF( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFF, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive Buffer Configuration ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_BUFF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RDPTR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_BUFFRDPTR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_RDPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFRDPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Receive First Full Pointer ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_WRPTR( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_BUFFWRPTR, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames transmitted OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_FRA( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_FRA ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Single collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SCOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Multiple collision frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_MCOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_MCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frames received OK ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_OK( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_OK ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Frame check sequence errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SEQE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SEQE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Alignment errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ALE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ALE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Late collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_LCOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_LCOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive collisions ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ECOL( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ECOL ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Transmit under-run errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_TUE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_TUE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Carrier sense errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_CSE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_CSE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive resource error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received overrun ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ROVR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ROVR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Received symbols error ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Excessive length errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_ELR( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_ELR ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Receive jabbers ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_RJB( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_RJB ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Undersize frames ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_USF( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_USF ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SQE test errors ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_SQEE( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SQEE ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 100 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0100( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0100 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 100 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0100( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0100, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 104 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0104( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0104 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 104 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0104( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0104, xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Read Julian 108 ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_Read_JULIAN_0108( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_EMAC_JULIAN_0108 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write Julian 108 ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Write_JULIAN_0108( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_EMAC_JULIAN_0108, xval ); ++} ++ ++void MHal_EMAC_Set_Tx_JULIAN_T(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xff0fffff; ++ value |= xval << 20; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++void MHal_EMAC_Set_TEST(u32 xval) ++{ ++ u32 value = 0xffffffff; ++ int i=0; ++ ++ for(i = 0x100; i< 0x160;i+=4){ ++ MHal_EMAC_WritReg32(i, value); ++ } ++ ++} ++ ++u32 MHal_EMAC_Get_Tx_FIFO_Threshold(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x00f00000) >> 20; ++} ++ ++void MHal_EMAC_Set_Rx_FIFO_Enlarge(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfcffffff; ++ value |= xval << 24; ++ ++ MHal_EMAC_WritReg32(0x134, value); ++} ++ ++u32 MHal_EMAC_Get_Rx_FIFO_Enlarge(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134) & 0x03000000) >> 24; ++} ++ ++void MHal_EMAC_Set_Miu_Priority(u32 xval) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(0x100, value); ++} ++ ++u32 MHal_EMAC_Get_Miu_Priority(void) ++{ ++ return (MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0100) & 0x00080000) >> 19; ++} ++ ++void MHal_EMAC_Set_Tx_Hang_Fix_ECO(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfffbffff; ++ value |= xval << 18; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_MIU_Out_Of_Range_Fix(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xefffffff; ++ value |= xval << 28; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Tx_Burst16_Mode(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xdfffffff; ++ value |= xval << 29; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Tx_Rx_Req_Priority_Switch(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xfff7ffff; ++ value |= xval << 19; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Set_Rx_Byte_Align_Offset(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xf3ffffff; ++ value |= xval << 26; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_Write_Protect(u32 start_addr, u32 length) ++{ ++ u32 value; ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_011C); ++ value &= 0x0000ffff; ++ value |= ((start_addr+length) >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_011C, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0120); ++ //value &= 0x00000000; ++ value |= ((start_addr+length) >> 4) >> 16; ++ value |= (start_addr >> 4) << 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0120, value); ++ ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0124); ++ value &= 0xffff0000; ++ value |= (start_addr >> 4) >> 16; ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0124, value); ++} ++ ++void MHal_EMAC_Set_Miu_Highway(u32 xval) ++{ ++ u32 value; ++ value = MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0134); ++ value &= 0xbfffffff; ++ value |= xval << 30; ++ ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0134, value); ++} ++ ++void MHal_EMAC_HW_init(void) ++{ ++ MHal_EMAC_Set_Miu_Priority(1); ++ MHal_EMAC_Set_Tx_JULIAN_T(4); ++ MHal_EMAC_Set_Rx_Tx_Burst16_Mode(1); ++ MHal_EMAC_Set_Rx_FIFO_Enlarge(2); ++ MHal_EMAC_Set_Tx_Hang_Fix_ECO(1); ++ MHal_EMAC_Set_MIU_Out_Of_Range_Fix(1); ++ #ifdef RX_BYTE_ALIGN_OFFSET ++ MHal_EMAC_Set_Rx_Byte_Align_Offset(2); ++ #endif ++ MHal_EMAC_WritReg32(REG_EMAC_JULIAN_0138, MHal_EMAC_ReadReg32(REG_EMAC_JULIAN_0138) | 0x00000001); ++// MHal_EMAC_Set_Miu_Highway(1); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// PHY INTERFACE ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable the MDIO bit in MAC control register ++// When not called from an interrupt-handler, access to the PHY must be ++// protected by a spinlock. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(); ++ xval |= EMAC_MPE; ++ MHal_EMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the MDIO bit in the MAC control register ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_mdi( void ) ++{ ++ u32 xval; ++ xval = MHal_EMAC_Read_CTL(); ++ xval &= ~EMAC_MPE; ++ MHal_EMAC_Write_CTL( xval ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Write value to the a PHY register ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_write_phy( unsigned char phy_addr, unsigned char address, u32 value ) ++{ ++#ifdef CONFIG_ETHERNET_ALBANY ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ ++ phy_addr =0; ++ ++ *(volatile unsigned int *)(uRegBase + address*4) = value; ++ udelay( 1 ); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ uRegVal = ( EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_W) | (( phy_addr & 0x1F ) << PHY_ADDR_OFFSET ) ++ | ( address << PHY_REGADDR_OFFSET ) | (value & 0xFFFF); ++ ++ uCTL = MHal_EMAC_Read_CTL(); ++ MHal_EMAC_enable_mdi(); ++ ++ MHal_EMAC_Write_MAN( uRegVal ); ++ // Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & EMAC_IDLE ) ) ++ { ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); ++ barrier(); ++ } ++ MHal_EMAC_Write_CTL(uCTL); ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// Read value stored in a PHY register. ++// Note: MDI interface is assumed to already have been enabled. ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_read_phy( unsigned char phy_addr, unsigned char address, u32* value ) ++{ ++#ifdef CONFIG_ETHERNET_ALBANY ++ ++ u32 uRegBase = INTERNEL_PHY_REG_BASE; ++ u32 tempvalue ; ++ ++ phy_addr =0; ++ ++ tempvalue = *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04); ++ tempvalue |= 0x0004; ++ *(volatile unsigned int *)(INTERNEL_PHY_REG_BASE + 0x04) = tempvalue; ++ udelay( 1 ); ++ *value = *(volatile unsigned int *)(uRegBase + address*4); ++#else ++ u32 uRegVal = 0, uCTL = 0; ++ ++ uRegVal = (EMAC_HIGH | EMAC_CODE_802_3 | EMAC_RW_R) ++ | ((phy_addr & 0x1f) << PHY_ADDR_OFFSET) | (address << PHY_REGADDR_OFFSET) | (0) ; ++ ++ uCTL = MHal_EMAC_Read_CTL(); ++ MHal_EMAC_enable_mdi(); ++ MHal_EMAC_Write_MAN(uRegVal); ++ ++ //Wait until IDLE bit in Network Status register is cleared // ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); //Must read Low 16 bit. ++ while ( !( uRegVal & EMAC_IDLE ) ) ++ { ++ uRegVal = MHal_EMAC_ReadReg32( REG_ETH_SR ); ++ barrier(); ++ } ++ *value = ( MHal_EMAC_Read_MAN() & 0x0000ffff ); ++ MHal_EMAC_Write_CTL(uCTL); ++#endif ++} ++ ++#ifdef CONFIG_ETHERNET_ALBANY ++void MHal_EMAC_TX_10MB_lookUp_table( void ) ++{ ++ // tx 10T link test pulse ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x0f*4) ) = 0x9800; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x10*4) ) = 0x8484; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x11*4) ) = 0x8888; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x12*4) ) = 0x8c8c; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x13*4) ) = 0xC898; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x14*4) ) = 0x0000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x15*4) ) = 0x1000; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) = ( (*( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x16*4) ) & 0xFF00) | 0x0000 ); ++ ++ // tx 10T look up table. ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x44*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x45*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x46*4) ) = 0x3C30; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x47*4) ) = 0x687C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x48*4) ) = 0x7834; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x49*4) ) = 0xD494; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4A*4) ) = 0x84A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4B*4) ) = 0xE4C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4C*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4D*4) ) = 0xC8E8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4E*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x4F*4) ) = 0x3C3C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x50*4) ) = 0x2430; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x51*4) ) = 0x707C; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x52*4) ) = 0x6420; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x53*4) ) = 0xD4A0; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x54*4) ) = 0x8498; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x55*4) ) = 0xD0C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x56*4) ) = 0xC8C8; ++ *( ( u32 * ) ( ( char * ) INTERNEL_PHY_REG_BASE + 0x57*4) ) = 0xC8C8; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Update MAC speed and H/F duplex ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_update_speed_duplex( u32 uspeed, u32 uduplex ) ++{ ++ u32 xval; ++ ++ xval = MHal_EMAC_ReadReg32( REG_ETH_CFG ) & ~( EMAC_SPD | EMAC_FD ); ++ ++ if ( uspeed == SPEED_100 ) ++ { ++ if ( uduplex == DUPLEX_FULL ) // 100 Full Duplex // ++ { ++ xval = xval | EMAC_SPD | EMAC_FD; ++ } ++ else // 100 Half Duplex /// ++ { ++ xval = xval | EMAC_SPD; ++ } ++ } ++ else ++ { ++ if ( uduplex == DUPLEX_FULL ) //10 Full Duplex // ++ { ++ xval = xval | EMAC_FD; ++ } ++ else // 10 Half Duplex // ++ { ++ } ++ } ++ MHal_EMAC_WritReg32( REG_ETH_CFG, xval ); ++} ++ ++u8 MHal_EMAC_CalcMACHash( u8 m0, u8 m1, u8 m2, u8 m3, u8 m4, u8 m5 ) ++{ ++ u8 hashIdx0 = ( m0&0x01 ) ^ ( ( m0&0x40 ) >> 6 ) ^ ( ( m1&0x10 ) >> 4 ) ^ ( ( m2&0x04 ) >> 2 ) ++ ^ ( m3&0x01 ) ^ ( ( m3&0x40 ) >> 6 ) ^ ( ( m4&0x10 ) >> 4 ) ^ ( ( m5&0x04 ) >> 2 ); ++ ++ u8 hashIdx1 = ( m0&0x02 ) ^ ( ( m0&0x80 ) >> 6 ) ^ ( ( m1&0x20 ) >> 4 ) ^ ( ( m2&0x08 ) >> 2 ) ++ ^ ( m3&0x02 ) ^ ( ( m3&0x80 ) >> 6 ) ^ ( ( m4&0x20 ) >> 4 ) ^ ( ( m5&0x08 ) >> 2 ); ++ ++ u8 hashIdx2 = ( m0&0x04 ) ^ ( ( m1&0x01 ) << 2 ) ^ ( ( m1&0x40 ) >> 4 ) ^ ( ( m2&0x10 ) >> 2 ) ++ ^ ( m3&0x04 ) ^ ( ( m4&0x01 ) << 2 ) ^ ( ( m4&0x40 ) >> 4 ) ^ ( ( m5&0x10 ) >> 2 ); ++ ++ u8 hashIdx3 = ( m0&0x08 ) ^ ( ( m1&0x02 ) << 2 ) ^ ( ( m1&0x80 ) >> 4 ) ^ ( ( m2&0x20 ) >> 2 ) ++ ^ ( m3&0x08 ) ^ ( ( m4&0x02 ) << 2 ) ^ ( ( m4&0x80 ) >> 4 ) ^ ( ( m5&0x20 ) >> 2 ); ++ ++ u8 hashIdx4 = ( m0&0x10 ) ^ ( ( m1&0x04 ) << 2 ) ^ ( ( m2&0x01 ) << 4 ) ^ ( ( m2&0x40 ) >> 2 ) ++ ^ ( m3&0x10 ) ^ ( ( m4&0x04 ) << 2 ) ^ ( ( m5&0x01 ) << 4 ) ^ ( ( m5&0x40 ) >> 2 ); ++ ++ u8 hashIdx5 = ( m0&0x20 ) ^ ( ( m1&0x08 ) << 2 ) ^ ( ( m2&0x02 ) << 4 ) ^ ( ( m2&0x80 ) >> 2 ) ++ ^ ( m3&0x20 ) ^ ( ( m4&0x08 ) << 2 ) ^ ( ( m5&0x02 ) << 4 ) ^ ( ( m5&0x80 ) >> 2 ); ++ ++ return( hashIdx0 | hashIdx1 | hashIdx2 | hashIdx3 | hashIdx4 | hashIdx5 ); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and enable the PHY interrupt when link-state changes ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_enable_phyirq( void ) ++{ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ u8 uRegVal; ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY2, 0x75*2); ++ uRegVal |= BIT4; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x75*2, uRegVal); ++ ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_ALBANY0, 0x30*2); ++ uRegVal = (uRegVal&~0x00F0) | 0x00A0; ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x30*2, uRegVal); ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable the PHY interrupt ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_disable_phyirq( void ) ++{ ++#if 0 ++ ++#endif ++} ++//------------------------------------------------------------------------------------------------- ++// ++//------------------------------------------------------------------------------------------------- ++ ++u32 MHal_EMAC_get_SA1H_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA1H ); ++} ++ ++u32 MHal_EMAC_get_SA1L_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA1L ); ++} ++ ++u32 MHal_EMAC_get_SA2H_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA2H ); ++} ++ ++u32 MHal_EMAC_get_SA2L_addr( void ) ++{ ++ return MHal_EMAC_ReadReg32( REG_ETH_SA2L ); ++} ++ ++void MHal_EMAC_Write_SA1H( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA1H, xval ); ++} ++ ++void MHal_EMAC_Write_SA1L( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA1L, xval ); ++} ++ ++void MHal_EMAC_Write_SA2H( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA2H, xval ); ++} ++ ++void MHal_EMAC_Write_SA2L( u32 xval ) ++{ ++ MHal_EMAC_WritReg32( REG_ETH_SA2L, xval ); ++} ++ ++void* MDev_memset( void* s, u32 c, unsigned long count ) ++{ ++ char* xs = ( char* ) s; ++ ++ while ( count-- ) ++ *xs++ = c; ++ ++ return s; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Check INT Done ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_CheckINTDone( void ) ++{ ++ u32 retIntStatus; ++ retIntStatus = MHal_EMAC_Read_ISR(); ++ MHalThisUVE.cntChkINTCounter = ( MHalThisUVE.cntChkINTCounter % ++ MHal_MAX_INT_COUNTER ); ++ MHalThisUVE.cntChkINTCounter ++; ++ if ( ( retIntStatus & EMAC_INT_DONE ) || ++ ( MHalThisUVE.cntChkINTCounter == ( MHal_MAX_INT_COUNTER - 1 ) ) ) ++ { ++ MHalThisUVE.flagISR_INT_DONE = 0x01; ++ return TRUE; ++ } ++ return FALSE; ++} ++ ++extern unsigned char phyaddr; ++//------------------------------------------------------------------------------------------------- ++// MAC cable connection detection ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_CableConnection( void ) ++{ ++ u32 retValue = 0; ++ u32 word_ETH_MAN = 0x00000000; ++ u32 word_ETH_CTL = MHal_EMAC_Read_CTL(); ++ ++ MHal_EMAC_Write_CTL( 0x00000010 | word_ETH_CTL ); ++ MHalThisUVE.flagISR_INT_DONE = 0x00; ++ MHalThisUVE.cntChkINTCounter = 0; ++ MHal_EMAC_read_phy(phyaddr, MII_BMSR, &word_ETH_MAN); ++ ++ if ( word_ETH_MAN & BMSR_LSTATUS ) ++ { ++ retValue = 1; ++ } ++ else ++ { ++ retValue = 0; ++ } ++ MHal_EMAC_Write_CTL( word_ETH_CTL ); ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Negotiation PHY ++//------------------------------------------------------------------------------------------------- ++u32 MHal_EMAC_NegotiationPHY( void ) ++{ ++ // Set PHY -------------------------------------------------------------- ++ u32 retValue = 0; ++ u32 bmsr; ++ ++ // IMPORTANT: Get real duplex by negotiation with peer. ++ u32 word_ETH_CTL = MHal_EMAC_Read_CTL(); ++ MHal_EMAC_Write_CTL( 0x0000001C | word_ETH_CTL ); ++ ++ MHalThisBCE.duplex = 1; // Set default as Half-duplex if negotiation fails. ++ retValue = 1; ++ ++ MHalThisUVE.flagISR_INT_DONE = 0x00; ++ MHalThisUVE.cntChkINTCounter = 0; ++ MHalThisUVE.cntChkCableConnect = 0; ++ ++ ++ MHal_EMAC_read_phy(phyaddr, MII_BMSR, &bmsr); ++ if ( (bmsr & BMSR_100FULL) || (bmsr & BMSR_10FULL) ) ++ { ++ MHalThisBCE.duplex = 2; ++ retValue = 2; ++ } ++ else ++ { ++ MHalThisBCE.duplex = 1; ++ retValue = 1; ++ } ++ ++ // NOTE: REG_ETH_CFG must be set according to new ThisBCE.duplex. ++ ++ MHal_EMAC_Write_CTL( word_ETH_CTL ); ++ // Set PHY -------------------------------------------------------------- ++ return(retValue); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer set for Receive function ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_timer_callback( unsigned long value ) ++{ ++ u32 uRegVal; ++ uRegVal = MHal_EMAC_Read_IER(); ++ uRegVal |= ( EMAC_INT_RCOM ); ++ MHal_EMAC_Write_IER( uRegVal ); ++} ++ ++void MHal_EMAC_trim_phy( void ) ++{ ++ ++ U16 val; ++ if( INREG16(BASE_REG_EFUSE_PA+0x0B*4) & BIT4 ) ++ { ++ SETREG16(BASE_REG_RIU_PA+0x3360*2, BIT2); ++ SETREG16(BASE_REG_RIU_PA+0x3368*2, BIT15); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4)) & 0x001F; //read bit[4:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (val<<5), 0x1F<<5); //overwrite bit[9:5] ++ printk("ETH 10T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 5) & 0x001F; //read bit[9:5] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), val, 0x001F); //overwrite bit[4:0] ++ printk("ETH 100T output swing trim=0x%x\n",val); ++ ++ val = (INREG16(BASE_REG_EFUSE_PA+0x0A*4) >> 10) & 0x000F; //read bit[13:10] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3360*2), (val<<7), 0xF<<7); //overwrite bit[10:7] //different with I1 ++ printk("ETH RX input impedance trim=0x%x\n",val); ++ ++ val = INREG16(BASE_REG_EFUSE_PA+0x0B*4) & 0x000F; //read bit[3:0] ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (val<<10), 0xF<<10); //overwrite bit[13:10] ++ printk("ETH TX output impedance trim=0x%x\n",val); ++ } ++ else ++ { ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0x0<<5), 0x1F<<5); //overwrite bit[9:5] ++ } ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ ++} ++ ++void MHal_EMAC_phy_trunMax( void ) ++{ ++ OUTREGMSK16((BASE_REG_RIU_PA+ 0x3368*2), (0xF<<5), 0x1F<<5); //overwrite bit[9:5] ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x79, 0xf0); // prevent packet drop by inverted waveform ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC clock on/off ++//------------------------------------------------------------------------------------------------- ++void MHal_EMAC_Power_On_Clk( struct device *dev ) ++{ ++ u8 uRegVal; ++ int num_parents, i; ++ struct clk **emac_clks; ++ struct clk *clk_parent; ++ ++ //Triming PHY setting via efuse value ++ //MHal_EMAC_trim_phy(); ++ ++ //swith RX discriptor format to mode 1 ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x3a, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x3b, 0x01); ++ ++ //RX shift patch ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, 0x00); ++ uRegVal |= 0x10; ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x00, uRegVal); ++ ++ //TX underrun patch ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, 0x39); ++ uRegVal |= 0x01; ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, 0x39, uRegVal); ++ ++ //emac_clk gen ++#ifdef CONFIG_ETHERNET_ALBANY ++/* ++ wriu 0x103884 0x00 //Set CLK_EMAC_AHB to 123MHz (Enabled) ++ wriu 0x113344 0x00 //Set CLK_EMAC_RX to CLK_EMAC_RX_in (25MHz) (Enabled) ++ wriu 0x113346 0x00 //Set CLK_EMAC_TX to CLK_EMAC_TX_IN (25MHz) (Enabled) ++*/ ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ ++ /* Get parent clock */ ++ clk_parent = clk_get_parent_by_index(emac_clks[i], 0); ++ if(IS_ERR(clk_parent)) ++ { ++ kfree(emac_clks); ++ printk( "[EMAC]can't get parent clock\n" ); ++ return; ++ } ++ /* Set clock parent */ ++ clk_set_parent(emac_clks[i], clk_parent); ++ clk_prepare_enable(emac_clks[i]); ++ } ++ kfree(emac_clks); ++ } ++#else ++ MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x44, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x46, 0x00); ++#endif ++ ++ /* eth_link_sar*/ ++ //gain shift ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xb4, 0x02); ++ ++ //det max ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x4f, 0x02); ++ ++ //det min ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x51, 0x01); ++ ++ //snr len (emc noise) ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x77, 0x18); ++ ++ //lpbk_enable set to 0 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x72, 0xa0); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfc, 0x00); // Power-on LDO ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfd, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xa1, 0x80); // Power-on SADC ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcc, 0x40); // Power-on ADCPL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xbb, 0x04); // Power-on REF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x3a, 0x00); // Power-on TX ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xf1, 0x00); // Power-on TX ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x8a, 0x01); // CLKO_ADC_SEL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x3b, 0x01); // reg_adc_clk_select ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xc4, 0x44); // TEST ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x80, 0x30); // sadc timer ++ ++ //100 gat ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xc5, 0x00); ++ ++ //200 gat ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x30, 0x43); ++ ++ //en_100t_phase ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x39, 0x41); // en_100t_phase; [6] save2x_tx ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xf2, 0xf5); // LP mode, DAC OFF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xf3, 0x0d); // DAC off ++ ++ // Prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x79, 0xd0); // prevent packet drop by inverted waveform ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x77, 0x5a); ++ ++ //disable eee ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x2d, 0x7c); // disable eee ++ ++ //10T waveform ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x06); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x2b, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x2b, 0x00); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x06); // shadow_ctrl ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xaa, 0x1c); // tin17_s2 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xac, 0x1c); // tin18_s2 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xad, 0x1c); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xae, 0x1c); // tin19_s2 ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xaf, 0x1c); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xe8, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xaa, 0x1c); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xab, 0x28); ++ ++ //speed up timing recovery ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xf5, 0x02); ++ ++ // Signal_det k ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x0f, 0xc9); ++ ++ // snr_h ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x89, 0x50); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x8b, 0x80); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x8e, 0x0e); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x90, 0x04); ++ ++ //set CLKsource to hv ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xC7, 0x80); ++ ++ ++ //enable LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30)|0x10; ++ MHal_EMAC_WritReg8(REG_BANK_PMSLEEP, 0x50, uRegVal); ++ ++ ////swap LED0 and LED1 ++ //MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, BIT7); ++ ++#else ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc0, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc1, 0x04); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc2, 0x04); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc3, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc4, 0x00); ++ //MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0xc5, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0x84, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x44, 0x04); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x45, 0x00); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x46, 0x04); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x47, 0x00); ++#endif ++ ++ //chiptop [15] allpad_in ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_CHIPTOP, 0xa1); ++ uRegVal &= 0x7f; ++ MHal_EMAC_WritReg8(REG_BANK_CHIPTOP, 0xa1, uRegVal); ++ ++ //chiptop :et_mode ++#ifdef CONFIG_ETHERNET_ALBANY ++ //uRegVal = MHal_EMAC_ReadReg8(REG_BANK_CHIPTOP, 0xdf); ++ //uRegVal &= 0xfe; ++ //MHal_EMAC_WritReg8(REG_BANK_CHIPTOP, 0xdf, uRegVal); ++#else ++ //0x101e_0f[2] ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_CHIPTOP, 0x1E); ++ uRegVal |= BIT2; ++ MHal_EMAC_WritReg8(REG_BANK_CHIPTOP, 0x1E, uRegVal); ++#endif ++ ++#ifdef HARDWARE_DISCONNECT_DELAY ++ /* ++ wriu -w 0x003162 0x112b // [14:12] slow_cnt_sel 001 42usx4 = 168us ++ // [9:0] dsp_cnt_sel ++ wriu -w 0x003160 0x06a4 // [11:9] slow_rst_sel 011 counter_hit 1334us x 6 ++ // [7:4] 1010 enable ++ // [3:0] 0000 rst_cnt_sel counter_hit ++ */ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x62, 0x2b); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x63, 0x11); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x60, 0xa4); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0x61, 0x06); ++#endif ++ ++} ++ ++void MHal_EMAC_Power_Off_Clk( struct device *dev ) ++{ ++ int num_parents, i; ++ struct clk **emac_clks; ++#ifdef CONFIG_ETHERNET_ALBANY ++ u8 uRegVal; ++#endif ++#if CONFIG_OF ++ num_parents = of_clk_get_parent_count(dev->of_node); ++ if(num_parents > 0) ++ { ++ emac_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(emac_clks == NULL) ++ { ++ printk( "[EMAC]kzalloc failed!\n" ); ++ return; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ emac_clks[i] = of_clk_get(dev->of_node, i); ++ if (IS_ERR(emac_clks[i])) ++ { ++ printk( "Fail to get EMAC clk!\n" ); ++ kfree(emac_clks); ++ return; ++ } ++ else ++ { ++ clk_disable_unprepare(emac_clks[i]); ++ } ++ } ++ kfree(emac_clks); ++ } ++#else ++ MHal_EMAC_WritReg8(REG_BANK_CLKGEN0, 0x84, 0x01); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x44, 0x01); ++ MHal_EMAC_WritReg8(REG_BANK_SCGPCTRL, 0x46, 0x01); ++#endif ++ ++ ++ ++#ifdef CONFIG_ETHERNET_ALBANY ++/* ++ wriu 0x003204 0x31 // Reset analog ++ ++ wait 100 ++ ++ wriu -w 0x0032fc 0x0102 // Power-off LDO ++ wriu 0x0033a1 0xa0 // Power-off SADC ++ wriu 0x0032cc 0x50 // Power-off ADCPL ++ wriu 0x0032bb 0xc4 // Power-off REF ++ wriu 0x00333a 0xf3 // Power-off TX ++ wriu 0x0033f1 0x3c // Power-off TX ++ ++ wriu 0x0033f3 0x0f // DAC off ++ ++ wriu 0x003204 0x11 // Release reset analog ++*/ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x04, 0x31); // Reset analog ++ mdelay(100); ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfc, 0x02); // Power-on LDO ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xfd, 0x01); ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xa1, 0xa0); // Power-off SADC ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xcc, 0x50); // Power-off ADCPL ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0xbb, 0xc4); // Power-off REF ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0x3a, 0xf3); // Power-off TX ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xf1, 0x3c); // Power-off TX ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY2, 0xf3, 0x0f); // DAC off ++ ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY1, 0x04, 0x11); // Release reset analog ++ ++ //turn off LED //16'0x0e_28[5:4]=01 ++ uRegVal = MHal_EMAC_ReadReg8(REG_BANK_PMSLEEP, 0x50); ++ uRegVal = (uRegVal&~0x30); ++ MHal_EMAC_WritReg8(REG_BANK_PMSLEEP, 0x50, uRegVal); ++ ++#endif ++} ++ ++void MHal_EMAC_Set_Reverse_LED(u32 xval) ++{ ++ u8 u8Reg; ++ ++ u8Reg = MHal_EMAC_ReadReg8( REG_BANK_ALBANY0, 0xf7 ); ++ if(xval==1) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, u8Reg|BIT7); ++ } ++ else if(xval==0) ++ { ++ MHal_EMAC_WritReg8(REG_BANK_ALBANY0, 0xf7, u8Reg&~BIT7); ++ } ++} ++u8 MHal_EMAC_Get_Reverse_LED(void) ++{ ++ return (MHal_EMAC_ReadReg8( REG_BANK_ALBANY0, 0xf7 )&BIT7)? 1:0; ++} ++ ++#if defined(NEW_TX_QUEUE_128) ++void MHal_EMAC_Set_TXQUEUE_INT_Level(u8 low, u8 high) ++{ ++ if(high >= low) ++ { ++ MHal_EMAC_WritReg32( REG_TXQUEUE_INT_LEVEL, low|(high<<8)); ++ } ++} ++void MHal_EMAC_enable_new_TXQUEUE(void) ++{ ++ u8 xval; ++ xval = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1); ++ xval = (xval&(~BIT7)) | BIT7; ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, REG_ETH_EMAC1_h24+1, xval); ++ ++ MHal_EMAC_WritReg8(REG_BANK_EMAC1, REG_ETH_EMAC1_h2F, NEW_TX_QUEUE_SIZE); ++ ++} ++u8 MHal_EMAC_get_TXQUEUE_Count(void) ++{ ++ /*patch:*/ ++ int i=0, ertry=0; ++ u8 read_val, xval; ++ ++ xval = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ do ++ { ++ read_val = MHal_EMAC_ReadReg8(REG_BANK_EMAC1, REG_ETH_EMAC1_h24) & 0x7F; ++ if(xval==read_val) ++ { ++ i++; ++ }else ++ { ++ i=0; ++ xval = read_val; ++ ertry++; ++ } ++ }while(i<2); ++ ++ return xval; ++} ++#endif +diff --git a/drivers/mstar/emac/hal/infinity3/mhal_emac.h b/drivers/mstar/emac/hal/infinity3/mhal_emac.h +new file mode 100644 +index 00000000..965edfd9 +--- /dev/null ++++ b/drivers/mstar/emac/hal/infinity3/mhal_emac.h +@@ -0,0 +1,458 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ( "MStar Confidential Information" ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file EMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief EMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h define start ++// ----------------------------------------------------------------------------- ++#ifndef __DRV_EMAC__ ++#define __DRV_EMAC__ ++ ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++//#include ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define SOFTWARE_DESCRIPTOR ++#define RX_CHECKSUM ++#define CHIP_FLUSH_READ ++//#define LAN_ESD_CARRIER_INTERRUPT ++//#define SOFTWARE_TX_FLOW_CONTROL ++//#define HARDWARE_DISCONNECT_DELAY ++ ++/*** RX Configuration ***/ ++#define INT_JULIAN_D ++//#define ISR_BOTTOM_HALF ++#define MSTAR_EMAC_NAPI ++#define RX_ZERO_COPY ++ ++/*** TX Configuration ***/ ++#define TX_QUEUE_4 ++//#define TX_SOFTWARE_QUEUE ++#define TX_SKB_PTR ++//#define TX_SW_QUEUE ++//#define NEW_TX_QUEUE_128 //I3E new ++//#define NEW_TX_QUEUE_INTERRUPT_THRESHOLD //I3E new ++ ++ ++#if defined (TX_QUEUE_4) ++#if defined(NEW_TX_QUEUE_128) ++#define NEW_TX_QUEUE_SIZE (127) //max is 0xffffff ++#define TX_RING_SIZE (NEW_TX_QUEUE_SIZE+4) ++#else ++#define TX_RING_SIZE (4) //effected size = TX_RING_SIZE - 1 ++#endif ++#else ++#define TX_RING_SIZE (2) //effected size = TX_RING_SIZE - 1 ++#endif ++ ++#ifdef TX_SW_QUEUE ++#define TX_SW_QUEUE_SIZE (256) //effected size = TX_RING_SIZE - 1 ++#define TX_DESC_CLEARED 0 ++#define TX_DESC_WROTE 1 ++#define TX_DESC_READ 2 ++#define TX_FIFO_SIZE TX_RING_SIZE //HW FIFO size ++#endif ++ ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++#define EMAC_INT_MASK (0x07000dff) ++#else ++#define EMAC_INT_MASK (0x00000dff) ++#endif ++ ++ ++// Compiler Switches ++#define REG_BIT_MAP ++#define URANUS_ETHER_ADDR_CONFIGURABLE /* MAC address can be changed? */ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#define TRUE 1 ++#define FALSE 0 ++ ++#define REG_BANK_EFUSE 0x0020 ++#define REG_BANK_CLKGEN0 0x1038 ++#define REG_BANK_SCGPCTRL 0x1133 ++#define REG_BANK_CHIPTOP 0x101E ++#define REG_BANK_EMAC0 0x1510 //0x1020 ++#define REG_BANK_EMAC1 0x1511 //0x1021 ++#define REG_BACK_EMAC2 0x1512 //0x1022 ++#define REG_BANK_EMAC3 0x1513 //0x1023 ++#define REG_BANK_X32_EMAC0 0x1A1E ++#define REG_BANK_X32_EMAC2 0x1A1F ++#define REG_BANK_X32_EMAC3 0x1A20 ++#define REG_BANK_ALBANY0 0x0031 ++#define REG_BANK_ALBANY1 0x0032 ++#define REG_BANK_ALBANY2 0x0033 ++#define REG_BANK_PMSLEEP 0x000E ++ ++ ++#define SOFTWARE_DESCRIPTOR_ENABLE 0x0001 ++#define CHECKSUM_ENABLE 0x0FE ++#define RX_CHECKSUM_ENABLE 0x000E ++#define CONFIG_EMAC_MOA 1 // System Type ++#define EMAC_SPEED_10 10 ++#define EMAC_SPEED_100 100 ++ ++#define EMAC_ALLFF 0xFFFFFFFF ++#define EMAC_ABSO_MEM_BASE 0xA0000000//EMAC_ABSO_MEM_BASE 0xA0000000 ++#define INTERNEL_PHY_REG_BASE (EMAC_RIU_REG_BASE+REG_BANK_ALBANY0*0x200)//0xFD243000 ++#define EMAC_RIU_REG_BASE 0xFD000000 ++#define EMAC_ABSO_PHY_BASE 0x80000000//EMAC_ABSO_MEM_BASE ++#define EMAC_ABSO_MEM_SIZE 0x30000//0x16000//0x180000//0x16000//(48 * 1024) // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_MEM_SIZE_SQU 4 // More than: (32 + 16(0x3FFF)) KB ++#define EMAC_BUFFER_MEM_SIZE 0x0004000 ++#define EMAC_MAX_TX_QUEUE 1000 ++ ++// Base address here: ++#define MIU0_BUS_BASE 0x20000000 ++#define REG_EMAC0_ADDR_BASE (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200)//0xFD204000 // The register address base. Depends on system define. ++#define RBQP_LENG 0x0100 // 0x40// // ==?descriptors ++#define MAX_RX_DESCR RBQP_LENG//32 /* max number of receive buffers */ ++#define SOFTWARE_DESC_LEN 0x600 ++#ifdef SOFTWARE_DESCRIPTOR ++#define RX_BUFFER_SEL 0x0001 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (RBQP_LENG*SOFTWARE_DESC_LEN) //0x10000//0x20000// ++#else ++#define RX_BUFFER_SEL 0x0003 // 0x0=2KB,0x1=4KB,0x2=8KB,0x3=16KB, 0x09=1MB ++#define RX_BUFFER_SIZE (0x2000< ( HZ / 1000 ) ++#define InputRNGJiffThreshold (10 * ( HZ / 1000 )) ++#define RIU_MAP 0xFD200000 ++#define RIU ((unsigned short volatile *) RIU_MAP) ++#define REG_MIPS_BASE (0x1D00) ++#define MIPS_REG(addr) RIU[(addr<<1)+REG_MIPS_BASE] ++#define REG_RNG_OUT 0x0e ++ ++#endif +diff --git a/drivers/mstar/emac/mdrv_emac.c b/drivers/mstar/emac/mdrv_emac.c +new file mode 100644 +index 00000000..54f5e451 +--- /dev/null ++++ b/drivers/mstar/emac/mdrv_emac.c +@@ -0,0 +1,4112 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file devEMAC.c ++/// @brief EMAC Driver ++/// @author MStar Semiconductor Inc. ++/// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++///////////////////////////////////////////////////// ++// sync 2015.9.25 ++// CL1408633 //THEALE/RedLion/mstar2/drv/emac/ ++// CL1317815 //THEALE/RedLion/mstar2/hal/clippers/emac/ ++// sync 2015.12.7 ++// CL1426052 //THEALE/RedLion/mstar2/drv/emac/ ++///////////////////////////////////////////////////// ++ ++#define CONFIG_EMAC_PHY_RESTART_AN 1 ++//------------------------------------------------------------------------------------------------- ++// Include files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(CONFIG_MIPS) ++#include ++#include "mhal_chiptop_reg.h" ++#elif defined(CONFIG_ARM) ++#include ++#include ++#endif ++ ++#include "mdrv_types.h" ++//#include "mst_platform.h" ++//#include "mdrv_system.h" ++//#include "chip_int.h" ++#include "mhal_emac.h" ++#include "mdrv_emac.h" ++#include "ms_platform.h" ++#include "registers.h" ++ ++#ifdef CONFIG_EMAC_SUPPLY_RNG ++#include ++#include ++#include "mhal_rng_reg.h" ++#endif ++ ++#include "mdrv_msys_io_st.h" ++#include ++#include ++#include ++#include "ms_msys.h" ++#include "gpio.h" ++ ++ ++int g_emac_led_orange = -1; ++int g_emac_led_green = -1; ++int g_emac_led_count = 0; ++int g_emac_led_flick_speed = 30; ++ ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); ++ ++int msys_request_dmem(MSYS_DMEM_INFO *mem_info); ++int msys_release_dmem(MSYS_DMEM_INFO *mem_info); ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++#define EMAC_RX_TMR (0) ++#define EMAC_LINK_TMR (1) ++#define EMAC_FLOW_CTL_TMR (2) ++ ++#define EMAC_CHECK_LINK_TIME (HZ) ++u32 gu32CheckLinkTime = HZ; ++u32 gu32CheckLinkTimeDis = 100; ++u32 gu32intrEnable; ++ ++ ++ ++#ifdef TX_SOFTWARE_QUEUE ++ #define EMAC_CHECK_CNT (10) ++#else ++ #define EMAC_CHECK_CNT (500000) ++#endif ++ ++#define EMAC_TX_PTK_BASE (TX_SKB_BASE + RAM_VA_PA_OFFSET) ++ ++#define ALBANY_OUI_MSB (0) ++#define RTL_8210 (0x1CUL) ++ ++#define RX_THROUGHPUT_TEST 0 ++#define TX_THROUGHPUT_TEST 0 ++#define PACKET_THRESHOLD 260 ++#define TXCOUNT_THRESHOLD 10 ++ ++#define TX_SW_QUEUE_IN_GENERAL_TX 0 ++#define TX_SW_QUEUE_IN_IRQ 1 ++#define TX_SW_QUEUE_IN_TIMER 2 ++ ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++#define MAC_CONTROL_TYPE 0x8808 ++#define MAC_CONTROL_OPCODE 0x0001 ++#define PAUSE_QUANTA_TIME_10M ((1000000*10)/500) ++#define PAUSE_QUANTA_TIME_100M ((1000000*100)/500) ++#define PAUSE_TIME_DIVISOR_10M (PAUSE_QUANTA_TIME_10M/HZ) ++#define PAUSE_TIME_DIVISOR_100M (PAUSE_QUANTA_TIME_100M/HZ) ++unsigned char g_emac_speed = 0; ++static unsigned int eth_pause_cmd_enable=0; ++spinlock_t emac_flow_ctl_lock; ++static struct timer_list EMAC_flow_ctl_timer; ++#endif ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//-------------------------------------------------------------------------------------------------- ++u32 contiROVR = 0; ++u32 initstate= 0; ++u8 txidx =0; ++u32 txcount = 0; ++spinlock_t emac_lock; ++ ++#ifdef RX_ZERO_COPY ++struct sk_buff *rx_skb[MAX_RX_DESCR]; ++u32 rx_abso_addr[MAX_RX_DESCR]; ++//struct sk_buff * rx_skb_dummy; ++//u32 rx_abso_addr_dummy; ++#endif ++ ++// 0x78c9: link is down. ++static u32 phy_status_register = 0x78c9UL; ++ ++struct sk_buff *pseudo_packet; ++ ++unsigned char phyaddr = 0; ++#if TX_THROUGHPUT_TEST ++unsigned char packet_content[] = { ++0xa4, 0xba, 0xdb, 0x95, 0x25, 0x29, 0x00, 0x30, 0x1b, 0xba, 0x02, 0xdb, 0x08, 0x00, 0x45, 0x00, ++0x05, 0xda, 0x69, 0x0a, 0x40, 0x00, 0x40, 0x11, 0xbe, 0x94, 0xac, 0x10, 0x5a, 0xe3, 0xac, 0x10, ++0x5a, 0x70, 0x92, 0x7f, 0x13, 0x89, 0x05, 0xc6, 0x0c, 0x5b, 0x00, 0x00, 0x03, 0x73, 0x00, 0x00, ++0x00, 0x65, 0x00, 0x06, 0xe1, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, ++0x13, 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0xff, 0xff, 0xfc, 0x18, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, ++0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, ++0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, ++0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, ++0x36, 0x37, 0x38, 0x39, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x31, ++0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39 ++}; ++#endif ++ ++static unsigned int max_rx_packet_count=0; ++static unsigned int max_tx_packet_count=0; ++static unsigned int min_tx_fifo_idle_count=0xffff; ++static unsigned int tx_bytes_per_timerbak=0; ++static unsigned int tx_bytes_per_timer=0; ++u32 RAM_ALLOC_SIZE=0; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct timer_list EMAC_timer, Link_timer; ++#if RX_THROUGHPUT_TEST ++static struct timer_list RX_timer; ++#endif ++static struct net_device *emac_dev; ++//------------------------------------------------------------------------------------------------- ++// EMAC Function ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_tx (struct sk_buff *skb, struct net_device *dev); ++static void MDev_EMAC_timer_callback( unsigned long value ); ++static int MDev_EMAC_SwReset(struct net_device *dev); ++#ifndef TX_SKB_PTR ++static void MDev_EMAC_Send_PausePkt(struct net_device* dev); ++#endif ++#ifdef RX_ZERO_COPY ++//static int fill_rx_ring(struct net_device *netdev); ++//static int dequeue_rx_buffer(struct EMAC_private *p, struct sk_buff **pskb); ++static void free_rx_skb(void) ++{ ++ int i = 0; ++ ++ for (i = 0; i < MAX_RX_DESCR; i ++) ++ { ++ if (rx_skb[i]) ++ kfree_skb(rx_skb[i]); ++ ++ } ++ ++} ++#endif ++ ++ ++#ifdef TX_SW_QUEUE ++static void _MDev_EMAC_tx_reset_TX_SW_QUEUE(struct net_device* netdev); ++#endif ++ ++unsigned long oldTime; ++unsigned long PreLinkStatus; ++#ifdef MSTAR_EMAC_NAPI ++static void MDEV_EMAC_ENABLE_RX_REG(void); ++static void MDEV_EMAC_DISABLE_RX_REG(void); ++static int MDev_EMAC_napi_poll(struct napi_struct *napi, int budget); ++#endif ++ ++#ifdef CONFIG_MSTAR_EEE ++static int MDev_EMAC_IS_TX_IDLE(void); ++#endif //CONFIG_MSTAR_EEE ++ ++ ++//!!!! PACKET_DUMP has not been tested as they are not used. 2016/07/18 ++#if defined(PACKET_DUMP) ++extern struct file* msys_kfile_open(const char* path, int flags, int rights); ++extern void msys_kfile_close(struct file* fp); ++extern int msys_kfile_write(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size); ++ ++static int txDumpCtrl=0; ++static int rxDumpCtrl=0; ++static int txDumpFileLength=0; ++static int rxDumpFileLength=0; ++static char txDumpFileName[32]={0}; ++static char rxDumpFileName[32]={0}; ++static struct file* txDumpFile=NULL; ++static struct file* rxDumpFile=NULL; ++ ++static ssize_t tx_dump_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ txDumpCtrl = simple_strtoul(buf, NULL, 10); ++ if(1==txDumpCtrl) ++ { ++ strcpy(txDumpFileName,"/tmp/emac/tx_dump"); ++ txDumpFile=msys_kfile_open(rxDumpFileName, O_RDWR | O_CREAT, 0644); ++ if(NULL!=txDumpFile) ++ { ++ txDumpFileLength=0; ++ printk(KERN_WARNING"success to open emac tx_dump file, '%s'...\n",txDumpFileName); ++ } ++ else ++ { ++ printk(KERN_WARNING"failed to open emac tx_dump file, '%s'!!\n",txDumpFileName); ++ } ++ } ++ else if(0==txDumpCtrl && txDumpFile!=NULL) ++ { ++ ++ msys_kfile_close(txDumpFile); ++ txDumpFile=NULL; ++ } ++ return count; ++} ++static ssize_t tx_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", txDumpCtrl); ++} ++DEVICE_ATTR(tx_dump, 0644, tx_dump_show, tx_dump_store); ++ ++static ssize_t rx_dump_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ rxDumpCtrl = simple_strtoul(buf, NULL, 10); ++ if(1==rxDumpCtrl) ++ { ++ strcpy(rxDumpFileName,"/tmp/emac/rx_dump"); ++ rxDumpFile=msys_kfile_open(rxDumpFileName, O_RDWR | O_CREAT, 0644); ++ if(NULL!=rxDumpFile) ++ { ++ rxDumpFileLength=0; ++ printk(KERN_WARNING"success to open emac rx_dump file, '%s'...\n",rxDumpFileName); ++ } ++ else ++ { ++ printk(KERN_WARNING"failed to open emac rx_dump file, '%s'!!\n",rxDumpFileName); ++ } ++ } ++ else if(0==rxDumpCtrl) ++ { ++ if(rxDumpFile!=NULL) ++ { ++ msys_kfile_close(rxDumpFile); ++ rxDumpFile=NULL; ++ } ++ } ++ return count; ++} ++static ssize_t rx_dump_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", rxDumpCtrl); ++} ++DEVICE_ATTR(rx_dump, 0644, rx_dump_show, rx_dump_store); ++#endif ++ ++static unsigned long getCurMs(void) ++{ ++ struct timeval tv; ++ unsigned long curMs; ++ ++ do_gettimeofday(&tv); ++ curMs = tv.tv_usec/1000; ++ curMs += tv.tv_sec * 1000; ++ return curMs; ++} ++ ++#if RX_THROUGHPUT_TEST ++int receive_bytes = 0; ++static void RX_timer_callback( unsigned long value){ ++ int get_bytes = receive_bytes; ++ int cur_speed; ++ receive_bytes = 0; ++ ++ cur_speed = get_bytes*8/20/1024; ++ printk(" %dkbps",cur_speed); ++ RX_timer.expires = jiffies + 20*EMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// PHY MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Access the PHY to determine the current Link speed and Mode, and update the ++// MAC accordingly. ++// If no link or auto-negotiation is busy, then no changes are made. ++// Returns: 0 : OK ++// -1 : No link ++// -2 : AutoNegotiation still in progress ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_update_linkspeed (struct net_device *dev) ++{ ++ u32 bmsr, bmcr, adv, lpa, neg; ++ u32 speed, duplex; ++ ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ u32 hcd_link_st_ok, an_100t_link_st = 0; ++ static unsigned int phy_restart_cnt = 0; ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ #ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE(); ++ ++ if (PreLinkStatus == 1) ++ { ++ MHal_EMAC_Reset_EEE(); ++ } ++ #endif ++ ++ PreLinkStatus = 0; ++ ++ return -1; //no link // ++ } ++ ++ MHal_EMAC_read_phy (phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ //EMAC_DBG("==> AutoNegotiation still in progress\n"); ++ return -2; ++ } ++ ++ /* Get Link partner and advertisement from the PHY not from the MAC */ ++ MHal_EMAC_read_phy(phyaddr, MII_ADVERTISE, &adv); ++ MHal_EMAC_read_phy(phyaddr, MII_LPA, &lpa); ++ ++ /* For Link Parterner adopts force mode and EPHY used, ++ * EPHY LPA reveals all zero value. ++ * EPHY would be forced to Full-Duplex mode. ++ */ ++ if (!lpa) ++ { ++ /* 100Mbps Full-Duplex */ ++ if (bmcr & BMCR_SPEED100) ++ lpa |= LPA_100FULL; ++ else /* 10Mbps Full-Duplex */ ++ lpa |= LPA_10FULL; ++ } ++ ++ neg = adv & lpa; ++ ++ if (neg & LPA_100FULL) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_100HALF) ++ { ++ speed = SPEED_100; ++ duplex = DUPLEX_HALF; ++ } ++ else if (neg & LPA_10FULL) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_FULL; ++ } ++ else if (neg & LPA_10HALF) ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ } ++ else ++ { ++ speed = SPEED_10; ++ duplex = DUPLEX_HALF; ++ EMAC_DBG("%s: No speed and mode found (LPA=0x%x, ADV=0x%x)\n", __FUNCTION__, lpa, adv); ++ } ++ ++ } ++ else ++ { ++ speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10; ++ duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF; ++ } ++ ++ // Update the MAC // ++ MHal_EMAC_update_speed_duplex(speed,duplex); ++ ++ ++#ifdef CONFIG_MSTAR_EEE ++ /*TX idle, enable EEE*/ ++ if((MDev_EMAC_IS_TX_IDLE()) && (speed == SPEED_100) && (duplex == DUPLEX_FULL)) ++ { ++ if (PreLinkStatus == 0) ++ { ++ MHal_EMAC_Enable_EEE(300); ++ } ++ else ++ { ++ MHal_EMAC_Enable_EEE(0); ++ } ++ } ++#endif ++ ++ PreLinkStatus = 1; ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ if (speed == SPEED_100) { ++ MHal_EMAC_read_phy(phyaddr, 0x21, &hcd_link_st_ok); ++ MHal_EMAC_read_phy(phyaddr, 0x22, &an_100t_link_st); ++ if (((hcd_link_st_ok & 0x100) && !(an_100t_link_st & 0x300)) || (!(hcd_link_st_ok & 0x100) && ((an_100t_link_st & 0x300) == 0x200))) { ++ phy_restart_cnt++; ++ if (phy_restart_cnt > 10) { ++ EMAC_DBG("MDev_EMAC_update_linkspeed: restart AN process\n"); ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1200UL); ++ phy_restart_cnt = 0; ++ } ++ } else { ++ phy_restart_cnt = 0; ++ } ++ } ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++ return 0; ++} ++ ++static int MDev_EMAC_get_info(struct net_device *dev) ++{ ++ u32 bmsr, bmcr, LocPtrA; ++ u32 uRegStatus =0; ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ if (!(bmsr & BMSR_LSTATUS)){ ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_NO_LINK; //no link // ++ } ++ MHal_EMAC_read_phy (phyaddr, MII_BMCR, &bmcr); ++ ++ if (bmcr & BMCR_ANENABLE) ++ { ++ //AutoNegotiation is enabled // ++ if (!(bmsr & BMSR_ANEGCOMPLETE)) ++ { ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_AUTO_NEGOTIATION; //AutoNegotiation // ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_RESET_STATE; ++ uRegStatus |= ETHERNET_TEST_LINK_SUCCESS; //link success // ++ } ++ ++ MHal_EMAC_read_phy (phyaddr, MII_LPA, &LocPtrA); ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_100HALF)) ++ { ++ uRegStatus |= ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if ((LocPtrA & LPA_100FULL) || (LocPtrA & LPA_10FULL)) ++ { ++ uRegStatus |= ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ else ++ { ++ if(bmcr & BMCR_SPEED100) ++ { ++ uRegStatus |= ETHERNET_TEST_SPEED_100M; //SPEED_100// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_SPEED_100M; //SPEED_10// ++ } ++ ++ if(bmcr & BMCR_FULLDPLX) ++ { ++ uRegStatus |= ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_FULL// ++ } ++ else ++ { ++ uRegStatus &= ~ETHERNET_TEST_DUPLEX_FULL; //DUPLEX_HALF// ++ } ++ } ++ ++ return uRegStatus; ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Program the hardware MAC address from dev->dev_addr. ++//------------------------------------------------------------------------------------------------- ++void MDev_EMAC_update_mac_address (struct net_device *dev) ++{ ++ u32 value; ++ value = (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) |(dev->dev_addr[0]); ++ MHal_EMAC_Write_SA1L(value); ++ value = (dev->dev_addr[5] << 8) | (dev->dev_addr[4]); ++ MHal_EMAC_Write_SA1H(value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// ADDRESS MANAGEMENT ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Set the ethernet MAC address in dev->dev_addr ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_get_mac_address (struct net_device *dev) ++{ ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_EMAC_get_SA1H_addr(); ++ LoAddr = MHal_EMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_EMAC_get_SA2H_addr(); ++ LoAddr = MHal_EMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (dev->dev_addr, &addr, 6); ++ return; ++ } ++} ++ ++#ifdef URANUS_ETHER_ADDR_CONFIGURABLE ++//------------------------------------------------------------------------------------------------- ++// Store the new hardware address in dev->dev_addr, and update the MAC. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_set_mac_address (struct net_device *dev, void *addr) ++{ ++ struct sockaddr *address = addr; ++ if (!is_valid_ether_addr (address->sa_data)) ++ return -EADDRNOTAVAIL; ++ ++ memcpy (dev->dev_addr, address->sa_data, dev->addr_len); ++ MDev_EMAC_update_mac_address (dev); ++ return 0; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Mstar Multicast hash rule ++//------------------------------------------------------------------------------------------------- ++//Hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] ++//Hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] ++//Hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] ++//Hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] ++//Hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] ++//Hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] ++//------------------------------------------------------------------------------------------------- ++ ++static void MDev_EMAC_sethashtable(unsigned char *addr) ++{ ++ u32 mc_filter[2]; ++ u32 uHashIdxBit; ++ u32 uHashValue; ++ u32 i; ++ u32 tmpcrc; ++ u32 uSubIdx; ++ u64 macaddr; ++ u64 mac[6]; ++ ++ uHashValue = 0; ++ macaddr = 0; ++ ++ // Restore mac // ++ for(i = 0; i < 6; i++) ++ { ++ mac[i] =(u64)addr[i]; ++ } ++ ++ // Truncate mac to u64 container // ++ macaddr |= mac[0] | (mac[1] << 8) | (mac[2] << 16); ++ macaddr |= (mac[3] << 24) | (mac[4] << 32) | (mac[5] << 40); ++ ++ // Caculate the hash value // ++ for(uHashIdxBit = 0; uHashIdxBit < 6; uHashIdxBit++) ++ { ++ tmpcrc = (macaddr & (0x1UL << uHashIdxBit)) >> uHashIdxBit; ++ for(i = 1; i < 8; i++) ++ { ++ uSubIdx = uHashIdxBit + (i * 6); ++ tmpcrc = tmpcrc ^ ((macaddr >> uSubIdx) & 0x1); ++ } ++ uHashValue |= (tmpcrc << uHashIdxBit); ++ } ++ ++ mc_filter[0] = MHal_EMAC_ReadReg32( REG_ETH_HSL); ++ mc_filter[1] = MHal_EMAC_ReadReg32( REG_ETH_HSH); ++ ++ // Set the corrsponding bit according to the hash value // ++ if(uHashValue < 32) ++ { ++ mc_filter[0] |= (0x1UL << uHashValue); ++ MHal_EMAC_WritReg32( REG_ETH_HSL, mc_filter[0] ); ++ } ++ else ++ { ++ mc_filter[1] |= (0x1UL << (uHashValue - 32)); ++ MHal_EMAC_WritReg32( REG_ETH_HSH, mc_filter[1] ); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++//Enable/Disable promiscuous and multicast modes. ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_set_rx_mode (struct net_device *dev) ++{ ++ u32 uRegVal; ++ struct netdev_hw_addr *ha; ++ ++ uRegVal = MHal_EMAC_Read_CFG(); ++ ++ if (dev->flags & IFF_PROMISC) ++ { ++ // Enable promiscuous mode // ++ uRegVal |= EMAC_CAF; ++ } ++ else if (dev->flags & (~IFF_PROMISC)) ++ { ++ // Disable promiscuous mode // ++ uRegVal &= ~EMAC_CAF; ++ } ++ MHal_EMAC_Write_CFG(uRegVal); ++ ++ if (dev->flags & IFF_ALLMULTI) ++ { ++ // Enable all multicast mode // ++ MHal_EMAC_update_HSH(-1,-1); ++ uRegVal |= EMAC_MTI; ++ } ++ else if (dev->flags & IFF_MULTICAST) ++ { ++ // Enable specific multicasts// ++ MHal_EMAC_update_HSH(0,0); ++ netdev_for_each_mc_addr(ha, dev) ++ { ++ MDev_EMAC_sethashtable(ha->addr); ++ } ++ uRegVal |= EMAC_MTI; ++ } ++ else if (dev->flags & ~(IFF_ALLMULTI | IFF_MULTICAST)) ++ { ++ // Disable all multicast mode// ++ MHal_EMAC_update_HSH(0,0); ++ uRegVal &= ~EMAC_MTI; ++ } ++ ++ MHal_EMAC_Write_CFG(uRegVal); ++} ++//------------------------------------------------------------------------------------------------- ++// IOCTL ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable MDIO ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_mdio_read (struct net_device *dev, int phy_id, int location) ++{ ++ u32 value; ++ MHal_EMAC_read_phy (phy_id, location, &value); ++ return value; ++} ++ ++static void MDev_EMAC_mdio_write (struct net_device *dev, int phy_id, int location, int value) ++{ ++ MHal_EMAC_write_phy (phy_id, location, value); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//ethtool support. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_ethtool_ioctl (struct net_device *dev, void *useraddr) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ u32 ethcmd; ++ int res = 0; ++ ++ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd))) ++ return -EFAULT; ++ ++ spin_lock_irq (LocPtr->lock); ++ ++ switch (ethcmd) ++ { ++ case ETHTOOL_GSET: ++ { ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ res = mii_ethtool_gset (&LocPtr->mii, &ecmd); ++ if (copy_to_user (useraddr, &ecmd, sizeof (ecmd))) ++ res = -EFAULT; ++ break; ++ } ++ case ETHTOOL_SSET: ++ { ++ struct ethtool_cmd ecmd; ++ if (copy_from_user (&ecmd, useraddr, sizeof (ecmd))) ++ res = -EFAULT; ++ else ++ res = mii_ethtool_sset (&LocPtr->mii, &ecmd); ++ break; ++ } ++ case ETHTOOL_NWAY_RST: ++ { ++ res = mii_nway_restart (&LocPtr->mii); ++ break; ++ } ++ case ETHTOOL_GLINK: ++ { ++ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ edata.data = mii_link_ok (&LocPtr->mii); ++ if (copy_to_user (useraddr, &edata, sizeof (edata))) ++ res = -EFAULT; ++ break; ++ } ++ default: ++ res = -EOPNOTSUPP; ++ } ++ spin_unlock_irq (LocPtr->lock); ++ return res; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// User-space ioctl interface. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_ioctl (struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ struct mii_ioctl_data *data = if_mii(rq); ++ u32 value; ++ if (!netif_running(dev)) ++ { ++ rq->ifr_metric = ETHERNET_TEST_INIT_FAIL; ++ } ++ ++ switch (cmd) ++ { ++ case SIOCGMIIPHY: ++ data->phy_id = (phyaddr & 0x1FUL); ++ return 0; ++ ++ case SIOCDEVPRIVATE: ++ rq->ifr_metric = (MDev_EMAC_get_info(emac_dev)|initstate); ++ return 0; ++/* ++ case SIOCDEVON: ++ MHal_EMAC_Power_On_Clk(); ++ return 0; ++ ++ case SIOCDEVOFF: ++ MHal_EMAC_Power_Off_Clk(); ++ return 0; ++*/ ++ case SIOCGMIIREG: ++ // check PHY's register 1. ++ if((data->reg_num & 0x1fUL) == 0x1UL) ++ { ++ // PHY's register 1 value is set by timer callback function. ++ spin_lock_irq(LocPtr->lock); ++ data->val_out = phy_status_register; ++ spin_unlock_irq(LocPtr->lock); ++ } ++ else ++ { ++ MHal_EMAC_read_phy((phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), (u32 *)&(value)); ++ data->val_out = value; ++ } ++ return 0; ++ ++ case SIOCSMIIREG: ++ if (!capable(CAP_NET_ADMIN)) ++ return -EPERM; ++ MHal_EMAC_write_phy((phyaddr & 0x1FUL), (data->reg_num & 0x1fUL), data->val_in); ++ return 0; ++ ++ case SIOCETHTOOL: ++ return MDev_EMAC_ethtool_ioctl (dev, (void *) rq->ifr_data); ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// MAC ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++//Initialize and start the Receiver and Transmit subsystems ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_start (struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ struct recv_desc_bufs *dlist; ++#ifdef SOFTWARE_DESCRIPTOR ++ int i; ++#endif ++ u32 uRegVal; ++ dlist = LocPtr->dlist; ++ ++#ifdef SOFTWARE_DESCRIPTOR ++ for(i = 0; i < MAX_RX_DESCR; i++) ++ { ++ dlist->descriptors[i].addr &= ~EMAC_DESC_DONE; ++ dlist->descriptors[i].size = 0; ++ //// Set the Wrap bit on the last descriptor // ++ // if(i ==(MAX_RX_DESCR - 1)) ++ // dlist->descriptors[MAX_RX_DESCR - 1].addr |= EMAC_DESC_WRAP; ++ } ++ // Program address of descriptor list in Rx Buffer Queue register // ++ uRegVal = ((EMAC_REG) & dlist->descriptors)- RAM_VA_PA_OFFSET - MIU0_BUS_BASE; ++ MHal_EMAC_Write_RBQP(uRegVal); ++#else ++ // set offset of read and write pointers in the receive circular buffer // ++ uRegVal = MHal_EMAC_Read_BUFF(); ++ uRegVal = (RX_BUFFER_BASE|RX_BUFFER_SEL) - MIU0_BUS_BASE; ++ MHal_EMAC_Write_BUFF(uRegVal); ++ MHal_EMAC_Write_RDPTR(0); ++ MHal_EMAC_Write_WRPTR(0); ++#endif ++ ++ //Reset buffer index// ++ LocPtr->rxBuffIndex = 0; ++ ++ // Enable Receive and Transmit // ++ uRegVal = MHal_EMAC_Read_CTL(); ++ uRegVal |= (EMAC_RE | EMAC_TE); ++ MHal_EMAC_Write_CTL(uRegVal); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Open the ethernet interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_open (struct net_device *dev) ++{ ++ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ u32 uRegVal; ++ unsigned long flags; ++ int ret; ++#ifdef MSTAR_EMAC_NAPI ++ napi_enable(&LocPtr->napi); ++#endif ++ ++ spin_lock_irqsave (LocPtr->lock,flags); ++ ret = MDev_EMAC_update_linkspeed(dev); ++ spin_unlock_irqrestore (LocPtr->lock,flags); ++ ++ if (!is_valid_ether_addr (dev->dev_addr)) ++ return -EADDRNOTAVAIL; ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(dev); ++#endif ++ //ato EMAC_SYS->PMC_PCER = 1 << EMAC_ID_EMAC; //Re-enable Peripheral clock // ++ //MHal_EMAC_Power_On_Clk(dev->dev); ++ uRegVal = MHal_EMAC_Read_CTL(); ++ uRegVal |= EMAC_CSR; ++ MHal_EMAC_Write_CTL(uRegVal); ++ // Enable PHY interrupt // ++ MHal_EMAC_enable_phyirq (); ++ ++ // Enable MAC interrupts // ++ MHal_EMAC_Write_IDR(0xFFFFFFFF); //clear interrupt maybe it was set in uboot ++ gu32intrEnable = EMAC_INT_RBNA|EMAC_INT_TUND|EMAC_INT_RTRY|EMAC_INT_ROVR|EMAC_INT_HRESP; ++#if defined(TX_SKB_PTR) ++ gu32intrEnable = gu32intrEnable | EMAC_INT_TCOM; ++#endif ++#if defined(INT_JULIAN_D) ++ // enable delay interrupt ++ uRegVal = MHal_EMAC_Read_JULIAN_0104(); ++ uRegVal |= 0x00000080UL; ++ MHal_EMAC_Write_JULIAN_0104(uRegVal); ++#else ++ gu32intrEnable = gu32intrEnable | EMAC_INT_RCOM; ++#endif ++ MHal_EMAC_Write_IER(gu32intrEnable); ++ ++ LocPtr->ep_flag |= EP_FLAG_OPEND; ++ ++ MDev_EMAC_start (dev); ++ netif_start_queue (dev); ++ ++ init_timer( &Link_timer ); ++ Link_timer.data = EMAC_LINK_TMR; ++ Link_timer.function = MDev_EMAC_timer_callback; ++ Link_timer.expires = jiffies + EMAC_CHECK_LINK_TIME; ++ add_timer(&Link_timer); ++ ++ /* check if network linked */ ++ if (-1 == ret) ++ { ++ netif_carrier_off(dev); ++ ThisBCE.connected = 0; ++ } ++ else if(0 == ret) ++ { ++ netif_carrier_on(dev); ++ ThisBCE.connected = 1; ++ } ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Close the interface ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_close (struct net_device *dev) ++{ ++ u32 uRegVal; ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++#ifdef MSTAR_EMAC_NAPI ++ napi_disable(&LocPtr->napi); ++#endif ++ ++ spin_lock_irq (LocPtr->lock); ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_EMAC_Read_CTL(); ++ uRegVal &= ~(EMAC_TE | EMAC_RE); ++ MHal_EMAC_Write_CTL(uRegVal); ++ // Disable PHY interrupt // ++ MHal_EMAC_disable_phyirq (); ++ ++ MHal_EMAC_Write_IDR(0xFFFFFFFF); ++#ifdef INT_JULIAN_D ++ ++#endif ++ netif_stop_queue (dev); ++ netif_carrier_off(dev); ++ del_timer(&Link_timer); ++ //MHal_EMAC_Power_Off_Clk(dev->dev); ++ ThisBCE.connected = 0; ++ LocPtr->ep_flag &= (~EP_FLAG_OPEND); ++ ++#if defined(TX_SKB_PTR) ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(dev); ++#else ++{ ++ int i; ++ for (i=0;itx_swq[i].used ==1 && LocPtr->tx_swq[i].skb != NULL) ++ { ++ dma_unmap_single(&dev->dev, LocPtr->tx_swq[i].skb_physaddr, ++ LocPtr->tx_swq[i].skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb_any(LocPtr->tx_swq[i].skb); ++ LocPtr->tx_swq[i].used = 0; ++ LocPtr->tx_swq[i].skb = NULL; ++ LocPtr->tx_swq[i].skb_physaddr = 0; ++ } ++ } ++} ++#endif ++#endif ++ spin_unlock_irq (LocPtr->lock); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Update the current statistics from the internal statistics registers. ++//------------------------------------------------------------------------------------------------- ++static struct net_device_stats * MDev_EMAC_stats (struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ int ale, lenerr, seqe, lcol, ecol; ++ ++ spin_lock_irq (LocPtr->lock); ++ ++ if (netif_running (dev)) ++ { ++ LocPtr->stats.rx_packets += MHal_EMAC_Read_OK(); /* Good frames received */ ++ ale = MHal_EMAC_Read_ALE(); ++ LocPtr->stats.rx_frame_errors += ale; /* Alignment errors */ ++ lenerr = MHal_EMAC_Read_ELR(); ++ LocPtr->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */ ++ seqe = MHal_EMAC_Read_SEQE(); ++ LocPtr->stats.rx_crc_errors += seqe; /* CRC error */ ++ LocPtr->stats.rx_fifo_errors += MHal_EMAC_Read_ROVR(); ++ LocPtr->stats.rx_errors += ale + lenerr + seqe + MHal_EMAC_Read_SE() + MHal_EMAC_Read_RJB(); ++ LocPtr->stats.tx_packets += MHal_EMAC_Read_FRA(); /* Frames successfully transmitted */ ++ LocPtr->stats.tx_fifo_errors += MHal_EMAC_Read_TUE(); /* Transmit FIFO underruns */ ++ LocPtr->stats.tx_carrier_errors += MHal_EMAC_Read_CSE(); /* Carrier Sense errors */ ++ LocPtr->stats.tx_heartbeat_errors += MHal_EMAC_Read_SQEE(); /* Heartbeat error */ ++ lcol = MHal_EMAC_Read_LCOL(); ++ ecol = MHal_EMAC_Read_ECOL(); ++ LocPtr->stats.tx_window_errors += lcol; /* Late collisions */ ++ LocPtr->stats.tx_aborted_errors += ecol; /* 16 collisions */ ++ LocPtr->stats.collisions += MHal_EMAC_Read_SCOL() + MHal_EMAC_Read_MCOL() + lcol + ecol; ++ } ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++ return &LocPtr->stats; ++} ++ ++static int MDev_EMAC_TxReset(void) ++{ ++ u32 val = MHal_EMAC_Read_CTL() & 0x000001FFUL; ++ MHal_EMAC_Write_CTL((val & ~EMAC_TE)); ++ ++ val = MHal_EMAC_Read_CTL() & 0x000001FFUL; ++ EMAC_ERR ("MAC0_CTL:0x%08x\n", val); ++ //MHal_EMAC_Write_TCR(0); ++ mdelay(1); ++ MHal_EMAC_Write_CTL((MHal_EMAC_Read_CTL() | EMAC_TE)); ++ val = MHal_EMAC_Read_CTL() & 0x000001FFUL; ++ EMAC_ERR ("MAC0_CTL:0x%08x\n", val); ++ return 0; ++} ++ ++#ifndef TX_SKB_PTR ++static int MDev_EMAC_CheckTSR(void) ++{ ++ u32 check; ++ u32 tsrval = 0; ++ ++ #ifdef TX_QUEUE_4 ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ for (check = 0; check < EMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_EMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ return NETDEV_TX_OK; ++ } ++ } ++ #else ++ for (check = 0; check < EMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_EMAC_Read_TSR(); ++ if ((tsrval & EMAC_IDLETSR) || (tsrval & EMAC_BNQ)) ++ return NETDEV_TX_OK; ++ } ++ #endif ++ ++#ifndef TX_SOFTWARE_QUEUE ++ EMAC_ERR("Err CheckTSR:0x%x\n", tsrval); ++ MDev_EMAC_TxReset(); ++#endif ++ ++ return NETDEV_TX_BUSY; ++} ++#endif ++ ++int MDev_EMAC_GetTXFIFOIdle(void) ++{ ++ u32 tsrval = 0; ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++ tsrval = MHal_EMAC_Read_TSR(); ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval > 4) ++ { ++ avlfifoval-=4; ++ } ++ else ++ { ++ avlfifoval= 0; ++ } ++ ++#if defined(NEW_TX_QUEUE_128) ++ avlfifoval = avlfifoval + (NEW_TX_QUEUE_SIZE - MHal_EMAC_get_TXQUEUE_Count()); ++#endif ++ return avlfifoval; ++} ++ ++#ifdef CONFIG_MSTAR_EEE ++static int MDev_EMAC_IS_TX_IDLE(void) ++{ ++ u32 check; ++ u32 tsrval = 0; ++ ++ u8 avlfifo[8] = {0}; ++ u8 avlfifoidx; ++ u8 avlfifoval = 0; ++ ++#ifdef TX_QUEUE_4 ++ for (check = 0; check < EMAC_CHECK_CNT; check++) ++ { ++ tsrval = MHal_EMAC_Read_TSR(); ++ ++ avlfifo[0] = ((tsrval & EMAC_IDLETSR) != 0)? 1 : 0; ++ avlfifo[1] = ((tsrval & EMAC_BNQ)!= 0)? 1 : 0; ++ avlfifo[2] = ((tsrval & EMAC_TBNQ) != 0)? 1 : 0; ++ avlfifo[3] = ((tsrval & EMAC_FBNQ) != 0)? 1 : 0; ++ avlfifo[4] = ((tsrval & EMAC_FIFO1IDLE) !=0)? 1 : 0; ++ avlfifo[5] = ((tsrval & EMAC_FIFO2IDLE) != 0)? 1 : 0; ++ avlfifo[6] = ((tsrval & EMAC_FIFO3IDLE) != 0)? 1 : 0; ++ avlfifo[7] = ((tsrval & EMAC_FIFO4IDLE) != 0)? 1 : 0; ++ ++ avlfifoval = 0; ++ ++ for(avlfifoidx = 0; avlfifoidx < 8; avlfifoidx++) ++ { ++ avlfifoval += avlfifo[avlfifoidx]; ++ } ++ ++ if (avlfifoval == 8) ++ return 1; ++ } ++#endif ++ ++ return 0; ++} ++#endif //CONFIG_MSTAR_EEE ++ ++ ++void MDrv_EMAC_DumpMem(phys_addr_t addr, u32 len) ++{ ++ u8 *ptr = (u8 *)addr; ++ u32 i; ++ ++ printk("\n ===== Dump %lx =====\n", (long unsigned int)ptr); ++ for (i=0; istats.tx_bytes += len; ++ ++ Chip_Flush_Cache_Range(skb_addr, len); // Chip_Flush_Memory(); ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_EMAC_Write_TAR(skb_addr - RAM_VA_PA_OFFSET - MIU0_BUS_BASE); ++ //printk("[EMAC]%d TODO:DMA buffer 0x%08x\n",__LINE__,skb_addr - RAM_VA_PA_OFFSET - MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_EMAC_Write_TCR(len); ++ ++ return NETDEV_TX_OK; ++} ++ ++static void MDev_EMAC_Send_PausePkt(struct net_device* dev) ++{ ++ u32 val = MHal_EMAC_Read_CTL() & 0x000001FFUL; ++ ++ //Disable Rx ++ MHal_EMAC_Write_CTL((val & ~EMAC_RE)); ++ memcpy(&pause_pkt[6], dev->dev_addr, 6); ++ MDev_EMAC_BGsend(dev, (phys_addr_t)pause_pkt, sizeof(pause_pkt)); ++ //Enable Rx ++ MHal_EMAC_Write_CTL((MHal_EMAC_Read_CTL() | EMAC_RE)); ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++//Patch for losing small-size packet when running SMARTBIT ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++static void MDev_EMAC_Period_Retry(struct sk_buff *skb, struct net_device* dev) ++{ ++ u32 xval; ++ u32 uRegVal; ++ ++ xval = MHal_EMAC_ReadReg32(REG_ETH_CFG); ++ ++ if((skb->len <= PACKET_THRESHOLD) && !(xval & EMAC_SPD) && !(xval & EMAC_FD)) ++ { ++ txcount++; ++ } ++ else ++ { ++ txcount = 0; ++ } ++ ++ if(txcount > TXCOUNT_THRESHOLD) ++ { ++ uRegVal = MHal_EMAC_Read_CFG(); ++ uRegVal |= 0x00001000UL; ++ MHal_EMAC_Write_CFG(uRegVal); ++ } ++ else ++ { ++ uRegVal = MHal_EMAC_Read_CFG(); ++ uRegVal &= ~(0x00001000UL); ++ MHal_EMAC_Write_CFG(uRegVal); ++ } ++} ++#endif ++ ++#ifdef TX_SOFTWARE_QUEUE ++int MDev_EMAC_enqueue(struct skb_node **queue_head, struct skb_node **queue_tail, struct sk_buff *skb) ++{ ++ struct skb_node *pskb_node = (struct skb_node *)kmalloc(sizeof(struct skb_node), GFP_ATOMIC); ++ ++ if(!pskb_node) ++ { ++ EMAC_ERR("*pskb_node kmalloc fail\n"); ++ BUG_ON(1); ++ return 1; ++ } ++ ++ /*Reset the content of pskb_node*/ ++ memset(pskb_node, 0x0, sizeof(struct skb_node)); ++ ++ pskb_node->skb = skb; ++ pskb_node->next = *queue_head; ++ pskb_node->prev = NULL; ++ ++ if(!(*queue_tail)) ++ { ++ (*queue_tail) = pskb_node; ++ } ++ ++ (*queue_tail)->queuesize = (*queue_tail)->queuesize + 1; ++ ++ if(!(*queue_head)) ++ { ++ (*queue_head) = pskb_node; ++ } ++ else ++ { ++ (*queue_head)->prev = pskb_node; ++ } ++ ++ (*queue_head) = pskb_node; ++ ++ return 0; ++} ++ ++struct sk_buff* MDev_EMAC_dequeue(struct skb_node **queue_head, struct skb_node **queue_tail) ++{ ++ struct sk_buff *skb; ++ ++ if(!(*queue_tail)) ++ { ++ return NULL; ++ } ++ else ++ { ++ skb = (*queue_tail)->skb; ++ ++ /* If the size of queue is equal to 1*/ ++ if(*queue_head == *queue_tail) ++ { ++ kfree(*queue_tail); ++ *queue_tail = NULL; ++ *queue_head = NULL; ++ } ++ else ++ { ++ (*queue_tail)->prev->queuesize = (*queue_tail)->queuesize - 1; ++ *queue_tail = (*queue_tail)->prev; ++ kfree((*queue_tail)->next); ++ (*queue_tail)->next = NULL; ++ } ++ } ++ ++ return skb; ++} ++ ++void MDev_EMAC_bottom_tx_task(struct work_struct *work) ++{ ++ struct sk_buff *skb; ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ struct EMAC_private *LocPtr = container_of(work, struct EMAC_private, tx_task); ++ struct net_device *dev = LocPtr->dev; ++ ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ ++ while(NETDEV_TX_OK == MDev_EMAC_CheckTSR()) ++ { ++ skb = MDev_EMAC_dequeue(&(LocPtr->tx_queue_head), &(LocPtr->tx_queue_tail)); ++ ++ if(skb == NULL) ++ { ++ break; ++ } ++ else ++ { ++ ++ skb_addr = get_tx_addr(); ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ ++ #ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++ MDev_EMAC_Period_Retry(skb, dev); ++ #endif ++ LocPtr->stats.tx_bytes += skb->len; ++ ++ Chip_Flush_Cache_Range(skb_addr, skb->len); //Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ ++ //MDrv_EMAC_DumpMem(tx_swq->skb_physaddr,skb->len); ++ ++ //Set address of the data in the Transmit Address register // ++ MHal_EMAC_Write_TAR(skb_addr - RAM_VA_PA_OFFSET - MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_EMAC_Write_TCR(skb->len); ++ ++ dev->trans_start = jiffies; ++ dev_kfree_skb_irq(skb); ++ } ++ } ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ int _ret; ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ ++ /*Add skb to tx software queue*/ ++ _ret = MDev_EMAC_enqueue(&(LocPtr->tx_queue_head), &(LocPtr->tx_queue_tail), skb); ++ ++ /*Triger tx_task*/ ++ schedule_work(&LocPtr->tx_task); ++ ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ ++ if(_ret == 1) ++ { ++ return NETDEV_TX_BUSY; ++ } ++ else ++ { ++ return NETDEV_TX_OK; ++ } ++} ++ ++#elif defined(TX_SKB_PTR) ++ ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++#ifdef TX_SW_QUEUE ++ ++// read skb from TX_SW_QUEUE to HW, ++// !!!! NO SPIN LOCK INSIDE !!!! ++static void _MDev_EMAC_tx_read_TX_SW_QUEUE(int txIdleCount,struct net_device *dev,int intr) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++// int txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ ++ while(txIdleCount>0){ ++ ++ struct tx_ring *txq=&(LocPtr->tx_swq[LocPtr->tx_rdidx]); ++ if(txq->used == TX_DESC_WROTE) ++ { ++ Chip_Flush_Cache_Range((size_t)txq->skb->data,txq->skb->len); ++ MHal_EMAC_Write_TAR(txq->skb_physaddr - MIU0_BUS_BASE ); ++ MHal_EMAC_Write_TCR(txq->skb->len); ++ txq->used=TX_DESC_READ; ++ LocPtr->tx_rdidx ++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_rdidx) ++ { ++ LocPtr->tx_rdwrp++; ++ LocPtr->tx_rdidx =0; ++ } ++ }else{ ++ break; ++ } ++ txIdleCount--; ++ } ++ ++} ++ ++// clear skb from TX_SW_QUEUE ++// !!!! NO SPIN LOCK INSIDE !!!! ++static void _MDev_EMAC_tx_clear_TX_SW_QUEUE(int txIdleCount,struct net_device *dev,int intr) ++{ ++ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ int clearcnt=0; ++ int fifoCount=0;//LocPtr->tx_rdidx-LocPtr->tx_clidx; ++ if(0==txIdleCount)return; ++ ++ fifoCount=LocPtr->tx_rdidx-LocPtr->tx_clidx; ++ if(fifoCount<0)fifoCount=LocPtr->tx_rdidx+(TX_SW_QUEUE_SIZE-LocPtr->tx_clidx); ++ ++ /* ++ * "fifoCount" is the count of the packets that has been sent to the EMAC HW. ++ * "(TX_FIFO_SIZE-txIdleCount)" is the packet count that has not yet been sent out completely by EMAC HW ++ */ ++ clearcnt = fifoCount-(TX_FIFO_SIZE-txIdleCount); ++ if((clearcnt > TX_FIFO_SIZE) || (clearcnt < 0)){ ++ printk(KERN_ERR"fifoCount in _MDev_EMAC_tx_clear_TX_SW_QUEUE() ERROR!! fifoCount=%d intr=%d, %d, %d, %d, %d\n", ++ fifoCount,intr,LocPtr->tx_rdidx,LocPtr->tx_clidx,txIdleCount,TX_FIFO_SIZE); ++ } ++ ++ while(clearcnt>0) ++ { ++ struct tx_ring *txq=&(LocPtr->tx_swq[LocPtr->tx_clidx]); ++ if(TX_DESC_READ==txq->used) ++ { ++ ++ dma_unmap_single(&dev->dev, txq->skb_physaddr, txq->skb->len, DMA_TO_DEVICE); ++ ++ LocPtr->stats.tx_bytes += txq->skb->len; ++ tx_bytes_per_timer += txq->skb->len; ++ ++ dev_kfree_skb_any(txq->skb); ++ ++ txq->used = TX_DESC_CLEARED; ++ txq->skb=NULL; ++ LocPtr->tx_clidx++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_clidx) ++ { ++ LocPtr->tx_clwrp++; ++ LocPtr->tx_clidx =0; ++ } ++ }else{ ++ break; ++ } ++ clearcnt--; ++ } ++} ++ ++static void _MDev_EMAC_tx_reset_TX_SW_QUEUE(struct net_device* netdev) ++{ ++ struct EMAC_private *LocPtr; ++ u32 i=0; ++ LocPtr = (struct EMAC_private*) netdev_priv(netdev); ++ for (i=0;itx_swq[i].skb != NULL) ++ { ++ dma_unmap_single(&netdev->dev, LocPtr->tx_swq[i].skb_physaddr, LocPtr->tx_swq[i].skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb_any(LocPtr->tx_swq[i].skb); ++ ++ } ++ LocPtr->tx_swq[i].skb = NULL; ++ LocPtr->tx_swq[i].used = TX_DESC_CLEARED; ++ LocPtr->tx_swq[i].skb_physaddr = 0; ++ } ++ LocPtr->tx_clidx = 0; ++ LocPtr->tx_wridx = 0; ++ LocPtr->tx_rdidx = 0; ++ LocPtr->tx_clwrp = 0; ++ LocPtr->tx_wrwrp = 0; ++ LocPtr->tx_rdwrp = 0; ++ LocPtr->tx_swq_full_cnt=0; ++} ++ ++#endif ++static int MDev_EMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ int txIdleCount=0; ++ ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ if(g_emac_led_count++ > g_emac_led_flick_speed){ ++ MDrv_GPIO_Set_Low(g_emac_led_orange); ++ g_emac_led_count=0; ++ } ++ } ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++#ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE_TX(); ++#endif ++ ++ if (netif_queue_stopped(emac_dev)){ ++ EMAC_ERR("netif_queue_stopped\n"); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ if (!netif_carrier_ok(emac_dev)){ ++ EMAC_ERR("netif_carrier_off\n"); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ if (skb->len > EMAC_MTU) ++ { ++ EMAC_ERR("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++#if defined(PACKET_DUMP) ++ if(1==txDumpCtrl && NULL!=txDumpFile) ++ { ++ txDumpFileLength+=msys_kfile_write(txDumpFile,txDumpFileLength,skb->data,skb->len); ++ } ++ else if(2==txDumpCtrl && NULL!=txDumpFile) ++ { ++ msys_kfile_close(txDumpFile); ++ txDumpFile=NULL; ++ printk(KERN_WARNING"close emac tx_dump file '%s', len=0x%08X...\n",txDumpFileName,txDumpFileLength); ++ } ++#endif ++ ++#ifdef TX_SW_QUEUE ++ { ++ ++ int queue_size=0; ++ //FIFO full, loop until HW empty then try again ++ //This is an abnormal condition as the upper network tx_queue should already been stopped by "netif_stop_queue(dev)" in code below ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used > TX_DESC_CLEARED) ++ { ++ printk(KERN_ERR"ABNORMAL !! %d, %d, %d, %d\n",LocPtr->tx_wridx,LocPtr->tx_rdidx,LocPtr->tx_clidx, LocPtr->tx_swq[LocPtr->tx_wridx].used ); ++ BUG(); ++ } ++ ++ //map skbuffer for DMA ++ skb_addr = dma_map_single(&dev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ ++ if (dma_mapping_error(&dev->dev, skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ ++ goto out_unlock; ++ } ++ ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb = skb; ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb_physaddr= skb_addr; ++ LocPtr->tx_swq[LocPtr->tx_wridx].used = TX_DESC_WROTE; ++ LocPtr->tx_wridx ++; ++ if(TX_SW_QUEUE_SIZE==LocPtr->tx_wridx) ++ { ++ LocPtr->tx_wridx=0; ++ LocPtr->tx_wrwrp++; ++ } ++ ++ ++ //if FIFO is full, netif_stop_queue ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used > TX_DESC_CLEARED) ++ { ++ LocPtr->tx_swq_full_cnt++; ++ netif_stop_queue(dev); ++ } ++ ++ queue_size=LocPtr->tx_wridx-LocPtr->tx_clidx; ++ if(queue_size<0)queue_size=LocPtr->tx_wridx+(TX_SW_QUEUE_SIZE-LocPtr->tx_clidx); ++ if(max_tx_packet_countlock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ //map skbuffer for DMA ++ skb_addr = dma_map_single(&dev->dev, skb->data, skb->len, DMA_TO_DEVICE); ++ if (dma_mapping_error(&dev->dev, skb_addr)) ++ { ++ dev_kfree_skb_any(skb); ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__); ++ dev->stats.tx_dropped++; ++ ++ goto out_unlock; ++ } ++ ++ /* push skb into software queue*/ ++ /* kick out the earliest skb in queue */ ++ if( LocPtr->tx_swq[LocPtr->tx_wridx].used ==1 && LocPtr->tx_swq[LocPtr->tx_wridx].skb != NULL) ++ { ++ dma_unmap_single(&dev->dev, LocPtr->tx_swq[LocPtr->tx_wridx].skb_physaddr, skb->len, DMA_TO_DEVICE); ++ dev_kfree_skb_any(LocPtr->tx_swq[LocPtr->tx_wridx].skb); ++ LocPtr->tx_swq[LocPtr->tx_wridx].used = 0; ++ LocPtr->stats.tx_bytes += skb->len; ++ tx_bytes_per_timer += skb->len; ++ } ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb = skb; ++ LocPtr->tx_swq[LocPtr->tx_wridx].used = 1; ++ LocPtr->tx_swq[LocPtr->tx_wridx].skb_physaddr= skb_addr; ++ LocPtr->tx_wridx ++; ++ LocPtr->tx_wridx = LocPtr->tx_wridx % TX_RING_SIZE; ++ ++ //set DMA address and trigger DMA ++ Chip_Flush_Cache_Range((size_t)skb->data, skb->len); ++ MHal_EMAC_Write_TAR( skb_addr - MIU0_BUS_BASE ); ++ // Set length of the packet in the Transmit Control register // ++ MHal_EMAC_Write_TCR(skb->len); ++ ++#endif ++ if(min_tx_fifo_idle_count>txIdleCount) min_tx_fifo_idle_count=txIdleCount; ++ ++ dev->trans_start = jiffies; ++ ++ ++out_unlock: ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_OK; ++} ++ ++ ++ ++#else ++//------------------------------------------------------------------------------------------------- ++//Transmit packet. ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_tx (struct sk_buff *skb, struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ unsigned long flags; ++ dma_addr_t skb_addr; ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ ++#ifdef CONFIG_MSTAR_EEE ++ MHal_EMAC_Disable_EEE_TX(); ++#endif ++ ++ if (skb->len > EMAC_MTU) ++ { ++ EMAC_ERR("Wrong Tx len:%u\n", skb->len); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; ++ } ++ ++ //find out the last one buffer, notice upperr layer to block transmit. ++ //if( MDev_EMAC_GetTXFIFOIdle() <= 1) ++ // netif_stop_queue(dev); ++ ++ ++ if (NETDEV_TX_OK != MDev_EMAC_CheckTSR()) ++ { ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_BUSY; //check ++ } ++ ++ ++ ++ skb_addr = get_tx_addr(); ++ ++ memcpy((void*)skb_addr, skb->data, skb->len); ++ ++ #ifdef CONFIG_MP_ETHERNET_MSTAR_ICMP_ENHANCE ++ MDev_EMAC_Period_Retry(skb, dev); ++ #endif ++ ++ if (!skb_addr) ++ { ++ dev_err(NULL, ++ "dma map 2 failed (%p, %i). Dropping packet\n", ++ skb->data, skb->len); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return -ENOMEM; ++ } ++ ++ // Store packet information (to free when Tx completed) // ++ //LocPtr->skb = skb; ++ //LocPtr->skb_length =(int) skb->len; ++ LocPtr->stats.tx_bytes += skb->len; ++ ++ Chip_Flush_Cache_Range(skb_addr, skb->len); //Chip_Flush_Memory_Range(0, 0xFFFFFFFFUL); ++ ++ //MDrv_EMAC_DumpMem(tx_swq->skb_physaddr,skb->len); ++ //Set address of the data in the Transmit Address register // ++ MHal_EMAC_Write_TAR(skb_addr - RAM_VA_PA_OFFSET - MIU0_BUS_BASE); ++ ++ // Set length of the packet in the Transmit Control register // ++ MHal_EMAC_Write_TCR(skb->len); ++ ++ dev->trans_start = jiffies; ++ ++ dev_kfree_skb_irq(skb); ++ ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return NETDEV_TX_OK; ++} ++#endif ++ ++#if 0 //ajtest ++static int ajtest_recv_count=0; ++static ssize_t ajtest_recv_count_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ ++ int val = simple_strtoul(buf, NULL, 10); ++ if(0==val) ++ { ++ ++ ajtest_recv_count=0; ++ } ++ return count; ++} ++static ssize_t ajtest_recv_count_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ++ return sprintf(buf, "%d\n", ajtest_recv_count); ++} ++DEVICE_ATTR(ajtest_recv_count, 0644, ajtest_recv_count_show, ajtest_recv_count_store); ++ ++ ++unsigned int aj_checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++ ++static int aj_check(char *pData, int pktlen, int flag) ++{ ++ int res=0; ++ if(pktlen>32) ++ { ++ char *dbuf=(pData+0x36); ++ ++ if(0x51==dbuf[0] && 0x58==dbuf[1] && 0x91==dbuf[2] && 0x58==dbuf[3]) ++ { ++ int dlen=0; ++ int pktid=0; ++ int pktcs=0;//((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ int cs=0; ++ unsigned char *buf=(unsigned char *)(dbuf+8); ++ ++ dlen=(dbuf[7]<<24) + (dbuf[6]<<16)+(dbuf[5]<<8) + (dbuf[4]); ++ pktid=(dbuf[11]<<24) + (dbuf[10]<<16)+(dbuf[9]<<8) + (dbuf[8]); ++ ++// printf("pktCount: %08d\n",pktCount); ++ pktcs=((buf[dlen-1])<<24) + (buf[dlen-2]<<16)+(buf[dlen-3]<<8) + (buf[dlen-4]); ++ cs=aj_checksum(buf,dlen-4); ++ if(pktcs!=cs) ++ { ++// int j=0; ++// unsigned int lc=0; ++ printk(KERN_WARNING"<[!! AJ_ERR %d, %d: 0x%08X, 0x%08X, %d ]>\n\n",ajtest_recv_count,pktid,cs,pktcs,flag); ++ res=-1; ++// for(j=0;j\n",ajss_recv_count,pktid,cs,pktcs,flag); ++// } ++ ++ ajtest_recv_count++; ++ } ++ } ++ return res; ++} ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Extract received frame from buffer descriptors and sent to upper layers. ++// (Called from interrupt context) ++// (Disable RX software discriptor) ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_rx (struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ struct recv_desc_bufs *dlist; ++ unsigned char *p_recv; ++ u32 pktlen; ++ u32 retval=0; ++ u32 received=0; ++ struct sk_buff *skb; ++ ++#ifdef RX_ZERO_COPY ++ u32 RBQP_offset; ++ u32 RBQP_rx_skb_addr = 0; ++// unsigned long flags; ++// int cidx=0; ++#endif ++ ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ if(g_emac_led_count++ > g_emac_led_flick_speed){ ++ MDrv_GPIO_Set_Low(g_emac_led_orange); ++ g_emac_led_count=0; ++ } ++ } ++ ++ ++ dlist = LocPtr->dlist ; ++ // If any Ownership bit is 1, frame received. ++ do ++ { ++#ifdef RX_ZERO_COPY ++ char* pData; ++#endif ++ Chip_Inv_Cache_Range((size_t)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)), sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr) ); ++ ++ if(!((dlist->descriptors[LocPtr->rxBuffIndex].addr) & EMAC_DESC_DONE)) ++ { ++ break; ++ } ++ ++ p_recv = (char *) ((((dlist->descriptors[LocPtr->rxBuffIndex].addr) & 0xFFFFFFFFUL) + RAM_VA_PA_OFFSET + MIU0_BUS_BASE) &~(EMAC_DESC_DONE | EMAC_DESC_WRAP)); ++ ++ pktlen = dlist->descriptors[LocPtr->rxBuffIndex].size & 0x7ffUL; /* Length of frame including FCS */ ++ ++ #if RX_THROUGHPUT_TEST ++ receive_bytes += pktlen; ++ #endif ++ ++ if (pktlen > EMAC_MTU || pktlen < 64) ++ { ++ EMAC_ERR("drop packet!!(pktlen = %d)", pktlen); ++ dlist->descriptors[LocPtr->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ ++ Chip_Flush_Cache_Range((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)), sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++ ++ //wrap after last buffer // ++ LocPtr->rxBuffIndex++; ++ if (LocPtr->rxBuffIndex == MAX_RX_DESCR) ++ { ++ LocPtr->rxBuffIndex = 0; ++ } ++ LocPtr->stats.rx_length_errors++; ++ LocPtr->stats.rx_errors++; ++ LocPtr->stats.rx_dropped++; ++ continue; ++ } ++ ++#ifndef RX_ZERO_COPY ++ ++ skb = alloc_skb (pktlen + 6, GFP_ATOMIC); ++ if (!skb) ++ { ++ LocPtr->stats.rx_dropped += 1; ++ printk(KERN_ERR"ERROR!![%s]%d\n",__FUNCTION__,__LINE__);; ++ return -ENOMEM; ++ } ++ skb_reserve (skb, 2); /* Align IP on 16 byte boundaries */ ++ ++ Chip_Inv_Cache_Range((unsigned long)p_recv, pktlen); //Chip_Inv_Cache_Range_VA_PA((unsigned long)p_recv,(unsigned long)(p_recv - RAM_VA_PA_OFFSET) ,pktlen); ++ ++ /* 'skb_put()' points to the start of sk_buff data area. */ ++ memcpy(skb_put(skb, pktlen), p_recv, pktlen); ++#else ++ pktlen -= 4; /* Remove FCS */ ++ skb = rx_skb[LocPtr->rxBuffIndex]; ++ pData=skb_put(rx_skb[LocPtr->rxBuffIndex], pktlen); ++ Chip_Inv_Cache_Range((unsigned long)pData, pktlen); ++ ++ //ajtest ++ /* below code is used to find the offset of ajtest header in incoming packet ++ for(cidx=0;cidx=pktlen) ++ { ++ break; ++ } ++ if(0x51==pData[cidx] && 0x58==pData[cidx+1] && 0x91==pData[cidx+2] && 0x58==pData[cidx+3]) ++ { ++ printk(KERN_WARNING"cidx: 0x%08X\n",cidx); ++ break; ++ } ++ } ++ */ ++#if defined(PACKET_DUMP) ++ if(1==rxDumpCtrl && NULL!=rxDumpFile) ++ { ++ rxDumpFileLength+=msys_kfile_write(rxDumpFile,rxDumpFileLength,pData,pktlen); ++ } ++ else if(2==rxDumpCtrl && NULL!=rxDumpFile) ++ { ++ msys_kfile_close(rxDumpFile); ++ rxDumpFile=NULL; ++ printk(KERN_WARNING"close emac rx_dump file '%s', len=0x%08X...\n",rxDumpFileName,rxDumpFileLength); ++ } ++#endif ++#endif ++ ++ skb->dev = dev; ++ skb->protocol = eth_type_trans (skb, dev); ++ //skb->len = pktlen; ++ dev->last_rx = jiffies; ++ LocPtr->stats.rx_bytes += pktlen; ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++ //check the pause ctl frame protocol //MAC_CONTROL_TYPE=0x8808 ++ if (((MAC_CONTROL_TYPE&0xFF)==((skb->protocol>>8)&0xFF)) && \ ++ (((MAC_CONTROL_TYPE>>8)&0xFF)==(skb->protocol&0xFF))) ++ { ++ int pause_time = 0; ++ int pause_time_to_jiffies = 0; ++ unsigned int mac_ctl_opcode = 0; ++ #if 0 ++ int i = 0; ++ unsigned char *pcc = p_recv; ++ ++ printk("Get ethernet flow control data:\n"); ++ for (i=0; i<((pktlen<0x20)?pktlen:0x20); i++) ++ { ++ printk("%02x ",*(pcc+i)); ++ if (i==7) printk(" "); ++ if ((0x100) && (0 == (i+1)%0x10)) printk("\n"); ++ } ++ //printk("\n"); ++ #endif ++ ++ //Get the pause ctl frame opcode //MAC_CONTROL_OPCODE=0x0001 ++ mac_ctl_opcode = (((*(p_recv+14))<<8)&0xFF00) + ((*(p_recv+15))&0xFF); ++ if (MAC_CONTROL_OPCODE == mac_ctl_opcode) ++ { ++ pause_time = (((*(p_recv+16))<<8)&0xFF00) + ((*(p_recv+17))&0xFF); ++ ++ spin_lock_irq(&emac_flow_ctl_lock); ++ if (0 == eth_pause_cmd_enable) ++ { ++ netif_stop_queue (dev); ++ ++ //init_timer(&EMAC_flow_ctl_timer); ++ //EMAC_flow_ctl_timer.data = EMAC_FLOW_CTL_TMR; ++ if (EMAC_SPEED_100 == ThisBCE.speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_100M)+((0==(pause_time%PAUSE_TIME_DIVISOR_100M))?0:1); ++ EMAC_flow_ctl_timer.expires = jiffies + pause_time_to_jiffies; ++ } ++ else if (EMAC_SPEED_10 == ThisBCE.speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_10M)+((0==(pause_time%PAUSE_TIME_DIVISOR_10M))?0:1); ++ EMAC_flow_ctl_timer.expires = jiffies + pause_time_to_jiffies; ++ } ++ else ++ { ++ printk(KERN_WARNING"[%s:%d] Get emac speed(%d) error!\n", __func__, __LINE__, g_emac_speed); ++ } ++ ++ //printk(KERN_WARNING"[pause ctl] jiffies=0x%lx, expires==0x%lx, pause_time_to_jiffies=%d\n", ++ // jiffies, EMAC_flow_ctl_timer.expires, pause_time_to_jiffies); ++ add_timer(&EMAC_flow_ctl_timer); ++ ++ eth_pause_cmd_enable = 1; ++ } ++ else ++ { ++ unsigned long expires_new = 0; ++ ++ if (EMAC_SPEED_100 == ThisBCE.speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_100M)+((0==(pause_time%PAUSE_TIME_DIVISOR_100M))?0:1); ++ expires_new = jiffies + pause_time_to_jiffies; ++ } ++ else if (EMAC_SPEED_10 == ThisBCE.speed) ++ { ++ pause_time_to_jiffies = (pause_time/PAUSE_TIME_DIVISOR_10M)+((0==(pause_time%PAUSE_TIME_DIVISOR_10M))?0:1); ++ expires_new = jiffies + pause_time_to_jiffies; ++ } ++ else ++ { ++ printk(KERN_WARNING"[%s:%d] Get emac speed(%d) error!\n", __func__, __LINE__, g_emac_speed); ++ } ++ ++ mod_timer(&EMAC_flow_ctl_timer, expires_new); ++ } ++ spin_unlock_irq(&emac_flow_ctl_lock); ++ printk(KERN_WARNING"[%s:%d] Get pause time(0x%04x) from MAC PAUSE frame, eth_pause_cmd_enable=%d\n", ++ __func__, __LINE__, pause_time, eth_pause_cmd_enable); ++ } ++ } ++#endif ++ #if RX_THROUGHPUT_TEST ++ kfree_skb(skb); ++ #else ++ ++ #ifdef RX_CHECKSUM ++ if(((dlist->descriptors[LocPtr->rxBuffIndex].size & EMAC_DESC_TCP ) || (dlist->descriptors[LocPtr->rxBuffIndex].size & EMAC_DESC_UDP )) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].size & EMAC_DESC_IP_CSUM) && \ ++ (dlist->descriptors[LocPtr->rxBuffIndex].size & EMAC_DESC_TCP_UDP_CSUM) ) ++ { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } ++ else ++ { ++ skb->ip_summed = CHECKSUM_NONE; ++ } ++ #endif ++ ++ #ifdef ISR_BOTTOM_HALF ++ retval = netif_rx_ni(skb); ++ #elif defined MSTAR_EMAC_NAPI ++ retval = netif_receive_skb(skb); ++ #else ++ retval = netif_rx (skb); ++ #endif ++ ++ received++; ++ #endif/*RX_THROUGHPUT_TEST*/ ++ ++ if (dlist->descriptors[LocPtr->rxBuffIndex].size & EMAC_MULTICAST) ++ { ++ LocPtr->stats.multicast++; ++ } ++ ++#ifdef RX_ZERO_COPY ++ //dequeue_rx_buffer(LocPtr, &skb); ++ //if (!skb) { ++ // printk(KERN_ERR"%d: rx_next:%d rx_next_fill:%d rx_current_fill:%d\n",__LINE__,LocPtr->rx_next, LocPtr->rx_next_fill, LocPtr->rx_current_fill); ++ // panic("Can't dequeue skb from buffer."); ++ //} ++ if (!(skb = alloc_skb (SOFTWARE_DESC_LEN, GFP_ATOMIC))) { ++ printk(KERN_ERR"Can't alloc skb.[%s]%d\n",__FUNCTION__,__LINE__);; ++ return -ENOMEM; ++ } ++ ++ rx_skb[LocPtr->rxBuffIndex] = skb; ++ rx_abso_addr[LocPtr->rxBuffIndex] = (u32)rx_skb[LocPtr->rxBuffIndex]->data; ++ ++ RBQP_offset = LocPtr->rxBuffIndex * RBQP_HW_BYTES; ++ ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[LocPtr->rxBuffIndex]) - MIU0_BUS_BASE; ++ RBQP_rx_skb_addr |= EMAC_DESC_DONE; ++ if(LocPtr->rxBuffIndex == (MAX_RX_DESCR-1)) ++ RBQP_rx_skb_addr |= EMAC_DESC_WRAP; ++ MHal_EMAC_WritRam32(RAM_VA_PA_OFFSET, RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++#endif ++ ++ dlist->descriptors[LocPtr->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */ ++ //Chip_Inv_Cache_Range_VA_PA((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)),(unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)) - RAM_VA_PA_OFFSET ,sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++ Chip_Flush_Cache_Range((unsigned long)(&(dlist->descriptors[LocPtr->rxBuffIndex].addr)), sizeof(dlist->descriptors[LocPtr->rxBuffIndex].addr)); ++ ++ ++ //wrap after last buffer // ++ LocPtr->rxBuffIndex++; ++ if (LocPtr->rxBuffIndex == MAX_RX_DESCR) ++ { ++ LocPtr->rxBuffIndex = 0; ++ } ++ ++#ifdef MSTAR_EMAC_NAPI ++ if(received >= EMAC_NAPI_WEIGHT) { ++ break; ++ } ++#endif ++ ++ }while(1); ++ ++ ++#ifdef RX_ZERO_COPY ++ //spin_lock_irqsave(LocPtr->lock, flags); ++ //fill_rx_ring(emac_dev); ++ //spin_unlock_irqrestore(LocPtr->lock, flags); ++#endif ++ ++ if(received>max_rx_packet_count)max_rx_packet_count=received; ++ return received; ++} ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++//MAC interrupt handler ++//(Interrupt delay enable) ++//------------------------------------------------------------------------------------------------- ++#if defined ISR_BOTTOM_HALF ++void MDev_EMAC_bottom_rx_task(struct work_struct *work) ++{ ++ struct EMAC_private *LocPtr = container_of(work, struct EMAC_private, rx_task); ++ struct net_device *dev = LocPtr->dev; ++ ++ mutex_lock(&(LocPtr->mutex)); ++ MDev_EMAC_rx(dev); ++ mutex_unlock(&(LocPtr->mutex)); ++} ++#endif ++static int RBNA_detailed=0; ++irqreturn_t MDev_EMAC_interrupt(int irq,void *dev_id) ++{ ++ struct net_device *dev = (struct net_device *) dev_id; ++ struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(dev); ++ u32 intstatus=0; ++ unsigned long flags; ++#ifdef TX_SW_QUEUE ++ int txIdleCount=0; ++#endif ++#ifndef RX_ZERO_COPY ++ u32 wp = 0; ++#endif ++ ++ spin_lock_irqsave(LocPtr->lock, flags); ++ LocPtr->irqcnt++; ++#ifdef INT_JULIAN_D ++ //MAC Interrupt Status register indicates what interrupts are pending. ++ //It is automatically cleared once read. ++ xoffsetValue = MHal_EMAC_Read_JULIAN_0108() & 0x0000FFFFUL; ++ xReceiveNum += xoffsetValue&0xFFUL; ++ if(xoffsetValue&0x8000UL) ++ { ++ LocPtr->xReceiveFlag = 1; ++ } ++#endif ++ ++#ifndef RX_ZERO_COPY ++ wp = MHal_EMAC_Read_JULIAN_0100() & 0x00100000UL; ++ if(wp) ++ { ++ EMAC_ERR("EMAC HW write invalid address\n"); ++ } ++#endif ++ ++ ++ ThisUVE.flagRBNA = 0; ++ ++ oldTime = getCurMs(); ++ while((LocPtr->xReceiveFlag == 1) || (intstatus = (MHal_EMAC_Read_ISR() & ~(MHal_EMAC_Read_IMR()) & EMAC_INT_MASK )) ) ++ { ++ if (intstatus & EMAC_INT_RBNA) ++ { ++ struct recv_desc_bufs *dlist=LocPtr->dlist; ++ int empty=0; ++ int idx; ++ LocPtr->stats.rx_missed_errors++; ++ ThisUVE.flagRBNA = 1; ++ LocPtr->xReceiveFlag = 1; ++ //write 1 clear ++ MHal_EMAC_Write_RSR(EMAC_BNA); ++ if(RBNA_detailed>0) ++ { ++ u32 u32RBQP_Addr = MHal_EMAC_Read_RBQP()-(RBQP_BASE - MIU0_BUS_BASE); ++ for(idx=0;idxdescriptors[idx].addr) & EMAC_DESC_DONE)) ++ { ++ empty++; ++ } ++ else ++ { ++ printk(KERN_ERR"RBNA: [0x%X]\n",idx); ++ } ++ ++ } ++ printk(KERN_ERR"RBNA: empty=0x%X, LocPtr->rxBuffIndex=0x%X, rx_missed_errors=%ld RBQP_offset=0x%x\n",empty,LocPtr->rxBuffIndex,LocPtr->stats.rx_missed_errors,u32RBQP_Addr); ++ } ++ //printk("RBNA\n"); ++ } ++ ++ // Transmit complete // ++ if (intstatus & EMAC_INT_TCOM) ++ { ++ LocPtr->tx_irqcnt++; ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ if(g_emac_led_count++ > g_emac_led_flick_speed){ ++ MDrv_GPIO_Set_High(g_emac_led_orange); ++ g_emac_led_count=0; ++ } ++ } ++ ++ #ifdef TX_SOFTWARE_QUEUE ++ /*Triger tx_task*/ ++ schedule_work(&LocPtr->tx_task); ++ #endif ++ ++ // The TCOM bit is set even if the transmission failed. // ++ if (intstatus & (EMAC_INT_TUND | EMAC_INT_RTRY)) ++ { ++ LocPtr->stats.tx_errors += 1; ++ if(intstatus & EMAC_INT_TUND) ++ { ++ //write 1 clear ++ MHal_EMAC_Write_TSR(EMAC_UND); ++ ++ //Reset TX engine ++ MDev_EMAC_TxReset(); ++ EMAC_ERR ("Transmit TUND error, TX reset\n"); ++ } ++ } ++ else ++ { ++ LocPtr->retx_count = 0; ++ } ++ ++ #if TX_THROUGHPUT_TEST ++ MDev_EMAC_tx(pseudo_packet, emac_dev); ++ #endif ++ #if defined(TX_SKB_PTR) ++ #ifdef TX_SW_QUEUE ++ if( ((LocPtr->ep_flag&EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ { ++ netif_wake_queue(dev); ++ } ++ txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ while(txIdleCount>0 && (LocPtr->tx_rdidx != LocPtr->tx_wridx)) ++ { ++ ++ _MDev_EMAC_tx_clear_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_IRQ); ++ _MDev_EMAC_tx_read_TX_SW_QUEUE(txIdleCount,dev,TX_SW_QUEUE_IN_IRQ); ++ txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ } ++ #else ++ if( (MDev_EMAC_GetTXFIFOIdle()>0) && netif_queue_stopped (dev)) ++ netif_wake_queue(dev); ++ ++ if (((LocPtr->ep_flag&EP_FLAG_SUSPENDING)==0) && netif_queue_stopped (dev)) ++ netif_wake_queue(dev); ++ #endif ++ #endif ++ } ++ ++ if(intstatus&EMAC_INT_DONE) ++ { ++ ThisUVE.flagISR_INT_DONE = 0x01UL; ++ } ++ ++ //Overrun // ++ if(intstatus & EMAC_INT_ROVR) ++ { ++ LocPtr->stats.rx_over_errors++; ++ contiROVR++; ++ //write 1 clear ++ MHal_EMAC_Write_RSR(EMAC_RSROVR); ++ EMAC_ERR ("==> %s: ROVR error %u times!\n", dev->name, contiROVR); ++ #ifndef TX_SKB_PTR ++ if (contiROVR < 3) ++ { ++ MDev_EMAC_Send_PausePkt(dev); ++ } ++ else ++ { ++ MDev_EMAC_SwReset(dev); ++ #ifdef INT_JULIAN_D ++ xReceiveNum = 0; ++ #endif ++ } ++ #endif ++ } ++ else ++ { ++ contiROVR = 0; ++ } ++ ++ //if(xReceiveNum != 0) ++ //{ ++ // LocPtr->xReceiveFlag = 1; ++ //} ++ ++ if(intstatus&EMAC_INT_RCOM) ++ { ++ LocPtr->xReceiveFlag = 1; ++ } ++ ++ // Receive complete // ++ if(LocPtr->xReceiveFlag == 1) ++ { ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ if(g_emac_led_count++ > g_emac_led_flick_speed){ ++ MDrv_GPIO_Set_High(g_emac_led_orange); ++ g_emac_led_count=0; ++ } ++ ++ } ++ ++ LocPtr->xReceiveFlag = 0; ++ #ifdef MSTAR_EMAC_NAPI ++ /* Receive packets are processed by poll routine. If not running start it now. */ ++ if (napi_schedule_prep(&LocPtr->napi)) { ++ MDEV_EMAC_DISABLE_RX_REG(); ++ __napi_schedule(&LocPtr->napi); ++ } ++ #elif defined ISR_BOTTOM_HALF ++ /*Triger rx_task*/ ++ schedule_work(&LocPtr->rx_task); ++ #else ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ MDev_EMAC_rx(dev); ++ spin_lock_irqsave(LocPtr->lock, flags); ++ #endif ++ } ++ } ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ return IRQ_HANDLED; ++} ++ ++#ifdef MSTAR_EMAC_NAPI ++ ++// Enable MAC interrupts ++static void MDEV_EMAC_ENABLE_RX_REG(void) ++{ ++ u32 uRegVal; ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++#ifndef INT_JULIAN_D ++ // enable MAC interrupts ++ MHal_EMAC_Write_IER(EMAC_INT_RCOM); ++#else ++ // enable delay interrupt ++ uRegVal = MHal_EMAC_Read_JULIAN_0104(); ++ uRegVal |= 0x00000080UL; ++ MHal_EMAC_Write_JULIAN_0104(uRegVal); ++#endif ++} ++ ++// Disable MAC interrupts ++static void MDEV_EMAC_DISABLE_RX_REG(void) ++{ ++ u32 uRegVal; ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++#ifndef INT_JULIAN_D ++ MHal_EMAC_Write_IDR(EMAC_INT_RCOM); ++#else ++ // disable delay interrupt ++ uRegVal = MHal_EMAC_Read_JULIAN_0104(); ++ uRegVal &= ~(0x00000080UL); ++ MHal_EMAC_Write_JULIAN_0104(uRegVal); ++#endif ++} ++ ++static int MDev_EMAC_napi_poll(struct napi_struct *napi, int budget) ++{ ++ struct EMAC_private *LocPtr = container_of(napi, struct EMAC_private,napi); ++ struct net_device *dev = LocPtr->dev; ++ unsigned long flags = 0; ++ int work_done = 0; ++ ++ //mutex_lock(&(LocPtr->mutex)); ++ work_done = MDev_EMAC_rx(dev); ++ //mutex_unlock(&(LocPtr->mutex)); ++ ++ /* If budget not fully consumed, exit the polling mode */ ++ if (work_done < budget) { ++ napi_complete(napi); ++ // enable MAC interrupt ++ spin_lock_irqsave(LocPtr->lock, flags); ++ MDEV_EMAC_ENABLE_RX_REG(); ++ spin_unlock_irqrestore(LocPtr->lock, flags); ++ } ++ ++ return work_done; ++} ++ ++ ++#endif ++ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++irqreturn_t MDev_EMAC_interrupt_cable_unplug(int irq,void *dev_id) ++{ ++ //printk( KERN_ERR "[EMAC] %s\n" , __FUNCTION__); ++ if (netif_carrier_ok(emac_dev)) ++ netif_carrier_off(emac_dev); ++ if (!netif_queue_stopped(emac_dev)) ++ netif_stop_queue(emac_dev); ++ ThisBCE.connected = 0; ++ ++ #ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(emac_dev); ++ #endif ++ ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ MDrv_GPIO_Set_Low(g_emac_led_orange); ++ MDrv_GPIO_Set_Low(g_emac_led_green); ++ } ++ ++ return IRQ_HANDLED; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Hardware register set ++//------------------------------------------------------------------------------------------------- ++void MDev_EMAC_HW_init(void) ++{ ++ u32 word_ETH_CTL = 0x00000000UL; ++ u32 word_ETH_CFG = 0x00000800UL; ++ u32 uJulian104Value = 0; ++ u32 uNegPhyVal = 0; ++#ifdef SOFTWARE_DESCRIPTOR ++ u32 idxRBQP = 0; ++ u32 RBQP_offset = 0; ++#ifdef RX_ZERO_COPY ++ struct sk_buff *skb = NULL; ++ u32 RBQP_rx_skb_addr = 0; ++// struct EMAC_private *LocPtr = (struct EMAC_private*) netdev_priv(emac_dev); ++#endif ++#endif ++ ++ // (20071026_CHARLES) Disable TX, RX and MDIO: (If RX still enabled, the RX buffer will be overwrited) ++ MHal_EMAC_Write_CTL(word_ETH_CTL); ++ MHal_EMAC_Write_BUFF(0x00000000UL); ++#ifndef SOFTWARE_DESCRIPTOR ++ // Init RX -------------------------------------------------------------- ++ memset((u8*)RAM_VA_PA_OFFSET + RX_BUFFER_BASE, 0x00UL, RX_BUFFER_SIZE); ++ ++ MHal_EMAC_Write_BUFF((RX_BUFFER_BASE | RX_BUFFER_SEL) - MIU0_BUS_BASE); ++ MHal_EMAC_Write_RDPTR(0x00000000UL); ++ MHal_EMAC_Write_WRPTR(0x00000000UL); ++#endif ++#ifdef INT_JULIAN_D ++ //Reg_rx_frame_cyc[15:8] -0xFF range 1~255 ++ //Reg_rx_frame_num[7:0] -0x05 receive frames per INT. ++ //0x80 Enable interrupt delay mode. ++ //register 0x104 receive counter need to modify smaller for ping ++ //Modify bigger(need small than 8) for throughput ++ uJulian104Value = JULIAN_104_VAL&(~0x80);//0xFF050080; ++ MHal_EMAC_Write_JULIAN_0104(uJulian104Value); ++#else ++ // Enable Interrupts ---------------------------------------------------- ++ uJulian104Value = 0x00000000UL; ++ MHal_EMAC_Write_JULIAN_0104(uJulian104Value); ++#endif ++ // Set MAC address ------------------------------------------------------ ++ MHal_EMAC_Write_SA1_MAC_Address(ThisBCE.sa1[0], ThisBCE.sa1[1], ThisBCE.sa1[2], ThisBCE.sa1[3], ThisBCE.sa1[4], ThisBCE.sa1[5]); ++ MHal_EMAC_Write_SA2_MAC_Address(ThisBCE.sa2[0], ThisBCE.sa2[1], ThisBCE.sa2[2], ThisBCE.sa2[3], ThisBCE.sa2[4], ThisBCE.sa2[5]); ++ MHal_EMAC_Write_SA3_MAC_Address(ThisBCE.sa3[0], ThisBCE.sa3[1], ThisBCE.sa3[2], ThisBCE.sa3[3], ThisBCE.sa3[4], ThisBCE.sa3[5]); ++ MHal_EMAC_Write_SA4_MAC_Address(ThisBCE.sa4[0], ThisBCE.sa4[1], ThisBCE.sa4[2], ThisBCE.sa4[3], ThisBCE.sa4[4], ThisBCE.sa4[5]); ++ ++#ifdef SOFTWARE_DESCRIPTOR ++ // Initialize "Receive Buffer Queue Pointer" ++ MHal_EMAC_Write_RBQP(RBQP_BASE - MIU0_BUS_BASE); ++ // Initialize Receive Buffer Descriptors ++ memset((u8*)RAM_VA_PA_OFFSET + RBQP_BASE, 0x00UL, RBQP_SIZE); // Clear for max(8*1024)bytes (max:1024 descriptors) ++ ++ #ifdef RX_CHECKSUM ++ uJulian104Value=uJulian104Value | (RX_CHECKSUM_ENABLE | SOFTWARE_DESCRIPTOR_ENABLE); ++ #else ++ uJulian104Value=uJulian104Value | SOFTWARE_DESCRIPTOR_ENABLE; ++ #endif ++ MHal_EMAC_Write_JULIAN_0104(uJulian104Value); ++ ++#ifdef RX_ZERO_COPY ++ for(idxRBQP = 0; idxRBQP < RBQP_LENG; idxRBQP++) ++ { ++ ++ //dequeue_rx_buffer(LocPtr, &skb); ++ //if (!skb) { ++ // skb = alloc_skb(SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ //} ++ if (!(skb = alloc_skb (SOFTWARE_DESC_LEN, GFP_ATOMIC))) { ++ printk("%s %d: alloc skb failed!\n",__func__, __LINE__); ++ panic("can't alloc skb"); ++ } ++ ++ rx_skb[idxRBQP] = skb; ++ ++ rx_abso_addr[idxRBQP] = (u32)rx_skb[idxRBQP]->data; ++ RBQP_offset = idxRBQP * 8; ++ if(idxRBQP < (RBQP_LENG - 1)) ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[idxRBQP]) - MIU0_BUS_BASE; ++ MHal_EMAC_WritRam32(RAM_VA_PA_OFFSET, RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ else ++ { ++ RBQP_rx_skb_addr = __virt_to_phys(rx_abso_addr[idxRBQP]) - MIU0_BUS_BASE + EMAC_DESC_WRAP; ++ MHal_EMAC_WritRam32(RAM_VA_PA_OFFSET, RBQP_BASE + RBQP_offset, RBQP_rx_skb_addr); ++ } ++ } ++#else ++ for(idxRBQP = 0; idxRBQP < RBQP_LENG; idxRBQP++) ++ { ++ ++ RBQP_offset = idxRBQP * RBQP_HW_BYTES; ++ if(idxRBQP < (RBQP_LENG - 1)) ++ { ++ MHal_EMAC_WritRam32(RAM_VA_PA_OFFSET, RBQP_BASE + RBQP_offset, (RX_BUFFER_BASE - MIU0_BUS_BASE + SOFTWARE_DESC_LEN * idxRBQP)); ++ } ++ else ++ { ++ MHal_EMAC_WritRam32(RAM_VA_PA_OFFSET, RBQP_BASE + RBQP_offset, (RX_BUFFER_BASE - MIU0_BUS_BASE + SOFTWARE_DESC_LEN * idxRBQP + EMAC_DESC_WRAP)); ++ } ++ ++ } ++#endif //#ifdef RX_ZERO_COPY ++#endif //#ifdef SOFTWARE_DESCRIPTOR ++ ++ if (!ThisUVE.initedEMAC) ++ { ++#ifdef CONFIG_EMAC_PHY_RESTART_AN ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1000UL); ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1000UL); ++ //MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1200UL); ++#else ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x9000UL); ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1000UL); ++#endif /* CONFIG_EMAC_PHY_RESTART_AN */ ++ ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++ MHal_EMAC_write_phy(phyaddr, MII_ADVERTISE, 0xDE1UL); //BIT0|BIT5~8|BIT10|BIT11 //pause disable transmit, enable receive ++#endif ++#if !defined( CONFIG_ETHERNET_ALBANY) ++ //force to set 10M on FPGA ++ MHal_EMAC_write_phy(phyaddr, MII_ADVERTISE, 0x0061UL); ++ MHal_EMAC_write_phy(phyaddr, MII_CTRL1000, 0x0000UL); ++ mdelay(10); ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1200UL); ++#endif ++ ++ // IMPORTANT: Run NegotiationPHY() before writing REG_ETH_CFG. ++ uNegPhyVal = MHal_EMAC_NegotiationPHY(); ++ if(uNegPhyVal == 0x01UL) ++ { ++ ThisUVE.flagMacTxPermit = 0x01UL; ++ ThisBCE.duplex = 1; ++ ++ } ++ else if(uNegPhyVal == 0x02UL) ++ { ++ ThisUVE.flagMacTxPermit = 0x01UL; ++ ThisBCE.duplex = 2; ++ } ++ ++ // ETH_CFG Register ----------------------------------------------------- ++ word_ETH_CFG = 0x00000800UL; // Init: CLK = 0x2 ++ // (20070808) IMPORTANT: REG_ETH_CFG:bit1(FD), 1:TX will halt running RX frame, 0:TX will not halt running RX frame. ++ // If always set FD=0, no CRC error will occur. But throughput maybe need re-evaluate. ++ // IMPORTANT: (20070809) NO_MANUAL_SET_DUPLEX : The real duplex is returned by "negotiation" ++ if(ThisBCE.speed == EMAC_SPEED_100) word_ETH_CFG |= 0x00000001UL; ++ if(ThisBCE.duplex == 2) word_ETH_CFG |= 0x00000002UL; ++ if(ThisBCE.cam == 1) word_ETH_CFG |= 0x00000200UL; ++ if(ThisBCE.rcv_bcast == 0) word_ETH_CFG |= 0x00000020UL; ++ if(ThisBCE.rlf == 1) word_ETH_CFG |= 0x00000100UL; ++ ++ MHal_EMAC_Write_CFG(word_ETH_CFG); ++ // ETH_CTL Register ----------------------------------------------------- ++ word_ETH_CTL = 0x0000000CUL; // Enable transmit and receive : TE + RE = 0x0C (Disable MDIO) ++ if(ThisBCE.wes == 1) word_ETH_CTL |= 0x00000080UL; ++ MHal_EMAC_Write_CTL(word_ETH_CTL); ++ MHal_EMAC_Write_JULIAN_0100(JULIAN_100_VAL); ++ ++ ThisUVE.flagPowerOn = 1; ++ ThisUVE.initedEMAC = 1; ++ } ++ ++ MHal_EMAC_HW_init(); ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC init Variable ++//------------------------------------------------------------------------------------------------- ++extern phys_addr_t memblock_start_of_DRAM(void); ++extern phys_addr_t memblock_size_of_first_region(void); ++ ++static phys_addr_t MDev_EMAC_VarInit(void) ++{ ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ ++ char addr[6]; ++ u32 HiAddr, LoAddr; ++ phys_addr_t *alloRAM_VA_BASE; ++ MSYS_DMEM_INFO mem_info; ++ int ret=0; ++ /********************************************************************/ ++ /*alloRAM_VA_BASE++buffer_offset private date(no use) */ ++ /* RBQP_BASE++RBQP_LENG*0x8 Descripter table */ ++ /* RX_BUFFER_BASE++RBQP_LENG*0x800 rx buffer */ ++ /* TX_BUFFER_BASE++RBQP_LENG*0x8 tx Descripter(no use) */ ++ /* TX_SKB_BASE++TX_RING_SIZE*0x800 tx skb buffer for TX_QUEUE_4 */ ++ /********************************************************-***********/ ++ ++#ifdef RX_ZERO_COPY ++ alloRAM_SIZE = RBQP_SIZE+SOFTWARE_DESC_LEN*TX_RING_SIZE; ++#else ++ alloRAM_SIZE = RBQP_SIZE+RX_BUFFER_SIZE+SOFTWARE_DESC_LEN*TX_RING_SIZE; ++#endif ++ ++ mem_info.length = alloRAM_SIZE; ++ strcpy(mem_info.name, "EMAC_BUFF"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ panic("unable to locate DMEM for EMAC alloRAM!! error=%d\n",ret); ++ } ++ alloRAM_PA_BASE = mem_info.phys; ++ alloRAM_VA_BASE = (phys_addr_t *)((size_t)mem_info.kvirt); ++ ++ EMAC_DBG("alloRAM_VA_BASE=0x%zx alloRAM_PA_BASE=0x%zx\n alloRAM_SIZE=0x%zx\n", (size_t) alloRAM_VA_BASE,(size_t) alloRAM_PA_BASE,(size_t)alloRAM_SIZE); ++ BUG_ON(!alloRAM_VA_BASE); ++ ++#ifndef RX_ZERO_COPY ++ //Add Write Protect ++ MHal_EMAC_Write_Protect(alloRAM_PA_BASE - MIU0_BUS_BASE, alloRAM_SIZE); ++#endif ++ memset((phys_addr_t *)alloRAM_VA_BASE,0x00UL,alloRAM_SIZE); ++ ++ //buffer_offset = 0;//(sizeof(struct EMAC_private) + 0x3FFFUL) & ~0x3FFFUL; //karl20151021:no used ++ RAM_ALLOC_SIZE = alloRAM_SIZE; ++ RAM_VA_BASE = ((phys_addr_t)alloRAM_VA_BASE ); // IMPORTANT: Let lowest 14 bits as zero. ++ RAM_PA_BASE = ((phys_addr_t)alloRAM_PA_BASE ); // IMPORTANT: Let lowest 14 bits as zero. ++ RAM_VA_PA_OFFSET = RAM_VA_BASE - RAM_PA_BASE; // IMPORTANT_TRICK_20070512 ++ ++ RBQP_BASE = RAM_PA_BASE; ++#ifndef RX_ZERO_COPY ++ RX_BUFFER_BASE = RBQP_BASE + RBQP_SIZE; ++ TX_SKB_BASE = RX_BUFFER_BASE + RX_BUFFER_SIZE; //TX_BUFFER_BASE + MAX_RX_DESCR * sizeof(struct rbf_t); ++#else ++ TX_SKB_BASE = RBQP_BASE + RBQP_SIZE; //TX_BUFFER_BASE + MAX_RX_DESCR * sizeof(struct rbf_t); ++#endif ++ ++ EMAC_DBG("RAM_VA_BASE=0x%08x\n", RAM_VA_BASE); ++ EMAC_DBG("RAM_PA_BASE=0x%08x\n", RAM_PA_BASE); ++ EMAC_DBG("RAM_VA_PA_OFFSET=0x%08x\n", RAM_VA_PA_OFFSET); ++ EMAC_DBG("RBQP_BASE=0x%08x size=0x%x\n", RBQP_BASE, RBQP_SIZE); ++#ifndef RX_ZERO_COPY ++ EMAC_DBG("RX_BUFFER_BASE=0x%08x size=0x%x\n", RX_BUFFER_BASE, RX_BUFFER_SIZE); ++#endif ++ EMAC_DBG("TX_SKB_BASE=0x%08x size=0x%x\n", TX_SKB_BASE,SOFTWARE_DESC_LEN*TX_RING_SIZE); ++ ++ memset(&ThisBCE,0x00UL,sizeof(BasicConfigEMAC)); ++ memset(&ThisUVE,0x00UL,sizeof(UtilityVarsEMAC)); ++ ++ ThisBCE.wes = 0; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ ThisBCE.duplex = 2; // 1:Half-duplex, 2:Full-duplex ++ ThisBCE.cam = 0; // 0:No CAM, 1:Yes ++ ThisBCE.rcv_bcast = 0; // 0:No, 1:Yes ++ ThisBCE.rlf = 0; // 0:No, 1:Yes receive long frame(1522) ++ ThisBCE.rcv_bcast = 1; ++ ThisBCE.speed = EMAC_SPEED_100; ++ ++ // Check if bootloader set address in Specific-Address 1 // ++ HiAddr = MHal_EMAC_get_SA1H_addr(); ++ LoAddr = MHal_EMAC_get_SA1L_addr(); ++ ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (ThisBCE.sa1, &addr, 6); ++ } ++ else ++ { ++ // Check if bootloader set address in Specific-Address 2 // ++ HiAddr = MHal_EMAC_get_SA2H_addr(); ++ LoAddr = MHal_EMAC_get_SA2L_addr(); ++ addr[0] = (LoAddr & 0xffUL); ++ addr[1] = (LoAddr & 0xff00UL) >> 8; ++ addr[2] = (LoAddr & 0xff0000UL) >> 16; ++ addr[3] = (LoAddr & 0xff000000UL) >> 24; ++ addr[4] = (HiAddr & 0xffUL); ++ addr[5] = (HiAddr & 0xff00UL) >> 8; ++ ++ if (is_valid_ether_addr (addr)) ++ { ++ memcpy (ThisBCE.sa1, &addr, 6); ++ } ++ else ++ { ++ ThisBCE.sa1[0] = MY_MAC[0]; ++ ThisBCE.sa1[1] = MY_MAC[1]; ++ ThisBCE.sa1[2] = MY_MAC[2]; ++ ThisBCE.sa1[3] = MY_MAC[3]; ++ ThisBCE.sa1[4] = MY_MAC[4]; ++ ThisBCE.sa1[5] = MY_MAC[5]; ++ } ++ } ++ ThisBCE.connected = 0; ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++ ThisBCE.sa2[0] = ETH_PAUSE_FRAME_DA_MAC[0]; ++ ThisBCE.sa2[1] = ETH_PAUSE_FRAME_DA_MAC[1]; ++ ThisBCE.sa2[2] = ETH_PAUSE_FRAME_DA_MAC[2]; ++ ThisBCE.sa2[3] = ETH_PAUSE_FRAME_DA_MAC[3]; ++ ThisBCE.sa2[4] = ETH_PAUSE_FRAME_DA_MAC[4]; ++ ThisBCE.sa2[5] = ETH_PAUSE_FRAME_DA_MAC[5]; ++#endif ++ return (phys_addr_t)alloRAM_VA_BASE; ++} ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++static void MDev_EMAC_netpoll(struct net_device *dev) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ MDev_EMAC_interrupt(dev->irq, dev); ++ local_irq_restore(flags); ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Initialize the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++static const struct net_device_ops mstar_lan_netdev_ops = { ++ .ndo_open = MDev_EMAC_open, ++ .ndo_stop = MDev_EMAC_close, ++ .ndo_start_xmit = MDev_EMAC_tx, ++ .ndo_set_mac_address = MDev_EMAC_set_mac_address, ++ .ndo_set_rx_mode = MDev_EMAC_set_rx_mode, ++ .ndo_do_ioctl = MDev_EMAC_ioctl, ++ .ndo_get_stats = MDev_EMAC_stats, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = MDev_EMAC_netpoll, ++#endif ++ ++}; ++ ++static int MDev_EMAC_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct EMAC_private *LocPtr =(struct EMAC_private *) netdev_priv(dev); ++ ++ mii_ethtool_gset (&LocPtr->mii, cmd); ++ ++ return 0; ++} ++ ++static int MDev_EMAC_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) ++{ ++ struct EMAC_private *LocPtr =(struct EMAC_private *) netdev_priv(dev); ++ ++ mii_ethtool_sset (&LocPtr->mii, cmd); ++ ++ return 0; ++} ++ ++static int MDev_EMAC_nway_reset(struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr =(struct EMAC_private *) netdev_priv(dev); ++ ++ mii_nway_restart (&LocPtr->mii); ++ ++ return 0; ++} ++ ++static u32 MDev_EMAC_get_link(struct net_device *dev) ++{ ++ u32 u32data; ++ struct EMAC_private *LocPtr =(struct EMAC_private *) netdev_priv(dev); ++ ++ u32data = mii_link_ok (&LocPtr->mii); ++ ++ return u32data; ++} ++ ++static const struct ethtool_ops ethtool_ops = { ++ .get_settings = MDev_EMAC_get_settings, ++ .set_settings = MDev_EMAC_set_settings, ++ .nway_reset = MDev_EMAC_nway_reset, ++ .get_link = MDev_EMAC_get_link, ++}; ++ ++#endif ++ ++static ssize_t dlist_info_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ if(0==input) ++ { ++ RBNA_detailed=0; ++ } ++ else if(1==input) ++ { ++ RBNA_detailed=1; ++ } ++ else if(2==input) ++ { ++ max_rx_packet_count=0; ++ max_tx_packet_count=0; ++ min_tx_fifo_idle_count=0xffff; ++ } ++ return count; ++} ++ ++static ssize_t dlist_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ int idx=0; ++ struct EMAC_private *LocPtr = (struct EMAC_private *) netdev_priv(emac_dev); ++ struct recv_desc_bufs *dlist=LocPtr->dlist; ++ int empty=0; ++ int max=MAX_RX_DESCR; ++ u32 u32RBQP_Addr=0; ++ ++ for(idx=0;idxdescriptors[idx].addr) & EMAC_DESC_DONE)) ++ { ++ empty++; ++ } ++ ++ } ++ u32RBQP_Addr =( MHal_EMAC_Read_RBQP()-(RBQP_BASE - MIU0_BUS_BASE))/RBQP_HW_BYTES; ++ ++ ++ str += scnprintf(str, end - str, "RBQP_size=0x%x, empty=0x%x, LocPtr->rxBuffIndex=0x%X, max_rx_packet_count=%d,u32RBQP_Addr=0x%x\n", ++ max,empty,LocPtr->rxBuffIndex,max_rx_packet_count,u32RBQP_Addr); ++ ++ ++ return (str - buf); ++} ++DEVICE_ATTR(dlist_info, 0644, dlist_info_show, dlist_info_store); ++ ++static ssize_t info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ //struct EMAC_private *LocPtr = (struct EMAC_private *) netdev_priv(emac_dev); ++ ++ //str += scnprintf(str, end - str, "%s %s\n", __DATE__, __TIME__); ++ str += scnprintf(str, end - str, "RAM_ALLOC_SIZE=0x%08x\n", RAM_ALLOC_SIZE); ++ str += scnprintf(str, end - str, "RAM_VA_BASE=0x%08x\n", RAM_VA_BASE); ++ str += scnprintf(str, end - str, "RAM_PA_BASE=0x%08x\n", RAM_PA_BASE); ++ str += scnprintf(str, end - str, "RAM_VA_PA_OFFSET=0x%08x\n", RAM_VA_PA_OFFSET); ++ str += scnprintf(str, end - str, "RBQP_BASE=0x%08x size=0x%x\n", RBQP_BASE, RBQP_SIZE); ++#ifndef RX_ZERO_COPY ++ str += scnprintf(str, end - str, "RX_BUFFER_BASE=0x%08x size=0x%x\n", RX_BUFFER_BASE, RX_BUFFER_SIZE); ++#endif ++ str += scnprintf(str, end - str, "TX_SKB_BASE=0x%08x size=0x%x\n", TX_SKB_BASE,SOFTWARE_DESC_LEN*TX_RING_SIZE); ++ ++#ifdef MSTAR_EMAC_NAPI ++ str += scnprintf(str, end - str, "NAPI enabled, NAPI_weight=%d\n", EMAC_NAPI_WEIGHT); ++#endif ++#ifdef RX_ZERO_COPY ++ str += scnprintf(str, end - str, "ZERO_COPY enabled\n"); ++#endif ++#ifdef TX_SKB_PTR ++ str += scnprintf(str, end - str, "TX_SKB_PTR enabled\n"); ++#endif ++#ifdef TX_SW_QUEUE ++ str += scnprintf(str, end - str, "TX_SW_QUEUE enabled, TX_SW_QUEUE_SIZE=%d\n", TX_SW_QUEUE_SIZE); ++#endif ++#ifdef NEW_TX_QUEUE_128 ++ str += scnprintf(str, end - str, "NEW_TX_QUEUE_128 enabled, NEW_TX_QUEUE_SIZE=%d\n",NEW_TX_QUEUE_SIZE); ++#endif ++#ifdef NEW_TX_QUEUE_INTERRUPT_THRESHOLD ++ str += scnprintf(str, end - str, "NEW_TX_QUEUE_INTERRUPT_THRESHOLD enabled\n"); ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++DEVICE_ATTR(info, 0444, info_show, NULL); ++ ++ ++//struct timeval proc_read_time; ++static ssize_t tx_sw_queue_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++#ifdef TX_SKB_PTR ++ struct EMAC_private *LocPtr = (struct EMAC_private *) netdev_priv(emac_dev); ++ int idleCount=0; ++ ++#if defined(TX_SW_QUEUE) ++// unsigned long flags=0; ++// spin_lock_irqsave(LocPtr->lock,flags); ++ ++ str += scnprintf(str, end - str, "tx_wr[%d:%d], tx_rd[%d:%d], tx_cl[%d:%d]\ntx_swq_full_cnt=%d \nmax_tx_packet_count=%d\n", ++ LocPtr->tx_wrwrp,LocPtr->tx_wridx, ++ LocPtr->tx_rdwrp,LocPtr->tx_rdidx, ++ LocPtr->tx_clwrp,LocPtr->tx_clidx, ++ LocPtr->tx_swq_full_cnt, ++ max_tx_packet_count); ++ ++// spin_unlock_irqrestore(LocPtr->lock,flags); ++#endif ++ idleCount=MDev_EMAC_GetTXFIFOIdle(); ++ str += scnprintf(str, end - str, ++ "netif_queue_stopped=%d \n idleCount=%d \n irqcnt=%d, tx_irqcnt=%d \n tx_bytes_per_timerbak=%d \n min_tx_fifo_idle_count=%d \n LocPtr->tx_wridx=%d\n", ++ netif_queue_stopped(emac_dev), ++ idleCount, LocPtr->irqcnt, LocPtr->tx_irqcnt, ++ tx_bytes_per_timerbak, ++ min_tx_fifo_idle_count, LocPtr->tx_wridx); ++#endif ++ ++ if (str > buf) ++ str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(tx_sw_queue_info, 0444, tx_sw_queue_info_show, NULL); ++ ++ ++static ssize_t reverse_led_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ MHal_EMAC_Set_Reverse_LED(input); ++ return count; ++} ++static ssize_t reverse_led_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ u8 u8reg=0; ++ u8reg = MHal_EMAC_Get_Reverse_LED(); ++ return sprintf(buf, "%d\n", u8reg); ++} ++DEVICE_ATTR(reverse_led, 0644, reverse_led_show, reverse_led_store); ++ ++ ++static ssize_t check_link_time_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gu32CheckLinkTime = input; ++ return count; ++} ++static ssize_t check_link_time_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32CheckLinkTime); ++} ++DEVICE_ATTR(check_link_time, 0644, check_link_time_show, check_link_time_store); ++ ++static ssize_t check_link_timedis_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ gu32CheckLinkTimeDis = input; ++ return count; ++} ++static ssize_t check_link_timedis_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32CheckLinkTimeDis); ++} ++DEVICE_ATTR(check_link_timedis, 0644, check_link_timedis_show, check_link_timedis_store); ++ ++static ssize_t sw_led_flick_speed_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ ++ input = simple_strtoul(buf, NULL, 10); ++ g_emac_led_flick_speed = input; ++ return count; ++} ++static ssize_t sw_led_flick_speed_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "LED flick speed, the smaller the faster\n%d\n", g_emac_led_flick_speed); ++} ++DEVICE_ATTR(sw_led_flick_speed, 0644, sw_led_flick_speed_show, sw_led_flick_speed_store); ++ ++extern void MHal_EMAC_phy_trunMax(void); ++extern void MHal_EMAC_trim_phy(void); ++static ssize_t turndrv_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ u32 input; ++ if(!strncmp(buf, "0",strlen("0"))) ++ { ++ MHal_EMAC_trim_phy(); ++ return count; ++ } ++ ++ if(!strncmp(buf, "max",strlen("max"))) ++ { ++ MHal_EMAC_phy_trunMax(); ++ return count; ++ } ++ ++ if(!strncmp(buf, "f10t",strlen("10t"))) ++ { ++ //force to set 10M on FPGA ++ MHal_EMAC_write_phy(phyaddr, MII_ADVERTISE, 0x0061UL); ++ mdelay(10); ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1200UL); ++ return count; ++ } ++ if(!strncmp(buf, "an",strlen("an"))) ++ { ++ //force to set 10M on FPGA ++ MHal_EMAC_write_phy(phyaddr, MII_ADVERTISE, 0x01e1UL); ++ mdelay(10); ++ MHal_EMAC_write_phy(phyaddr, MII_BMCR, 0x1200UL); ++ return count; ++ } ++ ++ input = simple_strtoul(buf, NULL, 10); ++ ++ return count; ++} ++static ssize_t turndrv_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return 0; ++} ++ ++DEVICE_ATTR(turndrv, 0644, turndrv_show, turndrv_store); ++ ++static int MDev_EMAC_setup (struct net_device *dev, unsigned long phy_type) ++{ ++ struct EMAC_private *LocPtr; ++ static int already_initialized = 0; ++ dma_addr_t dmaaddr; ++ phys_addr_t RetAddr; ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ u32 retval; ++#endif ++ ++ if (already_initialized) ++ return FALSE; ++ ++ LocPtr = (struct EMAC_private *) netdev_priv(dev); ++ if (LocPtr == NULL) ++ { ++ free_irq (dev->irq, dev); ++ EMAC_ERR("LocPtr fail\n"); ++ return -ENOMEM; ++ } ++ ++#if defined ISR_BOTTOM_HALF ++ /*Init tx and rx tasks*/ ++ INIT_WORK(&LocPtr->rx_task, MDev_EMAC_bottom_rx_task); ++#endif ++#ifdef TX_SOFTWARE_QUEUE ++ INIT_WORK(&LocPtr->tx_task, MDev_EMAC_bottom_tx_task); ++#endif ++ ++ LocPtr->dev = dev; ++ RetAddr = MDev_EMAC_VarInit(); ++ if(!RetAddr) ++ { ++ EMAC_ERR("Var init fail!!\n"); ++ return FALSE; ++ } ++ ++ dev->base_addr = (long) (EMAC_RIU_REG_BASE+REG_BANK_EMAC0*0x200); ++ ++ MDev_EMAC_HW_init(); ++#ifdef TX_SKB_PTR ++#ifndef TX_SW_QUEUE ++ { ++ int i; ++ ++ for (i=0;itx_swq[i].used = 0; ++ LocPtr->tx_swq[i].skb = 0; ++ LocPtr->tx_swq[i].skb_physaddr = 0; ++ } ++ //LocPtr->tx_rdidx = 0; ++ LocPtr->tx_wridx = 0; ++ } ++#endif ++#endif ++ ++ // Allocate memory for DMA Receive descriptors // ++ LocPtr->dlist = (struct recv_desc_bufs *) (RBQP_BASE + RAM_VA_PA_OFFSET); ++ ++ if (LocPtr->dlist == NULL) ++ { ++ dma_free_noncoherent((void *)LocPtr, EMAC_ABSO_MEM_SIZE,&dmaaddr,0);//kfree (dev->priv); ++ free_irq (dev->irq, dev); ++ return -ENOMEM; ++ } ++ ++ LocPtr->lock = &emac_lock; ++ spin_lock_init (LocPtr->lock); ++ mutex_init(&(LocPtr->mutex)); ++ ++ ether_setup (dev); ++#if LINUX_VERSION_CODE == KERNEL_VERSION(2,6,28) ++ dev->open = MDev_EMAC_open; ++ dev->stop = MDev_EMAC_close; ++ dev->hard_start_xmit = MDev_EMAC_tx; ++ dev->get_stats = MDev_EMAC_stats; ++ dev->set_multicast_list = MDev_EMAC_set_rx_mode; ++ dev->do_ioctl = MDev_EMAC_ioctl; ++ dev->set_mac_address = MDev_EMAC_set_mac_address; ++#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ dev->netdev_ops = &mstar_lan_netdev_ops; ++#endif ++ dev->tx_queue_len = EMAC_MAX_TX_QUEUE; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) ++ ////SET_ETHTOOL_OPS(dev, ðtool_ops); ++ //EMAC_TODO("set Ethtool_ops\n"); ++ netdev_set_default_ethtool_ops(dev, ðtool_ops); ++#endif ++ ++ ++ MDev_EMAC_get_mac_address (dev); // Get ethernet address and store it in dev->dev_addr // ++ MDev_EMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ spin_lock_irq (LocPtr->lock); ++ MHal_EMAC_enable_mdi (); ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++ //Support for ethtool // ++ LocPtr->mii.dev = dev; ++ LocPtr->mii.mdio_read = MDev_EMAC_mdio_read; ++ LocPtr->mii.mdio_write = MDev_EMAC_mdio_write; ++ already_initialized = 1; ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ retval = MHal_EMAC_Read_JULIAN_0104() | TX_CHECKSUM_ENABLE; ++ MHal_EMAC_Write_JULIAN_0104(retval); ++ dev->features |= NETIF_F_IP_CSUM; ++#endif ++ ++ LocPtr->irqcnt=0; ++ LocPtr->tx_irqcnt=0; ++ ++ /* clear interrupt status, to avoid interrupt was set in uboot*/ ++ MHal_EMAC_Read_ISR(); ++ MHal_EMAC_Write_IDR(0xFFFF); ++ #ifdef INT_JULIAN_D ++ MHal_EMAC_Read_JULIAN_0108(); ++ #endif ++ ++ emac_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0); ++ if (!emac_dev->irq) ++ { ++ EMAC_ERR("Get irq number0 error from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ ++ //Install the interrupt handler // ++ //Notes: Modify linux/kernel/irq/manage.c /* interrupt.h */ ++ if (request_irq(dev->irq, MDev_EMAC_interrupt, 0/*SA_INTERRUPT*/, dev->name, dev)) ++ return -EBUSY; ++ ++#ifdef LAN_ESD_CARRIER_INTERRUPT ++ val = irq_of_parse_and_map(dev->dev.of_node, 1); ++ if (!val) ++ { ++ EMAC_ERR("Get irq number0 error from DTS\n"); ++ return -EPROBE_DEFER; ++ } ++ if (request_irq(val/*INT_FIQ_LAN_ESD+32*/, MDev_EMAC_interrupt_cable_unplug, 0/*SA_INTERRUPT*/, dev->name, dev)) ++ return -EBUSY; ++#endif ++ //Determine current link speed // ++ spin_lock_irq (LocPtr->lock); ++ (void) MDev_EMAC_update_linkspeed (dev); ++ spin_unlock_irq (LocPtr->lock); ++ ++ ++ LocPtr->mstar_class_emac_device = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR_EMAC_NUM, MINOR_EMAC_NUM), NULL, "emac"); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_tx_sw_queue_info); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_dlist_info); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_reverse_led); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_check_link_time); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_check_link_timedis); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_info); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_sw_led_flick_speed); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_turndrv); ++#if 0//ajtest ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_ajtest_recv_count); ++#endif ++#if defined(PACKET_DUMP) ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_tx_dump); ++ device_create_file(LocPtr->mstar_class_emac_device, &dev_attr_rx_dump); ++#endif ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Restar the ethernet interface ++// @return TRUE : Yes ++// @return FALSE : FALSE ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_SwReset(struct net_device *dev) ++{ ++ struct EMAC_private *LocPtr = (struct EMAC_private *) netdev_priv(dev); ++ u32 oldCFG, oldCTL; ++ u32 retval; ++ ++ MDev_EMAC_get_mac_address (dev); ++ oldCFG = MHal_EMAC_Read_CFG(); ++ oldCTL = MHal_EMAC_Read_CTL() & ~(EMAC_TE | EMAC_RE); ++ ++ //free tx skb ++ if (LocPtr->retx_count) ++ { ++ if (LocPtr->skb) ++ { ++ dev_kfree_skb_irq(LocPtr->skb ); ++ LocPtr->skb = NULL; ++ } ++ if (netif_queue_stopped (dev)) ++ netif_wake_queue (dev); ++ } ++#ifdef RX_ZERO_COPY ++ free_rx_skb(); ++#endif ++ netif_stop_queue (dev); ++ ++ retval = MHal_EMAC_Read_JULIAN_0100(); ++ MHal_EMAC_Write_JULIAN_0100(retval & 0x00000FFFUL); ++ MHal_EMAC_Write_JULIAN_0100(retval); ++ ++ MDev_EMAC_HW_init(); ++ MHal_EMAC_Write_CFG(oldCFG); ++ MHal_EMAC_Write_CTL(oldCTL); ++ MHal_EMAC_enable_mdi (); ++ MDev_EMAC_update_mac_address (dev); // Program ethernet address into MAC // ++ (void)MDev_EMAC_update_linkspeed (dev); ++ MHal_EMAC_Write_IDR(0xFFFFFFFF); ++ MHal_EMAC_Write_IER(gu32intrEnable); ++ MDev_EMAC_start (dev); ++ MDev_EMAC_set_rx_mode(dev); ++ netif_start_queue (dev); ++ contiROVR = 0; ++ LocPtr->retx_count = 0; ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ retval = MHal_EMAC_Read_JULIAN_0104() | TX_CHECKSUM_ENABLE; ++ MHal_EMAC_Write_JULIAN_0104(retval); ++#endif ++ EMAC_ERR("=> Take %lu ms to reset EMAC!\n", (getCurMs() - oldTime)); ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Detect MAC and PHY and perform initialization ++//------------------------------------------------------------------------------------------------- ++#if defined (CONFIG_OF) ++static struct of_device_id mstaremac_of_device_ids[] = { ++ {.compatible = "mstar-emac"}, ++ {}, ++}; ++#endif ++ ++static int MDev_EMAC_probe (struct net_device *dev) ++{ ++ int detected; ++ /* Read the PHY ID registers - try all addresses */ ++ detected = MDev_EMAC_setup(dev, MII_URANUS_ID); ++ return detected; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC Timer to detect cable pluged/unplugged ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_timer_callback(unsigned long value) ++{ ++ int ret = 0; ++ struct EMAC_private *LocPtr = (struct EMAC_private *) netdev_priv(emac_dev); ++ static u32 bmsr, time_count = 0; ++ ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++ if (EMAC_FLOW_CTL_TMR == value) ++ { ++ netif_wake_queue((struct net_device *)emac_dev); ++ spin_lock_irq(&emac_flow_ctl_lock); ++ eth_pause_cmd_enable = 0; ++ spin_unlock_irq(&emac_flow_ctl_lock); ++ return; ++ } ++#endif ++ ++#ifndef INT_JULIAN_D ++ if (EMAC_RX_TMR == value) ++ { ++ MHal_EMAC_timer_callback(value); ++ return; ++ } ++#endif ++ ++ spin_lock_irq (LocPtr->lock); ++ ret = MDev_EMAC_update_linkspeed(emac_dev); ++ ++ if (!netif_queue_stopped(emac_dev)) ++ { ++ ++ ++#ifdef TX_SW_QUEUE ++ { ++ int txIdleCount=MDev_EMAC_GetTXFIFOIdle(); ++ _MDev_EMAC_tx_clear_TX_SW_QUEUE(txIdleCount,emac_dev,TX_SW_QUEUE_IN_TIMER); ++ _MDev_EMAC_tx_read_TX_SW_QUEUE(txIdleCount,emac_dev,TX_SW_QUEUE_IN_TIMER); ++ } ++ ++#endif ++ } ++ spin_unlock_irq (LocPtr->lock); ++ ++ tx_bytes_per_timerbak = tx_bytes_per_timer; ++ tx_bytes_per_timer = 0; ++ ++ if (0 == ret) ++ { ++ if (!ThisBCE.connected) ++ { ++ ThisBCE.connected = 1; ++ netif_carrier_on(emac_dev); ++ netif_start_queue(emac_dev); ++ //EMAC_ERR("connected\n"); ++ } ++ ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ MDrv_GPIO_Set_High(g_emac_led_orange); ++ MDrv_GPIO_Set_High(g_emac_led_green); ++ } ++ ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ time_count = 0; ++ spin_lock_irq (LocPtr->lock); ++ phy_status_register = bmsr; ++ spin_unlock_irq (LocPtr->lock); ++ // Normally, time out sets 1 Sec. ++ Link_timer.expires = jiffies + gu32CheckLinkTime; ++ } ++ else //no link ++ { ++ if(ThisBCE.connected) { ++ ThisBCE.connected = 0; ++ } ++ ++ if(g_emac_led_orange!=-1 && g_emac_led_green!=-1) ++ { ++ MDrv_GPIO_Set_Low(g_emac_led_orange); ++ MDrv_GPIO_Set_Low(g_emac_led_green); ++ } ++ ++ // If disconnected is over 3 Sec, the real value of PHY's status register will report to application. ++ if(time_count > CONFIG_DISCONNECT_DELAY_S*(HZ/gu32CheckLinkTimeDis)) { ++ // Link status is latched, so read twice to get current value // ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ MHal_EMAC_read_phy (phyaddr, MII_BMSR, &bmsr); ++ ++ // Report to kernel. ++ if (netif_carrier_ok(emac_dev)) ++ netif_carrier_off(emac_dev); ++ if (!netif_queue_stopped(emac_dev)) ++ netif_stop_queue(emac_dev); ++ spin_lock_irq (LocPtr->lock); ++ phy_status_register = bmsr; ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(emac_dev); ++#endif ++ spin_unlock_irq (LocPtr->lock); ++ ThisBCE.connected = 0; ++ // Normally, time out is set 1 Sec. ++ Link_timer.expires = jiffies + gu32CheckLinkTime; ++ } ++ else// if(time_count <= CONFIG_DISCONNECT_DELAY_S*10) ++ { ++ time_count++; ++ // Time out is set 100ms. Quickly checks next phy status. ++ Link_timer.expires = jiffies + gu32CheckLinkTimeDis; ++ //EMAC_ERR("disconnect\n"); ++ } ++ } ++ add_timer(&Link_timer); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC MACADDR Setup ++//------------------------------------------------------------------------------------------------- ++ ++#define MACADDR_FORMAT "XX:XX:XX:XX:XX:XX" ++ ++static int __init macaddr_auto_config_setup(char *addrs) ++{ ++ if (strlen(addrs) == strlen(MACADDR_FORMAT) ++ && ':' == addrs[2] ++ && ':' == addrs[5] ++ && ':' == addrs[8] ++ && ':' == addrs[11] ++ && ':' == addrs[14] ++ ) ++ { ++ addrs[2] = '\0'; ++ addrs[5] = '\0'; ++ addrs[8] = '\0'; ++ addrs[11] = '\0'; ++ addrs[14] = '\0'; ++ ++ MY_MAC[0] = (u8)simple_strtoul(&(addrs[0]), NULL, 16); ++ MY_MAC[1] = (u8)simple_strtoul(&(addrs[3]), NULL, 16); ++ MY_MAC[2] = (u8)simple_strtoul(&(addrs[6]), NULL, 16); ++ MY_MAC[3] = (u8)simple_strtoul(&(addrs[9]), NULL, 16); ++ MY_MAC[4] = (u8)simple_strtoul(&(addrs[12]), NULL, 16); ++ MY_MAC[5] = (u8)simple_strtoul(&(addrs[15]), NULL, 16); ++ ++ /* set back to ':' or the environment variable would be destoried */ // REVIEW: this coding style is dangerous ++ addrs[2] = ':'; ++ addrs[5] = ':'; ++ addrs[8] = ':'; ++ addrs[11] = ':'; ++ addrs[14] = ':'; ++ } ++ ++ return 1; ++} ++ ++__setup("macaddr=", macaddr_auto_config_setup); ++ ++//------------------------------------------------------------------------------------------------- ++// EMAC init module ++//------------------------------------------------------------------------------------------------- ++static int MDev_EMAC_ScanPhyAddr(void) ++{ ++ unsigned char addr = 0; ++ u32 value = 0; ++ ++ MHal_EMAC_Write_JULIAN_0100(JULIAN_100_VAL); ++ ++ MHal_EMAC_enable_mdi(); ++ do ++ { ++ MHal_EMAC_read_phy(addr, MII_BMSR, &value); ++ if (0 != value && 0x0000FFFFUL != value) ++ { ++ ++ EMAC_DBG("[ PHY Addr:%d ] ==> :%x\n", addr, value); ++ break; ++ } ++ }while(++addr && addr < 32); ++ MHal_EMAC_disable_mdi(); ++ phyaddr = addr; ++ ++ if (phyaddr >= 32) ++ { ++ EMAC_ERR("Wrong PHY Addr and reset to 0\n"); ++ phyaddr = 0; ++ return -1; ++ } ++ return 0; ++} ++ ++static void Rtl_Patch(void) ++{ ++ u32 val; ++ ++ MHal_EMAC_read_phy(phyaddr, 25, &val); ++ MHal_EMAC_write_phy(phyaddr, 25, 0x400UL); ++ MHal_EMAC_read_phy(phyaddr, 25, &val); ++} ++ ++static void MDev_EMAC_Patch_PHY(void) ++{ ++ u32 val; ++ ++ MHal_EMAC_read_phy(phyaddr, 2, &val); ++ if (RTL_8210 == val) ++ Rtl_Patch(); ++} ++ ++#ifdef RX_ZERO_COPY ++/* ++static int dequeue_rx_buffer(struct EMAC_private *p, struct sk_buff **pskb) ++{ ++ //p->rx_next = (p->rx_next + 1) % RX_RING_SIZE; ++ p->rx_current_fill--; ++ *pskb = __skb_dequeue(&p->rx_list); ++ ++// if (gmac_debug) ++// GMAC_DBG("rx_next:%d rx_next_fill:%d rx_current_fill:%d\n",p->rx_next, p->rx_next_fill, p->rx_current_fill); ++ return p->rx_current_fill; ++} ++ ++static int fill_rx_ring(struct net_device *netdev) ++{ ++ struct EMAC_private0 *p = netdev_priv(netdev); ++ printk("%s :current fill:%d\n",__func__, p->rx_current_fill); ++ ++ while (p->rx_current_fill < RX_RING_SIZE) ++ { ++ struct sk_buff *skb; ++ if (!(skb = alloc_skb (SOFTWARE_DESC_LEN, GFP_ATOMIC))) { ++// GMAC_DBG("%s %d: alloc skb failed! RX current fill:%d\n",__func__,__LINE__, p->rx_current_fill); ++ break; ++ } ++ ++// skb_reserve(skb, NET_IP_ALIGN); ++ __skb_queue_tail(&p->rx_list, skb); ++ p->rx_current_fill++; ++ p->rx_next_fill = (p->rx_next_fill + 1) % RX_RING_SIZE; ++ } ++ ++// if (unlikely(gmac_debug)) ++// GMAC_DBG("%s Current fill:%d. rx next fill:%d\n",__func__, p->rx_current_fill, p->rx_next_fill); ++ printk("%s : RX current fill:%d\n",__func__, p->rx_current_fill); ++ ++ return p->rx_current_fill; ++} ++*/ ++#endif /*GMAC_RX_ZERO_COPY*/ ++ ++ ++static int MDev_EMAC_init(struct platform_device *pdev) ++{ ++ struct EMAC_private *LocPtr; ++ int ret; ++/* ++ if(MDrv_SYS_GetPowerStates()!= SYS_POWER_Supply_Full) ++ { ++ EMAC_DBG("Power state(%d) does not support ethernet\n",MDrv_SYS_GetPowerStates()); ++ //return -1; ++ } ++*/ ++ if(emac_dev) ++ return -1; ++ ++ emac_dev = alloc_etherdev(sizeof(*LocPtr)); ++ LocPtr = netdev_priv(emac_dev); ++ ++ if (!emac_dev) ++ { ++ EMAC_ERR( KERN_ERR "No EMAC dev mem!\n" ); ++ return -ENOMEM; ++ } ++#ifdef RX_ZERO_COPY ++ //skb_queue_head_init(&LocPtr->rx_list); ++ //LocPtr->rx_next = 0; ++ //LocPtr->rx_next_fill = 0; ++ //LocPtr->rx_current_fill = 0; ++ //fill_rx_ring(emac_dev); ++#endif ++#if defined (NEW_TX_QUEUE_128) ++ MHal_EMAC_enable_new_TXQUEUE(); ++#endif ++ ++#if TX_THROUGHPUT_TEST ++ printk("==========TX_THROUGHPUT_TEST==============="); ++ pseudo_packet = alloc_skb(SOFTWARE_DESC_LEN, GFP_ATOMIC); ++ memcpy(pseudo_packet->data, (void *)packet_content, sizeof(packet_content)); ++ pseudo_packet->len = sizeof(packet_content); ++#endif ++ ++#if RX_THROUGHPUT_TEST ++ printk("==========RX_THROUGHPUT_TEST==============="); ++ init_timer(&RX_timer); ++ ++ RX_timer.data = EMAC_RX_TMR; ++ RX_timer.function = RX_timer_callback; ++ RX_timer.expires = jiffies + 20*EMAC_CHECK_LINK_TIME; ++ add_timer(&RX_timer); ++#endif ++ ++ MHal_EMAC_Power_On_Clk(&pdev->dev); ++ ++ init_timer(&EMAC_timer); ++ init_timer(&Link_timer); ++ ++ EMAC_timer.data = EMAC_RX_TMR; ++ EMAC_timer.function = MDev_EMAC_timer_callback; ++ EMAC_timer.expires = jiffies; ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++ spin_lock_init (&emac_flow_ctl_lock); ++ spin_lock_irq(&emac_flow_ctl_lock); ++ eth_pause_cmd_enable = 0; ++ spin_unlock_irq(&emac_flow_ctl_lock); ++ ++ init_timer(&EMAC_flow_ctl_timer); ++ EMAC_flow_ctl_timer.data = EMAC_FLOW_CTL_TMR; ++ EMAC_flow_ctl_timer.expires = jiffies; ++ EMAC_flow_ctl_timer.function = MDev_EMAC_timer_callback; /* timer handler */ ++#endif ++ MHal_EMAC_Write_JULIAN_0100(JULIAN_100_VAL); ++ ++ if (0 > MDev_EMAC_ScanPhyAddr()) ++ goto end; ++ ++ MDev_EMAC_Patch_PHY(); ++ ++#ifdef MSTAR_EMAC_NAPI ++ netif_napi_add(emac_dev, &LocPtr->napi, MDev_EMAC_napi_poll, EMAC_NAPI_WEIGHT); ++#endif ++ ++ emac_dev->dev.of_node = pdev->dev.of_node; //pass of_node to MDev_EMAC_setup() ++ ++ if (MDev_EMAC_probe (emac_dev)) ++ return -1; ++ ++ ++ ret = register_netdev (emac_dev); ++ ++ if(!ret) ++ { ++ printk( KERN_ERR "[EMAC]Init EMAC success! (add delay in reset)\n" ); ++ return ret; ++ } ++ ++ ++ ++end: ++ free_netdev(emac_dev); ++ emac_dev = 0; ++ initstate = ETHERNET_TEST_INIT_FAIL; ++ EMAC_ERR( KERN_ERR "Init EMAC error!\n" ); ++ return -1; ++} ++//------------------------------------------------------------------------------------------------- ++// EMAC exit module ++//------------------------------------------------------------------------------------------------- ++static void MDev_EMAC_exit(void) ++{ ++ if (emac_dev) ++ { ++ #ifndef INT_JULIAN_D ++ del_timer(&EMAC_timer); ++ #endif ++ unregister_netdev(emac_dev); ++ free_netdev(emac_dev); ++ } ++#if defined (SOFTWARE_TX_FLOW_CONTROL) ++ del_timer(&EMAC_flow_ctl_timer); ++#endif ++} ++ ++static int mstar_emac_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct EMAC_private *LocPtr; ++ u32 uRegVal; ++ printk(KERN_INFO "mstar_emac_drv_suspend\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ ++ LocPtr = (struct EMAC_private*) netdev_priv(netdev); ++ LocPtr->ep_flag |= EP_FLAG_SUSPENDING; ++ //netif_stop_queue (netdev); ++ ++ ++ disable_irq(netdev->irq); ++ del_timer(&Link_timer); ++ ++ //MHal_EMAC_Power_On_Clk(dev->dev); ++ ++ //corresponds with resume call MDev_EMAC_open ++#ifdef MSTAR_EMAC_NAPI ++ napi_disable(&LocPtr->napi); ++#endif ++ ++ //Disable Receiver and Transmitter // ++ uRegVal = MHal_EMAC_Read_CTL(); ++ uRegVal &= ~(EMAC_TE | EMAC_RE); ++ MHal_EMAC_Write_CTL(uRegVal); ++ ++#ifdef TX_SW_QUEUE ++ //make sure that TX HW FIFO is empty ++ while(TX_FIFO_SIZE!=MDev_EMAC_GetTXFIFOIdle()); ++#endif ++ ++ // Disable PHY interrupt // ++ MHal_EMAC_disable_phyirq (); ++ ++ MHal_EMAC_Write_IDR(0xFFFFFFFF); ++ ++ ++ MDev_EMAC_SwReset(netdev); ++ MHal_EMAC_Power_Off_Clk(&dev->dev); ++#if defined(TX_SKB_PTR) ++#ifdef TX_SW_QUEUE ++ _MDev_EMAC_tx_reset_TX_SW_QUEUE(netdev); ++#endif ++#endif ++ ++ ++ return 0; ++} ++static int mstar_emac_drv_resume(struct platform_device *dev) ++{ ++ struct net_device *netdev=(struct net_device*)dev->dev.platform_data; ++ struct EMAC_private *LocPtr; ++ ++#ifndef RX_ZERO_COPY ++ phys_addr_t alloRAM_PA_BASE; ++ phys_addr_t alloRAM_SIZE; ++ MSYS_DMEM_INFO mem_info; ++ int ret; ++#endif ++ printk(KERN_INFO "mstar_emac_drv_resume\n"); ++ if(!netdev) ++ { ++ return -1; ++ } ++ LocPtr = (struct EMAC_private*) netdev_priv(netdev);; ++ LocPtr->ep_flag &= ~EP_FLAG_SUSPENDING; ++ ++ MHal_EMAC_Power_On_Clk(&dev->dev); ++ ++ MHal_EMAC_Write_JULIAN_0100(JULIAN_100_VAL); ++ ++ if (0 > MDev_EMAC_ScanPhyAddr()) ++ return -1; ++ ++ MDev_EMAC_Patch_PHY(); ++ ++#ifndef RX_ZERO_COPY ++ ++ strcpy(mem_info.name, "EMAC_BUFF"); ++ if((ret=msys_request_dmem(&mem_info))) ++ { ++ panic("unable to locate DMEM for alloRAM_PA_BASE!! error=%d\n",ret); ++ } ++ alloRAM_PA_BASE = mem_info.phys; ++ alloRAM_SIZE = mem_info.length; ++ ++ //Add Write Protect ++ MHal_EMAC_Write_Protect(alloRAM_PA_BASE - MIU0_BUS_BASE, alloRAM_SIZE); ++#endif ++ ++ ThisUVE.initedEMAC = 0; ++ MDev_EMAC_HW_init(); ++ ++ MDev_EMAC_update_mac_address (netdev); // Program ethernet address into MAC // ++ spin_lock_irq (LocPtr->lock); ++ MHal_EMAC_enable_mdi (); ++ ++ spin_unlock_irq (LocPtr->lock); ++ ++#ifdef CONFIG_MSTAR_HW_TX_CHECKSUM ++ retval = MHal_EMAC_Read_JULIAN_0104() | TX_CHECKSUM_ENABLE; ++ MHal_EMAC_Write_JULIAN_0104(retval); ++#endif ++ ++ enable_irq(netdev->irq); ++ if(LocPtr->ep_flag & EP_FLAG_OPEND) ++ { ++ if(0>MDev_EMAC_open(netdev)) ++ { ++ printk(KERN_WARNING "Driver Emac: open failed after resume\n"); ++ } ++ } ++ ++ return 0; ++} ++ ++static int mstar_emac_drv_probe(struct platform_device *pdev) ++{ ++ int retval=0; ++ unsigned int led_data; ++ ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-emac") ++ || pdev->id!=0) ++ { ++ retval = -ENXIO; ++ } ++ ++ retval = MDev_EMAC_init(pdev); ++ if(!retval) ++ { ++ pdev->dev.platform_data=emac_dev; ++ } ++ ++ ++ if(!of_property_read_u32(pdev->dev.of_node, "led-orange", &led_data)) ++ { ++ g_emac_led_orange = (unsigned char)led_data; ++ printk(KERN_ERR "[EMAC]Set emac_led_orange=%d\n",led_data); ++ } ++ ++ if(!of_property_read_u32(pdev->dev.of_node, "led-green", &led_data)) ++ { ++ g_emac_led_green = (unsigned char)led_data; ++ printk(KERN_ERR "[EMAC]Set emac_led_green=%d\n",led_data); ++ } ++ ++ if(g_emac_led_orange!=-1) ++ { ++ MDrv_GPIO_Pad_Set(g_emac_led_orange); ++ } ++ if(g_emac_led_green!=-1) ++ { ++ MDrv_GPIO_Pad_Set(g_emac_led_green); ++ } ++ ++ ++ return retval; ++} ++ ++static int mstar_emac_drv_remove(struct platform_device *pdev) ++{ ++ if( !(pdev->name) || strcmp(pdev->name,"Mstar-emac") ++ || pdev->id!=0) ++ { ++ return -1; ++ } ++ MDev_EMAC_exit(); ++ MHal_EMAC_Power_Off_Clk(&pdev->dev); ++ ++ pdev->dev.platform_data=NULL; ++ return 0; ++} ++ ++ ++ ++static struct platform_driver Mstar_emac_driver = { ++ .probe = mstar_emac_drv_probe, ++ .remove = mstar_emac_drv_remove, ++ .suspend = mstar_emac_drv_suspend, ++ .resume = mstar_emac_drv_resume, ++ ++ .driver = { ++ .name = "Mstar-emac", ++#if defined(CONFIG_OF) ++ .of_match_table = mstaremac_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ } ++}; ++ ++ ++ ++static int __init mstar_emac_drv_init_module(void) ++{ ++ int retval=0; ++ ++ emac_dev=NULL; ++ retval = platform_driver_register(&Mstar_emac_driver); ++ if (retval) ++ { ++ printk(KERN_INFO"Mstar_emac_driver register failed...\n"); ++ return retval; ++ } ++ ++ return retval; ++} ++ ++static void __exit mstar_emac_drv_exit_module(void) ++{ ++ platform_driver_unregister(&Mstar_emac_driver); ++ emac_dev=NULL; ++} ++ ++ ++ ++module_init(mstar_emac_drv_init_module); ++module_exit(mstar_emac_drv_exit_module); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("EMAC Ethernet driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/emac/mdrv_emac.h b/drivers/mstar/emac/mdrv_emac.h +new file mode 100644 +index 00000000..06a9a1ad +--- /dev/null ++++ b/drivers/mstar/emac/mdrv_emac.h +@@ -0,0 +1,309 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file EMAC.h ++/// @author MStar Semiconductor Inc. ++/// @brief EMAC Driver Interface ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h define start ++// ----------------------------------------------------------------------------- ++ ++#ifndef __DRV_EMAC_H_ ++#define __DRV_EMAC_H_ ++ ++#define EMAC_DBG(fmt, args...) //{printk("Mstar_emac: "); printk(fmt, ##args);} ++#define EMAC_ERR(fmt, args...) {printk("Mstar_emac: "); printk(fmt, ##args);} ++#define EMAC_INFO {printk("Line:%u\n", __LINE__);} ++#define EMAC_TODO(fmt, args...) {printk("[EMAC]%d TODO:", __LINE__); printk(fmt, ##args);} ++ ++#define MINOR_EMAC_NUM 1 ++#define MAJOR_EMAC_NUM 241 ++//------------------------------------------------------------------------------------------------- ++// Define Enable or Compiler Switches ++//------------------------------------------------------------------------------------------------- ++#define USE_TASK 1 // 1:Yes, 0:No ++#define EMAC_MTU (1524) ++ ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Constant definition ++//-------------------------------------------------------------------------------------------------- ++#if (!USE_TASK) // MEM_BASE_ADJUSTMENT ...................................... ++#define RAM_VA_BASE 0xA0000000UL ++#define RAM_PA_BASE 0x00000000UL ++#define RAM_VA_PA_OFFSET 0x00000000UL ++#define RX_BUFFER_BASE 0x00000000UL // ==0xA0000000 ~~ 0xA0004000 (Max: 16 KB) ++#define RBQP_BASE RX_BUFFER_SIZE//0x00004000 // ==0xA0004000 ~~ 0xA0005FFF for MAX 1024 descriptors ++#define TX_BUFFER_BASE (RX_BUFFER_SIZE+RBQP_SIZE)//0x00006000 // ==0xA0006000 ~~ ???????? ++#define TX_SKB_BASE TX_BUFFER_BASE+0x100UL//0x00006100 ++#define RX_FRAME_ADDR TX_SKB_BASE+0x600UL//0x00007000 // Software COPY&STORE one RX frame. Size is not defined. ++#else // The memory allocation for TASK. ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++phys_addr_t RAM_VA_BASE; //= 0x00000000; // After init, RAM_ADDR_BASE = EMAC_ABSO_MEM_BASE ++phys_addr_t RAM_PA_BASE; ++phys_addr_t RAM_VA_PA_OFFSET; ++phys_addr_t RBQP_BASE; //= RX_BUFFER_SIZE;//0x00004000; // IMPORTANT: lowest 13 bits as zero. ++#ifndef RX_ZERO_COPY ++phys_addr_t RX_BUFFER_BASE; //= 0x00000000; // IMPORTANT: lowest 14 bits as zero. ++//phys_addr_t TX_BUFFER_BASE; //= (RX_BUFFER_SIZE+RBQP_SIZE);//0x00006000; ++#endif ++phys_addr_t TX_SKB_BASE; //= (RX_BUFFER_SIZE+RBQP_SIZE+0x600);//0x00006100; ++ ++#endif //^MEM_BASE_ADJUSTMENT ............................................... ++ ++#define ETHERNET_TEST_NO_LINK 0x00000000UL ++#define ETHERNET_TEST_AUTO_NEGOTIATION 0x00000001UL ++#define ETHERNET_TEST_LINK_SUCCESS 0x00000002UL ++#define ETHERNET_TEST_RESET_STATE 0x00000003UL ++#define ETHERNET_TEST_SPEED_100M 0x00000004UL ++#define ETHERNET_TEST_DUPLEX_FULL 0x00000008UL ++#define ETHERNET_TEST_INIT_FAIL 0x00000010UL ++ ++#ifdef RX_ZERO_COPY ++//#define RX_RING_SIZE (RBQP_LENG*2) ++#endif ++ ++u8 MY_DEV[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15}; ++u8 MY_MAC[6] = { 0x00UL, 0x30UL, 0x1BUL, 0xBAUL, 0x02UL, 0xDBUL }; ++u8 PC_MAC[6] = { 0x00UL, 0x1AUL, 0x4BUL, 0x5CUL, 0x39UL, 0xDFUL }; ++u8 ETH_PAUSE_FRAME_DA_MAC[6] = { 0x01UL, 0x80UL, 0xC2UL, 0x00UL, 0x00UL, 0x01UL }; ++ ++#ifdef INT_JULIAN_D ++ u32 xoffsetValue, xReceiveNum; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++struct rbf_t ++{ ++ u32 addr; ++ u32 size; ++}; ++ ++struct recv_desc_bufs ++{ ++ struct rbf_t descriptors[MAX_RX_DESCR]; /* must be on sizeof (rbf_t) boundary */ ++ char recv_buf[RX_BUFFER_SIZE]; /* must be on MAX_RBUFF_SZ boundary */ ++}; ++ ++struct tx_ring ++{ ++ u8 used; ++ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ ++}; ++ ++struct skb_node ++{ ++ u32 queuesize; ++ struct sk_buff *skb; ++ struct skb_node *next; ++ struct skb_node *prev; ++}; ++ ++#define EP_FLAG_OPEND 0X00000001UL ++#define EP_FLAG_SUSPENDING 0X00000002UL ++ ++ ++struct EMAC_private ++{ ++ struct net_device_stats stats; ++ struct mii_if_info mii; /* ethtool support */ ++ ++ /* PHY */ ++ unsigned long phy_type; /* type of PHY (PHY_ID) */ ++ spinlock_t *lock; /* lock for MDI interface */ ++ short phy_media; /* media interface type */ ++ ++ /* Transmit */ ++#if defined(TX_SKB_PTR) ++#if defined(TX_SW_QUEUE) ++ struct tx_ring tx_swq[TX_SW_QUEUE_SIZE]; ++ unsigned int tx_rdidx; /* TX_SW_QUEUE read to hw index */ ++ unsigned int tx_wridx; /* TX_SW_QUEUE write index */ ++ unsigned int tx_clidx; /* TX_SW_QUEUE clear index */ ++ ++ unsigned int tx_rdwrp; /* TX_SW_QUEUE read to hw index wrap*/ ++ unsigned int tx_wrwrp; /* TX_SW_QUEUE write index wrap*/ ++ unsigned int tx_clwrp; /* TX_SW_QUEUE clear index wrap */ ++ unsigned int tx_swq_full_cnt; /* TX_SW_QUEUE full stopped count*/ ++#else ++ struct tx_ring tx_swq[TX_RING_SIZE]; ++ //unsigned int tx_rdidx; ++ unsigned int tx_wridx; ++#endif ++#endif ++ unsigned int irqcnt; ++ unsigned int tx_irqcnt; ++ ++#ifdef RX_ZERO_COPY ++// struct rx_ring rx_ring_list[RX_RING_SIZE]; ++ /* RX variables only touched in napi_poll. No locking necessary. */ ++ //u64 *rx_ring; ++ //dma_addr_t rx_ring_handle; ++ //unsigned int rx_next; ++ //unsigned int rx_next_fill; ++ //unsigned int rx_current_fill; ++ //struct sk_buff_head rx_list; ++#endif ++ ++ ++ struct sk_buff *skb; /* holds skb until xmit interrupt completes */ ++ dma_addr_t skb_physaddr; /* phys addr from pci_map_single */ ++ int skb_length; /* saved skb length for pci_unmap_single */ ++ unsigned char retx_count; /* resend count of tx */ ++ unsigned int txpkt; /* previous tx packet pointer */ ++ ++ /* Receive */ ++ int rxBuffIndex; /* index into receive descriptor list */ ++ struct recv_desc_bufs *dlist; /* descriptor list address */ ++ //struct recv_desc_bufs *dlist_phys; /* descriptor list physical address */ ++ ++ /* Suspend and resume */ ++ unsigned long ep_flag; ++ ++ struct net_device *dev; ++ ++ /* Bottom task */ ++#if defined ISR_BOTTOM_HALF ++ struct work_struct rx_task; ++ struct work_struct tx_task; ++#endif ++ /* Tx software queue */ ++ struct skb_node *tx_queue_head; ++ struct skb_node *tx_queue_tail; ++ unsigned int xReceiveFlag; ++ ++ struct mutex mutex; ++ struct device *mstar_class_emac_device; ++#ifdef MSTAR_EMAC_NAPI ++ struct napi_struct napi; ++#endif ++}; ++ ++#define ROUND_SUP_4(x) (((x)+3)&~3) ++ ++struct eth_drv_sgX ++{ ++ u32 buf; ++ u32 len; ++}; ++ ++struct _BasicConfigEMAC ++{ ++ u8 connected; // 0:No, 1:Yes <== (20070515) Wait for Julian's reply ++ u8 speed; // 10:10Mbps, 100:100Mbps ++ // ETH_CTL Register: ++ u8 wes; // 0:Disable, 1:Enable (WR_ENABLE_STATISTICS_REGS) ++ // ETH_CFG Register: ++ u8 duplex; // 1:Half-duplex, 2:Full-duplex ++ u8 cam; // 0:No CAM, 1:Yes ++ u8 rcv_bcast; // 0:No, 1:Yes ++ u8 rlf; // 0:No, 1:Yes receive long frame(1522) ++ // MAC Address: ++ u8 sa1[6]; // Specific Addr 1 (MAC Address) ++ u8 sa2[6]; // Specific Addr 2 ++ u8 sa3[6]; // Specific Addr 3 ++ u8 sa4[6]; // Specific Addr 4 ++}; ++typedef struct _BasicConfigEMAC BasicConfigEMAC; ++ ++struct _UtilityVarsEMAC ++{ ++ u32 cntChkINTCounter; ++ u32 readIdxRBQP; // Reset = 0x00000000 ++ u32 rxOneFrameAddr; // Reset = 0x00000000 (Store the Addr of "ReadONE_RX_Frame") ++ // Statistics Counters : (accumulated) ++ u32 cntREG_ETH_FRA; ++ u32 cntREG_ETH_SCOL; ++ u32 cntREG_ETH_MCOL; ++ u32 cntREG_ETH_OK; ++ u32 cntREG_ETH_SEQE; ++ u32 cntREG_ETH_ALE; ++ u32 cntREG_ETH_DTE; ++ u32 cntREG_ETH_LCOL; ++ u32 cntREG_ETH_ECOL; ++ u32 cntREG_ETH_TUE; ++ u32 cntREG_ETH_CSE; ++ u32 cntREG_ETH_RE; ++ u32 cntREG_ETH_ROVR; ++ u32 cntREG_ETH_SE; ++ u32 cntREG_ETH_ELR; ++ u32 cntREG_ETH_RJB; ++ u32 cntREG_ETH_USF; ++ u32 cntREG_ETH_SQEE; ++ // Interrupt Counter : ++ u32 cntHRESP; // Reset = 0x0000 ++ u32 cntROVR; // Reset = 0x0000 ++ u32 cntLINK; // Reset = 0x0000 ++ u32 cntTIDLE; // Reset = 0x0000 ++ u32 cntTCOM; // Reset = 0x0000 ++ u32 cntTBRE; // Reset = 0x0000 ++ u32 cntRTRY; // Reset = 0x0000 ++ u32 cntTUND; // Reset = 0x0000 ++ u32 cntTOVR; // Reset = 0x0000 ++ u32 cntRBNA; // Reset = 0x0000 ++ u32 cntRCOM; // Reset = 0x0000 ++ u32 cntDONE; // Reset = 0x0000 ++ // Flags: ++ u8 flagMacTxPermit; // 0:No,1:Permitted. Initialize as "permitted" ++ u8 flagISR_INT_RCOM; ++ u8 flagISR_INT_RBNA; ++ u8 flagISR_INT_DONE; ++ u8 flagPowerOn; // 0:Poweroff, 1:Poweron ++ u8 initedEMAC; // 0:Not initialized, 1:Initialized. ++ u8 flagRBNA; ++ // Misc Counter: ++ u32 cntRxFrames; // Reset = 0x00000000 (Counter of RX frames,no matter it's me or not) ++ u32 cntReadONE_RX; // Counter for ReadONE_RX_Frame ++ u32 cntCase20070806; ++ u32 cntChkToTransmit; ++ // Misc Variables: ++ u32 mainThreadTasks; // (20071029_CHARLES) b0=Poweroff,b1=Poweron ++}; ++typedef struct _UtilityVarsEMAC UtilityVarsEMAC; ++ ++BasicConfigEMAC ThisBCE; ++UtilityVarsEMAC ThisUVE; ++ ++typedef volatile unsigned int EMAC_REG; ++ ++struct sk_buff *Tx_SkbAddr; ++ ++ ++#ifdef TESTING ++ extern void EMAC_TEST_All(void); ++#endif ++ ++struct sk_buff *rx_skb[MAX_RX_DESCR]; ++u32 rx_abso_addr[MAX_RX_DESCR]; ++struct sk_buff * rx_skb_dummy; ++u32 rx_abso_addr_dummy; ++#endif ++// ----------------------------------------------------------------------------- ++// Linux EMAC.h End ++// ----------------------------------------------------------------------------- ++ ++ +diff --git a/drivers/mstar/emac/policy.txt b/drivers/mstar/emac/policy.txt +new file mode 100644 +index 00000000..f06bedd4 +--- /dev/null ++++ b/drivers/mstar/emac/policy.txt +@@ -0,0 +1,45 @@ ++//////////////////////////////////////////// ++// What kind of test before release ++//////////////////////////////////////////// ++ ++A. Auto detection for different speed and duplex ++ 1. 10Mb Full ++ 2. 10Mb Half ++ 3. 100Mb Full ++ 4. 100Mb Half ++ ++B. Data Transfer Rate with different speed and duplex ++ 1. 10Mb Half ++ 1.1 64-byte icmp packet: greater than 7.6Mb ++ 1.2 128-byte icmp packet: greater than 7.6Mb ++ 1.3 256-byte icmp packet: greater than 7.6Mb ++ 1.4 512-byte icmp packet: greater than 7.6Mb ++ 1.5 1024-byte icmp packet: greater than 7.6Mb ++ 1.6 1280-byte icmp packet: greater than 7.6Mb ++ 1.7 1514-byte icmp packet: greater than 7.6Mb ++ 2. 10Mb Full ++ 2.1 64-byte icmp packet: greater than 7.6Mb ++ 2.2 128-byte icmp packet: greater than 7.6Mb ++ 2.3 256-byte icmp packet: greater than 7.6Mb ++ 2.4 512-byte icmp packet: greater than 7.6Mb ++ 2.5 1024-byte icmp packet: greater than 7.6Mb ++ 2.6 1280-byte icmp packet: greater than 7.6Mb ++ 2.7 1514-byte icmp packet: greater than 7.6Mb ++ 3. 100Mb Half ++ 3.1 64-byte icmp packet: greater than 7.6Mb ++ 3.2 128-byte icmp packet: greater than 10Mb ++ 3.3 256-byte icmp packet: greater than 15Mb ++ 3.4 512-byte icmp packet: greater than 30Mb ++ 3.5 1024-byte icmp packet: greater than 50Mb ++ 3.6 1280-byte icmp packet: greater than 55Mb ++ 3.7 1514-byte icmp packet: greater than 60Mb ++ 4. 100Mb Full ++ 4.1 64-byte icmp packet: greater than 7.6Mb ++ 4.2 128-byte icmp packet: greater than 10Mb ++ 4.3 256-byte icmp packet: greater than 15Mb ++ 4.4 512-byte icmp packet: greater than 30Mb ++ 4.5 1024-byte icmp packet: greater than 50Mb ++ 4.6 1280-byte icmp packet: greater than 55Mb ++ 4.7 1514-byte icmp packet: greater than 60Mb ++ ++ +\ No newline at end of file +diff --git a/drivers/mstar/emmc/Kconfig b/drivers/mstar/emmc/Kconfig +new file mode 100644 +index 00000000..01ca9e3b +--- /dev/null ++++ b/drivers/mstar/emmc/Kconfig +@@ -0,0 +1,20 @@ ++config MS_EMMC ++ tristate "EMMC driver" ++ depends on MMC ++ help ++ To enable MSTAR EMMC driver. ++ ++config MS_EMMC_CEDRIC ++ tristate "EMMC support for Cedric" ++ depends on MS_EMMC ++ depends on ARCH_CEDRIC ++ ++ ++config MS_EMMC_CHICAGO ++ tristate "EMMC support for Chicago" ++ depends on MS_EMMC ++ depends on ARCH_CHICAGO ++ ++config MS_EMMC_UNIFY_DRIVER ++ bool "UNIFY EMMC DRIVER" ++ depends on MS_EMMC +diff --git a/drivers/mstar/emmc/Makefile b/drivers/mstar/emmc/Makefile +new file mode 100644 +index 00000000..341360a6 +--- /dev/null ++++ b/drivers/mstar/emmc/Makefile +@@ -0,0 +1,3 @@ ++obj-$(CONFIG_MS_EMMC_CEDRIC) += cedric/ ++obj-$(CONFIG_MS_EMMC_CHICAGO) += chicago/ ++obj-$(CONFIG_MS_EMMC_UNIFY_DRIVER) += unify_driver/ +diff --git a/drivers/mstar/emmc/cedric/Makefile b/drivers/mstar/emmc/cedric/Makefile +new file mode 100644 +index 00000000..123eed83 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/Makefile +@@ -0,0 +1,23 @@ ++MS_ARCH_NAME=cedric ++EXTRA_CFLAGS += -Idrivers/mstar/include ++# ++# Makefile for MStar eMMC host drivers. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/$(MS_ARCH_NAME)/eMMCDrv/inc/api/ ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/$(MS_ARCH_NAME)/eMMCDrv/inc/common/ ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/$(MS_ARCH_NAME)/eMMCDrv/inc/config/ ++EXTRA_CFLAGS += -Werror ++ ++# specific options ++#EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++ ++obj-$(CONFIG_MS_EMMC_CEDRIC) += kdrv_emmc.o ++ ++kdrv_emmc-y := mstar_mci.o \ ++ eMMCDrv/src/api/eMMC_prg.o \ ++ eMMCDrv/src/common/eMMC_hal.o \ ++ eMMCDrv/src/common/eMMC_utl.o \ ++ eMMCDrv/src/config/eMMC_platform.o \ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/api/drv_eMMC.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/api/drv_eMMC.h +new file mode 100644 +index 00000000..1b015560 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/api/drv_eMMC.h +@@ -0,0 +1,214 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef __DRV_eMMC_H__ ++#define __DRV_eMMC_H__ ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++/*=============================================================*/ ++// Include files ++/*=============================================================*/ ++#include "eMMC_config.h" ++ ++/*=============================================================*/ ++// Extern definition ++/*=============================================================*/ ++typedef struct _eMMC_INFO ++{ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ ++ U16 u16_ECCCodeByteCnt; ++ U16 u16_PageSectorCnt; ++ U8 u8_WordMode; ++ ++} eMMC_INFO_t; ++ ++typedef struct _eMMC_CIS { ++ ++ U8 au8_eMMC_nni[512]; ++ U8 au8_eMMC_pni[512]; ++ ++} eMMC_CIS_t; ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Variable definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++extern U32 eMMC_Init(void); ++extern U32 eMMC_Init_Device(void); ++extern U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt); ++//-------------------------------------------- ++// CAUTION: u32_DataByteCnt has to be 512B x n ++//-------------------------------------------- ++extern U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++//-------------------------------------------- ++extern U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID); ++extern U32 eMMC_GetDevInfo(eMMC_INFO_t *peMMCInfo_t); ++ ++extern U32 eMMC_CheckCIS(eMMC_CIS_t *ptCISData); ++extern U32 eMMC_WriteCIS(eMMC_CIS_t *ptCISData); ++extern U32 eMMC_ReadCIS(eMMC_CIS_t *ptCISData); ++ ++extern U32 eMMC_WritePartitionInfo(U8 *pu8_Data, U32 u32_ByteCnt); ++extern U32 eMMC_ReadPartitionInfo(U8 *pu8_Data); ++extern U32 eMMC_DumpPartitionInfo(void); ++ ++extern U32 eMMC_WritePartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartPhySector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx); ++extern U32 eMMC_ReadPartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartPhySector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx); ++extern U32 eMMC_GetPartitionCapacity (U16 u16_PartType, ++ U32 *pu32_Cap); ++extern U32 eMMC_ErasePartition(U16 u16_PartType); ++extern U32 eMMC_EraseAllPartitions(void); ++extern U32 eMMC_EraseAll(void); ++extern U32 eMMC_FATAutoSize(void); ++ ++extern U32 eMMC_GetExtCSD(U8* pu8_Ext_CSD); ++extern U32 eMMC_SetExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++ ++/*=============================================================*/ ++// internal function definition ++/*=============================================================*/ ++extern U32 eMMC_ReadBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo); ++extern U32 eMMC_CheckIfReady(void); ++extern void eMMC_ResetReadyFlag(void); ++extern void eMMC_DumpDriverStatus(void); ++extern U32 eMMC_FCIE_BuildDDRTimingTable(void); ++ ++//-------------------------------------------- ++ //#if defined(eMMC_DRV_G2P_UBOOT) && eMMC_DRV_G2P_UBOOT ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++extern U32 eMMC_SearchDevNodeStartSector(void); ++ #endif ++//-------------------------------------------- ++ ++#endif //__DRV_eMMC_H__ ++ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC.h +new file mode 100644 +index 00000000..b053fb53 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC.h +@@ -0,0 +1,354 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef eMMC_DRIVER_H ++#define eMMC_DRIVER_H ++ ++ ++//=========================================================== ++// debug macro ++//=========================================================== ++ ++ ++//===================================================================================== ++#include "eMMC_config.h" // [CAUTION]: edit eMMC_config.h for your platform ++//===================================================================================== ++#include "eMMC_err_codes.h" ++ ++ ++//=========================================================== ++// macro for Spec. ++//=========================================================== ++#define ADDRESSING_MODE_BYTE 1 // 1 byte ++#define ADDRESSING_MODE_SECTOR 2 // 512 bytes ++#define ADDRESSING_MODE_4KB 3 // 4KB bytes ++ ++#define eMMC_SPEED_OLD 0 ++#define eMMC_SPEED_HIGH 1 ++#define eMMC_SPEED_HS200 2 ++ ++#define eMMC_FLAG_TRIM BIT0 ++#define eMMC_FLAG_HPI_CMD12 BIT1 ++#define eMMC_FLAG_HPI_CMD13 BIT2 ++ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++#define eMMC_SECTOR_512BYTE 0x200 ++#define eMMC_SECTOR_512BYTE_BITS 9 ++#define eMMC_SECTOR_512BYTE_MASK (eMMC_SECTOR_512BYTE-1) ++ ++#define eMMC_SECTOR_BUF_16KB (eMMC_SECTOR_512BYTE * 0x20) ++ ++#define eMMC_SECTOR_BYTECNT eMMC_SECTOR_512BYTE ++#define eMMC_SECTOR_BYTECNT_BITS eMMC_SECTOR_512BYTE_BITS ++//------------------------------------------------------- ++ ++#define eMMC_ExtCSD_SetBit 1 ++#define eMMC_ExtCSD_ClrBit 2 ++#define eMMC_ExtCSD_WByte 3 ++ ++#define eMMC_CMD_BYTE_CNT 5 ++#define eMMC_R1_BYTE_CNT 5 ++#define eMMC_R1b_BYTE_CNT 5 ++#define eMMC_R2_BYTE_CNT 16 ++#define eMMC_R3_BYTE_CNT 5 ++#define eMMC_R4_BYTE_CNT 5 ++#define eMMC_R5_BYTE_CNT 5 ++#define eMMC_MAX_RSP_BYTE_CNT eMMC_R2_BYTE_CNT ++ ++//=========================================================== ++// Partition Info parameters ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_NNI { ++ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 au8_padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ U8 u8_PairPageMapLoc; ++ U8 u8_PairPageMapType; ++ ++} eMMC_PACK1 eMMC_NNI_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PARTITION_RECORD { ++ ++ U16 u16_StartBlk; // the start block index, reserved for UNFD internal use. ++ U16 u16_BlkCnt; // project team defined ++ U16 u16_PartType; // project team defined, e.g. eMMC_PART_XXX_0 ++ U16 u16_BackupBlkCnt; // reserved good blocks count for backup, UNFD internal use. ++ // e.g. u16BackupBlkCnt = u16BlkCnt * 0.03 + 2 ++} eMMC_PACK1 eMMC_PARTITION_RECORD_t, *P_eMMC_PARTITION_RECORD_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PNI { ++ ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U16 u16_PartCnt; ++ U16 u16_UnitByteCnt; ++ eMMC_PARTITION_RECORD_t records[]; ++ ++} eMMC_PACK1 eMMC_PNI_t; ++ ++ ++// Logical Disk Info ++typedef struct _eMMC_DISK_INFO { ++ ++ U32 u32_StartSector; ++ U32 u32_SectorCnt; ++ ++} eMMC_DISK_INFO_t, *P_eMMC_DISK_INFO_t; ++ ++ ++//=========================================================== ++// internal data Sector Address ++//=========================================================== ++#define eMMC_ID_BYTE_CNT 15 ++#define eMMC_ID_FROM_CID_BYTE_CNT 10 ++#define eMMC_ID_DEFAULT_BYTE_CNT 11 // last byte means n GB ++ ++ ++//=========================================================== ++// DDR Timing Table ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_PARAM { ++ ++ U8 u8_DQS, u8_Cell; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_PARAM_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_WINDOW { ++ ++ U8 u8_Cnt; ++ // DQS uses index, not reg value (see code) ++ eMMC_FCIE_DDRT_PARAM_t aParam[2]; ++ // now G2P is 4 ++ U8 au8_DQSTryCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)+1]; ++ U8 au8_DQSValidCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)+1]; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_WINDOW_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_SET { ++ ++ U16 u16_Clk; ++ eMMC_FCIE_DDRT_PARAM_t Param; // register values ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_SET_t; ++ ++ ++#define eMMC_FCIE_DDRT_SET_CNT 12 ++#define eMMC_DDRT_SET_MAX 0 ++#define eMMC_DDRT_SET_NEXT 1 ++#define eMMC_DDRT_SET_MIN 2 ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_TABLE { ++ ++ U8 u8_SetCnt, u8_CurSetIdx; ++ eMMC_FCIE_DDRT_SET_t Set[eMMC_FCIE_DDRT_SET_CNT]; // 0:Max, 1:Next, 2:Min ++ ++ U32 u32_ChkSum; // put in the last ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_TABLE_t; ++ ++ ++//=========================================================== ++// driver structures ++//=========================================================== ++// driver flag ++#define DRV_FLAG_INIT_DONE BIT0 // include eMMC identify done ++ ++#define DRV_FLAG_GET_PART_INFO BIT1 ++#define DRV_FLAG_RSP_WAIT_D0H BIT2 // currently only R1b ++#define DRV_FLAG_DDR_MODE BIT3 ++#define DRV_FLAG_DDR_TUNING BIT4 ++ ++#define DRV_FLAG_SPEED_MASK (BIT5|BIT6) ++#define DRV_FLAG_SPEED_HIGH BIT5 ++#define DRV_FLAG_SPEED_HS200 BIT6 ++ ++#define DRV_FLAG_TESTING BIT7 ++ ++#define DRV_FLAG_RSPFROMRAM_SAVE BIT10 ++#define DRV_FLAG_ERROR_RETRY BIT11 ++ ++ ++typedef struct _eMMC_DRIVER ++{ ++ U32 u32_ChkSum; // [8th ~ last-512] bytes ++ U8 au8_Sig[4]; // 'e','M','M','C' ++ ++ // ---------------------------------------- ++ // FCIE ++ // ---------------------------------------- ++ U16 u16_RCA; ++ U32 u32_DrvFlag, u32_LastErrCode; ++ U8 au8_Rsp[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CSD[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CID[eMMC_MAX_RSP_BYTE_CNT]; ++ U16 u16_Reg10_Mode; ++ U32 u32_ClkKHz; ++ U16 u16_ClkRegVal, u8_PadType; ++ eMMC_FCIE_DDRT_TABLE_t DDRTable; ++ ++ // ---------------------------------------- ++ // eMMC ++ // ---------------------------------------- ++ // CSD ++ U8 u8_SPEC_VERS; ++ U8 u8_R_BL_LEN, u8_W_BL_LEN; // supported max blk len ++ U16 u16_C_SIZE; ++ U8 u8_TAAC, u8_NSAC, u8_Tran_Speed; ++ U8 u8_C_SIZE_MULT; ++ U8 u8_ERASE_GRP_SIZE, u8_ERASE_GRP_MULT; ++ U8 u8_R2W_FACTOR; ++ ++ U8 u8_IfSectorMode; ++ U32 u32_eMMCFlag; ++ U32 u32_EraseUnitSize; ++ ++ // ExtCSD ++ U32 u32_SEC_COUNT; ++ U32 u32_BOOT_SEC_COUNT; ++ U8 u8_BUS_WIDTH, u8_ErasedMemContent; ++ U16 u16_ReliableWBlkCnt; ++ ++ // ---------------------------------------- ++ // CIS ++ // ---------------------------------------- ++ // nni ++ U8 u8_IDByteCnt, au8_ID[eMMC_ID_BYTE_CNT]; ++ U8 au8_Vendor[16], au8_PartNumber[16]; ++ ++ // pni ++ U32 au32_Pad[2]; // don't move ++ ++ U32 u32_PartDevNodeStartSector; ++ U16 u16_PartDevNodeSectorCnt; ++ U32 u32_FATSectorCnt; ++ ++ // ---------------------- ++ #if eMMC_RSP_FROM_RAM ++ // rsp from ram ++ U8 au8_AllRsp[eMMC_SECTOR_512BYTE]; // last 4 bytes are CRC ++ #endif ++ ++} eMMC_DRIVER, *P_eMMC_DRIVER; ++ ++ ++extern eMMC_DRIVER g_eMMCDrv; ++ ++//=========================================================== ++// exposed APIs ++//=========================================================== ++#include "drv_eMMC.h" ++ ++//=========================================================== ++// internal used functions ++//=========================================================== ++#include "eMMC_utl.h" ++#include "eMMC_hal.h" ++ ++extern U32 eMMC_IPVerify_Main(void); ++extern U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void); ++extern void eMMCTest_DownCount(U32 u32_Sec); ++extern U32 eMMC_IPVerify_Performance(void); ++extern U32 eMMCTest_BlkWRC_ProbeDDR(U32 u32_eMMC_Addr); ++extern U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt); ++extern U32 eMMC_BootMode(void); ++extern void eMMC_Prepare_Power_Saving_Mode_Queue(void); ++ ++#endif // eMMC_DRIVER_H ++ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_err_codes.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_err_codes.h +new file mode 100644 +index 00000000..e3ff49c6 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_err_codes.h +@@ -0,0 +1,199 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_ERR_CODES_H__ ++#define __eMMC_ERR_CODES_H__ ++//=========================================================== ++// device status (R1, R1b) ++//=========================================================== ++#define eMMC_R1_ADDRESS_OUT_OF_RANGE BIT31 ++#define eMMC_R1_ADDRESS_MISALIGN BIT30 ++#define eMMC_R1_BLOCK_LEN_ERROR BIT29 ++#define eMMC_R1_ERASE_SEQ_ERROR BIT28 ++#define eMMC_R1_ERASE_PARAM BIT27 ++#define eMMC_R1_WP_VIOLATION BIT26 ++#define eMMC_R1_DEVICE_IS_LOCKED BIT25 ++#define eMMC_R1_LOCK_UNLOCK_FAILED BIT24 ++#define eMMC_R1_COM_CRC_ERROR BIT23 ++#define eMMC_R1_ILLEGAL_COMMAND BIT22 ++#define eMMC_R1_DEVICE_ECC_FAILED BIT21 ++#define eMMC_R1_CC_ERROR BIT20 ++#define eMMC_R1_ERROR BIT19 ++#define eMMC_R1_CID_CSD_OVERWRITE BIT16 ++#define eMMC_R1_WP_ERASE_SKIP BIT15 ++#define eMMC_R1_ERASE_RESET BIT13 ++#define eMMC_R1_CURRENT_STATE (BIT12|BIT11|BIT10|BIT9) ++#define eMMC_R1_READY_FOR_DATA BIT8 ++#define eMMC_R1_SWITCH_ERROR BIT7 ++#define eMMC_R1_EXCEPTION_EVENT BIT6 ++#define eMMC_R1_APP_CMD BIT5 ++ ++#define eMMC_ERR_R1_31_24 (eMMC_R1_ADDRESS_OUT_OF_RANGE| \ ++ eMMC_R1_ADDRESS_MISALIGN| \ ++ eMMC_R1_BLOCK_LEN_ERROR| \ ++ eMMC_R1_ERASE_SEQ_ERROR| \ ++ eMMC_R1_ERASE_PARAM| \ ++ eMMC_R1_WP_VIOLATION| \ ++ eMMC_R1_LOCK_UNLOCK_FAILED) ++#define eMMC_ERR_R1_23_16 (eMMC_R1_COM_CRC_ERROR| \ ++ eMMC_R1_ILLEGAL_COMMAND| \ ++ eMMC_R1_DEVICE_ECC_FAILED| \ ++ eMMC_R1_CC_ERROR| \ ++ eMMC_R1_ERROR| \ ++ eMMC_R1_CID_CSD_OVERWRITE) ++#define eMMC_ERR_R1_15_8 (eMMC_R1_WP_ERASE_SKIP| \ ++ eMMC_R1_ERASE_RESET) ++#define eMMC_ERR_R1_7_0 (eMMC_R1_SWITCH_ERROR) ++#define eMMC_ERR_R1_31_0 (eMMC_ERR_R1_31_24|eMMC_ERR_R1_23_16|eMMC_ERR_R1_15_8|eMMC_ERR_R1_7_0) ++#define eMMC_ERR_R1_NEED_RETRY (eMMC_R1_COM_CRC_ERROR|eMMC_R1_DEVICE_ECC_FAILED|eMMC_R1_CC_ERROR|eMMC_R1_ERROR|eMMC_R1_SWITCH_ERROR) ++ ++//=========================================================== ++// driver error codes ++//=========================================================== ++#define eMMC_ST_SUCCESS 0 ++ ++#define eMMC_ST_ERR_MEM_CORRUPT (0x0001 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_ALIGN (0x0002 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_PACKED (0x0003 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DATA_MISMATCH (0x0004 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAIT_REG0 (0x0005 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY (0x0006 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_MIULASTDONE (0x0007 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITD0HIGH (0x0008 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_CARDDMAEND (0x0009 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT (0x000A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_STS_ERR (0x000B | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_BIST_FAIL (0x0010 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DEBUG_MODE (0x0011 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_CLK (0x0012 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARAMETER (0x0013 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_INIT (0x0014 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INVALID_PARAM (0x0015 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARTITION_CHKSUM (0x0016 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PART_INFO (0x0017 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PARTITION (0x0018 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_OK_DDR_PARAM (0x0019 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SAVE_DDRT_FAIL (0x001A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_CHKSUM (0x001B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_NONA (0x001C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI (0x001D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI (0x001E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI_NONA (0x001F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI_NONA (0x0020 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SDR_DETECT_DDR (0x0021 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_CIS (0x0022 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_eMMC_PLATFROM (0x0023 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_RIU (0x0024 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INT_TO (0x0025 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_UNKNOWN_CLK (0x0026 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_BUILD_DDRT (0x0027 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_RSP_IN_RAM (0x0028 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_SLOWER_CLK (0x0029 | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_CMD1 (0x0A00 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD1_DEV_NOT_RDY (0x0A01 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD2 (0x0A02 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD3_CMD7 (0x0A03 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_31_24 (0x0A04 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_23_16 (0x0A05 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_15_8 (0x0A06 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_7_0 (0x0A07 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_CIFD (0x0A08 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_MIU (0x0A09 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_CIFD (0x0A0A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_MIU (0x0A0B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD18 (0x0A0C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6 (0x0A0D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD13 (0x0A0E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD12 (0x0A0F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD (0x0A10 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H (0x0A11 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_CHK_R1 (0x0A12 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU (0x0A13 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_WAIT_D0H (0x0A14 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_CHK_R1 (0x0A15 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25 (0x0A16 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_WAIT_D0H (0x0A17 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_CHK_R1 (0x0A18 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD9 (0x0A19 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SEC_UPFW_TO (0x0A20 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD16 (0x0A21 | eMMC_ST_PLAT) ++ ++ ++ ++#endif /* __eMMC_ERR_CODES_H__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_hal.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_hal.h +new file mode 100644 +index 00000000..bfa3ab11 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_hal.h +@@ -0,0 +1,162 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_HAL_H__ ++#define __eMMC_HAL_H__ ++ ++#include "eMMC.h" ++ ++extern U32 eMMC_FCIE_WaitEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_PollingEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir); ++extern void eMMC_FCIE_DumpDebugBus(void); ++extern void eMMC_FCIE_DumpRegisters(void); ++extern void eMMC_FCIE_CheckResetDone(void); ++extern U32 eMMC_FCIE_Reset(void); ++extern U32 eMMC_FCIE_Init(void); ++extern void eMMC_FCIE_ErrHandler_Stop(void); ++extern U32 eMMC_FCIE_ErrHandler_Retry(void); ++extern void eMMC_FCIE_ErrHandler_RestoreClk(void); ++extern void eMMC_FCIE_ErrHandler_ReInit(void); ++extern U32 eMMC_FCIE_SendCmd(U16 u16_Mode, U16 u16_Ctrl, U32 u32_Arg, U8 u8_CmdIdx, U8 u8_RspByteCnt); ++extern void eMMC_FCIE_ClearEvents(void); ++extern void eMMC_FCIE_ClearEvents_Reg0(void); ++extern U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us); ++extern U32 eMMC_FCIE_WaitD0High(U32 u32_us); ++extern void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_GetCIFD(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_SetDDRTimingReg(U8 u8_DQS, U8 u8_DelaySel); ++extern U32 eMMC_FCIE_EnableDDRMode(void); ++extern U32 eMMC_FCIE_EnableDDRMode_Ex(void); ++extern U32 eMMC_FCIE_EnableSDRMode(void); ++extern U32 eMMC_FCIE_DetectDDRTiming(void); ++extern void eMMC_FCIE_ApplyDDRTSet(U8 u8_DDRTIdx); ++extern void eMMC_DumpDDRTTable(void); ++extern U32 eMMC_LoadDDRTTable(void); ++ ++#if eMMC_RSP_FROM_RAM ++extern void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_SaveRsp(void); ++extern U32 eMMC_SaveDriverContext(void); ++extern U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf); ++extern U32 eMMC_LoadDriverContext(U8 *pu8_Buf); ++#endif ++ ++//---------------------------------------- ++extern U32 eMMC_Identify(void); ++extern U32 eMMC_CMD0(U32 u32_Arg); ++extern U32 eMMC_CMD1(void); ++extern U32 eMMC_CMD2(void); ++extern U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx); ++extern U32 eMMC_CMD9(U16 u16_RCA); ++extern U32 eMMC_CSD_Config(void); ++extern U32 eMMC_ExtCSD_Config(void); ++extern U32 eMMC_CMD8(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf); ++extern U32 eMMC_SetBusSpeed(U8 u8_BusSpeed); ++extern U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR); ++extern U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++extern U32 eMMC_CMD6(U32 u32_Arg); ++extern U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++extern U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx); ++extern U32 eMMC_CMD38(void); ++extern U32 eMMC_CMD13(U16 u16_RCA); ++extern U32 eMMC_CMD16(U32 u32_BlkLength); ++extern U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD12_NoCheck(U16 u16_RCA); ++extern U32 eMMC_CMD12(U16 u16_RCA); ++extern U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD18_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD23(U16 u16_BlkCnt); ++extern U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD25_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CheckR1Error(void); ++extern U32 eMMC_UpFW_Samsung(U8 *pu8_FWBin); ++ ++ ++//---------------------------------------- ++extern U32 eMMC_FCIE_PollingFifoClkReady(void); ++extern U32 eMMC_FCIE_PollingMIULastDone(void); ++ ++#endif // __eMMC_HAL_H__ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_utl.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_utl.h +new file mode 100644 +index 00000000..3788e1c2 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/common/eMMC_utl.h +@@ -0,0 +1,100 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_UTL_H__ ++#define __eMMC_UTL_H__ ++ ++#include "eMMC.h" ++ ++ ++typedef eMMC_PACK0 struct _eMMC_TEST_ALIGN_PACK { ++ ++ U8 u8_0; ++ U16 u16_0; ++ U32 u32_0, u32_1; ++ ++} eMMC_PACK1 eMMC_TEST_ALIGN_PACK_t; ++ ++extern U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt); ++extern void eMMC_dump_mem(unsigned char *buf, int cnt); ++extern U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt); ++extern U32 eMMC_ChkSum(U8 *pu8_Data, U32 u32_ByteCnt); ++extern U32 eMMC_PrintDeviceInfo(void); ++extern U32 eMMC_CompareCISTag(U8 *tag); ++extern void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo); ++extern void eMMC_dump_pni(eMMC_PNI_t *pPartInfo); ++#endif // __eMMC_UTL_H__ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_cedric_linux.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_cedric_linux.h +new file mode 100644 +index 00000000..72fda57f +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_cedric_linux.h +@@ -0,0 +1,473 @@ ++#ifndef __eMMC_CEDRIC_LINUX__ ++#define __eMMC_CEDRIC_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++//#include ++//#include "chip_int.h" ++ ++#ifdef CONFIG_ARM ++//#include ++#endif ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++//#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE 0x1F000000 ++#define RIU_BASE 0x1F200000 ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x8A00 ++#define REG_BANK_FCIE2 0x8A80 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++ ++ ++#define REG_BANK_PMU 0x700 ++#define REG_BANK_PMRTC 0x900 ++ ++#define RTC_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_PMRTC) ++#define REG_RESET GET_REG_ADDR(RTC_BASE, 0x0A) ++#define PMU_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_PMU) ++#define REG_BATTERY GET_REG_ADDR(PMU_BASE, 0x06) ++ ++ ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++/* ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN_BASE, 0x1D) ++*/ ++#define BIT_FCIE_CLK_MASK ((BIT7-1)<<8) ++#define BIT_FCIE_CLK_24M ((0<<2)<<8) ++#define BIT_FCIE_CLK_12M ((1<<2)<<8) ++#define BIT_FCIE_CLK_48M ((2<<2)<<8) ++#define BIT_FCIE_CLK_86M ((3<<2)<<8) ++#define BIT_FCIE_CLK_108M ((4<<2)<<8) ++#define BIT_FCIE_CLK_123M ((5<<2)<<8) ++#define BIT_FCIE_CLK_144M ((6<<2)<<8) ++#define BIT_FCIE_CLK_172M ((7<<2)<<8) ++#define BIT_FCIE_CLK_192M ((8<<2)<<8) ++#define BIT_FCIE_CLK_216M ((9<<2)<<8) ++#define BIT_FCIE_CLK_240M ((10<<2)<<8) ++#define BIT_FCIE_CLK_345M ((11<<2)<<8) ++#define BIT_FCIE_CLK_432M ((13<<2)<<8) ++#define BIT_FCIE_CLK_1200K ((14<<2)<<8) ++#define BIT_FCIE_CLK_300K ((15<<2)<<8) ++#define BIT_FCIE_CLK_32M ((16<<2)<<8) ++#define BIT_FCIE_CLK_36M ((17<<2)<<8) ++#define BIT_FCIE_CLK_40M ((18<<2)<<8) ++#define BIT_FCIE_CLK_43_2M ((19<<2)<<8) ++#define BIT_FCIE_CLK_54M ((20<<2)<<8) ++#define BIT_FCIE_CLK_62M ((21<<2)<<8) ++#define BIT_FCIE_CLK_72M ((22<<2)<<8) ++#define BIT_FCIE_CLK_80M ((23<<2)<<8) ++ ++#define eMMC_FCIE_VALID_CLK_CNT 10 ++extern U16 gau16_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define RIU_BASE_CLKGEN0 (RIU_BASE+(0x0580U< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 1 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 0 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 1 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++extern U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_1200K //BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_86M //BIT_FCIE_CLK_24M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_144M //BIT_FCIE_CLK_36M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++/* ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++*/ ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_chicago_linux.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_chicago_linux.h +new file mode 100644 +index 00000000..35757903 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_chicago_linux.h +@@ -0,0 +1,437 @@ ++#ifndef __eMMC_CHICAGO_LINUX__ ++#define __eMMC_CHICAGO_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++//#include "chip_int.h" ++ ++#ifdef CONFIG_ARM ++//#include ++#endif ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++//#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_BASE 0x1F000000 ++ ++#define REG_BANK_PADTOP 0x580 ++#define REG_BANK_CHIPTOP 0xF00 ++#define REG_BANK_FCIE0 0x1000 ++#define REG_BANK_FCIE1 0x1080 ++#define REG_BANK_FCIE2 0x1100 ++#define REG_BANK_FCIE3 0x1180 ++#define REG_BANK_PMU 0x1F80 ++ ++#define PMU_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_PMU) ++#define PADTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_PADTOP) ++#define CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++#define FCIE_POWEER_SAVE_MODE_BASE FCIE1_BASE ++ ++#define REG_PADTOP_00 GET_REG_ADDR(PADTOP_BASE, 0x00) ++#define REG_PADTOP_01 GET_REG_ADDR(PADTOP_BASE, 0x01) ++#define REG_PADTOP_40 GET_REG_ADDR(PADTOP_BASE, 0x40) ++#define REG_PADTOP_43 GET_REG_ADDR(PADTOP_BASE, 0x43) ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++ ++#define NFIE_REG_CLK_MASK ((BIT6-1)) ++#define NFIE_REG_4XCLK_1_3M ((0<<2)) ++#define NFIE_REG_4XCLK_26M ((1<<2)) ++#define NFIE_REG_4XCLK_48M ((2<<2)) ++#define NFIE_REG_4XCLK_80M ((3<<2)) ++#define NFIE_REG_4XCLK_96M ((4<<2)) ++#define NFIE_REG_4XCLK_120M ((5<<2)) ++#define NFIE_REG_4XCLK_147M ((6<<2)) ++#define NFIE_REG_4XCLK_160M ((7<<2)) ++#define NFIE_REG_4XCLK_176_8M ((8<<2)) ++#define NFIE_REG_4XCLK_192M ((9<<2)) ++#define NFIE_REG_4XCLK_221M ((10<<2)) ++#define NFIE_REG_4XCLK_240M ((11<<2)) ++#define NFIE_REG_4XCLK_294_6M ((13<<2)) ++#define NFIE_REG_4XCLK_353_6M ((14<<2)) ++#define NFIE_REG_4XCLK_60M ((15<<2)) ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U16 gau16_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BATTERY GET_REG_ADDR(PMU_BASE, 0x06) ++#define reg_nobat_int_en BIT3 ++ ++#define REG_CLK_EMMC GET_REG_ADDR(CHIPTOP_BASE, 0x25) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define REG_CLK_4X_DIV_EN GET_REG_ADDR(CHIPTOP_BASE, 0x3F) ++#define REG_RESET_PIN GET_REG_ADDR(CHIPTOP_BASE, 0x31) ++ ++#define eMMC_DBUS_WIDTH 8 ++#define eMMC_RST_L() REG_FCIE_CLRBIT(REG_RESET_PIN, BIT0) ++#define eMMC_RST_H() REG_FCIE_SETBIT(REG_RESET_PIN, BIT0) ++ ++//===================================================== ++// API declarations ++//===================================================== ++ ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (12*0x100000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++ ++#define WRITE_TO_eMMC 0 ++#define READ_FROM_eMMC 1 ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++//extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++ ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++ ++ ++#define eMMC_PART_ENV (0x0D|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_DEV_NODE (0x0F|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_MIU (0x20|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_EBOOT (0x21|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RTK (0x22|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_PARAMS (0x23|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_NVRAM (0x88|eMMC_LOGI_PART) //default start from 31 count ++ ++//extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 0 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 1 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++#define ENABLE_FCIE_HW_BUSY_CHECK 1 ++#define ENABLE_EMMC_POWER_SAVING_MODE 1 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++ ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 1 ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++extern U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x40 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK NFIE_REG_4XCLK_1_3M ++#define FCIE_SLOW_CLK NFIE_REG_4XCLK_80M ++#define FCIE_DEFAULT_CLK NFIE_REG_4XCLK_192M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_config.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_config.h +new file mode 100644 +index 00000000..6dce6709 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_config.h +@@ -0,0 +1,189 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. 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Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_CONFIG_H__ ++#define __eMMC_CONFIG_H__ ++ ++#define UNIFIED_eMMC_DRIVER 1 ++ ++//===================================================== ++// select a HW platform: ++// - 1: enable, 0: disable. ++// - only one platform can be 1, others have to be 0. ++// - search and check all [FIXME] if need modify or not ++//===================================================== ++#if defined(CONFIG_MSTAR_EAGLE) ++#define eMMC_DRV_EAGLE_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MSTAR_EDISON) ++#define eMMC_DRV_EDISON_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MSTAR_EIFFEL) ++#define eMMC_DRV_EIFFEL_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MSTAR_EINSTEIN) ++#define eMMC_DRV_EINSTEIN_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MS_EMMC_CEDRIC) || defined(CONFIG_MS_EMMC_CEDRIC_MODULE) ++#define eMMC_DRV_CEDRIC_LINUX 1 ++#endif ++ ++//#if defined(CONFIG_ARCH_CHICAGO) ++//#define eMMC_DRV_CHICAGO_LINUX 1 ++//#endif ++#define eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr){\ ++ dmaaddr -= MIU0_BUS_ADDR; \ ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT);\ ++}\ ++//===================================================== ++// do NOT edit the following content. ++//===================================================== ++#if defined(eMMC_DRV_G2P_ROM) && eMMC_DRV_G2P_ROM ++ #include "eMMC_g2p_rom.h" ++#elif defined(eMMC_DRV_G2P_UBOOT) && eMMC_DRV_G2P_UBOOT ++ #include "eMMC_msw8x68_uboot.h" ++#elif defined(eMMC_DRV_G2E_UBOOT) && eMMC_DRV_G2E_UBOOT ++ #include "eMMC_msw8x68t_uboot.h" ++#elif defined(eMMC_DRV_G2P_BL) && eMMC_DRV_G2P_BL ++ #include "eMMC_g2p_bl.h" ++#elif defined(eMMC_DRV_A3_UBOOT) && eMMC_DRV_A3_UBOOT ++ #include "eMMC_a3_uboot.h" ++#elif defined(eMMC_DRV_AGATE_UBOOT) && eMMC_DRV_AGATE_UBOOT ++ #include "eMMC_agate_uboot.h" ++#elif defined(eMMC_DRV_EAGLE_UBOOT) && eMMC_DRV_EAGLE_UBOOT ++ #include "eMMC_eagle_uboot.h" ++#elif defined(eMMC_DRV_EDISON_UBOOT) && eMMC_DRV_EDISON_UBOOT ++ #include "eMMC_edison_uboot.h" ++#elif defined(eMMC_DRV_EIFFEL_UBOOT) && eMMC_DRV_EIFFEL_UBOOT ++ #include "eMMC_eiffel_uboot.h" ++#elif defined(eMMC_DRV_G2P_LINUX) && eMMC_DRV_G2P_LINUX ++ #include "eMMC_msw8x68_linux.h" ++// [FIXME] add a .h file for your platform ++#elif defined(eMMC_DRV_EAGLE_LINUX) && eMMC_DRV_EAGLE_LINUX ++ #include "eMMC_eagle_linux.h" ++#elif defined(eMMC_DRV_EDISON_LINUX) && eMMC_DRV_EDISON_LINUX ++ #include "eMMC_edison_linux.h" ++#elif defined(eMMC_DRV_EIFFEL_LINUX) && eMMC_DRV_EIFFEL_LINUX ++ #include "eMMC_eiffel_linux.h" ++#elif defined(eMMC_DRV_EINSTEIN_LINUX) && eMMC_DRV_EINSTEIN_LINUX ++ #include "eMMC_einstein_linux.h" ++#elif defined(eMMC_DRV_CEDRIC_LINUX) && eMMC_DRV_CEDRIC_LINUX ++ #include "eMMC_cedric_linux.h" ++#elif defined(eMMC_DRV_CHICAGO_LINUX) && eMMC_DRV_CHICAGO_LINUX ++ #include "eMMC_chicago_linux.h" ++#else ++ #error "Error! no platform selected." ++#endif ++ ++//===================================================== ++// misc. do NOT edit the following content. ++//===================================================== ++#define eMMC_DMA_RACING_PATCH 1 ++#define eMMC_DMA_PATCH_WAIT_TIME DELAY_10ms_in_us ++#define eMMC_DMA_RACING_PATTERN0 (((U32)'M'<<24)|((U32)0<<16)|((U32)'S'<<8)|(U32)1) ++#define eMMC_DMA_RACING_PATTERN1 (((U32)'T'<<24)|((U32)6<<16)|((U32)'A'<<8)|(U32)8) ++ ++//=========================================================== ++// Time Dalay, do NOT edit the following content ++//=========================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RESET (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FIFOCLK_RDY (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_CMDRSP_END (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*5) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*10) // safe for 512 blocks ++#else ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*60*10) //10*60 s ++#define TIME_WAIT_ERASE_DAT0_HIGH (HW_TIMER_DELAY_1s*60*10) //10*60 s ++#define TIME_WAIT_FCIE_RESET HW_TIMER_DELAY_500ms ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT HW_TIMER_DELAY_1us ++#define TIME_WAIT_FIFOCLK_RDY HW_TIMER_DELAY_500ms ++#define TIME_WAIT_CMDRSP_END HW_TIMER_DELAY_1s ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*2) // safe for 512 blocks ++#endif ++ ++ ++ ++ ++#endif /* __eMMC_CONFIG_H__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_eagle_linux.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_eagle_linux.h +new file mode 100644 +index 00000000..c9005c00 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_eagle_linux.h +@@ -0,0 +1,521 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_EAGLE_LINUX__ ++#define __eMMC_EAGLE_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "chip_int.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_ARM ++#include ++#endif ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#ifdef CONFIG_ARM ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++#endif ++ ++#define REG_BANK_FCIE0 0x8980 // 1113h x 80h x 4 + 1F000000 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++#define REG_BANK_FCIE3 0x8A80 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++#define FCIE3_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE3) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ [FIXME]: refer to Bring-up Note --> ++// Mobile CMU = TV CLKGEN ++// TV CNM don't touch ++#define REG_BANK_CLKGEN 0x580 ++#define CLKGEN_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN) ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++ ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++//#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++//#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_48M 15 ++#define BIT_FCIE_CLK_300K 13 ++ ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN_BASE, 0x31) ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK ((BIT2|BIT3|BIT4)<<8) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK4X_20M 1 ++#define BIT_FCIE_CLK4X_27M 2 ++#define BIT_FCIE_CLK4X_36M 3 ++#define BIT_FCIE_CLK4X_40M 4 ++#define BIT_FCIE_CLK4X_48M 5 ++ ++#define reg_ckg_CMU GET_REG_ADDR(CLKGEN_BASE, 0x10) ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 // FIXME ++extern U8 gau8_FCIEClkSel[]; ++ ++ ++//------------------------------ ++#define REG_BANK_CHIPTOP 0xF00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++#define reg_chiptop_0x5A GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define reg_chiptop_0x1F GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1F) ++#define reg_chiptop_0x70 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x70) ++#define reg_chiptop_0x64 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define reg_chiptop_0x4F GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x4F) ++#define reg_chiptop_0x03 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x03) ++#define reg_chiptop_0x51 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x51) ++#define reg_chiptop_0x6F GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++ ++#define reg_chiptop_0x43 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x43) ++#define BIT_PAD_EMMC_CLK_SRC BIT0 ++#define BIT_PAD_BYPASS_MACRO BIT1 ++#define BIT_EMPTY BIT2 ++#define BIT_eMMC_RSTPIN_EN BIT3 ++#define BIT_eMMC_RSTPIN_VAL BIT4 ++ ++#define reg_chiptop_0x50 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_NAND_CS1_EN BIT10 ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_chiptop_0x0B GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define BIT_NAND_CS2_EN BIT0 ++#define BIT_NAND_CS3_EN BIT1 ++#define BIT_SD0_CFG (BIT2|BIT3) ++#define BIT_SD0_CFG2 (BIT4|BIT5) ++#define BIT_SD1_CFG (BIT6|BIT7) ++#define BIT_SD1_CFG2 (BIT8|BIT9) ++#define BIT_NAND_CFG (BIT12|BIT13|BIT14) ++ ++#define reg_chiptop_0x5D GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5D) ++#define BIT_eMMC_CFG_MASK (BIT14|BIT15) ++#define BIT_eMMC_CFG_MODE1 (BIT14) ++#define BIT_eMMC_CFG_MODE2 (BIT14|BIT15) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x59) ++#define CFG_EMMC_CMD_STRENGTH BIT12 ++#define CFG_EMMC_CLK_STRENGTH BIT13 ++ ++#define reg_pcm_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define CFG_PCM_DRV_STRENGTH (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++ ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define CFG_NAND_DRV_STRENGTH (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT0 ++#define BIT_SW_RST_Z BIT1 ++#define BIT_SW_RST_Z_EN BIT2 ++ ++#define eMMC_RST_L() {REG_FCIE_SETBIT(reg_chiptop_0x43, BIT_eMMC_RSTPIN_EN);\ ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, BIT_eMMC_RSTPIN_VAL);} ++#define eMMC_RST_H() REG_FCIE_SETBIT(reg_chiptop_0x43, BIT_eMMC_RSTPIN_EN|BIT_eMMC_RSTPIN_VAL) ++ ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 1 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 1 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++// [FIXME] --> ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++// <-- [FIXME] ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x80C00000 ++#define DMA_R_ADDR 0x80D00000 ++#define DMA_W_SPARE_ADDR 0x80E00000 ++#define DMA_R_SPARE_ADDR 0x80E80000 ++#define DMA_BAD_BLK_BUF 0x80F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#endif /* __eMMC_EAGLE_LINUX__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_edison_linux.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_edison_linux.h +new file mode 100644 +index 00000000..b7e0b4a4 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_edison_linux.h +@@ -0,0 +1,455 @@ ++#ifndef __eMMC_EDISON_LINUX__ ++#define __eMMC_EDISON_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_DEBUG_FS ++#include ++#include ++#endif ++#include "chip_int.h" ++ ++#include ++#include ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++#define REG_BANK_CLKGEN0 0x0580 ++#define CLKGEN0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN0) ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN0_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN0_BASE, 0x1D) ++#define reg_ckg_emmc GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++ ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK_XTAL 0 ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_300K 13 ++#define BIT_FCIE_CLK_48M 15 ++ ++#define BIT_FCIE_CLK4X_20M 0 ++#define BIT_FCIE_CLK4X_27M 1 ++#define BIT_FCIE_CLK4X_36M 2 ++#define BIT_FCIE_CLK4X_40M 3 ++#define BIT_FCIE_CLK4X_48M 4 ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BANK_CHIPTOP 0x0F00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define reg_pcm_d_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x09) ++#define reg_pcm_a_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0A) ++#define reg_pcm2_cd_n_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define reg_nand_ps GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0D) ++ ++#define reg_fcie2macro_sd_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x10) ++#define FCIE2MACRO_SD_BYPASS BIT8 ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT8 ++#define BIT_SW_RST_Z BIT9 ++#define BIT_SW_RST_Z_EN BIT10 ++ ++#define reg_sd_use_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x40) ++#define SD_USE_BYPASS BIT0 ++ ++#define reg_all_pad_in GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_sd_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define CFG_SD_PAD_MASK (BIT8|BIT9|BIT10|BIT11) ++ ++#define reg_pcmcia_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define CFG_PCMCIA_PAD_MASK (BIT0|BIT4) ++ ++#define reg_emmc_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6E) ++#define CFG_EMMC_PAD_MASK (BIT6|BIT7) ++ ++#define reg_nand_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++#define CFG_NAND_PAD_MASK (BIT6|BIT7) ++ ++#define eMMC_DBUS_WIDTH 8 ++ ++#define eMMC_RST_L() ++#define eMMC_RST_H() ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // Need to confirm ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++#define MIU_CHECK_LAST_DONE 1 ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_eiffel_linux.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_eiffel_linux.h +new file mode 100644 +index 00000000..a2411816 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_eiffel_linux.h +@@ -0,0 +1,455 @@ ++#ifndef __eMMC_EIFFEL_LINUX__ ++#define __eMMC_EIFFEL_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_DEBUG_FS ++#include ++#include ++#endif ++#include "chip_int.h" ++ ++#include ++#include ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++#define REG_BANK_CLKGEN0 0x0580 ++#define CLKGEN0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN0) ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN0_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN0_BASE, 0x1D) ++#define reg_ckg_emmc GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++ ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK_XTAL 0 ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_300K 13 ++#define BIT_FCIE_CLK_48M 15 ++ ++#define BIT_FCIE_CLK4X_20M 0 ++#define BIT_FCIE_CLK4X_27M 1 ++#define BIT_FCIE_CLK4X_36M 2 ++#define BIT_FCIE_CLK4X_40M 3 ++#define BIT_FCIE_CLK4X_48M 4 ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BANK_CHIPTOP 0x0F00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define reg_pcm_d_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x09) ++#define reg_pcm_a_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0A) ++#define reg_pcm2_cd_n_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define reg_nand_ps GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0D) ++ ++#define reg_fcie2macro_sd_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x10) ++#define FCIE2MACRO_SD_BYPASS BIT8 ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT8 ++#define BIT_SW_RST_Z BIT9 ++#define BIT_SW_RST_Z_EN BIT10 ++ ++#define reg_sd_use_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x40) ++#define SD_USE_BYPASS BIT0 ++ ++#define reg_all_pad_in GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_sd_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define CFG_SD_PAD_MASK (BIT8|BIT9|BIT10|BIT11) ++ ++#define reg_pcmcia_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define CFG_PCMCIA_PAD_MASK (BIT0|BIT4) ++ ++#define reg_emmc_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6E) ++#define CFG_EMMC_PAD_MASK (BIT6|BIT7) ++ ++#define reg_nand_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++#define CFG_NAND_PAD_MASK (BIT6|BIT7) ++ ++#define eMMC_DBUS_WIDTH 8 ++ ++#define eMMC_RST_L() ++#define eMMC_RST_H() ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // Need to confirm ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++#define MIU_CHECK_LAST_DONE 1 ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_einstein_linux.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_einstein_linux.h +new file mode 100644 +index 00000000..d55547b2 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_einstein_linux.h +@@ -0,0 +1,455 @@ ++#ifndef __eMMC_EINSTEIN_LINUX__ ++#define __eMMC_EINSTEIN_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_DEBUG_FS ++#include ++#include ++#endif ++#include "chip_int.h" ++ ++#include ++#include ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++#define REG_BANK_CLKGEN0 0x0580 ++#define CLKGEN0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN0) ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN0_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN0_BASE, 0x1D) ++#define reg_ckg_emmc GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++ ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK_XTAL 0 ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_300K 13 ++#define BIT_FCIE_CLK_48M 15 ++ ++#define BIT_FCIE_CLK4X_20M 0 ++#define BIT_FCIE_CLK4X_27M 1 ++#define BIT_FCIE_CLK4X_36M 2 ++#define BIT_FCIE_CLK4X_40M 3 ++#define BIT_FCIE_CLK4X_48M 4 ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BANK_CHIPTOP 0x0F00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define reg_pcm_d_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x09) ++#define reg_pcm_a_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0A) ++#define reg_pcm2_cd_n_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define reg_nand_ps GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0D) ++ ++#define reg_fcie2macro_sd_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x10) ++#define FCIE2MACRO_SD_BYPASS BIT8 ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT8 ++#define BIT_SW_RST_Z BIT9 ++#define BIT_SW_RST_Z_EN BIT10 ++ ++#define reg_sd_use_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x40) ++#define SD_USE_BYPASS BIT0 ++ ++#define reg_all_pad_in GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_sd_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define CFG_SD_PAD_MASK (BIT8|BIT9|BIT10|BIT11) ++ ++#define reg_pcmcia_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define CFG_PCMCIA_PAD_MASK (BIT0|BIT4) ++ ++#define reg_emmc_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6E) ++#define CFG_EMMC_PAD_MASK (BIT6|BIT7) ++ ++#define reg_nand_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++#define CFG_NAND_PAD_MASK (BIT6|BIT7) ++ ++#define eMMC_DBUS_WIDTH 8 ++ ++#define eMMC_RST_L() ++#define eMMC_RST_H() ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_BYPASS // [FIXME] ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 1 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // Need to confirm ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++#define MIU_CHECK_LAST_DONE 1 ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_reg.h b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_reg.h +new file mode 100644 +index 00000000..cebc6bc1 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/inc/config/eMMC_reg.h +@@ -0,0 +1,381 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_FCIE_REG_H__ ++#define __eMMC_FCIE_REG_H__ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++#ifndef BIT0 ++#define BIT0 (1<<0) ++#endif ++#ifndef BIT1 ++#define BIT1 (1<<1) ++#endif ++#ifndef BIT2 ++#define BIT2 (1<<2) ++#endif ++#ifndef BIT3 ++#define BIT3 (1<<3) ++#endif ++#ifndef BIT4 ++#define BIT4 (1<<4) ++#endif ++#ifndef BIT5 ++#define BIT5 (1<<5) ++#endif ++#ifndef BIT6 ++#define BIT6 (1<<6) ++#endif ++#ifndef BIT7 ++#define BIT7 (1<<7) ++#endif ++#ifndef BIT8 ++#define BIT8 (1<<8) ++#endif ++#ifndef BIT9 ++#define BIT9 (1<<9) ++#endif ++#ifndef BIT10 ++#define BIT10 (1<<10) ++#endif ++#ifndef BIT11 ++#define BIT11 (1<<11) ++#endif ++#ifndef BIT12 ++#define BIT12 (1<<12) ++#endif ++#ifndef BIT13 ++#define BIT13 (1<<13) ++#endif ++#ifndef BIT14 ++#define BIT14 (1<<14) ++#endif ++#ifndef BIT15 ++#define BIT15 (1<<15) ++#endif ++#ifndef BIT16 ++#define BIT16 (1<<16) ++#endif ++#ifndef BIT17 ++#define BIT17 (1<<17) ++#endif ++#ifndef BIT18 ++#define BIT18 (1<<18) ++#endif ++#ifndef BIT19 ++#define BIT19 (1<<19) ++#endif ++#ifndef BIT20 ++#define BIT20 (1<<20) ++#endif ++#ifndef BIT21 ++#define BIT21 (1<<21) ++#endif ++#ifndef BIT22 ++#define BIT22 (1<<22) ++#endif ++#ifndef BIT23 ++#define BIT23 (1<<23) ++#endif ++#ifndef BIT24 ++#define BIT24 (1<<24) ++#endif ++#ifndef BIT25 ++#define BIT25 (1<<25) ++#endif ++#ifndef BIT26 ++#define BIT26 (1<<26) ++#endif ++#ifndef BIT27 ++#define BIT27 (1<<27) ++#endif ++#ifndef BIT28 ++#define BIT28 (1<<28) ++#endif ++#ifndef BIT29 ++#define BIT29 (1<<29) ++#endif ++#ifndef BIT30 ++#define BIT30 (1<<30) ++#endif ++#ifndef BIT31 ++#define BIT31 (1<<31) ++#endif ++ ++//------------------------------------------------------------------ ++#define FCIE_MIE_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x00) ++#define FCIE_MIE_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x01) ++#define FCIE_MMA_PRI_REG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x02) ++#define FCIE_MIU_DMA_26_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x03) ++#define FCIE_MIU_DMA_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x04) ++#define FCIE_CARD_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x06) ++#define FCIE_CARD_POWER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x08) ++#define FCIE_FORCE_INT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x09) ++#define FCIE_PATH_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0A) ++#define FCIE_JOB_BL_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0B) ++#define FCIE_TR_BK_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0C) ++#define FCIE_RSP_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0D) ++#define FCIE_CMD_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0E) ++#define FCIE_CIFD_WORD_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0F) ++#define FCIE_SD_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_SD_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++#define FCIE_SD_STATUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x12) ++#define FCIE_REG16h GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x16) ++#define FCIE_SDIO_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1B) ++#define FCIE_SDIO_ADDR0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1C) ++#define FCIE_SDIO_ADDR1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1D) ++#define FCIE_SM_STS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2C) ++#define FCIE_REG_2Dh GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2D) ++#define FCIE_MIU_OFFSET GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2E) ++#define FCIE_BOOT_CONFIG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2F) ++#define FCIE_TEST_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x30) ++#define FCIE_DEBUG_BUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x31) ++#define FCIE_MACRO_REDNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x32) ++#define FCIE_TOGGLE_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x33) ++#define FCIE_PWR_SAVE_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x35) ++#define FCIE_MISC GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x36) ++#define NC_WIDTH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x41) ++ ++#define FCIE_CIFC_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFC_BASE_ADDR, u16_pos) ++#define FCIE_CIFC_BYTE_CNT 0x40 // 32 x 16 bits ++ ++#define FCIE_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFD_BASE_ADDR, u16_pos) ++#define FCIE_CIFD_BYTE_CNT 0x200 // 256 x 16 bits ++ ++//------------------------------------------------------------------ ++/* FCIE_MIE_EVENT 0x00 */ ++/* FCIE_MIE_INT_EN 0x01 */ ++#define BIT_MMA_DATA_END BIT0 ++#define BIT_SD_CMD_END BIT1 ++#define BIT_SD_DATA_END BIT2 ++#define BIT_SD_BUSY_END BIT4 ++#define BIT_CARD_DMA_END BIT11 ++#define BIT_MIU_LAST_DONE BIT14 ++#define BIT_CARD_BOOT_DONE BIT15 ++#define BIT_ALL_CARD_INT_EVENTS (BIT_MMA_DATA_END|BIT_SD_CMD_END|BIT_SD_DATA_END|BIT_SD_BUSY_END\ ++ |BIT_CARD_DMA_END|BIT_MIU_LAST_DONE|BIT_CARD_BOOT_DONE) ++/* FCIE_MMA_PRI_REG 0x02 */ ++#define BIT_DMA_DIR_W BIT2 ++#define BIT_MIU_REQUEST_RST BIT4 ++#define BIT_FIFO_CLKRDY BIT5 ++#define BIT_MIU_BURST_MASK (BIT8|BIT9|BIT10) ++#define BIT_MIU_BURST_CTRL BIT10 ++#define BIT_MIU_BURST_8 BIT_MIU_BURST_CTRL ++#define BIT_MIU_BURST_16 (BIT8|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_BURST_32 (BIT9|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_CLK_EN_SW BIT12 ++#define BIT_MIU_CLK_EN_HW BIT13 ++#define BIT_MIU_CLK_CTRL_SEL_SW BIT14 ++#define BIT_MIU_CLK_FREE_RUN BIT15 ++/* FCIE_MIU_DMA_26_16 0x03 */ ++#define BIT_MIU1_SELECT BIT15 ++/* FCIE_CARD_POWER 0x08 */ ++#define BIT_SD_PWR_ON_n BIT0 ++#define BIT_SD_PWR_OUT_n BIT2 ++/* FCIE_PATH_CTRL 0x0A */ ++#define BIT_MMA_EN BIT0 ++#define BIT_SD_EN BIT1 ++/* FCIE_JOB_BL_CNT 0x0B */ ++#define BIT_SD_JOB_BLK_CNT_MASK (BIT12-1) ++/* FCIE_RSP_SIZE 0x0D */ ++#define BIT_SD_RSP_SIZE_MASK (BIT7-1) ++/* FCIE_SD_MODE 0x10 */ ++#define BIT_SD_CLK_EN BIT0 ++#define BIT_SD_DATA_WIDTH_MASK (BIT1|BIT2) ++#define BIT_SD_DATA_WIDTH_1 0 ++#define BIT_SD_DATA_WIDTH_4 BIT1 ++#define BIT_SD_DATA_WIDTH_8 BIT2 ++#define BIT_SD_IF_LOW BIT3 ++#define BIT_SD_CLK_AUTO_STOP BIT4 ++#define BIT_SD_DATA_CIFD BIT5 ++#define BIT_SD_DATA_SYNC BIT6 // set for eMMC High Speed Mode ++#define BIT_SD_SELECT_SDIO BIT9 ++#define BIT_SD_DMA_R_CLK_STOP BIT11 ++ ++//#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_CLK_EN) ++#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_DATA_SYNC|BIT_SD_CLK_EN) ++ ++/* FCIE_SD_CTRL 0x11 */ ++#define BIT_SD_RSPR2_EN BIT0 ++#define BIT_SD_RSP_EN BIT1 ++#define BIT_SD_CMD_EN BIT2 ++#define BIT_SD_DAT_EN BIT3 ++#define BIT_SD_DAT_DIR_W BIT4 ++#define BIT_SD_BUSY_DET_ON BIT5 ++/* FCIE_SD_STATUS 0x12 */ ++#define BIT_SD_R_CRC_ERR BIT0 ++#define BIT_SD_W_FAIL BIT1 ++#define BIT_SD_W_CRC_ERR BIT2 ++#define BIT_SD_RSP_TIMEOUT BIT3 ++#define BIT_SD_RSP_CRC_ERR BIT4 ++#define BIT_SD_CARD_WP BIT5 ++#define BIT_SD_CARD_BUSY BIT6 ++#define BIT_SD_D0 BIT8 ++#define BIT_SD_DBUS_MASK (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++#define BIT_SD_DBUS_SHIFT 8 ++ ++//#define BIT_SD_FCIE_ERR_FLAGS ((BIT5-1)|BIT_SD_CARD_BUSY) ++#define BIT_SD_FCIE_ERR_FLAGS (BIT5-1) ++#define BIT_SD_CARD_D0_ST BIT8 ++#define BIT_SD_CARD_D1_ST BIT9 ++#define BIT_SD_CARD_D2_ST BIT10 ++#define BIT_SD_CARD_D3_ST BIT11 ++#define BIT_SD_CARD_D4_ST BIT12 ++#define BIT_SD_CARD_D5_ST BIT13 ++#define BIT_SD_CARD_D6_ST BIT14 ++#define BIT_SD_CARD_D7_ST BIT15 ++/* FCIE_REG16h */ ++#define BIT_EMMC_ACTIVE BIT0 ++/* FCIE_SDIO_CTRL 0x1B */ ++#define BIT_SDIO_BLK_SIZE_MASK (BIT13-1) ++#define BIT_SDIO_BLK_MODE BIT15 ++/* FCIE_SM_STS 0x2C */ ++#define BIT_DQS_DELAY_CELL_MASK (BIT8|BIT9|BIT10|BIT11) ++#define BIT_DQS_DELAY_CELL_SHIFT 8 ++#define BIT_DQS_MODE_MASK (BIT12|BIT13) ++#define BIT_DQS_MDOE_SHIFT 12 ++#define BIT_DQS_MODE_2T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (3 << BIT_DQS_MDOE_SHIFT) ++/* FCIE_REG_2Dh 0x2D */ ++#define BIT_NEW_DESIGN_ENn BIT14 ++/* FCIE_BOOT_CONFIG 0x2F */ ++#define BIT_BOOT_STG2_EN BIT0 ++#define BIT_BOOT_END_EN BIT1 ++#define BIT_BOOT_MODE_EN BIT2 ++#define BIT_MACRO_EN BIT8 ++#define BIT_SD_DDR_EN BIT9 ++#define BIT_SD_BYPASS_MODE_EN BIT10 ++#define BIT_SD_SDR_IN_BYPASS BIT11 ++#define BIT_SD_FROM_TMUX BIT12 ++#define BIT_SD_CLKOE_DELAY_EN BIT13 ++/* FCIE_TEST_MODE 0x30 */ ++#define BIT_FCIE_BIST_FAIL (BIT0|BIT1|BIT2|BIT3|BIT4) ++#define BIT_FCIE_DEBUG_MODE_MASK (BIT8|BIT9|BIT10) ++#define BIT_FCIE_DEBUG_MODE_SHIFT 8 ++#define BIT_FCIE_SOFT_RST_n BIT12 ++#define BIT_FCIE_PPFIFO_CLK BIT14 ++/* FCIE_MACRO_REDNT 0x32 */ ++#define BIT_DQS_DELAY_CELL_SEL_MASK (BIT0|BIT1|BIT2|BIT3) ++#define BIT_MACRO_TEST_MODE_MASK (BIT4|BIT5) ++#define BIT_MACRO_DIR BIT6 ++#define BIT_TOGGLE_CNT_RST BIT7 ++/* FCIE_TOGGLE_CNT */ ++#define BITS_8_R_TOGGLE_CNT 0x111 ++#define BITS_4_R_TOGGLE_CNT 0x211 ++#define BITS_8_W_TOGGLE_CNT 0x11A ++#define BITS_4_W_TOGGLE_CNT 0x21A ++/* FCIE_PWR_SAVE_MODE 0x35 */ ++#define BIT_POWER_SAVE_MODE_EN BIT0 /* Power Save HW enable, high active */ ++#define BIT_SD_POWER_SAVE_RIU BIT1 /* SW set register to emulate power lost event, high active */ ++#define BIT_POWER_SAVE_MODE_INT_EN BIT2 /* interrupt enable, high active */ ++#define BIT_SD_POWER_SAVE_RST BIT3 /* software reset Power Save HW, default is '1', set '0' to reset HW */ ++#define BIT_RIU_SAVE_EVENT BIT5 /* RO, RIU emulation power save event */ ++#define BIT_RST_SAVE_EVENT BIT6 /* RO, Hardware reset power save event */ ++#define BIT_BAT_SAVE_EVENT BIT7 /* RO, Battery lost power save event */ ++ ++/* NC_WIDTH 0x41 */ ++#define BIT_NC_DEB_SEL_SHIFT 12 ++#define BIT_NC_DEB_SEL_MASK (BIT12|BIT13|BIT14) ++#define BIT_NC_BCH_DEB_SEL BIT15 ++ ++//------------------------------------------------------------------ ++/* ++ * Power Save FIFO Cmd* ++ */ ++#define PWR_BAT_CLASS (0x1 << 13) /* Battery lost class */ ++#define PWR_RST_CLASS (0x1 << 12) /* Reset Class */ ++ ++/* Command Type */ ++#define PWR_CMD_WREG (0x0 << 9) /* Write data */ ++#define PWR_CMD_RDCP (0x1 << 9) /* Read and cmp data. If mismatch, HW retry */ ++#define PWR_CMD_WAIT (0x2 << 9) /* Wait idle, max. 128T */ ++#define PWR_CMD_WINT (0x3 << 9) /* Wait interrupt */ ++#define PWR_CMD_STOP (0x7 << 9) /* Stop */ ++ ++/* RIU Bank */ ++#define PWR_CMD_BK0 (0x0 << 7) ++#define PWR_CMD_BK1 (0x1 << 7) ++#define PWR_CMD_BK2 (0x2 << 7) ++#define PWR_CMD_BK3 (0x3 << 7) ++ ++#define PWR_RIU_ADDR (0x0 << 0) ++ ++#endif /* __eMMC_FCIE_REG_H__ */ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/src/api/eMMC_prg.c b/drivers/mstar/emmc/cedric/eMMCDrv/src/api/eMMC_prg.c +new file mode 100644 +index 00000000..13b8ab3c +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/src/api/eMMC_prg.c +@@ -0,0 +1,2046 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++ ++#include "eMMC.h" ++ ++ ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++static U32 eMMC_ReadPartitionInfo_Ex(void); ++static U32 eMMC_GetPartitionIndex(U16 u16_PartType, ++ U32 u32_LogicIdx, ++ volatile U16 *pu16_PartIdx); ++ ++/* frequency bases */ ++/* divided by 10 to be nice to platforms without floating point */ ++int fbase[] = { ++ 10000, ++ 100000, ++ 1000000, ++ 10000000, ++}; ++ ++/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice ++ * to platforms without floating point. ++ */ ++int multipliers[] = { ++ 0, /* reserved */ ++ 10, ++ 12, ++ 13, ++ 15, ++ 20, ++ 25, ++ 30, ++ 35, ++ 40, ++ 45, ++ 50, ++ 55, ++ 60, ++ 70, ++ 80, ++}; ++ ++//======================================================== ++U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt) ++{ ++ U32 u32_err, u32_i; ++ U16 u16_reg, u16_retry=0; ++ ++ // -------------------------------- ++ eMMC_PlatformInit(); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ //*(U16*)0x25020DD4 &= ~BIT6; // FPGA only ++ ++ LABEL_BOOT_MODE_START: ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ // -------------------------------- ++ eMMC_RST_L(); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1ms); ++ eMMC_RST_H(); ++ ++ u32_i = 0; ++ while(u32_i < u32_ItemCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"i:%u SecCnt:%Xh \n", u32_i, pu32_SectorCnt[u32_i]); ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, pu32_SectorCnt[u32_i]); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, pu32_Addr[u32_i] & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, pu32_Addr[u32_i] >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (pu32_Addr[u32_i]>>3) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(pu32_Addr[u32_i]>>3) >> 16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ if(0 == u32_i) // stg.1 ++ { ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_MODE_EN); ++ } ++ else // stg.2 ++ { ++ // can NOT set BIT_SD_DAT_EN ++ //REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_STG2_EN); ++ } ++ //eMMC_printf("BBB"); ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE, HW_TIMER_DELAY_1s); ++ ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((0==u16_retry) && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ u16_retry++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #if 0 ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ #endif ++ goto LABEL_BOOT_MODE_START; ++ } ++ #if 0 ++ else if(u16_retry && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry fail, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ } ++ #endif ++ u32_i++; ++ } ++ ++ // -------------------------------- ++ // boot end ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_END_EN); ++ //eMMC_printf("CCC"); ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_CARD_BOOT_DONE, HW_TIMER_DELAY_1s); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_LOAD_IMAGE_END: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: %Xh\n", u32_err); ++ return u32_err; ++} ++ ++ ++ ++//======================================================== ++U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID) ++{ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ *pu8IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(pu8ID, g_eMMCDrv.au8_ID, eMMC_ID_BYTE_CNT); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_CheckCIS(eMMC_CIS_t *ptCISData) ++{ ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ U32 u32_ChkSum; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ if (eMMC_CompareCISTag(peMMCInfo->au8_Tag)) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI Tag mismatch\n"); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&peMMCInfo->u16_SpareByteCnt, (U16)((U32)(&peMMCInfo->u16_SeqAccessTime)-(U32)(&peMMCInfo->u16_SpareByteCnt))); ++ if (u32_ChkSum != peMMCInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, peMMCInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)peMMCInfo, 0x200); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&pPartInfo->u16_SpareByteCnt, 0x200-0x04); ++ if (u32_ChkSum != pPartInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pni chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, pPartInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)pPartInfo, 0x200); ++ return eMMC_ST_ERR_CIS_PNI; ++ } ++ ++ eMMC_dump_nni(peMMCInfo); ++ eMMC_dump_pni(pPartInfo); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#if 0 ++U32 eMMC_WriteCIS(eMMC_CIS_t *ptCISData) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ u32_err = eMMC_CheckCIS(ptCISData); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ---------------------------- ++ // write NNI in Blk0 and Blk1 ++ for(u16_i=0; u16_iau8_Vendor, 16); ++ memcpy(g_eMMCDrv.au8_PartNumber, peMMCInfo->au8_PartNumber, 16); ++ ++ return u32_err; ++} ++#endif ++ ++// read CIS and set config to UNFD ++U32 eMMC_ReadCIS(eMMC_CIS_t *ptCISData) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ // read NNI in Blk0 and Blk1 ++ for(u16_i=0; u16_iu32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SpareByteCnt: %04Xh \n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PageByteCnt: %04Xh \n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkPageCnt: %04Xh \n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartitionCnt: %04Xh \n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"RecByteCnt: %04Xh \n", pPartInfo->u16_UnitByteCnt); ++ ++ u32_PniBlkByteCnt = pPartInfo->u16_PageByteCnt * pPartInfo->u16_BlkPageCnt; ++ u32_PniBlkCnt = 0; ++ ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Partition: %02u \n", u16_i); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"StartBlk: %04Xh \n", pPartInfo->records[u16_i].u16_StartBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->records[u16_i].u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartType: %04Xh \n", pPartInfo->records[u16_i].u16_PartType); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BackupBlkCnt:%04Xh \n", pPartInfo->records[u16_i].u16_BackupBlkCnt); ++ ++ if(u16_i < pPartInfo->u16_PartCnt-1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u KB\n", ++ (u32_PniBlkByteCnt * pPartInfo->records[u16_i].u16_BlkCnt)>>10); ++ ++ u32_PniBlkCnt += pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u MB\n", ++ (g_eMMCDrv.u32_SEC_COUNT - (u32_PniBlkCnt*u32_PniBlkByteCnt>>9))>>11); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// data length is 512 bytes ++U32 eMMC_FATAutoSize(void) ++{ ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ volatile U32 u32_PartSectorCnt=0; ++ ++ // calculate FAT sector cnt ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ ++ else if(u32_PartSectorCnt) ++ u32_PartSectorCnt += ++ (pPartInfo->records[u16_i].u16_BlkCnt + pPartInfo->records[u16_i].u16_BackupBlkCnt) ++ * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ g_eMMCDrv.u32_FATSectorCnt = g_eMMCDrv.u32_SEC_COUNT - u32_PartSectorCnt; ++ ++ u32_PartSectorCnt = 0; ++ // shift the StartBlk for partitions following FAT ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ { ++ pPartInfo->records[u16_i].u16_BlkCnt = ++ g_eMMCDrv.u32_FATSectorCnt / pPartInfo->u16_BlkPageCnt; ++ ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk + ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ else if(u32_PartSectorCnt) ++ { ++ pPartInfo->records[u16_i].u16_StartBlk = u32_PartSectorCnt; ++ ++ u32_PartSectorCnt += ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U32 eMMC_ReadPartitionInfo_Ex(void) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // read Partition Info from Blk0 and Blk1 (check) ++ for(u16_i=0; u16_iu32_ChkSum || pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info %u ChkSum failed: %Xh %Xh\n", ++ u16_i, pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: found Part Info %u\n", u16_i); ++ break; ++ } ++ } ++ ++ // print msg ++ if(eMMC_CIS_PNI_BLK_CNT== u16_i) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: no valid Partition Info\n"); ++ return eMMC_ST_ERR_NO_PART_INFO; ++ } ++ else{ ++ // calculate FAT capacity ++ eMMC_FATAutoSize(); ++ //eMMC_debug(0,1,"Total Sec: %Xh, FAT Sec: %Xh \n", g_eMMCDrv.u32_SEC_COUNT, g_eMMCDrv.u32_FATSectorCnt); ++ } ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_GET_PART_INFO; ++ return u32_err; ++} ++ ++ ++// data length is 512 bytes ++U32 eMMC_ReadPartitionInfo(U8 *pu8_Data) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_GET_PART_INFO)) ++ { ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadPartitionInfo_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ } ++ ++ memcpy(pu8_Data, gau8_eMMC_PartInfoBuf, 0x200); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#if 0 ++U32 eMMC_WritePartitionInfo(U8 *pu8_Data, U32 u32_ByteCnt) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)pu8_Data; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u16_SecCnt = (u32_ByteCnt>>eMMC_SECTOR_512BYTE_BITS) + (u32_ByteCnt&eMMC_SECTOR_512BYTE_MASK); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC input Part Info keeps %u sectors\n", u16_SecCnt); ++ ++ // search eMMC Partiton Info from pni (pu8_Data) ++ for(u16_i=0; u16_iu16_SpareByteCnt, pPartInfo->u16_BlkCnt); ++ if(1 == pPartInfo->u16_SpareByteCnt) ++ break; ++ pPartInfo = (eMMC_PNI_t*)((U32)pPartInfo+0x200); ++ } ++ if(u16_i == u16_SecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: no valid Part Info for eMMC\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info ChkSum failed for eMMC, %Xh %Xh\n", ++ pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ return eMMC_ST_ERR_PARTITION_CHKSUM; ++ } ++ ++ // write Partition Info in Blk0 and Blk1 (as MBR) ++ for(u16_i=0; u16_iu16_PartCnt; *pu16_PartIdx+=1) ++ { ++ if(u16_PartType == pPartInfo->records[*pu16_PartIdx].u16_PartType) ++ { ++ if(u16_PartCopy == u32_LogicIdx) ++ break; ++ u16_PartCopy++; ++ } ++ } ++ if(*pu16_PartIdx == pPartInfo->u16_PartCnt) ++ { ++ if(0 == u16_PartCopy) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown Partition ID: %Xh\n", u16_PartType); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: no %u Partition ID: %Xh \n", ++ u32_LogicIdx+1, u16_PartType); ++ ++ return eMMC_ST_ERR_NO_PARTITION; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_GetPartitionCapacity (U16 u16_PartType, U32 *pu32_Cap) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(eMMC_PART_FAT == u16_PartType) ++ *pu32_Cap = g_eMMCDrv.u32_FATSectorCnt; ++ else ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ *pu32_Cap = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ReadPartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_R); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_R fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ return u32_err; ++} ++ ++ ++U32 eMMC_WritePartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_WriteData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_W fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_GetDevInfo(eMMC_INFO_t *peMMCInfo_t) ++{ ++ const char *str = "MSTARSEMIUNFDCIS"; ++ ++ memcpy(peMMCInfo_t->au8_Tag, str, 16); ++ peMMCInfo_t->u8_IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(peMMCInfo_t->au8_ID, g_eMMCDrv.au8_ID, g_eMMCDrv.u8_IDByteCnt); ++ peMMCInfo_t->u16_SpareByteCnt = 1; ++ peMMCInfo_t->u16_PageByteCnt = eMMC_SECTOR_512BYTE; ++ peMMCInfo_t->u16_BlkPageCnt = g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u16_BlkCnt = g_eMMCDrv.u32_SEC_COUNT / g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u32_ChkSum = eMMC_ChkSum((U8*)&peMMCInfo_t->u16_SpareByteCnt, 0x32 - 0x24); ++ ++ memcpy(peMMCInfo_t->au8_Vendor, g_eMMCDrv.au8_Vendor, 16); ++ memcpy(peMMCInfo_t->au8_PartNumber, g_eMMCDrv.au8_PartNumber, 16); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ErasePartition(U16 u16_PartType) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_PartLogiIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ u32_PartLogiIdx++; ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ break; ++ } ++ } ++ ++ if(0 == u32_PartLogiIdx) ++ return u32_err; ++ ++ u32_err = eMMC_BootPartitionHandler_E(u16_PartType); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler fail: %Xh\n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++// erase partitions following eMMC_PART_NVRAMBAK ++U32 eMMC_EraseAllPartitions(void) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx=0, u16_PartIdx_tmp; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_NVRAMBAK, ++ u32_PartLogiIdx, &u16_PartIdx_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u16_PartIdx = u16_PartIdx_tmp; ++ u32_PartLogiIdx++; ++ } ++ ++ for(; u16_PartIdx < pPartInfo->u16_PartCnt; u16_PartIdx++) ++ { ++ // skip some partitions can not be erased ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++ if(eMMC_PART_DEV_NODE == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_E2PBAK == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_NVRAMBAK == pPartInfo->records[u16_PartIdx].u16_PartType) ++ continue; ++ #endif ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ return u32_err; ++ } ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseAll(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_EraseBlock(0, g_eMMCDrv.u32_SEC_COUNT-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: fail: %Xh \n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseBlock(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_EraseBlock fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseBlock( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 fail 0, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ // clear Access Boot Partition ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ // write Boot Code ++ u16_SecCnt = (u32_DataByteCnt>>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Boot Data keeps %Xh sectors, ChkSum: %Xh \n", ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, u16_SecCnt<<9)); ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, BOOT_PART_TOTAL_CNT<<9)); ++ ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u16_SecCnt<name, "Mstar-eMMC"); ++ mmc->has_init = 1; ++ mmc->capacity = g_eMMCDrv.u32_SEC_COUNT << 9; ++ ++ ++ eMMC_GetExtCSD((U8*)mmc->ext_csd); ++ ++ mmc->high_capacity = g_eMMCDrv.u8_IfSectorMode; ++ mmc->bus_width = g_eMMCDrv.u8_BUS_WIDTH << 1; ++ ++ switch (g_eMMCDrv.u8_SPEC_VERS) { ++ case 0: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ case 1: ++ mmc->version = MMC_VERSION_1_4; ++ break; ++ case 2: ++ mmc->version = MMC_VERSION_2_2; ++ break; ++ case 3: ++ mmc->version = MMC_VERSION_3; ++ break; ++ case 4: ++ mmc->version = MMC_VERSION_4; ++ break; ++ default: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ } ++ ++ /* divide frequency by 10, since the mults are 10x bigger */ ++ ++ mmc->tran_speed = fbase[( g_eMMCDrv.u8_Tran_Speed & 0x7)] * multipliers[((g_eMMCDrv.u8_Tran_Speed >> 3) & 0xf)]; ++ ++ // reliable write is supported ++ if ((mmc->ext_csd[EXT_CSD_WR_REL_SET] & 0x01) == 1) // reliable write is configured ++ mmc->reliable_write = 2; ++ else if((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[EXT_CSD_WR_REL_PARAM] & 0x1) == 0x1)) ++ { ++ mmc->reliable_write = 1; // reliable write is supported but not configured ++ //printf("[%s]\treliable write is supported\n", __func__); ++ } ++ else ++ { ++ mmc->reliable_write = 0; // reliable write is unsupported ++ //printf("[%s]\treliable write is unsupported\n", __func__); ++ } ++ ++ if ((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[160] & 0x3) == 3)) ++ { ++ mmc->slc_size = ((mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_0] ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_1]) << 8) ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_2]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ mmc->max_slc_size = ((mmc->ext_csd[157] ++ | ((u32)(mmc->ext_csd[158]) << 8) ++ | ((u32)(mmc->ext_csd[159]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ //printf("[%s]\t slc_size = %lld, max_slc_size = %lld\n",__func__, mmc->slc_size, mmc->max_slc_size); ++ } ++ else // slc mode is unsupported ++ { ++ mmc->slc_size = mmc->max_slc_size = 0; ++ //printf("[%s]\t slc mode is unsupported\n",__func__); ++ } ++ ++ ++ { ++ U16 u16_i; ++ for(u16_i = 0; u16_i < 4; u16_i ++) ++ { ++ if(u16_i < 3) ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8 | g_eMMCDrv.au8_CID[u16_i * 4 + 4]; ++ else ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8; ++ } ++ } ++ ++ mmc->read_bl_len = 512; ++ mmc->write_bl_len = 512; ++ mmc->block_dev.lun = 0; ++ mmc->block_dev.type = 0; ++ mmc->block_dev.blksz = 512; ++ mmc->block_dev.lba = g_eMMCDrv.u32_SEC_COUNT; ++ mmc->block_dev.part_type = PART_TYPE_EMMC; ++ sprintf(mmc->block_dev.vendor, "Man %06x Snr %08x", mmc->cid[0] >> 8, ++ (mmc->cid[2] << 8) | (mmc->cid[3] >> 24)); ++ sprintf(mmc->block_dev.product, "%c%c%c%c%c", mmc->cid[0] & 0xff, ++ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, ++ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); ++ sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28, ++ (mmc->cid[2] >> 24) & 0xf); ++ ++// init_part(&mmc->block_dev); ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ struct mmc* mmc = NULL; ++ ++ mmc = malloc(sizeof(struct mmc)); // uboot origianl design, don't free it. ++ if (!mmc) ++ return -ENOMEM; ++ memset(mmc, 0, sizeof(struct mmc)); ++ ++ eMMC_mmc_Init(mmc); ++ ++ mmc_register(mmc); ++ ++ mmc->block_dev.block_read = eMMC_bread; ++ mmc->block_dev.block_write = eMMC_bwrite; ++ mmc->block_dev.block_erase = eMMC_berase; ++ ++ return 0; // uboot origianl design, don't free mmc. ++} ++ ++#endif ++ ++#define eMMC_NOT_READY_MARK ~(('e'<<24)|('M'<<16)|('M'<<8)|'C') ++static U32 sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++ ++static U32 eMMC_Init_Ex(void) ++{ ++ U32 u32_err; ++ ++ //only for Cedric xxxxx ++ /* ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT3); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT3); ++ */ ++ ++ ++ ++ // --------------------------------- ++ u32_err = eMMC_CheckAlignPack(eMMC_CACHE_LINE); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ // --------------------------------- ++ // init platform & FCIE ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ // --------------------------------- ++ u32_err = eMMC_Init_Device(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ sgu32_IfReadyGuard = ~eMMC_NOT_READY_MARK; ++ ++ LABEL_INIT_END: ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ ++ // --------------------------------- ++ // setup ID ++ // use first 10 bytes of CID ++ memcpy(g_eMMCDrv.au8_ID, &g_eMMCDrv.au8_CID[1], eMMC_ID_FROM_CID_BYTE_CNT); ++ g_eMMCDrv.u8_IDByteCnt = eMMC_ID_DEFAULT_BYTE_CNT; ++ // add a 11-th byte for number of GB ++ g_eMMCDrv.au8_ID[eMMC_ID_FROM_CID_BYTE_CNT] = ++ (g_eMMCDrv.u32_SEC_COUNT >> (1+10+10)) + 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "eMMC %uMB\n", g_eMMCDrv.u32_SEC_COUNT>>11); ++ //eMMC_dump_mem(g_eMMCDrv.au8_ID, 0x10); ++ #if 0 ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Err: eMMC Init, no pni, :%Xh\n", u32_err); ++ return eMMC_ST_ERR_NO_CIS; ++ } ++ //eMMC_DumpDriverStatus(); ++ #endif ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Init_Device(void) ++{ ++ U32 u32_err; ++ #if IF_DETECT_eMMC_DDR_TIMING ++ static U8 su8_IfNotBuildDDR=0; ++ #endif ++ U8 u8_eMMC_Identify_retry; ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: Rsp from RAM\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSPFROMRAM_SAVE; ++ #endif ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_INIT_DONE; ++ ++ eMMC_PlatformInit(); ++ // init eMMC device ++ u8_eMMC_Identify_retry = 0; ++EMMC_IDENTIFY: //20130515 ++ u32_err = eMMC_Identify(); ++ if(u32_err) ++ { ++ eMMC_printf("eMMC Err: Identify fail, %X\r\n", u32_err); ++ u8_eMMC_Identify_retry ++; ++ if (u8_eMMC_Identify_retry < 3) ++ goto EMMC_IDENTIFY; ++ else ++ goto LABEL_INIT_END; ++ } ++ ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ ++ // determine device parameters, from CSD ++ u32_err = eMMC_CSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ // setup eMMC device ++ // CMD7 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ #if eMMC_RSP_FROM_RAM ++ u32_err = eMMC_CMD16(eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ #endif ++ ++ // determine device parameters, from Ext_CSD ++ u32_err = eMMC_ExtCSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ // --------------------------------- ++ u32_err = eMMC_SetBusWidth(8, 0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ u32_err = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_INIT_DONE; ++ ++ //eMMC_DumpDriverStatus(); ++ #if IF_DETECT_eMMC_DDR_TIMING //iantest ++ eMMC_printf("eMMC_FCIE_EnableDDRMode\r\n"); ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableDDRMode()) ++ { ++ eMMC_printf("eMMC_ST_SUCCESS != eMMC_FCIE_EnableDDRMode()\r\n"); ++ #if IF_DETECT_eMMC_DDR_TIMING ++ if(0==su8_IfNotBuildDDR) ++ { ++ su8_IfNotBuildDDR = 1; ++ eMMC_FCIE_BuildDDRTimingTable(); ++ } ++ #endif ++ } ++ #else ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_CMD18(0, gau8_eMMC_SectorBuf, 1); // get CMD12 Rsp ++ #endif ++ #endif ++ ++ //eMMC_dump_mem(g_eMMCDrv.au8_AllRsp, 0x100); ++ ++ LABEL_INIT_END: ++ return u32_err; ++} ++ ++ ++U32 eMMC_CheckIfReady(void) ++{ ++ if(eMMC_NOT_READY_MARK != sgu32_IfReadyGuard) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_Init_Ex(); ++} ++ ++void eMMC_ResetReadyFlag(void) ++{ ++ sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseCMDSeq(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 0: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseCMDSeq( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 1, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ return u32_err; ++} ++ ++U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ volatile U16 u16_BlkCnt; ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ ++ if(NULL == pu8_DataBuf) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w data buf is NULL: %Xh \n", (U32)pu8_DataBuf); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD25(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD24(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: W fail: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ return u32_err; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ volatile U16 u16_BlkCnt; ++ U8 u8_IfNotCacheLineAligned=0; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ // first 512 bytes, special handle if not cache line aligned ++ if((U32)pu8_DataBuf & (eMMC_CACHE_LINE-1)) ++ { ++ #if 0 ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING,1, ++ "eMMC Warn: R, buffer not Cache Line aligned: %Xh \n", ++ (U32)pu8_DataBuf); ++ #endif ++ ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.0: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ return u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ u32_BlkAddr += 1; ++ pu8_DataBuf += eMMC_SECTOR_512BYTE; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ ++ // last 512B must be not cache line aligned, ++ // reserved for last eMMC_CMD17_CIFD ++ if(u32_DataByteCnt){ ++ u8_IfNotCacheLineAligned = 1; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ } ++ } ++ ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD18(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD17(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.1: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ // last 512 bytes, special handle if not cache line aligned ++ if(u8_IfNotCacheLineAligned) ++ { ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.2: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ } ++ ++ return u32_err; ++} ++ ++ ++ ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++U32 eMMC_SearchDevNodeStartSector(void) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: init fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_DEV_NODE, 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: GetPartitionIndex fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ g_eMMCDrv.u32_PartDevNodeStartSector = pPartInfo->records[u16_PartIdx].u16_StartBlk; ++ g_eMMCDrv.u32_PartDevNodeStartSector *= pPartInfo->u16_BlkPageCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt *= pPartInfo->u16_BlkPageCnt; ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++ #endif ++ ++int get_NVRAM_start_sector(unsigned int *u32_startsector) ++{ ++ ++ ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ U16 u16_PartIdx; ++ if(eMMC_ST_SUCCESS==eMMC_GetPartitionIndex(eMMC_PART_NVRAM, 0, &u16_PartIdx)) ++ { ++ *u32_startsector = pPartInfo->records[u16_PartIdx].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ printk(KERN_INFO"eMMC_PART_NVRAM start sector: %X\r\n",*u32_startsector); ++ return 0; ++ } ++ ++ ++ return -1; ++} ++ ++//only support p1~p7 for each EMMC device in Linux ++int get_NVRAM_max_part_count(void) ++{ ++ //eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ //return (pPartInfo->u16_PartCnt-1); ++ return 0x0C; ++} ++ ++ ++int get_DEVNODE_start_sector(unsigned int *u32_startsector) ++{ ++ u32 u32_err; ++ if(0 == g_eMMCDrv.u32_PartDevNodeStartSector){ ++ u32_err = eMMC_SearchDevNodeStartSector(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ printk(KERN_ERR"** Err, %s **\n", __func__); ++ return (-1); ++ } ++ } ++ ++ *u32_startsector=g_eMMCDrv.u32_PartDevNodeStartSector; ++ ++ ++ return 0; ++ ++} ++ ++ ++EXPORT_SYMBOL(get_DEVNODE_start_sector); ++EXPORT_SYMBOL(get_NVRAM_max_part_count); ++ ++#endif ++ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/src/common/cmd_mstar_emmc_bootloader.txt b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/cmd_mstar_emmc_bootloader.txt +new file mode 100644 +index 00000000..bee76431 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/cmd_mstar_emmc_bootloader.txt +@@ -0,0 +1,12352 @@ ++0x27,0x37,0x91,0x35,0x67,0x32,0x70,0x5F, ++0x62,0x6F,0x6F,0x74,0x6C,0x6F,0x61,0x64, ++0x65,0x72,0x00,0x00,0x4B,0x9A,0x08,0x75, ++0x00,0x10,0x00,0x20,0xE8,0xDA,0x00,0x00, ++0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, ++0x0F,0x0A,0xF0,0x4F,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x0E,0x00,0x00,0xEA,0x05,0x00,0x00,0xEA, ++0x05,0x00,0x00,0xEA,0x05,0x00,0x00,0xEA, ++0x05,0x00,0x00,0xEA,0x00,0x00,0x00,0x00, ++0x04,0x00,0x00,0xEA,0x05,0x00,0x00,0xEA, ++0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, ++0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, ++0xC4,0xD0,0x9F,0xE5,0x0D,0xF0,0xA0,0xE1, ++0xC0,0x80,0x9F,0xE5,0x08,0xF0,0xA0,0xE1, ++0xBC,0x40,0x9F,0xE5,0x6C,0x40,0x84,0xE2, ++0x04,0xF0,0xA0,0xE1,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0xB0,0x0F,0x10,0xEE, ++0x03,0x00,0x10,0xE2,0x00,0x00,0x50,0xE3, ++0x78,0x00,0x9F,0x05,0x10,0xFF,0x2F,0x01, ++0x74,0x10,0x9F,0xE5,0xC2,0x20,0xA0,0xE3, ++0x20,0x00,0x81,0xE5,0x24,0x20,0x81,0xE5, ++0x00,0xF0,0x20,0xE3,0xFD,0xFF,0xFF,0xEA, ++0x5C,0x10,0x9F,0xE5,0xA9,0x22,0x00,0xE3, ++0x00,0x20,0x81,0xE4,0x54,0x10,0x9F,0xE5, ++0xD1,0x00,0xA0,0xE3,0x00,0xF0,0x21,0xE1, ++0x00,0xD0,0x41,0xE2,0xD2,0x00,0xA0,0xE3, ++0x00,0xF0,0x21,0xE1,0x00,0xD0,0x41,0xE2, ++0xDB,0x00,0xA0,0xE3,0x00,0xF0,0x21,0xE1, ++0x00,0xD0,0x41,0xE2,0xD3,0x00,0xA0,0xE3, ++0x00,0xF0,0x21,0xE1,0x20,0xD0,0x41,0xE2, ++0x1C,0x10,0x9F,0xE5,0xB7,0x20,0xA0,0xE3, ++0x00,0x20,0x81,0xE4,0x06,0x00,0x00,0xEB, ++0xFE,0xFF,0xFF,0xEA,0xEC,0xE8,0x03,0x20, ++0xB4,0xE8,0x03,0x20,0x00,0x10,0x00,0x20, ++0xA8,0x10,0x00,0x20,0x00,0x3C,0x30,0x25, ++0x94,0xE4,0x02,0x20,0x00,0x00,0x00,0xEB, ++0xED,0xC1,0x00,0xEB,0x2C,0x00,0x8F,0xE2, ++0x00,0x0C,0x90,0xE8,0x00,0xA0,0x8A,0xE0, ++0x00,0xB0,0x8B,0xE0,0x01,0x70,0x4A,0xE2, ++0x0B,0x00,0x5A,0xE1,0x00,0x00,0x00,0x1A, ++0xE5,0xC1,0x00,0xEB,0x0F,0x00,0xBA,0xE8, ++0x18,0xE0,0x4F,0xE2,0x01,0x00,0x13,0xE3, ++0x03,0xF0,0x47,0x10,0x13,0xFF,0x2F,0xE1, ++0xB8,0x00,0x00,0x00,0x08,0x01,0x00,0x00, ++0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0x8A,0x18,0x03,0x78,0x01,0x30,0x5C,0x07, ++0x64,0x0F,0x01,0xD1,0x04,0x78,0x01,0x30, ++0x1D,0x11,0x01,0xD1,0x05,0x78,0x01,0x30, ++0x01,0x3C,0x05,0xD0,0x06,0x78,0x01,0x30, ++0x0E,0x70,0x01,0x31,0x01,0x3C,0xF9,0xD1, ++0x1E,0x07,0x06,0xD4,0x2E,0x1C,0x0E,0xD0, ++0x01,0x3E,0x8C,0x55,0xFC,0xD1,0x49,0x19, ++0x09,0xE0,0x04,0x78,0x01,0x30,0x0C,0x1B, ++0x01,0x35,0x26,0x78,0x01,0x34,0x0E,0x70, ++0x01,0x31,0x01,0x3D,0xF9,0xD5,0x91,0x42, ++0xD7,0xD3,0x70,0x47,0x10,0x20,0x52,0xE2, ++0x78,0x00,0xB0,0x28,0x78,0x00,0xA1,0x28, ++0xFB,0xFF,0xFF,0x8A,0x82,0x2E,0xB0,0xE1, ++0x30,0x00,0xB0,0x28,0x30,0x00,0xA1,0x28, ++0x00,0x40,0x90,0x45,0x00,0x40,0x81,0x45, ++0x1E,0xFF,0x2F,0xE1,0x00,0x30,0xB0,0xE3, ++0x00,0x40,0xB0,0xE3,0x00,0x50,0xB0,0xE3, ++0x00,0x60,0xB0,0xE3,0x10,0x20,0x52,0xE2, ++0x78,0x00,0xA1,0x28,0xFC,0xFF,0xFF,0x8A, ++0x82,0x2E,0xB0,0xE1,0x30,0x00,0xA1,0x28, ++0x00,0x30,0x81,0x45,0x1E,0xFF,0x2F,0xE1, ++0x58,0x12,0x00,0x20,0x00,0x00,0x02,0x20, ++0x00,0x10,0x00,0x00,0x58,0x11,0x00,0x20, ++0x7C,0x12,0x00,0x20,0x00,0x10,0x02,0x20, ++0x00,0x40,0x00,0x00,0x58,0x11,0x00,0x20, ++0x00,0x13,0x00,0x20,0x94,0x04,0x03,0x20, ++0xF4,0x00,0x00,0x00,0xB4,0x11,0x00,0x20, ++0xF4,0x13,0x00,0x20,0xEC,0x17,0x03,0x20, ++0xF4,0xD6,0x00,0x00,0xB4,0x11,0x00,0x20, ++0xF4,0x13,0x00,0x20,0x88,0x05,0x03,0x20, ++0x64,0x12,0x00,0x00,0xDC,0x11,0x00,0x20, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0x10,0x00,0x00,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0x40,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x01,0x20,0x00,0x80,0x01,0x20, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xBC,0xB2,0xB2,0x9A,0x03,0x05,0x07,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x12,0x01,0x10,0x01,0x00,0x00,0x00,0x40, ++0x20,0x1B,0x00,0x03,0x00,0x01,0x00,0x00, ++0x00,0x01,0x0A,0x06,0x00,0x02,0x00,0x00, ++0x00,0x40,0x01,0x00,0x09,0x07,0x20,0x00, ++0x01,0x01,0x00,0xC0,0x00,0x09,0x04,0x00, ++0x00,0x02,0x08,0x06,0x50,0x00,0x07,0x05, ++0x81,0x02,0x40,0x00,0x00,0x07,0x05,0x02, ++0x02,0x40,0x00,0x00,0x09,0x02,0x20,0x00, ++0x01,0x01,0x00,0xC0,0x00,0x09,0x04,0x00, ++0x00,0x02,0x08,0x06,0x50,0x00,0x07,0x05, ++0x81,0x02,0x40,0x00,0x00,0x07,0x05,0x02, ++0x02,0x40,0x00,0x00,0x04,0x03,0x09,0x04, ++0x28,0x03,0x4D,0x00,0x61,0x00,0x73,0x00, ++0x73,0x00,0x20,0x00,0x53,0x00,0x74,0x00, ++0x6F,0x00,0x72,0x00,0x61,0x00,0x67,0x00, ++0x65,0x00,0x20,0x00,0x44,0x00,0x65,0x00, ++0x76,0x00,0x69,0x00,0x63,0x00,0x65,0x00, ++0x12,0x03,0x42,0x00,0x69,0x00,0x67,0x00, ++0x42,0x00,0x6C,0x00,0x75,0x00,0x65,0x00, ++0x34,0x00,0x00,0x00,0x30,0xEC,0x03,0x20, ++0x5A,0xA5,0x00,0x00,0x89,0x12,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x6E,0x00,0x51,0xE3, ++0x75,0x2F,0x00,0x0A,0x70,0x00,0x51,0xE3, ++0xF1,0x2C,0x00,0x0A,0x66,0x00,0x51,0xE3, ++0xC4,0x34,0x00,0x0A,0x65,0x00,0x51,0xE3, ++0xC2,0x34,0x00,0x0A,0x67,0x00,0x51,0xE3, ++0xC0,0x34,0x00,0x0A,0x61,0x00,0x51,0xE3, ++0x00,0x00,0xA0,0xE1,0x00,0x30,0x90,0xE5, ++0x23,0x34,0xB0,0xE1,0x80,0x10,0x81,0x23, ++0x69,0x00,0x51,0xE3,0x49,0x2F,0x00,0x0A, ++0x64,0x00,0x51,0xE3,0x47,0x2F,0x00,0x0A, ++0x75,0x00,0x51,0xE3,0x45,0x2F,0x00,0x0A, ++0x6F,0x00,0x51,0xE3,0xD3,0x2F,0x00,0x0A, ++0x78,0x00,0x51,0xE3,0x6A,0x34,0x00,0x0A, ++0xE9,0x00,0x51,0xE3,0xAA,0x2F,0x00,0x0A, ++0xE4,0x00,0x51,0xE3,0xA8,0x2F,0x00,0x0A, ++0xF5,0x00,0x51,0xE3,0xA6,0x2F,0x00,0x0A, ++0xEF,0x00,0x51,0xE3,0x64,0x34,0x00,0x0A, ++0xF8,0x00,0x51,0xE3,0x64,0x34,0x00,0x0A, ++0x00,0x30,0x90,0xE5,0xA3,0x33,0xB0,0xE1, ++0x80,0x10,0x81,0x23,0x63,0x00,0x51,0xE3, ++0x51,0x31,0x00,0x0A,0x73,0x00,0x51,0xE3, ++0x5F,0x34,0x00,0x0A,0xE3,0x00,0x51,0xE3, ++0x5B,0x31,0x00,0x0A,0xF3,0x00,0x51,0xE3, ++0x5D,0x34,0x00,0x0A,0x00,0x00,0xB0,0xE3, ++0x1E,0xFF,0x2F,0xE1,0x1F,0xB5,0x0D,0xF0, ++0x2E,0xE9,0x0C,0xF0,0x16,0xE8,0x04,0x00, ++0x00,0x20,0x00,0x21,0x0D,0xF0,0xDE,0xE8, ++0x40,0x1C,0x60,0x60,0x00,0x20,0x00,0x21, ++0x0D,0xF0,0xFC,0xE8,0xE0,0x60,0x1F,0xBD, ++0x10,0xB5,0x10,0xBD,0x7E,0x31,0x00,0xEB, ++0x02,0x10,0xA0,0xE1,0xF2,0xFF,0xFF,0xFA, ++0x1C,0xC0,0x9F,0xE5,0x0F,0xC0,0x8C,0xE0, ++0x01,0x00,0x1C,0xE3,0x0D,0xE0,0x8F,0x12, ++0x0F,0xE0,0xA0,0x01,0x1C,0xFF,0x2F,0xE1, ++0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0x0C,0xF0,0xBC,0xFB,0xA9,0x00,0x00,0x00, ++0xF0,0xFF,0xFF,0xFA,0xE0,0x31,0x00,0xFA, ++0x2D,0xE9,0xF0,0x41,0x04,0x00,0x0F,0x46, ++0x4F,0xF0,0x00,0x05,0x37,0xD0,0xA1,0x20, ++0x30,0x4E,0x30,0x60,0x2F,0xE0,0x75,0x60, ++0x38,0x46,0x0B,0xF0,0xF7,0xFA,0x02,0x46, ++0x39,0x46,0x20,0x46,0x0B,0xF0,0xA8,0xFA, ++0x18,0xBB,0xA3,0x20,0xC6,0xE9,0x00,0x04, ++0x38,0x46,0x0B,0xF0,0xEB,0xFA,0xB0,0x60, ++0x38,0x46,0x0B,0xF0,0xE7,0xFA,0x20,0x44, ++0x40,0x1C,0xF0,0x60,0x38,0x46,0x0B,0xF0, ++0xE1,0xFA,0x20,0x44,0x10,0x22,0x40,0x1C, ++0x00,0x21,0x0B,0xF0,0x57,0xFA,0x30,0x61, ++0xA4,0x20,0x30,0x60,0x38,0x46,0x0B,0xF0, ++0xD5,0xFA,0x20,0x44,0x10,0x22,0xBD,0xE8, ++0xF0,0x41,0x40,0x1C,0x00,0x21,0x0B,0xF0, ++0x49,0xBA,0x6D,0x1C,0x64,0x1C,0x20,0x78, ++0x08,0xB1,0xFF,0x2D,0xCB,0xDD,0x00,0x20, ++0xBD,0xE8,0xF0,0x81,0x70,0xB5,0xAB,0x20, ++0x12,0x4C,0x20,0x60,0x00,0xF0,0xAF,0xF8, ++0x15,0x48,0x11,0xA1,0xFF,0xF7,0xB4,0xFF, ++0x05,0x46,0x00,0xF0,0x1A,0xFC,0x12,0x49, ++0x2A,0x46,0x12,0xA0,0x00,0xF0,0x06,0xFC, ++0x16,0xA2,0x19,0xA1,0x1B,0xA0,0x00,0xF0, ++0x01,0xFC,0x0D,0x48,0x1E,0xA1,0xE0,0x60, ++0xFF,0xF7,0xA2,0xFF,0x0A,0x49,0xC2,0xB2, ++0x1E,0xA0,0x00,0xF0,0xF7,0xFB,0x25,0xA0, ++0x00,0xF0,0xF4,0xFB,0x00,0xF0,0xBA,0xFD, ++0xFE,0xE7,0x00,0x00,0x00,0x3C,0x30,0x25, ++0x64,0x65,0x62,0x75,0x67,0x5F,0x6D,0x65, ++0x6D,0x5F,0x74,0x61,0x69,0x6C,0x00,0x00, ++0x00,0xD0,0x02,0x20,0x52,0x4F,0x4D,0x20, ++0x70,0x61,0x72,0x61,0x6D,0x3A,0x25,0x78, ++0x2C,0x20,0x76,0x3D,0x30,0x78,0x25,0x78, ++0x0A,0x00,0x00,0x00,0x32,0x30,0x3A,0x35, ++0x34,0x3A,0x35,0x33,0x00,0x00,0x00,0x00, ++0x41,0x70,0x72,0x20,0x31,0x30,0x20,0x32, ++0x30,0x31,0x32,0x00,0x42,0x75,0x69,0x6C, ++0x74,0x20,0x6F,0x6E,0x20,0x25,0x73,0x20, ++0x61,0x74,0x20,0x25,0x73,0x0A,0x00,0x00, ++0x62,0x6F,0x6F,0x74,0x6D,0x6F,0x64,0x65, ++0x00,0x00,0x00,0x00,0x62,0x6F,0x6F,0x74, ++0x20,0x70,0x61,0x72,0x61,0x6D,0x3A,0x25, ++0x78,0x2C,0x20,0x62,0x6F,0x6F,0x74,0x6D, ++0x6F,0x64,0x65,0x3D,0x30,0x78,0x25,0x78, ++0x0A,0x00,0x00,0x00,0x2B,0x62,0x6F,0x6F, ++0x74,0x6C,0x6F,0x61,0x64,0x65,0x72,0x0A, ++0x00,0x00,0x00,0x00,0xD8,0x48,0x00,0x88, ++0xD8,0x49,0x08,0x60,0x70,0x47,0xD8,0x48, ++0x00,0x21,0x81,0x64,0x49,0x1E,0x01,0x64, ++0x82,0x21,0x81,0x64,0x70,0x47,0xD4,0x4A, ++0x01,0x21,0xD1,0x60,0x01,0xF0,0x16,0xB8, ++0x10,0xB5,0xC0,0x03,0x4F,0xF4,0x7A,0x71, ++0x0C,0xF0,0x02,0xEB,0x00,0xB9,0x01,0x20, ++0xCD,0x4C,0x00,0x21,0xA1,0x60,0x20,0x60, ++0x03,0x46,0xCC,0x4A,0x08,0x46,0x01,0xF0, ++0x63,0xF8,0x01,0x22,0x00,0x20,0x11,0x46, ++0x01,0xF0,0x6D,0xF8,0xA0,0x68,0x40,0xF0, ++0xE2,0x00,0xA0,0x60,0x10,0xBD,0xC6,0x49, ++0x08,0x88,0x20,0xF4,0x40,0x70,0x08,0x80, ++0x70,0x47,0xC4,0x49,0x08,0x68,0x40,0xF4, ++0x00,0x40,0x08,0x60,0xC0,0x49,0x7C,0x39, ++0x08,0x68,0x20,0xF4,0x60,0x40,0x40,0xF4, ++0xC0,0x40,0x08,0x60,0x70,0x47,0x10,0xB5, ++0xFF,0xF7,0xE9,0xFF,0xFF,0xF7,0xBA,0xFF, ++0x00,0xF0,0x38,0xFA,0xB5,0x49,0x02,0x28, ++0x01,0xD1,0xB9,0x48,0x07,0xE0,0x00,0xF0, ++0x31,0xFA,0x01,0x28,0x01,0xD1,0xB7,0x48, ++0x01,0xE0,0x4F,0xF4,0x00,0x40,0xAE,0x4A, ++0xC8,0x60,0x70,0x32,0x50,0x6F,0x20,0xF0, ++0x40,0x00,0x50,0x67,0xFF,0xF7,0xA7,0xFF, ++0xAD,0x48,0x40,0x38,0x01,0x68,0x21,0xF4, ++0x60,0x51,0x41,0xF4,0xC0,0x51,0x01,0x60, ++0x41,0x68,0x41,0xF0,0x01,0x01,0x41,0x60, ++0x90,0x8F,0x20,0xF4,0x10,0x40,0x90,0x87, ++0x00,0x20,0xA2,0xF8,0x0C,0x0D,0x52,0xF8, ++0x2C,0x0D,0x51,0x68,0xA6,0x4A,0x09,0x04, ++0xC0,0xEA,0x01,0x01,0x00,0x20,0x52,0xF8, ++0x20,0x30,0x41,0xF8,0x20,0x30,0x40,0x1C, ++0xFF,0x28,0xF8,0xD9,0x00,0x20,0xA1,0x49, ++0x08,0x62,0x48,0x62,0x08,0x61,0x48,0x61, ++0x88,0x60,0xC8,0x60,0x40,0x1E,0x88,0x61, ++0xC8,0x61,0x08,0x60,0x48,0x60,0x88,0x64, ++0xC8,0x64,0x40,0xF2,0x01,0x10,0x08,0x67, ++0x00,0x24,0x00,0x21,0x20,0x46,0x00,0xF0, ++0xAB,0xFF,0x64,0x1C,0xA4,0xB2,0x40,0x2C, ++0xF7,0xD3,0xBD,0xE8,0x10,0x40,0x0C,0xF0, ++0x35,0xBF,0x8A,0x4A,0xC0,0x43,0xF0,0xB5, ++0x10,0x32,0xC0,0xF3,0x07,0x21,0x16,0x68, ++0x4F,0xF0,0xFF,0x3C,0x55,0x68,0xC0,0xB2, ++0x0E,0x40,0x05,0x40,0x00,0x22,0x13,0x46, ++0x10,0x46,0x14,0x46,0x11,0x46,0x25,0xFA, ++0x01,0xF7,0xFF,0x07,0x01,0xD0,0x52,0x1C, ++0x08,0x46,0x26,0xFA,0x01,0xF7,0xFF,0x07, ++0x01,0xD0,0x5B,0x1C,0x0C,0x46,0x49,0x1C, ++0x08,0x29,0xF0,0xD3,0x01,0x2A,0x01,0xD1, ++0x01,0x2B,0x01,0xD0,0x60,0x46,0xF0,0xBD, ++0x04,0xF0,0x07,0x01,0x61,0xF3,0xDF,0x00, ++0xF0,0xBD,0x7D,0x49,0x2A,0x20,0x08,0x80, ++0x7C,0x48,0xB0,0xF8,0x60,0x02,0x00,0xF0, ++0x3F,0x00,0x70,0x47,0x78,0x49,0x28,0x20, ++0x08,0x80,0x79,0x48,0x01,0x68,0x6F,0xF3, ++0x0C,0x01,0x01,0x60,0x41,0x68,0x89,0xB2, ++0x41,0x60,0xA0,0xF5,0xC1,0x60,0x70,0x47, ++0x71,0x49,0x2B,0x20,0x2D,0xE9,0xF0,0x41, ++0x08,0x80,0x1E,0x20,0x00,0xF0,0xB8,0xF9, ++0x70,0x4F,0xB7,0xF8,0x04,0x66,0xFF,0xF7, ++0xDC,0xFF,0x04,0x46,0x61,0x48,0x4F,0xF4, ++0x7A,0x71,0xC0,0x68,0x0C,0xF0,0x24,0xEA, ++0x4F,0xF4,0xFA,0x61,0x00,0xFB,0x01,0xF5, ++0x30,0x46,0xFF,0xF7,0xA2,0xFF,0x02,0x46, ++0x21,0x46,0x67,0xA0,0x00,0xF0,0xA2,0xFA, ++0x00,0xF0,0x86,0xF9,0x05,0x44,0x30,0x46, ++0xFF,0xF7,0x97,0xFF,0xA0,0x42,0x1A,0xD1, ++0x3F,0x2C,0x18,0xD0,0x0D,0xE0,0xB7,0xF8, ++0x04,0x66,0x30,0x46,0xFF,0xF7,0x8D,0xFF, ++0xA0,0x42,0x06,0xD0,0x31,0x46,0x63,0xA0, ++0x00,0xF0,0x8C,0xFA,0x00,0x20,0xBD,0xE8, ++0xF0,0x81,0x00,0xF0,0x6D,0xF9,0xA8,0x42, ++0xED,0xD3,0x31,0x46,0x66,0xA0,0x00,0xF0, ++0x81,0xFA,0x01,0x20,0xF3,0xE7,0x31,0x46, ++0x6A,0xA0,0xED,0xE7,0x72,0x48,0x0E,0xB5, ++0x03,0x68,0x72,0x48,0x02,0x68,0x72,0x48, ++0x01,0x68,0x72,0x48,0x8D,0xE8,0x0E,0x00, ++0x4F,0xF4,0x80,0x71,0x03,0x68,0x70,0x4A, ++0x70,0x48,0x0A,0xF0,0x4D,0xFF,0x6F,0x48, ++0x0E,0xBD,0x2D,0xE9,0xF0,0x5F,0x00,0x24, ++0xDF,0xF8,0xB4,0x81,0x52,0x21,0x05,0x46, ++0xA8,0xF8,0x00,0x1C,0x01,0x46,0x6B,0xA0, ++0x00,0xF0,0x5C,0xFA,0x35,0x48,0x4F,0xF4, ++0x7A,0x71,0xC0,0x68,0x0C,0xF0,0xCC,0xE9, ++0x00,0xFB,0x05,0xF1,0x00,0xF0,0x38,0xF9, ++0x46,0x18,0x03,0xF0,0x50,0xFB,0xDF,0xF8, ++0x74,0xB1,0x4F,0xF4,0x72,0x4A,0xDF,0xF8, ++0xA4,0x91,0x33,0xE0,0xDB,0xF8,0x00,0x10, ++0x11,0xB1,0x59,0x48,0x00,0x68,0x88,0x47, ++0x20,0x04,0x04,0xF1,0x01,0x04,0x00,0x0C, ++0x02,0xD1,0x63,0xA0,0x00,0xF0,0x3A,0xFA, ++0x03,0xF0,0x44,0xFB,0x00,0x28,0x21,0xD0, ++0x60,0xA0,0x00,0xF0,0x33,0xFA,0x01,0xF0, ++0x0B,0xFD,0x67,0x48,0x49,0x46,0xD0,0xE9, ++0x06,0x75,0x66,0xA0,0x3A,0x46,0x2B,0x46, ++0x00,0xF0,0x28,0xFA,0x55,0x45,0x50,0x46, ++0x00,0xD9,0x05,0x46,0x31,0x20,0xA8,0xF8, ++0x00,0x0C,0x2A,0x46,0x49,0x46,0x38,0x46, ++0x0B,0xF0,0xF2,0xE8,0x02,0x20,0xFF,0xF7, ++0x9D,0xFF,0x39,0x46,0x64,0xA0,0x00,0xF0, ++0x15,0xFA,0xB8,0x47,0x00,0xF0,0xF8,0xF8, ++0xB0,0x42,0xC7,0xD3,0xBD,0xE8,0xF0,0x5F, ++0x67,0xA0,0x00,0xF0,0x0B,0xBA,0x0C,0x48, ++0x00,0x88,0x00,0xF0,0x0F,0x00,0x0C,0x28, ++0x0F,0xD2,0xDF,0xE8,0x00,0xF0,0x06,0x0A, ++0x06,0x08,0x0A,0x0C,0x08,0x0A,0x0C,0x06, ++0x0A,0x0C,0x01,0x20,0x70,0x47,0x02,0x20, ++0x70,0x47,0x03,0x20,0x70,0x47,0x04,0x20, ++0x70,0x47,0xFF,0x20,0x70,0x47,0x00,0x00, ++0x90,0x71,0x00,0x25,0x94,0x04,0x03,0x20, ++0x00,0x20,0x30,0x25,0x97,0x1A,0x03,0x20, ++0xC0,0x0B,0x02,0x25,0x14,0x3E,0x00,0x25, ++0x00,0xF0,0x49,0x02,0x80,0xBA,0x8C,0x01, ++0x00,0x10,0x00,0x20,0x14,0x0C,0x30,0x25, ++0x00,0x3C,0x30,0x25,0x00,0x20,0x00,0x25, ++0x08,0x06,0x30,0x25,0x00,0x00,0x30,0x25, ++0x50,0x72,0x65,0x73,0x73,0x65,0x64,0x5F, ++0x6B,0x65,0x79,0x28,0x25,0x78,0x29,0x2C, ++0x65,0x46,0x75,0x73,0x65,0x28,0x25,0x78, ++0x29,0x0A,0x00,0x00,0x72,0x65,0x6C,0x65, ++0x61,0x73,0x65,0x64,0x7C,0x50,0x72,0x65, ++0x73,0x73,0x65,0x64,0x5F,0x74,0x68,0x65, ++0x5F,0x77,0x72,0x6F,0x6E,0x67,0x5F,0x6B, ++0x65,0x79,0x28,0x25,0x78,0x29,0x0A,0x00, ++0x64,0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64, ++0x5F,0x4B,0x65,0x79,0x5F,0x70,0x72,0x65, ++0x73,0x73,0x65,0x64,0x28,0x25,0x78,0x29, ++0x0A,0x00,0x00,0x00,0x6E,0x6F,0x5F,0x6B, ++0x65,0x79,0x7C,0x50,0x72,0x65,0x73,0x73, ++0x65,0x64,0x5F,0x74,0x68,0x65,0x5F,0x77, ++0x72,0x6F,0x6E,0x67,0x5F,0x6B,0x65,0x79, ++0x28,0x25,0x78,0x29,0x0A,0x00,0x00,0x00, ++0xBC,0x04,0x03,0x20,0x80,0xD4,0x02,0x20, ++0x74,0xD4,0x02,0x20,0x78,0xD4,0x02,0x20, ++0x1C,0xEB,0x03,0x20,0x00,0xD0,0x02,0x20, ++0x00,0x30,0x30,0x25,0x73,0x79,0x73,0x5F, ++0x77,0x61,0x69,0x74,0x5F,0x62,0x6F,0x6F, ++0x74,0x73,0x74,0x72,0x61,0x70,0x28,0x25, ++0x64,0x29,0x6D,0x73,0x5B,0x49,0x4E,0x5D, ++0x0A,0x00,0x00,0x00,0x00,0x42,0x04,0x20, ++0x2E,0x00,0x00,0x00,0x0A,0x64,0x77,0x6C, ++0x64,0x20,0x62,0x6F,0x6F,0x74,0x73,0x74, ++0x72,0x61,0x70,0x20,0x66,0x72,0x6F,0x6D, ++0x20,0x55,0x53,0x42,0x2F,0x55,0x41,0x52, ++0x54,0x5B,0x4F,0x4B,0x5D,0x0A,0x00,0x00, ++0x00,0x40,0x04,0x20,0x20,0x63,0x6F,0x70, ++0x79,0x5F,0x44,0x57,0x4C,0x44,0x5F,0x52, ++0x41,0x4D,0x44,0x43,0x4F,0x44,0x45,0x28, ++0x25,0x6C,0x78,0x29,0x28,0x25,0x6C,0x78, ++0x29,0x28,0x25,0x6C,0x78,0x29,0x0A,0x00, ++0x46,0x69,0x6E,0x69,0x73,0x68,0x20,0x44, ++0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64,0x2C, ++0x20,0x6A,0x75,0x6D,0x70,0x28,0x30,0x78, ++0x25,0x6C,0x78,0x29,0x0A,0x0A,0x00,0x00, ++0x73,0x79,0x73,0x57,0x61,0x69,0x74,0x42, ++0x6F,0x6F,0x74,0x73,0x74,0x72,0x61,0x70, ++0x28,0x29,0x5F,0x74,0x69,0x6D,0x65,0x6F, ++0x75,0x74,0x21,0x0A,0x00,0x00,0x00,0x00, ++0x03,0x48,0x00,0x68,0x40,0x06,0x01,0xD5, ++0x01,0x20,0x70,0x47,0x02,0x20,0x70,0x47, ++0x94,0x04,0x03,0x20,0x03,0x48,0x00,0x68, ++0xC0,0x06,0x01,0xD5,0x02,0x20,0x70,0x47, ++0x01,0x20,0x70,0x47,0x94,0x04,0x03,0x20, ++0x01,0x48,0x40,0x6C,0xC0,0x43,0x70,0x47, ++0x00,0x20,0x30,0x25,0x70,0xB5,0x06,0x46, ++0xFF,0xF7,0xF6,0xFF,0x05,0x4C,0x05,0x46, ++0x4F,0xF4,0x7A,0x71,0x60,0x60,0xE0,0x68, ++0x0C,0xF0,0x7E,0xE8,0x06,0xFB,0x00,0x50, ++0xA0,0x60,0x70,0xBD,0x94,0x04,0x03,0x20, ++0x10,0xB5,0x04,0x46,0x08,0x48,0x4F,0xF4, ++0x7A,0x71,0xC0,0x68,0x0C,0xF0,0x70,0xE8, ++0x00,0xFB,0x04,0xF2,0xFF,0xF7,0xDC,0xFF, ++0x01,0x46,0xFF,0xF7,0xD9,0xFF,0x40,0x1A, ++0x90,0x42,0xFA,0xD3,0x10,0xBD,0x00,0x00, ++0x94,0x04,0x03,0x20,0x10,0xB5,0x04,0x46, ++0x08,0x48,0x07,0x49,0xC0,0x68,0x0C,0xF0, ++0x5C,0xE8,0x00,0xFB,0x04,0xF2,0xFF,0xF7, ++0xC7,0xFF,0x01,0x46,0xFF,0xF7,0xC4,0xFF, ++0x40,0x1A,0x90,0x42,0xFA,0xD3,0x10,0xBD, ++0x40,0x42,0x0F,0x00,0x94,0x04,0x03,0x20, ++0x04,0x48,0x00,0x68,0x00,0xF0,0x0F,0x00, ++0x08,0x28,0x01,0xD1,0x01,0x20,0x70,0x47, ++0x00,0x20,0x70,0x47,0x94,0x04,0x03,0x20, ++0x10,0xB5,0x04,0x46,0x09,0xB9,0x01,0x20, ++0x10,0xBD,0x49,0x1E,0x20,0x46,0xFF,0xF7, ++0xF7,0xFF,0x60,0x43,0x10,0xBD,0x09,0x28, ++0x01,0xD8,0x30,0x30,0x04,0xE0,0xA0,0xF1, ++0x0A,0x01,0x05,0x29,0x01,0xD8,0x37,0x30, ++0xC0,0xB2,0x70,0x47,0x2D,0xE9,0xF0,0x5F, ++0x01,0x25,0xDF,0xF8,0xA4,0xA0,0x05,0x24, ++0x06,0x46,0x4F,0xF4,0x7A,0x7B,0x4F,0xF0, ++0x00,0x09,0x0A,0x20,0x21,0x46,0xFF,0xF7, ++0xDB,0xFF,0x4F,0xEA,0xE0,0x78,0x07,0x46, ++0xA6,0xFB,0x0B,0x01,0xDA,0xF8,0x00,0x20, ++0x4B,0x46,0x0A,0xF0,0xEC,0xEB,0x43,0x46, ++0x3A,0x46,0x0A,0xF0,0xE8,0xEB,0x0A,0x21, ++0x0B,0xF0,0xCE,0xE8,0x01,0xB9,0x45,0xB9, ++0xC8,0xB2,0xFF,0xF7,0xD0,0xFF,0x19,0x4A, ++0x00,0x25,0x51,0x68,0x01,0xF8,0x01,0x0B, ++0x51,0x60,0x64,0x1E,0xDD,0xD5,0x2E,0x21, ++0x14,0x4F,0x01,0x24,0x5D,0x46,0x78,0x68, ++0x00,0xF8,0x01,0x1B,0x78,0x60,0x0A,0x20, ++0x21,0x46,0xFF,0xF7,0xB1,0xFF,0xC1,0x17, ++0x4B,0x46,0xA6,0xFB,0x00,0x20,0x06,0xFB, ++0x01,0x01,0xA5,0xFB,0x02,0x02,0x05,0xFB, ++0x01,0x21,0xDA,0xF8,0x00,0x20,0x0A,0xF0, ++0xBE,0xEB,0x0A,0x21,0x0B,0xF0,0xA4,0xE8, ++0xC8,0xB2,0xFF,0xF7,0xA8,0xFF,0x79,0x68, ++0x64,0x1C,0x02,0x2C,0x01,0xF8,0x01,0x0B, ++0x79,0x60,0xE0,0xDD,0xBD,0xE8,0xF0,0x9F, ++0xA0,0x04,0x03,0x20,0xB8,0x04,0x03,0x20, ++0x10,0xB5,0x3C,0x21,0x07,0x4C,0x60,0x68, ++0x00,0xF8,0x01,0x1B,0x60,0x60,0x06,0x48, ++0x40,0x6C,0xC0,0x43,0xFF,0xF7,0x9A,0xFF, ++0x60,0x68,0x3E,0x21,0x00,0xF8,0x01,0x1B, ++0x60,0x60,0x10,0xBD,0xB8,0x04,0x03,0x20, ++0x00,0x20,0x30,0x25,0x2D,0xE9,0xF0,0x41, ++0x07,0x46,0x30,0x4E,0x0D,0x46,0x30,0x4A, ++0x70,0x68,0x02,0xF1,0x20,0x04,0x01,0x44, ++0x91,0x42,0x0F,0xD9,0x00,0x21,0x02,0x46, ++0x01,0xE0,0x49,0x1C,0x52,0x1C,0xA2,0x42, ++0xFB,0xD3,0x00,0x29,0x02,0xDD,0x20,0x22, ++0x0A,0xF0,0xFA,0xEE,0x27,0x48,0x70,0x60, ++0x01,0x20,0x30,0x70,0xFF,0xF7,0xCC,0xFF, ++0x00,0x20,0x05,0xE0,0x71,0x68,0x3A,0x5C, ++0x40,0x1C,0x01,0xF8,0x01,0x2B,0x71,0x60, ++0xA8,0x42,0xF7,0xD3,0x30,0x78,0x01,0x28, ++0x16,0xD1,0x70,0x68,0x0A,0x21,0x00,0xF8, ++0x01,0x1B,0x00,0x21,0x03,0x46,0x70,0x60, ++0x01,0xE0,0x49,0x1C,0x5B,0x1C,0x42,0x5C, ++0x3C,0x2A,0x01,0xD0,0xA3,0x42,0xF8,0xD3, ++0x00,0x29,0x02,0xDD,0x20,0x22,0x0A,0xF0, ++0xD4,0xEE,0x70,0x68,0x40,0x1E,0x70,0x60, ++0xBD,0xE8,0xF0,0x81,0x0F,0xB4,0x40,0x21, ++0x11,0x48,0x10,0xB5,0x03,0xAB,0x02,0x9A, ++0x0A,0xF0,0xC0,0xFC,0x01,0x46,0x0E,0x48, ++0xFF,0xF7,0xB0,0xFF,0x10,0xBC,0x5D,0xF8, ++0x14,0xFB,0x10,0xB5,0x07,0x4C,0x10,0xB1, ++0x00,0xF5,0x00,0x70,0x00,0xE0,0x07,0x48, ++0x60,0x60,0x08,0xA0,0xFF,0xF7,0xE6,0xFF, ++0x61,0x68,0x0F,0xA0,0xBD,0xE8,0x10,0x40, ++0xE0,0xE7,0x00,0x00,0xB8,0x04,0x03,0x20, ++0xE0,0x0F,0x02,0x20,0x00,0x00,0x02,0x20, ++0x90,0x05,0x03,0x20,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x0A,0x00,0x00,0x00,0x00, ++0x62,0x6F,0x6F,0x74,0x6C,0x6F,0x61,0x64, ++0x65,0x72,0x20,0x43,0x75,0x72,0x72,0x65, ++0x6E,0x74,0x20,0x70,0x6F,0x69,0x6E,0x74, ++0x65,0x72,0x20,0x74,0x6F,0x20,0x70,0x44, ++0x65,0x62,0x75,0x67,0x4D,0x65,0x6D,0x20, ++0x61,0x64,0x64,0x72,0x65,0x73,0x73,0x20, ++0x25,0x6C,0x78,0x0A,0x00,0x00,0x00,0x00, ++0x38,0xB5,0xF9,0xA0,0xF7,0x49,0xFF,0xF7, ++0xA5,0xFF,0xFF,0xF7,0xCD,0xFE,0xFF,0x4C, ++0x00,0x23,0x00,0x93,0x20,0x23,0x00,0x22, ++0x21,0x68,0x18,0xB9,0x01,0x20,0x01,0xF0, ++0x1F,0xFF,0x03,0xE0,0x48,0xF2,0x01,0x00, ++0x02,0xF0,0x66,0xFC,0x50,0xB9,0xED,0x48, ++0x4F,0xF4,0x80,0x42,0x21,0x68,0x0A,0xF0, ++0x64,0xEE,0xBD,0xE8,0x38,0x40,0xF4,0xA0, ++0xFF,0xF7,0x88,0xBF,0xBD,0xE8,0x38,0x40, ++0x01,0x46,0xF8,0xA0,0xFF,0xF7,0x82,0xBF, ++0x2D,0xE9,0xF0,0x41,0x00,0x20,0xFE,0x4F, ++0x01,0x46,0x47,0xF8,0x20,0x10,0x40,0x1C, ++0x02,0x28,0xFA,0xD3,0xA5,0x22,0xDF,0x48, ++0x88,0x21,0x00,0xF0,0xFF,0xFE,0x05,0x00, ++0x20,0xD0,0xA5,0x22,0x88,0x21,0x28,0x46, ++0x00,0xF0,0xBA,0xFE,0x00,0x28,0x19,0xD0, ++0x00,0x24,0xF4,0x4E,0x13,0xE0,0x05,0xEB, ++0xC4,0x00,0x00,0x21,0x03,0x6A,0x4A,0x1C, ++0x32,0x43,0x9A,0x42,0x07,0xD1,0x42,0x6A, ++0xEF,0xA0,0x47,0xF8,0x21,0x20,0x49,0x1C, ++0xFF,0xF7,0x58,0xFF,0x02,0xE0,0x49,0x1C, ++0x02,0x29,0xF0,0xD3,0x64,0x1C,0xA8,0x8A, ++0xA0,0x42,0xE8,0xD8,0xBD,0xE8,0xF0,0x81, ++0x2D,0xE9,0xF0,0x41,0xA5,0x22,0xC9,0x48, ++0x81,0x21,0x00,0xF0,0xD3,0xFE,0x05,0x00, ++0xF4,0xD0,0xA5,0x22,0x81,0x21,0x28,0x46, ++0x00,0xF0,0x8E,0xFE,0x00,0x28,0xED,0xD0, ++0x00,0x24,0xE4,0x4E,0xE4,0x4F,0x13,0xE0, ++0x05,0xEB,0xC4,0x00,0x00,0x21,0x03,0x6A, ++0x4A,0x1C,0x32,0x43,0x9A,0x42,0x07,0xD1, ++0x42,0x6A,0xE0,0xA0,0x47,0xF8,0x21,0x20, ++0x49,0x1C,0xFF,0xF7,0x2B,0xFF,0x02,0xE0, ++0x49,0x1C,0x04,0x29,0xF0,0xD3,0x64,0x1C, ++0xA8,0x8A,0xA0,0x42,0xE8,0xD8,0xD1,0xE7, ++0xDD,0x49,0x00,0x20,0x08,0x60,0x48,0x60, ++0x70,0x47,0x70,0x47,0xD4,0x48,0x40,0x68, ++0xB0,0xF1,0x00,0x6F,0x05,0xD8,0x20,0xF0, ++0x03,0x01,0x4F,0xF0,0x00,0x40,0x0A,0xF0, ++0x71,0xBE,0x70,0x47,0x70,0x47,0xAB,0x48, ++0xA5,0x22,0x10,0xB5,0x87,0x21,0x00,0xF0, ++0x2E,0xFF,0xA8,0x48,0xA5,0x22,0x82,0x21, ++0x00,0xF0,0x29,0xFF,0xCF,0x49,0x40,0xF2, ++0xBE,0x60,0x08,0x80,0xCE,0xA0,0xFF,0xF7, ++0xFD,0xFE,0xA2,0x48,0xA5,0x22,0x83,0x21, ++0x00,0xF0,0x1D,0xFF,0x9F,0x48,0xA5,0x22, ++0x84,0x21,0x00,0xF0,0x18,0xFF,0xBD,0xE8, ++0x10,0x40,0xA5,0x22,0x9B,0x48,0x85,0x21, ++0x00,0xF0,0x11,0xBF,0x2D,0xE9,0xF8,0x43, ++0xFF,0xF7,0x12,0xFE,0xC7,0x4C,0x00,0x23, ++0x00,0x93,0x01,0x23,0x00,0x22,0x4C,0xF2, ++0x06,0x09,0x21,0x46,0x30,0xB9,0x06,0x20, ++0x01,0xF0,0x62,0xFE,0x50,0xB1,0x01,0x46, ++0xC1,0xA0,0x05,0xE0,0x48,0x46,0x02,0xF0, ++0xA7,0xFB,0x18,0xB1,0x01,0x46,0xC7,0xA0, ++0xFF,0xF7,0xD0,0xFE,0xCE,0x4A,0x21,0x68, ++0x91,0x42,0x02,0xD0,0xCD,0xA0,0xFF,0xF7, ++0xC9,0xFE,0x21,0x8C,0x02,0x29,0x03,0xD0, ++0x02,0x22,0xD4,0xA0,0xFF,0xF7,0xC2,0xFE, ++0xB4,0x4D,0xDD,0xA1,0x2D,0x1D,0x28,0x46, ++0x0A,0xF0,0x86,0xEE,0x20,0xB1,0xDD,0xA2, ++0x29,0x46,0xDE,0xA0,0xFF,0xF7,0xB6,0xFE, ++0x30,0x21,0x20,0x46,0x01,0xF0,0x0A,0xF8, ++0x21,0x6B,0x88,0x42,0x08,0xD0,0x30,0x21, ++0x20,0x46,0x01,0xF0,0x03,0xF8,0x21,0x6B, ++0x02,0x46,0xE0,0xA0,0xFF,0xF7,0xA6,0xFE, ++0xD4,0xE9,0x05,0x85,0xE8,0xA0,0xE7,0x6A, ++0xE6,0x69,0x29,0x46,0xFF,0xF7,0x9E,0xFE, ++0x31,0x46,0xEA,0xA0,0xFF,0xF7,0x9A,0xFE, ++0x41,0x46,0xEC,0xA0,0xFF,0xF7,0x96,0xFE, ++0x39,0x46,0xEF,0xA0,0xFF,0xF7,0x92,0xFE, ++0xFF,0xF7,0xBA,0xFD,0x4F,0xF0,0x00,0x03, ++0x01,0x21,0x00,0x93,0x00,0x28,0xE2,0x69, ++0xE0,0x6A,0x10,0x44,0x0A,0x46,0x01,0xEB, ++0x50,0x23,0x29,0x46,0x03,0xD1,0x06,0x20, ++0x01,0xF0,0x06,0xFE,0x02,0xE0,0x48,0x46, ++0x02,0xF0,0x4E,0xFB,0xF4,0x19,0x28,0x46, ++0x21,0x46,0x00,0xF0,0xCF,0xFF,0x40,0x45, ++0x08,0xD0,0x21,0x46,0x28,0x46,0x00,0xF0, ++0xC9,0xFF,0x01,0x46,0x42,0x46,0xE1,0xA0, ++0xFF,0xF7,0x6C,0xFE,0xFF,0xF7,0x5B,0xFF, ++0x7B,0x48,0x80,0x68,0x01,0x28,0x03,0xD1, ++0xE6,0xA0,0xFF,0xF7,0x63,0xFE,0xFE,0xE7, ++0xEA,0x48,0x00,0x21,0x80,0xF8,0x80,0x1D, ++0x80,0xF8,0x81,0x1D,0x80,0xF8,0x98,0x1D, ++0x80,0x22,0xA0,0xF8,0x50,0x23,0x15,0x22, ++0xA0,0xF8,0x38,0x23,0x03,0x22,0xA0,0xF8, ++0x50,0x23,0x07,0x22,0xA0,0xF8,0x48,0x23, ++0xE1,0x4A,0x11,0x80,0x20,0x21,0x91,0x87, ++0x68,0x21,0x01,0x80,0x4F,0xF4,0x90,0x71, ++0x81,0x80,0xDE,0x48,0x00,0x68,0x00,0xF0, ++0x76,0xF8,0x29,0x46,0xDC,0xA0,0xFF,0xF7, ++0x3D,0xFE,0xA8,0x47,0xDF,0xA0,0xFF,0xF7, ++0x39,0xFE,0xFE,0xE7,0x49,0x48,0x10,0xB5, ++0x02,0x68,0xD6,0x48,0x01,0x68,0xDE,0xA0, ++0xFF,0xF7,0x30,0xFE,0x00,0xF0,0x46,0xF8, ++0x20,0xB9,0x01,0x21,0xE4,0xA0,0xFF,0xF7, ++0x29,0xFE,0xFE,0xE7,0xE5,0xA0,0xFF,0xF7, ++0x25,0xFE,0xFF,0xF7,0x79,0xFE,0xFF,0xF7, ++0x9F,0xFE,0xFF,0xF7,0x4F,0xFB,0xFF,0xF7, ++0xEF,0xFC,0x02,0x28,0x02,0xD0,0xFF,0xF7, ++0x57,0xFB,0x50,0xB1,0xDF,0xA0,0xFF,0xF7, ++0x15,0xFE,0xFF,0xF7,0xA2,0xFA,0x01,0xF0, ++0x1D,0xF8,0x44,0xF6,0x20,0x60,0xFF,0xF7, ++0xA4,0xFB,0xDD,0xA0,0xFF,0xF7,0x0A,0xFE, ++0xFF,0xF7,0xBA,0xFE,0xDC,0xA0,0xFF,0xF7, ++0x05,0xFE,0xFF,0xF7,0xE1,0xFE,0xDC,0xA0, ++0xFF,0xF7,0x00,0xFE,0x23,0x48,0xA5,0x22, ++0x81,0x21,0x00,0xF0,0x20,0xFE,0xDA,0xA0, ++0xFF,0xF7,0xF8,0xFD,0x00,0xF0,0x06,0xFD, ++0xD9,0xA0,0xFF,0xF7,0xF3,0xFD,0xFF,0xF7, ++0xD5,0xFE,0xD9,0xA0,0xFF,0xF7,0xEE,0xFD, ++0xD9,0xA0,0xFF,0xF7,0xEB,0xFD,0xBD,0xE8, ++0x10,0x40,0xFB,0xE6,0x3A,0x49,0x00,0x20, ++0x10,0xB5,0x04,0x46,0x08,0x60,0x48,0x60, ++0x88,0x60,0xC8,0x60,0xFF,0xF7,0x08,0xFD, ++0x28,0xB9,0xD4,0xA0,0xFF,0xF7,0xDA,0xFD, ++0x01,0xF0,0x6E,0xF9,0x04,0xE0,0xD3,0xA0, ++0xFF,0xF7,0xD4,0xFD,0x02,0xF0,0x9C,0xFD, ++0x18,0xB9,0xD2,0xA0,0xFF,0xF7,0xCE,0xFD, ++0x01,0x24,0xE0,0xB2,0x10,0xBD,0x2D,0xE9, ++0xF0,0x41,0x06,0x46,0x07,0x4A,0x01,0x46, ++0xCE,0xA0,0xFF,0xF7,0xC3,0xFD,0x21,0x24, ++0x04,0x48,0xA5,0x22,0xE1,0xB2,0x0F,0x46, ++0x00,0xF0,0x48,0xFD,0x05,0x00,0x00,0xD0, ++0xA2,0xE1,0xB4,0xE1,0x00,0x10,0x02,0x20, ++0x5B,0x48,0x57,0x5F,0x43,0x46,0x47,0x5D, ++0x6C,0x6F,0x61,0x64,0x5F,0x6D,0x69,0x75, ++0x5F,0x70,0x61,0x72,0x74,0x69,0x74,0x69, ++0x6F,0x6E,0x5F,0x4F,0x4B,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0xB0,0x04,0x03,0x20, ++0x5B,0x48,0x57,0x5F,0x43,0x46,0x47,0x5D, ++0x52,0x65,0x61,0x64,0x5F,0x68,0x77,0x5F, ++0x63,0x6F,0x6E,0x66,0x69,0x67,0x5F,0x4F, ++0x4B,0x0A,0x00,0x00,0x5B,0x48,0x57,0x5F, ++0x43,0x46,0x47,0x5D,0x52,0x65,0x61,0x64, ++0x5F,0x68,0x77,0x5F,0x63,0x6F,0x6E,0x69, ++0x67,0x5F,0x46,0x61,0x69,0x6C,0x5F,0x28, ++0x25,0x6C,0x78,0x29,0x0A,0x00,0x00,0x00, ++0xA4,0x04,0x03,0x20,0x00,0x00,0xFD,0xFF, ++0x4B,0x65,0x79,0x42,0x69,0x74,0x73,0x4D, ++0x61,0x70,0x28,0x25,0x78,0x29,0x3D,0x25, ++0x78,0x0A,0x00,0x00,0x00,0x00,0xFE,0xFF, ++0xD0,0x05,0x03,0x20,0x62,0x6F,0x6F,0x74, ++0x5F,0x6F,0x70,0x74,0x28,0x25,0x78,0x29, ++0x3D,0x25,0x78,0x0A,0x00,0x00,0x00,0x00, ++0x00,0x3C,0x30,0x25,0x24,0x2B,0x00,0x25, ++0x73,0x65,0x74,0x5F,0x6D,0x63,0x75,0x5F, ++0x66,0x75,0x6C,0x6C,0x5F,0x73,0x70,0x65, ++0x65,0x64,0x0A,0x00,0x00,0xFE,0x1F,0x83, ++0x4E,0x41,0x4E,0x44,0x20,0x6C,0x6F,0x61, ++0x64,0x5F,0x75,0x62,0x6F,0x6F,0x74,0x5F, ++0x68,0x65,0x61,0x64,0x65,0x72,0x5B,0x46, ++0x41,0x49,0x4C,0x5D,0x28,0x25,0x6C,0x78, ++0x29,0x0A,0x00,0x00,0x65,0x4D,0x4D,0x43, ++0x20,0x6C,0x6F,0x61,0x64,0x5F,0x75,0x62, ++0x6F,0x6F,0x74,0x5F,0x68,0x65,0x61,0x64, ++0x65,0x72,0x5B,0x46,0x41,0x49,0x4C,0x5D, ++0x28,0x25,0x6C,0x78,0x29,0x0A,0x00,0x00, ++0x27,0x37,0x91,0x35,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x6D,0x61,0x67,0x69,0x63,0x28, ++0x58,0x5F,0x25,0x6C,0x78,0x2C,0x4F,0x5F, ++0x25,0x6C,0x78,0x29,0x5B,0x4E,0x47,0x5D, ++0x0A,0x00,0x00,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x69,0x6D,0x67,0x5F,0x74,0x79, ++0x70,0x65,0x28,0x58,0x5F,0x25,0x6C,0x78, ++0x2C,0x4F,0x5F,0x25,0x6C,0x78,0x29,0x5B, ++0x4E,0x47,0x5D,0x0A,0x00,0x00,0x00,0x00, ++0x47,0x32,0x50,0x55,0x42,0x4F,0x4F,0x54, ++0x00,0x00,0x00,0x00,0x47,0x32,0x55,0x42, ++0x4F,0x4F,0x54,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x69,0x6D,0x67,0x5F,0x6E,0x61, ++0x6D,0x65,0x28,0x58,0x5F,0x25,0x73,0x2C, ++0x4F,0x5F,0x25,0x73,0x29,0x5B,0x4E,0x47, ++0x5D,0x0A,0x00,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x63,0x68,0x65,0x63,0x6B,0x73, ++0x75,0x6D,0x28,0x58,0x5F,0x25,0x6C,0x78, ++0x2C,0x4F,0x5F,0x25,0x6C,0x78,0x29,0x5B, ++0x4E,0x47,0x5D,0x0A,0x00,0x00,0x00,0x00, ++0x4C,0x6F,0x61,0x64,0x41,0x64,0x64,0x72, ++0x65,0x73,0x73,0x28,0x25,0x6C,0x78,0x29, ++0x0A,0x00,0x00,0x00,0x49,0x6D,0x61,0x67, ++0x65,0x53,0x69,0x7A,0x65,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x49,0x6D,0x61,0x67, ++0x65,0x43,0x68,0x6B,0x73,0x75,0x6D,0x28, ++0x25,0x6C,0x78,0x29,0x0A,0x00,0x00,0x00, ++0x53,0x69,0x67,0x6E,0x61,0x74,0x75,0x72, ++0x65,0x53,0x69,0x7A,0x65,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x69,0x6D,0x61,0x67,0x65, ++0x5F,0x63,0x68,0x65,0x63,0x6B,0x73,0x75, ++0x6D,0x28,0x58,0x5F,0x25,0x6C,0x78,0x2C, ++0x4F,0x5F,0x25,0x6C,0x78,0x29,0x5B,0x4E, ++0x47,0x5D,0x0A,0x00,0x6C,0x6F,0x6F,0x70, ++0x5F,0x62,0x79,0x5F,0x62,0x6F,0x6F,0x74, ++0x5F,0x6F,0x70,0x74,0x69,0x6F,0x6E,0x0A, ++0x00,0x00,0x00,0x00,0xC8,0x70,0x00,0x25, ++0x14,0x2C,0x02,0x25,0xAC,0x04,0x03,0x20, ++0x6A,0x75,0x6D,0x70,0x20,0x74,0x6F,0x20, ++0x75,0x62,0x6F,0x6F,0x74,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x66,0x61,0x69,0x6C, ++0x20,0x6C,0x6F,0x6F,0x70,0x0A,0x00,0x00, ++0x67,0x75,0x38,0x75,0x63,0x44,0x6D,0x61, ++0x42,0x75,0x66,0x3D,0x30,0x78,0x25,0x78, ++0x2C,0x20,0x67,0x75,0x38,0x75,0x63,0x54, ++0x65,0x6D,0x70,0x42,0x75,0x66,0x3D,0x30, ++0x78,0x25,0x78,0x0A,0x00,0x00,0x00,0x00, ++0x45,0x72,0x72,0x5B,0x25,0x78,0x5D,0x0A, ++0x00,0x00,0x00,0x00,0x31,0x31,0x31,0x0A, ++0x00,0x00,0x00,0x00,0x44,0x57,0x4C,0x20, ++0x42,0x73,0x74,0x0A,0x00,0x00,0x00,0x00, ++0x32,0x32,0x32,0x0A,0x00,0x00,0x00,0x00, ++0x33,0x33,0x33,0x0A,0x00,0x00,0x00,0x00, ++0x34,0x34,0x34,0x0A,0x00,0x00,0x00,0x00, ++0x35,0x35,0x35,0x0A,0x00,0x00,0x00,0x00, ++0x36,0x36,0x36,0x0A,0x00,0x00,0x00,0x00, ++0x37,0x37,0x37,0x0A,0x00,0x00,0x00,0x00, ++0x62,0x6F,0x6F,0x74,0x5F,0x75,0x62,0x6F, ++0x6F,0x74,0x0A,0x00,0x4E,0x41,0x4E,0x44, ++0x0A,0x00,0x00,0x00,0x65,0x4D,0x4D,0x43, ++0x0A,0x00,0x00,0x00,0x20,0x4F,0x4B,0x0A, ++0x00,0x00,0x00,0x00,0x49,0x4D,0x49,0x5F, ++0x61,0x64,0x64,0x72,0x28,0x25,0x6C,0x78, ++0x29,0x5F,0x67,0x75,0x38,0x48,0x57,0x63, ++0x6F,0x6E,0x66,0x69,0x67,0x42,0x75,0x66, ++0x28,0x30,0x78,0x25,0x78,0x29,0x0A,0x00, ++0xA5,0x22,0x39,0x46,0x28,0x46,0x00,0xF0, ++0x5F,0xFB,0x60,0xB1,0xA8,0x8A,0x44,0xEA, ++0x00,0x40,0x01,0xC6,0x28,0x46,0xAA,0x8A, ++0x31,0x46,0x00,0xF0,0x0E,0xF8,0xA8,0x8A, ++0x06,0xEB,0xC0,0x06,0x04,0xE0,0x22,0x46, ++0x29,0x46,0x17,0xA0,0xFF,0xF7,0xFE,0xFB, ++0x64,0x1C,0x2F,0x2C,0x7F,0xF7,0x38,0xAE, ++0xA8,0xE4,0x2D,0xE9,0xF0,0x41,0x06,0x46, ++0x00,0x25,0x0C,0x46,0x17,0x46,0x17,0xA0, ++0xFF,0xF7,0xF0,0xFB,0x00,0x20,0x16,0xE0, ++0x06,0xEB,0xC0,0x01,0x0A,0x6A,0x53,0x1C, ++0x0B,0xD1,0x4A,0x6A,0x52,0x1C,0x0D,0xD1, ++0x40,0x1C,0x15,0x4A,0x22,0x60,0x89,0x6A, ++0x44,0xF8,0x04,0x1F,0x24,0x1D,0x6D,0x1C, ++0x04,0xE0,0x22,0x60,0x49,0x6A,0x44,0xF8, ++0x04,0x1F,0x24,0x1D,0x40,0x1C,0x79,0x19, ++0x81,0x42,0xE5,0xD8,0x82,0xE4,0x00,0x00, ++0x5B,0x48,0x57,0x5F,0x43,0x46,0x47,0x5D, ++0x28,0x30,0x78,0x25,0x78,0x29,0x46,0x61, ++0x69,0x6C,0x65,0x64,0x28,0x30,0x78,0x25, ++0x78,0x29,0x0A,0x00,0x54,0x4C,0x56,0x28, ++0x25,0x6C,0x78,0x29,0x53,0x65,0x74,0x28, ++0x25,0x78,0x29,0x0A,0x00,0x00,0x00,0x00, ++0x66,0x66,0xFF,0xFF,0x00,0x00,0x0F,0xE1, ++0xC0,0x10,0x80,0xE3,0x01,0xF0,0x21,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x0F,0xE1, ++0xC0,0x00,0xC0,0xE3,0x00,0xF0,0x21,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x00,0x10,0x0F,0xE1, ++0xC0,0x00,0x00,0xE2,0xC0,0x10,0xC1,0xE3, ++0x01,0x00,0x80,0xE1,0x00,0xF0,0x21,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x1F,0x20,0xC0,0xE3, ++0x01,0x00,0x80,0xE0,0x1F,0x00,0x80,0xE2, ++0x1F,0x00,0xC0,0xE3,0x00,0x00,0x52,0xE1, ++0x3E,0x2F,0x07,0x3E,0x20,0x20,0x82,0x32, ++0xFB,0xFF,0xFF,0x3A,0x00,0x00,0xA0,0xE3, ++0x9A,0x0F,0x07,0xEE,0x1E,0xFF,0x2F,0xE1, ++0x70,0x47,0x3F,0x28,0x05,0xDC,0x5A,0x4B, ++0x43,0xF8,0x20,0x10,0x59,0x49,0x41,0xF8, ++0x20,0x20,0x70,0x47,0x40,0x28,0x10,0xB5, ++0x15,0xD2,0xC1,0x17,0x56,0x4A,0x00,0xEB, ++0xD1,0x63,0x59,0x11,0x02,0xEB,0x81,0x02, ++0x14,0x68,0x23,0xF0,0x1F,0x03,0xC3,0x1A, ++0x01,0x20,0x98,0x40,0x04,0x43,0x14,0x60, ++0x4F,0x4A,0x08,0x3A,0x02,0xEB,0x81,0x01, ++0x0A,0x68,0x02,0x43,0x0A,0x60,0x10,0xBD, ++0x3F,0x28,0x0C,0xDC,0x48,0x4A,0x19,0xB1, ++0x52,0xF8,0x20,0x30,0x8B,0x42,0x06,0xD1, ++0x48,0x49,0x42,0xF8,0x20,0x10,0x00,0x21, ++0x44,0x4A,0x42,0xF8,0x20,0x10,0x70,0x47, ++0x10,0xB5,0x04,0x46,0xFF,0xF7,0x96,0xEF, ++0x40,0x2C,0x0F,0xD2,0xE1,0x17,0x04,0xEB, ++0xD1,0x62,0x3F,0x49,0x53,0x11,0x40,0x39, ++0x01,0xEB,0x83,0x01,0x0B,0x68,0x22,0xF0, ++0x1F,0x02,0xA4,0x1A,0x01,0x22,0xA2,0x40, ++0x13,0x43,0x0B,0x60,0xBD,0xE8,0x10,0x40, ++0x0B,0xF0,0x6C,0xBF,0x10,0xB5,0x04,0x46, ++0xFF,0xF7,0x7C,0xEF,0x40,0x2C,0x0F,0xD2, ++0xE1,0x17,0x04,0xEB,0xD1,0x62,0x32,0x49, ++0x53,0x11,0x40,0x39,0x01,0xEB,0x83,0x01, ++0x0B,0x68,0x22,0xF0,0x1F,0x02,0xA4,0x1A, ++0x01,0x22,0xA2,0x40,0x93,0x43,0x0B,0x60, ++0xBD,0xE8,0x10,0x40,0x0B,0xF0,0x52,0xBF, ++0x70,0xB5,0x04,0x46,0x15,0x46,0x1E,0x46, ++0xFF,0xF7,0xE0,0xFF,0x32,0x46,0x29,0x46, ++0x20,0x46,0xFF,0xF7,0x8E,0xFF,0x20,0x46, ++0xBD,0xE8,0x70,0x40,0xBC,0xE7,0x2D,0xE9, ++0xF0,0x41,0x04,0x46,0x0D,0x46,0x17,0x46, ++0xFF,0xF7,0x50,0xEF,0xE1,0x17,0x1E,0x4B, ++0x01,0x26,0x04,0xEB,0xD1,0x62,0x38,0x3B, ++0x22,0xF0,0x1F,0x01,0x61,0x1A,0x8E,0x40, ++0x51,0x11,0x01,0x2D,0x03,0xEB,0x81,0x01, ++0x0A,0x68,0x01,0xD1,0x32,0x43,0x00,0xE0, ++0xB2,0x43,0x0A,0x60,0xE2,0x17,0x14,0x49, ++0x04,0xEB,0xD2,0x62,0x30,0x39,0x52,0x11, ++0x01,0x2F,0x01,0xEB,0x82,0x01,0x0A,0x68, ++0x01,0xD1,0x32,0x43,0x00,0xE0,0xB2,0x43, ++0x0A,0x60,0xBD,0xE8,0xF0,0x41,0x0B,0xF0, ++0x15,0xBF,0x0D,0x48,0x00,0x78,0x00,0xF0, ++0x0F,0x00,0x06,0x28,0x07,0xD0,0x07,0x28, ++0x03,0xD0,0x08,0x28,0x05,0xD1,0x01,0x20, ++0x70,0x47,0x03,0x20,0x70,0x47,0x02,0x20, ++0x70,0x47,0x00,0x20,0x70,0x47,0x00,0x00, ++0x74,0xD2,0x02,0x20,0x74,0xD3,0x02,0x20, ++0x5C,0x0C,0x30,0x25,0xB9,0x2A,0x03,0x20, ++0x90,0x71,0x00,0x25,0x08,0x49,0xD1,0xF8, ++0x3C,0x0C,0x00,0xB2,0x82,0x05,0x04,0xD5, ++0xD1,0xF8,0x40,0x0C,0x00,0xB2,0x81,0x05, ++0x02,0xD4,0xC0,0xF3,0x85,0x00,0x70,0x47, ++0x4F,0xF0,0xFF,0x30,0x70,0x47,0x00,0x00, ++0x00,0x00,0x30,0x25,0x70,0x47,0x00,0x00, ++0x2D,0xE9,0xF0,0x47,0x00,0x25,0xDE,0x4C, ++0xA5,0x87,0xA5,0x87,0xA5,0x87,0x01,0x26, ++0xA6,0x87,0xA5,0x87,0xC8,0x20,0xFF,0xF7, ++0xB5,0xF9,0x4F,0xF6,0x7E,0x70,0xA4,0xF8, ++0x0C,0x01,0xA4,0xF8,0x9C,0x50,0xF7,0x03, ++0xA4,0xF8,0x48,0x70,0x24,0xF8,0x4C,0x5F, ++0x49,0xF6,0xE9,0x60,0xA0,0x87,0x7B,0x20, ++0xA4,0xF8,0x40,0x00,0x4F,0xF0,0x39,0x09, ++0xA4,0xF8,0x2C,0x90,0x4C,0xF2,0x1E,0x00, ++0x20,0x81,0x4F,0xF4,0xE0,0x40,0x20,0x82, ++0x30,0x02,0xA0,0x86,0x10,0x20,0x20,0x87, ++0x4F,0xF6,0x4F,0x70,0xA0,0x81,0x4F,0xF2, ++0xF0,0x00,0x20,0x83,0x4F,0xF4,0x7F,0x40, ++0xA0,0x82,0x4C,0x3C,0x44,0xF2,0x44,0x00, ++0xA4,0xF8,0x7C,0x00,0xA4,0xF8,0x80,0x50, ++0xAE,0x34,0x24,0xF8,0x2A,0x5C,0xC8,0x20, ++0xFF,0xF7,0x80,0xF9,0xBF,0x49,0x20,0x20, ++0xA1,0xF8,0x78,0x02,0x4F,0xF0,0x07,0x08, ++0xA4,0xF8,0x36,0x80,0x40,0xF6,0x78,0x00, ++0x60,0x87,0x48,0xF6,0x88,0x00,0xE0,0x87, ++0xAE,0x3C,0x47,0xF2,0x77,0x71,0xA4,0xF8, ++0xF0,0x10,0xA4,0xF8,0xF4,0x00,0x4F,0xF4, ++0x58,0x50,0xA4,0xF8,0xE4,0x01,0xA6,0x87, ++0xA5,0x87,0xA6,0x87,0xA5,0x87,0x40,0xF6, ++0x95,0x10,0xA0,0x80,0x41,0xF6,0xF9,0x70, ++0x20,0x81,0x45,0xF2,0x50,0x10,0xA0,0x81, ++0x40,0xF6,0x33,0x00,0x20,0x82,0xAC,0xA0, ++0xFF,0xF7,0x40,0xFA,0x40,0xF6,0x22,0x30, ++0xA0,0x82,0x45,0xF2,0x31,0x20,0x20,0x83, ++0x41,0xF2,0x16,0x20,0xA0,0x83,0x32,0x20, ++0x20,0x84,0xA7,0x84,0x48,0xF2,0x04,0x30, ++0xA4,0xF8,0x88,0x01,0x35,0x20,0xA4,0xF8, ++0x8C,0x01,0x4F,0xF6,0xFF,0x70,0xA4,0xF8, ++0x90,0x01,0xA4,0xF8,0x94,0x01,0xA4,0xF8, ++0x98,0x01,0xA4,0xF8,0x9C,0x01,0x24,0xF8, ++0x64,0x5F,0x40,0x20,0x20,0x81,0xA4,0xF8, ++0x14,0x90,0x1F,0x20,0xA4,0xF8,0xEC,0x00, ++0x40,0xF6,0xAA,0x20,0xA0,0x80,0x64,0x3C, ++0x03,0x20,0xA4,0xF8,0xB4,0x00,0xA4,0xF8, ++0xB4,0x60,0x40,0xF2,0x22,0x50,0xA4,0xF8, ++0x9C,0x00,0xE4,0x20,0xA4,0xF8,0xA0,0x00, ++0xA4,0xF8,0x90,0x50,0x25,0x80,0x06,0x20, ++0x20,0x80,0xC8,0x20,0xFF,0xF7,0x16,0xF9, ++0xA4,0xF8,0x00,0x80,0x4F,0xF4,0xFA,0x60, ++0xFF,0xF7,0x10,0xF9,0xC8,0x20,0xFF,0xF7, ++0x0D,0xF9,0x4F,0xF4,0x90,0x50,0xA4,0xF8, ++0xE4,0x01,0x78,0x1C,0xA4,0xF8,0x00,0x01, ++0xA6,0x86,0xA4,0xF8,0x0C,0x51,0xBD,0xE8, ++0xF0,0x87,0x2D,0xE9,0xF0,0x41,0x00,0x25, ++0x7D,0x4C,0xA5,0x87,0xA5,0x87,0xA5,0x87, ++0x01,0x26,0xA6,0x87,0x46,0x34,0x24,0xF8, ++0x0A,0x5C,0xB0,0x03,0x60,0x80,0x4F,0xF4, ++0x40,0x70,0xE0,0x80,0x4F,0xF4,0xE0,0x40, ++0xE0,0x82,0x4C,0xF6,0xC8,0x00,0xA4,0xF8, ++0x42,0x00,0x3C,0x20,0xA4,0xF8,0x46,0x00, ++0x37,0x02,0x67,0x87,0x4F,0xF0,0x10,0x08, ++0xA4,0xF8,0x3E,0x80,0x4F,0xF6,0xF0,0x70, ++0x60,0x83,0x46,0x3C,0x4F,0xF4,0x7F,0x40, ++0xA4,0xF8,0x64,0x00,0xA4,0xF8,0x80,0x50, ++0xA4,0xF8,0x84,0x50,0x0A,0x20,0xFF,0xF7, ++0xBB,0xF8,0x68,0x49,0x40,0x20,0xA1,0xF8, ++0x78,0x02,0x94,0x20,0xA0,0x80,0x4C,0xF6, ++0xF6,0x20,0x20,0x81,0x41,0xF2,0x28,0x10, ++0xA0,0x81,0x40,0xF6,0x33,0x00,0x20,0x82, ++0x40,0xF6,0x03,0x40,0xA0,0x82,0x46,0xF2, ++0x50,0x40,0x20,0x83,0x41,0xF2,0x0E,0x00, ++0xA0,0x83,0x31,0x20,0x20,0x84,0x4F,0xF4, ++0x10,0x50,0xA0,0x84,0xF0,0x03,0x20,0x85, ++0x4F,0xF4,0x40,0x40,0xA0,0x85,0x4F,0xF4, ++0x84,0x50,0xA4,0xF8,0x40,0x01,0xA4,0xF8, ++0x4C,0x51,0xA6,0x87,0xA5,0x87,0xA6,0x87, ++0xA5,0x87,0x42,0xF2,0xAA,0x20,0xA4,0xF8, ++0x90,0x00,0x40,0xF2,0xAA,0x20,0xA4,0xF8, ++0x94,0x00,0xA4,0xF8,0x9C,0x70,0xA4,0xF8, ++0xD0,0x60,0x25,0x80,0x06,0x20,0x20,0x80, ++0x07,0x20,0x20,0x80,0x0A,0x20,0xFF,0xF7, ++0x7B,0xF8,0x48,0xF2,0x01,0x00,0xA4,0xF8, ++0x00,0x01,0xA6,0x86,0xA4,0xF8,0x0C,0x51, ++0x4F,0xF4,0x58,0x50,0xA4,0xF8,0xE4,0x01, ++0xA4,0xF8,0xC4,0x51,0xA4,0xF8,0xC8,0x81, ++0xA4,0xF8,0xCC,0x51,0x45,0xF6,0xA5,0x20, ++0xA4,0xF8,0xD0,0x01,0xA4,0xF8,0xC0,0x51, ++0xBD,0xE8,0xF0,0x81,0x70,0x47,0x3D,0x49, ++0x07,0x28,0x09,0xD8,0x0A,0x88,0x22,0xF4, ++0x60,0x42,0x42,0xEA,0x40,0x30,0x08,0x80, ++0x4C,0xF2,0x50,0x30,0xFF,0xF7,0x6A,0xB8, ++0x70,0x47,0x36,0x48,0x00,0x88,0x20,0xF4, ++0x60,0x40,0x40,0x0B,0x70,0x47,0x34,0x48, ++0xA5,0x22,0x10,0xB5,0x86,0x21,0x00,0xF0, ++0x6E,0xF9,0x31,0x4C,0x31,0xA0,0x21,0x46, ++0xFF,0xF7,0x44,0xF9,0xA5,0x22,0x11,0x21, ++0x20,0x46,0x00,0xF0,0xCB,0xF8,0x04,0x00, ++0x11,0xD0,0xA5,0x22,0x11,0x21,0x20,0x46, ++0x00,0xF0,0x86,0xF8,0x58,0xB1,0x61,0x7C, ++0x30,0xA0,0xFF,0xF7,0x33,0xF9,0x20,0x46, ++0x00,0xF0,0xDD,0xF8,0x61,0x7C,0x31,0xA0, ++0xFF,0xF7,0x2C,0xF9,0x05,0xE0,0x34,0xA0, ++0xFF,0xF7,0x28,0xF9,0x01,0x20,0xFF,0xF7, ++0x77,0xFE,0xBD,0xE8,0x10,0x40,0x02,0xF0, ++0x2C,0xBD,0x19,0x48,0x94,0x21,0x81,0x80, ++0x48,0xF2,0xF5,0x21,0x01,0x81,0x41,0xF2, ++0x28,0x11,0x81,0x81,0x40,0xF6,0x33,0x01, ++0x01,0x82,0x40,0xF6,0x03,0x41,0x81,0x82, ++0x46,0xF2,0x50,0x41,0x01,0x83,0x41,0xF2, ++0x0E,0x21,0x81,0x83,0x31,0x21,0x01,0x84, ++0x4F,0xF4,0x10,0x51,0x81,0x84,0x4F,0xF4, ++0x00,0x41,0x01,0x85,0x4F,0xF4,0x40,0x41, ++0x81,0x85,0x00,0x21,0x01,0x80,0x06,0x22, ++0x02,0x80,0x07,0x22,0x02,0x80,0x23,0x4A, ++0x11,0x84,0x48,0xF2,0x01,0x02,0xA0,0xF8, ++0x00,0x21,0x01,0x22,0x82,0x86,0xA0,0xF8, ++0x0C,0x11,0x70,0x47,0x9F,0xE7,0x00,0x00, ++0x00,0x24,0x00,0x25,0x00,0x70,0x00,0x25, ++0x61,0x63,0x0A,0x00,0x44,0x0B,0x02,0x25, ++0x00,0x10,0x02,0x20,0x43,0x68,0x65,0x63, ++0x6B,0x20,0x4D,0x49,0x55,0x20,0x66,0x72, ++0x6F,0x6D,0x20,0x4E,0x41,0x4E,0x44,0x2F, ++0x55,0x53,0x42,0x28,0x30,0x78,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x75,0x73,0x65,0x5F, ++0x68,0x77,0x63,0x66,0x67,0x28,0x25,0x78, ++0x29,0x0A,0x00,0x00,0x65,0x6E,0x64,0x20, ++0x75,0x73,0x65,0x5F,0x68,0x77,0x63,0x66, ++0x67,0x28,0x25,0x78,0x29,0x0A,0x00,0x00, ++0x44,0x65,0x66,0x61,0x75,0x6C,0x74,0x5F, ++0x4D,0x49,0x55,0x5F,0x44,0x44,0x52,0x33, ++0x32,0x5F,0x69,0x6E,0x69,0x74,0x5B,0x69, ++0x6E,0x5D,0x0A,0x00,0x00,0x70,0x02,0x25, ++0x2D,0xE9,0xF0,0x41,0x04,0x46,0x88,0x46, ++0xC1,0x8A,0x20,0x30,0x16,0x46,0x00,0xF0, ++0x01,0xFA,0xDF,0xF8,0x2C,0xC3,0x05,0x46, ++0x20,0x68,0x60,0x45,0x13,0xD1,0xE2,0x7C, ++0x42,0x45,0x10,0xD1,0x63,0x7C,0xB3,0x42, ++0x01,0xD0,0xA5,0x2E,0x0B,0xD1,0x21,0x7C, ++0x04,0x29,0x08,0xD1,0xE7,0x69,0xAF,0x42, ++0x05,0xD1,0xC2,0xA0,0xFF,0xF7,0x92,0xF8, ++0x01,0x20,0xBD,0xE8,0xF0,0x81,0x01,0x46, ++0x62,0x46,0xC8,0xA0,0xFF,0xF7,0x8A,0xF8, ++0xE1,0x7C,0x42,0x46,0xCA,0xA0,0xFF,0xF7, ++0x85,0xF8,0x61,0x7C,0x32,0x46,0xCD,0xA0, ++0xFF,0xF7,0x80,0xF8,0xE1,0x69,0x2A,0x46, ++0xCF,0xA0,0xFF,0xF7,0x7B,0xF8,0x21,0x7C, ++0x04,0x22,0xD3,0xA0,0xFF,0xF7,0x76,0xF8, ++0x00,0x20,0xE2,0xE7,0x70,0xB5,0x04,0x46, ++0xAF,0x48,0x13,0x46,0x13,0xE0,0x25,0x7C, ++0x04,0x2D,0x0D,0xD1,0x8A,0x42,0x0B,0xD1, ++0x65,0x7C,0x9D,0x42,0x01,0xD0,0xA5,0x2B, ++0x06,0xD1,0x21,0x7C,0x23,0x46,0xCD,0xA0, ++0xFF,0xF7,0x60,0xF8,0x20,0x46,0x70,0xBD, ++0xE2,0x8A,0x20,0x34,0x14,0x44,0x22,0x68, ++0x82,0x42,0x02,0xD1,0xE2,0x7C,0xFF,0x2A, ++0xE5,0xD3,0x00,0x20,0x70,0xBD,0x2D,0xE9, ++0xF0,0x41,0x80,0x46,0x80,0x7C,0x00,0x26, ++0x00,0x28,0x6E,0xD0,0x01,0x28,0x6C,0xD1, ++0x00,0x25,0x65,0xE0,0x08,0xEB,0xC5,0x04, ++0x20,0x6A,0x41,0x1C,0x23,0xD1,0x60,0x6A, ++0x41,0x1C,0x03,0xD1,0xA0,0x6A,0xFE,0xF7, ++0x51,0xFF,0x19,0xE0,0x81,0x1C,0x09,0xD1, ++0xA7,0x6A,0x02,0xE0,0x01,0x20,0xFE,0xF7, ++0x49,0xFF,0x38,0x68,0xE1,0x6A,0x88,0x42, ++0xF8,0xD1,0x0D,0xE0,0xC0,0x1C,0x09,0xD1, ++0xA7,0x6A,0x02,0xE0,0x01,0x20,0xFE,0xF7, ++0x3D,0xFF,0x38,0x68,0xE1,0x6A,0x88,0x42, ++0xF8,0xD0,0x01,0xE0,0x6D,0x1E,0x76,0x1E, ++0x6D,0x1C,0x76,0x1C,0x3B,0xE0,0x4F,0xF6, ++0xFF,0x71,0xB1,0xEB,0x10,0x4F,0x05,0xD1, ++0x61,0x6A,0x80,0xB2,0x89,0xB2,0x02,0xF0, ++0xF2,0xFD,0x30,0xE0,0x4F,0xF6,0xFE,0x71, ++0xB1,0xEB,0x10,0x4F,0x2B,0xD0,0x49,0x1E, ++0xB1,0xEB,0x10,0x4F,0x06,0xD1,0x60,0x6A, ++0x02,0x68,0xA1,0x6A,0xE3,0x6A,0x8A,0x43, ++0x19,0x40,0x1A,0xE0,0x4F,0xF6,0xFC,0x71, ++0xB1,0xEB,0x10,0x4F,0x19,0xD1,0xC0,0x07, ++0x05,0xD0,0x01,0xF0,0xE7,0xFF,0x61,0x6A, ++0x88,0x42,0x10,0xD1,0x04,0xE0,0x01,0xF0, ++0xE1,0xFF,0x61,0x6A,0x88,0x42,0x0A,0xD3, ++0x20,0x6A,0xC0,0x06,0x00,0x28,0xA0,0x6A, ++0x01,0x68,0xE2,0x6A,0x01,0xDA,0x91,0x43, ++0x00,0xE0,0x11,0x43,0x01,0x60,0x6D,0x1C, ++0x01,0xE0,0x61,0x6A,0x01,0x60,0x6D,0x1C, ++0xB8,0xF8,0x14,0x00,0x30,0x44,0xA8,0x42, ++0x94,0xD8,0x01,0x20,0x49,0xE7,0x70,0xB5, ++0x04,0x46,0x0D,0x46,0x16,0x46,0x8E,0xA0, ++0xFE,0xF7,0xD4,0xFF,0x32,0x46,0x29,0x46, ++0x20,0x46,0xFF,0xF7,0x5B,0xFF,0x04,0x00, ++0x0D,0xD0,0x32,0x46,0x29,0x46,0x20,0x46, ++0xFF,0xF7,0x16,0xFF,0x38,0xB1,0x20,0x46, ++0xFF,0xF7,0x71,0xFF,0x89,0xA0,0xFE,0xF7, ++0xC1,0xFF,0x01,0x20,0x70,0xBD,0x89,0xA0, ++0xFE,0xF7,0xBC,0xFF,0x00,0x20,0x70,0xBD, ++0x2D,0xE9,0xF0,0x41,0x07,0x46,0x88,0x46, ++0x14,0x46,0x06,0x9E,0x1D,0x46,0x08,0x46, ++0x02,0xF0,0x80,0xFD,0x04,0xFA,0x05,0xF1, ++0x39,0x40,0x80,0xB2,0xE9,0x40,0xB4,0x40, ++0xB1,0x40,0x20,0xEA,0x04,0x02,0x0A,0x43, ++0x91,0xB2,0x88,0x42,0x04,0xD0,0x40,0x46, ++0xBD,0xE8,0xF0,0x41,0x02,0xF0,0x7B,0xBD, ++0x0B,0xE7,0x08,0xB5,0x07,0x23,0x01,0x22, ++0x42,0xF2,0x48,0x01,0x00,0x93,0x00,0x23, ++0x10,0x46,0xFF,0xF7,0xD9,0xFF,0x08,0xBD, ++0x2D,0xE9,0xF8,0x43,0x42,0xF2,0x36,0x00, ++0x02,0xF0,0x5C,0xFD,0x86,0xB2,0x42,0xF2, ++0x38,0x00,0x02,0xF0,0x57,0xFD,0x85,0xB2, ++0x42,0xF2,0x3A,0x00,0x02,0xF0,0x52,0xFD, ++0x00,0x23,0x40,0xF6,0xFF,0x72,0x84,0xB2, ++0x00,0x93,0x42,0xF2,0x30,0x01,0x30,0x46, ++0xFF,0xF7,0xBE,0xFF,0x00,0x23,0x42,0xF2, ++0x08,0x08,0x00,0x93,0x0C,0x23,0x0F,0x22, ++0x41,0x46,0x30,0x46,0xFF,0xF7,0xB4,0xFF, ++0x00,0x23,0x01,0x22,0x00,0x93,0x42,0xF2, ++0x0E,0x01,0x28,0x46,0xFF,0xF7,0xAC,0xFF, ++0x04,0x23,0x42,0xF2,0x04,0x06,0x00,0x93, ++0x01,0x23,0x03,0x22,0x31,0x46,0x28,0x46, ++0xFF,0xF7,0xA2,0xFF,0x03,0x23,0x42,0xF2, ++0x32,0x07,0x00,0x93,0x1A,0x46,0x39,0x46, ++0x28,0x46,0xFF,0xF7,0x99,0xFF,0x0A,0x23, ++0x03,0x22,0x00,0x93,0x05,0x23,0xB1,0x1D, ++0x28,0x46,0xFF,0xF7,0x91,0xFF,0x07,0x23, ++0x0F,0x22,0x00,0x93,0x39,0x46,0x28,0x46, ++0xFF,0xF7,0x8A,0xFF,0x04,0x23,0xB7,0x1C, ++0x00,0x93,0x0B,0x23,0x03,0x22,0x39,0x46, ++0x28,0x46,0xFF,0xF7,0x81,0xFF,0x0A,0x23, ++0x03,0x22,0x00,0x93,0x0D,0x23,0x39,0x46, ++0x28,0x46,0xFF,0xF7,0x79,0xFF,0x04,0xF0, ++0x01,0x01,0x05,0xF4,0x00,0x40,0x08,0x23, ++0x03,0x22,0x00,0xEB,0x41,0x00,0x00,0x93, ++0x00,0x23,0x31,0x46,0x80,0xB2,0xFF,0xF7, ++0x6B,0xFF,0x01,0x23,0x43,0xF6,0xFF,0x72, ++0x00,0x93,0x42,0xF2,0x34,0x01,0x20,0x46, ++0xFF,0xF7,0x62,0xFF,0x06,0x23,0x01,0x22, ++0x00,0x93,0x0F,0x23,0x41,0x46,0x20,0x46, ++0xFF,0xF7,0x5A,0xFF,0xBD,0xE8,0xF8,0x83, ++0x71,0x52,0x56,0x93,0x5B,0x48,0x57,0x5F, ++0x43,0x46,0x47,0x5D,0x63,0x68,0x69,0x70, ++0x28,0x30,0x78,0x25,0x78,0x29,0x64,0x61, ++0x74,0x61,0x28,0x25,0x6C,0x78,0x29,0x6D, ++0x69,0x75,0x28,0x25,0x6C,0x78,0x29,0x0A, ++0x00,0x00,0x00,0x00,0x6D,0x61,0x67,0x69, ++0x63,0x28,0x25,0x6C,0x78,0x29,0x6E,0x6F, ++0x77,0x28,0x25,0x6C,0x78,0x29,0x00,0x00, ++0x64,0x61,0x74,0x61,0x28,0x25,0x6C,0x78, ++0x29,0x6E,0x6F,0x77,0x28,0x25,0x6C,0x78, ++0x29,0x00,0x00,0x00,0x6D,0x69,0x75,0x28, ++0x25,0x6C,0x78,0x29,0x6E,0x6F,0x77,0x28, ++0x25,0x6C,0x78,0x29,0x00,0x00,0x00,0x00, ++0x63,0x68,0x6B,0x73,0x75,0x6D,0x28,0x25, ++0x6C,0x78,0x29,0x6E,0x6F,0x77,0x28,0x25, ++0x6C,0x78,0x29,0x0A,0x00,0x00,0x00,0x00, ++0x63,0x68,0x69,0x70,0x28,0x25,0x6C,0x78, ++0x29,0x6E,0x6F,0x77,0x28,0x25,0x6C,0x78, ++0x29,0x0A,0x00,0x00,0x63,0x68,0x69,0x70, ++0x28,0x25,0x78,0x29,0x64,0x61,0x74,0x61, ++0x28,0x25,0x78,0x29,0x61,0x64,0x64,0x72, ++0x28,0x25,0x6C,0x78,0x29,0x0A,0x00,0x00, ++0x53,0x65,0x74,0x5F,0x68,0x77,0x5F,0x63, ++0x6F,0x6E,0x66,0x69,0x67,0x28,0x25,0x78, ++0x29,0x00,0x00,0x00,0x64,0x6F,0x6E,0x65, ++0x0A,0x00,0x00,0x00,0x66,0x61,0x69,0x6C, ++0x0A,0x00,0x00,0x00,0x2D,0xE9,0xF0,0x41, ++0x04,0x00,0x0F,0x46,0x02,0xD1,0x01,0x20, ++0xBD,0xE8,0xF0,0x81,0x01,0x25,0x00,0x26, ++0x4D,0xE0,0x41,0xF2,0xB0,0x50,0x87,0x42, ++0x00,0xD2,0x38,0x46,0x3F,0x1A,0x31,0xE0, ++0x21,0x78,0x63,0x78,0x29,0x44,0x72,0x18, ++0x19,0x44,0xA3,0x78,0x0A,0x44,0x19,0x44, ++0xE3,0x78,0x0A,0x44,0x19,0x44,0x23,0x79, ++0x0A,0x44,0x19,0x44,0x63,0x79,0x0A,0x44, ++0x19,0x44,0xA3,0x79,0x0A,0x44,0x19,0x44, ++0xE3,0x79,0x0A,0x44,0x19,0x44,0x23,0x7A, ++0x0A,0x44,0x19,0x44,0x63,0x7A,0x0A,0x44, ++0x19,0x44,0xA3,0x7A,0x0A,0x44,0x19,0x44, ++0xE3,0x7A,0x0A,0x44,0x19,0x44,0x23,0x7B, ++0x0A,0x44,0x19,0x44,0x63,0x7B,0x0A,0x44, ++0x19,0x44,0xA3,0x7B,0x0A,0x44,0x19,0x44, ++0xE3,0x7B,0x0A,0x44,0x10,0x34,0x5D,0x18, ++0x56,0x19,0x10,0x38,0x10,0x28,0xCB,0xD2, ++0x28,0xB1,0x14,0xF8,0x01,0x1B,0x40,0x1E, ++0x0D,0x44,0x2E,0x44,0xF8,0xE7,0x4F,0xF6, ++0xF1,0x78,0x28,0x46,0x41,0x46,0x0A,0xF0, ++0xCC,0xED,0x0D,0x46,0x41,0x46,0x30,0x46, ++0x0A,0xF0,0xC6,0xED,0x0E,0x46,0x00,0x2F, ++0xAF,0xD1,0x45,0xEA,0x06,0x40,0xA7,0xE7, ++0xD8,0x48,0x10,0xB5,0x00,0x68,0x03,0xF0, ++0x3D,0xFC,0xBD,0xE8,0x10,0x40,0x37,0x20, ++0xFF,0xF7,0xC4,0xBA,0xD4,0x48,0xB0,0xF8, ++0xB4,0x11,0x41,0xF4,0x80,0x61,0xA0,0xF8, ++0xB4,0x11,0x01,0x88,0x41,0xF4,0x80,0x61, ++0x20,0xF8,0x40,0x1B,0x01,0x88,0x41,0xF4, ++0x80,0x61,0x01,0x80,0x70,0x47,0xCC,0x48, ++0xB0,0xF8,0xB4,0x11,0x21,0xF4,0x80,0x61, ++0xA0,0xF8,0xB4,0x11,0x01,0x88,0x21,0xF4, ++0x80,0x61,0x20,0xF8,0x40,0x1B,0x01,0x88, ++0x21,0xF4,0x80,0x61,0x01,0x80,0x70,0x47, ++0x10,0xB5,0x04,0x46,0x02,0xF0,0xEE,0xFC, ++0x00,0x28,0x04,0xD0,0x20,0x46,0xBD,0xE8, ++0x10,0x40,0x02,0xF0,0xB5,0xBE,0x10,0xBD, ++0x10,0xB5,0xAF,0xF2,0x1B,0x00,0xBD,0x49, ++0xBF,0x4A,0x08,0x60,0xBD,0x49,0xBC,0x48, ++0x05,0xC1,0xBF,0x49,0xBD,0x4A,0xC1,0xE9, ++0x00,0x20,0xBE,0xA0,0xFE,0xF7,0x02,0xFE, ++0x01,0x22,0x37,0x20,0x11,0x46,0xFF,0xF7, ++0xEE,0xFA,0x00,0x23,0xAF,0xF2,0x9F,0x02, ++0xBD,0xE8,0x10,0x40,0x37,0x20,0x19,0x46, ++0xFF,0xF7,0xD6,0xBA,0x2D,0xE9,0xF0,0x47, ++0x4F,0xF4,0x80,0x40,0xAB,0x49,0xDF,0xF8, ++0xE0,0x82,0xC1,0xF8,0x00,0x80,0xB7,0x49, ++0x08,0x60,0xAF,0xF2,0x6B,0x00,0xA9,0x49, ++0xAB,0x4A,0x08,0x60,0xA9,0x49,0xA8,0x48, ++0x05,0xC1,0xAB,0x49,0xA9,0x4A,0xC1,0xE9, ++0x00,0x20,0xB1,0x48,0x03,0xF0,0x7C,0xFC, ++0xAF,0x49,0x40,0x46,0x03,0xF0,0x5C,0xFC, ++0x40,0x46,0x03,0xF0,0x6D,0xFC,0x01,0x22, ++0x37,0x20,0x11,0x46,0xFF,0xF7,0xBF,0xFA, ++0x00,0x23,0xAF,0xF2,0xFB,0x02,0x37,0x20, ++0x19,0x46,0xFF,0xF7,0xA9,0xFA,0xA7,0x4E, ++0xB0,0x8A,0x40,0xF4,0x00,0x40,0xB0,0x82, ++0xA5,0x48,0xB0,0xF8,0xCC,0x1B,0x21,0xF4, ++0x80,0x51,0xA0,0xF8,0xCC,0x1B,0x01,0x88, ++0x21,0xF4,0x80,0x51,0x01,0x80,0x41,0xF2, ++0x03,0x40,0x30,0x82,0x42,0xF2,0x84,0x00, ++0xB0,0x80,0x48,0xF2,0x03,0x00,0xA6,0xF8, ++0x40,0x00,0x4F,0xF4,0xC0,0x40,0xA6,0xF8, ++0x44,0x00,0x46,0xF6,0xC3,0x30,0x30,0x80, ++0x4F,0xF4,0x7A,0x7A,0x54,0x46,0x50,0x46, ++0xFE,0xF7,0xB4,0xFC,0x46,0xF6,0xC3,0x10, ++0x30,0x80,0x4F,0xF4,0xFA,0x60,0xFE,0xF7, ++0xAD,0xFC,0x4F,0xF0,0x01,0x09,0xA6,0xF8, ++0x00,0x90,0xA6,0xF5,0x60,0x66,0x20,0x46, ++0xFE,0xF7,0xA4,0xFC,0x00,0x24,0x42,0xF2, ++0x10,0x75,0xB6,0xF8,0x60,0x7E,0x20,0x46, ++0x64,0x1C,0xA8,0x42,0x04,0xD8,0x01,0x20, ++0xFE,0xF7,0x98,0xFC,0xF8,0x07,0xF4,0xD0, ++0x68,0x20,0xA6,0xF8,0x00,0x0C,0x02,0x20, ++0xA6,0xF8,0x04,0x0C,0x40,0xF2,0xFF,0x10, ++0xA6,0xF8,0x24,0x0E,0xFF,0x20,0xA6,0xF8, ++0x24,0x0E,0x50,0x46,0xFE,0xF7,0x86,0xFC, ++0x4C,0x46,0xA6,0xF8,0x78,0x9E,0x00,0x27, ++0xA6,0xF8,0x78,0x7E,0x38,0x46,0x03,0xE0, ++0x01,0x46,0x40,0x1C,0xA9,0x42,0x03,0xD8, ++0xB6,0xF8,0x78,0x1E,0x89,0x07,0xF7,0xD5, ++0x06,0xF6,0x04,0x66,0x42,0xF6,0x84,0x00, ++0x30,0x80,0x4B,0xF2,0x40,0x00,0x30,0x81, ++0x49,0xF2,0x03,0x51,0xB1,0x81,0xC1,0x1C, ++0x31,0x81,0x30,0x81,0xFF,0xF7,0x12,0xFF, ++0x6E,0x4D,0xA8,0x79,0x00,0xF0,0xFE,0x00, ++0xA8,0x71,0xA8,0x79,0x40,0xF0,0x01,0x00, ++0xA8,0x71,0xFF,0xF7,0x18,0xFF,0xE8,0x88, ++0x40,0xF4,0x00,0x40,0xE8,0x80,0x03,0xF0, ++0xE7,0xF8,0x6F,0x81,0xEF,0x81,0x88,0xF8, ++0x2F,0x40,0x65,0x48,0x60,0x49,0x00,0x68, ++0xC8,0xF8,0x38,0x01,0x00,0xF5,0x00,0x50, ++0x08,0x62,0x05,0xF8,0xFA,0x7C,0xE8,0x7F, ++0x40,0xF0,0x08,0x00,0xE8,0x77,0x60,0x20, ++0x05,0xF8,0xF9,0x0C,0x05,0xF8,0x3A,0x7C, ++0x5C,0x48,0x04,0x70,0xBD,0xE8,0xF0,0x87, ++0x5B,0x48,0x01,0x68,0x21,0xF4,0x00,0x01, ++0x01,0x60,0x70,0x47,0x58,0x48,0x01,0x68, ++0x41,0xF4,0x00,0x01,0x01,0x60,0x70,0x47, ++0x2D,0xE9,0xF0,0x41,0x06,0x46,0x3F,0x48, ++0x00,0x27,0x0D,0x46,0x00,0x68,0xD0,0xF8, ++0x3C,0x41,0xE1,0x68,0x67,0x60,0x27,0x61, ++0x31,0xB1,0xA2,0x68,0x1A,0xB1,0x20,0x6A, ++0x01,0x44,0x09,0xF0,0xDE,0xEB,0xE7,0x60, ++0x44,0x49,0xA0,0x68,0x09,0x68,0x42,0x19, ++0x8A,0x42,0x00,0xD9,0x0D,0x1A,0x21,0x6A, ++0x2A,0x46,0x08,0x44,0x31,0x46,0x09,0xF0, ++0xD0,0xEB,0xA0,0x68,0x28,0x44,0xA0,0x60, ++0x28,0x46,0xBD,0xE8,0xF0,0x81,0x2D,0x4A, ++0x70,0xB5,0x00,0x26,0x12,0x68,0xD2,0xF8, ++0x3C,0x41,0x23,0x69,0x62,0x68,0xD2,0x1A, ++0x8A,0x42,0x01,0xD9,0x0D,0x46,0x01,0xE0, ++0x15,0x46,0x66,0x60,0x5D,0xB1,0x21,0x6A, ++0x2A,0x46,0x19,0x44,0x09,0xF0,0xB4,0xEB, ++0x60,0x68,0x08,0xB9,0x26,0x61,0x02,0xE0, ++0x20,0x69,0x28,0x44,0x20,0x61,0x28,0x46, ++0x70,0xBD,0x70,0x47,0x31,0x49,0x2A,0x48, ++0x09,0x78,0xD0,0xF8,0x3C,0x01,0x00,0x29, ++0x04,0xD0,0x00,0x21,0x41,0x60,0x01,0x61, ++0x01,0x77,0x81,0x60,0x70,0x47,0x70,0x47, ++0x16,0x49,0x00,0x20,0x09,0x68,0xD1,0xF8, ++0x3C,0x11,0x08,0x77,0x70,0x47,0x13,0x48, ++0x00,0x68,0xD0,0xF8,0x3C,0x01,0x00,0x7F, ++0x70,0x47,0x10,0x48,0x00,0x68,0xD0,0xF8, ++0x3C,0x01,0x80,0x68,0x08,0xB1,0x00,0x20, ++0x70,0x47,0x01,0x20,0x70,0x47,0x0B,0x49, ++0x09,0x68,0xD1,0xF8,0x3C,0x11,0x08,0x62, ++0x70,0x47,0x08,0x49,0x09,0x68,0xC1,0xF8, ++0x38,0x01,0x70,0x47,0x07,0x48,0x10,0xB5, ++0x01,0x68,0x11,0xB1,0x03,0x48,0x00,0x68, ++0x88,0x47,0x18,0x49,0xFF,0x20,0x08,0x80, ++0x08,0x81,0x10,0xBD,0x74,0xD4,0x02,0x20, ++0x18,0x7C,0x00,0x25,0x80,0xD4,0x02,0x20, ++0xD5,0x67,0x03,0x20,0x8C,0xD4,0x02,0x20, ++0x09,0x68,0x03,0x20,0x53,0x67,0x03,0x20, ++0x84,0xD4,0x02,0x20,0x4D,0x44,0x72,0x76, ++0x5F,0x55,0x53,0x42,0x5F,0x49,0x6E,0x69, ++0x74,0x5F,0x62,0x6F,0x6F,0x74,0x0A,0x00, ++0x00,0xD1,0x02,0x20,0xB4,0x04,0x03,0x20, ++0x48,0xD2,0x02,0x20,0x00,0x3E,0x00,0x25, ++0x94,0x72,0x00,0x25,0xFA,0x40,0x00,0x25, ++0xAC,0x04,0x03,0x20,0xC0,0x04,0x03,0x20, ++0x20,0x0C,0x30,0x25,0x14,0x3C,0x30,0x25, ++0x10,0xB5,0x03,0xF0,0x15,0xFB,0x04,0x46, ++0x20,0x20,0x05,0xF0,0xC4,0xFD,0xB4,0x21, ++0x20,0x46,0x09,0xF0,0xC2,0xEB,0x03,0xF0, ++0x9F,0xFB,0x03,0xF0,0x9A,0xFB,0xC4,0xF8, ++0x98,0x00,0x4F,0xF4,0x00,0x71,0x09,0xF0, ++0x96,0xEB,0x05,0xF0,0x31,0xFB,0x08,0xB1, ++0xFF,0x48,0x10,0xBD,0x05,0xF0,0xF9,0xF8, ++0x10,0xB1,0xFD,0x48,0x40,0x1E,0x10,0xBD, ++0xBD,0xE8,0x10,0x40,0x05,0xF0,0xC9,0xBB, ++0xDA,0xE7,0x70,0xB5,0x05,0x46,0x0C,0x46, ++0x03,0xF0,0xEE,0xFA,0x41,0x7C,0x0F,0x22, ++0x29,0x70,0x81,0x1C,0x20,0x46,0x09,0xF0, ++0x10,0xEB,0x00,0x20,0x70,0xBD,0x2D,0xE9, ++0xF0,0x41,0x04,0x46,0x00,0xF5,0x00,0x75, ++0x05,0xF0,0xA5,0xFB,0xEE,0x4E,0x35,0x3E, ++0x10,0xB1,0x30,0x46,0xBD,0xE8,0xF0,0x81, ++0x0E,0x21,0x04,0xF1,0x24,0x00,0x05,0xF0, ++0x50,0xFB,0x07,0x46,0x04,0xF1,0x20,0x00, ++0x09,0xF0,0x3A,0xEC,0x01,0x46,0x38,0x46, ++0x81,0x42,0x4F,0xF4,0x00,0x77,0x04,0xD0, ++0x39,0x46,0x20,0x46,0x05,0xF0,0x7F,0xFD, ++0xE7,0xE7,0x28,0x1D,0x4F,0xF4,0xFE,0x71, ++0x05,0xF0,0x3B,0xFB,0x06,0x46,0x28,0x46, ++0x09,0xF0,0x26,0xEC,0xB0,0x42,0x06,0xD0, ++0x39,0x46,0x28,0x46,0x05,0xF0,0x6F,0xFD, ++0xD9,0x48,0x34,0x38,0xD6,0xE7,0x20,0x46, ++0x05,0xF0,0x6A,0xFB,0x28,0x46,0x05,0xF0, ++0x22,0xFB,0x00,0x20,0xCE,0xE7,0x2D,0xE9, ++0xF0,0x4F,0x05,0x46,0x85,0xB0,0x03,0xF0, ++0xA3,0xFA,0x04,0x46,0xD0,0xF8,0x88,0x00, ++0x4F,0xF4,0x00,0x78,0x03,0x90,0x05,0xF5, ++0x00,0x70,0xD4,0xF8,0x84,0xA0,0x41,0x46, ++0x02,0x90,0xCC,0x48,0x01,0x90,0x09,0xF0, ++0x26,0xEB,0x01,0x9E,0x0F,0x21,0xA0,0x1C, ++0x09,0xF0,0x20,0xEB,0x2A,0x7C,0xA0,0x1C, ++0x05,0xF1,0x11,0x01,0x09,0xF0,0xB0,0xEA, ++0x28,0x7C,0x60,0x74,0x05,0xF1,0x24,0x00, ++0x41,0x78,0x02,0x78,0x42,0xEA,0x01,0x20, ++0xA0,0x87,0x05,0xF1,0x26,0x00,0x41,0x78, ++0x02,0x78,0x42,0xEA,0x01,0x20,0x60,0x87, ++0x05,0xF1,0x28,0x00,0x41,0x78,0x02,0x78, ++0x42,0xEA,0x01,0x20,0x20,0x87,0x05,0xF1, ++0x2A,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0xE0,0x86,0x05,0xF1,0x30,0x00, ++0x41,0x78,0x02,0x78,0x42,0xEA,0x01,0x20, ++0xE0,0x87,0x05,0xF1,0x2C,0x00,0x07,0x46, ++0x09,0xF0,0xCA,0xEB,0x20,0x64,0x05,0xF1, ++0x32,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0x10,0x22,0xA4,0xF8,0x44,0x00, ++0x05,0xF1,0x40,0x01,0x04,0xF1,0x46,0x00, ++0x09,0xF0,0x76,0xEA,0x10,0x22,0x05,0xF1, ++0x50,0x01,0x04,0xF1,0x56,0x00,0x09,0xF0, ++0x70,0xEA,0x38,0x46,0x09,0xF0,0xB0,0xEB, ++0x00,0xF0,0x01,0x00,0x04,0xF8,0x80,0x0F, ++0x95,0xF8,0x60,0x00,0x60,0x70,0x05,0xF1, ++0x32,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0x03,0xF0,0xBA,0xFA,0x28,0x46, ++0x05,0xF0,0xEE,0xFA,0x02,0x98,0x41,0x7B, ++0x00,0x7B,0x40,0xEA,0x01,0x22,0x02,0x98, ++0xC1,0x7B,0x83,0x7B,0x43,0xEA,0x01,0x20, ++0x02,0x99,0x42,0x43,0xA0,0x69,0x10,0x32, ++0x09,0xF0,0x4A,0xEA,0x02,0x98,0x05,0xF0, ++0x96,0xFA,0x03,0xF0,0x4E,0xFC,0x03,0xF0, ++0xD9,0xFF,0x14,0xF8,0x80,0x19,0x05,0xF5, ++0x80,0x60,0x04,0x90,0x61,0xB9,0x8C,0x49, ++0x00,0x20,0x42,0x46,0x01,0xEB,0x80,0x03, ++0x21,0xF8,0x20,0x00,0x58,0x80,0x40,0x1C, ++0x80,0xB2,0x90,0x42,0xF6,0xD3,0x10,0xE0, ++0x01,0x46,0x85,0x48,0x4F,0xF4,0x00,0x62, ++0x09,0xF0,0x2A,0xEA,0x82,0x48,0x94,0xF8, ++0x81,0x10,0x80,0x89,0x88,0x42,0x04,0xD0, ++0x7D,0x48,0x35,0x38,0x05,0xB0,0xBD,0xE8, ++0xF0,0x8F,0xA0,0x7C,0xFF,0x28,0x14,0xD0, ++0x94,0xF8,0x70,0x10,0x01,0x23,0x03,0x9A, ++0x88,0x40,0x79,0x49,0x09,0x89,0x00,0x93, ++0x53,0x46,0x08,0x44,0x00,0x21,0x80,0xB2, ++0x03,0xF0,0xEE,0xFA,0x28,0xB9,0x03,0x99, ++0x42,0x46,0x01,0x98,0x09,0xF0,0x08,0xEA, ++0x02,0xE0,0x30,0x46,0x05,0xF0,0xF8,0xFB, ++0x4F,0xF0,0x00,0x09,0x4F,0x46,0x60,0x8F, ++0x4F,0xF4,0x00,0x7B,0x58,0x45,0x03,0xD1, ++0x10,0x20,0xA0,0x87,0x03,0x20,0x05,0xE0, ++0x4F,0xF4,0x00,0x60,0x60,0x87,0xC0,0x10, ++0xA0,0x87,0x0A,0x20,0xE0,0x87,0x03,0xF0, ++0xF8,0xFB,0x03,0xF0,0x83,0xFF,0x20,0x8B, ++0x40,0xF4,0x80,0x50,0x20,0x83,0x01,0x23, ++0x94,0xF8,0x70,0x00,0x00,0x21,0x03,0x9A, ++0x00,0x93,0x53,0x46,0x07,0xFA,0x00,0xF0, ++0x1F,0xFA,0x80,0xF8,0x40,0x46,0x03,0xF0, ++0xBB,0xFA,0x06,0x46,0x9A,0xF8,0x00,0x00, ++0xFF,0x28,0x7E,0xD1,0x24,0x35,0x68,0x78, ++0x29,0x78,0x41,0xEA,0x00,0x20,0xA0,0x87, ++0xE8,0x78,0xA9,0x78,0x41,0xEA,0x00,0x20, ++0x60,0x87,0x68,0x7B,0x29,0x7B,0x24,0x3D, ++0x41,0xEA,0x00,0x20,0xE0,0x87,0x03,0xF0, ++0xCC,0xFB,0x03,0xF0,0x57,0xFF,0x20,0x8B, ++0x20,0xF4,0x80,0x50,0x20,0x83,0x38,0x46, ++0x05,0xF0,0x80,0xFB,0x06,0x00,0x7E,0xD1, ++0x61,0x8F,0x03,0x98,0x09,0xF0,0x1E,0xEA, ++0x03,0x98,0x5E,0x46,0x5A,0x46,0x29,0x46, ++0x09,0xF0,0xAE,0xE9,0xA1,0x8F,0x50,0x46, ++0x09,0xF0,0x14,0xEA,0xFF,0x20,0x8A,0xF8, ++0x00,0x00,0x00,0x20,0x8A,0xF8,0x01,0x00, ++0x60,0x8F,0xB0,0x42,0x03,0xD1,0x10,0x20, ++0xA0,0x87,0x03,0x20,0x05,0xE0,0x4F,0xF4, ++0x00,0x60,0x60,0x87,0xC0,0x10,0xA0,0x87, ++0x0A,0x20,0xE0,0x87,0x03,0xF0,0x9D,0xFB, ++0x03,0xF0,0x28,0xFF,0x20,0x8B,0x40,0xF4, ++0x80,0x50,0x20,0x83,0x01,0x23,0x03,0x9A, ++0x00,0x21,0x00,0x93,0x53,0x46,0x40,0x46, ++0x04,0xF0,0xA0,0xFB,0x24,0x35,0x06,0x46, ++0x68,0x78,0x29,0x78,0x41,0xEA,0x00,0x20, ++0xA0,0x87,0xE8,0x78,0xA9,0x78,0x41,0xEA, ++0x00,0x20,0x60,0x87,0x68,0x7B,0x29,0x7B, ++0x24,0x3D,0x41,0xEA,0x00,0x20,0xE0,0x87, ++0x03,0xF0,0x7B,0xFB,0x03,0xF0,0x06,0xFF, ++0x20,0x8B,0x20,0xF4,0x80,0x50,0x20,0x83, ++0x00,0x2E,0x51,0xD1,0x61,0x8F,0x03,0x98, ++0x09,0xF0,0xD0,0xE9,0xDD,0xE9,0x02,0x10, ++0x4F,0xF4,0x00,0x72,0x09,0xF0,0x60,0xE9, ++0xDF,0xF8,0x74,0xB0,0x01,0x23,0x00,0x93, ++0x53,0x46,0xBB,0xF8,0x04,0x00,0x40,0x44, ++0x00,0xE0,0x47,0xE0,0x03,0x9A,0x00,0x21, ++0x04,0xF0,0x6C,0xFB,0x06,0x00,0x37,0xD1, ++0x61,0x8F,0x03,0x98,0x09,0xF0,0xB6,0xE9, ++0x01,0x99,0x4F,0xF4,0x00,0x72,0x03,0x98, ++0x09,0xF0,0x46,0xE9,0x01,0x23,0x03,0x9A, ++0x00,0x93,0x00,0x21,0xBB,0xF8,0x08,0x00, ++0x53,0x46,0x40,0x44,0x04,0xF0,0x56,0xFB, ++0x06,0x00,0x21,0xD1,0x00,0xE0,0x1F,0xE0, ++0x94,0xF8,0x80,0x00,0x01,0x28,0x1F,0xD1, ++0x61,0x8F,0x03,0x98,0x09,0xF0,0x9A,0xE9, ++0xDD,0xE9,0x03,0x01,0x4F,0xF4,0x00,0x62, ++0x09,0xF0,0x2A,0xE9,0x06,0xE0,0x00,0x00, ++0x3A,0x00,0x00,0x80,0x00,0x00,0x10,0x80, ++0x00,0x0D,0x03,0x20,0xBB,0xF8,0x0C,0x00, ++0x01,0x23,0x03,0x99,0x52,0x46,0x40,0x44, ++0x03,0xF0,0xE2,0xF9,0x06,0x00,0x03,0xD0, ++0x38,0x46,0x05,0xF0,0xE7,0xFA,0x05,0xE0, ++0x09,0xF1,0x01,0x00,0xC0,0xB2,0x02,0x28, ++0x81,0x46,0x04,0xD0,0x7F,0x1C,0xBF,0xB2, ++0x0A,0x2F,0xFF,0xF4,0x08,0xAF,0x24,0x35, ++0x68,0x78,0x29,0x78,0x41,0xEA,0x00,0x20, ++0xA0,0x87,0xE8,0x78,0xA9,0x78,0x41,0xEA, ++0x00,0x20,0x60,0x87,0x68,0x7B,0x29,0x7B, ++0x41,0xEA,0x00,0x20,0xE0,0x87,0x03,0xF0, ++0x00,0xFB,0x03,0xF0,0x8B,0xFE,0x20,0x8B, ++0x20,0xF4,0x80,0x50,0x20,0x83,0x5F,0xEA, ++0x09,0x00,0x06,0xD0,0x01,0x28,0x06,0xD0, ++0x02,0x28,0x00,0xD1,0x00,0x26,0x30,0x46, ++0xC4,0xE6,0xFF,0x4E,0xFB,0xE7,0xFE,0x4E, ++0x76,0x1C,0xF8,0xE7,0x2D,0xE9,0xF0,0x4F, ++0x83,0x46,0x85,0xB0,0x03,0xF0,0xB4,0xF8, ++0xD0,0xE9,0x21,0x75,0x04,0x46,0x05,0x20, ++0x04,0x97,0x01,0x90,0x00,0x26,0x05,0xF0, ++0xDB,0xF8,0x01,0x98,0x01,0x23,0x00,0x93, ++0x00,0x21,0x04,0x9B,0x2A,0x46,0x06,0xFA, ++0x00,0xF8,0x40,0x46,0x03,0xF0,0xA8,0xF9, ++0x00,0x28,0x7D,0xD1,0x38,0x78,0xFF,0x28, ++0xFB,0xD1,0xF8,0x78,0xB9,0x78,0x41,0xEA, ++0x00,0x20,0x01,0x28,0x74,0xD8,0x28,0x46, ++0x05,0xF0,0x59,0xF9,0x00,0x28,0xF0,0xD1, ++0x0E,0x21,0x05,0xF1,0x24,0x00,0x05,0xF0, ++0x08,0xF9,0x81,0x46,0x05,0xF1,0x20,0x00, ++0x09,0xF0,0xF2,0xE9,0x48,0x45,0xE4,0xD1, ++0xF8,0x78,0xB9,0x78,0x41,0xEA,0x00,0x20, ++0x00,0xF0,0xFF,0x09,0x28,0x46,0x05,0xF0, ++0x37,0xF9,0x4F,0xF4,0x00,0x72,0x29,0x46, ++0x58,0x46,0x09,0xF0,0x9E,0xE8,0x05,0xF1, ++0x26,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0x60,0x87,0x05,0xF1,0x24,0x00, ++0x41,0x78,0x02,0x78,0x42,0xEA,0x01,0x20, ++0xA0,0x87,0x05,0xF1,0x28,0x00,0x41,0x78, ++0x02,0x78,0x42,0xEA,0x01,0x20,0x20,0x87, ++0x05,0xF1,0x2A,0x00,0x41,0x78,0x02,0x78, ++0x42,0xEA,0x01,0x20,0xE0,0x86,0x05,0xF1, ++0x30,0x00,0x42,0x78,0x01,0x78,0x41,0xEA, ++0x02,0x20,0xE0,0x87,0x28,0x7C,0x60,0x74, ++0x05,0xF1,0x2C,0x00,0x82,0x46,0x09,0xF0, ++0xB8,0xE9,0x20,0x64,0x10,0x22,0x05,0xF1, ++0x40,0x01,0x04,0xF1,0x46,0x00,0x09,0xF0, ++0x6C,0xE8,0x10,0x22,0x05,0xF1,0x50,0x01, ++0x04,0xF1,0x56,0x00,0x09,0xF0,0x64,0xE8, ++0x50,0x46,0x09,0xF0,0xA6,0xE9,0x00,0xF0, ++0x01,0x00,0x84,0xF8,0x80,0x00,0x95,0xF8, ++0x60,0x00,0x84,0xF8,0x81,0x00,0x03,0xF0, ++0x60,0xFA,0x03,0xF0,0xFF,0xFC,0xDF,0xF8, ++0xDC,0xA2,0x01,0x23,0x03,0x95,0x2A,0x46, ++0x00,0x93,0xBA,0xF8,0x04,0x10,0x04,0x9B, ++0x01,0xEB,0x08,0x00,0x00,0x21,0x00,0xE0, ++0x33,0xE0,0x03,0xF0,0x25,0xF9,0x80,0xBB, ++0x28,0x1D,0x4F,0xF4,0xFE,0x71,0x05,0xF0, ++0x94,0xF8,0x02,0x90,0x03,0x98,0x09,0xF0, ++0x80,0xE9,0x01,0x46,0x02,0x98,0x81,0x42, ++0x23,0xD1,0x03,0x98,0x05,0xF0,0x83,0xF8, ++0x03,0x99,0x4F,0xF4,0x00,0x72,0x0B,0xF5, ++0x00,0x70,0x09,0xF0,0x2E,0xE8,0x94,0xF8, ++0x80,0x00,0x01,0x28,0x12,0xD1,0xBA,0xF8, ++0x0C,0x10,0x04,0x9A,0x01,0x23,0x01,0xEB, ++0x08,0x00,0x29,0x46,0x03,0xF0,0xEF,0xF8, ++0x40,0xB9,0x03,0x99,0x4F,0xF4,0x00,0x62, ++0x0B,0xF5,0x80,0x60,0x09,0xF0,0x18,0xE8, ++0x00,0x20,0xF3,0xE5,0xB9,0xF1,0x00,0x0F, ++0x04,0xD1,0x76,0x1C,0xB6,0xB2,0x40,0x2E, ++0xFF,0xF4,0x39,0xAF,0x92,0x48,0x80,0x1D, ++0xE8,0xE5,0x2D,0xE9,0xFF,0x4F,0x83,0x46, ++0x85,0xB0,0x17,0x46,0x1E,0x46,0xDD,0xF8, ++0x48,0xA0,0x02,0xF0,0xD9,0xFF,0x81,0x46, ++0xD0,0xF8,0x98,0x00,0x4F,0xF0,0x00,0x08, ++0x10,0x30,0x45,0x46,0x59,0x46,0x05,0xF0, ++0xA4,0xFA,0x04,0x00,0x02,0xD1,0x86,0x48, ++0x0A,0x38,0x70,0xE0,0x28,0x46,0x6D,0x1C, ++0x50,0x45,0x02,0xD0,0x04,0xF1,0x08,0x00, ++0xF0,0xE7,0xB9,0xF8,0x3A,0x00,0x40,0x0A, ++0x05,0xF0,0x89,0xFA,0x99,0xF8,0x70,0x10, ++0x08,0x44,0x00,0xF0,0xFF,0x0A,0x99,0xF8, ++0x80,0x00,0x01,0x28,0x03,0xD1,0xAA,0xF1, ++0x01,0x00,0x00,0xF0,0xFF,0x0A,0x01,0x20, ++0x00,0xFA,0x0A,0xF0,0x1F,0xFA,0x80,0xFB, ++0xAB,0xF1,0x01,0x00,0x80,0xB2,0x03,0x90, ++0x27,0xFA,0x0A,0xF0,0x80,0xB2,0x04,0x90, ++0x60,0x78,0x21,0x78,0x41,0xEA,0x00,0x25, ++0x00,0x20,0x1B,0xE0,0x60,0x78,0x6D,0x1C, ++0x22,0x78,0xAD,0xB2,0x42,0xEA,0x00,0x21, ++0xE0,0x78,0xA2,0x78,0x42,0xEA,0x00,0x20, ++0xA2,0x79,0x01,0x44,0xE0,0x79,0x42,0xEA, ++0x00,0x20,0x08,0x44,0xA8,0x42,0x30,0xD9, ++0x28,0x46,0x05,0xF0,0x7A,0xFA,0x00,0x28, ++0xE8,0xD0,0x6D,0x1C,0x09,0xF1,0x01,0x00, ++0xAD,0xB2,0x80,0xB2,0x04,0x99,0x81,0x46, ++0x88,0x42,0xF1,0xD9,0x6D,0x1E,0x4D,0xE0, ++0x60,0x78,0x22,0x78,0x42,0xEA,0x00,0x21, ++0xE0,0x78,0xA2,0x78,0x42,0xEA,0x00,0x20, ++0xA2,0x79,0x01,0x44,0xE0,0x79,0x42,0xEA, ++0x00,0x20,0x08,0x44,0x0F,0xE0,0x60,0x78, ++0x6D,0x1C,0x22,0x78,0xAD,0xB2,0x42,0xEA, ++0x00,0x21,0xE0,0x78,0xA2,0x78,0x42,0xEA, ++0x00,0x20,0xA2,0x79,0x01,0x44,0xE0,0x79, ++0x42,0xEA,0x00,0x20,0x08,0x44,0xA8,0x42, ++0x03,0xD8,0x4D,0x48,0x08,0x38,0x80,0x46, ++0x2B,0xE0,0x28,0x46,0x05,0xF0,0x45,0xFA, ++0x00,0x28,0xE4,0xD0,0x03,0x99,0x27,0xFA, ++0x0A,0xF0,0x07,0xEA,0x01,0x02,0x31,0x46, ++0xAB,0xEB,0x02,0x03,0x80,0xB2,0xB3,0x42, ++0x00,0xD2,0x19,0x46,0xCD,0xE9,0x00,0x21, ++0x89,0x46,0x61,0x79,0x03,0x46,0x22,0x79, ++0x06,0x98,0x42,0xEA,0x01,0x21,0x2A,0x46, ++0xC9,0xB2,0x05,0xF0,0x07,0xFC,0x5F,0xEA, ++0x00,0x08,0x0A,0xD1,0x06,0x98,0x6D,0x1C, ++0xA6,0xEB,0x09,0x06,0x00,0xEB,0x49,0x20, ++0x4F,0x44,0x06,0x90,0x00,0x2E,0xAD,0xB2, ++0xAE,0xD1,0x40,0x46,0x09,0xB0,0x2E,0xE5, ++0x2D,0xE9,0xFF,0x4F,0x83,0x46,0x85,0xB0, ++0x17,0x46,0x1E,0x46,0xDD,0xF8,0x48,0xA0, ++0x02,0xF0,0x1E,0xFF,0x81,0x46,0xD0,0xF8, ++0x98,0x00,0x4F,0xF0,0x00,0x08,0x10,0x30, ++0x45,0x46,0x59,0x46,0x05,0xF0,0xE9,0xF9, ++0x04,0x00,0x02,0xD1,0x28,0x48,0x0A,0x38, ++0x74,0xE0,0x28,0x46,0x6D,0x1C,0x50,0x45, ++0x02,0xD0,0x04,0xF1,0x08,0x00,0xF0,0xE7, ++0xB9,0xF8,0x3A,0x00,0x40,0x0A,0x05,0xF0, ++0xCE,0xF9,0x99,0xF8,0x70,0x10,0x08,0x44, ++0x00,0xF0,0xFF,0x0A,0x99,0xF8,0x80,0x00, ++0x01,0x28,0x03,0xD1,0xAA,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x0A,0x01,0x20,0x00,0xFA, ++0x0A,0xF0,0x1F,0xFA,0x80,0xFB,0xAB,0xF1, ++0x01,0x00,0x80,0xB2,0x03,0x90,0x27,0xFA, ++0x0A,0xF0,0x80,0xB2,0x04,0x90,0x60,0x78, ++0x21,0x78,0x41,0xEA,0x00,0x25,0x00,0x20, ++0x1B,0xE0,0x60,0x78,0x6D,0x1C,0x22,0x78, ++0xAD,0xB2,0x42,0xEA,0x00,0x21,0xE0,0x78, ++0xA2,0x78,0x42,0xEA,0x00,0x20,0xA2,0x79, ++0x01,0x44,0xE0,0x79,0x42,0xEA,0x00,0x20, ++0x08,0x44,0xA8,0x42,0x35,0xD9,0x28,0x46, ++0x05,0xF0,0xBF,0xF9,0x00,0x28,0xE8,0xD0, ++0x6D,0x1C,0x09,0xF1,0x01,0x00,0xAD,0xB2, ++0x80,0xB2,0x04,0x99,0x81,0x46,0x88,0x42, ++0xF1,0xD9,0x6D,0x1E,0x51,0xE0,0x00,0x00, ++0x23,0x00,0x00,0x80,0x00,0x0D,0x03,0x20, ++0x60,0x78,0x22,0x78,0x42,0xEA,0x00,0x21, ++0xE0,0x78,0xA2,0x78,0x42,0xEA,0x00,0x20, ++0xA2,0x79,0x01,0x44,0xE0,0x79,0x42,0xEA, ++0x00,0x20,0x08,0x44,0x0F,0xE0,0x60,0x78, ++0x6D,0x1C,0x22,0x78,0xAD,0xB2,0x42,0xEA, ++0x00,0x21,0xE0,0x78,0xA2,0x78,0x42,0xEA, ++0x00,0x20,0xA2,0x79,0x01,0x44,0xE0,0x79, ++0x42,0xEA,0x00,0x20,0x08,0x44,0xA8,0x42, ++0x02,0xD8,0xC7,0x48,0x80,0x46,0x2B,0xE0, ++0x28,0x46,0x05,0xF0,0x86,0xF9,0x00,0x28, ++0xE5,0xD0,0x03,0x99,0x27,0xFA,0x0A,0xF0, ++0x07,0xEA,0x01,0x02,0x31,0x46,0xAB,0xEB, ++0x02,0x03,0x80,0xB2,0xB3,0x42,0x00,0xD2, ++0x19,0x46,0xCD,0xE9,0x00,0x21,0x89,0x46, ++0x61,0x79,0x03,0x46,0x22,0x79,0x06,0x98, ++0x42,0xEA,0x01,0x21,0x2A,0x46,0xC9,0xB2, ++0x05,0xF0,0x5F,0xFA,0x5F,0xEA,0x00,0x08, ++0x0A,0xD1,0x06,0x98,0x6D,0x1C,0xA6,0xEB, ++0x09,0x06,0x00,0xEB,0x49,0x20,0x4F,0x44, ++0x06,0x90,0x00,0x2E,0xAD,0xB2,0xAF,0xD1, ++0x40,0x46,0x3F,0xE7,0x2D,0xE9,0xF0,0x41, ++0x07,0x46,0x02,0xF0,0x65,0xFE,0xD0,0xF8, ++0x98,0x00,0x00,0x26,0x39,0x46,0x10,0x30, ++0x05,0xF0,0x33,0xF9,0x04,0x00,0x02,0xD1, ++0xA7,0x4E,0xB6,0x1E,0x4E,0xE0,0x60,0x78, ++0x21,0x78,0x41,0xEA,0x00,0x25,0x0E,0xE0, ++0x28,0x46,0x05,0xF0,0x42,0xF9,0x40,0xB1, ++0x28,0x46,0x05,0xF0,0x3B,0xF8,0x06,0x00, ++0x03,0xD0,0x28,0x46,0x05,0xF0,0x42,0xF8, ++0x06,0x46,0x6D,0x1C,0xAD,0xB2,0x60,0x78, ++0x21,0x78,0xA2,0x78,0x41,0xEA,0x00,0x20, ++0xE1,0x78,0x42,0xEA,0x01,0x21,0xA2,0x79, ++0x01,0x44,0xE0,0x79,0x42,0xEA,0x00,0x20, ++0x08,0x44,0xA8,0x42,0xE0,0xD8,0x04,0xF1, ++0x08,0x00,0x39,0x46,0x05,0xF0,0x05,0xF9, ++0x04,0x00,0x23,0xD0,0x60,0x78,0x21,0x78, ++0x41,0xEA,0x00,0x25,0x0E,0xE0,0x28,0x46, ++0x05,0xF0,0x17,0xF9,0x40,0xB1,0x28,0x46, ++0x05,0xF0,0x10,0xF8,0x06,0x00,0x03,0xD0, ++0x28,0x46,0x05,0xF0,0x17,0xF8,0x06,0x46, ++0x6D,0x1C,0xAD,0xB2,0x60,0x78,0x22,0x78, ++0x42,0xEA,0x00,0x21,0xE0,0x78,0xA2,0x78, ++0x42,0xEA,0x00,0x20,0xA2,0x79,0x01,0x44, ++0xE0,0x79,0x42,0xEA,0x00,0x20,0x08,0x44, ++0xA8,0x42,0xE0,0xD8,0x30,0x46,0xBD,0xE8, ++0xF0,0x81,0x70,0xB5,0x02,0xF0,0x04,0xFE, ++0xD0,0xF8,0x98,0x40,0x05,0x46,0x0B,0x21, ++0x10,0x34,0x20,0x46,0x05,0xF0,0xD1,0xF8, ++0x08,0xB9,0x20,0x46,0x00,0xE0,0x08,0x30, ++0x41,0x78,0x00,0x78,0x40,0xEA,0x01,0x24, ++0x0C,0xE0,0x20,0x46,0x05,0xF0,0xE1,0xF8, ++0x30,0xB1,0x20,0x46,0x04,0xF0,0xDA,0xFF, ++0x10,0xB1,0x20,0x46,0x04,0xF0,0xE2,0xFF, ++0x64,0x1C,0xA4,0xB2,0xE8,0x8E,0xA0,0x42, ++0xEF,0xD8,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x02,0xF0,0xDE,0xFD,0x05,0x46,0xD0,0xF8, ++0x98,0x00,0x41,0x7C,0x00,0x7C,0x40,0xEA, ++0x01,0x24,0x0C,0xE0,0x20,0x46,0x05,0xF0, ++0xC4,0xF8,0x30,0xB1,0x20,0x46,0x04,0xF0, ++0xBD,0xFF,0x10,0xB1,0x20,0x46,0x04,0xF0, ++0xC5,0xFF,0x64,0x1C,0xA4,0xB2,0xE8,0x8E, ++0xA0,0x42,0xEF,0xD8,0x00,0x20,0x70,0xBD, ++0x70,0xB5,0x06,0x46,0x0D,0x46,0x02,0xF0, ++0xBF,0xFD,0x04,0x46,0xD0,0xF8,0x98,0x00, ++0x31,0x46,0x10,0x30,0x05,0xF0,0x8D,0xF8, ++0x10,0xB9,0x55,0x48,0x80,0x1E,0x70,0xBD, ++0x14,0xF8,0x70,0x1F,0x83,0x78,0xA2,0x78, ++0x11,0x44,0xC2,0x78,0x43,0xEA,0x02,0x20, ++0x88,0x40,0x28,0x60,0x21,0x7C,0x01,0x29, ++0x03,0xD1,0x31,0x04,0x01,0xD4,0x40,0x08, ++0x28,0x60,0x00,0x20,0x70,0xBD,0x10,0xB5, ++0x02,0xF0,0x9E,0xFD,0x90,0xF8,0x70,0x10, ++0x90,0xF8,0x72,0x20,0xC0,0x8E,0x11,0x44, ++0x88,0x40,0x10,0xBD,0x70,0xB5,0x04,0x46, ++0x02,0xF0,0x92,0xFD,0x05,0x46,0x10,0x22, ++0x42,0xA1,0x20,0x46,0x08,0xF0,0xB4,0xED, ++0x68,0x7C,0xA9,0x1C,0x20,0x74,0x04,0xF1, ++0x11,0x00,0x6A,0x7C,0x08,0xF0,0xAC,0xED, ++0xA8,0x8F,0x0E,0x21,0xA0,0x84,0x68,0x8F, ++0xE0,0x84,0x28,0x8F,0x20,0x85,0xE8,0x8E, ++0x60,0x85,0x28,0x6C,0xE0,0x62,0xE8,0x8F, ++0x20,0x86,0x04,0xF1,0x24,0x00,0x04,0xF0, ++0xF0,0xFD,0x20,0x62,0x10,0x22,0xB5,0xF8, ++0x44,0x00,0x05,0xF1,0x46,0x01,0x60,0x86, ++0x04,0xF1,0x40,0x00,0x08,0xF0,0x90,0xED, ++0x10,0x22,0x05,0xF1,0x56,0x01,0x04,0xF1, ++0x50,0x00,0x08,0xF0,0x8A,0xED,0xB5,0xF8, ++0x6E,0x00,0x24,0xF8,0x60,0x0F,0xB5,0xF8, ++0x68,0x00,0x60,0x80,0x95,0xF8,0x30,0x00, ++0x20,0x71,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x02,0xF0,0x52,0xFD,0x00,0x24,0x05,0x46, ++0x08,0xE0,0x20,0x46,0x04,0xF0,0x3A,0xFF, ++0x10,0xB1,0x20,0x46,0x04,0xF0,0x42,0xFF, ++0x64,0x1C,0xA4,0xB2,0xE8,0x8E,0xA0,0x42, ++0xF3,0xD8,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x02,0xF0,0x3E,0xFD,0x00,0x24,0x05,0x46, ++0x0C,0xE0,0x20,0x46,0x05,0xF0,0x29,0xF8, ++0x30,0xB1,0x20,0x46,0x04,0xF0,0x22,0xFF, ++0x10,0xB1,0x20,0x46,0x04,0xF0,0x2A,0xFF, ++0x64,0x1C,0xA4,0xB2,0xE8,0x8E,0xA0,0x42, ++0xEF,0xD8,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x05,0x46,0x04,0xF0,0x13,0xFF,0x04,0x00, ++0x02,0xD0,0x28,0x46,0x04,0xF0,0x1A,0xFF, ++0x20,0x46,0x70,0xBD,0x01,0x23,0x02,0xF0, ++0x12,0xBE,0x01,0x23,0x02,0xF0,0x08,0xBE, ++0x10,0xB5,0x05,0xF0,0x06,0xF8,0x01,0x28, ++0x01,0xD1,0x00,0x20,0x10,0xBD,0x02,0x48, ++0x28,0x30,0x10,0xBD,0x03,0xF0,0x02,0xB8, ++0x1B,0x00,0x00,0x80,0x4D,0x53,0x54,0x41, ++0x52,0x53,0x45,0x4D,0x49,0x55,0x4E,0x46, ++0x44,0x43,0x49,0x53,0x00,0x00,0x00,0x00, ++0x2D,0xE9,0xF0,0x47,0x00,0x26,0x05,0x46, ++0x88,0x46,0x91,0x46,0x05,0xF0,0xC7,0xFB, ++0x00,0x20,0x05,0xF0,0x6E,0xFB,0xDF,0xF8, ++0xF4,0xA3,0xFD,0x4F,0x05,0xF0,0x37,0xFD, ++0x00,0x28,0x56,0xD1,0xFB,0x4C,0x20,0x88, ++0x20,0xF0,0x02,0x00,0x20,0x80,0x4F,0xF4, ++0x7A,0x70,0x05,0xF0,0x87,0xFA,0x20,0x88, ++0x40,0xF0,0x02,0x00,0x20,0x80,0x00,0x24, ++0x38,0xE0,0x05,0xF0,0x8D,0xFC,0xF4,0x48, ++0x80,0x8F,0xA7,0xF8,0x40,0x00,0x58,0xF8, ++0x24,0x00,0xB8,0x85,0x55,0xF8,0x24,0x00, ++0xA7,0xF8,0x70,0x00,0x55,0xF8,0x24,0x00, ++0x00,0x0C,0xA7,0xF8,0x74,0x00,0x38,0x89, ++0x20,0xF0,0x04,0x00,0x38,0x81,0x00,0x20, ++0x05,0xF0,0xE8,0xFD,0x00,0x28,0x2C,0xD1, ++0x38,0x8D,0x40,0xF0,0x01,0x00,0x38,0x85, ++0xB7,0xF8,0xBC,0x00,0x14,0xB9,0x40,0xF0, ++0x04,0x00,0x01,0xE0,0x40,0xF0,0x01,0x00, ++0xA7,0xF8,0xBC,0x00,0x52,0x46,0x4F,0xF4, ++0x80,0x41,0x38,0x46,0x05,0xF0,0xE0,0xFB, ++0x00,0x28,0x16,0xD1,0xB7,0xF8,0x48,0x00, ++0x1E,0xB9,0xC0,0x07,0x01,0xD0,0x01,0x26, ++0xB4,0xE7,0x64,0x1C,0x4C,0x45,0xC4,0xD3, ++0xB7,0xF8,0xBC,0x10,0x38,0x46,0x41,0xF0, ++0x02,0x01,0xA7,0xF8,0xBC,0x10,0x52,0x46, ++0x4F,0xF4,0x00,0x41,0x05,0xF0,0xC8,0xFB, ++0x00,0x28,0xBD,0xE8,0xF0,0x87,0x0B,0x46, ++0xCF,0x49,0x10,0xB5,0x0F,0x22,0x91,0xF8, ++0x8C,0x10,0x01,0x70,0x18,0x46,0xCC,0x49, ++0x8D,0x31,0x08,0xF0,0xB2,0xEC,0x00,0x20, ++0x10,0xBD,0x2D,0xE9,0xF0,0x41,0x04,0x46, ++0x00,0xF5,0x00,0x75,0x07,0xF0,0x82,0xF9, ++0xC6,0x4E,0x10,0xB1,0x30,0x46,0xBD,0xE8, ++0xF0,0x81,0x0E,0x21,0x04,0xF1,0x24,0x00, ++0x07,0xF0,0x6C,0xF9,0x07,0x46,0x04,0xF1, ++0x20,0x00,0x08,0xF0,0xDE,0xED,0x01,0x46, ++0x38,0x46,0x81,0x42,0x4F,0xF4,0x00,0x77, ++0x04,0xD0,0x39,0x46,0x20,0x46,0x07,0xF0, ++0x2E,0xF9,0xE7,0xE7,0x28,0x1D,0x4F,0xF4, ++0xFE,0x71,0x07,0xF0,0x57,0xF9,0x06,0x46, ++0x28,0x46,0x08,0xF0,0xCA,0xED,0xB0,0x42, ++0x06,0xD0,0x39,0x46,0x28,0x46,0x07,0xF0, ++0x1E,0xF9,0xB2,0x48,0x40,0x1C,0xD6,0xE7, ++0x20,0x46,0x07,0xF0,0x7C,0xF9,0x28,0x46, ++0x07,0xF0,0x84,0xF9,0x00,0x20,0xCE,0xE7, ++0x2D,0xE9,0xF0,0x41,0x05,0x46,0x00,0xF5, ++0x00,0x76,0xFF,0xF7,0xBE,0xFF,0x00,0x28, ++0xC5,0xD1,0x00,0x24,0x29,0x46,0x20,0x46, ++0x06,0xF0,0x70,0xFF,0x00,0x28,0xBE,0xD1, ++0x64,0x1C,0xA4,0xB2,0x02,0x2C,0xF5,0xD3, ++0x00,0x24,0xA0,0x1C,0x31,0x46,0x06,0xF0, ++0x65,0xFF,0x07,0x00,0x01,0xD0,0x38,0x46, ++0xB1,0xE7,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF3,0xD3,0x4F,0xF4,0x00,0x72,0x9C,0x48, ++0x31,0x46,0x00,0x68,0x08,0xF0,0x4C,0xEC, ++0x97,0x48,0x10,0x22,0x05,0xF1,0x40,0x01, ++0x9C,0x30,0x08,0xF0,0x46,0xEC,0x94,0x48, ++0x10,0x22,0x05,0xF1,0x50,0x01,0xAC,0x30, ++0x08,0xF0,0x3E,0xEC,0xE3,0xE7,0x70,0xB5, ++0x00,0x24,0x05,0x46,0x00,0xF5,0x00,0x76, ++0x29,0x46,0x20,0x46,0x05,0xF0,0x28,0xFE, ++0x18,0xB1,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF6,0xD3,0x02,0x2C,0x02,0xD1,0x89,0x48, ++0x80,0x1C,0x70,0xBD,0x00,0x24,0x31,0x46, ++0xA0,0x1C,0x05,0xF0,0x19,0xFE,0x05,0x00, ++0x03,0xD0,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF5,0xD3,0x02,0x2C,0x02,0xD1,0x81,0x48, ++0xC0,0x1C,0x70,0xBD,0x80,0x48,0x4F,0xF4, ++0x00,0x72,0x31,0x46,0x00,0x68,0x08,0xF0, ++0x14,0xEC,0x28,0x46,0x70,0xBD,0x7A,0x48, ++0x40,0x68,0x00,0x07,0x01,0xD5,0x05,0xF0, ++0x92,0xBC,0x70,0x47,0x2D,0xE9,0xF0,0x47, ++0x00,0x25,0x20,0x20,0x07,0xF0,0x9C,0xF8, ++0x73,0x4E,0x04,0x00,0x4D,0xD1,0xCC,0x21, ++0x30,0x46,0x08,0xF0,0x8A,0xEC,0x73,0x4F, ++0xA0,0x46,0x4F,0xF4,0x7A,0x7A,0x4F,0xF0, ++0x11,0x09,0x05,0xF0,0x9C,0xFA,0xB7,0xF8, ++0xCC,0x0D,0x20,0xF0,0x02,0x00,0xA7,0xF8, ++0xCC,0x0D,0x50,0x46,0x05,0xF0,0x66,0xF9, ++0x86,0xF8,0x88,0x80,0xA6,0xF8,0x3C,0x90, ++0xB7,0xF8,0xCC,0x0D,0x40,0xF0,0x02,0x00, ++0xA7,0xF8,0xCC,0x0D,0x05,0xF0,0xFF,0xFB, ++0x04,0x00,0x2A,0xD1,0x06,0xF0,0x7E,0xF8, ++0x04,0x00,0x04,0xD0,0x03,0x2D,0x24,0xD2, ++0x6D,0x1C,0xED,0xB2,0xDD,0xE7,0x00,0x20, ++0x05,0xF0,0x23,0xFA,0x06,0xF0,0xE3,0xF8, ++0x04,0x00,0x1A,0xD1,0x30,0x88,0x07,0x21, ++0x05,0xF0,0x4B,0xFF,0x04,0x00,0x14,0xD1, ++0x06,0xF0,0x08,0xFA,0x04,0x00,0x10,0xD1, ++0x00,0x21,0x08,0x20,0x05,0xF0,0xB4,0xFE, ++0x04,0x00,0x0A,0xD1,0x01,0x20,0x06,0xF0, ++0xBD,0xFA,0x04,0x00,0x05,0xD1,0x05,0x20, ++0x05,0xF0,0x07,0xFA,0x51,0x49,0x50,0x48, ++0x08,0x60,0x78,0x36,0x4A,0x49,0x0A,0x22, ++0x46,0xF8,0x70,0x4C,0x2D,0x31,0x01,0xF1, ++0x60,0x00,0x08,0xF0,0xAA,0xEB,0x0B,0x20, ++0x01,0x21,0x30,0x75,0xF0,0x68,0x01,0xEB, ++0x50,0x50,0xF0,0x77,0x00,0xF0,0x12,0xF8, ++0x04,0x00,0x02,0xD0,0x41,0x48,0x40,0x1D, ++0xDB,0xE6,0xFF,0xF7,0x88,0xFF,0x20,0x46, ++0xD7,0xE6,0x42,0x48,0x40,0x49,0x00,0x68, ++0xC9,0x43,0x88,0x42,0x01,0xD0,0x00,0x20, ++0x70,0x47,0x83,0xE7,0x2D,0xE9,0xF0,0x47, ++0x39,0x4D,0x2E,0x68,0xFF,0xF7,0xF1,0xFF, ++0x00,0x28,0x1D,0xD1,0x00,0x24,0xA8,0x46, ++0x4F,0xF4,0xFE,0x79,0xA0,0x1C,0xD8,0xF8, ++0x00,0x10,0x05,0xF0,0x71,0xFD,0x05,0x00, ++0x0A,0xD1,0x30,0x46,0x08,0xF0,0xBC,0xEC, ++0x30,0xB1,0x07,0x46,0x30,0x1D,0x49,0x46, ++0x07,0xF0,0x40,0xF8,0x87,0x42,0x03,0xD0, ++0x64,0x1C,0xA4,0xB2,0x02,0x2C,0xE9,0xD3, ++0x02,0x2C,0x02,0xD1,0x27,0x48,0x80,0x1F, ++0xA7,0xE6,0x25,0x48,0x41,0x68,0x41,0xF0, ++0x02,0x01,0x41,0x60,0x28,0x46,0xA0,0xE6, ++0x23,0x48,0x10,0xB5,0x04,0x68,0x20,0x48, ++0x40,0x68,0x80,0x07,0x03,0xD4,0xFF,0xF7, ++0xC9,0xFF,0x00,0x28,0x0B,0xD1,0x61,0x7B, ++0x22,0x7B,0x00,0x20,0x42,0xEA,0x01,0x21, ++0x02,0xE0,0x4A,0x1E,0x40,0x1C,0x80,0xB2, ++0x81,0x42,0xFA,0xD8,0x00,0x20,0x10,0xBD, ++0x10,0xB5,0x04,0x46,0xFF,0xF7,0xAD,0xFF, ++0x00,0x28,0x0F,0xD1,0x12,0x48,0x40,0x68, ++0x80,0x07,0x03,0xD4,0xFF,0xF7,0xAE,0xFF, ++0x00,0x28,0x07,0xD1,0x4F,0xF4,0x00,0x72, ++0x0F,0x48,0x01,0x68,0x20,0x46,0x08,0xF0, ++0x34,0xEB,0x00,0x20,0x10,0xBD,0x2D,0xE9, ++0xF0,0x41,0x0C,0x46,0x05,0x46,0xFF,0xF7, ++0x94,0xFF,0x00,0x28,0x27,0xD1,0xC4,0xF3, ++0x08,0x00,0x00,0xEB,0x54,0x20,0x81,0xB2, ++0x00,0x20,0x1B,0xE0,0x40,0x42,0x0F,0x00, ++0x00,0x50,0x00,0x25,0xCC,0x0D,0x02,0x25, ++0x20,0x15,0x03,0x20,0x1D,0x00,0x00,0x80, ++0x84,0x05,0x03,0x20,0x00,0x00,0x02,0x25, ++0x43,0x4D,0x4D,0x65,0xC4,0x04,0x03,0x20, ++0x6A,0x79,0x2B,0x79,0x43,0xEA,0x02,0x22, ++0x01,0x2A,0x05,0xD0,0x40,0x1C,0x05,0xF5, ++0x00,0x75,0x80,0xB2,0x88,0x42,0xF3,0xD3, ++0x88,0x42,0x01,0xD1,0xFC,0x48,0x5A,0xE6, ++0x28,0x46,0x08,0xF0,0x42,0xEC,0x04,0x46, ++0x28,0x1D,0x4F,0xF4,0xFE,0x71,0x06,0xF0, ++0xC5,0xFF,0x84,0x42,0x02,0xD0,0xF6,0x48, ++0x40,0x1C,0x4C,0xE6,0x00,0x24,0x29,0x46, ++0xA0,0x1C,0x06,0xF0,0xF7,0xFD,0x00,0x28, ++0xE9,0xD1,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF5,0xD3,0x00,0x24,0xEF,0x4E,0x4F,0xF4, ++0x00,0x78,0xA0,0x1C,0x31,0x68,0x05,0xF0, ++0xD3,0xFC,0x00,0x28,0xDB,0xD1,0x31,0x68, ++0x42,0x46,0x28,0x46,0x06,0xF0,0x85,0xFF, ++0x07,0x00,0x09,0xD0,0x44,0x46,0x41,0x46, ++0x28,0x46,0x06,0xF0,0x70,0xFF,0x30,0x68, ++0x21,0x46,0x06,0xF0,0x6C,0xFF,0x03,0xE0, ++0x64,0x1C,0xA4,0xB2,0x02,0x2C,0xE4,0xD3, ++0x38,0x46,0x20,0xE6,0x2D,0xE9,0xF0,0x41, ++0x07,0x46,0xDE,0x48,0x00,0x25,0x88,0x46, ++0x14,0x46,0x06,0x68,0xDC,0x48,0x40,0x68, ++0x80,0x07,0x03,0xD4,0xFF,0xF7,0x2A,0xFF, ++0x00,0x28,0x21,0xD1,0x00,0x20,0x0E,0xE0, ++0x20,0x88,0x06,0xEB,0xC0,0x00,0x41,0x7D, ++0x02,0x7D,0x42,0xEA,0x01,0x20,0xB8,0x42, ++0x03,0xD1,0x45,0x45,0x0B,0xD0,0x6D,0x1C, ++0xAD,0xB2,0x20,0x88,0x40,0x1C,0x20,0x80, ++0x21,0x88,0x70,0x7B,0x32,0x7B,0x42,0xEA, ++0x00,0x20,0x81,0x42,0xE8,0xD3,0x21,0x88, ++0x70,0x7B,0x32,0x7B,0x42,0xEA,0x00,0x20, ++0x81,0x42,0x02,0xD1,0xC6,0x48,0xC0,0x1C, ++0xED,0xE5,0x00,0x20,0xEB,0xE5,0xF8,0xB5, ++0x06,0x46,0xC4,0x48,0x0D,0x46,0x04,0x68, ++0xFF,0xF7,0xF3,0xFE,0x00,0x28,0x15,0xD1, ++0x00,0x21,0x6A,0x46,0x30,0x46,0xFF,0xF7, ++0xBD,0xFF,0x00,0x28,0x0E,0xD1,0xBD,0xF8, ++0x00,0x00,0x04,0xEB,0xC0,0x00,0xC1,0x7C, ++0x82,0x7C,0x42,0xEA,0x01,0x20,0x61,0x7A, ++0x22,0x7A,0x42,0xEA,0x01,0x21,0x48,0x43, ++0x28,0x60,0x00,0x20,0xF8,0xBD,0x2D,0xE9, ++0xF0,0x5F,0x07,0x46,0xB5,0x48,0x0C,0x46, ++0xB5,0x49,0x90,0x46,0x4F,0xF0,0x00,0x09, ++0x00,0x68,0x88,0x42,0x03,0xD1,0xAE,0x48, ++0x40,0x1E,0xBD,0xE8,0xF0,0x9F,0xE0,0x05, ++0x01,0xD0,0xAB,0x48,0xF9,0xE7,0xDF,0xF8, ++0xB0,0xA2,0xF8,0x06,0xDF,0xF8,0xB4,0xB2, ++0x3B,0xD0,0x40,0x46,0x5D,0x46,0xDB,0xF8, ++0x00,0x10,0x05,0xF0,0x45,0xFC,0x06,0x00, ++0x02,0xD0,0xCA,0xF8,0x08,0x60,0x45,0xE0, ++0x29,0x68,0x4F,0xF4,0x00,0x72,0x38,0x46, ++0x08,0xF0,0x46,0xEA,0xB4,0xF5,0x00,0x74, ++0x08,0xF1,0x01,0x08,0x07,0xF5,0x00,0x77, ++0x38,0xD0,0x4F,0xF0,0x01,0x09,0xA4,0xF5, ++0x00,0x74,0x1E,0xE0,0xB4,0xF5,0x00,0x7F, ++0x10,0xD9,0x40,0xF6,0xFF,0x75,0xB5,0xEB, ++0x54,0x2F,0x01,0xD9,0xC4,0xF3,0x4F,0x25, ++0x2A,0x46,0x39,0x46,0x40,0x46,0x06,0xF0, ++0xEF,0xFB,0x06,0x00,0x08,0xD0,0xCA,0xF8, ++0x08,0x60,0x0C,0xE0,0x01,0x25,0x39,0x46, ++0x40,0x46,0x05,0xF0,0x15,0xFC,0xF4,0xE7, ++0xA8,0x44,0x07,0xEB,0x45,0x27,0xA4,0xEB, ++0x45,0x24,0x00,0x2C,0xDE,0xD1,0xB9,0xF1, ++0x00,0x0F,0x0F,0xD0,0xDB,0xF8,0x00,0x10, ++0x5C,0x46,0x40,0x46,0x05,0xF0,0x04,0xFC, ++0x06,0x00,0x01,0xD0,0xCA,0xF8,0x08,0x60, ++0x21,0x68,0x4F,0xF4,0x00,0x72,0x38,0x46, ++0x08,0xF0,0x06,0xEA,0x30,0x46,0xA0,0xE7, ++0x2D,0xE9,0xFC,0x47,0x80,0x46,0x7D,0x48, ++0x89,0x46,0x0A,0x9F,0x15,0x46,0x1E,0x46, ++0x04,0x68,0xFF,0xF7,0x62,0xFE,0x00,0x28, ++0x1B,0xD1,0x01,0xAA,0x39,0x46,0x40,0x46, ++0xFF,0xF7,0x2C,0xFF,0x00,0x28,0x14,0xD1, ++0xBD,0xF8,0x04,0x00,0x04,0xEB,0xC0,0x00, ++0xC1,0x7C,0x82,0x7C,0x42,0xEA,0x01,0x20, ++0x61,0x7A,0x22,0x7A,0x42,0xEA,0x01,0x21, ++0x48,0x43,0x85,0x42,0x04,0xD8,0x86,0x42, ++0x02,0xD8,0xAA,0x19,0x82,0x42,0x02,0xD9, ++0x69,0x48,0xBD,0xE8,0xFC,0x87,0xBD,0xF8, ++0x04,0x00,0x04,0xEB,0xC0,0x00,0x42,0x7C, ++0x03,0x7C,0x43,0xEA,0x02,0x20,0x00,0xFB, ++0x01,0x52,0x71,0x02,0x48,0x46,0xFF,0xF7, ++0x5A,0xFF,0x00,0x28,0xED,0xD1,0x02,0x23, ++0x00,0x93,0x33,0x46,0x2A,0x46,0x41,0x46, ++0x48,0x46,0x05,0xF0,0x78,0xF8,0xE4,0xE7, ++0x2D,0xE9,0xF0,0x47,0x0C,0x46,0x5D,0x49, ++0x17,0x46,0x5D,0x4A,0x06,0x46,0x09,0x68, ++0x91,0x42,0x02,0xD1,0x56,0x48,0x40,0x1E, ++0xF3,0xE4,0x55,0x4A,0x1E,0xB1,0xE1,0x05, ++0x40,0xF6,0xFF,0x73,0x1E,0xD0,0x10,0x46, ++0xEB,0xE4,0x4C,0x45,0x0B,0xD9,0xB8,0xEB, ++0x54,0x2F,0x45,0x46,0x01,0xD9,0xC4,0xF3, ++0x4F,0x25,0x2A,0x46,0x31,0x46,0x38,0x46, ++0x06,0xF0,0xA7,0xFC,0x04,0xE0,0x01,0x25, ++0x31,0x46,0x38,0x46,0x06,0xF0,0xA2,0xFC, ++0x10,0xB1,0x49,0x49,0x88,0x60,0xD4,0xE4, ++0x2F,0x44,0x06,0xEB,0x45,0x26,0xA4,0xEB, ++0x45,0x24,0x02,0xE0,0x4F,0xF4,0x00,0x79, ++0x98,0x46,0x00,0x2C,0xDD,0xD1,0xC8,0xE4, ++0x2D,0xE9,0xFC,0x47,0x80,0x46,0x3F,0x48, ++0x89,0x46,0x0A,0x9F,0x15,0x46,0x1E,0x46, ++0x04,0x68,0xFF,0xF7,0xE6,0xFD,0x00,0x28, ++0x9F,0xD1,0x01,0xAA,0x39,0x46,0x40,0x46, ++0xFF,0xF7,0xB0,0xFE,0x00,0x28,0x98,0xD1, ++0xBD,0xF8,0x04,0x00,0x04,0xEB,0xC0,0x00, ++0xC1,0x7C,0x82,0x7C,0x42,0xEA,0x01,0x20, ++0x61,0x7A,0x22,0x7A,0x42,0xEA,0x01,0x21, ++0x48,0x43,0x85,0x42,0x04,0xD8,0x86,0x42, ++0x02,0xD8,0xAA,0x19,0x82,0x42,0x01,0xD9, ++0x2B,0x48,0x82,0xE7,0xBD,0xF8,0x04,0x00, ++0x04,0xEB,0xC0,0x00,0x42,0x7C,0x03,0x7C, ++0x43,0xEA,0x02,0x20,0x00,0xFB,0x01,0x52, ++0x71,0x02,0x48,0x46,0xFF,0xF7,0x90,0xFF, ++0x00,0x28,0xEE,0xD1,0x01,0x23,0x00,0x93, ++0x33,0x46,0x2A,0x46,0x41,0x46,0x48,0x46, ++0x04,0xF0,0xFD,0xFF,0x69,0xE7,0x70,0xB5, ++0x10,0x22,0x04,0x46,0x22,0xA1,0x08,0xF0, ++0x40,0xE9,0x1D,0x4D,0x80,0x35,0x05,0xF1, ++0x0D,0x01,0x28,0x7B,0x20,0x74,0x04,0xF1, ++0x11,0x00,0x2A,0x7B,0x08,0xF0,0x34,0xE9, ++0x01,0x20,0xA0,0x84,0x40,0x02,0xE0,0x84, ++0x28,0x68,0x20,0x85,0xD5,0xE9,0x00,0x10, ++0x09,0xF0,0xCA,0xE9,0x60,0x85,0x0E,0x21, ++0x04,0xF1,0x24,0x00,0x06,0xF0,0xF2,0xFD, ++0x05,0xF1,0x1C,0x01,0x20,0x62,0x04,0xF1, ++0x40,0x00,0x50,0x34,0x6C,0xC9,0x6C,0xC0, ++0x08,0x46,0x2E,0xC8,0x00,0x20,0x2E,0xC4, ++0x70,0xBD,0x2D,0xE9,0xF0,0x5F,0x80,0x46, ++0x07,0x4B,0x0D,0x46,0x58,0x68,0xC0,0x07, ++0x1C,0xD0,0x29,0x46,0x40,0x46,0x06,0xF0, ++0xF4,0xF8,0x04,0x46,0x76,0xE0,0x00,0x00, ++0x15,0x00,0x00,0x80,0x84,0x05,0x03,0x20, ++0x20,0x15,0x03,0x20,0xC4,0x04,0x03,0x20, ++0xBC,0xB2,0xB2,0x9A,0x80,0x05,0x03,0x20, ++0x4D,0x53,0x54,0x41,0x52,0x53,0x45,0x4D, ++0x49,0x55,0x4E,0x46,0x44,0x43,0x49,0x53, ++0x00,0x00,0x00,0x00,0xF5,0x4E,0x00,0x21, ++0xFF,0x20,0x4F,0xF4,0x00,0x77,0xBA,0x46, ++0x32,0x68,0x50,0x54,0x49,0x1C,0xB9,0x42, ++0xF9,0xD3,0xF1,0x48,0xD0,0xF8,0x80,0x60, ++0x40,0x46,0x31,0x46,0x09,0xF0,0x80,0xE9, ++0x40,0x1C,0x46,0x43,0xA5,0xEB,0x08,0x00, ++0x83,0x46,0xA6,0xEB,0x08,0x07,0xB8,0x42, ++0x00,0xD2,0x5F,0x46,0x00,0x26,0x12,0xE0, ++0xB9,0x1B,0x50,0x46,0xBA,0xEB,0x41,0x2F, ++0x00,0xD3,0x48,0x02,0x81,0x46,0x01,0x46, ++0xE2,0x48,0x08,0xEB,0x06,0x02,0x00,0x68, ++0xFF,0xF7,0x06,0xFF,0x04,0x00,0x31,0xD1, ++0x06,0xEB,0x59,0x26,0x76,0x1C,0xBE,0x42, ++0xEA,0xD3,0xBB,0x45,0x2A,0xD0,0x47,0x44, ++0xDF,0xF8,0x6C,0xB3,0xE8,0x1B,0xDB,0xF8, ++0x80,0x10,0x89,0x46,0x09,0xF0,0x54,0xE9, ++0x06,0x00,0x06,0xD0,0x38,0x46,0x06,0xFB, ++0x09,0x71,0x06,0xF0,0x96,0xF8,0x04,0x00, ++0x18,0xD1,0xDB,0xF8,0x80,0x00,0xDF,0xF8, ++0x44,0x83,0x06,0xFB,0x00,0x76,0x0F,0xE0, ++0xA8,0x1B,0x57,0x46,0xBA,0xEB,0x40,0x2F, ++0x00,0xD3,0x47,0x02,0xD8,0xF8,0x00,0x00, ++0x32,0x46,0x39,0x46,0xFF,0xF7,0xD8,0xFE, ++0x04,0x00,0x03,0xD1,0x06,0xEB,0x57,0x26, ++0xAE,0x42,0xED,0xD3,0x20,0x46,0x2C,0xE6, ++0x2D,0xE9,0xF8,0x43,0x80,0x46,0xC5,0x48, ++0x04,0x68,0xFF,0xF7,0xF2,0xFC,0x00,0x28, ++0x37,0xD1,0x00,0x25,0x6A,0x46,0x29,0x46, ++0x40,0x46,0xFF,0xF7,0xBB,0xFD,0x58,0xBB, ++0xBD,0xF8,0x00,0x00,0x6D,0x1C,0x23,0x7A, ++0x04,0xEB,0xC0,0x00,0x41,0x7C,0x02,0x7C, ++0x42,0xEA,0x01,0x20,0x61,0x7A,0x43,0xEA, ++0x01,0x22,0xE1,0x79,0xA3,0x79,0x50,0x43, ++0x43,0xEA,0x01,0x21,0x4B,0x0A,0xBD,0xF8, ++0x00,0x10,0x58,0x43,0x04,0xEB,0xC1,0x01, ++0x4E,0x7C,0x09,0x7C,0x41,0xEA,0x06,0x26, ++0xBD,0xF8,0x00,0x10,0x04,0xEB,0xC1,0x01, ++0xCF,0x7C,0x89,0x7C,0x41,0xEA,0x07,0x27, ++0xF1,0x19,0x59,0x43,0x51,0x43,0x49,0x1E, ++0xFF,0xF7,0x3F,0xFF,0x00,0x28,0xCD,0xD0, ++0x00,0x2D,0x02,0xD0,0x40,0x46,0x04,0xF0, ++0x1F,0xFF,0xBD,0xE8,0xF8,0x83,0xA5,0x48, ++0xF8,0xB5,0x05,0x68,0xFF,0xF7,0xB1,0xFC, ++0x00,0x28,0x32,0xD1,0x00,0x26,0x48,0xF2, ++0x0B,0x07,0x6A,0x46,0x31,0x46,0x38,0x46, ++0xFF,0xF7,0x78,0xFD,0x18,0xBB,0xBD,0xF8, ++0x00,0x40,0x76,0x1C,0xF5,0xE7,0x05,0xEB, ++0xC4,0x01,0x2B,0x7A,0xAF,0x79,0x48,0x7C, ++0x0A,0x7C,0x42,0xEA,0x00,0x26,0x68,0x7A, ++0x43,0xEA,0x00,0x22,0xEB,0x79,0x06,0xFB, ++0x02,0xF0,0x47,0xEA,0x03,0x23,0xCF,0x7C, ++0x89,0x7C,0x5B,0x0A,0x41,0xEA,0x07,0x27, ++0xF1,0x19,0x58,0x43,0x59,0x43,0x51,0x43, ++0x49,0x1E,0xFF,0xF7,0x06,0xFF,0x00,0x28, ++0x07,0xD1,0x64,0x1C,0xA4,0xB2,0x69,0x7B, ++0x2A,0x7B,0x42,0xEA,0x01,0x21,0xA1,0x42, ++0xD9,0xD8,0xF8,0xBD,0x86,0x48,0xD0,0xF8, ++0x84,0x10,0x49,0x1E,0x00,0x20,0xF4,0xE6, ++0x2D,0xE9,0xF0,0x5F,0x05,0x46,0x0C,0x46, ++0xFF,0xF7,0x6F,0xFC,0x00,0x28,0x75,0xD1, ++0x49,0x22,0xB3,0x21,0x03,0x20,0x05,0xF0, ++0xE2,0xFA,0x00,0x28,0x6E,0xD1,0x7C,0x4B, ++0x58,0x68,0xC0,0x07,0x06,0xD0,0x21,0x46, ++0x28,0x46,0xFF,0xF7,0xDE,0xFE,0x00,0x28, ++0x64,0xD1,0x5C,0xE0,0x75,0x4E,0xFF,0x21, ++0x4F,0xF4,0x00,0x77,0xB0,0x46,0xB9,0x46, ++0x32,0x68,0x11,0x54,0x40,0x1C,0xB8,0x42, ++0xF8,0xD3,0x71,0x48,0xD0,0xF8,0x80,0x60, ++0x28,0x46,0x31,0x46,0x09,0xF0,0x80,0xE8, ++0x40,0x1C,0x46,0x43,0x60,0x1B,0x82,0x46, ++0x77,0x1B,0xB8,0x42,0x00,0xD2,0x57,0x46, ++0x00,0x26,0xC3,0x46,0x11,0xE0,0xB9,0x1B, ++0x48,0x46,0xB9,0xEB,0x41,0x2F,0x00,0xD3, ++0x48,0x02,0x80,0x46,0x01,0x46,0xDB,0xF8, ++0x00,0x00,0xAA,0x19,0xFF,0xF7,0x08,0xFE, ++0x00,0x28,0x37,0xD1,0x06,0xEB,0x58,0x26, ++0x76,0x1C,0xBE,0x42,0xEB,0xD3,0xBA,0x45, ++0x29,0xD0,0xEE,0x19,0xDF,0xF8,0x70,0xA1, ++0xA0,0x1B,0xDA,0xF8,0x80,0x10,0x88,0x46, ++0x09,0xF0,0x56,0xE8,0x05,0x00,0x06,0xD0, ++0x30,0x46,0x05,0xFB,0x08,0x61,0xFF,0xF7, ++0x98,0xFE,0x00,0x28,0x1E,0xD1,0xDA,0xF8, ++0x80,0x00,0x4F,0x46,0x05,0xFB,0x00,0x65, ++0x0F,0xE0,0x60,0x1B,0x3E,0x46,0xB7,0xEB, ++0x40,0x2F,0x00,0xD3,0x46,0x02,0xDB,0xF8, ++0x00,0x00,0x2A,0x46,0x31,0x46,0xFF,0xF7, ++0xDB,0xFD,0x00,0x28,0x0A,0xD1,0x05,0xEB, ++0x56,0x25,0xA5,0x42,0xED,0xD3,0x48,0x22, ++0xBD,0xE8,0xF0,0x5F,0xB3,0x21,0x03,0x20, ++0x05,0xF0,0x71,0xBA,0x29,0xE5,0x2D,0xE9, ++0xF0,0x47,0x80,0x46,0x0D,0x46,0x14,0x46, ++0xFF,0xF7,0xEF,0xFB,0x00,0x28,0x39,0xD1, ++0x49,0x22,0xB3,0x21,0x03,0x20,0x05,0xF0, ++0x62,0xFA,0x00,0x28,0x32,0xD1,0xE8,0x05, ++0x00,0xD0,0x01,0x20,0x00,0xEB,0x55,0x20, ++0x22,0x46,0x85,0xB2,0x40,0x46,0x69,0x02, ++0xFF,0xF7,0xB2,0xFD,0x00,0x28,0x25,0xD1, ++0xFF,0x21,0x34,0x4F,0x4F,0xF4,0x00,0x76, ++0x3A,0x68,0x11,0x54,0x40,0x1C,0x80,0xB2, ++0xB0,0x42,0xF9,0xD3,0x39,0x68,0xC1,0x20, ++0x06,0xF0,0x6C,0xFA,0x00,0x28,0x15,0xD1, ++0xB1,0x46,0xA4,0xB2,0x15,0xE0,0x39,0x68, ++0x20,0x46,0x05,0xF0,0x4D,0xF9,0x00,0x28, ++0x0C,0xD1,0x39,0x68,0x08,0xEB,0x44,0x20, ++0x4A,0x46,0x06,0xF0,0xFE,0xFB,0x06,0x00, ++0x05,0xD0,0x38,0x68,0x49,0x46,0x06,0xF0, ++0xEA,0xFB,0x30,0x46,0x94,0xE5,0x64,0x1C, ++0xA4,0xB2,0xAC,0x42,0xE7,0xD3,0x0A,0x22, ++0xB1,0x21,0x03,0x20,0x05,0xF0,0x23,0xFA, ++0x00,0x28,0xF3,0xD1,0x48,0x22,0xB3,0x21, ++0x03,0x20,0x05,0xF0,0x1C,0xFA,0x00,0x28, ++0xEC,0xD1,0x01,0x22,0xBD,0xE8,0xF0,0x47, ++0xA2,0x21,0x03,0x20,0x05,0xF0,0x13,0xBA, ++0x70,0xB5,0x05,0x46,0x0C,0x46,0x16,0x46, ++0xFF,0xF7,0x93,0xFB,0x00,0x28,0x1A,0xD1, ++0x49,0x22,0xB3,0x21,0x03,0x20,0x05,0xF0, ++0x06,0xFA,0x00,0x28,0x13,0xD1,0xE0,0x05, ++0x00,0xD0,0x01,0x20,0x00,0xEB,0x54,0x20, ++0x32,0x46,0x00,0x04,0xC1,0x09,0x28,0x46, ++0xFF,0xF7,0xA5,0xFC,0x00,0x28,0x06,0xD1, ++0x48,0x22,0xBD,0xE8,0x70,0x40,0xB3,0x21, ++0x03,0x20,0x05,0xF0,0xF0,0xB9,0x70,0xBD, ++0xFF,0xF7,0x73,0xBB,0x05,0x49,0x04,0x48, ++0x08,0x60,0x70,0x47,0x80,0x05,0x03,0x20, ++0x20,0x15,0x03,0x20,0x84,0x05,0x03,0x20, ++0xBC,0xB2,0xB2,0x9A,0xC4,0x04,0x03,0x20, ++0x41,0x69,0x0A,0x78,0x0A,0x2A,0x0B,0xD2, ++0x4A,0x78,0x05,0x2A,0x08,0xD2,0x8A,0x78, ++0x02,0x2A,0x05,0xD2,0xC9,0x78,0x02,0x29, ++0x02,0xD2,0x01,0x77,0x01,0x20,0x70,0x47, ++0x00,0x20,0x70,0x47,0xB3,0x48,0x80,0x88, ++0x70,0x47,0xB2,0x48,0x00,0x88,0x70,0x47, ++0x41,0x69,0x0A,0x68,0x02,0x60,0xAF,0x48, ++0x82,0x88,0x00,0x88,0x42,0xEA,0x00,0x40, ++0x08,0x60,0x01,0x20,0x70,0x47,0x2D,0xE9, ++0xF0,0x41,0x00,0x24,0x87,0x69,0x05,0x46, ++0x0E,0x46,0x04,0xE0,0x38,0x5D,0x00,0xF0, ++0x4F,0xFE,0x64,0x1C,0xA4,0xB2,0xB4,0x42, ++0xF8,0xD3,0xA8,0x69,0x30,0x44,0xA8,0x61, ++0x28,0x68,0x80,0x1B,0x28,0x60,0x03,0xD1, ++0xA1,0x48,0x28,0x62,0x02,0x20,0x28,0x60, ++0x01,0x20,0xBD,0xE8,0xF0,0x81,0x70,0xB5, ++0x04,0x46,0x00,0xF0,0x55,0xFE,0x60,0x69, ++0x00,0x78,0x00,0xF0,0x35,0xFE,0x61,0x6A, ++0x20,0x46,0x88,0x47,0x05,0x00,0x0A,0xD0, ++0x98,0x48,0x20,0x62,0x41,0xF2,0x88,0x30, ++0xFC,0xF7,0xC0,0xFE,0xE1,0x6A,0x88,0x88, ++0x40,0xF4,0x80,0x70,0x88,0x80,0x28,0x46, ++0x70,0xBD,0xF8,0xB5,0x04,0x46,0x87,0x69, ++0x15,0x20,0x00,0x25,0x0E,0x46,0x00,0x90, ++0x04,0xE0,0x78,0x5D,0x00,0xF0,0x18,0xFE, ++0x6D,0x1C,0xAD,0xB2,0xB5,0x42,0xF8,0xD3, ++0xA0,0x69,0x30,0x44,0xA0,0x61,0x20,0x68, ++0x80,0x1B,0x20,0x60,0x34,0xD1,0x00,0xF0, ++0x1E,0xFE,0x30,0xB1,0xA1,0x6A,0x21,0xB1, ++0x20,0x46,0x88,0x47,0x08,0xB1,0x06,0x20, ++0x00,0x90,0x01,0x21,0xE0,0x6A,0x00,0x68, ++0x82,0x68,0x68,0x46,0x90,0x47,0x9D,0xF8, ++0x00,0x00,0x06,0x28,0x12,0xD1,0xA0,0x6A, ++0x7D,0x49,0x88,0x42,0x05,0xD1,0xE1,0x6A, ++0x60,0x69,0x09,0x68,0x49,0x68,0x88,0x47, ++0x08,0xE0,0x7A,0x49,0x88,0x42,0x05,0xD1, ++0xE2,0x6A,0x21,0x68,0x60,0x69,0x12,0x68, ++0x92,0x68,0x90,0x47,0x76,0x48,0x20,0x62, ++0x04,0xF1,0x08,0x00,0x60,0x61,0xA0,0x61, ++0x01,0x20,0x20,0x60,0x00,0x20,0xA0,0x62, ++0x41,0xF2,0x88,0x30,0xFC,0xF7,0x6E,0xFE, ++0x01,0x20,0xF8,0xBD,0x41,0x69,0x09,0x68, ++0x41,0x60,0x01,0x20,0x70,0x47,0x70,0xB5, ++0x04,0x46,0x40,0x69,0x21,0x69,0x05,0x68, ++0x6A,0x48,0x09,0x1A,0xFE,0xF7,0xCA,0xF8, ++0xA8,0x42,0x0B,0xD1,0xE0,0x6A,0x81,0x88, ++0x21,0xF4,0x80,0x71,0x81,0x80,0xE0,0x6A, ++0x81,0x88,0x41,0xF4,0x00,0x71,0x81,0x80, ++0x01,0x20,0x70,0xBD,0x00,0x20,0x70,0xBD, ++0x41,0x69,0x60,0x4A,0x09,0x68,0x11,0x44, ++0x02,0x69,0x8A,0x42,0x02,0xD3,0x01,0x61, ++0x01,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0x42,0x68,0x01,0x69,0x11,0x44,0x01,0x61, ++0x01,0x20,0x70,0x47,0x30,0xB5,0x01,0x24, ++0x41,0x69,0x04,0x23,0x00,0xF1,0x08,0x02, ++0x09,0x78,0x05,0x29,0x1C,0xD0,0x07,0xDC, ++0x01,0x29,0x15,0xD0,0x02,0x29,0x15,0xD0, ++0x04,0x29,0x22,0xD1,0x50,0x49,0x16,0xE0, ++0x07,0x29,0x13,0xD0,0x16,0x29,0x1C,0xD1, ++0x42,0x68,0x01,0x69,0x4D,0x4D,0x8B,0x18, ++0xAB,0x42,0x10,0xD8,0x41,0x61,0x4C,0x4B, ++0x83,0x62,0x02,0x60,0x81,0x61,0x11,0xE0, ++0x4A,0x49,0x04,0xE0,0x42,0x49,0x02,0xE0, ++0x49,0x49,0x00,0xE0,0x41,0x49,0x42,0x61, ++0x03,0x60,0x82,0x61,0x03,0xE0,0x41,0x61, ++0x02,0x60,0x81,0x61,0x00,0x21,0x81,0x62, ++0x00,0xE0,0x00,0x24,0x20,0x46,0x30,0xBD, ++0x3C,0x49,0x00,0x22,0x10,0xB5,0xC4,0x6A, ++0x01,0x61,0x39,0x49,0x02,0x77,0x01,0x62, ++0x3E,0x49,0x41,0x62,0x00,0xF1,0x08,0x01, ++0x41,0x61,0x81,0x61,0x01,0x21,0x82,0x62, ++0x01,0x60,0x00,0xF0,0x87,0xF8,0xA0,0x88, ++0x20,0xF4,0x80,0x70,0x80,0xB2,0x20,0xF4, ++0x00,0x70,0xA0,0x80,0x10,0xBD,0x37,0x49, ++0x35,0x48,0x08,0x60,0x36,0x49,0xC8,0x62, ++0x08,0x46,0xDD,0xE7,0x25,0x49,0xEB,0x20, ++0x08,0x81,0x70,0x47,0xF8,0xB5,0x00,0x25, ++0x31,0x4E,0x18,0x27,0xF4,0x6A,0xA0,0x88, ++0x81,0x05,0x01,0xD5,0x01,0x20,0xF8,0xBD, ++0xC1,0x05,0x09,0xD4,0x2D,0xB9,0x2D,0x49, ++0x65,0xF3,0x01,0x00,0x21,0x60,0xA0,0x80, ++0x06,0xE0,0x00,0x20,0x20,0x60,0x2B,0xE0, ++0xC0,0xF3,0x01,0x00,0xA8,0x42,0x27,0xD1, ++0x22,0x68,0x31,0x68,0xB0,0x69,0xD2,0x68, ++0x90,0x47,0x00,0x28,0x05,0xDD,0x32,0x6A, ++0x01,0x46,0x30,0x46,0x90,0x47,0xD8,0xB9, ++0x0B,0xE0,0x01,0x07,0x07,0xD5,0x40,0x07, ++0x16,0xD5,0x30,0x7F,0xA0,0xB1,0x20,0x68, ++0x00,0x68,0x80,0x47,0x10,0xE0,0x80,0x07, ++0x0E,0xD5,0x20,0x68,0x00,0x69,0x80,0x47, ++0x30,0x46,0xFF,0xF7,0xA1,0xFF,0x00,0x97, ++0x01,0x21,0x20,0x68,0x82,0x68,0x68,0x46, ++0x90,0x47,0x20,0x68,0x40,0x69,0xEC,0xE7, ++0x6D,0x1C,0x15,0xF0,0xFF,0x05,0xBE,0xD0, ++0x00,0x20,0xF8,0xBD,0x00,0x70,0x00,0x25, ++0x2B,0x52,0x03,0x20,0xBF,0x51,0x03,0x20, ++0x79,0x51,0x03,0x20,0xA9,0x51,0x03,0x20, ++0xF7,0x51,0x03,0x20,0x00,0x40,0x04,0x20, ++0xCF,0x52,0x03,0x20,0x00,0x32,0x05,0x20, ++0x19,0x53,0x03,0x20,0xC5,0x52,0x03,0x20, ++0x01,0x53,0x03,0x20,0x25,0x53,0x03,0x20, ++0x88,0x05,0x03,0x20,0x78,0xD4,0x02,0x20, ++0xE0,0x05,0x03,0x20,0x70,0xEB,0x03,0x20, ++0x01,0x46,0x5A,0x48,0x00,0xF0,0x70,0xB8, ++0x58,0x49,0x4A,0x69,0x92,0x06,0xFC,0xD5, ++0x08,0x60,0x70,0x47,0x70,0x47,0x30,0xB5, ++0x00,0x23,0x04,0x46,0x0D,0x46,0x03,0xE0, ++0xE0,0x5C,0xFF,0xF7,0xF1,0xFF,0x5B,0x1C, ++0xAB,0x42,0xF9,0xD3,0x28,0x46,0x30,0xBD, ++0x30,0xB4,0x4E,0x4C,0x83,0x78,0x42,0x78, ++0x01,0x78,0x20,0x46,0x30,0xBC,0x00,0xF0, ++0x61,0xB8,0x38,0xB5,0x4A,0xA0,0x49,0x4D, ++0xFC,0xF7,0x64,0xFE,0x4E,0x48,0x01,0x68, ++0x21,0xF4,0x00,0x41,0x01,0x60,0x4D,0x48, ++0x81,0x88,0x41,0xF0,0x20,0x01,0x81,0x80, ++0x01,0x88,0x21,0xF4,0xE0,0x71,0x41,0xF0, ++0x40,0x01,0x01,0x80,0x48,0x4C,0x20,0x68, ++0x20,0xF4,0x70,0x60,0x20,0x60,0x47,0xA0, ++0xFC,0xF7,0x4C,0xFE,0xE0,0x68,0x20,0xF0, ++0x0F,0x00,0xE0,0x60,0x4A,0xA0,0xFC,0xF7, ++0x45,0xFE,0x00,0x20,0x8D,0xF8,0x00,0x00, ++0x8D,0xF8,0x01,0x00,0x8D,0xF8,0x02,0x00, ++0x68,0x46,0xFF,0xF7,0xC9,0xFF,0x4B,0xA0, ++0xFC,0xF7,0x38,0xFE,0x03,0x20,0xA8,0x60, ++0x01,0x21,0x28,0x46,0x00,0xF0,0x1C,0xF8, ++0x38,0xBD,0x2E,0x48,0x03,0x21,0x81,0x60, ++0x01,0x68,0x00,0x21,0x00,0xF0,0x14,0xB8, ++0x2A,0x4B,0x10,0xB5,0x04,0x46,0x00,0x20, ++0x5A,0x69,0x12,0xF0,0x9E,0x01,0x05,0xD1, ++0xD1,0x07,0x02,0xD0,0x18,0x68,0x20,0x70, ++0x01,0x20,0x10,0xBD,0x43,0x48,0xC9,0x06, ++0xFB,0xD5,0x00,0x1D,0x10,0xBD,0xAC,0xE7, ++0x01,0x29,0x06,0xD1,0x41,0x69,0x49,0x06, ++0xFC,0xD5,0xC1,0x68,0x41,0xF0,0x40,0x01, ++0x02,0xE0,0xC1,0x68,0x21,0xF0,0x40,0x01, ++0xC1,0x60,0x70,0x47,0xF0,0xB5,0x04,0x46, ++0x8B,0xB0,0x0D,0x46,0x16,0x46,0x1F,0x46, ++0x60,0x69,0x40,0x06,0xFC,0xD5,0x36,0xA0, ++0xFC,0xF7,0xFC,0xFD,0xE0,0x68,0x40,0xF0, ++0x80,0x00,0xE0,0x60,0x28,0x22,0x36,0x49, ++0x01,0xA8,0x07,0xF0,0x80,0xED,0x01,0xA8, ++0x50,0xF8,0x25,0x10,0x33,0xA0,0xFC,0xF7, ++0xED,0xFD,0x31,0x48,0x14,0x38,0x30,0xF8, ++0x15,0x10,0xC9,0xB2,0x21,0x60,0x30,0xF8, ++0x15,0x00,0x00,0x0A,0x60,0x60,0x2C,0x48, ++0x2B,0x49,0x1A,0x38,0x1C,0x39,0x80,0x5D, ++0xC9,0x5D,0x08,0x43,0x40,0xF0,0x03,0x00, ++0xE0,0x60,0x03,0x20,0xA0,0x60,0x20,0x68, ++0x0B,0xB0,0xF0,0xBD,0x00,0x64,0x40,0x25, ++0x4D,0x44,0x72,0x76,0x5F,0x6D,0x63,0x75, ++0x5F,0x64,0x77,0x5F,0x75,0x61,0x72,0x74, ++0x30,0x5F,0x49,0x6E,0x69,0x74,0x0A,0x00, ++0x14,0x2C,0x02,0x25,0xC8,0x70,0x00,0x25, ++0x10,0x24,0x40,0x25,0x32,0x2E,0x4D,0x44, ++0x72,0x76,0x5F,0x6D,0x63,0x75,0x5F,0x64, ++0x77,0x5F,0x75,0x61,0x72,0x74,0x30,0x5F, ++0x49,0x6E,0x69,0x74,0x0A,0x00,0x00,0x00, ++0x33,0x2E,0x4D,0x44,0x72,0x76,0x5F,0x6D, ++0x63,0x75,0x5F,0x64,0x77,0x5F,0x75,0x61, ++0x72,0x74,0x30,0x5F,0x49,0x6E,0x69,0x74, ++0x0A,0x00,0x00,0x00,0x45,0x6E,0x64,0x20, ++0x6F,0x66,0x20,0x4D,0x44,0x72,0x76,0x5F, ++0x6D,0x63,0x75,0x5F,0x64,0x77,0x5F,0x75, ++0x61,0x72,0x74,0x30,0x5F,0x49,0x6E,0x69, ++0x74,0x0A,0x00,0x00,0x02,0x00,0x00,0x80, ++0x55,0x61,0x72,0x74,0x43,0x68,0x61,0x6E, ++0x5F,0x43,0x6F,0x6E,0x66,0x69,0x67,0x00, ++0xAC,0xEB,0x03,0x20,0x64,0x62,0x62,0x5F, ++0x6D,0x63,0x75,0x5F,0x64,0x77,0x5F,0x75, ++0x61,0x72,0x74,0x5F,0x42,0x52,0x28,0x25, ++0x64,0x29,0x0A,0x00,0xFF,0x48,0x00,0x68, ++0xC0,0xF3,0x01,0x00,0x02,0x28,0x01,0xD1, ++0x01,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0x70,0xB5,0x04,0x46,0xF9,0x4D,0x01,0x20, ++0x70,0x35,0x28,0x80,0x4F,0xF4,0x7A,0x70, ++0xFC,0xF7,0x7C,0xFC,0x03,0x20,0x28,0x80, ++0x28,0x80,0x00,0x20,0xA5,0xF2,0x74,0x45, ++0x9C,0xB1,0x01,0x2C,0x17,0xD0,0x02,0x2C, ++0x20,0xD0,0x03,0x2C,0x0A,0xD1,0x43,0xF2, ++0x77,0x01,0xA5,0xF8,0x7C,0x14,0xD4,0x21, ++0xA5,0xF8,0x78,0x14,0x4F,0xF4,0x00,0x41, ++0xA5,0xF8,0x90,0x14,0xA5,0xF8,0x74,0x04, ++0x70,0xBD,0x44,0xF2,0x44,0x01,0xA5,0xF8, ++0x7C,0x14,0x31,0x21,0x10,0xE0,0x43,0xF2, ++0x55,0x01,0xA5,0xF8,0x7C,0x14,0x40,0xF2, ++0x52,0x51,0xA5,0xF8,0x78,0x14,0x4F,0xF4, ++0x80,0x41,0xE9,0xE7,0x4F,0xF4,0x40,0x51, ++0xA5,0xF8,0x7C,0x14,0x40,0xF2,0x94,0x51, ++0xA5,0xF8,0x78,0x14,0xA5,0xF8,0x90,0x04, ++0xE0,0xE7,0x70,0x47,0xDB,0x48,0xDA,0x49, ++0x01,0x60,0x89,0x1C,0x41,0x60,0x81,0x60, ++0xD9,0x49,0xC1,0x60,0xD9,0x49,0x01,0x61, ++0x4F,0xF4,0x12,0x11,0x41,0x61,0x4F,0xF4, ++0xE8,0x11,0x81,0x61,0xD6,0x49,0x81,0x65, ++0xD6,0x49,0x41,0x65,0xD6,0x49,0xC1,0x65, ++0xD6,0x49,0x01,0x66,0xD6,0x49,0x41,0x66, ++0xD6,0x49,0x81,0x66,0x4F,0xF4,0x00,0x41, ++0xC1,0x66,0x49,0x10,0x01,0x67,0xD4,0x49, ++0x81,0x67,0x00,0x21,0x01,0x65,0x4F,0xF4, ++0x83,0x51,0xC0,0xF8,0x80,0x10,0x41,0xF2, ++0x3C,0x01,0xC0,0xF8,0x84,0x10,0xC0,0xF8, ++0x88,0x10,0xC0,0xF8,0x8C,0x10,0x70,0x47, ++0x2D,0xE9,0xF0,0x4F,0x07,0x46,0xC9,0xB0, ++0xFD,0xF7,0xA3,0xFB,0x00,0x21,0x45,0x90, ++0x43,0xA8,0x0A,0x46,0x06,0xC0,0x41,0xA8, ++0x06,0xC0,0x01,0x20,0xC5,0x49,0x40,0x90, ++0x3D,0xA8,0x1C,0xC9,0xF0,0x21,0x1C,0xC0, ++0x01,0xA8,0x07,0xF0,0x4A,0xEC,0xB5,0x4C, ++0x00,0x26,0xC1,0x4D,0x78,0x34,0x48,0x96, ++0xA2,0x46,0x2E,0x80,0x4F,0xF4,0x70,0x41, ++0xA9,0x80,0x2E,0x81,0x45,0xF6,0xA5,0x20, ++0xA8,0x81,0x28,0x8C,0x47,0x90,0x4F,0xF4, ++0x58,0x50,0x28,0x84,0xA5,0xF2,0xC4,0x55, ++0x38,0x46,0xFF,0xF7,0x5D,0xFF,0xB4,0xF8, ++0x00,0x90,0x20,0x88,0x00,0x27,0xAB,0x46, ++0x00,0xF4,0x70,0x40,0x46,0x90,0x07,0xEB, ++0x47,0x00,0x01,0xA9,0x01,0xEB,0xC0,0x05, ++0x3D,0xA8,0x50,0xF8,0x27,0x00,0x28,0x60, ++0x80,0xB2,0xFD,0xF7,0x58,0xFB,0x00,0x24, ++0x4F,0xF0,0x01,0x0C,0xBC,0xEB,0x14,0x1F, ++0x05,0xD1,0x48,0x46,0x64,0xF3,0x07,0x10, ++0x80,0x46,0xCC,0x20,0x06,0xE0,0x20,0x09, ++0x06,0xD1,0x48,0x46,0x64,0xF3,0x03,0x00, ++0x80,0x46,0x33,0x20,0xAB,0xF8,0xF4,0x05, ++0xAA,0xF8,0x00,0x80,0x00,0x20,0xDF,0xF8, ++0x84,0xE2,0x03,0x46,0x5A,0x46,0xA2,0xF8, ++0xC0,0x35,0x1E,0xF8,0x00,0x10,0xA2,0xF8, ++0xC0,0x15,0xB2,0xF8,0xC0,0x15,0x09,0x04, ++0xFB,0xD5,0xB2,0xF8,0xC0,0x15,0x11,0xF4, ++0xC0,0x4F,0x03,0xD1,0x40,0x1C,0xC0,0xB2, ++0x03,0x28,0xEC,0xD3,0xA2,0xF8,0xC0,0x35, ++0x03,0x28,0x0C,0xD1,0x04,0xF0,0x0F,0x00, ++0x3E,0xB9,0xBC,0xEB,0x14,0x1F,0x01,0xD1, ++0xA8,0x60,0x02,0xE0,0x21,0x09,0x00,0xD1, ++0x68,0x60,0x76,0x1C,0xF6,0xB2,0xE0,0x43, ++0x00,0x07,0x1E,0xD1,0x00,0x2E,0x1C,0xD0, ++0xBC,0xEB,0x14,0x1F,0xC5,0xF8,0x14,0xC0, ++0x09,0xD1,0xA8,0x68,0x76,0x1E,0x81,0x19, ++0x87,0xA0,0x29,0x61,0xFC,0xF7,0x6A,0xFC, ++0xA9,0x68,0x8C,0xA0,0x0A,0xE0,0x20,0x09, ++0x0A,0xD1,0x68,0x68,0x76,0x1E,0x81,0x19, ++0x8F,0xA0,0xE9,0x60,0xFC,0xF7,0x5E,0xFC, ++0x69,0x68,0x94,0xA0,0xFC,0xF7,0x5A,0xFC, ++0x00,0x26,0x64,0x1C,0xE4,0xB2,0x20,0x2C, ++0x9A,0xD3,0x7F,0x1C,0xBF,0xB2,0x03,0x2F, ++0x89,0xD3,0x00,0x20,0x5C,0x46,0xAB,0xF8, ++0xF4,0x05,0x45,0x98,0xFD,0xF7,0xE7,0xFA, ++0x00,0x21,0x01,0xAB,0x01,0xEB,0x41,0x00, ++0x03,0xEB,0xC0,0x00,0x42,0x69,0xFA,0xB1, ++0x40,0x9A,0x4A,0xB1,0x00,0x22,0x40,0x92, ++0xC2,0x68,0x41,0x92,0x02,0x69,0x42,0x92, ++0x42,0x68,0x43,0x92,0x82,0x68,0x44,0x92, ++0xC2,0x68,0x41,0x9D,0xAA,0x42,0x00,0xD9, ++0x41,0x92,0x02,0x69,0x42,0x9D,0xAA,0x42, ++0x00,0xD9,0x42,0x92,0x42,0x68,0x43,0x9D, ++0xAA,0x42,0x00,0xD2,0x43,0x92,0x80,0x68, ++0x44,0x9A,0x90,0x42,0x00,0xD2,0x44,0x90, ++0x49,0x1C,0x89,0xB2,0x03,0x29,0xD5,0xD3, ++0x43,0x99,0x41,0x98,0x43,0x9A,0x48,0x40, ++0x41,0x99,0x00,0xF0,0x01,0x00,0x44,0x9B, ++0x11,0x44,0x44,0x9A,0x00,0xEB,0x51,0x01, ++0x42,0x98,0x50,0x40,0x42,0x9A,0x00,0xF0, ++0x01,0x00,0x1A,0x44,0x00,0xEB,0x52,0x00, ++0x41,0xEA,0x00,0x10,0x46,0x99,0xC0,0xB2, ++0x08,0x43,0xAA,0xF8,0x00,0x00,0xA4,0xF8, ++0xD0,0x05,0xBA,0xF8,0x00,0x10,0x6C,0xA0, ++0xFC,0xF7,0xFC,0xFB,0x47,0x98,0xA4,0xF8, ++0xE4,0x05,0x48,0x98,0x49,0xB0,0xBD,0xE8, ++0xF0,0x8F,0x2D,0xE9,0xF0,0x4F,0xC9,0xB0, ++0xFD,0xF7,0x9B,0xFA,0x00,0x21,0x45,0x90, ++0x43,0xA8,0x0A,0x46,0x3D,0xAC,0x06,0xC0, ++0x41,0xA8,0x06,0xC0,0x01,0x20,0x40,0x90, ++0x40,0x48,0x0C,0x30,0x0E,0xC8,0x0E,0xC4, ++0xFF,0xF7,0x64,0xFE,0x01,0x28,0x01,0xD1, ++0x00,0x20,0xE3,0xE7,0xF0,0x21,0x01,0xA8, ++0x07,0xF0,0x3A,0xEB,0x2D,0x49,0x00,0x26, ++0x39,0x48,0x78,0x31,0x48,0x96,0x8A,0x46, ++0x06,0x80,0x4F,0xF4,0x70,0x43,0x83,0x80, ++0x06,0x81,0x45,0xF6,0xA5,0x23,0x83,0x81, ++0x03,0x8C,0x47,0x93,0x4F,0xF4,0x58,0x53, ++0x03,0x84,0xA0,0xF2,0xC4,0x5B,0xB1,0xF8, ++0x00,0x90,0x09,0x88,0x00,0x27,0x01,0xF4, ++0x70,0x41,0x46,0x91,0x07,0xEB,0x47,0x00, ++0x01,0xA9,0x01,0xEB,0xC0,0x05,0x3D,0xA8, ++0x50,0xF8,0x27,0x00,0x28,0x60,0x80,0xB2, ++0xFD,0xF7,0x4D,0xFA,0x00,0x24,0x4F,0xF0, ++0x01,0x0C,0xBC,0xEB,0x14,0x1F,0x05,0xD1, ++0x48,0x46,0x64,0xF3,0x07,0x10,0x80,0x46, ++0xCC,0x20,0x06,0xE0,0x20,0x09,0x06,0xD1, ++0x48,0x46,0x64,0xF3,0x03,0x00,0x80,0x46, ++0x33,0x20,0xAB,0xF8,0xF4,0x05,0xAA,0xF8, ++0x00,0x80,0x00,0x20,0xDF,0xF8,0x6C,0xE0, ++0x03,0x46,0x5A,0x46,0xA2,0xF8,0xC0,0x35, ++0x1E,0xF8,0x00,0x10,0xA2,0xF8,0xC0,0x15, ++0xB2,0xF8,0xC0,0x15,0x09,0x04,0xFB,0xD5, ++0xB2,0xF8,0xC0,0x15,0x11,0xF4,0xC0,0x4F, ++0x03,0xD1,0x40,0x1C,0xC0,0xB2,0x03,0x28, ++0xEC,0xD3,0xA2,0xF8,0xC0,0x35,0x03,0x28, ++0x6D,0xD1,0x5F,0xE0,0x04,0x24,0x00,0x25, ++0x01,0x00,0x1D,0x00,0x00,0x3E,0x30,0x25, ++0x77,0x30,0x1F,0x00,0xDC,0x00,0x1E,0x00, ++0x01,0x06,0x01,0x00,0x14,0x28,0x50,0x00, ++0x77,0x30,0x00,0x30,0x55,0x30,0x45,0x40, ++0xD4,0x00,0x94,0x05,0x52,0x05,0x31,0x00, ++0x1F,0x1E,0x24,0x00,0xD4,0xEB,0x03,0x20, ++0xC4,0x25,0x00,0x25,0xC8,0x04,0x03,0x20, ++0x70,0x68,0x5F,0x64,0x61,0x74,0x61,0x2D, ++0x3E,0x6D,0x61,0x78,0x5F,0x64,0x71,0x5B, ++0x31,0x5D,0x20,0x3D,0x20,0x25,0x23,0x78, ++0x0A,0x00,0x00,0x00,0x70,0x68,0x5F,0x64, ++0x61,0x74,0x61,0x2D,0x3E,0x6D,0x69,0x6E, ++0x5F,0x64,0x71,0x5B,0x31,0x5D,0x20,0x3D, ++0x20,0x25,0x23,0x78,0x0A,0x00,0x00,0x00, ++0x70,0x68,0x5F,0x64,0x61,0x74,0x61,0x2D, ++0x3E,0x6D,0x61,0x78,0x5F,0x64,0x71,0x5B, ++0x30,0x5D,0x20,0x3D,0x20,0x25,0x23,0x78, ++0x0A,0x00,0x00,0x00,0x70,0x68,0x5F,0x64, ++0x61,0x74,0x61,0x2D,0x3E,0x6D,0x69,0x6E, ++0x5F,0x64,0x71,0x5B,0x30,0x5D,0x20,0x3D, ++0x20,0x25,0x23,0x78,0x0A,0x00,0x00,0x00, ++0x75,0x33,0x32,0x44,0x71,0x73,0x50,0x68, ++0x41,0x64,0x64,0x72,0x3D,0x25,0x30,0x34, ++0x58,0x0A,0x00,0x00,0x04,0xF0,0x0F,0x00, ++0x3E,0xB9,0xBC,0xEB,0x14,0x1F,0x01,0xD1, ++0xA8,0x60,0x02,0xE0,0x21,0x09,0x00,0xD1, ++0x68,0x60,0x76,0x1C,0xF6,0xB2,0xE0,0x43, ++0x00,0x07,0x22,0xD1,0x00,0x2E,0x20,0xD0, ++0xBC,0xEB,0x14,0x1F,0xC5,0xF8,0x14,0xC0, ++0x0B,0xD1,0xA8,0x68,0x76,0x1E,0x81,0x19, ++0xAF,0xF2,0xBC,0x00,0x29,0x61,0xFC,0xF7, ++0xFD,0xFA,0xAF,0xF2,0xA8,0x00,0xA9,0x68, ++0x0C,0xE0,0x20,0x09,0x0C,0xD1,0x68,0x68, ++0x76,0x1E,0x81,0x19,0xAF,0xF2,0xA0,0x00, ++0xE9,0x60,0xFC,0xF7,0xEF,0xFA,0xAF,0xF2, ++0x8C,0x00,0x69,0x68,0xFC,0xF7,0xEA,0xFA, ++0x00,0x26,0x64,0x1C,0xE4,0xB2,0x20,0x2C, ++0xFF,0xF4,0x35,0xAF,0x7F,0x1C,0xBF,0xB2, ++0x03,0x2F,0xFF,0xF4,0x23,0xAF,0x00,0x20, ++0x5C,0x46,0xAB,0xF8,0xF4,0x05,0x45,0x98, ++0xFD,0xF7,0x75,0xF9,0x00,0x21,0x01,0xAB, ++0x01,0xEB,0x41,0x00,0x03,0xEB,0xC0,0x00, ++0x42,0x69,0xFA,0xB1,0x40,0x9A,0x4A,0xB1, ++0x00,0x22,0x40,0x92,0xC2,0x68,0x41,0x92, ++0x02,0x69,0x42,0x92,0x42,0x68,0x43,0x92, ++0x82,0x68,0x44,0x92,0xC2,0x68,0x41,0x9D, ++0xAA,0x42,0x00,0xD9,0x41,0x92,0x02,0x69, ++0x42,0x9D,0xAA,0x42,0x00,0xD9,0x42,0x92, ++0x42,0x68,0x43,0x9D,0xAA,0x42,0x00,0xD2, ++0x43,0x92,0x80,0x68,0x44,0x9A,0x90,0x42, ++0x00,0xD2,0x44,0x90,0x49,0x1C,0x89,0xB2, ++0x03,0x29,0xD5,0xD3,0x43,0x99,0x41,0x98, ++0x43,0x9A,0x48,0x40,0x41,0x99,0x00,0xF0, ++0x01,0x00,0x44,0x9B,0x11,0x44,0x44,0x9A, ++0x00,0xEB,0x51,0x01,0x42,0x98,0x50,0x40, ++0x42,0x9A,0x00,0xF0,0x01,0x00,0x1A,0x44, ++0x00,0xEB,0x52,0x00,0x41,0xEA,0x00,0x10, ++0xC5,0xB2,0x46,0x98,0x05,0x43,0xAA,0xF8, ++0x00,0x50,0xA4,0xF8,0xD0,0x55,0xBA,0xF8, ++0x00,0x10,0xAF,0xF2,0x34,0x10,0xFC,0xF7, ++0x89,0xFA,0x05,0x49,0x43,0xF2,0x55,0x00, ++0x00,0xEB,0x05,0x40,0x08,0x60,0x47,0x98, ++0xA4,0xF8,0xE4,0x05,0x48,0x98,0x85,0xE6, ++0x60,0x3E,0x30,0x25,0x4F,0xF0,0x28,0x50, ++0xD0,0xF8,0x6C,0x15,0xC9,0x07,0xFB,0xD0, ++0x01,0x21,0xC0,0xF8,0x70,0x15,0x70,0x47, ++0x60,0x4A,0x00,0x06,0x30,0xB5,0x00,0x0C, ++0x10,0x60,0x00,0x20,0x50,0x60,0x4D,0xF2, ++0xD0,0x11,0x91,0x60,0x03,0x21,0x11,0x62, ++0x47,0x21,0x51,0x62,0x90,0x62,0xD0,0x62, ++0x4F,0xF6,0xFF,0x74,0x14,0x63,0xFE,0x25, ++0xD5,0x67,0x01,0x23,0x93,0x66,0xFF,0xF7, ++0xDD,0xFF,0x4F,0xF4,0x00,0x70,0x10,0x62, ++0x94,0x63,0xD5,0x67,0x93,0x66,0xFF,0xF7, ++0xD5,0xFF,0xFF,0x20,0xD0,0x67,0x10,0x69, ++0x30,0xBD,0xC1,0xB2,0x10,0x22,0x00,0xB5, ++0x42,0xEA,0x01,0x21,0x4B,0x4A,0x11,0x60, ++0xC0,0xF3,0x07,0x20,0x50,0x60,0x03,0x20, ++0x10,0x62,0x47,0x20,0x50,0x62,0x00,0x20, ++0x90,0x62,0xD0,0x62,0x4F,0xF6,0xFF,0x70, ++0x10,0x63,0xFE,0x20,0xD0,0x67,0x01,0x20, ++0x90,0x66,0xFF,0xF7,0xB7,0xFF,0xFF,0x20, ++0xD0,0x67,0x00,0xBD,0x80,0xB2,0x00,0xB5, ++0xFF,0xF7,0xDF,0xFF,0x04,0x20,0xFF,0xF7, ++0xB7,0xFF,0xC0,0x07,0xFA,0xD0,0x5D,0xF8, ++0x04,0xEB,0x08,0x20,0xB0,0xE7,0xC2,0xB2, ++0x15,0x23,0x00,0xB5,0x43,0xEA,0x02,0x23, ++0x36,0x4A,0x13,0x60,0xCB,0xB2,0xC0,0xF3, ++0x07,0x20,0x40,0xEA,0x03,0x20,0x50,0x60, ++0xC1,0xF3,0x07,0x20,0x40,0xF4,0x50,0x40, ++0x90,0x60,0x05,0x20,0x10,0x62,0x47,0x20, ++0x50,0x62,0x00,0x20,0x90,0x62,0xD0,0x62, ++0x4F,0xF6,0xFF,0x70,0x10,0x63,0xFE,0x20, ++0xD0,0x67,0x01,0x20,0x90,0x66,0xFF,0xF7, ++0x85,0xFF,0xFF,0x20,0xD0,0x67,0x00,0xBD, ++0x30,0xB5,0x04,0x46,0x42,0xF2,0x10,0x05, ++0x28,0x46,0xFF,0xF7,0xC7,0xFF,0x06,0x2C, ++0x0A,0xD8,0x23,0x49,0x51,0xF8,0x24,0x40, ++0x64,0xF3,0x5F,0x30,0x01,0x46,0x28,0x46, ++0xFF,0xF7,0xC9,0xFF,0x20,0x46,0x30,0xBD, ++0x1E,0x48,0x30,0xBD,0x30,0xB5,0x04,0x46, ++0x42,0xF2,0x12,0x05,0x28,0x46,0xFF,0xF7, ++0xB1,0xFF,0xE1,0x1E,0x4F,0xF6,0x8F,0x72, ++0x07,0x29,0x0D,0xD8,0x10,0x40,0x16,0x49, ++0x1C,0x31,0x01,0xEB,0x84,0x01,0x51,0xF8, ++0x0C,0x4C,0x40,0xEA,0x04,0x11,0x28,0x46, ++0xFF,0xF7,0xAD,0xFF,0x20,0x46,0x30,0xBD, ++0x10,0x40,0x00,0x09,0xA0,0xF5,0x80,0x30, ++0x30,0xBD,0x30,0xB5,0x04,0x46,0x42,0xF2, ++0x12,0x05,0x28,0x46,0xFF,0xF7,0x92,0xFF, ++0x0A,0x2C,0x09,0xD8,0x4E,0xF2,0xFF,0x01, ++0x08,0x40,0x40,0xEA,0x04,0x21,0x28,0x46, ++0xFF,0xF7,0x95,0xFF,0x20,0x46,0x30,0xBD, ++0x00,0xF4,0x60,0x40,0x00,0x0A,0xA0,0xF5, ++0x80,0x30,0x30,0xBD,0x00,0x05,0x00,0x2A, ++0xEC,0xEB,0x03,0x20,0x00,0x00,0xFF,0xFF, ++0x2E,0x49,0x0A,0x88,0x10,0x44,0x80,0xB2, ++0xFF,0x28,0x08,0x80,0x01,0xD3,0xFF,0x38, ++0x08,0x80,0x48,0x88,0x0A,0x88,0x10,0x44, ++0x80,0xB2,0xFF,0x28,0x48,0x80,0x01,0xD3, ++0xFF,0x38,0x48,0x80,0x70,0x47,0x25,0x48, ++0x41,0x88,0x00,0x88,0x01,0x43,0x01,0xD1, ++0x01,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0x20,0x49,0x00,0x20,0x08,0x80,0x48,0x80, ++0x70,0x47,0xF0,0xB5,0x06,0x46,0x0F,0x46, ++0x15,0x46,0xFF,0xF7,0xF5,0xFF,0x00,0x24, ++0x03,0xE0,0x28,0x5D,0xFF,0xF7,0xD4,0xFF, ++0x64,0x1C,0x9C,0x42,0xF9,0xD3,0x17,0x49, ++0x48,0x88,0x09,0x88,0xC0,0xB2,0xC0,0xF5, ++0xFF,0x72,0x51,0x1A,0x31,0x70,0x38,0x70, ++0xF0,0xBD,0x2D,0xE9,0xF8,0x43,0x00,0x26, ++0x80,0x46,0x89,0x46,0x35,0x46,0x6F,0x46, ++0x34,0x46,0x0C,0xE0,0x18,0xF8,0x04,0x00, ++0xFF,0x21,0x30,0x44,0x08,0xF0,0xD8,0xE8, ++0x68,0x18,0x0E,0x46,0xFF,0x21,0x08,0xF0, ++0xD4,0xE8,0x64,0x1C,0x0D,0x46,0x4C,0x45, ++0xF0,0xD3,0x70,0x19,0xFF,0x21,0x08,0xF0, ++0xCC,0xE8,0xC1,0xF1,0xFF,0x00,0x38,0x70, ++0x7D,0x70,0xBD,0xF8,0x00,0x00,0xBD,0xE8, ++0xF8,0x83,0x00,0x00,0xCC,0x04,0x03,0x20, ++0x00,0x22,0x01,0x28,0x0B,0xD0,0x02,0x28, ++0x0C,0xD0,0x03,0x28,0x12,0xD0,0x04,0x28, ++0x02,0xD1,0x01,0x22,0x81,0xF8,0x2E,0x20, ++0x81,0xF8,0x27,0x00,0x70,0x47,0x81,0xF8, ++0x21,0x20,0xF9,0xE7,0x21,0x31,0x8A,0x70, ++0xCA,0x70,0x4A,0x70,0x0A,0x70,0x4A,0x73, ++0x21,0x39,0xF1,0xE7,0x81,0xF8,0x25,0x20, ++0xEE,0xE7,0x70,0x47,0x90,0xF8,0x27,0x00, ++0x04,0x28,0x01,0xD1,0x01,0x20,0x70,0x47, ++0x00,0x20,0x70,0x47,0x00,0xEB,0x80,0x00, ++0x70,0xB5,0x01,0xEB,0xC0,0x05,0x0C,0x46, ++0x95,0xF8,0x53,0x00,0x08,0xB9,0x24,0x20, ++0x07,0xE0,0x95,0xF8,0x53,0x00,0x00,0xF0, ++0xA9,0xFC,0x95,0xF8,0x54,0x00,0x10,0xB1, ++0x2C,0x20,0x20,0x21,0x01,0xE0,0x24,0x20, ++0x10,0x21,0x0D,0x4A,0x10,0x44,0x03,0x78, ++0x0B,0x43,0x03,0x70,0x95,0xF8,0x54,0x00, ++0x40,0xB1,0x92,0xF8,0x2C,0x00,0x80,0x06, ++0x0C,0xD5,0x94,0xF8,0x2E,0x00,0x01,0x28, ++0xF7,0xD0,0x07,0xE0,0x92,0xF8,0x24,0x00, ++0xC0,0x06,0x03,0xD5,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF7,0xD0,0x01,0x20,0x70,0xBD, ++0x00,0x40,0x00,0x25,0xF9,0x49,0x00,0x20, ++0x08,0x70,0x70,0x47,0xF7,0x48,0x00,0x78, ++0x70,0x47,0x70,0xB5,0x05,0x46,0x08,0x46, ++0xF5,0x49,0x1C,0x46,0x01,0x60,0x69,0x68, ++0x41,0x60,0x99,0x6B,0x81,0x60,0x02,0x73, ++0xD9,0x68,0x05,0xF0,0xAE,0xFD,0xE0,0x68, ++0x0D,0x21,0x22,0x46,0x00,0xF0,0xEC,0xFD, ++0xBD,0xE8,0x70,0x40,0x00,0xF0,0x48,0xBE, ++0x30,0xB5,0x05,0x46,0x89,0xB0,0x0C,0x46, ++0x24,0x22,0xEA,0xA1,0x68,0x46,0x07,0xF0, ++0x56,0xE8,0x24,0x20,0xE0,0x63,0x80,0x20, ++0x84,0xF8,0x34,0x00,0xA8,0x68,0x24,0x28, ++0x02,0xD2,0x4F,0xF0,0xFF,0x30,0x00,0xE0, ++0x24,0x38,0xA0,0x63,0x24,0x21,0x22,0x46, ++0x68,0x46,0x00,0xF0,0xCD,0xFD,0x09,0xB0, ++0x30,0xBD,0x30,0xB5,0x05,0x46,0x85,0xB0, ++0x0C,0x46,0x14,0x22,0xE4,0xA1,0x68,0x46, ++0x07,0xF0,0x38,0xE8,0x30,0x34,0x60,0x78, ++0x8D,0xF8,0x02,0x00,0xA0,0x78,0x8D,0xF8, ++0x0C,0x00,0xE0,0x78,0x8D,0xF8,0x0D,0x00, ++0x12,0x20,0xE0,0x60,0x80,0x20,0x20,0x71, ++0x30,0x3C,0xA8,0x68,0x12,0x28,0x02,0xD2, ++0x4F,0xF0,0xFF,0x30,0x00,0xE0,0x12,0x38, ++0xA0,0x63,0x12,0x21,0x22,0x46,0x68,0x46, ++0x00,0xF0,0xA6,0xFD,0x05,0xB0,0x30,0xBD, ++0x7C,0xB5,0x14,0x46,0x1A,0x46,0x00,0x23, ++0x6D,0x46,0x1E,0x46,0x49,0x1E,0x48,0xC5, ++0x0B,0x0A,0x8D,0xF8,0x03,0x10,0x8D,0xF8, ++0x02,0x30,0x0B,0x0C,0x09,0x0E,0x8D,0xF8, ++0x01,0x30,0x8D,0xF8,0x00,0x10,0x21,0x0A, ++0x8D,0xF8,0x07,0x40,0x8D,0xF8,0x06,0x10, ++0x21,0x0C,0x8D,0xF8,0x05,0x10,0x21,0x0E, ++0x8D,0xF8,0x04,0x10,0x08,0x21,0xD1,0x63, ++0x80,0x21,0x82,0xF8,0x34,0x10,0x80,0x68, ++0x08,0x28,0x02,0xD2,0x4F,0xF0,0xFF,0x30, ++0x00,0xE0,0x08,0x38,0x90,0x63,0x08,0x21, ++0x68,0x46,0x00,0xF0,0x75,0xFD,0x7C,0xBD, ++0x00,0x22,0xCA,0x63,0x81,0xF8,0x34,0x20, ++0x8A,0x63,0x00,0x7D,0x80,0x07,0x03,0xD5, ++0x01,0x20,0x81,0xF8,0x35,0x00,0x01,0xE0, ++0x81,0xF8,0x35,0x20,0x00,0x20,0x70,0x47, ++0x00,0x20,0x02,0x46,0xC8,0x63,0x81,0xF8, ++0x34,0x00,0x88,0x63,0x91,0xF8,0x35,0x30, ++0x00,0x2B,0x06,0xD0,0x01,0x20,0x02,0x23, ++0x01,0xF8,0x31,0x3F,0x3A,0x23,0x4B,0x70, ++0x8A,0x70,0x70,0x47,0x00,0x20,0xC8,0x63, ++0x81,0xF8,0x34,0x00,0x88,0x63,0x70,0x47, ++0xAC,0xA2,0x08,0xB5,0x12,0x68,0x00,0x92, ++0x04,0x22,0xCA,0x63,0x80,0x22,0x81,0xF8, ++0x34,0x20,0x80,0x68,0x04,0x28,0x02,0xD2, ++0x4F,0xF0,0xFF,0x30,0x00,0xE0,0x00,0x1F, ++0x88,0x63,0x0A,0x46,0x04,0x21,0x68,0x46, ++0x00,0xF0,0x36,0xFD,0x08,0xBD,0x2D,0xE9, ++0xFC,0x5F,0x04,0x46,0x00,0x20,0x0E,0x46, ++0x01,0x90,0x80,0x46,0x00,0x90,0x21,0x7C, ++0x89,0x06,0x11,0xD5,0x61,0x7D,0x8D,0xF8, ++0x00,0x10,0x21,0x7D,0x8D,0xF8,0x01,0x10, ++0xE1,0x7C,0x8D,0xF8,0x02,0x10,0xA1,0x7C, ++0x8D,0xF8,0x03,0x10,0xE1,0x7D,0x8D,0xF8, ++0x05,0x10,0x21,0x7E,0x8D,0xF8,0x04,0x10, ++0xBD,0xF8,0x04,0x10,0x49,0x02,0xF1,0x63, ++0xF5,0x6B,0x80,0x21,0x86,0xF8,0x34,0x10, ++0xA1,0x68,0xF2,0x6B,0x91,0x42,0x02,0xD2, ++0x4F,0xF0,0xFF,0x31,0x01,0xE0,0xF2,0x6B, ++0x89,0x1A,0xB1,0x63,0x4F,0xF4,0x00,0x59, ++0xDF,0xF8,0x24,0xA2,0xD6,0xF8,0x38,0xB1, ++0x1A,0xE0,0x4D,0x45,0x4F,0x46,0x00,0xD8, ++0x2F,0x46,0x60,0x7B,0xB1,0x78,0x88,0x42, ++0x08,0xD1,0xDA,0xF8,0x00,0x00,0x00,0x9A, ++0x79,0x0A,0x03,0x68,0x58,0x46,0x98,0x47, ++0x00,0xF0,0xFF,0x08,0x32,0x46,0x39,0x46, ++0x58,0x46,0x00,0xF0,0xB1,0xFC,0x00,0x99, ++0xED,0x1B,0x01,0xEB,0x57,0x21,0x00,0x91, ++0x00,0x2D,0xE2,0xD1,0x61,0x7B,0xB2,0x78, ++0x91,0x42,0x03,0xD1,0xB8,0xF1,0x00,0x0F, ++0x00,0xD0,0xFC,0x20,0xBD,0xE8,0xFC,0x9F, ++0x2D,0xE9,0xFE,0x4F,0x4F,0xF0,0x00,0x08, ++0x04,0x46,0x0E,0x46,0xCD,0xF8,0x04,0x80, ++0xC1,0x46,0xCD,0xF8,0x00,0x80,0x40,0x46, ++0x21,0x7C,0x89,0x06,0x11,0xD5,0x61,0x7D, ++0x8D,0xF8,0x00,0x10,0x21,0x7D,0x8D,0xF8, ++0x01,0x10,0xE1,0x7C,0x8D,0xF8,0x02,0x10, ++0xA1,0x7C,0x8D,0xF8,0x03,0x10,0xE1,0x7D, ++0x8D,0xF8,0x05,0x10,0x21,0x7E,0x8D,0xF8, ++0x04,0x10,0xBD,0xF8,0x04,0x10,0x49,0x02, ++0xF1,0x63,0xF5,0x6B,0x86,0xF8,0x34,0x00, ++0xA0,0x68,0xF1,0x6B,0x88,0x42,0x02,0xD2, ++0x4F,0xF0,0xFF,0x30,0x01,0xE0,0xF1,0x6B, ++0x40,0x1A,0xB0,0x63,0x4F,0xF4,0x00,0x5B, ++0xD6,0xF8,0x38,0x01,0xDF,0xF8,0x60,0xA1, ++0x02,0x90,0x1B,0xE0,0x5D,0x45,0x5F,0x46, ++0x00,0xD8,0x2F,0x46,0x02,0x98,0x32,0x46, ++0x39,0x46,0x00,0xF0,0xD3,0xFC,0xB1,0x78, ++0x80,0x46,0x60,0x7B,0x88,0x42,0x08,0xD1, ++0xDA,0xF8,0x00,0x00,0x00,0x9A,0x79,0x0A, ++0x43,0x68,0x02,0x98,0x98,0x47,0x00,0xF0, ++0xFF,0x09,0x00,0x98,0xED,0x1B,0x00,0xEB, ++0x57,0x20,0x00,0x90,0x00,0x2D,0xE1,0xD1, ++0x60,0x7B,0xB1,0x78,0x88,0x42,0x04,0xD1, ++0xB9,0xF1,0x00,0x0F,0x01,0xD0,0x4F,0xF0, ++0xFC,0x08,0x40,0x46,0xBD,0xE8,0xFE,0x8F, ++0x30,0xB5,0x04,0x46,0x40,0x7F,0x8D,0xB0, ++0x01,0x28,0x59,0xD1,0x00,0x20,0x00,0xF0, ++0xEF,0xFA,0x00,0xEB,0x80,0x00,0x04,0xEB, ++0xC0,0x05,0x95,0xF8,0x53,0x00,0x00,0xF0, ++0xE1,0xFA,0x00,0x20,0x60,0x77,0x60,0x69, ++0x05,0xA9,0x05,0xF0,0xF2,0xFB,0xE8,0x6C, ++0x1F,0x28,0x1F,0xD1,0x05,0x98,0x35,0x49, ++0x88,0x42,0x1B,0xD1,0x9D,0xF8,0x21,0x00, ++0x01,0x09,0x17,0xD1,0x21,0x78,0x88,0x42, ++0x14,0xD8,0x07,0x98,0xA0,0x63,0x9D,0xF8, ++0x24,0x00,0x03,0x28,0x15,0xD1,0x21,0x46, ++0x05,0xA8,0xFF,0xF7,0x7A,0xFE,0x2B,0xE0, ++0x9D,0xF8,0x20,0x00,0x00,0x06,0x20,0x46, ++0x08,0xD5,0x05,0xF0,0x13,0xFC,0x02,0x22, ++0x23,0x46,0x50,0xE0,0x07,0x98,0x00,0x28, ++0xF9,0xD0,0xF1,0xE7,0x05,0xF0,0x14,0xFC, ++0xF5,0xE7,0x12,0x28,0x04,0xD1,0x21,0x46, ++0x05,0xA8,0xFF,0xF7,0x45,0xFE,0x13,0xE0, ++0x1F,0x49,0xE0,0x28,0x05,0xD3,0x22,0x46, ++0x05,0xA8,0x0B,0x68,0x01,0xA9,0x98,0x47, ++0x0A,0xE0,0x4B,0x68,0x22,0x46,0x01,0xA9, ++0x05,0xA8,0x98,0x47,0x9D,0xF8,0x24,0x10, ++0x11,0xB9,0x04,0x4A,0x01,0x21,0x11,0x70, ++0x23,0x46,0x10,0xB9,0x00,0x22,0x2A,0xE0, ++0x2D,0xE0,0x27,0xE0,0xD0,0x04,0x03,0x20, ++0x55,0x53,0x42,0x53,0x00,0x80,0x00,0x00, ++0x1F,0x00,0x00,0x00,0x47,0x43,0x52,0x45, ++0x41,0x44,0x45,0x52,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x0A, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00, ++0x7C,0xD4,0x02,0x20,0x55,0x53,0x42,0x43, ++0x84,0xD4,0x02,0x20,0x01,0x22,0x01,0xA9, ++0x05,0xA8,0xFF,0xF7,0xE6,0xFD,0x0D,0xB0, ++0x30,0xBD,0x2D,0xE9,0xF0,0x47,0x0D,0x46, ++0x40,0x7B,0x14,0x46,0x91,0x78,0x4F,0xF0, ++0x00,0x08,0x01,0x27,0x4F,0xF0,0x02,0x09, ++0x88,0x42,0x4F,0xF0,0x3A,0x0A,0x46,0x46, ++0x19,0xD1,0xF9,0x48,0x00,0x68,0xC0,0x68, ++0x80,0x47,0x01,0x28,0x09,0xD0,0x02,0x28, ++0x11,0xD1,0x06,0x20,0x2F,0x73,0x04,0xF8, ++0x31,0x0F,0x28,0x20,0x60,0x70,0xA6,0x70, ++0x06,0xE0,0x2E,0x73,0x04,0xF8,0x31,0x6F, ++0x66,0x70,0xA6,0x70,0x4F,0xF0,0x01,0x08, ++0x40,0x46,0xBD,0xE8,0xF0,0x87,0x2F,0x73, ++0x04,0xF8,0x31,0x9F,0x50,0x46,0xED,0xE7, ++0x00,0x22,0xCA,0x63,0x81,0xF8,0x34,0x20, ++0x8A,0x63,0x00,0x7D,0x00,0x28,0x06,0xD0, ++0x01,0x20,0x05,0x23,0x01,0xF8,0x31,0x3F, ++0x24,0x23,0x4B,0x70,0x8A,0x70,0x70,0x47, ++0x2D,0xE9,0xF0,0x41,0x04,0x46,0xC0,0x7D, ++0xAD,0xF6,0x08,0x0D,0xDE,0x4E,0x0D,0x46, ++0xE8,0xB1,0x01,0x28,0x35,0xD1,0x20,0x7E, ++0x2A,0x46,0x8D,0xF8,0x05,0x08,0x60,0x7E, ++0x8D,0xF8,0x04,0x08,0xD5,0xF8,0x38,0x81, ++0xBD,0xF8,0x04,0x18,0x40,0x46,0x00,0xF0, ++0xF6,0xFB,0xA9,0x78,0x07,0x46,0x60,0x7B, ++0x88,0x42,0x03,0xD1,0x30,0x68,0x41,0x6A, ++0x40,0x46,0x88,0x47,0x38,0x46,0x0D,0xF6, ++0x08,0x0D,0xBD,0xE8,0xF0,0x81,0x4F,0xF4, ++0x00,0x61,0x01,0xA8,0x06,0xF0,0xC4,0xED, ++0x20,0x7E,0x8D,0xF8,0x05,0x08,0x60,0x7E, ++0x8D,0xF8,0x04,0x08,0x60,0x7B,0xA9,0x78, ++0x88,0x42,0x03,0xD1,0x30,0x68,0x01,0x6A, ++0x01,0xA8,0x88,0x47,0xBD,0xF8,0x04,0x18, ++0x2A,0x46,0x01,0xA8,0x00,0xF0,0x64,0xFB, ++0xE1,0xE7,0x00,0x20,0xDF,0xE7,0x38,0xB5, ++0xEC,0x24,0x00,0x21,0x00,0x91,0xC1,0x7C, ++0x8D,0xF8,0x00,0x10,0x81,0x7C,0x8D,0xF8, ++0x01,0x10,0x40,0x7C,0x8D,0xF8,0x02,0x00, ++0xB9,0x48,0x00,0x68,0x81,0x69,0x00,0x98, ++0x88,0x47,0x01,0x28,0x00,0xD1,0x00,0x24, ++0x20,0x46,0x38,0xBD,0x2D,0xE9,0xFC,0x41, ++0x0E,0x46,0x00,0x21,0xEC,0x25,0x01,0x91, ++0x41,0x7D,0x8D,0xF8,0x00,0x10,0x01,0x7D, ++0x8D,0xF8,0x01,0x10,0xC1,0x7C,0x8D,0xF8, ++0x02,0x10,0x81,0x7C,0x8D,0xF8,0x03,0x10, ++0x01,0x7E,0x8D,0xF8,0x05,0x10,0x40,0x7E, ++0x8D,0xF8,0x04,0x00,0xA8,0x48,0xD6,0xF8, ++0x38,0x81,0xBD,0xF8,0x04,0x20,0x00,0x68, ++0x41,0x46,0x14,0x46,0x03,0x69,0x00,0x98, ++0x98,0x47,0xB6,0xF8,0x6A,0x10,0x20,0x46, ++0x07,0xF0,0x82,0xED,0x60,0x1A,0x0F,0x46, ++0x04,0x04,0x24,0x0C,0x01,0x94,0x0D,0xD0, ++0x32,0x46,0x21,0x46,0x40,0x46,0x00,0xF0, ++0xDF,0xFA,0x05,0x00,0x06,0xD1,0x2F,0xB1, ++0x08,0xEB,0x04,0x00,0x32,0x46,0x39,0x46, ++0x00,0xF0,0x0E,0xFB,0x28,0x46,0xBD,0xE8, ++0xFC,0x81,0x2D,0xE9,0xFC,0x47,0x04,0x46, ++0x00,0x20,0x0F,0x46,0x01,0x90,0x4F,0xF0, ++0xEC,0x09,0x60,0x7D,0x8D,0xF8,0x00,0x00, ++0x20,0x7D,0x8D,0xF8,0x01,0x00,0xE0,0x7C, ++0x8D,0xF8,0x02,0x00,0xA0,0x7C,0x8D,0xF8, ++0x03,0x00,0x20,0x7E,0x8D,0xF8,0x05,0x00, ++0x60,0x7E,0x8D,0xF8,0x04,0x00,0xB1,0xF8, ++0x92,0x10,0xBD,0xF8,0x04,0x00,0x06,0x46, ++0x07,0xF0,0x4A,0xED,0x70,0x1A,0x0D,0x46, ++0x06,0x04,0x36,0x0C,0x01,0x96,0xD7,0xF8, ++0x38,0x81,0x05,0xD0,0x3A,0x46,0x31,0x46, ++0x40,0x46,0x00,0xF0,0x1B,0xFB,0x81,0x46, ++0x2D,0xB1,0x08,0xEB,0x06,0x00,0x3A,0x46, ++0x29,0x46,0x00,0xF0,0x40,0xFB,0x70,0x19, ++0xE3,0x7D,0x41,0x46,0x82,0xB2,0x78,0x48, ++0x00,0x68,0x44,0x69,0x00,0x98,0xA0,0x47, ++0x48,0x46,0xBD,0xE8,0xFC,0x87,0x82,0xB0, ++0x00,0x22,0x01,0x92,0x02,0x7E,0x8D,0xF8, ++0x05,0x20,0x0A,0x46,0x40,0x7E,0x8D,0xF8, ++0x04,0x00,0xD1,0xF8,0x38,0x01,0xBD,0xF8, ++0x04,0x10,0x02,0xB0,0x00,0xF0,0x23,0xBB, ++0x6B,0x49,0x10,0xB5,0x40,0x7C,0x09,0x68, ++0xC9,0x69,0x88,0x47,0x00,0x20,0x10,0xBD, ++0x7C,0xB5,0x05,0x46,0xD1,0xF8,0x3C,0x41, ++0x0E,0x46,0x69,0x7E,0x00,0x20,0x8D,0xF8, ++0x00,0x10,0x29,0x7E,0x8D,0xF8,0x01,0x10, ++0xE9,0x7D,0x8D,0xF8,0x02,0x10,0xA9,0x7D, ++0x8D,0xF8,0x03,0x10,0x69,0x7C,0x07,0x29, ++0x40,0xD2,0xDF,0xE8,0x01,0xF0,0x20,0x04, ++0x1B,0x38,0x04,0x3F,0x20,0x00,0xA0,0x68, ++0xD8,0xB9,0x60,0x68,0xC8,0xB9,0x00,0x98, ++0x32,0x46,0x60,0x60,0x00,0x98,0x00,0xF2, ++0xFF,0x10,0x6F,0xF3,0x08,0x00,0x00,0x90, ++0x20,0x6A,0x00,0x99,0x00,0xF0,0xC2,0xFA, ++0x69,0x7C,0x04,0x29,0x26,0xD1,0x01,0x21, ++0x21,0x77,0x23,0xE0,0x00,0x99,0x32,0x46, ++0x04,0xF1,0x08,0x00,0x1C,0xE0,0x60,0x68, ++0x08,0xB1,0xFC,0x20,0x7C,0xBD,0xE1,0x68, ++0x32,0x46,0x20,0x6A,0x08,0x44,0x00,0x99, ++0x00,0xF0,0x6E,0xFA,0xE1,0x68,0x00,0x9A, ++0x11,0x44,0xE1,0x60,0xA1,0x68,0x00,0x9A, ++0x91,0x42,0x01,0xD9,0x89,0x1A,0x00,0xE0, ++0x00,0x21,0xA1,0x60,0x06,0xE0,0x60,0x8B, ++0x32,0x46,0x00,0x99,0x01,0x90,0x01,0xA8, ++0x00,0xF0,0x5A,0xFA,0xB1,0x6B,0x00,0x9A, ++0x89,0x1A,0xB1,0x63,0xB1,0x6B,0x00,0x29, ++0xDC,0xDA,0x4F,0xF0,0xFF,0x31,0xB1,0x63, ++0x7C,0xBD,0x70,0xB5,0x00,0x25,0x01,0x7C, ++0x14,0x46,0xE2,0x29,0x03,0xD1,0x21,0x46, ++0xFF,0xF7,0xA2,0xFE,0x20,0xE0,0xE3,0x29, ++0x02,0xD1,0xFF,0xF7,0xE0,0xFE,0x1B,0xE0, ++0xE4,0x29,0x03,0xD1,0x21,0x46,0xFF,0xF7, ++0xF1,0xFE,0x15,0xE0,0xE5,0x29,0x03,0xD1, ++0x21,0x46,0xFF,0xF7,0x2A,0xFF,0x0F,0xE0, ++0xE6,0x29,0x03,0xD1,0x21,0x46,0xFF,0xF7, ++0x66,0xFF,0x09,0xE0,0xE7,0x29,0x02,0xD1, ++0xFF,0xF7,0x72,0xFF,0x04,0xE0,0xE8,0x29, ++0x04,0xD1,0x21,0x46,0xFF,0xF7,0x74,0xFF, ++0x05,0x46,0x11,0xE0,0x81,0x68,0x41,0xB1, ++0x00,0x7B,0x00,0x06,0x20,0x46,0x02,0xD5, ++0x05,0xF0,0xF0,0xF9,0x01,0xE0,0x05,0xF0, ++0xF7,0xF9,0x05,0x20,0x04,0xF8,0x31,0x0F, ++0x24,0x20,0x60,0x70,0x00,0x20,0xA0,0x70, ++0x28,0x46,0x70,0xBD,0x03,0x46,0x10,0x46, ++0x01,0x22,0x10,0xB5,0x0A,0x73,0x02,0x21, ++0x80,0xF8,0x31,0x10,0x3A,0x21,0x80,0xF8, ++0x32,0x10,0x00,0x21,0x80,0xF8,0x33,0x10, ++0x99,0x68,0x39,0xB1,0x19,0x7B,0x09,0x06, ++0x02,0xD5,0x05,0xF0,0xCF,0xF9,0x01,0xE0, ++0x05,0xF0,0xD6,0xF9,0xEC,0x20,0x10,0xBD, ++0x2D,0xE9,0xF0,0x41,0x00,0x27,0x04,0x7C, ++0x05,0x46,0x16,0x46,0xFF,0xF7,0x09,0xFE, ++0x78,0xB9,0xA8,0x68,0xEC,0x27,0x00,0x28, ++0x60,0xD0,0x28,0x7B,0x00,0x06,0x30,0x46, ++0x04,0xD5,0x05,0xF0,0xB7,0xF9,0x59,0xE0, ++0x7C,0xD4,0x02,0x20,0x05,0xF0,0xBC,0xF9, ++0x54,0xE0,0x25,0x2C,0x0F,0xD1,0x68,0x7B, ++0xB1,0x78,0x88,0x42,0x4E,0xD1,0x28,0x48, ++0x00,0x68,0x80,0x68,0x80,0x47,0x01,0x46, ++0x33,0x46,0x4F,0xF4,0x00,0x72,0x28,0x46, ++0xFF,0xF7,0x26,0xFC,0x2E,0xE0,0x1B,0x2C, ++0x04,0xD1,0x31,0x46,0x28,0x46,0xFF,0xF7, ++0x4F,0xFC,0x27,0xE0,0x24,0xB9,0x31,0x46, ++0x28,0x46,0xFF,0xF7,0x59,0xFC,0x21,0xE0, ++0x2F,0x2C,0x04,0xD1,0x31,0x46,0x28,0x46, ++0xFF,0xF7,0x64,0xFC,0x1A,0xE0,0x1A,0x2C, ++0x04,0xD1,0x31,0x46,0x28,0x46,0xFF,0xF7, ++0x63,0xFC,0x13,0xE0,0x28,0x2C,0x04,0xD1, ++0x31,0x46,0x28,0x46,0xFF,0xF7,0x73,0xFC, ++0x0C,0xE0,0x2A,0x2C,0x04,0xD1,0x31,0x46, ++0x28,0x46,0xFF,0xF7,0xC9,0xFC,0x05,0xE0, ++0x1E,0x2C,0x05,0xD1,0x31,0x46,0x28,0x46, ++0xFF,0xF7,0xE6,0xFD,0x07,0x46,0x11,0xE0, ++0xA8,0x68,0x40,0xB1,0x28,0x7B,0x00,0x06, ++0x30,0x46,0x02,0xD5,0x05,0xF0,0x66,0xF9, ++0x01,0xE0,0x05,0xF0,0x6D,0xF9,0x05,0x20, ++0x06,0xF8,0x31,0x0F,0x24,0x20,0x70,0x70, ++0x00,0x20,0xB0,0x70,0x38,0x46,0x04,0xE6, ++0x7C,0xD4,0x02,0x20,0xFE,0x4A,0x11,0x7F, ++0x81,0x42,0x00,0xD0,0x10,0x77,0x70,0x47, ++0x01,0x46,0x00,0x20,0x02,0x29,0x02,0xD0, ++0x01,0x29,0x01,0xD1,0x01,0x20,0x70,0x47, ++0x00,0x29,0xFC,0xD1,0x02,0x20,0x70,0x47, ++0xF5,0x49,0xFF,0x20,0xF7,0x22,0x4A,0x75, ++0x88,0x81,0x08,0x82,0x70,0x47,0x01,0xEB, ++0x81,0x01,0x02,0xEB,0xC1,0x02,0x91,0x6C, ++0xD3,0x6C,0xC9,0x1A,0xB2,0xF8,0x44,0x30, ++0x99,0x42,0x03,0xD2,0x91,0x6C,0xD3,0x6C, ++0xC9,0x1A,0x01,0xE0,0xB2,0xF8,0x44,0x10, ++0x00,0x29,0x15,0xDD,0x44,0x32,0x93,0x68, ++0x18,0x44,0x93,0x68,0x0B,0x44,0x93,0x60, ++0x13,0x88,0x5B,0x1A,0x13,0x80,0xD2,0x7B, ++0xE3,0x4B,0x40,0x33,0x03,0xEB,0xC2,0x02, ++0xC3,0x07,0x0A,0xD0,0x13,0x78,0x00,0xF8, ++0x01,0x3B,0x49,0x1E,0x00,0x29,0xF9,0xDC, ++0x70,0x47,0x13,0x88,0x20,0xF8,0x02,0x3B, ++0x89,0x1E,0x02,0x29,0x05,0xDB,0xC3,0x07, ++0xF7,0xD0,0x13,0x78,0x00,0xF8,0x01,0x3B, ++0x49,0x1E,0x00,0x29,0xF9,0xDC,0x70,0x47, ++0xD5,0x49,0x49,0x78,0x01,0x76,0x70,0x47, ++0xD3,0x49,0x91,0xF8,0xC0,0x10,0x80,0xF8, ++0x2A,0x10,0x70,0x47,0x18,0xB9,0x00,0x20, ++0x81,0xF8,0x2A,0x00,0x04,0xE0,0x91,0xF8, ++0x2A,0x20,0x82,0x43,0x81,0xF8,0x2A,0x20, ++0x11,0xF8,0x2A,0x2F,0xCA,0x48,0xC0,0x30, ++0x02,0x70,0x00,0x78,0x08,0x70,0x70,0x47, ++0xC8,0x48,0x00,0x21,0x01,0x81,0x01,0x88, ++0x21,0xF0,0x0F,0x01,0x01,0x80,0x70,0x47, ++0x10,0xB9,0x60,0x20,0x08,0x76,0x02,0xE0, ++0x0A,0x7E,0x82,0x43,0x0A,0x76,0x0A,0x7E, ++0xBF,0x48,0x42,0x70,0x40,0x78,0x08,0x76, ++0x70,0x47,0x11,0xF8,0x2A,0x2F,0x02,0x43, ++0x0A,0x70,0x0A,0x78,0xBB,0x48,0x4C,0x38, ++0x02,0x70,0x00,0x78,0x08,0x70,0x70,0x47, ++0xB8,0x48,0x4C,0x38,0x00,0x78,0xC0,0xF3, ++0xC1,0x00,0x00,0x28,0x07,0xD0,0x01,0x28, ++0x05,0xD0,0x02,0x28,0x03,0xD0,0x03,0x28, ++0x01,0xD0,0x4F,0xF0,0xFF,0x30,0x70,0x47, ++0x00,0xEB,0x80,0x00,0x30,0xB5,0x01,0xEB, ++0xC0,0x03,0x52,0x33,0x0C,0x46,0x58,0x78, ++0xFF,0xF7,0x58,0xFF,0x18,0x78,0x59,0x78, ++0x00,0xF0,0x03,0x00,0xA8,0x4A,0x60,0xF3, ++0x1F,0x11,0x90,0x8D,0x9D,0x78,0x52,0x3B, ++0x01,0x2D,0x14,0xD1,0x82,0xF8,0x38,0x10, ++0xB3,0xF8,0x42,0x10,0x11,0x85,0xC1,0x07, ++0x03,0xD0,0x11,0x8E,0xA3,0xF8,0x44,0x10, ++0x00,0xE0,0x80,0x20,0x93,0xF8,0x52,0x10, ++0x03,0x29,0x01,0xD1,0x40,0xF4,0x80,0x50, ++0x90,0x85,0x00,0x20,0x12,0xE0,0x94,0xF8, ++0x30,0x00,0x05,0x28,0x01,0xD1,0x82,0xF8, ++0x34,0x10,0x33,0xF8,0x42,0x0F,0x10,0x84, ++0x08,0x20,0x90,0x84,0x18,0x7C,0x01,0x28, ++0x02,0xD1,0x46,0xF2,0x40,0x00,0x01,0xE0, ++0x4F,0xF4,0x01,0x50,0x90,0x84,0x30,0xBD, ++0x70,0xB4,0x0D,0x46,0x00,0xEB,0x80,0x04, ++0xDD,0xE9,0x03,0x61,0x01,0xEB,0xC4,0x04, ++0x40,0x34,0x66,0x80,0x25,0x75,0x00,0x25, ++0xA5,0x80,0xA5,0x60,0xE5,0x60,0xA2,0x74, ++0xC2,0xB2,0xE2,0x74,0x65,0x75,0xE5,0x61, ++0x25,0x62,0x02,0x26,0xA6,0x75,0xE5,0x75, ++0x23,0x76,0x00,0x28,0x02,0xD0,0x10,0x46, ++0x70,0xBC,0xA1,0xE7,0x70,0xBC,0x70,0x47, ++0x7F,0x49,0x4A,0x78,0x02,0x76,0x91,0xF8, ++0xC0,0x10,0x80,0xF8,0x2A,0x10,0x70,0x47, ++0x01,0xEB,0x81,0x01,0x30,0xB5,0x02,0xEB, ++0xC1,0x02,0xB2,0xF8,0x42,0x10,0x49,0xB1, ++0x91,0x6C,0xD3,0x6C,0xC9,0x1A,0xB2,0xF8, ++0x42,0x30,0x99,0x42,0x02,0xD9,0xB2,0xF8, ++0x42,0x10,0x02,0xE0,0x91,0x6C,0xD3,0x6C, ++0xC9,0x1A,0x01,0x23,0x11,0xB9,0x82,0xF8, ++0x55,0x30,0x30,0xBD,0xD4,0x6C,0x20,0x44, ++0xD4,0x6C,0x0C,0x44,0xD4,0x64,0xD4,0x6C, ++0x95,0x6C,0xAC,0x42,0x01,0xD1,0x82,0xF8, ++0x55,0x30,0x92,0xF8,0x53,0x20,0x68,0x4B, ++0x40,0x33,0x00,0x29,0x03,0xEB,0xC2,0x02, ++0x0B,0xDD,0xC3,0x07,0x09,0xD0,0x10,0xF8, ++0x01,0x3B,0x13,0x70,0x49,0x1E,0xFA,0xD1, ++0x30,0xBD,0x30,0xF8,0x02,0x3B,0x13,0x80, ++0x89,0x1E,0x02,0x29,0x05,0xDB,0xC3,0x07, ++0xF7,0xD0,0x10,0xF8,0x01,0x3B,0x13,0x70, ++0x49,0x1E,0x00,0x29,0xF9,0xDC,0x30,0xBD, ++0x70,0xB5,0x14,0x46,0x00,0x23,0xFF,0x22, ++0x60,0x34,0x04,0xF8,0x45,0x2C,0xA3,0x77, ++0x21,0x61,0x63,0x61,0x63,0x77,0x60,0x62, ++0xE0,0x7E,0x00,0xF0,0x0F,0x00,0x40,0xF0, ++0x20,0x00,0x04,0xF8,0x44,0x0C,0xE0,0x7E, ++0x60,0x3C,0xFF,0xF7,0x9F,0xFE,0x4E,0x4D, ++0x95,0xF8,0x24,0x00,0x81,0x06,0x00,0xD5, ++0x40,0x23,0x80,0x07,0x01,0xD5,0x58,0x06, ++0x05,0xD5,0x00,0x22,0x0E,0x21,0x01,0x20, ++0x23,0x46,0x05,0xF0,0x41,0xF8,0xE0,0x7E, ++0xFF,0x28,0x03,0xD1,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF8,0xD0,0x95,0xF8,0x24,0x00, ++0x80,0x07,0x03,0xD5,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF7,0xD0,0x00,0x20,0x70,0xBD, ++0xF0,0xB5,0x14,0x46,0x00,0x25,0xFF,0x22, ++0x60,0x34,0x04,0xF8,0x47,0x2C,0x2E,0x46, ++0xA5,0x77,0x21,0x61,0x65,0x61,0x65,0x77, ++0x60,0x62,0xE0,0x7E,0x00,0xF0,0x0F,0x00, ++0x40,0xF0,0x20,0x00,0x04,0xF8,0x44,0x0C, ++0xE0,0x7E,0x60,0x3C,0xFF,0xF7,0x66,0xFE, ++0x31,0x4F,0x97,0xF8,0x24,0x00,0x81,0x06, ++0x00,0xD5,0x40,0x25,0x80,0x07,0x01,0xD5, ++0x68,0x06,0x07,0xD5,0xD4,0xF8,0x84,0x00, ++0x01,0x21,0x22,0x46,0xFF,0xF7,0x5C,0xFF, ++0x45,0xF0,0x01,0x05,0x0D,0xB1,0x87,0xF8, ++0x24,0x50,0x60,0x7E,0xFF,0x28,0x03,0xD1, ++0x94,0xF8,0x2E,0x00,0x01,0x28,0xF8,0xD0, ++0x94,0xF8,0x7D,0x00,0x18,0xB9,0x94,0xF8, ++0x2E,0x00,0x01,0x28,0xF8,0xD0,0x26,0x67, ++0x00,0x20,0xF0,0xBD,0x10,0xB5,0x14,0x46, ++0xFF,0x22,0x84,0x34,0x04,0xF8,0x6A,0x2C, ++0x61,0x61,0x00,0x22,0xA2,0x61,0xA0,0x62, ++0xE2,0x62,0x21,0x82,0xE0,0x7F,0x00,0xF0, ++0x0F,0x00,0x40,0xF0,0xA0,0x00,0x04,0xF8, ++0x68,0x0C,0x84,0x3C,0x0C,0x21,0x02,0x20, ++0x23,0x46,0x04,0xF0,0xD9,0xFF,0xA0,0x7E, ++0xFF,0x28,0x03,0xD1,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF8,0xD0,0x00,0x20,0x10,0xBD, ++0x0E,0x48,0x08,0x30,0x01,0x88,0x21,0xF4, ++0x00,0x41,0x01,0x80,0x01,0x88,0x41,0xF4, ++0x80,0x41,0x01,0x80,0x70,0x47,0xF0,0xB5, ++0x02,0xF1,0x98,0x04,0x0D,0x46,0x21,0x60, ++0x00,0x26,0x66,0x60,0x60,0x61,0xA6,0x61, ++0xE0,0x7A,0x14,0x46,0xFF,0xF7,0x06,0xFE, ++0xDF,0xF8,0x04,0xC0,0x01,0x27,0x35,0xE0, ++0x00,0x40,0x00,0x25,0x0C,0x41,0x00,0x25, ++0xFF,0xF7,0xDE,0xFF,0xA0,0x7F,0x01,0x28, ++0x2C,0xD1,0xA6,0x77,0xB4,0xF8,0x94,0x00, ++0x2D,0x1A,0x94,0xF8,0xA3,0x00,0x00,0xF0, ++0x0F,0x00,0x40,0xF0,0xA0,0x00,0x20,0x77, ++0xB4,0xF8,0x94,0x00,0xB4,0xF8,0x92,0x10, ++0x88,0x42,0x07,0xD3,0x94,0x34,0xA0,0x68, ++0x21,0x88,0x08,0x44,0x61,0x68,0x94,0x3C, ++0x88,0x42,0x02,0xD3,0x84,0xF8,0xA5,0x70, ++0x01,0xE0,0x84,0xF8,0xA5,0x60,0xD4,0xF8, ++0xAC,0x00,0x02,0x21,0x22,0x46,0xFF,0xF7, ++0xEE,0xFD,0xBC,0xF8,0x30,0x00,0xA4,0xF8, ++0x94,0x00,0xB4,0xF8,0x94,0x00,0x08,0xB9, ++0x8C,0xF8,0x2C,0x60,0x00,0x2D,0xCB,0xD1, ++0xD4,0xF8,0x98,0x00,0xD4,0xF8,0x9C,0x10, ++0x88,0x42,0x03,0xD0,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF5,0xD0,0x94,0xF8,0xA5,0x00, ++0x18,0xB9,0x94,0xF8,0x2E,0x00,0x01,0x28, ++0xF8,0xD0,0xC4,0xF8,0x98,0x60,0x00,0x20, ++0xF0,0xBD,0x03,0x46,0x10,0xB5,0x0C,0x46, ++0x08,0x46,0xFF,0xF7,0xAD,0xFE,0x58,0x79, ++0x28,0xB9,0x18,0x88,0x21,0x46,0xBD,0xE8, ++0x10,0x40,0x05,0xF0,0xD5,0xBC,0x94,0xF8, ++0x2A,0x00,0x40,0x07,0x05,0xD4,0x21,0x46, ++0xBD,0xE8,0x10,0x40,0x18,0x46,0x05,0xF0, ++0xE7,0xBA,0x10,0xBD,0x2D,0xE9,0xF1,0x4F, ++0x00,0x27,0x44,0x4C,0x84,0xB0,0x94,0xF8, ++0x1C,0x90,0x94,0xF8,0x00,0x04,0x84,0xF8, ++0x00,0x04,0x18,0xB1,0x04,0x99,0x01,0x20, ++0x05,0xF0,0x0B,0xF8,0x20,0x7D,0x20,0x75, ++0x38,0xB1,0x04,0x99,0xAD,0xF8,0x04,0x00, ++0x01,0xA8,0x8D,0xF8,0x09,0x70,0xFF,0xF7, ++0xCC,0xFF,0xA1,0x88,0xA0,0x46,0x20,0x46, ++0x3C,0x46,0x61,0xF3,0x0F,0x04,0x01,0x89, ++0x61,0xF3,0x1F,0x44,0xA5,0xB2,0x85,0x80, ++0x21,0x0C,0x01,0x81,0xE8,0x07,0x4F,0xF0, ++0x01,0x06,0x19,0xD0,0x41,0x46,0x88,0xF8, ++0x1C,0x70,0x98,0xF8,0x24,0x00,0x8D,0xF8, ++0x08,0x70,0x8D,0xF8,0x0D,0x70,0xAD,0xF8, ++0x04,0x00,0xC0,0x07,0x8D,0xF8,0x09,0x60, ++0x02,0xD0,0x08,0x8E,0xAD,0xF8,0x06,0x00, ++0x01,0xA8,0x04,0x99,0xFF,0xF7,0xA5,0xFF, ++0x25,0xF0,0x01,0x00,0x60,0xF3,0x0F,0x04, ++0x01,0x25,0xB2,0x46,0x8D,0xF8,0x09,0x60, ++0x02,0x26,0xBB,0x46,0x16,0xE0,0x37,0x42, ++0x10,0xD0,0x88,0xF8,0x1C,0x50,0x98,0xF8, ++0x24,0x00,0x04,0x99,0xAD,0xF8,0x04,0x00, ++0x01,0xA8,0x8D,0xF8,0x08,0xB0,0x8D,0xF8, ++0x0D,0x50,0xFF,0xF7,0x8A,0xFF,0xB7,0x43, ++0x67,0xF3,0x0F,0x04,0x6D,0x1C,0x70,0x04, ++0x06,0x0C,0xED,0xB2,0x27,0x04,0x3F,0x0C, ++0xE5,0xD1,0x01,0x25,0x02,0x26,0x1A,0xE0, ++0x37,0x42,0x14,0xD0,0x88,0xF8,0x1C,0x50, ++0x98,0xF8,0x2C,0x10,0x8D,0xF8,0x08,0xA0, ++0xAD,0xF8,0x04,0x10,0x8D,0xF8,0x0D,0x50, ++0xB8,0xF8,0x30,0x00,0x04,0x99,0xAD,0xF8, ++0x06,0x00,0x01,0xA8,0xFF,0xF7,0x69,0xFF, ++0xB7,0x43,0x67,0xF3,0x1F,0x44,0x6D,0x1C, ++0x70,0x04,0x06,0x0C,0xED,0xB2,0x27,0x0C, ++0xE2,0xD1,0x88,0xF8,0x1C,0x90,0x05,0xB0, ++0xBD,0xE8,0xF0,0x8F,0x00,0x40,0x00,0x25, ++0x70,0xB5,0x0D,0x46,0x04,0x46,0x4F,0xF4, ++0xA4,0x71,0x06,0xF0,0xD6,0xE8,0x01,0x20, ++0x60,0x71,0x7F,0x20,0xA0,0x71,0x0A,0x48, ++0xC4,0xF8,0x40,0x01,0x9A,0x20,0xC4,0xF8, ++0x44,0x01,0xC4,0xF8,0x3C,0x51,0x70,0xBD, ++0x00,0xF5,0x84,0x71,0xC1,0x60,0x20,0x39, ++0x01,0x61,0x30,0x31,0x41,0x61,0x70,0x47, ++0x2C,0x21,0x06,0xF0,0xBB,0xB8,0x00,0x00, ++0xD4,0x04,0x03,0x20,0x10,0xB5,0x04,0x46, ++0xFB,0xF7,0x68,0xF8,0x60,0x1C,0x10,0xBD, ++0x6A,0x48,0x70,0x47,0x69,0x49,0x10,0xB5, ++0x4A,0x8C,0x22,0xF0,0x0B,0x02,0x4A,0x84, ++0x01,0x28,0x67,0x4B,0x67,0x4C,0x68,0x4A, ++0x11,0xD1,0xB2,0xF8,0xBC,0x00,0x40,0xF4, ++0x00,0x60,0xA2,0xF8,0xBC,0x00,0x33,0xF8, ++0x80,0x0F,0x40,0xF0,0x02,0x00,0x18,0x80, ++0xB4,0xF8,0xCC,0x0D,0x40,0xF4,0x00,0x50, ++0xA4,0xF8,0xCC,0x0D,0x16,0xE0,0x02,0x28, ++0x14,0xD1,0xB2,0xF8,0xBC,0x00,0x20,0xF4, ++0x00,0x60,0xA2,0xF8,0xBC,0x00,0x33,0xF8, ++0x80,0x0F,0x20,0xF0,0x02,0x00,0x18,0x80, ++0xB4,0xF8,0xCC,0x0D,0x20,0xF4,0x00,0x50, ++0xA4,0xF8,0xCC,0x0D,0x48,0x8C,0x40,0xF0, ++0x0A,0x00,0x48,0x84,0x48,0x8C,0xA2,0xF8, ++0x60,0x01,0x00,0x20,0x10,0xBD,0x51,0x48, ++0xB0,0xF8,0xB4,0x11,0x21,0xF0,0x02,0x01, ++0xA0,0xF8,0xB4,0x11,0x01,0x88,0x21,0xF0, ++0x02,0x01,0x20,0xF8,0x40,0x1B,0x01,0x88, ++0x21,0xF0,0x02,0x01,0x01,0x80,0x00,0x20, ++0x70,0x47,0x48,0x48,0xB0,0xF8,0xB4,0x11, ++0x41,0xF0,0x02,0x01,0xA0,0xF8,0xB4,0x11, ++0x01,0x88,0x41,0xF0,0x02,0x01,0x20,0xF8, ++0x40,0x1B,0x01,0x88,0x41,0xF0,0x02,0x01, ++0x01,0x80,0x00,0x20,0x70,0x47,0x00,0xB5, ++0x02,0x46,0xFF,0xF7,0xEA,0xFF,0x3E,0x48, ++0x01,0x88,0x21,0xF0,0x10,0x01,0x01,0x80, ++0x01,0x88,0x41,0xF0,0x40,0x01,0x01,0x80, ++0x01,0x88,0x21,0xF4,0x80,0x51,0x01,0x80, ++0x01,0x88,0x41,0xF4,0x80,0x41,0x01,0x80, ++0xB0,0xF8,0x20,0x1C,0x21,0xF0,0x08,0x01, ++0xA0,0xF8,0x20,0x1C,0x01,0x88,0x21,0xF4, ++0x70,0x61,0x01,0x80,0x01,0x88,0x11,0x43, ++0x01,0x80,0xFF,0xF7,0xB8,0xFF,0x00,0x20, ++0x00,0xBD,0x00,0x20,0x70,0x47,0x70,0x47, ++0x70,0x47,0x10,0xB5,0x04,0x46,0xFB,0xF7, ++0x2A,0xED,0x20,0x46,0x10,0xBD,0x70,0x47, ++0x70,0x47,0x22,0x48,0xC0,0x30,0x70,0x47, ++0x70,0xB5,0x20,0x4C,0x20,0x34,0x01,0x20, ++0x20,0x74,0x24,0x48,0x01,0x88,0x41,0xF0, ++0x40,0x01,0x01,0x80,0x22,0x48,0x01,0x88, ++0x21,0xF4,0x00,0x41,0x01,0x80,0x21,0x48, ++0x01,0x88,0x41,0xF4,0x40,0x51,0x01,0x80, ++0x01,0x88,0x21,0xF4,0x00,0x41,0x01,0x80, ++0x00,0x25,0x65,0x80,0x01,0x20,0xFF,0xF7, ++0x51,0xFF,0xE5,0x60,0x28,0x46,0xFF,0xF7, ++0xAA,0xFF,0x19,0x48,0x00,0x68,0xA0,0x66, ++0x04,0xF5,0x28,0x70,0x60,0x66,0x00,0x20, ++0x25,0x72,0x65,0x72,0x00,0xF0,0x2C,0xF8, ++0x00,0x20,0x70,0xBD,0x10,0xB5,0xFB,0xF7, ++0xAC,0xFD,0x02,0x28,0x01,0xD1,0x00,0x20, ++0x10,0xBD,0x10,0x48,0x10,0xBD,0x10,0xB5, ++0xFB,0xF7,0xA3,0xFD,0x03,0x28,0x01,0xD1, ++0x00,0x20,0x10,0xBD,0x0B,0x48,0x80,0x1C, ++0x10,0xBD,0x00,0x00,0x20,0x06,0x03,0x20, ++0x00,0x70,0x00,0x25,0x00,0x00,0x02,0x25, ++0x00,0x50,0x00,0x25,0x18,0x7C,0x00,0x25, ++0x40,0x72,0x00,0x25,0x0C,0x7F,0x00,0x25, ++0x14,0x2C,0x02,0x25,0xCC,0x0D,0x02,0x25, ++0xAC,0x04,0x03,0x20,0x4D,0x00,0x00,0x80, ++0xFF,0x4A,0xFE,0x49,0x11,0x60,0x70,0x47, ++0x30,0xB4,0xFD,0x4C,0x24,0x68,0x24,0x68, ++0xA4,0x46,0x30,0xBC,0x60,0x47,0x30,0xB4, ++0xF9,0x4C,0x24,0x68,0x64,0x68,0xA4,0x46, ++0x30,0xBC,0x60,0x47,0x38,0xB5,0x1D,0x46, ++0x04,0x9B,0x00,0x93,0xF4,0x4B,0x1B,0x68, ++0x9C,0x68,0x2B,0x46,0xA0,0x47,0x38,0xBD, ++0x38,0xB5,0x1D,0x46,0x04,0x9B,0x00,0x93, ++0xEF,0x4B,0x1B,0x68,0xDC,0x68,0x2B,0x46, ++0xA0,0x47,0x38,0xBD,0x30,0xB4,0xEC,0x4C, ++0x24,0x68,0x24,0x69,0xA4,0x46,0x30,0xBC, ++0x60,0x47,0x30,0xB4,0xE8,0x4C,0x24,0x68, ++0x64,0x69,0xA4,0x46,0x30,0xBC,0x60,0x47, ++0x10,0xB5,0xFF,0xF7,0x2A,0xFF,0xE5,0x4C, ++0x4F,0xF6,0xFB,0x70,0xA4,0xF8,0x40,0x00, ++0x20,0x88,0x20,0xF4,0x80,0x50,0x20,0x80, ++0x01,0x20,0xFF,0xF7,0xCB,0xFE,0x20,0x88, ++0x40,0xF4,0x80,0x50,0x20,0x80,0x01,0x20, ++0xFF,0xF7,0xC4,0xFE,0xB4,0xF8,0x40,0x00, ++0xC0,0x3C,0x04,0x28,0x01,0xD0,0xDA,0x48, ++0x10,0xBD,0x20,0x89,0x40,0xF0,0x10,0x00, ++0x20,0x81,0x01,0x20,0xFF,0xF7,0xB6,0xFE, ++0x20,0x89,0x20,0xF0,0x10,0x00,0x20,0x81, ++0xFF,0xF7,0xF1,0xFE,0x00,0x20,0x10,0xBD, ++0x70,0xB5,0x00,0x24,0xCF,0x4E,0x4F,0xF4, ++0x80,0x35,0xC0,0x3E,0x30,0x89,0x80,0x06, ++0x05,0xD4,0x01,0x20,0xFF,0xF7,0xA2,0xFE, ++0x64,0x1C,0xAC,0x42,0xF6,0xD3,0xAC,0x42, ++0x04,0xD1,0xFF,0xF7,0xC1,0xFF,0xC8,0x48, ++0x09,0x30,0x70,0xBD,0x00,0x20,0x70,0xBD, ++0x70,0xB5,0x00,0x24,0xC3,0x4E,0xC5,0x4D, ++0xC0,0x3E,0x30,0x88,0x40,0x04,0x05,0xD4, ++0x64,0x1C,0x01,0x20,0xFF,0xF7,0x8A,0xFE, ++0xAC,0x42,0xF6,0xD3,0xAC,0x42,0x04,0xD1, ++0xFF,0xF7,0xAA,0xFF,0xBC,0x48,0x09,0x30, ++0x70,0xBD,0x00,0x20,0x70,0xBD,0xBC,0x48, ++0xFF,0x22,0x10,0xB5,0x00,0x24,0xC8,0x21, ++0x05,0xF0,0x9E,0xEE,0xB5,0x49,0x00,0x20, ++0xB7,0x4B,0xC0,0x39,0x31,0xF8,0xC0,0x2F, ++0x22,0xF4,0xE0,0x62,0x0A,0x80,0x0A,0x88, ++0x42,0xEA,0x00,0x22,0x0A,0x80,0x0A,0x88, ++0x23,0xF8,0x14,0x20,0x64,0x1C,0xA2,0xB2, ++0x8C,0x88,0x23,0xF8,0x12,0x40,0x52,0x1C, ++0x0C,0x89,0x92,0xB2,0x40,0x1C,0xC0,0x39, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x80,0xB2, ++0x94,0xB2,0x08,0x28,0xE2,0xD3,0x00,0x20, ++0xC6,0x31,0xCA,0x8F,0x22,0xF4,0xE0,0x42, ++0xCA,0x87,0xCA,0x8F,0x42,0xEA,0x00,0x32, ++0xCA,0x87,0x31,0xF8,0x06,0x2C,0x23,0xF8, ++0x14,0x20,0x64,0x1C,0xA2,0xB2,0xCC,0x8F, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x31,0xF8, ++0x02,0x4C,0x92,0xB2,0x23,0xF8,0x12,0x40, ++0x52,0x1C,0x4C,0x88,0x92,0xB2,0x40,0x1C, ++0xC6,0x39,0x23,0xF8,0x12,0x40,0x52,0x1C, ++0x80,0xB2,0x94,0xB2,0x08,0x28,0xDB,0xD3, ++0x10,0xBD,0x95,0x48,0xFF,0x22,0x10,0xB5, ++0x00,0x24,0xC8,0x21,0xC8,0x30,0x05,0xF0, ++0x50,0xEE,0x91,0x49,0x8D,0x48,0xC8,0x31, ++0xC0,0x38,0x30,0xF8,0x24,0x20,0x21,0xF8, ++0x14,0x20,0x64,0x1C,0xA4,0xB2,0x58,0x2C, ++0xF7,0xD3,0xDA,0x30,0x30,0xF8,0xDA,0x1C, ++0x30,0xF8,0xD6,0x1C,0x30,0xF8,0xD2,0x1C, ++0x30,0xF8,0xCE,0x1C,0x30,0xF8,0xBE,0x1C, ++0x30,0xF8,0xB2,0x1C,0x30,0xF8,0xAE,0x1C, ++0x30,0xF8,0xAA,0x1C,0x30,0xF8,0x6E,0x1C, ++0x30,0xF8,0x6A,0x1C,0x30,0xF8,0x66,0x1C, ++0x30,0xF8,0x5E,0x1C,0x30,0xF8,0x5A,0x1C, ++0x30,0xF8,0x26,0x1C,0x30,0xF8,0x22,0x1C, ++0x30,0xF8,0x1E,0x1C,0x30,0xF8,0x1A,0x1C, ++0x30,0xF8,0x16,0x1C,0x30,0xF8,0x12,0x1C, ++0x30,0xF8,0x06,0x1C,0x41,0x88,0xC1,0x88, ++0x41,0x89,0xC1,0x89,0x41,0x8A,0xC1,0x8A, ++0x41,0x8B,0x41,0x8C,0xC1,0x8C,0x41,0x8D, ++0xC1,0x8D,0x41,0x8E,0xC1,0x8E,0x41,0x8F, ++0x41,0x8D,0xC1,0x8F,0xB0,0xF8,0x42,0x10, ++0xB0,0xF8,0x46,0x10,0xB0,0xF8,0x4A,0x10, ++0xB0,0xF8,0x4E,0x10,0xB0,0xF8,0x5A,0x10, ++0xB0,0xF8,0x5E,0x10,0xB0,0xF8,0x62,0x10, ++0xB0,0xF8,0x66,0x10,0xB0,0xF8,0x6A,0x10, ++0xB0,0xF8,0x6E,0x10,0xB0,0xF8,0x72,0x10, ++0xB0,0xF8,0x7A,0x10,0xB0,0xF8,0x7E,0x00, ++0x10,0xBD,0x70,0xB5,0xFF,0xF7,0xCC,0xFD, ++0x04,0x46,0xC0,0x8F,0x08,0x28,0x02,0xD2, ++0x4F,0xF4,0x00,0x70,0x01,0xE0,0x4F,0xF4, ++0x80,0x60,0xA4,0xF8,0x6A,0x00,0x56,0x34, ++0x34,0xF8,0x1E,0x0C,0x02,0xF0,0x87,0xF8, ++0xA0,0x76,0x34,0xF8,0x1C,0x0C,0x02,0xF0, ++0x82,0xF8,0x20,0x77,0xA0,0x8A,0x02,0xF0, ++0x7E,0xF8,0xA0,0x77,0x01,0x25,0xA0,0x7E, ++0x05,0xFA,0x00,0xF0,0x40,0x1E,0x20,0x84, ++0x20,0x7F,0x05,0xFA,0x00,0xF0,0x40,0x1E, ++0xA0,0x84,0xA0,0x7F,0x05,0xFA,0x00,0xF1, ++0x49,0x1E,0x21,0x85,0x34,0xF8,0x1C,0x1C, ++0xC1,0x40,0x61,0x82,0x88,0xB2,0x02,0xF0, ++0x66,0xF8,0x60,0x77,0xC0,0xB2,0x05,0xFA, ++0x00,0xF1,0x49,0x1E,0xE1,0x84,0x34,0xF8, ++0x1A,0x1C,0xC1,0x40,0x89,0xB2,0x21,0xF0, ++0x01,0x01,0xE1,0x82,0x89,0xB2,0x81,0x40, ++0x24,0xF8,0x1A,0x1C,0xA1,0x7E,0x08,0x44, ++0xE0,0x76,0x85,0x40,0x25,0x82,0x6D,0x1E, ++0x00,0x20,0x65,0x84,0x70,0xBD,0x10,0xB5, ++0xFF,0xF7,0x7E,0xFD,0x82,0x8A,0x35,0x49, ++0x5E,0x31,0x21,0xF8,0xB2,0x2C,0xC2,0x8A, ++0x21,0xF8,0x1E,0x2C,0x02,0x8B,0x4A,0x80, ++0x42,0x8B,0xCA,0x80,0x82,0x8B,0x4A,0x84, ++0x31,0xF8,0x6E,0x2C,0x03,0x8C,0x03,0xF4, ++0x7C,0x53,0x1A,0x43,0x21,0xF8,0x6E,0x2C, ++0xC0,0x8B,0xC8,0x87,0x10,0xBD,0x2D,0xE9, ++0xF0,0x41,0x00,0x24,0x27,0x4F,0x05,0x46, ++0x0E,0x46,0xC0,0x3F,0x09,0xE0,0x38,0x88, ++0x35,0xEA,0x00,0x00,0x07,0xD0,0x01,0x20, ++0xFF,0xF7,0x50,0xFD,0xFF,0xF7,0xDC,0xFD, ++0x64,0x1C,0xB4,0x42,0xF3,0xD3,0xB4,0x42, ++0x02,0xD2,0x38,0x88,0x28,0x40,0x38,0x80, ++0x20,0x46,0xBD,0xE8,0xF0,0x81,0x10,0xB5, ++0xFF,0xF7,0x46,0xFD,0x04,0x46,0xFF,0xF7, ++0x63,0xFE,0x18,0x49,0xC0,0x39,0x88,0x88, ++0x4F,0xF6,0xFE,0x52,0x10,0x40,0x88,0x80, ++0x08,0x88,0x40,0xF2,0x01,0x22,0x10,0x40, ++0x08,0x80,0x20,0x20,0x08,0x85,0xA0,0x8A, ++0xA1,0xF8,0x6C,0x00,0xE0,0x8A,0xA1,0xF8, ++0x00,0x01,0xB1,0xF8,0x00,0x01,0xE0,0x8A, ++0x20,0x8B,0xA1,0xF8,0x20,0x01,0x60,0x8B, ++0xA1,0xF8,0x24,0x01,0xA0,0x8B,0xA1,0xF8, ++0x40,0x01,0xB1,0xF8,0xB0,0x20,0x20,0x8C, ++0x00,0xF4,0x7C,0x50,0x02,0x43,0xA1,0xF8, ++0xB0,0x20,0xE0,0x8B,0xA1,0xF8,0x5C,0x01, ++0x10,0xBD,0x00,0x00,0x30,0xEC,0x03,0x20, ++0x70,0x05,0x03,0x20,0xC0,0x50,0x00,0x25, ++0x2C,0x00,0x00,0x80,0x40,0x42,0x0F,0x00, ++0x60,0x0B,0x03,0x20,0x2D,0xE9,0xF0,0x41, ++0xFF,0xF7,0x06,0xFD,0x00,0x24,0x06,0x46, ++0x41,0xF2,0x88,0x37,0xFF,0x4D,0xA8,0x8B, ++0xC0,0x05,0x05,0xD4,0x01,0x20,0xFF,0xF7, ++0xF5,0xFC,0x64,0x1C,0xBC,0x42,0xF6,0xD3, ++0xF0,0x6A,0xFF,0xF7,0x54,0xFD,0xFF,0xF7, ++0xAA,0xFF,0x70,0x8C,0xA5,0xF8,0x60,0x01, ++0x28,0x88,0x00,0xF4,0x00,0x70,0x28,0x80, ++0x20,0x20,0xA5,0xF8,0x0C,0x01,0x48,0xF2, ++0x04,0x00,0xA5,0xF8,0x10,0x01,0x88,0x20, ++0xA5,0xF8,0x10,0x01,0x01,0x20,0xA5,0xF8, ++0x14,0x01,0xEF,0x4C,0x40,0x02,0x21,0x46, ++0xFF,0xF7,0x75,0xFF,0xA0,0x42,0xB5,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA5,0xF8, ++0x60,0x01,0x01,0xD1,0xE9,0x48,0x84,0xE7, ++0x00,0x20,0x82,0xE7,0x2D,0xE9,0xF0,0x41, ++0x04,0x46,0x0D,0x46,0x16,0x46,0x1F,0x46, ++0xFF,0xF7,0xC6,0xFC,0x00,0x22,0xD4,0xB3, ++0x01,0x8C,0x21,0xF4,0x40,0x51,0x01,0x84, ++0x01,0x8C,0x41,0xEA,0x05,0x31,0x01,0x84, ++0xDC,0x49,0xB0,0x31,0x0B,0x88,0x23,0xF4, ++0x40,0x53,0x0B,0x80,0x0B,0x88,0x04,0x8C, ++0x04,0xF4,0x40,0x54,0x23,0x43,0x0B,0x80, ++0x03,0x8C,0x23,0xF4,0x70,0x63,0x03,0x84, ++0x03,0x8C,0x43,0xEA,0x06,0x23,0x03,0x84, ++0x0B,0x88,0x23,0xF4,0x70,0x63,0x0B,0x80, ++0x0B,0x88,0x04,0x8C,0x04,0xF4,0x70,0x64, ++0x23,0x43,0x0B,0x80,0xC3,0x8B,0x4F,0xF2, ++0xF8,0x04,0x23,0x40,0xC3,0x83,0xC3,0x8B, ++0x43,0xEA,0x07,0x23,0xC3,0x83,0xC3,0x8B, ++0x23,0xF4,0x70,0x43,0xC3,0x83,0xC3,0x8B, ++0x43,0xF4,0x60,0x43,0xC3,0x83,0xC0,0x8B, ++0xA1,0xF8,0xAC,0x00,0x06,0xE0,0xFF,0xE7, ++0x01,0x20,0xFF,0xF7,0x87,0xFC,0xFF,0xF7, ++0x79,0xFF,0x02,0x46,0x10,0x46,0x34,0xE7, ++0xF0,0xB5,0xCB,0x07,0xBD,0x4F,0x0A,0xD0, ++0x4B,0x08,0x07,0xEB,0x83,0x03,0xB3,0xF8, ++0x00,0x34,0x49,0x1C,0x1B,0x0A,0x52,0x1E, ++0x01,0x26,0x03,0x70,0x00,0xE0,0x00,0x26, ++0x00,0x23,0x0C,0xE0,0x03,0xEB,0x51,0x04, ++0x07,0xEB,0x84,0x04,0xB4,0xF8,0x00,0x44, ++0x06,0xEB,0x43,0x05,0x44,0x55,0x05,0x44, ++0x24,0x0A,0x5B,0x1C,0x6C,0x70,0xB3,0xEB, ++0x52,0x0F,0xEF,0xD3,0xB2,0xEB,0x43,0x0F, ++0x08,0xD0,0x03,0xEB,0x51,0x01,0x07,0xEB, ++0x81,0x01,0xB1,0xF8,0x00,0x14,0x06,0xEB, ++0x43,0x02,0x81,0x54,0xF0,0xBD,0x2D,0xE9, ++0xF0,0x47,0x80,0x46,0x89,0x46,0x92,0x46, ++0x08,0x9D,0x1C,0x46,0xFF,0xF7,0x48,0xFC, ++0x06,0x46,0x40,0x8C,0xA1,0x4F,0xD2,0x37, ++0xA7,0xF8,0x8E,0x00,0x40,0xF2,0x01,0x20, ++0x27,0xF8,0xD2,0x0C,0x08,0x20,0x78,0x87, ++0xA7,0xF8,0x3E,0x80,0x0B,0x20,0x78,0x87, ++0x49,0xEA,0x09,0x20,0xF8,0x87,0x20,0x20, ++0x78,0x87,0x44,0xF6,0x10,0x40,0xF8,0x87, ++0xD2,0x3F,0xB8,0xF1,0x90,0x0F,0x05,0xD0, ++0x49,0xF6,0x80,0x10,0xA7,0xF8,0x10,0x01, ++0x88,0x20,0x01,0xE0,0x48,0xF6,0x99,0x00, ++0xA7,0xF8,0x10,0x01,0xE0,0x07,0x01,0xD0, ++0x64,0x1C,0xE4,0xB2,0x19,0x20,0xA7,0xF8, ++0x0C,0x01,0xA7,0xF8,0x10,0x41,0x00,0x20, ++0xA7,0xF8,0x10,0x01,0x03,0x20,0xA7,0xF8, ++0x14,0x01,0x4F,0xF4,0x96,0x78,0x41,0x46, ++0x4F,0xF4,0x00,0x70,0xFF,0xF7,0xA7,0xFE, ++0x40,0x45,0x12,0xD1,0x38,0x88,0xB7,0xF8, ++0x14,0x01,0xFF,0xF7,0x25,0xFD,0xFF,0xF7, ++0x82,0xFE,0xFF,0xF7,0xF7,0xFE,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0x7E,0x48,0x40,0x1C,0xBD,0xE8, ++0xF0,0x87,0x00,0x21,0x22,0x46,0x28,0x46, ++0xFF,0xF7,0x72,0xFF,0x70,0x8C,0x80,0x07, ++0x18,0xD0,0xBA,0xF1,0x01,0x0F,0x50,0x46, ++0x03,0xD0,0x02,0x28,0x12,0xD1,0x01,0x20, ++0x0E,0xE0,0x02,0x20,0x04,0xE0,0x15,0xF8, ++0x10,0x10,0x29,0x54,0x40,0x1C,0x80,0xB2, ++0xA0,0x42,0xF8,0xD3,0x06,0xE0,0x15,0xF8, ++0x10,0x10,0x29,0x54,0x40,0x1C,0x80,0xB2, ++0xA0,0x42,0xF8,0xD3,0xB7,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA7,0xF8,0x60,0x01, ++0x00,0x20,0xD4,0xE7,0x30,0xB5,0x01,0x22, ++0x89,0xB0,0x40,0x21,0x02,0xAB,0x90,0x20, ++0x00,0x93,0x0C,0x23,0xFF,0xF7,0x73,0xFF, ++0x00,0x28,0x1F,0xD1,0x00,0x21,0x02,0xAA, ++0x53,0x18,0x50,0x5C,0x5B,0x79,0x98,0x42, ++0x03,0xD1,0x49,0x1C,0xC9,0xB2,0x05,0x29, ++0xF6,0xD3,0x5C,0x48,0x19,0x30,0x05,0x29, ++0x10,0xD0,0x00,0x21,0x5A,0x4B,0x55,0x5C, ++0x5C,0x5C,0xAC,0x42,0x03,0xD1,0x49,0x1C, ++0xC9,0xB2,0x05,0x29,0xF7,0xD3,0x05,0x29, ++0x04,0xD1,0x9D,0xF8,0x0D,0x10,0x89,0x07, ++0x00,0xD5,0x00,0x20,0x09,0xB0,0x30,0xBD, ++0x2D,0xE9,0xF0,0x47,0xFF,0xF7,0x9C,0xFB, ++0x04,0x46,0xC0,0x6A,0x00,0x26,0xFF,0xF7, ++0xF6,0xFB,0xFF,0xF7,0x4C,0xFE,0x60,0x8C, ++0x80,0x07,0x02,0xD5,0x00,0x25,0x4B,0x4F, ++0x02,0xE0,0x48,0x48,0x1C,0x38,0x92,0xE7, ++0x00,0x24,0x01,0x20,0x23,0x46,0x32,0x46, ++0x29,0x46,0xFF,0xF7,0xB7,0xFE,0xB8,0x47, ++0x08,0xB3,0x64,0x1C,0xE4,0xB2,0x10,0x2C, ++0xF3,0xD3,0x6D,0x1C,0xED,0xB2,0x04,0x2D, ++0xEE,0xD3,0x00,0x25,0x01,0x26,0x00,0x24, ++0x01,0x20,0x23,0x46,0x32,0x46,0x29,0x46, ++0xFF,0xF7,0xA4,0xFE,0xB8,0x47,0x70,0xB1, ++0x64,0x1C,0xE4,0xB2,0x10,0x2C,0xF3,0xD3, ++0x76,0x1C,0xF6,0xB2,0x10,0x2E,0xEE,0xD3, ++0x6D,0x1C,0xED,0xB2,0x04,0x2D,0xE9,0xD3, ++0x32,0x48,0x1A,0x30,0x67,0xE7,0x64,0x1C, ++0xB0,0x46,0x04,0xF0,0xFF,0x09,0x00,0x24, ++0x0B,0xE0,0x01,0x20,0x4B,0x46,0x32,0x46, ++0x29,0x46,0xFF,0xF7,0x87,0xFE,0xB8,0x47, ++0x38,0xB9,0x04,0xB9,0xB0,0x46,0x64,0x1C, ++0xE4,0xB2,0x76,0x1C,0xF6,0xB2,0x10,0x2E, ++0xEF,0xD3,0x08,0xEB,0x54,0x00,0x4B,0x46, ++0x29,0x46,0xC2,0xB2,0x01,0x20,0xFF,0xF7, ++0x75,0xFE,0x00,0x20,0x47,0xE7,0x10,0xB5, ++0xFF,0xF7,0x3E,0xFB,0x04,0x46,0xFF,0xF7, ++0xFD,0xFB,0x00,0x28,0x09,0xD1,0x00,0x21, ++0x84,0xF8,0x30,0x10,0xA1,0x8B,0x21,0xF4, ++0x00,0x41,0xA1,0x83,0xA1,0x8B,0x1C,0x4A, ++0x11,0x80,0x15,0xE6,0x70,0xB5,0xFF,0xF7, ++0x2B,0xFB,0x14,0x4D,0x04,0x46,0x28,0x8D, ++0x20,0xF0,0x20,0x00,0x28,0x85,0x00,0x26, ++0xA5,0xF8,0x14,0x61,0xFF,0xF7,0x40,0xFC, ++0x00,0x28,0x70,0xD1,0x28,0x8D,0x40,0xF0, ++0x20,0x00,0x28,0x85,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0xC8,0x40,0xB4,0xF8,0x6A,0x10, ++0x08,0x44,0x20,0xF0,0x01,0x00,0xA0,0x82, ++0xA0,0x8A,0xA0,0x8A,0x40,0xF4,0x00,0x40, ++0xA0,0x82,0x3C,0x20,0xE0,0x82,0xE0,0x8A, ++0xA5,0xF8,0x00,0x01,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0x0B,0xE0,0x00,0x50,0x00,0x25, ++0x40,0x42,0x0F,0x00,0x34,0x00,0x00,0x80, ++0x28,0xEC,0x03,0x20,0x85,0x77,0x03,0x20, ++0x40,0x51,0x00,0x25,0x20,0xFA,0x01,0xF1, ++0x21,0x83,0x21,0x8B,0xFF,0x29,0x00,0xD8, ++0x21,0x8B,0x60,0x83,0x60,0x8B,0x4F,0xF4, ++0x00,0x61,0x88,0x42,0x00,0xD2,0x60,0x8B, ++0xA6,0x83,0x94,0xF8,0x30,0x00,0x18,0xB1, ++0xA0,0x8B,0x40,0xF4,0x00,0x40,0xA0,0x83, ++0x60,0x8F,0xB0,0xF5,0x00,0x5F,0x2F,0xD0, ++0x0C,0xDC,0xB0,0xF5,0x00,0x7F,0x13,0xD0, ++0x88,0x42,0x24,0xD0,0xB0,0xF5,0x80,0x5F, ++0x16,0xD1,0xA0,0x8B,0x40,0xF0,0x02,0x00, ++0xA0,0x83,0x11,0xE0,0xB0,0xF5,0x80,0x4F, ++0x22,0xD0,0xB0,0xF5,0x00,0x4F,0x0B,0xD1, ++0xA0,0x8B,0x40,0xF0,0x05,0x00,0xF3,0xE7, ++0xA0,0x8B,0x20,0xF0,0x07,0x00,0xA0,0x83, ++0x20,0x8B,0x40,0xF4,0x00,0x50,0x20,0x83, ++0xE0,0x8F,0x80,0x1E,0x09,0x28,0x20,0xD2, ++0xDF,0xE8,0x00,0xF0,0x12,0x18,0x4A,0x50, ++0x56,0x5C,0x62,0x68,0x6E,0x00,0xA0,0x8B, ++0x40,0xF0,0x01,0x00,0xDC,0xE7,0x3E,0xE0, ++0xA0,0x8B,0x40,0xF0,0x03,0x00,0xD7,0xE7, ++0xA0,0x8B,0x40,0xF0,0x04,0x00,0xD3,0xE7, ++0xA0,0x8B,0x20,0xF0,0x78,0x00,0xA0,0x83, ++0x08,0x20,0x04,0xE0,0xA0,0x8B,0x40,0xF0, ++0x08,0x00,0xA0,0x83,0x0E,0x20,0xA4,0xF8, ++0x6E,0x00,0xA0,0x8B,0x40,0xF0,0x80,0x00, ++0xA0,0x83,0xFF,0xF7,0x10,0xFD,0x00,0x23, ++0x1A,0x46,0x19,0x46,0x18,0x46,0xFF,0xF7, ++0xBD,0xFD,0x00,0x28,0x1B,0xD1,0xB5,0xF8, ++0xB0,0x00,0x20,0x84,0xB5,0xF8,0x5C,0x01, ++0xE0,0x83,0xB5,0xF8,0x60,0x01,0x60,0x84, ++0x60,0x8C,0x20,0xF0,0x03,0x00,0x60,0x84, ++0xFF,0xF7,0x39,0xFF,0xFE,0x49,0x88,0x42, ++0x06,0xD0,0x02,0x20,0xFF,0xF7,0x76,0xFA, ++0xFF,0xF7,0xD2,0xFE,0x00,0x28,0x02,0xD1, ++0xFF,0xF7,0xED,0xFC,0x00,0x20,0x70,0xBD, ++0xA0,0x8B,0x40,0xF0,0x10,0x00,0xA0,0x83, ++0x14,0x20,0xCC,0xE7,0xA0,0x8B,0x40,0xF0, ++0x18,0x00,0xA0,0x83,0x1A,0x20,0xC6,0xE7, ++0xA0,0x8B,0x40,0xF0,0x20,0x00,0xA0,0x83, ++0x22,0x20,0xC0,0xE7,0xA0,0x8B,0x40,0xF0, ++0x28,0x00,0xA0,0x83,0x28,0x20,0xBA,0xE7, ++0xA0,0x8B,0x40,0xF0,0x30,0x00,0xA0,0x83, ++0x2A,0x20,0xB4,0xE7,0xA0,0x8B,0x40,0xF0, ++0x38,0x00,0xA0,0x83,0x38,0x20,0xAE,0xE7, ++0xA0,0x8B,0x40,0xF0,0x40,0x00,0xA0,0x83, ++0x46,0x20,0xA8,0xE7,0x70,0xB5,0xFF,0xF7, ++0x3F,0xFA,0xE2,0x4E,0x04,0x46,0x30,0x8D, ++0x20,0xF0,0x20,0x00,0x30,0x85,0x00,0x25, ++0xA6,0xF8,0x14,0x51,0xFF,0xF7,0x54,0xFB, ++0x00,0x28,0x7D,0xD1,0x30,0x8D,0x40,0xF0, ++0x20,0x00,0x30,0x85,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0xC8,0x40,0xB4,0xF8,0x6A,0x10, ++0x08,0x44,0x20,0xF0,0x01,0x00,0xA0,0x82, ++0xA0,0x8A,0xA0,0x8A,0x40,0xF4,0x00,0x40, ++0xA0,0x82,0x3C,0x20,0xE0,0x82,0xE0,0x8A, ++0xA6,0xF8,0x00,0x01,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0x20,0xFA,0x01,0xF1,0x21,0x83, ++0x21,0x8B,0xFF,0x29,0x00,0xD8,0x21,0x8B, ++0x60,0x83,0x60,0x8B,0x4F,0xF4,0x00,0x61, ++0x88,0x42,0x00,0xD2,0x60,0x8B,0xA5,0x83, ++0x94,0xF8,0x30,0x00,0x18,0xB1,0xA0,0x8B, ++0x40,0xF4,0x00,0x40,0xA0,0x83,0x60,0x8F, ++0xB0,0xF5,0x00,0x5F,0x2D,0xD0,0x0B,0xDC, ++0xB0,0xF5,0x00,0x7F,0x12,0xD0,0x88,0x42, ++0x14,0xD0,0xB0,0xF5,0x80,0x5F,0x15,0xD1, ++0xA0,0x8B,0x40,0xF0,0x02,0x00,0x10,0xE0, ++0xB0,0xF5,0x80,0x4F,0x21,0xD0,0xB0,0xF5, ++0x00,0x4F,0x0B,0xD1,0xA0,0x8B,0x40,0xF0, ++0x05,0x00,0x06,0xE0,0xA0,0x8B,0x20,0xF0, ++0x07,0x00,0x02,0xE0,0xA0,0x8B,0x40,0xF0, ++0x01,0x00,0xA0,0x83,0x20,0x8B,0xA1,0x8E, ++0x08,0x43,0x20,0x83,0xE0,0x8F,0x0B,0x28, ++0x1D,0xD2,0xDF,0xE8,0x00,0xF0,0x1C,0x0E, ++0x15,0x22,0x28,0x2E,0x34,0x3A,0x40,0x46, ++0x4C,0x00,0xA0,0x8B,0x40,0xF0,0x03,0x00, ++0xEB,0xE7,0xA0,0x8B,0x40,0xF0,0x04,0x00, ++0xE7,0xE7,0xA0,0x8B,0x40,0xF0,0x40,0x00, ++0xA0,0x83,0x0A,0x20,0x05,0xE0,0x0B,0xE0, ++0xA0,0x8B,0x20,0xF0,0x78,0x00,0xA0,0x83, ++0x08,0x20,0xA4,0xF8,0x6E,0x00,0xA0,0x8B, ++0x40,0xF0,0x80,0x00,0xA0,0x83,0x00,0x20, ++0x70,0xBD,0xA0,0x8B,0x40,0xF0,0x08,0x00, ++0xA0,0x83,0x0E,0x20,0xF1,0xE7,0xA0,0x8B, ++0x40,0xF0,0x10,0x00,0xA0,0x83,0x14,0x20, ++0xEB,0xE7,0xA0,0x8B,0x40,0xF0,0x18,0x00, ++0xA0,0x83,0x1A,0x20,0xE5,0xE7,0xA0,0x8B, ++0x40,0xF0,0x20,0x00,0xA0,0x83,0x22,0x20, ++0xDF,0xE7,0xA0,0x8B,0x40,0xF0,0x28,0x00, ++0xA0,0x83,0x28,0x20,0xD9,0xE7,0xA0,0x8B, ++0x40,0xF0,0x30,0x00,0xA0,0x83,0x2A,0x20, ++0xD3,0xE7,0xA0,0x8B,0x40,0xF0,0x38,0x00, ++0xA0,0x83,0x38,0x20,0xCD,0xE7,0xA0,0x8B, ++0x40,0xF0,0x40,0x00,0xA0,0x83,0x46,0x20, ++0xC7,0xE7,0x2D,0xE9,0xFF,0x4F,0x81,0x46, ++0x83,0xB0,0x1D,0x46,0xFF,0xF7,0x7C,0xF9, ++0x04,0x46,0xB0,0xF8,0x76,0x00,0x4F,0xF0, ++0x00,0x0A,0x00,0xEA,0x09,0x00,0xD0,0x46, ++0x41,0x19,0x20,0x8F,0x56,0x46,0x81,0x42, ++0x04,0xD9,0x79,0x48,0x3B,0x38,0x07,0xB0, ++0xBD,0xE8,0xF0,0x8F,0xE0,0x6A,0xFF,0xF7, ++0xC6,0xF9,0xFF,0xF7,0x1C,0xFC,0x60,0x8C, ++0x74,0x4F,0xA7,0xF8,0x60,0x01,0x4F,0xF0, ++0x00,0x0B,0x40,0xF2,0x01,0x20,0x38,0x80, ++0x61,0x8F,0x04,0x98,0x69,0x43,0xFF,0xF7, ++0xE0,0xF9,0x61,0x8F,0xA7,0xF8,0x6C,0x11, ++0xA7,0xF8,0x70,0xB1,0x94,0xF8,0x73,0x10, ++0x05,0xFA,0x01,0xF1,0xB9,0x85,0xA7,0xF8, ++0x70,0x00,0x00,0x0C,0xA7,0xF8,0x74,0x00, ++0x38,0x89,0x20,0xF0,0x04,0x00,0x38,0x81, ++0xFF,0xF7,0x8E,0xFA,0x01,0x90,0x98,0xB1, ++0xFF,0xF7,0x5E,0xFA,0xFF,0xF7,0xBB,0xFB, ++0xFF,0xF7,0x30,0xFC,0x0A,0xF1,0x01,0x00, ++0xC0,0xB2,0x05,0x28,0x82,0x46,0xD4,0xD3, ++0xB7,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA7,0xF8,0x60,0x01,0x01,0x98,0xBE,0xE7, ++0xD2,0x37,0x37,0xF8,0xAA,0x0C,0x40,0xF0, ++0x01,0x00,0x27,0xF8,0xAA,0x0C,0x0B,0x20, ++0x78,0x87,0xA7,0xF8,0x3E,0xB0,0xA7,0xF8, ++0x3E,0x90,0x4F,0xEA,0x19,0x40,0xF8,0x87, ++0x20,0x20,0x78,0x87,0x94,0xF8,0x31,0x00, ++0x4F,0xEA,0x00,0x20,0xF8,0x87,0xD2,0x3F, ++0x20,0x8B,0x80,0x04,0x06,0xD5,0x49,0xF6, ++0x80,0x00,0xA7,0xF8,0x10,0x01,0x48,0xF6, ++0xB0,0x00,0x08,0xE0,0x48,0xF2,0x01,0x00, ++0xA7,0xF8,0x10,0x01,0x4B,0xF2,0x98,0x00, ++0xA7,0xF8,0x10,0x01,0x88,0x20,0xA7,0xF8, ++0x10,0x01,0x18,0x20,0xA7,0xF8,0x0C,0x01, ++0x68,0x1E,0xA7,0xF8,0x10,0x01,0x58,0xEA, ++0x06,0x00,0x02,0x90,0x04,0xD0,0x00,0x20, ++0xFF,0xF7,0x51,0xF9,0xA7,0xF8,0x04,0xB1, ++0x03,0x20,0xA7,0xF8,0x14,0x01,0x4F,0xF4, ++0x7A,0x70,0x05,0xFB,0x00,0xF1,0x40,0xF2, ++0x01,0x20,0xFF,0xF7,0x80,0xFB,0x05,0xEB, ++0x45,0x01,0xC1,0xEB,0xC5,0x11,0xB0,0xEB, ++0xC1,0x0F,0x19,0xD1,0xFF,0xF7,0xFC,0xF9, ++0xFF,0xF7,0x59,0xFB,0xFF,0xF7,0xCE,0xFB, ++0x08,0xF1,0x01,0x00,0xC0,0xB2,0x05,0x28, ++0x80,0x46,0x9C,0xD3,0x00,0x20,0xFF,0xF7, ++0x2E,0xF9,0xA7,0xF8,0x04,0xB1,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0x25,0x48,0x18,0x38,0x56,0xE7, ++0x02,0x98,0x20,0xB1,0x00,0x20,0xFF,0xF7, ++0x1E,0xF9,0xA7,0xF8,0x04,0xB1,0xB7,0xF8, ++0x44,0x01,0xC0,0x07,0x1D,0xD0,0x05,0x98, ++0x48,0xB1,0xA2,0x8F,0x4F,0xF4,0x00,0x70, ++0x82,0x42,0x00,0xD9,0x02,0x46,0x05,0x98, ++0x00,0x21,0xFF,0xF7,0x2D,0xFC,0xB7,0xF8, ++0x48,0x01,0xB7,0xF8,0x4C,0x01,0x05,0x2E, ++0x02,0xD2,0x76,0x1C,0xF6,0xB2,0x44,0xE7, ++0xB7,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA7,0xF8,0x60,0x01,0x10,0x48,0x41,0x38, ++0x2D,0xE7,0xFF,0xF7,0xFD,0xF9,0x30,0xB1, ++0xB7,0xF8,0x60,0x11,0x21,0xF0,0x03,0x01, ++0xA7,0xF8,0x60,0x11,0x23,0xE7,0x05,0x98, ++0x48,0xB1,0xA2,0x8F,0x4F,0xF4,0x00,0x70, ++0x82,0x42,0x00,0xD9,0x02,0x46,0x05,0x98, ++0x00,0x21,0xFF,0xF7,0x05,0xFC,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0x00,0x20,0x0F,0xE7,0x00,0x00, ++0x4D,0x00,0x00,0x80,0x00,0x50,0x00,0x25, ++0xFF,0x48,0x00,0x88,0xC1,0x07,0x02,0xD0, ++0x4F,0xF0,0xFF,0x30,0x70,0x47,0xC0,0xF3, ++0x45,0x00,0x70,0x47,0x2D,0xE9,0xFF,0x4F, ++0x82,0x46,0x81,0xB0,0x0F,0x46,0x1E,0x46, ++0xDD,0xF8,0x38,0x90,0xFF,0xF7,0x64,0xF8, ++0xB0,0xF8,0x76,0x20,0x04,0x46,0x90,0xF8, ++0x73,0x10,0x02,0xEA,0x0A,0x02,0x00,0x8F, ++0x8A,0x40,0x3A,0x44,0x88,0x40,0x4A,0x44, ++0x90,0x42,0x02,0xD2,0xEF,0x48,0x05,0xB0, ++0xE6,0xE6,0xE0,0x6A,0xFF,0xF7,0xAF,0xF8, ++0xFF,0xF7,0x05,0xFB,0x61,0x8C,0xDF,0xF8, ++0xB0,0xB3,0xAB,0xF8,0x60,0x11,0x40,0xF2, ++0x01,0x21,0xAB,0xF8,0x00,0x10,0x4D,0x46, ++0xB4,0xF8,0x68,0x00,0xC0,0x1B,0x48,0x45, ++0x00,0xD8,0x05,0x46,0x00,0x2D,0x7D,0xD0, ++0xB4,0xF8,0x6A,0x10,0x03,0x98,0x69,0x43, ++0xFF,0xF7,0xBF,0xF8,0x01,0x46,0x58,0x46, ++0xAB,0xF8,0x2C,0x50,0xBB,0xF8,0x40,0x21, ++0x52,0x07,0x18,0xD0,0x00,0xF5,0x8E,0x70, ++0x01,0x22,0x02,0x80,0x02,0x88,0x22,0xF0, ++0x7E,0x02,0x02,0x80,0x02,0x88,0x6F,0xF0, ++0x01,0x03,0x03,0xEB,0x45,0x03,0x1A,0x43, ++0x02,0x80,0x02,0x88,0x22,0xF4,0xFC,0x52, ++0x02,0x80,0x02,0x88,0x42,0xEA,0xC7,0x12, ++0x02,0x80,0xA0,0xF5,0x8E,0x70,0x80,0x46, ++0xA0,0xF8,0x70,0x10,0x09,0x0C,0xA0,0xF8, ++0x74,0x10,0x01,0x89,0x21,0xF0,0x04,0x01, ++0x01,0x81,0xFF,0xF7,0x55,0xF9,0x08,0xB1, ++0x41,0x46,0xC1,0xE0,0xB8,0xF8,0x28,0x00, ++0x40,0xF0,0x01,0x00,0xA8,0xF8,0x28,0x00, ++0x0B,0x20,0xA8,0xF8,0x0C,0x01,0x94,0xF8, ++0x30,0x00,0x00,0x28,0x94,0xF8,0x74,0x00, ++0x00,0xD1,0x00,0xE0,0x40,0x1E,0x07,0xFA, ++0x00,0xF7,0xA8,0xF8,0x10,0x71,0xA8,0xF8, ++0x10,0xA1,0x4F,0xEA,0x1A,0x40,0xA8,0xF8, ++0x10,0x01,0x20,0x20,0xA8,0xF8,0x0C,0x01, ++0x94,0xF8,0x31,0x00,0x4F,0xEA,0x00,0x20, ++0xA8,0xF8,0x10,0x01,0x20,0x8B,0x80,0x04, ++0x06,0xD5,0x49,0xF6,0x80,0x00,0xA8,0xF8, ++0x10,0x01,0x48,0xF6,0x88,0x00,0x05,0xE0, ++0x48,0xF2,0x01,0x00,0xA8,0xF8,0x10,0x01, ++0x48,0xF6,0x98,0x00,0xA8,0xF8,0x10,0x01, ++0x03,0x20,0xA8,0xF8,0x14,0x01,0x4F,0xF4, ++0x7A,0x71,0x40,0xF2,0x01,0x20,0xFF,0xF7, ++0x62,0xFA,0x00,0x27,0xB0,0xF5,0x7A,0x7F, ++0x12,0xD1,0xFF,0xF7,0xE1,0xF8,0xFF,0xF7, ++0x3E,0xFA,0x00,0xE0,0x3F,0xE0,0xB8,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA8,0xF8, ++0x60,0x01,0xFF,0xF7,0xAB,0xFA,0xA8,0xF8, ++0x1C,0x71,0x9E,0x48,0x23,0x30,0x5A,0xE7, ++0xB8,0xF8,0x44,0x01,0xC0,0x07,0x15,0xD0, ++0x2E,0xB1,0xB4,0xF8,0x6C,0x20,0x00,0x21, ++0x30,0x46,0xFF,0xF7,0x25,0xFB,0xB8,0xF8, ++0x48,0x01,0xB8,0xF8,0x4C,0x01,0xB8,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA8,0xF8, ++0x60,0x01,0xA8,0xF8,0x1C,0x71,0x91,0x48, ++0x80,0x1F,0x40,0xE7,0xFF,0xF7,0xF8,0xF8, ++0x30,0xB1,0xB8,0xF8,0x60,0x11,0x21,0xF0, ++0x03,0x01,0xA8,0xF8,0x60,0x11,0x36,0xE7, ++0x5E,0xB1,0xB4,0xF8,0x6C,0x20,0x4F,0xF4, ++0x00,0x70,0x6A,0x43,0x82,0x42,0x00,0xD9, ++0x02,0x46,0x00,0x21,0x30,0x46,0xFF,0xF7, ++0xFF,0xFA,0xA8,0xF8,0x1C,0x71,0xB9,0xEB, ++0x05,0x08,0x3C,0xD0,0x94,0xF8,0x73,0x10, ++0x0A,0xF1,0x01,0x0A,0x28,0xFA,0x01,0xF0, ++0x03,0x99,0x87,0xB2,0x94,0xF8,0x74,0x00, ++0x05,0xFA,0x00,0xF0,0x00,0xEB,0x01,0x09, ++0x1E,0xB1,0xB4,0xF8,0x6C,0x00,0x05,0xFB, ++0x00,0x66,0x37,0xB1,0x3B,0x46,0x32,0x46, ++0x49,0x46,0x50,0x46,0xFF,0xF7,0x57,0xF8, ++0xC8,0xB9,0x94,0xF8,0x73,0x10,0x07,0xFA, ++0x01,0xF0,0x94,0xF8,0x74,0x10,0x00,0xFA, ++0x01,0xF1,0x01,0xEB,0x09,0x02,0x1E,0xB1, ++0xB4,0xF8,0x6C,0x10,0x00,0xFB,0x01,0x66, ++0xB8,0xEB,0x00,0x03,0x0A,0xEB,0x07,0x00, ++0x0D,0xD0,0x00,0x93,0x00,0x21,0x33,0x46, ++0xFF,0xF7,0x4E,0xF8,0x38,0xB1,0x59,0x46, ++0xB1,0xF8,0x60,0x21,0x22,0xF0,0x03,0x02, ++0xA1,0xF8,0x60,0x21,0xE7,0xE6,0xBB,0xF8, ++0x60,0x11,0x21,0xF0,0x03,0x01,0xAB,0xF8, ++0x60,0x11,0x00,0x20,0xDF,0xE6,0x2D,0xE9, ++0xF0,0x5F,0x80,0x46,0x0E,0x46,0x93,0x46, ++0x0A,0x9D,0x99,0x46,0xFE,0xF7,0x2C,0xFF, ++0x04,0x46,0xC0,0x6A,0xFE,0xF7,0x87,0xFF, ++0xFF,0xF7,0xDD,0xF9,0x60,0x8C,0x58,0x4F, ++0xA7,0xF8,0x60,0x01,0x40,0xF2,0x01,0x2A, ++0xA7,0xF8,0x00,0xA0,0x58,0x46,0xB4,0xF8, ++0x6A,0x10,0x69,0x43,0xFE,0xF7,0xA1,0xFF, ++0xBD,0x85,0xB7,0xF8,0x40,0x11,0x49,0x07, ++0x15,0xD0,0x07,0xF5,0x8E,0x77,0x01,0x21, ++0x39,0x80,0x39,0x88,0x21,0xF0,0x7E,0x01, ++0x39,0x80,0x39,0x88,0x41,0xF0,0x02,0x01, ++0x39,0x80,0x39,0x88,0x21,0xF4,0xFC,0x51, ++0x39,0x80,0x39,0x88,0x41,0xEA,0xC6,0x11, ++0x39,0x80,0xA7,0xF5,0x8E,0x77,0xA7,0xF8, ++0x70,0x00,0x00,0x0C,0xA7,0xF8,0x74,0x00, ++0x38,0x89,0x20,0xF0,0x04,0x00,0x38,0x81, ++0xFF,0xF7,0x3E,0xF8,0x00,0x28,0x76,0xD1, ++0x38,0x8D,0x40,0xF0,0x01,0x00,0x38,0x85, ++0x0B,0x20,0xA7,0xF8,0x0C,0x01,0x94,0xF8, ++0x30,0x00,0x00,0x28,0x94,0xF8,0x74,0x00, ++0x00,0xD1,0x00,0xE0,0x40,0x1E,0x06,0xFA, ++0x00,0xF6,0xA7,0xF8,0x10,0x61,0xA7,0xF8, ++0x10,0x81,0x4F,0xEA,0x18,0x40,0xA7,0xF8, ++0x10,0x01,0x20,0x20,0xA7,0xF8,0x0C,0x01, ++0x94,0xF8,0x31,0x00,0x4F,0xEA,0x00,0x20, ++0xA7,0xF8,0x10,0x01,0x20,0x8B,0x80,0x04, ++0x06,0xD5,0x49,0xF6,0x80,0x00,0xA7,0xF8, ++0x10,0x01,0x48,0xF6,0xB0,0x00,0x09,0xE0, ++0x48,0xF2,0x01,0x00,0xA7,0xF8,0x10,0x01, ++0x4B,0xF2,0x98,0x00,0xA7,0xF8,0x10,0x01, ++0x48,0xF6,0x88,0x00,0xA7,0xF8,0x10,0x01, ++0x18,0x20,0xA7,0xF8,0x0C,0x01,0x4F,0xF0, ++0xFF,0x30,0x00,0xEB,0x55,0x00,0xA7,0xF8, ++0x10,0x01,0x03,0x20,0xA7,0xF8,0x14,0x01, ++0x4F,0xF4,0x7A,0x78,0x41,0x46,0x50,0x46, ++0xFF,0xF7,0x41,0xF9,0x00,0x26,0x40,0x45, ++0x11,0xD1,0xFE,0xF7,0xC1,0xFF,0xFF,0xF7, ++0x1E,0xF9,0xB7,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA7,0xF8,0x60,0x01,0xFF,0xF7, ++0x8D,0xF9,0xA7,0xF8,0x1C,0x61,0x0F,0x48, ++0x23,0x30,0xBD,0xE8,0xF0,0x9F,0xB7,0xF8, ++0x44,0x01,0xC0,0x07,0x1D,0xD0,0xB9,0xF1, ++0x00,0x0F,0x05,0xD0,0xB4,0xF8,0x6C,0x20, ++0x00,0x21,0x48,0x46,0xFF,0xF7,0x04,0xFA, ++0x07,0xF5,0xA4,0x77,0x38,0x88,0xB8,0x88, ++0x38,0x8B,0x20,0xF0,0x03,0x00,0x38,0x83, ++0x27,0xF8,0x2C,0x6C,0x06,0xE0,0x0B,0xE0, ++0x44,0x51,0x00,0x25,0x12,0x00,0x00,0x80, ++0x00,0x50,0x00,0x25,0xFA,0x48,0x80,0x1F, ++0xDB,0xE7,0xFE,0xF7,0xD1,0xFF,0x30,0xB1, ++0xB7,0xF8,0x60,0x11,0x21,0xF0,0x03,0x01, ++0xA7,0xF8,0x60,0x11,0xD1,0xE7,0xB9,0xF1, ++0x00,0x0F,0x0B,0xD0,0xB4,0xF8,0x6C,0x20, ++0x4F,0xF4,0x00,0x70,0x6A,0x43,0x82,0x42, ++0x00,0xD9,0x02,0x46,0x00,0x21,0x48,0x46, ++0xFF,0xF7,0xD6,0xF9,0xB7,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA7,0xF8,0x60,0x01, ++0xA7,0xF8,0x1C,0x61,0x00,0x20,0xB8,0xE7, ++0xE8,0x4A,0x01,0x46,0x00,0x20,0x12,0x88, ++0xD3,0x07,0x09,0xD0,0x01,0x29,0x02,0xD1, ++0xE3,0x48,0x00,0x1F,0x70,0x47,0x02,0x29, ++0xFC,0xD1,0xE1,0x48,0x2A,0x30,0x70,0x47, ++0x53,0x06,0x09,0xD4,0x01,0x29,0x02,0xD1, ++0xDD,0x48,0xC0,0x1F,0x70,0x47,0x02,0x29, ++0xFC,0xD1,0xDB,0x48,0x29,0x30,0x70,0x47, ++0x12,0x06,0xFC,0xD4,0x01,0x29,0x02,0xD1, ++0xD7,0x48,0xC0,0x1E,0x70,0x47,0x02,0x29, ++0xFC,0xD1,0xD5,0x48,0x2C,0x30,0x70,0x47, ++0x70,0xB5,0xCB,0x07,0xD4,0x4D,0x0B,0xD0, ++0x4B,0x08,0x05,0xEB,0x83,0x03,0xB3,0xF8, ++0x00,0x44,0xE4,0xB2,0x04,0xEB,0x00,0x24, ++0xA3,0xF8,0x00,0x44,0x49,0x1C,0x52,0x1E, ++0x00,0x23,0x00,0xEB,0x00,0x24,0x06,0xE0, ++0x03,0xEB,0x51,0x06,0x05,0xEB,0x86,0x06, ++0xA6,0xF8,0x00,0x44,0x5B,0x1C,0xB3,0xEB, ++0x52,0x0F,0xF5,0xD3,0xB2,0xEB,0x43,0x0F, ++0x0A,0xD0,0x03,0xEB,0x51,0x01,0x05,0xEB, ++0x81,0x01,0xB1,0xF8,0x00,0x24,0x02,0xF4, ++0x7F,0x42,0x10,0x44,0xA1,0xF8,0x00,0x04, ++0x70,0xBD,0xF0,0xB5,0xCB,0x07,0xBE,0x4F, ++0x0E,0xD0,0x4B,0x08,0x07,0xEB,0x83,0x03, ++0xB3,0xF8,0x00,0x44,0x05,0x78,0xE4,0xB2, ++0x04,0xEB,0x05,0x24,0xA3,0xF8,0x00,0x44, ++0x49,0x1C,0x52,0x1E,0x01,0x25,0x00,0xE0, ++0x00,0x25,0x00,0x23,0x0D,0xE0,0x05,0xEB, ++0x43,0x04,0x06,0x5D,0x04,0x44,0x64,0x78, ++0x06,0xEB,0x04,0x24,0x03,0xEB,0x51,0x06, ++0x07,0xEB,0x86,0x06,0xA6,0xF8,0x00,0x44, ++0x5B,0x1C,0xB3,0xEB,0x52,0x0F,0xEE,0xD3, ++0xB2,0xEB,0x43,0x0F,0x0D,0xD0,0x03,0xEB, ++0x51,0x01,0x07,0xEB,0x81,0x01,0xB1,0xF8, ++0x00,0x24,0x05,0xEB,0x43,0x03,0xC0,0x5C, ++0x02,0xF4,0x7F,0x42,0x10,0x44,0xA1,0xF8, ++0x00,0x04,0xF0,0xBD,0x2D,0xE9,0xF0,0x5F, ++0x80,0x46,0x0F,0x46,0x91,0x46,0x0A,0x9D, ++0x9B,0x46,0xFE,0xF7,0xB5,0xFD,0xB0,0xF8, ++0x68,0x20,0x04,0x46,0x9A,0x48,0x79,0x19, ++0x80,0x1D,0x91,0x42,0x49,0xD8,0x00,0x2D, ++0x47,0xD0,0xE0,0x6A,0xFE,0xF7,0x07,0xFE, ++0xFF,0xF7,0x5D,0xF8,0x60,0x8C,0x96,0x4E, ++0xA6,0xF8,0x60,0x01,0x40,0xF2,0x01,0x2A, ++0xA6,0xF8,0x00,0xA0,0x48,0x46,0xB4,0xF8, ++0x6A,0x10,0xFE,0xF7,0x22,0xFE,0xB5,0x85, ++0xB6,0xF8,0x40,0x11,0x4F,0xF0,0x01,0x09, ++0x49,0x07,0x18,0xD0,0x06,0xF5,0x8E,0x76, ++0xA6,0xF8,0x00,0x90,0x31,0x88,0x21,0xF0, ++0x7E,0x01,0x31,0x80,0x31,0x88,0x6F,0xF0, ++0x01,0x02,0x02,0xEB,0x45,0x02,0x11,0x43, ++0x31,0x80,0x31,0x88,0x21,0xF4,0xFC,0x51, ++0x31,0x80,0x31,0x88,0x41,0xEA,0xC7,0x11, ++0x31,0x80,0xA6,0xF5,0x8E,0x76,0xA6,0xF8, ++0x70,0x00,0x00,0x0C,0xA6,0xF8,0x74,0x00, ++0x30,0x89,0x40,0xF2,0x04,0x41,0x08,0x43, ++0x30,0x81,0xFE,0xF7,0xB9,0xFE,0x00,0x25, ++0x40,0xB1,0xB6,0xF8,0x60,0x11,0x21,0xF0, ++0x03,0x01,0xA6,0xF8,0x60,0x11,0xA6,0xF8, ++0x1C,0x51,0xCE,0xE6,0x30,0x8D,0x40,0xF0, ++0x01,0x00,0x30,0x85,0x4F,0xF0,0x0B,0x0C, ++0xA6,0xF8,0x0C,0xC1,0x94,0xF8,0x30,0x00, ++0x00,0x28,0x94,0xF8,0x74,0x00,0x00,0xD1, ++0x00,0xE0,0x40,0x1E,0x87,0x40,0xA6,0xF8, ++0x10,0x71,0x06,0xF5,0x86,0x76,0xA6,0xF8, ++0x04,0x80,0x4F,0xEA,0x18,0x40,0xB0,0x80, ++0x4F,0xF0,0x20,0x08,0xA6,0xF8,0x00,0x80, ++0x05,0x21,0x94,0xF8,0x31,0x00,0x01,0xEB, ++0x00,0x20,0xB0,0x80,0x4F,0xF4,0xD2,0x60, ++0xB0,0x80,0xA6,0xF5,0x86,0x76,0x94,0xF8, ++0x28,0x00,0x30,0xB9,0x4F,0xF4,0x58,0x60, ++0xA6,0xF8,0x10,0x01,0x48,0xF6,0x81,0x00, ++0x01,0xE0,0x48,0xF6,0x80,0x00,0xA6,0xF8, ++0x10,0x01,0xBB,0xF1,0x00,0x0F,0xB4,0xF8, ++0x6C,0x00,0xB4,0xF8,0x6E,0x10,0xA0,0xEB, ++0x01,0x02,0x4F,0xF0,0x00,0x01,0x03,0xD0, ++0x58,0x46,0xFF,0xF7,0x26,0xFF,0x02,0xE0, ++0xFF,0x20,0xFF,0xF7,0xF5,0xFE,0xA6,0xF8, ++0x14,0xC1,0x50,0x46,0x4F,0x4F,0x39,0x46, ++0xFE,0xF7,0xAD,0xFF,0xDF,0xF8,0x28,0xB1, ++0xB8,0x42,0x0B,0xF1,0x3D,0x0B,0x04,0xD1, ++0xA6,0xF8,0x1C,0x51,0xFE,0xF7,0x28,0xFE, ++0x21,0xE0,0x94,0xF8,0x28,0x00,0x01,0x28, ++0x29,0xD1,0xFE,0xF7,0xB8,0xFF,0xD6,0x36, ++0x26,0xF8,0xD6,0xAC,0xA6,0xF8,0x36,0x80, ++0x48,0xF2,0x0D,0x10,0x70,0x87,0x88,0x20, ++0x70,0x87,0xA6,0xF8,0x3E,0x90,0xD6,0x3E, ++0x39,0x46,0x4F,0xF4,0x00,0x70,0xFE,0xF7, ++0x8A,0xFF,0xB8,0x42,0x13,0xD1,0xA6,0xF8, ++0x1C,0x51,0xFE,0xF7,0x09,0xFE,0x20,0x8B, ++0x20,0xF4,0x00,0x60,0x20,0x83,0xFE,0xF7, ++0x62,0xFF,0xB6,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA6,0xF8,0x60,0x01,0xFE,0xF7, ++0xD1,0xFF,0x58,0x46,0x45,0xE6,0xB6,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA6,0xF8, ++0x60,0x01,0xA6,0xF8,0x1C,0x51,0x02,0x20, ++0xBD,0xE8,0xF0,0x5F,0x80,0xE6,0x2D,0xE9, ++0xF0,0x5F,0x80,0x46,0x0D,0x46,0x91,0x46, ++0xDD,0xF8,0x28,0xA0,0x1E,0x46,0xFE,0xF7, ++0xC3,0xFC,0x04,0x46,0xC0,0x6A,0xFE,0xF7, ++0x1E,0xFD,0xFE,0xF7,0x74,0xFF,0x60,0x8C, ++0x21,0x4F,0xA7,0xF8,0x60,0x01,0x40,0xF2, ++0x01,0x2B,0xA7,0xF8,0x00,0xB0,0x48,0x46, ++0xB4,0xF8,0x6A,0x10,0xFE,0xF7,0x39,0xFD, ++0xA7,0xF8,0x2C,0xA0,0xB7,0xF8,0x40,0x11, ++0x49,0x07,0x15,0xD0,0x07,0xF5,0x8E,0x77, ++0x01,0x21,0x39,0x80,0x39,0x88,0x21,0xF0, ++0x7E,0x01,0x39,0x80,0x39,0x88,0x41,0xF0, ++0x02,0x01,0x39,0x80,0x39,0x88,0x21,0xF4, ++0xFC,0x51,0x39,0x80,0x39,0x88,0x41,0xEA, ++0xC5,0x11,0x39,0x80,0xA7,0xF5,0x8E,0x77, ++0xA7,0xF8,0x70,0x00,0x00,0x0C,0xA7,0xF8, ++0x74,0x00,0x38,0x89,0x40,0xF2,0x04,0x41, ++0x08,0x43,0x38,0x81,0xFE,0xF7,0xD4,0xFD, ++0x4F,0xF0,0x00,0x09,0x80,0xB1,0xB7,0xF8, ++0x60,0x11,0x21,0xF0,0x03,0x01,0xA7,0xF8, ++0x60,0x11,0xA7,0xF8,0x1C,0x91,0xE8,0xE5, ++0x12,0x00,0x00,0x80,0x18,0x51,0x00,0x25, ++0x00,0x50,0x00,0x25,0x40,0x42,0x0F,0x00, ++0x38,0x8D,0x40,0xF0,0x01,0x00,0x38,0x85, ++0x4F,0xF0,0x0B,0x0C,0xA7,0xF8,0x0C,0xC1, ++0x94,0xF8,0x30,0x00,0x00,0x28,0x94,0xF8, ++0x74,0x00,0x00,0xD1,0x00,0xE0,0x40,0x1E, ++0x85,0x40,0xA7,0xF8,0x10,0x51,0x07,0xF5, ++0x86,0x77,0xA7,0xF8,0x04,0x80,0x4F,0xEA, ++0x18,0x40,0xB8,0x80,0x20,0x20,0x38,0x80, ++0x05,0x21,0x94,0xF8,0x31,0x00,0x01,0xEB, ++0x00,0x20,0xB8,0x80,0x4F,0xF4,0xD2,0x60, ++0xB8,0x80,0x4F,0xF4,0x58,0x60,0xB8,0x80, ++0x4B,0xF2,0x81,0x00,0xB8,0x80,0x88,0x20, ++0xB8,0x80,0x18,0x20,0x38,0x80,0x89,0x1F, ++0x01,0xEB,0x5A,0x00,0xB8,0x80,0x00,0x20, ++0xA7,0xF5,0x86,0x77,0x4F,0xF4,0x00,0x78, ++0xB6,0xB1,0x10,0xE0,0xB4,0xF8,0x6C,0x30, ++0x45,0x1C,0x03,0xFB,0x05,0xF1,0x41,0x45, ++0x22,0xDC,0xB4,0xF8,0x6E,0x10,0x5A,0x1A, ++0x03,0xFB,0x00,0xF1,0x03,0xFB,0x00,0x60, ++0xFF,0xF7,0x33,0xFE,0xA8,0xB2,0xB4,0xF8, ++0x68,0x10,0x81,0x42,0xEA,0xD8,0x13,0xE0, ++0x0E,0xE0,0xB4,0xF8,0x6C,0x10,0x45,0x1C, ++0x01,0xFB,0x05,0xF2,0x42,0x45,0x0B,0xDC, ++0xB4,0xF8,0x6E,0x20,0x8A,0x1A,0x41,0x43, ++0xFF,0x20,0xFF,0xF7,0xF1,0xFD,0xA8,0xB2, ++0xB4,0xF8,0x68,0x10,0x81,0x42,0xEC,0xD8, ++0xA7,0xF8,0x14,0xC1,0xFC,0x4C,0x58,0x46, ++0x21,0x46,0xFE,0xF7,0xA4,0xFE,0xA0,0x42, ++0x0F,0xD1,0xA7,0xF8,0x1C,0x91,0xFE,0xF7, ++0x23,0xFD,0xFE,0xF7,0x80,0xFE,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0xFE,0xF7,0xEF,0xFE,0xF3,0x48, ++0x63,0xE5,0xB7,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA7,0xF8,0x60,0x01,0xA7,0xF8, ++0x1C,0x91,0x02,0x20,0xBD,0xE8,0xF0,0x5F, ++0x9E,0xE5,0x2D,0xE9,0xF0,0x41,0x00,0x24, ++0xEB,0x4F,0x05,0x46,0x0E,0x46,0x0A,0xE0, ++0xB7,0xF8,0x7C,0x00,0x35,0xEA,0x00,0x00, ++0x07,0xD0,0x01,0x20,0xFE,0xF7,0xD6,0xFB, ++0xFE,0xF7,0x62,0xFC,0x64,0x1C,0xB4,0x42, ++0xF2,0xD3,0x20,0x46,0xBD,0xE8,0xF0,0x81, ++0x2D,0xE9,0xF0,0x5F,0x05,0x46,0x0E,0x46, ++0x17,0x46,0xFE,0xF7,0xCD,0xFB,0x04,0x46, ++0xC0,0x6A,0xB2,0x46,0xFE,0xF7,0x27,0xFC, ++0xFE,0xF7,0x7D,0xFE,0x60,0x8C,0xDA,0x4E, ++0xA6,0xF8,0x60,0x01,0xB6,0xF8,0x80,0x00, ++0x40,0xF0,0x01,0x00,0xA6,0xF8,0x80,0x00, ++0x41,0xF2,0x01,0x60,0x30,0x80,0xB4,0xF8, ++0x68,0x00,0xB0,0x85,0x4F,0xF0,0x00,0x08, ++0xA6,0xF8,0x70,0x80,0xA6,0xF8,0x74,0x80, ++0x30,0x89,0x40,0xF2,0x04,0x41,0x08,0x43, ++0x30,0x81,0xFE,0xF7,0xF5,0xFC,0x30,0xB1, ++0xB6,0xF8,0x60,0x11,0x21,0xF0,0x03,0x01, ++0xA6,0xF8,0x60,0x11,0x0D,0xE5,0xD2,0x36, ++0x36,0xF8,0xAA,0x0C,0x40,0xF0,0x01,0x00, ++0x26,0xF8,0xAA,0x0C,0x4F,0xF0,0x0B,0x0C, ++0xA6,0xF8,0x3A,0xC0,0xA6,0xF8,0x3E,0x80, ++0xF5,0x87,0x28,0x0C,0xF0,0x87,0x20,0x20, ++0x70,0x87,0x05,0x21,0x94,0xF8,0x31,0x00, ++0x01,0xEB,0x00,0x20,0xF0,0x87,0x4F,0xF4, ++0xD2,0x60,0xF0,0x87,0xD2,0x3E,0x94,0xF8, ++0x28,0x00,0x30,0xB9,0x4F,0xF4,0x58,0x60, ++0xA6,0xF8,0x10,0x01,0x48,0xF6,0x81,0x00, ++0x01,0xE0,0x48,0xF6,0x80,0x00,0xA6,0xF8, ++0x10,0x01,0x00,0x20,0x11,0xE0,0xB4,0xF8, ++0x6C,0x30,0x45,0x1C,0x03,0xFB,0x05,0xF1, ++0xB1,0xF5,0x00,0x7F,0x0D,0xDC,0xB4,0xF8, ++0x6E,0x10,0x5A,0x1A,0x03,0xFB,0x00,0xF1, ++0x03,0xFB,0x00,0x70,0xFF,0xF7,0x6D,0xFD, ++0xA8,0xB2,0xB4,0xF8,0x68,0x10,0x81,0x42, ++0xE9,0xD8,0xB1,0x46,0xA6,0xF8,0x14,0xC1, ++0x00,0x27,0xDF,0xF8,0x8C,0x82,0x4D,0xE0, ++0x00,0x26,0x44,0xE0,0x01,0x20,0x45,0x46, ++0x41,0x46,0xFF,0xF7,0x66,0xFF,0xA8,0x42, ++0x17,0xD1,0xB9,0xF8,0x28,0x00,0x4C,0x46, ++0x20,0xF0,0x01,0x00,0xA9,0xF8,0x28,0x00, ++0xB9,0xF8,0x80,0x00,0x20,0xF0,0x01,0x00, ++0xA9,0xF8,0x80,0x00,0xFE,0xF7,0x60,0xFC, ++0xFE,0xF7,0xBD,0xFD,0xB4,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA4,0xF8,0x60,0x01, ++0x52,0xE0,0x2E,0xB9,0x09,0xF1,0x80,0x00, ++0x01,0x88,0x41,0xF0,0x10,0x01,0x01,0x80, ++0x00,0x25,0x4F,0xF4,0x80,0x6B,0x41,0x46, ++0x58,0x46,0xFE,0xF7,0xC4,0xFD,0x40,0x45, ++0xD7,0xD0,0xB4,0xF8,0x6A,0x10,0x05,0xEB, ++0x06,0x20,0x49,0x08,0x07,0xFB,0x01,0x00, ++0x3A,0xF8,0x10,0x10,0x09,0xF1,0x80,0x00, ++0x01,0x81,0x01,0x88,0x41,0xF0,0x20,0x01, ++0x01,0x80,0x6D,0x1C,0xAD,0xB2,0xFF,0x2D, ++0xE5,0xD9,0x76,0x1C,0xB6,0xB2,0xB4,0xF8, ++0x6A,0x00,0xB6,0xEB,0x50,0x2F,0xB5,0xD3, ++0x7F,0x1C,0xBF,0xB2,0xB4,0xF8,0x68,0x00, ++0xB8,0x42,0xAD,0xD8,0x41,0x20,0x4D,0x46, ++0xA9,0xF8,0x80,0x00,0x40,0xF2,0x01,0x27, ++0x46,0x46,0x41,0x46,0x38,0x46,0xFE,0xF7, ++0x96,0xFD,0xB0,0x42,0x17,0xD1,0x28,0x88, ++0x28,0x8D,0x20,0xF0,0x01,0x00,0x28,0x85, ++0xB5,0xF8,0x80,0x00,0x20,0xF0,0x01,0x00, ++0xA5,0xF8,0x80,0x00,0xFE,0xF7,0x0C,0xFC, ++0xFE,0xF7,0x69,0xFD,0xB5,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA5,0xF8,0x60,0x01, ++0x68,0x48,0x0F,0x38,0x4D,0xE4,0x94,0xF8, ++0x28,0x00,0x01,0x28,0x22,0xD1,0xFE,0xF7, ++0x92,0xFD,0xD6,0x35,0x25,0xF8,0xD6,0x7C, ++0x20,0x20,0xE8,0x86,0x48,0xF2,0x0D,0x10, ++0x68,0x87,0x88,0x20,0x68,0x87,0x01,0x20, ++0xE8,0x87,0xD6,0x3D,0x40,0x02,0x31,0x46, ++0xFE,0xF7,0x65,0xFD,0xB0,0x42,0x0D,0xD1, ++0xFE,0xF7,0xE6,0xFB,0xFE,0xF7,0x43,0xFD, ++0xB5,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA5,0xF8,0x60,0x01,0xFE,0xF7,0xB2,0xFD, ++0x54,0x48,0x26,0xE4,0x80,0x35,0xB5,0xF8, ++0xE0,0x00,0x20,0xF0,0x03,0x00,0xA5,0xF8, ++0xE0,0x00,0x28,0x88,0x20,0xF0,0x01,0x00, ++0x28,0x80,0x02,0x20,0xBD,0xE8,0xF0,0x5F, ++0x5E,0xE4,0x2D,0xE9,0xF8,0x4F,0x07,0x46, ++0x0D,0x46,0x92,0x46,0x1E,0x46,0xFE,0xF7, ++0xA3,0xFA,0x04,0x46,0xC0,0x6A,0xFE,0xF7, ++0xFE,0xFA,0xFE,0xF7,0x54,0xFD,0x60,0x8C, ++0xDF,0xF8,0x14,0x81,0xA8,0xF8,0x60,0x01, ++0x40,0xF2,0x01,0x29,0xA8,0xF8,0x00,0x90, ++0x00,0x21,0x32,0x46,0x50,0x46,0xFF,0xF7, ++0x98,0xFC,0xF0,0x07,0x06,0xD0,0xFF,0x20, ++0x00,0x90,0x01,0x22,0x31,0x46,0x68,0x46, ++0xFF,0xF7,0x8F,0xFC,0x0B,0x20,0xA8,0xF8, ++0x0C,0x01,0x94,0xF8,0x30,0x10,0x09,0xB1, ++0x4F,0xEA,0x55,0x05,0x21,0x8B,0x89,0x04, ++0x03,0xD5,0x29,0x02,0xA8,0xF8,0x10,0x11, ++0x01,0xE0,0xA8,0xF8,0x10,0x51,0xA8,0xF8, ++0x10,0x71,0x39,0x0C,0xA8,0xF8,0x10,0x11, ++0x20,0x25,0xA8,0xF8,0x0C,0x51,0x05,0x22, ++0x94,0xF8,0x31,0x10,0x02,0xEB,0x01,0x21, ++0xA8,0xF8,0x10,0x11,0x40,0xF2,0x91,0x61, ++0xA8,0xF8,0x10,0x11,0x94,0xF8,0x28,0x10, ++0x31,0xB9,0x4F,0xF4,0x58,0x61,0xA8,0xF8, ++0x10,0x11,0x48,0xF6,0x81,0x01,0x01,0xE0, ++0x48,0xF6,0x80,0x01,0xA8,0xF8,0x10,0x11, ++0x19,0x21,0xA8,0xF8,0x0C,0x11,0x06,0xF0, ++0x01,0x01,0x31,0x44,0xA8,0xF8,0x10,0x11, ++0x00,0x21,0xA8,0xF8,0x10,0x11,0xA8,0xF8, ++0x14,0x01,0x4F,0xF4,0x00,0x7A,0x18,0x4E, ++0x50,0x46,0x31,0x46,0xFE,0xF7,0xDB,0xFC, ++0x16,0x4F,0xB0,0x42,0x19,0xD0,0x94,0xF8, ++0x28,0x00,0x01,0x28,0x2A,0xD1,0xFE,0xF7, ++0xEE,0xFC,0xA8,0xF8,0x00,0x90,0xA8,0xF8, ++0x0C,0x51,0x48,0xF2,0x0D,0x10,0xA8,0xF8, ++0x10,0x01,0x88,0x20,0xA8,0xF8,0x10,0x01, ++0x01,0x20,0xA8,0xF8,0x14,0x01,0x31,0x46, ++0x50,0x46,0xFE,0xF7,0xC0,0xFC,0xB0,0x42, ++0x14,0xD1,0xFE,0xF7,0x41,0xFB,0xFE,0xF7, ++0x9E,0xFC,0xB8,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA8,0xF8,0x60,0x01,0xFE,0xF7, ++0x0D,0xFD,0x38,0x46,0xBD,0xE8,0xF8,0x8F, ++0x40,0x42,0x0F,0x00,0x4F,0x00,0x00,0x80, ++0x00,0x50,0x00,0x25,0xB8,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA8,0xF8,0x60,0x01, ++0x02,0x20,0xBD,0xE8,0xF8,0x4F,0xFF,0xF7, ++0xB7,0xBB,0x70,0xB5,0xFE,0xF7,0x00,0xFA, ++0x04,0x46,0xC0,0x6A,0xFE,0xF7,0x5B,0xFA, ++0xFE,0xF7,0xB1,0xFC,0x60,0x8C,0xFF,0x4E, ++0xA6,0xF8,0x8E,0x00,0x40,0xF2,0x01,0x20, ++0x26,0xF8,0xD2,0x0C,0x0B,0x20,0x70,0x87, ++0x00,0x21,0xF1,0x87,0x20,0x20,0x70,0x87, ++0x44,0xF6,0x03,0x40,0xF0,0x87,0x48,0xF6, ++0x99,0x00,0xF0,0x87,0xD2,0x3E,0x94,0xF8, ++0x30,0x00,0x08,0xB1,0x1C,0x20,0x00,0xE0, ++0x0E,0x20,0x19,0x22,0xA6,0xF8,0x0C,0x21, ++0xA6,0xF8,0x10,0x01,0xA6,0xF8,0x10,0x11, ++0x03,0x20,0xA6,0xF8,0x14,0x01,0x4F,0xF4, ++0x00,0x70,0xED,0x4D,0x29,0x46,0xFE,0xF7, ++0x6A,0xFC,0xA8,0x42,0x0A,0xD1,0x30,0x88, ++0xB6,0xF8,0x14,0x01,0xB6,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA6,0xF8,0x60,0x01, ++0xE6,0x48,0x70,0xBD,0x94,0xF8,0x30,0x00, ++0x58,0xB1,0x00,0x25,0x01,0x22,0x60,0x19, ++0x69,0x00,0x80,0x1C,0xFE,0xF7,0x38,0xFD, ++0x6D,0x1C,0xAD,0xB2,0x0E,0x2D,0xF5,0xD3, ++0x04,0xE0,0x0E,0x22,0x00,0x21,0xA0,0x1C, ++0xFE,0xF7,0x2E,0xFD,0xA2,0x78,0x01,0x20, ++0x21,0x18,0x8B,0x78,0x93,0x42,0x03,0xD1, ++0xC9,0x78,0xE3,0x78,0x99,0x42,0x03,0xD0, ++0x40,0x1C,0x80,0xB2,0x0E,0x28,0xF3,0xD3, ++0x60,0x74,0xB6,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA6,0xF8,0x60,0x01,0x00,0x20, ++0x70,0xBD,0x1F,0xB5,0xFE,0xF7,0x94,0xF9, ++0x41,0x8C,0x89,0x07,0x08,0xD0,0x40,0x8C, ++0x80,0x07,0x03,0xD5,0xCB,0x48,0x1C,0x30, ++0x04,0xB0,0x10,0xBD,0x00,0x20,0xFB,0xE7, ++0xC0,0x6A,0xFE,0xF7,0xE4,0xF9,0xFE,0xF7, ++0x3A,0xFC,0x01,0xAB,0x02,0x22,0x00,0x93, ++0x04,0x23,0x01,0x21,0xEE,0x20,0xFE,0xF7, ++0x2A,0xFD,0x00,0x28,0xEC,0xD1,0x9D,0xF8, ++0x04,0x00,0x04,0x23,0x01,0x21,0x20,0xF0, ++0x30,0x00,0x01,0xAA,0xC0,0xB2,0x40,0xF0, ++0x10,0x00,0x8D,0xF8,0x04,0x00,0xEF,0x20, ++0x00,0xF0,0x3E,0xF9,0xDC,0xE7,0x10,0xB5, ++0xFE,0xF7,0x66,0xF9,0x04,0x46,0xFE,0xF7, ++0x2E,0xFA,0x00,0x28,0x0A,0xD1,0x00,0x21, ++0x84,0xF8,0x30,0x10,0xA1,0x8B,0x21,0xF4, ++0x00,0x41,0xA1,0x83,0xA1,0x8B,0xAF,0x4A, ++0x6E,0x32,0x11,0x80,0x10,0xBD,0x70,0xB5, ++0xFE,0xF7,0x52,0xF9,0x04,0x46,0xC0,0x6A, ++0xFE,0xF7,0xAD,0xF9,0xFE,0xF7,0x03,0xFC, ++0xA8,0x4D,0x40,0xF2,0x01,0x20,0x25,0xF8, ++0xD2,0x0C,0x0B,0x20,0x68,0x87,0x00,0x20, ++0xE8,0x87,0xE8,0x87,0xE8,0x87,0x20,0x20, ++0x68,0x87,0x94,0xF8,0x31,0x00,0x4F,0xEA, ++0x00,0x20,0xE8,0x87,0xD2,0x3D,0x20,0x8B, ++0x80,0x04,0x02,0xD5,0x48,0xF6,0x80,0x00, ++0x04,0xE0,0x48,0xF2,0x01,0x00,0xA5,0xF8, ++0x10,0x01,0x88,0x20,0xA5,0xF8,0x10,0x01, ++0x01,0x20,0xA5,0xF8,0x14,0x01,0x00,0x24, ++0x4F,0xF4,0x96,0x76,0x28,0x88,0x80,0x05, ++0x08,0xD4,0x01,0x20,0xFE,0xF7,0x1A,0xF9, ++0xFE,0xF7,0xA6,0xF9,0x64,0x1C,0xB4,0x42, ++0xF4,0xD3,0x07,0xE0,0xB4,0x42,0x05,0xD2, ++0x28,0x88,0x00,0xF4,0x00,0x70,0x28,0x80, ++0x00,0x20,0x70,0xBD,0xFE,0xF7,0x30,0xFA, ++0xFE,0xF7,0x8D,0xFB,0xFE,0xF7,0x02,0xFC, ++0x8A,0x48,0x70,0xBD,0x2D,0xE9,0xF0,0x5F, ++0x06,0x46,0xFE,0xF7,0x05,0xF9,0x05,0x46, ++0xC0,0x6A,0xFE,0xF7,0x60,0xF9,0xFE,0xF7, ++0xB6,0xFB,0x68,0x8C,0x81,0x4C,0xA4,0xF8, ++0x8E,0x00,0x34,0xF8,0xD2,0x0C,0x00,0xF4, ++0x00,0x70,0x24,0xF8,0xD2,0x0C,0x0B,0x20, ++0x60,0x87,0x00,0x20,0xE0,0x87,0xE6,0x87, ++0x30,0x0C,0xE0,0x87,0x4F,0xF0,0x20,0x08, ++0xA4,0xF8,0x3A,0x80,0x09,0x21,0x95,0xF8, ++0x32,0x00,0x41,0xEA,0x00,0x20,0xE0,0x87, ++0x48,0xF2,0x0A,0x00,0xE0,0x87,0xD2,0x3C, ++0x95,0xF8,0x28,0x00,0x88,0x26,0x48,0xF2, ++0x0D,0x1A,0x08,0xB9,0xA4,0xF8,0x10,0xA1, ++0xA4,0xF8,0x10,0x61,0x01,0x27,0xA4,0xF8, ++0x14,0x71,0x4F,0xF4,0x00,0x7B,0xDF,0xF8, ++0xB8,0x91,0x58,0x46,0x49,0x46,0xFE,0xF7, ++0x66,0xFB,0x48,0x45,0x0E,0xD1,0xFE,0xF7, ++0xE7,0xF9,0xFE,0xF7,0x44,0xFB,0xFE,0xF7, ++0xB9,0xFB,0xB4,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA4,0xF8,0x60,0x01,0x63,0x48, ++0x25,0x38,0x3C,0xE4,0x95,0xF8,0x28,0x00, ++0x01,0x28,0x23,0xD1,0xFE,0xF7,0x6B,0xFB, ++0xD6,0x34,0x40,0xF2,0x01,0x20,0x24,0xF8, ++0xD6,0x0C,0xA4,0xF8,0x36,0x80,0xA4,0xF8, ++0x3A,0xA0,0x66,0x87,0xE7,0x87,0xD6,0x3C, ++0x4D,0x46,0x49,0x46,0x58,0x46,0xFE,0xF7, ++0x3E,0xFB,0xA8,0x42,0x0E,0xD1,0xFE,0xF7, ++0xBF,0xF9,0xFE,0xF7,0x1C,0xFB,0xFE,0xF7, ++0x91,0xFB,0xB4,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA4,0xF8,0x60,0x01,0x4F,0x48, ++0x1A,0x30,0x14,0xE4,0x01,0x20,0xFF,0xF7, ++0x43,0xFA,0xB4,0xF8,0x60,0x11,0x21,0xF0, ++0x03,0x01,0xA4,0xF8,0x60,0x11,0x0A,0xE4, ++0x10,0xB5,0xFE,0xF7,0x85,0xF8,0x41,0x8C, ++0x44,0x48,0x3A,0x30,0xA0,0xF8,0x54,0x10, ++0x08,0x21,0x01,0x80,0xDD,0x21,0x81,0x80, ++0x20,0x21,0x01,0x80,0x48,0xF6,0x10,0x01, ++0x81,0x80,0x01,0x21,0x01,0x81,0x30,0xF8, ++0x54,0x1F,0x21,0xF0,0x03,0x01,0x01,0x80, ++0x10,0xBD,0x70,0xB5,0xFE,0xF7,0x6C,0xF8, ++0xD0,0xF8,0x84,0x50,0x04,0x46,0xC0,0x6A, ++0xFE,0xF7,0xC5,0xF8,0xFE,0xF7,0x1B,0xFB, ++0x60,0x8C,0x34,0x4C,0x3A,0x34,0xA4,0xF8, ++0x54,0x00,0x20,0x20,0x20,0x80,0x48,0xF2, ++0x0D,0x10,0xA0,0x80,0x88,0x20,0xA0,0x80, ++0x01,0x20,0x20,0x81,0xA4,0xF5,0x86,0x74, ++0x2D,0x4E,0x40,0x02,0x31,0x46,0xFE,0xF7, ++0xEA,0xFA,0xB0,0x42,0x07,0xD1,0xB4,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA4,0xF8, ++0x60,0x01,0x28,0x48,0x70,0xBD,0xB4,0xF8, ++0x18,0x01,0x28,0x70,0xB4,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA4,0xF8,0x60,0x01, ++0x00,0x20,0x70,0xBD,0x02,0x46,0x1F,0x48, ++0x00,0xB5,0x7A,0x30,0x00,0x88,0x80,0x07, ++0x02,0xD5,0x4F,0xF0,0xFF,0x30,0x01,0xE0, ++0xFE,0xF7,0xB6,0xFF,0x10,0x60,0x00,0xBD, ++0x2D,0xE9,0xF0,0x41,0x06,0x46,0x0F,0x46, ++0x90,0x46,0x1D,0x46,0xFE,0xF7,0x24,0xF8, ++0xE9,0x07,0x02,0xD0,0x15,0x48,0x22,0x38, ++0x48,0xE4,0x40,0x8C,0x11,0x4C,0x24,0x1D, ++0xA4,0xF8,0x8A,0x00,0x40,0xF2,0x01,0x20, ++0x24,0xF8,0xD6,0x0C,0x00,0x21,0x2A,0x46, ++0x40,0x46,0xFF,0xF7,0x1A,0xFA,0x08,0x20, ++0xE0,0x86,0x66,0x87,0x0B,0x20,0xE0,0x86, ++0x47,0xEA,0x07,0x21,0x61,0x87,0x20,0x21, ++0xE1,0x86,0x44,0xF6,0x10,0x41,0x61,0x87, ++0x48,0xF2,0x91,0x01,0x61,0x87,0x88,0x21, ++0x61,0x87,0x19,0x21,0xE1,0x86,0x65,0x87, ++0x00,0x21,0x07,0xE0,0xD2,0x50,0x00,0x25, ++0xA0,0x86,0x01,0x00,0x35,0x00,0x00,0x80, ++0x40,0x42,0x0F,0x00,0x61,0x87,0xE0,0x87, ++0xD6,0x3C,0x0D,0x4D,0x4F,0xF4,0x00,0x70, ++0x29,0x46,0xFE,0xF7,0x84,0xFA,0xA8,0x42, ++0x10,0xD1,0x20,0x88,0xB4,0xF8,0x14,0x01, ++0xFE,0xF7,0x02,0xF9,0xFE,0xF7,0x5F,0xFA, ++0xB4,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA4,0xF8,0x60,0x01,0xFE,0xF7,0xCE,0xFA, ++0x02,0x48,0xB5,0xE7,0x00,0x20,0xB3,0xE7, ++0xA0,0x86,0x01,0x00,0x50,0x00,0x00,0x80, ++0x70,0xB5,0xFD,0xF7,0xCD,0xFF,0x4F,0xF4, ++0x80,0x61,0xFD,0x4D,0xC1,0x86,0x20,0x21, ++0x01,0x87,0x04,0x46,0x89,0x01,0x41,0x87, ++0xC9,0x10,0x81,0x87,0x0A,0x21,0xC1,0x87, ++0xFE,0xF7,0xEF,0xF9,0xFE,0xF7,0x8E,0xFC, ++0x00,0x28,0x1E,0xD1,0x21,0xE0,0x28,0x79, ++0x84,0xF8,0x31,0x00,0x68,0x79,0x84,0xF8, ++0x32,0x00,0xE8,0x88,0xA0,0x86,0x20,0x8B, ++0x20,0xF4,0x00,0x50,0x20,0x83,0x20,0x8B, ++0xE9,0x88,0x08,0x43,0x20,0x83,0xFF,0xF7, ++0x52,0xFE,0x58,0xB9,0x94,0xF8,0x31,0x00, ++0x58,0x28,0x05,0xD1,0x20,0x8B,0x80,0x04, ++0x02,0xD4,0x01,0x20,0x84,0xF8,0x33,0x00, ++0x00,0x20,0x70,0xBD,0xFE,0xF7,0xB8,0xF8, ++0x08,0x35,0x28,0x68,0x00,0x28,0xDA,0xD1, ++0xE2,0x48,0x70,0xBD,0xB1,0xF5,0x80,0x6F, ++0x04,0xDC,0x00,0x20,0x00,0xE0,0x40,0x1C, ++0x88,0x42,0xFC,0xDB,0x70,0x47,0x41,0x7B, ++0x02,0x7B,0x10,0x30,0x42,0xEA,0x01,0x21, ++0xF0,0xE7,0x00,0x22,0x02,0xE0,0x10,0xF8, ++0x01,0x3B,0x1A,0x44,0x0B,0x00,0xA1,0xF1, ++0x01,0x01,0x89,0xB2,0xF7,0xD1,0x10,0x46, ++0x70,0x47,0xF8,0xB5,0x06,0x46,0xFD,0xF7, ++0x73,0xFF,0x04,0x46,0x01,0x23,0xD0,0xE9, ++0x21,0x05,0x00,0x21,0x00,0x93,0x03,0x46, ++0x30,0x46,0x2A,0x46,0xFE,0xF7,0x70,0xF8, ++0x00,0x28,0x0C,0xD1,0x28,0x1D,0x4F,0xF4, ++0xFE,0x71,0xFF,0xF7,0xDE,0xFF,0x06,0x46, ++0x28,0x46,0x04,0xF0,0xCA,0xE8,0xB0,0x42, ++0x02,0xD0,0xC6,0x48,0x34,0x38,0xF8,0xBD, ++0x68,0x7B,0x29,0x7B,0x41,0xEA,0x00,0x22, ++0xE8,0x7B,0xA9,0x7B,0x41,0xEA,0x00,0x20, ++0x29,0x46,0x42,0x43,0xD4,0xF8,0x98,0x00, ++0x10,0x32,0x03,0xF0,0x72,0xEF,0x28,0x46, ++0xFF,0xF7,0xBD,0xFF,0x00,0x20,0xF8,0xBD, ++0x00,0x21,0x49,0x1C,0x10,0x29,0xFC,0xDB, ++0x00,0x7C,0x00,0x21,0x00,0xE0,0x49,0x1C, ++0x88,0x42,0xFC,0xDC,0x70,0x47,0x00,0x21, ++0xB5,0xA2,0x10,0xB5,0x43,0x5C,0x54,0x5C, ++0xA3,0x42,0x01,0xD0,0x01,0x20,0x10,0xBD, ++0x49,0x1C,0x10,0x29,0xF6,0xDB,0x00,0x20, ++0x10,0xBD,0x2D,0xE9,0xF0,0x4F,0x87,0xB0, ++0xFD,0xF7,0x26,0xFF,0xD0,0xF8,0x88,0x50, ++0x04,0x46,0x4F,0xF0,0x00,0x08,0x4F,0xF0, ++0x68,0x0A,0x05,0x95,0x4F,0xF0,0x54,0x0B, ++0xD0,0xF8,0x84,0x00,0x04,0x90,0x03,0x90, ++0x05,0x20,0xFF,0x21,0x01,0x90,0xA1,0x74, ++0x00,0x27,0x01,0x99,0x08,0xFA,0x01,0xF9, ++0x4F,0xF4,0x80,0x60,0x9E,0x49,0xE0,0x86, ++0x20,0x20,0x20,0x87,0x07,0xEB,0x47,0x00, ++0x30,0x31,0x31,0xF8,0x10,0x20,0x01,0xEB, ++0x40,0x00,0x62,0x87,0x41,0x88,0xA1,0x87, ++0x80,0x88,0xE0,0x87,0xFE,0xF7,0x2D,0xF9, ++0xFE,0xF7,0xB8,0xFC,0x20,0x8B,0x40,0xF4, ++0x80,0x50,0x20,0x83,0x94,0xF8,0x33,0x00, ++0x20,0xB1,0x58,0x20,0x84,0xF8,0x31,0x00, ++0x44,0x20,0x48,0xE0,0x01,0x23,0x00,0x21, ++0x00,0x93,0x48,0x46,0xDD,0xE9,0x04,0x32, ++0xFD,0xF7,0xEE,0xFF,0x06,0x00,0x1D,0xD0, ++0x60,0x8C,0x80,0x07,0x30,0xD1,0x94,0xF8, ++0x30,0x00,0x30,0xB9,0x01,0x20,0x84,0xF8, ++0x30,0x00,0xA0,0x8B,0x40,0xF4,0x00,0x40, ++0x05,0xE0,0x00,0x20,0x84,0xF8,0x30,0x00, ++0xA0,0x8B,0x20,0xF4,0x00,0x40,0xA0,0x83, ++0x01,0x23,0x00,0x93,0x00,0x21,0xDD,0xE9, ++0x04,0x32,0x48,0x46,0xFD,0xF7,0xD0,0xFF, ++0x06,0x00,0x15,0xD1,0x03,0x98,0x00,0x78, ++0xFF,0x28,0x11,0xD1,0x28,0x46,0xFF,0xF7, ++0x86,0xFF,0x68,0xB9,0x05,0x98,0x0E,0x21, ++0x24,0x30,0xFF,0xF7,0x36,0xFF,0x02,0x90, ++0x05,0xF1,0x20,0x00,0x04,0xF0,0x20,0xE8, ++0x01,0x46,0x02,0x98,0x81,0x42,0x0D,0xD0, ++0x94,0xF8,0x33,0x00,0x01,0x28,0x77,0xD1, ++0x94,0xF8,0x31,0x00,0x68,0x28,0x73,0xD0, ++0x58,0x46,0x84,0xF8,0x31,0xA0,0x84,0xF8, ++0x32,0x00,0xB3,0xE7,0x28,0x46,0xFF,0xF7, ++0x5B,0xFF,0x12,0x35,0x68,0x7D,0x29,0x7D, ++0x41,0xEA,0x00,0x20,0x60,0x87,0xE8,0x7C, ++0xA9,0x7C,0x41,0xEA,0x00,0x20,0xA0,0x87, ++0xE8,0x7D,0xA9,0x7D,0x41,0xEA,0x00,0x20, ++0x20,0x87,0x68,0x7E,0x29,0x7E,0x41,0xEA, ++0x00,0x20,0xE0,0x86,0xE8,0x7F,0xA9,0x7F, ++0x41,0xEA,0x00,0x20,0xE0,0x87,0x15,0xF8, ++0x02,0x0C,0x12,0x3D,0x60,0x74,0x05,0xF1, ++0x2C,0x00,0x06,0x90,0x03,0xF0,0xE8,0xEF, ++0x20,0x64,0x10,0x22,0x95,0xF8,0x33,0x00, ++0x95,0xF8,0x32,0x10,0x41,0xEA,0x00,0x20, ++0x05,0xF1,0x40,0x01,0xA4,0xF8,0x44,0x00, ++0x04,0xF1,0x46,0x00,0x03,0xF0,0x94,0xEE, ++0x10,0x22,0x05,0xF1,0x50,0x01,0x04,0xF1, ++0x56,0x00,0x03,0xF0,0x8E,0xEE,0x06,0x98, ++0x03,0xF0,0xCE,0xEF,0x00,0xF0,0x01,0x00, ++0x04,0xF8,0x80,0x0F,0x95,0xF8,0x60,0x00, ++0x60,0x70,0xFE,0xF7,0x8A,0xF8,0xFE,0xF7, ++0x15,0xFC,0x14,0xF8,0x80,0x09,0x00,0xBB, ++0x48,0x49,0x05,0xE0,0x01,0xEB,0x80,0x02, ++0x21,0xF8,0x20,0x00,0x50,0x80,0x40,0x1C, ++0x22,0x8F,0x82,0x42,0xF6,0xD8,0x9E,0xB9, ++0x42,0x48,0x80,0x88,0x00,0xEB,0x09,0x06, ++0x30,0x46,0xFF,0xF7,0xCA,0xFE,0x58,0xB9, ++0x94,0xF8,0x70,0x00,0xC6,0x40,0xA6,0x74, ++0xB4,0xF8,0x44,0x00,0xFD,0xF7,0xBD,0xFE, ++0x00,0x20,0x07,0xB0,0xBD,0xE8,0xF0,0x8F, ++0x10,0xE0,0x94,0xF8,0x81,0x10,0x01,0x23, ++0x01,0xEB,0x09,0x00,0xDD,0xE9,0x04,0x21, ++0xFD,0xF7,0x21,0xFF,0x30,0xB9,0x33,0x48, ++0x4F,0xF4,0x00,0x62,0x05,0x99,0x03,0xF0, ++0x4C,0xEE,0xD9,0xE7,0x7F,0x1C,0xFF,0xB2, ++0x02,0x2F,0xFF,0xF4,0x0D,0xAF,0x08,0xF1, ++0x01,0x00,0x1F,0xFA,0x80,0xF8,0xB8,0xF1, ++0x40,0x0F,0xFF,0xF4,0x01,0xAF,0x23,0x48, ++0x11,0x38,0xDA,0xE7,0x10,0xB5,0x04,0x46, ++0xFD,0xF7,0x0E,0xFE,0x90,0xF8,0x70,0x00, ++0x04,0xFA,0x00,0xF0,0xBD,0xE8,0x10,0x40, ++0xFF,0xF7,0xFC,0xBC,0x70,0xB5,0x06,0x46, ++0xA0,0xB0,0xFD,0xF7,0x01,0xFE,0xD0,0xF8, ++0x88,0x50,0x04,0x46,0x30,0x46,0xFF,0xF7, ++0xE9,0xFF,0x80,0x21,0x68,0x46,0x03,0xF0, ++0xAC,0xEE,0x94,0xF8,0x70,0x00,0x01,0x23, ++0x6A,0x46,0x29,0x46,0x86,0x40,0x30,0x46, ++0xFD,0xF7,0xDE,0xFE,0x20,0x8F,0x76,0x1E, ++0x01,0x23,0x6A,0x46,0x30,0x44,0x29,0x46, ++0xFD,0xF7,0xD6,0xFE,0x20,0xB0,0x70,0xBD, ++0x2D,0xE9,0xFC,0x5F,0x80,0x46,0xFD,0xF7, ++0xDF,0xFD,0x81,0x46,0xD0,0xF8,0x88,0x00, ++0x00,0x25,0x01,0x90,0xD9,0xF8,0x40,0x00, ++0xD9,0xF8,0x84,0x40,0xC0,0xF3,0x42,0x06, ++0xC0,0xF3,0xC0,0x1A,0x73,0xE0,0x00,0x00, ++0x48,0xEC,0x03,0x20,0x3A,0x00,0x00,0x80, ++0x4D,0x53,0x54,0x41,0x52,0x53,0x45,0x4D, ++0x49,0x55,0x4E,0x46,0x44,0x43,0x49,0x53, ++0x00,0x00,0x00,0x00,0x00,0x0D,0x03,0x20, ++0x4F,0xF0,0x00,0x0B,0x5F,0x46,0x99,0xF8, ++0x70,0x00,0x01,0x23,0x01,0x9A,0x00,0x93, ++0x00,0x21,0x05,0xFA,0x00,0xF0,0x23,0x46, ++0x38,0x44,0xFD,0xF7,0xB9,0xFE,0xBA,0xF1, ++0x00,0x0F,0x01,0xD1,0xA0,0x5D,0x06,0xE0, ++0x14,0xF8,0x16,0x00,0xFF,0x28,0x25,0xD1, ++0x04,0xEB,0x46,0x00,0x40,0x78,0xFF,0x28, ++0x20,0xD1,0x99,0xF8,0x70,0x10,0x68,0x1C, ++0x01,0x23,0x01,0x9A,0x88,0x40,0x00,0x93, ++0xC0,0x1B,0x00,0x21,0x40,0x1E,0x23,0x46, ++0xFD,0xF7,0x9E,0xFE,0xBA,0xF1,0x00,0x0F, ++0x01,0xD1,0xA0,0x5D,0x06,0xE0,0x14,0xF8, ++0x16,0x00,0xFF,0x28,0x0A,0xD1,0x04,0xEB, ++0x46,0x00,0x40,0x78,0xFF,0x28,0x05,0xD1, ++0x7F,0x1C,0x03,0x2F,0xC7,0xD3,0xBB,0xF1, ++0x01,0x0F,0x23,0xD1,0x98,0xF8,0x05,0x10, ++0x98,0xF8,0x04,0x20,0x42,0xEA,0x01,0x20, ++0xFA,0x28,0x0C,0xD8,0x08,0xEB,0x40,0x00, ++0x29,0x0A,0x85,0x71,0x98,0xF8,0x05,0x20, ++0x98,0xF8,0x04,0x30,0x43,0xEA,0x02,0x20, ++0x08,0xEB,0x40,0x00,0xC1,0x71,0x98,0xF8, ++0x05,0x10,0x98,0xF8,0x04,0x20,0x42,0xEA, ++0x01,0x20,0x40,0x1C,0x88,0xF8,0x04,0x00, ++0x00,0x0A,0x88,0xF8,0x05,0x00,0xA8,0xB2, ++0xFF,0xF7,0x58,0xFF,0x6D,0x1C,0xB9,0xF8, ++0x36,0x00,0xA8,0x42,0x98,0xD8,0x4F,0xF4, ++0xFE,0x71,0x08,0xF1,0x04,0x00,0xFF,0xF7, ++0xD0,0xFD,0x41,0x46,0x03,0xF0,0xCC,0xEE, ++0x00,0x20,0xBD,0xE8,0xFC,0x9F,0xFF,0x49, ++0x40,0x1E,0x01,0x42,0x01,0xD0,0xFE,0x48, ++0x70,0x47,0x00,0x20,0x70,0x47,0x00,0x22, ++0x08,0xE0,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x10,0x32,0x8A,0x42,0xF4,0xDB, ++0x70,0x47,0x70,0x47,0x70,0x47,0x00,0x21, ++0x02,0xE0,0x49,0x1C,0x40,0x08,0xC9,0xB2, ++0x00,0x28,0xFA,0xD1,0x49,0x1E,0xC8,0xB2, ++0x70,0x47,0x70,0xB5,0x04,0x46,0x0D,0x46, ++0xFD,0xF7,0x26,0xFD,0xD0,0xF8,0x98,0x00, ++0x41,0x7B,0x02,0x7B,0x42,0xEA,0x01,0x21, ++0x08,0xE0,0x62,0x79,0x23,0x79,0x43,0xEA, ++0x02,0x22,0xAA,0x42,0x01,0xD1,0x20,0x46, ++0x70,0xBD,0x08,0x34,0x22,0x1A,0x10,0x3A, ++0xB1,0xEB,0xE2,0x0F,0xF1,0xDC,0x00,0x20, ++0x70,0xBD,0x38,0xB5,0x05,0x46,0xFD,0xF7, ++0x0B,0xFD,0x70,0x30,0x01,0x23,0x01,0x78, ++0xD0,0xE9,0x05,0x42,0x05,0xFA,0x01,0xF0, ++0x00,0x93,0x00,0x21,0x23,0x46,0xFD,0xF7, ++0x07,0xFE,0x20,0x78,0xFF,0x28,0x01,0xD0, ++0x00,0x20,0x38,0xBD,0x01,0x20,0x38,0xBD, ++0x00,0x22,0x05,0xE0,0x83,0x5C,0xFF,0x2B, ++0x01,0xD0,0x00,0x20,0x70,0x47,0x52,0x1C, ++0x8A,0x42,0xF7,0xD3,0xFF,0x20,0x70,0x47, ++0xF8,0xB5,0x05,0x46,0xFD,0xF7,0xE8,0xFC, ++0x90,0xF8,0x70,0x10,0x01,0x23,0xD0,0xE9, ++0x21,0x76,0x04,0x46,0x05,0xFA,0x01,0xF0, ++0x00,0x93,0x00,0x21,0x3B,0x46,0x32,0x46, ++0xFD,0xF7,0xE2,0xFD,0xC0,0xB9,0xB4,0xF8, ++0x6C,0x10,0x38,0x46,0xFF,0xF7,0xDC,0xFF, ++0xFF,0x28,0x11,0xD1,0x6C,0x34,0x68,0x1C, ++0x01,0x23,0x21,0x79,0x32,0x46,0x00,0x93, ++0x3B,0x46,0x88,0x40,0x00,0x21,0x40,0x1E, ++0xFD,0xF7,0xCE,0xFD,0x21,0x88,0x38,0x46, ++0xFF,0xF7,0xCA,0xFF,0xFF,0x28,0x01,0xD0, ++0x00,0x20,0xF8,0xBD,0x01,0x20,0xF8,0xBD, ++0x2D,0xE9,0xF8,0x4F,0x80,0x46,0xFD,0xF7, ++0xB7,0xFC,0xD0,0xE9,0x21,0xA9,0x05,0x46, ++0x90,0xF8,0x70,0x00,0x00,0x21,0x0E,0x46, ++0x08,0xFA,0x00,0xF2,0x28,0x8F,0x02,0xEB, ++0x50,0x04,0x1E,0xE0,0x01,0x23,0x00,0x21, ++0x00,0x93,0x53,0x46,0x4A,0x46,0x20,0x46, ++0xFD,0xF7,0xAA,0xFD,0xB5,0xF8,0x6C,0x10, ++0x07,0x46,0x50,0x46,0xFF,0xF7,0xA4,0xFF, ++0xFF,0x28,0x07,0xD1,0x37,0xB9,0x28,0x8F, ++0xB2,0x1C,0x4F,0xF0,0xFF,0x31,0xD0,0x40, ++0x24,0x1A,0x04,0xE0,0x28,0x8F,0xB2,0x1C, ++0x01,0x21,0xD0,0x40,0x04,0x44,0x76,0x1C, ++0xF6,0xB2,0x95,0xF8,0x70,0x00,0x40,0x1E, ++0xB0,0x42,0xDB,0xDC,0x95,0xF8,0x70,0x00, ++0x00,0x29,0x47,0x46,0x18,0xDA,0x87,0x40, ++0x01,0x23,0x00,0x93,0x00,0x21,0x53,0x46, ++0x4A,0x46,0x20,0x46,0xFD,0xF7,0x80,0xFD, ++0xB5,0xF8,0x6C,0x10,0x06,0x46,0x50,0x46, ++0xFF,0xF7,0x7A,0xFF,0xFF,0x28,0x03,0xD1, ++0x16,0xB9,0x64,0x1E,0xBC,0x42,0xEB,0xD2, ++0xB5,0xF8,0x76,0x00,0x64,0x1C,0x14,0xE0, ++0x7F,0x1C,0x87,0x40,0x01,0x23,0x00,0x93, ++0x00,0x21,0x53,0x46,0x4A,0x46,0x20,0x46, ++0xFD,0xF7,0x66,0xFD,0xB5,0xF8,0x6C,0x10, ++0x06,0x46,0x50,0x46,0xFF,0xF7,0x60,0xFF, ++0xFF,0x28,0x06,0xD1,0x2E,0xB9,0xB5,0xF8, ++0x76,0x00,0x20,0x40,0xC0,0xB2,0xBD,0xE8, ++0xF8,0x8F,0x64,0x1C,0xBC,0x42,0xE5,0xD3, ++0x4F,0xF6,0xFF,0x70,0xF7,0xE7,0x2D,0xE9, ++0xF0,0x5F,0x83,0x46,0x0C,0x46,0x90,0x46, ++0xFD,0xF7,0x42,0xFC,0x70,0x30,0xD0,0xE9, ++0x05,0x9A,0x00,0x78,0x84,0x40,0x0B,0xFA, ++0x00,0xF1,0xA6,0xB2,0x8F,0xB2,0x00,0x24, ++0x17,0xE0,0x30,0x19,0x01,0x23,0x4A,0x46, ++0x51,0x46,0xFD,0xF7,0x28,0xFD,0x00,0x28, ++0x0B,0xD1,0x38,0x19,0x01,0x23,0x4A,0x46, ++0x51,0x46,0xFD,0xF7,0x19,0xFD,0x05,0x00, ++0x05,0xD0,0x58,0x46,0xFF,0xF7,0x1E,0xFE, ++0x28,0x46,0xBD,0xE8,0xF0,0x9F,0x64,0x1C, ++0xA4,0xB2,0x44,0x45,0xE5,0xD3,0x00,0x20, ++0xF7,0xE7,0x2D,0xE9,0xF8,0x4F,0x81,0x46, ++0x93,0x46,0xDD,0xE9,0x0A,0x45,0xFD,0xF7, ++0x13,0xFC,0x06,0x46,0xD0,0xF8,0x88,0x00, ++0x00,0x90,0x70,0x8F,0x4F,0xEA,0x50,0x2A, ++0x50,0x46,0xFF,0xF7,0xD4,0xFE,0x01,0x21, ++0x07,0x46,0x81,0x40,0x49,0x1E,0x89,0xB2, ++0x04,0xEA,0x01,0x00,0x5F,0xEA,0x00,0x08, ++0x26,0xD0,0x96,0xF8,0x70,0x10,0x59,0x4A, ++0x01,0x23,0x0B,0xFA,0x01,0xF0,0x24,0xFA, ++0x07,0xF1,0x32,0xF8,0x21,0x10,0x00,0x22, ++0x08,0x44,0x00,0x99,0xFD,0xF7,0xE7,0xFC, ++0x00,0x28,0x9C,0xD1,0xAA,0xEB,0x08,0x02, ++0xAA,0x42,0x40,0x46,0x29,0x46,0x00,0xD2, ++0x11,0x46,0x1F,0xFA,0x81,0xF8,0x00,0x99, ++0x4F,0xEA,0x48,0x22,0x01,0xEB,0x40,0x21, ++0x48,0x46,0x03,0xF0,0x06,0xEC,0x09,0xEB, ++0x48,0x29,0x44,0x44,0xA5,0xEB,0x08,0x05, ++0x96,0xF8,0x70,0x00,0x45,0x49,0x0B,0xFA, ++0x00,0xF2,0x24,0xFA,0x07,0xF0,0x31,0xF8, ++0x20,0x00,0x10,0x44,0x25,0xFA,0x07,0xF2, ++0x1F,0xFA,0x82,0xF8,0x19,0xE0,0x01,0x23, ++0x00,0x22,0x49,0x46,0xFD,0xF7,0xBB,0xFC, ++0x00,0x28,0x2C,0xD1,0x70,0x8F,0x54,0x44, ++0x3A,0x4A,0x81,0x44,0xA8,0xF1,0x01,0x00, ++0xA5,0xEB,0x0A,0x05,0x1F,0xFA,0x80,0xF8, ++0x96,0xF8,0x70,0x00,0x0B,0xFA,0x00,0xF1, ++0x24,0xFA,0x07,0xF0,0x32,0xF8,0x20,0x00, ++0x08,0x44,0xB8,0xF1,0x00,0x0F,0xE2,0xD1, ++0xA5,0xB1,0x96,0xF8,0x70,0x10,0x01,0x23, ++0x00,0x22,0x0B,0xFA,0x01,0xF0,0x2D,0x49, ++0xFC,0x40,0x31,0xF8,0x24,0x10,0x08,0x44, ++0x00,0x99,0xFD,0xF7,0x94,0xFC,0x00,0x28, ++0x05,0xD1,0x00,0x99,0x6A,0x02,0x48,0x46, ++0x03,0xF0,0xBE,0xEB,0x00,0x20,0x42,0xE7, ++0x2D,0xE9,0xFF,0x4F,0x83,0x46,0x83,0xB0, ++0xDD,0xE9,0x10,0x56,0xFD,0xF7,0x8C,0xFB, ++0x04,0x46,0xD0,0xF8,0x88,0x00,0x02,0x90, ++0xD4,0xF8,0x84,0x00,0x01,0x90,0x60,0x8F, ++0x4F,0xEA,0x50,0x29,0x48,0x46,0xFF,0xF7, ++0x4A,0xFE,0xA1,0x8F,0x82,0x46,0x01,0x98, ++0xFF,0x22,0x03,0xF0,0x9A,0xEB,0x94,0xF8, ++0x70,0x00,0x05,0x9A,0x15,0x49,0x82,0x40, ++0x25,0xFA,0x0A,0xF0,0x31,0xF8,0x20,0x00, ++0x02,0xEB,0x00,0x08,0x26,0xFA,0x0A,0xF0, ++0x87,0xB2,0x19,0xE0,0x01,0x9A,0x01,0x23, ++0x59,0x46,0x40,0x46,0xFD,0xF7,0x54,0xFC, ++0x00,0x28,0x2E,0xD1,0x60,0x8F,0x94,0xF8, ++0x70,0x10,0x7F,0x1E,0x83,0x44,0x05,0x98, ++0x4D,0x44,0x08,0x4A,0xBF,0xB2,0x88,0x40, ++0xA6,0xEB,0x09,0x06,0x25,0xFA,0x0A,0xF1, ++0x32,0xF8,0x21,0x10,0x00,0xEB,0x01,0x08, ++0x00,0x2F,0x05,0xE0,0x00,0x15,0x03,0x20, ++0x48,0x00,0x00,0x80,0x00,0x0D,0x03,0x20, ++0xDC,0xD1,0x8E,0xB1,0x61,0x8F,0xFF,0x22, ++0x02,0x98,0x03,0xF0,0x62,0xEB,0x02,0x98, ++0x72,0x02,0x59,0x46,0x03,0xF0,0x64,0xEB, ++0xDD,0xE9,0x01,0x21,0x01,0x23,0x40,0x46, ++0xFD,0xF7,0x26,0xFC,0x00,0x28,0x00,0xD1, ++0x00,0x20,0xFA,0xE4,0x2D,0xE9,0xFF,0x4F, ++0x0E,0x46,0x85,0xB0,0x17,0x46,0x99,0x46, ++0xDD,0xF8,0x48,0xA0,0xFD,0xF7,0x28,0xFB, ++0x04,0x46,0xD0,0xE9,0x21,0x05,0x03,0x90, ++0x94,0xF8,0x80,0x00,0xB4,0xF8,0x38,0x80, ++0x01,0x28,0x01,0xD1,0x4F,0xEA,0x58,0x08, ++0x60,0x8F,0x40,0x0A,0xFF,0xF7,0xE3,0xFD, ++0x01,0x21,0x83,0x46,0x81,0x40,0x49,0x1E, ++0x89,0xB2,0x1A,0xEA,0x01,0x00,0x04,0x90, ++0x2F,0xD1,0x56,0x4A,0x2A,0xFA,0x0B,0xF1, ++0x94,0xF8,0x70,0x00,0x01,0x23,0x32,0xF8, ++0x21,0x10,0x07,0xFA,0x00,0xF0,0x03,0x9A, ++0x08,0x44,0x29,0x46,0xFD,0xF7,0xF7,0xFB, ++0x00,0x28,0x1C,0xD1,0xA1,0x8F,0x05,0xE0, ++0x03,0x9A,0x12,0x5C,0xFF,0x2A,0x18,0xD1, ++0x40,0x1C,0x80,0xB2,0x81,0x42,0xF7,0xD8, ++0x61,0x8F,0x00,0x20,0x04,0xE0,0x2A,0x5C, ++0xFF,0x2A,0x0E,0xD1,0x40,0x1C,0x80,0xB2, ++0x81,0x42,0xF8,0xD8,0x13,0x9B,0x3A,0x46, ++0x31,0x46,0xCD,0xE9,0x00,0xA3,0x4B,0x46, ++0x05,0x98,0xFF,0xF7,0x4D,0xFF,0x09,0xB0, ++0xA8,0xE4,0x3F,0x4E,0x2A,0xFA,0x0B,0xF9, ++0x04,0x98,0x08,0xB1,0x09,0xF1,0x01,0x09, ++0x00,0x25,0x14,0xE0,0x39,0x49,0x01,0x23, ++0x94,0xF8,0x70,0x00,0x00,0x22,0x31,0xF8, ++0x25,0x10,0x07,0xFA,0x00,0xF0,0x08,0x44, ++0x94,0xF8,0x72,0x10,0x05,0xFA,0x01,0xF1, ++0x31,0x44,0xFD,0xF7,0xBC,0xFB,0x00,0x28, ++0xE1,0xD1,0x6D,0x1C,0xAD,0xB2,0x4D,0x45, ++0xE8,0xD3,0x13,0x99,0xDF,0xF8,0xB4,0x90, ++0x0A,0xEB,0x01,0x00,0x20,0xFA,0x0B,0xF0, ++0x85,0xB2,0x13,0xE0,0x94,0xF8,0x70,0x00, ++0x01,0x23,0x39,0xF8,0x25,0x10,0x00,0x22, ++0x07,0xFA,0x00,0xF0,0x08,0x44,0x94,0xF8, ++0x72,0x10,0x05,0xFA,0x01,0xF1,0x31,0x44, ++0xFD,0xF7,0x9D,0xFB,0x00,0x28,0xC2,0xD1, ++0x6D,0x1C,0xAD,0xB2,0x45,0x45,0xE9,0xD3, ++0x13,0x98,0x05,0x99,0x42,0x02,0x06,0xEB, ++0x4A,0x20,0x03,0xF0,0xC2,0xEA,0x38,0x46, ++0xFF,0xF7,0x84,0xFC,0x05,0x00,0x04,0xD0, ++0x38,0x46,0xFF,0xF7,0x8B,0xFC,0x28,0x46, ++0xAD,0xE7,0xA1,0x8F,0xFF,0x22,0x03,0x98, ++0x03,0xF0,0xAA,0xEA,0x00,0x25,0xCA,0x46, ++0x19,0xE0,0x94,0xF8,0x70,0x00,0x01,0x23, ++0x3A,0xF8,0x25,0x10,0x03,0x9A,0x07,0xFA, ++0x00,0xF0,0x08,0x44,0x94,0xF8,0x72,0x10, ++0x05,0xFA,0x01,0xF1,0x31,0x44,0xFD,0xF7, ++0x67,0xFB,0x5F,0xEA,0x00,0x09,0x04,0xD0, ++0x38,0x46,0xFF,0xF7,0x6B,0xFC,0x48,0x46, ++0x8D,0xE7,0x6D,0x1C,0xAD,0xB2,0x45,0x45, ++0xE3,0xD3,0x00,0x20,0x87,0xE7,0x01,0x23, ++0xFD,0xF7,0x5D,0xBB,0x01,0x23,0xFD,0xF7, ++0x53,0xBB,0x00,0x00,0x00,0x0D,0x03,0x20, ++0x00,0x00,0x20,0x80,0x10,0xB5,0x04,0x46, ++0xF8,0xF7,0xC0,0xFA,0x20,0x46,0x10,0xBD, ++0x00,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0xB7,0x48,0x40,0x68,0x00,0xF4,0x40,0x70, ++0xB0,0xF5,0x80,0x7F,0x06,0xD0,0xB0,0xF5, ++0x00,0x7F,0x03,0xD0,0xB0,0xF5,0x40,0x7F, ++0x00,0xD0,0xFE,0xE7,0x00,0x20,0x80,0x1C, ++0xC0,0xB2,0x08,0x28,0xFB,0xD3,0x70,0x47, ++0xDF,0xF8,0xB8,0xC2,0xF0,0xB5,0xDC,0xF8, ++0x08,0x10,0x81,0x42,0x01,0xD1,0x00,0x20, ++0xF0,0xBD,0xA9,0x4B,0x01,0x28,0xAA,0x4A, ++0xAA,0x4C,0x59,0x68,0x21,0xF4,0x40,0x71, ++0x59,0x60,0x15,0xD0,0x02,0x28,0x25,0xD0, ++0x03,0x28,0x59,0xD1,0x32,0xF8,0xBC,0x5F, ++0x25,0xF4,0x00,0x75,0x15,0x80,0x15,0x88, ++0x45,0xF4,0xE8,0x55,0x15,0x80,0xB4,0xF8, ++0x80,0x20,0x42,0xF0,0x02,0x02,0xA4,0xF8, ++0x80,0x20,0x41,0xF4,0x40,0x71,0x22,0xE0, ++0x32,0xF8,0xBC,0x5F,0x25,0xF4,0xF8,0x55, ++0x15,0x80,0x15,0x88,0x45,0xF4,0x40,0x75, ++0x15,0x80,0xB4,0xF8,0x80,0x20,0x22,0xF0, ++0x02,0x02,0xA4,0xF8,0x80,0x20,0x41,0xF4, ++0x80,0x71,0x10,0xE0,0x32,0xF8,0xBC,0x5F, ++0x25,0xF4,0xF8,0x55,0x15,0x80,0x15,0x88, ++0x45,0xF4,0x80,0x75,0x15,0x80,0xB4,0xF8, ++0x80,0x20,0x22,0xF0,0x02,0x02,0xA4,0xF8, ++0x80,0x20,0x41,0xF4,0x00,0x71,0x59,0x60, ++0x34,0xF8,0xD0,0x1F,0x41,0xF0,0x02,0x01, ++0x21,0x80,0x89,0x49,0x0A,0x88,0x22,0xF4, ++0x00,0x42,0x0A,0x80,0x87,0x4E,0xB1,0x88, ++0x41,0xF0,0xB2,0x01,0xB1,0x80,0xB1,0x88, ++0x21,0xF0,0x04,0x01,0xB1,0x80,0x31,0x88, ++0x43,0xF2,0x16,0x62,0x11,0x43,0x31,0x80, ++0x31,0x88,0x47,0xF6,0x5F,0x72,0x11,0x40, ++0x31,0x80,0x00,0x21,0x80,0x27,0xA6,0xF6, ++0xC8,0x56,0x4F,0xF0,0x34,0x0E,0x01,0xE0, ++0x7B,0x48,0xF0,0xBD,0x4A,0x08,0x06,0xEB, ++0x82,0x02,0xB2,0xF8,0xA8,0x4D,0xCB,0x07, ++0x00,0x2B,0x01,0xD0,0x4F,0xF0,0x08,0x03, ++0x0E,0xFA,0x03,0xF5,0x44,0xEA,0x05,0x04, ++0xA2,0xF8,0xA8,0x4D,0xB2,0xF8,0xA8,0x4D, ++0x02,0xD0,0x4F,0xF0,0x08,0x03,0x00,0xE0, ++0x00,0x23,0x07,0xFA,0x03,0xF3,0x9C,0x43, ++0xA2,0xF8,0xA8,0x4D,0x49,0x1C,0xC9,0xB2, ++0x08,0x29,0xDF,0xD3,0xCC,0xF8,0x08,0x00, ++0x71,0xE7,0x6A,0x48,0xB0,0xF8,0xB4,0x11, ++0x21,0xF0,0x02,0x01,0xA0,0xF8,0xB4,0x11, ++0x01,0x88,0x21,0xF0,0x02,0x01,0x20,0xF8, ++0x40,0x1B,0x01,0x88,0x21,0xF0,0x02,0x01, ++0x01,0x80,0x00,0x20,0x70,0x47,0x61,0x48, ++0xB0,0xF8,0xB4,0x11,0x41,0xF0,0x02,0x01, ++0xA0,0xF8,0xB4,0x11,0x01,0x88,0x41,0xF0, ++0x02,0x01,0x20,0xF8,0x40,0x1B,0x01,0x88, ++0x41,0xF0,0x02,0x01,0x01,0x80,0x00,0x20, ++0x70,0x47,0x10,0xB5,0x02,0x46,0xFF,0xF7, ++0xEA,0xFF,0x4F,0x48,0x0E,0x2A,0x42,0xD2, ++0xDF,0xE8,0x02,0xF0,0x0A,0x2C,0x2F,0x32, ++0x35,0x38,0x3B,0x3E,0x41,0x41,0x41,0x41, ++0x41,0x07,0x4F,0xF4,0x96,0x71,0x01,0xE0, ++0x42,0xF6,0xE0,0x61,0x00,0x23,0x01,0x64, ++0x4D,0x49,0x0B,0x80,0x0B,0x88,0x44,0xF2, ++0x40,0x04,0x23,0x43,0x0B,0x80,0x0B,0x88, ++0x42,0xEA,0x02,0x24,0x23,0x43,0x0B,0x80, ++0x80,0xF8,0x44,0x20,0xB1,0xF8,0x20,0x0C, ++0x20,0xF0,0x08,0x00,0xA1,0xF8,0x20,0x0C, ++0xB1,0xF8,0xCC,0x0C,0x40,0xF0,0x40,0x00, ++0xA1,0xF8,0xCC,0x0C,0xFF,0xF7,0xA9,0xFF, ++0x00,0x20,0x10,0xBD,0x4F,0xF4,0x96,0x41, ++0xDC,0xE7,0x45,0xF6,0xC0,0x51,0xD9,0xE7, ++0x46,0xF6,0x08,0x31,0xD6,0xE7,0x4F,0xF4, ++0xFA,0x41,0xD3,0xE7,0x4F,0xF4,0x16,0x41, ++0xD0,0xE7,0x4A,0xF2,0x68,0x61,0xCD,0xE7, ++0x4B,0xF6,0x80,0x31,0xCA,0xE7,0x32,0x48, ++0x10,0xBD,0x70,0x47,0x70,0x47,0x10,0xB5, ++0x04,0x46,0xF8,0xF7,0xEC,0xEE,0x20,0x46, ++0x10,0xBD,0x70,0x47,0x70,0x47,0x2F,0x48, ++0x26,0x49,0x00,0xB5,0x00,0x68,0xC8,0x60, ++0x00,0xF5,0x00,0x70,0x08,0x61,0x02,0x20, ++0xFF,0xF7,0xE6,0xFE,0x0D,0x20,0xFF,0xF7, ++0x9C,0xFF,0x00,0x20,0x00,0xBD,0x30,0xB4, ++0xA1,0xF5,0x40,0x41,0x03,0x39,0x02,0x9C, ++0x06,0xD0,0x04,0x29,0x03,0xD0,0x05,0x29, ++0x08,0xD1,0x79,0x32,0x00,0xE0,0xB9,0x32, ++0x59,0x02,0x01,0x2C,0x05,0xD1,0x30,0xBC, ++0xFB,0xF7,0xA9,0xB9,0x30,0xBC,0x00,0x20, ++0x70,0x47,0x30,0xBC,0xFB,0xF7,0x00,0xBA, ++0xA0,0xF5,0x40,0x40,0x03,0x38,0x06,0xD0, ++0x04,0x28,0x07,0xD0,0x05,0x28,0x09,0xD1, ++0x79,0x20,0xB8,0x21,0x04,0xE0,0x00,0x20, ++0x78,0x21,0x01,0xE0,0xB9,0x20,0xC0,0x21, ++0xFB,0xF7,0x12,0xB9,0x00,0x20,0x70,0x47, ++0x08,0x48,0x01,0x68,0xA1,0xF5,0x25,0x42, ++0x5A,0x3A,0x04,0xD1,0x40,0x68,0xA0,0xF5, ++0x90,0x51,0x89,0x39,0x02,0xD0,0x08,0x48, ++0x14,0x38,0x70,0x47,0x00,0x20,0x70,0x47, ++0x20,0x15,0x03,0x20,0x74,0x05,0x03,0x20, ++0x00,0x50,0x00,0x25,0x00,0x70,0x00,0x25, ++0x14,0x2C,0x02,0x25,0xC8,0x0D,0x02,0x25, ++0x15,0x00,0x00,0x80,0x18,0x7C,0x00,0x25, ++0x40,0x72,0x00,0x25,0xAC,0x04,0x03,0x20, ++0x2D,0xE9,0xF0,0x41,0x00,0x24,0x06,0x46, ++0x0F,0x46,0x15,0x46,0x07,0xE0,0x01,0x20, ++0xFF,0xF7,0x68,0xFE,0x30,0x88,0x37,0xEA, ++0x00,0x00,0x02,0xD0,0x64,0x1C,0xAC,0x42, ++0xF5,0xD3,0xAC,0x42,0x02,0xD1,0xFD,0x48, ++0xBD,0xE8,0xF0,0x81,0x00,0x20,0xFB,0xE7, ++0xE6,0xE7,0xFB,0x48,0xFF,0x22,0x10,0xB5, ++0x00,0x24,0xC8,0x21,0x03,0xF0,0xD0,0xE8, ++0xF7,0x4B,0x00,0x20,0xF7,0x49,0x31,0xF8, ++0xC0,0x2F,0x22,0xF4,0xE0,0x62,0x0A,0x80, ++0x0A,0x88,0x42,0xEA,0x00,0x22,0x0A,0x80, ++0x0A,0x88,0x23,0xF8,0x14,0x20,0x64,0x1C, ++0xA2,0xB2,0x8C,0x88,0x40,0x1C,0x23,0xF8, ++0x12,0x40,0x52,0x1C,0x80,0xB2,0x94,0xB2, ++0xC0,0x39,0x08,0x28,0xE7,0xD3,0x00,0x20, ++0xC6,0x31,0xCA,0x8F,0x22,0xF4,0xE0,0x42, ++0xCA,0x87,0xCA,0x8F,0x42,0xEA,0x00,0x32, ++0xCA,0x87,0x31,0xF8,0x06,0x2C,0x23,0xF8, ++0x14,0x20,0x64,0x1C,0xA2,0xB2,0xCC,0x8F, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x31,0xF8, ++0x02,0x4C,0x92,0xB2,0x40,0x1C,0xC6,0x39, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x80,0xB2, ++0x94,0xB2,0x08,0x28,0xE0,0xD3,0x10,0xBD, ++0xDA,0x4B,0x00,0x20,0x10,0xB5,0x07,0xE0, ++0x03,0xEB,0x80,0x04,0xB4,0xF8,0x00,0x42, ++0x22,0xF8,0x10,0x40,0x40,0x1C,0x80,0xB2, ++0x88,0x42,0xF5,0xD3,0x10,0xBD,0xD3,0x49, ++0x00,0x20,0x00,0xB5,0x31,0xF8,0x20,0x20, ++0x40,0x1C,0x80,0xB2,0x60,0x28,0xF9,0xD3, ++0x20,0x21,0xCD,0x4A,0x00,0x20,0xC8,0x32, ++0xFF,0xF7,0xE2,0xFF,0x00,0x20,0x40,0x1C, ++0x80,0xB2,0x20,0x28,0xFB,0xD3,0x00,0xBD, ++0xC8,0x49,0x08,0x89,0x40,0xF0,0x10,0x00, ++0x08,0x81,0x4C,0xF6,0x07,0x02,0x0A,0x80, ++0x08,0x88,0x10,0x42,0xFB,0xD1,0xB1,0xF8, ++0x48,0x00,0x40,0xF0,0x1F,0x00,0xA1,0xF8, ++0x48,0x00,0x08,0x89,0x20,0xF0,0x10,0x00, ++0x08,0x81,0x70,0x47,0x3C,0xB5,0x45,0xF2, ++0x55,0x55,0xBC,0x4B,0x6C,0x46,0x6A,0x00, ++0x00,0x20,0x03,0xEB,0x80,0x01,0xA1,0xF8, ++0x00,0x52,0xB1,0xF8,0x00,0x12,0x24,0xF8, ++0x10,0x10,0x40,0x1C,0x80,0xB2,0x03,0x28, ++0xF3,0xD3,0x00,0x20,0x34,0xF8,0x10,0x10, ++0xA9,0x42,0x03,0xD1,0x40,0x1C,0x80,0xB2, ++0x03,0x28,0xF7,0xD3,0x03,0x28,0xE7,0xD1, ++0x00,0x20,0x03,0xEB,0x80,0x01,0xA1,0xF8, ++0x00,0x22,0xB1,0xF8,0x00,0x12,0x24,0xF8, ++0x10,0x10,0x40,0x1C,0x80,0xB2,0x03,0x28, ++0xF3,0xD3,0x00,0x20,0x34,0xF8,0x10,0x10, ++0x91,0x42,0x03,0xD1,0x40,0x1C,0x80,0xB2, ++0x03,0x28,0xF7,0xD3,0x03,0x28,0xE7,0xD1, ++0x3C,0xBD,0x2D,0xE9,0xF0,0x47,0x00,0x27, ++0xA0,0x48,0x01,0x89,0x41,0xF0,0x10,0x01, ++0x01,0x81,0x3D,0x46,0xDF,0xF8,0x78,0x82, ++0x81,0x46,0x45,0xF2,0x55,0x56,0xA9,0xF8, ++0x00,0x62,0xB9,0xF8,0x00,0x02,0x60,0xF3, ++0x0F,0x04,0xA0,0xB2,0xB0,0x42,0x05,0xD0, ++0x01,0x20,0xFF,0xF7,0x8B,0xFD,0x6D,0x1C, ++0x45,0x45,0xF0,0xD3,0x45,0x45,0xDF,0xF8, ++0x44,0xA2,0x0A,0xF1,0x0D,0x0A,0x15,0xD0, ++0xB9,0xF8,0xC0,0x10,0x21,0xF4,0x80,0x51, ++0xA9,0xF8,0xC0,0x10,0x00,0x25,0xB9,0xF8, ++0x00,0x02,0x60,0xF3,0x0F,0x04,0xA0,0xB2, ++0xB0,0x42,0x05,0xD1,0x01,0x20,0xFF,0xF7, ++0x71,0xFD,0x6D,0x1C,0x45,0x45,0xF2,0xD3, ++0x45,0x45,0x00,0xD1,0x57,0x46,0xB9,0xF8, ++0xC0,0x00,0x4C,0x46,0x40,0xF4,0x80,0x50, ++0xA9,0xF8,0xC0,0x00,0xFF,0xF7,0x86,0xFF, ++0x20,0x89,0x20,0xF0,0x10,0x00,0x20,0x81, ++0x38,0x46,0xBD,0xE8,0xF0,0x87,0x10,0xB5, ++0xFF,0xF7,0x1D,0xFE,0x7B,0x48,0x00,0x21, ++0x00,0x1D,0x01,0x80,0x4F,0xF4,0x00,0x42, ++0x82,0x80,0x02,0x22,0x82,0x84,0x05,0x22, ++0x82,0x86,0xA0,0xF8,0x40,0x10,0x81,0x87, ++0x4F,0xF4,0x02,0x42,0xA0,0xF8,0x68,0x20, ++0xA0,0xF8,0xD0,0x10,0xFF,0xF7,0x9D,0xFF, ++0x00,0x28,0x04,0xD1,0xFF,0xF7,0x4C,0xFF, ++0xFF,0xF7,0xEF,0xFD,0x00,0x20,0x10,0xBD, ++0x6E,0x48,0x10,0xB5,0x40,0x68,0xC0,0x06, ++0x07,0xD4,0xFA,0xF7,0xA8,0xFB,0xFF,0xF7, ++0x3B,0xFD,0xFF,0xF7,0x28,0xFF,0xFF,0xF7, ++0xD4,0xFE,0xBD,0xE8,0x10,0x40,0xCE,0xE7, ++0x64,0x4A,0xB0,0x32,0x13,0x88,0x23,0xF4, ++0x7C,0x53,0x13,0x80,0x13,0x88,0x43,0xEA, ++0x00,0x30,0x10,0x80,0x10,0x88,0x40,0xEA, ++0x01,0x20,0x10,0x80,0x70,0x47,0x70,0xB5, ++0x05,0x46,0x5E,0x4E,0x00,0xEB,0x40,0x00, ++0x84,0x19,0x14,0xF8,0x47,0x0F,0xFF,0xF7, ++0xE8,0xFD,0xA1,0x78,0x60,0x78,0xFF,0xF7, ++0xE3,0xFF,0x86,0xF8,0x46,0x50,0x70,0xBD, ++0x10,0xB5,0xFF,0xF7,0xAC,0xFF,0x55,0x48, ++0x81,0x8F,0x81,0xF0,0x40,0x01,0x81,0x87, ++0x41,0x68,0x09,0x07,0x04,0xD4,0xBD,0xE8, ++0x10,0x40,0x00,0x20,0xFF,0xF7,0xD1,0xBD, ++0x90,0xF8,0x45,0x00,0xBD,0xE8,0x10,0x40, ++0x40,0x1E,0xC0,0xB2,0xD7,0xE7,0x4B,0x49, ++0x00,0x20,0x91,0xF8,0x45,0x10,0x01,0xE0, ++0x40,0x1C,0x80,0xB2,0x81,0x42,0xFB,0xD8, ++0x70,0x47,0x46,0x48,0x41,0x7B,0x31,0xF0, ++0x02,0x01,0x01,0xD0,0x44,0x48,0x70,0x47, ++0x81,0x7B,0x11,0xF0,0xF9,0x0F,0x02,0xD0, ++0x41,0x48,0x40,0x1C,0x70,0x47,0xC1,0x7B, ++0x11,0xF0,0xA0,0x0F,0x02,0xD0,0x3E,0x48, ++0x80,0x1C,0x70,0x47,0x00,0x7C,0x00,0x06, ++0x02,0xD5,0x3B,0x48,0xC0,0x1C,0x70,0x47, ++0x00,0x20,0x70,0x47,0x2D,0xE9,0xF0,0x41, ++0x00,0x24,0x34,0x4F,0x34,0x4E,0xB7,0xF8, ++0x48,0x50,0x01,0x20,0xFF,0xF7,0xC2,0xFC, ++0xB7,0xF8,0x48,0x00,0xE9,0x05,0x01,0xD5, ++0xC0,0x05,0x02,0xD4,0x64,0x1C,0xB4,0x42, ++0xF1,0xD3,0xB4,0x42,0x02,0xD1,0x29,0x48, ++0xC0,0x1C,0x55,0xE6,0x00,0x20,0x53,0xE6, ++0x2D,0xE9,0xF0,0x41,0x0D,0x46,0x11,0x0E, ++0x26,0x4C,0x06,0x9F,0x43,0xEA,0x01,0x21, ++0x41,0xF0,0x40,0x01,0xA4,0xF8,0x00,0x12, ++0x02,0xF4,0x7F,0x41,0xC2,0xF3,0x07,0x46, ++0x31,0x43,0xA4,0xF8,0x04,0x12,0xD1,0xB2, ++0xA4,0xF8,0x08,0x12,0x07,0xF0,0x7F,0x01, ++0xA1,0x86,0xA4,0xF8,0x40,0x00,0x0C,0x2B, ++0x03,0xD0,0xFF,0xF7,0xC7,0xFF,0x00,0x28, ++0x0F,0xD1,0xA4,0xF8,0x44,0x50,0x19,0x48, ++0x40,0x68,0x40,0x07,0x03,0xD5,0xFF,0xF7, ++0xBD,0xFF,0x00,0x28,0x05,0xD1,0x20,0x46, ++0xBD,0xE8,0xF0,0x41,0x02,0x21,0x12,0x4A, ++0x0E,0xE6,0x21,0xE6,0x2D,0xE9,0xF0,0x41, ++0x0E,0x4F,0x39,0x89,0x01,0xF0,0x04,0x01, ++0x81,0x42,0xFA,0xD1,0x00,0x24,0x0C,0x4E, ++0x3D,0x89,0x01,0x20,0xFF,0xF7,0x72,0xFC, ++0x38,0x89,0xA9,0x06,0x01,0xD5,0x80,0x06, ++0x02,0xD4,0x64,0x1C,0xB4,0x42,0xF3,0xD3, ++0xB4,0x42,0x0F,0xD1,0x01,0x48,0x40,0x1C, ++0x06,0xE6,0x00,0x00,0x05,0x00,0x00,0x80, ++0xEC,0x15,0x03,0x20,0x00,0x50,0x00,0x25, ++0x80,0x96,0x98,0x00,0x20,0x15,0x03,0x20, ++0x04,0x0A,0x00,0x80,0x00,0x20,0xF7,0xE5, ++0x2D,0xE9,0xF3,0x4F,0x81,0x46,0xFB,0x4C, ++0x00,0x25,0x85,0xB0,0x2E,0x46,0x2F,0x46, ++0xA8,0x46,0x60,0x68,0x01,0x07,0x08,0xD5, ++0xC0,0x06,0x0D,0xD4,0x94,0xF8,0x46,0x00, ++0x50,0xB1,0x00,0x20,0xFF,0xF7,0x27,0xFF, ++0x06,0xE0,0x94,0xF8,0x44,0x00,0x05,0x28, ++0x02,0xD0,0x05,0x20,0xFF,0xF7,0x11,0xFD, ++0x94,0xF8,0x7B,0x10,0x00,0x20,0x01,0xB9, ++0x09,0x20,0xDF,0xF8,0xB4,0xA3,0x4F,0xF0, ++0x01,0x0B,0x09,0xFA,0x00,0xF1,0xA1,0x46, ++0x03,0x91,0xA0,0x8F,0x94,0xF8,0x88,0x10, ++0x08,0x43,0x02,0x90,0x0E,0x20,0x01,0x90, ++0x04,0xF1,0x0C,0x00,0x04,0x90,0xD9,0xF8, ++0x04,0x00,0x00,0x07,0x13,0xD5,0x0A,0xF1, ++0xC8,0x04,0x40,0xF2,0x11,0x10,0xA0,0x80, ++0x20,0x88,0x40,0xF0,0x80,0x00,0x20,0x80, ++0x20,0x88,0x20,0xF0,0x40,0x00,0x20,0x80, ++0xDC,0x48,0xFF,0xF7,0x0F,0xFC,0x20,0x88, ++0x20,0xF0,0x80,0x00,0x20,0x80,0xFF,0xF7, ++0x17,0xFE,0x54,0x46,0xAA,0xF8,0x2C,0xB0, ++0x06,0x98,0x4F,0xF4,0x00,0x71,0xFF,0xF7, ++0x26,0xFD,0xA4,0xF8,0x70,0x00,0x00,0x0C, ++0xA4,0xF8,0x74,0x00,0x20,0x89,0x20,0xF0, ++0x04,0x00,0x20,0x81,0x00,0x20,0xFF,0xF7, ++0x75,0xFF,0x04,0x00,0x0A,0xD0,0x02,0x2D, ++0x24,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x20,0xD4,0x6D,0x1C,0xED,0xB2,0xFF,0xF7, ++0x8E,0xFE,0xC4,0xE7,0xBA,0xF8,0x28,0x10, ++0x41,0xF0,0x01,0x01,0xAA,0xF8,0x28,0x10, ++0x05,0x23,0xDD,0xE9,0x02,0x02,0x01,0x99, ++0x00,0x93,0x11,0x23,0xFF,0xF7,0x28,0xFF, ++0x04,0x00,0x0E,0xD0,0xB8,0xF1,0x02,0x0F, ++0x08,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x08,0xF1,0x01,0x00,0x00,0xF0, ++0xFF,0x08,0x2C,0xE0,0xFF,0xF7,0x90,0xFE, ++0x2E,0xE0,0xB9,0x4A,0x4F,0xF4,0x90,0x41, ++0x54,0x46,0x50,0x46,0xFF,0xF7,0x50,0xFD, ++0xB4,0xF8,0x48,0x10,0x50,0xEA,0xC1,0x60, ++0x08,0xD0,0x02,0x2E,0x1E,0xD2,0xD9,0xF8, ++0x04,0x00,0xC0,0x06,0x1A,0xD4,0x76,0x1C, ++0xF6,0xB2,0x14,0xE0,0x04,0x9A,0x03,0x21, ++0x00,0x20,0xFF,0xF7,0x99,0xFD,0xFF,0xF7, ++0xC4,0xFE,0x04,0x00,0x10,0xD0,0x04,0x98, ++0x05,0x21,0x01,0xF0,0xCC,0xFA,0x02,0x2F, ++0x08,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x7F,0x1C,0xFF,0xB2,0xFF,0xF7, ++0x93,0xFE,0x78,0xE7,0xA3,0x4C,0xCD,0xE7, ++0xD9,0xF8,0x04,0x00,0x00,0x07,0x05,0xD5, ++0x0A,0xF1,0xC8,0x00,0x01,0x88,0x41,0xF0, ++0x40,0x01,0x01,0x80,0x0A,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x07,0xB0,0x20,0x46,0xBD,0xE8,0xF0,0x8F, ++0x2E,0xE7,0x70,0xB5,0x04,0x20,0x98,0x4C, ++0x21,0x68,0xFF,0xF7,0xF9,0xFF,0x91,0x4D, ++0x20,0xB1,0x21,0x68,0x05,0x20,0xFF,0xF7, ++0xF3,0xFF,0xE0,0xB9,0x8D,0x48,0x2A,0x22, ++0x21,0x68,0x45,0x30,0x04,0x46,0x02,0xF0, ++0xF8,0xED,0x26,0x21,0x20,0x46,0x01,0xF0, ++0xC1,0xFA,0x04,0x46,0x87,0x48,0x6B,0x30, ++0x02,0xF0,0x32,0xEF,0xA0,0x42,0x01,0xD0, ++0x8A,0x48,0x08,0xE0,0x5C,0xB9,0x95,0xF8, ++0x47,0x00,0x95,0xF8,0x4A,0x10,0x88,0x42, ++0x05,0xD1,0x86,0x48,0x40,0x1C,0x00,0x21, ++0x85,0xF8,0x45,0x10,0x70,0xBD,0x00,0x20, ++0x70,0xBD,0x2D,0xE9,0xFC,0x5F,0x00,0x25, ++0x7A,0x49,0x2E,0x46,0xDF,0xF8,0xE8,0x91, ++0x2F,0x46,0x4F,0xF0,0x06,0x0B,0x88,0x46, ++0xCA,0x6F,0x01,0xF1,0x0C,0x0A,0xC2,0xF3, ++0x80,0x02,0x42,0xEA,0x00,0x40,0x01,0x90, ++0xFF,0xF7,0x4E,0xFD,0x05,0x23,0x01,0x9A, ++0x00,0x93,0x0D,0x23,0xB8,0xF8,0x3C,0x00, ++0x59,0x46,0xFF,0xF7,0x85,0xFE,0x04,0x00, ++0x08,0xD0,0x02,0x2F,0x2F,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x2B,0xD4,0x7F,0x1C, ++0xFF,0xB2,0x25,0xE0,0xB9,0xF8,0x48,0x00, ++0x10,0xF0,0x18,0x0F,0x0B,0xD0,0x02,0x2E, ++0x06,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x02,0xD4,0x76,0x1C,0xF6,0xB2,0x17,0xE0, ++0x64,0x4C,0xE4,0x1C,0x17,0xE0,0x03,0x21, ++0x00,0x20,0x52,0x46,0xFF,0xF7,0x00,0xFD, ++0xFF,0xF7,0x2B,0xFE,0x04,0x00,0x10,0xD0, ++0x05,0x21,0x50,0x46,0x01,0xF0,0x33,0xFA, ++0x02,0x2D,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFF,0xF7,0xFA,0xFD,0xC0,0xE7,0xFF,0xF7, ++0xC7,0xFD,0x09,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x20,0x46, ++0xBD,0xE8,0xFC,0x9F,0x2D,0xE9,0xFC,0x5F, ++0x00,0x25,0x4C,0x49,0x82,0x46,0x06,0x20, ++0xDF,0xF8,0x2C,0x91,0x2E,0x46,0x2F,0x46, ++0x4A,0x68,0x88,0x46,0x01,0xF1,0x0C,0x0B, ++0x42,0xF0,0x04,0x02,0x4A,0x60,0x01,0x90, ++0xFF,0xF7,0xF2,0xFC,0x05,0x23,0x01,0x99, ++0x00,0x93,0x06,0x23,0xB8,0xF8,0x3C,0x00, ++0x52,0x46,0xFF,0xF7,0x29,0xFE,0x04,0x00, ++0x08,0xD0,0x02,0x2F,0x2F,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x2B,0xD4,0x7F,0x1C, ++0xFF,0xB2,0x25,0xE0,0xB9,0xF8,0x48,0x00, ++0x10,0xF0,0x18,0x0F,0x0B,0xD0,0x02,0x2E, ++0x06,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x02,0xD4,0x76,0x1C,0xF6,0xB2,0x17,0xE0, ++0x36,0x4C,0xA4,0x1C,0x17,0xE0,0x03,0x21, ++0x00,0x20,0x5A,0x46,0xFF,0xF7,0xA4,0xFC, ++0xFF,0xF7,0xCF,0xFD,0x04,0x00,0x10,0xD0, ++0x05,0x21,0x58,0x46,0x01,0xF0,0xD7,0xF9, ++0x02,0x2D,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFF,0xF7,0x9E,0xFD,0xC0,0xE7,0xFF,0xF7, ++0x6B,0xFD,0x09,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x20,0x46, ++0xD8,0xF8,0x04,0x10,0x21,0xF0,0x04,0x01, ++0xC8,0xF8,0x04,0x10,0x9C,0xE7,0x80,0x07, ++0x10,0xB5,0x80,0x09,0x40,0xEA,0x01,0x40, ++0x40,0xEA,0x02,0x20,0xFF,0xF7,0x96,0xFF, ++0x00,0x28,0x04,0xD1,0x17,0x48,0x00,0x88, ++0xBD,0xE8,0x10,0x40,0x31,0xE7,0x10,0xBD, ++0x10,0xB5,0x04,0x46,0x19,0x48,0x08,0x38, ++0x01,0x2C,0x31,0xD0,0x04,0x2C,0x31,0xD0, ++0x08,0x2C,0x1D,0xD1,0x02,0x22,0x09,0xB1, ++0x42,0xF0,0x04,0x02,0x04,0x2A,0x17,0xD0, ++0xB7,0x21,0x03,0x20,0xFF,0xF7,0xDB,0xFF, ++0x00,0x28,0x11,0xD1,0x01,0x2C,0x09,0x49, ++0x8A,0x8F,0x22,0xF0,0x06,0x02,0x8A,0x87, ++0x1E,0xD0,0x04,0x2C,0x20,0xD0,0x08,0x2C, ++0x06,0xD1,0x04,0x22,0x81,0xF8,0x88,0x20, ++0x8A,0x8F,0x42,0xF0,0x04,0x02,0x8A,0x87, ++0x10,0xBD,0x00,0x00,0x20,0x15,0x03,0x20, ++0x00,0x50,0x00,0x25,0x80,0x96,0x98,0x00, ++0x40,0x4B,0x4C,0x00,0x0B,0x0A,0x00,0x80, ++0x80,0x05,0x03,0x20,0x1B,0x00,0x00,0x80, ++0x00,0x22,0xD0,0xE7,0x01,0x22,0xCE,0xE7, ++0x00,0x22,0x81,0xF8,0x88,0x20,0xE7,0xE7, ++0x02,0x22,0x81,0xF8,0x88,0x20,0x8A,0x8F, ++0x42,0xF0,0x02,0x02,0xDF,0xE7,0x70,0xB5, ++0xFF,0x4C,0x60,0x68,0x00,0x07,0x17,0xD4, ++0xFF,0xF7,0xB3,0xFE,0x05,0x46,0x01,0x21, ++0x08,0x20,0xFF,0xF7,0xAD,0xFF,0x00,0x28, ++0x0F,0xD1,0x01,0x20,0xFF,0xF7,0x4C,0xFA, ++0xA0,0x8F,0x40,0xF0,0x40,0x00,0xA0,0x87, ++0x60,0x68,0x40,0xF0,0x08,0x00,0x60,0x60, ++0x15,0xB9,0x00,0x20,0xFF,0xF7,0x07,0xFD, ++0x00,0x20,0x70,0xBD,0x10,0xB5,0x00,0x21, ++0x08,0x20,0xFF,0xF7,0x95,0xFF,0x00,0x28, ++0xBA,0xD1,0x02,0x20,0xFF,0xF7,0x34,0xFA, ++0xEB,0x49,0x11,0x20,0x88,0x87,0x48,0x68, ++0x10,0xF0,0x60,0x0F,0x01,0xD0,0x51,0x22, ++0x8A,0x87,0x20,0xF0,0x08,0x00,0x48,0x60, ++0x00,0x20,0xA9,0xE7,0xE5,0x4B,0x00,0x20, ++0x10,0xB5,0x07,0xE0,0x03,0xEB,0x80,0x04, ++0xB4,0xF8,0x00,0x44,0x22,0xF8,0x10,0x40, ++0x40,0x1C,0x80,0xB2,0x88,0x42,0xF5,0xD3, ++0x9A,0xE7,0x2D,0xE9,0xFF,0x5F,0x00,0x26, ++0x81,0x46,0xDB,0x48,0x07,0x29,0x8A,0x46, ++0x34,0x46,0x37,0x46,0x04,0xD1,0x41,0x68, ++0x41,0xF0,0x04,0x01,0x41,0x60,0x01,0xE0, ++0x4F,0xF0,0xF0,0x04,0x4F,0xEA,0x09,0x41, ++0x02,0x91,0x04,0xD1,0x02,0x88,0x4A,0x45, ++0x01,0xD0,0x04,0x21,0x00,0xE0,0x06,0x21, ++0x80,0x46,0x0C,0x30,0xDF,0xF8,0x3C,0xB3, ++0x01,0x91,0x03,0x90,0xFF,0xF7,0xE4,0xFB, ++0x05,0x23,0x00,0x93,0x53,0x46,0xDD,0xE9, ++0x01,0x12,0xB8,0xF8,0x3C,0x00,0xFF,0xF7, ++0x1B,0xFD,0x05,0x00,0x08,0xD0,0x02,0x2F, ++0x35,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x31,0xD4,0x7F,0x1C,0xFF,0xB2,0x2B,0xE0, ++0xBB,0xF8,0x48,0x00,0xBA,0xF1,0x07,0x0F, ++0x03,0xD1,0xB8,0xF8,0x00,0x10,0x49,0x45, ++0x27,0xD1,0x10,0xF0,0x18,0x0F,0x0A,0xD0, ++0x02,0x2C,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x64,0x1C,0xE4,0xB2, ++0x16,0xE0,0xB9,0x4D,0x17,0xE0,0x03,0x9A, ++0x03,0x21,0x00,0x20,0xFF,0xF7,0x90,0xFB, ++0xFF,0xF7,0xBB,0xFC,0x05,0x00,0x10,0xD0, ++0x03,0x98,0x05,0x21,0x01,0xF0,0xC3,0xF8, ++0x02,0x2E,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x76,0x1C,0xF6,0xB2, ++0xFF,0xF7,0x8A,0xFC,0xBA,0xE7,0xFF,0xF7, ++0x57,0xFC,0x0B,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0xBA,0xF1, ++0x07,0x0F,0x05,0xD1,0xD8,0xF8,0x04,0x10, ++0x21,0xF0,0x04,0x01,0xC8,0xF8,0x04,0x10, ++0x04,0xB0,0x28,0x46,0xBD,0xE8,0xF0,0x9F, ++0x2D,0xE9,0xF8,0x4F,0x00,0x24,0xDF,0xF8, ++0x78,0x82,0x25,0x46,0x9D,0x4F,0xA2,0x46, ++0x4F,0xF0,0x07,0x09,0xFF,0xF7,0x80,0xFB, ++0x10,0x23,0x52,0x46,0x00,0x93,0x02,0x23, ++0xB8,0xF8,0x3C,0x00,0x49,0x46,0xFF,0xF7, ++0xB7,0xFC,0x06,0x00,0x07,0xD0,0x02,0x2D, ++0x02,0xD2,0x6D,0x1C,0xED,0xB2,0x0B,0xE0, ++0xFF,0xF7,0x26,0xFC,0x14,0xE0,0xB7,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x09,0xD0, ++0x02,0x2C,0x04,0xD2,0x64,0x1C,0xE4,0xB2, ++0xFF,0xF7,0x4A,0xFC,0xDE,0xE7,0x8C,0x4E, ++0x76,0x1E,0xED,0xE7,0x88,0x4A,0x08,0x21, ++0x00,0x20,0x2C,0x32,0xFF,0xF7,0x34,0xFB, ++0x37,0xF8,0x40,0x0F,0x20,0xF0,0x01,0x00, ++0x38,0x80,0x30,0x46,0xBD,0xE8,0xF8,0x8F, ++0x2D,0xE9,0xF8,0x4F,0x00,0x24,0xDF,0xF8, ++0x0C,0xA2,0x25,0x46,0x7F,0x4F,0x4F,0xF0, ++0x06,0x09,0xDF,0xF8,0xF4,0x81,0xFF,0xF7, ++0x43,0xFB,0x05,0x23,0x52,0x46,0x00,0x93, ++0x01,0x23,0xB8,0xF8,0x3C,0x00,0x49,0x46, ++0xFF,0xF7,0x7A,0xFC,0x06,0x00,0x07,0xD0, ++0x02,0x2D,0x02,0xD2,0x6D,0x1C,0xED,0xB2, ++0x0A,0xE0,0xFF,0xF7,0xE9,0xFB,0x1F,0xE0, ++0xB7,0xF8,0x48,0x00,0x00,0x07,0x09,0xD5, ++0x02,0x2C,0x04,0xD2,0x64,0x1C,0xE4,0xB2, ++0xFF,0xF7,0x0E,0xFC,0xDF,0xE7,0x6E,0x4E, ++0xF6,0x1E,0xEE,0xE7,0x6A,0x4A,0x03,0x21, ++0x00,0x20,0x0C,0x32,0xFF,0xF7,0xF8,0xFA, ++0x98,0xF8,0x0D,0x00,0x41,0x46,0x02,0x06, ++0x02,0xD4,0x67,0x4E,0xB6,0x1E,0x03,0xE0, ++0xC0,0xF3,0x80,0x10,0x81,0xF8,0x7B,0x00, ++0x37,0xF8,0x40,0x0F,0x20,0xF0,0x01,0x00, ++0x38,0x80,0x30,0x46,0xB6,0xE7,0x2D,0xE9, ++0xF8,0x43,0x00,0x24,0x5C,0x4E,0x04,0x27, ++0x80,0x46,0xFF,0xF7,0x01,0xFB,0x00,0x23, ++0x42,0x46,0x00,0x93,0x39,0x46,0xB0,0x8F, ++0xFF,0xF7,0x3A,0xFC,0x05,0x00,0x08,0xD0, ++0x02,0x2C,0x04,0xD2,0x64,0x1C,0xE4,0xB2, ++0xFF,0xF7,0xDA,0xFB,0xED,0xE7,0xFF,0xF7, ++0xA7,0xFB,0x52,0x48,0x40,0x30,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x28,0x46, ++0xBD,0xE8,0xF8,0x83,0x2D,0xE9,0xF0,0x41, ++0x00,0x20,0xFF,0xF7,0xD8,0xFF,0x00,0x28, ++0x10,0xD1,0x00,0x24,0x4F,0xF4,0x7A,0x77, ++0x4F,0xF4,0x80,0x56,0xFF,0xF7,0x88,0xFF, ++0x05,0x00,0x08,0xD0,0x38,0x46,0xFF,0xF7, ++0xC5,0xF8,0x64,0x1C,0xA4,0xB2,0xB4,0x42, ++0xF4,0xD3,0x28,0x46,0x09,0xE4,0xFF,0xF7, ++0x3F,0xFF,0x00,0x28,0xFA,0xD1,0x02,0x20, ++0x3D,0x4D,0x00,0x24,0x28,0x80,0x03,0x21, ++0x28,0x88,0xFF,0xF7,0xBA,0xFE,0x00,0x28, ++0xF0,0xD0,0x29,0x88,0x64,0x1C,0x49,0x1C, ++0xA4,0xB2,0x05,0x2C,0x29,0x80,0xF2,0xD3, ++0x27,0xE4,0x2D,0xE9,0xF8,0x4F,0x00,0x24, ++0xDF,0xF8,0xD0,0x80,0x25,0x46,0x32,0x4F, ++0x4F,0xEA,0x00,0x4A,0x4F,0xF0,0x07,0x09, ++0xFF,0xF7,0xAA,0xFA,0x10,0x23,0x52,0x46, ++0x00,0x93,0x09,0x23,0xB8,0x8F,0x49,0x46, ++0xFF,0xF7,0xE2,0xFB,0x06,0x00,0x0A,0xD0, ++0x02,0x2D,0x05,0xD2,0x78,0x68,0xC0,0x06, ++0x02,0xD4,0x6D,0x1C,0xED,0xB2,0x0E,0xE0, ++0xFF,0xF7,0x4E,0xFB,0x17,0xE0,0xB8,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0C,0xD0, ++0x02,0x2C,0x07,0xD2,0x78,0x68,0xC0,0x06, ++0x04,0xD4,0x64,0x1C,0xE4,0xB2,0xFF,0xF7, ++0x6F,0xFB,0xD9,0xE7,0x1E,0x4E,0x16,0x36, ++0xEA,0xE7,0x1B,0x4A,0x08,0x21,0x00,0x20, ++0x1C,0x32,0xFF,0xF7,0x59,0xFA,0x08,0xF1, ++0x40,0x00,0x01,0x88,0x21,0xF0,0x01,0x01, ++0x01,0x80,0x30,0x46,0x22,0xE7,0x70,0xB5, ++0x13,0x4C,0x20,0x88,0xFF,0xF7,0xB9,0xFF, ++0x00,0x28,0x65,0xD1,0x1C,0x34,0x60,0x78, ++0xC0,0xF3,0x83,0x00,0x84,0xF8,0x53,0x00, ++0xA0,0x79,0x00,0xF0,0x0F,0x02,0x84,0xF8, ++0x54,0x20,0x61,0x7B,0xA3,0x7B,0x88,0x07, ++0x00,0x0F,0x00,0xEB,0x93,0x10,0x84,0xF8, ++0x55,0x00,0xE0,0x79,0x23,0x7A,0x80,0x07, ++0x00,0x0D,0x80,0xB2,0x00,0xEB,0x83,0x00, ++0x63,0x7A,0x00,0xEB,0x93,0x10,0x80,0xB2, ++0xA4,0xF8,0x56,0x00,0x1C,0x3C,0x07,0xE0, ++0x20,0x15,0x03,0x20,0x00,0x50,0x00,0x25, ++0x03,0x0A,0x00,0x80,0x00,0x80,0xFF,0x40, ++0xA0,0xF5,0x70,0x63,0xFF,0x3B,0x03,0xD1, ++0x00,0x20,0xC4,0xF8,0x84,0x00,0x12,0xE0, ++0x24,0x34,0x40,0x1C,0xA3,0x78,0xE5,0x78, ++0x9B,0x07,0x5B,0x0F,0x03,0xEB,0xD5,0x13, ++0x84,0xF8,0x53,0x30,0xDB,0xB2,0x9B,0x1C, ++0x98,0x40,0x01,0x23,0x93,0x40,0x5A,0x12, ++0x50,0x43,0x20,0x66,0x24,0x3C,0x5C,0x34, ++0x14,0xF8,0x36,0x0C,0xC0,0xF3,0x84,0x02, ++0x22,0x77,0x80,0x07,0x14,0xF8,0x35,0x2C, ++0xC0,0x0E,0x00,0xEB,0x52,0x10,0x60,0x77, ++0x20,0x7F,0x62,0x7F,0x40,0x1C,0x52,0x1C, ++0x10,0xFB,0x02,0xF0,0x60,0x62,0x14,0xF8, ++0x3E,0x0C,0x20,0x76,0x14,0xF8,0x3D,0x0C, ++0x60,0x76,0x14,0xF8,0x3C,0x0C,0xA0,0x76, ++0xC1,0xF3,0x82,0x00,0xA0,0x77,0x00,0x20, ++0x70,0xBD,0x2D,0xE9,0xF1,0x4F,0x00,0x25, ++0xFD,0x4C,0x84,0xB0,0x2E,0x46,0x2F,0x46, ++0xA8,0x46,0x60,0x68,0x01,0x07,0x07,0xD5, ++0xC0,0x06,0x05,0xD4,0x94,0xF8,0x46,0x00, ++0x10,0xB1,0x00,0x20,0xFF,0xF7,0xCB,0xFA, ++0x00,0x20,0xDF,0xF8,0xD8,0xA3,0x03,0x90, ++0x4F,0xF0,0x01,0x0B,0xA0,0x8F,0xA1,0x46, ++0x94,0xF8,0x88,0x10,0x08,0x43,0x02,0x90, ++0x0E,0x20,0x01,0x90,0xD9,0xF8,0x04,0x00, ++0x00,0x07,0x13,0xD5,0x0A,0xF1,0xC8,0x04, ++0x40,0xF2,0x11,0x10,0xA0,0x80,0x20,0x88, ++0x40,0xF0,0x80,0x00,0x20,0x80,0x20,0x88, ++0x20,0xF0,0x40,0x00,0x20,0x80,0xE8,0x48, ++0xFE,0xF7,0xC4,0xFF,0x20,0x88,0x20,0xF0, ++0x80,0x00,0x20,0x80,0xFF,0xF7,0xCC,0xF9, ++0x54,0x46,0xAA,0xF8,0x2C,0xB0,0x04,0x98, ++0x4F,0xF4,0x00,0x71,0xFF,0xF7,0xDB,0xF8, ++0xA4,0xF8,0x70,0x00,0x00,0x0C,0xA4,0xF8, ++0x74,0x00,0x20,0x89,0x20,0xF0,0x04,0x00, ++0x20,0x81,0x00,0x20,0xFF,0xF7,0x2A,0xFB, ++0x04,0x00,0x0A,0xD0,0x02,0x2D,0x24,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x20,0xD4, ++0x6D,0x1C,0xED,0xB2,0xFF,0xF7,0x43,0xFA, ++0xC4,0xE7,0xBA,0xF8,0x28,0x10,0x41,0xF0, ++0x01,0x01,0xAA,0xF8,0x28,0x10,0x05,0x23, ++0xDD,0xE9,0x02,0x02,0x01,0x99,0x00,0x93, ++0x08,0x23,0xFF,0xF7,0xDD,0xFA,0x04,0x00, ++0x0E,0xD0,0xB8,0xF1,0x02,0x0F,0x08,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x04,0xD4, ++0x08,0xF1,0x01,0x00,0x00,0xF0,0xFF,0x08, ++0x2E,0xE0,0xFF,0xF7,0x45,0xFA,0x30,0xE0, ++0xC4,0x4A,0x4F,0xF4,0x90,0x41,0x54,0x46, ++0x50,0x46,0xFF,0xF7,0x05,0xF9,0xB4,0xF8, ++0x48,0x10,0x50,0xEA,0xC1,0x60,0x08,0xD0, ++0x02,0x2E,0x20,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x1C,0xD4,0x76,0x1C,0xF6,0xB2, ++0x16,0xE0,0xBB,0x48,0x03,0x21,0x02,0x68, ++0x00,0x20,0xFF,0xF7,0x4D,0xF9,0xFF,0xF7, ++0x78,0xFA,0x04,0x00,0x11,0xD0,0x05,0x21, ++0xB1,0x48,0x0C,0x30,0x00,0xF0,0x7F,0xFE, ++0x02,0x2F,0x08,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x7F,0x1C,0xFF,0xB2, ++0xFF,0xF7,0x46,0xFA,0x76,0xE7,0xAF,0x4C, ++0xCB,0xE7,0xD9,0xF8,0x04,0x00,0x00,0x07, ++0x05,0xD5,0x0A,0xF1,0xC8,0x00,0x01,0x88, ++0x41,0xF0,0x40,0x01,0x01,0x80,0x0A,0xF1, ++0x40,0x00,0x01,0x88,0x21,0xF0,0x01,0x01, ++0x01,0x80,0x20,0x46,0x05,0xB0,0xBD,0xE8, ++0xF0,0x8F,0x3E,0xE7,0x70,0xB5,0xA2,0x4D, ++0x28,0x68,0xFF,0xF7,0xFA,0xFF,0x00,0x28, ++0x46,0xD1,0x9B,0x4C,0xD4,0xF8,0x84,0x00, ++0x50,0xB9,0x28,0x68,0x06,0x46,0xD5,0x30, ++0x02,0xF0,0xF2,0xEA,0x96,0xF8,0xD4,0x10, ++0x41,0xEA,0x00,0x20,0xC4,0xF8,0x84,0x00, ++0x28,0x68,0x90,0xF8,0xB7,0x10,0x84,0xF8, ++0x88,0x10,0x31,0xB1,0x01,0x29,0x0C,0xD0, ++0x02,0x29,0x0C,0xD1,0x04,0x21,0x84,0xF8, ++0x88,0x10,0x90,0xF8,0xE7,0x10,0xC9,0x06, ++0xE1,0x6F,0x05,0xD5,0x41,0xF0,0x01,0x01, ++0x04,0xE0,0x02,0x21,0xF3,0xE7,0xFE,0xE7, ++0x21,0xF0,0x01,0x01,0xE1,0x67,0x90,0xF8, ++0xF7,0x11,0xCA,0x07,0x0F,0xD0,0x89,0x07, ++0xE1,0x6F,0x02,0xD5,0x41,0xF0,0x02,0x01, ++0x01,0xE0,0x41,0xF0,0x04,0x01,0xE1,0x67, ++0x90,0xF8,0xA6,0x10,0x49,0x07,0x06,0xD5, ++0x40,0xF6,0xFF,0x70,0x05,0xE0,0xE1,0x6F, ++0x21,0xF0,0x06,0x01,0xF3,0xE7,0x90,0xF8, ++0xDE,0x00,0xA4,0xF8,0x8A,0x00,0x00,0x20, ++0x70,0xBD,0x2D,0xE9,0xF1,0x4F,0x00,0x25, ++0xDF,0xF8,0xD8,0x91,0x84,0xB0,0x2E,0x46, ++0x2F,0x46,0xA9,0xF8,0x3C,0x50,0x4F,0xF0, ++0x0E,0x0B,0xDF,0xF8,0xC4,0x81,0x03,0x95, ++0xDF,0xF8,0xD0,0xA1,0xB8,0xF8,0x3C,0x00, ++0x98,0xF8,0x88,0x10,0xAA,0xF1,0x01,0x0A, ++0x08,0x43,0x40,0xF0,0x20,0x00,0x02,0x90, ++0xFF,0xF7,0xDA,0xF8,0xDD,0xE9,0x02,0x02, ++0x05,0x23,0x00,0x93,0x08,0x23,0x59,0x46, ++0xFF,0xF7,0x12,0xFA,0x04,0x00,0x0B,0xD0, ++0x02,0x2F,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x7F,0x1C,0xFF,0xB2, ++0x2D,0xE0,0xFF,0xF7,0x7D,0xF9,0x35,0xE0, ++0x60,0x4A,0x04,0x21,0x4C,0x46,0x48,0x46, ++0xFF,0xF7,0x3E,0xF8,0xB4,0xF8,0x48,0x10, ++0x08,0xB9,0xC8,0x06,0x08,0xD0,0x02,0x2D, ++0x20,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x1C,0xD4,0x6D,0x1C,0xED,0xB2,0x16,0xE0, ++0x57,0x48,0x03,0x21,0x02,0x68,0x00,0x20, ++0xFF,0xF7,0x86,0xF8,0xFF,0xF7,0xB1,0xF9, ++0x04,0x00,0x11,0xD0,0x05,0x21,0x4E,0x48, ++0x0C,0x30,0x00,0xF0,0xB8,0xFD,0x02,0x2E, ++0x08,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFF,0xF7, ++0x7F,0xF9,0xB9,0xE7,0x54,0x46,0xCC,0xE7, ++0x04,0x9A,0x00,0x20,0x4F,0xF4,0x80,0x71, ++0xFF,0xF7,0x78,0xFC,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0x3B,0xE7,0x02,0x46,0x10,0xB5, ++0x04,0x46,0xB9,0x21,0x03,0x20,0xFF,0xF7, ++0xDA,0xFB,0x00,0x28,0x0F,0xD1,0x01,0x2C, ++0x39,0x4A,0x51,0x68,0x21,0xF0,0x60,0x01, ++0x51,0x60,0x09,0xD0,0x02,0x2C,0x0A,0xD1, ++0x41,0xF0,0x40,0x01,0x51,0x60,0x91,0x8F, ++0x41,0xF0,0x40,0x01,0x91,0x87,0x16,0xE4, ++0x41,0xF0,0x20,0x01,0xF6,0xE7,0x91,0x8F, ++0x21,0xF0,0x40,0x01,0xF6,0xE7,0x2D,0xE9, ++0xFC,0x5F,0x06,0x20,0x00,0x25,0x01,0x90, ++0x2E,0x46,0x2B,0x48,0x2F,0x46,0xC1,0x6F, ++0xC9,0x07,0x00,0xD0,0x01,0x21,0xDF,0xF8, ++0xA4,0x90,0x8A,0x46,0x80,0x46,0x00,0xF1, ++0x0C,0x0B,0xFF,0xF7,0x51,0xF8,0x05,0x23, ++0x01,0x99,0x00,0x93,0x26,0x23,0xB8,0xF8, ++0x3C,0x00,0x52,0x46,0xFF,0xF7,0x88,0xF9, ++0x04,0x00,0x08,0xD0,0x02,0x2F,0x2F,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x2B,0xD4, ++0x7F,0x1C,0xFF,0xB2,0x25,0xE0,0xB9,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0B,0xD0, ++0x02,0x2E,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x76,0x1C,0xF6,0xB2, ++0x17,0xE0,0x18,0x4C,0xA4,0x1F,0x17,0xE0, ++0x03,0x21,0x00,0x20,0x5A,0x46,0xFF,0xF7, ++0x03,0xF8,0xFF,0xF7,0x2E,0xF9,0x04,0x00, ++0x10,0xD0,0x05,0x21,0x58,0x46,0x00,0xF0, ++0x36,0xFD,0x02,0x2D,0x08,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x6D,0x1C, ++0xED,0xB2,0xFF,0xF7,0xFD,0xF8,0xC0,0xE7, ++0xFF,0xF7,0xCA,0xF8,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0xBD,0xE8,0xFC,0x9F,0x00,0x00, ++0x20,0x15,0x03,0x20,0x00,0x50,0x00,0x25, ++0x80,0x96,0x98,0x00,0x40,0x4B,0x4C,0x00, ++0x80,0x05,0x03,0x20,0x09,0x0A,0x00,0x80, ++0x2D,0xE9,0xF3,0x4F,0x00,0x25,0xFB,0x4A, ++0x83,0xB0,0x06,0x21,0x2E,0x46,0x02,0x91, ++0x2F,0x46,0x92,0xF8,0x7B,0x30,0x29,0x46, ++0x03,0xB9,0x09,0x21,0xDF,0xF8,0xD8,0x93, ++0x90,0x46,0x02,0xF1,0x0C,0x0B,0x00,0xFA, ++0x01,0xFA,0xFE,0xF7,0xE5,0xFF,0x05,0x23, ++0x02,0x99,0x00,0x93,0x52,0x46,0xB8,0xF8, ++0x3C,0x00,0x04,0x9B,0xFF,0xF7,0x1C,0xF9, ++0x04,0x00,0x08,0xD0,0x02,0x2F,0x2E,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x2A,0xD4, ++0x7F,0x1C,0xFF,0xB2,0x24,0xE0,0xB9,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0A,0xD0, ++0x02,0x2E,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x76,0x1C,0xF6,0xB2, ++0x16,0xE0,0xE2,0x4C,0x17,0xE0,0x03,0x21, ++0x00,0x20,0x5A,0x46,0xFE,0xF7,0x98,0xFF, ++0xFF,0xF7,0xC3,0xF8,0x04,0x00,0x10,0xD0, ++0x05,0x21,0x58,0x46,0x00,0xF0,0xCB,0xFC, ++0x02,0x2D,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFF,0xF7,0x92,0xF8,0xC1,0xE7,0xFF,0xF7, ++0x5F,0xF8,0x09,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x20,0x46, ++0x54,0xE6,0x10,0xB5,0x0C,0x46,0x23,0x21, ++0xFF,0xF7,0x9E,0xFF,0x00,0x28,0x08,0xD1, ++0x24,0x21,0x20,0x46,0xFF,0xF7,0x98,0xFF, ++0x00,0x28,0x02,0xD1,0xBD,0xE8,0x10,0x40, ++0x29,0xE7,0x20,0xE7,0x2D,0xE9,0xF3,0x4F, ++0x00,0x25,0xDF,0xF8,0x14,0x93,0x85,0xB0, ++0x82,0x46,0x2E,0x46,0x2F,0x46,0xA8,0x46, ++0xA9,0xF8,0x3C,0x50,0xBF,0x4C,0x94,0xF8, ++0x44,0x00,0x05,0x28,0x02,0xD0,0x05,0x20, ++0xFE,0xF7,0x43,0xFE,0x94,0xF8,0x7B,0x10, ++0x40,0x46,0x01,0xB9,0x09,0x20,0xDF,0xF8, ++0xE4,0xB2,0xA0,0x46,0x0A,0xFA,0x00,0xF1, ++0xDF,0xF8,0xE0,0xA2,0x04,0x91,0x0B,0xF1, ++0x0C,0x0B,0xA0,0x8F,0x0A,0xF1,0x07,0x0A, ++0x94,0xF8,0x88,0x10,0x08,0x43,0x40,0xF0, ++0x20,0x00,0x03,0x90,0x0E,0x20,0x02,0x90, ++0xFE,0xF7,0x5E,0xFF,0x05,0x23,0x02,0x99, ++0x00,0x93,0x11,0x23,0xDD,0xE9,0x03,0x02, ++0xFF,0xF7,0x96,0xF8,0x04,0x00,0x0B,0xD0, ++0x02,0x2F,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x7F,0x1C,0xFF,0xB2, ++0x2B,0xE0,0xFF,0xF7,0x01,0xF8,0x33,0xE0, ++0xA5,0x4A,0x04,0x21,0x4C,0x46,0x48,0x46, ++0xFE,0xF7,0xC2,0xFE,0xB4,0xF8,0x48,0x10, ++0x50,0xEA,0xC1,0x60,0x08,0xD0,0x02,0x2E, ++0x1E,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x1A,0xD4,0x76,0x1C,0xF6,0xB2,0x14,0xE0, ++0x03,0x21,0x00,0x20,0x5A,0x46,0xFE,0xF7, ++0x0B,0xFF,0xFF,0xF7,0x36,0xF8,0x04,0x00, ++0x10,0xD0,0x05,0x21,0x58,0x46,0x00,0xF0, ++0x3E,0xFC,0x02,0x2D,0x08,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x6D,0x1C, ++0xED,0xB2,0xFF,0xF7,0x05,0xF8,0xBB,0xE7, ++0x54,0x46,0xCE,0xE7,0x06,0x9A,0x00,0x20, ++0x4F,0xF4,0x80,0x71,0xFF,0xF7,0xFE,0xFA, ++0x09,0xF1,0x40,0x00,0x01,0x88,0x21,0xF0, ++0x01,0x01,0x01,0x80,0x20,0x46,0x07,0xB0, ++0xC1,0xE5,0x2D,0xE9,0xFC,0x5F,0x00,0x25, ++0x82,0x49,0x2E,0x46,0xDF,0xF8,0x08,0x92, ++0x2F,0x46,0x4F,0xF0,0x06,0x0B,0x88,0x46, ++0x48,0x68,0x01,0xF1,0x0C,0x0A,0x40,0xF0, ++0x04,0x00,0x48,0x60,0x01,0x95,0xFE,0xF7, ++0xF7,0xFE,0x05,0x23,0x01,0x9A,0x00,0x93, ++0x0C,0x23,0xB8,0xF8,0x3C,0x00,0x59,0x46, ++0xFF,0xF7,0x2E,0xF8,0x04,0x00,0x08,0xD0, ++0x02,0x2F,0x2F,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x2B,0xD4,0x7F,0x1C,0xFF,0xB2, ++0x25,0xE0,0xB9,0xF8,0x48,0x00,0x10,0xF0, ++0x18,0x0F,0x0B,0xD0,0x02,0x2D,0x06,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x02,0xD4, ++0x6D,0x1C,0xED,0xB2,0x17,0xE0,0x6B,0x4C, ++0x0C,0x34,0x17,0xE0,0x03,0x21,0x00,0x20, ++0x52,0x46,0xFE,0xF7,0xA9,0xFE,0xFE,0xF7, ++0xD4,0xFF,0x04,0x00,0x10,0xD0,0x05,0x21, ++0x50,0x46,0x00,0xF0,0xDC,0xFB,0x02,0x2E, ++0x08,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFE,0xF7, ++0xA3,0xFF,0xC0,0xE7,0xFE,0xF7,0x70,0xFF, ++0x09,0xF1,0x40,0x00,0x01,0x88,0x21,0xF0, ++0x01,0x01,0x01,0x80,0x20,0x46,0xD8,0xF8, ++0x04,0x10,0x21,0xF0,0x04,0x01,0xC8,0xF8, ++0x04,0x10,0x9E,0xE6,0x2D,0xE9,0xF7,0x4F, ++0x81,0x46,0x52,0x4C,0x00,0x25,0x86,0xB0, ++0x92,0x46,0x2E,0x46,0x2F,0x46,0x60,0x68, ++0xA8,0x46,0x01,0x07,0x08,0xD5,0xC0,0x06, ++0x0D,0xD4,0x94,0xF8,0x46,0x00,0x50,0xB1, ++0x00,0x20,0xFE,0xF7,0x6C,0xFF,0x06,0xE0, ++0x94,0xF8,0x44,0x00,0x05,0x28,0x02,0xD0, ++0x05,0x20,0xFE,0xF7,0x56,0xFD,0x94,0xF8, ++0x7B,0x10,0x00,0x20,0x01,0xB9,0x09,0x20, ++0xDF,0xF8,0x0C,0xB1,0x09,0xFA,0x00,0xF1, ++0xA1,0x46,0x03,0x91,0xA0,0x8F,0x94,0xF8, ++0x88,0x10,0x08,0x43,0x02,0x90,0x0E,0x20, ++0x01,0x90,0x04,0xF1,0x0C,0x00,0x05,0x90, ++0x4F,0xEA,0x4A,0x20,0x04,0x90,0xD9,0xF8, ++0x04,0x00,0x00,0x07,0x13,0xD5,0x0B,0xF1, ++0xC8,0x04,0x40,0xF2,0x11,0x10,0xA0,0x80, ++0x20,0x88,0x40,0xF0,0x80,0x00,0x20,0x80, ++0x20,0x88,0x20,0xF0,0x40,0x00,0x20,0x80, ++0x34,0x48,0xFE,0xF7,0x53,0xFC,0x20,0x88, ++0x20,0xF0,0x80,0x00,0x20,0x80,0xFE,0xF7, ++0x5B,0xFE,0x5C,0x46,0xAB,0xF8,0x2C,0xA0, ++0x04,0x99,0x07,0x98,0xFE,0xF7,0x6B,0xFD, ++0xA4,0xF8,0x70,0x00,0x00,0x0C,0xA4,0xF8, ++0x74,0x00,0x20,0x89,0x20,0xF0,0x04,0x00, ++0x20,0x81,0x00,0x20,0xFE,0xF7,0xBA,0xFF, ++0x04,0x00,0x0A,0xD0,0x02,0x2D,0x24,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x20,0xD4, ++0x6D,0x1C,0xED,0xB2,0xFE,0xF7,0xD3,0xFE, ++0xC5,0xE7,0xBB,0xF8,0x28,0x10,0x41,0xF0, ++0x01,0x01,0xAB,0xF8,0x28,0x10,0x05,0x23, ++0xDD,0xE9,0x02,0x02,0x01,0x99,0x00,0x93, ++0x12,0x23,0xFE,0xF7,0x6D,0xFF,0x04,0x00, ++0x0E,0xD0,0xB8,0xF1,0x02,0x0F,0x08,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x04,0xD4, ++0x08,0xF1,0x01,0x00,0x00,0xF0,0xFF,0x08, ++0x3B,0xE0,0xFE,0xF7,0xD5,0xFE,0x3D,0xE0, ++0x10,0x48,0x01,0x21,0x01,0xEB,0x5A,0x22, ++0x4F,0xF4,0x90,0x41,0x5C,0x46,0x42,0x43, ++0x58,0x46,0xFE,0xF7,0xA9,0xFD,0xB4,0xF8, ++0x48,0x10,0x50,0xEA,0xC1,0x60,0x13,0xD0, ++0x02,0x2E,0x29,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x25,0xD4,0x76,0x1C,0xF6,0xB2, ++0x1F,0xE0,0x00,0x00,0x20,0x15,0x03,0x20, ++0x00,0x50,0x00,0x25,0x03,0x0A,0x00,0x80, ++0x40,0x4B,0x4C,0x00,0x80,0x96,0x98,0x00, ++0x05,0x9A,0x03,0x21,0x00,0x20,0xFE,0xF7, ++0xCF,0xFD,0xFE,0xF7,0xFA,0xFE,0x04,0x00, ++0x10,0xD0,0x05,0x98,0x05,0x21,0x00,0xF0, ++0x02,0xFB,0x02,0x2F,0x08,0xD2,0xD9,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x7F,0x1C, ++0xFF,0xB2,0xFE,0xF7,0xC9,0xFE,0x6A,0xE7, ++0xFB,0x4C,0xBE,0xE7,0xD9,0xF8,0x04,0x00, ++0x49,0x46,0x00,0x07,0x05,0xD5,0x0B,0xF1, ++0xC8,0x00,0x02,0x88,0x42,0xF0,0x40,0x02, ++0x02,0x80,0x08,0x88,0xFF,0xF7,0xC5,0xFE, ++0x01,0x46,0x0B,0xF1,0x40,0x00,0x02,0x88, ++0x22,0xF0,0x01,0x02,0x02,0x80,0x20,0x00, ++0x00,0xD1,0x08,0x46,0x09,0xB0,0x7A,0xE4, ++0x18,0xE7,0x2D,0xE9,0xFC,0x5F,0x00,0x25, ++0xDF,0xF8,0xB4,0x83,0x40,0xF0,0x00,0x40, ++0xDF,0xF8,0xA8,0x93,0x2E,0x46,0x01,0x90, ++0x2F,0x46,0x4F,0xF0,0x06,0x0B,0x08,0xF1, ++0x0C,0x0A,0xFE,0xF7,0xB1,0xFD,0x05,0x23, ++0x01,0x9A,0x00,0x93,0x17,0x23,0xB8,0xF8, ++0x3C,0x00,0x59,0x46,0xFE,0xF7,0xE8,0xFE, ++0x04,0x00,0x08,0xD0,0x02,0x2F,0x2F,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x2B,0xD4, ++0x7F,0x1C,0xFF,0xB2,0x25,0xE0,0xB9,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0B,0xD0, ++0x02,0x2E,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x76,0x1C,0xF6,0xB2, ++0x17,0xE0,0xD3,0x4C,0xA4,0x1C,0x17,0xE0, ++0x03,0x21,0x00,0x20,0x52,0x46,0xFE,0xF7, ++0x63,0xFD,0xFE,0xF7,0x8E,0xFE,0x04,0x00, ++0x10,0xD0,0x05,0x21,0x50,0x46,0x00,0xF0, ++0x96,0xFA,0x02,0x2D,0x08,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x6D,0x1C, ++0xED,0xB2,0xFE,0xF7,0x5D,0xFE,0xC0,0xE7, ++0xFE,0xF7,0x2A,0xFE,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0x5E,0xE5,0x2D,0xE9,0xF7,0x4F, ++0x05,0x46,0xC1,0x4C,0x00,0x20,0x86,0xB0, ++0x07,0x46,0x80,0x46,0x81,0x46,0x04,0x90, ++0x82,0x46,0x60,0x68,0x16,0x46,0x01,0x07, ++0x08,0xD5,0xC0,0x06,0x0D,0xD4,0x94,0xF8, ++0x46,0x00,0x50,0xB1,0x00,0x20,0xFE,0xF7, ++0x2A,0xFE,0x06,0xE0,0x94,0xF8,0x44,0x00, ++0x05,0x28,0x02,0xD0,0x05,0x20,0xFE,0xF7, ++0x14,0xFC,0x94,0xF8,0x7B,0x10,0x00,0x20, ++0x01,0xB9,0x09,0x20,0xA3,0x46,0x85,0x40, ++0x03,0x95,0xA0,0x8F,0x94,0xF8,0x88,0x10, ++0x08,0x43,0x02,0x90,0x06,0x20,0x01,0x90, ++0x04,0xF1,0x0C,0x00,0x05,0x90,0x5C,0x46, ++0xBB,0xF8,0x8A,0x00,0x35,0x46,0xB0,0x42, ++0x00,0xD2,0x05,0x46,0x28,0x46,0xFF,0xF7, ++0x6C,0xFF,0x00,0x28,0x7E,0xD1,0x60,0x68, ++0xA3,0x46,0x00,0x07,0x08,0xD5,0x4F,0xF4, ++0x8D,0x71,0xA0,0x48,0xC8,0x30,0x81,0x80, ++0x01,0x88,0x41,0xF0,0x40,0x01,0x01,0x80, ++0xFE,0xF7,0x1E,0xFD,0x9B,0x4C,0xA5,0x85, ++0x69,0x02,0x07,0x98,0xFE,0xF7,0x2F,0xFC, ++0xA4,0xF8,0x70,0x00,0x00,0x0C,0xA4,0xF8, ++0x74,0x00,0x20,0x89,0x40,0xF0,0x04,0x00, ++0x20,0x81,0x04,0x20,0xFE,0xF7,0x7E,0xFE, ++0x04,0x00,0x0D,0xD0,0x02,0x2F,0x08,0xD2, ++0xDB,0xF8,0x04,0x00,0xC0,0x06,0x04,0xD4, ++0x7F,0x1C,0xFF,0xB2,0xFE,0xF7,0x97,0xFD, ++0xC5,0xE7,0xFE,0xF7,0xB5,0xFD,0x6D,0xE0, ++0x8A,0x48,0x01,0x8D,0x41,0xF0,0x01,0x01, ++0x01,0x85,0x05,0x23,0xDD,0xE9,0x02,0x02, ++0x01,0x99,0x00,0x93,0x19,0x23,0xFE,0xF7, ++0x2F,0xFE,0x04,0x00,0x0B,0xD0,0xBA,0xF1, ++0x02,0x0F,0xEA,0xD2,0xDB,0xF8,0x04,0x00, ++0xC0,0x06,0xE6,0xD4,0x0A,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x0A,0x16,0xE0,0x05,0x9A, ++0x03,0x21,0x00,0x20,0xFE,0xF7,0xB8,0xFC, ++0xFE,0xF7,0xE3,0xFD,0xA0,0xB1,0x05,0x98, ++0x05,0x21,0x00,0xF0,0xEC,0xF9,0xB9,0xF1, ++0x02,0x0F,0x0A,0xD2,0xDB,0xF8,0x04,0x00, ++0xC0,0x06,0x06,0xD4,0x09,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x09,0xFE,0xF7,0xB0,0xFD, ++0x8D,0xE7,0x6F,0x4C,0x0C,0x34,0xC4,0xE7, ++0xFE,0xF7,0xE8,0xFD,0x10,0xB1,0x6C,0x4C, ++0x0B,0x34,0x2F,0xE0,0x6B,0x49,0x18,0x20, ++0x44,0x31,0x08,0x80,0x01,0x20,0x00,0xEB, ++0xD5,0x12,0x6A,0x48,0x4F,0xF4,0x00,0x61, ++0x42,0x43,0x66,0x48,0xFE,0xF7,0x48,0xFC, ++0x04,0x46,0x00,0xE0,0x2C,0xE0,0x63,0x48, ++0xB0,0xF8,0x48,0x00,0x00,0xF0,0x06,0x01, ++0x21,0x43,0x0E,0xD0,0xB8,0xF1,0x02,0x0F, ++0x08,0xD2,0xDB,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x08,0xF1,0x01,0x00,0x00,0xF0, ++0xFF,0x08,0xCF,0xE7,0x58,0x4C,0x0A,0x34, ++0x97,0xE7,0x07,0x98,0x00,0xEB,0x45,0x20, ++0x07,0x90,0x70,0x1B,0x06,0x04,0x36,0x0C, ++0x8E,0xD1,0x24,0xB1,0xBB,0xF8,0x00,0x00, ++0xFF,0xF7,0x7F,0xFD,0x04,0x90,0x51,0x48, ++0x40,0x30,0x01,0x88,0x21,0xF0,0x01,0x01, ++0x01,0x80,0x20,0x00,0x00,0xD1,0x04,0x98, ++0xB8,0xE6,0x13,0xE7,0x01,0x22,0x11,0xE7, ++0x2D,0xE9,0xF3,0x4F,0x81,0x46,0x4A,0x4C, ++0x00,0x25,0x85,0xB0,0x2E,0x46,0x2F,0x46, ++0xA8,0x46,0x60,0x68,0x01,0x07,0x08,0xD5, ++0xC0,0x06,0x0D,0xD4,0x94,0xF8,0x46,0x00, ++0x50,0xB1,0x00,0x20,0xFE,0xF7,0x3F,0xFD, ++0x06,0xE0,0x94,0xF8,0x44,0x00,0x05,0x28, ++0x02,0xD0,0x05,0x20,0xFE,0xF7,0x29,0xFB, ++0x94,0xF8,0x7B,0x10,0x00,0x20,0x01,0xB9, ++0x09,0x20,0xDF,0xF8,0xE8,0xA0,0x4F,0xF0, ++0x01,0x0B,0x09,0xFA,0x00,0xF1,0xA1,0x46, ++0x03,0x91,0xA0,0x8F,0x94,0xF8,0x88,0x10, ++0x08,0x43,0x02,0x90,0x06,0x20,0x01,0x90, ++0x04,0xF1,0x0C,0x00,0x04,0x90,0xD9,0xF8, ++0x04,0x00,0x00,0x07,0x08,0xD5,0x0A,0xF1, ++0xC8,0x00,0x4F,0xF4,0x8D,0x71,0x81,0x80, ++0x01,0x88,0x41,0xF0,0x40,0x01,0x01,0x80, ++0xFE,0xF7,0x3A,0xFC,0x54,0x46,0xAA,0xF8, ++0x2C,0xB0,0x06,0x98,0x4F,0xF4,0x00,0x71, ++0xFE,0xF7,0x49,0xFB,0xA4,0xF8,0x70,0x00, ++0x00,0x0C,0xA4,0xF8,0x74,0x00,0x20,0x89, ++0x40,0xF0,0x04,0x00,0x20,0x81,0x04,0x20, ++0xFE,0xF7,0x98,0xFD,0x04,0x00,0x0A,0xD0, ++0x02,0x2D,0x65,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x61,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFE,0xF7,0xB1,0xFC,0xCF,0xE7,0xBA,0xF8, ++0x28,0x10,0x41,0xF0,0x01,0x01,0xAA,0xF8, ++0x28,0x10,0x05,0x23,0xDD,0xE9,0x02,0x02, ++0x01,0x99,0x00,0x93,0x18,0x23,0xFE,0xF7, ++0x4B,0xFD,0x04,0x00,0x0B,0xD0,0xB8,0xF1, ++0x02,0x0F,0x49,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x45,0xD4,0x08,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x08,0x3B,0xE0,0x04,0x9A, ++0x03,0x21,0x00,0x20,0xFE,0xF7,0xD4,0xFB, ++0xFE,0xF7,0xFF,0xFC,0xB0,0xB1,0x04,0x98, ++0x05,0x21,0x00,0xF0,0x08,0xF9,0x02,0x2F, ++0x0E,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x0A,0xD4,0x7F,0x1C,0xFF,0xB2,0x26,0xE0, ++0x0C,0x0A,0x00,0x80,0x00,0x50,0x00,0x25, ++0x20,0x15,0x03,0x20,0x80,0x96,0x98,0x00, ++0x73,0x4C,0x21,0xE0,0xFE,0xF7,0x02,0xFD, ++0x10,0xB1,0x71,0x4C,0x64,0x1E,0x1D,0xE0, ++0x18,0x20,0xAA,0xF8,0x44,0x00,0x04,0x21, ++0x6E,0x4A,0x50,0x46,0xFE,0xF7,0x50,0xFB, ++0x04,0x46,0xBA,0xF8,0x48,0x00,0x00,0xF0, ++0x06,0x01,0x21,0x43,0x0E,0xD0,0x02,0x2E, ++0x08,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFE,0xF7, ++0xA7,0xFC,0x74,0xE7,0x62,0x4C,0xA4,0x1E, ++0xFE,0xF7,0x72,0xFC,0x0A,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0xA4,0xE4,0x2D,0xE9,0xFE,0x4F, ++0x00,0x25,0xDF,0xF8,0x74,0x91,0x83,0x46, ++0x0C,0x46,0x2E,0x46,0x2F,0x46,0xA8,0x46, ++0xA9,0xF8,0x3C,0x50,0xDF,0xF8,0x64,0xA1, ++0x9A,0xF8,0x44,0x00,0x05,0x28,0x02,0xD0, ++0x05,0x20,0xFE,0xF7,0x66,0xFA,0x00,0x20, ++0x34,0xF8,0x10,0x10,0x09,0xEB,0x80,0x02, ++0xA2,0xF8,0x00,0x14,0x40,0x1C,0x80,0xB2, ++0xFF,0x28,0xF5,0xD9,0x9A,0xF8,0x7B,0x10, ++0x40,0x46,0x52,0x46,0x01,0xB9,0x09,0x20, ++0xDF,0xF8,0x30,0xA1,0x90,0x46,0x0B,0xFA, ++0x00,0xF1,0x4F,0xF0,0x06,0x0B,0x02,0x91, ++0x0A,0xF1,0x0C,0x0A,0x90,0x8F,0x92,0xF8, ++0x88,0x10,0x08,0x43,0x40,0xF0,0x20,0x00, ++0x01,0x90,0xFE,0xF7,0x79,0xFB,0x05,0x23, ++0x59,0x46,0x00,0x93,0x18,0x23,0xDD,0xE9, ++0x01,0x02,0xFE,0xF7,0xB1,0xFC,0x04,0x00, ++0x08,0xD0,0x02,0x2F,0x40,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x3C,0xD4,0x7F,0x1C, ++0xFF,0xB2,0x34,0xE0,0x03,0x21,0x00,0x20, ++0x52,0x46,0xFE,0xF7,0x3D,0xFB,0xFE,0xF7, ++0x68,0xFC,0x78,0xB1,0x05,0x21,0x50,0x46, ++0x00,0xF0,0x71,0xF8,0x02,0x2D,0x06,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x02,0xD4, ++0x6D,0x1C,0xED,0xB2,0x1F,0xE0,0x2C,0x4C, ++0xE4,0x1E,0x21,0xE0,0xFE,0xF7,0x72,0xFC, ++0x10,0xB1,0x29,0x4C,0x24,0x1F,0x1D,0xE0, ++0x18,0x20,0xA9,0xF8,0x44,0x00,0x04,0x21, ++0x26,0x4A,0x48,0x46,0xFE,0xF7,0xC0,0xFA, ++0x04,0x46,0xB9,0xF8,0x48,0x00,0x00,0xF0, ++0x06,0x01,0x21,0x43,0x0E,0xD0,0x02,0x2E, ++0x08,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFE,0xF7, ++0x17,0xFC,0xB2,0xE7,0x1A,0x4C,0x64,0x1F, ++0xFE,0xF7,0xE2,0xFB,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0xBD,0xE8,0xFE,0x8F,0x2D,0xE9, ++0xF0,0x47,0x00,0x24,0x15,0x4D,0x4F,0xF4, ++0x10,0x67,0x4F,0xF4,0x7A,0x79,0x4F,0xF0, ++0x80,0x76,0x05,0xF1,0x0D,0x08,0x28,0x88, ++0xFE,0xF7,0xAF,0xFD,0x40,0x46,0x01,0xF0, ++0xCC,0xEC,0x00,0xBA,0x29,0x7C,0x20,0xF0, ++0xFF,0x00,0x08,0x43,0xB8,0x42,0x05,0xD0, ++0x48,0x46,0xFE,0xF7,0xF7,0xF8,0x64,0x1C, ++0xB4,0x42,0xEC,0xD3,0xB4,0x42,0x03,0xD1, ++0x03,0x48,0x0B,0x30,0xBD,0xE8,0xF0,0x87, ++0x00,0x20,0xFB,0xE7,0xFE,0xE7,0x00,0x00, ++0x15,0x0A,0x00,0x80,0x40,0x4B,0x4C,0x00, ++0x00,0x50,0x00,0x25,0x20,0x15,0x03,0x20, ++0x3B,0x49,0x40,0x1E,0x01,0x42,0x00,0xD0, ++0xFE,0xE7,0x00,0x20,0x70,0x47,0x00,0x22, ++0x08,0xE0,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x10,0x32,0x8A,0x42,0xF4,0xDB, ++0x70,0x47,0x0B,0x46,0x00,0x21,0x30,0xB5, ++0x04,0xE0,0x44,0x5C,0x5D,0x5C,0xAC,0x42, ++0x02,0xD1,0x49,0x1C,0x91,0x42,0xF8,0xD3, ++0x91,0x42,0x11,0xD0,0x2B,0x4A,0x52,0x68, ++0xD2,0x06,0x0D,0xD4,0x4C,0x0A,0x4F,0xF4, ++0x00,0x75,0x64,0x02,0x29,0x46,0x20,0x44, ++0xFF,0xF7,0xD9,0xFF,0x18,0x19,0x29,0x46, ++0xFF,0xF7,0xD5,0xFF,0x24,0x48,0x30,0xBD, ++0x00,0x20,0x30,0xBD,0x03,0x46,0x00,0x20, ++0x02,0x46,0x10,0xB5,0x03,0xE0,0x9C,0x5C, ++0x52,0x1C,0x92,0xB2,0x20,0x44,0x8A,0x42, ++0xF9,0xD3,0x10,0xBD,0x00,0x21,0x1D,0xA2, ++0x10,0xB5,0x43,0x5C,0x54,0x5C,0xA3,0x42, ++0x01,0xD0,0x01,0x20,0x10,0xBD,0x49,0x1C, ++0x10,0x29,0xF6,0xDB,0x00,0x20,0x10,0xBD, ++0x00,0xB5,0xAD,0xF5,0x01,0x7D,0xF8,0xF7, ++0x7C,0xFF,0x00,0x28,0x05,0xD1,0x01,0xA8, ++0xFF,0xF7,0x4F,0xF9,0x03,0x00,0x03,0xD0, ++0x18,0x46,0x0D,0xF5,0x01,0x7D,0x00,0xBD, ++0x0C,0x48,0x10,0x21,0x1C,0x30,0xFF,0xF7, ++0xA2,0xFF,0x0A,0x48,0x10,0x21,0x2C,0x30, ++0xFF,0xF7,0x9D,0xFF,0xF0,0xE7,0x00,0x21, ++0x49,0x1C,0x10,0x29,0xFC,0xDB,0x00,0x7C, ++0x00,0x21,0x00,0xE0,0x49,0x1C,0x88,0x42, ++0xFC,0xDC,0x70,0x47,0x70,0x47,0x00,0x00, ++0x80,0x17,0x03,0x20,0x20,0x15,0x03,0x20, ++0x04,0x00,0x00,0x80,0x4D,0x53,0x54,0x41, ++0x52,0x53,0x45,0x4D,0x49,0x55,0x4E,0x46, ++0x44,0x43,0x49,0x53,0x00,0x00,0x00,0x00, ++0x10,0xB5,0x43,0x78,0x04,0x78,0x04,0xEB, ++0x03,0x23,0x84,0x78,0xC0,0x78,0x24,0x04, ++0x04,0xEB,0x00,0x60,0x18,0x44,0x08,0x41, ++0x20,0x2A,0x03,0xD0,0x4F,0xF0,0xFF,0x31, ++0x91,0x40,0x88,0x43,0x10,0xBD,0x30,0xB5, ++0x05,0x00,0x1C,0x46,0x4F,0xF0,0x00,0x00, ++0x0A,0xD0,0x8B,0x18,0x20,0x2B,0x04,0xD8, ++0x28,0x46,0xFF,0xF7,0xE1,0xFF,0x00,0x21, ++0x00,0xE0,0xFE,0x21,0x21,0x70,0x30,0xBD, ++0xFF,0x21,0xFB,0xE7,0xF0,0xB5,0xC2,0xF1, ++0x08,0x04,0x1B,0x1B,0x4F,0xF0,0xFF,0x3C, ++0x10,0x3B,0x06,0x78,0x0C,0xFA,0x04,0xF5, ++0xEF,0x43,0x21,0xEA,0x05,0x05,0x97,0x40, ++0xBE,0x43,0x95,0x40,0x2E,0x43,0x41,0xFA, ++0x04,0xF2,0x06,0x70,0x0C,0xFA,0x03,0xFC, ++0x42,0x70,0x04,0xF1,0x08,0x02,0x41,0xFA, ++0x02,0xF2,0x10,0x34,0x82,0x70,0xC2,0x78, ++0x21,0x41,0x21,0xEA,0x0C,0x01,0x02,0xEA, ++0x0C,0x02,0x0A,0x43,0xC2,0x70,0xF0,0xBD, ++0xF0,0xB5,0xC2,0xF1,0x08,0x04,0x1B,0x1B, ++0x4F,0xF0,0xFF,0x3C,0x08,0x3B,0x06,0x78, ++0x0C,0xFA,0x04,0xF5,0xEF,0x43,0x21,0xEA, ++0x05,0x05,0x97,0x40,0xBE,0x43,0x95,0x40, ++0x2E,0x43,0x41,0xFA,0x04,0xF2,0x06,0x70, ++0x0C,0xFA,0x03,0xFC,0x08,0x34,0x42,0x70, ++0x82,0x78,0x21,0x41,0x02,0xEA,0x0C,0x02, ++0x21,0xEA,0x0C,0x01,0x0A,0x43,0x82,0x70, ++0xF0,0xBD,0xF0,0xB5,0xC2,0xF1,0x08,0x04, ++0x4F,0xF0,0xFF,0x3C,0x1B,0x1B,0x06,0x78, ++0x0C,0xFA,0x04,0xF5,0xEF,0x43,0x21,0xEA, ++0x05,0x05,0x97,0x40,0xBE,0x43,0x95,0x40, ++0x2E,0x43,0x0C,0xFA,0x03,0xFC,0x06,0x70, ++0x21,0x41,0x42,0x78,0x21,0xEA,0x0C,0x01, ++0x02,0xEA,0x0C,0x02,0x0A,0x43,0x42,0x70, ++0xF0,0xBD,0x30,0xB5,0x4F,0xF0,0xFF,0x34, ++0x05,0x78,0x9C,0x40,0xE3,0x43,0xA1,0x43, ++0x93,0x40,0x9D,0x43,0x91,0x40,0x0D,0x43, ++0x05,0x70,0x30,0xBD,0x30,0xB5,0x00,0x24, ++0xB8,0xB1,0xD5,0x18,0x08,0x2D,0x02,0xD8, ++0xFF,0xF7,0xEB,0xFF,0x13,0xE0,0x10,0x2D, ++0x02,0xD8,0xFF,0xF7,0xCA,0xFF,0x0E,0xE0, ++0x18,0x2D,0x02,0xD8,0xFF,0xF7,0xA4,0xFF, ++0x09,0xE0,0x20,0x2D,0x02,0xD8,0xFF,0xF7, ++0x79,0xFF,0x04,0xE0,0x6F,0xF0,0x01,0x04, ++0x01,0xE0,0x4F,0xF0,0xFF,0x34,0x20,0x46, ++0x30,0xBD,0x38,0xB5,0x0C,0x46,0x20,0x22, ++0x00,0x21,0x05,0x46,0x6B,0x46,0xFF,0xF7, ++0x56,0xFF,0x20,0x60,0x20,0x22,0x00,0x21, ++0x28,0x1D,0x6B,0x46,0xFF,0xF7,0x4F,0xFF, ++0x60,0x60,0x20,0x22,0x00,0x21,0x6B,0x46, ++0x05,0xF1,0x08,0x00,0xFF,0xF7,0x47,0xFF, ++0xA0,0x60,0x00,0x21,0x28,0x7B,0x20,0x73, ++0x68,0x7B,0x60,0x73,0xA8,0x7B,0xA0,0x73, ++0x68,0x18,0x62,0x18,0x49,0x1C,0xC0,0x7B, ++0xC9,0xB2,0x10,0x29,0x10,0x74,0xF7,0xD3, ++0x38,0xBD,0x30,0xB5,0x04,0x46,0x0D,0x46, ++0x01,0x68,0x20,0x23,0x00,0x22,0x28,0x46, ++0xFF,0xF7,0xB0,0xFF,0x61,0x68,0x20,0x23, ++0x00,0x22,0x28,0x1D,0xFF,0xF7,0xAA,0xFF, ++0xA1,0x68,0x20,0x23,0x00,0x22,0x05,0xF1, ++0x08,0x00,0xFF,0xF7,0xA3,0xFF,0x20,0x7B, ++0x28,0x73,0x30,0xBD,0x10,0xB5,0x04,0x46, ++0x01,0x20,0xFA,0xF7,0xA9,0xFE,0x21,0x46, ++0xBD,0xE8,0x10,0x40,0xFA,0xF7,0xE6,0xB9, ++0x10,0xB5,0x04,0x46,0x00,0x20,0xFA,0xF7, ++0x9F,0xFE,0x21,0x46,0xBD,0xE8,0x10,0x40, ++0xFA,0xF7,0xDC,0xB9,0x8A,0xB2,0x02,0x60, ++0x09,0x0C,0x41,0x60,0x70,0x47,0x41,0x68, ++0x00,0x68,0x61,0xF3,0x1F,0x40,0x70,0x47, ++0x00,0x21,0x01,0x22,0x83,0x79,0x13,0x42, ++0x05,0xD0,0x83,0x79,0x93,0x43,0x83,0x71, ++0x49,0x1C,0x48,0xB2,0x70,0x47,0x49,0x1C, ++0x52,0x00,0x49,0xB2,0x01,0x29,0x52,0xB2, ++0xF0,0xDB,0x4F,0xF0,0xFF,0x30,0x70,0x47, ++0x8A,0x79,0x40,0x1E,0x01,0x23,0x83,0x40, ++0x1A,0x43,0x8A,0x71,0x70,0x47,0x00,0xEB, ++0x80,0x00,0x10,0xB5,0x02,0xEB,0xC0,0x00, ++0x90,0xF8,0x53,0x00,0x8A,0x07,0x04,0xD5, ++0x0C,0x22,0x08,0x28,0x05,0xD3,0x0D,0x22, ++0x03,0xE0,0x10,0x22,0x08,0x28,0x00,0xD3, ++0x11,0x22,0xC6,0x4B,0x13,0x44,0x1A,0x78, ++0x00,0xF0,0x07,0x04,0x01,0x20,0xA0,0x40, ++0xC9,0x07,0xC0,0xB2,0x01,0xD0,0x02,0x43, ++0x00,0xE0,0x82,0x43,0x1A,0x70,0x10,0xBD, ++0x2D,0xE9,0xFF,0x5F,0x0F,0x46,0x9A,0x46, ++0x00,0x98,0x00,0xEB,0x80,0x01,0x03,0xEB, ++0xC1,0x04,0xE0,0x6D,0xE1,0x6C,0x00,0xEB, ++0x01,0x08,0xA0,0x6C,0xE1,0x6C,0x4F,0xF0, ++0xFF,0x3C,0x45,0x1A,0x40,0x2D,0x04,0xD3, ++0x50,0x46,0xFF,0xF7,0xAD,0xFF,0x06,0x1E, ++0x03,0xDA,0x60,0x46,0x04,0xB0,0xBD,0xE8, ++0xF0,0x9F,0xB4,0xF8,0x42,0x00,0xA8,0x42, ++0x02,0xD2,0x47,0xF0,0x04,0x07,0x0E,0xE0, ++0xB8,0x07,0x06,0xD5,0xB4,0xF8,0x42,0x00, ++0xA8,0x42,0x08,0xD2,0xB4,0xF8,0x42,0x50, ++0x05,0xE0,0xB4,0xF8,0x44,0x00,0xA8,0x42, ++0x01,0xD2,0xB4,0xF8,0x44,0x50,0x94,0xF8, ++0x53,0x00,0x40,0xF2,0x01,0x61,0x47,0xEA, ++0x00,0x10,0x08,0x43,0x1F,0xFA,0x80,0xF9, ++0x40,0x46,0x00,0xF0,0xC7,0xFD,0xA0,0x49, ++0x01,0xEB,0x46,0x12,0x01,0x46,0x10,0x46, ++0xFF,0xF7,0x74,0xFF,0x9C,0x48,0xA9,0xB2, ++0x08,0x30,0x00,0xEB,0x46,0x10,0x01,0x60, ++0x29,0x0C,0x41,0x60,0xDF,0xF8,0x5C,0x82, ++0x98,0xF8,0x1C,0xB0,0x94,0xF8,0x53,0x00, ++0x88,0xF8,0x1C,0x00,0x17,0xF0,0x06,0x00, ++0x18,0xD0,0x02,0x28,0x22,0xD0,0x04,0x28, ++0x2A,0xD0,0x06,0x28,0x0A,0xD1,0x00,0x98, ++0x03,0x21,0x52,0x46,0xFF,0xF7,0x7B,0xFF, ++0x98,0xF8,0x25,0x00,0x40,0xF0,0x94,0x00, ++0x88,0xF8,0x25,0x00,0x88,0xF8,0x1C,0xB0, ++0x08,0xEB,0x46,0x11,0xA1,0xF8,0xE8,0x93, ++0x01,0x20,0xA7,0xE7,0x98,0xF8,0x2D,0x40, ++0x01,0x21,0x00,0x98,0x52,0x46,0xFF,0xF7, ++0x66,0xFF,0x24,0xF0,0xA8,0x00,0x88,0xF8, ++0x2D,0x00,0xEB,0xE7,0x00,0x98,0x03,0x21, ++0x52,0x46,0xFF,0xF7,0x5C,0xFF,0x98,0xF8, ++0x25,0x00,0x20,0xF0,0x94,0x00,0xDF,0xE7, ++0x98,0xF8,0x2D,0x70,0x08,0xEB,0x46,0x11, ++0xA1,0xF8,0xE8,0x93,0x01,0x21,0x00,0x98, ++0x52,0x46,0xFF,0xF7,0x4C,0xFF,0x9A,0xF8, ++0x2A,0x00,0x40,0x07,0x02,0xD5,0x47,0xF0, ++0xE8,0x00,0x01,0xE0,0x47,0xF0,0xA8,0x00, ++0x88,0xF8,0x2D,0x00,0x00,0x20,0x88,0xF8, ++0x2C,0x00,0x9A,0xF8,0x30,0x00,0xA8,0xB9, ++0xB8,0xF8,0x14,0x01,0x00,0xF4,0x00,0x50, ++0xA8,0xF8,0x14,0x01,0xB4,0xF8,0x42,0x10, ++0x28,0x46,0x02,0xF0,0x82,0xE9,0xB8,0xF8, ++0x14,0x11,0x08,0x43,0xA8,0xF8,0x14,0x01, ++0xB8,0xF8,0x14,0x01,0x40,0xF4,0x00,0x40, ++0xA8,0xF8,0x14,0x01,0x88,0xF8,0x1C,0xB0, ++0xB2,0xE7,0x60,0x49,0x01,0xEB,0x40,0x10, ++0xB0,0xF8,0xE8,0x13,0x21,0xF0,0x01,0x01, ++0xA0,0xF8,0xE8,0x13,0x70,0x47,0x5B,0x49, ++0x01,0xEB,0x40,0x10,0xB0,0xF8,0xE8,0x03, ++0x70,0x47,0x2D,0xE9,0xF8,0x4F,0x07,0x46, ++0xDF,0xF8,0x58,0x81,0x0D,0x46,0x08,0xEB, ++0x40,0x12,0x02,0xF5,0x7A,0x72,0xB2,0xF8, ++0x00,0x90,0x10,0x88,0x00,0xF0,0x0F,0x06, ++0x51,0x48,0x00,0xEB,0x47,0x10,0xFF,0xF7, ++0xDE,0xFE,0x82,0x46,0x4E,0x48,0x08,0x30, ++0x00,0xEB,0x47,0x10,0xFF,0xF7,0xD7,0xFE, ++0x00,0x90,0x10,0x88,0xC0,0xF3,0x03,0x1B, ++0x0B,0xEB,0x8B,0x00,0x05,0xEB,0xC0,0x04, ++0xE0,0x6D,0xE1,0x6C,0x08,0x44,0x00,0xF0, ++0x12,0xFD,0xE1,0x6C,0xAA,0xEB,0x00,0x00, ++0x08,0x44,0xE0,0x64,0x98,0xF8,0x1C,0xA0, ++0x94,0xF8,0x53,0x10,0x88,0xF8,0x1C,0x10, ++0x29,0x46,0x78,0xB2,0xFF,0xF7,0xD4,0xFE, ++0xB0,0x07,0x41,0x46,0x05,0xD5,0x11,0xF8, ++0x25,0x0F,0x20,0xF0,0x94,0x00,0x08,0x70, ++0x0C,0xE0,0x91,0xF8,0x2D,0x00,0x95,0xF8, ++0x2A,0x20,0x52,0x07,0x02,0xD5,0x20,0xF0, ++0xE8,0x00,0x01,0xE0,0x20,0xF0,0xA8,0x00, ++0x81,0xF8,0x2D,0x00,0x5F,0xEA,0xC9,0x50, ++0x08,0xD5,0xB1,0x07,0x4F,0xF0,0xEC,0x00, ++0x02,0xD5,0xE8,0x76,0xBD,0xE8,0xF8,0x8F, ++0xA8,0x76,0xFB,0xE7,0xB0,0x07,0x4F,0xF0, ++0x01,0x07,0x4F,0xF0,0x00,0x09,0x1C,0xD5, ++0xE0,0x6C,0xA1,0x6C,0x88,0x42,0x13,0xD1, ++0xB4,0xF8,0x42,0x10,0xE0,0x6C,0x02,0xF0, ++0xFC,0xE8,0x11,0xB1,0x84,0xF8,0x55,0x70, ++0x0A,0xE0,0x70,0x07,0x03,0xD5,0x84,0xF8, ++0x55,0x70,0x48,0x46,0xE1,0xE7,0x28,0x7F, ++0xC0,0xF3,0x01,0x10,0x02,0x28,0xF1,0xD0, ++0x88,0xF8,0x24,0x70,0x85,0xF8,0x1B,0x90, ++0x1E,0xE0,0x01,0x21,0x2A,0x46,0x58,0x46, ++0xFF,0xF7,0x91,0xFE,0x00,0x98,0xA4,0xF8, ++0x44,0x00,0xB4,0xF8,0x44,0x00,0x68,0xB9, ++0xB4,0xF8,0x42,0x10,0xE0,0x6C,0x02,0xF0, ++0xD8,0xE8,0x11,0xB1,0x84,0xF8,0x55,0x70, ++0x04,0xE0,0x70,0x07,0x02,0xD5,0x84,0xF8, ++0x55,0x70,0x18,0xE0,0x08,0xF1,0x2C,0x01, ++0x08,0x78,0x20,0xF0,0x01,0x00,0x08,0x70, ++0x88,0xF8,0x1C,0xA0,0xB0,0x07,0xB5,0xD4, ++0xB4,0xF8,0x44,0x00,0x10,0xB9,0x94,0xF8, ++0x55,0x00,0x18,0xB9,0xE0,0x6C,0xA1,0x6C, ++0x88,0x42,0xAB,0xD3,0x28,0x7F,0xC0,0xF3, ++0x01,0x10,0x01,0x28,0xA6,0xD0,0x48,0x46, ++0xA6,0xE7,0x00,0x00,0x00,0x40,0x00,0x25, ++0xF0,0x43,0x00,0x25,0x7C,0xB5,0x04,0x46, ++0x90,0xF8,0x2B,0x00,0x02,0x28,0x15,0xD1, ++0x40,0x22,0x00,0x23,0x02,0x21,0xCD,0xE9, ++0x00,0x24,0x1A,0x46,0x18,0x46,0xFA,0xF7, ++0x9B,0xFD,0x4F,0xF4,0x00,0x75,0x00,0x23, ++0xCD,0xE9,0x00,0x54,0x02,0x22,0x01,0x20, ++0x19,0x46,0xFA,0xF7,0x91,0xFD,0x23,0x46, ++0x2A,0x46,0x17,0xE0,0x94,0xF8,0x2B,0x00, ++0x01,0x28,0x1B,0xD1,0x40,0x22,0x00,0x23, ++0x02,0x21,0xCD,0xE9,0x00,0x24,0x1A,0x46, ++0x18,0x46,0xFA,0xF7,0x81,0xFD,0x40,0x22, ++0x00,0x23,0xCD,0xE9,0x00,0x24,0x02,0x22, ++0x01,0x20,0x19,0x46,0xFA,0xF7,0x78,0xFD, ++0x40,0x22,0x23,0x46,0xCD,0xE9,0x00,0x23, ++0x02,0x22,0x00,0x23,0x01,0x21,0x10,0x46, ++0xFA,0xF7,0x6E,0xFD,0x7C,0xBD,0x00,0xEB, ++0x80,0x02,0x70,0xB5,0x01,0xEB,0xC2,0x04, ++0x02,0x25,0xE3,0x6D,0x0A,0x46,0xC1,0xB2, ++0x18,0x46,0xFA,0xF7,0x89,0xFD,0x94,0xF8, ++0x55,0x00,0x18,0xB1,0x0A,0x25,0x02,0x20, ++0x84,0xF8,0x56,0x00,0x28,0x46,0x70,0xBD, ++0x2D,0xE9,0xF0,0x41,0x04,0x46,0x90,0xF8, ++0xE0,0x00,0x1E,0x25,0x4F,0xF0,0x01,0x06, ++0x10,0xF0,0x60,0x0F,0x17,0xD0,0x94,0xF8, ++0xE0,0x00,0xC0,0xF3,0x41,0x10,0x01,0x28, ++0x06,0xD1,0x94,0xF8,0xE1,0x00,0xFE,0x28, ++0x03,0xD0,0xFF,0x28,0xF8,0xD1,0xD2,0x25, ++0xA7,0xE1,0x26,0x66,0xE4,0x65,0x94,0xF8, ++0xE0,0x00,0x00,0xF0,0x1F,0x00,0x01,0x28, ++0xF6,0xD1,0x69,0x25,0x9D,0xE1,0x94,0xF8, ++0xE1,0x00,0x02,0x23,0xFF,0x4F,0x00,0x22, ++0x0C,0x28,0xED,0xD2,0xDF,0xE8,0x00,0xF0, ++0x06,0x35,0x4F,0x82,0x4F,0xF9,0xF8,0xF7, ++0xF6,0xF5,0xF4,0xF3,0x62,0x81,0xB4,0xF8, ++0xE6,0x00,0x20,0x66,0x04,0xF1,0x0A,0x00, ++0xE0,0x65,0x94,0xF8,0xE0,0x00,0xC0,0x06, ++0x08,0xD1,0x94,0xF8,0x22,0x00,0x00,0xB1, ++0x63,0x81,0x60,0x89,0x40,0xF0,0x01,0x00, ++0x60,0x81,0xDA,0xE7,0x94,0xF8,0xE0,0x00, ++0x00,0xF0,0x1F,0x00,0x01,0x28,0xD4,0xD0, ++0x94,0xF8,0xE0,0x00,0x00,0xF0,0x1F,0x00, ++0x02,0x28,0xC5,0xD1,0xB4,0xF8,0xE4,0x00, ++0x10,0xF0,0x0F,0x00,0xC0,0xD0,0x00,0xEB, ++0x80,0x00,0x04,0xEB,0xC0,0x00,0x90,0xF8, ++0x57,0x00,0x00,0x28,0xC1,0xD0,0x66,0x81, ++0xBF,0xE7,0x94,0xF8,0x27,0x00,0x03,0x28, ++0xB2,0xD3,0x94,0xF8,0xE0,0x00,0xC0,0x06, ++0x07,0xD1,0xB4,0xF8,0xE2,0x00,0xC0,0xB2, ++0x01,0x28,0xA9,0xD1,0x84,0xF8,0x22,0x20, ++0xA5,0xE7,0x94,0xF8,0xE0,0x00,0x00,0xF0, ++0x1F,0x00,0x01,0x28,0x04,0xD1,0x94,0xF8, ++0x27,0x00,0x04,0x28,0x9B,0xD0,0x44,0xE1, ++0x94,0xF8,0xE0,0x00,0x00,0xF0,0x1F,0x00, ++0x02,0x28,0x95,0xD1,0x94,0xF8,0x27,0x00, ++0x03,0x28,0x04,0xD1,0xB4,0xF8,0xE4,0x00, ++0x10,0xF0,0xFF,0x0F,0x8C,0xD1,0xB4,0xF8, ++0xE2,0x00,0x10,0xF0,0xFF,0x0F,0x87,0xD1, ++0xB4,0xF8,0xE4,0x00,0x10,0xF0,0x0F,0x00, ++0x81,0xD0,0x90,0x46,0x00,0xEB,0x80,0x00, ++0x04,0xEB,0xC0,0x05,0x53,0x35,0x2A,0x71, ++0x28,0x78,0xFA,0xF7,0xDB,0xFB,0x68,0x78, ++0x10,0xB1,0x80,0x20,0x2C,0x37,0x01,0xE0, ++0x40,0x20,0x24,0x37,0x38,0x70,0x87,0xF8, ++0x00,0x80,0x00,0x20,0xFA,0xF7,0xCE,0xFB, ++0x26,0x71,0x68,0xE7,0x94,0xF8,0x27,0x00, ++0x02,0x28,0xC8,0xD3,0x94,0xF8,0xE0,0x00, ++0xC0,0x06,0x26,0xD1,0xB4,0xF8,0xE2,0x00, ++0xC0,0xB2,0x01,0x28,0x02,0xD1,0x84,0xF8, ++0x22,0x60,0x58,0xE7,0xB4,0xF8,0xE2,0x00, ++0xC0,0xB2,0x02,0x28,0x03,0xD1,0xB4,0xF8, ++0xE4,0x00,0x20,0x81,0x4F,0xE7,0xB4,0xF8, ++0xE2,0x00,0xC0,0xB2,0x03,0x28,0x05,0xD1, ++0x60,0x79,0x00,0x28,0xAB,0xD0,0x84,0xF8, ++0x23,0x60,0x44,0xE7,0xB4,0xF8,0xE2,0x00, ++0xC0,0xB2,0x04,0x28,0xA3,0xD1,0x60,0x79, ++0x00,0x28,0xA0,0xD0,0x84,0xF8,0x24,0x60, ++0x39,0xE7,0x94,0xF8,0xE0,0x00,0x00,0xF0, ++0x1F,0x00,0x01,0x28,0x13,0xD1,0x94,0xF8, ++0x27,0x00,0x04,0x28,0x93,0xD1,0xB4,0xF8, ++0xE2,0x00,0xC0,0xB2,0x03,0x28,0xC0,0xD0, ++0xB4,0xF8,0xE2,0x00,0xC0,0xB2,0x04,0x28, ++0xBB,0xD0,0xB4,0xF8,0xE2,0x00,0xC0,0xB2, ++0x05,0x28,0xB6,0xD0,0xC9,0xE0,0x94,0xF8, ++0xE0,0x00,0x00,0xF0,0x1F,0x00,0x02,0x28, ++0xF8,0xD1,0x94,0xF8,0x27,0x00,0x03,0x28, ++0x04,0xD1,0xB4,0xF8,0xE4,0x00,0x10,0xF0, ++0xFF,0x0F,0xEF,0xD1,0xB4,0xF8,0xE2,0x00, ++0x10,0xF0,0xFF,0x0F,0xEA,0xD1,0xB4,0xF8, ++0xE4,0x00,0x10,0xF0,0x0F,0x00,0x9C,0xD0, ++0x00,0xEB,0x80,0x00,0x04,0xEB,0xC0,0x04, ++0x53,0x34,0x26,0x71,0x20,0x78,0xFA,0xF7, ++0x61,0xFB,0x60,0x78,0x50,0xB1,0x20,0x20, ++0x87,0xF8,0x2C,0x00,0x09,0xE0,0x98,0xE0, ++0x8C,0xE0,0x6F,0xE0,0x68,0xE0,0x5F,0xE0, ++0x19,0xE0,0x06,0xE0,0x10,0x20,0x87,0xF8, ++0x24,0x00,0x00,0x20,0xFA,0xF7,0x4E,0xFB, ++0xE9,0xE6,0xB4,0xF8,0xE2,0x00,0x7F,0x28, ++0x3D,0xD8,0xB4,0xF8,0xE2,0x00,0x84,0xF8, ++0x29,0x00,0x94,0xF8,0x27,0x00,0x02,0x28, ++0x8C,0xD1,0x94,0xF8,0x29,0x00,0x00,0x28, ++0x88,0xD0,0xE2,0x70,0xD7,0xE6,0xB4,0xF8, ++0xE2,0x00,0x01,0x0A,0x01,0x29,0x07,0xD0, ++0x02,0x29,0x05,0xD0,0x03,0x29,0x03,0xD0, ++0x06,0x29,0x01,0xD0,0x07,0x29,0x74,0xD1, ++0x94,0xF8,0x30,0x00,0x00,0x28,0x70,0xD1, ++0x04,0xF5,0xA0,0x70,0x41,0xC8,0x94,0xF8, ++0x2B,0x70,0x02,0x2F,0x05,0xD1,0x00,0xF8, ++0x52,0x2F,0x43,0x70,0xC2,0x71,0x03,0x72, ++0x52,0x38,0x00,0x28,0x61,0xD0,0x00,0x2E, ++0x5F,0xDD,0xB4,0xF8,0xE2,0x20,0xD2,0xB2, ++0x43,0x78,0x8B,0x42,0x02,0xD1,0x3A,0xB1, ++0x52,0x1E,0xD2,0xB2,0x03,0x78,0xF6,0x1A, ++0x18,0x44,0x00,0x2E,0xF4,0xDC,0x50,0xE0, ++0x00,0x2E,0x4E,0xDD,0x02,0x29,0x01,0xD0, ++0x07,0x29,0x04,0xD1,0xC2,0x78,0x81,0x78, ++0x01,0xEB,0x02,0x21,0x00,0xE0,0x01,0x78, ++0xB4,0xF8,0xE6,0x20,0x8A,0x42,0x01,0xDA, ++0xB4,0xF8,0xE6,0x10,0x21,0x66,0x32,0xE0, ++0xB4,0xF8,0xE6,0x10,0x04,0xF1,0xE8,0x00, ++0x21,0x66,0xE0,0x65,0xE1,0x25,0x34,0xE0, ++0xB4,0xF8,0xE6,0x00,0x20,0x66,0x04,0xF1, ++0x25,0x00,0x24,0xE0,0x94,0xF8,0x27,0x00, ++0x03,0x28,0x2A,0xD3,0xB4,0xF8,0xE2,0x00, ++0x10,0xF0,0xFF,0x0F,0x04,0xD1,0x03,0x20, ++0x21,0x46,0xF9,0xF7,0xFD,0xFD,0x76,0xE6, ++0xB4,0xF8,0xE2,0x00,0x10,0xF0,0xFF,0x0F, ++0x1B,0xD0,0xB4,0xF8,0xE2,0x00,0x84,0xF8, ++0x25,0x00,0x04,0x20,0x21,0x46,0xF9,0xF7, ++0xEF,0xFD,0x0E,0xE0,0x94,0xF8,0x27,0x00, ++0x04,0x28,0x0E,0xD1,0xB4,0xF8,0xE6,0x00, ++0x20,0x66,0x04,0xF1,0x26,0x00,0xE0,0x65, ++0x67,0xE6,0x94,0xF8,0x27,0x00,0x04,0x28, ++0x00,0xD1,0xD2,0x25,0x20,0x46,0xFF,0xF7, ++0xED,0xFD,0x28,0x46,0xBD,0xE8,0xF0,0x81, ++0x2D,0xE9,0xF0,0x4F,0x05,0x46,0x8F,0xB0, ++0x0C,0x46,0x38,0x22,0x2E,0xA1,0x68,0x46, ++0x00,0xF0,0xA4,0xEE,0x95,0xF9,0x09,0x80, ++0x00,0x26,0xFF,0x20,0x60,0x76,0x08,0xF0, ++0xFF,0x00,0x83,0x46,0xFA,0xF7,0xA2,0xFA, ++0x26,0x4F,0xB8,0xF1,0x00,0x0F,0x4F,0xF0, ++0x01,0x0A,0xB1,0x46,0x7E,0xD1,0x20,0x89, ++0x08,0x22,0x48,0xB3,0x20,0x89,0xB0,0xF5, ++0x80,0x7F,0x01,0xD1,0x02,0x20,0x78,0x77, ++0x20,0x89,0xB0,0xF5,0x00,0x7F,0x01,0xD1, ++0x04,0x20,0x78,0x77,0x20,0x89,0xB0,0xF5, ++0x40,0x7F,0x01,0xD1,0x87,0xF8,0x1D,0xA0, ++0x20,0x89,0xB0,0xF5,0x80,0x6F,0x11,0xD1, ++0x94,0xF8,0x53,0x00,0x15,0x49,0xEC,0x46, ++0x40,0x31,0x01,0xEB,0xC0,0x03,0x00,0x20, ++0x1C,0xF8,0x00,0x10,0x40,0x1C,0x35,0x28, ++0x19,0x70,0xF9,0xDB,0x02,0x20,0x87,0xF8, ++0x24,0x00,0x7A,0x77,0xA4,0xF8,0x08,0x90, ++0x28,0x88,0x40,0x07,0x04,0xD5,0x02,0x20, ++0x84,0xF8,0x56,0x00,0x87,0xF8,0x24,0x90, ++0x28,0x88,0xC0,0x06,0x05,0xD5,0x80,0x26, ++0x02,0x20,0x84,0xF8,0x56,0x00,0x87,0xF8, ++0x24,0x60,0x94,0xF8,0x56,0x00,0x02,0x28, ++0x74,0xD1,0x28,0x88,0xC0,0x07,0x66,0xD0, ++0x40,0x26,0x1D,0xE0,0x00,0x40,0x00,0x25, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, ++0xAA,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, ++0xEE,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0xBF,0xDF, ++0xEF,0xF7,0xFB,0xFD,0xFC,0x7E,0xBF,0xDF, ++0xEF,0xF7,0xFB,0xFD,0x7E,0x00,0x00,0x00, ++0x68,0x88,0xA4,0xF8,0x44,0x00,0xA2,0x64, ++0xC4,0xF8,0x4C,0x90,0x04,0xF1,0xE0,0x00, ++0x0E,0x90,0x00,0x21,0x22,0x46,0xFA,0xF7, ++0x42,0xFA,0x0E,0x98,0xF9,0xF7,0x65,0xFD, ++0x20,0x46,0xFF,0xF7,0xA9,0xFD,0xC0,0xB2, ++0x87,0xF8,0x1C,0x90,0xD2,0x28,0x12,0xD1, ++0x48,0x26,0x00,0xE0,0x68,0xE0,0xE0,0x78, ++0x60,0xB9,0x94,0xF8,0x29,0x00,0x48,0xB1, ++0x94,0xF8,0x27,0x00,0x03,0x28,0x2D,0xD2, ++0x03,0x20,0x21,0x46,0xF9,0xF7,0x30,0xFD, ++0x84,0xF8,0x03,0xA0,0x26,0xE0,0xE1,0x28, ++0x09,0xD1,0x87,0xF8,0x24,0x60,0x84,0xF8, ++0x56,0xA0,0xC4,0xF8,0x4C,0x90,0xB4,0xF8, ++0xE6,0x00,0xA0,0x64,0xCE,0xE0,0x69,0x28, ++0x0B,0xD1,0x87,0xF8,0x24,0x60,0x00,0x26, ++0x84,0xF8,0x56,0x90,0x84,0xF8,0x55,0x90, ++0xC4,0xF8,0x4C,0x90,0x20,0x6E,0xA0,0x64, ++0x0C,0xE0,0x60,0x26,0x0A,0xE0,0xE0,0x78, ++0x10,0xB1,0x94,0xF8,0x29,0x00,0x38,0x70, ++0x48,0x46,0x84,0xF8,0x03,0x90,0x21,0x79, ++0x01,0xB1,0x20,0x71,0x94,0xF8,0x56,0x00, ++0x20,0xB9,0x00,0x20,0x21,0x46,0xFF,0xF7, ++0x4E,0xFD,0x06,0x46,0x94,0xF8,0x56,0x00, ++0x01,0x28,0x18,0xD1,0x28,0x88,0xC0,0x07, ++0x15,0xD0,0x68,0x88,0xA4,0xF8,0x44,0x00, ++0xE0,0x6D,0x00,0x21,0x22,0x46,0xFA,0xF7, ++0xE6,0xF9,0xE0,0x6C,0xA1,0x6C,0x88,0x42, ++0x07,0xD3,0x08,0x20,0x02,0x21,0x84,0xF8, ++0x56,0x10,0x87,0xF8,0x1C,0x90,0x87,0xF8, ++0x24,0x00,0x40,0x20,0x8C,0xE0,0x00,0x2E, ++0x09,0xD0,0x87,0xF8,0x24,0x60,0x94,0xF8, ++0x23,0x00,0x00,0x28,0x03,0xD0,0x03,0x20, ++0x21,0x46,0xFA,0xF7,0x36,0xFA,0x81,0xE0, ++0x28,0x79,0xEC,0x21,0x01,0x28,0x28,0x88, ++0x5D,0xD1,0x42,0x06,0x01,0xD4,0xC0,0x07, ++0x03,0xD1,0x61,0x76,0x87,0xF8,0x2C,0x60, ++0x74,0xE0,0x08,0xEB,0x88,0x00,0x04,0xEB, ++0xC0,0x06,0x96,0xF8,0x57,0x00,0x18,0xB1, ++0x20,0x20,0x87,0xF8,0x2C,0x00,0x69,0xE0, ++0x68,0x88,0xA6,0xF8,0x44,0x00,0xB6,0xF8, ++0x44,0x00,0x1E,0x28,0x07,0xD0,0xB6,0xF8, ++0x44,0x00,0x1F,0x28,0x03,0xD0,0xB6,0xF8, ++0x44,0x00,0x20,0x28,0x33,0xD1,0xC6,0xF8, ++0x4C,0x90,0x69,0x88,0xB1,0x64,0x61,0x69, ++0xF1,0x65,0xC6,0xF8,0x60,0x90,0xB6,0xF8, ++0x44,0x00,0xB6,0xF8,0x42,0x10,0x88,0x42, ++0x06,0xD3,0xF1,0x6C,0xB6,0xF8,0x44,0x00, ++0x01,0x44,0xB0,0x6C,0x81,0x42,0x01,0xD3, ++0x50,0x46,0x00,0xE0,0x48,0x46,0x86,0xF8, ++0x55,0x00,0xF0,0x6D,0x22,0x46,0x59,0x46, ++0xFA,0xF7,0x85,0xF9,0xB6,0xF8,0x44,0x00, ++0x10,0xB9,0x96,0xF8,0x55,0x00,0x18,0xB9, ++0xF1,0x6C,0xB0,0x6C,0x81,0x42,0x01,0xD3, ++0x84,0xF8,0x19,0x90,0x38,0x8E,0x26,0xF8, ++0x44,0x0F,0x30,0x88,0x08,0xB9,0x87,0xF8, ++0x2C,0x90,0x50,0x46,0x05,0xE0,0xB6,0xF8, ++0x44,0x00,0x08,0xB1,0x84,0xF8,0x1E,0xA0, ++0x48,0x46,0x60,0x77,0x1E,0xE0,0x80,0x06, ++0x05,0xD5,0x61,0x76,0x87,0xF8,0x24,0x90, ++0x0F,0xB0,0xBD,0xE8,0xF0,0x8F,0x08,0xEB, ++0x88,0x00,0x04,0xEB,0xC0,0x00,0x90,0xF8, ++0x55,0x10,0x11,0xB1,0x84,0xF8,0x19,0x90, ++0x0C,0xE0,0x90,0xF8,0x57,0x10,0x09,0xB1, ++0x10,0x20,0x05,0xE0,0xC0,0x6D,0x22,0x46, ++0x59,0x46,0xFA,0xF7,0x39,0xFA,0x50,0x46, ++0x87,0xF8,0x24,0x00,0x60,0x7E,0xFF,0x28, ++0xE2,0xD0,0x08,0xEB,0x88,0x00,0x04,0xEB, ++0xC0,0x00,0x90,0xF8,0x52,0x10,0xC1,0xF3, ++0x01,0x11,0x01,0x29,0xD8,0xD0,0x80,0xF8, ++0x56,0x90,0xB0,0xF8,0x44,0x10,0x00,0x29, ++0xD2,0xD0,0xC0,0x6D,0x0F,0xB0,0x22,0x46, ++0x59,0x46,0xBD,0xE8,0xF0,0x4F,0xFA,0xF7, ++0x2E,0xB9,0x00,0x00,0x10,0xB5,0x04,0x46, ++0xFA,0xF7,0x66,0xF9,0x94,0xF8,0x2A,0x00, ++0xC0,0x07,0x04,0xD0,0x28,0x34,0xA0,0x78, ++0xC0,0x09,0x20,0x70,0x10,0xBD,0x02,0x20, ++0x84,0xF8,0x28,0x00,0x10,0xBD,0x70,0xB5, ++0x04,0x46,0x0D,0x46,0x28,0x46,0xFA,0xF7, ++0xFB,0xF9,0xEC,0x77,0x4C,0xB1,0x11,0x2C, ++0x01,0xD0,0x21,0x2C,0x0F,0xD1,0xFA,0xF7, ++0x83,0xF9,0x02,0x28,0x0B,0xDA,0x00,0x24, ++0xF0,0xE7,0x00,0x20,0x29,0x46,0xFA,0xF7, ++0x63,0xF9,0x29,0x46,0x00,0x20,0xBD,0xE8, ++0x70,0x40,0xFA,0xF7,0x43,0xB9,0x70,0xBD, ++0x00,0x22,0x10,0xB5,0x02,0x24,0x13,0x46, ++0x02,0xEB,0x82,0x01,0x00,0xEB,0xC1,0x01, ++0x44,0x31,0x8C,0x74,0x0B,0x80,0x4B,0x60, ++0x8B,0x60,0x4B,0x74,0xCB,0x74,0x52,0x1C, ++0xD2,0xB2,0x04,0x2A,0xF0,0xD3,0x10,0xBD, ++0x2D,0xE9,0xF0,0x41,0x05,0x46,0x42,0x4E, ++0x00,0x06,0x0C,0x46,0x09,0xD5,0x00,0x20, ++0x21,0x46,0xFF,0xF7,0xC4,0xFF,0x96,0xF8, ++0xC0,0x00,0x40,0xF0,0x01,0x00,0x86,0xF8, ++0xC0,0x00,0xE8,0x06,0x4F,0xF0,0x00,0x07, ++0x0B,0xD5,0x84,0xF8,0x29,0x70,0x94,0xF8, ++0x29,0x00,0x30,0x70,0x20,0x46,0xFF,0xF7, ++0xA1,0xFF,0x23,0x20,0x21,0x46,0xFF,0xF7, ++0xAE,0xFF,0xA8,0x06,0x4F,0xF0,0x7F,0x08, ++0x08,0xD5,0x04,0xF8,0x21,0x7F,0xA7,0x71, ++0x67,0x73,0xA7,0x73,0x04,0xF8,0x1B,0x8C, ++0x27,0x75,0x21,0x3C,0x68,0x07,0x4E,0xD5, ++0x20,0x46,0xFF,0xF7,0x8B,0xFF,0x94,0xF8, ++0x2A,0x00,0x40,0x07,0x20,0xD4,0x20,0x46, ++0xFF,0xF7,0xB2,0xFF,0x84,0xF8,0x06,0x80, ++0x84,0xF8,0x29,0x70,0x02,0x20,0x21,0x46, ++0xF9,0xF7,0xB2,0xFB,0x94,0xF8,0x20,0x00, ++0x18,0xB9,0x11,0x20,0x21,0x46,0xFF,0xF7, ++0x86,0xFF,0x20,0x46,0xFA,0xF7,0xD8,0xF8, ++0x20,0x7E,0xC1,0x06,0x4F,0xF0,0x01,0x00, ++0x03,0xD5,0x02,0x21,0x84,0xF8,0x2B,0x10, ++0x01,0xE0,0x84,0xF8,0x2B,0x00,0xE0,0x71, ++0x94,0xF8,0x30,0x00,0x00,0x28,0x22,0xD1, ++0x67,0x77,0x01,0x20,0xFF,0xF7,0xEB,0xFA, ++0x00,0xF0,0xFE,0x00,0xA6,0xF8,0x08,0x04, ++0xFA,0xF7,0xDA,0xF8,0xB6,0xF8,0x0C,0x01, ++0x40,0xF0,0x02,0x00,0xA6,0xF8,0x0C,0x01, ++0xB6,0xF8,0x14,0x01,0x40,0xF4,0xC0,0x40, ++0xA6,0xF8,0x14,0x01,0x94,0xF8,0x2B,0x00, ++0x01,0x28,0xB6,0xF8,0x14,0x01,0x02,0xD1, ++0x40,0xF0,0x80,0x00,0x01,0xE0,0x40,0xF0, ++0x10,0x00,0xA6,0xF8,0x14,0x01,0xBD,0xE8, ++0xF0,0x81,0xC0,0x7F,0x00,0xF0,0x0F,0x00, ++0x01,0x28,0x00,0xD0,0x00,0x20,0x70,0x47, ++0x00,0x40,0x00,0x25,0x70,0x47,0x70,0x47, ++0x1E,0xFF,0x2F,0xE1,0x70,0x40,0x2D,0xE9, ++0x03,0x40,0xA0,0xE1,0x02,0x50,0xA0,0xE1, ++0x01,0x30,0xA0,0xE1,0x00,0x20,0xA0,0xE1, ++0x00,0x00,0x54,0xE3,0x04,0xC0,0xA0,0x11, ++0x05,0xC0,0xA0,0x01,0x1C,0xEF,0x6F,0xE1, ++0x01,0x00,0x8E,0xE2,0x1C,0xC0,0xA0,0xE1, ++0x3F,0xE0,0x7E,0x12,0x1F,0xE0,0x7E,0x02, ++0x85,0x00,0x00,0x4A,0x00,0x00,0x53,0xE3, ++0x13,0x1F,0x6F,0x11,0x12,0x1F,0x6F,0x01, ++0x3F,0x10,0x71,0x12,0x1F,0x10,0x71,0x02, ++0x0E,0x60,0x51,0xE0,0x83,0x00,0x00,0x4A, ++0x04,0x00,0x76,0x52,0x84,0x00,0x00,0x5A, ++0x20,0x00,0x4E,0xE2,0x04,0x00,0x50,0xE3, ++0x35,0xC0,0x8C,0xD1,0x2C,0xCE,0xA0,0xE1, ++0x8F,0x1F,0x8F,0xE2,0x0C,0xC1,0x91,0xE7, ++0x1F,0x00,0x5E,0xE3,0x20,0xE0,0x4E,0x82, ++0x20,0x60,0x6E,0xE2,0x40,0x00,0x00,0x8A, ++0x9C,0x05,0x81,0xE0,0x11,0x16,0xA0,0xE1, ++0x30,0x1E,0x81,0xE1,0x10,0x06,0xA0,0xE1, ++0x00,0x00,0x70,0xE2,0x00,0x10,0xE1,0xE2, ++0x9C,0x01,0x81,0xE0,0x01,0xC0,0x8C,0xE0, ++0x9C,0x05,0x81,0xE0,0x11,0x16,0xA0,0xE1, ++0x30,0x1E,0x81,0xE1,0x10,0x06,0xA0,0xE1, ++0x00,0x00,0x70,0xE2,0x00,0x10,0xE1,0xE2, ++0x00,0x00,0x53,0xE3,0x9C,0x01,0x81,0xE0, ++0x01,0xC0,0x8C,0xE0,0x07,0x00,0x00,0x0A, ++0x9C,0x05,0x81,0xE0,0x11,0x16,0xA0,0xE1, ++0x30,0x1E,0x81,0xE1,0x10,0x06,0xA0,0xE1, ++0x00,0x00,0x70,0xE2,0x00,0x10,0xE1,0xE2, ++0x9C,0x01,0x81,0xE0,0x01,0xC0,0x8C,0xE0, ++0x9C,0x12,0x80,0xE0,0x00,0x10,0xA0,0xE3, ++0x9C,0x03,0xA1,0xE0,0x30,0x0E,0xA0,0xE1, ++0x11,0x06,0x80,0xE1,0x90,0x65,0x84,0xE0, ++0x31,0x1E,0xA0,0xE1,0x91,0x45,0x24,0xE0, ++0x06,0x20,0x52,0xE0,0x04,0x30,0xC3,0xE0, ++0x01,0x00,0x53,0xE3,0x05,0x00,0x52,0x31, ++0x70,0x80,0xBD,0x38,0x9C,0x42,0x86,0xE0, ++0x00,0x40,0xA0,0xE3,0x9C,0x63,0xA4,0xE0, ++0x00,0x30,0xA0,0xE3,0x20,0xC0,0x6E,0xE2, ++0x36,0x6E,0xA0,0xE1,0x14,0x6C,0x86,0xE1, ++0x34,0x4E,0xA0,0xE1,0x96,0xE5,0x8C,0xE0, ++0x06,0x00,0x90,0xE0,0x04,0x10,0xA1,0xE0, ++0x0E,0x20,0x42,0xE0,0x05,0x00,0x52,0xE1, ++0x70,0x80,0xBD,0x38,0x01,0x00,0x90,0xE2, ++0x00,0x10,0xA1,0xE2,0x05,0x20,0x42,0xE0, ++0x05,0xC0,0x52,0xE0,0x0C,0x20,0xA0,0x21, ++0x00,0x00,0xB0,0xE2,0x00,0x10,0xA1,0xE2, ++0x05,0xC0,0x52,0xE0,0x0C,0x20,0xA0,0x21, ++0x00,0x00,0xB0,0xE2,0x00,0x10,0xA1,0xE2, ++0x70,0x80,0xBD,0xE8,0x9C,0x15,0x80,0xE0, ++0x00,0x10,0xA0,0xE3,0x9C,0x04,0xA1,0xE0, ++0x11,0x16,0xA0,0xE1,0x30,0x1E,0x81,0xE1, ++0x10,0x06,0xA0,0xE1,0x00,0x00,0x70,0xE2, ++0x00,0x10,0xE1,0xE2,0x9C,0x01,0x81,0xE0, ++0x01,0xC0,0x8C,0xE0,0x9C,0x15,0x80,0xE0, ++0x00,0x10,0xA0,0xE3,0x9C,0x04,0xA1,0xE0, ++0x11,0x16,0xA0,0xE1,0x30,0x1E,0x81,0xE1, ++0x10,0x06,0xA0,0xE1,0x00,0x00,0x70,0xE2, ++0x00,0x10,0xE1,0xE2,0x9C,0x01,0x81,0xE0, ++0x01,0xC0,0x8C,0xE0,0x01,0xC0,0x4C,0xE2, ++0x9C,0x12,0x80,0xE0,0x00,0x10,0xA0,0xE3, ++0x9C,0x03,0xA1,0xE0,0x31,0x0E,0xA0,0xE1, ++0x90,0x65,0x81,0xE0,0x06,0x20,0x52,0xE0, ++0x90,0x14,0x21,0xE0,0x01,0x30,0xC3,0xE0, ++0x04,0x00,0x53,0xE1,0x05,0x00,0x52,0x01, ++0x00,0x10,0xA0,0x33,0x70,0x80,0xBD,0x38, ++0x9C,0x62,0x81,0xE0,0x00,0x60,0xA0,0xE3, ++0x9C,0x13,0xA6,0xE0,0x00,0x10,0xA0,0xE3, ++0x36,0x6E,0xA0,0xE1,0x96,0xE5,0x8C,0xE0, ++0x06,0x00,0x80,0xE0,0x0E,0x20,0x52,0xE0, ++0x96,0xC4,0x2E,0xE0,0x0E,0x30,0xC3,0xE0, ++0x04,0x00,0x53,0xE1,0x05,0x00,0x52,0x01, ++0x70,0x80,0xBD,0x38,0x01,0x00,0x80,0xE2, ++0x05,0x20,0x52,0xE0,0x04,0x30,0xC3,0xE0, ++0x70,0x80,0xBD,0xE8,0x0C,0x00,0x2D,0xE9, ++0x00,0x10,0xA0,0xE3,0x00,0x00,0xA0,0xE3, ++0x41,0x02,0x00,0xEB,0x7C,0x80,0xBD,0xE8, ++0x00,0x10,0xA0,0xE3,0x00,0x00,0xA0,0xE3, ++0x70,0x80,0xBD,0xE8,0x20,0xE0,0x66,0xE2, ++0x00,0x00,0xA0,0xE3,0x00,0x10,0xA0,0xE3, ++0x14,0x46,0xA0,0xE1,0x35,0x4E,0x84,0xE1, ++0x15,0x56,0xA0,0xE1,0x05,0xE0,0x52,0xE0, ++0x04,0xC0,0xD3,0xE0,0x00,0x00,0xA0,0xE0, ++0x0C,0x30,0xA0,0x21,0x0E,0x20,0xA0,0x21, ++0x01,0x60,0x56,0xE2,0x70,0x80,0xBD,0x38, ++0xA4,0x40,0xB0,0xE1,0x65,0x50,0xA0,0xE1, ++0xF5,0xFF,0xFF,0xEA,0xF0,0xF0,0xF0,0xF0, ++0xE3,0x38,0x8E,0xE3,0xE5,0x35,0x94,0xD7, ++0xCC,0xCC,0xCC,0xCC,0xC3,0x30,0x0C,0xC3, ++0xA2,0x8B,0x2E,0xBA,0xC8,0x42,0x16,0xB2, ++0xAA,0xAA,0xAA,0xAA,0x3D,0x0A,0xD7,0xA3, ++0x9D,0xD8,0x89,0x9D,0xED,0x25,0xB4,0x97, ++0x92,0x24,0x49,0x92,0x08,0xCB,0x3D,0x8D, ++0x88,0x88,0x88,0x88,0x42,0x08,0x21,0x84, ++0x00,0x00,0x00,0x80,0x7C,0xB5,0x0C,0x00, ++0x15,0x00,0x00,0x29,0x00,0x90,0x01,0xD0, ++0x00,0x19,0x40,0x1E,0x6A,0x46,0x07,0x49, ++0x79,0x44,0x01,0x90,0x28,0x00,0x00,0xF0, ++0x4A,0xFD,0x05,0x00,0x00,0x2C,0x03,0xD0, ++0x69,0x46,0x00,0x20,0x00,0xF0,0x56,0xFD, ++0x28,0x00,0x7C,0xBD,0xCB,0x0A,0x00,0x00, ++0x0F,0xB4,0x7C,0xB5,0x0C,0x00,0x09,0xAB, ++0x00,0x90,0x01,0xD0,0x00,0x19,0x40,0x1E, ++0x6A,0x46,0x09,0x49,0x79,0x44,0x01,0x90, ++0x08,0x98,0x00,0xF0,0x30,0xFD,0x05,0x00, ++0x00,0x2C,0x03,0xD0,0x69,0x46,0x00,0x20, ++0x00,0xF0,0x3C,0xFD,0x28,0x00,0x7C,0xBC, ++0x08,0xBC,0x04,0xB0,0x18,0x47,0x00,0x00, ++0x97,0x0A,0x00,0x00,0x9B,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0xF0,0xB5,0x15,0x00, ++0x1F,0xB4,0x82,0xB0,0x1E,0x00,0x02,0x98, ++0x00,0x68,0x00,0x05,0x02,0xD5,0x27,0x4F, ++0x7F,0x44,0x02,0xE0,0x25,0x4F,0x7F,0x44, ++0x0E,0x37,0x02,0x98,0x00,0x24,0x24,0x30, ++0x01,0x90,0x09,0xE0,0x28,0x07,0x01,0x99, ++0x00,0x0F,0x2D,0x09,0x38,0x5C,0x08,0x55, ++0x30,0x07,0x64,0x1C,0x05,0x43,0x36,0x09, ++0x00,0x23,0x31,0x00,0x28,0x00,0x59,0x40, ++0x58,0x40,0x08,0x43,0xEE,0xD1,0x02,0x98, ++0x3A,0x00,0x00,0x68,0x00,0x07,0x09,0xD5, ++0x03,0x98,0x70,0x28,0x02,0xD1,0x10,0x32, ++0x01,0x23,0x03,0xE0,0x00,0x2C,0x01,0xD0, ++0x11,0x32,0x02,0x23,0x02,0x98,0x21,0x00, ++0x00,0xF0,0x37,0xFC,0x07,0xB0,0xF0,0xBD, ++0x70,0xB5,0x04,0x00,0x0D,0x00,0x10,0x68, ++0x21,0x00,0x00,0xF0,0xFA,0xFB,0x02,0x00, ++0x00,0x23,0x29,0x00,0x20,0x00,0xFF,0xF7, ++0xB9,0xFF,0x70,0xBD,0xD2,0x1D,0xD3,0x08, ++0xDB,0x00,0x0C,0xCB,0xB2,0xE7,0x30,0xB4, ++0x03,0x68,0x20,0x24,0x12,0x68,0x23,0x43, ++0x03,0x60,0x08,0x23,0xC3,0x61,0x30,0xBC, ++0x00,0x23,0xA7,0xE7,0xA0,0x20,0x00,0x00, ++0xF3,0xB5,0x05,0x00,0x00,0x20,0x81,0xB0, ++0xBE,0xE0,0xE9,0x68,0x28,0x00,0x88,0x47, ++0x00,0x28,0x7E,0xD0,0x25,0x28,0x02,0xD0, ++0x6A,0x68,0xA9,0x68,0xB1,0xE0,0x5C,0x4F, ++0x00,0x26,0x7F,0x44,0xE9,0x68,0x28,0x00, ++0x88,0x47,0x04,0x00,0x20,0x28,0x08,0xDB, ++0x31,0x2C,0x06,0xD2,0x38,0x19,0x20,0x38, ++0x00,0x78,0x00,0x28,0x01,0xD0,0x06,0x43, ++0xF0,0xE7,0xB0,0x07,0x01,0xD5,0x04,0x20, ++0x86,0x43,0x00,0x20,0xE8,0x61,0x07,0x00, ++0xA8,0x61,0x2A,0x2C,0x11,0xD1,0x02,0x98, ++0xBA,0x00,0x52,0x19,0x02,0xC8,0x91,0x61, ++0x02,0x90,0xE9,0x68,0x28,0x00,0x88,0x47, ++0x04,0x00,0x01,0x2F,0x26,0xD1,0xE8,0x69, ++0x00,0x28,0x2E,0xDA,0x20,0x20,0x86,0x43, ++0x2B,0xE0,0x20,0x00,0x30,0x38,0x01,0x22, ++0x01,0x00,0x0A,0x28,0x18,0xD2,0x00,0x2A, ++0x16,0xD0,0xB8,0x00,0x40,0x19,0x00,0x90, ++0x81,0x61,0x07,0xE0,0x00,0x98,0x0A,0x21, ++0x80,0x69,0x48,0x43,0x00,0x99,0x00,0x19, ++0x30,0x38,0x88,0x61,0xE9,0x68,0x28,0x00, ++0x88,0x47,0x04,0x00,0x01,0x21,0x30,0x38, ++0x0A,0x28,0x01,0xD2,0x00,0x29,0xED,0xD1, ++0x01,0x2F,0x0A,0xD0,0x2E,0x2C,0x08,0xD1, ++0xE9,0x68,0x28,0x00,0x88,0x47,0x04,0x00, ++0x20,0x20,0x06,0x43,0x7F,0x1C,0x02,0x2F, ++0xBF,0xDB,0xA8,0x69,0x00,0x28,0x03,0xDA, ++0x40,0x42,0xA8,0x61,0x01,0x20,0x06,0x43, ++0xF0,0x07,0x01,0xD0,0x10,0x20,0x86,0x43, ++0x6C,0x2C,0x01,0xD0,0x68,0x2C,0x17,0xD1, ++0xE9,0x68,0x27,0x00,0x28,0x00,0x88,0x47, ++0x04,0x00,0xB8,0x42,0x0A,0xD1,0x80,0x20, ++0x6C,0x2F,0x00,0xD0,0xC0,0x00,0xE9,0x68, ++0x06,0x43,0x28,0x00,0x88,0x47,0x04,0x00, ++0x16,0xE0,0x3B,0xE0,0x40,0x20,0x6C,0x2F, ++0x00,0xD0,0x80,0x00,0x06,0x43,0x0F,0xE0, ++0x4C,0x2C,0x05,0xD0,0x6A,0x2C,0x03,0xD0, ++0x74,0x2C,0x01,0xD0,0x7A,0x2C,0x07,0xD1, ++0x00,0x20,0x4C,0x2C,0xE7,0xD0,0x80,0x20, ++0x6A,0x2C,0xE4,0xD0,0x00,0x20,0xE2,0xE7, ++0x00,0x2C,0x23,0xD0,0x20,0x00,0x41,0x38, ++0x19,0x28,0x03,0xD8,0x01,0x20,0xC0,0x02, ++0x06,0x43,0x20,0x34,0x2E,0x60,0x02,0x9A, ++0x21,0x00,0x28,0x00,0x16,0x00,0xF4,0xF7, ++0x06,0xED,0x00,0x28,0x0A,0xD0,0x01,0x28, ++0x02,0xD1,0x36,0x1D,0x02,0x96,0x4C,0xE7, ++0xF6,0x1D,0xF0,0x08,0xC0,0x00,0x08,0x30, ++0x02,0x90,0x46,0xE7,0x6A,0x68,0xA9,0x68, ++0x20,0x00,0x90,0x47,0x28,0x6A,0x40,0x1C, ++0x28,0x62,0x3E,0xE7,0x28,0x6A,0xFE,0xBD, ++0x06,0x20,0x00,0x00,0xF7,0xB5,0x82,0xB0, ++0x0F,0x00,0x02,0x9C,0x00,0x26,0x00,0xF0, ++0xD8,0xEA,0x01,0x90,0x00,0x68,0x00,0x90, ++0x25,0x78,0x64,0x1C,0x00,0x2D,0x05,0xD0, ++0x00,0xF0,0xC0,0xEA,0x00,0x68,0x40,0x5D, ++0xC0,0x07,0xF5,0xD1,0x2B,0x2D,0x06,0xD0, ++0x2D,0x2D,0x03,0xD1,0x01,0x20,0x80,0x02, ++0x06,0x43,0x00,0xE0,0x64,0x1E,0x01,0x98, ++0x00,0x21,0x01,0x60,0x04,0x9A,0x39,0x00, ++0x20,0x00,0x00,0xF0,0xE1,0xFC,0x01,0x00, ++0x00,0x2F,0x04,0xD0,0x38,0x68,0xA0,0x42, ++0x01,0xD1,0x02,0x98,0x38,0x60,0x01,0x98, ++0x00,0x68,0x02,0x28,0x05,0xD0,0x01,0x98, ++0x00,0x9A,0x02,0x60,0x48,0x42,0x72,0x05, ++0x00,0xD4,0x08,0x00,0x05,0xB0,0xF0,0xBD, ++0x03,0x00,0x0B,0x43,0xF0,0xB5,0x9B,0x07, ++0x28,0xD1,0x21,0x4E,0xF7,0x01,0x04,0x2A, ++0x24,0xD3,0x08,0xC8,0x10,0xC9,0x12,0x1F, ++0x9D,0x1B,0x9D,0x43,0x3D,0x40,0x01,0xD1, ++0xA3,0x42,0xF4,0xD0,0x18,0x06,0x21,0x06, ++0x00,0x0E,0x09,0x0E,0x40,0x1A,0x29,0x06, ++0x01,0x43,0x12,0xD1,0x18,0x04,0x21,0x04, ++0x00,0x0C,0x09,0x0C,0x40,0x1A,0x29,0x04, ++0x01,0x43,0x0A,0xD1,0x18,0x02,0x21,0x02, ++0x00,0x0A,0x09,0x0A,0x40,0x1A,0x29,0x02, ++0x01,0x43,0x02,0xD1,0x18,0x0E,0x21,0x0E, ++0x40,0x1A,0xF0,0xBD,0x00,0x2A,0x01,0xD1, ++0x00,0x20,0xF0,0xBD,0x03,0x78,0x0C,0x78, ++0x40,0x1C,0x49,0x1C,0x00,0x2B,0x0D,0xD0, ++0xA3,0x42,0x0B,0xD1,0x52,0x1E,0x09,0xD0, ++0x03,0x78,0x0C,0x78,0x40,0x1C,0x49,0x1C, ++0x00,0x2B,0x03,0xD0,0xA3,0x42,0x01,0xD1, ++0x52,0x1E,0xEB,0xD1,0x18,0x1B,0xF0,0xBD, ++0x01,0x01,0x01,0x01,0x30,0xB5,0x44,0x1C, ++0x05,0xE0,0x01,0x78,0x40,0x1C,0x00,0x29, ++0x01,0xD1,0x00,0x1B,0x30,0xBD,0x81,0x07, ++0xF7,0xD1,0x0A,0x4B,0xDD,0x01,0x04,0xC8, ++0xD1,0x1A,0x91,0x43,0x29,0x40,0xFA,0xD0, ++0x00,0x1B,0x0A,0x06,0x01,0xD0,0xC0,0x1E, ++0x30,0xBD,0x0A,0x04,0x01,0xD0,0x80,0x1E, ++0x30,0xBD,0x09,0x02,0xFC,0xD0,0x40,0x1E, ++0x30,0xBD,0x00,0x00,0x01,0x01,0x01,0x01, ++0xFF,0x30,0x02,0xE2,0x03,0x24,0x83,0xE1, ++0x02,0x28,0x82,0xE1,0x35,0x00,0x00,0xEA, ++0x03,0x00,0x52,0xE3,0x2A,0x00,0x00,0x9A, ++0x03,0xC0,0x10,0xE2,0x08,0x00,0x00,0x0A, ++0x01,0x30,0xD1,0xE4,0x02,0x00,0x5C,0xE3, ++0x0C,0x20,0x82,0xE0,0x01,0xC0,0xD1,0x94, ++0x01,0x30,0xC0,0xE4,0x01,0x30,0xD1,0x34, ++0x01,0xC0,0xC0,0x94,0x04,0x20,0x42,0xE2, ++0x01,0x30,0xC0,0x34,0x03,0x30,0x11,0xE2, ++0x4B,0x00,0x00,0x0A,0x04,0x20,0x52,0xE2, ++0x1B,0x00,0x00,0x3A,0x03,0xC0,0x31,0xE7, ++0x02,0x00,0x53,0xE3,0x08,0x00,0x00,0x0A, ++0x0F,0x00,0x00,0x8A,0x2C,0x34,0xA0,0xE1, ++0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2, ++0x0C,0x3C,0x83,0xE1,0x04,0x30,0x80,0xE4, ++0xF9,0xFF,0xFF,0x2A,0x01,0x10,0x81,0xE2, ++0x0F,0x00,0x00,0xEA,0x2C,0x38,0xA0,0xE1, ++0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2, ++0x0C,0x38,0x83,0xE1,0x04,0x30,0x80,0xE4, ++0xF9,0xFF,0xFF,0x2A,0x02,0x10,0x81,0xE2, ++0x07,0x00,0x00,0xEA,0x2C,0x3C,0xA0,0xE1, ++0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2, ++0x0C,0x34,0x83,0xE1,0x04,0x30,0x80,0xE4, ++0xF9,0xFF,0xFF,0x2A,0x03,0x10,0x81,0xE2, ++0x00,0x00,0xA0,0xE1,0x82,0x2F,0xB0,0xE1, ++0x01,0x30,0xD1,0x24,0x01,0xC0,0xD1,0x24, ++0x01,0x20,0xD1,0x44,0x01,0x30,0xC0,0x24, ++0x01,0xC0,0xC0,0x24,0x01,0x20,0xC0,0x44, ++0x1E,0xFF,0x2F,0xE1,0x00,0x20,0xA0,0xE3, ++0x04,0x00,0x51,0xE3,0x07,0x00,0x00,0x3A, ++0x03,0xC0,0x10,0xE2,0x0C,0x00,0x00,0x0A, ++0x04,0xC0,0x6C,0xE2,0x02,0x00,0x5C,0xE3, ++0x01,0x20,0xC0,0x14,0x0C,0x10,0x41,0xE0, ++0xB2,0x20,0xC0,0xA0,0x06,0x00,0x00,0xEA, ++0x81,0xCF,0xB0,0xE1,0x01,0x20,0xC0,0x24, ++0x01,0x20,0xC0,0x24,0x01,0x20,0xC0,0x44, ++0x1E,0xFF,0x2F,0xE1,0x78,0x47,0xC0,0x46, ++0x00,0x20,0xA0,0xE3,0x00,0x40,0x2D,0xE9, ++0x02,0x30,0xA0,0xE1,0x02,0xC0,0xA0,0xE1, ++0x02,0xE0,0xA0,0xE1,0x20,0x10,0x51,0xE2, ++0x0C,0x50,0xA0,0x28,0x0C,0x50,0xA0,0x28, ++0x20,0x10,0x51,0x22,0xFB,0xFF,0xFF,0x2A, ++0x01,0x1E,0xB0,0xE1,0x0C,0x50,0xA0,0x28, ++0x0C,0x00,0xA0,0x48,0x00,0x40,0xBD,0xE8, ++0x01,0x11,0xB0,0xE1,0x04,0x20,0x80,0x24, ++0x1E,0xFF,0x2F,0x01,0xB2,0x20,0xC0,0x40, ++0x01,0x01,0x11,0xE3,0x01,0x20,0xC0,0x14, ++0x1E,0xFF,0x2F,0xE1,0xF0,0x41,0x2D,0xE9, ++0x20,0x20,0x52,0xE2,0x0B,0x00,0x00,0x3A, ++0x80,0x00,0x52,0xE3,0x05,0x00,0x00,0x3A, ++0x80,0xF0,0xD1,0xF5,0xF8,0x51,0xB1,0xE8, ++0x20,0x20,0x42,0xE2,0x80,0x00,0x52,0xE3, ++0xF8,0x51,0xA0,0xE8,0xF9,0xFF,0xFF,0x2A, ++0xF8,0x51,0xB1,0xE8,0x20,0x20,0x52,0xE2, ++0xF8,0x51,0xA0,0xE8,0xFB,0xFF,0xFF,0x2A, ++0x02,0xCE,0xB0,0xE1,0x18,0x50,0xB1,0x28, ++0x18,0x50,0xA0,0x28,0x18,0x00,0xB1,0x48, ++0x18,0x00,0xA0,0x48,0xF0,0x41,0xBD,0xE8, ++0x02,0xCF,0xB0,0xE1,0x04,0x30,0x91,0x24, ++0x04,0x30,0x80,0x24,0x1E,0xFF,0x2F,0x01, ++0x82,0x2F,0xB0,0xE1,0xB2,0x30,0xD1,0x20, ++0x01,0x20,0xD1,0x44,0xB2,0x30,0xC0,0x20, ++0x01,0x20,0xC0,0x44,0x1E,0xFF,0x2F,0xE1, ++0x03,0x00,0x10,0xE3,0x03,0x00,0x11,0x03, ++0x17,0x00,0x00,0x1A,0x00,0x40,0x2D,0xE9, ++0x84,0xE0,0x9F,0xE5,0x04,0x20,0x90,0xE4, ++0x04,0x30,0x91,0xE4,0x0E,0xC0,0x42,0xE0, ++0x02,0xC0,0xCC,0xE1,0x8E,0xC3,0x1C,0xE0, ++0x03,0x00,0x52,0x01,0xF8,0xFF,0xFF,0x0A, ++0x00,0x40,0xBD,0xE8,0x03,0x0C,0xA0,0xE1, ++0x02,0x0C,0x50,0xE0,0xFF,0x0E,0x1C,0x03, ++0x07,0x00,0x00,0x1A,0x03,0x08,0xA0,0xE1, ++0x02,0x08,0x50,0xE0,0xFF,0x0C,0x1C,0x03, ++0x03,0x00,0x00,0x1A,0x03,0x04,0xA0,0xE1, ++0x02,0x04,0x50,0xE0,0xFF,0x08,0x1C,0x03, ++0x02,0x00,0x53,0x00,0x60,0x00,0xA0,0x11, ++0x1E,0xFF,0x2F,0xE1,0x01,0x20,0xD0,0xE4, ++0x01,0x30,0xD1,0xE4,0x01,0x00,0x52,0xE3, ++0x03,0x00,0x52,0x21,0x04,0x00,0x00,0x1A, ++0x01,0x20,0xD0,0xE4,0x01,0x30,0xD1,0xE4, ++0x01,0x00,0x52,0xE3,0x03,0x00,0x52,0x21, ++0xF5,0xFF,0xFF,0x0A,0x03,0x00,0x42,0xE0, ++0x1E,0xFF,0x2F,0xE1,0x01,0x01,0x01,0x01, ++0x01,0x20,0xD0,0xE5,0x00,0x10,0xD0,0xE5, ++0x02,0x30,0xD0,0xE5,0x03,0x00,0xD0,0xE5, ++0x02,0x14,0x81,0xE1,0x03,0x18,0x81,0xE1, ++0x00,0x0C,0x81,0xE1,0x1E,0xFF,0x2F,0xE1, ++0x20,0x24,0xA0,0xE1,0x00,0x00,0xC1,0xE5, ++0x01,0x20,0xC1,0xE5,0x20,0x28,0xA0,0xE1, ++0x02,0x20,0xC1,0xE5,0x20,0x2C,0xA0,0xE1, ++0x03,0x20,0xC1,0xE5,0x1E,0xFF,0x2F,0xE1, ++0x01,0x30,0x90,0xE1,0x21,0x00,0x00,0x4A, ++0x00,0x20,0xB0,0xE3,0xA0,0x30,0x71,0xE0, ++0x1A,0x00,0x00,0x3A,0x20,0x32,0x71,0xE0, ++0x0F,0x00,0x00,0x3A,0x20,0x34,0x71,0xE0, ++0x01,0x00,0x00,0x3A,0x00,0xC0,0xA0,0xE3, ++0x20,0x00,0x00,0xEA,0xA0,0x33,0x71,0xE0, ++0x81,0x03,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x20,0x33,0x71,0xE0,0x01,0x03,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0xA0,0x32,0x71,0xE0, ++0x81,0x02,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x20,0x32,0x71,0xE0,0x01,0x02,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0xA0,0x31,0x71,0xE0, ++0x81,0x01,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x20,0x31,0x71,0xE0,0x01,0x01,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0xA0,0x30,0x71,0xE0, ++0x81,0x00,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x01,0x10,0x50,0xE0,0x00,0x10,0xA0,0x31, ++0x02,0x00,0xA2,0xE0,0x1E,0xFF,0x2F,0xE1, ++0x02,0x21,0x11,0xE2,0x00,0x10,0x61,0x42, ++0x40,0xC0,0x32,0xE0,0x00,0x00,0x60,0x22, ++0x20,0x32,0x71,0xE0,0x1D,0x00,0x00,0x3A, ++0x20,0x34,0x71,0xE0,0x0F,0x00,0x00,0x3A, ++0x01,0x13,0xA0,0xE1,0x20,0x34,0x71,0xE0, ++0x3F,0x23,0x82,0xE3,0x0B,0x00,0x00,0x3A, ++0x01,0x13,0xA0,0xE1,0x20,0x34,0x71,0xE0, ++0x3F,0x26,0x82,0xE3,0x07,0x00,0x00,0x3A, ++0x01,0x13,0xA0,0xE1,0x20,0x34,0x71,0xE0, ++0x3F,0x29,0x82,0xE3,0x01,0x13,0xA0,0x21, ++0x3F,0x2C,0x82,0x23,0x00,0x30,0x71,0xE2, ++0x1D,0x00,0x00,0x2A,0x21,0x13,0xA0,0x21, ++0xA0,0x33,0x71,0xE0,0x81,0x03,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0x20,0x33,0x71,0xE0, ++0x01,0x03,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0xA0,0x32,0x71,0xE0,0x81,0x02,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0x20,0x32,0x71,0xE0, ++0x01,0x02,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0xA0,0x31,0x71,0xE0,0x81,0x01,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0x20,0x31,0x71,0xE0, ++0x01,0x01,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0xEB,0xFF,0xFF,0x2A,0xA0,0x30,0x71,0xE0, ++0x81,0x00,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x01,0x10,0x50,0xE0,0x00,0x10,0xA0,0x31, ++0x02,0x00,0xA2,0xE0,0xCC,0xCF,0xB0,0xE1, ++0x00,0x00,0x60,0x42,0x00,0x10,0x61,0x22, ++0x1E,0xFF,0x2F,0xE1,0xCC,0xCF,0xB0,0xE1, ++0x00,0x00,0x60,0x42,0x01,0x40,0x2D,0xE9, ++0x00,0x00,0xB0,0xE3,0x05,0x00,0x00,0xEB, ++0x02,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9, ++0x48,0x01,0x00,0xEB,0x04,0x00,0x90,0xE2, ++0x10,0x80,0xBD,0xE8,0xB8,0x16,0x00,0x00, ++0x40,0x01,0x00,0xEA,0x3F,0x01,0x00,0xEA, ++0x04,0x00,0x9F,0xE5,0x1E,0xFF,0x2F,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x8C,0x17,0x03,0x20, ++0x70,0xB5,0x85,0x69,0x04,0x00,0x00,0x68, ++0x30,0x26,0xC1,0x06,0x00,0xD4,0x20,0x26, ++0xC0,0x07,0x09,0xD1,0x06,0xE0,0x62,0x68, ++0xA1,0x68,0x30,0x00,0x90,0x47,0x20,0x6A, ++0x40,0x1C,0x20,0x62,0x6D,0x1E,0xF6,0xD5, ++0x70,0xBD,0x70,0xB5,0x85,0x69,0x04,0x00, ++0x00,0x68,0xC0,0x07,0x09,0xD0,0x06,0xE0, ++0x62,0x68,0xA1,0x68,0x20,0x20,0x90,0x47, ++0x20,0x6A,0x40,0x1C,0x20,0x62,0x6D,0x1E, ++0xF6,0xD5,0x70,0xBD,0x09,0x68,0x4A,0x05, ++0x02,0xD5,0x00,0x06,0x00,0x16,0x70,0x47, ++0xC9,0x05,0xFC,0xD5,0x00,0x04,0x00,0x14, ++0x70,0x47,0x09,0x68,0x4A,0x05,0x02,0xD5, ++0x00,0x06,0x00,0x0E,0x70,0x47,0xC9,0x05, ++0xFC,0xD5,0x00,0x04,0x00,0x0C,0x70,0x47, ++0x70,0xB5,0x05,0x00,0x0C,0x00,0x01,0x2A, ++0x01,0xD1,0x01,0x20,0x0B,0xE0,0x28,0x68, ++0x80,0x06,0x00,0xD5,0xEA,0x69,0x00,0x20, ++0x00,0xE0,0x40,0x1C,0x90,0x42,0x02,0xD2, ++0x21,0x5C,0x00,0x29,0xF9,0xD1,0xA9,0x69, ++0x26,0x18,0x09,0x1A,0xA9,0x61,0x29,0x6A, ++0x09,0x18,0x28,0x00,0x29,0x62,0xFF,0xF7, ++0xA7,0xFF,0x04,0xE0,0x6A,0x68,0x20,0x78, ++0xA9,0x68,0x64,0x1C,0x90,0x47,0xB4,0x42, ++0xF8,0xD3,0x28,0x00,0xFF,0xF7,0xB1,0xFF, ++0x70,0xBD,0xFF,0xB5,0x04,0x00,0x81,0xB0, ++0x24,0x30,0x0D,0x00,0x00,0x90,0x21,0x68, ++0x88,0x06,0x04,0xD5,0x10,0x22,0xE0,0x69, ++0x91,0x43,0x21,0x60,0x00,0xE0,0x01,0x20, ++0x00,0x27,0xA8,0x42,0x00,0xDD,0x47,0x1B, ++0x04,0x98,0xA1,0x69,0x7A,0x19,0x10,0x18, ++0x08,0x1A,0xA0,0x61,0x20,0x68,0xC0,0x06, ++0x02,0xD4,0x20,0x00,0xFF,0xF7,0x7C,0xFF, ++0x00,0x26,0x08,0xE0,0x03,0x98,0x62,0x68, ++0xA1,0x68,0x80,0x5D,0x90,0x47,0x20,0x6A, ++0x40,0x1C,0x76,0x1C,0x20,0x62,0x04,0x98, ++0x86,0x42,0xF3,0xDB,0x20,0x68,0xC0,0x06, ++0x0A,0xD5,0x20,0x00,0xFF,0xF7,0x68,0xFF, ++0x06,0xE0,0x62,0x68,0xA1,0x68,0x30,0x20, ++0x90,0x47,0x20,0x6A,0x40,0x1C,0x20,0x62, ++0x38,0x00,0x7F,0x1E,0x00,0x28,0xF4,0xDC, ++0x07,0xE0,0x00,0x98,0x62,0x68,0xA1,0x68, ++0x40,0x5D,0x90,0x47,0x20,0x6A,0x40,0x1C, ++0x20,0x62,0x28,0x00,0x6D,0x1E,0x00,0x28, ++0xF3,0xDC,0x20,0x00,0xFF,0xF7,0x61,0xFF, ++0x21,0x68,0x02,0x20,0x09,0x06,0x00,0xD4, ++0x01,0x20,0x05,0xB0,0xF0,0xBD,0x00,0x00, ++0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0xF7,0xB5,0x00,0x25,0x75,0x29,0x10,0x68, ++0x00,0x99,0x14,0xA6,0x11,0xD0,0xFF,0xF7, ++0x5D,0xFF,0x00,0x28,0x02,0xDA,0x40,0x42, ++0x11,0xA6,0x08,0xE0,0x00,0x99,0x09,0x68, ++0x8A,0x07,0x01,0xD5,0x0F,0xA6,0x02,0xE0, ++0x49,0x07,0x04,0xD5,0x0E,0xA6,0x01,0x25, ++0x01,0xE0,0xFF,0xF7,0x56,0xFF,0x00,0x9F, ++0x00,0x24,0x24,0x37,0x04,0xE0,0x00,0xF0, ++0x84,0xEC,0x30,0x31,0x39,0x55,0x64,0x1C, ++0x00,0x28,0xF8,0xD1,0x00,0x98,0x2B,0x00, ++0x32,0x00,0x21,0x00,0xFF,0xF7,0x79,0xFF, ++0xFE,0xBD,0x00,0x00,0x00,0x00,0x00,0x00, ++0x2D,0x00,0x00,0x00,0x2B,0x00,0x00,0x00, ++0x20,0x00,0x00,0x00,0x01,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0x11,0x68,0x02,0x68, ++0x00,0x6A,0x53,0x05,0x01,0xD5,0x08,0x70, ++0x0A,0xE0,0xD3,0x05,0x01,0xD5,0x08,0x80, ++0x06,0xE0,0x13,0x06,0x02,0xD5,0xC2,0x17, ++0x05,0xC1,0x01,0xE0,0x52,0x06,0x08,0x60, ++0x01,0x20,0x70,0x47,0x01,0x69,0x4A,0x1C, ++0x02,0x61,0x08,0x78,0x70,0x47,0x10,0xB5, ++0x90,0xB0,0x0C,0x00,0x03,0x92,0x00,0x22, ++0x06,0x92,0x05,0x4A,0x05,0x90,0x19,0x00, ++0x7A,0x44,0x01,0xA8,0x02,0x94,0x04,0x92, ++0xFF,0xF7,0x2E,0xFB,0x10,0xB0,0x10,0xBD, ++0xE1,0xFF,0xFF,0xFF,0x0A,0x68,0x10,0x70, ++0x52,0x1C,0x0A,0x60,0x70,0x47,0x4B,0x68, ++0x0A,0x68,0x9A,0x42,0x02,0xD2,0x53,0x1C, ++0x0B,0x60,0x10,0x70,0x70,0x47,0x00,0x00, ++0xF7,0xB5,0x04,0x00,0x15,0x00,0x2C,0x48, ++0x86,0xB0,0x78,0x44,0x00,0x27,0x03,0xC8, ++0x3E,0x00,0x03,0x90,0x04,0x91,0x11,0xE0, ++0x07,0x98,0x71,0x00,0x03,0xAA,0x41,0x5A, ++0x01,0xA8,0x00,0xF0,0xFB,0xFB,0x41,0x1C, ++0x07,0xD0,0x21,0x68,0x89,0x06,0x03,0xD5, ++0xE2,0x69,0x39,0x18,0x91,0x42,0x0E,0xD8, ++0x3F,0x18,0x76,0x1C,0x20,0x68,0x80,0x06, ++0x02,0xD5,0xE0,0x69,0xB8,0x42,0x06,0xDD, ++0xAE,0x42,0xE5,0xDB,0x07,0x98,0x71,0x00, ++0x40,0x5A,0x00,0x28,0xE0,0xD1,0xA0,0x69, ++0xC0,0x1B,0xA0,0x61,0x20,0x00,0xFF,0xF7, ++0x9B,0xFE,0x15,0x48,0x78,0x44,0x5A,0x38, ++0x03,0xC8,0x03,0x90,0x00,0x20,0x04,0x91, ++0x16,0xE0,0x41,0x00,0x07,0x98,0x03,0xAA, ++0x41,0x5A,0x01,0xA8,0x00,0xF0,0xCE,0xFB, ++0x00,0x90,0x40,0x1C,0x0A,0xD0,0x00,0x25, ++0x05,0xE0,0x62,0x68,0x01,0xA8,0xA1,0x68, ++0x40,0x5D,0x90,0x47,0x6D,0x1C,0x00,0x98, ++0x85,0x42,0xF6,0xD3,0x05,0x98,0x40,0x1C, ++0xB0,0x42,0x05,0x90,0xE5,0xDB,0x20,0x6A, ++0xC0,0x19,0x20,0x62,0x20,0x00,0xFF,0xF7, ++0x88,0xFE,0x09,0xB0,0xF0,0xBD,0x00,0x00, ++0x6A,0x16,0x00,0x00,0x01,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0xF7,0xB5,0xD2,0x1D, ++0x82,0xB0,0xD0,0x08,0x00,0x25,0xC0,0x00, ++0xF5,0x29,0xC0,0xC8,0x1A,0xA0,0x01,0x90, ++0x14,0xD0,0x00,0x23,0x39,0x00,0xF0,0x1A, ++0x99,0x41,0x04,0xDA,0x76,0x42,0x92,0x41, ++0xD7,0x1B,0x16,0xA0,0x08,0xE0,0x02,0x98, ++0x00,0x68,0x81,0x07,0x01,0xD5,0x14,0xA0, ++0x02,0xE0,0x40,0x07,0x02,0xD5,0x13,0xA0, ++0x01,0x25,0x01,0x90,0x02,0x98,0x00,0x24, ++0x24,0x30,0x00,0x90,0x09,0xE0,0x39,0x00, ++0x30,0x00,0x00,0xF0,0xCA,0xE8,0x00,0x9B, ++0x30,0x32,0x06,0x00,0x1A,0x55,0x64,0x1C, ++0x0F,0x00,0x00,0x23,0x39,0x00,0x30,0x00, ++0x59,0x40,0x58,0x40,0x08,0x43,0xEE,0xD1, ++0x01,0x9A,0x02,0x98,0x2B,0x00,0x21,0x00, ++0xFF,0xF7,0x93,0xFE,0x05,0xB0,0xF0,0xBD, ++0x00,0x00,0x00,0x00,0x2D,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00,0x20,0x00,0x00,0x00, ++0x57,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0xF8,0xB5,0x07,0x00,0x15,0x00,0x1E,0x00, ++0x00,0x24,0x24,0x30,0x00,0x90,0x09,0xE0, ++0x00,0x99,0x68,0x07,0xED,0x08,0x40,0x0F, ++0x30,0x30,0x08,0x55,0x70,0x07,0x64,0x1C, ++0x05,0x43,0xF6,0x08,0x00,0x23,0x31,0x00, ++0x28,0x00,0x59,0x40,0x58,0x40,0x08,0x43, ++0xEE,0xD1,0x38,0x68,0x10,0xA2,0x01,0x07, ++0x08,0xD5,0x20,0x21,0x08,0x40,0x20,0x43, ++0x04,0xD0,0xF8,0x69,0x01,0x23,0x0D,0xA2, ++0x40,0x1E,0xF8,0x61,0x21,0x00,0x38,0x00, ++0xFF,0xF7,0x5B,0xFE,0xF8,0xBD,0x10,0xB5, ++0x04,0x00,0x10,0x68,0x21,0x00,0xFF,0xF7, ++0x20,0xFE,0x02,0x00,0x00,0x23,0x20,0x00, ++0xFF,0xF7,0xCA,0xFF,0x10,0xBD,0xD2,0x1D, ++0xD1,0x08,0xC9,0x00,0x0C,0xC9,0xC3,0xE7, ++0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00, ++0xF7,0xB5,0x82,0xB0,0x00,0x27,0x02,0x9C, ++0x15,0x00,0x20,0x78,0x64,0x1C,0x01,0x97, ++0x30,0x28,0x13,0xD1,0x20,0x78,0x01,0x27, ++0x64,0x1C,0x78,0x28,0x01,0xD0,0x58,0x28, ++0x08,0xD1,0x00,0x2D,0x01,0xD0,0x10,0x2D, ++0x0B,0xD1,0x20,0x78,0x00,0x27,0x10,0x25, ++0x64,0x1C,0x06,0xE0,0x00,0x2D,0x04,0xD1, ++0x08,0x25,0x02,0xE0,0x00,0x2D,0x00,0xD1, ++0x0A,0x25,0x00,0x26,0x00,0x96,0x11,0xE0, ++0x00,0x99,0x01,0x27,0x69,0x43,0x08,0x18, ++0x29,0x00,0x02,0x0C,0x71,0x43,0x00,0x04, ++0x00,0x0C,0x00,0x90,0x8E,0x18,0x38,0x04, ++0x86,0x42,0x01,0xD3,0x01,0x20,0x01,0x90, ++0x20,0x78,0x64,0x1C,0x29,0x00,0x00,0xF0, ++0xD8,0xFA,0x00,0x28,0xE8,0xDA,0x03,0x98, ++0x00,0x28,0x04,0xD0,0x64,0x1E,0x00,0x2F, ++0x00,0xD1,0x02,0x9C,0x04,0x60,0x01,0x98, ++0x00,0x28,0x06,0xD0,0xFF,0xF7,0x90,0xED, ++0x02,0x21,0x01,0x60,0xC8,0x1E,0x05,0xB0, ++0xF0,0xBD,0x00,0x99,0x30,0x04,0x08,0x43, ++0xF9,0xE7,0x00,0x00,0x00,0x00,0x9F,0xE5, ++0x1E,0xFF,0x2F,0xE1,0x8C,0x17,0x03,0x20, ++0x07,0x40,0x2D,0xE9,0x02,0x00,0xB0,0xE3, ++0xEA,0x01,0x00,0xFA,0x07,0x80,0xBD,0xE8, ++0x04,0x00,0x9F,0xE5,0x1E,0xFF,0x2F,0xE1, ++0x1E,0xFF,0x2F,0xE1,0xAC,0x17,0x03,0x20, ++0x30,0x40,0x2D,0xE9,0x0A,0x20,0x50,0xE2, ++0x20,0xE1,0xA0,0xE1,0x00,0x30,0xD1,0xE2, ++0x01,0xEF,0x8E,0xE1,0x0E,0x00,0x50,0xE0, ++0x21,0x11,0xC1,0xE0,0x20,0xE2,0xA0,0xE1, ++0x01,0xEE,0x8E,0xE1,0x0E,0x00,0x90,0xE0, ++0x21,0x12,0xA1,0xE0,0x20,0xE4,0xA0,0xE1, ++0x01,0xEC,0x8E,0xE1,0x0E,0x00,0x90,0xE0, ++0x21,0x14,0xA1,0xE0,0x20,0xE8,0xA0,0xE1, ++0x01,0xE8,0x8E,0xE1,0x0E,0x00,0x90,0xE0, ++0x21,0x18,0xA1,0xE0,0x01,0x00,0x90,0xE0, ++0x00,0x10,0xA1,0xE2,0xA0,0x01,0xA0,0xE1, ++0x81,0x0E,0x80,0xE1,0xA1,0x11,0xA0,0xE1, ++0x00,0x51,0x90,0xE0,0x01,0x41,0xA0,0xE1, ++0x20,0x4F,0x84,0xE1,0x01,0x40,0xA4,0xE0, ++0x05,0x50,0x95,0xE0,0x04,0x40,0xA4,0xE0, ++0x05,0x20,0x52,0xE0,0x04,0x30,0xD3,0xE0, ++0x00,0x30,0xA0,0xE3,0x0A,0x20,0x82,0x42, ++0x30,0x80,0xBD,0x48,0x01,0x00,0x90,0xE2, ++0x00,0x10,0xA1,0xE2,0x30,0x80,0xBD,0xE8, ++0x70,0x47,0xFF,0xB5,0x0C,0x00,0x8F,0xB0, ++0x50,0x68,0x11,0x68,0x09,0x90,0x46,0x00, ++0x08,0x91,0x75,0x0D,0x00,0xD1,0x6D,0x1E, ++0x00,0x21,0x08,0x00,0x01,0xF0,0xB4,0xE8, ++0x03,0x21,0x09,0x9A,0x89,0x05,0x08,0x40, ++0x00,0x2A,0x03,0xDA,0x82,0x00,0x80,0x18, ++0x40,0x08,0x08,0x40,0x80,0x0D,0x01,0x28, ++0x0A,0x90,0x02,0xDD,0x00,0x20,0xC0,0x43, ++0x0A,0x90,0x08,0x98,0x06,0x43,0x19,0xD1, ++0x18,0x98,0x01,0x28,0x03,0xD1,0x12,0x99, ++0x00,0x20,0xCA,0x43,0x09,0xE0,0x00,0x20, ++0x30,0x21,0x01,0xE0,0x21,0x54,0x40,0x1C, ++0x12,0x9A,0x90,0x42,0xFA,0xDB,0x10,0x00, ++0x00,0x22,0x18,0x9B,0x00,0x21,0x21,0x54, ++0x0F,0x99,0x8B,0x60,0x0A,0x60,0x48,0x60, ++0x13,0xB0,0xF0,0xBD,0xF0,0x48,0xF1,0x49, ++0x28,0x18,0x48,0x43,0x00,0x14,0x0C,0x90, ++0x0A,0x98,0x40,0x42,0x0D,0x90,0x18,0x98, ++0x00,0x28,0x04,0xD1,0x12,0x99,0x0C,0x98, ++0x45,0x1A,0x6D,0x1C,0x01,0xE0,0x12,0x98, ++0x45,0x42,0x0D,0x9A,0x00,0x2D,0x00,0xDC, ++0x0A,0x9A,0x29,0x1E,0x00,0xDA,0x69,0x42, ++0x03,0xA8,0x00,0xF0,0xBD,0xFA,0x08,0x99, ++0x09,0x98,0x00,0xF0,0x44,0xEB,0x01,0x91, ++0x01,0x00,0xE1,0x48,0x02,0x92,0x09,0x18, ++0x00,0x2D,0x00,0x91,0x0A,0xDD,0xDE,0x49, ++0x03,0x98,0x0A,0x9A,0x49,0x42,0x40,0x18, ++0x03,0xA9,0x03,0x90,0x68,0x46,0x00,0xF0, ++0xBE,0xED,0x07,0xE0,0x03,0x99,0x0A,0x9A, ++0x08,0x18,0x03,0xA9,0x03,0x90,0x68,0x46, ++0x00,0xF0,0xCC,0xED,0x00,0x90,0x00,0x04, ++0x02,0x92,0x01,0x91,0x03,0xD0,0x00,0x25, ++0xED,0x43,0x6E,0x08,0x01,0xE0,0x0E,0x00, ++0x15,0x00,0x18,0x98,0x00,0x28,0x26,0xD1, ++0x12,0x9F,0x07,0xE0,0x31,0x00,0x28,0x00, ++0xFF,0xF7,0x26,0xEF,0x30,0x32,0x05,0x00, ++0x0E,0x00,0xE2,0x55,0x7F,0x1E,0xF5,0xD5, ++0x12,0x98,0x00,0x23,0x31,0x00,0x07,0x90, ++0x28,0x00,0x01,0x27,0x59,0x40,0x58,0x40, ++0x08,0x43,0x03,0xD0,0x0C,0x98,0x00,0x27, ++0x40,0x1C,0x07,0xE0,0x20,0x78,0x30,0x28, ++0x01,0xD0,0x0C,0x98,0x03,0xE0,0x0C,0x98, ++0x00,0x27,0x40,0x1E,0x0C,0x90,0x00,0x2F, ++0x06,0x90,0x98,0xD0,0x35,0xE0,0x00,0x20, ++0x07,0x00,0x0B,0x90,0x0A,0xE0,0x11,0x2F, ++0x0F,0xDA,0x31,0x00,0x28,0x00,0xFF,0xF7, ++0xFC,0xEE,0x30,0x32,0x05,0x00,0x0E,0x00, ++0xE2,0x55,0x7F,0x1C,0x00,0x23,0x31,0x00, ++0x28,0x00,0x59,0x40,0x58,0x40,0x08,0x43, ++0xED,0xD1,0x00,0x23,0x31,0x00,0x28,0x00, ++0x59,0x40,0x58,0x40,0x08,0x43,0x10,0xD1, ++0x00,0x21,0x38,0x00,0x04,0xE0,0x23,0x5C, ++0x62,0x5C,0x63,0x54,0x49,0x1C,0x22,0x54, ++0x40,0x1E,0x81,0x42,0xF7,0xDB,0x12,0x98, ++0x07,0x97,0x38,0x1A,0x40,0x1E,0x06,0x90, ++0x07,0xE0,0x0B,0x98,0x00,0x28,0x04,0xD1, ++0x11,0x20,0x12,0x90,0x00,0x20,0x18,0x90, ++0x61,0xE7,0x07,0x9A,0x18,0x99,0x00,0x20, ++0xA0,0x54,0x0F,0x98,0x81,0x60,0x07,0x99, ++0x41,0x60,0x06,0x99,0x01,0x60,0x4B,0xE7, ++0xF0,0xB5,0xD2,0x1D,0x04,0x00,0xD0,0x08, ++0x0D,0x00,0xC0,0x00,0x95,0xB0,0x01,0x68, ++0x40,0x68,0x02,0x91,0x01,0x00,0x03,0x90, ++0x02,0x98,0x00,0xF0,0x64,0xEF,0x02,0x00, ++0x03,0x98,0xC1,0x0F,0x2D,0x20,0x00,0x29, ++0x06,0xD1,0x21,0x68,0x2B,0x20,0x8B,0x07, ++0x02,0xD4,0x48,0x07,0xC0,0x0F,0x40,0x01, ++0x03,0x2A,0x07,0x90,0x01,0xD0,0x07,0x2A, ++0x05,0xDB,0x03,0x00,0x29,0x00,0x20,0x00, ++0x00,0xF0,0xC0,0xF9,0x05,0xE1,0x20,0x68, ++0x80,0x06,0x01,0xD5,0xE7,0x69,0x00,0xE0, ++0x06,0x27,0x28,0x00,0x11,0x23,0x65,0x2D, ++0x1B,0xD0,0x66,0x28,0x26,0xD0,0x67,0x28, ++0x61,0xD1,0x01,0x2F,0x00,0xDA,0x01,0x27, ++0x00,0x22,0x11,0x2F,0x00,0x92,0x00,0xDC, ++0x3B,0x00,0x02,0xAA,0x0A,0xA9,0x12,0xA8, ++0xFF,0xF7,0xCF,0xFE,0x20,0x68,0x00,0x26, ++0x3D,0x00,0x00,0x07,0x35,0xD4,0x13,0x98, ++0xA8,0x42,0x00,0xDA,0x05,0x00,0x0A,0xA8, ++0x28,0xE0,0x00,0x22,0x11,0x2F,0x00,0x92, ++0x00,0xDA,0x7B,0x1C,0x02,0xAA,0x0A,0xA9, ++0x12,0xA8,0xFF,0xF7,0xBA,0xFE,0x00,0x26, ++0x7D,0x1C,0x27,0xE0,0x01,0x20,0x01,0x22, ++0xC0,0x07,0x00,0x92,0x04,0x90,0x3B,0x00, ++0x02,0xAA,0x0A,0xA9,0x12,0xA8,0xFF,0xF7, ++0xAC,0xFE,0x14,0x98,0x13,0x9D,0x00,0x26, ++0x00,0x28,0x02,0xD1,0x12,0x99,0x78,0x1C, ++0x0D,0x18,0x78,0x1B,0x02,0xD4,0x46,0x42, ++0x76,0x1E,0x7D,0x1C,0xE8,0x1B,0x05,0x90, ++0x21,0xE0,0x6D,0x1E,0x01,0x2D,0x04,0xDD, ++0x41,0x19,0x20,0x39,0xC9,0x7F,0x30,0x29, ++0xF7,0xD0,0x12,0x98,0xB8,0x42,0x01,0xDA, ++0x01,0x1D,0x03,0xDA,0x01,0x20,0x05,0x90, ++0x12,0x98,0x0F,0xE0,0x00,0x28,0x02,0xDC, ++0x86,0x19,0x2D,0x1A,0x04,0xE0,0x40,0x1C, ++0xA8,0x42,0x01,0xDD,0x12,0x9D,0x6D,0x1C, ++0x12,0x98,0x80,0x1B,0x40,0x1C,0x05,0x90, ++0x01,0x20,0xC0,0x07,0x04,0x90,0x20,0x68, ++0x00,0x07,0x05,0xD4,0x05,0x98,0xA8,0x42, ++0x02,0xDB,0x00,0x20,0xC0,0x43,0x05,0x90, ++0x08,0xAB,0x00,0x20,0xD8,0x71,0x04,0x98, ++0x01,0x21,0x09,0xAF,0x03,0x37,0xC9,0x07, ++0x88,0x42,0x24,0xD0,0x02,0x20,0x01,0x90, ++0x2B,0x20,0x00,0x90,0x04,0x98,0x00,0x28, ++0x0B,0xDA,0x40,0x42,0x04,0x90,0x2D,0x20, ++0x00,0x90,0x06,0xE0,0x04,0x98,0x00,0xF0, ++0xE8,0xE8,0x30,0x31,0x7F,0x1E,0x04,0x90, ++0x39,0x70,0x01,0x98,0x41,0x1E,0x00,0x28, ++0x01,0x91,0xF3,0xDC,0x04,0x98,0x00,0x28, ++0xF0,0xD1,0x00,0x98,0x7F,0x1E,0x38,0x70, ++0x21,0x68,0x45,0x20,0x09,0x05,0x00,0xD4, ++0x65,0x20,0x7F,0x1E,0x38,0x70,0x08,0xA8, ++0xC0,0x1B,0xC0,0x1D,0x06,0x90,0x07,0x98, ++0x00,0x28,0x00,0xD0,0x01,0x20,0x41,0x19, ++0x05,0x98,0xC0,0x17,0x09,0x18,0x06,0x98, ++0x08,0x18,0xA1,0x69,0x08,0x1A,0x40,0x1E, ++0xA0,0x61,0x20,0x68,0xC0,0x06,0x02,0xD4, ++0x20,0x00,0xFF,0xF7,0x55,0xFB,0x07,0x98, ++0x00,0x28,0x05,0xD0,0x62,0x68,0xA1,0x68, ++0x90,0x47,0x20,0x6A,0x40,0x1C,0x20,0x62, ++0x20,0x68,0xC0,0x06,0x24,0xD5,0x20,0x00, ++0xFF,0xF7,0x46,0xFB,0x20,0xE0,0x00,0x2E, ++0x07,0xDB,0x13,0x98,0xB0,0x42,0x04,0xDD, ++0x0A,0xA8,0x62,0x68,0x80,0x5D,0xA1,0x68, ++0x02,0xE0,0x62,0x68,0xA1,0x68,0x30,0x20, ++0x90,0x47,0x20,0x6A,0x76,0x1C,0x40,0x1C, ++0x20,0x62,0x05,0x98,0x40,0x1E,0x05,0x90, ++0x0A,0xD1,0xFF,0xF7,0xAE,0xED,0xC0,0x68, ++0x62,0x68,0x01,0x68,0x40,0x5C,0xA1,0x68, ++0x90,0x47,0x20,0x6A,0x40,0x1C,0x20,0x62, ++0x28,0x00,0x6D,0x1E,0x00,0x28,0xDA,0xDC, ++0x07,0xE0,0x62,0x68,0x38,0x78,0xA1,0x68, ++0x7F,0x1C,0x90,0x47,0x20,0x6A,0x40,0x1C, ++0x20,0x62,0x06,0x98,0x41,0x1E,0x00,0x28, ++0x06,0x91,0xF2,0xDC,0x20,0x00,0xFF,0xF7, ++0x24,0xFB,0x15,0xB0,0x02,0x20,0xF0,0xBD, ++0x01,0xFC,0xFF,0xFF,0x10,0x4D,0x00,0x00, ++0xE1,0xDF,0xFF,0xFF,0x17,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0x10,0xB5,0x43,0x69, ++0x00,0x2B,0x02,0xD0,0xAF,0xF3,0x00,0x80, ++0x01,0xE0,0xFF,0xF7,0x35,0xFB,0x01,0x20, ++0x10,0xBD,0x12,0x68,0x01,0x00,0x24,0x31, ++0x0A,0x70,0x00,0x22,0x4A,0x70,0x01,0x22, ++0xEC,0xE7,0x11,0x68,0x00,0x22,0xD2,0x43, ++0xE8,0xE7,0x00,0x00,0x17,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0x10,0xB5,0x43,0x69, ++0x00,0x2B,0x02,0xD0,0xAF,0xF3,0x00,0x80, ++0x01,0xE0,0xFF,0xF7,0x11,0xFC,0x01,0x20, ++0x10,0xBD,0x12,0x68,0x01,0x00,0x24,0x31, ++0x82,0x84,0x00,0x22,0xC2,0x84,0x01,0x22, ++0xEC,0xE7,0x11,0x68,0x00,0x22,0xD2,0x43, ++0xE8,0xE7,0x3A,0x28,0x00,0xD2,0x30,0x38, ++0x20,0x23,0x02,0x00,0x9A,0x43,0x41,0x2A, ++0x01,0xD3,0x10,0x00,0x37,0x38,0x00,0x22, ++0xD2,0x43,0x88,0x42,0x00,0xD2,0x02,0x00, ++0x10,0x00,0x70,0x47,0x70,0xB5,0x05,0x00, ++0x0C,0x00,0x16,0x00,0xFF,0xF7,0xA2,0xEA, ++0x00,0x68,0xFF,0x21,0x02,0x31,0x09,0x5C, ++0x01,0x29,0x0A,0xD1,0xFF,0x21,0x08,0x31, ++0x32,0x00,0x09,0x58,0x43,0x18,0xFF,0x33, ++0x08,0x33,0x21,0x00,0x28,0x00,0x98,0x47, ++0x70,0xBD,0xFF,0x2C,0x05,0xD8,0x00,0x5D, ++0x00,0x28,0x02,0xD0,0x01,0x20,0x2C,0x70, ++0x70,0xBD,0x00,0x20,0xC0,0x43,0x70,0xBD, ++0x0A,0x10,0x40,0xE2,0x20,0x01,0x40,0xE0, ++0x20,0x02,0x80,0xE0,0x20,0x04,0x80,0xE0, ++0x20,0x08,0x80,0xE0,0xA0,0x01,0xA0,0xE1, ++0x00,0x21,0x80,0xE0,0x82,0x10,0x51,0xE0, ++0x01,0x00,0x80,0x52,0x0A,0x10,0x81,0x42, ++0x1E,0xFF,0x2F,0xE1,0x0E,0x50,0xA0,0xE1, ++0x79,0xFE,0xFF,0xEB,0x05,0xE0,0xA0,0xE1, ++0x00,0x50,0xB0,0xE1,0x0D,0x10,0xA0,0xE1, ++0x0A,0x30,0xA0,0xE1,0x07,0x00,0xC0,0xE3, ++0x00,0xD0,0xA0,0xE1,0x60,0xD0,0x8D,0xE2, ++0x20,0x40,0x2D,0xE9,0x65,0x00,0x00,0xFA, ++0x20,0x40,0xBD,0xE8,0x00,0x60,0xA0,0xE3, ++0x00,0x70,0xA0,0xE3,0x00,0x80,0xA0,0xE3, ++0x00,0xB0,0xA0,0xE3,0x07,0x10,0xC1,0xE3, ++0x05,0xC0,0xA0,0xE1,0xC0,0x09,0xAC,0xE8, ++0xC0,0x09,0xAC,0xE8,0xC0,0x09,0xAC,0xE8, ++0xC0,0x09,0xAC,0xE8,0x01,0xD0,0xA0,0xE1, ++0x1E,0xFF,0x2F,0xE1,0xF8,0xB5,0x04,0x00, ++0x01,0x68,0x01,0x20,0x1F,0x00,0xC0,0x02, ++0x03,0x26,0x08,0x40,0x07,0x2A,0x04,0xDB, ++0x00,0x28,0x17,0xA5,0x05,0xD1,0x17,0xA5, ++0x03,0xE0,0x00,0x28,0x16,0xA5,0x00,0xD1, ++0x16,0xA5,0x10,0x20,0x81,0x43,0x21,0x60, ++0xA0,0x69,0xC0,0x1E,0x00,0x2F,0xA0,0x61, ++0x01,0xD0,0x40,0x1E,0xA0,0x61,0x20,0x00, ++0xFF,0xF7,0x36,0xFA,0x00,0x2F,0x01,0xD1, ++0x20,0x6A,0x06,0xE0,0x62,0x68,0xA1,0x68, ++0x38,0x00,0x90,0x47,0x20,0x6A,0x40,0x1C, ++0x20,0x62,0xC0,0x1C,0x20,0x62,0x04,0xE0, ++0x62,0x68,0x28,0x78,0xA1,0x68,0x6D,0x1C, ++0x90,0x47,0x76,0x1E,0xF8,0xD2,0x20,0x00, ++0xFF,0xF7,0x33,0xFA,0xF8,0xBD,0x00,0x00, ++0x4E,0x41,0x4E,0x00,0x6E,0x61,0x6E,0x00, ++0x49,0x4E,0x46,0x00,0x69,0x6E,0x66,0x00, ++0xF7,0xB5,0x08,0x00,0x17,0x00,0x2E,0x49, ++0x8A,0xB0,0x79,0x44,0x06,0xAC,0x2C,0xC9, ++0x2C,0xC4,0x2C,0xC9,0x37,0x21,0x03,0xAC, ++0xC9,0x01,0x40,0x18,0x2C,0xC4,0x37,0x21, ++0x1B,0x30,0xFF,0xF7,0x2E,0xE9,0x05,0x00, ++0x80,0x3D,0x0C,0x00,0x1B,0x3C,0x02,0xD5, ++0x64,0x42,0x01,0x20,0x00,0xE0,0x00,0x20, ++0x00,0x26,0x09,0x90,0x0F,0xE0,0xE0,0x07, ++0x0B,0xD0,0x0C,0x20,0x1E,0x49,0x70,0x43, ++0x79,0x44,0xBA,0x39,0x41,0x18,0x3A,0x00, ++0x06,0xA8,0x00,0xF0,0x04,0xEB,0x06,0xAB, ++0x07,0xC3,0x64,0x10,0x76,0x1C,0x00,0x2C, ++0xED,0xD1,0x6E,0x46,0x18,0xE0,0xE8,0x07, ++0x14,0xD0,0x15,0x48,0x21,0x01,0x78,0x44, ++0xA4,0x38,0x08,0x18,0x0E,0xC8,0x0E,0xC6, ++0x00,0x68,0x0C,0x3E,0xF8,0x42,0x02,0xD1, ++0x02,0x98,0xC0,0x19,0x02,0x90,0x69,0x46, ++0x3A,0x00,0x03,0xA8,0x00,0xF0,0xE6,0xEA, ++0x03,0xAB,0x07,0xC3,0x6D,0x10,0x64,0x1C, ++0x00,0x2D,0xE4,0xD1,0x09,0x98,0x00,0x28, ++0x05,0xD0,0x3A,0x00,0x06,0xA9,0x03,0xA8, ++0x00,0xF0,0xC0,0xEA,0x04,0xE0,0x3A,0x00, ++0x06,0xA9,0x03,0xA8,0x00,0xF0,0xD2,0xEA, ++0x0A,0x9B,0x07,0xC3,0x0D,0xB0,0xF0,0xBD, ++0x7E,0x0D,0x00,0x00,0x04,0x00,0xAF,0xF3, ++0x00,0x80,0x20,0x00,0xF3,0xF7,0x40,0xEC, ++0x01,0x00,0x10,0xB5,0x02,0x20,0x00,0xF0, ++0xB4,0xEC,0x10,0xBD,0x00,0xF0,0xCE,0xBC, ++0x01,0x48,0x02,0x4B,0x02,0x46,0x70,0x47, ++0x94,0xD4,0x02,0x20,0x94,0xE4,0x02,0x20, ++0x70,0x47,0x70,0x47,0x70,0x47,0x00,0x00, ++0x00,0x20,0xB0,0xE3,0x20,0x32,0x71,0xE0, ++0x75,0xFC,0xFF,0x3A,0x20,0x34,0x71,0xE0, ++0x67,0xFC,0xFF,0x3A,0x00,0xC0,0xA0,0xE3, ++0x86,0xFC,0xFF,0xEA,0x80,0xC0,0xB0,0xE1, ++0x00,0x00,0x31,0x03,0x2C,0x0A,0xA0,0xE1, ++0x0C,0x35,0xA0,0xE1,0x81,0x25,0xA0,0xE1, ++0x1E,0x0B,0x80,0x12,0xA1,0x1A,0x83,0xE1, ++0x60,0x00,0xA0,0xE1,0x02,0x11,0x81,0x13, ++0xCC,0xCA,0xB0,0xE1,0x17,0x00,0x00,0x0A, ++0x01,0x00,0x7C,0xE3,0x01,0x01,0x80,0x03, ++0x1E,0xFF,0x2F,0xE1,0x22,0x38,0xB0,0xE1, ++0x02,0x28,0xA0,0x01,0x10,0xC0,0xA0,0x03, ++0x00,0xC0,0xA0,0x13,0x1F,0x00,0x40,0xE2, ++0x22,0x3C,0xB0,0xE1,0x02,0x24,0xA0,0x01, ++0x08,0xC0,0x8C,0x02,0x22,0x3E,0xB0,0xE1, ++0x02,0x22,0xA0,0x01,0x04,0xC0,0x8C,0x02, ++0x22,0x3F,0xB0,0xE1,0x02,0x21,0xA0,0x01, ++0x02,0xC0,0x8C,0x02,0xA2,0x3F,0xB0,0xE1, ++0x82,0x20,0xA0,0x01,0x01,0xC0,0x8C,0x02, ++0x02,0x10,0xA0,0xE1,0x00,0x20,0xA0,0xE3, ++0x0C,0x00,0x40,0xE0,0x1E,0xFF,0x2F,0xE1, ++0x02,0x01,0x11,0xE3,0x1E,0xFF,0x2F,0x01, ++0x02,0x11,0xD1,0xE3,0xE6,0xFF,0xFF,0x0A, ++0x21,0x38,0xB0,0xE1,0x01,0x18,0xA0,0x01, ++0x10,0xC0,0xA0,0x03,0x00,0xC0,0xA0,0x13, ++0x21,0x3C,0xB0,0xE1,0x01,0x14,0xA0,0x01, ++0x08,0xC0,0x8C,0x02,0x21,0x3E,0xB0,0xE1, ++0x01,0x12,0xA0,0x01,0x04,0xC0,0x8C,0x02, ++0x21,0x3F,0xB0,0xE1,0x01,0x11,0xA0,0x01, ++0x02,0xC0,0x8C,0x02,0xA1,0x3F,0xB0,0xE1, ++0x01,0xC0,0x8C,0x02,0x20,0x30,0x6C,0xE2, ++0x81,0x10,0xA0,0x01,0x32,0x13,0x81,0xE1, ++0x12,0x2C,0xA0,0xE1,0x0C,0x00,0x40,0xE0, ++0x01,0x00,0x80,0xE2,0x1E,0xFF,0x2F,0xE1, ++0xFF,0xC4,0xC0,0xE3,0x03,0x00,0x20,0xE0, ++0xFF,0x74,0xC3,0xE3,0x07,0x30,0x4C,0xE0, ++0x3F,0x3C,0x83,0xE2,0x02,0x01,0x00,0xE2, ++0xFF,0x30,0x83,0xE2,0x80,0x49,0x2D,0xE9, ++0x22,0x6E,0x8F,0xE2,0x09,0x00,0x2D,0xE9, ++0x24,0x38,0xA0,0xE1,0x25,0xB8,0xA0,0xE1, ++0x23,0x64,0xD6,0xE7,0x0B,0xE8,0xC5,0xE1, ++0x03,0x88,0xC4,0xE1,0xA1,0x10,0xB0,0xE1, ++0x93,0x66,0x27,0xE0,0x62,0x20,0xB0,0xE1, ++0x02,0x01,0xA0,0x23,0x00,0x00,0xA0,0x33, ++0x02,0x75,0x67,0xE2,0x97,0x06,0x06,0xE0, ++0xA4,0x76,0xA0,0xE1,0xA6,0x69,0xA0,0xE1, ++0x02,0x60,0x86,0xE2,0x97,0x66,0x2C,0xE0, ++0x02,0xC2,0x6C,0xE2,0x2C,0x78,0xA0,0xE1, ++0x07,0xC8,0xCC,0xE1,0x97,0x06,0x04,0xE0, ++0x9C,0x06,0x05,0xE0,0xA1,0x77,0xA0,0xE1, ++0x25,0x68,0x84,0xE0,0x26,0x63,0xA0,0xE1, ++0x96,0x07,0x0C,0xE0,0x2C,0xC8,0xA0,0xE1, ++0x9C,0x0B,0x07,0xE0,0x0C,0x48,0xA0,0xE1, ++0x07,0x20,0x52,0xE0,0x93,0x0C,0x07,0xE0, ++0x07,0x10,0xC1,0xE0,0x9C,0x0E,0x07,0xE0, ++0x07,0x08,0x50,0xE0,0x27,0x28,0xD2,0xE0, ++0x9C,0x08,0x07,0xE0,0x07,0x28,0x42,0x30, ++0x07,0x28,0x52,0x20,0x27,0x18,0xC1,0xE0, ++0x21,0x71,0xA0,0xE1,0x96,0x07,0x0C,0xE0, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x87,0x09,0x50,0xE0,0xA7,0x26,0xD2,0xE0, ++0x93,0x0C,0x07,0xE0,0x87,0x29,0x42,0x30, ++0x87,0x29,0x52,0x20,0xA7,0x16,0xC1,0xE0, ++0x9C,0x0E,0x07,0xE0,0x8C,0x41,0x84,0xE0, ++0x87,0x01,0x50,0xE0,0xA7,0x2E,0xD2,0xE0, ++0x9C,0x08,0x07,0xE0,0x87,0x21,0x42,0x30, ++0x87,0x21,0x52,0x20,0xA7,0x1E,0xC1,0xE0, ++0x0C,0x70,0x9D,0xE5,0x01,0x1D,0xA0,0xE1, ++0x22,0x13,0x81,0xE1,0x02,0x2D,0xA0,0xE1, ++0xA1,0x77,0xA0,0xE1,0x20,0x23,0x82,0xE1, ++0x96,0x07,0x0C,0xE0,0x00,0x0D,0xA0,0xE1, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x0C,0x5B,0xA0,0xE1,0x2C,0x45,0x84,0xE0, ++0x07,0x20,0x52,0xE0,0x93,0x0C,0x07,0xE0, ++0x07,0x10,0xC1,0xE0,0x9C,0x0E,0x07,0xE0, ++0x07,0x08,0x50,0xE0,0x27,0x28,0xD2,0xE0, ++0x9C,0x08,0x07,0xE0,0x07,0x28,0x42,0x30, ++0x07,0x28,0x52,0x20,0x27,0x18,0xC1,0xE0, ++0x21,0x71,0xA0,0xE1,0x96,0x07,0x0C,0xE0, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x87,0x09,0x50,0xE0,0xA7,0x26,0xD2,0xE0, ++0x93,0x0C,0x07,0xE0,0x87,0x29,0x42,0x30, ++0x87,0x29,0x52,0x20,0xA7,0x16,0xC1,0xE0, ++0x9C,0x0E,0x07,0xE0,0x87,0x01,0x50,0xE0, ++0xA7,0x2E,0xD2,0xE0,0x9C,0x08,0x07,0xE0, ++0x87,0x21,0x42,0x30,0x87,0x21,0x52,0x20, ++0xA7,0x1E,0xC1,0xE0,0x01,0x1D,0xA0,0xE1, ++0x22,0x13,0x81,0xE1,0x8C,0x54,0x95,0xE0, ++0xA1,0x77,0xA0,0xE1,0x02,0x2D,0xA0,0xE1, ++0x96,0x07,0x0C,0xE0,0x20,0x23,0x82,0xE1, ++0x00,0x40,0xA4,0xE2,0x00,0x0D,0xA0,0xE1, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x0C,0x6E,0xA0,0xE1,0x07,0x20,0x52,0xE0, ++0x93,0x0C,0x07,0xE0,0x07,0x10,0xC1,0xE0, ++0x9C,0x0E,0x07,0xE0,0x07,0x08,0x50,0xE0, ++0x27,0x28,0xD2,0xE0,0x9C,0x08,0x07,0xE0, ++0x07,0x28,0x42,0x30,0x07,0x28,0x52,0x20, ++0x27,0x18,0xC1,0xE0,0x2C,0x52,0x95,0xE0, ++0x01,0x17,0xA0,0xE1,0x22,0x19,0x81,0xE1, ++0x02,0x27,0xA0,0xE1,0x20,0x29,0x82,0xE1, ++0x00,0x07,0xA0,0xE1,0x00,0x40,0xA4,0xE2, ++0x03,0x38,0x88,0xE1,0x0B,0x88,0x8E,0xE1, ++0x00,0xE0,0xA0,0xE3,0x00,0xB0,0xA0,0xE3, ++0x08,0xC0,0x52,0xE0,0x03,0x70,0xD1,0xE0, ++0x0E,0xE0,0xAE,0xE0,0x0C,0x20,0xA0,0x21, ++0x07,0x10,0xA0,0x21,0x00,0x00,0x90,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xB1,0xE0, ++0x0B,0xB0,0xAB,0xE0,0x08,0xC0,0x52,0xE0, ++0x03,0x70,0xD1,0xE0,0x00,0xB0,0xDB,0xE2, ++0x00,0xB0,0xA0,0xE3,0x0E,0xE0,0xAE,0xE0, ++0x0C,0x20,0xA0,0x21,0x07,0x10,0xA0,0x21, ++0x00,0x00,0x90,0xE0,0x02,0x20,0xB2,0xE0, ++0x01,0x10,0xB1,0xE0,0x0B,0xB0,0xAB,0xE0, ++0x08,0xC0,0x52,0xE0,0x03,0x70,0xD1,0xE0, ++0x00,0xB0,0xDB,0xE2,0x0C,0x20,0xA0,0x21, ++0x07,0x10,0xA0,0x21,0x0E,0xE0,0xAE,0xE0, ++0x02,0x70,0x91,0xE1,0x01,0x60,0x86,0x13, ++0x0E,0x6E,0x96,0xE0,0x00,0x20,0xB5,0xE2, ++0x00,0x10,0xB4,0xE2,0x89,0x01,0xBD,0x48, ++0x00,0x88,0xBD,0x48,0x06,0x60,0x96,0xE0, ++0x89,0x01,0xBD,0xE8,0x02,0x20,0xB2,0xE0, ++0x00,0x48,0xBD,0xE8,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x80,0x80,0x7F,0x7E,0x7D,0x7C,0x7B,0x7A, ++0x79,0x78,0x77,0x76,0x76,0x75,0x74,0x73, ++0x72,0x71,0x71,0x70,0x6F,0x6E,0x6E,0x6D, ++0x6C,0x6C,0x6B,0x6A,0x6A,0x69,0x68,0x68, ++0x67,0x66,0x66,0x65,0x64,0x64,0x63,0x63, ++0x62,0x61,0x61,0x60,0x60,0x5F,0x5F,0x5E, ++0x5E,0x5D,0x5D,0x5C,0x5C,0x5B,0x5B,0x5A, ++0x5A,0x59,0x59,0x58,0x58,0x57,0x57,0x56, ++0x56,0x55,0x55,0x55,0x54,0x54,0x53,0x53, ++0x52,0x52,0x52,0x51,0x51,0x50,0x50,0x50, ++0x4F,0x4F,0x4F,0x4E,0x4E,0x4D,0x4D,0x4D, ++0x4C,0x4C,0x4C,0x4B,0x4B,0x4B,0x4A,0x4A, ++0x4A,0x49,0x49,0x49,0x48,0x48,0x48,0x47, ++0x47,0x47,0x47,0x46,0x46,0x46,0x45,0x45, ++0x45,0x44,0x44,0x44,0x44,0x43,0x43,0x43, ++0x43,0x42,0x42,0x42,0x42,0x41,0x41,0x41, ++0x00,0x00,0x53,0xE3,0x16,0x00,0x00,0x4A, ++0x86,0x70,0xB0,0xE1,0x11,0x00,0x00,0x0A, ++0x1C,0x40,0x2D,0xE9,0x67,0x70,0xA0,0xE1, ++0x03,0x00,0x2D,0xE9,0x10,0x00,0xA0,0xE3, ++0x10,0x10,0xA0,0xE3,0x00,0x00,0xA0,0xE3, ++0x0F,0x00,0xBD,0xE8,0x01,0xB0,0x8B,0xE2, ++0x01,0x00,0x5B,0xE3,0x27,0x70,0xB0,0x01, ++0x10,0x40,0xBD,0xE8,0x01,0x20,0x92,0x22, ++0x01,0x10,0x91,0x22,0x02,0x11,0xA0,0x23, ++0x00,0x30,0xA3,0xE2,0x02,0x01,0x00,0xE2, ++0x00,0x00,0x83,0xE1,0x1E,0xFF,0x2F,0xE1, ++0xFB,0xFF,0xFF,0x3A,0xA2,0x70,0xB0,0xE1, ++0xEA,0xFF,0xFF,0xEA,0x06,0x68,0x86,0xE1, ++0x40,0x00,0x73,0xE3,0x26,0x68,0xA0,0xE1, ++0x0F,0x00,0x00,0xDA,0x20,0x00,0x73,0xE3, ++0x02,0x60,0x86,0xD1,0x01,0x20,0xA0,0xD1, ++0x00,0x10,0xA0,0xD3,0x20,0x30,0x83,0xD2, ++0x00,0x30,0x73,0xE2,0xDD,0xFF,0xFF,0x0A, ++0x06,0x68,0x86,0xE1,0x20,0x70,0x63,0xE2, ++0x26,0x68,0xA0,0xE1,0x12,0x67,0x86,0xE1, ++0x32,0x23,0xA0,0xE1,0x11,0x27,0x82,0xE1, ++0x31,0x13,0xA0,0xE1,0x00,0x30,0xA0,0xE3, ++0xD4,0xFF,0xFF,0xEA,0x02,0x60,0x86,0xE1, ++0x00,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3, ++0x06,0x68,0x86,0xE1,0x26,0x68,0xA0,0xE1, ++0x01,0x60,0x86,0xE1,0x00,0x10,0xA0,0xE3, ++0x06,0x68,0x86,0xB1,0x26,0x68,0xA0,0xB1, ++0xCA,0xFF,0xFF,0xEA,0xC0,0x48,0x2D,0xE9, ++0x02,0xB0,0xA0,0xE1,0x30,0x00,0x2D,0xE9, ++0x38,0x00,0x91,0xE8,0x07,0x00,0x90,0xE8, ++0x80,0xC0,0xD1,0xE1,0x83,0xC0,0xD4,0x41, ++0x01,0x00,0x00,0x5A,0xED,0xFE,0xFF,0xEB, ++0xBE,0xFF,0xFF,0xEB,0xF0,0x00,0xBD,0xE8, ++0x00,0x88,0xBD,0xE8,0xC0,0x48,0x2D,0xE9, ++0x02,0xB0,0xA0,0xE1,0x30,0x00,0x2D,0xE9, ++0x38,0x00,0x91,0xE8,0x07,0x00,0x90,0xE8, ++0x01,0x01,0x10,0xE3,0x01,0x01,0x13,0x03, ++0x01,0x00,0x00,0x1A,0x02,0x00,0x00,0xEB, ++0xB2,0xFF,0xFF,0xEB,0xF0,0x00,0xBD,0xE8, ++0x00,0x88,0xBD,0xE8,0xFF,0x74,0xC0,0xE3, ++0x03,0x00,0x20,0xE0,0xFF,0xC4,0xC3,0xE3, ++0x0C,0x30,0x87,0xE0,0x3F,0x3C,0x43,0xE2, ++0x02,0x01,0x00,0xE2,0xFE,0x30,0x43,0xE2, ++0x00,0x00,0x32,0xE3,0x5D,0x00,0x00,0x0A, ++0x00,0x00,0x35,0xE3,0x3D,0x00,0x00,0x0A, ++0x01,0x49,0x2D,0xE9,0x21,0x08,0xA0,0xE1, ++0x24,0x68,0xA0,0xE1,0x00,0x88,0xC1,0xE1, ++0x90,0x06,0x0C,0xE0,0x06,0x78,0xC4,0xE1, ++0x98,0x06,0x06,0xE0,0x97,0x08,0x08,0xE0, ++0x90,0x07,0x07,0xE0,0x06,0x88,0x98,0xE0, ++0x26,0xC8,0xAC,0xE0,0x22,0xB8,0xA0,0xE1, ++0x07,0x88,0x98,0xE0,0x25,0x68,0xA0,0xE1, ++0x27,0x08,0xAC,0xE0,0x0B,0xE8,0xC2,0xE1, ++0x9B,0x06,0x0C,0xE0,0x06,0x78,0xC5,0xE1, ++0x9E,0x06,0x06,0xE0,0x97,0x0E,0x0E,0xE0, ++0x9B,0x07,0x07,0xE0,0x06,0xE8,0x9E,0xE0, ++0x26,0xC8,0xAC,0xE0,0x00,0x60,0xA0,0xE3, ++0x07,0xE8,0x9E,0xE0,0x27,0xB8,0xAC,0xE0, ++0x0B,0x80,0x98,0xE0,0x00,0x00,0xA0,0xE2, ++0x0E,0xB0,0x98,0xE0,0x00,0x80,0xB8,0xE0, ++0x00,0x00,0xA0,0xE2,0x02,0x70,0x51,0xE0, ++0x00,0x10,0xA0,0xE3,0x01,0x10,0xE0,0x31, ++0x05,0x60,0x44,0x30,0x04,0xC0,0x55,0x10, ++0x27,0x48,0xA0,0xE1,0x00,0x10,0xA0,0x03, ++0x07,0x60,0x46,0x30,0x04,0x58,0xC7,0xE1, ++0x2C,0x78,0xA0,0xE1,0x01,0x10,0xE0,0x31, ++0x94,0x67,0x22,0xE0,0x07,0xC8,0xCC,0xE1, ++0x95,0x07,0x07,0xE0,0x9C,0x05,0x06,0xE0, ++0x94,0x0C,0x0C,0xE0,0x07,0x68,0x96,0xE0, ++0x27,0x28,0xA2,0xE0,0x0C,0x68,0x96,0xE0, ++0x2C,0x28,0xA2,0xE0,0x06,0x60,0x9B,0xE0, ++0x0E,0xE1,0x8E,0xE1,0x02,0x20,0xB8,0xE0, ++0x01,0x10,0xB0,0xE0,0x2E,0x61,0x86,0xE1, ++0x01,0x89,0xBD,0x48,0x06,0x60,0x96,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x01,0x89,0xBD,0xE8, ++0x24,0x58,0xA0,0xE1,0x21,0x78,0xA0,0xE1, ++0x05,0x68,0xC4,0xE1,0x07,0xC8,0xC1,0xE1, ++0x95,0x07,0x04,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x01,0xE0,0x95,0x0C,0x0C,0xE0, ++0x07,0x18,0x91,0xE0,0x27,0x48,0xA4,0xE0, ++0x22,0x78,0xA0,0xE1,0x0C,0x18,0x91,0xE0, ++0x2C,0x48,0xA4,0xE0,0x07,0xC8,0xC2,0xE1, ++0x95,0x07,0x02,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x06,0xE0,0x95,0x0C,0x0C,0xE0, ++0x07,0x68,0x96,0xE0,0x27,0x28,0xA2,0xE0, ++0x0C,0x68,0x96,0xE0,0x2C,0x58,0xA2,0xE0, ++0x01,0x20,0x95,0xE0,0x00,0x10,0xB4,0xE2, ++0x1E,0xFF,0x2F,0x41,0x06,0x60,0x96,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x00,0x00,0x35,0xE3,0x1D,0x00,0x00,0x0A, ++0x21,0x28,0xA0,0xE1,0x24,0x78,0xA0,0xE1, ++0x02,0x68,0xC1,0xE1,0x07,0xC8,0xC4,0xE1, ++0x92,0x07,0x01,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x04,0xE0,0x92,0x0C,0x0C,0xE0, ++0x07,0x48,0x94,0xE0,0x27,0x18,0xA1,0xE0, ++0x25,0x78,0xA0,0xE1,0x0C,0x48,0x94,0xE0, ++0x2C,0x18,0xA1,0xE0,0x07,0xC8,0xC5,0xE1, ++0x92,0x07,0x05,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x06,0xE0,0x92,0x0C,0x0C,0xE0, ++0x07,0x68,0x96,0xE0,0x27,0x58,0xA5,0xE0, ++0x0C,0x68,0x96,0xE0,0x2C,0x28,0xA5,0xE0, ++0x04,0x20,0x92,0xE0,0x00,0x10,0xB1,0xE2, ++0x1E,0xFF,0x2F,0x41,0x06,0x60,0x96,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x24,0x58,0xA0,0xE1,0x21,0x78,0xA0,0xE1, ++0x05,0x68,0xC4,0xE1,0x07,0xC8,0xC1,0xE1, ++0x95,0x07,0x01,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x02,0xE0,0x00,0x60,0xA0,0xE3, ++0x95,0x0C,0x0C,0xE0,0x07,0x28,0x92,0xE0, ++0x27,0x18,0xA1,0xE0,0x0C,0x28,0x92,0xE0, ++0x2C,0x18,0xB1,0xE0,0x1E,0xFF,0x2F,0x41, ++0x02,0x20,0x92,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x94,0x04,0x03,0x20,0x74,0xD2,0x02,0x20, ++0x74,0xD3,0x02,0x20,0x00,0x80,0x4F,0xE1, ++0x1F,0x90,0x08,0xE2,0x12,0x00,0x59,0xE3, ++0x02,0x00,0x00,0x1A,0x40,0x80,0x88,0xE3, ++0x08,0xF0,0x61,0xE1,0x04,0xF0,0x5E,0xE2, ++0x30,0xD0,0x1F,0xE5,0x00,0x41,0x0D,0xE9, ++0xD2,0x80,0xA0,0xE3,0x08,0xF0,0x21,0xE1, ++0x40,0xD0,0x1F,0xE5,0x00,0x60,0x1D,0xE9, ++0x0D,0xF0,0x6F,0xE1,0x4C,0xD0,0x1F,0xE5, ++0x3F,0x00,0x2D,0xE9,0x04,0x00,0x4E,0xE2, ++0x00,0x10,0x4F,0xE1,0x06,0x20,0xA0,0xE3, ++0x0D,0x30,0xA0,0xE1,0x00,0x40,0x0F,0xE1, ++0x1F,0x40,0xC4,0xE3,0x53,0x40,0x84,0xE3, ++0x04,0xF0,0x21,0xE1,0x0D,0x50,0xA0,0xE1, ++0x0E,0x40,0xA0,0xE1,0x37,0x00,0x2D,0xE9, ++0x0D,0x00,0xA0,0xE1,0x00,0x20,0x0F,0xE1, ++0xC0,0x10,0x81,0xE3,0x20,0x10,0xC1,0xE3, ++0x01,0xF0,0x21,0xE1,0x00,0x7F,0x20,0xE9, ++0x02,0xF0,0x21,0xE1,0x00,0xD0,0xA0,0xE1, ++0x3F,0x00,0x93,0xE8,0xFF,0x00,0x2D,0xE9, ++0x40,0x10,0x9D,0xE5,0x1F,0x10,0x01,0xE2, ++0x13,0x00,0x51,0xE3,0x4C,0x10,0x9D,0x05, ++0x34,0x10,0x8D,0x05,0x0D,0xB0,0xA0,0xE1, ++0x0B,0x00,0xA0,0xE1,0xB4,0xD0,0xFF,0xFA, ++0x00,0x40,0xA0,0xE1,0x01,0x00,0x70,0xE3, ++0x02,0x00,0x00,0x1A,0x0B,0x00,0xA0,0xE1, ++0xB9,0xD0,0xFF,0xFA,0x05,0x00,0x00,0xEA, ++0xD8,0x10,0x1F,0xE5,0x04,0x11,0x91,0xE7, ++0xE4,0x20,0x1F,0xE5,0x04,0x61,0x92,0xE7, ++0x0B,0x20,0xA0,0xE1,0x36,0xFF,0x2F,0xE1, ++0x40,0x00,0x9D,0xE5,0x1F,0x10,0x00,0xE2, ++0x13,0x00,0x51,0xE3,0x04,0x00,0x00,0x1A, ++0x20,0x00,0x10,0xE3,0x00,0xF0,0x6F,0x11, ++0xFF,0xFF,0xDD,0x18,0x00,0xF0,0x2F,0xE1, ++0xFF,0xFF,0x9D,0xE8,0x00,0xF0,0x6F,0xE1, ++0x20,0x20,0x8D,0xE2,0x00,0x10,0x0F,0xE1, ++0xC0,0x00,0x80,0xE3,0x20,0x00,0xC0,0xE3, ++0x00,0xF0,0x21,0xE1,0x00,0x7F,0x92,0xE8, ++0x01,0xF0,0x21,0xE1,0x4C,0x00,0x9D,0xE5, ++0x20,0x00,0x8D,0xE5,0x48,0x00,0x9D,0xE5, ++0x24,0x00,0x8D,0xE5,0x3C,0x00,0x9D,0xE5, ++0x28,0x00,0x8D,0xE5,0xFF,0xE0,0xDD,0xE8, ++0x0F,0x00,0x00,0xEA,0x04,0xF0,0x1F,0xE5, ++0x41,0xCC,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x0F,0xD8,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x5D,0xCC,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x03,0xDE,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x3B,0xDE,0x03,0x20,0x78,0x47,0xC0,0x46, ++0x0D,0xD0,0xFF,0xEA,0x78,0x47,0xC0,0x46, ++0x0F,0xD0,0xFF,0xEA,0x78,0x47,0xC0,0x46, ++0x70,0x09,0xFF,0xEA,0x04,0xF0,0x1F,0xE5, ++0x00,0x00,0x00,0x00,0x04,0xF0,0x1F,0xE5, ++0x69,0xDB,0x03,0x20,0x81,0x10,0xA0,0xE1, ++0x81,0x05,0x90,0xE1,0x04,0x00,0xA0,0x13, ++0xA1,0x2A,0xB0,0xE1,0x14,0x20,0x9F,0xE5, ++0x01,0x00,0x80,0x13,0xA1,0x0A,0x52,0xE1, ++0x02,0x00,0x80,0x03,0x01,0x00,0x50,0xE3, ++0x05,0x00,0xA0,0x03,0x1E,0xFF,0x2F,0xE1, ++0xFF,0x07,0x00,0x00,0x10,0x40,0x2D,0xE9, ++0x00,0x00,0x51,0xE3,0x09,0x00,0x00,0x0A, ++0x00,0x00,0xD1,0xE5,0x00,0x00,0x50,0xE3, ++0x06,0x00,0x00,0x0A,0x20,0x00,0x9F,0xE5, ++0x00,0x00,0x8F,0xE0,0xAD,0xF9,0xFF,0xEB, ++0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A, ++0x00,0x00,0xB0,0xE3,0x10,0x80,0xBD,0xE8, ++0x08,0x00,0x9F,0xE5,0x00,0x00,0x8F,0xE0, ++0x10,0x80,0xBD,0xE8,0x18,0x03,0x00,0x00, ++0x04,0x03,0x00,0x00,0x10,0x40,0x2D,0xE9, ++0x00,0x00,0x51,0xE3,0x09,0x00,0x00,0x0A, ++0x00,0x00,0xD1,0xE5,0x00,0x00,0x50,0xE3, ++0x06,0x00,0x00,0x0A,0x20,0x00,0x9F,0xE5, ++0x00,0x00,0x8F,0xE0,0x9B,0xF9,0xFF,0xEB, ++0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A, ++0x00,0x00,0xB0,0xE3,0x10,0x80,0xBD,0xE8, ++0x08,0x00,0x9F,0xE5,0x00,0x00,0x8F,0xE0, ++0x10,0x80,0xBD,0xE8,0xE0,0x03,0x00,0x00, ++0xCC,0x03,0x00,0x00,0x1E,0xFF,0x2F,0xE1, ++0x00,0x00,0xA0,0xE3,0x1E,0xFF,0x2F,0xE1, ++0xC9,0xFF,0xFF,0xEA,0x64,0x77,0x6C,0x64, ++0x70,0x61,0x74,0x68,0x3D,0x30,0x78,0x25, ++0x78,0x2C,0x20,0x75,0x73,0x62,0x73,0x74, ++0x72,0x75,0x63,0x74,0x3D,0x30,0x78,0x25, ++0x78,0x2C,0x20,0x75,0x73,0x62,0x63,0x6D, ++0x64,0x6C,0x6F,0x6F,0x70,0x3D,0x30,0x78, ++0x25,0x78,0x2C,0x20,0x64,0x65,0x62,0x75, ++0x67,0x5F,0x6D,0x65,0x6D,0x5F,0x74,0x61, ++0x69,0x6C,0x3D,0x30,0x78,0x25,0x78,0x2C, ++0x20,0x62,0x6F,0x6F,0x74,0x73,0x74,0x72, ++0x61,0x70,0x2D,0x61,0x72,0x67,0x00,0x00, ++0xA1,0x35,0x03,0x20,0x1B,0x38,0x03,0x20, ++0x91,0x37,0x03,0x20,0xDF,0x37,0x03,0x20, ++0x1D,0x38,0x03,0x20,0x37,0x38,0x03,0x20, ++0xED,0x5F,0x03,0x20,0xE5,0x5F,0x03,0x20, ++0x00,0x04,0x00,0x08,0x18,0x08,0x18,0x00, ++0xC4,0x09,0xE2,0x04,0x71,0x02,0x38,0x01, ++0x9C,0x00,0x68,0x00,0x34,0x00,0x1A,0x00, ++0x0D,0x00,0x06,0x00,0x60,0x09,0x00,0x00, ++0xC0,0x12,0x00,0x00,0x80,0x25,0x00,0x00, ++0x00,0x4B,0x00,0x00,0x00,0x96,0x00,0x00, ++0x00,0xE1,0x00,0x00,0x00,0xC2,0x01,0x00, ++0x00,0x84,0x03,0x00,0x00,0x08,0x07,0x00, ++0x00,0x10,0x0E,0x00,0x00,0x00,0x00,0x00, ++0x07,0x00,0x00,0x00,0x05,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00, ++0x05,0x00,0x00,0x00,0x05,0x00,0x00,0x00, ++0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, ++0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, ++0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00, ++0x04,0x00,0x00,0x00,0x05,0x00,0x00,0x00, ++0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00, ++0x4A,0x45,0x44,0x45,0x43,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x1B,0x7C,0x03,0x20, ++0x00,0x00,0x00,0x00,0x45,0x7E,0x03,0x20, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x92,0xED,0x03,0x20,0x48,0x44,0x00,0x20, ++0xA2,0xED,0x03,0x20,0x58,0x54,0x00,0x20, ++0x5C,0xED,0x03,0x20,0x58,0x44,0x00,0x00, ++0x6E,0xED,0x03,0x20,0x68,0x54,0x00,0x00, ++0x80,0xED,0x03,0x20,0x78,0x54,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x08,0x00,0x01,0x0A,0x00,0x00,0x02, ++0x10,0x00,0x03,0x00,0x30,0x31,0x32,0x33, ++0x34,0x35,0x36,0x37,0x38,0x39,0x41,0x42, ++0x43,0x44,0x45,0x46,0x40,0x30,0x58,0x00, ++0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, ++0x38,0x39,0x61,0x62,0x63,0x64,0x65,0x66, ++0x40,0x30,0x78,0x00,0x04,0x00,0x00,0x08, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02, ++0x00,0x01,0x00,0x00,0x10,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x40,0x00,0x00,0x00,0x00,0x00,0xA0, ++0x00,0x00,0x00,0x00,0x05,0x40,0x00,0x00, ++0x00,0x00,0x00,0xC8,0x00,0x00,0x00,0x00, ++0x0C,0x40,0x00,0x00,0x00,0x00,0x40,0x9C, ++0x00,0x00,0x00,0x00,0x19,0x40,0x00,0x00, ++0x00,0x20,0xBC,0xBE,0x00,0x00,0x00,0x00, ++0x34,0x40,0x00,0x00,0xBF,0xC9,0x1B,0x8E, ++0x00,0x00,0x00,0x04,0xB5,0x40,0x00,0x00, ++0x50,0x4B,0xCF,0xD0,0x66,0x07,0xE2,0xCF, ++0x01,0x00,0x00,0x00,0x6C,0x41,0x00,0x00, ++0x3E,0x82,0x51,0xAA,0xDF,0xEE,0xA7,0x34, ++0x01,0x00,0x00,0x00,0xD9,0x42,0x00,0x00, ++0xDC,0xB5,0xA0,0xE2,0x3A,0x30,0x1F,0x97, ++0xFF,0xFF,0xFF,0xFF,0xB4,0x45,0x00,0x00, ++0xFD,0x25,0xA0,0xC8,0xE9,0xA3,0xC1,0x4F, ++0xFF,0xFF,0xFF,0xFF,0xFF,0x3F,0x00,0x00, ++0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00, ++0xFF,0x3F,0x00,0x00,0x00,0x00,0x00,0x80, ++0x00,0x00,0x00,0x00,0x52,0x5F,0x53,0x45, ++0x51,0x55,0x45,0x4E,0x43,0x45,0x5F,0x30, ++0x30,0x34,0x41,0x33,0x30,0x00,0x52,0x5F, ++0x53,0x45,0x51,0x55,0x45,0x4E,0x43,0x45, ++0x5F,0x30,0x30,0x35,0x41,0x33,0x30,0x00, ++0x52,0x5F,0x53,0x45,0x51,0x55,0x45,0x4E, ++0x43,0x45,0x5F,0x30,0x30,0x36,0x41,0x33, ++0x30,0x00,0x52,0x5F,0x53,0x45,0x51,0x55, ++0x45,0x4E,0x43,0x45,0x5F,0x30,0x30,0x33, ++0x41,0x00,0x52,0x5F,0x53,0x45,0x51,0x55, ++0x45,0x4E,0x43,0x45,0x5F,0x30,0x30,0x34, ++0x41,0x00,0x00,0x00,0x10,0x01,0x00,0x00, ++0x43,0x00,0x00,0x00,0xF8,0xFF,0xFF,0xFF, ++0x00,0x40,0x40,0x40,0x40,0x40,0x40,0x40, ++0x40,0x40,0x41,0x41,0x41,0x41,0x41,0x40, ++0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, ++0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, ++0x40,0x05,0x02,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02, ++0x02,0x20,0x20,0x20,0x20,0x20,0x20,0x20, ++0x20,0x20,0x20,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x90,0x90,0x90,0x90,0x90,0x90, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x02,0x02,0x02,0x02, ++0x02,0x02,0x88,0x88,0x88,0x88,0x88,0x88, ++0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08,0x02,0x02,0x02,0x02, ++0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0x00, ++0x43,0x00,0x00,0x00,0xF8,0xFF,0xFF,0xFF, ++0x0C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00, ++0x0F,0x00,0x00,0x00,0x2E,0x00,0x00,0x00, ++0x50,0x5B,0xE2,0x75,0xA4,0xA1,0xBA,0x71, ++0x57,0x63,0x9A,0xE4,0x3E,0xA6,0x00,0x0B, ++0x3D,0xC2,0x04,0xD9,0xBE,0xF5,0x2A,0x20, ++0x62,0xDA,0xC8,0xC2,0x54,0xCD,0x72,0x51, ++0xEB,0x59,0xD1,0xB0,0x86,0x83,0xC5,0x64, ++0xA0,0x5B,0x3E,0xBF,0x70,0xC9,0xF9,0x24, ++0x28,0xE1,0x5F,0xB6,0x0C,0x47,0x42,0x33, ++0x2F,0xF7,0xEC,0x86,0x33,0x1B,0x3D,0x3A, ++0x34,0xB5,0x8A,0xAC,0x80,0x01,0x6B,0xBC, ++0xFE,0x0E,0x7A,0xDE,0x2E,0xE1,0x84,0xA3, ++0x92,0x2D,0x16,0x40,0x7A,0x40,0x53,0x59, ++0x98,0x5E,0x74,0xF7,0xB5,0xAB,0x31,0xBB, ++0x7F,0xC4,0x6E,0xBE,0x5F,0x88,0x2E,0x05, ++0x0E,0x7F,0xA9,0x70,0xB2,0x2C,0x7B,0x29, ++0x66,0xF2,0xFB,0xBD,0xDF,0xF7,0x0F,0xF2, ++0x7A,0x6A,0xFD,0x24,0xA8,0x8C,0x3B,0x73, ++0x0B,0xD8,0x8B,0x83,0x8B,0x79,0x81,0xF0, ++0x1F,0xC5,0xD3,0x6F,0x3D,0xFE,0x8A,0xB8, ++0x45,0x1C,0xDD,0x10,0xB7,0x12,0xF9,0x2E, ++0x06,0xC9,0xBF,0xB8,0xC8,0xB7,0x6F,0x5F, ++0x24,0x5B,0xDB,0xC4,0x14,0x74,0xF5,0xA3, ++0xE3,0x4E,0x52,0x70,0x62,0x5E,0xA8,0x45, ++0xFB,0x3E,0x4C,0x94,0x7C,0xEF,0x46,0xE7, ++0x4F,0xB7,0xF7,0xBA,0xD0,0x0E,0x80,0x3D, ++0x86,0x68,0x85,0x80,0xEB,0xDC,0x6B,0xDD, ++0x3D,0xCA,0xE5,0x91,0x54,0xEB,0xCB,0x68, ++0x81,0xF6,0x4F,0xB4,0x88,0x10,0x71,0x9D, ++0x6D,0x26,0x32,0x6B,0x37,0x49,0xC4,0x5E, ++0x1F,0x57,0x68,0xC8,0x0C,0x3D,0x52,0x40, ++0x09,0xA9,0xEF,0x24,0x00,0xD4,0x5F,0x6E, ++0xE0,0x96,0x10,0xCE,0xB3,0x13,0x3C,0x32, ++0x9B,0xB4,0x78,0x00,0xB7,0x70,0x38,0x8E, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0x9B,0x30,0x36,0xE1,0xB0,0xFF,0x01,0x0D, ++0x58,0xA4,0xA4,0x09,0x02,0xE5,0x73,0xED, ++0x8F,0x7A,0xEC,0xDA,0xA4,0x30,0xA8,0xA3, ++0xF6,0x95,0x1C,0x9F,0xB9,0xB2,0x41,0x10, ++0x8A,0x9B,0x34,0x78,0x28,0x6E,0x88,0xED, ++0x66,0x0A,0xF9,0xDF,0xDD,0x84,0x1B,0x52, ++0x94,0x8B,0xF7,0xA2,0x2C,0xB9,0x6A,0xB8, ++0x0C,0x11,0x8C,0xB5,0x3B,0x40,0x52,0x43, ++0x30,0xEA,0xA7,0xBA,0xE4,0x11,0x55,0xEA, ++0xDA,0xD3,0x02,0x6F,0x94,0x41,0x91,0x20, ++0xA5,0x3F,0x4B,0x72,0xC8,0x2F,0x9B,0x11, ++0x30,0x80,0xEE,0x91,0x2C,0xC9,0x0D,0x8A, ++0xA8,0x1D,0x59,0x1B,0x5B,0xED,0xF5,0x5A, ++0x06,0x65,0x29,0x0C,0xFB,0xD6,0xCD,0xA4, ++0xFC,0x4F,0xD4,0x8B,0xB0,0x16,0x7F,0x01, ++0x70,0x7D,0x7F,0xFC,0x36,0xCE,0xA2,0xCD, ++0xDA,0xCF,0xFF,0xBB,0xA0,0x39,0x02,0x9C, ++0x62,0x0A,0xF7,0x71,0x63,0x01,0x26,0x6D, ++0x42,0xF6,0x77,0xBC,0x40,0x7D,0x9C,0x24, ++0x0B,0xD5,0xC5,0xF6,0xDF,0xBA,0xE7,0x86, ++0x30,0xC4,0xB3,0xAF,0x64,0xAD,0x76,0x65, ++0xE8,0xF3,0xDA,0xFC,0x55,0x84,0xFE,0xA3, ++0x81,0x0B,0xC6,0xF7,0xB4,0xD5,0x68,0x2F, ++0x5A,0xA9,0xC7,0xE2,0x9A,0x0F,0x7F,0x59, ++0xA5,0x93,0x93,0x44,0x73,0x50,0x8E,0x94, ++0x29,0x51,0xCE,0xA6,0x65,0xE4,0xC9,0x60, ++0xFF,0x73,0xD0,0x4B,0xB7,0x74,0xB1,0x03, ++0x15,0xAC,0x64,0x74,0xCD,0x53,0x86,0xE2, ++0xDD,0xA8,0x61,0x47,0x56,0x2B,0xA0,0x53, ++0x95,0xE8,0xFE,0xB3,0x76,0x6B,0x24,0xB1, ++0xD9,0x58,0xC1,0xB7,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x46,0x1B,0x3F,0xB6, ++0x10,0xE8,0xC1,0xB5,0x56,0x6B,0x23,0xB6, ++0xD5,0x78,0xFE,0xB3,0x54,0x2B,0xA0,0xB8, ++0xDD,0xF8,0x63,0x76,0x56,0x17,0x90,0x76, ++0x77,0x42,0xC8,0xDC,0xFC,0x81,0x0A,0x12, ++0x24,0x02,0xCB,0x17,0xD0,0x81,0x85,0x1B, ++0x77,0x0E,0x5B,0x14,0xFC,0x21,0x80,0x19, ++0x77,0xB2,0x40,0x1C,0xFD,0xF1,0x40,0x1B, ++0x7C,0x02,0x91,0x1D,0xFC,0x81,0x0A,0xE3, ++0x3C,0x02,0xCB,0x17,0xF3,0x81,0xB0,0x11, ++0x6F,0xE2,0x84,0x1E,0xFD,0x81,0x19,0x1A, ++0x74,0xF2,0x8C,0xEC,0xEF,0x7E,0x25,0x18, ++0x33,0x3F,0xCB,0xFC,0xA8,0xBC,0x0A,0xF9, ++0x77,0x32,0x7B,0x1F,0xFC,0xC1,0xBA,0x1A, ++0x77,0x52,0x7B,0x1F,0xFC,0xE1,0xBA,0x1A, ++0x67,0x22,0x99,0x1E,0x84,0x81,0xAB,0xD1, ++0x8B,0xFD,0x34,0x76,0x7E,0xAF,0xBA,0x18, ++0x47,0x02,0x6A,0xD4,0xFC,0xB1,0x8B,0xBC, ++0x69,0xFD,0xE4,0x1D,0x92,0x81,0x5B,0x1A, ++0x8B,0x0A,0xCB,0xF6,0x8C,0x81,0x5B,0x1A, ++0x34,0xC7,0x07,0x3A,0x56,0x4D,0x97,0xD6, ++0xBF,0xC1,0x07,0x3A,0x55,0x4D,0x97,0xD6, ++0xB9,0xC1,0x07,0x3A,0x57,0x4D,0x97,0xD6, ++0xBB,0xC1,0x07,0x3A,0x51,0x4D,0x97,0xD6, ++0xBB,0xCE,0xA7,0xD1,0x30,0x7D,0x56,0xD0, ++0x98,0xFA,0xB7,0xD1,0xB0,0x5D,0x47,0x16, ++0xD2,0xCE,0x56,0xD3,0xE0,0x45,0xC6,0x3F, ++0xDF,0xCE,0x56,0xD3,0xFE,0x45,0xC6,0x3F, ++0xCE,0xCE,0x56,0xD3,0xFC,0x45,0xC6,0x3F, ++0xD4,0xCE,0x56,0xD3,0x6A,0x44,0xC6,0x3F, ++0xC3,0xCE,0x56,0xD3,0x82,0x43,0xC6,0x3F, ++0x52,0xCE,0x56,0xD3,0x01,0x44,0xC6,0x3F, ++0x5F,0xCE,0x56,0xD3,0x1F,0x44,0xC6,0x3F, ++0x4E,0xCE,0x56,0xD3,0x1D,0x44,0xC6,0x3F, ++0x54,0xCE,0x56,0xD3,0x9C,0x43,0xC6,0x3F, ++0x43,0xCE,0x56,0xD3,0x9C,0x43,0xC6,0x3F, ++0xEE,0xAB,0xC2,0x80,0xC6,0x2B,0x23,0x81, ++0x6E,0x8B,0xD3,0x46,0x06,0x18,0xC2,0x83, ++0x25,0x90,0x52,0x6F,0x16,0x18,0xC2,0x83, ++0x49,0x95,0x52,0x6F,0x86,0x18,0xC2,0x83, ++0x3B,0x90,0x52,0x6F,0x96,0x18,0xC2,0x83, ++0x4B,0x95,0x52,0x6F,0x65,0x18,0x23,0x83, ++0xF0,0x64,0x7D,0x84,0x7A,0xAD,0x90,0x90, ++0x40,0x76,0x50,0x95,0xD1,0xF4,0x97,0x60, ++0xEE,0xBB,0x52,0x44,0x66,0xE8,0xCD,0x8D, ++0xAE,0x87,0x32,0x05,0x65,0x38,0x93,0x41, ++0xED,0x6B,0x2E,0x88,0x85,0x78,0x8C,0xDD, ++0xFE,0x2E,0x42,0xD8,0x9D,0x13,0x93,0x8B, ++0xEC,0x8B,0xF2,0x84,0x97,0xE7,0x6C,0x9A, ++0xF2,0x5B,0xCD,0x80,0x6A,0xD8,0x1F,0x80, ++0xEF,0x9B,0x4E,0x86,0x68,0xF8,0x1C,0x72, ++0xE1,0x7B,0xF2,0x64,0x79,0xE7,0xBC,0x81, ++0x98,0x2C,0xAA,0xF0,0x0E,0x90,0xCB,0xF6, ++0x9A,0x1C,0x95,0xEA,0x0E,0x6B,0xE4,0x17, ++0x69,0x13,0xDA,0xE8,0xED,0x90,0x1B,0xFC, ++0x1B,0x13,0xDA,0xF8,0x1A,0x6F,0x7B,0xF2, ++0x91,0xDC,0xBA,0xF7,0x12,0x4F,0x44,0xF6, ++0x87,0x13,0x0A,0xF3,0x12,0x6F,0xE7,0x37, ++0x99,0xAC,0x26,0x32,0x62,0x2F,0xC9,0xFE, ++0x99,0x8C,0x85,0xF3,0x32,0x3E,0x7B,0xF2, ++0xB9,0xCD,0xBA,0xF7,0x16,0x6F,0x71,0xF2, ++0xB9,0xAC,0xA7,0xF0,0x12,0x7F,0x65,0xF7, ++0x9B,0xEC,0x74,0xF3,0x19,0x6F,0xE4,0x8D, ++0x99,0xFC,0x85,0xF1,0x12,0x4F,0x44,0xF6, ++0x9D,0xEC,0x77,0xF3,0x13,0x7F,0x65,0x25, ++0x98,0xCC,0xA7,0x20,0xE9,0x90,0x1B,0x2D, ++0xB9,0xCC,0x85,0xF1,0xDC,0x68,0xE4,0xFC, ++0x75,0xEC,0xBA,0xF7,0x16,0x6F,0x61,0xF2, ++0x67,0x13,0x7A,0x0E,0xED,0x90,0xDE,0x0D, ++0x66,0x13,0x7A,0x0E,0xED,0xB0,0xCD,0x0F, ++0x66,0x13,0x88,0x0E,0xE9,0x80,0x8E,0xFD, ++0x67,0x13,0x5A,0xFF,0xEC,0xB0,0xDA,0xFC, ++0x62,0x03,0x5F,0xF8,0x15,0x6F,0xE4,0xF2, ++0x66,0x13,0x0F,0x08,0xEC,0x90,0x4B,0x0B, ++0x16,0x93,0x67,0xF5,0xE7,0x80,0xBB,0x0B, ++0x62,0x13,0x4F,0x08,0xEC,0x80,0xDB,0x0C, ++0x66,0x03,0x7A,0x0E,0xED,0xA0,0xBB,0x09, ++0x62,0x13,0x5F,0x08,0xEC,0x90,0x1B,0x02, ++0x67,0x03,0x5B,0x0F,0xEC,0xA0,0x98,0x0A, ++0x67,0x33,0x0A,0x0A,0xD1,0x90,0x49,0x0B, ++0x62,0x13,0x89,0xFC,0x14,0x6F,0xE4,0xD2, ++0x46,0x33,0x7A,0x0E,0x5D,0x97,0x1B,0x03, ++0x62,0x13,0x4F,0x08,0xEC,0x90,0x5B,0x0A, ++0x62,0x13,0x5F,0x08,0x9D,0x10,0xA6,0x00, ++0xE1,0x9B,0x7F,0x8C,0x64,0x04,0x33,0x83, ++0xEA,0x7B,0x7F,0x80,0x24,0xC7,0xDE,0x82, ++0xAD,0xA4,0xDF,0x87,0x61,0x18,0x1E,0x82, ++0xE6,0xBA,0xCF,0x80,0x63,0x1F,0x93,0x9A, ++0xEE,0x8B,0xF2,0x84,0x61,0x18,0x1E,0x82, ++0x2F,0x64,0xAD,0x8E,0x24,0xC7,0x1E,0x82, ++0xFA,0x6B,0xCF,0x81,0x65,0x18,0xC3,0x83, ++0xFE,0xDB,0x7F,0x8C,0x45,0x58,0x0C,0x85, ++0xEF,0x97,0xD2,0x77,0x45,0x18,0x0C,0x65, ++0xEA,0x9B,0xD6,0x80,0x79,0x18,0x1C,0x82, ++0x04,0x64,0xAD,0x8E,0x61,0x08,0x07,0x85, ++0xD2,0x9B,0xDD,0x87,0x75,0x58,0x2E,0x88, ++0x08,0x64,0xAD,0x8F,0x7D,0x97,0x91,0x40, ++0x0E,0x94,0x50,0x45,0x65,0x18,0x91,0x40, ++0xD3,0xA6,0x6F,0x58,0x58,0x25,0xAE,0x5D, ++0xD3,0xA6,0x6F,0x58,0x58,0x25,0xAE,0x5D, ++0xE0,0x95,0x5C,0x6B,0x6B,0x16,0x9D,0x6E, ++0xE0,0x95,0x5C,0x6B,0x6B,0x16,0x9D,0x6E, ++0xE0,0x95,0x5C,0x6B,0x6B,0x16,0x9D,0x6E, ++0xD7,0xA8,0x61,0x56,0x19,0x7F,0xF0,0x73, ++0x9E,0xDD,0x13,0x24,0x33,0x45,0xD4,0x73, ++0xAD,0xC7,0x08,0x38,0x22,0x4E,0xD2,0x73, ++0xA9,0xC7,0x41,0x26,0x12,0x4E,0xC2,0x26, ++0xBA,0xE5,0x04,0x3B,0x76,0x4A,0xC4,0x37, ++0xAF,0xCD,0x12,0x25,0x76,0x0E,0xCC,0x2B, ++0xD7,0xA8,0x61,0x56,0x62,0x38,0x3F,0xB6, ++0x6D,0xA8,0xA0,0xB7,0xE6,0x2B,0x71,0xB2, ++0xC3,0x57,0x4E,0xB7,0x7E,0x28,0x3F,0xB6, ++0xBD,0xA4,0xF1,0xB3,0x46,0x2B,0xB0,0xB1, ++0xDC,0xA8,0xC1,0x45,0x48,0xD4,0x8F,0xB2, ++0xCD,0xBB,0xFE,0xB3,0xE2,0x2B,0x61,0xB2, ++0x69,0xA8,0xB0,0xB7,0x48,0xD4,0x8F,0xB2, ++0x34,0xFA,0x5D,0xAE,0x47,0xFA,0x11,0xA3, ++0xCC,0xFA,0xEF,0xA2,0x46,0x5A,0x11,0xA3, ++0xCE,0xC9,0xD0,0xA6,0x00,0x3A,0x11,0xA1, ++0x27,0x46,0x8F,0xAC,0xB7,0x68,0x2E,0xA7, ++0xCC,0xB9,0x27,0xA4,0x4D,0x3A,0xB1,0x58, ++0x74,0xA9,0xA6,0xA6,0xFD,0x3A,0x67,0xA3, ++0x72,0x99,0xA6,0xA6,0x53,0xBA,0x2D,0xA7, ++0xC8,0xD9,0x30,0xA5,0xD6,0x3A,0xB0,0xA2, ++0x5F,0xAB,0x51,0xA7,0x67,0x2A,0x30,0xA0, ++0xCE,0xFB,0xF1,0xA5,0x58,0x70,0x35,0xA0, ++0xEC,0xB9,0x70,0xAD,0x46,0x3A,0xE6,0xA1, ++0xC9,0x39,0xD0,0x46,0x5D,0x3A,0xB1,0x48, ++0xCE,0xB9,0x27,0xA4,0x76,0x3A,0xB1,0x58, ++0xD8,0x39,0xEC,0xA2,0x77,0x3A,0x11,0xA1, ++0x19,0x46,0x8F,0xAC,0x47,0x2A,0x25,0xA7, ++0x54,0x9B,0xEF,0xA2,0x45,0x3A,0xE0,0xA3, ++0xF0,0x2F,0x66,0xCC,0xDA,0xA3,0x28,0xC1, ++0xE5,0x32,0x3D,0x3F,0xDC,0xA3,0x79,0x38, ++0x50,0x20,0xE9,0xD4,0xDC,0x83,0x88,0x38, ++0xF6,0x2F,0x66,0x3C,0x49,0x5C,0xD7,0x30, ++0xF3,0x2F,0x66,0x3C,0x4B,0x5C,0xD7,0x30, ++0x75,0x20,0xE9,0x34,0xEE,0xB3,0x88,0x38, ++0x51,0x20,0x49,0x3F,0xBF,0xA2,0x28,0x30, ++0x65,0x30,0x7D,0x3B,0xDE,0xA3,0x79,0x3A, ++0x55,0x00,0x49,0xCF,0x7C,0xAC,0xA7,0xC9, ++0xA6,0xDF,0x16,0xC4,0xC6,0xF3,0xBC,0x3E, ++0x49,0x40,0x7D,0x3B,0xD8,0xE3,0xAD,0x3B, ++0x55,0x40,0x64,0x3B,0xDB,0x93,0x88,0x3A, ++0x5D,0x00,0x49,0x3F,0xDA,0xB3,0x88,0x3A, ++0x5F,0x2D,0x66,0x3C,0x5D,0x5C,0xD7,0x30, ++0x55,0x40,0x64,0x3B,0xDB,0x93,0x88,0x3A, ++0x5D,0x00,0x49,0x3F,0xDA,0xB3,0x88,0x3A, ++0xAA,0xDF,0xB6,0xC2,0xDB,0x5D,0xD7,0xCF, ++0xAA,0xDF,0x46,0xC2,0x25,0x5C,0xD7,0x3E, ++0xAD,0xCF,0xB6,0xC0,0x82,0x53,0x58,0xC6, ++0xD2,0x20,0xE9,0xCA,0x20,0x5C,0x77,0xC7, ++0x52,0x5C,0xAB,0xC9,0x21,0x4C,0x77,0xC5, ++0x0F,0xD0,0x99,0xC3,0x52,0xA3,0x28,0xCF, ++0xAA,0xDF,0xB6,0xC2,0xD9,0xDF,0x6A,0xCC, ++0x5A,0x9E,0x3B,0xC8,0x21,0x1C,0x67,0xC5, ++0xAB,0xAF,0xB6,0xC0,0x21,0x0C,0x77,0xC7, ++0x84,0xDF,0x16,0x2B,0x80,0x5C,0x77,0xC7, ++0x1A,0xBE,0x89,0xC4,0x21,0x5C,0x51,0xC1, ++0x8C,0xDF,0x16,0xCB,0x25,0x0C,0x51,0xC1, ++0xAD,0xDF,0xB6,0xC0,0xF9,0x5A,0xD7,0xCF, ++0xAA,0xFF,0xB6,0xC0,0x26,0x4C,0x77,0xC5, ++0xAE,0xDF,0xB6,0xC0,0xBD,0x5A,0xD7,0xCF, ++0xAA,0xDF,0x46,0xC2,0x3A,0x5C,0xD7,0x3E, ++0x6F,0xB9,0xD0,0xA4,0x56,0x3A,0x37,0xAA, ++0xCB,0xB9,0xD0,0xA6,0x89,0x3C,0xB1,0xA9, ++0xC4,0xB9,0xF6,0xA2,0x40,0x3A,0x11,0xA3, ++0x07,0xBF,0x70,0xAC,0x43,0x3A,0x31,0xA2, ++0xCD,0xB9,0xF0,0xA5,0x4B,0x3A,0x37,0xA7, ++0xCB,0xB9,0xD0,0xA6,0x81,0x3C,0xB1,0xA9, ++0xC8,0xB9,0xF0,0xA7,0x57,0x1A,0x11,0xA1, ++0xCD,0xB9,0xF0,0xA5,0x47,0x2A,0x11,0xA1, ++0xA0,0xBF,0x70,0xBD,0x57,0x3A,0x37,0xA7, ++0x68,0xB9,0xD0,0xA4,0x47,0x3A,0x37,0xA7, ++0xCB,0xB9,0xD0,0xA6,0xFB,0x3C,0xB1,0xA9, ++0xC8,0xB9,0xF0,0xA7,0x57,0x1A,0x11,0xA1, ++0x3C,0xF8,0xCD,0xAF,0x46,0x3A,0x31,0xA0, ++0xCC,0xA9,0xD0,0xA4,0x18,0x3C,0xB1,0xA8, ++0xCD,0xE9,0xF5,0xA5,0x46,0x7A,0x35,0xA0, ++0xCC,0xB9,0xA4,0xA2,0x47,0x3A,0xE1,0xA1, ++0x89,0xF1,0x61,0x10,0xD7,0x81,0x0A,0xBC, ++0x88,0xFD,0x94,0xE0,0xF3,0xFF,0x48,0xEE, ++0x78,0xBC,0x19,0xEA,0xA8,0x7E,0x55,0xE5, ++0x60,0xBD,0xAB,0xE6,0x04,0x63,0x7A,0xE4, ++0x88,0xFD,0xB0,0xE6,0xB7,0x7F,0x6A,0xE3, ++0x84,0xFD,0xB0,0xE6,0xC2,0x81,0x0A,0xED, ++0x88,0xAD,0x94,0xE2,0x3D,0x81,0x0A,0xED, ++0x28,0xEC,0xAB,0xE6,0x06,0x5E,0x55,0xE7, ++0xE3,0xF2,0xBB,0xE1,0x2E,0x81,0x0A,0xED, ++0x18,0xFC,0xAB,0xE6,0x04,0x63,0x7A,0xE4, ++0x30,0x02,0xCB,0xE8,0xFC,0x2E,0xF5,0xE4, ++0x8F,0xF0,0xBB,0xE1,0x06,0x6E,0x55,0xE7, ++0xAE,0x02,0xCB,0xE8,0xCF,0x7E,0x55,0xE5, ++0x88,0x9D,0x94,0xE0,0x03,0x7E,0x71,0xE3, ++0xBC,0xFF,0x35,0xE0,0x17,0x2E,0x51,0xE3, ++0x8C,0xFD,0xB0,0xE6,0x18,0x70,0x7A,0xE4, ++0xEC,0x70,0x67,0x2A,0x11,0xCE,0x7D,0x28, ++0x58,0xCE,0x07,0x24,0xF1,0xB3,0x39,0x21, ++0x44,0x31,0xA8,0x2C,0x4C,0xB2,0x39,0xD0, ++0x02,0x31,0x58,0x2C,0x85,0x4D,0xC6,0x21, ++0x45,0x31,0xAD,0x2C,0xBD,0xB2,0x39,0xD0, ++0x0D,0x31,0x58,0x2C,0x80,0x4D,0xC6,0x21, ++0x26,0x3E,0x77,0x2D,0xDE,0x4D,0xC6,0x21, ++0x44,0x01,0x58,0x2C,0xC8,0xA2,0x99,0x2B, ++0x47,0x11,0x58,0x2E,0xCB,0xB2,0x99,0x2B, ++0x08,0xCE,0x07,0x24,0xCE,0xB2,0x69,0x29, ++0x33,0x31,0xF8,0xD5,0x92,0xBD,0xB6,0x28, ++0x4C,0xCE,0x07,0x24,0x85,0xB2,0x99,0x29, ++0x06,0xCE,0x07,0x24,0xCE,0x82,0x99,0x29, ++0x43,0x21,0x58,0x2E,0xCC,0x92,0x99,0x2B, ++0x40,0x31,0x58,0x2E,0x8E,0x4D,0xC6,0x21, ++0x45,0x31,0xA8,0x2C,0xA3,0xB2,0x39,0xD0, ++0x21,0x0D,0x44,0x1E,0x98,0x81,0x0A,0x13, ++0x77,0x3E,0xFB,0xD9,0xFC,0x91,0x3A,0xDC, ++0x77,0x0C,0xCB,0xDC,0xDC,0x71,0x0B,0xD9, ++0x50,0x35,0x5A,0xC9,0x91,0xE0,0x6D,0x90, ++0x14,0x2A,0xEE,0x90,0x84,0xAD,0x2F,0x95, ++0x0F,0x2B,0xC1,0xFC,0x95,0xEC,0x6B,0x9E, ++0x12,0x56,0xB2,0x8C,0x99,0xA9,0x2F,0x95, ++0x0F,0x2E,0xEE,0x90,0x84,0xA8,0x00,0xF9, ++0x15,0x6D,0xA4,0x8F,0x88,0xF3,0x6B,0x89, ++0x57,0x6A,0xAE,0x9D,0x98,0xE4,0x78,0xA2, ++0x39,0x45,0x96,0xFC,0x94,0xE4,0x6B,0x9D, ++0x12,0x70,0x88,0x94,0x99,0xE2,0x61,0x8A, ++0x02,0x6F,0xE3,0xD9,0x90,0xF9,0x26,0xDC, ++0x1B,0x7A,0xE2,0xF6,0xFC,0x81,0x0A,0xF9, ++0x57,0x74,0xBB,0xAF,0x95,0xE6,0x64,0x98, ++0x03,0x77,0xB9,0x99,0xD4,0xA4,0x66,0x81, ++0x92,0xEE,0x71,0x40,0x7B,0x28,0xBF,0x1D, ++0x9E,0xA2,0x7F,0x19,0x10,0x3B,0xB6,0x71, ++0xDA,0xBA,0x66,0x18,0x15,0x21,0xBE,0x1C, ++0x9B,0xBB,0x34,0x02,0x63,0x24,0xBC,0x50, ++0x93,0xEB,0x6B,0x48,0x19,0x47,0xC6,0x35, ++0xD4,0xBA,0x77,0x6F,0x43,0x28,0xA5,0x40, ++0xC9,0xA7,0x73,0x49,0x6F,0x2E,0xAE,0x50, ++0xD8,0xA5,0x2F,0x15,0x48,0x64,0x9D,0x7A, ++0xF0,0x93,0x0D,0x30,0x5F,0x39,0xB6,0x6A, ++0xC8,0xAB,0x64,0x45,0x42,0x24,0xB2,0x4C, ++0xE4,0xAD,0x6F,0x55,0x53,0x26,0xEE,0x10, ++0xC3,0xE7,0x5C,0x7E,0x77,0x10,0xCC,0x35, ++0xBB,0x1E,0x05,0x10,0x54,0x28,0xA4,0x40, ++0xDC,0x91,0x6A,0x55,0x5D,0x12,0xB2,0x54, ++0xD2,0xA2,0x07,0x30,0x52,0x22,0xA9,0x41, ++0x9B,0xBE,0x66,0x42,0x51,0x20,0xFC,0x10, ++0x2D,0x0C,0xC9,0xBB,0xB0,0xC7,0x77,0xB4, ++0x33,0x7F,0x84,0xBB,0xB3,0x9E,0x18,0xA3, ++0x70,0x58,0xE3,0xDE,0xBC,0xCC,0x47,0xAF, ++0x38,0x4F,0x8D,0xBB,0xDE,0xA3,0x28,0xDB, ++0x37,0x4F,0x86,0xAA,0xB3,0xCC,0x4C,0xBE, ++0x68,0x10,0x91,0xFB,0xA6,0xA9,0x28,0xDB, ++0x55,0xEE,0xEB,0xFE,0xB1,0xD7,0x58,0x84, ++0x3C,0x4E,0x80,0xAA,0xF6,0x8A,0x22,0xDB, ++0x37,0x4F,0x86,0xAA,0xFE,0xCD,0x47,0xA9, ++0x38,0x41,0x85,0xD4,0xDE,0xA3,0x28,0xDB, ++0x27,0x4F,0x86,0xAA,0xFE,0xC8,0x4D,0xA2, ++0x75,0x70,0x88,0xAD,0xAD,0xA9,0x28,0xDB, ++0x37,0x4F,0x86,0xAA,0xB2,0xCC,0x49,0xBF, ++0x30,0x52,0xC9,0x8E,0xBF,0xD0,0x5B,0xD1, ++0x55,0x20,0xE9,0xDE,0x95,0xA3,0x88,0x38, ++0x89,0xDE,0x16,0x35,0xDC,0x93,0x88,0x38, ++0x34,0x56,0x2F,0x59,0xBB,0xE5,0xEE,0x5C, ++0x37,0x46,0x2F,0x59,0x63,0x3B,0xB1,0x56, ++0x32,0x46,0xDF,0x5B,0xBE,0xC5,0x4E,0xA7, ++0xEF,0x46,0x00,0x5A,0x2F,0x3B,0xB1,0x56, ++0x32,0x26,0x2F,0x5B,0xBA,0xC5,0x4E,0x57, ++0x33,0x56,0x2F,0x59,0x60,0xC5,0xC1,0x5F, ++0xA1,0xB8,0x70,0x53,0xF6,0xC5,0xEE,0x5E, ++0xF0,0xB8,0x70,0x53,0xB8,0xC5,0xDA,0x58, ++0xEB,0x56,0x10,0x5D,0xB9,0xC5,0x1E,0x5C, ++0x23,0x46,0x8F,0xA2,0x68,0xC5,0xC1,0x5F, ++0xB9,0xB8,0x70,0x53,0xAC,0xD5,0xDA,0x58, ++0xEF,0x46,0x00,0x5A,0xB4,0xE5,0xDA,0x58, ++0xB5,0xB8,0x70,0x53,0xAC,0xC5,0xDA,0x58, ++0x3F,0x56,0x1B,0x5D,0x8C,0xC3,0x4E,0x56, ++0x37,0x46,0x1B,0x5D,0xB4,0xD5,0xDA,0x58, ++0x32,0x46,0xCF,0x58,0xA8,0xD5,0xDA,0x58, ++0x13,0x66,0xCF,0x5A,0x78,0xC5,0xC1,0x5F, ++0x4F,0xB8,0x70,0x53,0xB9,0xC5,0x4E,0x57, ++0xF7,0x46,0x00,0x5A,0xC1,0x3B,0xB1,0x56, ++0x33,0x46,0xD9,0x5B,0xB6,0xC5,0x4E,0xA7, ++0x7E,0x46,0x2F,0x5B,0x09,0x3B,0xB1,0x56, ++0x98,0xB8,0x70,0x53,0xB9,0xC5,0x1E,0x5E, ++0x3A,0x46,0x8F,0xA2,0xF7,0xC5,0xEE,0x5E, ++0x90,0xB8,0x70,0x53,0x14,0xC5,0xC1,0x5F, ++0x5D,0xB8,0x70,0x53,0x08,0xF5,0xD1,0x58, ++0x9F,0x66,0x2F,0x5B,0x14,0xD5,0xC1,0x5F, ++0x83,0x46,0x00,0x5A,0xD1,0x3B,0xB1,0x56, ++0xCD,0xB9,0x70,0x52,0xF4,0xC5,0xEE,0x5E, ++0xAA,0xB8,0x70,0x53,0x04,0x85,0xD1,0x58, ++0x8F,0x46,0x00,0x5A,0xDB,0x3B,0xB1,0x56, ++0x07,0xB9,0xA0,0x59,0xB8,0xC5,0xEE,0x5E, ++0xC3,0xC7,0x32,0x50,0xDA,0xAA,0x21,0xC9, ++0xD9,0xAB,0x64,0x40,0x51,0x7C,0x87,0x45, ++0xD9,0xAC,0x1C,0x21,0x4E,0x28,0xA7,0x7B, ++0xC3,0xB1,0x7F,0x55,0x09,0x79,0xAF,0x0D, ++0xF1,0x91,0x51,0x7C,0x2B,0x5C,0xD7,0x24, ++0x61,0xEE,0x59,0x76,0x42,0x30,0xB2,0x45, ++0xD8,0x80,0x65,0x44,0x4F,0x2F,0xBE,0x50, ++0xC3,0xA9,0x73,0x7E,0x45,0x3D,0xA3,0x45, ++0xA0,0xDF,0x16,0x21,0x01,0x37,0xB2,0x5D, ++0x82,0xFA,0x7A,0x59,0x0D,0x79,0xBB,0x5C, ++0x83,0xD5,0x16,0x21,0x01,0x3A,0xA2,0x4A, ++0xC9,0xF7,0x33,0x4D,0x59,0x70,0xF2,0x48, ++0xD2,0xF6,0x1C,0x21,0x4E,0x28,0xA7,0x7B, ++0xC2,0xBA,0x77,0x45,0x44,0x2E,0xF7,0x4A, ++0xC5,0xFF,0x7F,0x4F,0x47,0x33,0xDD,0x24, ++0xCE,0xBA,0x77,0x45,0x7E,0x30,0xB8,0x4B, ++0xDA,0xD5,0x16,0x21,0xDD,0xD0,0xD5,0x04, ++0x7C,0x05,0xC4,0xF4,0xB4,0x84,0x6C,0x9F, ++0x53,0x31,0xEA,0xA0,0xBA,0x81,0x0D,0xF6, ++0x7D,0x11,0xDF,0xFF,0xBA,0x86,0x18,0xBF, ++0x34,0x17,0x97,0xBF,0xFE,0xC8,0x49,0xEC, ++0x39,0x4D,0x8C,0x90,0x9A,0xE7,0x6C,0x9F, ++0x11,0x74,0xAD,0xBA,0xD0,0x92,0x01,0xEF, ++0x31,0x10,0xC2,0xBA,0xC8,0xA6,0x21,0xBF, ++0x72,0x0B,0xC9,0xFF,0x90,0xE7,0x6C,0x9F, ++0xE1,0x25,0x80,0x73,0x9A,0xA7,0xDC,0x7E, ++0x10,0x14,0x0D,0x7B,0x9B,0xE7,0xCC,0x9C, ++0xE1,0xE5,0x10,0x92,0x9B,0xB7,0xCC,0x7C, ++0x11,0x04,0x0D,0x79,0xDC,0xE7,0x6C,0x75, ++0xA1,0x61,0xAC,0x79,0x9A,0xE7,0x3B,0x7E, ++0x16,0x64,0x0D,0xAB,0x9A,0x97,0x2B,0x7F, ++0x20,0x64,0xAD,0x70,0x9A,0xF7,0xB8,0x7A, ++0x01,0x64,0xED,0x78,0x9B,0xD7,0xB8,0x7A, ++0x27,0x47,0x1F,0x49,0xA8,0xF4,0xD9,0x4C, ++0x21,0x47,0x1F,0x49,0xAB,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x21,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xAD,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x27,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xAF,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x25,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xA1,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x2B,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xA3,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x29,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x65,0x03,0x5B,0x0D,0xE1,0xA0,0xCF,0x0D, ++0x67,0x33,0x58,0x0D,0xEE,0x80,0x9A,0x08, ++0x6B,0x23,0x0E,0x08,0xEC,0xB0,0x99,0x08, ++0x65,0x03,0x5B,0x0D,0xE3,0xA0,0xCF,0x0D, ++0x67,0x33,0x58,0x0D,0xEE,0x80,0x9A,0x08, ++0x69,0x23,0x0E,0x08,0xEC,0xB0,0x99,0x08, ++0x76,0x53,0x5E,0x0F,0xEC,0xC0,0x98,0x08, ++0x63,0x73,0x58,0x0D,0xFD,0x90,0x4B,0x0B, ++0xAD,0xEC,0x25,0xC7,0xED,0x90,0x4B,0x0B, ++0x67,0x03,0x0E,0xF9,0xEC,0x90,0x5B,0xFA, ++0x67,0x43,0x5F,0xFD,0xE8,0xF0,0x9D,0xF8, ++0x9F,0xEC,0x25,0xF7,0x1C,0x8F,0x14,0x0B, ++0x63,0x13,0x7A,0x0C,0xC3,0x9A,0x1B,0x03, ++0x67,0x43,0x7A,0x0C,0x1C,0x8F,0x14,0x0B, ++0x60,0x13,0x7A,0x0C,0xC7,0x9A,0x1B,0x03, ++0x67,0x73,0x7A,0x0C,0xED,0x90,0x4C,0x0B, ++0x2F,0x13,0xDA,0x08,0x14,0x67,0x61,0xF6, ++0x69,0x6D,0x98,0xFA,0x76,0x6F,0x7B,0xF2, ++0x29,0xFA,0xF5,0xF3,0x13,0x76,0x25,0xF4, ++0x29,0xFA,0xE5,0xF3,0x1C,0x43,0xA4,0xF5, ++0xED,0xFE,0xB7,0xF7,0x52,0x7F,0x25,0xF4, ++0xED,0xFE,0xA7,0xF7,0x5A,0x7F,0x7B,0xF2, ++0xD1,0xCC,0xB4,0xF7,0x92,0x4F,0x26,0xF4, ++0xD1,0xCC,0xA4,0xF7,0x12,0x4F,0x04,0xF4, ++0xD9,0xCC,0xA4,0xF7,0x5A,0x4F,0x75,0xF2, ++0x1B,0xCC,0xA7,0xF1,0x5A,0x4F,0x65,0xF2, ++0x21,0xFA,0xF5,0xF3,0x6D,0x7F,0x25,0xF4, ++0x89,0xFC,0xA4,0xF1,0xAA,0x79,0x24,0xF6, ++0xDE,0xFC,0xA4,0xF1,0xAA,0x79,0x24,0xF6, ++0x89,0xFC,0xE4,0xF1,0xAA,0x79,0x24,0xF6, ++0x99,0xEC,0x85,0xF1,0x0C,0x90,0xCB,0xF6, ++0x99,0x92,0x25,0x37,0x12,0x4F,0xD4,0x32, ++0xB4,0x76,0xD5,0x26,0xCF,0xC2,0x99,0x2B, ++0x07,0xEF,0xB5,0x2D,0xCE,0x32,0x99,0x2B, ++0x46,0xA1,0x58,0x2E,0xCC,0xD2,0x99,0x2B, ++0x14,0x95,0x65,0x2A,0x8E,0xEC,0xB4,0x28, ++0x41,0x01,0x58,0x2E,0xC9,0xA2,0x99,0x2B, ++0x4E,0x11,0x58,0x2E,0x84,0xBD,0xB6,0x28, ++0xF6,0xCC,0x07,0x24,0xCA,0x92,0x99,0x2B, ++0x4E,0x21,0x58,0x2E,0xC9,0xB2,0x99,0x2B, ++0x65,0x35,0xF8,0x24,0xCF,0xF2,0x99,0x2B, ++0x44,0x21,0x58,0x2E,0xCF,0xE2,0xB4,0x2F, ++0x4E,0x01,0x58,0x2E,0xC9,0x92,0x99,0x2B, ++0x57,0x3F,0x77,0x2D,0x68,0x4F,0xC6,0x21, ++0x44,0x31,0xAC,0x2C,0xCB,0xB2,0x99,0xDB, ++0x52,0x31,0xF8,0xD5,0x99,0xBD,0xB6,0x28, ++0xE6,0xCC,0x07,0x24,0xDF,0xD2,0xB4,0x28, ++0x4D,0x11,0x58,0x2E,0xC9,0x82,0x99,0x2B, ++0x19,0x74,0x0D,0x7B,0x9D,0xE7,0xCC,0x7E, ++0x25,0x67,0xAD,0x71,0x9F,0xEA,0xE3,0x7D, ++0x8B,0x99,0x52,0x71,0x9A,0xA7,0xCC,0x7C, ++0x15,0x64,0x7B,0x7D,0x9E,0xF7,0xB9,0x78, ++0x10,0x64,0xFD,0x7B,0x93,0xE7,0x6C,0x95, ++0x15,0x54,0x78,0x7D,0x9E,0xF7,0xCC,0x7E, ++0x5B,0x6B,0x22,0x78,0x9A,0xD7,0xE1,0x7A, ++0x15,0x54,0x0D,0x7B,0x9E,0xC7,0xBA,0x78, ++0x9F,0x99,0x52,0x71,0x98,0xE7,0xCC,0x7C, ++0x52,0xBA,0x20,0x78,0x6A,0x60,0xD1,0x77, ++0x0E,0x64,0xF9,0x79,0x9E,0xF7,0xCC,0x9E, ++0x5B,0x6B,0x22,0x98,0x1D,0x1A,0x93,0x94, ++0x10,0x24,0x29,0x78,0xBA,0xE7,0x38,0x7C, ++0xFB,0x9B,0x52,0x20,0x9A,0xE7,0xCC,0x7C, ++0xE5,0x9B,0x52,0x70,0xEA,0xA7,0x41,0x76, ++0x12,0x34,0x0D,0x7B,0xD8,0x38,0x21,0x7D, ++0x23,0x57,0x3E,0x48,0xA9,0x94,0xFF,0x4F, ++0x2A,0x47,0x13,0x4B,0xB1,0xE5,0xC2,0x49, ++0x26,0x37,0x4C,0x4E,0xAD,0xB4,0x9E,0x4B, ++0x23,0x17,0x1A,0x4B,0xA8,0xD8,0x0B,0x4F, ++0xD8,0xA8,0x61,0x93,0xA9,0x94,0xFF,0x4F, ++0x26,0x47,0x13,0x4B,0xAD,0xB4,0xDD,0x4C, ++0x22,0x36,0x48,0x4C,0xAD,0xB4,0x9E,0x4B, ++0x23,0x17,0x1A,0x4B,0xAD,0xD4,0x0B,0x4F, ++0xDB,0xA8,0x61,0x93,0xA9,0xE4,0xD2,0x49, ++0x27,0x67,0x3E,0x48,0xAD,0xF4,0xD2,0x4E, ++0x2A,0x47,0x13,0x4B,0x00,0x2B,0xA0,0x47, ++0x60,0x88,0x13,0x4B,0xD9,0x54,0xE2,0x44, ++0x51,0x3F,0xFF,0x89,0x9B,0xE1,0x69,0x8C, ++0x4B,0x39,0xBE,0xED,0xC8,0xA0,0x3E,0x91, ++0x12,0x2F,0xBB,0xD1,0x85,0xF4,0x13,0xC9, ++0x4C,0x6A,0xAE,0xD1,0x8C,0xAC,0x73,0x8C, ++0xEC,0x94,0x53,0x66,0x70,0x0A,0xC8,0x36, ++0xF0,0xD8,0x4C,0x09,0x03,0x7E,0xF5,0x06, ++0xFB,0x95,0x55,0x23,0x31,0x4B,0xC3,0x26, ++0xE7,0x88,0x40,0x23,0x2F,0x5E,0x87,0x63, ++0xFC,0xC0,0x04,0x7B,0x26,0x06,0xFF,0x26, ++0xCC,0x9C,0x40,0x62,0x3E,0x4E,0x8D,0x23, ++0xF0,0xD1,0x14,0x4F,0x66,0x10,0xC8,0x36, ++0xF0,0xD8,0x4C,0x2F,0x23,0x1A,0x9C,0x61, ++0xED,0x8E,0x40,0x3E,0x33,0x06,0xD0,0x7E, ++0x82,0xFD,0x34,0x03,0x51,0x2D,0xB4,0x26, ++0xE1,0x93,0x3E,0x03,0x51,0x2D,0xB4,0x26, ++0xE7,0x88,0x40,0x09,0x03,0x7E,0xF5,0x06, ++0xFB,0x94,0x53,0x6D,0x62,0x0A,0x80,0x74, ++0xED,0xA6,0x11,0x67,0x5E,0x43,0xD0,0x36, ++0xBA,0xA5,0x14,0x22,0x3E,0x5E,0x91,0x6F, ++0xEF,0x98,0x47,0x77,0x58,0x5B,0x91,0x5B, ++0x3D,0x50,0x8C,0xB9,0xD3,0xD6,0x77,0x8E, ++0x70,0x14,0xCF,0xF8,0xA6,0xD3,0x19,0x84, ++0x00,0x75,0xBC,0x8B,0xFB,0xB6,0x50,0x67, ++0x21,0x4D,0x1C,0x6A,0xFA,0xA6,0x82,0x68, ++0x72,0x65,0x43,0x6D,0xA9,0xBE,0xDD,0x6F, ++0x95,0x74,0xBA,0x6B,0x1E,0xF2,0x78,0x6E, ++0x93,0x74,0xBE,0x6B,0x8B,0x96,0xFD,0x6B, ++0x02,0x65,0x39,0x6B,0x89,0xF6,0x2C,0x6F, ++0x00,0x55,0x1C,0xA8,0x8A,0xD6,0xDD,0xBD, ++0x02,0x5D,0x1C,0x6A,0xAA,0xDE,0xFF,0x6E, ++0x01,0x6D,0x1C,0x6A,0x8A,0xA6,0xFB,0x6E, ++0x01,0x75,0xE9,0x6A,0x8B,0xA6,0xFD,0x6B, ++0x01,0x55,0x3E,0xB9,0x18,0xD2,0x5C,0x6E, ++0x04,0x65,0x3C,0x6E,0x8B,0xF6,0xDD,0x6D, ++0x70,0xF5,0x01,0x63,0x74,0xB9,0x50,0x67, ++0x02,0x74,0xAF,0x68,0x9F,0x26,0x30,0x6C, ++0x00,0xF5,0x1C,0x6A,0x8B,0x56,0xDD,0x6D, ++0x03,0x15,0x1C,0x6A,0x93,0xF6,0xE0,0x8B, ++0x00,0xD5,0x3C,0x8E,0x8B,0xF6,0x9D,0x8D, ++0x00,0xD5,0x34,0x8E,0xF2,0xF6,0x7D,0x84, ++0x00,0x75,0x2E,0x6E,0xAD,0xAE,0xDD,0x6F, ++0x76,0x05,0x43,0x6D,0xFB,0x66,0x82,0x68, ++0x20,0xCD,0x1C,0x6A,0x8F,0xF6,0xEF,0x6B, ++0x0C,0xD5,0x31,0x6E,0xFB,0xE6,0x82,0x68, ++0x20,0x7D,0x1C,0x6A,0x8E,0xF6,0x2D,0x6F, ++0x00,0x35,0x1C,0xB8,0x8A,0xB6,0xDD,0xAD, ++0x00,0x75,0xE8,0x68,0x8E,0xF6,0x3D,0x9E, ++0x00,0x7D,0x3D,0x9A,0x8B,0xF6,0x2A,0x9F, ++0x04,0x75,0x2E,0x6E,0x8A,0xB6,0x39,0x0C, ++0x00,0x75,0xE8,0x68,0x83,0xF6,0xF0,0x6B, ++0x0B,0x75,0xBC,0x81,0x8C,0xC6,0xDD,0x6F, ++0x05,0x55,0x1C,0x6A,0x8F,0xE6,0xDD,0x6F, ++0xE6,0x9B,0xDF,0x87,0xAD,0x1A,0x93,0x8B, ++0xE2,0x9B,0xCF,0x80,0x45,0x10,0x23,0x81, ++0xE6,0x9B,0xCF,0x70,0x64,0x58,0xD7,0x72, ++0xE2,0x3B,0xDF,0x70,0x63,0x18,0x13,0x70, ++0xE6,0x9B,0xDF,0x70,0x60,0x08,0x33,0x81, ++0xE6,0x9B,0xCF,0x80,0x61,0x58,0x1E,0x85, ++0xFE,0x9B,0xDF,0x80,0x5F,0x11,0x93,0x8B, ++0x7E,0x9E,0x53,0x85,0x65,0x58,0x33,0x81, ++0xFE,0x9B,0xCF,0x80,0x64,0x10,0xC7,0x83, ++0xEF,0x8B,0x12,0x85,0x64,0x30,0x18,0x81, ++0xEC,0x9B,0x52,0x6F,0xF1,0x1F,0x93,0x80, ++0xEC,0x9B,0x02,0x84,0x62,0x18,0x93,0xFA, ++0xEB,0x9B,0xD3,0x85,0x64,0x10,0xC3,0x83, ++0xEF,0xDB,0x16,0x87,0x65,0x00,0x18,0x81, ++0xEC,0x9B,0x52,0x4F,0xF1,0x1F,0x93,0x80, ++0xEF,0x9B,0x02,0x84,0x64,0x58,0xD7,0xE2, ++0xB3,0xCE,0x9A,0xD5,0x37,0x7D,0x66,0xD4, ++0xBE,0xEE,0xA7,0xD1,0x34,0x5D,0x66,0xD4, ++0x9B,0xC6,0xA7,0xD1,0x3C,0x4D,0x4B,0xD0, ++0xB3,0xCE,0x9A,0xD5,0x30,0x45,0x4D,0xD4, ++0xB3,0xCE,0x8A,0xD5,0x38,0x4D,0x4B,0xD7, ++0x24,0xCC,0x07,0xDB,0x3C,0x4D,0x5B,0xD0, ++0xBE,0xDE,0xA7,0xD1,0x10,0x45,0x76,0xD4, ++0xB3,0xCE,0x9A,0x25,0x31,0x0D,0x82,0x27, ++0xB7,0x6E,0x8A,0x25,0x36,0x4D,0x46,0x25, ++0xB3,0xCE,0x8A,0x25,0x34,0x45,0x66,0xD4, ++0xBB,0xCE,0x8F,0xD5,0x38,0xFD,0x5B,0xD0, ++0xB0,0xCE,0xA7,0xD1,0x20,0x44,0xC6,0xDE, ++0x2B,0x7B,0x66,0xD0,0x31,0x45,0x96,0xD6, ++0xBB,0x8E,0xA7,0xD1,0x31,0x65,0x4F,0xD4, ++0xB9,0xCE,0x07,0x3A,0xA4,0x4A,0xC6,0xD5, ++0xB9,0xCE,0x57,0xD1,0x37,0x4D,0xC6,0xAF, ++0xC9,0xB9,0xF1,0xA7,0x46,0x32,0xE1,0xA1, ++0xCD,0xF9,0x34,0xA5,0x47,0x22,0x38,0xA3, ++0xCE,0xB9,0x70,0x6D,0xD3,0x3D,0xB1,0xA2, ++0xCD,0xB9,0x20,0xA6,0x46,0x7A,0xF5,0xC0, ++0xC4,0xB9,0xED,0xA2,0x40,0x0A,0x11,0xA3, ++0xC9,0x99,0xD0,0xA6,0x43,0x2A,0x11,0xA3, ++0xEC,0xB1,0xD0,0xA6,0x4B,0x3A,0x3C,0xA7, ++0xC4,0xB9,0xED,0xA2,0x47,0x32,0x38,0xA3, ++0xC4,0xB9,0xFD,0xA2,0x4F,0x3A,0x3C,0xA0, ++0xBB,0xBB,0x70,0xAC,0x4B,0x3A,0x2C,0xA7, ++0xEC,0xB1,0xC0,0xA6,0x4F,0x3A,0x2C,0x57, ++0xCD,0xF9,0x34,0x55,0x4B,0x9A,0x3C,0x57, ++0xCA,0xB9,0xF0,0x57,0x4F,0x3A,0x3C,0x57, ++0xCC,0xB9,0xE8,0xA2,0x33,0x2A,0x4E,0xA4, ++0xCD,0xB9,0xF0,0xA6,0x47,0x3A,0x39,0xA7, ++0xD4,0xB9,0xED,0xA2,0x4F,0x2A,0x2C,0xA7, ++0x33,0x56,0x0F,0x5D,0xBC,0xC5,0xD3,0x58, ++0x17,0x96,0x02,0x5A,0x48,0x4A,0xF3,0x55, ++0xC3,0x06,0xA2,0x51,0x98,0xC5,0x1C,0x5E, ++0x33,0x06,0x6F,0x0B,0xB8,0x95,0xEE,0x0E, ++0x13,0xA6,0xED,0x0A,0x8C,0x07,0xAE,0x0C, ++0x36,0x06,0x2F,0x09,0xA6,0xC5,0x4E,0x07, ++0xF1,0x09,0x2F,0x59,0xB8,0xA5,0xEE,0x5E, ++0x97,0x3B,0x0D,0x58,0xBB,0x85,0xEE,0x5C, ++0xF4,0x14,0x2F,0x59,0xBC,0xC5,0x4E,0x57, ++0x36,0x46,0xDB,0x59,0xBD,0x05,0x0A,0x1D, ++0x37,0x27,0x0F,0x0F,0xB4,0x04,0xDF,0x1A, ++0x37,0x87,0x0F,0x1F,0xB9,0x85,0x1A,0x5F, ++0xCB,0xB9,0x70,0x92,0xA7,0x85,0x89,0x5E, ++0x37,0x66,0xDD,0x58,0xBD,0x85,0x0D,0x5D, ++0x37,0x57,0x1E,0x5F,0xA9,0x87,0xEE,0x5C, ++0x31,0x46,0x8F,0xB2,0xB8,0xD5,0xEE,0x5C, ++0x48,0x20,0xE9,0xCA,0x21,0x1C,0x53,0xC5, ++0xAE,0xDF,0xB6,0xC0,0xD1,0xDC,0x6A,0xCC, ++0xAE,0xBE,0x87,0xC6,0x2D,0x2C,0xD1,0xC4, ++0xBC,0x8D,0x93,0xC0,0x16,0x22,0x77,0xC5, ++0xAE,0x8E,0x96,0xC6,0x26,0x0C,0x77,0xC5, ++0xAB,0x9F,0x92,0xC3,0x22,0x5C,0x83,0xC5, ++0x5C,0x20,0xE9,0x9B,0x24,0x5C,0x77,0xC5, ++0x5A,0x5F,0xAB,0xC9,0xD1,0x1C,0xFA,0xCD, ++0x8A,0xDF,0x44,0xC2,0x21,0x1C,0x37,0x97, ++0x8A,0xAF,0x74,0x93,0x35,0x9E,0x37,0x95, ++0xAA,0x9F,0xB6,0x92,0x3F,0x5C,0xD7,0x9E, ++0x68,0x90,0xB6,0xC0,0x85,0x91,0x55,0xC4, ++0xAA,0x9F,0xB6,0xC2,0x25,0x2C,0x77,0xC5, ++0x66,0xBD,0xB6,0xC0,0x24,0x5C,0xD7,0xCE, ++0xAC,0x8F,0x92,0xC1,0x22,0x5C,0x82,0xC5, ++0xAF,0x8E,0x87,0x96,0x25,0x2D,0x57,0x83, ++0xAE,0x8E,0x96,0x96,0x20,0x1C,0x53,0xC6, ++0xA9,0xDF,0x42,0xC0,0xD6,0xA3,0x28,0x9E, ++0xAC,0xCE,0x97,0xC1,0x3E,0x1C,0x1B,0xC7, ++0xAE,0xCF,0x07,0xC4,0x25,0x7C,0x85,0xC4, ++0x9B,0x9D,0xB6,0xC0,0x2D,0x5C,0xD7,0x2E, ++0xAA,0xCF,0xB6,0xC0,0xC3,0xA3,0x28,0xCF, ++0xAA,0x9F,0x92,0xC0,0x29,0x5C,0xD7,0xCE, ++0xA9,0x8E,0x87,0xC6,0x2D,0x3C,0xD2,0xC4, ++0x9F,0x8D,0xB6,0xC0,0x37,0x3B,0x77,0xC5, ++0xAF,0x9F,0x92,0xC0,0x22,0x1D,0x57,0xC3, ++0xAC,0x9F,0xB6,0xC0,0x20,0x6C,0x84,0xC6, ++0x5C,0x20,0xE9,0x0B,0x25,0x5C,0x77,0xC5, ++0x5A,0x5F,0xAB,0xC9,0xDE,0x13,0xFA,0xCD, ++0xAA,0x7F,0xB6,0xC0,0x15,0x8C,0x9A,0xC6, ++0xA8,0xAF,0xB6,0xC0,0x22,0x1C,0x77,0xC5, ++0xA9,0xCF,0xB6,0xC0,0x4D,0x0C,0x4A,0xC1, ++0xE0,0x6D,0xA9,0xE6,0x24,0x7C,0xF5,0xED, ++0xB0,0xFD,0xA9,0xE6,0x07,0x6E,0x55,0xE7, ++0xAC,0xFF,0x34,0xE8,0x06,0x6E,0x55,0xE7, ++0x81,0xFD,0x94,0xE2,0x13,0x7C,0xF5,0xED, ++0x88,0x9D,0x94,0xE2,0x07,0x6E,0x55,0xE7, ++0x8F,0xFD,0x94,0xE2,0x0F,0x7C,0xF5,0xED, ++0x88,0xFD,0x62,0xE0,0x05,0x7E,0xB5,0xE6, ++0xA0,0xFD,0xB9,0xE6,0x03,0x7E,0x15,0x05, ++0x7D,0xFD,0x34,0x09,0x02,0x7E,0xA3,0xE5, ++0xAE,0xFD,0x34,0x19,0x03,0x6E,0x6C,0xE3, ++0x88,0xFD,0x60,0xE0,0x03,0x7E,0xA4,0x15, ++0x88,0xFD,0x94,0x00,0x1D,0x7E,0xF5,0x0C, ++0x8A,0xFC,0x94,0xE0,0x03,0x2E,0x55,0xE5, ++0x88,0xFD,0x25,0xE2,0x00,0x7E,0xF5,0x1C, ++0x89,0xAD,0xB1,0xE1,0x23,0x7E,0xA0,0xE5, ++0x28,0xFD,0x94,0xE2,0xFA,0x81,0x0A,0xBC, ++0x33,0x32,0x3E,0x48,0xAD,0xE4,0xFF,0x4D, ++0x27,0x77,0x3E,0x48,0xAE,0xC4,0xFF,0x4D, ++0x28,0x57,0x3E,0x48,0xD4,0x2B,0xA0,0x47, ++0x28,0x27,0x3E,0x48,0xA1,0xD4,0xD2,0x49, ++0x2A,0x57,0x9E,0x43,0xA1,0xD4,0xC2,0x49, ++0x24,0x67,0x3E,0x48,0xA5,0xF4,0xD2,0x4E, ++0x2A,0x47,0x13,0x4B,0xB9,0xD4,0xD2,0x49, ++0x26,0x56,0x09,0x4E,0xA5,0xD4,0xD2,0x49, ++0x26,0x56,0x14,0x49,0x43,0x2A,0xA0,0x47, ++0x23,0x17,0xCA,0x4B,0x5D,0x2B,0xA0,0x86, ++0x2A,0x57,0x03,0x4C,0x99,0xD1,0xFF,0x4D, ++0x2A,0x57,0x13,0x4C,0x91,0xC4,0xC2,0x49, ++0x22,0x57,0x1F,0x4C,0x62,0xD4,0x5F,0x46, ++0x22,0x57,0xCE,0x4A,0xAD,0xD4,0x5F,0x06, ++0x1A,0x57,0x03,0x4C,0xAD,0xF4,0xFF,0x4D, ++0x25,0x47,0x3E,0x48,0x48,0xD5,0x5F,0x47, ++0x3B,0x8A,0x43,0x9E,0x63,0x09,0x82,0x6B, ++0xF9,0x8A,0xE3,0x95,0x72,0x09,0x82,0x9B, ++0xFF,0x9B,0xD4,0x93,0x74,0x28,0x1B,0x96, ++0xFD,0x8A,0x12,0x95,0x75,0x09,0x22,0xF2, ++0xFB,0x8A,0x43,0xFE,0x74,0x09,0x62,0x42, ++0xFD,0x8A,0x43,0x4E,0x75,0x09,0xD2,0x93, ++0x09,0x75,0xBC,0x5E,0x74,0x09,0x22,0x92, ++0xFF,0x8A,0x13,0x97,0x9F,0xF6,0x7D,0xCB, ++0xF7,0x8A,0x43,0x6E,0x75,0x09,0x22,0x92, ++0xFF,0x9A,0xE3,0x97,0x70,0x09,0xD2,0x90, ++0xFF,0x9B,0xC9,0xC3,0x75,0x09,0x02,0xC3, ++0x04,0x75,0xBC,0xCE,0x75,0x09,0x22,0x92, ++0xFF,0x8A,0xC9,0x91,0xDF,0x09,0x82,0x9B, ++0xFF,0x9A,0xE3,0x97,0x72,0x88,0x0B,0x91, ++0xD3,0x9A,0xCE,0x91,0x76,0x08,0x22,0x92, ++0xFB,0x9A,0x5B,0x91,0x74,0x09,0x93,0x90, ++0x9C,0xEC,0x25,0x08,0x3E,0x4F,0x79,0xF2, ++0x39,0xEC,0x85,0xF3,0x13,0x4F,0x66,0xF5, ++0xB9,0xEC,0x77,0xF1,0x3E,0x4F,0x69,0xF2, ++0x6E,0x13,0xDA,0xA8,0x3E,0x4F,0x79,0xF2, ++0x9F,0xDC,0x85,0xF3,0x1B,0x7F,0x44,0xF6, ++0x90,0xEC,0x85,0xF3,0x25,0x90,0x1B,0xFC, ++0xB1,0xEC,0xB8,0xF7,0x15,0x7F,0x44,0xF6, ++0xB5,0xCC,0xB8,0xF7,0x12,0x5F,0x62,0xF7, ++0xA1,0xEC,0xB8,0xF7,0x23,0x90,0x1B,0xFC, ++0xA1,0xFC,0xB8,0xF7,0x0A,0x6F,0x69,0xF2, ++0x8D,0xFC,0xA8,0xF7,0x3A,0x1F,0x79,0xF2, ++0x99,0xEC,0x72,0xF1,0x68,0x6F,0xE4,0xAD, ++0x8D,0xFC,0xB8,0xF7,0x0E,0x6F,0x69,0xF2, ++0x9F,0xEC,0xA2,0xF2,0x12,0x2F,0x44,0xF4, ++0x81,0xCC,0xA8,0xF0,0x12,0x6E,0x65,0xF7, ++0xB9,0xFC,0xA8,0xF0,0x22,0x6F,0x69,0xF2, ++0xD9,0xA8,0x71,0xB3,0x4E,0x2B,0x2D,0xB6, ++0xF9,0xA8,0xEC,0xB4,0x52,0x1B,0xB8,0xB6, ++0x4A,0x56,0x9E,0xBD,0x56,0x2B,0xF0,0xB0, ++0xD7,0xA8,0x61,0x5C,0x56,0x2B,0x40,0xB0, ++0xF9,0xA8,0xEC,0xB3,0x66,0x2B,0x3D,0xB6, ++0xD9,0xA8,0x71,0xB3,0x76,0x2B,0x2D,0xB6, ++0xD9,0xB8,0x79,0xB3,0x57,0x2B,0x20,0xB3, ++0xFD,0xA8,0xEC,0xB3,0x52,0x3B,0xB8,0xB6, ++0xDD,0xA8,0x30,0xB7,0x57,0x6B,0x00,0xD0, ++0xF9,0xA8,0xFC,0xB3,0x56,0x2B,0xF0,0xB0, ++0xC6,0xA8,0x61,0x5C,0x56,0x2B,0xF4,0xB0, ++0xC4,0xA8,0x61,0x4C,0x66,0x3B,0x3D,0xB6, ++0xD5,0x88,0x79,0xB3,0x5E,0x1B,0xB1,0xB6, ++0xFD,0xB8,0xFC,0xB3,0x9C,0x2A,0xA0,0xB8, ++0xDD,0xA8,0x31,0xB5,0x44,0x2B,0xA0,0x59, ++0xF9,0xA8,0xFC,0xB3,0x76,0x3B,0x3D,0xB6, ++0x10,0x64,0xED,0x78,0xBE,0xE7,0xE1,0x7A, ++0x15,0x64,0xB5,0x7F,0x9A,0xF7,0xED,0x7F, ++0x31,0x74,0x20,0x7F,0x9E,0xE7,0x74,0x7A, ++0x10,0x64,0xFD,0x7B,0x92,0xE7,0x6C,0x15, ++0x21,0x64,0x30,0x7F,0x92,0xC7,0x74,0x7A, ++0x19,0x54,0xBD,0x7F,0xBE,0xE7,0xF1,0x7A, ++0xA8,0x65,0xAD,0x71,0x9A,0xE7,0x3C,0x7C, ++0x35,0x64,0x30,0x8F,0x9B,0xE7,0x2C,0x8D, ++0x35,0x64,0x20,0x8F,0x8E,0xE7,0xF1,0x7A, ++0x16,0x35,0x2D,0x7A,0x86,0xE7,0xF1,0x7A, ++0x1D,0x64,0x20,0x7F,0xBE,0xE7,0xF1,0x7A, ++0x11,0x64,0xFD,0x79,0x8A,0xE7,0xE1,0x7A, ++0x1D,0x64,0x30,0x9F,0x81,0xE7,0x6C,0x95, ++0x11,0xD4,0x0D,0x79,0x91,0xA7,0xCC,0x7E, ++0x05,0x64,0xAD,0x70,0x9E,0xC6,0xF5,0x78, ++0x15,0x64,0x20,0x78,0x8A,0xF7,0xF1,0x7A, ++0xF8,0x30,0xF8,0xDB,0x34,0x4C,0x53,0xD2, ++0xB0,0xDE,0x47,0xD0,0x3B,0x4D,0x26,0xD4, ++0xBF,0xDF,0x82,0xD7,0x30,0x4D,0x97,0xD4, ++0xBF,0xEE,0x9A,0xD5,0x30,0x4D,0x66,0xA6, ++0xBA,0xCE,0xA7,0xB3,0x32,0x5D,0x87,0xD5, ++0xBF,0xDF,0x82,0xD7,0x31,0x0D,0x42,0xD7, ++0xBF,0xEE,0x9A,0xD5,0x32,0x6D,0x26,0xD4, ++0xB9,0xCE,0x56,0xD1,0x38,0x5D,0x5B,0xD0, ++0xBA,0xCE,0x87,0xB2,0x30,0xFD,0x47,0xD5, ++0xBD,0xCE,0x53,0xD1,0xD8,0xB2,0x39,0x8F, ++0xB7,0xCE,0x9A,0xD5,0x3B,0x4D,0x86,0xD5, ++0x9F,0xDE,0x9A,0xD5,0x30,0x4D,0x96,0xD6, ++0xBC,0xDF,0x8D,0xD7,0x23,0x4D,0xC6,0x3F, ++0xBA,0xCE,0x46,0xD2,0x30,0x5D,0x66,0xD6, ++0xBC,0xCF,0x8D,0xD7,0x31,0x4D,0x66,0xD4, ++0xB7,0xCE,0x07,0xDA,0x30,0x6C,0x53,0xD2, ++0x89,0xDD,0xB6,0xE3,0x03,0x5F,0x70,0xE1, ++0x89,0xFD,0x66,0xE2,0x03,0x4F,0x6C,0xE1, ++0x88,0xED,0x94,0x20,0x02,0x6E,0x55,0x35, ++0x8B,0xDD,0xB6,0xE3,0x03,0x5F,0x70,0xE1, ++0x88,0xCC,0xAD,0xE4,0x02,0x7E,0x75,0xE4, ++0x8B,0xFD,0x66,0xE2,0x02,0x6E,0x74,0x34, ++0x8E,0xFD,0x64,0xE2,0xF3,0x81,0x0A,0xBC, ++0xB8,0xFD,0xA9,0xE6,0x02,0x0E,0xA2,0xE4, ++0x8C,0xFD,0x24,0xE6,0x1B,0x7E,0x78,0xE3, ++0x0C,0x02,0xCB,0x59,0x2B,0x6E,0x68,0xE3, ++0x8E,0xFD,0x94,0xE2,0x03,0x4E,0x55,0xE5, ++0x8E,0xED,0xB5,0xE3,0x03,0x7E,0xA4,0xE7, ++0x9C,0xDD,0xA9,0xC6,0x03,0x4F,0x77,0xC1, ++0x89,0xFD,0xB4,0xC1,0xF9,0x81,0x0A,0xCC, ++0xB0,0xED,0xA9,0xE6,0x2F,0x5E,0x68,0xE3, ++0x8E,0xCD,0x94,0xE2,0x02,0x7E,0x55,0xE7, ++0x54,0x12,0xDA,0xF9,0x3E,0x4F,0x79,0xF2, ++0x9F,0xDC,0x85,0xF3,0x1B,0x7F,0x44,0xF6, ++0x90,0xEC,0x85,0xF3,0xDA,0x91,0x1B,0xFC, ++0x99,0xEC,0x85,0xF1,0x56,0xBF,0x69,0xF5, ++0x69,0x63,0x98,0xFA,0xE5,0x20,0xC9,0xFE, ++0x99,0x8C,0x85,0xF3,0x12,0x6F,0x44,0xF4, ++0x91,0x3C,0x68,0xF0,0x10,0xCF,0x44,0xF6, ++0x1B,0xFC,0x85,0xF3,0x12,0x4F,0x44,0xF6, ++0x98,0xEC,0x75,0xF3,0x12,0x4E,0x62,0xA0, ++0x98,0xEC,0xA5,0xA0,0xE9,0x90,0x1B,0xAD, ++0x99,0xAC,0x85,0xF1,0x13,0xDF,0xA5,0xF5, ++0x9D,0xBC,0x85,0xF3,0x4E,0x6F,0xE4,0xFD, ++0x95,0xEC,0xB8,0xF7,0x97,0x1F,0x44,0xF6, ++0x9C,0xFD,0xB5,0xF5,0x1F,0x6F,0x44,0xF6, ++0x98,0xCC,0x85,0xF3,0xF4,0x92,0x1B,0xFC, ++0x99,0xEC,0xB8,0xF7,0x12,0xEF,0x44,0xF4, ++0x07,0x64,0x2A,0x6C,0x8A,0xF6,0xFD,0x6E, ++0x00,0x75,0x31,0x6E,0x8C,0xE7,0xEB,0x69, ++0x01,0x75,0xEC,0x6A,0x8F,0xF6,0xE0,0xBB, ++0x01,0x75,0x3C,0xB9,0x8F,0xF6,0xF0,0xBB, ++0x0B,0x75,0xEB,0x6A,0x8C,0xF6,0x7D,0x94, ++0x00,0x75,0xE8,0x68,0x8E,0xF6,0x7D,0x84, ++0x04,0x75,0x21,0x6E,0x8F,0xF6,0xFD,0x6E, ++0x04,0x75,0xEC,0x6A,0x8B,0xB6,0xDD,0x6D, ++0x01,0xF5,0x1C,0xB8,0x8F,0xF6,0xF0,0x6B, ++0x00,0x75,0x21,0x6E,0x8C,0xF7,0xFB,0x69, ++0x01,0x05,0x39,0x69,0x8F,0x66,0xE0,0x6B, ++0x37,0x75,0xBC,0x61,0x87,0xF6,0xE0,0x6B, ++0x05,0x54,0x2C,0x6C,0x8C,0xE7,0xED,0x69, ++0x0D,0x75,0x1C,0x6A,0x43,0x0B,0x82,0x65, ++0x00,0x55,0x21,0x6E,0x8B,0xF6,0xE0,0x6B, ++0x82,0x55,0x1C,0x6A,0x8B,0xD6,0xF0,0x6B, ++0xC6,0x0C,0x7A,0x0C,0xE9,0xB0,0x86,0x0D, ++0x62,0x13,0x47,0x08,0x6F,0x80,0x9A,0x09, ++0x62,0x03,0x57,0x08,0x4D,0x9F,0xBB,0x09, ++0x66,0x03,0x47,0x08,0xE4,0x80,0x9A,0x08, ++0x6F,0x13,0x8B,0x0C,0xED,0x80,0x96,0x0D, ++0x65,0x13,0xDA,0xC7,0xE9,0x80,0x86,0x0D, ++0x67,0x03,0x4B,0x0F,0xEC,0x90,0x9B,0xEA, ++0x62,0x03,0x57,0x08,0xE9,0x80,0x86,0x0D, ++0x66,0x33,0x47,0x08,0xE5,0x80,0x9A,0x08, ++0x6E,0x13,0x8B,0x0C,0xE9,0x80,0x96,0x0D, ++0x61,0x03,0x5F,0x0D,0xEC,0x90,0x9B,0xDA, ++0x67,0x22,0x4C,0x0A,0xEE,0xB0,0x99,0x08, ++0x66,0x33,0x57,0x08,0xEC,0xA1,0x8D,0x0F, ++0x65,0x13,0x88,0x0C,0xEE,0x90,0x1B,0xC2, ++0x62,0x33,0x47,0x08,0xEC,0xB0,0x89,0x0A, ++0x67,0x13,0x5A,0xEF,0xE9,0xB0,0x96,0x0D, ++0xF4,0x8A,0x12,0x95,0x73,0x09,0x82,0x6B, ++0xFF,0x8A,0x17,0x97,0x71,0x09,0x82,0x7B, ++0xFB,0xAA,0xDE,0x91,0x70,0x29,0x00,0x91, ++0xFB,0x8A,0x11,0x95,0x74,0x49,0x22,0x92, ++0xFE,0x8A,0xC3,0x46,0x70,0x29,0x0F,0x94, ++0xFF,0xAA,0xDE,0x91,0x74,0x89,0x22,0x90, ++0xFE,0xFA,0xC4,0x96,0x75,0x28,0x04,0x96, ++0xFB,0x1A,0xDE,0x91,0x7E,0x09,0xD5,0x90, ++0x3A,0x75,0xBC,0xCE,0x7E,0xB9,0x07,0x91, ++0xF7,0xCA,0xE3,0x95,0x75,0x59,0x07,0x93, ++0xF4,0x1B,0xC5,0x93,0x7E,0x09,0xD7,0x90, ++0x5F,0x75,0xBC,0xCE,0x60,0xD9,0x0F,0x93, ++0xFF,0x8A,0xE3,0x97,0x84,0x86,0x3F,0x99, ++0x01,0xC5,0x6E,0x9D,0x74,0x99,0x22,0x90, ++0xFE,0x2A,0xE3,0x95,0x76,0x69,0x22,0x90, ++0xCF,0xFA,0xDE,0x91,0x77,0x49,0x22,0x90, ++0x44,0x31,0xAF,0x2C,0xCF,0xB2,0xD9,0xC9, ++0x17,0x31,0xF8,0xC5,0xB7,0xB6,0xA6,0x2F, ++0xC3,0xB1,0x58,0x2E,0xC7,0xA2,0x99,0x2B, ++0xE6,0x31,0xF8,0x24,0xA3,0xB6,0xA6,0x2F, ++0x4C,0x21,0x58,0x2E,0x50,0xB2,0x39,0x21, ++0x20,0x35,0x67,0x2A,0xC7,0xA2,0x99,0x2B, ++0xD8,0x31,0xF8,0x24,0x93,0xB6,0xA6,0x2F, ++0x43,0x21,0x58,0x2E,0x56,0xB2,0x39,0x21, ++0x10,0x35,0x67,0x2A,0xC8,0xA2,0x99,0x2B, ++0xD2,0x31,0xF8,0x24,0x8B,0xB6,0xA6,0x2F, ++0x43,0x11,0x58,0x2E,0xCB,0xA2,0x99,0x2B, ++0xCE,0x31,0xF8,0x24,0xC8,0xA2,0x99,0x2B, ++0x42,0x31,0x58,0x2E,0xB1,0xB2,0x39,0x21, ++0x44,0x71,0x58,0x2E,0xCD,0xB3,0x99,0x29, ++0x40,0x20,0x7E,0x2F,0xCB,0xA2,0x28,0x2F, ++0x44,0x31,0xE9,0x2E,0xCD,0xB2,0x39,0xD0, ++0xD7,0x02,0x7B,0x1D,0x07,0x7E,0xF5,0xE3, ++0x74,0x02,0xCB,0x16,0xFD,0x81,0x5A,0x1A, ++0x75,0x53,0x6B,0xFF,0xFD,0xC1,0x4E,0xFB, ++0x77,0x02,0xCB,0xF6,0x5C,0xD1,0xAA,0x18, ++0x83,0x01,0x54,0x19,0xFB,0xA1,0xAA,0x18, ++0x7D,0x12,0x6B,0x1D,0x89,0x81,0x0A,0x12, ++0x55,0x02,0xCB,0x16,0x1C,0x92,0x95,0x1C, ++0x70,0x22,0x6B,0x1D,0xFB,0x8A,0x4B,0x1B, ++0x20,0xFD,0x34,0x17,0x34,0xB2,0x95,0x1C, ++0x75,0x29,0x88,0x1E,0x08,0xA1,0xC7,0x18, ++0x75,0x39,0x48,0x1E,0xFC,0xF1,0x87,0x1C, ++0x7F,0x22,0x6B,0x1D,0xFA,0x9A,0x49,0x1B, ++0x76,0x09,0x48,0x1E,0x47,0x81,0x0A,0x12, ++0x73,0x03,0x4D,0x1C,0xF8,0x81,0x1A,0x1C, ++0x72,0x02,0xDB,0x1D,0xF1,0x81,0x0A,0xF3, ++0x70,0x32,0x6B,0x1D,0x64,0x92,0x95,0x1C, ++0x28,0x77,0x3E,0x48,0xAE,0xDF,0x1E,0x4E, ++0x4E,0x57,0x9E,0x42,0x29,0xE7,0xC0,0x49, ++0x20,0x7C,0xDD,0x4B,0x5D,0xF4,0x92,0x4D, ++0x20,0x6C,0x1D,0x4B,0xA9,0xA4,0xD2,0x49, ++0x2A,0x77,0x3E,0x48,0xAF,0xCF,0x1C,0x4E, ++0x23,0x5C,0x1D,0x4B,0x00,0xD4,0x5F,0x47, ++0x23,0x57,0xCB,0x4A,0x0C,0x84,0xFF,0xBD, ++0x20,0x06,0x3E,0xAA,0xA8,0x94,0x1B,0xAE, ++0x22,0x57,0xCA,0x4A,0x73,0x2B,0xA0,0xB6, ++0x25,0x77,0x3E,0x48,0xE1,0xC7,0xC0,0x49, ++0x2B,0x57,0x3E,0x48,0xE2,0xD4,0x5F,0x47, ++0x22,0x57,0x3E,0x4A,0x57,0x5B,0xE2,0x44, ++0xD2,0x08,0xB3,0x40,0xA9,0x74,0xFF,0x4D, ++0x63,0x8A,0xD3,0x4B,0xA8,0x64,0xFF,0x4D, ++0x13,0x1A,0x13,0x4B,0xAB,0x54,0xFF,0x4D, ++0x21,0xC7,0x3E,0x48,0xA8,0xC8,0xFF,0x4F, ++0xEA,0x9B,0xF2,0x84,0x22,0x18,0x93,0x8B, ++0xCF,0xC6,0xDF,0x87,0x64,0x04,0x33,0x83, ++0xEB,0x9B,0xF2,0x84,0x26,0x18,0x93,0x8B, ++0xFF,0xF6,0xDF,0x87,0x64,0x04,0x33,0x83, ++0xE8,0x9B,0xF2,0x84,0x5A,0x18,0x93,0x8B, ++0xAE,0xEB,0xDF,0x87,0x64,0x04,0x33,0x83, ++0xE9,0x9B,0xF2,0x84,0x5E,0x18,0x93,0x8B, ++0xEF,0xA7,0xF2,0x86,0x6F,0x38,0x33,0x81, ++0xED,0x8B,0xF2,0x84,0x61,0x18,0x33,0x81, ++0x7A,0x9B,0x52,0x8E,0x64,0x24,0x33,0x83, ++0xE5,0xBB,0xF2,0x84,0x66,0x08,0x33,0x81, ++0xEB,0x9B,0xF2,0x84,0xEA,0x18,0x93,0x8B, ++0xEA,0xAB,0xF2,0x86,0x6D,0x38,0x33,0x81, ++0xEF,0x87,0xF2,0x86,0x63,0x18,0x33,0x81, ++0x64,0x9B,0x52,0x8E,0x64,0x24,0x33,0x83, ++0xE8,0xBB,0xF2,0x84,0x65,0x28,0x1E,0x85, ++0x05,0x45,0x1C,0x6A,0x8F,0xE6,0xDD,0x6F, ++0x07,0x75,0x1C,0x6A,0xFE,0x09,0x82,0x65, ++0x01,0x59,0x1C,0x68,0x8C,0xE6,0xDD,0x6F, ++0x09,0x75,0x1C,0x6A,0x49,0xF7,0x7D,0x65, ++0x41,0xA8,0x31,0x69,0x8B,0xF6,0xDD,0x6D, ++0xF0,0xEA,0x01,0x63,0x1A,0xF5,0x7E,0x6E, ++0x91,0x77,0xBD,0x6B,0x8A,0xDE,0xFE,0x6E, ++0x00,0x45,0x2C,0x6E,0x89,0xC6,0x3E,0x6E, ++0x02,0x55,0x5C,0x6A,0x8B,0xC6,0xFD,0x6B, ++0x02,0x75,0xEF,0x6A,0x8F,0xD6,0xED,0x6B, ++0x01,0x55,0xFE,0x09,0xAA,0xEE,0x3F,0x6E, ++0x04,0x55,0x3C,0x0E,0x8F,0xE6,0xFD,0x6B, ++0x1E,0x8A,0x93,0x6A,0x88,0xF6,0x7D,0x64, ++0x01,0x54,0x2C,0x6C,0x8B,0xF6,0x2F,0x6D, ++0x01,0x75,0x3D,0x99,0x95,0x09,0x52,0x9F, ++0x01,0x65,0xED,0x69,0x72,0x09,0x82,0xA4, ++0x66,0x13,0x7A,0x0E,0xF3,0x6F,0x34,0x09, ++0x66,0x23,0x7A,0x0E,0xFD,0xD0,0x36,0x01, ++0x64,0x13,0x89,0x0C,0xEE,0xD1,0x8A,0x5F, ++0x65,0x52,0x5A,0x5A,0xEC,0xA0,0x98,0x5A, ++0x9C,0xEC,0x25,0x57,0xFD,0x10,0xA6,0x00, ++0x66,0x33,0x7A,0x0E,0xEC,0x80,0x5A,0x0A, ++0x67,0x13,0xAB,0x0E,0xEC,0xB1,0x9B,0xFF, ++0x9D,0xEC,0x25,0xF7,0xF3,0x6F,0x34,0x09, ++0x9A,0x4C,0xF7,0x04,0xED,0xF0,0xBB,0x09, ++0x66,0x13,0x7A,0x0E,0xEC,0x30,0xBB,0x09, ++0x64,0x83,0x7A,0x0C,0xEE,0x10,0xBB,0x09, ++0x66,0xA3,0x7A,0x0C,0x65,0x90,0x4B,0x09, ++0x66,0xA2,0x5C,0x5A,0xEC,0x90,0x9B,0x5A, ++0x9D,0xEC,0x25,0x57,0xED,0xD0,0xBB,0x0B, ++0x43,0x13,0xDA,0x07,0xE9,0x91,0x82,0x0F, ++0x66,0x13,0x8A,0x0E,0xED,0xE0,0xBB,0xFB, ++0x70,0x52,0x6B,0xED,0xE7,0x81,0x0A,0xE3, ++0x7F,0x02,0x4F,0x1C,0xFC,0x30,0x8C,0x1E, ++0x6B,0x02,0xCB,0x16,0xF8,0xA0,0x93,0x1E, ++0x7A,0x02,0x6B,0x1D,0xF9,0x90,0x90,0x1E, ++0xCC,0xFE,0x34,0x17,0xFC,0x81,0x97,0x1C, ++0x70,0x02,0x4B,0x1C,0xFB,0x81,0x5A,0x18, ++0x77,0x02,0x46,0x19,0xF8,0x81,0x97,0xCC, ++0x77,0x12,0x56,0x19,0xFD,0x81,0x8A,0xCB, ++0x73,0x02,0x46,0xC9,0xF8,0x81,0x8F,0x19, ++0x76,0x52,0x4E,0x1E,0xFC,0xA0,0x9C,0x1E, ++0x75,0x12,0x4A,0x1C,0xFC,0x91,0x87,0x1C, ++0x77,0x23,0x5D,0x1B,0xFE,0x81,0x5B,0x18, ++0x73,0x12,0x56,0xC9,0xFD,0x91,0x8B,0xCB, ++0x73,0x12,0x46,0xC9,0xFC,0x91,0x97,0x1C, ++0x77,0x13,0x4D,0x1B,0xF8,0xF1,0x97,0x1C, ++0x7F,0x02,0x9E,0x1D,0x18,0x7E,0xF5,0x43, ++0xD5,0xA8,0xE5,0xB6,0x56,0x5A,0x26,0xB4, ++0xDC,0xE8,0xE5,0xB4,0x5E,0x2B,0xF4,0xB2, ++0x0A,0x57,0x9E,0xEC,0x56,0x2B,0x00,0xB0, ++0x21,0x37,0xDC,0xBE,0x2A,0x6B,0x8D,0xBA, ++0xDC,0xE8,0xC1,0xB7,0x56,0x3B,0x00,0xB2, ++0xDE,0xF8,0xC1,0xB7,0x5B,0x2B,0x00,0xB2, ++0x4A,0x54,0x9E,0xBD,0x52,0x2B,0x3D,0xB6, ++0xD9,0xA8,0x31,0xB7,0x55,0x2B,0xA0,0x69, ++0xDD,0xA8,0xFC,0xC3,0x53,0x2B,0xF0,0xC2, ++0xDC,0xA8,0xC1,0xD5,0x56,0x2B,0xA0,0xD9, ++0xDD,0xA8,0xC1,0xB5,0x2A,0xAB,0x1D,0xBB, ++0x21,0xE9,0x4C,0xBF,0x54,0x5B,0x00,0xB2, ++0xDD,0xE8,0xC1,0xB7,0x55,0x0B,0x00,0xB2, ++0xFD,0xF8,0xFC,0xB3,0x51,0x1B,0x00,0xB2, ++0xF9,0xA8,0xFC,0xB3,0x7E,0x4B,0x3D,0xB6, ++0xF9,0xA8,0xEC,0xBE,0x57,0x0B,0x00,0xB2, ++0x53,0x30,0x49,0x3F,0xA8,0x5E,0xD7,0x30, ++0x50,0x00,0x49,0x3F,0xD8,0xB3,0x88,0x3A, ++0x51,0x20,0x49,0x3F,0x45,0x5C,0xD7,0x30, ++0x55,0x20,0x49,0x3D,0x22,0x22,0x95,0x33, ++0xA5,0x61,0xC4,0x37,0xDE,0xF3,0x88,0x3A, ++0x54,0x40,0x49,0x3F,0xDC,0xE3,0x88,0x3A, ++0x56,0x50,0x49,0x3F,0x45,0x5C,0xD7,0x30, ++0x55,0x20,0x49,0x3D,0xDF,0xB3,0x6F,0x39, ++0x59,0x20,0xE9,0x34,0xDE,0x93,0x88,0x38, ++0x56,0x00,0x49,0x3F,0xDD,0xA3,0x28,0x31, ++0x54,0x50,0x3D,0x39,0xDF,0xB3,0x69,0x39, ++0x42,0x12,0x6A,0x3F,0xD6,0x83,0xAA,0x39, ++0x55,0x20,0xB8,0x3D,0xDF,0xA3,0x28,0x61, ++0x75,0x20,0xBB,0x3D,0x29,0x5C,0xD7,0x61, ++0x55,0x11,0x6C,0x39,0xDF,0xA3,0xA8,0x39, ++0x53,0x20,0xB9,0x3F,0x2E,0x22,0x95,0x73, ++0x55,0x20,0xB8,0x3D,0x30,0x5C,0xD7,0x71, ++0xA5,0xA1,0x54,0x36,0xFE,0x2C,0x2A,0xFB, ++0x75,0xB7,0xEB,0xFE,0xFE,0x3C,0x2A,0xFB, ++0x75,0x87,0xEB,0xFE,0xFE,0x08,0x2A,0xFB, ++0x55,0x10,0x49,0x3F,0x21,0xB3,0x29,0x39, ++0x54,0x00,0xAB,0x3C,0xDF,0xA3,0x5A,0x38, ++0x54,0x30,0x2A,0xCA,0x25,0x5C,0xD7,0xC1, ++0x4B,0xDF,0xC6,0x3F,0x06,0xA2,0xB7,0x3E, ++0x11,0x20,0x79,0x3B,0xDE,0xA3,0xC8,0x3A, ++0x4B,0xDF,0xC6,0x3F,0x2E,0xE2,0x05,0x32, ++0x54,0xA0,0x49,0x3D,0xDF,0xE3,0x88,0x3A, ++0xF4,0x38,0x61,0x3E,0xDF,0xA3,0x79,0x38, ++0x57,0x50,0x49,0x3F,0x6A,0x82,0xB7,0x5E, ++0xE5,0x41,0x76,0x4B,0x4F,0xA1,0x2E,0x5B, ++0xF9,0x31,0x76,0x3B,0xFA,0x87,0x88,0x3A, ++0x55,0x60,0x28,0x3B,0x9F,0xBB,0xA9,0x3A, ++0x33,0x66,0x4E,0x5D,0xB9,0xD5,0xCF,0x5F, ++0x17,0x6E,0x2F,0x59,0xB8,0xE5,0x8F,0x58, ++0xF2,0x50,0x0E,0x59,0x9C,0xE9,0xEE,0x5C, ++0x33,0x66,0x4E,0x5D,0xB9,0xD5,0xCF,0x5F, ++0x13,0x62,0x2F,0x59,0xB8,0xC5,0x8F,0x58, ++0x72,0x5E,0x0E,0x59,0xB8,0xE5,0x8F,0x58, ++0x32,0x56,0x0E,0x5A,0x98,0xED,0xEE,0x5C, ++0x13,0x4A,0x2F,0x59,0xB8,0xE5,0x8F,0x58, ++0xF2,0x50,0x0E,0x59,0xB8,0xC5,0x8F,0x58, ++0x35,0x56,0x2F,0x59,0xED,0xCA,0xC1,0x5F, ++0x59,0xBF,0x70,0x53,0xD8,0xC4,0xD1,0x58, ++0xCB,0x69,0x88,0x5B,0xBA,0xD9,0xEE,0x5E, ++0x33,0x86,0x2F,0x5B,0x00,0xE3,0x8E,0x5C, ++0x32,0x66,0x8D,0x5B,0x04,0xE3,0x8E,0x5C, ++0x87,0xC0,0x4F,0x59,0x08,0x82,0x8E,0x5C, ++0x17,0x6E,0x2F,0x59,0x0C,0xE2,0x8E,0x5C, ++0x7C,0xAF,0xB0,0xA6,0x73,0x7B,0x2E,0xA7, ++0x3C,0xB7,0xE4,0xA2,0x45,0x32,0x31,0xA1, ++0x3C,0xB7,0xF4,0xA2,0x57,0xF4,0x35,0xA7, ++0xDC,0x37,0xF4,0xA2,0x81,0xC5,0x4E,0xA9, ++0xCA,0x99,0xF0,0xA7,0x5B,0x34,0x25,0xA7, ++0xCD,0xB9,0x70,0xA5,0x46,0x3A,0xE1,0xA1, ++0xCF,0xB9,0x70,0x4D,0x87,0xC5,0x4E,0xA9, ++0xCE,0xB9,0x20,0xA6,0x47,0x6A,0x11,0xA3, ++0x3B,0x46,0x8F,0x7D,0x45,0x3A,0xE4,0xA3, ++0xC0,0x89,0xD0,0x76,0x47,0x1A,0x11,0x71, ++0xD8,0xB9,0x70,0x7D,0x42,0x2A,0x11,0xA3, ++0x28,0xB9,0xFF,0xA5,0x00,0xC3,0x4E,0xA9, ++0x8D,0xB6,0xFF,0xA5,0x61,0x3A,0xB1,0xA8, ++0x60,0xB9,0xF2,0xA7,0x47,0x3B,0x35,0xA2, ++0xEC,0x57,0xE0,0xA2,0x47,0x2A,0x11,0xA1, ++0xCE,0x38,0xF1,0xA7,0xC6,0x3B,0x11,0xA3, ++0x2F,0x64,0x0D,0x7B,0x92,0xE7,0xAB,0x78, ++0x10,0x64,0x2C,0x78,0xEA,0xF7,0x93,0x79, ++0x15,0x64,0xFC,0x79,0x6D,0x18,0x93,0xA5, ++0x13,0x64,0x2E,0x78,0xEA,0xD7,0x93,0x79, ++0x10,0x64,0x2F,0x78,0xEA,0xC7,0x93,0x79, ++0x1E,0x64,0xFE,0x79,0x77,0x18,0x93,0x05, ++0x51,0x64,0x0D,0x79,0x8A,0xE9,0xE8,0x7A, ++0x8E,0x9B,0x52,0x71,0x9C,0xC7,0xEC,0x7F, ++0x0D,0x6A,0x39,0x7F,0x98,0xE7,0x7C,0x7C, ++0x12,0x64,0xAD,0x90,0x00,0x18,0x93,0x74, ++0x13,0x64,0xFD,0x7B,0x9A,0xB7,0xCC,0x7E, ++0xE9,0x9B,0x52,0xA0,0x98,0xE7,0x39,0x7E, ++0xE1,0x6A,0x39,0xAF,0x98,0xEF,0xAC,0xAC, ++0xE1,0x6A,0x29,0xAF,0x9A,0xE7,0xCC,0xAC, ++0xE1,0xE5,0x10,0xA2,0x9F,0xF7,0xCC,0x7E, ++0x6D,0x64,0x22,0x78,0x85,0x1E,0x93,0x74, ++0xD8,0x31,0x77,0x2D,0xD2,0x4B,0xC6,0x21, ++0xB4,0x3F,0x6C,0x2A,0xCD,0xBA,0xF9,0x29, ++0xB4,0x3F,0x7C,0x2A,0xCA,0xB2,0x99,0x29, ++0xB4,0xB0,0x45,0x27,0xCF,0x92,0x09,0xEF, ++0xE4,0xC6,0xFB,0xCF,0x37,0xCD,0x38,0xEA, ++0x00,0x54,0x94,0xAE,0xB6,0x92,0x6D,0xA3, ++0x27,0x5A,0x8B,0xF2,0xFF,0xCA,0x1C,0xB2, ++0x4E,0x31,0xF8,0xCF,0xCF,0xD1,0x39,0xEF, ++0x44,0x21,0xC8,0xEA,0xFE,0x92,0x7A,0xBF, ++0x36,0x65,0x91,0xAC,0xA4,0xC1,0x04,0xFA, ++0x3C,0x14,0x80,0xE3,0xEF,0xE5,0x58,0xA3, ++0x30,0x64,0x96,0xBB,0xA6,0xDE,0x6D,0xA3, ++0x27,0x5A,0x8B,0xF2,0xFF,0xCA,0x1C,0xB2, ++0x4E,0x31,0xF8,0xCF,0xA7,0xD3,0x4A,0xA2, ++0x64,0x45,0x91,0xA2,0xAA,0x92,0x56,0xBF, ++0x30,0x3B,0xF8,0xCF,0xFD,0x92,0x7A,0xBF, ++0xAF,0xFC,0x08,0x35,0x3D,0x58,0x9D,0x63, ++0xA5,0x8D,0x19,0x7A,0x76,0x7C,0xC1,0x3A, ++0xA9,0xFD,0x0F,0x22,0x3F,0x47,0xF4,0x3A, ++0xBE,0xC3,0x12,0x6B,0x66,0x53,0x85,0x2B, ++0xD7,0xA8,0x61,0x56,0x35,0x47,0xC5,0x32, ++0xAF,0x88,0x15,0x3F,0x3B,0x4E,0xD2,0x73, ++0xB2,0xDD,0x15,0x5C,0x56,0x2B,0xA0,0x53, ++0xC3,0x57,0x4E,0xB7,0x2A,0x9E,0xAC,0x53, ++0xC8,0xA8,0x61,0x7F,0x56,0xBB,0xA1,0x83, ++0xDD,0xB1,0x21,0x48,0x3C,0x6D,0xA7,0x1A, ++0xA4,0xEC,0x60,0xC6,0x7E,0x2B,0xA0,0xA3, ++0x35,0x52,0x64,0x56,0x56,0x07,0xA3,0x83, ++0xB4,0xEE,0x61,0x76,0x56,0xDB,0x54,0xA9, ++0xF5,0xA8,0x1D,0xEB,0x51,0x2D,0xA0,0x53, ++0xDC,0x68,0xEE,0xB4,0x4A,0xD4,0x8F,0xB2, ++0x2A,0x1D,0xE3,0xE6,0x59,0x2B,0xA2,0xCF, ++0xEE,0xBD,0x52,0x95,0x6B,0xF2,0x92,0xF0, ++0xEE,0xF3,0x52,0xF5,0x40,0x60,0xF7,0x7C, ++0xEE,0xB6,0x57,0xB5,0x65,0xE8,0x6B,0x89, ++0xEE,0xF3,0x12,0x38,0xA5,0x1F,0x66,0xB1, ++0xC5,0xB6,0x54,0xB5,0x48,0x35,0x90,0xB1, ++0xEF,0xBB,0xD2,0x67,0x63,0x5B,0x93,0x80, ++0x8A,0x85,0x53,0xFD,0x65,0x39,0x92,0x00, ++0xEA,0x01,0x6B,0x65,0x45,0x18,0x93,0x90, ++0x07,0x67,0x53,0x65,0x65,0x37,0x97,0xB0, ++0xD6,0xF3,0xF2,0x27,0x64,0xC9,0x91,0xF8, ++0xD6,0xFB,0x53,0xFD,0x65,0x70,0x91,0x48, ++0xEB,0x4B,0x53,0xFD,0x65,0x82,0x91,0x00, ++0xA6,0xD9,0x20,0x60,0x65,0xCC,0x9B,0x60, ++0xEB,0x2B,0xA2,0xD8,0x64,0x28,0x13,0x81, ++0xFE,0xDB,0x7F,0x8C,0x66,0x18,0x80,0x83, ++0xF0,0x9B,0x52,0x7F,0xA1,0x58,0x0C,0x85, ++0xFB,0x8A,0x11,0x97,0x6F,0x09,0x82,0x4B, ++0xFB,0xBA,0xD3,0x90,0x70,0xC9,0x13,0x95, ++0xFB,0xAA,0x01,0x96,0x87,0xE6,0xE6,0x97, ++0xFF,0x8A,0x1D,0x97,0x71,0x09,0x82,0x6B, ++0xF3,0x8A,0x10,0x95,0x81,0xF6,0x7D,0x7B, ++0xCC,0x85,0xFC,0x92,0x48,0x16,0x3D,0x97, ++0xFE,0x8A,0x03,0x94,0x64,0x89,0x3F,0x99, ++0x00,0x8A,0x40,0x96,0x8B,0x19,0x8E,0x93, ++0xFE,0x8A,0x03,0x94,0x7A,0x15,0x12,0x90, ++0x8C,0x8A,0xBC,0x72,0x08,0x19,0x7D,0x77, ++0xFE,0x8A,0x03,0x74,0x7A,0x11,0x12,0x70, ++0x00,0x9E,0x80,0x77,0x8B,0x0D,0x4E,0x72, ++0xFF,0x8A,0x02,0x74,0x7A,0x1D,0x12,0x70, ++0xEF,0x0A,0xFE,0x6C,0x57,0x05,0x22,0x90, ++0xD3,0x86,0x03,0x94,0x64,0x89,0x3F,0x99, ++0xFF,0x8A,0x11,0x97,0x74,0x09,0x22,0x72, ++0x76,0x93,0x67,0xE5,0xEC,0xA0,0xCB,0x0C, ++0x67,0xD3,0x0B,0x09,0xED,0x90,0x48,0x0B, ++0x6C,0x13,0xDA,0xE7,0xE1,0x90,0x48,0x09, ++0x6E,0x13,0xDA,0xF7,0xEC,0xB0,0x49,0x0A, ++0x67,0x23,0x0A,0xF9,0xEC,0x50,0xCA,0xFC, ++0x66,0x13,0x89,0xFE,0xEE,0x90,0x1B,0xE2, ++0x6A,0x13,0x89,0x0C,0xEC,0x90,0x1B,0xF2, ++0x67,0x33,0x88,0x0F,0x1D,0x6F,0xE4,0xF2, ++0x6A,0x13,0x99,0x0D,0xFD,0x10,0xA6,0x00, ++0x67,0x12,0xDB,0xEC,0xEC,0xB0,0x9B,0x0A, ++0x65,0x13,0xDA,0x07,0xEC,0x80,0xCB,0x0C, ++0x66,0x13,0x8B,0x0E,0xEF,0x90,0x5B,0xE8, ++0x78,0xEC,0xF5,0xEC,0xEE,0x90,0x0B,0x0B, ++0x9F,0xEC,0x25,0xF7,0xD9,0xA0,0x84,0x0D, ++0x62,0x03,0x4A,0x09,0x1C,0x8F,0x78,0x0E, ++0x66,0x13,0x8B,0x0E,0x16,0x6F,0xE4,0xE2, ++0x9B,0xEC,0x65,0xF2,0x13,0x43,0x54,0xF6, ++0x9A,0xEC,0x65,0x00,0x0C,0x90,0xCB,0x06, ++0x98,0xC4,0x95,0xF3,0x10,0x6F,0xA4,0x05, ++0x87,0x13,0x0A,0x03,0x13,0x7B,0x54,0xF6, ++0x98,0xEC,0x65,0x00,0x0C,0x90,0xCB,0xF6, ++0x98,0xED,0x24,0x13,0x11,0x6F,0xB6,0xF4, ++0x8E,0xEC,0x25,0x88,0x11,0xAF,0xF4,0xF5, ++0x91,0xEC,0x25,0x18,0x13,0x5F,0x35,0xF3, ++0x9B,0xEC,0x79,0xF1,0x1E,0x4F,0x66,0xF7, ++0x98,0x2C,0xF4,0x86,0x13,0x5F,0x24,0xF3, ++0x98,0xDC,0xF4,0x26,0x13,0xAF,0x24,0x83, ++0x9D,0xCC,0x67,0xF0,0x13,0x5F,0x24,0x23, ++0x9A,0xDC,0x34,0xF0,0x5A,0x6D,0xE4,0x1D, ++0x91,0xCC,0x77,0xF0,0x16,0x6F,0xE4,0x2D, ++0x9D,0xDC,0xB4,0xF6,0x16,0xAF,0x75,0xF3, ++0x9D,0xDC,0xA5,0xF6,0x16,0xAF,0x64,0xF3, ++0x07,0x75,0xBC,0x9E,0x70,0x29,0x10,0x93, ++0xFB,0xBA,0xD2,0x20,0x70,0x39,0x02,0x25, ++0xFF,0x8A,0xE3,0x95,0xF6,0x26,0x32,0x90, ++0xFE,0xBA,0x92,0x50,0x75,0xC9,0x53,0x55, ++0xFE,0xAA,0x92,0x30,0x75,0x39,0x42,0x55, ++0xFE,0x4A,0x83,0x50,0x75,0x29,0x42,0x35, ++0xE1,0x75,0x6C,0x95,0x8B,0x39,0x80,0x93, ++0xFC,0xAE,0xC0,0x95,0x76,0x21,0x00,0x90, ++0xFF,0x8A,0x43,0x9E,0x74,0x29,0x22,0x92, ++0xFB,0x8A,0x12,0x97,0x73,0x09,0x82,0x4B, ++0xFC,0x4A,0x53,0x96,0x6C,0x0B,0x82,0x7B, ++0xFB,0x4A,0x2F,0x96,0x76,0x09,0xDE,0x92, ++0xFE,0xAA,0x83,0x60,0x78,0x19,0xC3,0x91, ++0x4D,0xAA,0x83,0xD4,0x66,0x0B,0x82,0x9B, ++0x7E,0x45,0xF3,0x95,0x75,0x29,0x42,0x55, ++0xFE,0xAA,0x83,0x50,0x75,0x29,0x42,0x35, ++0xA5,0x31,0x28,0xD1,0x31,0x7D,0x56,0xD4, ++0x9A,0xCE,0x07,0x7A,0x30,0x6D,0x76,0xD6, ++0x1B,0xFE,0x76,0xD0,0x2A,0x4D,0xC6,0x0F, ++0x9B,0xFC,0x76,0xD0,0x3F,0x4D,0xC6,0x0F, ++0x9B,0xFA,0x76,0xD0,0x31,0x4D,0xC6,0x0F, ++0xBB,0x0E,0xA7,0xD3,0x10,0x4D,0xC6,0xDF, ++0x1B,0xFD,0x76,0xD0,0xB1,0x4E,0x86,0x15, ++0xB9,0xEE,0xB5,0xD0,0x10,0x7E,0xB7,0xD5, ++0xBA,0xCD,0x47,0x10,0x32,0x6D,0x74,0xD5, ++0x1B,0xFC,0x76,0xD0,0xB1,0x4F,0x86,0x15, ++0xB9,0xEE,0xB5,0xD0,0x10,0x7F,0xB7,0xD5, ++0xBA,0xCC,0x47,0x10,0x32,0x6D,0x74,0xD5, ++0x1B,0xFF,0x76,0xD0,0xB1,0x4C,0x86,0x15, ++0xB9,0xEE,0xB5,0xD0,0x10,0x7C,0xB7,0xD5, ++0xBA,0xCF,0x47,0x10,0x32,0x6D,0x74,0xD5, ++0x1B,0xFE,0x76,0xD0,0xB1,0x4D,0x86,0x15, ++0x75,0x22,0x79,0x1C,0xFD,0x91,0x5A,0x19, ++0x77,0x12,0x6B,0xCD,0xFE,0x81,0xA8,0x19, ++0x69,0xFD,0xE4,0x1D,0xFE,0xA0,0x1B,0x1B, ++0x77,0x12,0xAA,0xBE,0xBC,0x41,0x38,0x19, ++0x77,0x02,0xAB,0xDE,0xDC,0xB3,0x7B,0x19, ++0x6A,0x02,0xCB,0xC6,0xDC,0xB5,0x7B,0x19, ++0x78,0x02,0xCB,0xC6,0xFD,0x92,0xAA,0x18, ++0x57,0x36,0xBA,0x1C,0xC3,0xA2,0x88,0x1A, ++0x7C,0x02,0xCB,0xC6,0xFD,0x92,0xAA,0x18, ++0x57,0x36,0xBA,0x1C,0xC3,0xA7,0x88,0x1A, ++0x70,0x02,0xCB,0xC6,0xFD,0x92,0xAA,0x18, ++0x57,0x36,0xBA,0x1C,0xC3,0xA8,0x88,0x1A, ++0x76,0x11,0x6B,0xDD,0xC3,0xAD,0x88,0xDA, ++0x77,0x32,0xBA,0x1E,0xE1,0x81,0x0A,0xD3, ++0x56,0x11,0x6B,0xDD,0x5C,0xB2,0x7B,0x19, ++0xF6,0x01,0x8B,0xDC,0xFE,0xA1,0xB8,0x19, ++0xEC,0x8A,0x01,0xA7,0x46,0x39,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0xE7,0x08,0xC0,0xA2, ++0x4D,0xBB,0x30,0x67,0x45,0x1A,0x03,0xA2, ++0xEC,0x8B,0x01,0xA7,0x46,0x38,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0xE7,0x0B,0xC0,0xA2, ++0x4D,0xB8,0x30,0x67,0x45,0x1A,0x03,0xA2, ++0xEC,0x88,0x01,0xA7,0x46,0x3B,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0xAC,0xC5,0x4E,0x68, ++0x6C,0x89,0x01,0xA7,0xC6,0x3A,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0x46,0x2A,0xE1,0xA2, ++0xCC,0xA9,0xD0,0x76,0x45,0x3A,0x13,0xA2, ++0x00,0x76,0xC0,0xA6,0x47,0x3A,0xD1,0x00, ++0xCC,0xA9,0x11,0x65,0x59,0xC5,0x9E,0xA3, ++0x00,0x76,0xC0,0xA6,0x47,0x3A,0xD1,0x00, ++0xCD,0xF9,0x5D,0xAE,0x47,0x3A,0x01,0xA1, ++0xCB,0xB9,0x70,0xAC,0x45,0xBA,0x0C,0xAA, ++0xBC,0xFE,0x00,0x00,0x37,0x7D,0xB1,0x42, ++0xDC,0xF9,0x5D,0xAE,0xA3,0x3B,0xB1,0xA9, ++0xC8,0xB9,0xE0,0xA5,0x57,0xBA,0x0C,0xAA, ++0x20,0xA1,0x70,0x47,0x9B,0x3B,0xB1,0xA8, ++0xC8,0xB9,0xEF,0xA2,0x59,0xC5,0x9E,0xA3, ++0xD2,0x46,0x5F,0xA6,0x67,0x95,0xB3,0x62, ++0xBC,0x0C,0xF5,0x2E,0x43,0x3A,0xB1,0x2A, ++0xFC,0x9F,0xB1,0x41,0x47,0xEE,0x91,0x64, ++0x0C,0xBE,0x79,0x96,0x41,0xDA,0xD3,0x2A, ++0x6D,0xD1,0x40,0x47,0xD7,0x7D,0x91,0x28, ++0x8C,0xA5,0x50,0x25,0x2A,0x24,0x47,0x97, ++0xBC,0x04,0x00,0xF2,0xC2,0x53,0xB5,0x42, ++0xCC,0xD1,0xB0,0x40,0x4E,0xEA,0xB7,0xA2, ++0xAE,0xD1,0xD1,0x2F,0x67,0x1A,0x21,0x05, ++0xEC,0xD3,0x30,0x5B,0x67,0x58,0xDC,0x5C, ++0x3A,0x6C,0x00,0xFA,0x4E,0x52,0xFB,0x47, ++0xEC,0x4E,0x52,0x63,0x65,0x0E,0xE3,0x27, ++0x27,0x9E,0xAE,0xB0,0x65,0x1C,0x93,0x74, ++0x9E,0xDC,0x5B,0x0D,0x2F,0x1D,0x91,0xB5, ++0xEE,0x9D,0x52,0x6B,0x15,0x5F,0x5A,0x65, ++0x12,0x4E,0x52,0x61,0x65,0x14,0xE3,0x27, ++0x9E,0x2E,0x57,0x65,0x69,0x18,0x92,0x4A, ++0xEF,0x4A,0x53,0x45,0x6E,0xF8,0xBB,0x08, ++0x6E,0x9D,0x52,0xB0,0x8F,0x71,0x93,0x40, ++0xEE,0x7B,0x12,0x79,0xF5,0x5A,0x91,0xB2, ++0xCF,0xC7,0x52,0x4C,0x9C,0xC9,0x3A,0x09, ++0xC8,0x83,0x5B,0x7F,0xCC,0x79,0xBA,0x0A, ++0xE7,0x83,0x7A,0x65,0x4C,0x7A,0x6C,0x97, ++0x49,0x64,0x56,0x85,0x0F,0x70,0xB3,0x18, ++0x47,0xF3,0x36,0x79,0xF5,0x5F,0x27,0x22, ++0x16,0x48,0x7A,0x65,0x9A,0xEF,0x22,0x9F, ++0x9E,0x26,0x52,0x65,0x64,0xD8,0x1C,0x82, ++0x58,0xCE,0xD7,0x2E,0x38,0x07,0x39,0xEF, ++0x31,0x18,0xE8,0xA7,0xCF,0x2B,0x2D,0x6C, ++0x55,0xE1,0x07,0x38,0x7C,0x4D,0x39,0xE2, ++0x46,0xEB,0xB8,0x8D,0xDE,0x14,0x31,0x2A, ++0x44,0xA8,0xF1,0xA7,0x45,0xB5,0x38,0x1F, ++0x4B,0x97,0xFA,0x2F,0x86,0xB5,0x3D,0x1F, ++0x4A,0x97,0xF9,0xEA,0xCE,0x52,0xC6,0x3D, ++0xE8,0xCE,0xF8,0x50,0xCF,0x96,0x1D,0xFD, ++0x40,0xD1,0xF8,0x3F,0xA5,0x5C,0x09,0xFB, ++0x7D,0x64,0x9C,0xD3,0xCF,0x9A,0xC1,0x1B, ++0x44,0xA9,0xD3,0xCF,0xFD,0xB2,0x18,0xCA, ++0x44,0xC1,0x80,0x34,0x31,0x0F,0x39,0xCA, ++0x44,0x31,0xF8,0xCF,0xE2,0xB2,0x39,0xCA, ++0x6F,0x31,0xF8,0xCF,0xEF,0xB2,0x39,0xCA, ++0x45,0xF1,0x77,0x2D,0xD3,0x4D,0x16,0x2B, ++0x55,0x59,0xFA,0xA7,0xCF,0xD8,0x6A,0xCF, ++0x89,0x28,0x3C,0x73,0x09,0x9E,0x26,0x03, ++0x89,0x28,0x3C,0x83,0x05,0x9E,0xE6,0x00, ++0x8A,0x28,0xF6,0x14,0x06,0xBF,0xF4,0xE6, ++0xDA,0xFB,0x3C,0x63,0x02,0x5E,0x85,0x41, ++0x89,0x94,0x7E,0x1F,0x01,0x1F,0xFD,0x7E, ++0xF8,0xBA,0x24,0xB6,0x93,0xCE,0xF9,0x06, ++0x8B,0x6F,0x34,0x21,0x05,0xEC,0xF0,0x4C, ++0x8D,0x6D,0x2D,0x03,0x79,0x3A,0xF4,0xAE, ++0x8A,0x69,0x30,0x91,0x03,0x8E,0xA9,0xFF, ++0x98,0x4D,0x24,0xBE,0xE2,0x81,0x0A,0xF9, ++0x82,0x95,0x24,0x73,0x51,0x62,0xFF,0x66, ++0xF8,0xBA,0x7F,0x6B,0x09,0x16,0x6F,0x44, ++0x8A,0x2F,0x67,0x1F,0x08,0x1E,0xE5,0x76, ++0xF8,0xBA,0x34,0x03,0xF4,0xCB,0xF1,0x06, ++0x9D,0xFD,0x18,0x4B,0x85,0xCE,0x8D,0x42, ++0x88,0xDA,0x37,0xCB,0x3D,0x7E,0xF6,0x96, ++0xD9,0x39,0x70,0xB6,0x51,0xB3,0xD1,0x53, ++0xDE,0x02,0x20,0x0C,0x57,0x83,0xA0,0xA3, ++0x3C,0x55,0x20,0x4A,0x51,0xFB,0x81,0x3B, ++0x54,0xAE,0x62,0x83,0xB4,0x42,0x99,0x4B, ++0x4C,0xEA,0x6F,0x8E,0x69,0x33,0xD6,0x4F, ++0xFD,0xC0,0xE1,0x50,0x54,0xFE,0x40,0x3A, ++0x65,0xEA,0x67,0x8B,0xF8,0x69,0x45,0x88, ++0xDA,0x30,0x10,0x56,0x16,0x71,0xA0,0x7B, ++0x3D,0x79,0xC1,0x3F,0x96,0x30,0x00,0x32, ++0xFD,0xA8,0x9E,0xA1,0xA7,0xD5,0xB5,0x1B, ++0xA5,0xEC,0x3B,0x6E,0x55,0xE3,0xA3,0xC3, ++0xDD,0x88,0x65,0xC7,0x40,0xCB,0xE1,0x53, ++0xDA,0x30,0x62,0xFC,0x17,0x71,0xA1,0xFB, ++0xDD,0x58,0xD5,0xAB,0x56,0xBB,0xE0,0x4F, ++0xD7,0x78,0x61,0x73,0x53,0xCB,0xC2,0x3B, ++0xDC,0x00,0xC0,0x3E,0x16,0x76,0x30,0x14, ++0xC7,0xC3,0x16,0xB9,0xA4,0x1E,0x21,0xF7, ++0xAF,0x47,0x56,0x3D,0x91,0x1E,0xD2,0xB4, ++0x4F,0x04,0x36,0x4B,0xE1,0x45,0xF7,0x46, ++0x8A,0xDF,0xE9,0xD6,0xFF,0xA2,0xDE,0x94, ++0x5A,0x62,0x16,0x21,0x93,0x4B,0xD7,0x24, ++0xAB,0x1F,0x99,0xC3,0x3D,0xA3,0xF8,0xC5, ++0x5D,0x6A,0xC4,0x3C,0xA3,0xEC,0x07,0x2C, ++0xAA,0xFA,0xD6,0x21,0xD4,0x75,0x17,0xEC, ++0xB0,0x7F,0x17,0xB1,0x35,0x8C,0xD7,0x07, ++0x93,0xDF,0xE6,0x3B,0xB8,0x1D,0xD3,0xFE, ++0xDC,0x9D,0x84,0x60,0xF6,0x47,0xC1,0x84, ++0xA2,0x3F,0x14,0xB9,0x21,0x34,0x56,0x23, ++0xAB,0x0A,0x02,0x81,0x23,0xBC,0x97,0x23, ++0xA8,0x0A,0x05,0x81,0x20,0x79,0xD6,0xB4, ++0xA8,0x47,0x16,0x05,0x05,0x6C,0xD7,0xB4, ++0xA3,0x3F,0x2F,0x21,0x11,0x5C,0xD7,0xD4, ++0x0F,0xCA,0xE9,0x45,0xEE,0x91,0x2E,0xDB, ++0x4F,0x75,0x8D,0xC2,0xD1,0xA3,0x28,0xF8, ++0x6C,0x20,0xD9,0xDE,0x87,0xE3,0x70,0x9B, ++0x5D,0x63,0x07,0x0F,0xDF,0x39,0x2A,0x43, ++0x7E,0x20,0xC8,0xDE,0xDE,0x53,0xBA,0x21, ++0x50,0x90,0x19,0x63,0xDE,0xA3,0x28,0xDB, ++0x78,0x20,0xE9,0xDE,0xF5,0xA3,0x28,0xDB, ++0x75,0x20,0xE9,0xDE,0x89,0x63,0xA7,0x39, ++0x49,0xDF,0xC6,0x3F,0x26,0x16,0x2F,0xDB, ++0x40,0x20,0xF7,0xDE,0xDE,0x87,0x0C,0xEB, ++0x55,0xB0,0xE0,0x3E,0xDE,0x3A,0x40,0xDC, ++0xB8,0x28,0xA9,0xD1,0xEE,0x93,0x20,0x8E, ++0x25,0x27,0x8D,0xC2,0xDB,0xE0,0xDE,0xD3, ++0x55,0x03,0xD8,0xDE,0xF6,0xA3,0x71,0x9B, ++0x0D,0x60,0xE1,0x9D,0x30,0x72,0x10,0xB3, ++0x45,0x82,0xE8,0xD9,0xD6,0x76,0x08,0xFA, ++0x5D,0x60,0xC9,0x9D,0xDA,0x73,0xD0,0xB2, ++0x54,0x03,0xE4,0x7C,0x9E,0xBD,0xD0,0xBA, ++0x74,0x20,0xD1,0xDE,0xDE,0x53,0x72,0x21, ++0xAD,0x9D,0xF9,0x6B,0xDA,0xA3,0x38,0xB3, ++0x74,0x20,0x16,0x29,0xA8,0x5D,0x2A,0xDB, ++0x55,0x03,0xC9,0xDE,0x21,0x54,0xE2,0x24, ++0x45,0x9D,0x3B,0xC3,0x0F,0xAB,0xE1,0xDB, ++0x59,0xE9,0x2A,0x39,0xDE,0xA3,0x28,0xDB, ++0x65,0x20,0xE9,0xDE,0x45,0x63,0xA7,0x39, ++0x49,0xDF,0xC6,0x3F,0x2E,0x16,0x3D,0xDB, ++0x4A,0x94,0x6B,0x6E,0xC0,0xA3,0x2A,0x43, ++0x55,0x48,0xE9,0xDB,0xDC,0x76,0x0F,0x94, ++0x2A,0x64,0xEB,0x3E,0xFB,0xEC,0x57,0x9F, ++0x5B,0x17,0xEB,0x46,0xDE,0x87,0x0C,0xEB, ++0x54,0xB0,0xE0,0x3E,0xF6,0xA4,0x29,0x42, ++0x55,0x2F,0xC4,0xD7,0xE6,0xFF,0x20,0x8E, ++0x9A,0xD8,0x72,0x3D,0x24,0x1F,0xE1,0x2D, ++0xAA,0xFC,0x27,0x21,0x09,0x5C,0x8E,0x64, ++0xF2,0x9F,0x1E,0x62,0xCF,0x8D,0xD5,0xBC, ++0x90,0xDF,0x16,0x49,0x21,0x5B,0xDE,0xF1, ++0xA9,0x47,0x66,0x09,0x23,0x8D,0xC7,0x16, ++0xAB,0xFC,0x15,0xC1,0x21,0x70,0xD6,0xF4, ++0xBB,0xED,0x14,0x02,0x23,0xC4,0xF6,0x24, ++0xAA,0x2F,0x1E,0xDB,0x26,0xEC,0x27,0x99, ++0xDA,0x6A,0x12,0x21,0x2C,0x5C,0xC7,0x4C, ++0x8B,0xDF,0xE9,0xD6,0x03,0xA2,0xD5,0x24, ++0xAA,0xFC,0x3F,0x21,0x01,0x5C,0x28,0xD3, ++0x13,0x20,0x66,0x9C,0xF3,0x41,0x04,0x2C, ++0x71,0xDF,0x1A,0xEA,0x93,0xBB,0xE7,0x90, ++0xA9,0xB7,0x36,0x05,0x33,0x34,0xF4,0x67, ++0xA9,0xBF,0x1E,0x02,0xE2,0x3D,0xE7,0x98, ++0xAA,0xFC,0xB1,0xC6,0xF1,0x49,0xD7,0x24, ++0x84,0xB7,0xCE,0xFC,0xFC,0xA1,0x8B,0x49, ++0xC9,0xE2,0x22,0x94,0xD4,0x81,0x82,0xBE, ++0x77,0x2A,0xB5,0x2C,0xD9,0xA9,0x08,0x29, ++0x1D,0x6A,0x62,0x94,0x4D,0x61,0x56,0xB6, ++0x77,0x24,0xB4,0xB8,0x15,0xE9,0x22,0xF9, ++0xFF,0x45,0xCF,0xFC,0xDC,0xA9,0x02,0x22, ++0x46,0x2E,0xCD,0x2E,0xC4,0x98,0x2A,0xC1, ++0x77,0x7A,0xCB,0xD4,0xFD,0x51,0x0C,0xBA, ++0x87,0xE5,0x7B,0xFB,0xFD,0x54,0x0E,0xD9, ++0xF1,0x41,0xCB,0xDC,0x14,0xE0,0x0D,0xF9, ++0xDF,0x63,0xE1,0xD0,0xED,0x50,0x08,0x61, ++0xCD,0x02,0x99,0xE5,0xFE,0x49,0x9B,0x98, ++0x75,0x92,0x22,0x94,0xD4,0x81,0x82,0xBE, ++0x73,0x02,0xCA,0xD3,0xDA,0x50,0xE2,0x90, ++0x77,0x2A,0xE5,0x26,0xDC,0xA1,0x8C,0xBA, ++0x5C,0xE2,0xEB,0xFC,0xCC,0xB9,0x0B,0xDB, ++0x23,0x57,0x94,0x81,0xB1,0x06,0x5F,0x86, ++0x34,0x87,0x26,0xA9,0xE9,0xCD,0x5F,0x3C, ++0xA3,0x36,0x99,0x49,0xA9,0x4C,0x55,0x8D, ++0xA2,0x3E,0xD6,0xEA,0xA9,0x4D,0x5F,0xB5, ++0x12,0x6F,0x16,0xC8,0x40,0xBC,0x77,0xAC, ++0xAA,0x10,0x9A,0xA9,0xA8,0xF5,0x6F,0x94, ++0x28,0x7F,0x9F,0x7B,0xA9,0xFD,0xB2,0x7D, ++0x23,0x78,0x94,0x79,0x87,0xF8,0x57,0x7D, ++0xCB,0x3F,0xB6,0xA9,0x21,0x93,0x5B,0xAC, ++0x02,0x77,0x98,0xEA,0xD6,0xC8,0x5D,0x83, ++0x9D,0x8C,0x36,0xC0,0xA9,0xFC,0x5C,0x76, ++0x62,0x15,0x36,0xC8,0xA8,0xF4,0x59,0xEF, ++0xD2,0x50,0x9F,0x79,0xB9,0xF4,0xD9,0xEF, ++0x4E,0x7B,0x9F,0x79,0xC1,0xF8,0x48,0x7D, ++0xCB,0x3F,0xB9,0xA9,0x81,0xD4,0xD7,0xEB, ++0x26,0x57,0x26,0xEB,0xA3,0x05,0xDF,0x8C, ++0x7D,0x4B,0xAD,0x4A,0x5A,0xE7,0x85,0xF7, ++0x17,0x27,0x85,0x9A,0x12,0xA0,0x68,0x9F, ++0x07,0x84,0x96,0x7A,0xDA,0xC7,0x00,0xB0, ++0x11,0xB4,0x2D,0x9A,0x9C,0xA4,0x63,0x7F, ++0x5D,0x48,0xA8,0x4A,0xF0,0xCB,0x6F,0x4F, ++0x65,0x48,0xAC,0x4A,0xE0,0xCB,0x6B,0x4E, ++0x11,0x44,0xE1,0xB6,0x7D,0x37,0xEC,0xBF, ++0x7B,0x48,0x49,0x4A,0x9A,0xC7,0x8E,0x78, ++0x11,0x48,0x8E,0x4A,0xBA,0xE7,0x2D,0xA7, ++0x08,0x4C,0xAE,0x42,0x9B,0xC7,0xAC,0x9D, ++0x17,0x27,0x8D,0xAE,0xB4,0x87,0x6E,0x05, ++0x30,0x64,0x85,0x9A,0x8C,0xE7,0x91,0x68, ++0xDB,0x8F,0xAD,0xB2,0x90,0x37,0x6D,0xB7, ++0x13,0xB5,0x9B,0x87,0x98,0x71,0x20,0x78, ++0xE7,0x79,0x5D,0x92,0x5A,0xE7,0x64,0xAF, ++0x13,0xF4,0xEB,0x7D,0xF0,0x8F,0xC5,0xF7, ++0x9B,0xCE,0x97,0x77,0x18,0x27,0x86,0x29, ++0x93,0xAC,0x39,0xD7,0x18,0x27,0x38,0x88, ++0x8D,0xDB,0x07,0x30,0xC7,0xF8,0x44,0x85, ++0xBB,0xE9,0x05,0xAC,0x25,0x4D,0xE6,0x4D, ++0xDF,0xD2,0x06,0xA7,0x00,0x65,0xD5,0xE4, ++0x9B,0xB6,0x06,0x17,0x54,0x51,0xBE,0x1D, ++0xBA,0x1E,0x5F,0x18,0x38,0x9C,0xC6,0x18, ++0xBA,0x1E,0x17,0x1D,0x3B,0x9C,0xE6,0x4D, ++0xBB,0xE9,0x17,0x15,0x54,0x51,0xC0,0xD5, ++0xBB,0xE3,0x03,0xE1,0x38,0x68,0xC4,0xD5, ++0xBB,0xE3,0x07,0xE1,0x3A,0x68,0xC6,0x13, ++0xBB,0x58,0x16,0xD0,0x30,0xD4,0xC7,0x12, ++0xD2,0x8D,0x0F,0x28,0x19,0x4D,0xC4,0x39, ++0xCA,0x8D,0x07,0x34,0x30,0x41,0xC6,0xA5, ++0x35,0xD6,0x3F,0x34,0xB6,0x0F,0xC7,0xE6, ++0xBA,0xEE,0x06,0xA0,0x10,0x35,0xA2,0x29, ++0x1A,0x46,0x8F,0x48,0x2E,0x3E,0x4E,0x95, ++0xDB,0x9C,0x8C,0x20,0xB8,0xED,0x4A,0x6D, ++0x57,0x58,0x8F,0x97,0xB8,0x14,0x4C,0x21, ++0x37,0x26,0x8E,0x20,0xB8,0xED,0x48,0x6D, ++0xCC,0xB1,0x31,0x54,0xBA,0xE4,0x4F,0xDD, ++0xFB,0x58,0x8A,0x08,0x48,0x78,0x4E,0x24, ++0x03,0x42,0x87,0xFB,0x41,0x22,0x4E,0xBD, ++0x33,0x66,0x2F,0x5B,0xB8,0x85,0x63,0x54, ++0x31,0x76,0x2F,0x59,0xBA,0x05,0xEE,0x5C, ++0x31,0xA6,0x2F,0x59,0x98,0xD5,0x1F,0x5F, ++0x3F,0x16,0x2F,0x90,0xB4,0x95,0xEE,0x95, ++0x13,0x56,0xDE,0x9A,0x43,0x3A,0xB1,0x97, ++0x32,0x58,0x3F,0x59,0xB4,0x95,0xEE,0x95, ++0x3F,0x46,0x2F,0xF0,0xB8,0x85,0xF3,0x55, ++0x32,0x57,0x3F,0x59,0xBC,0xE5,0xCE,0x99, ++0x2D,0xB9,0xA0,0xB9,0x0A,0xE5,0x8E,0xFD, ++0x32,0x47,0x9E,0x5B,0xB9,0xE5,0x8E,0xA9, ++0x2D,0xB9,0xA0,0x59,0x48,0x84,0x63,0x54, ++0x13,0x66,0xDD,0x5A,0xB3,0xC5,0x4E,0x87, ++0xB3,0x46,0xDD,0x5B,0xBD,0xC5,0x4E,0x87, ++0xB3,0xB6,0x5E,0x4D,0x40,0x94,0xFF,0x55, ++0x13,0x66,0xCD,0x5A,0x38,0xC5,0x1C,0x5E, ++0xCB,0x17,0x2F,0x50,0x41,0x3A,0xB1,0x97, ++0xCB,0x17,0x3E,0x50,0x98,0xE5,0x1C,0x5F, ++0xCB,0x17,0x2F,0x50,0x43,0x3A,0xB1,0x97, ++0x31,0x88,0x3F,0x59,0xA0,0x95,0xFF,0x95, ++0x2B,0x16,0x2F,0x90,0xA0,0xC5,0xFF,0xF5, ++0x2B,0x46,0x2F,0xF0,0x48,0x84,0xF3,0x55, ++0x31,0x89,0x3F,0x59,0xBC,0xF5,0xDF,0x99, ++0x37,0x76,0x0F,0x9C,0xA6,0x3A,0x61,0xBC, ++0xB1,0x69,0x3F,0x59,0x0A,0xF5,0x9F,0x9D, ++0x32,0x66,0x5E,0xFC,0x0A,0xF5,0x8E,0x9D, ++0x45,0x11,0x38,0x8B,0xD1,0x4D,0x16,0x2B, ++0x44,0x31,0x67,0x2A,0xD1,0x4D,0x16,0x2B, ++0x64,0x9E,0xFA,0xEF,0xC8,0xF2,0x14,0x23, ++0x46,0x31,0x48,0x2C,0xDA,0xB0,0x39,0x30, ++0x43,0xB1,0x45,0x27,0xCB,0xB2,0xA6,0x2F, ++0x5A,0xCE,0xD7,0x2E,0xD1,0x4D,0x16,0x2B, ++0x04,0x9E,0xFA,0xEF,0xFF,0xF2,0x14,0x23, ++0x4E,0x11,0xA8,0x2D,0xEF,0x53,0x99,0x2B, ++0x44,0x01,0x29,0x2D,0xCE,0x5D,0xB7,0x2B, ++0x4A,0x31,0xA8,0x2F,0xEE,0xA3,0xF8,0x2A, ++0x64,0xD3,0x58,0x2E,0xCE,0x5C,0xB7,0x2B, ++0x4A,0x31,0x68,0x2F,0xEE,0xA0,0x98,0x2A, ++0x64,0xD5,0x58,0x2E,0xCE,0x5E,0xB7,0x2B, ++0x4A,0x31,0x68,0x2F,0xEE,0xA6,0x98,0x2A, ++0x64,0xD9,0x58,0x2E,0xCE,0x5A,0xB7,0x2B, ++0x4A,0x31,0x68,0x2F,0xEE,0xAA,0x98,0x2A, ++0x89,0xFD,0xA4,0xE3,0x03,0x6E,0x54,0xE4, ++0x28,0xFC,0x94,0xE2,0x82,0x70,0x75,0xE7, ++0x29,0xEC,0x94,0xE2,0x03,0x2F,0x65,0xE6, ++0x89,0xBC,0x94,0xE2,0x23,0x31,0x71,0xE7, ++0x89,0xBD,0x90,0xE3,0x06,0x2E,0x60,0xE6, ++0x8C,0xBD,0x90,0xE3,0x06,0x5E,0xA7,0xE6, ++0x8C,0xCD,0xE7,0xE3,0x03,0x4E,0x55,0xE5, ++0x82,0xDD,0xB6,0x41,0x33,0xFE,0x48,0x4E, ++0x89,0xFD,0xA4,0xE1,0x03,0x6E,0x54,0xE4, ++0xB8,0x7D,0x89,0xEB,0xFC,0xCB,0xF1,0x06, ++0x09,0x4D,0x10,0x33,0x0E,0x7E,0xF5,0x96, ++0xA9,0x95,0xBC,0x05,0x07,0xAB,0xE5,0x24, ++0x68,0x94,0xA5,0x40,0x22,0x1E,0xF5,0xE6, ++0x89,0xDD,0x34,0x24,0xAB,0x3C,0xF5,0xDB, ++0xCF,0xE6,0x30,0x9B,0xA2,0x17,0x8F,0x1F, ++0x98,0xE5,0x3C,0x19,0xA3,0x1F,0xD5,0x6E, ++0xA6,0x15,0xD8,0x39,0xCD,0x90,0xE4,0x1F, ++0xB5,0xE8,0xDA,0xCB,0xE5,0x70,0x18,0x70, ++0x04,0x7B,0x7B,0x85,0x6D,0xCD,0x8B,0xAF, ++0x46,0x79,0x9A,0xF1,0x9B,0x8C,0x3B,0x8A, ++0x62,0x8B,0x5C,0xAF,0x1E,0x4B,0x3B,0x80, ++0xA6,0x15,0xD0,0x38,0xCD,0x90,0xE4,0x1F, ++0xD9,0xE8,0xDC,0x0D,0x8F,0xF8,0xBA,0x80, ++0x56,0x33,0x4A,0xAA,0xCD,0xFA,0x5B,0xF4, ++0x46,0x71,0xE2,0xED,0x92,0x8E,0x1B,0xC0, ++0x92,0xCF,0xDD,0x0D,0xED,0x08,0x79,0x80, ++0xC7,0x7B,0x9A,0xB0,0x7D,0xD7,0x3B,0x82, ++0x26,0x0F,0xFA,0x8F,0xC5,0x90,0x76,0xF6, ++0x66,0x3B,0x29,0x31,0xCD,0x90,0xE4,0x1F, ++0xDE,0xE8,0xFB,0x85,0xEF,0xB0,0x12,0xEE, ++0x66,0xC7,0xDB,0xCD,0xE8,0x20,0xEB,0x55, ++0x16,0x54,0x25,0x58,0xE1,0x90,0x94,0x58, ++0x50,0x1D,0xAD,0xE3,0x82,0x66,0x3B,0x8E, ++0x08,0xE4,0xC9,0x86,0x8B,0x27,0x10,0x90, ++0x00,0x54,0xB4,0x8B,0x8A,0x06,0x3D,0x66, ++0x03,0x54,0xB5,0x11,0x02,0xF3,0x75,0xCE, ++0x00,0x5F,0xBF,0x51,0x09,0xF6,0xFD,0x96, ++0x40,0x7D,0xB4,0xCB,0x0B,0xFB,0x7C,0xA6, ++0x0A,0xE5,0xBE,0x56,0x8B,0xD6,0xBD,0xCD, ++0x0A,0xE5,0xB4,0x13,0x8D,0xB5,0x64,0x5F, ++0x18,0xED,0xBD,0xA3,0x88,0x27,0x6F,0x17, ++0x00,0x55,0x76,0xC8,0x82,0x16,0x7D,0xAE, ++0x30,0x54,0xBD,0x6B,0xAA,0xA2,0x3D,0x92, ++0x12,0xEF,0x2C,0xC9,0x71,0x2D,0x6D,0x8E, ++0x00,0x57,0xA4,0x10,0x8B,0xD7,0x5C,0xDA, ++0x0F,0xEC,0x37,0xEB,0x81,0x96,0x35,0xEE, ++0x13,0xC5,0x4C,0x36,0x7B,0xBE,0x8C,0xC7, ++0x28,0x6D,0xF4,0xC8,0x8B,0xE2,0x71,0x1E, ++0x0A,0xED,0xFC,0xC9,0x86,0x66,0x65,0x16, ++0x00,0x5D,0xB8,0x5A,0x99,0x6F,0x71,0x16, ++0x45,0x6F,0xD1,0x97,0x8A,0x16,0x6F,0x16, ++0x45,0x37,0xB1,0x11,0x8B,0xDB,0x7D,0x52, ++0x0A,0xEF,0x95,0x95,0x8B,0x2C,0x14,0xCC, ++0x03,0xDD,0xBC,0x7B,0x36,0x0C,0x75,0x17, ++0x09,0xED,0xBC,0x7B,0x0D,0x1D,0x7C,0x1F, ++0x01,0x75,0x5D,0xC3,0x89,0x64,0x74,0x96, ++0x00,0x58,0xBC,0x1A,0x81,0x2B,0xA3,0xC7, ++0x03,0xED,0xB6,0x11,0xC2,0xB4,0x3D,0x96, ++0x03,0xDC,0xBF,0x1B,0xE3,0xB0,0x7D,0x7E, ++0x00,0x9B,0xBB,0x6B,0x88,0x6F,0x77,0x14, ++0x08,0x6D,0xBF,0x22,0x88,0x66,0x15,0xC8, ++0x00,0x85,0xB2,0x65,0x8B,0x66,0x7D,0x8A, ++0x02,0xE7,0xBD,0x1A,0x88,0x26,0x7D,0xAB, ++0xED,0x36,0xD2,0x83,0x8A,0x16,0x73,0x8E, ++0x8C,0xEC,0x3D,0x8A,0x12,0x47,0xC2,0xC6, ++0x8B,0x73,0x22,0xF2,0x23,0x6F,0xCC,0x17, ++0x66,0x1B,0xF5,0xFC,0x22,0x5D,0xE1,0x17, ++0x97,0xEC,0xC7,0x47,0x6D,0x71,0x11,0xC2, ++0x8B,0x74,0x25,0x31,0x23,0x6F,0xE3,0x87, ++0xB1,0xEC,0x24,0x35,0x4B,0x2F,0xBC,0x57, ++0x91,0xAF,0x26,0xC2,0x1E,0xF7,0xE4,0x30, ++0xD9,0xF0,0x22,0xF2,0x32,0x17,0xD4,0x3F, ++0x98,0x3C,0x29,0x8A,0x11,0x8F,0xE8,0x8F, ++0x99,0xCB,0x65,0x0C,0x1E,0xFF,0xE4,0x38, ++0x9F,0x7C,0xBD,0xC2,0x27,0x8F,0xE4,0x37, ++0x9E,0xEC,0x2E,0x82,0x18,0x8F,0xF5,0x38, ++0x96,0x36,0x14,0x12,0x3A,0x6F,0x1B,0xE0, ++0x3F,0x02,0x15,0x20,0x17,0x6F,0xEA,0x17, ++0x7B,0xB9,0x5A,0x0E,0x12,0x4C,0xD5,0x17, ++0xB1,0xEC,0x7C,0x52,0x4A,0x2F,0xEC,0x54, ++0xCF,0x86,0x9E,0x8A,0x98,0xD4,0x77,0xAC, ++0x7B,0x17,0xC6,0xE9,0xA1,0x97,0x4F,0x7D, ++0x22,0x76,0xA6,0xA9,0xAD,0x34,0x7C,0xF0, ++0x40,0x0B,0xFD,0xFD,0xE0,0xC8,0x7D,0xF8, ++0x62,0x49,0x1F,0xEB,0x5E,0x0F,0x4D,0x34, ++0x25,0xC0,0xA6,0xB3,0xE9,0xCA,0x59,0x3C, ++0x25,0xB7,0x95,0x31,0xA9,0xFC,0x5B,0x7D, ++0x33,0x77,0x8C,0x39,0xA9,0xF4,0x47,0x3C, ++0x43,0xB0,0x99,0x33,0xB1,0x4D,0x5F,0x8C, ++0x82,0x03,0x91,0x31,0x28,0xB4,0x58,0x35, ++0x63,0x37,0x98,0x30,0xA8,0xB4,0x14,0x4B, ++0xD2,0xE2,0x4C,0xB4,0xAD,0xD4,0x8F,0xA4, ++0x2F,0x57,0x5E,0xA9,0x3C,0x64,0x5E,0xC4, ++0x62,0x3F,0x9C,0x38,0xA8,0xD4,0x5C,0x3C, ++0x20,0xCF,0x9E,0x59,0x59,0x3A,0x5D,0xAC, ++0x21,0xCF,0x5F,0xA6,0x84,0xF4,0x5F,0x85, ++0x17,0xB5,0x8C,0xF2,0xB1,0xC7,0xE7,0x98, ++0x13,0xB0,0xE5,0x9D,0x5A,0xE8,0x2C,0x9E, ++0x12,0x4E,0xAA,0x0A,0x9B,0x37,0x6B,0xB5, ++0x14,0xBF,0xAE,0x9A,0xB3,0xE7,0x4C,0x9F, ++0x11,0x94,0x6D,0x63,0x9F,0x06,0x4C,0xF7, ++0x91,0x62,0xAC,0x4F,0x7D,0x8E,0x6C,0x7F, ++0x17,0x43,0x85,0x9A,0x8B,0xC4,0x09,0xB2, ++0x0A,0xB4,0xCB,0xB2,0xBC,0x37,0x0B,0xB7, ++0x70,0xB5,0xAC,0xB5,0x9A,0x3D,0x6D,0xB8, ++0x11,0x46,0xBC,0xB5,0x9A,0x75,0x6C,0x43, ++0x2A,0x64,0xAF,0x30,0x90,0x4E,0x7E,0x37, ++0xEE,0x93,0x62,0x64,0xBA,0x8F,0x6C,0xB9, ++0x2C,0x64,0xAD,0x9D,0xAF,0x33,0x7F,0x07, ++0xB9,0x26,0xAD,0x40,0x9F,0xE7,0x66,0x37, ++0x39,0x84,0xAD,0xB8,0x8B,0xC8,0x6C,0x0D, ++0x11,0xBE,0xD6,0x86,0x98,0x4D,0x66,0x36, ++0xDE,0x11,0x8F,0xB0,0xFD,0xC4,0xB1,0x64, ++0xB1,0xA5,0x57,0xA7,0x46,0x1A,0xB0,0x60, ++0x0C,0xBE,0x70,0xD5,0x43,0xAA,0x8A,0x42, ++0xCE,0x13,0x7A,0xEE,0x55,0x92,0x4E,0xB5, ++0x60,0x47,0x64,0xDF,0x54,0xA7,0xB1,0x64, ++0xCC,0x91,0x72,0x96,0x55,0xA3,0xC9,0x5E, ++0xC1,0xA1,0x08,0x5C,0x45,0xEE,0xF7,0x00, ++0xBA,0xA7,0x0D,0x5B,0xAF,0x21,0xB4,0xD2, ++0xED,0x59,0x1D,0x59,0x46,0x17,0xB5,0x9F, ++0x8D,0xA0,0x50,0x7E,0x8E,0x45,0x81,0x6B, ++0x3B,0x69,0x62,0xDF,0xFF,0x78,0xB0,0x98, ++0xCD,0xA4,0x73,0x9D,0x46,0x1A,0xB4,0xD2, ++0xDE,0x21,0x7F,0xA7,0x47,0x12,0xB3,0x9E, ++0x4A,0xA0,0x5D,0x5D,0x43,0xDA,0xF1,0x5E, ++0x64,0xFB,0x71,0x9A,0x55,0xA7,0xDC,0x5E, ++0xDE,0x21,0xF0,0x5C,0x07,0x26,0xB4,0xD2, ++0xAB,0xFF,0xD6,0x26,0x25,0xCC,0xF7,0x4C, ++0xAA,0xD8,0x13,0xF5,0x24,0xC4,0x7F,0x66, ++0xA8,0x04,0x16,0x01,0xE1,0x1F,0xD2,0xB4, ++0xA2,0x74,0x16,0x01,0xF9,0x2D,0xD3,0xBC, ++0xAB,0xFE,0x1F,0x8E,0x22,0x6B,0x1E,0x23, ++0x22,0x9D,0x32,0xF1,0x23,0x7C,0xD6,0xB4, ++0x81,0xFF,0x16,0xB1,0x25,0xC4,0xD7,0x0C, ++0xA1,0x05,0x56,0x63,0x25,0xCC,0xFA,0x04, ++0xAA,0x4F,0x10,0xC1,0x25,0xC4,0xD7,0xD4, ++0x42,0x37,0x26,0x10,0x5E,0x42,0xD3,0xB4, ++0x93,0xAF,0x17,0xB9,0x60,0x42,0xD7,0x0C, ++0xAB,0x4E,0xE5,0xFD,0x25,0xC4,0xD7,0x0C, ++0x5A,0x0E,0x16,0xB9,0x5E,0x42,0xEF,0x54, ++0x8B,0xB7,0x53,0x01,0x28,0x59,0xD7,0xF0, ++0xCF,0xFF,0x69,0x3F,0x19,0x2C,0xDF,0x8C, ++0x6A,0xC4,0xD6,0x3C,0x27,0xCC,0xD0,0xBC, ++0xEE,0xB3,0x52,0xB5,0x64,0x38,0xD2,0x79, ++0xEB,0x03,0x92,0x72,0x6C,0x00,0x95,0xF8, ++0xE6,0x83,0xF3,0x0C,0x6D,0x02,0xD3,0x7E, ++0x4E,0xFA,0x72,0x0D,0xA5,0x1E,0x91,0xB4, ++0xCE,0x9B,0xAD,0x92,0xA0,0xE1,0x94,0xF8, ++0xEE,0xB3,0x57,0xB5,0x07,0x70,0x32,0x08, ++0x7E,0xDC,0x72,0x0F,0x25,0x04,0xB3,0x02, ++0xCE,0xF3,0x92,0x63,0x41,0xCD,0xB3,0x60, ++0x11,0x6C,0xE4,0x9C,0x45,0xF8,0x93,0x4E, ++0xE9,0x40,0x41,0xFD,0xD5,0x5A,0x97,0xBD, ++0xE4,0x33,0x30,0x0D,0xE5,0x45,0x32,0x08, ++0xEC,0x7B,0x30,0x0D,0xC4,0x70,0xA3,0x40, ++0x7E,0xDC,0x72,0x0F,0x13,0x04,0xD3,0x7C, ++0xCE,0xF9,0x57,0xFD,0x25,0x06,0x96,0xF0, ++0xE4,0x4A,0xAD,0x92,0x3D,0xF5,0x53,0x08, ++0x8C,0xF3,0x53,0x0D,0x25,0x44,0x32,0x08, ++0xB2,0x10,0xBE,0xC3,0xE9,0xC8,0x7F,0xCE, ++0x0A,0x57,0xF3,0xB7,0xA9,0xFC,0x85,0x70, ++0x25,0xB7,0xFC,0xC1,0x91,0xAC,0xFE,0xC4, ++0x5D,0x4B,0x0E,0xEE,0x89,0xBE,0x1F,0xB0, ++0x02,0x35,0x98,0x31,0xE8,0xCA,0x5F,0x84, ++0x24,0xC6,0x6C,0x75,0x89,0xD4,0xA0,0x5B, ++0xB6,0xAE,0x8B,0x19,0xAB,0xF4,0xAF,0x11, ++0x23,0xAB,0x61,0x56,0xB9,0x99,0x5F,0xAC, ++0xC3,0x88,0x61,0x56,0xBE,0x14,0xD0,0x4E, ++0x3E,0xA8,0xB1,0x48,0xB9,0x61,0x1C,0xC5, ++0x22,0x7C,0x9C,0x79,0x06,0x27,0x5F,0x2C, ++0x23,0xB7,0x61,0x5E,0x0C,0x2D,0x5E,0x8C, ++0x32,0xEA,0x8C,0xC1,0xA8,0xD4,0x7B,0x9D, ++0x28,0x27,0x9E,0x8B,0xE3,0xA4,0x5E,0x8E, ++0xCE,0xB0,0x8F,0xC1,0xA9,0xF6,0x8D,0xEF, ++0xCA,0xB0,0x9E,0xA9,0xBE,0x14,0xD0,0x4E, ++0x94,0x02,0x1B,0xE2,0x13,0xCB,0xB6,0x6F, ++0x88,0xD6,0x36,0xD3,0xAC,0x8D,0xF5,0x86, ++0x89,0x1D,0xCB,0xF4,0x28,0x84,0xF4,0x26, ++0x98,0x40,0x26,0x6B,0x02,0x7E,0xD1,0x37, ++0x0A,0x79,0x34,0x21,0xC1,0xFA,0xF4,0x24, ++0x64,0x1A,0x25,0x6B,0x03,0x5C,0x27,0x45, ++0x60,0x1A,0x0E,0x2B,0x03,0xAC,0xC5,0x3E, ++0xA8,0xDE,0x36,0x03,0x99,0x3D,0xB4,0x2C, ++0x89,0x2E,0x24,0x03,0x34,0x46,0xF5,0x24, ++0x5A,0xBE,0xBC,0x41,0x03,0xAC,0xF7,0x06, ++0x98,0xFD,0x44,0x44,0x73,0xCB,0xF0,0x06, ++0x84,0xFD,0x22,0x03,0xFC,0x89,0xE1,0xEF, ++0x88,0x95,0xCB,0x22,0x01,0x4F,0xFC,0x5A, ++0x89,0xD4,0x3E,0xD2,0xFC,0x5F,0xFD,0x37, ++0xBA,0xFD,0x3D,0x5B,0x40,0x66,0x0A,0x35, ++0x80,0xCE,0x15,0x03,0x2B,0x7E,0x6D,0x41, ++0xCB,0x73,0xF8,0x1C,0x35,0x95,0xC6,0x68, ++0xBB,0xE6,0x05,0xE0,0x31,0x6D,0xEA,0x45, ++0xCB,0x73,0x07,0x10,0xF0,0x0E,0xB6,0x88, ++0xB1,0xDE,0x47,0xD2,0x10,0x4C,0x86,0xD5, ++0x9B,0xCC,0x87,0xD0,0x10,0x49,0x46,0xD5, ++0x9B,0xC6,0x87,0xD0,0x90,0x4C,0x66,0xD4, ++0xBB,0xEF,0x87,0xD0,0xB2,0x5D,0x97,0xD5, ++0xBA,0xCE,0x87,0x62,0x3A,0x5D,0x47,0x77, ++0xA5,0x31,0x28,0xD1,0x3E,0x1D,0x66,0xD4, ++0xF5,0x30,0xF8,0xDB,0x35,0xAD,0x66,0xD4, ++0xBB,0x9E,0xB7,0xD1,0x3D,0x5D,0x66,0xD4, ++0xB1,0xFE,0xA7,0xD1,0x37,0x4D,0x06,0xD6, ++0xBB,0x1E,0xA7,0xD1,0x50,0x9D,0x4B,0xD7, ++0x9B,0x8E,0x2A,0xD9,0x3A,0xB9,0x39,0xDE, ++0x9B,0x8E,0xBA,0xD8,0x30,0x2D,0x66,0xD6, ++0xBB,0xBE,0xA7,0xD3,0x30,0xCD,0x66,0xD6, ++0xAA,0x6F,0xB6,0xC2,0x26,0x4C,0x16,0xC7, ++0xAF,0x1F,0xB6,0xC0,0xE1,0x55,0x7B,0xCC, ++0x6A,0xD6,0xBA,0xC9,0xE1,0x55,0x7B,0xCC, ++0x6A,0xD6,0xBA,0xC9,0x20,0x8C,0x77,0xC5, ++0xB4,0x20,0x39,0xC0,0xD9,0xE9,0xD3,0x24, ++0xAB,0xB7,0x17,0x01,0x3E,0x5C,0x17,0x26, ++0xA9,0xF9,0x1E,0x61,0x26,0x76,0xD3,0xFF, ++0xAA,0xF7,0x01,0x84,0x24,0x8D,0xC0,0x81, ++0xA9,0x3F,0x16,0x09,0x37,0xF9,0xD7,0xF5, ++0xBC,0x7A,0x06,0x01,0xA0,0x1F,0xF6,0x44, ++0x0A,0xB6,0xD6,0x3F,0x21,0x73,0x77,0x45, ++0xAB,0x0F,0x56,0x3F,0x81,0x3D,0xF7,0x24, ++0x55,0x28,0xB0,0xD9,0x21,0x73,0xD6,0xF5, ++0x8A,0xB5,0x10,0xC1,0x43,0x34,0x76,0x4C, ++0x92,0xDF,0x86,0x66,0x01,0x36,0x97,0x38, ++0x8A,0xBD,0xD6,0x3D,0x01,0x3E,0xD3,0xC4, ++0x51,0x2E,0xA7,0xC0,0x19,0xAD,0x23,0xA1, ++0xA3,0x01,0xF9,0xA6,0x40,0x17,0x6E,0xBD, ++0xCC,0xB1,0x2C,0x40,0x40,0x78,0x4E,0xBD, ++0x7D,0x07,0xC1,0xB8,0xD6,0xA4,0x20,0xBD, ++0x7A,0x08,0xC9,0xB8,0xD1,0xAB,0x28,0xBD, ++0xC4,0xF3,0x87,0xB8,0xAF,0xC5,0x60,0xF4, ++0xB9,0xF6,0xF6,0xFC,0xBE,0x69,0x62,0x74, ++0x1F,0x82,0xA3,0x71,0x8F,0xE4,0x4D,0x11, ++0xFA,0x47,0xCF,0xA0,0x94,0x01,0x79,0x9C, ++0x28,0x76,0x71,0x4F,0x24,0x2A,0x4B,0xBD, ++0xB3,0x7B,0x83,0xB8,0xA3,0xF9,0x4C,0x68, ++0x57,0x04,0x8E,0x98,0xB8,0x25,0x4E,0x9D, ++0x33,0x60,0x86,0x28,0xB7,0x25,0xAE,0xBA, ++0x38,0x96,0x83,0x98,0xA6,0x8C,0x3E,0xFE, ++0x4A,0x02,0x35,0x81,0xF9,0xDD,0x74,0xBD, ++0x35,0xEE,0x8F,0x48,0xFE,0x2E,0x48,0x16, ++0xDA,0x6B,0x05,0x46,0x20,0x37,0xA0,0x7F, ++0x30,0x79,0x0F,0x10,0x4E,0xCB,0x48,0x54, ++0xC9,0x78,0x74,0x1E,0x77,0x2A,0xD8,0x17, ++0x79,0x90,0x69,0x4E,0x58,0xE3,0xAE,0x95, ++0xDD,0xC0,0x6D,0x68,0xAE,0x69,0xA2,0x82, ++0xDF,0x30,0xA1,0x4F,0x54,0xBB,0xC9,0x15, ++0xE7,0xA8,0x62,0xFE,0x56,0xDB,0x88,0xB8, ++0xDE,0x03,0x66,0x95,0x3B,0x3B,0xC4,0x4F, ++0xDD,0x85,0x85,0x87,0x5F,0xB3,0xA0,0x7B, ++0xD8,0x78,0x5B,0x56,0x50,0x82,0xA3,0xFB, ++0xDD,0x58,0x63,0xBD,0x52,0xCB,0x9A,0x53, ++0xDB,0x01,0x62,0xFE,0x56,0xDB,0xB4,0xB8, ++0xD7,0x33,0x66,0x95,0x5B,0x9B,0x50,0xEE, ++0xEB,0xA3,0x61,0x56,0x52,0x2B,0x0F,0xA0, ++0xDD,0x28,0x41,0x56,0xAA,0xDC,0xEC,0xBC, ++0xDC,0xA8,0x71,0xE3,0x54,0x0B,0xA0,0xA3, ++0xC6,0x11,0x24,0xBE,0x00,0x7E,0xE5,0xE5, ++0x8B,0xFD,0x25,0x00,0x14,0x7E,0xF5,0x1C, ++0x88,0xBD,0x19,0xEA,0x87,0x9E,0x6A,0xE3, ++0x8C,0xDD,0xA4,0xE7,0x07,0x4E,0x64,0xE2, ++0x86,0x3D,0x76,0xE3,0x01,0xBE,0x39,0xE7, ++0x06,0x3E,0x28,0xE3,0x00,0x7E,0xA7,0x07, ++0x70,0x02,0xCB,0x09,0x03,0x3E,0x48,0xEE, ++0x8B,0xF1,0x94,0xE2,0x01,0x72,0xA5,0xE6, ++0x77,0xF3,0x28,0x00,0x04,0x7E,0xF5,0x1C, ++0x8B,0xF5,0x94,0xE2,0x01,0x76,0xA5,0xE6, ++0x77,0xF1,0x28,0x00,0x00,0x7E,0xF5,0x1C, ++0x8B,0xF9,0x94,0xE2,0x01,0x7A,0xA5,0xE6, ++0x77,0xF5,0x28,0x00,0x01,0x7E,0xA6,0x06, ++0xE8,0xFD,0x94,0x12,0x1D,0x81,0xDA,0xE7, ++0x89,0xDD,0xE4,0xE7,0x02,0x4E,0x24,0xE2, ++0x89,0xFD,0x66,0xE0,0x00,0x7E,0xA7,0x27, ++0xFB,0x8A,0x43,0x6E,0x75,0x29,0x52,0x95, ++0xFE,0xBA,0x92,0x90,0x75,0x09,0xD0,0x92, ++0xFC,0x8A,0x11,0x55,0x81,0xF6,0x7D,0x7B, ++0xFC,0x8A,0x01,0x94,0x6A,0xF6,0xAD,0x90, ++0xFE,0x8B,0x42,0x75,0x74,0x29,0x32,0x92, ++0xDF,0xB8,0x32,0x94,0xFF,0xF2,0x7D,0x4B, ++0xDF,0xBE,0x32,0x94,0x09,0xF2,0x7D,0x4B, ++0xFF,0x4A,0xE3,0x97,0xE8,0xF2,0x7D,0x9B, ++0x7F,0x4A,0xF3,0x95,0x74,0x09,0xB3,0x72, ++0xD3,0x80,0xE3,0x95,0x78,0x3C,0x22,0x90, ++0x7E,0xAF,0xE3,0x95,0x6A,0x02,0x02,0x63, ++0x5E,0x90,0xC0,0x95,0x14,0x09,0x22,0x90, ++0xFD,0x9B,0xC2,0x67,0xB8,0xC3,0x32,0x90, ++0xE8,0x8A,0x43,0x7E,0x75,0x09,0xFE,0x92, ++0xFE,0x8B,0xC3,0x77,0x6A,0xF6,0xAD,0x90, ++0xDD,0xB2,0xF3,0x95,0x76,0x21,0x22,0x70, ++0x10,0xB5,0x1C,0x88,0x8B,0x36,0xDD,0x9D, ++0x1F,0x75,0xFC,0x69,0xA9,0xCA,0xCD,0x6F, ++0x02,0x51,0x1C,0x8A,0x83,0x36,0xF1,0x8C, ++0x22,0x4B,0x0C,0x6A,0x89,0xD4,0xDD,0x8F, ++0x04,0xB5,0x30,0x89,0xA9,0xC9,0xCD,0x6F, ++0x02,0x54,0x1C,0x8A,0x89,0x36,0xF1,0x8C, ++0xA2,0x4A,0x0C,0x6A,0x09,0xD6,0xDD,0x8F, ++0x01,0xB5,0x30,0x89,0x89,0xE6,0xDD,0x6F, ++0x00,0x55,0x1C,0x68,0x87,0xF6,0x3D,0x6E, ++0x1E,0x8A,0x93,0x6A,0x89,0xF7,0x6C,0x6D, ++0x1E,0x8A,0x93,0x8A,0x89,0xE7,0xAC,0x6D, ++0xE6,0x8A,0x43,0x81,0xAA,0xCE,0xCD,0x6F, ++0x01,0x6D,0x1C,0x8A,0x9B,0x36,0xDD,0x8D, ++0x00,0xB5,0x1C,0x98,0xAA,0xCA,0xCD,0x6F, ++0x01,0x61,0x1C,0x8A,0x83,0x36,0xF1,0x8C, ++0x21,0x4B,0x0C,0x6A,0x8A,0xE4,0xDD,0x8F, ++0x9D,0x2C,0xA9,0x10,0x33,0x50,0x54,0xF6, ++0x98,0xFD,0x85,0x13,0x10,0xAF,0x68,0x15, ++0x38,0xD3,0x95,0xF3,0x13,0xAF,0x68,0x15, ++0xB9,0xDC,0x49,0xF0,0x93,0x7F,0x44,0x16, ++0xAB,0xFF,0xA4,0xF3,0x00,0x43,0x44,0xF6, ++0x95,0xEC,0x65,0xF2,0x13,0x6F,0x64,0xF5, ++0x87,0x13,0x0A,0xF3,0xED,0xAB,0x24,0xF4, ++0x9A,0xEC,0x05,0xF2,0xED,0x1B,0x27,0xF4, ++0x9E,0xDC,0x69,0xF2,0x2D,0x53,0x67,0xF5, ++0x9B,0xED,0x25,0xF0,0xED,0x5F,0x67,0xF5, ++0x19,0xA5,0x08,0xFB,0x30,0x01,0x6B,0xF5, ++0x90,0xEC,0x08,0xFB,0x36,0x57,0x44,0xF6, ++0xBC,0x54,0x85,0xF3,0x31,0x0B,0x32,0xF0, ++0x92,0x04,0xE0,0xF3,0x11,0xE7,0x20,0xF6, ++0x38,0xFC,0x95,0xF3,0x81,0x09,0xC3,0xF7, ++0xFB,0xCC,0x95,0xF3,0x10,0x6E,0x44,0x34, ++0x99,0xEC,0x85,0x21,0x10,0x1A,0x83,0xF5, ++0x0E,0xEA,0x23,0xF2,0xB6,0x19,0x44,0xF6, ++0x3F,0x85,0x85,0xF3,0x10,0x0F,0x62,0xF5, ++0x0E,0x8A,0x09,0xF2,0x10,0xAD,0x88,0xF5, ++0xB5,0x94,0x85,0xF3,0x15,0xA7,0x28,0xF6, ++0x0E,0xEA,0x21,0xF2,0x8E,0x69,0xE1,0xF7, ++0x38,0x9B,0x85,0xF3,0x37,0x07,0x60,0xF7, ++0xBF,0x8F,0x85,0xF3,0x84,0x68,0xE8,0xF7, ++0xB5,0x24,0x85,0xF3,0x8E,0x64,0xE3,0xF7, ++0x95,0xA4,0x85,0xF3,0x15,0x4F,0xB6,0xF7, ++0x0A,0xE0,0x22,0xF2,0x15,0x7F,0x25,0xF7, ++0x05,0xE2,0x22,0xF2,0x15,0x67,0xB4,0xF7, ++0xBE,0xC4,0xF7,0xF2,0x8E,0x67,0xE3,0xF7, ++0x9E,0xC4,0x67,0x22,0x15,0x47,0xB6,0x37, ++0xBE,0xF4,0xE4,0xF2,0x33,0x1E,0x44,0xF6, ++0x0F,0xEB,0x29,0xF2,0x3E,0xA7,0x44,0xF6, ++0x27,0xC5,0x00,0xD0,0xB7,0x44,0x96,0xD5, ++0x1C,0xE8,0xD5,0xD0,0xA3,0x41,0xC1,0xD5, ++0x3C,0xE7,0x45,0x00,0xB7,0x64,0x94,0x15, ++0x1C,0xD8,0xC6,0xD0,0xAC,0x43,0xC1,0xD5, ++0x37,0x8F,0x83,0xD0,0xB7,0x4C,0x96,0xD5, ++0x1C,0xE0,0xD5,0xD0,0xAC,0x45,0xC1,0xD5, ++0x3C,0xEF,0x45,0x00,0xB7,0x6C,0x94,0x15, ++0x1C,0xD0,0xC6,0xD0,0x3C,0x3D,0x5B,0xD0, ++0xBA,0xD3,0xA7,0xD1,0x12,0x5E,0x47,0xD4, ++0xB9,0xE3,0xA7,0xD1,0x91,0x3A,0x66,0xD4, ++0x9B,0xED,0x85,0xD1,0xA6,0x4A,0xCA,0xD5, ++0xBB,0xC3,0xA7,0xD1,0x1C,0x85,0x66,0xD4, ++0x27,0xC5,0x00,0xD0,0x3C,0x16,0x66,0xD4, ++0x97,0x8B,0x83,0xD0,0x37,0x6D,0x94,0xD5, ++0x28,0xC2,0x00,0xD0,0x37,0x5D,0x07,0xD5, ++0x27,0xC0,0x00,0xD0,0x37,0x45,0x96,0xD5, ++0x36,0x4C,0x7F,0x7A,0x06,0xEF,0x6B,0x7F, ++0x16,0x4C,0xEF,0xAA,0x9D,0xCF,0x3E,0xBF, ++0x36,0x7C,0x6C,0x7A,0xBB,0x96,0xCC,0x7E, ++0x87,0x63,0xA1,0x7A,0xB6,0x2F,0xCC,0x7E, ++0x8D,0x6F,0xAA,0x7A,0x1D,0xEE,0x3C,0x7F, ++0xB6,0x42,0x7F,0x7A,0x09,0xEB,0x6B,0x7F, ++0x96,0x4D,0xEF,0xAA,0x1D,0xCE,0x3E,0xBF, ++0xB6,0x72,0x6C,0x7A,0x06,0xE9,0x6B,0x7F, ++0x96,0x65,0xFD,0x7A,0x3D,0xC9,0xBE,0x7F, ++0x8D,0x6C,0xAA,0x7A,0x1D,0xC6,0x2E,0xAF, ++0x96,0x45,0xFF,0xBA,0x3D,0xF9,0xAD,0x7F, ++0x10,0x79,0x0D,0x7B,0xB8,0xF4,0xED,0x7E, ++0x9D,0x30,0x38,0x7A,0x3B,0x90,0xCC,0x7E, ++0x13,0x49,0x0D,0x7B,0x0C,0xE0,0x60,0x7F, ++0x31,0x47,0x2F,0x7B,0x9A,0xA7,0xC8,0x7D, ++0x11,0x69,0x0D,0x7B,0xB6,0x2F,0xCC,0x7E, ++0xD8,0x3A,0xFF,0x2F,0xC3,0xDC,0x99,0x2B, ++0x43,0x11,0xAA,0x2F,0x5C,0xBE,0x3E,0x2A, ++0x43,0x21,0x39,0x2F,0x53,0xBC,0x3E,0x2A, ++0x43,0x39,0xA8,0x2F,0xE8,0x9A,0xEB,0x2A, ++0xD8,0x39,0xFF,0x2F,0xC8,0x9A,0x7B,0xFA, ++0x43,0x19,0xAA,0xEF,0xE8,0xAA,0xF8,0x2A, ++0x68,0x63,0x6D,0x2F,0xCE,0xA5,0x99,0x2B, ++0x66,0x28,0x79,0x2E,0xCD,0x95,0x99,0x2B, ++0x64,0x18,0x7A,0x2E,0xCF,0xB5,0x99,0x2B, ++0x44,0x71,0x5C,0x2D,0xCC,0x8A,0xB1,0x2B, ++0x4F,0xB9,0x76,0x2E,0xCF,0x52,0x99,0x29, ++0x44,0x81,0x58,0x2C,0xC7,0x72,0x6B,0x2A, ++0x47,0x41,0x29,0x2F,0xC1,0x52,0x97,0x2A, ++0x48,0x11,0x58,0xEE,0xC8,0xA2,0x99,0xEB, ++0x44,0x31,0x68,0x2F,0xCD,0x92,0x8B,0x2A, ++0x45,0x21,0x49,0x2F,0xC4,0x02,0x92,0x2A, ++0xE6,0x5B,0x00,0x85,0x66,0x68,0x42,0x80, ++0xEE,0x2B,0x89,0x87,0x65,0xA8,0x33,0x83, ++0xE0,0x7B,0xFC,0x85,0x69,0x38,0x33,0x41, ++0xE9,0x8B,0xF2,0x44,0x65,0x18,0x03,0x80, ++0xEC,0xBB,0xE0,0x85,0x64,0x08,0x22,0x80, ++0xE5,0x2B,0xF9,0x85,0x6D,0xD8,0xC1,0x80, ++0xED,0xEB,0x83,0x85,0x65,0xA8,0x48,0x82, ++0xE2,0xBB,0xF2,0x44,0x62,0x08,0x33,0x41, ++0xE0,0x7B,0xFC,0x85,0x67,0x68,0x02,0x81, ++0xEF,0xFB,0xD4,0x76,0x6B,0x76,0x05,0x80, ++0xEE,0xBB,0xE7,0x87,0x65,0x08,0x27,0x82, ++0x67,0x9A,0xEF,0x2D,0x65,0x90,0x2E,0x28, ++0xE8,0xFB,0xC4,0x85,0xEC,0x19,0x2E,0x88, ++0xEC,0xBB,0xE0,0x85,0x65,0x50,0x2E,0x88, ++0xEF,0x8B,0xF3,0x85,0x64,0x28,0xD0,0x82, ++0xF0,0x64,0x7D,0x84,0xE5,0x98,0xEC,0x1E, ++0x1B,0x6F,0xA1,0x97,0x94,0xE8,0x6C,0x9E, ++0x10,0x66,0xAE,0x9E,0x9F,0xE1,0x6A,0x98, ++0x09,0x7D,0xB4,0x80,0x81,0xFC,0x70,0x82, ++0x0C,0x7A,0xB2,0x85,0x8A,0xF6,0x7D,0x8D, ++0x02,0x77,0xB9,0x8E,0x8F,0xF1,0x7A,0x88, ++0x06,0x4C,0x85,0xB3,0xB3,0xCD,0x46,0xB4, ++0x3A,0x48,0x81,0xB7,0xB7,0xC9,0x42,0xB0, ++0x3E,0x44,0x8D,0xBB,0xBB,0xC5,0x4E,0xBD, ++0x32,0x47,0x89,0xBE,0xBF,0xC2,0x49,0xB9, ++0x37,0x43,0x8A,0xBD,0xA2,0xDF,0x54,0xA6, ++0x28,0x5E,0x97,0xA0,0xA1,0xDC,0x57,0xA3, ++0x2D,0x58,0x90,0xA7,0xA7,0xD9,0x52,0xA1, ++0x2E,0x5B,0x92,0xAA,0xAA,0xD7,0x5C,0xAE, ++0x20,0x55,0x9F,0xA8,0xA8,0xD4,0x5F,0xAC, ++0x22,0x50,0x99,0xAE,0xAE,0xD2,0x59,0xAA, ++0x24,0x52,0x9B,0xAC,0xED,0x90,0x48,0x0B, ++0x70,0x13,0xDA,0xA7,0x6B,0xE0,0xAB,0x09, ++0x77,0x13,0xDA,0xE7,0xF1,0xD0,0x36,0x01, ++0x01,0x63,0x7A,0x0C,0xEE,0x90,0x36,0x01, ++0x76,0x13,0x7A,0x0E,0xFD,0x80,0xBB,0x0B, ++0x66,0x13,0x7A,0x0E,0xE2,0x90,0xA6,0x00, ++0x67,0xA3,0x51,0x0F,0xEC,0x90,0x40,0x0B, ++0x41,0x63,0x6A,0xEC,0xFD,0xD0,0xA6,0x00, ++0x67,0x33,0x48,0xCF,0xEC,0x80,0x8A,0xCA, ++0x64,0x02,0x7A,0xCE,0xED,0xA0,0xB8,0x0A, ++0x64,0x12,0xDA,0x0F,0xED,0x90,0x98,0x09, ++0x78,0xEC,0xF5,0x0C,0x16,0x6F,0xE4,0xD2, ++0xC4,0x63,0x6A,0x0C,0x07,0x6F,0xE4,0x02, ++0x60,0x7B,0x5C,0x0C,0xAD,0x90,0x68,0x0B, ++0x40,0x7B,0x7A,0x0C,0xE2,0x90,0x1B,0x32, ++0x46,0x13,0xA9,0x0E,0xEF,0xF0,0x9D,0x39, ++0x67,0x33,0x7A,0x3C,0xED,0x80,0xBB,0x3B, ++0x20,0x45,0x3F,0x59,0x8B,0xC6,0x0E,0x6C, ++0xDD,0x8A,0x43,0x81,0x8D,0x9E,0xFB,0x6F, ++0x20,0x05,0xDF,0x69,0xAD,0x9E,0xDD,0x6F, ++0x12,0x12,0x3A,0x6A,0xB9,0xD5,0xDD,0x6F, ++0x11,0x52,0x3E,0x6A,0xBA,0xE5,0xDD,0x6F, ++0x00,0x45,0x1C,0x68,0x5F,0x09,0x82,0x64, ++0x02,0x15,0x3A,0x6A,0x8B,0xC6,0xDD,0x6D, ++0x00,0x55,0x1C,0x68,0x8D,0x9E,0xFB,0x6F, ++0x26,0x1D,0x1C,0x6A,0x8A,0x96,0xFB,0x6F, ++0x00,0x65,0x1C,0x68,0x8D,0x9E,0xFB,0x3F, ++0x26,0x1D,0x1C,0x3A,0x41,0x09,0x82,0x64, ++0xC0,0x3D,0x91,0x62,0x89,0x46,0xDD,0x6F, ++0x30,0x75,0x91,0x62,0xB3,0xF6,0xEC,0x66, ++0x07,0x75,0x2C,0x63,0x0B,0x36,0xAC,0x6F, ++0x83,0xB5,0x68,0xCA,0x8A,0xF6,0x7D,0xD4, ++0xED,0x8B,0x43,0x60,0x35,0x09,0x82,0x65, ++0x0F,0x8A,0xFE,0x9C,0x74,0x81,0x3F,0x99, ++0x3F,0xC2,0x6E,0x9D,0x76,0xB9,0x22,0x90, ++0xCF,0x8A,0x6E,0x9D,0x4C,0x09,0x13,0x99, ++0xF8,0x8A,0xD3,0x9C,0x75,0x08,0x92,0x92, ++0xFE,0x8B,0x50,0x77,0x75,0x09,0x82,0x6B, ++0xFD,0x8A,0x43,0x9F,0xC6,0xF6,0x7D,0x9A, ++0x0F,0x8A,0xFE,0x9C,0x74,0x81,0x3F,0x99, ++0x00,0xFE,0x83,0x97,0x77,0x09,0xA2,0x91, ++0x00,0x4E,0x80,0x97,0x78,0x39,0x05,0x91, ++0xC0,0xB6,0x00,0x96,0x76,0x08,0x82,0x93, ++0x01,0xBA,0x00,0x96,0x74,0x09,0xB0,0x92, ++0xA2,0x8A,0x43,0x7E,0x74,0x09,0xB7,0x92, ++0xC2,0x8A,0x43,0x7E,0x75,0x40,0xAF,0x98, ++0xDE,0x82,0xE3,0x95,0x50,0x61,0x22,0x90, ++0xFF,0x02,0x82,0x95,0xE4,0x0F,0x8E,0x91, ++0xF9,0xF2,0x87,0x95,0xEC,0x0F,0x84,0x91, ++0xB5,0x5F,0x96,0x49,0x39,0xD3,0x58,0x4C, ++0x24,0xDF,0x06,0x49,0x8F,0x1C,0xF3,0x4C, ++0x00,0xEF,0x3E,0x48,0xAE,0x5C,0xC7,0x4C, ++0x07,0x3F,0x3E,0x48,0x8E,0xDC,0xF3,0x4C, ++0x29,0xBF,0x5C,0x48,0x32,0xD2,0x53,0x4C, ++0x24,0x2F,0x5B,0x48,0x37,0xD2,0x59,0x4C, ++0xB5,0x59,0x90,0x49,0x32,0xD3,0x58,0x4C, ++0x24,0xBF,0x00,0x49,0x8F,0x1C,0xF3,0x4C, ++0x22,0x37,0x3E,0x4A,0xAE,0x3C,0xC1,0x4C, ++0x05,0xEF,0x32,0x49,0xA2,0x54,0xC7,0x4C, ++0x22,0x57,0x3E,0x4B,0xA7,0x64,0xC7,0x4C, ++0x22,0xD7,0x26,0x49,0xA9,0xD4,0xFF,0x4E, ++0x20,0x27,0xCF,0x49,0xA9,0xC4,0xFF,0x4F, ++0x23,0x47,0x7E,0x98,0xAC,0xB4,0x1B,0x9C, ++0x26,0x97,0xCB,0xB9,0x8E,0x9C,0xFF,0x4D, ++0x22,0x47,0x3E,0xAA,0xAE,0xB4,0x19,0x9C, ++0x73,0x5A,0x0C,0x1D,0xD0,0xF9,0xAA,0x18, ++0x76,0x12,0x2B,0xCD,0x68,0xE6,0x28,0x19, ++0x70,0xCA,0x07,0x1D,0x69,0x86,0x0D,0x19, ++0xEB,0x07,0xCD,0x1C,0x68,0x8D,0x06,0x19, ++0x70,0x6A,0x5D,0x1C,0xDB,0xA9,0xA8,0x19, ++0x7B,0x6A,0x5D,0x1C,0xD0,0xA9,0xA8,0x19, ++0x71,0x62,0x50,0x1C,0xF2,0x60,0x84,0x18, ++0x75,0x22,0x73,0x1C,0xFD,0x91,0xBA,0x19, ++0x59,0x63,0x4D,0x1D,0xFD,0x08,0xB7,0xB1, ++0x71,0x62,0x5D,0x1C,0xFE,0xA1,0xB8,0x19, ++0x76,0x12,0x6A,0x1C,0xFD,0xB1,0x49,0x1B, ++0x76,0x8B,0x76,0x14,0xD8,0xD9,0xAA,0x18, ++0x56,0x7A,0x6B,0x1D,0xF9,0xE9,0xCE,0x18, ++0x70,0xCA,0x0A,0x1D,0x69,0x86,0x0E,0x19, ++0xE1,0x05,0xCC,0x1C,0x60,0x87,0x0B,0x19, ++0xE2,0x0E,0xC7,0x1C,0xFB,0x99,0x9B,0x19, ++0x72,0x68,0x4D,0x3E,0xFC,0xDB,0x88,0x3A, ++0x59,0x38,0x78,0x3E,0xF2,0xEB,0x8C,0x3B, ++0x52,0xE8,0x2B,0x3F,0x4B,0xA4,0x2A,0x3B, ++0xC3,0x27,0xEE,0x3E,0x42,0xA5,0x2E,0x3B, ++0xC0,0x2C,0xE5,0x3E,0xD9,0xCB,0xBE,0x3B, ++0x72,0x08,0x4B,0x3E,0xD2,0xCB,0xBE,0x3B, ++0x79,0x78,0x4B,0x3E,0xDF,0x83,0xBD,0x3B, ++0x55,0x30,0x5D,0x3C,0xC0,0x5C,0x07,0x9A, ++0x53,0x40,0x7F,0x3E,0xDC,0x83,0x9A,0x3B, ++0x54,0x30,0x48,0x3E,0xDF,0x93,0x6B,0x39, ++0x4B,0xDF,0xC6,0x3F,0xDE,0xA3,0x1D,0x38, ++0x48,0x20,0xE9,0xD4,0xFF,0x8B,0x88,0x3A, ++0x71,0x58,0x49,0x3F,0xDC,0xCB,0xE9,0x3A, ++0x52,0xE8,0x2D,0x3F,0x4C,0xA4,0x29,0x3B, ++0xC3,0x27,0xEE,0x3E,0x42,0xA5,0x2C,0x3B, ++0xC7,0x2C,0xE5,0x3E,0xD9,0xEB,0xBC,0x3B, ++0xEB,0xA1,0xD1,0xA7,0x62,0x42,0x11,0xA3, ++0xC0,0xF1,0xE4,0xA7,0x6B,0x22,0x10,0xA2, ++0xCB,0x71,0xB5,0xA6,0xD5,0x3D,0xB4,0xA2, ++0x5A,0xBE,0x77,0xA7,0xDB,0x3C,0xB7,0xA2, ++0x5E,0xB5,0x7C,0xA7,0x40,0x52,0x27,0xA2, ++0xEB,0xE1,0xD5,0xA7,0x4B,0x52,0x27,0xA2, ++0xE0,0x91,0xD5,0xA7,0x43,0x1A,0x23,0xA2, ++0xCC,0xA9,0xC1,0xA5,0x59,0xC5,0x9E,0x03, ++0xCA,0xD9,0xE6,0xA7,0x45,0x1A,0x03,0xA2, ++0xCD,0xA9,0xD1,0xA7,0x46,0x0A,0xF2,0xA0, ++0xD2,0x46,0x5F,0xA6,0x63,0x62,0x11,0xA3, ++0xED,0xC1,0xD0,0xA6,0x42,0x52,0x75,0xA3, ++0xCB,0x71,0xB1,0xA6,0xD2,0x3D,0xB0,0xA2, ++0x5A,0xBE,0x77,0xA7,0xDB,0x3C,0xB3,0xA2, ++0xCC,0xD9,0xD0,0xA4,0xD2,0x36,0xBD,0xA2, ++0xCB,0x91,0xE2,0xA7,0x60,0x22,0x10,0xA2, ++0x7B,0x2A,0x59,0x1C,0xD0,0x99,0xBB,0x19, ++0x69,0xFD,0xE4,0xBD,0xFE,0xA1,0x98,0x19, ++0x76,0x12,0x6A,0x1C,0xFD,0xB1,0x49,0x1B, ++0x69,0xFD,0xE4,0x1D,0xFC,0x41,0xAA,0x1A, ++0x6B,0xFD,0xE4,0x1D,0xF8,0x71,0x15,0x1C, ++0xEE,0x75,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0x7C,0x75,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0xC2,0x75,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0xBC,0x82,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0x74,0x83,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0x46,0x7C,0xC9,0xDC,0x7D,0x91,0xAA,0x18, ++0xF6,0x07,0x5B,0x1D,0xF8,0x81,0xAA,0xEA, ++0xD6,0x28,0x7B,0x1D,0xE8,0xA1,0x95,0x1C, ++0x76,0x02,0x4B,0xEF,0x5D,0x8B,0x58,0x18, ++0x75,0x02,0x4B,0xFF,0xFD,0x81,0x5A,0x1A, ++0x72,0x02,0x6B,0xFF,0xE2,0x7E,0x25,0x18, ++0xBB,0x36,0xF8,0xCF,0xDF,0xF2,0x14,0x23, ++0x44,0x31,0xA9,0x2C,0xC6,0xB2,0x39,0xC0, ++0x44,0x31,0x29,0x2A,0xCF,0xB2,0x69,0x29, ++0x42,0x31,0xF8,0xC5,0xEF,0xB2,0xA6,0x2F, ++0x44,0x31,0x77,0x2F,0x79,0x4F,0xC6,0x21, ++0x44,0x31,0xA8,0x2C,0xCE,0xB2,0x39,0xC0, ++0x44,0x31,0x48,0x2C,0xDF,0x32,0x84,0x22, ++0x4C,0x31,0x67,0x2A,0xCF,0xB2,0xB6,0x2A, ++0x54,0xB1,0x45,0x27,0xBF,0xB3,0x39,0xCA, ++0x18,0x30,0xF8,0xCF,0xDF,0xF2,0x14,0x23, ++0x44,0x31,0xA9,0x2C,0xC6,0xB2,0x39,0xC0, ++0x44,0x31,0x29,0x2A,0xCF,0xB2,0x69,0x29, ++0x42,0x31,0xF8,0xC5,0xEF,0xB2,0xA6,0x2F, ++0x44,0x31,0x77,0x2F,0x6B,0x4F,0xC6,0x21, ++0x44,0x31,0xA8,0x2C,0xCE,0xB2,0x39,0xC0, ++0x44,0x31,0x48,0x2C,0xDF,0x32,0x84,0x22, ++0x19,0x64,0x32,0x7F,0x9A,0xE7,0xE3,0x7F, ++0x01,0xE4,0x10,0x72,0xA2,0xE5,0x6C,0x9F, ++0x35,0x66,0xAD,0x9A,0x84,0x18,0x43,0x7E, ++0x11,0x64,0x0D,0x79,0x84,0x18,0x43,0x7E, ++0xD8,0x9B,0x52,0x70,0xF7,0x86,0x05,0xF1, ++0x11,0x64,0xAD,0x9A,0x9A,0xE7,0x6C,0x9F, ++0x11,0x64,0xAD,0x9A,0xAA,0xD6,0x5E,0xAC, ++0x25,0x51,0x9B,0xAD,0xA2,0xDE,0x2D,0xDD, ++0x52,0x20,0xE8,0xDC,0xDA,0xD7,0x34,0x9F, ++0x21,0x55,0x9F,0xA9,0xAE,0xD2,0x5A,0xA8, ++0x29,0x5D,0xCC,0xF8,0xF9,0x83,0x09,0xF9, ++0x51,0x54,0xD5,0x9A,0x9E,0xE7,0x6C,0x97, ++0x11,0x64,0xAD,0x9A,0x9A,0xE7,0x6C,0x9D, ++0x11,0x65,0xAD,0x9A,0x8A,0xE7,0x6C,0x9F, ++0x13,0x24,0xAD,0x9A,0x9A,0xE7,0x6C,0x3F, ++0x11,0x64,0xAD,0x9A,0x9F,0xA7,0x6C,0x9F, ++0xDD,0xA8,0x61,0x9E,0x56,0x2B,0xA0,0x53, ++0xD1,0xE8,0x61,0x56,0x56,0x2B,0xE0,0xCF, ++0xDD,0xA8,0x61,0x56,0x4F,0x6B,0xA0,0x53, ++0xDD,0x88,0xDD,0xE8,0x56,0x2B,0xA0,0x53, ++0xE9,0xE8,0x61,0x56,0xE9,0xE2,0xBB,0xDD, ++0xDD,0xA8,0x61,0x52,0xE3,0x6B,0xA0,0x53, ++0x8D,0xE3,0xAE,0x86,0x30,0x2C,0x42,0x9C, ++0xDC,0xA8,0x61,0x56,0x3A,0x6A,0xA0,0x53, ++0xE3,0x2A,0x30,0xFC,0x89,0xC5,0x07,0x67, ++0xDC,0xA8,0x61,0x56,0x8F,0x69,0xA0,0x53, ++0x01,0x1D,0xC1,0xB4,0x6C,0x1B,0xBF,0xC4, ++0x22,0x57,0x9E,0xA9,0xE2,0x6E,0xA0,0x53, ++0x20,0x8D,0xC1,0x9E,0xBF,0x88,0x61,0x1C, ++0x22,0x57,0x9E,0xA9,0xA9,0x14,0xA0,0x53, ++0xDD,0xA8,0x61,0xD6,0x56,0x2B,0xA0,0x53, ++0x22,0x97,0x61,0x56,0x56,0x2B,0xA0,0xD3, ++0x33,0x46,0x8F,0xB8,0x98,0x4A,0x4C,0x9D, ++0x13,0xC9,0x8D,0x98,0xD8,0xE5,0x4E,0xBD, ++0x93,0x16,0x8D,0x98,0xA8,0xC4,0x4E,0xBD, ++0x70,0x46,0x8F,0xB8,0x40,0x3A,0xB1,0x42, ++0x33,0x06,0xCF,0xF8,0xF8,0x85,0x0E,0xFD, ++0x73,0x06,0xCE,0xF9,0xF9,0x84,0x0F,0xFD, ++0x73,0x06,0xCF,0xF8,0xF8,0x85,0x0E,0xFD, ++0x73,0x06,0xCF,0xF8,0xF8,0x85,0x0E,0xFD, ++0x73,0x43,0x8D,0xBA,0xBA,0xC7,0x4C,0xBF, ++0x31,0x44,0x8D,0xBA,0xBA,0xC7,0x4C,0xBF, ++0x31,0x66,0xAF,0x98,0x98,0xE5,0x6E,0x9D, ++0x13,0x66,0xAF,0xBA,0xBA,0xC7,0x4C,0xBF, ++0x31,0x44,0x1F,0x28,0x28,0x55,0xDE,0x2D, ++0x23,0x56,0x9F,0xA8,0xA8,0xD5,0x5E,0xAD, ++0x23,0x56,0x9F,0xA8,0xA8,0xD5,0x5E,0xAD, ++0x23,0x56,0x9F,0xA8,0xBA,0xC7,0x4C,0xBF, ++0x57,0x22,0x61,0x56,0x56,0x2B,0xA0,0x53, ++0x5D,0x28,0xE1,0xD6,0xD6,0xAB,0x20,0xD3, ++0x5D,0x28,0xE1,0xD6,0xD6,0xAB,0x20,0xD3, ++0x5D,0x28,0xE1,0xD6,0xDC,0xA1,0x2A,0xD9, ++0x15,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xE0,0x81,0x0A,0xF9, ++0x34,0x02,0xCB,0xFC,0x04,0x7E,0xF5,0x06, ++0x7B,0x02,0xCB,0xFC,0xF2,0x81,0x0A,0xF9, ++0x78,0x02,0xCB,0xFC,0xD2,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0xD0,0xB2,0xFB,0x73,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0x9E,0xA4,0x5B,0xD3,0x01,0x00,0x00,0x00, ++0x01,0x00,0x08,0x01,0x01,0x00,0x00,0x01, ++0x64,0xF6,0xC0,0x06,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xB7,0x76,0xD2,0x16,0x0F,0x45,0x0F,0x8F, ++0xC3,0x71,0xEC,0xE3,0xCE,0xFF,0x99,0x49, ++0x47,0x38,0xC9,0xA2,0xFB,0xA3,0xC3,0xC9, ++0x7D,0xD4,0x1B,0xFE,0x23,0xF3,0x60,0xD4, ++0x7C,0xAC,0x96,0x86,0x31,0x91,0x17,0x6A, ++0xD3,0x79,0x07,0x64,0x9F,0x81,0xF3,0x83, ++0x9D,0xAC,0x3D,0x11,0x4D,0xEA,0xF2,0xA2, ++0x6E,0x05,0x77,0x40,0xA1,0x94,0x0E,0x8C, ++0x3D,0xA0,0xF9,0x33,0x3A,0x82,0x6C,0xDE, ++0x9F,0xFC,0x77,0xFA,0xC4,0x33,0x73,0x07, ++0x6E,0x8C,0x48,0xE3,0x37,0x39,0x01,0x6D, ++0xFC,0x24,0xB0,0x4A,0x32,0x97,0xF4,0xC8, ++0x3A,0x1E,0x17,0x01,0x51,0x85,0x06,0xF9, ++0x7E,0x7F,0x55,0x11,0x8A,0x58,0x19,0x8D, ++0x0B,0x67,0x12,0x3D,0xB1,0x66,0x7D,0xA6, ++0x30,0x42,0xC5,0xC8,0x40,0x1D,0xAD,0x79, ++0x6A,0xC8,0x0F,0x30,0x6A,0x7A,0x33,0x59, ++0xC1,0x28,0xC6,0xE3,0xC4,0x8F,0xDA,0x8A, ++0x21,0x82,0x05,0xAA,0x01,0x11,0x7F,0xE9, ++0x47,0x9D,0x66,0x3D,0x05,0x3E,0x49,0xC5, ++0x75,0xEE,0xA9,0x7C,0x0B,0x16,0x8F,0x9F, ++0xEC,0x26,0xEB,0x7C,0x06,0x04,0x37,0x23, ++0xDD,0x50,0x17,0xBC,0xDB,0xE5,0xB2,0xBA, ++0x72,0x13,0x09,0x33,0xD6,0x5F,0x15,0xCE, ++0x18,0xB6,0xCF,0xA0,0xF4,0x4F,0x87,0xCA, ++0x48,0x3F,0x63,0x94,0x0C,0x26,0xD7,0xA1, ++0x4B,0xEB,0x28,0xAA,0xDB,0xFA,0x83,0x2A, ++0x09,0x66,0x26,0x0B,0x15,0xD0,0x3F,0x33, ++0xB3,0x23,0x0F,0xD0,0xFE,0x71,0x1C,0x05, ++0xEE,0xAE,0x61,0x3E,0x12,0xE4,0x6A,0x9B, ++0x3D,0xF5,0xF7,0xF8,0x58,0xE0,0x99,0x12, ++0x2A,0xA7,0x85,0xFF,0xC1,0x1B,0x46,0x75, ++0x00,0x00,0x00,0x11,0x00,0x00,0x00,0x00, ++0x01,0x19,0xA6,0x7D,0x9B,0xF9,0x12,0x75, ++0xA2,0x99,0x27,0x2B,0x93,0x10,0xDD,0xBC, ++0x22,0x1C,0x89,0xA3,0x4F,0x12,0x49,0x21, ++0xC1,0x71,0x31,0xB9,0x1F,0xB5,0x86,0x4A, ++0x58,0xB2,0xB9,0xB5,0xDF,0x3B,0x95,0x47, ++0xF4,0xA2,0x1C,0x72,0x8A,0x31,0xA4,0xAF, ++0xA0,0x95,0x57,0x79,0x93,0x77,0x22,0x3F, ++0x25,0xBB,0xAC,0xBC,0x45,0x0B,0xB8,0x4E, ++0x31,0xC2,0xCC,0x7A,0xA8,0x32,0xE8,0xE2, ++0x0E,0x4D,0x8F,0xDF,0xDF,0x70,0x85,0x42, ++0xC7,0xC9,0x78,0x4A,0xB4,0x94,0x6A,0x56, ++0xB5,0x3A,0x10,0xF8,0xBB,0xF4,0xA0,0x55, ++0xB5,0xE3,0xA0,0x5D,0x6B,0x9A,0x9A,0xED, ++0x13,0x67,0xF3,0xE4,0x04,0x20,0x12,0x87, ++0xFF,0xA2,0xB5,0x71,0x0F,0x85,0x75,0x3F, ++0xB0,0x21,0xC9,0x73,0x55,0x06,0x53,0x9A, ++0x2B,0x42,0x4C,0xFC,0x24,0x8E,0xB5,0xF7, ++0x54,0x98,0x85,0xD8,0x7C,0xE9,0x8B,0x5A, ++0x82,0x4B,0x11,0xF6,0x8F,0x7A,0xF4,0x4F, ++0xC7,0x65,0x31,0xC0,0x65,0x05,0x1D,0x08, ++0xBF,0x0B,0xDD,0x0C,0xBD,0xF1,0xF5,0x4B, ++0xA1,0xA8,0x12,0xEE,0x72,0x86,0xA5,0xA6, ++0x5C,0x86,0x1E,0x9F,0xB5,0xD8,0x4C,0x82, ++0x63,0x64,0xC2,0x8D,0x7C,0x96,0x1D,0x31, ++0x38,0xA8,0xA1,0xF0,0x39,0x10,0xEC,0xCB, ++0x11,0x3A,0x62,0x9F,0x59,0x3B,0x58,0x52, ++0x23,0x82,0x73,0x11,0x21,0x8F,0xAB,0x45, ++0x1F,0x16,0xF5,0xA6,0xD0,0x08,0x85,0x72, ++0xE4,0xB7,0xAE,0xE5,0x33,0xA5,0x17,0xDF, ++0xC9,0xC8,0xC0,0xBA,0xC6,0xD9,0x67,0x49, ++0x5E,0xC2,0xB7,0x90,0x7F,0x07,0x1F,0xC8, ++0xA3,0x36,0xB2,0xFA,0x01,0x7F,0xA9,0x09, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +\ No newline at end of file +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_hal.c b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_hal.c +new file mode 100644 +index 00000000..70c7bfe5 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_hal.c +@@ -0,0 +1,3566 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//======================================================== ++// HAL pre-processors ++//======================================================== ++#if IF_FCIE_SHARE_IP ++ // re-config FCIE3 for NFIE mode ++ #define eMMC_RECONFIG() //eMMC_ReConfig(); ++#else ++ // NULL to save CPU a JMP/RET time ++ #define eMMC_RECONFIG() ++#endif ++ ++ ++#if eMMC_RSP_FROM_RAM ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) \ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSPFROMRAM_SAVE)\ ++ eMMC_KeepRsp(pu8_OneRspBuf, u8_CmdIdx) ++#else ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) // NULL to save CPU a JMP/RET time ++#endif ++ ++ ++#define eMMC_FCIE_CLK_DIS() REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN) ++ ++#define eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT 30 ++#define eMMC_CMD_API_ERR_RETRY_CNT 30 ++#define eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT 30 ++ ++#define eMMC_CMD1_RETRY_CNT 0x1000 ++#define eMMC_CMD3_RETRY_CNT 0x5 ++ ++//======================================================== ++// HAL APIs ++//======================================================== ++U32 eMMC_FCIE_WaitEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ return eMMC_WaitCompleteIntr(u32_RegAddr, u16_Events, u32_MicroSec); ++ #else ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ u16_Events |= BIT_CARD_DMA_END; ++ ++ //eMMC_printf("A"); ++ return eMMC_FCIE_PollingEvents(u32_RegAddr, u16_Events, u32_MicroSec); ++ #endif ++} ++ ++U32 eMMC_FCIE_PollingEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ volatile U32 u32_i; ++ volatile U16 u16_val; ++ for(u32_i=0; u32_i>REG_OFFSET_SHIFT_BITS, ++ u16_val, u16_Events); ++ ++ return eMMC_ST_ERR_TIMEOUT_WAIT_REG0; ++ } ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U16 sgau16_eMMCDebugBus[100]; ++void eMMC_FCIE_DumpDebugBus(void) ++{ ++ volatile U16 u16_reg, u16_i; ++ U16 u16_idx = 0; ++ ++ memset(sgau16_eMMCDebugBus, 0xFF, sizeof(sgau16_eMMCDebugBus)); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ ++ for(u16_i=0; u16_i<8; u16_i++) ++ { ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_FCIE_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, u16_i< 0; u16_i--) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "%u ", u16_i); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ ++ // check FCIE reg.30h ++ REG_FCIE_R(FCIE_TEST_MODE, u16_reg); ++ if(0)//u16_reg & BIT_FCIE_BIST_FAIL) /* Andersen: "don't care." */ ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h BIST fail: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_BIST_FAIL; ++ } ++ if(u16_reg & BIT_FCIE_DEBUG_MODE_MASK) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h Debug Mode: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_DEBUG_MODE; ++ } ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ } ++ #endif // eMMC_TEST_IN_DESIGN ++ ++ // ------------------------------------------ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); ++ REG_FCIE_W(FCIE_MMA_PRI_REG, BIT_MIU_CLK_FREE_RUN); ++ REG_FCIE_W(FCIE_PATH_CTRL, BIT_SD_EN); ++ // all cmd are 5 bytes (excluding CRC) ++ REG_FCIE_W(FCIE_CMD_SIZE, eMMC_CMD_BYTE_CNT); ++ REG_FCIE_W(FCIE_SD_CTRL, 0); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ #if FICE_BYTE_MODE_ENABLE ++ // default sector size: 0x200 ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE | eMMC_SECTOR_512BYTE); ++ #else ++ REG_FCIE_W(FCIE_SDIO_CTRL, 0); ++ #endif ++ //REG_FCIE_W(FCIE_BOOT_CONFIG, 0); // set by eMMC_pads_switch ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, 0); ++ eMMC_FCIE_ClearEvents(); ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; // ok ++} ++ ++ ++#if 1// defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++void eMMC_DumpDDRTTable(void) ++{ ++ U16 u16_i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC DDR Timing Table: Cnt:%u CurIdx:%u \n", ++ g_eMMCDrv.DDRTable.u8_SetCnt, g_eMMCDrv.DDRTable.u8_CurSetIdx); ++ ++ for(u16_i=0; u16_i 500 && u32_us-u32_cnt > 1000) ++ { ++ eMMC_hw_timer_sleep(1); ++ u32_cnt += 1000-2; ++ } ++ } ++ ++ return u32_cnt; ++} ++ ++U32 eMMC_FCIE_WaitD0High(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ ++ u32_cnt = eMMC_FCIE_WaitD0High_Ex(u32_us); ++ ++ if(u32_us == u32_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H timeout %u us\n", u32_cnt); ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++#define FIFO_CLK_RDY_CHECK_CNT 3 ++U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir) ++{ ++ volatile U32 u32_cnt=0; ++ volatile U16 au16_read[FIFO_CLK_RDY_CHECK_CNT], u16_i; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_MMA_PRI_REG, au16_read[0]); ++ if(u8_Dir == (au16_read[0]&BIT_DMA_DIR_W)) ++ break; ++ } ++ if(TIME_WAIT_FIFOCLK_RDY == u32_cnt) ++ return eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ for(u16_i=0; u16_i>24)<<8) | (0x40|u8_CmdIdx)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), u32_Arg&0xFF); ++ ++ REG_FCIE_R(FCIE_CIFC_ADDR(0),au16_tmp[0]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(1),au16_tmp[1]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(2),au16_tmp[2]); ++ ++ if(au16_tmp[0] == (((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx))&& ++ au16_tmp[1] == ((u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF))&& ++ au16_tmp[2] == (u32_Arg&0xFF)) ++ break; ++ } ++ ++ if(12 != u8_CmdIdx) ++ { ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ #endif ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSP_WAIT_D0H){ ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ // wait event ++ //eMMC_printf("eMMC_FCIE_SendCmd %X, %X, %X, %X, %X", u16_Mode, u16_Ctrl, u32_Arg, u8_CmdIdx, u8_RspByteCnt); ++ //eMMC_printf("M"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, TIME_WAIT_CMDRSP_END); ++ ++ LABEL_SEND_CMD_ERROR: ++ return u32_err; ++ ++} ++ ++ ++void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ eMMC_die("\n"); // should be system fatal error, not eMMC driver ++ } ++ ++ memcpy(g_eMMCDrv.au8_AllRsp + u16_idx, pu8_OneRspBuf, u8_ByteCnt); ++ ++} ++ ++ ++U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ if(0 == g_eMMCDrv.au8_AllRsp[u16_idx]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: no rsp, %u %u \n", u8_CmdIdx, u16_idx); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ memcpy(pu8_OneRspBuf, g_eMMCDrv.au8_AllRsp + u16_idx, u8_ByteCnt); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ------------------------------- ++U32 eMMC_SaveRsp(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_SaveDriverContext(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_LoadDriverContext(U8 *pu8_Buf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++//======================================================== ++// Send CMD HAL APIs ++//======================================================== ++U32 eMMC_Identify(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_i, u16_retry=0; ++ ++ g_eMMCDrv.u16_RCA=1; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ LABEL_IDENTIFY_CMD0: ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(u16_retry > 10) ++ return u32_err; ++ if(u16_retry) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Warn: retry: %u\n", u16_retry); ++ ++ // CMD0 ++ u32_err = eMMC_CMD0(0); // reset to idle state ++ if(eMMC_ST_SUCCESS != u32_err) ++ {u16_retry++; goto LABEL_IDENTIFY_CMD0;} ++ ++ // CMD1 ++ for(u16_i=0; u16_i>6; ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 1); ++ } ++ } ++ #else ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD1 ok, do things here ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ else ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ } ++ } ++ #endif ++ ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// send CID ++U32 eMMC_CMD2(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 2, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD2, %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD2; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD2 Reg.12: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD2 ok, do things here (get CID) ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CID); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CID, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CID, 2); ++ } ++ } ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// CMD3: assign RCA. CMD7: select device ++U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ if(7 == u8_CmdIdx) ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ else{ ++ u8_retry_fcie = 0xF0; // CMD3: not retry ++ } ++ ++ u32_arg = u16_RCA<<16; ++ ++ if(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA) ++ u16_ctrl = BIT_SD_CMD_EN; ++ else ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ return u32_err; ++ } ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ // de-select has no rsp ++ if(!(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA)){ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ return u32_err; ++ } ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ return u32_err; ++ } ++ ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ }} ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_CSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------ ++ g_eMMCDrv.u8_SPEC_VERS = (g_eMMCDrv.au8_CSD[1]&0x3C)>>2; ++ g_eMMCDrv.u8_R_BL_LEN = g_eMMCDrv.au8_CSD[6] & 0xF; ++ g_eMMCDrv.u8_W_BL_LEN = ((g_eMMCDrv.au8_CSD[13]&0x3)<<2)+ ++ ((g_eMMCDrv.au8_CSD[14]&0xC0)>>6); ++ ++ // ------------------------------ ++ g_eMMCDrv.u16_C_SIZE = (g_eMMCDrv.au8_CSD[7] & 3)<<10; ++ g_eMMCDrv.u16_C_SIZE += g_eMMCDrv.au8_CSD[8] << 2; ++ g_eMMCDrv.u16_C_SIZE +=(g_eMMCDrv.au8_CSD[9] & 0xC0) >> 6; ++ if(0xFFF == g_eMMCDrv.u16_C_SIZE) ++ { ++ g_eMMCDrv.u32_SEC_COUNT = 0; ++ } ++ else ++ { ++ g_eMMCDrv.u8_C_SIZE_MULT = ((g_eMMCDrv.au8_CSD[10]&3)<<1)+ ++ ((g_eMMCDrv.au8_CSD[11]&0x80)>>7); ++ ++ g_eMMCDrv.u32_SEC_COUNT = ++ (g_eMMCDrv.u16_C_SIZE+1)* ++ (1<<(g_eMMCDrv.u8_C_SIZE_MULT+2))* ++ ((1<>9) - 8; // -8: //Toshiba CMD18 access the last block report out of range error ++ } ++ // ------------------------------ ++ g_eMMCDrv.u8_ERASE_GRP_SIZE = (g_eMMCDrv.au8_CSD[10]&0x7C)>>2; ++ g_eMMCDrv.u8_ERASE_GRP_MULT = ((g_eMMCDrv.au8_CSD[10]&0x03)<<3)+ ++ ((g_eMMCDrv.au8_CSD[11]&0xE0)>>5); ++ g_eMMCDrv.u32_EraseUnitSize = (g_eMMCDrv.u8_ERASE_GRP_SIZE+1)* ++ (g_eMMCDrv.u8_ERASE_GRP_MULT+1); ++ // ------------------------------ ++ // others ++ g_eMMCDrv.u8_TAAC = g_eMMCDrv.au8_CSD[2]; ++ g_eMMCDrv.u8_NSAC = g_eMMCDrv.au8_CSD[3]; ++ g_eMMCDrv.u8_Tran_Speed = g_eMMCDrv.au8_CSD[4]; ++ g_eMMCDrv.u8_R2W_FACTOR = (g_eMMCDrv.au8_CSD[13]&0x1C)>>2; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// send CSD (in R2) ++U32 eMMC_CMD9(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_RCA<<16; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 9, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD9 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD9; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD9 Reg.12: %04Xh, Retry fail: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD2 ok, do things here ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CSD); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CSD, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CSD, 9); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_ExtCSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD8(gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_dump_mem(gau8_eMMC_SectorBuf, 0x200); ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((gau8_eMMC_SectorBuf[215]<<24)| ++ (gau8_eMMC_SectorBuf[214]<<16)| ++ (gau8_eMMC_SectorBuf[213]<< 8)| ++ (gau8_eMMC_SectorBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = gau8_eMMC_SectorBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_BUS_WIDTH = gau8_eMMC_SectorBuf[183]; ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[503]&BIT0) // HPI ++ { ++ if(gau8_eMMC_SectorBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ }else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ #else ++ if((gau8_eMMC_SectorBuf[503]&BIT0) && 1==gau8_eMMC_SectorBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(gau8_eMMC_SectorBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ else ++ { ++ eMMC_debug(0,1,"eMMC Warn: not support Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = gau8_eMMC_SectorBuf[181]; ++ ++ if (gau8_eMMC_SectorBuf[224] != 0) ++ { ++ g_eMMCDrv.u32_EraseUnitSize = gau8_eMMC_SectorBuf[224] << 10; ++ } ++ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_CMD8(U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD8_CIFD(pu8_DataBuf); ++ #else ++ return eMMC_CMD8_MIU(pu8_DataBuf); ++ #endif ++} ++ ++// CMD8: send EXT_CSD ++U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_dma_addr; ++ ++ // ------------------------------- ++ #if 0==IF_IP_VERIFY ++ if(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE){ ++ if(0 == eMMC_IF_DDRT_TUNING()) ++ { ++ if(eMMC_DDRT_SET_MAX != g_eMMCDrv.DDRTable.u8_CurSetIdx) ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ } ++ } ++ else{ // SDR Mode ++ //if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ // eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_R_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE, READ_FROM_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ //eMMC_printf("L"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ volatile U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0;; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ //u16_mode |= BIT_SD_DATA_CIFD; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ //eMMC_printf("K"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ //eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 8); ++ ++ // ------------------------------- ++ // CMD8 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetBusSpeed(U8 u8_BusSpeed) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, u8_BusSpeed); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_SPEED_MASK; ++ switch(u8_BusSpeed) ++ { ++ case eMMC_SPEED_HIGH: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_SYNC; ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC set bus HIGH speed\n"); ++ break; ++ case eMMC_SPEED_HS200: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS200; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_SYNC; ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC set bus HS200 speed\n"); ++ break; ++ default: ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC set bus LOW speed\n"); ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR) ++{ ++ U8 u8_value; ++ U32 u32_err; ++ ++ // ------------------------------- ++ switch(u8_BusWidth) ++ { ++ case 1: u8_value=0; break; ++ case 4: u8_value=1; break; ++ case 8: u8_value=2; break; ++ default: return eMMC_ST_ERR_PARAMETER; ++ } ++ ++ if(u8_IfDDR) ++ u8_value |= BIT2; ++ if(BIT2 == u8_value) ++ return eMMC_ST_ERR_PARAMETER; ++ ++ // ------------------------------- ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 183, u8_value); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------- ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ switch(u8_BusWidth) ++ { ++ case 1: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_1; ++ break; ++ case 4: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_4; ++ break; ++ case 8: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_8; ++ break; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"set %u bus width\n", u8_BusWidth); ++ return u32_err; ++} ++ ++U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ U32 u32_arg, u32_err; ++ ++ u32_arg = ((u8_AccessMode&3)<<24) | (u8_ByteIdx<<16) | ++ (u8_Value<<8); ++ ++ u32_err = eMMC_CMD6(u32_arg); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ ++ u32_err = eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++// SWITCH cmd ++U32 eMMC_CMD6(U32 u32_Arg) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_Arg; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 6, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD6; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 6); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_start, 35); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_end, 36); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD38(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ return u32_err; ++} ++ ++U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD38(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ u32_arg = 0x1; ++ else ++ u32_arg = 0x0; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 38, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD38 retry:%u, %Xh \n", ++ u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD38 retry:%u, %Xh \n", ++ u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD38 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD38 check R1 error: %Xh, retry: %u\n", ++ u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 check R1 error: %Xh, retry: %u\n", ++ u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 38); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++// CMD13: send Status ++U32 eMMC_CMD13(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = (u16_RCA<<16) | ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD13)?1:0); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 13, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 13); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD16(U32 u32_BlkLength) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_BlkLength; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 16, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD16; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD16 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 16); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++//------------------------------------------------ ++ ++U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD17_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD17_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_dma_addr; ++ ++ // ------------------------------- ++ #if 0==IF_IP_VERIFY ++ if(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE){ ++ if(0 == eMMC_IF_DDRT_TUNING()) ++ { ++ if(eMMC_DDRT_SET_MAX != g_eMMCDrv.DDRTable.u8_CurSetIdx) ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ } ++ } ++ else{ // SDR Mode ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_R_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE, READ_FROM_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ //eMMC_printf("J"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ #if 0==IF_IP_VERIFY ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ //eMMC_printf("I"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // CMD17 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check reg.12h error: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD12; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check reg.12h error: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 12); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12_NoCheck(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ //eMMC_printf("H"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>9))); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++// enable Reliable Write ++U32 eMMC_CMD23(U16 u16_BlkCnt) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_BlkCnt&0xFFFF; // don't set BIT24 ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ u32_arg |= BIT31; // don't set BIT24 ++ #endif ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 23, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 23); ++ ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt g_eMMCDrv.u16_ReliableWBlkCnt ? ++ g_eMMCDrv.u16_ReliableWBlkCnt : u16_BlkCntTotal; ++ u32_err = eMMC_CMD23(u16_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD23 fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ u16_BlkCnt = u16_BlkCntTotal; ++ #endif ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_W_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u16_BlkCnt); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE*u16_BlkCnt, WRITE_TO_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD25 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD25 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ #ifdef STATIC_RELIABLE_TEST ++ //set watchdog ++ if(enable_pm_sleep_flag == 1) ++ { ++ MDrv_WDT_ClearRstFlag(); ++ MDrv_WDT_SetTimer(1, 60); ++ } ++ #endif ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ ++ #ifdef STATIC_RELIABLE_TEST ++ //cut off power for eMMC ++ if(enable_pm_sleep_flag == 1) ++ { ++ if(reliable_test_sleep>0) ++ udelay(reliable_test_sleep*1000); ++ ++ temp = *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x10*2)*2); ++ temp &= ~BIT4; ++ *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x010*2)*2) =temp; ++ temp = *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x0F*2)*2); ++ temp &= ~BIT4; ++ *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x0F*2)*2) =temp; ++ *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x12*2)*2) = 0xBABE; ++ } ++ #endif ++ //eMMC_printf("G"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>7))); ++ ++ #ifdef STATIC_RELIABLE_TEST ++ if(enable_pm_sleep_flag == 1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "write done\n"); ++ } ++ #endif ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ if(g_eMMCDrv.u16_ReliableWBlkCnt) ++ { ++ u32_eMMCBlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt * eMMC_SECTOR_512BYTE; ++ u16_BlkCntTotal -= u16_BlkCnt; ++ if(u16_BlkCntTotal) ++ goto LABEL_RELIABLE_W_START; ++ } ++ #endif ++ ++ LABEL_END: ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ if(eMMC_ST_SUCCESS != u32_err || 0==g_eMMCDrv.u16_ReliableWBlkCnt) ++ #endif ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD24_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ return eMMC_CMD25(u32_eMMCBlkAddr, pu8_DataBuf, 1); ++ #else ++ return eMMC_CMD24_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++ #endif ++} ++ ++U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_dma_addr; ++ ++ // ------------------------------- ++ #if 0==IF_IP_VERIFY ++ if(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE){ ++ if(0 == eMMC_IF_DDRT_TUNING()) ++ { ++ if(eMMC_DDRT_SET_MAX != g_eMMCDrv.DDRTable.u8_CurSetIdx) ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ } ++ } ++ else{ // SDR Mode ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_W_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE, WRITE_TO_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_MIU_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ //eMMC_printf("F"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i, *pu16_dat=(U16*)pu8_DataBuf; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ // ------------------------------- ++ // fill CIFD with data ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ #if 0==IF_IP_VERIFY ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ #endif ++ ++ for(u16_i=0; u16_i<(FCIE_CIFD_BYTE_CNT>>1); u16_i++) ++ REG_FCIE_W(FCIE_CIFD_ADDR(u16_i), pu16_dat[u16_i]); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ //eMMC_printf("E"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CheckR1Error(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ ++ if(g_eMMCDrv.au8_Rsp[1] & (eMMC_ERR_R1_31_24>>24)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_31_24 \n "); ++ u32_err = eMMC_ST_ERR_R1_31_24; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[2] & (eMMC_ERR_R1_23_16>>16)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_23_16 \n "); ++ u32_err = eMMC_ST_ERR_R1_23_16; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[3] & (eMMC_ERR_R1_15_8>>8)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_15_8 \n "); ++ u32_err = eMMC_ST_ERR_R1_15_8; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[4] & (eMMC_ERR_R1_7_0>>0)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_7_0 \n "); ++ u32_err = eMMC_ST_ERR_R1_7_0; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ LABEL_CHECK_R1_END: ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R1_BYTE_CNT); ++ ++ if(24==g_eMMCDrv.au8_Rsp[0] || 25==g_eMMCDrv.au8_Rsp[0] || ++ 18==g_eMMCDrv.au8_Rsp[0] || 12==g_eMMCDrv.au8_Rsp[0]) ++ eMMC_FCIE_ErrHandler_ReInit(); ++ } ++ return u32_err; ++} ++ ++ ++// ==================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define UPFW_SEC_WIAT_CNT 0x1000000 ++#define UPFW_SEC_BYTE_CNT (128*1024) ++static U32 eMMC_UpFW_Samsung_Wait(void) ++{ ++ U32 u32_err, u32_cnt, u32_st; ++ ++ for(u32_cnt=0; u32_cnt>eMMC_SECTOR_512BYTE_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: write fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 3, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ // --------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"close ... \n"); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, 0, 28, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD28 fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 4, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ LABEL_END_OF_UPFW: ++ return u32_err; ++ ++} ++#endif // eMMC_UPDATE_FIRMWARE ++#endif ++ +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_ip_verify.c b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_ip_verify.c +new file mode 100644 +index 00000000..14802983 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_ip_verify.c +@@ -0,0 +1,1007 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined (UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++ ++//============================================================= ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ ++#define DDR_TEST_BLK_CNT 8 ++#define DDR_TEST_BUFFER_SIZE (eMMC_SECTOR_512BYTE*DDR_TEST_BLK_CNT) ++ ++eMMC_ALIGN0 static U8 gau8_WBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++eMMC_ALIGN0 static U8 gau8_RBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++ ++U32 eMMCTest_BlkWRC_ProbeDDR(U32 u32_eMMC_Addr) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf_DDR, *pu32_R=(U32*)gau8_RBuf_DDR; ++ U32 u32_BlkCnt=eMMC_TEST_BLK_CNT, u32_BufByteCnt; ++ ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ u32_BufByteCnt = u32_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_R[u32_i] = 0; ++ ++ for(u32_j=0; u32_j<9; u32_j++) ++ { ++ // init data pattern ++ switch(u32_j) ++ { ++ case 0: // increase ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = u32_i+1; ++ break; ++ case 1: // decrease ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = 0-(u32_i+1); // more FF, more chance to lose start bit ++ break; ++ #else ++ continue; ++ #endif ++ case 2: // 0xF00F ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xF00FF00F; ++ break; ++ case 3: // 0xFF00 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFF00FF00; ++ break; ++ case 4: // 0x5AA5 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5AA55AA5; ++ break; ++ case 5: // 0x55AA ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x55AA55AA; ++ break; ++ case 6: // 0x5A5A ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5A5A5A5A; ++ break; ++ #else ++ continue; ++ #endif ++ case 7: // 0x0000 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x00000000; ++ break; ++ case 8: // 0xFFFF ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFFFFFFFF; ++ break; ++ ++ } ++ ++ #if 0 ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.single, %Xh \n", u32_err); ++ break; ++ } ++ #endif ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMC_Addr, gau8_WBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD18_MIU(u32_eMMC_Addr, gau8_RBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, u32_BufByteCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.multi %Xh \n", u32_err); ++ break; ++ } ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_debug(0,0,"data pattern %u: %02X%02X%02X%02Xh \n\n", ++ u32_j, gau8_WBuf_DDR[3], gau8_WBuf_DDR[2], gau8_WBuf_DDR[1], gau8_WBuf_DDR[0]); ++ } ++ ++ return u32_err; ++} ++ ++ ++// can use for RF team test ++U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, u32_k; ++ U32 u32_BlkCnt, u32_eMMC_Addr; ++ ++ u32_eMMC_Addr = eMMC_TEST_BLK_0; ++ ++ u32_BlkCnt = eMMC_TEST_BLK_CNT; ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ ++ if(8 != u32_BlkCnt) ++ { ++ eMMC_debug(0,1,"Blk count needs to be 8 \n"); ++ while(1); ++ } ++ ++ for(u32_j=0; u32_j>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u32_err = eMMC_CMD24_CIFD(u32_eMMC_Addr, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_CIFD(u32_eMMC_Addr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, FCIE_CIFD_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++extern U32 gu32_DMAAddr; ++U32 eMMCTest_SingleBlkWRC_MIU(U32 u32_eMMC_Addr, U32 u32_DataPattern) ++{ ++ U32 u32_err; ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, FCIE_CIFD_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMCTest_MultiBlkWRC_MIU(U32 u32_eMMC_Addr, U16 u16_BlkCnt, U32 u32_DataPattern) ++{ ++ U32 u32_err; ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ U16 u16_BlkCnt_tmp; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u16_BlkCnt_tmp = TEST_BUFFER_SIZE >> eMMC_SECTOR_512BYTE_BITS; ++ u16_BlkCnt_tmp = u16_BlkCnt_tmp > u16_BlkCnt ? u16_BlkCnt : u16_BlkCnt_tmp; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS; ++ #if IF_eMMC_BOOT_MODE_STG2 ++ au32_Addr[1] = (U32)gau8_BootImage1; ++ au32_SectorCnt[1] = sizeof(gau8_BootImage1)>>eMMC_SECTOR_512BYTE_BITS; ++ au32_Addr[2] = (U32)gau8_BootImage2; ++ au32_SectorCnt[2] = sizeof(gau8_BootImage2)>>eMMC_SECTOR_512BYTE_BITS; ++ #endif ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 1); ++ #else ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 3); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, eMMC_LoadImages: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ //eMMC_debug(0,1,"ChkSum -: %Xh \n", eMMC_ChkSum((U8*)au32_Addr, sizeof(gau8_BootImageOri))); ++ eMMC_debug(0,1,"ChkSum -: %Xh, Addr: %Xh \n", eMMC_ChkSum((U8*)au32_Addr[0], 0xC1< u32_t1) ++ while(0==(u32_t0-eMMC_hw_timer_tick())/eMMC_HW_TIMER_MHZ) ++ ; ++ else ++ while(0==(eMMC_hw_timer_tick()-u32_t0)/eMMC_HW_TIMER_MHZ) ++ ; ++ #endif ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,".\n"); ++} ++ ++U32 eMMC_IPVerify_Performance(void) ++{ ++ volatile U32 u32_err, u32_i, u32_SectorAddr=0, u32_SectorCnt=0, u32_t0, u32_t1, u32_t; ++ U8 u8_IfDDRTest=0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"SectorBuf:%Xh, RBuf:%Xh, WBuf:%Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_Init ok] \n"); ++ ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == g_eMMCDrv.DDRTable.u8_SetCnt){ ++ eMMC_FCIE_BuildDDRTimingTable(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: BuildDDRTimingTable fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ }else ++ eMMC_DumpDDRTTable(); ++ #endif ++ ++ eMMCTest_DownCount(eMMC_SPEED_TEST_COUNTDOWN); ++ for(u32_i=0; u32_i>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_W); ++ ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_W; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ //eMMC_debug(0,0,"%08Xh \n", u32_SectorAddr+u32_i); ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ u32_err = eMMC_CMD24(u32_SectorAddr, gau8_WBuf); ++ #else ++ u32_err = eMMC_CMD24_MIU(u32_SectorAddr, gau8_WBuf); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u KB/sec \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_W<>10)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_SINGLE_BLKCNT_W<>10)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Single Read, total: %uKB, %u blocks\n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R)<>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_R); ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_R; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ u32_err = eMMC_CMD17_MIU(u32_SectorAddr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u KB/sec \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R<>10)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_SINGLE_BLKCNT_R<>10)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Write, total: %uMB, %u blocks\n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20, ++ eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W); ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ u32_SectorCnt = ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS) > eMMC_TEST_BLK_CNT ? ++ eMMC_TEST_BLK_CNT : (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS); ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u MB/sec \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Read, total: %uMB, %u blocks\n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20, ++ eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R); ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ u32_SectorCnt = ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS) > eMMC_TEST_BLK_CNT ? ++ eMMC_TEST_BLK_CNT : (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS); ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u MB/sec \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ if(u8_IfDDRTest) ++ return eMMC_ST_SUCCESS; ++ ++ // =============================================== ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"DDR\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"======================================\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ ++ u8_IfDDRTest = 1; ++ goto LABEL_TEST_START; ++ #endif ++ ++ return u32_err; ++ ++} ++ ++ ++U32 eMMC_IPVerify_Main(void) ++{ ++ U32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC_IPVerify_Main\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"%Xh %Xh %Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ #if 0 ++ eMMC_BootMode(); ++ //while(1); ++ return 0; ++ #endif ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_Init ok] \n"); ++ ++ // =============================================== ++ #if 0 ++ eMMC_debug(0,1,"BootImage ByteCnt: %Xh, ChkSum:%Xh\n", ++ sizeof(gau8_BootImageOri), eMMC_ChkSum(gau8_BootImageOri, sizeof(gau8_BootImageOri))); ++ ++ u32_err = eMMC_WriteBootPart(gau8_BootImageOri, sizeof(gau8_BootImageOri), 0, 1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_WriteBootPart fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "[eMMC_WriteBootPart ok] \n"); ++ ++ while(1); ++ #endif ++ ++ // =============================================== ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal pattern test ok\n\n"); ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "specific pattern test ok\n\n"); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_IPVerify_Main_Ex(U32 u32_DataPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ //eMMC_debug(0,1,"Total Sec: %Xh, StartSec: %Xh, SecCnt: %Xh \n", ++ // g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ ++ #if 1 ++ if(0==(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ u32_err = eMMCTest_SingleBlkWRC_RIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_RIU fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_RIU ok] \n");} ++ #endif ++ #if 1 ++ u32_err = eMMCTest_SingleBlkWRC_MIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMCTest_MultiBlkWRC_MIU(u32_StartSector, u32_SectorCnt, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_MultiBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_MultiBlkWRC_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++ ++U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void) ++{ ++ U32 u32_err; ++ U8 u8_SDRClkIdx, u8_DDRClkIdx; ++ ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == g_eMMCDrv.DDRTable.u8_SetCnt){ ++ eMMC_FCIE_BuildDDRTimingTable(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: BuildDDRTimingTable fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ }else ++ eMMC_DumpDDRTTable(); ++ #endif ++ ++ u8_SDRClkIdx = 0; ++ u8_DDRClkIdx = 0; ++ ++ while(1) ++ { ++ #if 1 ++ //eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"SDR\n"); ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ //if(0==u8_SDRClkIdx) u8_SDRClkIdx++; // skip 48MHz ++ eMMC_clock_setting(gau8_FCIEClkSel[u8_SDRClkIdx]); ++ u8_SDRClkIdx++; ++ //u8_SDRClkIdx = u8_SDRClkIdx%(eMMC_FCIE_VALID_CLK_CNT-1);// skip 300KHz ++ u8_SDRClkIdx = u8_SDRClkIdx%eMMC_FCIE_VALID_CLK_CNT; ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ #endif ++ ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ //eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"DDR\n"); ++ ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ #if 1 ++ eMMC_FCIE_ApplyDDRTSet(u8_DDRClkIdx); ++ u8_DDRClkIdx++; ++ u8_DDRClkIdx = u8_DDRClkIdx%g_eMMCDrv.DDRTable.u8_SetCnt; ++ #endif ++ #if 0 ++ do{ // skip 42.6MHz ++ u8_DDRClkIdx++; ++ u8_DDRClkIdx = u8_DDRClkIdx%g_eMMCDrv.DDRTable.u8_SetCnt; ++ eMMC_FCIE_ApplyDDRTSet(u8_DDRClkIdx); ++ }while(BIT_FCIE_CLK_42_6M == g_eMMCDrv.DDRTable.Set[u8_DDRClkIdx].u8_Clk); ++ #endif ++ #if 0 ++ eMMC_FCIE_ApplyDDRTSet(1); ++ #endif ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ #endif ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++#endif +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_utl.c b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_utl.c +new file mode 100644 +index 00000000..f048fb37 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/src/common/eMMC_utl.c +@@ -0,0 +1,342 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//-------------------------------------------------------------------------- ++static eMMC_ALIGN0 eMMC_TEST_ALIGN_PACK_t g_eMMCTestAlignPack_t eMMC_ALIGN1; ++U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt) ++{ ++ // check alignment ++ if((U32)&(g_eMMCTestAlignPack_t.u8_0) & (u8_AlignByteCnt-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not aliged. expect %Xh but %Xh \n", ++ u8_AlignByteCnt, (U32)&(g_eMMCTestAlignPack_t.u8_0)); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_ALIGN; ++ } ++ // check packed - 0 ++ if((U32)&(g_eMMCTestAlignPack_t.u16_0)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 1 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_0)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 3 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_1)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 7) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not packed. check err.0 \n"); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_PACKED; ++ } ++ // check packed - 1 ++ if((U32)&(g_eMMCTestAlignPack_t.u16_0)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 1 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_0)-(U32)&(g_eMMCTestAlignPack_t.u16_0)!= 2 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_1)-(U32)&(g_eMMCTestAlignPack_t.u32_0)!= 4) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not packed. check err.1 \n"); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_PACKED; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "ok\n"); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static __inline void dump_mem_line(unsigned char *buf, int cnt) ++{ ++ int i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " 0x%08X: ", (U32)buf); ++ for (i= 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%02Xh ", buf[i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " | "); ++ ++ for (i = 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%c", (buf[i] >= 32 && buf[i] < 128) ? buf[i] : '.'); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "\n"); ++} ++ ++void eMMC_dump_mem(unsigned char *buf, int cnt) ++{ ++ int i; ++ ++ for (i= 0; i < cnt; i+= 16) ++ dump_mem_line(buf + i, 16); ++} ++ ++ ++U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt) ++{ ++ U32 u32_i, u32_offset; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS)<>11); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "eMMC BUS_WIDTH: %Xh\n", g_eMMCDrv.u8_BUS_WIDTH); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TRIM: %Xh\n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_TRIM)?1:0); ++ ++ if(g_eMMCDrv.u32_eMMCFlag & (eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13)) ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: CMD%u \n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_HPI_CMD12)?12:13); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: 0 \n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"Reliable Write BlkCnt: %Xh\n", g_eMMCDrv.u16_ReliableWBlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ // ------------------------------ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(0, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CSD:\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CSD[0], eMMC_MAX_RSP_BYTE_CNT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "SPEC_VERS: %Xh, R_BL_LEN: %Xh, W_BL_LEN: %Xh \n", ++ g_eMMCDrv.u8_SPEC_VERS, g_eMMCDrv.u8_R_BL_LEN, g_eMMCDrv.u8_W_BL_LEN); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "Access Mode: %s\n", g_eMMCDrv.u8_IfSectorMode?"Sector":"Byte"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "C_SIZE: %Xh\n", g_eMMCDrv.u16_C_SIZE); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "ERASE_GRP_SIZE: %Xh, ERASE_GRP_MULT: %Xh\n", ++ g_eMMCDrv.u8_ERASE_GRP_SIZE, g_eMMCDrv.u8_ERASE_GRP_MULT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "EraseUnitSize: %u\n", g_eMMCDrv.u32_EraseUnitSize); ++ switch(g_eMMCDrv.u8_Tran_Speed) ++ { ++ case 0x2A: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 20MHz\n"); break; ++ case 0x32: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 26MHz\n"); break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal TRAN_SPEED: %Xh\n", g_eMMCDrv.u8_Tran_Speed); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TAAC: %Xh, NSAC: %Xh, R2W_FACTOR: %Xh\n", ++ g_eMMCDrv.u8_TAAC, g_eMMCDrv.u8_NSAC, g_eMMCDrv.u8_R2W_FACTOR); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "RCA: %Xh\n", g_eMMCDrv.u16_RCA); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CID:\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CID[0], eMMC_MAX_RSP_BYTE_CNT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ return u32_err; ++} ++ ++ ++void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ int i; ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC NNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "peMMCInfo: 0x%08X\n", (U32)peMMCInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_Tag : ["); ++ for (i = 0; i < 16; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%c", peMMCInfo->au8_Tag[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_IDByteCnt : 0x%04x\n", peMMCInfo->u8_IDByteCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_ID : 0x[ "); ++ for (i = 0; i < peMMCInfo->u8_IDByteCnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%02X ", peMMCInfo->au8_ID[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", peMMCInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", peMMCInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", peMMCInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", peMMCInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", peMMCInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_Config : 0x%08X\n", peMMCInfo->u32_Config); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_ECCType : 0x%04x\n", peMMCInfo->u16_ECCType); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SeqAccessTime: 0x%04x\n", peMMCInfo->u16_SeqAccessTime); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_Vendor: %s\n", peMMCInfo->au8_Vendor); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PartNumber: %s\n", peMMCInfo->au8_PartNumber); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapLoc: 0x%04x\n", peMMCInfo->u8_PairPageMapLoc); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapType: 0x%04x\n", peMMCInfo->u8_PairPageMapType); ++#endif ++} ++ ++void eMMC_dump_pni(eMMC_PNI_t *pPartInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC PNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "pPartInfo: 0x%08X\n", (U32)pPartInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", pPartInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PartCnt : 0x%04x\n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_UnitByteCnt : 0x%04x\n", pPartInfo->u16_UnitByteCnt); ++ ++ //dump_part_records(pPartInfo->records, pPartInfo->u16_PartCnt); ++#endif ++} ++ ++#endif +diff --git a/drivers/mstar/emmc/cedric/eMMCDrv/src/config/eMMC_platform.c b/drivers/mstar/emmc/cedric/eMMCDrv/src/config/eMMC_platform.c +new file mode 100644 +index 00000000..f9f2038b +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/eMMCDrv/src/config/eMMC_platform.c +@@ -0,0 +1,6554 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++#define DDR_TEST_BLK_CNT 8 ++#define DDR_TEST_BUFFER_SIZE (eMMC_SECTOR_512BYTE*DDR_TEST_BLK_CNT) ++ ++eMMC_ALIGN0 static U8 gau8_WBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++eMMC_ALIGN0 static U8 gau8_RBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++ ++U32 eMMCTest_BlkWRC_ProbeDDR(U32 u32_eMMC_Addr) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf_DDR, *pu32_R=(U32*)gau8_RBuf_DDR; ++ U32 u32_BlkCnt=eMMC_TEST_BLK_CNT, u32_BufByteCnt; ++ ++ //eMMC_printf("eMMCTest_BlkWRC_ProbeDDR\r\n"); ++ ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ u32_BufByteCnt = u32_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_R[u32_i] = 0; ++ ++ for(u32_j=0; u32_j<9; u32_j++) ++ { ++ // init data pattern ++ switch(u32_j) ++ { ++ case 0: // increase ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = u32_i+1; ++ break; ++ case 1: // decrease ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = 0-(u32_i+1); // more FF, more chance to lose start bit ++ break; ++ #else ++ continue; ++ #endif ++ case 2: // 0xF00F ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xF00FF00F; ++ break; ++ case 3: // 0xFF00 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFF00FF00; ++ break; ++ case 4: // 0x5AA5 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5AA55AA5; ++ break; ++ case 5: // 0x55AA ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x55AA55AA; ++ break; ++ case 6: // 0x5A5A ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5A5A5A5A; ++ break; ++ #else ++ continue; ++ #endif ++ case 7: // 0x0000 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x00000000; ++ break; ++ case 8: // 0xFFFF ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFFFFFFFF; ++ break; ++ ++ } ++ ++ #if 0 ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.single, %Xh \n", u32_err); ++ break; ++ } ++ #endif ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMC_Addr, gau8_WBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD18_MIU(u32_eMMC_Addr, gau8_RBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, u32_BufByteCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.multi %Xh \n", u32_err); ++ break; ++ } ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_debug(0,0,"data pattern %u: %02X%02X%02X%02Xh \n\n", ++ u32_j, gau8_WBuf_DDR[3], gau8_WBuf_DDR[2], gau8_WBuf_DDR[1], gau8_WBuf_DDR[0]); ++ } ++ ++ return u32_err; ++} ++ ++void eMMC_Prepare_Power_Saving_Mode_Queue(void) ++{ ++ #if (defined(eMMC_DRV_CHICAGO_LINUX) && eMMC_DRV_CHICAGO_LINUX) ++ REG_FCIE_SETBIT(REG_BATTERY, reg_nobat_int_en); ++ ++ /* (1) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x40), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x41), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (2) Clear All Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x42), 0xffff); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x43), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (3) Clear SDE MODE Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x44), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x45), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (4) Clear SDE CTL Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x46), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x47), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (5) Reset Start */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x48), 0x4800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x49), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (6) Reset End */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4A), 0x5800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (7) Set "SD_MOD" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4C), 0x0051); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (8) Enable "csreg_sd_en" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4E), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (9) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x50), 0x0040); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x51), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x00); ++ ++ /* (10) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x52), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x53), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x01); ++ ++ /* (11) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x54), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x55), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x02); ++ ++ /* (12) Command Size */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x56), 0x0005); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x57), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0E); ++ ++ /* (13) Response Size */ ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x58), 0x0000); ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x59), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0D); ++ ++ /* (14) Enable Interrupt, SD_CMD_END */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5A), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x01); ++ ++ /* (15) Command Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5C), 0x0004); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (16) Wait Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5E), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WINT); ++ ++ /* (17) Clear Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x60), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x61), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (18) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x62), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x63), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (19) STOP */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x64), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x65), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_STOP); ++ ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, BIT_POWER_SAVE_MODE_EN | BIT_SD_POWER_SAVE_RST); ++ #endif ++} ++ ++ ++//============================================================= ++#if (defined(eMMC_DRV_G2P_ROM)&&eMMC_DRV_G2P_ROM) ++//============================================================= ++#elif (defined(eMMC_DRV_EAGLE_LINUX)&&eMMC_DRV_EAGLE_LINUX) // [FIXME] clone for your flatform ++// [FIXME] --> ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ // TIMER_FREERUN_32K 32 KHz ++ // TIMER_FREERUN_XTAL 38.4 MHz, ++ // counting down ++ return 0;//HalTimerRead(TIMER_FREERUN_32K); ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 1, "FCIE 1X (0x%X):0x%X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 1, "FCIE 4X (0x%X):0x%X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 1, "CMU (0x%X):0x%X\n", reg_ckg_CMU, REG_FCIE_U16(reg_ckg_CMU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ eMMC_debug(0, 1, "chiptop_0x5A (0x%X):0x%X\n", reg_chiptop_0x5A, REG_FCIE_U16(reg_chiptop_0x5A)); ++ eMMC_debug(0, 1, "chiptop_0x1F (0x%X):0x%X\n", reg_chiptop_0x1F, REG_FCIE_U16(reg_chiptop_0x1F)); ++ eMMC_debug(0, 1, "chiptop_0x70 (0x%X):0x%X\n", reg_chiptop_0x70, REG_FCIE_U16(reg_chiptop_0x70)); ++ eMMC_debug(0, 1, "chiptop_0x64 (0x%X):0x%X\n", reg_chiptop_0x64, REG_FCIE_U16(reg_chiptop_0x64)); ++ eMMC_debug(0, 1, "chiptop_0x4F (0x%X):0x%X\n", reg_chiptop_0x4F, REG_FCIE_U16(reg_chiptop_0x4F)); ++ eMMC_debug(0, 1, "chiptop_0x03 (0x%X):0x%X\n", reg_chiptop_0x03, REG_FCIE_U16(reg_chiptop_0x03)); ++ eMMC_debug(0, 1, "chiptop_0x51 (0x%X):0x%X\n", reg_chiptop_0x51, REG_FCIE_U16(reg_chiptop_0x51)); ++ eMMC_debug(0, 1, "chiptop_0x6F (0x%X):0x%X\n\n", reg_chiptop_0x6F, REG_FCIE_U16(reg_chiptop_0x6F)); ++ ++ eMMC_debug(0, 1, "chiptop_0x43 (0x%X):0x%X\n", reg_chiptop_0x43, REG_FCIE_U16(reg_chiptop_0x43)); ++ eMMC_debug(0, 1, "chiptop_0x50 (0x%X):0x%X\n", reg_chiptop_0x50, REG_FCIE_U16(reg_chiptop_0x50)); ++ eMMC_debug(0, 1, "chiptop_0x0B (0x%X):0x%X\n", reg_chiptop_0x0B, REG_FCIE_U16(reg_chiptop_0x0B)); ++ eMMC_debug(0, 1, "chiptop_0x5D (0x%X):0x%X\n", reg_chiptop_0x5D, REG_FCIE_U16(reg_chiptop_0x5D)); ++ ++ eMMC_debug(0, 1, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, ++ BIT_MACRO_EN|BIT_SD_DDR_EN|BIT_SD_BYPASS_MODE_EN|BIT_SD_SDR_IN_BYPASS|BIT_SD_FROM_TMUX); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC pads: DDR\n"); ++ ++ REG_FCIE_SETBIT(reg_chiptop_0x43, ++ BIT_PAD_EMMC_CLK_SRC|BIT_eMMC_RSTPIN_VAL); ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, ++ BIT_EMPTY|BIT_eMMC_RSTPIN_EN|BIT_PAD_BYPASS_MACRO); ++ ++ // set DDR mode ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_MACRO_EN|BIT_SD_DDR_EN); ++ // set chiptop ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC pads: SDR\n"); ++ ++ REG_FCIE_SETBIT(reg_chiptop_0x43, ++ BIT_PAD_EMMC_CLK_SRC|BIT_eMMC_RSTPIN_VAL); ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, ++ BIT_EMPTY|BIT_eMMC_RSTPIN_EN|BIT_PAD_BYPASS_MACRO); ++ ++ // set SDR mode ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_MACRO_EN); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC pads: BYPASS\n"); ++ ++ REG_FCIE_SETBIT(reg_chiptop_0x43, ++ BIT_PAD_EMMC_CLK_SRC|BIT_eMMC_RSTPIN_VAL|BIT_PAD_BYPASS_MACRO); ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, ++ BIT_EMPTY|BIT_eMMC_RSTPIN_EN); ++ ++ // set bypadd mode ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, ++ BIT_MACRO_EN|BIT_SD_BYPASS_MODE_EN|BIT_SD_SDR_IN_BYPASS); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ #if 0 ++ REG_FCIE_CLRBIT(reg_chiptop_0x5A, BIT0|BIT1|BIT2); ++ //REG_FCIE_CLRBIT(reg_chiptop_0x1F, BIT0|BIT1); // don't touch for card-detect ++ //REG_FCIE_CLRBIT(reg_chiptop_0x70, BIT2); // don't touch for card-detect ++ REG_FCIE_CLRBIT(reg_chiptop_0x64, BIT0); ++ REG_FCIE_CLRBIT(reg_chiptop_0x4F, BIT13|BIT14); ++ REG_FCIE_CLRBIT(reg_chiptop_0x03, BIT6|BIT7); ++ //REG_FCIE_CLRBIT(reg_chiptop_0x51, BIT10|BIT11); //Cause EAGLE CI card lag issue. ++ REG_FCIE_CLRBIT(reg_chiptop_0x6F, BIT14|BIT15); ++ #endif ++ ++ REG_FCIE_CLRBIT(reg_chiptop_0x50, BIT_NAND_CS1_EN|BIT_ALL_PAD_IN); ++ REG_FCIE_CLRBIT(reg_chiptop_0x0B, BIT_NAND_CS2_EN|BIT_NAND_CS3_EN| ++ BIT_SD0_CFG|BIT_SD0_CFG2|BIT_SD1_CFG|BIT_SD1_CFG2|BIT_NAND_CFG); ++ ++ REG_FCIE_SETBIT(FCIE_REG_2Dh, BIT_NEW_DESIGN_ENn); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{0, BIT_FCIE_CLK4X_20M, BIT_FCIE_CLK4X_27M, 0, ++ BIT_FCIE_CLK4X_36M, BIT_FCIE_CLK4X_40M, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, BIT_FCIE_CLK4X_48M}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid clk: %Xh\n", u16_ClkParam); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx=0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 3 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 3) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp); ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#if 0 ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++#endif ++ ++#include "chip_int.h" ++#include "chip_setup.h" ++#if defined(CONFIG_ARM) // ARM: AMBER3, AGATE ++#include ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ #if 0 ++ U32 dmaaddr; ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ #else ++ extern void ___dma_single_cpu_to_dev(const void *kaddr, size_t size, enum dma_data_direction dir); ++ ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ else ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++ #endif ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eagle SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++//--------------------------------------- ++ ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ // Temp patch for someone driver overwrite the register ++ // The patch for SD card SD_CDZ issue (Eagle). ++ REG_FCIE_SETBIT(reg_chiptop_0x1F, BIT0); ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ //eMMC_clock_setting(FCIE_SLOW_CLK); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #else ++ // as usual ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ // Reset PIU Timer1 ++ REG_FCIE_W(TIMER1_MAX_LOW, 0xFFFF); ++ REG_FCIE_W(TIMER1_MAX_HIGH, 0xFFFF); ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ // Start PIU Timer1 ++ REG_FCIE_W(TIMER1_ENABLE, 0x1); ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ U32 u32HWTimer = 0; ++ U32 u32TimerLow = 0; ++ U32 u32TimerHigh = 0; ++ ++ // Get timer value ++ u32TimerLow = REG_FCIE(TIMER1_CAP_LOW); ++ u32TimerHigh = REG_FCIE(TIMER1_CAP_HIGH); ++ ++ u32HWTimer = (u32TimerHigh<<16) | u32TimerLow; ++ ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ return u32HWTimer; ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 0, "FCIE 1X (0x%X):0x%04X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 0, "FCIE 4X (0x%X):0x%04X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 0, "MIU (0x%X):0x%04X\n", reg_ckg_MIU, REG_FCIE_U16(reg_ckg_MIU)); ++ eMMC_debug(0, 0, "MCU (0x%X):0x%04X\n", reg_ckg_MCU, REG_FCIE_U16(reg_ckg_MCU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ ++ eMMC_debug(0, 0, "reg_all_pad_in (0x%08X):0x%04X\n", reg_all_pad_in, REG_FCIE_U16(reg_all_pad_in)); ++ ++ eMMC_debug(0, 0, "reg_emmc_pad (0x%08X):0x%04X\n", reg_emmc_pad, REG_FCIE_U16(reg_emmc_pad)); ++ eMMC_debug(0, 0, "reg_pcm_d_pe (0x%08X):0x%04X\n", reg_pcm_d_pe, REG_FCIE_U16(reg_pcm_d_pe)); ++ eMMC_debug(0, 0, "reg_pcm_a_pe (0x%08X):0x%04X\n", reg_pcm_a_pe, REG_FCIE_U16(reg_pcm_a_pe)); ++ eMMC_debug(0, 0, "reg_pcm2_cd_n_pe (0x%08X):0x%04X\n", reg_pcm2_cd_n_pe, REG_FCIE_U16(reg_pcm2_cd_n_pe)); ++ ++ eMMC_debug(0, 0, "reg_sd_use_bypass (0x%08X):0x%04X\n", reg_sd_use_bypass, REG_FCIE_U16(reg_sd_use_bypass)); ++ eMMC_debug(0, 0, "reg_fcie2macro_sd_bypass (0x%08X):0x%04X\n", reg_fcie2macro_sd_bypass, REG_FCIE_U16(reg_fcie2macro_sd_bypass)); ++ ++ eMMC_debug(0, 0, "reg_pcmcia_pad (0x%08X):0x%04X\n", reg_pcmcia_pad, REG_FCIE_U16(reg_pcmcia_pad)); ++ eMMC_debug(0, 0, "reg_nand_pad (0x%08X):0x%04X\n", reg_nand_pad, REG_FCIE_U16(reg_nand_pad)); ++ eMMC_debug(0, 0, "reg_sd_pad (0x%08X):0x%04X\n", reg_sd_pad, REG_FCIE_U16(reg_sd_pad)); ++ ++ eMMC_debug(0, 0, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT8|BIT9|BIT10|BIT11|BIT12); ++ REG_FCIE_SETBIT(reg_pcm_d_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm_a_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm2_cd_n_pe, BIT1); // reg_pcm_pe ++ REG_FCIE_CLRBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(reg_sd_use_bypass, BIT0); // reg_sd_use_bypass ++ ++ REG_FCIE_SETBIT(reg_emmc_drv, 0x0007); ++ REG_FCIE_SETBIT(reg_nand_drv, 0xFF00); ++ REG_FCIE_SETBIT(reg_nand_ps, 0xFFFF); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: DDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT9); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: SDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: BYPASS\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT10|BIT11); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ case FCIE_eMMC_TMUX: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: TMUX\n"); ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT10|BIT12); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_TMUX; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ ++ REG_FCIE_CLRBIT(reg_pcmcia_pad, BIT0|BIT4); ++ REG_FCIE_CLRBIT(reg_nand_pad, BIT5|BIT6|BIT7); ++ REG_FCIE_CLRBIT(reg_sd_pad, BIT8|BIT9|BIT10|BIT11); ++ ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT15); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{ ++ 0, ++ BIT_FCIE_CLK4X_20M, ++ BIT_FCIE_CLK4X_27M, ++ 0, ++ BIT_FCIE_CLK4X_36M, ++ BIT_FCIE_CLK4X_40M, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ BIT_FCIE_CLK4X_48M ++}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx = 0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 7 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 7) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ U32 dmaaddr; ++ ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++#if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++#endif ++ ++ return IRQ_NONE; ++ ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ #endif ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eagle SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++ ++//--------------------------------------- ++ ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ // Reset PIU Timer1 ++ REG_FCIE_W(TIMER1_MAX_LOW, 0xFFFF); ++ REG_FCIE_W(TIMER1_MAX_HIGH, 0xFFFF); ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ // Start PIU Timer1 ++ REG_FCIE_W(TIMER1_ENABLE, 0x1); ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ U32 u32HWTimer = 0; ++ U32 u32TimerLow = 0; ++ U32 u32TimerHigh = 0; ++ ++ // Get timer value ++ u32TimerLow = REG_FCIE(TIMER1_CAP_LOW); ++ u32TimerHigh = REG_FCIE(TIMER1_CAP_HIGH); ++ ++ u32HWTimer = (u32TimerHigh<<16) | u32TimerLow; ++ ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ return u32HWTimer; ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 0, "FCIE 1X (0x%X):0x%04X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 0, "FCIE 4X (0x%X):0x%04X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 0, "MIU (0x%X):0x%04X\n", reg_ckg_MIU, REG_FCIE_U16(reg_ckg_MIU)); ++ eMMC_debug(0, 0, "MCU (0x%X):0x%04X\n", reg_ckg_MCU, REG_FCIE_U16(reg_ckg_MCU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ ++ eMMC_debug(0, 0, "reg_all_pad_in (0x%08X):0x%04X\n", reg_all_pad_in, REG_FCIE_U16(reg_all_pad_in)); ++ ++ eMMC_debug(0, 0, "reg_emmc_pad (0x%08X):0x%04X\n", reg_emmc_pad, REG_FCIE_U16(reg_emmc_pad)); ++ eMMC_debug(0, 0, "reg_pcm_d_pe (0x%08X):0x%04X\n", reg_pcm_d_pe, REG_FCIE_U16(reg_pcm_d_pe)); ++ eMMC_debug(0, 0, "reg_pcm_a_pe (0x%08X):0x%04X\n", reg_pcm_a_pe, REG_FCIE_U16(reg_pcm_a_pe)); ++ eMMC_debug(0, 0, "reg_pcm2_cd_n_pe (0x%08X):0x%04X\n", reg_pcm2_cd_n_pe, REG_FCIE_U16(reg_pcm2_cd_n_pe)); ++ ++ eMMC_debug(0, 0, "reg_sd_use_bypass (0x%08X):0x%04X\n", reg_sd_use_bypass, REG_FCIE_U16(reg_sd_use_bypass)); ++ eMMC_debug(0, 0, "reg_fcie2macro_sd_bypass (0x%08X):0x%04X\n", reg_fcie2macro_sd_bypass, REG_FCIE_U16(reg_fcie2macro_sd_bypass)); ++ ++ eMMC_debug(0, 0, "reg_pcmcia_pad (0x%08X):0x%04X\n", reg_pcmcia_pad, REG_FCIE_U16(reg_pcmcia_pad)); ++ eMMC_debug(0, 0, "reg_nand_pad (0x%08X):0x%04X\n", reg_nand_pad, REG_FCIE_U16(reg_nand_pad)); ++ eMMC_debug(0, 0, "reg_sd_pad (0x%08X):0x%04X\n", reg_sd_pad, REG_FCIE_U16(reg_sd_pad)); ++ ++ eMMC_debug(0, 0, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT8|BIT9|BIT10|BIT11|BIT12); ++ REG_FCIE_SETBIT(reg_pcm_d_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm_a_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm2_cd_n_pe, BIT1); // reg_pcm_pe ++ REG_FCIE_CLRBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(reg_sd_use_bypass, BIT0); // reg_sd_use_bypass ++ ++ REG_FCIE_SETBIT(reg_emmc_drv, 0x0007); ++ REG_FCIE_SETBIT(reg_nand_drv, 0xFF00); ++ REG_FCIE_SETBIT(reg_nand_ps, 0xFFFF); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: DDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT9); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: SDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: BYPASS\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT10|BIT11); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ case FCIE_eMMC_TMUX: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: TMUX\n"); ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT10|BIT12); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_TMUX; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ ++ REG_FCIE_CLRBIT(reg_pcmcia_pad, BIT0|BIT4); ++ REG_FCIE_CLRBIT(reg_nand_pad, BIT5|BIT6|BIT7); ++ REG_FCIE_CLRBIT(reg_sd_pad, BIT8|BIT9|BIT10|BIT11); ++ ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT15); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{ ++ 0, ++ BIT_FCIE_CLK4X_20M, ++ BIT_FCIE_CLK4X_27M, ++ 0, ++ BIT_FCIE_CLK4X_36M, ++ BIT_FCIE_CLK4X_40M, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ BIT_FCIE_CLK4X_48M ++}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx = 0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 7 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 7) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ U32 dmaaddr; ++ ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++#if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++#endif ++ ++ return IRQ_NONE; ++ ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ #endif ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eiffel SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++ ++//--------------------------------------- ++ ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ // Reset PIU Timer1 ++ REG_FCIE_W(TIMER1_MAX_LOW, 0xFFFF); ++ REG_FCIE_W(TIMER1_MAX_HIGH, 0xFFFF); ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ // Start PIU Timer1 ++ REG_FCIE_W(TIMER1_ENABLE, 0x1); ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ U32 u32HWTimer = 0; ++ U32 u32TimerLow = 0; ++ U32 u32TimerHigh = 0; ++ ++ // Get timer value ++ u32TimerLow = REG_FCIE(TIMER1_CAP_LOW); ++ u32TimerHigh = REG_FCIE(TIMER1_CAP_HIGH); ++ ++ u32HWTimer = (u32TimerHigh<<16) | u32TimerLow; ++ ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ return u32HWTimer; ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 0, "FCIE 1X (0x%X):0x%04X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 0, "FCIE 4X (0x%X):0x%04X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 0, "MIU (0x%X):0x%04X\n", reg_ckg_MIU, REG_FCIE_U16(reg_ckg_MIU)); ++ eMMC_debug(0, 0, "MCU (0x%X):0x%04X\n", reg_ckg_MCU, REG_FCIE_U16(reg_ckg_MCU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ ++ eMMC_debug(0, 0, "reg_all_pad_in (0x%08X):0x%04X\n", reg_all_pad_in, REG_FCIE_U16(reg_all_pad_in)); ++ ++ eMMC_debug(0, 0, "reg_emmc_pad (0x%08X):0x%04X\n", reg_emmc_pad, REG_FCIE_U16(reg_emmc_pad)); ++ eMMC_debug(0, 0, "reg_pcm_d_pe (0x%08X):0x%04X\n", reg_pcm_d_pe, REG_FCIE_U16(reg_pcm_d_pe)); ++ eMMC_debug(0, 0, "reg_pcm_a_pe (0x%08X):0x%04X\n", reg_pcm_a_pe, REG_FCIE_U16(reg_pcm_a_pe)); ++ eMMC_debug(0, 0, "reg_pcm2_cd_n_pe (0x%08X):0x%04X\n", reg_pcm2_cd_n_pe, REG_FCIE_U16(reg_pcm2_cd_n_pe)); ++ ++ eMMC_debug(0, 0, "reg_sd_use_bypass (0x%08X):0x%04X\n", reg_sd_use_bypass, REG_FCIE_U16(reg_sd_use_bypass)); ++ eMMC_debug(0, 0, "reg_fcie2macro_sd_bypass (0x%08X):0x%04X\n", reg_fcie2macro_sd_bypass, REG_FCIE_U16(reg_fcie2macro_sd_bypass)); ++ ++ eMMC_debug(0, 0, "reg_pcmcia_pad (0x%08X):0x%04X\n", reg_pcmcia_pad, REG_FCIE_U16(reg_pcmcia_pad)); ++ eMMC_debug(0, 0, "reg_nand_pad (0x%08X):0x%04X\n", reg_nand_pad, REG_FCIE_U16(reg_nand_pad)); ++ eMMC_debug(0, 0, "reg_sd_pad (0x%08X):0x%04X\n", reg_sd_pad, REG_FCIE_U16(reg_sd_pad)); ++ ++ eMMC_debug(0, 0, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT8|BIT9|BIT10|BIT11|BIT12); ++ REG_FCIE_SETBIT(reg_pcm_d_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm_a_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm2_cd_n_pe, BIT1); // reg_pcm_pe ++ REG_FCIE_CLRBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(reg_sd_use_bypass, BIT0); // reg_sd_use_bypass ++ ++ REG_FCIE_SETBIT(reg_emmc_drv, 0x0007); ++ REG_FCIE_SETBIT(reg_nand_drv, 0xFF00); ++ REG_FCIE_SETBIT(reg_nand_ps, 0xFFFF); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: DDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT9); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: SDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: BYPASS\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT10|BIT11); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ case FCIE_eMMC_TMUX: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: TMUX\n"); ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT10|BIT12); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_TMUX; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ ++ REG_FCIE_CLRBIT(reg_pcmcia_pad, BIT0|BIT4); ++ REG_FCIE_CLRBIT(reg_nand_pad, BIT5|BIT6|BIT7); ++ REG_FCIE_CLRBIT(reg_sd_pad, BIT8|BIT9|BIT10|BIT11); ++ ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT15); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{ ++ 0, ++ BIT_FCIE_CLK4X_20M, ++ BIT_FCIE_CLK4X_27M, ++ 0, ++ BIT_FCIE_CLK4X_36M, ++ BIT_FCIE_CLK4X_40M, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ BIT_FCIE_CLK4X_48M ++}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx = 0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 7 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 7) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ U32 dmaaddr; ++ ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++#if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++#endif ++ ++ return IRQ_NONE; ++ ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ #endif ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eiffel SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++ ++//--------------------------------------- ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32usTick) ++{ ++ #if 1 //xxx tomodify ++ udelay(u32usTick); ++ #else ++ volatile U32 i = 0; ++ ++ for (i = 0; i < (u32usTick>>4); i++) ++ { ++ #if 0 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #endif ++ ++ return u32usTick + 1; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ // TIMER_FREERUN_32K 32 KHz ++ // TIMER_FREERUN_XTAL 38.4 MHz, ++ // counting down ++ return 0;//HalTimerRead(TIMER_FREERUN_32K); ++} ++//-------------------------------- ++ ++ ++void eMMC_DumpPadClk(void) ++{ ++#if 0 ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 1, "FCIE 1X (0x%X):0x%X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 1, "FCIE 4X (0x%X):0x%X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 1, "CMU (0x%X):0x%X\n", reg_ckg_CMU, REG_FCIE_U16(reg_ckg_CMU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u32_Flag & FCIE_FLAG_PADTYPE_MASK) ++ { ++ case FCIE_FLAG_PADTYPE_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_FLAG_PADTYPE_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_FLAG_PADTYPE_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown\n"); eMMC_die("\n"); ++ } ++ eMMC_debug(0, 1, "chiptop_0x5A (0x%X):0x%X\n", reg_chiptop_0x5A, REG_FCIE_U16(reg_chiptop_0x5A)); ++ eMMC_debug(0, 1, "chiptop_0x1F (0x%X):0x%X\n", reg_chiptop_0x1F, REG_FCIE_U16(reg_chiptop_0x1F)); ++ eMMC_debug(0, 1, "chiptop_0x70 (0x%X):0x%X\n", reg_chiptop_0x70, REG_FCIE_U16(reg_chiptop_0x70)); ++ eMMC_debug(0, 1, "chiptop_0x64 (0x%X):0x%X\n", reg_chiptop_0x64, REG_FCIE_U16(reg_chiptop_0x64)); ++ eMMC_debug(0, 1, "chiptop_0x4F (0x%X):0x%X\n", reg_chiptop_0x4F, REG_FCIE_U16(reg_chiptop_0x4F)); ++ eMMC_debug(0, 1, "chiptop_0x03 (0x%X):0x%X\n", reg_chiptop_0x03, REG_FCIE_U16(reg_chiptop_0x03)); ++ eMMC_debug(0, 1, "chiptop_0x51 (0x%X):0x%X\n", reg_chiptop_0x51, REG_FCIE_U16(reg_chiptop_0x51)); ++ eMMC_debug(0, 1, "chiptop_0x6F (0x%X):0x%X\n\n", reg_chiptop_0x6F, REG_FCIE_U16(reg_chiptop_0x6F)); ++ ++ eMMC_debug(0, 1, "chiptop_0x43 (0x%X):0x%X\n", reg_chiptop_0x43, REG_FCIE_U16(reg_chiptop_0x43)); ++ eMMC_debug(0, 1, "chiptop_0x50 (0x%X):0x%X\n", reg_chiptop_0x50, REG_FCIE_U16(reg_chiptop_0x50)); ++ eMMC_debug(0, 1, "chiptop_0x0B (0x%X):0x%X\n", reg_chiptop_0x0B, REG_FCIE_U16(reg_chiptop_0x0B)); ++ eMMC_debug(0, 1, "chiptop_0x5D (0x%X):0x%X\n", reg_chiptop_0x5D, REG_FCIE_U16(reg_chiptop_0x5D)); ++ ++ eMMC_debug(0, 1, "\n"); ++#endif ++} ++ ++U8 gu8_NANDeMMC_need_preset_flag = 1; ++#define BIT_BOOT_CONFIG_MODE_MASK BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ //only for Cedric eMMC ++ if (gu8_NANDeMMC_need_preset_flag == 1) ++ { ++ eMMC_printf("========== gu8_NANDeMMC_need_preset_flag = 1 =========="); ++ //REG_FCIE_SETBIT(FCIE_REG_2Dh, BIT_NEW_DESIGN_ENn); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT3); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_10us); ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT3); ++ ++ gu8_NANDeMMC_need_preset_flag = 0; ++ } ++ ++ ++ ++// REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, ++// BIT_MACRO_EN|BIT_SD_DDR_EN|BIT_SD_BYPASS_MODE_EN|BIT_SD_SDR_IN_BYPASS|BIT_SD_FROM_TMUX); ++ ++ switch(u32_FCIE_IF_Type) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_printf("eMMC_pads_switch FCIE_eMMC_DDR\r\n"); ++ #define R_DDR_MODE BIT_MACRO_EN | BIT_SD_DDR_EN ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_BOOT_CONFIG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, R_DDR_MODE); ++ REG_FCIE_SETBIT(RIU_BASE_CHIPTOP + (0x4 << 2), BIT1); ++ REG_FCIE_CLRBIT(REG_BPS_MODE, 0x3FF); ++ REG_FCIE_CLRBIT(REG_ALL_PAD_IN, BIT0); ++ REG_FCIE_SETBIT(REG_EMMC_MODE, BIT13); ++ ++ REG_FCIE_SETBIT(eMMC_REG_CLK_4X_DIV_EN, BIT0); ++ ++ // set chiptop ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_printf("eMMC_pads_switch FCIE_eMMC_SDR\r\n"); ++ #define R_SDR_MODE BIT_MACRO_EN ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_BOOT_CONFIG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, R_SDR_MODE); ++ REG_FCIE_SETBIT(RIU_BASE_CHIPTOP + (0x4 << 2), BIT1); ++ REG_FCIE_CLRBIT(REG_BPS_MODE, 0x3FF); ++ REG_FCIE_CLRBIT(REG_ALL_PAD_IN, BIT0); ++ REG_FCIE_SETBIT(REG_EMMC_MODE, BIT13); ++ REG_FCIE_SETBIT(eMMC_REG_CLK_4X_DIV_EN, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_printf("eMMC_pads_switch FCIE_eMMC_BYPASS\r\n"); ++ #define R_BYPASS_MODE BIT_MACRO_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_BOOT_CONFIG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, R_BYPASS_MODE); ++ REG_FCIE_SETBIT(RIU_BASE_CHIPTOP + (0x4 << 2), BIT1); ++ REG_FCIE_SETBIT(REG_BPS_MODE, 0x3FF); ++ REG_FCIE_CLRBIT(REG_ALL_PAD_IN, BIT0); ++ REG_FCIE_SETBIT(REG_EMMC_MODE, BIT13); ++ REG_FCIE_CLRBIT(eMMC_REG_CLK_4X_DIV_EN, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_SETBIT(FCIE_REG_2Dh, BIT_NEW_DESIGN_ENn); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_24M: g_eMMCDrv.u32_ClkKHz = 24000; break; ++ case BIT_FCIE_CLK_12M: g_eMMCDrv.u32_ClkKHz = 12000; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ case BIT_FCIE_CLK_86M: g_eMMCDrv.u32_ClkKHz = 86000; break; ++ case BIT_FCIE_CLK_108M: g_eMMCDrv.u32_ClkKHz = 108000; break; ++ case BIT_FCIE_CLK_123M: g_eMMCDrv.u32_ClkKHz = 123000; break; ++ case BIT_FCIE_CLK_144M: g_eMMCDrv.u32_ClkKHz = 144000; break; ++ case BIT_FCIE_CLK_172M: g_eMMCDrv.u32_ClkKHz = 172000; break; ++ case BIT_FCIE_CLK_192M: g_eMMCDrv.u32_ClkKHz = 192000; break; ++ case BIT_FCIE_CLK_216M: g_eMMCDrv.u32_ClkKHz = 216000; break; ++ case BIT_FCIE_CLK_240M: g_eMMCDrv.u32_ClkKHz = 240000; break; ++ case BIT_FCIE_CLK_345M: g_eMMCDrv.u32_ClkKHz = 345000; break; ++ case BIT_FCIE_CLK_432M: g_eMMCDrv.u32_ClkKHz = 432000; break; ++ case BIT_FCIE_CLK_1200K: g_eMMCDrv.u32_ClkKHz = 1200; break; ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_54M: g_eMMCDrv.u32_ClkKHz = 54000; break; ++ case BIT_FCIE_CLK_62M: g_eMMCDrv.u32_ClkKHz = 62000; break; ++ case BIT_FCIE_CLK_72M: g_eMMCDrv.u32_ClkKHz = 72000; break; ++ case BIT_FCIE_CLK_80M: g_eMMCDrv.u32_ClkKHz = 80000; break; ++ ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid clk: %Xh\n", u16_ClkParam); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_W(REG_CLK_EMMC, (u16_ClkParam)); ++ g_eMMCDrv.u16_ClkRegVal = (U16)u16_ClkParam; ++ ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_clock_gating(void) ++{ ++ eMMC_PlatformResetPre(); ++ g_eMMCDrv.u32_ClkKHz = 0; ++ REG_FCIE_W(REG_CLK_EMMC, BIT_FCIE_CLK_Gate); ++ //REG_FCIE_W(reg_ckg_fcie_4X, BIT_FCIE_CLK4X_Gate); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U16 gau16_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT]={ ++ ++ BIT_FCIE_CLK_192M, BIT_FCIE_CLK_172M, /*BIT_FCIE_CLK_144M,*/ BIT_FCIE_CLK_123M, /*BIT_FCIE_CLK_108M,*/ ++ BIT_FCIE_CLK_86M, /*BIT_FCIE_CLK_80M, BIT_FCIE_CLK_72M,*/ BIT_FCIE_CLK_62M, BIT_FCIE_CLK_54M, ++ /*BIT_FCIE_CLK_48M, BIT_FCIE_CLK_43_2M,*/ BIT_FCIE_CLK_40M, /*BIT_FCIE_CLK_36M,*/ BIT_FCIE_CLK_32M, ++ BIT_FCIE_CLK_24M, BIT_FCIE_CLK_12M/*, BIT_FCIE_CLK_1200K, BIT_FCIE_CLK_300K*/ ++}; ++#define FCIE_SLOW_CLK_4X BIT_FCIE_CLK_12M ++ ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++static char *sgachar_string[]={" 2T", "1.5T", "2.5T"," 1T"}; ++ ++static U32 eMMC_FCIE_DetectDDRTiming_Ex(U8 u8_DQS, U8 u8_DelaySel) ++{ ++ U32 u32_SectorAddr; ++ ++ //eMMC_printf("eMMC_FCIE_DetectDDRTiming_Ex\r\n"); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ ++ //eMMC_printf("eMMC_TEST_BLK_0: %X\r\n", u32_SectorAddr); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\ndqs:%s[%Xh] cell:%02Xh \n", ++ sgachar_string[u8_DQS], u8_DQS, u8_DelaySel); ++ ++ eMMC_FCIE_SetDDRTimingReg(u8_DQS, u8_DelaySel); ++ return eMMCTest_BlkWRC_ProbeDDR(u32_SectorAddr); ++} ++ ++#define FCIE_DELAY_CELL_ts 300 // 0.3ns ++static eMMC_FCIE_DDRT_WINDOW_t sg_DDRTWindow[2]; ++ ++U32 eMMC_FCIE_DetectDDRTiming(void) ++{ ++ U8 u8_dqs, u8_delay_sel, u8_i; ++ U8 u8_dqs_prev=0xFF, u8_delay_sel_prev=0; ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 au8_DQS_10T[4]={0,15,20,25}; // 0T, 1.5T, 2T, 2.5T ++ ++ U8 u8_delay_Sel_max; ++ U32 u32_ts; ++ U32 u32_err; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow = &sg_DDRTWindow[0]; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_TUNING; // just to turn off some log ++ ++ //-------------------------------------------------- ++ sg_DDRTWindow[0].u8_Cnt = 0; ++ sg_DDRTWindow[0].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[0].aParam[1].u8_DQS = 0; ++ sg_DDRTWindow[1].u8_Cnt = 0; ++ sg_DDRTWindow[1].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[1].aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++// u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ eMMC_printf("u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)\r\n"); ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_printf("DetectDDRTiming pass\r\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_SUCCESS; ++ } ++ else ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ } ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx=0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ //eMMC_printf("eMMC Info: building DDR table, please wait... \n"); ++ ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ ++ ++ //iantest ttt ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE)) ++ { ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //RETAILMSG(1, (TEXT("eMMC Error: set DDR IF fail: %Xh\r\n"),u32_err)); ++ eMMC_printf("eMMC Error: set DDR IF fail: %Xh\r\n",u32_err); ++ return u32_err; ++ } ++ } ++ ++ eMMC_pads_switch(FCIE_eMMC_DDR); //iantest ttt ++ //iantest ttt ++ ++ ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 3 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 3) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK_4X == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk) ++ { ++ eMMC_printf("FCIE_SLOW_CLK_4X == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk\r\n"); ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ } ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ ++ eMMC_printf("gau16_FCIEClkSel[0] : %X\r\n", gau16_FCIEClkSel[0]); ++ eMMC_printf("g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk : %X\r\n", g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk); ++ eMMC_printf("g_eMMCDrv.DDRTable.u8_SetCnt : %X\r\n", g_eMMCDrv.DDRTable.u8_SetCnt); ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk == gau16_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk != gau16_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ eMMC_FCIE_EnableSDRMode(); ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++#define MSTAR_MIU0_BUS_BASE 0x40000000 ++#define MSTAR_MIU1_BUS_BASE 0xA0000000 ++ ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++#if 1 ++ extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ //mode 0 for write, 1 for read ++ if( mode == WRITE_TO_eMMC ) //Write ++ { ++ //Write (DRAM->NAND)-> flush ++ Chip_Clean_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ else //Read ++ { ++ //Read (NAND->DRAM) -> inv ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ /* ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ { ++ REG_SET_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ } ++ else ++ REG_CLR_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ */ ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++#else ++ flush_cache(u32_DMAAddr, u32_ByteCnt); ++ return (u32_DMAAddr); ++#endif ++} ++ ++/* ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ flush_cache(u32_addr, s32_size); ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++*/ ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i ++//extern struct semaphore PfModeSem; ++extern struct mutex FCIE3_mutex; ++//#define CRIT_SECT_BEGIN(x) mutex_lock(x) ++//#define CRIT_SECT_END(x) mutex_unlock(x) ++ ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ mutex_lock(&FCIE3_mutex); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ mutex_unlock(&FCIE3_mutex); ++ ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32usTick) ++{ ++ volatile U32 u32_i=u32usTick; ++ ++ while(u32_i>1000) ++ { ++ udelay(1000); ++ u32_i-=1000; ++ } ++ ++ udelay(u32usTick); ++ return u32usTick + 1; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ return 0; ++} ++//-------------------------------- ++ ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 1, "FCIE 1X (0x%X):0x%X\n", REG_CLK_EMMC, REG_FCIE_U16(REG_CLK_EMMC)); ++ eMMC_debug(0, 1, "FCIE 4X (0x%X):0x%X\n", REG_CLK_4X_DIV_EN, REG_FCIE_U16(REG_CLK_4X_DIV_EN)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); ++ break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); ++ break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); ++ break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown\n"); ++ eMMC_die("\n"); ++ } ++ eMMC_debug(0, 1, "padtop_0x00 (0x%X):0x%X\n", REG_PADTOP_00, REG_FCIE_U16(REG_PADTOP_00)); ++ eMMC_debug(0, 1, "padtop_0x01 (0x%X):0x%X\n", REG_PADTOP_01, REG_FCIE_U16(REG_PADTOP_01)); ++ eMMC_debug(0, 1, "padtop_0x40 (0x%X):0x%X\n", REG_PADTOP_40, REG_FCIE_U16(REG_PADTOP_40)); ++ eMMC_debug(0, 1, "padtop_0x43 (0x%X):0x%X\n", REG_PADTOP_43, REG_FCIE_U16(REG_PADTOP_43)); ++ eMMC_debug(0, 1, "chiptop_0x31 (0x%X):0x%X\n", REG_RESET_PIN, REG_FCIE_U16(REG_RESET_PIN)); ++ ++ eMMC_debug(0, 1, "fcie_0x2F (0x%X):0x%X\n", FCIE_BOOT_CONFIG, REG_FCIE_U16(FCIE_BOOT_CONFIG)); ++ eMMC_debug(0, 1, "fcie_0x2D (0x%X):0x%X\n", FCIE_REG_2Dh, REG_FCIE_U16(FCIE_REG_2Dh)); ++ ++ ++ eMMC_debug(0, 1, "\n"); ++ ++} ++ ++U8 gu8_NANDeMMC_need_preset_flag = 1; ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ U16 u16_reg; ++ switch(u32_FCIE_IF_Type) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"eMMC_pads_switch FCIE_eMMC_DDR\r\n"); ++ REG_FCIE_R(FCIE_BOOT_CONFIG, u16_reg); ++ u16_reg &= ~(BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX); ++ u16_reg |= (BIT_MACRO_EN | BIT_SD_DDR_EN); ++ REG_FCIE_W(FCIE_BOOT_CONFIG, u16_reg); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT14); ++ ++ //CLRREG16(FCIE_BOOT_CONFIG, BIT3); //to MIU ++ REG_FCIE_R(REG_PADTOP_00, u16_reg); ++ u16_reg |= BIT15; ++ u16_reg &= ~(BIT0 + BIT14); ++ REG_FCIE_W(REG_PADTOP_00, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_01, u16_reg); ++ u16_reg &= ~(BIT3); ++ REG_FCIE_W(REG_PADTOP_01, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_40, u16_reg); ++ u16_reg &= ~(BIT3 + BIT8 + BIT9); ++ REG_FCIE_W(REG_PADTOP_40, u16_reg); ++ ++ REG_FCIE_SETBIT(REG_PADTOP_43, BIT3); ++ ++ REG_FCIE_SETBIT(REG_CLK_4X_DIV_EN, BIT0); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"eMMC_pads_switch FCIE_eMMC_SDR\r\n"); ++ REG_FCIE_R(FCIE_BOOT_CONFIG, u16_reg); ++ u16_reg &= ~(BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX); ++ u16_reg |= (BIT_MACRO_EN); ++ REG_FCIE_W(FCIE_BOOT_CONFIG, u16_reg); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT14); ++ ++ //CLRREG16(FCIE_BOOT_CONFIG, BIT3); //to MIU ++ REG_FCIE_R(REG_PADTOP_00, u16_reg); ++ u16_reg |= BIT15; ++ u16_reg &= ~(BIT0 + BIT14); ++ REG_FCIE_W(REG_PADTOP_00, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_01, u16_reg); ++ u16_reg &= ~(BIT3); ++ REG_FCIE_W(REG_PADTOP_01, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_40, u16_reg); ++ u16_reg &= ~(BIT3 + BIT8 + BIT9); ++ REG_FCIE_W(REG_PADTOP_40, u16_reg); ++ ++ REG_FCIE_SETBIT(REG_PADTOP_43, BIT3); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"eMMC_pads_switch FCIE_eMMC_BYPASS\r\n"); ++ REG_FCIE_R(FCIE_BOOT_CONFIG, u16_reg); ++ u16_reg &= ~(BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX); ++ u16_reg |= (BIT_MACRO_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS); ++ REG_FCIE_W(FCIE_BOOT_CONFIG, u16_reg); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT14); ++ ++ //CLRREG16(FCIE_BOOT_CONFIG, BIT3); //to MIU ++ ++ REG_FCIE_R(REG_PADTOP_00, u16_reg); ++ u16_reg |= BIT15; ++ u16_reg &= ~(BIT0 + BIT14); ++ REG_FCIE_W(REG_PADTOP_00, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_01, u16_reg); ++ u16_reg &= ~(BIT3); ++ REG_FCIE_W(REG_PADTOP_01, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_40, u16_reg); ++ u16_reg |= (BIT3 + BIT8 + BIT9); ++ REG_FCIE_W(REG_PADTOP_40, u16_reg); ++ ++ REG_FCIE_SETBIT(REG_PADTOP_43, BIT3); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_SETBIT(REG_CLK_4X_DIV_EN, BIT0); ++ ++ switch(u16_ClkParam) { ++ case NFIE_REG_4XCLK_1_3M: g_eMMCDrv.u32_ClkKHz = 1300; break; ++ case NFIE_REG_4XCLK_26M: g_eMMCDrv.u32_ClkKHz = 26000; break; ++ case NFIE_REG_4XCLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ case NFIE_REG_4XCLK_80M: g_eMMCDrv.u32_ClkKHz = 80000; break; ++ case NFIE_REG_4XCLK_96M: g_eMMCDrv.u32_ClkKHz = 96000; break; ++ case NFIE_REG_4XCLK_120M: g_eMMCDrv.u32_ClkKHz = 120000; break; ++ case NFIE_REG_4XCLK_147M: g_eMMCDrv.u32_ClkKHz = 147000; break; ++ case NFIE_REG_4XCLK_160M: g_eMMCDrv.u32_ClkKHz = 160000; break; ++ case NFIE_REG_4XCLK_176_8M: g_eMMCDrv.u32_ClkKHz = 176800; break; ++ case NFIE_REG_4XCLK_192M: g_eMMCDrv.u32_ClkKHz = 192000; break; ++ case NFIE_REG_4XCLK_221M: g_eMMCDrv.u32_ClkKHz = 221000; break; ++ case NFIE_REG_4XCLK_240M: g_eMMCDrv.u32_ClkKHz = 240000; break; ++ case NFIE_REG_4XCLK_294_6M: g_eMMCDrv.u32_ClkKHz = 294600; break; ++ case NFIE_REG_4XCLK_353_6M: g_eMMCDrv.u32_ClkKHz = 353600; break; ++ case NFIE_REG_4XCLK_60M: g_eMMCDrv.u32_ClkKHz = 60000; break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid clk: %Xh\n", u16_ClkParam); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ //printf("REG_CLK_EMMC : %X, %uKHZ\r\n", u16_ClkParam, g_eMMCDrv.u32_ClkKHz/4); ++ ++ REG_FCIE_W(REG_CLK_EMMC, (u16_ClkParam)); ++ g_eMMCDrv.u16_ClkRegVal = (U16)u16_ClkParam; ++ ++ ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_clock_gating(void) ++{ ++ eMMC_PlatformResetPre(); ++ g_eMMCDrv.u32_ClkKHz = 0; ++ REG_FCIE_W(REG_CLK_EMMC, BIT_FCIE_CLK_Gate); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U16 gau16_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT]={ ++ NFIE_REG_4XCLK_192M, NFIE_REG_4XCLK_160M, NFIE_REG_4XCLK_120M, ++ NFIE_REG_4XCLK_96M ,NFIE_REG_4XCLK_80M ++ ++}; ++ ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++static char *sgachar_string[]={" 0T", "0.5T", " 1T", "1.5T", " 2T", "2.5T", " 3T", "3.5T"}; ++ ++static U32 eMMC_FCIE_DetectDDRTiming_Ex(U8 u8_DQS, U8 u8_DelaySel) ++{ ++ U32 u32_SectorAddr; ++ ++ //eMMC_printf("eMMC_FCIE_DetectDDRTiming_Ex\r\n"); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ ++ //eMMC_printf("eMMC_TEST_BLK_0: %X\r\n", u32_SectorAddr); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\ndqs:%s[%Xh] cell:%02Xh \n", ++ sgachar_string[u8_DQS], u8_DQS, u8_DelaySel); ++ ++ eMMC_FCIE_SetDDRTimingReg(u8_DQS, u8_DelaySel); ++ return eMMCTest_BlkWRC_ProbeDDR(u32_SectorAddr); ++} ++ ++#define FCIE_DELAY_CELL_ts 300 // 0.3ns ++static eMMC_FCIE_DDRT_WINDOW_t sg_DDRTWindow[2]; ++ ++U32 eMMC_FCIE_DetectDDRTiming(void) ++{ ++ U8 u8_dqs, u8_delay_sel, u8_i; ++ U8 u8_dqs_prev=0xFF, u8_delay_sel_prev=0; ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3,5T ++ U8 au8_DQS_10T[8]={0,5,10,15,20,25,30,35}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3,5T ++ ++ U8 u8_delay_Sel_max; ++ U32 u32_ts; ++ U32 u32_err; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow = &sg_DDRTWindow[0]; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_TUNING; // just to turn off some log ++ ++ //-------------------------------------------------- ++ sg_DDRTWindow[0].u8_Cnt = 0; ++ sg_DDRTWindow[0].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[0].aParam[1].u8_DQS = 0; ++ sg_DDRTWindow[1].u8_Cnt = 0; ++ sg_DDRTWindow[1].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[1].aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++// u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ eMMC_printf("u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)\r\n"); ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_printf("DetectDDRTiming pass\r\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_SUCCESS; ++ } ++ else ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ } ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx=0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ //eMMC_printf("eMMC Info: building DDR table, please wait... \n"); ++ ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ ++ ++ //iantest ttt ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE)) ++ { ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //RETAILMSG(1, (TEXT("eMMC Error: set DDR IF fail: %Xh\r\n"),u32_err)); ++ eMMC_printf("eMMC Error: set DDR IF fail: %Xh\r\n",u32_err); ++ return u32_err; ++ } ++ } ++ ++ eMMC_pads_switch(FCIE_eMMC_DDR); //iantest ttt ++ //iantest ttt ++ ++ ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 3 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 3) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk) ++ { ++ eMMC_printf("FCIE_SLOW_CLK_4X == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk\r\n"); ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ } ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ ++ eMMC_printf("gau16_FCIEClkSel[0] : %X\r\n", gau16_FCIEClkSel[0]); ++ eMMC_printf("g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk : %X\r\n", g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk); ++ eMMC_printf("g_eMMCDrv.DDRTable.u8_SetCnt : %X\r\n", g_eMMCDrv.DDRTable.u8_SetCnt); ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk == gau16_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk != gau16_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ eMMC_FCIE_EnableSDRMode(); ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++#if 1 ++ extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ //mode 0 for write, 1 for read ++ if( mode == WRITE_TO_eMMC ) //Write ++ { ++ //Write (DRAM->NAND)-> flush ++ Chip_Clean_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ else //Read ++ { ++ //Read (NAND->DRAM) -> inv ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ /* ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ { ++ REG_SET_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ } ++ else ++ REG_CLR_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ */ ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++#else ++ flush_cache(u32_DMAAddr, u32_ByteCnt); ++ return (u32_DMAAddr); ++#endif ++} ++ ++/* ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ flush_cache(u32_addr, s32_size); ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++*/ ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ else if(u16_Events & BIT_SD_BUSY_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_BUSY_END); ++ REG_FCIE_CLRBIT(FCIE_SD_CTRL, BIT_SD_BUSY_DET_ON); ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ #endif ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i ++//extern struct semaphore PfModeSem; ++extern struct mutex FCIE3_mutex; ++//#define CRIT_SECT_BEGIN(x) mutex_lock(x) ++//#define CRIT_SECT_END(x) mutex_unlock(x) ++ ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ mutex_lock(&FCIE3_mutex); ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ mutex_unlock(&FCIE3_mutex); ++} ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ #if defined(ENABLE_EMMC_POWER_SAVING_MODE) && ENABLE_EMMC_POWER_SAVING_MODE ++ eMMC_Prepare_Power_Saving_Mode_Queue(); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++#include ++#include ++ ++#include "mstar_mci.h" ++#include "linux/mmc/card.h" ++#include "ms_platform.h" ++ ++/****************************************************************************** ++ * Defines ++ ******************************************************************************/ ++#define MCI_RETRY_CNT_CMD_TO 100 ++#define MCI_RETRY_CNT_CRC_ERR 200 // avoid stack overflow ++#define MCI_RETRY_CNT_OK_CLK_UP 10 ++/****************************************************************************** ++ * Function Prototypes ++ ******************************************************************************/ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st); ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st); ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st); ++#endif ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st); ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st); ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st); ++static u32 mstar_mci_WaitD0High(u32 u32_us); ++static U32 u32_ok_cnt=0; ++ ++static U32 MIU0_BUS_ADDR=0; ++/***************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++/* MSTAR Multimedia Card Interface Operations */ ++static const struct mmc_host_ops sg_mstar_mci_ops = ++{ ++ .request = mstar_mci_request, ++ .set_ios = mstar_mci_set_ios, ++ .get_ro = mstar_mci_get_ro, ++}; ++ ++/****************************************************************************** ++ * Functions ++ ******************************************************************************/ ++ ++static int mstar_mci_get_dma_dir(struct mmc_data *data) ++{ ++ if (data->flags & MMC_DATA_WRITE) ++ return DMA_TO_DEVICE; ++ else ++ return DMA_FROM_DEVICE; ++} ++ ++static void mstar_mci_pre_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct scatterlist *pSG_st = 0; ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ u32 u32_dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ pSG_st = &pData_st->sg[0]; ++ dmaaddr = (u32)sg_dma_address(pSG_st); ++ u32_dmalen = sg_dma_len(pSG_st); ++ u32_dmalen = ((u32_dmalen&0x1FF)?1:0) + u32_dmalen/512; ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_R_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ eMMC_FCIE_FifoClkRdy(0); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++} ++ ++ ++static U32 mstar_mci_post_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ int err = eMMC_ST_SUCCESS; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ pSG_st = &(pData_st->sg[0]); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ return err; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ // [WHY] not dma_map_sg ? ++ for(i=1; isg_len; i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ pSG_st = &(pData_st->sg[i]); ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT,(dmalen/512)); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, ++ eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ goto dma_read_end; ++ ++ } ++ pData_st->bytes_xfered += pSG_st->length; ++ } ++ ++ dma_read_end: ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ if( !err ) // success ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++ return err; ++} ++ ++static U32 mstar_mci_dma_write(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_W_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ ++ for(i=0; isg_len; i++) ++ { ++ pSG_st = &(pData_st->sg[i]); ++ ++ dmaaddr = sg_dma_address(pSG_st); ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ dmalen = sg_dma_len(pSG_st); ++ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, (dmalen >> eMMC_SECTOR_BYTECNT_BITS)); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, (dmaaddr & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, (dmaaddr >> 16)); ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ if(0==i) ++ eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END, ++ eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ ++ } ++ pData_st->bytes_xfered += pSG_st->length; ++ } ++ dma_write_end: ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ ++ if( !err ) ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++ return err; ++ ++} ++ ++ ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ u16 u16_st, u16_i; ++ u8 *pTemp; ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ static u32 u32_retry_cnt=0, u32_run_cnt=0; ++ ++ u32_run_cnt++; ++ // ---------------------------------- ++ // retrun response from FCIE to mmc driver ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3 - (u16_i % 4)) + (4 * (u16_i / 4))] = ++ (u8)(REG_FCIE(FCIE1_BASE+(((u16_i+1)/2)*4)) >> (8*((u16_i+1)%2))); ++ } ++ #if 0 ++ eMMC_debug(0,0,"------------------\n"); ++ eMMC_dump_mem(pTemp, 0x10); ++ eMMC_debug(0,0,"------------------\n"); ++ #endif ++ ++ // ---------------------------------- ++ u16_st = REG_FCIE(FCIE_SD_STATUS); ++ if((u16_st & BIT_SD_FCIE_ERR_FLAGS) || (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ if((u16_st & BIT_SD_RSP_CRC_ERR) && !(mmc_resp_type(pCmd_st) & MMC_RSP_CRC)) ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ else ++ { ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: ST:%Xh, CMD:%u, retry: %u, flag: %Xh, R1 err: %Xh\n", ++ u16_st, pCmd_st->opcode, u32_retry_cnt, g_eMMCDrv.u32_DrvFlag, ++ pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY); ++ ++ u32_ok_cnt = 0; ++ if(u32_retry_cnt++ >= MCI_RETRY_CNT_CRC_ERR) ++ eMMC_FCIE_ErrHandler_Stop(); // fatal error ++ ++ if(25==pCmd_st->opcode || 12==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_hw_timer_sleep(1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ ++ if(0 != pCmd_st->data) ++ { ++ eMMC_FCIE_ErrHandler_Retry(); // slow dwon clock ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ } ++ else // for CMD12 ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: no data, just reset eMMC. \n"); ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ if(0==u32_retry_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: retry ok \n"); ++ return; ++ } ++ ++ //----------------------------------------- ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: ST:%Xh, CMD:%u, retry:%u \n", ++ u16_st, pCmd_st->opcode, pCmd_st->retries); ++ #endif ++ ++ ++ if(u16_st & (BIT_SD_RSP_TIMEOUT | BIT_SD_W_FAIL)) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ } ++ else if(u16_st & (BIT_SD_RSP_CRC_ERR | BIT_SD_R_CRC_ERR | BIT_SD_W_CRC_ERR)) ++ { ++ pCmd_st->error = -EILSEQ; ++ } ++ else ++ { ++ pCmd_st->error = -EIO; ++ } ++ } ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ ++ if((pCmd_st->opcode == 17) || (pCmd_st->opcode == 18) //read ++ ||(pCmd_st->opcode == 24) || (pCmd_st->opcode == 25) //write ++ ||(pCmd_st->opcode == 12)) //stop transmission ++ { ++ if(pCmd_st->resp[0] & eMMC_ERR_R1_31_0) ++ { ++ pCmd_st->error |= -EIO; ++ ++ if(pCmd_st->opcode == 12) ++ eMMC_debug(0,0, "eMMC Warn: CMD12 R1 error: %Xh \n", ++ pCmd_st->resp[0]); ++ else ++ eMMC_debug(0,0, "eMMC Warn: CMD%u R1 error: %Xh, arg %08x, blocks %08x\n", ++ pCmd_st->opcode, pCmd_st->resp[0], pCmd_st->arg, pCmd_st->data->blocks); ++ } ++ } ++ ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++} ++ ++ ++#define WAIT_D0H_POLLING_TIME HW_TIMER_DELAY_500us ++u32 mstar_mci_WaitD0High(u32 u32_us) ++{ ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // enable busy int ++ REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_BUSY_DET_ON); ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_SD_BUSY_END); ++ #endif ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_BUSY_END,u32_us) != eMMC_ST_SUCCESS) ++ { ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ return eMMC_ST_SUCCESS; ++ #else ++ u32 u32_cnt, u32_wait; ++ ++ for(u32_cnt=0; u32_cnt HW_TIMER_DELAY_1ms) ++ { ++ msleep(1); ++ u32_cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ #endif ++} ++ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st) ++{ ++ struct mmc_data *pData_st; ++ u32 u32_mie_int=0, u32_sd_ctl=0, u32_sd_mode; ++ u8 u8_retry_cmd=0, u8_retry_D0H=0; ++ u8 u8_retry_data=0; ++ u32 err = 0; ++ ++ LABEL_SEND_CMD: ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ u32_sd_mode = g_eMMCDrv.u16_Reg10_Mode; ++ pMStarHost_st->cmd = pCmd_st; ++ pData_st = pCmd_st->data; ++ ++ ++ eMMC_FCIE_ClearEvents(); ++ if(12!=pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(HW_TIMER_DELAY_500ms)) ++ { ++ u32_ok_cnt = 0; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ u8_retry_D0H++; ++ if(u8_retry_D0H < 10) ++ { ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ } ++ if(u8_retry_D0H) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: wait D0 H [ok]\n"); ++ u8_retry_D0H = 0; ++ } ++ ++ ++ if(pData_st) ++ { ++ pData_st->bytes_xfered = 0; ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE|(u16)pData_st->blksz); ++ ++ if (pData_st->flags & MMC_DATA_READ) ++ { ++ u32_sd_ctl |= BIT_SD_DAT_EN; ++ ++ // Enable stoping read clock when using scatter list DMA ++ if((pData_st->sg_len > 1) && (pCmd_st->opcode == 18)) ++ u32_sd_mode |= BIT_SD_DMA_R_CLK_STOP; ++ else ++ u32_sd_mode &= ~BIT_SD_DMA_R_CLK_STOP; ++ ++ mstar_mci_pre_dma_read(pMStarHost_st); ++ } ++ } ++ ++ u32_sd_ctl |= BIT_SD_CMD_EN; ++ u32_mie_int |= BIT_SD_CMD_END; ++ REG_FCIE_W(FCIE_CIFC_ADDR(0), (((pCmd_st->arg >> 24)<<8) | (0x40|pCmd_st->opcode))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), ((pCmd_st->arg & 0xFF00) | ((pCmd_st->arg>>16)&0xFF))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), (pCmd_st->arg & 0xFF)); ++ ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_NONE) ++ { ++ u32_sd_ctl &= ~BIT_SD_RSP_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 0); ++ } ++ else ++ { ++ u32_sd_ctl |= BIT_SD_RSP_EN; ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_R2) ++ { ++ u32_sd_ctl |= BIT_SD_RSPR2_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 16); /* (136-8)/8 */ ++ } ++ else ++ { ++ REG_FCIE_W(FCIE_RSP_SIZE, 5); /*(48-8)/8 */ ++ } ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC: INT_EN: %Xh\n", u32_mie_int); ++ REG_FCIE_W(FCIE_MIE_INT_EN, u32_mie_int); ++ #endif ++ ++ #if 0 ++ eMMC_debug(0,0,"\n"); ++ eMMC_debug(0,0,"cmd:%u, arg:%Xh, databuf:%Xh\n", ++ pCmd_st->opcode, pCmd_st->arg, (u32)pData_st); ++ //while(1); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_MODE, u32_sd_mode); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl); ++ // [FIXME]: retry and timing, and omre... ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, ++ HW_TIMER_DELAY_1s) != eMMC_ST_SUCCESS|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ // ------------------------------------ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if(NULL==pData_st) // no data, no retry ++ { ++ mstar_mci_completed_command(pMStarHost_st); ++ return; ++ } ++ #endif ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: cmd.%u arg.%Xh, retry %u \n", ++ pCmd_st->opcode, pCmd_st->arg, u8_retry_cmd); ++ ++ if(u8_retry_cmd < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_cmd++; ++ if(12==pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS !=mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ #endif ++ return; ++ } ++ if(25==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ if(u8_retry_cmd) ++ eMMC_debug(0,0,"eMMC: CMD retry ok\n"); ++ ++ if(pData_st) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pMStarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ ++ err = mstar_mci_post_dma_read(pMStarHost_st); ++ } ++ if( err ) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ } ++ ++ } ++ else ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd without data ++ ++ if( pCmd_st->opcode == 23 ) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); // CMD18 or CMD25 ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++} ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st) ++{ ++ struct mstar_mci_host *pMStarHost_st; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ if (!pMRQ_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMRQ_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ ++ pMStarHost_st->request = pMRQ_st; ++ ++ // --------------------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ eMMC_Init_Device(); ++ } ++ ++ ++ if(NULL == pMStarHost_st->request->cmd->data && 6 != pMStarHost_st->request->cmd->opcode) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ if(6 == pMStarHost_st->request->cmd->opcode && ++ (((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB70000)|| ++ ((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB90000))) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ #endif ++ // --------------------------------------------- ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ ++} ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ u16 au16_cifc[32], u16_i; ++ u8 *pTemp; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != eMMC_ReturnRsp((u8*)au16_cifc, (u8)pCmd_st->opcode)) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ //eMMC_debug(0,0,"eMMC Info: no rsp\n"); ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3-(u16_i%4)) + 4*(u16_i/4)] = ++ (u8)(au16_cifc[(u16_i+1)/2] >> 8*((u16_i+1)%2)); ++ } ++ #if 0 ++ eMMC_debug(0,1,"------------------\n"); ++ eMMC_dump_mem((u8*)&(pCmd_st->resp[0]), 0x10); ++ eMMC_debug(0,1,"------------------\n"); ++ #endif ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++} ++#endif ++ ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st) ++{ ++ /* Define Local Variables */ ++ struct mstar_mci_host *pMStarHost_st; ++ ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ goto LABEL_END; ++ } ++ if (!pIOS_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pIOS_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "eMMC: clock: %u, bus_width %Xh \n", ++ // pIOS_st->clock, pIOS_st->bus_width); ++ ++ // ---------------------------------- ++ if (pIOS_st->clock == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "eMMC Warn: disable clk \n"); ++ eMMC_clock_gating(); ++ } ++ // ---------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ else ++ { eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ } ++ pMStarHost_st->sd_mod = (BIT_SD_DEFAULT_MODE_REG & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ #else ++ // ---------------------------------- ++ else ++ { ++ pMStarHost_st->sd_mod = BIT_SD_DEFAULT_MODE_REG; ++ ++ if(pIOS_st->clock > CLK_400KHz) ++ { ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ else ++ { eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ } ++ ++ if (pIOS_st->bus_width == MMC_BUS_WIDTH_8) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ } ++ else if (pIOS_st->bus_width == MMC_BUS_WIDTH_4) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_4; ++ } ++ else ++ { g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK); ++ } ++ #endif ++ ++ LABEL_END: ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,0,"\n"); ++ ++ ++ ++} ++ ++ ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st) ++{ ++ s32 read_only; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ read_only = 0; ++ if(!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ read_only = -EINVAL; ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return read_only; ++} ++ ++ ++//======================================================================= ++static void mstar_mci_enable(struct mstar_mci_host *pMStarHost_st) ++{ ++ u32 u32_err; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ eMMC_PlatformInit(); ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ ++ u32_err = eMMC_FCIE_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Init fail: %Xh \n", u32_err); ++} ++ ++static void mstar_mci_disable(struct mstar_mci_host *pMStarHost_st) ++{ ++ u32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Reset fail: %Xh\n", u32_err); ++ eMMC_clock_gating(); ++} ++ ++static s32 mstar_mci_probe(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ int irq = 0; ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pMStarHost_st; ++ s32 s32_ret; ++ ++ // -------------------------------- ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pDev_st is NULL \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ irq = irq_of_parse_and_map(pDev_st->dev.of_node, 0); ++ if (!irq) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: irq_of_parse_and_map error!! \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st = 0; ++ pMStarHost_st = 0; ++ s32_ret = 0; ++ g_eMMCDrv.u8_PadType = FCIE_DEFAULT_PAD; ++ g_eMMCDrv.u16_ClkRegVal = FCIE_SLOWEST_CLK; ++ // -------------------------------- ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ mstar_mci_enable(pMStarHost_st); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ pMMCHost_st = mmc_alloc_host(sizeof(struct mstar_mci_host), &pDev_st->dev); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: mmc_alloc_host fail \n"); ++ s32_ret = -ENOMEM; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st->ops = &sg_mstar_mci_ops; ++ // [FIXME]-> ++ pMMCHost_st->f_min = CLK_400KHz; ++ pMMCHost_st->f_max = CLK_200MHz; ++ pMMCHost_st->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | \ ++ MMC_VDD_31_32 | MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; ++ ++ pMMCHost_st->max_blk_count = BIT_SD_JOB_BLK_CNT_MASK; ++ pMMCHost_st->max_blk_size = 512; /* sector */ ++ pMMCHost_st->max_req_size = pMMCHost_st->max_blk_count * pMMCHost_st->max_blk_size; ++ ++ pMMCHost_st->max_seg_size = pMMCHost_st->max_req_size; ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,20) ++ pMMCHost_st->max_phys_segs = 128; ++ pMMCHost_st->max_hw_segs = 128; ++ #else ++ pMMCHost_st->max_segs = 128; ++ #endif ++ //--------------------------------------- ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ pMStarHost_st->mmc = pMMCHost_st; ++ //--------------------------------------- ++ ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_NONREMOVABLE; ++ ++ #if defined(DDR_MODE_ENABLE) && DDR_MODE_ENABLE ++ pMMCHost_st->caps |= MMC_CAP_1_8V_DDR; ++ #endif ++ ++ ++ pMStarHost_st->baseaddr = (void __iomem *)FCIE0_BASE; ++ // <-[FIXME] ++ ++ strcpy(pMStarHost_st->name,MSTAR_MCI_NAME); ++ ++ mmc_add_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, pMMCHost_st); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ s32_ret = request_irq(irq, eMMC_FCIE_IRQ, IRQF_SHARED, DRIVER_NAME, pMStarHost_st); ++ if (s32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: request_irq fail \n"); ++ mmc_free_host(pMMCHost_st); ++ goto LABEL_END; ++ } ++ #endif ++ ++ LABEL_END: ++ return s32_ret; ++} ++ ++static s32 __exit mstar_mci_remove(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pMStarHost_st; ++ s32 s32_ret; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ s32_ret = 0; ++ ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pDev_st is NULL\n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pMMCHost_st is NULL\n"); ++ s32_ret= -1; ++ goto LABEL_END; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove +\n"); ++ ++ mmc_remove_host(pMMCHost_st); ++ ++ mstar_mci_disable(pMStarHost_st); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ free_irq(pMStarHost_st->irq, pMStarHost_st); ++ #endif ++ ++ mmc_free_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, NULL); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove -\n"); ++ ++ LABEL_END: ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return s32_ret; ++} ++ ++ ++#ifdef CONFIG_PM ++static s32 mstar_mci_suspend(struct platform_device *pDev_st, pm_message_t state) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ if (pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend + \n"); ++ ret = mmc_suspend_host(pMMCHost_st); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend -, %Xh\n", ret); ++ return ret; ++} ++ ++extern U8 gu8_NANDeMMC_need_preset_flag; ++static s32 mstar_mci_resume(struct platform_device *pDev_st) ++{ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ ++ //only for Cedric xxxxx ++ gu8_NANDeMMC_need_preset_flag = 1; ++ ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ mstar_mci_enable(mmc_priv(pMMCHost_st)); ++ ++ if (pMMCHost_st) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume +\n"); ++ ret = mmc_resume_host(pMMCHost_st); ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume -, %Xh\n", ret); ++ return ret; ++} ++#endif /* End ifdef CONFIG_PM */ ++ ++static const struct of_device_id ms_emmc_of_match_table[] = { ++ { .compatible = "mstar,emmc-cedric" }, ++ {} ++}; ++ ++/****************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++static struct platform_driver sg_mstar_mci_driver = ++{ ++ .probe = mstar_mci_probe, ++ .remove = __exit_p(mstar_mci_remove), ++ ++ #ifdef CONFIG_PM ++ .suspend = mstar_mci_suspend, ++ .resume = mstar_mci_resume, ++ #endif ++ ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_emmc_of_match_table), ++ }, ++}; ++ ++//static struct platform_device sg_mstar_emmc_device_st = ++//{ ++// .name = DRIVER_NAME, ++// .id = 0, ++// .resource = NULL, ++// .num_resources = 0, ++//}; ++ ++extern int Chip_Boot_Get_Dev_Type(void); ++extern unsigned long long Chip_MIU_to_Phys(unsigned long long phys); ++ ++/****************************************************************************** ++ * Init & Exit Modules ++ ******************************************************************************/ ++static s32 __init mstar_mci_init(void) ++{ ++ int err = 0; ++ ++ if(MS_BOOT_DEV_EMMC!=(MS_BOOT_DEV_TYPE)Chip_Boot_Get_Dev_Type()) ++ { ++ pr_info("[eMMC] skipping device initialization\n"); ++ return -1; ++ } ++ ++ MIU0_BUS_ADDR=Chip_MIU_to_Phys(0);//get the MIU0 base; ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"\n"); ++ ++// if((err = platform_device_register(&sg_mstar_emmc_device_st)) < 0) ++// eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ if((err = platform_driver_register(&sg_mstar_mci_driver)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ return err; ++} ++ ++static void __exit mstar_mci_exit(void) ++{ ++ platform_driver_unregister(&sg_mstar_mci_driver); ++} ++ ++ ++bool mstar_mci_is_mstar_host(struct mmc_card* card) ++{ ++ struct mstar_mci_host *mci_host; ++ ++ if( NULL==(card) ++ || NULL==(card->host) ++ || NULL==(mci_host=((struct mstar_mci_host *)card->host->private) ) ++ || 0!=strncmp(mci_host->name,MSTAR_MCI_NAME,strlen(MSTAR_MCI_NAME)) ++ ) ++ { ++ return false; ++ } ++ else ++ { ++ return true; ++ } ++ ++} ++ ++EXPORT_SYMBOL(mstar_mci_is_mstar_host); ++ ++ ++module_init(mstar_mci_init); ++module_exit(mstar_mci_exit); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/emmc/cedric/mstar_mci.h b/drivers/mstar/emmc/cedric/mstar_mci.h +new file mode 100644 +index 00000000..a5b87437 +--- /dev/null ++++ b/drivers/mstar/emmc/cedric/mstar_mci.h +@@ -0,0 +1,60 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef MSTAR_MCI_H ++#define MSTAR_MCI_H ++ ++#include "eMMC.h" ++ ++/****************************************************************************** ++* Function define for this driver ++******************************************************************************/ ++ ++/****************************************************************************** ++* Register Address Base ++******************************************************************************/ ++#define CLK_400KHz 400*1000 ++#define CLK_200MHz 200*1000*1000 ++ ++#define eMMC_GENERIC_WAIT_TIME (HW_TIMER_DELAY_1s*3) ++#define eMMC_READ_WAIT_TIME (HW_TIMER_DELAY_500ms) ++ ++/****************************************************************************** ++* Low level type for this driver ++******************************************************************************/ ++struct mstar_mci_host ++{ ++ struct mmc_host *mmc; ++ struct mmc_command *cmd; ++ struct mmc_request *request; ++ ++ void __iomem *baseaddr; ++ s32 irq; ++ ++ u16 sd_clk; ++ u16 sd_mod; ++ ++ /* Flag indicating when the command has been sent. */ ++ /* This is used to work out whether or not to send the stop */ ++ u32 flags; ++ u32 present; ++ char name[16]; ++}; /* struct mstar_mci_host*/ ++ ++ ++#define MSTAR_MCI_NAME "MSTAR_MCI" ++#endif +diff --git a/drivers/mstar/emmc/chicago/Makefile b/drivers/mstar/emmc/chicago/Makefile +new file mode 100644 +index 00000000..11c1f92b +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/Makefile +@@ -0,0 +1,23 @@ ++MS_ARCH_NAME=chicago ++EXTRA_CFLAGS += -Idrivers/mstar/include ++# ++# Makefile for MStar eMMC host drivers. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/$(MS_ARCH_NAME)/eMMCDrv/inc/api/ ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/$(MS_ARCH_NAME)/eMMCDrv/inc/common/ ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/$(MS_ARCH_NAME)/eMMCDrv/inc/config/ ++EXTRA_CFLAGS += -Werror ++ ++# specific options ++#EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++ ++obj-$(CONFIG_MS_EMMC_CHICAGO) := kdrv_emmc.o ++ ++kdrv_emmc-y := mstar_mci.o ++kdrv_emmc-y += eMMCDrv/src/api/eMMC_prg.o ++kdrv_emmc-y += eMMCDrv/src/common/eMMC_hal.o ++kdrv_emmc-y += eMMCDrv/src/common/eMMC_utl.o ++kdrv_emmc-y += eMMCDrv/src/config/eMMC_platform.o +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/api/drv_eMMC.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/api/drv_eMMC.h +new file mode 100644 +index 00000000..1b015560 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/api/drv_eMMC.h +@@ -0,0 +1,214 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef __DRV_eMMC_H__ ++#define __DRV_eMMC_H__ ++ ++#ifndef U32 ++#define U32 unsigned long ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++/*=============================================================*/ ++// Include files ++/*=============================================================*/ ++#include "eMMC_config.h" ++ ++/*=============================================================*/ ++// Extern definition ++/*=============================================================*/ ++typedef struct _eMMC_INFO ++{ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ ++ U16 u16_ECCCodeByteCnt; ++ U16 u16_PageSectorCnt; ++ U8 u8_WordMode; ++ ++} eMMC_INFO_t; ++ ++typedef struct _eMMC_CIS { ++ ++ U8 au8_eMMC_nni[512]; ++ U8 au8_eMMC_pni[512]; ++ ++} eMMC_CIS_t; ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Variable definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++extern U32 eMMC_Init(void); ++extern U32 eMMC_Init_Device(void); ++extern U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt); ++//-------------------------------------------- ++// CAUTION: u32_DataByteCnt has to be 512B x n ++//-------------------------------------------- ++extern U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++//-------------------------------------------- ++extern U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID); ++extern U32 eMMC_GetDevInfo(eMMC_INFO_t *peMMCInfo_t); ++ ++extern U32 eMMC_CheckCIS(eMMC_CIS_t *ptCISData); ++extern U32 eMMC_WriteCIS(eMMC_CIS_t *ptCISData); ++extern U32 eMMC_ReadCIS(eMMC_CIS_t *ptCISData); ++ ++extern U32 eMMC_WritePartitionInfo(U8 *pu8_Data, U32 u32_ByteCnt); ++extern U32 eMMC_ReadPartitionInfo(U8 *pu8_Data); ++extern U32 eMMC_DumpPartitionInfo(void); ++ ++extern U32 eMMC_WritePartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartPhySector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx); ++extern U32 eMMC_ReadPartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartPhySector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx); ++extern U32 eMMC_GetPartitionCapacity (U16 u16_PartType, ++ U32 *pu32_Cap); ++extern U32 eMMC_ErasePartition(U16 u16_PartType); ++extern U32 eMMC_EraseAllPartitions(void); ++extern U32 eMMC_EraseAll(void); ++extern U32 eMMC_FATAutoSize(void); ++ ++extern U32 eMMC_GetExtCSD(U8* pu8_Ext_CSD); ++extern U32 eMMC_SetExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++ ++/*=============================================================*/ ++// internal function definition ++/*=============================================================*/ ++extern U32 eMMC_ReadBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo); ++extern U32 eMMC_CheckIfReady(void); ++extern void eMMC_ResetReadyFlag(void); ++extern void eMMC_DumpDriverStatus(void); ++extern U32 eMMC_FCIE_BuildDDRTimingTable(void); ++ ++//-------------------------------------------- ++ //#if defined(eMMC_DRV_G2P_UBOOT) && eMMC_DRV_G2P_UBOOT ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++extern U32 eMMC_SearchDevNodeStartSector(void); ++ #endif ++//-------------------------------------------- ++ ++#endif //__DRV_eMMC_H__ ++ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC.h +new file mode 100644 +index 00000000..b053fb53 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC.h +@@ -0,0 +1,354 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef eMMC_DRIVER_H ++#define eMMC_DRIVER_H ++ ++ ++//=========================================================== ++// debug macro ++//=========================================================== ++ ++ ++//===================================================================================== ++#include "eMMC_config.h" // [CAUTION]: edit eMMC_config.h for your platform ++//===================================================================================== ++#include "eMMC_err_codes.h" ++ ++ ++//=========================================================== ++// macro for Spec. ++//=========================================================== ++#define ADDRESSING_MODE_BYTE 1 // 1 byte ++#define ADDRESSING_MODE_SECTOR 2 // 512 bytes ++#define ADDRESSING_MODE_4KB 3 // 4KB bytes ++ ++#define eMMC_SPEED_OLD 0 ++#define eMMC_SPEED_HIGH 1 ++#define eMMC_SPEED_HS200 2 ++ ++#define eMMC_FLAG_TRIM BIT0 ++#define eMMC_FLAG_HPI_CMD12 BIT1 ++#define eMMC_FLAG_HPI_CMD13 BIT2 ++ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++#define eMMC_SECTOR_512BYTE 0x200 ++#define eMMC_SECTOR_512BYTE_BITS 9 ++#define eMMC_SECTOR_512BYTE_MASK (eMMC_SECTOR_512BYTE-1) ++ ++#define eMMC_SECTOR_BUF_16KB (eMMC_SECTOR_512BYTE * 0x20) ++ ++#define eMMC_SECTOR_BYTECNT eMMC_SECTOR_512BYTE ++#define eMMC_SECTOR_BYTECNT_BITS eMMC_SECTOR_512BYTE_BITS ++//------------------------------------------------------- ++ ++#define eMMC_ExtCSD_SetBit 1 ++#define eMMC_ExtCSD_ClrBit 2 ++#define eMMC_ExtCSD_WByte 3 ++ ++#define eMMC_CMD_BYTE_CNT 5 ++#define eMMC_R1_BYTE_CNT 5 ++#define eMMC_R1b_BYTE_CNT 5 ++#define eMMC_R2_BYTE_CNT 16 ++#define eMMC_R3_BYTE_CNT 5 ++#define eMMC_R4_BYTE_CNT 5 ++#define eMMC_R5_BYTE_CNT 5 ++#define eMMC_MAX_RSP_BYTE_CNT eMMC_R2_BYTE_CNT ++ ++//=========================================================== ++// Partition Info parameters ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_NNI { ++ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 au8_padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ U8 u8_PairPageMapLoc; ++ U8 u8_PairPageMapType; ++ ++} eMMC_PACK1 eMMC_NNI_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PARTITION_RECORD { ++ ++ U16 u16_StartBlk; // the start block index, reserved for UNFD internal use. ++ U16 u16_BlkCnt; // project team defined ++ U16 u16_PartType; // project team defined, e.g. eMMC_PART_XXX_0 ++ U16 u16_BackupBlkCnt; // reserved good blocks count for backup, UNFD internal use. ++ // e.g. u16BackupBlkCnt = u16BlkCnt * 0.03 + 2 ++} eMMC_PACK1 eMMC_PARTITION_RECORD_t, *P_eMMC_PARTITION_RECORD_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PNI { ++ ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U16 u16_PartCnt; ++ U16 u16_UnitByteCnt; ++ eMMC_PARTITION_RECORD_t records[]; ++ ++} eMMC_PACK1 eMMC_PNI_t; ++ ++ ++// Logical Disk Info ++typedef struct _eMMC_DISK_INFO { ++ ++ U32 u32_StartSector; ++ U32 u32_SectorCnt; ++ ++} eMMC_DISK_INFO_t, *P_eMMC_DISK_INFO_t; ++ ++ ++//=========================================================== ++// internal data Sector Address ++//=========================================================== ++#define eMMC_ID_BYTE_CNT 15 ++#define eMMC_ID_FROM_CID_BYTE_CNT 10 ++#define eMMC_ID_DEFAULT_BYTE_CNT 11 // last byte means n GB ++ ++ ++//=========================================================== ++// DDR Timing Table ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_PARAM { ++ ++ U8 u8_DQS, u8_Cell; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_PARAM_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_WINDOW { ++ ++ U8 u8_Cnt; ++ // DQS uses index, not reg value (see code) ++ eMMC_FCIE_DDRT_PARAM_t aParam[2]; ++ // now G2P is 4 ++ U8 au8_DQSTryCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)+1]; ++ U8 au8_DQSValidCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)+1]; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_WINDOW_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_SET { ++ ++ U16 u16_Clk; ++ eMMC_FCIE_DDRT_PARAM_t Param; // register values ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_SET_t; ++ ++ ++#define eMMC_FCIE_DDRT_SET_CNT 12 ++#define eMMC_DDRT_SET_MAX 0 ++#define eMMC_DDRT_SET_NEXT 1 ++#define eMMC_DDRT_SET_MIN 2 ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_TABLE { ++ ++ U8 u8_SetCnt, u8_CurSetIdx; ++ eMMC_FCIE_DDRT_SET_t Set[eMMC_FCIE_DDRT_SET_CNT]; // 0:Max, 1:Next, 2:Min ++ ++ U32 u32_ChkSum; // put in the last ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_TABLE_t; ++ ++ ++//=========================================================== ++// driver structures ++//=========================================================== ++// driver flag ++#define DRV_FLAG_INIT_DONE BIT0 // include eMMC identify done ++ ++#define DRV_FLAG_GET_PART_INFO BIT1 ++#define DRV_FLAG_RSP_WAIT_D0H BIT2 // currently only R1b ++#define DRV_FLAG_DDR_MODE BIT3 ++#define DRV_FLAG_DDR_TUNING BIT4 ++ ++#define DRV_FLAG_SPEED_MASK (BIT5|BIT6) ++#define DRV_FLAG_SPEED_HIGH BIT5 ++#define DRV_FLAG_SPEED_HS200 BIT6 ++ ++#define DRV_FLAG_TESTING BIT7 ++ ++#define DRV_FLAG_RSPFROMRAM_SAVE BIT10 ++#define DRV_FLAG_ERROR_RETRY BIT11 ++ ++ ++typedef struct _eMMC_DRIVER ++{ ++ U32 u32_ChkSum; // [8th ~ last-512] bytes ++ U8 au8_Sig[4]; // 'e','M','M','C' ++ ++ // ---------------------------------------- ++ // FCIE ++ // ---------------------------------------- ++ U16 u16_RCA; ++ U32 u32_DrvFlag, u32_LastErrCode; ++ U8 au8_Rsp[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CSD[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CID[eMMC_MAX_RSP_BYTE_CNT]; ++ U16 u16_Reg10_Mode; ++ U32 u32_ClkKHz; ++ U16 u16_ClkRegVal, u8_PadType; ++ eMMC_FCIE_DDRT_TABLE_t DDRTable; ++ ++ // ---------------------------------------- ++ // eMMC ++ // ---------------------------------------- ++ // CSD ++ U8 u8_SPEC_VERS; ++ U8 u8_R_BL_LEN, u8_W_BL_LEN; // supported max blk len ++ U16 u16_C_SIZE; ++ U8 u8_TAAC, u8_NSAC, u8_Tran_Speed; ++ U8 u8_C_SIZE_MULT; ++ U8 u8_ERASE_GRP_SIZE, u8_ERASE_GRP_MULT; ++ U8 u8_R2W_FACTOR; ++ ++ U8 u8_IfSectorMode; ++ U32 u32_eMMCFlag; ++ U32 u32_EraseUnitSize; ++ ++ // ExtCSD ++ U32 u32_SEC_COUNT; ++ U32 u32_BOOT_SEC_COUNT; ++ U8 u8_BUS_WIDTH, u8_ErasedMemContent; ++ U16 u16_ReliableWBlkCnt; ++ ++ // ---------------------------------------- ++ // CIS ++ // ---------------------------------------- ++ // nni ++ U8 u8_IDByteCnt, au8_ID[eMMC_ID_BYTE_CNT]; ++ U8 au8_Vendor[16], au8_PartNumber[16]; ++ ++ // pni ++ U32 au32_Pad[2]; // don't move ++ ++ U32 u32_PartDevNodeStartSector; ++ U16 u16_PartDevNodeSectorCnt; ++ U32 u32_FATSectorCnt; ++ ++ // ---------------------- ++ #if eMMC_RSP_FROM_RAM ++ // rsp from ram ++ U8 au8_AllRsp[eMMC_SECTOR_512BYTE]; // last 4 bytes are CRC ++ #endif ++ ++} eMMC_DRIVER, *P_eMMC_DRIVER; ++ ++ ++extern eMMC_DRIVER g_eMMCDrv; ++ ++//=========================================================== ++// exposed APIs ++//=========================================================== ++#include "drv_eMMC.h" ++ ++//=========================================================== ++// internal used functions ++//=========================================================== ++#include "eMMC_utl.h" ++#include "eMMC_hal.h" ++ ++extern U32 eMMC_IPVerify_Main(void); ++extern U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void); ++extern void eMMCTest_DownCount(U32 u32_Sec); ++extern U32 eMMC_IPVerify_Performance(void); ++extern U32 eMMCTest_BlkWRC_ProbeDDR(U32 u32_eMMC_Addr); ++extern U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt); ++extern U32 eMMC_BootMode(void); ++extern void eMMC_Prepare_Power_Saving_Mode_Queue(void); ++ ++#endif // eMMC_DRIVER_H ++ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_err_codes.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_err_codes.h +new file mode 100644 +index 00000000..e3ff49c6 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_err_codes.h +@@ -0,0 +1,199 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_ERR_CODES_H__ ++#define __eMMC_ERR_CODES_H__ ++//=========================================================== ++// device status (R1, R1b) ++//=========================================================== ++#define eMMC_R1_ADDRESS_OUT_OF_RANGE BIT31 ++#define eMMC_R1_ADDRESS_MISALIGN BIT30 ++#define eMMC_R1_BLOCK_LEN_ERROR BIT29 ++#define eMMC_R1_ERASE_SEQ_ERROR BIT28 ++#define eMMC_R1_ERASE_PARAM BIT27 ++#define eMMC_R1_WP_VIOLATION BIT26 ++#define eMMC_R1_DEVICE_IS_LOCKED BIT25 ++#define eMMC_R1_LOCK_UNLOCK_FAILED BIT24 ++#define eMMC_R1_COM_CRC_ERROR BIT23 ++#define eMMC_R1_ILLEGAL_COMMAND BIT22 ++#define eMMC_R1_DEVICE_ECC_FAILED BIT21 ++#define eMMC_R1_CC_ERROR BIT20 ++#define eMMC_R1_ERROR BIT19 ++#define eMMC_R1_CID_CSD_OVERWRITE BIT16 ++#define eMMC_R1_WP_ERASE_SKIP BIT15 ++#define eMMC_R1_ERASE_RESET BIT13 ++#define eMMC_R1_CURRENT_STATE (BIT12|BIT11|BIT10|BIT9) ++#define eMMC_R1_READY_FOR_DATA BIT8 ++#define eMMC_R1_SWITCH_ERROR BIT7 ++#define eMMC_R1_EXCEPTION_EVENT BIT6 ++#define eMMC_R1_APP_CMD BIT5 ++ ++#define eMMC_ERR_R1_31_24 (eMMC_R1_ADDRESS_OUT_OF_RANGE| \ ++ eMMC_R1_ADDRESS_MISALIGN| \ ++ eMMC_R1_BLOCK_LEN_ERROR| \ ++ eMMC_R1_ERASE_SEQ_ERROR| \ ++ eMMC_R1_ERASE_PARAM| \ ++ eMMC_R1_WP_VIOLATION| \ ++ eMMC_R1_LOCK_UNLOCK_FAILED) ++#define eMMC_ERR_R1_23_16 (eMMC_R1_COM_CRC_ERROR| \ ++ eMMC_R1_ILLEGAL_COMMAND| \ ++ eMMC_R1_DEVICE_ECC_FAILED| \ ++ eMMC_R1_CC_ERROR| \ ++ eMMC_R1_ERROR| \ ++ eMMC_R1_CID_CSD_OVERWRITE) ++#define eMMC_ERR_R1_15_8 (eMMC_R1_WP_ERASE_SKIP| \ ++ eMMC_R1_ERASE_RESET) ++#define eMMC_ERR_R1_7_0 (eMMC_R1_SWITCH_ERROR) ++#define eMMC_ERR_R1_31_0 (eMMC_ERR_R1_31_24|eMMC_ERR_R1_23_16|eMMC_ERR_R1_15_8|eMMC_ERR_R1_7_0) ++#define eMMC_ERR_R1_NEED_RETRY (eMMC_R1_COM_CRC_ERROR|eMMC_R1_DEVICE_ECC_FAILED|eMMC_R1_CC_ERROR|eMMC_R1_ERROR|eMMC_R1_SWITCH_ERROR) ++ ++//=========================================================== ++// driver error codes ++//=========================================================== ++#define eMMC_ST_SUCCESS 0 ++ ++#define eMMC_ST_ERR_MEM_CORRUPT (0x0001 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_ALIGN (0x0002 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_PACKED (0x0003 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DATA_MISMATCH (0x0004 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAIT_REG0 (0x0005 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY (0x0006 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_MIULASTDONE (0x0007 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITD0HIGH (0x0008 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_CARDDMAEND (0x0009 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT (0x000A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_STS_ERR (0x000B | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_BIST_FAIL (0x0010 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DEBUG_MODE (0x0011 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_CLK (0x0012 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARAMETER (0x0013 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_INIT (0x0014 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INVALID_PARAM (0x0015 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARTITION_CHKSUM (0x0016 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PART_INFO (0x0017 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PARTITION (0x0018 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_OK_DDR_PARAM (0x0019 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SAVE_DDRT_FAIL (0x001A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_CHKSUM (0x001B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_NONA (0x001C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI (0x001D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI (0x001E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI_NONA (0x001F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI_NONA (0x0020 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SDR_DETECT_DDR (0x0021 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_CIS (0x0022 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_eMMC_PLATFROM (0x0023 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_RIU (0x0024 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INT_TO (0x0025 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_UNKNOWN_CLK (0x0026 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_BUILD_DDRT (0x0027 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_RSP_IN_RAM (0x0028 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_SLOWER_CLK (0x0029 | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_CMD1 (0x0A00 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD1_DEV_NOT_RDY (0x0A01 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD2 (0x0A02 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD3_CMD7 (0x0A03 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_31_24 (0x0A04 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_23_16 (0x0A05 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_15_8 (0x0A06 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_7_0 (0x0A07 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_CIFD (0x0A08 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_MIU (0x0A09 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_CIFD (0x0A0A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_MIU (0x0A0B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD18 (0x0A0C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6 (0x0A0D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD13 (0x0A0E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD12 (0x0A0F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD (0x0A10 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H (0x0A11 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_CHK_R1 (0x0A12 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU (0x0A13 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_WAIT_D0H (0x0A14 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_CHK_R1 (0x0A15 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25 (0x0A16 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_WAIT_D0H (0x0A17 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_CHK_R1 (0x0A18 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD9 (0x0A19 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SEC_UPFW_TO (0x0A20 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD16 (0x0A21 | eMMC_ST_PLAT) ++ ++ ++ ++#endif /* __eMMC_ERR_CODES_H__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_hal.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_hal.h +new file mode 100644 +index 00000000..bfa3ab11 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_hal.h +@@ -0,0 +1,162 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_HAL_H__ ++#define __eMMC_HAL_H__ ++ ++#include "eMMC.h" ++ ++extern U32 eMMC_FCIE_WaitEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_PollingEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir); ++extern void eMMC_FCIE_DumpDebugBus(void); ++extern void eMMC_FCIE_DumpRegisters(void); ++extern void eMMC_FCIE_CheckResetDone(void); ++extern U32 eMMC_FCIE_Reset(void); ++extern U32 eMMC_FCIE_Init(void); ++extern void eMMC_FCIE_ErrHandler_Stop(void); ++extern U32 eMMC_FCIE_ErrHandler_Retry(void); ++extern void eMMC_FCIE_ErrHandler_RestoreClk(void); ++extern void eMMC_FCIE_ErrHandler_ReInit(void); ++extern U32 eMMC_FCIE_SendCmd(U16 u16_Mode, U16 u16_Ctrl, U32 u32_Arg, U8 u8_CmdIdx, U8 u8_RspByteCnt); ++extern void eMMC_FCIE_ClearEvents(void); ++extern void eMMC_FCIE_ClearEvents_Reg0(void); ++extern U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us); ++extern U32 eMMC_FCIE_WaitD0High(U32 u32_us); ++extern void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_GetCIFD(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_SetDDRTimingReg(U8 u8_DQS, U8 u8_DelaySel); ++extern U32 eMMC_FCIE_EnableDDRMode(void); ++extern U32 eMMC_FCIE_EnableDDRMode_Ex(void); ++extern U32 eMMC_FCIE_EnableSDRMode(void); ++extern U32 eMMC_FCIE_DetectDDRTiming(void); ++extern void eMMC_FCIE_ApplyDDRTSet(U8 u8_DDRTIdx); ++extern void eMMC_DumpDDRTTable(void); ++extern U32 eMMC_LoadDDRTTable(void); ++ ++#if eMMC_RSP_FROM_RAM ++extern void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_SaveRsp(void); ++extern U32 eMMC_SaveDriverContext(void); ++extern U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf); ++extern U32 eMMC_LoadDriverContext(U8 *pu8_Buf); ++#endif ++ ++//---------------------------------------- ++extern U32 eMMC_Identify(void); ++extern U32 eMMC_CMD0(U32 u32_Arg); ++extern U32 eMMC_CMD1(void); ++extern U32 eMMC_CMD2(void); ++extern U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx); ++extern U32 eMMC_CMD9(U16 u16_RCA); ++extern U32 eMMC_CSD_Config(void); ++extern U32 eMMC_ExtCSD_Config(void); ++extern U32 eMMC_CMD8(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf); ++extern U32 eMMC_SetBusSpeed(U8 u8_BusSpeed); ++extern U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR); ++extern U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++extern U32 eMMC_CMD6(U32 u32_Arg); ++extern U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++extern U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx); ++extern U32 eMMC_CMD38(void); ++extern U32 eMMC_CMD13(U16 u16_RCA); ++extern U32 eMMC_CMD16(U32 u32_BlkLength); ++extern U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD12_NoCheck(U16 u16_RCA); ++extern U32 eMMC_CMD12(U16 u16_RCA); ++extern U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD18_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD23(U16 u16_BlkCnt); ++extern U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD25_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CheckR1Error(void); ++extern U32 eMMC_UpFW_Samsung(U8 *pu8_FWBin); ++ ++ ++//---------------------------------------- ++extern U32 eMMC_FCIE_PollingFifoClkReady(void); ++extern U32 eMMC_FCIE_PollingMIULastDone(void); ++ ++#endif // __eMMC_HAL_H__ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_utl.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_utl.h +new file mode 100644 +index 00000000..3788e1c2 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/common/eMMC_utl.h +@@ -0,0 +1,100 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_UTL_H__ ++#define __eMMC_UTL_H__ ++ ++#include "eMMC.h" ++ ++ ++typedef eMMC_PACK0 struct _eMMC_TEST_ALIGN_PACK { ++ ++ U8 u8_0; ++ U16 u16_0; ++ U32 u32_0, u32_1; ++ ++} eMMC_PACK1 eMMC_TEST_ALIGN_PACK_t; ++ ++extern U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt); ++extern void eMMC_dump_mem(unsigned char *buf, int cnt); ++extern U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt); ++extern U32 eMMC_ChkSum(U8 *pu8_Data, U32 u32_ByteCnt); ++extern U32 eMMC_PrintDeviceInfo(void); ++extern U32 eMMC_CompareCISTag(U8 *tag); ++extern void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo); ++extern void eMMC_dump_pni(eMMC_PNI_t *pPartInfo); ++#endif // __eMMC_UTL_H__ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_cedric_linux.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_cedric_linux.h +new file mode 100644 +index 00000000..72fda57f +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_cedric_linux.h +@@ -0,0 +1,473 @@ ++#ifndef __eMMC_CEDRIC_LINUX__ ++#define __eMMC_CEDRIC_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++//#include ++//#include "chip_int.h" ++ ++#ifdef CONFIG_ARM ++//#include ++#endif ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++//#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE 0x1F000000 ++#define RIU_BASE 0x1F200000 ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x8A00 ++#define REG_BANK_FCIE2 0x8A80 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++ ++ ++#define REG_BANK_PMU 0x700 ++#define REG_BANK_PMRTC 0x900 ++ ++#define RTC_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_PMRTC) ++#define REG_RESET GET_REG_ADDR(RTC_BASE, 0x0A) ++#define PMU_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_PMU) ++#define REG_BATTERY GET_REG_ADDR(PMU_BASE, 0x06) ++ ++ ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++/* ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN_BASE, 0x1D) ++*/ ++#define BIT_FCIE_CLK_MASK ((BIT7-1)<<8) ++#define BIT_FCIE_CLK_24M ((0<<2)<<8) ++#define BIT_FCIE_CLK_12M ((1<<2)<<8) ++#define BIT_FCIE_CLK_48M ((2<<2)<<8) ++#define BIT_FCIE_CLK_86M ((3<<2)<<8) ++#define BIT_FCIE_CLK_108M ((4<<2)<<8) ++#define BIT_FCIE_CLK_123M ((5<<2)<<8) ++#define BIT_FCIE_CLK_144M ((6<<2)<<8) ++#define BIT_FCIE_CLK_172M ((7<<2)<<8) ++#define BIT_FCIE_CLK_192M ((8<<2)<<8) ++#define BIT_FCIE_CLK_216M ((9<<2)<<8) ++#define BIT_FCIE_CLK_240M ((10<<2)<<8) ++#define BIT_FCIE_CLK_345M ((11<<2)<<8) ++#define BIT_FCIE_CLK_432M ((13<<2)<<8) ++#define BIT_FCIE_CLK_1200K ((14<<2)<<8) ++#define BIT_FCIE_CLK_300K ((15<<2)<<8) ++#define BIT_FCIE_CLK_32M ((16<<2)<<8) ++#define BIT_FCIE_CLK_36M ((17<<2)<<8) ++#define BIT_FCIE_CLK_40M ((18<<2)<<8) ++#define BIT_FCIE_CLK_43_2M ((19<<2)<<8) ++#define BIT_FCIE_CLK_54M ((20<<2)<<8) ++#define BIT_FCIE_CLK_62M ((21<<2)<<8) ++#define BIT_FCIE_CLK_72M ((22<<2)<<8) ++#define BIT_FCIE_CLK_80M ((23<<2)<<8) ++ ++#define eMMC_FCIE_VALID_CLK_CNT 10 ++extern U16 gau16_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define RIU_BASE_CLKGEN0 (RIU_BASE+(0x0580U< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 1 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 0 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 1 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++extern U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_1200K //BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_86M //BIT_FCIE_CLK_24M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_144M //BIT_FCIE_CLK_36M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++/* ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++*/ ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_chicago_linux.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_chicago_linux.h +new file mode 100644 +index 00000000..94ceee5d +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_chicago_linux.h +@@ -0,0 +1,438 @@ ++#ifndef __eMMC_CHICAGO_LINUX__ ++#define __eMMC_CHICAGO_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++//#include ++//#include "chip_int.h" ++ ++#ifdef CONFIG_ARM ++//#include ++#endif ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++//#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_BASE 0x1F000000 ++ ++#define REG_BANK_PADTOP 0x580 ++#define REG_BANK_CHIPTOP 0xF00 ++#define REG_BANK_FCIE0 0x1000 ++#define REG_BANK_FCIE1 0x1080 ++#define REG_BANK_FCIE2 0x1100 ++#define REG_BANK_FCIE3 0x1180 ++#define REG_BANK_PMU 0x1F80 ++ ++#define PMU_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_PMU) ++#define PADTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_PADTOP) ++#define CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++#define FCIE_POWEER_SAVE_MODE_BASE FCIE1_BASE ++ ++#define REG_PADTOP_00 GET_REG_ADDR(PADTOP_BASE, 0x00) ++#define REG_PADTOP_01 GET_REG_ADDR(PADTOP_BASE, 0x01) ++#define REG_PADTOP_40 GET_REG_ADDR(PADTOP_BASE, 0x40) ++#define REG_PADTOP_43 GET_REG_ADDR(PADTOP_BASE, 0x43) ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++ ++#define NFIE_REG_CLK_MASK ((BIT6-1)) ++#define NFIE_REG_4XCLK_1_3M ((0<<2)) ++#define NFIE_REG_4XCLK_26M ((1<<2)) ++#define NFIE_REG_4XCLK_48M ((2<<2)) ++#define NFIE_REG_4XCLK_80M ((3<<2)) ++#define NFIE_REG_4XCLK_96M ((4<<2)) ++#define NFIE_REG_4XCLK_120M ((5<<2)) ++#define NFIE_REG_4XCLK_147M ((6<<2)) ++#define NFIE_REG_4XCLK_160M ((7<<2)) ++#define NFIE_REG_4XCLK_176_8M ((8<<2)) ++#define NFIE_REG_4XCLK_192M ((9<<2)) ++#define NFIE_REG_4XCLK_221M ((10<<2)) ++#define NFIE_REG_4XCLK_240M ((11<<2)) ++#define NFIE_REG_4XCLK_294_6M ((13<<2)) ++#define NFIE_REG_4XCLK_353_6M ((14<<2)) ++#define NFIE_REG_4XCLK_60M ((15<<2)) ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U16 gau16_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BATTERY GET_REG_ADDR(PMU_BASE, 0x06) ++#define reg_nobat_int_en BIT3 ++ ++#define REG_CLK_EMMC GET_REG_ADDR(CHIPTOP_BASE, 0x25) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define REG_CLK_4X_DIV_EN GET_REG_ADDR(CHIPTOP_BASE, 0x3F) ++#define REG_RESET_PIN GET_REG_ADDR(CHIPTOP_BASE, 0x31) ++ ++#define eMMC_DBUS_WIDTH 8 ++#define eMMC_RST_L() REG_FCIE_CLRBIT(REG_RESET_PIN, BIT0) ++#define eMMC_RST_H() REG_FCIE_SETBIT(REG_RESET_PIN, BIT0) ++ ++//===================================================== ++// API declarations ++//===================================================== ++ ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (12*0x100000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++ ++#define WRITE_TO_eMMC 0 ++#define READ_FROM_eMMC 1 ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++//extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++ ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++ ++ ++#define eMMC_PART_ENV (0x0D|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_DEV_NODE (0x0F|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_MIU (0x20|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_EBOOT (0x21|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RTK (0x22|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_PARAMS (0x23|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_NVRAM (0x88|eMMC_LOGI_PART) //default start from 31 count ++ ++//extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 0 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 1 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++#define ENABLE_FCIE_HW_BUSY_CHECK 1 ++#define ENABLE_EMMC_POWER_SAVING_MODE 1 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++ ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 1 ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++extern U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x40 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK NFIE_REG_4XCLK_1_3M ++#define FCIE_SLOW_CLK NFIE_REG_4XCLK_80M ++#define FCIE_DEFAULT_CLK NFIE_REG_4XCLK_192M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_config.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_config.h +new file mode 100644 +index 00000000..e535e5f3 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_config.h +@@ -0,0 +1,189 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. 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Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_CONFIG_H__ ++#define __eMMC_CONFIG_H__ ++ ++#define UNIFIED_eMMC_DRIVER 1 ++ ++//===================================================== ++// select a HW platform: ++// - 1: enable, 0: disable. ++// - only one platform can be 1, others have to be 0. ++// - search and check all [FIXME] if need modify or not ++//===================================================== ++#if defined(CONFIG_MSTAR_EAGLE) ++#define eMMC_DRV_EAGLE_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MSTAR_EDISON) ++#define eMMC_DRV_EDISON_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MSTAR_EIFFEL) ++#define eMMC_DRV_EIFFEL_LINUX 1 ++#endif ++ ++#if defined(CONFIG_MSTAR_EINSTEIN) ++#define eMMC_DRV_EINSTEIN_LINUX 1 ++#endif ++ ++//#if defined(CONFIG_ARCH_CEDRIC) ++//#define eMMC_DRV_CEDRIC_LINUX 1 ++//#endif ++ ++#if defined(CONFIG_MS_EMMC_CHICAGO) || defined(CONFIG_MS_EMMC_CHICAGO_MODULE) ++#define eMMC_DRV_CHICAGO_LINUX 1 ++#endif ++#define eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr){\ ++ dmaaddr -= MIU0_BUS_ADDR; \ ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT);\ ++}\ ++//===================================================== ++// do NOT edit the following content. ++//===================================================== ++#if defined(eMMC_DRV_G2P_ROM) && eMMC_DRV_G2P_ROM ++ #include "eMMC_g2p_rom.h" ++#elif defined(eMMC_DRV_G2P_UBOOT) && eMMC_DRV_G2P_UBOOT ++ #include "eMMC_msw8x68_uboot.h" ++#elif defined(eMMC_DRV_G2E_UBOOT) && eMMC_DRV_G2E_UBOOT ++ #include "eMMC_msw8x68t_uboot.h" ++#elif defined(eMMC_DRV_G2P_BL) && eMMC_DRV_G2P_BL ++ #include "eMMC_g2p_bl.h" ++#elif defined(eMMC_DRV_A3_UBOOT) && eMMC_DRV_A3_UBOOT ++ #include "eMMC_a3_uboot.h" ++#elif defined(eMMC_DRV_AGATE_UBOOT) && eMMC_DRV_AGATE_UBOOT ++ #include "eMMC_agate_uboot.h" ++#elif defined(eMMC_DRV_EAGLE_UBOOT) && eMMC_DRV_EAGLE_UBOOT ++ #include "eMMC_eagle_uboot.h" ++#elif defined(eMMC_DRV_EDISON_UBOOT) && eMMC_DRV_EDISON_UBOOT ++ #include "eMMC_edison_uboot.h" ++#elif defined(eMMC_DRV_EIFFEL_UBOOT) && eMMC_DRV_EIFFEL_UBOOT ++ #include "eMMC_eiffel_uboot.h" ++#elif defined(eMMC_DRV_G2P_LINUX) && eMMC_DRV_G2P_LINUX ++ #include "eMMC_msw8x68_linux.h" ++// [FIXME] add a .h file for your platform ++#elif defined(eMMC_DRV_EAGLE_LINUX) && eMMC_DRV_EAGLE_LINUX ++ #include "eMMC_eagle_linux.h" ++#elif defined(eMMC_DRV_EDISON_LINUX) && eMMC_DRV_EDISON_LINUX ++ #include "eMMC_edison_linux.h" ++#elif defined(eMMC_DRV_EIFFEL_LINUX) && eMMC_DRV_EIFFEL_LINUX ++ #include "eMMC_eiffel_linux.h" ++#elif defined(eMMC_DRV_EINSTEIN_LINUX) && eMMC_DRV_EINSTEIN_LINUX ++ #include "eMMC_einstein_linux.h" ++#elif defined(eMMC_DRV_CEDRIC_LINUX) && eMMC_DRV_CEDRIC_LINUX ++ #include "eMMC_cedric_linux.h" ++#elif defined(eMMC_DRV_CHICAGO_LINUX) && eMMC_DRV_CHICAGO_LINUX ++ #include "eMMC_chicago_linux.h" ++#else ++ #error "Error! no platform selected." ++#endif ++ ++//===================================================== ++// misc. do NOT edit the following content. ++//===================================================== ++#define eMMC_DMA_RACING_PATCH 1 ++#define eMMC_DMA_PATCH_WAIT_TIME DELAY_10ms_in_us ++#define eMMC_DMA_RACING_PATTERN0 (((U32)'M'<<24)|((U32)0<<16)|((U32)'S'<<8)|(U32)1) ++#define eMMC_DMA_RACING_PATTERN1 (((U32)'T'<<24)|((U32)6<<16)|((U32)'A'<<8)|(U32)8) ++ ++//=========================================================== ++// Time Dalay, do NOT edit the following content ++//=========================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RESET (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FIFOCLK_RDY (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_CMDRSP_END (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*5) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*10) // safe for 512 blocks ++#else ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*60*10) //10*60 s ++#define TIME_WAIT_ERASE_DAT0_HIGH (HW_TIMER_DELAY_1s*60*10) //10*60 s ++#define TIME_WAIT_FCIE_RESET HW_TIMER_DELAY_500ms ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT HW_TIMER_DELAY_1us ++#define TIME_WAIT_FIFOCLK_RDY HW_TIMER_DELAY_500ms ++#define TIME_WAIT_CMDRSP_END HW_TIMER_DELAY_1s ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*2) // safe for 512 blocks ++#endif ++ ++ ++ ++ ++#endif /* __eMMC_CONFIG_H__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_eagle_linux.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_eagle_linux.h +new file mode 100644 +index 00000000..c9005c00 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_eagle_linux.h +@@ -0,0 +1,521 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_EAGLE_LINUX__ ++#define __eMMC_EAGLE_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "chip_int.h" ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_ARM ++#include ++#endif ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#ifdef CONFIG_ARM ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++#endif ++ ++#define REG_BANK_FCIE0 0x8980 // 1113h x 80h x 4 + 1F000000 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++#define REG_BANK_FCIE3 0x8A80 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++#define FCIE3_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE3) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ [FIXME]: refer to Bring-up Note --> ++// Mobile CMU = TV CLKGEN ++// TV CNM don't touch ++#define REG_BANK_CLKGEN 0x580 ++#define CLKGEN_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN) ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++ ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++//#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++//#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_48M 15 ++#define BIT_FCIE_CLK_300K 13 ++ ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN_BASE, 0x31) ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK ((BIT2|BIT3|BIT4)<<8) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK4X_20M 1 ++#define BIT_FCIE_CLK4X_27M 2 ++#define BIT_FCIE_CLK4X_36M 3 ++#define BIT_FCIE_CLK4X_40M 4 ++#define BIT_FCIE_CLK4X_48M 5 ++ ++#define reg_ckg_CMU GET_REG_ADDR(CLKGEN_BASE, 0x10) ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 // FIXME ++extern U8 gau8_FCIEClkSel[]; ++ ++ ++//------------------------------ ++#define REG_BANK_CHIPTOP 0xF00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++#define reg_chiptop_0x5A GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define reg_chiptop_0x1F GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1F) ++#define reg_chiptop_0x70 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x70) ++#define reg_chiptop_0x64 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define reg_chiptop_0x4F GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x4F) ++#define reg_chiptop_0x03 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x03) ++#define reg_chiptop_0x51 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x51) ++#define reg_chiptop_0x6F GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++ ++#define reg_chiptop_0x43 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x43) ++#define BIT_PAD_EMMC_CLK_SRC BIT0 ++#define BIT_PAD_BYPASS_MACRO BIT1 ++#define BIT_EMPTY BIT2 ++#define BIT_eMMC_RSTPIN_EN BIT3 ++#define BIT_eMMC_RSTPIN_VAL BIT4 ++ ++#define reg_chiptop_0x50 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_NAND_CS1_EN BIT10 ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_chiptop_0x0B GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define BIT_NAND_CS2_EN BIT0 ++#define BIT_NAND_CS3_EN BIT1 ++#define BIT_SD0_CFG (BIT2|BIT3) ++#define BIT_SD0_CFG2 (BIT4|BIT5) ++#define BIT_SD1_CFG (BIT6|BIT7) ++#define BIT_SD1_CFG2 (BIT8|BIT9) ++#define BIT_NAND_CFG (BIT12|BIT13|BIT14) ++ ++#define reg_chiptop_0x5D GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5D) ++#define BIT_eMMC_CFG_MASK (BIT14|BIT15) ++#define BIT_eMMC_CFG_MODE1 (BIT14) ++#define BIT_eMMC_CFG_MODE2 (BIT14|BIT15) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x59) ++#define CFG_EMMC_CMD_STRENGTH BIT12 ++#define CFG_EMMC_CLK_STRENGTH BIT13 ++ ++#define reg_pcm_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define CFG_PCM_DRV_STRENGTH (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++ ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define CFG_NAND_DRV_STRENGTH (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT0 ++#define BIT_SW_RST_Z BIT1 ++#define BIT_SW_RST_Z_EN BIT2 ++ ++#define eMMC_RST_L() {REG_FCIE_SETBIT(reg_chiptop_0x43, BIT_eMMC_RSTPIN_EN);\ ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, BIT_eMMC_RSTPIN_VAL);} ++#define eMMC_RST_H() REG_FCIE_SETBIT(reg_chiptop_0x43, BIT_eMMC_RSTPIN_EN|BIT_eMMC_RSTPIN_VAL) ++ ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 1 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 1 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++// [FIXME] --> ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++// <-- [FIXME] ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x80C00000 ++#define DMA_R_ADDR 0x80D00000 ++#define DMA_W_SPARE_ADDR 0x80E00000 ++#define DMA_R_SPARE_ADDR 0x80E80000 ++#define DMA_BAD_BLK_BUF 0x80F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#endif /* __eMMC_EAGLE_LINUX__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_edison_linux.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_edison_linux.h +new file mode 100644 +index 00000000..b7e0b4a4 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_edison_linux.h +@@ -0,0 +1,455 @@ ++#ifndef __eMMC_EDISON_LINUX__ ++#define __eMMC_EDISON_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_DEBUG_FS ++#include ++#include ++#endif ++#include "chip_int.h" ++ ++#include ++#include ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++#define REG_BANK_CLKGEN0 0x0580 ++#define CLKGEN0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN0) ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN0_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN0_BASE, 0x1D) ++#define reg_ckg_emmc GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++ ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK_XTAL 0 ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_300K 13 ++#define BIT_FCIE_CLK_48M 15 ++ ++#define BIT_FCIE_CLK4X_20M 0 ++#define BIT_FCIE_CLK4X_27M 1 ++#define BIT_FCIE_CLK4X_36M 2 ++#define BIT_FCIE_CLK4X_40M 3 ++#define BIT_FCIE_CLK4X_48M 4 ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BANK_CHIPTOP 0x0F00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define reg_pcm_d_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x09) ++#define reg_pcm_a_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0A) ++#define reg_pcm2_cd_n_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define reg_nand_ps GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0D) ++ ++#define reg_fcie2macro_sd_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x10) ++#define FCIE2MACRO_SD_BYPASS BIT8 ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT8 ++#define BIT_SW_RST_Z BIT9 ++#define BIT_SW_RST_Z_EN BIT10 ++ ++#define reg_sd_use_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x40) ++#define SD_USE_BYPASS BIT0 ++ ++#define reg_all_pad_in GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_sd_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define CFG_SD_PAD_MASK (BIT8|BIT9|BIT10|BIT11) ++ ++#define reg_pcmcia_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define CFG_PCMCIA_PAD_MASK (BIT0|BIT4) ++ ++#define reg_emmc_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6E) ++#define CFG_EMMC_PAD_MASK (BIT6|BIT7) ++ ++#define reg_nand_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++#define CFG_NAND_PAD_MASK (BIT6|BIT7) ++ ++#define eMMC_DBUS_WIDTH 8 ++ ++#define eMMC_RST_L() ++#define eMMC_RST_H() ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // Need to confirm ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++#define MIU_CHECK_LAST_DONE 1 ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_eiffel_linux.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_eiffel_linux.h +new file mode 100644 +index 00000000..a2411816 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_eiffel_linux.h +@@ -0,0 +1,455 @@ ++#ifndef __eMMC_EIFFEL_LINUX__ ++#define __eMMC_EIFFEL_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_DEBUG_FS ++#include ++#include ++#endif ++#include "chip_int.h" ++ ++#include ++#include ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++#define REG_BANK_CLKGEN0 0x0580 ++#define CLKGEN0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN0) ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN0_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN0_BASE, 0x1D) ++#define reg_ckg_emmc GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++ ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK_XTAL 0 ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_300K 13 ++#define BIT_FCIE_CLK_48M 15 ++ ++#define BIT_FCIE_CLK4X_20M 0 ++#define BIT_FCIE_CLK4X_27M 1 ++#define BIT_FCIE_CLK4X_36M 2 ++#define BIT_FCIE_CLK4X_40M 3 ++#define BIT_FCIE_CLK4X_48M 4 ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BANK_CHIPTOP 0x0F00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define reg_pcm_d_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x09) ++#define reg_pcm_a_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0A) ++#define reg_pcm2_cd_n_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define reg_nand_ps GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0D) ++ ++#define reg_fcie2macro_sd_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x10) ++#define FCIE2MACRO_SD_BYPASS BIT8 ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT8 ++#define BIT_SW_RST_Z BIT9 ++#define BIT_SW_RST_Z_EN BIT10 ++ ++#define reg_sd_use_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x40) ++#define SD_USE_BYPASS BIT0 ++ ++#define reg_all_pad_in GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_sd_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define CFG_SD_PAD_MASK (BIT8|BIT9|BIT10|BIT11) ++ ++#define reg_pcmcia_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define CFG_PCMCIA_PAD_MASK (BIT0|BIT4) ++ ++#define reg_emmc_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6E) ++#define CFG_EMMC_PAD_MASK (BIT6|BIT7) ++ ++#define reg_nand_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++#define CFG_NAND_PAD_MASK (BIT6|BIT7) ++ ++#define eMMC_DBUS_WIDTH 8 ++ ++#define eMMC_RST_L() ++#define eMMC_RST_H() ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_SDR // [FIXME] ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 0 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // Need to confirm ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++#define MIU_CHECK_LAST_DONE 1 ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_einstein_linux.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_einstein_linux.h +new file mode 100644 +index 00000000..d55547b2 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_einstein_linux.h +@@ -0,0 +1,455 @@ ++#ifndef __eMMC_EINSTEIN_LINUX__ ++#define __eMMC_EINSTEIN_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_DEBUG_FS ++#include ++#include ++#endif ++#include "chip_int.h" ++ ++#include ++#include ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++#define REG_OFFSET_SHIFT_BITS 2 ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(Reg_Addr)) ++#define GET_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_SHIFT_BITS)) ++ ++#define REG_FCIE(reg_addr) REG_FCIE_U16(reg_addr) ++#define REG_FCIE_W(reg_addr, val) REG_FCIE(reg_addr) = (val) ++#define REG_FCIE_R(reg_addr, val) val = REG_FCIE(reg_addr) ++#define REG_FCIE_SETBIT(reg_addr, val) REG_FCIE(reg_addr) |= (val) ++#define REG_FCIE_CLRBIT(reg_addr, val) REG_FCIE(reg_addr) &= ~(val) ++#define REG_FCIE_W1C(reg_addr, val) REG_FCIE_W(reg_addr, REG_FCIE(reg_addr)&(val)) ++ ++//------------------------------ ++#define RIU_PM_BASE (IO_ADDRESS(0x1F000000)) ++#define RIU_BASE (IO_ADDRESS(0x1F200000)) ++ ++#define REG_BANK_FCIE0 0x8980 ++#define REG_BANK_FCIE1 0x89E0 ++#define REG_BANK_FCIE2 0x8A00 ++ ++#define FCIE0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE0) ++#define FCIE1_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE1) ++#define FCIE2_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_FCIE2) ++ ++#define FCIE_REG_BASE_ADDR FCIE0_BASE ++#define FCIE_CIFC_BASE_ADDR FCIE1_BASE ++#define FCIE_CIFD_BASE_ADDR FCIE2_BASE ++ ++#include "eMMC_reg.h" ++ ++//------------------------------ ++#define REG_BANK_CLKGEN0 0x0580 ++#define CLKGEN0_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CLKGEN0) ++ ++#define reg_ckg_MCU GET_REG_ADDR(CLKGEN0_BASE, 0x10) ++#define reg_ckg_MIU GET_REG_ADDR(CLKGEN0_BASE, 0x1D) ++#define reg_ckg_emmc GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++ ++#define reg_ckg_fcie_1X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define reg_ckg_fcie_4X GET_REG_ADDR(CLKGEN0_BASE, 0x64) ++#define BIT_FCIE_CLK_Gate BIT0 ++#define BIT_FCIE_CLK_Inverse BIT1 ++#define BIT_FCIE_CLK_MASK (BIT2|BIT3|BIT4|BIT5) ++#define BIT_FCIE_CLK_SHIFT 2 ++#define BIT_FCIE_CLK_SEL BIT6 // 1: NFIE, 0: 12MHz ++#define BIT_FCIE_CLK4X_Gate BIT8 ++#define BIT_FCIE_CLK4X_Inverse BIT9 ++#define BIT_FCIE_CLK4X_MASK (BIT10|BIT11|BIT12) ++#define BIT_FCIE_CLK4X_SHIFT 10 ++ ++#define BIT_FCIE_CLK_XTAL 0 ++#define BIT_FCIE_CLK_20M 1 ++#define BIT_FCIE_CLK_27M 2 ++#define BIT_FCIE_CLK_32M 3 ++#define BIT_FCIE_CLK_36M 4 ++#define BIT_FCIE_CLK_40M 5 ++#define BIT_FCIE_CLK_43_2M 6 ++#define BIT_FCIE_CLK_300K 13 ++#define BIT_FCIE_CLK_48M 15 ++ ++#define BIT_FCIE_CLK4X_20M 0 ++#define BIT_FCIE_CLK4X_27M 1 ++#define BIT_FCIE_CLK4X_36M 2 ++#define BIT_FCIE_CLK4X_40M 3 ++#define BIT_FCIE_CLK4X_48M 4 ++ ++ ++#define eMMC_FCIE_VALID_CLK_CNT 5 ++extern U8 gau8_FCIEClkSel[]; ++ ++//--------------------------sd/eMMC/nand Mode ++#define REG_BANK_CHIPTOP 0x0F00 ++#define PAD_CHIPTOP_BASE GET_REG_ADDR(RIU_BASE, REG_BANK_CHIPTOP) ++ ++#define reg_emmc_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x08) ++#define reg_pcm_d_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x09) ++#define reg_pcm_a_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0A) ++#define reg_pcm2_cd_n_pe GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0B) ++#define reg_nand_drv GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0C) ++#define reg_nand_ps GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x0D) ++ ++#define reg_fcie2macro_sd_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x10) ++#define FCIE2MACRO_SD_BYPASS BIT8 ++ ++#define reg_chip_dummy1 GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x1D) ++#define BIT_DDR_TIMING_PATCH BIT8 ++#define BIT_SW_RST_Z BIT9 ++#define BIT_SW_RST_Z_EN BIT10 ++ ++#define reg_sd_use_bypass GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x40) ++#define SD_USE_BYPASS BIT0 ++ ++#define reg_all_pad_in GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x50) ++#define BIT_ALL_PAD_IN BIT15 ++ ++#define reg_sd_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x5A) ++#define CFG_SD_PAD_MASK (BIT8|BIT9|BIT10|BIT11) ++ ++#define reg_pcmcia_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x64) ++#define CFG_PCMCIA_PAD_MASK (BIT0|BIT4) ++ ++#define reg_emmc_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6E) ++#define CFG_EMMC_PAD_MASK (BIT6|BIT7) ++ ++#define reg_nand_pad GET_REG_ADDR(PAD_CHIPTOP_BASE, 0x6F) ++#define CFG_NAND_PAD_MASK (BIT6|BIT7) ++ ++#define eMMC_DBUS_WIDTH 8 ++ ++#define eMMC_RST_L() ++#define eMMC_RST_H() ++ ++//===================================================== ++// API declarations ++//===================================================== ++extern U32 eMMC_hw_timer_delay(U32 u32us); ++extern U32 eMMC_hw_timer_sleep(U32 u32ms); ++ ++#define eMMC_HW_TIMER_MHZ (32*1024)//(384*100*1000) // [FIXME] ++#define FCIE_eMMC_DISABLE 0 ++#define FCIE_eMMC_DDR 1 ++#define FCIE_eMMC_SDR 2 ++#define FCIE_eMMC_BYPASS 3 ++#define FCIE_eMMC_TMUX 4 ++#define FCIE_DEFAULT_PAD FCIE_eMMC_BYPASS // [FIXME] ++ ++extern U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type); ++extern U32 eMMC_clock_setting(U16 u16_ClkParam); ++extern U32 eMMC_clock_gating(void); ++extern void eMMC_set_WatchDog(U8 u8_IfEnable); ++extern void eMMC_reset_WatchDog(void); ++extern U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt); ++extern void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size); ++extern void eMMC_flush_miu_pipe(void); ++extern U32 eMMC_PlatformResetPre(void); ++extern U32 eMMC_PlatformResetPost(void); ++extern U32 eMMC_PlatformInit(void); ++extern U32 eMMC_CheckIfMemCorrupt(void); ++extern void eMMC_DumpPadClk(void); ++#define eMMC_BOOT_PART_W BIT0 ++#define eMMC_BOOT_PART_R BIT1 ++extern U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP); ++extern U32 eMMC_BootPartitionHandler_E(U16 u16_PartType); ++extern U32 eMMC_hw_timer_start(void); ++extern U32 eMMC_hw_timer_tick(void); ++extern irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy); // [FIXME] ++extern U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec); ++extern struct mutex FCIE3_mutex; ++extern void eMMC_LockFCIE(U8 *pu8_str); ++extern void eMMC_UnlockFCIE(U8 *pu8_str); ++ ++ ++//===================================================== ++// partitions config ++//===================================================== ++// every blk is 512 bytes (reserve 2MB for internal use) ++// reserve 0x1200 x 0x200, more than 2MB ++#define eMMC_DRV_RESERVED_BLK_CNT (0x200000/0x200) ++ ++#define eMMC_CIS_NNI_BLK_CNT 2 ++#define eMMC_CIS_PNI_BLK_CNT 2 ++#define eMMC_TEST_BLK_CNT (0x100000/0x200) ++ ++#define eMMC_CIS_BLK_0 (64*1024/512) // from 64KB ++#define eMMC_NNI_BLK_0 (eMMC_CIS_BLK_0+0) ++#define eMMC_NNI_BLK_1 (eMMC_CIS_BLK_0+1) ++#define eMMC_PNI_BLK_0 (eMMC_CIS_BLK_0+2) ++#define eMMC_PNI_BLK_1 (eMMC_CIS_BLK_0+3) ++#define eMMC_DDRTABLE_BLK_0 (eMMC_CIS_BLK_0+4) ++#define eMMC_DDRTABLE_BLK_1 (eMMC_CIS_BLK_0+5) ++#define eMMC_DrvContext_BLK_0 (eMMC_CIS_BLK_0+6) ++#define eMMC_DrvContext_BLK_1 (eMMC_CIS_BLK_0+7) ++#define eMMC_ALLRSP_BLK_0 (eMMC_CIS_BLK_0+8) ++#define eMMC_ALLRSP_BLK_1 (eMMC_CIS_BLK_0+9) ++#define eMMC_CIS_BLK_END eMMC_ALLRSP_BLK_1 ++ ++// last 1MB in reserved area, use for eMMC test ++#define eMMC_TEST_BLK_0 (eMMC_DRV_RESERVED_BLK_CNT-eMMC_TEST_BLK_CNT) ++ ++ ++#define eMMC_LOGI_PART 0x8000 // bit-or if the partition needs Wear-Leveling ++#define eMMC_HIDDEN_PART 0x4000 // bit-or if this partition is hidden, normally it is set for the LOGI PARTs. ++ ++#define eMMC_PART_HWCONFIG (1|eMMC_LOGI_PART) ++#define eMMC_PART_BOOTLOGO (2|eMMC_LOGI_PART) ++#define eMMC_PART_BL (3|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OS (4|eMMC_LOGI_PART) ++#define eMMC_PART_CUS (5|eMMC_LOGI_PART) ++#define eMMC_PART_UBOOT (6|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_SECINFO (7|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_OTP (8|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++#define eMMC_PART_RECOVERY (9|eMMC_LOGI_PART) ++#define eMMC_PART_E2PBAK (10|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAMBAK (11|eMMC_LOGI_PART) ++#define eMMC_PART_APANIC (12|eMMC_LOGI_PART) ++#define eMMC_PART_ENV (13|eMMC_LOGI_PART|eMMC_HIDDEN_PART) // uboot env ++#define eMMC_PART_MISC (14|eMMC_LOGI_PART) ++#define eMMC_PART_DEV_NODE (15|eMMC_LOGI_PART|eMMC_HIDDEN_PART) ++ ++#define eMMC_PART_FDD (17|eMMC_LOGI_PART) ++#define eMMC_PART_TDD (18|eMMC_LOGI_PART) ++ ++#define eMMC_PART_E2P0 (19|eMMC_LOGI_PART) ++#define eMMC_PART_E2P1 (20|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM0 (21|eMMC_LOGI_PART) ++#define eMMC_PART_NVRAM1 (22|eMMC_LOGI_PART) ++#define eMMC_PART_SYSTEM (23|eMMC_LOGI_PART) ++#define eMMC_PART_CACHE (24|eMMC_LOGI_PART) ++#define eMMC_PART_DATA (25|eMMC_LOGI_PART) ++#define eMMC_PART_FAT (26|eMMC_LOGI_PART) ++ ++extern char *gpas8_eMMCPartName[]; ++ ++//===================================================== ++// Driver configs ++//===================================================== ++#define DRIVER_NAME "mstar_mci" ++#define eMMC_UPDATE_FIRMWARE 0 ++ ++#define eMMC_ST_PLAT 0x80000000 ++// [CAUTION]: to verify IP and HAL code, defaut 0 ++#define IF_IP_VERIFY 0 // [FIXME] --> ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++#define IF_DETECT_eMMC_DDR_TIMING 0 ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_TUNING) ++ ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 1 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++#define eMMC_RSP_FROM_RAM 1 ++ ++//------------------------------ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KB ++extern U8 gau8_eMMC_SectorBuf[]; ++extern U8 gau8_eMMC_PartInfoBuf[]; ++ ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_WARNING ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() Ln.%u ] ", __FUNCTION__, __LINE__); \ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(str) {eMMC_printf("eMMC Die: %s() Ln.%u, %s \n", __FUNCTION__, __LINE__, str); \ ++ panic("\n");} ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++#define REG_BANK_TIMER1 0x1800 ++#define TIMER1_BASE GET_REG_ADDR(RIU_PM_BASE, REG_BANK_TIMER1) ++ ++#define TIMER1_ENABLE GET_REG_ADDR(TIMER1_BASE, 0x20) ++#define TIMER1_HIT GET_REG_ADDR(TIMER1_BASE, 0x21) ++#define TIMER1_MAX_LOW GET_REG_ADDR(TIMER1_BASE, 0x22) ++#define TIMER1_MAX_HIGH GET_REG_ADDR(TIMER1_BASE, 0x23) ++#define TIMER1_CAP_LOW GET_REG_ADDR(TIMER1_BASE, 0x24) ++#define TIMER1_CAP_HIGH GET_REG_ADDR(TIMER1_BASE, 0x25) ++ ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_SLOW_CLK BIT_FCIE_CLK_20M ++#define FCIE_DEFAULT_CLK BIT_FCIE_CLK_48M ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // Need to confirm ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++#define MIU_CHECK_LAST_DONE 1 ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++#if (defined(BIT_DQS_MODE_MASK) && (BIT_DQS_MODE_MASK != (BIT12|BIT13|BIT14))) ++ ++#undef BIT_DQS_MODE_MASK ++#undef BIT_DQS_MODE_2T ++#undef BIT_DQS_MODE_1_5T ++#undef BIT_DQS_MODE_2_5T ++#undef BIT_DQS_MODE_1T ++ ++#define BIT_DQS_MODE_MASK (BIT12|BIT13|BIT14) ++#define BIT_DQS_MODE_0T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_0_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (3 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2T (4 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (5 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3T (6 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_3_5T (7 << BIT_DQS_MDOE_SHIFT) ++ ++#endif ++ ++#endif /* __eMMC_G2P_UBOOT__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_reg.h b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_reg.h +new file mode 100644 +index 00000000..cebc6bc1 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/inc/config/eMMC_reg.h +@@ -0,0 +1,381 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_FCIE_REG_H__ ++#define __eMMC_FCIE_REG_H__ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++#ifndef BIT0 ++#define BIT0 (1<<0) ++#endif ++#ifndef BIT1 ++#define BIT1 (1<<1) ++#endif ++#ifndef BIT2 ++#define BIT2 (1<<2) ++#endif ++#ifndef BIT3 ++#define BIT3 (1<<3) ++#endif ++#ifndef BIT4 ++#define BIT4 (1<<4) ++#endif ++#ifndef BIT5 ++#define BIT5 (1<<5) ++#endif ++#ifndef BIT6 ++#define BIT6 (1<<6) ++#endif ++#ifndef BIT7 ++#define BIT7 (1<<7) ++#endif ++#ifndef BIT8 ++#define BIT8 (1<<8) ++#endif ++#ifndef BIT9 ++#define BIT9 (1<<9) ++#endif ++#ifndef BIT10 ++#define BIT10 (1<<10) ++#endif ++#ifndef BIT11 ++#define BIT11 (1<<11) ++#endif ++#ifndef BIT12 ++#define BIT12 (1<<12) ++#endif ++#ifndef BIT13 ++#define BIT13 (1<<13) ++#endif ++#ifndef BIT14 ++#define BIT14 (1<<14) ++#endif ++#ifndef BIT15 ++#define BIT15 (1<<15) ++#endif ++#ifndef BIT16 ++#define BIT16 (1<<16) ++#endif ++#ifndef BIT17 ++#define BIT17 (1<<17) ++#endif ++#ifndef BIT18 ++#define BIT18 (1<<18) ++#endif ++#ifndef BIT19 ++#define BIT19 (1<<19) ++#endif ++#ifndef BIT20 ++#define BIT20 (1<<20) ++#endif ++#ifndef BIT21 ++#define BIT21 (1<<21) ++#endif ++#ifndef BIT22 ++#define BIT22 (1<<22) ++#endif ++#ifndef BIT23 ++#define BIT23 (1<<23) ++#endif ++#ifndef BIT24 ++#define BIT24 (1<<24) ++#endif ++#ifndef BIT25 ++#define BIT25 (1<<25) ++#endif ++#ifndef BIT26 ++#define BIT26 (1<<26) ++#endif ++#ifndef BIT27 ++#define BIT27 (1<<27) ++#endif ++#ifndef BIT28 ++#define BIT28 (1<<28) ++#endif ++#ifndef BIT29 ++#define BIT29 (1<<29) ++#endif ++#ifndef BIT30 ++#define BIT30 (1<<30) ++#endif ++#ifndef BIT31 ++#define BIT31 (1<<31) ++#endif ++ ++//------------------------------------------------------------------ ++#define FCIE_MIE_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x00) ++#define FCIE_MIE_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x01) ++#define FCIE_MMA_PRI_REG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x02) ++#define FCIE_MIU_DMA_26_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x03) ++#define FCIE_MIU_DMA_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x04) ++#define FCIE_CARD_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x06) ++#define FCIE_CARD_POWER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x08) ++#define FCIE_FORCE_INT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x09) ++#define FCIE_PATH_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0A) ++#define FCIE_JOB_BL_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0B) ++#define FCIE_TR_BK_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0C) ++#define FCIE_RSP_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0D) ++#define FCIE_CMD_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0E) ++#define FCIE_CIFD_WORD_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0F) ++#define FCIE_SD_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_SD_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++#define FCIE_SD_STATUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x12) ++#define FCIE_REG16h GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x16) ++#define FCIE_SDIO_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1B) ++#define FCIE_SDIO_ADDR0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1C) ++#define FCIE_SDIO_ADDR1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1D) ++#define FCIE_SM_STS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2C) ++#define FCIE_REG_2Dh GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2D) ++#define FCIE_MIU_OFFSET GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2E) ++#define FCIE_BOOT_CONFIG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2F) ++#define FCIE_TEST_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x30) ++#define FCIE_DEBUG_BUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x31) ++#define FCIE_MACRO_REDNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x32) ++#define FCIE_TOGGLE_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x33) ++#define FCIE_PWR_SAVE_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x35) ++#define FCIE_MISC GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x36) ++#define NC_WIDTH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x41) ++ ++#define FCIE_CIFC_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFC_BASE_ADDR, u16_pos) ++#define FCIE_CIFC_BYTE_CNT 0x40 // 32 x 16 bits ++ ++#define FCIE_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFD_BASE_ADDR, u16_pos) ++#define FCIE_CIFD_BYTE_CNT 0x200 // 256 x 16 bits ++ ++//------------------------------------------------------------------ ++/* FCIE_MIE_EVENT 0x00 */ ++/* FCIE_MIE_INT_EN 0x01 */ ++#define BIT_MMA_DATA_END BIT0 ++#define BIT_SD_CMD_END BIT1 ++#define BIT_SD_DATA_END BIT2 ++#define BIT_SD_BUSY_END BIT4 ++#define BIT_CARD_DMA_END BIT11 ++#define BIT_MIU_LAST_DONE BIT14 ++#define BIT_CARD_BOOT_DONE BIT15 ++#define BIT_ALL_CARD_INT_EVENTS (BIT_MMA_DATA_END|BIT_SD_CMD_END|BIT_SD_DATA_END|BIT_SD_BUSY_END\ ++ |BIT_CARD_DMA_END|BIT_MIU_LAST_DONE|BIT_CARD_BOOT_DONE) ++/* FCIE_MMA_PRI_REG 0x02 */ ++#define BIT_DMA_DIR_W BIT2 ++#define BIT_MIU_REQUEST_RST BIT4 ++#define BIT_FIFO_CLKRDY BIT5 ++#define BIT_MIU_BURST_MASK (BIT8|BIT9|BIT10) ++#define BIT_MIU_BURST_CTRL BIT10 ++#define BIT_MIU_BURST_8 BIT_MIU_BURST_CTRL ++#define BIT_MIU_BURST_16 (BIT8|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_BURST_32 (BIT9|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_CLK_EN_SW BIT12 ++#define BIT_MIU_CLK_EN_HW BIT13 ++#define BIT_MIU_CLK_CTRL_SEL_SW BIT14 ++#define BIT_MIU_CLK_FREE_RUN BIT15 ++/* FCIE_MIU_DMA_26_16 0x03 */ ++#define BIT_MIU1_SELECT BIT15 ++/* FCIE_CARD_POWER 0x08 */ ++#define BIT_SD_PWR_ON_n BIT0 ++#define BIT_SD_PWR_OUT_n BIT2 ++/* FCIE_PATH_CTRL 0x0A */ ++#define BIT_MMA_EN BIT0 ++#define BIT_SD_EN BIT1 ++/* FCIE_JOB_BL_CNT 0x0B */ ++#define BIT_SD_JOB_BLK_CNT_MASK (BIT12-1) ++/* FCIE_RSP_SIZE 0x0D */ ++#define BIT_SD_RSP_SIZE_MASK (BIT7-1) ++/* FCIE_SD_MODE 0x10 */ ++#define BIT_SD_CLK_EN BIT0 ++#define BIT_SD_DATA_WIDTH_MASK (BIT1|BIT2) ++#define BIT_SD_DATA_WIDTH_1 0 ++#define BIT_SD_DATA_WIDTH_4 BIT1 ++#define BIT_SD_DATA_WIDTH_8 BIT2 ++#define BIT_SD_IF_LOW BIT3 ++#define BIT_SD_CLK_AUTO_STOP BIT4 ++#define BIT_SD_DATA_CIFD BIT5 ++#define BIT_SD_DATA_SYNC BIT6 // set for eMMC High Speed Mode ++#define BIT_SD_SELECT_SDIO BIT9 ++#define BIT_SD_DMA_R_CLK_STOP BIT11 ++ ++//#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_CLK_EN) ++#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_DATA_SYNC|BIT_SD_CLK_EN) ++ ++/* FCIE_SD_CTRL 0x11 */ ++#define BIT_SD_RSPR2_EN BIT0 ++#define BIT_SD_RSP_EN BIT1 ++#define BIT_SD_CMD_EN BIT2 ++#define BIT_SD_DAT_EN BIT3 ++#define BIT_SD_DAT_DIR_W BIT4 ++#define BIT_SD_BUSY_DET_ON BIT5 ++/* FCIE_SD_STATUS 0x12 */ ++#define BIT_SD_R_CRC_ERR BIT0 ++#define BIT_SD_W_FAIL BIT1 ++#define BIT_SD_W_CRC_ERR BIT2 ++#define BIT_SD_RSP_TIMEOUT BIT3 ++#define BIT_SD_RSP_CRC_ERR BIT4 ++#define BIT_SD_CARD_WP BIT5 ++#define BIT_SD_CARD_BUSY BIT6 ++#define BIT_SD_D0 BIT8 ++#define BIT_SD_DBUS_MASK (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++#define BIT_SD_DBUS_SHIFT 8 ++ ++//#define BIT_SD_FCIE_ERR_FLAGS ((BIT5-1)|BIT_SD_CARD_BUSY) ++#define BIT_SD_FCIE_ERR_FLAGS (BIT5-1) ++#define BIT_SD_CARD_D0_ST BIT8 ++#define BIT_SD_CARD_D1_ST BIT9 ++#define BIT_SD_CARD_D2_ST BIT10 ++#define BIT_SD_CARD_D3_ST BIT11 ++#define BIT_SD_CARD_D4_ST BIT12 ++#define BIT_SD_CARD_D5_ST BIT13 ++#define BIT_SD_CARD_D6_ST BIT14 ++#define BIT_SD_CARD_D7_ST BIT15 ++/* FCIE_REG16h */ ++#define BIT_EMMC_ACTIVE BIT0 ++/* FCIE_SDIO_CTRL 0x1B */ ++#define BIT_SDIO_BLK_SIZE_MASK (BIT13-1) ++#define BIT_SDIO_BLK_MODE BIT15 ++/* FCIE_SM_STS 0x2C */ ++#define BIT_DQS_DELAY_CELL_MASK (BIT8|BIT9|BIT10|BIT11) ++#define BIT_DQS_DELAY_CELL_SHIFT 8 ++#define BIT_DQS_MODE_MASK (BIT12|BIT13) ++#define BIT_DQS_MDOE_SHIFT 12 ++#define BIT_DQS_MODE_2T (0 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1_5T (1 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_2_5T (2 << BIT_DQS_MDOE_SHIFT) ++#define BIT_DQS_MODE_1T (3 << BIT_DQS_MDOE_SHIFT) ++/* FCIE_REG_2Dh 0x2D */ ++#define BIT_NEW_DESIGN_ENn BIT14 ++/* FCIE_BOOT_CONFIG 0x2F */ ++#define BIT_BOOT_STG2_EN BIT0 ++#define BIT_BOOT_END_EN BIT1 ++#define BIT_BOOT_MODE_EN BIT2 ++#define BIT_MACRO_EN BIT8 ++#define BIT_SD_DDR_EN BIT9 ++#define BIT_SD_BYPASS_MODE_EN BIT10 ++#define BIT_SD_SDR_IN_BYPASS BIT11 ++#define BIT_SD_FROM_TMUX BIT12 ++#define BIT_SD_CLKOE_DELAY_EN BIT13 ++/* FCIE_TEST_MODE 0x30 */ ++#define BIT_FCIE_BIST_FAIL (BIT0|BIT1|BIT2|BIT3|BIT4) ++#define BIT_FCIE_DEBUG_MODE_MASK (BIT8|BIT9|BIT10) ++#define BIT_FCIE_DEBUG_MODE_SHIFT 8 ++#define BIT_FCIE_SOFT_RST_n BIT12 ++#define BIT_FCIE_PPFIFO_CLK BIT14 ++/* FCIE_MACRO_REDNT 0x32 */ ++#define BIT_DQS_DELAY_CELL_SEL_MASK (BIT0|BIT1|BIT2|BIT3) ++#define BIT_MACRO_TEST_MODE_MASK (BIT4|BIT5) ++#define BIT_MACRO_DIR BIT6 ++#define BIT_TOGGLE_CNT_RST BIT7 ++/* FCIE_TOGGLE_CNT */ ++#define BITS_8_R_TOGGLE_CNT 0x111 ++#define BITS_4_R_TOGGLE_CNT 0x211 ++#define BITS_8_W_TOGGLE_CNT 0x11A ++#define BITS_4_W_TOGGLE_CNT 0x21A ++/* FCIE_PWR_SAVE_MODE 0x35 */ ++#define BIT_POWER_SAVE_MODE_EN BIT0 /* Power Save HW enable, high active */ ++#define BIT_SD_POWER_SAVE_RIU BIT1 /* SW set register to emulate power lost event, high active */ ++#define BIT_POWER_SAVE_MODE_INT_EN BIT2 /* interrupt enable, high active */ ++#define BIT_SD_POWER_SAVE_RST BIT3 /* software reset Power Save HW, default is '1', set '0' to reset HW */ ++#define BIT_RIU_SAVE_EVENT BIT5 /* RO, RIU emulation power save event */ ++#define BIT_RST_SAVE_EVENT BIT6 /* RO, Hardware reset power save event */ ++#define BIT_BAT_SAVE_EVENT BIT7 /* RO, Battery lost power save event */ ++ ++/* NC_WIDTH 0x41 */ ++#define BIT_NC_DEB_SEL_SHIFT 12 ++#define BIT_NC_DEB_SEL_MASK (BIT12|BIT13|BIT14) ++#define BIT_NC_BCH_DEB_SEL BIT15 ++ ++//------------------------------------------------------------------ ++/* ++ * Power Save FIFO Cmd* ++ */ ++#define PWR_BAT_CLASS (0x1 << 13) /* Battery lost class */ ++#define PWR_RST_CLASS (0x1 << 12) /* Reset Class */ ++ ++/* Command Type */ ++#define PWR_CMD_WREG (0x0 << 9) /* Write data */ ++#define PWR_CMD_RDCP (0x1 << 9) /* Read and cmp data. If mismatch, HW retry */ ++#define PWR_CMD_WAIT (0x2 << 9) /* Wait idle, max. 128T */ ++#define PWR_CMD_WINT (0x3 << 9) /* Wait interrupt */ ++#define PWR_CMD_STOP (0x7 << 9) /* Stop */ ++ ++/* RIU Bank */ ++#define PWR_CMD_BK0 (0x0 << 7) ++#define PWR_CMD_BK1 (0x1 << 7) ++#define PWR_CMD_BK2 (0x2 << 7) ++#define PWR_CMD_BK3 (0x3 << 7) ++ ++#define PWR_RIU_ADDR (0x0 << 0) ++ ++#endif /* __eMMC_FCIE_REG_H__ */ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/src/api/eMMC_prg.c b/drivers/mstar/emmc/chicago/eMMCDrv/src/api/eMMC_prg.c +new file mode 100644 +index 00000000..dcb6ac70 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/src/api/eMMC_prg.c +@@ -0,0 +1,2046 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++ ++#include "eMMC.h" ++ ++ ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++static U32 eMMC_ReadPartitionInfo_Ex(void); ++static U32 eMMC_GetPartitionIndex(U16 u16_PartType, ++ U32 u32_LogicIdx, ++ volatile U16 *pu16_PartIdx); ++ ++/* frequency bases */ ++/* divided by 10 to be nice to platforms without floating point */ ++int fbase[] = { ++ 10000, ++ 100000, ++ 1000000, ++ 10000000, ++}; ++ ++/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice ++ * to platforms without floating point. ++ */ ++int multipliers[] = { ++ 0, /* reserved */ ++ 10, ++ 12, ++ 13, ++ 15, ++ 20, ++ 25, ++ 30, ++ 35, ++ 40, ++ 45, ++ 50, ++ 55, ++ 60, ++ 70, ++ 80, ++}; ++ ++//======================================================== ++U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt) ++{ ++ U32 u32_err, u32_i; ++ U16 u16_reg, u16_retry=0; ++ ++ // -------------------------------- ++ eMMC_PlatformInit(); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ //*(U16*)0x25020DD4 &= ~BIT6; // FPGA only ++ ++ LABEL_BOOT_MODE_START: ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ // -------------------------------- ++ eMMC_RST_L(); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1ms); ++ eMMC_RST_H(); ++ ++ u32_i = 0; ++ while(u32_i < u32_ItemCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"i:%u SecCnt:%Xh \n", u32_i, pu32_SectorCnt[u32_i]); ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, pu32_SectorCnt[u32_i]); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, pu32_Addr[u32_i] & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, pu32_Addr[u32_i] >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (pu32_Addr[u32_i]>>3) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(pu32_Addr[u32_i]>>3) >> 16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ if(0 == u32_i) // stg.1 ++ { ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_MODE_EN); ++ } ++ else // stg.2 ++ { ++ // can NOT set BIT_SD_DAT_EN ++ //REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_STG2_EN); ++ } ++ //eMMC_printf("BBB"); ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE, HW_TIMER_DELAY_1s); ++ ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((0==u16_retry) && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ u16_retry++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #if 0 ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ #endif ++ goto LABEL_BOOT_MODE_START; ++ } ++ #if 0 ++ else if(u16_retry && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry fail, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ } ++ #endif ++ u32_i++; ++ } ++ ++ // -------------------------------- ++ // boot end ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_END_EN); ++ //eMMC_printf("CCC"); ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_CARD_BOOT_DONE, HW_TIMER_DELAY_1s); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_LOAD_IMAGE_END: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: %Xh\n", u32_err); ++ return u32_err; ++} ++ ++ ++ ++//======================================================== ++U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID) ++{ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ *pu8IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(pu8ID, g_eMMCDrv.au8_ID, eMMC_ID_BYTE_CNT); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_CheckCIS(eMMC_CIS_t *ptCISData) ++{ ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ U32 u32_ChkSum; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ if (eMMC_CompareCISTag(peMMCInfo->au8_Tag)) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI Tag mismatch\n"); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&peMMCInfo->u16_SpareByteCnt, (U16)((U32)(&peMMCInfo->u16_SeqAccessTime)-(U32)(&peMMCInfo->u16_SpareByteCnt))); ++ if (u32_ChkSum != peMMCInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, peMMCInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)peMMCInfo, 0x200); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&pPartInfo->u16_SpareByteCnt, 0x200-0x04); ++ if (u32_ChkSum != pPartInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pni chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, pPartInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)pPartInfo, 0x200); ++ return eMMC_ST_ERR_CIS_PNI; ++ } ++ ++ eMMC_dump_nni(peMMCInfo); ++ eMMC_dump_pni(pPartInfo); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#if 0 ++U32 eMMC_WriteCIS(eMMC_CIS_t *ptCISData) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ u32_err = eMMC_CheckCIS(ptCISData); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ---------------------------- ++ // write NNI in Blk0 and Blk1 ++ for(u16_i=0; u16_iau8_Vendor, 16); ++ memcpy(g_eMMCDrv.au8_PartNumber, peMMCInfo->au8_PartNumber, 16); ++ ++ return u32_err; ++} ++#endif ++ ++// read CIS and set config to UNFD ++U32 eMMC_ReadCIS(eMMC_CIS_t *ptCISData) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ // read NNI in Blk0 and Blk1 ++ for(u16_i=0; u16_iu32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SpareByteCnt: %04Xh \n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PageByteCnt: %04Xh \n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkPageCnt: %04Xh \n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartitionCnt: %04Xh \n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"RecByteCnt: %04Xh \n", pPartInfo->u16_UnitByteCnt); ++ ++ u32_PniBlkByteCnt = pPartInfo->u16_PageByteCnt * pPartInfo->u16_BlkPageCnt; ++ u32_PniBlkCnt = 0; ++ ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Partition: %02u \n", u16_i); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"StartBlk: %04Xh \n", pPartInfo->records[u16_i].u16_StartBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->records[u16_i].u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartType: %04Xh \n", pPartInfo->records[u16_i].u16_PartType); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BackupBlkCnt:%04Xh \n", pPartInfo->records[u16_i].u16_BackupBlkCnt); ++ ++ if(u16_i < pPartInfo->u16_PartCnt-1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u KB\n", ++ (u32_PniBlkByteCnt * pPartInfo->records[u16_i].u16_BlkCnt)>>10); ++ ++ u32_PniBlkCnt += pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u MB\n", ++ (g_eMMCDrv.u32_SEC_COUNT - (u32_PniBlkCnt*u32_PniBlkByteCnt>>9))>>11); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// data length is 512 bytes ++U32 eMMC_FATAutoSize(void) ++{ ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ volatile U32 u32_PartSectorCnt=0; ++ ++ // calculate FAT sector cnt ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ ++ else if(u32_PartSectorCnt) ++ u32_PartSectorCnt += ++ (pPartInfo->records[u16_i].u16_BlkCnt + pPartInfo->records[u16_i].u16_BackupBlkCnt) ++ * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ g_eMMCDrv.u32_FATSectorCnt = g_eMMCDrv.u32_SEC_COUNT - u32_PartSectorCnt; ++ ++ u32_PartSectorCnt = 0; ++ // shift the StartBlk for partitions following FAT ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ { ++ pPartInfo->records[u16_i].u16_BlkCnt = ++ g_eMMCDrv.u32_FATSectorCnt / pPartInfo->u16_BlkPageCnt; ++ ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk + ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ else if(u32_PartSectorCnt) ++ { ++ pPartInfo->records[u16_i].u16_StartBlk = u32_PartSectorCnt; ++ ++ u32_PartSectorCnt += ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U32 eMMC_ReadPartitionInfo_Ex(void) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // read Partition Info from Blk0 and Blk1 (check) ++ for(u16_i=0; u16_iu32_ChkSum || pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info %u ChkSum failed: %Xh %Xh\n", ++ u16_i, pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: found Part Info %u\n", u16_i); ++ break; ++ } ++ } ++ ++ // print msg ++ if(eMMC_CIS_PNI_BLK_CNT== u16_i) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: no valid Partition Info\n"); ++ return eMMC_ST_ERR_NO_PART_INFO; ++ } ++ else{ ++ // calculate FAT capacity ++ eMMC_FATAutoSize(); ++ //eMMC_debug(0,1,"Total Sec: %Xh, FAT Sec: %Xh \n", g_eMMCDrv.u32_SEC_COUNT, g_eMMCDrv.u32_FATSectorCnt); ++ } ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_GET_PART_INFO; ++ return u32_err; ++} ++ ++ ++// data length is 512 bytes ++U32 eMMC_ReadPartitionInfo(U8 *pu8_Data) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_GET_PART_INFO)) ++ { ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadPartitionInfo_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ } ++ ++ memcpy(pu8_Data, gau8_eMMC_PartInfoBuf, 0x200); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#if 0 ++U32 eMMC_WritePartitionInfo(U8 *pu8_Data, U32 u32_ByteCnt) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)pu8_Data; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u16_SecCnt = (u32_ByteCnt>>eMMC_SECTOR_512BYTE_BITS) + (u32_ByteCnt&eMMC_SECTOR_512BYTE_MASK); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC input Part Info keeps %u sectors\n", u16_SecCnt); ++ ++ // search eMMC Partiton Info from pni (pu8_Data) ++ for(u16_i=0; u16_iu16_SpareByteCnt, pPartInfo->u16_BlkCnt); ++ if(1 == pPartInfo->u16_SpareByteCnt) ++ break; ++ pPartInfo = (eMMC_PNI_t*)((U32)pPartInfo+0x200); ++ } ++ if(u16_i == u16_SecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: no valid Part Info for eMMC\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info ChkSum failed for eMMC, %Xh %Xh\n", ++ pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ return eMMC_ST_ERR_PARTITION_CHKSUM; ++ } ++ ++ // write Partition Info in Blk0 and Blk1 (as MBR) ++ for(u16_i=0; u16_iu16_PartCnt; *pu16_PartIdx+=1) ++ { ++ if(u16_PartType == pPartInfo->records[*pu16_PartIdx].u16_PartType) ++ { ++ if(u16_PartCopy == u32_LogicIdx) ++ break; ++ u16_PartCopy++; ++ } ++ } ++ if(*pu16_PartIdx == pPartInfo->u16_PartCnt) ++ { ++ if(0 == u16_PartCopy) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown Partition ID: %Xh\n", u16_PartType); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: no %u Partition ID: %Xh \n", ++ u32_LogicIdx+1, u16_PartType); ++ ++ return eMMC_ST_ERR_NO_PARTITION; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_GetPartitionCapacity (U16 u16_PartType, U32 *pu32_Cap) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(eMMC_PART_FAT == u16_PartType) ++ *pu32_Cap = g_eMMCDrv.u32_FATSectorCnt; ++ else ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ *pu32_Cap = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ReadPartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_R); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_R fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ return u32_err; ++} ++ ++ ++U32 eMMC_WritePartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_WriteData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_W fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_GetDevInfo(eMMC_INFO_t *peMMCInfo_t) ++{ ++ const char *str = "MSTARSEMIUNFDCIS"; ++ ++ memcpy(peMMCInfo_t->au8_Tag, str, 16); ++ peMMCInfo_t->u8_IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(peMMCInfo_t->au8_ID, g_eMMCDrv.au8_ID, g_eMMCDrv.u8_IDByteCnt); ++ peMMCInfo_t->u16_SpareByteCnt = 1; ++ peMMCInfo_t->u16_PageByteCnt = eMMC_SECTOR_512BYTE; ++ peMMCInfo_t->u16_BlkPageCnt = g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u16_BlkCnt = g_eMMCDrv.u32_SEC_COUNT / g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u32_ChkSum = eMMC_ChkSum((U8*)&peMMCInfo_t->u16_SpareByteCnt, 0x32 - 0x24); ++ ++ memcpy(peMMCInfo_t->au8_Vendor, g_eMMCDrv.au8_Vendor, 16); ++ memcpy(peMMCInfo_t->au8_PartNumber, g_eMMCDrv.au8_PartNumber, 16); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ErasePartition(U16 u16_PartType) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_PartLogiIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ u32_PartLogiIdx++; ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ break; ++ } ++ } ++ ++ if(0 == u32_PartLogiIdx) ++ return u32_err; ++ ++ u32_err = eMMC_BootPartitionHandler_E(u16_PartType); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler fail: %Xh\n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++// erase partitions following eMMC_PART_NVRAMBAK ++U32 eMMC_EraseAllPartitions(void) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx=0, u16_PartIdx_tmp; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_NVRAMBAK, ++ u32_PartLogiIdx, &u16_PartIdx_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u16_PartIdx = u16_PartIdx_tmp; ++ u32_PartLogiIdx++; ++ } ++ ++ for(; u16_PartIdx < pPartInfo->u16_PartCnt; u16_PartIdx++) ++ { ++ // skip some partitions can not be erased ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++ if(eMMC_PART_DEV_NODE == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_E2PBAK == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_NVRAMBAK == pPartInfo->records[u16_PartIdx].u16_PartType) ++ continue; ++ #endif ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ return u32_err; ++ } ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseAll(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_EraseBlock(0, g_eMMCDrv.u32_SEC_COUNT-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: fail: %Xh \n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseBlock(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_EraseBlock fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseBlock( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 fail 0, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ // clear Access Boot Partition ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ // write Boot Code ++ u16_SecCnt = (u32_DataByteCnt>>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Boot Data keeps %Xh sectors, ChkSum: %Xh \n", ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, u16_SecCnt<<9)); ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, BOOT_PART_TOTAL_CNT<<9)); ++ ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u16_SecCnt<name, "Mstar-eMMC"); ++ mmc->has_init = 1; ++ mmc->capacity = g_eMMCDrv.u32_SEC_COUNT << 9; ++ ++ ++ eMMC_GetExtCSD((U8*)mmc->ext_csd); ++ ++ mmc->high_capacity = g_eMMCDrv.u8_IfSectorMode; ++ mmc->bus_width = g_eMMCDrv.u8_BUS_WIDTH << 1; ++ ++ switch (g_eMMCDrv.u8_SPEC_VERS) { ++ case 0: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ case 1: ++ mmc->version = MMC_VERSION_1_4; ++ break; ++ case 2: ++ mmc->version = MMC_VERSION_2_2; ++ break; ++ case 3: ++ mmc->version = MMC_VERSION_3; ++ break; ++ case 4: ++ mmc->version = MMC_VERSION_4; ++ break; ++ default: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ } ++ ++ /* divide frequency by 10, since the mults are 10x bigger */ ++ ++ mmc->tran_speed = fbase[( g_eMMCDrv.u8_Tran_Speed & 0x7)] * multipliers[((g_eMMCDrv.u8_Tran_Speed >> 3) & 0xf)]; ++ ++ // reliable write is supported ++ if ((mmc->ext_csd[EXT_CSD_WR_REL_SET] & 0x01) == 1) // reliable write is configured ++ mmc->reliable_write = 2; ++ else if((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[EXT_CSD_WR_REL_PARAM] & 0x1) == 0x1)) ++ { ++ mmc->reliable_write = 1; // reliable write is supported but not configured ++ //printf("[%s]\treliable write is supported\n", __func__); ++ } ++ else ++ { ++ mmc->reliable_write = 0; // reliable write is unsupported ++ //printf("[%s]\treliable write is unsupported\n", __func__); ++ } ++ ++ if ((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[160] & 0x3) == 3)) ++ { ++ mmc->slc_size = ((mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_0] ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_1]) << 8) ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_2]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ mmc->max_slc_size = ((mmc->ext_csd[157] ++ | ((u32)(mmc->ext_csd[158]) << 8) ++ | ((u32)(mmc->ext_csd[159]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ //printf("[%s]\t slc_size = %lld, max_slc_size = %lld\n",__func__, mmc->slc_size, mmc->max_slc_size); ++ } ++ else // slc mode is unsupported ++ { ++ mmc->slc_size = mmc->max_slc_size = 0; ++ //printf("[%s]\t slc mode is unsupported\n",__func__); ++ } ++ ++ ++ { ++ U16 u16_i; ++ for(u16_i = 0; u16_i < 4; u16_i ++) ++ { ++ if(u16_i < 3) ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8 | g_eMMCDrv.au8_CID[u16_i * 4 + 4]; ++ else ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8; ++ } ++ } ++ ++ mmc->read_bl_len = 512; ++ mmc->write_bl_len = 512; ++ mmc->block_dev.lun = 0; ++ mmc->block_dev.type = 0; ++ mmc->block_dev.blksz = 512; ++ mmc->block_dev.lba = g_eMMCDrv.u32_SEC_COUNT; ++ mmc->block_dev.part_type = PART_TYPE_EMMC; ++ sprintf(mmc->block_dev.vendor, "Man %06x Snr %08x", mmc->cid[0] >> 8, ++ (mmc->cid[2] << 8) | (mmc->cid[3] >> 24)); ++ sprintf(mmc->block_dev.product, "%c%c%c%c%c", mmc->cid[0] & 0xff, ++ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, ++ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); ++ sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28, ++ (mmc->cid[2] >> 24) & 0xf); ++ ++// init_part(&mmc->block_dev); ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ struct mmc* mmc = NULL; ++ ++ mmc = malloc(sizeof(struct mmc)); // uboot origianl design, don't free it. ++ if (!mmc) ++ return -ENOMEM; ++ memset(mmc, 0, sizeof(struct mmc)); ++ ++ eMMC_mmc_Init(mmc); ++ ++ mmc_register(mmc); ++ ++ mmc->block_dev.block_read = eMMC_bread; ++ mmc->block_dev.block_write = eMMC_bwrite; ++ mmc->block_dev.block_erase = eMMC_berase; ++ ++ return 0; // uboot origianl design, don't free mmc. ++} ++ ++#endif ++ ++#define eMMC_NOT_READY_MARK ~(('e'<<24)|('M'<<16)|('M'<<8)|'C') ++static U32 sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++ ++static U32 eMMC_Init_Ex(void) ++{ ++ U32 u32_err; ++ ++ //only for Cedric xxxxx ++ /* ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT3); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT3); ++ */ ++ ++ ++ ++ // --------------------------------- ++ u32_err = eMMC_CheckAlignPack(eMMC_CACHE_LINE); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ // --------------------------------- ++ // init platform & FCIE ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ // --------------------------------- ++ u32_err = eMMC_Init_Device(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ sgu32_IfReadyGuard = ~eMMC_NOT_READY_MARK; ++ ++ LABEL_INIT_END: ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ ++ // --------------------------------- ++ // setup ID ++ // use first 10 bytes of CID ++ memcpy(g_eMMCDrv.au8_ID, &g_eMMCDrv.au8_CID[1], eMMC_ID_FROM_CID_BYTE_CNT); ++ g_eMMCDrv.u8_IDByteCnt = eMMC_ID_DEFAULT_BYTE_CNT; ++ // add a 11-th byte for number of GB ++ g_eMMCDrv.au8_ID[eMMC_ID_FROM_CID_BYTE_CNT] = ++ (g_eMMCDrv.u32_SEC_COUNT >> (1+10+10)) + 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "eMMC %uMB\n", g_eMMCDrv.u32_SEC_COUNT>>11); ++ //eMMC_dump_mem(g_eMMCDrv.au8_ID, 0x10); ++ #if 0 ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Err: eMMC Init, no pni, :%Xh\n", u32_err); ++ return eMMC_ST_ERR_NO_CIS; ++ } ++ //eMMC_DumpDriverStatus(); ++ #endif ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Init_Device(void) ++{ ++ U32 u32_err; ++ #if IF_DETECT_eMMC_DDR_TIMING ++ static U8 su8_IfNotBuildDDR=0; ++ #endif ++ U8 u8_eMMC_Identify_retry; ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: Rsp from RAM\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSPFROMRAM_SAVE; ++ #endif ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_INIT_DONE; ++ ++ eMMC_PlatformInit(); ++ // init eMMC device ++ u8_eMMC_Identify_retry = 0; ++EMMC_IDENTIFY: //20130515 ++ u32_err = eMMC_Identify(); ++ if(u32_err) ++ { ++ eMMC_printf("eMMC Err: Identify fail, %X\r\n", u32_err); ++ u8_eMMC_Identify_retry ++; ++ if (u8_eMMC_Identify_retry < 3) ++ goto EMMC_IDENTIFY; ++ else ++ goto LABEL_INIT_END; ++ } ++ ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ ++ // determine device parameters, from CSD ++ u32_err = eMMC_CSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ // setup eMMC device ++ // CMD7 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ #if eMMC_RSP_FROM_RAM ++ u32_err = eMMC_CMD16(eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ #endif ++ ++ // determine device parameters, from Ext_CSD ++ u32_err = eMMC_ExtCSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ // --------------------------------- ++ u32_err = eMMC_SetBusWidth(8, 0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ u32_err = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_INIT_DONE; ++ ++ //eMMC_DumpDriverStatus(); ++ #if IF_DETECT_eMMC_DDR_TIMING //iantest ++ eMMC_printf("eMMC_FCIE_EnableDDRMode\r\n"); ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableDDRMode()) ++ { ++ eMMC_printf("eMMC_ST_SUCCESS != eMMC_FCIE_EnableDDRMode()\r\n"); ++ #if IF_DETECT_eMMC_DDR_TIMING ++ if(0==su8_IfNotBuildDDR) ++ { ++ su8_IfNotBuildDDR = 1; ++ eMMC_FCIE_BuildDDRTimingTable(); ++ } ++ #endif ++ } ++ #else ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_CMD18(0, gau8_eMMC_SectorBuf, 1); // get CMD12 Rsp ++ #endif ++ #endif ++ ++ //eMMC_dump_mem(g_eMMCDrv.au8_AllRsp, 0x100); ++ ++ LABEL_INIT_END: ++ return u32_err; ++} ++ ++ ++U32 eMMC_CheckIfReady(void) ++{ ++ if(eMMC_NOT_READY_MARK != sgu32_IfReadyGuard) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_Init_Ex(); ++} ++ ++void eMMC_ResetReadyFlag(void) ++{ ++ sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseCMDSeq(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 0: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseCMDSeq( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 1, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ return u32_err; ++} ++ ++U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ volatile U16 u16_BlkCnt; ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ ++ if(NULL == pu8_DataBuf) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w data buf is NULL: %Xh \n", (U32)pu8_DataBuf); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD25(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD24(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: W fail: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ return u32_err; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ volatile U16 u16_BlkCnt; ++ U8 u8_IfNotCacheLineAligned=0; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ // first 512 bytes, special handle if not cache line aligned ++ if((U32)pu8_DataBuf & (eMMC_CACHE_LINE-1)) ++ { ++ #if 0 ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING,1, ++ "eMMC Warn: R, buffer not Cache Line aligned: %Xh \n", ++ (U32)pu8_DataBuf); ++ #endif ++ ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.0: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ return u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ u32_BlkAddr += 1; ++ pu8_DataBuf += eMMC_SECTOR_512BYTE; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ ++ // last 512B must be not cache line aligned, ++ // reserved for last eMMC_CMD17_CIFD ++ if(u32_DataByteCnt){ ++ u8_IfNotCacheLineAligned = 1; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ } ++ } ++ ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD18(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD17(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.1: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ // last 512 bytes, special handle if not cache line aligned ++ if(u8_IfNotCacheLineAligned) ++ { ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.2: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ } ++ ++ return u32_err; ++} ++ ++ ++ ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++U32 eMMC_SearchDevNodeStartSector(void) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: init fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_DEV_NODE, 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: GetPartitionIndex fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ g_eMMCDrv.u32_PartDevNodeStartSector = pPartInfo->records[u16_PartIdx].u16_StartBlk; ++ g_eMMCDrv.u32_PartDevNodeStartSector *= pPartInfo->u16_BlkPageCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt *= pPartInfo->u16_BlkPageCnt; ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++ #endif ++ ++int get_NVRAM_start_sector(unsigned int *u32_startsector) ++{ ++ ++ ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ U16 u16_PartIdx; ++ if(eMMC_ST_SUCCESS==eMMC_GetPartitionIndex(eMMC_PART_NVRAM, 0, &u16_PartIdx)) ++ { ++ *u32_startsector = pPartInfo->records[u16_PartIdx].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ printk(KERN_INFO"eMMC_PART_NVRAM start sector: %X\r\n",*u32_startsector); ++ return 0; ++ } ++ ++ ++ return -1; ++} ++ ++//only support p1~p7 for each EMMC device in Linux ++int get_NVRAM_max_part_count(void) ++{ ++ //eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ //return (pPartInfo->u16_PartCnt-1); ++ return 0x0C; ++} ++ ++ ++int get_DEVNODE_start_sector(unsigned int *u32_startsector) ++{ ++ u32 u32_err; ++ if(0 == g_eMMCDrv.u32_PartDevNodeStartSector){ ++ u32_err = eMMC_SearchDevNodeStartSector(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ printk(KERN_ERR"** Err, %s **\n", __func__); ++ return (-1); ++ } ++ } ++ ++ *u32_startsector=g_eMMCDrv.u32_PartDevNodeStartSector; ++ ++ ++ return 0; ++ ++} ++ ++ ++ ++ ++ ++#endif ++ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/src/common/cmd_mstar_emmc_bootloader.txt b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/cmd_mstar_emmc_bootloader.txt +new file mode 100644 +index 00000000..bee76431 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/cmd_mstar_emmc_bootloader.txt +@@ -0,0 +1,12352 @@ ++0x27,0x37,0x91,0x35,0x67,0x32,0x70,0x5F, ++0x62,0x6F,0x6F,0x74,0x6C,0x6F,0x61,0x64, ++0x65,0x72,0x00,0x00,0x4B,0x9A,0x08,0x75, ++0x00,0x10,0x00,0x20,0xE8,0xDA,0x00,0x00, ++0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00, ++0x0F,0x0A,0xF0,0x4F,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x0E,0x00,0x00,0xEA,0x05,0x00,0x00,0xEA, ++0x05,0x00,0x00,0xEA,0x05,0x00,0x00,0xEA, ++0x05,0x00,0x00,0xEA,0x00,0x00,0x00,0x00, ++0x04,0x00,0x00,0xEA,0x05,0x00,0x00,0xEA, ++0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, ++0xFE,0xFF,0xFF,0xEA,0xFE,0xFF,0xFF,0xEA, ++0xC4,0xD0,0x9F,0xE5,0x0D,0xF0,0xA0,0xE1, ++0xC0,0x80,0x9F,0xE5,0x08,0xF0,0xA0,0xE1, ++0xBC,0x40,0x9F,0xE5,0x6C,0x40,0x84,0xE2, ++0x04,0xF0,0xA0,0xE1,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0x00,0xF0,0x20,0xE3, ++0x00,0xF0,0x20,0xE3,0xB0,0x0F,0x10,0xEE, ++0x03,0x00,0x10,0xE2,0x00,0x00,0x50,0xE3, ++0x78,0x00,0x9F,0x05,0x10,0xFF,0x2F,0x01, ++0x74,0x10,0x9F,0xE5,0xC2,0x20,0xA0,0xE3, ++0x20,0x00,0x81,0xE5,0x24,0x20,0x81,0xE5, ++0x00,0xF0,0x20,0xE3,0xFD,0xFF,0xFF,0xEA, ++0x5C,0x10,0x9F,0xE5,0xA9,0x22,0x00,0xE3, ++0x00,0x20,0x81,0xE4,0x54,0x10,0x9F,0xE5, ++0xD1,0x00,0xA0,0xE3,0x00,0xF0,0x21,0xE1, ++0x00,0xD0,0x41,0xE2,0xD2,0x00,0xA0,0xE3, ++0x00,0xF0,0x21,0xE1,0x00,0xD0,0x41,0xE2, ++0xDB,0x00,0xA0,0xE3,0x00,0xF0,0x21,0xE1, ++0x00,0xD0,0x41,0xE2,0xD3,0x00,0xA0,0xE3, ++0x00,0xF0,0x21,0xE1,0x20,0xD0,0x41,0xE2, ++0x1C,0x10,0x9F,0xE5,0xB7,0x20,0xA0,0xE3, ++0x00,0x20,0x81,0xE4,0x06,0x00,0x00,0xEB, ++0xFE,0xFF,0xFF,0xEA,0xEC,0xE8,0x03,0x20, ++0xB4,0xE8,0x03,0x20,0x00,0x10,0x00,0x20, ++0xA8,0x10,0x00,0x20,0x00,0x3C,0x30,0x25, ++0x94,0xE4,0x02,0x20,0x00,0x00,0x00,0xEB, ++0xED,0xC1,0x00,0xEB,0x2C,0x00,0x8F,0xE2, ++0x00,0x0C,0x90,0xE8,0x00,0xA0,0x8A,0xE0, ++0x00,0xB0,0x8B,0xE0,0x01,0x70,0x4A,0xE2, ++0x0B,0x00,0x5A,0xE1,0x00,0x00,0x00,0x1A, ++0xE5,0xC1,0x00,0xEB,0x0F,0x00,0xBA,0xE8, ++0x18,0xE0,0x4F,0xE2,0x01,0x00,0x13,0xE3, ++0x03,0xF0,0x47,0x10,0x13,0xFF,0x2F,0xE1, ++0xB8,0x00,0x00,0x00,0x08,0x01,0x00,0x00, ++0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0x8A,0x18,0x03,0x78,0x01,0x30,0x5C,0x07, ++0x64,0x0F,0x01,0xD1,0x04,0x78,0x01,0x30, ++0x1D,0x11,0x01,0xD1,0x05,0x78,0x01,0x30, ++0x01,0x3C,0x05,0xD0,0x06,0x78,0x01,0x30, ++0x0E,0x70,0x01,0x31,0x01,0x3C,0xF9,0xD1, ++0x1E,0x07,0x06,0xD4,0x2E,0x1C,0x0E,0xD0, ++0x01,0x3E,0x8C,0x55,0xFC,0xD1,0x49,0x19, ++0x09,0xE0,0x04,0x78,0x01,0x30,0x0C,0x1B, ++0x01,0x35,0x26,0x78,0x01,0x34,0x0E,0x70, ++0x01,0x31,0x01,0x3D,0xF9,0xD5,0x91,0x42, ++0xD7,0xD3,0x70,0x47,0x10,0x20,0x52,0xE2, ++0x78,0x00,0xB0,0x28,0x78,0x00,0xA1,0x28, ++0xFB,0xFF,0xFF,0x8A,0x82,0x2E,0xB0,0xE1, ++0x30,0x00,0xB0,0x28,0x30,0x00,0xA1,0x28, ++0x00,0x40,0x90,0x45,0x00,0x40,0x81,0x45, ++0x1E,0xFF,0x2F,0xE1,0x00,0x30,0xB0,0xE3, ++0x00,0x40,0xB0,0xE3,0x00,0x50,0xB0,0xE3, ++0x00,0x60,0xB0,0xE3,0x10,0x20,0x52,0xE2, ++0x78,0x00,0xA1,0x28,0xFC,0xFF,0xFF,0x8A, ++0x82,0x2E,0xB0,0xE1,0x30,0x00,0xA1,0x28, ++0x00,0x30,0x81,0x45,0x1E,0xFF,0x2F,0xE1, ++0x58,0x12,0x00,0x20,0x00,0x00,0x02,0x20, ++0x00,0x10,0x00,0x00,0x58,0x11,0x00,0x20, ++0x7C,0x12,0x00,0x20,0x00,0x10,0x02,0x20, ++0x00,0x40,0x00,0x00,0x58,0x11,0x00,0x20, ++0x00,0x13,0x00,0x20,0x94,0x04,0x03,0x20, ++0xF4,0x00,0x00,0x00,0xB4,0x11,0x00,0x20, ++0xF4,0x13,0x00,0x20,0xEC,0x17,0x03,0x20, ++0xF4,0xD6,0x00,0x00,0xB4,0x11,0x00,0x20, ++0xF4,0x13,0x00,0x20,0x88,0x05,0x03,0x20, ++0x64,0x12,0x00,0x00,0xDC,0x11,0x00,0x20, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0x10,0x00,0x00,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0xFF,0x01,0xFF, ++0x01,0xFF,0x01,0xFF,0x01,0x40,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x01,0x20,0x00,0x80,0x01,0x20, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xBC,0xB2,0xB2,0x9A,0x03,0x05,0x07,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x12,0x01,0x10,0x01,0x00,0x00,0x00,0x40, ++0x20,0x1B,0x00,0x03,0x00,0x01,0x00,0x00, ++0x00,0x01,0x0A,0x06,0x00,0x02,0x00,0x00, ++0x00,0x40,0x01,0x00,0x09,0x07,0x20,0x00, ++0x01,0x01,0x00,0xC0,0x00,0x09,0x04,0x00, ++0x00,0x02,0x08,0x06,0x50,0x00,0x07,0x05, ++0x81,0x02,0x40,0x00,0x00,0x07,0x05,0x02, ++0x02,0x40,0x00,0x00,0x09,0x02,0x20,0x00, ++0x01,0x01,0x00,0xC0,0x00,0x09,0x04,0x00, ++0x00,0x02,0x08,0x06,0x50,0x00,0x07,0x05, ++0x81,0x02,0x40,0x00,0x00,0x07,0x05,0x02, ++0x02,0x40,0x00,0x00,0x04,0x03,0x09,0x04, ++0x28,0x03,0x4D,0x00,0x61,0x00,0x73,0x00, ++0x73,0x00,0x20,0x00,0x53,0x00,0x74,0x00, ++0x6F,0x00,0x72,0x00,0x61,0x00,0x67,0x00, ++0x65,0x00,0x20,0x00,0x44,0x00,0x65,0x00, ++0x76,0x00,0x69,0x00,0x63,0x00,0x65,0x00, ++0x12,0x03,0x42,0x00,0x69,0x00,0x67,0x00, ++0x42,0x00,0x6C,0x00,0x75,0x00,0x65,0x00, ++0x34,0x00,0x00,0x00,0x30,0xEC,0x03,0x20, ++0x5A,0xA5,0x00,0x00,0x89,0x12,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x6E,0x00,0x51,0xE3, ++0x75,0x2F,0x00,0x0A,0x70,0x00,0x51,0xE3, ++0xF1,0x2C,0x00,0x0A,0x66,0x00,0x51,0xE3, ++0xC4,0x34,0x00,0x0A,0x65,0x00,0x51,0xE3, ++0xC2,0x34,0x00,0x0A,0x67,0x00,0x51,0xE3, ++0xC0,0x34,0x00,0x0A,0x61,0x00,0x51,0xE3, ++0x00,0x00,0xA0,0xE1,0x00,0x30,0x90,0xE5, ++0x23,0x34,0xB0,0xE1,0x80,0x10,0x81,0x23, ++0x69,0x00,0x51,0xE3,0x49,0x2F,0x00,0x0A, ++0x64,0x00,0x51,0xE3,0x47,0x2F,0x00,0x0A, ++0x75,0x00,0x51,0xE3,0x45,0x2F,0x00,0x0A, ++0x6F,0x00,0x51,0xE3,0xD3,0x2F,0x00,0x0A, ++0x78,0x00,0x51,0xE3,0x6A,0x34,0x00,0x0A, ++0xE9,0x00,0x51,0xE3,0xAA,0x2F,0x00,0x0A, ++0xE4,0x00,0x51,0xE3,0xA8,0x2F,0x00,0x0A, ++0xF5,0x00,0x51,0xE3,0xA6,0x2F,0x00,0x0A, ++0xEF,0x00,0x51,0xE3,0x64,0x34,0x00,0x0A, ++0xF8,0x00,0x51,0xE3,0x64,0x34,0x00,0x0A, ++0x00,0x30,0x90,0xE5,0xA3,0x33,0xB0,0xE1, ++0x80,0x10,0x81,0x23,0x63,0x00,0x51,0xE3, ++0x51,0x31,0x00,0x0A,0x73,0x00,0x51,0xE3, ++0x5F,0x34,0x00,0x0A,0xE3,0x00,0x51,0xE3, ++0x5B,0x31,0x00,0x0A,0xF3,0x00,0x51,0xE3, ++0x5D,0x34,0x00,0x0A,0x00,0x00,0xB0,0xE3, ++0x1E,0xFF,0x2F,0xE1,0x1F,0xB5,0x0D,0xF0, ++0x2E,0xE9,0x0C,0xF0,0x16,0xE8,0x04,0x00, ++0x00,0x20,0x00,0x21,0x0D,0xF0,0xDE,0xE8, ++0x40,0x1C,0x60,0x60,0x00,0x20,0x00,0x21, ++0x0D,0xF0,0xFC,0xE8,0xE0,0x60,0x1F,0xBD, ++0x10,0xB5,0x10,0xBD,0x7E,0x31,0x00,0xEB, ++0x02,0x10,0xA0,0xE1,0xF2,0xFF,0xFF,0xFA, ++0x1C,0xC0,0x9F,0xE5,0x0F,0xC0,0x8C,0xE0, ++0x01,0x00,0x1C,0xE3,0x0D,0xE0,0x8F,0x12, ++0x0F,0xE0,0xA0,0x01,0x1C,0xFF,0x2F,0xE1, ++0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0x0C,0xF0,0xBC,0xFB,0xA9,0x00,0x00,0x00, ++0xF0,0xFF,0xFF,0xFA,0xE0,0x31,0x00,0xFA, ++0x2D,0xE9,0xF0,0x41,0x04,0x00,0x0F,0x46, ++0x4F,0xF0,0x00,0x05,0x37,0xD0,0xA1,0x20, ++0x30,0x4E,0x30,0x60,0x2F,0xE0,0x75,0x60, ++0x38,0x46,0x0B,0xF0,0xF7,0xFA,0x02,0x46, ++0x39,0x46,0x20,0x46,0x0B,0xF0,0xA8,0xFA, ++0x18,0xBB,0xA3,0x20,0xC6,0xE9,0x00,0x04, ++0x38,0x46,0x0B,0xF0,0xEB,0xFA,0xB0,0x60, ++0x38,0x46,0x0B,0xF0,0xE7,0xFA,0x20,0x44, ++0x40,0x1C,0xF0,0x60,0x38,0x46,0x0B,0xF0, ++0xE1,0xFA,0x20,0x44,0x10,0x22,0x40,0x1C, ++0x00,0x21,0x0B,0xF0,0x57,0xFA,0x30,0x61, ++0xA4,0x20,0x30,0x60,0x38,0x46,0x0B,0xF0, ++0xD5,0xFA,0x20,0x44,0x10,0x22,0xBD,0xE8, ++0xF0,0x41,0x40,0x1C,0x00,0x21,0x0B,0xF0, ++0x49,0xBA,0x6D,0x1C,0x64,0x1C,0x20,0x78, ++0x08,0xB1,0xFF,0x2D,0xCB,0xDD,0x00,0x20, ++0xBD,0xE8,0xF0,0x81,0x70,0xB5,0xAB,0x20, ++0x12,0x4C,0x20,0x60,0x00,0xF0,0xAF,0xF8, ++0x15,0x48,0x11,0xA1,0xFF,0xF7,0xB4,0xFF, ++0x05,0x46,0x00,0xF0,0x1A,0xFC,0x12,0x49, ++0x2A,0x46,0x12,0xA0,0x00,0xF0,0x06,0xFC, ++0x16,0xA2,0x19,0xA1,0x1B,0xA0,0x00,0xF0, ++0x01,0xFC,0x0D,0x48,0x1E,0xA1,0xE0,0x60, ++0xFF,0xF7,0xA2,0xFF,0x0A,0x49,0xC2,0xB2, ++0x1E,0xA0,0x00,0xF0,0xF7,0xFB,0x25,0xA0, ++0x00,0xF0,0xF4,0xFB,0x00,0xF0,0xBA,0xFD, ++0xFE,0xE7,0x00,0x00,0x00,0x3C,0x30,0x25, ++0x64,0x65,0x62,0x75,0x67,0x5F,0x6D,0x65, ++0x6D,0x5F,0x74,0x61,0x69,0x6C,0x00,0x00, ++0x00,0xD0,0x02,0x20,0x52,0x4F,0x4D,0x20, ++0x70,0x61,0x72,0x61,0x6D,0x3A,0x25,0x78, ++0x2C,0x20,0x76,0x3D,0x30,0x78,0x25,0x78, ++0x0A,0x00,0x00,0x00,0x32,0x30,0x3A,0x35, ++0x34,0x3A,0x35,0x33,0x00,0x00,0x00,0x00, ++0x41,0x70,0x72,0x20,0x31,0x30,0x20,0x32, ++0x30,0x31,0x32,0x00,0x42,0x75,0x69,0x6C, ++0x74,0x20,0x6F,0x6E,0x20,0x25,0x73,0x20, ++0x61,0x74,0x20,0x25,0x73,0x0A,0x00,0x00, ++0x62,0x6F,0x6F,0x74,0x6D,0x6F,0x64,0x65, ++0x00,0x00,0x00,0x00,0x62,0x6F,0x6F,0x74, ++0x20,0x70,0x61,0x72,0x61,0x6D,0x3A,0x25, ++0x78,0x2C,0x20,0x62,0x6F,0x6F,0x74,0x6D, ++0x6F,0x64,0x65,0x3D,0x30,0x78,0x25,0x78, ++0x0A,0x00,0x00,0x00,0x2B,0x62,0x6F,0x6F, ++0x74,0x6C,0x6F,0x61,0x64,0x65,0x72,0x0A, ++0x00,0x00,0x00,0x00,0xD8,0x48,0x00,0x88, ++0xD8,0x49,0x08,0x60,0x70,0x47,0xD8,0x48, ++0x00,0x21,0x81,0x64,0x49,0x1E,0x01,0x64, ++0x82,0x21,0x81,0x64,0x70,0x47,0xD4,0x4A, ++0x01,0x21,0xD1,0x60,0x01,0xF0,0x16,0xB8, ++0x10,0xB5,0xC0,0x03,0x4F,0xF4,0x7A,0x71, ++0x0C,0xF0,0x02,0xEB,0x00,0xB9,0x01,0x20, ++0xCD,0x4C,0x00,0x21,0xA1,0x60,0x20,0x60, ++0x03,0x46,0xCC,0x4A,0x08,0x46,0x01,0xF0, ++0x63,0xF8,0x01,0x22,0x00,0x20,0x11,0x46, ++0x01,0xF0,0x6D,0xF8,0xA0,0x68,0x40,0xF0, ++0xE2,0x00,0xA0,0x60,0x10,0xBD,0xC6,0x49, ++0x08,0x88,0x20,0xF4,0x40,0x70,0x08,0x80, ++0x70,0x47,0xC4,0x49,0x08,0x68,0x40,0xF4, ++0x00,0x40,0x08,0x60,0xC0,0x49,0x7C,0x39, ++0x08,0x68,0x20,0xF4,0x60,0x40,0x40,0xF4, ++0xC0,0x40,0x08,0x60,0x70,0x47,0x10,0xB5, ++0xFF,0xF7,0xE9,0xFF,0xFF,0xF7,0xBA,0xFF, ++0x00,0xF0,0x38,0xFA,0xB5,0x49,0x02,0x28, ++0x01,0xD1,0xB9,0x48,0x07,0xE0,0x00,0xF0, ++0x31,0xFA,0x01,0x28,0x01,0xD1,0xB7,0x48, ++0x01,0xE0,0x4F,0xF4,0x00,0x40,0xAE,0x4A, ++0xC8,0x60,0x70,0x32,0x50,0x6F,0x20,0xF0, ++0x40,0x00,0x50,0x67,0xFF,0xF7,0xA7,0xFF, ++0xAD,0x48,0x40,0x38,0x01,0x68,0x21,0xF4, ++0x60,0x51,0x41,0xF4,0xC0,0x51,0x01,0x60, ++0x41,0x68,0x41,0xF0,0x01,0x01,0x41,0x60, ++0x90,0x8F,0x20,0xF4,0x10,0x40,0x90,0x87, ++0x00,0x20,0xA2,0xF8,0x0C,0x0D,0x52,0xF8, ++0x2C,0x0D,0x51,0x68,0xA6,0x4A,0x09,0x04, ++0xC0,0xEA,0x01,0x01,0x00,0x20,0x52,0xF8, ++0x20,0x30,0x41,0xF8,0x20,0x30,0x40,0x1C, ++0xFF,0x28,0xF8,0xD9,0x00,0x20,0xA1,0x49, ++0x08,0x62,0x48,0x62,0x08,0x61,0x48,0x61, ++0x88,0x60,0xC8,0x60,0x40,0x1E,0x88,0x61, ++0xC8,0x61,0x08,0x60,0x48,0x60,0x88,0x64, ++0xC8,0x64,0x40,0xF2,0x01,0x10,0x08,0x67, ++0x00,0x24,0x00,0x21,0x20,0x46,0x00,0xF0, ++0xAB,0xFF,0x64,0x1C,0xA4,0xB2,0x40,0x2C, ++0xF7,0xD3,0xBD,0xE8,0x10,0x40,0x0C,0xF0, ++0x35,0xBF,0x8A,0x4A,0xC0,0x43,0xF0,0xB5, ++0x10,0x32,0xC0,0xF3,0x07,0x21,0x16,0x68, ++0x4F,0xF0,0xFF,0x3C,0x55,0x68,0xC0,0xB2, ++0x0E,0x40,0x05,0x40,0x00,0x22,0x13,0x46, ++0x10,0x46,0x14,0x46,0x11,0x46,0x25,0xFA, ++0x01,0xF7,0xFF,0x07,0x01,0xD0,0x52,0x1C, ++0x08,0x46,0x26,0xFA,0x01,0xF7,0xFF,0x07, ++0x01,0xD0,0x5B,0x1C,0x0C,0x46,0x49,0x1C, ++0x08,0x29,0xF0,0xD3,0x01,0x2A,0x01,0xD1, ++0x01,0x2B,0x01,0xD0,0x60,0x46,0xF0,0xBD, ++0x04,0xF0,0x07,0x01,0x61,0xF3,0xDF,0x00, ++0xF0,0xBD,0x7D,0x49,0x2A,0x20,0x08,0x80, ++0x7C,0x48,0xB0,0xF8,0x60,0x02,0x00,0xF0, ++0x3F,0x00,0x70,0x47,0x78,0x49,0x28,0x20, ++0x08,0x80,0x79,0x48,0x01,0x68,0x6F,0xF3, ++0x0C,0x01,0x01,0x60,0x41,0x68,0x89,0xB2, ++0x41,0x60,0xA0,0xF5,0xC1,0x60,0x70,0x47, ++0x71,0x49,0x2B,0x20,0x2D,0xE9,0xF0,0x41, ++0x08,0x80,0x1E,0x20,0x00,0xF0,0xB8,0xF9, ++0x70,0x4F,0xB7,0xF8,0x04,0x66,0xFF,0xF7, ++0xDC,0xFF,0x04,0x46,0x61,0x48,0x4F,0xF4, ++0x7A,0x71,0xC0,0x68,0x0C,0xF0,0x24,0xEA, ++0x4F,0xF4,0xFA,0x61,0x00,0xFB,0x01,0xF5, ++0x30,0x46,0xFF,0xF7,0xA2,0xFF,0x02,0x46, ++0x21,0x46,0x67,0xA0,0x00,0xF0,0xA2,0xFA, ++0x00,0xF0,0x86,0xF9,0x05,0x44,0x30,0x46, ++0xFF,0xF7,0x97,0xFF,0xA0,0x42,0x1A,0xD1, ++0x3F,0x2C,0x18,0xD0,0x0D,0xE0,0xB7,0xF8, ++0x04,0x66,0x30,0x46,0xFF,0xF7,0x8D,0xFF, ++0xA0,0x42,0x06,0xD0,0x31,0x46,0x63,0xA0, ++0x00,0xF0,0x8C,0xFA,0x00,0x20,0xBD,0xE8, ++0xF0,0x81,0x00,0xF0,0x6D,0xF9,0xA8,0x42, ++0xED,0xD3,0x31,0x46,0x66,0xA0,0x00,0xF0, ++0x81,0xFA,0x01,0x20,0xF3,0xE7,0x31,0x46, ++0x6A,0xA0,0xED,0xE7,0x72,0x48,0x0E,0xB5, ++0x03,0x68,0x72,0x48,0x02,0x68,0x72,0x48, ++0x01,0x68,0x72,0x48,0x8D,0xE8,0x0E,0x00, ++0x4F,0xF4,0x80,0x71,0x03,0x68,0x70,0x4A, ++0x70,0x48,0x0A,0xF0,0x4D,0xFF,0x6F,0x48, ++0x0E,0xBD,0x2D,0xE9,0xF0,0x5F,0x00,0x24, ++0xDF,0xF8,0xB4,0x81,0x52,0x21,0x05,0x46, ++0xA8,0xF8,0x00,0x1C,0x01,0x46,0x6B,0xA0, ++0x00,0xF0,0x5C,0xFA,0x35,0x48,0x4F,0xF4, ++0x7A,0x71,0xC0,0x68,0x0C,0xF0,0xCC,0xE9, ++0x00,0xFB,0x05,0xF1,0x00,0xF0,0x38,0xF9, ++0x46,0x18,0x03,0xF0,0x50,0xFB,0xDF,0xF8, ++0x74,0xB1,0x4F,0xF4,0x72,0x4A,0xDF,0xF8, ++0xA4,0x91,0x33,0xE0,0xDB,0xF8,0x00,0x10, ++0x11,0xB1,0x59,0x48,0x00,0x68,0x88,0x47, ++0x20,0x04,0x04,0xF1,0x01,0x04,0x00,0x0C, ++0x02,0xD1,0x63,0xA0,0x00,0xF0,0x3A,0xFA, ++0x03,0xF0,0x44,0xFB,0x00,0x28,0x21,0xD0, ++0x60,0xA0,0x00,0xF0,0x33,0xFA,0x01,0xF0, ++0x0B,0xFD,0x67,0x48,0x49,0x46,0xD0,0xE9, ++0x06,0x75,0x66,0xA0,0x3A,0x46,0x2B,0x46, ++0x00,0xF0,0x28,0xFA,0x55,0x45,0x50,0x46, ++0x00,0xD9,0x05,0x46,0x31,0x20,0xA8,0xF8, ++0x00,0x0C,0x2A,0x46,0x49,0x46,0x38,0x46, ++0x0B,0xF0,0xF2,0xE8,0x02,0x20,0xFF,0xF7, ++0x9D,0xFF,0x39,0x46,0x64,0xA0,0x00,0xF0, ++0x15,0xFA,0xB8,0x47,0x00,0xF0,0xF8,0xF8, ++0xB0,0x42,0xC7,0xD3,0xBD,0xE8,0xF0,0x5F, ++0x67,0xA0,0x00,0xF0,0x0B,0xBA,0x0C,0x48, ++0x00,0x88,0x00,0xF0,0x0F,0x00,0x0C,0x28, ++0x0F,0xD2,0xDF,0xE8,0x00,0xF0,0x06,0x0A, ++0x06,0x08,0x0A,0x0C,0x08,0x0A,0x0C,0x06, ++0x0A,0x0C,0x01,0x20,0x70,0x47,0x02,0x20, ++0x70,0x47,0x03,0x20,0x70,0x47,0x04,0x20, ++0x70,0x47,0xFF,0x20,0x70,0x47,0x00,0x00, ++0x90,0x71,0x00,0x25,0x94,0x04,0x03,0x20, ++0x00,0x20,0x30,0x25,0x97,0x1A,0x03,0x20, ++0xC0,0x0B,0x02,0x25,0x14,0x3E,0x00,0x25, ++0x00,0xF0,0x49,0x02,0x80,0xBA,0x8C,0x01, ++0x00,0x10,0x00,0x20,0x14,0x0C,0x30,0x25, ++0x00,0x3C,0x30,0x25,0x00,0x20,0x00,0x25, ++0x08,0x06,0x30,0x25,0x00,0x00,0x30,0x25, ++0x50,0x72,0x65,0x73,0x73,0x65,0x64,0x5F, ++0x6B,0x65,0x79,0x28,0x25,0x78,0x29,0x2C, ++0x65,0x46,0x75,0x73,0x65,0x28,0x25,0x78, ++0x29,0x0A,0x00,0x00,0x72,0x65,0x6C,0x65, ++0x61,0x73,0x65,0x64,0x7C,0x50,0x72,0x65, ++0x73,0x73,0x65,0x64,0x5F,0x74,0x68,0x65, ++0x5F,0x77,0x72,0x6F,0x6E,0x67,0x5F,0x6B, ++0x65,0x79,0x28,0x25,0x78,0x29,0x0A,0x00, ++0x64,0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64, ++0x5F,0x4B,0x65,0x79,0x5F,0x70,0x72,0x65, ++0x73,0x73,0x65,0x64,0x28,0x25,0x78,0x29, ++0x0A,0x00,0x00,0x00,0x6E,0x6F,0x5F,0x6B, ++0x65,0x79,0x7C,0x50,0x72,0x65,0x73,0x73, ++0x65,0x64,0x5F,0x74,0x68,0x65,0x5F,0x77, ++0x72,0x6F,0x6E,0x67,0x5F,0x6B,0x65,0x79, ++0x28,0x25,0x78,0x29,0x0A,0x00,0x00,0x00, ++0xBC,0x04,0x03,0x20,0x80,0xD4,0x02,0x20, ++0x74,0xD4,0x02,0x20,0x78,0xD4,0x02,0x20, ++0x1C,0xEB,0x03,0x20,0x00,0xD0,0x02,0x20, ++0x00,0x30,0x30,0x25,0x73,0x79,0x73,0x5F, ++0x77,0x61,0x69,0x74,0x5F,0x62,0x6F,0x6F, ++0x74,0x73,0x74,0x72,0x61,0x70,0x28,0x25, ++0x64,0x29,0x6D,0x73,0x5B,0x49,0x4E,0x5D, ++0x0A,0x00,0x00,0x00,0x00,0x42,0x04,0x20, ++0x2E,0x00,0x00,0x00,0x0A,0x64,0x77,0x6C, ++0x64,0x20,0x62,0x6F,0x6F,0x74,0x73,0x74, ++0x72,0x61,0x70,0x20,0x66,0x72,0x6F,0x6D, ++0x20,0x55,0x53,0x42,0x2F,0x55,0x41,0x52, ++0x54,0x5B,0x4F,0x4B,0x5D,0x0A,0x00,0x00, ++0x00,0x40,0x04,0x20,0x20,0x63,0x6F,0x70, ++0x79,0x5F,0x44,0x57,0x4C,0x44,0x5F,0x52, ++0x41,0x4D,0x44,0x43,0x4F,0x44,0x45,0x28, ++0x25,0x6C,0x78,0x29,0x28,0x25,0x6C,0x78, ++0x29,0x28,0x25,0x6C,0x78,0x29,0x0A,0x00, ++0x46,0x69,0x6E,0x69,0x73,0x68,0x20,0x44, ++0x6F,0x77,0x6E,0x6C,0x6F,0x61,0x64,0x2C, ++0x20,0x6A,0x75,0x6D,0x70,0x28,0x30,0x78, ++0x25,0x6C,0x78,0x29,0x0A,0x0A,0x00,0x00, ++0x73,0x79,0x73,0x57,0x61,0x69,0x74,0x42, ++0x6F,0x6F,0x74,0x73,0x74,0x72,0x61,0x70, ++0x28,0x29,0x5F,0x74,0x69,0x6D,0x65,0x6F, ++0x75,0x74,0x21,0x0A,0x00,0x00,0x00,0x00, ++0x03,0x48,0x00,0x68,0x40,0x06,0x01,0xD5, ++0x01,0x20,0x70,0x47,0x02,0x20,0x70,0x47, ++0x94,0x04,0x03,0x20,0x03,0x48,0x00,0x68, ++0xC0,0x06,0x01,0xD5,0x02,0x20,0x70,0x47, ++0x01,0x20,0x70,0x47,0x94,0x04,0x03,0x20, ++0x01,0x48,0x40,0x6C,0xC0,0x43,0x70,0x47, ++0x00,0x20,0x30,0x25,0x70,0xB5,0x06,0x46, ++0xFF,0xF7,0xF6,0xFF,0x05,0x4C,0x05,0x46, ++0x4F,0xF4,0x7A,0x71,0x60,0x60,0xE0,0x68, ++0x0C,0xF0,0x7E,0xE8,0x06,0xFB,0x00,0x50, ++0xA0,0x60,0x70,0xBD,0x94,0x04,0x03,0x20, ++0x10,0xB5,0x04,0x46,0x08,0x48,0x4F,0xF4, ++0x7A,0x71,0xC0,0x68,0x0C,0xF0,0x70,0xE8, ++0x00,0xFB,0x04,0xF2,0xFF,0xF7,0xDC,0xFF, ++0x01,0x46,0xFF,0xF7,0xD9,0xFF,0x40,0x1A, ++0x90,0x42,0xFA,0xD3,0x10,0xBD,0x00,0x00, ++0x94,0x04,0x03,0x20,0x10,0xB5,0x04,0x46, ++0x08,0x48,0x07,0x49,0xC0,0x68,0x0C,0xF0, ++0x5C,0xE8,0x00,0xFB,0x04,0xF2,0xFF,0xF7, ++0xC7,0xFF,0x01,0x46,0xFF,0xF7,0xC4,0xFF, ++0x40,0x1A,0x90,0x42,0xFA,0xD3,0x10,0xBD, ++0x40,0x42,0x0F,0x00,0x94,0x04,0x03,0x20, ++0x04,0x48,0x00,0x68,0x00,0xF0,0x0F,0x00, ++0x08,0x28,0x01,0xD1,0x01,0x20,0x70,0x47, ++0x00,0x20,0x70,0x47,0x94,0x04,0x03,0x20, ++0x10,0xB5,0x04,0x46,0x09,0xB9,0x01,0x20, ++0x10,0xBD,0x49,0x1E,0x20,0x46,0xFF,0xF7, ++0xF7,0xFF,0x60,0x43,0x10,0xBD,0x09,0x28, ++0x01,0xD8,0x30,0x30,0x04,0xE0,0xA0,0xF1, ++0x0A,0x01,0x05,0x29,0x01,0xD8,0x37,0x30, ++0xC0,0xB2,0x70,0x47,0x2D,0xE9,0xF0,0x5F, ++0x01,0x25,0xDF,0xF8,0xA4,0xA0,0x05,0x24, ++0x06,0x46,0x4F,0xF4,0x7A,0x7B,0x4F,0xF0, ++0x00,0x09,0x0A,0x20,0x21,0x46,0xFF,0xF7, ++0xDB,0xFF,0x4F,0xEA,0xE0,0x78,0x07,0x46, ++0xA6,0xFB,0x0B,0x01,0xDA,0xF8,0x00,0x20, ++0x4B,0x46,0x0A,0xF0,0xEC,0xEB,0x43,0x46, ++0x3A,0x46,0x0A,0xF0,0xE8,0xEB,0x0A,0x21, ++0x0B,0xF0,0xCE,0xE8,0x01,0xB9,0x45,0xB9, ++0xC8,0xB2,0xFF,0xF7,0xD0,0xFF,0x19,0x4A, ++0x00,0x25,0x51,0x68,0x01,0xF8,0x01,0x0B, ++0x51,0x60,0x64,0x1E,0xDD,0xD5,0x2E,0x21, ++0x14,0x4F,0x01,0x24,0x5D,0x46,0x78,0x68, ++0x00,0xF8,0x01,0x1B,0x78,0x60,0x0A,0x20, ++0x21,0x46,0xFF,0xF7,0xB1,0xFF,0xC1,0x17, ++0x4B,0x46,0xA6,0xFB,0x00,0x20,0x06,0xFB, ++0x01,0x01,0xA5,0xFB,0x02,0x02,0x05,0xFB, ++0x01,0x21,0xDA,0xF8,0x00,0x20,0x0A,0xF0, ++0xBE,0xEB,0x0A,0x21,0x0B,0xF0,0xA4,0xE8, ++0xC8,0xB2,0xFF,0xF7,0xA8,0xFF,0x79,0x68, ++0x64,0x1C,0x02,0x2C,0x01,0xF8,0x01,0x0B, ++0x79,0x60,0xE0,0xDD,0xBD,0xE8,0xF0,0x9F, ++0xA0,0x04,0x03,0x20,0xB8,0x04,0x03,0x20, ++0x10,0xB5,0x3C,0x21,0x07,0x4C,0x60,0x68, ++0x00,0xF8,0x01,0x1B,0x60,0x60,0x06,0x48, ++0x40,0x6C,0xC0,0x43,0xFF,0xF7,0x9A,0xFF, ++0x60,0x68,0x3E,0x21,0x00,0xF8,0x01,0x1B, ++0x60,0x60,0x10,0xBD,0xB8,0x04,0x03,0x20, ++0x00,0x20,0x30,0x25,0x2D,0xE9,0xF0,0x41, ++0x07,0x46,0x30,0x4E,0x0D,0x46,0x30,0x4A, ++0x70,0x68,0x02,0xF1,0x20,0x04,0x01,0x44, ++0x91,0x42,0x0F,0xD9,0x00,0x21,0x02,0x46, ++0x01,0xE0,0x49,0x1C,0x52,0x1C,0xA2,0x42, ++0xFB,0xD3,0x00,0x29,0x02,0xDD,0x20,0x22, ++0x0A,0xF0,0xFA,0xEE,0x27,0x48,0x70,0x60, ++0x01,0x20,0x30,0x70,0xFF,0xF7,0xCC,0xFF, ++0x00,0x20,0x05,0xE0,0x71,0x68,0x3A,0x5C, ++0x40,0x1C,0x01,0xF8,0x01,0x2B,0x71,0x60, ++0xA8,0x42,0xF7,0xD3,0x30,0x78,0x01,0x28, ++0x16,0xD1,0x70,0x68,0x0A,0x21,0x00,0xF8, ++0x01,0x1B,0x00,0x21,0x03,0x46,0x70,0x60, ++0x01,0xE0,0x49,0x1C,0x5B,0x1C,0x42,0x5C, ++0x3C,0x2A,0x01,0xD0,0xA3,0x42,0xF8,0xD3, ++0x00,0x29,0x02,0xDD,0x20,0x22,0x0A,0xF0, ++0xD4,0xEE,0x70,0x68,0x40,0x1E,0x70,0x60, ++0xBD,0xE8,0xF0,0x81,0x0F,0xB4,0x40,0x21, ++0x11,0x48,0x10,0xB5,0x03,0xAB,0x02,0x9A, ++0x0A,0xF0,0xC0,0xFC,0x01,0x46,0x0E,0x48, ++0xFF,0xF7,0xB0,0xFF,0x10,0xBC,0x5D,0xF8, ++0x14,0xFB,0x10,0xB5,0x07,0x4C,0x10,0xB1, ++0x00,0xF5,0x00,0x70,0x00,0xE0,0x07,0x48, ++0x60,0x60,0x08,0xA0,0xFF,0xF7,0xE6,0xFF, ++0x61,0x68,0x0F,0xA0,0xBD,0xE8,0x10,0x40, ++0xE0,0xE7,0x00,0x00,0xB8,0x04,0x03,0x20, ++0xE0,0x0F,0x02,0x20,0x00,0x00,0x02,0x20, ++0x90,0x05,0x03,0x20,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D,0x3D, ++0x3D,0x3D,0x3D,0x0A,0x00,0x00,0x00,0x00, ++0x62,0x6F,0x6F,0x74,0x6C,0x6F,0x61,0x64, ++0x65,0x72,0x20,0x43,0x75,0x72,0x72,0x65, ++0x6E,0x74,0x20,0x70,0x6F,0x69,0x6E,0x74, ++0x65,0x72,0x20,0x74,0x6F,0x20,0x70,0x44, ++0x65,0x62,0x75,0x67,0x4D,0x65,0x6D,0x20, ++0x61,0x64,0x64,0x72,0x65,0x73,0x73,0x20, ++0x25,0x6C,0x78,0x0A,0x00,0x00,0x00,0x00, ++0x38,0xB5,0xF9,0xA0,0xF7,0x49,0xFF,0xF7, ++0xA5,0xFF,0xFF,0xF7,0xCD,0xFE,0xFF,0x4C, ++0x00,0x23,0x00,0x93,0x20,0x23,0x00,0x22, ++0x21,0x68,0x18,0xB9,0x01,0x20,0x01,0xF0, ++0x1F,0xFF,0x03,0xE0,0x48,0xF2,0x01,0x00, ++0x02,0xF0,0x66,0xFC,0x50,0xB9,0xED,0x48, ++0x4F,0xF4,0x80,0x42,0x21,0x68,0x0A,0xF0, ++0x64,0xEE,0xBD,0xE8,0x38,0x40,0xF4,0xA0, ++0xFF,0xF7,0x88,0xBF,0xBD,0xE8,0x38,0x40, ++0x01,0x46,0xF8,0xA0,0xFF,0xF7,0x82,0xBF, ++0x2D,0xE9,0xF0,0x41,0x00,0x20,0xFE,0x4F, ++0x01,0x46,0x47,0xF8,0x20,0x10,0x40,0x1C, ++0x02,0x28,0xFA,0xD3,0xA5,0x22,0xDF,0x48, ++0x88,0x21,0x00,0xF0,0xFF,0xFE,0x05,0x00, ++0x20,0xD0,0xA5,0x22,0x88,0x21,0x28,0x46, ++0x00,0xF0,0xBA,0xFE,0x00,0x28,0x19,0xD0, ++0x00,0x24,0xF4,0x4E,0x13,0xE0,0x05,0xEB, ++0xC4,0x00,0x00,0x21,0x03,0x6A,0x4A,0x1C, ++0x32,0x43,0x9A,0x42,0x07,0xD1,0x42,0x6A, ++0xEF,0xA0,0x47,0xF8,0x21,0x20,0x49,0x1C, ++0xFF,0xF7,0x58,0xFF,0x02,0xE0,0x49,0x1C, ++0x02,0x29,0xF0,0xD3,0x64,0x1C,0xA8,0x8A, ++0xA0,0x42,0xE8,0xD8,0xBD,0xE8,0xF0,0x81, ++0x2D,0xE9,0xF0,0x41,0xA5,0x22,0xC9,0x48, ++0x81,0x21,0x00,0xF0,0xD3,0xFE,0x05,0x00, ++0xF4,0xD0,0xA5,0x22,0x81,0x21,0x28,0x46, ++0x00,0xF0,0x8E,0xFE,0x00,0x28,0xED,0xD0, ++0x00,0x24,0xE4,0x4E,0xE4,0x4F,0x13,0xE0, ++0x05,0xEB,0xC4,0x00,0x00,0x21,0x03,0x6A, ++0x4A,0x1C,0x32,0x43,0x9A,0x42,0x07,0xD1, ++0x42,0x6A,0xE0,0xA0,0x47,0xF8,0x21,0x20, ++0x49,0x1C,0xFF,0xF7,0x2B,0xFF,0x02,0xE0, ++0x49,0x1C,0x04,0x29,0xF0,0xD3,0x64,0x1C, ++0xA8,0x8A,0xA0,0x42,0xE8,0xD8,0xD1,0xE7, ++0xDD,0x49,0x00,0x20,0x08,0x60,0x48,0x60, ++0x70,0x47,0x70,0x47,0xD4,0x48,0x40,0x68, ++0xB0,0xF1,0x00,0x6F,0x05,0xD8,0x20,0xF0, ++0x03,0x01,0x4F,0xF0,0x00,0x40,0x0A,0xF0, ++0x71,0xBE,0x70,0x47,0x70,0x47,0xAB,0x48, ++0xA5,0x22,0x10,0xB5,0x87,0x21,0x00,0xF0, ++0x2E,0xFF,0xA8,0x48,0xA5,0x22,0x82,0x21, ++0x00,0xF0,0x29,0xFF,0xCF,0x49,0x40,0xF2, ++0xBE,0x60,0x08,0x80,0xCE,0xA0,0xFF,0xF7, ++0xFD,0xFE,0xA2,0x48,0xA5,0x22,0x83,0x21, ++0x00,0xF0,0x1D,0xFF,0x9F,0x48,0xA5,0x22, ++0x84,0x21,0x00,0xF0,0x18,0xFF,0xBD,0xE8, ++0x10,0x40,0xA5,0x22,0x9B,0x48,0x85,0x21, ++0x00,0xF0,0x11,0xBF,0x2D,0xE9,0xF8,0x43, ++0xFF,0xF7,0x12,0xFE,0xC7,0x4C,0x00,0x23, ++0x00,0x93,0x01,0x23,0x00,0x22,0x4C,0xF2, ++0x06,0x09,0x21,0x46,0x30,0xB9,0x06,0x20, ++0x01,0xF0,0x62,0xFE,0x50,0xB1,0x01,0x46, ++0xC1,0xA0,0x05,0xE0,0x48,0x46,0x02,0xF0, ++0xA7,0xFB,0x18,0xB1,0x01,0x46,0xC7,0xA0, ++0xFF,0xF7,0xD0,0xFE,0xCE,0x4A,0x21,0x68, ++0x91,0x42,0x02,0xD0,0xCD,0xA0,0xFF,0xF7, ++0xC9,0xFE,0x21,0x8C,0x02,0x29,0x03,0xD0, ++0x02,0x22,0xD4,0xA0,0xFF,0xF7,0xC2,0xFE, ++0xB4,0x4D,0xDD,0xA1,0x2D,0x1D,0x28,0x46, ++0x0A,0xF0,0x86,0xEE,0x20,0xB1,0xDD,0xA2, ++0x29,0x46,0xDE,0xA0,0xFF,0xF7,0xB6,0xFE, ++0x30,0x21,0x20,0x46,0x01,0xF0,0x0A,0xF8, ++0x21,0x6B,0x88,0x42,0x08,0xD0,0x30,0x21, ++0x20,0x46,0x01,0xF0,0x03,0xF8,0x21,0x6B, ++0x02,0x46,0xE0,0xA0,0xFF,0xF7,0xA6,0xFE, ++0xD4,0xE9,0x05,0x85,0xE8,0xA0,0xE7,0x6A, ++0xE6,0x69,0x29,0x46,0xFF,0xF7,0x9E,0xFE, ++0x31,0x46,0xEA,0xA0,0xFF,0xF7,0x9A,0xFE, ++0x41,0x46,0xEC,0xA0,0xFF,0xF7,0x96,0xFE, ++0x39,0x46,0xEF,0xA0,0xFF,0xF7,0x92,0xFE, ++0xFF,0xF7,0xBA,0xFD,0x4F,0xF0,0x00,0x03, ++0x01,0x21,0x00,0x93,0x00,0x28,0xE2,0x69, ++0xE0,0x6A,0x10,0x44,0x0A,0x46,0x01,0xEB, ++0x50,0x23,0x29,0x46,0x03,0xD1,0x06,0x20, ++0x01,0xF0,0x06,0xFE,0x02,0xE0,0x48,0x46, ++0x02,0xF0,0x4E,0xFB,0xF4,0x19,0x28,0x46, ++0x21,0x46,0x00,0xF0,0xCF,0xFF,0x40,0x45, ++0x08,0xD0,0x21,0x46,0x28,0x46,0x00,0xF0, ++0xC9,0xFF,0x01,0x46,0x42,0x46,0xE1,0xA0, ++0xFF,0xF7,0x6C,0xFE,0xFF,0xF7,0x5B,0xFF, ++0x7B,0x48,0x80,0x68,0x01,0x28,0x03,0xD1, ++0xE6,0xA0,0xFF,0xF7,0x63,0xFE,0xFE,0xE7, ++0xEA,0x48,0x00,0x21,0x80,0xF8,0x80,0x1D, ++0x80,0xF8,0x81,0x1D,0x80,0xF8,0x98,0x1D, ++0x80,0x22,0xA0,0xF8,0x50,0x23,0x15,0x22, ++0xA0,0xF8,0x38,0x23,0x03,0x22,0xA0,0xF8, ++0x50,0x23,0x07,0x22,0xA0,0xF8,0x48,0x23, ++0xE1,0x4A,0x11,0x80,0x20,0x21,0x91,0x87, ++0x68,0x21,0x01,0x80,0x4F,0xF4,0x90,0x71, ++0x81,0x80,0xDE,0x48,0x00,0x68,0x00,0xF0, ++0x76,0xF8,0x29,0x46,0xDC,0xA0,0xFF,0xF7, ++0x3D,0xFE,0xA8,0x47,0xDF,0xA0,0xFF,0xF7, ++0x39,0xFE,0xFE,0xE7,0x49,0x48,0x10,0xB5, ++0x02,0x68,0xD6,0x48,0x01,0x68,0xDE,0xA0, ++0xFF,0xF7,0x30,0xFE,0x00,0xF0,0x46,0xF8, ++0x20,0xB9,0x01,0x21,0xE4,0xA0,0xFF,0xF7, ++0x29,0xFE,0xFE,0xE7,0xE5,0xA0,0xFF,0xF7, ++0x25,0xFE,0xFF,0xF7,0x79,0xFE,0xFF,0xF7, ++0x9F,0xFE,0xFF,0xF7,0x4F,0xFB,0xFF,0xF7, ++0xEF,0xFC,0x02,0x28,0x02,0xD0,0xFF,0xF7, ++0x57,0xFB,0x50,0xB1,0xDF,0xA0,0xFF,0xF7, ++0x15,0xFE,0xFF,0xF7,0xA2,0xFA,0x01,0xF0, ++0x1D,0xF8,0x44,0xF6,0x20,0x60,0xFF,0xF7, ++0xA4,0xFB,0xDD,0xA0,0xFF,0xF7,0x0A,0xFE, ++0xFF,0xF7,0xBA,0xFE,0xDC,0xA0,0xFF,0xF7, ++0x05,0xFE,0xFF,0xF7,0xE1,0xFE,0xDC,0xA0, ++0xFF,0xF7,0x00,0xFE,0x23,0x48,0xA5,0x22, ++0x81,0x21,0x00,0xF0,0x20,0xFE,0xDA,0xA0, ++0xFF,0xF7,0xF8,0xFD,0x00,0xF0,0x06,0xFD, ++0xD9,0xA0,0xFF,0xF7,0xF3,0xFD,0xFF,0xF7, ++0xD5,0xFE,0xD9,0xA0,0xFF,0xF7,0xEE,0xFD, ++0xD9,0xA0,0xFF,0xF7,0xEB,0xFD,0xBD,0xE8, ++0x10,0x40,0xFB,0xE6,0x3A,0x49,0x00,0x20, ++0x10,0xB5,0x04,0x46,0x08,0x60,0x48,0x60, ++0x88,0x60,0xC8,0x60,0xFF,0xF7,0x08,0xFD, ++0x28,0xB9,0xD4,0xA0,0xFF,0xF7,0xDA,0xFD, ++0x01,0xF0,0x6E,0xF9,0x04,0xE0,0xD3,0xA0, ++0xFF,0xF7,0xD4,0xFD,0x02,0xF0,0x9C,0xFD, ++0x18,0xB9,0xD2,0xA0,0xFF,0xF7,0xCE,0xFD, ++0x01,0x24,0xE0,0xB2,0x10,0xBD,0x2D,0xE9, ++0xF0,0x41,0x06,0x46,0x07,0x4A,0x01,0x46, ++0xCE,0xA0,0xFF,0xF7,0xC3,0xFD,0x21,0x24, ++0x04,0x48,0xA5,0x22,0xE1,0xB2,0x0F,0x46, ++0x00,0xF0,0x48,0xFD,0x05,0x00,0x00,0xD0, ++0xA2,0xE1,0xB4,0xE1,0x00,0x10,0x02,0x20, ++0x5B,0x48,0x57,0x5F,0x43,0x46,0x47,0x5D, ++0x6C,0x6F,0x61,0x64,0x5F,0x6D,0x69,0x75, ++0x5F,0x70,0x61,0x72,0x74,0x69,0x74,0x69, ++0x6F,0x6E,0x5F,0x4F,0x4B,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0xB0,0x04,0x03,0x20, ++0x5B,0x48,0x57,0x5F,0x43,0x46,0x47,0x5D, ++0x52,0x65,0x61,0x64,0x5F,0x68,0x77,0x5F, ++0x63,0x6F,0x6E,0x66,0x69,0x67,0x5F,0x4F, ++0x4B,0x0A,0x00,0x00,0x5B,0x48,0x57,0x5F, ++0x43,0x46,0x47,0x5D,0x52,0x65,0x61,0x64, ++0x5F,0x68,0x77,0x5F,0x63,0x6F,0x6E,0x69, ++0x67,0x5F,0x46,0x61,0x69,0x6C,0x5F,0x28, ++0x25,0x6C,0x78,0x29,0x0A,0x00,0x00,0x00, ++0xA4,0x04,0x03,0x20,0x00,0x00,0xFD,0xFF, ++0x4B,0x65,0x79,0x42,0x69,0x74,0x73,0x4D, ++0x61,0x70,0x28,0x25,0x78,0x29,0x3D,0x25, ++0x78,0x0A,0x00,0x00,0x00,0x00,0xFE,0xFF, ++0xD0,0x05,0x03,0x20,0x62,0x6F,0x6F,0x74, ++0x5F,0x6F,0x70,0x74,0x28,0x25,0x78,0x29, ++0x3D,0x25,0x78,0x0A,0x00,0x00,0x00,0x00, ++0x00,0x3C,0x30,0x25,0x24,0x2B,0x00,0x25, ++0x73,0x65,0x74,0x5F,0x6D,0x63,0x75,0x5F, ++0x66,0x75,0x6C,0x6C,0x5F,0x73,0x70,0x65, ++0x65,0x64,0x0A,0x00,0x00,0xFE,0x1F,0x83, ++0x4E,0x41,0x4E,0x44,0x20,0x6C,0x6F,0x61, ++0x64,0x5F,0x75,0x62,0x6F,0x6F,0x74,0x5F, ++0x68,0x65,0x61,0x64,0x65,0x72,0x5B,0x46, ++0x41,0x49,0x4C,0x5D,0x28,0x25,0x6C,0x78, ++0x29,0x0A,0x00,0x00,0x65,0x4D,0x4D,0x43, ++0x20,0x6C,0x6F,0x61,0x64,0x5F,0x75,0x62, ++0x6F,0x6F,0x74,0x5F,0x68,0x65,0x61,0x64, ++0x65,0x72,0x5B,0x46,0x41,0x49,0x4C,0x5D, ++0x28,0x25,0x6C,0x78,0x29,0x0A,0x00,0x00, ++0x27,0x37,0x91,0x35,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x6D,0x61,0x67,0x69,0x63,0x28, ++0x58,0x5F,0x25,0x6C,0x78,0x2C,0x4F,0x5F, ++0x25,0x6C,0x78,0x29,0x5B,0x4E,0x47,0x5D, ++0x0A,0x00,0x00,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x69,0x6D,0x67,0x5F,0x74,0x79, ++0x70,0x65,0x28,0x58,0x5F,0x25,0x6C,0x78, ++0x2C,0x4F,0x5F,0x25,0x6C,0x78,0x29,0x5B, ++0x4E,0x47,0x5D,0x0A,0x00,0x00,0x00,0x00, ++0x47,0x32,0x50,0x55,0x42,0x4F,0x4F,0x54, ++0x00,0x00,0x00,0x00,0x47,0x32,0x55,0x42, ++0x4F,0x4F,0x54,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x69,0x6D,0x67,0x5F,0x6E,0x61, ++0x6D,0x65,0x28,0x58,0x5F,0x25,0x73,0x2C, ++0x4F,0x5F,0x25,0x73,0x29,0x5B,0x4E,0x47, ++0x5D,0x0A,0x00,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x68,0x65,0x61,0x64,0x65, ++0x72,0x5F,0x63,0x68,0x65,0x63,0x6B,0x73, ++0x75,0x6D,0x28,0x58,0x5F,0x25,0x6C,0x78, ++0x2C,0x4F,0x5F,0x25,0x6C,0x78,0x29,0x5B, ++0x4E,0x47,0x5D,0x0A,0x00,0x00,0x00,0x00, ++0x4C,0x6F,0x61,0x64,0x41,0x64,0x64,0x72, ++0x65,0x73,0x73,0x28,0x25,0x6C,0x78,0x29, ++0x0A,0x00,0x00,0x00,0x49,0x6D,0x61,0x67, ++0x65,0x53,0x69,0x7A,0x65,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x49,0x6D,0x61,0x67, ++0x65,0x43,0x68,0x6B,0x73,0x75,0x6D,0x28, ++0x25,0x6C,0x78,0x29,0x0A,0x00,0x00,0x00, ++0x53,0x69,0x67,0x6E,0x61,0x74,0x75,0x72, ++0x65,0x53,0x69,0x7A,0x65,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x20,0x75,0x62,0x6F, ++0x6F,0x74,0x5F,0x69,0x6D,0x61,0x67,0x65, ++0x5F,0x63,0x68,0x65,0x63,0x6B,0x73,0x75, ++0x6D,0x28,0x58,0x5F,0x25,0x6C,0x78,0x2C, ++0x4F,0x5F,0x25,0x6C,0x78,0x29,0x5B,0x4E, ++0x47,0x5D,0x0A,0x00,0x6C,0x6F,0x6F,0x70, ++0x5F,0x62,0x79,0x5F,0x62,0x6F,0x6F,0x74, ++0x5F,0x6F,0x70,0x74,0x69,0x6F,0x6E,0x0A, ++0x00,0x00,0x00,0x00,0xC8,0x70,0x00,0x25, ++0x14,0x2C,0x02,0x25,0xAC,0x04,0x03,0x20, ++0x6A,0x75,0x6D,0x70,0x20,0x74,0x6F,0x20, ++0x75,0x62,0x6F,0x6F,0x74,0x28,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x66,0x61,0x69,0x6C, ++0x20,0x6C,0x6F,0x6F,0x70,0x0A,0x00,0x00, ++0x67,0x75,0x38,0x75,0x63,0x44,0x6D,0x61, ++0x42,0x75,0x66,0x3D,0x30,0x78,0x25,0x78, ++0x2C,0x20,0x67,0x75,0x38,0x75,0x63,0x54, ++0x65,0x6D,0x70,0x42,0x75,0x66,0x3D,0x30, ++0x78,0x25,0x78,0x0A,0x00,0x00,0x00,0x00, ++0x45,0x72,0x72,0x5B,0x25,0x78,0x5D,0x0A, ++0x00,0x00,0x00,0x00,0x31,0x31,0x31,0x0A, ++0x00,0x00,0x00,0x00,0x44,0x57,0x4C,0x20, ++0x42,0x73,0x74,0x0A,0x00,0x00,0x00,0x00, ++0x32,0x32,0x32,0x0A,0x00,0x00,0x00,0x00, ++0x33,0x33,0x33,0x0A,0x00,0x00,0x00,0x00, ++0x34,0x34,0x34,0x0A,0x00,0x00,0x00,0x00, ++0x35,0x35,0x35,0x0A,0x00,0x00,0x00,0x00, ++0x36,0x36,0x36,0x0A,0x00,0x00,0x00,0x00, ++0x37,0x37,0x37,0x0A,0x00,0x00,0x00,0x00, ++0x62,0x6F,0x6F,0x74,0x5F,0x75,0x62,0x6F, ++0x6F,0x74,0x0A,0x00,0x4E,0x41,0x4E,0x44, ++0x0A,0x00,0x00,0x00,0x65,0x4D,0x4D,0x43, ++0x0A,0x00,0x00,0x00,0x20,0x4F,0x4B,0x0A, ++0x00,0x00,0x00,0x00,0x49,0x4D,0x49,0x5F, ++0x61,0x64,0x64,0x72,0x28,0x25,0x6C,0x78, ++0x29,0x5F,0x67,0x75,0x38,0x48,0x57,0x63, ++0x6F,0x6E,0x66,0x69,0x67,0x42,0x75,0x66, ++0x28,0x30,0x78,0x25,0x78,0x29,0x0A,0x00, ++0xA5,0x22,0x39,0x46,0x28,0x46,0x00,0xF0, ++0x5F,0xFB,0x60,0xB1,0xA8,0x8A,0x44,0xEA, ++0x00,0x40,0x01,0xC6,0x28,0x46,0xAA,0x8A, ++0x31,0x46,0x00,0xF0,0x0E,0xF8,0xA8,0x8A, ++0x06,0xEB,0xC0,0x06,0x04,0xE0,0x22,0x46, ++0x29,0x46,0x17,0xA0,0xFF,0xF7,0xFE,0xFB, ++0x64,0x1C,0x2F,0x2C,0x7F,0xF7,0x38,0xAE, ++0xA8,0xE4,0x2D,0xE9,0xF0,0x41,0x06,0x46, ++0x00,0x25,0x0C,0x46,0x17,0x46,0x17,0xA0, ++0xFF,0xF7,0xF0,0xFB,0x00,0x20,0x16,0xE0, ++0x06,0xEB,0xC0,0x01,0x0A,0x6A,0x53,0x1C, ++0x0B,0xD1,0x4A,0x6A,0x52,0x1C,0x0D,0xD1, ++0x40,0x1C,0x15,0x4A,0x22,0x60,0x89,0x6A, ++0x44,0xF8,0x04,0x1F,0x24,0x1D,0x6D,0x1C, ++0x04,0xE0,0x22,0x60,0x49,0x6A,0x44,0xF8, ++0x04,0x1F,0x24,0x1D,0x40,0x1C,0x79,0x19, ++0x81,0x42,0xE5,0xD8,0x82,0xE4,0x00,0x00, ++0x5B,0x48,0x57,0x5F,0x43,0x46,0x47,0x5D, ++0x28,0x30,0x78,0x25,0x78,0x29,0x46,0x61, ++0x69,0x6C,0x65,0x64,0x28,0x30,0x78,0x25, ++0x78,0x29,0x0A,0x00,0x54,0x4C,0x56,0x28, ++0x25,0x6C,0x78,0x29,0x53,0x65,0x74,0x28, ++0x25,0x78,0x29,0x0A,0x00,0x00,0x00,0x00, ++0x66,0x66,0xFF,0xFF,0x00,0x00,0x0F,0xE1, ++0xC0,0x10,0x80,0xE3,0x01,0xF0,0x21,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x00,0x00,0x0F,0xE1, ++0xC0,0x00,0xC0,0xE3,0x00,0xF0,0x21,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x00,0x10,0x0F,0xE1, ++0xC0,0x00,0x00,0xE2,0xC0,0x10,0xC1,0xE3, ++0x01,0x00,0x80,0xE1,0x00,0xF0,0x21,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x1F,0x20,0xC0,0xE3, ++0x01,0x00,0x80,0xE0,0x1F,0x00,0x80,0xE2, ++0x1F,0x00,0xC0,0xE3,0x00,0x00,0x52,0xE1, ++0x3E,0x2F,0x07,0x3E,0x20,0x20,0x82,0x32, ++0xFB,0xFF,0xFF,0x3A,0x00,0x00,0xA0,0xE3, ++0x9A,0x0F,0x07,0xEE,0x1E,0xFF,0x2F,0xE1, ++0x70,0x47,0x3F,0x28,0x05,0xDC,0x5A,0x4B, ++0x43,0xF8,0x20,0x10,0x59,0x49,0x41,0xF8, ++0x20,0x20,0x70,0x47,0x40,0x28,0x10,0xB5, ++0x15,0xD2,0xC1,0x17,0x56,0x4A,0x00,0xEB, ++0xD1,0x63,0x59,0x11,0x02,0xEB,0x81,0x02, ++0x14,0x68,0x23,0xF0,0x1F,0x03,0xC3,0x1A, ++0x01,0x20,0x98,0x40,0x04,0x43,0x14,0x60, ++0x4F,0x4A,0x08,0x3A,0x02,0xEB,0x81,0x01, ++0x0A,0x68,0x02,0x43,0x0A,0x60,0x10,0xBD, ++0x3F,0x28,0x0C,0xDC,0x48,0x4A,0x19,0xB1, ++0x52,0xF8,0x20,0x30,0x8B,0x42,0x06,0xD1, ++0x48,0x49,0x42,0xF8,0x20,0x10,0x00,0x21, ++0x44,0x4A,0x42,0xF8,0x20,0x10,0x70,0x47, ++0x10,0xB5,0x04,0x46,0xFF,0xF7,0x96,0xEF, ++0x40,0x2C,0x0F,0xD2,0xE1,0x17,0x04,0xEB, ++0xD1,0x62,0x3F,0x49,0x53,0x11,0x40,0x39, ++0x01,0xEB,0x83,0x01,0x0B,0x68,0x22,0xF0, ++0x1F,0x02,0xA4,0x1A,0x01,0x22,0xA2,0x40, ++0x13,0x43,0x0B,0x60,0xBD,0xE8,0x10,0x40, ++0x0B,0xF0,0x6C,0xBF,0x10,0xB5,0x04,0x46, ++0xFF,0xF7,0x7C,0xEF,0x40,0x2C,0x0F,0xD2, ++0xE1,0x17,0x04,0xEB,0xD1,0x62,0x32,0x49, ++0x53,0x11,0x40,0x39,0x01,0xEB,0x83,0x01, ++0x0B,0x68,0x22,0xF0,0x1F,0x02,0xA4,0x1A, ++0x01,0x22,0xA2,0x40,0x93,0x43,0x0B,0x60, ++0xBD,0xE8,0x10,0x40,0x0B,0xF0,0x52,0xBF, ++0x70,0xB5,0x04,0x46,0x15,0x46,0x1E,0x46, ++0xFF,0xF7,0xE0,0xFF,0x32,0x46,0x29,0x46, ++0x20,0x46,0xFF,0xF7,0x8E,0xFF,0x20,0x46, ++0xBD,0xE8,0x70,0x40,0xBC,0xE7,0x2D,0xE9, ++0xF0,0x41,0x04,0x46,0x0D,0x46,0x17,0x46, ++0xFF,0xF7,0x50,0xEF,0xE1,0x17,0x1E,0x4B, ++0x01,0x26,0x04,0xEB,0xD1,0x62,0x38,0x3B, ++0x22,0xF0,0x1F,0x01,0x61,0x1A,0x8E,0x40, ++0x51,0x11,0x01,0x2D,0x03,0xEB,0x81,0x01, ++0x0A,0x68,0x01,0xD1,0x32,0x43,0x00,0xE0, ++0xB2,0x43,0x0A,0x60,0xE2,0x17,0x14,0x49, ++0x04,0xEB,0xD2,0x62,0x30,0x39,0x52,0x11, ++0x01,0x2F,0x01,0xEB,0x82,0x01,0x0A,0x68, ++0x01,0xD1,0x32,0x43,0x00,0xE0,0xB2,0x43, ++0x0A,0x60,0xBD,0xE8,0xF0,0x41,0x0B,0xF0, ++0x15,0xBF,0x0D,0x48,0x00,0x78,0x00,0xF0, ++0x0F,0x00,0x06,0x28,0x07,0xD0,0x07,0x28, ++0x03,0xD0,0x08,0x28,0x05,0xD1,0x01,0x20, ++0x70,0x47,0x03,0x20,0x70,0x47,0x02,0x20, ++0x70,0x47,0x00,0x20,0x70,0x47,0x00,0x00, ++0x74,0xD2,0x02,0x20,0x74,0xD3,0x02,0x20, ++0x5C,0x0C,0x30,0x25,0xB9,0x2A,0x03,0x20, ++0x90,0x71,0x00,0x25,0x08,0x49,0xD1,0xF8, ++0x3C,0x0C,0x00,0xB2,0x82,0x05,0x04,0xD5, ++0xD1,0xF8,0x40,0x0C,0x00,0xB2,0x81,0x05, ++0x02,0xD4,0xC0,0xF3,0x85,0x00,0x70,0x47, ++0x4F,0xF0,0xFF,0x30,0x70,0x47,0x00,0x00, ++0x00,0x00,0x30,0x25,0x70,0x47,0x00,0x00, ++0x2D,0xE9,0xF0,0x47,0x00,0x25,0xDE,0x4C, ++0xA5,0x87,0xA5,0x87,0xA5,0x87,0x01,0x26, ++0xA6,0x87,0xA5,0x87,0xC8,0x20,0xFF,0xF7, ++0xB5,0xF9,0x4F,0xF6,0x7E,0x70,0xA4,0xF8, ++0x0C,0x01,0xA4,0xF8,0x9C,0x50,0xF7,0x03, ++0xA4,0xF8,0x48,0x70,0x24,0xF8,0x4C,0x5F, ++0x49,0xF6,0xE9,0x60,0xA0,0x87,0x7B,0x20, ++0xA4,0xF8,0x40,0x00,0x4F,0xF0,0x39,0x09, ++0xA4,0xF8,0x2C,0x90,0x4C,0xF2,0x1E,0x00, ++0x20,0x81,0x4F,0xF4,0xE0,0x40,0x20,0x82, ++0x30,0x02,0xA0,0x86,0x10,0x20,0x20,0x87, ++0x4F,0xF6,0x4F,0x70,0xA0,0x81,0x4F,0xF2, ++0xF0,0x00,0x20,0x83,0x4F,0xF4,0x7F,0x40, ++0xA0,0x82,0x4C,0x3C,0x44,0xF2,0x44,0x00, ++0xA4,0xF8,0x7C,0x00,0xA4,0xF8,0x80,0x50, ++0xAE,0x34,0x24,0xF8,0x2A,0x5C,0xC8,0x20, ++0xFF,0xF7,0x80,0xF9,0xBF,0x49,0x20,0x20, ++0xA1,0xF8,0x78,0x02,0x4F,0xF0,0x07,0x08, ++0xA4,0xF8,0x36,0x80,0x40,0xF6,0x78,0x00, ++0x60,0x87,0x48,0xF6,0x88,0x00,0xE0,0x87, ++0xAE,0x3C,0x47,0xF2,0x77,0x71,0xA4,0xF8, ++0xF0,0x10,0xA4,0xF8,0xF4,0x00,0x4F,0xF4, ++0x58,0x50,0xA4,0xF8,0xE4,0x01,0xA6,0x87, ++0xA5,0x87,0xA6,0x87,0xA5,0x87,0x40,0xF6, ++0x95,0x10,0xA0,0x80,0x41,0xF6,0xF9,0x70, ++0x20,0x81,0x45,0xF2,0x50,0x10,0xA0,0x81, ++0x40,0xF6,0x33,0x00,0x20,0x82,0xAC,0xA0, ++0xFF,0xF7,0x40,0xFA,0x40,0xF6,0x22,0x30, ++0xA0,0x82,0x45,0xF2,0x31,0x20,0x20,0x83, ++0x41,0xF2,0x16,0x20,0xA0,0x83,0x32,0x20, ++0x20,0x84,0xA7,0x84,0x48,0xF2,0x04,0x30, ++0xA4,0xF8,0x88,0x01,0x35,0x20,0xA4,0xF8, ++0x8C,0x01,0x4F,0xF6,0xFF,0x70,0xA4,0xF8, ++0x90,0x01,0xA4,0xF8,0x94,0x01,0xA4,0xF8, ++0x98,0x01,0xA4,0xF8,0x9C,0x01,0x24,0xF8, ++0x64,0x5F,0x40,0x20,0x20,0x81,0xA4,0xF8, ++0x14,0x90,0x1F,0x20,0xA4,0xF8,0xEC,0x00, ++0x40,0xF6,0xAA,0x20,0xA0,0x80,0x64,0x3C, ++0x03,0x20,0xA4,0xF8,0xB4,0x00,0xA4,0xF8, ++0xB4,0x60,0x40,0xF2,0x22,0x50,0xA4,0xF8, ++0x9C,0x00,0xE4,0x20,0xA4,0xF8,0xA0,0x00, ++0xA4,0xF8,0x90,0x50,0x25,0x80,0x06,0x20, ++0x20,0x80,0xC8,0x20,0xFF,0xF7,0x16,0xF9, ++0xA4,0xF8,0x00,0x80,0x4F,0xF4,0xFA,0x60, ++0xFF,0xF7,0x10,0xF9,0xC8,0x20,0xFF,0xF7, ++0x0D,0xF9,0x4F,0xF4,0x90,0x50,0xA4,0xF8, ++0xE4,0x01,0x78,0x1C,0xA4,0xF8,0x00,0x01, ++0xA6,0x86,0xA4,0xF8,0x0C,0x51,0xBD,0xE8, ++0xF0,0x87,0x2D,0xE9,0xF0,0x41,0x00,0x25, ++0x7D,0x4C,0xA5,0x87,0xA5,0x87,0xA5,0x87, ++0x01,0x26,0xA6,0x87,0x46,0x34,0x24,0xF8, ++0x0A,0x5C,0xB0,0x03,0x60,0x80,0x4F,0xF4, ++0x40,0x70,0xE0,0x80,0x4F,0xF4,0xE0,0x40, ++0xE0,0x82,0x4C,0xF6,0xC8,0x00,0xA4,0xF8, ++0x42,0x00,0x3C,0x20,0xA4,0xF8,0x46,0x00, ++0x37,0x02,0x67,0x87,0x4F,0xF0,0x10,0x08, ++0xA4,0xF8,0x3E,0x80,0x4F,0xF6,0xF0,0x70, ++0x60,0x83,0x46,0x3C,0x4F,0xF4,0x7F,0x40, ++0xA4,0xF8,0x64,0x00,0xA4,0xF8,0x80,0x50, ++0xA4,0xF8,0x84,0x50,0x0A,0x20,0xFF,0xF7, ++0xBB,0xF8,0x68,0x49,0x40,0x20,0xA1,0xF8, ++0x78,0x02,0x94,0x20,0xA0,0x80,0x4C,0xF6, ++0xF6,0x20,0x20,0x81,0x41,0xF2,0x28,0x10, ++0xA0,0x81,0x40,0xF6,0x33,0x00,0x20,0x82, ++0x40,0xF6,0x03,0x40,0xA0,0x82,0x46,0xF2, ++0x50,0x40,0x20,0x83,0x41,0xF2,0x0E,0x00, ++0xA0,0x83,0x31,0x20,0x20,0x84,0x4F,0xF4, ++0x10,0x50,0xA0,0x84,0xF0,0x03,0x20,0x85, ++0x4F,0xF4,0x40,0x40,0xA0,0x85,0x4F,0xF4, ++0x84,0x50,0xA4,0xF8,0x40,0x01,0xA4,0xF8, ++0x4C,0x51,0xA6,0x87,0xA5,0x87,0xA6,0x87, ++0xA5,0x87,0x42,0xF2,0xAA,0x20,0xA4,0xF8, ++0x90,0x00,0x40,0xF2,0xAA,0x20,0xA4,0xF8, ++0x94,0x00,0xA4,0xF8,0x9C,0x70,0xA4,0xF8, ++0xD0,0x60,0x25,0x80,0x06,0x20,0x20,0x80, ++0x07,0x20,0x20,0x80,0x0A,0x20,0xFF,0xF7, ++0x7B,0xF8,0x48,0xF2,0x01,0x00,0xA4,0xF8, ++0x00,0x01,0xA6,0x86,0xA4,0xF8,0x0C,0x51, ++0x4F,0xF4,0x58,0x50,0xA4,0xF8,0xE4,0x01, ++0xA4,0xF8,0xC4,0x51,0xA4,0xF8,0xC8,0x81, ++0xA4,0xF8,0xCC,0x51,0x45,0xF6,0xA5,0x20, ++0xA4,0xF8,0xD0,0x01,0xA4,0xF8,0xC0,0x51, ++0xBD,0xE8,0xF0,0x81,0x70,0x47,0x3D,0x49, ++0x07,0x28,0x09,0xD8,0x0A,0x88,0x22,0xF4, ++0x60,0x42,0x42,0xEA,0x40,0x30,0x08,0x80, ++0x4C,0xF2,0x50,0x30,0xFF,0xF7,0x6A,0xB8, ++0x70,0x47,0x36,0x48,0x00,0x88,0x20,0xF4, ++0x60,0x40,0x40,0x0B,0x70,0x47,0x34,0x48, ++0xA5,0x22,0x10,0xB5,0x86,0x21,0x00,0xF0, ++0x6E,0xF9,0x31,0x4C,0x31,0xA0,0x21,0x46, ++0xFF,0xF7,0x44,0xF9,0xA5,0x22,0x11,0x21, ++0x20,0x46,0x00,0xF0,0xCB,0xF8,0x04,0x00, ++0x11,0xD0,0xA5,0x22,0x11,0x21,0x20,0x46, ++0x00,0xF0,0x86,0xF8,0x58,0xB1,0x61,0x7C, ++0x30,0xA0,0xFF,0xF7,0x33,0xF9,0x20,0x46, ++0x00,0xF0,0xDD,0xF8,0x61,0x7C,0x31,0xA0, ++0xFF,0xF7,0x2C,0xF9,0x05,0xE0,0x34,0xA0, ++0xFF,0xF7,0x28,0xF9,0x01,0x20,0xFF,0xF7, ++0x77,0xFE,0xBD,0xE8,0x10,0x40,0x02,0xF0, ++0x2C,0xBD,0x19,0x48,0x94,0x21,0x81,0x80, ++0x48,0xF2,0xF5,0x21,0x01,0x81,0x41,0xF2, ++0x28,0x11,0x81,0x81,0x40,0xF6,0x33,0x01, ++0x01,0x82,0x40,0xF6,0x03,0x41,0x81,0x82, ++0x46,0xF2,0x50,0x41,0x01,0x83,0x41,0xF2, ++0x0E,0x21,0x81,0x83,0x31,0x21,0x01,0x84, ++0x4F,0xF4,0x10,0x51,0x81,0x84,0x4F,0xF4, ++0x00,0x41,0x01,0x85,0x4F,0xF4,0x40,0x41, ++0x81,0x85,0x00,0x21,0x01,0x80,0x06,0x22, ++0x02,0x80,0x07,0x22,0x02,0x80,0x23,0x4A, ++0x11,0x84,0x48,0xF2,0x01,0x02,0xA0,0xF8, ++0x00,0x21,0x01,0x22,0x82,0x86,0xA0,0xF8, ++0x0C,0x11,0x70,0x47,0x9F,0xE7,0x00,0x00, ++0x00,0x24,0x00,0x25,0x00,0x70,0x00,0x25, ++0x61,0x63,0x0A,0x00,0x44,0x0B,0x02,0x25, ++0x00,0x10,0x02,0x20,0x43,0x68,0x65,0x63, ++0x6B,0x20,0x4D,0x49,0x55,0x20,0x66,0x72, ++0x6F,0x6D,0x20,0x4E,0x41,0x4E,0x44,0x2F, ++0x55,0x53,0x42,0x28,0x30,0x78,0x25,0x6C, ++0x78,0x29,0x0A,0x00,0x75,0x73,0x65,0x5F, ++0x68,0x77,0x63,0x66,0x67,0x28,0x25,0x78, ++0x29,0x0A,0x00,0x00,0x65,0x6E,0x64,0x20, ++0x75,0x73,0x65,0x5F,0x68,0x77,0x63,0x66, ++0x67,0x28,0x25,0x78,0x29,0x0A,0x00,0x00, ++0x44,0x65,0x66,0x61,0x75,0x6C,0x74,0x5F, ++0x4D,0x49,0x55,0x5F,0x44,0x44,0x52,0x33, ++0x32,0x5F,0x69,0x6E,0x69,0x74,0x5B,0x69, ++0x6E,0x5D,0x0A,0x00,0x00,0x70,0x02,0x25, ++0x2D,0xE9,0xF0,0x41,0x04,0x46,0x88,0x46, ++0xC1,0x8A,0x20,0x30,0x16,0x46,0x00,0xF0, ++0x01,0xFA,0xDF,0xF8,0x2C,0xC3,0x05,0x46, ++0x20,0x68,0x60,0x45,0x13,0xD1,0xE2,0x7C, ++0x42,0x45,0x10,0xD1,0x63,0x7C,0xB3,0x42, ++0x01,0xD0,0xA5,0x2E,0x0B,0xD1,0x21,0x7C, ++0x04,0x29,0x08,0xD1,0xE7,0x69,0xAF,0x42, ++0x05,0xD1,0xC2,0xA0,0xFF,0xF7,0x92,0xF8, ++0x01,0x20,0xBD,0xE8,0xF0,0x81,0x01,0x46, ++0x62,0x46,0xC8,0xA0,0xFF,0xF7,0x8A,0xF8, ++0xE1,0x7C,0x42,0x46,0xCA,0xA0,0xFF,0xF7, ++0x85,0xF8,0x61,0x7C,0x32,0x46,0xCD,0xA0, ++0xFF,0xF7,0x80,0xF8,0xE1,0x69,0x2A,0x46, ++0xCF,0xA0,0xFF,0xF7,0x7B,0xF8,0x21,0x7C, ++0x04,0x22,0xD3,0xA0,0xFF,0xF7,0x76,0xF8, ++0x00,0x20,0xE2,0xE7,0x70,0xB5,0x04,0x46, ++0xAF,0x48,0x13,0x46,0x13,0xE0,0x25,0x7C, ++0x04,0x2D,0x0D,0xD1,0x8A,0x42,0x0B,0xD1, ++0x65,0x7C,0x9D,0x42,0x01,0xD0,0xA5,0x2B, ++0x06,0xD1,0x21,0x7C,0x23,0x46,0xCD,0xA0, ++0xFF,0xF7,0x60,0xF8,0x20,0x46,0x70,0xBD, ++0xE2,0x8A,0x20,0x34,0x14,0x44,0x22,0x68, ++0x82,0x42,0x02,0xD1,0xE2,0x7C,0xFF,0x2A, ++0xE5,0xD3,0x00,0x20,0x70,0xBD,0x2D,0xE9, ++0xF0,0x41,0x80,0x46,0x80,0x7C,0x00,0x26, ++0x00,0x28,0x6E,0xD0,0x01,0x28,0x6C,0xD1, ++0x00,0x25,0x65,0xE0,0x08,0xEB,0xC5,0x04, ++0x20,0x6A,0x41,0x1C,0x23,0xD1,0x60,0x6A, ++0x41,0x1C,0x03,0xD1,0xA0,0x6A,0xFE,0xF7, ++0x51,0xFF,0x19,0xE0,0x81,0x1C,0x09,0xD1, ++0xA7,0x6A,0x02,0xE0,0x01,0x20,0xFE,0xF7, ++0x49,0xFF,0x38,0x68,0xE1,0x6A,0x88,0x42, ++0xF8,0xD1,0x0D,0xE0,0xC0,0x1C,0x09,0xD1, ++0xA7,0x6A,0x02,0xE0,0x01,0x20,0xFE,0xF7, ++0x3D,0xFF,0x38,0x68,0xE1,0x6A,0x88,0x42, ++0xF8,0xD0,0x01,0xE0,0x6D,0x1E,0x76,0x1E, ++0x6D,0x1C,0x76,0x1C,0x3B,0xE0,0x4F,0xF6, ++0xFF,0x71,0xB1,0xEB,0x10,0x4F,0x05,0xD1, ++0x61,0x6A,0x80,0xB2,0x89,0xB2,0x02,0xF0, ++0xF2,0xFD,0x30,0xE0,0x4F,0xF6,0xFE,0x71, ++0xB1,0xEB,0x10,0x4F,0x2B,0xD0,0x49,0x1E, ++0xB1,0xEB,0x10,0x4F,0x06,0xD1,0x60,0x6A, ++0x02,0x68,0xA1,0x6A,0xE3,0x6A,0x8A,0x43, ++0x19,0x40,0x1A,0xE0,0x4F,0xF6,0xFC,0x71, ++0xB1,0xEB,0x10,0x4F,0x19,0xD1,0xC0,0x07, ++0x05,0xD0,0x01,0xF0,0xE7,0xFF,0x61,0x6A, ++0x88,0x42,0x10,0xD1,0x04,0xE0,0x01,0xF0, ++0xE1,0xFF,0x61,0x6A,0x88,0x42,0x0A,0xD3, ++0x20,0x6A,0xC0,0x06,0x00,0x28,0xA0,0x6A, ++0x01,0x68,0xE2,0x6A,0x01,0xDA,0x91,0x43, ++0x00,0xE0,0x11,0x43,0x01,0x60,0x6D,0x1C, ++0x01,0xE0,0x61,0x6A,0x01,0x60,0x6D,0x1C, ++0xB8,0xF8,0x14,0x00,0x30,0x44,0xA8,0x42, ++0x94,0xD8,0x01,0x20,0x49,0xE7,0x70,0xB5, ++0x04,0x46,0x0D,0x46,0x16,0x46,0x8E,0xA0, ++0xFE,0xF7,0xD4,0xFF,0x32,0x46,0x29,0x46, ++0x20,0x46,0xFF,0xF7,0x5B,0xFF,0x04,0x00, ++0x0D,0xD0,0x32,0x46,0x29,0x46,0x20,0x46, ++0xFF,0xF7,0x16,0xFF,0x38,0xB1,0x20,0x46, ++0xFF,0xF7,0x71,0xFF,0x89,0xA0,0xFE,0xF7, ++0xC1,0xFF,0x01,0x20,0x70,0xBD,0x89,0xA0, ++0xFE,0xF7,0xBC,0xFF,0x00,0x20,0x70,0xBD, ++0x2D,0xE9,0xF0,0x41,0x07,0x46,0x88,0x46, ++0x14,0x46,0x06,0x9E,0x1D,0x46,0x08,0x46, ++0x02,0xF0,0x80,0xFD,0x04,0xFA,0x05,0xF1, ++0x39,0x40,0x80,0xB2,0xE9,0x40,0xB4,0x40, ++0xB1,0x40,0x20,0xEA,0x04,0x02,0x0A,0x43, ++0x91,0xB2,0x88,0x42,0x04,0xD0,0x40,0x46, ++0xBD,0xE8,0xF0,0x41,0x02,0xF0,0x7B,0xBD, ++0x0B,0xE7,0x08,0xB5,0x07,0x23,0x01,0x22, ++0x42,0xF2,0x48,0x01,0x00,0x93,0x00,0x23, ++0x10,0x46,0xFF,0xF7,0xD9,0xFF,0x08,0xBD, ++0x2D,0xE9,0xF8,0x43,0x42,0xF2,0x36,0x00, ++0x02,0xF0,0x5C,0xFD,0x86,0xB2,0x42,0xF2, ++0x38,0x00,0x02,0xF0,0x57,0xFD,0x85,0xB2, ++0x42,0xF2,0x3A,0x00,0x02,0xF0,0x52,0xFD, ++0x00,0x23,0x40,0xF6,0xFF,0x72,0x84,0xB2, ++0x00,0x93,0x42,0xF2,0x30,0x01,0x30,0x46, ++0xFF,0xF7,0xBE,0xFF,0x00,0x23,0x42,0xF2, ++0x08,0x08,0x00,0x93,0x0C,0x23,0x0F,0x22, ++0x41,0x46,0x30,0x46,0xFF,0xF7,0xB4,0xFF, ++0x00,0x23,0x01,0x22,0x00,0x93,0x42,0xF2, ++0x0E,0x01,0x28,0x46,0xFF,0xF7,0xAC,0xFF, ++0x04,0x23,0x42,0xF2,0x04,0x06,0x00,0x93, ++0x01,0x23,0x03,0x22,0x31,0x46,0x28,0x46, ++0xFF,0xF7,0xA2,0xFF,0x03,0x23,0x42,0xF2, ++0x32,0x07,0x00,0x93,0x1A,0x46,0x39,0x46, ++0x28,0x46,0xFF,0xF7,0x99,0xFF,0x0A,0x23, ++0x03,0x22,0x00,0x93,0x05,0x23,0xB1,0x1D, ++0x28,0x46,0xFF,0xF7,0x91,0xFF,0x07,0x23, ++0x0F,0x22,0x00,0x93,0x39,0x46,0x28,0x46, ++0xFF,0xF7,0x8A,0xFF,0x04,0x23,0xB7,0x1C, ++0x00,0x93,0x0B,0x23,0x03,0x22,0x39,0x46, ++0x28,0x46,0xFF,0xF7,0x81,0xFF,0x0A,0x23, ++0x03,0x22,0x00,0x93,0x0D,0x23,0x39,0x46, ++0x28,0x46,0xFF,0xF7,0x79,0xFF,0x04,0xF0, ++0x01,0x01,0x05,0xF4,0x00,0x40,0x08,0x23, ++0x03,0x22,0x00,0xEB,0x41,0x00,0x00,0x93, ++0x00,0x23,0x31,0x46,0x80,0xB2,0xFF,0xF7, ++0x6B,0xFF,0x01,0x23,0x43,0xF6,0xFF,0x72, ++0x00,0x93,0x42,0xF2,0x34,0x01,0x20,0x46, ++0xFF,0xF7,0x62,0xFF,0x06,0x23,0x01,0x22, ++0x00,0x93,0x0F,0x23,0x41,0x46,0x20,0x46, ++0xFF,0xF7,0x5A,0xFF,0xBD,0xE8,0xF8,0x83, ++0x71,0x52,0x56,0x93,0x5B,0x48,0x57,0x5F, ++0x43,0x46,0x47,0x5D,0x63,0x68,0x69,0x70, ++0x28,0x30,0x78,0x25,0x78,0x29,0x64,0x61, ++0x74,0x61,0x28,0x25,0x6C,0x78,0x29,0x6D, ++0x69,0x75,0x28,0x25,0x6C,0x78,0x29,0x0A, ++0x00,0x00,0x00,0x00,0x6D,0x61,0x67,0x69, ++0x63,0x28,0x25,0x6C,0x78,0x29,0x6E,0x6F, ++0x77,0x28,0x25,0x6C,0x78,0x29,0x00,0x00, ++0x64,0x61,0x74,0x61,0x28,0x25,0x6C,0x78, ++0x29,0x6E,0x6F,0x77,0x28,0x25,0x6C,0x78, ++0x29,0x00,0x00,0x00,0x6D,0x69,0x75,0x28, ++0x25,0x6C,0x78,0x29,0x6E,0x6F,0x77,0x28, ++0x25,0x6C,0x78,0x29,0x00,0x00,0x00,0x00, ++0x63,0x68,0x6B,0x73,0x75,0x6D,0x28,0x25, ++0x6C,0x78,0x29,0x6E,0x6F,0x77,0x28,0x25, ++0x6C,0x78,0x29,0x0A,0x00,0x00,0x00,0x00, ++0x63,0x68,0x69,0x70,0x28,0x25,0x6C,0x78, ++0x29,0x6E,0x6F,0x77,0x28,0x25,0x6C,0x78, ++0x29,0x0A,0x00,0x00,0x63,0x68,0x69,0x70, ++0x28,0x25,0x78,0x29,0x64,0x61,0x74,0x61, ++0x28,0x25,0x78,0x29,0x61,0x64,0x64,0x72, ++0x28,0x25,0x6C,0x78,0x29,0x0A,0x00,0x00, ++0x53,0x65,0x74,0x5F,0x68,0x77,0x5F,0x63, ++0x6F,0x6E,0x66,0x69,0x67,0x28,0x25,0x78, ++0x29,0x00,0x00,0x00,0x64,0x6F,0x6E,0x65, ++0x0A,0x00,0x00,0x00,0x66,0x61,0x69,0x6C, ++0x0A,0x00,0x00,0x00,0x2D,0xE9,0xF0,0x41, ++0x04,0x00,0x0F,0x46,0x02,0xD1,0x01,0x20, ++0xBD,0xE8,0xF0,0x81,0x01,0x25,0x00,0x26, ++0x4D,0xE0,0x41,0xF2,0xB0,0x50,0x87,0x42, ++0x00,0xD2,0x38,0x46,0x3F,0x1A,0x31,0xE0, ++0x21,0x78,0x63,0x78,0x29,0x44,0x72,0x18, ++0x19,0x44,0xA3,0x78,0x0A,0x44,0x19,0x44, ++0xE3,0x78,0x0A,0x44,0x19,0x44,0x23,0x79, ++0x0A,0x44,0x19,0x44,0x63,0x79,0x0A,0x44, ++0x19,0x44,0xA3,0x79,0x0A,0x44,0x19,0x44, ++0xE3,0x79,0x0A,0x44,0x19,0x44,0x23,0x7A, ++0x0A,0x44,0x19,0x44,0x63,0x7A,0x0A,0x44, ++0x19,0x44,0xA3,0x7A,0x0A,0x44,0x19,0x44, ++0xE3,0x7A,0x0A,0x44,0x19,0x44,0x23,0x7B, ++0x0A,0x44,0x19,0x44,0x63,0x7B,0x0A,0x44, ++0x19,0x44,0xA3,0x7B,0x0A,0x44,0x19,0x44, ++0xE3,0x7B,0x0A,0x44,0x10,0x34,0x5D,0x18, ++0x56,0x19,0x10,0x38,0x10,0x28,0xCB,0xD2, ++0x28,0xB1,0x14,0xF8,0x01,0x1B,0x40,0x1E, ++0x0D,0x44,0x2E,0x44,0xF8,0xE7,0x4F,0xF6, ++0xF1,0x78,0x28,0x46,0x41,0x46,0x0A,0xF0, ++0xCC,0xED,0x0D,0x46,0x41,0x46,0x30,0x46, ++0x0A,0xF0,0xC6,0xED,0x0E,0x46,0x00,0x2F, ++0xAF,0xD1,0x45,0xEA,0x06,0x40,0xA7,0xE7, ++0xD8,0x48,0x10,0xB5,0x00,0x68,0x03,0xF0, ++0x3D,0xFC,0xBD,0xE8,0x10,0x40,0x37,0x20, ++0xFF,0xF7,0xC4,0xBA,0xD4,0x48,0xB0,0xF8, ++0xB4,0x11,0x41,0xF4,0x80,0x61,0xA0,0xF8, ++0xB4,0x11,0x01,0x88,0x41,0xF4,0x80,0x61, ++0x20,0xF8,0x40,0x1B,0x01,0x88,0x41,0xF4, ++0x80,0x61,0x01,0x80,0x70,0x47,0xCC,0x48, ++0xB0,0xF8,0xB4,0x11,0x21,0xF4,0x80,0x61, ++0xA0,0xF8,0xB4,0x11,0x01,0x88,0x21,0xF4, ++0x80,0x61,0x20,0xF8,0x40,0x1B,0x01,0x88, ++0x21,0xF4,0x80,0x61,0x01,0x80,0x70,0x47, ++0x10,0xB5,0x04,0x46,0x02,0xF0,0xEE,0xFC, ++0x00,0x28,0x04,0xD0,0x20,0x46,0xBD,0xE8, ++0x10,0x40,0x02,0xF0,0xB5,0xBE,0x10,0xBD, ++0x10,0xB5,0xAF,0xF2,0x1B,0x00,0xBD,0x49, ++0xBF,0x4A,0x08,0x60,0xBD,0x49,0xBC,0x48, ++0x05,0xC1,0xBF,0x49,0xBD,0x4A,0xC1,0xE9, ++0x00,0x20,0xBE,0xA0,0xFE,0xF7,0x02,0xFE, ++0x01,0x22,0x37,0x20,0x11,0x46,0xFF,0xF7, ++0xEE,0xFA,0x00,0x23,0xAF,0xF2,0x9F,0x02, ++0xBD,0xE8,0x10,0x40,0x37,0x20,0x19,0x46, ++0xFF,0xF7,0xD6,0xBA,0x2D,0xE9,0xF0,0x47, ++0x4F,0xF4,0x80,0x40,0xAB,0x49,0xDF,0xF8, ++0xE0,0x82,0xC1,0xF8,0x00,0x80,0xB7,0x49, ++0x08,0x60,0xAF,0xF2,0x6B,0x00,0xA9,0x49, ++0xAB,0x4A,0x08,0x60,0xA9,0x49,0xA8,0x48, ++0x05,0xC1,0xAB,0x49,0xA9,0x4A,0xC1,0xE9, ++0x00,0x20,0xB1,0x48,0x03,0xF0,0x7C,0xFC, ++0xAF,0x49,0x40,0x46,0x03,0xF0,0x5C,0xFC, ++0x40,0x46,0x03,0xF0,0x6D,0xFC,0x01,0x22, ++0x37,0x20,0x11,0x46,0xFF,0xF7,0xBF,0xFA, ++0x00,0x23,0xAF,0xF2,0xFB,0x02,0x37,0x20, ++0x19,0x46,0xFF,0xF7,0xA9,0xFA,0xA7,0x4E, ++0xB0,0x8A,0x40,0xF4,0x00,0x40,0xB0,0x82, ++0xA5,0x48,0xB0,0xF8,0xCC,0x1B,0x21,0xF4, ++0x80,0x51,0xA0,0xF8,0xCC,0x1B,0x01,0x88, ++0x21,0xF4,0x80,0x51,0x01,0x80,0x41,0xF2, ++0x03,0x40,0x30,0x82,0x42,0xF2,0x84,0x00, ++0xB0,0x80,0x48,0xF2,0x03,0x00,0xA6,0xF8, ++0x40,0x00,0x4F,0xF4,0xC0,0x40,0xA6,0xF8, ++0x44,0x00,0x46,0xF6,0xC3,0x30,0x30,0x80, ++0x4F,0xF4,0x7A,0x7A,0x54,0x46,0x50,0x46, ++0xFE,0xF7,0xB4,0xFC,0x46,0xF6,0xC3,0x10, ++0x30,0x80,0x4F,0xF4,0xFA,0x60,0xFE,0xF7, ++0xAD,0xFC,0x4F,0xF0,0x01,0x09,0xA6,0xF8, ++0x00,0x90,0xA6,0xF5,0x60,0x66,0x20,0x46, ++0xFE,0xF7,0xA4,0xFC,0x00,0x24,0x42,0xF2, ++0x10,0x75,0xB6,0xF8,0x60,0x7E,0x20,0x46, ++0x64,0x1C,0xA8,0x42,0x04,0xD8,0x01,0x20, ++0xFE,0xF7,0x98,0xFC,0xF8,0x07,0xF4,0xD0, ++0x68,0x20,0xA6,0xF8,0x00,0x0C,0x02,0x20, ++0xA6,0xF8,0x04,0x0C,0x40,0xF2,0xFF,0x10, ++0xA6,0xF8,0x24,0x0E,0xFF,0x20,0xA6,0xF8, ++0x24,0x0E,0x50,0x46,0xFE,0xF7,0x86,0xFC, ++0x4C,0x46,0xA6,0xF8,0x78,0x9E,0x00,0x27, ++0xA6,0xF8,0x78,0x7E,0x38,0x46,0x03,0xE0, ++0x01,0x46,0x40,0x1C,0xA9,0x42,0x03,0xD8, ++0xB6,0xF8,0x78,0x1E,0x89,0x07,0xF7,0xD5, ++0x06,0xF6,0x04,0x66,0x42,0xF6,0x84,0x00, ++0x30,0x80,0x4B,0xF2,0x40,0x00,0x30,0x81, ++0x49,0xF2,0x03,0x51,0xB1,0x81,0xC1,0x1C, ++0x31,0x81,0x30,0x81,0xFF,0xF7,0x12,0xFF, ++0x6E,0x4D,0xA8,0x79,0x00,0xF0,0xFE,0x00, ++0xA8,0x71,0xA8,0x79,0x40,0xF0,0x01,0x00, ++0xA8,0x71,0xFF,0xF7,0x18,0xFF,0xE8,0x88, ++0x40,0xF4,0x00,0x40,0xE8,0x80,0x03,0xF0, ++0xE7,0xF8,0x6F,0x81,0xEF,0x81,0x88,0xF8, ++0x2F,0x40,0x65,0x48,0x60,0x49,0x00,0x68, ++0xC8,0xF8,0x38,0x01,0x00,0xF5,0x00,0x50, ++0x08,0x62,0x05,0xF8,0xFA,0x7C,0xE8,0x7F, ++0x40,0xF0,0x08,0x00,0xE8,0x77,0x60,0x20, ++0x05,0xF8,0xF9,0x0C,0x05,0xF8,0x3A,0x7C, ++0x5C,0x48,0x04,0x70,0xBD,0xE8,0xF0,0x87, ++0x5B,0x48,0x01,0x68,0x21,0xF4,0x00,0x01, ++0x01,0x60,0x70,0x47,0x58,0x48,0x01,0x68, ++0x41,0xF4,0x00,0x01,0x01,0x60,0x70,0x47, ++0x2D,0xE9,0xF0,0x41,0x06,0x46,0x3F,0x48, ++0x00,0x27,0x0D,0x46,0x00,0x68,0xD0,0xF8, ++0x3C,0x41,0xE1,0x68,0x67,0x60,0x27,0x61, ++0x31,0xB1,0xA2,0x68,0x1A,0xB1,0x20,0x6A, ++0x01,0x44,0x09,0xF0,0xDE,0xEB,0xE7,0x60, ++0x44,0x49,0xA0,0x68,0x09,0x68,0x42,0x19, ++0x8A,0x42,0x00,0xD9,0x0D,0x1A,0x21,0x6A, ++0x2A,0x46,0x08,0x44,0x31,0x46,0x09,0xF0, ++0xD0,0xEB,0xA0,0x68,0x28,0x44,0xA0,0x60, ++0x28,0x46,0xBD,0xE8,0xF0,0x81,0x2D,0x4A, ++0x70,0xB5,0x00,0x26,0x12,0x68,0xD2,0xF8, ++0x3C,0x41,0x23,0x69,0x62,0x68,0xD2,0x1A, ++0x8A,0x42,0x01,0xD9,0x0D,0x46,0x01,0xE0, ++0x15,0x46,0x66,0x60,0x5D,0xB1,0x21,0x6A, ++0x2A,0x46,0x19,0x44,0x09,0xF0,0xB4,0xEB, ++0x60,0x68,0x08,0xB9,0x26,0x61,0x02,0xE0, ++0x20,0x69,0x28,0x44,0x20,0x61,0x28,0x46, ++0x70,0xBD,0x70,0x47,0x31,0x49,0x2A,0x48, ++0x09,0x78,0xD0,0xF8,0x3C,0x01,0x00,0x29, ++0x04,0xD0,0x00,0x21,0x41,0x60,0x01,0x61, ++0x01,0x77,0x81,0x60,0x70,0x47,0x70,0x47, ++0x16,0x49,0x00,0x20,0x09,0x68,0xD1,0xF8, ++0x3C,0x11,0x08,0x77,0x70,0x47,0x13,0x48, ++0x00,0x68,0xD0,0xF8,0x3C,0x01,0x00,0x7F, ++0x70,0x47,0x10,0x48,0x00,0x68,0xD0,0xF8, ++0x3C,0x01,0x80,0x68,0x08,0xB1,0x00,0x20, ++0x70,0x47,0x01,0x20,0x70,0x47,0x0B,0x49, ++0x09,0x68,0xD1,0xF8,0x3C,0x11,0x08,0x62, ++0x70,0x47,0x08,0x49,0x09,0x68,0xC1,0xF8, ++0x38,0x01,0x70,0x47,0x07,0x48,0x10,0xB5, ++0x01,0x68,0x11,0xB1,0x03,0x48,0x00,0x68, ++0x88,0x47,0x18,0x49,0xFF,0x20,0x08,0x80, ++0x08,0x81,0x10,0xBD,0x74,0xD4,0x02,0x20, ++0x18,0x7C,0x00,0x25,0x80,0xD4,0x02,0x20, ++0xD5,0x67,0x03,0x20,0x8C,0xD4,0x02,0x20, ++0x09,0x68,0x03,0x20,0x53,0x67,0x03,0x20, ++0x84,0xD4,0x02,0x20,0x4D,0x44,0x72,0x76, ++0x5F,0x55,0x53,0x42,0x5F,0x49,0x6E,0x69, ++0x74,0x5F,0x62,0x6F,0x6F,0x74,0x0A,0x00, ++0x00,0xD1,0x02,0x20,0xB4,0x04,0x03,0x20, ++0x48,0xD2,0x02,0x20,0x00,0x3E,0x00,0x25, ++0x94,0x72,0x00,0x25,0xFA,0x40,0x00,0x25, ++0xAC,0x04,0x03,0x20,0xC0,0x04,0x03,0x20, ++0x20,0x0C,0x30,0x25,0x14,0x3C,0x30,0x25, ++0x10,0xB5,0x03,0xF0,0x15,0xFB,0x04,0x46, ++0x20,0x20,0x05,0xF0,0xC4,0xFD,0xB4,0x21, ++0x20,0x46,0x09,0xF0,0xC2,0xEB,0x03,0xF0, ++0x9F,0xFB,0x03,0xF0,0x9A,0xFB,0xC4,0xF8, ++0x98,0x00,0x4F,0xF4,0x00,0x71,0x09,0xF0, ++0x96,0xEB,0x05,0xF0,0x31,0xFB,0x08,0xB1, ++0xFF,0x48,0x10,0xBD,0x05,0xF0,0xF9,0xF8, ++0x10,0xB1,0xFD,0x48,0x40,0x1E,0x10,0xBD, ++0xBD,0xE8,0x10,0x40,0x05,0xF0,0xC9,0xBB, ++0xDA,0xE7,0x70,0xB5,0x05,0x46,0x0C,0x46, ++0x03,0xF0,0xEE,0xFA,0x41,0x7C,0x0F,0x22, ++0x29,0x70,0x81,0x1C,0x20,0x46,0x09,0xF0, ++0x10,0xEB,0x00,0x20,0x70,0xBD,0x2D,0xE9, ++0xF0,0x41,0x04,0x46,0x00,0xF5,0x00,0x75, ++0x05,0xF0,0xA5,0xFB,0xEE,0x4E,0x35,0x3E, ++0x10,0xB1,0x30,0x46,0xBD,0xE8,0xF0,0x81, ++0x0E,0x21,0x04,0xF1,0x24,0x00,0x05,0xF0, ++0x50,0xFB,0x07,0x46,0x04,0xF1,0x20,0x00, ++0x09,0xF0,0x3A,0xEC,0x01,0x46,0x38,0x46, ++0x81,0x42,0x4F,0xF4,0x00,0x77,0x04,0xD0, ++0x39,0x46,0x20,0x46,0x05,0xF0,0x7F,0xFD, ++0xE7,0xE7,0x28,0x1D,0x4F,0xF4,0xFE,0x71, ++0x05,0xF0,0x3B,0xFB,0x06,0x46,0x28,0x46, ++0x09,0xF0,0x26,0xEC,0xB0,0x42,0x06,0xD0, ++0x39,0x46,0x28,0x46,0x05,0xF0,0x6F,0xFD, ++0xD9,0x48,0x34,0x38,0xD6,0xE7,0x20,0x46, ++0x05,0xF0,0x6A,0xFB,0x28,0x46,0x05,0xF0, ++0x22,0xFB,0x00,0x20,0xCE,0xE7,0x2D,0xE9, ++0xF0,0x4F,0x05,0x46,0x85,0xB0,0x03,0xF0, ++0xA3,0xFA,0x04,0x46,0xD0,0xF8,0x88,0x00, ++0x4F,0xF4,0x00,0x78,0x03,0x90,0x05,0xF5, ++0x00,0x70,0xD4,0xF8,0x84,0xA0,0x41,0x46, ++0x02,0x90,0xCC,0x48,0x01,0x90,0x09,0xF0, ++0x26,0xEB,0x01,0x9E,0x0F,0x21,0xA0,0x1C, ++0x09,0xF0,0x20,0xEB,0x2A,0x7C,0xA0,0x1C, ++0x05,0xF1,0x11,0x01,0x09,0xF0,0xB0,0xEA, ++0x28,0x7C,0x60,0x74,0x05,0xF1,0x24,0x00, ++0x41,0x78,0x02,0x78,0x42,0xEA,0x01,0x20, ++0xA0,0x87,0x05,0xF1,0x26,0x00,0x41,0x78, ++0x02,0x78,0x42,0xEA,0x01,0x20,0x60,0x87, ++0x05,0xF1,0x28,0x00,0x41,0x78,0x02,0x78, ++0x42,0xEA,0x01,0x20,0x20,0x87,0x05,0xF1, ++0x2A,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0xE0,0x86,0x05,0xF1,0x30,0x00, ++0x41,0x78,0x02,0x78,0x42,0xEA,0x01,0x20, ++0xE0,0x87,0x05,0xF1,0x2C,0x00,0x07,0x46, ++0x09,0xF0,0xCA,0xEB,0x20,0x64,0x05,0xF1, ++0x32,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0x10,0x22,0xA4,0xF8,0x44,0x00, ++0x05,0xF1,0x40,0x01,0x04,0xF1,0x46,0x00, ++0x09,0xF0,0x76,0xEA,0x10,0x22,0x05,0xF1, ++0x50,0x01,0x04,0xF1,0x56,0x00,0x09,0xF0, ++0x70,0xEA,0x38,0x46,0x09,0xF0,0xB0,0xEB, ++0x00,0xF0,0x01,0x00,0x04,0xF8,0x80,0x0F, ++0x95,0xF8,0x60,0x00,0x60,0x70,0x05,0xF1, ++0x32,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0x03,0xF0,0xBA,0xFA,0x28,0x46, ++0x05,0xF0,0xEE,0xFA,0x02,0x98,0x41,0x7B, ++0x00,0x7B,0x40,0xEA,0x01,0x22,0x02,0x98, ++0xC1,0x7B,0x83,0x7B,0x43,0xEA,0x01,0x20, ++0x02,0x99,0x42,0x43,0xA0,0x69,0x10,0x32, ++0x09,0xF0,0x4A,0xEA,0x02,0x98,0x05,0xF0, ++0x96,0xFA,0x03,0xF0,0x4E,0xFC,0x03,0xF0, ++0xD9,0xFF,0x14,0xF8,0x80,0x19,0x05,0xF5, ++0x80,0x60,0x04,0x90,0x61,0xB9,0x8C,0x49, ++0x00,0x20,0x42,0x46,0x01,0xEB,0x80,0x03, ++0x21,0xF8,0x20,0x00,0x58,0x80,0x40,0x1C, ++0x80,0xB2,0x90,0x42,0xF6,0xD3,0x10,0xE0, ++0x01,0x46,0x85,0x48,0x4F,0xF4,0x00,0x62, ++0x09,0xF0,0x2A,0xEA,0x82,0x48,0x94,0xF8, ++0x81,0x10,0x80,0x89,0x88,0x42,0x04,0xD0, ++0x7D,0x48,0x35,0x38,0x05,0xB0,0xBD,0xE8, ++0xF0,0x8F,0xA0,0x7C,0xFF,0x28,0x14,0xD0, ++0x94,0xF8,0x70,0x10,0x01,0x23,0x03,0x9A, ++0x88,0x40,0x79,0x49,0x09,0x89,0x00,0x93, ++0x53,0x46,0x08,0x44,0x00,0x21,0x80,0xB2, ++0x03,0xF0,0xEE,0xFA,0x28,0xB9,0x03,0x99, ++0x42,0x46,0x01,0x98,0x09,0xF0,0x08,0xEA, ++0x02,0xE0,0x30,0x46,0x05,0xF0,0xF8,0xFB, ++0x4F,0xF0,0x00,0x09,0x4F,0x46,0x60,0x8F, ++0x4F,0xF4,0x00,0x7B,0x58,0x45,0x03,0xD1, ++0x10,0x20,0xA0,0x87,0x03,0x20,0x05,0xE0, ++0x4F,0xF4,0x00,0x60,0x60,0x87,0xC0,0x10, ++0xA0,0x87,0x0A,0x20,0xE0,0x87,0x03,0xF0, ++0xF8,0xFB,0x03,0xF0,0x83,0xFF,0x20,0x8B, ++0x40,0xF4,0x80,0x50,0x20,0x83,0x01,0x23, ++0x94,0xF8,0x70,0x00,0x00,0x21,0x03,0x9A, ++0x00,0x93,0x53,0x46,0x07,0xFA,0x00,0xF0, ++0x1F,0xFA,0x80,0xF8,0x40,0x46,0x03,0xF0, ++0xBB,0xFA,0x06,0x46,0x9A,0xF8,0x00,0x00, ++0xFF,0x28,0x7E,0xD1,0x24,0x35,0x68,0x78, ++0x29,0x78,0x41,0xEA,0x00,0x20,0xA0,0x87, ++0xE8,0x78,0xA9,0x78,0x41,0xEA,0x00,0x20, ++0x60,0x87,0x68,0x7B,0x29,0x7B,0x24,0x3D, ++0x41,0xEA,0x00,0x20,0xE0,0x87,0x03,0xF0, ++0xCC,0xFB,0x03,0xF0,0x57,0xFF,0x20,0x8B, ++0x20,0xF4,0x80,0x50,0x20,0x83,0x38,0x46, ++0x05,0xF0,0x80,0xFB,0x06,0x00,0x7E,0xD1, ++0x61,0x8F,0x03,0x98,0x09,0xF0,0x1E,0xEA, ++0x03,0x98,0x5E,0x46,0x5A,0x46,0x29,0x46, ++0x09,0xF0,0xAE,0xE9,0xA1,0x8F,0x50,0x46, ++0x09,0xF0,0x14,0xEA,0xFF,0x20,0x8A,0xF8, ++0x00,0x00,0x00,0x20,0x8A,0xF8,0x01,0x00, ++0x60,0x8F,0xB0,0x42,0x03,0xD1,0x10,0x20, ++0xA0,0x87,0x03,0x20,0x05,0xE0,0x4F,0xF4, ++0x00,0x60,0x60,0x87,0xC0,0x10,0xA0,0x87, ++0x0A,0x20,0xE0,0x87,0x03,0xF0,0x9D,0xFB, ++0x03,0xF0,0x28,0xFF,0x20,0x8B,0x40,0xF4, ++0x80,0x50,0x20,0x83,0x01,0x23,0x03,0x9A, ++0x00,0x21,0x00,0x93,0x53,0x46,0x40,0x46, ++0x04,0xF0,0xA0,0xFB,0x24,0x35,0x06,0x46, ++0x68,0x78,0x29,0x78,0x41,0xEA,0x00,0x20, ++0xA0,0x87,0xE8,0x78,0xA9,0x78,0x41,0xEA, ++0x00,0x20,0x60,0x87,0x68,0x7B,0x29,0x7B, ++0x24,0x3D,0x41,0xEA,0x00,0x20,0xE0,0x87, ++0x03,0xF0,0x7B,0xFB,0x03,0xF0,0x06,0xFF, ++0x20,0x8B,0x20,0xF4,0x80,0x50,0x20,0x83, ++0x00,0x2E,0x51,0xD1,0x61,0x8F,0x03,0x98, ++0x09,0xF0,0xD0,0xE9,0xDD,0xE9,0x02,0x10, ++0x4F,0xF4,0x00,0x72,0x09,0xF0,0x60,0xE9, ++0xDF,0xF8,0x74,0xB0,0x01,0x23,0x00,0x93, ++0x53,0x46,0xBB,0xF8,0x04,0x00,0x40,0x44, ++0x00,0xE0,0x47,0xE0,0x03,0x9A,0x00,0x21, ++0x04,0xF0,0x6C,0xFB,0x06,0x00,0x37,0xD1, ++0x61,0x8F,0x03,0x98,0x09,0xF0,0xB6,0xE9, ++0x01,0x99,0x4F,0xF4,0x00,0x72,0x03,0x98, ++0x09,0xF0,0x46,0xE9,0x01,0x23,0x03,0x9A, ++0x00,0x93,0x00,0x21,0xBB,0xF8,0x08,0x00, ++0x53,0x46,0x40,0x44,0x04,0xF0,0x56,0xFB, ++0x06,0x00,0x21,0xD1,0x00,0xE0,0x1F,0xE0, ++0x94,0xF8,0x80,0x00,0x01,0x28,0x1F,0xD1, ++0x61,0x8F,0x03,0x98,0x09,0xF0,0x9A,0xE9, ++0xDD,0xE9,0x03,0x01,0x4F,0xF4,0x00,0x62, ++0x09,0xF0,0x2A,0xE9,0x06,0xE0,0x00,0x00, ++0x3A,0x00,0x00,0x80,0x00,0x00,0x10,0x80, ++0x00,0x0D,0x03,0x20,0xBB,0xF8,0x0C,0x00, ++0x01,0x23,0x03,0x99,0x52,0x46,0x40,0x44, ++0x03,0xF0,0xE2,0xF9,0x06,0x00,0x03,0xD0, ++0x38,0x46,0x05,0xF0,0xE7,0xFA,0x05,0xE0, ++0x09,0xF1,0x01,0x00,0xC0,0xB2,0x02,0x28, ++0x81,0x46,0x04,0xD0,0x7F,0x1C,0xBF,0xB2, ++0x0A,0x2F,0xFF,0xF4,0x08,0xAF,0x24,0x35, ++0x68,0x78,0x29,0x78,0x41,0xEA,0x00,0x20, ++0xA0,0x87,0xE8,0x78,0xA9,0x78,0x41,0xEA, ++0x00,0x20,0x60,0x87,0x68,0x7B,0x29,0x7B, ++0x41,0xEA,0x00,0x20,0xE0,0x87,0x03,0xF0, ++0x00,0xFB,0x03,0xF0,0x8B,0xFE,0x20,0x8B, ++0x20,0xF4,0x80,0x50,0x20,0x83,0x5F,0xEA, ++0x09,0x00,0x06,0xD0,0x01,0x28,0x06,0xD0, ++0x02,0x28,0x00,0xD1,0x00,0x26,0x30,0x46, ++0xC4,0xE6,0xFF,0x4E,0xFB,0xE7,0xFE,0x4E, ++0x76,0x1C,0xF8,0xE7,0x2D,0xE9,0xF0,0x4F, ++0x83,0x46,0x85,0xB0,0x03,0xF0,0xB4,0xF8, ++0xD0,0xE9,0x21,0x75,0x04,0x46,0x05,0x20, ++0x04,0x97,0x01,0x90,0x00,0x26,0x05,0xF0, ++0xDB,0xF8,0x01,0x98,0x01,0x23,0x00,0x93, ++0x00,0x21,0x04,0x9B,0x2A,0x46,0x06,0xFA, ++0x00,0xF8,0x40,0x46,0x03,0xF0,0xA8,0xF9, ++0x00,0x28,0x7D,0xD1,0x38,0x78,0xFF,0x28, ++0xFB,0xD1,0xF8,0x78,0xB9,0x78,0x41,0xEA, ++0x00,0x20,0x01,0x28,0x74,0xD8,0x28,0x46, ++0x05,0xF0,0x59,0xF9,0x00,0x28,0xF0,0xD1, ++0x0E,0x21,0x05,0xF1,0x24,0x00,0x05,0xF0, ++0x08,0xF9,0x81,0x46,0x05,0xF1,0x20,0x00, ++0x09,0xF0,0xF2,0xE9,0x48,0x45,0xE4,0xD1, ++0xF8,0x78,0xB9,0x78,0x41,0xEA,0x00,0x20, ++0x00,0xF0,0xFF,0x09,0x28,0x46,0x05,0xF0, ++0x37,0xF9,0x4F,0xF4,0x00,0x72,0x29,0x46, ++0x58,0x46,0x09,0xF0,0x9E,0xE8,0x05,0xF1, ++0x26,0x00,0x41,0x78,0x02,0x78,0x42,0xEA, ++0x01,0x20,0x60,0x87,0x05,0xF1,0x24,0x00, ++0x41,0x78,0x02,0x78,0x42,0xEA,0x01,0x20, ++0xA0,0x87,0x05,0xF1,0x28,0x00,0x41,0x78, ++0x02,0x78,0x42,0xEA,0x01,0x20,0x20,0x87, ++0x05,0xF1,0x2A,0x00,0x41,0x78,0x02,0x78, ++0x42,0xEA,0x01,0x20,0xE0,0x86,0x05,0xF1, ++0x30,0x00,0x42,0x78,0x01,0x78,0x41,0xEA, ++0x02,0x20,0xE0,0x87,0x28,0x7C,0x60,0x74, ++0x05,0xF1,0x2C,0x00,0x82,0x46,0x09,0xF0, ++0xB8,0xE9,0x20,0x64,0x10,0x22,0x05,0xF1, ++0x40,0x01,0x04,0xF1,0x46,0x00,0x09,0xF0, ++0x6C,0xE8,0x10,0x22,0x05,0xF1,0x50,0x01, ++0x04,0xF1,0x56,0x00,0x09,0xF0,0x64,0xE8, ++0x50,0x46,0x09,0xF0,0xA6,0xE9,0x00,0xF0, ++0x01,0x00,0x84,0xF8,0x80,0x00,0x95,0xF8, ++0x60,0x00,0x84,0xF8,0x81,0x00,0x03,0xF0, ++0x60,0xFA,0x03,0xF0,0xFF,0xFC,0xDF,0xF8, ++0xDC,0xA2,0x01,0x23,0x03,0x95,0x2A,0x46, ++0x00,0x93,0xBA,0xF8,0x04,0x10,0x04,0x9B, ++0x01,0xEB,0x08,0x00,0x00,0x21,0x00,0xE0, ++0x33,0xE0,0x03,0xF0,0x25,0xF9,0x80,0xBB, ++0x28,0x1D,0x4F,0xF4,0xFE,0x71,0x05,0xF0, ++0x94,0xF8,0x02,0x90,0x03,0x98,0x09,0xF0, ++0x80,0xE9,0x01,0x46,0x02,0x98,0x81,0x42, ++0x23,0xD1,0x03,0x98,0x05,0xF0,0x83,0xF8, ++0x03,0x99,0x4F,0xF4,0x00,0x72,0x0B,0xF5, ++0x00,0x70,0x09,0xF0,0x2E,0xE8,0x94,0xF8, ++0x80,0x00,0x01,0x28,0x12,0xD1,0xBA,0xF8, ++0x0C,0x10,0x04,0x9A,0x01,0x23,0x01,0xEB, ++0x08,0x00,0x29,0x46,0x03,0xF0,0xEF,0xF8, ++0x40,0xB9,0x03,0x99,0x4F,0xF4,0x00,0x62, ++0x0B,0xF5,0x80,0x60,0x09,0xF0,0x18,0xE8, ++0x00,0x20,0xF3,0xE5,0xB9,0xF1,0x00,0x0F, ++0x04,0xD1,0x76,0x1C,0xB6,0xB2,0x40,0x2E, ++0xFF,0xF4,0x39,0xAF,0x92,0x48,0x80,0x1D, ++0xE8,0xE5,0x2D,0xE9,0xFF,0x4F,0x83,0x46, ++0x85,0xB0,0x17,0x46,0x1E,0x46,0xDD,0xF8, ++0x48,0xA0,0x02,0xF0,0xD9,0xFF,0x81,0x46, ++0xD0,0xF8,0x98,0x00,0x4F,0xF0,0x00,0x08, ++0x10,0x30,0x45,0x46,0x59,0x46,0x05,0xF0, ++0xA4,0xFA,0x04,0x00,0x02,0xD1,0x86,0x48, ++0x0A,0x38,0x70,0xE0,0x28,0x46,0x6D,0x1C, ++0x50,0x45,0x02,0xD0,0x04,0xF1,0x08,0x00, ++0xF0,0xE7,0xB9,0xF8,0x3A,0x00,0x40,0x0A, ++0x05,0xF0,0x89,0xFA,0x99,0xF8,0x70,0x10, ++0x08,0x44,0x00,0xF0,0xFF,0x0A,0x99,0xF8, ++0x80,0x00,0x01,0x28,0x03,0xD1,0xAA,0xF1, ++0x01,0x00,0x00,0xF0,0xFF,0x0A,0x01,0x20, ++0x00,0xFA,0x0A,0xF0,0x1F,0xFA,0x80,0xFB, ++0xAB,0xF1,0x01,0x00,0x80,0xB2,0x03,0x90, ++0x27,0xFA,0x0A,0xF0,0x80,0xB2,0x04,0x90, ++0x60,0x78,0x21,0x78,0x41,0xEA,0x00,0x25, ++0x00,0x20,0x1B,0xE0,0x60,0x78,0x6D,0x1C, ++0x22,0x78,0xAD,0xB2,0x42,0xEA,0x00,0x21, ++0xE0,0x78,0xA2,0x78,0x42,0xEA,0x00,0x20, ++0xA2,0x79,0x01,0x44,0xE0,0x79,0x42,0xEA, ++0x00,0x20,0x08,0x44,0xA8,0x42,0x30,0xD9, ++0x28,0x46,0x05,0xF0,0x7A,0xFA,0x00,0x28, ++0xE8,0xD0,0x6D,0x1C,0x09,0xF1,0x01,0x00, ++0xAD,0xB2,0x80,0xB2,0x04,0x99,0x81,0x46, ++0x88,0x42,0xF1,0xD9,0x6D,0x1E,0x4D,0xE0, ++0x60,0x78,0x22,0x78,0x42,0xEA,0x00,0x21, ++0xE0,0x78,0xA2,0x78,0x42,0xEA,0x00,0x20, ++0xA2,0x79,0x01,0x44,0xE0,0x79,0x42,0xEA, ++0x00,0x20,0x08,0x44,0x0F,0xE0,0x60,0x78, ++0x6D,0x1C,0x22,0x78,0xAD,0xB2,0x42,0xEA, ++0x00,0x21,0xE0,0x78,0xA2,0x78,0x42,0xEA, ++0x00,0x20,0xA2,0x79,0x01,0x44,0xE0,0x79, ++0x42,0xEA,0x00,0x20,0x08,0x44,0xA8,0x42, ++0x03,0xD8,0x4D,0x48,0x08,0x38,0x80,0x46, ++0x2B,0xE0,0x28,0x46,0x05,0xF0,0x45,0xFA, ++0x00,0x28,0xE4,0xD0,0x03,0x99,0x27,0xFA, ++0x0A,0xF0,0x07,0xEA,0x01,0x02,0x31,0x46, ++0xAB,0xEB,0x02,0x03,0x80,0xB2,0xB3,0x42, ++0x00,0xD2,0x19,0x46,0xCD,0xE9,0x00,0x21, ++0x89,0x46,0x61,0x79,0x03,0x46,0x22,0x79, ++0x06,0x98,0x42,0xEA,0x01,0x21,0x2A,0x46, ++0xC9,0xB2,0x05,0xF0,0x07,0xFC,0x5F,0xEA, ++0x00,0x08,0x0A,0xD1,0x06,0x98,0x6D,0x1C, ++0xA6,0xEB,0x09,0x06,0x00,0xEB,0x49,0x20, ++0x4F,0x44,0x06,0x90,0x00,0x2E,0xAD,0xB2, ++0xAE,0xD1,0x40,0x46,0x09,0xB0,0x2E,0xE5, ++0x2D,0xE9,0xFF,0x4F,0x83,0x46,0x85,0xB0, ++0x17,0x46,0x1E,0x46,0xDD,0xF8,0x48,0xA0, ++0x02,0xF0,0x1E,0xFF,0x81,0x46,0xD0,0xF8, ++0x98,0x00,0x4F,0xF0,0x00,0x08,0x10,0x30, ++0x45,0x46,0x59,0x46,0x05,0xF0,0xE9,0xF9, ++0x04,0x00,0x02,0xD1,0x28,0x48,0x0A,0x38, ++0x74,0xE0,0x28,0x46,0x6D,0x1C,0x50,0x45, ++0x02,0xD0,0x04,0xF1,0x08,0x00,0xF0,0xE7, ++0xB9,0xF8,0x3A,0x00,0x40,0x0A,0x05,0xF0, ++0xCE,0xF9,0x99,0xF8,0x70,0x10,0x08,0x44, ++0x00,0xF0,0xFF,0x0A,0x99,0xF8,0x80,0x00, ++0x01,0x28,0x03,0xD1,0xAA,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x0A,0x01,0x20,0x00,0xFA, ++0x0A,0xF0,0x1F,0xFA,0x80,0xFB,0xAB,0xF1, ++0x01,0x00,0x80,0xB2,0x03,0x90,0x27,0xFA, ++0x0A,0xF0,0x80,0xB2,0x04,0x90,0x60,0x78, ++0x21,0x78,0x41,0xEA,0x00,0x25,0x00,0x20, ++0x1B,0xE0,0x60,0x78,0x6D,0x1C,0x22,0x78, ++0xAD,0xB2,0x42,0xEA,0x00,0x21,0xE0,0x78, ++0xA2,0x78,0x42,0xEA,0x00,0x20,0xA2,0x79, ++0x01,0x44,0xE0,0x79,0x42,0xEA,0x00,0x20, ++0x08,0x44,0xA8,0x42,0x35,0xD9,0x28,0x46, ++0x05,0xF0,0xBF,0xF9,0x00,0x28,0xE8,0xD0, ++0x6D,0x1C,0x09,0xF1,0x01,0x00,0xAD,0xB2, ++0x80,0xB2,0x04,0x99,0x81,0x46,0x88,0x42, ++0xF1,0xD9,0x6D,0x1E,0x51,0xE0,0x00,0x00, ++0x23,0x00,0x00,0x80,0x00,0x0D,0x03,0x20, ++0x60,0x78,0x22,0x78,0x42,0xEA,0x00,0x21, ++0xE0,0x78,0xA2,0x78,0x42,0xEA,0x00,0x20, ++0xA2,0x79,0x01,0x44,0xE0,0x79,0x42,0xEA, ++0x00,0x20,0x08,0x44,0x0F,0xE0,0x60,0x78, ++0x6D,0x1C,0x22,0x78,0xAD,0xB2,0x42,0xEA, ++0x00,0x21,0xE0,0x78,0xA2,0x78,0x42,0xEA, ++0x00,0x20,0xA2,0x79,0x01,0x44,0xE0,0x79, ++0x42,0xEA,0x00,0x20,0x08,0x44,0xA8,0x42, ++0x02,0xD8,0xC7,0x48,0x80,0x46,0x2B,0xE0, ++0x28,0x46,0x05,0xF0,0x86,0xF9,0x00,0x28, ++0xE5,0xD0,0x03,0x99,0x27,0xFA,0x0A,0xF0, ++0x07,0xEA,0x01,0x02,0x31,0x46,0xAB,0xEB, ++0x02,0x03,0x80,0xB2,0xB3,0x42,0x00,0xD2, ++0x19,0x46,0xCD,0xE9,0x00,0x21,0x89,0x46, ++0x61,0x79,0x03,0x46,0x22,0x79,0x06,0x98, ++0x42,0xEA,0x01,0x21,0x2A,0x46,0xC9,0xB2, ++0x05,0xF0,0x5F,0xFA,0x5F,0xEA,0x00,0x08, ++0x0A,0xD1,0x06,0x98,0x6D,0x1C,0xA6,0xEB, ++0x09,0x06,0x00,0xEB,0x49,0x20,0x4F,0x44, ++0x06,0x90,0x00,0x2E,0xAD,0xB2,0xAF,0xD1, ++0x40,0x46,0x3F,0xE7,0x2D,0xE9,0xF0,0x41, ++0x07,0x46,0x02,0xF0,0x65,0xFE,0xD0,0xF8, ++0x98,0x00,0x00,0x26,0x39,0x46,0x10,0x30, ++0x05,0xF0,0x33,0xF9,0x04,0x00,0x02,0xD1, ++0xA7,0x4E,0xB6,0x1E,0x4E,0xE0,0x60,0x78, ++0x21,0x78,0x41,0xEA,0x00,0x25,0x0E,0xE0, ++0x28,0x46,0x05,0xF0,0x42,0xF9,0x40,0xB1, ++0x28,0x46,0x05,0xF0,0x3B,0xF8,0x06,0x00, ++0x03,0xD0,0x28,0x46,0x05,0xF0,0x42,0xF8, ++0x06,0x46,0x6D,0x1C,0xAD,0xB2,0x60,0x78, ++0x21,0x78,0xA2,0x78,0x41,0xEA,0x00,0x20, ++0xE1,0x78,0x42,0xEA,0x01,0x21,0xA2,0x79, ++0x01,0x44,0xE0,0x79,0x42,0xEA,0x00,0x20, ++0x08,0x44,0xA8,0x42,0xE0,0xD8,0x04,0xF1, ++0x08,0x00,0x39,0x46,0x05,0xF0,0x05,0xF9, ++0x04,0x00,0x23,0xD0,0x60,0x78,0x21,0x78, ++0x41,0xEA,0x00,0x25,0x0E,0xE0,0x28,0x46, ++0x05,0xF0,0x17,0xF9,0x40,0xB1,0x28,0x46, ++0x05,0xF0,0x10,0xF8,0x06,0x00,0x03,0xD0, ++0x28,0x46,0x05,0xF0,0x17,0xF8,0x06,0x46, ++0x6D,0x1C,0xAD,0xB2,0x60,0x78,0x22,0x78, ++0x42,0xEA,0x00,0x21,0xE0,0x78,0xA2,0x78, ++0x42,0xEA,0x00,0x20,0xA2,0x79,0x01,0x44, ++0xE0,0x79,0x42,0xEA,0x00,0x20,0x08,0x44, ++0xA8,0x42,0xE0,0xD8,0x30,0x46,0xBD,0xE8, ++0xF0,0x81,0x70,0xB5,0x02,0xF0,0x04,0xFE, ++0xD0,0xF8,0x98,0x40,0x05,0x46,0x0B,0x21, ++0x10,0x34,0x20,0x46,0x05,0xF0,0xD1,0xF8, ++0x08,0xB9,0x20,0x46,0x00,0xE0,0x08,0x30, ++0x41,0x78,0x00,0x78,0x40,0xEA,0x01,0x24, ++0x0C,0xE0,0x20,0x46,0x05,0xF0,0xE1,0xF8, ++0x30,0xB1,0x20,0x46,0x04,0xF0,0xDA,0xFF, ++0x10,0xB1,0x20,0x46,0x04,0xF0,0xE2,0xFF, ++0x64,0x1C,0xA4,0xB2,0xE8,0x8E,0xA0,0x42, ++0xEF,0xD8,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x02,0xF0,0xDE,0xFD,0x05,0x46,0xD0,0xF8, ++0x98,0x00,0x41,0x7C,0x00,0x7C,0x40,0xEA, ++0x01,0x24,0x0C,0xE0,0x20,0x46,0x05,0xF0, ++0xC4,0xF8,0x30,0xB1,0x20,0x46,0x04,0xF0, ++0xBD,0xFF,0x10,0xB1,0x20,0x46,0x04,0xF0, ++0xC5,0xFF,0x64,0x1C,0xA4,0xB2,0xE8,0x8E, ++0xA0,0x42,0xEF,0xD8,0x00,0x20,0x70,0xBD, ++0x70,0xB5,0x06,0x46,0x0D,0x46,0x02,0xF0, ++0xBF,0xFD,0x04,0x46,0xD0,0xF8,0x98,0x00, ++0x31,0x46,0x10,0x30,0x05,0xF0,0x8D,0xF8, ++0x10,0xB9,0x55,0x48,0x80,0x1E,0x70,0xBD, ++0x14,0xF8,0x70,0x1F,0x83,0x78,0xA2,0x78, ++0x11,0x44,0xC2,0x78,0x43,0xEA,0x02,0x20, ++0x88,0x40,0x28,0x60,0x21,0x7C,0x01,0x29, ++0x03,0xD1,0x31,0x04,0x01,0xD4,0x40,0x08, ++0x28,0x60,0x00,0x20,0x70,0xBD,0x10,0xB5, ++0x02,0xF0,0x9E,0xFD,0x90,0xF8,0x70,0x10, ++0x90,0xF8,0x72,0x20,0xC0,0x8E,0x11,0x44, ++0x88,0x40,0x10,0xBD,0x70,0xB5,0x04,0x46, ++0x02,0xF0,0x92,0xFD,0x05,0x46,0x10,0x22, ++0x42,0xA1,0x20,0x46,0x08,0xF0,0xB4,0xED, ++0x68,0x7C,0xA9,0x1C,0x20,0x74,0x04,0xF1, ++0x11,0x00,0x6A,0x7C,0x08,0xF0,0xAC,0xED, ++0xA8,0x8F,0x0E,0x21,0xA0,0x84,0x68,0x8F, ++0xE0,0x84,0x28,0x8F,0x20,0x85,0xE8,0x8E, ++0x60,0x85,0x28,0x6C,0xE0,0x62,0xE8,0x8F, ++0x20,0x86,0x04,0xF1,0x24,0x00,0x04,0xF0, ++0xF0,0xFD,0x20,0x62,0x10,0x22,0xB5,0xF8, ++0x44,0x00,0x05,0xF1,0x46,0x01,0x60,0x86, ++0x04,0xF1,0x40,0x00,0x08,0xF0,0x90,0xED, ++0x10,0x22,0x05,0xF1,0x56,0x01,0x04,0xF1, ++0x50,0x00,0x08,0xF0,0x8A,0xED,0xB5,0xF8, ++0x6E,0x00,0x24,0xF8,0x60,0x0F,0xB5,0xF8, ++0x68,0x00,0x60,0x80,0x95,0xF8,0x30,0x00, ++0x20,0x71,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x02,0xF0,0x52,0xFD,0x00,0x24,0x05,0x46, ++0x08,0xE0,0x20,0x46,0x04,0xF0,0x3A,0xFF, ++0x10,0xB1,0x20,0x46,0x04,0xF0,0x42,0xFF, ++0x64,0x1C,0xA4,0xB2,0xE8,0x8E,0xA0,0x42, ++0xF3,0xD8,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x02,0xF0,0x3E,0xFD,0x00,0x24,0x05,0x46, ++0x0C,0xE0,0x20,0x46,0x05,0xF0,0x29,0xF8, ++0x30,0xB1,0x20,0x46,0x04,0xF0,0x22,0xFF, ++0x10,0xB1,0x20,0x46,0x04,0xF0,0x2A,0xFF, ++0x64,0x1C,0xA4,0xB2,0xE8,0x8E,0xA0,0x42, ++0xEF,0xD8,0x00,0x20,0x70,0xBD,0x70,0xB5, ++0x05,0x46,0x04,0xF0,0x13,0xFF,0x04,0x00, ++0x02,0xD0,0x28,0x46,0x04,0xF0,0x1A,0xFF, ++0x20,0x46,0x70,0xBD,0x01,0x23,0x02,0xF0, ++0x12,0xBE,0x01,0x23,0x02,0xF0,0x08,0xBE, ++0x10,0xB5,0x05,0xF0,0x06,0xF8,0x01,0x28, ++0x01,0xD1,0x00,0x20,0x10,0xBD,0x02,0x48, ++0x28,0x30,0x10,0xBD,0x03,0xF0,0x02,0xB8, ++0x1B,0x00,0x00,0x80,0x4D,0x53,0x54,0x41, ++0x52,0x53,0x45,0x4D,0x49,0x55,0x4E,0x46, ++0x44,0x43,0x49,0x53,0x00,0x00,0x00,0x00, ++0x2D,0xE9,0xF0,0x47,0x00,0x26,0x05,0x46, ++0x88,0x46,0x91,0x46,0x05,0xF0,0xC7,0xFB, ++0x00,0x20,0x05,0xF0,0x6E,0xFB,0xDF,0xF8, ++0xF4,0xA3,0xFD,0x4F,0x05,0xF0,0x37,0xFD, ++0x00,0x28,0x56,0xD1,0xFB,0x4C,0x20,0x88, ++0x20,0xF0,0x02,0x00,0x20,0x80,0x4F,0xF4, ++0x7A,0x70,0x05,0xF0,0x87,0xFA,0x20,0x88, ++0x40,0xF0,0x02,0x00,0x20,0x80,0x00,0x24, ++0x38,0xE0,0x05,0xF0,0x8D,0xFC,0xF4,0x48, ++0x80,0x8F,0xA7,0xF8,0x40,0x00,0x58,0xF8, ++0x24,0x00,0xB8,0x85,0x55,0xF8,0x24,0x00, ++0xA7,0xF8,0x70,0x00,0x55,0xF8,0x24,0x00, ++0x00,0x0C,0xA7,0xF8,0x74,0x00,0x38,0x89, ++0x20,0xF0,0x04,0x00,0x38,0x81,0x00,0x20, ++0x05,0xF0,0xE8,0xFD,0x00,0x28,0x2C,0xD1, ++0x38,0x8D,0x40,0xF0,0x01,0x00,0x38,0x85, ++0xB7,0xF8,0xBC,0x00,0x14,0xB9,0x40,0xF0, ++0x04,0x00,0x01,0xE0,0x40,0xF0,0x01,0x00, ++0xA7,0xF8,0xBC,0x00,0x52,0x46,0x4F,0xF4, ++0x80,0x41,0x38,0x46,0x05,0xF0,0xE0,0xFB, ++0x00,0x28,0x16,0xD1,0xB7,0xF8,0x48,0x00, ++0x1E,0xB9,0xC0,0x07,0x01,0xD0,0x01,0x26, ++0xB4,0xE7,0x64,0x1C,0x4C,0x45,0xC4,0xD3, ++0xB7,0xF8,0xBC,0x10,0x38,0x46,0x41,0xF0, ++0x02,0x01,0xA7,0xF8,0xBC,0x10,0x52,0x46, ++0x4F,0xF4,0x00,0x41,0x05,0xF0,0xC8,0xFB, ++0x00,0x28,0xBD,0xE8,0xF0,0x87,0x0B,0x46, ++0xCF,0x49,0x10,0xB5,0x0F,0x22,0x91,0xF8, ++0x8C,0x10,0x01,0x70,0x18,0x46,0xCC,0x49, ++0x8D,0x31,0x08,0xF0,0xB2,0xEC,0x00,0x20, ++0x10,0xBD,0x2D,0xE9,0xF0,0x41,0x04,0x46, ++0x00,0xF5,0x00,0x75,0x07,0xF0,0x82,0xF9, ++0xC6,0x4E,0x10,0xB1,0x30,0x46,0xBD,0xE8, ++0xF0,0x81,0x0E,0x21,0x04,0xF1,0x24,0x00, ++0x07,0xF0,0x6C,0xF9,0x07,0x46,0x04,0xF1, ++0x20,0x00,0x08,0xF0,0xDE,0xED,0x01,0x46, ++0x38,0x46,0x81,0x42,0x4F,0xF4,0x00,0x77, ++0x04,0xD0,0x39,0x46,0x20,0x46,0x07,0xF0, ++0x2E,0xF9,0xE7,0xE7,0x28,0x1D,0x4F,0xF4, ++0xFE,0x71,0x07,0xF0,0x57,0xF9,0x06,0x46, ++0x28,0x46,0x08,0xF0,0xCA,0xED,0xB0,0x42, ++0x06,0xD0,0x39,0x46,0x28,0x46,0x07,0xF0, ++0x1E,0xF9,0xB2,0x48,0x40,0x1C,0xD6,0xE7, ++0x20,0x46,0x07,0xF0,0x7C,0xF9,0x28,0x46, ++0x07,0xF0,0x84,0xF9,0x00,0x20,0xCE,0xE7, ++0x2D,0xE9,0xF0,0x41,0x05,0x46,0x00,0xF5, ++0x00,0x76,0xFF,0xF7,0xBE,0xFF,0x00,0x28, ++0xC5,0xD1,0x00,0x24,0x29,0x46,0x20,0x46, ++0x06,0xF0,0x70,0xFF,0x00,0x28,0xBE,0xD1, ++0x64,0x1C,0xA4,0xB2,0x02,0x2C,0xF5,0xD3, ++0x00,0x24,0xA0,0x1C,0x31,0x46,0x06,0xF0, ++0x65,0xFF,0x07,0x00,0x01,0xD0,0x38,0x46, ++0xB1,0xE7,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF3,0xD3,0x4F,0xF4,0x00,0x72,0x9C,0x48, ++0x31,0x46,0x00,0x68,0x08,0xF0,0x4C,0xEC, ++0x97,0x48,0x10,0x22,0x05,0xF1,0x40,0x01, ++0x9C,0x30,0x08,0xF0,0x46,0xEC,0x94,0x48, ++0x10,0x22,0x05,0xF1,0x50,0x01,0xAC,0x30, ++0x08,0xF0,0x3E,0xEC,0xE3,0xE7,0x70,0xB5, ++0x00,0x24,0x05,0x46,0x00,0xF5,0x00,0x76, ++0x29,0x46,0x20,0x46,0x05,0xF0,0x28,0xFE, ++0x18,0xB1,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF6,0xD3,0x02,0x2C,0x02,0xD1,0x89,0x48, ++0x80,0x1C,0x70,0xBD,0x00,0x24,0x31,0x46, ++0xA0,0x1C,0x05,0xF0,0x19,0xFE,0x05,0x00, ++0x03,0xD0,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF5,0xD3,0x02,0x2C,0x02,0xD1,0x81,0x48, ++0xC0,0x1C,0x70,0xBD,0x80,0x48,0x4F,0xF4, ++0x00,0x72,0x31,0x46,0x00,0x68,0x08,0xF0, ++0x14,0xEC,0x28,0x46,0x70,0xBD,0x7A,0x48, ++0x40,0x68,0x00,0x07,0x01,0xD5,0x05,0xF0, ++0x92,0xBC,0x70,0x47,0x2D,0xE9,0xF0,0x47, ++0x00,0x25,0x20,0x20,0x07,0xF0,0x9C,0xF8, ++0x73,0x4E,0x04,0x00,0x4D,0xD1,0xCC,0x21, ++0x30,0x46,0x08,0xF0,0x8A,0xEC,0x73,0x4F, ++0xA0,0x46,0x4F,0xF4,0x7A,0x7A,0x4F,0xF0, ++0x11,0x09,0x05,0xF0,0x9C,0xFA,0xB7,0xF8, ++0xCC,0x0D,0x20,0xF0,0x02,0x00,0xA7,0xF8, ++0xCC,0x0D,0x50,0x46,0x05,0xF0,0x66,0xF9, ++0x86,0xF8,0x88,0x80,0xA6,0xF8,0x3C,0x90, ++0xB7,0xF8,0xCC,0x0D,0x40,0xF0,0x02,0x00, ++0xA7,0xF8,0xCC,0x0D,0x05,0xF0,0xFF,0xFB, ++0x04,0x00,0x2A,0xD1,0x06,0xF0,0x7E,0xF8, ++0x04,0x00,0x04,0xD0,0x03,0x2D,0x24,0xD2, ++0x6D,0x1C,0xED,0xB2,0xDD,0xE7,0x00,0x20, ++0x05,0xF0,0x23,0xFA,0x06,0xF0,0xE3,0xF8, ++0x04,0x00,0x1A,0xD1,0x30,0x88,0x07,0x21, ++0x05,0xF0,0x4B,0xFF,0x04,0x00,0x14,0xD1, ++0x06,0xF0,0x08,0xFA,0x04,0x00,0x10,0xD1, ++0x00,0x21,0x08,0x20,0x05,0xF0,0xB4,0xFE, ++0x04,0x00,0x0A,0xD1,0x01,0x20,0x06,0xF0, ++0xBD,0xFA,0x04,0x00,0x05,0xD1,0x05,0x20, ++0x05,0xF0,0x07,0xFA,0x51,0x49,0x50,0x48, ++0x08,0x60,0x78,0x36,0x4A,0x49,0x0A,0x22, ++0x46,0xF8,0x70,0x4C,0x2D,0x31,0x01,0xF1, ++0x60,0x00,0x08,0xF0,0xAA,0xEB,0x0B,0x20, ++0x01,0x21,0x30,0x75,0xF0,0x68,0x01,0xEB, ++0x50,0x50,0xF0,0x77,0x00,0xF0,0x12,0xF8, ++0x04,0x00,0x02,0xD0,0x41,0x48,0x40,0x1D, ++0xDB,0xE6,0xFF,0xF7,0x88,0xFF,0x20,0x46, ++0xD7,0xE6,0x42,0x48,0x40,0x49,0x00,0x68, ++0xC9,0x43,0x88,0x42,0x01,0xD0,0x00,0x20, ++0x70,0x47,0x83,0xE7,0x2D,0xE9,0xF0,0x47, ++0x39,0x4D,0x2E,0x68,0xFF,0xF7,0xF1,0xFF, ++0x00,0x28,0x1D,0xD1,0x00,0x24,0xA8,0x46, ++0x4F,0xF4,0xFE,0x79,0xA0,0x1C,0xD8,0xF8, ++0x00,0x10,0x05,0xF0,0x71,0xFD,0x05,0x00, ++0x0A,0xD1,0x30,0x46,0x08,0xF0,0xBC,0xEC, ++0x30,0xB1,0x07,0x46,0x30,0x1D,0x49,0x46, ++0x07,0xF0,0x40,0xF8,0x87,0x42,0x03,0xD0, ++0x64,0x1C,0xA4,0xB2,0x02,0x2C,0xE9,0xD3, ++0x02,0x2C,0x02,0xD1,0x27,0x48,0x80,0x1F, ++0xA7,0xE6,0x25,0x48,0x41,0x68,0x41,0xF0, ++0x02,0x01,0x41,0x60,0x28,0x46,0xA0,0xE6, ++0x23,0x48,0x10,0xB5,0x04,0x68,0x20,0x48, ++0x40,0x68,0x80,0x07,0x03,0xD4,0xFF,0xF7, ++0xC9,0xFF,0x00,0x28,0x0B,0xD1,0x61,0x7B, ++0x22,0x7B,0x00,0x20,0x42,0xEA,0x01,0x21, ++0x02,0xE0,0x4A,0x1E,0x40,0x1C,0x80,0xB2, ++0x81,0x42,0xFA,0xD8,0x00,0x20,0x10,0xBD, ++0x10,0xB5,0x04,0x46,0xFF,0xF7,0xAD,0xFF, ++0x00,0x28,0x0F,0xD1,0x12,0x48,0x40,0x68, ++0x80,0x07,0x03,0xD4,0xFF,0xF7,0xAE,0xFF, ++0x00,0x28,0x07,0xD1,0x4F,0xF4,0x00,0x72, ++0x0F,0x48,0x01,0x68,0x20,0x46,0x08,0xF0, ++0x34,0xEB,0x00,0x20,0x10,0xBD,0x2D,0xE9, ++0xF0,0x41,0x0C,0x46,0x05,0x46,0xFF,0xF7, ++0x94,0xFF,0x00,0x28,0x27,0xD1,0xC4,0xF3, ++0x08,0x00,0x00,0xEB,0x54,0x20,0x81,0xB2, ++0x00,0x20,0x1B,0xE0,0x40,0x42,0x0F,0x00, ++0x00,0x50,0x00,0x25,0xCC,0x0D,0x02,0x25, ++0x20,0x15,0x03,0x20,0x1D,0x00,0x00,0x80, ++0x84,0x05,0x03,0x20,0x00,0x00,0x02,0x25, ++0x43,0x4D,0x4D,0x65,0xC4,0x04,0x03,0x20, ++0x6A,0x79,0x2B,0x79,0x43,0xEA,0x02,0x22, ++0x01,0x2A,0x05,0xD0,0x40,0x1C,0x05,0xF5, ++0x00,0x75,0x80,0xB2,0x88,0x42,0xF3,0xD3, ++0x88,0x42,0x01,0xD1,0xFC,0x48,0x5A,0xE6, ++0x28,0x46,0x08,0xF0,0x42,0xEC,0x04,0x46, ++0x28,0x1D,0x4F,0xF4,0xFE,0x71,0x06,0xF0, ++0xC5,0xFF,0x84,0x42,0x02,0xD0,0xF6,0x48, ++0x40,0x1C,0x4C,0xE6,0x00,0x24,0x29,0x46, ++0xA0,0x1C,0x06,0xF0,0xF7,0xFD,0x00,0x28, ++0xE9,0xD1,0x64,0x1C,0xA4,0xB2,0x02,0x2C, ++0xF5,0xD3,0x00,0x24,0xEF,0x4E,0x4F,0xF4, ++0x00,0x78,0xA0,0x1C,0x31,0x68,0x05,0xF0, ++0xD3,0xFC,0x00,0x28,0xDB,0xD1,0x31,0x68, ++0x42,0x46,0x28,0x46,0x06,0xF0,0x85,0xFF, ++0x07,0x00,0x09,0xD0,0x44,0x46,0x41,0x46, ++0x28,0x46,0x06,0xF0,0x70,0xFF,0x30,0x68, ++0x21,0x46,0x06,0xF0,0x6C,0xFF,0x03,0xE0, ++0x64,0x1C,0xA4,0xB2,0x02,0x2C,0xE4,0xD3, ++0x38,0x46,0x20,0xE6,0x2D,0xE9,0xF0,0x41, ++0x07,0x46,0xDE,0x48,0x00,0x25,0x88,0x46, ++0x14,0x46,0x06,0x68,0xDC,0x48,0x40,0x68, ++0x80,0x07,0x03,0xD4,0xFF,0xF7,0x2A,0xFF, ++0x00,0x28,0x21,0xD1,0x00,0x20,0x0E,0xE0, ++0x20,0x88,0x06,0xEB,0xC0,0x00,0x41,0x7D, ++0x02,0x7D,0x42,0xEA,0x01,0x20,0xB8,0x42, ++0x03,0xD1,0x45,0x45,0x0B,0xD0,0x6D,0x1C, ++0xAD,0xB2,0x20,0x88,0x40,0x1C,0x20,0x80, ++0x21,0x88,0x70,0x7B,0x32,0x7B,0x42,0xEA, ++0x00,0x20,0x81,0x42,0xE8,0xD3,0x21,0x88, ++0x70,0x7B,0x32,0x7B,0x42,0xEA,0x00,0x20, ++0x81,0x42,0x02,0xD1,0xC6,0x48,0xC0,0x1C, ++0xED,0xE5,0x00,0x20,0xEB,0xE5,0xF8,0xB5, ++0x06,0x46,0xC4,0x48,0x0D,0x46,0x04,0x68, ++0xFF,0xF7,0xF3,0xFE,0x00,0x28,0x15,0xD1, ++0x00,0x21,0x6A,0x46,0x30,0x46,0xFF,0xF7, ++0xBD,0xFF,0x00,0x28,0x0E,0xD1,0xBD,0xF8, ++0x00,0x00,0x04,0xEB,0xC0,0x00,0xC1,0x7C, ++0x82,0x7C,0x42,0xEA,0x01,0x20,0x61,0x7A, ++0x22,0x7A,0x42,0xEA,0x01,0x21,0x48,0x43, ++0x28,0x60,0x00,0x20,0xF8,0xBD,0x2D,0xE9, ++0xF0,0x5F,0x07,0x46,0xB5,0x48,0x0C,0x46, ++0xB5,0x49,0x90,0x46,0x4F,0xF0,0x00,0x09, ++0x00,0x68,0x88,0x42,0x03,0xD1,0xAE,0x48, ++0x40,0x1E,0xBD,0xE8,0xF0,0x9F,0xE0,0x05, ++0x01,0xD0,0xAB,0x48,0xF9,0xE7,0xDF,0xF8, ++0xB0,0xA2,0xF8,0x06,0xDF,0xF8,0xB4,0xB2, ++0x3B,0xD0,0x40,0x46,0x5D,0x46,0xDB,0xF8, ++0x00,0x10,0x05,0xF0,0x45,0xFC,0x06,0x00, ++0x02,0xD0,0xCA,0xF8,0x08,0x60,0x45,0xE0, ++0x29,0x68,0x4F,0xF4,0x00,0x72,0x38,0x46, ++0x08,0xF0,0x46,0xEA,0xB4,0xF5,0x00,0x74, ++0x08,0xF1,0x01,0x08,0x07,0xF5,0x00,0x77, ++0x38,0xD0,0x4F,0xF0,0x01,0x09,0xA4,0xF5, ++0x00,0x74,0x1E,0xE0,0xB4,0xF5,0x00,0x7F, ++0x10,0xD9,0x40,0xF6,0xFF,0x75,0xB5,0xEB, ++0x54,0x2F,0x01,0xD9,0xC4,0xF3,0x4F,0x25, ++0x2A,0x46,0x39,0x46,0x40,0x46,0x06,0xF0, ++0xEF,0xFB,0x06,0x00,0x08,0xD0,0xCA,0xF8, ++0x08,0x60,0x0C,0xE0,0x01,0x25,0x39,0x46, ++0x40,0x46,0x05,0xF0,0x15,0xFC,0xF4,0xE7, ++0xA8,0x44,0x07,0xEB,0x45,0x27,0xA4,0xEB, ++0x45,0x24,0x00,0x2C,0xDE,0xD1,0xB9,0xF1, ++0x00,0x0F,0x0F,0xD0,0xDB,0xF8,0x00,0x10, ++0x5C,0x46,0x40,0x46,0x05,0xF0,0x04,0xFC, ++0x06,0x00,0x01,0xD0,0xCA,0xF8,0x08,0x60, ++0x21,0x68,0x4F,0xF4,0x00,0x72,0x38,0x46, ++0x08,0xF0,0x06,0xEA,0x30,0x46,0xA0,0xE7, ++0x2D,0xE9,0xFC,0x47,0x80,0x46,0x7D,0x48, ++0x89,0x46,0x0A,0x9F,0x15,0x46,0x1E,0x46, ++0x04,0x68,0xFF,0xF7,0x62,0xFE,0x00,0x28, ++0x1B,0xD1,0x01,0xAA,0x39,0x46,0x40,0x46, ++0xFF,0xF7,0x2C,0xFF,0x00,0x28,0x14,0xD1, ++0xBD,0xF8,0x04,0x00,0x04,0xEB,0xC0,0x00, ++0xC1,0x7C,0x82,0x7C,0x42,0xEA,0x01,0x20, ++0x61,0x7A,0x22,0x7A,0x42,0xEA,0x01,0x21, ++0x48,0x43,0x85,0x42,0x04,0xD8,0x86,0x42, ++0x02,0xD8,0xAA,0x19,0x82,0x42,0x02,0xD9, ++0x69,0x48,0xBD,0xE8,0xFC,0x87,0xBD,0xF8, ++0x04,0x00,0x04,0xEB,0xC0,0x00,0x42,0x7C, ++0x03,0x7C,0x43,0xEA,0x02,0x20,0x00,0xFB, ++0x01,0x52,0x71,0x02,0x48,0x46,0xFF,0xF7, ++0x5A,0xFF,0x00,0x28,0xED,0xD1,0x02,0x23, ++0x00,0x93,0x33,0x46,0x2A,0x46,0x41,0x46, ++0x48,0x46,0x05,0xF0,0x78,0xF8,0xE4,0xE7, ++0x2D,0xE9,0xF0,0x47,0x0C,0x46,0x5D,0x49, ++0x17,0x46,0x5D,0x4A,0x06,0x46,0x09,0x68, ++0x91,0x42,0x02,0xD1,0x56,0x48,0x40,0x1E, ++0xF3,0xE4,0x55,0x4A,0x1E,0xB1,0xE1,0x05, ++0x40,0xF6,0xFF,0x73,0x1E,0xD0,0x10,0x46, ++0xEB,0xE4,0x4C,0x45,0x0B,0xD9,0xB8,0xEB, ++0x54,0x2F,0x45,0x46,0x01,0xD9,0xC4,0xF3, ++0x4F,0x25,0x2A,0x46,0x31,0x46,0x38,0x46, ++0x06,0xF0,0xA7,0xFC,0x04,0xE0,0x01,0x25, ++0x31,0x46,0x38,0x46,0x06,0xF0,0xA2,0xFC, ++0x10,0xB1,0x49,0x49,0x88,0x60,0xD4,0xE4, ++0x2F,0x44,0x06,0xEB,0x45,0x26,0xA4,0xEB, ++0x45,0x24,0x02,0xE0,0x4F,0xF4,0x00,0x79, ++0x98,0x46,0x00,0x2C,0xDD,0xD1,0xC8,0xE4, ++0x2D,0xE9,0xFC,0x47,0x80,0x46,0x3F,0x48, ++0x89,0x46,0x0A,0x9F,0x15,0x46,0x1E,0x46, ++0x04,0x68,0xFF,0xF7,0xE6,0xFD,0x00,0x28, ++0x9F,0xD1,0x01,0xAA,0x39,0x46,0x40,0x46, ++0xFF,0xF7,0xB0,0xFE,0x00,0x28,0x98,0xD1, ++0xBD,0xF8,0x04,0x00,0x04,0xEB,0xC0,0x00, ++0xC1,0x7C,0x82,0x7C,0x42,0xEA,0x01,0x20, ++0x61,0x7A,0x22,0x7A,0x42,0xEA,0x01,0x21, ++0x48,0x43,0x85,0x42,0x04,0xD8,0x86,0x42, ++0x02,0xD8,0xAA,0x19,0x82,0x42,0x01,0xD9, ++0x2B,0x48,0x82,0xE7,0xBD,0xF8,0x04,0x00, ++0x04,0xEB,0xC0,0x00,0x42,0x7C,0x03,0x7C, ++0x43,0xEA,0x02,0x20,0x00,0xFB,0x01,0x52, ++0x71,0x02,0x48,0x46,0xFF,0xF7,0x90,0xFF, ++0x00,0x28,0xEE,0xD1,0x01,0x23,0x00,0x93, ++0x33,0x46,0x2A,0x46,0x41,0x46,0x48,0x46, ++0x04,0xF0,0xFD,0xFF,0x69,0xE7,0x70,0xB5, ++0x10,0x22,0x04,0x46,0x22,0xA1,0x08,0xF0, ++0x40,0xE9,0x1D,0x4D,0x80,0x35,0x05,0xF1, ++0x0D,0x01,0x28,0x7B,0x20,0x74,0x04,0xF1, ++0x11,0x00,0x2A,0x7B,0x08,0xF0,0x34,0xE9, ++0x01,0x20,0xA0,0x84,0x40,0x02,0xE0,0x84, ++0x28,0x68,0x20,0x85,0xD5,0xE9,0x00,0x10, ++0x09,0xF0,0xCA,0xE9,0x60,0x85,0x0E,0x21, ++0x04,0xF1,0x24,0x00,0x06,0xF0,0xF2,0xFD, ++0x05,0xF1,0x1C,0x01,0x20,0x62,0x04,0xF1, ++0x40,0x00,0x50,0x34,0x6C,0xC9,0x6C,0xC0, ++0x08,0x46,0x2E,0xC8,0x00,0x20,0x2E,0xC4, ++0x70,0xBD,0x2D,0xE9,0xF0,0x5F,0x80,0x46, ++0x07,0x4B,0x0D,0x46,0x58,0x68,0xC0,0x07, ++0x1C,0xD0,0x29,0x46,0x40,0x46,0x06,0xF0, ++0xF4,0xF8,0x04,0x46,0x76,0xE0,0x00,0x00, ++0x15,0x00,0x00,0x80,0x84,0x05,0x03,0x20, ++0x20,0x15,0x03,0x20,0xC4,0x04,0x03,0x20, ++0xBC,0xB2,0xB2,0x9A,0x80,0x05,0x03,0x20, ++0x4D,0x53,0x54,0x41,0x52,0x53,0x45,0x4D, ++0x49,0x55,0x4E,0x46,0x44,0x43,0x49,0x53, ++0x00,0x00,0x00,0x00,0xF5,0x4E,0x00,0x21, ++0xFF,0x20,0x4F,0xF4,0x00,0x77,0xBA,0x46, ++0x32,0x68,0x50,0x54,0x49,0x1C,0xB9,0x42, ++0xF9,0xD3,0xF1,0x48,0xD0,0xF8,0x80,0x60, ++0x40,0x46,0x31,0x46,0x09,0xF0,0x80,0xE9, ++0x40,0x1C,0x46,0x43,0xA5,0xEB,0x08,0x00, ++0x83,0x46,0xA6,0xEB,0x08,0x07,0xB8,0x42, ++0x00,0xD2,0x5F,0x46,0x00,0x26,0x12,0xE0, ++0xB9,0x1B,0x50,0x46,0xBA,0xEB,0x41,0x2F, ++0x00,0xD3,0x48,0x02,0x81,0x46,0x01,0x46, ++0xE2,0x48,0x08,0xEB,0x06,0x02,0x00,0x68, ++0xFF,0xF7,0x06,0xFF,0x04,0x00,0x31,0xD1, ++0x06,0xEB,0x59,0x26,0x76,0x1C,0xBE,0x42, ++0xEA,0xD3,0xBB,0x45,0x2A,0xD0,0x47,0x44, ++0xDF,0xF8,0x6C,0xB3,0xE8,0x1B,0xDB,0xF8, ++0x80,0x10,0x89,0x46,0x09,0xF0,0x54,0xE9, ++0x06,0x00,0x06,0xD0,0x38,0x46,0x06,0xFB, ++0x09,0x71,0x06,0xF0,0x96,0xF8,0x04,0x00, ++0x18,0xD1,0xDB,0xF8,0x80,0x00,0xDF,0xF8, ++0x44,0x83,0x06,0xFB,0x00,0x76,0x0F,0xE0, ++0xA8,0x1B,0x57,0x46,0xBA,0xEB,0x40,0x2F, ++0x00,0xD3,0x47,0x02,0xD8,0xF8,0x00,0x00, ++0x32,0x46,0x39,0x46,0xFF,0xF7,0xD8,0xFE, ++0x04,0x00,0x03,0xD1,0x06,0xEB,0x57,0x26, ++0xAE,0x42,0xED,0xD3,0x20,0x46,0x2C,0xE6, ++0x2D,0xE9,0xF8,0x43,0x80,0x46,0xC5,0x48, ++0x04,0x68,0xFF,0xF7,0xF2,0xFC,0x00,0x28, ++0x37,0xD1,0x00,0x25,0x6A,0x46,0x29,0x46, ++0x40,0x46,0xFF,0xF7,0xBB,0xFD,0x58,0xBB, ++0xBD,0xF8,0x00,0x00,0x6D,0x1C,0x23,0x7A, ++0x04,0xEB,0xC0,0x00,0x41,0x7C,0x02,0x7C, ++0x42,0xEA,0x01,0x20,0x61,0x7A,0x43,0xEA, ++0x01,0x22,0xE1,0x79,0xA3,0x79,0x50,0x43, ++0x43,0xEA,0x01,0x21,0x4B,0x0A,0xBD,0xF8, ++0x00,0x10,0x58,0x43,0x04,0xEB,0xC1,0x01, ++0x4E,0x7C,0x09,0x7C,0x41,0xEA,0x06,0x26, ++0xBD,0xF8,0x00,0x10,0x04,0xEB,0xC1,0x01, ++0xCF,0x7C,0x89,0x7C,0x41,0xEA,0x07,0x27, ++0xF1,0x19,0x59,0x43,0x51,0x43,0x49,0x1E, ++0xFF,0xF7,0x3F,0xFF,0x00,0x28,0xCD,0xD0, ++0x00,0x2D,0x02,0xD0,0x40,0x46,0x04,0xF0, ++0x1F,0xFF,0xBD,0xE8,0xF8,0x83,0xA5,0x48, ++0xF8,0xB5,0x05,0x68,0xFF,0xF7,0xB1,0xFC, ++0x00,0x28,0x32,0xD1,0x00,0x26,0x48,0xF2, ++0x0B,0x07,0x6A,0x46,0x31,0x46,0x38,0x46, ++0xFF,0xF7,0x78,0xFD,0x18,0xBB,0xBD,0xF8, ++0x00,0x40,0x76,0x1C,0xF5,0xE7,0x05,0xEB, ++0xC4,0x01,0x2B,0x7A,0xAF,0x79,0x48,0x7C, ++0x0A,0x7C,0x42,0xEA,0x00,0x26,0x68,0x7A, ++0x43,0xEA,0x00,0x22,0xEB,0x79,0x06,0xFB, ++0x02,0xF0,0x47,0xEA,0x03,0x23,0xCF,0x7C, ++0x89,0x7C,0x5B,0x0A,0x41,0xEA,0x07,0x27, ++0xF1,0x19,0x58,0x43,0x59,0x43,0x51,0x43, ++0x49,0x1E,0xFF,0xF7,0x06,0xFF,0x00,0x28, ++0x07,0xD1,0x64,0x1C,0xA4,0xB2,0x69,0x7B, ++0x2A,0x7B,0x42,0xEA,0x01,0x21,0xA1,0x42, ++0xD9,0xD8,0xF8,0xBD,0x86,0x48,0xD0,0xF8, ++0x84,0x10,0x49,0x1E,0x00,0x20,0xF4,0xE6, ++0x2D,0xE9,0xF0,0x5F,0x05,0x46,0x0C,0x46, ++0xFF,0xF7,0x6F,0xFC,0x00,0x28,0x75,0xD1, ++0x49,0x22,0xB3,0x21,0x03,0x20,0x05,0xF0, ++0xE2,0xFA,0x00,0x28,0x6E,0xD1,0x7C,0x4B, ++0x58,0x68,0xC0,0x07,0x06,0xD0,0x21,0x46, ++0x28,0x46,0xFF,0xF7,0xDE,0xFE,0x00,0x28, ++0x64,0xD1,0x5C,0xE0,0x75,0x4E,0xFF,0x21, ++0x4F,0xF4,0x00,0x77,0xB0,0x46,0xB9,0x46, ++0x32,0x68,0x11,0x54,0x40,0x1C,0xB8,0x42, ++0xF8,0xD3,0x71,0x48,0xD0,0xF8,0x80,0x60, ++0x28,0x46,0x31,0x46,0x09,0xF0,0x80,0xE8, ++0x40,0x1C,0x46,0x43,0x60,0x1B,0x82,0x46, ++0x77,0x1B,0xB8,0x42,0x00,0xD2,0x57,0x46, ++0x00,0x26,0xC3,0x46,0x11,0xE0,0xB9,0x1B, ++0x48,0x46,0xB9,0xEB,0x41,0x2F,0x00,0xD3, ++0x48,0x02,0x80,0x46,0x01,0x46,0xDB,0xF8, ++0x00,0x00,0xAA,0x19,0xFF,0xF7,0x08,0xFE, ++0x00,0x28,0x37,0xD1,0x06,0xEB,0x58,0x26, ++0x76,0x1C,0xBE,0x42,0xEB,0xD3,0xBA,0x45, ++0x29,0xD0,0xEE,0x19,0xDF,0xF8,0x70,0xA1, ++0xA0,0x1B,0xDA,0xF8,0x80,0x10,0x88,0x46, ++0x09,0xF0,0x56,0xE8,0x05,0x00,0x06,0xD0, ++0x30,0x46,0x05,0xFB,0x08,0x61,0xFF,0xF7, ++0x98,0xFE,0x00,0x28,0x1E,0xD1,0xDA,0xF8, ++0x80,0x00,0x4F,0x46,0x05,0xFB,0x00,0x65, ++0x0F,0xE0,0x60,0x1B,0x3E,0x46,0xB7,0xEB, ++0x40,0x2F,0x00,0xD3,0x46,0x02,0xDB,0xF8, ++0x00,0x00,0x2A,0x46,0x31,0x46,0xFF,0xF7, ++0xDB,0xFD,0x00,0x28,0x0A,0xD1,0x05,0xEB, ++0x56,0x25,0xA5,0x42,0xED,0xD3,0x48,0x22, ++0xBD,0xE8,0xF0,0x5F,0xB3,0x21,0x03,0x20, ++0x05,0xF0,0x71,0xBA,0x29,0xE5,0x2D,0xE9, ++0xF0,0x47,0x80,0x46,0x0D,0x46,0x14,0x46, ++0xFF,0xF7,0xEF,0xFB,0x00,0x28,0x39,0xD1, ++0x49,0x22,0xB3,0x21,0x03,0x20,0x05,0xF0, ++0x62,0xFA,0x00,0x28,0x32,0xD1,0xE8,0x05, ++0x00,0xD0,0x01,0x20,0x00,0xEB,0x55,0x20, ++0x22,0x46,0x85,0xB2,0x40,0x46,0x69,0x02, ++0xFF,0xF7,0xB2,0xFD,0x00,0x28,0x25,0xD1, ++0xFF,0x21,0x34,0x4F,0x4F,0xF4,0x00,0x76, ++0x3A,0x68,0x11,0x54,0x40,0x1C,0x80,0xB2, ++0xB0,0x42,0xF9,0xD3,0x39,0x68,0xC1,0x20, ++0x06,0xF0,0x6C,0xFA,0x00,0x28,0x15,0xD1, ++0xB1,0x46,0xA4,0xB2,0x15,0xE0,0x39,0x68, ++0x20,0x46,0x05,0xF0,0x4D,0xF9,0x00,0x28, ++0x0C,0xD1,0x39,0x68,0x08,0xEB,0x44,0x20, ++0x4A,0x46,0x06,0xF0,0xFE,0xFB,0x06,0x00, ++0x05,0xD0,0x38,0x68,0x49,0x46,0x06,0xF0, ++0xEA,0xFB,0x30,0x46,0x94,0xE5,0x64,0x1C, ++0xA4,0xB2,0xAC,0x42,0xE7,0xD3,0x0A,0x22, ++0xB1,0x21,0x03,0x20,0x05,0xF0,0x23,0xFA, ++0x00,0x28,0xF3,0xD1,0x48,0x22,0xB3,0x21, ++0x03,0x20,0x05,0xF0,0x1C,0xFA,0x00,0x28, ++0xEC,0xD1,0x01,0x22,0xBD,0xE8,0xF0,0x47, ++0xA2,0x21,0x03,0x20,0x05,0xF0,0x13,0xBA, ++0x70,0xB5,0x05,0x46,0x0C,0x46,0x16,0x46, ++0xFF,0xF7,0x93,0xFB,0x00,0x28,0x1A,0xD1, ++0x49,0x22,0xB3,0x21,0x03,0x20,0x05,0xF0, ++0x06,0xFA,0x00,0x28,0x13,0xD1,0xE0,0x05, ++0x00,0xD0,0x01,0x20,0x00,0xEB,0x54,0x20, ++0x32,0x46,0x00,0x04,0xC1,0x09,0x28,0x46, ++0xFF,0xF7,0xA5,0xFC,0x00,0x28,0x06,0xD1, ++0x48,0x22,0xBD,0xE8,0x70,0x40,0xB3,0x21, ++0x03,0x20,0x05,0xF0,0xF0,0xB9,0x70,0xBD, ++0xFF,0xF7,0x73,0xBB,0x05,0x49,0x04,0x48, ++0x08,0x60,0x70,0x47,0x80,0x05,0x03,0x20, ++0x20,0x15,0x03,0x20,0x84,0x05,0x03,0x20, ++0xBC,0xB2,0xB2,0x9A,0xC4,0x04,0x03,0x20, ++0x41,0x69,0x0A,0x78,0x0A,0x2A,0x0B,0xD2, ++0x4A,0x78,0x05,0x2A,0x08,0xD2,0x8A,0x78, ++0x02,0x2A,0x05,0xD2,0xC9,0x78,0x02,0x29, ++0x02,0xD2,0x01,0x77,0x01,0x20,0x70,0x47, ++0x00,0x20,0x70,0x47,0xB3,0x48,0x80,0x88, ++0x70,0x47,0xB2,0x48,0x00,0x88,0x70,0x47, ++0x41,0x69,0x0A,0x68,0x02,0x60,0xAF,0x48, ++0x82,0x88,0x00,0x88,0x42,0xEA,0x00,0x40, ++0x08,0x60,0x01,0x20,0x70,0x47,0x2D,0xE9, ++0xF0,0x41,0x00,0x24,0x87,0x69,0x05,0x46, ++0x0E,0x46,0x04,0xE0,0x38,0x5D,0x00,0xF0, ++0x4F,0xFE,0x64,0x1C,0xA4,0xB2,0xB4,0x42, ++0xF8,0xD3,0xA8,0x69,0x30,0x44,0xA8,0x61, ++0x28,0x68,0x80,0x1B,0x28,0x60,0x03,0xD1, ++0xA1,0x48,0x28,0x62,0x02,0x20,0x28,0x60, ++0x01,0x20,0xBD,0xE8,0xF0,0x81,0x70,0xB5, ++0x04,0x46,0x00,0xF0,0x55,0xFE,0x60,0x69, ++0x00,0x78,0x00,0xF0,0x35,0xFE,0x61,0x6A, ++0x20,0x46,0x88,0x47,0x05,0x00,0x0A,0xD0, ++0x98,0x48,0x20,0x62,0x41,0xF2,0x88,0x30, ++0xFC,0xF7,0xC0,0xFE,0xE1,0x6A,0x88,0x88, ++0x40,0xF4,0x80,0x70,0x88,0x80,0x28,0x46, ++0x70,0xBD,0xF8,0xB5,0x04,0x46,0x87,0x69, ++0x15,0x20,0x00,0x25,0x0E,0x46,0x00,0x90, ++0x04,0xE0,0x78,0x5D,0x00,0xF0,0x18,0xFE, ++0x6D,0x1C,0xAD,0xB2,0xB5,0x42,0xF8,0xD3, ++0xA0,0x69,0x30,0x44,0xA0,0x61,0x20,0x68, ++0x80,0x1B,0x20,0x60,0x34,0xD1,0x00,0xF0, ++0x1E,0xFE,0x30,0xB1,0xA1,0x6A,0x21,0xB1, ++0x20,0x46,0x88,0x47,0x08,0xB1,0x06,0x20, ++0x00,0x90,0x01,0x21,0xE0,0x6A,0x00,0x68, ++0x82,0x68,0x68,0x46,0x90,0x47,0x9D,0xF8, ++0x00,0x00,0x06,0x28,0x12,0xD1,0xA0,0x6A, ++0x7D,0x49,0x88,0x42,0x05,0xD1,0xE1,0x6A, ++0x60,0x69,0x09,0x68,0x49,0x68,0x88,0x47, ++0x08,0xE0,0x7A,0x49,0x88,0x42,0x05,0xD1, ++0xE2,0x6A,0x21,0x68,0x60,0x69,0x12,0x68, ++0x92,0x68,0x90,0x47,0x76,0x48,0x20,0x62, ++0x04,0xF1,0x08,0x00,0x60,0x61,0xA0,0x61, ++0x01,0x20,0x20,0x60,0x00,0x20,0xA0,0x62, ++0x41,0xF2,0x88,0x30,0xFC,0xF7,0x6E,0xFE, ++0x01,0x20,0xF8,0xBD,0x41,0x69,0x09,0x68, ++0x41,0x60,0x01,0x20,0x70,0x47,0x70,0xB5, ++0x04,0x46,0x40,0x69,0x21,0x69,0x05,0x68, ++0x6A,0x48,0x09,0x1A,0xFE,0xF7,0xCA,0xF8, ++0xA8,0x42,0x0B,0xD1,0xE0,0x6A,0x81,0x88, ++0x21,0xF4,0x80,0x71,0x81,0x80,0xE0,0x6A, ++0x81,0x88,0x41,0xF4,0x00,0x71,0x81,0x80, ++0x01,0x20,0x70,0xBD,0x00,0x20,0x70,0xBD, ++0x41,0x69,0x60,0x4A,0x09,0x68,0x11,0x44, ++0x02,0x69,0x8A,0x42,0x02,0xD3,0x01,0x61, ++0x01,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0x42,0x68,0x01,0x69,0x11,0x44,0x01,0x61, ++0x01,0x20,0x70,0x47,0x30,0xB5,0x01,0x24, ++0x41,0x69,0x04,0x23,0x00,0xF1,0x08,0x02, ++0x09,0x78,0x05,0x29,0x1C,0xD0,0x07,0xDC, ++0x01,0x29,0x15,0xD0,0x02,0x29,0x15,0xD0, ++0x04,0x29,0x22,0xD1,0x50,0x49,0x16,0xE0, ++0x07,0x29,0x13,0xD0,0x16,0x29,0x1C,0xD1, ++0x42,0x68,0x01,0x69,0x4D,0x4D,0x8B,0x18, ++0xAB,0x42,0x10,0xD8,0x41,0x61,0x4C,0x4B, ++0x83,0x62,0x02,0x60,0x81,0x61,0x11,0xE0, ++0x4A,0x49,0x04,0xE0,0x42,0x49,0x02,0xE0, ++0x49,0x49,0x00,0xE0,0x41,0x49,0x42,0x61, ++0x03,0x60,0x82,0x61,0x03,0xE0,0x41,0x61, ++0x02,0x60,0x81,0x61,0x00,0x21,0x81,0x62, ++0x00,0xE0,0x00,0x24,0x20,0x46,0x30,0xBD, ++0x3C,0x49,0x00,0x22,0x10,0xB5,0xC4,0x6A, ++0x01,0x61,0x39,0x49,0x02,0x77,0x01,0x62, ++0x3E,0x49,0x41,0x62,0x00,0xF1,0x08,0x01, ++0x41,0x61,0x81,0x61,0x01,0x21,0x82,0x62, ++0x01,0x60,0x00,0xF0,0x87,0xF8,0xA0,0x88, ++0x20,0xF4,0x80,0x70,0x80,0xB2,0x20,0xF4, ++0x00,0x70,0xA0,0x80,0x10,0xBD,0x37,0x49, ++0x35,0x48,0x08,0x60,0x36,0x49,0xC8,0x62, ++0x08,0x46,0xDD,0xE7,0x25,0x49,0xEB,0x20, ++0x08,0x81,0x70,0x47,0xF8,0xB5,0x00,0x25, ++0x31,0x4E,0x18,0x27,0xF4,0x6A,0xA0,0x88, ++0x81,0x05,0x01,0xD5,0x01,0x20,0xF8,0xBD, ++0xC1,0x05,0x09,0xD4,0x2D,0xB9,0x2D,0x49, ++0x65,0xF3,0x01,0x00,0x21,0x60,0xA0,0x80, ++0x06,0xE0,0x00,0x20,0x20,0x60,0x2B,0xE0, ++0xC0,0xF3,0x01,0x00,0xA8,0x42,0x27,0xD1, ++0x22,0x68,0x31,0x68,0xB0,0x69,0xD2,0x68, ++0x90,0x47,0x00,0x28,0x05,0xDD,0x32,0x6A, ++0x01,0x46,0x30,0x46,0x90,0x47,0xD8,0xB9, ++0x0B,0xE0,0x01,0x07,0x07,0xD5,0x40,0x07, ++0x16,0xD5,0x30,0x7F,0xA0,0xB1,0x20,0x68, ++0x00,0x68,0x80,0x47,0x10,0xE0,0x80,0x07, ++0x0E,0xD5,0x20,0x68,0x00,0x69,0x80,0x47, ++0x30,0x46,0xFF,0xF7,0xA1,0xFF,0x00,0x97, ++0x01,0x21,0x20,0x68,0x82,0x68,0x68,0x46, ++0x90,0x47,0x20,0x68,0x40,0x69,0xEC,0xE7, ++0x6D,0x1C,0x15,0xF0,0xFF,0x05,0xBE,0xD0, ++0x00,0x20,0xF8,0xBD,0x00,0x70,0x00,0x25, ++0x2B,0x52,0x03,0x20,0xBF,0x51,0x03,0x20, ++0x79,0x51,0x03,0x20,0xA9,0x51,0x03,0x20, ++0xF7,0x51,0x03,0x20,0x00,0x40,0x04,0x20, ++0xCF,0x52,0x03,0x20,0x00,0x32,0x05,0x20, ++0x19,0x53,0x03,0x20,0xC5,0x52,0x03,0x20, ++0x01,0x53,0x03,0x20,0x25,0x53,0x03,0x20, ++0x88,0x05,0x03,0x20,0x78,0xD4,0x02,0x20, ++0xE0,0x05,0x03,0x20,0x70,0xEB,0x03,0x20, ++0x01,0x46,0x5A,0x48,0x00,0xF0,0x70,0xB8, ++0x58,0x49,0x4A,0x69,0x92,0x06,0xFC,0xD5, ++0x08,0x60,0x70,0x47,0x70,0x47,0x30,0xB5, ++0x00,0x23,0x04,0x46,0x0D,0x46,0x03,0xE0, ++0xE0,0x5C,0xFF,0xF7,0xF1,0xFF,0x5B,0x1C, ++0xAB,0x42,0xF9,0xD3,0x28,0x46,0x30,0xBD, ++0x30,0xB4,0x4E,0x4C,0x83,0x78,0x42,0x78, ++0x01,0x78,0x20,0x46,0x30,0xBC,0x00,0xF0, ++0x61,0xB8,0x38,0xB5,0x4A,0xA0,0x49,0x4D, ++0xFC,0xF7,0x64,0xFE,0x4E,0x48,0x01,0x68, ++0x21,0xF4,0x00,0x41,0x01,0x60,0x4D,0x48, ++0x81,0x88,0x41,0xF0,0x20,0x01,0x81,0x80, ++0x01,0x88,0x21,0xF4,0xE0,0x71,0x41,0xF0, ++0x40,0x01,0x01,0x80,0x48,0x4C,0x20,0x68, ++0x20,0xF4,0x70,0x60,0x20,0x60,0x47,0xA0, ++0xFC,0xF7,0x4C,0xFE,0xE0,0x68,0x20,0xF0, ++0x0F,0x00,0xE0,0x60,0x4A,0xA0,0xFC,0xF7, ++0x45,0xFE,0x00,0x20,0x8D,0xF8,0x00,0x00, ++0x8D,0xF8,0x01,0x00,0x8D,0xF8,0x02,0x00, ++0x68,0x46,0xFF,0xF7,0xC9,0xFF,0x4B,0xA0, ++0xFC,0xF7,0x38,0xFE,0x03,0x20,0xA8,0x60, ++0x01,0x21,0x28,0x46,0x00,0xF0,0x1C,0xF8, ++0x38,0xBD,0x2E,0x48,0x03,0x21,0x81,0x60, ++0x01,0x68,0x00,0x21,0x00,0xF0,0x14,0xB8, ++0x2A,0x4B,0x10,0xB5,0x04,0x46,0x00,0x20, ++0x5A,0x69,0x12,0xF0,0x9E,0x01,0x05,0xD1, ++0xD1,0x07,0x02,0xD0,0x18,0x68,0x20,0x70, ++0x01,0x20,0x10,0xBD,0x43,0x48,0xC9,0x06, ++0xFB,0xD5,0x00,0x1D,0x10,0xBD,0xAC,0xE7, ++0x01,0x29,0x06,0xD1,0x41,0x69,0x49,0x06, ++0xFC,0xD5,0xC1,0x68,0x41,0xF0,0x40,0x01, ++0x02,0xE0,0xC1,0x68,0x21,0xF0,0x40,0x01, ++0xC1,0x60,0x70,0x47,0xF0,0xB5,0x04,0x46, ++0x8B,0xB0,0x0D,0x46,0x16,0x46,0x1F,0x46, ++0x60,0x69,0x40,0x06,0xFC,0xD5,0x36,0xA0, ++0xFC,0xF7,0xFC,0xFD,0xE0,0x68,0x40,0xF0, ++0x80,0x00,0xE0,0x60,0x28,0x22,0x36,0x49, ++0x01,0xA8,0x07,0xF0,0x80,0xED,0x01,0xA8, ++0x50,0xF8,0x25,0x10,0x33,0xA0,0xFC,0xF7, ++0xED,0xFD,0x31,0x48,0x14,0x38,0x30,0xF8, ++0x15,0x10,0xC9,0xB2,0x21,0x60,0x30,0xF8, ++0x15,0x00,0x00,0x0A,0x60,0x60,0x2C,0x48, ++0x2B,0x49,0x1A,0x38,0x1C,0x39,0x80,0x5D, ++0xC9,0x5D,0x08,0x43,0x40,0xF0,0x03,0x00, ++0xE0,0x60,0x03,0x20,0xA0,0x60,0x20,0x68, ++0x0B,0xB0,0xF0,0xBD,0x00,0x64,0x40,0x25, ++0x4D,0x44,0x72,0x76,0x5F,0x6D,0x63,0x75, ++0x5F,0x64,0x77,0x5F,0x75,0x61,0x72,0x74, ++0x30,0x5F,0x49,0x6E,0x69,0x74,0x0A,0x00, ++0x14,0x2C,0x02,0x25,0xC8,0x70,0x00,0x25, ++0x10,0x24,0x40,0x25,0x32,0x2E,0x4D,0x44, ++0x72,0x76,0x5F,0x6D,0x63,0x75,0x5F,0x64, ++0x77,0x5F,0x75,0x61,0x72,0x74,0x30,0x5F, ++0x49,0x6E,0x69,0x74,0x0A,0x00,0x00,0x00, ++0x33,0x2E,0x4D,0x44,0x72,0x76,0x5F,0x6D, ++0x63,0x75,0x5F,0x64,0x77,0x5F,0x75,0x61, ++0x72,0x74,0x30,0x5F,0x49,0x6E,0x69,0x74, ++0x0A,0x00,0x00,0x00,0x45,0x6E,0x64,0x20, ++0x6F,0x66,0x20,0x4D,0x44,0x72,0x76,0x5F, ++0x6D,0x63,0x75,0x5F,0x64,0x77,0x5F,0x75, ++0x61,0x72,0x74,0x30,0x5F,0x49,0x6E,0x69, ++0x74,0x0A,0x00,0x00,0x02,0x00,0x00,0x80, ++0x55,0x61,0x72,0x74,0x43,0x68,0x61,0x6E, ++0x5F,0x43,0x6F,0x6E,0x66,0x69,0x67,0x00, ++0xAC,0xEB,0x03,0x20,0x64,0x62,0x62,0x5F, ++0x6D,0x63,0x75,0x5F,0x64,0x77,0x5F,0x75, ++0x61,0x72,0x74,0x5F,0x42,0x52,0x28,0x25, ++0x64,0x29,0x0A,0x00,0xFF,0x48,0x00,0x68, ++0xC0,0xF3,0x01,0x00,0x02,0x28,0x01,0xD1, ++0x01,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0x70,0xB5,0x04,0x46,0xF9,0x4D,0x01,0x20, ++0x70,0x35,0x28,0x80,0x4F,0xF4,0x7A,0x70, ++0xFC,0xF7,0x7C,0xFC,0x03,0x20,0x28,0x80, ++0x28,0x80,0x00,0x20,0xA5,0xF2,0x74,0x45, ++0x9C,0xB1,0x01,0x2C,0x17,0xD0,0x02,0x2C, ++0x20,0xD0,0x03,0x2C,0x0A,0xD1,0x43,0xF2, ++0x77,0x01,0xA5,0xF8,0x7C,0x14,0xD4,0x21, ++0xA5,0xF8,0x78,0x14,0x4F,0xF4,0x00,0x41, ++0xA5,0xF8,0x90,0x14,0xA5,0xF8,0x74,0x04, ++0x70,0xBD,0x44,0xF2,0x44,0x01,0xA5,0xF8, ++0x7C,0x14,0x31,0x21,0x10,0xE0,0x43,0xF2, ++0x55,0x01,0xA5,0xF8,0x7C,0x14,0x40,0xF2, ++0x52,0x51,0xA5,0xF8,0x78,0x14,0x4F,0xF4, ++0x80,0x41,0xE9,0xE7,0x4F,0xF4,0x40,0x51, ++0xA5,0xF8,0x7C,0x14,0x40,0xF2,0x94,0x51, ++0xA5,0xF8,0x78,0x14,0xA5,0xF8,0x90,0x04, ++0xE0,0xE7,0x70,0x47,0xDB,0x48,0xDA,0x49, ++0x01,0x60,0x89,0x1C,0x41,0x60,0x81,0x60, ++0xD9,0x49,0xC1,0x60,0xD9,0x49,0x01,0x61, ++0x4F,0xF4,0x12,0x11,0x41,0x61,0x4F,0xF4, ++0xE8,0x11,0x81,0x61,0xD6,0x49,0x81,0x65, ++0xD6,0x49,0x41,0x65,0xD6,0x49,0xC1,0x65, ++0xD6,0x49,0x01,0x66,0xD6,0x49,0x41,0x66, ++0xD6,0x49,0x81,0x66,0x4F,0xF4,0x00,0x41, ++0xC1,0x66,0x49,0x10,0x01,0x67,0xD4,0x49, ++0x81,0x67,0x00,0x21,0x01,0x65,0x4F,0xF4, ++0x83,0x51,0xC0,0xF8,0x80,0x10,0x41,0xF2, ++0x3C,0x01,0xC0,0xF8,0x84,0x10,0xC0,0xF8, ++0x88,0x10,0xC0,0xF8,0x8C,0x10,0x70,0x47, ++0x2D,0xE9,0xF0,0x4F,0x07,0x46,0xC9,0xB0, ++0xFD,0xF7,0xA3,0xFB,0x00,0x21,0x45,0x90, ++0x43,0xA8,0x0A,0x46,0x06,0xC0,0x41,0xA8, ++0x06,0xC0,0x01,0x20,0xC5,0x49,0x40,0x90, ++0x3D,0xA8,0x1C,0xC9,0xF0,0x21,0x1C,0xC0, ++0x01,0xA8,0x07,0xF0,0x4A,0xEC,0xB5,0x4C, ++0x00,0x26,0xC1,0x4D,0x78,0x34,0x48,0x96, ++0xA2,0x46,0x2E,0x80,0x4F,0xF4,0x70,0x41, ++0xA9,0x80,0x2E,0x81,0x45,0xF6,0xA5,0x20, ++0xA8,0x81,0x28,0x8C,0x47,0x90,0x4F,0xF4, ++0x58,0x50,0x28,0x84,0xA5,0xF2,0xC4,0x55, ++0x38,0x46,0xFF,0xF7,0x5D,0xFF,0xB4,0xF8, ++0x00,0x90,0x20,0x88,0x00,0x27,0xAB,0x46, ++0x00,0xF4,0x70,0x40,0x46,0x90,0x07,0xEB, ++0x47,0x00,0x01,0xA9,0x01,0xEB,0xC0,0x05, ++0x3D,0xA8,0x50,0xF8,0x27,0x00,0x28,0x60, ++0x80,0xB2,0xFD,0xF7,0x58,0xFB,0x00,0x24, ++0x4F,0xF0,0x01,0x0C,0xBC,0xEB,0x14,0x1F, ++0x05,0xD1,0x48,0x46,0x64,0xF3,0x07,0x10, ++0x80,0x46,0xCC,0x20,0x06,0xE0,0x20,0x09, ++0x06,0xD1,0x48,0x46,0x64,0xF3,0x03,0x00, ++0x80,0x46,0x33,0x20,0xAB,0xF8,0xF4,0x05, ++0xAA,0xF8,0x00,0x80,0x00,0x20,0xDF,0xF8, ++0x84,0xE2,0x03,0x46,0x5A,0x46,0xA2,0xF8, ++0xC0,0x35,0x1E,0xF8,0x00,0x10,0xA2,0xF8, ++0xC0,0x15,0xB2,0xF8,0xC0,0x15,0x09,0x04, ++0xFB,0xD5,0xB2,0xF8,0xC0,0x15,0x11,0xF4, ++0xC0,0x4F,0x03,0xD1,0x40,0x1C,0xC0,0xB2, ++0x03,0x28,0xEC,0xD3,0xA2,0xF8,0xC0,0x35, ++0x03,0x28,0x0C,0xD1,0x04,0xF0,0x0F,0x00, ++0x3E,0xB9,0xBC,0xEB,0x14,0x1F,0x01,0xD1, ++0xA8,0x60,0x02,0xE0,0x21,0x09,0x00,0xD1, ++0x68,0x60,0x76,0x1C,0xF6,0xB2,0xE0,0x43, ++0x00,0x07,0x1E,0xD1,0x00,0x2E,0x1C,0xD0, ++0xBC,0xEB,0x14,0x1F,0xC5,0xF8,0x14,0xC0, ++0x09,0xD1,0xA8,0x68,0x76,0x1E,0x81,0x19, ++0x87,0xA0,0x29,0x61,0xFC,0xF7,0x6A,0xFC, ++0xA9,0x68,0x8C,0xA0,0x0A,0xE0,0x20,0x09, ++0x0A,0xD1,0x68,0x68,0x76,0x1E,0x81,0x19, ++0x8F,0xA0,0xE9,0x60,0xFC,0xF7,0x5E,0xFC, ++0x69,0x68,0x94,0xA0,0xFC,0xF7,0x5A,0xFC, ++0x00,0x26,0x64,0x1C,0xE4,0xB2,0x20,0x2C, ++0x9A,0xD3,0x7F,0x1C,0xBF,0xB2,0x03,0x2F, ++0x89,0xD3,0x00,0x20,0x5C,0x46,0xAB,0xF8, ++0xF4,0x05,0x45,0x98,0xFD,0xF7,0xE7,0xFA, ++0x00,0x21,0x01,0xAB,0x01,0xEB,0x41,0x00, ++0x03,0xEB,0xC0,0x00,0x42,0x69,0xFA,0xB1, ++0x40,0x9A,0x4A,0xB1,0x00,0x22,0x40,0x92, ++0xC2,0x68,0x41,0x92,0x02,0x69,0x42,0x92, ++0x42,0x68,0x43,0x92,0x82,0x68,0x44,0x92, ++0xC2,0x68,0x41,0x9D,0xAA,0x42,0x00,0xD9, ++0x41,0x92,0x02,0x69,0x42,0x9D,0xAA,0x42, ++0x00,0xD9,0x42,0x92,0x42,0x68,0x43,0x9D, ++0xAA,0x42,0x00,0xD2,0x43,0x92,0x80,0x68, ++0x44,0x9A,0x90,0x42,0x00,0xD2,0x44,0x90, ++0x49,0x1C,0x89,0xB2,0x03,0x29,0xD5,0xD3, ++0x43,0x99,0x41,0x98,0x43,0x9A,0x48,0x40, ++0x41,0x99,0x00,0xF0,0x01,0x00,0x44,0x9B, ++0x11,0x44,0x44,0x9A,0x00,0xEB,0x51,0x01, ++0x42,0x98,0x50,0x40,0x42,0x9A,0x00,0xF0, ++0x01,0x00,0x1A,0x44,0x00,0xEB,0x52,0x00, ++0x41,0xEA,0x00,0x10,0x46,0x99,0xC0,0xB2, ++0x08,0x43,0xAA,0xF8,0x00,0x00,0xA4,0xF8, ++0xD0,0x05,0xBA,0xF8,0x00,0x10,0x6C,0xA0, ++0xFC,0xF7,0xFC,0xFB,0x47,0x98,0xA4,0xF8, ++0xE4,0x05,0x48,0x98,0x49,0xB0,0xBD,0xE8, ++0xF0,0x8F,0x2D,0xE9,0xF0,0x4F,0xC9,0xB0, ++0xFD,0xF7,0x9B,0xFA,0x00,0x21,0x45,0x90, ++0x43,0xA8,0x0A,0x46,0x3D,0xAC,0x06,0xC0, ++0x41,0xA8,0x06,0xC0,0x01,0x20,0x40,0x90, ++0x40,0x48,0x0C,0x30,0x0E,0xC8,0x0E,0xC4, ++0xFF,0xF7,0x64,0xFE,0x01,0x28,0x01,0xD1, ++0x00,0x20,0xE3,0xE7,0xF0,0x21,0x01,0xA8, ++0x07,0xF0,0x3A,0xEB,0x2D,0x49,0x00,0x26, ++0x39,0x48,0x78,0x31,0x48,0x96,0x8A,0x46, ++0x06,0x80,0x4F,0xF4,0x70,0x43,0x83,0x80, ++0x06,0x81,0x45,0xF6,0xA5,0x23,0x83,0x81, ++0x03,0x8C,0x47,0x93,0x4F,0xF4,0x58,0x53, ++0x03,0x84,0xA0,0xF2,0xC4,0x5B,0xB1,0xF8, ++0x00,0x90,0x09,0x88,0x00,0x27,0x01,0xF4, ++0x70,0x41,0x46,0x91,0x07,0xEB,0x47,0x00, ++0x01,0xA9,0x01,0xEB,0xC0,0x05,0x3D,0xA8, ++0x50,0xF8,0x27,0x00,0x28,0x60,0x80,0xB2, ++0xFD,0xF7,0x4D,0xFA,0x00,0x24,0x4F,0xF0, ++0x01,0x0C,0xBC,0xEB,0x14,0x1F,0x05,0xD1, ++0x48,0x46,0x64,0xF3,0x07,0x10,0x80,0x46, ++0xCC,0x20,0x06,0xE0,0x20,0x09,0x06,0xD1, ++0x48,0x46,0x64,0xF3,0x03,0x00,0x80,0x46, ++0x33,0x20,0xAB,0xF8,0xF4,0x05,0xAA,0xF8, ++0x00,0x80,0x00,0x20,0xDF,0xF8,0x6C,0xE0, ++0x03,0x46,0x5A,0x46,0xA2,0xF8,0xC0,0x35, ++0x1E,0xF8,0x00,0x10,0xA2,0xF8,0xC0,0x15, ++0xB2,0xF8,0xC0,0x15,0x09,0x04,0xFB,0xD5, ++0xB2,0xF8,0xC0,0x15,0x11,0xF4,0xC0,0x4F, ++0x03,0xD1,0x40,0x1C,0xC0,0xB2,0x03,0x28, ++0xEC,0xD3,0xA2,0xF8,0xC0,0x35,0x03,0x28, ++0x6D,0xD1,0x5F,0xE0,0x04,0x24,0x00,0x25, ++0x01,0x00,0x1D,0x00,0x00,0x3E,0x30,0x25, ++0x77,0x30,0x1F,0x00,0xDC,0x00,0x1E,0x00, ++0x01,0x06,0x01,0x00,0x14,0x28,0x50,0x00, ++0x77,0x30,0x00,0x30,0x55,0x30,0x45,0x40, ++0xD4,0x00,0x94,0x05,0x52,0x05,0x31,0x00, ++0x1F,0x1E,0x24,0x00,0xD4,0xEB,0x03,0x20, ++0xC4,0x25,0x00,0x25,0xC8,0x04,0x03,0x20, ++0x70,0x68,0x5F,0x64,0x61,0x74,0x61,0x2D, ++0x3E,0x6D,0x61,0x78,0x5F,0x64,0x71,0x5B, ++0x31,0x5D,0x20,0x3D,0x20,0x25,0x23,0x78, ++0x0A,0x00,0x00,0x00,0x70,0x68,0x5F,0x64, ++0x61,0x74,0x61,0x2D,0x3E,0x6D,0x69,0x6E, ++0x5F,0x64,0x71,0x5B,0x31,0x5D,0x20,0x3D, ++0x20,0x25,0x23,0x78,0x0A,0x00,0x00,0x00, ++0x70,0x68,0x5F,0x64,0x61,0x74,0x61,0x2D, ++0x3E,0x6D,0x61,0x78,0x5F,0x64,0x71,0x5B, ++0x30,0x5D,0x20,0x3D,0x20,0x25,0x23,0x78, ++0x0A,0x00,0x00,0x00,0x70,0x68,0x5F,0x64, ++0x61,0x74,0x61,0x2D,0x3E,0x6D,0x69,0x6E, ++0x5F,0x64,0x71,0x5B,0x30,0x5D,0x20,0x3D, ++0x20,0x25,0x23,0x78,0x0A,0x00,0x00,0x00, ++0x75,0x33,0x32,0x44,0x71,0x73,0x50,0x68, ++0x41,0x64,0x64,0x72,0x3D,0x25,0x30,0x34, ++0x58,0x0A,0x00,0x00,0x04,0xF0,0x0F,0x00, ++0x3E,0xB9,0xBC,0xEB,0x14,0x1F,0x01,0xD1, ++0xA8,0x60,0x02,0xE0,0x21,0x09,0x00,0xD1, ++0x68,0x60,0x76,0x1C,0xF6,0xB2,0xE0,0x43, ++0x00,0x07,0x22,0xD1,0x00,0x2E,0x20,0xD0, ++0xBC,0xEB,0x14,0x1F,0xC5,0xF8,0x14,0xC0, ++0x0B,0xD1,0xA8,0x68,0x76,0x1E,0x81,0x19, ++0xAF,0xF2,0xBC,0x00,0x29,0x61,0xFC,0xF7, ++0xFD,0xFA,0xAF,0xF2,0xA8,0x00,0xA9,0x68, ++0x0C,0xE0,0x20,0x09,0x0C,0xD1,0x68,0x68, ++0x76,0x1E,0x81,0x19,0xAF,0xF2,0xA0,0x00, ++0xE9,0x60,0xFC,0xF7,0xEF,0xFA,0xAF,0xF2, ++0x8C,0x00,0x69,0x68,0xFC,0xF7,0xEA,0xFA, ++0x00,0x26,0x64,0x1C,0xE4,0xB2,0x20,0x2C, ++0xFF,0xF4,0x35,0xAF,0x7F,0x1C,0xBF,0xB2, ++0x03,0x2F,0xFF,0xF4,0x23,0xAF,0x00,0x20, ++0x5C,0x46,0xAB,0xF8,0xF4,0x05,0x45,0x98, ++0xFD,0xF7,0x75,0xF9,0x00,0x21,0x01,0xAB, ++0x01,0xEB,0x41,0x00,0x03,0xEB,0xC0,0x00, ++0x42,0x69,0xFA,0xB1,0x40,0x9A,0x4A,0xB1, ++0x00,0x22,0x40,0x92,0xC2,0x68,0x41,0x92, ++0x02,0x69,0x42,0x92,0x42,0x68,0x43,0x92, ++0x82,0x68,0x44,0x92,0xC2,0x68,0x41,0x9D, ++0xAA,0x42,0x00,0xD9,0x41,0x92,0x02,0x69, ++0x42,0x9D,0xAA,0x42,0x00,0xD9,0x42,0x92, ++0x42,0x68,0x43,0x9D,0xAA,0x42,0x00,0xD2, ++0x43,0x92,0x80,0x68,0x44,0x9A,0x90,0x42, ++0x00,0xD2,0x44,0x90,0x49,0x1C,0x89,0xB2, ++0x03,0x29,0xD5,0xD3,0x43,0x99,0x41,0x98, ++0x43,0x9A,0x48,0x40,0x41,0x99,0x00,0xF0, ++0x01,0x00,0x44,0x9B,0x11,0x44,0x44,0x9A, ++0x00,0xEB,0x51,0x01,0x42,0x98,0x50,0x40, ++0x42,0x9A,0x00,0xF0,0x01,0x00,0x1A,0x44, ++0x00,0xEB,0x52,0x00,0x41,0xEA,0x00,0x10, ++0xC5,0xB2,0x46,0x98,0x05,0x43,0xAA,0xF8, ++0x00,0x50,0xA4,0xF8,0xD0,0x55,0xBA,0xF8, ++0x00,0x10,0xAF,0xF2,0x34,0x10,0xFC,0xF7, ++0x89,0xFA,0x05,0x49,0x43,0xF2,0x55,0x00, ++0x00,0xEB,0x05,0x40,0x08,0x60,0x47,0x98, ++0xA4,0xF8,0xE4,0x05,0x48,0x98,0x85,0xE6, ++0x60,0x3E,0x30,0x25,0x4F,0xF0,0x28,0x50, ++0xD0,0xF8,0x6C,0x15,0xC9,0x07,0xFB,0xD0, ++0x01,0x21,0xC0,0xF8,0x70,0x15,0x70,0x47, ++0x60,0x4A,0x00,0x06,0x30,0xB5,0x00,0x0C, ++0x10,0x60,0x00,0x20,0x50,0x60,0x4D,0xF2, ++0xD0,0x11,0x91,0x60,0x03,0x21,0x11,0x62, ++0x47,0x21,0x51,0x62,0x90,0x62,0xD0,0x62, ++0x4F,0xF6,0xFF,0x74,0x14,0x63,0xFE,0x25, ++0xD5,0x67,0x01,0x23,0x93,0x66,0xFF,0xF7, ++0xDD,0xFF,0x4F,0xF4,0x00,0x70,0x10,0x62, ++0x94,0x63,0xD5,0x67,0x93,0x66,0xFF,0xF7, ++0xD5,0xFF,0xFF,0x20,0xD0,0x67,0x10,0x69, ++0x30,0xBD,0xC1,0xB2,0x10,0x22,0x00,0xB5, ++0x42,0xEA,0x01,0x21,0x4B,0x4A,0x11,0x60, ++0xC0,0xF3,0x07,0x20,0x50,0x60,0x03,0x20, ++0x10,0x62,0x47,0x20,0x50,0x62,0x00,0x20, ++0x90,0x62,0xD0,0x62,0x4F,0xF6,0xFF,0x70, ++0x10,0x63,0xFE,0x20,0xD0,0x67,0x01,0x20, ++0x90,0x66,0xFF,0xF7,0xB7,0xFF,0xFF,0x20, ++0xD0,0x67,0x00,0xBD,0x80,0xB2,0x00,0xB5, ++0xFF,0xF7,0xDF,0xFF,0x04,0x20,0xFF,0xF7, ++0xB7,0xFF,0xC0,0x07,0xFA,0xD0,0x5D,0xF8, ++0x04,0xEB,0x08,0x20,0xB0,0xE7,0xC2,0xB2, ++0x15,0x23,0x00,0xB5,0x43,0xEA,0x02,0x23, ++0x36,0x4A,0x13,0x60,0xCB,0xB2,0xC0,0xF3, ++0x07,0x20,0x40,0xEA,0x03,0x20,0x50,0x60, ++0xC1,0xF3,0x07,0x20,0x40,0xF4,0x50,0x40, ++0x90,0x60,0x05,0x20,0x10,0x62,0x47,0x20, ++0x50,0x62,0x00,0x20,0x90,0x62,0xD0,0x62, ++0x4F,0xF6,0xFF,0x70,0x10,0x63,0xFE,0x20, ++0xD0,0x67,0x01,0x20,0x90,0x66,0xFF,0xF7, ++0x85,0xFF,0xFF,0x20,0xD0,0x67,0x00,0xBD, ++0x30,0xB5,0x04,0x46,0x42,0xF2,0x10,0x05, ++0x28,0x46,0xFF,0xF7,0xC7,0xFF,0x06,0x2C, ++0x0A,0xD8,0x23,0x49,0x51,0xF8,0x24,0x40, ++0x64,0xF3,0x5F,0x30,0x01,0x46,0x28,0x46, ++0xFF,0xF7,0xC9,0xFF,0x20,0x46,0x30,0xBD, ++0x1E,0x48,0x30,0xBD,0x30,0xB5,0x04,0x46, ++0x42,0xF2,0x12,0x05,0x28,0x46,0xFF,0xF7, ++0xB1,0xFF,0xE1,0x1E,0x4F,0xF6,0x8F,0x72, ++0x07,0x29,0x0D,0xD8,0x10,0x40,0x16,0x49, ++0x1C,0x31,0x01,0xEB,0x84,0x01,0x51,0xF8, ++0x0C,0x4C,0x40,0xEA,0x04,0x11,0x28,0x46, ++0xFF,0xF7,0xAD,0xFF,0x20,0x46,0x30,0xBD, ++0x10,0x40,0x00,0x09,0xA0,0xF5,0x80,0x30, ++0x30,0xBD,0x30,0xB5,0x04,0x46,0x42,0xF2, ++0x12,0x05,0x28,0x46,0xFF,0xF7,0x92,0xFF, ++0x0A,0x2C,0x09,0xD8,0x4E,0xF2,0xFF,0x01, ++0x08,0x40,0x40,0xEA,0x04,0x21,0x28,0x46, ++0xFF,0xF7,0x95,0xFF,0x20,0x46,0x30,0xBD, ++0x00,0xF4,0x60,0x40,0x00,0x0A,0xA0,0xF5, ++0x80,0x30,0x30,0xBD,0x00,0x05,0x00,0x2A, ++0xEC,0xEB,0x03,0x20,0x00,0x00,0xFF,0xFF, ++0x2E,0x49,0x0A,0x88,0x10,0x44,0x80,0xB2, ++0xFF,0x28,0x08,0x80,0x01,0xD3,0xFF,0x38, ++0x08,0x80,0x48,0x88,0x0A,0x88,0x10,0x44, ++0x80,0xB2,0xFF,0x28,0x48,0x80,0x01,0xD3, ++0xFF,0x38,0x48,0x80,0x70,0x47,0x25,0x48, ++0x41,0x88,0x00,0x88,0x01,0x43,0x01,0xD1, ++0x01,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0x20,0x49,0x00,0x20,0x08,0x80,0x48,0x80, ++0x70,0x47,0xF0,0xB5,0x06,0x46,0x0F,0x46, ++0x15,0x46,0xFF,0xF7,0xF5,0xFF,0x00,0x24, ++0x03,0xE0,0x28,0x5D,0xFF,0xF7,0xD4,0xFF, ++0x64,0x1C,0x9C,0x42,0xF9,0xD3,0x17,0x49, ++0x48,0x88,0x09,0x88,0xC0,0xB2,0xC0,0xF5, ++0xFF,0x72,0x51,0x1A,0x31,0x70,0x38,0x70, ++0xF0,0xBD,0x2D,0xE9,0xF8,0x43,0x00,0x26, ++0x80,0x46,0x89,0x46,0x35,0x46,0x6F,0x46, ++0x34,0x46,0x0C,0xE0,0x18,0xF8,0x04,0x00, ++0xFF,0x21,0x30,0x44,0x08,0xF0,0xD8,0xE8, ++0x68,0x18,0x0E,0x46,0xFF,0x21,0x08,0xF0, ++0xD4,0xE8,0x64,0x1C,0x0D,0x46,0x4C,0x45, ++0xF0,0xD3,0x70,0x19,0xFF,0x21,0x08,0xF0, ++0xCC,0xE8,0xC1,0xF1,0xFF,0x00,0x38,0x70, ++0x7D,0x70,0xBD,0xF8,0x00,0x00,0xBD,0xE8, ++0xF8,0x83,0x00,0x00,0xCC,0x04,0x03,0x20, ++0x00,0x22,0x01,0x28,0x0B,0xD0,0x02,0x28, ++0x0C,0xD0,0x03,0x28,0x12,0xD0,0x04,0x28, ++0x02,0xD1,0x01,0x22,0x81,0xF8,0x2E,0x20, ++0x81,0xF8,0x27,0x00,0x70,0x47,0x81,0xF8, ++0x21,0x20,0xF9,0xE7,0x21,0x31,0x8A,0x70, ++0xCA,0x70,0x4A,0x70,0x0A,0x70,0x4A,0x73, ++0x21,0x39,0xF1,0xE7,0x81,0xF8,0x25,0x20, ++0xEE,0xE7,0x70,0x47,0x90,0xF8,0x27,0x00, ++0x04,0x28,0x01,0xD1,0x01,0x20,0x70,0x47, ++0x00,0x20,0x70,0x47,0x00,0xEB,0x80,0x00, ++0x70,0xB5,0x01,0xEB,0xC0,0x05,0x0C,0x46, ++0x95,0xF8,0x53,0x00,0x08,0xB9,0x24,0x20, ++0x07,0xE0,0x95,0xF8,0x53,0x00,0x00,0xF0, ++0xA9,0xFC,0x95,0xF8,0x54,0x00,0x10,0xB1, ++0x2C,0x20,0x20,0x21,0x01,0xE0,0x24,0x20, ++0x10,0x21,0x0D,0x4A,0x10,0x44,0x03,0x78, ++0x0B,0x43,0x03,0x70,0x95,0xF8,0x54,0x00, ++0x40,0xB1,0x92,0xF8,0x2C,0x00,0x80,0x06, ++0x0C,0xD5,0x94,0xF8,0x2E,0x00,0x01,0x28, ++0xF7,0xD0,0x07,0xE0,0x92,0xF8,0x24,0x00, ++0xC0,0x06,0x03,0xD5,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF7,0xD0,0x01,0x20,0x70,0xBD, ++0x00,0x40,0x00,0x25,0xF9,0x49,0x00,0x20, ++0x08,0x70,0x70,0x47,0xF7,0x48,0x00,0x78, ++0x70,0x47,0x70,0xB5,0x05,0x46,0x08,0x46, ++0xF5,0x49,0x1C,0x46,0x01,0x60,0x69,0x68, ++0x41,0x60,0x99,0x6B,0x81,0x60,0x02,0x73, ++0xD9,0x68,0x05,0xF0,0xAE,0xFD,0xE0,0x68, ++0x0D,0x21,0x22,0x46,0x00,0xF0,0xEC,0xFD, ++0xBD,0xE8,0x70,0x40,0x00,0xF0,0x48,0xBE, ++0x30,0xB5,0x05,0x46,0x89,0xB0,0x0C,0x46, ++0x24,0x22,0xEA,0xA1,0x68,0x46,0x07,0xF0, ++0x56,0xE8,0x24,0x20,0xE0,0x63,0x80,0x20, ++0x84,0xF8,0x34,0x00,0xA8,0x68,0x24,0x28, ++0x02,0xD2,0x4F,0xF0,0xFF,0x30,0x00,0xE0, ++0x24,0x38,0xA0,0x63,0x24,0x21,0x22,0x46, ++0x68,0x46,0x00,0xF0,0xCD,0xFD,0x09,0xB0, ++0x30,0xBD,0x30,0xB5,0x05,0x46,0x85,0xB0, ++0x0C,0x46,0x14,0x22,0xE4,0xA1,0x68,0x46, ++0x07,0xF0,0x38,0xE8,0x30,0x34,0x60,0x78, ++0x8D,0xF8,0x02,0x00,0xA0,0x78,0x8D,0xF8, ++0x0C,0x00,0xE0,0x78,0x8D,0xF8,0x0D,0x00, ++0x12,0x20,0xE0,0x60,0x80,0x20,0x20,0x71, ++0x30,0x3C,0xA8,0x68,0x12,0x28,0x02,0xD2, ++0x4F,0xF0,0xFF,0x30,0x00,0xE0,0x12,0x38, ++0xA0,0x63,0x12,0x21,0x22,0x46,0x68,0x46, ++0x00,0xF0,0xA6,0xFD,0x05,0xB0,0x30,0xBD, ++0x7C,0xB5,0x14,0x46,0x1A,0x46,0x00,0x23, ++0x6D,0x46,0x1E,0x46,0x49,0x1E,0x48,0xC5, ++0x0B,0x0A,0x8D,0xF8,0x03,0x10,0x8D,0xF8, ++0x02,0x30,0x0B,0x0C,0x09,0x0E,0x8D,0xF8, ++0x01,0x30,0x8D,0xF8,0x00,0x10,0x21,0x0A, ++0x8D,0xF8,0x07,0x40,0x8D,0xF8,0x06,0x10, ++0x21,0x0C,0x8D,0xF8,0x05,0x10,0x21,0x0E, ++0x8D,0xF8,0x04,0x10,0x08,0x21,0xD1,0x63, ++0x80,0x21,0x82,0xF8,0x34,0x10,0x80,0x68, ++0x08,0x28,0x02,0xD2,0x4F,0xF0,0xFF,0x30, ++0x00,0xE0,0x08,0x38,0x90,0x63,0x08,0x21, ++0x68,0x46,0x00,0xF0,0x75,0xFD,0x7C,0xBD, ++0x00,0x22,0xCA,0x63,0x81,0xF8,0x34,0x20, ++0x8A,0x63,0x00,0x7D,0x80,0x07,0x03,0xD5, ++0x01,0x20,0x81,0xF8,0x35,0x00,0x01,0xE0, ++0x81,0xF8,0x35,0x20,0x00,0x20,0x70,0x47, ++0x00,0x20,0x02,0x46,0xC8,0x63,0x81,0xF8, ++0x34,0x00,0x88,0x63,0x91,0xF8,0x35,0x30, ++0x00,0x2B,0x06,0xD0,0x01,0x20,0x02,0x23, ++0x01,0xF8,0x31,0x3F,0x3A,0x23,0x4B,0x70, ++0x8A,0x70,0x70,0x47,0x00,0x20,0xC8,0x63, ++0x81,0xF8,0x34,0x00,0x88,0x63,0x70,0x47, ++0xAC,0xA2,0x08,0xB5,0x12,0x68,0x00,0x92, ++0x04,0x22,0xCA,0x63,0x80,0x22,0x81,0xF8, ++0x34,0x20,0x80,0x68,0x04,0x28,0x02,0xD2, ++0x4F,0xF0,0xFF,0x30,0x00,0xE0,0x00,0x1F, ++0x88,0x63,0x0A,0x46,0x04,0x21,0x68,0x46, ++0x00,0xF0,0x36,0xFD,0x08,0xBD,0x2D,0xE9, ++0xFC,0x5F,0x04,0x46,0x00,0x20,0x0E,0x46, ++0x01,0x90,0x80,0x46,0x00,0x90,0x21,0x7C, ++0x89,0x06,0x11,0xD5,0x61,0x7D,0x8D,0xF8, ++0x00,0x10,0x21,0x7D,0x8D,0xF8,0x01,0x10, ++0xE1,0x7C,0x8D,0xF8,0x02,0x10,0xA1,0x7C, ++0x8D,0xF8,0x03,0x10,0xE1,0x7D,0x8D,0xF8, ++0x05,0x10,0x21,0x7E,0x8D,0xF8,0x04,0x10, ++0xBD,0xF8,0x04,0x10,0x49,0x02,0xF1,0x63, ++0xF5,0x6B,0x80,0x21,0x86,0xF8,0x34,0x10, ++0xA1,0x68,0xF2,0x6B,0x91,0x42,0x02,0xD2, ++0x4F,0xF0,0xFF,0x31,0x01,0xE0,0xF2,0x6B, ++0x89,0x1A,0xB1,0x63,0x4F,0xF4,0x00,0x59, ++0xDF,0xF8,0x24,0xA2,0xD6,0xF8,0x38,0xB1, ++0x1A,0xE0,0x4D,0x45,0x4F,0x46,0x00,0xD8, ++0x2F,0x46,0x60,0x7B,0xB1,0x78,0x88,0x42, ++0x08,0xD1,0xDA,0xF8,0x00,0x00,0x00,0x9A, ++0x79,0x0A,0x03,0x68,0x58,0x46,0x98,0x47, ++0x00,0xF0,0xFF,0x08,0x32,0x46,0x39,0x46, ++0x58,0x46,0x00,0xF0,0xB1,0xFC,0x00,0x99, ++0xED,0x1B,0x01,0xEB,0x57,0x21,0x00,0x91, ++0x00,0x2D,0xE2,0xD1,0x61,0x7B,0xB2,0x78, ++0x91,0x42,0x03,0xD1,0xB8,0xF1,0x00,0x0F, ++0x00,0xD0,0xFC,0x20,0xBD,0xE8,0xFC,0x9F, ++0x2D,0xE9,0xFE,0x4F,0x4F,0xF0,0x00,0x08, ++0x04,0x46,0x0E,0x46,0xCD,0xF8,0x04,0x80, ++0xC1,0x46,0xCD,0xF8,0x00,0x80,0x40,0x46, ++0x21,0x7C,0x89,0x06,0x11,0xD5,0x61,0x7D, ++0x8D,0xF8,0x00,0x10,0x21,0x7D,0x8D,0xF8, ++0x01,0x10,0xE1,0x7C,0x8D,0xF8,0x02,0x10, ++0xA1,0x7C,0x8D,0xF8,0x03,0x10,0xE1,0x7D, ++0x8D,0xF8,0x05,0x10,0x21,0x7E,0x8D,0xF8, ++0x04,0x10,0xBD,0xF8,0x04,0x10,0x49,0x02, ++0xF1,0x63,0xF5,0x6B,0x86,0xF8,0x34,0x00, ++0xA0,0x68,0xF1,0x6B,0x88,0x42,0x02,0xD2, ++0x4F,0xF0,0xFF,0x30,0x01,0xE0,0xF1,0x6B, ++0x40,0x1A,0xB0,0x63,0x4F,0xF4,0x00,0x5B, ++0xD6,0xF8,0x38,0x01,0xDF,0xF8,0x60,0xA1, ++0x02,0x90,0x1B,0xE0,0x5D,0x45,0x5F,0x46, ++0x00,0xD8,0x2F,0x46,0x02,0x98,0x32,0x46, ++0x39,0x46,0x00,0xF0,0xD3,0xFC,0xB1,0x78, ++0x80,0x46,0x60,0x7B,0x88,0x42,0x08,0xD1, ++0xDA,0xF8,0x00,0x00,0x00,0x9A,0x79,0x0A, ++0x43,0x68,0x02,0x98,0x98,0x47,0x00,0xF0, ++0xFF,0x09,0x00,0x98,0xED,0x1B,0x00,0xEB, ++0x57,0x20,0x00,0x90,0x00,0x2D,0xE1,0xD1, ++0x60,0x7B,0xB1,0x78,0x88,0x42,0x04,0xD1, ++0xB9,0xF1,0x00,0x0F,0x01,0xD0,0x4F,0xF0, ++0xFC,0x08,0x40,0x46,0xBD,0xE8,0xFE,0x8F, ++0x30,0xB5,0x04,0x46,0x40,0x7F,0x8D,0xB0, ++0x01,0x28,0x59,0xD1,0x00,0x20,0x00,0xF0, ++0xEF,0xFA,0x00,0xEB,0x80,0x00,0x04,0xEB, ++0xC0,0x05,0x95,0xF8,0x53,0x00,0x00,0xF0, ++0xE1,0xFA,0x00,0x20,0x60,0x77,0x60,0x69, ++0x05,0xA9,0x05,0xF0,0xF2,0xFB,0xE8,0x6C, ++0x1F,0x28,0x1F,0xD1,0x05,0x98,0x35,0x49, ++0x88,0x42,0x1B,0xD1,0x9D,0xF8,0x21,0x00, ++0x01,0x09,0x17,0xD1,0x21,0x78,0x88,0x42, ++0x14,0xD8,0x07,0x98,0xA0,0x63,0x9D,0xF8, ++0x24,0x00,0x03,0x28,0x15,0xD1,0x21,0x46, ++0x05,0xA8,0xFF,0xF7,0x7A,0xFE,0x2B,0xE0, ++0x9D,0xF8,0x20,0x00,0x00,0x06,0x20,0x46, ++0x08,0xD5,0x05,0xF0,0x13,0xFC,0x02,0x22, ++0x23,0x46,0x50,0xE0,0x07,0x98,0x00,0x28, ++0xF9,0xD0,0xF1,0xE7,0x05,0xF0,0x14,0xFC, ++0xF5,0xE7,0x12,0x28,0x04,0xD1,0x21,0x46, ++0x05,0xA8,0xFF,0xF7,0x45,0xFE,0x13,0xE0, ++0x1F,0x49,0xE0,0x28,0x05,0xD3,0x22,0x46, ++0x05,0xA8,0x0B,0x68,0x01,0xA9,0x98,0x47, ++0x0A,0xE0,0x4B,0x68,0x22,0x46,0x01,0xA9, ++0x05,0xA8,0x98,0x47,0x9D,0xF8,0x24,0x10, ++0x11,0xB9,0x04,0x4A,0x01,0x21,0x11,0x70, ++0x23,0x46,0x10,0xB9,0x00,0x22,0x2A,0xE0, ++0x2D,0xE0,0x27,0xE0,0xD0,0x04,0x03,0x20, ++0x55,0x53,0x42,0x53,0x00,0x80,0x00,0x00, ++0x1F,0x00,0x00,0x00,0x47,0x43,0x52,0x45, ++0x41,0x44,0x45,0x52,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x0A, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x00, ++0x7C,0xD4,0x02,0x20,0x55,0x53,0x42,0x43, ++0x84,0xD4,0x02,0x20,0x01,0x22,0x01,0xA9, ++0x05,0xA8,0xFF,0xF7,0xE6,0xFD,0x0D,0xB0, ++0x30,0xBD,0x2D,0xE9,0xF0,0x47,0x0D,0x46, ++0x40,0x7B,0x14,0x46,0x91,0x78,0x4F,0xF0, ++0x00,0x08,0x01,0x27,0x4F,0xF0,0x02,0x09, ++0x88,0x42,0x4F,0xF0,0x3A,0x0A,0x46,0x46, ++0x19,0xD1,0xF9,0x48,0x00,0x68,0xC0,0x68, ++0x80,0x47,0x01,0x28,0x09,0xD0,0x02,0x28, ++0x11,0xD1,0x06,0x20,0x2F,0x73,0x04,0xF8, ++0x31,0x0F,0x28,0x20,0x60,0x70,0xA6,0x70, ++0x06,0xE0,0x2E,0x73,0x04,0xF8,0x31,0x6F, ++0x66,0x70,0xA6,0x70,0x4F,0xF0,0x01,0x08, ++0x40,0x46,0xBD,0xE8,0xF0,0x87,0x2F,0x73, ++0x04,0xF8,0x31,0x9F,0x50,0x46,0xED,0xE7, ++0x00,0x22,0xCA,0x63,0x81,0xF8,0x34,0x20, ++0x8A,0x63,0x00,0x7D,0x00,0x28,0x06,0xD0, ++0x01,0x20,0x05,0x23,0x01,0xF8,0x31,0x3F, ++0x24,0x23,0x4B,0x70,0x8A,0x70,0x70,0x47, ++0x2D,0xE9,0xF0,0x41,0x04,0x46,0xC0,0x7D, ++0xAD,0xF6,0x08,0x0D,0xDE,0x4E,0x0D,0x46, ++0xE8,0xB1,0x01,0x28,0x35,0xD1,0x20,0x7E, ++0x2A,0x46,0x8D,0xF8,0x05,0x08,0x60,0x7E, ++0x8D,0xF8,0x04,0x08,0xD5,0xF8,0x38,0x81, ++0xBD,0xF8,0x04,0x18,0x40,0x46,0x00,0xF0, ++0xF6,0xFB,0xA9,0x78,0x07,0x46,0x60,0x7B, ++0x88,0x42,0x03,0xD1,0x30,0x68,0x41,0x6A, ++0x40,0x46,0x88,0x47,0x38,0x46,0x0D,0xF6, ++0x08,0x0D,0xBD,0xE8,0xF0,0x81,0x4F,0xF4, ++0x00,0x61,0x01,0xA8,0x06,0xF0,0xC4,0xED, ++0x20,0x7E,0x8D,0xF8,0x05,0x08,0x60,0x7E, ++0x8D,0xF8,0x04,0x08,0x60,0x7B,0xA9,0x78, ++0x88,0x42,0x03,0xD1,0x30,0x68,0x01,0x6A, ++0x01,0xA8,0x88,0x47,0xBD,0xF8,0x04,0x18, ++0x2A,0x46,0x01,0xA8,0x00,0xF0,0x64,0xFB, ++0xE1,0xE7,0x00,0x20,0xDF,0xE7,0x38,0xB5, ++0xEC,0x24,0x00,0x21,0x00,0x91,0xC1,0x7C, ++0x8D,0xF8,0x00,0x10,0x81,0x7C,0x8D,0xF8, ++0x01,0x10,0x40,0x7C,0x8D,0xF8,0x02,0x00, ++0xB9,0x48,0x00,0x68,0x81,0x69,0x00,0x98, ++0x88,0x47,0x01,0x28,0x00,0xD1,0x00,0x24, ++0x20,0x46,0x38,0xBD,0x2D,0xE9,0xFC,0x41, ++0x0E,0x46,0x00,0x21,0xEC,0x25,0x01,0x91, ++0x41,0x7D,0x8D,0xF8,0x00,0x10,0x01,0x7D, ++0x8D,0xF8,0x01,0x10,0xC1,0x7C,0x8D,0xF8, ++0x02,0x10,0x81,0x7C,0x8D,0xF8,0x03,0x10, ++0x01,0x7E,0x8D,0xF8,0x05,0x10,0x40,0x7E, ++0x8D,0xF8,0x04,0x00,0xA8,0x48,0xD6,0xF8, ++0x38,0x81,0xBD,0xF8,0x04,0x20,0x00,0x68, ++0x41,0x46,0x14,0x46,0x03,0x69,0x00,0x98, ++0x98,0x47,0xB6,0xF8,0x6A,0x10,0x20,0x46, ++0x07,0xF0,0x82,0xED,0x60,0x1A,0x0F,0x46, ++0x04,0x04,0x24,0x0C,0x01,0x94,0x0D,0xD0, ++0x32,0x46,0x21,0x46,0x40,0x46,0x00,0xF0, ++0xDF,0xFA,0x05,0x00,0x06,0xD1,0x2F,0xB1, ++0x08,0xEB,0x04,0x00,0x32,0x46,0x39,0x46, ++0x00,0xF0,0x0E,0xFB,0x28,0x46,0xBD,0xE8, ++0xFC,0x81,0x2D,0xE9,0xFC,0x47,0x04,0x46, ++0x00,0x20,0x0F,0x46,0x01,0x90,0x4F,0xF0, ++0xEC,0x09,0x60,0x7D,0x8D,0xF8,0x00,0x00, ++0x20,0x7D,0x8D,0xF8,0x01,0x00,0xE0,0x7C, ++0x8D,0xF8,0x02,0x00,0xA0,0x7C,0x8D,0xF8, ++0x03,0x00,0x20,0x7E,0x8D,0xF8,0x05,0x00, ++0x60,0x7E,0x8D,0xF8,0x04,0x00,0xB1,0xF8, ++0x92,0x10,0xBD,0xF8,0x04,0x00,0x06,0x46, ++0x07,0xF0,0x4A,0xED,0x70,0x1A,0x0D,0x46, ++0x06,0x04,0x36,0x0C,0x01,0x96,0xD7,0xF8, ++0x38,0x81,0x05,0xD0,0x3A,0x46,0x31,0x46, ++0x40,0x46,0x00,0xF0,0x1B,0xFB,0x81,0x46, ++0x2D,0xB1,0x08,0xEB,0x06,0x00,0x3A,0x46, ++0x29,0x46,0x00,0xF0,0x40,0xFB,0x70,0x19, ++0xE3,0x7D,0x41,0x46,0x82,0xB2,0x78,0x48, ++0x00,0x68,0x44,0x69,0x00,0x98,0xA0,0x47, ++0x48,0x46,0xBD,0xE8,0xFC,0x87,0x82,0xB0, ++0x00,0x22,0x01,0x92,0x02,0x7E,0x8D,0xF8, ++0x05,0x20,0x0A,0x46,0x40,0x7E,0x8D,0xF8, ++0x04,0x00,0xD1,0xF8,0x38,0x01,0xBD,0xF8, ++0x04,0x10,0x02,0xB0,0x00,0xF0,0x23,0xBB, ++0x6B,0x49,0x10,0xB5,0x40,0x7C,0x09,0x68, ++0xC9,0x69,0x88,0x47,0x00,0x20,0x10,0xBD, ++0x7C,0xB5,0x05,0x46,0xD1,0xF8,0x3C,0x41, ++0x0E,0x46,0x69,0x7E,0x00,0x20,0x8D,0xF8, ++0x00,0x10,0x29,0x7E,0x8D,0xF8,0x01,0x10, ++0xE9,0x7D,0x8D,0xF8,0x02,0x10,0xA9,0x7D, ++0x8D,0xF8,0x03,0x10,0x69,0x7C,0x07,0x29, ++0x40,0xD2,0xDF,0xE8,0x01,0xF0,0x20,0x04, ++0x1B,0x38,0x04,0x3F,0x20,0x00,0xA0,0x68, ++0xD8,0xB9,0x60,0x68,0xC8,0xB9,0x00,0x98, ++0x32,0x46,0x60,0x60,0x00,0x98,0x00,0xF2, ++0xFF,0x10,0x6F,0xF3,0x08,0x00,0x00,0x90, ++0x20,0x6A,0x00,0x99,0x00,0xF0,0xC2,0xFA, ++0x69,0x7C,0x04,0x29,0x26,0xD1,0x01,0x21, ++0x21,0x77,0x23,0xE0,0x00,0x99,0x32,0x46, ++0x04,0xF1,0x08,0x00,0x1C,0xE0,0x60,0x68, ++0x08,0xB1,0xFC,0x20,0x7C,0xBD,0xE1,0x68, ++0x32,0x46,0x20,0x6A,0x08,0x44,0x00,0x99, ++0x00,0xF0,0x6E,0xFA,0xE1,0x68,0x00,0x9A, ++0x11,0x44,0xE1,0x60,0xA1,0x68,0x00,0x9A, ++0x91,0x42,0x01,0xD9,0x89,0x1A,0x00,0xE0, ++0x00,0x21,0xA1,0x60,0x06,0xE0,0x60,0x8B, ++0x32,0x46,0x00,0x99,0x01,0x90,0x01,0xA8, ++0x00,0xF0,0x5A,0xFA,0xB1,0x6B,0x00,0x9A, ++0x89,0x1A,0xB1,0x63,0xB1,0x6B,0x00,0x29, ++0xDC,0xDA,0x4F,0xF0,0xFF,0x31,0xB1,0x63, ++0x7C,0xBD,0x70,0xB5,0x00,0x25,0x01,0x7C, ++0x14,0x46,0xE2,0x29,0x03,0xD1,0x21,0x46, ++0xFF,0xF7,0xA2,0xFE,0x20,0xE0,0xE3,0x29, ++0x02,0xD1,0xFF,0xF7,0xE0,0xFE,0x1B,0xE0, ++0xE4,0x29,0x03,0xD1,0x21,0x46,0xFF,0xF7, ++0xF1,0xFE,0x15,0xE0,0xE5,0x29,0x03,0xD1, ++0x21,0x46,0xFF,0xF7,0x2A,0xFF,0x0F,0xE0, ++0xE6,0x29,0x03,0xD1,0x21,0x46,0xFF,0xF7, ++0x66,0xFF,0x09,0xE0,0xE7,0x29,0x02,0xD1, ++0xFF,0xF7,0x72,0xFF,0x04,0xE0,0xE8,0x29, ++0x04,0xD1,0x21,0x46,0xFF,0xF7,0x74,0xFF, ++0x05,0x46,0x11,0xE0,0x81,0x68,0x41,0xB1, ++0x00,0x7B,0x00,0x06,0x20,0x46,0x02,0xD5, ++0x05,0xF0,0xF0,0xF9,0x01,0xE0,0x05,0xF0, ++0xF7,0xF9,0x05,0x20,0x04,0xF8,0x31,0x0F, ++0x24,0x20,0x60,0x70,0x00,0x20,0xA0,0x70, ++0x28,0x46,0x70,0xBD,0x03,0x46,0x10,0x46, ++0x01,0x22,0x10,0xB5,0x0A,0x73,0x02,0x21, ++0x80,0xF8,0x31,0x10,0x3A,0x21,0x80,0xF8, ++0x32,0x10,0x00,0x21,0x80,0xF8,0x33,0x10, ++0x99,0x68,0x39,0xB1,0x19,0x7B,0x09,0x06, ++0x02,0xD5,0x05,0xF0,0xCF,0xF9,0x01,0xE0, ++0x05,0xF0,0xD6,0xF9,0xEC,0x20,0x10,0xBD, ++0x2D,0xE9,0xF0,0x41,0x00,0x27,0x04,0x7C, ++0x05,0x46,0x16,0x46,0xFF,0xF7,0x09,0xFE, ++0x78,0xB9,0xA8,0x68,0xEC,0x27,0x00,0x28, ++0x60,0xD0,0x28,0x7B,0x00,0x06,0x30,0x46, ++0x04,0xD5,0x05,0xF0,0xB7,0xF9,0x59,0xE0, ++0x7C,0xD4,0x02,0x20,0x05,0xF0,0xBC,0xF9, ++0x54,0xE0,0x25,0x2C,0x0F,0xD1,0x68,0x7B, ++0xB1,0x78,0x88,0x42,0x4E,0xD1,0x28,0x48, ++0x00,0x68,0x80,0x68,0x80,0x47,0x01,0x46, ++0x33,0x46,0x4F,0xF4,0x00,0x72,0x28,0x46, ++0xFF,0xF7,0x26,0xFC,0x2E,0xE0,0x1B,0x2C, ++0x04,0xD1,0x31,0x46,0x28,0x46,0xFF,0xF7, ++0x4F,0xFC,0x27,0xE0,0x24,0xB9,0x31,0x46, ++0x28,0x46,0xFF,0xF7,0x59,0xFC,0x21,0xE0, ++0x2F,0x2C,0x04,0xD1,0x31,0x46,0x28,0x46, ++0xFF,0xF7,0x64,0xFC,0x1A,0xE0,0x1A,0x2C, ++0x04,0xD1,0x31,0x46,0x28,0x46,0xFF,0xF7, ++0x63,0xFC,0x13,0xE0,0x28,0x2C,0x04,0xD1, ++0x31,0x46,0x28,0x46,0xFF,0xF7,0x73,0xFC, ++0x0C,0xE0,0x2A,0x2C,0x04,0xD1,0x31,0x46, ++0x28,0x46,0xFF,0xF7,0xC9,0xFC,0x05,0xE0, ++0x1E,0x2C,0x05,0xD1,0x31,0x46,0x28,0x46, ++0xFF,0xF7,0xE6,0xFD,0x07,0x46,0x11,0xE0, ++0xA8,0x68,0x40,0xB1,0x28,0x7B,0x00,0x06, ++0x30,0x46,0x02,0xD5,0x05,0xF0,0x66,0xF9, ++0x01,0xE0,0x05,0xF0,0x6D,0xF9,0x05,0x20, ++0x06,0xF8,0x31,0x0F,0x24,0x20,0x70,0x70, ++0x00,0x20,0xB0,0x70,0x38,0x46,0x04,0xE6, ++0x7C,0xD4,0x02,0x20,0xFE,0x4A,0x11,0x7F, ++0x81,0x42,0x00,0xD0,0x10,0x77,0x70,0x47, ++0x01,0x46,0x00,0x20,0x02,0x29,0x02,0xD0, ++0x01,0x29,0x01,0xD1,0x01,0x20,0x70,0x47, ++0x00,0x29,0xFC,0xD1,0x02,0x20,0x70,0x47, ++0xF5,0x49,0xFF,0x20,0xF7,0x22,0x4A,0x75, ++0x88,0x81,0x08,0x82,0x70,0x47,0x01,0xEB, ++0x81,0x01,0x02,0xEB,0xC1,0x02,0x91,0x6C, ++0xD3,0x6C,0xC9,0x1A,0xB2,0xF8,0x44,0x30, ++0x99,0x42,0x03,0xD2,0x91,0x6C,0xD3,0x6C, ++0xC9,0x1A,0x01,0xE0,0xB2,0xF8,0x44,0x10, ++0x00,0x29,0x15,0xDD,0x44,0x32,0x93,0x68, ++0x18,0x44,0x93,0x68,0x0B,0x44,0x93,0x60, ++0x13,0x88,0x5B,0x1A,0x13,0x80,0xD2,0x7B, ++0xE3,0x4B,0x40,0x33,0x03,0xEB,0xC2,0x02, ++0xC3,0x07,0x0A,0xD0,0x13,0x78,0x00,0xF8, ++0x01,0x3B,0x49,0x1E,0x00,0x29,0xF9,0xDC, ++0x70,0x47,0x13,0x88,0x20,0xF8,0x02,0x3B, ++0x89,0x1E,0x02,0x29,0x05,0xDB,0xC3,0x07, ++0xF7,0xD0,0x13,0x78,0x00,0xF8,0x01,0x3B, ++0x49,0x1E,0x00,0x29,0xF9,0xDC,0x70,0x47, ++0xD5,0x49,0x49,0x78,0x01,0x76,0x70,0x47, ++0xD3,0x49,0x91,0xF8,0xC0,0x10,0x80,0xF8, ++0x2A,0x10,0x70,0x47,0x18,0xB9,0x00,0x20, ++0x81,0xF8,0x2A,0x00,0x04,0xE0,0x91,0xF8, ++0x2A,0x20,0x82,0x43,0x81,0xF8,0x2A,0x20, ++0x11,0xF8,0x2A,0x2F,0xCA,0x48,0xC0,0x30, ++0x02,0x70,0x00,0x78,0x08,0x70,0x70,0x47, ++0xC8,0x48,0x00,0x21,0x01,0x81,0x01,0x88, ++0x21,0xF0,0x0F,0x01,0x01,0x80,0x70,0x47, ++0x10,0xB9,0x60,0x20,0x08,0x76,0x02,0xE0, ++0x0A,0x7E,0x82,0x43,0x0A,0x76,0x0A,0x7E, ++0xBF,0x48,0x42,0x70,0x40,0x78,0x08,0x76, ++0x70,0x47,0x11,0xF8,0x2A,0x2F,0x02,0x43, ++0x0A,0x70,0x0A,0x78,0xBB,0x48,0x4C,0x38, ++0x02,0x70,0x00,0x78,0x08,0x70,0x70,0x47, ++0xB8,0x48,0x4C,0x38,0x00,0x78,0xC0,0xF3, ++0xC1,0x00,0x00,0x28,0x07,0xD0,0x01,0x28, ++0x05,0xD0,0x02,0x28,0x03,0xD0,0x03,0x28, ++0x01,0xD0,0x4F,0xF0,0xFF,0x30,0x70,0x47, ++0x00,0xEB,0x80,0x00,0x30,0xB5,0x01,0xEB, ++0xC0,0x03,0x52,0x33,0x0C,0x46,0x58,0x78, ++0xFF,0xF7,0x58,0xFF,0x18,0x78,0x59,0x78, ++0x00,0xF0,0x03,0x00,0xA8,0x4A,0x60,0xF3, ++0x1F,0x11,0x90,0x8D,0x9D,0x78,0x52,0x3B, ++0x01,0x2D,0x14,0xD1,0x82,0xF8,0x38,0x10, ++0xB3,0xF8,0x42,0x10,0x11,0x85,0xC1,0x07, ++0x03,0xD0,0x11,0x8E,0xA3,0xF8,0x44,0x10, ++0x00,0xE0,0x80,0x20,0x93,0xF8,0x52,0x10, ++0x03,0x29,0x01,0xD1,0x40,0xF4,0x80,0x50, ++0x90,0x85,0x00,0x20,0x12,0xE0,0x94,0xF8, ++0x30,0x00,0x05,0x28,0x01,0xD1,0x82,0xF8, ++0x34,0x10,0x33,0xF8,0x42,0x0F,0x10,0x84, ++0x08,0x20,0x90,0x84,0x18,0x7C,0x01,0x28, ++0x02,0xD1,0x46,0xF2,0x40,0x00,0x01,0xE0, ++0x4F,0xF4,0x01,0x50,0x90,0x84,0x30,0xBD, ++0x70,0xB4,0x0D,0x46,0x00,0xEB,0x80,0x04, ++0xDD,0xE9,0x03,0x61,0x01,0xEB,0xC4,0x04, ++0x40,0x34,0x66,0x80,0x25,0x75,0x00,0x25, ++0xA5,0x80,0xA5,0x60,0xE5,0x60,0xA2,0x74, ++0xC2,0xB2,0xE2,0x74,0x65,0x75,0xE5,0x61, ++0x25,0x62,0x02,0x26,0xA6,0x75,0xE5,0x75, ++0x23,0x76,0x00,0x28,0x02,0xD0,0x10,0x46, ++0x70,0xBC,0xA1,0xE7,0x70,0xBC,0x70,0x47, ++0x7F,0x49,0x4A,0x78,0x02,0x76,0x91,0xF8, ++0xC0,0x10,0x80,0xF8,0x2A,0x10,0x70,0x47, ++0x01,0xEB,0x81,0x01,0x30,0xB5,0x02,0xEB, ++0xC1,0x02,0xB2,0xF8,0x42,0x10,0x49,0xB1, ++0x91,0x6C,0xD3,0x6C,0xC9,0x1A,0xB2,0xF8, ++0x42,0x30,0x99,0x42,0x02,0xD9,0xB2,0xF8, ++0x42,0x10,0x02,0xE0,0x91,0x6C,0xD3,0x6C, ++0xC9,0x1A,0x01,0x23,0x11,0xB9,0x82,0xF8, ++0x55,0x30,0x30,0xBD,0xD4,0x6C,0x20,0x44, ++0xD4,0x6C,0x0C,0x44,0xD4,0x64,0xD4,0x6C, ++0x95,0x6C,0xAC,0x42,0x01,0xD1,0x82,0xF8, ++0x55,0x30,0x92,0xF8,0x53,0x20,0x68,0x4B, ++0x40,0x33,0x00,0x29,0x03,0xEB,0xC2,0x02, ++0x0B,0xDD,0xC3,0x07,0x09,0xD0,0x10,0xF8, ++0x01,0x3B,0x13,0x70,0x49,0x1E,0xFA,0xD1, ++0x30,0xBD,0x30,0xF8,0x02,0x3B,0x13,0x80, ++0x89,0x1E,0x02,0x29,0x05,0xDB,0xC3,0x07, ++0xF7,0xD0,0x10,0xF8,0x01,0x3B,0x13,0x70, ++0x49,0x1E,0x00,0x29,0xF9,0xDC,0x30,0xBD, ++0x70,0xB5,0x14,0x46,0x00,0x23,0xFF,0x22, ++0x60,0x34,0x04,0xF8,0x45,0x2C,0xA3,0x77, ++0x21,0x61,0x63,0x61,0x63,0x77,0x60,0x62, ++0xE0,0x7E,0x00,0xF0,0x0F,0x00,0x40,0xF0, ++0x20,0x00,0x04,0xF8,0x44,0x0C,0xE0,0x7E, ++0x60,0x3C,0xFF,0xF7,0x9F,0xFE,0x4E,0x4D, ++0x95,0xF8,0x24,0x00,0x81,0x06,0x00,0xD5, ++0x40,0x23,0x80,0x07,0x01,0xD5,0x58,0x06, ++0x05,0xD5,0x00,0x22,0x0E,0x21,0x01,0x20, ++0x23,0x46,0x05,0xF0,0x41,0xF8,0xE0,0x7E, ++0xFF,0x28,0x03,0xD1,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF8,0xD0,0x95,0xF8,0x24,0x00, ++0x80,0x07,0x03,0xD5,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF7,0xD0,0x00,0x20,0x70,0xBD, ++0xF0,0xB5,0x14,0x46,0x00,0x25,0xFF,0x22, ++0x60,0x34,0x04,0xF8,0x47,0x2C,0x2E,0x46, ++0xA5,0x77,0x21,0x61,0x65,0x61,0x65,0x77, ++0x60,0x62,0xE0,0x7E,0x00,0xF0,0x0F,0x00, ++0x40,0xF0,0x20,0x00,0x04,0xF8,0x44,0x0C, ++0xE0,0x7E,0x60,0x3C,0xFF,0xF7,0x66,0xFE, ++0x31,0x4F,0x97,0xF8,0x24,0x00,0x81,0x06, ++0x00,0xD5,0x40,0x25,0x80,0x07,0x01,0xD5, ++0x68,0x06,0x07,0xD5,0xD4,0xF8,0x84,0x00, ++0x01,0x21,0x22,0x46,0xFF,0xF7,0x5C,0xFF, ++0x45,0xF0,0x01,0x05,0x0D,0xB1,0x87,0xF8, ++0x24,0x50,0x60,0x7E,0xFF,0x28,0x03,0xD1, ++0x94,0xF8,0x2E,0x00,0x01,0x28,0xF8,0xD0, ++0x94,0xF8,0x7D,0x00,0x18,0xB9,0x94,0xF8, ++0x2E,0x00,0x01,0x28,0xF8,0xD0,0x26,0x67, ++0x00,0x20,0xF0,0xBD,0x10,0xB5,0x14,0x46, ++0xFF,0x22,0x84,0x34,0x04,0xF8,0x6A,0x2C, ++0x61,0x61,0x00,0x22,0xA2,0x61,0xA0,0x62, ++0xE2,0x62,0x21,0x82,0xE0,0x7F,0x00,0xF0, ++0x0F,0x00,0x40,0xF0,0xA0,0x00,0x04,0xF8, ++0x68,0x0C,0x84,0x3C,0x0C,0x21,0x02,0x20, ++0x23,0x46,0x04,0xF0,0xD9,0xFF,0xA0,0x7E, ++0xFF,0x28,0x03,0xD1,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF8,0xD0,0x00,0x20,0x10,0xBD, ++0x0E,0x48,0x08,0x30,0x01,0x88,0x21,0xF4, ++0x00,0x41,0x01,0x80,0x01,0x88,0x41,0xF4, ++0x80,0x41,0x01,0x80,0x70,0x47,0xF0,0xB5, ++0x02,0xF1,0x98,0x04,0x0D,0x46,0x21,0x60, ++0x00,0x26,0x66,0x60,0x60,0x61,0xA6,0x61, ++0xE0,0x7A,0x14,0x46,0xFF,0xF7,0x06,0xFE, ++0xDF,0xF8,0x04,0xC0,0x01,0x27,0x35,0xE0, ++0x00,0x40,0x00,0x25,0x0C,0x41,0x00,0x25, ++0xFF,0xF7,0xDE,0xFF,0xA0,0x7F,0x01,0x28, ++0x2C,0xD1,0xA6,0x77,0xB4,0xF8,0x94,0x00, ++0x2D,0x1A,0x94,0xF8,0xA3,0x00,0x00,0xF0, ++0x0F,0x00,0x40,0xF0,0xA0,0x00,0x20,0x77, ++0xB4,0xF8,0x94,0x00,0xB4,0xF8,0x92,0x10, ++0x88,0x42,0x07,0xD3,0x94,0x34,0xA0,0x68, ++0x21,0x88,0x08,0x44,0x61,0x68,0x94,0x3C, ++0x88,0x42,0x02,0xD3,0x84,0xF8,0xA5,0x70, ++0x01,0xE0,0x84,0xF8,0xA5,0x60,0xD4,0xF8, ++0xAC,0x00,0x02,0x21,0x22,0x46,0xFF,0xF7, ++0xEE,0xFD,0xBC,0xF8,0x30,0x00,0xA4,0xF8, ++0x94,0x00,0xB4,0xF8,0x94,0x00,0x08,0xB9, ++0x8C,0xF8,0x2C,0x60,0x00,0x2D,0xCB,0xD1, ++0xD4,0xF8,0x98,0x00,0xD4,0xF8,0x9C,0x10, ++0x88,0x42,0x03,0xD0,0x94,0xF8,0x2E,0x00, ++0x01,0x28,0xF5,0xD0,0x94,0xF8,0xA5,0x00, ++0x18,0xB9,0x94,0xF8,0x2E,0x00,0x01,0x28, ++0xF8,0xD0,0xC4,0xF8,0x98,0x60,0x00,0x20, ++0xF0,0xBD,0x03,0x46,0x10,0xB5,0x0C,0x46, ++0x08,0x46,0xFF,0xF7,0xAD,0xFE,0x58,0x79, ++0x28,0xB9,0x18,0x88,0x21,0x46,0xBD,0xE8, ++0x10,0x40,0x05,0xF0,0xD5,0xBC,0x94,0xF8, ++0x2A,0x00,0x40,0x07,0x05,0xD4,0x21,0x46, ++0xBD,0xE8,0x10,0x40,0x18,0x46,0x05,0xF0, ++0xE7,0xBA,0x10,0xBD,0x2D,0xE9,0xF1,0x4F, ++0x00,0x27,0x44,0x4C,0x84,0xB0,0x94,0xF8, ++0x1C,0x90,0x94,0xF8,0x00,0x04,0x84,0xF8, ++0x00,0x04,0x18,0xB1,0x04,0x99,0x01,0x20, ++0x05,0xF0,0x0B,0xF8,0x20,0x7D,0x20,0x75, ++0x38,0xB1,0x04,0x99,0xAD,0xF8,0x04,0x00, ++0x01,0xA8,0x8D,0xF8,0x09,0x70,0xFF,0xF7, ++0xCC,0xFF,0xA1,0x88,0xA0,0x46,0x20,0x46, ++0x3C,0x46,0x61,0xF3,0x0F,0x04,0x01,0x89, ++0x61,0xF3,0x1F,0x44,0xA5,0xB2,0x85,0x80, ++0x21,0x0C,0x01,0x81,0xE8,0x07,0x4F,0xF0, ++0x01,0x06,0x19,0xD0,0x41,0x46,0x88,0xF8, ++0x1C,0x70,0x98,0xF8,0x24,0x00,0x8D,0xF8, ++0x08,0x70,0x8D,0xF8,0x0D,0x70,0xAD,0xF8, ++0x04,0x00,0xC0,0x07,0x8D,0xF8,0x09,0x60, ++0x02,0xD0,0x08,0x8E,0xAD,0xF8,0x06,0x00, ++0x01,0xA8,0x04,0x99,0xFF,0xF7,0xA5,0xFF, ++0x25,0xF0,0x01,0x00,0x60,0xF3,0x0F,0x04, ++0x01,0x25,0xB2,0x46,0x8D,0xF8,0x09,0x60, ++0x02,0x26,0xBB,0x46,0x16,0xE0,0x37,0x42, ++0x10,0xD0,0x88,0xF8,0x1C,0x50,0x98,0xF8, ++0x24,0x00,0x04,0x99,0xAD,0xF8,0x04,0x00, ++0x01,0xA8,0x8D,0xF8,0x08,0xB0,0x8D,0xF8, ++0x0D,0x50,0xFF,0xF7,0x8A,0xFF,0xB7,0x43, ++0x67,0xF3,0x0F,0x04,0x6D,0x1C,0x70,0x04, ++0x06,0x0C,0xED,0xB2,0x27,0x04,0x3F,0x0C, ++0xE5,0xD1,0x01,0x25,0x02,0x26,0x1A,0xE0, ++0x37,0x42,0x14,0xD0,0x88,0xF8,0x1C,0x50, ++0x98,0xF8,0x2C,0x10,0x8D,0xF8,0x08,0xA0, ++0xAD,0xF8,0x04,0x10,0x8D,0xF8,0x0D,0x50, ++0xB8,0xF8,0x30,0x00,0x04,0x99,0xAD,0xF8, ++0x06,0x00,0x01,0xA8,0xFF,0xF7,0x69,0xFF, ++0xB7,0x43,0x67,0xF3,0x1F,0x44,0x6D,0x1C, ++0x70,0x04,0x06,0x0C,0xED,0xB2,0x27,0x0C, ++0xE2,0xD1,0x88,0xF8,0x1C,0x90,0x05,0xB0, ++0xBD,0xE8,0xF0,0x8F,0x00,0x40,0x00,0x25, ++0x70,0xB5,0x0D,0x46,0x04,0x46,0x4F,0xF4, ++0xA4,0x71,0x06,0xF0,0xD6,0xE8,0x01,0x20, ++0x60,0x71,0x7F,0x20,0xA0,0x71,0x0A,0x48, ++0xC4,0xF8,0x40,0x01,0x9A,0x20,0xC4,0xF8, ++0x44,0x01,0xC4,0xF8,0x3C,0x51,0x70,0xBD, ++0x00,0xF5,0x84,0x71,0xC1,0x60,0x20,0x39, ++0x01,0x61,0x30,0x31,0x41,0x61,0x70,0x47, ++0x2C,0x21,0x06,0xF0,0xBB,0xB8,0x00,0x00, ++0xD4,0x04,0x03,0x20,0x10,0xB5,0x04,0x46, ++0xFB,0xF7,0x68,0xF8,0x60,0x1C,0x10,0xBD, ++0x6A,0x48,0x70,0x47,0x69,0x49,0x10,0xB5, ++0x4A,0x8C,0x22,0xF0,0x0B,0x02,0x4A,0x84, ++0x01,0x28,0x67,0x4B,0x67,0x4C,0x68,0x4A, ++0x11,0xD1,0xB2,0xF8,0xBC,0x00,0x40,0xF4, ++0x00,0x60,0xA2,0xF8,0xBC,0x00,0x33,0xF8, ++0x80,0x0F,0x40,0xF0,0x02,0x00,0x18,0x80, ++0xB4,0xF8,0xCC,0x0D,0x40,0xF4,0x00,0x50, ++0xA4,0xF8,0xCC,0x0D,0x16,0xE0,0x02,0x28, ++0x14,0xD1,0xB2,0xF8,0xBC,0x00,0x20,0xF4, ++0x00,0x60,0xA2,0xF8,0xBC,0x00,0x33,0xF8, ++0x80,0x0F,0x20,0xF0,0x02,0x00,0x18,0x80, ++0xB4,0xF8,0xCC,0x0D,0x20,0xF4,0x00,0x50, ++0xA4,0xF8,0xCC,0x0D,0x48,0x8C,0x40,0xF0, ++0x0A,0x00,0x48,0x84,0x48,0x8C,0xA2,0xF8, ++0x60,0x01,0x00,0x20,0x10,0xBD,0x51,0x48, ++0xB0,0xF8,0xB4,0x11,0x21,0xF0,0x02,0x01, ++0xA0,0xF8,0xB4,0x11,0x01,0x88,0x21,0xF0, ++0x02,0x01,0x20,0xF8,0x40,0x1B,0x01,0x88, ++0x21,0xF0,0x02,0x01,0x01,0x80,0x00,0x20, ++0x70,0x47,0x48,0x48,0xB0,0xF8,0xB4,0x11, ++0x41,0xF0,0x02,0x01,0xA0,0xF8,0xB4,0x11, ++0x01,0x88,0x41,0xF0,0x02,0x01,0x20,0xF8, ++0x40,0x1B,0x01,0x88,0x41,0xF0,0x02,0x01, ++0x01,0x80,0x00,0x20,0x70,0x47,0x00,0xB5, ++0x02,0x46,0xFF,0xF7,0xEA,0xFF,0x3E,0x48, ++0x01,0x88,0x21,0xF0,0x10,0x01,0x01,0x80, ++0x01,0x88,0x41,0xF0,0x40,0x01,0x01,0x80, ++0x01,0x88,0x21,0xF4,0x80,0x51,0x01,0x80, ++0x01,0x88,0x41,0xF4,0x80,0x41,0x01,0x80, ++0xB0,0xF8,0x20,0x1C,0x21,0xF0,0x08,0x01, ++0xA0,0xF8,0x20,0x1C,0x01,0x88,0x21,0xF4, ++0x70,0x61,0x01,0x80,0x01,0x88,0x11,0x43, ++0x01,0x80,0xFF,0xF7,0xB8,0xFF,0x00,0x20, ++0x00,0xBD,0x00,0x20,0x70,0x47,0x70,0x47, ++0x70,0x47,0x10,0xB5,0x04,0x46,0xFB,0xF7, ++0x2A,0xED,0x20,0x46,0x10,0xBD,0x70,0x47, ++0x70,0x47,0x22,0x48,0xC0,0x30,0x70,0x47, ++0x70,0xB5,0x20,0x4C,0x20,0x34,0x01,0x20, ++0x20,0x74,0x24,0x48,0x01,0x88,0x41,0xF0, ++0x40,0x01,0x01,0x80,0x22,0x48,0x01,0x88, ++0x21,0xF4,0x00,0x41,0x01,0x80,0x21,0x48, ++0x01,0x88,0x41,0xF4,0x40,0x51,0x01,0x80, ++0x01,0x88,0x21,0xF4,0x00,0x41,0x01,0x80, ++0x00,0x25,0x65,0x80,0x01,0x20,0xFF,0xF7, ++0x51,0xFF,0xE5,0x60,0x28,0x46,0xFF,0xF7, ++0xAA,0xFF,0x19,0x48,0x00,0x68,0xA0,0x66, ++0x04,0xF5,0x28,0x70,0x60,0x66,0x00,0x20, ++0x25,0x72,0x65,0x72,0x00,0xF0,0x2C,0xF8, ++0x00,0x20,0x70,0xBD,0x10,0xB5,0xFB,0xF7, ++0xAC,0xFD,0x02,0x28,0x01,0xD1,0x00,0x20, ++0x10,0xBD,0x10,0x48,0x10,0xBD,0x10,0xB5, ++0xFB,0xF7,0xA3,0xFD,0x03,0x28,0x01,0xD1, ++0x00,0x20,0x10,0xBD,0x0B,0x48,0x80,0x1C, ++0x10,0xBD,0x00,0x00,0x20,0x06,0x03,0x20, ++0x00,0x70,0x00,0x25,0x00,0x00,0x02,0x25, ++0x00,0x50,0x00,0x25,0x18,0x7C,0x00,0x25, ++0x40,0x72,0x00,0x25,0x0C,0x7F,0x00,0x25, ++0x14,0x2C,0x02,0x25,0xCC,0x0D,0x02,0x25, ++0xAC,0x04,0x03,0x20,0x4D,0x00,0x00,0x80, ++0xFF,0x4A,0xFE,0x49,0x11,0x60,0x70,0x47, ++0x30,0xB4,0xFD,0x4C,0x24,0x68,0x24,0x68, ++0xA4,0x46,0x30,0xBC,0x60,0x47,0x30,0xB4, ++0xF9,0x4C,0x24,0x68,0x64,0x68,0xA4,0x46, ++0x30,0xBC,0x60,0x47,0x38,0xB5,0x1D,0x46, ++0x04,0x9B,0x00,0x93,0xF4,0x4B,0x1B,0x68, ++0x9C,0x68,0x2B,0x46,0xA0,0x47,0x38,0xBD, ++0x38,0xB5,0x1D,0x46,0x04,0x9B,0x00,0x93, ++0xEF,0x4B,0x1B,0x68,0xDC,0x68,0x2B,0x46, ++0xA0,0x47,0x38,0xBD,0x30,0xB4,0xEC,0x4C, ++0x24,0x68,0x24,0x69,0xA4,0x46,0x30,0xBC, ++0x60,0x47,0x30,0xB4,0xE8,0x4C,0x24,0x68, ++0x64,0x69,0xA4,0x46,0x30,0xBC,0x60,0x47, ++0x10,0xB5,0xFF,0xF7,0x2A,0xFF,0xE5,0x4C, ++0x4F,0xF6,0xFB,0x70,0xA4,0xF8,0x40,0x00, ++0x20,0x88,0x20,0xF4,0x80,0x50,0x20,0x80, ++0x01,0x20,0xFF,0xF7,0xCB,0xFE,0x20,0x88, ++0x40,0xF4,0x80,0x50,0x20,0x80,0x01,0x20, ++0xFF,0xF7,0xC4,0xFE,0xB4,0xF8,0x40,0x00, ++0xC0,0x3C,0x04,0x28,0x01,0xD0,0xDA,0x48, ++0x10,0xBD,0x20,0x89,0x40,0xF0,0x10,0x00, ++0x20,0x81,0x01,0x20,0xFF,0xF7,0xB6,0xFE, ++0x20,0x89,0x20,0xF0,0x10,0x00,0x20,0x81, ++0xFF,0xF7,0xF1,0xFE,0x00,0x20,0x10,0xBD, ++0x70,0xB5,0x00,0x24,0xCF,0x4E,0x4F,0xF4, ++0x80,0x35,0xC0,0x3E,0x30,0x89,0x80,0x06, ++0x05,0xD4,0x01,0x20,0xFF,0xF7,0xA2,0xFE, ++0x64,0x1C,0xAC,0x42,0xF6,0xD3,0xAC,0x42, ++0x04,0xD1,0xFF,0xF7,0xC1,0xFF,0xC8,0x48, ++0x09,0x30,0x70,0xBD,0x00,0x20,0x70,0xBD, ++0x70,0xB5,0x00,0x24,0xC3,0x4E,0xC5,0x4D, ++0xC0,0x3E,0x30,0x88,0x40,0x04,0x05,0xD4, ++0x64,0x1C,0x01,0x20,0xFF,0xF7,0x8A,0xFE, ++0xAC,0x42,0xF6,0xD3,0xAC,0x42,0x04,0xD1, ++0xFF,0xF7,0xAA,0xFF,0xBC,0x48,0x09,0x30, ++0x70,0xBD,0x00,0x20,0x70,0xBD,0xBC,0x48, ++0xFF,0x22,0x10,0xB5,0x00,0x24,0xC8,0x21, ++0x05,0xF0,0x9E,0xEE,0xB5,0x49,0x00,0x20, ++0xB7,0x4B,0xC0,0x39,0x31,0xF8,0xC0,0x2F, ++0x22,0xF4,0xE0,0x62,0x0A,0x80,0x0A,0x88, ++0x42,0xEA,0x00,0x22,0x0A,0x80,0x0A,0x88, ++0x23,0xF8,0x14,0x20,0x64,0x1C,0xA2,0xB2, ++0x8C,0x88,0x23,0xF8,0x12,0x40,0x52,0x1C, ++0x0C,0x89,0x92,0xB2,0x40,0x1C,0xC0,0x39, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x80,0xB2, ++0x94,0xB2,0x08,0x28,0xE2,0xD3,0x00,0x20, ++0xC6,0x31,0xCA,0x8F,0x22,0xF4,0xE0,0x42, ++0xCA,0x87,0xCA,0x8F,0x42,0xEA,0x00,0x32, ++0xCA,0x87,0x31,0xF8,0x06,0x2C,0x23,0xF8, ++0x14,0x20,0x64,0x1C,0xA2,0xB2,0xCC,0x8F, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x31,0xF8, ++0x02,0x4C,0x92,0xB2,0x23,0xF8,0x12,0x40, ++0x52,0x1C,0x4C,0x88,0x92,0xB2,0x40,0x1C, ++0xC6,0x39,0x23,0xF8,0x12,0x40,0x52,0x1C, ++0x80,0xB2,0x94,0xB2,0x08,0x28,0xDB,0xD3, ++0x10,0xBD,0x95,0x48,0xFF,0x22,0x10,0xB5, ++0x00,0x24,0xC8,0x21,0xC8,0x30,0x05,0xF0, ++0x50,0xEE,0x91,0x49,0x8D,0x48,0xC8,0x31, ++0xC0,0x38,0x30,0xF8,0x24,0x20,0x21,0xF8, ++0x14,0x20,0x64,0x1C,0xA4,0xB2,0x58,0x2C, ++0xF7,0xD3,0xDA,0x30,0x30,0xF8,0xDA,0x1C, ++0x30,0xF8,0xD6,0x1C,0x30,0xF8,0xD2,0x1C, ++0x30,0xF8,0xCE,0x1C,0x30,0xF8,0xBE,0x1C, ++0x30,0xF8,0xB2,0x1C,0x30,0xF8,0xAE,0x1C, ++0x30,0xF8,0xAA,0x1C,0x30,0xF8,0x6E,0x1C, ++0x30,0xF8,0x6A,0x1C,0x30,0xF8,0x66,0x1C, ++0x30,0xF8,0x5E,0x1C,0x30,0xF8,0x5A,0x1C, ++0x30,0xF8,0x26,0x1C,0x30,0xF8,0x22,0x1C, ++0x30,0xF8,0x1E,0x1C,0x30,0xF8,0x1A,0x1C, ++0x30,0xF8,0x16,0x1C,0x30,0xF8,0x12,0x1C, ++0x30,0xF8,0x06,0x1C,0x41,0x88,0xC1,0x88, ++0x41,0x89,0xC1,0x89,0x41,0x8A,0xC1,0x8A, ++0x41,0x8B,0x41,0x8C,0xC1,0x8C,0x41,0x8D, ++0xC1,0x8D,0x41,0x8E,0xC1,0x8E,0x41,0x8F, ++0x41,0x8D,0xC1,0x8F,0xB0,0xF8,0x42,0x10, ++0xB0,0xF8,0x46,0x10,0xB0,0xF8,0x4A,0x10, ++0xB0,0xF8,0x4E,0x10,0xB0,0xF8,0x5A,0x10, ++0xB0,0xF8,0x5E,0x10,0xB0,0xF8,0x62,0x10, ++0xB0,0xF8,0x66,0x10,0xB0,0xF8,0x6A,0x10, ++0xB0,0xF8,0x6E,0x10,0xB0,0xF8,0x72,0x10, ++0xB0,0xF8,0x7A,0x10,0xB0,0xF8,0x7E,0x00, ++0x10,0xBD,0x70,0xB5,0xFF,0xF7,0xCC,0xFD, ++0x04,0x46,0xC0,0x8F,0x08,0x28,0x02,0xD2, ++0x4F,0xF4,0x00,0x70,0x01,0xE0,0x4F,0xF4, ++0x80,0x60,0xA4,0xF8,0x6A,0x00,0x56,0x34, ++0x34,0xF8,0x1E,0x0C,0x02,0xF0,0x87,0xF8, ++0xA0,0x76,0x34,0xF8,0x1C,0x0C,0x02,0xF0, ++0x82,0xF8,0x20,0x77,0xA0,0x8A,0x02,0xF0, ++0x7E,0xF8,0xA0,0x77,0x01,0x25,0xA0,0x7E, ++0x05,0xFA,0x00,0xF0,0x40,0x1E,0x20,0x84, ++0x20,0x7F,0x05,0xFA,0x00,0xF0,0x40,0x1E, ++0xA0,0x84,0xA0,0x7F,0x05,0xFA,0x00,0xF1, ++0x49,0x1E,0x21,0x85,0x34,0xF8,0x1C,0x1C, ++0xC1,0x40,0x61,0x82,0x88,0xB2,0x02,0xF0, ++0x66,0xF8,0x60,0x77,0xC0,0xB2,0x05,0xFA, ++0x00,0xF1,0x49,0x1E,0xE1,0x84,0x34,0xF8, ++0x1A,0x1C,0xC1,0x40,0x89,0xB2,0x21,0xF0, ++0x01,0x01,0xE1,0x82,0x89,0xB2,0x81,0x40, ++0x24,0xF8,0x1A,0x1C,0xA1,0x7E,0x08,0x44, ++0xE0,0x76,0x85,0x40,0x25,0x82,0x6D,0x1E, ++0x00,0x20,0x65,0x84,0x70,0xBD,0x10,0xB5, ++0xFF,0xF7,0x7E,0xFD,0x82,0x8A,0x35,0x49, ++0x5E,0x31,0x21,0xF8,0xB2,0x2C,0xC2,0x8A, ++0x21,0xF8,0x1E,0x2C,0x02,0x8B,0x4A,0x80, ++0x42,0x8B,0xCA,0x80,0x82,0x8B,0x4A,0x84, ++0x31,0xF8,0x6E,0x2C,0x03,0x8C,0x03,0xF4, ++0x7C,0x53,0x1A,0x43,0x21,0xF8,0x6E,0x2C, ++0xC0,0x8B,0xC8,0x87,0x10,0xBD,0x2D,0xE9, ++0xF0,0x41,0x00,0x24,0x27,0x4F,0x05,0x46, ++0x0E,0x46,0xC0,0x3F,0x09,0xE0,0x38,0x88, ++0x35,0xEA,0x00,0x00,0x07,0xD0,0x01,0x20, ++0xFF,0xF7,0x50,0xFD,0xFF,0xF7,0xDC,0xFD, ++0x64,0x1C,0xB4,0x42,0xF3,0xD3,0xB4,0x42, ++0x02,0xD2,0x38,0x88,0x28,0x40,0x38,0x80, ++0x20,0x46,0xBD,0xE8,0xF0,0x81,0x10,0xB5, ++0xFF,0xF7,0x46,0xFD,0x04,0x46,0xFF,0xF7, ++0x63,0xFE,0x18,0x49,0xC0,0x39,0x88,0x88, ++0x4F,0xF6,0xFE,0x52,0x10,0x40,0x88,0x80, ++0x08,0x88,0x40,0xF2,0x01,0x22,0x10,0x40, ++0x08,0x80,0x20,0x20,0x08,0x85,0xA0,0x8A, ++0xA1,0xF8,0x6C,0x00,0xE0,0x8A,0xA1,0xF8, ++0x00,0x01,0xB1,0xF8,0x00,0x01,0xE0,0x8A, ++0x20,0x8B,0xA1,0xF8,0x20,0x01,0x60,0x8B, ++0xA1,0xF8,0x24,0x01,0xA0,0x8B,0xA1,0xF8, ++0x40,0x01,0xB1,0xF8,0xB0,0x20,0x20,0x8C, ++0x00,0xF4,0x7C,0x50,0x02,0x43,0xA1,0xF8, ++0xB0,0x20,0xE0,0x8B,0xA1,0xF8,0x5C,0x01, ++0x10,0xBD,0x00,0x00,0x30,0xEC,0x03,0x20, ++0x70,0x05,0x03,0x20,0xC0,0x50,0x00,0x25, ++0x2C,0x00,0x00,0x80,0x40,0x42,0x0F,0x00, ++0x60,0x0B,0x03,0x20,0x2D,0xE9,0xF0,0x41, ++0xFF,0xF7,0x06,0xFD,0x00,0x24,0x06,0x46, ++0x41,0xF2,0x88,0x37,0xFF,0x4D,0xA8,0x8B, ++0xC0,0x05,0x05,0xD4,0x01,0x20,0xFF,0xF7, ++0xF5,0xFC,0x64,0x1C,0xBC,0x42,0xF6,0xD3, ++0xF0,0x6A,0xFF,0xF7,0x54,0xFD,0xFF,0xF7, ++0xAA,0xFF,0x70,0x8C,0xA5,0xF8,0x60,0x01, ++0x28,0x88,0x00,0xF4,0x00,0x70,0x28,0x80, ++0x20,0x20,0xA5,0xF8,0x0C,0x01,0x48,0xF2, ++0x04,0x00,0xA5,0xF8,0x10,0x01,0x88,0x20, ++0xA5,0xF8,0x10,0x01,0x01,0x20,0xA5,0xF8, ++0x14,0x01,0xEF,0x4C,0x40,0x02,0x21,0x46, ++0xFF,0xF7,0x75,0xFF,0xA0,0x42,0xB5,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA5,0xF8, ++0x60,0x01,0x01,0xD1,0xE9,0x48,0x84,0xE7, ++0x00,0x20,0x82,0xE7,0x2D,0xE9,0xF0,0x41, ++0x04,0x46,0x0D,0x46,0x16,0x46,0x1F,0x46, ++0xFF,0xF7,0xC6,0xFC,0x00,0x22,0xD4,0xB3, ++0x01,0x8C,0x21,0xF4,0x40,0x51,0x01,0x84, ++0x01,0x8C,0x41,0xEA,0x05,0x31,0x01,0x84, ++0xDC,0x49,0xB0,0x31,0x0B,0x88,0x23,0xF4, ++0x40,0x53,0x0B,0x80,0x0B,0x88,0x04,0x8C, ++0x04,0xF4,0x40,0x54,0x23,0x43,0x0B,0x80, ++0x03,0x8C,0x23,0xF4,0x70,0x63,0x03,0x84, ++0x03,0x8C,0x43,0xEA,0x06,0x23,0x03,0x84, ++0x0B,0x88,0x23,0xF4,0x70,0x63,0x0B,0x80, ++0x0B,0x88,0x04,0x8C,0x04,0xF4,0x70,0x64, ++0x23,0x43,0x0B,0x80,0xC3,0x8B,0x4F,0xF2, ++0xF8,0x04,0x23,0x40,0xC3,0x83,0xC3,0x8B, ++0x43,0xEA,0x07,0x23,0xC3,0x83,0xC3,0x8B, ++0x23,0xF4,0x70,0x43,0xC3,0x83,0xC3,0x8B, ++0x43,0xF4,0x60,0x43,0xC3,0x83,0xC0,0x8B, ++0xA1,0xF8,0xAC,0x00,0x06,0xE0,0xFF,0xE7, ++0x01,0x20,0xFF,0xF7,0x87,0xFC,0xFF,0xF7, ++0x79,0xFF,0x02,0x46,0x10,0x46,0x34,0xE7, ++0xF0,0xB5,0xCB,0x07,0xBD,0x4F,0x0A,0xD0, ++0x4B,0x08,0x07,0xEB,0x83,0x03,0xB3,0xF8, ++0x00,0x34,0x49,0x1C,0x1B,0x0A,0x52,0x1E, ++0x01,0x26,0x03,0x70,0x00,0xE0,0x00,0x26, ++0x00,0x23,0x0C,0xE0,0x03,0xEB,0x51,0x04, ++0x07,0xEB,0x84,0x04,0xB4,0xF8,0x00,0x44, ++0x06,0xEB,0x43,0x05,0x44,0x55,0x05,0x44, ++0x24,0x0A,0x5B,0x1C,0x6C,0x70,0xB3,0xEB, ++0x52,0x0F,0xEF,0xD3,0xB2,0xEB,0x43,0x0F, ++0x08,0xD0,0x03,0xEB,0x51,0x01,0x07,0xEB, ++0x81,0x01,0xB1,0xF8,0x00,0x14,0x06,0xEB, ++0x43,0x02,0x81,0x54,0xF0,0xBD,0x2D,0xE9, ++0xF0,0x47,0x80,0x46,0x89,0x46,0x92,0x46, ++0x08,0x9D,0x1C,0x46,0xFF,0xF7,0x48,0xFC, ++0x06,0x46,0x40,0x8C,0xA1,0x4F,0xD2,0x37, ++0xA7,0xF8,0x8E,0x00,0x40,0xF2,0x01,0x20, ++0x27,0xF8,0xD2,0x0C,0x08,0x20,0x78,0x87, ++0xA7,0xF8,0x3E,0x80,0x0B,0x20,0x78,0x87, ++0x49,0xEA,0x09,0x20,0xF8,0x87,0x20,0x20, ++0x78,0x87,0x44,0xF6,0x10,0x40,0xF8,0x87, ++0xD2,0x3F,0xB8,0xF1,0x90,0x0F,0x05,0xD0, ++0x49,0xF6,0x80,0x10,0xA7,0xF8,0x10,0x01, ++0x88,0x20,0x01,0xE0,0x48,0xF6,0x99,0x00, ++0xA7,0xF8,0x10,0x01,0xE0,0x07,0x01,0xD0, ++0x64,0x1C,0xE4,0xB2,0x19,0x20,0xA7,0xF8, ++0x0C,0x01,0xA7,0xF8,0x10,0x41,0x00,0x20, ++0xA7,0xF8,0x10,0x01,0x03,0x20,0xA7,0xF8, ++0x14,0x01,0x4F,0xF4,0x96,0x78,0x41,0x46, ++0x4F,0xF4,0x00,0x70,0xFF,0xF7,0xA7,0xFE, ++0x40,0x45,0x12,0xD1,0x38,0x88,0xB7,0xF8, ++0x14,0x01,0xFF,0xF7,0x25,0xFD,0xFF,0xF7, ++0x82,0xFE,0xFF,0xF7,0xF7,0xFE,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0x7E,0x48,0x40,0x1C,0xBD,0xE8, ++0xF0,0x87,0x00,0x21,0x22,0x46,0x28,0x46, ++0xFF,0xF7,0x72,0xFF,0x70,0x8C,0x80,0x07, ++0x18,0xD0,0xBA,0xF1,0x01,0x0F,0x50,0x46, ++0x03,0xD0,0x02,0x28,0x12,0xD1,0x01,0x20, ++0x0E,0xE0,0x02,0x20,0x04,0xE0,0x15,0xF8, ++0x10,0x10,0x29,0x54,0x40,0x1C,0x80,0xB2, ++0xA0,0x42,0xF8,0xD3,0x06,0xE0,0x15,0xF8, ++0x10,0x10,0x29,0x54,0x40,0x1C,0x80,0xB2, ++0xA0,0x42,0xF8,0xD3,0xB7,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA7,0xF8,0x60,0x01, ++0x00,0x20,0xD4,0xE7,0x30,0xB5,0x01,0x22, ++0x89,0xB0,0x40,0x21,0x02,0xAB,0x90,0x20, ++0x00,0x93,0x0C,0x23,0xFF,0xF7,0x73,0xFF, ++0x00,0x28,0x1F,0xD1,0x00,0x21,0x02,0xAA, ++0x53,0x18,0x50,0x5C,0x5B,0x79,0x98,0x42, ++0x03,0xD1,0x49,0x1C,0xC9,0xB2,0x05,0x29, ++0xF6,0xD3,0x5C,0x48,0x19,0x30,0x05,0x29, ++0x10,0xD0,0x00,0x21,0x5A,0x4B,0x55,0x5C, ++0x5C,0x5C,0xAC,0x42,0x03,0xD1,0x49,0x1C, ++0xC9,0xB2,0x05,0x29,0xF7,0xD3,0x05,0x29, ++0x04,0xD1,0x9D,0xF8,0x0D,0x10,0x89,0x07, ++0x00,0xD5,0x00,0x20,0x09,0xB0,0x30,0xBD, ++0x2D,0xE9,0xF0,0x47,0xFF,0xF7,0x9C,0xFB, ++0x04,0x46,0xC0,0x6A,0x00,0x26,0xFF,0xF7, ++0xF6,0xFB,0xFF,0xF7,0x4C,0xFE,0x60,0x8C, ++0x80,0x07,0x02,0xD5,0x00,0x25,0x4B,0x4F, ++0x02,0xE0,0x48,0x48,0x1C,0x38,0x92,0xE7, ++0x00,0x24,0x01,0x20,0x23,0x46,0x32,0x46, ++0x29,0x46,0xFF,0xF7,0xB7,0xFE,0xB8,0x47, ++0x08,0xB3,0x64,0x1C,0xE4,0xB2,0x10,0x2C, ++0xF3,0xD3,0x6D,0x1C,0xED,0xB2,0x04,0x2D, ++0xEE,0xD3,0x00,0x25,0x01,0x26,0x00,0x24, ++0x01,0x20,0x23,0x46,0x32,0x46,0x29,0x46, ++0xFF,0xF7,0xA4,0xFE,0xB8,0x47,0x70,0xB1, ++0x64,0x1C,0xE4,0xB2,0x10,0x2C,0xF3,0xD3, ++0x76,0x1C,0xF6,0xB2,0x10,0x2E,0xEE,0xD3, ++0x6D,0x1C,0xED,0xB2,0x04,0x2D,0xE9,0xD3, ++0x32,0x48,0x1A,0x30,0x67,0xE7,0x64,0x1C, ++0xB0,0x46,0x04,0xF0,0xFF,0x09,0x00,0x24, ++0x0B,0xE0,0x01,0x20,0x4B,0x46,0x32,0x46, ++0x29,0x46,0xFF,0xF7,0x87,0xFE,0xB8,0x47, ++0x38,0xB9,0x04,0xB9,0xB0,0x46,0x64,0x1C, ++0xE4,0xB2,0x76,0x1C,0xF6,0xB2,0x10,0x2E, ++0xEF,0xD3,0x08,0xEB,0x54,0x00,0x4B,0x46, ++0x29,0x46,0xC2,0xB2,0x01,0x20,0xFF,0xF7, ++0x75,0xFE,0x00,0x20,0x47,0xE7,0x10,0xB5, ++0xFF,0xF7,0x3E,0xFB,0x04,0x46,0xFF,0xF7, ++0xFD,0xFB,0x00,0x28,0x09,0xD1,0x00,0x21, ++0x84,0xF8,0x30,0x10,0xA1,0x8B,0x21,0xF4, ++0x00,0x41,0xA1,0x83,0xA1,0x8B,0x1C,0x4A, ++0x11,0x80,0x15,0xE6,0x70,0xB5,0xFF,0xF7, ++0x2B,0xFB,0x14,0x4D,0x04,0x46,0x28,0x8D, ++0x20,0xF0,0x20,0x00,0x28,0x85,0x00,0x26, ++0xA5,0xF8,0x14,0x61,0xFF,0xF7,0x40,0xFC, ++0x00,0x28,0x70,0xD1,0x28,0x8D,0x40,0xF0, ++0x20,0x00,0x28,0x85,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0xC8,0x40,0xB4,0xF8,0x6A,0x10, ++0x08,0x44,0x20,0xF0,0x01,0x00,0xA0,0x82, ++0xA0,0x8A,0xA0,0x8A,0x40,0xF4,0x00,0x40, ++0xA0,0x82,0x3C,0x20,0xE0,0x82,0xE0,0x8A, ++0xA5,0xF8,0x00,0x01,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0x0B,0xE0,0x00,0x50,0x00,0x25, ++0x40,0x42,0x0F,0x00,0x34,0x00,0x00,0x80, ++0x28,0xEC,0x03,0x20,0x85,0x77,0x03,0x20, ++0x40,0x51,0x00,0x25,0x20,0xFA,0x01,0xF1, ++0x21,0x83,0x21,0x8B,0xFF,0x29,0x00,0xD8, ++0x21,0x8B,0x60,0x83,0x60,0x8B,0x4F,0xF4, ++0x00,0x61,0x88,0x42,0x00,0xD2,0x60,0x8B, ++0xA6,0x83,0x94,0xF8,0x30,0x00,0x18,0xB1, ++0xA0,0x8B,0x40,0xF4,0x00,0x40,0xA0,0x83, ++0x60,0x8F,0xB0,0xF5,0x00,0x5F,0x2F,0xD0, ++0x0C,0xDC,0xB0,0xF5,0x00,0x7F,0x13,0xD0, ++0x88,0x42,0x24,0xD0,0xB0,0xF5,0x80,0x5F, ++0x16,0xD1,0xA0,0x8B,0x40,0xF0,0x02,0x00, ++0xA0,0x83,0x11,0xE0,0xB0,0xF5,0x80,0x4F, ++0x22,0xD0,0xB0,0xF5,0x00,0x4F,0x0B,0xD1, ++0xA0,0x8B,0x40,0xF0,0x05,0x00,0xF3,0xE7, ++0xA0,0x8B,0x20,0xF0,0x07,0x00,0xA0,0x83, ++0x20,0x8B,0x40,0xF4,0x00,0x50,0x20,0x83, ++0xE0,0x8F,0x80,0x1E,0x09,0x28,0x20,0xD2, ++0xDF,0xE8,0x00,0xF0,0x12,0x18,0x4A,0x50, ++0x56,0x5C,0x62,0x68,0x6E,0x00,0xA0,0x8B, ++0x40,0xF0,0x01,0x00,0xDC,0xE7,0x3E,0xE0, ++0xA0,0x8B,0x40,0xF0,0x03,0x00,0xD7,0xE7, ++0xA0,0x8B,0x40,0xF0,0x04,0x00,0xD3,0xE7, ++0xA0,0x8B,0x20,0xF0,0x78,0x00,0xA0,0x83, ++0x08,0x20,0x04,0xE0,0xA0,0x8B,0x40,0xF0, ++0x08,0x00,0xA0,0x83,0x0E,0x20,0xA4,0xF8, ++0x6E,0x00,0xA0,0x8B,0x40,0xF0,0x80,0x00, ++0xA0,0x83,0xFF,0xF7,0x10,0xFD,0x00,0x23, ++0x1A,0x46,0x19,0x46,0x18,0x46,0xFF,0xF7, ++0xBD,0xFD,0x00,0x28,0x1B,0xD1,0xB5,0xF8, ++0xB0,0x00,0x20,0x84,0xB5,0xF8,0x5C,0x01, ++0xE0,0x83,0xB5,0xF8,0x60,0x01,0x60,0x84, ++0x60,0x8C,0x20,0xF0,0x03,0x00,0x60,0x84, ++0xFF,0xF7,0x39,0xFF,0xFE,0x49,0x88,0x42, ++0x06,0xD0,0x02,0x20,0xFF,0xF7,0x76,0xFA, ++0xFF,0xF7,0xD2,0xFE,0x00,0x28,0x02,0xD1, ++0xFF,0xF7,0xED,0xFC,0x00,0x20,0x70,0xBD, ++0xA0,0x8B,0x40,0xF0,0x10,0x00,0xA0,0x83, ++0x14,0x20,0xCC,0xE7,0xA0,0x8B,0x40,0xF0, ++0x18,0x00,0xA0,0x83,0x1A,0x20,0xC6,0xE7, ++0xA0,0x8B,0x40,0xF0,0x20,0x00,0xA0,0x83, ++0x22,0x20,0xC0,0xE7,0xA0,0x8B,0x40,0xF0, ++0x28,0x00,0xA0,0x83,0x28,0x20,0xBA,0xE7, ++0xA0,0x8B,0x40,0xF0,0x30,0x00,0xA0,0x83, ++0x2A,0x20,0xB4,0xE7,0xA0,0x8B,0x40,0xF0, ++0x38,0x00,0xA0,0x83,0x38,0x20,0xAE,0xE7, ++0xA0,0x8B,0x40,0xF0,0x40,0x00,0xA0,0x83, ++0x46,0x20,0xA8,0xE7,0x70,0xB5,0xFF,0xF7, ++0x3F,0xFA,0xE2,0x4E,0x04,0x46,0x30,0x8D, ++0x20,0xF0,0x20,0x00,0x30,0x85,0x00,0x25, ++0xA6,0xF8,0x14,0x51,0xFF,0xF7,0x54,0xFB, ++0x00,0x28,0x7D,0xD1,0x30,0x8D,0x40,0xF0, ++0x20,0x00,0x30,0x85,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0xC8,0x40,0xB4,0xF8,0x6A,0x10, ++0x08,0x44,0x20,0xF0,0x01,0x00,0xA0,0x82, ++0xA0,0x8A,0xA0,0x8A,0x40,0xF4,0x00,0x40, ++0xA0,0x82,0x3C,0x20,0xE0,0x82,0xE0,0x8A, ++0xA6,0xF8,0x00,0x01,0xA0,0x8F,0x94,0xF8, ++0x73,0x10,0x20,0xFA,0x01,0xF1,0x21,0x83, ++0x21,0x8B,0xFF,0x29,0x00,0xD8,0x21,0x8B, ++0x60,0x83,0x60,0x8B,0x4F,0xF4,0x00,0x61, ++0x88,0x42,0x00,0xD2,0x60,0x8B,0xA5,0x83, ++0x94,0xF8,0x30,0x00,0x18,0xB1,0xA0,0x8B, ++0x40,0xF4,0x00,0x40,0xA0,0x83,0x60,0x8F, ++0xB0,0xF5,0x00,0x5F,0x2D,0xD0,0x0B,0xDC, ++0xB0,0xF5,0x00,0x7F,0x12,0xD0,0x88,0x42, ++0x14,0xD0,0xB0,0xF5,0x80,0x5F,0x15,0xD1, ++0xA0,0x8B,0x40,0xF0,0x02,0x00,0x10,0xE0, ++0xB0,0xF5,0x80,0x4F,0x21,0xD0,0xB0,0xF5, ++0x00,0x4F,0x0B,0xD1,0xA0,0x8B,0x40,0xF0, ++0x05,0x00,0x06,0xE0,0xA0,0x8B,0x20,0xF0, ++0x07,0x00,0x02,0xE0,0xA0,0x8B,0x40,0xF0, ++0x01,0x00,0xA0,0x83,0x20,0x8B,0xA1,0x8E, ++0x08,0x43,0x20,0x83,0xE0,0x8F,0x0B,0x28, ++0x1D,0xD2,0xDF,0xE8,0x00,0xF0,0x1C,0x0E, ++0x15,0x22,0x28,0x2E,0x34,0x3A,0x40,0x46, ++0x4C,0x00,0xA0,0x8B,0x40,0xF0,0x03,0x00, ++0xEB,0xE7,0xA0,0x8B,0x40,0xF0,0x04,0x00, ++0xE7,0xE7,0xA0,0x8B,0x40,0xF0,0x40,0x00, ++0xA0,0x83,0x0A,0x20,0x05,0xE0,0x0B,0xE0, ++0xA0,0x8B,0x20,0xF0,0x78,0x00,0xA0,0x83, ++0x08,0x20,0xA4,0xF8,0x6E,0x00,0xA0,0x8B, ++0x40,0xF0,0x80,0x00,0xA0,0x83,0x00,0x20, ++0x70,0xBD,0xA0,0x8B,0x40,0xF0,0x08,0x00, ++0xA0,0x83,0x0E,0x20,0xF1,0xE7,0xA0,0x8B, ++0x40,0xF0,0x10,0x00,0xA0,0x83,0x14,0x20, ++0xEB,0xE7,0xA0,0x8B,0x40,0xF0,0x18,0x00, ++0xA0,0x83,0x1A,0x20,0xE5,0xE7,0xA0,0x8B, ++0x40,0xF0,0x20,0x00,0xA0,0x83,0x22,0x20, ++0xDF,0xE7,0xA0,0x8B,0x40,0xF0,0x28,0x00, ++0xA0,0x83,0x28,0x20,0xD9,0xE7,0xA0,0x8B, ++0x40,0xF0,0x30,0x00,0xA0,0x83,0x2A,0x20, ++0xD3,0xE7,0xA0,0x8B,0x40,0xF0,0x38,0x00, ++0xA0,0x83,0x38,0x20,0xCD,0xE7,0xA0,0x8B, ++0x40,0xF0,0x40,0x00,0xA0,0x83,0x46,0x20, ++0xC7,0xE7,0x2D,0xE9,0xFF,0x4F,0x81,0x46, ++0x83,0xB0,0x1D,0x46,0xFF,0xF7,0x7C,0xF9, ++0x04,0x46,0xB0,0xF8,0x76,0x00,0x4F,0xF0, ++0x00,0x0A,0x00,0xEA,0x09,0x00,0xD0,0x46, ++0x41,0x19,0x20,0x8F,0x56,0x46,0x81,0x42, ++0x04,0xD9,0x79,0x48,0x3B,0x38,0x07,0xB0, ++0xBD,0xE8,0xF0,0x8F,0xE0,0x6A,0xFF,0xF7, ++0xC6,0xF9,0xFF,0xF7,0x1C,0xFC,0x60,0x8C, ++0x74,0x4F,0xA7,0xF8,0x60,0x01,0x4F,0xF0, ++0x00,0x0B,0x40,0xF2,0x01,0x20,0x38,0x80, ++0x61,0x8F,0x04,0x98,0x69,0x43,0xFF,0xF7, ++0xE0,0xF9,0x61,0x8F,0xA7,0xF8,0x6C,0x11, ++0xA7,0xF8,0x70,0xB1,0x94,0xF8,0x73,0x10, ++0x05,0xFA,0x01,0xF1,0xB9,0x85,0xA7,0xF8, ++0x70,0x00,0x00,0x0C,0xA7,0xF8,0x74,0x00, ++0x38,0x89,0x20,0xF0,0x04,0x00,0x38,0x81, ++0xFF,0xF7,0x8E,0xFA,0x01,0x90,0x98,0xB1, ++0xFF,0xF7,0x5E,0xFA,0xFF,0xF7,0xBB,0xFB, ++0xFF,0xF7,0x30,0xFC,0x0A,0xF1,0x01,0x00, ++0xC0,0xB2,0x05,0x28,0x82,0x46,0xD4,0xD3, ++0xB7,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA7,0xF8,0x60,0x01,0x01,0x98,0xBE,0xE7, ++0xD2,0x37,0x37,0xF8,0xAA,0x0C,0x40,0xF0, ++0x01,0x00,0x27,0xF8,0xAA,0x0C,0x0B,0x20, ++0x78,0x87,0xA7,0xF8,0x3E,0xB0,0xA7,0xF8, ++0x3E,0x90,0x4F,0xEA,0x19,0x40,0xF8,0x87, ++0x20,0x20,0x78,0x87,0x94,0xF8,0x31,0x00, ++0x4F,0xEA,0x00,0x20,0xF8,0x87,0xD2,0x3F, ++0x20,0x8B,0x80,0x04,0x06,0xD5,0x49,0xF6, ++0x80,0x00,0xA7,0xF8,0x10,0x01,0x48,0xF6, ++0xB0,0x00,0x08,0xE0,0x48,0xF2,0x01,0x00, ++0xA7,0xF8,0x10,0x01,0x4B,0xF2,0x98,0x00, ++0xA7,0xF8,0x10,0x01,0x88,0x20,0xA7,0xF8, ++0x10,0x01,0x18,0x20,0xA7,0xF8,0x0C,0x01, ++0x68,0x1E,0xA7,0xF8,0x10,0x01,0x58,0xEA, ++0x06,0x00,0x02,0x90,0x04,0xD0,0x00,0x20, ++0xFF,0xF7,0x51,0xF9,0xA7,0xF8,0x04,0xB1, ++0x03,0x20,0xA7,0xF8,0x14,0x01,0x4F,0xF4, ++0x7A,0x70,0x05,0xFB,0x00,0xF1,0x40,0xF2, ++0x01,0x20,0xFF,0xF7,0x80,0xFB,0x05,0xEB, ++0x45,0x01,0xC1,0xEB,0xC5,0x11,0xB0,0xEB, ++0xC1,0x0F,0x19,0xD1,0xFF,0xF7,0xFC,0xF9, ++0xFF,0xF7,0x59,0xFB,0xFF,0xF7,0xCE,0xFB, ++0x08,0xF1,0x01,0x00,0xC0,0xB2,0x05,0x28, ++0x80,0x46,0x9C,0xD3,0x00,0x20,0xFF,0xF7, ++0x2E,0xF9,0xA7,0xF8,0x04,0xB1,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0x25,0x48,0x18,0x38,0x56,0xE7, ++0x02,0x98,0x20,0xB1,0x00,0x20,0xFF,0xF7, ++0x1E,0xF9,0xA7,0xF8,0x04,0xB1,0xB7,0xF8, ++0x44,0x01,0xC0,0x07,0x1D,0xD0,0x05,0x98, ++0x48,0xB1,0xA2,0x8F,0x4F,0xF4,0x00,0x70, ++0x82,0x42,0x00,0xD9,0x02,0x46,0x05,0x98, ++0x00,0x21,0xFF,0xF7,0x2D,0xFC,0xB7,0xF8, ++0x48,0x01,0xB7,0xF8,0x4C,0x01,0x05,0x2E, ++0x02,0xD2,0x76,0x1C,0xF6,0xB2,0x44,0xE7, ++0xB7,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA7,0xF8,0x60,0x01,0x10,0x48,0x41,0x38, ++0x2D,0xE7,0xFF,0xF7,0xFD,0xF9,0x30,0xB1, ++0xB7,0xF8,0x60,0x11,0x21,0xF0,0x03,0x01, ++0xA7,0xF8,0x60,0x11,0x23,0xE7,0x05,0x98, ++0x48,0xB1,0xA2,0x8F,0x4F,0xF4,0x00,0x70, ++0x82,0x42,0x00,0xD9,0x02,0x46,0x05,0x98, ++0x00,0x21,0xFF,0xF7,0x05,0xFC,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0x00,0x20,0x0F,0xE7,0x00,0x00, ++0x4D,0x00,0x00,0x80,0x00,0x50,0x00,0x25, ++0xFF,0x48,0x00,0x88,0xC1,0x07,0x02,0xD0, ++0x4F,0xF0,0xFF,0x30,0x70,0x47,0xC0,0xF3, ++0x45,0x00,0x70,0x47,0x2D,0xE9,0xFF,0x4F, ++0x82,0x46,0x81,0xB0,0x0F,0x46,0x1E,0x46, ++0xDD,0xF8,0x38,0x90,0xFF,0xF7,0x64,0xF8, ++0xB0,0xF8,0x76,0x20,0x04,0x46,0x90,0xF8, ++0x73,0x10,0x02,0xEA,0x0A,0x02,0x00,0x8F, ++0x8A,0x40,0x3A,0x44,0x88,0x40,0x4A,0x44, ++0x90,0x42,0x02,0xD2,0xEF,0x48,0x05,0xB0, ++0xE6,0xE6,0xE0,0x6A,0xFF,0xF7,0xAF,0xF8, ++0xFF,0xF7,0x05,0xFB,0x61,0x8C,0xDF,0xF8, ++0xB0,0xB3,0xAB,0xF8,0x60,0x11,0x40,0xF2, ++0x01,0x21,0xAB,0xF8,0x00,0x10,0x4D,0x46, ++0xB4,0xF8,0x68,0x00,0xC0,0x1B,0x48,0x45, ++0x00,0xD8,0x05,0x46,0x00,0x2D,0x7D,0xD0, ++0xB4,0xF8,0x6A,0x10,0x03,0x98,0x69,0x43, ++0xFF,0xF7,0xBF,0xF8,0x01,0x46,0x58,0x46, ++0xAB,0xF8,0x2C,0x50,0xBB,0xF8,0x40,0x21, ++0x52,0x07,0x18,0xD0,0x00,0xF5,0x8E,0x70, ++0x01,0x22,0x02,0x80,0x02,0x88,0x22,0xF0, ++0x7E,0x02,0x02,0x80,0x02,0x88,0x6F,0xF0, ++0x01,0x03,0x03,0xEB,0x45,0x03,0x1A,0x43, ++0x02,0x80,0x02,0x88,0x22,0xF4,0xFC,0x52, ++0x02,0x80,0x02,0x88,0x42,0xEA,0xC7,0x12, ++0x02,0x80,0xA0,0xF5,0x8E,0x70,0x80,0x46, ++0xA0,0xF8,0x70,0x10,0x09,0x0C,0xA0,0xF8, ++0x74,0x10,0x01,0x89,0x21,0xF0,0x04,0x01, ++0x01,0x81,0xFF,0xF7,0x55,0xF9,0x08,0xB1, ++0x41,0x46,0xC1,0xE0,0xB8,0xF8,0x28,0x00, ++0x40,0xF0,0x01,0x00,0xA8,0xF8,0x28,0x00, ++0x0B,0x20,0xA8,0xF8,0x0C,0x01,0x94,0xF8, ++0x30,0x00,0x00,0x28,0x94,0xF8,0x74,0x00, ++0x00,0xD1,0x00,0xE0,0x40,0x1E,0x07,0xFA, ++0x00,0xF7,0xA8,0xF8,0x10,0x71,0xA8,0xF8, ++0x10,0xA1,0x4F,0xEA,0x1A,0x40,0xA8,0xF8, ++0x10,0x01,0x20,0x20,0xA8,0xF8,0x0C,0x01, ++0x94,0xF8,0x31,0x00,0x4F,0xEA,0x00,0x20, ++0xA8,0xF8,0x10,0x01,0x20,0x8B,0x80,0x04, ++0x06,0xD5,0x49,0xF6,0x80,0x00,0xA8,0xF8, ++0x10,0x01,0x48,0xF6,0x88,0x00,0x05,0xE0, ++0x48,0xF2,0x01,0x00,0xA8,0xF8,0x10,0x01, ++0x48,0xF6,0x98,0x00,0xA8,0xF8,0x10,0x01, ++0x03,0x20,0xA8,0xF8,0x14,0x01,0x4F,0xF4, ++0x7A,0x71,0x40,0xF2,0x01,0x20,0xFF,0xF7, ++0x62,0xFA,0x00,0x27,0xB0,0xF5,0x7A,0x7F, ++0x12,0xD1,0xFF,0xF7,0xE1,0xF8,0xFF,0xF7, ++0x3E,0xFA,0x00,0xE0,0x3F,0xE0,0xB8,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA8,0xF8, ++0x60,0x01,0xFF,0xF7,0xAB,0xFA,0xA8,0xF8, ++0x1C,0x71,0x9E,0x48,0x23,0x30,0x5A,0xE7, ++0xB8,0xF8,0x44,0x01,0xC0,0x07,0x15,0xD0, ++0x2E,0xB1,0xB4,0xF8,0x6C,0x20,0x00,0x21, ++0x30,0x46,0xFF,0xF7,0x25,0xFB,0xB8,0xF8, ++0x48,0x01,0xB8,0xF8,0x4C,0x01,0xB8,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA8,0xF8, ++0x60,0x01,0xA8,0xF8,0x1C,0x71,0x91,0x48, ++0x80,0x1F,0x40,0xE7,0xFF,0xF7,0xF8,0xF8, ++0x30,0xB1,0xB8,0xF8,0x60,0x11,0x21,0xF0, ++0x03,0x01,0xA8,0xF8,0x60,0x11,0x36,0xE7, ++0x5E,0xB1,0xB4,0xF8,0x6C,0x20,0x4F,0xF4, ++0x00,0x70,0x6A,0x43,0x82,0x42,0x00,0xD9, ++0x02,0x46,0x00,0x21,0x30,0x46,0xFF,0xF7, ++0xFF,0xFA,0xA8,0xF8,0x1C,0x71,0xB9,0xEB, ++0x05,0x08,0x3C,0xD0,0x94,0xF8,0x73,0x10, ++0x0A,0xF1,0x01,0x0A,0x28,0xFA,0x01,0xF0, ++0x03,0x99,0x87,0xB2,0x94,0xF8,0x74,0x00, ++0x05,0xFA,0x00,0xF0,0x00,0xEB,0x01,0x09, ++0x1E,0xB1,0xB4,0xF8,0x6C,0x00,0x05,0xFB, ++0x00,0x66,0x37,0xB1,0x3B,0x46,0x32,0x46, ++0x49,0x46,0x50,0x46,0xFF,0xF7,0x57,0xF8, ++0xC8,0xB9,0x94,0xF8,0x73,0x10,0x07,0xFA, ++0x01,0xF0,0x94,0xF8,0x74,0x10,0x00,0xFA, ++0x01,0xF1,0x01,0xEB,0x09,0x02,0x1E,0xB1, ++0xB4,0xF8,0x6C,0x10,0x00,0xFB,0x01,0x66, ++0xB8,0xEB,0x00,0x03,0x0A,0xEB,0x07,0x00, ++0x0D,0xD0,0x00,0x93,0x00,0x21,0x33,0x46, ++0xFF,0xF7,0x4E,0xF8,0x38,0xB1,0x59,0x46, ++0xB1,0xF8,0x60,0x21,0x22,0xF0,0x03,0x02, ++0xA1,0xF8,0x60,0x21,0xE7,0xE6,0xBB,0xF8, ++0x60,0x11,0x21,0xF0,0x03,0x01,0xAB,0xF8, ++0x60,0x11,0x00,0x20,0xDF,0xE6,0x2D,0xE9, ++0xF0,0x5F,0x80,0x46,0x0E,0x46,0x93,0x46, ++0x0A,0x9D,0x99,0x46,0xFE,0xF7,0x2C,0xFF, ++0x04,0x46,0xC0,0x6A,0xFE,0xF7,0x87,0xFF, ++0xFF,0xF7,0xDD,0xF9,0x60,0x8C,0x58,0x4F, ++0xA7,0xF8,0x60,0x01,0x40,0xF2,0x01,0x2A, ++0xA7,0xF8,0x00,0xA0,0x58,0x46,0xB4,0xF8, ++0x6A,0x10,0x69,0x43,0xFE,0xF7,0xA1,0xFF, ++0xBD,0x85,0xB7,0xF8,0x40,0x11,0x49,0x07, ++0x15,0xD0,0x07,0xF5,0x8E,0x77,0x01,0x21, ++0x39,0x80,0x39,0x88,0x21,0xF0,0x7E,0x01, ++0x39,0x80,0x39,0x88,0x41,0xF0,0x02,0x01, ++0x39,0x80,0x39,0x88,0x21,0xF4,0xFC,0x51, ++0x39,0x80,0x39,0x88,0x41,0xEA,0xC6,0x11, ++0x39,0x80,0xA7,0xF5,0x8E,0x77,0xA7,0xF8, ++0x70,0x00,0x00,0x0C,0xA7,0xF8,0x74,0x00, ++0x38,0x89,0x20,0xF0,0x04,0x00,0x38,0x81, ++0xFF,0xF7,0x3E,0xF8,0x00,0x28,0x76,0xD1, ++0x38,0x8D,0x40,0xF0,0x01,0x00,0x38,0x85, ++0x0B,0x20,0xA7,0xF8,0x0C,0x01,0x94,0xF8, ++0x30,0x00,0x00,0x28,0x94,0xF8,0x74,0x00, ++0x00,0xD1,0x00,0xE0,0x40,0x1E,0x06,0xFA, ++0x00,0xF6,0xA7,0xF8,0x10,0x61,0xA7,0xF8, ++0x10,0x81,0x4F,0xEA,0x18,0x40,0xA7,0xF8, ++0x10,0x01,0x20,0x20,0xA7,0xF8,0x0C,0x01, ++0x94,0xF8,0x31,0x00,0x4F,0xEA,0x00,0x20, ++0xA7,0xF8,0x10,0x01,0x20,0x8B,0x80,0x04, ++0x06,0xD5,0x49,0xF6,0x80,0x00,0xA7,0xF8, ++0x10,0x01,0x48,0xF6,0xB0,0x00,0x09,0xE0, ++0x48,0xF2,0x01,0x00,0xA7,0xF8,0x10,0x01, ++0x4B,0xF2,0x98,0x00,0xA7,0xF8,0x10,0x01, ++0x48,0xF6,0x88,0x00,0xA7,0xF8,0x10,0x01, ++0x18,0x20,0xA7,0xF8,0x0C,0x01,0x4F,0xF0, ++0xFF,0x30,0x00,0xEB,0x55,0x00,0xA7,0xF8, ++0x10,0x01,0x03,0x20,0xA7,0xF8,0x14,0x01, ++0x4F,0xF4,0x7A,0x78,0x41,0x46,0x50,0x46, ++0xFF,0xF7,0x41,0xF9,0x00,0x26,0x40,0x45, ++0x11,0xD1,0xFE,0xF7,0xC1,0xFF,0xFF,0xF7, ++0x1E,0xF9,0xB7,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA7,0xF8,0x60,0x01,0xFF,0xF7, ++0x8D,0xF9,0xA7,0xF8,0x1C,0x61,0x0F,0x48, ++0x23,0x30,0xBD,0xE8,0xF0,0x9F,0xB7,0xF8, ++0x44,0x01,0xC0,0x07,0x1D,0xD0,0xB9,0xF1, ++0x00,0x0F,0x05,0xD0,0xB4,0xF8,0x6C,0x20, ++0x00,0x21,0x48,0x46,0xFF,0xF7,0x04,0xFA, ++0x07,0xF5,0xA4,0x77,0x38,0x88,0xB8,0x88, ++0x38,0x8B,0x20,0xF0,0x03,0x00,0x38,0x83, ++0x27,0xF8,0x2C,0x6C,0x06,0xE0,0x0B,0xE0, ++0x44,0x51,0x00,0x25,0x12,0x00,0x00,0x80, ++0x00,0x50,0x00,0x25,0xFA,0x48,0x80,0x1F, ++0xDB,0xE7,0xFE,0xF7,0xD1,0xFF,0x30,0xB1, ++0xB7,0xF8,0x60,0x11,0x21,0xF0,0x03,0x01, ++0xA7,0xF8,0x60,0x11,0xD1,0xE7,0xB9,0xF1, ++0x00,0x0F,0x0B,0xD0,0xB4,0xF8,0x6C,0x20, ++0x4F,0xF4,0x00,0x70,0x6A,0x43,0x82,0x42, ++0x00,0xD9,0x02,0x46,0x00,0x21,0x48,0x46, ++0xFF,0xF7,0xD6,0xF9,0xB7,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA7,0xF8,0x60,0x01, ++0xA7,0xF8,0x1C,0x61,0x00,0x20,0xB8,0xE7, ++0xE8,0x4A,0x01,0x46,0x00,0x20,0x12,0x88, ++0xD3,0x07,0x09,0xD0,0x01,0x29,0x02,0xD1, ++0xE3,0x48,0x00,0x1F,0x70,0x47,0x02,0x29, ++0xFC,0xD1,0xE1,0x48,0x2A,0x30,0x70,0x47, ++0x53,0x06,0x09,0xD4,0x01,0x29,0x02,0xD1, ++0xDD,0x48,0xC0,0x1F,0x70,0x47,0x02,0x29, ++0xFC,0xD1,0xDB,0x48,0x29,0x30,0x70,0x47, ++0x12,0x06,0xFC,0xD4,0x01,0x29,0x02,0xD1, ++0xD7,0x48,0xC0,0x1E,0x70,0x47,0x02,0x29, ++0xFC,0xD1,0xD5,0x48,0x2C,0x30,0x70,0x47, ++0x70,0xB5,0xCB,0x07,0xD4,0x4D,0x0B,0xD0, ++0x4B,0x08,0x05,0xEB,0x83,0x03,0xB3,0xF8, ++0x00,0x44,0xE4,0xB2,0x04,0xEB,0x00,0x24, ++0xA3,0xF8,0x00,0x44,0x49,0x1C,0x52,0x1E, ++0x00,0x23,0x00,0xEB,0x00,0x24,0x06,0xE0, ++0x03,0xEB,0x51,0x06,0x05,0xEB,0x86,0x06, ++0xA6,0xF8,0x00,0x44,0x5B,0x1C,0xB3,0xEB, ++0x52,0x0F,0xF5,0xD3,0xB2,0xEB,0x43,0x0F, ++0x0A,0xD0,0x03,0xEB,0x51,0x01,0x05,0xEB, ++0x81,0x01,0xB1,0xF8,0x00,0x24,0x02,0xF4, ++0x7F,0x42,0x10,0x44,0xA1,0xF8,0x00,0x04, ++0x70,0xBD,0xF0,0xB5,0xCB,0x07,0xBE,0x4F, ++0x0E,0xD0,0x4B,0x08,0x07,0xEB,0x83,0x03, ++0xB3,0xF8,0x00,0x44,0x05,0x78,0xE4,0xB2, ++0x04,0xEB,0x05,0x24,0xA3,0xF8,0x00,0x44, ++0x49,0x1C,0x52,0x1E,0x01,0x25,0x00,0xE0, ++0x00,0x25,0x00,0x23,0x0D,0xE0,0x05,0xEB, ++0x43,0x04,0x06,0x5D,0x04,0x44,0x64,0x78, ++0x06,0xEB,0x04,0x24,0x03,0xEB,0x51,0x06, ++0x07,0xEB,0x86,0x06,0xA6,0xF8,0x00,0x44, ++0x5B,0x1C,0xB3,0xEB,0x52,0x0F,0xEE,0xD3, ++0xB2,0xEB,0x43,0x0F,0x0D,0xD0,0x03,0xEB, ++0x51,0x01,0x07,0xEB,0x81,0x01,0xB1,0xF8, ++0x00,0x24,0x05,0xEB,0x43,0x03,0xC0,0x5C, ++0x02,0xF4,0x7F,0x42,0x10,0x44,0xA1,0xF8, ++0x00,0x04,0xF0,0xBD,0x2D,0xE9,0xF0,0x5F, ++0x80,0x46,0x0F,0x46,0x91,0x46,0x0A,0x9D, ++0x9B,0x46,0xFE,0xF7,0xB5,0xFD,0xB0,0xF8, ++0x68,0x20,0x04,0x46,0x9A,0x48,0x79,0x19, ++0x80,0x1D,0x91,0x42,0x49,0xD8,0x00,0x2D, ++0x47,0xD0,0xE0,0x6A,0xFE,0xF7,0x07,0xFE, ++0xFF,0xF7,0x5D,0xF8,0x60,0x8C,0x96,0x4E, ++0xA6,0xF8,0x60,0x01,0x40,0xF2,0x01,0x2A, ++0xA6,0xF8,0x00,0xA0,0x48,0x46,0xB4,0xF8, ++0x6A,0x10,0xFE,0xF7,0x22,0xFE,0xB5,0x85, ++0xB6,0xF8,0x40,0x11,0x4F,0xF0,0x01,0x09, ++0x49,0x07,0x18,0xD0,0x06,0xF5,0x8E,0x76, ++0xA6,0xF8,0x00,0x90,0x31,0x88,0x21,0xF0, ++0x7E,0x01,0x31,0x80,0x31,0x88,0x6F,0xF0, ++0x01,0x02,0x02,0xEB,0x45,0x02,0x11,0x43, ++0x31,0x80,0x31,0x88,0x21,0xF4,0xFC,0x51, ++0x31,0x80,0x31,0x88,0x41,0xEA,0xC7,0x11, ++0x31,0x80,0xA6,0xF5,0x8E,0x76,0xA6,0xF8, ++0x70,0x00,0x00,0x0C,0xA6,0xF8,0x74,0x00, ++0x30,0x89,0x40,0xF2,0x04,0x41,0x08,0x43, ++0x30,0x81,0xFE,0xF7,0xB9,0xFE,0x00,0x25, ++0x40,0xB1,0xB6,0xF8,0x60,0x11,0x21,0xF0, ++0x03,0x01,0xA6,0xF8,0x60,0x11,0xA6,0xF8, ++0x1C,0x51,0xCE,0xE6,0x30,0x8D,0x40,0xF0, ++0x01,0x00,0x30,0x85,0x4F,0xF0,0x0B,0x0C, ++0xA6,0xF8,0x0C,0xC1,0x94,0xF8,0x30,0x00, ++0x00,0x28,0x94,0xF8,0x74,0x00,0x00,0xD1, ++0x00,0xE0,0x40,0x1E,0x87,0x40,0xA6,0xF8, ++0x10,0x71,0x06,0xF5,0x86,0x76,0xA6,0xF8, ++0x04,0x80,0x4F,0xEA,0x18,0x40,0xB0,0x80, ++0x4F,0xF0,0x20,0x08,0xA6,0xF8,0x00,0x80, ++0x05,0x21,0x94,0xF8,0x31,0x00,0x01,0xEB, ++0x00,0x20,0xB0,0x80,0x4F,0xF4,0xD2,0x60, ++0xB0,0x80,0xA6,0xF5,0x86,0x76,0x94,0xF8, ++0x28,0x00,0x30,0xB9,0x4F,0xF4,0x58,0x60, ++0xA6,0xF8,0x10,0x01,0x48,0xF6,0x81,0x00, ++0x01,0xE0,0x48,0xF6,0x80,0x00,0xA6,0xF8, ++0x10,0x01,0xBB,0xF1,0x00,0x0F,0xB4,0xF8, ++0x6C,0x00,0xB4,0xF8,0x6E,0x10,0xA0,0xEB, ++0x01,0x02,0x4F,0xF0,0x00,0x01,0x03,0xD0, ++0x58,0x46,0xFF,0xF7,0x26,0xFF,0x02,0xE0, ++0xFF,0x20,0xFF,0xF7,0xF5,0xFE,0xA6,0xF8, ++0x14,0xC1,0x50,0x46,0x4F,0x4F,0x39,0x46, ++0xFE,0xF7,0xAD,0xFF,0xDF,0xF8,0x28,0xB1, ++0xB8,0x42,0x0B,0xF1,0x3D,0x0B,0x04,0xD1, ++0xA6,0xF8,0x1C,0x51,0xFE,0xF7,0x28,0xFE, ++0x21,0xE0,0x94,0xF8,0x28,0x00,0x01,0x28, ++0x29,0xD1,0xFE,0xF7,0xB8,0xFF,0xD6,0x36, ++0x26,0xF8,0xD6,0xAC,0xA6,0xF8,0x36,0x80, ++0x48,0xF2,0x0D,0x10,0x70,0x87,0x88,0x20, ++0x70,0x87,0xA6,0xF8,0x3E,0x90,0xD6,0x3E, ++0x39,0x46,0x4F,0xF4,0x00,0x70,0xFE,0xF7, ++0x8A,0xFF,0xB8,0x42,0x13,0xD1,0xA6,0xF8, ++0x1C,0x51,0xFE,0xF7,0x09,0xFE,0x20,0x8B, ++0x20,0xF4,0x00,0x60,0x20,0x83,0xFE,0xF7, ++0x62,0xFF,0xB6,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA6,0xF8,0x60,0x01,0xFE,0xF7, ++0xD1,0xFF,0x58,0x46,0x45,0xE6,0xB6,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA6,0xF8, ++0x60,0x01,0xA6,0xF8,0x1C,0x51,0x02,0x20, ++0xBD,0xE8,0xF0,0x5F,0x80,0xE6,0x2D,0xE9, ++0xF0,0x5F,0x80,0x46,0x0D,0x46,0x91,0x46, ++0xDD,0xF8,0x28,0xA0,0x1E,0x46,0xFE,0xF7, ++0xC3,0xFC,0x04,0x46,0xC0,0x6A,0xFE,0xF7, ++0x1E,0xFD,0xFE,0xF7,0x74,0xFF,0x60,0x8C, ++0x21,0x4F,0xA7,0xF8,0x60,0x01,0x40,0xF2, ++0x01,0x2B,0xA7,0xF8,0x00,0xB0,0x48,0x46, ++0xB4,0xF8,0x6A,0x10,0xFE,0xF7,0x39,0xFD, ++0xA7,0xF8,0x2C,0xA0,0xB7,0xF8,0x40,0x11, ++0x49,0x07,0x15,0xD0,0x07,0xF5,0x8E,0x77, ++0x01,0x21,0x39,0x80,0x39,0x88,0x21,0xF0, ++0x7E,0x01,0x39,0x80,0x39,0x88,0x41,0xF0, ++0x02,0x01,0x39,0x80,0x39,0x88,0x21,0xF4, ++0xFC,0x51,0x39,0x80,0x39,0x88,0x41,0xEA, ++0xC5,0x11,0x39,0x80,0xA7,0xF5,0x8E,0x77, ++0xA7,0xF8,0x70,0x00,0x00,0x0C,0xA7,0xF8, ++0x74,0x00,0x38,0x89,0x40,0xF2,0x04,0x41, ++0x08,0x43,0x38,0x81,0xFE,0xF7,0xD4,0xFD, ++0x4F,0xF0,0x00,0x09,0x80,0xB1,0xB7,0xF8, ++0x60,0x11,0x21,0xF0,0x03,0x01,0xA7,0xF8, ++0x60,0x11,0xA7,0xF8,0x1C,0x91,0xE8,0xE5, ++0x12,0x00,0x00,0x80,0x18,0x51,0x00,0x25, ++0x00,0x50,0x00,0x25,0x40,0x42,0x0F,0x00, ++0x38,0x8D,0x40,0xF0,0x01,0x00,0x38,0x85, ++0x4F,0xF0,0x0B,0x0C,0xA7,0xF8,0x0C,0xC1, ++0x94,0xF8,0x30,0x00,0x00,0x28,0x94,0xF8, ++0x74,0x00,0x00,0xD1,0x00,0xE0,0x40,0x1E, ++0x85,0x40,0xA7,0xF8,0x10,0x51,0x07,0xF5, ++0x86,0x77,0xA7,0xF8,0x04,0x80,0x4F,0xEA, ++0x18,0x40,0xB8,0x80,0x20,0x20,0x38,0x80, ++0x05,0x21,0x94,0xF8,0x31,0x00,0x01,0xEB, ++0x00,0x20,0xB8,0x80,0x4F,0xF4,0xD2,0x60, ++0xB8,0x80,0x4F,0xF4,0x58,0x60,0xB8,0x80, ++0x4B,0xF2,0x81,0x00,0xB8,0x80,0x88,0x20, ++0xB8,0x80,0x18,0x20,0x38,0x80,0x89,0x1F, ++0x01,0xEB,0x5A,0x00,0xB8,0x80,0x00,0x20, ++0xA7,0xF5,0x86,0x77,0x4F,0xF4,0x00,0x78, ++0xB6,0xB1,0x10,0xE0,0xB4,0xF8,0x6C,0x30, ++0x45,0x1C,0x03,0xFB,0x05,0xF1,0x41,0x45, ++0x22,0xDC,0xB4,0xF8,0x6E,0x10,0x5A,0x1A, ++0x03,0xFB,0x00,0xF1,0x03,0xFB,0x00,0x60, ++0xFF,0xF7,0x33,0xFE,0xA8,0xB2,0xB4,0xF8, ++0x68,0x10,0x81,0x42,0xEA,0xD8,0x13,0xE0, ++0x0E,0xE0,0xB4,0xF8,0x6C,0x10,0x45,0x1C, ++0x01,0xFB,0x05,0xF2,0x42,0x45,0x0B,0xDC, ++0xB4,0xF8,0x6E,0x20,0x8A,0x1A,0x41,0x43, ++0xFF,0x20,0xFF,0xF7,0xF1,0xFD,0xA8,0xB2, ++0xB4,0xF8,0x68,0x10,0x81,0x42,0xEC,0xD8, ++0xA7,0xF8,0x14,0xC1,0xFC,0x4C,0x58,0x46, ++0x21,0x46,0xFE,0xF7,0xA4,0xFE,0xA0,0x42, ++0x0F,0xD1,0xA7,0xF8,0x1C,0x91,0xFE,0xF7, ++0x23,0xFD,0xFE,0xF7,0x80,0xFE,0xB7,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA7,0xF8, ++0x60,0x01,0xFE,0xF7,0xEF,0xFE,0xF3,0x48, ++0x63,0xE5,0xB7,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA7,0xF8,0x60,0x01,0xA7,0xF8, ++0x1C,0x91,0x02,0x20,0xBD,0xE8,0xF0,0x5F, ++0x9E,0xE5,0x2D,0xE9,0xF0,0x41,0x00,0x24, ++0xEB,0x4F,0x05,0x46,0x0E,0x46,0x0A,0xE0, ++0xB7,0xF8,0x7C,0x00,0x35,0xEA,0x00,0x00, ++0x07,0xD0,0x01,0x20,0xFE,0xF7,0xD6,0xFB, ++0xFE,0xF7,0x62,0xFC,0x64,0x1C,0xB4,0x42, ++0xF2,0xD3,0x20,0x46,0xBD,0xE8,0xF0,0x81, ++0x2D,0xE9,0xF0,0x5F,0x05,0x46,0x0E,0x46, ++0x17,0x46,0xFE,0xF7,0xCD,0xFB,0x04,0x46, ++0xC0,0x6A,0xB2,0x46,0xFE,0xF7,0x27,0xFC, ++0xFE,0xF7,0x7D,0xFE,0x60,0x8C,0xDA,0x4E, ++0xA6,0xF8,0x60,0x01,0xB6,0xF8,0x80,0x00, ++0x40,0xF0,0x01,0x00,0xA6,0xF8,0x80,0x00, ++0x41,0xF2,0x01,0x60,0x30,0x80,0xB4,0xF8, ++0x68,0x00,0xB0,0x85,0x4F,0xF0,0x00,0x08, ++0xA6,0xF8,0x70,0x80,0xA6,0xF8,0x74,0x80, ++0x30,0x89,0x40,0xF2,0x04,0x41,0x08,0x43, ++0x30,0x81,0xFE,0xF7,0xF5,0xFC,0x30,0xB1, ++0xB6,0xF8,0x60,0x11,0x21,0xF0,0x03,0x01, ++0xA6,0xF8,0x60,0x11,0x0D,0xE5,0xD2,0x36, ++0x36,0xF8,0xAA,0x0C,0x40,0xF0,0x01,0x00, ++0x26,0xF8,0xAA,0x0C,0x4F,0xF0,0x0B,0x0C, ++0xA6,0xF8,0x3A,0xC0,0xA6,0xF8,0x3E,0x80, ++0xF5,0x87,0x28,0x0C,0xF0,0x87,0x20,0x20, ++0x70,0x87,0x05,0x21,0x94,0xF8,0x31,0x00, ++0x01,0xEB,0x00,0x20,0xF0,0x87,0x4F,0xF4, ++0xD2,0x60,0xF0,0x87,0xD2,0x3E,0x94,0xF8, ++0x28,0x00,0x30,0xB9,0x4F,0xF4,0x58,0x60, ++0xA6,0xF8,0x10,0x01,0x48,0xF6,0x81,0x00, ++0x01,0xE0,0x48,0xF6,0x80,0x00,0xA6,0xF8, ++0x10,0x01,0x00,0x20,0x11,0xE0,0xB4,0xF8, ++0x6C,0x30,0x45,0x1C,0x03,0xFB,0x05,0xF1, ++0xB1,0xF5,0x00,0x7F,0x0D,0xDC,0xB4,0xF8, ++0x6E,0x10,0x5A,0x1A,0x03,0xFB,0x00,0xF1, ++0x03,0xFB,0x00,0x70,0xFF,0xF7,0x6D,0xFD, ++0xA8,0xB2,0xB4,0xF8,0x68,0x10,0x81,0x42, ++0xE9,0xD8,0xB1,0x46,0xA6,0xF8,0x14,0xC1, ++0x00,0x27,0xDF,0xF8,0x8C,0x82,0x4D,0xE0, ++0x00,0x26,0x44,0xE0,0x01,0x20,0x45,0x46, ++0x41,0x46,0xFF,0xF7,0x66,0xFF,0xA8,0x42, ++0x17,0xD1,0xB9,0xF8,0x28,0x00,0x4C,0x46, ++0x20,0xF0,0x01,0x00,0xA9,0xF8,0x28,0x00, ++0xB9,0xF8,0x80,0x00,0x20,0xF0,0x01,0x00, ++0xA9,0xF8,0x80,0x00,0xFE,0xF7,0x60,0xFC, ++0xFE,0xF7,0xBD,0xFD,0xB4,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA4,0xF8,0x60,0x01, ++0x52,0xE0,0x2E,0xB9,0x09,0xF1,0x80,0x00, ++0x01,0x88,0x41,0xF0,0x10,0x01,0x01,0x80, ++0x00,0x25,0x4F,0xF4,0x80,0x6B,0x41,0x46, ++0x58,0x46,0xFE,0xF7,0xC4,0xFD,0x40,0x45, ++0xD7,0xD0,0xB4,0xF8,0x6A,0x10,0x05,0xEB, ++0x06,0x20,0x49,0x08,0x07,0xFB,0x01,0x00, ++0x3A,0xF8,0x10,0x10,0x09,0xF1,0x80,0x00, ++0x01,0x81,0x01,0x88,0x41,0xF0,0x20,0x01, ++0x01,0x80,0x6D,0x1C,0xAD,0xB2,0xFF,0x2D, ++0xE5,0xD9,0x76,0x1C,0xB6,0xB2,0xB4,0xF8, ++0x6A,0x00,0xB6,0xEB,0x50,0x2F,0xB5,0xD3, ++0x7F,0x1C,0xBF,0xB2,0xB4,0xF8,0x68,0x00, ++0xB8,0x42,0xAD,0xD8,0x41,0x20,0x4D,0x46, ++0xA9,0xF8,0x80,0x00,0x40,0xF2,0x01,0x27, ++0x46,0x46,0x41,0x46,0x38,0x46,0xFE,0xF7, ++0x96,0xFD,0xB0,0x42,0x17,0xD1,0x28,0x88, ++0x28,0x8D,0x20,0xF0,0x01,0x00,0x28,0x85, ++0xB5,0xF8,0x80,0x00,0x20,0xF0,0x01,0x00, ++0xA5,0xF8,0x80,0x00,0xFE,0xF7,0x0C,0xFC, ++0xFE,0xF7,0x69,0xFD,0xB5,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA5,0xF8,0x60,0x01, ++0x68,0x48,0x0F,0x38,0x4D,0xE4,0x94,0xF8, ++0x28,0x00,0x01,0x28,0x22,0xD1,0xFE,0xF7, ++0x92,0xFD,0xD6,0x35,0x25,0xF8,0xD6,0x7C, ++0x20,0x20,0xE8,0x86,0x48,0xF2,0x0D,0x10, ++0x68,0x87,0x88,0x20,0x68,0x87,0x01,0x20, ++0xE8,0x87,0xD6,0x3D,0x40,0x02,0x31,0x46, ++0xFE,0xF7,0x65,0xFD,0xB0,0x42,0x0D,0xD1, ++0xFE,0xF7,0xE6,0xFB,0xFE,0xF7,0x43,0xFD, ++0xB5,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA5,0xF8,0x60,0x01,0xFE,0xF7,0xB2,0xFD, ++0x54,0x48,0x26,0xE4,0x80,0x35,0xB5,0xF8, ++0xE0,0x00,0x20,0xF0,0x03,0x00,0xA5,0xF8, ++0xE0,0x00,0x28,0x88,0x20,0xF0,0x01,0x00, ++0x28,0x80,0x02,0x20,0xBD,0xE8,0xF0,0x5F, ++0x5E,0xE4,0x2D,0xE9,0xF8,0x4F,0x07,0x46, ++0x0D,0x46,0x92,0x46,0x1E,0x46,0xFE,0xF7, ++0xA3,0xFA,0x04,0x46,0xC0,0x6A,0xFE,0xF7, ++0xFE,0xFA,0xFE,0xF7,0x54,0xFD,0x60,0x8C, ++0xDF,0xF8,0x14,0x81,0xA8,0xF8,0x60,0x01, ++0x40,0xF2,0x01,0x29,0xA8,0xF8,0x00,0x90, ++0x00,0x21,0x32,0x46,0x50,0x46,0xFF,0xF7, ++0x98,0xFC,0xF0,0x07,0x06,0xD0,0xFF,0x20, ++0x00,0x90,0x01,0x22,0x31,0x46,0x68,0x46, ++0xFF,0xF7,0x8F,0xFC,0x0B,0x20,0xA8,0xF8, ++0x0C,0x01,0x94,0xF8,0x30,0x10,0x09,0xB1, ++0x4F,0xEA,0x55,0x05,0x21,0x8B,0x89,0x04, ++0x03,0xD5,0x29,0x02,0xA8,0xF8,0x10,0x11, ++0x01,0xE0,0xA8,0xF8,0x10,0x51,0xA8,0xF8, ++0x10,0x71,0x39,0x0C,0xA8,0xF8,0x10,0x11, ++0x20,0x25,0xA8,0xF8,0x0C,0x51,0x05,0x22, ++0x94,0xF8,0x31,0x10,0x02,0xEB,0x01,0x21, ++0xA8,0xF8,0x10,0x11,0x40,0xF2,0x91,0x61, ++0xA8,0xF8,0x10,0x11,0x94,0xF8,0x28,0x10, ++0x31,0xB9,0x4F,0xF4,0x58,0x61,0xA8,0xF8, ++0x10,0x11,0x48,0xF6,0x81,0x01,0x01,0xE0, ++0x48,0xF6,0x80,0x01,0xA8,0xF8,0x10,0x11, ++0x19,0x21,0xA8,0xF8,0x0C,0x11,0x06,0xF0, ++0x01,0x01,0x31,0x44,0xA8,0xF8,0x10,0x11, ++0x00,0x21,0xA8,0xF8,0x10,0x11,0xA8,0xF8, ++0x14,0x01,0x4F,0xF4,0x00,0x7A,0x18,0x4E, ++0x50,0x46,0x31,0x46,0xFE,0xF7,0xDB,0xFC, ++0x16,0x4F,0xB0,0x42,0x19,0xD0,0x94,0xF8, ++0x28,0x00,0x01,0x28,0x2A,0xD1,0xFE,0xF7, ++0xEE,0xFC,0xA8,0xF8,0x00,0x90,0xA8,0xF8, ++0x0C,0x51,0x48,0xF2,0x0D,0x10,0xA8,0xF8, ++0x10,0x01,0x88,0x20,0xA8,0xF8,0x10,0x01, ++0x01,0x20,0xA8,0xF8,0x14,0x01,0x31,0x46, ++0x50,0x46,0xFE,0xF7,0xC0,0xFC,0xB0,0x42, ++0x14,0xD1,0xFE,0xF7,0x41,0xFB,0xFE,0xF7, ++0x9E,0xFC,0xB8,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA8,0xF8,0x60,0x01,0xFE,0xF7, ++0x0D,0xFD,0x38,0x46,0xBD,0xE8,0xF8,0x8F, ++0x40,0x42,0x0F,0x00,0x4F,0x00,0x00,0x80, ++0x00,0x50,0x00,0x25,0xB8,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA8,0xF8,0x60,0x01, ++0x02,0x20,0xBD,0xE8,0xF8,0x4F,0xFF,0xF7, ++0xB7,0xBB,0x70,0xB5,0xFE,0xF7,0x00,0xFA, ++0x04,0x46,0xC0,0x6A,0xFE,0xF7,0x5B,0xFA, ++0xFE,0xF7,0xB1,0xFC,0x60,0x8C,0xFF,0x4E, ++0xA6,0xF8,0x8E,0x00,0x40,0xF2,0x01,0x20, ++0x26,0xF8,0xD2,0x0C,0x0B,0x20,0x70,0x87, ++0x00,0x21,0xF1,0x87,0x20,0x20,0x70,0x87, ++0x44,0xF6,0x03,0x40,0xF0,0x87,0x48,0xF6, ++0x99,0x00,0xF0,0x87,0xD2,0x3E,0x94,0xF8, ++0x30,0x00,0x08,0xB1,0x1C,0x20,0x00,0xE0, ++0x0E,0x20,0x19,0x22,0xA6,0xF8,0x0C,0x21, ++0xA6,0xF8,0x10,0x01,0xA6,0xF8,0x10,0x11, ++0x03,0x20,0xA6,0xF8,0x14,0x01,0x4F,0xF4, ++0x00,0x70,0xED,0x4D,0x29,0x46,0xFE,0xF7, ++0x6A,0xFC,0xA8,0x42,0x0A,0xD1,0x30,0x88, ++0xB6,0xF8,0x14,0x01,0xB6,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA6,0xF8,0x60,0x01, ++0xE6,0x48,0x70,0xBD,0x94,0xF8,0x30,0x00, ++0x58,0xB1,0x00,0x25,0x01,0x22,0x60,0x19, ++0x69,0x00,0x80,0x1C,0xFE,0xF7,0x38,0xFD, ++0x6D,0x1C,0xAD,0xB2,0x0E,0x2D,0xF5,0xD3, ++0x04,0xE0,0x0E,0x22,0x00,0x21,0xA0,0x1C, ++0xFE,0xF7,0x2E,0xFD,0xA2,0x78,0x01,0x20, ++0x21,0x18,0x8B,0x78,0x93,0x42,0x03,0xD1, ++0xC9,0x78,0xE3,0x78,0x99,0x42,0x03,0xD0, ++0x40,0x1C,0x80,0xB2,0x0E,0x28,0xF3,0xD3, ++0x60,0x74,0xB6,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA6,0xF8,0x60,0x01,0x00,0x20, ++0x70,0xBD,0x1F,0xB5,0xFE,0xF7,0x94,0xF9, ++0x41,0x8C,0x89,0x07,0x08,0xD0,0x40,0x8C, ++0x80,0x07,0x03,0xD5,0xCB,0x48,0x1C,0x30, ++0x04,0xB0,0x10,0xBD,0x00,0x20,0xFB,0xE7, ++0xC0,0x6A,0xFE,0xF7,0xE4,0xF9,0xFE,0xF7, ++0x3A,0xFC,0x01,0xAB,0x02,0x22,0x00,0x93, ++0x04,0x23,0x01,0x21,0xEE,0x20,0xFE,0xF7, ++0x2A,0xFD,0x00,0x28,0xEC,0xD1,0x9D,0xF8, ++0x04,0x00,0x04,0x23,0x01,0x21,0x20,0xF0, ++0x30,0x00,0x01,0xAA,0xC0,0xB2,0x40,0xF0, ++0x10,0x00,0x8D,0xF8,0x04,0x00,0xEF,0x20, ++0x00,0xF0,0x3E,0xF9,0xDC,0xE7,0x10,0xB5, ++0xFE,0xF7,0x66,0xF9,0x04,0x46,0xFE,0xF7, ++0x2E,0xFA,0x00,0x28,0x0A,0xD1,0x00,0x21, ++0x84,0xF8,0x30,0x10,0xA1,0x8B,0x21,0xF4, ++0x00,0x41,0xA1,0x83,0xA1,0x8B,0xAF,0x4A, ++0x6E,0x32,0x11,0x80,0x10,0xBD,0x70,0xB5, ++0xFE,0xF7,0x52,0xF9,0x04,0x46,0xC0,0x6A, ++0xFE,0xF7,0xAD,0xF9,0xFE,0xF7,0x03,0xFC, ++0xA8,0x4D,0x40,0xF2,0x01,0x20,0x25,0xF8, ++0xD2,0x0C,0x0B,0x20,0x68,0x87,0x00,0x20, ++0xE8,0x87,0xE8,0x87,0xE8,0x87,0x20,0x20, ++0x68,0x87,0x94,0xF8,0x31,0x00,0x4F,0xEA, ++0x00,0x20,0xE8,0x87,0xD2,0x3D,0x20,0x8B, ++0x80,0x04,0x02,0xD5,0x48,0xF6,0x80,0x00, ++0x04,0xE0,0x48,0xF2,0x01,0x00,0xA5,0xF8, ++0x10,0x01,0x88,0x20,0xA5,0xF8,0x10,0x01, ++0x01,0x20,0xA5,0xF8,0x14,0x01,0x00,0x24, ++0x4F,0xF4,0x96,0x76,0x28,0x88,0x80,0x05, ++0x08,0xD4,0x01,0x20,0xFE,0xF7,0x1A,0xF9, ++0xFE,0xF7,0xA6,0xF9,0x64,0x1C,0xB4,0x42, ++0xF4,0xD3,0x07,0xE0,0xB4,0x42,0x05,0xD2, ++0x28,0x88,0x00,0xF4,0x00,0x70,0x28,0x80, ++0x00,0x20,0x70,0xBD,0xFE,0xF7,0x30,0xFA, ++0xFE,0xF7,0x8D,0xFB,0xFE,0xF7,0x02,0xFC, ++0x8A,0x48,0x70,0xBD,0x2D,0xE9,0xF0,0x5F, ++0x06,0x46,0xFE,0xF7,0x05,0xF9,0x05,0x46, ++0xC0,0x6A,0xFE,0xF7,0x60,0xF9,0xFE,0xF7, ++0xB6,0xFB,0x68,0x8C,0x81,0x4C,0xA4,0xF8, ++0x8E,0x00,0x34,0xF8,0xD2,0x0C,0x00,0xF4, ++0x00,0x70,0x24,0xF8,0xD2,0x0C,0x0B,0x20, ++0x60,0x87,0x00,0x20,0xE0,0x87,0xE6,0x87, ++0x30,0x0C,0xE0,0x87,0x4F,0xF0,0x20,0x08, ++0xA4,0xF8,0x3A,0x80,0x09,0x21,0x95,0xF8, ++0x32,0x00,0x41,0xEA,0x00,0x20,0xE0,0x87, ++0x48,0xF2,0x0A,0x00,0xE0,0x87,0xD2,0x3C, ++0x95,0xF8,0x28,0x00,0x88,0x26,0x48,0xF2, ++0x0D,0x1A,0x08,0xB9,0xA4,0xF8,0x10,0xA1, ++0xA4,0xF8,0x10,0x61,0x01,0x27,0xA4,0xF8, ++0x14,0x71,0x4F,0xF4,0x00,0x7B,0xDF,0xF8, ++0xB8,0x91,0x58,0x46,0x49,0x46,0xFE,0xF7, ++0x66,0xFB,0x48,0x45,0x0E,0xD1,0xFE,0xF7, ++0xE7,0xF9,0xFE,0xF7,0x44,0xFB,0xFE,0xF7, ++0xB9,0xFB,0xB4,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA4,0xF8,0x60,0x01,0x63,0x48, ++0x25,0x38,0x3C,0xE4,0x95,0xF8,0x28,0x00, ++0x01,0x28,0x23,0xD1,0xFE,0xF7,0x6B,0xFB, ++0xD6,0x34,0x40,0xF2,0x01,0x20,0x24,0xF8, ++0xD6,0x0C,0xA4,0xF8,0x36,0x80,0xA4,0xF8, ++0x3A,0xA0,0x66,0x87,0xE7,0x87,0xD6,0x3C, ++0x4D,0x46,0x49,0x46,0x58,0x46,0xFE,0xF7, ++0x3E,0xFB,0xA8,0x42,0x0E,0xD1,0xFE,0xF7, ++0xBF,0xF9,0xFE,0xF7,0x1C,0xFB,0xFE,0xF7, ++0x91,0xFB,0xB4,0xF8,0x60,0x01,0x20,0xF0, ++0x03,0x00,0xA4,0xF8,0x60,0x01,0x4F,0x48, ++0x1A,0x30,0x14,0xE4,0x01,0x20,0xFF,0xF7, ++0x43,0xFA,0xB4,0xF8,0x60,0x11,0x21,0xF0, ++0x03,0x01,0xA4,0xF8,0x60,0x11,0x0A,0xE4, ++0x10,0xB5,0xFE,0xF7,0x85,0xF8,0x41,0x8C, ++0x44,0x48,0x3A,0x30,0xA0,0xF8,0x54,0x10, ++0x08,0x21,0x01,0x80,0xDD,0x21,0x81,0x80, ++0x20,0x21,0x01,0x80,0x48,0xF6,0x10,0x01, ++0x81,0x80,0x01,0x21,0x01,0x81,0x30,0xF8, ++0x54,0x1F,0x21,0xF0,0x03,0x01,0x01,0x80, ++0x10,0xBD,0x70,0xB5,0xFE,0xF7,0x6C,0xF8, ++0xD0,0xF8,0x84,0x50,0x04,0x46,0xC0,0x6A, ++0xFE,0xF7,0xC5,0xF8,0xFE,0xF7,0x1B,0xFB, ++0x60,0x8C,0x34,0x4C,0x3A,0x34,0xA4,0xF8, ++0x54,0x00,0x20,0x20,0x20,0x80,0x48,0xF2, ++0x0D,0x10,0xA0,0x80,0x88,0x20,0xA0,0x80, ++0x01,0x20,0x20,0x81,0xA4,0xF5,0x86,0x74, ++0x2D,0x4E,0x40,0x02,0x31,0x46,0xFE,0xF7, ++0xEA,0xFA,0xB0,0x42,0x07,0xD1,0xB4,0xF8, ++0x60,0x01,0x20,0xF0,0x03,0x00,0xA4,0xF8, ++0x60,0x01,0x28,0x48,0x70,0xBD,0xB4,0xF8, ++0x18,0x01,0x28,0x70,0xB4,0xF8,0x60,0x01, ++0x20,0xF0,0x03,0x00,0xA4,0xF8,0x60,0x01, ++0x00,0x20,0x70,0xBD,0x02,0x46,0x1F,0x48, ++0x00,0xB5,0x7A,0x30,0x00,0x88,0x80,0x07, ++0x02,0xD5,0x4F,0xF0,0xFF,0x30,0x01,0xE0, ++0xFE,0xF7,0xB6,0xFF,0x10,0x60,0x00,0xBD, ++0x2D,0xE9,0xF0,0x41,0x06,0x46,0x0F,0x46, ++0x90,0x46,0x1D,0x46,0xFE,0xF7,0x24,0xF8, ++0xE9,0x07,0x02,0xD0,0x15,0x48,0x22,0x38, ++0x48,0xE4,0x40,0x8C,0x11,0x4C,0x24,0x1D, ++0xA4,0xF8,0x8A,0x00,0x40,0xF2,0x01,0x20, ++0x24,0xF8,0xD6,0x0C,0x00,0x21,0x2A,0x46, ++0x40,0x46,0xFF,0xF7,0x1A,0xFA,0x08,0x20, ++0xE0,0x86,0x66,0x87,0x0B,0x20,0xE0,0x86, ++0x47,0xEA,0x07,0x21,0x61,0x87,0x20,0x21, ++0xE1,0x86,0x44,0xF6,0x10,0x41,0x61,0x87, ++0x48,0xF2,0x91,0x01,0x61,0x87,0x88,0x21, ++0x61,0x87,0x19,0x21,0xE1,0x86,0x65,0x87, ++0x00,0x21,0x07,0xE0,0xD2,0x50,0x00,0x25, ++0xA0,0x86,0x01,0x00,0x35,0x00,0x00,0x80, ++0x40,0x42,0x0F,0x00,0x61,0x87,0xE0,0x87, ++0xD6,0x3C,0x0D,0x4D,0x4F,0xF4,0x00,0x70, ++0x29,0x46,0xFE,0xF7,0x84,0xFA,0xA8,0x42, ++0x10,0xD1,0x20,0x88,0xB4,0xF8,0x14,0x01, ++0xFE,0xF7,0x02,0xF9,0xFE,0xF7,0x5F,0xFA, ++0xB4,0xF8,0x60,0x01,0x20,0xF0,0x03,0x00, ++0xA4,0xF8,0x60,0x01,0xFE,0xF7,0xCE,0xFA, ++0x02,0x48,0xB5,0xE7,0x00,0x20,0xB3,0xE7, ++0xA0,0x86,0x01,0x00,0x50,0x00,0x00,0x80, ++0x70,0xB5,0xFD,0xF7,0xCD,0xFF,0x4F,0xF4, ++0x80,0x61,0xFD,0x4D,0xC1,0x86,0x20,0x21, ++0x01,0x87,0x04,0x46,0x89,0x01,0x41,0x87, ++0xC9,0x10,0x81,0x87,0x0A,0x21,0xC1,0x87, ++0xFE,0xF7,0xEF,0xF9,0xFE,0xF7,0x8E,0xFC, ++0x00,0x28,0x1E,0xD1,0x21,0xE0,0x28,0x79, ++0x84,0xF8,0x31,0x00,0x68,0x79,0x84,0xF8, ++0x32,0x00,0xE8,0x88,0xA0,0x86,0x20,0x8B, ++0x20,0xF4,0x00,0x50,0x20,0x83,0x20,0x8B, ++0xE9,0x88,0x08,0x43,0x20,0x83,0xFF,0xF7, ++0x52,0xFE,0x58,0xB9,0x94,0xF8,0x31,0x00, ++0x58,0x28,0x05,0xD1,0x20,0x8B,0x80,0x04, ++0x02,0xD4,0x01,0x20,0x84,0xF8,0x33,0x00, ++0x00,0x20,0x70,0xBD,0xFE,0xF7,0xB8,0xF8, ++0x08,0x35,0x28,0x68,0x00,0x28,0xDA,0xD1, ++0xE2,0x48,0x70,0xBD,0xB1,0xF5,0x80,0x6F, ++0x04,0xDC,0x00,0x20,0x00,0xE0,0x40,0x1C, ++0x88,0x42,0xFC,0xDB,0x70,0x47,0x41,0x7B, ++0x02,0x7B,0x10,0x30,0x42,0xEA,0x01,0x21, ++0xF0,0xE7,0x00,0x22,0x02,0xE0,0x10,0xF8, ++0x01,0x3B,0x1A,0x44,0x0B,0x00,0xA1,0xF1, ++0x01,0x01,0x89,0xB2,0xF7,0xD1,0x10,0x46, ++0x70,0x47,0xF8,0xB5,0x06,0x46,0xFD,0xF7, ++0x73,0xFF,0x04,0x46,0x01,0x23,0xD0,0xE9, ++0x21,0x05,0x00,0x21,0x00,0x93,0x03,0x46, ++0x30,0x46,0x2A,0x46,0xFE,0xF7,0x70,0xF8, ++0x00,0x28,0x0C,0xD1,0x28,0x1D,0x4F,0xF4, ++0xFE,0x71,0xFF,0xF7,0xDE,0xFF,0x06,0x46, ++0x28,0x46,0x04,0xF0,0xCA,0xE8,0xB0,0x42, ++0x02,0xD0,0xC6,0x48,0x34,0x38,0xF8,0xBD, ++0x68,0x7B,0x29,0x7B,0x41,0xEA,0x00,0x22, ++0xE8,0x7B,0xA9,0x7B,0x41,0xEA,0x00,0x20, ++0x29,0x46,0x42,0x43,0xD4,0xF8,0x98,0x00, ++0x10,0x32,0x03,0xF0,0x72,0xEF,0x28,0x46, ++0xFF,0xF7,0xBD,0xFF,0x00,0x20,0xF8,0xBD, ++0x00,0x21,0x49,0x1C,0x10,0x29,0xFC,0xDB, ++0x00,0x7C,0x00,0x21,0x00,0xE0,0x49,0x1C, ++0x88,0x42,0xFC,0xDC,0x70,0x47,0x00,0x21, ++0xB5,0xA2,0x10,0xB5,0x43,0x5C,0x54,0x5C, ++0xA3,0x42,0x01,0xD0,0x01,0x20,0x10,0xBD, ++0x49,0x1C,0x10,0x29,0xF6,0xDB,0x00,0x20, ++0x10,0xBD,0x2D,0xE9,0xF0,0x4F,0x87,0xB0, ++0xFD,0xF7,0x26,0xFF,0xD0,0xF8,0x88,0x50, ++0x04,0x46,0x4F,0xF0,0x00,0x08,0x4F,0xF0, ++0x68,0x0A,0x05,0x95,0x4F,0xF0,0x54,0x0B, ++0xD0,0xF8,0x84,0x00,0x04,0x90,0x03,0x90, ++0x05,0x20,0xFF,0x21,0x01,0x90,0xA1,0x74, ++0x00,0x27,0x01,0x99,0x08,0xFA,0x01,0xF9, ++0x4F,0xF4,0x80,0x60,0x9E,0x49,0xE0,0x86, ++0x20,0x20,0x20,0x87,0x07,0xEB,0x47,0x00, ++0x30,0x31,0x31,0xF8,0x10,0x20,0x01,0xEB, ++0x40,0x00,0x62,0x87,0x41,0x88,0xA1,0x87, ++0x80,0x88,0xE0,0x87,0xFE,0xF7,0x2D,0xF9, ++0xFE,0xF7,0xB8,0xFC,0x20,0x8B,0x40,0xF4, ++0x80,0x50,0x20,0x83,0x94,0xF8,0x33,0x00, ++0x20,0xB1,0x58,0x20,0x84,0xF8,0x31,0x00, ++0x44,0x20,0x48,0xE0,0x01,0x23,0x00,0x21, ++0x00,0x93,0x48,0x46,0xDD,0xE9,0x04,0x32, ++0xFD,0xF7,0xEE,0xFF,0x06,0x00,0x1D,0xD0, ++0x60,0x8C,0x80,0x07,0x30,0xD1,0x94,0xF8, ++0x30,0x00,0x30,0xB9,0x01,0x20,0x84,0xF8, ++0x30,0x00,0xA0,0x8B,0x40,0xF4,0x00,0x40, ++0x05,0xE0,0x00,0x20,0x84,0xF8,0x30,0x00, ++0xA0,0x8B,0x20,0xF4,0x00,0x40,0xA0,0x83, ++0x01,0x23,0x00,0x93,0x00,0x21,0xDD,0xE9, ++0x04,0x32,0x48,0x46,0xFD,0xF7,0xD0,0xFF, ++0x06,0x00,0x15,0xD1,0x03,0x98,0x00,0x78, ++0xFF,0x28,0x11,0xD1,0x28,0x46,0xFF,0xF7, ++0x86,0xFF,0x68,0xB9,0x05,0x98,0x0E,0x21, ++0x24,0x30,0xFF,0xF7,0x36,0xFF,0x02,0x90, ++0x05,0xF1,0x20,0x00,0x04,0xF0,0x20,0xE8, ++0x01,0x46,0x02,0x98,0x81,0x42,0x0D,0xD0, ++0x94,0xF8,0x33,0x00,0x01,0x28,0x77,0xD1, ++0x94,0xF8,0x31,0x00,0x68,0x28,0x73,0xD0, ++0x58,0x46,0x84,0xF8,0x31,0xA0,0x84,0xF8, ++0x32,0x00,0xB3,0xE7,0x28,0x46,0xFF,0xF7, ++0x5B,0xFF,0x12,0x35,0x68,0x7D,0x29,0x7D, ++0x41,0xEA,0x00,0x20,0x60,0x87,0xE8,0x7C, ++0xA9,0x7C,0x41,0xEA,0x00,0x20,0xA0,0x87, ++0xE8,0x7D,0xA9,0x7D,0x41,0xEA,0x00,0x20, ++0x20,0x87,0x68,0x7E,0x29,0x7E,0x41,0xEA, ++0x00,0x20,0xE0,0x86,0xE8,0x7F,0xA9,0x7F, ++0x41,0xEA,0x00,0x20,0xE0,0x87,0x15,0xF8, ++0x02,0x0C,0x12,0x3D,0x60,0x74,0x05,0xF1, ++0x2C,0x00,0x06,0x90,0x03,0xF0,0xE8,0xEF, ++0x20,0x64,0x10,0x22,0x95,0xF8,0x33,0x00, ++0x95,0xF8,0x32,0x10,0x41,0xEA,0x00,0x20, ++0x05,0xF1,0x40,0x01,0xA4,0xF8,0x44,0x00, ++0x04,0xF1,0x46,0x00,0x03,0xF0,0x94,0xEE, ++0x10,0x22,0x05,0xF1,0x50,0x01,0x04,0xF1, ++0x56,0x00,0x03,0xF0,0x8E,0xEE,0x06,0x98, ++0x03,0xF0,0xCE,0xEF,0x00,0xF0,0x01,0x00, ++0x04,0xF8,0x80,0x0F,0x95,0xF8,0x60,0x00, ++0x60,0x70,0xFE,0xF7,0x8A,0xF8,0xFE,0xF7, ++0x15,0xFC,0x14,0xF8,0x80,0x09,0x00,0xBB, ++0x48,0x49,0x05,0xE0,0x01,0xEB,0x80,0x02, ++0x21,0xF8,0x20,0x00,0x50,0x80,0x40,0x1C, ++0x22,0x8F,0x82,0x42,0xF6,0xD8,0x9E,0xB9, ++0x42,0x48,0x80,0x88,0x00,0xEB,0x09,0x06, ++0x30,0x46,0xFF,0xF7,0xCA,0xFE,0x58,0xB9, ++0x94,0xF8,0x70,0x00,0xC6,0x40,0xA6,0x74, ++0xB4,0xF8,0x44,0x00,0xFD,0xF7,0xBD,0xFE, ++0x00,0x20,0x07,0xB0,0xBD,0xE8,0xF0,0x8F, ++0x10,0xE0,0x94,0xF8,0x81,0x10,0x01,0x23, ++0x01,0xEB,0x09,0x00,0xDD,0xE9,0x04,0x21, ++0xFD,0xF7,0x21,0xFF,0x30,0xB9,0x33,0x48, ++0x4F,0xF4,0x00,0x62,0x05,0x99,0x03,0xF0, ++0x4C,0xEE,0xD9,0xE7,0x7F,0x1C,0xFF,0xB2, ++0x02,0x2F,0xFF,0xF4,0x0D,0xAF,0x08,0xF1, ++0x01,0x00,0x1F,0xFA,0x80,0xF8,0xB8,0xF1, ++0x40,0x0F,0xFF,0xF4,0x01,0xAF,0x23,0x48, ++0x11,0x38,0xDA,0xE7,0x10,0xB5,0x04,0x46, ++0xFD,0xF7,0x0E,0xFE,0x90,0xF8,0x70,0x00, ++0x04,0xFA,0x00,0xF0,0xBD,0xE8,0x10,0x40, ++0xFF,0xF7,0xFC,0xBC,0x70,0xB5,0x06,0x46, ++0xA0,0xB0,0xFD,0xF7,0x01,0xFE,0xD0,0xF8, ++0x88,0x50,0x04,0x46,0x30,0x46,0xFF,0xF7, ++0xE9,0xFF,0x80,0x21,0x68,0x46,0x03,0xF0, ++0xAC,0xEE,0x94,0xF8,0x70,0x00,0x01,0x23, ++0x6A,0x46,0x29,0x46,0x86,0x40,0x30,0x46, ++0xFD,0xF7,0xDE,0xFE,0x20,0x8F,0x76,0x1E, ++0x01,0x23,0x6A,0x46,0x30,0x44,0x29,0x46, ++0xFD,0xF7,0xD6,0xFE,0x20,0xB0,0x70,0xBD, ++0x2D,0xE9,0xFC,0x5F,0x80,0x46,0xFD,0xF7, ++0xDF,0xFD,0x81,0x46,0xD0,0xF8,0x88,0x00, ++0x00,0x25,0x01,0x90,0xD9,0xF8,0x40,0x00, ++0xD9,0xF8,0x84,0x40,0xC0,0xF3,0x42,0x06, ++0xC0,0xF3,0xC0,0x1A,0x73,0xE0,0x00,0x00, ++0x48,0xEC,0x03,0x20,0x3A,0x00,0x00,0x80, ++0x4D,0x53,0x54,0x41,0x52,0x53,0x45,0x4D, ++0x49,0x55,0x4E,0x46,0x44,0x43,0x49,0x53, ++0x00,0x00,0x00,0x00,0x00,0x0D,0x03,0x20, ++0x4F,0xF0,0x00,0x0B,0x5F,0x46,0x99,0xF8, ++0x70,0x00,0x01,0x23,0x01,0x9A,0x00,0x93, ++0x00,0x21,0x05,0xFA,0x00,0xF0,0x23,0x46, ++0x38,0x44,0xFD,0xF7,0xB9,0xFE,0xBA,0xF1, ++0x00,0x0F,0x01,0xD1,0xA0,0x5D,0x06,0xE0, ++0x14,0xF8,0x16,0x00,0xFF,0x28,0x25,0xD1, ++0x04,0xEB,0x46,0x00,0x40,0x78,0xFF,0x28, ++0x20,0xD1,0x99,0xF8,0x70,0x10,0x68,0x1C, ++0x01,0x23,0x01,0x9A,0x88,0x40,0x00,0x93, ++0xC0,0x1B,0x00,0x21,0x40,0x1E,0x23,0x46, ++0xFD,0xF7,0x9E,0xFE,0xBA,0xF1,0x00,0x0F, ++0x01,0xD1,0xA0,0x5D,0x06,0xE0,0x14,0xF8, ++0x16,0x00,0xFF,0x28,0x0A,0xD1,0x04,0xEB, ++0x46,0x00,0x40,0x78,0xFF,0x28,0x05,0xD1, ++0x7F,0x1C,0x03,0x2F,0xC7,0xD3,0xBB,0xF1, ++0x01,0x0F,0x23,0xD1,0x98,0xF8,0x05,0x10, ++0x98,0xF8,0x04,0x20,0x42,0xEA,0x01,0x20, ++0xFA,0x28,0x0C,0xD8,0x08,0xEB,0x40,0x00, ++0x29,0x0A,0x85,0x71,0x98,0xF8,0x05,0x20, ++0x98,0xF8,0x04,0x30,0x43,0xEA,0x02,0x20, ++0x08,0xEB,0x40,0x00,0xC1,0x71,0x98,0xF8, ++0x05,0x10,0x98,0xF8,0x04,0x20,0x42,0xEA, ++0x01,0x20,0x40,0x1C,0x88,0xF8,0x04,0x00, ++0x00,0x0A,0x88,0xF8,0x05,0x00,0xA8,0xB2, ++0xFF,0xF7,0x58,0xFF,0x6D,0x1C,0xB9,0xF8, ++0x36,0x00,0xA8,0x42,0x98,0xD8,0x4F,0xF4, ++0xFE,0x71,0x08,0xF1,0x04,0x00,0xFF,0xF7, ++0xD0,0xFD,0x41,0x46,0x03,0xF0,0xCC,0xEE, ++0x00,0x20,0xBD,0xE8,0xFC,0x9F,0xFF,0x49, ++0x40,0x1E,0x01,0x42,0x01,0xD0,0xFE,0x48, ++0x70,0x47,0x00,0x20,0x70,0x47,0x00,0x22, ++0x08,0xE0,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x10,0x32,0x8A,0x42,0xF4,0xDB, ++0x70,0x47,0x70,0x47,0x70,0x47,0x00,0x21, ++0x02,0xE0,0x49,0x1C,0x40,0x08,0xC9,0xB2, ++0x00,0x28,0xFA,0xD1,0x49,0x1E,0xC8,0xB2, ++0x70,0x47,0x70,0xB5,0x04,0x46,0x0D,0x46, ++0xFD,0xF7,0x26,0xFD,0xD0,0xF8,0x98,0x00, ++0x41,0x7B,0x02,0x7B,0x42,0xEA,0x01,0x21, ++0x08,0xE0,0x62,0x79,0x23,0x79,0x43,0xEA, ++0x02,0x22,0xAA,0x42,0x01,0xD1,0x20,0x46, ++0x70,0xBD,0x08,0x34,0x22,0x1A,0x10,0x3A, ++0xB1,0xEB,0xE2,0x0F,0xF1,0xDC,0x00,0x20, ++0x70,0xBD,0x38,0xB5,0x05,0x46,0xFD,0xF7, ++0x0B,0xFD,0x70,0x30,0x01,0x23,0x01,0x78, ++0xD0,0xE9,0x05,0x42,0x05,0xFA,0x01,0xF0, ++0x00,0x93,0x00,0x21,0x23,0x46,0xFD,0xF7, ++0x07,0xFE,0x20,0x78,0xFF,0x28,0x01,0xD0, ++0x00,0x20,0x38,0xBD,0x01,0x20,0x38,0xBD, ++0x00,0x22,0x05,0xE0,0x83,0x5C,0xFF,0x2B, ++0x01,0xD0,0x00,0x20,0x70,0x47,0x52,0x1C, ++0x8A,0x42,0xF7,0xD3,0xFF,0x20,0x70,0x47, ++0xF8,0xB5,0x05,0x46,0xFD,0xF7,0xE8,0xFC, ++0x90,0xF8,0x70,0x10,0x01,0x23,0xD0,0xE9, ++0x21,0x76,0x04,0x46,0x05,0xFA,0x01,0xF0, ++0x00,0x93,0x00,0x21,0x3B,0x46,0x32,0x46, ++0xFD,0xF7,0xE2,0xFD,0xC0,0xB9,0xB4,0xF8, ++0x6C,0x10,0x38,0x46,0xFF,0xF7,0xDC,0xFF, ++0xFF,0x28,0x11,0xD1,0x6C,0x34,0x68,0x1C, ++0x01,0x23,0x21,0x79,0x32,0x46,0x00,0x93, ++0x3B,0x46,0x88,0x40,0x00,0x21,0x40,0x1E, ++0xFD,0xF7,0xCE,0xFD,0x21,0x88,0x38,0x46, ++0xFF,0xF7,0xCA,0xFF,0xFF,0x28,0x01,0xD0, ++0x00,0x20,0xF8,0xBD,0x01,0x20,0xF8,0xBD, ++0x2D,0xE9,0xF8,0x4F,0x80,0x46,0xFD,0xF7, ++0xB7,0xFC,0xD0,0xE9,0x21,0xA9,0x05,0x46, ++0x90,0xF8,0x70,0x00,0x00,0x21,0x0E,0x46, ++0x08,0xFA,0x00,0xF2,0x28,0x8F,0x02,0xEB, ++0x50,0x04,0x1E,0xE0,0x01,0x23,0x00,0x21, ++0x00,0x93,0x53,0x46,0x4A,0x46,0x20,0x46, ++0xFD,0xF7,0xAA,0xFD,0xB5,0xF8,0x6C,0x10, ++0x07,0x46,0x50,0x46,0xFF,0xF7,0xA4,0xFF, ++0xFF,0x28,0x07,0xD1,0x37,0xB9,0x28,0x8F, ++0xB2,0x1C,0x4F,0xF0,0xFF,0x31,0xD0,0x40, ++0x24,0x1A,0x04,0xE0,0x28,0x8F,0xB2,0x1C, ++0x01,0x21,0xD0,0x40,0x04,0x44,0x76,0x1C, ++0xF6,0xB2,0x95,0xF8,0x70,0x00,0x40,0x1E, ++0xB0,0x42,0xDB,0xDC,0x95,0xF8,0x70,0x00, ++0x00,0x29,0x47,0x46,0x18,0xDA,0x87,0x40, ++0x01,0x23,0x00,0x93,0x00,0x21,0x53,0x46, ++0x4A,0x46,0x20,0x46,0xFD,0xF7,0x80,0xFD, ++0xB5,0xF8,0x6C,0x10,0x06,0x46,0x50,0x46, ++0xFF,0xF7,0x7A,0xFF,0xFF,0x28,0x03,0xD1, ++0x16,0xB9,0x64,0x1E,0xBC,0x42,0xEB,0xD2, ++0xB5,0xF8,0x76,0x00,0x64,0x1C,0x14,0xE0, ++0x7F,0x1C,0x87,0x40,0x01,0x23,0x00,0x93, ++0x00,0x21,0x53,0x46,0x4A,0x46,0x20,0x46, ++0xFD,0xF7,0x66,0xFD,0xB5,0xF8,0x6C,0x10, ++0x06,0x46,0x50,0x46,0xFF,0xF7,0x60,0xFF, ++0xFF,0x28,0x06,0xD1,0x2E,0xB9,0xB5,0xF8, ++0x76,0x00,0x20,0x40,0xC0,0xB2,0xBD,0xE8, ++0xF8,0x8F,0x64,0x1C,0xBC,0x42,0xE5,0xD3, ++0x4F,0xF6,0xFF,0x70,0xF7,0xE7,0x2D,0xE9, ++0xF0,0x5F,0x83,0x46,0x0C,0x46,0x90,0x46, ++0xFD,0xF7,0x42,0xFC,0x70,0x30,0xD0,0xE9, ++0x05,0x9A,0x00,0x78,0x84,0x40,0x0B,0xFA, ++0x00,0xF1,0xA6,0xB2,0x8F,0xB2,0x00,0x24, ++0x17,0xE0,0x30,0x19,0x01,0x23,0x4A,0x46, ++0x51,0x46,0xFD,0xF7,0x28,0xFD,0x00,0x28, ++0x0B,0xD1,0x38,0x19,0x01,0x23,0x4A,0x46, ++0x51,0x46,0xFD,0xF7,0x19,0xFD,0x05,0x00, ++0x05,0xD0,0x58,0x46,0xFF,0xF7,0x1E,0xFE, ++0x28,0x46,0xBD,0xE8,0xF0,0x9F,0x64,0x1C, ++0xA4,0xB2,0x44,0x45,0xE5,0xD3,0x00,0x20, ++0xF7,0xE7,0x2D,0xE9,0xF8,0x4F,0x81,0x46, ++0x93,0x46,0xDD,0xE9,0x0A,0x45,0xFD,0xF7, ++0x13,0xFC,0x06,0x46,0xD0,0xF8,0x88,0x00, ++0x00,0x90,0x70,0x8F,0x4F,0xEA,0x50,0x2A, ++0x50,0x46,0xFF,0xF7,0xD4,0xFE,0x01,0x21, ++0x07,0x46,0x81,0x40,0x49,0x1E,0x89,0xB2, ++0x04,0xEA,0x01,0x00,0x5F,0xEA,0x00,0x08, ++0x26,0xD0,0x96,0xF8,0x70,0x10,0x59,0x4A, ++0x01,0x23,0x0B,0xFA,0x01,0xF0,0x24,0xFA, ++0x07,0xF1,0x32,0xF8,0x21,0x10,0x00,0x22, ++0x08,0x44,0x00,0x99,0xFD,0xF7,0xE7,0xFC, ++0x00,0x28,0x9C,0xD1,0xAA,0xEB,0x08,0x02, ++0xAA,0x42,0x40,0x46,0x29,0x46,0x00,0xD2, ++0x11,0x46,0x1F,0xFA,0x81,0xF8,0x00,0x99, ++0x4F,0xEA,0x48,0x22,0x01,0xEB,0x40,0x21, ++0x48,0x46,0x03,0xF0,0x06,0xEC,0x09,0xEB, ++0x48,0x29,0x44,0x44,0xA5,0xEB,0x08,0x05, ++0x96,0xF8,0x70,0x00,0x45,0x49,0x0B,0xFA, ++0x00,0xF2,0x24,0xFA,0x07,0xF0,0x31,0xF8, ++0x20,0x00,0x10,0x44,0x25,0xFA,0x07,0xF2, ++0x1F,0xFA,0x82,0xF8,0x19,0xE0,0x01,0x23, ++0x00,0x22,0x49,0x46,0xFD,0xF7,0xBB,0xFC, ++0x00,0x28,0x2C,0xD1,0x70,0x8F,0x54,0x44, ++0x3A,0x4A,0x81,0x44,0xA8,0xF1,0x01,0x00, ++0xA5,0xEB,0x0A,0x05,0x1F,0xFA,0x80,0xF8, ++0x96,0xF8,0x70,0x00,0x0B,0xFA,0x00,0xF1, ++0x24,0xFA,0x07,0xF0,0x32,0xF8,0x20,0x00, ++0x08,0x44,0xB8,0xF1,0x00,0x0F,0xE2,0xD1, ++0xA5,0xB1,0x96,0xF8,0x70,0x10,0x01,0x23, ++0x00,0x22,0x0B,0xFA,0x01,0xF0,0x2D,0x49, ++0xFC,0x40,0x31,0xF8,0x24,0x10,0x08,0x44, ++0x00,0x99,0xFD,0xF7,0x94,0xFC,0x00,0x28, ++0x05,0xD1,0x00,0x99,0x6A,0x02,0x48,0x46, ++0x03,0xF0,0xBE,0xEB,0x00,0x20,0x42,0xE7, ++0x2D,0xE9,0xFF,0x4F,0x83,0x46,0x83,0xB0, ++0xDD,0xE9,0x10,0x56,0xFD,0xF7,0x8C,0xFB, ++0x04,0x46,0xD0,0xF8,0x88,0x00,0x02,0x90, ++0xD4,0xF8,0x84,0x00,0x01,0x90,0x60,0x8F, ++0x4F,0xEA,0x50,0x29,0x48,0x46,0xFF,0xF7, ++0x4A,0xFE,0xA1,0x8F,0x82,0x46,0x01,0x98, ++0xFF,0x22,0x03,0xF0,0x9A,0xEB,0x94,0xF8, ++0x70,0x00,0x05,0x9A,0x15,0x49,0x82,0x40, ++0x25,0xFA,0x0A,0xF0,0x31,0xF8,0x20,0x00, ++0x02,0xEB,0x00,0x08,0x26,0xFA,0x0A,0xF0, ++0x87,0xB2,0x19,0xE0,0x01,0x9A,0x01,0x23, ++0x59,0x46,0x40,0x46,0xFD,0xF7,0x54,0xFC, ++0x00,0x28,0x2E,0xD1,0x60,0x8F,0x94,0xF8, ++0x70,0x10,0x7F,0x1E,0x83,0x44,0x05,0x98, ++0x4D,0x44,0x08,0x4A,0xBF,0xB2,0x88,0x40, ++0xA6,0xEB,0x09,0x06,0x25,0xFA,0x0A,0xF1, ++0x32,0xF8,0x21,0x10,0x00,0xEB,0x01,0x08, ++0x00,0x2F,0x05,0xE0,0x00,0x15,0x03,0x20, ++0x48,0x00,0x00,0x80,0x00,0x0D,0x03,0x20, ++0xDC,0xD1,0x8E,0xB1,0x61,0x8F,0xFF,0x22, ++0x02,0x98,0x03,0xF0,0x62,0xEB,0x02,0x98, ++0x72,0x02,0x59,0x46,0x03,0xF0,0x64,0xEB, ++0xDD,0xE9,0x01,0x21,0x01,0x23,0x40,0x46, ++0xFD,0xF7,0x26,0xFC,0x00,0x28,0x00,0xD1, ++0x00,0x20,0xFA,0xE4,0x2D,0xE9,0xFF,0x4F, ++0x0E,0x46,0x85,0xB0,0x17,0x46,0x99,0x46, ++0xDD,0xF8,0x48,0xA0,0xFD,0xF7,0x28,0xFB, ++0x04,0x46,0xD0,0xE9,0x21,0x05,0x03,0x90, ++0x94,0xF8,0x80,0x00,0xB4,0xF8,0x38,0x80, ++0x01,0x28,0x01,0xD1,0x4F,0xEA,0x58,0x08, ++0x60,0x8F,0x40,0x0A,0xFF,0xF7,0xE3,0xFD, ++0x01,0x21,0x83,0x46,0x81,0x40,0x49,0x1E, ++0x89,0xB2,0x1A,0xEA,0x01,0x00,0x04,0x90, ++0x2F,0xD1,0x56,0x4A,0x2A,0xFA,0x0B,0xF1, ++0x94,0xF8,0x70,0x00,0x01,0x23,0x32,0xF8, ++0x21,0x10,0x07,0xFA,0x00,0xF0,0x03,0x9A, ++0x08,0x44,0x29,0x46,0xFD,0xF7,0xF7,0xFB, ++0x00,0x28,0x1C,0xD1,0xA1,0x8F,0x05,0xE0, ++0x03,0x9A,0x12,0x5C,0xFF,0x2A,0x18,0xD1, ++0x40,0x1C,0x80,0xB2,0x81,0x42,0xF7,0xD8, ++0x61,0x8F,0x00,0x20,0x04,0xE0,0x2A,0x5C, ++0xFF,0x2A,0x0E,0xD1,0x40,0x1C,0x80,0xB2, ++0x81,0x42,0xF8,0xD8,0x13,0x9B,0x3A,0x46, ++0x31,0x46,0xCD,0xE9,0x00,0xA3,0x4B,0x46, ++0x05,0x98,0xFF,0xF7,0x4D,0xFF,0x09,0xB0, ++0xA8,0xE4,0x3F,0x4E,0x2A,0xFA,0x0B,0xF9, ++0x04,0x98,0x08,0xB1,0x09,0xF1,0x01,0x09, ++0x00,0x25,0x14,0xE0,0x39,0x49,0x01,0x23, ++0x94,0xF8,0x70,0x00,0x00,0x22,0x31,0xF8, ++0x25,0x10,0x07,0xFA,0x00,0xF0,0x08,0x44, ++0x94,0xF8,0x72,0x10,0x05,0xFA,0x01,0xF1, ++0x31,0x44,0xFD,0xF7,0xBC,0xFB,0x00,0x28, ++0xE1,0xD1,0x6D,0x1C,0xAD,0xB2,0x4D,0x45, ++0xE8,0xD3,0x13,0x99,0xDF,0xF8,0xB4,0x90, ++0x0A,0xEB,0x01,0x00,0x20,0xFA,0x0B,0xF0, ++0x85,0xB2,0x13,0xE0,0x94,0xF8,0x70,0x00, ++0x01,0x23,0x39,0xF8,0x25,0x10,0x00,0x22, ++0x07,0xFA,0x00,0xF0,0x08,0x44,0x94,0xF8, ++0x72,0x10,0x05,0xFA,0x01,0xF1,0x31,0x44, ++0xFD,0xF7,0x9D,0xFB,0x00,0x28,0xC2,0xD1, ++0x6D,0x1C,0xAD,0xB2,0x45,0x45,0xE9,0xD3, ++0x13,0x98,0x05,0x99,0x42,0x02,0x06,0xEB, ++0x4A,0x20,0x03,0xF0,0xC2,0xEA,0x38,0x46, ++0xFF,0xF7,0x84,0xFC,0x05,0x00,0x04,0xD0, ++0x38,0x46,0xFF,0xF7,0x8B,0xFC,0x28,0x46, ++0xAD,0xE7,0xA1,0x8F,0xFF,0x22,0x03,0x98, ++0x03,0xF0,0xAA,0xEA,0x00,0x25,0xCA,0x46, ++0x19,0xE0,0x94,0xF8,0x70,0x00,0x01,0x23, ++0x3A,0xF8,0x25,0x10,0x03,0x9A,0x07,0xFA, ++0x00,0xF0,0x08,0x44,0x94,0xF8,0x72,0x10, ++0x05,0xFA,0x01,0xF1,0x31,0x44,0xFD,0xF7, ++0x67,0xFB,0x5F,0xEA,0x00,0x09,0x04,0xD0, ++0x38,0x46,0xFF,0xF7,0x6B,0xFC,0x48,0x46, ++0x8D,0xE7,0x6D,0x1C,0xAD,0xB2,0x45,0x45, ++0xE3,0xD3,0x00,0x20,0x87,0xE7,0x01,0x23, ++0xFD,0xF7,0x5D,0xBB,0x01,0x23,0xFD,0xF7, ++0x53,0xBB,0x00,0x00,0x00,0x0D,0x03,0x20, ++0x00,0x00,0x20,0x80,0x10,0xB5,0x04,0x46, ++0xF8,0xF7,0xC0,0xFA,0x20,0x46,0x10,0xBD, ++0x00,0x20,0x70,0x47,0x00,0x20,0x70,0x47, ++0xB7,0x48,0x40,0x68,0x00,0xF4,0x40,0x70, ++0xB0,0xF5,0x80,0x7F,0x06,0xD0,0xB0,0xF5, ++0x00,0x7F,0x03,0xD0,0xB0,0xF5,0x40,0x7F, ++0x00,0xD0,0xFE,0xE7,0x00,0x20,0x80,0x1C, ++0xC0,0xB2,0x08,0x28,0xFB,0xD3,0x70,0x47, ++0xDF,0xF8,0xB8,0xC2,0xF0,0xB5,0xDC,0xF8, ++0x08,0x10,0x81,0x42,0x01,0xD1,0x00,0x20, ++0xF0,0xBD,0xA9,0x4B,0x01,0x28,0xAA,0x4A, ++0xAA,0x4C,0x59,0x68,0x21,0xF4,0x40,0x71, ++0x59,0x60,0x15,0xD0,0x02,0x28,0x25,0xD0, ++0x03,0x28,0x59,0xD1,0x32,0xF8,0xBC,0x5F, ++0x25,0xF4,0x00,0x75,0x15,0x80,0x15,0x88, ++0x45,0xF4,0xE8,0x55,0x15,0x80,0xB4,0xF8, ++0x80,0x20,0x42,0xF0,0x02,0x02,0xA4,0xF8, ++0x80,0x20,0x41,0xF4,0x40,0x71,0x22,0xE0, ++0x32,0xF8,0xBC,0x5F,0x25,0xF4,0xF8,0x55, ++0x15,0x80,0x15,0x88,0x45,0xF4,0x40,0x75, ++0x15,0x80,0xB4,0xF8,0x80,0x20,0x22,0xF0, ++0x02,0x02,0xA4,0xF8,0x80,0x20,0x41,0xF4, ++0x80,0x71,0x10,0xE0,0x32,0xF8,0xBC,0x5F, ++0x25,0xF4,0xF8,0x55,0x15,0x80,0x15,0x88, ++0x45,0xF4,0x80,0x75,0x15,0x80,0xB4,0xF8, ++0x80,0x20,0x22,0xF0,0x02,0x02,0xA4,0xF8, ++0x80,0x20,0x41,0xF4,0x00,0x71,0x59,0x60, ++0x34,0xF8,0xD0,0x1F,0x41,0xF0,0x02,0x01, ++0x21,0x80,0x89,0x49,0x0A,0x88,0x22,0xF4, ++0x00,0x42,0x0A,0x80,0x87,0x4E,0xB1,0x88, ++0x41,0xF0,0xB2,0x01,0xB1,0x80,0xB1,0x88, ++0x21,0xF0,0x04,0x01,0xB1,0x80,0x31,0x88, ++0x43,0xF2,0x16,0x62,0x11,0x43,0x31,0x80, ++0x31,0x88,0x47,0xF6,0x5F,0x72,0x11,0x40, ++0x31,0x80,0x00,0x21,0x80,0x27,0xA6,0xF6, ++0xC8,0x56,0x4F,0xF0,0x34,0x0E,0x01,0xE0, ++0x7B,0x48,0xF0,0xBD,0x4A,0x08,0x06,0xEB, ++0x82,0x02,0xB2,0xF8,0xA8,0x4D,0xCB,0x07, ++0x00,0x2B,0x01,0xD0,0x4F,0xF0,0x08,0x03, ++0x0E,0xFA,0x03,0xF5,0x44,0xEA,0x05,0x04, ++0xA2,0xF8,0xA8,0x4D,0xB2,0xF8,0xA8,0x4D, ++0x02,0xD0,0x4F,0xF0,0x08,0x03,0x00,0xE0, ++0x00,0x23,0x07,0xFA,0x03,0xF3,0x9C,0x43, ++0xA2,0xF8,0xA8,0x4D,0x49,0x1C,0xC9,0xB2, ++0x08,0x29,0xDF,0xD3,0xCC,0xF8,0x08,0x00, ++0x71,0xE7,0x6A,0x48,0xB0,0xF8,0xB4,0x11, ++0x21,0xF0,0x02,0x01,0xA0,0xF8,0xB4,0x11, ++0x01,0x88,0x21,0xF0,0x02,0x01,0x20,0xF8, ++0x40,0x1B,0x01,0x88,0x21,0xF0,0x02,0x01, ++0x01,0x80,0x00,0x20,0x70,0x47,0x61,0x48, ++0xB0,0xF8,0xB4,0x11,0x41,0xF0,0x02,0x01, ++0xA0,0xF8,0xB4,0x11,0x01,0x88,0x41,0xF0, ++0x02,0x01,0x20,0xF8,0x40,0x1B,0x01,0x88, ++0x41,0xF0,0x02,0x01,0x01,0x80,0x00,0x20, ++0x70,0x47,0x10,0xB5,0x02,0x46,0xFF,0xF7, ++0xEA,0xFF,0x4F,0x48,0x0E,0x2A,0x42,0xD2, ++0xDF,0xE8,0x02,0xF0,0x0A,0x2C,0x2F,0x32, ++0x35,0x38,0x3B,0x3E,0x41,0x41,0x41,0x41, ++0x41,0x07,0x4F,0xF4,0x96,0x71,0x01,0xE0, ++0x42,0xF6,0xE0,0x61,0x00,0x23,0x01,0x64, ++0x4D,0x49,0x0B,0x80,0x0B,0x88,0x44,0xF2, ++0x40,0x04,0x23,0x43,0x0B,0x80,0x0B,0x88, ++0x42,0xEA,0x02,0x24,0x23,0x43,0x0B,0x80, ++0x80,0xF8,0x44,0x20,0xB1,0xF8,0x20,0x0C, ++0x20,0xF0,0x08,0x00,0xA1,0xF8,0x20,0x0C, ++0xB1,0xF8,0xCC,0x0C,0x40,0xF0,0x40,0x00, ++0xA1,0xF8,0xCC,0x0C,0xFF,0xF7,0xA9,0xFF, ++0x00,0x20,0x10,0xBD,0x4F,0xF4,0x96,0x41, ++0xDC,0xE7,0x45,0xF6,0xC0,0x51,0xD9,0xE7, ++0x46,0xF6,0x08,0x31,0xD6,0xE7,0x4F,0xF4, ++0xFA,0x41,0xD3,0xE7,0x4F,0xF4,0x16,0x41, ++0xD0,0xE7,0x4A,0xF2,0x68,0x61,0xCD,0xE7, ++0x4B,0xF6,0x80,0x31,0xCA,0xE7,0x32,0x48, ++0x10,0xBD,0x70,0x47,0x70,0x47,0x10,0xB5, ++0x04,0x46,0xF8,0xF7,0xEC,0xEE,0x20,0x46, ++0x10,0xBD,0x70,0x47,0x70,0x47,0x2F,0x48, ++0x26,0x49,0x00,0xB5,0x00,0x68,0xC8,0x60, ++0x00,0xF5,0x00,0x70,0x08,0x61,0x02,0x20, ++0xFF,0xF7,0xE6,0xFE,0x0D,0x20,0xFF,0xF7, ++0x9C,0xFF,0x00,0x20,0x00,0xBD,0x30,0xB4, ++0xA1,0xF5,0x40,0x41,0x03,0x39,0x02,0x9C, ++0x06,0xD0,0x04,0x29,0x03,0xD0,0x05,0x29, ++0x08,0xD1,0x79,0x32,0x00,0xE0,0xB9,0x32, ++0x59,0x02,0x01,0x2C,0x05,0xD1,0x30,0xBC, ++0xFB,0xF7,0xA9,0xB9,0x30,0xBC,0x00,0x20, ++0x70,0x47,0x30,0xBC,0xFB,0xF7,0x00,0xBA, ++0xA0,0xF5,0x40,0x40,0x03,0x38,0x06,0xD0, ++0x04,0x28,0x07,0xD0,0x05,0x28,0x09,0xD1, ++0x79,0x20,0xB8,0x21,0x04,0xE0,0x00,0x20, ++0x78,0x21,0x01,0xE0,0xB9,0x20,0xC0,0x21, ++0xFB,0xF7,0x12,0xB9,0x00,0x20,0x70,0x47, ++0x08,0x48,0x01,0x68,0xA1,0xF5,0x25,0x42, ++0x5A,0x3A,0x04,0xD1,0x40,0x68,0xA0,0xF5, ++0x90,0x51,0x89,0x39,0x02,0xD0,0x08,0x48, ++0x14,0x38,0x70,0x47,0x00,0x20,0x70,0x47, ++0x20,0x15,0x03,0x20,0x74,0x05,0x03,0x20, ++0x00,0x50,0x00,0x25,0x00,0x70,0x00,0x25, ++0x14,0x2C,0x02,0x25,0xC8,0x0D,0x02,0x25, ++0x15,0x00,0x00,0x80,0x18,0x7C,0x00,0x25, ++0x40,0x72,0x00,0x25,0xAC,0x04,0x03,0x20, ++0x2D,0xE9,0xF0,0x41,0x00,0x24,0x06,0x46, ++0x0F,0x46,0x15,0x46,0x07,0xE0,0x01,0x20, ++0xFF,0xF7,0x68,0xFE,0x30,0x88,0x37,0xEA, ++0x00,0x00,0x02,0xD0,0x64,0x1C,0xAC,0x42, ++0xF5,0xD3,0xAC,0x42,0x02,0xD1,0xFD,0x48, ++0xBD,0xE8,0xF0,0x81,0x00,0x20,0xFB,0xE7, ++0xE6,0xE7,0xFB,0x48,0xFF,0x22,0x10,0xB5, ++0x00,0x24,0xC8,0x21,0x03,0xF0,0xD0,0xE8, ++0xF7,0x4B,0x00,0x20,0xF7,0x49,0x31,0xF8, ++0xC0,0x2F,0x22,0xF4,0xE0,0x62,0x0A,0x80, ++0x0A,0x88,0x42,0xEA,0x00,0x22,0x0A,0x80, ++0x0A,0x88,0x23,0xF8,0x14,0x20,0x64,0x1C, ++0xA2,0xB2,0x8C,0x88,0x40,0x1C,0x23,0xF8, ++0x12,0x40,0x52,0x1C,0x80,0xB2,0x94,0xB2, ++0xC0,0x39,0x08,0x28,0xE7,0xD3,0x00,0x20, ++0xC6,0x31,0xCA,0x8F,0x22,0xF4,0xE0,0x42, ++0xCA,0x87,0xCA,0x8F,0x42,0xEA,0x00,0x32, ++0xCA,0x87,0x31,0xF8,0x06,0x2C,0x23,0xF8, ++0x14,0x20,0x64,0x1C,0xA2,0xB2,0xCC,0x8F, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x31,0xF8, ++0x02,0x4C,0x92,0xB2,0x40,0x1C,0xC6,0x39, ++0x23,0xF8,0x12,0x40,0x52,0x1C,0x80,0xB2, ++0x94,0xB2,0x08,0x28,0xE0,0xD3,0x10,0xBD, ++0xDA,0x4B,0x00,0x20,0x10,0xB5,0x07,0xE0, ++0x03,0xEB,0x80,0x04,0xB4,0xF8,0x00,0x42, ++0x22,0xF8,0x10,0x40,0x40,0x1C,0x80,0xB2, ++0x88,0x42,0xF5,0xD3,0x10,0xBD,0xD3,0x49, ++0x00,0x20,0x00,0xB5,0x31,0xF8,0x20,0x20, ++0x40,0x1C,0x80,0xB2,0x60,0x28,0xF9,0xD3, ++0x20,0x21,0xCD,0x4A,0x00,0x20,0xC8,0x32, ++0xFF,0xF7,0xE2,0xFF,0x00,0x20,0x40,0x1C, ++0x80,0xB2,0x20,0x28,0xFB,0xD3,0x00,0xBD, ++0xC8,0x49,0x08,0x89,0x40,0xF0,0x10,0x00, ++0x08,0x81,0x4C,0xF6,0x07,0x02,0x0A,0x80, ++0x08,0x88,0x10,0x42,0xFB,0xD1,0xB1,0xF8, ++0x48,0x00,0x40,0xF0,0x1F,0x00,0xA1,0xF8, ++0x48,0x00,0x08,0x89,0x20,0xF0,0x10,0x00, ++0x08,0x81,0x70,0x47,0x3C,0xB5,0x45,0xF2, ++0x55,0x55,0xBC,0x4B,0x6C,0x46,0x6A,0x00, ++0x00,0x20,0x03,0xEB,0x80,0x01,0xA1,0xF8, ++0x00,0x52,0xB1,0xF8,0x00,0x12,0x24,0xF8, ++0x10,0x10,0x40,0x1C,0x80,0xB2,0x03,0x28, ++0xF3,0xD3,0x00,0x20,0x34,0xF8,0x10,0x10, ++0xA9,0x42,0x03,0xD1,0x40,0x1C,0x80,0xB2, ++0x03,0x28,0xF7,0xD3,0x03,0x28,0xE7,0xD1, ++0x00,0x20,0x03,0xEB,0x80,0x01,0xA1,0xF8, ++0x00,0x22,0xB1,0xF8,0x00,0x12,0x24,0xF8, ++0x10,0x10,0x40,0x1C,0x80,0xB2,0x03,0x28, ++0xF3,0xD3,0x00,0x20,0x34,0xF8,0x10,0x10, ++0x91,0x42,0x03,0xD1,0x40,0x1C,0x80,0xB2, ++0x03,0x28,0xF7,0xD3,0x03,0x28,0xE7,0xD1, ++0x3C,0xBD,0x2D,0xE9,0xF0,0x47,0x00,0x27, ++0xA0,0x48,0x01,0x89,0x41,0xF0,0x10,0x01, ++0x01,0x81,0x3D,0x46,0xDF,0xF8,0x78,0x82, ++0x81,0x46,0x45,0xF2,0x55,0x56,0xA9,0xF8, ++0x00,0x62,0xB9,0xF8,0x00,0x02,0x60,0xF3, ++0x0F,0x04,0xA0,0xB2,0xB0,0x42,0x05,0xD0, ++0x01,0x20,0xFF,0xF7,0x8B,0xFD,0x6D,0x1C, ++0x45,0x45,0xF0,0xD3,0x45,0x45,0xDF,0xF8, ++0x44,0xA2,0x0A,0xF1,0x0D,0x0A,0x15,0xD0, ++0xB9,0xF8,0xC0,0x10,0x21,0xF4,0x80,0x51, ++0xA9,0xF8,0xC0,0x10,0x00,0x25,0xB9,0xF8, ++0x00,0x02,0x60,0xF3,0x0F,0x04,0xA0,0xB2, ++0xB0,0x42,0x05,0xD1,0x01,0x20,0xFF,0xF7, ++0x71,0xFD,0x6D,0x1C,0x45,0x45,0xF2,0xD3, ++0x45,0x45,0x00,0xD1,0x57,0x46,0xB9,0xF8, ++0xC0,0x00,0x4C,0x46,0x40,0xF4,0x80,0x50, ++0xA9,0xF8,0xC0,0x00,0xFF,0xF7,0x86,0xFF, ++0x20,0x89,0x20,0xF0,0x10,0x00,0x20,0x81, ++0x38,0x46,0xBD,0xE8,0xF0,0x87,0x10,0xB5, ++0xFF,0xF7,0x1D,0xFE,0x7B,0x48,0x00,0x21, ++0x00,0x1D,0x01,0x80,0x4F,0xF4,0x00,0x42, ++0x82,0x80,0x02,0x22,0x82,0x84,0x05,0x22, ++0x82,0x86,0xA0,0xF8,0x40,0x10,0x81,0x87, ++0x4F,0xF4,0x02,0x42,0xA0,0xF8,0x68,0x20, ++0xA0,0xF8,0xD0,0x10,0xFF,0xF7,0x9D,0xFF, ++0x00,0x28,0x04,0xD1,0xFF,0xF7,0x4C,0xFF, ++0xFF,0xF7,0xEF,0xFD,0x00,0x20,0x10,0xBD, ++0x6E,0x48,0x10,0xB5,0x40,0x68,0xC0,0x06, ++0x07,0xD4,0xFA,0xF7,0xA8,0xFB,0xFF,0xF7, ++0x3B,0xFD,0xFF,0xF7,0x28,0xFF,0xFF,0xF7, ++0xD4,0xFE,0xBD,0xE8,0x10,0x40,0xCE,0xE7, ++0x64,0x4A,0xB0,0x32,0x13,0x88,0x23,0xF4, ++0x7C,0x53,0x13,0x80,0x13,0x88,0x43,0xEA, ++0x00,0x30,0x10,0x80,0x10,0x88,0x40,0xEA, ++0x01,0x20,0x10,0x80,0x70,0x47,0x70,0xB5, ++0x05,0x46,0x5E,0x4E,0x00,0xEB,0x40,0x00, ++0x84,0x19,0x14,0xF8,0x47,0x0F,0xFF,0xF7, ++0xE8,0xFD,0xA1,0x78,0x60,0x78,0xFF,0xF7, ++0xE3,0xFF,0x86,0xF8,0x46,0x50,0x70,0xBD, ++0x10,0xB5,0xFF,0xF7,0xAC,0xFF,0x55,0x48, ++0x81,0x8F,0x81,0xF0,0x40,0x01,0x81,0x87, ++0x41,0x68,0x09,0x07,0x04,0xD4,0xBD,0xE8, ++0x10,0x40,0x00,0x20,0xFF,0xF7,0xD1,0xBD, ++0x90,0xF8,0x45,0x00,0xBD,0xE8,0x10,0x40, ++0x40,0x1E,0xC0,0xB2,0xD7,0xE7,0x4B,0x49, ++0x00,0x20,0x91,0xF8,0x45,0x10,0x01,0xE0, ++0x40,0x1C,0x80,0xB2,0x81,0x42,0xFB,0xD8, ++0x70,0x47,0x46,0x48,0x41,0x7B,0x31,0xF0, ++0x02,0x01,0x01,0xD0,0x44,0x48,0x70,0x47, ++0x81,0x7B,0x11,0xF0,0xF9,0x0F,0x02,0xD0, ++0x41,0x48,0x40,0x1C,0x70,0x47,0xC1,0x7B, ++0x11,0xF0,0xA0,0x0F,0x02,0xD0,0x3E,0x48, ++0x80,0x1C,0x70,0x47,0x00,0x7C,0x00,0x06, ++0x02,0xD5,0x3B,0x48,0xC0,0x1C,0x70,0x47, ++0x00,0x20,0x70,0x47,0x2D,0xE9,0xF0,0x41, ++0x00,0x24,0x34,0x4F,0x34,0x4E,0xB7,0xF8, ++0x48,0x50,0x01,0x20,0xFF,0xF7,0xC2,0xFC, ++0xB7,0xF8,0x48,0x00,0xE9,0x05,0x01,0xD5, ++0xC0,0x05,0x02,0xD4,0x64,0x1C,0xB4,0x42, ++0xF1,0xD3,0xB4,0x42,0x02,0xD1,0x29,0x48, ++0xC0,0x1C,0x55,0xE6,0x00,0x20,0x53,0xE6, ++0x2D,0xE9,0xF0,0x41,0x0D,0x46,0x11,0x0E, ++0x26,0x4C,0x06,0x9F,0x43,0xEA,0x01,0x21, ++0x41,0xF0,0x40,0x01,0xA4,0xF8,0x00,0x12, ++0x02,0xF4,0x7F,0x41,0xC2,0xF3,0x07,0x46, ++0x31,0x43,0xA4,0xF8,0x04,0x12,0xD1,0xB2, ++0xA4,0xF8,0x08,0x12,0x07,0xF0,0x7F,0x01, ++0xA1,0x86,0xA4,0xF8,0x40,0x00,0x0C,0x2B, ++0x03,0xD0,0xFF,0xF7,0xC7,0xFF,0x00,0x28, ++0x0F,0xD1,0xA4,0xF8,0x44,0x50,0x19,0x48, ++0x40,0x68,0x40,0x07,0x03,0xD5,0xFF,0xF7, ++0xBD,0xFF,0x00,0x28,0x05,0xD1,0x20,0x46, ++0xBD,0xE8,0xF0,0x41,0x02,0x21,0x12,0x4A, ++0x0E,0xE6,0x21,0xE6,0x2D,0xE9,0xF0,0x41, ++0x0E,0x4F,0x39,0x89,0x01,0xF0,0x04,0x01, ++0x81,0x42,0xFA,0xD1,0x00,0x24,0x0C,0x4E, ++0x3D,0x89,0x01,0x20,0xFF,0xF7,0x72,0xFC, ++0x38,0x89,0xA9,0x06,0x01,0xD5,0x80,0x06, ++0x02,0xD4,0x64,0x1C,0xB4,0x42,0xF3,0xD3, ++0xB4,0x42,0x0F,0xD1,0x01,0x48,0x40,0x1C, ++0x06,0xE6,0x00,0x00,0x05,0x00,0x00,0x80, ++0xEC,0x15,0x03,0x20,0x00,0x50,0x00,0x25, ++0x80,0x96,0x98,0x00,0x20,0x15,0x03,0x20, ++0x04,0x0A,0x00,0x80,0x00,0x20,0xF7,0xE5, ++0x2D,0xE9,0xF3,0x4F,0x81,0x46,0xFB,0x4C, ++0x00,0x25,0x85,0xB0,0x2E,0x46,0x2F,0x46, ++0xA8,0x46,0x60,0x68,0x01,0x07,0x08,0xD5, ++0xC0,0x06,0x0D,0xD4,0x94,0xF8,0x46,0x00, ++0x50,0xB1,0x00,0x20,0xFF,0xF7,0x27,0xFF, ++0x06,0xE0,0x94,0xF8,0x44,0x00,0x05,0x28, ++0x02,0xD0,0x05,0x20,0xFF,0xF7,0x11,0xFD, ++0x94,0xF8,0x7B,0x10,0x00,0x20,0x01,0xB9, ++0x09,0x20,0xDF,0xF8,0xB4,0xA3,0x4F,0xF0, ++0x01,0x0B,0x09,0xFA,0x00,0xF1,0xA1,0x46, ++0x03,0x91,0xA0,0x8F,0x94,0xF8,0x88,0x10, ++0x08,0x43,0x02,0x90,0x0E,0x20,0x01,0x90, ++0x04,0xF1,0x0C,0x00,0x04,0x90,0xD9,0xF8, ++0x04,0x00,0x00,0x07,0x13,0xD5,0x0A,0xF1, ++0xC8,0x04,0x40,0xF2,0x11,0x10,0xA0,0x80, ++0x20,0x88,0x40,0xF0,0x80,0x00,0x20,0x80, ++0x20,0x88,0x20,0xF0,0x40,0x00,0x20,0x80, ++0xDC,0x48,0xFF,0xF7,0x0F,0xFC,0x20,0x88, ++0x20,0xF0,0x80,0x00,0x20,0x80,0xFF,0xF7, ++0x17,0xFE,0x54,0x46,0xAA,0xF8,0x2C,0xB0, ++0x06,0x98,0x4F,0xF4,0x00,0x71,0xFF,0xF7, ++0x26,0xFD,0xA4,0xF8,0x70,0x00,0x00,0x0C, ++0xA4,0xF8,0x74,0x00,0x20,0x89,0x20,0xF0, ++0x04,0x00,0x20,0x81,0x00,0x20,0xFF,0xF7, ++0x75,0xFF,0x04,0x00,0x0A,0xD0,0x02,0x2D, ++0x24,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x20,0xD4,0x6D,0x1C,0xED,0xB2,0xFF,0xF7, ++0x8E,0xFE,0xC4,0xE7,0xBA,0xF8,0x28,0x10, ++0x41,0xF0,0x01,0x01,0xAA,0xF8,0x28,0x10, ++0x05,0x23,0xDD,0xE9,0x02,0x02,0x01,0x99, ++0x00,0x93,0x11,0x23,0xFF,0xF7,0x28,0xFF, ++0x04,0x00,0x0E,0xD0,0xB8,0xF1,0x02,0x0F, ++0x08,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x08,0xF1,0x01,0x00,0x00,0xF0, ++0xFF,0x08,0x2C,0xE0,0xFF,0xF7,0x90,0xFE, ++0x2E,0xE0,0xB9,0x4A,0x4F,0xF4,0x90,0x41, ++0x54,0x46,0x50,0x46,0xFF,0xF7,0x50,0xFD, ++0xB4,0xF8,0x48,0x10,0x50,0xEA,0xC1,0x60, ++0x08,0xD0,0x02,0x2E,0x1E,0xD2,0xD9,0xF8, ++0x04,0x00,0xC0,0x06,0x1A,0xD4,0x76,0x1C, ++0xF6,0xB2,0x14,0xE0,0x04,0x9A,0x03,0x21, ++0x00,0x20,0xFF,0xF7,0x99,0xFD,0xFF,0xF7, ++0xC4,0xFE,0x04,0x00,0x10,0xD0,0x04,0x98, ++0x05,0x21,0x01,0xF0,0xCC,0xFA,0x02,0x2F, ++0x08,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x7F,0x1C,0xFF,0xB2,0xFF,0xF7, ++0x93,0xFE,0x78,0xE7,0xA3,0x4C,0xCD,0xE7, ++0xD9,0xF8,0x04,0x00,0x00,0x07,0x05,0xD5, ++0x0A,0xF1,0xC8,0x00,0x01,0x88,0x41,0xF0, ++0x40,0x01,0x01,0x80,0x0A,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x07,0xB0,0x20,0x46,0xBD,0xE8,0xF0,0x8F, ++0x2E,0xE7,0x70,0xB5,0x04,0x20,0x98,0x4C, ++0x21,0x68,0xFF,0xF7,0xF9,0xFF,0x91,0x4D, ++0x20,0xB1,0x21,0x68,0x05,0x20,0xFF,0xF7, ++0xF3,0xFF,0xE0,0xB9,0x8D,0x48,0x2A,0x22, ++0x21,0x68,0x45,0x30,0x04,0x46,0x02,0xF0, ++0xF8,0xED,0x26,0x21,0x20,0x46,0x01,0xF0, ++0xC1,0xFA,0x04,0x46,0x87,0x48,0x6B,0x30, ++0x02,0xF0,0x32,0xEF,0xA0,0x42,0x01,0xD0, ++0x8A,0x48,0x08,0xE0,0x5C,0xB9,0x95,0xF8, ++0x47,0x00,0x95,0xF8,0x4A,0x10,0x88,0x42, ++0x05,0xD1,0x86,0x48,0x40,0x1C,0x00,0x21, ++0x85,0xF8,0x45,0x10,0x70,0xBD,0x00,0x20, ++0x70,0xBD,0x2D,0xE9,0xFC,0x5F,0x00,0x25, ++0x7A,0x49,0x2E,0x46,0xDF,0xF8,0xE8,0x91, ++0x2F,0x46,0x4F,0xF0,0x06,0x0B,0x88,0x46, ++0xCA,0x6F,0x01,0xF1,0x0C,0x0A,0xC2,0xF3, ++0x80,0x02,0x42,0xEA,0x00,0x40,0x01,0x90, ++0xFF,0xF7,0x4E,0xFD,0x05,0x23,0x01,0x9A, ++0x00,0x93,0x0D,0x23,0xB8,0xF8,0x3C,0x00, ++0x59,0x46,0xFF,0xF7,0x85,0xFE,0x04,0x00, ++0x08,0xD0,0x02,0x2F,0x2F,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x2B,0xD4,0x7F,0x1C, ++0xFF,0xB2,0x25,0xE0,0xB9,0xF8,0x48,0x00, ++0x10,0xF0,0x18,0x0F,0x0B,0xD0,0x02,0x2E, ++0x06,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x02,0xD4,0x76,0x1C,0xF6,0xB2,0x17,0xE0, ++0x64,0x4C,0xE4,0x1C,0x17,0xE0,0x03,0x21, ++0x00,0x20,0x52,0x46,0xFF,0xF7,0x00,0xFD, ++0xFF,0xF7,0x2B,0xFE,0x04,0x00,0x10,0xD0, ++0x05,0x21,0x50,0x46,0x01,0xF0,0x33,0xFA, ++0x02,0x2D,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFF,0xF7,0xFA,0xFD,0xC0,0xE7,0xFF,0xF7, ++0xC7,0xFD,0x09,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x20,0x46, ++0xBD,0xE8,0xFC,0x9F,0x2D,0xE9,0xFC,0x5F, ++0x00,0x25,0x4C,0x49,0x82,0x46,0x06,0x20, ++0xDF,0xF8,0x2C,0x91,0x2E,0x46,0x2F,0x46, ++0x4A,0x68,0x88,0x46,0x01,0xF1,0x0C,0x0B, ++0x42,0xF0,0x04,0x02,0x4A,0x60,0x01,0x90, ++0xFF,0xF7,0xF2,0xFC,0x05,0x23,0x01,0x99, ++0x00,0x93,0x06,0x23,0xB8,0xF8,0x3C,0x00, ++0x52,0x46,0xFF,0xF7,0x29,0xFE,0x04,0x00, ++0x08,0xD0,0x02,0x2F,0x2F,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x2B,0xD4,0x7F,0x1C, ++0xFF,0xB2,0x25,0xE0,0xB9,0xF8,0x48,0x00, ++0x10,0xF0,0x18,0x0F,0x0B,0xD0,0x02,0x2E, ++0x06,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x02,0xD4,0x76,0x1C,0xF6,0xB2,0x17,0xE0, ++0x36,0x4C,0xA4,0x1C,0x17,0xE0,0x03,0x21, ++0x00,0x20,0x5A,0x46,0xFF,0xF7,0xA4,0xFC, ++0xFF,0xF7,0xCF,0xFD,0x04,0x00,0x10,0xD0, ++0x05,0x21,0x58,0x46,0x01,0xF0,0xD7,0xF9, ++0x02,0x2D,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFF,0xF7,0x9E,0xFD,0xC0,0xE7,0xFF,0xF7, ++0x6B,0xFD,0x09,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x20,0x46, ++0xD8,0xF8,0x04,0x10,0x21,0xF0,0x04,0x01, ++0xC8,0xF8,0x04,0x10,0x9C,0xE7,0x80,0x07, ++0x10,0xB5,0x80,0x09,0x40,0xEA,0x01,0x40, ++0x40,0xEA,0x02,0x20,0xFF,0xF7,0x96,0xFF, ++0x00,0x28,0x04,0xD1,0x17,0x48,0x00,0x88, ++0xBD,0xE8,0x10,0x40,0x31,0xE7,0x10,0xBD, ++0x10,0xB5,0x04,0x46,0x19,0x48,0x08,0x38, ++0x01,0x2C,0x31,0xD0,0x04,0x2C,0x31,0xD0, ++0x08,0x2C,0x1D,0xD1,0x02,0x22,0x09,0xB1, ++0x42,0xF0,0x04,0x02,0x04,0x2A,0x17,0xD0, ++0xB7,0x21,0x03,0x20,0xFF,0xF7,0xDB,0xFF, ++0x00,0x28,0x11,0xD1,0x01,0x2C,0x09,0x49, ++0x8A,0x8F,0x22,0xF0,0x06,0x02,0x8A,0x87, ++0x1E,0xD0,0x04,0x2C,0x20,0xD0,0x08,0x2C, ++0x06,0xD1,0x04,0x22,0x81,0xF8,0x88,0x20, ++0x8A,0x8F,0x42,0xF0,0x04,0x02,0x8A,0x87, ++0x10,0xBD,0x00,0x00,0x20,0x15,0x03,0x20, ++0x00,0x50,0x00,0x25,0x80,0x96,0x98,0x00, ++0x40,0x4B,0x4C,0x00,0x0B,0x0A,0x00,0x80, ++0x80,0x05,0x03,0x20,0x1B,0x00,0x00,0x80, ++0x00,0x22,0xD0,0xE7,0x01,0x22,0xCE,0xE7, ++0x00,0x22,0x81,0xF8,0x88,0x20,0xE7,0xE7, ++0x02,0x22,0x81,0xF8,0x88,0x20,0x8A,0x8F, ++0x42,0xF0,0x02,0x02,0xDF,0xE7,0x70,0xB5, ++0xFF,0x4C,0x60,0x68,0x00,0x07,0x17,0xD4, ++0xFF,0xF7,0xB3,0xFE,0x05,0x46,0x01,0x21, ++0x08,0x20,0xFF,0xF7,0xAD,0xFF,0x00,0x28, ++0x0F,0xD1,0x01,0x20,0xFF,0xF7,0x4C,0xFA, ++0xA0,0x8F,0x40,0xF0,0x40,0x00,0xA0,0x87, ++0x60,0x68,0x40,0xF0,0x08,0x00,0x60,0x60, ++0x15,0xB9,0x00,0x20,0xFF,0xF7,0x07,0xFD, ++0x00,0x20,0x70,0xBD,0x10,0xB5,0x00,0x21, ++0x08,0x20,0xFF,0xF7,0x95,0xFF,0x00,0x28, ++0xBA,0xD1,0x02,0x20,0xFF,0xF7,0x34,0xFA, ++0xEB,0x49,0x11,0x20,0x88,0x87,0x48,0x68, ++0x10,0xF0,0x60,0x0F,0x01,0xD0,0x51,0x22, ++0x8A,0x87,0x20,0xF0,0x08,0x00,0x48,0x60, ++0x00,0x20,0xA9,0xE7,0xE5,0x4B,0x00,0x20, ++0x10,0xB5,0x07,0xE0,0x03,0xEB,0x80,0x04, ++0xB4,0xF8,0x00,0x44,0x22,0xF8,0x10,0x40, ++0x40,0x1C,0x80,0xB2,0x88,0x42,0xF5,0xD3, ++0x9A,0xE7,0x2D,0xE9,0xFF,0x5F,0x00,0x26, ++0x81,0x46,0xDB,0x48,0x07,0x29,0x8A,0x46, ++0x34,0x46,0x37,0x46,0x04,0xD1,0x41,0x68, ++0x41,0xF0,0x04,0x01,0x41,0x60,0x01,0xE0, ++0x4F,0xF0,0xF0,0x04,0x4F,0xEA,0x09,0x41, ++0x02,0x91,0x04,0xD1,0x02,0x88,0x4A,0x45, ++0x01,0xD0,0x04,0x21,0x00,0xE0,0x06,0x21, ++0x80,0x46,0x0C,0x30,0xDF,0xF8,0x3C,0xB3, ++0x01,0x91,0x03,0x90,0xFF,0xF7,0xE4,0xFB, ++0x05,0x23,0x00,0x93,0x53,0x46,0xDD,0xE9, ++0x01,0x12,0xB8,0xF8,0x3C,0x00,0xFF,0xF7, ++0x1B,0xFD,0x05,0x00,0x08,0xD0,0x02,0x2F, ++0x35,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x31,0xD4,0x7F,0x1C,0xFF,0xB2,0x2B,0xE0, ++0xBB,0xF8,0x48,0x00,0xBA,0xF1,0x07,0x0F, ++0x03,0xD1,0xB8,0xF8,0x00,0x10,0x49,0x45, ++0x27,0xD1,0x10,0xF0,0x18,0x0F,0x0A,0xD0, ++0x02,0x2C,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x64,0x1C,0xE4,0xB2, ++0x16,0xE0,0xB9,0x4D,0x17,0xE0,0x03,0x9A, ++0x03,0x21,0x00,0x20,0xFF,0xF7,0x90,0xFB, ++0xFF,0xF7,0xBB,0xFC,0x05,0x00,0x10,0xD0, ++0x03,0x98,0x05,0x21,0x01,0xF0,0xC3,0xF8, ++0x02,0x2E,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x76,0x1C,0xF6,0xB2, ++0xFF,0xF7,0x8A,0xFC,0xBA,0xE7,0xFF,0xF7, ++0x57,0xFC,0x0B,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0xBA,0xF1, ++0x07,0x0F,0x05,0xD1,0xD8,0xF8,0x04,0x10, ++0x21,0xF0,0x04,0x01,0xC8,0xF8,0x04,0x10, ++0x04,0xB0,0x28,0x46,0xBD,0xE8,0xF0,0x9F, ++0x2D,0xE9,0xF8,0x4F,0x00,0x24,0xDF,0xF8, ++0x78,0x82,0x25,0x46,0x9D,0x4F,0xA2,0x46, ++0x4F,0xF0,0x07,0x09,0xFF,0xF7,0x80,0xFB, ++0x10,0x23,0x52,0x46,0x00,0x93,0x02,0x23, ++0xB8,0xF8,0x3C,0x00,0x49,0x46,0xFF,0xF7, ++0xB7,0xFC,0x06,0x00,0x07,0xD0,0x02,0x2D, ++0x02,0xD2,0x6D,0x1C,0xED,0xB2,0x0B,0xE0, ++0xFF,0xF7,0x26,0xFC,0x14,0xE0,0xB7,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x09,0xD0, ++0x02,0x2C,0x04,0xD2,0x64,0x1C,0xE4,0xB2, ++0xFF,0xF7,0x4A,0xFC,0xDE,0xE7,0x8C,0x4E, ++0x76,0x1E,0xED,0xE7,0x88,0x4A,0x08,0x21, ++0x00,0x20,0x2C,0x32,0xFF,0xF7,0x34,0xFB, ++0x37,0xF8,0x40,0x0F,0x20,0xF0,0x01,0x00, ++0x38,0x80,0x30,0x46,0xBD,0xE8,0xF8,0x8F, ++0x2D,0xE9,0xF8,0x4F,0x00,0x24,0xDF,0xF8, ++0x0C,0xA2,0x25,0x46,0x7F,0x4F,0x4F,0xF0, ++0x06,0x09,0xDF,0xF8,0xF4,0x81,0xFF,0xF7, ++0x43,0xFB,0x05,0x23,0x52,0x46,0x00,0x93, ++0x01,0x23,0xB8,0xF8,0x3C,0x00,0x49,0x46, ++0xFF,0xF7,0x7A,0xFC,0x06,0x00,0x07,0xD0, ++0x02,0x2D,0x02,0xD2,0x6D,0x1C,0xED,0xB2, ++0x0A,0xE0,0xFF,0xF7,0xE9,0xFB,0x1F,0xE0, ++0xB7,0xF8,0x48,0x00,0x00,0x07,0x09,0xD5, ++0x02,0x2C,0x04,0xD2,0x64,0x1C,0xE4,0xB2, ++0xFF,0xF7,0x0E,0xFC,0xDF,0xE7,0x6E,0x4E, ++0xF6,0x1E,0xEE,0xE7,0x6A,0x4A,0x03,0x21, ++0x00,0x20,0x0C,0x32,0xFF,0xF7,0xF8,0xFA, ++0x98,0xF8,0x0D,0x00,0x41,0x46,0x02,0x06, ++0x02,0xD4,0x67,0x4E,0xB6,0x1E,0x03,0xE0, ++0xC0,0xF3,0x80,0x10,0x81,0xF8,0x7B,0x00, ++0x37,0xF8,0x40,0x0F,0x20,0xF0,0x01,0x00, ++0x38,0x80,0x30,0x46,0xB6,0xE7,0x2D,0xE9, ++0xF8,0x43,0x00,0x24,0x5C,0x4E,0x04,0x27, ++0x80,0x46,0xFF,0xF7,0x01,0xFB,0x00,0x23, ++0x42,0x46,0x00,0x93,0x39,0x46,0xB0,0x8F, ++0xFF,0xF7,0x3A,0xFC,0x05,0x00,0x08,0xD0, ++0x02,0x2C,0x04,0xD2,0x64,0x1C,0xE4,0xB2, ++0xFF,0xF7,0xDA,0xFB,0xED,0xE7,0xFF,0xF7, ++0xA7,0xFB,0x52,0x48,0x40,0x30,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x28,0x46, ++0xBD,0xE8,0xF8,0x83,0x2D,0xE9,0xF0,0x41, ++0x00,0x20,0xFF,0xF7,0xD8,0xFF,0x00,0x28, ++0x10,0xD1,0x00,0x24,0x4F,0xF4,0x7A,0x77, ++0x4F,0xF4,0x80,0x56,0xFF,0xF7,0x88,0xFF, ++0x05,0x00,0x08,0xD0,0x38,0x46,0xFF,0xF7, ++0xC5,0xF8,0x64,0x1C,0xA4,0xB2,0xB4,0x42, ++0xF4,0xD3,0x28,0x46,0x09,0xE4,0xFF,0xF7, ++0x3F,0xFF,0x00,0x28,0xFA,0xD1,0x02,0x20, ++0x3D,0x4D,0x00,0x24,0x28,0x80,0x03,0x21, ++0x28,0x88,0xFF,0xF7,0xBA,0xFE,0x00,0x28, ++0xF0,0xD0,0x29,0x88,0x64,0x1C,0x49,0x1C, ++0xA4,0xB2,0x05,0x2C,0x29,0x80,0xF2,0xD3, ++0x27,0xE4,0x2D,0xE9,0xF8,0x4F,0x00,0x24, ++0xDF,0xF8,0xD0,0x80,0x25,0x46,0x32,0x4F, ++0x4F,0xEA,0x00,0x4A,0x4F,0xF0,0x07,0x09, ++0xFF,0xF7,0xAA,0xFA,0x10,0x23,0x52,0x46, ++0x00,0x93,0x09,0x23,0xB8,0x8F,0x49,0x46, ++0xFF,0xF7,0xE2,0xFB,0x06,0x00,0x0A,0xD0, ++0x02,0x2D,0x05,0xD2,0x78,0x68,0xC0,0x06, ++0x02,0xD4,0x6D,0x1C,0xED,0xB2,0x0E,0xE0, ++0xFF,0xF7,0x4E,0xFB,0x17,0xE0,0xB8,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0C,0xD0, ++0x02,0x2C,0x07,0xD2,0x78,0x68,0xC0,0x06, ++0x04,0xD4,0x64,0x1C,0xE4,0xB2,0xFF,0xF7, ++0x6F,0xFB,0xD9,0xE7,0x1E,0x4E,0x16,0x36, ++0xEA,0xE7,0x1B,0x4A,0x08,0x21,0x00,0x20, ++0x1C,0x32,0xFF,0xF7,0x59,0xFA,0x08,0xF1, ++0x40,0x00,0x01,0x88,0x21,0xF0,0x01,0x01, ++0x01,0x80,0x30,0x46,0x22,0xE7,0x70,0xB5, ++0x13,0x4C,0x20,0x88,0xFF,0xF7,0xB9,0xFF, ++0x00,0x28,0x65,0xD1,0x1C,0x34,0x60,0x78, ++0xC0,0xF3,0x83,0x00,0x84,0xF8,0x53,0x00, ++0xA0,0x79,0x00,0xF0,0x0F,0x02,0x84,0xF8, ++0x54,0x20,0x61,0x7B,0xA3,0x7B,0x88,0x07, ++0x00,0x0F,0x00,0xEB,0x93,0x10,0x84,0xF8, ++0x55,0x00,0xE0,0x79,0x23,0x7A,0x80,0x07, ++0x00,0x0D,0x80,0xB2,0x00,0xEB,0x83,0x00, ++0x63,0x7A,0x00,0xEB,0x93,0x10,0x80,0xB2, ++0xA4,0xF8,0x56,0x00,0x1C,0x3C,0x07,0xE0, ++0x20,0x15,0x03,0x20,0x00,0x50,0x00,0x25, ++0x03,0x0A,0x00,0x80,0x00,0x80,0xFF,0x40, ++0xA0,0xF5,0x70,0x63,0xFF,0x3B,0x03,0xD1, ++0x00,0x20,0xC4,0xF8,0x84,0x00,0x12,0xE0, ++0x24,0x34,0x40,0x1C,0xA3,0x78,0xE5,0x78, ++0x9B,0x07,0x5B,0x0F,0x03,0xEB,0xD5,0x13, ++0x84,0xF8,0x53,0x30,0xDB,0xB2,0x9B,0x1C, ++0x98,0x40,0x01,0x23,0x93,0x40,0x5A,0x12, ++0x50,0x43,0x20,0x66,0x24,0x3C,0x5C,0x34, ++0x14,0xF8,0x36,0x0C,0xC0,0xF3,0x84,0x02, ++0x22,0x77,0x80,0x07,0x14,0xF8,0x35,0x2C, ++0xC0,0x0E,0x00,0xEB,0x52,0x10,0x60,0x77, ++0x20,0x7F,0x62,0x7F,0x40,0x1C,0x52,0x1C, ++0x10,0xFB,0x02,0xF0,0x60,0x62,0x14,0xF8, ++0x3E,0x0C,0x20,0x76,0x14,0xF8,0x3D,0x0C, ++0x60,0x76,0x14,0xF8,0x3C,0x0C,0xA0,0x76, ++0xC1,0xF3,0x82,0x00,0xA0,0x77,0x00,0x20, ++0x70,0xBD,0x2D,0xE9,0xF1,0x4F,0x00,0x25, ++0xFD,0x4C,0x84,0xB0,0x2E,0x46,0x2F,0x46, ++0xA8,0x46,0x60,0x68,0x01,0x07,0x07,0xD5, ++0xC0,0x06,0x05,0xD4,0x94,0xF8,0x46,0x00, ++0x10,0xB1,0x00,0x20,0xFF,0xF7,0xCB,0xFA, ++0x00,0x20,0xDF,0xF8,0xD8,0xA3,0x03,0x90, ++0x4F,0xF0,0x01,0x0B,0xA0,0x8F,0xA1,0x46, ++0x94,0xF8,0x88,0x10,0x08,0x43,0x02,0x90, ++0x0E,0x20,0x01,0x90,0xD9,0xF8,0x04,0x00, ++0x00,0x07,0x13,0xD5,0x0A,0xF1,0xC8,0x04, ++0x40,0xF2,0x11,0x10,0xA0,0x80,0x20,0x88, ++0x40,0xF0,0x80,0x00,0x20,0x80,0x20,0x88, ++0x20,0xF0,0x40,0x00,0x20,0x80,0xE8,0x48, ++0xFE,0xF7,0xC4,0xFF,0x20,0x88,0x20,0xF0, ++0x80,0x00,0x20,0x80,0xFF,0xF7,0xCC,0xF9, ++0x54,0x46,0xAA,0xF8,0x2C,0xB0,0x04,0x98, ++0x4F,0xF4,0x00,0x71,0xFF,0xF7,0xDB,0xF8, ++0xA4,0xF8,0x70,0x00,0x00,0x0C,0xA4,0xF8, ++0x74,0x00,0x20,0x89,0x20,0xF0,0x04,0x00, ++0x20,0x81,0x00,0x20,0xFF,0xF7,0x2A,0xFB, ++0x04,0x00,0x0A,0xD0,0x02,0x2D,0x24,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x20,0xD4, ++0x6D,0x1C,0xED,0xB2,0xFF,0xF7,0x43,0xFA, ++0xC4,0xE7,0xBA,0xF8,0x28,0x10,0x41,0xF0, ++0x01,0x01,0xAA,0xF8,0x28,0x10,0x05,0x23, ++0xDD,0xE9,0x02,0x02,0x01,0x99,0x00,0x93, ++0x08,0x23,0xFF,0xF7,0xDD,0xFA,0x04,0x00, ++0x0E,0xD0,0xB8,0xF1,0x02,0x0F,0x08,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x04,0xD4, ++0x08,0xF1,0x01,0x00,0x00,0xF0,0xFF,0x08, ++0x2E,0xE0,0xFF,0xF7,0x45,0xFA,0x30,0xE0, ++0xC4,0x4A,0x4F,0xF4,0x90,0x41,0x54,0x46, ++0x50,0x46,0xFF,0xF7,0x05,0xF9,0xB4,0xF8, ++0x48,0x10,0x50,0xEA,0xC1,0x60,0x08,0xD0, ++0x02,0x2E,0x20,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x1C,0xD4,0x76,0x1C,0xF6,0xB2, ++0x16,0xE0,0xBB,0x48,0x03,0x21,0x02,0x68, ++0x00,0x20,0xFF,0xF7,0x4D,0xF9,0xFF,0xF7, ++0x78,0xFA,0x04,0x00,0x11,0xD0,0x05,0x21, ++0xB1,0x48,0x0C,0x30,0x00,0xF0,0x7F,0xFE, ++0x02,0x2F,0x08,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x7F,0x1C,0xFF,0xB2, ++0xFF,0xF7,0x46,0xFA,0x76,0xE7,0xAF,0x4C, ++0xCB,0xE7,0xD9,0xF8,0x04,0x00,0x00,0x07, ++0x05,0xD5,0x0A,0xF1,0xC8,0x00,0x01,0x88, ++0x41,0xF0,0x40,0x01,0x01,0x80,0x0A,0xF1, ++0x40,0x00,0x01,0x88,0x21,0xF0,0x01,0x01, ++0x01,0x80,0x20,0x46,0x05,0xB0,0xBD,0xE8, ++0xF0,0x8F,0x3E,0xE7,0x70,0xB5,0xA2,0x4D, ++0x28,0x68,0xFF,0xF7,0xFA,0xFF,0x00,0x28, ++0x46,0xD1,0x9B,0x4C,0xD4,0xF8,0x84,0x00, ++0x50,0xB9,0x28,0x68,0x06,0x46,0xD5,0x30, ++0x02,0xF0,0xF2,0xEA,0x96,0xF8,0xD4,0x10, ++0x41,0xEA,0x00,0x20,0xC4,0xF8,0x84,0x00, ++0x28,0x68,0x90,0xF8,0xB7,0x10,0x84,0xF8, ++0x88,0x10,0x31,0xB1,0x01,0x29,0x0C,0xD0, ++0x02,0x29,0x0C,0xD1,0x04,0x21,0x84,0xF8, ++0x88,0x10,0x90,0xF8,0xE7,0x10,0xC9,0x06, ++0xE1,0x6F,0x05,0xD5,0x41,0xF0,0x01,0x01, ++0x04,0xE0,0x02,0x21,0xF3,0xE7,0xFE,0xE7, ++0x21,0xF0,0x01,0x01,0xE1,0x67,0x90,0xF8, ++0xF7,0x11,0xCA,0x07,0x0F,0xD0,0x89,0x07, ++0xE1,0x6F,0x02,0xD5,0x41,0xF0,0x02,0x01, ++0x01,0xE0,0x41,0xF0,0x04,0x01,0xE1,0x67, ++0x90,0xF8,0xA6,0x10,0x49,0x07,0x06,0xD5, ++0x40,0xF6,0xFF,0x70,0x05,0xE0,0xE1,0x6F, ++0x21,0xF0,0x06,0x01,0xF3,0xE7,0x90,0xF8, ++0xDE,0x00,0xA4,0xF8,0x8A,0x00,0x00,0x20, ++0x70,0xBD,0x2D,0xE9,0xF1,0x4F,0x00,0x25, ++0xDF,0xF8,0xD8,0x91,0x84,0xB0,0x2E,0x46, ++0x2F,0x46,0xA9,0xF8,0x3C,0x50,0x4F,0xF0, ++0x0E,0x0B,0xDF,0xF8,0xC4,0x81,0x03,0x95, ++0xDF,0xF8,0xD0,0xA1,0xB8,0xF8,0x3C,0x00, ++0x98,0xF8,0x88,0x10,0xAA,0xF1,0x01,0x0A, ++0x08,0x43,0x40,0xF0,0x20,0x00,0x02,0x90, ++0xFF,0xF7,0xDA,0xF8,0xDD,0xE9,0x02,0x02, ++0x05,0x23,0x00,0x93,0x08,0x23,0x59,0x46, ++0xFF,0xF7,0x12,0xFA,0x04,0x00,0x0B,0xD0, ++0x02,0x2F,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x7F,0x1C,0xFF,0xB2, ++0x2D,0xE0,0xFF,0xF7,0x7D,0xF9,0x35,0xE0, ++0x60,0x4A,0x04,0x21,0x4C,0x46,0x48,0x46, ++0xFF,0xF7,0x3E,0xF8,0xB4,0xF8,0x48,0x10, ++0x08,0xB9,0xC8,0x06,0x08,0xD0,0x02,0x2D, ++0x20,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x1C,0xD4,0x6D,0x1C,0xED,0xB2,0x16,0xE0, ++0x57,0x48,0x03,0x21,0x02,0x68,0x00,0x20, ++0xFF,0xF7,0x86,0xF8,0xFF,0xF7,0xB1,0xF9, ++0x04,0x00,0x11,0xD0,0x05,0x21,0x4E,0x48, ++0x0C,0x30,0x00,0xF0,0xB8,0xFD,0x02,0x2E, ++0x08,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFF,0xF7, ++0x7F,0xF9,0xB9,0xE7,0x54,0x46,0xCC,0xE7, ++0x04,0x9A,0x00,0x20,0x4F,0xF4,0x80,0x71, ++0xFF,0xF7,0x78,0xFC,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0x3B,0xE7,0x02,0x46,0x10,0xB5, ++0x04,0x46,0xB9,0x21,0x03,0x20,0xFF,0xF7, ++0xDA,0xFB,0x00,0x28,0x0F,0xD1,0x01,0x2C, ++0x39,0x4A,0x51,0x68,0x21,0xF0,0x60,0x01, ++0x51,0x60,0x09,0xD0,0x02,0x2C,0x0A,0xD1, ++0x41,0xF0,0x40,0x01,0x51,0x60,0x91,0x8F, ++0x41,0xF0,0x40,0x01,0x91,0x87,0x16,0xE4, ++0x41,0xF0,0x20,0x01,0xF6,0xE7,0x91,0x8F, ++0x21,0xF0,0x40,0x01,0xF6,0xE7,0x2D,0xE9, ++0xFC,0x5F,0x06,0x20,0x00,0x25,0x01,0x90, ++0x2E,0x46,0x2B,0x48,0x2F,0x46,0xC1,0x6F, ++0xC9,0x07,0x00,0xD0,0x01,0x21,0xDF,0xF8, ++0xA4,0x90,0x8A,0x46,0x80,0x46,0x00,0xF1, ++0x0C,0x0B,0xFF,0xF7,0x51,0xF8,0x05,0x23, ++0x01,0x99,0x00,0x93,0x26,0x23,0xB8,0xF8, ++0x3C,0x00,0x52,0x46,0xFF,0xF7,0x88,0xF9, ++0x04,0x00,0x08,0xD0,0x02,0x2F,0x2F,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x2B,0xD4, ++0x7F,0x1C,0xFF,0xB2,0x25,0xE0,0xB9,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0B,0xD0, ++0x02,0x2E,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x76,0x1C,0xF6,0xB2, ++0x17,0xE0,0x18,0x4C,0xA4,0x1F,0x17,0xE0, ++0x03,0x21,0x00,0x20,0x5A,0x46,0xFF,0xF7, ++0x03,0xF8,0xFF,0xF7,0x2E,0xF9,0x04,0x00, ++0x10,0xD0,0x05,0x21,0x58,0x46,0x00,0xF0, ++0x36,0xFD,0x02,0x2D,0x08,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x6D,0x1C, ++0xED,0xB2,0xFF,0xF7,0xFD,0xF8,0xC0,0xE7, ++0xFF,0xF7,0xCA,0xF8,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0xBD,0xE8,0xFC,0x9F,0x00,0x00, ++0x20,0x15,0x03,0x20,0x00,0x50,0x00,0x25, ++0x80,0x96,0x98,0x00,0x40,0x4B,0x4C,0x00, ++0x80,0x05,0x03,0x20,0x09,0x0A,0x00,0x80, ++0x2D,0xE9,0xF3,0x4F,0x00,0x25,0xFB,0x4A, ++0x83,0xB0,0x06,0x21,0x2E,0x46,0x02,0x91, ++0x2F,0x46,0x92,0xF8,0x7B,0x30,0x29,0x46, ++0x03,0xB9,0x09,0x21,0xDF,0xF8,0xD8,0x93, ++0x90,0x46,0x02,0xF1,0x0C,0x0B,0x00,0xFA, ++0x01,0xFA,0xFE,0xF7,0xE5,0xFF,0x05,0x23, ++0x02,0x99,0x00,0x93,0x52,0x46,0xB8,0xF8, ++0x3C,0x00,0x04,0x9B,0xFF,0xF7,0x1C,0xF9, ++0x04,0x00,0x08,0xD0,0x02,0x2F,0x2E,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x2A,0xD4, ++0x7F,0x1C,0xFF,0xB2,0x24,0xE0,0xB9,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0A,0xD0, ++0x02,0x2E,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x76,0x1C,0xF6,0xB2, ++0x16,0xE0,0xE2,0x4C,0x17,0xE0,0x03,0x21, ++0x00,0x20,0x5A,0x46,0xFE,0xF7,0x98,0xFF, ++0xFF,0xF7,0xC3,0xF8,0x04,0x00,0x10,0xD0, ++0x05,0x21,0x58,0x46,0x00,0xF0,0xCB,0xFC, ++0x02,0x2D,0x08,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x04,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFF,0xF7,0x92,0xF8,0xC1,0xE7,0xFF,0xF7, ++0x5F,0xF8,0x09,0xF1,0x40,0x00,0x01,0x88, ++0x21,0xF0,0x01,0x01,0x01,0x80,0x20,0x46, ++0x54,0xE6,0x10,0xB5,0x0C,0x46,0x23,0x21, ++0xFF,0xF7,0x9E,0xFF,0x00,0x28,0x08,0xD1, ++0x24,0x21,0x20,0x46,0xFF,0xF7,0x98,0xFF, ++0x00,0x28,0x02,0xD1,0xBD,0xE8,0x10,0x40, ++0x29,0xE7,0x20,0xE7,0x2D,0xE9,0xF3,0x4F, ++0x00,0x25,0xDF,0xF8,0x14,0x93,0x85,0xB0, ++0x82,0x46,0x2E,0x46,0x2F,0x46,0xA8,0x46, ++0xA9,0xF8,0x3C,0x50,0xBF,0x4C,0x94,0xF8, ++0x44,0x00,0x05,0x28,0x02,0xD0,0x05,0x20, ++0xFE,0xF7,0x43,0xFE,0x94,0xF8,0x7B,0x10, ++0x40,0x46,0x01,0xB9,0x09,0x20,0xDF,0xF8, ++0xE4,0xB2,0xA0,0x46,0x0A,0xFA,0x00,0xF1, ++0xDF,0xF8,0xE0,0xA2,0x04,0x91,0x0B,0xF1, ++0x0C,0x0B,0xA0,0x8F,0x0A,0xF1,0x07,0x0A, ++0x94,0xF8,0x88,0x10,0x08,0x43,0x40,0xF0, ++0x20,0x00,0x03,0x90,0x0E,0x20,0x02,0x90, ++0xFE,0xF7,0x5E,0xFF,0x05,0x23,0x02,0x99, ++0x00,0x93,0x11,0x23,0xDD,0xE9,0x03,0x02, ++0xFF,0xF7,0x96,0xF8,0x04,0x00,0x0B,0xD0, ++0x02,0x2F,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x7F,0x1C,0xFF,0xB2, ++0x2B,0xE0,0xFF,0xF7,0x01,0xF8,0x33,0xE0, ++0xA5,0x4A,0x04,0x21,0x4C,0x46,0x48,0x46, ++0xFE,0xF7,0xC2,0xFE,0xB4,0xF8,0x48,0x10, ++0x50,0xEA,0xC1,0x60,0x08,0xD0,0x02,0x2E, ++0x1E,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x1A,0xD4,0x76,0x1C,0xF6,0xB2,0x14,0xE0, ++0x03,0x21,0x00,0x20,0x5A,0x46,0xFE,0xF7, ++0x0B,0xFF,0xFF,0xF7,0x36,0xF8,0x04,0x00, ++0x10,0xD0,0x05,0x21,0x58,0x46,0x00,0xF0, ++0x3E,0xFC,0x02,0x2D,0x08,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x6D,0x1C, ++0xED,0xB2,0xFF,0xF7,0x05,0xF8,0xBB,0xE7, ++0x54,0x46,0xCE,0xE7,0x06,0x9A,0x00,0x20, ++0x4F,0xF4,0x80,0x71,0xFF,0xF7,0xFE,0xFA, ++0x09,0xF1,0x40,0x00,0x01,0x88,0x21,0xF0, ++0x01,0x01,0x01,0x80,0x20,0x46,0x07,0xB0, ++0xC1,0xE5,0x2D,0xE9,0xFC,0x5F,0x00,0x25, ++0x82,0x49,0x2E,0x46,0xDF,0xF8,0x08,0x92, ++0x2F,0x46,0x4F,0xF0,0x06,0x0B,0x88,0x46, ++0x48,0x68,0x01,0xF1,0x0C,0x0A,0x40,0xF0, ++0x04,0x00,0x48,0x60,0x01,0x95,0xFE,0xF7, ++0xF7,0xFE,0x05,0x23,0x01,0x9A,0x00,0x93, ++0x0C,0x23,0xB8,0xF8,0x3C,0x00,0x59,0x46, ++0xFF,0xF7,0x2E,0xF8,0x04,0x00,0x08,0xD0, ++0x02,0x2F,0x2F,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x2B,0xD4,0x7F,0x1C,0xFF,0xB2, ++0x25,0xE0,0xB9,0xF8,0x48,0x00,0x10,0xF0, ++0x18,0x0F,0x0B,0xD0,0x02,0x2D,0x06,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x02,0xD4, ++0x6D,0x1C,0xED,0xB2,0x17,0xE0,0x6B,0x4C, ++0x0C,0x34,0x17,0xE0,0x03,0x21,0x00,0x20, ++0x52,0x46,0xFE,0xF7,0xA9,0xFE,0xFE,0xF7, ++0xD4,0xFF,0x04,0x00,0x10,0xD0,0x05,0x21, ++0x50,0x46,0x00,0xF0,0xDC,0xFB,0x02,0x2E, ++0x08,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFE,0xF7, ++0xA3,0xFF,0xC0,0xE7,0xFE,0xF7,0x70,0xFF, ++0x09,0xF1,0x40,0x00,0x01,0x88,0x21,0xF0, ++0x01,0x01,0x01,0x80,0x20,0x46,0xD8,0xF8, ++0x04,0x10,0x21,0xF0,0x04,0x01,0xC8,0xF8, ++0x04,0x10,0x9E,0xE6,0x2D,0xE9,0xF7,0x4F, ++0x81,0x46,0x52,0x4C,0x00,0x25,0x86,0xB0, ++0x92,0x46,0x2E,0x46,0x2F,0x46,0x60,0x68, ++0xA8,0x46,0x01,0x07,0x08,0xD5,0xC0,0x06, ++0x0D,0xD4,0x94,0xF8,0x46,0x00,0x50,0xB1, ++0x00,0x20,0xFE,0xF7,0x6C,0xFF,0x06,0xE0, ++0x94,0xF8,0x44,0x00,0x05,0x28,0x02,0xD0, ++0x05,0x20,0xFE,0xF7,0x56,0xFD,0x94,0xF8, ++0x7B,0x10,0x00,0x20,0x01,0xB9,0x09,0x20, ++0xDF,0xF8,0x0C,0xB1,0x09,0xFA,0x00,0xF1, ++0xA1,0x46,0x03,0x91,0xA0,0x8F,0x94,0xF8, ++0x88,0x10,0x08,0x43,0x02,0x90,0x0E,0x20, ++0x01,0x90,0x04,0xF1,0x0C,0x00,0x05,0x90, ++0x4F,0xEA,0x4A,0x20,0x04,0x90,0xD9,0xF8, ++0x04,0x00,0x00,0x07,0x13,0xD5,0x0B,0xF1, ++0xC8,0x04,0x40,0xF2,0x11,0x10,0xA0,0x80, ++0x20,0x88,0x40,0xF0,0x80,0x00,0x20,0x80, ++0x20,0x88,0x20,0xF0,0x40,0x00,0x20,0x80, ++0x34,0x48,0xFE,0xF7,0x53,0xFC,0x20,0x88, ++0x20,0xF0,0x80,0x00,0x20,0x80,0xFE,0xF7, ++0x5B,0xFE,0x5C,0x46,0xAB,0xF8,0x2C,0xA0, ++0x04,0x99,0x07,0x98,0xFE,0xF7,0x6B,0xFD, ++0xA4,0xF8,0x70,0x00,0x00,0x0C,0xA4,0xF8, ++0x74,0x00,0x20,0x89,0x20,0xF0,0x04,0x00, ++0x20,0x81,0x00,0x20,0xFE,0xF7,0xBA,0xFF, ++0x04,0x00,0x0A,0xD0,0x02,0x2D,0x24,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x20,0xD4, ++0x6D,0x1C,0xED,0xB2,0xFE,0xF7,0xD3,0xFE, ++0xC5,0xE7,0xBB,0xF8,0x28,0x10,0x41,0xF0, ++0x01,0x01,0xAB,0xF8,0x28,0x10,0x05,0x23, ++0xDD,0xE9,0x02,0x02,0x01,0x99,0x00,0x93, ++0x12,0x23,0xFE,0xF7,0x6D,0xFF,0x04,0x00, ++0x0E,0xD0,0xB8,0xF1,0x02,0x0F,0x08,0xD2, ++0xD9,0xF8,0x04,0x00,0xC0,0x06,0x04,0xD4, ++0x08,0xF1,0x01,0x00,0x00,0xF0,0xFF,0x08, ++0x3B,0xE0,0xFE,0xF7,0xD5,0xFE,0x3D,0xE0, ++0x10,0x48,0x01,0x21,0x01,0xEB,0x5A,0x22, ++0x4F,0xF4,0x90,0x41,0x5C,0x46,0x42,0x43, ++0x58,0x46,0xFE,0xF7,0xA9,0xFD,0xB4,0xF8, ++0x48,0x10,0x50,0xEA,0xC1,0x60,0x13,0xD0, ++0x02,0x2E,0x29,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x25,0xD4,0x76,0x1C,0xF6,0xB2, ++0x1F,0xE0,0x00,0x00,0x20,0x15,0x03,0x20, ++0x00,0x50,0x00,0x25,0x03,0x0A,0x00,0x80, ++0x40,0x4B,0x4C,0x00,0x80,0x96,0x98,0x00, ++0x05,0x9A,0x03,0x21,0x00,0x20,0xFE,0xF7, ++0xCF,0xFD,0xFE,0xF7,0xFA,0xFE,0x04,0x00, ++0x10,0xD0,0x05,0x98,0x05,0x21,0x00,0xF0, ++0x02,0xFB,0x02,0x2F,0x08,0xD2,0xD9,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x7F,0x1C, ++0xFF,0xB2,0xFE,0xF7,0xC9,0xFE,0x6A,0xE7, ++0xFB,0x4C,0xBE,0xE7,0xD9,0xF8,0x04,0x00, ++0x49,0x46,0x00,0x07,0x05,0xD5,0x0B,0xF1, ++0xC8,0x00,0x02,0x88,0x42,0xF0,0x40,0x02, ++0x02,0x80,0x08,0x88,0xFF,0xF7,0xC5,0xFE, ++0x01,0x46,0x0B,0xF1,0x40,0x00,0x02,0x88, ++0x22,0xF0,0x01,0x02,0x02,0x80,0x20,0x00, ++0x00,0xD1,0x08,0x46,0x09,0xB0,0x7A,0xE4, ++0x18,0xE7,0x2D,0xE9,0xFC,0x5F,0x00,0x25, ++0xDF,0xF8,0xB4,0x83,0x40,0xF0,0x00,0x40, ++0xDF,0xF8,0xA8,0x93,0x2E,0x46,0x01,0x90, ++0x2F,0x46,0x4F,0xF0,0x06,0x0B,0x08,0xF1, ++0x0C,0x0A,0xFE,0xF7,0xB1,0xFD,0x05,0x23, ++0x01,0x9A,0x00,0x93,0x17,0x23,0xB8,0xF8, ++0x3C,0x00,0x59,0x46,0xFE,0xF7,0xE8,0xFE, ++0x04,0x00,0x08,0xD0,0x02,0x2F,0x2F,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x2B,0xD4, ++0x7F,0x1C,0xFF,0xB2,0x25,0xE0,0xB9,0xF8, ++0x48,0x00,0x10,0xF0,0x18,0x0F,0x0B,0xD0, ++0x02,0x2E,0x06,0xD2,0xD8,0xF8,0x04,0x00, ++0xC0,0x06,0x02,0xD4,0x76,0x1C,0xF6,0xB2, ++0x17,0xE0,0xD3,0x4C,0xA4,0x1C,0x17,0xE0, ++0x03,0x21,0x00,0x20,0x52,0x46,0xFE,0xF7, ++0x63,0xFD,0xFE,0xF7,0x8E,0xFE,0x04,0x00, ++0x10,0xD0,0x05,0x21,0x50,0x46,0x00,0xF0, ++0x96,0xFA,0x02,0x2D,0x08,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x04,0xD4,0x6D,0x1C, ++0xED,0xB2,0xFE,0xF7,0x5D,0xFE,0xC0,0xE7, ++0xFE,0xF7,0x2A,0xFE,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0x5E,0xE5,0x2D,0xE9,0xF7,0x4F, ++0x05,0x46,0xC1,0x4C,0x00,0x20,0x86,0xB0, ++0x07,0x46,0x80,0x46,0x81,0x46,0x04,0x90, ++0x82,0x46,0x60,0x68,0x16,0x46,0x01,0x07, ++0x08,0xD5,0xC0,0x06,0x0D,0xD4,0x94,0xF8, ++0x46,0x00,0x50,0xB1,0x00,0x20,0xFE,0xF7, ++0x2A,0xFE,0x06,0xE0,0x94,0xF8,0x44,0x00, ++0x05,0x28,0x02,0xD0,0x05,0x20,0xFE,0xF7, ++0x14,0xFC,0x94,0xF8,0x7B,0x10,0x00,0x20, ++0x01,0xB9,0x09,0x20,0xA3,0x46,0x85,0x40, ++0x03,0x95,0xA0,0x8F,0x94,0xF8,0x88,0x10, ++0x08,0x43,0x02,0x90,0x06,0x20,0x01,0x90, ++0x04,0xF1,0x0C,0x00,0x05,0x90,0x5C,0x46, ++0xBB,0xF8,0x8A,0x00,0x35,0x46,0xB0,0x42, ++0x00,0xD2,0x05,0x46,0x28,0x46,0xFF,0xF7, ++0x6C,0xFF,0x00,0x28,0x7E,0xD1,0x60,0x68, ++0xA3,0x46,0x00,0x07,0x08,0xD5,0x4F,0xF4, ++0x8D,0x71,0xA0,0x48,0xC8,0x30,0x81,0x80, ++0x01,0x88,0x41,0xF0,0x40,0x01,0x01,0x80, ++0xFE,0xF7,0x1E,0xFD,0x9B,0x4C,0xA5,0x85, ++0x69,0x02,0x07,0x98,0xFE,0xF7,0x2F,0xFC, ++0xA4,0xF8,0x70,0x00,0x00,0x0C,0xA4,0xF8, ++0x74,0x00,0x20,0x89,0x40,0xF0,0x04,0x00, ++0x20,0x81,0x04,0x20,0xFE,0xF7,0x7E,0xFE, ++0x04,0x00,0x0D,0xD0,0x02,0x2F,0x08,0xD2, ++0xDB,0xF8,0x04,0x00,0xC0,0x06,0x04,0xD4, ++0x7F,0x1C,0xFF,0xB2,0xFE,0xF7,0x97,0xFD, ++0xC5,0xE7,0xFE,0xF7,0xB5,0xFD,0x6D,0xE0, ++0x8A,0x48,0x01,0x8D,0x41,0xF0,0x01,0x01, ++0x01,0x85,0x05,0x23,0xDD,0xE9,0x02,0x02, ++0x01,0x99,0x00,0x93,0x19,0x23,0xFE,0xF7, ++0x2F,0xFE,0x04,0x00,0x0B,0xD0,0xBA,0xF1, ++0x02,0x0F,0xEA,0xD2,0xDB,0xF8,0x04,0x00, ++0xC0,0x06,0xE6,0xD4,0x0A,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x0A,0x16,0xE0,0x05,0x9A, ++0x03,0x21,0x00,0x20,0xFE,0xF7,0xB8,0xFC, ++0xFE,0xF7,0xE3,0xFD,0xA0,0xB1,0x05,0x98, ++0x05,0x21,0x00,0xF0,0xEC,0xF9,0xB9,0xF1, ++0x02,0x0F,0x0A,0xD2,0xDB,0xF8,0x04,0x00, ++0xC0,0x06,0x06,0xD4,0x09,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x09,0xFE,0xF7,0xB0,0xFD, ++0x8D,0xE7,0x6F,0x4C,0x0C,0x34,0xC4,0xE7, ++0xFE,0xF7,0xE8,0xFD,0x10,0xB1,0x6C,0x4C, ++0x0B,0x34,0x2F,0xE0,0x6B,0x49,0x18,0x20, ++0x44,0x31,0x08,0x80,0x01,0x20,0x00,0xEB, ++0xD5,0x12,0x6A,0x48,0x4F,0xF4,0x00,0x61, ++0x42,0x43,0x66,0x48,0xFE,0xF7,0x48,0xFC, ++0x04,0x46,0x00,0xE0,0x2C,0xE0,0x63,0x48, ++0xB0,0xF8,0x48,0x00,0x00,0xF0,0x06,0x01, ++0x21,0x43,0x0E,0xD0,0xB8,0xF1,0x02,0x0F, ++0x08,0xD2,0xDB,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x08,0xF1,0x01,0x00,0x00,0xF0, ++0xFF,0x08,0xCF,0xE7,0x58,0x4C,0x0A,0x34, ++0x97,0xE7,0x07,0x98,0x00,0xEB,0x45,0x20, ++0x07,0x90,0x70,0x1B,0x06,0x04,0x36,0x0C, ++0x8E,0xD1,0x24,0xB1,0xBB,0xF8,0x00,0x00, ++0xFF,0xF7,0x7F,0xFD,0x04,0x90,0x51,0x48, ++0x40,0x30,0x01,0x88,0x21,0xF0,0x01,0x01, ++0x01,0x80,0x20,0x00,0x00,0xD1,0x04,0x98, ++0xB8,0xE6,0x13,0xE7,0x01,0x22,0x11,0xE7, ++0x2D,0xE9,0xF3,0x4F,0x81,0x46,0x4A,0x4C, ++0x00,0x25,0x85,0xB0,0x2E,0x46,0x2F,0x46, ++0xA8,0x46,0x60,0x68,0x01,0x07,0x08,0xD5, ++0xC0,0x06,0x0D,0xD4,0x94,0xF8,0x46,0x00, ++0x50,0xB1,0x00,0x20,0xFE,0xF7,0x3F,0xFD, ++0x06,0xE0,0x94,0xF8,0x44,0x00,0x05,0x28, ++0x02,0xD0,0x05,0x20,0xFE,0xF7,0x29,0xFB, ++0x94,0xF8,0x7B,0x10,0x00,0x20,0x01,0xB9, ++0x09,0x20,0xDF,0xF8,0xE8,0xA0,0x4F,0xF0, ++0x01,0x0B,0x09,0xFA,0x00,0xF1,0xA1,0x46, ++0x03,0x91,0xA0,0x8F,0x94,0xF8,0x88,0x10, ++0x08,0x43,0x02,0x90,0x06,0x20,0x01,0x90, ++0x04,0xF1,0x0C,0x00,0x04,0x90,0xD9,0xF8, ++0x04,0x00,0x00,0x07,0x08,0xD5,0x0A,0xF1, ++0xC8,0x00,0x4F,0xF4,0x8D,0x71,0x81,0x80, ++0x01,0x88,0x41,0xF0,0x40,0x01,0x01,0x80, ++0xFE,0xF7,0x3A,0xFC,0x54,0x46,0xAA,0xF8, ++0x2C,0xB0,0x06,0x98,0x4F,0xF4,0x00,0x71, ++0xFE,0xF7,0x49,0xFB,0xA4,0xF8,0x70,0x00, ++0x00,0x0C,0xA4,0xF8,0x74,0x00,0x20,0x89, ++0x40,0xF0,0x04,0x00,0x20,0x81,0x04,0x20, ++0xFE,0xF7,0x98,0xFD,0x04,0x00,0x0A,0xD0, ++0x02,0x2D,0x65,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x61,0xD4,0x6D,0x1C,0xED,0xB2, ++0xFE,0xF7,0xB1,0xFC,0xCF,0xE7,0xBA,0xF8, ++0x28,0x10,0x41,0xF0,0x01,0x01,0xAA,0xF8, ++0x28,0x10,0x05,0x23,0xDD,0xE9,0x02,0x02, ++0x01,0x99,0x00,0x93,0x18,0x23,0xFE,0xF7, ++0x4B,0xFD,0x04,0x00,0x0B,0xD0,0xB8,0xF1, ++0x02,0x0F,0x49,0xD2,0xD9,0xF8,0x04,0x00, ++0xC0,0x06,0x45,0xD4,0x08,0xF1,0x01,0x00, ++0x00,0xF0,0xFF,0x08,0x3B,0xE0,0x04,0x9A, ++0x03,0x21,0x00,0x20,0xFE,0xF7,0xD4,0xFB, ++0xFE,0xF7,0xFF,0xFC,0xB0,0xB1,0x04,0x98, ++0x05,0x21,0x00,0xF0,0x08,0xF9,0x02,0x2F, ++0x0E,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x0A,0xD4,0x7F,0x1C,0xFF,0xB2,0x26,0xE0, ++0x0C,0x0A,0x00,0x80,0x00,0x50,0x00,0x25, ++0x20,0x15,0x03,0x20,0x80,0x96,0x98,0x00, ++0x73,0x4C,0x21,0xE0,0xFE,0xF7,0x02,0xFD, ++0x10,0xB1,0x71,0x4C,0x64,0x1E,0x1D,0xE0, ++0x18,0x20,0xAA,0xF8,0x44,0x00,0x04,0x21, ++0x6E,0x4A,0x50,0x46,0xFE,0xF7,0x50,0xFB, ++0x04,0x46,0xBA,0xF8,0x48,0x00,0x00,0xF0, ++0x06,0x01,0x21,0x43,0x0E,0xD0,0x02,0x2E, ++0x08,0xD2,0xD9,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFE,0xF7, ++0xA7,0xFC,0x74,0xE7,0x62,0x4C,0xA4,0x1E, ++0xFE,0xF7,0x72,0xFC,0x0A,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0xA4,0xE4,0x2D,0xE9,0xFE,0x4F, ++0x00,0x25,0xDF,0xF8,0x74,0x91,0x83,0x46, ++0x0C,0x46,0x2E,0x46,0x2F,0x46,0xA8,0x46, ++0xA9,0xF8,0x3C,0x50,0xDF,0xF8,0x64,0xA1, ++0x9A,0xF8,0x44,0x00,0x05,0x28,0x02,0xD0, ++0x05,0x20,0xFE,0xF7,0x66,0xFA,0x00,0x20, ++0x34,0xF8,0x10,0x10,0x09,0xEB,0x80,0x02, ++0xA2,0xF8,0x00,0x14,0x40,0x1C,0x80,0xB2, ++0xFF,0x28,0xF5,0xD9,0x9A,0xF8,0x7B,0x10, ++0x40,0x46,0x52,0x46,0x01,0xB9,0x09,0x20, ++0xDF,0xF8,0x30,0xA1,0x90,0x46,0x0B,0xFA, ++0x00,0xF1,0x4F,0xF0,0x06,0x0B,0x02,0x91, ++0x0A,0xF1,0x0C,0x0A,0x90,0x8F,0x92,0xF8, ++0x88,0x10,0x08,0x43,0x40,0xF0,0x20,0x00, ++0x01,0x90,0xFE,0xF7,0x79,0xFB,0x05,0x23, ++0x59,0x46,0x00,0x93,0x18,0x23,0xDD,0xE9, ++0x01,0x02,0xFE,0xF7,0xB1,0xFC,0x04,0x00, ++0x08,0xD0,0x02,0x2F,0x40,0xD2,0xD8,0xF8, ++0x04,0x00,0xC0,0x06,0x3C,0xD4,0x7F,0x1C, ++0xFF,0xB2,0x34,0xE0,0x03,0x21,0x00,0x20, ++0x52,0x46,0xFE,0xF7,0x3D,0xFB,0xFE,0xF7, ++0x68,0xFC,0x78,0xB1,0x05,0x21,0x50,0x46, ++0x00,0xF0,0x71,0xF8,0x02,0x2D,0x06,0xD2, ++0xD8,0xF8,0x04,0x00,0xC0,0x06,0x02,0xD4, ++0x6D,0x1C,0xED,0xB2,0x1F,0xE0,0x2C,0x4C, ++0xE4,0x1E,0x21,0xE0,0xFE,0xF7,0x72,0xFC, ++0x10,0xB1,0x29,0x4C,0x24,0x1F,0x1D,0xE0, ++0x18,0x20,0xA9,0xF8,0x44,0x00,0x04,0x21, ++0x26,0x4A,0x48,0x46,0xFE,0xF7,0xC0,0xFA, ++0x04,0x46,0xB9,0xF8,0x48,0x00,0x00,0xF0, ++0x06,0x01,0x21,0x43,0x0E,0xD0,0x02,0x2E, ++0x08,0xD2,0xD8,0xF8,0x04,0x00,0xC0,0x06, ++0x04,0xD4,0x76,0x1C,0xF6,0xB2,0xFE,0xF7, ++0x17,0xFC,0xB2,0xE7,0x1A,0x4C,0x64,0x1F, ++0xFE,0xF7,0xE2,0xFB,0x09,0xF1,0x40,0x00, ++0x01,0x88,0x21,0xF0,0x01,0x01,0x01,0x80, ++0x20,0x46,0xBD,0xE8,0xFE,0x8F,0x2D,0xE9, ++0xF0,0x47,0x00,0x24,0x15,0x4D,0x4F,0xF4, ++0x10,0x67,0x4F,0xF4,0x7A,0x79,0x4F,0xF0, ++0x80,0x76,0x05,0xF1,0x0D,0x08,0x28,0x88, ++0xFE,0xF7,0xAF,0xFD,0x40,0x46,0x01,0xF0, ++0xCC,0xEC,0x00,0xBA,0x29,0x7C,0x20,0xF0, ++0xFF,0x00,0x08,0x43,0xB8,0x42,0x05,0xD0, ++0x48,0x46,0xFE,0xF7,0xF7,0xF8,0x64,0x1C, ++0xB4,0x42,0xEC,0xD3,0xB4,0x42,0x03,0xD1, ++0x03,0x48,0x0B,0x30,0xBD,0xE8,0xF0,0x87, ++0x00,0x20,0xFB,0xE7,0xFE,0xE7,0x00,0x00, ++0x15,0x0A,0x00,0x80,0x40,0x4B,0x4C,0x00, ++0x00,0x50,0x00,0x25,0x20,0x15,0x03,0x20, ++0x3B,0x49,0x40,0x1E,0x01,0x42,0x00,0xD0, ++0xFE,0xE7,0x00,0x20,0x70,0x47,0x00,0x22, ++0x08,0xE0,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x00,0x20,0x40,0x1C,0x10,0x28, ++0xFC,0xDB,0x10,0x32,0x8A,0x42,0xF4,0xDB, ++0x70,0x47,0x0B,0x46,0x00,0x21,0x30,0xB5, ++0x04,0xE0,0x44,0x5C,0x5D,0x5C,0xAC,0x42, ++0x02,0xD1,0x49,0x1C,0x91,0x42,0xF8,0xD3, ++0x91,0x42,0x11,0xD0,0x2B,0x4A,0x52,0x68, ++0xD2,0x06,0x0D,0xD4,0x4C,0x0A,0x4F,0xF4, ++0x00,0x75,0x64,0x02,0x29,0x46,0x20,0x44, ++0xFF,0xF7,0xD9,0xFF,0x18,0x19,0x29,0x46, ++0xFF,0xF7,0xD5,0xFF,0x24,0x48,0x30,0xBD, ++0x00,0x20,0x30,0xBD,0x03,0x46,0x00,0x20, ++0x02,0x46,0x10,0xB5,0x03,0xE0,0x9C,0x5C, ++0x52,0x1C,0x92,0xB2,0x20,0x44,0x8A,0x42, ++0xF9,0xD3,0x10,0xBD,0x00,0x21,0x1D,0xA2, ++0x10,0xB5,0x43,0x5C,0x54,0x5C,0xA3,0x42, ++0x01,0xD0,0x01,0x20,0x10,0xBD,0x49,0x1C, ++0x10,0x29,0xF6,0xDB,0x00,0x20,0x10,0xBD, ++0x00,0xB5,0xAD,0xF5,0x01,0x7D,0xF8,0xF7, ++0x7C,0xFF,0x00,0x28,0x05,0xD1,0x01,0xA8, ++0xFF,0xF7,0x4F,0xF9,0x03,0x00,0x03,0xD0, ++0x18,0x46,0x0D,0xF5,0x01,0x7D,0x00,0xBD, ++0x0C,0x48,0x10,0x21,0x1C,0x30,0xFF,0xF7, ++0xA2,0xFF,0x0A,0x48,0x10,0x21,0x2C,0x30, ++0xFF,0xF7,0x9D,0xFF,0xF0,0xE7,0x00,0x21, ++0x49,0x1C,0x10,0x29,0xFC,0xDB,0x00,0x7C, ++0x00,0x21,0x00,0xE0,0x49,0x1C,0x88,0x42, ++0xFC,0xDC,0x70,0x47,0x70,0x47,0x00,0x00, ++0x80,0x17,0x03,0x20,0x20,0x15,0x03,0x20, ++0x04,0x00,0x00,0x80,0x4D,0x53,0x54,0x41, ++0x52,0x53,0x45,0x4D,0x49,0x55,0x4E,0x46, ++0x44,0x43,0x49,0x53,0x00,0x00,0x00,0x00, ++0x10,0xB5,0x43,0x78,0x04,0x78,0x04,0xEB, ++0x03,0x23,0x84,0x78,0xC0,0x78,0x24,0x04, ++0x04,0xEB,0x00,0x60,0x18,0x44,0x08,0x41, ++0x20,0x2A,0x03,0xD0,0x4F,0xF0,0xFF,0x31, ++0x91,0x40,0x88,0x43,0x10,0xBD,0x30,0xB5, ++0x05,0x00,0x1C,0x46,0x4F,0xF0,0x00,0x00, ++0x0A,0xD0,0x8B,0x18,0x20,0x2B,0x04,0xD8, ++0x28,0x46,0xFF,0xF7,0xE1,0xFF,0x00,0x21, ++0x00,0xE0,0xFE,0x21,0x21,0x70,0x30,0xBD, ++0xFF,0x21,0xFB,0xE7,0xF0,0xB5,0xC2,0xF1, ++0x08,0x04,0x1B,0x1B,0x4F,0xF0,0xFF,0x3C, ++0x10,0x3B,0x06,0x78,0x0C,0xFA,0x04,0xF5, ++0xEF,0x43,0x21,0xEA,0x05,0x05,0x97,0x40, ++0xBE,0x43,0x95,0x40,0x2E,0x43,0x41,0xFA, ++0x04,0xF2,0x06,0x70,0x0C,0xFA,0x03,0xFC, ++0x42,0x70,0x04,0xF1,0x08,0x02,0x41,0xFA, ++0x02,0xF2,0x10,0x34,0x82,0x70,0xC2,0x78, ++0x21,0x41,0x21,0xEA,0x0C,0x01,0x02,0xEA, ++0x0C,0x02,0x0A,0x43,0xC2,0x70,0xF0,0xBD, ++0xF0,0xB5,0xC2,0xF1,0x08,0x04,0x1B,0x1B, ++0x4F,0xF0,0xFF,0x3C,0x08,0x3B,0x06,0x78, ++0x0C,0xFA,0x04,0xF5,0xEF,0x43,0x21,0xEA, ++0x05,0x05,0x97,0x40,0xBE,0x43,0x95,0x40, ++0x2E,0x43,0x41,0xFA,0x04,0xF2,0x06,0x70, ++0x0C,0xFA,0x03,0xFC,0x08,0x34,0x42,0x70, ++0x82,0x78,0x21,0x41,0x02,0xEA,0x0C,0x02, ++0x21,0xEA,0x0C,0x01,0x0A,0x43,0x82,0x70, ++0xF0,0xBD,0xF0,0xB5,0xC2,0xF1,0x08,0x04, ++0x4F,0xF0,0xFF,0x3C,0x1B,0x1B,0x06,0x78, ++0x0C,0xFA,0x04,0xF5,0xEF,0x43,0x21,0xEA, ++0x05,0x05,0x97,0x40,0xBE,0x43,0x95,0x40, ++0x2E,0x43,0x0C,0xFA,0x03,0xFC,0x06,0x70, ++0x21,0x41,0x42,0x78,0x21,0xEA,0x0C,0x01, ++0x02,0xEA,0x0C,0x02,0x0A,0x43,0x42,0x70, ++0xF0,0xBD,0x30,0xB5,0x4F,0xF0,0xFF,0x34, ++0x05,0x78,0x9C,0x40,0xE3,0x43,0xA1,0x43, ++0x93,0x40,0x9D,0x43,0x91,0x40,0x0D,0x43, ++0x05,0x70,0x30,0xBD,0x30,0xB5,0x00,0x24, ++0xB8,0xB1,0xD5,0x18,0x08,0x2D,0x02,0xD8, ++0xFF,0xF7,0xEB,0xFF,0x13,0xE0,0x10,0x2D, ++0x02,0xD8,0xFF,0xF7,0xCA,0xFF,0x0E,0xE0, ++0x18,0x2D,0x02,0xD8,0xFF,0xF7,0xA4,0xFF, ++0x09,0xE0,0x20,0x2D,0x02,0xD8,0xFF,0xF7, ++0x79,0xFF,0x04,0xE0,0x6F,0xF0,0x01,0x04, ++0x01,0xE0,0x4F,0xF0,0xFF,0x34,0x20,0x46, ++0x30,0xBD,0x38,0xB5,0x0C,0x46,0x20,0x22, ++0x00,0x21,0x05,0x46,0x6B,0x46,0xFF,0xF7, ++0x56,0xFF,0x20,0x60,0x20,0x22,0x00,0x21, ++0x28,0x1D,0x6B,0x46,0xFF,0xF7,0x4F,0xFF, ++0x60,0x60,0x20,0x22,0x00,0x21,0x6B,0x46, ++0x05,0xF1,0x08,0x00,0xFF,0xF7,0x47,0xFF, ++0xA0,0x60,0x00,0x21,0x28,0x7B,0x20,0x73, ++0x68,0x7B,0x60,0x73,0xA8,0x7B,0xA0,0x73, ++0x68,0x18,0x62,0x18,0x49,0x1C,0xC0,0x7B, ++0xC9,0xB2,0x10,0x29,0x10,0x74,0xF7,0xD3, ++0x38,0xBD,0x30,0xB5,0x04,0x46,0x0D,0x46, ++0x01,0x68,0x20,0x23,0x00,0x22,0x28,0x46, ++0xFF,0xF7,0xB0,0xFF,0x61,0x68,0x20,0x23, ++0x00,0x22,0x28,0x1D,0xFF,0xF7,0xAA,0xFF, ++0xA1,0x68,0x20,0x23,0x00,0x22,0x05,0xF1, ++0x08,0x00,0xFF,0xF7,0xA3,0xFF,0x20,0x7B, ++0x28,0x73,0x30,0xBD,0x10,0xB5,0x04,0x46, ++0x01,0x20,0xFA,0xF7,0xA9,0xFE,0x21,0x46, ++0xBD,0xE8,0x10,0x40,0xFA,0xF7,0xE6,0xB9, ++0x10,0xB5,0x04,0x46,0x00,0x20,0xFA,0xF7, ++0x9F,0xFE,0x21,0x46,0xBD,0xE8,0x10,0x40, ++0xFA,0xF7,0xDC,0xB9,0x8A,0xB2,0x02,0x60, ++0x09,0x0C,0x41,0x60,0x70,0x47,0x41,0x68, ++0x00,0x68,0x61,0xF3,0x1F,0x40,0x70,0x47, ++0x00,0x21,0x01,0x22,0x83,0x79,0x13,0x42, ++0x05,0xD0,0x83,0x79,0x93,0x43,0x83,0x71, ++0x49,0x1C,0x48,0xB2,0x70,0x47,0x49,0x1C, ++0x52,0x00,0x49,0xB2,0x01,0x29,0x52,0xB2, ++0xF0,0xDB,0x4F,0xF0,0xFF,0x30,0x70,0x47, ++0x8A,0x79,0x40,0x1E,0x01,0x23,0x83,0x40, ++0x1A,0x43,0x8A,0x71,0x70,0x47,0x00,0xEB, ++0x80,0x00,0x10,0xB5,0x02,0xEB,0xC0,0x00, ++0x90,0xF8,0x53,0x00,0x8A,0x07,0x04,0xD5, ++0x0C,0x22,0x08,0x28,0x05,0xD3,0x0D,0x22, ++0x03,0xE0,0x10,0x22,0x08,0x28,0x00,0xD3, ++0x11,0x22,0xC6,0x4B,0x13,0x44,0x1A,0x78, ++0x00,0xF0,0x07,0x04,0x01,0x20,0xA0,0x40, ++0xC9,0x07,0xC0,0xB2,0x01,0xD0,0x02,0x43, ++0x00,0xE0,0x82,0x43,0x1A,0x70,0x10,0xBD, ++0x2D,0xE9,0xFF,0x5F,0x0F,0x46,0x9A,0x46, ++0x00,0x98,0x00,0xEB,0x80,0x01,0x03,0xEB, ++0xC1,0x04,0xE0,0x6D,0xE1,0x6C,0x00,0xEB, ++0x01,0x08,0xA0,0x6C,0xE1,0x6C,0x4F,0xF0, ++0xFF,0x3C,0x45,0x1A,0x40,0x2D,0x04,0xD3, ++0x50,0x46,0xFF,0xF7,0xAD,0xFF,0x06,0x1E, ++0x03,0xDA,0x60,0x46,0x04,0xB0,0xBD,0xE8, ++0xF0,0x9F,0xB4,0xF8,0x42,0x00,0xA8,0x42, ++0x02,0xD2,0x47,0xF0,0x04,0x07,0x0E,0xE0, ++0xB8,0x07,0x06,0xD5,0xB4,0xF8,0x42,0x00, ++0xA8,0x42,0x08,0xD2,0xB4,0xF8,0x42,0x50, ++0x05,0xE0,0xB4,0xF8,0x44,0x00,0xA8,0x42, ++0x01,0xD2,0xB4,0xF8,0x44,0x50,0x94,0xF8, ++0x53,0x00,0x40,0xF2,0x01,0x61,0x47,0xEA, ++0x00,0x10,0x08,0x43,0x1F,0xFA,0x80,0xF9, ++0x40,0x46,0x00,0xF0,0xC7,0xFD,0xA0,0x49, ++0x01,0xEB,0x46,0x12,0x01,0x46,0x10,0x46, ++0xFF,0xF7,0x74,0xFF,0x9C,0x48,0xA9,0xB2, ++0x08,0x30,0x00,0xEB,0x46,0x10,0x01,0x60, ++0x29,0x0C,0x41,0x60,0xDF,0xF8,0x5C,0x82, ++0x98,0xF8,0x1C,0xB0,0x94,0xF8,0x53,0x00, ++0x88,0xF8,0x1C,0x00,0x17,0xF0,0x06,0x00, ++0x18,0xD0,0x02,0x28,0x22,0xD0,0x04,0x28, ++0x2A,0xD0,0x06,0x28,0x0A,0xD1,0x00,0x98, ++0x03,0x21,0x52,0x46,0xFF,0xF7,0x7B,0xFF, ++0x98,0xF8,0x25,0x00,0x40,0xF0,0x94,0x00, ++0x88,0xF8,0x25,0x00,0x88,0xF8,0x1C,0xB0, ++0x08,0xEB,0x46,0x11,0xA1,0xF8,0xE8,0x93, ++0x01,0x20,0xA7,0xE7,0x98,0xF8,0x2D,0x40, ++0x01,0x21,0x00,0x98,0x52,0x46,0xFF,0xF7, ++0x66,0xFF,0x24,0xF0,0xA8,0x00,0x88,0xF8, ++0x2D,0x00,0xEB,0xE7,0x00,0x98,0x03,0x21, ++0x52,0x46,0xFF,0xF7,0x5C,0xFF,0x98,0xF8, ++0x25,0x00,0x20,0xF0,0x94,0x00,0xDF,0xE7, ++0x98,0xF8,0x2D,0x70,0x08,0xEB,0x46,0x11, ++0xA1,0xF8,0xE8,0x93,0x01,0x21,0x00,0x98, ++0x52,0x46,0xFF,0xF7,0x4C,0xFF,0x9A,0xF8, ++0x2A,0x00,0x40,0x07,0x02,0xD5,0x47,0xF0, ++0xE8,0x00,0x01,0xE0,0x47,0xF0,0xA8,0x00, ++0x88,0xF8,0x2D,0x00,0x00,0x20,0x88,0xF8, ++0x2C,0x00,0x9A,0xF8,0x30,0x00,0xA8,0xB9, ++0xB8,0xF8,0x14,0x01,0x00,0xF4,0x00,0x50, ++0xA8,0xF8,0x14,0x01,0xB4,0xF8,0x42,0x10, ++0x28,0x46,0x02,0xF0,0x82,0xE9,0xB8,0xF8, ++0x14,0x11,0x08,0x43,0xA8,0xF8,0x14,0x01, ++0xB8,0xF8,0x14,0x01,0x40,0xF4,0x00,0x40, ++0xA8,0xF8,0x14,0x01,0x88,0xF8,0x1C,0xB0, ++0xB2,0xE7,0x60,0x49,0x01,0xEB,0x40,0x10, ++0xB0,0xF8,0xE8,0x13,0x21,0xF0,0x01,0x01, ++0xA0,0xF8,0xE8,0x13,0x70,0x47,0x5B,0x49, ++0x01,0xEB,0x40,0x10,0xB0,0xF8,0xE8,0x03, ++0x70,0x47,0x2D,0xE9,0xF8,0x4F,0x07,0x46, ++0xDF,0xF8,0x58,0x81,0x0D,0x46,0x08,0xEB, ++0x40,0x12,0x02,0xF5,0x7A,0x72,0xB2,0xF8, ++0x00,0x90,0x10,0x88,0x00,0xF0,0x0F,0x06, ++0x51,0x48,0x00,0xEB,0x47,0x10,0xFF,0xF7, ++0xDE,0xFE,0x82,0x46,0x4E,0x48,0x08,0x30, ++0x00,0xEB,0x47,0x10,0xFF,0xF7,0xD7,0xFE, ++0x00,0x90,0x10,0x88,0xC0,0xF3,0x03,0x1B, ++0x0B,0xEB,0x8B,0x00,0x05,0xEB,0xC0,0x04, ++0xE0,0x6D,0xE1,0x6C,0x08,0x44,0x00,0xF0, ++0x12,0xFD,0xE1,0x6C,0xAA,0xEB,0x00,0x00, ++0x08,0x44,0xE0,0x64,0x98,0xF8,0x1C,0xA0, ++0x94,0xF8,0x53,0x10,0x88,0xF8,0x1C,0x10, ++0x29,0x46,0x78,0xB2,0xFF,0xF7,0xD4,0xFE, ++0xB0,0x07,0x41,0x46,0x05,0xD5,0x11,0xF8, ++0x25,0x0F,0x20,0xF0,0x94,0x00,0x08,0x70, ++0x0C,0xE0,0x91,0xF8,0x2D,0x00,0x95,0xF8, ++0x2A,0x20,0x52,0x07,0x02,0xD5,0x20,0xF0, ++0xE8,0x00,0x01,0xE0,0x20,0xF0,0xA8,0x00, ++0x81,0xF8,0x2D,0x00,0x5F,0xEA,0xC9,0x50, ++0x08,0xD5,0xB1,0x07,0x4F,0xF0,0xEC,0x00, ++0x02,0xD5,0xE8,0x76,0xBD,0xE8,0xF8,0x8F, ++0xA8,0x76,0xFB,0xE7,0xB0,0x07,0x4F,0xF0, ++0x01,0x07,0x4F,0xF0,0x00,0x09,0x1C,0xD5, ++0xE0,0x6C,0xA1,0x6C,0x88,0x42,0x13,0xD1, ++0xB4,0xF8,0x42,0x10,0xE0,0x6C,0x02,0xF0, ++0xFC,0xE8,0x11,0xB1,0x84,0xF8,0x55,0x70, ++0x0A,0xE0,0x70,0x07,0x03,0xD5,0x84,0xF8, ++0x55,0x70,0x48,0x46,0xE1,0xE7,0x28,0x7F, ++0xC0,0xF3,0x01,0x10,0x02,0x28,0xF1,0xD0, ++0x88,0xF8,0x24,0x70,0x85,0xF8,0x1B,0x90, ++0x1E,0xE0,0x01,0x21,0x2A,0x46,0x58,0x46, ++0xFF,0xF7,0x91,0xFE,0x00,0x98,0xA4,0xF8, ++0x44,0x00,0xB4,0xF8,0x44,0x00,0x68,0xB9, ++0xB4,0xF8,0x42,0x10,0xE0,0x6C,0x02,0xF0, ++0xD8,0xE8,0x11,0xB1,0x84,0xF8,0x55,0x70, ++0x04,0xE0,0x70,0x07,0x02,0xD5,0x84,0xF8, ++0x55,0x70,0x18,0xE0,0x08,0xF1,0x2C,0x01, ++0x08,0x78,0x20,0xF0,0x01,0x00,0x08,0x70, ++0x88,0xF8,0x1C,0xA0,0xB0,0x07,0xB5,0xD4, ++0xB4,0xF8,0x44,0x00,0x10,0xB9,0x94,0xF8, ++0x55,0x00,0x18,0xB9,0xE0,0x6C,0xA1,0x6C, ++0x88,0x42,0xAB,0xD3,0x28,0x7F,0xC0,0xF3, ++0x01,0x10,0x01,0x28,0xA6,0xD0,0x48,0x46, ++0xA6,0xE7,0x00,0x00,0x00,0x40,0x00,0x25, ++0xF0,0x43,0x00,0x25,0x7C,0xB5,0x04,0x46, ++0x90,0xF8,0x2B,0x00,0x02,0x28,0x15,0xD1, ++0x40,0x22,0x00,0x23,0x02,0x21,0xCD,0xE9, ++0x00,0x24,0x1A,0x46,0x18,0x46,0xFA,0xF7, ++0x9B,0xFD,0x4F,0xF4,0x00,0x75,0x00,0x23, ++0xCD,0xE9,0x00,0x54,0x02,0x22,0x01,0x20, ++0x19,0x46,0xFA,0xF7,0x91,0xFD,0x23,0x46, ++0x2A,0x46,0x17,0xE0,0x94,0xF8,0x2B,0x00, ++0x01,0x28,0x1B,0xD1,0x40,0x22,0x00,0x23, ++0x02,0x21,0xCD,0xE9,0x00,0x24,0x1A,0x46, ++0x18,0x46,0xFA,0xF7,0x81,0xFD,0x40,0x22, ++0x00,0x23,0xCD,0xE9,0x00,0x24,0x02,0x22, ++0x01,0x20,0x19,0x46,0xFA,0xF7,0x78,0xFD, ++0x40,0x22,0x23,0x46,0xCD,0xE9,0x00,0x23, ++0x02,0x22,0x00,0x23,0x01,0x21,0x10,0x46, ++0xFA,0xF7,0x6E,0xFD,0x7C,0xBD,0x00,0xEB, ++0x80,0x02,0x70,0xB5,0x01,0xEB,0xC2,0x04, ++0x02,0x25,0xE3,0x6D,0x0A,0x46,0xC1,0xB2, ++0x18,0x46,0xFA,0xF7,0x89,0xFD,0x94,0xF8, ++0x55,0x00,0x18,0xB1,0x0A,0x25,0x02,0x20, ++0x84,0xF8,0x56,0x00,0x28,0x46,0x70,0xBD, ++0x2D,0xE9,0xF0,0x41,0x04,0x46,0x90,0xF8, ++0xE0,0x00,0x1E,0x25,0x4F,0xF0,0x01,0x06, ++0x10,0xF0,0x60,0x0F,0x17,0xD0,0x94,0xF8, ++0xE0,0x00,0xC0,0xF3,0x41,0x10,0x01,0x28, ++0x06,0xD1,0x94,0xF8,0xE1,0x00,0xFE,0x28, ++0x03,0xD0,0xFF,0x28,0xF8,0xD1,0xD2,0x25, ++0xA7,0xE1,0x26,0x66,0xE4,0x65,0x94,0xF8, ++0xE0,0x00,0x00,0xF0,0x1F,0x00,0x01,0x28, ++0xF6,0xD1,0x69,0x25,0x9D,0xE1,0x94,0xF8, ++0xE1,0x00,0x02,0x23,0xFF,0x4F,0x00,0x22, ++0x0C,0x28,0xED,0xD2,0xDF,0xE8,0x00,0xF0, ++0x06,0x35,0x4F,0x82,0x4F,0xF9,0xF8,0xF7, ++0xF6,0xF5,0xF4,0xF3,0x62,0x81,0xB4,0xF8, ++0xE6,0x00,0x20,0x66,0x04,0xF1,0x0A,0x00, ++0xE0,0x65,0x94,0xF8,0xE0,0x00,0xC0,0x06, ++0x08,0xD1,0x94,0xF8,0x22,0x00,0x00,0xB1, ++0x63,0x81,0x60,0x89,0x40,0xF0,0x01,0x00, ++0x60,0x81,0xDA,0xE7,0x94,0xF8,0xE0,0x00, ++0x00,0xF0,0x1F,0x00,0x01,0x28,0xD4,0xD0, ++0x94,0xF8,0xE0,0x00,0x00,0xF0,0x1F,0x00, ++0x02,0x28,0xC5,0xD1,0xB4,0xF8,0xE4,0x00, ++0x10,0xF0,0x0F,0x00,0xC0,0xD0,0x00,0xEB, ++0x80,0x00,0x04,0xEB,0xC0,0x00,0x90,0xF8, ++0x57,0x00,0x00,0x28,0xC1,0xD0,0x66,0x81, ++0xBF,0xE7,0x94,0xF8,0x27,0x00,0x03,0x28, ++0xB2,0xD3,0x94,0xF8,0xE0,0x00,0xC0,0x06, ++0x07,0xD1,0xB4,0xF8,0xE2,0x00,0xC0,0xB2, ++0x01,0x28,0xA9,0xD1,0x84,0xF8,0x22,0x20, ++0xA5,0xE7,0x94,0xF8,0xE0,0x00,0x00,0xF0, ++0x1F,0x00,0x01,0x28,0x04,0xD1,0x94,0xF8, ++0x27,0x00,0x04,0x28,0x9B,0xD0,0x44,0xE1, ++0x94,0xF8,0xE0,0x00,0x00,0xF0,0x1F,0x00, ++0x02,0x28,0x95,0xD1,0x94,0xF8,0x27,0x00, ++0x03,0x28,0x04,0xD1,0xB4,0xF8,0xE4,0x00, ++0x10,0xF0,0xFF,0x0F,0x8C,0xD1,0xB4,0xF8, ++0xE2,0x00,0x10,0xF0,0xFF,0x0F,0x87,0xD1, ++0xB4,0xF8,0xE4,0x00,0x10,0xF0,0x0F,0x00, ++0x81,0xD0,0x90,0x46,0x00,0xEB,0x80,0x00, ++0x04,0xEB,0xC0,0x05,0x53,0x35,0x2A,0x71, ++0x28,0x78,0xFA,0xF7,0xDB,0xFB,0x68,0x78, ++0x10,0xB1,0x80,0x20,0x2C,0x37,0x01,0xE0, ++0x40,0x20,0x24,0x37,0x38,0x70,0x87,0xF8, ++0x00,0x80,0x00,0x20,0xFA,0xF7,0xCE,0xFB, ++0x26,0x71,0x68,0xE7,0x94,0xF8,0x27,0x00, ++0x02,0x28,0xC8,0xD3,0x94,0xF8,0xE0,0x00, ++0xC0,0x06,0x26,0xD1,0xB4,0xF8,0xE2,0x00, ++0xC0,0xB2,0x01,0x28,0x02,0xD1,0x84,0xF8, ++0x22,0x60,0x58,0xE7,0xB4,0xF8,0xE2,0x00, ++0xC0,0xB2,0x02,0x28,0x03,0xD1,0xB4,0xF8, ++0xE4,0x00,0x20,0x81,0x4F,0xE7,0xB4,0xF8, ++0xE2,0x00,0xC0,0xB2,0x03,0x28,0x05,0xD1, ++0x60,0x79,0x00,0x28,0xAB,0xD0,0x84,0xF8, ++0x23,0x60,0x44,0xE7,0xB4,0xF8,0xE2,0x00, ++0xC0,0xB2,0x04,0x28,0xA3,0xD1,0x60,0x79, ++0x00,0x28,0xA0,0xD0,0x84,0xF8,0x24,0x60, ++0x39,0xE7,0x94,0xF8,0xE0,0x00,0x00,0xF0, ++0x1F,0x00,0x01,0x28,0x13,0xD1,0x94,0xF8, ++0x27,0x00,0x04,0x28,0x93,0xD1,0xB4,0xF8, ++0xE2,0x00,0xC0,0xB2,0x03,0x28,0xC0,0xD0, ++0xB4,0xF8,0xE2,0x00,0xC0,0xB2,0x04,0x28, ++0xBB,0xD0,0xB4,0xF8,0xE2,0x00,0xC0,0xB2, ++0x05,0x28,0xB6,0xD0,0xC9,0xE0,0x94,0xF8, ++0xE0,0x00,0x00,0xF0,0x1F,0x00,0x02,0x28, ++0xF8,0xD1,0x94,0xF8,0x27,0x00,0x03,0x28, ++0x04,0xD1,0xB4,0xF8,0xE4,0x00,0x10,0xF0, ++0xFF,0x0F,0xEF,0xD1,0xB4,0xF8,0xE2,0x00, ++0x10,0xF0,0xFF,0x0F,0xEA,0xD1,0xB4,0xF8, ++0xE4,0x00,0x10,0xF0,0x0F,0x00,0x9C,0xD0, ++0x00,0xEB,0x80,0x00,0x04,0xEB,0xC0,0x04, ++0x53,0x34,0x26,0x71,0x20,0x78,0xFA,0xF7, ++0x61,0xFB,0x60,0x78,0x50,0xB1,0x20,0x20, ++0x87,0xF8,0x2C,0x00,0x09,0xE0,0x98,0xE0, ++0x8C,0xE0,0x6F,0xE0,0x68,0xE0,0x5F,0xE0, ++0x19,0xE0,0x06,0xE0,0x10,0x20,0x87,0xF8, ++0x24,0x00,0x00,0x20,0xFA,0xF7,0x4E,0xFB, ++0xE9,0xE6,0xB4,0xF8,0xE2,0x00,0x7F,0x28, ++0x3D,0xD8,0xB4,0xF8,0xE2,0x00,0x84,0xF8, ++0x29,0x00,0x94,0xF8,0x27,0x00,0x02,0x28, ++0x8C,0xD1,0x94,0xF8,0x29,0x00,0x00,0x28, ++0x88,0xD0,0xE2,0x70,0xD7,0xE6,0xB4,0xF8, ++0xE2,0x00,0x01,0x0A,0x01,0x29,0x07,0xD0, ++0x02,0x29,0x05,0xD0,0x03,0x29,0x03,0xD0, ++0x06,0x29,0x01,0xD0,0x07,0x29,0x74,0xD1, ++0x94,0xF8,0x30,0x00,0x00,0x28,0x70,0xD1, ++0x04,0xF5,0xA0,0x70,0x41,0xC8,0x94,0xF8, ++0x2B,0x70,0x02,0x2F,0x05,0xD1,0x00,0xF8, ++0x52,0x2F,0x43,0x70,0xC2,0x71,0x03,0x72, ++0x52,0x38,0x00,0x28,0x61,0xD0,0x00,0x2E, ++0x5F,0xDD,0xB4,0xF8,0xE2,0x20,0xD2,0xB2, ++0x43,0x78,0x8B,0x42,0x02,0xD1,0x3A,0xB1, ++0x52,0x1E,0xD2,0xB2,0x03,0x78,0xF6,0x1A, ++0x18,0x44,0x00,0x2E,0xF4,0xDC,0x50,0xE0, ++0x00,0x2E,0x4E,0xDD,0x02,0x29,0x01,0xD0, ++0x07,0x29,0x04,0xD1,0xC2,0x78,0x81,0x78, ++0x01,0xEB,0x02,0x21,0x00,0xE0,0x01,0x78, ++0xB4,0xF8,0xE6,0x20,0x8A,0x42,0x01,0xDA, ++0xB4,0xF8,0xE6,0x10,0x21,0x66,0x32,0xE0, ++0xB4,0xF8,0xE6,0x10,0x04,0xF1,0xE8,0x00, ++0x21,0x66,0xE0,0x65,0xE1,0x25,0x34,0xE0, ++0xB4,0xF8,0xE6,0x00,0x20,0x66,0x04,0xF1, ++0x25,0x00,0x24,0xE0,0x94,0xF8,0x27,0x00, ++0x03,0x28,0x2A,0xD3,0xB4,0xF8,0xE2,0x00, ++0x10,0xF0,0xFF,0x0F,0x04,0xD1,0x03,0x20, ++0x21,0x46,0xF9,0xF7,0xFD,0xFD,0x76,0xE6, ++0xB4,0xF8,0xE2,0x00,0x10,0xF0,0xFF,0x0F, ++0x1B,0xD0,0xB4,0xF8,0xE2,0x00,0x84,0xF8, ++0x25,0x00,0x04,0x20,0x21,0x46,0xF9,0xF7, ++0xEF,0xFD,0x0E,0xE0,0x94,0xF8,0x27,0x00, ++0x04,0x28,0x0E,0xD1,0xB4,0xF8,0xE6,0x00, ++0x20,0x66,0x04,0xF1,0x26,0x00,0xE0,0x65, ++0x67,0xE6,0x94,0xF8,0x27,0x00,0x04,0x28, ++0x00,0xD1,0xD2,0x25,0x20,0x46,0xFF,0xF7, ++0xED,0xFD,0x28,0x46,0xBD,0xE8,0xF0,0x81, ++0x2D,0xE9,0xF0,0x4F,0x05,0x46,0x8F,0xB0, ++0x0C,0x46,0x38,0x22,0x2E,0xA1,0x68,0x46, ++0x00,0xF0,0xA4,0xEE,0x95,0xF9,0x09,0x80, ++0x00,0x26,0xFF,0x20,0x60,0x76,0x08,0xF0, ++0xFF,0x00,0x83,0x46,0xFA,0xF7,0xA2,0xFA, ++0x26,0x4F,0xB8,0xF1,0x00,0x0F,0x4F,0xF0, ++0x01,0x0A,0xB1,0x46,0x7E,0xD1,0x20,0x89, ++0x08,0x22,0x48,0xB3,0x20,0x89,0xB0,0xF5, ++0x80,0x7F,0x01,0xD1,0x02,0x20,0x78,0x77, ++0x20,0x89,0xB0,0xF5,0x00,0x7F,0x01,0xD1, ++0x04,0x20,0x78,0x77,0x20,0x89,0xB0,0xF5, ++0x40,0x7F,0x01,0xD1,0x87,0xF8,0x1D,0xA0, ++0x20,0x89,0xB0,0xF5,0x80,0x6F,0x11,0xD1, ++0x94,0xF8,0x53,0x00,0x15,0x49,0xEC,0x46, ++0x40,0x31,0x01,0xEB,0xC0,0x03,0x00,0x20, ++0x1C,0xF8,0x00,0x10,0x40,0x1C,0x35,0x28, ++0x19,0x70,0xF9,0xDB,0x02,0x20,0x87,0xF8, ++0x24,0x00,0x7A,0x77,0xA4,0xF8,0x08,0x90, ++0x28,0x88,0x40,0x07,0x04,0xD5,0x02,0x20, ++0x84,0xF8,0x56,0x00,0x87,0xF8,0x24,0x90, ++0x28,0x88,0xC0,0x06,0x05,0xD5,0x80,0x26, ++0x02,0x20,0x84,0xF8,0x56,0x00,0x87,0xF8, ++0x24,0x60,0x94,0xF8,0x56,0x00,0x02,0x28, ++0x74,0xD1,0x28,0x88,0xC0,0x07,0x66,0xD0, ++0x40,0x26,0x1D,0xE0,0x00,0x40,0x00,0x25, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, ++0xAA,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, ++0xEE,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0xBF,0xDF, ++0xEF,0xF7,0xFB,0xFD,0xFC,0x7E,0xBF,0xDF, ++0xEF,0xF7,0xFB,0xFD,0x7E,0x00,0x00,0x00, ++0x68,0x88,0xA4,0xF8,0x44,0x00,0xA2,0x64, ++0xC4,0xF8,0x4C,0x90,0x04,0xF1,0xE0,0x00, ++0x0E,0x90,0x00,0x21,0x22,0x46,0xFA,0xF7, ++0x42,0xFA,0x0E,0x98,0xF9,0xF7,0x65,0xFD, ++0x20,0x46,0xFF,0xF7,0xA9,0xFD,0xC0,0xB2, ++0x87,0xF8,0x1C,0x90,0xD2,0x28,0x12,0xD1, ++0x48,0x26,0x00,0xE0,0x68,0xE0,0xE0,0x78, ++0x60,0xB9,0x94,0xF8,0x29,0x00,0x48,0xB1, ++0x94,0xF8,0x27,0x00,0x03,0x28,0x2D,0xD2, ++0x03,0x20,0x21,0x46,0xF9,0xF7,0x30,0xFD, ++0x84,0xF8,0x03,0xA0,0x26,0xE0,0xE1,0x28, ++0x09,0xD1,0x87,0xF8,0x24,0x60,0x84,0xF8, ++0x56,0xA0,0xC4,0xF8,0x4C,0x90,0xB4,0xF8, ++0xE6,0x00,0xA0,0x64,0xCE,0xE0,0x69,0x28, ++0x0B,0xD1,0x87,0xF8,0x24,0x60,0x00,0x26, ++0x84,0xF8,0x56,0x90,0x84,0xF8,0x55,0x90, ++0xC4,0xF8,0x4C,0x90,0x20,0x6E,0xA0,0x64, ++0x0C,0xE0,0x60,0x26,0x0A,0xE0,0xE0,0x78, ++0x10,0xB1,0x94,0xF8,0x29,0x00,0x38,0x70, ++0x48,0x46,0x84,0xF8,0x03,0x90,0x21,0x79, ++0x01,0xB1,0x20,0x71,0x94,0xF8,0x56,0x00, ++0x20,0xB9,0x00,0x20,0x21,0x46,0xFF,0xF7, ++0x4E,0xFD,0x06,0x46,0x94,0xF8,0x56,0x00, ++0x01,0x28,0x18,0xD1,0x28,0x88,0xC0,0x07, ++0x15,0xD0,0x68,0x88,0xA4,0xF8,0x44,0x00, ++0xE0,0x6D,0x00,0x21,0x22,0x46,0xFA,0xF7, ++0xE6,0xF9,0xE0,0x6C,0xA1,0x6C,0x88,0x42, ++0x07,0xD3,0x08,0x20,0x02,0x21,0x84,0xF8, ++0x56,0x10,0x87,0xF8,0x1C,0x90,0x87,0xF8, ++0x24,0x00,0x40,0x20,0x8C,0xE0,0x00,0x2E, ++0x09,0xD0,0x87,0xF8,0x24,0x60,0x94,0xF8, ++0x23,0x00,0x00,0x28,0x03,0xD0,0x03,0x20, ++0x21,0x46,0xFA,0xF7,0x36,0xFA,0x81,0xE0, ++0x28,0x79,0xEC,0x21,0x01,0x28,0x28,0x88, ++0x5D,0xD1,0x42,0x06,0x01,0xD4,0xC0,0x07, ++0x03,0xD1,0x61,0x76,0x87,0xF8,0x2C,0x60, ++0x74,0xE0,0x08,0xEB,0x88,0x00,0x04,0xEB, ++0xC0,0x06,0x96,0xF8,0x57,0x00,0x18,0xB1, ++0x20,0x20,0x87,0xF8,0x2C,0x00,0x69,0xE0, ++0x68,0x88,0xA6,0xF8,0x44,0x00,0xB6,0xF8, ++0x44,0x00,0x1E,0x28,0x07,0xD0,0xB6,0xF8, ++0x44,0x00,0x1F,0x28,0x03,0xD0,0xB6,0xF8, ++0x44,0x00,0x20,0x28,0x33,0xD1,0xC6,0xF8, ++0x4C,0x90,0x69,0x88,0xB1,0x64,0x61,0x69, ++0xF1,0x65,0xC6,0xF8,0x60,0x90,0xB6,0xF8, ++0x44,0x00,0xB6,0xF8,0x42,0x10,0x88,0x42, ++0x06,0xD3,0xF1,0x6C,0xB6,0xF8,0x44,0x00, ++0x01,0x44,0xB0,0x6C,0x81,0x42,0x01,0xD3, ++0x50,0x46,0x00,0xE0,0x48,0x46,0x86,0xF8, ++0x55,0x00,0xF0,0x6D,0x22,0x46,0x59,0x46, ++0xFA,0xF7,0x85,0xF9,0xB6,0xF8,0x44,0x00, ++0x10,0xB9,0x96,0xF8,0x55,0x00,0x18,0xB9, ++0xF1,0x6C,0xB0,0x6C,0x81,0x42,0x01,0xD3, ++0x84,0xF8,0x19,0x90,0x38,0x8E,0x26,0xF8, ++0x44,0x0F,0x30,0x88,0x08,0xB9,0x87,0xF8, ++0x2C,0x90,0x50,0x46,0x05,0xE0,0xB6,0xF8, ++0x44,0x00,0x08,0xB1,0x84,0xF8,0x1E,0xA0, ++0x48,0x46,0x60,0x77,0x1E,0xE0,0x80,0x06, ++0x05,0xD5,0x61,0x76,0x87,0xF8,0x24,0x90, ++0x0F,0xB0,0xBD,0xE8,0xF0,0x8F,0x08,0xEB, ++0x88,0x00,0x04,0xEB,0xC0,0x00,0x90,0xF8, ++0x55,0x10,0x11,0xB1,0x84,0xF8,0x19,0x90, ++0x0C,0xE0,0x90,0xF8,0x57,0x10,0x09,0xB1, ++0x10,0x20,0x05,0xE0,0xC0,0x6D,0x22,0x46, ++0x59,0x46,0xFA,0xF7,0x39,0xFA,0x50,0x46, ++0x87,0xF8,0x24,0x00,0x60,0x7E,0xFF,0x28, ++0xE2,0xD0,0x08,0xEB,0x88,0x00,0x04,0xEB, ++0xC0,0x00,0x90,0xF8,0x52,0x10,0xC1,0xF3, ++0x01,0x11,0x01,0x29,0xD8,0xD0,0x80,0xF8, ++0x56,0x90,0xB0,0xF8,0x44,0x10,0x00,0x29, ++0xD2,0xD0,0xC0,0x6D,0x0F,0xB0,0x22,0x46, ++0x59,0x46,0xBD,0xE8,0xF0,0x4F,0xFA,0xF7, ++0x2E,0xB9,0x00,0x00,0x10,0xB5,0x04,0x46, ++0xFA,0xF7,0x66,0xF9,0x94,0xF8,0x2A,0x00, ++0xC0,0x07,0x04,0xD0,0x28,0x34,0xA0,0x78, ++0xC0,0x09,0x20,0x70,0x10,0xBD,0x02,0x20, ++0x84,0xF8,0x28,0x00,0x10,0xBD,0x70,0xB5, ++0x04,0x46,0x0D,0x46,0x28,0x46,0xFA,0xF7, ++0xFB,0xF9,0xEC,0x77,0x4C,0xB1,0x11,0x2C, ++0x01,0xD0,0x21,0x2C,0x0F,0xD1,0xFA,0xF7, ++0x83,0xF9,0x02,0x28,0x0B,0xDA,0x00,0x24, ++0xF0,0xE7,0x00,0x20,0x29,0x46,0xFA,0xF7, ++0x63,0xF9,0x29,0x46,0x00,0x20,0xBD,0xE8, ++0x70,0x40,0xFA,0xF7,0x43,0xB9,0x70,0xBD, ++0x00,0x22,0x10,0xB5,0x02,0x24,0x13,0x46, ++0x02,0xEB,0x82,0x01,0x00,0xEB,0xC1,0x01, ++0x44,0x31,0x8C,0x74,0x0B,0x80,0x4B,0x60, ++0x8B,0x60,0x4B,0x74,0xCB,0x74,0x52,0x1C, ++0xD2,0xB2,0x04,0x2A,0xF0,0xD3,0x10,0xBD, ++0x2D,0xE9,0xF0,0x41,0x05,0x46,0x42,0x4E, ++0x00,0x06,0x0C,0x46,0x09,0xD5,0x00,0x20, ++0x21,0x46,0xFF,0xF7,0xC4,0xFF,0x96,0xF8, ++0xC0,0x00,0x40,0xF0,0x01,0x00,0x86,0xF8, ++0xC0,0x00,0xE8,0x06,0x4F,0xF0,0x00,0x07, ++0x0B,0xD5,0x84,0xF8,0x29,0x70,0x94,0xF8, ++0x29,0x00,0x30,0x70,0x20,0x46,0xFF,0xF7, ++0xA1,0xFF,0x23,0x20,0x21,0x46,0xFF,0xF7, ++0xAE,0xFF,0xA8,0x06,0x4F,0xF0,0x7F,0x08, ++0x08,0xD5,0x04,0xF8,0x21,0x7F,0xA7,0x71, ++0x67,0x73,0xA7,0x73,0x04,0xF8,0x1B,0x8C, ++0x27,0x75,0x21,0x3C,0x68,0x07,0x4E,0xD5, ++0x20,0x46,0xFF,0xF7,0x8B,0xFF,0x94,0xF8, ++0x2A,0x00,0x40,0x07,0x20,0xD4,0x20,0x46, ++0xFF,0xF7,0xB2,0xFF,0x84,0xF8,0x06,0x80, ++0x84,0xF8,0x29,0x70,0x02,0x20,0x21,0x46, ++0xF9,0xF7,0xB2,0xFB,0x94,0xF8,0x20,0x00, ++0x18,0xB9,0x11,0x20,0x21,0x46,0xFF,0xF7, ++0x86,0xFF,0x20,0x46,0xFA,0xF7,0xD8,0xF8, ++0x20,0x7E,0xC1,0x06,0x4F,0xF0,0x01,0x00, ++0x03,0xD5,0x02,0x21,0x84,0xF8,0x2B,0x10, ++0x01,0xE0,0x84,0xF8,0x2B,0x00,0xE0,0x71, ++0x94,0xF8,0x30,0x00,0x00,0x28,0x22,0xD1, ++0x67,0x77,0x01,0x20,0xFF,0xF7,0xEB,0xFA, ++0x00,0xF0,0xFE,0x00,0xA6,0xF8,0x08,0x04, ++0xFA,0xF7,0xDA,0xF8,0xB6,0xF8,0x0C,0x01, ++0x40,0xF0,0x02,0x00,0xA6,0xF8,0x0C,0x01, ++0xB6,0xF8,0x14,0x01,0x40,0xF4,0xC0,0x40, ++0xA6,0xF8,0x14,0x01,0x94,0xF8,0x2B,0x00, ++0x01,0x28,0xB6,0xF8,0x14,0x01,0x02,0xD1, ++0x40,0xF0,0x80,0x00,0x01,0xE0,0x40,0xF0, ++0x10,0x00,0xA6,0xF8,0x14,0x01,0xBD,0xE8, ++0xF0,0x81,0xC0,0x7F,0x00,0xF0,0x0F,0x00, ++0x01,0x28,0x00,0xD0,0x00,0x20,0x70,0x47, ++0x00,0x40,0x00,0x25,0x70,0x47,0x70,0x47, ++0x1E,0xFF,0x2F,0xE1,0x70,0x40,0x2D,0xE9, ++0x03,0x40,0xA0,0xE1,0x02,0x50,0xA0,0xE1, ++0x01,0x30,0xA0,0xE1,0x00,0x20,0xA0,0xE1, ++0x00,0x00,0x54,0xE3,0x04,0xC0,0xA0,0x11, ++0x05,0xC0,0xA0,0x01,0x1C,0xEF,0x6F,0xE1, ++0x01,0x00,0x8E,0xE2,0x1C,0xC0,0xA0,0xE1, ++0x3F,0xE0,0x7E,0x12,0x1F,0xE0,0x7E,0x02, ++0x85,0x00,0x00,0x4A,0x00,0x00,0x53,0xE3, ++0x13,0x1F,0x6F,0x11,0x12,0x1F,0x6F,0x01, ++0x3F,0x10,0x71,0x12,0x1F,0x10,0x71,0x02, ++0x0E,0x60,0x51,0xE0,0x83,0x00,0x00,0x4A, ++0x04,0x00,0x76,0x52,0x84,0x00,0x00,0x5A, ++0x20,0x00,0x4E,0xE2,0x04,0x00,0x50,0xE3, ++0x35,0xC0,0x8C,0xD1,0x2C,0xCE,0xA0,0xE1, ++0x8F,0x1F,0x8F,0xE2,0x0C,0xC1,0x91,0xE7, ++0x1F,0x00,0x5E,0xE3,0x20,0xE0,0x4E,0x82, ++0x20,0x60,0x6E,0xE2,0x40,0x00,0x00,0x8A, ++0x9C,0x05,0x81,0xE0,0x11,0x16,0xA0,0xE1, ++0x30,0x1E,0x81,0xE1,0x10,0x06,0xA0,0xE1, ++0x00,0x00,0x70,0xE2,0x00,0x10,0xE1,0xE2, ++0x9C,0x01,0x81,0xE0,0x01,0xC0,0x8C,0xE0, ++0x9C,0x05,0x81,0xE0,0x11,0x16,0xA0,0xE1, ++0x30,0x1E,0x81,0xE1,0x10,0x06,0xA0,0xE1, ++0x00,0x00,0x70,0xE2,0x00,0x10,0xE1,0xE2, ++0x00,0x00,0x53,0xE3,0x9C,0x01,0x81,0xE0, ++0x01,0xC0,0x8C,0xE0,0x07,0x00,0x00,0x0A, ++0x9C,0x05,0x81,0xE0,0x11,0x16,0xA0,0xE1, ++0x30,0x1E,0x81,0xE1,0x10,0x06,0xA0,0xE1, ++0x00,0x00,0x70,0xE2,0x00,0x10,0xE1,0xE2, ++0x9C,0x01,0x81,0xE0,0x01,0xC0,0x8C,0xE0, ++0x9C,0x12,0x80,0xE0,0x00,0x10,0xA0,0xE3, ++0x9C,0x03,0xA1,0xE0,0x30,0x0E,0xA0,0xE1, ++0x11,0x06,0x80,0xE1,0x90,0x65,0x84,0xE0, ++0x31,0x1E,0xA0,0xE1,0x91,0x45,0x24,0xE0, ++0x06,0x20,0x52,0xE0,0x04,0x30,0xC3,0xE0, ++0x01,0x00,0x53,0xE3,0x05,0x00,0x52,0x31, ++0x70,0x80,0xBD,0x38,0x9C,0x42,0x86,0xE0, ++0x00,0x40,0xA0,0xE3,0x9C,0x63,0xA4,0xE0, ++0x00,0x30,0xA0,0xE3,0x20,0xC0,0x6E,0xE2, ++0x36,0x6E,0xA0,0xE1,0x14,0x6C,0x86,0xE1, ++0x34,0x4E,0xA0,0xE1,0x96,0xE5,0x8C,0xE0, ++0x06,0x00,0x90,0xE0,0x04,0x10,0xA1,0xE0, ++0x0E,0x20,0x42,0xE0,0x05,0x00,0x52,0xE1, ++0x70,0x80,0xBD,0x38,0x01,0x00,0x90,0xE2, ++0x00,0x10,0xA1,0xE2,0x05,0x20,0x42,0xE0, ++0x05,0xC0,0x52,0xE0,0x0C,0x20,0xA0,0x21, ++0x00,0x00,0xB0,0xE2,0x00,0x10,0xA1,0xE2, ++0x05,0xC0,0x52,0xE0,0x0C,0x20,0xA0,0x21, ++0x00,0x00,0xB0,0xE2,0x00,0x10,0xA1,0xE2, ++0x70,0x80,0xBD,0xE8,0x9C,0x15,0x80,0xE0, ++0x00,0x10,0xA0,0xE3,0x9C,0x04,0xA1,0xE0, ++0x11,0x16,0xA0,0xE1,0x30,0x1E,0x81,0xE1, ++0x10,0x06,0xA0,0xE1,0x00,0x00,0x70,0xE2, ++0x00,0x10,0xE1,0xE2,0x9C,0x01,0x81,0xE0, ++0x01,0xC0,0x8C,0xE0,0x9C,0x15,0x80,0xE0, ++0x00,0x10,0xA0,0xE3,0x9C,0x04,0xA1,0xE0, ++0x11,0x16,0xA0,0xE1,0x30,0x1E,0x81,0xE1, ++0x10,0x06,0xA0,0xE1,0x00,0x00,0x70,0xE2, ++0x00,0x10,0xE1,0xE2,0x9C,0x01,0x81,0xE0, ++0x01,0xC0,0x8C,0xE0,0x01,0xC0,0x4C,0xE2, ++0x9C,0x12,0x80,0xE0,0x00,0x10,0xA0,0xE3, ++0x9C,0x03,0xA1,0xE0,0x31,0x0E,0xA0,0xE1, ++0x90,0x65,0x81,0xE0,0x06,0x20,0x52,0xE0, ++0x90,0x14,0x21,0xE0,0x01,0x30,0xC3,0xE0, ++0x04,0x00,0x53,0xE1,0x05,0x00,0x52,0x01, ++0x00,0x10,0xA0,0x33,0x70,0x80,0xBD,0x38, ++0x9C,0x62,0x81,0xE0,0x00,0x60,0xA0,0xE3, ++0x9C,0x13,0xA6,0xE0,0x00,0x10,0xA0,0xE3, ++0x36,0x6E,0xA0,0xE1,0x96,0xE5,0x8C,0xE0, ++0x06,0x00,0x80,0xE0,0x0E,0x20,0x52,0xE0, ++0x96,0xC4,0x2E,0xE0,0x0E,0x30,0xC3,0xE0, ++0x04,0x00,0x53,0xE1,0x05,0x00,0x52,0x01, ++0x70,0x80,0xBD,0x38,0x01,0x00,0x80,0xE2, ++0x05,0x20,0x52,0xE0,0x04,0x30,0xC3,0xE0, ++0x70,0x80,0xBD,0xE8,0x0C,0x00,0x2D,0xE9, ++0x00,0x10,0xA0,0xE3,0x00,0x00,0xA0,0xE3, ++0x41,0x02,0x00,0xEB,0x7C,0x80,0xBD,0xE8, ++0x00,0x10,0xA0,0xE3,0x00,0x00,0xA0,0xE3, ++0x70,0x80,0xBD,0xE8,0x20,0xE0,0x66,0xE2, ++0x00,0x00,0xA0,0xE3,0x00,0x10,0xA0,0xE3, ++0x14,0x46,0xA0,0xE1,0x35,0x4E,0x84,0xE1, ++0x15,0x56,0xA0,0xE1,0x05,0xE0,0x52,0xE0, ++0x04,0xC0,0xD3,0xE0,0x00,0x00,0xA0,0xE0, ++0x0C,0x30,0xA0,0x21,0x0E,0x20,0xA0,0x21, ++0x01,0x60,0x56,0xE2,0x70,0x80,0xBD,0x38, ++0xA4,0x40,0xB0,0xE1,0x65,0x50,0xA0,0xE1, ++0xF5,0xFF,0xFF,0xEA,0xF0,0xF0,0xF0,0xF0, ++0xE3,0x38,0x8E,0xE3,0xE5,0x35,0x94,0xD7, ++0xCC,0xCC,0xCC,0xCC,0xC3,0x30,0x0C,0xC3, ++0xA2,0x8B,0x2E,0xBA,0xC8,0x42,0x16,0xB2, ++0xAA,0xAA,0xAA,0xAA,0x3D,0x0A,0xD7,0xA3, ++0x9D,0xD8,0x89,0x9D,0xED,0x25,0xB4,0x97, ++0x92,0x24,0x49,0x92,0x08,0xCB,0x3D,0x8D, ++0x88,0x88,0x88,0x88,0x42,0x08,0x21,0x84, ++0x00,0x00,0x00,0x80,0x7C,0xB5,0x0C,0x00, ++0x15,0x00,0x00,0x29,0x00,0x90,0x01,0xD0, ++0x00,0x19,0x40,0x1E,0x6A,0x46,0x07,0x49, ++0x79,0x44,0x01,0x90,0x28,0x00,0x00,0xF0, ++0x4A,0xFD,0x05,0x00,0x00,0x2C,0x03,0xD0, ++0x69,0x46,0x00,0x20,0x00,0xF0,0x56,0xFD, ++0x28,0x00,0x7C,0xBD,0xCB,0x0A,0x00,0x00, ++0x0F,0xB4,0x7C,0xB5,0x0C,0x00,0x09,0xAB, ++0x00,0x90,0x01,0xD0,0x00,0x19,0x40,0x1E, ++0x6A,0x46,0x09,0x49,0x79,0x44,0x01,0x90, ++0x08,0x98,0x00,0xF0,0x30,0xFD,0x05,0x00, ++0x00,0x2C,0x03,0xD0,0x69,0x46,0x00,0x20, ++0x00,0xF0,0x3C,0xFD,0x28,0x00,0x7C,0xBC, ++0x08,0xBC,0x04,0xB0,0x18,0x47,0x00,0x00, ++0x97,0x0A,0x00,0x00,0x9B,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0xF0,0xB5,0x15,0x00, ++0x1F,0xB4,0x82,0xB0,0x1E,0x00,0x02,0x98, ++0x00,0x68,0x00,0x05,0x02,0xD5,0x27,0x4F, ++0x7F,0x44,0x02,0xE0,0x25,0x4F,0x7F,0x44, ++0x0E,0x37,0x02,0x98,0x00,0x24,0x24,0x30, ++0x01,0x90,0x09,0xE0,0x28,0x07,0x01,0x99, ++0x00,0x0F,0x2D,0x09,0x38,0x5C,0x08,0x55, ++0x30,0x07,0x64,0x1C,0x05,0x43,0x36,0x09, ++0x00,0x23,0x31,0x00,0x28,0x00,0x59,0x40, ++0x58,0x40,0x08,0x43,0xEE,0xD1,0x02,0x98, ++0x3A,0x00,0x00,0x68,0x00,0x07,0x09,0xD5, ++0x03,0x98,0x70,0x28,0x02,0xD1,0x10,0x32, ++0x01,0x23,0x03,0xE0,0x00,0x2C,0x01,0xD0, ++0x11,0x32,0x02,0x23,0x02,0x98,0x21,0x00, ++0x00,0xF0,0x37,0xFC,0x07,0xB0,0xF0,0xBD, ++0x70,0xB5,0x04,0x00,0x0D,0x00,0x10,0x68, ++0x21,0x00,0x00,0xF0,0xFA,0xFB,0x02,0x00, ++0x00,0x23,0x29,0x00,0x20,0x00,0xFF,0xF7, ++0xB9,0xFF,0x70,0xBD,0xD2,0x1D,0xD3,0x08, ++0xDB,0x00,0x0C,0xCB,0xB2,0xE7,0x30,0xB4, ++0x03,0x68,0x20,0x24,0x12,0x68,0x23,0x43, ++0x03,0x60,0x08,0x23,0xC3,0x61,0x30,0xBC, ++0x00,0x23,0xA7,0xE7,0xA0,0x20,0x00,0x00, ++0xF3,0xB5,0x05,0x00,0x00,0x20,0x81,0xB0, ++0xBE,0xE0,0xE9,0x68,0x28,0x00,0x88,0x47, ++0x00,0x28,0x7E,0xD0,0x25,0x28,0x02,0xD0, ++0x6A,0x68,0xA9,0x68,0xB1,0xE0,0x5C,0x4F, ++0x00,0x26,0x7F,0x44,0xE9,0x68,0x28,0x00, ++0x88,0x47,0x04,0x00,0x20,0x28,0x08,0xDB, ++0x31,0x2C,0x06,0xD2,0x38,0x19,0x20,0x38, ++0x00,0x78,0x00,0x28,0x01,0xD0,0x06,0x43, ++0xF0,0xE7,0xB0,0x07,0x01,0xD5,0x04,0x20, ++0x86,0x43,0x00,0x20,0xE8,0x61,0x07,0x00, ++0xA8,0x61,0x2A,0x2C,0x11,0xD1,0x02,0x98, ++0xBA,0x00,0x52,0x19,0x02,0xC8,0x91,0x61, ++0x02,0x90,0xE9,0x68,0x28,0x00,0x88,0x47, ++0x04,0x00,0x01,0x2F,0x26,0xD1,0xE8,0x69, ++0x00,0x28,0x2E,0xDA,0x20,0x20,0x86,0x43, ++0x2B,0xE0,0x20,0x00,0x30,0x38,0x01,0x22, ++0x01,0x00,0x0A,0x28,0x18,0xD2,0x00,0x2A, ++0x16,0xD0,0xB8,0x00,0x40,0x19,0x00,0x90, ++0x81,0x61,0x07,0xE0,0x00,0x98,0x0A,0x21, ++0x80,0x69,0x48,0x43,0x00,0x99,0x00,0x19, ++0x30,0x38,0x88,0x61,0xE9,0x68,0x28,0x00, ++0x88,0x47,0x04,0x00,0x01,0x21,0x30,0x38, ++0x0A,0x28,0x01,0xD2,0x00,0x29,0xED,0xD1, ++0x01,0x2F,0x0A,0xD0,0x2E,0x2C,0x08,0xD1, ++0xE9,0x68,0x28,0x00,0x88,0x47,0x04,0x00, ++0x20,0x20,0x06,0x43,0x7F,0x1C,0x02,0x2F, ++0xBF,0xDB,0xA8,0x69,0x00,0x28,0x03,0xDA, ++0x40,0x42,0xA8,0x61,0x01,0x20,0x06,0x43, ++0xF0,0x07,0x01,0xD0,0x10,0x20,0x86,0x43, ++0x6C,0x2C,0x01,0xD0,0x68,0x2C,0x17,0xD1, ++0xE9,0x68,0x27,0x00,0x28,0x00,0x88,0x47, ++0x04,0x00,0xB8,0x42,0x0A,0xD1,0x80,0x20, ++0x6C,0x2F,0x00,0xD0,0xC0,0x00,0xE9,0x68, ++0x06,0x43,0x28,0x00,0x88,0x47,0x04,0x00, ++0x16,0xE0,0x3B,0xE0,0x40,0x20,0x6C,0x2F, ++0x00,0xD0,0x80,0x00,0x06,0x43,0x0F,0xE0, ++0x4C,0x2C,0x05,0xD0,0x6A,0x2C,0x03,0xD0, ++0x74,0x2C,0x01,0xD0,0x7A,0x2C,0x07,0xD1, ++0x00,0x20,0x4C,0x2C,0xE7,0xD0,0x80,0x20, ++0x6A,0x2C,0xE4,0xD0,0x00,0x20,0xE2,0xE7, ++0x00,0x2C,0x23,0xD0,0x20,0x00,0x41,0x38, ++0x19,0x28,0x03,0xD8,0x01,0x20,0xC0,0x02, ++0x06,0x43,0x20,0x34,0x2E,0x60,0x02,0x9A, ++0x21,0x00,0x28,0x00,0x16,0x00,0xF4,0xF7, ++0x06,0xED,0x00,0x28,0x0A,0xD0,0x01,0x28, ++0x02,0xD1,0x36,0x1D,0x02,0x96,0x4C,0xE7, ++0xF6,0x1D,0xF0,0x08,0xC0,0x00,0x08,0x30, ++0x02,0x90,0x46,0xE7,0x6A,0x68,0xA9,0x68, ++0x20,0x00,0x90,0x47,0x28,0x6A,0x40,0x1C, ++0x28,0x62,0x3E,0xE7,0x28,0x6A,0xFE,0xBD, ++0x06,0x20,0x00,0x00,0xF7,0xB5,0x82,0xB0, ++0x0F,0x00,0x02,0x9C,0x00,0x26,0x00,0xF0, ++0xD8,0xEA,0x01,0x90,0x00,0x68,0x00,0x90, ++0x25,0x78,0x64,0x1C,0x00,0x2D,0x05,0xD0, ++0x00,0xF0,0xC0,0xEA,0x00,0x68,0x40,0x5D, ++0xC0,0x07,0xF5,0xD1,0x2B,0x2D,0x06,0xD0, ++0x2D,0x2D,0x03,0xD1,0x01,0x20,0x80,0x02, ++0x06,0x43,0x00,0xE0,0x64,0x1E,0x01,0x98, ++0x00,0x21,0x01,0x60,0x04,0x9A,0x39,0x00, ++0x20,0x00,0x00,0xF0,0xE1,0xFC,0x01,0x00, ++0x00,0x2F,0x04,0xD0,0x38,0x68,0xA0,0x42, ++0x01,0xD1,0x02,0x98,0x38,0x60,0x01,0x98, ++0x00,0x68,0x02,0x28,0x05,0xD0,0x01,0x98, ++0x00,0x9A,0x02,0x60,0x48,0x42,0x72,0x05, ++0x00,0xD4,0x08,0x00,0x05,0xB0,0xF0,0xBD, ++0x03,0x00,0x0B,0x43,0xF0,0xB5,0x9B,0x07, ++0x28,0xD1,0x21,0x4E,0xF7,0x01,0x04,0x2A, ++0x24,0xD3,0x08,0xC8,0x10,0xC9,0x12,0x1F, ++0x9D,0x1B,0x9D,0x43,0x3D,0x40,0x01,0xD1, ++0xA3,0x42,0xF4,0xD0,0x18,0x06,0x21,0x06, ++0x00,0x0E,0x09,0x0E,0x40,0x1A,0x29,0x06, ++0x01,0x43,0x12,0xD1,0x18,0x04,0x21,0x04, ++0x00,0x0C,0x09,0x0C,0x40,0x1A,0x29,0x04, ++0x01,0x43,0x0A,0xD1,0x18,0x02,0x21,0x02, ++0x00,0x0A,0x09,0x0A,0x40,0x1A,0x29,0x02, ++0x01,0x43,0x02,0xD1,0x18,0x0E,0x21,0x0E, ++0x40,0x1A,0xF0,0xBD,0x00,0x2A,0x01,0xD1, ++0x00,0x20,0xF0,0xBD,0x03,0x78,0x0C,0x78, ++0x40,0x1C,0x49,0x1C,0x00,0x2B,0x0D,0xD0, ++0xA3,0x42,0x0B,0xD1,0x52,0x1E,0x09,0xD0, ++0x03,0x78,0x0C,0x78,0x40,0x1C,0x49,0x1C, ++0x00,0x2B,0x03,0xD0,0xA3,0x42,0x01,0xD1, ++0x52,0x1E,0xEB,0xD1,0x18,0x1B,0xF0,0xBD, ++0x01,0x01,0x01,0x01,0x30,0xB5,0x44,0x1C, ++0x05,0xE0,0x01,0x78,0x40,0x1C,0x00,0x29, ++0x01,0xD1,0x00,0x1B,0x30,0xBD,0x81,0x07, ++0xF7,0xD1,0x0A,0x4B,0xDD,0x01,0x04,0xC8, ++0xD1,0x1A,0x91,0x43,0x29,0x40,0xFA,0xD0, ++0x00,0x1B,0x0A,0x06,0x01,0xD0,0xC0,0x1E, ++0x30,0xBD,0x0A,0x04,0x01,0xD0,0x80,0x1E, ++0x30,0xBD,0x09,0x02,0xFC,0xD0,0x40,0x1E, ++0x30,0xBD,0x00,0x00,0x01,0x01,0x01,0x01, ++0xFF,0x30,0x02,0xE2,0x03,0x24,0x83,0xE1, ++0x02,0x28,0x82,0xE1,0x35,0x00,0x00,0xEA, ++0x03,0x00,0x52,0xE3,0x2A,0x00,0x00,0x9A, ++0x03,0xC0,0x10,0xE2,0x08,0x00,0x00,0x0A, ++0x01,0x30,0xD1,0xE4,0x02,0x00,0x5C,0xE3, ++0x0C,0x20,0x82,0xE0,0x01,0xC0,0xD1,0x94, ++0x01,0x30,0xC0,0xE4,0x01,0x30,0xD1,0x34, ++0x01,0xC0,0xC0,0x94,0x04,0x20,0x42,0xE2, ++0x01,0x30,0xC0,0x34,0x03,0x30,0x11,0xE2, ++0x4B,0x00,0x00,0x0A,0x04,0x20,0x52,0xE2, ++0x1B,0x00,0x00,0x3A,0x03,0xC0,0x31,0xE7, ++0x02,0x00,0x53,0xE3,0x08,0x00,0x00,0x0A, ++0x0F,0x00,0x00,0x8A,0x2C,0x34,0xA0,0xE1, ++0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2, ++0x0C,0x3C,0x83,0xE1,0x04,0x30,0x80,0xE4, ++0xF9,0xFF,0xFF,0x2A,0x01,0x10,0x81,0xE2, ++0x0F,0x00,0x00,0xEA,0x2C,0x38,0xA0,0xE1, ++0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2, ++0x0C,0x38,0x83,0xE1,0x04,0x30,0x80,0xE4, ++0xF9,0xFF,0xFF,0x2A,0x02,0x10,0x81,0xE2, ++0x07,0x00,0x00,0xEA,0x2C,0x3C,0xA0,0xE1, ++0x04,0xC0,0xB1,0xE5,0x04,0x20,0x52,0xE2, ++0x0C,0x34,0x83,0xE1,0x04,0x30,0x80,0xE4, ++0xF9,0xFF,0xFF,0x2A,0x03,0x10,0x81,0xE2, ++0x00,0x00,0xA0,0xE1,0x82,0x2F,0xB0,0xE1, ++0x01,0x30,0xD1,0x24,0x01,0xC0,0xD1,0x24, ++0x01,0x20,0xD1,0x44,0x01,0x30,0xC0,0x24, ++0x01,0xC0,0xC0,0x24,0x01,0x20,0xC0,0x44, ++0x1E,0xFF,0x2F,0xE1,0x00,0x20,0xA0,0xE3, ++0x04,0x00,0x51,0xE3,0x07,0x00,0x00,0x3A, ++0x03,0xC0,0x10,0xE2,0x0C,0x00,0x00,0x0A, ++0x04,0xC0,0x6C,0xE2,0x02,0x00,0x5C,0xE3, ++0x01,0x20,0xC0,0x14,0x0C,0x10,0x41,0xE0, ++0xB2,0x20,0xC0,0xA0,0x06,0x00,0x00,0xEA, ++0x81,0xCF,0xB0,0xE1,0x01,0x20,0xC0,0x24, ++0x01,0x20,0xC0,0x24,0x01,0x20,0xC0,0x44, ++0x1E,0xFF,0x2F,0xE1,0x78,0x47,0xC0,0x46, ++0x00,0x20,0xA0,0xE3,0x00,0x40,0x2D,0xE9, ++0x02,0x30,0xA0,0xE1,0x02,0xC0,0xA0,0xE1, ++0x02,0xE0,0xA0,0xE1,0x20,0x10,0x51,0xE2, ++0x0C,0x50,0xA0,0x28,0x0C,0x50,0xA0,0x28, ++0x20,0x10,0x51,0x22,0xFB,0xFF,0xFF,0x2A, ++0x01,0x1E,0xB0,0xE1,0x0C,0x50,0xA0,0x28, ++0x0C,0x00,0xA0,0x48,0x00,0x40,0xBD,0xE8, ++0x01,0x11,0xB0,0xE1,0x04,0x20,0x80,0x24, ++0x1E,0xFF,0x2F,0x01,0xB2,0x20,0xC0,0x40, ++0x01,0x01,0x11,0xE3,0x01,0x20,0xC0,0x14, ++0x1E,0xFF,0x2F,0xE1,0xF0,0x41,0x2D,0xE9, ++0x20,0x20,0x52,0xE2,0x0B,0x00,0x00,0x3A, ++0x80,0x00,0x52,0xE3,0x05,0x00,0x00,0x3A, ++0x80,0xF0,0xD1,0xF5,0xF8,0x51,0xB1,0xE8, ++0x20,0x20,0x42,0xE2,0x80,0x00,0x52,0xE3, ++0xF8,0x51,0xA0,0xE8,0xF9,0xFF,0xFF,0x2A, ++0xF8,0x51,0xB1,0xE8,0x20,0x20,0x52,0xE2, ++0xF8,0x51,0xA0,0xE8,0xFB,0xFF,0xFF,0x2A, ++0x02,0xCE,0xB0,0xE1,0x18,0x50,0xB1,0x28, ++0x18,0x50,0xA0,0x28,0x18,0x00,0xB1,0x48, ++0x18,0x00,0xA0,0x48,0xF0,0x41,0xBD,0xE8, ++0x02,0xCF,0xB0,0xE1,0x04,0x30,0x91,0x24, ++0x04,0x30,0x80,0x24,0x1E,0xFF,0x2F,0x01, ++0x82,0x2F,0xB0,0xE1,0xB2,0x30,0xD1,0x20, ++0x01,0x20,0xD1,0x44,0xB2,0x30,0xC0,0x20, ++0x01,0x20,0xC0,0x44,0x1E,0xFF,0x2F,0xE1, ++0x03,0x00,0x10,0xE3,0x03,0x00,0x11,0x03, ++0x17,0x00,0x00,0x1A,0x00,0x40,0x2D,0xE9, ++0x84,0xE0,0x9F,0xE5,0x04,0x20,0x90,0xE4, ++0x04,0x30,0x91,0xE4,0x0E,0xC0,0x42,0xE0, ++0x02,0xC0,0xCC,0xE1,0x8E,0xC3,0x1C,0xE0, ++0x03,0x00,0x52,0x01,0xF8,0xFF,0xFF,0x0A, ++0x00,0x40,0xBD,0xE8,0x03,0x0C,0xA0,0xE1, ++0x02,0x0C,0x50,0xE0,0xFF,0x0E,0x1C,0x03, ++0x07,0x00,0x00,0x1A,0x03,0x08,0xA0,0xE1, ++0x02,0x08,0x50,0xE0,0xFF,0x0C,0x1C,0x03, ++0x03,0x00,0x00,0x1A,0x03,0x04,0xA0,0xE1, ++0x02,0x04,0x50,0xE0,0xFF,0x08,0x1C,0x03, ++0x02,0x00,0x53,0x00,0x60,0x00,0xA0,0x11, ++0x1E,0xFF,0x2F,0xE1,0x01,0x20,0xD0,0xE4, ++0x01,0x30,0xD1,0xE4,0x01,0x00,0x52,0xE3, ++0x03,0x00,0x52,0x21,0x04,0x00,0x00,0x1A, ++0x01,0x20,0xD0,0xE4,0x01,0x30,0xD1,0xE4, ++0x01,0x00,0x52,0xE3,0x03,0x00,0x52,0x21, ++0xF5,0xFF,0xFF,0x0A,0x03,0x00,0x42,0xE0, ++0x1E,0xFF,0x2F,0xE1,0x01,0x01,0x01,0x01, ++0x01,0x20,0xD0,0xE5,0x00,0x10,0xD0,0xE5, ++0x02,0x30,0xD0,0xE5,0x03,0x00,0xD0,0xE5, ++0x02,0x14,0x81,0xE1,0x03,0x18,0x81,0xE1, ++0x00,0x0C,0x81,0xE1,0x1E,0xFF,0x2F,0xE1, ++0x20,0x24,0xA0,0xE1,0x00,0x00,0xC1,0xE5, ++0x01,0x20,0xC1,0xE5,0x20,0x28,0xA0,0xE1, ++0x02,0x20,0xC1,0xE5,0x20,0x2C,0xA0,0xE1, ++0x03,0x20,0xC1,0xE5,0x1E,0xFF,0x2F,0xE1, ++0x01,0x30,0x90,0xE1,0x21,0x00,0x00,0x4A, ++0x00,0x20,0xB0,0xE3,0xA0,0x30,0x71,0xE0, ++0x1A,0x00,0x00,0x3A,0x20,0x32,0x71,0xE0, ++0x0F,0x00,0x00,0x3A,0x20,0x34,0x71,0xE0, ++0x01,0x00,0x00,0x3A,0x00,0xC0,0xA0,0xE3, ++0x20,0x00,0x00,0xEA,0xA0,0x33,0x71,0xE0, ++0x81,0x03,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x20,0x33,0x71,0xE0,0x01,0x03,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0xA0,0x32,0x71,0xE0, ++0x81,0x02,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x20,0x32,0x71,0xE0,0x01,0x02,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0xA0,0x31,0x71,0xE0, ++0x81,0x01,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x20,0x31,0x71,0xE0,0x01,0x01,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0xA0,0x30,0x71,0xE0, ++0x81,0x00,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x01,0x10,0x50,0xE0,0x00,0x10,0xA0,0x31, ++0x02,0x00,0xA2,0xE0,0x1E,0xFF,0x2F,0xE1, ++0x02,0x21,0x11,0xE2,0x00,0x10,0x61,0x42, ++0x40,0xC0,0x32,0xE0,0x00,0x00,0x60,0x22, ++0x20,0x32,0x71,0xE0,0x1D,0x00,0x00,0x3A, ++0x20,0x34,0x71,0xE0,0x0F,0x00,0x00,0x3A, ++0x01,0x13,0xA0,0xE1,0x20,0x34,0x71,0xE0, ++0x3F,0x23,0x82,0xE3,0x0B,0x00,0x00,0x3A, ++0x01,0x13,0xA0,0xE1,0x20,0x34,0x71,0xE0, ++0x3F,0x26,0x82,0xE3,0x07,0x00,0x00,0x3A, ++0x01,0x13,0xA0,0xE1,0x20,0x34,0x71,0xE0, ++0x3F,0x29,0x82,0xE3,0x01,0x13,0xA0,0x21, ++0x3F,0x2C,0x82,0x23,0x00,0x30,0x71,0xE2, ++0x1D,0x00,0x00,0x2A,0x21,0x13,0xA0,0x21, ++0xA0,0x33,0x71,0xE0,0x81,0x03,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0x20,0x33,0x71,0xE0, ++0x01,0x03,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0xA0,0x32,0x71,0xE0,0x81,0x02,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0x20,0x32,0x71,0xE0, ++0x01,0x02,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0xA0,0x31,0x71,0xE0,0x81,0x01,0x40,0x20, ++0x02,0x20,0xB2,0xE0,0x20,0x31,0x71,0xE0, ++0x01,0x01,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0xEB,0xFF,0xFF,0x2A,0xA0,0x30,0x71,0xE0, ++0x81,0x00,0x40,0x20,0x02,0x20,0xB2,0xE0, ++0x01,0x10,0x50,0xE0,0x00,0x10,0xA0,0x31, ++0x02,0x00,0xA2,0xE0,0xCC,0xCF,0xB0,0xE1, ++0x00,0x00,0x60,0x42,0x00,0x10,0x61,0x22, ++0x1E,0xFF,0x2F,0xE1,0xCC,0xCF,0xB0,0xE1, ++0x00,0x00,0x60,0x42,0x01,0x40,0x2D,0xE9, ++0x00,0x00,0xB0,0xE3,0x05,0x00,0x00,0xEB, ++0x02,0x80,0xBD,0xE8,0x10,0x40,0x2D,0xE9, ++0x48,0x01,0x00,0xEB,0x04,0x00,0x90,0xE2, ++0x10,0x80,0xBD,0xE8,0xB8,0x16,0x00,0x00, ++0x40,0x01,0x00,0xEA,0x3F,0x01,0x00,0xEA, ++0x04,0x00,0x9F,0xE5,0x1E,0xFF,0x2F,0xE1, ++0x1E,0xFF,0x2F,0xE1,0x8C,0x17,0x03,0x20, ++0x70,0xB5,0x85,0x69,0x04,0x00,0x00,0x68, ++0x30,0x26,0xC1,0x06,0x00,0xD4,0x20,0x26, ++0xC0,0x07,0x09,0xD1,0x06,0xE0,0x62,0x68, ++0xA1,0x68,0x30,0x00,0x90,0x47,0x20,0x6A, ++0x40,0x1C,0x20,0x62,0x6D,0x1E,0xF6,0xD5, ++0x70,0xBD,0x70,0xB5,0x85,0x69,0x04,0x00, ++0x00,0x68,0xC0,0x07,0x09,0xD0,0x06,0xE0, ++0x62,0x68,0xA1,0x68,0x20,0x20,0x90,0x47, ++0x20,0x6A,0x40,0x1C,0x20,0x62,0x6D,0x1E, ++0xF6,0xD5,0x70,0xBD,0x09,0x68,0x4A,0x05, ++0x02,0xD5,0x00,0x06,0x00,0x16,0x70,0x47, ++0xC9,0x05,0xFC,0xD5,0x00,0x04,0x00,0x14, ++0x70,0x47,0x09,0x68,0x4A,0x05,0x02,0xD5, ++0x00,0x06,0x00,0x0E,0x70,0x47,0xC9,0x05, ++0xFC,0xD5,0x00,0x04,0x00,0x0C,0x70,0x47, ++0x70,0xB5,0x05,0x00,0x0C,0x00,0x01,0x2A, ++0x01,0xD1,0x01,0x20,0x0B,0xE0,0x28,0x68, ++0x80,0x06,0x00,0xD5,0xEA,0x69,0x00,0x20, ++0x00,0xE0,0x40,0x1C,0x90,0x42,0x02,0xD2, ++0x21,0x5C,0x00,0x29,0xF9,0xD1,0xA9,0x69, ++0x26,0x18,0x09,0x1A,0xA9,0x61,0x29,0x6A, ++0x09,0x18,0x28,0x00,0x29,0x62,0xFF,0xF7, ++0xA7,0xFF,0x04,0xE0,0x6A,0x68,0x20,0x78, ++0xA9,0x68,0x64,0x1C,0x90,0x47,0xB4,0x42, ++0xF8,0xD3,0x28,0x00,0xFF,0xF7,0xB1,0xFF, ++0x70,0xBD,0xFF,0xB5,0x04,0x00,0x81,0xB0, ++0x24,0x30,0x0D,0x00,0x00,0x90,0x21,0x68, ++0x88,0x06,0x04,0xD5,0x10,0x22,0xE0,0x69, ++0x91,0x43,0x21,0x60,0x00,0xE0,0x01,0x20, ++0x00,0x27,0xA8,0x42,0x00,0xDD,0x47,0x1B, ++0x04,0x98,0xA1,0x69,0x7A,0x19,0x10,0x18, ++0x08,0x1A,0xA0,0x61,0x20,0x68,0xC0,0x06, ++0x02,0xD4,0x20,0x00,0xFF,0xF7,0x7C,0xFF, ++0x00,0x26,0x08,0xE0,0x03,0x98,0x62,0x68, ++0xA1,0x68,0x80,0x5D,0x90,0x47,0x20,0x6A, ++0x40,0x1C,0x76,0x1C,0x20,0x62,0x04,0x98, ++0x86,0x42,0xF3,0xDB,0x20,0x68,0xC0,0x06, ++0x0A,0xD5,0x20,0x00,0xFF,0xF7,0x68,0xFF, ++0x06,0xE0,0x62,0x68,0xA1,0x68,0x30,0x20, ++0x90,0x47,0x20,0x6A,0x40,0x1C,0x20,0x62, ++0x38,0x00,0x7F,0x1E,0x00,0x28,0xF4,0xDC, ++0x07,0xE0,0x00,0x98,0x62,0x68,0xA1,0x68, ++0x40,0x5D,0x90,0x47,0x20,0x6A,0x40,0x1C, ++0x20,0x62,0x28,0x00,0x6D,0x1E,0x00,0x28, ++0xF3,0xDC,0x20,0x00,0xFF,0xF7,0x61,0xFF, ++0x21,0x68,0x02,0x20,0x09,0x06,0x00,0xD4, ++0x01,0x20,0x05,0xB0,0xF0,0xBD,0x00,0x00, ++0x01,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0xF7,0xB5,0x00,0x25,0x75,0x29,0x10,0x68, ++0x00,0x99,0x14,0xA6,0x11,0xD0,0xFF,0xF7, ++0x5D,0xFF,0x00,0x28,0x02,0xDA,0x40,0x42, ++0x11,0xA6,0x08,0xE0,0x00,0x99,0x09,0x68, ++0x8A,0x07,0x01,0xD5,0x0F,0xA6,0x02,0xE0, ++0x49,0x07,0x04,0xD5,0x0E,0xA6,0x01,0x25, ++0x01,0xE0,0xFF,0xF7,0x56,0xFF,0x00,0x9F, ++0x00,0x24,0x24,0x37,0x04,0xE0,0x00,0xF0, ++0x84,0xEC,0x30,0x31,0x39,0x55,0x64,0x1C, ++0x00,0x28,0xF8,0xD1,0x00,0x98,0x2B,0x00, ++0x32,0x00,0x21,0x00,0xFF,0xF7,0x79,0xFF, ++0xFE,0xBD,0x00,0x00,0x00,0x00,0x00,0x00, ++0x2D,0x00,0x00,0x00,0x2B,0x00,0x00,0x00, ++0x20,0x00,0x00,0x00,0x01,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0x11,0x68,0x02,0x68, ++0x00,0x6A,0x53,0x05,0x01,0xD5,0x08,0x70, ++0x0A,0xE0,0xD3,0x05,0x01,0xD5,0x08,0x80, ++0x06,0xE0,0x13,0x06,0x02,0xD5,0xC2,0x17, ++0x05,0xC1,0x01,0xE0,0x52,0x06,0x08,0x60, ++0x01,0x20,0x70,0x47,0x01,0x69,0x4A,0x1C, ++0x02,0x61,0x08,0x78,0x70,0x47,0x10,0xB5, ++0x90,0xB0,0x0C,0x00,0x03,0x92,0x00,0x22, ++0x06,0x92,0x05,0x4A,0x05,0x90,0x19,0x00, ++0x7A,0x44,0x01,0xA8,0x02,0x94,0x04,0x92, ++0xFF,0xF7,0x2E,0xFB,0x10,0xB0,0x10,0xBD, ++0xE1,0xFF,0xFF,0xFF,0x0A,0x68,0x10,0x70, ++0x52,0x1C,0x0A,0x60,0x70,0x47,0x4B,0x68, ++0x0A,0x68,0x9A,0x42,0x02,0xD2,0x53,0x1C, ++0x0B,0x60,0x10,0x70,0x70,0x47,0x00,0x00, ++0xF7,0xB5,0x04,0x00,0x15,0x00,0x2C,0x48, ++0x86,0xB0,0x78,0x44,0x00,0x27,0x03,0xC8, ++0x3E,0x00,0x03,0x90,0x04,0x91,0x11,0xE0, ++0x07,0x98,0x71,0x00,0x03,0xAA,0x41,0x5A, ++0x01,0xA8,0x00,0xF0,0xFB,0xFB,0x41,0x1C, ++0x07,0xD0,0x21,0x68,0x89,0x06,0x03,0xD5, ++0xE2,0x69,0x39,0x18,0x91,0x42,0x0E,0xD8, ++0x3F,0x18,0x76,0x1C,0x20,0x68,0x80,0x06, ++0x02,0xD5,0xE0,0x69,0xB8,0x42,0x06,0xDD, ++0xAE,0x42,0xE5,0xDB,0x07,0x98,0x71,0x00, ++0x40,0x5A,0x00,0x28,0xE0,0xD1,0xA0,0x69, ++0xC0,0x1B,0xA0,0x61,0x20,0x00,0xFF,0xF7, ++0x9B,0xFE,0x15,0x48,0x78,0x44,0x5A,0x38, ++0x03,0xC8,0x03,0x90,0x00,0x20,0x04,0x91, ++0x16,0xE0,0x41,0x00,0x07,0x98,0x03,0xAA, ++0x41,0x5A,0x01,0xA8,0x00,0xF0,0xCE,0xFB, ++0x00,0x90,0x40,0x1C,0x0A,0xD0,0x00,0x25, ++0x05,0xE0,0x62,0x68,0x01,0xA8,0xA1,0x68, ++0x40,0x5D,0x90,0x47,0x6D,0x1C,0x00,0x98, ++0x85,0x42,0xF6,0xD3,0x05,0x98,0x40,0x1C, ++0xB0,0x42,0x05,0x90,0xE5,0xDB,0x20,0x6A, ++0xC0,0x19,0x20,0x62,0x20,0x00,0xFF,0xF7, ++0x88,0xFE,0x09,0xB0,0xF0,0xBD,0x00,0x00, ++0x6A,0x16,0x00,0x00,0x01,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0xF7,0xB5,0xD2,0x1D, ++0x82,0xB0,0xD0,0x08,0x00,0x25,0xC0,0x00, ++0xF5,0x29,0xC0,0xC8,0x1A,0xA0,0x01,0x90, ++0x14,0xD0,0x00,0x23,0x39,0x00,0xF0,0x1A, ++0x99,0x41,0x04,0xDA,0x76,0x42,0x92,0x41, ++0xD7,0x1B,0x16,0xA0,0x08,0xE0,0x02,0x98, ++0x00,0x68,0x81,0x07,0x01,0xD5,0x14,0xA0, ++0x02,0xE0,0x40,0x07,0x02,0xD5,0x13,0xA0, ++0x01,0x25,0x01,0x90,0x02,0x98,0x00,0x24, ++0x24,0x30,0x00,0x90,0x09,0xE0,0x39,0x00, ++0x30,0x00,0x00,0xF0,0xCA,0xE8,0x00,0x9B, ++0x30,0x32,0x06,0x00,0x1A,0x55,0x64,0x1C, ++0x0F,0x00,0x00,0x23,0x39,0x00,0x30,0x00, ++0x59,0x40,0x58,0x40,0x08,0x43,0xEE,0xD1, ++0x01,0x9A,0x02,0x98,0x2B,0x00,0x21,0x00, ++0xFF,0xF7,0x93,0xFE,0x05,0xB0,0xF0,0xBD, ++0x00,0x00,0x00,0x00,0x2D,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00,0x20,0x00,0x00,0x00, ++0x57,0xC0,0x8F,0xE2,0x1C,0xFF,0x2F,0xE1, ++0xF8,0xB5,0x07,0x00,0x15,0x00,0x1E,0x00, ++0x00,0x24,0x24,0x30,0x00,0x90,0x09,0xE0, ++0x00,0x99,0x68,0x07,0xED,0x08,0x40,0x0F, ++0x30,0x30,0x08,0x55,0x70,0x07,0x64,0x1C, ++0x05,0x43,0xF6,0x08,0x00,0x23,0x31,0x00, ++0x28,0x00,0x59,0x40,0x58,0x40,0x08,0x43, ++0xEE,0xD1,0x38,0x68,0x10,0xA2,0x01,0x07, ++0x08,0xD5,0x20,0x21,0x08,0x40,0x20,0x43, ++0x04,0xD0,0xF8,0x69,0x01,0x23,0x0D,0xA2, ++0x40,0x1E,0xF8,0x61,0x21,0x00,0x38,0x00, ++0xFF,0xF7,0x5B,0xFE,0xF8,0xBD,0x10,0xB5, ++0x04,0x00,0x10,0x68,0x21,0x00,0xFF,0xF7, ++0x20,0xFE,0x02,0x00,0x00,0x23,0x20,0x00, ++0xFF,0xF7,0xCA,0xFF,0x10,0xBD,0xD2,0x1D, ++0xD1,0x08,0xC9,0x00,0x0C,0xC9,0xC3,0xE7, ++0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x00, ++0xF7,0xB5,0x82,0xB0,0x00,0x27,0x02,0x9C, ++0x15,0x00,0x20,0x78,0x64,0x1C,0x01,0x97, ++0x30,0x28,0x13,0xD1,0x20,0x78,0x01,0x27, ++0x64,0x1C,0x78,0x28,0x01,0xD0,0x58,0x28, ++0x08,0xD1,0x00,0x2D,0x01,0xD0,0x10,0x2D, ++0x0B,0xD1,0x20,0x78,0x00,0x27,0x10,0x25, ++0x64,0x1C,0x06,0xE0,0x00,0x2D,0x04,0xD1, ++0x08,0x25,0x02,0xE0,0x00,0x2D,0x00,0xD1, ++0x0A,0x25,0x00,0x26,0x00,0x96,0x11,0xE0, ++0x00,0x99,0x01,0x27,0x69,0x43,0x08,0x18, ++0x29,0x00,0x02,0x0C,0x71,0x43,0x00,0x04, ++0x00,0x0C,0x00,0x90,0x8E,0x18,0x38,0x04, ++0x86,0x42,0x01,0xD3,0x01,0x20,0x01,0x90, ++0x20,0x78,0x64,0x1C,0x29,0x00,0x00,0xF0, ++0xD8,0xFA,0x00,0x28,0xE8,0xDA,0x03,0x98, ++0x00,0x28,0x04,0xD0,0x64,0x1E,0x00,0x2F, ++0x00,0xD1,0x02,0x9C,0x04,0x60,0x01,0x98, ++0x00,0x28,0x06,0xD0,0xFF,0xF7,0x90,0xED, ++0x02,0x21,0x01,0x60,0xC8,0x1E,0x05,0xB0, ++0xF0,0xBD,0x00,0x99,0x30,0x04,0x08,0x43, ++0xF9,0xE7,0x00,0x00,0x00,0x00,0x9F,0xE5, ++0x1E,0xFF,0x2F,0xE1,0x8C,0x17,0x03,0x20, ++0x07,0x40,0x2D,0xE9,0x02,0x00,0xB0,0xE3, ++0xEA,0x01,0x00,0xFA,0x07,0x80,0xBD,0xE8, ++0x04,0x00,0x9F,0xE5,0x1E,0xFF,0x2F,0xE1, ++0x1E,0xFF,0x2F,0xE1,0xAC,0x17,0x03,0x20, ++0x30,0x40,0x2D,0xE9,0x0A,0x20,0x50,0xE2, ++0x20,0xE1,0xA0,0xE1,0x00,0x30,0xD1,0xE2, ++0x01,0xEF,0x8E,0xE1,0x0E,0x00,0x50,0xE0, ++0x21,0x11,0xC1,0xE0,0x20,0xE2,0xA0,0xE1, ++0x01,0xEE,0x8E,0xE1,0x0E,0x00,0x90,0xE0, ++0x21,0x12,0xA1,0xE0,0x20,0xE4,0xA0,0xE1, ++0x01,0xEC,0x8E,0xE1,0x0E,0x00,0x90,0xE0, ++0x21,0x14,0xA1,0xE0,0x20,0xE8,0xA0,0xE1, ++0x01,0xE8,0x8E,0xE1,0x0E,0x00,0x90,0xE0, ++0x21,0x18,0xA1,0xE0,0x01,0x00,0x90,0xE0, ++0x00,0x10,0xA1,0xE2,0xA0,0x01,0xA0,0xE1, ++0x81,0x0E,0x80,0xE1,0xA1,0x11,0xA0,0xE1, ++0x00,0x51,0x90,0xE0,0x01,0x41,0xA0,0xE1, ++0x20,0x4F,0x84,0xE1,0x01,0x40,0xA4,0xE0, ++0x05,0x50,0x95,0xE0,0x04,0x40,0xA4,0xE0, ++0x05,0x20,0x52,0xE0,0x04,0x30,0xD3,0xE0, ++0x00,0x30,0xA0,0xE3,0x0A,0x20,0x82,0x42, ++0x30,0x80,0xBD,0x48,0x01,0x00,0x90,0xE2, ++0x00,0x10,0xA1,0xE2,0x30,0x80,0xBD,0xE8, ++0x70,0x47,0xFF,0xB5,0x0C,0x00,0x8F,0xB0, ++0x50,0x68,0x11,0x68,0x09,0x90,0x46,0x00, ++0x08,0x91,0x75,0x0D,0x00,0xD1,0x6D,0x1E, ++0x00,0x21,0x08,0x00,0x01,0xF0,0xB4,0xE8, ++0x03,0x21,0x09,0x9A,0x89,0x05,0x08,0x40, ++0x00,0x2A,0x03,0xDA,0x82,0x00,0x80,0x18, ++0x40,0x08,0x08,0x40,0x80,0x0D,0x01,0x28, ++0x0A,0x90,0x02,0xDD,0x00,0x20,0xC0,0x43, ++0x0A,0x90,0x08,0x98,0x06,0x43,0x19,0xD1, ++0x18,0x98,0x01,0x28,0x03,0xD1,0x12,0x99, ++0x00,0x20,0xCA,0x43,0x09,0xE0,0x00,0x20, ++0x30,0x21,0x01,0xE0,0x21,0x54,0x40,0x1C, ++0x12,0x9A,0x90,0x42,0xFA,0xDB,0x10,0x00, ++0x00,0x22,0x18,0x9B,0x00,0x21,0x21,0x54, ++0x0F,0x99,0x8B,0x60,0x0A,0x60,0x48,0x60, ++0x13,0xB0,0xF0,0xBD,0xF0,0x48,0xF1,0x49, ++0x28,0x18,0x48,0x43,0x00,0x14,0x0C,0x90, ++0x0A,0x98,0x40,0x42,0x0D,0x90,0x18,0x98, ++0x00,0x28,0x04,0xD1,0x12,0x99,0x0C,0x98, ++0x45,0x1A,0x6D,0x1C,0x01,0xE0,0x12,0x98, ++0x45,0x42,0x0D,0x9A,0x00,0x2D,0x00,0xDC, ++0x0A,0x9A,0x29,0x1E,0x00,0xDA,0x69,0x42, ++0x03,0xA8,0x00,0xF0,0xBD,0xFA,0x08,0x99, ++0x09,0x98,0x00,0xF0,0x44,0xEB,0x01,0x91, ++0x01,0x00,0xE1,0x48,0x02,0x92,0x09,0x18, ++0x00,0x2D,0x00,0x91,0x0A,0xDD,0xDE,0x49, ++0x03,0x98,0x0A,0x9A,0x49,0x42,0x40,0x18, ++0x03,0xA9,0x03,0x90,0x68,0x46,0x00,0xF0, ++0xBE,0xED,0x07,0xE0,0x03,0x99,0x0A,0x9A, ++0x08,0x18,0x03,0xA9,0x03,0x90,0x68,0x46, ++0x00,0xF0,0xCC,0xED,0x00,0x90,0x00,0x04, ++0x02,0x92,0x01,0x91,0x03,0xD0,0x00,0x25, ++0xED,0x43,0x6E,0x08,0x01,0xE0,0x0E,0x00, ++0x15,0x00,0x18,0x98,0x00,0x28,0x26,0xD1, ++0x12,0x9F,0x07,0xE0,0x31,0x00,0x28,0x00, ++0xFF,0xF7,0x26,0xEF,0x30,0x32,0x05,0x00, ++0x0E,0x00,0xE2,0x55,0x7F,0x1E,0xF5,0xD5, ++0x12,0x98,0x00,0x23,0x31,0x00,0x07,0x90, ++0x28,0x00,0x01,0x27,0x59,0x40,0x58,0x40, ++0x08,0x43,0x03,0xD0,0x0C,0x98,0x00,0x27, ++0x40,0x1C,0x07,0xE0,0x20,0x78,0x30,0x28, ++0x01,0xD0,0x0C,0x98,0x03,0xE0,0x0C,0x98, ++0x00,0x27,0x40,0x1E,0x0C,0x90,0x00,0x2F, ++0x06,0x90,0x98,0xD0,0x35,0xE0,0x00,0x20, ++0x07,0x00,0x0B,0x90,0x0A,0xE0,0x11,0x2F, ++0x0F,0xDA,0x31,0x00,0x28,0x00,0xFF,0xF7, ++0xFC,0xEE,0x30,0x32,0x05,0x00,0x0E,0x00, ++0xE2,0x55,0x7F,0x1C,0x00,0x23,0x31,0x00, ++0x28,0x00,0x59,0x40,0x58,0x40,0x08,0x43, ++0xED,0xD1,0x00,0x23,0x31,0x00,0x28,0x00, ++0x59,0x40,0x58,0x40,0x08,0x43,0x10,0xD1, ++0x00,0x21,0x38,0x00,0x04,0xE0,0x23,0x5C, ++0x62,0x5C,0x63,0x54,0x49,0x1C,0x22,0x54, ++0x40,0x1E,0x81,0x42,0xF7,0xDB,0x12,0x98, ++0x07,0x97,0x38,0x1A,0x40,0x1E,0x06,0x90, ++0x07,0xE0,0x0B,0x98,0x00,0x28,0x04,0xD1, ++0x11,0x20,0x12,0x90,0x00,0x20,0x18,0x90, ++0x61,0xE7,0x07,0x9A,0x18,0x99,0x00,0x20, ++0xA0,0x54,0x0F,0x98,0x81,0x60,0x07,0x99, ++0x41,0x60,0x06,0x99,0x01,0x60,0x4B,0xE7, ++0xF0,0xB5,0xD2,0x1D,0x04,0x00,0xD0,0x08, ++0x0D,0x00,0xC0,0x00,0x95,0xB0,0x01,0x68, ++0x40,0x68,0x02,0x91,0x01,0x00,0x03,0x90, ++0x02,0x98,0x00,0xF0,0x64,0xEF,0x02,0x00, ++0x03,0x98,0xC1,0x0F,0x2D,0x20,0x00,0x29, ++0x06,0xD1,0x21,0x68,0x2B,0x20,0x8B,0x07, ++0x02,0xD4,0x48,0x07,0xC0,0x0F,0x40,0x01, ++0x03,0x2A,0x07,0x90,0x01,0xD0,0x07,0x2A, ++0x05,0xDB,0x03,0x00,0x29,0x00,0x20,0x00, ++0x00,0xF0,0xC0,0xF9,0x05,0xE1,0x20,0x68, ++0x80,0x06,0x01,0xD5,0xE7,0x69,0x00,0xE0, ++0x06,0x27,0x28,0x00,0x11,0x23,0x65,0x2D, ++0x1B,0xD0,0x66,0x28,0x26,0xD0,0x67,0x28, ++0x61,0xD1,0x01,0x2F,0x00,0xDA,0x01,0x27, ++0x00,0x22,0x11,0x2F,0x00,0x92,0x00,0xDC, ++0x3B,0x00,0x02,0xAA,0x0A,0xA9,0x12,0xA8, ++0xFF,0xF7,0xCF,0xFE,0x20,0x68,0x00,0x26, ++0x3D,0x00,0x00,0x07,0x35,0xD4,0x13,0x98, ++0xA8,0x42,0x00,0xDA,0x05,0x00,0x0A,0xA8, ++0x28,0xE0,0x00,0x22,0x11,0x2F,0x00,0x92, ++0x00,0xDA,0x7B,0x1C,0x02,0xAA,0x0A,0xA9, ++0x12,0xA8,0xFF,0xF7,0xBA,0xFE,0x00,0x26, ++0x7D,0x1C,0x27,0xE0,0x01,0x20,0x01,0x22, ++0xC0,0x07,0x00,0x92,0x04,0x90,0x3B,0x00, ++0x02,0xAA,0x0A,0xA9,0x12,0xA8,0xFF,0xF7, ++0xAC,0xFE,0x14,0x98,0x13,0x9D,0x00,0x26, ++0x00,0x28,0x02,0xD1,0x12,0x99,0x78,0x1C, ++0x0D,0x18,0x78,0x1B,0x02,0xD4,0x46,0x42, ++0x76,0x1E,0x7D,0x1C,0xE8,0x1B,0x05,0x90, ++0x21,0xE0,0x6D,0x1E,0x01,0x2D,0x04,0xDD, ++0x41,0x19,0x20,0x39,0xC9,0x7F,0x30,0x29, ++0xF7,0xD0,0x12,0x98,0xB8,0x42,0x01,0xDA, ++0x01,0x1D,0x03,0xDA,0x01,0x20,0x05,0x90, ++0x12,0x98,0x0F,0xE0,0x00,0x28,0x02,0xDC, ++0x86,0x19,0x2D,0x1A,0x04,0xE0,0x40,0x1C, ++0xA8,0x42,0x01,0xDD,0x12,0x9D,0x6D,0x1C, ++0x12,0x98,0x80,0x1B,0x40,0x1C,0x05,0x90, ++0x01,0x20,0xC0,0x07,0x04,0x90,0x20,0x68, ++0x00,0x07,0x05,0xD4,0x05,0x98,0xA8,0x42, ++0x02,0xDB,0x00,0x20,0xC0,0x43,0x05,0x90, ++0x08,0xAB,0x00,0x20,0xD8,0x71,0x04,0x98, ++0x01,0x21,0x09,0xAF,0x03,0x37,0xC9,0x07, ++0x88,0x42,0x24,0xD0,0x02,0x20,0x01,0x90, ++0x2B,0x20,0x00,0x90,0x04,0x98,0x00,0x28, ++0x0B,0xDA,0x40,0x42,0x04,0x90,0x2D,0x20, ++0x00,0x90,0x06,0xE0,0x04,0x98,0x00,0xF0, ++0xE8,0xE8,0x30,0x31,0x7F,0x1E,0x04,0x90, ++0x39,0x70,0x01,0x98,0x41,0x1E,0x00,0x28, ++0x01,0x91,0xF3,0xDC,0x04,0x98,0x00,0x28, ++0xF0,0xD1,0x00,0x98,0x7F,0x1E,0x38,0x70, ++0x21,0x68,0x45,0x20,0x09,0x05,0x00,0xD4, ++0x65,0x20,0x7F,0x1E,0x38,0x70,0x08,0xA8, ++0xC0,0x1B,0xC0,0x1D,0x06,0x90,0x07,0x98, ++0x00,0x28,0x00,0xD0,0x01,0x20,0x41,0x19, ++0x05,0x98,0xC0,0x17,0x09,0x18,0x06,0x98, ++0x08,0x18,0xA1,0x69,0x08,0x1A,0x40,0x1E, ++0xA0,0x61,0x20,0x68,0xC0,0x06,0x02,0xD4, ++0x20,0x00,0xFF,0xF7,0x55,0xFB,0x07,0x98, ++0x00,0x28,0x05,0xD0,0x62,0x68,0xA1,0x68, ++0x90,0x47,0x20,0x6A,0x40,0x1C,0x20,0x62, ++0x20,0x68,0xC0,0x06,0x24,0xD5,0x20,0x00, ++0xFF,0xF7,0x46,0xFB,0x20,0xE0,0x00,0x2E, ++0x07,0xDB,0x13,0x98,0xB0,0x42,0x04,0xDD, ++0x0A,0xA8,0x62,0x68,0x80,0x5D,0xA1,0x68, ++0x02,0xE0,0x62,0x68,0xA1,0x68,0x30,0x20, ++0x90,0x47,0x20,0x6A,0x76,0x1C,0x40,0x1C, ++0x20,0x62,0x05,0x98,0x40,0x1E,0x05,0x90, ++0x0A,0xD1,0xFF,0xF7,0xAE,0xED,0xC0,0x68, ++0x62,0x68,0x01,0x68,0x40,0x5C,0xA1,0x68, ++0x90,0x47,0x20,0x6A,0x40,0x1C,0x20,0x62, ++0x28,0x00,0x6D,0x1E,0x00,0x28,0xDA,0xDC, ++0x07,0xE0,0x62,0x68,0x38,0x78,0xA1,0x68, ++0x7F,0x1C,0x90,0x47,0x20,0x6A,0x40,0x1C, ++0x20,0x62,0x06,0x98,0x41,0x1E,0x00,0x28, ++0x06,0x91,0xF2,0xDC,0x20,0x00,0xFF,0xF7, ++0x24,0xFB,0x15,0xB0,0x02,0x20,0xF0,0xBD, ++0x01,0xFC,0xFF,0xFF,0x10,0x4D,0x00,0x00, ++0xE1,0xDF,0xFF,0xFF,0x17,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0x10,0xB5,0x43,0x69, ++0x00,0x2B,0x02,0xD0,0xAF,0xF3,0x00,0x80, ++0x01,0xE0,0xFF,0xF7,0x35,0xFB,0x01,0x20, ++0x10,0xBD,0x12,0x68,0x01,0x00,0x24,0x31, ++0x0A,0x70,0x00,0x22,0x4A,0x70,0x01,0x22, ++0xEC,0xE7,0x11,0x68,0x00,0x22,0xD2,0x43, ++0xE8,0xE7,0x00,0x00,0x17,0xC0,0x8F,0xE2, ++0x1C,0xFF,0x2F,0xE1,0x10,0xB5,0x43,0x69, ++0x00,0x2B,0x02,0xD0,0xAF,0xF3,0x00,0x80, ++0x01,0xE0,0xFF,0xF7,0x11,0xFC,0x01,0x20, ++0x10,0xBD,0x12,0x68,0x01,0x00,0x24,0x31, ++0x82,0x84,0x00,0x22,0xC2,0x84,0x01,0x22, ++0xEC,0xE7,0x11,0x68,0x00,0x22,0xD2,0x43, ++0xE8,0xE7,0x3A,0x28,0x00,0xD2,0x30,0x38, ++0x20,0x23,0x02,0x00,0x9A,0x43,0x41,0x2A, ++0x01,0xD3,0x10,0x00,0x37,0x38,0x00,0x22, ++0xD2,0x43,0x88,0x42,0x00,0xD2,0x02,0x00, ++0x10,0x00,0x70,0x47,0x70,0xB5,0x05,0x00, ++0x0C,0x00,0x16,0x00,0xFF,0xF7,0xA2,0xEA, ++0x00,0x68,0xFF,0x21,0x02,0x31,0x09,0x5C, ++0x01,0x29,0x0A,0xD1,0xFF,0x21,0x08,0x31, ++0x32,0x00,0x09,0x58,0x43,0x18,0xFF,0x33, ++0x08,0x33,0x21,0x00,0x28,0x00,0x98,0x47, ++0x70,0xBD,0xFF,0x2C,0x05,0xD8,0x00,0x5D, ++0x00,0x28,0x02,0xD0,0x01,0x20,0x2C,0x70, ++0x70,0xBD,0x00,0x20,0xC0,0x43,0x70,0xBD, ++0x0A,0x10,0x40,0xE2,0x20,0x01,0x40,0xE0, ++0x20,0x02,0x80,0xE0,0x20,0x04,0x80,0xE0, ++0x20,0x08,0x80,0xE0,0xA0,0x01,0xA0,0xE1, ++0x00,0x21,0x80,0xE0,0x82,0x10,0x51,0xE0, ++0x01,0x00,0x80,0x52,0x0A,0x10,0x81,0x42, ++0x1E,0xFF,0x2F,0xE1,0x0E,0x50,0xA0,0xE1, ++0x79,0xFE,0xFF,0xEB,0x05,0xE0,0xA0,0xE1, ++0x00,0x50,0xB0,0xE1,0x0D,0x10,0xA0,0xE1, ++0x0A,0x30,0xA0,0xE1,0x07,0x00,0xC0,0xE3, ++0x00,0xD0,0xA0,0xE1,0x60,0xD0,0x8D,0xE2, ++0x20,0x40,0x2D,0xE9,0x65,0x00,0x00,0xFA, ++0x20,0x40,0xBD,0xE8,0x00,0x60,0xA0,0xE3, ++0x00,0x70,0xA0,0xE3,0x00,0x80,0xA0,0xE3, ++0x00,0xB0,0xA0,0xE3,0x07,0x10,0xC1,0xE3, ++0x05,0xC0,0xA0,0xE1,0xC0,0x09,0xAC,0xE8, ++0xC0,0x09,0xAC,0xE8,0xC0,0x09,0xAC,0xE8, ++0xC0,0x09,0xAC,0xE8,0x01,0xD0,0xA0,0xE1, ++0x1E,0xFF,0x2F,0xE1,0xF8,0xB5,0x04,0x00, ++0x01,0x68,0x01,0x20,0x1F,0x00,0xC0,0x02, ++0x03,0x26,0x08,0x40,0x07,0x2A,0x04,0xDB, ++0x00,0x28,0x17,0xA5,0x05,0xD1,0x17,0xA5, ++0x03,0xE0,0x00,0x28,0x16,0xA5,0x00,0xD1, ++0x16,0xA5,0x10,0x20,0x81,0x43,0x21,0x60, ++0xA0,0x69,0xC0,0x1E,0x00,0x2F,0xA0,0x61, ++0x01,0xD0,0x40,0x1E,0xA0,0x61,0x20,0x00, ++0xFF,0xF7,0x36,0xFA,0x00,0x2F,0x01,0xD1, ++0x20,0x6A,0x06,0xE0,0x62,0x68,0xA1,0x68, ++0x38,0x00,0x90,0x47,0x20,0x6A,0x40,0x1C, ++0x20,0x62,0xC0,0x1C,0x20,0x62,0x04,0xE0, ++0x62,0x68,0x28,0x78,0xA1,0x68,0x6D,0x1C, ++0x90,0x47,0x76,0x1E,0xF8,0xD2,0x20,0x00, ++0xFF,0xF7,0x33,0xFA,0xF8,0xBD,0x00,0x00, ++0x4E,0x41,0x4E,0x00,0x6E,0x61,0x6E,0x00, ++0x49,0x4E,0x46,0x00,0x69,0x6E,0x66,0x00, ++0xF7,0xB5,0x08,0x00,0x17,0x00,0x2E,0x49, ++0x8A,0xB0,0x79,0x44,0x06,0xAC,0x2C,0xC9, ++0x2C,0xC4,0x2C,0xC9,0x37,0x21,0x03,0xAC, ++0xC9,0x01,0x40,0x18,0x2C,0xC4,0x37,0x21, ++0x1B,0x30,0xFF,0xF7,0x2E,0xE9,0x05,0x00, ++0x80,0x3D,0x0C,0x00,0x1B,0x3C,0x02,0xD5, ++0x64,0x42,0x01,0x20,0x00,0xE0,0x00,0x20, ++0x00,0x26,0x09,0x90,0x0F,0xE0,0xE0,0x07, ++0x0B,0xD0,0x0C,0x20,0x1E,0x49,0x70,0x43, ++0x79,0x44,0xBA,0x39,0x41,0x18,0x3A,0x00, ++0x06,0xA8,0x00,0xF0,0x04,0xEB,0x06,0xAB, ++0x07,0xC3,0x64,0x10,0x76,0x1C,0x00,0x2C, ++0xED,0xD1,0x6E,0x46,0x18,0xE0,0xE8,0x07, ++0x14,0xD0,0x15,0x48,0x21,0x01,0x78,0x44, ++0xA4,0x38,0x08,0x18,0x0E,0xC8,0x0E,0xC6, ++0x00,0x68,0x0C,0x3E,0xF8,0x42,0x02,0xD1, ++0x02,0x98,0xC0,0x19,0x02,0x90,0x69,0x46, ++0x3A,0x00,0x03,0xA8,0x00,0xF0,0xE6,0xEA, ++0x03,0xAB,0x07,0xC3,0x6D,0x10,0x64,0x1C, ++0x00,0x2D,0xE4,0xD1,0x09,0x98,0x00,0x28, ++0x05,0xD0,0x3A,0x00,0x06,0xA9,0x03,0xA8, ++0x00,0xF0,0xC0,0xEA,0x04,0xE0,0x3A,0x00, ++0x06,0xA9,0x03,0xA8,0x00,0xF0,0xD2,0xEA, ++0x0A,0x9B,0x07,0xC3,0x0D,0xB0,0xF0,0xBD, ++0x7E,0x0D,0x00,0x00,0x04,0x00,0xAF,0xF3, ++0x00,0x80,0x20,0x00,0xF3,0xF7,0x40,0xEC, ++0x01,0x00,0x10,0xB5,0x02,0x20,0x00,0xF0, ++0xB4,0xEC,0x10,0xBD,0x00,0xF0,0xCE,0xBC, ++0x01,0x48,0x02,0x4B,0x02,0x46,0x70,0x47, ++0x94,0xD4,0x02,0x20,0x94,0xE4,0x02,0x20, ++0x70,0x47,0x70,0x47,0x70,0x47,0x00,0x00, ++0x00,0x20,0xB0,0xE3,0x20,0x32,0x71,0xE0, ++0x75,0xFC,0xFF,0x3A,0x20,0x34,0x71,0xE0, ++0x67,0xFC,0xFF,0x3A,0x00,0xC0,0xA0,0xE3, ++0x86,0xFC,0xFF,0xEA,0x80,0xC0,0xB0,0xE1, ++0x00,0x00,0x31,0x03,0x2C,0x0A,0xA0,0xE1, ++0x0C,0x35,0xA0,0xE1,0x81,0x25,0xA0,0xE1, ++0x1E,0x0B,0x80,0x12,0xA1,0x1A,0x83,0xE1, ++0x60,0x00,0xA0,0xE1,0x02,0x11,0x81,0x13, ++0xCC,0xCA,0xB0,0xE1,0x17,0x00,0x00,0x0A, ++0x01,0x00,0x7C,0xE3,0x01,0x01,0x80,0x03, ++0x1E,0xFF,0x2F,0xE1,0x22,0x38,0xB0,0xE1, ++0x02,0x28,0xA0,0x01,0x10,0xC0,0xA0,0x03, ++0x00,0xC0,0xA0,0x13,0x1F,0x00,0x40,0xE2, ++0x22,0x3C,0xB0,0xE1,0x02,0x24,0xA0,0x01, ++0x08,0xC0,0x8C,0x02,0x22,0x3E,0xB0,0xE1, ++0x02,0x22,0xA0,0x01,0x04,0xC0,0x8C,0x02, ++0x22,0x3F,0xB0,0xE1,0x02,0x21,0xA0,0x01, ++0x02,0xC0,0x8C,0x02,0xA2,0x3F,0xB0,0xE1, ++0x82,0x20,0xA0,0x01,0x01,0xC0,0x8C,0x02, ++0x02,0x10,0xA0,0xE1,0x00,0x20,0xA0,0xE3, ++0x0C,0x00,0x40,0xE0,0x1E,0xFF,0x2F,0xE1, ++0x02,0x01,0x11,0xE3,0x1E,0xFF,0x2F,0x01, ++0x02,0x11,0xD1,0xE3,0xE6,0xFF,0xFF,0x0A, ++0x21,0x38,0xB0,0xE1,0x01,0x18,0xA0,0x01, ++0x10,0xC0,0xA0,0x03,0x00,0xC0,0xA0,0x13, ++0x21,0x3C,0xB0,0xE1,0x01,0x14,0xA0,0x01, ++0x08,0xC0,0x8C,0x02,0x21,0x3E,0xB0,0xE1, ++0x01,0x12,0xA0,0x01,0x04,0xC0,0x8C,0x02, ++0x21,0x3F,0xB0,0xE1,0x01,0x11,0xA0,0x01, ++0x02,0xC0,0x8C,0x02,0xA1,0x3F,0xB0,0xE1, ++0x01,0xC0,0x8C,0x02,0x20,0x30,0x6C,0xE2, ++0x81,0x10,0xA0,0x01,0x32,0x13,0x81,0xE1, ++0x12,0x2C,0xA0,0xE1,0x0C,0x00,0x40,0xE0, ++0x01,0x00,0x80,0xE2,0x1E,0xFF,0x2F,0xE1, ++0xFF,0xC4,0xC0,0xE3,0x03,0x00,0x20,0xE0, ++0xFF,0x74,0xC3,0xE3,0x07,0x30,0x4C,0xE0, ++0x3F,0x3C,0x83,0xE2,0x02,0x01,0x00,0xE2, ++0xFF,0x30,0x83,0xE2,0x80,0x49,0x2D,0xE9, ++0x22,0x6E,0x8F,0xE2,0x09,0x00,0x2D,0xE9, ++0x24,0x38,0xA0,0xE1,0x25,0xB8,0xA0,0xE1, ++0x23,0x64,0xD6,0xE7,0x0B,0xE8,0xC5,0xE1, ++0x03,0x88,0xC4,0xE1,0xA1,0x10,0xB0,0xE1, ++0x93,0x66,0x27,0xE0,0x62,0x20,0xB0,0xE1, ++0x02,0x01,0xA0,0x23,0x00,0x00,0xA0,0x33, ++0x02,0x75,0x67,0xE2,0x97,0x06,0x06,0xE0, ++0xA4,0x76,0xA0,0xE1,0xA6,0x69,0xA0,0xE1, ++0x02,0x60,0x86,0xE2,0x97,0x66,0x2C,0xE0, ++0x02,0xC2,0x6C,0xE2,0x2C,0x78,0xA0,0xE1, ++0x07,0xC8,0xCC,0xE1,0x97,0x06,0x04,0xE0, ++0x9C,0x06,0x05,0xE0,0xA1,0x77,0xA0,0xE1, ++0x25,0x68,0x84,0xE0,0x26,0x63,0xA0,0xE1, ++0x96,0x07,0x0C,0xE0,0x2C,0xC8,0xA0,0xE1, ++0x9C,0x0B,0x07,0xE0,0x0C,0x48,0xA0,0xE1, ++0x07,0x20,0x52,0xE0,0x93,0x0C,0x07,0xE0, ++0x07,0x10,0xC1,0xE0,0x9C,0x0E,0x07,0xE0, ++0x07,0x08,0x50,0xE0,0x27,0x28,0xD2,0xE0, ++0x9C,0x08,0x07,0xE0,0x07,0x28,0x42,0x30, ++0x07,0x28,0x52,0x20,0x27,0x18,0xC1,0xE0, ++0x21,0x71,0xA0,0xE1,0x96,0x07,0x0C,0xE0, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x87,0x09,0x50,0xE0,0xA7,0x26,0xD2,0xE0, ++0x93,0x0C,0x07,0xE0,0x87,0x29,0x42,0x30, ++0x87,0x29,0x52,0x20,0xA7,0x16,0xC1,0xE0, ++0x9C,0x0E,0x07,0xE0,0x8C,0x41,0x84,0xE0, ++0x87,0x01,0x50,0xE0,0xA7,0x2E,0xD2,0xE0, ++0x9C,0x08,0x07,0xE0,0x87,0x21,0x42,0x30, ++0x87,0x21,0x52,0x20,0xA7,0x1E,0xC1,0xE0, ++0x0C,0x70,0x9D,0xE5,0x01,0x1D,0xA0,0xE1, ++0x22,0x13,0x81,0xE1,0x02,0x2D,0xA0,0xE1, ++0xA1,0x77,0xA0,0xE1,0x20,0x23,0x82,0xE1, ++0x96,0x07,0x0C,0xE0,0x00,0x0D,0xA0,0xE1, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x0C,0x5B,0xA0,0xE1,0x2C,0x45,0x84,0xE0, ++0x07,0x20,0x52,0xE0,0x93,0x0C,0x07,0xE0, ++0x07,0x10,0xC1,0xE0,0x9C,0x0E,0x07,0xE0, ++0x07,0x08,0x50,0xE0,0x27,0x28,0xD2,0xE0, ++0x9C,0x08,0x07,0xE0,0x07,0x28,0x42,0x30, ++0x07,0x28,0x52,0x20,0x27,0x18,0xC1,0xE0, ++0x21,0x71,0xA0,0xE1,0x96,0x07,0x0C,0xE0, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x87,0x09,0x50,0xE0,0xA7,0x26,0xD2,0xE0, ++0x93,0x0C,0x07,0xE0,0x87,0x29,0x42,0x30, ++0x87,0x29,0x52,0x20,0xA7,0x16,0xC1,0xE0, ++0x9C,0x0E,0x07,0xE0,0x87,0x01,0x50,0xE0, ++0xA7,0x2E,0xD2,0xE0,0x9C,0x08,0x07,0xE0, ++0x87,0x21,0x42,0x30,0x87,0x21,0x52,0x20, ++0xA7,0x1E,0xC1,0xE0,0x01,0x1D,0xA0,0xE1, ++0x22,0x13,0x81,0xE1,0x8C,0x54,0x95,0xE0, ++0xA1,0x77,0xA0,0xE1,0x02,0x2D,0xA0,0xE1, ++0x96,0x07,0x0C,0xE0,0x20,0x23,0x82,0xE1, ++0x00,0x40,0xA4,0xE2,0x00,0x0D,0xA0,0xE1, ++0x2C,0xC8,0xA0,0xE1,0x9C,0x0B,0x07,0xE0, ++0x0C,0x6E,0xA0,0xE1,0x07,0x20,0x52,0xE0, ++0x93,0x0C,0x07,0xE0,0x07,0x10,0xC1,0xE0, ++0x9C,0x0E,0x07,0xE0,0x07,0x08,0x50,0xE0, ++0x27,0x28,0xD2,0xE0,0x9C,0x08,0x07,0xE0, ++0x07,0x28,0x42,0x30,0x07,0x28,0x52,0x20, ++0x27,0x18,0xC1,0xE0,0x2C,0x52,0x95,0xE0, ++0x01,0x17,0xA0,0xE1,0x22,0x19,0x81,0xE1, ++0x02,0x27,0xA0,0xE1,0x20,0x29,0x82,0xE1, ++0x00,0x07,0xA0,0xE1,0x00,0x40,0xA4,0xE2, ++0x03,0x38,0x88,0xE1,0x0B,0x88,0x8E,0xE1, ++0x00,0xE0,0xA0,0xE3,0x00,0xB0,0xA0,0xE3, ++0x08,0xC0,0x52,0xE0,0x03,0x70,0xD1,0xE0, ++0x0E,0xE0,0xAE,0xE0,0x0C,0x20,0xA0,0x21, ++0x07,0x10,0xA0,0x21,0x00,0x00,0x90,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xB1,0xE0, ++0x0B,0xB0,0xAB,0xE0,0x08,0xC0,0x52,0xE0, ++0x03,0x70,0xD1,0xE0,0x00,0xB0,0xDB,0xE2, ++0x00,0xB0,0xA0,0xE3,0x0E,0xE0,0xAE,0xE0, ++0x0C,0x20,0xA0,0x21,0x07,0x10,0xA0,0x21, ++0x00,0x00,0x90,0xE0,0x02,0x20,0xB2,0xE0, ++0x01,0x10,0xB1,0xE0,0x0B,0xB0,0xAB,0xE0, ++0x08,0xC0,0x52,0xE0,0x03,0x70,0xD1,0xE0, ++0x00,0xB0,0xDB,0xE2,0x0C,0x20,0xA0,0x21, ++0x07,0x10,0xA0,0x21,0x0E,0xE0,0xAE,0xE0, ++0x02,0x70,0x91,0xE1,0x01,0x60,0x86,0x13, ++0x0E,0x6E,0x96,0xE0,0x00,0x20,0xB5,0xE2, ++0x00,0x10,0xB4,0xE2,0x89,0x01,0xBD,0x48, ++0x00,0x88,0xBD,0x48,0x06,0x60,0x96,0xE0, ++0x89,0x01,0xBD,0xE8,0x02,0x20,0xB2,0xE0, ++0x00,0x48,0xBD,0xE8,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x80,0x80,0x7F,0x7E,0x7D,0x7C,0x7B,0x7A, ++0x79,0x78,0x77,0x76,0x76,0x75,0x74,0x73, ++0x72,0x71,0x71,0x70,0x6F,0x6E,0x6E,0x6D, ++0x6C,0x6C,0x6B,0x6A,0x6A,0x69,0x68,0x68, ++0x67,0x66,0x66,0x65,0x64,0x64,0x63,0x63, ++0x62,0x61,0x61,0x60,0x60,0x5F,0x5F,0x5E, ++0x5E,0x5D,0x5D,0x5C,0x5C,0x5B,0x5B,0x5A, ++0x5A,0x59,0x59,0x58,0x58,0x57,0x57,0x56, ++0x56,0x55,0x55,0x55,0x54,0x54,0x53,0x53, ++0x52,0x52,0x52,0x51,0x51,0x50,0x50,0x50, ++0x4F,0x4F,0x4F,0x4E,0x4E,0x4D,0x4D,0x4D, ++0x4C,0x4C,0x4C,0x4B,0x4B,0x4B,0x4A,0x4A, ++0x4A,0x49,0x49,0x49,0x48,0x48,0x48,0x47, ++0x47,0x47,0x47,0x46,0x46,0x46,0x45,0x45, ++0x45,0x44,0x44,0x44,0x44,0x43,0x43,0x43, ++0x43,0x42,0x42,0x42,0x42,0x41,0x41,0x41, ++0x00,0x00,0x53,0xE3,0x16,0x00,0x00,0x4A, ++0x86,0x70,0xB0,0xE1,0x11,0x00,0x00,0x0A, ++0x1C,0x40,0x2D,0xE9,0x67,0x70,0xA0,0xE1, ++0x03,0x00,0x2D,0xE9,0x10,0x00,0xA0,0xE3, ++0x10,0x10,0xA0,0xE3,0x00,0x00,0xA0,0xE3, ++0x0F,0x00,0xBD,0xE8,0x01,0xB0,0x8B,0xE2, ++0x01,0x00,0x5B,0xE3,0x27,0x70,0xB0,0x01, ++0x10,0x40,0xBD,0xE8,0x01,0x20,0x92,0x22, ++0x01,0x10,0x91,0x22,0x02,0x11,0xA0,0x23, ++0x00,0x30,0xA3,0xE2,0x02,0x01,0x00,0xE2, ++0x00,0x00,0x83,0xE1,0x1E,0xFF,0x2F,0xE1, ++0xFB,0xFF,0xFF,0x3A,0xA2,0x70,0xB0,0xE1, ++0xEA,0xFF,0xFF,0xEA,0x06,0x68,0x86,0xE1, ++0x40,0x00,0x73,0xE3,0x26,0x68,0xA0,0xE1, ++0x0F,0x00,0x00,0xDA,0x20,0x00,0x73,0xE3, ++0x02,0x60,0x86,0xD1,0x01,0x20,0xA0,0xD1, ++0x00,0x10,0xA0,0xD3,0x20,0x30,0x83,0xD2, ++0x00,0x30,0x73,0xE2,0xDD,0xFF,0xFF,0x0A, ++0x06,0x68,0x86,0xE1,0x20,0x70,0x63,0xE2, ++0x26,0x68,0xA0,0xE1,0x12,0x67,0x86,0xE1, ++0x32,0x23,0xA0,0xE1,0x11,0x27,0x82,0xE1, ++0x31,0x13,0xA0,0xE1,0x00,0x30,0xA0,0xE3, ++0xD4,0xFF,0xFF,0xEA,0x02,0x60,0x86,0xE1, ++0x00,0x30,0xA0,0xE3,0x00,0x20,0xA0,0xE3, ++0x06,0x68,0x86,0xE1,0x26,0x68,0xA0,0xE1, ++0x01,0x60,0x86,0xE1,0x00,0x10,0xA0,0xE3, ++0x06,0x68,0x86,0xB1,0x26,0x68,0xA0,0xB1, ++0xCA,0xFF,0xFF,0xEA,0xC0,0x48,0x2D,0xE9, ++0x02,0xB0,0xA0,0xE1,0x30,0x00,0x2D,0xE9, ++0x38,0x00,0x91,0xE8,0x07,0x00,0x90,0xE8, ++0x80,0xC0,0xD1,0xE1,0x83,0xC0,0xD4,0x41, ++0x01,0x00,0x00,0x5A,0xED,0xFE,0xFF,0xEB, ++0xBE,0xFF,0xFF,0xEB,0xF0,0x00,0xBD,0xE8, ++0x00,0x88,0xBD,0xE8,0xC0,0x48,0x2D,0xE9, ++0x02,0xB0,0xA0,0xE1,0x30,0x00,0x2D,0xE9, ++0x38,0x00,0x91,0xE8,0x07,0x00,0x90,0xE8, ++0x01,0x01,0x10,0xE3,0x01,0x01,0x13,0x03, ++0x01,0x00,0x00,0x1A,0x02,0x00,0x00,0xEB, ++0xB2,0xFF,0xFF,0xEB,0xF0,0x00,0xBD,0xE8, ++0x00,0x88,0xBD,0xE8,0xFF,0x74,0xC0,0xE3, ++0x03,0x00,0x20,0xE0,0xFF,0xC4,0xC3,0xE3, ++0x0C,0x30,0x87,0xE0,0x3F,0x3C,0x43,0xE2, ++0x02,0x01,0x00,0xE2,0xFE,0x30,0x43,0xE2, ++0x00,0x00,0x32,0xE3,0x5D,0x00,0x00,0x0A, ++0x00,0x00,0x35,0xE3,0x3D,0x00,0x00,0x0A, ++0x01,0x49,0x2D,0xE9,0x21,0x08,0xA0,0xE1, ++0x24,0x68,0xA0,0xE1,0x00,0x88,0xC1,0xE1, ++0x90,0x06,0x0C,0xE0,0x06,0x78,0xC4,0xE1, ++0x98,0x06,0x06,0xE0,0x97,0x08,0x08,0xE0, ++0x90,0x07,0x07,0xE0,0x06,0x88,0x98,0xE0, ++0x26,0xC8,0xAC,0xE0,0x22,0xB8,0xA0,0xE1, ++0x07,0x88,0x98,0xE0,0x25,0x68,0xA0,0xE1, ++0x27,0x08,0xAC,0xE0,0x0B,0xE8,0xC2,0xE1, ++0x9B,0x06,0x0C,0xE0,0x06,0x78,0xC5,0xE1, ++0x9E,0x06,0x06,0xE0,0x97,0x0E,0x0E,0xE0, ++0x9B,0x07,0x07,0xE0,0x06,0xE8,0x9E,0xE0, ++0x26,0xC8,0xAC,0xE0,0x00,0x60,0xA0,0xE3, ++0x07,0xE8,0x9E,0xE0,0x27,0xB8,0xAC,0xE0, ++0x0B,0x80,0x98,0xE0,0x00,0x00,0xA0,0xE2, ++0x0E,0xB0,0x98,0xE0,0x00,0x80,0xB8,0xE0, ++0x00,0x00,0xA0,0xE2,0x02,0x70,0x51,0xE0, ++0x00,0x10,0xA0,0xE3,0x01,0x10,0xE0,0x31, ++0x05,0x60,0x44,0x30,0x04,0xC0,0x55,0x10, ++0x27,0x48,0xA0,0xE1,0x00,0x10,0xA0,0x03, ++0x07,0x60,0x46,0x30,0x04,0x58,0xC7,0xE1, ++0x2C,0x78,0xA0,0xE1,0x01,0x10,0xE0,0x31, ++0x94,0x67,0x22,0xE0,0x07,0xC8,0xCC,0xE1, ++0x95,0x07,0x07,0xE0,0x9C,0x05,0x06,0xE0, ++0x94,0x0C,0x0C,0xE0,0x07,0x68,0x96,0xE0, ++0x27,0x28,0xA2,0xE0,0x0C,0x68,0x96,0xE0, ++0x2C,0x28,0xA2,0xE0,0x06,0x60,0x9B,0xE0, ++0x0E,0xE1,0x8E,0xE1,0x02,0x20,0xB8,0xE0, ++0x01,0x10,0xB0,0xE0,0x2E,0x61,0x86,0xE1, ++0x01,0x89,0xBD,0x48,0x06,0x60,0x96,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x01,0x89,0xBD,0xE8, ++0x24,0x58,0xA0,0xE1,0x21,0x78,0xA0,0xE1, ++0x05,0x68,0xC4,0xE1,0x07,0xC8,0xC1,0xE1, ++0x95,0x07,0x04,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x01,0xE0,0x95,0x0C,0x0C,0xE0, ++0x07,0x18,0x91,0xE0,0x27,0x48,0xA4,0xE0, ++0x22,0x78,0xA0,0xE1,0x0C,0x18,0x91,0xE0, ++0x2C,0x48,0xA4,0xE0,0x07,0xC8,0xC2,0xE1, ++0x95,0x07,0x02,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x06,0xE0,0x95,0x0C,0x0C,0xE0, ++0x07,0x68,0x96,0xE0,0x27,0x28,0xA2,0xE0, ++0x0C,0x68,0x96,0xE0,0x2C,0x58,0xA2,0xE0, ++0x01,0x20,0x95,0xE0,0x00,0x10,0xB4,0xE2, ++0x1E,0xFF,0x2F,0x41,0x06,0x60,0x96,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x00,0x00,0x35,0xE3,0x1D,0x00,0x00,0x0A, ++0x21,0x28,0xA0,0xE1,0x24,0x78,0xA0,0xE1, ++0x02,0x68,0xC1,0xE1,0x07,0xC8,0xC4,0xE1, ++0x92,0x07,0x01,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x04,0xE0,0x92,0x0C,0x0C,0xE0, ++0x07,0x48,0x94,0xE0,0x27,0x18,0xA1,0xE0, ++0x25,0x78,0xA0,0xE1,0x0C,0x48,0x94,0xE0, ++0x2C,0x18,0xA1,0xE0,0x07,0xC8,0xC5,0xE1, ++0x92,0x07,0x05,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x06,0xE0,0x92,0x0C,0x0C,0xE0, ++0x07,0x68,0x96,0xE0,0x27,0x58,0xA5,0xE0, ++0x0C,0x68,0x96,0xE0,0x2C,0x28,0xA5,0xE0, ++0x04,0x20,0x92,0xE0,0x00,0x10,0xB1,0xE2, ++0x1E,0xFF,0x2F,0x41,0x06,0x60,0x96,0xE0, ++0x02,0x20,0xB2,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x24,0x58,0xA0,0xE1,0x21,0x78,0xA0,0xE1, ++0x05,0x68,0xC4,0xE1,0x07,0xC8,0xC1,0xE1, ++0x95,0x07,0x01,0xE0,0x96,0x07,0x07,0xE0, ++0x9C,0x06,0x02,0xE0,0x00,0x60,0xA0,0xE3, ++0x95,0x0C,0x0C,0xE0,0x07,0x28,0x92,0xE0, ++0x27,0x18,0xA1,0xE0,0x0C,0x28,0x92,0xE0, ++0x2C,0x18,0xB1,0xE0,0x1E,0xFF,0x2F,0x41, ++0x02,0x20,0x92,0xE0,0x01,0x10,0xA1,0xE0, ++0x01,0x30,0x43,0xE2,0x1E,0xFF,0x2F,0xE1, ++0x94,0x04,0x03,0x20,0x74,0xD2,0x02,0x20, ++0x74,0xD3,0x02,0x20,0x00,0x80,0x4F,0xE1, ++0x1F,0x90,0x08,0xE2,0x12,0x00,0x59,0xE3, ++0x02,0x00,0x00,0x1A,0x40,0x80,0x88,0xE3, ++0x08,0xF0,0x61,0xE1,0x04,0xF0,0x5E,0xE2, ++0x30,0xD0,0x1F,0xE5,0x00,0x41,0x0D,0xE9, ++0xD2,0x80,0xA0,0xE3,0x08,0xF0,0x21,0xE1, ++0x40,0xD0,0x1F,0xE5,0x00,0x60,0x1D,0xE9, ++0x0D,0xF0,0x6F,0xE1,0x4C,0xD0,0x1F,0xE5, ++0x3F,0x00,0x2D,0xE9,0x04,0x00,0x4E,0xE2, ++0x00,0x10,0x4F,0xE1,0x06,0x20,0xA0,0xE3, ++0x0D,0x30,0xA0,0xE1,0x00,0x40,0x0F,0xE1, ++0x1F,0x40,0xC4,0xE3,0x53,0x40,0x84,0xE3, ++0x04,0xF0,0x21,0xE1,0x0D,0x50,0xA0,0xE1, ++0x0E,0x40,0xA0,0xE1,0x37,0x00,0x2D,0xE9, ++0x0D,0x00,0xA0,0xE1,0x00,0x20,0x0F,0xE1, ++0xC0,0x10,0x81,0xE3,0x20,0x10,0xC1,0xE3, ++0x01,0xF0,0x21,0xE1,0x00,0x7F,0x20,0xE9, ++0x02,0xF0,0x21,0xE1,0x00,0xD0,0xA0,0xE1, ++0x3F,0x00,0x93,0xE8,0xFF,0x00,0x2D,0xE9, ++0x40,0x10,0x9D,0xE5,0x1F,0x10,0x01,0xE2, ++0x13,0x00,0x51,0xE3,0x4C,0x10,0x9D,0x05, ++0x34,0x10,0x8D,0x05,0x0D,0xB0,0xA0,0xE1, ++0x0B,0x00,0xA0,0xE1,0xB4,0xD0,0xFF,0xFA, ++0x00,0x40,0xA0,0xE1,0x01,0x00,0x70,0xE3, ++0x02,0x00,0x00,0x1A,0x0B,0x00,0xA0,0xE1, ++0xB9,0xD0,0xFF,0xFA,0x05,0x00,0x00,0xEA, ++0xD8,0x10,0x1F,0xE5,0x04,0x11,0x91,0xE7, ++0xE4,0x20,0x1F,0xE5,0x04,0x61,0x92,0xE7, ++0x0B,0x20,0xA0,0xE1,0x36,0xFF,0x2F,0xE1, ++0x40,0x00,0x9D,0xE5,0x1F,0x10,0x00,0xE2, ++0x13,0x00,0x51,0xE3,0x04,0x00,0x00,0x1A, ++0x20,0x00,0x10,0xE3,0x00,0xF0,0x6F,0x11, ++0xFF,0xFF,0xDD,0x18,0x00,0xF0,0x2F,0xE1, ++0xFF,0xFF,0x9D,0xE8,0x00,0xF0,0x6F,0xE1, ++0x20,0x20,0x8D,0xE2,0x00,0x10,0x0F,0xE1, ++0xC0,0x00,0x80,0xE3,0x20,0x00,0xC0,0xE3, ++0x00,0xF0,0x21,0xE1,0x00,0x7F,0x92,0xE8, ++0x01,0xF0,0x21,0xE1,0x4C,0x00,0x9D,0xE5, ++0x20,0x00,0x8D,0xE5,0x48,0x00,0x9D,0xE5, ++0x24,0x00,0x8D,0xE5,0x3C,0x00,0x9D,0xE5, ++0x28,0x00,0x8D,0xE5,0xFF,0xE0,0xDD,0xE8, ++0x0F,0x00,0x00,0xEA,0x04,0xF0,0x1F,0xE5, ++0x41,0xCC,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x0F,0xD8,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x5D,0xCC,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x03,0xDE,0x03,0x20,0x04,0xF0,0x1F,0xE5, ++0x3B,0xDE,0x03,0x20,0x78,0x47,0xC0,0x46, ++0x0D,0xD0,0xFF,0xEA,0x78,0x47,0xC0,0x46, ++0x0F,0xD0,0xFF,0xEA,0x78,0x47,0xC0,0x46, ++0x70,0x09,0xFF,0xEA,0x04,0xF0,0x1F,0xE5, ++0x00,0x00,0x00,0x00,0x04,0xF0,0x1F,0xE5, ++0x69,0xDB,0x03,0x20,0x81,0x10,0xA0,0xE1, ++0x81,0x05,0x90,0xE1,0x04,0x00,0xA0,0x13, ++0xA1,0x2A,0xB0,0xE1,0x14,0x20,0x9F,0xE5, ++0x01,0x00,0x80,0x13,0xA1,0x0A,0x52,0xE1, ++0x02,0x00,0x80,0x03,0x01,0x00,0x50,0xE3, ++0x05,0x00,0xA0,0x03,0x1E,0xFF,0x2F,0xE1, ++0xFF,0x07,0x00,0x00,0x10,0x40,0x2D,0xE9, ++0x00,0x00,0x51,0xE3,0x09,0x00,0x00,0x0A, ++0x00,0x00,0xD1,0xE5,0x00,0x00,0x50,0xE3, ++0x06,0x00,0x00,0x0A,0x20,0x00,0x9F,0xE5, ++0x00,0x00,0x8F,0xE0,0xAD,0xF9,0xFF,0xEB, ++0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A, ++0x00,0x00,0xB0,0xE3,0x10,0x80,0xBD,0xE8, ++0x08,0x00,0x9F,0xE5,0x00,0x00,0x8F,0xE0, ++0x10,0x80,0xBD,0xE8,0x18,0x03,0x00,0x00, ++0x04,0x03,0x00,0x00,0x10,0x40,0x2D,0xE9, ++0x00,0x00,0x51,0xE3,0x09,0x00,0x00,0x0A, ++0x00,0x00,0xD1,0xE5,0x00,0x00,0x50,0xE3, ++0x06,0x00,0x00,0x0A,0x20,0x00,0x9F,0xE5, ++0x00,0x00,0x8F,0xE0,0x9B,0xF9,0xFF,0xEB, ++0x00,0x00,0x50,0xE3,0x01,0x00,0x00,0x0A, ++0x00,0x00,0xB0,0xE3,0x10,0x80,0xBD,0xE8, ++0x08,0x00,0x9F,0xE5,0x00,0x00,0x8F,0xE0, ++0x10,0x80,0xBD,0xE8,0xE0,0x03,0x00,0x00, ++0xCC,0x03,0x00,0x00,0x1E,0xFF,0x2F,0xE1, ++0x00,0x00,0xA0,0xE3,0x1E,0xFF,0x2F,0xE1, ++0xC9,0xFF,0xFF,0xEA,0x64,0x77,0x6C,0x64, ++0x70,0x61,0x74,0x68,0x3D,0x30,0x78,0x25, ++0x78,0x2C,0x20,0x75,0x73,0x62,0x73,0x74, ++0x72,0x75,0x63,0x74,0x3D,0x30,0x78,0x25, ++0x78,0x2C,0x20,0x75,0x73,0x62,0x63,0x6D, ++0x64,0x6C,0x6F,0x6F,0x70,0x3D,0x30,0x78, ++0x25,0x78,0x2C,0x20,0x64,0x65,0x62,0x75, ++0x67,0x5F,0x6D,0x65,0x6D,0x5F,0x74,0x61, ++0x69,0x6C,0x3D,0x30,0x78,0x25,0x78,0x2C, ++0x20,0x62,0x6F,0x6F,0x74,0x73,0x74,0x72, ++0x61,0x70,0x2D,0x61,0x72,0x67,0x00,0x00, ++0xA1,0x35,0x03,0x20,0x1B,0x38,0x03,0x20, ++0x91,0x37,0x03,0x20,0xDF,0x37,0x03,0x20, ++0x1D,0x38,0x03,0x20,0x37,0x38,0x03,0x20, ++0xED,0x5F,0x03,0x20,0xE5,0x5F,0x03,0x20, ++0x00,0x04,0x00,0x08,0x18,0x08,0x18,0x00, ++0xC4,0x09,0xE2,0x04,0x71,0x02,0x38,0x01, ++0x9C,0x00,0x68,0x00,0x34,0x00,0x1A,0x00, ++0x0D,0x00,0x06,0x00,0x60,0x09,0x00,0x00, ++0xC0,0x12,0x00,0x00,0x80,0x25,0x00,0x00, ++0x00,0x4B,0x00,0x00,0x00,0x96,0x00,0x00, ++0x00,0xE1,0x00,0x00,0x00,0xC2,0x01,0x00, ++0x00,0x84,0x03,0x00,0x00,0x08,0x07,0x00, ++0x00,0x10,0x0E,0x00,0x00,0x00,0x00,0x00, ++0x07,0x00,0x00,0x00,0x05,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00, ++0x05,0x00,0x00,0x00,0x05,0x00,0x00,0x00, ++0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, ++0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00, ++0x02,0x00,0x00,0x00,0x03,0x00,0x00,0x00, ++0x04,0x00,0x00,0x00,0x05,0x00,0x00,0x00, ++0x06,0x00,0x00,0x00,0x07,0x00,0x00,0x00, ++0x4A,0x45,0x44,0x45,0x43,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x1B,0x7C,0x03,0x20, ++0x00,0x00,0x00,0x00,0x45,0x7E,0x03,0x20, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x92,0xED,0x03,0x20,0x48,0x44,0x00,0x20, ++0xA2,0xED,0x03,0x20,0x58,0x54,0x00,0x20, ++0x5C,0xED,0x03,0x20,0x58,0x44,0x00,0x00, ++0x6E,0xED,0x03,0x20,0x68,0x54,0x00,0x00, ++0x80,0xED,0x03,0x20,0x78,0x54,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x08,0x00,0x01,0x0A,0x00,0x00,0x02, ++0x10,0x00,0x03,0x00,0x30,0x31,0x32,0x33, ++0x34,0x35,0x36,0x37,0x38,0x39,0x41,0x42, ++0x43,0x44,0x45,0x46,0x40,0x30,0x58,0x00, ++0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, ++0x38,0x39,0x61,0x62,0x63,0x64,0x65,0x66, ++0x40,0x30,0x78,0x00,0x04,0x00,0x00,0x08, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02, ++0x00,0x01,0x00,0x00,0x10,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x40,0x00,0x00,0x00,0x00,0x00,0xA0, ++0x00,0x00,0x00,0x00,0x05,0x40,0x00,0x00, ++0x00,0x00,0x00,0xC8,0x00,0x00,0x00,0x00, ++0x0C,0x40,0x00,0x00,0x00,0x00,0x40,0x9C, ++0x00,0x00,0x00,0x00,0x19,0x40,0x00,0x00, ++0x00,0x20,0xBC,0xBE,0x00,0x00,0x00,0x00, ++0x34,0x40,0x00,0x00,0xBF,0xC9,0x1B,0x8E, ++0x00,0x00,0x00,0x04,0xB5,0x40,0x00,0x00, ++0x50,0x4B,0xCF,0xD0,0x66,0x07,0xE2,0xCF, ++0x01,0x00,0x00,0x00,0x6C,0x41,0x00,0x00, ++0x3E,0x82,0x51,0xAA,0xDF,0xEE,0xA7,0x34, ++0x01,0x00,0x00,0x00,0xD9,0x42,0x00,0x00, ++0xDC,0xB5,0xA0,0xE2,0x3A,0x30,0x1F,0x97, ++0xFF,0xFF,0xFF,0xFF,0xB4,0x45,0x00,0x00, ++0xFD,0x25,0xA0,0xC8,0xE9,0xA3,0xC1,0x4F, ++0xFF,0xFF,0xFF,0xFF,0xFF,0x3F,0x00,0x00, ++0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00, ++0xFF,0x3F,0x00,0x00,0x00,0x00,0x00,0x80, ++0x00,0x00,0x00,0x00,0x52,0x5F,0x53,0x45, ++0x51,0x55,0x45,0x4E,0x43,0x45,0x5F,0x30, ++0x30,0x34,0x41,0x33,0x30,0x00,0x52,0x5F, ++0x53,0x45,0x51,0x55,0x45,0x4E,0x43,0x45, ++0x5F,0x30,0x30,0x35,0x41,0x33,0x30,0x00, ++0x52,0x5F,0x53,0x45,0x51,0x55,0x45,0x4E, ++0x43,0x45,0x5F,0x30,0x30,0x36,0x41,0x33, ++0x30,0x00,0x52,0x5F,0x53,0x45,0x51,0x55, ++0x45,0x4E,0x43,0x45,0x5F,0x30,0x30,0x33, ++0x41,0x00,0x52,0x5F,0x53,0x45,0x51,0x55, ++0x45,0x4E,0x43,0x45,0x5F,0x30,0x30,0x34, ++0x41,0x00,0x00,0x00,0x10,0x01,0x00,0x00, ++0x43,0x00,0x00,0x00,0xF8,0xFF,0xFF,0xFF, ++0x00,0x40,0x40,0x40,0x40,0x40,0x40,0x40, ++0x40,0x40,0x41,0x41,0x41,0x41,0x41,0x40, ++0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, ++0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40, ++0x40,0x05,0x02,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02, ++0x02,0x20,0x20,0x20,0x20,0x20,0x20,0x20, ++0x20,0x20,0x20,0x02,0x02,0x02,0x02,0x02, ++0x02,0x02,0x90,0x90,0x90,0x90,0x90,0x90, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10,0x02,0x02,0x02,0x02, ++0x02,0x02,0x88,0x88,0x88,0x88,0x88,0x88, ++0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08,0x02,0x02,0x02,0x02, ++0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x1C,0x00,0x00,0x00, ++0x43,0x00,0x00,0x00,0xF8,0xFF,0xFF,0xFF, ++0x0C,0x00,0x00,0x00,0x0E,0x00,0x00,0x00, ++0x0F,0x00,0x00,0x00,0x2E,0x00,0x00,0x00, ++0x50,0x5B,0xE2,0x75,0xA4,0xA1,0xBA,0x71, ++0x57,0x63,0x9A,0xE4,0x3E,0xA6,0x00,0x0B, ++0x3D,0xC2,0x04,0xD9,0xBE,0xF5,0x2A,0x20, ++0x62,0xDA,0xC8,0xC2,0x54,0xCD,0x72,0x51, ++0xEB,0x59,0xD1,0xB0,0x86,0x83,0xC5,0x64, ++0xA0,0x5B,0x3E,0xBF,0x70,0xC9,0xF9,0x24, ++0x28,0xE1,0x5F,0xB6,0x0C,0x47,0x42,0x33, ++0x2F,0xF7,0xEC,0x86,0x33,0x1B,0x3D,0x3A, ++0x34,0xB5,0x8A,0xAC,0x80,0x01,0x6B,0xBC, ++0xFE,0x0E,0x7A,0xDE,0x2E,0xE1,0x84,0xA3, ++0x92,0x2D,0x16,0x40,0x7A,0x40,0x53,0x59, ++0x98,0x5E,0x74,0xF7,0xB5,0xAB,0x31,0xBB, ++0x7F,0xC4,0x6E,0xBE,0x5F,0x88,0x2E,0x05, ++0x0E,0x7F,0xA9,0x70,0xB2,0x2C,0x7B,0x29, ++0x66,0xF2,0xFB,0xBD,0xDF,0xF7,0x0F,0xF2, ++0x7A,0x6A,0xFD,0x24,0xA8,0x8C,0x3B,0x73, ++0x0B,0xD8,0x8B,0x83,0x8B,0x79,0x81,0xF0, ++0x1F,0xC5,0xD3,0x6F,0x3D,0xFE,0x8A,0xB8, ++0x45,0x1C,0xDD,0x10,0xB7,0x12,0xF9,0x2E, ++0x06,0xC9,0xBF,0xB8,0xC8,0xB7,0x6F,0x5F, ++0x24,0x5B,0xDB,0xC4,0x14,0x74,0xF5,0xA3, ++0xE3,0x4E,0x52,0x70,0x62,0x5E,0xA8,0x45, ++0xFB,0x3E,0x4C,0x94,0x7C,0xEF,0x46,0xE7, ++0x4F,0xB7,0xF7,0xBA,0xD0,0x0E,0x80,0x3D, ++0x86,0x68,0x85,0x80,0xEB,0xDC,0x6B,0xDD, ++0x3D,0xCA,0xE5,0x91,0x54,0xEB,0xCB,0x68, ++0x81,0xF6,0x4F,0xB4,0x88,0x10,0x71,0x9D, ++0x6D,0x26,0x32,0x6B,0x37,0x49,0xC4,0x5E, ++0x1F,0x57,0x68,0xC8,0x0C,0x3D,0x52,0x40, ++0x09,0xA9,0xEF,0x24,0x00,0xD4,0x5F,0x6E, ++0xE0,0x96,0x10,0xCE,0xB3,0x13,0x3C,0x32, ++0x9B,0xB4,0x78,0x00,0xB7,0x70,0x38,0x8E, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0x9B,0x30,0x36,0xE1,0xB0,0xFF,0x01,0x0D, ++0x58,0xA4,0xA4,0x09,0x02,0xE5,0x73,0xED, ++0x8F,0x7A,0xEC,0xDA,0xA4,0x30,0xA8,0xA3, ++0xF6,0x95,0x1C,0x9F,0xB9,0xB2,0x41,0x10, ++0x8A,0x9B,0x34,0x78,0x28,0x6E,0x88,0xED, ++0x66,0x0A,0xF9,0xDF,0xDD,0x84,0x1B,0x52, ++0x94,0x8B,0xF7,0xA2,0x2C,0xB9,0x6A,0xB8, ++0x0C,0x11,0x8C,0xB5,0x3B,0x40,0x52,0x43, ++0x30,0xEA,0xA7,0xBA,0xE4,0x11,0x55,0xEA, ++0xDA,0xD3,0x02,0x6F,0x94,0x41,0x91,0x20, ++0xA5,0x3F,0x4B,0x72,0xC8,0x2F,0x9B,0x11, ++0x30,0x80,0xEE,0x91,0x2C,0xC9,0x0D,0x8A, ++0xA8,0x1D,0x59,0x1B,0x5B,0xED,0xF5,0x5A, ++0x06,0x65,0x29,0x0C,0xFB,0xD6,0xCD,0xA4, ++0xFC,0x4F,0xD4,0x8B,0xB0,0x16,0x7F,0x01, ++0x70,0x7D,0x7F,0xFC,0x36,0xCE,0xA2,0xCD, ++0xDA,0xCF,0xFF,0xBB,0xA0,0x39,0x02,0x9C, ++0x62,0x0A,0xF7,0x71,0x63,0x01,0x26,0x6D, ++0x42,0xF6,0x77,0xBC,0x40,0x7D,0x9C,0x24, ++0x0B,0xD5,0xC5,0xF6,0xDF,0xBA,0xE7,0x86, ++0x30,0xC4,0xB3,0xAF,0x64,0xAD,0x76,0x65, ++0xE8,0xF3,0xDA,0xFC,0x55,0x84,0xFE,0xA3, ++0x81,0x0B,0xC6,0xF7,0xB4,0xD5,0x68,0x2F, ++0x5A,0xA9,0xC7,0xE2,0x9A,0x0F,0x7F,0x59, ++0xA5,0x93,0x93,0x44,0x73,0x50,0x8E,0x94, ++0x29,0x51,0xCE,0xA6,0x65,0xE4,0xC9,0x60, ++0xFF,0x73,0xD0,0x4B,0xB7,0x74,0xB1,0x03, ++0x15,0xAC,0x64,0x74,0xCD,0x53,0x86,0xE2, ++0xDD,0xA8,0x61,0x47,0x56,0x2B,0xA0,0x53, ++0x95,0xE8,0xFE,0xB3,0x76,0x6B,0x24,0xB1, ++0xD9,0x58,0xC1,0xB7,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x56,0xDB,0x80,0xB0, ++0xDD,0x58,0x41,0xB5,0x46,0x1B,0x3F,0xB6, ++0x10,0xE8,0xC1,0xB5,0x56,0x6B,0x23,0xB6, ++0xD5,0x78,0xFE,0xB3,0x54,0x2B,0xA0,0xB8, ++0xDD,0xF8,0x63,0x76,0x56,0x17,0x90,0x76, ++0x77,0x42,0xC8,0xDC,0xFC,0x81,0x0A,0x12, ++0x24,0x02,0xCB,0x17,0xD0,0x81,0x85,0x1B, ++0x77,0x0E,0x5B,0x14,0xFC,0x21,0x80,0x19, ++0x77,0xB2,0x40,0x1C,0xFD,0xF1,0x40,0x1B, ++0x7C,0x02,0x91,0x1D,0xFC,0x81,0x0A,0xE3, ++0x3C,0x02,0xCB,0x17,0xF3,0x81,0xB0,0x11, ++0x6F,0xE2,0x84,0x1E,0xFD,0x81,0x19,0x1A, ++0x74,0xF2,0x8C,0xEC,0xEF,0x7E,0x25,0x18, ++0x33,0x3F,0xCB,0xFC,0xA8,0xBC,0x0A,0xF9, ++0x77,0x32,0x7B,0x1F,0xFC,0xC1,0xBA,0x1A, ++0x77,0x52,0x7B,0x1F,0xFC,0xE1,0xBA,0x1A, ++0x67,0x22,0x99,0x1E,0x84,0x81,0xAB,0xD1, ++0x8B,0xFD,0x34,0x76,0x7E,0xAF,0xBA,0x18, ++0x47,0x02,0x6A,0xD4,0xFC,0xB1,0x8B,0xBC, ++0x69,0xFD,0xE4,0x1D,0x92,0x81,0x5B,0x1A, ++0x8B,0x0A,0xCB,0xF6,0x8C,0x81,0x5B,0x1A, ++0x34,0xC7,0x07,0x3A,0x56,0x4D,0x97,0xD6, ++0xBF,0xC1,0x07,0x3A,0x55,0x4D,0x97,0xD6, ++0xB9,0xC1,0x07,0x3A,0x57,0x4D,0x97,0xD6, ++0xBB,0xC1,0x07,0x3A,0x51,0x4D,0x97,0xD6, ++0xBB,0xCE,0xA7,0xD1,0x30,0x7D,0x56,0xD0, ++0x98,0xFA,0xB7,0xD1,0xB0,0x5D,0x47,0x16, ++0xD2,0xCE,0x56,0xD3,0xE0,0x45,0xC6,0x3F, ++0xDF,0xCE,0x56,0xD3,0xFE,0x45,0xC6,0x3F, ++0xCE,0xCE,0x56,0xD3,0xFC,0x45,0xC6,0x3F, ++0xD4,0xCE,0x56,0xD3,0x6A,0x44,0xC6,0x3F, ++0xC3,0xCE,0x56,0xD3,0x82,0x43,0xC6,0x3F, ++0x52,0xCE,0x56,0xD3,0x01,0x44,0xC6,0x3F, ++0x5F,0xCE,0x56,0xD3,0x1F,0x44,0xC6,0x3F, ++0x4E,0xCE,0x56,0xD3,0x1D,0x44,0xC6,0x3F, ++0x54,0xCE,0x56,0xD3,0x9C,0x43,0xC6,0x3F, ++0x43,0xCE,0x56,0xD3,0x9C,0x43,0xC6,0x3F, ++0xEE,0xAB,0xC2,0x80,0xC6,0x2B,0x23,0x81, ++0x6E,0x8B,0xD3,0x46,0x06,0x18,0xC2,0x83, ++0x25,0x90,0x52,0x6F,0x16,0x18,0xC2,0x83, ++0x49,0x95,0x52,0x6F,0x86,0x18,0xC2,0x83, ++0x3B,0x90,0x52,0x6F,0x96,0x18,0xC2,0x83, ++0x4B,0x95,0x52,0x6F,0x65,0x18,0x23,0x83, ++0xF0,0x64,0x7D,0x84,0x7A,0xAD,0x90,0x90, ++0x40,0x76,0x50,0x95,0xD1,0xF4,0x97,0x60, ++0xEE,0xBB,0x52,0x44,0x66,0xE8,0xCD,0x8D, ++0xAE,0x87,0x32,0x05,0x65,0x38,0x93,0x41, ++0xED,0x6B,0x2E,0x88,0x85,0x78,0x8C,0xDD, ++0xFE,0x2E,0x42,0xD8,0x9D,0x13,0x93,0x8B, ++0xEC,0x8B,0xF2,0x84,0x97,0xE7,0x6C,0x9A, ++0xF2,0x5B,0xCD,0x80,0x6A,0xD8,0x1F,0x80, ++0xEF,0x9B,0x4E,0x86,0x68,0xF8,0x1C,0x72, ++0xE1,0x7B,0xF2,0x64,0x79,0xE7,0xBC,0x81, ++0x98,0x2C,0xAA,0xF0,0x0E,0x90,0xCB,0xF6, ++0x9A,0x1C,0x95,0xEA,0x0E,0x6B,0xE4,0x17, ++0x69,0x13,0xDA,0xE8,0xED,0x90,0x1B,0xFC, ++0x1B,0x13,0xDA,0xF8,0x1A,0x6F,0x7B,0xF2, ++0x91,0xDC,0xBA,0xF7,0x12,0x4F,0x44,0xF6, ++0x87,0x13,0x0A,0xF3,0x12,0x6F,0xE7,0x37, ++0x99,0xAC,0x26,0x32,0x62,0x2F,0xC9,0xFE, ++0x99,0x8C,0x85,0xF3,0x32,0x3E,0x7B,0xF2, ++0xB9,0xCD,0xBA,0xF7,0x16,0x6F,0x71,0xF2, ++0xB9,0xAC,0xA7,0xF0,0x12,0x7F,0x65,0xF7, ++0x9B,0xEC,0x74,0xF3,0x19,0x6F,0xE4,0x8D, ++0x99,0xFC,0x85,0xF1,0x12,0x4F,0x44,0xF6, ++0x9D,0xEC,0x77,0xF3,0x13,0x7F,0x65,0x25, ++0x98,0xCC,0xA7,0x20,0xE9,0x90,0x1B,0x2D, ++0xB9,0xCC,0x85,0xF1,0xDC,0x68,0xE4,0xFC, ++0x75,0xEC,0xBA,0xF7,0x16,0x6F,0x61,0xF2, ++0x67,0x13,0x7A,0x0E,0xED,0x90,0xDE,0x0D, ++0x66,0x13,0x7A,0x0E,0xED,0xB0,0xCD,0x0F, ++0x66,0x13,0x88,0x0E,0xE9,0x80,0x8E,0xFD, ++0x67,0x13,0x5A,0xFF,0xEC,0xB0,0xDA,0xFC, ++0x62,0x03,0x5F,0xF8,0x15,0x6F,0xE4,0xF2, ++0x66,0x13,0x0F,0x08,0xEC,0x90,0x4B,0x0B, ++0x16,0x93,0x67,0xF5,0xE7,0x80,0xBB,0x0B, ++0x62,0x13,0x4F,0x08,0xEC,0x80,0xDB,0x0C, ++0x66,0x03,0x7A,0x0E,0xED,0xA0,0xBB,0x09, ++0x62,0x13,0x5F,0x08,0xEC,0x90,0x1B,0x02, ++0x67,0x03,0x5B,0x0F,0xEC,0xA0,0x98,0x0A, ++0x67,0x33,0x0A,0x0A,0xD1,0x90,0x49,0x0B, ++0x62,0x13,0x89,0xFC,0x14,0x6F,0xE4,0xD2, ++0x46,0x33,0x7A,0x0E,0x5D,0x97,0x1B,0x03, ++0x62,0x13,0x4F,0x08,0xEC,0x90,0x5B,0x0A, ++0x62,0x13,0x5F,0x08,0x9D,0x10,0xA6,0x00, ++0xE1,0x9B,0x7F,0x8C,0x64,0x04,0x33,0x83, ++0xEA,0x7B,0x7F,0x80,0x24,0xC7,0xDE,0x82, ++0xAD,0xA4,0xDF,0x87,0x61,0x18,0x1E,0x82, ++0xE6,0xBA,0xCF,0x80,0x63,0x1F,0x93,0x9A, ++0xEE,0x8B,0xF2,0x84,0x61,0x18,0x1E,0x82, ++0x2F,0x64,0xAD,0x8E,0x24,0xC7,0x1E,0x82, ++0xFA,0x6B,0xCF,0x81,0x65,0x18,0xC3,0x83, ++0xFE,0xDB,0x7F,0x8C,0x45,0x58,0x0C,0x85, ++0xEF,0x97,0xD2,0x77,0x45,0x18,0x0C,0x65, ++0xEA,0x9B,0xD6,0x80,0x79,0x18,0x1C,0x82, ++0x04,0x64,0xAD,0x8E,0x61,0x08,0x07,0x85, ++0xD2,0x9B,0xDD,0x87,0x75,0x58,0x2E,0x88, ++0x08,0x64,0xAD,0x8F,0x7D,0x97,0x91,0x40, ++0x0E,0x94,0x50,0x45,0x65,0x18,0x91,0x40, ++0xD3,0xA6,0x6F,0x58,0x58,0x25,0xAE,0x5D, ++0xD3,0xA6,0x6F,0x58,0x58,0x25,0xAE,0x5D, ++0xE0,0x95,0x5C,0x6B,0x6B,0x16,0x9D,0x6E, ++0xE0,0x95,0x5C,0x6B,0x6B,0x16,0x9D,0x6E, ++0xE0,0x95,0x5C,0x6B,0x6B,0x16,0x9D,0x6E, ++0xD7,0xA8,0x61,0x56,0x19,0x7F,0xF0,0x73, ++0x9E,0xDD,0x13,0x24,0x33,0x45,0xD4,0x73, ++0xAD,0xC7,0x08,0x38,0x22,0x4E,0xD2,0x73, ++0xA9,0xC7,0x41,0x26,0x12,0x4E,0xC2,0x26, ++0xBA,0xE5,0x04,0x3B,0x76,0x4A,0xC4,0x37, ++0xAF,0xCD,0x12,0x25,0x76,0x0E,0xCC,0x2B, ++0xD7,0xA8,0x61,0x56,0x62,0x38,0x3F,0xB6, ++0x6D,0xA8,0xA0,0xB7,0xE6,0x2B,0x71,0xB2, ++0xC3,0x57,0x4E,0xB7,0x7E,0x28,0x3F,0xB6, ++0xBD,0xA4,0xF1,0xB3,0x46,0x2B,0xB0,0xB1, ++0xDC,0xA8,0xC1,0x45,0x48,0xD4,0x8F,0xB2, ++0xCD,0xBB,0xFE,0xB3,0xE2,0x2B,0x61,0xB2, ++0x69,0xA8,0xB0,0xB7,0x48,0xD4,0x8F,0xB2, ++0x34,0xFA,0x5D,0xAE,0x47,0xFA,0x11,0xA3, ++0xCC,0xFA,0xEF,0xA2,0x46,0x5A,0x11,0xA3, ++0xCE,0xC9,0xD0,0xA6,0x00,0x3A,0x11,0xA1, ++0x27,0x46,0x8F,0xAC,0xB7,0x68,0x2E,0xA7, ++0xCC,0xB9,0x27,0xA4,0x4D,0x3A,0xB1,0x58, ++0x74,0xA9,0xA6,0xA6,0xFD,0x3A,0x67,0xA3, ++0x72,0x99,0xA6,0xA6,0x53,0xBA,0x2D,0xA7, ++0xC8,0xD9,0x30,0xA5,0xD6,0x3A,0xB0,0xA2, ++0x5F,0xAB,0x51,0xA7,0x67,0x2A,0x30,0xA0, ++0xCE,0xFB,0xF1,0xA5,0x58,0x70,0x35,0xA0, ++0xEC,0xB9,0x70,0xAD,0x46,0x3A,0xE6,0xA1, ++0xC9,0x39,0xD0,0x46,0x5D,0x3A,0xB1,0x48, ++0xCE,0xB9,0x27,0xA4,0x76,0x3A,0xB1,0x58, ++0xD8,0x39,0xEC,0xA2,0x77,0x3A,0x11,0xA1, ++0x19,0x46,0x8F,0xAC,0x47,0x2A,0x25,0xA7, ++0x54,0x9B,0xEF,0xA2,0x45,0x3A,0xE0,0xA3, ++0xF0,0x2F,0x66,0xCC,0xDA,0xA3,0x28,0xC1, ++0xE5,0x32,0x3D,0x3F,0xDC,0xA3,0x79,0x38, ++0x50,0x20,0xE9,0xD4,0xDC,0x83,0x88,0x38, ++0xF6,0x2F,0x66,0x3C,0x49,0x5C,0xD7,0x30, ++0xF3,0x2F,0x66,0x3C,0x4B,0x5C,0xD7,0x30, ++0x75,0x20,0xE9,0x34,0xEE,0xB3,0x88,0x38, ++0x51,0x20,0x49,0x3F,0xBF,0xA2,0x28,0x30, ++0x65,0x30,0x7D,0x3B,0xDE,0xA3,0x79,0x3A, ++0x55,0x00,0x49,0xCF,0x7C,0xAC,0xA7,0xC9, ++0xA6,0xDF,0x16,0xC4,0xC6,0xF3,0xBC,0x3E, ++0x49,0x40,0x7D,0x3B,0xD8,0xE3,0xAD,0x3B, ++0x55,0x40,0x64,0x3B,0xDB,0x93,0x88,0x3A, ++0x5D,0x00,0x49,0x3F,0xDA,0xB3,0x88,0x3A, ++0x5F,0x2D,0x66,0x3C,0x5D,0x5C,0xD7,0x30, ++0x55,0x40,0x64,0x3B,0xDB,0x93,0x88,0x3A, ++0x5D,0x00,0x49,0x3F,0xDA,0xB3,0x88,0x3A, ++0xAA,0xDF,0xB6,0xC2,0xDB,0x5D,0xD7,0xCF, ++0xAA,0xDF,0x46,0xC2,0x25,0x5C,0xD7,0x3E, ++0xAD,0xCF,0xB6,0xC0,0x82,0x53,0x58,0xC6, ++0xD2,0x20,0xE9,0xCA,0x20,0x5C,0x77,0xC7, ++0x52,0x5C,0xAB,0xC9,0x21,0x4C,0x77,0xC5, ++0x0F,0xD0,0x99,0xC3,0x52,0xA3,0x28,0xCF, ++0xAA,0xDF,0xB6,0xC2,0xD9,0xDF,0x6A,0xCC, ++0x5A,0x9E,0x3B,0xC8,0x21,0x1C,0x67,0xC5, ++0xAB,0xAF,0xB6,0xC0,0x21,0x0C,0x77,0xC7, ++0x84,0xDF,0x16,0x2B,0x80,0x5C,0x77,0xC7, ++0x1A,0xBE,0x89,0xC4,0x21,0x5C,0x51,0xC1, ++0x8C,0xDF,0x16,0xCB,0x25,0x0C,0x51,0xC1, ++0xAD,0xDF,0xB6,0xC0,0xF9,0x5A,0xD7,0xCF, ++0xAA,0xFF,0xB6,0xC0,0x26,0x4C,0x77,0xC5, ++0xAE,0xDF,0xB6,0xC0,0xBD,0x5A,0xD7,0xCF, ++0xAA,0xDF,0x46,0xC2,0x3A,0x5C,0xD7,0x3E, ++0x6F,0xB9,0xD0,0xA4,0x56,0x3A,0x37,0xAA, ++0xCB,0xB9,0xD0,0xA6,0x89,0x3C,0xB1,0xA9, ++0xC4,0xB9,0xF6,0xA2,0x40,0x3A,0x11,0xA3, ++0x07,0xBF,0x70,0xAC,0x43,0x3A,0x31,0xA2, ++0xCD,0xB9,0xF0,0xA5,0x4B,0x3A,0x37,0xA7, ++0xCB,0xB9,0xD0,0xA6,0x81,0x3C,0xB1,0xA9, ++0xC8,0xB9,0xF0,0xA7,0x57,0x1A,0x11,0xA1, ++0xCD,0xB9,0xF0,0xA5,0x47,0x2A,0x11,0xA1, ++0xA0,0xBF,0x70,0xBD,0x57,0x3A,0x37,0xA7, ++0x68,0xB9,0xD0,0xA4,0x47,0x3A,0x37,0xA7, ++0xCB,0xB9,0xD0,0xA6,0xFB,0x3C,0xB1,0xA9, ++0xC8,0xB9,0xF0,0xA7,0x57,0x1A,0x11,0xA1, ++0x3C,0xF8,0xCD,0xAF,0x46,0x3A,0x31,0xA0, ++0xCC,0xA9,0xD0,0xA4,0x18,0x3C,0xB1,0xA8, ++0xCD,0xE9,0xF5,0xA5,0x46,0x7A,0x35,0xA0, ++0xCC,0xB9,0xA4,0xA2,0x47,0x3A,0xE1,0xA1, ++0x89,0xF1,0x61,0x10,0xD7,0x81,0x0A,0xBC, ++0x88,0xFD,0x94,0xE0,0xF3,0xFF,0x48,0xEE, ++0x78,0xBC,0x19,0xEA,0xA8,0x7E,0x55,0xE5, ++0x60,0xBD,0xAB,0xE6,0x04,0x63,0x7A,0xE4, ++0x88,0xFD,0xB0,0xE6,0xB7,0x7F,0x6A,0xE3, ++0x84,0xFD,0xB0,0xE6,0xC2,0x81,0x0A,0xED, ++0x88,0xAD,0x94,0xE2,0x3D,0x81,0x0A,0xED, ++0x28,0xEC,0xAB,0xE6,0x06,0x5E,0x55,0xE7, ++0xE3,0xF2,0xBB,0xE1,0x2E,0x81,0x0A,0xED, ++0x18,0xFC,0xAB,0xE6,0x04,0x63,0x7A,0xE4, ++0x30,0x02,0xCB,0xE8,0xFC,0x2E,0xF5,0xE4, ++0x8F,0xF0,0xBB,0xE1,0x06,0x6E,0x55,0xE7, ++0xAE,0x02,0xCB,0xE8,0xCF,0x7E,0x55,0xE5, ++0x88,0x9D,0x94,0xE0,0x03,0x7E,0x71,0xE3, ++0xBC,0xFF,0x35,0xE0,0x17,0x2E,0x51,0xE3, ++0x8C,0xFD,0xB0,0xE6,0x18,0x70,0x7A,0xE4, ++0xEC,0x70,0x67,0x2A,0x11,0xCE,0x7D,0x28, ++0x58,0xCE,0x07,0x24,0xF1,0xB3,0x39,0x21, ++0x44,0x31,0xA8,0x2C,0x4C,0xB2,0x39,0xD0, ++0x02,0x31,0x58,0x2C,0x85,0x4D,0xC6,0x21, ++0x45,0x31,0xAD,0x2C,0xBD,0xB2,0x39,0xD0, ++0x0D,0x31,0x58,0x2C,0x80,0x4D,0xC6,0x21, ++0x26,0x3E,0x77,0x2D,0xDE,0x4D,0xC6,0x21, ++0x44,0x01,0x58,0x2C,0xC8,0xA2,0x99,0x2B, ++0x47,0x11,0x58,0x2E,0xCB,0xB2,0x99,0x2B, ++0x08,0xCE,0x07,0x24,0xCE,0xB2,0x69,0x29, ++0x33,0x31,0xF8,0xD5,0x92,0xBD,0xB6,0x28, ++0x4C,0xCE,0x07,0x24,0x85,0xB2,0x99,0x29, ++0x06,0xCE,0x07,0x24,0xCE,0x82,0x99,0x29, ++0x43,0x21,0x58,0x2E,0xCC,0x92,0x99,0x2B, ++0x40,0x31,0x58,0x2E,0x8E,0x4D,0xC6,0x21, ++0x45,0x31,0xA8,0x2C,0xA3,0xB2,0x39,0xD0, ++0x21,0x0D,0x44,0x1E,0x98,0x81,0x0A,0x13, ++0x77,0x3E,0xFB,0xD9,0xFC,0x91,0x3A,0xDC, ++0x77,0x0C,0xCB,0xDC,0xDC,0x71,0x0B,0xD9, ++0x50,0x35,0x5A,0xC9,0x91,0xE0,0x6D,0x90, ++0x14,0x2A,0xEE,0x90,0x84,0xAD,0x2F,0x95, ++0x0F,0x2B,0xC1,0xFC,0x95,0xEC,0x6B,0x9E, ++0x12,0x56,0xB2,0x8C,0x99,0xA9,0x2F,0x95, ++0x0F,0x2E,0xEE,0x90,0x84,0xA8,0x00,0xF9, ++0x15,0x6D,0xA4,0x8F,0x88,0xF3,0x6B,0x89, ++0x57,0x6A,0xAE,0x9D,0x98,0xE4,0x78,0xA2, ++0x39,0x45,0x96,0xFC,0x94,0xE4,0x6B,0x9D, ++0x12,0x70,0x88,0x94,0x99,0xE2,0x61,0x8A, ++0x02,0x6F,0xE3,0xD9,0x90,0xF9,0x26,0xDC, ++0x1B,0x7A,0xE2,0xF6,0xFC,0x81,0x0A,0xF9, ++0x57,0x74,0xBB,0xAF,0x95,0xE6,0x64,0x98, ++0x03,0x77,0xB9,0x99,0xD4,0xA4,0x66,0x81, ++0x92,0xEE,0x71,0x40,0x7B,0x28,0xBF,0x1D, ++0x9E,0xA2,0x7F,0x19,0x10,0x3B,0xB6,0x71, ++0xDA,0xBA,0x66,0x18,0x15,0x21,0xBE,0x1C, ++0x9B,0xBB,0x34,0x02,0x63,0x24,0xBC,0x50, ++0x93,0xEB,0x6B,0x48,0x19,0x47,0xC6,0x35, ++0xD4,0xBA,0x77,0x6F,0x43,0x28,0xA5,0x40, ++0xC9,0xA7,0x73,0x49,0x6F,0x2E,0xAE,0x50, ++0xD8,0xA5,0x2F,0x15,0x48,0x64,0x9D,0x7A, ++0xF0,0x93,0x0D,0x30,0x5F,0x39,0xB6,0x6A, ++0xC8,0xAB,0x64,0x45,0x42,0x24,0xB2,0x4C, ++0xE4,0xAD,0x6F,0x55,0x53,0x26,0xEE,0x10, ++0xC3,0xE7,0x5C,0x7E,0x77,0x10,0xCC,0x35, ++0xBB,0x1E,0x05,0x10,0x54,0x28,0xA4,0x40, ++0xDC,0x91,0x6A,0x55,0x5D,0x12,0xB2,0x54, ++0xD2,0xA2,0x07,0x30,0x52,0x22,0xA9,0x41, ++0x9B,0xBE,0x66,0x42,0x51,0x20,0xFC,0x10, ++0x2D,0x0C,0xC9,0xBB,0xB0,0xC7,0x77,0xB4, ++0x33,0x7F,0x84,0xBB,0xB3,0x9E,0x18,0xA3, ++0x70,0x58,0xE3,0xDE,0xBC,0xCC,0x47,0xAF, ++0x38,0x4F,0x8D,0xBB,0xDE,0xA3,0x28,0xDB, ++0x37,0x4F,0x86,0xAA,0xB3,0xCC,0x4C,0xBE, ++0x68,0x10,0x91,0xFB,0xA6,0xA9,0x28,0xDB, ++0x55,0xEE,0xEB,0xFE,0xB1,0xD7,0x58,0x84, ++0x3C,0x4E,0x80,0xAA,0xF6,0x8A,0x22,0xDB, ++0x37,0x4F,0x86,0xAA,0xFE,0xCD,0x47,0xA9, ++0x38,0x41,0x85,0xD4,0xDE,0xA3,0x28,0xDB, ++0x27,0x4F,0x86,0xAA,0xFE,0xC8,0x4D,0xA2, ++0x75,0x70,0x88,0xAD,0xAD,0xA9,0x28,0xDB, ++0x37,0x4F,0x86,0xAA,0xB2,0xCC,0x49,0xBF, ++0x30,0x52,0xC9,0x8E,0xBF,0xD0,0x5B,0xD1, ++0x55,0x20,0xE9,0xDE,0x95,0xA3,0x88,0x38, ++0x89,0xDE,0x16,0x35,0xDC,0x93,0x88,0x38, ++0x34,0x56,0x2F,0x59,0xBB,0xE5,0xEE,0x5C, ++0x37,0x46,0x2F,0x59,0x63,0x3B,0xB1,0x56, ++0x32,0x46,0xDF,0x5B,0xBE,0xC5,0x4E,0xA7, ++0xEF,0x46,0x00,0x5A,0x2F,0x3B,0xB1,0x56, ++0x32,0x26,0x2F,0x5B,0xBA,0xC5,0x4E,0x57, ++0x33,0x56,0x2F,0x59,0x60,0xC5,0xC1,0x5F, ++0xA1,0xB8,0x70,0x53,0xF6,0xC5,0xEE,0x5E, ++0xF0,0xB8,0x70,0x53,0xB8,0xC5,0xDA,0x58, ++0xEB,0x56,0x10,0x5D,0xB9,0xC5,0x1E,0x5C, ++0x23,0x46,0x8F,0xA2,0x68,0xC5,0xC1,0x5F, ++0xB9,0xB8,0x70,0x53,0xAC,0xD5,0xDA,0x58, ++0xEF,0x46,0x00,0x5A,0xB4,0xE5,0xDA,0x58, ++0xB5,0xB8,0x70,0x53,0xAC,0xC5,0xDA,0x58, ++0x3F,0x56,0x1B,0x5D,0x8C,0xC3,0x4E,0x56, ++0x37,0x46,0x1B,0x5D,0xB4,0xD5,0xDA,0x58, ++0x32,0x46,0xCF,0x58,0xA8,0xD5,0xDA,0x58, ++0x13,0x66,0xCF,0x5A,0x78,0xC5,0xC1,0x5F, ++0x4F,0xB8,0x70,0x53,0xB9,0xC5,0x4E,0x57, ++0xF7,0x46,0x00,0x5A,0xC1,0x3B,0xB1,0x56, ++0x33,0x46,0xD9,0x5B,0xB6,0xC5,0x4E,0xA7, ++0x7E,0x46,0x2F,0x5B,0x09,0x3B,0xB1,0x56, ++0x98,0xB8,0x70,0x53,0xB9,0xC5,0x1E,0x5E, ++0x3A,0x46,0x8F,0xA2,0xF7,0xC5,0xEE,0x5E, ++0x90,0xB8,0x70,0x53,0x14,0xC5,0xC1,0x5F, ++0x5D,0xB8,0x70,0x53,0x08,0xF5,0xD1,0x58, ++0x9F,0x66,0x2F,0x5B,0x14,0xD5,0xC1,0x5F, ++0x83,0x46,0x00,0x5A,0xD1,0x3B,0xB1,0x56, ++0xCD,0xB9,0x70,0x52,0xF4,0xC5,0xEE,0x5E, ++0xAA,0xB8,0x70,0x53,0x04,0x85,0xD1,0x58, ++0x8F,0x46,0x00,0x5A,0xDB,0x3B,0xB1,0x56, ++0x07,0xB9,0xA0,0x59,0xB8,0xC5,0xEE,0x5E, ++0xC3,0xC7,0x32,0x50,0xDA,0xAA,0x21,0xC9, ++0xD9,0xAB,0x64,0x40,0x51,0x7C,0x87,0x45, ++0xD9,0xAC,0x1C,0x21,0x4E,0x28,0xA7,0x7B, ++0xC3,0xB1,0x7F,0x55,0x09,0x79,0xAF,0x0D, ++0xF1,0x91,0x51,0x7C,0x2B,0x5C,0xD7,0x24, ++0x61,0xEE,0x59,0x76,0x42,0x30,0xB2,0x45, ++0xD8,0x80,0x65,0x44,0x4F,0x2F,0xBE,0x50, ++0xC3,0xA9,0x73,0x7E,0x45,0x3D,0xA3,0x45, ++0xA0,0xDF,0x16,0x21,0x01,0x37,0xB2,0x5D, ++0x82,0xFA,0x7A,0x59,0x0D,0x79,0xBB,0x5C, ++0x83,0xD5,0x16,0x21,0x01,0x3A,0xA2,0x4A, ++0xC9,0xF7,0x33,0x4D,0x59,0x70,0xF2,0x48, ++0xD2,0xF6,0x1C,0x21,0x4E,0x28,0xA7,0x7B, ++0xC2,0xBA,0x77,0x45,0x44,0x2E,0xF7,0x4A, ++0xC5,0xFF,0x7F,0x4F,0x47,0x33,0xDD,0x24, ++0xCE,0xBA,0x77,0x45,0x7E,0x30,0xB8,0x4B, ++0xDA,0xD5,0x16,0x21,0xDD,0xD0,0xD5,0x04, ++0x7C,0x05,0xC4,0xF4,0xB4,0x84,0x6C,0x9F, ++0x53,0x31,0xEA,0xA0,0xBA,0x81,0x0D,0xF6, ++0x7D,0x11,0xDF,0xFF,0xBA,0x86,0x18,0xBF, ++0x34,0x17,0x97,0xBF,0xFE,0xC8,0x49,0xEC, ++0x39,0x4D,0x8C,0x90,0x9A,0xE7,0x6C,0x9F, ++0x11,0x74,0xAD,0xBA,0xD0,0x92,0x01,0xEF, ++0x31,0x10,0xC2,0xBA,0xC8,0xA6,0x21,0xBF, ++0x72,0x0B,0xC9,0xFF,0x90,0xE7,0x6C,0x9F, ++0xE1,0x25,0x80,0x73,0x9A,0xA7,0xDC,0x7E, ++0x10,0x14,0x0D,0x7B,0x9B,0xE7,0xCC,0x9C, ++0xE1,0xE5,0x10,0x92,0x9B,0xB7,0xCC,0x7C, ++0x11,0x04,0x0D,0x79,0xDC,0xE7,0x6C,0x75, ++0xA1,0x61,0xAC,0x79,0x9A,0xE7,0x3B,0x7E, ++0x16,0x64,0x0D,0xAB,0x9A,0x97,0x2B,0x7F, ++0x20,0x64,0xAD,0x70,0x9A,0xF7,0xB8,0x7A, ++0x01,0x64,0xED,0x78,0x9B,0xD7,0xB8,0x7A, ++0x27,0x47,0x1F,0x49,0xA8,0xF4,0xD9,0x4C, ++0x21,0x47,0x1F,0x49,0xAB,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x21,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xAD,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x27,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xAF,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x25,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xA1,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x2B,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x21,0x47,0x1F,0x49,0xA3,0xE4,0x8B,0x49, ++0x23,0x77,0x1C,0x49,0xAA,0xC4,0xDE,0x4C, ++0x29,0x67,0x4A,0x4C,0xA8,0xF4,0xDD,0x4C, ++0x65,0x03,0x5B,0x0D,0xE1,0xA0,0xCF,0x0D, ++0x67,0x33,0x58,0x0D,0xEE,0x80,0x9A,0x08, ++0x6B,0x23,0x0E,0x08,0xEC,0xB0,0x99,0x08, ++0x65,0x03,0x5B,0x0D,0xE3,0xA0,0xCF,0x0D, ++0x67,0x33,0x58,0x0D,0xEE,0x80,0x9A,0x08, ++0x69,0x23,0x0E,0x08,0xEC,0xB0,0x99,0x08, ++0x76,0x53,0x5E,0x0F,0xEC,0xC0,0x98,0x08, ++0x63,0x73,0x58,0x0D,0xFD,0x90,0x4B,0x0B, ++0xAD,0xEC,0x25,0xC7,0xED,0x90,0x4B,0x0B, ++0x67,0x03,0x0E,0xF9,0xEC,0x90,0x5B,0xFA, ++0x67,0x43,0x5F,0xFD,0xE8,0xF0,0x9D,0xF8, ++0x9F,0xEC,0x25,0xF7,0x1C,0x8F,0x14,0x0B, ++0x63,0x13,0x7A,0x0C,0xC3,0x9A,0x1B,0x03, ++0x67,0x43,0x7A,0x0C,0x1C,0x8F,0x14,0x0B, ++0x60,0x13,0x7A,0x0C,0xC7,0x9A,0x1B,0x03, ++0x67,0x73,0x7A,0x0C,0xED,0x90,0x4C,0x0B, ++0x2F,0x13,0xDA,0x08,0x14,0x67,0x61,0xF6, ++0x69,0x6D,0x98,0xFA,0x76,0x6F,0x7B,0xF2, ++0x29,0xFA,0xF5,0xF3,0x13,0x76,0x25,0xF4, ++0x29,0xFA,0xE5,0xF3,0x1C,0x43,0xA4,0xF5, ++0xED,0xFE,0xB7,0xF7,0x52,0x7F,0x25,0xF4, ++0xED,0xFE,0xA7,0xF7,0x5A,0x7F,0x7B,0xF2, ++0xD1,0xCC,0xB4,0xF7,0x92,0x4F,0x26,0xF4, ++0xD1,0xCC,0xA4,0xF7,0x12,0x4F,0x04,0xF4, ++0xD9,0xCC,0xA4,0xF7,0x5A,0x4F,0x75,0xF2, ++0x1B,0xCC,0xA7,0xF1,0x5A,0x4F,0x65,0xF2, ++0x21,0xFA,0xF5,0xF3,0x6D,0x7F,0x25,0xF4, ++0x89,0xFC,0xA4,0xF1,0xAA,0x79,0x24,0xF6, ++0xDE,0xFC,0xA4,0xF1,0xAA,0x79,0x24,0xF6, ++0x89,0xFC,0xE4,0xF1,0xAA,0x79,0x24,0xF6, ++0x99,0xEC,0x85,0xF1,0x0C,0x90,0xCB,0xF6, ++0x99,0x92,0x25,0x37,0x12,0x4F,0xD4,0x32, ++0xB4,0x76,0xD5,0x26,0xCF,0xC2,0x99,0x2B, ++0x07,0xEF,0xB5,0x2D,0xCE,0x32,0x99,0x2B, ++0x46,0xA1,0x58,0x2E,0xCC,0xD2,0x99,0x2B, ++0x14,0x95,0x65,0x2A,0x8E,0xEC,0xB4,0x28, ++0x41,0x01,0x58,0x2E,0xC9,0xA2,0x99,0x2B, ++0x4E,0x11,0x58,0x2E,0x84,0xBD,0xB6,0x28, ++0xF6,0xCC,0x07,0x24,0xCA,0x92,0x99,0x2B, ++0x4E,0x21,0x58,0x2E,0xC9,0xB2,0x99,0x2B, ++0x65,0x35,0xF8,0x24,0xCF,0xF2,0x99,0x2B, ++0x44,0x21,0x58,0x2E,0xCF,0xE2,0xB4,0x2F, ++0x4E,0x01,0x58,0x2E,0xC9,0x92,0x99,0x2B, ++0x57,0x3F,0x77,0x2D,0x68,0x4F,0xC6,0x21, ++0x44,0x31,0xAC,0x2C,0xCB,0xB2,0x99,0xDB, ++0x52,0x31,0xF8,0xD5,0x99,0xBD,0xB6,0x28, ++0xE6,0xCC,0x07,0x24,0xDF,0xD2,0xB4,0x28, ++0x4D,0x11,0x58,0x2E,0xC9,0x82,0x99,0x2B, ++0x19,0x74,0x0D,0x7B,0x9D,0xE7,0xCC,0x7E, ++0x25,0x67,0xAD,0x71,0x9F,0xEA,0xE3,0x7D, ++0x8B,0x99,0x52,0x71,0x9A,0xA7,0xCC,0x7C, ++0x15,0x64,0x7B,0x7D,0x9E,0xF7,0xB9,0x78, ++0x10,0x64,0xFD,0x7B,0x93,0xE7,0x6C,0x95, ++0x15,0x54,0x78,0x7D,0x9E,0xF7,0xCC,0x7E, ++0x5B,0x6B,0x22,0x78,0x9A,0xD7,0xE1,0x7A, ++0x15,0x54,0x0D,0x7B,0x9E,0xC7,0xBA,0x78, ++0x9F,0x99,0x52,0x71,0x98,0xE7,0xCC,0x7C, ++0x52,0xBA,0x20,0x78,0x6A,0x60,0xD1,0x77, ++0x0E,0x64,0xF9,0x79,0x9E,0xF7,0xCC,0x9E, ++0x5B,0x6B,0x22,0x98,0x1D,0x1A,0x93,0x94, ++0x10,0x24,0x29,0x78,0xBA,0xE7,0x38,0x7C, ++0xFB,0x9B,0x52,0x20,0x9A,0xE7,0xCC,0x7C, ++0xE5,0x9B,0x52,0x70,0xEA,0xA7,0x41,0x76, ++0x12,0x34,0x0D,0x7B,0xD8,0x38,0x21,0x7D, ++0x23,0x57,0x3E,0x48,0xA9,0x94,0xFF,0x4F, ++0x2A,0x47,0x13,0x4B,0xB1,0xE5,0xC2,0x49, ++0x26,0x37,0x4C,0x4E,0xAD,0xB4,0x9E,0x4B, ++0x23,0x17,0x1A,0x4B,0xA8,0xD8,0x0B,0x4F, ++0xD8,0xA8,0x61,0x93,0xA9,0x94,0xFF,0x4F, ++0x26,0x47,0x13,0x4B,0xAD,0xB4,0xDD,0x4C, ++0x22,0x36,0x48,0x4C,0xAD,0xB4,0x9E,0x4B, ++0x23,0x17,0x1A,0x4B,0xAD,0xD4,0x0B,0x4F, ++0xDB,0xA8,0x61,0x93,0xA9,0xE4,0xD2,0x49, ++0x27,0x67,0x3E,0x48,0xAD,0xF4,0xD2,0x4E, ++0x2A,0x47,0x13,0x4B,0x00,0x2B,0xA0,0x47, ++0x60,0x88,0x13,0x4B,0xD9,0x54,0xE2,0x44, ++0x51,0x3F,0xFF,0x89,0x9B,0xE1,0x69,0x8C, ++0x4B,0x39,0xBE,0xED,0xC8,0xA0,0x3E,0x91, ++0x12,0x2F,0xBB,0xD1,0x85,0xF4,0x13,0xC9, ++0x4C,0x6A,0xAE,0xD1,0x8C,0xAC,0x73,0x8C, ++0xEC,0x94,0x53,0x66,0x70,0x0A,0xC8,0x36, ++0xF0,0xD8,0x4C,0x09,0x03,0x7E,0xF5,0x06, ++0xFB,0x95,0x55,0x23,0x31,0x4B,0xC3,0x26, ++0xE7,0x88,0x40,0x23,0x2F,0x5E,0x87,0x63, ++0xFC,0xC0,0x04,0x7B,0x26,0x06,0xFF,0x26, ++0xCC,0x9C,0x40,0x62,0x3E,0x4E,0x8D,0x23, ++0xF0,0xD1,0x14,0x4F,0x66,0x10,0xC8,0x36, ++0xF0,0xD8,0x4C,0x2F,0x23,0x1A,0x9C,0x61, ++0xED,0x8E,0x40,0x3E,0x33,0x06,0xD0,0x7E, ++0x82,0xFD,0x34,0x03,0x51,0x2D,0xB4,0x26, ++0xE1,0x93,0x3E,0x03,0x51,0x2D,0xB4,0x26, ++0xE7,0x88,0x40,0x09,0x03,0x7E,0xF5,0x06, ++0xFB,0x94,0x53,0x6D,0x62,0x0A,0x80,0x74, ++0xED,0xA6,0x11,0x67,0x5E,0x43,0xD0,0x36, ++0xBA,0xA5,0x14,0x22,0x3E,0x5E,0x91,0x6F, ++0xEF,0x98,0x47,0x77,0x58,0x5B,0x91,0x5B, ++0x3D,0x50,0x8C,0xB9,0xD3,0xD6,0x77,0x8E, ++0x70,0x14,0xCF,0xF8,0xA6,0xD3,0x19,0x84, ++0x00,0x75,0xBC,0x8B,0xFB,0xB6,0x50,0x67, ++0x21,0x4D,0x1C,0x6A,0xFA,0xA6,0x82,0x68, ++0x72,0x65,0x43,0x6D,0xA9,0xBE,0xDD,0x6F, ++0x95,0x74,0xBA,0x6B,0x1E,0xF2,0x78,0x6E, ++0x93,0x74,0xBE,0x6B,0x8B,0x96,0xFD,0x6B, ++0x02,0x65,0x39,0x6B,0x89,0xF6,0x2C,0x6F, ++0x00,0x55,0x1C,0xA8,0x8A,0xD6,0xDD,0xBD, ++0x02,0x5D,0x1C,0x6A,0xAA,0xDE,0xFF,0x6E, ++0x01,0x6D,0x1C,0x6A,0x8A,0xA6,0xFB,0x6E, ++0x01,0x75,0xE9,0x6A,0x8B,0xA6,0xFD,0x6B, ++0x01,0x55,0x3E,0xB9,0x18,0xD2,0x5C,0x6E, ++0x04,0x65,0x3C,0x6E,0x8B,0xF6,0xDD,0x6D, ++0x70,0xF5,0x01,0x63,0x74,0xB9,0x50,0x67, ++0x02,0x74,0xAF,0x68,0x9F,0x26,0x30,0x6C, ++0x00,0xF5,0x1C,0x6A,0x8B,0x56,0xDD,0x6D, ++0x03,0x15,0x1C,0x6A,0x93,0xF6,0xE0,0x8B, ++0x00,0xD5,0x3C,0x8E,0x8B,0xF6,0x9D,0x8D, ++0x00,0xD5,0x34,0x8E,0xF2,0xF6,0x7D,0x84, ++0x00,0x75,0x2E,0x6E,0xAD,0xAE,0xDD,0x6F, ++0x76,0x05,0x43,0x6D,0xFB,0x66,0x82,0x68, ++0x20,0xCD,0x1C,0x6A,0x8F,0xF6,0xEF,0x6B, ++0x0C,0xD5,0x31,0x6E,0xFB,0xE6,0x82,0x68, ++0x20,0x7D,0x1C,0x6A,0x8E,0xF6,0x2D,0x6F, ++0x00,0x35,0x1C,0xB8,0x8A,0xB6,0xDD,0xAD, ++0x00,0x75,0xE8,0x68,0x8E,0xF6,0x3D,0x9E, ++0x00,0x7D,0x3D,0x9A,0x8B,0xF6,0x2A,0x9F, ++0x04,0x75,0x2E,0x6E,0x8A,0xB6,0x39,0x0C, ++0x00,0x75,0xE8,0x68,0x83,0xF6,0xF0,0x6B, ++0x0B,0x75,0xBC,0x81,0x8C,0xC6,0xDD,0x6F, ++0x05,0x55,0x1C,0x6A,0x8F,0xE6,0xDD,0x6F, ++0xE6,0x9B,0xDF,0x87,0xAD,0x1A,0x93,0x8B, ++0xE2,0x9B,0xCF,0x80,0x45,0x10,0x23,0x81, ++0xE6,0x9B,0xCF,0x70,0x64,0x58,0xD7,0x72, ++0xE2,0x3B,0xDF,0x70,0x63,0x18,0x13,0x70, ++0xE6,0x9B,0xDF,0x70,0x60,0x08,0x33,0x81, ++0xE6,0x9B,0xCF,0x80,0x61,0x58,0x1E,0x85, ++0xFE,0x9B,0xDF,0x80,0x5F,0x11,0x93,0x8B, ++0x7E,0x9E,0x53,0x85,0x65,0x58,0x33,0x81, ++0xFE,0x9B,0xCF,0x80,0x64,0x10,0xC7,0x83, ++0xEF,0x8B,0x12,0x85,0x64,0x30,0x18,0x81, ++0xEC,0x9B,0x52,0x6F,0xF1,0x1F,0x93,0x80, ++0xEC,0x9B,0x02,0x84,0x62,0x18,0x93,0xFA, ++0xEB,0x9B,0xD3,0x85,0x64,0x10,0xC3,0x83, ++0xEF,0xDB,0x16,0x87,0x65,0x00,0x18,0x81, ++0xEC,0x9B,0x52,0x4F,0xF1,0x1F,0x93,0x80, ++0xEF,0x9B,0x02,0x84,0x64,0x58,0xD7,0xE2, ++0xB3,0xCE,0x9A,0xD5,0x37,0x7D,0x66,0xD4, ++0xBE,0xEE,0xA7,0xD1,0x34,0x5D,0x66,0xD4, ++0x9B,0xC6,0xA7,0xD1,0x3C,0x4D,0x4B,0xD0, ++0xB3,0xCE,0x9A,0xD5,0x30,0x45,0x4D,0xD4, ++0xB3,0xCE,0x8A,0xD5,0x38,0x4D,0x4B,0xD7, ++0x24,0xCC,0x07,0xDB,0x3C,0x4D,0x5B,0xD0, ++0xBE,0xDE,0xA7,0xD1,0x10,0x45,0x76,0xD4, ++0xB3,0xCE,0x9A,0x25,0x31,0x0D,0x82,0x27, ++0xB7,0x6E,0x8A,0x25,0x36,0x4D,0x46,0x25, ++0xB3,0xCE,0x8A,0x25,0x34,0x45,0x66,0xD4, ++0xBB,0xCE,0x8F,0xD5,0x38,0xFD,0x5B,0xD0, ++0xB0,0xCE,0xA7,0xD1,0x20,0x44,0xC6,0xDE, ++0x2B,0x7B,0x66,0xD0,0x31,0x45,0x96,0xD6, ++0xBB,0x8E,0xA7,0xD1,0x31,0x65,0x4F,0xD4, ++0xB9,0xCE,0x07,0x3A,0xA4,0x4A,0xC6,0xD5, ++0xB9,0xCE,0x57,0xD1,0x37,0x4D,0xC6,0xAF, ++0xC9,0xB9,0xF1,0xA7,0x46,0x32,0xE1,0xA1, ++0xCD,0xF9,0x34,0xA5,0x47,0x22,0x38,0xA3, ++0xCE,0xB9,0x70,0x6D,0xD3,0x3D,0xB1,0xA2, ++0xCD,0xB9,0x20,0xA6,0x46,0x7A,0xF5,0xC0, ++0xC4,0xB9,0xED,0xA2,0x40,0x0A,0x11,0xA3, ++0xC9,0x99,0xD0,0xA6,0x43,0x2A,0x11,0xA3, ++0xEC,0xB1,0xD0,0xA6,0x4B,0x3A,0x3C,0xA7, ++0xC4,0xB9,0xED,0xA2,0x47,0x32,0x38,0xA3, ++0xC4,0xB9,0xFD,0xA2,0x4F,0x3A,0x3C,0xA0, ++0xBB,0xBB,0x70,0xAC,0x4B,0x3A,0x2C,0xA7, ++0xEC,0xB1,0xC0,0xA6,0x4F,0x3A,0x2C,0x57, ++0xCD,0xF9,0x34,0x55,0x4B,0x9A,0x3C,0x57, ++0xCA,0xB9,0xF0,0x57,0x4F,0x3A,0x3C,0x57, ++0xCC,0xB9,0xE8,0xA2,0x33,0x2A,0x4E,0xA4, ++0xCD,0xB9,0xF0,0xA6,0x47,0x3A,0x39,0xA7, ++0xD4,0xB9,0xED,0xA2,0x4F,0x2A,0x2C,0xA7, ++0x33,0x56,0x0F,0x5D,0xBC,0xC5,0xD3,0x58, ++0x17,0x96,0x02,0x5A,0x48,0x4A,0xF3,0x55, ++0xC3,0x06,0xA2,0x51,0x98,0xC5,0x1C,0x5E, ++0x33,0x06,0x6F,0x0B,0xB8,0x95,0xEE,0x0E, ++0x13,0xA6,0xED,0x0A,0x8C,0x07,0xAE,0x0C, ++0x36,0x06,0x2F,0x09,0xA6,0xC5,0x4E,0x07, ++0xF1,0x09,0x2F,0x59,0xB8,0xA5,0xEE,0x5E, ++0x97,0x3B,0x0D,0x58,0xBB,0x85,0xEE,0x5C, ++0xF4,0x14,0x2F,0x59,0xBC,0xC5,0x4E,0x57, ++0x36,0x46,0xDB,0x59,0xBD,0x05,0x0A,0x1D, ++0x37,0x27,0x0F,0x0F,0xB4,0x04,0xDF,0x1A, ++0x37,0x87,0x0F,0x1F,0xB9,0x85,0x1A,0x5F, ++0xCB,0xB9,0x70,0x92,0xA7,0x85,0x89,0x5E, ++0x37,0x66,0xDD,0x58,0xBD,0x85,0x0D,0x5D, ++0x37,0x57,0x1E,0x5F,0xA9,0x87,0xEE,0x5C, ++0x31,0x46,0x8F,0xB2,0xB8,0xD5,0xEE,0x5C, ++0x48,0x20,0xE9,0xCA,0x21,0x1C,0x53,0xC5, ++0xAE,0xDF,0xB6,0xC0,0xD1,0xDC,0x6A,0xCC, ++0xAE,0xBE,0x87,0xC6,0x2D,0x2C,0xD1,0xC4, ++0xBC,0x8D,0x93,0xC0,0x16,0x22,0x77,0xC5, ++0xAE,0x8E,0x96,0xC6,0x26,0x0C,0x77,0xC5, ++0xAB,0x9F,0x92,0xC3,0x22,0x5C,0x83,0xC5, ++0x5C,0x20,0xE9,0x9B,0x24,0x5C,0x77,0xC5, ++0x5A,0x5F,0xAB,0xC9,0xD1,0x1C,0xFA,0xCD, ++0x8A,0xDF,0x44,0xC2,0x21,0x1C,0x37,0x97, ++0x8A,0xAF,0x74,0x93,0x35,0x9E,0x37,0x95, ++0xAA,0x9F,0xB6,0x92,0x3F,0x5C,0xD7,0x9E, ++0x68,0x90,0xB6,0xC0,0x85,0x91,0x55,0xC4, ++0xAA,0x9F,0xB6,0xC2,0x25,0x2C,0x77,0xC5, ++0x66,0xBD,0xB6,0xC0,0x24,0x5C,0xD7,0xCE, ++0xAC,0x8F,0x92,0xC1,0x22,0x5C,0x82,0xC5, ++0xAF,0x8E,0x87,0x96,0x25,0x2D,0x57,0x83, ++0xAE,0x8E,0x96,0x96,0x20,0x1C,0x53,0xC6, ++0xA9,0xDF,0x42,0xC0,0xD6,0xA3,0x28,0x9E, ++0xAC,0xCE,0x97,0xC1,0x3E,0x1C,0x1B,0xC7, ++0xAE,0xCF,0x07,0xC4,0x25,0x7C,0x85,0xC4, ++0x9B,0x9D,0xB6,0xC0,0x2D,0x5C,0xD7,0x2E, ++0xAA,0xCF,0xB6,0xC0,0xC3,0xA3,0x28,0xCF, ++0xAA,0x9F,0x92,0xC0,0x29,0x5C,0xD7,0xCE, ++0xA9,0x8E,0x87,0xC6,0x2D,0x3C,0xD2,0xC4, ++0x9F,0x8D,0xB6,0xC0,0x37,0x3B,0x77,0xC5, ++0xAF,0x9F,0x92,0xC0,0x22,0x1D,0x57,0xC3, ++0xAC,0x9F,0xB6,0xC0,0x20,0x6C,0x84,0xC6, ++0x5C,0x20,0xE9,0x0B,0x25,0x5C,0x77,0xC5, ++0x5A,0x5F,0xAB,0xC9,0xDE,0x13,0xFA,0xCD, ++0xAA,0x7F,0xB6,0xC0,0x15,0x8C,0x9A,0xC6, ++0xA8,0xAF,0xB6,0xC0,0x22,0x1C,0x77,0xC5, ++0xA9,0xCF,0xB6,0xC0,0x4D,0x0C,0x4A,0xC1, ++0xE0,0x6D,0xA9,0xE6,0x24,0x7C,0xF5,0xED, ++0xB0,0xFD,0xA9,0xE6,0x07,0x6E,0x55,0xE7, ++0xAC,0xFF,0x34,0xE8,0x06,0x6E,0x55,0xE7, ++0x81,0xFD,0x94,0xE2,0x13,0x7C,0xF5,0xED, ++0x88,0x9D,0x94,0xE2,0x07,0x6E,0x55,0xE7, ++0x8F,0xFD,0x94,0xE2,0x0F,0x7C,0xF5,0xED, ++0x88,0xFD,0x62,0xE0,0x05,0x7E,0xB5,0xE6, ++0xA0,0xFD,0xB9,0xE6,0x03,0x7E,0x15,0x05, ++0x7D,0xFD,0x34,0x09,0x02,0x7E,0xA3,0xE5, ++0xAE,0xFD,0x34,0x19,0x03,0x6E,0x6C,0xE3, ++0x88,0xFD,0x60,0xE0,0x03,0x7E,0xA4,0x15, ++0x88,0xFD,0x94,0x00,0x1D,0x7E,0xF5,0x0C, ++0x8A,0xFC,0x94,0xE0,0x03,0x2E,0x55,0xE5, ++0x88,0xFD,0x25,0xE2,0x00,0x7E,0xF5,0x1C, ++0x89,0xAD,0xB1,0xE1,0x23,0x7E,0xA0,0xE5, ++0x28,0xFD,0x94,0xE2,0xFA,0x81,0x0A,0xBC, ++0x33,0x32,0x3E,0x48,0xAD,0xE4,0xFF,0x4D, ++0x27,0x77,0x3E,0x48,0xAE,0xC4,0xFF,0x4D, ++0x28,0x57,0x3E,0x48,0xD4,0x2B,0xA0,0x47, ++0x28,0x27,0x3E,0x48,0xA1,0xD4,0xD2,0x49, ++0x2A,0x57,0x9E,0x43,0xA1,0xD4,0xC2,0x49, ++0x24,0x67,0x3E,0x48,0xA5,0xF4,0xD2,0x4E, ++0x2A,0x47,0x13,0x4B,0xB9,0xD4,0xD2,0x49, ++0x26,0x56,0x09,0x4E,0xA5,0xD4,0xD2,0x49, ++0x26,0x56,0x14,0x49,0x43,0x2A,0xA0,0x47, ++0x23,0x17,0xCA,0x4B,0x5D,0x2B,0xA0,0x86, ++0x2A,0x57,0x03,0x4C,0x99,0xD1,0xFF,0x4D, ++0x2A,0x57,0x13,0x4C,0x91,0xC4,0xC2,0x49, ++0x22,0x57,0x1F,0x4C,0x62,0xD4,0x5F,0x46, ++0x22,0x57,0xCE,0x4A,0xAD,0xD4,0x5F,0x06, ++0x1A,0x57,0x03,0x4C,0xAD,0xF4,0xFF,0x4D, ++0x25,0x47,0x3E,0x48,0x48,0xD5,0x5F,0x47, ++0x3B,0x8A,0x43,0x9E,0x63,0x09,0x82,0x6B, ++0xF9,0x8A,0xE3,0x95,0x72,0x09,0x82,0x9B, ++0xFF,0x9B,0xD4,0x93,0x74,0x28,0x1B,0x96, ++0xFD,0x8A,0x12,0x95,0x75,0x09,0x22,0xF2, ++0xFB,0x8A,0x43,0xFE,0x74,0x09,0x62,0x42, ++0xFD,0x8A,0x43,0x4E,0x75,0x09,0xD2,0x93, ++0x09,0x75,0xBC,0x5E,0x74,0x09,0x22,0x92, ++0xFF,0x8A,0x13,0x97,0x9F,0xF6,0x7D,0xCB, ++0xF7,0x8A,0x43,0x6E,0x75,0x09,0x22,0x92, ++0xFF,0x9A,0xE3,0x97,0x70,0x09,0xD2,0x90, ++0xFF,0x9B,0xC9,0xC3,0x75,0x09,0x02,0xC3, ++0x04,0x75,0xBC,0xCE,0x75,0x09,0x22,0x92, ++0xFF,0x8A,0xC9,0x91,0xDF,0x09,0x82,0x9B, ++0xFF,0x9A,0xE3,0x97,0x72,0x88,0x0B,0x91, ++0xD3,0x9A,0xCE,0x91,0x76,0x08,0x22,0x92, ++0xFB,0x9A,0x5B,0x91,0x74,0x09,0x93,0x90, ++0x9C,0xEC,0x25,0x08,0x3E,0x4F,0x79,0xF2, ++0x39,0xEC,0x85,0xF3,0x13,0x4F,0x66,0xF5, ++0xB9,0xEC,0x77,0xF1,0x3E,0x4F,0x69,0xF2, ++0x6E,0x13,0xDA,0xA8,0x3E,0x4F,0x79,0xF2, ++0x9F,0xDC,0x85,0xF3,0x1B,0x7F,0x44,0xF6, ++0x90,0xEC,0x85,0xF3,0x25,0x90,0x1B,0xFC, ++0xB1,0xEC,0xB8,0xF7,0x15,0x7F,0x44,0xF6, ++0xB5,0xCC,0xB8,0xF7,0x12,0x5F,0x62,0xF7, ++0xA1,0xEC,0xB8,0xF7,0x23,0x90,0x1B,0xFC, ++0xA1,0xFC,0xB8,0xF7,0x0A,0x6F,0x69,0xF2, ++0x8D,0xFC,0xA8,0xF7,0x3A,0x1F,0x79,0xF2, ++0x99,0xEC,0x72,0xF1,0x68,0x6F,0xE4,0xAD, ++0x8D,0xFC,0xB8,0xF7,0x0E,0x6F,0x69,0xF2, ++0x9F,0xEC,0xA2,0xF2,0x12,0x2F,0x44,0xF4, ++0x81,0xCC,0xA8,0xF0,0x12,0x6E,0x65,0xF7, ++0xB9,0xFC,0xA8,0xF0,0x22,0x6F,0x69,0xF2, ++0xD9,0xA8,0x71,0xB3,0x4E,0x2B,0x2D,0xB6, ++0xF9,0xA8,0xEC,0xB4,0x52,0x1B,0xB8,0xB6, ++0x4A,0x56,0x9E,0xBD,0x56,0x2B,0xF0,0xB0, ++0xD7,0xA8,0x61,0x5C,0x56,0x2B,0x40,0xB0, ++0xF9,0xA8,0xEC,0xB3,0x66,0x2B,0x3D,0xB6, ++0xD9,0xA8,0x71,0xB3,0x76,0x2B,0x2D,0xB6, ++0xD9,0xB8,0x79,0xB3,0x57,0x2B,0x20,0xB3, ++0xFD,0xA8,0xEC,0xB3,0x52,0x3B,0xB8,0xB6, ++0xDD,0xA8,0x30,0xB7,0x57,0x6B,0x00,0xD0, ++0xF9,0xA8,0xFC,0xB3,0x56,0x2B,0xF0,0xB0, ++0xC6,0xA8,0x61,0x5C,0x56,0x2B,0xF4,0xB0, ++0xC4,0xA8,0x61,0x4C,0x66,0x3B,0x3D,0xB6, ++0xD5,0x88,0x79,0xB3,0x5E,0x1B,0xB1,0xB6, ++0xFD,0xB8,0xFC,0xB3,0x9C,0x2A,0xA0,0xB8, ++0xDD,0xA8,0x31,0xB5,0x44,0x2B,0xA0,0x59, ++0xF9,0xA8,0xFC,0xB3,0x76,0x3B,0x3D,0xB6, ++0x10,0x64,0xED,0x78,0xBE,0xE7,0xE1,0x7A, ++0x15,0x64,0xB5,0x7F,0x9A,0xF7,0xED,0x7F, ++0x31,0x74,0x20,0x7F,0x9E,0xE7,0x74,0x7A, ++0x10,0x64,0xFD,0x7B,0x92,0xE7,0x6C,0x15, ++0x21,0x64,0x30,0x7F,0x92,0xC7,0x74,0x7A, ++0x19,0x54,0xBD,0x7F,0xBE,0xE7,0xF1,0x7A, ++0xA8,0x65,0xAD,0x71,0x9A,0xE7,0x3C,0x7C, ++0x35,0x64,0x30,0x8F,0x9B,0xE7,0x2C,0x8D, ++0x35,0x64,0x20,0x8F,0x8E,0xE7,0xF1,0x7A, ++0x16,0x35,0x2D,0x7A,0x86,0xE7,0xF1,0x7A, ++0x1D,0x64,0x20,0x7F,0xBE,0xE7,0xF1,0x7A, ++0x11,0x64,0xFD,0x79,0x8A,0xE7,0xE1,0x7A, ++0x1D,0x64,0x30,0x9F,0x81,0xE7,0x6C,0x95, ++0x11,0xD4,0x0D,0x79,0x91,0xA7,0xCC,0x7E, ++0x05,0x64,0xAD,0x70,0x9E,0xC6,0xF5,0x78, ++0x15,0x64,0x20,0x78,0x8A,0xF7,0xF1,0x7A, ++0xF8,0x30,0xF8,0xDB,0x34,0x4C,0x53,0xD2, ++0xB0,0xDE,0x47,0xD0,0x3B,0x4D,0x26,0xD4, ++0xBF,0xDF,0x82,0xD7,0x30,0x4D,0x97,0xD4, ++0xBF,0xEE,0x9A,0xD5,0x30,0x4D,0x66,0xA6, ++0xBA,0xCE,0xA7,0xB3,0x32,0x5D,0x87,0xD5, ++0xBF,0xDF,0x82,0xD7,0x31,0x0D,0x42,0xD7, ++0xBF,0xEE,0x9A,0xD5,0x32,0x6D,0x26,0xD4, ++0xB9,0xCE,0x56,0xD1,0x38,0x5D,0x5B,0xD0, ++0xBA,0xCE,0x87,0xB2,0x30,0xFD,0x47,0xD5, ++0xBD,0xCE,0x53,0xD1,0xD8,0xB2,0x39,0x8F, ++0xB7,0xCE,0x9A,0xD5,0x3B,0x4D,0x86,0xD5, ++0x9F,0xDE,0x9A,0xD5,0x30,0x4D,0x96,0xD6, ++0xBC,0xDF,0x8D,0xD7,0x23,0x4D,0xC6,0x3F, ++0xBA,0xCE,0x46,0xD2,0x30,0x5D,0x66,0xD6, ++0xBC,0xCF,0x8D,0xD7,0x31,0x4D,0x66,0xD4, ++0xB7,0xCE,0x07,0xDA,0x30,0x6C,0x53,0xD2, ++0x89,0xDD,0xB6,0xE3,0x03,0x5F,0x70,0xE1, ++0x89,0xFD,0x66,0xE2,0x03,0x4F,0x6C,0xE1, ++0x88,0xED,0x94,0x20,0x02,0x6E,0x55,0x35, ++0x8B,0xDD,0xB6,0xE3,0x03,0x5F,0x70,0xE1, ++0x88,0xCC,0xAD,0xE4,0x02,0x7E,0x75,0xE4, ++0x8B,0xFD,0x66,0xE2,0x02,0x6E,0x74,0x34, ++0x8E,0xFD,0x64,0xE2,0xF3,0x81,0x0A,0xBC, ++0xB8,0xFD,0xA9,0xE6,0x02,0x0E,0xA2,0xE4, ++0x8C,0xFD,0x24,0xE6,0x1B,0x7E,0x78,0xE3, ++0x0C,0x02,0xCB,0x59,0x2B,0x6E,0x68,0xE3, ++0x8E,0xFD,0x94,0xE2,0x03,0x4E,0x55,0xE5, ++0x8E,0xED,0xB5,0xE3,0x03,0x7E,0xA4,0xE7, ++0x9C,0xDD,0xA9,0xC6,0x03,0x4F,0x77,0xC1, ++0x89,0xFD,0xB4,0xC1,0xF9,0x81,0x0A,0xCC, ++0xB0,0xED,0xA9,0xE6,0x2F,0x5E,0x68,0xE3, ++0x8E,0xCD,0x94,0xE2,0x02,0x7E,0x55,0xE7, ++0x54,0x12,0xDA,0xF9,0x3E,0x4F,0x79,0xF2, ++0x9F,0xDC,0x85,0xF3,0x1B,0x7F,0x44,0xF6, ++0x90,0xEC,0x85,0xF3,0xDA,0x91,0x1B,0xFC, ++0x99,0xEC,0x85,0xF1,0x56,0xBF,0x69,0xF5, ++0x69,0x63,0x98,0xFA,0xE5,0x20,0xC9,0xFE, ++0x99,0x8C,0x85,0xF3,0x12,0x6F,0x44,0xF4, ++0x91,0x3C,0x68,0xF0,0x10,0xCF,0x44,0xF6, ++0x1B,0xFC,0x85,0xF3,0x12,0x4F,0x44,0xF6, ++0x98,0xEC,0x75,0xF3,0x12,0x4E,0x62,0xA0, ++0x98,0xEC,0xA5,0xA0,0xE9,0x90,0x1B,0xAD, ++0x99,0xAC,0x85,0xF1,0x13,0xDF,0xA5,0xF5, ++0x9D,0xBC,0x85,0xF3,0x4E,0x6F,0xE4,0xFD, ++0x95,0xEC,0xB8,0xF7,0x97,0x1F,0x44,0xF6, ++0x9C,0xFD,0xB5,0xF5,0x1F,0x6F,0x44,0xF6, ++0x98,0xCC,0x85,0xF3,0xF4,0x92,0x1B,0xFC, ++0x99,0xEC,0xB8,0xF7,0x12,0xEF,0x44,0xF4, ++0x07,0x64,0x2A,0x6C,0x8A,0xF6,0xFD,0x6E, ++0x00,0x75,0x31,0x6E,0x8C,0xE7,0xEB,0x69, ++0x01,0x75,0xEC,0x6A,0x8F,0xF6,0xE0,0xBB, ++0x01,0x75,0x3C,0xB9,0x8F,0xF6,0xF0,0xBB, ++0x0B,0x75,0xEB,0x6A,0x8C,0xF6,0x7D,0x94, ++0x00,0x75,0xE8,0x68,0x8E,0xF6,0x7D,0x84, ++0x04,0x75,0x21,0x6E,0x8F,0xF6,0xFD,0x6E, ++0x04,0x75,0xEC,0x6A,0x8B,0xB6,0xDD,0x6D, ++0x01,0xF5,0x1C,0xB8,0x8F,0xF6,0xF0,0x6B, ++0x00,0x75,0x21,0x6E,0x8C,0xF7,0xFB,0x69, ++0x01,0x05,0x39,0x69,0x8F,0x66,0xE0,0x6B, ++0x37,0x75,0xBC,0x61,0x87,0xF6,0xE0,0x6B, ++0x05,0x54,0x2C,0x6C,0x8C,0xE7,0xED,0x69, ++0x0D,0x75,0x1C,0x6A,0x43,0x0B,0x82,0x65, ++0x00,0x55,0x21,0x6E,0x8B,0xF6,0xE0,0x6B, ++0x82,0x55,0x1C,0x6A,0x8B,0xD6,0xF0,0x6B, ++0xC6,0x0C,0x7A,0x0C,0xE9,0xB0,0x86,0x0D, ++0x62,0x13,0x47,0x08,0x6F,0x80,0x9A,0x09, ++0x62,0x03,0x57,0x08,0x4D,0x9F,0xBB,0x09, ++0x66,0x03,0x47,0x08,0xE4,0x80,0x9A,0x08, ++0x6F,0x13,0x8B,0x0C,0xED,0x80,0x96,0x0D, ++0x65,0x13,0xDA,0xC7,0xE9,0x80,0x86,0x0D, ++0x67,0x03,0x4B,0x0F,0xEC,0x90,0x9B,0xEA, ++0x62,0x03,0x57,0x08,0xE9,0x80,0x86,0x0D, ++0x66,0x33,0x47,0x08,0xE5,0x80,0x9A,0x08, ++0x6E,0x13,0x8B,0x0C,0xE9,0x80,0x96,0x0D, ++0x61,0x03,0x5F,0x0D,0xEC,0x90,0x9B,0xDA, ++0x67,0x22,0x4C,0x0A,0xEE,0xB0,0x99,0x08, ++0x66,0x33,0x57,0x08,0xEC,0xA1,0x8D,0x0F, ++0x65,0x13,0x88,0x0C,0xEE,0x90,0x1B,0xC2, ++0x62,0x33,0x47,0x08,0xEC,0xB0,0x89,0x0A, ++0x67,0x13,0x5A,0xEF,0xE9,0xB0,0x96,0x0D, ++0xF4,0x8A,0x12,0x95,0x73,0x09,0x82,0x6B, ++0xFF,0x8A,0x17,0x97,0x71,0x09,0x82,0x7B, ++0xFB,0xAA,0xDE,0x91,0x70,0x29,0x00,0x91, ++0xFB,0x8A,0x11,0x95,0x74,0x49,0x22,0x92, ++0xFE,0x8A,0xC3,0x46,0x70,0x29,0x0F,0x94, ++0xFF,0xAA,0xDE,0x91,0x74,0x89,0x22,0x90, ++0xFE,0xFA,0xC4,0x96,0x75,0x28,0x04,0x96, ++0xFB,0x1A,0xDE,0x91,0x7E,0x09,0xD5,0x90, ++0x3A,0x75,0xBC,0xCE,0x7E,0xB9,0x07,0x91, ++0xF7,0xCA,0xE3,0x95,0x75,0x59,0x07,0x93, ++0xF4,0x1B,0xC5,0x93,0x7E,0x09,0xD7,0x90, ++0x5F,0x75,0xBC,0xCE,0x60,0xD9,0x0F,0x93, ++0xFF,0x8A,0xE3,0x97,0x84,0x86,0x3F,0x99, ++0x01,0xC5,0x6E,0x9D,0x74,0x99,0x22,0x90, ++0xFE,0x2A,0xE3,0x95,0x76,0x69,0x22,0x90, ++0xCF,0xFA,0xDE,0x91,0x77,0x49,0x22,0x90, ++0x44,0x31,0xAF,0x2C,0xCF,0xB2,0xD9,0xC9, ++0x17,0x31,0xF8,0xC5,0xB7,0xB6,0xA6,0x2F, ++0xC3,0xB1,0x58,0x2E,0xC7,0xA2,0x99,0x2B, ++0xE6,0x31,0xF8,0x24,0xA3,0xB6,0xA6,0x2F, ++0x4C,0x21,0x58,0x2E,0x50,0xB2,0x39,0x21, ++0x20,0x35,0x67,0x2A,0xC7,0xA2,0x99,0x2B, ++0xD8,0x31,0xF8,0x24,0x93,0xB6,0xA6,0x2F, ++0x43,0x21,0x58,0x2E,0x56,0xB2,0x39,0x21, ++0x10,0x35,0x67,0x2A,0xC8,0xA2,0x99,0x2B, ++0xD2,0x31,0xF8,0x24,0x8B,0xB6,0xA6,0x2F, ++0x43,0x11,0x58,0x2E,0xCB,0xA2,0x99,0x2B, ++0xCE,0x31,0xF8,0x24,0xC8,0xA2,0x99,0x2B, ++0x42,0x31,0x58,0x2E,0xB1,0xB2,0x39,0x21, ++0x44,0x71,0x58,0x2E,0xCD,0xB3,0x99,0x29, ++0x40,0x20,0x7E,0x2F,0xCB,0xA2,0x28,0x2F, ++0x44,0x31,0xE9,0x2E,0xCD,0xB2,0x39,0xD0, ++0xD7,0x02,0x7B,0x1D,0x07,0x7E,0xF5,0xE3, ++0x74,0x02,0xCB,0x16,0xFD,0x81,0x5A,0x1A, ++0x75,0x53,0x6B,0xFF,0xFD,0xC1,0x4E,0xFB, ++0x77,0x02,0xCB,0xF6,0x5C,0xD1,0xAA,0x18, ++0x83,0x01,0x54,0x19,0xFB,0xA1,0xAA,0x18, ++0x7D,0x12,0x6B,0x1D,0x89,0x81,0x0A,0x12, ++0x55,0x02,0xCB,0x16,0x1C,0x92,0x95,0x1C, ++0x70,0x22,0x6B,0x1D,0xFB,0x8A,0x4B,0x1B, ++0x20,0xFD,0x34,0x17,0x34,0xB2,0x95,0x1C, ++0x75,0x29,0x88,0x1E,0x08,0xA1,0xC7,0x18, ++0x75,0x39,0x48,0x1E,0xFC,0xF1,0x87,0x1C, ++0x7F,0x22,0x6B,0x1D,0xFA,0x9A,0x49,0x1B, ++0x76,0x09,0x48,0x1E,0x47,0x81,0x0A,0x12, ++0x73,0x03,0x4D,0x1C,0xF8,0x81,0x1A,0x1C, ++0x72,0x02,0xDB,0x1D,0xF1,0x81,0x0A,0xF3, ++0x70,0x32,0x6B,0x1D,0x64,0x92,0x95,0x1C, ++0x28,0x77,0x3E,0x48,0xAE,0xDF,0x1E,0x4E, ++0x4E,0x57,0x9E,0x42,0x29,0xE7,0xC0,0x49, ++0x20,0x7C,0xDD,0x4B,0x5D,0xF4,0x92,0x4D, ++0x20,0x6C,0x1D,0x4B,0xA9,0xA4,0xD2,0x49, ++0x2A,0x77,0x3E,0x48,0xAF,0xCF,0x1C,0x4E, ++0x23,0x5C,0x1D,0x4B,0x00,0xD4,0x5F,0x47, ++0x23,0x57,0xCB,0x4A,0x0C,0x84,0xFF,0xBD, ++0x20,0x06,0x3E,0xAA,0xA8,0x94,0x1B,0xAE, ++0x22,0x57,0xCA,0x4A,0x73,0x2B,0xA0,0xB6, ++0x25,0x77,0x3E,0x48,0xE1,0xC7,0xC0,0x49, ++0x2B,0x57,0x3E,0x48,0xE2,0xD4,0x5F,0x47, ++0x22,0x57,0x3E,0x4A,0x57,0x5B,0xE2,0x44, ++0xD2,0x08,0xB3,0x40,0xA9,0x74,0xFF,0x4D, ++0x63,0x8A,0xD3,0x4B,0xA8,0x64,0xFF,0x4D, ++0x13,0x1A,0x13,0x4B,0xAB,0x54,0xFF,0x4D, ++0x21,0xC7,0x3E,0x48,0xA8,0xC8,0xFF,0x4F, ++0xEA,0x9B,0xF2,0x84,0x22,0x18,0x93,0x8B, ++0xCF,0xC6,0xDF,0x87,0x64,0x04,0x33,0x83, ++0xEB,0x9B,0xF2,0x84,0x26,0x18,0x93,0x8B, ++0xFF,0xF6,0xDF,0x87,0x64,0x04,0x33,0x83, ++0xE8,0x9B,0xF2,0x84,0x5A,0x18,0x93,0x8B, ++0xAE,0xEB,0xDF,0x87,0x64,0x04,0x33,0x83, ++0xE9,0x9B,0xF2,0x84,0x5E,0x18,0x93,0x8B, ++0xEF,0xA7,0xF2,0x86,0x6F,0x38,0x33,0x81, ++0xED,0x8B,0xF2,0x84,0x61,0x18,0x33,0x81, ++0x7A,0x9B,0x52,0x8E,0x64,0x24,0x33,0x83, ++0xE5,0xBB,0xF2,0x84,0x66,0x08,0x33,0x81, ++0xEB,0x9B,0xF2,0x84,0xEA,0x18,0x93,0x8B, ++0xEA,0xAB,0xF2,0x86,0x6D,0x38,0x33,0x81, ++0xEF,0x87,0xF2,0x86,0x63,0x18,0x33,0x81, ++0x64,0x9B,0x52,0x8E,0x64,0x24,0x33,0x83, ++0xE8,0xBB,0xF2,0x84,0x65,0x28,0x1E,0x85, ++0x05,0x45,0x1C,0x6A,0x8F,0xE6,0xDD,0x6F, ++0x07,0x75,0x1C,0x6A,0xFE,0x09,0x82,0x65, ++0x01,0x59,0x1C,0x68,0x8C,0xE6,0xDD,0x6F, ++0x09,0x75,0x1C,0x6A,0x49,0xF7,0x7D,0x65, ++0x41,0xA8,0x31,0x69,0x8B,0xF6,0xDD,0x6D, ++0xF0,0xEA,0x01,0x63,0x1A,0xF5,0x7E,0x6E, ++0x91,0x77,0xBD,0x6B,0x8A,0xDE,0xFE,0x6E, ++0x00,0x45,0x2C,0x6E,0x89,0xC6,0x3E,0x6E, ++0x02,0x55,0x5C,0x6A,0x8B,0xC6,0xFD,0x6B, ++0x02,0x75,0xEF,0x6A,0x8F,0xD6,0xED,0x6B, ++0x01,0x55,0xFE,0x09,0xAA,0xEE,0x3F,0x6E, ++0x04,0x55,0x3C,0x0E,0x8F,0xE6,0xFD,0x6B, ++0x1E,0x8A,0x93,0x6A,0x88,0xF6,0x7D,0x64, ++0x01,0x54,0x2C,0x6C,0x8B,0xF6,0x2F,0x6D, ++0x01,0x75,0x3D,0x99,0x95,0x09,0x52,0x9F, ++0x01,0x65,0xED,0x69,0x72,0x09,0x82,0xA4, ++0x66,0x13,0x7A,0x0E,0xF3,0x6F,0x34,0x09, ++0x66,0x23,0x7A,0x0E,0xFD,0xD0,0x36,0x01, ++0x64,0x13,0x89,0x0C,0xEE,0xD1,0x8A,0x5F, ++0x65,0x52,0x5A,0x5A,0xEC,0xA0,0x98,0x5A, ++0x9C,0xEC,0x25,0x57,0xFD,0x10,0xA6,0x00, ++0x66,0x33,0x7A,0x0E,0xEC,0x80,0x5A,0x0A, ++0x67,0x13,0xAB,0x0E,0xEC,0xB1,0x9B,0xFF, ++0x9D,0xEC,0x25,0xF7,0xF3,0x6F,0x34,0x09, ++0x9A,0x4C,0xF7,0x04,0xED,0xF0,0xBB,0x09, ++0x66,0x13,0x7A,0x0E,0xEC,0x30,0xBB,0x09, ++0x64,0x83,0x7A,0x0C,0xEE,0x10,0xBB,0x09, ++0x66,0xA3,0x7A,0x0C,0x65,0x90,0x4B,0x09, ++0x66,0xA2,0x5C,0x5A,0xEC,0x90,0x9B,0x5A, ++0x9D,0xEC,0x25,0x57,0xED,0xD0,0xBB,0x0B, ++0x43,0x13,0xDA,0x07,0xE9,0x91,0x82,0x0F, ++0x66,0x13,0x8A,0x0E,0xED,0xE0,0xBB,0xFB, ++0x70,0x52,0x6B,0xED,0xE7,0x81,0x0A,0xE3, ++0x7F,0x02,0x4F,0x1C,0xFC,0x30,0x8C,0x1E, ++0x6B,0x02,0xCB,0x16,0xF8,0xA0,0x93,0x1E, ++0x7A,0x02,0x6B,0x1D,0xF9,0x90,0x90,0x1E, ++0xCC,0xFE,0x34,0x17,0xFC,0x81,0x97,0x1C, ++0x70,0x02,0x4B,0x1C,0xFB,0x81,0x5A,0x18, ++0x77,0x02,0x46,0x19,0xF8,0x81,0x97,0xCC, ++0x77,0x12,0x56,0x19,0xFD,0x81,0x8A,0xCB, ++0x73,0x02,0x46,0xC9,0xF8,0x81,0x8F,0x19, ++0x76,0x52,0x4E,0x1E,0xFC,0xA0,0x9C,0x1E, ++0x75,0x12,0x4A,0x1C,0xFC,0x91,0x87,0x1C, ++0x77,0x23,0x5D,0x1B,0xFE,0x81,0x5B,0x18, ++0x73,0x12,0x56,0xC9,0xFD,0x91,0x8B,0xCB, ++0x73,0x12,0x46,0xC9,0xFC,0x91,0x97,0x1C, ++0x77,0x13,0x4D,0x1B,0xF8,0xF1,0x97,0x1C, ++0x7F,0x02,0x9E,0x1D,0x18,0x7E,0xF5,0x43, ++0xD5,0xA8,0xE5,0xB6,0x56,0x5A,0x26,0xB4, ++0xDC,0xE8,0xE5,0xB4,0x5E,0x2B,0xF4,0xB2, ++0x0A,0x57,0x9E,0xEC,0x56,0x2B,0x00,0xB0, ++0x21,0x37,0xDC,0xBE,0x2A,0x6B,0x8D,0xBA, ++0xDC,0xE8,0xC1,0xB7,0x56,0x3B,0x00,0xB2, ++0xDE,0xF8,0xC1,0xB7,0x5B,0x2B,0x00,0xB2, ++0x4A,0x54,0x9E,0xBD,0x52,0x2B,0x3D,0xB6, ++0xD9,0xA8,0x31,0xB7,0x55,0x2B,0xA0,0x69, ++0xDD,0xA8,0xFC,0xC3,0x53,0x2B,0xF0,0xC2, ++0xDC,0xA8,0xC1,0xD5,0x56,0x2B,0xA0,0xD9, ++0xDD,0xA8,0xC1,0xB5,0x2A,0xAB,0x1D,0xBB, ++0x21,0xE9,0x4C,0xBF,0x54,0x5B,0x00,0xB2, ++0xDD,0xE8,0xC1,0xB7,0x55,0x0B,0x00,0xB2, ++0xFD,0xF8,0xFC,0xB3,0x51,0x1B,0x00,0xB2, ++0xF9,0xA8,0xFC,0xB3,0x7E,0x4B,0x3D,0xB6, ++0xF9,0xA8,0xEC,0xBE,0x57,0x0B,0x00,0xB2, ++0x53,0x30,0x49,0x3F,0xA8,0x5E,0xD7,0x30, ++0x50,0x00,0x49,0x3F,0xD8,0xB3,0x88,0x3A, ++0x51,0x20,0x49,0x3F,0x45,0x5C,0xD7,0x30, ++0x55,0x20,0x49,0x3D,0x22,0x22,0x95,0x33, ++0xA5,0x61,0xC4,0x37,0xDE,0xF3,0x88,0x3A, ++0x54,0x40,0x49,0x3F,0xDC,0xE3,0x88,0x3A, ++0x56,0x50,0x49,0x3F,0x45,0x5C,0xD7,0x30, ++0x55,0x20,0x49,0x3D,0xDF,0xB3,0x6F,0x39, ++0x59,0x20,0xE9,0x34,0xDE,0x93,0x88,0x38, ++0x56,0x00,0x49,0x3F,0xDD,0xA3,0x28,0x31, ++0x54,0x50,0x3D,0x39,0xDF,0xB3,0x69,0x39, ++0x42,0x12,0x6A,0x3F,0xD6,0x83,0xAA,0x39, ++0x55,0x20,0xB8,0x3D,0xDF,0xA3,0x28,0x61, ++0x75,0x20,0xBB,0x3D,0x29,0x5C,0xD7,0x61, ++0x55,0x11,0x6C,0x39,0xDF,0xA3,0xA8,0x39, ++0x53,0x20,0xB9,0x3F,0x2E,0x22,0x95,0x73, ++0x55,0x20,0xB8,0x3D,0x30,0x5C,0xD7,0x71, ++0xA5,0xA1,0x54,0x36,0xFE,0x2C,0x2A,0xFB, ++0x75,0xB7,0xEB,0xFE,0xFE,0x3C,0x2A,0xFB, ++0x75,0x87,0xEB,0xFE,0xFE,0x08,0x2A,0xFB, ++0x55,0x10,0x49,0x3F,0x21,0xB3,0x29,0x39, ++0x54,0x00,0xAB,0x3C,0xDF,0xA3,0x5A,0x38, ++0x54,0x30,0x2A,0xCA,0x25,0x5C,0xD7,0xC1, ++0x4B,0xDF,0xC6,0x3F,0x06,0xA2,0xB7,0x3E, ++0x11,0x20,0x79,0x3B,0xDE,0xA3,0xC8,0x3A, ++0x4B,0xDF,0xC6,0x3F,0x2E,0xE2,0x05,0x32, ++0x54,0xA0,0x49,0x3D,0xDF,0xE3,0x88,0x3A, ++0xF4,0x38,0x61,0x3E,0xDF,0xA3,0x79,0x38, ++0x57,0x50,0x49,0x3F,0x6A,0x82,0xB7,0x5E, ++0xE5,0x41,0x76,0x4B,0x4F,0xA1,0x2E,0x5B, ++0xF9,0x31,0x76,0x3B,0xFA,0x87,0x88,0x3A, ++0x55,0x60,0x28,0x3B,0x9F,0xBB,0xA9,0x3A, ++0x33,0x66,0x4E,0x5D,0xB9,0xD5,0xCF,0x5F, ++0x17,0x6E,0x2F,0x59,0xB8,0xE5,0x8F,0x58, ++0xF2,0x50,0x0E,0x59,0x9C,0xE9,0xEE,0x5C, ++0x33,0x66,0x4E,0x5D,0xB9,0xD5,0xCF,0x5F, ++0x13,0x62,0x2F,0x59,0xB8,0xC5,0x8F,0x58, ++0x72,0x5E,0x0E,0x59,0xB8,0xE5,0x8F,0x58, ++0x32,0x56,0x0E,0x5A,0x98,0xED,0xEE,0x5C, ++0x13,0x4A,0x2F,0x59,0xB8,0xE5,0x8F,0x58, ++0xF2,0x50,0x0E,0x59,0xB8,0xC5,0x8F,0x58, ++0x35,0x56,0x2F,0x59,0xED,0xCA,0xC1,0x5F, ++0x59,0xBF,0x70,0x53,0xD8,0xC4,0xD1,0x58, ++0xCB,0x69,0x88,0x5B,0xBA,0xD9,0xEE,0x5E, ++0x33,0x86,0x2F,0x5B,0x00,0xE3,0x8E,0x5C, ++0x32,0x66,0x8D,0x5B,0x04,0xE3,0x8E,0x5C, ++0x87,0xC0,0x4F,0x59,0x08,0x82,0x8E,0x5C, ++0x17,0x6E,0x2F,0x59,0x0C,0xE2,0x8E,0x5C, ++0x7C,0xAF,0xB0,0xA6,0x73,0x7B,0x2E,0xA7, ++0x3C,0xB7,0xE4,0xA2,0x45,0x32,0x31,0xA1, ++0x3C,0xB7,0xF4,0xA2,0x57,0xF4,0x35,0xA7, ++0xDC,0x37,0xF4,0xA2,0x81,0xC5,0x4E,0xA9, ++0xCA,0x99,0xF0,0xA7,0x5B,0x34,0x25,0xA7, ++0xCD,0xB9,0x70,0xA5,0x46,0x3A,0xE1,0xA1, ++0xCF,0xB9,0x70,0x4D,0x87,0xC5,0x4E,0xA9, ++0xCE,0xB9,0x20,0xA6,0x47,0x6A,0x11,0xA3, ++0x3B,0x46,0x8F,0x7D,0x45,0x3A,0xE4,0xA3, ++0xC0,0x89,0xD0,0x76,0x47,0x1A,0x11,0x71, ++0xD8,0xB9,0x70,0x7D,0x42,0x2A,0x11,0xA3, ++0x28,0xB9,0xFF,0xA5,0x00,0xC3,0x4E,0xA9, ++0x8D,0xB6,0xFF,0xA5,0x61,0x3A,0xB1,0xA8, ++0x60,0xB9,0xF2,0xA7,0x47,0x3B,0x35,0xA2, ++0xEC,0x57,0xE0,0xA2,0x47,0x2A,0x11,0xA1, ++0xCE,0x38,0xF1,0xA7,0xC6,0x3B,0x11,0xA3, ++0x2F,0x64,0x0D,0x7B,0x92,0xE7,0xAB,0x78, ++0x10,0x64,0x2C,0x78,0xEA,0xF7,0x93,0x79, ++0x15,0x64,0xFC,0x79,0x6D,0x18,0x93,0xA5, ++0x13,0x64,0x2E,0x78,0xEA,0xD7,0x93,0x79, ++0x10,0x64,0x2F,0x78,0xEA,0xC7,0x93,0x79, ++0x1E,0x64,0xFE,0x79,0x77,0x18,0x93,0x05, ++0x51,0x64,0x0D,0x79,0x8A,0xE9,0xE8,0x7A, ++0x8E,0x9B,0x52,0x71,0x9C,0xC7,0xEC,0x7F, ++0x0D,0x6A,0x39,0x7F,0x98,0xE7,0x7C,0x7C, ++0x12,0x64,0xAD,0x90,0x00,0x18,0x93,0x74, ++0x13,0x64,0xFD,0x7B,0x9A,0xB7,0xCC,0x7E, ++0xE9,0x9B,0x52,0xA0,0x98,0xE7,0x39,0x7E, ++0xE1,0x6A,0x39,0xAF,0x98,0xEF,0xAC,0xAC, ++0xE1,0x6A,0x29,0xAF,0x9A,0xE7,0xCC,0xAC, ++0xE1,0xE5,0x10,0xA2,0x9F,0xF7,0xCC,0x7E, ++0x6D,0x64,0x22,0x78,0x85,0x1E,0x93,0x74, ++0xD8,0x31,0x77,0x2D,0xD2,0x4B,0xC6,0x21, ++0xB4,0x3F,0x6C,0x2A,0xCD,0xBA,0xF9,0x29, ++0xB4,0x3F,0x7C,0x2A,0xCA,0xB2,0x99,0x29, ++0xB4,0xB0,0x45,0x27,0xCF,0x92,0x09,0xEF, ++0xE4,0xC6,0xFB,0xCF,0x37,0xCD,0x38,0xEA, ++0x00,0x54,0x94,0xAE,0xB6,0x92,0x6D,0xA3, ++0x27,0x5A,0x8B,0xF2,0xFF,0xCA,0x1C,0xB2, ++0x4E,0x31,0xF8,0xCF,0xCF,0xD1,0x39,0xEF, ++0x44,0x21,0xC8,0xEA,0xFE,0x92,0x7A,0xBF, ++0x36,0x65,0x91,0xAC,0xA4,0xC1,0x04,0xFA, ++0x3C,0x14,0x80,0xE3,0xEF,0xE5,0x58,0xA3, ++0x30,0x64,0x96,0xBB,0xA6,0xDE,0x6D,0xA3, ++0x27,0x5A,0x8B,0xF2,0xFF,0xCA,0x1C,0xB2, ++0x4E,0x31,0xF8,0xCF,0xA7,0xD3,0x4A,0xA2, ++0x64,0x45,0x91,0xA2,0xAA,0x92,0x56,0xBF, ++0x30,0x3B,0xF8,0xCF,0xFD,0x92,0x7A,0xBF, ++0xAF,0xFC,0x08,0x35,0x3D,0x58,0x9D,0x63, ++0xA5,0x8D,0x19,0x7A,0x76,0x7C,0xC1,0x3A, ++0xA9,0xFD,0x0F,0x22,0x3F,0x47,0xF4,0x3A, ++0xBE,0xC3,0x12,0x6B,0x66,0x53,0x85,0x2B, ++0xD7,0xA8,0x61,0x56,0x35,0x47,0xC5,0x32, ++0xAF,0x88,0x15,0x3F,0x3B,0x4E,0xD2,0x73, ++0xB2,0xDD,0x15,0x5C,0x56,0x2B,0xA0,0x53, ++0xC3,0x57,0x4E,0xB7,0x2A,0x9E,0xAC,0x53, ++0xC8,0xA8,0x61,0x7F,0x56,0xBB,0xA1,0x83, ++0xDD,0xB1,0x21,0x48,0x3C,0x6D,0xA7,0x1A, ++0xA4,0xEC,0x60,0xC6,0x7E,0x2B,0xA0,0xA3, ++0x35,0x52,0x64,0x56,0x56,0x07,0xA3,0x83, ++0xB4,0xEE,0x61,0x76,0x56,0xDB,0x54,0xA9, ++0xF5,0xA8,0x1D,0xEB,0x51,0x2D,0xA0,0x53, ++0xDC,0x68,0xEE,0xB4,0x4A,0xD4,0x8F,0xB2, ++0x2A,0x1D,0xE3,0xE6,0x59,0x2B,0xA2,0xCF, ++0xEE,0xBD,0x52,0x95,0x6B,0xF2,0x92,0xF0, ++0xEE,0xF3,0x52,0xF5,0x40,0x60,0xF7,0x7C, ++0xEE,0xB6,0x57,0xB5,0x65,0xE8,0x6B,0x89, ++0xEE,0xF3,0x12,0x38,0xA5,0x1F,0x66,0xB1, ++0xC5,0xB6,0x54,0xB5,0x48,0x35,0x90,0xB1, ++0xEF,0xBB,0xD2,0x67,0x63,0x5B,0x93,0x80, ++0x8A,0x85,0x53,0xFD,0x65,0x39,0x92,0x00, ++0xEA,0x01,0x6B,0x65,0x45,0x18,0x93,0x90, ++0x07,0x67,0x53,0x65,0x65,0x37,0x97,0xB0, ++0xD6,0xF3,0xF2,0x27,0x64,0xC9,0x91,0xF8, ++0xD6,0xFB,0x53,0xFD,0x65,0x70,0x91,0x48, ++0xEB,0x4B,0x53,0xFD,0x65,0x82,0x91,0x00, ++0xA6,0xD9,0x20,0x60,0x65,0xCC,0x9B,0x60, ++0xEB,0x2B,0xA2,0xD8,0x64,0x28,0x13,0x81, ++0xFE,0xDB,0x7F,0x8C,0x66,0x18,0x80,0x83, ++0xF0,0x9B,0x52,0x7F,0xA1,0x58,0x0C,0x85, ++0xFB,0x8A,0x11,0x97,0x6F,0x09,0x82,0x4B, ++0xFB,0xBA,0xD3,0x90,0x70,0xC9,0x13,0x95, ++0xFB,0xAA,0x01,0x96,0x87,0xE6,0xE6,0x97, ++0xFF,0x8A,0x1D,0x97,0x71,0x09,0x82,0x6B, ++0xF3,0x8A,0x10,0x95,0x81,0xF6,0x7D,0x7B, ++0xCC,0x85,0xFC,0x92,0x48,0x16,0x3D,0x97, ++0xFE,0x8A,0x03,0x94,0x64,0x89,0x3F,0x99, ++0x00,0x8A,0x40,0x96,0x8B,0x19,0x8E,0x93, ++0xFE,0x8A,0x03,0x94,0x7A,0x15,0x12,0x90, ++0x8C,0x8A,0xBC,0x72,0x08,0x19,0x7D,0x77, ++0xFE,0x8A,0x03,0x74,0x7A,0x11,0x12,0x70, ++0x00,0x9E,0x80,0x77,0x8B,0x0D,0x4E,0x72, ++0xFF,0x8A,0x02,0x74,0x7A,0x1D,0x12,0x70, ++0xEF,0x0A,0xFE,0x6C,0x57,0x05,0x22,0x90, ++0xD3,0x86,0x03,0x94,0x64,0x89,0x3F,0x99, ++0xFF,0x8A,0x11,0x97,0x74,0x09,0x22,0x72, ++0x76,0x93,0x67,0xE5,0xEC,0xA0,0xCB,0x0C, ++0x67,0xD3,0x0B,0x09,0xED,0x90,0x48,0x0B, ++0x6C,0x13,0xDA,0xE7,0xE1,0x90,0x48,0x09, ++0x6E,0x13,0xDA,0xF7,0xEC,0xB0,0x49,0x0A, ++0x67,0x23,0x0A,0xF9,0xEC,0x50,0xCA,0xFC, ++0x66,0x13,0x89,0xFE,0xEE,0x90,0x1B,0xE2, ++0x6A,0x13,0x89,0x0C,0xEC,0x90,0x1B,0xF2, ++0x67,0x33,0x88,0x0F,0x1D,0x6F,0xE4,0xF2, ++0x6A,0x13,0x99,0x0D,0xFD,0x10,0xA6,0x00, ++0x67,0x12,0xDB,0xEC,0xEC,0xB0,0x9B,0x0A, ++0x65,0x13,0xDA,0x07,0xEC,0x80,0xCB,0x0C, ++0x66,0x13,0x8B,0x0E,0xEF,0x90,0x5B,0xE8, ++0x78,0xEC,0xF5,0xEC,0xEE,0x90,0x0B,0x0B, ++0x9F,0xEC,0x25,0xF7,0xD9,0xA0,0x84,0x0D, ++0x62,0x03,0x4A,0x09,0x1C,0x8F,0x78,0x0E, ++0x66,0x13,0x8B,0x0E,0x16,0x6F,0xE4,0xE2, ++0x9B,0xEC,0x65,0xF2,0x13,0x43,0x54,0xF6, ++0x9A,0xEC,0x65,0x00,0x0C,0x90,0xCB,0x06, ++0x98,0xC4,0x95,0xF3,0x10,0x6F,0xA4,0x05, ++0x87,0x13,0x0A,0x03,0x13,0x7B,0x54,0xF6, ++0x98,0xEC,0x65,0x00,0x0C,0x90,0xCB,0xF6, ++0x98,0xED,0x24,0x13,0x11,0x6F,0xB6,0xF4, ++0x8E,0xEC,0x25,0x88,0x11,0xAF,0xF4,0xF5, ++0x91,0xEC,0x25,0x18,0x13,0x5F,0x35,0xF3, ++0x9B,0xEC,0x79,0xF1,0x1E,0x4F,0x66,0xF7, ++0x98,0x2C,0xF4,0x86,0x13,0x5F,0x24,0xF3, ++0x98,0xDC,0xF4,0x26,0x13,0xAF,0x24,0x83, ++0x9D,0xCC,0x67,0xF0,0x13,0x5F,0x24,0x23, ++0x9A,0xDC,0x34,0xF0,0x5A,0x6D,0xE4,0x1D, ++0x91,0xCC,0x77,0xF0,0x16,0x6F,0xE4,0x2D, ++0x9D,0xDC,0xB4,0xF6,0x16,0xAF,0x75,0xF3, ++0x9D,0xDC,0xA5,0xF6,0x16,0xAF,0x64,0xF3, ++0x07,0x75,0xBC,0x9E,0x70,0x29,0x10,0x93, ++0xFB,0xBA,0xD2,0x20,0x70,0x39,0x02,0x25, ++0xFF,0x8A,0xE3,0x95,0xF6,0x26,0x32,0x90, ++0xFE,0xBA,0x92,0x50,0x75,0xC9,0x53,0x55, ++0xFE,0xAA,0x92,0x30,0x75,0x39,0x42,0x55, ++0xFE,0x4A,0x83,0x50,0x75,0x29,0x42,0x35, ++0xE1,0x75,0x6C,0x95,0x8B,0x39,0x80,0x93, ++0xFC,0xAE,0xC0,0x95,0x76,0x21,0x00,0x90, ++0xFF,0x8A,0x43,0x9E,0x74,0x29,0x22,0x92, ++0xFB,0x8A,0x12,0x97,0x73,0x09,0x82,0x4B, ++0xFC,0x4A,0x53,0x96,0x6C,0x0B,0x82,0x7B, ++0xFB,0x4A,0x2F,0x96,0x76,0x09,0xDE,0x92, ++0xFE,0xAA,0x83,0x60,0x78,0x19,0xC3,0x91, ++0x4D,0xAA,0x83,0xD4,0x66,0x0B,0x82,0x9B, ++0x7E,0x45,0xF3,0x95,0x75,0x29,0x42,0x55, ++0xFE,0xAA,0x83,0x50,0x75,0x29,0x42,0x35, ++0xA5,0x31,0x28,0xD1,0x31,0x7D,0x56,0xD4, ++0x9A,0xCE,0x07,0x7A,0x30,0x6D,0x76,0xD6, ++0x1B,0xFE,0x76,0xD0,0x2A,0x4D,0xC6,0x0F, ++0x9B,0xFC,0x76,0xD0,0x3F,0x4D,0xC6,0x0F, ++0x9B,0xFA,0x76,0xD0,0x31,0x4D,0xC6,0x0F, ++0xBB,0x0E,0xA7,0xD3,0x10,0x4D,0xC6,0xDF, ++0x1B,0xFD,0x76,0xD0,0xB1,0x4E,0x86,0x15, ++0xB9,0xEE,0xB5,0xD0,0x10,0x7E,0xB7,0xD5, ++0xBA,0xCD,0x47,0x10,0x32,0x6D,0x74,0xD5, ++0x1B,0xFC,0x76,0xD0,0xB1,0x4F,0x86,0x15, ++0xB9,0xEE,0xB5,0xD0,0x10,0x7F,0xB7,0xD5, ++0xBA,0xCC,0x47,0x10,0x32,0x6D,0x74,0xD5, ++0x1B,0xFF,0x76,0xD0,0xB1,0x4C,0x86,0x15, ++0xB9,0xEE,0xB5,0xD0,0x10,0x7C,0xB7,0xD5, ++0xBA,0xCF,0x47,0x10,0x32,0x6D,0x74,0xD5, ++0x1B,0xFE,0x76,0xD0,0xB1,0x4D,0x86,0x15, ++0x75,0x22,0x79,0x1C,0xFD,0x91,0x5A,0x19, ++0x77,0x12,0x6B,0xCD,0xFE,0x81,0xA8,0x19, ++0x69,0xFD,0xE4,0x1D,0xFE,0xA0,0x1B,0x1B, ++0x77,0x12,0xAA,0xBE,0xBC,0x41,0x38,0x19, ++0x77,0x02,0xAB,0xDE,0xDC,0xB3,0x7B,0x19, ++0x6A,0x02,0xCB,0xC6,0xDC,0xB5,0x7B,0x19, ++0x78,0x02,0xCB,0xC6,0xFD,0x92,0xAA,0x18, ++0x57,0x36,0xBA,0x1C,0xC3,0xA2,0x88,0x1A, ++0x7C,0x02,0xCB,0xC6,0xFD,0x92,0xAA,0x18, ++0x57,0x36,0xBA,0x1C,0xC3,0xA7,0x88,0x1A, ++0x70,0x02,0xCB,0xC6,0xFD,0x92,0xAA,0x18, ++0x57,0x36,0xBA,0x1C,0xC3,0xA8,0x88,0x1A, ++0x76,0x11,0x6B,0xDD,0xC3,0xAD,0x88,0xDA, ++0x77,0x32,0xBA,0x1E,0xE1,0x81,0x0A,0xD3, ++0x56,0x11,0x6B,0xDD,0x5C,0xB2,0x7B,0x19, ++0xF6,0x01,0x8B,0xDC,0xFE,0xA1,0xB8,0x19, ++0xEC,0x8A,0x01,0xA7,0x46,0x39,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0xE7,0x08,0xC0,0xA2, ++0x4D,0xBB,0x30,0x67,0x45,0x1A,0x03,0xA2, ++0xEC,0x8B,0x01,0xA7,0x46,0x38,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0xE7,0x0B,0xC0,0xA2, ++0x4D,0xB8,0x30,0x67,0x45,0x1A,0x03,0xA2, ++0xEC,0x88,0x01,0xA7,0x46,0x3B,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0xAC,0xC5,0x4E,0x68, ++0x6C,0x89,0x01,0xA7,0xC6,0x3A,0xF1,0x62, ++0xCE,0x99,0xC2,0xA7,0x46,0x2A,0xE1,0xA2, ++0xCC,0xA9,0xD0,0x76,0x45,0x3A,0x13,0xA2, ++0x00,0x76,0xC0,0xA6,0x47,0x3A,0xD1,0x00, ++0xCC,0xA9,0x11,0x65,0x59,0xC5,0x9E,0xA3, ++0x00,0x76,0xC0,0xA6,0x47,0x3A,0xD1,0x00, ++0xCD,0xF9,0x5D,0xAE,0x47,0x3A,0x01,0xA1, ++0xCB,0xB9,0x70,0xAC,0x45,0xBA,0x0C,0xAA, ++0xBC,0xFE,0x00,0x00,0x37,0x7D,0xB1,0x42, ++0xDC,0xF9,0x5D,0xAE,0xA3,0x3B,0xB1,0xA9, ++0xC8,0xB9,0xE0,0xA5,0x57,0xBA,0x0C,0xAA, ++0x20,0xA1,0x70,0x47,0x9B,0x3B,0xB1,0xA8, ++0xC8,0xB9,0xEF,0xA2,0x59,0xC5,0x9E,0xA3, ++0xD2,0x46,0x5F,0xA6,0x67,0x95,0xB3,0x62, ++0xBC,0x0C,0xF5,0x2E,0x43,0x3A,0xB1,0x2A, ++0xFC,0x9F,0xB1,0x41,0x47,0xEE,0x91,0x64, ++0x0C,0xBE,0x79,0x96,0x41,0xDA,0xD3,0x2A, ++0x6D,0xD1,0x40,0x47,0xD7,0x7D,0x91,0x28, ++0x8C,0xA5,0x50,0x25,0x2A,0x24,0x47,0x97, ++0xBC,0x04,0x00,0xF2,0xC2,0x53,0xB5,0x42, ++0xCC,0xD1,0xB0,0x40,0x4E,0xEA,0xB7,0xA2, ++0xAE,0xD1,0xD1,0x2F,0x67,0x1A,0x21,0x05, ++0xEC,0xD3,0x30,0x5B,0x67,0x58,0xDC,0x5C, ++0x3A,0x6C,0x00,0xFA,0x4E,0x52,0xFB,0x47, ++0xEC,0x4E,0x52,0x63,0x65,0x0E,0xE3,0x27, ++0x27,0x9E,0xAE,0xB0,0x65,0x1C,0x93,0x74, ++0x9E,0xDC,0x5B,0x0D,0x2F,0x1D,0x91,0xB5, ++0xEE,0x9D,0x52,0x6B,0x15,0x5F,0x5A,0x65, ++0x12,0x4E,0x52,0x61,0x65,0x14,0xE3,0x27, ++0x9E,0x2E,0x57,0x65,0x69,0x18,0x92,0x4A, ++0xEF,0x4A,0x53,0x45,0x6E,0xF8,0xBB,0x08, ++0x6E,0x9D,0x52,0xB0,0x8F,0x71,0x93,0x40, ++0xEE,0x7B,0x12,0x79,0xF5,0x5A,0x91,0xB2, ++0xCF,0xC7,0x52,0x4C,0x9C,0xC9,0x3A,0x09, ++0xC8,0x83,0x5B,0x7F,0xCC,0x79,0xBA,0x0A, ++0xE7,0x83,0x7A,0x65,0x4C,0x7A,0x6C,0x97, ++0x49,0x64,0x56,0x85,0x0F,0x70,0xB3,0x18, ++0x47,0xF3,0x36,0x79,0xF5,0x5F,0x27,0x22, ++0x16,0x48,0x7A,0x65,0x9A,0xEF,0x22,0x9F, ++0x9E,0x26,0x52,0x65,0x64,0xD8,0x1C,0x82, ++0x58,0xCE,0xD7,0x2E,0x38,0x07,0x39,0xEF, ++0x31,0x18,0xE8,0xA7,0xCF,0x2B,0x2D,0x6C, ++0x55,0xE1,0x07,0x38,0x7C,0x4D,0x39,0xE2, ++0x46,0xEB,0xB8,0x8D,0xDE,0x14,0x31,0x2A, ++0x44,0xA8,0xF1,0xA7,0x45,0xB5,0x38,0x1F, ++0x4B,0x97,0xFA,0x2F,0x86,0xB5,0x3D,0x1F, ++0x4A,0x97,0xF9,0xEA,0xCE,0x52,0xC6,0x3D, ++0xE8,0xCE,0xF8,0x50,0xCF,0x96,0x1D,0xFD, ++0x40,0xD1,0xF8,0x3F,0xA5,0x5C,0x09,0xFB, ++0x7D,0x64,0x9C,0xD3,0xCF,0x9A,0xC1,0x1B, ++0x44,0xA9,0xD3,0xCF,0xFD,0xB2,0x18,0xCA, ++0x44,0xC1,0x80,0x34,0x31,0x0F,0x39,0xCA, ++0x44,0x31,0xF8,0xCF,0xE2,0xB2,0x39,0xCA, ++0x6F,0x31,0xF8,0xCF,0xEF,0xB2,0x39,0xCA, ++0x45,0xF1,0x77,0x2D,0xD3,0x4D,0x16,0x2B, ++0x55,0x59,0xFA,0xA7,0xCF,0xD8,0x6A,0xCF, ++0x89,0x28,0x3C,0x73,0x09,0x9E,0x26,0x03, ++0x89,0x28,0x3C,0x83,0x05,0x9E,0xE6,0x00, ++0x8A,0x28,0xF6,0x14,0x06,0xBF,0xF4,0xE6, ++0xDA,0xFB,0x3C,0x63,0x02,0x5E,0x85,0x41, ++0x89,0x94,0x7E,0x1F,0x01,0x1F,0xFD,0x7E, ++0xF8,0xBA,0x24,0xB6,0x93,0xCE,0xF9,0x06, ++0x8B,0x6F,0x34,0x21,0x05,0xEC,0xF0,0x4C, ++0x8D,0x6D,0x2D,0x03,0x79,0x3A,0xF4,0xAE, ++0x8A,0x69,0x30,0x91,0x03,0x8E,0xA9,0xFF, ++0x98,0x4D,0x24,0xBE,0xE2,0x81,0x0A,0xF9, ++0x82,0x95,0x24,0x73,0x51,0x62,0xFF,0x66, ++0xF8,0xBA,0x7F,0x6B,0x09,0x16,0x6F,0x44, ++0x8A,0x2F,0x67,0x1F,0x08,0x1E,0xE5,0x76, ++0xF8,0xBA,0x34,0x03,0xF4,0xCB,0xF1,0x06, ++0x9D,0xFD,0x18,0x4B,0x85,0xCE,0x8D,0x42, ++0x88,0xDA,0x37,0xCB,0x3D,0x7E,0xF6,0x96, ++0xD9,0x39,0x70,0xB6,0x51,0xB3,0xD1,0x53, ++0xDE,0x02,0x20,0x0C,0x57,0x83,0xA0,0xA3, ++0x3C,0x55,0x20,0x4A,0x51,0xFB,0x81,0x3B, ++0x54,0xAE,0x62,0x83,0xB4,0x42,0x99,0x4B, ++0x4C,0xEA,0x6F,0x8E,0x69,0x33,0xD6,0x4F, ++0xFD,0xC0,0xE1,0x50,0x54,0xFE,0x40,0x3A, ++0x65,0xEA,0x67,0x8B,0xF8,0x69,0x45,0x88, ++0xDA,0x30,0x10,0x56,0x16,0x71,0xA0,0x7B, ++0x3D,0x79,0xC1,0x3F,0x96,0x30,0x00,0x32, ++0xFD,0xA8,0x9E,0xA1,0xA7,0xD5,0xB5,0x1B, ++0xA5,0xEC,0x3B,0x6E,0x55,0xE3,0xA3,0xC3, ++0xDD,0x88,0x65,0xC7,0x40,0xCB,0xE1,0x53, ++0xDA,0x30,0x62,0xFC,0x17,0x71,0xA1,0xFB, ++0xDD,0x58,0xD5,0xAB,0x56,0xBB,0xE0,0x4F, ++0xD7,0x78,0x61,0x73,0x53,0xCB,0xC2,0x3B, ++0xDC,0x00,0xC0,0x3E,0x16,0x76,0x30,0x14, ++0xC7,0xC3,0x16,0xB9,0xA4,0x1E,0x21,0xF7, ++0xAF,0x47,0x56,0x3D,0x91,0x1E,0xD2,0xB4, ++0x4F,0x04,0x36,0x4B,0xE1,0x45,0xF7,0x46, ++0x8A,0xDF,0xE9,0xD6,0xFF,0xA2,0xDE,0x94, ++0x5A,0x62,0x16,0x21,0x93,0x4B,0xD7,0x24, ++0xAB,0x1F,0x99,0xC3,0x3D,0xA3,0xF8,0xC5, ++0x5D,0x6A,0xC4,0x3C,0xA3,0xEC,0x07,0x2C, ++0xAA,0xFA,0xD6,0x21,0xD4,0x75,0x17,0xEC, ++0xB0,0x7F,0x17,0xB1,0x35,0x8C,0xD7,0x07, ++0x93,0xDF,0xE6,0x3B,0xB8,0x1D,0xD3,0xFE, ++0xDC,0x9D,0x84,0x60,0xF6,0x47,0xC1,0x84, ++0xA2,0x3F,0x14,0xB9,0x21,0x34,0x56,0x23, ++0xAB,0x0A,0x02,0x81,0x23,0xBC,0x97,0x23, ++0xA8,0x0A,0x05,0x81,0x20,0x79,0xD6,0xB4, ++0xA8,0x47,0x16,0x05,0x05,0x6C,0xD7,0xB4, ++0xA3,0x3F,0x2F,0x21,0x11,0x5C,0xD7,0xD4, ++0x0F,0xCA,0xE9,0x45,0xEE,0x91,0x2E,0xDB, ++0x4F,0x75,0x8D,0xC2,0xD1,0xA3,0x28,0xF8, ++0x6C,0x20,0xD9,0xDE,0x87,0xE3,0x70,0x9B, ++0x5D,0x63,0x07,0x0F,0xDF,0x39,0x2A,0x43, ++0x7E,0x20,0xC8,0xDE,0xDE,0x53,0xBA,0x21, ++0x50,0x90,0x19,0x63,0xDE,0xA3,0x28,0xDB, ++0x78,0x20,0xE9,0xDE,0xF5,0xA3,0x28,0xDB, ++0x75,0x20,0xE9,0xDE,0x89,0x63,0xA7,0x39, ++0x49,0xDF,0xC6,0x3F,0x26,0x16,0x2F,0xDB, ++0x40,0x20,0xF7,0xDE,0xDE,0x87,0x0C,0xEB, ++0x55,0xB0,0xE0,0x3E,0xDE,0x3A,0x40,0xDC, ++0xB8,0x28,0xA9,0xD1,0xEE,0x93,0x20,0x8E, ++0x25,0x27,0x8D,0xC2,0xDB,0xE0,0xDE,0xD3, ++0x55,0x03,0xD8,0xDE,0xF6,0xA3,0x71,0x9B, ++0x0D,0x60,0xE1,0x9D,0x30,0x72,0x10,0xB3, ++0x45,0x82,0xE8,0xD9,0xD6,0x76,0x08,0xFA, ++0x5D,0x60,0xC9,0x9D,0xDA,0x73,0xD0,0xB2, ++0x54,0x03,0xE4,0x7C,0x9E,0xBD,0xD0,0xBA, ++0x74,0x20,0xD1,0xDE,0xDE,0x53,0x72,0x21, ++0xAD,0x9D,0xF9,0x6B,0xDA,0xA3,0x38,0xB3, ++0x74,0x20,0x16,0x29,0xA8,0x5D,0x2A,0xDB, ++0x55,0x03,0xC9,0xDE,0x21,0x54,0xE2,0x24, ++0x45,0x9D,0x3B,0xC3,0x0F,0xAB,0xE1,0xDB, ++0x59,0xE9,0x2A,0x39,0xDE,0xA3,0x28,0xDB, ++0x65,0x20,0xE9,0xDE,0x45,0x63,0xA7,0x39, ++0x49,0xDF,0xC6,0x3F,0x2E,0x16,0x3D,0xDB, ++0x4A,0x94,0x6B,0x6E,0xC0,0xA3,0x2A,0x43, ++0x55,0x48,0xE9,0xDB,0xDC,0x76,0x0F,0x94, ++0x2A,0x64,0xEB,0x3E,0xFB,0xEC,0x57,0x9F, ++0x5B,0x17,0xEB,0x46,0xDE,0x87,0x0C,0xEB, ++0x54,0xB0,0xE0,0x3E,0xF6,0xA4,0x29,0x42, ++0x55,0x2F,0xC4,0xD7,0xE6,0xFF,0x20,0x8E, ++0x9A,0xD8,0x72,0x3D,0x24,0x1F,0xE1,0x2D, ++0xAA,0xFC,0x27,0x21,0x09,0x5C,0x8E,0x64, ++0xF2,0x9F,0x1E,0x62,0xCF,0x8D,0xD5,0xBC, ++0x90,0xDF,0x16,0x49,0x21,0x5B,0xDE,0xF1, ++0xA9,0x47,0x66,0x09,0x23,0x8D,0xC7,0x16, ++0xAB,0xFC,0x15,0xC1,0x21,0x70,0xD6,0xF4, ++0xBB,0xED,0x14,0x02,0x23,0xC4,0xF6,0x24, ++0xAA,0x2F,0x1E,0xDB,0x26,0xEC,0x27,0x99, ++0xDA,0x6A,0x12,0x21,0x2C,0x5C,0xC7,0x4C, ++0x8B,0xDF,0xE9,0xD6,0x03,0xA2,0xD5,0x24, ++0xAA,0xFC,0x3F,0x21,0x01,0x5C,0x28,0xD3, ++0x13,0x20,0x66,0x9C,0xF3,0x41,0x04,0x2C, ++0x71,0xDF,0x1A,0xEA,0x93,0xBB,0xE7,0x90, ++0xA9,0xB7,0x36,0x05,0x33,0x34,0xF4,0x67, ++0xA9,0xBF,0x1E,0x02,0xE2,0x3D,0xE7,0x98, ++0xAA,0xFC,0xB1,0xC6,0xF1,0x49,0xD7,0x24, ++0x84,0xB7,0xCE,0xFC,0xFC,0xA1,0x8B,0x49, ++0xC9,0xE2,0x22,0x94,0xD4,0x81,0x82,0xBE, ++0x77,0x2A,0xB5,0x2C,0xD9,0xA9,0x08,0x29, ++0x1D,0x6A,0x62,0x94,0x4D,0x61,0x56,0xB6, ++0x77,0x24,0xB4,0xB8,0x15,0xE9,0x22,0xF9, ++0xFF,0x45,0xCF,0xFC,0xDC,0xA9,0x02,0x22, ++0x46,0x2E,0xCD,0x2E,0xC4,0x98,0x2A,0xC1, ++0x77,0x7A,0xCB,0xD4,0xFD,0x51,0x0C,0xBA, ++0x87,0xE5,0x7B,0xFB,0xFD,0x54,0x0E,0xD9, ++0xF1,0x41,0xCB,0xDC,0x14,0xE0,0x0D,0xF9, ++0xDF,0x63,0xE1,0xD0,0xED,0x50,0x08,0x61, ++0xCD,0x02,0x99,0xE5,0xFE,0x49,0x9B,0x98, ++0x75,0x92,0x22,0x94,0xD4,0x81,0x82,0xBE, ++0x73,0x02,0xCA,0xD3,0xDA,0x50,0xE2,0x90, ++0x77,0x2A,0xE5,0x26,0xDC,0xA1,0x8C,0xBA, ++0x5C,0xE2,0xEB,0xFC,0xCC,0xB9,0x0B,0xDB, ++0x23,0x57,0x94,0x81,0xB1,0x06,0x5F,0x86, ++0x34,0x87,0x26,0xA9,0xE9,0xCD,0x5F,0x3C, ++0xA3,0x36,0x99,0x49,0xA9,0x4C,0x55,0x8D, ++0xA2,0x3E,0xD6,0xEA,0xA9,0x4D,0x5F,0xB5, ++0x12,0x6F,0x16,0xC8,0x40,0xBC,0x77,0xAC, ++0xAA,0x10,0x9A,0xA9,0xA8,0xF5,0x6F,0x94, ++0x28,0x7F,0x9F,0x7B,0xA9,0xFD,0xB2,0x7D, ++0x23,0x78,0x94,0x79,0x87,0xF8,0x57,0x7D, ++0xCB,0x3F,0xB6,0xA9,0x21,0x93,0x5B,0xAC, ++0x02,0x77,0x98,0xEA,0xD6,0xC8,0x5D,0x83, ++0x9D,0x8C,0x36,0xC0,0xA9,0xFC,0x5C,0x76, ++0x62,0x15,0x36,0xC8,0xA8,0xF4,0x59,0xEF, ++0xD2,0x50,0x9F,0x79,0xB9,0xF4,0xD9,0xEF, ++0x4E,0x7B,0x9F,0x79,0xC1,0xF8,0x48,0x7D, ++0xCB,0x3F,0xB9,0xA9,0x81,0xD4,0xD7,0xEB, ++0x26,0x57,0x26,0xEB,0xA3,0x05,0xDF,0x8C, ++0x7D,0x4B,0xAD,0x4A,0x5A,0xE7,0x85,0xF7, ++0x17,0x27,0x85,0x9A,0x12,0xA0,0x68,0x9F, ++0x07,0x84,0x96,0x7A,0xDA,0xC7,0x00,0xB0, ++0x11,0xB4,0x2D,0x9A,0x9C,0xA4,0x63,0x7F, ++0x5D,0x48,0xA8,0x4A,0xF0,0xCB,0x6F,0x4F, ++0x65,0x48,0xAC,0x4A,0xE0,0xCB,0x6B,0x4E, ++0x11,0x44,0xE1,0xB6,0x7D,0x37,0xEC,0xBF, ++0x7B,0x48,0x49,0x4A,0x9A,0xC7,0x8E,0x78, ++0x11,0x48,0x8E,0x4A,0xBA,0xE7,0x2D,0xA7, ++0x08,0x4C,0xAE,0x42,0x9B,0xC7,0xAC,0x9D, ++0x17,0x27,0x8D,0xAE,0xB4,0x87,0x6E,0x05, ++0x30,0x64,0x85,0x9A,0x8C,0xE7,0x91,0x68, ++0xDB,0x8F,0xAD,0xB2,0x90,0x37,0x6D,0xB7, ++0x13,0xB5,0x9B,0x87,0x98,0x71,0x20,0x78, ++0xE7,0x79,0x5D,0x92,0x5A,0xE7,0x64,0xAF, ++0x13,0xF4,0xEB,0x7D,0xF0,0x8F,0xC5,0xF7, ++0x9B,0xCE,0x97,0x77,0x18,0x27,0x86,0x29, ++0x93,0xAC,0x39,0xD7,0x18,0x27,0x38,0x88, ++0x8D,0xDB,0x07,0x30,0xC7,0xF8,0x44,0x85, ++0xBB,0xE9,0x05,0xAC,0x25,0x4D,0xE6,0x4D, ++0xDF,0xD2,0x06,0xA7,0x00,0x65,0xD5,0xE4, ++0x9B,0xB6,0x06,0x17,0x54,0x51,0xBE,0x1D, ++0xBA,0x1E,0x5F,0x18,0x38,0x9C,0xC6,0x18, ++0xBA,0x1E,0x17,0x1D,0x3B,0x9C,0xE6,0x4D, ++0xBB,0xE9,0x17,0x15,0x54,0x51,0xC0,0xD5, ++0xBB,0xE3,0x03,0xE1,0x38,0x68,0xC4,0xD5, ++0xBB,0xE3,0x07,0xE1,0x3A,0x68,0xC6,0x13, ++0xBB,0x58,0x16,0xD0,0x30,0xD4,0xC7,0x12, ++0xD2,0x8D,0x0F,0x28,0x19,0x4D,0xC4,0x39, ++0xCA,0x8D,0x07,0x34,0x30,0x41,0xC6,0xA5, ++0x35,0xD6,0x3F,0x34,0xB6,0x0F,0xC7,0xE6, ++0xBA,0xEE,0x06,0xA0,0x10,0x35,0xA2,0x29, ++0x1A,0x46,0x8F,0x48,0x2E,0x3E,0x4E,0x95, ++0xDB,0x9C,0x8C,0x20,0xB8,0xED,0x4A,0x6D, ++0x57,0x58,0x8F,0x97,0xB8,0x14,0x4C,0x21, ++0x37,0x26,0x8E,0x20,0xB8,0xED,0x48,0x6D, ++0xCC,0xB1,0x31,0x54,0xBA,0xE4,0x4F,0xDD, ++0xFB,0x58,0x8A,0x08,0x48,0x78,0x4E,0x24, ++0x03,0x42,0x87,0xFB,0x41,0x22,0x4E,0xBD, ++0x33,0x66,0x2F,0x5B,0xB8,0x85,0x63,0x54, ++0x31,0x76,0x2F,0x59,0xBA,0x05,0xEE,0x5C, ++0x31,0xA6,0x2F,0x59,0x98,0xD5,0x1F,0x5F, ++0x3F,0x16,0x2F,0x90,0xB4,0x95,0xEE,0x95, ++0x13,0x56,0xDE,0x9A,0x43,0x3A,0xB1,0x97, ++0x32,0x58,0x3F,0x59,0xB4,0x95,0xEE,0x95, ++0x3F,0x46,0x2F,0xF0,0xB8,0x85,0xF3,0x55, ++0x32,0x57,0x3F,0x59,0xBC,0xE5,0xCE,0x99, ++0x2D,0xB9,0xA0,0xB9,0x0A,0xE5,0x8E,0xFD, ++0x32,0x47,0x9E,0x5B,0xB9,0xE5,0x8E,0xA9, ++0x2D,0xB9,0xA0,0x59,0x48,0x84,0x63,0x54, ++0x13,0x66,0xDD,0x5A,0xB3,0xC5,0x4E,0x87, ++0xB3,0x46,0xDD,0x5B,0xBD,0xC5,0x4E,0x87, ++0xB3,0xB6,0x5E,0x4D,0x40,0x94,0xFF,0x55, ++0x13,0x66,0xCD,0x5A,0x38,0xC5,0x1C,0x5E, ++0xCB,0x17,0x2F,0x50,0x41,0x3A,0xB1,0x97, ++0xCB,0x17,0x3E,0x50,0x98,0xE5,0x1C,0x5F, ++0xCB,0x17,0x2F,0x50,0x43,0x3A,0xB1,0x97, ++0x31,0x88,0x3F,0x59,0xA0,0x95,0xFF,0x95, ++0x2B,0x16,0x2F,0x90,0xA0,0xC5,0xFF,0xF5, ++0x2B,0x46,0x2F,0xF0,0x48,0x84,0xF3,0x55, ++0x31,0x89,0x3F,0x59,0xBC,0xF5,0xDF,0x99, ++0x37,0x76,0x0F,0x9C,0xA6,0x3A,0x61,0xBC, ++0xB1,0x69,0x3F,0x59,0x0A,0xF5,0x9F,0x9D, ++0x32,0x66,0x5E,0xFC,0x0A,0xF5,0x8E,0x9D, ++0x45,0x11,0x38,0x8B,0xD1,0x4D,0x16,0x2B, ++0x44,0x31,0x67,0x2A,0xD1,0x4D,0x16,0x2B, ++0x64,0x9E,0xFA,0xEF,0xC8,0xF2,0x14,0x23, ++0x46,0x31,0x48,0x2C,0xDA,0xB0,0x39,0x30, ++0x43,0xB1,0x45,0x27,0xCB,0xB2,0xA6,0x2F, ++0x5A,0xCE,0xD7,0x2E,0xD1,0x4D,0x16,0x2B, ++0x04,0x9E,0xFA,0xEF,0xFF,0xF2,0x14,0x23, ++0x4E,0x11,0xA8,0x2D,0xEF,0x53,0x99,0x2B, ++0x44,0x01,0x29,0x2D,0xCE,0x5D,0xB7,0x2B, ++0x4A,0x31,0xA8,0x2F,0xEE,0xA3,0xF8,0x2A, ++0x64,0xD3,0x58,0x2E,0xCE,0x5C,0xB7,0x2B, ++0x4A,0x31,0x68,0x2F,0xEE,0xA0,0x98,0x2A, ++0x64,0xD5,0x58,0x2E,0xCE,0x5E,0xB7,0x2B, ++0x4A,0x31,0x68,0x2F,0xEE,0xA6,0x98,0x2A, ++0x64,0xD9,0x58,0x2E,0xCE,0x5A,0xB7,0x2B, ++0x4A,0x31,0x68,0x2F,0xEE,0xAA,0x98,0x2A, ++0x89,0xFD,0xA4,0xE3,0x03,0x6E,0x54,0xE4, ++0x28,0xFC,0x94,0xE2,0x82,0x70,0x75,0xE7, ++0x29,0xEC,0x94,0xE2,0x03,0x2F,0x65,0xE6, ++0x89,0xBC,0x94,0xE2,0x23,0x31,0x71,0xE7, ++0x89,0xBD,0x90,0xE3,0x06,0x2E,0x60,0xE6, ++0x8C,0xBD,0x90,0xE3,0x06,0x5E,0xA7,0xE6, ++0x8C,0xCD,0xE7,0xE3,0x03,0x4E,0x55,0xE5, ++0x82,0xDD,0xB6,0x41,0x33,0xFE,0x48,0x4E, ++0x89,0xFD,0xA4,0xE1,0x03,0x6E,0x54,0xE4, ++0xB8,0x7D,0x89,0xEB,0xFC,0xCB,0xF1,0x06, ++0x09,0x4D,0x10,0x33,0x0E,0x7E,0xF5,0x96, ++0xA9,0x95,0xBC,0x05,0x07,0xAB,0xE5,0x24, ++0x68,0x94,0xA5,0x40,0x22,0x1E,0xF5,0xE6, ++0x89,0xDD,0x34,0x24,0xAB,0x3C,0xF5,0xDB, ++0xCF,0xE6,0x30,0x9B,0xA2,0x17,0x8F,0x1F, ++0x98,0xE5,0x3C,0x19,0xA3,0x1F,0xD5,0x6E, ++0xA6,0x15,0xD8,0x39,0xCD,0x90,0xE4,0x1F, ++0xB5,0xE8,0xDA,0xCB,0xE5,0x70,0x18,0x70, ++0x04,0x7B,0x7B,0x85,0x6D,0xCD,0x8B,0xAF, ++0x46,0x79,0x9A,0xF1,0x9B,0x8C,0x3B,0x8A, ++0x62,0x8B,0x5C,0xAF,0x1E,0x4B,0x3B,0x80, ++0xA6,0x15,0xD0,0x38,0xCD,0x90,0xE4,0x1F, ++0xD9,0xE8,0xDC,0x0D,0x8F,0xF8,0xBA,0x80, ++0x56,0x33,0x4A,0xAA,0xCD,0xFA,0x5B,0xF4, ++0x46,0x71,0xE2,0xED,0x92,0x8E,0x1B,0xC0, ++0x92,0xCF,0xDD,0x0D,0xED,0x08,0x79,0x80, ++0xC7,0x7B,0x9A,0xB0,0x7D,0xD7,0x3B,0x82, ++0x26,0x0F,0xFA,0x8F,0xC5,0x90,0x76,0xF6, ++0x66,0x3B,0x29,0x31,0xCD,0x90,0xE4,0x1F, ++0xDE,0xE8,0xFB,0x85,0xEF,0xB0,0x12,0xEE, ++0x66,0xC7,0xDB,0xCD,0xE8,0x20,0xEB,0x55, ++0x16,0x54,0x25,0x58,0xE1,0x90,0x94,0x58, ++0x50,0x1D,0xAD,0xE3,0x82,0x66,0x3B,0x8E, ++0x08,0xE4,0xC9,0x86,0x8B,0x27,0x10,0x90, ++0x00,0x54,0xB4,0x8B,0x8A,0x06,0x3D,0x66, ++0x03,0x54,0xB5,0x11,0x02,0xF3,0x75,0xCE, ++0x00,0x5F,0xBF,0x51,0x09,0xF6,0xFD,0x96, ++0x40,0x7D,0xB4,0xCB,0x0B,0xFB,0x7C,0xA6, ++0x0A,0xE5,0xBE,0x56,0x8B,0xD6,0xBD,0xCD, ++0x0A,0xE5,0xB4,0x13,0x8D,0xB5,0x64,0x5F, ++0x18,0xED,0xBD,0xA3,0x88,0x27,0x6F,0x17, ++0x00,0x55,0x76,0xC8,0x82,0x16,0x7D,0xAE, ++0x30,0x54,0xBD,0x6B,0xAA,0xA2,0x3D,0x92, ++0x12,0xEF,0x2C,0xC9,0x71,0x2D,0x6D,0x8E, ++0x00,0x57,0xA4,0x10,0x8B,0xD7,0x5C,0xDA, ++0x0F,0xEC,0x37,0xEB,0x81,0x96,0x35,0xEE, ++0x13,0xC5,0x4C,0x36,0x7B,0xBE,0x8C,0xC7, ++0x28,0x6D,0xF4,0xC8,0x8B,0xE2,0x71,0x1E, ++0x0A,0xED,0xFC,0xC9,0x86,0x66,0x65,0x16, ++0x00,0x5D,0xB8,0x5A,0x99,0x6F,0x71,0x16, ++0x45,0x6F,0xD1,0x97,0x8A,0x16,0x6F,0x16, ++0x45,0x37,0xB1,0x11,0x8B,0xDB,0x7D,0x52, ++0x0A,0xEF,0x95,0x95,0x8B,0x2C,0x14,0xCC, ++0x03,0xDD,0xBC,0x7B,0x36,0x0C,0x75,0x17, ++0x09,0xED,0xBC,0x7B,0x0D,0x1D,0x7C,0x1F, ++0x01,0x75,0x5D,0xC3,0x89,0x64,0x74,0x96, ++0x00,0x58,0xBC,0x1A,0x81,0x2B,0xA3,0xC7, ++0x03,0xED,0xB6,0x11,0xC2,0xB4,0x3D,0x96, ++0x03,0xDC,0xBF,0x1B,0xE3,0xB0,0x7D,0x7E, ++0x00,0x9B,0xBB,0x6B,0x88,0x6F,0x77,0x14, ++0x08,0x6D,0xBF,0x22,0x88,0x66,0x15,0xC8, ++0x00,0x85,0xB2,0x65,0x8B,0x66,0x7D,0x8A, ++0x02,0xE7,0xBD,0x1A,0x88,0x26,0x7D,0xAB, ++0xED,0x36,0xD2,0x83,0x8A,0x16,0x73,0x8E, ++0x8C,0xEC,0x3D,0x8A,0x12,0x47,0xC2,0xC6, ++0x8B,0x73,0x22,0xF2,0x23,0x6F,0xCC,0x17, ++0x66,0x1B,0xF5,0xFC,0x22,0x5D,0xE1,0x17, ++0x97,0xEC,0xC7,0x47,0x6D,0x71,0x11,0xC2, ++0x8B,0x74,0x25,0x31,0x23,0x6F,0xE3,0x87, ++0xB1,0xEC,0x24,0x35,0x4B,0x2F,0xBC,0x57, ++0x91,0xAF,0x26,0xC2,0x1E,0xF7,0xE4,0x30, ++0xD9,0xF0,0x22,0xF2,0x32,0x17,0xD4,0x3F, ++0x98,0x3C,0x29,0x8A,0x11,0x8F,0xE8,0x8F, ++0x99,0xCB,0x65,0x0C,0x1E,0xFF,0xE4,0x38, ++0x9F,0x7C,0xBD,0xC2,0x27,0x8F,0xE4,0x37, ++0x9E,0xEC,0x2E,0x82,0x18,0x8F,0xF5,0x38, ++0x96,0x36,0x14,0x12,0x3A,0x6F,0x1B,0xE0, ++0x3F,0x02,0x15,0x20,0x17,0x6F,0xEA,0x17, ++0x7B,0xB9,0x5A,0x0E,0x12,0x4C,0xD5,0x17, ++0xB1,0xEC,0x7C,0x52,0x4A,0x2F,0xEC,0x54, ++0xCF,0x86,0x9E,0x8A,0x98,0xD4,0x77,0xAC, ++0x7B,0x17,0xC6,0xE9,0xA1,0x97,0x4F,0x7D, ++0x22,0x76,0xA6,0xA9,0xAD,0x34,0x7C,0xF0, ++0x40,0x0B,0xFD,0xFD,0xE0,0xC8,0x7D,0xF8, ++0x62,0x49,0x1F,0xEB,0x5E,0x0F,0x4D,0x34, ++0x25,0xC0,0xA6,0xB3,0xE9,0xCA,0x59,0x3C, ++0x25,0xB7,0x95,0x31,0xA9,0xFC,0x5B,0x7D, ++0x33,0x77,0x8C,0x39,0xA9,0xF4,0x47,0x3C, ++0x43,0xB0,0x99,0x33,0xB1,0x4D,0x5F,0x8C, ++0x82,0x03,0x91,0x31,0x28,0xB4,0x58,0x35, ++0x63,0x37,0x98,0x30,0xA8,0xB4,0x14,0x4B, ++0xD2,0xE2,0x4C,0xB4,0xAD,0xD4,0x8F,0xA4, ++0x2F,0x57,0x5E,0xA9,0x3C,0x64,0x5E,0xC4, ++0x62,0x3F,0x9C,0x38,0xA8,0xD4,0x5C,0x3C, ++0x20,0xCF,0x9E,0x59,0x59,0x3A,0x5D,0xAC, ++0x21,0xCF,0x5F,0xA6,0x84,0xF4,0x5F,0x85, ++0x17,0xB5,0x8C,0xF2,0xB1,0xC7,0xE7,0x98, ++0x13,0xB0,0xE5,0x9D,0x5A,0xE8,0x2C,0x9E, ++0x12,0x4E,0xAA,0x0A,0x9B,0x37,0x6B,0xB5, ++0x14,0xBF,0xAE,0x9A,0xB3,0xE7,0x4C,0x9F, ++0x11,0x94,0x6D,0x63,0x9F,0x06,0x4C,0xF7, ++0x91,0x62,0xAC,0x4F,0x7D,0x8E,0x6C,0x7F, ++0x17,0x43,0x85,0x9A,0x8B,0xC4,0x09,0xB2, ++0x0A,0xB4,0xCB,0xB2,0xBC,0x37,0x0B,0xB7, ++0x70,0xB5,0xAC,0xB5,0x9A,0x3D,0x6D,0xB8, ++0x11,0x46,0xBC,0xB5,0x9A,0x75,0x6C,0x43, ++0x2A,0x64,0xAF,0x30,0x90,0x4E,0x7E,0x37, ++0xEE,0x93,0x62,0x64,0xBA,0x8F,0x6C,0xB9, ++0x2C,0x64,0xAD,0x9D,0xAF,0x33,0x7F,0x07, ++0xB9,0x26,0xAD,0x40,0x9F,0xE7,0x66,0x37, ++0x39,0x84,0xAD,0xB8,0x8B,0xC8,0x6C,0x0D, ++0x11,0xBE,0xD6,0x86,0x98,0x4D,0x66,0x36, ++0xDE,0x11,0x8F,0xB0,0xFD,0xC4,0xB1,0x64, ++0xB1,0xA5,0x57,0xA7,0x46,0x1A,0xB0,0x60, ++0x0C,0xBE,0x70,0xD5,0x43,0xAA,0x8A,0x42, ++0xCE,0x13,0x7A,0xEE,0x55,0x92,0x4E,0xB5, ++0x60,0x47,0x64,0xDF,0x54,0xA7,0xB1,0x64, ++0xCC,0x91,0x72,0x96,0x55,0xA3,0xC9,0x5E, ++0xC1,0xA1,0x08,0x5C,0x45,0xEE,0xF7,0x00, ++0xBA,0xA7,0x0D,0x5B,0xAF,0x21,0xB4,0xD2, ++0xED,0x59,0x1D,0x59,0x46,0x17,0xB5,0x9F, ++0x8D,0xA0,0x50,0x7E,0x8E,0x45,0x81,0x6B, ++0x3B,0x69,0x62,0xDF,0xFF,0x78,0xB0,0x98, ++0xCD,0xA4,0x73,0x9D,0x46,0x1A,0xB4,0xD2, ++0xDE,0x21,0x7F,0xA7,0x47,0x12,0xB3,0x9E, ++0x4A,0xA0,0x5D,0x5D,0x43,0xDA,0xF1,0x5E, ++0x64,0xFB,0x71,0x9A,0x55,0xA7,0xDC,0x5E, ++0xDE,0x21,0xF0,0x5C,0x07,0x26,0xB4,0xD2, ++0xAB,0xFF,0xD6,0x26,0x25,0xCC,0xF7,0x4C, ++0xAA,0xD8,0x13,0xF5,0x24,0xC4,0x7F,0x66, ++0xA8,0x04,0x16,0x01,0xE1,0x1F,0xD2,0xB4, ++0xA2,0x74,0x16,0x01,0xF9,0x2D,0xD3,0xBC, ++0xAB,0xFE,0x1F,0x8E,0x22,0x6B,0x1E,0x23, ++0x22,0x9D,0x32,0xF1,0x23,0x7C,0xD6,0xB4, ++0x81,0xFF,0x16,0xB1,0x25,0xC4,0xD7,0x0C, ++0xA1,0x05,0x56,0x63,0x25,0xCC,0xFA,0x04, ++0xAA,0x4F,0x10,0xC1,0x25,0xC4,0xD7,0xD4, ++0x42,0x37,0x26,0x10,0x5E,0x42,0xD3,0xB4, ++0x93,0xAF,0x17,0xB9,0x60,0x42,0xD7,0x0C, ++0xAB,0x4E,0xE5,0xFD,0x25,0xC4,0xD7,0x0C, ++0x5A,0x0E,0x16,0xB9,0x5E,0x42,0xEF,0x54, ++0x8B,0xB7,0x53,0x01,0x28,0x59,0xD7,0xF0, ++0xCF,0xFF,0x69,0x3F,0x19,0x2C,0xDF,0x8C, ++0x6A,0xC4,0xD6,0x3C,0x27,0xCC,0xD0,0xBC, ++0xEE,0xB3,0x52,0xB5,0x64,0x38,0xD2,0x79, ++0xEB,0x03,0x92,0x72,0x6C,0x00,0x95,0xF8, ++0xE6,0x83,0xF3,0x0C,0x6D,0x02,0xD3,0x7E, ++0x4E,0xFA,0x72,0x0D,0xA5,0x1E,0x91,0xB4, ++0xCE,0x9B,0xAD,0x92,0xA0,0xE1,0x94,0xF8, ++0xEE,0xB3,0x57,0xB5,0x07,0x70,0x32,0x08, ++0x7E,0xDC,0x72,0x0F,0x25,0x04,0xB3,0x02, ++0xCE,0xF3,0x92,0x63,0x41,0xCD,0xB3,0x60, ++0x11,0x6C,0xE4,0x9C,0x45,0xF8,0x93,0x4E, ++0xE9,0x40,0x41,0xFD,0xD5,0x5A,0x97,0xBD, ++0xE4,0x33,0x30,0x0D,0xE5,0x45,0x32,0x08, ++0xEC,0x7B,0x30,0x0D,0xC4,0x70,0xA3,0x40, ++0x7E,0xDC,0x72,0x0F,0x13,0x04,0xD3,0x7C, ++0xCE,0xF9,0x57,0xFD,0x25,0x06,0x96,0xF0, ++0xE4,0x4A,0xAD,0x92,0x3D,0xF5,0x53,0x08, ++0x8C,0xF3,0x53,0x0D,0x25,0x44,0x32,0x08, ++0xB2,0x10,0xBE,0xC3,0xE9,0xC8,0x7F,0xCE, ++0x0A,0x57,0xF3,0xB7,0xA9,0xFC,0x85,0x70, ++0x25,0xB7,0xFC,0xC1,0x91,0xAC,0xFE,0xC4, ++0x5D,0x4B,0x0E,0xEE,0x89,0xBE,0x1F,0xB0, ++0x02,0x35,0x98,0x31,0xE8,0xCA,0x5F,0x84, ++0x24,0xC6,0x6C,0x75,0x89,0xD4,0xA0,0x5B, ++0xB6,0xAE,0x8B,0x19,0xAB,0xF4,0xAF,0x11, ++0x23,0xAB,0x61,0x56,0xB9,0x99,0x5F,0xAC, ++0xC3,0x88,0x61,0x56,0xBE,0x14,0xD0,0x4E, ++0x3E,0xA8,0xB1,0x48,0xB9,0x61,0x1C,0xC5, ++0x22,0x7C,0x9C,0x79,0x06,0x27,0x5F,0x2C, ++0x23,0xB7,0x61,0x5E,0x0C,0x2D,0x5E,0x8C, ++0x32,0xEA,0x8C,0xC1,0xA8,0xD4,0x7B,0x9D, ++0x28,0x27,0x9E,0x8B,0xE3,0xA4,0x5E,0x8E, ++0xCE,0xB0,0x8F,0xC1,0xA9,0xF6,0x8D,0xEF, ++0xCA,0xB0,0x9E,0xA9,0xBE,0x14,0xD0,0x4E, ++0x94,0x02,0x1B,0xE2,0x13,0xCB,0xB6,0x6F, ++0x88,0xD6,0x36,0xD3,0xAC,0x8D,0xF5,0x86, ++0x89,0x1D,0xCB,0xF4,0x28,0x84,0xF4,0x26, ++0x98,0x40,0x26,0x6B,0x02,0x7E,0xD1,0x37, ++0x0A,0x79,0x34,0x21,0xC1,0xFA,0xF4,0x24, ++0x64,0x1A,0x25,0x6B,0x03,0x5C,0x27,0x45, ++0x60,0x1A,0x0E,0x2B,0x03,0xAC,0xC5,0x3E, ++0xA8,0xDE,0x36,0x03,0x99,0x3D,0xB4,0x2C, ++0x89,0x2E,0x24,0x03,0x34,0x46,0xF5,0x24, ++0x5A,0xBE,0xBC,0x41,0x03,0xAC,0xF7,0x06, ++0x98,0xFD,0x44,0x44,0x73,0xCB,0xF0,0x06, ++0x84,0xFD,0x22,0x03,0xFC,0x89,0xE1,0xEF, ++0x88,0x95,0xCB,0x22,0x01,0x4F,0xFC,0x5A, ++0x89,0xD4,0x3E,0xD2,0xFC,0x5F,0xFD,0x37, ++0xBA,0xFD,0x3D,0x5B,0x40,0x66,0x0A,0x35, ++0x80,0xCE,0x15,0x03,0x2B,0x7E,0x6D,0x41, ++0xCB,0x73,0xF8,0x1C,0x35,0x95,0xC6,0x68, ++0xBB,0xE6,0x05,0xE0,0x31,0x6D,0xEA,0x45, ++0xCB,0x73,0x07,0x10,0xF0,0x0E,0xB6,0x88, ++0xB1,0xDE,0x47,0xD2,0x10,0x4C,0x86,0xD5, ++0x9B,0xCC,0x87,0xD0,0x10,0x49,0x46,0xD5, ++0x9B,0xC6,0x87,0xD0,0x90,0x4C,0x66,0xD4, ++0xBB,0xEF,0x87,0xD0,0xB2,0x5D,0x97,0xD5, ++0xBA,0xCE,0x87,0x62,0x3A,0x5D,0x47,0x77, ++0xA5,0x31,0x28,0xD1,0x3E,0x1D,0x66,0xD4, ++0xF5,0x30,0xF8,0xDB,0x35,0xAD,0x66,0xD4, ++0xBB,0x9E,0xB7,0xD1,0x3D,0x5D,0x66,0xD4, ++0xB1,0xFE,0xA7,0xD1,0x37,0x4D,0x06,0xD6, ++0xBB,0x1E,0xA7,0xD1,0x50,0x9D,0x4B,0xD7, ++0x9B,0x8E,0x2A,0xD9,0x3A,0xB9,0x39,0xDE, ++0x9B,0x8E,0xBA,0xD8,0x30,0x2D,0x66,0xD6, ++0xBB,0xBE,0xA7,0xD3,0x30,0xCD,0x66,0xD6, ++0xAA,0x6F,0xB6,0xC2,0x26,0x4C,0x16,0xC7, ++0xAF,0x1F,0xB6,0xC0,0xE1,0x55,0x7B,0xCC, ++0x6A,0xD6,0xBA,0xC9,0xE1,0x55,0x7B,0xCC, ++0x6A,0xD6,0xBA,0xC9,0x20,0x8C,0x77,0xC5, ++0xB4,0x20,0x39,0xC0,0xD9,0xE9,0xD3,0x24, ++0xAB,0xB7,0x17,0x01,0x3E,0x5C,0x17,0x26, ++0xA9,0xF9,0x1E,0x61,0x26,0x76,0xD3,0xFF, ++0xAA,0xF7,0x01,0x84,0x24,0x8D,0xC0,0x81, ++0xA9,0x3F,0x16,0x09,0x37,0xF9,0xD7,0xF5, ++0xBC,0x7A,0x06,0x01,0xA0,0x1F,0xF6,0x44, ++0x0A,0xB6,0xD6,0x3F,0x21,0x73,0x77,0x45, ++0xAB,0x0F,0x56,0x3F,0x81,0x3D,0xF7,0x24, ++0x55,0x28,0xB0,0xD9,0x21,0x73,0xD6,0xF5, ++0x8A,0xB5,0x10,0xC1,0x43,0x34,0x76,0x4C, ++0x92,0xDF,0x86,0x66,0x01,0x36,0x97,0x38, ++0x8A,0xBD,0xD6,0x3D,0x01,0x3E,0xD3,0xC4, ++0x51,0x2E,0xA7,0xC0,0x19,0xAD,0x23,0xA1, ++0xA3,0x01,0xF9,0xA6,0x40,0x17,0x6E,0xBD, ++0xCC,0xB1,0x2C,0x40,0x40,0x78,0x4E,0xBD, ++0x7D,0x07,0xC1,0xB8,0xD6,0xA4,0x20,0xBD, ++0x7A,0x08,0xC9,0xB8,0xD1,0xAB,0x28,0xBD, ++0xC4,0xF3,0x87,0xB8,0xAF,0xC5,0x60,0xF4, ++0xB9,0xF6,0xF6,0xFC,0xBE,0x69,0x62,0x74, ++0x1F,0x82,0xA3,0x71,0x8F,0xE4,0x4D,0x11, ++0xFA,0x47,0xCF,0xA0,0x94,0x01,0x79,0x9C, ++0x28,0x76,0x71,0x4F,0x24,0x2A,0x4B,0xBD, ++0xB3,0x7B,0x83,0xB8,0xA3,0xF9,0x4C,0x68, ++0x57,0x04,0x8E,0x98,0xB8,0x25,0x4E,0x9D, ++0x33,0x60,0x86,0x28,0xB7,0x25,0xAE,0xBA, ++0x38,0x96,0x83,0x98,0xA6,0x8C,0x3E,0xFE, ++0x4A,0x02,0x35,0x81,0xF9,0xDD,0x74,0xBD, ++0x35,0xEE,0x8F,0x48,0xFE,0x2E,0x48,0x16, ++0xDA,0x6B,0x05,0x46,0x20,0x37,0xA0,0x7F, ++0x30,0x79,0x0F,0x10,0x4E,0xCB,0x48,0x54, ++0xC9,0x78,0x74,0x1E,0x77,0x2A,0xD8,0x17, ++0x79,0x90,0x69,0x4E,0x58,0xE3,0xAE,0x95, ++0xDD,0xC0,0x6D,0x68,0xAE,0x69,0xA2,0x82, ++0xDF,0x30,0xA1,0x4F,0x54,0xBB,0xC9,0x15, ++0xE7,0xA8,0x62,0xFE,0x56,0xDB,0x88,0xB8, ++0xDE,0x03,0x66,0x95,0x3B,0x3B,0xC4,0x4F, ++0xDD,0x85,0x85,0x87,0x5F,0xB3,0xA0,0x7B, ++0xD8,0x78,0x5B,0x56,0x50,0x82,0xA3,0xFB, ++0xDD,0x58,0x63,0xBD,0x52,0xCB,0x9A,0x53, ++0xDB,0x01,0x62,0xFE,0x56,0xDB,0xB4,0xB8, ++0xD7,0x33,0x66,0x95,0x5B,0x9B,0x50,0xEE, ++0xEB,0xA3,0x61,0x56,0x52,0x2B,0x0F,0xA0, ++0xDD,0x28,0x41,0x56,0xAA,0xDC,0xEC,0xBC, ++0xDC,0xA8,0x71,0xE3,0x54,0x0B,0xA0,0xA3, ++0xC6,0x11,0x24,0xBE,0x00,0x7E,0xE5,0xE5, ++0x8B,0xFD,0x25,0x00,0x14,0x7E,0xF5,0x1C, ++0x88,0xBD,0x19,0xEA,0x87,0x9E,0x6A,0xE3, ++0x8C,0xDD,0xA4,0xE7,0x07,0x4E,0x64,0xE2, ++0x86,0x3D,0x76,0xE3,0x01,0xBE,0x39,0xE7, ++0x06,0x3E,0x28,0xE3,0x00,0x7E,0xA7,0x07, ++0x70,0x02,0xCB,0x09,0x03,0x3E,0x48,0xEE, ++0x8B,0xF1,0x94,0xE2,0x01,0x72,0xA5,0xE6, ++0x77,0xF3,0x28,0x00,0x04,0x7E,0xF5,0x1C, ++0x8B,0xF5,0x94,0xE2,0x01,0x76,0xA5,0xE6, ++0x77,0xF1,0x28,0x00,0x00,0x7E,0xF5,0x1C, ++0x8B,0xF9,0x94,0xE2,0x01,0x7A,0xA5,0xE6, ++0x77,0xF5,0x28,0x00,0x01,0x7E,0xA6,0x06, ++0xE8,0xFD,0x94,0x12,0x1D,0x81,0xDA,0xE7, ++0x89,0xDD,0xE4,0xE7,0x02,0x4E,0x24,0xE2, ++0x89,0xFD,0x66,0xE0,0x00,0x7E,0xA7,0x27, ++0xFB,0x8A,0x43,0x6E,0x75,0x29,0x52,0x95, ++0xFE,0xBA,0x92,0x90,0x75,0x09,0xD0,0x92, ++0xFC,0x8A,0x11,0x55,0x81,0xF6,0x7D,0x7B, ++0xFC,0x8A,0x01,0x94,0x6A,0xF6,0xAD,0x90, ++0xFE,0x8B,0x42,0x75,0x74,0x29,0x32,0x92, ++0xDF,0xB8,0x32,0x94,0xFF,0xF2,0x7D,0x4B, ++0xDF,0xBE,0x32,0x94,0x09,0xF2,0x7D,0x4B, ++0xFF,0x4A,0xE3,0x97,0xE8,0xF2,0x7D,0x9B, ++0x7F,0x4A,0xF3,0x95,0x74,0x09,0xB3,0x72, ++0xD3,0x80,0xE3,0x95,0x78,0x3C,0x22,0x90, ++0x7E,0xAF,0xE3,0x95,0x6A,0x02,0x02,0x63, ++0x5E,0x90,0xC0,0x95,0x14,0x09,0x22,0x90, ++0xFD,0x9B,0xC2,0x67,0xB8,0xC3,0x32,0x90, ++0xE8,0x8A,0x43,0x7E,0x75,0x09,0xFE,0x92, ++0xFE,0x8B,0xC3,0x77,0x6A,0xF6,0xAD,0x90, ++0xDD,0xB2,0xF3,0x95,0x76,0x21,0x22,0x70, ++0x10,0xB5,0x1C,0x88,0x8B,0x36,0xDD,0x9D, ++0x1F,0x75,0xFC,0x69,0xA9,0xCA,0xCD,0x6F, ++0x02,0x51,0x1C,0x8A,0x83,0x36,0xF1,0x8C, ++0x22,0x4B,0x0C,0x6A,0x89,0xD4,0xDD,0x8F, ++0x04,0xB5,0x30,0x89,0xA9,0xC9,0xCD,0x6F, ++0x02,0x54,0x1C,0x8A,0x89,0x36,0xF1,0x8C, ++0xA2,0x4A,0x0C,0x6A,0x09,0xD6,0xDD,0x8F, ++0x01,0xB5,0x30,0x89,0x89,0xE6,0xDD,0x6F, ++0x00,0x55,0x1C,0x68,0x87,0xF6,0x3D,0x6E, ++0x1E,0x8A,0x93,0x6A,0x89,0xF7,0x6C,0x6D, ++0x1E,0x8A,0x93,0x8A,0x89,0xE7,0xAC,0x6D, ++0xE6,0x8A,0x43,0x81,0xAA,0xCE,0xCD,0x6F, ++0x01,0x6D,0x1C,0x8A,0x9B,0x36,0xDD,0x8D, ++0x00,0xB5,0x1C,0x98,0xAA,0xCA,0xCD,0x6F, ++0x01,0x61,0x1C,0x8A,0x83,0x36,0xF1,0x8C, ++0x21,0x4B,0x0C,0x6A,0x8A,0xE4,0xDD,0x8F, ++0x9D,0x2C,0xA9,0x10,0x33,0x50,0x54,0xF6, ++0x98,0xFD,0x85,0x13,0x10,0xAF,0x68,0x15, ++0x38,0xD3,0x95,0xF3,0x13,0xAF,0x68,0x15, ++0xB9,0xDC,0x49,0xF0,0x93,0x7F,0x44,0x16, ++0xAB,0xFF,0xA4,0xF3,0x00,0x43,0x44,0xF6, ++0x95,0xEC,0x65,0xF2,0x13,0x6F,0x64,0xF5, ++0x87,0x13,0x0A,0xF3,0xED,0xAB,0x24,0xF4, ++0x9A,0xEC,0x05,0xF2,0xED,0x1B,0x27,0xF4, ++0x9E,0xDC,0x69,0xF2,0x2D,0x53,0x67,0xF5, ++0x9B,0xED,0x25,0xF0,0xED,0x5F,0x67,0xF5, ++0x19,0xA5,0x08,0xFB,0x30,0x01,0x6B,0xF5, ++0x90,0xEC,0x08,0xFB,0x36,0x57,0x44,0xF6, ++0xBC,0x54,0x85,0xF3,0x31,0x0B,0x32,0xF0, ++0x92,0x04,0xE0,0xF3,0x11,0xE7,0x20,0xF6, ++0x38,0xFC,0x95,0xF3,0x81,0x09,0xC3,0xF7, ++0xFB,0xCC,0x95,0xF3,0x10,0x6E,0x44,0x34, ++0x99,0xEC,0x85,0x21,0x10,0x1A,0x83,0xF5, ++0x0E,0xEA,0x23,0xF2,0xB6,0x19,0x44,0xF6, ++0x3F,0x85,0x85,0xF3,0x10,0x0F,0x62,0xF5, ++0x0E,0x8A,0x09,0xF2,0x10,0xAD,0x88,0xF5, ++0xB5,0x94,0x85,0xF3,0x15,0xA7,0x28,0xF6, ++0x0E,0xEA,0x21,0xF2,0x8E,0x69,0xE1,0xF7, ++0x38,0x9B,0x85,0xF3,0x37,0x07,0x60,0xF7, ++0xBF,0x8F,0x85,0xF3,0x84,0x68,0xE8,0xF7, ++0xB5,0x24,0x85,0xF3,0x8E,0x64,0xE3,0xF7, ++0x95,0xA4,0x85,0xF3,0x15,0x4F,0xB6,0xF7, ++0x0A,0xE0,0x22,0xF2,0x15,0x7F,0x25,0xF7, ++0x05,0xE2,0x22,0xF2,0x15,0x67,0xB4,0xF7, ++0xBE,0xC4,0xF7,0xF2,0x8E,0x67,0xE3,0xF7, ++0x9E,0xC4,0x67,0x22,0x15,0x47,0xB6,0x37, ++0xBE,0xF4,0xE4,0xF2,0x33,0x1E,0x44,0xF6, ++0x0F,0xEB,0x29,0xF2,0x3E,0xA7,0x44,0xF6, ++0x27,0xC5,0x00,0xD0,0xB7,0x44,0x96,0xD5, ++0x1C,0xE8,0xD5,0xD0,0xA3,0x41,0xC1,0xD5, ++0x3C,0xE7,0x45,0x00,0xB7,0x64,0x94,0x15, ++0x1C,0xD8,0xC6,0xD0,0xAC,0x43,0xC1,0xD5, ++0x37,0x8F,0x83,0xD0,0xB7,0x4C,0x96,0xD5, ++0x1C,0xE0,0xD5,0xD0,0xAC,0x45,0xC1,0xD5, ++0x3C,0xEF,0x45,0x00,0xB7,0x6C,0x94,0x15, ++0x1C,0xD0,0xC6,0xD0,0x3C,0x3D,0x5B,0xD0, ++0xBA,0xD3,0xA7,0xD1,0x12,0x5E,0x47,0xD4, ++0xB9,0xE3,0xA7,0xD1,0x91,0x3A,0x66,0xD4, ++0x9B,0xED,0x85,0xD1,0xA6,0x4A,0xCA,0xD5, ++0xBB,0xC3,0xA7,0xD1,0x1C,0x85,0x66,0xD4, ++0x27,0xC5,0x00,0xD0,0x3C,0x16,0x66,0xD4, ++0x97,0x8B,0x83,0xD0,0x37,0x6D,0x94,0xD5, ++0x28,0xC2,0x00,0xD0,0x37,0x5D,0x07,0xD5, ++0x27,0xC0,0x00,0xD0,0x37,0x45,0x96,0xD5, ++0x36,0x4C,0x7F,0x7A,0x06,0xEF,0x6B,0x7F, ++0x16,0x4C,0xEF,0xAA,0x9D,0xCF,0x3E,0xBF, ++0x36,0x7C,0x6C,0x7A,0xBB,0x96,0xCC,0x7E, ++0x87,0x63,0xA1,0x7A,0xB6,0x2F,0xCC,0x7E, ++0x8D,0x6F,0xAA,0x7A,0x1D,0xEE,0x3C,0x7F, ++0xB6,0x42,0x7F,0x7A,0x09,0xEB,0x6B,0x7F, ++0x96,0x4D,0xEF,0xAA,0x1D,0xCE,0x3E,0xBF, ++0xB6,0x72,0x6C,0x7A,0x06,0xE9,0x6B,0x7F, ++0x96,0x65,0xFD,0x7A,0x3D,0xC9,0xBE,0x7F, ++0x8D,0x6C,0xAA,0x7A,0x1D,0xC6,0x2E,0xAF, ++0x96,0x45,0xFF,0xBA,0x3D,0xF9,0xAD,0x7F, ++0x10,0x79,0x0D,0x7B,0xB8,0xF4,0xED,0x7E, ++0x9D,0x30,0x38,0x7A,0x3B,0x90,0xCC,0x7E, ++0x13,0x49,0x0D,0x7B,0x0C,0xE0,0x60,0x7F, ++0x31,0x47,0x2F,0x7B,0x9A,0xA7,0xC8,0x7D, ++0x11,0x69,0x0D,0x7B,0xB6,0x2F,0xCC,0x7E, ++0xD8,0x3A,0xFF,0x2F,0xC3,0xDC,0x99,0x2B, ++0x43,0x11,0xAA,0x2F,0x5C,0xBE,0x3E,0x2A, ++0x43,0x21,0x39,0x2F,0x53,0xBC,0x3E,0x2A, ++0x43,0x39,0xA8,0x2F,0xE8,0x9A,0xEB,0x2A, ++0xD8,0x39,0xFF,0x2F,0xC8,0x9A,0x7B,0xFA, ++0x43,0x19,0xAA,0xEF,0xE8,0xAA,0xF8,0x2A, ++0x68,0x63,0x6D,0x2F,0xCE,0xA5,0x99,0x2B, ++0x66,0x28,0x79,0x2E,0xCD,0x95,0x99,0x2B, ++0x64,0x18,0x7A,0x2E,0xCF,0xB5,0x99,0x2B, ++0x44,0x71,0x5C,0x2D,0xCC,0x8A,0xB1,0x2B, ++0x4F,0xB9,0x76,0x2E,0xCF,0x52,0x99,0x29, ++0x44,0x81,0x58,0x2C,0xC7,0x72,0x6B,0x2A, ++0x47,0x41,0x29,0x2F,0xC1,0x52,0x97,0x2A, ++0x48,0x11,0x58,0xEE,0xC8,0xA2,0x99,0xEB, ++0x44,0x31,0x68,0x2F,0xCD,0x92,0x8B,0x2A, ++0x45,0x21,0x49,0x2F,0xC4,0x02,0x92,0x2A, ++0xE6,0x5B,0x00,0x85,0x66,0x68,0x42,0x80, ++0xEE,0x2B,0x89,0x87,0x65,0xA8,0x33,0x83, ++0xE0,0x7B,0xFC,0x85,0x69,0x38,0x33,0x41, ++0xE9,0x8B,0xF2,0x44,0x65,0x18,0x03,0x80, ++0xEC,0xBB,0xE0,0x85,0x64,0x08,0x22,0x80, ++0xE5,0x2B,0xF9,0x85,0x6D,0xD8,0xC1,0x80, ++0xED,0xEB,0x83,0x85,0x65,0xA8,0x48,0x82, ++0xE2,0xBB,0xF2,0x44,0x62,0x08,0x33,0x41, ++0xE0,0x7B,0xFC,0x85,0x67,0x68,0x02,0x81, ++0xEF,0xFB,0xD4,0x76,0x6B,0x76,0x05,0x80, ++0xEE,0xBB,0xE7,0x87,0x65,0x08,0x27,0x82, ++0x67,0x9A,0xEF,0x2D,0x65,0x90,0x2E,0x28, ++0xE8,0xFB,0xC4,0x85,0xEC,0x19,0x2E,0x88, ++0xEC,0xBB,0xE0,0x85,0x65,0x50,0x2E,0x88, ++0xEF,0x8B,0xF3,0x85,0x64,0x28,0xD0,0x82, ++0xF0,0x64,0x7D,0x84,0xE5,0x98,0xEC,0x1E, ++0x1B,0x6F,0xA1,0x97,0x94,0xE8,0x6C,0x9E, ++0x10,0x66,0xAE,0x9E,0x9F,0xE1,0x6A,0x98, ++0x09,0x7D,0xB4,0x80,0x81,0xFC,0x70,0x82, ++0x0C,0x7A,0xB2,0x85,0x8A,0xF6,0x7D,0x8D, ++0x02,0x77,0xB9,0x8E,0x8F,0xF1,0x7A,0x88, ++0x06,0x4C,0x85,0xB3,0xB3,0xCD,0x46,0xB4, ++0x3A,0x48,0x81,0xB7,0xB7,0xC9,0x42,0xB0, ++0x3E,0x44,0x8D,0xBB,0xBB,0xC5,0x4E,0xBD, ++0x32,0x47,0x89,0xBE,0xBF,0xC2,0x49,0xB9, ++0x37,0x43,0x8A,0xBD,0xA2,0xDF,0x54,0xA6, ++0x28,0x5E,0x97,0xA0,0xA1,0xDC,0x57,0xA3, ++0x2D,0x58,0x90,0xA7,0xA7,0xD9,0x52,0xA1, ++0x2E,0x5B,0x92,0xAA,0xAA,0xD7,0x5C,0xAE, ++0x20,0x55,0x9F,0xA8,0xA8,0xD4,0x5F,0xAC, ++0x22,0x50,0x99,0xAE,0xAE,0xD2,0x59,0xAA, ++0x24,0x52,0x9B,0xAC,0xED,0x90,0x48,0x0B, ++0x70,0x13,0xDA,0xA7,0x6B,0xE0,0xAB,0x09, ++0x77,0x13,0xDA,0xE7,0xF1,0xD0,0x36,0x01, ++0x01,0x63,0x7A,0x0C,0xEE,0x90,0x36,0x01, ++0x76,0x13,0x7A,0x0E,0xFD,0x80,0xBB,0x0B, ++0x66,0x13,0x7A,0x0E,0xE2,0x90,0xA6,0x00, ++0x67,0xA3,0x51,0x0F,0xEC,0x90,0x40,0x0B, ++0x41,0x63,0x6A,0xEC,0xFD,0xD0,0xA6,0x00, ++0x67,0x33,0x48,0xCF,0xEC,0x80,0x8A,0xCA, ++0x64,0x02,0x7A,0xCE,0xED,0xA0,0xB8,0x0A, ++0x64,0x12,0xDA,0x0F,0xED,0x90,0x98,0x09, ++0x78,0xEC,0xF5,0x0C,0x16,0x6F,0xE4,0xD2, ++0xC4,0x63,0x6A,0x0C,0x07,0x6F,0xE4,0x02, ++0x60,0x7B,0x5C,0x0C,0xAD,0x90,0x68,0x0B, ++0x40,0x7B,0x7A,0x0C,0xE2,0x90,0x1B,0x32, ++0x46,0x13,0xA9,0x0E,0xEF,0xF0,0x9D,0x39, ++0x67,0x33,0x7A,0x3C,0xED,0x80,0xBB,0x3B, ++0x20,0x45,0x3F,0x59,0x8B,0xC6,0x0E,0x6C, ++0xDD,0x8A,0x43,0x81,0x8D,0x9E,0xFB,0x6F, ++0x20,0x05,0xDF,0x69,0xAD,0x9E,0xDD,0x6F, ++0x12,0x12,0x3A,0x6A,0xB9,0xD5,0xDD,0x6F, ++0x11,0x52,0x3E,0x6A,0xBA,0xE5,0xDD,0x6F, ++0x00,0x45,0x1C,0x68,0x5F,0x09,0x82,0x64, ++0x02,0x15,0x3A,0x6A,0x8B,0xC6,0xDD,0x6D, ++0x00,0x55,0x1C,0x68,0x8D,0x9E,0xFB,0x6F, ++0x26,0x1D,0x1C,0x6A,0x8A,0x96,0xFB,0x6F, ++0x00,0x65,0x1C,0x68,0x8D,0x9E,0xFB,0x3F, ++0x26,0x1D,0x1C,0x3A,0x41,0x09,0x82,0x64, ++0xC0,0x3D,0x91,0x62,0x89,0x46,0xDD,0x6F, ++0x30,0x75,0x91,0x62,0xB3,0xF6,0xEC,0x66, ++0x07,0x75,0x2C,0x63,0x0B,0x36,0xAC,0x6F, ++0x83,0xB5,0x68,0xCA,0x8A,0xF6,0x7D,0xD4, ++0xED,0x8B,0x43,0x60,0x35,0x09,0x82,0x65, ++0x0F,0x8A,0xFE,0x9C,0x74,0x81,0x3F,0x99, ++0x3F,0xC2,0x6E,0x9D,0x76,0xB9,0x22,0x90, ++0xCF,0x8A,0x6E,0x9D,0x4C,0x09,0x13,0x99, ++0xF8,0x8A,0xD3,0x9C,0x75,0x08,0x92,0x92, ++0xFE,0x8B,0x50,0x77,0x75,0x09,0x82,0x6B, ++0xFD,0x8A,0x43,0x9F,0xC6,0xF6,0x7D,0x9A, ++0x0F,0x8A,0xFE,0x9C,0x74,0x81,0x3F,0x99, ++0x00,0xFE,0x83,0x97,0x77,0x09,0xA2,0x91, ++0x00,0x4E,0x80,0x97,0x78,0x39,0x05,0x91, ++0xC0,0xB6,0x00,0x96,0x76,0x08,0x82,0x93, ++0x01,0xBA,0x00,0x96,0x74,0x09,0xB0,0x92, ++0xA2,0x8A,0x43,0x7E,0x74,0x09,0xB7,0x92, ++0xC2,0x8A,0x43,0x7E,0x75,0x40,0xAF,0x98, ++0xDE,0x82,0xE3,0x95,0x50,0x61,0x22,0x90, ++0xFF,0x02,0x82,0x95,0xE4,0x0F,0x8E,0x91, ++0xF9,0xF2,0x87,0x95,0xEC,0x0F,0x84,0x91, ++0xB5,0x5F,0x96,0x49,0x39,0xD3,0x58,0x4C, ++0x24,0xDF,0x06,0x49,0x8F,0x1C,0xF3,0x4C, ++0x00,0xEF,0x3E,0x48,0xAE,0x5C,0xC7,0x4C, ++0x07,0x3F,0x3E,0x48,0x8E,0xDC,0xF3,0x4C, ++0x29,0xBF,0x5C,0x48,0x32,0xD2,0x53,0x4C, ++0x24,0x2F,0x5B,0x48,0x37,0xD2,0x59,0x4C, ++0xB5,0x59,0x90,0x49,0x32,0xD3,0x58,0x4C, ++0x24,0xBF,0x00,0x49,0x8F,0x1C,0xF3,0x4C, ++0x22,0x37,0x3E,0x4A,0xAE,0x3C,0xC1,0x4C, ++0x05,0xEF,0x32,0x49,0xA2,0x54,0xC7,0x4C, ++0x22,0x57,0x3E,0x4B,0xA7,0x64,0xC7,0x4C, ++0x22,0xD7,0x26,0x49,0xA9,0xD4,0xFF,0x4E, ++0x20,0x27,0xCF,0x49,0xA9,0xC4,0xFF,0x4F, ++0x23,0x47,0x7E,0x98,0xAC,0xB4,0x1B,0x9C, ++0x26,0x97,0xCB,0xB9,0x8E,0x9C,0xFF,0x4D, ++0x22,0x47,0x3E,0xAA,0xAE,0xB4,0x19,0x9C, ++0x73,0x5A,0x0C,0x1D,0xD0,0xF9,0xAA,0x18, ++0x76,0x12,0x2B,0xCD,0x68,0xE6,0x28,0x19, ++0x70,0xCA,0x07,0x1D,0x69,0x86,0x0D,0x19, ++0xEB,0x07,0xCD,0x1C,0x68,0x8D,0x06,0x19, ++0x70,0x6A,0x5D,0x1C,0xDB,0xA9,0xA8,0x19, ++0x7B,0x6A,0x5D,0x1C,0xD0,0xA9,0xA8,0x19, ++0x71,0x62,0x50,0x1C,0xF2,0x60,0x84,0x18, ++0x75,0x22,0x73,0x1C,0xFD,0x91,0xBA,0x19, ++0x59,0x63,0x4D,0x1D,0xFD,0x08,0xB7,0xB1, ++0x71,0x62,0x5D,0x1C,0xFE,0xA1,0xB8,0x19, ++0x76,0x12,0x6A,0x1C,0xFD,0xB1,0x49,0x1B, ++0x76,0x8B,0x76,0x14,0xD8,0xD9,0xAA,0x18, ++0x56,0x7A,0x6B,0x1D,0xF9,0xE9,0xCE,0x18, ++0x70,0xCA,0x0A,0x1D,0x69,0x86,0x0E,0x19, ++0xE1,0x05,0xCC,0x1C,0x60,0x87,0x0B,0x19, ++0xE2,0x0E,0xC7,0x1C,0xFB,0x99,0x9B,0x19, ++0x72,0x68,0x4D,0x3E,0xFC,0xDB,0x88,0x3A, ++0x59,0x38,0x78,0x3E,0xF2,0xEB,0x8C,0x3B, ++0x52,0xE8,0x2B,0x3F,0x4B,0xA4,0x2A,0x3B, ++0xC3,0x27,0xEE,0x3E,0x42,0xA5,0x2E,0x3B, ++0xC0,0x2C,0xE5,0x3E,0xD9,0xCB,0xBE,0x3B, ++0x72,0x08,0x4B,0x3E,0xD2,0xCB,0xBE,0x3B, ++0x79,0x78,0x4B,0x3E,0xDF,0x83,0xBD,0x3B, ++0x55,0x30,0x5D,0x3C,0xC0,0x5C,0x07,0x9A, ++0x53,0x40,0x7F,0x3E,0xDC,0x83,0x9A,0x3B, ++0x54,0x30,0x48,0x3E,0xDF,0x93,0x6B,0x39, ++0x4B,0xDF,0xC6,0x3F,0xDE,0xA3,0x1D,0x38, ++0x48,0x20,0xE9,0xD4,0xFF,0x8B,0x88,0x3A, ++0x71,0x58,0x49,0x3F,0xDC,0xCB,0xE9,0x3A, ++0x52,0xE8,0x2D,0x3F,0x4C,0xA4,0x29,0x3B, ++0xC3,0x27,0xEE,0x3E,0x42,0xA5,0x2C,0x3B, ++0xC7,0x2C,0xE5,0x3E,0xD9,0xEB,0xBC,0x3B, ++0xEB,0xA1,0xD1,0xA7,0x62,0x42,0x11,0xA3, ++0xC0,0xF1,0xE4,0xA7,0x6B,0x22,0x10,0xA2, ++0xCB,0x71,0xB5,0xA6,0xD5,0x3D,0xB4,0xA2, ++0x5A,0xBE,0x77,0xA7,0xDB,0x3C,0xB7,0xA2, ++0x5E,0xB5,0x7C,0xA7,0x40,0x52,0x27,0xA2, ++0xEB,0xE1,0xD5,0xA7,0x4B,0x52,0x27,0xA2, ++0xE0,0x91,0xD5,0xA7,0x43,0x1A,0x23,0xA2, ++0xCC,0xA9,0xC1,0xA5,0x59,0xC5,0x9E,0x03, ++0xCA,0xD9,0xE6,0xA7,0x45,0x1A,0x03,0xA2, ++0xCD,0xA9,0xD1,0xA7,0x46,0x0A,0xF2,0xA0, ++0xD2,0x46,0x5F,0xA6,0x63,0x62,0x11,0xA3, ++0xED,0xC1,0xD0,0xA6,0x42,0x52,0x75,0xA3, ++0xCB,0x71,0xB1,0xA6,0xD2,0x3D,0xB0,0xA2, ++0x5A,0xBE,0x77,0xA7,0xDB,0x3C,0xB3,0xA2, ++0xCC,0xD9,0xD0,0xA4,0xD2,0x36,0xBD,0xA2, ++0xCB,0x91,0xE2,0xA7,0x60,0x22,0x10,0xA2, ++0x7B,0x2A,0x59,0x1C,0xD0,0x99,0xBB,0x19, ++0x69,0xFD,0xE4,0xBD,0xFE,0xA1,0x98,0x19, ++0x76,0x12,0x6A,0x1C,0xFD,0xB1,0x49,0x1B, ++0x69,0xFD,0xE4,0x1D,0xFC,0x41,0xAA,0x1A, ++0x6B,0xFD,0xE4,0x1D,0xF8,0x71,0x15,0x1C, ++0xEE,0x75,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0x7C,0x75,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0xC2,0x75,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0xBC,0x82,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0x74,0x83,0xC9,0xDC,0xF8,0x71,0x15,0x1C, ++0x46,0x7C,0xC9,0xDC,0x7D,0x91,0xAA,0x18, ++0xF6,0x07,0x5B,0x1D,0xF8,0x81,0xAA,0xEA, ++0xD6,0x28,0x7B,0x1D,0xE8,0xA1,0x95,0x1C, ++0x76,0x02,0x4B,0xEF,0x5D,0x8B,0x58,0x18, ++0x75,0x02,0x4B,0xFF,0xFD,0x81,0x5A,0x1A, ++0x72,0x02,0x6B,0xFF,0xE2,0x7E,0x25,0x18, ++0xBB,0x36,0xF8,0xCF,0xDF,0xF2,0x14,0x23, ++0x44,0x31,0xA9,0x2C,0xC6,0xB2,0x39,0xC0, ++0x44,0x31,0x29,0x2A,0xCF,0xB2,0x69,0x29, ++0x42,0x31,0xF8,0xC5,0xEF,0xB2,0xA6,0x2F, ++0x44,0x31,0x77,0x2F,0x79,0x4F,0xC6,0x21, ++0x44,0x31,0xA8,0x2C,0xCE,0xB2,0x39,0xC0, ++0x44,0x31,0x48,0x2C,0xDF,0x32,0x84,0x22, ++0x4C,0x31,0x67,0x2A,0xCF,0xB2,0xB6,0x2A, ++0x54,0xB1,0x45,0x27,0xBF,0xB3,0x39,0xCA, ++0x18,0x30,0xF8,0xCF,0xDF,0xF2,0x14,0x23, ++0x44,0x31,0xA9,0x2C,0xC6,0xB2,0x39,0xC0, ++0x44,0x31,0x29,0x2A,0xCF,0xB2,0x69,0x29, ++0x42,0x31,0xF8,0xC5,0xEF,0xB2,0xA6,0x2F, ++0x44,0x31,0x77,0x2F,0x6B,0x4F,0xC6,0x21, ++0x44,0x31,0xA8,0x2C,0xCE,0xB2,0x39,0xC0, ++0x44,0x31,0x48,0x2C,0xDF,0x32,0x84,0x22, ++0x19,0x64,0x32,0x7F,0x9A,0xE7,0xE3,0x7F, ++0x01,0xE4,0x10,0x72,0xA2,0xE5,0x6C,0x9F, ++0x35,0x66,0xAD,0x9A,0x84,0x18,0x43,0x7E, ++0x11,0x64,0x0D,0x79,0x84,0x18,0x43,0x7E, ++0xD8,0x9B,0x52,0x70,0xF7,0x86,0x05,0xF1, ++0x11,0x64,0xAD,0x9A,0x9A,0xE7,0x6C,0x9F, ++0x11,0x64,0xAD,0x9A,0xAA,0xD6,0x5E,0xAC, ++0x25,0x51,0x9B,0xAD,0xA2,0xDE,0x2D,0xDD, ++0x52,0x20,0xE8,0xDC,0xDA,0xD7,0x34,0x9F, ++0x21,0x55,0x9F,0xA9,0xAE,0xD2,0x5A,0xA8, ++0x29,0x5D,0xCC,0xF8,0xF9,0x83,0x09,0xF9, ++0x51,0x54,0xD5,0x9A,0x9E,0xE7,0x6C,0x97, ++0x11,0x64,0xAD,0x9A,0x9A,0xE7,0x6C,0x9D, ++0x11,0x65,0xAD,0x9A,0x8A,0xE7,0x6C,0x9F, ++0x13,0x24,0xAD,0x9A,0x9A,0xE7,0x6C,0x3F, ++0x11,0x64,0xAD,0x9A,0x9F,0xA7,0x6C,0x9F, ++0xDD,0xA8,0x61,0x9E,0x56,0x2B,0xA0,0x53, ++0xD1,0xE8,0x61,0x56,0x56,0x2B,0xE0,0xCF, ++0xDD,0xA8,0x61,0x56,0x4F,0x6B,0xA0,0x53, ++0xDD,0x88,0xDD,0xE8,0x56,0x2B,0xA0,0x53, ++0xE9,0xE8,0x61,0x56,0xE9,0xE2,0xBB,0xDD, ++0xDD,0xA8,0x61,0x52,0xE3,0x6B,0xA0,0x53, ++0x8D,0xE3,0xAE,0x86,0x30,0x2C,0x42,0x9C, ++0xDC,0xA8,0x61,0x56,0x3A,0x6A,0xA0,0x53, ++0xE3,0x2A,0x30,0xFC,0x89,0xC5,0x07,0x67, ++0xDC,0xA8,0x61,0x56,0x8F,0x69,0xA0,0x53, ++0x01,0x1D,0xC1,0xB4,0x6C,0x1B,0xBF,0xC4, ++0x22,0x57,0x9E,0xA9,0xE2,0x6E,0xA0,0x53, ++0x20,0x8D,0xC1,0x9E,0xBF,0x88,0x61,0x1C, ++0x22,0x57,0x9E,0xA9,0xA9,0x14,0xA0,0x53, ++0xDD,0xA8,0x61,0xD6,0x56,0x2B,0xA0,0x53, ++0x22,0x97,0x61,0x56,0x56,0x2B,0xA0,0xD3, ++0x33,0x46,0x8F,0xB8,0x98,0x4A,0x4C,0x9D, ++0x13,0xC9,0x8D,0x98,0xD8,0xE5,0x4E,0xBD, ++0x93,0x16,0x8D,0x98,0xA8,0xC4,0x4E,0xBD, ++0x70,0x46,0x8F,0xB8,0x40,0x3A,0xB1,0x42, ++0x33,0x06,0xCF,0xF8,0xF8,0x85,0x0E,0xFD, ++0x73,0x06,0xCE,0xF9,0xF9,0x84,0x0F,0xFD, ++0x73,0x06,0xCF,0xF8,0xF8,0x85,0x0E,0xFD, ++0x73,0x06,0xCF,0xF8,0xF8,0x85,0x0E,0xFD, ++0x73,0x43,0x8D,0xBA,0xBA,0xC7,0x4C,0xBF, ++0x31,0x44,0x8D,0xBA,0xBA,0xC7,0x4C,0xBF, ++0x31,0x66,0xAF,0x98,0x98,0xE5,0x6E,0x9D, ++0x13,0x66,0xAF,0xBA,0xBA,0xC7,0x4C,0xBF, ++0x31,0x44,0x1F,0x28,0x28,0x55,0xDE,0x2D, ++0x23,0x56,0x9F,0xA8,0xA8,0xD5,0x5E,0xAD, ++0x23,0x56,0x9F,0xA8,0xA8,0xD5,0x5E,0xAD, ++0x23,0x56,0x9F,0xA8,0xBA,0xC7,0x4C,0xBF, ++0x57,0x22,0x61,0x56,0x56,0x2B,0xA0,0x53, ++0x5D,0x28,0xE1,0xD6,0xD6,0xAB,0x20,0xD3, ++0x5D,0x28,0xE1,0xD6,0xD6,0xAB,0x20,0xD3, ++0x5D,0x28,0xE1,0xD6,0xDC,0xA1,0x2A,0xD9, ++0x15,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x55,0x20,0xE9,0xDE,0xDE,0xA3,0x28,0xDB, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xE0,0x81,0x0A,0xF9, ++0x34,0x02,0xCB,0xFC,0x04,0x7E,0xF5,0x06, ++0x7B,0x02,0xCB,0xFC,0xF2,0x81,0x0A,0xF9, ++0x78,0x02,0xCB,0xFC,0xD2,0x81,0x0A,0xF9, ++0x77,0x02,0xCB,0xFC,0xFC,0x81,0x0A,0xF9, ++0xD0,0xB2,0xFB,0x73,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0x9E,0xA4,0x5B,0xD3,0x01,0x00,0x00,0x00, ++0x01,0x00,0x08,0x01,0x01,0x00,0x00,0x01, ++0x64,0xF6,0xC0,0x06,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xB7,0x76,0xD2,0x16,0x0F,0x45,0x0F,0x8F, ++0xC3,0x71,0xEC,0xE3,0xCE,0xFF,0x99,0x49, ++0x47,0x38,0xC9,0xA2,0xFB,0xA3,0xC3,0xC9, ++0x7D,0xD4,0x1B,0xFE,0x23,0xF3,0x60,0xD4, ++0x7C,0xAC,0x96,0x86,0x31,0x91,0x17,0x6A, ++0xD3,0x79,0x07,0x64,0x9F,0x81,0xF3,0x83, ++0x9D,0xAC,0x3D,0x11,0x4D,0xEA,0xF2,0xA2, ++0x6E,0x05,0x77,0x40,0xA1,0x94,0x0E,0x8C, ++0x3D,0xA0,0xF9,0x33,0x3A,0x82,0x6C,0xDE, ++0x9F,0xFC,0x77,0xFA,0xC4,0x33,0x73,0x07, ++0x6E,0x8C,0x48,0xE3,0x37,0x39,0x01,0x6D, ++0xFC,0x24,0xB0,0x4A,0x32,0x97,0xF4,0xC8, ++0x3A,0x1E,0x17,0x01,0x51,0x85,0x06,0xF9, ++0x7E,0x7F,0x55,0x11,0x8A,0x58,0x19,0x8D, ++0x0B,0x67,0x12,0x3D,0xB1,0x66,0x7D,0xA6, ++0x30,0x42,0xC5,0xC8,0x40,0x1D,0xAD,0x79, ++0x6A,0xC8,0x0F,0x30,0x6A,0x7A,0x33,0x59, ++0xC1,0x28,0xC6,0xE3,0xC4,0x8F,0xDA,0x8A, ++0x21,0x82,0x05,0xAA,0x01,0x11,0x7F,0xE9, ++0x47,0x9D,0x66,0x3D,0x05,0x3E,0x49,0xC5, ++0x75,0xEE,0xA9,0x7C,0x0B,0x16,0x8F,0x9F, ++0xEC,0x26,0xEB,0x7C,0x06,0x04,0x37,0x23, ++0xDD,0x50,0x17,0xBC,0xDB,0xE5,0xB2,0xBA, ++0x72,0x13,0x09,0x33,0xD6,0x5F,0x15,0xCE, ++0x18,0xB6,0xCF,0xA0,0xF4,0x4F,0x87,0xCA, ++0x48,0x3F,0x63,0x94,0x0C,0x26,0xD7,0xA1, ++0x4B,0xEB,0x28,0xAA,0xDB,0xFA,0x83,0x2A, ++0x09,0x66,0x26,0x0B,0x15,0xD0,0x3F,0x33, ++0xB3,0x23,0x0F,0xD0,0xFE,0x71,0x1C,0x05, ++0xEE,0xAE,0x61,0x3E,0x12,0xE4,0x6A,0x9B, ++0x3D,0xF5,0xF7,0xF8,0x58,0xE0,0x99,0x12, ++0x2A,0xA7,0x85,0xFF,0xC1,0x1B,0x46,0x75, ++0x00,0x00,0x00,0x11,0x00,0x00,0x00,0x00, ++0x01,0x19,0xA6,0x7D,0x9B,0xF9,0x12,0x75, ++0xA2,0x99,0x27,0x2B,0x93,0x10,0xDD,0xBC, ++0x22,0x1C,0x89,0xA3,0x4F,0x12,0x49,0x21, ++0xC1,0x71,0x31,0xB9,0x1F,0xB5,0x86,0x4A, ++0x58,0xB2,0xB9,0xB5,0xDF,0x3B,0x95,0x47, ++0xF4,0xA2,0x1C,0x72,0x8A,0x31,0xA4,0xAF, ++0xA0,0x95,0x57,0x79,0x93,0x77,0x22,0x3F, ++0x25,0xBB,0xAC,0xBC,0x45,0x0B,0xB8,0x4E, ++0x31,0xC2,0xCC,0x7A,0xA8,0x32,0xE8,0xE2, ++0x0E,0x4D,0x8F,0xDF,0xDF,0x70,0x85,0x42, ++0xC7,0xC9,0x78,0x4A,0xB4,0x94,0x6A,0x56, ++0xB5,0x3A,0x10,0xF8,0xBB,0xF4,0xA0,0x55, ++0xB5,0xE3,0xA0,0x5D,0x6B,0x9A,0x9A,0xED, ++0x13,0x67,0xF3,0xE4,0x04,0x20,0x12,0x87, ++0xFF,0xA2,0xB5,0x71,0x0F,0x85,0x75,0x3F, ++0xB0,0x21,0xC9,0x73,0x55,0x06,0x53,0x9A, ++0x2B,0x42,0x4C,0xFC,0x24,0x8E,0xB5,0xF7, ++0x54,0x98,0x85,0xD8,0x7C,0xE9,0x8B,0x5A, ++0x82,0x4B,0x11,0xF6,0x8F,0x7A,0xF4,0x4F, ++0xC7,0x65,0x31,0xC0,0x65,0x05,0x1D,0x08, ++0xBF,0x0B,0xDD,0x0C,0xBD,0xF1,0xF5,0x4B, ++0xA1,0xA8,0x12,0xEE,0x72,0x86,0xA5,0xA6, ++0x5C,0x86,0x1E,0x9F,0xB5,0xD8,0x4C,0x82, ++0x63,0x64,0xC2,0x8D,0x7C,0x96,0x1D,0x31, ++0x38,0xA8,0xA1,0xF0,0x39,0x10,0xEC,0xCB, ++0x11,0x3A,0x62,0x9F,0x59,0x3B,0x58,0x52, ++0x23,0x82,0x73,0x11,0x21,0x8F,0xAB,0x45, ++0x1F,0x16,0xF5,0xA6,0xD0,0x08,0x85,0x72, ++0xE4,0xB7,0xAE,0xE5,0x33,0xA5,0x17,0xDF, ++0xC9,0xC8,0xC0,0xBA,0xC6,0xD9,0x67,0x49, ++0x5E,0xC2,0xB7,0x90,0x7F,0x07,0x1F,0xC8, ++0xA3,0x36,0xB2,0xFA,0x01,0x7F,0xA9,0x09, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 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++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, +\ No newline at end of file +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_hal.c b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_hal.c +new file mode 100644 +index 00000000..70c7bfe5 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_hal.c +@@ -0,0 +1,3566 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//======================================================== ++// HAL pre-processors ++//======================================================== ++#if IF_FCIE_SHARE_IP ++ // re-config FCIE3 for NFIE mode ++ #define eMMC_RECONFIG() //eMMC_ReConfig(); ++#else ++ // NULL to save CPU a JMP/RET time ++ #define eMMC_RECONFIG() ++#endif ++ ++ ++#if eMMC_RSP_FROM_RAM ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) \ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSPFROMRAM_SAVE)\ ++ eMMC_KeepRsp(pu8_OneRspBuf, u8_CmdIdx) ++#else ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) // NULL to save CPU a JMP/RET time ++#endif ++ ++ ++#define eMMC_FCIE_CLK_DIS() REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN) ++ ++#define eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT 30 ++#define eMMC_CMD_API_ERR_RETRY_CNT 30 ++#define eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT 30 ++ ++#define eMMC_CMD1_RETRY_CNT 0x1000 ++#define eMMC_CMD3_RETRY_CNT 0x5 ++ ++//======================================================== ++// HAL APIs ++//======================================================== ++U32 eMMC_FCIE_WaitEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ return eMMC_WaitCompleteIntr(u32_RegAddr, u16_Events, u32_MicroSec); ++ #else ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ u16_Events |= BIT_CARD_DMA_END; ++ ++ //eMMC_printf("A"); ++ return eMMC_FCIE_PollingEvents(u32_RegAddr, u16_Events, u32_MicroSec); ++ #endif ++} ++ ++U32 eMMC_FCIE_PollingEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ volatile U32 u32_i; ++ volatile U16 u16_val; ++ for(u32_i=0; u32_i>REG_OFFSET_SHIFT_BITS, ++ u16_val, u16_Events); ++ ++ return eMMC_ST_ERR_TIMEOUT_WAIT_REG0; ++ } ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U16 sgau16_eMMCDebugBus[100]; ++void eMMC_FCIE_DumpDebugBus(void) ++{ ++ volatile U16 u16_reg, u16_i; ++ U16 u16_idx = 0; ++ ++ memset(sgau16_eMMCDebugBus, 0xFF, sizeof(sgau16_eMMCDebugBus)); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ ++ for(u16_i=0; u16_i<8; u16_i++) ++ { ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_FCIE_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, u16_i< 0; u16_i--) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "%u ", u16_i); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ ++ // check FCIE reg.30h ++ REG_FCIE_R(FCIE_TEST_MODE, u16_reg); ++ if(0)//u16_reg & BIT_FCIE_BIST_FAIL) /* Andersen: "don't care." */ ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h BIST fail: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_BIST_FAIL; ++ } ++ if(u16_reg & BIT_FCIE_DEBUG_MODE_MASK) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h Debug Mode: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_DEBUG_MODE; ++ } ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ } ++ #endif // eMMC_TEST_IN_DESIGN ++ ++ // ------------------------------------------ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); ++ REG_FCIE_W(FCIE_MMA_PRI_REG, BIT_MIU_CLK_FREE_RUN); ++ REG_FCIE_W(FCIE_PATH_CTRL, BIT_SD_EN); ++ // all cmd are 5 bytes (excluding CRC) ++ REG_FCIE_W(FCIE_CMD_SIZE, eMMC_CMD_BYTE_CNT); ++ REG_FCIE_W(FCIE_SD_CTRL, 0); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ #if FICE_BYTE_MODE_ENABLE ++ // default sector size: 0x200 ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE | eMMC_SECTOR_512BYTE); ++ #else ++ REG_FCIE_W(FCIE_SDIO_CTRL, 0); ++ #endif ++ //REG_FCIE_W(FCIE_BOOT_CONFIG, 0); // set by eMMC_pads_switch ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, 0); ++ eMMC_FCIE_ClearEvents(); ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; // ok ++} ++ ++ ++#if 1// defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++void eMMC_DumpDDRTTable(void) ++{ ++ U16 u16_i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC DDR Timing Table: Cnt:%u CurIdx:%u \n", ++ g_eMMCDrv.DDRTable.u8_SetCnt, g_eMMCDrv.DDRTable.u8_CurSetIdx); ++ ++ for(u16_i=0; u16_i 500 && u32_us-u32_cnt > 1000) ++ { ++ eMMC_hw_timer_sleep(1); ++ u32_cnt += 1000-2; ++ } ++ } ++ ++ return u32_cnt; ++} ++ ++U32 eMMC_FCIE_WaitD0High(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ ++ u32_cnt = eMMC_FCIE_WaitD0High_Ex(u32_us); ++ ++ if(u32_us == u32_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H timeout %u us\n", u32_cnt); ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++#define FIFO_CLK_RDY_CHECK_CNT 3 ++U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir) ++{ ++ volatile U32 u32_cnt=0; ++ volatile U16 au16_read[FIFO_CLK_RDY_CHECK_CNT], u16_i; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_MMA_PRI_REG, au16_read[0]); ++ if(u8_Dir == (au16_read[0]&BIT_DMA_DIR_W)) ++ break; ++ } ++ if(TIME_WAIT_FIFOCLK_RDY == u32_cnt) ++ return eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ for(u16_i=0; u16_i>24)<<8) | (0x40|u8_CmdIdx)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), u32_Arg&0xFF); ++ ++ REG_FCIE_R(FCIE_CIFC_ADDR(0),au16_tmp[0]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(1),au16_tmp[1]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(2),au16_tmp[2]); ++ ++ if(au16_tmp[0] == (((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx))&& ++ au16_tmp[1] == ((u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF))&& ++ au16_tmp[2] == (u32_Arg&0xFF)) ++ break; ++ } ++ ++ if(12 != u8_CmdIdx) ++ { ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ #endif ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSP_WAIT_D0H){ ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ // wait event ++ //eMMC_printf("eMMC_FCIE_SendCmd %X, %X, %X, %X, %X", u16_Mode, u16_Ctrl, u32_Arg, u8_CmdIdx, u8_RspByteCnt); ++ //eMMC_printf("M"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, TIME_WAIT_CMDRSP_END); ++ ++ LABEL_SEND_CMD_ERROR: ++ return u32_err; ++ ++} ++ ++ ++void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ eMMC_die("\n"); // should be system fatal error, not eMMC driver ++ } ++ ++ memcpy(g_eMMCDrv.au8_AllRsp + u16_idx, pu8_OneRspBuf, u8_ByteCnt); ++ ++} ++ ++ ++U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ if(0 == g_eMMCDrv.au8_AllRsp[u16_idx]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: no rsp, %u %u \n", u8_CmdIdx, u16_idx); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ memcpy(pu8_OneRspBuf, g_eMMCDrv.au8_AllRsp + u16_idx, u8_ByteCnt); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ------------------------------- ++U32 eMMC_SaveRsp(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_SaveDriverContext(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_LoadDriverContext(U8 *pu8_Buf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++//======================================================== ++// Send CMD HAL APIs ++//======================================================== ++U32 eMMC_Identify(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_i, u16_retry=0; ++ ++ g_eMMCDrv.u16_RCA=1; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ LABEL_IDENTIFY_CMD0: ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(u16_retry > 10) ++ return u32_err; ++ if(u16_retry) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Warn: retry: %u\n", u16_retry); ++ ++ // CMD0 ++ u32_err = eMMC_CMD0(0); // reset to idle state ++ if(eMMC_ST_SUCCESS != u32_err) ++ {u16_retry++; goto LABEL_IDENTIFY_CMD0;} ++ ++ // CMD1 ++ for(u16_i=0; u16_i>6; ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 1); ++ } ++ } ++ #else ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD1 ok, do things here ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ else ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ } ++ } ++ #endif ++ ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// send CID ++U32 eMMC_CMD2(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 2, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD2, %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD2; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD2 Reg.12: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD2 ok, do things here (get CID) ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CID); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CID, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CID, 2); ++ } ++ } ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// CMD3: assign RCA. CMD7: select device ++U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ if(7 == u8_CmdIdx) ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ else{ ++ u8_retry_fcie = 0xF0; // CMD3: not retry ++ } ++ ++ u32_arg = u16_RCA<<16; ++ ++ if(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA) ++ u16_ctrl = BIT_SD_CMD_EN; ++ else ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ return u32_err; ++ } ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ // de-select has no rsp ++ if(!(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA)){ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ return u32_err; ++ } ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ return u32_err; ++ } ++ ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ }} ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_CSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------ ++ g_eMMCDrv.u8_SPEC_VERS = (g_eMMCDrv.au8_CSD[1]&0x3C)>>2; ++ g_eMMCDrv.u8_R_BL_LEN = g_eMMCDrv.au8_CSD[6] & 0xF; ++ g_eMMCDrv.u8_W_BL_LEN = ((g_eMMCDrv.au8_CSD[13]&0x3)<<2)+ ++ ((g_eMMCDrv.au8_CSD[14]&0xC0)>>6); ++ ++ // ------------------------------ ++ g_eMMCDrv.u16_C_SIZE = (g_eMMCDrv.au8_CSD[7] & 3)<<10; ++ g_eMMCDrv.u16_C_SIZE += g_eMMCDrv.au8_CSD[8] << 2; ++ g_eMMCDrv.u16_C_SIZE +=(g_eMMCDrv.au8_CSD[9] & 0xC0) >> 6; ++ if(0xFFF == g_eMMCDrv.u16_C_SIZE) ++ { ++ g_eMMCDrv.u32_SEC_COUNT = 0; ++ } ++ else ++ { ++ g_eMMCDrv.u8_C_SIZE_MULT = ((g_eMMCDrv.au8_CSD[10]&3)<<1)+ ++ ((g_eMMCDrv.au8_CSD[11]&0x80)>>7); ++ ++ g_eMMCDrv.u32_SEC_COUNT = ++ (g_eMMCDrv.u16_C_SIZE+1)* ++ (1<<(g_eMMCDrv.u8_C_SIZE_MULT+2))* ++ ((1<>9) - 8; // -8: //Toshiba CMD18 access the last block report out of range error ++ } ++ // ------------------------------ ++ g_eMMCDrv.u8_ERASE_GRP_SIZE = (g_eMMCDrv.au8_CSD[10]&0x7C)>>2; ++ g_eMMCDrv.u8_ERASE_GRP_MULT = ((g_eMMCDrv.au8_CSD[10]&0x03)<<3)+ ++ ((g_eMMCDrv.au8_CSD[11]&0xE0)>>5); ++ g_eMMCDrv.u32_EraseUnitSize = (g_eMMCDrv.u8_ERASE_GRP_SIZE+1)* ++ (g_eMMCDrv.u8_ERASE_GRP_MULT+1); ++ // ------------------------------ ++ // others ++ g_eMMCDrv.u8_TAAC = g_eMMCDrv.au8_CSD[2]; ++ g_eMMCDrv.u8_NSAC = g_eMMCDrv.au8_CSD[3]; ++ g_eMMCDrv.u8_Tran_Speed = g_eMMCDrv.au8_CSD[4]; ++ g_eMMCDrv.u8_R2W_FACTOR = (g_eMMCDrv.au8_CSD[13]&0x1C)>>2; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// send CSD (in R2) ++U32 eMMC_CMD9(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_RCA<<16; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 9, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD9 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD9; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD9 Reg.12: %04Xh, Retry fail: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD2 ok, do things here ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CSD); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CSD, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CSD, 9); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_ExtCSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD8(gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_dump_mem(gau8_eMMC_SectorBuf, 0x200); ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((gau8_eMMC_SectorBuf[215]<<24)| ++ (gau8_eMMC_SectorBuf[214]<<16)| ++ (gau8_eMMC_SectorBuf[213]<< 8)| ++ (gau8_eMMC_SectorBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = gau8_eMMC_SectorBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_BUS_WIDTH = gau8_eMMC_SectorBuf[183]; ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[503]&BIT0) // HPI ++ { ++ if(gau8_eMMC_SectorBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ }else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ #else ++ if((gau8_eMMC_SectorBuf[503]&BIT0) && 1==gau8_eMMC_SectorBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(gau8_eMMC_SectorBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ else ++ { ++ eMMC_debug(0,1,"eMMC Warn: not support Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = gau8_eMMC_SectorBuf[181]; ++ ++ if (gau8_eMMC_SectorBuf[224] != 0) ++ { ++ g_eMMCDrv.u32_EraseUnitSize = gau8_eMMC_SectorBuf[224] << 10; ++ } ++ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_CMD8(U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD8_CIFD(pu8_DataBuf); ++ #else ++ return eMMC_CMD8_MIU(pu8_DataBuf); ++ #endif ++} ++ ++// CMD8: send EXT_CSD ++U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_dma_addr; ++ ++ // ------------------------------- ++ #if 0==IF_IP_VERIFY ++ if(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE){ ++ if(0 == eMMC_IF_DDRT_TUNING()) ++ { ++ if(eMMC_DDRT_SET_MAX != g_eMMCDrv.DDRTable.u8_CurSetIdx) ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ } ++ } ++ else{ // SDR Mode ++ //if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ // eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_R_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE, READ_FROM_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ //eMMC_printf("L"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ volatile U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0;; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ //u16_mode |= BIT_SD_DATA_CIFD; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ //eMMC_printf("K"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ //eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 8); ++ ++ // ------------------------------- ++ // CMD8 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetBusSpeed(U8 u8_BusSpeed) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, u8_BusSpeed); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_SPEED_MASK; ++ switch(u8_BusSpeed) ++ { ++ case eMMC_SPEED_HIGH: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_SYNC; ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC set bus HIGH speed\n"); ++ break; ++ case eMMC_SPEED_HS200: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS200; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_SYNC; ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC set bus HS200 speed\n"); ++ break; ++ default: ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC set bus LOW speed\n"); ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR) ++{ ++ U8 u8_value; ++ U32 u32_err; ++ ++ // ------------------------------- ++ switch(u8_BusWidth) ++ { ++ case 1: u8_value=0; break; ++ case 4: u8_value=1; break; ++ case 8: u8_value=2; break; ++ default: return eMMC_ST_ERR_PARAMETER; ++ } ++ ++ if(u8_IfDDR) ++ u8_value |= BIT2; ++ if(BIT2 == u8_value) ++ return eMMC_ST_ERR_PARAMETER; ++ ++ // ------------------------------- ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 183, u8_value); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------- ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ switch(u8_BusWidth) ++ { ++ case 1: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_1; ++ break; ++ case 4: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_4; ++ break; ++ case 8: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_8; ++ break; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"set %u bus width\n", u8_BusWidth); ++ return u32_err; ++} ++ ++U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ U32 u32_arg, u32_err; ++ ++ u32_arg = ((u8_AccessMode&3)<<24) | (u8_ByteIdx<<16) | ++ (u8_Value<<8); ++ ++ u32_err = eMMC_CMD6(u32_arg); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ ++ u32_err = eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++// SWITCH cmd ++U32 eMMC_CMD6(U32 u32_Arg) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_Arg; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 6, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD6; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 6); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_start, 35); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_end, 36); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD38(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ return u32_err; ++} ++ ++U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD38(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ u32_arg = 0x1; ++ else ++ u32_arg = 0x0; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 38, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD38 retry:%u, %Xh \n", ++ u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD38 retry:%u, %Xh \n", ++ u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD38 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD38 check R1 error: %Xh, retry: %u\n", ++ u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 check R1 error: %Xh, retry: %u\n", ++ u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 38); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++// CMD13: send Status ++U32 eMMC_CMD13(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = (u16_RCA<<16) | ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD13)?1:0); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 13, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 13); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD16(U32 u32_BlkLength) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_BlkLength; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 16, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD16; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD16 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 16); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++//------------------------------------------------ ++ ++U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD17_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD17_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_dma_addr; ++ ++ // ------------------------------- ++ #if 0==IF_IP_VERIFY ++ if(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE){ ++ if(0 == eMMC_IF_DDRT_TUNING()) ++ { ++ if(eMMC_DDRT_SET_MAX != g_eMMCDrv.DDRTable.u8_CurSetIdx) ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ } ++ } ++ else{ // SDR Mode ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_R_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE, READ_FROM_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ //eMMC_printf("J"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ #if 0==IF_IP_VERIFY ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ //eMMC_printf("I"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // CMD17 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check reg.12h error: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD12; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check reg.12h error: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 12); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12_NoCheck(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ //eMMC_printf("H"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>9))); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++// enable Reliable Write ++U32 eMMC_CMD23(U16 u16_BlkCnt) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_BlkCnt&0xFFFF; // don't set BIT24 ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ u32_arg |= BIT31; // don't set BIT24 ++ #endif ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 23, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 23); ++ ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt g_eMMCDrv.u16_ReliableWBlkCnt ? ++ g_eMMCDrv.u16_ReliableWBlkCnt : u16_BlkCntTotal; ++ u32_err = eMMC_CMD23(u16_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD23 fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ u16_BlkCnt = u16_BlkCntTotal; ++ #endif ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_W_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u16_BlkCnt); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE*u16_BlkCnt, WRITE_TO_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD25 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD25 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ #ifdef STATIC_RELIABLE_TEST ++ //set watchdog ++ if(enable_pm_sleep_flag == 1) ++ { ++ MDrv_WDT_ClearRstFlag(); ++ MDrv_WDT_SetTimer(1, 60); ++ } ++ #endif ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ ++ #ifdef STATIC_RELIABLE_TEST ++ //cut off power for eMMC ++ if(enable_pm_sleep_flag == 1) ++ { ++ if(reliable_test_sleep>0) ++ udelay(reliable_test_sleep*1000); ++ ++ temp = *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x10*2)*2); ++ temp &= ~BIT4; ++ *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x010*2)*2) =temp; ++ temp = *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x0F*2)*2); ++ temp &= ~BIT4; ++ *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x0F*2)*2) =temp; ++ *(volatile unsigned int *)(0x1f000000+(0x0700*2 + 0x12*2)*2) = 0xBABE; ++ } ++ #endif ++ //eMMC_printf("G"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>7))); ++ ++ #ifdef STATIC_RELIABLE_TEST ++ if(enable_pm_sleep_flag == 1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "write done\n"); ++ } ++ #endif ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ if(g_eMMCDrv.u16_ReliableWBlkCnt) ++ { ++ u32_eMMCBlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt * eMMC_SECTOR_512BYTE; ++ u16_BlkCntTotal -= u16_BlkCnt; ++ if(u16_BlkCntTotal) ++ goto LABEL_RELIABLE_W_START; ++ } ++ #endif ++ ++ LABEL_END: ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ if(eMMC_ST_SUCCESS != u32_err || 0==g_eMMCDrv.u16_ReliableWBlkCnt) ++ #endif ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD24_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ return eMMC_CMD25(u32_eMMCBlkAddr, pu8_DataBuf, 1); ++ #else ++ return eMMC_CMD24_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++ #endif ++} ++ ++U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_dma_addr; ++ ++ // ------------------------------- ++ #if 0==IF_IP_VERIFY ++ if(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE){ ++ if(0 == eMMC_IF_DDRT_TUNING()) ++ { ++ if(eMMC_DDRT_SET_MAX != g_eMMCDrv.DDRTable.u8_CurSetIdx) ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ } ++ } ++ else{ // SDR Mode ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ #endif ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_W_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_dma_addr = eMMC_translate_DMA_address_Ex((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE, WRITE_TO_eMMC); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_dma_addr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_dma_addr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_MIU_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ //eMMC_printf("F"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i, *pu16_dat=(U16*)pu8_DataBuf; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ // ------------------------------- ++ // fill CIFD with data ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ #if 0==IF_IP_VERIFY ++ if(FCIE_DEFAULT_CLK != g_eMMCDrv.u16_ClkRegVal) ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ #endif ++ ++ for(u16_i=0; u16_i<(FCIE_CIFD_BYTE_CNT>>1); u16_i++) ++ REG_FCIE_W(FCIE_CIFD_ADDR(u16_i), pu16_dat[u16_i]); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ //check power cut ++ #if (defined(eMMC_DRV_CEDRIC_LINUX)&&eMMC_DRV_CEDRIC_LINUX) ++ while ((((REG_FCIE(REG_RESET)) & BIT3) == 0) || (((REG_FCIE(REG_BATTERY)) & BIT7) == BIT7)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"Stop for powercut or reset\r\n"); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_100ms); ++ } ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ //eMMC_printf("E"); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_DDRT_TUNING()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CheckR1Error(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ ++ if(g_eMMCDrv.au8_Rsp[1] & (eMMC_ERR_R1_31_24>>24)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_31_24 \n "); ++ u32_err = eMMC_ST_ERR_R1_31_24; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[2] & (eMMC_ERR_R1_23_16>>16)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_23_16 \n "); ++ u32_err = eMMC_ST_ERR_R1_23_16; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[3] & (eMMC_ERR_R1_15_8>>8)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_15_8 \n "); ++ u32_err = eMMC_ST_ERR_R1_15_8; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[4] & (eMMC_ERR_R1_7_0>>0)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_7_0 \n "); ++ u32_err = eMMC_ST_ERR_R1_7_0; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ LABEL_CHECK_R1_END: ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R1_BYTE_CNT); ++ ++ if(24==g_eMMCDrv.au8_Rsp[0] || 25==g_eMMCDrv.au8_Rsp[0] || ++ 18==g_eMMCDrv.au8_Rsp[0] || 12==g_eMMCDrv.au8_Rsp[0]) ++ eMMC_FCIE_ErrHandler_ReInit(); ++ } ++ return u32_err; ++} ++ ++ ++// ==================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define UPFW_SEC_WIAT_CNT 0x1000000 ++#define UPFW_SEC_BYTE_CNT (128*1024) ++static U32 eMMC_UpFW_Samsung_Wait(void) ++{ ++ U32 u32_err, u32_cnt, u32_st; ++ ++ for(u32_cnt=0; u32_cnt>eMMC_SECTOR_512BYTE_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: write fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 3, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ // --------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"close ... \n"); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, 0, 28, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD28 fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 4, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ LABEL_END_OF_UPFW: ++ return u32_err; ++ ++} ++#endif // eMMC_UPDATE_FIRMWARE ++#endif ++ +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_ip_verify.c b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_ip_verify.c +new file mode 100644 +index 00000000..14802983 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_ip_verify.c +@@ -0,0 +1,1007 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined (UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++ ++//============================================================= ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ ++#define DDR_TEST_BLK_CNT 8 ++#define DDR_TEST_BUFFER_SIZE (eMMC_SECTOR_512BYTE*DDR_TEST_BLK_CNT) ++ ++eMMC_ALIGN0 static U8 gau8_WBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++eMMC_ALIGN0 static U8 gau8_RBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++ ++U32 eMMCTest_BlkWRC_ProbeDDR(U32 u32_eMMC_Addr) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf_DDR, *pu32_R=(U32*)gau8_RBuf_DDR; ++ U32 u32_BlkCnt=eMMC_TEST_BLK_CNT, u32_BufByteCnt; ++ ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ u32_BufByteCnt = u32_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_R[u32_i] = 0; ++ ++ for(u32_j=0; u32_j<9; u32_j++) ++ { ++ // init data pattern ++ switch(u32_j) ++ { ++ case 0: // increase ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = u32_i+1; ++ break; ++ case 1: // decrease ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = 0-(u32_i+1); // more FF, more chance to lose start bit ++ break; ++ #else ++ continue; ++ #endif ++ case 2: // 0xF00F ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xF00FF00F; ++ break; ++ case 3: // 0xFF00 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFF00FF00; ++ break; ++ case 4: // 0x5AA5 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5AA55AA5; ++ break; ++ case 5: // 0x55AA ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x55AA55AA; ++ break; ++ case 6: // 0x5A5A ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5A5A5A5A; ++ break; ++ #else ++ continue; ++ #endif ++ case 7: // 0x0000 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x00000000; ++ break; ++ case 8: // 0xFFFF ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFFFFFFFF; ++ break; ++ ++ } ++ ++ #if 0 ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.single, %Xh \n", u32_err); ++ break; ++ } ++ #endif ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMC_Addr, gau8_WBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD18_MIU(u32_eMMC_Addr, gau8_RBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, u32_BufByteCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.multi %Xh \n", u32_err); ++ break; ++ } ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_debug(0,0,"data pattern %u: %02X%02X%02X%02Xh \n\n", ++ u32_j, gau8_WBuf_DDR[3], gau8_WBuf_DDR[2], gau8_WBuf_DDR[1], gau8_WBuf_DDR[0]); ++ } ++ ++ return u32_err; ++} ++ ++ ++// can use for RF team test ++U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, u32_k; ++ U32 u32_BlkCnt, u32_eMMC_Addr; ++ ++ u32_eMMC_Addr = eMMC_TEST_BLK_0; ++ ++ u32_BlkCnt = eMMC_TEST_BLK_CNT; ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ ++ if(8 != u32_BlkCnt) ++ { ++ eMMC_debug(0,1,"Blk count needs to be 8 \n"); ++ while(1); ++ } ++ ++ for(u32_j=0; u32_j>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u32_err = eMMC_CMD24_CIFD(u32_eMMC_Addr, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_CIFD(u32_eMMC_Addr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, FCIE_CIFD_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++extern U32 gu32_DMAAddr; ++U32 eMMCTest_SingleBlkWRC_MIU(U32 u32_eMMC_Addr, U32 u32_DataPattern) ++{ ++ U32 u32_err; ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, FCIE_CIFD_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMCTest_MultiBlkWRC_MIU(U32 u32_eMMC_Addr, U16 u16_BlkCnt, U32 u32_DataPattern) ++{ ++ U32 u32_err; ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ U16 u16_BlkCnt_tmp; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u16_BlkCnt_tmp = TEST_BUFFER_SIZE >> eMMC_SECTOR_512BYTE_BITS; ++ u16_BlkCnt_tmp = u16_BlkCnt_tmp > u16_BlkCnt ? u16_BlkCnt : u16_BlkCnt_tmp; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS; ++ #if IF_eMMC_BOOT_MODE_STG2 ++ au32_Addr[1] = (U32)gau8_BootImage1; ++ au32_SectorCnt[1] = sizeof(gau8_BootImage1)>>eMMC_SECTOR_512BYTE_BITS; ++ au32_Addr[2] = (U32)gau8_BootImage2; ++ au32_SectorCnt[2] = sizeof(gau8_BootImage2)>>eMMC_SECTOR_512BYTE_BITS; ++ #endif ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 1); ++ #else ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 3); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, eMMC_LoadImages: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ //eMMC_debug(0,1,"ChkSum -: %Xh \n", eMMC_ChkSum((U8*)au32_Addr, sizeof(gau8_BootImageOri))); ++ eMMC_debug(0,1,"ChkSum -: %Xh, Addr: %Xh \n", eMMC_ChkSum((U8*)au32_Addr[0], 0xC1< u32_t1) ++ while(0==(u32_t0-eMMC_hw_timer_tick())/eMMC_HW_TIMER_MHZ) ++ ; ++ else ++ while(0==(eMMC_hw_timer_tick()-u32_t0)/eMMC_HW_TIMER_MHZ) ++ ; ++ #endif ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,".\n"); ++} ++ ++U32 eMMC_IPVerify_Performance(void) ++{ ++ volatile U32 u32_err, u32_i, u32_SectorAddr=0, u32_SectorCnt=0, u32_t0, u32_t1, u32_t; ++ U8 u8_IfDDRTest=0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"SectorBuf:%Xh, RBuf:%Xh, WBuf:%Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_Init ok] \n"); ++ ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == g_eMMCDrv.DDRTable.u8_SetCnt){ ++ eMMC_FCIE_BuildDDRTimingTable(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: BuildDDRTimingTable fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ }else ++ eMMC_DumpDDRTTable(); ++ #endif ++ ++ eMMCTest_DownCount(eMMC_SPEED_TEST_COUNTDOWN); ++ for(u32_i=0; u32_i>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_W); ++ ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_W; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ //eMMC_debug(0,0,"%08Xh \n", u32_SectorAddr+u32_i); ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ u32_err = eMMC_CMD24(u32_SectorAddr, gau8_WBuf); ++ #else ++ u32_err = eMMC_CMD24_MIU(u32_SectorAddr, gau8_WBuf); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u KB/sec \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_W<>10)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_SINGLE_BLKCNT_W<>10)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Single Read, total: %uKB, %u blocks\n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R)<>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_R); ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_R; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ u32_err = eMMC_CMD17_MIU(u32_SectorAddr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u KB/sec \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R<>10)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_SINGLE_BLKCNT_R<>10)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Write, total: %uMB, %u blocks\n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20, ++ eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W); ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ u32_SectorCnt = ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS) > eMMC_TEST_BLK_CNT ? ++ eMMC_TEST_BLK_CNT : (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS); ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u MB/sec \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Read, total: %uMB, %u blocks\n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20, ++ eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R); ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ u32_SectorCnt = ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS) > eMMC_TEST_BLK_CNT ? ++ eMMC_TEST_BLK_CNT : (TEST_BUFFER_SIZE>>eMMC_SECTOR_512BYTE_BITS); ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : u32_t0-u32_t1; ++ if(u32_t > (U32)u32_t*10) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: timer overflow \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0," %u.%u MB/sec \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20)*100/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)), ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20)*1000/ ++ (u32_t*10/(eMMC_HW_TIMER_MHZ/10)))%10); ++ ++ if(u8_IfDDRTest) ++ return eMMC_ST_SUCCESS; ++ ++ // =============================================== ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"DDR\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"======================================\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ ++ u8_IfDDRTest = 1; ++ goto LABEL_TEST_START; ++ #endif ++ ++ return u32_err; ++ ++} ++ ++ ++U32 eMMC_IPVerify_Main(void) ++{ ++ U32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC_IPVerify_Main\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"%Xh %Xh %Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ #if 0 ++ eMMC_BootMode(); ++ //while(1); ++ return 0; ++ #endif ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_Init ok] \n"); ++ ++ // =============================================== ++ #if 0 ++ eMMC_debug(0,1,"BootImage ByteCnt: %Xh, ChkSum:%Xh\n", ++ sizeof(gau8_BootImageOri), eMMC_ChkSum(gau8_BootImageOri, sizeof(gau8_BootImageOri))); ++ ++ u32_err = eMMC_WriteBootPart(gau8_BootImageOri, sizeof(gau8_BootImageOri), 0, 1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_WriteBootPart fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "[eMMC_WriteBootPart ok] \n"); ++ ++ while(1); ++ #endif ++ ++ // =============================================== ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal pattern test ok\n\n"); ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "specific pattern test ok\n\n"); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_IPVerify_Main_Ex(U32 u32_DataPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ //eMMC_debug(0,1,"Total Sec: %Xh, StartSec: %Xh, SecCnt: %Xh \n", ++ // g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ ++ #if 1 ++ if(0==(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ u32_err = eMMCTest_SingleBlkWRC_RIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_RIU fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_RIU ok] \n");} ++ #endif ++ #if 1 ++ u32_err = eMMCTest_SingleBlkWRC_MIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMCTest_MultiBlkWRC_MIU(u32_StartSector, u32_SectorCnt, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_MultiBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_MultiBlkWRC_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++ ++U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void) ++{ ++ U32 u32_err; ++ U8 u8_SDRClkIdx, u8_DDRClkIdx; ++ ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == g_eMMCDrv.DDRTable.u8_SetCnt){ ++ eMMC_FCIE_BuildDDRTimingTable(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: BuildDDRTimingTable fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ }else ++ eMMC_DumpDDRTTable(); ++ #endif ++ ++ u8_SDRClkIdx = 0; ++ u8_DDRClkIdx = 0; ++ ++ while(1) ++ { ++ #if 1 ++ //eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"SDR\n"); ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ //if(0==u8_SDRClkIdx) u8_SDRClkIdx++; // skip 48MHz ++ eMMC_clock_setting(gau8_FCIEClkSel[u8_SDRClkIdx]); ++ u8_SDRClkIdx++; ++ //u8_SDRClkIdx = u8_SDRClkIdx%(eMMC_FCIE_VALID_CLK_CNT-1);// skip 300KHz ++ u8_SDRClkIdx = u8_SDRClkIdx%eMMC_FCIE_VALID_CLK_CNT; ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ #endif ++ ++ #if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ //eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"DDR\n"); ++ ++ u32_err = eMMC_FCIE_EnableDDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableDDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ #if 1 ++ eMMC_FCIE_ApplyDDRTSet(u8_DDRClkIdx); ++ u8_DDRClkIdx++; ++ u8_DDRClkIdx = u8_DDRClkIdx%g_eMMCDrv.DDRTable.u8_SetCnt; ++ #endif ++ #if 0 ++ do{ // skip 42.6MHz ++ u8_DDRClkIdx++; ++ u8_DDRClkIdx = u8_DDRClkIdx%g_eMMCDrv.DDRTable.u8_SetCnt; ++ eMMC_FCIE_ApplyDDRTSet(u8_DDRClkIdx); ++ }while(BIT_FCIE_CLK_42_6M == g_eMMCDrv.DDRTable.Set[u8_DDRClkIdx].u8_Clk); ++ #endif ++ #if 0 ++ eMMC_FCIE_ApplyDDRTSet(1); ++ #endif ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ #endif ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++#endif +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_utl.c b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_utl.c +new file mode 100644 +index 00000000..f048fb37 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/src/common/eMMC_utl.c +@@ -0,0 +1,342 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//-------------------------------------------------------------------------- ++static eMMC_ALIGN0 eMMC_TEST_ALIGN_PACK_t g_eMMCTestAlignPack_t eMMC_ALIGN1; ++U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt) ++{ ++ // check alignment ++ if((U32)&(g_eMMCTestAlignPack_t.u8_0) & (u8_AlignByteCnt-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not aliged. expect %Xh but %Xh \n", ++ u8_AlignByteCnt, (U32)&(g_eMMCTestAlignPack_t.u8_0)); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_ALIGN; ++ } ++ // check packed - 0 ++ if((U32)&(g_eMMCTestAlignPack_t.u16_0)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 1 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_0)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 3 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_1)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 7) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not packed. check err.0 \n"); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_PACKED; ++ } ++ // check packed - 1 ++ if((U32)&(g_eMMCTestAlignPack_t.u16_0)-(U32)&(g_eMMCTestAlignPack_t.u8_0) != 1 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_0)-(U32)&(g_eMMCTestAlignPack_t.u16_0)!= 2 || ++ (U32)&(g_eMMCTestAlignPack_t.u32_1)-(U32)&(g_eMMCTestAlignPack_t.u32_0)!= 4) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not packed. check err.1 \n"); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_PACKED; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "ok\n"); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static __inline void dump_mem_line(unsigned char *buf, int cnt) ++{ ++ int i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " 0x%08X: ", (U32)buf); ++ for (i= 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%02Xh ", buf[i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " | "); ++ ++ for (i = 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%c", (buf[i] >= 32 && buf[i] < 128) ? buf[i] : '.'); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "\n"); ++} ++ ++void eMMC_dump_mem(unsigned char *buf, int cnt) ++{ ++ int i; ++ ++ for (i= 0; i < cnt; i+= 16) ++ dump_mem_line(buf + i, 16); ++} ++ ++ ++U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt) ++{ ++ U32 u32_i, u32_offset; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS)<>11); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "eMMC BUS_WIDTH: %Xh\n", g_eMMCDrv.u8_BUS_WIDTH); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TRIM: %Xh\n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_TRIM)?1:0); ++ ++ if(g_eMMCDrv.u32_eMMCFlag & (eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13)) ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: CMD%u \n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_HPI_CMD12)?12:13); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: 0 \n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"Reliable Write BlkCnt: %Xh\n", g_eMMCDrv.u16_ReliableWBlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ // ------------------------------ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(0, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CSD:\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CSD[0], eMMC_MAX_RSP_BYTE_CNT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "SPEC_VERS: %Xh, R_BL_LEN: %Xh, W_BL_LEN: %Xh \n", ++ g_eMMCDrv.u8_SPEC_VERS, g_eMMCDrv.u8_R_BL_LEN, g_eMMCDrv.u8_W_BL_LEN); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "Access Mode: %s\n", g_eMMCDrv.u8_IfSectorMode?"Sector":"Byte"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "C_SIZE: %Xh\n", g_eMMCDrv.u16_C_SIZE); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "ERASE_GRP_SIZE: %Xh, ERASE_GRP_MULT: %Xh\n", ++ g_eMMCDrv.u8_ERASE_GRP_SIZE, g_eMMCDrv.u8_ERASE_GRP_MULT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "EraseUnitSize: %u\n", g_eMMCDrv.u32_EraseUnitSize); ++ switch(g_eMMCDrv.u8_Tran_Speed) ++ { ++ case 0x2A: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 20MHz\n"); break; ++ case 0x32: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 26MHz\n"); break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal TRAN_SPEED: %Xh\n", g_eMMCDrv.u8_Tran_Speed); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TAAC: %Xh, NSAC: %Xh, R2W_FACTOR: %Xh\n", ++ g_eMMCDrv.u8_TAAC, g_eMMCDrv.u8_NSAC, g_eMMCDrv.u8_R2W_FACTOR); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "RCA: %Xh\n", g_eMMCDrv.u16_RCA); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CID:\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CID[0], eMMC_MAX_RSP_BYTE_CNT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ return u32_err; ++} ++ ++ ++void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ int i; ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC NNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "peMMCInfo: 0x%08X\n", (U32)peMMCInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_Tag : ["); ++ for (i = 0; i < 16; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%c", peMMCInfo->au8_Tag[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_IDByteCnt : 0x%04x\n", peMMCInfo->u8_IDByteCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_ID : 0x[ "); ++ for (i = 0; i < peMMCInfo->u8_IDByteCnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%02X ", peMMCInfo->au8_ID[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", peMMCInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", peMMCInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", peMMCInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", peMMCInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", peMMCInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_Config : 0x%08X\n", peMMCInfo->u32_Config); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_ECCType : 0x%04x\n", peMMCInfo->u16_ECCType); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SeqAccessTime: 0x%04x\n", peMMCInfo->u16_SeqAccessTime); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_Vendor: %s\n", peMMCInfo->au8_Vendor); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PartNumber: %s\n", peMMCInfo->au8_PartNumber); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapLoc: 0x%04x\n", peMMCInfo->u8_PairPageMapLoc); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapType: 0x%04x\n", peMMCInfo->u8_PairPageMapType); ++#endif ++} ++ ++void eMMC_dump_pni(eMMC_PNI_t *pPartInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC PNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "pPartInfo: 0x%08X\n", (U32)pPartInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", pPartInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PartCnt : 0x%04x\n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_UnitByteCnt : 0x%04x\n", pPartInfo->u16_UnitByteCnt); ++ ++ //dump_part_records(pPartInfo->records, pPartInfo->u16_PartCnt); ++#endif ++} ++ ++#endif +diff --git a/drivers/mstar/emmc/chicago/eMMCDrv/src/config/eMMC_platform.c b/drivers/mstar/emmc/chicago/eMMCDrv/src/config/eMMC_platform.c +new file mode 100644 +index 00000000..f9f2038b +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/eMMCDrv/src/config/eMMC_platform.c +@@ -0,0 +1,6554 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++#define DDR_TEST_BLK_CNT 8 ++#define DDR_TEST_BUFFER_SIZE (eMMC_SECTOR_512BYTE*DDR_TEST_BLK_CNT) ++ ++eMMC_ALIGN0 static U8 gau8_WBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++eMMC_ALIGN0 static U8 gau8_RBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++ ++U32 eMMCTest_BlkWRC_ProbeDDR(U32 u32_eMMC_Addr) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf_DDR, *pu32_R=(U32*)gau8_RBuf_DDR; ++ U32 u32_BlkCnt=eMMC_TEST_BLK_CNT, u32_BufByteCnt; ++ ++ //eMMC_printf("eMMCTest_BlkWRC_ProbeDDR\r\n"); ++ ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ u32_BufByteCnt = u32_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_R[u32_i] = 0; ++ ++ for(u32_j=0; u32_j<9; u32_j++) ++ { ++ // init data pattern ++ switch(u32_j) ++ { ++ case 0: // increase ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = u32_i+1; ++ break; ++ case 1: // decrease ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = 0-(u32_i+1); // more FF, more chance to lose start bit ++ break; ++ #else ++ continue; ++ #endif ++ case 2: // 0xF00F ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xF00FF00F; ++ break; ++ case 3: // 0xFF00 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFF00FF00; ++ break; ++ case 4: // 0x5AA5 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5AA55AA5; ++ break; ++ case 5: // 0x55AA ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x55AA55AA; ++ break; ++ case 6: // 0x5A5A ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5A5A5A5A; ++ break; ++ #else ++ continue; ++ #endif ++ case 7: // 0x0000 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x00000000; ++ break; ++ case 8: // 0xFFFF ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFFFFFFFF; ++ break; ++ ++ } ++ ++ #if 0 ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.single, %Xh \n", u32_err); ++ break; ++ } ++ #endif ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMC_Addr, gau8_WBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD18_MIU(u32_eMMC_Addr, gau8_RBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, u32_BufByteCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.multi %Xh \n", u32_err); ++ break; ++ } ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_debug(0,0,"data pattern %u: %02X%02X%02X%02Xh \n\n", ++ u32_j, gau8_WBuf_DDR[3], gau8_WBuf_DDR[2], gau8_WBuf_DDR[1], gau8_WBuf_DDR[0]); ++ } ++ ++ return u32_err; ++} ++ ++void eMMC_Prepare_Power_Saving_Mode_Queue(void) ++{ ++ #if (defined(eMMC_DRV_CHICAGO_LINUX) && eMMC_DRV_CHICAGO_LINUX) ++ REG_FCIE_SETBIT(REG_BATTERY, reg_nobat_int_en); ++ ++ /* (1) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x40), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x41), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (2) Clear All Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x42), 0xffff); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x43), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (3) Clear SDE MODE Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x44), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x45), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (4) Clear SDE CTL Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x46), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x47), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (5) Reset Start */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x48), 0x4800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x49), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (6) Reset End */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4A), 0x5800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (7) Set "SD_MOD" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4C), 0x0051); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (8) Enable "csreg_sd_en" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4E), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (9) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x50), 0x0040); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x51), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x00); ++ ++ /* (10) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x52), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x53), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x01); ++ ++ /* (11) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x54), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x55), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x02); ++ ++ /* (12) Command Size */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x56), 0x0005); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x57), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0E); ++ ++ /* (13) Response Size */ ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x58), 0x0000); ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x59), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0D); ++ ++ /* (14) Enable Interrupt, SD_CMD_END */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5A), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x01); ++ ++ /* (15) Command Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5C), 0x0004); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (16) Wait Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5E), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WINT); ++ ++ /* (17) Clear Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x60), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x61), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (18) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x62), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x63), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (19) STOP */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x64), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x65), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_STOP); ++ ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, BIT_POWER_SAVE_MODE_EN | BIT_SD_POWER_SAVE_RST); ++ #endif ++} ++ ++ ++//============================================================= ++#if (defined(eMMC_DRV_G2P_ROM)&&eMMC_DRV_G2P_ROM) ++//============================================================= ++#elif (defined(eMMC_DRV_EAGLE_LINUX)&&eMMC_DRV_EAGLE_LINUX) // [FIXME] clone for your flatform ++// [FIXME] --> ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ // TIMER_FREERUN_32K 32 KHz ++ // TIMER_FREERUN_XTAL 38.4 MHz, ++ // counting down ++ return 0;//HalTimerRead(TIMER_FREERUN_32K); ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 1, "FCIE 1X (0x%X):0x%X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 1, "FCIE 4X (0x%X):0x%X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 1, "CMU (0x%X):0x%X\n", reg_ckg_CMU, REG_FCIE_U16(reg_ckg_CMU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ eMMC_debug(0, 1, "chiptop_0x5A (0x%X):0x%X\n", reg_chiptop_0x5A, REG_FCIE_U16(reg_chiptop_0x5A)); ++ eMMC_debug(0, 1, "chiptop_0x1F (0x%X):0x%X\n", reg_chiptop_0x1F, REG_FCIE_U16(reg_chiptop_0x1F)); ++ eMMC_debug(0, 1, "chiptop_0x70 (0x%X):0x%X\n", reg_chiptop_0x70, REG_FCIE_U16(reg_chiptop_0x70)); ++ eMMC_debug(0, 1, "chiptop_0x64 (0x%X):0x%X\n", reg_chiptop_0x64, REG_FCIE_U16(reg_chiptop_0x64)); ++ eMMC_debug(0, 1, "chiptop_0x4F (0x%X):0x%X\n", reg_chiptop_0x4F, REG_FCIE_U16(reg_chiptop_0x4F)); ++ eMMC_debug(0, 1, "chiptop_0x03 (0x%X):0x%X\n", reg_chiptop_0x03, REG_FCIE_U16(reg_chiptop_0x03)); ++ eMMC_debug(0, 1, "chiptop_0x51 (0x%X):0x%X\n", reg_chiptop_0x51, REG_FCIE_U16(reg_chiptop_0x51)); ++ eMMC_debug(0, 1, "chiptop_0x6F (0x%X):0x%X\n\n", reg_chiptop_0x6F, REG_FCIE_U16(reg_chiptop_0x6F)); ++ ++ eMMC_debug(0, 1, "chiptop_0x43 (0x%X):0x%X\n", reg_chiptop_0x43, REG_FCIE_U16(reg_chiptop_0x43)); ++ eMMC_debug(0, 1, "chiptop_0x50 (0x%X):0x%X\n", reg_chiptop_0x50, REG_FCIE_U16(reg_chiptop_0x50)); ++ eMMC_debug(0, 1, "chiptop_0x0B (0x%X):0x%X\n", reg_chiptop_0x0B, REG_FCIE_U16(reg_chiptop_0x0B)); ++ eMMC_debug(0, 1, "chiptop_0x5D (0x%X):0x%X\n", reg_chiptop_0x5D, REG_FCIE_U16(reg_chiptop_0x5D)); ++ ++ eMMC_debug(0, 1, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, ++ BIT_MACRO_EN|BIT_SD_DDR_EN|BIT_SD_BYPASS_MODE_EN|BIT_SD_SDR_IN_BYPASS|BIT_SD_FROM_TMUX); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC pads: DDR\n"); ++ ++ REG_FCIE_SETBIT(reg_chiptop_0x43, ++ BIT_PAD_EMMC_CLK_SRC|BIT_eMMC_RSTPIN_VAL); ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, ++ BIT_EMPTY|BIT_eMMC_RSTPIN_EN|BIT_PAD_BYPASS_MACRO); ++ ++ // set DDR mode ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_MACRO_EN|BIT_SD_DDR_EN); ++ // set chiptop ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC pads: SDR\n"); ++ ++ REG_FCIE_SETBIT(reg_chiptop_0x43, ++ BIT_PAD_EMMC_CLK_SRC|BIT_eMMC_RSTPIN_VAL); ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, ++ BIT_EMPTY|BIT_eMMC_RSTPIN_EN|BIT_PAD_BYPASS_MACRO); ++ ++ // set SDR mode ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_MACRO_EN); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC pads: BYPASS\n"); ++ ++ REG_FCIE_SETBIT(reg_chiptop_0x43, ++ BIT_PAD_EMMC_CLK_SRC|BIT_eMMC_RSTPIN_VAL|BIT_PAD_BYPASS_MACRO); ++ REG_FCIE_CLRBIT(reg_chiptop_0x43, ++ BIT_EMPTY|BIT_eMMC_RSTPIN_EN); ++ ++ // set bypadd mode ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, ++ BIT_MACRO_EN|BIT_SD_BYPASS_MODE_EN|BIT_SD_SDR_IN_BYPASS); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ #if 0 ++ REG_FCIE_CLRBIT(reg_chiptop_0x5A, BIT0|BIT1|BIT2); ++ //REG_FCIE_CLRBIT(reg_chiptop_0x1F, BIT0|BIT1); // don't touch for card-detect ++ //REG_FCIE_CLRBIT(reg_chiptop_0x70, BIT2); // don't touch for card-detect ++ REG_FCIE_CLRBIT(reg_chiptop_0x64, BIT0); ++ REG_FCIE_CLRBIT(reg_chiptop_0x4F, BIT13|BIT14); ++ REG_FCIE_CLRBIT(reg_chiptop_0x03, BIT6|BIT7); ++ //REG_FCIE_CLRBIT(reg_chiptop_0x51, BIT10|BIT11); //Cause EAGLE CI card lag issue. ++ REG_FCIE_CLRBIT(reg_chiptop_0x6F, BIT14|BIT15); ++ #endif ++ ++ REG_FCIE_CLRBIT(reg_chiptop_0x50, BIT_NAND_CS1_EN|BIT_ALL_PAD_IN); ++ REG_FCIE_CLRBIT(reg_chiptop_0x0B, BIT_NAND_CS2_EN|BIT_NAND_CS3_EN| ++ BIT_SD0_CFG|BIT_SD0_CFG2|BIT_SD1_CFG|BIT_SD1_CFG2|BIT_NAND_CFG); ++ ++ REG_FCIE_SETBIT(FCIE_REG_2Dh, BIT_NEW_DESIGN_ENn); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{0, BIT_FCIE_CLK4X_20M, BIT_FCIE_CLK4X_27M, 0, ++ BIT_FCIE_CLK4X_36M, BIT_FCIE_CLK4X_40M, 0, 0, ++ 0, 0, 0, 0, ++ 0, 0, 0, BIT_FCIE_CLK4X_48M}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid clk: %Xh\n", u16_ClkParam); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx=0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 3 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 3) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp); ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#if 0 ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++#endif ++ ++#include "chip_int.h" ++#include "chip_setup.h" ++#if defined(CONFIG_ARM) // ARM: AMBER3, AGATE ++#include ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ #if 0 ++ U32 dmaaddr; ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ #else ++ extern void ___dma_single_cpu_to_dev(const void *kaddr, size_t size, enum dma_data_direction dir); ++ ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ else ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++ #endif ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eagle SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++//--------------------------------------- ++ ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ // Temp patch for someone driver overwrite the register ++ // The patch for SD card SD_CDZ issue (Eagle). ++ REG_FCIE_SETBIT(reg_chiptop_0x1F, BIT0); ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ //eMMC_clock_setting(FCIE_SLOW_CLK); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #else ++ // as usual ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ // Reset PIU Timer1 ++ REG_FCIE_W(TIMER1_MAX_LOW, 0xFFFF); ++ REG_FCIE_W(TIMER1_MAX_HIGH, 0xFFFF); ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ // Start PIU Timer1 ++ REG_FCIE_W(TIMER1_ENABLE, 0x1); ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ U32 u32HWTimer = 0; ++ U32 u32TimerLow = 0; ++ U32 u32TimerHigh = 0; ++ ++ // Get timer value ++ u32TimerLow = REG_FCIE(TIMER1_CAP_LOW); ++ u32TimerHigh = REG_FCIE(TIMER1_CAP_HIGH); ++ ++ u32HWTimer = (u32TimerHigh<<16) | u32TimerLow; ++ ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ return u32HWTimer; ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 0, "FCIE 1X (0x%X):0x%04X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 0, "FCIE 4X (0x%X):0x%04X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 0, "MIU (0x%X):0x%04X\n", reg_ckg_MIU, REG_FCIE_U16(reg_ckg_MIU)); ++ eMMC_debug(0, 0, "MCU (0x%X):0x%04X\n", reg_ckg_MCU, REG_FCIE_U16(reg_ckg_MCU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ ++ eMMC_debug(0, 0, "reg_all_pad_in (0x%08X):0x%04X\n", reg_all_pad_in, REG_FCIE_U16(reg_all_pad_in)); ++ ++ eMMC_debug(0, 0, "reg_emmc_pad (0x%08X):0x%04X\n", reg_emmc_pad, REG_FCIE_U16(reg_emmc_pad)); ++ eMMC_debug(0, 0, "reg_pcm_d_pe (0x%08X):0x%04X\n", reg_pcm_d_pe, REG_FCIE_U16(reg_pcm_d_pe)); ++ eMMC_debug(0, 0, "reg_pcm_a_pe (0x%08X):0x%04X\n", reg_pcm_a_pe, REG_FCIE_U16(reg_pcm_a_pe)); ++ eMMC_debug(0, 0, "reg_pcm2_cd_n_pe (0x%08X):0x%04X\n", reg_pcm2_cd_n_pe, REG_FCIE_U16(reg_pcm2_cd_n_pe)); ++ ++ eMMC_debug(0, 0, "reg_sd_use_bypass (0x%08X):0x%04X\n", reg_sd_use_bypass, REG_FCIE_U16(reg_sd_use_bypass)); ++ eMMC_debug(0, 0, "reg_fcie2macro_sd_bypass (0x%08X):0x%04X\n", reg_fcie2macro_sd_bypass, REG_FCIE_U16(reg_fcie2macro_sd_bypass)); ++ ++ eMMC_debug(0, 0, "reg_pcmcia_pad (0x%08X):0x%04X\n", reg_pcmcia_pad, REG_FCIE_U16(reg_pcmcia_pad)); ++ eMMC_debug(0, 0, "reg_nand_pad (0x%08X):0x%04X\n", reg_nand_pad, REG_FCIE_U16(reg_nand_pad)); ++ eMMC_debug(0, 0, "reg_sd_pad (0x%08X):0x%04X\n", reg_sd_pad, REG_FCIE_U16(reg_sd_pad)); ++ ++ eMMC_debug(0, 0, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT8|BIT9|BIT10|BIT11|BIT12); ++ REG_FCIE_SETBIT(reg_pcm_d_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm_a_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm2_cd_n_pe, BIT1); // reg_pcm_pe ++ REG_FCIE_CLRBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(reg_sd_use_bypass, BIT0); // reg_sd_use_bypass ++ ++ REG_FCIE_SETBIT(reg_emmc_drv, 0x0007); ++ REG_FCIE_SETBIT(reg_nand_drv, 0xFF00); ++ REG_FCIE_SETBIT(reg_nand_ps, 0xFFFF); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: DDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT9); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: SDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: BYPASS\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT10|BIT11); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ case FCIE_eMMC_TMUX: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: TMUX\n"); ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT10|BIT12); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_TMUX; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ ++ REG_FCIE_CLRBIT(reg_pcmcia_pad, BIT0|BIT4); ++ REG_FCIE_CLRBIT(reg_nand_pad, BIT5|BIT6|BIT7); ++ REG_FCIE_CLRBIT(reg_sd_pad, BIT8|BIT9|BIT10|BIT11); ++ ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT15); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{ ++ 0, ++ BIT_FCIE_CLK4X_20M, ++ BIT_FCIE_CLK4X_27M, ++ 0, ++ BIT_FCIE_CLK4X_36M, ++ BIT_FCIE_CLK4X_40M, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ BIT_FCIE_CLK4X_48M ++}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx = 0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 7 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 7) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ U32 dmaaddr; ++ ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++#if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++#endif ++ ++ return IRQ_NONE; ++ ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ #endif ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eagle SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++ ++//--------------------------------------- ++ ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ // Reset PIU Timer1 ++ REG_FCIE_W(TIMER1_MAX_LOW, 0xFFFF); ++ REG_FCIE_W(TIMER1_MAX_HIGH, 0xFFFF); ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ // Start PIU Timer1 ++ REG_FCIE_W(TIMER1_ENABLE, 0x1); ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ U32 u32HWTimer = 0; ++ U32 u32TimerLow = 0; ++ U32 u32TimerHigh = 0; ++ ++ // Get timer value ++ u32TimerLow = REG_FCIE(TIMER1_CAP_LOW); ++ u32TimerHigh = REG_FCIE(TIMER1_CAP_HIGH); ++ ++ u32HWTimer = (u32TimerHigh<<16) | u32TimerLow; ++ ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ return u32HWTimer; ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 0, "FCIE 1X (0x%X):0x%04X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 0, "FCIE 4X (0x%X):0x%04X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 0, "MIU (0x%X):0x%04X\n", reg_ckg_MIU, REG_FCIE_U16(reg_ckg_MIU)); ++ eMMC_debug(0, 0, "MCU (0x%X):0x%04X\n", reg_ckg_MCU, REG_FCIE_U16(reg_ckg_MCU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ ++ eMMC_debug(0, 0, "reg_all_pad_in (0x%08X):0x%04X\n", reg_all_pad_in, REG_FCIE_U16(reg_all_pad_in)); ++ ++ eMMC_debug(0, 0, "reg_emmc_pad (0x%08X):0x%04X\n", reg_emmc_pad, REG_FCIE_U16(reg_emmc_pad)); ++ eMMC_debug(0, 0, "reg_pcm_d_pe (0x%08X):0x%04X\n", reg_pcm_d_pe, REG_FCIE_U16(reg_pcm_d_pe)); ++ eMMC_debug(0, 0, "reg_pcm_a_pe (0x%08X):0x%04X\n", reg_pcm_a_pe, REG_FCIE_U16(reg_pcm_a_pe)); ++ eMMC_debug(0, 0, "reg_pcm2_cd_n_pe (0x%08X):0x%04X\n", reg_pcm2_cd_n_pe, REG_FCIE_U16(reg_pcm2_cd_n_pe)); ++ ++ eMMC_debug(0, 0, "reg_sd_use_bypass (0x%08X):0x%04X\n", reg_sd_use_bypass, REG_FCIE_U16(reg_sd_use_bypass)); ++ eMMC_debug(0, 0, "reg_fcie2macro_sd_bypass (0x%08X):0x%04X\n", reg_fcie2macro_sd_bypass, REG_FCIE_U16(reg_fcie2macro_sd_bypass)); ++ ++ eMMC_debug(0, 0, "reg_pcmcia_pad (0x%08X):0x%04X\n", reg_pcmcia_pad, REG_FCIE_U16(reg_pcmcia_pad)); ++ eMMC_debug(0, 0, "reg_nand_pad (0x%08X):0x%04X\n", reg_nand_pad, REG_FCIE_U16(reg_nand_pad)); ++ eMMC_debug(0, 0, "reg_sd_pad (0x%08X):0x%04X\n", reg_sd_pad, REG_FCIE_U16(reg_sd_pad)); ++ ++ eMMC_debug(0, 0, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT8|BIT9|BIT10|BIT11|BIT12); ++ REG_FCIE_SETBIT(reg_pcm_d_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm_a_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm2_cd_n_pe, BIT1); // reg_pcm_pe ++ REG_FCIE_CLRBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(reg_sd_use_bypass, BIT0); // reg_sd_use_bypass ++ ++ REG_FCIE_SETBIT(reg_emmc_drv, 0x0007); ++ REG_FCIE_SETBIT(reg_nand_drv, 0xFF00); ++ REG_FCIE_SETBIT(reg_nand_ps, 0xFFFF); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: DDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT9); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: SDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: BYPASS\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT10|BIT11); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ case FCIE_eMMC_TMUX: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: TMUX\n"); ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT10|BIT12); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_TMUX; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ ++ REG_FCIE_CLRBIT(reg_pcmcia_pad, BIT0|BIT4); ++ REG_FCIE_CLRBIT(reg_nand_pad, BIT5|BIT6|BIT7); ++ REG_FCIE_CLRBIT(reg_sd_pad, BIT8|BIT9|BIT10|BIT11); ++ ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT15); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{ ++ 0, ++ BIT_FCIE_CLK4X_20M, ++ BIT_FCIE_CLK4X_27M, ++ 0, ++ BIT_FCIE_CLK4X_36M, ++ BIT_FCIE_CLK4X_40M, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ BIT_FCIE_CLK4X_48M ++}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx = 0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 7 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 7) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ U32 dmaaddr; ++ ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++#if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++#endif ++ ++ return IRQ_NONE; ++ ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ #endif ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eiffel SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++ ++//--------------------------------------- ++ ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32us) ++{ ++ #if 0 // udelay not work ++ volatile u32 i = 0; ++ ++ for (i = 0; i < (u32us>>0); i++) ++ { ++ #if 1 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0x38; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #else ++ U32 u32_i = u32us; ++ ++ while(u32_i > 1000) ++ { ++ mdelay(1); ++ u32_i -= 1000; ++ } ++ udelay(u32_i); ++ #endif ++ return u32us; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ // Reset PIU Timer1 ++ REG_FCIE_W(TIMER1_MAX_LOW, 0xFFFF); ++ REG_FCIE_W(TIMER1_MAX_HIGH, 0xFFFF); ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ // Start PIU Timer1 ++ REG_FCIE_W(TIMER1_ENABLE, 0x1); ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ U32 u32HWTimer = 0; ++ U32 u32TimerLow = 0; ++ U32 u32TimerHigh = 0; ++ ++ // Get timer value ++ u32TimerLow = REG_FCIE(TIMER1_CAP_LOW); ++ u32TimerHigh = REG_FCIE(TIMER1_CAP_HIGH); ++ ++ u32HWTimer = (u32TimerHigh<<16) | u32TimerLow; ++ ++ REG_FCIE_W(TIMER1_ENABLE, 0); ++ ++ return u32HWTimer; ++} ++//-------------------------------- ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 0, "FCIE 1X (0x%X):0x%04X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 0, "FCIE 4X (0x%X):0x%04X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 0, "MIU (0x%X):0x%04X\n", reg_ckg_MIU, REG_FCIE_U16(reg_ckg_MIU)); ++ eMMC_debug(0, 0, "MCU (0x%X):0x%04X\n", reg_ckg_MCU, REG_FCIE_U16(reg_ckg_MCU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 0, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown, %Xh\n", g_eMMCDrv.u8_PadType); eMMC_die("\n"); ++ } ++ ++ eMMC_debug(0, 0, "reg_all_pad_in (0x%08X):0x%04X\n", reg_all_pad_in, REG_FCIE_U16(reg_all_pad_in)); ++ ++ eMMC_debug(0, 0, "reg_emmc_pad (0x%08X):0x%04X\n", reg_emmc_pad, REG_FCIE_U16(reg_emmc_pad)); ++ eMMC_debug(0, 0, "reg_pcm_d_pe (0x%08X):0x%04X\n", reg_pcm_d_pe, REG_FCIE_U16(reg_pcm_d_pe)); ++ eMMC_debug(0, 0, "reg_pcm_a_pe (0x%08X):0x%04X\n", reg_pcm_a_pe, REG_FCIE_U16(reg_pcm_a_pe)); ++ eMMC_debug(0, 0, "reg_pcm2_cd_n_pe (0x%08X):0x%04X\n", reg_pcm2_cd_n_pe, REG_FCIE_U16(reg_pcm2_cd_n_pe)); ++ ++ eMMC_debug(0, 0, "reg_sd_use_bypass (0x%08X):0x%04X\n", reg_sd_use_bypass, REG_FCIE_U16(reg_sd_use_bypass)); ++ eMMC_debug(0, 0, "reg_fcie2macro_sd_bypass (0x%08X):0x%04X\n", reg_fcie2macro_sd_bypass, REG_FCIE_U16(reg_fcie2macro_sd_bypass)); ++ ++ eMMC_debug(0, 0, "reg_pcmcia_pad (0x%08X):0x%04X\n", reg_pcmcia_pad, REG_FCIE_U16(reg_pcmcia_pad)); ++ eMMC_debug(0, 0, "reg_nand_pad (0x%08X):0x%04X\n", reg_nand_pad, REG_FCIE_U16(reg_nand_pad)); ++ eMMC_debug(0, 0, "reg_sd_pad (0x%08X):0x%04X\n", reg_sd_pad, REG_FCIE_U16(reg_sd_pad)); ++ ++ eMMC_debug(0, 0, "\n"); ++} ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT8|BIT9|BIT10|BIT11|BIT12); ++ REG_FCIE_SETBIT(reg_pcm_d_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm_a_pe, 0x00FF); // reg_pcm_pe ++ REG_FCIE_SETBIT(reg_pcm2_cd_n_pe, BIT1); // reg_pcm_pe ++ REG_FCIE_CLRBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(reg_sd_use_bypass, BIT0); // reg_sd_use_bypass ++ ++ REG_FCIE_SETBIT(reg_emmc_drv, 0x0007); ++ REG_FCIE_SETBIT(reg_nand_drv, 0xFF00); ++ REG_FCIE_SETBIT(reg_nand_ps, 0xFFFF); ++ ++ switch(u32_FCIE_IF_Type){ ++ case FCIE_eMMC_DDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: DDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT9); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: SDR\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: BYPASS\n"); ++ ++ // Let onboot & PCMCIA detemine the pad (reg_chiptop_0x6E) value ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT8|BIT10|BIT11); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ case FCIE_eMMC_TMUX: ++ eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 0,"eMMC pads: TMUX\n"); ++ ++ REG_FCIE_SETBIT(reg_fcie2macro_sd_bypass, BIT8); // reg_fcie2marco_sd_bypass ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT10|BIT12); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_TMUX; ++ break; ++ ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // set chiptop ++ ++ REG_FCIE_CLRBIT(reg_pcmcia_pad, BIT0|BIT4); ++ REG_FCIE_CLRBIT(reg_nand_pad, BIT5|BIT6|BIT7); ++ REG_FCIE_CLRBIT(reg_sd_pad, BIT8|BIT9|BIT10|BIT11); ++ ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT15); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++static U8 sgau8_FCIEClk_1X_To_4X_[0x10]= // index is 1X reg value ++{ ++ 0, ++ BIT_FCIE_CLK4X_20M, ++ BIT_FCIE_CLK4X_27M, ++ 0, ++ BIT_FCIE_CLK4X_36M, ++ BIT_FCIE_CLK4X_40M, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ 0, ++ BIT_FCIE_CLK4X_48M ++}; ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_27M: g_eMMCDrv.u32_ClkKHz = 27000; break; ++ //case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ //case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_Gate|BIT_FCIE_CLK_MASK); ++ REG_FCIE_SETBIT(reg_ckg_fcie_1X, BIT_FCIE_CLK_SEL|(u16_ClkParam<>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++ u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx = 0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)){ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: SDR mode can't detect DDR timing\n"); ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ printf("eMMC Err: set DDR IF fail: %X\n", u32_err); ++ return u32_err; ++ } ++ } ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 7 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 7) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u8_Clk) ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk == gau8_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u8_Clk != gau8_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ u32_ret = eMMC_ST_ERR_BUILD_DDRT; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail! please call CAE or RD for helps, %Xh \n", ++ u32_ret); ++ eMMC_ResetReadyFlag(); ++ eMMC_Init(); ++ eMMC_FCIE_EnableSDRMode(); ++ ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++//--------------------------------------- ++#ifdef CONFIG_OUTER_CACHE ++#include ++#endif ++#define HalUtilPHY2MIUAddr(addr) addr ++#define HalUtilMIU2PHYAddr(addr) addr ++ ++#define SYSHAL_DCACHE_LINE_SIZE 32 ++ ++#define HAL_DCACHE_START_ADDRESS(_addr_) \ ++ (((u32)(_addr_)) & ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++#define HAL_DCACHE_END_ADDRESS(_addr_, _asize_) \ ++ (((u32)((_addr_) + (_asize_) + (SYSHAL_DCACHE_LINE_SIZE-1) )) & \ ++ ~(SYSHAL_DCACHE_LINE_SIZE-1)) ++ ++static void _hal_dcache_flush(void *base , u32 asize) ++{ ++ register u32 _addr_ = HAL_DCACHE_START_ADDRESS((u32)base); ++ register u32 _eaddr_ = HAL_DCACHE_END_ADDRESS((u32)(base), asize); ++ ++ for( ; _addr_ < _eaddr_; _addr_ += SYSHAL_DCACHE_LINE_SIZE ) ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c14, 1" : : "r" (_addr_)); ++ ++ /* Drain write buffer */ ++ _addr_ = 0x00UL; ++ __asm__ __volatile__ ("MCR p15, 0, %0, c7, c10, 4" : : "r" (_addr_)); ++} ++ ++#define dma_dcache_flush(addr, size) _hal_dcache_flush(addr, size) ++#define dma_dcache_invalidate(addr, size) ++#ifdef CONFIG_OUTER_CACHE ++#define dma_dcache_flush_invalidate(addr, size) \ ++ do{ \ ++ _hal_dcache_flush((void *)addr, size); \ ++ outer_flush_range(__pa(addr),__pa(addr) + size); \ ++ outer_inv_range(__pa(addr),__pa(addr) + size); \ ++ }while(0) ++#else ++#define dma_dcache_flush_invalidate(addr, size) _hal_dcache_flush((void *)addr, size) ++#endif ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt) ++{ ++ U32 dmaaddr; ++ ++ dma_dcache_flush_invalidate(u32_DMAAddr, u32_ByteCnt); ++ dmaaddr = (virt_to_phys((void *)u32_DMAAddr)); ++ ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ REG_FCIE_SETBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ else ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ REG_FCIE_CLRBIT(FCIE_MIU_DMA_26_16, BIT_MIU1_SELECT); ++ } ++ return dmaaddr; ++ ++} ++ ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ if((REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++#if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++#endif ++ ++ return IRQ_NONE; ++ ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i= HW_TIMER_DELAY_1s*10) ++ { ++ eMMC_debug(0,1,"eMMC Info: PCM check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ #endif ++ return true; ++} ++ ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForCI); ++ ++ ++bool mstar_mci_exit_checkdone_ForSD(void) ++{ ++ U32 u32_Cnt=0; ++ ++ // eiffel SD_mode_x does not share pins ++ //if(BIT_eMMC_CFG_MODE2 == (REG_FCIE(reg_chiptop_0x5D)&BIT_eMMC_CFG_MASK)) ++ // return TRUE; ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ while(mstar_mci_exit_checkdone_Ex() == 0) /* card busy */ ++ { ++ if ((++u32_Cnt) >= HW_TIMER_DELAY_1s*10) ++ { ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ eMMC_debug(0,1,"eMMC Info: SD check -> D0 busy\n"); ++ return false; ++ } ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(0 == (u32_Cnt%HW_TIMER_DELAY_100us)) ++ { ++ msleep(1); ++ u32_Cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ return true; ++} ++EXPORT_SYMBOL(mstar_mci_exit_checkdone_ForSD); ++ ++ ++ ++//--------------------------------------- ++extern struct semaphore PfModeSem; ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ down(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_EMMC_ACTIVE); ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ up(&PfModeSem); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++//--------------------------------------- ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))|=0x02; // emi mask ++ *((volatile unsigned short *)(0x25007C18))|=0x02; // imi0 mask ++ *((volatile unsigned short *)(0x25007C58))|=0x02; // imi1 mask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ /**((volatile unsigned short *)(0x25007DCC))&=(~0x02); // emi unmask ++ *((volatile unsigned short *)(0x25007C18))&=(~0x02); // imi0 unmask ++ *((volatile unsigned short *)(0x25007C58))&=(~0x02); // imi1 unmask ++ */ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_DEFAULT_PAD); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32usTick) ++{ ++ #if 1 //xxx tomodify ++ udelay(u32usTick); ++ #else ++ volatile U32 i = 0; ++ ++ for (i = 0; i < (u32usTick>>4); i++) ++ { ++ #if 0 ++ volatile int j = 0, tmp; ++ for (j = 0; j < 0; j++) ++ { ++ tmp = j; ++ } ++ #endif ++ } ++ #endif ++ ++ return u32usTick + 1; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ // TIMER_FREERUN_32K 32 KHz ++ // TIMER_FREERUN_XTAL 38.4 MHz, ++ // counting down ++ return 0;//HalTimerRead(TIMER_FREERUN_32K); ++} ++//-------------------------------- ++ ++ ++void eMMC_DumpPadClk(void) ++{ ++#if 0 ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 1, "FCIE 1X (0x%X):0x%X\n", reg_ckg_fcie_1X, REG_FCIE_U16(reg_ckg_fcie_1X)); ++ eMMC_debug(0, 1, "FCIE 4X (0x%X):0x%X\n", reg_ckg_fcie_4X, REG_FCIE_U16(reg_ckg_fcie_4X)); ++ eMMC_debug(0, 1, "CMU (0x%X):0x%X\n", reg_ckg_CMU, REG_FCIE_U16(reg_ckg_CMU)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u32_Flag & FCIE_FLAG_PADTYPE_MASK) ++ { ++ case FCIE_FLAG_PADTYPE_DDR: ++ eMMC_debug(0,0,"DDR\n"); break; ++ case FCIE_FLAG_PADTYPE_SDR: ++ eMMC_debug(0,0,"SDR\n"); break; ++ case FCIE_FLAG_PADTYPE_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown\n"); eMMC_die("\n"); ++ } ++ eMMC_debug(0, 1, "chiptop_0x5A (0x%X):0x%X\n", reg_chiptop_0x5A, REG_FCIE_U16(reg_chiptop_0x5A)); ++ eMMC_debug(0, 1, "chiptop_0x1F (0x%X):0x%X\n", reg_chiptop_0x1F, REG_FCIE_U16(reg_chiptop_0x1F)); ++ eMMC_debug(0, 1, "chiptop_0x70 (0x%X):0x%X\n", reg_chiptop_0x70, REG_FCIE_U16(reg_chiptop_0x70)); ++ eMMC_debug(0, 1, "chiptop_0x64 (0x%X):0x%X\n", reg_chiptop_0x64, REG_FCIE_U16(reg_chiptop_0x64)); ++ eMMC_debug(0, 1, "chiptop_0x4F (0x%X):0x%X\n", reg_chiptop_0x4F, REG_FCIE_U16(reg_chiptop_0x4F)); ++ eMMC_debug(0, 1, "chiptop_0x03 (0x%X):0x%X\n", reg_chiptop_0x03, REG_FCIE_U16(reg_chiptop_0x03)); ++ eMMC_debug(0, 1, "chiptop_0x51 (0x%X):0x%X\n", reg_chiptop_0x51, REG_FCIE_U16(reg_chiptop_0x51)); ++ eMMC_debug(0, 1, "chiptop_0x6F (0x%X):0x%X\n\n", reg_chiptop_0x6F, REG_FCIE_U16(reg_chiptop_0x6F)); ++ ++ eMMC_debug(0, 1, "chiptop_0x43 (0x%X):0x%X\n", reg_chiptop_0x43, REG_FCIE_U16(reg_chiptop_0x43)); ++ eMMC_debug(0, 1, "chiptop_0x50 (0x%X):0x%X\n", reg_chiptop_0x50, REG_FCIE_U16(reg_chiptop_0x50)); ++ eMMC_debug(0, 1, "chiptop_0x0B (0x%X):0x%X\n", reg_chiptop_0x0B, REG_FCIE_U16(reg_chiptop_0x0B)); ++ eMMC_debug(0, 1, "chiptop_0x5D (0x%X):0x%X\n", reg_chiptop_0x5D, REG_FCIE_U16(reg_chiptop_0x5D)); ++ ++ eMMC_debug(0, 1, "\n"); ++#endif ++} ++ ++U8 gu8_NANDeMMC_need_preset_flag = 1; ++#define BIT_BOOT_CONFIG_MODE_MASK BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ //only for Cedric eMMC ++ if (gu8_NANDeMMC_need_preset_flag == 1) ++ { ++ eMMC_printf("========== gu8_NANDeMMC_need_preset_flag = 1 =========="); ++ //REG_FCIE_SETBIT(FCIE_REG_2Dh, BIT_NEW_DESIGN_ENn); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT3); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_10us); ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT3); ++ ++ gu8_NANDeMMC_need_preset_flag = 0; ++ } ++ ++ ++ ++// REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, ++// BIT_MACRO_EN|BIT_SD_DDR_EN|BIT_SD_BYPASS_MODE_EN|BIT_SD_SDR_IN_BYPASS|BIT_SD_FROM_TMUX); ++ ++ switch(u32_FCIE_IF_Type) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_printf("eMMC_pads_switch FCIE_eMMC_DDR\r\n"); ++ #define R_DDR_MODE BIT_MACRO_EN | BIT_SD_DDR_EN ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_BOOT_CONFIG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, R_DDR_MODE); ++ REG_FCIE_SETBIT(RIU_BASE_CHIPTOP + (0x4 << 2), BIT1); ++ REG_FCIE_CLRBIT(REG_BPS_MODE, 0x3FF); ++ REG_FCIE_CLRBIT(REG_ALL_PAD_IN, BIT0); ++ REG_FCIE_SETBIT(REG_EMMC_MODE, BIT13); ++ ++ REG_FCIE_SETBIT(eMMC_REG_CLK_4X_DIV_EN, BIT0); ++ ++ // set chiptop ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_printf("eMMC_pads_switch FCIE_eMMC_SDR\r\n"); ++ #define R_SDR_MODE BIT_MACRO_EN ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_BOOT_CONFIG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, R_SDR_MODE); ++ REG_FCIE_SETBIT(RIU_BASE_CHIPTOP + (0x4 << 2), BIT1); ++ REG_FCIE_CLRBIT(REG_BPS_MODE, 0x3FF); ++ REG_FCIE_CLRBIT(REG_ALL_PAD_IN, BIT0); ++ REG_FCIE_SETBIT(REG_EMMC_MODE, BIT13); ++ REG_FCIE_SETBIT(eMMC_REG_CLK_4X_DIV_EN, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_printf("eMMC_pads_switch FCIE_eMMC_BYPASS\r\n"); ++ #define R_BYPASS_MODE BIT_MACRO_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS ++ REG_FCIE_CLRBIT(FCIE_BOOT_CONFIG, BIT_BOOT_CONFIG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, R_BYPASS_MODE); ++ REG_FCIE_SETBIT(RIU_BASE_CHIPTOP + (0x4 << 2), BIT1); ++ REG_FCIE_SETBIT(REG_BPS_MODE, 0x3FF); ++ REG_FCIE_CLRBIT(REG_ALL_PAD_IN, BIT0); ++ REG_FCIE_SETBIT(REG_EMMC_MODE, BIT13); ++ REG_FCIE_CLRBIT(eMMC_REG_CLK_4X_DIV_EN, BIT0); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_SETBIT(FCIE_REG_2Dh, BIT_NEW_DESIGN_ENn); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_24M: g_eMMCDrv.u32_ClkKHz = 24000; break; ++ case BIT_FCIE_CLK_12M: g_eMMCDrv.u32_ClkKHz = 12000; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ case BIT_FCIE_CLK_86M: g_eMMCDrv.u32_ClkKHz = 86000; break; ++ case BIT_FCIE_CLK_108M: g_eMMCDrv.u32_ClkKHz = 108000; break; ++ case BIT_FCIE_CLK_123M: g_eMMCDrv.u32_ClkKHz = 123000; break; ++ case BIT_FCIE_CLK_144M: g_eMMCDrv.u32_ClkKHz = 144000; break; ++ case BIT_FCIE_CLK_172M: g_eMMCDrv.u32_ClkKHz = 172000; break; ++ case BIT_FCIE_CLK_192M: g_eMMCDrv.u32_ClkKHz = 192000; break; ++ case BIT_FCIE_CLK_216M: g_eMMCDrv.u32_ClkKHz = 216000; break; ++ case BIT_FCIE_CLK_240M: g_eMMCDrv.u32_ClkKHz = 240000; break; ++ case BIT_FCIE_CLK_345M: g_eMMCDrv.u32_ClkKHz = 345000; break; ++ case BIT_FCIE_CLK_432M: g_eMMCDrv.u32_ClkKHz = 432000; break; ++ case BIT_FCIE_CLK_1200K: g_eMMCDrv.u32_ClkKHz = 1200; break; ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_54M: g_eMMCDrv.u32_ClkKHz = 54000; break; ++ case BIT_FCIE_CLK_62M: g_eMMCDrv.u32_ClkKHz = 62000; break; ++ case BIT_FCIE_CLK_72M: g_eMMCDrv.u32_ClkKHz = 72000; break; ++ case BIT_FCIE_CLK_80M: g_eMMCDrv.u32_ClkKHz = 80000; break; ++ ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid clk: %Xh\n", u16_ClkParam); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ REG_FCIE_W(REG_CLK_EMMC, (u16_ClkParam)); ++ g_eMMCDrv.u16_ClkRegVal = (U16)u16_ClkParam; ++ ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_clock_gating(void) ++{ ++ eMMC_PlatformResetPre(); ++ g_eMMCDrv.u32_ClkKHz = 0; ++ REG_FCIE_W(REG_CLK_EMMC, BIT_FCIE_CLK_Gate); ++ //REG_FCIE_W(reg_ckg_fcie_4X, BIT_FCIE_CLK4X_Gate); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U16 gau16_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT]={ ++ ++ BIT_FCIE_CLK_192M, BIT_FCIE_CLK_172M, /*BIT_FCIE_CLK_144M,*/ BIT_FCIE_CLK_123M, /*BIT_FCIE_CLK_108M,*/ ++ BIT_FCIE_CLK_86M, /*BIT_FCIE_CLK_80M, BIT_FCIE_CLK_72M,*/ BIT_FCIE_CLK_62M, BIT_FCIE_CLK_54M, ++ /*BIT_FCIE_CLK_48M, BIT_FCIE_CLK_43_2M,*/ BIT_FCIE_CLK_40M, /*BIT_FCIE_CLK_36M,*/ BIT_FCIE_CLK_32M, ++ BIT_FCIE_CLK_24M, BIT_FCIE_CLK_12M/*, BIT_FCIE_CLK_1200K, BIT_FCIE_CLK_300K*/ ++}; ++#define FCIE_SLOW_CLK_4X BIT_FCIE_CLK_12M ++ ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++static char *sgachar_string[]={" 2T", "1.5T", "2.5T"," 1T"}; ++ ++static U32 eMMC_FCIE_DetectDDRTiming_Ex(U8 u8_DQS, U8 u8_DelaySel) ++{ ++ U32 u32_SectorAddr; ++ ++ //eMMC_printf("eMMC_FCIE_DetectDDRTiming_Ex\r\n"); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ ++ //eMMC_printf("eMMC_TEST_BLK_0: %X\r\n", u32_SectorAddr); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\ndqs:%s[%Xh] cell:%02Xh \n", ++ sgachar_string[u8_DQS], u8_DQS, u8_DelaySel); ++ ++ eMMC_FCIE_SetDDRTimingReg(u8_DQS, u8_DelaySel); ++ return eMMCTest_BlkWRC_ProbeDDR(u32_SectorAddr); ++} ++ ++#define FCIE_DELAY_CELL_ts 300 // 0.3ns ++static eMMC_FCIE_DDRT_WINDOW_t sg_DDRTWindow[2]; ++ ++U32 eMMC_FCIE_DetectDDRTiming(void) ++{ ++ U8 u8_dqs, u8_delay_sel, u8_i; ++ U8 u8_dqs_prev=0xFF, u8_delay_sel_prev=0; ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 au8_DQS_10T[4]={0,15,20,25}; // 0T, 1.5T, 2T, 2.5T ++ ++ U8 u8_delay_Sel_max; ++ U32 u32_ts; ++ U32 u32_err; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow = &sg_DDRTWindow[0]; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_TUNING; // just to turn off some log ++ ++ //-------------------------------------------------- ++ sg_DDRTWindow[0].u8_Cnt = 0; ++ sg_DDRTWindow[0].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[0].aParam[1].u8_DQS = 0; ++ sg_DDRTWindow[1].u8_Cnt = 0; ++ sg_DDRTWindow[1].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[1].aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++// u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ eMMC_printf("u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)\r\n"); ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_printf("DetectDDRTiming pass\r\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_SUCCESS; ++ } ++ else ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ } ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx=0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ //eMMC_printf("eMMC Info: building DDR table, please wait... \n"); ++ ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ ++ ++ //iantest ttt ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE)) ++ { ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //RETAILMSG(1, (TEXT("eMMC Error: set DDR IF fail: %Xh\r\n"),u32_err)); ++ eMMC_printf("eMMC Error: set DDR IF fail: %Xh\r\n",u32_err); ++ return u32_err; ++ } ++ } ++ ++ eMMC_pads_switch(FCIE_eMMC_DDR); //iantest ttt ++ //iantest ttt ++ ++ ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 3 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 3) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK_4X == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk) ++ { ++ eMMC_printf("FCIE_SLOW_CLK_4X == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk\r\n"); ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ } ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ ++ eMMC_printf("gau16_FCIEClkSel[0] : %X\r\n", gau16_FCIEClkSel[0]); ++ eMMC_printf("g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk : %X\r\n", g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk); ++ eMMC_printf("g_eMMCDrv.DDRTable.u8_SetCnt : %X\r\n", g_eMMCDrv.DDRTable.u8_SetCnt); ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk == gau16_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk != gau16_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ eMMC_FCIE_EnableSDRMode(); ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++#define MSTAR_MIU0_BUS_BASE 0x40000000 ++#define MSTAR_MIU1_BUS_BASE 0xA0000000 ++ ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++#if 1 ++ extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ //mode 0 for write, 1 for read ++ if( mode == WRITE_TO_eMMC ) //Write ++ { ++ //Write (DRAM->NAND)-> flush ++ Chip_Clean_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ else //Read ++ { ++ //Read (NAND->DRAM) -> inv ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ /* ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ { ++ REG_SET_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ } ++ else ++ REG_CLR_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ */ ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++#else ++ flush_cache(u32_DMAAddr, u32_ByteCnt); ++ return (u32_DMAAddr); ++#endif ++} ++ ++/* ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ flush_cache(u32_addr, s32_size); ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++*/ ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i ++//extern struct semaphore PfModeSem; ++extern struct mutex FCIE3_mutex; ++//#define CRIT_SECT_BEGIN(x) mutex_lock(x) ++//#define CRIT_SECT_END(x) mutex_unlock(x) ++ ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ mutex_lock(&FCIE3_mutex); ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ //eMMC_debug(0,1,"%s 1\n", pu8_str); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ mutex_unlock(&FCIE3_mutex); ++ ++ //eMMC_debug(0,1,"%s 2\n", pu8_str); ++} ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++U32 eMMC_hw_timer_delay(U32 u32usTick) ++{ ++ volatile U32 u32_i=u32usTick; ++ ++ while(u32_i>1000) ++ { ++ udelay(1000); ++ u32_i-=1000; ++ } ++ ++ udelay(u32usTick); ++ return u32usTick + 1; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ return 0; ++} ++//-------------------------------- ++ ++ ++void eMMC_DumpPadClk(void) ++{ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[clk setting]: %uKHz \n", g_eMMCDrv.u32_ClkKHz); ++ eMMC_debug(0, 1, "FCIE 1X (0x%X):0x%X\n", REG_CLK_EMMC, REG_FCIE_U16(REG_CLK_EMMC)); ++ eMMC_debug(0, 1, "FCIE 4X (0x%X):0x%X\n", REG_CLK_4X_DIV_EN, REG_FCIE_U16(REG_CLK_4X_DIV_EN)); ++ ++ //---------------------------------------------- ++ eMMC_debug(0, 1, "\n[pad setting]: "); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"DDR\n"); ++ break; ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"SDR\n"); ++ break; ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"BYPASS\n"); ++ break; ++ default: ++ eMMC_debug(0,0,"eMMC Err: Pad unknown\n"); ++ eMMC_die("\n"); ++ } ++ eMMC_debug(0, 1, "padtop_0x00 (0x%X):0x%X\n", REG_PADTOP_00, REG_FCIE_U16(REG_PADTOP_00)); ++ eMMC_debug(0, 1, "padtop_0x01 (0x%X):0x%X\n", REG_PADTOP_01, REG_FCIE_U16(REG_PADTOP_01)); ++ eMMC_debug(0, 1, "padtop_0x40 (0x%X):0x%X\n", REG_PADTOP_40, REG_FCIE_U16(REG_PADTOP_40)); ++ eMMC_debug(0, 1, "padtop_0x43 (0x%X):0x%X\n", REG_PADTOP_43, REG_FCIE_U16(REG_PADTOP_43)); ++ eMMC_debug(0, 1, "chiptop_0x31 (0x%X):0x%X\n", REG_RESET_PIN, REG_FCIE_U16(REG_RESET_PIN)); ++ ++ eMMC_debug(0, 1, "fcie_0x2F (0x%X):0x%X\n", FCIE_BOOT_CONFIG, REG_FCIE_U16(FCIE_BOOT_CONFIG)); ++ eMMC_debug(0, 1, "fcie_0x2D (0x%X):0x%X\n", FCIE_REG_2Dh, REG_FCIE_U16(FCIE_REG_2Dh)); ++ ++ ++ eMMC_debug(0, 1, "\n"); ++ ++} ++ ++U8 gu8_NANDeMMC_need_preset_flag = 1; ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ U16 u16_reg; ++ switch(u32_FCIE_IF_Type) ++ { ++ case FCIE_eMMC_DDR: ++ eMMC_debug(0,0,"eMMC_pads_switch FCIE_eMMC_DDR\r\n"); ++ REG_FCIE_R(FCIE_BOOT_CONFIG, u16_reg); ++ u16_reg &= ~(BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX); ++ u16_reg |= (BIT_MACRO_EN | BIT_SD_DDR_EN); ++ REG_FCIE_W(FCIE_BOOT_CONFIG, u16_reg); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT14); ++ ++ //CLRREG16(FCIE_BOOT_CONFIG, BIT3); //to MIU ++ REG_FCIE_R(REG_PADTOP_00, u16_reg); ++ u16_reg |= BIT15; ++ u16_reg &= ~(BIT0 + BIT14); ++ REG_FCIE_W(REG_PADTOP_00, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_01, u16_reg); ++ u16_reg &= ~(BIT3); ++ REG_FCIE_W(REG_PADTOP_01, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_40, u16_reg); ++ u16_reg &= ~(BIT3 + BIT8 + BIT9); ++ REG_FCIE_W(REG_PADTOP_40, u16_reg); ++ ++ REG_FCIE_SETBIT(REG_PADTOP_43, BIT3); ++ ++ REG_FCIE_SETBIT(REG_CLK_4X_DIV_EN, BIT0); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_DDR; ++ break; ++ ++ case FCIE_eMMC_SDR: ++ eMMC_debug(0,0,"eMMC_pads_switch FCIE_eMMC_SDR\r\n"); ++ REG_FCIE_R(FCIE_BOOT_CONFIG, u16_reg); ++ u16_reg &= ~(BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX); ++ u16_reg |= (BIT_MACRO_EN); ++ REG_FCIE_W(FCIE_BOOT_CONFIG, u16_reg); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT14); ++ ++ //CLRREG16(FCIE_BOOT_CONFIG, BIT3); //to MIU ++ REG_FCIE_R(REG_PADTOP_00, u16_reg); ++ u16_reg |= BIT15; ++ u16_reg &= ~(BIT0 + BIT14); ++ REG_FCIE_W(REG_PADTOP_00, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_01, u16_reg); ++ u16_reg &= ~(BIT3); ++ REG_FCIE_W(REG_PADTOP_01, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_40, u16_reg); ++ u16_reg &= ~(BIT3 + BIT8 + BIT9); ++ REG_FCIE_W(REG_PADTOP_40, u16_reg); ++ ++ REG_FCIE_SETBIT(REG_PADTOP_43, BIT3); ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ break; ++ ++ ++ case FCIE_eMMC_BYPASS: ++ eMMC_debug(0,0,"eMMC_pads_switch FCIE_eMMC_BYPASS\r\n"); ++ REG_FCIE_R(FCIE_BOOT_CONFIG, u16_reg); ++ u16_reg &= ~(BIT_MACRO_EN | BIT_SD_DDR_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS | BIT_SD_FROM_TMUX); ++ u16_reg |= (BIT_MACRO_EN | BIT_SD_BYPASS_MODE_EN | BIT_SD_SDR_IN_BYPASS); ++ REG_FCIE_W(FCIE_BOOT_CONFIG, u16_reg); ++ ++ REG_FCIE_CLRBIT(FCIE_REG_2Dh, BIT14); ++ ++ //CLRREG16(FCIE_BOOT_CONFIG, BIT3); //to MIU ++ ++ REG_FCIE_R(REG_PADTOP_00, u16_reg); ++ u16_reg |= BIT15; ++ u16_reg &= ~(BIT0 + BIT14); ++ REG_FCIE_W(REG_PADTOP_00, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_01, u16_reg); ++ u16_reg &= ~(BIT3); ++ REG_FCIE_W(REG_PADTOP_01, u16_reg); ++ ++ REG_FCIE_R(REG_PADTOP_40, u16_reg); ++ u16_reg |= (BIT3 + BIT8 + BIT9); ++ REG_FCIE_W(REG_PADTOP_40, u16_reg); ++ ++ REG_FCIE_SETBIT(REG_PADTOP_43, BIT3); ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ break; ++ ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown interface: %X\n",u32_FCIE_IF_Type); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++ eMMC_PlatformResetPre(); ++ ++ REG_FCIE_SETBIT(REG_CLK_4X_DIV_EN, BIT0); ++ ++ switch(u16_ClkParam) { ++ case NFIE_REG_4XCLK_1_3M: g_eMMCDrv.u32_ClkKHz = 1300; break; ++ case NFIE_REG_4XCLK_26M: g_eMMCDrv.u32_ClkKHz = 26000; break; ++ case NFIE_REG_4XCLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ case NFIE_REG_4XCLK_80M: g_eMMCDrv.u32_ClkKHz = 80000; break; ++ case NFIE_REG_4XCLK_96M: g_eMMCDrv.u32_ClkKHz = 96000; break; ++ case NFIE_REG_4XCLK_120M: g_eMMCDrv.u32_ClkKHz = 120000; break; ++ case NFIE_REG_4XCLK_147M: g_eMMCDrv.u32_ClkKHz = 147000; break; ++ case NFIE_REG_4XCLK_160M: g_eMMCDrv.u32_ClkKHz = 160000; break; ++ case NFIE_REG_4XCLK_176_8M: g_eMMCDrv.u32_ClkKHz = 176800; break; ++ case NFIE_REG_4XCLK_192M: g_eMMCDrv.u32_ClkKHz = 192000; break; ++ case NFIE_REG_4XCLK_221M: g_eMMCDrv.u32_ClkKHz = 221000; break; ++ case NFIE_REG_4XCLK_240M: g_eMMCDrv.u32_ClkKHz = 240000; break; ++ case NFIE_REG_4XCLK_294_6M: g_eMMCDrv.u32_ClkKHz = 294600; break; ++ case NFIE_REG_4XCLK_353_6M: g_eMMCDrv.u32_ClkKHz = 353600; break; ++ case NFIE_REG_4XCLK_60M: g_eMMCDrv.u32_ClkKHz = 60000; break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid clk: %Xh\n", u16_ClkParam); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ //printf("REG_CLK_EMMC : %X, %uKHZ\r\n", u16_ClkParam, g_eMMCDrv.u32_ClkKHz/4); ++ ++ REG_FCIE_W(REG_CLK_EMMC, (u16_ClkParam)); ++ g_eMMCDrv.u16_ClkRegVal = (U16)u16_ClkParam; ++ ++ ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_clock_gating(void) ++{ ++ eMMC_PlatformResetPre(); ++ g_eMMCDrv.u32_ClkKHz = 0; ++ REG_FCIE_W(REG_CLK_EMMC, BIT_FCIE_CLK_Gate); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++U16 gau16_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT]={ ++ NFIE_REG_4XCLK_192M, NFIE_REG_4XCLK_160M, NFIE_REG_4XCLK_120M, ++ NFIE_REG_4XCLK_96M ,NFIE_REG_4XCLK_80M ++ ++}; ++ ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++static char *sgachar_string[]={" 0T", "0.5T", " 1T", "1.5T", " 2T", "2.5T", " 3T", "3.5T"}; ++ ++static U32 eMMC_FCIE_DetectDDRTiming_Ex(U8 u8_DQS, U8 u8_DelaySel) ++{ ++ U32 u32_SectorAddr; ++ ++ //eMMC_printf("eMMC_FCIE_DetectDDRTiming_Ex\r\n"); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ ++ //eMMC_printf("eMMC_TEST_BLK_0: %X\r\n", u32_SectorAddr); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\ndqs:%s[%Xh] cell:%02Xh \n", ++ sgachar_string[u8_DQS], u8_DQS, u8_DelaySel); ++ ++ eMMC_FCIE_SetDDRTimingReg(u8_DQS, u8_DelaySel); ++ return eMMCTest_BlkWRC_ProbeDDR(u32_SectorAddr); ++} ++ ++#define FCIE_DELAY_CELL_ts 300 // 0.3ns ++static eMMC_FCIE_DDRT_WINDOW_t sg_DDRTWindow[2]; ++ ++U32 eMMC_FCIE_DetectDDRTiming(void) ++{ ++ U8 u8_dqs, u8_delay_sel, u8_i; ++ U8 u8_dqs_prev=0xFF, u8_delay_sel_prev=0; ++ U8 au8_DQSRegVal[8]={0,1,2,3,4,5,6,7}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3,5T ++ U8 au8_DQS_10T[8]={0,5,10,15,20,25,30,35}; // 0T, 0.5T, 1T, 1.5T, 2T, 2.5T, 3T, 3,5T ++ ++ U8 u8_delay_Sel_max; ++ U32 u32_ts; ++ U32 u32_err; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow = &sg_DDRTWindow[0]; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_TUNING; // just to turn off some log ++ ++ //-------------------------------------------------- ++ sg_DDRTWindow[0].u8_Cnt = 0; ++ sg_DDRTWindow[0].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[0].aParam[1].u8_DQS = 0; ++ sg_DDRTWindow[1].u8_Cnt = 0; ++ sg_DDRTWindow[1].aParam[0].u8_DQS = 0; ++ sg_DDRTWindow[1].aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]=0; ++ sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]=0; ++ } ++ ++ //-------------------------------------------------- ++ // calculate delay_Sel_max ++ u32_ts = 1000*1000*1000 / g_eMMCDrv.u32_ClkKHz; ++// u32_ts >>= 2; // for 4X's 1T ++ ++ //-------------------------------------------------- ++ // no need to try DQS of no delay ++ //for(u8_dqs=0; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ for(u8_dqs=1; u8_dqs<=(BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT); u8_dqs++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n---------------------------\n"); ++ ++ if(u8_dqs < (BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT)) ++ u8_delay_Sel_max = ++ (au8_DQS_10T[u8_dqs+1]-au8_DQS_10T[u8_dqs]) ++ *u32_ts/(FCIE_DELAY_CELL_ts*10); ++ else ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ ++ if(u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n", u8_delay_Sel_max); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"invalid, not try\n\n"); ++ //continue; ++ eMMC_printf("u8_delay_Sel_max > (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT)\r\n"); ++ u8_delay_Sel_max = (BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"max delay cell: %u\n\n", u8_delay_Sel_max); ++ ++ sg_DDRTWindow[0].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ sg_DDRTWindow[1].au8_DQSTryCellCnt[u8_dqs] = u8_delay_Sel_max; ++ ++ //for(u8_delay_sel=0; u8_delay_sel<=(BIT_DQS_DELAY_CELL_MASK>>BIT_DQS_DELAY_CELL_SHIFT); u8_delay_sel++) ++ for(u8_delay_sel=0; u8_delay_sel<=u8_delay_Sel_max; u8_delay_sel++) ++ { ++ u32_err = eMMC_FCIE_DetectDDRTiming_Ex(au8_DQSRegVal[u8_dqs], u8_delay_sel); ++ if(eMMC_ST_SUCCESS == u32_err) ++ { ++ eMMC_printf("DetectDDRTiming pass\r\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0," PASS\n\n"); ++ pWindow->u8_Cnt++; ++ if(0 == pWindow->aParam[0].u8_DQS) // save the window head ++ { ++ pWindow->aParam[0].u8_DQS = u8_dqs; // dqs uses index ++ pWindow->aParam[0].u8_Cell = u8_delay_sel; ++ } ++ pWindow->au8_DQSValidCellCnt[u8_dqs]++; ++ ++ u8_dqs_prev = u8_dqs; ++ u8_delay_sel_prev = u8_delay_sel; ++ } ++ else ++ { // save the window tail ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ u8_dqs_prev = 0xFF; ++ ++ // discard & re-use the window having less PASS cnt ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt < sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ pWindow->u8_Cnt = 0; ++ pWindow->aParam[0].u8_DQS = 0; ++ pWindow->aParam[1].u8_DQS = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ pWindow->au8_DQSValidCellCnt[u8_i]=0; ++ } ++ } ++ } ++ ++ // for the case of last try is ok ++ if(0xFF != u8_dqs_prev) ++ { ++ pWindow->aParam[1].u8_DQS = u8_dqs_prev; // dqs uses index ++ pWindow->aParam[1].u8_Cell = u8_delay_sel_prev; ++ } ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_TUNING; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W0, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[0].u8_Cnt, ++ sg_DDRTWindow[0].aParam[0].u8_DQS, sg_DDRTWindow[0].aParam[0].u8_Cell, ++ sg_DDRTWindow[0].aParam[1].u8_DQS, sg_DDRTWindow[0].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[0].au8_DQSValidCellCnt[u8_i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"\n W1, Cnt:%Xh, [%Xh %Xh], [%Xh %Xh]\n", ++ sg_DDRTWindow[1].u8_Cnt, ++ sg_DDRTWindow[1].aParam[0].u8_DQS, sg_DDRTWindow[1].aParam[0].u8_Cell, ++ sg_DDRTWindow[1].aParam[1].u8_DQS, sg_DDRTWindow[1].aParam[1].u8_Cell); ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,0,"DQSValidCellCnt[%u]:%u \n", ++ u8_i, sg_DDRTWindow[1].au8_DQSValidCellCnt[u8_i]); ++ ++ if(sg_DDRTWindow[0].u8_Cnt || sg_DDRTWindow[1].u8_Cnt) ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_SUCCESS; ++ } ++ else ++ { ++ eMMC_printf("eMMC_FCIE_DetectDDRTiming OK\r\n"); ++ return eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ } ++} ++ ++ ++U32 eMMC_FCIE_BuildDDRTimingTable(void) ++{ ++ U8 au8_DQSRegVal[4]={3,1,0,2}; // 0T, 1.5T, 2T, 2.5T ++ U8 u8_i, u8_ClkIdx, u8_SetIdx, u8_tmp, u8_DqsIdx=0, u8_CellBase; ++ U32 u32_err, u32_ret=eMMC_ST_ERR_NO_OK_DDR_PARAM; ++ eMMC_FCIE_DDRT_WINDOW_t *pWindow; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: building DDR table, please wait... \n"); ++ //eMMC_printf("eMMC Info: building DDR table, please wait... \n"); ++ ++ memset((void*)&g_eMMCDrv.DDRTable, '\0', sizeof(g_eMMCDrv.DDRTable)); ++ u8_SetIdx = 0; ++ ++ ++ ++ //iantest ttt ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE)) ++ { ++ u32_err = eMMC_FCIE_EnableDDRMode_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //RETAILMSG(1, (TEXT("eMMC Error: set DDR IF fail: %Xh\r\n"),u32_err)); ++ eMMC_printf("eMMC Error: set DDR IF fail: %Xh\r\n",u32_err); ++ return u32_err; ++ } ++ } ++ ++ eMMC_pads_switch(FCIE_eMMC_DDR); //iantest ttt ++ //iantest ttt ++ ++ ++ for(u8_ClkIdx=0; u8_ClkIdx sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ // --------------------------- ++ if(NULL != pWindow) ++ { ++ ++ // pick up the DQS having max valid cell ++ u8_tmp = 0; ++ for(u8_i=1; u8_i <= BIT_DQS_MODE_MASK>>BIT_DQS_MDOE_SHIFT; u8_i++) ++ { ++ if(u8_tmp <= pWindow->au8_DQSValidCellCnt[u8_i]){ ++ u8_tmp = pWindow->au8_DQSValidCellCnt[u8_i]; ++ u8_DqsIdx = u8_i; ++ } ++ } ++ if(0 != u8_DqsIdx) // do not use 0T, this should be always TRUE ++ { ++ if(pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] >= 3 && ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] >= 3) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = 0; // nice ++ } ++ else ++ { ++ u8_tmp = (pWindow->au8_DQSValidCellCnt[u8_DqsIdx] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) / 2; ++ ++ ++ if(u8_tmp < pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]) ++ { ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx-1]; ++ ++ u8_CellBase = pWindow->au8_DQSTryCellCnt[u8_DqsIdx-1] - pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ u8_CellBase + pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx] - u8_tmp; ++ } ++ else ++ { g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = ++ au8_DQSRegVal[u8_DqsIdx]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->au8_DQSValidCellCnt[u8_DqsIdx-1] + ++ pWindow->au8_DQSValidCellCnt[u8_DqsIdx]) / 2; ++ } ++ } ++ } ++ } ++ ++ // --------------------------- ++ // or, pick up the Window of large PASS Cnt ++ else //if(NULL == pWindow) ++ { ++ pWindow = ++ (sg_DDRTWindow[0].u8_Cnt > sg_DDRTWindow[1].u8_Cnt) ? ++ &sg_DDRTWindow[0] : &sg_DDRTWindow[1]; ++ ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_DQS = au8_DQSRegVal[pWindow->aParam[0].u8_DQS]; ++ g_eMMCDrv.DDRTable.Set[u8_SetIdx].Param.u8_Cell = ++ (pWindow->aParam[0].u8_Cell + pWindow->aParam[1].u8_Cell)/2; ++ } ++ ++ #if 0 ++ // --------------------------- ++ // use 12M for Set.Min ++ if(eMMC_FCIE_DDRT_SET_CNT-2 == u8_SetIdx) ++ u8_ClkIdx = eMMC_FCIE_VALID_CLK_CNT-2; ++ #else ++ if(FCIE_SLOW_CLK == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk) ++ { ++ eMMC_printf("FCIE_SLOW_CLK_4X == g_eMMCDrv.DDRTable.Set[u8_SetIdx].u16_Clk\r\n"); ++ g_eMMCDrv.DDRTable.u8_SetCnt = u8_SetIdx + 1; ++ } ++ #endif ++ ++ u8_SetIdx++; ++ } ++ } ++ ++ // dump DDRT Set ++ u8_tmp = eMMC_FCIE_VALID_CLK_CNT > eMMC_FCIE_DDRT_SET_CNT ? ++ eMMC_FCIE_DDRT_SET_CNT : eMMC_FCIE_VALID_CLK_CNT; ++ u8_tmp = u8_tmp > g_eMMCDrv.DDRTable.u8_SetCnt ? ++ g_eMMCDrv.DDRTable.u8_SetCnt : u8_tmp; ++ ++ eMMC_DumpDDRTTable(); ++ ++ // ====================================================== ++ // CAUTION: expect 48MHz can have valid DDRT parameter ++ ++ eMMC_printf("gau16_FCIEClkSel[0] : %X\r\n", gau16_FCIEClkSel[0]); ++ eMMC_printf("g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk : %X\r\n", g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk); ++ eMMC_printf("g_eMMCDrv.DDRTable.u8_SetCnt : %X\r\n", g_eMMCDrv.DDRTable.u8_SetCnt); ++ if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk == gau16_FCIEClkSel[0] ++ && 0 != g_eMMCDrv.DDRTable.u8_SetCnt) ++ u32_ret = eMMC_ST_SUCCESS; ++ else if(g_eMMCDrv.DDRTable.Set[eMMC_DDRT_SET_MAX].u16_Clk != gau16_FCIEClkSel[0]) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: max clk can NOT run DDR\n"); ++ else if(0 == g_eMMCDrv.DDRTable.u8_SetCnt) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: min clk can NOT run DDR\n"); ++ // ====================================================== ++ ++ // --------------------------- ++ // save DDRT Table ++ if(eMMC_ST_SUCCESS == u32_ret) ++ { ++ ++ g_eMMCDrv.DDRTable.u32_ChkSum = ++ eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)-4); ++ memcpy(gau8_eMMC_SectorBuf, (U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable)); ++ ++ eMMC_FCIE_ApplyDDRTSet(eMMC_DDRT_SET_MAX); ++ ++ u32_err = eMMC_CMD24(eMMC_DDRTABLE_BLK_0, gau8_eMMC_SectorBuf); ++ u32_ret = eMMC_CMD24(eMMC_DDRTABLE_BLK_1, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS!=u32_err && eMMC_ST_SUCCESS!=u32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC ERROR: %Xh %Xh\n", ++ u32_err, u32_ret); ++ return eMMC_ST_ERR_SAVE_DDRT_FAIL; ++ } ++ } ++ else ++ { ++ gau8_eMMC_SectorBuf[0] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>24); ++ gau8_eMMC_SectorBuf[1] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>>16); ++ gau8_eMMC_SectorBuf[2] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 8); ++ gau8_eMMC_SectorBuf[3] = (U8)~(eMMC_ChkSum((U8*)&g_eMMCDrv.DDRTable, sizeof(g_eMMCDrv.DDRTable))>> 0); ++ ++ eMMC_FCIE_EnableSDRMode(); ++ } ++ ++ return u32_ret; ++} ++ ++#endif // IF_DETECT_eMMC_DDR_TIMING ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++ ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++#if 1 ++ extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ //mode 0 for write, 1 for read ++ if( mode == WRITE_TO_eMMC ) //Write ++ { ++ //Write (DRAM->NAND)-> flush ++ Chip_Clean_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ else //Read ++ { ++ //Read (NAND->DRAM) -> inv ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ /* ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ { ++ REG_SET_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ } ++ else ++ REG_CLR_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ */ ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++#else ++ flush_cache(u32_DMAAddr, u32_ByteCnt); ++ return (u32_DMAAddr); ++#endif ++} ++ ++/* ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ flush_cache(u32_addr, s32_size); ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++*/ ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 1 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ // one time enable one bit ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & BIT_MIU_LAST_DONE) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CARD_DMA_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_SD_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ else if(u16_Events & BIT_SD_BUSY_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_SD_BUSY_END); ++ REG_FCIE_CLRBIT(FCIE_SD_CTRL, BIT_SD_BUSY_DET_ON); ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ #endif ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(U32 u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i ++//extern struct semaphore PfModeSem; ++extern struct mutex FCIE3_mutex; ++//#define CRIT_SECT_BEGIN(x) mutex_lock(x) ++//#define CRIT_SECT_END(x) mutex_unlock(x) ++ ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ mutex_lock(&FCIE3_mutex); ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ if(false == ms_sdmmc_wait_d0_for_emmc()) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ #endif ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // output clock ++} ++ ++void eMMC_UnlockFCIE(U8 *pu8_str) ++{ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); // not output clock ++ mutex_unlock(&FCIE3_mutex); ++} ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ #if defined(ENABLE_EMMC_POWER_SAVING_MODE) && ENABLE_EMMC_POWER_SAVING_MODE ++ eMMC_Prepare_Power_Saving_Mode_Queue(); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ switch(u16_PartType) ++ { ++ case eMMC_PART_BL: ++ u32_StartSector += BL_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_OTP: ++ u32_StartSector += OTP_BLK_OFFSET; ++ break; ++ ++ case eMMC_PART_SECINFO: ++ u32_StartSector += SecInfo_BLK_OFFSET; ++ break; ++ ++ default: ++ return eMMC_ST_SUCCESS; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SecAddr: %Xh, SecCnt: %Xh\n", u32_StartSector, u32_SectorCnt); ++ ++ if(eMMC_BOOT_PART_W == u8_OP) ++ return eMMC_WriteBootPart(pDataBuf, ++ u32_SectorCnt< ++#include ++#include ++ ++#include "mstar_mci.h" ++#include "linux/mmc/card.h" ++#include "ms_platform.h" ++ ++/****************************************************************************** ++ * Defines ++ ******************************************************************************/ ++#define MCI_RETRY_CNT_CMD_TO 100 ++#define MCI_RETRY_CNT_CRC_ERR 200 // avoid stack overflow ++#define MCI_RETRY_CNT_OK_CLK_UP 10 ++/****************************************************************************** ++ * Function Prototypes ++ ******************************************************************************/ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st); ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st); ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st); ++#endif ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st); ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st); ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st); ++static u32 mstar_mci_WaitD0High(u32 u32_us); ++static U32 u32_ok_cnt=0; ++ ++static U32 MIU0_BUS_ADDR=0; ++/***************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++/* MSTAR Multimedia Card Interface Operations */ ++static const struct mmc_host_ops sg_mstar_mci_ops = ++{ ++ .request = mstar_mci_request, ++ .set_ios = mstar_mci_set_ios, ++ .get_ro = mstar_mci_get_ro, ++}; ++ ++/****************************************************************************** ++ * Functions ++ ******************************************************************************/ ++ ++static int mstar_mci_get_dma_dir(struct mmc_data *data) ++{ ++ if (data->flags & MMC_DATA_WRITE) ++ return DMA_TO_DEVICE; ++ else ++ return DMA_FROM_DEVICE; ++} ++ ++static void mstar_mci_pre_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct scatterlist *pSG_st = 0; ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ u32 u32_dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ pSG_st = &pData_st->sg[0]; ++ dmaaddr = (u32)sg_dma_address(pSG_st); ++ u32_dmalen = sg_dma_len(pSG_st); ++ u32_dmalen = ((u32_dmalen&0x1FF)?1:0) + u32_dmalen/512; ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_R_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ eMMC_FCIE_FifoClkRdy(0); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++} ++ ++ ++static U32 mstar_mci_post_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ int err = eMMC_ST_SUCCESS; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ pSG_st = &(pData_st->sg[0]); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ return err; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ // [WHY] not dma_map_sg ? ++ for(i=1; isg_len; i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ pSG_st = &(pData_st->sg[i]); ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT,(dmalen/512)); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, ++ eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ goto dma_read_end; ++ ++ } ++ pData_st->bytes_xfered += pSG_st->length; ++ } ++ ++ dma_read_end: ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ if( !err ) // success ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++ return err; ++} ++ ++static U32 mstar_mci_dma_write(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, BITS_8_W_TOGGLE_CNT); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ ++ for(i=0; isg_len; i++) ++ { ++ pSG_st = &(pData_st->sg[i]); ++ ++ dmaaddr = sg_dma_address(pSG_st); ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ dmalen = sg_dma_len(pSG_st); ++ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, (dmalen >> eMMC_SECTOR_BYTECNT_BITS)); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, (dmaaddr & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, (dmaaddr >> 16)); ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ if(0==i) ++ eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END, ++ eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ ++ } ++ pData_st->bytes_xfered += pSG_st->length; ++ } ++ dma_write_end: ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ ++ if( !err ) ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++ return err; ++ ++} ++ ++ ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ u16 u16_st, u16_i; ++ u8 *pTemp; ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ static u32 u32_retry_cnt=0, u32_run_cnt=0; ++ ++ u32_run_cnt++; ++ // ---------------------------------- ++ // retrun response from FCIE to mmc driver ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3 - (u16_i % 4)) + (4 * (u16_i / 4))] = ++ (u8)(REG_FCIE(FCIE1_BASE+(((u16_i+1)/2)*4)) >> (8*((u16_i+1)%2))); ++ } ++ #if 0 ++ eMMC_debug(0,0,"------------------\n"); ++ eMMC_dump_mem(pTemp, 0x10); ++ eMMC_debug(0,0,"------------------\n"); ++ #endif ++ ++ // ---------------------------------- ++ u16_st = REG_FCIE(FCIE_SD_STATUS); ++ if((u16_st & BIT_SD_FCIE_ERR_FLAGS) || (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ if((u16_st & BIT_SD_RSP_CRC_ERR) && !(mmc_resp_type(pCmd_st) & MMC_RSP_CRC)) ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ else ++ { ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: ST:%Xh, CMD:%u, retry: %u, flag: %Xh, R1 err: %Xh\n", ++ u16_st, pCmd_st->opcode, u32_retry_cnt, g_eMMCDrv.u32_DrvFlag, ++ pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY); ++ ++ u32_ok_cnt = 0; ++ if(u32_retry_cnt++ >= MCI_RETRY_CNT_CRC_ERR) ++ eMMC_FCIE_ErrHandler_Stop(); // fatal error ++ ++ if(25==pCmd_st->opcode || 12==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_hw_timer_sleep(1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ ++ if(0 != pCmd_st->data) ++ { ++ eMMC_FCIE_ErrHandler_Retry(); // slow dwon clock ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ } ++ else // for CMD12 ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: no data, just reset eMMC. \n"); ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ if(0==u32_retry_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: retry ok \n"); ++ return; ++ } ++ ++ //----------------------------------------- ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: ST:%Xh, CMD:%u, retry:%u \n", ++ u16_st, pCmd_st->opcode, pCmd_st->retries); ++ #endif ++ ++ ++ if(u16_st & (BIT_SD_RSP_TIMEOUT | BIT_SD_W_FAIL)) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ } ++ else if(u16_st & (BIT_SD_RSP_CRC_ERR | BIT_SD_R_CRC_ERR | BIT_SD_W_CRC_ERR)) ++ { ++ pCmd_st->error = -EILSEQ; ++ } ++ else ++ { ++ pCmd_st->error = -EIO; ++ } ++ } ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ ++ if((pCmd_st->opcode == 17) || (pCmd_st->opcode == 18) //read ++ ||(pCmd_st->opcode == 24) || (pCmd_st->opcode == 25) //write ++ ||(pCmd_st->opcode == 12)) //stop transmission ++ { ++ if(pCmd_st->resp[0] & eMMC_ERR_R1_31_0) ++ { ++ pCmd_st->error |= -EIO; ++ ++ if(pCmd_st->opcode == 12) ++ eMMC_debug(0,0, "eMMC Warn: CMD12 R1 error: %Xh \n", ++ pCmd_st->resp[0]); ++ else ++ eMMC_debug(0,0, "eMMC Warn: CMD%u R1 error: %Xh, arg %08x, blocks %08x\n", ++ pCmd_st->opcode, pCmd_st->resp[0], pCmd_st->arg, pCmd_st->data->blocks); ++ } ++ } ++ ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++} ++ ++ ++#define WAIT_D0H_POLLING_TIME HW_TIMER_DELAY_500us ++u32 mstar_mci_WaitD0High(u32 u32_us) ++{ ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // enable busy int ++ REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_BUSY_DET_ON); ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_SD_BUSY_END); ++ #endif ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_BUSY_END,u32_us) != eMMC_ST_SUCCESS) ++ { ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ return eMMC_ST_SUCCESS; ++ #else ++ u32 u32_cnt, u32_wait; ++ ++ for(u32_cnt=0; u32_cnt HW_TIMER_DELAY_1ms) ++ { ++ msleep(1); ++ u32_cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ #endif ++} ++ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st) ++{ ++ struct mmc_data *pData_st; ++ u32 u32_mie_int=0, u32_sd_ctl=0, u32_sd_mode; ++ u8 u8_retry_cmd=0, u8_retry_D0H=0; ++ u8 u8_retry_data=0; ++ u32 err = 0; ++ ++ LABEL_SEND_CMD: ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ u32_sd_mode = g_eMMCDrv.u16_Reg10_Mode; ++ pMStarHost_st->cmd = pCmd_st; ++ pData_st = pCmd_st->data; ++ ++ ++ eMMC_FCIE_ClearEvents(); ++ if(12!=pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(HW_TIMER_DELAY_500ms)) ++ { ++ u32_ok_cnt = 0; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ u8_retry_D0H++; ++ if(u8_retry_D0H < 10) ++ { ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ } ++ if(u8_retry_D0H) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: wait D0 H [ok]\n"); ++ u8_retry_D0H = 0; ++ } ++ ++ ++ if(pData_st) ++ { ++ pData_st->bytes_xfered = 0; ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE|(u16)pData_st->blksz); ++ ++ if (pData_st->flags & MMC_DATA_READ) ++ { ++ u32_sd_ctl |= BIT_SD_DAT_EN; ++ ++ // Enable stoping read clock when using scatter list DMA ++ if((pData_st->sg_len > 1) && (pCmd_st->opcode == 18)) ++ u32_sd_mode |= BIT_SD_DMA_R_CLK_STOP; ++ else ++ u32_sd_mode &= ~BIT_SD_DMA_R_CLK_STOP; ++ ++ mstar_mci_pre_dma_read(pMStarHost_st); ++ } ++ } ++ ++ u32_sd_ctl |= BIT_SD_CMD_EN; ++ u32_mie_int |= BIT_SD_CMD_END; ++ REG_FCIE_W(FCIE_CIFC_ADDR(0), (((pCmd_st->arg >> 24)<<8) | (0x40|pCmd_st->opcode))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), ((pCmd_st->arg & 0xFF00) | ((pCmd_st->arg>>16)&0xFF))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), (pCmd_st->arg & 0xFF)); ++ ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_NONE) ++ { ++ u32_sd_ctl &= ~BIT_SD_RSP_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 0); ++ } ++ else ++ { ++ u32_sd_ctl |= BIT_SD_RSP_EN; ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_R2) ++ { ++ u32_sd_ctl |= BIT_SD_RSPR2_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 16); /* (136-8)/8 */ ++ } ++ else ++ { ++ REG_FCIE_W(FCIE_RSP_SIZE, 5); /*(48-8)/8 */ ++ } ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC: INT_EN: %Xh\n", u32_mie_int); ++ REG_FCIE_W(FCIE_MIE_INT_EN, u32_mie_int); ++ #endif ++ ++ #if 0 ++ eMMC_debug(0,0,"\n"); ++ eMMC_debug(0,0,"cmd:%u, arg:%Xh, databuf:%Xh\n", ++ pCmd_st->opcode, pCmd_st->arg, (u32)pData_st); ++ //while(1); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_MODE, u32_sd_mode); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl); ++ // [FIXME]: retry and timing, and omre... ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, ++ HW_TIMER_DELAY_1s) != eMMC_ST_SUCCESS|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ // ------------------------------------ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if(NULL==pData_st) // no data, no retry ++ { ++ mstar_mci_completed_command(pMStarHost_st); ++ return; ++ } ++ #endif ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: cmd.%u arg.%Xh, retry %u \n", ++ pCmd_st->opcode, pCmd_st->arg, u8_retry_cmd); ++ ++ if(u8_retry_cmd < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_cmd++; ++ if(12==pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS !=mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ #endif ++ return; ++ } ++ if(25==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ if(u8_retry_cmd) ++ eMMC_debug(0,0,"eMMC: CMD retry ok\n"); ++ ++ if(pData_st) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pMStarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ ++ err = mstar_mci_post_dma_read(pMStarHost_st); ++ } ++ if( err ) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ } ++ ++ } ++ else ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd without data ++ ++ if( pCmd_st->opcode == 23 ) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); // CMD18 or CMD25 ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++} ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st) ++{ ++ struct mstar_mci_host *pMStarHost_st; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ if (!pMRQ_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMRQ_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ ++ pMStarHost_st->request = pMRQ_st; ++ ++ // --------------------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ eMMC_Init_Device(); ++ } ++ ++ ++ if(NULL == pMStarHost_st->request->cmd->data && 6 != pMStarHost_st->request->cmd->opcode) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ if(6 == pMStarHost_st->request->cmd->opcode && ++ (((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB70000)|| ++ ((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB90000))) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ #endif ++ // --------------------------------------------- ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ ++} ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ u16 au16_cifc[32], u16_i; ++ u8 *pTemp; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != eMMC_ReturnRsp((u8*)au16_cifc, (u8)pCmd_st->opcode)) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ //eMMC_debug(0,0,"eMMC Info: no rsp\n"); ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3-(u16_i%4)) + 4*(u16_i/4)] = ++ (u8)(au16_cifc[(u16_i+1)/2] >> 8*((u16_i+1)%2)); ++ } ++ #if 0 ++ eMMC_debug(0,1,"------------------\n"); ++ eMMC_dump_mem((u8*)&(pCmd_st->resp[0]), 0x10); ++ eMMC_debug(0,1,"------------------\n"); ++ #endif ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++} ++#endif ++ ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st) ++{ ++ /* Define Local Variables */ ++ struct mstar_mci_host *pMStarHost_st; ++ ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ goto LABEL_END; ++ } ++ if (!pIOS_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pIOS_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "eMMC: clock: %u, bus_width %Xh \n", ++ // pIOS_st->clock, pIOS_st->bus_width); ++ ++ // ---------------------------------- ++ if (pIOS_st->clock == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "eMMC Warn: disable clk \n"); ++ eMMC_clock_gating(); ++ } ++ // ---------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ else ++ { eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ } ++ pMStarHost_st->sd_mod = (BIT_SD_DEFAULT_MODE_REG & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ #else ++ // ---------------------------------- ++ else ++ { ++ pMStarHost_st->sd_mod = BIT_SD_DEFAULT_MODE_REG; ++ ++ if(pIOS_st->clock > CLK_400KHz) ++ { ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ else ++ { eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ } ++ ++ if (pIOS_st->bus_width == MMC_BUS_WIDTH_8) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ } ++ else if (pIOS_st->bus_width == MMC_BUS_WIDTH_4) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_4; ++ } ++ else ++ { g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK); ++ } ++ #endif ++ ++ LABEL_END: ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,0,"\n"); ++ ++ ++ ++} ++ ++ ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st) ++{ ++ s32 read_only; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ read_only = 0; ++ if(!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ read_only = -EINVAL; ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return read_only; ++} ++ ++ ++//======================================================================= ++static void mstar_mci_enable(struct mstar_mci_host *pMStarHost_st) ++{ ++ u32 u32_err; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ eMMC_PlatformInit(); ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ ++ u32_err = eMMC_FCIE_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Init fail: %Xh \n", u32_err); ++} ++ ++static void mstar_mci_disable(struct mstar_mci_host *pMStarHost_st) ++{ ++ u32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Reset fail: %Xh\n", u32_err); ++ eMMC_clock_gating(); ++} ++ ++static s32 mstar_mci_probe(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ ++ int irq = 0; ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pMStarHost_st; ++ s32 s32_ret; ++ ++ // -------------------------------- ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pDev_st is NULL \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ irq = irq_of_parse_and_map(pDev_st->dev.of_node, 0); ++ if (!irq) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: irq_of_parse_and_map error!! \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st = 0; ++ pMStarHost_st = 0; ++ s32_ret = 0; ++ g_eMMCDrv.u8_PadType = FCIE_DEFAULT_PAD; ++ g_eMMCDrv.u16_ClkRegVal = FCIE_SLOWEST_CLK; ++ // -------------------------------- ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ mstar_mci_enable(pMStarHost_st); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ pMMCHost_st = mmc_alloc_host(sizeof(struct mstar_mci_host), &pDev_st->dev); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: mmc_alloc_host fail \n"); ++ s32_ret = -ENOMEM; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st->ops = &sg_mstar_mci_ops; ++ // [FIXME]-> ++ pMMCHost_st->f_min = CLK_400KHz; ++ pMMCHost_st->f_max = CLK_200MHz; ++ pMMCHost_st->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | \ ++ MMC_VDD_31_32 | MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; ++ ++ pMMCHost_st->max_blk_count = BIT_SD_JOB_BLK_CNT_MASK; ++ pMMCHost_st->max_blk_size = 512; /* sector */ ++ pMMCHost_st->max_req_size = pMMCHost_st->max_blk_count * pMMCHost_st->max_blk_size; ++ ++ pMMCHost_st->max_seg_size = pMMCHost_st->max_req_size; ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,20) ++ pMMCHost_st->max_phys_segs = 128; ++ pMMCHost_st->max_hw_segs = 128; ++ #else ++ pMMCHost_st->max_segs = 128; ++ #endif ++ //--------------------------------------- ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ pMStarHost_st->mmc = pMMCHost_st; ++ //--------------------------------------- ++ ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_NONREMOVABLE; ++ ++ #if defined(DDR_MODE_ENABLE) && DDR_MODE_ENABLE ++ pMMCHost_st->caps |= MMC_CAP_1_8V_DDR; ++ #endif ++ ++ ++ pMStarHost_st->baseaddr = (void __iomem *)FCIE0_BASE; ++ // <-[FIXME] ++ ++ strcpy(pMStarHost_st->name,MSTAR_MCI_NAME); ++ ++ mmc_add_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, pMMCHost_st); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ s32_ret = request_irq(irq, eMMC_FCIE_IRQ, IRQF_SHARED, DRIVER_NAME, pMStarHost_st); ++ if (s32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: request_irq fail \n"); ++ mmc_free_host(pMMCHost_st); ++ goto LABEL_END; ++ } ++ #endif ++ ++ LABEL_END: ++ return s32_ret; ++} ++ ++static s32 __exit mstar_mci_remove(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pMStarHost_st; ++ s32 s32_ret; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ s32_ret = 0; ++ ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pDev_st is NULL\n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pMMCHost_st is NULL\n"); ++ s32_ret= -1; ++ goto LABEL_END; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove +\n"); ++ ++ mmc_remove_host(pMMCHost_st); ++ ++ mstar_mci_disable(pMStarHost_st); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ free_irq(pMStarHost_st->irq, pMStarHost_st); ++ #endif ++ ++ mmc_free_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, NULL); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove -\n"); ++ ++ LABEL_END: ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return s32_ret; ++} ++ ++ ++#ifdef CONFIG_PM ++static s32 mstar_mci_suspend(struct platform_device *pDev_st, pm_message_t state) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ if (pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend + \n"); ++ ret = mmc_suspend_host(pMMCHost_st); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend -, %Xh\n", ret); ++ return ret; ++} ++ ++extern U8 gu8_NANDeMMC_need_preset_flag; ++static s32 mstar_mci_resume(struct platform_device *pDev_st) ++{ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ ++ //only for Cedric xxxxx ++ gu8_NANDeMMC_need_preset_flag = 1; ++ ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ mstar_mci_enable(mmc_priv(pMMCHost_st)); ++ ++ if (pMMCHost_st) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume +\n"); ++ ret = mmc_resume_host(pMMCHost_st); ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume -, %Xh\n", ret); ++ return ret; ++} ++#endif /* End ifdef CONFIG_PM */ ++ ++static const struct of_device_id ms_emmc_of_match_table[] = { ++ { .compatible = "mstar,emmc-chicago" }, ++ {} ++}; ++ ++/****************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++static struct platform_driver sg_mstar_mci_driver = ++{ ++ .probe = mstar_mci_probe, ++ .remove = __exit_p(mstar_mci_remove), ++ ++ #ifdef CONFIG_PM ++ .suspend = mstar_mci_suspend, ++ .resume = mstar_mci_resume, ++ #endif ++ ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_emmc_of_match_table), ++ }, ++}; ++ ++//static struct platform_device sg_mstar_emmc_device_st = ++//{ ++// .name = DRIVER_NAME, ++// .id = 0, ++// .resource = NULL, ++// .num_resources = 0, ++//}; ++ ++extern MS_BOOT_DEV_TYPE Chip_Get_Boot_Dev_Type(void); ++extern unsigned long long Chip_MIU_to_Phys(unsigned long long phys); ++ ++/****************************************************************************** ++ * Init & Exit Modules ++ ******************************************************************************/ ++static s32 __init mstar_mci_init(void) ++{ ++ int err = 0; ++ ++ if(MS_BOOT_DEV_EMMC!=Chip_Get_Boot_Dev_Type()) ++ { ++ pr_info("[eMMC] skipping device initialization\n"); ++ return -1; ++ } ++ ++ MIU0_BUS_ADDR=Chip_MIU_to_Phys(0);//get the MIU0 base; ++ ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"\n"); ++ ++// if((err = platform_device_register(&sg_mstar_emmc_device_st)) < 0) ++// eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ if((err = platform_driver_register(&sg_mstar_mci_driver)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ return err; ++} ++ ++static void __exit mstar_mci_exit(void) ++{ ++ platform_driver_unregister(&sg_mstar_mci_driver); ++} ++ ++ ++bool mstar_mci_is_mstar_host(struct mmc_card* card) ++{ ++ struct mstar_mci_host *mci_host; ++ ++ if( NULL==(card) ++ || NULL==(card->host) ++ || NULL==(mci_host=((struct mstar_mci_host *)card->host->private) ) ++ || 0!=strncmp(mci_host->name,MSTAR_MCI_NAME,strlen(MSTAR_MCI_NAME)) ++ ) ++ { ++ return false; ++ } ++ else ++ { ++ return true; ++ } ++ ++} ++ ++subsys_initcall(mstar_mci_init); ++//module_init(mstar_mci_init); ++module_exit(mstar_mci_exit); +diff --git a/drivers/mstar/emmc/chicago/mstar_mci.h b/drivers/mstar/emmc/chicago/mstar_mci.h +new file mode 100644 +index 00000000..a5b87437 +--- /dev/null ++++ b/drivers/mstar/emmc/chicago/mstar_mci.h +@@ -0,0 +1,60 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef MSTAR_MCI_H ++#define MSTAR_MCI_H ++ ++#include "eMMC.h" ++ ++/****************************************************************************** ++* Function define for this driver ++******************************************************************************/ ++ ++/****************************************************************************** ++* Register Address Base ++******************************************************************************/ ++#define CLK_400KHz 400*1000 ++#define CLK_200MHz 200*1000*1000 ++ ++#define eMMC_GENERIC_WAIT_TIME (HW_TIMER_DELAY_1s*3) ++#define eMMC_READ_WAIT_TIME (HW_TIMER_DELAY_500ms) ++ ++/****************************************************************************** ++* Low level type for this driver ++******************************************************************************/ ++struct mstar_mci_host ++{ ++ struct mmc_host *mmc; ++ struct mmc_command *cmd; ++ struct mmc_request *request; ++ ++ void __iomem *baseaddr; ++ s32 irq; ++ ++ u16 sd_clk; ++ u16 sd_mod; ++ ++ /* Flag indicating when the command has been sent. */ ++ /* This is used to work out whether or not to send the stop */ ++ u32 flags; ++ u32 present; ++ char name[16]; ++}; /* struct mstar_mci_host*/ ++ ++ ++#define MSTAR_MCI_NAME "MSTAR_MCI" ++#endif +diff --git a/drivers/mstar/emmc/unify_driver/Makefile b/drivers/mstar/emmc/unify_driver/Makefile +new file mode 100644 +index 00000000..8ceaa6b6 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/Makefile +@@ -0,0 +1,26 @@ ++# ++# Makefile for MStar eMMC host drivers. ++# ++obj-$(CONFIG_MS_EMMC) += kdrv_emmc.o ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/unify_driver/inc/api/ ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/unify_driver/inc/common/ ++EXTRA_CFLAGS += -Idrivers/mstar/emmc/unify_driver/inc/config/ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ifndef CONFIG_ARM_LPAE ++#EXTRA_CFLAGS += -Werror ++endif ++ ++# specific options ++ ++# files ++kdrv_emmc-y += src/api/eMMC_prg.o ++kdrv_emmc-y += src/common/eMMC_hal_speed.o ++kdrv_emmc-y += src/common/eMMC_hal_v5.o ++kdrv_emmc-y += mstar_mci_v5.o ++ ++kdrv_emmc-y += src/common/eMMC_ip_verify.o ++kdrv_emmc-y += src/common/eMMC_utl.o ++kdrv_emmc-y += src/config/eMMC_platform.o ++ +diff --git a/drivers/mstar/emmc/unify_driver/inc/api/drv_eMMC.h b/drivers/mstar/emmc/unify_driver/inc/api/drv_eMMC.h +new file mode 100644 +index 00000000..cf1e32b7 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/api/drv_eMMC.h +@@ -0,0 +1,186 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef __DRV_eMMC_H__ ++#define __DRV_eMMC_H__ ++ ++ ++/*=============================================================*/ ++// Include files ++/*=============================================================*/ ++#include "../config/eMMC_config.h" ++ ++/*=============================================================*/ ++// Extern definition ++/*=============================================================*/ ++typedef struct _eMMC_INFO ++{ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ ++ U16 u16_ECCCodeByteCnt; ++ U16 u16_PageSectorCnt; ++ U8 u8_WordMode; ++ ++} eMMC_INFO_t; ++ ++typedef struct _eMMC_CIS { ++ ++ U8 au8_eMMC_nni[512]; ++ U8 au8_eMMC_pni[512]; ++ ++} eMMC_CIS_t; ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Variable definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++extern U32 eMMC_Init(void); ++extern U32 eMMC_Init_Device(void); ++extern U32 eMMC_Init_Device_Ex(void); ++extern U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt); ++//-------------------------------------------- ++// CAUTION: u32_DataByteCnt has to be 512B x n ++//-------------------------------------------- ++extern U32 eMMC_WriteData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_ReadData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++// skip driver-reserved area ++extern U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr); ++extern U32 eMMC_GetCapacity(U32 *pu32_TotalSectorCnt); // 1 sector = 512B ++extern U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++//-------------------------------------------- ++extern U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID); ++ ++extern U32 eMMC_EraseAll(void); ++ ++extern U32 eMMC_GetExtCSD(U8* pu8_Ext_CSD); ++extern U32 eMMC_SetExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++ ++/*=============================================================*/ ++// internal function definition ++/*=============================================================*/ ++extern U32 eMMC_ReadBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo); ++extern U32 eMMC_CheckIfReady(void); ++extern void eMMC_ResetReadyFlag(void); ++extern void eMMC_DumpDriverStatus(void); ++extern void eMMC_DumpSpeedStatus(void); ++extern U32 eMMC_FCIE_BuildDDRTimingTable(void); ++extern U32 eMMC_FCIE_BuildHS200TimingTable(void); ++extern void eMMC_FCIE_SetSkew4Value(U32 u32Value); ++extern void eMMC_FCIE_SetDelayLatch(U32 u32Value); ++extern U32 eMMC_SetEnhanceUserPartition(U32 u32_StartAddr,U32 u32_Size,U8 u8_EnAttr, U8 u8_RelW); ++extern U32 eMMC_SetGPPartition(U8 u8_PartNo,U32 u32_PartSize,U8 u8_EnAttr,U8 u8_ExtAttr, U8 u8_RelW); ++extern U32 eMMC_SetPartitionComplete(void); ++extern U32 eMMC_ReadGPPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern U32 eMMC_WriteGPPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo); ++extern void eMMC_PrintGPPartition(void); ++ ++//-------------------------------------------- ++ #if defined(eMMC_DRV_G2P_UBOOT) && eMMC_DRV_G2P_UBOOT ++extern U32 eMMC_SearchDevNodeStartSector(void); ++ #endif ++//-------------------------------------------- ++ ++#endif //__DRV_eMMC_H__ ++ +diff --git a/drivers/mstar/emmc/unify_driver/inc/common/eMMC.h b/drivers/mstar/emmc/unify_driver/inc/common/eMMC.h +new file mode 100644 +index 00000000..624eec21 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/common/eMMC.h +@@ -0,0 +1,554 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef eMMC_DRIVER_H ++#define eMMC_DRIVER_H ++ ++//===================================================================================== ++#include "../config/eMMC_config.h" // [CAUTION]: edit eMMC_config.h for your platform ++//===================================================================================== ++#include "eMMC_err_codes.h" ++ ++#define eMMC_DRIVER_VERSION 3 // used to sync with other SW stages (e.g. MBoot) ++ ++//=========================================================== ++// debug macro ++//=========================================================== ++extern U32 gu32_eMMCDrvExtFlag; ++ ++#define eMMCDRV_EXTFLAG_DISABLE_LOG BIT0 ++#define eMMC_DISABLE_LOG(yes) \ ++ do{ \ ++ if(yes) gu32_eMMCDrvExtFlag |= eMMCDRV_EXTFLAG_DISABLE_LOG; \ ++ else gu32_eMMCDrvExtFlag &= ~eMMCDRV_EXTFLAG_DISABLE_LOG;\ ++ }while(0); ++#define eMMC_IF_DISABLE_LOG() \ ++ (gu32_eMMCDrvExtFlag & eMMCDRV_EXTFLAG_DISABLE_LOG) ++ ++#define eMMCDRV_EXTFLAG_BKG_SCAN BIT1 // for Irwin ++#define eMMC_SET_BKG_SCAN_HS200() gu32_eMMCDrvExtFlag |= eMMCDRV_EXTFLAG_BKG_SCAN; ++#define eMMC_CLR_BKG_SCAN_HS200() gu32_eMMCDrvExtFlag &= ~eMMCDRV_EXTFLAG_BKG_SCAN; ++#define eMMC_CHK_BKG_SCAN_HS200() (gu32_eMMCDrvExtFlag & eMMCDRV_EXTFLAG_BKG_SCAN) ++ ++ ++//=========================================================== ++// macro for Spec. ++//=========================================================== ++#define ADDRESSING_MODE_BYTE 1 // 1 byte ++#define ADDRESSING_MODE_SECTOR 2 // 512 bytes ++#define ADDRESSING_MODE_4KB 3 // 4KB bytes ++ ++#define eMMC_DEVTYPE_HS400_1_8V BIT6 // ECSD[196] ++#define eMMC_DEVTYPE_HS200_1_8V BIT4 ++#define eMMC_DEVTYPE_DDR BIT2 ++#define eMMC_DEVTYPE_ALL (eMMC_DEVTYPE_HS400_1_8V|eMMC_DEVTYPE_HS200_1_8V|eMMC_DEVTYPE_DDR) ++ ++#define eMMC_SPEED_OLD 0 // ECSD[185] ++#define eMMC_SPEED_HIGH 1 ++#define eMMC_SPEED_HS200 2 ++#define eMMC_SPEED_HS400 3 ++ ++#define eMMC_DRIVING_TYPE0 0 // x1 ++#define eMMC_DRIVING_TYPE1 1 // x1.5 ++#define eMMC_DRIVING_TYPE2 2 // x0.75 ++#define eMMC_DRIVING_TYPE3 3 // x0.5 ++#define eMMC_DRIVING_TYPE4 4 // x1.2 ++ ++#define eMMC_FLAG_TRIM BIT0 ++#define eMMC_FLAG_HPI_CMD12 BIT1 ++#define eMMC_FLAG_HPI_CMD13 BIT2 ++ ++#define eMMC_PwrOffNotif_OFF 0 ++#define eMMC_PwrOffNotif_ON 1 ++#define eMMC_PwrOffNotif_SHORT 2 ++#define eMMC_PwrOffNotif_LONG 3 ++ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++#define eMMC_SECTOR_512BYTE 0x200 ++#define eMMC_SECTOR_512BYTE_BITS 9 ++#define eMMC_SECTOR_512BYTE_MASK (eMMC_SECTOR_512BYTE-1) ++ ++#define eMMC_SECTOR_BUF_16KB (eMMC_SECTOR_512BYTE * 0x20) ++ ++#define eMMC_SECTOR_BYTECNT eMMC_SECTOR_512BYTE ++#define eMMC_SECTOR_BYTECNT_BITS eMMC_SECTOR_512BYTE_BITS ++//------------------------------------------------------- ++ ++#define eMMC_ExtCSD_SetBit 1 ++#define eMMC_ExtCSD_ClrBit 2 ++#define eMMC_ExtCSD_WByte 3 ++ ++#define eMMC_CMD_BYTE_CNT 5 ++#define eMMC_R1_BYTE_CNT 5 ++#define eMMC_R1b_BYTE_CNT 5 ++#define eMMC_R2_BYTE_CNT 16 ++#define eMMC_R3_BYTE_CNT 5 ++#define eMMC_R4_BYTE_CNT 5 ++#define eMMC_R5_BYTE_CNT 5 ++#define eMMC_MAX_RSP_BYTE_CNT eMMC_R2_BYTE_CNT ++ ++//=========================================================== ++// Partition Info parameters ++//=========================================================== ++ ++// internal data Sector Address ++#define eMMC_ID_BYTE_CNT 15 ++#define eMMC_ID_FROM_CID_BYTE_CNT 10 ++#define eMMC_ID_DEFAULT_BYTE_CNT 11 // last byte means n GB ++ ++typedef eMMC_PACK0 struct _eMMC_NNI { ++ ++ U8 au8_Tag[16]; ++ U8 u8_IDByteCnt; ++ U8 au8_ID[15]; ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U32 u32_Config; ++ U16 u16_ECCType; ++ U16 u16_SeqAccessTime; ++ U8 au8_padding[12]; ++ U8 au8_Vendor[16]; ++ U8 au8_PartNumber[16]; ++ U8 u8_PairPageMapLoc; ++ U8 u8_PairPageMapType; ++ ++} eMMC_PACK1 eMMC_NNI_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PARTITION_RECORD { ++ ++ U16 u16_StartBlk; // the start block index, reserved for UNFD internal use. ++ U16 u16_BlkCnt; // project team defined ++ U16 u16_PartType; // project team defined, e.g. eMMC_PART_XXX_0 ++ U16 u16_BackupBlkCnt; // reserved good blocks count for backup, UNFD internal use. ++ // e.g. u16BackupBlkCnt = u16BlkCnt * 0.03 + 2 ++} eMMC_PACK1 eMMC_PARTITION_RECORD_t, *P_eMMC_PARTITION_RECORD_t; ++ ++ ++typedef eMMC_PACK0 struct _eMMC_PNI { ++ ++ U32 u32_ChkSum; ++ U16 u16_SpareByteCnt; ++ U16 u16_PageByteCnt; ++ U16 u16_BlkPageCnt; ++ U16 u16_BlkCnt; ++ U16 u16_PartCnt; ++ U16 u16_UnitByteCnt; ++ eMMC_PARTITION_RECORD_t records[]; ++ ++} eMMC_PACK1 eMMC_PNI_t; ++ ++ ++// Logical Disk Info ++typedef struct _eMMC_DISK_INFO { ++ ++ U32 u32_StartSector; ++ U32 u32_SectorCnt; ++ ++} eMMC_DISK_INFO_t, *P_eMMC_DISK_INFO_t; ++ ++//=========================================================== ++// DDR Timing Table ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_PARAM { ++ ++ U8 u8_DQS, u8_Cell; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_PARAM_t; ++ ++#if 0 ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_WINDOW { ++ ++ U8 u8_Cnt; ++ // DQS uses index, not reg value (see code) ++ eMMC_FCIE_DDRT_PARAM_t aParam[2]; ++ U8 au8_DQSTryCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MODE_SHIFT)+1]; ++ U8 au8_DQSValidCellCnt[(BIT_DQS_MODE_MASK>>BIT_DQS_MODE_SHIFT)+1]; ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_WINDOW_t; ++#endif ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_SET { ++ ++ U8 u8_Clk; ++ eMMC_FCIE_DDRT_PARAM_t Param; // register values ++ ++} eMMC_PACK1 eMMC_FCIE_DDRT_SET_t; ++ ++ ++#define eMMC_FCIE_DDRT_SET_CNT 12 ++ ++#define eMMC_TIMING_SET_MAX 0 ++#define eMMC_TIMING_SET_MIN 1 ++ ++// ---------------------------------------------- ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_TABLE { ++ ++ U8 u8_SetCnt, u8_CurSetIdx; ++ ++ #if !(defined(ENABLE_eMMC_ATOP) && ENABLE_eMMC_ATOP) ++ // DDR48 (digital macro) ++ eMMC_FCIE_DDRT_SET_t Set[eMMC_FCIE_DDRT_SET_CNT]; ++ #else ++ // ATOP (for DDR52, HS200, HS400) ++ eMMC_FCIE_ATOP_SET_t Set[1];//eMMC_FCIE_VALID_CLK_CNT]; ++ #endif ++ ++ U32 u32_ChkSum; // put in the last ++ U32 u32_VerNo; // for auto update ++ ++} eMMC_PACK1 eMMC_FCIE_TIMING_TABLE_t; ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_DDRT_EXT_TABLE { //temp solution for monaco U02 HS400 ++ eMMC_FCIE_ATOP_SET_EXT_t Set; ++ U32 u32_ChkSum; // put in the last ++ U32 u32_VerNo; // for auto update ++} eMMC_PACK1 eMMC_FCIE_TIMING_EXT_TABLE_t; ++ ++#define REG_OP_W 1 ++#define REG_OP_CLRBIT 2 ++#define REG_OP_SETBIT 3 ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_REG_SET { //total 10 bytes ++ U32 u32_RegAddress; //(BANK_ADDRESS + REGISTER OFFSET ) << 2 ++ U16 u16_RegValue; ++ U16 u16_RegMask; ++ U16 u16_OpCode; ++} eMMC_PACK1 eMMC_FCIE_REG_SET_t; ++ ++typedef eMMC_PACK0 struct _eMMC_FCIE_GEN_TIMING_TABLE { ++ U32 u32_ChkSum; ++ U32 u32_VerNo; // for auto update ++ U32 u32_Clk; ++ U8 u8_SpeedMode; ++ U8 u8_CurSetIdx; ++ U8 u8_RegisterCnt; ++ U8 u8_SetCnt; ++ U8 au8_CID[eMMC_MAX_RSP_BYTE_CNT]; ++ U32 u32_Dummy[6]; //for extension ++ eMMC_FCIE_REG_SET_t RegSet[45]; //at most 45 register set ++} eMMC_PACK1 eMMC_FCIE_GEN_TIMING_TABLE_t; ++ ++#if defined(CONFIG_EMMC_FORCE_DDR52) ++#define eMMC_TIMING_TABLE_VERSION 2 ++#else ++#define eMMC_TIMING_TABLE_VERSION 4 // for CL.731742 & later ++#endif ++#define eMMC_TIMING_TABLE_CHKSUM_OFFSET 8 ++ ++//=========================================================== ++// burst length for write speed ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_FCIE_WLen_TABLE { ++ ++ U16 u16_BestBrustLen, u16_WorstBrustLen; ++ ++ U16 u16_BestMBPerSec, u16_BestMBPerSecPoint; ++ U16 u16_WorstMBPerSec, u16_WorstMBPerSecPoint; ++ ++ U32 u32_ChkSum; // put in the last ++ ++} eMMC_PACK1 eMMC_FCIE_WLen_TABLE_t; ++ ++//=========================================================== ++// Gernel Purpose Partition ++//=========================================================== ++typedef eMMC_PACK0 struct _eMMC_GP_Part{ ++ U32 u32_PartSize; ++ U8 u8_EnAttr; ++ U8 u8_ExtAttr; ++ U8 u8_RelW; ++} eMMC_PACK1 eMMC_GP_Part_t; ++ ++//=========================================================== ++// driver flag (u32_DrvFlag) ++//=========================================================== ++#define DRV_FLAG_INIT_DONE BIT0 // include eMMC identify done ++ ++#define DRV_FLAG_GET_PART_INFO BIT1 ++#define DRV_FLAG_RSP_WAIT_D0H BIT2 // currently only R1b ++ ++#define DRV_FLAG_DDR_MODE BIT3 ++#define DRV_FLAG_TUNING_TTABLE BIT4 // to avoid retry & heavy log ++#define DRV_FLAG_SPEED_MASK (BIT7|BIT6|BIT5) ++#define DRV_FLAG_SPEED_HIGH BIT5 ++#define DRV_FLAG_SPEED_HS200 BIT6 ++#define DRV_FLAG_SPEED_HS400 BIT7 ++#define eMMC_IF_NORMAL_SDR() (0==(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_DDR_MODE)&&\ ++ DRV_FLAG_SPEED_HIGH==(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_MASK)) ++#define eMMC_SPEED_MODE() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_MASK) ++#define eMMC_IF_DDRT_TUNING() (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_TUNING_TTABLE) ++ ++#define DRV_FLAG_PwrOffNotif_MASK (BIT8|BIT9) ++#define DRV_FLAG_PwrOffNotif_OFF 0 ++#define DRV_FLAG_PwrOffNotif_ON BIT8 ++#define DRV_FLAG_PwrOffNotif_SHORT BIT9 ++#define DRV_FLAG_PwrOffNotif_LONG (BIT8|BIT9) ++ ++#define DRV_FLAG_RSPFROMRAM_SAVE BIT10 ++#define DRV_FLAG_ERROR_RETRY BIT11 ++ ++ ++typedef struct _eMMC_DRIVER ++{ ++ U32 u32_ChkSum; // [8th ~ last-512] bytes ++ U8 au8_Sig[4]; // 'e','M','M','C' ++ ++ // ---------------------------------------- ++ // FCIE ++ // ---------------------------------------- ++ U16 u16_RCA; ++ U32 u32_DrvFlag, u32_LastErrCode; ++ U8 au8_Rsp[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CSD[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 au8_CID[eMMC_MAX_RSP_BYTE_CNT]; ++ U8 u8_PadType; ++ U16 u16_Reg10_Mode; ++ U32 u32_ClkKHz; ++ U16 u16_ClkRegVal; ++ eMMC_FCIE_TIMING_TABLE_t TimingTable_t; ++ eMMC_FCIE_TIMING_EXT_TABLE_t TimingTable_Ext_t; ++ eMMC_FCIE_GEN_TIMING_TABLE_t TimingTable_G_t; ++ ++ // ---------------------------------------- ++ // eMMC ++ // ---------------------------------------- ++ // CSD ++ U8 u8_SPEC_VERS; ++ U8 u8_R_BL_LEN, u8_W_BL_LEN; // supported max blk len ++ U16 u16_C_SIZE; ++ U8 u8_TAAC, u8_NSAC, u8_Tran_Speed; ++ U8 u8_C_SIZE_MULT; ++ U8 u8_ERASE_GRP_SIZE, u8_ERASE_GRP_MULT; ++ U8 u8_R2W_FACTOR; ++ ++ U8 u8_IfSectorMode; ++ U32 u32_eMMCFlag; ++ U32 u32_EraseUnitSize; ++ ++ // ExtCSD ++ U32 u32_SEC_COUNT; ++ U32 u32_BOOT_SEC_COUNT; ++ ++ #define BUS_WIDTH_1 1 ++ #define BUS_WIDTH_4 4 ++ #define BUS_WIDTH_8 8 ++ ++ U8 u8_BUS_WIDTH; ++ U8 u8_ErasedMemContent; ++ U16 u16_ReliableWBlkCnt; ++ U8 u8_ECSD185_HsTiming, u8_ECSD192_Ver, u8_ECSD196_DevType, u8_ECSD197_DriverStrength; ++ U8 u8_ECSD248_CMD6TO, u8_ECSD247_PwrOffLongTO, u8_ECSD34_PwrOffCtrl; ++ U8 u8_ECSD160_PartSupField, u8_ECSD224_HCEraseGRPSize, u8_ECSD221_HCWpGRPSize; ++ U8 u8_ECSD159_MaxEnhSize_2, u8_ECSD158_MaxEnhSize_1, u8_ECSD157_MaxEnhSize_0; ++ U8 u8_u8_ECSD155_PartSetComplete, u8_ECSD166_WrRelParam; ++ U8 u8_ECSD184_Stroe_Support; ++ ++ // ---------------------------------------- ++ // CIS ++ // ---------------------------------------- ++ // nni ++ U8 u8_IDByteCnt, au8_ID[eMMC_ID_BYTE_CNT]; ++ U8 au8_Vendor[16], au8_PartNumber[16]; ++ ++ // pni ++ U32 au32_Pad[2]; // don't move ++ ++ U32 u32_PartDevNodeStartSector; ++ U16 u16_PartDevNodeSectorCnt; ++ U32 u32_FATSectorCnt; ++ ++ // ---------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ // rsp from ram ++ U8 au8_AllRsp[eMMC_SECTOR_512BYTE]; // last 4 bytes are CRC ++ #endif ++ ++ // ---------------------- ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ eMMC_FCIE_WLen_TABLE_t BurstWriteLen_t; ++ #endif ++ ++ // ---------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ U32 u32_CNT_CMD17, u32_CNT_CMD24, u32_CNT_CMD18, u32_CNT_CMD25; ++ U64 u64_CNT_TotalRBlk, u64_CNT_TotalWBlk; ++ ++ U32 u32_CNT_MinRBlk, u32_CNT_MinWBlk, u32_CNT_MaxRBlk, u32_CNT_MaxWBlk; ++ U32 u32_RBlk_tmp, u32_WBlk_tmp; ++ U32 au32_CNT_MinRBlk[0x200], au32_CNT_MinWBlk[0x200]; // for blk count < 0x200, how many times ++ ++ U32 u32_Addr_RLast, u32_Addr_WLast; ++ U32 u32_Addr_RHitCnt, u32_Addr_WHitCnt; ++ ++ U32 u32_temp_count; ++ #endif ++ ++ eMMC_GP_Part_t GP_Part[4]; ++ ++ U32 u32_EnUserStartAddr; ++ U32 u32_EnUserSize; ++ U8 u8_EnUserEnAttr; ++ U8 u8_EnUserRelW; ++ ++ //FCIE5 ++ ++ U16 u16_MacroToggleCnt; ++ U16 u16_EmmcPll_IOBusWidth; ++ U16 u16_EmmcPll_DqsPageByteCnt; ++ U8 u8_MacroType; ++ U8 u8_DefaultBusMode; ++ U8 u8_HS400_mode; ++ ++ // misc ++ U8 u8_disable_retry; ++ ++ U8 u8_make_sts_err; ++ ++ #define FCIE_NOT_MAKE_ERR 0 ++ #define FCIE_MAKE_RD_CRC_ERR 1 ++ #define FCIE_MAKE_WR_CRC_ERR 2 ++ #define FCIE_MAKE_WR_TOUT_ERR 3 ++ #define FCIE_MAKE_CMD_NO_RSP 4 ++ #define FCIE_MAKE_CMD_RSP_ERR 5 ++ #define FCIE_MAKE_RD_TOUT_ERR 6 ++ #define FCIE_MAKE_CARD_BUSY 7 ++ ++ U8 u8_check_last_blk_crc; ++ ++} eMMC_DRIVER, *P_eMMC_DRIVER; ++ ++extern eMMC_DRIVER g_eMMCDrv; ++ ++// ADMA Descriptor ++struct _AdmaDescriptor{ ++ U32 u32_End : 1; ++ U32 u32_MiuSel : 2; ++ U32 : 13; ++ U32 u32_JobCnt : 16; ++ U32 u32_Address; ++ U32 u32_DmaLen; ++ U32 u32_Dummy; ++}; ++ ++ ++//=========================================================== ++// exposed APIs ++//=========================================================== ++#include "../api/drv_eMMC.h" ++ ++//=========================================================== ++// internal used functions ++//=========================================================== ++#include "eMMC_utl.h" ++#include "eMMC_hal.h" ++ ++extern U32 eMMC_IPVerify_Main(void); ++extern U32 eMMC_IPVerify_Main_Ex(U32 u32_DataPattern); ++#define eMMC_TEST_READONLY 1 ++#define eMMC_TEST_WRITEONLY 2 ++extern U32 eMMC_IPVerify_WriteOnly(U16 u16_TestPattern); ++extern U32 eMMC_IPVerify_ReadOnly(void); ++extern U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void); ++extern void eMMCTest_DownCount(U32 u32_Sec); ++extern U32 eMMC_IPVerify_Performance(void); ++extern U32 eMMCTest_BlkWRC_ProbeTiming(U32 u32_eMMC_Addr); ++extern U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt); ++extern U32 eMMCTest_Lifetime(U8 u8_TestMode); ++extern U32 eMMCTest_PwrCut_InitData(U8* u8_DataBuf, U32 u32_BlkStartAddr); ++extern U32 eMMCTest_PwrCut_Test(U8* u8_DataBuf, U32 u32_BlkStartAddr); ++extern U32 eMMCTest_PwrCut_Test2(U8* u8_DataBuf, U32 u32_BlkStartAddr); ++//power cut ++extern void eMMC_CheckPowerCut(void); ++extern void eMMC_Prepare_Power_Saving_Mode_Queue(void); ++ ++#define eMMC_LIFETIME_TEST_FIXED 1 ++#define eMMC_LIFETIME_TEST_FILLED 2 ++#define eMMC_LIFETIME_TEST_RANDOM 3 ++ ++extern U32 eMMC_BootMode(void); ++ ++ ++#endif // eMMC_DRIVER_H ++ +diff --git a/drivers/mstar/emmc/unify_driver/inc/common/eMMC_err_codes.h b/drivers/mstar/emmc/unify_driver/inc/common/eMMC_err_codes.h +new file mode 100644 +index 00000000..95d4997f +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/common/eMMC_err_codes.h +@@ -0,0 +1,247 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_ERR_CODES_H__ ++#define __eMMC_ERR_CODES_H__ ++//=========================================================== ++// device status (R1, R1b) ++//=========================================================== ++#define eMMC_R1_ADDRESS_OUT_OF_RANGE BIT31 ++#define eMMC_R1_ADDRESS_MISALIGN BIT30 ++#define eMMC_R1_BLOCK_LEN_ERROR BIT29 ++#define eMMC_R1_ERASE_SEQ_ERROR BIT28 ++#define eMMC_R1_ERASE_PARAM BIT27 ++#define eMMC_R1_WP_VIOLATION BIT26 ++#define eMMC_R1_DEVICE_IS_LOCKED BIT25 ++#define eMMC_R1_LOCK_UNLOCK_FAILED BIT24 ++#define eMMC_R1_COM_CRC_ERROR BIT23 ++#define eMMC_R1_ILLEGAL_COMMAND BIT22 ++#define eMMC_R1_DEVICE_ECC_FAILED BIT21 ++#define eMMC_R1_CC_ERROR BIT20 ++#define eMMC_R1_ERROR BIT19 ++#define eMMC_R1_CID_CSD_OVERWRITE BIT16 ++#define eMMC_R1_WP_ERASE_SKIP BIT15 ++#define eMMC_R1_ERASE_RESET BIT13 ++#define eMMC_R1_CURRENT_STATE (BIT12|BIT11|BIT10|BIT9) ++#define eMMC_R1_READY_FOR_DATA BIT8 ++#define eMMC_R1_SWITCH_ERROR BIT7 ++#define eMMC_R1_EXCEPTION_EVENT BIT6 ++#define eMMC_R1_APP_CMD BIT5 ++ ++#define eMMC_ERR_R1_31_24 (eMMC_R1_ADDRESS_OUT_OF_RANGE| \ ++ eMMC_R1_ADDRESS_MISALIGN| \ ++ eMMC_R1_BLOCK_LEN_ERROR| \ ++ eMMC_R1_ERASE_SEQ_ERROR| \ ++ eMMC_R1_ERASE_PARAM| \ ++ eMMC_R1_WP_VIOLATION| \ ++ eMMC_R1_LOCK_UNLOCK_FAILED) ++#define eMMC_ERR_R1_23_16 (eMMC_R1_COM_CRC_ERROR| \ ++ eMMC_R1_ILLEGAL_COMMAND| \ ++ eMMC_R1_DEVICE_ECC_FAILED| \ ++ eMMC_R1_CC_ERROR| \ ++ eMMC_R1_ERROR| \ ++ eMMC_R1_CID_CSD_OVERWRITE) ++#define eMMC_ERR_R1_15_8 (eMMC_R1_WP_ERASE_SKIP| \ ++ eMMC_R1_ERASE_RESET) ++#define eMMC_ERR_R1_7_0 (eMMC_R1_SWITCH_ERROR) ++ ++#define eMMC_ERR_R1_31_0 (eMMC_ERR_R1_31_24|eMMC_ERR_R1_23_16|eMMC_ERR_R1_15_8|eMMC_ERR_R1_7_0) ++#define eMMC_ERR_R1_NEED_RETRY (eMMC_R1_COM_CRC_ERROR|eMMC_R1_DEVICE_ECC_FAILED|eMMC_R1_CC_ERROR|eMMC_R1_ERROR|eMMC_R1_SWITCH_ERROR) ++//=========================================================== ++// driver error codes ++//=========================================================== ++#define eMMC_ST_SUCCESS 0 ++ ++#define eMMC_ST_ERR_MEM_CORRUPT (0x0001 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_ALIGN (0x0002 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_PACKED (0x0003 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DATA_MISMATCH (0x0004 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAIT_REG0 (0x0005 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY (0x0006 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_MIULASTDONE (0x0007 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITD0HIGH (0x0008 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_CARDDMAEND (0x0009 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT (0x000A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_STS_ERR (0x000B | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_BIST_FAIL (0x0010 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DEBUG_MODE (0x0011 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_CLK (0x0012 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARAMETER (0x0013 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_INIT (0x0014 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INVALID_PARAM (0x0015 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PARTITION_CHKSUM (0x0016 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PART_INFO (0x0017 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_PARTITION (0x0018 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_OK_DDR_PARAM (0x0019 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SAVE_DDRT_FAIL (0x001A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_CHKSUM (0x001B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_DDRT_NONA (0x001C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI (0x001D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI (0x001E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_NNI_NONA (0x001F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CIS_PNI_NONA (0x0020 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SDR_DETECT_DDR (0x0021 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_CIS (0x0022 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NOT_eMMC_PLATFROM (0x0023 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_FCIE_NO_RIU (0x0024 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_INT_TO (0x0025 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_UNKNOWN_CLK (0x0026 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_BUILD_DDRT (0x0027 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_RSP_IN_RAM (0x0028 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_SLOWER_CLK (0x0029 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_PAD_ABNORMAL_OFF (0x0030 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SAVE_BLEN_FAIL (0x0031 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_BLEN_CHKSUM (0x0032 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CHKSUM (0x0033 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ERR_DET (0x0034 | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_CMD1 (0x0A00 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD1_DEV_NOT_RDY (0x0A01 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD2 (0x0A02 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD3_CMD7 (0x0A03 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_31_24 (0x0A04 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_23_16 (0x0A05 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_15_8 (0x0A06 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_R1_7_0 (0x0A07 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_CIFD (0x0A08 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_MIU (0x0A09 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_CIFD (0x0A0A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD17_MIU (0x0A0B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD18 (0x0A0C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6 (0x0A0D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD13 (0x0A0E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD12 (0x0A0F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD (0x0A10 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H (0x0A11 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_CIFD_CHK_R1 (0x0A12 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU (0x0A13 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_WAIT_D0H (0x0A14 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD24_MIU_CHK_R1 (0x0A15 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25 (0x0A16 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_WAIT_D0H (0x0A17 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD25_CHK_R1 (0x0A18 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD9 (0x0A19 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SEC_UPFW_TO (0x0A20 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD16 (0x0A21 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_NO_HS200_1_8V (0x0A22 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_ONE_BIT (0x0A23 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_NO_RSP (0x0A24 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_DATA_CRC (0x0A25 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_NO_DRVING (0x0A26 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_HS200_FAIL (0x0A27 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_DATA_CMP (0x0A28 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD21_NO_HS200_1_8V (0x0A29 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SET_DRV_STRENGTH (0x0A2A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_SKEW4 (0x0A2B | eMMC_ST_PLAT) ++ ++#define eMMC_ST_ERR_CMD8_ECHO (0x0B00 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD8_NO_RSP (0x0B01 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD55_NO_RSP (0x0B02 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD55_RSP_CRC (0x0B03 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD55_APP_CMD_BIT (0x0B04 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD41_DEV_BUSY (0x0B05 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD41_NO_RSP (0x0B06 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD9_CSD_FMT (0x0B07 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD6_NO_RSP (0x0B08 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD6_WRONG_PARA (0x0B09 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD13_NO_RSP (0x0B0A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_ACMD13_DAT_CRC (0x0B0B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_NO_RSP (0x0B0C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_DAT_CRC (0x0B0D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_WRONG_PARA (0x0B0E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_HS_NOT_SRPO (0x0B0F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_SWC_STS_ERR (0x0B10 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD6_SWC_STS_CODE (0x0B11 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_NO_RSP (0x0B12 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_SEQ_ERR (0x0B13 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_PARAM_ERR (0x0B14 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD32_RESET (0x0B15 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_NO_RSP (0x0B16 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_SEQ_ERR (0x0B17 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_PARAM_ERR (0x0B18 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD33_RESET (0x0B19 | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_NO_RSP (0x0B1A | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_SEQ_ERR (0x0B1B | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_PARAM_ERR (0x0B1C | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_RESET (0x0B1D | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_TO (0x0B1E | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD3536_ERR (0x0B1F | eMMC_ST_PLAT) ++#define eMMC_ST_ERR_CMD38_ERR (0x0B20 | eMMC_ST_PLAT) ++ ++ ++#endif /* __eMMC_ERR_CODES_H__ */ +diff --git a/drivers/mstar/emmc/unify_driver/inc/common/eMMC_hal.h b/drivers/mstar/emmc/unify_driver/inc/common/eMMC_hal.h +new file mode 100644 +index 00000000..bab89517 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/common/eMMC_hal.h +@@ -0,0 +1,232 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_HAL_H__ ++#define __eMMC_HAL_H__ ++ ++#include "eMMC.h" ++ ++#define U32BEND2LEND(X) ( ((X&0x000000FF)<<24) + ((X&0x0000FF00)<<8) + ((X&0x00FF0000)>>8) + ((X&0xFF000000)>>24) ) ++#define U16BEND2LEND(X) ( ((X&0x00FF)<<8) + ((X&0xFF00)>>8) ) ++ ++#define _START_TXMIT 0x40 // transmission bit ++ ++#define eMMC_GO_IDLE_STATE (_START_TXMIT+0) ++#define eMMC_SEND_OP_COND (_START_TXMIT+1) ++#define eMMC_ALL_SEND_CID (_START_TXMIT+2) ++#define eMMC_SET_RLT_ADDR (_START_TXMIT+3) ++#define eMMC_SEL_DESEL_CARD (_START_TXMIT+7) ++#define eMMC_SEND_EXT_CSD (_START_TXMIT+8) ++#define eMMC_SEND_CSD (_START_TXMIT+9) ++#define eMMC_SWITCH (_START_TXMIT+6) ++#define eMMC_ERASE_GROUP_S (_START_TXMIT+35) ++#define eMMC_ERASE_GROUP_E (_START_TXMIT+36) ++#define eMMC_ERASE (_START_TXMIT+38) ++#define eMMC_SEND_STATUS (_START_TXMIT+13) ++#define eMMC_R_SINGLE_BLOCK (_START_TXMIT+17) ++#define eMMC_R_MULTIP_BLOCK (_START_TXMIT+18) ++#define eMMC_STOP_TRANSMIT (_START_TXMIT+12) ++#define eMMC_W_SINGLE_BLOCK (_START_TXMIT+24) ++#define eMMC_W_MULTIP_BLOCK (_START_TXMIT+25) ++#define eMMC_SEND_TUNING_BLK (_START_TXMIT+21) ++ ++#define STUFF_BITS 0x00000000 ++ ++extern U32 eMMC_FCIE_WaitEvents(uintptr_t ulongRegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_PollingEvents(uintptr_t ulongRegAddr, U16 u16_Events, U32 u32_MicroSec); ++extern U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir); ++extern void eMMC_FCIE_DumpDebugBus(void); ++extern void eMMC_FCIE_DumpRegisters(void); ++extern void eMMC_FCIE_CheckResetDone(void); ++extern U32 eMMC_FCIE_Reset(void); ++extern U32 eMMC_FCIE_Init(void); ++extern void eMMC_FCIE_ErrHandler_Stop(void); ++extern U32 eMMC_FCIE_ErrHandler_Retry(void); ++extern void eMMC_FCIE_ErrHandler_RestoreClk(void); ++extern void eMMC_FCIE_ErrHandler_ReInit(void); ++extern U32 eMMC_FCIE_ErrHandler_ReInit_Ex(void); ++extern U32 eMMC_FCIE_SendCmd(U16 u16_Mode, U16 u16_Ctrl, U32 u32_Arg, U8 u8_CmdIdx, U8 u8_RspByteCnt); ++extern void eMMC_FCIE_ClearEvents(void); ++extern void eMMC_FCIE_ClearEvents_Reg0(void); ++extern U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us); ++extern U32 eMMC_FCIE_WaitD0High(U32 u32_us); ++extern void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_GetCMDFIFO(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern void eMMC_FCIE_GetCIFD(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++extern U8 eMMC_FCIE_CmdRspBufGet(U8 u8addr); ++extern U8 eMMC_FCIE_DataFifoGet(U8 u8addr); ++ ++// eMMC_hal_speed.c ++ ++extern U32 eMMC_FCIE_EnableDDRMode_Ex(void); ++extern void eMMC_FCIE_ApplyDDRTSet(U8 u8_DDRTIdx); ++extern void eMMC_DumpDDRTTable(void); ++ ++extern U32 eMMC_FCIE_ChooseSpeedMode(void); ++extern void eMMC_FCIE_ApplyTimingSet(U8 u8_Idx); ++extern void eMMC_FCIE_SetATopTimingReg(U8 u8_SetIdx); ++extern U32 eMMC_FCIE_EnableFastMode_Ex(U8 u8_PadType); ++ ++extern void eMMC_FCIE_SetDDR48TimingReg(U8 u8_DQS, U8 u8_DelaySel); ++extern U32 eMMC_FCIE_EnableFastMode(U8 u8_PadType); ++extern U32 eMMC_FCIE_EnableSDRMode(void); ++extern U32 eMMC_FCIE_DetectDDRTiming(void); ++extern void eMMC_DumpTimingTable(void); ++extern U32 eMMC_LoadTimingTable(U8 u8_PadType); ++extern U32 eMMC_TuningDDR52_Skew(void); ++extern U32 eMMC_TuningHS200_Skew(void); ++extern U32 eMMC_SlectBestSkew4(U32 u32_Candidate); ++extern U32 eMMC_Skew_ReTune(void); ++extern U32 eMMC_ATOP_EnableHS200(void); ++extern U32 eMMC_ATOP_EnableDDR52(void); ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++extern void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_SaveRsp(void); ++extern U32 eMMC_SaveDriverContext(void); ++extern U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx); ++extern U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf); ++extern U32 eMMC_LoadDriverContext(U8 *pu8_Buf); ++#endif ++ ++#if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++extern void eMMC_DumpBurstLenTable(void); ++extern U32 eMMC_LoadBurstLenTable(void); ++extern U32 eMMC_SaveBurstLenTable(void); ++#endif ++ ++//---------------------------------------- ++extern U32 eMMC_Identify(void); ++extern U32 eMMC_CMD0(U32 u32_Arg); ++extern U32 eMMC_CMD1(void); ++extern U32 eMMC_CMD2(void); ++extern U32 eMMC_CMD3(U16 u16_RCA); ++extern U32 eMMC_CMD7(U16 u16_RCA); ++extern U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx); ++extern U32 eMMC_CMD9(U16 u16_RCA); ++extern U32 eMMC_CSD_Config(void); ++extern U32 eMMC_ExtCSD_Config(void); ++extern U32 eMMC_CMD8(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf); ++extern U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf); ++extern U32 eMMC_SetPwrOffNotification(U8 u8_SetECSD34); ++extern U32 eMMC_SetBusSpeed(U8 u8_BusSpeed); ++extern U32 eMMC_Sanitize(U8 u8_ECSD165); ++extern U32 eMMC_SetDrivingStrength(U8 u8Driving); ++extern U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR); ++extern U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value); ++extern U32 eMMC_CMD6(U32 u32_Arg); ++extern U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end); ++extern U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx); ++extern U32 eMMC_CMD38(void); ++extern U32 eMMC_Dump_eMMCStatus(void); ++extern U32 eMMC_CMD13(U16 u16_RCA); ++extern U32 eMMC_CMD16(U32 u32_BlkLength); ++extern U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf); ++extern U32 eMMC_CMD12_NoCheck(U16 u16_RCA); ++extern U32 eMMC_CMD12(U16 u16_RCA); ++extern U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD18_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD23(U16 u16_BlkCnt); ++extern U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD25_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern U32 eMMC_CMD21(void); ++extern U32 eMMC_GetR1(void); ++extern U32 eMMC_CheckR1Error(void); ++extern U32 eMMC_UpFW_Samsung(U8 *pu8_FWBin); ++extern U32 eMMC_CMD25_NoSched(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt); ++extern void eMMC_TuningSkew4ForHS200(void); ++ ++//---------------------------------------- ++extern U32 eMMC_FCIE_PollingFifoClkReady(void); ++extern U32 eMMC_FCIE_PollingMIULastDone(void); ++ ++extern void HalFcie_SetFlag4Kernel2RuneMMC(void); ++extern bool HalFcie_CheckIfeMMCRun4Kernel(void); ++ ++extern void eMMC_DumpATopTable(void); ++extern void eMMC_FCIE_SymmetrySkew4(void); ++ ++extern U8 sgu8_IfNeedRestorePadType; // = 0xff ++extern U8 u8_sdr_retry_count; // = 0 ++ ++#endif // __eMMC_HAL_H__ +diff --git a/drivers/mstar/emmc/unify_driver/inc/common/eMMC_utl.h b/drivers/mstar/emmc/unify_driver/inc/common/eMMC_utl.h +new file mode 100644 +index 00000000..07853064 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/common/eMMC_utl.h +@@ -0,0 +1,102 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_UTL_H__ ++#define __eMMC_UTL_H__ ++ ++#include "eMMC.h" ++ ++ ++typedef eMMC_PACK0 struct _eMMC_TEST_ALIGN_PACK { ++ ++ U8 u8_0; ++ U16 u16_0; ++ U32 u32_0, u32_1; ++ ++} eMMC_PACK1 eMMC_TEST_ALIGN_PACK_t; ++ ++extern U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt); ++extern void eMMC_dump_mem(unsigned char *buf, U32 cnt); ++extern void eMMC_dump_mem_32(U32 *buf, U32 cnt); ++extern U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt); ++extern U32 eMMC_ChkSum(U8 *pu8_Data, U32 u32_ByteCnt); ++extern U32 eMMC_PrintDeviceInfo(void); ++extern U32 eMMC_CompareCISTag(U8 *tag); ++extern void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo); ++extern void eMMC_dump_pni(eMMC_PNI_t *pPartInfo); ++extern void eMMC_dump_WR_Count(void); ++#endif // __eMMC_UTL_H__ +diff --git a/drivers/mstar/emmc/unify_driver/inc/config/eMMC_config.h b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_config.h +new file mode 100644 +index 00000000..b3dccd16 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_config.h +@@ -0,0 +1,157 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_CONFIG_H__ ++#define __eMMC_CONFIG_H__ ++ ++#define UNIFIED_eMMC_DRIVER 1 ++ ++//===================================================== ++// select a HW platform: ++// - 1: enable, 0: disable. ++// - only one platform can be 1, others have to be 0. ++// - search and check all [FIXME] if need modify or not ++//===================================================== ++ ++#ifndef U64 ++#define U64 unsigned long long ++#endif ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S64 ++#define S64 signed long long ++#endif ++#ifndef S32 ++#define S32 signed int ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++#if defined(CONFIG_ARCH_INFINITY3) ++#define eMMC_DRV_INFINITY3_LINUX 1 ++#endif ++ ++#if defined(eMMC_DRV_INFINITY3_LINUX) && eMMC_DRV_INFINITY3_LINUX ++#include "eMMC_infinity3_linux.h" ++#else ++#error "Error! no platform selected." ++#endif ++ ++//===================================================== ++// misc. do NOT edit the following content. ++//===================================================== ++#define eMMC_DMA_RACING_PATCH 1 ++#define eMMC_DMA_PATCH_WAIT_TIME DELAY_10ms_in_us ++#define eMMC_DMA_RACING_PATTERN0 (((U32)'M'<<24)|((U32)0<<16)|((U32)'S'<<8)|(U32)1) ++#define eMMC_DMA_RACING_PATTERN1 (((U32)'T'<<24)|((U32)6<<16)|((U32)'A'<<8)|(U32)8) ++ ++//=========================================================== ++// Time Dalay, do NOT edit the following content ++//=========================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RESET (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FIFOCLK_RDY (HW_TIMER_DELAY_10ms*10) ++#define TIME_WAIT_CMDRSP_END (HW_TIMER_DELAY_10ms*10) ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*5) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*10) // safe for 512 blocks ++#else ++#define TIME_WAIT_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_ERASE_DAT0_HIGH (HW_TIMER_DELAY_1s*10) ++#define TIME_WAIT_FCIE_RESET HW_TIMER_DELAY_500ms ++#define TIME_WAIT_FCIE_RST_TOGGLE_CNT HW_TIMER_DELAY_1us ++#define TIME_WAIT_FIFOCLK_RDY HW_TIMER_DELAY_10ms ++#define TIME_WAIT_CMDRSP_END HW_TIMER_DELAY_10ms ++#define TIME_WAIT_1_BLK_END (HW_TIMER_DELAY_1s*1) ++#define TIME_WAIT_n_BLK_END (HW_TIMER_DELAY_1s*2) // safe for 512 blocks ++#endif ++ ++extern void mdelay_MacroToFun(u32 time); ++ ++#endif /* __eMMC_CONFIG_H__ */ +diff --git a/drivers/mstar/emmc/unify_driver/inc/config/eMMC_infinity3_linux.h b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_infinity3_linux.h +new file mode 100644 +index 00000000..caebb325 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_infinity3_linux.h +@@ -0,0 +1,542 @@ ++#ifndef __eMMC_INFINITY3_LINUX__ ++#define __eMMC_INFINITY3_LINUX__ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++#ifndef U32 ++#define U32 unsigned int ++#endif ++#ifndef U16 ++#define U16 unsigned short ++#endif ++#ifndef U8 ++#define U8 unsigned char ++#endif ++#ifndef S32 ++#define S32 signed long ++#endif ++#ifndef S16 ++#define S16 signed short ++#endif ++#ifndef S8 ++#define S8 signed char ++#endif ++ ++ ++//===================================================== ++// HW registers ++//===================================================== ++ ++#define REG_FCIE_U16(Reg_Addr) (*(volatile U16*)(IO_ADDRESS(Reg_Addr))) ++#define REG_OFFSET_SHIFT_BITS 2 ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++// [CAUTION]: to detect DDR timiing parameters, only for DL ++// need to eMMC_pads_switch ++// need to eMMC_clock_setting ++#define IF_FCIE_SHARE_IP 1 ++ ++ ++//------------------------------ ++#define FICE_BYTE_MODE_ENABLE 1 // always 1 ++#define ENABLE_eMMC_INTERRUPT_MODE 0 ++#define ENABLE_eMMC_RIU_MODE 0 // for debug cache issue ++ ++#if ENABLE_eMMC_RIU_MODE ++#undef IF_DETECT_eMMC_DDR_TIMING ++#define IF_DETECT_eMMC_DDR_TIMING 0 // RIU mode can NOT use DDR ++#endif ++// <-- [FIXME] ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#define ENABLE_EMMC_PRE_DEFINED_BLK 1 ++#endif ++//------------------------------ ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#if eMMC_UPDATE_FIRMWARE ++#undef eMMC_FEATURE_RELIABLE_WRITE ++#define eMMC_FEATURE_RELIABLE_WRITE 0 ++#endif ++ ++//------------------------------ ++//#define eMMC_RSP_FROM_RAM_SAVE 1 ++//#define eMMC_RSP_FROM_RAM_LOAD 0 ++#define eMMC_RSP_FROM_RAM 1 ++ ++#define eMMC_FCIE_LINUX_DRIVER 1 ++ ++//------------------------------ ++//------------------------------------------------------- ++// Devices has to be in 512B block length mode by default ++// after power-on, or software reset. ++//------------------------------------------------------- ++ ++#define eMMC_SECTOR_512BYTEa 0x200 ++#define eMMC_SECTOR_512BYTE_BITSa 9 ++#define eMMC_SECTOR_512BYTE_MASKa (eMMC_SECTOR_512BYTEa-1) ++ ++#define eMMC_SECTOR_BUF_16KBa (eMMC_SECTOR_512BYTEa * 0x20) ++ ++#define eMMC_SECTOR_BYTECNTa eMMC_SECTOR_512BYTEa ++#define eMMC_SECTOR_BYTECNT_BITSa eMMC_SECTOR_512BYTE_BITSa ++ ++#define eMMC_SECTOR_BUF_BYTECTN eMMC_SECTOR_BUF_16KBa ++extern U8 *gau8_eMMC_SectorBuf; // 512 bytes ++extern U8 *gau8_eMMC_PartInfoBuf; // 512 bytes ++//U8 gau8_eMMC_SectorBuf[eMMC_SECTOR_BUF_16KBa]; // 512 bytes ++//U8 gau8_eMMC_PartInfoBuf[eMMC_SECTOR_512BYTEa]; // 512 bytes ++//------------------------------ ++// Boot Partition: ++// [FIXME]: if platform has ROM code like G2P ++//------------------------------ ++// No Need in A3 ++#define BL_BLK_OFFSET 0 ++#define BL_BLK_CNT (0xF200/0x200) ++#define OTP_BLK_OFFSET BL_BLK_CNT ++#define OTP_BLK_CNT (0x8000/0x200) ++#define SecInfo_BLK_OFFSET (BL_BLK_CNT+OTP_BLK_CNT) ++#define SecInfo_BLK_CNT (0x1000/0x200) ++#define BOOT_PART_TOTAL_CNT (BL_BLK_CNT+OTP_BLK_CNT+SecInfo_BLK_CNT) ++// <-- [FIXME] ++ ++#define eMMC_CACHE_LINE 0x20 // [FIXME] ++ ++//===================================================== ++// tool-chain attributes ++//===================================================== [FIXME] --> ++#define eMMC_PACK0 ++#define eMMC_PACK1 __attribute__((__packed__)) ++#define eMMC_ALIGN0 ++#define eMMC_ALIGN1 __attribute__((aligned(eMMC_CACHE_LINE))) ++// <-- [FIXME] ++ ++//===================================================== ++// debug option ++//===================================================== ++#define eMMC_TEST_IN_DESIGN 0 // [FIXME]: set 1 to verify HW timer ++ ++#ifndef eMMC_DEBUG_MSG ++#define eMMC_DEBUG_MSG 1 ++#endif ++ ++/* Define trace levels. */ ++#define eMMC_DEBUG_LEVEL_ERROR (1) /* Error condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_WARNING (2) /* Warning condition debug messages. */ ++#define eMMC_DEBUG_LEVEL_HIGH (3) /* Debug messages (high debugging). */ ++#define eMMC_DEBUG_LEVEL_MEDIUM (4) /* Debug messages. */ ++#define eMMC_DEBUG_LEVEL_LOW (5) /* Debug messages (low debugging). */ ++ ++/* Higer debug level means more verbose */ ++#ifndef eMMC_DEBUG_LEVEL ++#define eMMC_DEBUG_LEVEL eMMC_DEBUG_LEVEL_LOW// ++#endif ++ ++#if defined(eMMC_DEBUG_MSG) && eMMC_DEBUG_MSG ++#define eMMC_printf pr_info // <-- [FIXME] ++#define eMMC_debug(dbg_lv, tag, str, ...) \ ++ do { \ ++ if (dbg_lv > eMMC_DEBUG_LEVEL) \ ++ break; \ ++ else if(eMMC_IF_DDRT_TUNING()) \ ++ break; \ ++ else { \ ++ if (tag) \ ++ eMMC_printf("[ %s() ] ", __func__);\ ++ \ ++ eMMC_printf(str, ##__VA_ARGS__); \ ++ } \ ++ } while(0) ++#else /* eMMC_DEBUG_MSG */ ++#define eMMC_printf(...) ++#define eMMC_debug(enable, tag, str, ...) do{}while(0) ++#endif /* eMMC_DEBUG_MSG */ ++ ++#define eMMC_die(msg) while(1);//SYS_FAIL(""msg); ++ ++#define eMMC_stop() \ ++ while(1) eMMC_reset_WatchDog(); ++ ++//===================================================== ++// unit for HW Timer delay (unit of us) ++//===================================================== ++#define HW_TIMER_DELAY_1us 1 ++#define HW_TIMER_DELAY_5us 5 ++#define HW_TIMER_DELAY_10us 10 ++#define HW_TIMER_DELAY_100us 100 ++#define HW_TIMER_DELAY_500us 500 ++#define HW_TIMER_DELAY_1ms (1000 * HW_TIMER_DELAY_1us) ++#define HW_TIMER_DELAY_5ms (5 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_10ms (10 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_100ms (100 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_500ms (500 * HW_TIMER_DELAY_1ms) ++#define HW_TIMER_DELAY_1s (1000 * HW_TIMER_DELAY_1ms) ++ ++//===================================================== ++// set FCIE clock ++//===================================================== ++#define FCIE_SLOWEST_CLK BIT_FCIE_CLK_300K ++#define FCIE_DEFO_SPEED_CLK BIT_FCIE_CLK_12M ++#define FCIE_HIGH_SPEED_CLK BIT_FCIE_CLK_48M ++ ++// for backward compatible ++#define FCIE_SLOW_CLK FCIE_DEFO_SPEED_CLK ++#define FCIE_DEFAULT_CLK FCIE_HIGH_SPEED_CLK ++#define eMMC_PLL_CLK_SLOW FCIE_DEFO_SPEED_CLK ++ ++//===================================================== ++// transfer DMA Address ++//===================================================== ++#define MIU_BUS_WIDTH_BITS 3 // 8 bytes width [FIXME] ++/* ++ * Important: ++ * The following buffers should be large enough for a whole eMMC block ++ */ ++// FIXME, this is only for verifing IP ++#define DMA_W_ADDR 0x40C00000 ++#define DMA_R_ADDR 0x40D00000 ++#define DMA_W_SPARE_ADDR 0x40E00000 ++#define DMA_R_SPARE_ADDR 0x40E80000 ++#define DMA_BAD_BLK_BUF 0x40F00000 ++ ++ ++//===================================================== ++// misc ++//===================================================== ++//#define BIG_ENDIAN ++#define LITTLE_ENDIAN ++ ++ ++#endif /* __eMMC_INFINITY3_LINUX__ */ +diff --git a/drivers/mstar/emmc/unify_driver/inc/config/eMMC_reg.h b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_reg.h +new file mode 100644 +index 00000000..f874a012 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_reg.h +@@ -0,0 +1,417 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __eMMC_FCIE_REG_H__ ++#define __eMMC_FCIE_REG_H__ ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++#ifndef BIT0 ++#define BIT0 (1<<0) ++#endif ++#ifndef BIT1 ++#define BIT1 (1<<1) ++#endif ++#ifndef BIT2 ++#define BIT2 (1<<2) ++#endif ++#ifndef BIT3 ++#define BIT3 (1<<3) ++#endif ++#ifndef BIT4 ++#define BIT4 (1<<4) ++#endif ++#ifndef BIT5 ++#define BIT5 (1<<5) ++#endif ++#ifndef BIT6 ++#define BIT6 (1<<6) ++#endif ++#ifndef BIT7 ++#define BIT7 (1<<7) ++#endif ++#ifndef BIT8 ++#define BIT8 (1<<8) ++#endif ++#ifndef BIT9 ++#define BIT9 (1<<9) ++#endif ++#ifndef BIT10 ++#define BIT10 (1<<10) ++#endif ++#ifndef BIT11 ++#define BIT11 (1<<11) ++#endif ++#ifndef BIT12 ++#define BIT12 (1<<12) ++#endif ++#ifndef BIT13 ++#define BIT13 (1<<13) ++#endif ++#ifndef BIT14 ++#define BIT14 (1<<14) ++#endif ++#ifndef BIT15 ++#define BIT15 (1<<15) ++#endif ++#ifndef BIT16 ++#define BIT16 (1<<16) ++#endif ++#ifndef BIT17 ++#define BIT17 (1<<17) ++#endif ++#ifndef BIT18 ++#define BIT18 (1<<18) ++#endif ++#ifndef BIT19 ++#define BIT19 (1<<19) ++#endif ++#ifndef BIT20 ++#define BIT20 (1<<20) ++#endif ++#ifndef BIT21 ++#define BIT21 (1<<21) ++#endif ++#ifndef BIT22 ++#define BIT22 (1<<22) ++#endif ++#ifndef BIT23 ++#define BIT23 (1<<23) ++#endif ++#ifndef BIT24 ++#define BIT24 (1<<24) ++#endif ++#ifndef BIT25 ++#define BIT25 (1<<25) ++#endif ++#ifndef BIT26 ++#define BIT26 (1<<26) ++#endif ++#ifndef BIT27 ++#define BIT27 (1<<27) ++#endif ++#ifndef BIT28 ++#define BIT28 (1<<28) ++#endif ++#ifndef BIT29 ++#define BIT29 (1<<29) ++#endif ++#ifndef BIT30 ++#define BIT30 (1<<30) ++#endif ++#ifndef BIT31 ++#define BIT31 (1<<31) ++#endif ++ ++//------------------------------------------------------------------ ++#define FCIE_MIE_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x00) ++#define FCIE_MIE_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x01) ++#define FCIE_MMA_PRI_REG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x02) ++#define FCIE_MIU_DMA_26_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x03) ++#define FCIE_MIU_DMA_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x04) ++#define FCIE_CARD_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x06) ++#define FCIE_CARD_POWER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x08) ++#define FCIE_FORCE_INT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x09) ++#define FCIE_PATH_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0A) ++#define FCIE_JOB_BL_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0B) ++#define FCIE_TR_BK_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0C) ++#define FCIE_RSP_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0D) ++#define FCIE_CMD_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0E) ++#define FCIE_CIFD_WORD_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0F) ++#define FCIE_SD_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_SD_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++#define FCIE_SD_STATUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x12) ++#define FCIE_REG16h GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x16) ++#define FCIE_SDIO_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1B) ++#define FCIE_SDIO_ADDR0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1C) ++#define FCIE_SDIO_ADDR1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1D) ++#define FCIE_SD_MACRO_REDNT2 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2B) ++#define FCIE_SM_STS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2C) ++#define FCIE_REG_2Dh GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2D) ++#define FCIE_MIU_OFFSET GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2E) ++#define FCIE_BOOT_CONFIG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x2F) ++#define FCIE_TEST_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x30) ++#define FCIE_DEBUG_BUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x31) ++#define FCIE_MACRO_REDNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x32) ++#define FCIE_TOGGLE_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x33) ++#define FCIE_PWR_SAVE_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x35) ++#define FCIE_MISC GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x36) ++#define FCIE_HS200_PATCH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x3F) ++#define NC_WIDTH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x41) ++ ++#define FCIE_CIFC_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFC_BASE_ADDR, u16_pos) ++#define FCIE_CIFC_BYTE_CNT 0x40 // 32 x 16 bits ++ ++#define FCIE_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFD_BASE_ADDR, u16_pos) ++#define FCIE_CIFD_BYTE_CNT 0x200 // 256 x 16 bits ++ ++//------------------------------------------------------------------ ++/* FCIE_MIE_EVENT 0x00 */ ++/* FCIE_MIE_INT_EN 0x01 */ ++#define BIT_MMA_DATA_END BIT0 ++#define BIT_SD_CMD_END BIT1 ++#define BIT_SD_DATA_END BIT2 ++#define BIT_CARD_DMA_END BIT11 ++#define BIT_MIU_LAST_DONE BIT14 ++#define BIT_CARD_BOOT_DONE BIT15 ++#define BIT_ALL_CARD_INT_EVENTS (BIT_MMA_DATA_END|BIT_SD_CMD_END|BIT_SD_DATA_END\ ++ |BIT_CARD_DMA_END|BIT_MIU_LAST_DONE|BIT_CARD_BOOT_DONE) ++/* FCIE_MMA_PRI_REG 0x02 */ ++#define BIT_DMA_DIR_W BIT2 ++#define BIT_MIU_REQUEST_RST BIT4 ++#define BIT_FIFO_CLKRDY BIT5 ++#define BIT_MIU_BURST_MASK (BIT8|BIT9|BIT10) ++#define BIT_MIU_BURST_CTRL BIT10 ++#define BIT_MIU_BURST_8 BIT_MIU_BURST_CTRL ++#define BIT_MIU_BURST_16 (BIT8|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_BURST_32 (BIT9|BIT_MIU_BURST_CTRL) ++#define BIT_MIU_CLK_EN_SW BIT12 ++#define BIT_MIU_CLK_EN_HW BIT13 ++#define BIT_MIU_CLK_CTRL_SEL_SW BIT14 ++#define BIT_MIU_CLK_FREE_RUN BIT15 ++/* FCIE_MIU_DMA_26_16 0x03 */ ++#define BIT_MIU1_SELECT BIT15 ++/* FCIE_CARD_POWER 0x08 */ ++#define BIT_SD_PWR_ON_n BIT0 ++#define BIT_SD_PWR_OUT_n BIT2 ++/* FCIE_PATH_CTRL 0x0A */ ++#define BIT_MMA_EN BIT0 ++#define BIT_SD_EN BIT1 ++/* FCIE_JOB_BL_CNT 0x0B */ ++#define BIT_SD_JOB_BLK_CNT_MASK (BIT12-1) ++#define BIT_SD_JOB_CNT_SRC_MIU BIT14 ++#define BIT_SD_JOB_CNT_SRC_SEL BIT15 ++/* FCIE_RSP_SIZE 0x0D */ ++#define BIT_SD_RSP_SIZE_MASK (BIT7-1) ++/* FCIE_SD_MODE 0x10 */ ++#define BIT_SD_CLK_EN BIT0 ++#define BIT_SD_DATA_WIDTH_MASK (BIT1|BIT2) ++#define BIT_SD_DATA_WIDTH_1 0 ++#define BIT_SD_DATA_WIDTH_4 BIT1 ++#define BIT_SD_DATA_WIDTH_8 BIT2 ++#define BIT_SD_IF_LOW BIT3 ++#define BIT_SD_CLK_AUTO_STOP BIT4 ++#define BIT_SD_DATA_CIFD BIT5 ++#define BIT_SD_DATA_SYNC BIT6 // set for eMMC High Speed Mode ++#define BIT_SD_SELECT_SDIO BIT9 ++#define BIT_SD_DMA_R_CLK_STOP BIT11 ++ ++//#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_CLK_EN) ++#define BIT_SD_DEFAULT_MODE_REG (BIT_SD_CLK_AUTO_STOP|BIT_SD_DATA_SYNC|BIT_SD_CLK_EN) ++ ++/* FCIE_SD_CTRL 0x11 */ ++#define BIT_SD_RSPR2_EN BIT0 ++#define BIT_SD_RSP_EN BIT1 ++#define BIT_SD_CMD_EN BIT2 ++#define BIT_SD_DAT_EN BIT3 ++#define BIT_SD_DAT_DIR_W BIT4 ++/* FCIE_SD_STATUS 0x12 */ ++#define BIT_SD_R_CRC_ERR BIT0 ++#define BIT_SD_W_FAIL BIT1 // no any positive/negative CRC status latched ++#define BIT_SD_W_CRC_ERR BIT2 // negative CRC status latched ++#define BIT_SD_RSP_TIMEOUT BIT3 // response time out in 64 clocks ++#define BIT_SD_RSP_CRC_ERR BIT4 // response crc error ++#define BIT_SD_CARD_WP BIT5 ++#define BIT_SD_CARD_BUSY BIT6 ++#define BIT_SD_D0 BIT8 ++#define BIT_SD_DBUS_MASK (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++#define BIT_SD_DBUS_SHIFT 8 ++ ++//#define BIT_SD_FCIE_ERR_FLAGS ((BIT5-1)|BIT_SD_CARD_BUSY) ++#define BIT_SD_FCIE_ERR_FLAGS (BIT5-1) ++#define BIT_SD_CARD_D0_ST BIT8 ++#define BIT_SD_CARD_D1_ST BIT9 ++#define BIT_SD_CARD_D2_ST BIT10 ++#define BIT_SD_CARD_D3_ST BIT11 ++#define BIT_SD_CARD_D4_ST BIT12 ++#define BIT_SD_CARD_D5_ST BIT13 ++#define BIT_SD_CARD_D6_ST BIT14 ++#define BIT_SD_CARD_D7_ST BIT15 ++/* FCIE_REG16h */ ++#define BIT_EMMC_ACTIVE BIT0 ++#define BIT_KERN_NAND (BIT3|BIT1) ++#define BIT_KERN_EMMC (BIT3|BIT2) ++#define BIT_KERN_CHK_NAND_EMMC BIT3 ++#define BIT_KERN_CHK_NAND_EMMC_MSK (BIT3|BIT2|BIT1) ++/* FCIE_SDIO_CTRL 0x1B */ ++#define BIT_SDIO_BLK_SIZE_MASK (BIT13-1) ++#define BIT_SDIO_BLK_MODE BIT15 ++/* FCIE_SM_STS 0x2B */ ++#define BIT_DDR_TIMING_LATCH BIT8 ++/* FCIE_SM_STS 0x2C */ ++#define BIT_DQS_DELAY_CELL_MASK (BIT8|BIT9|BIT10|BIT11) ++#define BIT_DQS_DELAY_CELL_SHIFT 8 ++#define BIT_DQS_MODE_MASK (BIT12|BIT13) ++#define BIT_DQS_MODE_SHIFT 12 ++#define BIT_DQS_MODE_2T (0 << BIT_DQS_MODE_SHIFT) ++#define BIT_DQS_MODE_1_5T (1 << BIT_DQS_MODE_SHIFT) ++#define BIT_DQS_MODE_2_5T (2 << BIT_DQS_MODE_SHIFT) ++#define BIT_DQS_MODE_1T (3 << BIT_DQS_MODE_SHIFT) ++ ++#define BIT_SKEW1_INV BIT8 ++#define BIT_SKEW2_INV BIT9 ++#define BIT_SKEW3_INV BIT10 ++#define BIT_SKEW4_INV BIT11 ++ ++#define BITS_SKEW_SET_MSK 0x0F00 ++#define BITS_SKEW_SET0 0x0700 ++#define BITS_SKEW_SET1 0x0000 ++ ++/* FCIE_REG_2Dh 0x2D */ ++#define BIT_ddr_timing_patch BIT0 ++#define BIT_eco_d0_busy_check BIT3 ++ ++#define BIT_csreg_miu_wp_last2_sel BIT14 ++/* FCIE_BOOT_CONFIG 0x2F */ ++#define BIT_BOOT_STG2_EN BIT0 ++#define BIT_BOOT_END_EN BIT1 ++#define BIT_BOOT_MODE_EN BIT2 ++#define BIT_MACRO_EN BIT8 ++#define BIT_SD_DDR_EN BIT9 ++#define BIT_SD_BYPASS_MODE_EN BIT10 ++#define BIT_SD_SDR_IN_BYPASS BIT11 ++#define BIT_SD_FROM_TMUX BIT12 ++#define BIT_SD_CLKOE_DELAY_EN BIT13 ++/* FCIE_TEST_MODE 0x30 */ ++#define BIT_FCIE_BIST_FAIL (BIT0|BIT1|BIT2|BIT3|BIT4) ++#define BIT_FCIE_DEBUG_MODE_MASK (BIT8|BIT9|BIT10) ++#define BIT_FCIE_DEBUG_MODE_SHIFT 8 ++#define BIT_FCIE_SOFT_RST_n BIT12 ++#define BIT_FCIE_PPFIFO_CLK BIT14 ++/* FCIE_MACRO_REDNT 0x32 */ ++#define BIT_CRC_STATUS_4_HS200 BIT0 ++#define BIT_LATE_DATA0_W_IP_CLK BIT1 ++#define BIT_DQS_DELAY_CELL_SEL_MASK (BIT0|BIT1|BIT2|BIT3) ++#define BIT_MACRO_TEST_MODE_MASK (BIT4|BIT5) ++#define BIT_MACRO_DIR BIT6 ++#define BIT_TOGGLE_CNT_RST BIT7 ++/* FCIE_TOGGLE_CNT */ ++#define BITS_8_R_TOGGLE_CNT 0x0111 // 256 data clock + 17 bits CRC ++#define BITS_4_R_TOGGLE_CNT 0x0211 // 512 data clcok + 17 bits CRC ++#define BITS_8_W_TOGGLE_CNT 0x011A // 256 data clcok + 26 bits CRC + CRC status ++#define BITS_4_W_TOGGLE_CNT 0x021A // 512 data clcok + 26 bits CRC + CRC status ++ ++#define TOGGLE_CNT_128_CLK_R 0x0091 // 128 data clcok + 17 bits CRC ++#define TOGGLE_CNT_256_CLK_R 0x0111 // 256 data clcok + 17 bits CRC ++#define TOGGLE_CNT_512_CLK_R 0x0211 // 512 data clcok + 17 bits CRC ++#define TOGGLE_CNT_256_CLK_W 0x011A // 256 data clcok + 26 bits CRC + CRC status ++#define TOGGLE_CNT_512_CLK_W 0x021A // 512 data clcok + 26 bits CRC + CRC status ++ ++/* FCIE_PWR_SAVE_MODE 0x35 */ ++#define BIT_POWER_SAVE_MODE_EN BIT0 /* Power Save HW enable, high active */ ++#define BIT_SD_POWER_SAVE_RIU BIT1 /* SW set register to emulate power lost event, high active */ ++#define BIT_POWER_SAVE_MODE_INT_EN BIT2 /* interrupt enable, high active */ ++#define BIT_SD_POWER_SAVE_RST BIT3 /* software reset Power Save HW, default is '1', set '0' to reset HW */ ++#define BIT_RIU_SAVE_EVENT BIT5 /* RO, RIU emulation power save event */ ++#define BIT_RST_SAVE_EVENT BIT6 /* RO, Hardware reset power save event */ ++#define BIT_BAT_SAVE_EVENT BIT7 /* RO, Battery lost power save event */ ++/*FCIE_HS200_PATCH 0x3F*/ ++#define BIT_HS200_RDDAT_PATCH BIT8 ++#define BIT_HS200_NORSP_PATCH BIT9 ++#define BIT_HS200_WCRC_PATCH BIT10 ++#define BIT_sbit_lose_patch BIT11 ++#define BIT_HS200_PATCH_MASK (BIT_HS200_RDDAT_PATCH|BIT_HS200_NORSP_PATCH|BIT_HS200_WCRC_PATCH|BIT_sbit_lose_patch) ++ ++/* NC_WIDTH 0x41 */ ++#define BIT_NC_DEB_SEL_SHIFT 12 ++#define BIT_NC_DEB_SEL_MASK (BIT12|BIT13|BIT14) ++#define BIT_NC_BCH_DEB_SEL BIT15 ++ ++//------------------------------------------------------------------ ++/* ++ * Power Save FIFO Cmd* ++ */ ++#define PWR_BAT_CLASS (0x1 << 13) /* Battery lost class */ ++#define PWR_RST_CLASS (0x1 << 12) /* Reset Class */ ++ ++/* Command Type */ ++#define PWR_CMD_WREG (0x0 << 9) /* Write data */ ++#define PWR_CMD_RDCP (0x1 << 9) /* Read and cmp data. If mismatch, HW retry */ ++#define PWR_CMD_WAIT (0x2 << 9) /* Wait idle, max. 128T */ ++#define PWR_CMD_WINT (0x3 << 9) /* Wait interrupt */ ++#define PWR_CMD_STOP (0x7 << 9) /* Stop */ ++ ++/* RIU Bank */ ++#define PWR_CMD_BK0 (0x0 << 7) ++#define PWR_CMD_BK1 (0x1 << 7) ++#define PWR_CMD_BK2 (0x2 << 7) ++#define PWR_CMD_BK3 (0x3 << 7) ++ ++#define PWR_RIU_ADDR (0x0 << 0) ++ ++#endif /* __eMMC_FCIE_REG_H__ */ +diff --git a/drivers/mstar/emmc/unify_driver/inc/config/eMMC_reg_v5.h b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_reg_v5.h +new file mode 100644 +index 00000000..6759a2fc +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/inc/config/eMMC_reg_v5.h +@@ -0,0 +1,487 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++#ifndef __EMMC_REG_V5_H__ ++#define __EMMC_REG_V5_H__ ++ ++#define IP_FCIE_VERSION_5 ++ ++#ifndef NULL ++#define NULL ((void*)0) ++#endif ++#ifndef BIT0 ++#define BIT0 (1<<0) ++#endif ++#ifndef BIT1 ++#define BIT1 (1<<1) ++#endif ++#ifndef BIT2 ++#define BIT2 (1<<2) ++#endif ++#ifndef BIT3 ++#define BIT3 (1<<3) ++#endif ++#ifndef BIT4 ++#define BIT4 (1<<4) ++#endif ++#ifndef BIT5 ++#define BIT5 (1<<5) ++#endif ++#ifndef BIT6 ++#define BIT6 (1<<6) ++#endif ++#ifndef BIT7 ++#define BIT7 (1<<7) ++#endif ++#ifndef BIT8 ++#define BIT8 (1<<8) ++#endif ++#ifndef BIT9 ++#define BIT9 (1<<9) ++#endif ++#ifndef BIT10 ++#define BIT10 (1<<10) ++#endif ++#ifndef BIT11 ++#define BIT11 (1<<11) ++#endif ++#ifndef BIT12 ++#define BIT12 (1<<12) ++#endif ++#ifndef BIT13 ++#define BIT13 (1<<13) ++#endif ++#ifndef BIT14 ++#define BIT14 (1<<14) ++#endif ++#ifndef BIT15 ++#define BIT15 (1<<15) ++#endif ++#ifndef BIT16 ++#define BIT16 (1<<16) ++#endif ++#ifndef BIT17 ++#define BIT17 (1<<17) ++#endif ++#ifndef BIT18 ++#define BIT18 (1<<18) ++#endif ++#ifndef BIT19 ++#define BIT19 (1<<19) ++#endif ++#ifndef BIT20 ++#define BIT20 (1<<20) ++#endif ++#ifndef BIT21 ++#define BIT21 (1<<21) ++#endif ++#ifndef BIT22 ++#define BIT22 (1<<22) ++#endif ++#ifndef BIT23 ++#define BIT23 (1<<23) ++#endif ++#ifndef BIT24 ++#define BIT24 (1<<24) ++#endif ++#ifndef BIT25 ++#define BIT25 (1<<25) ++#endif ++#ifndef BIT26 ++#define BIT26 (1<<26) ++#endif ++#ifndef BIT27 ++#define BIT27 (1<<27) ++#endif ++#ifndef BIT28 ++#define BIT28 (1<<28) ++#endif ++#ifndef BIT29 ++#define BIT29 (1<<29) ++#endif ++#ifndef BIT30 ++#define BIT30 (1<<30) ++#endif ++#ifndef BIT31 ++#define BIT31 (1<<31) ++#endif ++ ++//------------------------------------------------------------------ ++#define FCIE_MIE_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x00) ++#define FCIE_MIE_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x01) ++#define FCIE_MMA_PRI_REG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x02) ++#define FCIE_MIU_DMA_ADDR_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x03) ++#define FCIE_MIU_DMA_ADDR_31_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x04) ++#define FCIE_MIU_DMA_LEN_15_0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x05) ++#define FCIE_MIU_DMA_LEN_31_16 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x06) ++#define FCIE_MIE_FUNC_CTL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x07) ++#define FCIE_JOB_BL_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x08) ++#define FCIE_BLK_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x09) ++#define FCIE_CMD_RSP_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0A) ++#define FCIE_SD_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0B) ++#define FCIE_SD_CTRL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0C) ++#define FCIE_SD_STATUS GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0D) ++#define FCIE_BOOT_CONFIG GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0E) ++#define FCIE_DDR_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x0F) ++//#define FCIE_DDR_TOGGLE_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_RESERVED_FOR_SW GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x10) ++#define FCIE_SDIO_MOD GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++//#define FCIE_SBIT_TIMER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x11) ++#define FCIE_RSP_SHIFT_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x12) ++#define FCIE_RX_SHIFT_CNT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x13) ++#define FCIE_ZDEC_CTL0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x14) ++#define FCIE_TEST_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x15) ++#define FCIE_MMA_BANK_SIZE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x16) ++#define FCIE_WR_SBIT_TIMER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x17) ++//#define FCIE_SDIO_MODE GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x17) ++#define FCIE_RD_SBIT_TIMER GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x18) ++//#define FCIE_DEBUG_BUS0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1E) ++//#define FCIE_DEBUG_BUS1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x1F) ++#define NC_CIFD_EVENT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x30) ++#define NC_CIFD_INT_EN GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x31) ++#define FCIE_PWR_RD_MASK GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x34) ++#define FCIE_PWR_SAVE_CTL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x35) ++#define FCIE_BIST GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x36) ++#define FCIE_BOOT GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x37) ++#define FCIE_EMMC_DEBUG_BUS0 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x38) ++#define FCIE_EMMC_DEBUG_BUS1 GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x39) ++#define FCIE_RST GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x3F) ++//#define NC_WIDTH GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x41) ++#define FCIE_NC_FUN_CTL GET_REG_ADDR(FCIE_REG_BASE_ADDR, 0x63) ++ ++ ++#define FCIE_CMDFIFO_ADDR(u16_pos) GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, u16_pos) ++#define FCIE_CMDFIFO_BYTE_CNT 0x12// 9 x 16 bits ++ ++#define FCIE_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_CIFD_BASE_ADDR, u16_pos) ++ ++ ++#define NC_WBUF_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_NC_WBUF_CIFD_BASE, u16_pos) // 32 x 16 bits SW Read only ++#define NC_RBUF_CIFD_ADDR(u16_pos) GET_REG_ADDR(FCIE_NC_RBUF_CIFD_BASE, u16_pos) // 32 x 16 bits SW write/read ++ ++#define NC_CIFD_ADDR(u16_pos) NC_RBUF_CIFD_ADDR(u16_pos) ++ ++#define NC_CIFD_WBUF_BYTE_CNT 0x40 // 32 x 16 bits ++#define NC_CIFD_RBUF_BYTE_CNT 0x40 // 32 x 16 bits ++ ++#define FCIE_CIFD_BYTE_CNT 0x40 // 256 x 16 bits ++ ++//------------------------------------------------------------------ ++/* FCIE_MIE_EVENT 0x00 */ ++/* FCIE_MIE_INT_EN 0x01 */ ++#define BIT_DMA_END BIT0 ++#define BIT_CMD_END BIT1 ++#define BIT_ERR_STS BIT2 ++//#define BIT_SD_DATA_END BIT2 ++#define BIT_SDIO_INT BIT3 ++#define BIT_BUSY_END_INT BIT4 ++#define BIT_R2N_RDY_INT BIT5 ++#define BIT_CARD_CHANGE BIT6 ++#define BIT_CARD2_CHANGE BIT7 ++//#define BIT_PWR_SAVE_INT BIT14 ++//#define BIT_BOOT_DONE_INT BIT15 ++//#define BIT_ALL_CARD_INT_EVENTS (BIT_DMA_END|BIT_CMD_END|BIT_BUSY_END_INT) ++#define BIT_ALL_CARD_INT_EVENTS (BIT_DMA_END|BIT_CMD_END|BIT_ERR_STS|BIT_BUSY_END_INT|BIT_R2N_RDY_INT) ++ ++/* FCIE_MMA_PRI_REG 0x02 */ ++#define BIT_MIU_R_PRI BIT0 ++#define BIT_MIU_W_PRI BIT1 ++#define BIT_MIU_SELECT_MASK (BIT3|BIT2) ++#define BIT_MIU1_SELECT BIT2 ++#define BIT_MIU2_SELECT BIT3 ++#define BIT_MIU3_SELECT (BIT3|BIT2) ++//#define BIT_DATA_SCRAMBLE BIT3 ++#define BIT_MIU_BUS_TYPE_MASK (BIT4|BIT5) ++#define BIT_MIU_BURST1 (~BIT_MIU_BUS_TYPE_MASK) ++#define BIT_MIU_BURST2 (BIT4) ++#define BIT_MIU_BURST4 (BIT5) ++#define BIT_MIU_BURST8 (BIT4|BIT5) ++ ++/* FCIE_MIE_FUNC_CTL 0x07 */ ++#define BIT_EMMC_EN BIT0 ++#define BIT_SD_EN BIT1 ++#define BIT_SDIO_MOD BIT2 ++#define BIT_EMMC_ACTIVE BIT12 ++#define BIT_KERN_NAND (BIT_KERN_CHK_NAND_EMMC|BIT13) ++#define BIT_KERN_EMMC (BIT_KERN_CHK_NAND_EMMC|BIT14) ++#define BIT_KERN_CHK_NAND_EMMC BIT15 ++#define BIT_KERN_CHK_NAND_EMMC_MSK (BIT13|BIT14|BIT15) ++ ++/* FCIE_BLK_CNT 0x08 */ ++#define BIT_SD_JOB_BLK_CNT_MASK (BIT13-1) ++ ++/* FCIE_CMD_RSP_SIZE 0x0A */ ++#define BIT_RSP_SIZE_MASK (BIT6-1) ++#define BIT_CMD_SIZE_MASK (BIT13|BIT12|BIT11|BIT10|BIT9|BIT8) ++#define BIT_CMD_SIZE_SHIFT 8 ++ ++/* FCIE_SD_MODE 0x0B */ ++#define BIT_CLK_EN BIT0 ++#define BIT_SD_CLK_EN BIT_CLK_EN ++#define BIT_SD_DATA_WIDTH_MASK (BIT2|BIT1) ++#define BIT_SD_DATA_WIDTH_1 0 ++#define BIT_SD_DATA_WIDTH_4 BIT1 ++#define BIT_SD_DATA_WIDTH_8 BIT2 ++#define BIT_DATA_DEST BIT4 // 0: DMA mode, 1: R2N mode ++#define BIT_SD_DATA_CIFD BIT_DATA_DEST ++#define BIT_DATA_SYNC BIT5 ++#define BIT_SD_DMA_R_CLK_STOP BIT7 ++#define BIT_DIS_WR_BUSY_CHK BIT8 ++ ++#define BIT_SD_DEFAULT_MODE_REG (BIT_CLK_EN) ++ ++/* FCIE_SD_CTRL 0x0C */ ++#define BIT_SD_RSPR2_EN BIT0 ++#define BIT_SD_RSP_EN BIT1 ++#define BIT_SD_CMD_EN BIT2 ++#define BIT_SD_DTRX_EN BIT3 ++#define BIT_SD_DAT_EN BIT_SD_DTRX_EN ++#define BIT_SD_DAT_DIR_W BIT4 ++#define BIT_ADMA_EN BIT5 ++#define BIT_JOB_START BIT6 ++#define BIT_CHK_CMD BIT7 ++#define BIT_BUSY_DET_ON BIT8 ++#define BIT_ERR_DET_ON BIT9 ++ ++/* FCIE_SD_STATUS 0x0D */ ++#define BIT_DAT_RD_CERR BIT0 ++#define BIT_SD_R_CRC_ERR BIT_DAT_RD_CERR ++#define BIT_DAT_WR_CERR BIT1 ++#define BIT_SD_W_FAIL BIT_DAT_WR_CERR ++#define BIT_DAT_WR_TOUT BIT2 ++#define BIT_SD_W_CRC_ERR BIT_DAT_WR_TOUT ++#define BIT_CMD_NO_RSP BIT3 ++#define BIT_SD_RSP_TIMEOUT BIT_CMD_NO_RSP ++#define BIT_CMD_RSP_CERR BIT4 ++#define BIT_SD_RSP_CRC_ERR BIT_CMD_RSP_CERR ++#define BIT_DAT_RD_TOUT BIT5 ++//#define BIT_SD_CARD_WP BIT5 ++#define BIT_SD_CARD_BUSY BIT6 ++ ++#define BITS_ERROR (BIT_SD_R_CRC_ERR|BIT_DAT_WR_CERR|BIT_DAT_WR_TOUT|BIT_CMD_NO_RSP|BIT_CMD_RSP_CERR|BIT_DAT_RD_TOUT) ++ ++#define BIT_SD_D0 BIT8 // not correct D0 in 32 bits macron ++//#define BIT_SD_DBUS_MASK (BIT8|BIT9|BIT10|BIT11|BIT12|BIT13|BIT14|BIT15) ++//#define BIT_SD_DBUS_SHIFT 8 ++#define BIT_SD_FCIE_ERR_FLAGS (BIT6-1) ++#define BIT_SD_CARD_D0_ST BIT8 ++#define BIT_SD_CARD_D1_ST BIT9 ++#define BIT_SD_CARD_D2_ST BIT10 ++#define BIT_SD_CARD_D3_ST BIT11 ++#define BIT_SD_CARD_D4_ST BIT12 ++#define BIT_SD_CARD_D5_ST BIT13 ++#define BIT_SD_CARD_D6_ST BIT14 ++#define BIT_SD_CARD_D7_ST BIT15 ++ ++/* FCIE_BOOT_CONFIG 0x0E */ ++#define BIT_EMMC_RSTZ BIT0 ++#define BIT_EMMC_RSTZ_EN BIT1 ++#define BIT_BOOT_MODE_EN BIT2 ++//#define BIT_BOOT_END BIT3 ++ ++/* FCIE_DDR_MODE 0x0F */ ++//#define BIT_DQS_DELAY_CELL_MASK (BIT0|BIT1|BIT2|BIT3) ++//#define BIT_DQS_DELAY_CELL_SHIFT 0 ++#define BIT_MACRO_MODE_MASK (BIT7|BIT8|BIT12|BIT13|BIT14|BIT15) ++#define BIT_8BIT_MACRO_EN BIT7 ++#define BIT_DDR_EN BIT8 ++//#define BIT_SDR200_EN BIT9 ++#define BIT_CLK2_SEL BIT10 ++//#define BIT_SDRIN_BYPASS_EN BIT11 ++#define BIT_32BIT_MACRO_EN BIT12 ++#define BIT_PAD_IN_SEL_SD BIT13 ++#define BIT_FALL_LATCH BIT14 ++#define BIT_PAD_IN_MASK BIT15 ++ ++/* FCIE_TOGGLE_CNT 0x10 */ ++#define BITS_8_MACRO32_DDR52_TOGGLE_CNT 0x110 ++#define BITS_4_MACRO32_DDR52_TOGGLE_CNT 0x210 ++ ++#define BITS_8_MACRO32_HS200_TOGGLE_CNT 0x210 ++#define BITS_4_MACRO32_HS200_TOGGLE_CNT 0x410 ++ ++/* FCIE_SDIO_MOD 0x11 */ ++#define BIT_REG_SDIO_MOD_MASK (BIT1|BIT0) ++#define BIT_SDIO_DET_ON BIT2 ++#define BIT_SDIO_DET_INT_SRC BIT3 ++ ++/* FCIE_RSP_SHIFT_CNT 0x12 */ ++#define BIT_RSP_SHIFT_TUNE_MASK (BIT4 - 1) ++#define BIT_RSP_SHIFT_SEL BIT4 /*SW or HW by default 0*/ ++ ++/* FCIE_RX_SHIFT_CNT 0x13 */ ++#define BIT_RSTOP_SHIFT_TUNE_MASK (BIT4 - 1) ++#define BIT_RSTOP_SHIFT_SEL BIT4 ++#define BIT_WRSTS_SHIFT_TUNE_MASK (BIT8|BIT9|BIT10|BIT11) ++#define BIT_WRSTS_SHIFT_SEL BIT12 ++ ++/* FCIE_ZDEC_CTL0 0x14 */ ++#define BIT_ZDEC_EN BIT0 ++#define BIT_SD2ZDEC_PTR_CLR BIT1 ++ ++/* FCIE_TEST_MODE 0x15 */ ++#define BIT_SDDR1 BIT0 ++#define BIT_DEBUG_MODE_MASK (BIT3|BIT2|BIT1) ++#define BIT_DEBUG_MODE_SHIFT 1 ++#define BIT_BIST_MODE BIT4 ++//#define BIT_DS_TESTEN BIT1 ++//#define BIT_TEST_MODE BIT2 ++//#define BIT_DEBUG_MODE_MASK BIT3|BIT4|BIT5 ++//#define BIT_DEBUG_MODE_SHIFT 3 ++//#define BIT_TEST_MIU BIT6 ++//#define BIT_TEST_MIE BIT7 ++//#define BIT_TEST_MIU_STS BIT8 ++//#define BIT_TEST_MIE_STS BIT9 ++//#define BIT_BIST_MODE BIT10 ++ ++/* FCIE_WR_SBIT_TIMER 0x17 */ ++#define BIT_WR_SBIT_TIMER_MASK (BIT15-1) ++#define BIT_WR_SBIT_TIMER_EN BIT15 ++ ++/* FCIE_RD_SBIT_TIMER 0x18 */ ++#define BIT_RD_SBIT_TIMER_MASK (BIT15-1) ++#define BIT_RD_SBIT_TIMER_EN BIT15 ++ ++ ++/* NC_CIFD_EVENT 0x30 */ ++#define BIT_WBUF_FULL BIT0 ++#define BIT_WBUF_EMPTY_TRI BIT1 ++#define BIT_RBUF_FULL_TRI BIT2 ++#define BIT_RBUF_EMPTY BIT3 ++ ++/* NC_CIFD_INT_EN 0x31 */ ++#define BIT_WBUF_FULL_INT_EN BIT0 ++#define BIT_RBUF_EMPTY_INT_EN BIT1 ++#define BIT_F_WBUF_FULL_INT BIT2 ++#define BIT_F_RBUF_EMPTY_INT BIT3 ++ ++/* FCIE_PWR_SAVE_CTL 0x35 */ ++#define BIT_POWER_SAVE_MODE BIT0 ++#define BIT_SD_POWER_SAVE_RIU BIT1 ++#define BIT_POWER_SAVE_MODE_INT_EN BIT2 ++#define BIT_SD_POWER_SAVE_RST BIT3 ++#define BIT_POWER_SAVE_INT_FORCE BIT4 ++#define BIT_RIU_SAVE_EVENT BIT5 ++#define BIT_RST_SAVE_EVENT BIT6 ++#define BIT_BAT_SAVE_EVENT BIT7 ++#define BIT_BAT_SD_POWER_SAVE_MASK BIT8 ++#define BIT_RST_SD_POWER_SAVE_MASK BIT9 ++#define BIT_POWER_SAVE_MODE_INT BIT15 ++ ++/* FCIE_BOOT 0x37 */ ++#define BIT_NAND_BOOT_EN BIT0 ++#define BIT_BOOTSRAM_ACCESS_SEL BIT1 ++ ++/* FCIE_BOOT 0x39 */ ++#define BIT_DEBUG_MODE_MSK (BIT11|BIT10|BIT9|BIT8) ++#define BIT_DEBUG_MODE_SET (BIT10|BIT8) ++ ++/* FCIE_RESET 0x3F */ ++ ++#define BIT_FCIE_SOFT_RST_n BIT0 ++#define BIT_RST_MIU_STS BIT1 ++#define BIT_RST_MIE_STS BIT2 ++#define BIT_RST_MCU_STS BIT3 ++#define BIT_RST_ECC_STS BIT4 ++//#define BIT_RST_STS_MASK (BIT_RST_MIU_STS | BIT_RST_MIE_STS | BIT_RST_MCU_STS | BIT_RST_ECC_STS) ++#define BIT_RST_STS_MASK (BIT_RST_MIU_STS | BIT_RST_MIE_STS | BIT_RST_MCU_STS) ++#define BIT_NC_DEB_SEL_SHIFT 12 ++#define BIT_NC_DEB_SEL_MASK (BIT15|BIT14|BIT13|BIT12) ++ ++//------------------------------------------------------------------ ++/* ++ * Power Save FIFO Cmd* ++ */ ++#define PWR_BAT_CLASS (0x1 << 13) /* Battery lost class */ ++#define PWR_RST_CLASS (0x1 << 12) /* Reset Class */ ++ ++/* Command Type */ ++#define PWR_CMD_WREG (0x0 << 9) /* Write data */ ++#define PWR_CMD_RDCP (0x1 << 9) /* Read and cmp data. If mismatch, HW retry */ ++#define PWR_CMD_WAIT (0x2 << 9) /* Wait idle, max. 128T */ ++#define PWR_CMD_WINT (0x3 << 9) /* Wait interrupt */ ++#define PWR_CMD_STOP (0x7 << 9) /* Stop */ ++ ++/* RIU Bank */ ++#define PWR_CMD_BK0 (0x0 << 7) ++#define PWR_CMD_BK1 (0x1 << 7) ++#define PWR_CMD_BK2 (0x2 << 7) ++#define PWR_CMD_BK3 (0x3 << 7) ++ ++#define PWR_RIU_ADDR (0x0 << 0) ++ ++#endif /* __EMMC_REG_V5_H__ */ +diff --git a/drivers/mstar/emmc/unify_driver/mmc.lds b/drivers/mstar/emmc/unify_driver/mmc.lds +new file mode 100644 +index 00000000..2e8e3639 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/mmc.lds +@@ -0,0 +1,17 @@ ++SECTIONS ++{ ++ .FCIE.module.text : { *(.text) } ++ .FCIE.module.rodata : { ++ *(.rodata) *(.rodata.*) ++ *(__vermagic) *(__tracepoints_ptrs) *(__markers_strings) *(__tracepoints_strings) ++ *(.rodata1) *(.rio_switch_ops) ++ *(SORT(___ksymtab+*)) *(SORT(___ksymtab_gpl+*)) *(SORT(___ksymtab_unused+*)) *(SORT(___ksymtab_unused_gpl+*)) *(SORT(___ksymtab_gpl_future+*)) ++ *(SORT(___kcrctab+*)) *(SORT(___kcrctab_gpl+*)) *(SORT(___kcrctab_unused+*)) *(SORT(___kcrctab_unused_gpl+*)) *(SORT(___kcrctab_gpl_future+*)) ++ *(__ksymtab_strings) ++ *(.ref.rodata) ++ *(.devinit.rodata) *(.devexit.rodata) ++ *(.cpuinit.rodata) *(.cpuexit.rodata) ++ *(__param) ++ *(__modver) ++ } ++} +diff --git a/drivers/mstar/emmc/unify_driver/mstar_mci.c b/drivers/mstar/emmc/unify_driver/mstar_mci.c +new file mode 100644 +index 00000000..c0addd4b +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/mstar_mci.c +@@ -0,0 +1,1735 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "mstar_mci.h" ++ ++/****************************************************************************** ++ * Defines ++ ******************************************************************************/ ++#define MCI_RETRY_CNT_CMD_TO 100 ++#define MCI_RETRY_CNT_CRC_ERR 200 // avoid stack overflow ++#define MCI_RETRY_CNT_OK_CLK_UP 10 ++ ++/****************************************************************************** ++ * Function Prototypes ++ ******************************************************************************/ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st); ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st); ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st); ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *pMStarHost_st, struct mmc_data *data, struct mstar_mci_host_next *next); ++static void mstar_mci_pre_req(struct mmc_host *pMMCHost_st, struct mmc_request *mrq, bool is_first_req); ++static void mstar_mci_post_req(struct mmc_host * pMMCHost_st,struct mmc_request * mrq,int err); ++#endif ++#endif ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st); ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st); ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st); ++ ++u32 mstar_mci_WaitD0High(u32 u32_us); ++static U32 u32_ok_cnt=0; ++ ++/***************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++/* MSTAR Multimedia Card Interface Operations */ ++static const struct mmc_host_ops sg_mstar_mci_ops = ++{ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ .pre_req = mstar_mci_pre_req, ++ .post_req = mstar_mci_post_req, ++ #endif ++ #endif ++ .request = mstar_mci_request, ++ .set_ios = mstar_mci_set_ios, ++ .get_ro = mstar_mci_get_ro, ++}; ++ ++static struct task_struct *sgp_eMMCThread_st = NULL; ++static ulong wr_seg_size = 0; ++static ulong wr_split_threshold = 0; ++ ++u8 u8_enable_sar5 = 0; ++ ++// =============================== ++// for /sys files ++U32 gu32_pwrsvr_gpio_enable = 0; ++U32 gu32_pwrsvr_gpio_addr = 0; ++U32 gu32_pwrsvr_gpio_bit = 0; ++U32 gu32_pwrsvr_gpio_trigger = 0; ++U32 gu32_emmc_sanitize = 0; ++ ++/***************************************************************************** ++ * for profiling ++ ******************************************************************************/ ++#if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++static struct proc_dir_entry * writefile; ++const char procfs_name[] = "StorageBytes"; ++ ++int procfile_read(char* buffer, char ** buffer_location, off_t offset, ++ int buffer_length, int *eof, void *data) ++{ ++ int ret; ++ if(offset > 0) ++ ret = 0; ++ else ++ ret = sprintf(buffer,"TotalWriteBytes %llu GB %llu MB\nTotalReadBytes %llu GB %llu MB\n", ++ g_eMMCDrv.u64_CNT_TotalWBlk/1024/1024/2, (g_eMMCDrv.u64_CNT_TotalWBlk/1024/2) % 1024, ++ g_eMMCDrv.u64_CNT_TotalRBlk/1024/1024/2, (g_eMMCDrv.u64_CNT_TotalRBlk/1024/2) % 1024); ++ return ret; ++} ++#endif ++ ++/****************************************************************************** ++ * Functions ++ ******************************************************************************/ ++static int mstar_mci_get_dma_dir(struct mmc_data *data) ++{ ++ #if defined(CONFIG_ENABLE_EMMC_ACP) && CONFIG_ENABLE_EMMC_ACP ++ return DMA_ACP; ++ #else ++ if (data->flags & MMC_DATA_WRITE) ++ return DMA_TO_DEVICE; ++ else ++ return DMA_FROM_DEVICE; ++ #endif ++} ++ ++static void mstar_mci_pre_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct scatterlist *pSG_st = 0; ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ //int sg_count = 0; ++ u32 u32_dmalen = 0; ++ //u32 u32_sg_count; ++ dma_addr_t dmaaddr = 0; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pMStarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ pSG_st = &pData_st->sg[0]; ++ dmaaddr = (u32)sg_dma_address(pSG_st); ++ u32_dmalen = sg_dma_len(pSG_st); ++ u32_dmalen = ((u32_dmalen&0x1FF)?1:0) + u32_dmalen/512; ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ eMMC_FCIE_FifoClkRdy(0); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += u32_dmalen; ++ g_eMMCDrv.u32_RBlk_tmp = u32_dmalen; ++ #endif ++ ++} ++ ++static U32 mstar_mci_post_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ int err = eMMC_ST_SUCCESS; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ pSG_st = &(pData_st->sg[0]); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ return err; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ for(i=1; isg_len; i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ pSG_st = &(pData_st->sg[i]); ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT,(dmalen/512)); ++ REG_FCIE_W(FCIE_SDIO_ADDR0,(((u32)dmaaddr) & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1,(((u32)dmaaddr) >> 16)); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, ++ eMMC_READ_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ goto dma_read_end; ++ } ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ ++ // ----------------------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen / 512); ++ g_eMMCDrv.u32_RBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ dma_read_end: ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_RBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinRBlk[g_eMMCDrv.u32_RBlk_tmp]++; ++ else if(g_eMMCDrv.u32_RBlk_tmp > g_eMMCDrv.u32_CNT_MaxRBlk) ++ g_eMMCDrv.u32_CNT_MaxRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ else if(g_eMMCDrv.u32_RBlk_tmp < g_eMMCDrv.u32_CNT_MinRBlk) ++ g_eMMCDrv.u32_CNT_MinRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_RLast += g_eMMCDrv.u32_RBlk_tmp; ++ g_eMMCDrv.u32_RBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ if( !err ) // success ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++ return err; ++} ++ ++ ++static U32 mstar_mci_dma_write(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = 0; ++ struct mmc_data *pData_st = 0; ++ struct scatterlist *pSG_st = 0; ++ int i; ++ //int sg_count; ++ u32 dmalen = 0, split_len = 0, split_unit_len = 0, split_up_len = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_W : TOGGLE_CNT_256_CLK_W); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ pCmd_st = pMStarHost_st->cmd; ++ pData_st = pCmd_st->data; ++ split_unit_len = wr_seg_size << (10 - eMMC_SECTOR_BYTECNT_BITS); ++ split_up_len = wr_split_threshold << (10 - eMMC_SECTOR_BYTECNT_BITS); ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pMStarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ for(i=0; isg_len; i++) ++ { ++ pSG_st = &(pData_st->sg[i]); ++ dmaaddr = sg_dma_address(pSG_st); ++ eMMC_FCIE_MIU0_MIU1_SEL(dmaaddr); ++ dmalen = sg_dma_len(pSG_st)>>eMMC_SECTOR_BYTECNT_BITS; ++ ++ do{ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ split_len = ++ dmalen > g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen ? ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen : dmalen; ++ split_len = ++ split_len == g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen ? ++ split_len>>1 : split_len; ++ #else ++ split_len = dmalen; ++ #endif ++ ++ if(split_unit_len && (!split_up_len || dmalen <= split_up_len)) ++ split_len = dmalen > split_unit_len ? ++ split_unit_len : dmalen; ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, split_len); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, (dmaaddr & 0xFFFF)); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, (dmaaddr >> 16)); ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ if(0==i) ++ eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ ++ eMMC_CheckPowerCut(); ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END, ++ eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ ++ dmalen -= split_len; ++ dmaaddr += split_len << eMMC_SECTOR_BYTECNT_BITS; ++ ++ // ----------------------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalWBlk += (split_len / 512); ++ g_eMMCDrv.u32_WBlk_tmp += (split_len / 512); ++ #endif ++ ++ }while(dmalen > 0); ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ } ++ ++dma_write_end: ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_WBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinWBlk[g_eMMCDrv.u32_WBlk_tmp]++; ++ else if(g_eMMCDrv.u32_WBlk_tmp > g_eMMCDrv.u32_CNT_MaxWBlk) ++ g_eMMCDrv.u32_CNT_MaxWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ else if(g_eMMCDrv.u32_WBlk_tmp < g_eMMCDrv.u32_CNT_MinWBlk) ++ g_eMMCDrv.u32_CNT_MinWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_WLast += g_eMMCDrv.u32_WBlk_tmp; ++ g_eMMCDrv.u32_WBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if( !err ) ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++ return err; ++} ++ ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ u16 u16_st, u16_i; ++ u8 *pTemp; ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ static u32 u32_retry_cnt=0, u32_run_cnt=0; ++ ++ u32_run_cnt++; ++ // ---------------------------------- ++ // retrun response from FCIE to mmc driver ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3 - (u16_i % 4)) + (4 * (u16_i / 4))] = ++ (u8)(REG_FCIE(FCIE1_BASE+(((u16_i+1)/2)*4)) >> (8*((u16_i+1)%2))); ++ } ++ #if 0 ++ eMMC_debug(0,0,"------------------\n"); ++ eMMC_debug(0,1,"resp[0]: %08Xh\n", pCmd_st->resp[0]); ++ eMMC_debug(0,1,"CIFC: %04Xh %04Xh %04Xh \n", REG_FCIE(FCIE_CIFC_BASE_ADDR), ++ REG_FCIE(FCIE_CIFC_BASE_ADDR+4), REG_FCIE(FCIE_CIFC_BASE_ADDR+8)); ++ //eMMC_dump_mem(pTemp, 0x10); ++ eMMC_debug(0,0,"------------------\n"); ++ #endif ++ ++ // ---------------------------------- ++ u16_st = REG_FCIE(FCIE_SD_STATUS); ++ if((u16_st & BIT_SD_FCIE_ERR_FLAGS) /*|| mstar_SD_CardChange()*/ ++ || (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY))// || ((mmc_resp_type(pCmd_st)==MMC_RSP_R1) && (pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY))) ++ { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ ++ if((u16_st & BIT_SD_RSP_CRC_ERR) && !(mmc_resp_type(pCmd_st) & MMC_RSP_CRC)) ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ else ++ { ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: ST:%Xh, CMD:%u, retry: %u, flag: %Xh, R1 err: %Xh\n", ++ u16_st, pCmd_st->opcode, u32_retry_cnt, g_eMMCDrv.u32_DrvFlag, ++ pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY); ++ ++ u32_ok_cnt = 0; ++ if(u32_retry_cnt++ >= MCI_RETRY_CNT_CRC_ERR) ++ eMMC_FCIE_ErrHandler_Stop(); // fatal error ++ ++ if(25==pCmd_st->opcode || 12==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_hw_timer_sleep(1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ ++ if(0 != pCmd_st->data) ++ { ++ eMMC_FCIE_ErrHandler_Retry(); // slow dwon clock ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ } ++ else // for CMD12 ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: no data, just reset eMMC. \n"); ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ if(0==u32_retry_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: retry ok \n"); ++ return; ++ } ++ ++ //----------------------------------------- ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: ST:%Xh, CMD:%u, retry:%u \n", ++ u16_st, pCmd_st->opcode, pCmd_st->retries); ++ #endif ++ ++ // should be trivial ++ if(u16_st & (BIT_SD_RSP_TIMEOUT | BIT_SD_W_FAIL)) ++ pCmd_st->error = -ETIMEDOUT; ++ else if(u16_st & (BIT_SD_RSP_CRC_ERR | BIT_SD_R_CRC_ERR | BIT_SD_W_CRC_ERR)) ++ pCmd_st->error = -EILSEQ; ++ else ++ pCmd_st->error = -EIO; ++ } ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ ++ u32_retry_cnt = 0; ++ } ++ ++ if((pCmd_st->opcode == 17) || (pCmd_st->opcode == 18) //read ++ ||(pCmd_st->opcode == 24) || (pCmd_st->opcode == 25) //write ++ ||(pCmd_st->opcode == 12)) //stop transmission ++ { ++ if(pCmd_st->resp[0] & eMMC_ERR_R1_31_0) ++ { ++ pCmd_st->error |= -EIO; ++ if(pCmd_st->opcode == 12) ++ eMMC_debug(0,0, "eMMC Warn: CMD12 R1 error: %Xh \n", ++ pCmd_st->resp[0]); ++ else ++ eMMC_debug(0,0, "eMMC Warn: CMD%u R1 error: %Xh, arg %08x, blocks %08x\n", ++ pCmd_st->opcode, pCmd_st->resp[0], pCmd_st->arg, pCmd_st->data->blocks); ++ } ++ } ++ ++ #if 0 ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt) ++ { ++ eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++} ++ ++#define WAIT_D0H_POLLING_TIME HW_TIMER_DELAY_100us ++u32 mstar_mci_WaitD0High(u32 u32_us) ++{ ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ ++ REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_BUSY_DET_ON); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // enable busy int ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_SD_BUSY_END); ++ #endif ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_BUSY_END,u32_us) != eMMC_ST_SUCCESS) ++ { ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ return eMMC_ST_SUCCESS; ++ #else ++ u32 u32_cnt, u32_wait; ++ ++ for(u32_cnt=0; u32_cnt HW_TIMER_DELAY_1ms) ++ { ++ //msleep(1); ++ //schedule_hrtimeout is more precise and can reduce idle time of emmc ++ { ++ ktime_t expires = ktime_add_ns(ktime_get(), 1000 * 1000); ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ schedule_hrtimeout(&expires, HRTIMER_MODE_ABS); ++ } ++ u32_cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ #endif ++} ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static void mstar_mci_send_data(struct work_struct *work) ++{ ++ struct mstar_mci_host *pMStarHost_st = container_of(work, struct mstar_mci_host, async_work); ++ struct mmc_command *pCmd_st; ++ struct mmc_data *pData_st; ++ static u8 u8_retry_data=0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if( !pMStarHost_st ) ++ return; ++ ++ pCmd_st = pMStarHost_st->cmd; ++ ++ if( !pCmd_st ) ++ return; ++ ++ pData_st = pCmd_st->data; ++ ++ if( !pData_st ) ++ return; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pMStarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ err = mstar_mci_post_dma_read(pMStarHost_st); ++ } ++ ++ if( err ) ++ { ++ u32_ok_cnt = 0; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w, cmd.%u arg.%Xh, ST: %Xh or TO\n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r, cmd.%u arg.%Xh, ST: %Xh or TO \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ } ++ else ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ ++ u8_retry_data =0; ++ } ++} ++#endif ++ ++static void mstar_mci_send_command ++( ++ struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st ++) ++{ ++ struct mmc_data *pData_st; ++ u32 u32_mie_int=0, u32_sd_ctl=0, u32_sd_mode; ++ u8 u8_retry_cmd=0, u8_retry_D0H=0; ++ ++ #if !(defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO) ++ u8 u8_retry_data=0; ++ u32 err = 0; ++ #endif ++ ++ LABEL_SEND_CMD: ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ u32_sd_mode = g_eMMCDrv.u16_Reg10_Mode; ++ pMStarHost_st->cmd = pCmd_st; ++ pData_st = pCmd_st->data; ++ ++ eMMC_FCIE_ClearEvents(); ++ if(12!=pCmd_st->opcode) ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(HW_TIMER_DELAY_500ms)) ++ { ++ u32_ok_cnt = 0; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ u8_retry_D0H++; ++ if(u8_retry_D0H < 10) ++ { ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ if(u8_retry_D0H) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: wait D0 H [ok]\n"); ++ u8_retry_D0H = 0; ++ } ++ ++ if(pData_st) ++ { ++ pData_st->bytes_xfered = 0; ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE|(u16)pData_st->blksz); ++ ++ if (pData_st->flags & MMC_DATA_READ) ++ { ++ u32_sd_ctl |= BIT_SD_DAT_EN; ++ ++ // enable stoping read clock when using scatter list DMA ++ //if(pData_st->sg_len > 1) ++ if(pCmd_st->opcode == 18) ++ u32_sd_mode |= BIT_SD_DMA_R_CLK_STOP; ++ else ++ u32_sd_mode &= ~BIT_SD_DMA_R_CLK_STOP; ++ ++ mstar_mci_pre_dma_read(pMStarHost_st); ++ } ++ } ++ ++ u32_sd_ctl |= BIT_SD_CMD_EN; ++ u32_mie_int |= BIT_SD_CMD_END; ++ REG_FCIE_W(FCIE_CIFC_ADDR(0), (((pCmd_st->arg >> 24)<<8) | (0x40|pCmd_st->opcode))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), ((pCmd_st->arg & 0xFF00) | ((pCmd_st->arg>>16)&0xFF))); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), (pCmd_st->arg & 0xFF)); ++ ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_NONE) ++ { ++ u32_sd_ctl &= ~BIT_SD_RSP_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 0); ++ } ++ else ++ { ++ u32_sd_ctl |= BIT_SD_RSP_EN; ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_R2) ++ { ++ u32_sd_ctl |= BIT_SD_RSPR2_EN; ++ REG_FCIE_W(FCIE_RSP_SIZE, 16); /* (136-8)/8 */ ++ } ++ else ++ { ++ REG_FCIE_W(FCIE_RSP_SIZE, 5); /*(48-8)/8 */ ++ } ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC: INT_EN: %Xh\n", u32_mie_int); ++ REG_FCIE_W(FCIE_MIE_INT_EN, u32_mie_int); ++ #endif ++ ++ #if 0 ++ //eMMC_debug(0,0,"\n"); ++ eMMC_debug(0,0,"cmd:%u, arg:%Xh, buf:%Xh, ST:%Xh, mode:%Xh, ctrl:%Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, (u32)pData_st, ++ REG_FCIE(FCIE_SD_STATUS), u32_sd_mode, u32_sd_ctl); ++ //eMMC_debug(0,0,"cmd:%u arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ //while(1); ++ #endif ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ switch(pCmd_st->opcode) ++ { ++ case 17: ++ case 18: ++ if(18 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD18++; ++ else if(17 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD17++; ++ ++ if(g_eMMCDrv.u32_Addr_RLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_RHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_RLast = pCmd_st->arg; ++ ++ case 24: ++ case 25: ++ if(25 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD25++; ++ else if(24 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD24++; ++ ++ if(g_eMMCDrv.u32_Addr_WLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_WHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_WLast = pCmd_st->arg; ++ } ++ ++ #endif ++ ++ // ----------------------------------- ++ if((pCmd_st->opcode==12)||(pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ { ++ eMMC_CheckPowerCut(); ++ } ++ ++ REG_FCIE_W(FCIE_SD_MODE, u32_sd_mode); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl); ++ // [FIXME]: retry and timing, and omre... ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, ++ HW_TIMER_DELAY_1s) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)))// || 0==u8_retry_cmd) ++ { ++ // ------------------------------------ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if(NULL==pData_st) // no data, no retry ++ { ++ mstar_mci_completed_command(pMStarHost_st); ++ return; ++ } ++ #endif ++ ++ // ------------------------------------ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: cmd.%u arg.%Xh St: %Xh, retry %u \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS), u8_retry_cmd); ++ if(u8_retry_cmd < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_cmd++; ++ if(12==pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ #endif ++ return; ++ } ++ ++ if(25==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ if(u8_retry_cmd) ++ eMMC_debug(0,0,"eMMC: CMD retry ok\n"); ++ ++ if(pData_st) ++ { ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ schedule_work(&pMStarHost_st->async_work); ++ #else ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pMStarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ err = mstar_mci_post_dma_read(pMStarHost_st); ++ } ++ ++ if( err ) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ } ++ #endif ++ } ++ else ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd without data ++ ++ if( pCmd_st->opcode == 23 ) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); // CMD18 or CMD25 ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++ ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *host, struct mmc_data *data, struct mstar_mci_host_next *next) ++{ ++ int dma_len; ++ ++ /* Check if next job is already prepared */ ++ if (next || (!next && data->host_cookie != host->next_data.cookie)) ++ { ++ dma_len = dma_map_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ else ++ { ++ dma_len = host->next_data.dma_len; ++ host->next_data.dma_len = 0; ++ } ++ ++ if (dma_len == 0) ++ return -EINVAL; ++ ++ if (next) ++ { ++ next->dma_len = dma_len; ++ data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; ++ } ++ ++ return 0; ++} ++ ++ ++static void mstar_mci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, bool is_first_req) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if( mrq->data->host_cookie ) ++ { ++ mrq->data->host_cookie = 0; ++ return; ++ } ++ ++ if (mstar_mci_pre_dma_transfer(host, mrq->data, &host->next_data)) ++ mrq->data->host_cookie = 0; ++ ++} ++ ++static void mstar_mci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ struct mmc_data *data = mrq->data; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if (data->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ ++ data->host_cookie = 0; ++} ++#endif ++#endif ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st) ++{ ++ struct mstar_mci_host *pMStarHost_st; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ if (!pMRQ_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMRQ_st is NULL \n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return; ++ } ++ ++ pMStarHost_st->request = pMRQ_st; ++ ++ // --------------------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ eMMC_Init_Device(); ++ } ++ ++ #ifdef CONFIG_MP_EMMC_TRIM ++ switch(pMStarHost_st->request->cmd->opcode) ++ { ++ case 35: ++ eMMC_CMD35_CMD36(pMStarHost_st->request->cmd->arg, 35); ++ break; ++ case 36: ++ eMMC_CMD35_CMD36(pMStarHost_st->request->cmd->arg, 36); ++ break; ++ case 38: ++ eMMC_CMD38(); ++ break; ++ default: ++ break; ++ } ++ #endif ++ ++ if(NULL == pMStarHost_st->request->cmd->data && 6 != pMStarHost_st->request->cmd->opcode) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ if(6 == pMStarHost_st->request->cmd->opcode && ++ (((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB70000)|| ++ ((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB90000))) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ #endif ++ // --------------------------------------------- ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++} ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ u16 au16_cifc[32], u16_i; ++ u8 *pTemp; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != eMMC_ReturnRsp((u8*)au16_cifc, (u8)pCmd_st->opcode)) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ //eMMC_debug(0,0,"eMMC Info: no rsp\n"); ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3-(u16_i%4)) + 4*(u16_i/4)] = ++ (u8)(au16_cifc[(u16_i+1)/2] >> 8*((u16_i+1)%2)); ++ } ++ #if 0 ++ eMMC_debug(0,1,"------------------\n"); ++ eMMC_dump_mem((u8*)&(pCmd_st->resp[0]), 0x10); ++ eMMC_debug(0,1,"------------------\n"); ++ #endif ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++} ++#endif ++ ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st) ++{ ++ /* Define Local Variables */ ++ struct mstar_mci_host *pMStarHost_st; ++ static u8 u8_IfLock=0; ++ ++ if(0 == (REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ //eMMC_debug(0,1,"lock\n"); ++ } ++ ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ goto LABEL_END; ++ } ++ if (!pIOS_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pIOS_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "eMMC: clock: %u, bus_width %Xh \n", ++ // pIOS_st->clock, pIOS_st->bus_width); ++ ++ // ---------------------------------- ++ if (pIOS_st->clock == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "eMMC Warn: disable clk \n"); ++ eMMC_clock_gating(); ++ } ++ // ---------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ else ++ { eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ } ++ pMStarHost_st->sd_mod = (BIT_SD_DEFAULT_MODE_REG & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ #else ++ // ---------------------------------- ++ else ++ { ++ pMStarHost_st->sd_mod = BIT_SD_DEFAULT_MODE_REG; ++ ++ if(pIOS_st->clock > CLK_400KHz) ++ { ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ } ++ else ++ { eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ } ++ ++ if (pIOS_st->bus_width == MMC_BUS_WIDTH_8) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ } ++ else if (pIOS_st->bus_width == MMC_BUS_WIDTH_4) ++ { ++ g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_4; ++ } ++ else ++ { g_eMMCDrv.u16_Reg10_Mode = (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK); ++ } ++ #endif ++ ++ LABEL_END: ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ //eMMC_debug(0,1,"unlock\n"); ++ } ++} ++ ++static s32 mstar_mci_get_ro(struct mmc_host *pMMCHost_st) ++{ ++ s32 read_only; ++ ++ read_only = 0; ++ if(!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ read_only = -EINVAL; ++ } ++ ++ return read_only; ++} ++ ++//======================================================================= ++static void mstar_mci_enable(struct mstar_mci_host *pMStarHost_st) ++{ ++ u32 u32_err; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ eMMC_PlatformInit(); ++ ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ ++ u32_err = eMMC_FCIE_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Init fail: %Xh \n", u32_err); ++} ++ ++static void mstar_mci_disable(struct mstar_mci_host *pMStarHost_st) ++{ ++ u32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_Reset fail: %Xh\n", u32_err); ++ eMMC_clock_gating(); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_trigger_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_trigger); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_trigger_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_trigger = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_trigger)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_trigger > 1) ++ return -EINVAL; ++ gu32_pwrsvr_gpio_trigger = u32_pwrsvr_gpio_trigger; ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_trigger, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_trigger_show, ++ fcie_pwrsvr_gpio_trigger_store); ++ ++static ssize_t fcie_pwrsvr_gpio_bit_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_bit); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_bit_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_bit = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_bit)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_bit) ++ { ++ if(u32_pwrsvr_gpio_bit > 0xF) ++ return -EINVAL; ++ gu32_pwrsvr_gpio_bit = u32_pwrsvr_gpio_bit; ++ } ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_bit, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_bit_show, ++ fcie_pwrsvr_gpio_bit_store); ++ ++static ssize_t fcie_pwrsvr_gpio_addr_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "0x%X\n", gu32_pwrsvr_gpio_addr); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_addr_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_addr = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_addr)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_addr) ++ gu32_pwrsvr_gpio_addr = u32_pwrsvr_gpio_addr; ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_addr, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_addr_show, ++ fcie_pwrsvr_gpio_addr_store); ++ ++static ssize_t fcie_pwrsvr_gpio_enable_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_enable); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_enable_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_enable = 0; ++ //struct mmc_card *card = mmc_dev_to_card(dev); ++ ++ if(u8_enable_sar5) ++ return count; ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_enable)) ++ return -EINVAL; ++ if(u32_pwrsvr_gpio_enable) ++ gu32_pwrsvr_gpio_enable = u32_pwrsvr_gpio_enable; ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_enable, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_enable_show, ++ fcie_pwrsvr_gpio_enable_store); ++ ++ ++static ssize_t emmc_sanitize_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_emmc_sanitize); ++} ++ ++static ssize_t emmc_sanitize_store(struct device *dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_temp = 0; ++ ++ if(kstrtoul(buf, 0, &u32_temp)) ++ return -EINVAL; ++ ++ gu32_emmc_sanitize = u32_temp; ++ //printk("%Xh\n", gu32_emmc_sanitize); ++ ++ if(gu32_emmc_sanitize) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: santizing ...\n"); ++ eMMC_Sanitize(0xAA); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: done\n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(emmc_sanitize, ++ S_IRUSR | S_IWUSR, ++ emmc_sanitize_show, ++ emmc_sanitize_store); ++ ++static struct attribute *mstar_mci_attr[] = ++{ ++ &dev_attr_fcie_pwrsvr_gpio_enable.attr, ++ &dev_attr_fcie_pwrsvr_gpio_addr.attr, ++ &dev_attr_fcie_pwrsvr_gpio_bit.attr, ++ &dev_attr_fcie_pwrsvr_gpio_trigger.attr, ++ &dev_attr_emmc_sanitize.attr, ++ NULL, ++}; ++ ++static struct attribute_group mstar_mci_attr_grp = ++{ ++ .attrs = mstar_mci_attr, ++}; ++ ++static s32 mstar_mci_probe(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pMStarHost_st; ++ s32 s32_ret; ++ ++ #if IF_FCIE_SHARE_IP && defined(CONFIG_MSTAR_SDMMC) ++ eMMC_debug(0,0,"eMMC: has SD 0722\n"); ++ #else ++ eMMC_debug(0,0,"eMMC: no SD 0722\n"); ++ #endif ++ ++ // -------------------------------- ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pDev_st is NULL \n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st = 0; ++ pMStarHost_st = 0; ++ s32_ret = 0; ++ g_eMMCDrv.u8_PadType = FCIE_DEFAULT_PAD; ++ g_eMMCDrv.u16_ClkRegVal = FCIE_SLOWEST_CLK; ++ // -------------------------------- ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ mstar_mci_enable(pMStarHost_st); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ pMMCHost_st = mmc_alloc_host(sizeof(struct mstar_mci_host), &pDev_st->dev); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: mmc_alloc_host fail \n"); ++ s32_ret = -ENOMEM; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st->ops = &sg_mstar_mci_ops; ++ // [FIXME]-> ++ pMMCHost_st->f_min = CLK_400KHz; ++ pMMCHost_st->f_max = CLK_200MHz; ++ pMMCHost_st->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | \ ++ MMC_VDD_31_32 | MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; ++ ++ pMMCHost_st->max_blk_count = BIT_SD_JOB_BLK_CNT_MASK; ++ pMMCHost_st->max_blk_size = 512; /* sector */ ++ pMMCHost_st->max_req_size = pMMCHost_st->max_blk_count * pMMCHost_st->max_blk_size; ++ ++ pMMCHost_st->max_seg_size = pMMCHost_st->max_req_size; ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,20) ++ pMMCHost_st->max_phys_segs = 511; ++ pMMCHost_st->max_hw_segs = 511; ++ #else ++ pMMCHost_st->max_segs = 511; // (2^12-1)*512/4096 ++ #endif ++ //--------------------------------------- ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ pMStarHost_st->mmc = pMMCHost_st; ++ //--------------------------------------- ++ ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_NONREMOVABLE; ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ pMMCHost_st->caps |= MMC_CAP_CMD23; ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_TRIM ++ pMMCHost_st->caps |= MMC_CAP_ERASE; ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_CACHE ++ pMMCHost_st->caps2 |= MMC_CAP2_CACHE_CTRL; ++ #endif ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(3,1,10) ++ pMMCHost_st->caps2 |= MMC_CAP2_NO_SLEEP_CMD; ++ #endif ++ pMStarHost_st->baseaddr = (void __iomem *)FCIE0_BASE; ++ // <-[FIXME] ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ pMStarHost_st->next_data.cookie = 1; ++ INIT_WORK(&pMStarHost_st->async_work, mstar_mci_send_data); ++ #endif ++ #endif ++ ++ mmc_add_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, pMMCHost_st); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ s32_ret = request_irq(E_IRQ_NFIE, eMMC_FCIE_IRQ, IRQF_SHARED, DRIVER_NAME, pMStarHost_st); ++ if (s32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: request_irq fail \n"); ++ mmc_free_host(pMMCHost_st); ++ goto LABEL_END; ++ } ++ #endif ++ ++ // For getting and showing device attributes from/to user space. ++ s32_ret = sysfs_create_group(&pDev_st->dev.kobj, &mstar_mci_attr_grp); ++ ++ sgp_eMMCThread_st = kthread_create(mstar_mci_Housekeep, NULL, "eMMC_bg_thread"); ++ if(IS_ERR(sgp_eMMCThread_st)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: create thread fail \n"); ++ return PTR_ERR(sgp_eMMCThread_st); ++ } ++ wake_up_process(sgp_eMMCThread_st); ++ ++ #if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++ g_eMMCDrv.u64_CNT_TotalRBlk = 0; ++ g_eMMCDrv.u64_CNT_TotalWBlk = 0; ++ writefile = create_proc_entry (procfs_name, 0644, NULL); ++ if(writefile == NULL) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Err: Can not initialize /proc/%s\n", procfs_name); ++ else ++ { ++ writefile->read_proc = procfile_read; ++ writefile->mode = S_IFREG | S_IRUGO; ++ writefile->uid = 0; ++ writefile->gid = 0; ++ writefile->size = 0x10; ++ } ++ #endif ++ ++ LABEL_END: ++ return s32_ret; ++} ++ ++static s32 __exit mstar_mci_remove(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ struct mstar_mci_host *pMStarHost_st; ++ s32 s32_ret; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ s32_ret = 0; ++ ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pDev_st is NULL\n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pMMCHost_st is NULL\n"); ++ s32_ret= -1; ++ goto LABEL_END; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove +\n"); ++ ++ mmc_remove_host(pMMCHost_st); ++ ++ mstar_mci_disable(pMStarHost_st); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ free_irq(pMStarHost_st->irq, pMStarHost_st); ++ #endif ++ ++ mmc_free_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, NULL); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove -\n"); ++ ++ LABEL_END: ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if(sgp_eMMCThread_st) ++ kthread_stop(sgp_eMMCThread_st); ++ ++ return s32_ret; ++} ++ ++#ifdef CONFIG_PM ++static s32 mstar_mci_suspend(struct platform_device *pDev_st, pm_message_t state) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ // wait for D0 high before losing eMMC Vcc ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_PlatformDeinit(); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if (pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend + \n"); ++ ret = mmc_suspend_host(pMMCHost_st); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend -, %Xh\n", ret); ++ return ret; ++} ++ ++static s32 mstar_mci_resume(struct platform_device *pDev_st) ++{ ++ struct mmc_host *pMMCHost_st; ++ s32 ret; ++ static u8 u8_IfLock=0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume +\n"); ++ pMMCHost_st = platform_get_drvdata(pDev_st); ++ ret = 0; ++ ++ if(0 == (REG_FCIE(FCIE_REG16h) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"lock\n"); ++ } ++ ++ mstar_mci_enable(mmc_priv(pMMCHost_st)); ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"unlock\n"); ++ } ++ ++ if (pMMCHost_st) ++ { ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume +\n"); ++ ret = mmc_resume_host(pMMCHost_st); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume -\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, resume -, %Xh\n", ret); ++ return ret; ++} ++#endif /* End ifdef CONFIG_PM */ ++ ++/****************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++static struct platform_driver sg_mstar_mci_driver = ++{ ++ .probe = mstar_mci_probe, ++ .remove = __exit_p(mstar_mci_remove), ++ ++ #ifdef CONFIG_PM ++ .suspend = mstar_mci_suspend, ++ .resume = mstar_mci_resume, ++ #endif ++ ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++struct platform_device sg_mstar_emmc_device_st = ++{ ++ .name = DRIVER_NAME, ++ .id = 0, ++ .resource = NULL, ++ .num_resources = 0, ++}; ++ ++/****************************************************************************** ++ * Init & Exit Modules ++ ******************************************************************************/ ++static s32 __init mstar_mci_init(void) ++{ ++ int err = 0; ++ u16 u16_regval = 0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"\n"); ++ ++ u16_regval = REG_FCIE(FCIE_REG16h); ++ ++ if( (u16_regval & BIT_KERN_CHK_NAND_EMMC) == BIT_KERN_CHK_NAND_EMMC ) ++ { ++ if( (u16_regval & BIT_KERN_EMMC) != BIT_KERN_EMMC ) ++ return 0; ++ } ++ ++ if((err = platform_device_register(&sg_mstar_emmc_device_st)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ if((err = platform_driver_register(&sg_mstar_mci_driver)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ return err; ++} ++ ++static void __exit mstar_mci_exit(void) ++{ ++ platform_driver_unregister(&sg_mstar_mci_driver); ++} ++ ++static int __init write_seg_size_setup(char *str) ++{ ++ wr_seg_size = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++ ++static int __init write_seg_theshold_setup(char *str) ++{ ++ wr_split_threshold = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++ ++/* SAR5=ON in set_config will enable this feature */ ++static int __init sar5_setup_for_pwr_cut(char * str) ++{ ++ if(str != NULL) ++ { ++ printk(KERN_CRIT"SAR5=%s", str); ++ if(strcmp((const char *) str, "ON") == 0) ++ u8_enable_sar5 = 1; ++ } ++ ++ return 0; ++} ++early_param("SAR5", sar5_setup_for_pwr_cut); ++ ++__setup("mmc_wrsize=", write_seg_size_setup); ++__setup("mmc_wrupsize=", write_seg_theshold_setup); ++ ++subsys_initcall(mstar_mci_init); ++//module_init(mstar_mci_init); ++module_exit(mstar_mci_exit); ++ ++MODULE_LICENSE("non-GPL"); ++MODULE_DESCRIPTION("Mstar Multimedia Card Interface driver"); ++MODULE_AUTHOR("Benson.Hsiao"); +diff --git a/drivers/mstar/emmc/unify_driver/mstar_mci.h b/drivers/mstar/emmc/unify_driver/mstar_mci.h +new file mode 100644 +index 00000000..4f1fcb12 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/mstar_mci.h +@@ -0,0 +1,72 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef MSTAR_MCI_H ++#define MSTAR_MCI_H ++ ++#include "eMMC.h" ++ ++/****************************************************************************** ++* Function define for this driver ++******************************************************************************/ ++ ++/****************************************************************************** ++* Register Address Base ++******************************************************************************/ ++#define CLK_400KHz 400*1000 ++#define CLK_200MHz 200*1000*1000 ++ ++#define eMMC_GENERIC_WAIT_TIME (HW_TIMER_DELAY_1s*10) ++#define eMMC_READ_WAIT_TIME (HW_TIMER_DELAY_500ms) ++ ++/****************************************************************************** ++* Low level type for this driver ++******************************************************************************/ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++struct mstar_mci_host_next ++{ ++ unsigned int dma_len; ++ s32 cookie; ++}; ++#endif ++#endif ++ ++struct mstar_mci_host ++{ ++ struct mmc_host *mmc; ++ struct mmc_command *cmd; ++ struct mmc_request *request; ++ ++ void __iomem *baseaddr; ++ s32 irq; ++ ++ u16 sd_clk; ++ u16 sd_mod; ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,20) ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ struct mstar_mci_host_next next_data; ++ struct work_struct async_work; ++ #endif ++ #endif ++ char name[16]; ++}; /* struct mstar_mci_host*/ ++ ++#define MSTAR_MCI_NAME "MSTAR_MCI" ++ ++#endif +diff --git a/drivers/mstar/emmc/unify_driver/mstar_mci_v5.c b/drivers/mstar/emmc/unify_driver/mstar_mci_v5.c +new file mode 100644 +index 00000000..1b0b959c +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/mstar_mci_v5.c +@@ -0,0 +1,3040 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "mstar_mci.h" ++#include "linux/mmc/mmc.h" ++ ++/****************************************************************************** ++ * Defines ++ ******************************************************************************/ ++#define MCI_RETRY_CNT_CMD_TO 100 ++#define MCI_RETRY_CNT_CRC_ERR 200 // avoid stack overflow ++#define MCI_RETRY_CNT_OK_CLK_UP 10 ++ ++/****************************************************************************** ++ * Function Prototypes ++ ******************************************************************************/ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st); ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st); ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st); ++#endif ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *pMStarHost_st, struct mmc_data *data, struct mstar_mci_host_next *next); ++#endif ++ ++u32 mstar_mci_WaitD0High(u32 u32_us); ++ ++ ++/***************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++static U32 u32_ok_cnt = 0; ++static struct task_struct *sgp_eMMCThread_st = NULL; ++#if 0 ++static ulong wr_seg_size = 0; ++static ulong wr_split_threshold = 0; ++#endif ++u8 u8_enable_sar5 = 0; ++U32 MIU0_BUS_ADDR=0; ++#if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++static int fcie_irq = 0; ++#endif ++// =============================== ++// for /sys files ++#if 0 ++U32 gu32_pwrsvr_gpio_enable = 0; ++U32 gu32_pwrsvr_gpio_addr = 0; ++U32 gu32_pwrsvr_gpio_bit = 0; ++U32 gu32_pwrsvr_gpio_trigger = 0; ++U32 gu32_emmc_sanitize = 0; ++#endif ++U32 gu32_eMMC_read_log_enable =0; ++U32 gu32_eMMC_write_log_enable =0; ++U32 gu32_eMMC_monitor_enable=0; ++U32 gu32_eMMC_read_cnt =0; ++U32 gu32_eMMC_write_cnt =0; ++static unsigned long long gu64_jiffies_org; ++static unsigned long long gu64_jiffies_write=0,gu64_jiffies_read=0; ++ ++U16 u16_OldPLLClkParam=0xFFFF; ++U16 u16_OldPLLDLLClkParam=0xFFFF; ++ ++#define FCIE_ADMA_DESC_COUNT 512 ++struct _AdmaDescriptor eMMC_ALIGN0 gAdmaDesc_st[FCIE_ADMA_DESC_COUNT] eMMC_ALIGN1; ++ ++#if defined(CONFIG_OF) ++struct clk_data{ ++ int num_parents; ++ struct clk **clk_fcie; ++ //struct clk *clk_ecc; ++}; ++struct clk_data* clkdata; ++#endif ++ ++ ++/***************************************************************************** ++ * for profiling ++ ******************************************************************************/ ++#if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++static struct proc_dir_entry * writefile; ++const char procfs_name[] = "StorageBytes"; ++ ++int procfile_read(char* buffer, char ** buffer_location, off_t offset, ++ int buffer_length, int *eof, void *data) ++{ ++ int ret; ++ ++ if(offset > 0) ++ ret = 0; ++ else ++ { ++ ret = sprintf(buffer, ++ "TotalWriteBytes %llu GB %llu MB\nTotalReadBytes %llu GB %llu MB\n", ++ g_eMMCDrv.u64_CNT_TotalWBlk/1024/1024/2, ++ (g_eMMCDrv.u64_CNT_TotalWBlk/1024/2) % 1024, ++ g_eMMCDrv.u64_CNT_TotalRBlk/1024/1024/2, ++ (g_eMMCDrv.u64_CNT_TotalRBlk/1024/2) % 1024); ++ } ++ ++ return ret; ++} ++#endif ++ ++/****************************************************************************** ++ * Functions ++ ******************************************************************************/ ++static int mstar_mci_get_dma_dir(struct mmc_data *data) ++{ ++ #if defined(CONFIG_ENABLE_EMMC_ACP) && CONFIG_ENABLE_EMMC_ACP ++ ++ return DMA_ACP; ++ ++ #else ++ ++ if (data->flags & MMC_DATA_WRITE) ++ return DMA_TO_DEVICE; ++ else ++ return DMA_FROM_DEVICE; ++ ++ #endif ++} ++ ++#if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++static int mstar_mci_config_ecsd(struct mmc_data *pData_st) ++{ ++ struct scatterlist *pSG_st = 0; ++ dma_addr_t dmaaddr = 0; ++ int err = 0; ++ u8 *pBuf; ++ int i; ++ ++ if( !pData_st ) ++ { ++ return -EINVAL; ++ } ++ ++ if(0 ==(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ pSG_st = &pData_st->sg[0]; ++ dmaaddr = sg_dma_address(pSG_st); ++ ++ pBuf = (u8*)phys_to_virt(dmaaddr); ++ ++ for(i=0; i<512; i++) ++ { ++ if( (i&0xF) == 0x0 ) eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%03X: ", i); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%02X ", pBuf[i]); ++ if( (i&0xF) == 0xF ) eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "\n"); ++ } ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((pBuf[215]<<24)| ++ (pBuf[214]<<16)| ++ (pBuf[213]<< 8)| ++ (pBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = pBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ if(!g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = pBuf[183]; ++ ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ } ++ ++ //-------------------------------- ++ if(pBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(pBuf[503]&BIT0) // HPI ++ { ++ if(pBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ } ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(pBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = pBuf[222]; ++ #else ++ if((pBuf[503]&BIT0) && 1==pBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(pBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = pBuf[222]; ++ else ++ { ++ //eMMC_debug(0,1,"eMMC Warn: not support dynamic Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = pBuf[181]; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ECSD184_Stroe_Support = pBuf[184]; ++ g_eMMCDrv.u8_ECSD185_HsTiming = pBuf[185]; ++ g_eMMCDrv.u8_ECSD192_Ver = pBuf[192]; ++ g_eMMCDrv.u8_ECSD196_DevType = pBuf[196]; ++ g_eMMCDrv.u8_ECSD197_DriverStrength = pBuf[197]; ++ g_eMMCDrv.u8_ECSD248_CMD6TO = pBuf[248]; ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO = pBuf[247]; ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl = pBuf[34]; ++ ++ //for GP Partition ++ g_eMMCDrv.u8_ECSD160_PartSupField = pBuf[160]; ++ g_eMMCDrv.u8_ECSD224_HCEraseGRPSize= pBuf[224]; ++ g_eMMCDrv.u8_ECSD221_HCWpGRPSize= pBuf[221]; ++ ++ g_eMMCDrv.GP_Part[0].u32_PartSize = ((pBuf[145] << 16) | ++ (pBuf[144] << 8) | ++ (pBuf[143])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[1].u32_PartSize = ((pBuf[148] << 16) | ++ (pBuf[147] << 8) | ++ (pBuf[146])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[2].u32_PartSize = ((pBuf[151] << 16) | ++ (pBuf[150] << 8) | ++ (pBuf[149])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[3].u32_PartSize = ((pBuf[154] << 16) | ++ (pBuf[153] << 8) | ++ (pBuf[152])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ //for Max Enhance Size ++ g_eMMCDrv.u8_ECSD157_MaxEnhSize_0= pBuf[157]; ++ g_eMMCDrv.u8_ECSD158_MaxEnhSize_1= pBuf[158]; ++ g_eMMCDrv.u8_ECSD159_MaxEnhSize_2= pBuf[159]; ++ ++ g_eMMCDrv.u8_u8_ECSD155_PartSetComplete = pBuf[155]; ++ g_eMMCDrv.u8_ECSD166_WrRelParam = pBuf[166]; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_INIT_DONE; ++ ++ } ++ ++ return err; ++} ++#endif ++ ++#if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ ++static void mstar_mci_pre_adma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = pData_st->sg; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 u32_dma_addr = 0; ++ int i; ++ ++ if( pData_st->sg_len > FCIE_ADMA_DESC_COUNT ) ++ { ++ eMMC_die("mstar_mci_pre_adma_read: sglist has more than FCIE_ADMA_DESC_COUNT items. Must change 512 to larger value.\n"); ++ } ++ ++ memset(gAdmaDesc_st, 0, sizeof(struct _AdmaDescriptor)*FCIE_ADMA_DESC_COUNT); ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pMStarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ for(i=0; isg_len; i++) ++ { ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_read_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 2; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 1; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 0; ++ } ++ ++ gAdmaDesc_st[i].u32_Address = (u32)dmaaddr; ++ gAdmaDesc_st[i].u32_DmaLen = dmalen; ++ if(dmalen >= 0x200) ++ { ++ gAdmaDesc_st[i].u32_JobCnt = (dmalen >> 9); ++ //eMMC_debug(0,0," %Xh JobCnt\n", (dmalen >> 9)); ++ } ++ else ++ { // should be only one sg element ++ gAdmaDesc_st[i].u32_JobCnt = 1; ++ REG_FCIE_W(FCIE_BLK_SIZE, dmalen); ++ //eMMC_debug(0,0," %Xh bytes\n", dmalen); ++ } ++ ++ pSG_st = sg_next(pSG_st); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen / 512); ++ g_eMMCDrv.u32_RBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ gAdmaDesc_st[pData_st->sg_len-1].u32_End = 1; ++ ++ Chip_Clean_Cache_Range_VA_PA((uintptr_t)gAdmaDesc_st, ++ (uintptr_t)virt_to_phys(gAdmaDesc_st), ++ sizeof(struct _AdmaDescriptor)*pData_st->sg_len); ++ ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(virt_to_phys(gAdmaDesc_st), 0); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_dma_addr >> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, 0x0010); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,0x0000); ++ ++} ++ ++static U32 mstar_mci_post_adma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS) || ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_R_CRC_ERR|BIT_DAT_RD_TOUT))) ++ { ++ if(REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ return eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ } ++ #if defined(eMMC_EMULATE_WR_FAIL) &&eMMC_EMULATE_WR_FAIL ++ if(!(prandom_u32() % 1000)) ++ { ++ return eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ } ++ #endif ++ pData_st->bytes_xfered = pData_st->blocks * pData_st->blksz; ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_RBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinRBlk[g_eMMCDrv.u32_RBlk_tmp]++; ++ if(g_eMMCDrv.u32_RBlk_tmp > g_eMMCDrv.u32_CNT_MaxRBlk) ++ g_eMMCDrv.u32_CNT_MaxRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ if(g_eMMCDrv.u32_RBlk_tmp < g_eMMCDrv.u32_CNT_MinRBlk) ++ g_eMMCDrv.u32_CNT_MinRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_RLast += g_eMMCDrv.u32_RBlk_tmp; ++ g_eMMCDrv.u32_RBlk_tmp = 0; ++ #endif ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(gu32_eMMC_read_log_enable) ++ { ++ eMMC_debug(0,0,"\n"); ++ if(pCmd_st->opcode==17) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh\n",pCmd_st->opcode, pCmd_st->arg); ++ } ++ else if(pCmd_st->opcode==18) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh, blk cnt:%xh\n",pCmd_st->opcode, pCmd_st->arg ,pData_st->blocks); ++ } ++ } ++ ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#else ++ ++static void mstar_mci_pre_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = &pData_st->sg[0]; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pMStarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU2_SELECT); ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU1_SELECT); ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, dmaaddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, dmaaddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, dmalen & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, dmalen >> 16); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen/512); ++ g_eMMCDrv.u32_RBlk_tmp = (dmalen/512); ++ #endif ++ ++} ++ ++static U32 mstar_mci_post_dma_read(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = &(pData_st->sg[0]); ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ int i; ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)& (BIT_SD_R_CRC_ERR|BIT_DAT_RD_TOUT))) ++ { ++ if(REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout, MIE EVENT 0x%X\n", REG_FCIE(FCIE_MIE_EVENT)); ++ return eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ if(gu32_eMMC_monitor_enable) ++ gu32_eMMC_read_cnt++; ++ ++ for(i=1; isg_len; i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ pSG_st = sg_next(pSG_st); ++ ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_read_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU2_SELECT); ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU1_SELECT); ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, dmaaddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, dmaaddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, dmalen & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, dmalen >> 16); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS)|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_R_CRC_ERR|BIT_DAT_RD_TOUT))) ++ { ++ if(REG_FCIE(FCIE_SD_STATUS)&BIT_SD_R_CRC_ERR) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS)); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: r timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ u32_err = eMMC_ST_ERR_TIMEOUT_MIULASTDONE; ++ goto dma_read_end; ++ } ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ ++ // ----------------------------------- ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalRBlk += (dmalen / 512); ++ g_eMMCDrv.u32_RBlk_tmp += (dmalen / 512); ++ #endif ++ ++ } ++ ++ dma_read_end: ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_RBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinRBlk[g_eMMCDrv.u32_RBlk_tmp]++; ++ if(g_eMMCDrv.u32_RBlk_tmp > g_eMMCDrv.u32_CNT_MaxRBlk) ++ g_eMMCDrv.u32_CNT_MaxRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ if(g_eMMCDrv.u32_RBlk_tmp < g_eMMCDrv.u32_CNT_MinRBlk) ++ g_eMMCDrv.u32_CNT_MinRBlk = g_eMMCDrv.u32_RBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_RLast += g_eMMCDrv.u32_RBlk_tmp; ++ g_eMMCDrv.u32_RBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(gu32_eMMC_read_log_enable) ++ { ++ eMMC_debug(0,0,"\n"); ++ if(pCmd_st->opcode==17) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh\n",pCmd_st->opcode, pCmd_st->arg); ++ } ++ else if(pCmd_st->opcode==18) ++ { ++ eMMC_debug(0,0,"cmd:%u ,arg:%xh, blk cnt:%xh\n",pCmd_st->opcode, pCmd_st->arg ,pData_st->blocks); ++ } ++ } ++ ++ if( !u32_err ) // success ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ } ++ } ++ ++ return u32_err; ++} ++ ++#endif ++ ++static U32 mstar_mci_dma_write(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ struct scatterlist *pSG_st = 0; ++ u32 dmalen = 0; ++ dma_addr_t dmaaddr = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ U32 u32_dma_addr = 0; ++ #endif ++ int i; ++ ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ if( pData_st->sg_len > FCIE_ADMA_DESC_COUNT ) ++ { ++ eMMC_die("mstar_mci_pre_adma_read: sglist has more than FCIE_ADMA_DESC_COUNT items. Must change 512 to larger value.\n"); ++ } ++ ++ memset(gAdmaDesc_st, 0, sizeof(struct _AdmaDescriptor)*FCIE_ADMA_DESC_COUNT); ++ #endif ++ ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ mstar_mci_pre_dma_transfer(pMStarHost_st, pData_st, NULL); ++ #else ++ dma_map_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ pSG_st = pData_st->sg; ++ for(i=0; isg_len; i++) ++ { ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_write_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 2; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 1; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ gAdmaDesc_st[i].u32_MiuSel = 0; ++ } ++ ++ gAdmaDesc_st[i].u32_Address = dmaaddr; ++ gAdmaDesc_st[i].u32_DmaLen = dmalen; ++ gAdmaDesc_st[i].u32_JobCnt = (dmalen >> 9); ++ ++ pSG_st = sg_next(pSG_st); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalWBlk += (dmalen / 512); ++ g_eMMCDrv.u32_WBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ gAdmaDesc_st[pData_st->sg_len-1].u32_End = 1; ++ ++ Chip_Clean_Cache_Range_VA_PA((uintptr_t)gAdmaDesc_st, ++ (uintptr_t)virt_to_phys(gAdmaDesc_st), ++ sizeof(struct _AdmaDescriptor)*pData_st->sg_len); ++ ++ //eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(virt_to_phys(gAdmaDesc_st), 0); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_dma_addr >> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, 0x0010); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,0x0000); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DTRX_EN|BIT_SD_DAT_DIR_W|BIT_ADMA_EN|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS)|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_W_FAIL)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS) ); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ ++ #if defined(eMMC_EMULATE_WR_FAIL) &&eMMC_EMULATE_WR_FAIL ++ if(!(prandom_u32() % 500)) ++ { ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ #endif ++ pData_st->bytes_xfered = pData_st->blocks * pData_st->blksz; ++ ++ #else ++ ++ pSG_st = &(pData_st->sg[0]); ++ for(i=0; isg_len; i++) ++ { ++ dmaaddr = sg_dma_address(pSG_st); ++ dmalen = sg_dma_len(pSG_st); ++ if(gu32_eMMC_monitor_enable) ++ { ++ gu32_eMMC_write_cnt += (dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ #ifdef MSTAR_MIU2_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU2_BUS_BASE) // MIU2 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU2_SELECT); ++ dmaaddr -= MSTAR_MIU2_BUS_BASE; ++ } ++ else ++ #endif ++ #ifdef MSTAR_MIU1_BUS_BASE ++ if( dmaaddr >= MSTAR_MIU1_BUS_BASE) // MIU1 ++ { ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU1_SELECT); ++ dmaaddr -= MSTAR_MIU1_BUS_BASE; ++ } ++ else // MIU0 ++ #endif ++ { ++ dmaaddr -= MSTAR_MIU0_BUS_BASE; ++ } ++ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ REG_FCIE_W(FCIE_BLK_SIZE, 512); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, dmalen>>eMMC_SECTOR_BYTECNT_BITS); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, dmaaddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, dmaaddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, dmalen & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, dmalen >> 16); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ if((eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, (BIT_DMA_END|BIT_ERR_STS), eMMC_GENERIC_WAIT_TIME) != eMMC_ST_SUCCESS)|| ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if((REG_FCIE(FCIE_SD_STATUS)&BIT_SD_W_FAIL)) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CRC STS 0x%X \n", REG_FCIE(FCIE_SD_STATUS)); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w timeout \n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ err = eMMC_ST_ERR_TIMEOUT_CARDDMAEND; ++ goto dma_write_end; ++ } ++ ++ // ----------------------------------- ++ ++ pData_st->bytes_xfered += pSG_st->length; ++ pSG_st = sg_next(pSG_st); ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ g_eMMCDrv.u64_CNT_TotalWBlk += (dmalen / 512); ++ g_eMMCDrv.u32_WBlk_tmp += (dmalen / 512); ++ #endif ++ } ++ ++ #endif ++ ++ dma_write_end: ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ if(g_eMMCDrv.u32_WBlk_tmp < 0x200) ++ g_eMMCDrv.au32_CNT_MinWBlk[g_eMMCDrv.u32_WBlk_tmp]++; ++ if(g_eMMCDrv.u32_WBlk_tmp > g_eMMCDrv.u32_CNT_MaxWBlk) ++ g_eMMCDrv.u32_CNT_MaxWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ if(g_eMMCDrv.u32_WBlk_tmp < g_eMMCDrv.u32_CNT_MinWBlk) ++ g_eMMCDrv.u32_CNT_MinWBlk = g_eMMCDrv.u32_WBlk_tmp; ++ ++ g_eMMCDrv.u32_Addr_WLast += g_eMMCDrv.u32_WBlk_tmp; ++ g_eMMCDrv.u32_WBlk_tmp = 0; ++ #endif ++ ++ // ----------------------------------- ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ if(!pData_st->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, (int)pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ } ++ #else ++ dma_unmap_sg(mmc_dev(pMStarHost_st->mmc), pData_st->sg, pData_st->sg_len, mstar_mci_get_dma_dir(pData_st)); ++ #endif ++ ++ if(gu32_eMMC_write_log_enable) ++ { ++ eMMC_debug(0,0,"\n"); ++ if(pCmd_st->opcode==24) ++ { ++ eMMC_debug(0,0,"cmd:%u, arg:%xh\n",pCmd_st->opcode,pCmd_st->arg); ++ } ++ else if(pCmd_st->opcode==25) ++ { ++ eMMC_debug(0,0,"cmd:%u, arg:%xh, blk cnt:%xh\n",pCmd_st->opcode,pCmd_st->arg,pData_st->blocks); ++ } ++ } ++ ++ if( !err ) ++ { ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd with data ++ ++ if( ++ pMStarHost_st->request->stop ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && !pMStarHost_st->request->sbc ++ #endif ++ ) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->stop); ++ } ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ } ++ } ++ ++ return err; ++} ++ ++static void mstar_mci_completed_command(struct mstar_mci_host *pMStarHost_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ static u32 u32_retry_cnt = 0; ++ static u32 u32_run_cnt = 0; ++ u16 u16_st; ++ u16 u16_i; ++ u8 *pTemp; ++ ++ u32_run_cnt++; ++ ++ // ---------------------------------- ++ // retrun response from FCIE to mmc driver ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3 - (u16_i % 4)) + (4 * (u16_i / 4))] = ++ (u8)(REG_FCIE(FCIE_CMDFIFO_BASE_ADDR+(((u16_i+1)/2)*4)) >> (8*((u16_i+1)%2))); ++ } ++ #if 0 ++ eMMC_debug(0,0,"------------------\n"); ++ eMMC_debug(0,1,"resp[0]: %08Xh\n", pCmd_st->resp[0]); ++ eMMC_debug(0,1,"CIFC: %04Xh %04Xh %04Xh \n", REG_FCIE(FCIE_CMDFIFO_BASE_ADDR), ++ REG_FCIE(FCIE_CMDFIFO_BASE_ADDR+4), REG_FCIE(FCIE_CMDFIFO_BASE_ADDR+8)); ++ //eMMC_dump_mem(pTemp, 0x10); ++ eMMC_debug(0,0,"------------------\n"); ++ #endif ++ ++ // ---------------------------------- ++ u16_st = REG_FCIE(FCIE_SD_STATUS); ++ if((u16_st & BIT_SD_FCIE_ERR_FLAGS) || (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ ++ if((u16_st & BIT_SD_RSP_CRC_ERR) && !(mmc_resp_type(pCmd_st) & MMC_RSP_CRC)) ++ { ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ if((pCmd_st->opcode == 1) &&((pCmd_st->resp[0]>>31) & BIT0)) ++ g_eMMCDrv.u8_IfSectorMode= (pCmd_st->resp[0] >>30) & BIT0; ++ } ++ else ++ { ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: ST:%Xh, CMD:%u, retry: %u, flag: %Xh, R1 err: %Xh\n", ++ u16_st, pCmd_st->opcode, u32_retry_cnt, g_eMMCDrv.u32_DrvFlag, ++ pCmd_st->resp[0]&eMMC_ERR_R1_NEED_RETRY); ++ ++ u32_ok_cnt = 0; ++ ++ if(u32_retry_cnt++ >= MCI_RETRY_CNT_CRC_ERR) ++ eMMC_FCIE_ErrHandler_Stop(); // fatal error ++ ++ if(25==pCmd_st->opcode || 12==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_hw_timer_sleep(1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ ++ if(0 != pCmd_st->data) ++ { ++ eMMC_FCIE_ErrHandler_Retry(); // slow dwon clock ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ } ++ else // for CMD12 ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: no data, just reset eMMC. \n"); ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ if(0==u32_retry_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: retry ok \n"); ++ return; ++ } ++ ++ //----------------------------------------- ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: ST:%Xh, CMD:%u, arg:%xh, retry:%u \n", ++ u16_st, pCmd_st->opcode, pCmd_st->arg , pCmd_st->retries); ++ #endif ++ ++ // should be trivial ++ if(u16_st & (BIT_SD_RSP_TIMEOUT)) ++ pCmd_st->error = -ETIMEDOUT; ++ else if(u16_st & (BIT_SD_RSP_CRC_ERR | BIT_SD_R_CRC_ERR | BIT_SD_W_CRC_ERR)) ++ pCmd_st->error = -EILSEQ; ++ else ++ pCmd_st->error = -EIO; ++ } ++ } ++ else ++ { ++ #if 0 ++ u16 u16_Tmp; ++ ++ // To prevent res bit shift ++ u16_Tmp = REG_FCIE(FCIE_CMDFIFO_BASE_ADDR); ++ ++ if( (mmc_resp_type(pCmd_st) == MMC_RSP_R2) || ++ (mmc_resp_type(pCmd_st) == MMC_RSP_R3) ) ++ { ++ if( (u16_Tmp & 0x3F) != 0x3F ) ++ { ++ pCmd_st->error = -EILSEQ; ++ eMMC_debug(0, 1, "CMD%d response buffer error\n", pCmd_st->opcode); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ else ++ { ++ if( (u16_Tmp & 0xFF) != pCmd_st->opcode ) ++ { ++ pCmd_st->error = -EILSEQ; ++ eMMC_debug(0, 1, "CMD%d response buffer error\n", pCmd_st->opcode); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ #endif ++ ++ pCmd_st->error = 0; ++ u32_retry_cnt = 0; ++ } ++ ++ ++ if((pCmd_st->opcode == 17) || (pCmd_st->opcode == 18) || ++ (pCmd_st->opcode == 24) || (pCmd_st->opcode == 25) || ++ (pCmd_st->opcode == 12)) //stop transmission ++ { ++ if(pCmd_st->resp[0] & eMMC_ERR_R1_31_0) ++ { ++ pCmd_st->error |= -EIO; ++ ++ if(pCmd_st->opcode == 12) ++ eMMC_debug(0,0, "eMMC Warn: CMD12 R1 error: %Xh \n", pCmd_st->resp[0]); ++ else ++ eMMC_debug(0,0, "eMMC Warn: CMD%u R1 error: %Xh, arg %08x, blocks %08x\n", ++ pCmd_st->opcode, pCmd_st->resp[0], pCmd_st->arg, pCmd_st->data->blocks); ++ } ++ } ++ ++ #if 0 ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt) ++ { ++ eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); ++} ++ ++#define WAIT_D0H_POLLING_TIME HW_TIMER_DELAY_100us ++u32 mstar_mci_WaitD0High(u32 u32_us) ++{ ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ ++ REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_BUSY_DET_ON); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // enable busy int ++ REG_FCIE_SETBIT(FCIE_MIE_INT_EN, BIT_BUSY_END_INT); ++ #endif ++ ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_BUSY_END_INT, u32_us) != eMMC_ST_SUCCESS) ++ { ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++ ++ #else ++ ++ u32 u32_cnt, u32_wait; ++ ++ for(u32_cnt=0; u32_cnt HW_TIMER_DELAY_1ms) ++ { ++ //msleep(1); ++ //schedule_hrtimeout is more precise and can reduce idle time of emmc ++ ++ { ++ ktime_t expires = ktime_add_ns(ktime_get(), 1000 * 1000); ++ set_current_state(TASK_UNINTERRUPTIBLE); ++ schedule_hrtimeout(&expires, HRTIMER_MODE_ABS); ++ } ++ ++ u32_cnt += HW_TIMER_DELAY_1ms; ++ } ++ } ++ ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ ++ #endif ++} ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static void mstar_mci_send_data(struct work_struct *work) ++{ ++ struct mstar_mci_host *pMStarHost_st = container_of(work, struct mstar_mci_host, async_work); ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ struct mmc_data *pData_st = pCmd_st->data; ++ static u8 u8_retry_data = 0; ++ U32 err = eMMC_ST_SUCCESS; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pMStarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ err = mstar_mci_post_adma_read(pMStarHost_st); ++ #else ++ err = mstar_mci_post_dma_read(pMStarHost_st); ++ #endif ++ } ++ ++ if( err ) ++ { ++ u32_ok_cnt = 0; ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w, cmd.%u arg.%Xh, ST: %Xh or TO\n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r, cmd.%u arg.%Xh, ST: %Xh or TO \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ } ++ else ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ eMMC_dump_mem((U8*)gAdmaDesc_st, (U32)(sizeof(struct _AdmaDescriptor)*(pData_st->sg_len+1))); ++ #endif ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: cmd.%u arg.%Xh: data retry ok \n",pCmd_st->opcode, pCmd_st->arg); ++ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if( pCmd_st->opcode == 8 ) ++ { ++ mstar_mci_config_ecsd(pData_st); ++ } ++ #endif ++ ++ u8_retry_data =0; ++ if(gu32_eMMC_monitor_enable) ++ { ++ if((pCmd_st->opcode==17)||(pCmd_st->opcode==18)) ++ gu64_jiffies_read += (jiffies_64 - gu64_jiffies_org); ++ else if((pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ gu64_jiffies_write += (jiffies_64 - gu64_jiffies_org); ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++} ++#endif ++ ++static void mstar_mci_send_command(struct mstar_mci_host *pMStarHost_st, struct mmc_command *pCmd_st) ++{ ++ u32 u32_mie_int = 0; ++ u32 u32_sd_ctl = 0; ++ u32 u32_sd_mode = 0; ++ static u8 u8_retry_cmd = 0; ++ u8 u8_retry_D0H = 0; ++ struct mmc_data *pData_st; ++ ++ #if !(defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO) ++ static u8 u8_retry_data=0; ++ #endif ++ u32 err = 0; ++ ++ LABEL_SEND_CMD: ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_ERROR_RETRY; ++ u32_sd_mode = g_eMMCDrv.u16_Reg10_Mode; ++ pMStarHost_st->cmd = pCmd_st; ++ pData_st = pCmd_st->data; ++ ++ eMMC_FCIE_ClearEvents(); ++ ++ #if 0 ++ if(12!=pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ u32_ok_cnt = 0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ ++ u8_retry_D0H++; ++ if(u8_retry_D0H < 10) ++ { ++ eMMC_pads_switch(g_eMMCDrv.u8_PadType); ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ } ++ ++ if(u8_retry_D0H) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: wait D0 H [ok]\n"); ++ u8_retry_D0H = 0; ++ } ++ #endif ++ ++ if(pData_st) ++ { ++ pData_st->bytes_xfered = 0; ++ ++ if (pData_st->flags & MMC_DATA_READ) ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ u32_sd_ctl |= (BIT_SD_DAT_EN | BIT_ADMA_EN | BIT_ERR_DET_ON); ++ mstar_mci_pre_adma_read(pMStarHost_st); ++ #else ++ u32_sd_ctl |= (BIT_SD_DAT_EN | BIT_ERR_DET_ON); ++ ++ mstar_mci_pre_dma_read(pMStarHost_st); ++ #endif ++ } ++ } ++ ++ u32_sd_ctl |= BIT_SD_CMD_EN; ++ u32_mie_int |= BIT_CMD_END; ++ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, 0x00), ++ (((pCmd_st->arg >> 24)<<8) | (0x40|pCmd_st->opcode))); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, 0x01), ++ ((pCmd_st->arg & 0xFF00) | ((pCmd_st->arg>>16)&0xFF))); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_CMDFIFO_BASE_ADDR, 0x02), ++ (pCmd_st->arg & 0xFF)); ++ ++ REG_FCIE_CLRBIT(FCIE_CMD_RSP_SIZE, BIT_RSP_SIZE_MASK); ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_NONE) ++ { ++ u32_sd_ctl &= ~BIT_SD_RSP_EN; ++ } ++ else ++ { ++ u32_sd_ctl |= BIT_SD_RSP_EN; ++ if(mmc_resp_type(pCmd_st) == MMC_RSP_R2) ++ { ++ u32_sd_ctl |= BIT_SD_RSPR2_EN; ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, 16); ++ } ++ else ++ { ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, 5); ++ } ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, u32_mie_int); ++ #endif ++ ++ #if 0 ++ //eMMC_debug(0,0,"\n"); ++ eMMC_debug(0,0,"cmd:%u, arg:%Xh, buf:%Xh, block:%u, ST:%Xh, mode:%Xh, ctrl:%Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, (u32)pData_st, pData_st ? pData_st->blocks : 0, ++ REG_FCIE(FCIE_SD_STATUS), u32_sd_mode, u32_sd_ctl); ++ //eMMC_debug(0,0,"cmd:%u arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ //while(1); ++ #endif ++ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ switch(pCmd_st->opcode) ++ { ++ case 17: ++ case 18: ++ if(18 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD18++; ++ else if(17 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD17++; ++ ++ if(g_eMMCDrv.u32_Addr_RLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_RHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_RLast = pCmd_st->arg; ++ ++ case 24: ++ case 25: ++ if(25 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD25++; ++ else if(24 == pCmd_st->opcode) ++ g_eMMCDrv.u32_CNT_CMD24++; ++ ++ if(g_eMMCDrv.u32_Addr_WLast == pCmd_st->arg) ++ g_eMMCDrv.u32_Addr_WHitCnt++; ++ else ++ g_eMMCDrv.u32_Addr_WLast = pCmd_st->arg; ++ } ++ ++ #endif ++ ++ #if defined(ENABLE_EMMC_POWER_SAVING_MODE) && ENABLE_EMMC_POWER_SAVING_MODE ++ // ----------------------------------- ++ if((pCmd_st->opcode==12)||(pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ { ++ eMMC_CheckPowerCut(); ++ } ++ #endif ++ if(gu32_eMMC_monitor_enable) ++ { ++ if((pCmd_st->opcode==17)||(pCmd_st->opcode==18)|| ++ (pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ gu64_jiffies_org = jiffies_64; ++ } ++ REG_FCIE_W(FCIE_SD_MODE, u32_sd_mode); ++ REG_FCIE_W(FCIE_SD_CTRL, u32_sd_ctl|BIT_JOB_START); ++ ++ // [FIXME]: retry and timing, and omre... ++ if(eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CMD_END, HW_TIMER_DELAY_1s) != eMMC_ST_SUCCESS || ++ (REG_FCIE(FCIE_SD_STATUS)&(BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ // ------------------------------------ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if(NULL==pData_st ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ && NULL==pMStarHost_st->request->sbc ++ #endif ++ ) // no data, no retry ++ { ++ mstar_mci_completed_command(pMStarHost_st); ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ return; ++ } ++ #endif ++ ++ // ------------------------------------ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: cmd.%u arg.%Xh St: %Xh, retry %u \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS), u8_retry_cmd); ++ ++ if(u8_retry_cmd < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_cmd++; ++ ++ if(12==pCmd_st->opcode) ++ { ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ #endif ++ ++ return; ++ } ++ ++ #if 0 ++ if(25==pCmd_st->opcode) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ #endif ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ ++ u32_ok_cnt = 0; ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ { ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ return; ++ } ++ #endif ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ if(u8_retry_cmd) ++ { ++ u8_retry_cmd =0; ++ eMMC_debug(0,0,"eMMC: cmd.%u arg.%Xh CMD retry ok\n",pCmd_st->opcode, pCmd_st->arg); ++ } ++ ++ if(pData_st) ++ { ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ ++ schedule_work(&pMStarHost_st->async_work); ++ ++ #else ++ ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ err = mstar_mci_dma_write(pMStarHost_st); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ err = mstar_mci_post_adma_read(pMStarHost_st); ++ #else ++ err = mstar_mci_post_dma_read(pMStarHost_st); ++ #endif ++ } ++ ++ if( err ) ++ { ++ if(pData_st->flags & MMC_DATA_WRITE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: w timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ else if(pData_st->flags & MMC_DATA_READ) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: r timeout, cmd.%u arg.%Xh, ST: %Xh \n", ++ pCmd_st->opcode, pCmd_st->arg, REG_FCIE(FCIE_SD_STATUS)); ++ } ++ ++ if(u8_retry_data < MCI_RETRY_CNT_CMD_TO) ++ { ++ u8_retry_data++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ u32_ok_cnt = 0; ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++ ++ } ++ else ++ { ++ #if defined(ENABLE_FCIE_ADMA) && ENABLE_FCIE_ADMA ++ eMMC_dump_mem((U8*)gAdmaDesc_st, (U32)(sizeof(struct _AdmaDescriptor)*(pData_st->sg_len+1))); ++ #endif ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ } ++ else ++ { ++ if(u8_retry_data) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: data retry ok \n"); ++ ++ #if !(defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM) ++ if( pCmd_st->opcode == 8 ) ++ { ++ mstar_mci_config_ecsd(pData_st); ++ } ++ #endif ++ ++ if(gu32_eMMC_monitor_enable) ++ { ++ if((pCmd_st->opcode==17)||(pCmd_st->opcode==18)) ++ gu64_jiffies_read += (jiffies_64 - gu64_jiffies_org); ++ else if((pCmd_st->opcode==24)||(pCmd_st->opcode==25)) ++ gu64_jiffies_write += (jiffies_64 - gu64_jiffies_org); ++ } ++ u8_retry_data =0; ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ ++ #endif ++ } ++ else ++ { ++ if( (mmc_resp_type(pCmd_st) & MMC_RSP_R1B) == MMC_RSP_R1B ) ++ { ++ err = mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ ++ while(err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: retry wait D0 H.\n"); ++ ++ u8_retry_D0H++; ++ ++ if(u8_retry_D0H < 10) ++ { ++ err = mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: wait D0 H timeout\n"); ++ ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ eMMC_Dump_eMMCStatus(); ++ ++ mstar_mci_completed_command(pMStarHost_st); ++ ++ pCmd_st->error = -ETIMEDOUT; ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ ++ return; ++ } ++ } ++ } ++ ++ mstar_mci_completed_command(pMStarHost_st); // copy back rsp for cmd without data ++ ++ if( pCmd_st->opcode == 23 ) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); // CMD18 or CMD25 ++ else ++ { ++ if(MCI_RETRY_CNT_OK_CLK_UP == u32_ok_cnt++) ++ { ++ //eMMC_debug(0,1,"eMMC: restore IF\n"); ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ } ++ } ++} ++ ++#if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++static int mstar_mci_pre_dma_transfer(struct mstar_mci_host *host, struct mmc_data *data, struct mstar_mci_host_next *next) ++{ ++ int dma_len; ++ ++ /* Check if next job is already prepared */ ++ if (next || (!next && data->host_cookie != host->next_data.cookie)) ++ { ++ dma_len = dma_map_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ else ++ { ++ dma_len = host->next_data.dma_len; ++ host->next_data.dma_len = 0; ++ } ++ ++ if (dma_len == 0) ++ return -EINVAL; ++ ++ if (next) ++ { ++ next->dma_len = dma_len; ++ data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; ++ } ++ ++ return 0; ++} ++ ++ ++static void mstar_mci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, bool is_first_req) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if( mrq->data->host_cookie ) ++ { ++ mrq->data->host_cookie = 0; ++ return; ++ } ++ ++ if (mstar_mci_pre_dma_transfer(host, mrq->data, &host->next_data)) ++ mrq->data->host_cookie = 0; ++} ++ ++static void mstar_mci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) ++{ ++ struct mstar_mci_host *host = mmc_priv(mmc); ++ struct mmc_data *data = mrq->data; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "\n"); ++ ++ if (data->host_cookie) ++ { ++ dma_unmap_sg(mmc_dev(host->mmc), ++ data->sg, ++ data->sg_len, ++ mstar_mci_get_dma_dir(data)); ++ } ++ ++ data->host_cookie = 0; ++} ++#endif ++ ++static void mstar_mci_request(struct mmc_host *pMMCHost_st, struct mmc_request *pMRQ_st) ++{ ++ struct mstar_mci_host *pMStarHost_st; ++ ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ return; ++ } ++ ++ if (!pMRQ_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMRQ_st is NULL \n"); ++ return; ++ } ++ ++ pMStarHost_st->request = pMRQ_st; ++ ++ // SD command filter ++ if( (pMStarHost_st->request->cmd->opcode == 52) || ++ (pMStarHost_st->request->cmd->opcode == 55) || ++ ((pMStarHost_st->request->cmd->opcode == 8) && pMStarHost_st->request->cmd->arg) || ++ ((pMStarHost_st->request->cmd->opcode == 5) && (pMStarHost_st->request->cmd->arg == 0)) ) ++ { ++ pMStarHost_st->request->cmd->error = -ETIMEDOUT; ++ ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++ ++ return; ++ } ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ // --------------------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_INIT_DONE)) ++ { ++ eMMC_Init_Device(); ++ } ++ ++ #if 0 //def CONFIG_MP_EMMC_TRIM ++ switch(pMStarHost_st->request->cmd->opcode) ++ { ++ case 35: ++ eMMC_CMD35_CMD36(pMStarHost_st->request->cmd->arg, 35); ++ break; ++ case 36: ++ eMMC_CMD35_CMD36(pMStarHost_st->request->cmd->arg, 36); ++ break; ++ case 38: ++ eMMC_CMD38(); ++ break; ++ default: ++ break; ++ } ++ #endif ++ ++ if(NULL == pMStarHost_st->request->cmd->data && 6 != pMStarHost_st->request->cmd->opcode) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ ++ #if 0 ++ if(6 == pMStarHost_st->request->cmd->opcode && ++ (((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB70000)|| ++ ((pMStarHost_st->request->cmd->arg & 0xff0000) == 0xB90000))) ++ { ++ pMStarHost_st->cmd = pMStarHost_st->request->cmd; ++ mstar_mci_completed_command_FromRAM(pMStarHost_st); ++ return; ++ } ++ #endif ++ ++ #endif ++ ++ // --------------------------------------------- ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ if( pMStarHost_st->request->sbc) ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->sbc); ++ else ++ #endif ++ mstar_mci_send_command(pMStarHost_st, pMStarHost_st->request->cmd); ++} ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++static void mstar_mci_completed_command_FromRAM(struct mstar_mci_host *pMStarHost_st) ++{ ++ struct mmc_command *pCmd_st = pMStarHost_st->cmd; ++ u16 au16_cifc[32] = {0}; ++ u16 u16_i; ++ u8 *pTemp; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh\n", pCmd_st->opcode, pCmd_st->arg); ++ #endif ++ ++ if(eMMC_ST_SUCCESS != eMMC_ReturnRsp((u8*)au16_cifc, (u8)pCmd_st->opcode)) ++ { ++ if( mmc_resp_type(pCmd_st) != MMC_RSP_NONE ) ++ { ++ pCmd_st->error = -ETIMEDOUT; ++ eMMC_debug(0,0,"eMMC Info: no rsp\n"); ++ } ++ } ++ else ++ { ++ pCmd_st->error = 0; ++ pTemp = (u8*)&(pCmd_st->resp[0]); ++ for(u16_i=0; u16_i < 15; u16_i++) ++ { ++ pTemp[(3-(u16_i%4)) + 4*(u16_i/4)] = ++ (u8)(au16_cifc[(u16_i+1)/2] >> 8*((u16_i+1)%2)); ++ } ++ #if 0 ++ eMMC_debug(0,1,"------------------\n"); ++ eMMC_dump_mem((u8*)&(pCmd_st->resp[0]), 0x10); ++ eMMC_debug(0,1,"------------------\n"); ++ #endif ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ mmc_request_done(pMStarHost_st->mmc, pMStarHost_st->request); ++} ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++static u8 u8_cur_timing = 0; ++ ++static u32 mstar_mci_read_blocks(struct mmc_host *host, u8 *buf, ulong blkaddr, ulong blkcnt) ++{ ++ struct mmc_request mrq = {NULL}; ++ struct mmc_command cmd = {0}; ++ struct mmc_data data = {0}; ++ struct scatterlist sg; ++ ++ mrq.cmd = &cmd; ++ mrq.data = &data; ++ ++ cmd.opcode = MMC_READ_SINGLE_BLOCK; ++ cmd.arg = blkaddr; ++ ++ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; ++ ++ data.blksz = 512; ++ data.blocks = blkcnt; ++ data.flags = MMC_DATA_READ; ++ data.sg = &sg; ++ data.sg_len = 1; ++ ++ sg_init_one(&sg, buf, 512*blkcnt); ++ ++ data.timeout_ns = TIME_WAIT_1_BLK_END * 1000; ++ data.timeout_clks = 0; ++ ++ mmc_wait_for_req(host, &mrq); ++ ++ if (cmd.error) ++ return cmd.error; ++ ++ if (data.error) ++ return data.error; ++ ++ return 0; ++} ++ ++#endif ++ ++static void mstar_mci_set_ios(struct mmc_host *pMMCHost_st, struct mmc_ios *pIOS_st) ++{ ++ /* Define Local Variables */ ++ struct mstar_mci_host *pMStarHost_st; ++ static u8 u8_IfLock=0; ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ u8 u8_pad_type = 0; ++ char *s8_timing_str = 0; ++ #endif ++ ++ if(0 == (REG_FCIE(FCIE_MIE_FUNC_CTL) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ //eMMC_debug(0,1,"lock\n"); ++ } ++ ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pMMCHost_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ if (!pIOS_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pIOS_st is NULL \n"); ++ goto LABEL_END; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "eMMC: clock: %u, bus_width %Xh \n", ++ // pIOS_st->clock, pIOS_st->bus_width); ++ ++ // ---------------------------------- ++ if (pIOS_st->clock == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "eMMC Warn: disable clk \n"); ++ eMMC_clock_gating(); ++ } ++ // ---------------------------------- ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ else ++ { ++ eMMC_clock_setting(g_eMMCDrv.u16_ClkRegVal); ++ } ++ #else ++ // ---------------------------------- ++ else ++ { ++ if( pIOS_st->bus_width == MMC_BUS_WIDTH_8 ) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode = ++ (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_8; ++ } ++ else if( pIOS_st->bus_width == MMC_BUS_WIDTH_4 ) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode = ++ (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK) | BIT_SD_DATA_WIDTH_4; ++ } ++ else if( pIOS_st->bus_width == MMC_BUS_WIDTH_1 ) ++ { ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = ++ (g_eMMCDrv.u16_Reg10_Mode & ~BIT_SD_DATA_WIDTH_MASK); ++ } ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ ++ if( u8_cur_timing != pIOS_st->timing ) ++ { ++ if( pIOS_st->timing == MMC_TIMING_LEGACY ) ++ { ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ ++ if( pIOS_st->clock > CLK_400KHz ) ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ else ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ u8_cur_timing = pIOS_st->timing; ++ } ++ else if( pIOS_st->timing == MMC_TIMING_MMC_HS ) ++ { ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ u8_cur_timing = pIOS_st->timing; ++ } ++ else if( (pIOS_st->timing == MMC_TIMING_UHS_DDR50) || ++ (pIOS_st->timing == MMC_TIMING_MMC_DDR52) ) ++ { ++ if(u8_IfLock==0) ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_FCIE_EnableSDRMode(); ++ if(g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_DDR) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_DDR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode DDR fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ { ++ eMMC_debug(0,0,"\neMMC: DDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ u8_cur_timing = pIOS_st->timing; ++ } ++ } ++ if(u8_IfLock==0) ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ } ++ else ++ { ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ if( pIOS_st->timing == MMC_TIMING_MMC_HS200 ) ++ { ++ u8_cur_timing = pIOS_st->timing; ++ goto LABEL_END; ++ } ++ #endif ++ ++ switch( pIOS_st->timing ) ++ { ++ case MMC_TIMING_MMC_HS200: ++ u8_pad_type = FCIE_eMMC_HS200; ++ s8_timing_str = "HS200"; ++ break; ++ case MMC_TIMING_MMC_HS400: ++ u8_pad_type = FCIE_eMMC_HS400; ++ s8_timing_str = "HS400"; ++ break; ++ } ++ ++ eMMC_pads_switch(u8_pad_type); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ eMMC_debug(0,0,"eMMC: %s %uMHz \n", s8_timing_str, g_eMMCDrv.u32_ClkKHz/1000); ++ ++ #if defined(ENABLE_eMMC_HS400)&&ENABLE_eMMC_HS400 ++ if(g_eMMCDrv.TimingTable_G_t.u8_SetCnt && u8_pad_type == FCIE_eMMC_HS400) ++ eMMC_FCIE_ApplyTimingSet(g_eMMCDrv.TimingTable_G_t.u8_CurSetIdx); ++ else ++ #endif ++ if(g_eMMCDrv.TimingTable_t.u8_SetCnt) ++ eMMC_FCIE_ApplyTimingSet(eMMC_TIMING_SET_MAX); ++ ++ u8_cur_timing = pIOS_st->timing; ++ } ++ } ++ ++ #else ++ if(pIOS_st->clock > CLK_400KHz) ++ { ++ switch( pIOS_st->timing ) ++ { ++ case MMC_TIMING_LEGACY: ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ break; ++ case MMC_TIMING_UHS_DDR50: ++ if(u8_IfLock==0) ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_FCIE_EnableSDRMode(); ++ if(g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_DDR) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_DDR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode DDR fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ eMMC_debug(0,0,"\neMMC: DDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ if(u8_IfLock==0) ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ break; ++ case MMC_TIMING_MMC_HS200: ++ eMMC_pads_switch(FCIE_eMMC_HS200); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ break; ++ case MMC_TIMING_MMC_HS400: ++ eMMC_pads_switch(FCIE_eMMC_HS400); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ break; ++ //case MMC_TIMING_MMC_HS: ++ default: ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ break; ++ } ++ } ++ else ++ { ++ eMMC_pads_switch(FCIE_eMMC_BYPASS); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ } ++ #endif ++ } ++ #endif ++ ++ LABEL_END: ++ ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ //eMMC_debug(0,1,"unlock\n"); ++ } ++} ++ ++static int mstar_mci_execute_tuning(struct mmc_host *host, u32 opcode) ++{ ++ u32 u32_err = 0; ++ ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ ++ #if 1 ++ ++ U32 u32_ChkSum; ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ mstar_mci_read_blocks(host, gau8_eMMC_SectorBuf, eMMC_HS400TABLE_BLK_0, 1); ++ #elif defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ mstar_mci_read_blocks(host, gau8_eMMC_SectorBuf, eMMC_HS200TABLE_BLK_0, 1); ++ #endif ++ ++ memcpy((U8 *)&g_eMMCDrv.TimingTable_t, gau8_eMMC_SectorBuf, ++ sizeof(g_eMMCDrv.TimingTable_t)); ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&g_eMMCDrv.TimingTable_t, ++ sizeof(g_eMMCDrv.TimingTable_t) - ++ eMMC_TIMING_TABLE_CHKSUM_OFFSET); ++ if(u32_ChkSum != g_eMMCDrv.TimingTable_t.u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: ChkSum error, no Table \n"); ++ printk("u32_ChkSum=%08X\n", u32_ChkSum); ++ printk("g_eMMCDrv.TimingTable_t.u32_ChkSum=%08X\n", ++ g_eMMCDrv.TimingTable_t.u32_ChkSum); ++ eMMC_dump_mem((U8 *)&g_eMMCDrv.TimingTable_t, ++ sizeof(g_eMMCDrv.TimingTable_t)); ++ u32_err = eMMC_ST_ERR_DDRT_CHKSUM; ++ return u32_err; ++ } ++ ++ if (0 == u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: no Table \n"); ++ u32_err = eMMC_ST_ERR_DDRT_NONA; ++ return u32_err; ++ } ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ ++ mstar_mci_read_blocks(host, gau8_eMMC_SectorBuf, ++ eMMC_HS400EXTTABLE_BLK_0, 1); ++ ++ memcpy((U8 *)&g_eMMCDrv.TimingTable_G_t, gau8_eMMC_SectorBuf, ++ sizeof(g_eMMCDrv.TimingTable_G_t)); ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&g_eMMCDrv.TimingTable_G_t.u32_VerNo, ++ (sizeof(g_eMMCDrv.TimingTable_G_t) - sizeof(U32))); ++ ++ if (u32_ChkSum != g_eMMCDrv.TimingTable_G_t.u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: ChkSum error, no Gen_TTable \n"); ++ g_eMMCDrv.TimingTable_G_t.u8_SetCnt = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_ChkSum = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_VerNo = 0; ++ u32_err = eMMC_ST_ERR_DDRT_CHKSUM; ++ return u32_err; ++ } ++ ++ if (0 == u32_ChkSum) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: no Gen_TTable \n"); ++ g_eMMCDrv.TimingTable_G_t.u8_SetCnt = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_ChkSum = 0; ++ g_eMMCDrv.TimingTable_G_t.u32_VerNo = 0; ++ u32_err = eMMC_ST_ERR_DDRT_CHKSUM; ++ return u32_err; ++ } ++ #endif ++ ++ #else ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ if( (g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS400_1_8V) && (host->caps2 & MMC_CAP2_HS400_1_8V) ) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ u32_err = eMMC_LoadTimingTable(FCIE_eMMC_HS400); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: no Timing Table, %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ #endif ++ ++ #if defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ if( (g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS200_1_8V) && (host->caps2 & MMC_CAP2_HS200_1_8V_SDR) ) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ u32_err = eMMC_LoadTimingTable(FCIE_eMMC_HS200); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: no Timing Table, %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ #endif ++ ++ #endif ++ ++ #else ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ #if defined(CONFIG_MSTAR_MONACO) || defined(CONFIG_MSTAR_CLIPPERS) ++ if( (REG_FCIE(reg_chip_version)>>8) >= 0x01 ) ++ { ++ #endif ++ ++ if((g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS400_1_8V) && (host->caps2 & MMC_CAP2_HS400_1_8V_DDR) ) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_HS400)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode HS400 fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ eMMC_debug(0,0,"\neMMC: HS400 %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ ++ #if defined(CONFIG_MSTAR_MONACO) || defined(CONFIG_MSTAR_CLIPPERS) ++ } ++ #endif ++ #endif //defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ ++ #if defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ if((g_eMMCDrv.u8_ECSD196_DevType & eMMC_DEVTYPE_HS200_1_8V) && (host->caps2 & MMC_CAP2_HS200_1_8V_SDR)) ++ { ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_EnableFastMode(FCIE_eMMC_HS200)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_FCIE_EnableFastMode HS200 fail\n"); ++ eMMC_debug(0,0,"\neMMC: SDR %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ } ++ else ++ eMMC_debug(0,0,"\neMMC: HS200 %uMHz \n", g_eMMCDrv.u32_ClkKHz/1000); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ return u32_err; ++ } ++ #endif ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ #endif ++ ++ return u32_err; ++} ++ ++//======================================================================= ++static void mstar_mci_enable(void) ++{ ++ u32 u32_err; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ //reset retry status to default ++ sgu8_IfNeedRestorePadType=0xFF; ++ u8_sdr_retry_count = 0; ++ ++ eMMC_PlatformInit(); ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ g_eMMCDrv.u16_RCA=1; ++ ++ u32_err = eMMC_FCIE_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, "eMMC Err: eMMC_FCIE_Init fail: %Xh \n", u32_err); ++} ++ ++static void mstar_mci_disable(void) ++{ ++ u32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, "eMMC Err: eMMC_FCIE_Reset fail: %Xh\n", u32_err); ++ ++ eMMC_clock_gating(); ++} ++ ++#if 0 ++static ssize_t fcie_pwrsvr_gpio_trigger_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_trigger); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_trigger_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_trigger = 0; ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_trigger)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_trigger > 1) ++ return -EINVAL; ++ ++ gu32_pwrsvr_gpio_trigger = u32_pwrsvr_gpio_trigger; ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_trigger, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_trigger_show, ++ fcie_pwrsvr_gpio_trigger_store); ++ ++static ssize_t fcie_pwrsvr_gpio_bit_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_bit); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_bit_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_bit = 0; ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_bit)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_bit) ++ { ++ if(u32_pwrsvr_gpio_bit > 0xF) ++ return -EINVAL; ++ gu32_pwrsvr_gpio_bit = u32_pwrsvr_gpio_bit; ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_bit, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_bit_show, ++ fcie_pwrsvr_gpio_bit_store); ++ ++static ssize_t fcie_pwrsvr_gpio_addr_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "0x%X\n", gu32_pwrsvr_gpio_addr); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_addr_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_addr = 0; ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_addr)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_addr) ++ gu32_pwrsvr_gpio_addr = u32_pwrsvr_gpio_addr; ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_addr, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_addr_show, ++ fcie_pwrsvr_gpio_addr_store); ++ ++static ssize_t fcie_pwrsvr_gpio_enable_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_pwrsvr_gpio_enable); ++} ++ ++static ssize_t fcie_pwrsvr_gpio_enable_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_pwrsvr_gpio_enable = 0; ++ ++ #if 0 ++ if(u8_enable_sar5) ++ return count; ++ #endif ++ ++ if(kstrtoul(buf, 0, &u32_pwrsvr_gpio_enable)) ++ return -EINVAL; ++ ++ if(u32_pwrsvr_gpio_enable) ++ gu32_pwrsvr_gpio_enable = u32_pwrsvr_gpio_enable; ++ ++ return count; ++} ++ ++DEVICE_ATTR(fcie_pwrsvr_gpio_enable, ++ S_IRUSR | S_IWUSR, ++ fcie_pwrsvr_gpio_enable_show, ++ fcie_pwrsvr_gpio_enable_store); ++ ++ ++static ssize_t emmc_sanitize_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf, "%d\n", gu32_emmc_sanitize); ++} ++ ++static ssize_t emmc_sanitize_store(struct device *dev, struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ unsigned long u32_temp = 0; ++ ++ if(kstrtoul(buf, 0, &u32_temp)) ++ return -EINVAL; ++ ++ gu32_emmc_sanitize = u32_temp; ++ //printk("%Xh\n", gu32_emmc_sanitize); ++ ++ if(gu32_emmc_sanitize) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: santizing ...\n"); ++ eMMC_Sanitize(0xAA); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: done\n"); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(emmc_sanitize, ++ S_IRUSR | S_IWUSR, ++ emmc_sanitize_show, ++ emmc_sanitize_store); ++#endif ++ ++static ssize_t eMMC_monitor_count_enable_show(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ U32 u32_read_bytes,u32_write_bytes; ++ U32 u32_speed_read=0,u32_speed_write=0; ++ ++ u32_read_bytes = ((gu32_eMMC_read_cnt<num_parents = of_clk_get_parent_count(pDev_st->dev.of_node); ++ if(clkdata->num_parents > 0) ++ { ++ clkdata->clk_fcie = kzalloc(sizeof(struct clk*) * clkdata->num_parents, GFP_KERNEL); ++ } ++ else ++ { ++ printk(KERN_ERR "Unable to get nand clk count from dts\n"); ++ return -ENODEV; ++ } ++ ++ for(u16_i = 0 ; u16_i < clkdata->num_parents; u16_i ++) ++ { ++ clkdata->clk_fcie[u16_i] = of_clk_get(pDev_st->dev.of_node, u16_i); ++ if(IS_ERR(clkdata->clk_fcie[u16_i])) ++ { ++ printk(KERN_CRIT"Unable to get nand clk from dts\n"); ++ return -ENODEV; ++ } ++ } ++ ++ #endif ++ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_BYPASS; ++ g_eMMCDrv.u16_ClkRegVal = FCIE_SLOWEST_CLK; ++ ++ // -------------------------------- ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ mstar_mci_enable(); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ pMMCHost_st = mmc_alloc_host(sizeof(struct mstar_mci_host), &pDev_st->dev); ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: mmc_alloc_host fail \n"); ++ s32_ret = -ENOMEM; ++ goto LABEL_END; ++ } ++ ++ pMMCHost_st->ops = &sg_mstar_mci_ops; ++ ++ // [FIXME]-> ++ pMMCHost_st->f_min = CLK_400KHz; ++ pMMCHost_st->f_max = CLK_200MHz; ++ pMMCHost_st->ocr_avail = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | \ ++ MMC_VDD_31_32 | MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; ++ ++ pMMCHost_st->max_blk_count = BIT_SD_JOB_BLK_CNT_MASK; ++ pMMCHost_st->max_blk_size = 512; ++ pMMCHost_st->max_req_size = pMMCHost_st->max_blk_count * pMMCHost_st->max_blk_size; //could be optimized ++ ++ pMMCHost_st->max_seg_size = pMMCHost_st->max_req_size; ++ pMMCHost_st->max_segs = 32; ++ ++ //--------------------------------------- ++ pMStarHost_st = mmc_priv(pMMCHost_st); ++ pMStarHost_st->mmc = pMMCHost_st; ++ ++ //--------------------------------------- ++ pMMCHost_st->caps = MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_NONREMOVABLE; ++ ++ #if defined(ENABLE_EMMC_PRE_DEFINED_BLK) && ENABLE_EMMC_PRE_DEFINED_BLK ++ pMMCHost_st->caps |= MMC_CAP_CMD23; ++ #endif ++ ++ #if (defined(ENABLE_eMMC_ATOP)&&ENABLE_eMMC_ATOP) ++ ++ #if defined(ENABLE_eMMC_HS400) && ENABLE_eMMC_HS400 ++ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0) ++ pMMCHost_st->caps2 |= MMC_CAP2_HS400_1_8V; ++ #else ++ pMMCHost_st->caps2 |= MMC_CAP2_HS400_1_8V_DDR; ++ #endif ++ #endif ++ ++ #if defined(ENABLE_eMMC_HS200) && ENABLE_eMMC_HS200 ++ pMMCHost_st->caps2 |= MMC_CAP2_HS200_1_8V_SDR; ++ #endif ++ ++ pMMCHost_st->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50; ++ ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_TRIM ++ pMMCHost_st->caps |= MMC_CAP_ERASE; ++ #endif ++ ++ #ifdef CONFIG_MP_EMMC_CACHE ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) ++ pMMCHost_st->caps2 |= MMC_CAP2_CACHE_CTRL; ++ #endif ++ #endif ++ ++// #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,3,1) && LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) ++// pMMCHost_st->caps2 |= MMC_CAP2_NO_SLEEP_CMD; ++// #endif ++ strcpy(pMStarHost_st->name,MSTAR_MCI_NAME); ++ ++ // <-[FIXME] ++ #if defined(ENABLE_EMMC_ASYNC_IO) && ENABLE_EMMC_ASYNC_IO ++ pMStarHost_st->next_data.cookie = 1; ++ INIT_WORK(&pMStarHost_st->async_work, mstar_mci_send_data); ++ #endif ++ ++ mmc_add_host(pMMCHost_st); ++ platform_set_drvdata(pDev_st, pMMCHost_st); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ fcie_irq = platform_get_irq(pDev_st, 0); ++ if (fcie_irq < 0) ++ return -ENXIO; ++ ++ s32_ret = request_irq(fcie_irq, eMMC_FCIE_IRQ, IRQF_SHARED, DRIVER_NAME, pMStarHost_st); ++ if (s32_ret) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: request_irq fail \n"); ++ mmc_free_host(pMMCHost_st); ++ goto LABEL_END; ++ } ++ #endif ++ ++ #if 1 ++ // For getting and showing device attributes from/to user space. ++ s32_ret = sysfs_create_group(&pDev_st->dev.kobj, &mstar_mci_attr_grp); ++ #endif ++ ++ sgp_eMMCThread_st = kthread_create(mstar_mci_Housekeep, NULL, "eMMC_bg_thread"); ++ if(IS_ERR(sgp_eMMCThread_st)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: create thread fail \n"); ++ return PTR_ERR(sgp_eMMCThread_st); ++ } ++ wake_up_process(sgp_eMMCThread_st); ++ ++ #if defined(CONFIG_MMC_MSTAR_MMC_EMMC_LIFETEST) ++ g_eMMCDrv.u64_CNT_TotalRBlk = 0; ++ g_eMMCDrv.u64_CNT_TotalWBlk = 0; ++ writefile = create_proc_entry (procfs_name, 0644, NULL); ++ if(writefile == NULL) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Err: Can not initialize /proc/%s\n", procfs_name); ++ else ++ { ++ writefile->read_proc = procfile_read; ++ writefile->mode = S_IFREG | S_IRUGO; ++ writefile->uid = 0; ++ writefile->gid = 0; ++ writefile->size = 0x10; ++ } ++ #endif ++ ++ LABEL_END: ++ ++ return s32_ret; ++} ++ ++static s32 __exit mstar_mci_remove(struct platform_device *pDev_st) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st = platform_get_drvdata(pDev_st); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ struct mstar_mci_host *pMStarHost_st = mmc_priv(pMMCHost_st); ++ #endif ++ s32 s32_ret = 0; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ if (!pDev_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pDev_st is NULL\n"); ++ s32_ret = -EINVAL; ++ goto LABEL_END; ++ } ++ ++ if (!pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: pMMCHost_st is NULL\n"); ++ s32_ret= -1; ++ goto LABEL_END; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove +\n"); ++ ++ mmc_remove_host(pMMCHost_st); ++ ++ mstar_mci_disable(); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ free_irq(fcie_irq, pMStarHost_st); ++ #endif ++ ++ mmc_free_host(pMMCHost_st); ++ ++ platform_set_drvdata(pDev_st, NULL); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, remove -\n"); ++ ++ LABEL_END: ++ ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if(sgp_eMMCThread_st) ++ kthread_stop(sgp_eMMCThread_st); ++ ++ return s32_ret; ++} ++ ++#ifdef CONFIG_PM ++static s32 mstar_mci_suspend(struct platform_device *pDev_st, pm_message_t state) ++{ ++ /* Define Local Variables */ ++ struct mmc_host *pMMCHost_st = platform_get_drvdata(pDev_st); ++ s32 ret = 0; ++ ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ ++ // wait for D0 high before losing eMMC Vcc ++ if(eMMC_ST_SUCCESS != mstar_mci_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_CMD0(0); mdelay(10); //msleep(10); ++ eMMC_PlatformDeinit(); ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ ++ if (pMMCHost_st) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend + \n"); ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) ++ ret = mmc_suspend_host(pMMCHost_st); ++ #endif ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC, suspend -, %Xh\n", ret); ++ ++ u16_OldPLLClkParam = 0xFFFF; ++ u16_OldPLLDLLClkParam = 0xFFFF; ++ ++ return ret; ++} ++ ++static s32 mstar_mci_resume(struct platform_device *pDev_st) ++{ ++ struct mmc_host *pMMCHost_st = platform_get_drvdata(pDev_st); ++ s32 ret = 0; ++ static u8 u8_IfLock = 0; ++ ++ if(0 == (REG_FCIE(FCIE_MIE_FUNC_CTL) & BIT_EMMC_ACTIVE)) ++ { ++ eMMC_LockFCIE((U8*)__FUNCTION__); ++ u8_IfLock = 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"lock\n"); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume +\n"); ++#if defined(CONFIG_OF) ++ //enable clock here with clock framework ++ { ++ int i; ++ for(i = 0 ;i < clkdata->num_parents; i ++) ++ clk_prepare_enable(clkdata->clk_fcie[i]); ++ } ++#endif ++ ++ mstar_mci_enable(); ++ ++ if(u8_IfLock) ++ { ++ u8_IfLock = 0; ++ eMMC_UnlockFCIE((U8*)__FUNCTION__); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"unlock\n"); ++ } ++ ++ if (pMMCHost_st) ++ { ++ #if LINUX_VERSION_CODE < KERNEL_VERSION(3,18,0) ++ ret = mmc_resume_host(pMMCHost_st); ++ #endif ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC, resume -\n"); ++ ++ return ret; ++} ++#endif /* End ifdef CONFIG_PM */ ++ ++/****************************************************************************** ++ * Define Static Global Variables ++ ******************************************************************************/ ++ #if defined(CONFIG_OF) ++static struct of_device_id ms_mstar_mci_dt_ids[] = { ++ { ++ .compatible = DRIVER_NAME ++ }, ++ {}, ++}; ++#endif ++ ++static struct platform_driver sg_mstar_mci_driver = ++{ ++ .probe = mstar_mci_probe, ++ .remove = __exit_p(mstar_mci_remove), ++ ++ #ifdef CONFIG_PM ++ .suspend = mstar_mci_suspend, ++ .resume = mstar_mci_resume, ++ #endif ++ ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++#if defined(CONFIG_OF) ++ .of_match_table = ms_mstar_mci_dt_ids, ++#endif ++ }, ++}; ++ ++extern int Chip_Boot_Get_Dev_Type(void); ++extern unsigned long long Chip_MIU_to_Phys(unsigned long long phys); ++ ++/****************************************************************************** ++ * Init & Exit Modules ++ ******************************************************************************/ ++static s32 __init mstar_mci_init(void) ++{ ++ int err = 0; ++ ++ #if 0 ++ if(MS_BOOT_DEV_EMMC!=(MS_BOOT_DEV_TYPE)Chip_Boot_Get_Dev_Type()) ++ { ++ pr_info("[eMMC] skipping device initialization\n"); ++ return -1; ++ } ++ #endif ++ ++ memset(&g_eMMCDrv, 0, sizeof(eMMC_DRIVER)); ++ MIU0_BUS_ADDR=Chip_MIU_to_Phys(0);//get the MIU0 base; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"\n"); ++ ++#if !defined(CONFIG_OF) ++ if((err = platform_device_register(&sg_mstar_emmc_device_st)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++#endif ++ ++ if((err = platform_driver_register(&sg_mstar_mci_driver)) < 0) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: platform_driver_register fail, %Xh\n", err); ++ ++ return err; ++} ++ ++static void __exit mstar_mci_exit(void) ++{ ++ platform_driver_unregister(&sg_mstar_mci_driver); ++} ++bool mstar_mci_is_mstar_host(struct mmc_card* card) ++{ ++ struct mstar_mci_host *mci_host; ++ ++ if( NULL==(card) ++ || NULL==(card->host) ++ || NULL==(mci_host=((struct mstar_mci_host *)card->host->private) ) ++ || 0!=strncmp(mci_host->name,MSTAR_MCI_NAME,strlen(MSTAR_MCI_NAME)) ++ ) ++ { ++ return false; ++ } ++ else ++ { ++ return true; ++ } ++ ++} ++ ++EXPORT_SYMBOL(mstar_mci_is_mstar_host); ++ ++#if 0 ++static int __init write_seg_size_setup(char *str) ++{ ++ wr_seg_size = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++ ++static int __init write_seg_theshold_setup(char *str) ++{ ++ wr_split_threshold = simple_strtoul(str, NULL, 16); ++ return 1; ++} ++#endif ++ ++/* SAR5=ON in set_config will enable this feature */ ++#if 0 ++static int __init sar5_setup_for_pwr_cut(char * str) ++{ ++ if(str != NULL) ++ { ++ printk(KERN_CRIT"SAR5=%s", str); ++ if(strcmp((const char *) str, "ON") == 0) ++ u8_enable_sar5 = 1; ++ } ++ ++ return 0; ++} ++early_param("SAR5", sar5_setup_for_pwr_cut); ++#endif ++ ++#if 0 ++__setup("mmc_wrsize=", write_seg_size_setup); ++__setup("mmc_wrupsize=", write_seg_theshold_setup); ++#endif ++ ++#ifndef CONFIG_MS_EMMC_MODULE ++#if !defined(CONFIG_OF) ++subsys_initcall(mstar_mci_init); ++#endif ++#endif ++module_init(mstar_mci_init); ++module_exit(mstar_mci_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Mstar Multimedia Card Interface driver"); ++MODULE_AUTHOR("MStar"); +diff --git a/drivers/mstar/emmc/unify_driver/src/api/eMMC_prg.c b/drivers/mstar/emmc/unify_driver/src/api/eMMC_prg.c +new file mode 100644 +index 00000000..80f37b0a +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/src/api/eMMC_prg.c +@@ -0,0 +1,2572 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++ ++#include "../../inc/common/eMMC.h" ++ ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++/* frequency bases */ ++/* divided by 10 to be nice to platforms without floating point */ ++int fbase[] = { ++ 10000, ++ 100000, ++ 1000000, ++ 10000000, ++}; ++ ++/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice ++ * to platforms without floating point. ++ */ ++int multipliers[] = { ++ 0, /* reserved */ ++ 10, ++ 12, ++ 13, ++ 15, ++ 20, ++ 25, ++ 30, ++ 35, ++ 40, ++ 45, ++ 50, ++ 55, ++ 60, ++ 70, ++ 80, ++}; ++ ++//======================================================== ++ ++#ifndef IP_FCIE_VERSION_5 ++ ++U32 eMMC_LoadImages(U32 *pu32_Addr, U32 *pu32_SectorCnt, U32 u32_ItemCnt) ++{ ++ U32 u32_err, u32_i; ++ U16 u16_reg, u16_retry=0; ++ ++ // -------------------------------- ++ eMMC_PlatformInit(); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ //*(U16*)0x25020DD4 &= ~BIT6; // FPGA only ++ ++ LABEL_BOOT_MODE_START: ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ // -------------------------------- ++ eMMC_RST_L(); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1ms); ++ eMMC_RST_H(); ++ ++ u32_i = 0; ++ while(u32_i < u32_ItemCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"i:%u SecCnt:%Xh \n", u32_i, pu32_SectorCnt[u32_i]); ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, pu32_SectorCnt[u32_i]); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, pu32_Addr[u32_i] & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, pu32_Addr[u32_i] >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (pu32_Addr[u32_i]>>3) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(pu32_Addr[u32_i]>>3) >> 16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ if(0 == u32_i) // stg.1 ++ { ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_MODE_EN); ++ } ++ else // stg.2 ++ { ++ // can NOT set BIT_SD_DAT_EN ++ //REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_STG2_EN); ++ } ++ ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE, HW_TIMER_DELAY_1s); ++ ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((0==u16_retry) && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ u16_retry++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ #if 0 ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ #endif ++ goto LABEL_BOOT_MODE_START; ++ } ++ #if 0 ++ else if(u16_retry && (eMMC_ST_SUCCESS!=u32_err || (u16_reg & BIT_SD_R_CRC_ERR))) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC retry fail, reg.12h: %Xh\n", u16_reg); ++ //eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ eMMC_DumpDriverStatus(); ++ eMMC_DumpPadClk(); ++ eMMC_FCIE_DumpRegisters(); ++ eMMC_FCIE_DumpDebugBus(); ++ } ++ #endif ++ u32_i++; ++ } ++ ++ // -------------------------------- ++ // boot end ++ REG_FCIE_SETBIT(FCIE_BOOT_CONFIG, BIT_BOOT_END_EN); ++ u32_err = eMMC_FCIE_PollingEvents(FCIE_MIE_EVENT, ++ BIT_CARD_BOOT_DONE, HW_TIMER_DELAY_1s); ++ if(u32_err) ++ goto LABEL_LOAD_IMAGE_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_LOAD_IMAGE_END: ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: %Xh\n", u32_err); ++ return u32_err; ++} ++ ++#endif ++ ++ ++//======================================================== ++U32 eMMC_GetID(U8 *pu8IDByteCnt, U8 *pu8ID) ++{ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ *pu8IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(pu8ID, g_eMMCDrv.au8_ID, eMMC_ID_BYTE_CNT); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++// data length is 512 bytes ++U32 eMMC_FATAutoSize(void) ++{ ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ volatile U32 u32_PartSectorCnt=0; ++ ++ // calculate FAT sector cnt ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ ++ else if(u32_PartSectorCnt) ++ u32_PartSectorCnt += ++ (pPartInfo->records[u16_i].u16_BlkCnt + pPartInfo->records[u16_i].u16_BackupBlkCnt) ++ * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ g_eMMCDrv.u32_FATSectorCnt = g_eMMCDrv.u32_SEC_COUNT - u32_PartSectorCnt; ++ ++ u32_PartSectorCnt = 0; ++ // shift the StartBlk for partitions following FAT ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ if(eMMC_PART_FAT == pPartInfo->records[u16_i].u16_PartType) ++ { ++ pPartInfo->records[u16_i].u16_BlkCnt = ++ g_eMMCDrv.u32_FATSectorCnt / pPartInfo->u16_BlkPageCnt; ++ ++ u32_PartSectorCnt = ++ pPartInfo->records[u16_i].u16_StartBlk + ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ else if(u32_PartSectorCnt) ++ { ++ pPartInfo->records[u16_i].u16_StartBlk = u32_PartSectorCnt; ++ ++ u32_PartSectorCnt += ++ pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U32 eMMC_ReadPartitionInfo_Ex(void) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ // read Partition Info from Blk0 and Blk1 (check) ++ for(u16_i=0; u16_iu32_ChkSum || pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info %u ChkSum failed: %Xh %Xh\n", ++ u16_i, pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC: found Part Info %u\n", u16_i); ++ break; ++ } ++ } ++ ++ // print msg ++ if(eMMC_CIS_PNI_BLK_CNT== u16_i) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: no valid Partition Info\n"); ++ return eMMC_ST_ERR_NO_PART_INFO; ++ } ++ else{ ++ // calculate FAT capacity ++ eMMC_FATAutoSize(); ++ //eMMC_debug(0,1,"Total Sec: %Xh, FAT Sec: %Xh \n", g_eMMCDrv.u32_SEC_COUNT, g_eMMCDrv.u32_FATSectorCnt); ++ } ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_GET_PART_INFO; ++ return u32_err; ++} ++ ++ ++// data length is 512 bytes ++U32 eMMC_ReadPartitionInfo(U8 *pu8_Data) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(0 == (g_eMMCDrv.u32_DrvFlag & DRV_FLAG_GET_PART_INFO)) ++ { ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadPartitionInfo_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ } ++ ++ memcpy(pu8_Data, gau8_eMMC_PartInfoBuf, 0x200); ++ ++ return eMMC_ST_SUCCESS; ++} ++U32 eMMC_CheckCIS(eMMC_CIS_t *ptCISData) ++{ ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ U32 u32_ChkSum; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ if (eMMC_CompareCISTag(peMMCInfo->au8_Tag)) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI Tag mismatch\n"); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&peMMCInfo->u16_SpareByteCnt, (U16)((U32)(&peMMCInfo->u16_SeqAccessTime)-(U32)(&peMMCInfo->u16_SpareByteCnt))); ++ if (u32_ChkSum != peMMCInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: NNI chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, peMMCInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)peMMCInfo, 0x200); ++ return eMMC_ST_ERR_CIS_NNI; ++ } ++ ++ u32_ChkSum = eMMC_ChkSum((U8 *)&pPartInfo->u16_SpareByteCnt, 0x200-0x04); ++ if (u32_ChkSum != pPartInfo->u32_ChkSum) { ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: pni chksum mismatch: 0x%08X, 0x%08X\n", ++ u32_ChkSum, pPartInfo->u32_ChkSum); ++ ++ eMMC_dump_mem((unsigned char *)pPartInfo, 0x200); ++ return eMMC_ST_ERR_CIS_PNI; ++ } ++ ++ eMMC_dump_nni(peMMCInfo); ++ eMMC_dump_pni(pPartInfo); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++// read CIS and set config to UNFD ++U32 eMMC_ReadCIS(eMMC_CIS_t *ptCISData) ++{ ++ U32 u32_err; ++ U16 u16_i; ++ eMMC_NNI_t *peMMCInfo = (eMMC_NNI_t*)&ptCISData->au8_eMMC_nni[0]; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)&ptCISData->au8_eMMC_pni[0]; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "\n"); ++ ++ // read NNI in Blk0 and Blk1 ++ for(u16_i=0; u16_iu32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"SpareByteCnt: %04Xh \n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PageByteCnt: %04Xh \n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkPageCnt: %04Xh \n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartitionCnt: %04Xh \n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"RecByteCnt: %04Xh \n", pPartInfo->u16_UnitByteCnt); ++ ++ u32_PniBlkByteCnt = pPartInfo->u16_PageByteCnt * pPartInfo->u16_BlkPageCnt; ++ u32_PniBlkCnt = 0; ++ ++ for(u16_i=0; u16_iu16_PartCnt; u16_i++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Partition: %02u \n", u16_i); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"StartBlk: %04Xh \n", pPartInfo->records[u16_i].u16_StartBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BlkCnt: %04Xh \n", pPartInfo->records[u16_i].u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"PartType: %04Xh \n", pPartInfo->records[u16_i].u16_PartType); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"BackupBlkCnt:%04Xh \n", pPartInfo->records[u16_i].u16_BackupBlkCnt); ++ ++ if(u16_i < pPartInfo->u16_PartCnt-1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u KB\n", ++ (u32_PniBlkByteCnt * pPartInfo->records[u16_i].u16_BlkCnt)>>10); ++ ++ u32_PniBlkCnt += pPartInfo->records[u16_i].u16_BlkCnt + ++ pPartInfo->records[u16_i].u16_BackupBlkCnt; ++ } ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Capacity: %u MB\n", ++ (g_eMMCDrv.u32_SEC_COUNT - (u32_PniBlkCnt*u32_PniBlkByteCnt>>9))>>11); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#if 0 ++U32 eMMC_WritePartitionInfo(U8 *pu8_Data, U32 u32_ByteCnt) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)pu8_Data; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u16_SecCnt = (u32_ByteCnt>>eMMC_SECTOR_512BYTE_BITS) + (u32_ByteCnt&eMMC_SECTOR_512BYTE_MASK); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC input Part Info keeps %u sectors\n", u16_SecCnt); ++ ++ // search eMMC Partiton Info from pni (pu8_Data) ++ for(u16_i=0; u16_iu16_SpareByteCnt, pPartInfo->u16_BlkCnt); ++ if(1 == pPartInfo->u16_SpareByteCnt) ++ break; ++ pPartInfo = (eMMC_PNI_t*)((U32)pPartInfo+0x200); ++ } ++ if(u16_i == u16_SecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: no valid Part Info for eMMC\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(pPartInfo->u32_ChkSum != eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Part Info ChkSum failed for eMMC, %Xh %Xh\n", ++ pPartInfo->u32_ChkSum, eMMC_ChkSum((U8*)&(pPartInfo->u16_SpareByteCnt), 0x200-4)); ++ return eMMC_ST_ERR_PARTITION_CHKSUM; ++ } ++ ++ // write Partition Info in Blk0 and Blk1 (as MBR) ++ for(u16_i=0; u16_iu16_PartCnt; *pu16_PartIdx+=1) ++ { ++ if(u16_PartType == pPartInfo->records[*pu16_PartIdx].u16_PartType) ++ { ++ if(u16_PartCopy == u32_LogicIdx) ++ break; ++ u16_PartCopy++; ++ } ++ } ++ if(*pu16_PartIdx == pPartInfo->u16_PartCnt) ++ { ++ if(0 == u16_PartCopy) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: unknown Partition ID: %Xh\n", u16_PartType); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: no %u Partition ID: %Xh \n", ++ u32_LogicIdx+1, u16_PartType); ++ ++ return eMMC_ST_ERR_NO_PARTITION; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_GetPartitionCapacity (U16 u16_PartType, U32 *pu32_Cap) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ if(eMMC_PART_FAT == u16_PartType) ++ *pu32_Cap = g_eMMCDrv.u32_FATSectorCnt; ++ else ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ *pu32_Cap = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ReadPartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ReadData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_R); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_R fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ return u32_err; ++} ++ ++ ++U32 eMMC_WritePartition(U16 u16_PartType, ++ U8 *pu8_DataBuf, ++ U32 u32_StartSector, ++ U32 u32_SectorCnt, ++ U32 u32_LogicIdx) ++{ ++ U32 u32_err, u32_PartSecCnt; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_LogicIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // check address ++ u32_PartSecCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt * pPartInfo->u16_BlkPageCnt; ++ ++ if(u32_StartSector > u32_PartSecCnt || u32_SectorCnt > u32_PartSecCnt || ++ (u32_StartSector+u32_SectorCnt) > u32_PartSecCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid Sector Addr: %Xh, Sector Cnt: %Xh\n", ++ u32_StartSector, u32_SectorCnt); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u32_SectorCnt<records[u16_PartIdx].u16_StartBlk* ++ pPartInfo->u16_BlkPageCnt+ ++ u32_StartSector); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_WriteData fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_BootPartitionHandler_WR(pu8_DataBuf, u16_PartType, ++ u32_StartSector, u32_SectorCnt, eMMC_BOOT_PART_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler_W fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_GetDevInfo(eMMC_INFO_t *peMMCInfo_t) ++{ ++ const char *str = "MSTARSEMIUNFDCIS"; ++ ++ memcpy(peMMCInfo_t->au8_Tag, str, 16); ++ peMMCInfo_t->u8_IDByteCnt = g_eMMCDrv.u8_IDByteCnt; ++ memcpy(peMMCInfo_t->au8_ID, g_eMMCDrv.au8_ID, g_eMMCDrv.u8_IDByteCnt); ++ peMMCInfo_t->u16_SpareByteCnt = 1; ++ peMMCInfo_t->u16_PageByteCnt = eMMC_SECTOR_512BYTE; ++ peMMCInfo_t->u16_BlkPageCnt = g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u16_BlkCnt = g_eMMCDrv.u32_SEC_COUNT / g_eMMCDrv.u32_EraseUnitSize; ++ peMMCInfo_t->u32_ChkSum = eMMC_ChkSum((U8*)&peMMCInfo_t->u16_SpareByteCnt, 0x32 - 0x24); ++ ++ memcpy(peMMCInfo_t->au8_Vendor, g_eMMCDrv.au8_Vendor, 16); ++ memcpy(peMMCInfo_t->au8_PartNumber, g_eMMCDrv.au8_PartNumber, 16); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_ErasePartition(U16 u16_PartType) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(u16_PartType, ++ u32_PartLogiIdx, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ u32_PartLogiIdx++; ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ break; ++ } ++ } ++ ++ if(0 == u32_PartLogiIdx) ++ return u32_err; ++ ++ u32_err = eMMC_BootPartitionHandler_E(u16_PartType); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_BootPartitionHandler fail: %Xh\n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++// erase partitions following eMMC_PART_NVRAMBAK ++U32 eMMC_EraseAllPartitions(void) ++{ ++ U32 u32_err, u32_PartLogiIdx; ++ volatile U16 u16_PartIdx=0, u16_PartIdx_tmp; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ U32 u32_eMMCStartBlk, u32_eMMCEndBlk; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh", u32_err); ++ return u32_err; ++ } ++ ++ u32_PartLogiIdx = 0; ++ while(1) // find all partition copies ++ { ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_NVRAMBAK, ++ u32_PartLogiIdx, &u16_PartIdx_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u16_PartIdx = u16_PartIdx_tmp; ++ u32_PartLogiIdx++; ++ } ++ ++ for(; u16_PartIdx < pPartInfo->u16_PartCnt; u16_PartIdx++) ++ { ++ // skip some partitions can not be erased ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++ if(eMMC_PART_DEV_NODE == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_E2PBAK == pPartInfo->records[u16_PartIdx].u16_PartType || ++ eMMC_PART_NVRAMBAK == pPartInfo->records[u16_PartIdx].u16_PartType) ++ continue; ++ #endif ++ ++ u32_eMMCStartBlk = pPartInfo->records[u16_PartIdx].u16_StartBlk ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_eMMCEndBlk = (pPartInfo->records[u16_PartIdx].u16_StartBlk ++ + pPartInfo->records[u16_PartIdx].u16_BlkCnt) ++ * (pPartInfo->u16_PageByteCnt>>eMMC_SECTOR_512BYTE_BITS) ++ * pPartInfo->u16_BlkPageCnt; ++ ++ u32_err = eMMC_EraseBlock(u32_eMMCStartBlk, u32_eMMCEndBlk-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: eMMC_EraseBlock fail: %Xh, PardIdx:%Xh", ++ u32_err, u16_PartIdx); ++ return u32_err; ++ } ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_EraseAll(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_EraseBlock(0, g_eMMCDrv.u32_SEC_COUNT-1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: fail: %Xh \n", u32_err); ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseBootPart(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end, U8 u8_PartNo) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseBlock(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_EraseBlock fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseBlock( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 fail 0, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ // clear Access Boot Partition ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_WriteBootPart(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr, U8 u8_PartNo) ++{ ++ U32 u32_err; ++ U16 u16_SecCnt, u16_i ,u16_j; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ // set Access Boot Partition 1 ++ if(u8_PartNo == 1) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT0); ++ } ++ else if(u8_PartNo == 2) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 179, BIT6|BIT3|BIT1); // still boot from BP1 ++ } ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[179]: %Xh fail\n", ++ u32_err, BIT6|BIT3|BIT0); ++ return u32_err; ++ } ++ ++ // write Boot Code ++ u16_SecCnt = (u32_DataByteCnt>>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Boot Data keeps %Xh sectors, ChkSum: %Xh \n", ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, u16_SecCnt<<9)); ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, BOOT_PART_TOTAL_CNT<<9)); ++ ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Boot Data keeps %Xh sectors, ChkSum: %Xh \n", ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, u16_SecCnt<<9)); ++ // u16_SecCnt, eMMC_ChkSum(pu8_DataBuf, BOOT_PART_TOTAL_CNT<<9)); ++ ++ u32_err = eMMC_WriteData(pu8_DataBuf, ++ u16_SecCnt<>9) + ((u32_DataByteCnt&0x1FF)?1:0); ++ ++ u32_err = eMMC_ReadData(pu8_DataBuf, ++ u16_SecCnt<> 9 ; ++ else ++ g_eMMCDrv.u32_EnUserStartAddr = u32_StartAddr; ++ g_eMMCDrv.u8_EnUserEnAttr= u8_EnAttr; ++ g_eMMCDrv.u8_EnUserRelW= u8_RelW; ++ return eMMC_ST_SUCCESS; ++ } ++ return eMMC_ST_ERR_INVALID_PARAM; ++} ++ ++U32 eMMC_SetPartitionComplete(void) ++{ ++ U64 u64_MaxEnhSize, u64_tmp; ++ U32 u32_err, u32_HC_WP_Size, u32_tmp; ++ U8 u8_i, u8_j, u8_tmp, u16_tmp; ++ ++ if((g_eMMCDrv.u8_ECSD160_PartSupField & BIT0) == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC doesn't support GP and enhance partitions.\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if((g_eMMCDrv.u8_u8_ECSD155_PartSetComplete & BIT0) == BIT0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Partition setting is already configured.\n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ u32_HC_WP_Size = g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000; ++ ++ //set to HC Erase Define ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 175, BIT0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[175]: %Xh fail\n", ++ u32_err, BIT0); ++ return u32_err; ++ } ++ ++ //set Enhance Attribute for each partition ++ if(g_eMMCDrv.u8_ECSD160_PartSupField & BIT1) ++ { ++ u64_MaxEnhSize = (U64)((((U32)(g_eMMCDrv.u8_ECSD159_MaxEnhSize_2) << 16)| ++ ((U32)(g_eMMCDrv.u8_ECSD158_MaxEnhSize_1) << 8) | ++ (U32)(g_eMMCDrv.u8_ECSD157_MaxEnhSize_0)) * u32_HC_WP_Size); ++ ++ ++ u8_tmp = 0; ++ u64_tmp = 0; ++ if(g_eMMCDrv.u8_EnUserEnAttr == 1) ++ { ++ u64_tmp = (U64)g_eMMCDrv.u32_EnUserSize; ++ u8_tmp |= BIT0; ++ } ++ ++ for(u8_i = 0; u8_i < 4; u8_i ++) ++ { ++ if(g_eMMCDrv.GP_Part[u8_i].u8_EnAttr == 1) ++ { ++ u64_tmp += (U64)g_eMMCDrv.GP_Part[u8_i].u32_PartSize; ++ u8_tmp |= (1 << (u8_i + 1)); ++ } ++ } ++ ++ if(u64_MaxEnhSize < u64_tmp) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Sum of all enhance partition size shell be less than 0x%llX, but get 0x%llX\n", u64_MaxEnhSize, u64_tmp); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [156], Partition Attribute, to 0x%X\n", u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 156, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[156]: %Xh fail\n", ++ u32_err, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ ++ //set enhance user partition, if defined ++ if(g_eMMCDrv.u32_EnUserSize) ++ { ++ //size enhance user partition size ++ u32_tmp = g_eMMCDrv.u32_EnUserSize / u32_HC_WP_Size; ++ ++ for(u8_i = 3; u8_i > 0; u8_i --) ++ { ++ u8_tmp = (u32_tmp >> (8 * (u8_i - 1))) & 0xFF; ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Enhance User Size, to 0x%X\n", 140 + (u8_i - 1), u8_tmp); ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 140 + (u8_i - 1), u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 140 + (u8_i - 1), u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ //set enhance user partition start address ++ u32_tmp = g_eMMCDrv.u32_EnUserStartAddr; ++ ++ for(u8_i = 4; u8_i > 0 ;u8_i --) ++ { ++ u8_tmp = (u32_tmp >> (8 * (u8_i - 1))) & 0xFF; ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Enhance Start Address, to 0x%X\n", 136 + u8_i - 1, u8_tmp); ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 136 + u8_i - 1, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 136 + u8_i - 1, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ } ++ } ++ ++ //set GP partition size ++ for(u8_i = 0; u8_i < 4; u8_i ++) ++ { ++ u32_tmp = g_eMMCDrv.GP_Part[u8_i].u32_PartSize / u32_HC_WP_Size; ++ u16_tmp = 143 + u8_i * 3; ++ for(u8_j = 3; u8_j > 0; u8_j --) ++ { ++ u8_tmp = (u32_tmp >> (8 * (u8_j - 1))) & 0xFF; ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], GP Part %d, to 0x%X\n", u16_tmp + (u8_j - 1), u8_i, u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, u16_tmp + (u8_j - 1), u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, u16_tmp + (u8_j - 1), u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ } ++ //set GP partition extend attribute ++ ++ if(g_eMMCDrv.u8_ECSD160_PartSupField & BIT2) ++ { ++ u8_tmp = 0; ++ if(g_eMMCDrv.GP_Part[0].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[0].u8_ExtAttr < 3) ++ { ++ u8_tmp |= (g_eMMCDrv.GP_Part[0].u8_ExtAttr & 0xF); ++ } ++ if(g_eMMCDrv.GP_Part[1].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[1].u8_ExtAttr < 3) ++ { ++ u8_tmp |= ((g_eMMCDrv.GP_Part[1].u8_ExtAttr << 4) & 0xF0); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Extend Attr, to 0x%X\n", 52, u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 52, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 52, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ ++ u8_tmp = 0; ++ if(g_eMMCDrv.GP_Part[2].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[2].u8_ExtAttr < 3) ++ { ++ u8_tmp |= (g_eMMCDrv.GP_Part[2].u8_ExtAttr & 0xF); ++ } ++ if(g_eMMCDrv.GP_Part[3].u8_ExtAttr > 0 && g_eMMCDrv.GP_Part[3].u8_ExtAttr < 3) ++ { ++ u8_tmp |= ((g_eMMCDrv.GP_Part[3].u8_ExtAttr << 4) & 0xF0); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Extend Attr, to 0x%X\n", 53, u8_tmp); ++ ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 53, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 53, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ else ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Warning: eMMC doesn't support GP ext Attribute\n") ++ ; ++ } ++ //set reliable write ++ ++ if((g_eMMCDrv.u8_ECSD166_WrRelParam & (BIT0|BIT2)) == BIT0) //if BIT2 is set -> device support reliable write by default ++ { ++ u8_tmp = 0; ++ if(g_eMMCDrv.u8_EnUserRelW== 1) ++ { ++ u8_tmp |= BIT0; ++ } ++ ++ for(u8_i = 0; u8_i < 4; u8_i ++) ++ { ++ if(g_eMMCDrv.GP_Part[u8_i].u8_RelW == 1) ++ { ++ u8_tmp |= (1 << (u8_i + 1)); ++ } ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Reliable Write Setting, to 0x%X\n", 167, u8_tmp); ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 167, u8_tmp); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 167, u8_tmp); ++ return u32_err; ++ } ++ #endif ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING, 1, "Set Ext_CSD [%d], Complete Setting, to 0x%X\n", 155, BIT0); ++ ++ //finally set partition setting completed bit ++ #if 1 ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 155, BIT0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[%d]: %Xh fail\n", ++ u32_err, 155, BIT0); ++ return u32_err; ++ } ++ #endif ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ============================================================== ++void eMMC_DumpSpeedStatus(void) ++{ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," DDR Mode\n"); ++ eMMC_DumpTimingTable(); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," \n"); ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," SDR Mode\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," FCIE Clk: %u.%u MHz, %Xh\n", ++ g_eMMCDrv.u32_ClkKHz/1000, (g_eMMCDrv.u32_ClkKHz/100)%10, g_eMMCDrv.u16_ClkRegVal); ++ ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case BIT_SD_DATA_WIDTH_1: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," 1-bit "); ++ break; ++ case BIT_SD_DATA_WIDTH_4: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," 4-bits "); ++ break; ++ case BIT_SD_DATA_WIDTH_8: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," 8-bits "); ++ break; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"width\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," Bus Speed:"); ++ switch(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_SPEED_MASK) ++ { ++ case DRV_FLAG_SPEED_HIGH: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," HIGH\n"); ++ break; ++ case DRV_FLAG_SPEED_HS200: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," HS200\n"); ++ eMMC_DumpTimingTable(); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," \n"); ++ break; ++ case DRV_FLAG_SPEED_HS400: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," HS400\n"); ++ eMMC_DumpTimingTable(); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," \n"); ++ break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," LOW\n"); ++ } ++} ++ ++ ++void eMMC_DumpDriverStatus(void) ++{ ++ eMMC_debug(0,1,"\n eMMCDrvExtFlag: %Xh \n\n", gu32_eMMCDrvExtFlag); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC Status: 2014/03/25 \n"); ++ ++ // ------------------------------------------------------ ++ // helpful debug info ++ // ------------------------------------------------------ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," RIU Mode\n"); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," MIU Mode\n"); ++ #endif ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," Interrupt Mode\n"); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," Polling Mode\n"); ++ #endif ++ ++ #if defined(FICE_BYTE_MODE_ENABLE)&&FICE_BYTE_MODE_ENABLE ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," FCIE Byte Mode\n"); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," FCIE Block Mode\n"); ++ #endif ++ ++ eMMC_DumpSpeedStatus(); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," PwrOff Notification: "); ++ switch(g_eMMCDrv.u32_DrvFlag&DRV_FLAG_PwrOffNotif_MASK) ++ { ++ case DRV_FLAG_PwrOffNotif_OFF: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"OFF\n"); break; ++ case DRV_FLAG_PwrOffNotif_ON: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"ON\n"); break; ++ case DRV_FLAG_PwrOffNotif_SHORT: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"SHORT\n"); break; ++ case DRV_FLAG_PwrOffNotif_LONG: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"LONG\n"); break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL,0," eMMC Err: unknown: %Xh\n", ++ g_eMMCDrv.u32_DrvFlag&DRV_FLAG_PwrOffNotif_MASK); ++ } ++ ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ eMMC_DumpBurstLenTable(); ++ #endif ++ ++} ++ ++ ++U32 eMMC_Init(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_Init_Ex fail: %Xh\n", u32_err); ++ ++ return u32_err; ++} ++ ++#ifdef CONFIG_GENERIC_MMC ++ ++extern int fbase[]; ++extern int multipliers[]; ++ ++ ++U32 eMMC_GetExtCSD(U8* pu8_Ext_CSD) ++{ ++ return eMMC_CMD8(pu8_Ext_CSD); ++} ++ ++U32 eMMC_SetExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ return eMMC_ModifyExtCSD(u8_AccessMode, u8_ByteIdx,u8_Value); ++} ++static ulong eMMC_bread(int dev_num, ulong start, lbaint_t blkcnt, void *dst) ++{ ++ U32 u32_Err; ++ if( blkcnt == 0) ++ return 0; ++ u32_Err = eMMC_ReadData(dst, blkcnt << 9, start); ++ if (u32_Err == eMMC_ST_SUCCESS) ++ return blkcnt; ++ else ++ return 0; ++} ++ ++static ulong eMMC_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void *src) ++{ ++ U32 u32_Err, u32_blkcnt, u32_start = start; ++ U8* pu8_src = (U8*) src; ++ ++ u32_blkcnt = blkcnt; ++ ++ u32_Err = eMMC_WriteData(pu8_src, u32_blkcnt << 9, u32_start); ++ ++ if (u32_Err == eMMC_ST_SUCCESS) ++ return blkcnt; ++ else ++ return 0; ++} ++ ++static ulong eMMC_berase(int dev_num, ulong start, lbaint_t blkcnt) ++{ ++ ++ U32 u32_Err; ++ u32_Err = eMMC_EraseBlock (start, start + blkcnt - 1); ++ if (u32_Err == eMMC_ST_SUCCESS) ++ return blkcnt; ++ else ++ return 0; ++} ++ ++int eMMC_mmc_Init(struct mmc* mmc) ++{ ++ ++ eMMC_Init(); ++ ++ sprintf(mmc->name, "Mstar-eMMC"); ++ mmc->has_init = 1; ++ mmc->capacity = (u64)g_eMMCDrv.u32_SEC_COUNT << 9; ++ ++ ++ eMMC_GetExtCSD((U8*)mmc->ext_csd); ++ ++ mmc->high_capacity = g_eMMCDrv.u8_IfSectorMode; ++ mmc->bus_width = g_eMMCDrv.u8_BUS_WIDTH; ++ ++ switch (g_eMMCDrv.u8_SPEC_VERS) { ++ case 0: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ case 1: ++ mmc->version = MMC_VERSION_1_4; ++ break; ++ case 2: ++ mmc->version = MMC_VERSION_2_2; ++ break; ++ case 3: ++ mmc->version = MMC_VERSION_3; ++ break; ++ case 4: ++ mmc->version = MMC_VERSION_4; ++ break; ++ default: ++ mmc->version = MMC_VERSION_1_2; ++ break; ++ } ++ ++ /* divide frequency by 10, since the mults are 10x bigger */ ++ ++ mmc->tran_speed = fbase[( g_eMMCDrv.u8_Tran_Speed & 0x7)] * multipliers[((g_eMMCDrv.u8_Tran_Speed >> 3) & 0xf)]; ++ ++ // reliable write is supported ++ if ((mmc->ext_csd[EXT_CSD_WR_REL_SET] & 0x01) == 1) // reliable write is configured ++ mmc->reliable_write = 2; ++ else if((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[EXT_CSD_WR_REL_PARAM] & BIT0) == BIT0)) ++ { ++ mmc->reliable_write = 1; // reliable write is supported but not configured ++ //eMMC_debug(0,0,"[%s]\treliable write is supported\n", __func__); ++ } ++ else if((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[EXT_CSD_WR_REL_PARAM] & BIT2) == BIT2)) ++ { ++ mmc->reliable_write = 3; // reliable write is supported but not configurable ++ //eMMC_debug(0,0,"[%s]\treliable write is supported\n", __func__); ++ } ++ else ++ { ++ mmc->reliable_write = 0; // reliable write is unsupported ++ //eMMC_debug(0,0,"[%s]\treliable write is unsupported\n", __func__); ++ } ++ ++ if ((mmc->ext_csd[192] >= 5) && ((mmc->ext_csd[160] & 0x3) == 3)) ++ { ++ mmc->slc_size = ((u64)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_0] ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_1]) << 8) ++ | ((u32)(mmc->ext_csd[EXT_CSD_ENH_SIZE_MULT_2]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ mmc->max_slc_size = ((u64)(mmc->ext_csd[157] ++ | ((u32)(mmc->ext_csd[158]) << 8) ++ | ((u32)(mmc->ext_csd[159]) << 16)) << 19) ++ * mmc->ext_csd[221] * mmc->ext_csd[224]; ++ //eMMC_debug(0,0,"[%s]\t slc_size = %lld, max_slc_size = %lld\n",__func__, mmc->slc_size, mmc->max_slc_size); ++ } ++ else // slc mode is unsupported ++ { ++ mmc->slc_size = mmc->max_slc_size = 0; ++ //eMMC_debug(0,0,"[%s]\t slc mode is unsupported\n",__func__); ++ } ++ ++ ++ { ++ U16 u16_i; ++ for(u16_i = 0; u16_i < 4; u16_i ++) ++ { ++ if(u16_i < 3) ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8 | g_eMMCDrv.au8_CID[u16_i * 4 + 4]; ++ else ++ mmc->cid[u16_i] = ++ g_eMMCDrv.au8_CID[u16_i * 4 + 1] << 24 | g_eMMCDrv.au8_CID[u16_i * 4 + 2] << 16| ++ g_eMMCDrv.au8_CID[u16_i * 4 + 3] << 8; ++ } ++ } ++ ++ mmc->read_bl_len = 512; ++ mmc->write_bl_len = 512; ++ mmc->block_dev.lun = 0; ++ mmc->block_dev.type = 0; ++ mmc->block_dev.blksz = 512; ++ mmc->block_dev.lba = g_eMMCDrv.u32_SEC_COUNT; ++ mmc->block_dev.part_type = PART_TYPE_EMMC; ++ sprintf(mmc->block_dev.vendor, "Man %06x Snr %08x", mmc->cid[0] >> 8, ++ (mmc->cid[2] << 8) | (mmc->cid[3] >> 24)); ++ sprintf(mmc->block_dev.product, "%c%c%c%c%c", mmc->cid[0] & 0xff, ++ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, ++ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff); ++ sprintf(mmc->block_dev.revision, "%d.%d", mmc->cid[2] >> 28, ++ (mmc->cid[2] >> 24) & 0xf); ++ ++// init_part(&mmc->block_dev); ++ return 0; ++} ++ ++int board_mmc_init(bd_t *bis) ++{ ++ struct mmc* mmc = NULL; ++ ++ mmc = malloc(sizeof(struct mmc)); // uboot origianl design, don't free it. ++ if (!mmc) ++ return -ENOMEM; ++ memset(mmc, 0, sizeof(struct mmc)); ++ ++ eMMC_mmc_Init(mmc); ++ ++ mmc_register(mmc); ++ ++ mmc->block_dev.block_read = eMMC_bread; ++ mmc->block_dev.block_write = eMMC_bwrite; ++ mmc->block_dev.block_erase = eMMC_berase; ++ ++ return 0; // uboot origianl design, don't free mmc. ++} ++ ++#endif ++ ++#define eMMC_NOT_READY_MARK ~(('e'<<24)|('M'<<16)|('M'<<8)|'C') ++static U32 sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++ ++static U32 eMMC_Init_Ex(void) ++{ ++ U32 u32_err; ++ ++ // --------------------------------- ++ u32_err = eMMC_CheckAlignPack(eMMC_CACHE_LINE); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ memset((void*)&g_eMMCDrv, '\0', sizeof(eMMC_DRIVER)); ++ ++ g_eMMCDrv.u16_Reg10_Mode = BIT_SD_DEFAULT_MODE_REG; ++ ++ // --------------------------------- ++ // init platform & FCIE ++ eMMC_PlatformInit(); ++ u32_err = eMMC_FCIE_Init(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ // --------------------------------- ++ u32_err = eMMC_Init_Device(); ++ if(u32_err) ++ goto LABEL_INIT_END; ++ ++ sgu32_IfReadyGuard = ~eMMC_NOT_READY_MARK; ++ ++ LABEL_INIT_END: ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ ++ // --------------------------------- ++ // setup ID ++ // use first 10 bytes of CID ++ memcpy(g_eMMCDrv.au8_ID, &g_eMMCDrv.au8_CID[1], eMMC_ID_FROM_CID_BYTE_CNT); ++ g_eMMCDrv.u8_IDByteCnt = eMMC_ID_DEFAULT_BYTE_CNT; ++ // add a 11-th byte for number of GB ++ g_eMMCDrv.au8_ID[eMMC_ID_FROM_CID_BYTE_CNT] = ++ (g_eMMCDrv.u32_SEC_COUNT >> (1+10+10)) + 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "%u.%u GB [%Xh]\n", ++ g_eMMCDrv.u32_SEC_COUNT>>11>>10, ++ (g_eMMCDrv.u32_SEC_COUNT>>11)*100/1024%100, ++ g_eMMCDrv.u32_SEC_COUNT); ++ //eMMC_dump_mem(g_eMMCDrv.au8_ID, 0x10); ++ #if 0 ++ u32_err = eMMC_ReadPartitionInfo_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Err: eMMC Init, no pni, :%Xh\n", u32_err); ++ return eMMC_ST_ERR_NO_CIS; ++ } ++ //eMMC_DumpDriverStatus(); ++ #endif ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Init_Device_Ex(void) ++{ ++ U32 u32_err; ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSPFROMRAM_SAVE; ++ #endif ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_INIT_DONE; ++ ++ // init eMMC device ++ u32_err = eMMC_Identify(); ++ if(u32_err) ++ return u32_err; ++ ++ //eMMC_debug(0, 1, "eMMC 12MHz\n"); ++ eMMC_clock_setting(FCIE_SLOW_CLK); ++ ++ // determine device parameters, from CSD ++ u32_err = eMMC_CSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // setup eMMC device ++ // CMD7 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ #if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ u32_err = eMMC_CMD16(eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ ++ // determine device parameters, from Ext_CSD ++ u32_err = eMMC_ExtCSD_Config(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_debug(0,0,"set bus witdth 8 bits\n"); ++ u32_err = eMMC_SetBusWidth(8, 0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_debug(0,0,"set to high speed\n"); ++ u32_err = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #ifdef IP_FCIE_VERSION_5 ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ #endif ++ ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_INIT_DONE; ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Init_Device(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_Init_Device_Ex(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ ++ // ---------------------------------------- ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_INIT_END; ++ //while(1); ++ ++ // ---------------------------------------- ++ #if defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG ++ u32_err = eMMC_LoadBurstLenTable(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_SaveBurstLenTable(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: save Burst Len: %Xh\n", u32_err); ++ goto LABEL_INIT_END; ++ } ++ else ++ eMMC_DumpBurstLenTable(); ++ } ++ #endif ++ ++ //eMMC_dump_mem(g_eMMCDrv.au8_AllRsp, 0x100); ++ LABEL_INIT_END: ++ ++ return u32_err; ++ ++} ++ ++ ++U32 eMMC_CheckIfReady(void) ++{ ++ if(eMMC_NOT_READY_MARK != sgu32_IfReadyGuard) ++ return eMMC_ST_SUCCESS; ++ else ++ return eMMC_Init_Ex(); ++} ++ ++void eMMC_ResetReadyFlag(void) ++{ ++ sgu32_IfReadyGuard = eMMC_NOT_READY_MARK; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++ ++U32 eMMC_EraseBlock(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err, u32_SectorCnt, u32_i, u32_j; ++ ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ { ++ u32_err = eMMC_EraseCMDSeq(u32_eMMCBlkAddr_start, u32_eMMCBlkAddr_end); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 0: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ else ++ { ++ for(u32_i=0; u32_i (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) ? ++ (u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) : u32_SectorCnt; ++ ++ for(u32_i=0; u32_ieMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_SectorCnt-u32_i)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ if((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start) == u32_SectorCnt) ++ goto LABEL_END_OF_ERASE; ++ ++ // erase blocks ++ u32_i = ++ (u32_eMMCBlkAddr_end - (u32_eMMCBlkAddr_start+u32_SectorCnt)) ++ /g_eMMCDrv.u32_EraseUnitSize; ++ if(u32_i) ++ { ++ u32_err = eMMC_EraseCMDSeq( ++ (u32_eMMCBlkAddr_start+u32_SectorCnt), ++ (u32_eMMCBlkAddr_start+u32_SectorCnt)+u32_i*g_eMMCDrv.u32_EraseUnitSize); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EraseCMDSeq fail 1, %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ ++ // erase blocks after EraseUnitSize ++ u32_eMMCBlkAddr_start = ++ (u32_eMMCBlkAddr_start+u32_SectorCnt) + u32_i*g_eMMCDrv.u32_EraseUnitSize; ++ ++ while(u32_eMMCBlkAddr_start < u32_eMMCBlkAddr_end) ++ { ++ u32_j = ((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<eMMC_SECTOR_BUF_BYTECTN? ++ eMMC_SECTOR_BUF_BYTECTN:((u32_eMMCBlkAddr_end-u32_eMMCBlkAddr_start)<>eMMC_SECTOR_512BYTE_BITS; ++ } ++ } ++ ++ LABEL_END_OF_ERASE: ++ return u32_err; ++} ++ ++// ok: return 0 ++U32 eMMC_WriteData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ eMMC_LockFCIE(NULL); ++ #if defined(MSOS_TYPE_ECOS) ++ u32_BlkAddr += eMMC_TOTAL_RESERVED_BLK_CNT; ++ #endif ++ u32_err = eMMC_WriteData_Ex(pu8_DataBuf, u32_DataByteCnt, u32_BlkAddr); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++} ++ ++U32 eMMC_WriteData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ volatile U16 u16_BlkCnt; ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ } ++ ++ if(NULL == pu8_DataBuf) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: w data buf is NULL: %ph \n", pu8_DataBuf); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // write data ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD25(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD24(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: W fail: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ return u32_err; ++} ++ ++ ++// ======================================================= ++// u32_DataByteCnt: has to be 512B-boundary ! ++// ======================================================= ++// ok: return 0 ++U32 eMMC_ReadData(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ eMMC_LockFCIE(NULL); ++ #if defined(MSOS_TYPE_ECOS) ++ u32_BlkAddr += eMMC_TOTAL_RESERVED_BLK_CNT; ++ #endif ++ u32_err = eMMC_ReadData_Ex(pu8_DataBuf, u32_DataByteCnt, u32_BlkAddr); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++} ++ ++U32 eMMC_ReadData_Ex(U8* pu8_DataBuf, U32 u32_DataByteCnt, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ volatile U16 u16_BlkCnt; ++ U8 u8_IfNotCacheLineAligned=0; ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"\n"); ++ ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ } ++ // check if u32_DataByteCnt is 512B boundary ++ if(u32_DataByteCnt & (eMMC_SECTOR_512BYTE-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: data not 512B boundary \n"); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if(u32_BlkAddr + (u32_DataByteCnt>>9) > g_eMMCDrv.u32_SEC_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: invalid data range, %Xh > %Xh \n", ++ u32_BlkAddr + (u32_DataByteCnt>>9), g_eMMCDrv.u32_SEC_COUNT); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ // read data ++ // first 512 bytes, special handle if not cache line aligned ++ if((uintptr_t)pu8_DataBuf & (eMMC_CACHE_LINE-1)) ++ { ++ #if 0 ++ eMMC_debug(eMMC_DEBUG_LEVEL_WARNING,1, ++ "eMMC Warn: R, buffer not Cache Line aligned: %Xh \n", ++ (U32)pu8_DataBuf); ++ #endif ++ ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.0: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ return u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ u32_BlkAddr += 1; ++ pu8_DataBuf += eMMC_SECTOR_512BYTE; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ ++ // last 512B must be not cache line aligned, ++ // reserved for last eMMC_CMD17_CIFD ++ if(u32_DataByteCnt){ ++ u8_IfNotCacheLineAligned = 1; ++ u32_DataByteCnt -= eMMC_SECTOR_512BYTE; ++ } ++ } ++ ++ while(u32_DataByteCnt) ++ { ++ if(u32_DataByteCnt > eMMC_SECTOR_512BYTE) ++ { ++ if((u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS) < BIT_SD_JOB_BLK_CNT_MASK) ++ u16_BlkCnt = (u32_DataByteCnt>>eMMC_SECTOR_512BYTE_BITS); ++ else ++ u16_BlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ ++ u32_err = eMMC_CMD18(u32_BlkAddr, pu8_DataBuf, u16_BlkCnt); ++ } ++ else ++ { ++ u16_BlkCnt = 1; ++ u32_err = eMMC_CMD17(u32_BlkAddr, pu8_DataBuf); ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.1: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ break; ++ } ++ ++ u32_BlkAddr += u16_BlkCnt; ++ pu8_DataBuf += u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ u32_DataByteCnt -= u16_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ } ++ ++ // last 512 bytes, special handle if not cache line aligned ++ if(u8_IfNotCacheLineAligned) ++ { ++ u32_err = eMMC_CMD17(u32_BlkAddr, gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: R fail.2: %Xh\n", u32_err); ++ g_eMMCDrv.u32_LastErrCode = u32_err; ++ } ++ memcpy(pu8_DataBuf, gau8_eMMC_SectorBuf, eMMC_SECTOR_512BYTE); ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_GetCapacity(U32 *pu32_TotalSectorCnt) // 1 sector = 512B ++{ ++ U32 u32_err; ++ ++ eMMC_LockFCIE(NULL); ++ // check if eMMC Init ++ if(eMMC_NOT_READY_MARK == sgu32_IfReadyGuard) ++ { ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC not ready (init) \n"); ++ eMMC_UnlockFCIE(NULL); ++ return eMMC_ST_ERR_NOT_INIT; ++ } ++ } ++ ++ *pu32_TotalSectorCnt = g_eMMCDrv.u32_SEC_COUNT; ++ #if defined(MSOS_TYPE_ECOS) ++ *pu32_TotalSectorCnt -= eMMC_TOTAL_RESERVED_BLK_CNT; ++ #endif ++ eMMC_UnlockFCIE(NULL); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++ #if defined(eMMC_FCIE_LINUX_DRIVER) && eMMC_FCIE_LINUX_DRIVER ++U32 eMMC_SearchDevNodeStartSector(void) ++{ ++ U32 u32_err; ++ volatile U16 u16_PartIdx; ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ eMMC_LockFCIE(NULL); ++ ++ u32_err = eMMC_CheckIfReady(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: init fail: %Xh\n", u32_err); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_GetPartitionIndex(eMMC_PART_DEV_NODE, 0, &u16_PartIdx); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: GetPartitionIndex fail: %Xh\n", u32_err); ++ eMMC_UnlockFCIE(NULL); ++ return u32_err; ++ } ++ ++ g_eMMCDrv.u32_PartDevNodeStartSector = pPartInfo->records[u16_PartIdx].u16_StartBlk; ++ g_eMMCDrv.u32_PartDevNodeStartSector *= pPartInfo->u16_BlkPageCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt = pPartInfo->records[u16_PartIdx].u16_BlkCnt; ++ g_eMMCDrv.u16_PartDevNodeSectorCnt *= pPartInfo->u16_BlkPageCnt; ++ eMMC_UnlockFCIE(NULL); ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ int get_NVRAM_start_sector(unsigned int *u32_startsector) ++{ ++ ++ ++ eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ ++ U16 u16_PartIdx; ++ eMMC_LockFCIE(NULL); ++ ++ if(eMMC_ST_SUCCESS==eMMC_GetPartitionIndex(eMMC_PART_NVRAM, 0, &u16_PartIdx)) ++ { ++ *u32_startsector = pPartInfo->records[u16_PartIdx].u16_StartBlk * pPartInfo->u16_BlkPageCnt; ++ printk(KERN_INFO"eMMC_PART_NVRAM start sector: %X\r\n",*u32_startsector); ++ eMMC_UnlockFCIE(NULL); ++ ++ return 0; ++ } ++ ++ eMMC_UnlockFCIE(NULL); ++ ++ return -1; ++} ++ //only support p1~p7 for each EMMC device in Linux ++ int get_NVRAM_max_part_count(void) ++ { ++ //eMMC_PNI_t *pPartInfo = (eMMC_PNI_t*)gau8_eMMC_PartInfoBuf; ++ //return (pPartInfo->u16_PartCnt-1); ++ return 0x0C; ++ } ++ ++ ++ int get_DEVNODE_start_sector(unsigned int *u32_startsector) ++ { ++ u32 u32_err; ++ if(0 == g_eMMCDrv.u32_PartDevNodeStartSector){ ++ u32_err = eMMC_SearchDevNodeStartSector(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ printk(KERN_ERR"** Err, %s **\n", __func__); ++ return (-1); ++ } ++ } ++ ++ *u32_startsector=g_eMMCDrv.u32_PartDevNodeStartSector; ++ ++ ++ return 0; ++ ++ } ++ ++ ++ EXPORT_SYMBOL(get_DEVNODE_start_sector); ++ EXPORT_SYMBOL(get_NVRAM_max_part_count); ++ ++ #endif ++#endif ++ +diff --git a/drivers/mstar/emmc/unify_driver/src/common/eMMC_hal.c b/drivers/mstar/emmc/unify_driver/src/common/eMMC_hal.c +new file mode 100644 +index 00000000..44871a9e +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/src/common/eMMC_hal.c +@@ -0,0 +1,3809 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//======================================================== ++// HAL pre-processors ++//======================================================== ++#if IF_FCIE_SHARE_IP ++ // re-config FCIE3 for NFIE mode ++ #define eMMC_RECONFIG() //eMMC_ReConfig(); ++#else ++ // NULL to save CPU a JMP/RET time ++ #define eMMC_RECONFIG() ++#endif ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) \ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSPFROMRAM_SAVE)\ ++ eMMC_KeepRsp(pu8_OneRspBuf, u8_CmdIdx) ++#else ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) // NULL to save CPU a JMP/RET time ++#endif ++ ++ ++#define eMMC_FCIE_CLK_DIS() REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN) ++ ++#define eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT 20 ++#define eMMC_CMD_API_ERR_RETRY_CNT 20 ++#define eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT 20 ++ ++#define eMMC_CMD1_RETRY_CNT 0x8000 ++#define eMMC_CMD3_RETRY_CNT 0x5 ++ ++static U32 (*sgpFn_eMMC_FCIE_WaitEvents_Ex)(U32, U16, U32) = NULL; ++//======================================================== ++// HAL APIs ++//======================================================== ++U32 eMMC_FCIE_WaitEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ return (*sgpFn_eMMC_FCIE_WaitEvents_Ex)(u32_RegAddr, u16_Events, u32_MicroSec); ++} ++ ++ ++U32 eMMC_FCIE_PollingEvents(U32 u32_RegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ volatile U32 u32_i, u32_DelayX; ++ volatile U16 u16_val; ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); // mask interrupts ++ if(u32_MicroSec > HW_TIMER_DELAY_100us) ++ { ++ u32_DelayX = HW_TIMER_DELAY_100us/HW_TIMER_DELAY_1us; ++ u32_MicroSec /= u32_DelayX; ++ } ++ else ++ u32_DelayX = 1; ++ ++ for(u32_i=0; u32_i>REG_OFFSET_SHIFT_BITS, ++ u16_val, u16_Events); ++ ++ return eMMC_ST_ERR_TIMEOUT_WAIT_REG0; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static U16 sgau16_eMMCDebugBus[100]; ++void eMMC_FCIE_DumpDebugBus(void) ++{ ++ volatile U16 u16_reg, u16_i; ++ U16 u16_idx = 0; ++ ++ memset(sgau16_eMMCDebugBus, 0xFF, sizeof(sgau16_eMMCDebugBus)); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ ++ for(u16_i=0; u16_i<8; u16_i++) ++ { ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_FCIE_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, u16_i< 0; u16_i--) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "%u ", u16_i); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ ++ // check FCIE reg.30h ++ REG_FCIE_R(FCIE_TEST_MODE, u16_reg); ++ if(0)//u16_reg & BIT_FCIE_BIST_FAIL) /* Andersen: "don't care." */ ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h BIST fail: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_BIST_FAIL; ++ } ++ if(u16_reg & BIT_FCIE_DEBUG_MODE_MASK) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h Debug Mode: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_DEBUG_MODE; ++ } ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ } ++ #endif // eMMC_TEST_IN_DESIGN ++ ++ // ------------------------------------------ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); ++ REG_FCIE_W(FCIE_MMA_PRI_REG, BIT_MIU_CLK_FREE_RUN); ++ REG_FCIE_W(FCIE_PATH_CTRL, BIT_SD_EN); ++ // all cmd are 5 bytes (excluding CRC) ++ REG_FCIE_W(FCIE_CMD_SIZE, eMMC_CMD_BYTE_CNT); ++ REG_FCIE_W(FCIE_SD_CTRL, 0); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ #if FICE_BYTE_MODE_ENABLE ++ // default sector size: 0x200 ++ REG_FCIE_W(FCIE_SDIO_CTRL, BIT_SDIO_BLK_MODE | eMMC_SECTOR_512BYTE); ++ #else ++ REG_FCIE_W(FCIE_SDIO_CTRL, 0); ++ #endif ++ ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, 0); ++ eMMC_FCIE_ClearEvents(); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; // ok ++} ++ ++ ++void eMMC_FCIE_ClearEvents(void) ++{ ++ volatile U16 u16_reg; ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_MIU_REQUEST_RST); ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++ REG_FCIE_W1C(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); // W1C ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_REQUEST_RST); ++} ++ ++ ++void eMMC_FCIE_ClearEvents_Reg0(void) ++{ ++ volatile U16 u16_reg; ++ ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++} ++ ++ ++U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ volatile U16 u16_read0=0, u16_read1=0; ++ ++ for(u32_cnt=0; u32_cnt < u32_us; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read0); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read1); ++ ++ if((u16_read0&BIT_SD_CARD_D0_ST) && (u16_read1&BIT_SD_CARD_D0_ST)) ++ break; ++ ++ // interrupt mode, then sleep ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ if(eMMC_WaitCompleteIntr == sgpFn_eMMC_FCIE_WaitEvents_Ex) ++ if(u32_cnt > 500 && u32_us-u32_cnt > 1000) ++ { ++ eMMC_hw_timer_sleep(1); ++ u32_cnt += 1000-2; ++ } ++ #endif ++ } ++ ++ return u32_cnt; ++} ++ ++ ++U32 eMMC_FCIE_WaitD0High(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ u32_cnt = eMMC_FCIE_WaitD0High_Ex(u32_us); ++ ++ if(u32_us == u32_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H timeout %u us\n", u32_cnt); ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++#define FIFO_CLK_RDY_CHECK_CNT 3 ++U32 eMMC_FCIE_FifoClkRdy(U8 u8_Dir) ++{ ++ volatile U32 u32_cnt=0; ++ volatile U16 au16_read[FIFO_CLK_RDY_CHECK_CNT], u16_i; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_MMA_PRI_REG, au16_read[0]); ++ if(u8_Dir == (au16_read[0]&BIT_DMA_DIR_W)) ++ break; ++ } ++ if(TIME_WAIT_FIFOCLK_RDY == u32_cnt) ++ return eMMC_ST_ERR_TIMEOUT_FIFOCLKRDY; ++ ++ for(u32_cnt=0; u32_cnt < TIME_WAIT_FIFOCLK_RDY; u32_cnt++) ++ { ++ for(u16_i=0; u16_i>24)<<8) | (0x40|u8_CmdIdx)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(1), (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++ REG_FCIE_W(FCIE_CIFC_ADDR(2), u32_Arg&0xFF); ++ ++ REG_FCIE_R(FCIE_CIFC_ADDR(0),au16_tmp[0]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(1),au16_tmp[1]); ++ REG_FCIE_R(FCIE_CIFC_ADDR(2),au16_tmp[2]); ++ ++ if(au16_tmp[0] == (((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx))&& ++ au16_tmp[1] == ((u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF))&& ++ au16_tmp[2] == (u32_Arg&0xFF)) ++ break; ++ } ++ ++ if(12 != u8_CmdIdx) ++ { ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl); ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_SD_CMD_END); ++ #endif ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSP_WAIT_D0H){ ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ // wait event ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_SD_CMD_END, TIME_WAIT_CMDRSP_END); ++ ++ LABEL_SEND_CMD_ERROR: ++ return u32_err; ++ ++} ++ ++ ++void eMMC_FCIE_GetCIFC(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i>1)); ++ ++ if(u8addr&0x1) ++ { ++ return ((u16Tmp>>8)&0xFF); ++ } ++ else ++ { ++ return (u16Tmp&0xFF); ++ } ++} ++ ++U8 eMMC_FCIE_DataFifoGet(U8 u8addr) ++{ ++ U16 u16Tmp; ++ ++ u16Tmp = REG_FCIE(FCIE_CIFD_ADDR(u8addr>>1)); ++ ++ if(u8addr&0x1) ++ return ((u16Tmp>>8)&0xFF); ++ else ++ return (u16Tmp&0xFF); ++} ++ ++//=================================================== ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ eMMC_die("\n"); // should be system fatal error, not eMMC driver ++ } ++ ++ memcpy(g_eMMCDrv.au8_AllRsp + u16_idx, pu8_OneRspBuf, u8_ByteCnt); ++ ++} ++ ++ ++U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ if(0 == g_eMMCDrv.au8_AllRsp[u16_idx]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: no rsp, %u %u \n", u8_CmdIdx, u16_idx); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ memcpy(pu8_OneRspBuf, g_eMMCDrv.au8_AllRsp + u16_idx, u8_ByteCnt); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ------------------------------- ++U32 eMMC_SaveRsp(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_SaveDriverContext(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_LoadDriverContext(U8 *pu8_Buf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++//======================================================== ++// Send CMD HAL APIs ++//======================================================== ++U32 eMMC_Identify(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_i, u16_retry=0; ++ ++ g_eMMCDrv.u16_RCA=1; ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ ++ LABEL_IDENTIFY_CMD0: ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(u16_retry > 10) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ if(u16_retry) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Warn: retry: %u\n", u16_retry); ++ ++ // CMD0 ++ u32_err = eMMC_CMD0(0); // reset to idle state ++ if(eMMC_ST_SUCCESS != u32_err) ++ {u16_retry++; goto LABEL_IDENTIFY_CMD0;} ++ ++ // CMD1 ++ for(u16_i=0; u16_i>6; ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 1); ++ } ++ } ++ #else ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD1 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD1 ok, do things here ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ else ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ } ++ } ++ #endif ++ ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// send CID ++U32 eMMC_CMD2(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 2, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD2, %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD2; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD2 Reg.12: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD2 ok, do things here (get CID) ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CID); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CID, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CID, 2); ++ } ++ } ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// CMD3: assign RCA. CMD7: select device ++U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ if(7 == u8_CmdIdx) ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ else{ ++ u8_retry_fcie = 0xF0; // CMD3: not retry ++ } ++ ++ u32_arg = u16_RCA<<16; ++ ++ if(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA) ++ u16_ctrl = BIT_SD_CMD_EN; ++ else ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ return u32_err; ++ } ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ // de-select has no rsp ++ if(!(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA)){ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ return u32_err; ++ } ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u Reg.12: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ return u32_err; ++ } ++ ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ }} ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_CSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------ ++ g_eMMCDrv.u8_SPEC_VERS = (g_eMMCDrv.au8_CSD[1]&0x3C)>>2; ++ g_eMMCDrv.u8_R_BL_LEN = g_eMMCDrv.au8_CSD[6] & 0xF; ++ g_eMMCDrv.u8_W_BL_LEN = ((g_eMMCDrv.au8_CSD[13]&0x3)<<2)+ ++ ((g_eMMCDrv.au8_CSD[14]&0xC0)>>6); ++ ++ // ------------------------------ ++ g_eMMCDrv.u16_C_SIZE = (g_eMMCDrv.au8_CSD[7] & 3)<<10; ++ g_eMMCDrv.u16_C_SIZE += g_eMMCDrv.au8_CSD[8] << 2; ++ g_eMMCDrv.u16_C_SIZE +=(g_eMMCDrv.au8_CSD[9] & 0xC0) >> 6; ++ if(0xFFF == g_eMMCDrv.u16_C_SIZE) ++ { ++ g_eMMCDrv.u32_SEC_COUNT = 0; ++ } ++ else ++ { ++ g_eMMCDrv.u8_C_SIZE_MULT = ((g_eMMCDrv.au8_CSD[10]&3)<<1)+ ++ ((g_eMMCDrv.au8_CSD[11]&0x80)>>7); ++ ++ g_eMMCDrv.u32_SEC_COUNT = ++ (g_eMMCDrv.u16_C_SIZE+1)* ++ (1<<(g_eMMCDrv.u8_C_SIZE_MULT+2))* ++ ((1<>9) - 8; // -8: //Toshiba CMD18 access the last block report out of range error ++ } ++ // ------------------------------ ++ g_eMMCDrv.u8_ERASE_GRP_SIZE = (g_eMMCDrv.au8_CSD[10]&0x7C)>>2; ++ g_eMMCDrv.u8_ERASE_GRP_MULT = ((g_eMMCDrv.au8_CSD[10]&0x03)<<3)+ ++ ((g_eMMCDrv.au8_CSD[11]&0xE0)>>5); ++ g_eMMCDrv.u32_EraseUnitSize = (g_eMMCDrv.u8_ERASE_GRP_SIZE+1)* ++ (g_eMMCDrv.u8_ERASE_GRP_MULT+1); ++ // ------------------------------ ++ // others ++ g_eMMCDrv.u8_TAAC = g_eMMCDrv.au8_CSD[2]; ++ g_eMMCDrv.u8_NSAC = g_eMMCDrv.au8_CSD[3]; ++ g_eMMCDrv.u8_Tran_Speed = g_eMMCDrv.au8_CSD[4]; ++ g_eMMCDrv.u8_R2W_FACTOR = (g_eMMCDrv.au8_CSD[13]&0x1C)>>2; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// send CSD (in R2) ++U32 eMMC_CMD9(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_RCA<<16; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 9, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD9 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD9; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD9 Reg.12: %04Xh, Retry fail: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD2 ok, do things here ++ eMMC_FCIE_GetCIFC(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CSD); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CSD, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CSD, 9); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_ExtCSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD8(gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_dump_mem(gau8_eMMC_SectorBuf, 0x200); ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((gau8_eMMC_SectorBuf[215]<<24)| ++ (gau8_eMMC_SectorBuf[214]<<16)| ++ (gau8_eMMC_SectorBuf[213]<< 8)| ++ (gau8_eMMC_SectorBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = gau8_eMMC_SectorBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ if(!g_eMMCDrv.u8_BUS_WIDTH) { ++ g_eMMCDrv.u8_BUS_WIDTH = gau8_eMMC_SectorBuf[183]; ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ } ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[503]&BIT0) // HPI ++ { ++ if(gau8_eMMC_SectorBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ }else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ #else ++ if((gau8_eMMC_SectorBuf[503]&BIT0) && 1==gau8_eMMC_SectorBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(gau8_eMMC_SectorBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ else ++ { ++ //eMMC_debug(0,1,"eMMC Warn: not support dynamic Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = gau8_eMMC_SectorBuf[181]; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ECSD185_HsTiming = gau8_eMMC_SectorBuf[185]; ++ g_eMMCDrv.u8_ECSD192_Ver = gau8_eMMC_SectorBuf[192]; ++ g_eMMCDrv.u8_ECSD196_DevType = gau8_eMMC_SectorBuf[196]; ++ g_eMMCDrv.u8_ECSD197_DriverStrength = gau8_eMMC_SectorBuf[197]; ++ g_eMMCDrv.u8_ECSD248_CMD6TO = gau8_eMMC_SectorBuf[248]; ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO = gau8_eMMC_SectorBuf[247]; ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl = gau8_eMMC_SectorBuf[34]; ++ ++ //for GP Partition ++ g_eMMCDrv.u8_ECSD160_PartSupField = gau8_eMMC_SectorBuf[160]; ++ g_eMMCDrv.u8_ECSD224_HCEraseGRPSize= gau8_eMMC_SectorBuf[224]; ++ g_eMMCDrv.u8_ECSD221_HCWpGRPSize= gau8_eMMC_SectorBuf[221]; ++ ++ g_eMMCDrv.GP_Part[0].u32_PartSize = ((gau8_eMMC_SectorBuf[145] << 16) | ++ (gau8_eMMC_SectorBuf[144] << 8) | ++ (gau8_eMMC_SectorBuf[143])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[1].u32_PartSize = ((gau8_eMMC_SectorBuf[148] << 16) | ++ (gau8_eMMC_SectorBuf[147] << 8) | ++ (gau8_eMMC_SectorBuf[146])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[2].u32_PartSize = ((gau8_eMMC_SectorBuf[151] << 16) | ++ (gau8_eMMC_SectorBuf[150] << 8) | ++ (gau8_eMMC_SectorBuf[149])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[3].u32_PartSize = ((gau8_eMMC_SectorBuf[154] << 16) | ++ (gau8_eMMC_SectorBuf[153] << 8) | ++ (gau8_eMMC_SectorBuf[152])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ //for Max Enhance Size ++ g_eMMCDrv.u8_ECSD157_MaxEnhSize_0= gau8_eMMC_SectorBuf[157]; ++ g_eMMCDrv.u8_ECSD158_MaxEnhSize_1= gau8_eMMC_SectorBuf[158]; ++ g_eMMCDrv.u8_ECSD159_MaxEnhSize_2= gau8_eMMC_SectorBuf[159]; ++ ++ g_eMMCDrv.u8_u8_ECSD155_PartSetComplete = gau8_eMMC_SectorBuf[155]; ++ g_eMMCDrv.u8_ECSD166_WrRelParam = gau8_eMMC_SectorBuf[166]; ++ ++ //-------------------------------- ++ // set HW RST ++ if(0 == gau8_eMMC_SectorBuf[162]) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 162, BIT0); // RST_FUNC ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[162]: %Xh fail\n", ++ u32_err, BIT0); ++ return u32_err; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_CMD8(U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD8_CIFD(pu8_DataBuf); ++ #else ++ return eMMC_CMD8_MIU(pu8_DataBuf); ++ #endif ++} ++ ++// CMD8: send EXT_CSD ++U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr, u32_DataMapAddr; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_DataMapAddr = eMMC_DMA_MAP_address((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(u32_DataMapAddr, eMMC_SECTOR_512BYTE); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_DataDMAAddr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD8 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200)) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ volatile U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0;; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ //eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 8); ++ ++ // ------------------------------- ++ // CMD8 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetPwrOffNotification(U8 u8_SetECSD34) ++{ ++ U32 u32_err; ++ static U8 u8_OldECSD34=0; ++ ++ if(eMMC_PwrOffNotif_SHORT==u8_OldECSD34 || eMMC_PwrOffNotif_LONG==u8_OldECSD34) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: PwrOffNotif already set: %u, now: %u\n", ++ u8_OldECSD34, u8_SetECSD34); ++ return eMMC_ST_SUCCESS; ++ } ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 34, u8_SetECSD34); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_PwrOffNotif_MASK; ++ switch(u8_SetECSD34) ++ { ++ case eMMC_PwrOffNotif_OFF: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_OFF; break; ++ case eMMC_PwrOffNotif_ON: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_ON; break; ++ case eMMC_PwrOffNotif_SHORT: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_SHORT; break; ++ case eMMC_PwrOffNotif_LONG: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_LONG; break; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Sanitize(U8 u8_ECSD165) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 165, u8_ECSD165); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH<<2); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#define BITS_MSK_DRIVER_STRENGTH 0xF0 ++#define BITS_MSK_TIMING 0x0F ++ ++U32 eMMC_SetBusSpeed(U8 u8_BusSpeed) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_TIMING; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8_BusSpeed; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_SPEED_MASK; ++ switch(u8_BusSpeed) ++ { ++ case eMMC_SPEED_HIGH: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_SYNC; ++ break; ++ case eMMC_SPEED_HS200: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS200; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ break; ++ case eMMC_SPEED_HS400: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS400; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ break; ++ default: ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_SYNC; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_SetDrivingStrength(U8 u8Driving) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_DRIVER_STRENGTH; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8Driving<<4; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); // HS_TIMING, HS200 ++ if(eMMC_ST_SUCCESS != u32_err) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail: %Xh\n", u32_err); ++ return eMMC_ST_ERR_SET_DRV_STRENGTH; ++ } ++ return eMMC_ST_SUCCESS; ++} ++ ++// Use CMD6 to set ExtCSD[183] BUS_WIDTH ++U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR) ++{ ++ U8 u8_value; ++ U32 u32_err; ++ ++ // ------------------------------- ++ switch(u8_BusWidth) ++ { ++ case 1: u8_value=0; break; ++ case 4: u8_value=1; break; ++ case 8: u8_value=2; break; ++ default: return eMMC_ST_ERR_PARAMETER; ++ } ++ ++ if(u8_IfDDR) ++ { ++ u8_value |= BIT2; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_MODE; ++ } ++ else ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_MODE; ++ ++ ++ // ------------------------------- ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 183, u8_value); // BUS_WIDTH ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------- ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ switch(u8_BusWidth) ++ { ++ case 1: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_1; ++ break; ++ case 4: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_4; ++ break; ++ case 8: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_8; ++ break; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"set %u bus width\n", u8_BusWidth); ++ return u32_err; ++} ++ ++U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ U32 u32_arg, u32_err; ++ ++ u32_arg = ((u8_AccessMode&3)<<24) | (u8_ByteIdx<<16) | ++ (u8_Value<<8); ++ ++ u32_err = eMMC_CMD6(u32_arg); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Warn: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++// SWITCH cmd ++U32 eMMC_CMD6(U32 u32_Arg) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_Arg; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 6, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD6; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 6); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err; ++ U8 u8_retry_cmd=0; ++ ++ LABEL_SEND_CMD: ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_start, 35); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_end, 36); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD38(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEN_END: ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u fail, %Xh \n", ++ u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u Reg.12: %04Xh \n", u8_CmdIdx, u16_reg); ++ return eMMC_ST_ERR_CMD3536_ERR; ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh\n", u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD38(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ u32_arg = 0x1; ++ else ++ u32_arg = 0x0; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 38, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD38 fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD38_ERR; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 Reg.12: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD38 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 check R1 error: %Xh\n", u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 38); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++// CMD13: send Status ++U32 eMMC_CMD13(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0;// ,u8_retry_r1=0; ++ ++ u32_arg = (u16_RCA<<16); // | ++ // ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD13)?1:0); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 13, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ #if 0 ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ #else ++ eMMC_debug(0, 1, ++ "eMMC: CMD13 check R1 error: %Xh, should not retry\n", u32_err); ++ #endif ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 13); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD16(U32 u32_BlkLength) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_BlkLength; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 16, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD16; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD16 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 16); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++//------------------------------------------------ ++ ++U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD17_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD17_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++#if 0 ++static U32 u32_TestCnt=0; ++#define IF_TEST_RETRY(x) (0==++u32_TestCnt%x) ++#else ++#define IF_TEST_RETRY(x) (0)//==++u32_TestCnt%x) ++#endif ++ ++U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr, u32_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_DataMapAddr = eMMC_DMA_MAP_address((U32)pu8_DataBuf,eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(u32_DataMapAddr, eMMC_SECTOR_512BYTE); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_DataDMAAddr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD17 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(7) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200)) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ //if(0 == eMMC_IF_TUNING_TTABLE()) ++ // eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ sgu8_IfNeedRestorePadType = g_eMMCDrv.u8_PadType; ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(28) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // CMD17 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ if(IF_TEST_RETRY(10) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(IF_TEST_RETRY(3) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check Reg.12: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD12; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check Reg.12: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 12); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12_NoCheck(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++ ++U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD18 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(20) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE|BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>11))); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 Reg.12: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(24) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(1, 1, "eMMC Err: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200)) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++ ++} ++ ++ ++// enable Reliable Write ++U32 eMMC_CMD23(U16 u16_BlkCnt) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_BlkCnt&0xFFFF; // don't set BIT24 ++ #if defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE ++ u32_arg |= BIT31; // don't set BIT24 ++ #endif ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 23, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 Reg.12: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 23); ++ ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ #endif ++ ++ #if eMMC_BURST_LEN_AUTOCFG || ENABLE_eMMC_RIU_MODE ++ U16 u16_RetryCnt=0; ++ LABEL_CMD25: ++ #endif ++ // ------------------------------RIU mode ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ for(u16_cnt=0; u16_cnt g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen ? ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen : u16_BlkCnt-u16_blk_pos; ++ u16_blk_cnt = u16_blk_cnt == g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen ? ++ u16_blk_cnt/2 : u16_blk_cnt; ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMCBlkAddr+u16_blk_pos, ++ pu8_DataBuf+(u16_blk_pos< u32_t1-u32_t0) ++ { ++ u32_tMin = u32_t1-u32_t0; ++ u16_BestBlkCnt = u16_BurstBlkCnt; ++ } ++ if(u32_tMax < u32_t1-u32_t0) ++ { ++ u32_tMax = u32_t1-u32_t0; ++ u16_WorstBlkCnt = u16_BurstBlkCnt; ++ } ++ ++ if(MAX_DETECT_BLK_CNT != u16_BurstBlkCnt) ++ goto LABEL_DETECT; ++ ++ // -------------------------- ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen = u16_BestBlkCnt; ++ g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen = u16_WorstBlkCnt; ++ ++ u32_tmp = (U32)(MAX_DETECT_BLK_CNT<> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)& 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr >> MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(IF_TEST_RETRY(32) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD25 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(1, 1, "eMMC WARN: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>9))); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(43) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ #if 1 //!(defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE) ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ #endif ++ ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD24_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD24_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fifoclk=0, u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr, u32_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) { ++ ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_W : TOGGLE_CNT_256_CLK_W); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ u32_DataMapAddr = eMMC_DMA_MAP_address((U32)pu8_DataBuf, eMMC_SECTOR_512BYTE,0); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(u32_DataMapAddr, eMMC_SECTOR_512BYTE); ++ #if FICE_BYTE_MODE_ENABLE ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_DataDMAAddr >> 16); ++ #else ++ REG_FCIE_W(FCIE_MIU_DMA_15_0, (u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)&0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_26_16,(u32_DataDMAAddr>>MIU_BUS_WIDTH_BITS)>>16); ++ #endif ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_fifoclk < eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fifoclk++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC WARN: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_Init(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: CMD24 wait FIFOClk retry: %u \n", u8_retry_fifoclk); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(25) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(34) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_MIU_WAIT_D0H; ++ goto LABEL_END; ++ } ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_CARD_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(11) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: CMD24 %sReg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 %sReg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_DMA_UNMAP_address(u32_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i, *pu16_dat=(U16*)pu8_DataBuf; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ ++ // fill CIFD with data ++ REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ for(u16_i=0; u16_i<(FCIE_CIFD_BYTE_CNT>>1); u16_i++) ++ REG_FCIE_W(FCIE_CIFD_ADDR(u16_i), pu16_dat[u16_i]); ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ sgu8_IfNeedRestorePadType = g_eMMCDrv.u8_PadType; ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_ClearEvents(); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(19) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_SD_DATA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 TO Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD Reg.12: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(u8_retry_fcie) ++ eMMC_debug(0,1,"eMMC Info: retry ok\n"); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_GetR1(void) ++{ ++ return (g_eMMCDrv.au8_Rsp[1]<<24) | (g_eMMCDrv.au8_Rsp[2]<<16) ++ | (g_eMMCDrv.au8_Rsp[3]<<8) | g_eMMCDrv.au8_Rsp[4]; ++} ++ ++U32 eMMC_CheckR1Error(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ ++ if(g_eMMCDrv.au8_Rsp[1] & (eMMC_ERR_R1_31_24>>24)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_31_24 \n "); ++ u32_err = eMMC_ST_ERR_R1_31_24; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[2] & (eMMC_ERR_R1_23_16>>16)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_23_16 \n "); ++ u32_err = eMMC_ST_ERR_R1_23_16; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[3] & (eMMC_ERR_R1_15_8>>8)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_15_8 \n "); ++ u32_err = eMMC_ST_ERR_R1_15_8; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[4] & (eMMC_ERR_R1_7_0>>0)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_7_0 \n "); ++ u32_err = eMMC_ST_ERR_R1_7_0; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++LABEL_CHECK_R1_END: ++ ++ /*u8_cs = (eMMC_FCIE_CmdRspBufGet(3) & (eMMC_R1_CURRENT_STATE>>8))>>1; ++ eMMC_debug(0,0,"card state: %d ", u8_cs); ++ switch(u8_cs) { ++ case 0: eMMC_debug(0,0,"(idle)\n"); break; ++ case 1: eMMC_debug(0,0,"(ready)\n"); break; ++ case 2: eMMC_debug(0,0,"(ident)\n"); break; ++ case 3: eMMC_debug(0,0,"(stby)\n"); break; ++ case 4: eMMC_debug(0,0,"(tran)\n"); break; ++ case 5: eMMC_debug(0,0,"(data)\n"); break; ++ case 6: eMMC_debug(0,0,"(rcv)\n"); break; ++ case 7: eMMC_debug(0,0,"(prg)\n"); break; ++ case 8: eMMC_debug(0,0,"(dis)\n"); break; ++ default: eMMC_debug(0,0,"(?)\n"); break; ++ }*/ ++ ++ if(eMMC_ST_SUCCESS != u32_err)// && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R1_BYTE_CNT); ++ } ++ return u32_err; ++} ++ ++ ++// ==================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define UPFW_SEC_WIAT_CNT 0x1000000 ++#define UPFW_SEC_BYTE_CNT (128*1024) ++static U32 eMMC_UpFW_Samsung_Wait(void) ++{ ++ U32 u32_err, u32_cnt, u32_st; ++ ++ for(u32_cnt=0; u32_cnt>eMMC_SECTOR_512BYTE_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: write fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 3, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ // --------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"close ... \n"); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, 0, 28, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD28 fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 4, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ LABEL_END_OF_UPFW: ++ return u32_err; ++ ++} ++#endif // eMMC_UPDATE_FIRMWARE ++ ++void HalFcie_SetFlag4Kernel2RuneMMC(void) ++{ ++ REG_FCIE_CLRBIT(FCIE_REG16h, BIT_KERN_CHK_NAND_EMMC_MSK); ++ REG_FCIE_SETBIT(FCIE_REG16h, BIT_KERN_EMMC); ++} ++ ++bool HalFcie_CheckIfeMMCRun4Kernel(void) ++{ ++ u16 u16_regval = 0; ++ ++ u16_regval = REG_FCIE(FCIE_REG16h); ++ ++ if( (u16_regval & BIT_KERN_CHK_NAND_EMMC) == BIT_KERN_CHK_NAND_EMMC ) ++ { ++ return ( (u16_regval & BIT_KERN_EMMC) != BIT_KERN_EMMC ) ? 0 : 1; ++ } ++ return 0; ++} ++ ++#endif // UNIFIED_eMMC_DRIVER ++ +diff --git a/drivers/mstar/emmc/unify_driver/src/common/eMMC_hal_speed.c b/drivers/mstar/emmc/unify_driver/src/common/eMMC_hal_speed.c +new file mode 100644 +index 00000000..f33df182 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/src/common/eMMC_hal_speed.c +@@ -0,0 +1,704 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++ ++// ========================================================== ++U32 eMMC_FCIE_EnableSDRMode(void) ++{ ++ U32 u32_ErrSpeed = eMMC_ST_SUCCESS, u32_ErrWidth = eMMC_ST_SUCCESS, u32_Err = eMMC_ST_SUCCESS; ++ ++ // ---------------------------------------- ++ // may call from any other interface status ++ #if 0 ++ if(DRV_FLAG_SPEED_HS200 == eMMC_SPEED_MODE()) ++ { ++ u32_ErrSpeed = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ } ++ else if(DRV_FLAG_SPEED_HS400 == eMMC_SPEED_MODE()) ++ { ++ u32_ErrSpeed = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ u32_ErrWidth = eMMC_SetBusWidth(8, 0); ++ } ++ else ++ #else ++ if(DRV_FLAG_SPEED_HS200 == eMMC_SPEED_MODE()|| ++ DRV_FLAG_SPEED_HS400 == eMMC_SPEED_MODE()) ++ { ++ u32_Err = eMMC_FCIE_ErrHandler_ReInit_Ex(); ++ if(eMMC_ST_SUCCESS != u32_Err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_Err); ++ return u32_Err; ++ } ++ } ++ #endif ++ { ++ u32_ErrSpeed = eMMC_SetBusSpeed(eMMC_SPEED_HIGH); ++ u32_ErrWidth = eMMC_SetBusWidth(8, 0); ++ } ++ ++ if(eMMC_ST_SUCCESS!=u32_ErrSpeed || eMMC_ST_SUCCESS!=u32_ErrWidth) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh %Xh\n", u32_ErrSpeed, u32_ErrWidth); ++ return u32_ErrSpeed ? u32_ErrSpeed : u32_ErrWidth; ++ } ++ ++ // ---------------------------------------- ++ // set to normal SDR 48MHz ++ eMMC_pads_switch(FCIE_eMMC_SDR); ++ eMMC_clock_setting(FCIE_DEFAULT_CLK); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// =========================== ++#if !(defined(ENABLE_eMMC_ATOP) && ENABLE_eMMC_ATOP) ++void eMMC_DumpDDR48TTable(void) ++{ ++ U16 u16_i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC DDR Timing Table: Cnt:%u CurIdx:%u \n", ++ g_eMMCDrv.TimingTable_t.u8_SetCnt, g_eMMCDrv.TimingTable_t.u8_CurSetIdx); ++ ++ for(u16_i=0; u16_i ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//======================================================== ++// HAL pre-processors ++//======================================================== ++#if IF_FCIE_SHARE_IP ++ // re-config FCIE3 for NFIE mode ++ #define eMMC_RECONFIG() //eMMC_ReConfig(); ++#else ++ // NULL to save CPU a JMP/RET time ++ #define eMMC_RECONFIG() ++#endif ++ ++ ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) \ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSPFROMRAM_SAVE)\ ++ eMMC_KeepRsp(pu8_OneRspBuf, u8_CmdIdx) ++#else ++ #define eMMC_KEEP_RSP(pu8_OneRspBuf, u8_CmdIdx) // NULL to save CPU a JMP/RET time ++#endif ++ ++ ++#define eMMC_FCIE_CLK_DIS() REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_CLK_EN) ++ ++#define eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT 20 ++#define eMMC_CMD_API_ERR_RETRY_CNT 20 ++#define eMMC_CMD_API_WAIT_FIFOCLK_RETRY_CNT 20 ++ ++#define eMMC_CMD1_RETRY_CNT 0x8000 ++#define eMMC_CMD3_RETRY_CNT 0x5 ++ ++void eMMC_FCIE_GetCMDFIFO(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf); ++ ++static U32 (*sgpFn_eMMC_FCIE_WaitEvents_Ex)(uintptr_t, U16, U32) = NULL; ++void (*sleep_or_delay)(U32) = msleep; ++//======================================================== ++// HAL APIs ++//======================================================== ++U32 eMMC_FCIE_WaitEvents(uintptr_t ulongRegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ return (*sgpFn_eMMC_FCIE_WaitEvents_Ex)(ulongRegAddr, u16_Events, u32_MicroSec); ++} ++ ++U32 eMMC_FCIE_PollingEvents(uintptr_t ulongRegAddr, U16 u16_Events, U32 u32_MicroSec) ++{ ++ volatile U32 u32_i, u32_DelayX; ++ volatile U16 u16_val; ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); // mask interrupts ++ if(u32_MicroSec > HW_TIMER_DELAY_100us) ++ { ++ u32_DelayX = HW_TIMER_DELAY_100us/HW_TIMER_DELAY_1us; ++ u32_MicroSec /= u32_DelayX; ++ } ++ else ++ u32_DelayX = 1; ++ ++ for(u32_i=0; u32_i>REG_OFFSET_SHIFT_BITS, ++ u16_val, u16_Events); ++ ++ return eMMC_ST_ERR_TIMEOUT_WAIT_REG0; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++char *gDebugModeName[] = ++{ ++ NULL, ++ NULL, //"NAND", ++ NULL, //"CIFD", ++ "MMA", ++ NULL, //"BOOT", ++ "CARD", ++ NULL, //"BIST", ++ NULL, ++ "REG_QIFX_CNT", ++ "REG_QIFY_CNT", ++ "REG_DMA_REQ_CNT", ++ "REG_DMA_RSP_CNT", ++ NULL, //"BOOT_RDATA_CNT", ++ NULL, //"BIST_RDATA_CNT", ++ NULL, //"MACRO_DBUS1", ++ NULL, //"MACRO_DBUS2", ++}; ++ ++void eMMC_FCIE_DumpDebugBus(void) ++{ ++ U16 u16_i; ++ U16 u16_j; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ ++ for(u16_j=0; u16_j<0x10; u16_j++) ++ { ++ if( gDebugModeName[u16_j] == NULL ) ++ continue; ++ ++ REG_FCIE_CLRBIT(FCIE_EMMC_DEBUG_BUS1, BIT_DEBUG_MODE_MSK); ++ REG_FCIE_SETBIT(FCIE_EMMC_DEBUG_BUS1, u16_j<<8); ++ ++ if( u16_j == 5 ) ++ { ++ for(u16_i=1; u16_i<=4; u16_i++) ++ { ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, u16_i<=1000) ++ eMMC_debug(1, 0, "eMMC Err: FCIE reset fail!\n"); ++ } ++ ++ REG_FCIE_SETBIT(FCIE_RST, BIT_FCIE_SOFT_RST_n); ++ u16Cnt = 0; ++ while(1) ++ { ++ if((REG_FCIE(FCIE_RST)&BIT_RST_STS_MASK)==0) // reset success ++ break; ++ ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ ++ if(u16Cnt++>=1000) ++ eMMC_debug(1, 0, "eMMC Err: FCIE reset fail2!\n"); ++ } ++ ++ eMMC_clock_setting(u16_clk); ++ return 0; ++ ++ #if 0 ++ U16 u16Reg, u16Cnt; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_clk = g_eMMCDrv.u16_ClkRegVal; ++ ++ eMMC_clock_setting(gau8_FCIEClkSel[0]); // speed up FCIE reset done ++ REG_FCIE_CLRBIT(FCIE_MIE_FUNC_CTL, BIT_FUNC_MASK); ++ REG_FCIE_SETBIT(FCIE_MIE_FUNC_CTL, BIT_EMMC_EN); ++ eMMC_FCIE_CLK_DIS(); // do not output clock ++ ++ // FCIE reset - set ++ REG_FCIE_CLRBIT(FCIE_RST, BIT_FCIE_SOFT_RST_n); /* active low */ ++ REG_FCIE_CLRBIT(reg_emmcpll_0x6f, BIT1|BIT0); //macro reset ++ ++ // FCIE reset - wait ++ ++ u16Cnt=0; ++ do ++ { ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ if(0x1000 == u16Cnt++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: FCIE Reset fail: %Xh \n", eMMC_ST_ERR_FCIE_NO_CLK); ++ return eMMC_ST_ERR_FCIE_NO_CLK; ++ } ++ ++ REG_FCIE_R(FCIE_RST, u16Reg); ++ ++ }while (BIT_RST_STS_MASK != (u16Reg & BIT_RST_STS_MASK)); ++ ++ //[FIXME] is there any method to check that reseting FCIE is done? ++ ++ // FCIE reset - clear ++ REG_FCIE_SETBIT(FCIE_RST, BIT_FCIE_SOFT_RST_n); ++ REG_FCIE_SETBIT(reg_emmcpll_0x6f, BIT1|BIT0); ++ // FCIE reset - check ++ ++ u16Cnt=0; ++ do ++ { ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ if(0x1000 == u16Cnt++) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: FCIE Reset fail2: %Xh \n", eMMC_ST_ERR_FCIE_NO_CLK); ++ return eMMC_ST_ERR_FCIE_NO_CLK; ++ } ++ ++ REG_FCIE_R(FCIE_RST, u16Reg); ++ ++ }while (0 != (u16Reg & BIT_RST_STS_MASK)); ++ ++ eMMC_clock_setting(u16_clk); ++ return u32_err; ++ #endif ++} ++ ++ ++U32 eMMC_FCIE_Init(void) ++{ ++ U32 u32_err; ++ ++ // ------------------------------------------ ++ // setup function pointer to wait for events ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ if(NULL==sgpFn_eMMC_FCIE_WaitEvents_Ex) ++ sgpFn_eMMC_FCIE_WaitEvents_Ex = eMMC_WaitCompleteIntr; ++ #else ++ if(NULL==sgpFn_eMMC_FCIE_WaitEvents_Ex) ++ sgpFn_eMMC_FCIE_WaitEvents_Ex = eMMC_FCIE_PollingEvents; ++ #endif ++ ++ // ------------------------------------------ ++ eMMC_PlatformResetPre(); ++ ++ // ------------------------------------------ ++ #if eMMC_TEST_IN_DESIGN ++ { ++ volatile U16 u16_i, u16_reg; ++ // check timer clock ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Timer test, for 6 sec: "); ++ for(u16_i = 6; u16_i > 0; u16_i--) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "%u ", u16_i); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++ ++ // check FCIE reg.30h ++ REG_FCIE_R(FCIE_TEST_MODE, u16_reg); ++ if(0)//u16_reg & BIT_FCIE_BIST_FAIL) /* Andersen: "don't care." */ ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h BIST fail: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_BIST_FAIL; ++ } ++ if(u16_reg & BIT_FCIE_DEBUG_MODE_MASK) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: Reg0x30h Debug Mode: %04Xh \r\n", u16_reg); ++ return eMMC_ST_ERR_DEBUG_MODE; ++ } ++ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ } ++ #endif // eMMC_TEST_IN_DESIGN ++ ++ // ------------------------------------------ ++ u32_err = eMMC_FCIE_Reset(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: reset fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ ++ REG_FCIE_W(FCIE_MIE_INT_EN, 0); ++ REG_FCIE_W(FCIE_MIE_FUNC_CTL, BIT_SD_EN|BIT_EMMC_ACTIVE); ++ // all cmd are 5 bytes (excluding CRC) ++ REG_FCIE_CLRBIT(FCIE_CMD_RSP_SIZE, BIT_CMD_SIZE_MASK); ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, (eMMC_CMD_BYTE_CNT)<< BIT_CMD_SIZE_SHIFT); ++ REG_FCIE_W(FCIE_SD_CTRL, 0); ++ REG_FCIE_W(FCIE_SD_MODE, g_eMMCDrv.u16_Reg10_Mode); ++ // default sector size: 0x200 ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_RSP_SHIFT_CNT, 0); ++ REG_FCIE_W(FCIE_RX_SHIFT_CNT, 0); ++ //REG_FCIE_CLRBIT(FCIE_RX_SHIFT_CNT, BIT_RSTOP_SHIFT_SEL|BIT_RSTOP_SHIFT_TUNE_MASK); ++ ++ ++ eMMC_FCIE_ClearEvents(); ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; // ok ++} ++ ++ ++void eMMC_FCIE_ClearEvents(void) ++{ ++ volatile U16 u16_reg; ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++ REG_FCIE_W1C(FCIE_SD_STATUS, BIT_SD_FCIE_ERR_FLAGS); // W1C ++} ++ ++ ++void eMMC_FCIE_ClearEvents_Reg0(void) ++{ ++ volatile U16 u16_reg; ++ ++ while(1){ ++ REG_FCIE_W(FCIE_MIE_EVENT, BIT_ALL_CARD_INT_EVENTS); ++ REG_FCIE_R(FCIE_MIE_EVENT, u16_reg); ++ if(0==(u16_reg&BIT_ALL_CARD_INT_EVENTS)) ++ break; ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ REG_FCIE_W(FCIE_MIE_EVENT, 0); ++ } ++} ++ ++ ++U32 eMMC_FCIE_WaitD0High_Ex(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ volatile U16 u16_read0=0, u16_read1=0; ++ ++ for(u32_cnt=0; u32_cnt < u32_us; u32_cnt++) ++ { ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read0); ++ eMMC_hw_timer_delay(HW_TIMER_DELAY_1us); ++ REG_FCIE_R(FCIE_SD_STATUS, u16_read1); ++ ++ if((u16_read0&BIT_SD_CARD_BUSY) ==0 && (u16_read1&BIT_SD_CARD_BUSY) ==0) ++ break; ++ ++ if(u32_cnt > 500 && u32_us-u32_cnt > 1000) ++ { ++ eMMC_hw_timer_sleep(1); ++ u32_cnt += 1000-2; ++ } ++ } ++ ++ return u32_cnt; ++} ++ ++ ++U32 eMMC_FCIE_WaitD0High(U32 u32_us) ++{ ++ volatile U32 u32_cnt; ++ ++ REG_FCIE_SETBIT(FCIE_SD_MODE, BIT_CLK_EN); ++ ++ ++ u32_cnt = eMMC_FCIE_WaitD0High_Ex(u32_us); ++ ++ if(u32_us == u32_cnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: wait D0 H timeout %u us\n", u32_cnt); ++ return eMMC_ST_ERR_TIMEOUT_WAITD0HIGH; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_FCIE_SendCmd ++( ++ U16 u16_Mode, U16 u16_Ctrl, U32 u32_Arg, U8 u8_CmdIdx, U8 u8_RspByteCnt ++) ++{ ++ U32 u32_err, u32_Timeout = TIME_WAIT_DAT0_HIGH; ++ //U16 au16_tmp[3]; ++ ++ if(38 == u8_CmdIdx) ++ u32_Timeout = TIME_WAIT_ERASE_DAT0_HIGH; ++ ++ #if 0 ++ eMMC_debug(0,1,"\n"); ++ eMMC_debug(0,1,"cmd:%u, arg:%Xh, rspb:%Xh, mode:%Xh, ctrl:%Xh \n", ++ u8_CmdIdx, u32_Arg, u8_RspByteCnt, u16_Mode, u16_Ctrl); ++ #endif ++ ++ REG_FCIE_CLRBIT(FCIE_CMD_RSP_SIZE, BIT_RSP_SIZE_MASK); ++ ++ REG_FCIE_SETBIT(FCIE_CMD_RSP_SIZE, u8_RspByteCnt & BIT_RSP_SIZE_MASK); ++ ++ REG_FCIE_W(FCIE_SD_MODE, u16_Mode); ++ ++ // set cmd ++ // CMDFIFO(0) = 39:32 | 47:40 ++ // CMDFIFO(1) = 23:16 | 31:24 ++ // CMDFIFO(2) = (CIFC(2) & 0xFF00) | 15:8, ignore (CRC7 | end_bit). ++ ++ //check command FIFO for filled command value ++ //REG_FCIE_SETBIT(FCIE_SD_CTRL, BIT_CHK_CMD); ++ //while(1) ++ //{ ++// eMMC_debug(0, 1, "FIFO 0 = 0x%4X\n", ((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx)); ++// eMMC_debug(0, 1, "FIFO 1 = 0x%4X\n", (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++// eMMC_debug(0, 1, "FIFO 2 = 0x%4X\n", u32_Arg&0xFF); ++ REG_FCIE_W(FCIE_CMDFIFO_ADDR(0),((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx)); ++ REG_FCIE_W(FCIE_CMDFIFO_ADDR(1), (u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF)); ++ REG_FCIE_W(FCIE_CMDFIFO_ADDR(2), u32_Arg&0xFF); ++ ++ //REG_FCIE_R(FCIE_CMDFIFO_ADDR(0),au16_tmp[0]); ++ //REG_FCIE_R(FCIE_CMDFIFO_ADDR(1),au16_tmp[1]); ++ //REG_FCIE_R(FCIE_CMDFIFO_ADDR(2),au16_tmp[2]); ++ ++ //if(au16_tmp[0] == (((u32_Arg>>24)<<8) | (0x40|u8_CmdIdx))&& ++ // au16_tmp[1] == ((u32_Arg&0xFF00) | ((u32_Arg>>16)&0xFF))&& ++ // au16_tmp[2] == (u32_Arg&0xFF)) ++ // break; ++ //} ++ ++ //clear command check for reading response value ++ //REG_FCIE_CLRBIT(FCIE_SD_CTRL, BIT_CHK_CMD); ++ ++ if(12 != u8_CmdIdx) ++ { ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CMD_END); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, u16_Ctrl |BIT_JOB_START); ++ ++ #if 1//defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ // wait event ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CMD_END, HW_TIMER_DELAY_1s); ++ #endif ++ ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_RSP_WAIT_D0H){ ++ u32_err = eMMC_FCIE_WaitD0High(u32_Timeout); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEL_SEND_CMD_ERROR; ++ } ++ ++ LABEL_SEND_CMD_ERROR: ++ return u32_err; ++ ++} ++ ++ ++void eMMC_FCIE_GetCMDFIFO(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i= u32_MicroSec) ++ { ++ REG_FCIE_R(NC_CIFD_EVENT, u16_Reg); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "CIFD Event Timout %X\n", u16_Reg); ++ } ++ return u32_Count; ++} ++ ++U32 eMMC_WaitSetCIFD(U8 * pu8_DataBuf, U32 u32_ByteCnt) ++{ ++ U16 u16_i, *pu16_Data = (U16*)pu8_DataBuf; ++ ++ if(u32_ByteCnt > FCIE_CIFD_BYTE_CNT) ++ { ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ for(u16_i=0; u16_i<(u32_ByteCnt>>1); u16_i++) ++ REG_FCIE_W(NC_RBUF_CIFD_ADDR(u16_i), pu16_Data[u16_i]); ++ ++ REG_FCIE_SETBIT(NC_CIFD_EVENT, BIT_RBUF_FULL_TRI); ++ ++ if (eMMC_WaitCIFD_Event(BIT_RBUF_EMPTY, HW_TIMER_DELAY_500ms)== (HW_TIMER_DELAY_500ms )) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Error: CIFD timeout 0, ErrCode:%Xh\r\n", eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT); ++ return eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT; // timeout ++ } ++ ++ REG_FCIE_SETBIT(NC_CIFD_EVENT, BIT_RBUF_EMPTY); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++void eMMC_FCIE_GetCIFD(U16 u16_WordPos, U16 u16_WordCnt, U16 *pu16_Buf) ++{ ++ U16 u16_i; ++ ++ for(u16_i=0; u16_i FCIE_CIFD_BYTE_CNT) ++ { ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ if (eMMC_WaitCIFD_Event(BIT_WBUF_FULL, HW_TIMER_DELAY_500ms)== (HW_TIMER_DELAY_500ms )) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Error: CIFD timeout 0, ErrCode:%Xh\r\n", eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT); ++ return eMMC_ST_ERR_TIMEOUT_WAITCIFDEVENT; // timeout ++ } ++ ++ for(u16_i=0; u16_i<(u32_ByteCnt>>1); u16_i++) ++ REG_FCIE_R(NC_WBUF_CIFD_ADDR(u16_i), pu16_Data[u16_i]); ++ ++ REG_FCIE_W(NC_CIFD_EVENT,BIT_WBUF_FULL); ++ ++ REG_FCIE_W(NC_CIFD_EVENT, BIT_WBUF_EMPTY_TRI); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U8 eMMC_FCIE_CmdRspBufGet(U8 u8addr) ++{ ++ U16 u16Tmp; ++ ++ u16Tmp = REG_FCIE(FCIE_CMDFIFO_ADDR(u8addr>>1)); ++ ++ if(u8addr&0x1) ++ { ++ return ((u16Tmp>>8)&0xFF); ++ } ++ else ++ { ++ return (u16Tmp&0xFF); ++ } ++} ++ ++U8 eMMC_FCIE_DataFifoGet(U8 u8addr) ++{ ++ U16 u16Tmp; ++ ++ u16Tmp = REG_FCIE(FCIE_CIFD_ADDR(u8addr>>1)); ++ ++ if(u8addr&0x1) ++ return ((u16Tmp>>8)&0xFF); ++ else ++ return (u16Tmp&0xFF); ++} ++ ++//=================================================== ++#if defined(eMMC_RSP_FROM_RAM) && eMMC_RSP_FROM_RAM ++void eMMC_KeepRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ eMMC_die("\n"); // should be system fatal error, not eMMC driver ++ } ++ ++ memcpy(g_eMMCDrv.au8_AllRsp + u16_idx, pu8_OneRspBuf, u8_ByteCnt); ++ ++} ++ ++ ++U32 eMMC_ReturnRsp(U8 *pu8_OneRspBuf, U8 u8_CmdIdx) ++{ ++ U16 u16_idx; ++ U8 u8_ByteCnt; ++ ++ u16_idx = u8_CmdIdx * eMMC_CMD_BYTE_CNT; ++ u8_ByteCnt = eMMC_CMD_BYTE_CNT; ++ ++ if(u8_CmdIdx > 10) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*3; ++ else if(u8_CmdIdx > 9) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*2; ++ else if(u8_CmdIdx > 2) ++ u16_idx += (eMMC_R2_BYTE_CNT-eMMC_CMD_BYTE_CNT)*1; ++ ++ if(10==u8_CmdIdx || 9==u8_CmdIdx || 2==u8_CmdIdx) ++ u8_ByteCnt = eMMC_R2_BYTE_CNT; ++ ++ if(u16_idx+u8_ByteCnt > eMMC_SECTOR_512BYTE-4) // last 4 bytes are CRC ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: KeepRsp over 512B, %Xh, %Xh, %Xh\n", ++ u8_CmdIdx, u16_idx, u8_ByteCnt); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ if(0 == g_eMMCDrv.au8_AllRsp[u16_idx]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Info: no rsp, %u %u \n", u8_CmdIdx, u16_idx); ++ return eMMC_ST_ERR_NO_RSP_IN_RAM; ++ } ++ ++ memcpy(pu8_OneRspBuf, g_eMMCDrv.au8_AllRsp + u16_idx, u8_ByteCnt); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// ------------------------------- ++U32 eMMC_SaveRsp(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_SaveDriverContext(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_LoadRsp(U8 *pu8_AllRspBuf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_LoadDriverContext(U8 *pu8_Buf) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#endif ++//======================================================== ++// Send CMD HAL APIs ++//======================================================== ++U32 eMMC_Identify(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U16 u16_i, u16_retry=0; ++ ++ g_eMMCDrv.u16_RCA=1; ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ ++ LABEL_IDENTIFY_CMD0: ++ if(eMMC_ST_SUCCESS != eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: WaitD0High TO\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_RST_L(); eMMC_hw_timer_sleep(1); ++ eMMC_RST_H(); eMMC_hw_timer_sleep(1); ++ ++ if(u16_retry > 10) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++ } ++ if(u16_retry) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Warn: retry: %u\n", u16_retry); ++ ++ // CMD0 ++ u32_err = eMMC_CMD0(0); // reset to idle state ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u16_retry++; ++ goto LABEL_IDENTIFY_CMD0; ++ } ++ ++ // CMD1 ++ for(u16_i=0; u16_i>6; ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 1); ++ } ++ } ++ #else ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD1 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ // R3 has no CRC, so does not check BIT_SD_RSP_CRC_ERR ++ if(u16_reg & BIT_SD_RSP_TIMEOUT) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD1 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD1 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD1 ok, do things here ++ eMMC_FCIE_GetCIFC(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ //eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R3_BYTE_CNT); ++ ++ if(0 == (g_eMMCDrv.au8_Rsp[1] & 0x80)) ++ u32_err = eMMC_ST_ERR_CMD1_DEV_NOT_RDY; ++ else ++ g_eMMCDrv.u8_IfSectorMode = (g_eMMCDrv.au8_Rsp[1]&BIT6)>>6; ++ } ++ } ++ #endif ++ ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// send CID ++U32 eMMC_CMD2(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 2, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD2, %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD2; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD2 SD_STS: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD2 ok, do things here (get CID) ++ eMMC_FCIE_GetCMDFIFO(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CID); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CID, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CID, 2); ++ } ++ } ++ //eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++// CMD3: assign RCA. CMD7: select device ++U32 eMMC_CMD3_CMD7(U16 u16_RCA, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ if(7 == u8_CmdIdx) ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ else{ ++ u8_retry_fcie = 0xF0; // CMD3: not retry ++ } ++ ++ u32_arg = u16_RCA<<16; ++ ++ if(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA) ++ u16_ctrl = BIT_SD_CMD_EN; ++ else ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ return u32_err; ++ } ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD%u retry:%u, %Xh \n", ++ u8_CmdIdx, u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ // de-select has no rsp ++ if(!(7==u8_CmdIdx && u16_RCA!=g_eMMCDrv.u16_RCA)){ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u SD_STS: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ return u32_err; ++ } ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u SD_STS: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD3_CMD7; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u SD_STS: %04Xh, Retry: %u\n", u8_CmdIdx, u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(3 == u8_CmdIdx) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ return u32_err; ++ } ++ ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh, retry: %u\n", ++ u8_CmdIdx, u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ }} ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_CSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------ ++ g_eMMCDrv.u8_SPEC_VERS = (g_eMMCDrv.au8_CSD[1]&0x3C)>>2; ++ g_eMMCDrv.u8_R_BL_LEN = g_eMMCDrv.au8_CSD[6] & 0xF; ++ g_eMMCDrv.u8_W_BL_LEN = ((g_eMMCDrv.au8_CSD[13]&0x3)<<2)+ ++ ((g_eMMCDrv.au8_CSD[14]&0xC0)>>6); ++ ++ // ------------------------------ ++ g_eMMCDrv.u16_C_SIZE = (g_eMMCDrv.au8_CSD[7] & 3)<<10; ++ g_eMMCDrv.u16_C_SIZE += g_eMMCDrv.au8_CSD[8] << 2; ++ g_eMMCDrv.u16_C_SIZE +=(g_eMMCDrv.au8_CSD[9] & 0xC0) >> 6; ++ if(0xFFF == g_eMMCDrv.u16_C_SIZE) ++ { ++ g_eMMCDrv.u32_SEC_COUNT = 0; ++ } ++ else ++ { ++ g_eMMCDrv.u8_C_SIZE_MULT = ((g_eMMCDrv.au8_CSD[10]&3)<<1)+ ++ ((g_eMMCDrv.au8_CSD[11]&0x80)>>7); ++ ++ g_eMMCDrv.u32_SEC_COUNT = ++ (g_eMMCDrv.u16_C_SIZE+1)* ++ (1<<(g_eMMCDrv.u8_C_SIZE_MULT+2))* ++ ((1<>9) - 8; // -8: //Toshiba CMD18 access the last block report out of range error ++ } ++ // ------------------------------ ++ g_eMMCDrv.u8_ERASE_GRP_SIZE = (g_eMMCDrv.au8_CSD[10]&0x7C)>>2; ++ g_eMMCDrv.u8_ERASE_GRP_MULT = ((g_eMMCDrv.au8_CSD[10]&0x03)<<3)+ ++ ((g_eMMCDrv.au8_CSD[11]&0xE0)>>5); ++ g_eMMCDrv.u32_EraseUnitSize = (g_eMMCDrv.u8_ERASE_GRP_SIZE+1)* ++ (g_eMMCDrv.u8_ERASE_GRP_MULT+1); ++ // ------------------------------ ++ // others ++ g_eMMCDrv.u8_TAAC = g_eMMCDrv.au8_CSD[2]; ++ g_eMMCDrv.u8_NSAC = g_eMMCDrv.au8_CSD[3]; ++ g_eMMCDrv.u8_Tran_Speed = g_eMMCDrv.au8_CSD[4]; ++ g_eMMCDrv.u8_R2W_FACTOR = (g_eMMCDrv.au8_CSD[13]&0x1C)>>2; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// send CSD (in R2) ++U32 eMMC_CMD9(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_RCA<<16; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_RSPR2_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 9, eMMC_R2_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD9 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD9 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD9; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD9 SD_STS: %04Xh, Retry fail: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD2 ok, do things here ++ eMMC_FCIE_GetCMDFIFO(0, eMMC_R2_BYTE_CNT>>1, (U16*)g_eMMCDrv.au8_CSD); ++ //eMMC_dump_mem(g_eMMCDrv.au8_CSD, eMMC_R2_BYTE_CNT); ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_CSD, 9); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++//------------------------------------------------ ++U32 eMMC_ExtCSD_Config(void) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD8(gau8_eMMC_SectorBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ //eMMC_dump_mem(gau8_eMMC_SectorBuf, 0x200); ++ ++ //-------------------------------- ++ if(0 == g_eMMCDrv.u32_SEC_COUNT) ++ g_eMMCDrv.u32_SEC_COUNT = ((gau8_eMMC_SectorBuf[215]<<24)| ++ (gau8_eMMC_SectorBuf[214]<<16)| ++ (gau8_eMMC_SectorBuf[213]<< 8)| ++ (gau8_eMMC_SectorBuf[212])) - 8; //-8: Toshiba CMD18 access the last block report out of range error ++ ++ //------------------------------- ++ if(0 == g_eMMCDrv.u32_BOOT_SEC_COUNT) ++ g_eMMCDrv.u32_BOOT_SEC_COUNT = gau8_eMMC_SectorBuf[226] * 128 * 2; ++ ++ //-------------------------------- ++ if(!g_eMMCDrv.u8_BUS_WIDTH) { ++ g_eMMCDrv.u8_BUS_WIDTH = gau8_eMMC_SectorBuf[183]; ++ switch(g_eMMCDrv.u8_BUS_WIDTH) ++ { ++ case 0: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; break; ++ case 1: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; break; ++ case 2: g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; break; ++ default: eMMC_debug(0,1,"eMMC Err: eMMC BUS_WIDTH not support \n"); ++ while(1); ++ } ++ } ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[231]&BIT4) // TRIM ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_TRIM; ++ else ++ g_eMMCDrv.u32_eMMCFlag &= ~eMMC_FLAG_TRIM; ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[503]&BIT0) // HPI ++ { ++ if(gau8_eMMC_SectorBuf[503]&BIT1) ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD12; ++ else ++ g_eMMCDrv.u32_eMMCFlag |= eMMC_FLAG_HPI_CMD13; ++ }else ++ g_eMMCDrv.u32_eMMCFlag &= ~(eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13); ++ ++ //-------------------------------- ++ if(gau8_eMMC_SectorBuf[166]&BIT2) // Reliable Write ++ g_eMMCDrv.u16_ReliableWBlkCnt = BIT_SD_JOB_BLK_CNT_MASK; ++ else ++ { ++ #if 0 ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ #else ++ if((gau8_eMMC_SectorBuf[503]&BIT0) && 1==gau8_eMMC_SectorBuf[222]) ++ g_eMMCDrv.u16_ReliableWBlkCnt = 1; ++ else if(0==(gau8_eMMC_SectorBuf[503]&BIT0)) ++ g_eMMCDrv.u16_ReliableWBlkCnt = gau8_eMMC_SectorBuf[222]; ++ else ++ { ++ //eMMC_debug(0,1,"eMMC Warn: not support dynamic Reliable-W\n"); ++ g_eMMCDrv.u16_ReliableWBlkCnt = 0; // can not support Reliable Write ++ } ++ #endif ++ } ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ErasedMemContent = gau8_eMMC_SectorBuf[181]; ++ ++ //-------------------------------- ++ g_eMMCDrv.u8_ECSD184_Stroe_Support = gau8_eMMC_SectorBuf[184]; ++ g_eMMCDrv.u8_ECSD185_HsTiming = gau8_eMMC_SectorBuf[185]; ++ g_eMMCDrv.u8_ECSD192_Ver = gau8_eMMC_SectorBuf[192]; ++ g_eMMCDrv.u8_ECSD196_DevType = gau8_eMMC_SectorBuf[196]; ++ g_eMMCDrv.u8_ECSD197_DriverStrength = gau8_eMMC_SectorBuf[197]; ++ g_eMMCDrv.u8_ECSD248_CMD6TO = gau8_eMMC_SectorBuf[248]; ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO = gau8_eMMC_SectorBuf[247]; ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl = gau8_eMMC_SectorBuf[34]; ++ ++ //for GP Partition ++ g_eMMCDrv.u8_ECSD160_PartSupField = gau8_eMMC_SectorBuf[160]; ++ g_eMMCDrv.u8_ECSD224_HCEraseGRPSize= gau8_eMMC_SectorBuf[224]; ++ g_eMMCDrv.u8_ECSD221_HCWpGRPSize= gau8_eMMC_SectorBuf[221]; ++ ++ g_eMMCDrv.GP_Part[0].u32_PartSize = ((gau8_eMMC_SectorBuf[145] << 16) | ++ (gau8_eMMC_SectorBuf[144] << 8) | ++ (gau8_eMMC_SectorBuf[143])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[1].u32_PartSize = ((gau8_eMMC_SectorBuf[148] << 16) | ++ (gau8_eMMC_SectorBuf[147] << 8) | ++ (gau8_eMMC_SectorBuf[146])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[2].u32_PartSize = ((gau8_eMMC_SectorBuf[151] << 16) | ++ (gau8_eMMC_SectorBuf[150] << 8) | ++ (gau8_eMMC_SectorBuf[149])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ g_eMMCDrv.GP_Part[3].u32_PartSize = ((gau8_eMMC_SectorBuf[154] << 16) | ++ (gau8_eMMC_SectorBuf[153] << 8) | ++ (gau8_eMMC_SectorBuf[152])) * ++ (g_eMMCDrv.u8_ECSD224_HCEraseGRPSize * g_eMMCDrv.u8_ECSD221_HCWpGRPSize * 0x80000); ++ ++ //for Max Enhance Size ++ g_eMMCDrv.u8_ECSD157_MaxEnhSize_0= gau8_eMMC_SectorBuf[157]; ++ g_eMMCDrv.u8_ECSD158_MaxEnhSize_1= gau8_eMMC_SectorBuf[158]; ++ g_eMMCDrv.u8_ECSD159_MaxEnhSize_2= gau8_eMMC_SectorBuf[159]; ++ ++ g_eMMCDrv.u8_u8_ECSD155_PartSetComplete = gau8_eMMC_SectorBuf[155]; ++ g_eMMCDrv.u8_ECSD166_WrRelParam = gau8_eMMC_SectorBuf[166]; ++ ++ //-------------------------------- ++ // set HW RST ++ if(0 == gau8_eMMC_SectorBuf[162]) ++ { ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 162, BIT0); // RST_FUNC ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh, eMMC, set Ext_CSD[162]: %Xh fail\n", ++ u32_err, BIT0); ++ return u32_err; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_CMD8(U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD8_CIFD(pu8_DataBuf); ++ #else ++ return eMMC_CMD8_MIU(pu8_DataBuf); ++ #endif ++} ++ ++// CMD8: send EXT_CSD ++U32 eMMC_CMD8_MIU(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr; ++ dma_addr_t dma_DataMapAddr; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN |BIT_ERR_DET_ON; ++ ++ LABEL_SEND_CMD: ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ dma_DataMapAddr = eMMC_DMA_MAP_address((uintptr_t)pu8_DataBuf, eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(dma_DataMapAddr, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_DataDMAAddr >> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD8_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD8_CIFD(U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ volatile U16 u16_mode, u16_ctrl, u16_reg, u16_j, u16_Tmp; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0;; ++ ++// REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ // ------------------------------- ++ // send cmd ++ u32_arg = 0; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 8, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD8 CIFD retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ //read for data ++ for (u16_j=0; u16_j< (eMMC_SECTOR_512BYTE >> 6); u16_j++) ++ { // read data ++ u16_Tmp =( (eMMC_SECTOR_512BYTE - (u16_j << 6)) >= 0x40) ? ++ 0x40 : (eMMC_SECTOR_512BYTE - (u16_j << 6) ); ++ u32_err = eMMC_WaitGetCIFD((U8*)((uintptr_t)pu8_DataBuf + (u16_j << 6)), u16_Tmp); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD8_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD8 CIFD check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ //eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 8); ++ ++ // ------------------------------- ++ // CMD8 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_SetPwrOffNotification(U8 u8_SetECSD34) ++{ ++ U32 u32_err; ++ static U8 u8_OldECSD34=0; ++ ++ if(eMMC_PwrOffNotif_SHORT==u8_OldECSD34 || eMMC_PwrOffNotif_LONG==u8_OldECSD34) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: PwrOffNotif already set: %u, now: %u\n", ++ u8_OldECSD34, u8_SetECSD34); ++ return eMMC_ST_SUCCESS; ++ } ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 34, u8_SetECSD34); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_PwrOffNotif_MASK; ++ switch(u8_SetECSD34) ++ { ++ case eMMC_PwrOffNotif_OFF: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_OFF; break; ++ case eMMC_PwrOffNotif_ON: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_ON; break; ++ case eMMC_PwrOffNotif_SHORT: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_SHORT; break; ++ case eMMC_PwrOffNotif_LONG: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_PwrOffNotif_LONG; break; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_Sanitize(U8 u8_ECSD165) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 165, u8_ECSD165); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH<<2); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++#define BITS_MSK_DRIVER_STRENGTH 0xF0 ++#define BITS_MSK_TIMING 0x0F ++ ++U32 eMMC_SetBusSpeed(U8 u8_BusSpeed) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_TIMING; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8_BusSpeed; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_SPEED_MASK; ++ switch(u8_BusSpeed) ++ { ++ case eMMC_SPEED_HIGH: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ break; ++ case eMMC_SPEED_HS200: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS200; ++ break; ++ case eMMC_SPEED_HS400: ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HS400; ++ break; ++ default: ++ break; ++ } ++ ++ return u32_err; ++} ++ ++U32 eMMC_SetDrivingStrength(U8 u8Driving) ++{ ++ U32 u32_err; ++ ++ g_eMMCDrv.u8_ECSD185_HsTiming &= ~BITS_MSK_DRIVER_STRENGTH; ++ g_eMMCDrv.u8_ECSD185_HsTiming |= u8Driving<<4; ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 185, g_eMMCDrv.u8_ECSD185_HsTiming); // HS_TIMING, HS200 ++ if(eMMC_ST_SUCCESS != u32_err) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: fail: %Xh\n", u32_err); ++ return eMMC_ST_ERR_SET_DRV_STRENGTH; ++ } ++ return eMMC_ST_SUCCESS; ++} ++ ++// Use CMD6 to set ExtCSD[183] BUS_WIDTH ++U32 eMMC_SetBusWidth(U8 u8_BusWidth, U8 u8_IfDDR) ++{ ++ U8 u8_value; ++ U32 u32_err; ++ ++ // ------------------------------- ++ switch(u8_BusWidth) ++ { ++ case 1: u8_value=0; break; ++ case 4: u8_value=1; break; ++ case 8: u8_value=2; break; ++ default: return eMMC_ST_ERR_PARAMETER; ++ } ++ ++ if(u8_IfDDR) ++ { ++ u8_value |= BIT2; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_DDR_MODE; ++ } ++ else ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_DDR_MODE; ++ ++ if(u8_IfDDR == 2 && g_eMMCDrv.u8_ECSD184_Stroe_Support ) ++ { ++ eMMC_debug(0,1,"Enhance Strobe\n"); ++ u8_value |= BIT7; // Enhanced Storbe ++ } ++ ++ // ------------------------------- ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, 183, u8_value); // BUS_WIDTH ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // ------------------------------- ++ g_eMMCDrv.u16_Reg10_Mode &= ~BIT_SD_DATA_WIDTH_MASK; ++ switch(u8_BusWidth) ++ { ++ case 1: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_1; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_1; ++ break; ++ case 4: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_4; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_4; ++ break; ++ case 8: ++ g_eMMCDrv.u8_BUS_WIDTH = BIT_SD_DATA_WIDTH_8; ++ g_eMMCDrv.u16_Reg10_Mode |= BIT_SD_DATA_WIDTH_8; ++ break; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL,1,"set %u bus width\n", u8_BusWidth); ++ return u32_err; ++} ++ ++U32 eMMC_ModifyExtCSD(U8 u8_AccessMode, U8 u8_ByteIdx, U8 u8_Value) ++{ ++ U32 u32_arg, u32_err; ++ U8 u8_retry_prg = 0; ++ ++ u32_arg = ((u8_AccessMode&3)<<24) | (u8_ByteIdx<<16) | ++ (u8_Value<<8); ++ ++ u32_err = eMMC_CMD6(u32_arg); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: eMMC: %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ do { ++ if (u8_retry_prg > 5) ++ break; ++ ++ u32_err = eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ if ((eMMC_ST_ERR_R1_7_0 != u32_err) && (eMMC_ST_SUCCESS != u32_err)) { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Warn: %Xh \n", u32_err); ++ return u32_err; ++ } ++ else if (eMMC_ST_SUCCESS == u32_err) ++ break; ++ ++ u8_retry_prg++; ++ } while (eMMC_ST_ERR_R1_7_0 == u32_err); ++ ++ return u32_err; ++} ++ ++// SWITCH cmd ++U32 eMMC_CMD6(U32 u32_Arg) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_Arg; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 6, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD6 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD6; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD6 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 6); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_EraseCMDSeq(U32 u32_eMMCBlkAddr_start, U32 u32_eMMCBlkAddr_end) ++{ ++ U32 u32_err; ++ U8 u8_retry_cmd=0; ++ ++ LABEL_SEND_CMD: ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_start, 35); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD35_CMD36(u32_eMMCBlkAddr_end, 36); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ u32_err = eMMC_CMD38(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ goto LABEN_END; ++ ++ return eMMC_ST_SUCCESS; ++ ++ LABEN_END: ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD35_CMD36(U32 u32_eMMCBlkAddr, U8 u8_CmdIdx) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, u8_CmdIdx, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD%u fail, %Xh \n", ++ u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD%u SD_STS: %04Xh \n", u8_CmdIdx, u16_reg); ++ return eMMC_ST_ERR_CMD3536_ERR; ++ } ++ else ++ { // CMD3 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD%u check R1 error: %Xh\n", u8_CmdIdx, u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, u8_CmdIdx); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD38(void) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ if(g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_TRIM) ++ u32_arg = 0x1; ++ else ++ u32_arg = 0x0; ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 38, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD38 fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ else ++ { ++ // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ u32_err = eMMC_ST_ERR_CMD38_ERR; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 SD_STS: %04Xh\n", u16_reg); ++ return u32_err; ++ } ++ else ++ { // CMD38 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD38 check R1 error: %Xh\n", u32_err); ++ return u32_err; ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 38); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++U32 eMMC_Dump_eMMCStatus(void) ++{ ++ eMMC_CMD13(g_eMMCDrv.u16_RCA); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC St: %Xh %Xh %Xh %Xh \n", ++ g_eMMCDrv.au8_Rsp[1], g_eMMCDrv.au8_Rsp[2], g_eMMCDrv.au8_Rsp[3], g_eMMCDrv.au8_Rsp[4]); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++// CMD13: send Status ++U32 eMMC_CMD13(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_cmd=0;// ,u8_retry_r1=0; ++ ++ u32_arg = (u16_RCA<<16); // | ++ // ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD13)?1:0); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 13, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD13 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ #if 0 ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD13 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ #else ++ eMMC_debug(0, 1, ++ "eMMC: CMD13 check R1 error: %Xh, should not retry\n", u32_err); ++ #endif ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 13); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD16(U32 u32_BlkLength) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u32_BlkLength; ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 16, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD16 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD16; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD16 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD16 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 16); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++//------------------------------------------------ ++ ++U32 eMMC_CMD17(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD17_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD17_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++#if 0 ++static U32 u32_TestCnt=0; ++#define IF_TEST_RETRY(x) (0==++u32_TestCnt%x) ++#else ++#define IF_TEST_RETRY(x) (0)//==++u32_TestCnt%x) ++#endif ++ ++U32 eMMC_CMD17_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr; ++ dma_addr_t dma_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN |BIT_ERR_DET_ON; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ dma_DataMapAddr = eMMC_DMA_MAP_address((uintptr_t)pu8_DataBuf,eMMC_SECTOR_512BYTE,1); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(dma_DataMapAddr, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_DataDMAAddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_1_BLK_END); ++ ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(7) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ goto LABEL_SEND_CMD; ++ } ++ else ++ { u32_err = eMMC_ST_ERR_CMD17_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ LABEL_END: ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE,1); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD17_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++// REG_FCIE_W(FCIE_CIFD_WORD_CNT, 0); ++ ++ //if(0 == eMMC_IF_TUNING_TTABLE()) ++ // eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN | BIT_SD_DAT_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 17, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD17 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ for (u16_i=0; u16_i< (eMMC_SECTOR_512BYTE >> 6); u16_i++) ++ { // read data ++ u32_err = eMMC_WaitGetCIFD((U8*)((uintptr_t)pu8_DataBuf + (u16_i << 6)), 0x40); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ //read for data ++ for (u16_i=0; u16_i< (eMMC_SECTOR_512BYTE >> 6); u16_i++) ++ { // read data ++ u32_err = eMMC_WaitGetCIFD((U8*)((uintptr_t)pu8_DataBuf + (u16_i << 6)), 0x40); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(28) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(33) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD17_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD17 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // CMD17 ok, do things here ++ eMMC_FCIE_GetCIFD(0, eMMC_SECTOR_512BYTE>>1, (U16*)pu8_DataBuf); ++ ++ LABEL_END: ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ if(IF_TEST_RETRY(10) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD12 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(IF_TEST_RETRY(3) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check SD_STS: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD12; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check SD_STS: %Xh, %Xh, retry: %u\n", ++ u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ //eMMC_FCIE_ErrHandler_Retry(); ++ //goto LABEL_SEND_CMD; ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD12 check R1 error: %Xh, Retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 12); ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD12_NoCheck(U16 u16_RCA) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl; ++ ++ #if 1 ++ u32_arg = (u16_RCA<<16)| ++ ((g_eMMCDrv.u32_eMMCFlag & eMMC_FLAG_HPI_CMD12)?1:0); ++ #else ++ u32_arg = (u16_RCA<<16); ++ #endif ++ ++ #if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++ u32_arg = 0; ++ #endif ++ ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_RSP_WAIT_D0H; ++ ++ //LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 12, eMMC_R1b_BYTE_CNT); ++ ++ g_eMMCDrv.u32_DrvFlag &= ~DRV_FLAG_RSP_WAIT_D0H; ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD18(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ U32 u32_err; ++ ++ for(u16_cnt=0; u16_cnt> 16); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, (eMMC_SECTOR_512BYTE*u16_BlkCnt) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,( eMMC_SECTOR_512BYTE*u16_BlkCnt) >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd(u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(20) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD18 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check FCIE ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>11))); ++ ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || eMMC_ST_SUCCESS != u32_err || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD18 SD_STS: %04Xh, Err: %Xh, Retry: %u\n", u16_reg, u32_err, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(24) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(1, 1, "eMMC Err: CMD18 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr,eMMC_SECTOR_512BYTE*u16_BlkCnt,1); ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++// enable Reliable Write ++U32 eMMC_CMD23(U16 u16_BlkCnt) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_ctrl, u16_reg; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ u32_arg = u16_BlkCnt&0xFFFF; // don't set BIT24 ++ #if defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE ++ u32_arg |= BIT31; // don't set BIT24 ++ #endif ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, u32_arg, 23, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD23 retry:%u, %Xh \n", u8_retry_cmd, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // check status ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ ++ if(u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ ++ u32_err = eMMC_ST_ERR_CMD13; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 SD_STS: %04Xh, Retry: %u\n", u16_reg, u8_retry_fcie); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ else ++ { // CMD13 ok, do things here ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()){ ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD23 check R1 error: %Xh, retry: %u\n", u32_err, u8_retry_r1); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ eMMC_KEEP_RSP(g_eMMCDrv.au8_Rsp, 23); ++ ++ } ++ } ++ ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD25(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf, U16 u16_BlkCnt) ++{ ++ U32 u32_err=eMMC_ST_SUCCESS; ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ U16 u16_cnt; ++ #endif ++ ++ #if (defined(eMMC_BURST_LEN_AUTOCFG) && eMMC_BURST_LEN_AUTOCFG) || ENABLE_eMMC_RIU_MODE ++ U16 u16_RetryCnt=0; ++ LABEL_CMD25: ++ #endif ++ // ------------------------------RIU mode ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ for(u16_cnt=0; u16_cnt g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen ? ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen : u16_BlkCnt-u16_blk_pos; ++ u16_blk_cnt = u16_blk_cnt == g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen ? ++ u16_blk_cnt/2 : u16_blk_cnt; ++ ++ u32_err = eMMC_CMD25_MIU(u32_eMMCBlkAddr+u16_blk_pos, ++ pu8_DataBuf+(u16_blk_pos< u32_t1-u32_t0) ++ { ++ u32_tMin = u32_t1-u32_t0; ++ u16_BestBlkCnt = u16_BurstBlkCnt; ++ } ++ if(u32_tMax < u32_t1-u32_t0) ++ { ++ u32_tMax = u32_t1-u32_t0; ++ u16_WorstBlkCnt = u16_BurstBlkCnt; ++ } ++ ++ if(MAX_DETECT_BLK_CNT != u16_BurstBlkCnt) ++ goto LABEL_DETECT; ++ ++ // -------------------------- ++ g_eMMCDrv.BurstWriteLen_t.u16_BestBrustLen = u16_BestBlkCnt; ++ g_eMMCDrv.BurstWriteLen_t.u16_WorstBrustLen = u16_WorstBlkCnt; ++ ++ u32_tmp = (U32)(MAX_DETECT_BLK_CNT<> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, (eMMC_SECTOR_512BYTE*u16_BlkCnt) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, (eMMC_SECTOR_512BYTE*u16_BlkCnt) >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD25 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(13) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(1, 1, "eMMC WARN: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_n_BLK_END*(1+(u16_BlkCnt>>9))); ++ ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(43) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD25 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ #if 1 //!(defined(eMMC_FEATURE_RELIABLE_WRITE) && eMMC_FEATURE_RELIABLE_WRITE) ++ if(eMMC_ST_SUCCESS != eMMC_CMD12(g_eMMCDrv.u16_RCA)) ++ eMMC_CMD12_NoCheck(g_eMMCDrv.u16_RCA); ++ #endif ++ ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE*u16_BlkCnt,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++ ++U32 eMMC_CMD24(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ #if defined(ENABLE_eMMC_RIU_MODE)&&ENABLE_eMMC_RIU_MODE ++ return eMMC_CMD24_CIFD(u32_eMMCBlkAddr, pu8_DataBuf); ++ #else ++ return eMMC_CMD24_MIU(u32_eMMCBlkAddr, pu8_DataBuf); ++ #endif ++} ++ ++U32 eMMC_CMD24_MIU(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg; ++ U8 u8_retry_fcie=0, u8_retry_r1=0, u8_retry_cmd=0; ++ U32 u32_DataDMAAddr; ++ dma_addr_t dma_DataMapAddr; ++ ++ // ------------------------------- ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ dma_DataMapAddr = eMMC_DMA_MAP_address((uintptr_t)pu8_DataBuf, eMMC_SECTOR_512BYTE,0); ++ u32_DataDMAAddr = eMMC_translate_DMA_address_Ex(dma_DataMapAddr, eMMC_SECTOR_512BYTE); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_15_0, u32_DataDMAAddr & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_ADDR_31_16, u32_DataDMAAddr >> 16); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, (eMMC_SECTOR_512BYTE) & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16,( eMMC_SECTOR_512BYTE) >> 16); ++ REG_FCIE_W(FCIE_BLK_SIZE, eMMC_SECTOR_512BYTE); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(25) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(34) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(31) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 check R1 error: %Xh, Retry: %u, Arg: %Xh\n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_MIU_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ #endif ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START|BIT_ERR_DET_ON); ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ (BIT_DMA_END|BIT_ERR_STS), TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(11) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Warn: CMD24 %s SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_MIU; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 %s SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", ++ (eMMC_ST_SUCCESS!=u32_err)?"TO ":"", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ eMMC_DMA_UNMAP_address(dma_DataMapAddr, eMMC_SECTOR_512BYTE,0); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_CMD24_CIFD(U32 u32_eMMCBlkAddr, U8 *pu8_DataBuf) ++{ ++ U32 u32_err, u32_arg; ++ U16 u16_mode, u16_ctrl, u16_reg, u16_i; ++ U8 u8_retry_r1=0, u8_retry_fcie=0, u8_retry_cmd=0; ++ ++ // ------------------------------- ++ #if 0 ++ if(0 == eMMC_IF_TUNING_TTABLE()) ++ eMMC_FCIE_ErrHandler_RestoreClk(); ++ #endif ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ LABEL_SEND_CMD: ++ u32_arg = u32_eMMCBlkAddr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ u16_mode = BIT_SD_DATA_CIFD | g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ eMMC_FCIE_ClearEvents(); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, 1); ++ ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_15_0, eMMC_SECTOR_512BYTE & 0xFFFF); ++ REG_FCIE_W(FCIE_MIU_DMA_LEN_31_16, eMMC_SECTOR_512BYTE >> 16); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 24, eMMC_R1_BYTE_CNT); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cmd < eMMC_FCIE_CMD_RSP_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_cmd++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC WARN: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD24 CIFD retry:%u, %Xh, Arg: %Xh \n", u8_retry_cmd, u32_err, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(19) || (u16_reg & (BIT_SD_RSP_TIMEOUT|BIT_SD_RSP_CRC_ERR)) ) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ u32_err = eMMC_CheckR1Error(); ++ if(IF_TEST_RETRY(17) || eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_r1 < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_r1++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD check R1 error: %Xh, Retry: %u, Arg: %Xh \n", u32_err, u8_retry_r1, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // send data ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ u32_err = eMMC_ST_ERR_CMD24_CIFD_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W|BIT_JOB_START); ++ ++ for (u16_i=0; u16_i< (eMMC_SECTOR_512BYTE >> 6); u16_i++) ++ { ++ u32_err = eMMC_WaitSetCIFD( (U8*)( (uintptr_t) pu8_DataBuf + (u16_i << 6)), 0x40); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_DMA_END, TIME_WAIT_1_BLK_END); ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if(IF_TEST_RETRY(23) || eMMC_ST_SUCCESS != u32_err || (u16_reg & (BIT_SD_W_FAIL|BIT_SD_W_CRC_ERR))) ++ { ++ if(u8_retry_fcie < eMMC_CMD_API_ERR_RETRY_CNT && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ u8_retry_fcie++; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC WARN: CMD24 TO SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_SEND_CMD; ++ } ++ u32_err = eMMC_ST_ERR_CMD24_CIFD; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: CMD24 CIFD SD_STS: %04Xh, Err: %Xh, Retry: %u, Arg: %Xh\n", u16_reg, u32_err, u8_retry_fcie, u32_arg); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(u8_retry_fcie) ++ eMMC_debug(0,1,"eMMC Info: retry ok\n"); ++ eMMC_FCIE_CLK_DIS(); ++ return u32_err; ++} ++ ++U32 eMMC_GetR1(void) ++{ ++ return (g_eMMCDrv.au8_Rsp[1]<<24) | (g_eMMCDrv.au8_Rsp[2]<<16) ++ | (g_eMMCDrv.au8_Rsp[3]<<8) | g_eMMCDrv.au8_Rsp[4]; ++} ++ ++U32 eMMC_CheckR1Error(void) ++{ ++ U32 u32_err = eMMC_ST_SUCCESS; ++ ++ eMMC_FCIE_GetCMDFIFO(0, 3, (U16*)g_eMMCDrv.au8_Rsp); ++ ++ if(g_eMMCDrv.au8_Rsp[1] & (eMMC_ERR_R1_31_24>>24)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_31_24 \n "); ++ u32_err = eMMC_ST_ERR_R1_31_24; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[2] & (eMMC_ERR_R1_23_16>>16)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_23_16 \n "); ++ u32_err = eMMC_ST_ERR_R1_23_16; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[3] & (eMMC_ERR_R1_15_8>>8)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_15_8 \n "); ++ u32_err = eMMC_ST_ERR_R1_15_8; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++ if(g_eMMCDrv.au8_Rsp[4] & (eMMC_ERR_R1_7_0>>0)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: eMMC_ST_ERR_R1_7_0 \n "); ++ u32_err = eMMC_ST_ERR_R1_7_0; ++ goto LABEL_CHECK_R1_END; ++ } ++ ++LABEL_CHECK_R1_END: ++ ++ /*u8_cs = (eMMC_FCIE_CmdRspBufGet(3) & (eMMC_R1_CURRENT_STATE>>8))>>1; ++ eMMC_debug(0,0,"card state: %d ", u8_cs); ++ switch(u8_cs) { ++ case 0: eMMC_debug(0,0,"(idle)\n"); break; ++ case 1: eMMC_debug(0,0,"(ready)\n"); break; ++ case 2: eMMC_debug(0,0,"(ident)\n"); break; ++ case 3: eMMC_debug(0,0,"(stby)\n"); break; ++ case 4: eMMC_debug(0,0,"(tran)\n"); break; ++ case 5: eMMC_debug(0,0,"(data)\n"); break; ++ case 6: eMMC_debug(0,0,"(rcv)\n"); break; ++ case 7: eMMC_debug(0,0,"(prg)\n"); break; ++ case 8: eMMC_debug(0,0,"(dis)\n"); break; ++ default: eMMC_debug(0,0,"(?)\n"); break; ++ }*/ ++ ++ if(eMMC_ST_SUCCESS != u32_err)// && 0==eMMC_IF_TUNING_TTABLE()) ++ { ++ eMMC_dump_mem(g_eMMCDrv.au8_Rsp, eMMC_R1_BYTE_CNT); ++ } ++ return u32_err; ++} ++ ++ ++// ==================================================== ++#if defined(eMMC_UPDATE_FIRMWARE) && (eMMC_UPDATE_FIRMWARE) ++#define UPFW_SEC_WIAT_CNT 0x1000000 ++#define UPFW_SEC_BYTE_CNT (128*1024) ++static U32 eMMC_UpFW_Samsung_Wait(void) ++{ ++ U32 u32_err, u32_cnt, u32_st; ++ ++ for(u32_cnt=0; u32_cnt>eMMC_SECTOR_512BYTE_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: write fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 3, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ // --------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"close ... \n"); ++ u16_ctrl = BIT_SD_CMD_EN | BIT_SD_RSP_EN; ++ ++ eMMC_FCIE_ClearEvents(); ++ u32_err = eMMC_FCIE_SendCmd( ++ g_eMMCDrv.u16_Reg10_Mode, u16_ctrl, 0, 28, eMMC_R1b_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD28 fail, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ u32_err = eMMC_UpFW_Samsung_Wait(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: timeout 4, %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END_OF_UPFW; ++ } ++ ++ LABEL_END_OF_UPFW: ++ return u32_err; ++ ++} ++#endif // eMMC_UPDATE_FIRMWARE ++ ++#endif // UNIFIED_eMMC_DRIVER ++ +diff --git a/drivers/mstar/emmc/unify_driver/src/common/eMMC_ip_verify.c b/drivers/mstar/emmc/unify_driver/src/common/eMMC_ip_verify.c +new file mode 100644 +index 00000000..8dfc6652 +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/src/common/eMMC_ip_verify.c +@@ -0,0 +1,2297 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined (UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++#define DDR_TEST_BLK_CNT 8 ++#define DDR_TEST_BUFFER_SIZE (eMMC_SECTOR_512BYTE*DDR_TEST_BLK_CNT) ++ ++eMMC_ALIGN0 static U8 gau8_WBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++eMMC_ALIGN0 static U8 gau8_RBuf_DDR[DDR_TEST_BUFFER_SIZE] eMMC_ALIGN1; ++ ++U32 eMMCTest_BlkWRC_ProbeTiming(U32 u32_eMMC_Addr) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf_DDR, *pu32_R=(U32*)gau8_RBuf_DDR; ++ U32 u32_BlkCnt=eMMC_TEST_BLK_CNT, u32_BufByteCnt; ++ ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ u32_BufByteCnt = u32_BlkCnt << eMMC_SECTOR_512BYTE_BITS; ++ ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_R[u32_i] = 0; ++ ++ for(u32_j=0; u32_j<9; u32_j++) ++ { ++ // init data pattern ++ switch(u32_j) ++ { ++ case 0: // increase ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = u32_i+1; ++ break; ++ #else ++ continue; ++ #endif ++ case 1: // decrease ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i] = 0-(u32_i+1); // more FF, more chance to lose start bit ++ break; ++ #else ++ continue; ++ #endif ++ case 2: // 0xF00F ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xF00FF00F; ++ break; ++ case 3: // 0xFF00 ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFF00FF00; ++ break; ++ #else ++ continue; ++ #endif ++ case 4: // 0x5AA5 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5AA55AA5; ++ break; ++ case 5: // 0x55AA ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x55AA55AA; ++ break; ++ #else ++ continue; ++ #endif ++ case 6: // 0x5A5A ++ #if 0 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x5A5A5A5A; ++ break; ++ #else ++ continue; ++ #endif ++ case 7: // 0x0000 ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0x00000000; ++ break; ++ #else ++ continue; ++ #endif ++ case 8: // 0xFFFF ++ #if 1 ++ for(u32_i=0; u32_i>2; u32_i++) ++ pu32_W[u32_i]=0xFFFFFFFF; ++ break; ++ #else ++ continue; ++ #endif ++ } ++ ++ #if 1 ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, gau8_WBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, gau8_RBuf_DDR); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, eMMC_SECTOR_512BYTE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.single, %Xh \n", u32_err); ++ break; ++ } ++ #endif ++ u32_err = eMMC_CMD25_MIU(u32_eMMC_Addr, gau8_WBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_CMD18_MIU(u32_eMMC_Addr, gau8_RBuf_DDR, u32_BlkCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ break; ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf_DDR, gau8_RBuf_DDR, u32_BufByteCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, compare fail.multi %Xh \n", u32_err); ++ break; ++ } ++ } ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ //eMMC_debug(0,0,"%s() fail %Xh\n", __FUNCTION__, u32_err); ++ //eMMC_FCIE_ErrHandler_ReInit(); ++ eMMC_debug(1,1,"data pattern %u: %02X%02X%02X%02Xh \n\n", ++ u32_j, gau8_WBuf_DDR[3], gau8_WBuf_DDR[2], gau8_WBuf_DDR[1], gau8_WBuf_DDR[0]); ++ } ++ //eMMC_debug(0,0,"%s() return %Xh\n", __FUNCTION__, u32_err); ++ return u32_err; ++} ++ ++ ++//============================================================= ++#if defined(IF_DETECT_eMMC_DDR_TIMING) && IF_DETECT_eMMC_DDR_TIMING ++ ++ ++// can use for RF team test ++#ifndef IP_FCIE_VERSION_5 ++U32 eMMCTest_KeepR_TestDDR(U32 u32_LoopCnt) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, u32_k; ++ U32 u32_BlkCnt, u32_eMMC_Addr; ++ ++ u32_eMMC_Addr = eMMC_TEST_BLK_0; ++ ++ u32_BlkCnt = eMMC_TEST_BLK_CNT; ++ u32_BlkCnt = u32_BlkCnt > DDR_TEST_BLK_CNT ? DDR_TEST_BLK_CNT : u32_BlkCnt; ++ ++ if(8 != u32_BlkCnt) ++ { ++ eMMC_debug(0,1,"Blk count needs to be 8 \n"); ++ while(1); ++ } ++ ++ for(u32_j=0; u32_j>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u32_err = eMMC_CMD24_CIFD(u32_eMMC_Addr, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_CIFD(u32_eMMC_Addr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, FCIE_CIFD_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++extern U32 gu32_DMAAddr; ++U32 eMMCTest_SingleBlkWRC_MIU(U32 u32_eMMC_Addr, U32 u32_DataPattern) ++{ ++ volatile U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ return eMMCTest_SingleBlkWRC_MIU_Ex(u32_eMMC_Addr, (U8*)pu32_W, (U8*)pu32_R); ++} ++ ++ ++U32 eMMCTest_SingleBlkWRC_MIU_Ex(U32 u32_eMMC_Addr, U8 *pu8_W, U8 *pu8_R) ++{ ++ U32 u32_err; ++ ++ u32_err = eMMC_CMD24_MIU(u32_eMMC_Addr, pu8_W); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC W, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_CMD17_MIU(u32_eMMC_Addr, pu8_R); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC R, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ u32_err = eMMC_ComapreData(pu8_W, pu8_R, eMMC_SECTOR_BYTECNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, SingleBlkWRC C, %Xh \n", u32_err); ++ return u32_err; ++ } ++ ++ return u32_err; ++} ++ ++ ++#define eMMC_RETRY_CNT 10 ++ ++U32 eMMCTest_SgW_MIU(U32 u32_eMMC_Addr) ++{ ++ U16 u16_mode, u16_ctrl=0, u16_reg; ++ U32 u32_dmaaddr,u32_dma_addr,u32_dmalen,u32_arg; ++ U32 u32_err,u32_err_12=eMMC_ST_SUCCESS,u32_i; ++ U8 u8_retry_cnt=0; ++ ++ LABEL_RETRY: ++ eMMC_FCIE_ClearEvents(); ++ // ------------------------------- ++ // send cmd ++ u16_ctrl = (BIT_SD_CMD_EN | BIT_SD_RSP_EN); ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ ++ // ------------------------------- ++ ++ u32_arg = u32_eMMC_Addr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 25, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: CMD fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: R1 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_CHK_R1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: R1 fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_W : TOGGLE_CNT_256_CLK_W); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ } ++ ++ for(u32_i=0; u32_i< MAX_SCATTERLIST_COUNT; u32_i++) ++ { ++ u32_dmaaddr = pSG_st[u32_i].u32_dma_address; ++ u32_dmalen = pSG_st[u32_i].u32_length; ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(u32_dmaaddr, u32_dmalen); ++ ++ eMMC_FCIE_ClearEvents_Reg0(); ++ u32_err = eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Wait D0 H TO: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD25_WAIT_D0H; ++ goto LABEL_END; ++ } ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ ++ REG_FCIE_SETBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ if(u32_i ==0) ++ { ++ u32_err = eMMC_FCIE_FifoClkRdy(BIT_DMA_DIR_W); ++ ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: FifoClkRdy fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: FifoClkRdy fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN|BIT_SD_DAT_DIR_W); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_CARD_DMA_END); ++ #endif ++ //u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END|BIT_MIU_LAST_DONE, eMMC_GENERIC_WAIT_TIME); ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_CARD_DMA_END, eMMC_GENERIC_WAIT_TIME); ++ if(u32_err!= eMMC_ST_SUCCESS) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: event TO: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: event TO \n"); ++ //eMMC_die("\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ break; ++ } ++ //eMMC_hw_timer_delay(1000000); ++ } ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((u16_reg & BIT_SD_FCIE_ERR_FLAGS)||(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Reg.12h: %Xh fail: %Xh \n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD25; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, ++ "eMMC Err: Reg.12h: %04Xh, Err: %Xh\n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err_12 && u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD12 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++U32 eMMCTest_SgR_MIU(U32 u32_eMMC_Addr) ++{ ++ U16 u16_mode, u16_ctrl=0, u16_reg; ++ U32 u32_dmaaddr,u32_dma_addr,u32_dmalen,u32_arg; ++ U32 u32_err,u32_err_12=eMMC_ST_SUCCESS,u32_i; ++ U8 u8_retry_cnt=0; ++ ++ LABEL_RETRY: ++ eMMC_FCIE_ClearEvents(); ++ ++ u16_ctrl = BIT_SD_DAT_EN; ++ u16_mode = g_eMMCDrv.u16_Reg10_Mode | g_eMMCDrv.u8_BUS_WIDTH; ++ u16_mode |= BIT_SD_DMA_R_CLK_STOP; ++ ++ REG_FCIE_W(FCIE_SD_MODE, u16_mode); ++ ++ if(g_eMMCDrv.u32_DrvFlag & (DRV_FLAG_DDR_MODE|DRV_FLAG_SPEED_HS200) ) ++ { ++ REG_FCIE_W(FCIE_TOGGLE_CNT, (g_eMMCDrv.u32_DrvFlag&DRV_FLAG_SPEED_HS200) ? TOGGLE_CNT_512_CLK_R : TOGGLE_CNT_256_CLK_R); ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ eMMC_hw_timer_delay(TIME_WAIT_FCIE_RST_TOGGLE_CNT); // Brian needs 2T ++ REG_FCIE_CLRBIT(FCIE_MACRO_REDNT, BIT_TOGGLE_CNT_RST); ++ } ++ ++ u32_dmaaddr = pSG_st[0].u32_dma_address; ++ u32_dmalen = pSG_st[0].u32_length; ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(u32_dmaaddr, u32_dmalen); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen>>eMMC_SECTOR_512BYTE_BITS); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_DMA_DIR_W); ++ ++ u32_err = eMMC_FCIE_FifoClkRdy(0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: FifoClkRdy fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: FifoClkRdy fail\n"); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ ++ // ------------------------------- ++ // send cmd ++ u16_ctrl |= (BIT_SD_CMD_EN | BIT_SD_RSP_EN); ++ ++ // ------------------------------- ++ u32_arg = u32_eMMC_Addr << (g_eMMCDrv.u8_IfSectorMode?0:eMMC_SECTOR_512BYTE_BITS); ++ ++ u32_err = eMMC_FCIE_SendCmd( ++ u16_mode, u16_ctrl, u32_arg, 18, eMMC_R1_BYTE_CNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "eMMC Err: CMD fail %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ else ++ { ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, ++ BIT_MIU_LAST_DONE, eMMC_GENERIC_WAIT_TIME); ++ if(u32_err!= eMMC_ST_SUCCESS) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: event TO.0: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: event TO.0 \n"); ++ //eMMC_die("\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ return u32_err; ++ } ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((eMMC_ST_SUCCESS != u32_err) || (u16_reg & BIT_SD_FCIE_ERR_FLAGS)) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Reg.12h: %Xh fail: %Xh \n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, ++ "eMMC Err: Reg.12h: %Xh fail: %Xh\n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ for(u32_i=1; u32_i< MAX_SCATTERLIST_COUNT; u32_i++) ++ { ++ eMMC_FCIE_ClearEvents_Reg0(); ++ ++ u32_dmaaddr = pSG_st[u32_i].u32_dma_address; ++ u32_dmalen = pSG_st[u32_i].u32_length; ++ u32_dma_addr = eMMC_translate_DMA_address_Ex(u32_dmaaddr, u32_dmalen); ++ ++ REG_FCIE_W(FCIE_JOB_BL_CNT, u32_dmalen>>9); ++ REG_FCIE_W(FCIE_SDIO_ADDR0, u32_dma_addr & 0xFFFF); ++ REG_FCIE_W(FCIE_SDIO_ADDR1, u32_dma_addr >> 16); ++ REG_FCIE_SETBIT(FCIE_PATH_CTRL, BIT_MMA_EN); ++ REG_FCIE_W(FCIE_SD_CTRL, BIT_SD_DAT_EN); ++ #if defined(ENABLE_eMMC_INTERRUPT_MODE) && ENABLE_eMMC_INTERRUPT_MODE ++ REG_FCIE_W(FCIE_MIE_INT_EN, BIT_MIU_LAST_DONE); ++ #endif ++ u32_err = eMMC_FCIE_WaitEvents(FCIE_MIE_EVENT, BIT_MIU_LAST_DONE, TIME_WAIT_n_BLK_END*(1+(u32_dmalen>>24))); ++ if(u32_err!= eMMC_ST_SUCCESS) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: event TO.1: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: event TO.1 \n"); ++ //eMMC_die("\n"); ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_ERROR_RETRY; ++ break; ++ } ++ } ++ } ++ ++ REG_FCIE_R(FCIE_SD_STATUS, u16_reg); ++ if((u16_reg & BIT_SD_FCIE_ERR_FLAGS)||(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_ERROR_RETRY)) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: Reg.12h: %Xh fail: %Xh \n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: Reg.12h: %Xh fail: %Xh\n", u16_reg, u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ // ------------------------------- ++ // check device ++ u32_err = eMMC_CheckR1Error(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ if(u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: R1 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ u32_err = eMMC_ST_ERR_CMD18; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, ++ "eMMC Err: R1 fail: %Xh\n", u32_err); ++ eMMC_FCIE_ErrHandler_Stop(); ++ goto LABEL_END; ++ } ++ ++ LABEL_END: ++ if(g_eMMCDrv.u32_DrvFlag & DRV_FLAG_DDR_MODE) ++ REG_FCIE_SETBIT(FCIE_MACRO_REDNT, BIT_MACRO_DIR); ++ ++ u32_err_12 = eMMC_CMD12(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err_12 && u8_retry_cnt++ < eMMC_RETRY_CNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "eMMC Warn: CMD12 fail: %Xh \n", u32_err); ++ eMMC_FCIE_ErrHandler_ReInit(); eMMC_FCIE_ErrHandler_Retry(); ++ goto LABEL_RETRY; ++ } ++ ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_SD_CLK_EN); ++ return u32_err ? u32_err : u32_err_12; ++} ++ ++ ++U32 eMMCTest_SgWRC_MIU(U32 u32_eMMC_Addr, U16 u16_BlkCnt, U32 u32_DataPattern) ++{ ++ U32 u32_err; ++ U32 u32_i, u32_j, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf; ++ U32 u32_temp, u32_sg_blocks; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ //check scatterlist count ++ if(u16_BlkCnt % MAX_SCATTERLIST_COUNT) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"eMMC Err: Scatterlist Count Error\n"); ++ return eMMC_ST_ERR_NOT_ALIGN; ++ } ++ ++ u32_sg_blocks = u16_BlkCnt/MAX_SCATTERLIST_COUNT; ++ u32_temp =0; ++ //setting scatterlist dma address and dma length for write multiple block ++ for(u32_i=0; u32_i< MAX_SCATTERLIST_COUNT/4; u32_i++) ++ { ++ for(u32_j=0; u32_j< 4; u32_j++) // 4 groups ++ { ++ pSG_st[u32_i*4+u32_j].u32_dma_address = (U32)(gau8_WBuf+ u32_temp); ++ if(u32_j < 3) // first 3 have 1 block ++ { ++ pSG_st[u32_i*4+u32_j].u32_length = eMMC_SECTOR_512BYTE; ++ u32_temp += eMMC_SECTOR_512BYTE; ++ } ++ else ++ { ++ pSG_st[u32_i*4+u32_j].u32_length = (4*u32_sg_blocks-3)<>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ u16_BlkCnt_tmp = TEST_BUFFER_SIZE >> eMMC_SECTOR_512BYTE_BITS; ++ u16_BlkCnt_tmp = u16_BlkCnt_tmp > u16_BlkCnt ? u16_BlkCnt : u16_BlkCnt_tmp; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS; ++ #if IF_eMMC_BOOT_MODE_STG2 ++ au32_Addr[1] = (U32)gau8_BootImage1; ++ au32_SectorCnt[1] = sizeof(gau8_BootImage1)>>eMMC_SECTOR_512BYTE_BITS; ++ au32_Addr[2] = (U32)gau8_BootImage2; ++ au32_SectorCnt[2] = sizeof(gau8_BootImage2)>>eMMC_SECTOR_512BYTE_BITS; ++ #endif ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 1); ++ #else ++ u32_err = eMMC_LoadImages(au32_Addr, au32_SectorCnt, 3); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, eMMC_LoadImages: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ #if 0 == IF_eMMC_BOOT_MODE_STG2 ++ //eMMC_debug(0,1,"ChkSum -: %Xh \n", eMMC_ChkSum((U8*)au32_Addr, sizeof(gau8_BootImageOri))); ++ eMMC_debug(0,1,"ChkSum -: %Xh, Addr: %Xh \n", eMMC_ChkSum((U8*)au32_Addr[0], 0xC1< u32_t1) ++ while(0==(u32_t0-eMMC_hw_timer_tick())/eMMC_HW_TIMER_HZ) ++ ; ++ else ++ while(0==(eMMC_hw_timer_tick()-u32_t0)/eMMC_HW_TIMER_HZ) ++ ; ++ #endif ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,".\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"%u %u %u %u %u %u \n", ++ // au32_tmp[0], au32_tmp[1], au32_tmp[2], au32_tmp[3], au32_tmp[4], au32_tmp[5]); ++} ++ ++U32 eMMC_IPVerify_Performance(void) ++{ ++ volatile U32 u32_err, u32_i, u32_SectorAddr=0, u32_SectorCnt=0, u32_t0, u32_t1, u32_t; ++ U8 u8_LoopCnt=0; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"SectorBuf:%Xh, RBuf:%Xh, WBuf:%Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMCTest_DownCount(eMMC_SPEED_TEST_COUNTDOWN); ++ for(u32_i=0; u32_i>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_W, 1<>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_W; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ //eMMC_debug(0,0,"%08Xh \n", u32_SectorAddr+u32_i); ++ #if eMMC_FEATURE_RELIABLE_WRITE ++ u32_err = eMMC_CMD24(u32_SectorAddr, gau8_WBuf); ++ #else ++ u32_err = eMMC_CMD24_MIU(u32_SectorAddr, gau8_WBuf); ++ #endif ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/1000); // ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u KB/s \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_W<>10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Single Read, total: %u KB, %u blocks, burst size: %Xh\n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R)<>10, ++ eMMC_SPEED_TEST_SINGLE_BLKCNT_R, 1<>2) + 333*u32_i; ++ u32_SectorAddr %= g_eMMCDrv.u32_SEC_COUNT; ++ if(u32_SectorAddr < g_eMMCDrv.u32_SEC_COUNT>>1) ++ u32_SectorAddr += g_eMMCDrv.u32_SEC_COUNT>>1; ++ u32_SectorAddr -= eMMC_SPEED_TEST_SINGLE_BLKCNT_R; ++ u32_SectorAddr = eMMC_TEST_BLK_0+(u32_SectorAddr%eMMC_TEST_BLK_CNT); ++ ++ u32_err = eMMC_CMD17_MIU(u32_SectorAddr, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: %Xh \n", u32_err); ++ return u32_err; ++ } ++ } ++ eMMC_FCIE_WaitD0High(TIME_WAIT_DAT0_HIGH); ++ u32_t1 = eMMC_hw_timer_tick(); ++ u32_t = u32_t1 > u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/1000); // ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u KB/s \n", ++ ((eMMC_SPEED_TEST_SINGLE_BLKCNT_R<>10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ // ================================== ++ u32_SectorCnt = 0; ++ LABEL_MULTI: ++ eMMC_debug(0,0,"------------------------------\n"); ++ switch(u32_SectorCnt) ++ { ++ case 0: ++ u32_SectorCnt = 0x400*4 >> eMMC_SECTOR_512BYTE_BITS; //4KB ++ break; ++ case 0x400*4 >> eMMC_SECTOR_512BYTE_BITS: ++ u32_SectorCnt = 0x400*16 >> eMMC_SECTOR_512BYTE_BITS; //16KB ++ break; ++ case 0x400*16 >> eMMC_SECTOR_512BYTE_BITS: ++ u32_SectorCnt = 0x400*64 >> eMMC_SECTOR_512BYTE_BITS; //64KB ++ break; ++ case 0x400*64 >> eMMC_SECTOR_512BYTE_BITS: ++ u32_SectorCnt = 0x400*1024 >> eMMC_SECTOR_512BYTE_BITS; //1MB ++ break; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Write, total: %u MB, burst size: %u KB\n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20, u32_SectorCnt>>1); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/100); // 10ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u.%u MB/s \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>20, ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_W<>10)*10/1024%10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ // ----------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"Multi Read, total: %uMB, burst size: %u KB \n", ++ (eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20, u32_SectorCnt>>1); ++ ++ u32_SectorAddr = eMMC_TEST_BLK_0; ++ eMMC_hw_timer_start(); ++ u32_t0 = eMMC_hw_timer_tick(); ++ for(u32_i=0; u32_i u32_t0 ? u32_t1-u32_t0 : 0xFFFFFFFF-u32_t0+u32_t1; ++ u32_t = u32_t/(eMMC_HW_TIMER_HZ/10); // 100ms ++ if(0!=u32_t) ++ eMMC_debug(0,0," %u.%u MB/s \n", ++ ((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>20, ++ (((eMMC_SPEED_TEST_MULTIPLE_BLKCNT_R<>10)*10/1024%10); ++ else ++ eMMC_debug(0,0,"t=0 \n"); ++ ++ if(u32_SectorCnt != 0x400*1024 >> eMMC_SECTOR_512BYTE_BITS) ++ goto LABEL_MULTI; ++ ++ // =============================================== ++ if(0==u8_LoopCnt) ++ { ++ u8_LoopCnt++; ++ ++ eMMC_debug(0,0,"\n\n"); ++ // test for next mode ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: ChooseSpeedMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ ++ goto LABEL_TEST_START; ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_Main(void) ++{ ++ U32 u32_err; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"eMMC_IPVerify_Main\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"%Xh %Xh %Xh\n", ++ (U32)gau8_eMMC_SectorBuf, (U32)gau8_RBuf, (U32)gau8_WBuf); ++ ++ // =============================================== ++ #if 0 ++ eMMC_BootMode(); ++ //while(1); ++ return 0; ++ #endif ++ ++ // =============================================== ++ u32_err = eMMC_Init(); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_Init fail: %Xh \n", u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_Init ok] \n"); ++ ++ // =============================================== ++ #if 0 ++ eMMC_debug(0,1,"BootImage ByteCnt: %Xh, ChkSum:%Xh\n", ++ sizeof(gau8_BootImageOri), eMMC_ChkSum(gau8_BootImageOri, sizeof(gau8_BootImageOri))); ++ ++ u32_err = eMMC_WriteBootPart(gau8_BootImageOri, sizeof(gau8_BootImageOri), 0, 1); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_WriteBootPart fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "[eMMC_WriteBootPart ok] \n"); ++ ++ while(1); ++ #endif ++ ++ // =============================================== ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal pattern test ok\n\n"); ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "specific pattern test ok\n\n"); ++ ++ #if 1 ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00000000); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal pattern test ok\n\n"); ++ ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "specific pattern test ok\n\n"); ++ #endif ++ ++ #if 1 ++ eMMC_IPVerify_Main_API_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_API_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "APIs test ok\n\n"); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_IPVerify_Main_API_Ex(U32 u32_DataPattern) ++{ ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, *pu32_R=(U32*)gau8_RBuf, u32_err; ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = u32_DataPattern; ++ pu32_R[u32_i] = ~pu32_W[u32_i]; ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ ++ u32_err = eMMC_WriteData((U8*)pu32_W, TEST_BUFFER_SIZE, eMMC_TEST_BLK_0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_WriteData fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_WriteData ok] \n"); ++ ++ u32_err = eMMC_ReadData((U8*)pu32_R, TEST_BUFFER_SIZE, eMMC_TEST_BLK_0); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMC_ReadData fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMC_ReadData ok] \n"); ++ ++ u32_err = eMMC_ComapreData((U8*)pu32_W, (U8*)pu32_R, TEST_BUFFER_SIZE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, eMMC_ComapreData fail: %u, %Xh \n", u32_i, u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_Main_Sg_Ex(U32 u32_DataPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt = eMMC_TEST_BLK_CNT; ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ ++ #if 1 ++ u32_err = eMMCTest_SgWRC_MIU(u32_StartSector, u32_SectorCnt, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SgWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SgWRC_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_Main_Ex(U32 u32_DataPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "Data Pattern: %08Xh\n", u32_DataPattern); ++ //eMMC_debug(0,1,"Total Sec: %Xh, StartSec: %Xh, SecCnt: %Xh \n", ++ // g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ ++ #if 1 ++ if(eMMC_IF_NORMAL_SDR()){ ++ u32_err = eMMCTest_SingleBlkWRC_RIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_RIU fail: %Xh \n", u32_err); ++ //goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_RIU ok] \n");} ++ #endif ++ ++ #if 1 ++ u32_err = eMMCTest_SingleBlkWRC_MIU(u32_StartSector, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_SingleBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_SingleBlkWRC_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMCTest_MultiBlkWRC_MIU(u32_StartSector, u32_SectorCnt, u32_DataPattern); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "Err, eMMCTest_MultiBlkWRC_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[eMMCTest_MultiBlkWRC_MIU ok] \n"); ++ #endif ++ ++ ++ // =============================================== ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[eMMC IPVerify Fail: %Xh] \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_ReadOnly(void) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ #if 1 ++ if(eMMC_IF_NORMAL_SDR()){ ++ u32_err = eMMC_CMD17_CIFD(u32_StartSector, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD17_CIFD fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD17_CIFD ok] \n");} ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD17_MIU(u32_StartSector, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD17_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD17_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD18_MIU(u32_StartSector, gau8_RBuf, u32_SectorCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD18_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD18_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "fail: %Xh \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_WriteOnly(U16 u16_TestPattern) ++{ ++ static U32 u32_StartSector=0, u32_SectorCnt=0, u32_err; ++ U32 u32_i, *pu32_W=(U32*)gau8_WBuf, u32_ByteCnt; ++ ++ // make StartSector SectorCnt random ++ u32_StartSector = eMMC_TEST_BLK_0; ++ u32_SectorCnt++; ++ while(u32_SectorCnt > eMMC_TEST_BLK_CNT) ++ u32_SectorCnt = 1; ++ ++ u32_ByteCnt = (u32_SectorCnt<<9) > TEST_BUFFER_SIZE ? ++ TEST_BUFFER_SIZE : (u32_SectorCnt<<9); ++ ++ // init data pattern ++ for(u32_i=0; u32_i>2; u32_i++) ++ { ++ pu32_W[u32_i] = (u16_TestPattern<<16)+u16_TestPattern; ++ } ++ ++ #if 1 ++ if(eMMC_IF_NORMAL_SDR()){ ++ u32_err = eMMC_CMD24_CIFD(u32_StartSector, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD24_CIFD fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD24_CIFD ok] \n");} ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD24_MIU(u32_StartSector, gau8_WBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD24_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD24_MIU ok] \n"); ++ #endif ++ ++ #if 1 ++ u32_err = eMMC_CMD25_MIU(u32_StartSector, gau8_WBuf, u32_SectorCnt); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD25_MIU fail: %Xh \n", u32_err); ++ goto LABEL_IP_VERIFY_ERROR; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL_HIGH,1,"[CMD25_MIU ok] \n"); ++ #endif ++ ++ // =============================================== ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ //eMMC_debug(eMMC_DEBUG_LEVEL, 1, "[OK] \n\n"); ++ return eMMC_ST_SUCCESS; ++ ++ LABEL_IP_VERIFY_ERROR: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Total Sec: %Xh, Test: StartSec: %Xh, SecCnt: %Xh \n", ++ g_eMMCDrv.u32_SEC_COUNT, u32_StartSector, u32_SectorCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "fail: %Xh \n\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ while(1); ++ return u32_err; ++} ++ ++ ++ ++U32 eMMCTest_Lifetime(U8 u8_TestMode) ++{ ++ U32 u32_i, u32_err=eMMC_ST_SUCCESS, u32_BlkAddr; ++ U32 u32_BlkCnt0=0, u32_BlkCnt1=0, *pu32_BlkCnt, u32_LoopCnt=0; ++ ++ // set to slow & safe clock ++ eMMC_clock_setting(gau8_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT-1]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"===========================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"CAUTION: will damage images in eMMC \n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"===========================================\n"); ++ ++ //------------------------------------------------- ++ if(eMMC_LIFETIME_TEST_FIXED == u8_TestMode) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"fixed addr: 6th block\n"); ++ ++ while(1) ++ { ++ eMMC_reset_WatchDog(); ++ ++ if(u32_BlkCnt0 < (U32)(0-1)) ++ pu32_BlkCnt = &u32_BlkCnt0; ++ else if((U32)(0-1) == u32_BlkCnt1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC: %Xh %Xh blocks tested, stop \n", ++ u32_BlkCnt1, u32_BlkCnt0); ++ while(1); ++ } ++ else ++ pu32_BlkCnt = &u32_BlkCnt1; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD18_MIU, %Xh \n", u32_err); ++ break; ++ }u32_err = eMMC_CMD18_MIU( // to drop data from possible cache inside eMMC ++ 100, gau8_RBuf, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD18_MIU, %Xh \n", u32_err); ++ break; ++ } ++ ++ u32_err = eMMC_CMD17_MIU(6, gau8_RBuf); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, CMD17_MIU, %Xh \n", u32_err); ++ break; ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, eMMC_SECTOR_BYTECNT); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(0,1,"Err, ComapreData, %Xh \n", u32_err); ++ break; ++ } ++ ++ *pu32_BlkCnt+=1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: %08X %08X blocks tested ... ", ++ u32_BlkCnt1, u32_BlkCnt0); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: %Xh %Xh blocks tested, stop \n", ++ u32_BlkCnt1, u32_BlkCnt0); ++ eMMC_FCIE_ErrHandler_Stop(); ++ ++ } ++ //------------------------------------------------- ++ else if(eMMC_LIFETIME_TEST_FILLED == u8_TestMode) ++ { ++ while(1) ++ { ++ eMMC_reset_WatchDog(); ++ ++ if((U32)(0-1) == u32_LoopCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC: %u loops tested, stop \n", ++ u32_LoopCnt); ++ while(1); ++ } ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: w fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_i += TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS; ++ if(g_eMMCDrv.u32_SEC_COUNT-u32_i < ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS)) ++ break; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: w (%08Xh x %08Xh + %08Xh) blocks ... ", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT, u32_i); ++ } ++ // r & c ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: r fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, TEST_BUFFER_SIZE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: c fail: %Xh \n", u32_err); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_i += TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS; ++ if(g_eMMCDrv.u32_SEC_COUNT-u32_i < ++ (TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS)) ++ break; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: r c (%08Xh x %08Xh + %08Xh) blocks ... ", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT, u32_i); ++ } ++ ++ u32_LoopCnt += 1; ++ } ++ } ++ //------------------------------------------------- ++ else if(eMMC_LIFETIME_TEST_RANDOM == u8_TestMode) ++ { ++ eMMC_hw_timer_start(); // use to get tick as a random seed ++ ++ while(1) ++ { ++ eMMC_reset_WatchDog(); ++ ++ if((U32)(0-1) == u32_LoopCnt) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n eMMC: %u loops tested, stop \n", ++ u32_LoopCnt); ++ while(1); ++ } ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_BYTECNT_BITS)) ++ u32_BlkAddr = g_eMMCDrv.u32_SEC_COUNT ++ - (TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS) - 1; ++ // w ++ u32_err = eMMC_CMD25_MIU(u32_BlkAddr, gau8_WBuf, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: w fail: %Xh, BlkAddr: %Xh \n", u32_err, u32_BlkAddr); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ // r & c ++ u32_err = eMMC_CMD18_MIU(u32_BlkAddr, gau8_RBuf, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: r fail: %Xh, BlkAddr: %Xh \n", u32_err, u32_BlkAddr); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ u32_err = eMMC_ComapreData(gau8_WBuf, gau8_RBuf, TEST_BUFFER_SIZE); ++ if(eMMC_ST_SUCCESS != u32_err) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0,"\neMMC Err: c fail: %Xh, BlkAddr: %Xh \n", u32_err, u32_BlkAddr); ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"eMMC: (%Xh x %Xh) blocks tested, stop \n", ++ u32_LoopCnt, g_eMMCDrv.u32_SEC_COUNT); ++ eMMC_FCIE_ErrHandler_Stop(); ++ } ++ ++ u32_LoopCnt += 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\r eMMC: now @ %08Xh block, total %08Xh x %Xh blocks tested ... ", ++ u32_BlkAddr, u32_LoopCnt, TEST_BUFFER_SIZE>>eMMC_SECTOR_BYTECNT_BITS); ++ } ++ } ++ ++ return u32_err; ++} ++ ++ ++U32 eMMC_IPVerify_SDRDDR_AllClkTemp(void) ++{ ++ U32 u32_err; ++ U8 u8_SDRClkIdx, u8_DDRClkIdx; ++ ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: ChooseSpeedMode fail: %Xh\n", u32_err); ++ return u32_err; ++ } ++ eMMC_DumpTimingTable(); ++ ++ u8_SDRClkIdx = 0; ++ u8_DDRClkIdx = 0; ++ ++ while(1) ++ { ++ #if 1 ++ //eMMC_hw_timer_delay(HW_TIMER_DELAY_1s); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"SDR\n"); ++ u32_err = eMMC_FCIE_EnableSDRMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: EnableSDRMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ //if(0==u8_SDRClkIdx) u8_SDRClkIdx++; // skip 48MHz ++ eMMC_clock_setting(gau8_FCIEClkSel[u8_SDRClkIdx]); ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Clk: %u %sHz\n", ++ g_eMMCDrv.u32_ClkKHz>1000 ? g_eMMCDrv.u32_ClkKHz/1000 : g_eMMCDrv.u32_ClkKHz, ++ g_eMMCDrv.u32_ClkKHz>1000 ? "M" : "K"); ++ u8_SDRClkIdx++; ++ //u8_SDRClkIdx = u8_SDRClkIdx%(eMMC_FCIE_VALID_CLK_CNT-1);// skip 300KHz ++ u8_SDRClkIdx = u8_SDRClkIdx%eMMC_FCIE_VALID_CLK_CNT; ++ ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ #endif ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"======================================\n"); ++ // [CAUTION]: switch to fast mode, Brian said a fixed clock for emmcpll, do not switch emmcpll clock. [2013 Nov.. Napoli back] ++ u32_err = eMMC_FCIE_ChooseSpeedMode(); ++ if(eMMC_ST_SUCCESS != u32_err){ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: ChooseSpeedMode fail: %Xh\n", u32_err); ++ eMMC_DumpDriverStatus(); ++ return u32_err; ++ } ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Ex(eMMC_PATTERN_AA55AA55); ++ ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_FFFFFFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00000000); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_000000FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_0000FFFF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_00FF00FF); ++ eMMC_IPVerify_Main_Sg_Ex(eMMC_PATTERN_AA55AA55); ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"\n"); ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++#define eMMC_PWRCUT_DATA0 0x55 ++#define eMMC_PWRCUT_DATA1 0xAA ++#define eMMC_PWRCUT_DATA_CNT 2 ++ ++#define eMMC_PWRCUT_TEST_UNIT_BYTECNT 0x1000000 ++#define eMMC_PWRCUT_TEST_SPACE_BYTECNT (16*eMMC_PWRCUT_TEST_UNIT_BYTECNT) // 256MB ++#define eMMC_PWRCUT_TEST_UNIT_CNT (eMMC_PWRCUT_TEST_SPACE_BYTECNT/eMMC_PWRCUT_TEST_UNIT_BYTECNT) ++ ++typedef eMMC_PACK0 struct _eMMC_PWRCUT_CTRLBLK { ++ ++ U32 u32_CheckSum; ++ U8 u8_TargetUnit; ++ U8 au8_TaegetData[eMMC_PWRCUT_TEST_UNIT_CNT]; ++ ++} eMMC_PACK1 eMMC_PWRCUT_CTRLBLK_t; ++ ++void eMMC_DumpsPwrCutCtrlBlk(eMMC_PWRCUT_CTRLBLK_t *pCtrlBlk_t) ++{ ++ U32 u32_i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, ++ "eMMC: CheckSum: %Xh\n", pCtrlBlk_t->u32_CheckSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, ++ "eMMC: TargetUnit: %Xh\n", pCtrlBlk_t->u8_TargetUnit); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, " Target Data: "); ++ for(u32_i=0; u32_iau8_TaegetData[u32_i]); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "\n"); ++} ++ ++U32 eMMC_CheckPwrCutCtrlBlk(U8* u8_DataBuf, U32 u32_BlkAddr) ++{ ++ U32 u32_err; ++ eMMC_PWRCUT_CTRLBLK_t *pCtrlBlk_t; ++ ++ u32_err = eMMC_ReadData(u8_DataBuf, eMMC_SECTOR_512BYTE, u32_BlkAddr); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: read CtrlBlk, Err:%x\n", u32_err); ++ return u32_err; ++ } ++ ++ pCtrlBlk_t = (eMMC_PWRCUT_CTRLBLK_t*)u8_DataBuf; ++ ++ if(pCtrlBlk_t->u32_CheckSum != ++ eMMC_ChkSum(u8_DataBuf+4, sizeof(eMMC_PWRCUT_CTRLBLK_t)-4)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: read CtrlBlk, CheckSum fail\n"); ++ return eMMC_ST_ERR_CHKSUM; ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMCTest_PwrCut_InitData(U8* u8_DataBuf, U32 u32_BlkStartAddr) ++{ ++ U32 u32_i, u32_j; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ eMMC_PWRCUT_CTRLBLK_t CtrlBlk_t; ++ ++ struct mmc *mmc = find_mmc_device(0); ++ mmc_slc_mode(mmc, 0, 1); // enable reliable ++ ++ // --------------------------------------- ++ CtrlBlk_t.u8_TargetUnit = 0xFF; ++ ++ for(u32_i=0; u32_i>9)); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: Reliable write Fail @ %u unit, Err:%x\n", u32_i, u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"%03u%% \r", (u32_i+1)*100/eMMC_PWRCUT_TEST_UNIT_CNT); ++ } ++ ++ // --------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"\ncheck ...\n"); ++ ++ if(eMMC_ST_SUCCESS != eMMC_CheckPwrCutCtrlBlk(u8_DataBuf, u32_BlkStartAddr-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: read CtrlBlk fail\n"); ++ return eMMC_ST_ERR_CHKSUM; ++ } ++ ++ for(u32_i=0; u32_i>9)); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: Reliable write Fail @ %u unit, Err:%x\n", u32_i, u32_err); ++ return u32_err; ++ } ++ ++ for (u32_j=0; u32_j < eMMC_PWRCUT_TEST_UNIT_BYTECNT; u32_j++) ++ { ++ if (u8_DataBuf[u32_j] != eMMC_PWRCUT_DATA0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: Data Mismatch: Blk:%Xh ByteIdx:%Xh ByteVal:%Xh \n", ++ u32_BlkStartAddr+u32_i*(eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9)+(u32_j>>9), ++ u32_j & 0x1FF, u8_DataBuf[u32_j]); ++ return eMMC_ST_ERR_DATA_MISMATCH; ++ } ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"%03u%% \r", (u32_i+1)*100/eMMC_PWRCUT_TEST_UNIT_CNT); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"\n init success\n"); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMCTest_PwrCut_Test(U8* u8_DataBuf, U32 u32_BlkStartAddr) ++{ ++ U32 u32_i, u32_j; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U32 u32_T0, u32_BlkAddr; ++ eMMC_PWRCUT_CTRLBLK_t CtrlBlk_t; ++ ++ eMMC_hw_timer_start(); ++ ++ // --------------------------------------- ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"\n eMMC PwrCut Test, checking ...\n"); ++ ++ // get Ctrl Blk ++ if(eMMC_ST_SUCCESS != eMMC_CheckPwrCutCtrlBlk(u8_DataBuf, u32_BlkStartAddr)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: read CtrlBlk fail\n"); ++ //return eMMC_ST_ERR_CHKSUM; ++ while(1); ++ } ++ memcpy(&CtrlBlk_t, u8_DataBuf, sizeof(eMMC_PWRCUT_CTRLBLK_t)); ++ ++ // check data ++ u32_BlkStartAddr++; ++ ++ for(u32_i=0; u32_i>9)); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, ++ "\neMMC Err: Reliable write Fail @ %u unit, Err:%x\n", u32_i, u32_err); ++ return u32_err; ++ } ++ ++ if(u32_i == CtrlBlk_t.u8_TargetUnit){ ++ for (u32_j=0; u32_j < eMMC_PWRCUT_TEST_UNIT_BYTECNT; u32_j++) ++ { ++ if (u8_DataBuf[u32_j]!=eMMC_PWRCUT_DATA0 && ++ u8_DataBuf[u32_j]!=eMMC_PWRCUT_DATA1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, ++ "\neMMC Err: Target Data Mismatch: Unit:%Xh " ++ "Blk: %Xh + %Xh x %Xh + %Xh = %Xh, ByteIdx:%Xh ByteVal:%Xh \n", ++ u32_i, ++ u32_BlkStartAddr, u32_i, (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9), (u32_j>>9), ++ u32_BlkStartAddr+u32_i*(eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9)+(u32_j>>9), ++ u32_j & 0x1FF, u8_DataBuf[u32_j]); ++ eMMC_DumpsPwrCutCtrlBlk(&CtrlBlk_t); ++ eMMC_dump_mem(&u8_DataBuf[u32_j]-0x10, 0x30); ++ return eMMC_ST_ERR_DATA_MISMATCH; ++ } ++ } ++ // recover TargetUnit ++ u32_BlkAddr = u32_BlkStartAddr + ++ CtrlBlk_t.u8_TargetUnit * ++ (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>eMMC_SECTOR_512BYTE_BITS); ++ memset(u8_DataBuf, CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit], eMMC_PWRCUT_TEST_UNIT_BYTECNT); ++ u32_err = eMMC_WriteData(u8_DataBuf, eMMC_PWRCUT_TEST_UNIT_BYTECNT, u32_BlkAddr); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: write TargetUnit fail, Err:%x\n",u32_err); ++ return u32_err; ++ }} ++ else{ ++ for (u32_j=0; u32_j < eMMC_PWRCUT_TEST_UNIT_BYTECNT; u32_j++) ++ { ++ if (u8_DataBuf[u32_j]!=CtrlBlk_t.au8_TaegetData[u32_i]) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, ++ "\neMMC Err: Data Mismatch: Unit:%Xh " ++ "Blk: %Xh + %Xh x %Xh + %Xh = %Xh, ByteIdx:%Xh ByteVal:%Xh \n", ++ u32_i, ++ u32_BlkStartAddr, u32_i, (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9), (u32_j>>9), ++ u32_BlkStartAddr+u32_i*(eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9)+(u32_j>>9), ++ u32_j & 0x1FF, u8_DataBuf[u32_j]); ++ eMMC_DumpsPwrCutCtrlBlk(&CtrlBlk_t); ++ eMMC_dump_mem(&u8_DataBuf[u32_j]-0x10, 0x30); ++ //return eMMC_ST_ERR_DATA_MISMATCH; ++ while(1); ++ } ++ }} ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0,"%03u%% \r", (u32_i+1)*100/eMMC_PWRCUT_TEST_UNIT_CNT); ++ } ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0," ok\n"); ++ ++ // --------------------------------------- ++ while(1) ++ { ++ u32_T0 = eMMC_hw_timer_tick(); ++ CtrlBlk_t.u8_TargetUnit = u32_T0 % eMMC_PWRCUT_TEST_UNIT_CNT; ++ CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit] ^= 0xFF; ++ CtrlBlk_t.u32_CheckSum = eMMC_ChkSum((U8*)&CtrlBlk_t.u8_TargetUnit, ++ sizeof(eMMC_PWRCUT_CTRLBLK_t)-4); ++ u32_err = eMMC_WriteData((U8*)&CtrlBlk_t, eMMC_SECTOR_512BYTE, u32_BlkStartAddr-1); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Err: write CtrlBlk, Err:%x\n", u32_err); ++ return u32_err; ++ } ++ ++ u32_BlkAddr = u32_BlkStartAddr + ++ CtrlBlk_t.u8_TargetUnit * ++ (eMMC_PWRCUT_TEST_UNIT_BYTECNT>>eMMC_SECTOR_512BYTE_BITS); ++ memset(u8_DataBuf, CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit], eMMC_PWRCUT_TEST_UNIT_BYTECNT); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0 ,"writing... %02Xh %08Xh %02Xh\n", ++ CtrlBlk_t.u8_TargetUnit, u32_BlkAddr, CtrlBlk_t.au8_TaegetData[CtrlBlk_t.u8_TargetUnit]); ++ ++ u32_err = eMMC_WriteData(u8_DataBuf, eMMC_PWRCUT_TEST_UNIT_BYTECNT, u32_BlkAddr); ++ //u32_err = eMMC_CMD25(u32_BlkAddr, u8_DataBuf, eMMC_PWRCUT_TEST_UNIT_BYTECNT>>9); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: write Fail, Err:%x\n",u32_err); ++ return u32_err; ++ } ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMCTest_PwrCut_Test2(U8* u8_DataBuf, U32 u32_BlkStartAddr) ++{ ++ U32 u32_blk_cnt ,u32_i,u32_test_loop; ++ U32 u32_err = eMMC_ST_SUCCESS; ++ U8 data; ++ ++ struct mmc *mmc = find_mmc_device(0); ++ ++ if (!mmc) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: no mmc device at slot\n"); ++ return 1; ++ } ++ ++ if(!mmc->has_init) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Need mmc init first!\n"); ++ return 1; ++ } ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: Reliable write ext_csd[167] 0x%02x, ext_csd[166] 0x%02x\n", mmc->ext_csd[167], mmc->ext_csd[166]); ++ ++ if (mmc->reliable_write == 1) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: Reliable write is supported but unconfigured\n"); ++ ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, EXT_CSD_WR_REL_SET, 0x1f); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ // complete the partition configuration ++ u32_err = eMMC_ModifyExtCSD(eMMC_ExtCSD_WByte, EXT_CSD_PARTITION_SETTING_COMPLETED, 0x01); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ mmc->reliable_write = 2; ++ ++ while (1) ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"eMMC Info: Please reset the board!!!!!! Reliable write would be active after reset!!!!!!\n"); ++ } ++ else if (mmc->reliable_write == 2) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1,"eMMC Info: Reliable write is supported and has been configured\n"); ++ } ++ else if (mmc->reliable_write == 0) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Info: Reliable write is unsupported\n"); ++ while(1); ++ } ++ ++ u32_blk_cnt = (48 *1024 * 1024)>>eMMC_SECTOR_512BYTE_BITS; ++ ++ memset(u8_DataBuf, 0, (48 *1024 * 1024)); ++ //step1 ++ u32_err = eMMC_ReadData(u8_DataBuf, u32_blk_cnt<>9,u32_i & 0x1FF, u8_DataBuf[u32_i], data); ++ return eMMC_ST_ERR_DATA_MISMATCH; ++ } ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Reliable read compare success\n"); ++ ++ data = (U8)eMMC_hw_timer_tick();//rRand((unsigned int)data, (unsigned int)(u8_DataBuf - data)); ++ memset(u8_DataBuf, data, (48 *1024 * 1024)); ++ u32_test_loop=0; ++ ++ u32_err = eMMC_WriteData(u8_DataBuf, (48 *1024 * 1024), u32_BlkStartAddr); ++ if(u32_err != eMMC_ST_SUCCESS) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: Reliable write Fail,Err:%x\n",u32_err); ++ return u32_err; ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL,1,"Reliable write Success\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"power cut test loop star\n"); ++ ++ u32_BlkStartAddr += ((48 *1024 * 1024) >> eMMC_SECTOR_512BYTE_BITS); ++ u32_blk_cnt = (4 *1024 * 1024)>>eMMC_SECTOR_512BYTE_BITS; ++ while(1) ++ { ++ //step3 ++ for (u32_i=0; u32_i < u32_blk_cnt; u32_i++) ++ { ++ u32_err = eMMC_WriteData(u8_DataBuf+(u32_i< ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++//-------------------------------------------------------------------------- ++static eMMC_ALIGN0 eMMC_TEST_ALIGN_PACK_t g_eMMCTestAlignPack_t eMMC_ALIGN1; ++U32 eMMC_CheckAlignPack(U8 u8_AlignByteCnt) ++{ ++ // check alignment ++ if((uintptr_t)&(g_eMMCTestAlignPack_t.u8_0) & (u8_AlignByteCnt-1)) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not aliged. expect %Xh but %lXh \n", ++ u8_AlignByteCnt, (uintptr_t)&(g_eMMCTestAlignPack_t.u8_0)); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_ALIGN; ++ } ++ // check packed - 0 ++ if((uintptr_t)&(g_eMMCTestAlignPack_t.u16_0)-(uintptr_t)&(g_eMMCTestAlignPack_t.u8_0) != 1 || ++ (uintptr_t)&(g_eMMCTestAlignPack_t.u32_0)-(uintptr_t)&(g_eMMCTestAlignPack_t.u8_0) != 3 || ++ (uintptr_t)&(g_eMMCTestAlignPack_t.u32_1)-(uintptr_t)&(g_eMMCTestAlignPack_t.u8_0) != 7) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not packed. check err.0 \n"); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_PACKED; ++ } ++ // check packed - 1 ++ if((uintptr_t)&(g_eMMCTestAlignPack_t.u16_0)-(uintptr_t)&(g_eMMCTestAlignPack_t.u8_0) != 1 || ++ (uintptr_t)&(g_eMMCTestAlignPack_t.u32_0)-(uintptr_t)&(g_eMMCTestAlignPack_t.u16_0)!= 2 || ++ (uintptr_t)&(g_eMMCTestAlignPack_t.u32_1)-(uintptr_t)&(g_eMMCTestAlignPack_t.u32_0)!= 4) ++ { ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 1, "eMMC Err: not packed. check err.1 \n"); ++ eMMC_die("\n"); ++ return eMMC_ST_ERR_NOT_PACKED; ++ } ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_HIGH, 1, "ok\n"); ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++static __inline void dump_mem_line(unsigned char *buf, U32 cnt) ++{ ++ U32 i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " 0x%08lX: ", (uintptr_t)buf); ++ for (i= 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%02Xh ", buf[i]); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " | "); ++ ++ for (i = 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%c", (buf[i] >= 32 && buf[i] < 128) ? buf[i] : '.'); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "\n"); ++} ++ ++void eMMC_dump_mem(unsigned char *buf, U32 cnt) ++{ ++ U32 i; ++ ++ for (i= 0; i < cnt; i+= 16) ++ dump_mem_line(buf + i, 16); ++} ++ ++static __inline void dump_mem_line_32(U32 *buf, int cnt) ++{ ++ U32 i; ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " 0x%08lX: ", (uintptr_t)buf); ++ for (i= 0; i < cnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, "%08Xh ", buf[i]); ++} ++ ++void eMMC_dump_mem_32(U32 *buf, U32 cnt) ++{ ++ U32 i; ++ ++ for (i= 0; i < cnt; i+= 8) ++ { ++ dump_mem_line_32(buf + i, 8); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR, 0, " | 0x%08X \n", i+7); ++ } ++} ++ ++ ++ ++U32 eMMC_ComapreData(U8 *pu8_Buf0, U8 *pu8_Buf1, U32 u32_ByteCnt) ++{ ++ U32 u32_i, u32_offset; ++ ++ for(u32_i=0; u32_i>eMMC_SECTOR_512BYTE_BITS)<>11); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "eMMC BUS_WIDTH: %Xh\n", g_eMMCDrv.u8_BUS_WIDTH); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TRIM: %Xh\n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_TRIM)?1:0); ++ ++ if(g_eMMCDrv.u32_eMMCFlag & (eMMC_FLAG_HPI_CMD12|eMMC_FLAG_HPI_CMD13)) ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: CMD%u \n", ++ (g_eMMCDrv.u32_eMMCFlag&eMMC_FLAG_HPI_CMD12)?12:13); ++ else ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "HPI: 0 \n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"Reliable Write BlkCnt: %Xh\n", g_eMMCDrv.u16_ReliableWBlkCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL,0,"Power Off Notification: ECSD[34]:%Xh, Short: %u ms, Long: %u ms\n", ++ g_eMMCDrv.u8_ECSD34_PwrOffCtrl, ++ g_eMMCDrv.u8_ECSD248_CMD6TO*10, ++ g_eMMCDrv.u8_ECSD247_PwrOffLongTO*10); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ // ------------------------------ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(0, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ ++ u32_err = eMMC_CMD9(g_eMMCDrv.u16_RCA); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CSD:\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CSD[0], eMMC_MAX_RSP_BYTE_CNT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "SPEC_VERS: %Xh, R_BL_LEN: %Xh, W_BL_LEN: %Xh \n", ++ g_eMMCDrv.u8_SPEC_VERS, g_eMMCDrv.u8_R_BL_LEN, g_eMMCDrv.u8_W_BL_LEN); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "Access Mode: %s\n", g_eMMCDrv.u8_IfSectorMode?"Sector":"Byte"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "C_SIZE: %Xh\n", g_eMMCDrv.u16_C_SIZE); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "ERASE_GRP_SIZE: %Xh, ERASE_GRP_MULT: %Xh\n", ++ g_eMMCDrv.u8_ERASE_GRP_SIZE, g_eMMCDrv.u8_ERASE_GRP_MULT); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "EraseUnitSize: %u\n", g_eMMCDrv.u32_EraseUnitSize); ++ switch(g_eMMCDrv.u8_Tran_Speed) ++ { ++ case 0x2A: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 20MHz\n"); break; ++ case 0x32: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "default speed 26MHz\n"); break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "normal TRAN_SPEED: %Xh\n", g_eMMCDrv.u8_Tran_Speed); ++ } ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "TAAC: %Xh, NSAC: %Xh, R2W_FACTOR: %Xh\n", ++ g_eMMCDrv.u8_TAAC, g_eMMCDrv.u8_NSAC, g_eMMCDrv.u8_R2W_FACTOR); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "RCA: %Xh\n", g_eMMCDrv.u16_RCA); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "CID:\n"); ++ eMMC_dump_mem(&g_eMMCDrv.au8_CID[1], eMMC_MAX_RSP_BYTE_CNT-1); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 0, "-------------------------------\n\n"); ++ ++ #if 0 ++ u32_err = eMMC_CMD3_CMD7(g_eMMCDrv.u16_RCA, 7); ++ if(eMMC_ST_SUCCESS != u32_err) ++ return u32_err; ++ #endif ++ return u32_err; ++} ++ ++ ++void eMMC_dump_nni(eMMC_NNI_t *peMMCInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ int i; ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC NNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "peMMCInfo: 0x%08lX\n", (uintptr_t)peMMCInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_Tag : ["); ++ for (i = 0; i < 16; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%c", peMMCInfo->au8_Tag[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_IDByteCnt : 0x%04x\n", peMMCInfo->u8_IDByteCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "au8_ID : 0x[ "); ++ for (i = 0; i < peMMCInfo->u8_IDByteCnt; i++) ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "%02X ", peMMCInfo->au8_ID[i]); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 0, "]\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", peMMCInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", peMMCInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", peMMCInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", peMMCInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", peMMCInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_Config : 0x%08X\n", peMMCInfo->u32_Config); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_ECCType : 0x%04x\n", peMMCInfo->u16_ECCType); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SeqAccessTime: 0x%04x\n", peMMCInfo->u16_SeqAccessTime); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_Vendor: %s\n", peMMCInfo->au8_Vendor); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PartNumber: %s\n", peMMCInfo->au8_PartNumber); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapLoc: 0x%04x\n", peMMCInfo->u8_PairPageMapLoc); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u8_PairPageMapType: 0x%04x\n", peMMCInfo->u8_PairPageMapType); ++#endif ++} ++ ++void eMMC_dump_pni(eMMC_PNI_t *pPartInfo) ++{ ++#if eMMC_DEBUG_LEVEL <= eMMC_DEBUG_LEVEL_LOW ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "# eMMC PNI #\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "###############################################\n"); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "pPartInfo: 0x%08lX\n", (uintptr_t)pPartInfo); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u32_ChkSum : 0x%04X\n", pPartInfo->u32_ChkSum); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_SpareByteCnt : 0x%04x\n", pPartInfo->u16_SpareByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PageByteCnt : 0x%04x\n", pPartInfo->u16_PageByteCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkPageCnt : 0x%04x\n", pPartInfo->u16_BlkPageCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_BlkCnt : 0x%04x\n", pPartInfo->u16_BlkCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_PartCnt : 0x%04x\n", pPartInfo->u16_PartCnt); ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW, 1, "u16_UnitByteCnt : 0x%04x\n", pPartInfo->u16_UnitByteCnt); ++ ++ //dump_part_records(pPartInfo->records, pPartInfo->u16_PartCnt); ++#endif ++} ++ ++void eMMC_dump_WR_Count(void) ++{ ++ #if defined(eMMC_PROFILE_WR) && eMMC_PROFILE_WR ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "\n"); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "CNT_CMD17: %u, CNT_CMD24: %u \n", g_eMMCDrv.u32_CNT_CMD17, g_eMMCDrv.u32_CNT_CMD24); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "CNT_CMD18: %u, CNT_CMD25: %u \n", g_eMMCDrv.u32_CNT_CMD18, g_eMMCDrv.u32_CNT_CMD25); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "TotalRBlk: %llu, TotalWBlk: %llu \n", g_eMMCDrv.u64_CNT_TotalRBlk, g_eMMCDrv.u64_CNT_TotalWBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "MinRBlk: %u, MinWBlk: %u \n", g_eMMCDrv.u32_CNT_MinRBlk, g_eMMCDrv.u32_CNT_MinWBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "MaxRBlk: %u, MaxWBlk: %u \n", g_eMMCDrv.u32_CNT_MaxRBlk, g_eMMCDrv.u32_CNT_MaxWBlk); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "RHitCnt: %u, WHitCnt: %u \n", g_eMMCDrv.u32_Addr_RHitCnt, g_eMMCDrv.u32_Addr_WHitCnt); ++ ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "au32_CNT_MinRBlk: \n"); ++ eMMC_dump_mem_32(g_eMMCDrv.au32_CNT_MinRBlk, 0x200); ++ eMMC_debug(eMMC_DEBUG_LEVEL, 1, "au32_CNT_MinWBlk: \n"); ++ eMMC_dump_mem_32(g_eMMCDrv.au32_CNT_MinWBlk, 0x200); ++ ++ #endif ++} ++ ++#endif +diff --git a/drivers/mstar/emmc/unify_driver/src/config/eMMC_platform.c b/drivers/mstar/emmc/unify_driver/src/config/eMMC_platform.c +new file mode 100644 +index 00000000..cfb706fb +--- /dev/null ++++ b/drivers/mstar/emmc/unify_driver/src/config/eMMC_platform.c +@@ -0,0 +1,784 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#include "eMMC.h" ++#if defined(UNIFIED_eMMC_DRIVER) && UNIFIED_eMMC_DRIVER ++ ++void eMMC_Prepare_Power_Saving_Mode_Queue(void) ++{ ++ #if (defined(eMMC_DRV_CHICAGO_LINUX) && eMMC_DRV_CHICAGO_LINUX) ++ REG_FCIE_SETBIT(REG_BATTERY, reg_nobat_int_en); ++ ++ /* (1) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x40), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x41), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (2) Clear All Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x42), 0xffff); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x43), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (3) Clear SDE MODE Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x44), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x45), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (4) Clear SDE CTL Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x46), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x47), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (5) Reset Start */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x48), 0x4800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x49), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (6) Reset End */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4A), 0x5800); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x30); ++ ++ /* (7) Set "SD_MOD" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4C), 0x0051); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x10); ++ ++ /* (8) Enable "csreg_sd_en" */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4E), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x4F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (9) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x50), 0x0040); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x51), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x00); ++ ++ /* (10) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x52), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x53), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x01); ++ ++ /* (11) Command Content, IDLE */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x54), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x55), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK1 | 0x02); ++ ++ /* (12) Command Size */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x56), 0x0005); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x57), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0E); ++ ++ /* (13) Response Size */ ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x58), 0x0000); ++ OUTREG16(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x59), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0D); ++ ++ /* (14) Enable Interrupt, SD_CMD_END */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5A), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5B), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x01); ++ ++ /* (15) Command Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5C), 0x0004); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5D), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x11); ++ ++ /* (16) Wait Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5E), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x5F), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WINT); ++ ++ /* (17) Clear Interrupt */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x60), 0x0002); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x61), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x00); ++ ++ /* (18) Clear HW Enable */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x62), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x63), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_WREG | PWR_CMD_BK0 | 0x0A); ++ ++ /* (19) STOP */ ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x64), 0x0000); ++ REG_FCIE_W(GET_REG_ADDR(FCIE_POWEER_SAVE_MODE_BASE, 0x65), ++ PWR_BAT_CLASS | PWR_RST_CLASS | PWR_CMD_STOP); ++ ++ REG_FCIE_W(FCIE_PWR_SAVE_MODE, BIT_POWER_SAVE_MODE_EN | BIT_SD_POWER_SAVE_RST); ++ #endif ++} ++ ++ ++//============================================================= ++#if (defined(eMMC_DRV_INFINITY3_LINUX)&&eMMC_DRV_INFINITY3_LINUX) ++//============================================================= ++U8 gau8_FCIEClkSel[eMMC_FCIE_VALID_CLK_CNT]={ ++ BIT_FCIE_CLK_48M, ++ BIT_FCIE_CLK_40M, ++ BIT_FCIE_CLK_36M, ++ BIT_FCIE_CLK_32M, ++ BIT_FCIE_CLK_20M, ++}; ++U32 gu32_eMMCDrvExtFlag = 0; ++ ++#if defined(CONFIG_OF) ++struct clk_data{ ++ int num_parents; ++ struct clk **clk_fcie; ++// struct clk *clk_ecc; ++}; ++extern struct clk_data *clkdata; ++#endif ++ ++void mdelay_MacroToFun(u32 time) ++{ ++ mdelay(time); ++} ++ ++U32 eMMC_hw_timer_delay(U32 u32usTick) ++{ ++ volatile U32 u32_i=u32usTick; ++ ++ while(u32_i>1000) ++ { ++ udelay(1000); ++ u32_i-=1000; ++ } ++ ++ udelay(u32usTick); ++ return u32usTick + 1; ++} ++ ++U32 eMMC_hw_timer_sleep(U32 u32ms) ++{ ++ U32 u32_i = u32ms; ++ ++ while(u32_i > 1000) ++ { ++ msleep(1000); ++ u32_i -= 1000; ++ } ++ ++ msleep(u32_i); ++ return u32ms; ++} ++ ++//-------------------------------- ++// use to performance test ++U32 eMMC_hw_timer_start(void) ++{ ++ return 0; ++} ++ ++U32 eMMC_hw_timer_tick(void) ++{ ++ return 0; ++} ++ ++void eMMC_DumpPadClk(void) ++{ ++ //--------------------------------------------------------------------- ++ eMMC_debug(0, 0, "[pad setting]:\r\n"); ++ switch(g_eMMCDrv.u8_PadType) ++ { ++ case FCIE_eMMC_BYPASS: eMMC_debug(0, 0, "Bypass\r\n"); break; ++ case FCIE_eMMC_SDR: eMMC_debug(0, 0, "SDR\r\n"); break; ++ default: ++ eMMC_debug(0, 0, "eMMC Err: Pad unknown, %d\r\n", g_eMMCDrv.u8_PadType); eMMC_die("\r\n"); ++ break; ++ } ++} ++ ++U8 gu8_NANDeMMC_need_preset_flag = 1; ++ ++U32 eMMC_pads_switch(U32 u32_FCIE_IF_Type) ++{ ++ g_eMMCDrv.u8_PadType = FCIE_eMMC_SDR; ++ ++ // chiptop ++ REG_FCIE_CLRBIT(reg_all_pad_in, BIT_ALL_PAD_IN); ++ REG_FCIE_CLRBIT(reg_sd_config, BIT_SD_MODE_MASK); ++ REG_FCIE_SETBIT(reg_emmc_config, BIT_EMMC_MODE_1); ++ REG_FCIE_CLRBIT(reg_nand_config,BIT_NAND_MODE_MASK); ++ ++ // fcie ++ REG_FCIE_CLRBIT(FCIE_DDR_MODE, BIT_MACRO_MODE_MASK); ++ ++ //eMMC_debug(eMMC_DEBUG_LEVEL_MEDIUM, 1, "SDR\r\n"); ++ ++ REG_FCIE_SETBIT(FCIE_DDR_MODE, BIT_PAD_IN_SEL_SD|BIT_FALL_LATCH|BIT10); ++ ++ g_eMMCDrv.u32_DrvFlag |= DRV_FLAG_SPEED_HIGH; ++ ++ return eMMC_ST_SUCCESS; ++ ++} ++ ++ ++ ++U32 eMMC_clock_setting(U16 u16_ClkParam) ++{ ++#if defined(CONFIG_OF) ++ U32 u32_clkrate = 0; ++ switch(u16_ClkParam) ++ { ++ case BIT_FCIE_CLK_300K: ++ u32_clkrate = 300*1000; ++ break; ++ case BIT_CLK_XTAL_12M: ++ u32_clkrate = 12*1000*1000; ++ break; ++ case BIT_FCIE_CLK_20M: ++ u32_clkrate = 20*1000*1000; ++ break; ++ case BIT_FCIE_CLK_32M: ++ u32_clkrate = 32*1000*1000; ++ break; ++ case BIT_FCIE_CLK_36M: ++ u32_clkrate = 36*1000*1000; ++ break; ++ case BIT_FCIE_CLK_40M: ++ u32_clkrate = 40*1000*1000; ++ break; ++ case BIT_FCIE_CLK_43_2M: ++ u32_clkrate = 43*1000*1000; ++ break; ++ case BIT_FCIE_CLK_48M: ++ u32_clkrate = 48*1000*1000; ++ break; ++ default: ++ eMMC_die(); ++ break; ++ } ++ //printk("set clock %d\n", u32_clkrate); ++ g_eMMCDrv.u32_ClkKHz = u32_clkrate/1000; ++ g_eMMCDrv.u16_ClkRegVal = u16_ClkParam; ++ clk_set_rate(clkdata->clk_fcie[0], u32_clkrate); ++#else ++ eMMC_PlatformResetPre(); ++ ++ switch(u16_ClkParam) { ++ case BIT_FCIE_CLK_300K: g_eMMCDrv.u32_ClkKHz = 300; break; ++ case BIT_CLK_XTAL_12M: g_eMMCDrv.u32_ClkKHz = 12000; break; ++ case BIT_FCIE_CLK_20M: g_eMMCDrv.u32_ClkKHz = 20000; break; ++ case BIT_FCIE_CLK_32M: g_eMMCDrv.u32_ClkKHz = 32000; break; ++ case BIT_FCIE_CLK_36M: g_eMMCDrv.u32_ClkKHz = 36000; break; ++ case BIT_FCIE_CLK_40M: g_eMMCDrv.u32_ClkKHz = 40000; break; ++ case BIT_FCIE_CLK_43_2M: g_eMMCDrv.u32_ClkKHz = 43200; break; ++ case BIT_FCIE_CLK_48M: g_eMMCDrv.u32_ClkKHz = 48000; break; ++ default: ++ eMMC_debug(eMMC_DEBUG_LEVEL_LOW,1,"eMMC Err: %Xh\n", eMMC_ST_ERR_INVALID_PARAM); ++ return eMMC_ST_ERR_INVALID_PARAM; ++ } ++ ++ //eMMC_debug(0, 1, "clock %dk\n", g_eMMCDrv.u32_ClkKHz); ++ ++ REG_FCIE_CLRBIT(reg_ckg_fcie, BIT0|BIT1); ++ REG_FCIE_CLRBIT(reg_ckg_fcie, BIT_CLKGEN_FCIE_MASK|BIT_FCIE_CLK_SRC_SEL); ++ REG_FCIE_SETBIT(reg_ckg_fcie, u16_ClkParam<<2); ++ ++ REG_FCIE_SETBIT(reg_sc_gp_ctrl, BIT7); ++ ++ g_eMMCDrv.u16_ClkRegVal = u16_ClkParam; ++ ++#endif ++ eMMC_PlatformResetPost(); ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_clock_gating(void) ++{ ++ eMMC_PlatformResetPre(); ++ REG_FCIE_CLRBIT(FCIE_SD_MODE, BIT_CLK_EN); ++ eMMC_PlatformResetPost(); ++ return eMMC_ST_SUCCESS; ++} ++ ++void eMMC_set_WatchDog(U8 u8_IfEnable) ++{ ++ // do nothing ++} ++ ++void eMMC_reset_WatchDog(void) ++{ ++ // do nothing ++} ++extern struct platform_device sg_mstar_emmc_device_st; ++ ++dma_addr_t eMMC_DMA_MAP_address(uintptr_t ulongBuffer, U32 u32_ByteCnt, int mode) ++{ ++ dma_addr_t dma_addr; ++ ++ if(mode == 0) //write ++ { ++ dma_addr = dma_map_single(&sg_mstar_emmc_device_st.dev, (void*)ulongBuffer, u32_ByteCnt, DMA_TO_DEVICE); ++ } ++ else ++ { ++ dma_addr = dma_map_single(&sg_mstar_emmc_device_st.dev, (void*)ulongBuffer, u32_ByteCnt, DMA_FROM_DEVICE); ++ } ++ ++ if( dma_mapping_error(&sg_mstar_emmc_device_st.dev, dma_addr) ) ++ { ++ dma_unmap_single(&sg_mstar_emmc_device_st.dev, dma_addr, u32_ByteCnt, (mode) ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ eMMC_die("eMMC_DMA_MAP_address: Kernel can't mapping dma correctly\n"); ++ } ++ ++ return dma_addr; ++} ++ ++void eMMC_DMA_UNMAP_address(dma_addr_t dma_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++ if(mode == 0) //write ++ { ++ dma_unmap_single(&sg_mstar_emmc_device_st.dev, dma_DMAAddr, u32_ByteCnt, DMA_TO_DEVICE); ++ } ++ else ++ { ++ dma_unmap_single(&sg_mstar_emmc_device_st.dev, dma_DMAAddr, u32_ByteCnt, DMA_FROM_DEVICE); ++ } ++} ++ ++#if 0 ++U32 eMMC_translate_DMA_address_Ex(U32 u32_DMAAddr, U32 u32_ByteCnt, int mode) ++{ ++#if 1 ++ extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++ //mode 0 for write, 1 for read ++ if( mode == WRITE_TO_eMMC ) //Write ++ { ++ //Write (DRAM->NAND)-> flush ++ Chip_Clean_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ else //Read ++ { ++ //Read (NAND->DRAM) -> inv ++ Chip_Flush_Cache_Range_VA_PA(u32_DMAAddr,__pa(u32_DMAAddr), u32_ByteCnt); ++ } ++ /* ++ if(virt_to_phys((void *)u32_DMAAddr) >= MSTAR_MIU1_BUS_BASE) ++ { ++ REG_SET_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ } ++ else ++ REG_CLR_BITS_UINT16( NC_MIU_DMA_SEL, BIT_MIU1_SELECT); ++ */ ++ ++ return virt_to_phys((void *)u32_DMAAddr); ++#else ++ flush_cache(u32_DMAAddr, u32_ByteCnt); ++ return (u32_DMAAddr); ++#endif ++} ++#else ++extern U32 MIU0_BUS_ADDR; ++U32 eMMC_translate_DMA_address_Ex(dma_addr_t dma_DMAAddr, U32 u32_ByteCnt) ++{ ++ REG_FCIE_CLRBIT(FCIE_MMA_PRI_REG, BIT_MIU_SELECT_MASK); ++ dma_DMAAddr -= MSTAR_MIU0_BUS_BASE; ++ ++ return ((U32)dma_DMAAddr); ++} ++ ++#endif ++/* ++void eMMC_Invalidate_data_cache_buffer(U32 u32_addr, S32 s32_size) ++{ ++ flush_cache(u32_addr, s32_size); ++} ++ ++void eMMC_flush_miu_pipe(void) ++{ ++ ++} ++*/ ++ ++ ++//--------------------------------------- ++#if defined(ENABLE_eMMC_INTERRUPT_MODE)&&ENABLE_eMMC_INTERRUPT_MODE ++ ++static DECLARE_WAIT_QUEUE_HEAD(fcie_wait); ++static volatile U32 fcie_int = 0; ++ ++#define eMMC_IRQ_DEBUG 0 ++ ++irqreturn_t eMMC_FCIE_IRQ(int irq, void *dummy) ++{ ++ volatile u16 u16_Events; ++ ++ // one time enable one bit ++ ++ REG_FCIE_R(FCIE_PWR_SAVE_CTL, u16_Events); ++ ++ if(u16_Events & BIT_POWER_SAVE_MODE_INT) ++ { ++ REG_FCIE_CLRBIT(FCIE_PWR_SAVE_CTL, BIT_POWER_SAVE_MODE_INT_EN); ++ fcie_int = 1; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,0, "SAR5 eMMC WARN.\n"); ++ while(1); ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ ++ if((REG_FCIE(FCIE_MIE_FUNC_CTL) & BIT_EMMC_ACTIVE) != BIT_EMMC_ACTIVE) ++ { ++ return IRQ_NONE; ++ } ++ ++ u16_Events = REG_FCIE(FCIE_MIE_EVENT) & REG_FCIE(FCIE_MIE_INT_EN); ++ ++ if(u16_Events & (BIT_DMA_END|BIT_ERR_STS)) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, (BIT_DMA_END|BIT_ERR_STS)); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ else if(u16_Events & BIT_CMD_END) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_CMD_END); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ return IRQ_HANDLED; ++ } ++ #if defined(ENABLE_FCIE_HW_BUSY_CHECK)&&ENABLE_FCIE_HW_BUSY_CHECK ++ else if(u16_Events & BIT_BUSY_END_INT) ++ { ++ REG_FCIE_CLRBIT(FCIE_MIE_INT_EN, BIT_BUSY_END_INT); ++ REG_FCIE_CLRBIT(FCIE_SD_CTRL, BIT_BUSY_DET_ON); ++ ++ fcie_int = 1; ++ wake_up(&fcie_wait); ++ ++ return IRQ_HANDLED; ++ } ++ #endif ++ ++ ++ #if eMMC_IRQ_DEBUG ++ if(0==fcie_int) ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Warn: Int St:%Xh, En:%Xh, Evt:%Xh \n", ++ REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), u16_Events); ++ #endif ++ ++ return IRQ_NONE; ++} ++ ++ ++U32 eMMC_WaitCompleteIntr(uintptr_t u32_RegAddr, U16 u16_WaitEvent, U32 u32_MicroSec) ++{ ++ U32 u32_i=0; ++ ++ #if eMMC_IRQ_DEBUG ++ U32 u32_isr_tmp[2]; ++ unsigned long long u64_jiffies_tmp, u64_jiffies_now; ++ struct timeval time_st; ++ time_t sec_tmp; ++ suseconds_t us_tmp; ++ ++ u32_isr_tmp[0] = fcie_int; ++ do_gettimeofday(&time_st); ++ sec_tmp = time_st.tv_sec; ++ us_tmp = time_st.tv_usec; ++ u64_jiffies_tmp = jiffies_64; ++ #endif ++ ++ //---------------------------------------- ++ if(wait_event_timeout(fcie_wait, (fcie_int == 1), usecs_to_jiffies(u32_MicroSec)) == 0) ++ { ++ #if eMMC_IRQ_DEBUG ++ u32_isr_tmp[1] = fcie_int; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh, ISR:%u->%u->%u \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN), ++ u32_isr_tmp[0], u32_isr_tmp[1], fcie_int); ++ ++ do_gettimeofday(&time_st); ++ u64_jiffies_now = jiffies_64; ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ " PassTime: %lu s, %lu us, %llu jiffies. WaitTime: %u us, %lu jiffies, HZ:%u.\n", ++ time_st.tv_sec-sec_tmp, time_st.tv_usec-us_tmp, u64_jiffies_now-u64_jiffies_tmp, ++ u32_MicroSec, usecs_to_jiffies(u32_MicroSec), HZ); ++ #else ++ eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1, ++ "eMMC Warn: int timeout, WaitEvt:%Xh, NowEvt:%Xh, IntEn:%Xh \n", ++ u16_WaitEvent, REG_FCIE(FCIE_MIE_EVENT), REG_FCIE(FCIE_MIE_INT_EN)); ++ #endif ++ ++ // switch to polling ++ for(u32_i=0; u32_i ++//extern struct semaphore PfModeSem; ++extern struct mutex FCIE3_mutex; ++//#define CRIT_SECT_BEGIN(x) mutex_lock(x) ++//#define CRIT_SECT_END(x) mutex_unlock(x) ++ ++extern bool ms_sdmmc_wait_d0_for_emmc(void); ++ ++void eMMC_LockFCIE(U8 *pu8_str) ++{ ++ mutex_lock(&FCIE3_mutex); ++ #if defined (CONFIG_OF) ++ { ++ int i; ++ for(i = 0 ;i < clkdata->num_parents; i ++) ++ clk_prepare_enable(clkdata->clk_fcie[i]); ++ } ++ #endif ++ ++ #if IF_FCIE_SHARE_IP // && defined(CONFIG_MS_SDMMC) ++// if(false == ms_sdmmc_wait_d0_for_emmc()) ++// { ++// eMMC_debug(eMMC_DEBUG_LEVEL_ERROR,1,"eMMC Err: SD keep D0 low \n"); ++// eMMC_FCIE_ErrHandler_Stop(); ++// } ++ ++ REG_FCIE_CLRBIT(FCIE_TEST_MODE, BIT_DEBUG_MODE_MASK); ++ REG_FCIE_SETBIT(FCIE_TEST_MODE, 2<num_parents; i ++) ++ clk_disable_unprepare(clkdata->clk_fcie[i]); ++ } ++ #endif ++ ++ mutex_unlock(&FCIE3_mutex); ++} ++ ++U32 eMMC_PlatformResetPre(void) ++{ ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++U32 eMMC_PlatformResetPost(void) ++{ ++ #if defined(ENABLE_EMMC_POWER_SAVING_MODE) && ENABLE_EMMC_POWER_SAVING_MODE ++ eMMC_Prepare_Power_Saving_Mode_Queue(); ++ #endif ++ ++ return eMMC_ST_SUCCESS; ++} ++struct page *eMMC_SectorPage = 0; ++struct page *eMMC_PartInfoPage = 0; ++U8 *gau8_eMMC_SectorBuf = 0; // 512 bytes ++U8 *gau8_eMMC_PartInfoBuf =0; // 512 bytes ++ ++U32 eMMC_PlatformInit(void) ++{ ++ eMMC_pads_switch(EMMC_DEFO_SPEED_MODE); ++ eMMC_clock_setting(FCIE_SLOWEST_CLK); ++ ++ if(gau8_eMMC_SectorBuf == NULL) ++ { ++ eMMC_SectorPage = alloc_pages(__GFP_COMP, 2); ++ if(eMMC_SectorPage ==NULL) ++ { ++ eMMC_debug(0, 1, "Err allocate page 1 fails\n"); ++ eMMC_die(); ++ } ++ gau8_eMMC_SectorBuf =(U8*) kmap(eMMC_SectorPage); ++ } ++ ++ if(gau8_eMMC_PartInfoBuf == NULL) ++ { ++ eMMC_PartInfoPage = alloc_pages(__GFP_COMP, 0); ++ if(eMMC_PartInfoPage ==NULL) ++ { ++ eMMC_debug(0, 1, "Err allocate page 2 fails\n"); ++ eMMC_die(); ++ } ++ gau8_eMMC_PartInfoBuf = (U8*)kmap(eMMC_PartInfoPage); ++ } ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_WR(U8 *pDataBuf, U16 u16_PartType, U32 u32_StartSector, U32 u32_SectorCnt, U8 u8_OP) ++{ ++ return eMMC_ST_SUCCESS; ++} ++ ++ ++U32 eMMC_BootPartitionHandler_E(U16 u16_PartType) ++{ ++ return eMMC_ST_SUCCESS; ++} ++ ++// -------------------------------------------- ++static U32 sgu32_MemGuard0 = 0xA55A; ++eMMC_ALIGN0 eMMC_DRIVER g_eMMCDrv eMMC_ALIGN1; ++static U32 sgu32_MemGuard1 = 0x1289; ++ ++U32 eMMC_CheckIfMemCorrupt(void) ++{ ++ if(0xA55A != sgu32_MemGuard0 || 0x1289 != sgu32_MemGuard1) ++ return eMMC_ST_ERR_MEM_CORRUPT; ++ ++ return eMMC_ST_SUCCESS; ++} ++ ++int mstar_mci_Housekeep(void *pData) ++{ ++ #if !(defined(eMMC_HOUSEKEEP_THREAD) && eMMC_HOUSEKEEP_THREAD) ++ return 0; ++ #endif ++ ++ ++ ++ while(1) ++ { ++ if(kthread_should_stop()) ++ break; ++ } ++ ++ return 0; ++} ++ ++U32 eMMC_PlatformDeinit(void) ++{ ++ return eMMC_ST_SUCCESS; ++} ++ ++#else ++ ++ ++ #error "Error! no platform functions." ++#endif ++#endif +diff --git a/drivers/mstar/fb/Kconfig b/drivers/mstar/fb/Kconfig +new file mode 100644 +index 00000000..86156dde +--- /dev/null ++++ b/drivers/mstar/fb/Kconfig +@@ -0,0 +1,28 @@ ++config MS_FB ++ tristate "FB driver" ++ default y ++ select FB ++ select FB_SYS_FILLRECT ++ select FB_SYS_COPYAREA ++ select FB_SYS_IMAGEBLIT ++ select FB_SYS_FOPS ++ help ++ ++config MS_FB_CEDRIC ++ tristate "FB driver support for Cedric" ++ depends on MS_FB ++ depends on ARCH_CEDRIC ++ ++config MS_FB_CHICAGO ++ tristate "FB driver support for Chicago" ++ depends on MS_FB ++ depends on ARCH_CHICAGO ++ ++config MS_FB_INFINITY ++ tristate "FB driver support for iNfinity" ++ depends on MS_FB ++ depends on ARCH_INFINITY ++config MS_FB_INFINITY3 ++ tristate "FB driver (GOP0) support for iNfinity3" ++ depends on MS_FB ++ depends on ARCH_INFINITY3 +\ No newline at end of file +diff --git a/drivers/mstar/fb/Makefile b/drivers/mstar/fb/Makefile +new file mode 100644 +index 00000000..8fe703d3 +--- /dev/null ++++ b/drivers/mstar/fb/Makefile +@@ -0,0 +1,4 @@ ++obj-$(CONFIG_MS_FB_CEDRIC) += cedric/ ++obj-$(CONFIG_MS_FB_CHICAGO) += chicago/ ++obj-$(CONFIG_MS_FB_INFINITY) += infinity/ ++obj-$(CONFIG_MS_FB_INFINITY3) += infinity3/ +diff --git a/drivers/mstar/fb/cedric/Makefile b/drivers/mstar/fb/cedric/Makefile +new file mode 100644 +index 00000000..80cc6aa9 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/Makefile +@@ -0,0 +1,21 @@ ++# ++# Makefile for MStar fb device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++#--------gop-------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/gop ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/gop/hal ++#--------ge--------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/ge ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/ge/columbus2 ++ ++#EXTRA_CFLAGS += -Idrivers/mstar/gfx ++ ++# specific options ++EXTRA_CFLAGS += ++ ++# files ++obj-$(CONFIG_MS_FB_CEDRIC) += gop/mdrv_gop_io.o ++obj-$(CONFIG_MS_FB_CEDRIC) += gop/mdrv_gop.o ++obj-$(CONFIG_MS_FB_CEDRIC) += mdrv_fb.o +diff --git a/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge.c b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge.c +new file mode 100644 +index 00000000..49df2858 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge.c +@@ -0,0 +1,2430 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// File name: drvGE.c ++// Description: GR driver implementation. ++// 1. PE part : piexl engine ++// 2. Blt part : fast blt engine ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++//---------------------------------------------------------------------------- ++// Include Files ++//---------------------------------------------------------------------------- ++ ++#include ++#include /* printk() */ ++#include ++#include ++#include ++ ++ ++#include "mach/ms_types.h" ++#include "mhal_ge_reg.h" ++#include "mhal_ge.h" ++#include "mhal_ge_fp.h" ++ ++//---------------------------------------------------------------------------- ++// Compile options ++//---------------------------------------------------------------------------- ++// #define GE_DEBUG ++ ++//---------------------------------------------------------------------------- ++// Local Defines ++//---------------------------------------------------------------------------- ++#define WAIT_CMD_FIFO 1 ++#if WAIT_CMD_FIFO ++#define PATCH_RD_CMD 1 ++#else ++#define PATCH_RD_CMD 0 ++#endif ++ ++//---------------------------------------------------------------------------- ++// Debug Macros ++//---------------------------------------------------------------------------- ++#define GE_DEBUGINFO(x) //x ++#define GE_WARN(x) printk(KERN_WARNING x); ++ ++ //#undef GE_DEBUG ++// #define GE_DEBUG ++ ++#ifdef GE_DEBUG ++#define GE_ASSERT(_bool, _f) if (!(_bool)) { (_f); while (1) printk("G0"); } ++#else ++#define GE_ASSERT(_bool, _f) while (0) ++#endif // #ifdef SCL_DEBUG ++ ++#ifdef GE_DEBUG ++ ++#define _GE_CHECK_BUFFER_ALIGN0(addr, color_fmt) \ ++ switch ((color_fmt)){ \ ++ case GE_FMT_I1: \ ++ case GE_FMT_I2: \ ++ case GE_FMT_I4: \ ++ case GE_FMT_I8: \ ++ break; \ ++ case GE_FMT_YUV422: \ ++ case GE_FMT_1ABFGBG12355: \ ++ case GE_FMT_RGB565 : \ ++ case GE_FMT_ARGB1555 : \ ++ case GE_FMT_ARGB4444 : \ ++ GE_ASSERT(!(0x1 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ break; \ ++ case GE_FMT_ARGB8888 : \ ++ GE_ASSERT(!(0x3 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ break; \ ++ default: \ ++ GE_ASSERT(0, printk("[GE DRV][%06d] Invalid color format\n")); \ ++ break; \ ++ } ++ ++ ++#define _GE_CHECK_BUFFER_ALIGN1(addr, width, height, pitch, color_fmt) \ ++ switch ((color_fmt)){ \ ++ case GE_FMT_I1: \ ++ case GE_FMT_I2: \ ++ case GE_FMT_I4: \ ++ case GE_FMT_I8: \ ++ break; \ ++ case GE_FMT_YUV422: \ ++ case GE_FMT_1ABFGBG12355: \ ++ case GE_FMT_RGB565 : \ ++ case GE_FMT_ARGB1555 : \ ++ case GE_FMT_ARGB4444 : \ ++ GE_ASSERT(!(0x1 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ GE_ASSERT(!(0x1 & (pitch)), printk("[GE DRV][%06d] Bad buffer pitch (%d, %d)\n", (pitch), (color_fmt))); \ ++ GE_ASSERT(((pitch)>>1)== (width), printk("[GE DRV][%06d] Bad buffer pitch/width (%d, %d)\n", (pitch), (width))); \ ++ break; \ ++ case GE_FMT_ARGB8888 : \ ++ GE_ASSERT(!(0x3 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ GE_ASSERT(!(0x3 & (pitch)), printk("[GE DRV][%06d] Bad buffer pitch (%d, %d)\n", (pitch), (color_fmt))); \ ++ GE_ASSERT(((pitch)>>2)== (width), printk("8888[GE DRV][%06d] Bad buffer pitch/width (%d, %d)\n", (pitch), (width))); \ ++ break; \ ++ default: \ ++ GE_ASSERT(0, printk("[GE DRV][%06d] Invalid color format\n")); \ ++ break; \ ++ } ++ ++#define _GE_SIMPLE_BB_CHECK() \ ++ GE_WaitAvailableCMDQueue(32); \ ++ if (!(GE_VAL_EN_STRETCH_BITBLT & GE_ReadReg(GE_REG_FMT_BLT))) \ ++ { \ ++ if (GE_ReadReg(GE_REG_STBB_INIT_DX) || GE_ReadReg(GE_REG_STBB_INIT_DY)) \ ++ { \ ++ while (1)printk("G1"); \ ++ } \ ++ if (GE_ReadReg(GE_REG_STBB_WIDTH)!= (GE_ReadReg(GE_REG_PRI_V1_X)- GE_ReadReg(GE_REG_PRI_V0_X)+ 1)) \ ++ { \ ++ while (1)printk("G2"); \ ++ } \ ++ if (GE_ReadReg(GE_REG_STBB_HEIGHT)!= (GE_ReadReg(GE_REG_PRI_V1_Y)- GE_ReadReg(GE_REG_PRI_V0_Y)+ 1)) \ ++ { \ ++ while (1)printk("G3"); \ ++ } \ ++ } ++ ++#else // #ifdef GE_DEBUG ++ ++#define _GE_CHECK_BUFFER_ALIGN0(addr, color_fmt) while (0); ++#define _GE_CHECK_BUFFER_ALIGN1(addr, width, height, pitch, color_fmt) while (0); ++#define _GE_SIMPLE_BB_CHECK() while (0); ++ ++#endif // #ifdef GE_DEBUG ++ ++//---------------------------------------------------------------------------- ++// Macros ++//---------------------------------------------------------------------------- ++#define delay(ms) ++ ++#if 1 ++#define GE_WaitCmdEmpty() while(((GE_Reg(GE_REG_STATUS)) & GE_MSK_CMQ_FIFO_STATUS) != 0x80) ++#define GE_WaitCmdNotFull() while ((GE_Reg(GE_REG_STATUS) & GE_MSK_CMQ_FIFO_STATUS)== 0x00) ++#else ++#define GE_WaitCmdEmpty ++#define GE_WaitCmdNotFull ++#endif ++ ++ ++//---------------------------------------------------------------------------- ++// Global Variables ++//---------------------------------------------------------------------------- ++ ++DEFINE_SEMAPHORE(g_GESem); ++ ++#ifdef DBGLOG ++//debug use only ++static U16 _bOutFileLog = false; ++static U16 *_pu16OutLogAddr = NULL; ++static U16 _u16LogCount=0; ++#endif ++ ++static U32 _u32Reg60hFlag = 0; ++#if PATCH_RD_CMD ++static U32 _u32Reg0hValue = 0; ++#endif ++static U16 _u16PeClipX1 = 0; ++static U16 _u16PeClipX2 = 0; ++static U16 _u16PeClipY1 = 0; ++static U16 _u16PeClipY2 = 0; ++ ++static U8 _u8TypeGE[32] = "MstarTypeGE"; ++ ++//---------------------------------------------------------------------------- ++// Local Function Prototypes ++//---------------------------------------------------------------------------- ++void GE_ConvertRGB2DBFmt(GE_Buffer_Format Fmt, U32 *color, U16* low, U16* high); ++// void BLT_ConvertRGB2DBFmt(GE_Buffer_Format Fmt, U32 *colorinfo, U16* low, U16* high); ++ ++//------------------------------------------------------------------------------------------------- ++static U32 GE_ReadReg(U32 addr) ++{ ++ return GE_Reg(addr); ++} ++ ++//------------------------------------------------------------------------------------------------- ++static void GE_WaitAvailableCMDQueue(U8 u8CMDCount) ++{ ++#if WAIT_CMD_FIFO ++ U32 wait_count= 1; ++ unsigned int tt ; ++ u8CMDCount = 32 ; ++ u8CMDCount = (u8CMDCount > 32)? 32 : u8CMDCount; ++ ++ //Note: In Titania, 1 empty count can save 2 commands. ++ // And if the empty item only saves 1 commands, it is treated as empty; ++ // therefore 15 cmmands will need (15+1)/2 empty items. ++ u8CMDCount = ((u8CMDCount + 1)>>1); ++ ++ ++ // check GE busy status to avoid command queue bug ++ tt = 0 ; ++ while (((GE_Reg(GE_REG_STATUS)&0x01))) ++ { ++ //msleep(2) ; ++ tt++ ; ++ if( (tt&0xFFFFFF)==0 ) ++ printk("G5 ") ; ++ } ++ ++ while (((GE_Reg(GE_REG_STATUS)&GE_MSK_CMQ_FIFO_STATUS)>>2) < u8CMDCount) ++ { ++ if (0x0000== (0xFFF & wait_count)) ++ { ++ printk("[GE INFO] GE wait command queue\n"); ++ } ++ wait_count++; ++ } ++#endif ++} ++ ++void outGE_WaitAvailableCMDQueue(void){ ++ GE_WaitAvailableCMDQueue(32) ; ++} ++ ++static void GE_WriteReg(U32 u32addr, U32 u32val) ++{ ++#if WAIT_CMD_FIFO ++ // Wait GE command queue empty before fire to avoid GE hang ++ if (GE_REG_CMD== u32addr) ++ { ++ GE_WaitAvailableCMDQueue(32); ++ } ++ ++ GE_Reg(u32addr)=u32val; ++#else ++ GE_Reg(u32addr)=u32val; ++ if ((u32addr == GE_REG_CMD)&&(GE_Reg(GE_REG_EN)& GE_VAL_EN_PE)) ++ { ++ while ( GE_Reg(GE_REG_STATUS)& GE_VAL_BUSY) ++ { ++ MsOS_YieldTask(); ++ } ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++static U16 GE_CheckInClipWindow(U16 u16X1, U16 u16Y1, U16 u16X2, U16 u16Y2) ++{ ++ if (((u16X1 < _u16PeClipX1) && (u16X2 < _u16PeClipX1)) || ++ ((u16X1 > _u16PeClipX2) && (u16X2 > _u16PeClipX2)) || ++ ((u16Y1 < _u16PeClipY1) && (u16Y2 < _u16PeClipY1)) || ++ ((u16Y1 > _u16PeClipY2) && (u16Y2 > _u16PeClipY2))) ++ { ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Description: for debug output register log use ++// Arguments: enable - true or false ++// ++// Return: NONE ++// ++// Notes: if any ++//------------------------------------------------------------------------------------------------- ++void MHal_GE_Debug_SetOutputLog(U16 enable) ++{ ++#ifdef DBGLOG ++ _bOutFileLog = enable; ++ if (enable) ++ { ++ _pu16OutLogAddr = (U16 *)GE_LOG_ADR; ++ memset(_pu16OutLogAddr, 0, 0x100000); ++ //write header ++ *_pu16OutLogAddr = 0xffff; ++ _pu16OutLogAddr++; ++ *_pu16OutLogAddr = 0x55AA; ++ _pu16OutLogAddr++; ++ _u16LogCount =2; ++ } ++ else ++ { ++ *_pu16OutLogAddr = 0xffff; ++ _pu16OutLogAddr++; ++ *_pu16OutLogAddr = _u16LogCount; ++ _pu16OutLogAddr++; ++ _u16LogCount = 0; ++ } ++#endif ++} ++ ++static void GE_Enable_CmdQ(void) ++{ ++ GE_WriteReg(GE_REG_FMT_BLT, GE_VAL_EN_CMDQ); ++} ++ ++static void GE_Register_Reset(void) ++{ ++/* ++#if 1 ++ GE_WaitAvailableCMDQueue(32); ++#else ++ while (((GE_Reg(GE_REG_STATUS) & GE_VAL_BUSY))){ ++ MsOS_YieldTask(); ++ } ++ while (((GE_Reg(GE_REG_STATUS) & 0xfc)>>2) < 32) ++ { ++ MsOS_YieldTask(); ++ } ++#endif ++*/ ++ ++ // GE_WriteReg(GE_REG_EN, 0); ++ GE_WriteReg(GE_REG_EN, GE_VAL_EN_PE); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = GE_VAL_EN_PE; ++#endif ++ ++ GE_WriteReg(GE_REG_STBB_TH, 0x08); ++ ++ //Set Line pattern to default. ++ //GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ //GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ _u32Reg60hFlag = 0; ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Begin PE Engine drawing, this function should be called before all PE drawing function, ++/// and it will lock PE engine resource, reset all PE register and static variable. ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_BeginDraw(void) ++{ ++ down(&g_GESem); ++ ++ GE_DEBUGINFO(printk( "MHal_GE_BeginDraw\n")); ++ ++#ifdef DYNAMIC_POWER_ON_OFF ++ MDrv_Power_ClockTurnOn(E_POWER_MODULE_GE); ++#endif ++ ++ GE_Register_Reset(); ++ ++ return GESTATUS_SUCCESS; ++} ++//------------------------------------------------------------------------------------------------- ++/// Initial PE engine ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MHal_GE_Init(void) ++{ ++ GE_DEBUGINFO(printk( "MHal_GE_Init\n")); ++ ++#ifdef MOVE_TO_USER_SPACE ++#ifdef DYNAMIC_POWER_ON_OFF ++ MDrv_Power_ClockTurnOn(E_POWER_MODULE_GE); ++#endif ++#endif ++ ++ GE_Enable_CmdQ(); ++ ++ GE_WriteReg(GE_REG_SCK_LTH0, *(U32*)&_u8TypeGE[0]); ++ GE_WriteReg(GE_REG_SCK_LTH1, *(U32*)&_u8TypeGE[4]); ++ GE_WriteReg(GE_REG_SCK_HTH0, *(U32*)&_u8TypeGE[8]); ++ GE_WriteReg(GE_REG_SCK_HTH1, *(U32*)&_u8TypeGE[12]); ++ ++#ifdef DYNAMIC_POWER_ON_OFF ++ while ( GE_Reg(GE_REG_STATUS)& GE_VAL_BUSY); ++#if MOVE_TO_USER_SPACE ++ MDrv_Power_ClockTurnOff(E_POWER_MODULE_GE); ++#endif ++#endif ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// End PE engine drawing (pair with MHal_GE_BeginDraw), this function should be called after ++/// all PE drawing function. And it will release PE engine resource. ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_EndDraw(void) ++{ ++#ifdef DYNAMIC_POWER_ON_OFF ++ GE_WaitAvailableCMDQueue(32); ++ while (GE_Reg(GE_REG_STATUS)& GE_VAL_BUSY) ++ { ++ MsOS_YieldTask(); ++ } ++ MDrv_Power_ClockTurnOff(E_POWER_MODULE_GE); ++#endif ++ ++ up(&g_GESem); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE Engine dither ++/// @param enable \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetDither(U16 enable) ++{ ++ U32 u32Value; ++ ++ GE_DEBUGINFO(printk("MDrv_SetDither\n")); ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_DITHER; ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_DITHER; ++ } ++ ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE source color key ++/// @param enable \b IN: true/false\n ++/// When enable is FALSE, do not care the other parameters.\n ++/// @param opMode \b IN: source color key mode ++/// The alpha channel does not matter\n ++/// @param fmt \b IN: source color key format ++/// @param ps_color \b IN: pointer of source color key start (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// For all RGB color, the color set as the ARGB8888 format.\n ++/// Each color component need to shift to high bit.\n ++/// Use ARGB1555 as the example, the source color key as the following:\n ++/// ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++/// *ps_color --> A0000000RRRRR000GGGGG000BBBBB000 (every character represents one bit)\n\n ++/// For GE_FMT_I8 format, the index set to b component (ps_color->b = b).\n ++/// For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++/// @param pe_color \b IN: pointer of source color key end (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetSrcColorKey(U16 enable, ++ GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, ++ void *ps_color, ++ void *pe_color) ++{ ++ U32 u32Value, u32Value2; ++ U16 u16Color0, u16Color1; ++ ++ GE_DEBUGINFO(printk("MHal_GE_SetSrcColorKey\n")); ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_SCK; ++ ++ // Color key threshold ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)ps_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_SCK_LTH0, u16Color0); ++ GE_WriteReg(GE_REG_SCK_LTH1, u16Color1); ++ ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)pe_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_SCK_HTH0, u16Color0); ++ GE_WriteReg(GE_REG_SCK_HTH1, u16Color1); ++ ++ // Color op ++ u32Value2 = GE_ReadReg(GE_REG_KEY_OP); ++ u32Value2 = (u32Value2 & ~GE_VAL_SCK_OP_TRUE) | opMode; ++ GE_WriteReg(GE_REG_KEY_OP, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~(GE_VAL_EN_SCK); ++ } ++ ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE destination color key ++/// @param enable \b IN: true/false\n ++/// When enable is FALSE, do not care the other parameters.\n ++/// @param opMode \b IN: destination color key mode\n ++/// The alpha channel does not matter\n ++/// @param fmt \b IN: destination color key format ++/// @param ps_color \b IN: pointer of destination color key start (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// For all RGB color, the color set as the ARGB8888 format.\n ++/// Each color component need to shift to high bit.\n ++/// Use ARGB1555 as the example, the source color key as the following:\n ++/// ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++/// *ps_color --> A0000000RRRRR000GGGGG000BBBBBB000 (every character represents one bit)\n\n ++/// For GE_FMT_I8 format, the index set to b component (ps_color->b = b).\n ++/// For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++/// @param pe_color \b IN: pointer of destination color key end (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetDstColorKey(U16 enable, ++ GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, ++ void *ps_color, ++ void *pe_color) ++{ ++ U32 u32Value, u32Value2; ++ U16 u16Color0, u16Color1; ++ ++ GE_DEBUGINFO(printk("MHal_GE_SetDstColorKey\n")); ++ ++ GE_WaitAvailableCMDQueue(8); ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_DCK; ++ ++ // Color key threshold ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)ps_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_DCK_LTH0, u16Color0); ++ GE_WriteReg(GE_REG_DCK_LTH1, u16Color1); ++ ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)pe_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_DCK_HTH0, u16Color0); ++ GE_WriteReg(GE_REG_DCK_HTH1, u16Color1); ++ ++ // Color op ++ u32Value2 = GE_ReadReg(GE_REG_KEY_OP); ++ u32Value2 = (u32Value2 & ~GE_VAL_DCK_OP_TRUE) | (opMode<<1); ++ GE_WriteReg(GE_REG_KEY_OP, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_DCK; ++ } ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE intensity : total 16 color Palette in PE ++/// @param id \b IN: id of intensity ++/// @param fmt \b IN: intensity color format (GE_FMT_ARGB8888 , GE_FMT_1BAAFGBG123433 or GE_FMT_I8) ++/// @param pColor \b IN: pointer of intensity (GE_RGB_COLOR or GE_BLINK_DATA depend on color format) ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @return GESTATUS_INVALID_INTENSITY_ID - Inavlid index (id >= 16) ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetIntensity(U32 id, GE_Buffer_Format fmt, U32 *pColor) ++{ ++ U16 u16Color0, u16Color1; ++ GE_DEBUGINFO(printk("MHal_GE_SetIntensity\n")); ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++ if (id < GE_INTENSITY_NUM) ++ { ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)pColor, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_I0_C0 + (2*id), u16Color0); ++ GE_WriteReg(GE_REG_I0_C1 + (2*id), u16Color1); ++ } ++ else ++ { ++ return GESTATUS_INVALID_INTENSITY_ID; ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE raster operation ++/// @param enable \b IN: true/false ++/// @param eRopMode \b IN: raster operation ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetROP2(U16 enable, GE_ROP2_OP eRopMode) ++{ ++ U32 u32Value, u32Value2; ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_ROP; ++ ++ u32Value2 = GE_ReadReg(GE_REG_ROP2); ++ u32Value2 = (u32Value2 & ~GE_MSK_ROP2) | eRopMode; ++ GE_WriteReg(GE_REG_ROP2, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_ROP; ++ } ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++void dummyRegWrite( void ){ ++ GE_WriteReg(GE_REG_STBB_WIDTH, GE_ReadReg(GE_REG_STBB_WIDTH)); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Force PE draw line ++/// @param pline \b IN: pointer to line info ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_DrawLine(GE_DRAW_LINE_INFO *pline) ++{ ++ U32 u32Start, u32End; ++ U32 u32Width, u32Height, u32Ratio; ++ U32 u32Value, u32Value2; ++ U32 u32X1, u32X2, u32Y1, u32Y2; ++ S32 i; ++ S16 s16Dif; ++ U16 bYMajor = false; ++ U16 bInverse = false; ++ U16 u16Color0, u16Color1; ++ GE_RGB_COLOR color_s, color_e; ++ GE_BLINK_DATA *blinkData = NULL; ++ ++ GE_DEBUGINFO( printk("MHal_GE_DrawLine\n")); ++ ++ GE_WaitAvailableCMDQueue(24); ++ ++ if ((!GE_CheckInClipWindow(pline->x1, pline->y1, pline->x2, pline->y2)) && (pline->width == 1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ ++ u32X1 = pline->x1; ++ u32X2 = pline->x2; ++ u32Y1 = pline->y1; ++ u32Y2 = pline->y2; ++ ++ u32Width = u32X2 - u32X1 ; ++ u32Height = u32Y2 - u32Y1 ; ++ color_s = pline->colorRange.color_s; ++ color_e = pline->colorRange.color_e; ++ ++ if ( u32Y1 > u32Y2 ) ++ { ++ u32Height = u32Y1 - u32Y2; ++ } ++ ++ if ( u32X1 > u32X2 ) ++ { ++ u32Width = u32X1 - u32X2; ++ } ++ ++ ++ u32Value2 = GE_VAL_PRIM_LINE; ++ ++ if( (u32Height >= u32Width)||(u32Width==0)) ++ { ++ bYMajor = true; ++ } ++ ++ if (bYMajor) ++ { ++ if (pline->x1 >= pline->x2) ++ { ++ if (!GE_CheckInClipWindow(pline->x1+pline->width, pline->y1, pline->x2, pline->y2)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ else ++ { ++ if (!GE_CheckInClipWindow(pline->x1, pline->y1, pline->x2+pline->width, pline->y2)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ if (pline->y1 >= pline->y2) ++ { ++ if (!GE_CheckInClipWindow(pline->x1, pline->y1+pline->width, pline->x2, pline->y2)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ else ++ { ++ if (!GE_CheckInClipWindow(pline->x1, pline->y1, pline->x2, pline->y2+pline->width)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ } ++/* ++ if ( bYMajor ) ++ { ++ if ( u32X1 > u32X2) ++ { ++ u32X1 = pline->x2; ++ u32X2 = pline->x1; ++ u32Y1 = pline->y2; ++ u32Y2 = pline->y1; ++ bInverse = true; ++ } ++ if ( u32Y1 > u32Y2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; ++ } ++ else ++ { ++ if ( u32Y1 > u32Y2) ++ { ++ u32X1 = pline->x2; ++ u32X2 = pline->x1; ++ u32Y1 = pline->y2; ++ u32Y2 = pline->y1; ++ bInverse = true; ++ } ++ if ( u32X1 > u32X2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; ++ } ++*/ ++ if ( bYMajor ) ++ { ++ if ( u32X1 > u32X2) ++ { ++ bInverse = true; ++ } ++ if ( u32Y1 > u32Y2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; // @FIXME: Richard: should be Y NEG??? ++ } ++ else ++ { ++ if ( u32Y1 > u32Y2) ++ { ++ bInverse = true; ++ } ++ if ( u32X1 > u32X2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; ++ } ++ ++ if ((u32Width==0)||(u32Height==0)) ++ { ++ u32Value = 0; ++ } ++ else ++ { ++ ++ if ( bYMajor ) ++ { ++ if (bInverse) ++ { ++ u32Value = (0x4000 - (U16)Divide2Fixed(u32Width, u32Height, 1, 12)) << 1; //sc ++ } ++ else ++ { ++ u32Value = (U16)Divide2Fixed(u32Width, u32Height, 1, 12) << 1; //sc ++ } ++ bInverse = FALSE; ++ } ++ else ++ { ++ if (bInverse) ++ { ++ u32Value = (0x4000 - (U16)Divide2Fixed(u32Height, u32Width, 1, 12)) << 1; //sc ++ } ++ else ++ { ++ u32Value = (U16)Divide2Fixed(u32Height, u32Width, 1, 12) << 1; //sc ++ } ++ bInverse = FALSE; ++ } ++ } ++ ++ if ( bYMajor ) ++ { ++ GE_WriteReg(GE_REG_LINE_DTA, (u32Value & GE_MSK_LINE_DTA )|GE_VAL_LINE_Y_MAJOR); ++ } ++ else ++ { ++ GE_WriteReg(GE_REG_LINE_DTA, (u32Value & GE_MSK_LINE_DTA )); ++ } ++ ++ // Start color ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355!= pline->fmt) ++ // if (pline->fmt != GE_FMT_1BAAFGBG123433) ++ { ++ GE_ConvertRGB2DBFmt(pline->fmt, (U32*)&color_s, &u16Color0, &u16Color1); ++ } ++ else ++ { ++#if 0 ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ // 1 A B Fg Bg ++ // 1 2 3 5 5 ++ // ++ // 1 B A A Fg Bg ++ // 1 2 3 4 3 3 ++ ++ blinkData =(GE_BLINK_DATA *)&color_s; ++ u16Color0 = ((((blinkData->background&0x7) | ((blinkData->foreground&0x7)<<3))<<2) | ((blinkData->Bits.BlinkAlpha&0xf)<<12)); ++ u16Color1 = (0xff00 | ((((blinkData->Bits.Blink&0x3)<<3) | (blinkData->Bits.Alpha&0x7))<<3)); ++#else ++ blinkData= (GE_BLINK_DATA *)&color_s; ++ u16Color0= (0x1F & blinkData->background) | ++ ((0x1F & blinkData->foreground) << 8); ++ u16Color1= (0x7 & blinkData->Bits.Blink) | ++ ((0x3 & blinkData->Bits.Alpha) << 3) | ++ BIT8; ++#endif ++ } ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ ++ if (bYMajor) u32Ratio = u32Height; ++ else u32Ratio = u32Width; ++ ++ if(pline->flag & GELINE_FLAG_COLOR_GRADIENT) ++ { ++ if(bInverse) ++ { ++ GE_ConvertRGB2DBFmt(pline->fmt, (U32*)&color_e, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ //GE_WriteReg(GE_REG_PRI_BG_ST, (pline->color2.b & 0xff) | ((pline->color2.g & 0xff) << 8)); ++ //GE_WriteReg(GE_REG_PRI_RA_ST, (pline->color2.r & 0xff) | ((pline->color2.a & 0xff) << 8)); ++ } ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.r - color_e.r; ++ } ++ else ++ { ++ s16Dif = color_e.r - color_s.r; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio , 7, 12); ++ GE_WriteReg(GE_REG_PRI_R_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_R_DX1, u32Value >> 16); ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.g - color_e.g; ++ } ++ else ++ { ++ s16Dif = color_e.g - color_s.g; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio, 7, 12); ++ GE_WriteReg(GE_REG_PRI_G_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_G_DX1, u32Value >> 16); ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.b - color_e.b; ++ } ++ else ++ { ++ s16Dif = color_e.b - color_s.b; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio, 7, 12); ++ GE_WriteReg(GE_REG_PRI_B_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_B_DX1, u32Value >> 16); ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.a - color_e.a; ++ } ++ else ++ { ++ s16Dif = color_e.a - color_s.a; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio, 4, 11); ++ GE_WriteReg(GE_REG_PRI_A_DX, u32Value & 0xffff); ++ ++ u32Value2 |= GE_VAL_LINE_GRADIENT; ++ } ++ ++ GE_ASSERT(0x7FF>= u32X1, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32X2, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32Y1, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32Y2, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_WriteReg(GE_REG_PRI_V0_X, u32X1); ++ GE_WriteReg(GE_REG_PRI_V1_X, u32X2); ++ GE_WriteReg(GE_REG_PRI_V0_Y, u32Y1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, u32Y2); ++ ++ if(bYMajor) ++ { ++ u32Start = u32X1; ++ u32End = u32X2; ++ for(i=0;iwidth;i++) ++ { ++ GE_WaitAvailableCMDQueue(8); ++ GE_ASSERT(0x7FF>= u32Start, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32End, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_WriteReg(GE_REG_LENGTH, u32Height); ++ GE_WriteReg(GE_REG_PRI_V0_X, u32Start); ++ GE_WriteReg(GE_REG_PRI_V1_X, u32End); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ u32Start++; ++ u32End++; ++ } ++ } ++ else ++ { ++ u32Start = u32Y1; ++ u32End = u32Y2; ++ for (i=0;iwidth;i++) ++ { ++ GE_WaitAvailableCMDQueue(8); ++ GE_ASSERT(0x7FF>= u32Start, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32End, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_WriteReg(GE_REG_LENGTH, u32Width); ++ GE_WriteReg(GE_REG_PRI_V0_Y, u32Start); ++ GE_WriteReg(GE_REG_PRI_V1_Y, u32End); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ u32Start++; ++ u32End++; ++ } ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++GESTATUS MHal_GE_DrawOval(GE_OVAL_FILL_INFO* pOval) ++{ ++ S32 x, y, c_x, c_y; ++ S32 Xchange, Ychange; ++ S32 EllipseError; ++ S32 TwoASquare, TwoBSquare; ++ S32 StoppingX, StoppingY; ++ U32 Xradius, Yradius; ++ U32 u32Value2 = 0; ++ U16 u16Color0, u16Color1; ++ GE_BLINK_DATA *blinkData = NULL; ++ ++ if (!GE_CheckInClipWindow(pOval->dstBlock.x, pOval->dstBlock.y, pOval->dstBlock.x+pOval->dstBlock.width-1, pOval->dstBlock.y+pOval->dstBlock.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++ Xradius = (pOval->dstBlock.width - pOval->u32LineWidth*2) / 2; ++ Yradius = (pOval->dstBlock.height - pOval->u32LineWidth*2) / 2; ++ ++ /* center of ellipse */ ++ //c_x = pOval->dstBlock.x + Xradius + pOval->u32LineWidth/2; ++ //c_y = pOval->dstBlock.y + Yradius + pOval->u32LineWidth/2; ++ c_x = pOval->dstBlock.x + Xradius + pOval->u32LineWidth; ++ c_y = pOval->dstBlock.y + Yradius + pOval->u32LineWidth; ++ ++ TwoASquare = 2*Xradius*Xradius; ++ TwoBSquare = 2*Yradius*Yradius; ++ ++ /*1st set of points*/ ++ x = Xradius-1; /*radius zero == draw nothing*/ ++ y = 0; ++ ++ Xchange = Yradius*Yradius*(1-2*Xradius); ++ Ychange = Xradius*Xradius; ++ ++ EllipseError = 0; ++ ++ StoppingX = TwoBSquare*Xradius; ++ StoppingY = 0; ++ ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ ++ u32Value2 = GE_VAL_PRIM_LINE; ++ GE_WriteReg(GE_REG_LINE_DTA, 0); ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355!= pOval->fmt) ++ // if (pOval->fmt != GE_FMT_1BAAFGBG123433) ++ { ++ GE_ConvertRGB2DBFmt(pOval->fmt, (U32*)&pOval->color, &u16Color0, &u16Color1); ++ } ++ else ++ { ++#if 0 ++ blinkData =(GE_BLINK_DATA *)&pOval->blink_data; ++ u16Color0 = ((((blinkData->background&0x7) | ((blinkData->foreground&0x7)<<3))<<2) | ((blinkData->Bits.BlinkAlpha&0xf)<<12)); ++ u16Color1 = (0xff00 | ((((blinkData->Bits.Blink&0x3)<<3) | (blinkData->Bits.Alpha&0x7))<<3)); ++#else ++ blinkData =(GE_BLINK_DATA *)&pOval->blink_data; ++ u16Color0= (0x1F & blinkData->background) | ++ ((0x1F & blinkData->foreground) << 8); ++ u16Color1= (0x7 & blinkData->Bits.Blink) | ++ ((0x3 & blinkData->Bits.Alpha) << 3) | ++ BIT8; ++#endif ++ } ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ ++ ++ ++ ++ /*Plot 2 ellipse scan lines for iteration*/ ++ while (StoppingX > StoppingY) ++ { ++ GE_WaitAvailableCMDQueue(16); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y + y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y + y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y - y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y - y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ ++y; ++ StoppingY += TwoASquare; ++ EllipseError += Ychange; ++ Ychange += TwoASquare; ++ if (( 2*EllipseError + Xchange) > 0) ++ { ++ --x; ++ StoppingX -= TwoBSquare; ++ EllipseError += Xchange; ++ Xchange += TwoBSquare; ++ } ++ } ++ ++ /*2nd set of points*/ ++ x = 0; ++ y = Yradius-1; /*radius zero == draw nothing*/ ++ Xchange = Yradius*Yradius; ++ Ychange = Xradius*Xradius*(1-2*Yradius); ++ EllipseError = 0; ++ StoppingX = 0; ++ StoppingY = TwoASquare*Yradius; ++ ++ /*Plot 2 ellipse scan lines for iteration*/ ++ while (StoppingX < StoppingY) ++ { ++ GE_WaitAvailableCMDQueue(16); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y + y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y + y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y - y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y - y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ ++x; ++ StoppingX += TwoBSquare; ++ EllipseError += Xchange; ++ Xchange += TwoBSquare; ++ if ((2*EllipseError + Ychange) > 0) ++ { ++ --y; ++ StoppingY -= TwoASquare; ++ EllipseError += Ychange; ++ Ychange += TwoASquare; ++ } ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Force PE rectangle fill ++/// @param pfillblock \b IN: pointer to block info ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_RectFill(GE_RECT_FILL_INFO *pfillblock) ++{ ++ S16 s16Dif; ++ U32 u32Value, u32Value2; ++ GE_RGB_COLOR color_s, color_e; ++ U16 u16Color0, u16Color1; ++ GE_BLINK_DATA *blinkData = NULL; ++ ++ ++ GE_DEBUGINFO( printk("MHal_GE_RectFill\n")); ++ ++ if((pfillblock->dstBlock.width == 0) ||(pfillblock->dstBlock.height==0)) ++ { ++ GE_DEBUGINFO(printk("MHal_GE_RectFill error!! width or height equal 0!!\n")); ++ return FALSE; ++ } ++ ++ if (!GE_CheckInClipWindow(pfillblock->dstBlock.x, pfillblock->dstBlock.y, ++ pfillblock->dstBlock.x+pfillblock->dstBlock.width-1, ++ pfillblock->dstBlock.y+pfillblock->dstBlock.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(20); ++ ++ //u32Value = GE_ReadReg(GE_REG_EN); ++ //u32Value |= GE_VAL_EN_PE; ++ //GE_WriteReg(GE_REG_EN, u32Value); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, pfillblock->dstBlock.x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, pfillblock->dstBlock.y); ++ GE_WriteReg(GE_REG_PRI_V1_X, pfillblock->dstBlock.x + pfillblock->dstBlock.width - 1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, pfillblock->dstBlock.y + pfillblock->dstBlock.height - 1); ++ ++ // Start color ++ color_s = pfillblock->colorRange.color_s; ++ color_e = pfillblock->colorRange.color_e; ++ ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355!= pfillblock->fmt) ++ // if (pfillblock->fmt != GE_FMT_1BAAFGBG123433) ++ { ++ GE_ConvertRGB2DBFmt(pfillblock->fmt, (U32*)&color_s, &u16Color0, &u16Color1); ++ } ++ else ++ { ++#if 0 ++ blinkData =(GE_BLINK_DATA *)&color_s; ++ u16Color0 = ((((blinkData->background&0x7) | ((blinkData->foreground&0x7)<<3))<<2) | ((blinkData->Bits.BlinkAlpha&0xf)<<12)); ++ u16Color1 = (0xff00 | ((((blinkData->Bits.Blink&0x3)<<3) | (blinkData->Bits.Alpha&0x7))<<3)); ++#else ++ blinkData= (GE_BLINK_DATA *)&color_s; ++ u16Color0= (0x1F & blinkData->background) | ++ ((0x1F & blinkData->foreground) << 8); ++ u16Color1= (0x7 & blinkData->Bits.Blink) | ++ ((0x3 & blinkData->Bits.Alpha) << 3) | ++ BIT8; ++#endif ++ } ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ ++ ++ GE_WriteReg(GE_REG_PRI_A_DY, 0); ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ u32Value2 = GE_VAL_PRIM_RECTANGLE; ++ ++ if((pfillblock->flag & GERECT_FLAG_COLOR_GRADIENT_Y) == GERECT_FLAG_COLOR_GRADIENT_Y) ++ { ++ s16Dif = color_e.r - color_s.r; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_R_DY0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_R_DY1, u32Value >> 16); ++ ++ s16Dif = color_e.g - color_s.g; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_G_DY0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_G_DY1, u32Value >> 16); ++ ++ s16Dif = color_e.b - color_s.b; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_B_DY0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_B_DY1, u32Value >> 16); ++ ++ s16Dif = color_e.a - color_s.a; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 4, 11); ++ GE_WriteReg(GE_REG_PRI_A_DY, u32Value & 0xffff); ++ ++ u32Value2 |= GE_VAL_RECT_GRADIENT_V; ++ } ++ if((pfillblock->flag & GERECT_FLAG_COLOR_GRADIENT_X) == GERECT_FLAG_COLOR_GRADIENT_X) ++ { ++ s16Dif = color_e.r - color_s.r; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_R_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_R_DX1, u32Value >> 16); ++ ++ s16Dif = color_e.g - color_s.g; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_G_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_G_DX1, u32Value >> 16); ++ ++ s16Dif = color_e.b - color_s.b; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_B_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_B_DX1, u32Value >> 16); ++ ++ s16Dif = color_e.a - color_s.a; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 4, 11); ++ GE_WriteReg(GE_REG_PRI_A_DX, u32Value & 0xffff); ++ ++ u32Value2 |= GE_VAL_RECT_GRADIENT_H; ++ } ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Reset PE line pattern ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_Line_Pattern_Reset(void) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++ u32Value = GE_ReadReg(GE_REG_LPT) | GE_VAL_LPT_RESET; ++ GE_WriteReg(GE_REG_LPT, u32Value); ++ ++ u32Value = GE_ReadReg(GE_REG_LPT) & (~GE_VAL_LPT_RESET); ++ GE_WriteReg(GE_REG_LPT, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE line pattern ++/// @param enable \b IN: true/false ++/// @param linePattern \b IN: p0-0x3F one bit represent draw(1) or not draw(0) ++/// @param repeatFactor \b IN: 0 : repeat once, 1 : repeat twice, 2: repeat 3, 3: repeat 4 ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_Set_Line_Pattern(U16 enable, U8 linePattern, U8 repeatFactor) ++{ ++ U32 u32Value, u32Value2; ++ ++ GE_WaitAvailableCMDQueue(6); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if (enable) ++ { ++ u32Value |= GE_VAL_EN_LPT; ++ u32Value2 = ((linePattern & GE_MSK_LP) | ((repeatFactor << 6) & GE_MSK_LPT_FACTOR) | GE_VAL_LPT_RESET); ++ GE_WriteReg(GE_REG_LPT, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_LPT; ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ } ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE Bit blt ++/// @param drawbuf \b IN: pointer to drawbuf info ++/// @param drawflag \b IN: draw flag \n ++/// GEDRAW_FLAG_DEFAULT \n ++/// GEDRAW_FLAG_SCALE \n ++/// GEDRAW_FLAG_DUPLICAPE \n ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_BitBlt(GE_DRAW_RECT *drawbuf,U32 drawflag) ++{ ++ U32 u32Width, u32Height; ++ U32 u32Value, u32Value2; ++ ++ if((!drawbuf->dstblk.width)||(!drawbuf->dstblk.height)||(!drawbuf->srcblk.width)||(!drawbuf->srcblk.height)) { ++ GE_WARN("GE bilblt: zero condition!!!!!\n"); ++ return GESTATUS_SUCCESS; // no need to do things, so it means success ++ } ++ ++ GE_DEBUGINFO( printk( "MHal_GE_BitBlt\n" ) ); ++ if (!GE_CheckInClipWindow(drawbuf->dstblk.x, drawbuf->dstblk.y, ++ drawbuf->dstblk.x+drawbuf->dstblk.width-1, ++ drawbuf->dstblk.y+drawbuf->dstblk.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(20); ++ ++ u32Value2 = GE_ReadReg(GE_REG_FMT_BLT); ++ ++ u32Width = drawbuf->srcblk.width; ++ u32Height = drawbuf->srcblk.height; ++ ++ GE_WriteReg(GE_REG_STBB_WIDTH, u32Width); ++ GE_WriteReg(GE_REG_STBB_HEIGHT,u32Height); ++ ++ // Set source coordinate ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x); ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y); ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_X_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x + drawbuf->srcblk.width - 1); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_Y_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y + drawbuf->srcblk.height - 1); ++ } ++ ++ if(drawflag&GEDRAW_FLAG_DUPLICAPE) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ else ++ { ++ _u32Reg60hFlag &= ~GE_VAL_STBB_PATCH; ++ } ++ ++ if(drawflag&GEDRAW_FLAG_SCALE) ++ { ++ u32Value = Divide2Fixed(u32Width, drawbuf->dstblk.width, 1, 12);//<< 2 ; //sc ++ GE_WriteReg(GE_REG_STBB_DX, u32Value & 0xffff); ++ u32Value = Divide2Fixed((u32Width - drawbuf->dstblk.width), 2* drawbuf->dstblk.width, 1, 12);// << 2; //sc ++ GE_WriteReg(GE_REG_STBB_INIT_DX, u32Value); ++ ++ u32Value = Divide2Fixed(u32Height, drawbuf->dstblk.height, 1, 12);// << 2 ; //sc ++ GE_WriteReg(GE_REG_STBB_DY, u32Value & 0xffff); ++ u32Value = Divide2Fixed((u32Height - drawbuf->dstblk.height), 2* drawbuf->dstblk.height, 0, 12);// << 2; //sc ++ GE_WriteReg(GE_REG_STBB_INIT_DY, u32Value); ++ ++ //scale = (U16)((float)(u32Width-1) * ((float)pbmpfmt->width / (float)u32Width));//TODO ++// u32Scale = (((U32)drawbuf->dstblk.width << 5) / u32Width * (u32Width-1)) >> 5; //sc ++// u32Width = u32Scale; //pbmpfmt->width; ++ u32Width = drawbuf->dstblk.width; ++ ++ //scale = (U16)((float)(u32Height-1) * ((float)pbmpfmt->height / (float)u32Height));//TODO ++// u32Scale = (((U32)drawbuf->dstblk.height << 5) / u32Height * (u32Height-1)) >> 5; //sc ++// u32Height = u32Scale; //pbmpfmt->height; ++ u32Height = drawbuf->dstblk.height; ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Width = drawbuf->dstblk.width; ++ u32Height = drawbuf->dstblk.height; ++ GE_WriteReg(GE_REG_STBB_DX, 0x1000); ++ GE_WriteReg(GE_REG_STBB_DY, 0x1000); ++ GE_WriteReg(GE_REG_STBB_INIT_DX, 0); ++ GE_WriteReg(GE_REG_STBB_INIT_DY, 0); ++ if ((drawbuf->dstblk.width != drawbuf->srcblk.width) || ++ (drawbuf->dstblk.height != drawbuf->srcblk.height)) ++ { ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ } ++ } ++ ++ GE_WriteReg(GE_REG_FMT_BLT, u32Value2); ++ ++ if (u32Value2 & GE_VAL_EN_STRETCH_BITBLT) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ ++ //------------------------------------------------------------ ++ // Destination coordinate ++ //------------------------------------------------------------ ++ GE_WriteReg(GE_REG_PRI_V0_X, drawbuf->dstblk.x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, drawbuf->dstblk.y); ++ GE_WriteReg(GE_REG_PRI_V1_X, drawbuf->dstblk.x + u32Width - 1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, drawbuf->dstblk.y + u32Height - 1); ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ GE_WriteReg(GE_REG_CMD, (GE_VAL_PRIM_BITBLT|_u32Reg60hFlag)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++GESTATUS MHal_GE_BitBltEx(GE_DRAW_RECT * drawbuf, U32 drawflag, GE_SCALE_INFO * ScaleInfo) ++{ ++ U32 u32Width, u32Height; ++ U32 u32Value2; ++ ++ GE_DEBUGINFO( printk( "MHal_GE_BitBltEx\n" ) ); ++ if (!GE_CheckInClipWindow(drawbuf->dstblk.x, drawbuf->dstblk.y, ++ drawbuf->dstblk.x+drawbuf->dstblk.width-1, ++ drawbuf->dstblk.y+drawbuf->dstblk.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(20); ++ ++ u32Value2 = GE_ReadReg(GE_REG_FMT_BLT); ++ ++ u32Width = drawbuf->srcblk.width; ++ u32Height = drawbuf->srcblk.height; ++ ++ GE_WriteReg(GE_REG_STBB_WIDTH, u32Width); ++ GE_WriteReg(GE_REG_STBB_HEIGHT,u32Height); ++ ++ // Set source coordinate ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x); ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y); ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_X_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x + drawbuf->srcblk.width - 1); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_Y_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y + drawbuf->srcblk.height - 1); ++ } ++ ++ if(drawflag&GEDRAW_FLAG_DUPLICAPE) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ else ++ { ++ _u32Reg60hFlag &= ~GE_VAL_STBB_PATCH; ++ } ++ ++ if(drawflag&GEDRAW_FLAG_SCALE) ++ { ++ GE_WriteReg(GE_REG_STBB_DX, (ScaleInfo->u32DeltaX & 0xffff)); ++ GE_WriteReg(GE_REG_STBB_INIT_DX, (ScaleInfo->u32InitDelatX & 0xffff)); ++ GE_WriteReg(GE_REG_STBB_DY, (ScaleInfo->u32DeltaY & 0xffff)); ++ GE_WriteReg(GE_REG_STBB_INIT_DY, (ScaleInfo->u32InitDelatY & 0xffff)); ++ ++ u32Width = drawbuf->dstblk.width; ++ u32Height = drawbuf->dstblk.height; ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Width = drawbuf->dstblk.width; ++ u32Height = drawbuf->dstblk.height; ++ GE_WriteReg(GE_REG_STBB_DX, 0x1000); ++ GE_WriteReg(GE_REG_STBB_DY, 0x1000); ++ GE_WriteReg(GE_REG_STBB_INIT_DX, 0); ++ GE_WriteReg(GE_REG_STBB_INIT_DY, 0); ++ if ((drawbuf->dstblk.width != drawbuf->srcblk.width) || ++ (drawbuf->dstblk.height != drawbuf->srcblk.height)) ++ { ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ } ++ } ++ ++ GE_WriteReg(GE_REG_FMT_BLT, u32Value2); ++ ++ if (u32Value2 & GE_VAL_EN_STRETCH_BITBLT) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ ++ //------------------------------------------------------------ ++ // Destination coordinate ++ //------------------------------------------------------------ ++ GE_WriteReg(GE_REG_PRI_V0_X, drawbuf->dstblk.x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, drawbuf->dstblk.y); ++ GE_WriteReg(GE_REG_PRI_V1_X, drawbuf->dstblk.x + u32Width - 1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, drawbuf->dstblk.y + u32Height - 1); ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ GE_WriteReg(GE_REG_CMD, (GE_VAL_PRIM_BITBLT|_u32Reg60hFlag)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++GESTATUS MHal_GE_GetScaleBltInfo(GE_DRAW_RECT* pdrawbuf, GE_BLOCK* pSrcBlk, GE_BLOCK* pDstBlk, GE_SCALE_INFO * pScaleInfo) ++{ ++ U32 u32InitDx, u32InitDy; ++ U32 u32Temp; ++ //U32 u32Temp1; ++ U32 u32InverseDeltaX; ++ U32 u32InverseDeltaY; ++ U16 bXStartMinus_1 = FALSE; ++ U16 bYStartMinus_1 = FALSE; ++ U32 u32Temp2, u32Temp3; ++ ++ if (pdrawbuf->srcblk.width == pdrawbuf->dstblk.width) ++ { ++ pDstBlk->x = pSrcBlk->x; ++ pDstBlk->width = pSrcBlk->width; ++ pScaleInfo->u32DeltaX = 0x1000; ++ pScaleInfo->u32InitDelatX = 0; ++ } ++ else ++ { ++ pScaleInfo->u32DeltaX = Divide2Fixed(pdrawbuf->srcblk.width, pdrawbuf->dstblk.width, 1, 12);//<< 2 ; //sc ++ u32InverseDeltaX = Divide2Fixed(pdrawbuf->dstblk.width, pdrawbuf->srcblk.width, 1, 12);//<< 2 ; //sc ++ u32InitDx = Divide2Fixed((pdrawbuf->srcblk.width -pdrawbuf->dstblk.width), 2*pdrawbuf->dstblk.width,0, 12);// << 2; //sc ++ ++ if (pdrawbuf->srcblk.width > pdrawbuf->dstblk.width) ++ { ++ //Horizontal down scaling ++ //Get destination x ++ if (pSrcBlk->x == 0) ++ { ++ pDstBlk->x = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->x<<12) - (u32InitDx & 0xfff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = ((((pSrcBlk->x<<12) - (u32InitDx & 0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = (((pSrcBlk->x<<12) - (u32Temp2*pScaleInfo->u32DeltaX + u32InitDx))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) > u32InverseDeltaX) ++ { ++ pDstBlk->x = ((u32Temp & 0xfffff000)>>12)+1; ++ bXStartMinus_1 = FALSE; ++ } ++ else ++ { ++ pDstBlk->x = ((u32Temp & 0xfffff000)>>12); ++ bXStartMinus_1 = TRUE; ++ } ++ } ++ ++ //Get Destination width ++ //u32Temp = ((((pSrcBlk->x+pSrcBlk->width)<<12) - (u32InitDx & 0x1fff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = (((((pSrcBlk->x+pSrcBlk->width)<<12) - (u32InitDx & 0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = ((((pSrcBlk->x+pSrcBlk->width)<<12) - (u32Temp2*pScaleInfo->u32DeltaX + u32InitDx))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) < u32InverseDeltaX) ++ { ++ pSrcBlk->width++; ++ } ++ pDstBlk->width = ((u32Temp & 0xfffff000)>>12) - pDstBlk->x + 1; ++ ++ ++ //Get x initial delta. ++ if (bXStartMinus_1) ++ { ++ pSrcBlk->x--; ++ pSrcBlk->width++; ++ } ++ u32Temp = pDstBlk->x *pScaleInfo->u32DeltaX + u32InitDx; ++ //u32Temp = ((pDstBlk->x<<12)*pdrawbuf->srcblk.width)/pdrawbuf->dstblk.width + u32InitDx; ++ } ++ else ++ { ++ //Horizontal up scaling ++ //Get destination x ++ if (pSrcBlk->x == 0) ++ { ++ pDstBlk->x = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->x<<12) - ((~u32InitDx+1)&0xfff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = ((((pSrcBlk->x<<12) + ((~u32InitDx+1)&0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = ((((pSrcBlk->x<<12) - (u32Temp2*pScaleInfo->u32DeltaX - ((~u32InitDx+1)&0xfff))))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->x = (((u32Temp-u32InverseDeltaX)&0xfffff000)>>12)+1; ++ bXStartMinus_1 = TRUE; ++ } ++ ++ //Get Destination width ++ //u32Temp = ((((pSrcBlk->x + pSrcBlk->width)<<12) + ((~u32InitDx+1) & 0x1fff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = (((((pSrcBlk->x + pSrcBlk->width)<<12) + ((~u32InitDx+1)&0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = (((((pSrcBlk->x + pSrcBlk->width)<<12) - (u32Temp2*pScaleInfo->u32DeltaX - ((~u32InitDx+1)&0xfff))))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->width = ((u32Temp & 0xfffff000)>>12) - pDstBlk->x + 1; ++ pSrcBlk->width++; ++ ++ ++ //Get x initial delta. ++ if (bXStartMinus_1) ++ { ++ pSrcBlk->x--; ++ pSrcBlk->width++; ++ } ++ u32Temp = pDstBlk->x *pScaleInfo->u32DeltaX - ((~u32InitDx+1)&0xfff); ++ //u32Temp = ((pDstBlk->x<<12)*pdrawbuf->srcblk.width)/pdrawbuf->dstblk.width - ((~u32InitDx+1)&0xfff); ++ } ++ ++ if (pDstBlk->x == 0) ++ { ++ pScaleInfo->u32InitDelatX = u32InitDx; ++ } ++ else ++ { ++ if (u32Temp > (pSrcBlk->x<<12)) ++ { ++ if ((u32Temp - (pSrcBlk->x<<12)) < 0x1000) ++ { ++ pScaleInfo->u32InitDelatX = (u32Temp- (pSrcBlk->x<<12)); ++ } ++ else ++ { ++ //Invalid destination X position. ++ //printk("+ ,Invalid destination X position.\n"); ++ pScaleInfo->u32InitDelatX = 0xfff; ++ } ++ } ++ else ++ { ++ //printk("- ,Invalid destination X direction.\n"); ++ pScaleInfo->u32InitDelatX = 0; ++ } ++ } ++ } ++ ++ if (pdrawbuf->srcblk.height == pdrawbuf->dstblk.height) ++ { ++ pDstBlk->y = pSrcBlk->y; ++ pDstBlk->height = pSrcBlk->height; ++ pScaleInfo->u32DeltaY = 0x1000; ++ pScaleInfo->u32InitDelatY = 0; ++ } ++ else ++ { ++ pScaleInfo->u32DeltaY = Divide2Fixed(pdrawbuf->srcblk.height, pdrawbuf->dstblk.height, 1, 12);// << 2 ; //sc ++ u32InverseDeltaY = Divide2Fixed(pdrawbuf->dstblk.height, pdrawbuf->srcblk.height, 1, 12);// << 2 ; //sc ++ u32InitDy = Divide2Fixed((pdrawbuf->srcblk.height - pdrawbuf->dstblk.height), 2*pdrawbuf->dstblk.height, 0, 12);// << 2; //sc ++ ++ ++ if (pdrawbuf->srcblk.height > pdrawbuf->dstblk.height) ++ { ++ //Vertical down scaling ++ //Get destination y ++ if (pSrcBlk->y == 0) ++ { ++ pDstBlk->y = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->y<<12) - (u32InitDy & 0xfff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = ((((pSrcBlk->y<<12) - (u32InitDy & 0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = (((pSrcBlk->y<<12) - (u32Temp2*pScaleInfo->u32DeltaY + u32InitDy))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) > u32InverseDeltaY) ++ { ++ pDstBlk->y = ((u32Temp & 0xfffff000)>>12)+1; ++ bYStartMinus_1 = FALSE; ++ } ++ else ++ { ++ pDstBlk->y = ((u32Temp & 0xfffff000)>>12); ++ bYStartMinus_1 = TRUE; ++ } ++ } ++ ++ //Get Destination height ++ //u32Temp = ((((pSrcBlk->y+pSrcBlk->height)<<12) - (u32InitDy & 0x1fff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = (((((pSrcBlk->y+pSrcBlk->height)<<12) - (u32InitDy & 0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = ((((pSrcBlk->y+pSrcBlk->height)<<12) - (u32Temp2*pScaleInfo->u32DeltaY + u32InitDy))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) < u32InverseDeltaY) ++ { ++ pSrcBlk->height++; ++ } ++ pDstBlk->height = ((u32Temp & 0xfffff000)>>12) - pDstBlk->y + 1; ++ ++ //Get x initial delta. ++ if (bYStartMinus_1) ++ { ++ pSrcBlk->y--; ++ pSrcBlk->height++; ++ } ++ u32Temp = pDstBlk->y*pScaleInfo->u32DeltaY + u32InitDy; ++ //u32Temp = ((pDstBlk->y<<12)*pdrawbuf->srcblk.height)/pdrawbuf->dstblk.height + u32InitDy; ++ } ++ else ++ { ++ //Vertical up scaling ++ //Get destination y ++ if (pSrcBlk->y == 0) ++ { ++ pDstBlk->y = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->y<<12) + ((~u32InitDy+1)&0xfff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = ((((pSrcBlk->y<<12) + ((~u32InitDy+1)&0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = ((((pSrcBlk->y<<12) - (u32Temp2*pScaleInfo->u32DeltaY - ((~u32InitDy+1)&0xfff))))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->y = (((u32Temp-u32InverseDeltaY)&0xfffff000)>>12)+1; ++ bYStartMinus_1 = TRUE; ++ } ++ ++ //Get Destination height ++ //u32Temp = ((((pSrcBlk->y + pSrcBlk->height)<<12) + ((~u32InitDy+1) & 0x1fff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = (((((pSrcBlk->y + pSrcBlk->height)<<12) + ((~u32InitDy+1)&0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = (((((pSrcBlk->y + pSrcBlk->height)<<12) - (u32Temp2*pScaleInfo->u32DeltaY - ((~u32InitDy+1)&0xfff))))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->height = ((u32Temp & 0xfffff000)>>12) - pDstBlk->y + 1; ++ pSrcBlk->height++; ++ ++ //Get x initial delta. ++ if (bYStartMinus_1) ++ { ++ pSrcBlk->y--; ++ pSrcBlk->height++; ++ } ++ u32Temp = pDstBlk->y*pScaleInfo->u32DeltaY- ((~u32InitDy+1)&0xfff); ++ //u32Temp = ((pDstBlk->y<<12)*pdrawbuf->srcblk.height)/pdrawbuf->dstblk.height - ((~u32InitDy+1)&0xfff); ++ } ++ ++ if (pDstBlk->y == 0) ++ { ++ pScaleInfo->u32InitDelatY = u32InitDy; ++ } ++ else ++ { ++ if (u32Temp > (pSrcBlk->y<<12)) ++ { ++ if ((u32Temp - (pSrcBlk->y<<12)) < 0x1000) ++ { ++ pScaleInfo->u32InitDelatY = (u32Temp- (pSrcBlk->y<<12)); ++ } ++ else ++ { ++ //Invalid destination Y position. ++ //printk("+ ,Invalid destination Y position.\n"); ++ pScaleInfo->u32InitDelatY = 0xfff; ++ } ++ } ++ else ++ { ++ //printk("- ,Invalid destination Y direction.\n"); ++ pScaleInfo->u32InitDelatY = 0; ++ } ++ } ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE Screen to Screen bitblt ++/// @param psrcblk \b IN: pointer of source block ++/// @param pdstblk \b IN: pointer of destination block ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_ScreenCopy(GE_BLOCK *psrcblk, GE_BLOCK *pdstblk) ++{ ++ //U32 u32Addr; ++ U32 u32Scale, u32Value, u32Value2, u32Value3; ++ ++ GE_DEBUGINFO( printk( "MHal_GE_ScreenCopy\n" ) ); ++ ++ GE_WaitAvailableCMDQueue(25); ++ ++ if (!GE_CheckInClipWindow(pdstblk->x, pdstblk->y, ++ pdstblk->x+pdstblk->width-1, pdstblk->y+pdstblk->height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ //u32Value = GE_ReadReg(GE_REG_EN); ++ //u32Value |= GE_VAL_EN_PE; ++ //GE_WriteReg(GE_REG_EN, u32Value); ++ ++ u32Value2 = GE_ReadReg(GE_REG_FMT_BLT); ++ ++ GE_WriteReg(GE_REG_STBB_WIDTH, psrcblk->width); ++ GE_WriteReg(GE_REG_STBB_HEIGHT, psrcblk->height); ++ ++ // Set stretch delta ++ if(psrcblk->width != pdstblk->width) ++ { ++ u32Value = Divide2Fixed(psrcblk->width, pdstblk->width, 1, 12);// << 2; //sc ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ u32Value3 = Divide2Fixed((psrcblk->width - pdstblk->width), 2* pdstblk->width, 1, 12);// << 2; //sc ++ } ++ else ++ { ++ u32Value = 0x1000; ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ u32Value3 = 0; ++ } ++ GE_WriteReg(GE_REG_STBB_DX, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_STBB_INIT_DX,u32Value3); ++ ++ if(psrcblk->height != pdstblk->height) ++ { ++ u32Value = (U16)Divide2Fixed(psrcblk->height, pdstblk->height, 1, 12);//<<2; //sc ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ u32Value3 = Divide2Fixed((psrcblk->height - pdstblk->height), 2* pdstblk->height, 1, 12);// << 2; //sc ++ } ++ else ++ { ++ u32Value = 0x1000; ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ } ++ GE_WriteReg(GE_REG_STBB_DY, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_STBB_INIT_DY,u32Value3); ++ ++ GE_WriteReg(GE_REG_FMT_BLT, u32Value2); ++ ++ // Source coordinate ++ GE_WriteReg(GE_REG_PRI_V2_X, psrcblk->x); ++ GE_WriteReg(GE_REG_PRI_V2_Y, psrcblk->y); ++ ++ if ((psrcblk->x <= pdstblk->x) && (pdstblk->x <= (psrcblk->x + psrcblk->width)) && ++ (psrcblk->y <= pdstblk->y) && (pdstblk->y <= (psrcblk->y + psrcblk->height))) ++ { ++ _u32Reg60hFlag |= (GE_VAL_DRAW_DST_DIR_X_NEG | GE_VAL_DRAW_DST_DIR_Y_NEG | GE_VAL_DRAW_SRC_DIR_X_NEG | GE_VAL_DRAW_SRC_DIR_Y_NEG); ++ } ++ if ((psrcblk->x <= (pdstblk->x + pdstblk->width)) && ((pdstblk->x + pdstblk->width) <= (psrcblk->x + psrcblk->width)) && ++ (psrcblk->y <= pdstblk->y) && (pdstblk->y <= (psrcblk->y + psrcblk->height))) ++ { ++ _u32Reg60hFlag |= (GE_VAL_DRAW_DST_DIR_Y_NEG | GE_VAL_DRAW_SRC_DIR_Y_NEG); ++ } ++ ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_X_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_X, psrcblk->x + psrcblk->width - 1); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_Y_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_Y, psrcblk->y + psrcblk->height - 1); ++ } ++ ++ ++ // Set source pitch buffer information with destination buffer. ++ GE_WriteReg(GE_REG_SB_PIT, GE_ReadReg(GE_REG_DB_PIT)); ++ GE_WriteReg(GE_REG_SB_BASE0, GE_ReadReg(GE_REG_DB_BASE0)); ++ GE_WriteReg(GE_REG_SB_BASE1, GE_ReadReg(GE_REG_DB_BASE1)); ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ u32Value2 = (u32Value & GE_MSK_DB_FMT) | ((u32Value & GE_MSK_DB_FMT)>>8); ++ GE_WriteReg(GE_REG_SB_DB_MODE, u32Value2); ++ ++ ++ // Destination coordinate ++ if (_u32Reg60hFlag & GE_VAL_DRAW_DST_DIR_X_NEG) ++ { ++ u32Scale = (((U32)pdstblk->width << 5) / psrcblk->width * (psrcblk->width-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V0_X, pdstblk->x + u32Scale); ++ GE_WriteReg(GE_REG_PRI_V1_X, pdstblk->x); ++ } ++ else ++ { ++ GE_WriteReg(GE_REG_PRI_V0_X, pdstblk->x); ++ u32Scale = (((U32)pdstblk->width << 5) / psrcblk->width * (psrcblk->width-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_X, pdstblk->x + u32Scale); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_DST_DIR_Y_NEG) ++ { ++ u32Scale = (((U32)pdstblk->height << 5) / psrcblk->height * (psrcblk->height-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V0_Y, pdstblk->y + u32Scale); ++ GE_WriteReg(GE_REG_PRI_V1_Y, pdstblk->y); ++ } ++ else ++ { ++ GE_WriteReg(GE_REG_PRI_V0_Y, pdstblk->y); ++ u32Scale = (((U32)pdstblk->height << 5) / psrcblk->height * (psrcblk->height-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_Y, pdstblk->y + u32Scale); ++ } ++/* ++ GE_WriteReg(GE_REG_PRI_V0_X, pdstblk->x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, pdstblk->y); ++ u32Scale = (((U32)pdstblk->width << 5) / psrcblk->width * (psrcblk->width-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_X, pdstblk->x + u32Scale); ++ u32Scale = (((U32)pdstblk->height << 5) / psrcblk->height * (psrcblk->height-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_Y, pdstblk->y + u32Scale); ++*/ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ u32Value = GE_VAL_PRIM_BITBLT; ++ ++ GE_WriteReg(GE_REG_CMD, u32Value|_u32Reg60hFlag); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE clipping window ++/// @param v0 \b IN: left-top position ++/// @param v1 \b IN: right-down position ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetClip(GE_POINT_t* v0, GE_POINT_t* v1) ++{ ++ GE_WaitAvailableCMDQueue(8); ++ GE_WriteReg(GE_REG_CLIP_LEFT, v0->x); ++ GE_WriteReg(GE_REG_CLIP_TOP, v0->y); ++ //GE_WriteReg(GE_REG_CLIP_RIGHT, v1->x - 1); ++ //GE_WriteReg(GE_REG_CLIP_BOTTOM, v1->y - 1); ++ GE_WriteReg(GE_REG_CLIP_RIGHT, v1->x); ++ GE_WriteReg(GE_REG_CLIP_BOTTOM, v1->y); ++ _u16PeClipX1 = v0->x; ++ _u16PeClipY1 = v0->y; ++ _u16PeClipX2 = v1->x; ++ _u16PeClipY2 = v1->y; ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE rotate ++/// @param angle \b IN: rotate angle ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @note ++/// The rotate process can't perform with italic process. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetRotate(GEROTATE_ANGLE angle) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++ u32Value = GE_ReadReg(GE_REG_ROT_MIRROR); ++ u32Value &= ~GE_MSK_ROT; ++ u32Value |= (U32)angle; ++ GE_WriteReg(GE_REG_ROT_MIRROR, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE alpha source ++/// @param eMode \b IN: alpha source come from , this indicate alpha channel output source ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetAlphaSrcFrom( GE_ALPHA_SRC_FROM eMode ) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++ u32Value = GE_ReadReg(GE_REG_DB_ABL); ++ ++ u32Value = ((u32Value & (~GE_MSK_DB_ABL))| (eMode<<8)); ++ GE_WriteReg(GE_REG_DB_ABL, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Description: ++// Arguments: eMode : ABL_FROM_CONST, ABL_FROM_ASRC, ABL_FROM_ADST ++// blendcoef : COEF_ONE, COEF_CONST, COEF_ASRC, COEF_ADST ++// COEF_ZERO, COEF_1_CONST, COEF_1_ASRC, COEF_1_ADST ++// blendfactor : value : [0,0xff] ++// Return: NONE ++// ++// Notes: if any ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++/// Set PE alpha blending. Dst = A * Src + (1 - A) Dst ++/// @param blendcoef \b IN: alpha source from ++/// @param u8ConstantAlpha \b IN: Contant alpha when blendcoef is equal to COEF_CONST ++/// or COEF_1_CONST. ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetAlphaBlending(GE_BLEND_COEF blendcoef, U8 u8ConstantAlpha) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++ u32Value = GE_ReadReg(GE_REG_ABL_COEF); ++ u32Value &= ~(GE_MSK_ABL_COEF); ++ u32Value |= blendcoef ; ++ GE_WriteReg(GE_REG_ABL_COEF, u32Value); ++ ++ GE_WriteReg(GE_REG_ABL_CONST, (U32)(u8ConstantAlpha&0xff)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable PE alpha blending ++/// @param enable \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_EnableAlphaBlending(U16 enable) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_GY_ABL; ++ GE_WriteReg(GE_REG_EN, u32Value); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_GY_ABL; ++ GE_WriteReg(GE_REG_EN, u32Value); ++ } ++ ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable PE mirror ++/// @param isMirrorX \b IN: true/false ++/// @param isMirrorY \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @note ++/// The mirror process can't perform on the source format is GE_FMT_I1, GE_FMT_I2 or GE_FMT_I4. ++/// The mirror process can't perform with italic process. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetMirror(U16 isMirrorX, U16 isMirrorY) ++{ ++ _u32Reg60hFlag = (_u32Reg60hFlag & ~(GE_VAL_DRAW_SRC_DIR_X_NEG|GE_VAL_DRAW_SRC_DIR_Y_NEG)); ++ _u32Reg60hFlag |= ( (isMirrorX << 7) | (isMirrorY << 8) ); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable PE NearestMode ++/// @param enable \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetNearestMode(U16 enable) ++{ ++ _u32Reg60hFlag = (_u32Reg60hFlag & ~(GE_VAL_STBB_NEAREST)); ++ _u32Reg60hFlag |= (enable << 14); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE source buffer info ++/// @param bufInfo \b IN: buffer handle ++/// @param offsetofByte \b IN: start offset (should be 128 bit aligned) ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @return GESTATUS_NON_ALIGN_PITCH - The pitch is not 16 bytes alignment ++/// @return GESTATUS_NON_ALIGN_ADDRESS - The address is not 16 bytes alignment ++/// @note ++/// The buffer start address must be 128 bits alignment. ++/// In GE_FMT_I1, GE_FMT_I2 and GE_FMT_I4 format, the pitch must be 8 bits alignment. ++/// In other format, the pitch must be 128 bits alignment. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetSrcBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte) ++{ ++ U32 u32Value , u32Addr; ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++ _GE_CHECK_BUFFER_ALIGN1( ++ bufInfo->u32Addr + offsetofByte, ++ bufInfo->u32Width, ++ bufInfo->u32Height, ++ bufInfo->u32Pitch, ++ bufInfo->u32ColorFmt); ++ ++ if ((bufInfo->u32Addr + offsetofByte)%16) ++ { ++ printk(KERN_WARNING "GESTATUS_NON_ALIGN_ADDRESS(%d)\n", __LINE__); ++ return GESTATUS_NON_ALIGN_ADDRESS; ++ } ++ ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ u32Value = (u32Value & ~GE_MSK_SB_FMT) | (bufInfo->u32ColorFmt); // one-bit format ++ GE_WriteReg(GE_REG_SB_DB_MODE, u32Value); ++ ++ ++ // Set source address ++ u32Addr = (bufInfo->u32Addr + offsetofByte); ++ GE_WriteReg(GE_REG_SB_BASE0, u32Addr & 0xffff); ++ GE_WriteReg(GE_REG_SB_BASE1, u32Addr >> 16); ++ ++ // Set source pitch ++ GE_WriteReg(GE_REG_SB_PIT, (bufInfo->u32Pitch)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE destination buffer info ++/// @param bufInfo \b IN: buffer handle ++/// @param offsetofByte \b IN: start offset (should be 128 bit aligned) ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @return GESTATUS_NON_ALIGN_PITCH - The pitch is not 16 bytes alignment ++/// @return GESTATUS_NON_ALIGN_ADDRESS - The address is not 16 bytes alignment ++/// @note ++/// The buffer start address and pitch smust be 128 bits alignment. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetDstBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte) ++{ ++ U32 u32Value; ++ U32 u32Addr = (bufInfo->u32Addr + offsetofByte ); ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++ _GE_CHECK_BUFFER_ALIGN1( ++ bufInfo->u32Addr + offsetofByte, ++ bufInfo->u32Width, ++ bufInfo->u32Height, ++ bufInfo->u32Pitch, ++ bufInfo->u32ColorFmt); ++ ++ if (u32Addr%16) ++ { ++ printk(KERN_WARNING "GESTATUS_NON_ALIGN_ADDRESS(%d)\n", __LINE__); ++ return GESTATUS_NON_ALIGN_ADDRESS; ++ } ++ ++ // Destination Buffer ++ GE_WriteReg(GE_REG_DB_PIT, bufInfo->u32Pitch); // Pitch ++ GE_WriteReg(GE_REG_DB_BASE0, u32Addr & 0xffff); // Address ++ GE_WriteReg(GE_REG_DB_BASE1, u32Addr >> 16); // Address ++ ++ if( GE_FMT_ARGB1555==bufInfo->u32ColorFmt ) ++ bufInfo->u32ColorFmt = GE_FMT_ARGB1555_DST; ++ ++ // Destination frame buffer format ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ u32Value = (u32Value & ~GE_MSK_DB_FMT) | (bufInfo->u32ColorFmt<<8); // one-bit format ++ GE_WriteReg(GE_REG_SB_DB_MODE, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_GetFrameBufferInfo(U32 *width, ++ U32 *height, ++ U32 *pitch, ++ U32 *fbFmt, ++ U32 *addr) ++{ ++ // TODO: width & height have not been retrieved ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(31); ++ ++ u32Value = GE_ReadReg(GE_REG_DB_PIT); ++ *pitch = u32Value; ++ ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ *fbFmt = ((u32Value & GE_MSK_DB_FMT)>>8); ++ ++ u32Value = GE_ReadReg(GE_REG_DB_BASE0); ++ *addr = u32Value; ++ u32Value = GE_ReadReg(GE_REG_DB_BASE1); ++ *addr |= (u32Value << 16); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_YUV_Set(GE_YUV_INFO* pYuvInfo) ++{ ++ U32 u32YuvInfo= 0; ++ ++ GE_ASSERT(pYuvInfo, printk("[GE DRV][%06d] NULL pointer\n", __LINE__)); ++ ++ // if (bEnable){ ++ u32YuvInfo|= (pYuvInfo->rgb2yuv_mode)? GE_VAL_RGB2YUV_255: GE_VAL_RGB2YUV_PC; ++ u32YuvInfo|= (pYuvInfo->yuv_range_out)? GE_VAL_YUV_RANGE_OUT_PC: GE_VAL_YUV_RANGE_OUT_255; ++ u32YuvInfo|= (pYuvInfo->yuv_range_in)? GE_VAL_YUV_RANGE_IN_127: GE_VAL_YUV_RANGE_IN_255; ++ u32YuvInfo|= ((pYuvInfo->yuv_mem_fmt_src & 0x3)<< GE_SHFT_YUV_MEM_FMT_SRC); ++ u32YuvInfo|= ((pYuvInfo->yuv_mem_fmt_dst & 0x3)<< GE_SHFT_YUV_MEM_FMT_DST); ++ // } ++ ++ GE_WriteReg(GE_REG_YUV, u32YuvInfo); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++GESTATUS MHal_GE_YUV_Get(GE_YUV_INFO* pYuvInfo) ++{ ++ U32 u32YuvInfo; ++ ++ GE_ASSERT(pYuvInfo, printk("[GE DRV][%06d] NULL pointer\n", __LINE__)); ++ u32YuvInfo= GE_ReadReg(GE_REG_YUV); ++ pYuvInfo->rgb2yuv_mode= (u32YuvInfo & GE_VAL_RGB2YUV_255)? GE_RGB2YUV_255_MODE: GE_RGB2YUV_PC_MODE; ++ pYuvInfo->yuv_range_out= (u32YuvInfo & GE_VAL_YUV_RANGE_OUT_PC)? GE_YUV_RANGE_OUT_PC: GE_YUV_RANGE_OUT_255; ++ pYuvInfo->yuv_range_in= (u32YuvInfo & GE_VAL_YUV_RANGE_IN_127)? GE_YUV_RANGE_IN_127: GE_YUV_RANGE_IN_255; ++ pYuvInfo->yuv_mem_fmt_src= (u32YuvInfo & GE_MASK_YUV_MEM_FMT_SRC) >> GE_SHFT_YUV_MEM_FMT_SRC; ++ pYuvInfo->yuv_mem_fmt_dst= (u32YuvInfo & GE_MASK_YUV_MEM_FMT_DST) >> GE_SHFT_YUV_MEM_FMT_DST; ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++void GE_ConvertRGB2DBFmt(GE_Buffer_Format Fmt, U32 *colorinfo, U16* low, U16* high) ++{ ++ GE_RGB_COLOR *color = NULL; ++ GE_BLINK_DATA *blinkData = NULL; ++ //U8 a, r, g, b; ++ ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355== Fmt) ++ // if (Fmt == GE_FMT_1BAAFGBG123433) ++ { ++ blinkData =(GE_BLINK_DATA *)colorinfo; ++ } ++ else ++ { ++ color =(GE_RGB_COLOR *)colorinfo; ++ } ++ ++ switch (Fmt) ++ { ++ case GE_FMT_RGB565 : ++ *low = ((color->b & 0xf8) + (color->b >> 5)) | (((color->g & 0xfc) + (color->g>>6))<<8); ++ *high = ((color->r & 0xf8) + (color->r >> 5)) | ((color->a & 0xff) << 8); ++ break; ++ case GE_FMT_ARGB1555 : ++ *low = ((color->b & 0xf8) + (color->b >> 5)) | (((color->g & 0xf8) + (color->g >> 5))<<8); ++ if (color->a > 0) ++ { ++ *high = ((color->r & 0xf8) + (color->r >> 5)) | (0xff << 8); ++ } ++ else ++ { ++ *high = ((color->r & 0xf8) + (color->r >> 5)); ++ } ++ break; ++ case GE_FMT_ARGB4444 : ++ *low = ((color->b & 0xf0) + (color->b >> 4)) | (((color->g & 0xf0) + (color->g >> 4))<<8); ++ *high = ((color->r & 0xf0) + (color->r >> 4)) | (((color->a & 0xf0) + (color->a >> 4))<<8); ++ break; ++ case GE_FMT_ARGB8888 : ++ *low =(color->b & 0xff) | ((color->g & 0xff) << 8); ++ *high =(color->r & 0xff) | ((color->a & 0xff) << 8); ++ break; ++ case GE_FMT_I8 : ++ *low = (color->b & 0xff)|((color->b & 0xff) << 8); ++ *high = (color->b & 0xff)|((color->b & 0xff) << 8); ++ break; ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ // 1 A B Fg Bg ++ // 1 2 3 5 5 ++ case GE_FMT_1ABFGBG12355: ++ *low = (0x1f & blinkData->background) | // Bg: 4..0 ++ ((0x1f & blinkData->foreground)<< 5) | // Fg: 9..5 ++ ((0x1f & blinkData->ctrl_flag)<< 10) | // [A, B]: [14..13, 12..10] ++ BIT15; // Bit 15 ++ *high= (0x1f & blinkData->background) | // Bg: 4..0 ++ ((0x1f & blinkData->foreground)<< 5) | // Fg: 9..5 ++ ((0x1f & blinkData->ctrl_flag)<< 10) | // [A, B]: [14..13, 12..10] ++ BIT15; // Bit 15 ++ break; ++#if 0 ++ 1 B A A Fg Bg ++ 1 2 3 4 3 3 ++ case GE_FMT_1BAAFGBG123433 : ++ *low = ((blinkData->background & 0x7)|((blinkData->foreground & 0x7) << 3)|((blinkData->ctrl_flag & 0x1ff)<<6)|(0x1 << 15)); ++ *high = ((blinkData->background & 0x7)|((blinkData->foreground & 0x7) << 3)|((blinkData->ctrl_flag & 0x1ff)<<6)|(0x1 << 15)); ++ break; ++#endif ++ case GE_FMT_YUV422: ++ printk("[GE DRV][%06d] Are you sure to draw in YUV?\n", __LINE__); ++ ++ default: ++ GE_ASSERT(0, printk("[GE DRV][%06d] Bad color format\n", __LINE__)); ++ *low =(color->b & 0xff) | ((color->g & 0xff) << 8); ++ *high =(color->r & 0xff) | ((color->a & 0xff) << 8); ++ break; ++ } ++ ++} ++ ++void MHal_GE_PowerOff(void) ++{ ++ GE_WriteReg(GE_REG_FMT_BLT, GE_VAL_EN_CMDQ); ++ GE_WriteReg(GE_REG_EN, GE_VAL_EN_PE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Set a palette entry, I8(8-bit palette) format. ++// @param palEntry \b IN: ptr to palette data ++// @param u32Index \b IN: Palette Index, ++// @return TRUE: sucess / FALSE: fail ++// @note: Titania2 GE (support 256 entries: Index: 0-255) ++//------------------------------------------------------------------------------------------------- ++GESTATUS _MHal_GE_Palette_Set( GePaletteEntry palEntry, U32 u32Index) ++{ ++ U32 u32RegVal; ++ ++ GE_WaitAvailableCMDQueue(8); ++ u32RegVal=palEntry.u32Data; ++ ++ GE_WriteReg(PE_REG_PT_GB, (u32RegVal & 0xFFFF)); ++ GE_WriteReg(PE_REG_PT_AR,((u32RegVal>>16)& 0xFFFF)); ++ u32RegVal=GE_ReadReg(PE_REG_PT_IDX); ++ GE_WriteReg(PE_REG_PT_IDX, ((u32Index&0xFF)|0x100)); ++ GE_WriteReg(PE_REG_PT_IDX,(u32RegVal &0xFEFF)); ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set GE palette for I8(8-bit palette) format ++/// @param pPalArray \b IN: ptr to palette entry array ++/// @param u32PalStart \b IN: Define palette entry start index for set (range: 0~255) ++/// @param u32PalEnd \b IN: Define palette entry end index for set (range: 0~255) ++/// @return TRUE: sucess / FALSE: fail ++/// @note 1: GE palette is single port SRAM, You must set palettes before you read palette table. ++/// - I8 (valid palette index: 0~255) ++/// - Example: MHal_GE_Palette_Set ( pPalArray, 32, 255) ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_Palette_Set(GePaletteEntry * pPalArray, U32 u32PalStart, U32 u32PalEnd) ++{ ++ U32 u32I; ++ GESTATUS bRet = FALSE; ++ ++ if((u32PalEnd >= GE_PALETTE_ENTRY_NUM) || (u32PalStart > u32PalEnd)) ++ { ++ return FALSE; ++ } ++ ++ for (u32I = u32PalStart; u32I<=u32PalEnd; u32I++) ++ { ++ bRet = _MHal_GE_Palette_Set(pPalArray[u32I], u32I); ++ if (bRet == FALSE) ++ break; ++ } ++ ++ return bRet; ++} ++ +diff --git a/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge.h b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge.h +new file mode 100644 +index 00000000..a2ca09a4 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge.h +@@ -0,0 +1,582 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// @file drvGE.h ++/// @brief Graphics Engine Driver Interface ++/// @author MStar Semiconductor Inc. ++/// ++/// GE is used to paint OSD ++/// ++/// Features: ++/// - BLT engine : fast and simply blt function ++/// - Pixel engine(PE) : complex blt function ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef __DRVGE_H__ ++#define __DRVGE_H__ ++ ++#define GE_PALETTE_ENTRY_NUM 256 ++ ++//------------------------------------------------------------------------------ ++// macro ++//------------------------------------------------------------------------------ ++ ++//GE return code ++/// GE DDI return value ++#define GESTATUS U32 ++/// @name GESTATUS ++/// GESTATUS return value ++/// @{ ++#define GESTATUS_SUCCESS 0x00000000 //0 ++#define GESTATUS_FAIL 0x00000001 //Bit(0) ++#define GESTATUS_NON_ALIGN_ADDRESS 0x00000002 //Bit(1) ++#define GESTATUS_NON_ALIGN_PITCH 0x00000004 //Bit(2) ++#define GESTATUS_INVALID_INTENSITY_ID 0x00000008 //Bit(3) ++#define GESTATUS_INVALID_PARAMETERS 0x00000010 //Bit(4) ++ ++/// The above lines are moved from drvGE.h ++ ++ ++//------------------------------------------------------------------------------ ++// enum ++//------------------------------------------------------------------------------ ++ ++ ++ ++//------------------------------------------------------------------------------ ++// structure ++//------------------------------------------------------------------------------ ++ ++ ++///Define Raster Operation ++typedef enum ++{ ++ /// rop_result = 0; ++ ROP2_OP_ZORE = 0, ++ /// rop_result = ~( rop_src | rop_dst ); ++ ROP2_OP_NOT_PS_OR_PD = 1, ++ /// rop_result = ((~rop_src) & rop_dst); ++ ROP2_OP_NS_AND_PD = 2, ++ /// rop_result = ~(rop_src); ++ ROP2_OP_NS = 3, ++ /// rop_result = (rop_src & (~rop_dst)); ++ ROP2_OP_PS_AND_ND = 4, ++ /// rop_result = ~(rop_dst); ++ ROP2_OP_ND = 5, ++ /// rop_result = ( rop_src ^ rop_dst); ++ ROP2_OP_PS_XOR_PD = 6, ++ /// rop_result = ~(rop_src & rop_dst); ++ ROP2_OP_NOT_PS_AND_PD = 7, ++ /// rop_result = (rop_src & rop_dst); ++ ROP2_OP_PS_AND_PD = 8, ++ /// rop_result = ~(rop_dst ^ rop_src); ++ ROP2_OP_NOT_PS_XOR_PD = 9, ++ /// rop_result = rop_dst; ++ ROP2_OP_PD = 10, ++ /// rop_result = (rop_dst | (~rop_src)); ++ ROP2_OP_NS_OR_PD = 11, ++ /// rop_result = rop_src; ++ ROP2_OP_PS = 12, ++ /// rop_result = (rop_src | (~rop_dst)); ++ ROP2_OP_PS_OR_ND = 13, ++ /// rop_result = (rop_dst | rop_src); ++ ROP2_OP_PD_OR_PS = 14, ++ /// rop_result = 0xffffff; ++ ROP2_OP_ONE = 15, ++} GE_ROP2_OP; ++ ++ ++/// Color Key Operation Mode ++typedef enum ++{ ++ /// Not equal ++ CK_OP_NOT_EQUQL = 0, ++ /// Equal ++ CK_OP_EQUQL = 1, ++} GE_COLOR_KEY_MODE; ++ ++///Define Blending Coefficient ++typedef enum ++{ ++ /// 1 ++ COEF_ONE = 0, ++ /// constant ++ COEF_CONST = 1, ++ /// source alpha ++ COEF_ASRC = 2, ++ /// destination alpha ++ COEF_ADST = 3, ++ /// 0 ++ COEF_ZERO = 4, ++ /// 1 - constant ++ COEF_1_CONST = 5, ++ /// 1 - source alpha ++ COEF_1_ASRC = 6, ++ /// 1 - destination alpha ++ COEF_1_ADST = 7, ++} GE_BLEND_COEF; ++ ++///Define Blending Source from ++typedef enum ++{ ++ /// constant ++ ABL_FROM_CONST = 0, ++ /// source alpha ++ ABL_FROM_ASRC = 1, ++ /// destination alpha ++ ABL_FROM_ADST = 2, ++} GE_ALPHA_SRC_FROM; ++ ++/// GE buffer format ++typedef enum ++{ ++ /// font mode I1 ++ GE_FMT_I1 = 0x0, ++ /// font mode I2 ++ GE_FMT_I2 = 0x1, ++ /// font mode I4 ++ GE_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ GE_FMT_I8 = 0x4, ++ /// color format for blinking display format ++ GE_FMT_1ABFGBG12355 = 0x7, ++ /// color format RGB565 ++ GE_FMT_RGB565 = 0x8, ++ /// color format ORGB1555 ++ GE_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ GE_FMT_ARGB4444 = 0xa, ++ /// color format for blinking display format ++ GE_FMT_1BAAFGBG123433 = 0xb, ++ /// color format ARGB1555 of destination buffer ++ GE_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ GE_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ GE_FMT_ARGB8888 = 0xf ++}GE_Buffer_Format; ++ ++///Define Drawing type ++typedef enum ++{ ++ /// none ++ GE_DRAW_NONE = 0, ++ /// draw line ++ GE_DRAW_LINE = 1, ++ /// rectangle fill ++ GE_DRAW_RECTANGLE = 3, ++ /// bitblt ++ GE_DRAW_BITBLT = 4, ++}GE_DRAW_TYPE; ++ ++//------------------------------------------------- ++/// Define color ++typedef struct ++{ ++ /// Blue ++ U8 b; ++ /// Green ++ U8 g; ++ /// Red ++ U8 r; ++ /// Alpha ++ U8 a; ++} GE_RGB_COLOR; ++ ++typedef struct ++{ ++ U32 Y:8; ++ U32 U:4; ++ U32 V:4; ++} GE_YUV_COLOR; ++ ++typedef struct{ ++ union{ ++ GE_RGB_COLOR rgb; ++ GE_YUV_COLOR yuv; ++ }; ++} GE_COLOR; ++ ++//------------------------------------------------- ++/// Define the start color & end color ++typedef struct ++{ ++ /// start color ++ GE_RGB_COLOR color_s; ++ /// end color ++ GE_RGB_COLOR color_e; ++} GE_COLOR_RANGE; ++ ++//------------------------------------------------- ++/// Define the position of one point. ++typedef struct GE_POINT_s ++{ ++ /// X address ++ U16 x; ++ /// Y address ++ U16 y; ++} GE_POINT_t; ++ ++//------------------------------------------------- ++/// Specify the blink data ++#if 0 ++ // 1 B A A Fg Bg ++ // 1 2 3 4 3 3 ++typedef struct ++{ ++ /// BG color (for blink mode use) ++ U8 background; ++ /// FG color (for blink mode use) ++ U8 foreground; ++ /// Control flag\n ++ union{ ++ U16 ctrl_flag; ++ struct{ ++ U16 BlinkAlpha:4; ++ U16 Alpha:3; ++ U16 Blink:2; ++ U16 reserved:7; ++ }Bits; ++ }; ++ ++} GE_BLINK_DATA; ++#else ++ // 1 A B Fg Bg ++ // 1 2 3 5 5 ++typedef struct ++{ ++ /// BG color (for blink mode use) ++ U8 background; // 5 bits ++ /// FG color (for blink mode use) ++ U8 foreground; // 5 bits ++ /// Control flag\n ++ union{ ++ U16 ctrl_flag; ++ struct{ ++ U16 Blink:3; // 3 bits ++ U16 Alpha:2; // 2 bits ++ U16 reserved1:11; ++ } Bits; ++ }; ++ ++} GE_BLINK_DATA; ++ ++#endif ++ ++/// Define the start blink color & end blink color. ++typedef struct ++{ ++ /// start blink color ++ GE_BLINK_DATA blink_data_s; ++ /// end blink color ++ GE_BLINK_DATA blink_data_e; ++} GE_BLINK_DATA_RANGE; ++ ++//------------------------------------------------- ++//------------------------------------------------- ++#define GELINE_FLAG_COLOR_CONSTANT 0x00 ++#define GELINE_FLAG_COLOR_GRADIENT 0x01 ++/// Define the attribute of line. ++typedef struct ++{ ++ /// start X address ++ U16 x1; ++ /// Start Y address ++ U16 y1; ++ /// End X address ++ U16 x2; ++ /// End Y address ++ U16 y2; ++ /// Color format ++ GE_Buffer_Format fmt; ++ union ++ { ++ /// Color ++ ///For all RGB color, the color set as the ARGB8888 format.\n ++ ///Each color component need to shift to high bit.\n ++ ///Use ARGB1555 as the example, the source color key as the following:\n ++ ///ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++ ///colorRange.color_s --> A0000000RRRRR000GGGGG000BBBBB000 (every character represents one bit)\n\n ++ ///For GE_FMT_I8 format, the index set to b component (colorRange.color_s.b = b).\n ++ GE_COLOR_RANGE colorRange; ++ ///Blink attribute ++ ///For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++ GE_BLINK_DATA_RANGE blkDataRange; ++ }; ++ /// Line width ++ U32 width; ++ /// GELINE_FLAG_COLOR_CONSTANT: Constant color\n ++ /// GELINE_FLAG_COLOR_GRADIENT: Gradient color ++ U32 flag; ++ ++} GE_DRAW_LINE_INFO; ++ ++//------------------------------------------------- ++ ++/// Define the dimension of one block ++typedef struct ++{ ++ /// X start address ++ U16 x; ++ /// Y start address ++ U16 y; ++ /// width ++ U16 width; ++ /// height ++ U16 height; ++} GE_BLOCK; ++ ++ ++//------------------------------------------------- ++ ++#define GERECT_FLAG_COLOR_CONSTANT 0x0 ++#define GERECT_FLAG_COLOR_GRADIENT_X 0x1 ++#define GERECT_FLAG_COLOR_GRADIENT_Y 0x2 ++/// Define the info. of one block. ++typedef struct ++{ ++ /// dst block info ++ GE_BLOCK dstBlock; ++ /// Color format ++ GE_Buffer_Format fmt; ++ union ++ { ++ /// Color ++ ///For all RGB color, the color set as the ARGB8888 format.\n ++ ///Each color component need to shift to high bit.\n ++ ///Use ARGB1555 as the example, the source color key as the following:\n ++ ///ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++ ///color_s --> A0000000RRRRR000GGGGG000BBBBB000 (every character represents one bit)\n\n ++ ///For GE_FMT_I8 format, the index set to b component (colorRange.color_s.b = b).\n ++ GE_COLOR_RANGE colorRange; ++ ///Blink attribute ++ ///For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++ GE_BLINK_DATA_RANGE blkDataRange; ++ }; ++ ++ /// GERECT_FLAG_COLOR_CONSTANT: Constant color\n ++ /// GERECT_FLAG_COLOR_GRADIENT_X: X direction gradient color\n ++ /// GERECT_FLAG_COLOR_GRADIENT_Y: Y direction gradient color\n ++ U32 flag; ++ ++} GE_RECT_FILL_INFO; ++ ++typedef struct ++{ ++ /// dst block info ++ GE_BLOCK dstBlock; ++ /// Color format ++ GE_Buffer_Format fmt; ++ union{ ++ GE_RGB_COLOR color; ++ GE_BLINK_DATA blink_data; ++ }; ++ U32 u32LineWidth; ++} GE_OVAL_FILL_INFO; ++ ++ ++//------------------------------------------------- ++typedef enum ++{ ++ GEBLINK_NONE = 0x0, ++ GEBLINK_BACKGROUND, ++ GEBLINK_FOREGROUND, ++ GEBLINK_BOTH, ++} GE_BLINK_TYPE; ++ ++ ++//------------------------------------------------- ++typedef struct ++{ ++ U8 flag; ++ U32 delta_r; ++ U32 delta_g; ++ U32 delta_b; ++} GEColorDelta; ++ ++ ++//------------------------------------------------- ++/// Define rotation angle ++typedef enum ++{ ++ /// Do not rotate ++ GEROTATE_0 = 0, ++ /// Rotate 90 degree ++ GEROTATE_90 = 1, ++ /// Rotate 180 degree ++ GEROTATE_180 = 2, ++ /// Rotate 270 degree ++ GEROTATE_270 = 3 ++} GEROTATE_ANGLE; ++ ++ ++//============================================================================= ++// GE palette information ++//============================================================================= ++/// Define the entry of palette. ++typedef union ++{ ++ /// ARGB8888 ++ struct ++ { ++ /// B8 ++ U32 u8B: 8; ++ /// G8 ++ U32 u8G: 8; ++ /// R8 ++ U32 u8R: 8; ++ /// A8 ++ U32 u8A: 8; ++ } ARGB; ++ // 32-bit direct access. ++ U32 u32Data; ++} GePaletteEntry; ++ ++ ++//============================================================================= ++// Draw Rect info ++//============================================================================= ++/// Define the bitblt source & destination block. ++typedef struct ++{ ++ /// Source block ++ GE_BLOCK srcblk; ++ /// Destination block ++ GE_BLOCK dstblk; ++}GE_DRAW_RECT; ++ ++ ++/// Define the scaling factor for X & Y direction. ++typedef struct ++{ ++ U32 u32DeltaX; ++ U32 u32DeltaY; ++ U32 u32InitDelatX; ++ U32 u32InitDelatY; ++}GE_SCALE_INFO; ++ ++//============================================================================= ++// Data Buffer info ++//============================================================================= ++/// Data buffer info. ++typedef struct ++{ ++ /// start memory address ++ U32 u32Addr; // flat address of whole memory map ++ /// width ++ U32 u32Width; ++ /// height ++ U32 u32Height; ++ /// pitch ++ U32 u32Pitch; ++ /// Color format\n ++ /// - GE_FMT_I1\n ++ /// - GE_FMT_I2\n ++ /// - GE_FMT_I4\n ++ /// - GE_FMT_I8\n ++ /// - GE_FMT_RGB565\n ++ /// - GE_FMT_ARGB1555\n ++ /// - GE_FMT_ARGB4444\n ++ /// - GE_FMT_1BAAFGBG123433\n ++ /// - GE_FMT_ARGB8888\n ++ GE_Buffer_Format u32ColorFmt; ++} GE_BUFFER_INFO; ++ ++typedef GE_BUFFER_INFO* PGE_BUFFER_INFO; ++ ++#define GEDRAW_FLAG_DEFAULT 0x0 ++#define GEDRAW_FLAG_SCALE 0x1 ++#define GEDRAW_FLAG_DUPLICAPE 0x2 ++ ++ ++#define FB_FMT_AS_DEFAULT 0xFFFF ++ ++#define GE_DMA_WIDTH 32 ++#define GE_DMA_PITCH 16 ++ ++//============================================================================= ++// YUV color setting ++//============================================================================= ++typedef U8 GE_RGB2YUV_MODE; ++#define GE_RGB2YUV_PC_MODE ((GE_RGB2YUV_MODE)0x0) // computer mode Y: 16~ 235, UV: 0~ 240 ++#define GE_RGB2YUV_255_MODE ((GE_RGB2YUV_MODE)0x1) // To 0~ 255 ++ ++typedef U8 GE_YUV_RANGE_OUT; ++#define GE_YUV_RANGE_OUT_255 ((GE_YUV_RANGE_OUT)0x0) // To 0~ 255 ++#define GE_YUV_RANGE_OUT_PC ((GE_YUV_RANGE_OUT)0x1) // To Y: 16~ 235 ++ ++typedef U8 GE_YUV_RANGE_IN; ++#define GE_YUV_RANGE_IN_255 ((GE_YUV_RANGE_IN)0x0) // UV input range, 0~ 255 ++#define GE_YUV_RANGE_IN_127 ((GE_YUV_RANGE_IN)0x1) // UV input range, -128~ 127 ++ ++typedef U8 GE_YUV_422_FMT; ++#define GE_YUV_422_FMT_UY1VY0 ((GE_YUV_422_FMT)0x00) // CbY1CrY0 ++#define GE_YUV_422_FMT_VY1UY0 ((GE_YUV_422_FMT)0x01) // CrY1CbY0 ++#define GE_YUV_422_FMT_Y1UY0V ((GE_YUV_422_FMT)0x02) // Y1CbY0Cr ++#define GE_YUV_422_FMT_Y1VY0U ((GE_YUV_422_FMT)0x03) // Y1CrY0Cb ++ ++typedef struct ++{ ++ GE_RGB2YUV_MODE rgb2yuv_mode; ++ GE_YUV_RANGE_OUT yuv_range_out; ++ GE_YUV_RANGE_IN yuv_range_in; ++ GE_YUV_422_FMT yuv_mem_fmt_src; ++ GE_YUV_422_FMT yuv_mem_fmt_dst; ++} GE_YUV_INFO; ++ ++ ++//============================================================================= ++// GE Driver Function ++//============================================================================= ++extern void MHal_GE_Init(void); ++extern void MHal_GE_PowerOff(void); ++extern GESTATUS MHal_GE_ScreenCopy(GE_BLOCK *psrcblk, GE_BLOCK *pdstblk); ++extern GESTATUS MHal_GE_GetFrameBufferInfo(U32 *width, U32 *height, U32 *pitch, U32 *fbFmt, U32 *addr); ++extern GESTATUS MHal_GE_DrawLine(GE_DRAW_LINE_INFO *pline); ++extern GESTATUS MHal_GE_DrawOval(GE_OVAL_FILL_INFO* pOval); ++extern GESTATUS MHal_GE_RectFill(GE_RECT_FILL_INFO *pfillblock); ++extern GESTATUS MHal_GE_SetClip(GE_POINT_t* v0, GE_POINT_t* v1); ++extern GESTATUS MHal_GE_SetDither(U16 enable); ++extern GESTATUS MHal_GE_SetSrcBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte); ++extern GESTATUS MHal_GE_SetDstBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte); ++extern GESTATUS MHal_GE_SetNearestMode(U16 enable); ++extern GESTATUS MHal_GE_SetMirror(U16 isMirrorX, U16 isMirrorY); ++extern GESTATUS MHal_GE_SetROP2(U16 enable, GE_ROP2_OP eRopMode); ++extern GESTATUS MHal_GE_SetRotate(GEROTATE_ANGLE angle); ++extern GESTATUS MHal_GE_SetSrcColorKey(U16 enable, GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, void *ps_color, ++ void *pe_color); ++extern GESTATUS MHal_GE_SetDstColorKey(U16 enable, GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, void *ps_color, ++ void *pe_color); ++extern GESTATUS MHal_GE_SetAlphaSrcFrom(GE_ALPHA_SRC_FROM eMode); ++extern GESTATUS MHal_GE_SetAlphaBlending(GE_BLEND_COEF blendcoef, U8 blendfactor); ++extern GESTATUS MHal_GE_EnableAlphaBlending(U16 enable); ++extern GESTATUS MHal_GE_Line_Pattern_Reset(void); ++extern GESTATUS MHal_GE_Set_Line_Pattern(U16 enable, U8 linePattern, U8 repeatFactor); ++extern GESTATUS MHal_GE_BitBlt(GE_DRAW_RECT *drawbuf,U32 drawflag); ++extern GESTATUS MHal_GE_BitBltEx(GE_DRAW_RECT * drawbuf, U32 drawflag, GE_SCALE_INFO * ScaleInfo); ++extern GESTATUS MHal_GE_GetScaleBltInfo(GE_DRAW_RECT* pdrawbuf, GE_BLOCK* pSrcBlk, GE_BLOCK* pDstBlk, GE_SCALE_INFO * pScaleInfo); ++extern GESTATUS MHal_GE_SetIntensity(U32 id, GE_Buffer_Format fmt, U32 *pColor); ++extern GESTATUS MHal_GE_BeginDraw(void); ++extern GESTATUS MHal_GE_EndDraw(void); ++extern GESTATUS MHal_GE_YUV_Set(GE_YUV_INFO* pYuvInfo); ++extern GESTATUS MHal_GE_YUV_Get(GE_YUV_INFO* pYuvInfo); ++extern GESTATUS MHal_GE_Palette_Set(GePaletteEntry * pPalArray, U32 u32PalStart, U32 u32PalEnd); ++ ++#endif ++ +diff --git a/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_fp.c b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_fp.c +new file mode 100644 +index 00000000..9dd4d3b8 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_fp.c +@@ -0,0 +1,191 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "mach/ms_types.h" ++#include "mhal_ge.h" ++ ++ ++//******************************************************************************/ ++// This function performs integer division ++// parameter: ++// u16x: numerator ++// u16y: denominator ++// nInterger: bit count of integer ++// nFraction: bit count of fraction ++// return: a U32 value in s.nInteger.nFraction form ++//******************************************************************************/ ++U32 Divide2Fixed(U16 u16x, U16 u16y, U8 nInteger, U8 nFraction) ++{ ++ U8 neg = 0; ++ U32 mask; ++ U32 u32x; ++ U32 u32y; ++ ++ if (u16x & 0x8000) ++ { ++ u32x = 0xFFFF0000 | u16x; ++ u32x = ~u32x + 1; //convert to positive ++ neg++; ++ } ++ else ++ { ++ u32x = u16x; ++ } ++ ++ if (u16y & 0x8000) ++ { ++ u32y = 0xFFFF0000 | u16y; ++ u32y = ~u32y + 1; //convert to positive ++ neg++; ++ } ++ else ++ { ++ u32y = u16y; ++ } ++ ++ // start calculation ++ u32x = (u32x << nFraction) / u32y; ++ if (neg % 2) ++ { ++ u32x = ~u32x + 1; ++ } ++ // total bit number is: 1(s) + nInteger + nFraction ++ mask = (1 << (1 + nInteger + nFraction)) - 1; ++ u32x &= mask; ++ ++ return u32x; ++} ++ ++#if 0 ++void FixPLine_S1_11(U16 u16x, U16 u16y, LONG16_BYTE* pu16ret) ++{ ++ FLOAT_BYTE tmp; ++ U16 t, t2; ++ U8 exp; ++ ++ if(u16y==0) ++ { ++ pu16ret->u16Num = 0; ++ return; ++ } ++ tmp.fvalue = (float)u16y / (float)u16x;//TODO ++ GE_DEBUGINFO(printf("tmp: %02bx %02bx %02bx %02bx\n", tmp.u8Num[0], tmp.u8Num[1], tmp.u8Num[2], tmp.u8Num[3])); ++ ++ pu16ret->u16Num = 0; ++ if((tmp.u8Num[0]&0x80) > 0) // negative number ++ { ++ pu16ret->u8Num[0] |= 0x10; ++ } ++ ++ exp = (tmp.u8Num[0]<<1) | (tmp.u8Num[1]&0x80)>>7; ++ GE_DEBUGINFO(printf("exp = %bx\n", exp)); ++ ++ t2 = tmp.u8Num[1] & 0x7F; ++ t = 0x800 | (t2 << 4) | (tmp.u8Num[2] & 0xF0) >> 4; ++ if(exp < 127) ++ { ++ pu16ret->u16Num |= (t >> (127 - exp)); ++ } ++ else ++ { ++ pu16ret->u16Num |= (t << (exp - 127)); ++ } ++ ++ GE_DEBUGINFO(printf("FixPLine_S1_11 = %f\n", tmp.fvalue)); ++ GE_DEBUGINFO(printf("S.1.11 = %x\n", pu16ret->u16Num)); ++ ++ pu16ret->u16Num = pu16ret->u16Num << 2; ++ GE_DEBUGINFO(printf("line reg = %x\n", pu16ret->u16Num)); ++} ++ ++/******************************************************************************/ ++/******************************************************************************/ ++void FixPClr_S8_11(S16 s16color, U16 u16dis, LONG32_BYTE* pu32ret) ++{ ++ FLOAT_BYTE tmp; ++ U32 t, t2; ++ U8 exp; ++ ++ tmp.fvalue = (float)s16color / (float)u16dis;//TODO ++ ++ GE_DEBUGINFO(printf("tmp: %02bx %02bx %02bx %02bx\n", tmp.u8Num[0], tmp.u8Num[1], tmp.u8Num[2], tmp.u8Num[3])); ++ ++ pu32ret->u32Num = 0; // reset return value ++// if((tmp.u8Num[0]&0x80) > 0) // negative number ++// { ++// pu32ret->u8Num[1] = 0x8; // bit 19 ++// } ++ ++ exp = (tmp.u8Num[0]<<1) | (tmp.u8Num[1]&0x80)>>7; ++ GE_DEBUGINFO(printf("exp = %bx\n", exp)); ++ ++ t2 = tmp.u8Num[1] & 0x7F; ++ t = 0x800 | (t2 << 4) | (tmp.u8Num[2] & 0xF0) >> 4; ++ if(exp < 127) ++ { ++ pu32ret->u32Num |= (t >> (127 - exp)); ++ } ++ else ++ { ++ pu32ret->u32Num |= (t << (exp - 127)); ++ } ++ ++ if((tmp.u8Num[0]&0x80) > 0) // negative number ++ { ++ pu32ret->u32Num = 0xFFFFFFFF - pu32ret->u32Num + 1; ++ } ++ ++ GE_DEBUGINFO(printf("FixPClr_S8_11 = %f\n", tmp.fvalue)); ++ GE_DEBUGINFO(printf("S.8.11 = %Lx\n", pu32ret->u32Num)); ++ ++ pu32ret->u32Num = pu32ret->u32Num << 12; ++ GE_DEBUGINFO(printf("Color delta reg = %Lx\n", pu32ret->u32Num)); ++} ++ ++/******************************************************************************/ ++/******************************************************************************/ ++void FixPBlt_S1_15(U16 u16src, U16 u16dst, LONG16_BYTE* pu16ret) ++{ ++ U32 t2; ++ U8 exp; ++ FLOAT_BYTE tmp; ++ ++ tmp.fvalue = (float)u16src / (float)u16dst;//TODO ++ ++ GE_DEBUGINFO(printf("tmp: %02bx %02bx %02bx %02bx\n", ++ tmp.u8Num[0], tmp.u8Num[1], tmp.u8Num[2], tmp.u8Num[3])); ++ ++ exp = (tmp.u8Num[0]<<1) | (tmp.u8Num[1]&0x80)>>7; ++ GE_DEBUGINFO(printf("exp = %bx\n", exp)); ++ ++ t2 = tmp.u8Num[1] & 0x7F; ++ pu16ret->u8Num[1] = tmp.u8Num[2]; ++ pu16ret->u8Num[0] = 0x80 | t2; ++ if(exp < 127) ++ { ++ pu16ret->u16Num = (pu16ret->u16Num >> (127 - exp)); ++ } ++ else ++ { ++ pu16ret->u16Num = (pu16ret->u16Num << (exp - 127)); ++ } ++ ++ GE_DEBUGINFO(printf("FixPBlt_S1_15 = %f\n", tmp.fvalue)); ++ GE_DEBUGINFO(printf("S.1.15 = %x\n", pu16ret->u16Num)); ++} ++ ++#endif //0 +diff --git a/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_fp.h b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_fp.h +new file mode 100644 +index 00000000..fda6350f +--- /dev/null ++++ b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_fp.h +@@ -0,0 +1,33 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef DRV_FIXEDPOINT_H ++#define DRV_FIXEDPOINT_H ++ ++#include "mhal_ge_reg.h" ++ ++ ++extern U32 Divide2Fixed(U16 u16x, U16 u16y, U8 nInterger, U8 nFraction); ++ ++#if 0 ++extern void FixPLine_S1_11(MS_U16 u16x, MS_U16 u16y, LONG16_BYTE* pu16ret); ++extern void FixPClr_S8_11(MS_S16 s8color, MS_U16 u16dis, LONG32_BYTE* pu32ret); ++extern void FixPBlt_S1_15(MS_U16 u16src, MS_U16 u16dst, LONG16_BYTE* pu16ret); ++#endif ++ ++#endif +diff --git a/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_reg.h b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_reg.h +new file mode 100644 +index 00000000..b04350f0 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/ge/columbus2/mhal_ge_reg.h +@@ -0,0 +1,275 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2010 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __REGGE_H__ ++#define __REGGE_H__ ++ ++#include ++ ++#define GE_LOG_ADR 0xa1600000 ++ ++///#define REG_GE_BASE (0xA0006C00+IO_OFFSET) ++ ++#define COLUMBUS_BASE_REG_RIU_PA (0xFD000000) ++#define REG_OFFSET_SHIFT_BITS 2 ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++#include // for MKDEV() ++#include ++#include ++#include ++#include ++ ++#include "mach/ms_types.h" ++#include "mhal_ge.h" ++#include "mdrv_ge.h" ++ ++#define MDRV_NAME_GE "ge" ++#define MDRV_MAJOR_GE 124 ++#define MDRV_MINOR_GE 1 ++ ++static int MDrv_GE_Open(struct inode *inode, struct file *filp); ++static int MDrv_GE_Release(struct inode *inode, struct file *filp); ++static long MDrv_GE_IOCtl(struct file *filp, unsigned int cmd, unsigned long arg); ++ ++//------------------------------------------------------------------------------ ++// structure ++//------------------------------------------------------------------------------ ++struct file_operations _ge_fops = ++{ ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = MDrv_GE_IOCtl, ++ .open = MDrv_GE_Open, ++ .release = MDrv_GE_Release, ++}; ++ ++// ----------------------------------------------------------------------------- ++// Global variable ++// ----------------------------------------------------------------------------- ++struct cdev *g_pGEDev = NULL; ++struct class *g_pGEClass = NULL; ++ ++// ----------------------------------------------------------------------------- ++// Local function ++// ----------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------ ++// GE & PE Function ++//------------------------------------------------------------------------------ ++ ++void MDrv_GE_Init(unsigned long arg) ++{ ++ MHal_GE_Init(); ++} ++ ++void MDrv_GE_PowerOff(unsigned long arg) ++{ ++ MHal_GE_PowerOff(); ++} ++ ++int MDrv_GE_ScreenCopy(unsigned long arg) ++{ ++ GE_BLOCK geSrcBlk, geDstBlk; ++ ++ if (copy_from_user(&geSrcBlk, ((MS_GE_SCREEN_COPY __user *)arg)->pSrcBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ ++ if (copy_from_user(&geDstBlk, ((MS_GE_SCREEN_COPY __user *)arg)->pDstBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_ScreenCopy(&geSrcBlk, &geDstBlk)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_GetFrameBufferInfo(unsigned long arg) ++{ ++ U32 u32Width; ++ U32 u32Height; ++ U32 u32Pitch; ++ U32 u32FbFmt; ++ U32 u32Addr; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_GetFrameBufferInfo(&u32Width, &u32Height, &u32Pitch, &u32FbFmt, &u32Addr)) ++ { ++ __put_user(u32Width, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Width)); ++ __put_user(u32Height, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Height)); ++ __put_user(u32Pitch, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Pitch)); ++ __put_user(u32FbFmt, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32FbFmt)); ++ __put_user(u32Addr, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Addr)); ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_DrawLine(unsigned long arg) ++{ ++ GE_DRAW_LINE_INFO geDrawLineInfo; ++ ++ if (copy_from_user(&geDrawLineInfo, ((GE_DRAW_LINE_INFO __user *)arg), sizeof(GE_DRAW_LINE_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_DrawLine(&(geDrawLineInfo))) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_DrawOval(unsigned long arg) ++{ ++ GE_OVAL_FILL_INFO geOval; ++ ++ if (copy_from_user(&geOval, ((GE_OVAL_FILL_INFO __user *)arg), sizeof(GE_OVAL_FILL_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_DrawOval(&geOval)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_RectFill(unsigned long arg) ++{ ++ GE_RECT_FILL_INFO geRectFillInfo; ++ ++ if (copy_from_user(&geRectFillInfo, ((GE_RECT_FILL_INFO __user *)arg), sizeof(GE_RECT_FILL_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_RectFill(&geRectFillInfo)) ++ { ++ //printk("MDrv_GE_RectFill Success\n"); ++ return 0; ++ } ++ else ++ { ++ printk("MDrv_GE_RectFill Fail\n"); ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetClip(unsigned long arg) ++{ ++ GE_POINT_t geV0, geV1; ++ ++ if (copy_from_user(&geV0, ((MS_GE_SET_CLIP __user *)arg)->pPoint0, sizeof(GE_POINT_t))) ++ return EFAULT; ++ ++ if (copy_from_user(&geV1, ((MS_GE_SET_CLIP __user *)arg)->pPoint1, sizeof(GE_POINT_t))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetClip(&geV0, &geV1)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetDither(unsigned long arg) ++{ ++ U16 blDither; ++ ++ if (__get_user(blDither, (U16 __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetDither(blDither)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetSrcBufferInfo(unsigned long arg) ++{ ++ GE_BUFFER_INFO geBufferInfo; ++ U32 u32OffsetofByte; ++ ++ if (copy_from_user(&geBufferInfo, ((MS_GE_SET_BUFFERINFO __user *)arg)->pBufferInfo, sizeof(GE_BUFFER_INFO))) ++ return EFAULT; ++ if (__get_user(u32OffsetofByte, &(((MS_GE_SET_BUFFERINFO __user *)arg)->u32OffsetofByte))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetSrcBufferInfo(&geBufferInfo, u32OffsetofByte)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetDstBufferInfo(unsigned long arg) ++{ ++ GE_BUFFER_INFO geBufferInfo; ++ U32 u32OffsetofByte; ++ ++ if (copy_from_user(&geBufferInfo, ((MS_GE_SET_BUFFERINFO __user *)arg)->pBufferInfo, sizeof(GE_BUFFER_INFO))) ++ return EFAULT; ++ if (__get_user(u32OffsetofByte, &(((MS_GE_SET_BUFFERINFO __user *)arg)->u32OffsetofByte))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetDstBufferInfo(&geBufferInfo, u32OffsetofByte)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetNearestMode(unsigned long arg) ++{ ++ U16 bNearestMode; ++ ++ if (__get_user(bNearestMode, (U16 __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetNearestMode(bNearestMode)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetMirror(unsigned long arg) ++{ ++ MS_GE_SET_MIRROR geSetMirror; ++ ++ if (copy_from_user(&geSetMirror, (MS_GE_SET_MIRROR __user *)arg, sizeof(MS_GE_SET_MIRROR))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetMirror(geSetMirror.blIsMirrorX, geSetMirror.blIsMirrorY)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetROP2(unsigned long arg) ++{ ++ MS_GE_SET_ROP2 geSetROP2; ++ ++ if (copy_from_user(&geSetROP2, (MS_GE_SET_ROP2 __user *)arg, sizeof(MS_GE_SET_ROP2))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetROP2(geSetROP2.blEnable, geSetROP2.eRopMode)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetRotate(unsigned long arg) ++{ ++ GEROTATE_ANGLE geRotateAngle; ++ ++ if (__get_user(geRotateAngle, (GEROTATE_ANGLE __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetRotate(geRotateAngle)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetSrcColorKey(unsigned long arg) ++{ ++ U16 blEnable; ++ GE_COLOR_KEY_MODE enColorKeyMode; ++ GE_Buffer_Format enBufferFmt; ++ U32 u32PS_Color; ++ U32 u32GE_Color; ++ ++ if (__get_user(blEnable, &((MS_GE_SET_COLORKEY __user *)arg)->blEnable)) ++ return EFAULT; ++ ++ if (__get_user(enColorKeyMode, &((MS_GE_SET_COLORKEY __user *)arg)->eOPMode)) ++ return EFAULT; ++ ++ if (__get_user(enBufferFmt, &((MS_GE_SET_COLORKEY __user *)arg)->enBufferFmt)) ++ return EFAULT; ++ ++ if (__get_user(u32PS_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32PS_Color)) ++ return EFAULT; ++ ++ if (__get_user(u32GE_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32GE_Color)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetSrcColorKey(blEnable, enColorKeyMode, enBufferFmt, &u32PS_Color, &u32GE_Color)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetDstColorKey(unsigned long arg) ++{ ++ U16 blEnable; ++ GE_COLOR_KEY_MODE enColorKeyMode; ++ GE_Buffer_Format enBufferFmt; ++ U32 u32PS_Color; ++ U32 u32GE_Color; ++ ++ if (__get_user(blEnable, &((MS_GE_SET_COLORKEY __user *)arg)->blEnable)) ++ return EFAULT; ++ ++ if (__get_user(enColorKeyMode, &((MS_GE_SET_COLORKEY __user *)arg)->eOPMode)) ++ return EFAULT; ++ ++ if (__get_user(enBufferFmt, &((MS_GE_SET_COLORKEY __user *)arg)->enBufferFmt)) ++ return EFAULT; ++ ++ if (__get_user(u32PS_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32PS_Color)) ++ return EFAULT; ++ ++ if (__get_user(u32GE_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32GE_Color)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetDstColorKey(blEnable, enColorKeyMode, enBufferFmt, &u32PS_Color, &u32GE_Color)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetAlphaSrcFrom(unsigned long arg) ++{ ++ GE_ALPHA_SRC_FROM eMode; ++ ++ if (__get_user(eMode, (GE_ALPHA_SRC_FROM __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetAlphaSrcFrom(eMode)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetAlphaBlending(unsigned long arg) ++{ ++ MS_GE_SET_ALPHABLENDING geSetAlphaBlending; ++ ++ if (copy_from_user(&geSetAlphaBlending, (MS_GE_SET_ALPHABLENDING __user *)arg, sizeof(MS_GE_SET_ALPHABLENDING))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetAlphaBlending(geSetAlphaBlending.enBlendCoef, geSetAlphaBlending.u8BlendFactor)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_EnableAlphaBlending(unsigned long arg) ++{ ++ U16 blEnable; ++ ++ if (__get_user(blEnable, (U16 __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_EnableAlphaBlending(blEnable)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_Line_Pattern_Reset(unsigned long arg) ++{ ++ if (GESTATUS_SUCCESS == MHal_GE_Line_Pattern_Reset()) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_Set_Line_Pattern(unsigned long arg) ++{ ++ U16 blEnable; ++ U8 u8LinePattern; ++ U8 u8RepeatFactor; ++ ++ if (__get_user(blEnable, &(((MS_GE_SET_LINEPATTERN __user *)arg)->blEnable))) ++ return EFAULT; ++ if (__get_user(u8LinePattern, &(((MS_GE_SET_LINEPATTERN __user *)arg)->u8LinePattern))) ++ return EFAULT; ++ if (__get_user(u8RepeatFactor, &(((MS_GE_SET_LINEPATTERN __user *)arg)->u8RepeatFactor))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_Set_Line_Pattern(blEnable, u8LinePattern, u8RepeatFactor)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_BitBlt(unsigned long arg) ++{ ++ GE_DRAW_RECT geDrawRect; ++ U32 u32DrawFlag; ++ ++ if (copy_from_user(&geDrawRect, ((MS_GE_SET_BITBLT __user *)arg)->pGEDrawRect, sizeof(GE_DRAW_RECT))) ++ return EFAULT; ++ if (__get_user(u32DrawFlag, &(((MS_GE_SET_BITBLT __user *)arg)->u32DrawFlag))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_BitBlt(&geDrawRect, u32DrawFlag)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_BitBltEx(unsigned long arg) ++{ ++ GE_DRAW_RECT geDrawRect; ++ U32 u32DrawFlag; ++ GE_SCALE_INFO geScaleInfo; ++ ++ if (copy_from_user(&geDrawRect, ((MS_GE_SET_BITBLTEX __user *)arg)->pDrawRect, sizeof(GE_DRAW_RECT))) ++ return EFAULT; ++ if (__get_user(u32DrawFlag, &(((MS_GE_SET_BITBLTEX __user *)arg)->u32DrawFlag))) ++ return EFAULT; ++ if (copy_from_user(&geScaleInfo, ((MS_GE_SET_BITBLTEX __user *)arg)->pScaleInfo, sizeof(GE_SCALE_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_BitBltEx(&geDrawRect, u32DrawFlag, &geScaleInfo)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_GetScaleBltInfo(unsigned long arg) ++{ ++ GE_DRAW_RECT geDrawRect; ++ GE_BLOCK geSrcBlk; ++ GE_BLOCK geDstBlk; ++ GE_SCALE_INFO geScaleInfo; ++ ++ if (copy_from_user(&geDrawRect, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pDrawRect, sizeof(GE_DRAW_RECT))) ++ return EFAULT; ++ if (copy_from_user(&geSrcBlk, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pSrcBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ if (copy_from_user(&geDstBlk, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pDstBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ if (copy_from_user(&geScaleInfo, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pScaleInfo, sizeof(GE_SCALE_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_GetScaleBltInfo(&geDrawRect, &geSrcBlk, &geDstBlk, &geScaleInfo)) ++ { ++ unsigned long r = 0; ++ r = copy_to_user(((MS_GE_GET_SCALEBLTINFO __user *)arg)->pSrcBlk, &geSrcBlk, sizeof(GE_BLOCK)); ++ if (r) return r; ++ r = copy_to_user(((MS_GE_GET_SCALEBLTINFO __user *)arg)->pDstBlk, &geDstBlk, sizeof(GE_BLOCK)); ++ if (r) return r; ++ r = copy_to_user(((MS_GE_GET_SCALEBLTINFO __user *)arg)->pScaleInfo, &geScaleInfo, sizeof(GE_SCALE_INFO)); ++ if (r) return r; ++ ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetIntensity(unsigned long arg) ++{ ++ U32 u32ID; ++ GE_Buffer_Format enBufferFmt; ++ U32 u32Color; ++ ++ if (__get_user(u32ID, &(((MS_GE_SET_INTENSITY __user *)arg)->u32ID))) ++ return EFAULT; ++ if (__get_user(enBufferFmt, &(((MS_GE_SET_INTENSITY __user *)arg)->enBufferFmt))) ++ return EFAULT; ++ if (__get_user(u32Color, ((MS_GE_SET_INTENSITY __user *)arg)->pu32Color)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetIntensity(u32ID, enBufferFmt, &u32Color)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_BeginDraw(unsigned long arg) ++{ ++ if (GESTATUS_SUCCESS == MHal_GE_BeginDraw()) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_EndDraw(unsigned long arg) ++{ ++ if (GESTATUS_SUCCESS == MHal_GE_EndDraw()) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_YUV_Set(unsigned long arg) ++{ ++ GE_YUV_INFO geYUVInfo; ++ if (copy_from_user(&geYUVInfo, (GE_BUFFER_INFO __user *)arg, sizeof(geYUVInfo))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_YUV_Set(&geYUVInfo)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_YUV_Get(unsigned long arg) ++{ ++ GE_YUV_INFO geYUVInfo; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_YUV_Get(&geYUVInfo)) ++ { ++ return copy_to_user(( GE_BUFFER_INFO __user *)arg, &geYUVInfo, sizeof(GE_BUFFER_INFO)); ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_Palette_Set(unsigned long arg) ++{ ++ GePaletteEntry *pGePalArray; ++ U32 u32PalStart; ++ U32 u32PalEnd; ++ U32 u32PalSize; ++ int iRet = 0; ++ ++ if (__get_user(u32PalStart, &((MS_GE_SET_PALETTE __user *)arg)->u32PalStart)) ++ iRet = EFAULT; ++ if (__get_user(u32PalEnd, &((MS_GE_SET_PALETTE __user *)arg)->u32PalEnd)) ++ iRet = EFAULT; ++ ++ u32PalSize = u32PalEnd - u32PalStart + 1; ++ ++ pGePalArray = kmalloc(sizeof(GePaletteEntry) * u32PalSize, GFP_KERNEL); ++ ++ if (pGePalArray) ++ { ++ if (copy_from_user(pGePalArray, ((MS_GE_SET_PALETTE __user *)arg)->pPalArray, sizeof(GePaletteEntry)*u32PalSize)) ++ { ++ iRet = EFAULT; ++ } ++ ++ if (MHal_GE_Palette_Set(pGePalArray, u32PalStart, u32PalEnd)) ++ { ++ iRet = EFAULT; ++ } ++ ++ kfree(pGePalArray); ++ } ++ else ++ { ++ iRet = EFAULT; ++ } ++ ++ return iRet; ++} ++ ++ ++// ----------------------------------------------------------------------------- ++// Device Methods ++// ----------------------------------------------------------------------------- ++ ++/* ++ * Open and close ++ */ ++ ++int MDrv_GE_Open(struct inode *inode, struct file *filp) ++{ ++ struct cdev *pDev = inode->i_cdev; ++ filp->private_data = pDev; /* for other methods */ ++ ++ printk("GE opens successfully\n"); ++ ++ return 0; /* success */ ++} ++ ++int MDrv_GE_Release(struct inode *inode, struct file *filp) ++{ ++ printk("GE closes successfully\n"); ++ ++ return 0; ++} ++ ++extern void dummyRegWrite( void ) ; ++extern void outGE_WaitAvailableCMDQueue(void); ++ ++long MDrv_GE_IOCtl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ /* ++ * extract the type and number bitfields, and don't decode ++ * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ */ ++ if (_IOC_TYPE(cmd) != MDRV_GE_IOC_MAGIC) { ++ printk("IOCtl Type Error!!! (Cmd=%x)\n",cmd); ++ return -ENOTTY; ++ } ++ if (_IOC_NR(cmd) > MDRV_GE_IOC_MAXNR) { ++ printk("IOCtl NR Error!!! (Cmd=%x)\n",cmd); ++ return -ENOTTY; ++ } ++ ++ /* ++ * the direction is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. `Type' is user-oriented, while ++ * access_ok is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ if (err) { ++ printk("IOCtl Error!!! (cmd=%x)\n",cmd); ++ return -EFAULT; ++ } ++ ++ switch(cmd) { ++ case MDRV_GE_IOC_INIT: ++ MDrv_GE_Init(arg); ++ break; ++ ++ case MDRV_GE_IOC_POWER_OFF: ++ MDrv_GE_PowerOff(arg); ++ break; ++ ++ case MDRV_GE_IOC_SCREEN_COPY: ++ retval = MDrv_GE_ScreenCopy(arg); ++ break; ++ ++ case MDRV_GE_IOC_GET_FRAMEBUFFERINFO: ++ retval = MDrv_GE_GetFrameBufferInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_DRAW_LINE: ++ retval = MDrv_GE_DrawLine(arg); ++ break; ++ ++ case MDRV_GE_IOC_DRAW_OVAL: ++ retval = MDrv_GE_DrawOval(arg); ++ break; ++ ++ case MDRV_GE_IOC_RECT_FILL: ++ MDrv_GE_RectFill(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_CLIP: ++ MDrv_GE_SetClip(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_DITHER: ++ MDrv_GE_SetDither(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_SRCBUFFERINO: ++ MDrv_GE_SetSrcBufferInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_DSTBUFFERINO: ++ MDrv_GE_SetDstBufferInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_NEARESTMODE: ++ MDrv_GE_SetNearestMode(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_MIRROR: ++ MDrv_GE_SetMirror(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ROP2: ++ MDrv_GE_SetROP2(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ROTATE: ++ MDrv_GE_SetRotate(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_SRCCOLORKEY: ++ MDrv_GE_SetSrcColorKey(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_DSTCOLORKEY: ++ MDrv_GE_SetDstColorKey(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ALPHASRCFROM: ++ MDrv_GE_SetAlphaSrcFrom(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ALPHABLENDING: ++ MDrv_GE_SetAlphaBlending(arg); ++ break; ++ ++ case MDRV_GE_IOC_ENABLE_ALPHABLENDING: ++ MDrv_GE_EnableAlphaBlending(arg); ++ break; ++ ++ case MDRV_GE_IOC_LINEPATTERN_RESET: ++ MDrv_GE_Line_Pattern_Reset(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_LINEPATTERN: ++ MDrv_GE_Set_Line_Pattern(arg); ++ break; ++ ++ case MDRV_GE_IOC_BITBLT: ++ MDrv_GE_BitBlt(arg); ++ break; ++ ++ case MDRV_GE_IOC_BITBLTEX: ++ MDrv_GE_BitBltEx(arg); ++ break; ++ ++ case MDRV_GE_IOC_Get_SCALEBLTINFO: ++ MDrv_GE_GetScaleBltInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_INTENSITY: ++ MDrv_GE_SetIntensity(arg); ++ break; ++ ++ case MDRV_GE_IOC_BEGIN_DRAW: ++ MDrv_GE_BeginDraw(arg); ++ break; ++ ++ case MDRV_GE_IOC_END_DRAW: ++ MDrv_GE_EndDraw(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_YUV: ++ MDrv_GE_YUV_Set(arg); ++ break; ++ ++ case MDRV_GE_IOC_GET_YUV: ++ MDrv_GE_YUV_Get(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_PALETTE: ++ MDrv_GE_Palette_Set(arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ printk("Unknow IOCTL %x\n",cmd); ++ return -ENOTTY; ++ } ++ ++ outGE_WaitAvailableCMDQueue(); ++ ++ dummyRegWrite() ; ++ ++ return retval; ++} ++ ++static int __init MDrv_GE_Module_Init(void) ++{ ++ int err, devno = MKDEV(MDRV_MAJOR_GE, MDRV_MINOR_GE); ++ ++ printk("GE driver inits\n"); ++ ++ /* register the 'dummy_dev' char device */ ++ g_pGEDev = cdev_alloc(); ++ cdev_init(g_pGEDev, &_ge_fops); ++ ++ g_pGEDev->owner = THIS_MODULE; ++ ++ err = cdev_add(g_pGEDev, devno, 1); ++ if (err != 0) ++ printk("dummy pci device register failed!\n"); ++ ++ /* creating your own class */ ++ g_pGEClass = class_create(THIS_MODULE, "ge"); ++ if(IS_ERR(g_pGEClass)) { ++ printk("Err: failed in creating class.\n"); ++ return -1; ++ } ++ ++ /* register your own device in sysfs, and this will cause udevd to create corresponding device node */ ++ device_create(g_pGEClass, NULL, devno, NULL, "ge"); ++ ++ // Maybe need to move to MHal_GE_Module_Init ++ MHal_GE_Init(); ++ ++ return 0; ++} ++ ++static void __exit MDrv_GE_Module_Exit(void) ++{ ++ cdev_del(g_pGEDev); ++ ++ device_destroy(g_pGEClass, MKDEV(MDRV_MAJOR_GE, MDRV_MINOR_GE)); ++ class_destroy(g_pGEClass); ++ ++ printk("GE driver exits\n"); ++} ++ ++module_init(MDrv_GE_Module_Init); ++module_exit(MDrv_GE_Module_Exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GE driver"); ++MODULE_LICENSE("MSTAR"); +diff --git a/drivers/mstar/fb/cedric/gop/Makefile b/drivers/mstar/fb/cedric/gop/Makefile +new file mode 100644 +index 00000000..852db369 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_MS_FB_CEDRIC) += hal/ ++ +diff --git a/drivers/mstar/fb/cedric/gop/hal/cedric_r2.h b/drivers/mstar/fb/cedric/gop/hal/cedric_r2.h +new file mode 100644 +index 00000000..dcd280ab +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/hal/cedric_r2.h +@@ -0,0 +1,439 @@ ++// $Change: 627140 $ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2012 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// cedric_QST.h ++// ++// DESCRIPTION ++// ++// ++// HISTORY ++//----------------------------------------------------------------------------- ++ ++#ifndef __CEDRIC_R2_H__ ++#define __CEDRIC_R2_H__ ++ ++ ++//------------------------------------------------------------------------------ ++// Macro ++//------------------------------------------------------------------------------ ++#include "platform.h" ++ ++#define HK_CNTROL_CAR_BACKING ++//display related ++//rtk qstart related--mailbox ++ ++#define DETECT_METHOD 1 ++// 0 for interrupt from rtk ++// 1 for polling mailbox ++ ++#define QST_ALWAYS_RUN 1 ++ ++ ++#define TOKEN_GET 0x08 ++#define CAR_MODE 0x04 ++ ++ ++#define MBX_TX (0X41) //HOSTKEEPER_MBX ++#define MBX_RX (0x42) //CARBACKING_MBX ++#define MBX_TOUCH_X (0X43) ++#define MBX_TOUCH_Y (0X44) ++ ++ ++#define CEDRIC_BASE_REG_MBX_PA GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x81980) ++#define REG_MBX_BASE GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,0X40) ++#define REG_MBX_RX GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_RX) ++#define REG_MBX_TX GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TX) ++#define REG_MBX_TOUCH_X GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TOUCH_X) ++#define REG_MBX_TOUCH_Y GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TOUCH_Y) ++ ++ ++#define LOOP_THRESHOLD 8 ++#define CarBackingState (1<<2) ++ ++ ++ ++typedef struct ++{ ++/* ++h0040 h0040 15 0 reg_mb0_0 ++*/ ++ U16 reg_mb0_0; ++ U16 u16REG_RESERVED_40; ++ ++/* ++ ++h0041 h0041 15 0 reg_mb0_1 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_1; /* 00h */ ++ struct ++ { ++ volatile U16 token :4; ++ volatile U16 touch_flag :1; ++ //#define VALID 1 ++ //#define INVALID 0 ++ volatile U16 bt_flag :1; ++ volatile U16 suspend_flag :1; ++ volatile U16 Os_flag :1; ++ volatile U16 boot_type :1; ++ volatile U16 cfg_loaded :1; ++ volatile U16 Os_reset :1; ++ volatile U16 reserve41 :5; ++ //bit 3~f reserve ++ }; ++ }; ++ U16 u16REG_RESERVED_41; ++ ++/* ++ ++h0042 h0042 15 0 reg_mb0_2 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_2; /* 00h */ ++ struct ++ { ++ volatile U16 disp_inited :1; ++ //#define DISP_INIT 1 ++ //#define DISP_NON 0 ++ ++ volatile U16 cvbs_in :1; //represent cvbs in is ok or not ++ //#define CVBS_IN_OK 1 ++ //#define CVBS_IN_NON 0 ++ ++ volatile U16 carbacking_status :1; ++ //value as enum CAR_BACKING_MODE ++ ++ volatile U16 token_switch :1; ++ //#define TOKEN_CP 0 //co processor ++ //#define TOKEN_HK 1 //host keeper ++ volatile U16 app_launch :4; ////max support 15 apps ++ ++ volatile U16 bt_call_rsp :2; // give response to ARM OS ++ ++ volatile U16 mmi_task_running :1; //mmi task exist or not ++ volatile U16 reserve42 :5; ++ ++ }; ++ }; ++ U16 u16REG_RESERVED_42; ++ ++/* ++h0043 h0043 15 0 reg_mb0_3 ++*/ ++ U16 u16MBX_TOUCH_X; ++ U16 u16REG_RESERVED_43; ++ ++/* ++h0044 h0044 15 0 reg_mb0_4 ++*/ ++ U16 u16MBX_TOUCH_Y; ++ U16 u16REG_RESERVED_44; ++ ++/* ++h0045 h0045 15 0 reg_mb0_5 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_5; /* 00h */ ++ struct ++ { ++ volatile U16 rtk_heart :1; ++ volatile U16 reserve45 :15; ++ ++ }; ++ }; ++ U16 u16REG_RESERVED_45; ++ ++/* ++h0046 h0046 15 0 reg_mb0_6 ++*/ ++ U16 reg_mb0_6; ++ U16 u16REG_RESERVED_46; ++ ++/* ++h0047 h0047 15 0 reg_mb0_7 ++*/ ++ U16 reg_mb0_7; ++ U16 u16REG_RESERVED_47; ++ ++/* ++h0048 h0048 15 0 reg_mb0_8 ++*/ ++ U16 reg_mb0_8; ++ U16 u16REG_RESERVED_48; ++ ++/* ++h0049 h0049 15 0 reg_mb0_9 ++*/ ++ U16 reg_mb0_9; ++ U16 u16REG_RESERVED_49; ++ ++/* ++h004a h004a 15 0 reg_mb0_a ++*/ ++ U16 reg_mb0_a; ++ U16 u16REG_RESERVED_4a; ++ ++/* ++h004b h004b 15 0 reg_mb0_b ++*/ ++ U16 reg_mb0_b; ++ U16 u16REG_RESERVED_4b; ++ ++/* ++h004c h004c 15 0 reg_mb0_c ++*/ ++ U16 reg_mb0_c; ++ U16 u16REG_RESERVED_4c; ++ ++/* ++h004d h004d 15 0 reg_mb0_d ++*/ ++ U16 reg_mb0_d; ++ U16 u16REG_RESERVED_4d; ++ ++/* ++h004e h004e 15 0 reg_mb0_e ++*/ ++ U16 reg_mb0_e; ++ U16 u16REG_RESERVED_4e; ++ ++/* ++h004f h004f 15 0 reg_mb0_f ++*/ ++ U16 reg_mb0_f; ++ U16 u16REG_RESERVED_4f; ++ ++/* ++h0050 h0050 15 0 reg_mb0_10 ++*/ ++ U16 reg_mb0_10; ++ U16 u16REG_RESERVED_50; ++ ++/* ++h0051 h0051 15 0 reg_mb0_11 ++*/ ++ U16 reg_mb0_11; ++ U16 u16REG_RESERVED_51; ++ ++/* ++h0052 h0052 15 0 reg_mb0_12 ++*/ ++ U16 reg_mb0_12; ++ U16 u16REG_RESERVED_52; ++ ++/* ++h0053 h0053 15 0 reg_mb0_13 ++*/ ++ U16 reg_mb0_13; ++ U16 u16REG_RESERVED_53; ++ ++/* ++h0054 h0054 15 0 reg_mb0_14 ++*/ ++ U16 reg_mb0_14; ++ U16 u16REG_RESERVED_54; ++ ++/* ++h0055 h0055 15 0 reg_mb0_15 ++*/ ++ U16 reg_mb0_15; ++ U16 u16REG_RESERVED_55; ++ ++/* ++h0056 h0056 15 0 reg_mb0_16 ++*/ ++ U16 reg_mb0_16; ++ U16 u16REG_RESERVED_56; ++ ++/* ++h0057 h0057 15 0 reg_mb0_17 ++*/ ++ U16 reg_mb0_17; ++ U16 u16REG_RESERVED_57; ++ ++/* ++h0058 h0058 15 0 reg_mb0_18 ++*/ ++ U16 reg_mb0_18; ++ U16 u16REG_RESERVED_58; ++ ++/* ++h0059 h0059 15 0 reg_mb0_19 ++*/ ++ U16 reg_mb0_19; ++ U16 u16REG_RESERVED_59; ++ ++/* ++h005A h005A 15 0 reg_mb0_1A ++*/ ++ U16 reg_mb0_1A; ++ U16 u16REG_RESERVED_5a; ++ ++/* ++h005B h005B 15 0 reg_mb0_1B ++*/ ++ U16 reg_mb0_1B; ++ U16 u16REG_RESERVED_5b; ++ ++/* ++h005C h005C 15 0 reg_mb0_1C ++*/ ++ U16 reg_mb0_1C; ++ U16 u16REG_RESERVED_5c; ++ ++/* ++h005D h005D 15 0 reg_mb0_1D ++*/ ++ U16 reg_mb0_1D; ++ U16 u16REG_RESERVED_5d; ++ ++/* ++h005E h005E 15 0 reg_mb0_1E ++*/ ++ U16 reg_mb0_1E; ++ U16 u16REG_RESERVED_5e; ++ ++/* ++h005f h005f 15 0 reg_mb0_1f ++*/ ++ U16 reg_mb0_1f; ++ U16 u16REG_RESERVED_5f; ++ ++/* ++h0060 h0060 15 0 reg_mb0_20 ++*/ ++ U16 reg_mb0_20; ++ U16 u16REG_RESERVED_60; ++ ++/* ++h0061 h0061 15 0 reg_mb0_21 ++*/ ++ U16 reg_mb0_21; ++ U16 u16REG_RESERVED_61; ++ ++/* ++h0062 h0062 15 0 reg_mb0_22 ++*/ ++ U16 reg_mb0_22; ++ U16 u16REG_RESERVED_62; ++ ++/* ++h0063 h0063 15 0 reg_mb0_23 ++*/ ++ U16 reg_mb0_23; ++ U16 u16REG_RESERVED_63; ++ ++/* ++h0064 h0064 15 0 reg_mb0_24 ++*/ ++ U16 reg_mb0_24; ++ U16 u16REG_RESERVED_64; ++ ++/* ++h0065 h0065 15 0 reg_mb0_25 ++*/ ++ U16 reg_mb0_25; ++ U16 u16REG_RESERVED_65; ++ ++/* ++h0066 h0066 15 0 reg_mb0_26 ++*/ ++ U16 reg_mb0_26; ++ U16 u16REG_RESERVED_66; ++ ++/* ++h0067 h0067 15 0 reg_mb0_27 ++*/ ++ U16 reg_mb0_27; ++ U16 u16REG_RESERVED_67; ++ ++/* ++h0068 h0068 15 0 reg_mb0_28 ++*/ ++ U16 reg_mb0_28; ++ U16 u16REG_RESERVED_68; ++ ++/* ++h0069 h0069 15 0 reg_mb0_29 ++*/ ++ U16 reg_mb0_29; ++ U16 u16REG_RESERVED_69; ++ ++/* ++h006A h006A 15 0 reg_mb0_2A ++*/ ++ U16 reg_mb0_2A; ++ U16 u16REG_RESERVED_6a; ++ ++/* ++h006B h006B 15 0 reg_mb0_2B ++*/ ++ U16 reg_mb0_2B; ++ U16 u16REG_RESERVED_6b; ++ ++/* ++h006C h006C 15 0 reg_mb0_2C ++*/ ++ U16 reg_mb0_2C; ++ U16 u16REG_RESERVED_6c; ++ ++/* ++h006D h006D 15 0 reg_mb0_2D ++*/ ++ U16 reg_mb0_2D; ++ U16 u16REG_RESERVED_6d; ++ ++/* ++h006E h006E 15 0 reg_mb0_2E ++*/ ++ U16 reg_mb0_2E; ++ U16 u16REG_RESERVED_6e; ++ ++/* ++h006F h006F 15 0 reg_mb0_2F ++*/ ++ U16 reg_mb0_2F; ++ U16 u16REG_RESERVED_6f; ++ ++/* ++*/ ++}REG_MBX_st,*PREG_MBX_st; ++ ++ ++ ++ ++enum ++{ ++ BACK, ++ FORWARD, ++ DIR_NONE, ++ DIR_NUM = DIR_NONE, ++}; ++enum ++{ ++ NON_event = 0, ++ RTOS_event, ++ USER_event, ++ GOP_refresh_event, ++}; ++ ++enum ++{ ++ HK_PREPARE, ++ HK_START , ++ HK_ALIVE, ++ USR_OP_START, ++ USR_OP_BACK, ++ USR_OP_FORWARD, ++ ++}; ++ ++ ++#endif //__CEDRIC_QST__ +\ No newline at end of file +diff --git a/drivers/mstar/fb/cedric/gop/hal/gop_c2_reg.h b/drivers/mstar/fb/cedric/gop/hal/gop_c2_reg.h +new file mode 100644 +index 00000000..a2999814 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/hal/gop_c2_reg.h +@@ -0,0 +1,280 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME gop_c2_reg.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++ ++ ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define COLUMBUS_BASE_REG_RIU_PA (0x1F000000) ++#define CLKG0_REG_BASE_PA (0x100B00) ++ ++#define RIU_BASE (0xA0000000) ++ ++ ++#define CEDRIC_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080F80) ++#define CHICAGO_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x001A80) ++ ++// same as cedric ++#define mdrv_BASE_REG_GOP_PA CEDRIC_BASE_REG_GOP_PA ++ ++#define mdrv_BASE_REG_CHIPTOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080580) ++ ++#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120200/2)) ++#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120300/2)) ++#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120400/2)) ++#define mdrv_BASE_REG_GOP10_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120500/2)) ++#define mdrv_BASE_REG_GOP11_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120600/2)) ++#define mdrv_BASE_REG_GOP12_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120700/2)) ++#define mdrv_BASE_REG_GOP20_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120800/2)) ++#define mdrv_BASE_REG_GOP21_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120900/2)) ++#define mdrv_BASE_REG_GOP22_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120A00/2)) ++#define mdrv_BASE_REG_GOP30_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120B00/2)) ++#define mdrv_BASE_REG_GOP31_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120C00/2)) ++#define mdrv_BASE_REG_GOP32_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120D00/2)) ++ ++#define mdrv_REG_GOP31_7E GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x7E) ++#define mdrv_REG_GOP31_7F GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x7F) ++#define mdrv_REG_GOP01_WIN GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x00) ++#define mdrv_REG_GOP31_WIN GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x00) ++#define mdrv_REG_GOP01_ALPHA GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x0A) ++#define mdrv_REG_GOP01_7F GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x7F) ++#define mdrv_REG_GOP31_ALPHA GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x0A) ++ ++#define mdrv_GWin0_Disable (0xFFFE) ++#define mdrv_GWIN0_Enable (0x1) ++ ++#define mdrv_ENABLE_CONST_ALPHA (~(0x1<<14)) ++//fomrat define ++ ++#define RGB1555_Blink 0x0000 ++#define RGB565 0x0010 ++#define ARGB4444 0x0020 ++#define _2266 0x0030 ++#define _8Bit_Palette 0x0040 ++ ++#define RGBA8888 0x0050 ++ ++#define ARGB1555 0x0060 ++ ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++#define ARGB8888 0x0070 ++#endif ++ ++#define RGB1555_UV7Y8 0x0080 ++#define UV8Y8 0x0090 ++#define RGBA5551 0x00A0 ++#define RGBA4444 0x00B0 ++ ++//------------------------------------------------------------------------------ ++// GOP ++//------------------------------------------------------------------------------ ++// Bank 0 ++// REG_GOP_00 ++#define GOP_SOFT_RESET 0x0001 ++#define GOP_VS_INV 0x0002 ++#define GOP_HS_INV 0x0004 ++#define GOP_DISPLAY_MODE 0x0008 ++#define GOP_FIELD_INV 0x0010 ++#define GOP_TEST_PATTENR_MODE 0x0040 ++#define GOP_5541_EN 0x0080 // RGB5541 alpha mask mode enable, only for RGB1555 Data type ++#define GOP_REG_OUTPUT_READY 0x0100 ++ ++#define GOP_GENSHOT_FAST 0x0200 ++#define GOP_YUVOUT 0x0400 ++#define GOP_RGB_Transparent_color_enable 0x0800 ++ ++#define GOP_HS_MASK 0x4000 ++#define GOP_ALPHA_INV 0x8000 ++ ++#define GOP_ALPHA_MASK 0x7F00 ++#define GOP_ALPHA 0x3F00 ++#define GOP_PIXEL_ALPHA_EN 0x4000 ++ ++#define GWIN_display_mode_progress 0x0008 ++#define GWIN_display_mode_interlace 0x0000 ++ ++ ++// REG_GOP_01 ++#define GOP_DST_IP_MAIN 0x0000 ++#define GOP_DST_IP_SUB 0x0001 ++#define GOP_DST_OP 0x0002 ++#define GOP_DST_MVOP 0x0003 ++#define GOP_DST_SC1_IP_MAIN 0x0004 ++#define GOP_DST_SC1_OP 0x0005 ++ ++ ++ ++#define GOP_DMA_LEN_8 0x0000 ++#define GOP_DMA_LEN_16 0x0004 ++#define GOP_DMA_LEN_32 0x0008 ++#define GOP_DMA_LEN_ALL 0x000C ++#define GOP_MIU_TSH_1 0x0010 ++#define GOP_REGDMA_INTERVAL_START 0x0300 ++#define GOP_REGDMA_INTERVAL_END 0x5000 ++ ++// REG_GOP_02 ++#define GOP_BLINK_DISABLE 0x0000 ++#define GOP_BLINK_ENABLE 0x8000 ++ ++// REG_GOP_06 ++#define GOP_REGDMA_END 0x0034 ++ ++// REG_GOP_07 ++#define GOP_REGDMA_STR 0x0000 ++ ++//REG_GOP_0F ++ ++ ++#define AMBER3_GOP_HSYNC_PIPE_DLY 0x00E5 ++#define CEDRIC_GOP_HSYNC_PIPE_DLY 0x0070 ++#define AMBER3_GOP_HSYNC_PIPE_DLY 0x00E5 ++#define CEDRIC_GOP_HSYNC_PIPE_DLY 0x0070 ++#define CHICAGO_GOP_HSYNC_PIPE_DLY 0x000B ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++#define GOP_HSYNC_PIPE_DLY_FOR_SC1_OP 0x00A0 ++#define HSYNC_PIPE_DLY_FOR_SC0_2GOP 0x0044 ++ ++ ++ ++// same as cedric ++#define GOP_HSYNC_PIPE_DLY CEDRIC_GOP_HSYNC_PIPE_DLY ++ ++ ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++ ++// REG_GOP_20 ++#define GOP_GWIN_HIGH_PRI_0 0x0000 ++#define GOP_GWIN_HIGH_PRI_1 0x0001 ++ ++ ++ ++#define GOP_STRETCH_HST 0x0000 ++ ++ ++// REG_GOP_34 ++#define GOP_STRETCH_VST 0x0000 ++ ++// REG_GOP_35 ++#define GOP_STRETCH_HRATIO 0x1000 ++ ++// REG_GOP_36 ++#define GOP_STRETCH_VRATIO 0x1000 ++ ++// REG_GOP_38 ++#define GOP_STRETCH_HINI 0x0000 ++ ++// REG_GOP_39 ++#define GOP_STRETCH_VINI 0x0000 ++ ++// REG_GOP_7E ++#define GOP_GOPG0_MUX_MASK 0x0007 ++#define GOP_GOPG0_MUX_4G 0x0000 ++#define GOP_GOPG0_MUX_2G 0x0001 ++ ++#define GOP_Layer0_MUX_MASK 0x0007 ++#define GOP_Layer0_Sel_GOP0 0x0000 ++#define GOP_Layer0_Sel_GOP1 0x0001 ++#define GOP_Layer0_Sel_GOP2 0x0002 ++#define GOP_Layer0_Sel_GOP3 0x0003 ++#define GOP_Layer0_Sel_GOP_Null 0x0004 ++ ++#define GOP_Layer1_MUX_MASK (0x0007)<<3 ++#define GOP_Layer1_Sel_GOP0 (0x0000)<<3 ++#define GOP_Layer1_Sel_GOP1 (0x0001)<<3 ++#define GOP_Layer1_Sel_GOP2 (0x0002)<<3 ++#define GOP_Layer1_Sel_GOP3 (0x0003)<<3 ++#define GOP_Layer1_Sel_GOP_Null (0x0004)<<3 ++ ++#define GOP_Layer2_MUX_MASK (0x0007)<<6 ++#define GOP_Layer2_Sel_GOP0 (0x0000)<<6 ++#define GOP_Layer2_Sel_GOP1 (0x0001)<<6 ++#define GOP_Layer2_Sel_GOP2 (0x0002)<<6 ++#define GOP_Layer2_Sel_GOP3 (0x0003)<<6 ++#define GOP_Layer2_Sel_GOP_Null (0x0004)<<6 ++ ++#define GOP_Layer3_MUX_MASK (0x0007)<<9 ++#define GOP_Layer3_Sel_GOP0 (0x0000)<<9 ++#define GOP_Layer3_Sel_GOP1 (0x0001)<<9 ++#define GOP_Layer3_Sel_GOP2 (0x0002)<<9 ++#define GOP_Layer3_Sel_GOP3 (0x0003)<<9 ++#define GOP_Layer3_Sel_GOP_Null (0x0004)<<9 ++ ++ ++ ++ ++ ++// REG_GOP_7F ++#define GOP_BANK_G0_0 0x0000 ++#define GOP_BANK_G0_1 0x0001 ++#define GOP_BANK_G1_0 0x0003 ++#define GOP_BANK_G1_1 0x0004 ++#define GOP_BANK_G2_0 0x0006 ++#define GOP_BANK_G2_1 0x0007 ++#define GOP_BANK_G3_0 0x0009 ++#define GOP_BANK_G3_1 0x000A ++#define GOP_BANK_GPD 0x0006 ++ ++#define GOP_BANK_DOUBLE_WR 0x0100 ++#define GOP_BANK_FORCE_WR 0x0200 ++ ++#define GOP_BANK_DOUBLE_WR_G0 0x0400 ++#define GOP_BANK_DOUBLE_WR_G1 0x0403 ++#define GOP_BANK_DOUBLE_WR_G2 0x0406 ++#define GOP_BANK_DOUBLE_WR_G3 0x0409 ++#define GOP_BANK_DOUBLE_WR_MSK 0x0400 ++#define GOP_BANK_SEL_MSK 0x000F ++// GOP0 Bank 1 ++// REG_GOP_00 ++#define GOP0_GWin0_Enable 0x0001 ++ ++// REG_GOP_20 ++#define GOP0_GWin1_Enable 0x0001 ++ ++ ++ ++ ++// Chip Device ID ++#define DEVICE_COLUMBUS2 (0x2E) ++#define DEVICE_AMBER3 (0x47) ++#define DEVICE_CEDRIC (0x50) ++#define DEVICE_CHICAGO (0x70) ++ ++ +diff --git a/drivers/mstar/fb/cedric/gop/hal/platform.h b/drivers/mstar/fb/cedric/gop/hal/platform.h +new file mode 100644 +index 00000000..e04d58fd +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/hal/platform.h +@@ -0,0 +1,189 @@ ++#ifndef __PLATFORM_H__ ++#define __PLATFORM_H__ ++ ++//------------------------------------------------------------------------------ ++// Include Files ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Macros ++//------------------------------------------------------------------------------ ++#define MIU0_BUS_ADDR 0x40000000 ++#define MIU1_MASK 0x00000000 //use (ADDR & MIU1_MASK) to check if ADDR is in MIU1 after calling ms_mem_bus_to_MIU() ++ ++ ++#define IO_PHYS 0x1F000000 ++#define IO_OFFSET 0xDE000000 ++#define IO_SIZE 0x00400000 ++#define IO_VIRT (IO_PHYS + IO_OFFSET) ++#define io_p2v(pa) ((pa) + IO_OFFSET) ++#define io_v2p(va) ((va) - IO_OFFSET) ++//#define IO_ADDRESS(x) io_p2v((unsigned int)x) ++ ++ ++#define PERI_PHYS 0x16000000 ++#define PERI_OFFSET 0xE6000000 ++#define PERI_SIZE 0x2000 ++#define PERI_VIRT (PERI_PHYS + PERI_OFFSET) ++#define peri_p2v(pa) ((pa) + PERI_OFFSET) ++#define peri_v2p(va) ((va) - PERI_OFFSET) ++#define PERI_ADDRESS(x) peri_p2v(x) ++ ++#define PERI_W(a,v) (*(volatile unsigned int *)PERI_ADDRESS(a)=v) ++#define PERI_R(a) (*(volatile unsigned int *)PERI_ADDRESS(a)) ++ ++#define SCU_PHYS (PERI_PHYS) ++ ++#define L2_CACHE_PHYS 0x15000000 ++#define L2_CACHE_OFFSET 0xE7003000 ++#define L2_CACHE_SIZE 0x1000 ++#define L2_CACHE_VIRT (L2_CACHE_PHYS + L2_CACHE_OFFSET) ++#define L2_CACHE_p2v(pa) ((pa) + L2_CACHE_OFFSET) ++#define L2_CACHE_v2p(va) ((va) - L2_CACHE_OFFSET) ++#define L2_CACHE_ADDRESS(x) L2_CACHE_p2v(x) ++ ++#define L2_CACHE_write(v,a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a) = (v)) ++#define L2_CACHE_read(a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a)) ++ ++ ++#define IMI_PHYS 0xE0000000 ++#define IMI_OFFSET 0x1C005000 ++#define IMI_SIZE 0x50000 ++#define IMI_VIRT (IMI_PHYS + IMI_OFFSET) ++#define imi_p2v(pa) ((pa) + IMI_OFFSET) ++#define imi_v2p(va) ((va) - IMI_OFFSET) ++#define IMI_ADDRESS(x) imi_p2v((unsigned int)x) ++ ++ ++ ++ ++// Register macros ++#define GET_REG_ADDR(x, y) ((x) + ((y) << 2)) ++ ++ ++/* read register by byte */ ++#define ms_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) ++ ++/* read register by word */ ++#define ms_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++ ++/* read register by long */ ++#define ms_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) ++ ++/* write register by byte */ ++#define ms_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) ++ ++/* write register by word */ ++#define ms_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++ ++/* write register by long */ ++#define ms_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Macros: INREGx/OUTREGx/SETREGx/CLRREGx ++// ++// This macros encapsulates basic I/O operations. ++// Memory address space operation is used on all platforms. ++// ++#define INREG8(x) ms_readb(x) ++#define OUTREG8(x, y) ms_writeb((u8)(y), x) ++#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y)) ++#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y)) ++#define INREGMSK8(x, y) (INREG8(x) & (y)) ++#define OUTREGMSK8(x, y, z) OUTREG8(x, ((INREG8(x)&~(z))|((y)&(z)))) ++ ++#define INREG16(x) ms_readw(x) ++#define OUTREG16(x, y) ms_writew((u16)(y), x) ++#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) ++#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) ++#define INREGMSK16(x, y) (INREG16(x) & (y)) ++#define OUTREGMSK16(x, y, z) OUTREG16(x, ((INREG16(x)&~(z))|((y)&(z)))) ++ ++#define INREG32(x) ms_readl(x) ++#define OUTREG32(x, y) ms_writel((u32)(y), x) ++#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y)) ++#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y)) ++#define INREGMSK32(x, y) (INREG32(x) & (y)) ++#define OUTREGMSK32(x, y, z) OUTREG32(x, ((INREG32(x)&~(z))|((y)&(z)))) ++ ++ ++#define PM_READ32(x) ((((unsigned int)INREG16(x+4)<<16)&0xFFFF0000) | (INREG16(x) & 0x0000FFFF)) ++#define PM_WRITE32(x,y) do{OUTREG16(x,(y&0x0000FFFF));OUTREG16((x+4),((y>>16)&0x0000FFFF));}while(0) ++ ++#define XTAL_26000K 26000000 ++#define XTAL_24000K 24000000 ++#define XTAL_16369K 16369000 ++#define XTAL_16367K 16367000 ++ ++#define CPU_ID_CORE0 0x0 ++#define CPU_ID_CORE1 0x1 ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Define: MSBASE_REG_RIU_PA ++// ++// Locates the RIU register base. ++// ++#define MS_BASE_REG_RIU_PA IO_PHYS ++ ++ ++ ++extern unsigned long long ms_mem_bus_to_phys(unsigned long long x); ++extern unsigned long long ms_mem_phys_to_bus(unsigned long long x); ++extern unsigned long long ms_mem_bus_to_MIU(unsigned long long x); ++extern unsigned long long ms_mem_MIU_to_bus(unsigned long long x); ++ ++typedef enum ++{ ++ DEVINFO_BOOT_TYPE_SPI=0x01, ++ DEVINFO_BOOT_TYPE_EMMC=0x02, ++ DEVINFO_BOOT_TYPE_8051=0x03, ++}DEVINFO_BOOT_TYPE; ++ ++typedef enum ++{ ++ DEVINFO_PANEL_070_DEFAULT = 0x0, ++ DEVINFO_PANEL_HSD_070I_DW1 = 0x01, ++ DEVINFO_PANEL_HSD_070P_FW3 = 0x02, ++ DEVINFO_PANEL_AT_102_03TT91 = 0x03, ++ DEVINFO_PANEL_HSD_062I_DW1 = 0x04, ++ DEVINFO_PANEL_HSD_070I_DW2 = 0x05, ++ DEVINFO_PANEL_HSD_LVDS_800480= 0x06, ++ DEVINFO_PANEL_N070ICG_LD1 =0x08, ++ DEVINFO_PANEL_HSD_062I_DW2 = 0x09, ++ DEVINFO_PANEL_HSD_070I_MODE2 = 0x0a, ++ E_PANEL_UNKNOWN = 0xFF ++}DEVINFO_PANEL_TYPE; ++ ++ ++typedef enum ++{ ++ DEVINFO_BD_MST154A_D01A_S = 0x0801, ++ DEVINFO_BD_MST786_SZDEMO = 0x0802, ++ DEVINFO_BD_MST786_CUSTOM10 = 0x0810, ++ DEVINFO_BD_MST786_CUSTOM20 = 0x0820, ++ DEVINFO_BD_MST786_CUSTOM30 = 0x0830, ++ E_BD_UNKNOWN = 0xFFFF ++}DEVINFO_BOARD_TYPE; ++ ++typedef enum ++{ ++ DEVINFO_RTK_FLAG_0 = 0x0, ++ DEVINFO_RTK_FLAG_1 = 0x01, ++ E_RTK_UNKNOWN = 0xFFFF ++}DEVINFO_RTK_FLAG; ++ ++typedef struct ++{ ++ char name[16]; ++ unsigned long start; //MIU Address ++ unsigned long length; ++ unsigned long flag0; ++ unsigned long flag1; //Kernel Virtual Address ++} MS_MEM_INFO; ++ ++ ++#endif +diff --git a/drivers/mstar/fb/cedric/gop/mdrv_gop.c b/drivers/mstar/fb/cedric/gop/mdrv_gop.c +new file mode 100644 +index 00000000..ac604e67 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/mdrv_gop.c +@@ -0,0 +1,720 @@ ++ ++#include "mdrv_gop.h" ++ ++#include ++static volatile PREG_MBX_st sg_pMbxRegs = NULL; ++extern DEVINFO_RTK_FLAG ms_devinfo_rtk_flag(void); ++ ++U32 OALReadDeviceId(U32 devId) ++{ ++ U16 tmp = 0; ++ // need to refine for another SOC ++ tmp = 0x50; //C3 ++ return tmp; ++} ++ ++ ++ ++ ++U16 GOP_MIU_BUS(U16 MIU_BUS) ++{ ++ // A3: MIU Bus = 0x5; ++ // C2: MIU Bus = 0x3; ++ // C3: MIU Bus = 0x4; ++ // C4: MIU Bus = 0x3; ++ // Need to check with HW team ++ ++ U32 devId=0; ++ ++ devId=OALReadDeviceId(devId); ++ ++ if(DEVICE_AMBER3==devId) ++ { ++ GOPDBG("***** devId is AMBER3 *****\r\n"); ++ MIU_BUS = 5; ++ } ++ else if(DEVICE_CEDRIC==devId) ++ { ++ GOPDBG("***** devId is CEDRIC *****\r\n"); ++ MIU_BUS = 0x4; ++ } ++ else if(DEVICE_CHICAGO==devId) ++ { ++ GOPDBG("***** devId is DEVICE_CHICAGO *****\r\n"); ++ MIU_BUS = 0x3; ++ } ++ else ++ { ++ GOPDBG("***** devId UNKNOWN *****\r\n"); ++ MIU_BUS = 0x4; ++ ++ } ++ ++ GOPDBG("GOP_MIU_BUS devId is %d BUS is %d \n",devId,MIU_BUS); ++ ++ ++ return MIU_BUS; ++} ++ ++ ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr ) ++{ ++ ++ U32 FB_add = FB_Start_Addr; ++ ++ U32 s32BuffAddr=0; ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = Screen == 0 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ ++ GOPDBG ("GOP_Pan_Display: in \r\n"); ++ ++ // 1 GOP fetch framebuffer information ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ GOPDBG ("GOP_Pan_Display: out \r\n"); ++} ++ ++void GOP_Change_Alpha(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ //U16 FB_WIDTH=Panel_Width; ++ //U16 FB_HEIGHT=Panel_Height; ++ ++ ++ //U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ //U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ //U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ //U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ //U16 u16DispImage_HStart=0; ++ //U16 u16DispImage_HSize=FB_WIDTH; ++ //U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ //U16 u16DispImage_VStart=000; ++ //U16 u16DispImage_VSize=FB_HEIGHT; ++ //U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ //U32 s32BuffAddr=0; ++ //U32 u32TempVal=0; ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ //U16 DISPLAY_Format=Pixel_Format; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = Screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ if (Screen == 0) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ } ++ else if (Screen == 1) ++ { ++ OUTREG16(mdrv_BASE_REG_CHIPTOP_PA+BK_REG(0x40), 0x1000); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV|GOP_ALPHA); // constant alpha 0x3F, RGB565, enable ++ if(bInterlaceOut) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_interlace|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ else ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_SC1_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY_FOR_SC1_OP);//Hsync input pipe delay ++ } ++ ++ ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Setmode( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ ++ ++ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart=0; ++ U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart=000; ++ U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 MIU_BUS=0x04; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++ sg_pMbxRegs = (PREG_MBX_st)IO_ADDRESS(REG_MBX_BASE); ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ if (Screen == 0) ++ { ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ } ++ else if (Screen == 1) ++ { ++ GOP_block_0=GOP_BANK_G1_0; ++ GOP_block_1=GOP_BANK_G1_1; ++ } ++ ++ GOPDBG ("GOP_Setmode: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ ++ ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = GOP_block_0 == GOP_BANK_G0_0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ // GOP Global seting ; destination, Hsync ++ if (Screen == 0) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ } ++ else if (Screen == 1) ++ { ++ OUTREG16(mdrv_BASE_REG_CHIPTOP_PA+BK_REG(0x40), 0x1000); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV|GOP_ALPHA); // constant alpha 0x3F, RGB565, enable ++ if(bInterlaceOut) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_interlace|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ else ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_SC1_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY_FOR_SC1_OP);//Hsync input pipe delay ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); // Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); // Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++ ++ GOP_Reg_Base = GOP_block_1 == GOP_BANK_G0_1 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ ++ if (Screen == 0) ++ { ++ ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ //normal ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP0); ++ } ++ else ++ { ++ OUTREG16(mdrv_REG_GOP01_WIN, INREG16(mdrv_REG_GOP01_WIN) & mdrv_GWin0_Disable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP3); ++ } ++ ++ } ++ else if (Screen == 1) ++ { ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK|GOP_Layer3_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++ else ++ { ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ // OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++ ++void GOP_Set_OutFormat(int screen, int byuvoutput) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ GOPDBG("GOP_Set_OutFormat: screen:%d, byuvoutput:%d\n", screen, byuvoutput); ++ ++ if(byuvoutput) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_YUVOUT, GOP_YUVOUT); ++ ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP_YUVOUT); ++ } ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++} ++ ++ ++ ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetConstatnAlpha: screen:%d, bEn:%d, alpha:%x\n", screen, bEn, alpha); ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ // alpha inv ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : 0x8000), 0x8000); ++ ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++ ++ // constant or pixel alpha ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : 0x4000), 0x4000); ++ ++ // alhap value ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_0A, (bEn ? alpha : 0x0000), 0x00FF); ++ ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ ++} ++ ++ ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetColorKey: screen:%d, bEn:%d, (%x %x %x)\n", screen, bEn, u8R, u8G, u8B); ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ if(bEn) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0800, 0x0800); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_24, (u8B|(u8G<<8)), 0xFFFF); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_25, u8R, 0x00FF); ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0000, 0x0800); ++ } ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++void GOP_Set_PipeDelay(int screen, int delay) ++{ ++ U16 pipe_delay = 0x00; ++ ++ U32 GOP_Reg_Base; ++ ++ U16 GOP_Reg_DB; ++ ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ if (screen == 0) ++ { ++ pipe_delay = 0x50 + delay; ++ } ++ else if (screen == 1) ++ { ++ pipe_delay = 0x2E + delay; ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F, pipe_delay); ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++} ++ ++ ++void GOP_Setmode_and_win( ++ int bResume, int Screen, ++ int H_Start, int V_Start, ++ int H_End, int V_End, ++ int Panel_Width, int Panel_Height, ++ U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, ++ int bInterlaceOut) ++{ ++ ++ ++ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart= H_Start; ++ //U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd= H_End; //u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart= bInterlaceOut ? V_Start/2 : V_Start; ++ //U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd= bInterlaceOut ? V_End/2 : V_End; //u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++ sg_pMbxRegs = (PREG_MBX_st)IO_ADDRESS(REG_MBX_BASE); ++ ++ GOPDBG("screen:%d, pixel_format:%d, binter:%d\n", Screen, Pixel_Format, bInterlaceOut); ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ if (Screen == 0) ++ { ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ } ++ else if (Screen == 1) ++ { ++ GOP_block_0=GOP_BANK_G1_0; ++ GOP_block_1=GOP_BANK_G1_1; ++ } ++ ++ GOPDBG ("GOP_Setmode: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ ++ GOP_Reg_Base = GOP_block_0 == GOP_BANK_G0_0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++ ++ if (Screen == 0) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ } ++ else if (Screen == 1) ++ { ++ OUTREG16(mdrv_BASE_REG_CHIPTOP_PA+BK_REG(0x40), 0x1000); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV|GOP_ALPHA); // constant alpha 0x3F, RGB565, enable ++ if(bInterlaceOut) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_interlace|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ else ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_SC1_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY_FOR_SC1_OP);//Hsync input pipe delay ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST);// Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); // Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++ ++ GOP_Reg_Base = GOP_block_1 == GOP_BANK_G0_1 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ ++ if (Screen == 0) ++ { ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ //normal ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP0); ++ } ++ else ++ { ++ OUTREG16(mdrv_REG_GOP01_WIN, INREG16(mdrv_REG_GOP01_WIN) & mdrv_GWin0_Disable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP3); ++ } ++ ++ } ++ else if (Screen == 1) ++ { ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK|GOP_Layer3_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++ else ++ { ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ // OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ ++} ++//MODULE_LICENSE("GPL") +diff --git a/drivers/mstar/fb/cedric/gop/mdrv_gop.h b/drivers/mstar/fb/cedric/gop/mdrv_gop.h +new file mode 100644 +index 00000000..4cc11db4 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/mdrv_gop.h +@@ -0,0 +1,265 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_gop.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++ ++#include "hal/gop_c2_reg.h" ++ ++ ++#define CHIPTOP_REG_BASE_PA (0x101E00) ++#define SC_REG_BASE_PA (0x130000) ++#define LPLL_REG_BASE_PA (0x103100) ++#define CLKG0_REG_BASE_PA (0x100B00) ++#define MOD_REG_BASE_PA (0x103200) ++#define GPIO0_REG_BASE_PA (0x102B00) ++#define GPIO1_REG_BASE_PA (0x101A00) ++ ++#define GOP_DEBUG 0 ++#if (GOP_DEBUG==1) ++#define GOPDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOPDBG(fmt, arg...) ++#endif ++ ++ ++//#define GOPIO_DEBUG_ENABLE ++ ++#define GOP_DBG_LV_IOCTL 0 ++#define GOP_DBG_LV_0 1 ++ ++ ++#ifdef GOPIO_DEBUG_ENABLE ++#define GOPIO_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define GOP_DBG(dbglv, _fmt, _args...) \ ++ do \ ++ if(dbglv) \ ++ { \ ++ printk(KERN_WARNING _fmt, ## _args); \ ++ }while(0) ++ ++#else ++#define GOPIO_ASSERT(arg) ++#define GOP_DBG(dbglv, _fmt, _args...) ++ ++#endif ++ ++#define BK_REG(reg) ((reg) * 4) ++ ++/* ---------------------------------------------------------------------------- ++ * GOP_OFFSET ++ * ---------------------------------------------------------------------------- ++ */ ++#define REG_GOP_00 BK_REG(0x00) ++#define REG_GOP_01 BK_REG(0x01) ++#define REG_GOP_02 BK_REG(0x02) ++#define REG_GOP_03 BK_REG(0x03) ++#define REG_GOP_04 BK_REG(0x04) ++#define REG_GOP_05 BK_REG(0x05) ++#define REG_GOP_06 BK_REG(0x06) ++#define REG_GOP_07 BK_REG(0x07) ++#define REG_GOP_08 BK_REG(0x08) ++#define REG_GOP_09 BK_REG(0x09) ++#define REG_GOP_0A BK_REG(0x0A) ++#define REG_GOP_0B BK_REG(0x0B) ++#define REG_GOP_0C BK_REG(0x0C) ++#define REG_GOP_0D BK_REG(0x0D) ++#define REG_GOP_0E BK_REG(0x0E) ++#define REG_GOP_0F BK_REG(0x0F) ++ ++ ++#define REG_GOP_10 BK_REG(0x10) ++#define REG_GOP_11 BK_REG(0x11) ++#define REG_GOP_12 BK_REG(0x12) ++#define REG_GOP_13 BK_REG(0x13) ++#define REG_GOP_14 BK_REG(0x14) ++#define REG_GOP_15 BK_REG(0x15) ++#define REG_GOP_16 BK_REG(0x16) ++#define REG_GOP_17 BK_REG(0x17) ++#define REG_GOP_18 BK_REG(0x18) ++#define REG_GOP_19 BK_REG(0x19) ++#define REG_GOP_1A BK_REG(0x1A) ++#define REG_GOP_1B BK_REG(0x1B) ++#define REG_GOP_1C BK_REG(0x1C) ++#define REG_GOP_1D BK_REG(0x1D) ++#define REG_GOP_1E BK_REG(0x1E) ++#define REG_GOP_1F BK_REG(0x1F) ++ ++#define REG_GOP_20 BK_REG(0x20) ++#define REG_GOP_21 BK_REG(0x21) ++#define REG_GOP_22 BK_REG(0x22) ++#define REG_GOP_23 BK_REG(0x23) ++#define REG_GOP_24 BK_REG(0x24) ++#define REG_GOP_25 BK_REG(0x25) ++#define REG_GOP_26 BK_REG(0x26) ++#define REG_GOP_27 BK_REG(0x27) ++#define REG_GOP_28 BK_REG(0x28) ++#define REG_GOP_29 BK_REG(0x29) ++#define REG_GOP_2A BK_REG(0x2A) ++#define REG_GOP_2B BK_REG(0x2B) ++#define REG_GOP_2C BK_REG(0x2C) ++#define REG_GOP_2D BK_REG(0x2D) ++#define REG_GOP_2E BK_REG(0x2E) ++#define REG_GOP_2F BK_REG(0x2F) ++ ++ ++#define REG_GOP_30 BK_REG(0x30) ++#define REG_GOP_31 BK_REG(0x31) ++#define REG_GOP_32 BK_REG(0x32) ++#define REG_GOP_33 BK_REG(0x33) ++#define REG_GOP_34 BK_REG(0x34) ++#define REG_GOP_35 BK_REG(0x35) ++#define REG_GOP_36 BK_REG(0x36) ++#define REG_GOP_37 BK_REG(0x37) ++#define REG_GOP_38 BK_REG(0x38) ++#define REG_GOP_39 BK_REG(0x39) ++#define REG_GOP_3A BK_REG(0x3A) ++#define REG_GOP_3B BK_REG(0x3B) ++#define REG_GOP_3C BK_REG(0x3C) ++#define REG_GOP_3D BK_REG(0x3D) ++#define REG_GOP_3E BK_REG(0x3E) ++#define REG_GOP_3F BK_REG(0x3F) ++ ++ ++#define REG_GOP_40 BK_REG(0x40) ++#define REG_GOP_41 BK_REG(0x41) ++#define REG_GOP_42 BK_REG(0x42) ++#define REG_GOP_43 BK_REG(0x43) ++#define REG_GOP_44 BK_REG(0x44) ++#define REG_GOP_45 BK_REG(0x45) ++#define REG_GOP_46 BK_REG(0x46) ++#define REG_GOP_47 BK_REG(0x47) ++#define REG_GOP_48 BK_REG(0x48) ++#define REG_GOP_49 BK_REG(0x49) ++#define REG_GOP_4A BK_REG(0x4A) ++#define REG_GOP_4B BK_REG(0x4B) ++#define REG_GOP_4C BK_REG(0x4C) ++#define REG_GOP_4D BK_REG(0x4D) ++#define REG_GOP_4E BK_REG(0x4E) ++#define REG_GOP_4F BK_REG(0x4F) ++ ++ ++#define REG_GOP_50 BK_REG(0x50) ++#define REG_GOP_51 BK_REG(0x51) ++#define REG_GOP_52 BK_REG(0x52) ++#define REG_GOP_53 BK_REG(0x53) ++#define REG_GOP_54 BK_REG(0x54) ++#define REG_GOP_55 BK_REG(0x55) ++#define REG_GOP_56 BK_REG(0x56) ++#define REG_GOP_57 BK_REG(0x57) ++#define REG_GOP_58 BK_REG(0x58) ++#define REG_GOP_59 BK_REG(0x59) ++#define REG_GOP_5A BK_REG(0x5A) ++#define REG_GOP_5B BK_REG(0x5B) ++#define REG_GOP_5C BK_REG(0x5C) ++#define REG_GOP_5D BK_REG(0x5D) ++#define REG_GOP_5E BK_REG(0x5E) ++#define REG_GOP_5F BK_REG(0x5F) ++ ++ ++#define REG_GOP_60 BK_REG(0x60) ++#define REG_GOP_61 BK_REG(0x61) ++#define REG_GOP_62 BK_REG(0x62) ++#define REG_GOP_63 BK_REG(0x63) ++#define REG_GOP_64 BK_REG(0x64) ++#define REG_GOP_65 BK_REG(0x65) ++#define REG_GOP_66 BK_REG(0x66) ++#define REG_GOP_67 BK_REG(0x67) ++#define REG_GOP_68 BK_REG(0x68) ++#define REG_GOP_69 BK_REG(0x69) ++#define REG_GOP_6A BK_REG(0x6A) ++#define REG_GOP_6B BK_REG(0x6B) ++#define REG_GOP_6C BK_REG(0x6C) ++#define REG_GOP_6D BK_REG(0x6D) ++#define REG_GOP_6E BK_REG(0x6E) ++#define REG_GOP_6F BK_REG(0x6F) ++ ++ ++#define REG_GOP_70 BK_REG(0x70) ++#define REG_GOP_71 BK_REG(0x71) ++#define REG_GOP_72 BK_REG(0x72) ++#define REG_GOP_73 BK_REG(0x73) ++#define REG_GOP_74 BK_REG(0x74) ++#define REG_GOP_75 BK_REG(0x75) ++#define REG_GOP_76 BK_REG(0x76) ++#define REG_GOP_77 BK_REG(0x77) ++#define REG_GOP_78 BK_REG(0x78) ++#define REG_GOP_79 BK_REG(0x79) ++#define REG_GOP_7A BK_REG(0x7A) ++#define REG_GOP_7B BK_REG(0x7B) ++#define REG_GOP_7C BK_REG(0x7C) ++#define REG_GOP_7D BK_REG(0x7D) ++#define REG_GOP_7E BK_REG(0x7E) ++#define REG_GOP_7F BK_REG(0x7F) ++ ++void GOP_Setmode(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++void GOP_Change_Alpha(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr); ++void GOP_Set_OutFormat(int screen, int byuvoutput); ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha); ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B); ++void GOP_Set_PipeDelay(int screen, int delay); ++void GOP_Setmode_and_win(int bResume, int Screen, int H_Start, int V_Start, int H_End, int V_End, int Panel_Width, int Panel_Height, U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++ ++ ++ ++ +diff --git a/drivers/mstar/fb/cedric/gop/mdrv_gop_io.c b/drivers/mstar/fb/cedric/gop/mdrv_gop_io.c +new file mode 100644 +index 00000000..26eef6d5 +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/mdrv_gop_io.c +@@ -0,0 +1,415 @@ ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_gop.h" ++#include "mdrv_gop_io.h" ++ ++#define MDRV_GOP_DEVICE_COUNT 1 ++#define MDRV_GOP_NAME "mstar_gop" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_GOP "mstar_gop" ++#define MDRV_MAJOR_GOP 0xea ++#define MDRV_MINOR_GOP 0x01 ++ ++ ++int mstar_gop_drv_open(struct inode *inode, struct file *filp); ++int mstar_gop_drv_release(struct inode *inode, struct file *filp); ++long mstar_gop_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mstar_gop_drv_probe(struct platform_device *pdev); ++static int mstar_gop_drv_remove(struct platform_device *pdev); ++static int mstar_gop_drv_suspend(struct platform_device *dev, pm_message_t state); ++static int mstar_gop_drv_resume(struct platform_device *dev); ++static void mstar_gop_drv_platfrom_release(struct device *device); ++#if defined (CONFIG_ARCH_CEDRIC) ++extern int mstar_sca_drv_get_h_backporch(int sc_num); ++#endif ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++}GOP_DEV; ++ ++static GOP_DEV _devGOP = ++{ ++ .s32Major = MDRV_MAJOR_GOP, ++ .s32Minor = MDRV_MINOR_GOP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_GOP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mstar_gop_drv_open, ++ .release = mstar_gop_drv_release, ++ .unlocked_ioctl = mstar_gop_drv_ioctl, ++ } ++}; ++ ++static struct class * gop_class; ++static char * gop_classname = "mstar_gop_class"; ++ ++ ++static struct platform_driver Mstar_gop_driver = { ++ .probe = mstar_gop_drv_probe, ++ .remove = mstar_gop_drv_remove, ++ .suspend = mstar_gop_drv_suspend, ++ .resume = mstar_gop_drv_resume, ++ ++ .driver = { ++ .name = "mstar_gop", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static u64 sg_mstar_device_gop_dmamask = 0xffffffffUL; ++ ++static struct platform_device sg_mdrv_gop_device = ++{ ++ .name = "mstar_gop", ++ .id = 0, ++ .dev = ++ { ++ .release = mstar_gop_drv_platfrom_release, ++ .dma_mask = &sg_mstar_device_gop_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_GOPIO_IOC_Set_BaseAddr(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_BASE_ADDR_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (GOP_SET_BASE_ADDR_CONFIG __user *)arg, sizeof(GOP_SET_BASE_ADDR_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetBase: GOP_%d, Base=%x, \n", stCfg.enGopNum, (int)stCfg.u32Base); ++ ++ GOP_Pan_Display(stCfg.enGopNum, stCfg.u32Base); ++ ++ ++ return 0; ++} ++ ++int _MDrv_GOPIO_IOC_SetMode(struct file *filp, unsigned long arg) ++{ ++ GOP_SETMODE_CONFIG stCfg; ++ int Pixel_Format, Bytes_Per_Pixel; ++ if(copy_from_user(&stCfg, (GOP_SETMODE_CONFIG __user *)arg, sizeof(GOP_SETMODE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetMode: GOP_%d, (%d, %d) FM=%d, Base=%x, interlace=%d, yuv=%d,\n", ++ stCfg.enGopNum, stCfg.u16width, stCfg.u16height, stCfg.enSrcFormat, (int)stCfg.u32BaseAddr, stCfg.bInterlace, stCfg.bYUVOutput); ++ ++ switch(stCfg.enSrcFormat) ++ { ++ case E_GOP_SRC_RGB565: ++ Pixel_Format = 0x0010; ++ Bytes_Per_Pixel = 2; ++ break; ++ ++ case E_GOP_SRC_ARGB8888: ++ Pixel_Format = 0x0050; ++ Bytes_Per_Pixel = 4; ++ break; ++ ++ case E_GOP_SRC_ABGR8888: ++ Pixel_Format = 0x0070; ++ Bytes_Per_Pixel = 4; ++ break; ++ ++ } ++ ++ ++ GOP_Setmode(FALSE, stCfg.enGopNum, stCfg.u16width, stCfg.u16height, stCfg.u32BaseAddr, Pixel_Format, Bytes_Per_Pixel, stCfg.bInterlace); ++ ++ GOP_Set_OutFormat(stCfg.enGopNum, stCfg.bYUVOutput); ++#if defined (CONFIG_ARCH_CEDRIC) ++ if(stCfg.enGopNum == E_GOP_1) ++ { ++ GOP_Set_PipeDelay(1, mstar_sca_drv_get_h_backporch(1) ); ++ } ++#endif ++ return 0; ++} ++ ++ ++int _MDrv_GOPIO_IOC_Set_Constant_Alpha(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_CONSTANT_ALPHA_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (GOP_SET_CONSTANT_ALPHA_CONFIG __user *)arg, sizeof(GOP_SET_CONSTANT_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Constant_Alpha(stCfg.enGopNum, stCfg.bEn, stCfg.u8Alpha); ++ ++ return 0; ++} ++ ++int _MDrv_GOPIO_IOC_Set_Color_Key(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_COLOR_KEY_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (GOP_SET_COLOR_KEY_CONFIG __user *)arg, sizeof(GOP_SET_COLOR_KEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Color_Key(stCfg.enGopNum, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ return 0; ++} ++ ++//============================================================================== ++long mstar_gop_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_devGOP.refCnt <= 0) ++ { ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOPIO_IOCTL refCnt =%d!!! \n", _devGOP.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(GOP_IOC_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= GOP_IOC_MAX_NR) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ switch(u32Cmd) ++ { ++ case GOP_IOC_SET_BASE_ADDR: ++ retval = _MDrv_GOPIO_IOC_Set_BaseAddr(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_MODE: ++ retval = _MDrv_GOPIO_IOC_SetMode(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_CONSTANT_ALPHA: ++ retval = _MDrv_GOPIO_IOC_Set_Constant_Alpha(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_COLOR_KEY: ++ retval = _MDrv_GOPIO_IOC_Set_Color_Key(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++static int mstar_gop_drv_probe(struct platform_device *pdev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_probe\n"); ++ ++ return 0; ++} ++ ++static int mstar_gop_drv_remove(struct platform_device *pdev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_remove\n"); ++ ++ return 0; ++} ++ ++ ++static int mstar_gop_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_suspend\n"); ++ ++ ++ return 0; ++} ++ ++ ++static int mstar_gop_drv_resume(struct platform_device *dev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_resume\n"); ++ ++ ++ return 0; ++} ++ ++static void mstar_gop_drv_platfrom_release(struct device *device) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_platfrom_release\n"); ++ ++} ++ ++ ++int mstar_gop_drv_open(struct inode *inode, struct file *filp) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOP DRIVER OPEN\n"); ++ ++ GOPIO_ASSERT(_devGOP.refCnt>=0); ++ _devGOP.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mstar_gop_drv_release(struct inode *inode, struct file *filp) ++{ ++ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOP DRIVER RELEASE\n"); ++ _devGOP.refCnt--; ++ GOPIO_ASSERT(_devGOP.refCnt>=0); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_GOPIO_ModuleInit(void) ++{ ++ int s32Ret; ++ dev_t dev; ++ int ret = 0; ++ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOPIO]_Init \n"); ++ ++ if(_devGOP.s32Major) ++ { ++ dev = MKDEV(_devGOP.s32Major, _devGOP.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_GOP_DEVICE_COUNT, MDRV_GOP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _devGOP.s32Minor, MDRV_GOP_DEVICE_COUNT, MDRV_GOP_NAME); ++ _devGOP.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] Unable to get major %d\n", _devGOP.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_devGOP.cdev, &_devGOP.fops); ++ if (0 != (s32Ret= cdev_add(&_devGOP.cdev, dev, MDRV_GOP_DEVICE_COUNT))) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_GOP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ gop_class = class_create(THIS_MODULE, gop_classname); ++ if(IS_ERR(gop_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(gop_class, NULL, dev,NULL, "mstar_gop"); ++ } ++ ++ /* initial the whole GOP Driver */ ++ ret = platform_driver_register(&Mstar_gop_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&sg_mdrv_gop_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&Mstar_gop_driver); ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] register failed\n"); ++ ++ } ++ else ++ { ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _MDrv_GOPIO_ModuleExit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ GOP_DBG(GOP_DBG_LV_0, "[GOPIO]_Exit \n"); ++ ++ cdev_del(&_devGOP.cdev); ++ device_destroy(gop_class, MKDEV(_devGOP.s32Major, _devGOP.s32Minor)); ++ class_destroy(gop_class); ++ unregister_chrdev_region(MKDEV(_devGOP.s32Major, _devGOP.s32Minor), MDRV_GOP_DEVICE_COUNT); ++ platform_driver_unregister(&Mstar_gop_driver); ++} ++ ++ ++module_init(_MDrv_GOPIO_ModuleInit); ++module_exit(_MDrv_GOPIO_ModuleExit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GOPioctrl driver"); ++MODULE_LICENSE("GOP"); ++ +diff --git a/drivers/mstar/fb/cedric/gop/mdrv_gop_io.h b/drivers/mstar/fb/cedric/gop/mdrv_gop_io.h +new file mode 100644 +index 00000000..a010fcec +--- /dev/null ++++ b/drivers/mstar/fb/cedric/gop/mdrv_gop_io.h +@@ -0,0 +1,123 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_GOP_IO_H ++#define _MDRV_GOP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_GOP_LIB_CODE {'G','O','P','\0'} ++#define MSIF_GOP_BUILDNUM {'_','0','1','\0'} ++#define MSIF_GOP_LIBVER (2) ++#define MSIF_GOP_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++#define GOP_IOC_SET_BASE_ADDR_NR (0) ++#define GOP_IOC_SET_MODE_NR (1) ++#define GOP_IOC_SET_CONSTANT_ALPHA_NR (2) ++#define GOP_IOC_SET_COLOR_KEY_NR (3) ++#define GOP_IOC_MAX_NR (4) ++ ++ ++// use 'm' as magic number ++#define GOP_IOC_MAGIC ('3') ++#define GOP_IOC_SET_BASE_ADDR _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_BASE_ADDR_NR, GOP_SET_BASE_ADDR_CONFIG) ++#define GOP_IOC_SET_MODE _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_MODE_NR, GOP_SETMODE_CONFIG) ++#define GOP_IOC_SET_CONSTANT_ALPHA _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_CONSTANT_ALPHA_NR, GOP_SET_CONSTANT_ALPHA_CONFIG) ++#define GOP_IOC_SET_COLOR_KEY _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_COLOR_KEY_NR, GOP_SET_COLOR_KEY_CONFIG) ++//============================================================================= ++// enum ++//============================================================================= ++typedef enum ++{ ++ E_GOP_0, ++ E_GOP_1, ++ E_GOP_2, ++ E_GOP_3, ++ E_GOP_MAX, ++}E_GOP_NUM_TYPE; ++ ++ ++typedef enum ++{ ++ E_GOP_SRC_RGB565, ++ E_GOP_SRC_ARGB8888, ++ E_GOP_SRC_ABGR8888, ++}E_GOP_SRC_FORMAT_TYPE; ++//============================================================================= ++// struct ++//============================================================================= ++#ifndef _MS_TYPES_H_ ++typedef unsigned char MS_U8; ++typedef unsigned short MS_U16; ++typedef unsigned long MS_U32; ++typedef unsigned long long MS_U64; ++typedef unsigned char MS_BOOL; ++typedef signed short MS_S16; ++#endif ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_U32 u32Base; ++}GOP_SET_BASE_ADDR_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ E_GOP_SRC_FORMAT_TYPE enSrcFormat; ++ MS_U16 u16width; ++ MS_U16 u16height; ++ MS_BOOL bInterlace; ++ MS_U32 u32BaseAddr; ++ MS_BOOL bYUVOutput; ++}GOP_SETMODE_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_BOOL bEn; ++ MS_U8 u8Alpha; ++}GOP_SET_CONSTANT_ALPHA_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_BOOL bEn; ++ MS_U8 u8R; ++ MS_U8 u8G; ++ MS_U8 u8B; ++}GOP_SET_COLOR_KEY_CONFIG; ++#endif //_MDRV_GFLIP_IO_H ++ ++ ++ +diff --git a/drivers/mstar/fb/cedric/mdrv_fb.c b/drivers/mstar/fb/cedric/mdrv_fb.c +new file mode 100644 +index 00000000..7daf341f +--- /dev/null ++++ b/drivers/mstar/fb/cedric/mdrv_fb.c +@@ -0,0 +1,1117 @@ ++ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_general_fb.c ++ * DESCRIPTION For mdrv LinuxBSP Display driver, use frame buffer ++ * architecture ++ * ++ * AUTHOR Chun Fan ++ * ++ * ++ * HISTORY 2008/05/06 initial version ++ * linux/drivers/video/mdrv_general_fb.c ++ * -- mdrv frame buffer device ++ *****************************************************************************/ ++ ++ ++#define mdrv_GEN_FB_C ++ ++ ++#include "mdrv_fb.h" ++#include "mdrv_fb_io.h" ++#include "mdrv_fb_st.h" ++#include "ge/columbus2/mhal_ge.h" ++ ++ ++//#include "../scaler/mdrv_sca_io.h" ++/* ++ * RAM we reserve for the frame buffer. This defines the maximum screen ++ * size ++ * ++ * The default can be overridden if the driver is compiled as a module ++ */ ++ ++/* must use u_long, or it will have following message ++ * drivers/video/mdrv_general_fb.c: In function '__check_sg_videomemorysize': ++ * drivers/video/mdrv_general_fb.c:54: warning: ++ * return from incompatible pointer type ++ */ ++ /* frame buffer size */ ++static u_long sg_videomemorysize; ++ ++/* physical address, used in probe(), ioctl(), remove(), CreateGWin() */ ++/* physical address of frame buffer 1 2 */ ++dma_addr_t sg_G3D_fb2_bus_addr1 = 0; ++ ++extern int mstar_sca_drv_get_pnl_width(void); ++extern int mstar_sca_drv_get_pnl_height(void); ++extern int mstar_sca_drv_get_pnl_refresh_rate(void); ++extern void mstar_sca_drv_init_pnl(BOOLEAN bSkipTime); ++ ++static struct platform_device *psg_mdrv_fbdev0; ++ ++FB_GOP_GWIN_CONFIG genGWinInfo={0}; ++ ++//static DECLARE_MUTEX(mstar_panel_alloc_sem); ++ ++module_param(sg_videomemorysize, ulong, 0); ++ ++static void __init mdrvfb2_updateinfo(void) ++{ ++ ++ static int main_videomemory_size=0; ++ FBDBG("mdrvfb2_updateinfo !\n"); ++ ++ sg_mdrvfb2_default_var.xres = 720;//fix size in Infinity//mstar_sca_drv_get_pnl_width(); ++ sg_mdrvfb2_default_var.yres = 480;//fix size in Infinity//mstar_sca_drv_get_pnl_height(); ++ //GWin init, same size as screen ++ genGWinInfo.u18HStart = 0; ++ genGWinInfo.u18HEnd = genGWinInfo.u18HStart+sg_mdrvfb2_default_var.xres; ++ genGWinInfo.u18VStart = 0; ++ genGWinInfo.u18VEnd = genGWinInfo.u18VStart+sg_mdrvfb2_default_var.yres; ++ main_videomemory_size = (sg_mdrvfb2_default_var.xres*sg_mdrvfb2_default_var.yres * ANDROID_BYTES_PER_PIXEL * (ANDROID_NUMBER_OF_BUFFERS+1)); ++ ++ sg_mdrvfb2_default_fbmode.refresh=mstar_sca_drv_get_pnl_refresh_rate(); ++ ++ sg_videomemorysize = main_videomemory_size; ++ ++ FBDBG ("mdrvfb2_updateinfo: LCD_PANEL_WIDTH = [%d] \r\n",sg_mdrvfb2_default_var.xres); ++ FBDBG ("mdrvfb2_updateinfo: LCD_PANEL_HEIGHT = [%d] \r\n",sg_mdrvfb2_default_var.yres); ++ FBDBG ("mdrvfb2_updateinfo: sg_videomemorysize = 0x%x \r\n",(unsigned int)sg_videomemorysize); ++ ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb2_mmap +++------------------------------------------------------------------------------ ++| DESCRIPTION : memory map function, Let user application can get virtual ++| address to access in user space. need pass in physical address ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| vma | x | x | we use Remap-pfn-range will mark the range VM_IO ++| | | | and VM_RESERVED, and save these information in ++| | | | vma +++------------------------------------------------------------------------------ ++*/ ++ ++static int mdrvfb2_mmap(struct fb_info *pinfo, struct vm_area_struct *vma) ++{ ++ size_t size; ++ size = 0; ++ ++ MstarFB_ENTER(); ++ ++ ++ if (NULL == pinfo) ++ { ++ FBDBG("ERROR: mdrvfb2_mmap, pinfo is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ if (NULL == vma) ++ { ++ FBDBG("ERROR: mdrvfb2_mmap, vma is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_pgoff += ((sg_G3D_fb2_bus_addr1 ) >> PAGE_SHIFT); ++ ++ FBDBG( ++ "mdrvfb2_mmap vma->vm_start=%x\n vma->vm_end=%x\n vma->vm_pgoff =%x\n", ++ (unsigned int) vma->vm_start, (unsigned int)vma->vm_end , ++ (unsigned int)vma->vm_pgoff); ++ ++ //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ ++ MstarFB_LEAVE(); ++ return 0; ++} ++ ++static const char* KEY_DMEM_FB_BUF="FB_BUFFER"; ++ ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++ ++// FB Ioctl Functions ++ ++int _MDrv_FBIO_IOC_Get_SUPINFO(unsigned long arg) ++{ ++ FB_GOP_SUPINF_CONFIG stCfg; ++ ++ // enable gwin is in GOP01 ++ ++ stCfg.bKeyAlpha = 1; ++ stCfg.bConstAlpha = 1; ++ stCfg.bPixelAlpha = 1; ++ stCfg.bColFmt[COLORFMT_ARGB8888] = 1; ++ stCfg.bColFmt[COLORFMT_RGB565] = 1; ++ stCfg.bColFmt[COLORFMT_YUV422] = 1; ++ stCfg.u32MaxWidth = 1920; ++ stCfg.u32MaxWidth = 1080; ++ ++ if(copy_to_user((FB_GOP_SUPINF_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_SUPINF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_GWIN(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_GWIN_CONFIG stCfg; ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ stCfg.u18HStart = genGWinInfo.u18HStart; ++ stCfg.u18HEnd = genGWinInfo.u18HEnd; ++ stCfg.u18VStart = genGWinInfo.u18VStart; ++ stCfg.u18VEnd = genGWinInfo.u18VEnd; ++ ++ if(copy_to_user((FB_GOP_GWIN_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_GWIN(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_GWIN_CONFIG stCfg; ++ unsigned short MIU_BUS = 0x04; ++ unsigned short u16FrameBuffer_Bytes_Per_Pixel = ANDROID_BYTES_PER_PIXEL; ++ unsigned long u32TempVal = 0; ++ unsigned long GOP_Reg_DB=0x0400; ++ ++ // gwin info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_GWIN_CONFIG __user *)arg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ genGWinInfo.u18HStart = stCfg.u18HStart; ++ genGWinInfo.u18HEnd = stCfg.u18HEnd; ++ genGWinInfo.u18VStart = stCfg.u18VStart; ++ genGWinInfo.u18VEnd = stCfg.u18VEnd; ++ ++ // GOP Display Setting, GWIN ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(genGWinInfo.u18HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(genGWinInfo.u18HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,genGWinInfo.u18VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,genGWinInfo.u18VEnd); // V end line ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_EnGOP(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ unsigned char enGOP; ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // get enable/disable gwin ++ enGOP=(unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0001); ++ ++ if(copy_to_user((unsigned char __user *)arg, &enGOP, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnGOP(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ unsigned char enGOP; ++ unsigned long GOP_Reg_DB=0x0400; ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ if(copy_from_user(&enGOP, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ // enable/disable gwin ++ if(enGOP) ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0001,0x0001); ++ else ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0000,0x0001); ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_Alpha(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_ALPHA_CONFIG stCfg; ++ // alpha info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // enable/disable ++ stCfg.bEn=TRUE; ++ ++ // constant or pixel alpha ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x4000)>>14) ++ stCfg.enAlphaType = PIXEL_ALPHA; ++ else ++ stCfg.enAlphaType = CONST_ALPHA; ++ ++ // alhap value ++ stCfg.u8Alpha = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_0A, 0x00FF); ++ ++ if(copy_to_user((FB_GOP_ALPHA_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Constant_Alpha(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Constant_Alpha(0, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_Color_Key(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ // colorkey setting is in GOP00 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // enable/disable ++ stCfg.bEn = (INREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0800)>>11); ++ ++ // colorkey value ++ stCfg.u8R = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_25,0x00FF); ++ stCfg.u8G = (unsigned char)(INREGMSK16(GOP_Reg_Base+REG_GOP_24,0xFF00)>>8); ++ stCfg.u8B = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_24,0x00FF); ++ ++ if(copy_to_user((FB_GOP_COLORKEY_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Color_Key(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Color_Key(0, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_imageblit(struct fb_info *info,unsigned long arg) ++{ ++ struct fb_image stCfg; ++ //struct fb_image image; ++ if(copy_from_user(&stCfg, (struct fb_image __user *)arg, sizeof(const struct fb_image))) ++ { ++ return -EFAULT; ++ } ++ ++ if (NULL == stCfg.data) ++ { ++ FBDBG("ERROR:in mdrvfb2_ioctl, fb_image.data is NULL pointer\r\n"); ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Imgblit test, dst (x,y)=(%d,%d), width=%d, height=%d, colordepth=%d \n" ,stCfg.dx,stCfg.dy,stCfg.width,stCfg.height,stCfg.depth); ++ ++ sys_imageblit(info,&stCfg); ++ ++ return 0; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb2_ioctl +++------------------------------------------------------------------------------ ++| DESCRIPTION : IO control code. we provide some customize ioctl code, GLES, ++| and test code. now, we provide the following IOCTL command ++| G3D_GETVFRAMEVIRTUAL1 ++| G3D_GETVFRAMEVIRTUAL2 ++| G3D_GETCOMMANDQVIRTUAL ++| G3D_GETREGISTERVIRTUAL ++| G3D_GETTEXTUREVIRTUAL ++| G3D_FREETEXTUREVIRTUAL ++| SET_DISPLAY_COLOR ++| G3D_IOC_MAXNR 20 ++| ++| + define color ++| COLOR_MASK ++| WHITE_COLOR ++| ++| RETURN : When the operation is success, it return 0. ++| some ioctl will return the physical address for GLES use ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| cmd | x | | pass in the ioctl command ++|--------------------+---+---+------------------------------------------------- ++| arg | x | x | pass in/out argument, from user space or to user ++| | | | space +++------------------------------------------------------------------------------ ++*/ ++/* I reserve the unsgined long here, ++ because it is the ioctl() function template */ ++static int ++mdrvfb2_ioctl(struct fb_info *pinfo, unsigned int cmd, unsigned long arg) ++{ ++ int err=0, ret=0; ++ unsigned int ret_Phy=0; ++ ++ if (NULL == pinfo) ++ { ++ FBDBG("ERROR:in mdrvfb2_ioctl, pinfo is NULL pointer\r\n"); ++ return -ENOTTY; ++ } ++ ++ /* don't even decode wrong cmds: better returning ENOTTY than EFAULT */ ++ if (_IOC_TYPE(cmd) != G3D_IOC_MAGIC_INFINITY) ++ return -ENOTTY; ++// if (_IOC_NR(cmd) > G3D_IOC_MAXNR) ++// return -ENOTTY; ++ ++ /* ++ * the type is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. Note that the type is user-oriented, while ++ * verify_area is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ err = !access_ok(VERIFY_WRITE, CAST_2_USER_VOID_P arg, _IOC_SIZE(cmd)); ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ err = !access_ok(VERIFY_READ, CAST_2_USER_VOID_P arg, _IOC_SIZE(cmd)); ++ ++ /* check if occurred error */ ++ if (err) ++ return -EFAULT; ++ ++ switch (cmd) ++ { ++ case IOCTL_FB_GETFBPHYADDRESS: ++ ret_Phy = sg_G3D_fb2_bus_addr1; ++ FBDBG( "[FB Driver] Phy Addr =%x\r\n",ret_Phy); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ ++ case IOCTL_FB_GETVIDEOMEMSIZE: ++ ret_Phy = sg_videomemorysize; ++ FBDBG( "[FB Driver] Kernel VideoMemSize =0x%x \n" ,(unsigned int)sg_videomemorysize); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ ++ case IOCTL_FB_GETFBSUPPORTINF: ++ FBDBG( "[FB Driver] Get Framebuffer Support Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_SUPINFO(arg); ++ break; ++ ++ case IOCTL_FB_GETGWININFO: ++ FBDBG( "[FB Driver] Get Framebuffer GWIN Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_GWIN(arg); ++ break; ++ ++ case IOCTL_FB_SETGWININFO: ++ FBDBG( "[FB Driver] Set Framebuffer GWIN Information.\n"); ++ ret=_MDrv_FBIO_IOC_Set_GWIN(arg); ++ break; ++ ++ case IOCTL_FB_GETENABLEGOP: ++ FBDBG( "[FB Driver] Get GOP Enable/Disable.\n"); ++ ret=_MDrv_FBIO_IOC_Get_EnGOP(arg); ++ break; ++ ++ case IOCTL_FB_SETENABLEGOP: ++ FBDBG( "[FB Driver] Set GOP Enable/Disable.\n"); ++ ret=_MDrv_FBIO_IOC_Set_EnGOP(arg); ++ break; ++ ++ case IOCTL_FB_GETALPHA: ++ FBDBG( "[FB Driver] Get Alpha Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_Alpha(arg); ++ break; ++ ++ case IOCTL_FB_SETALPHA: ++ FBDBG( "[FB Driver] Set Alpha Information.\n"); ++ ret=_MDrv_FBIO_IOC_Set_Constant_Alpha(arg); ++ break; ++ ++ case IOCTL_FB_GETCOLORKEY: ++ FBDBG( "[FB Driver] Get Colorkey Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_Color_Key(arg); ++ break; ++ ++ case IOCTL_FB_SETCOLORKEY: ++ FBDBG( "[FB Driver] Set Colorkey Information.\n"); ++ ret=_MDrv_FBIO_IOC_Set_Color_Key(arg); ++ break; ++ ++ case IOCTL_FB_IMAGEBLIT: ++ FBDBG( "[FB Driver] Use Imageblit.\n"); ++ ret=_MDrv_FBIO_IOC_imageblit(pinfo,arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ FBDBG("in default ioct\r\n"); ++ return -ENOTTY; ++ } ++ return ret; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb2_platform_release +++------------------------------------------------------------------------------ ++| DESCRIPTION : when module is unloaded, this function will be called ++| This is called when the reference count goes to zero. ++| ++| RETURN : no return value ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| device | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++ ++static void mdrvfb2_platform_release(struct device *device) ++{ ++ ++ MstarFB_ENTER(); ++ ++ if (NULL == device) ++ { ++ FBDBG("ERROR: in mdrvfb2_platform_release, \ ++ device is NULL pointer !\r\n"); ++ } ++ else ++ { ++ FBDBG("in mdrvfb2_platform_release, module unload!\n"); ++ } ++ ++ MstarFB_LEAVE(); ++} ++ ++#if 0 ++void mdrvgop_DispCreateGWin2(struct fb_info *WG) ++{ ++ ++ int xx=0; ++ xx++; ++ ++ FBDBG("fb%d: mdrv frame buffer device, of video memory\n", WG->node); ++} ++#endif ++static int mdrvfb2_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ FBDBG(" in mdrvfb2_suspend \r\n"); ++ return 0; ++} ++ ++static int mdrvfb2_resume(struct platform_device *pdev) ++{ ++ dma_addr_t fb2_PHY_ADD_SHOW=0; ++ FBDBG(" mdrvfb2_resume \r\n"); ++ ++ if(unlikely(useCalibrationFrameBuffer)) ++ { ++ fb2_PHY_ADD_SHOW = sg_G3D_fb2_bus_addr1 + ((sg_mdrvfb2_default_var.xres * sg_mdrvfb2_default_var.yres * ANDROID_BYTES_PER_PIXEL)*ANDROID_NUMBER_OF_BUFFERS); ++ GOP_Setmode(TRUE, 0,sg_mdrvfb2_default_var.xres,sg_mdrvfb2_default_var.yres,fb2_PHY_ADD_SHOW,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ } ++ else ++ { ++ GOP_Setmode(TRUE, 0,sg_mdrvfb2_default_var.xres,sg_mdrvfb2_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ } ++ ++ //printk("fb2 resume sleep ! \n"); ++ //msleep(5000); ++ return 0; ++} ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb2_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : Initialization. Initial HW, fill table, when load module, ++| this function will be called. ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++ ++static int mdrvfb2_probe(struct platform_device *dev) ++{ ++ struct fb_info *pinfo = NULL; ++ int retval = -ENOMEM; ++ ++ int fb_format=0; ++ ++ MstarFB_ENTER(); ++ ++ if (NULL == dev) ++ { ++ FBDBG("ERROR: in mdrvfb2_prob: dev is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ fb_format=ANDROID_FB_FORMAT; ++ ++ // static global variable, pass at probe(), used by dma alloc and dma free in ioctl(), ++ psg_mdrv_fbdev0 = dev; ++ ++ FBDBG("mdrvfb2: sg_videomemorysize is 0x%X to allocate screen memory\n",(unsigned int)sg_videomemorysize); ++ ++ /* For G3D frame buffer2 */ ++ if (!(sg_pG3D_fb2_vir_addr1 = alloc_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ &sg_G3D_fb2_bus_addr1))) ++ { ++ FBDBG("mdrvfb2: unable to allocate screen memory\n"); ++ return retval; ++ } ++ ++ //printk("---------1 \n"); ++ //msleep(6000); ++ // prevent initial garbage on screen ; to clean memory ++ memset(CAST_2_IOMEM_CHAR_P sg_pG3D_fb2_vir_addr1,OTHER_COLOR, sg_videomemorysize); ++ ++ FBDBG("mdrvfb2 vir=0x%x, phy=0x%x\n", (unsigned int)sg_pG3D_fb2_vir_addr1, sg_G3D_fb2_bus_addr1); ++ ++ sg_mdrvfb2_fix.smem_start = sg_G3D_fb2_bus_addr1; ++ sg_mdrvfb2_fix.smem_len = sg_videomemorysize; ++ ++ pinfo = framebuffer_alloc(sizeof(struct fb_info), &dev->dev); ++ if (!pinfo) ++ goto err; ++ ++ ++ pinfo->screen_base = CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ FBDBG( "sg_mdrvfb2_fix.smem_start=0x%x ",(unsigned int) sg_mdrvfb2_fix.smem_start); ++ ++ //printk("---------2 \n"); ++ //msleep(6000); ++ ++ pinfo->fbops = &sg_mdrvfb2_ops; ++ pinfo->var = sg_mdrvfb2_default_var; ++ pinfo->fix = sg_mdrvfb2_fix; ++ pinfo->pseudo_palette = pinfo->par; ++ pinfo->par = NULL; ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ ++ ++ /* allocate color map */ ++ /* 256 is following to the vfb.c */ ++ retval = fb_alloc_cmap(&pinfo->cmap, 256, 0); ++ if (retval < 0) ++ goto err1; ++ ++ ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ pinfo->fix.type = FB_TYPE_PACKED_PIXELS; ++ pinfo->fix.visual = FB_VISUAL_TRUECOLOR; ++ pinfo->fix.line_length = sg_mdrvfb2_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ pinfo->fix.accel = FB_ACCEL_NONE; ++ pinfo->fix.ypanstep = 1; ++ ++ pinfo->var.xres = sg_mdrvfb2_default_var.xres; ++ pinfo->var.yres = sg_mdrvfb2_default_var.yres; ++ pinfo->var.xres_virtual = sg_mdrvfb2_default_var.xres; ++ pinfo->var.yres_virtual = sg_mdrvfb2_default_var.yres * ANDROID_NUMBER_OF_BUFFERS; ++ pinfo->var.bits_per_pixel = BPX; ++ pinfo->var.activate = FB_ACTIVATE_NOW; ++ pinfo->var.height = sg_mdrvfb2_default_var.yres; ++ pinfo->var.width = sg_mdrvfb2_default_var.xres; ++ pinfo->fix.smem_len = sg_videomemorysize; ++ ++ //printk("---------3 \n"); ++ //msleep(6000); ++ ++ ++ if (RGB565==fb_format) ++ { ++ ++ pinfo->var.red.offset = 11; ++ pinfo->var.red.length = 5; ++ pinfo->var.green.offset = 5; ++ pinfo->var.green.length = 6; ++ pinfo->var.blue.offset = 0; ++ pinfo->var.blue.length = 5; ++ } ++ else if(ARGB8888==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 8; ++ pinfo->var.red.length = 8; ++ pinfo->var.green.length = 8; ++ pinfo->var.blue.length = 8; ++ ++ pinfo->var.transp.offset = 24; ++ pinfo->var.red.offset = 16; ++ pinfo->var.green.offset = 8; ++ pinfo->var.blue.offset = 0; ++ } ++ // same define as cedric ++ else if(RGBA8888==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 8; ++ pinfo->var.red.length = 8; ++ pinfo->var.green.length = 8; ++ pinfo->var.blue.length = 8; ++ ++ pinfo->var.transp.offset = 0; ++ pinfo->var.red.offset = 24; ++ pinfo->var.green.offset = 16; ++ pinfo->var.blue.offset = 8; ++ } ++ else ++ { ++ ++ printk(KERN_ERR"ERROR!! mdrvfb2_probe fb_format =%d Not Support!!",fb_format); ++ while(1); ++ ++ } ++ /* register mdrvfb to fbmem.c */ ++ retval = register_framebuffer(pinfo); ++ if (retval < 0) ++ goto err2; ++ ++ platform_set_drvdata(dev, pinfo); ++ ++ //patch some setting due to our panel setting may have problems ++ { ++ struct list_head *pos; ++ struct fb_modelist *modelist; ++ ++ list_for_each(pos, &pinfo->modelist) { ++ modelist = list_entry(pos, struct fb_modelist, list); ++ modelist->mode.refresh=sg_mdrvfb2_default_fbmode.refresh; ++ } ++ } ++ ++ //printk("---------4 \n"); ++ //msleep(6000); ++ ++ /* ======================================================== */ ++ /* HW INIT related code */ ++ /* ======================================================== */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_58 , 0x1); /* power switch enable */ ++ ++ //CLRREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_57, 0x0200); /* external device power on output enable */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_57, 0x0002); /* external device power on enable */ ++ ++ /* 0. CHIPTOP Register - BIT_9 : Enable RGB output, Bit_14 reg_OP2_en */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_09 , 0x4200); /* */ ++ ++ //ms_writew( 0x0040,MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_26); //add ++ ++ /* h'28 CLK_GE clock control */ ++ /* ++ //weichun temp disable ++ CLRREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_28, 0x1F); ++ SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_28 , 0x8); ++ */ ++ /*h'2A CLK_GOPG0 clock control */ ++ /* ++ ++ */ ++ /* 2. Set CLK_ODCLK's source is LPLL */ ++ //ms_writew( 0x1C00,MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_1B); ++ ++ ++ //CLRREG16(0xA0002604 , 0x0008); ++ ++ //ms_writew(0, MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_2C ); ++ ++ /* Create GWIN, make a window to show graph, setting HW(GOP) */ ++ //mdrvgop_DispCreateGWin(); ++ ++ // FB info ++ // FB Width ++ // FB Pitch ++ // FB Height ++ // FB Starting address ++ // FB Format ++ ++ // View info ++ ++ // mdrvgop_DispCreateGWin2(pinfo); ++ //mdrvgop_DispCreateGWin(sg_G3D_Fb_bus_addr1,sg_G3D_Fb_bus_addr2,sg_mdrvfb_default_var.xres,sg_mdrvfb_default_var.yres,ANDROID_BYTES_PER_PIXEL); ++// #if (UBOOT_SHOW_LOGO==0) ++ ++ ++ GOP_Setmode(FALSE, 0,sg_mdrvfb2_default_var.xres,sg_mdrvfb2_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ //set to sca2 for test Infinity in cedric ++ #define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120200/2)) ++ #define mdrv_BASE_REG_DIP GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x133400/2)) ++ #define mdrv_BASE_REG_CLKGEN GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x100B00/2)) ++ OUTREG16(mdrv_BASE_REG_GOP00_PA + (0x7E<<2),0x924); ++ OUTREG16(mdrv_BASE_REG_GOP00_PA + (0x7B<<2),0x04); ++ OUTREG16(mdrv_BASE_REG_GOP00_PA + (0x01<<2),((INREG16(mdrv_BASE_REG_GOP00_PA + (0x01<<2))&0xFFF0)|0x07)); ++ OUTREG16(mdrv_BASE_REG_DIP+ (0x10<<2),((INREG16(mdrv_BASE_REG_DIP + (0x10<<2)))&0xFFEE)|0x11); ++ OUTREG16(mdrv_BASE_REG_CLKGEN+ (0x40<<2),((INREG16(mdrv_BASE_REG_CLKGEN + (0x40<<2)))&0xFFF0)|0x04); ++ GOP_Set_OutFormat(0,1); ++ ++ ++ //#else ++ // GOP_Change_Alpha(FALSE, 0,sg_mdrvfb2_default_var.xres,sg_mdrvfb2_default_var.yres,sg_G3D_fb2_bus_addr2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++// #endif ++ ++ ++// FBDBG("fb%d: mdrv frame buffer device, using %ldK of video memory\n", pinfo->node, sg_videomemorysize >> 10); ++ ++ //printk("---------5 \n"); ++ //msleep(6000); ++ MstarFB_LEAVE(); ++ return 0; ++ ++err2: ++ fb_dealloc_cmap(&pinfo->cmap); ++err1: ++ framebuffer_release(pinfo); ++err: ++ ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ ++ return retval; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb2_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : we free memory, release frame buffer here ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvfb2_remove(struct platform_device *dev) ++{ ++ struct fb_info *pinfo; ++ pinfo = 0; ++ ++ ++ MstarFB_ENTER(); ++ ++ ++ if (NULL == dev) ++ { ++ FBDBG("ERROR: mdrvfb2_remove: dev is NULL pointer \n"); ++ return -ENOTTY; ++ } ++ ++ pinfo = platform_get_drvdata(dev); ++ if (pinfo) ++ { ++ unregister_framebuffer(pinfo); ++ ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ ++ framebuffer_release(pinfo); ++ } ++ ++ MstarFB_LEAVE(); ++ return 0; ++} ++ ++static int mdrvfb2_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ ++ //MstarFB_ENTER(); ++ dma_addr_t fb2_PHY_ADD_SHOW=0; ++ ++ if( unlikely(useCalibrationFrameBuffer)) ++ { ++ return 0; ++ } ++ else ++ { ++ ++ if (info->var.yoffset >= (info->var.height << 1)) ++ { ++ fb2_PHY_ADD_SHOW = info->fix.smem_start + ((info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL) << 1); ++ } ++ else if (info->var.yoffset >= info->var.height) ++ { ++ fb2_PHY_ADD_SHOW = info->fix.smem_start + (info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL); ++ } ++ else ++ { ++ fb2_PHY_ADD_SHOW = info->fix.smem_start; ++ } ++ ++ GOP_Pan_Display(0, fb2_PHY_ADD_SHOW); ++ } ++ ++ return 0; ++} ++ ++ ++/* check var to see if supported by this device. Probably doesn't ++ * need modifying. ++ */ ++static int mdrvfb2_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ ++ //MstarFB_ENTER(); ++ ++ if((var->rotate & 1) != (info->var.rotate & 1)) ++ { ++ if((var->xres != info->var.yres) || ++ (var->yres != info->var.xres) || ++ (var->xres_virtual != info->var.yres) || ++ (var->yres_virtual > ++ info->var.xres * ANDROID_NUMBER_OF_BUFFERS) || ++ (var->yres_virtual < info->var.xres )) ++ { ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ if((var->xres != info->var.xres) || ++ (var->yres != info->var.yres) || ++ (var->xres_virtual != info->var.xres) || ++ (var->yres_virtual > ++ info->var.yres * ANDROID_NUMBER_OF_BUFFERS) || ++ (var->yres_virtual < info->var.yres )) ++ { ++ return -EINVAL; ++ } ++ } ++ if((var->xoffset != info->var.xoffset) || ++ (var->bits_per_pixel != info->var.bits_per_pixel) || ++ (var->grayscale != info->var.grayscale)) ++ { ++ return -EINVAL; ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb_init +++------------------------------------------------------------------------------ ++| DESCRIPTION : register the driver to kernel, ++| to tell it what facility or function we provide ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| ++| Variable Name : no variable +++------------------------------------------------------------------------------ ++*/ ++ ++/* register the driver to kernel, ++ to tell it what facility or function we provide */ ++static int __init mdrvfb2_init(void) ++{ ++ int ret = 0; ++ ++ MstarFB_ENTER(); ++ ++ /* register the driver into kernel */ ++ ++ // how to get the Panel type and what kind of output display device ? ++ ++ ++ //MApi_PNL_Init(tPanelNANOVISON_45); ++ #if(UBOOT_SHOW_LOGO==1) ++ mstar_sca_drv_init_pnl(TRUE); ++ #else ++ mstar_sca_drv_init_pnl(FALSE); ++ #endif ++ mdrvfb2_updateinfo(); ++ ++ ret = platform_driver_register(&sg_mdrvfb2_driver); ++ ++ if (!ret) ++ { /* register driver sucess */ ++ /* register device */ ++ ret = platform_device_register(&sg_mdrvfb2_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&sg_mdrvfb2_driver); ++ printk(KERN_INFO"mdrvfb2_device register failed...\n"); ++ } ++ else ++ { ++ printk(KERN_INFO"mdrvfb2_device register success...\n"); ++ } ++ } ++ ++ ++ MstarFB_LEAVE(); ++ ++ return ret; ++} ++ ++ ++module_init(mdrvfb2_init); /* tell kernel where the init function */ ++ ++#ifdef MODULE ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb2_exit +++------------------------------------------------------------------------------ ++| DESCRIPTION : cleanup the driver from kernel ++| ++| RETURN : no return value ++| ++| Variable Name : no variable +++------------------------------------------------------------------------------ ++*/ ++ ++static void __exit mdrvfb2_exit(void) ++{ ++ ++ MstarFB_ENTER(); ++ ++ platform_device_unregister(&sg_mdrvfb2_device); ++ ++ platform_driver_unregister(&sg_mdrvfb2_driver); ++ ++ MstarFB_LEAVE(); ++ ++} ++ ++module_exit(mdrvfb2_exit); /* tel kernel where is the clean up function */ ++ ++MODULE_LICENSE("GPL"); ++/* use GPL license to avoid Kernel to complain this driver */ ++#endif /* MODULE */ ++ ++ ++ ++//MODULE_LICENSE("GPL") +diff --git a/drivers/mstar/fb/cedric/mdrv_fb.h b/drivers/mstar/fb/cedric/mdrv_fb.h +new file mode 100644 +index 00000000..6c3ac50b +--- /dev/null ++++ b/drivers/mstar/fb/cedric/mdrv_fb.h +@@ -0,0 +1,275 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_fb.h ++ * DESCRIPTION ++ * Including some MACRO needed in mdrvfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/mdrvfb.h -- mdrvfb frame buffer device ++ ******************************************************************************/ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++#include "gop/mdrv_gop.h" ++#include "gop/mdrv_gop.h" ++#include "gop/mdrv_gop_io.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" /* for dma_alloc_coherent */ ++ ++ ++#define FB_DEBUG 1 ++#define FB_FUNBUG 1 ++ ++// same define as cedric ++#define UBOOT_SHOW_LOGO 1 ++ ++ ++#if (FB_DEBUG==1) ++#define FBDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define FBDBG(fmt, arg...) ++#endif ++ ++#define MstarTrace printk ++ ++#if 0 ++#if (FB_FUNBUG==1) ++#define MstarTrace printk ++#else ++#define MstarTrace if(0) printk ++#endif ++#endif ++ ++#define MstarFB_ENTER(...) MstarTrace("============ FB ============\r\n%s START\n", __func__) ++#define MstarFB_LEAVE(...) MstarTrace("%s END\n============ FB ============\r\n", __func__) ++ ++ ++#ifdef mdrv_GEN_FB_C /* in frame buffer driver */ ++#define PRIVATE_FB_DATA ++#else /* in user space */ ++#define PRIVATE_FB_DATA const ++#endif /* mdrv_GEN_FB_C */ ++ ++ ++/* ========================================================================= */ ++/* define type cast macro */ ++#define CAST_2_USER_VOID_P (void __user *) ++#define CAST_2_USER_UINT_P (unsigned int __user *) ++#define CAST_2_USER_TEXTURE_INFO_P (TEXTURE_INFO __user *) ++#define CAST_2_IOMEM_CHAR_P (u8 __iomem *) ++#define CAST_2_ULONG (unsigned long) ++ ++ ++static int useCalibrationFrameBuffer = 0 ; ++ ++ ++/* ========================================================================= */ ++/* define color */ ++#define COLOR_MASK 0xffff ++#define WHITE_COLOR 0xffff ++#define OTHER_COLOR 0xFF00 ++ ++ ++#define ANDROID_NUMBER_OF_BUFFERS 3 ++ ++ ++// same define as cedric ++#define ANDROID_FB_FORMAT RGBA8888 ++ ++ ++#define defult_XRES 800 // PANEL_WIDTH ++#define defult_YRES 480 //PANEL_HEIGHT ++#if (ANDROID_FB_FORMAT == RGB565) ++#define BPX 16 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 2 ++#elif ((ANDROID_FB_FORMAT == ARGB8888) || (ANDROID_FB_FORMAT == RGBA8888)) ++#define BPX 32 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 4 ++//#elif (ANDROID_FB_FORMAT == ARGB8888) ++//#define BPX 32 /* bits per pixel */ ++//#define ANDROID_BYTES_PER_PIXEL 4 ++#else ++ #ERROR("Not Support") ++#endif ++ ++ ++/* ========================================================================= */ ++/* prototype of function */ ++ ++static s32 mdrvfb2_ioctl(struct fb_info *info, u32 cmd, unsigned long arg); ++static s32 mdrvfb2_mmap(struct fb_info *info, struct vm_area_struct *vma); ++static s32 mdrvfb2_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); ++static s32 mdrvfb2_check_var(struct fb_var_screeninfo *var, struct fb_info *info); ++ ++static struct fb_var_screeninfo sg_mdrvfb2_default_var = ++{ ++ .xres = defult_XRES, ++ .yres = defult_YRES, ++ .xres_virtual = defult_XRES, ++ .yres_virtual = defult_YRES, ++ .bits_per_pixel = BPX, ++#if (BPX == 32) ++ .transp ={0,8,0}, ++ .red = { 24, 8, 0 }, /* {offset,length,!= 0 : MSB is right} */ ++ .green = { 16, 8, 0 }, ++ .blue = { 8, 8, 0 }, ++#elif (BPX == 16) ++ .red = { 11, 5, 0 }, /* {offset,length,!= 0 : MSB is right} */ ++ .green = { 5, 6, 0 }, ++ .blue = { 0, 5, 0 }, ++#endif ++ .activate = FB_ACTIVATE_NOW, ++ .height = -1, /* =maximum, in fb.h is delcalred as _u32* */ ++ .width = -1, ++ ++ /* timing useless ? use the vfb default */ ++ .pixclock = 100000,//20000, /* pixel clock in ps (pico seconds) */ ++ .left_margin = 24,//64, /* time from sync to picture */ ++ .right_margin = 4,//64, /* time from picture to sync */ ++ .upper_margin = 6,//32, /* time from sync to picture */ ++ .lower_margin = 4,//32, ++ .hsync_len = 64, /* length of horizontal sync */ ++ .vsync_len = 2, /* length of vertical sync */ ++ .vmode = FB_VMODE_NONINTERLACED, ++ /* non interlaced, the most basical framebuffer */ ++}; ++ ++/* Device independent unchangeable information */ ++static struct fb_fix_screeninfo sg_mdrvfb2_fix = ++{ ++ .id = "mdrv FB", ++ .type = FB_TYPE_PACKED_PIXELS, /* see FB_TYPE_* */ ++ .visual = FB_VISUAL_TRUECOLOR, /* see FB_VISUAL_* */ ++ .xpanstep = 0, /* zero if no hardware panning */ ++ .ypanstep = 0, ++ .ywrapstep = 0, ++ .line_length = (defult_XRES * BPX >> 3), /* length of a line in bytes */ ++ .mmio_start=0x20000000, /* Start of Memory Mapped I/O */ ++ /* (physical address) */ ++ .mmio_len=0x10000000, /* Length of Memory Mapped I/O */ ++ .accel = FB_ACCEL_NONE, ++ /* Indicate to driver which specific chip/card we have */ ++}; ++ ++static struct fb_videomode sg_mdrvfb2_default_fbmode; ++ ++static struct fb_ops sg_mdrvfb2_ops = ++{ ++ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = sys_fillrect, ++ ++ /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = sys_copyarea, ++ ++ /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = sys_imageblit, ++ ++ /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ .fb_mmap = mdrvfb2_mmap, /* for non cached memory */ ++ ++ /* vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); */ ++ .fb_ioctl = mdrvfb2_ioctl, ++ ++ .fb_pan_display = mdrvfb2_pan_display, ++ ++ .fb_check_var = mdrvfb2_check_var, ++ ++}; ++ ++//extern void MDrv_Scaler_Enable_GOP(BOOL); ++extern void sys_fillrect(struct fb_info *p, const struct fb_fillrect *rect); ++ ++/* virtual address in Kernel space, used in probe(), remove() */ ++//static void *sg_pG3D_fb2_vir_addr1 = 0; /* virtual address of frame buffer 1 */ ++static void *sg_pG3D_fb2_vir_addr1 = 0; /* virtual address of frame buffer 2 */ ++ ++#if 1 //def CONFIG_PM ++static int mdrvfb2_suspend(struct platform_device *pdev, ++ pm_message_t state); ++ ++static int mdrvfb2_resume(struct platform_device *pdev); ++#else ++#define mdrvfb2_suspend NULL ++#define mdrvfb2_resume NULL ++#endif ++ ++ ++ ++static int mdrvfb2_probe(struct platform_device *dev); ++static int mdrvfb2_remove(struct platform_device *dev); ++static void mdrvfb2_platform_release(struct device *device); ++/* device .name and driver .name must be the same, then it will call ++ probe function */ ++static struct platform_driver sg_mdrvfb2_driver = ++{ ++ .probe = mdrvfb2_probe, /* initiailize */ ++ .remove = mdrvfb2_remove, /* it free(mem), ++ release framebuffer, free irq etc. */ ++ .suspend = mdrvfb2_suspend, ++ .resume = mdrvfb2_resume, ++ ++ .driver = ++ { ++ .name = "mdrvfb2", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static u64 sg_mdrvfb2_device_lcd_dmamask = 0xffffffffUL; ++/* for 0x08000000 */ ++static struct platform_device sg_mdrvfb2_device = ++{ ++ .name = "mdrvfb2", ++ .id = 0, ++ .dev = ++ { ++ .release = mdrvfb2_platform_release, ++ .dma_mask = &sg_mdrvfb2_device_lcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ +diff --git a/drivers/mstar/fb/chicago/Makefile b/drivers/mstar/fb/chicago/Makefile +new file mode 100644 +index 00000000..ee4aec47 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/Makefile +@@ -0,0 +1,21 @@ ++# ++# Makefile for MStar fb device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++#--------gop-------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/chicago/gop ++EXTRA_CFLAGS += -Idrivers/mstar/fb/chicago/gop/hal ++#--------ge--------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/chicago/ge ++EXTRA_CFLAGS += -Idrivers/mstar/fb/chicago/ge/columbus2 ++ ++#EXTRA_CFLAGS += -Idrivers/mstar/gfx ++ ++# specific options ++EXTRA_CFLAGS += ++ ++# files ++obj-$(CONFIG_MS_FB_CHICAGO) += gop/mdrv_gop_io.o ++obj-$(CONFIG_MS_FB_CHICAGO) += gop/mdrv_gop.o ++obj-$(CONFIG_MS_FB_CHICAGO) += mdrv_fb.o +diff --git a/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge.c b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge.c +new file mode 100644 +index 00000000..49df2858 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge.c +@@ -0,0 +1,2430 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// File name: drvGE.c ++// Description: GR driver implementation. ++// 1. PE part : piexl engine ++// 2. Blt part : fast blt engine ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++//---------------------------------------------------------------------------- ++// Include Files ++//---------------------------------------------------------------------------- ++ ++#include ++#include /* printk() */ ++#include ++#include ++#include ++ ++ ++#include "mach/ms_types.h" ++#include "mhal_ge_reg.h" ++#include "mhal_ge.h" ++#include "mhal_ge_fp.h" ++ ++//---------------------------------------------------------------------------- ++// Compile options ++//---------------------------------------------------------------------------- ++// #define GE_DEBUG ++ ++//---------------------------------------------------------------------------- ++// Local Defines ++//---------------------------------------------------------------------------- ++#define WAIT_CMD_FIFO 1 ++#if WAIT_CMD_FIFO ++#define PATCH_RD_CMD 1 ++#else ++#define PATCH_RD_CMD 0 ++#endif ++ ++//---------------------------------------------------------------------------- ++// Debug Macros ++//---------------------------------------------------------------------------- ++#define GE_DEBUGINFO(x) //x ++#define GE_WARN(x) printk(KERN_WARNING x); ++ ++ //#undef GE_DEBUG ++// #define GE_DEBUG ++ ++#ifdef GE_DEBUG ++#define GE_ASSERT(_bool, _f) if (!(_bool)) { (_f); while (1) printk("G0"); } ++#else ++#define GE_ASSERT(_bool, _f) while (0) ++#endif // #ifdef SCL_DEBUG ++ ++#ifdef GE_DEBUG ++ ++#define _GE_CHECK_BUFFER_ALIGN0(addr, color_fmt) \ ++ switch ((color_fmt)){ \ ++ case GE_FMT_I1: \ ++ case GE_FMT_I2: \ ++ case GE_FMT_I4: \ ++ case GE_FMT_I8: \ ++ break; \ ++ case GE_FMT_YUV422: \ ++ case GE_FMT_1ABFGBG12355: \ ++ case GE_FMT_RGB565 : \ ++ case GE_FMT_ARGB1555 : \ ++ case GE_FMT_ARGB4444 : \ ++ GE_ASSERT(!(0x1 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ break; \ ++ case GE_FMT_ARGB8888 : \ ++ GE_ASSERT(!(0x3 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ break; \ ++ default: \ ++ GE_ASSERT(0, printk("[GE DRV][%06d] Invalid color format\n")); \ ++ break; \ ++ } ++ ++ ++#define _GE_CHECK_BUFFER_ALIGN1(addr, width, height, pitch, color_fmt) \ ++ switch ((color_fmt)){ \ ++ case GE_FMT_I1: \ ++ case GE_FMT_I2: \ ++ case GE_FMT_I4: \ ++ case GE_FMT_I8: \ ++ break; \ ++ case GE_FMT_YUV422: \ ++ case GE_FMT_1ABFGBG12355: \ ++ case GE_FMT_RGB565 : \ ++ case GE_FMT_ARGB1555 : \ ++ case GE_FMT_ARGB4444 : \ ++ GE_ASSERT(!(0x1 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ GE_ASSERT(!(0x1 & (pitch)), printk("[GE DRV][%06d] Bad buffer pitch (%d, %d)\n", (pitch), (color_fmt))); \ ++ GE_ASSERT(((pitch)>>1)== (width), printk("[GE DRV][%06d] Bad buffer pitch/width (%d, %d)\n", (pitch), (width))); \ ++ break; \ ++ case GE_FMT_ARGB8888 : \ ++ GE_ASSERT(!(0x3 & (addr)), printk("[GE DRV][%06d] Bad buffer address (0x%08x, %d)\n", (addr), (color_fmt))); \ ++ GE_ASSERT(!(0x3 & (pitch)), printk("[GE DRV][%06d] Bad buffer pitch (%d, %d)\n", (pitch), (color_fmt))); \ ++ GE_ASSERT(((pitch)>>2)== (width), printk("8888[GE DRV][%06d] Bad buffer pitch/width (%d, %d)\n", (pitch), (width))); \ ++ break; \ ++ default: \ ++ GE_ASSERT(0, printk("[GE DRV][%06d] Invalid color format\n")); \ ++ break; \ ++ } ++ ++#define _GE_SIMPLE_BB_CHECK() \ ++ GE_WaitAvailableCMDQueue(32); \ ++ if (!(GE_VAL_EN_STRETCH_BITBLT & GE_ReadReg(GE_REG_FMT_BLT))) \ ++ { \ ++ if (GE_ReadReg(GE_REG_STBB_INIT_DX) || GE_ReadReg(GE_REG_STBB_INIT_DY)) \ ++ { \ ++ while (1)printk("G1"); \ ++ } \ ++ if (GE_ReadReg(GE_REG_STBB_WIDTH)!= (GE_ReadReg(GE_REG_PRI_V1_X)- GE_ReadReg(GE_REG_PRI_V0_X)+ 1)) \ ++ { \ ++ while (1)printk("G2"); \ ++ } \ ++ if (GE_ReadReg(GE_REG_STBB_HEIGHT)!= (GE_ReadReg(GE_REG_PRI_V1_Y)- GE_ReadReg(GE_REG_PRI_V0_Y)+ 1)) \ ++ { \ ++ while (1)printk("G3"); \ ++ } \ ++ } ++ ++#else // #ifdef GE_DEBUG ++ ++#define _GE_CHECK_BUFFER_ALIGN0(addr, color_fmt) while (0); ++#define _GE_CHECK_BUFFER_ALIGN1(addr, width, height, pitch, color_fmt) while (0); ++#define _GE_SIMPLE_BB_CHECK() while (0); ++ ++#endif // #ifdef GE_DEBUG ++ ++//---------------------------------------------------------------------------- ++// Macros ++//---------------------------------------------------------------------------- ++#define delay(ms) ++ ++#if 1 ++#define GE_WaitCmdEmpty() while(((GE_Reg(GE_REG_STATUS)) & GE_MSK_CMQ_FIFO_STATUS) != 0x80) ++#define GE_WaitCmdNotFull() while ((GE_Reg(GE_REG_STATUS) & GE_MSK_CMQ_FIFO_STATUS)== 0x00) ++#else ++#define GE_WaitCmdEmpty ++#define GE_WaitCmdNotFull ++#endif ++ ++ ++//---------------------------------------------------------------------------- ++// Global Variables ++//---------------------------------------------------------------------------- ++ ++DEFINE_SEMAPHORE(g_GESem); ++ ++#ifdef DBGLOG ++//debug use only ++static U16 _bOutFileLog = false; ++static U16 *_pu16OutLogAddr = NULL; ++static U16 _u16LogCount=0; ++#endif ++ ++static U32 _u32Reg60hFlag = 0; ++#if PATCH_RD_CMD ++static U32 _u32Reg0hValue = 0; ++#endif ++static U16 _u16PeClipX1 = 0; ++static U16 _u16PeClipX2 = 0; ++static U16 _u16PeClipY1 = 0; ++static U16 _u16PeClipY2 = 0; ++ ++static U8 _u8TypeGE[32] = "MstarTypeGE"; ++ ++//---------------------------------------------------------------------------- ++// Local Function Prototypes ++//---------------------------------------------------------------------------- ++void GE_ConvertRGB2DBFmt(GE_Buffer_Format Fmt, U32 *color, U16* low, U16* high); ++// void BLT_ConvertRGB2DBFmt(GE_Buffer_Format Fmt, U32 *colorinfo, U16* low, U16* high); ++ ++//------------------------------------------------------------------------------------------------- ++static U32 GE_ReadReg(U32 addr) ++{ ++ return GE_Reg(addr); ++} ++ ++//------------------------------------------------------------------------------------------------- ++static void GE_WaitAvailableCMDQueue(U8 u8CMDCount) ++{ ++#if WAIT_CMD_FIFO ++ U32 wait_count= 1; ++ unsigned int tt ; ++ u8CMDCount = 32 ; ++ u8CMDCount = (u8CMDCount > 32)? 32 : u8CMDCount; ++ ++ //Note: In Titania, 1 empty count can save 2 commands. ++ // And if the empty item only saves 1 commands, it is treated as empty; ++ // therefore 15 cmmands will need (15+1)/2 empty items. ++ u8CMDCount = ((u8CMDCount + 1)>>1); ++ ++ ++ // check GE busy status to avoid command queue bug ++ tt = 0 ; ++ while (((GE_Reg(GE_REG_STATUS)&0x01))) ++ { ++ //msleep(2) ; ++ tt++ ; ++ if( (tt&0xFFFFFF)==0 ) ++ printk("G5 ") ; ++ } ++ ++ while (((GE_Reg(GE_REG_STATUS)&GE_MSK_CMQ_FIFO_STATUS)>>2) < u8CMDCount) ++ { ++ if (0x0000== (0xFFF & wait_count)) ++ { ++ printk("[GE INFO] GE wait command queue\n"); ++ } ++ wait_count++; ++ } ++#endif ++} ++ ++void outGE_WaitAvailableCMDQueue(void){ ++ GE_WaitAvailableCMDQueue(32) ; ++} ++ ++static void GE_WriteReg(U32 u32addr, U32 u32val) ++{ ++#if WAIT_CMD_FIFO ++ // Wait GE command queue empty before fire to avoid GE hang ++ if (GE_REG_CMD== u32addr) ++ { ++ GE_WaitAvailableCMDQueue(32); ++ } ++ ++ GE_Reg(u32addr)=u32val; ++#else ++ GE_Reg(u32addr)=u32val; ++ if ((u32addr == GE_REG_CMD)&&(GE_Reg(GE_REG_EN)& GE_VAL_EN_PE)) ++ { ++ while ( GE_Reg(GE_REG_STATUS)& GE_VAL_BUSY) ++ { ++ MsOS_YieldTask(); ++ } ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++static U16 GE_CheckInClipWindow(U16 u16X1, U16 u16Y1, U16 u16X2, U16 u16Y2) ++{ ++ if (((u16X1 < _u16PeClipX1) && (u16X2 < _u16PeClipX1)) || ++ ((u16X1 > _u16PeClipX2) && (u16X2 > _u16PeClipX2)) || ++ ((u16Y1 < _u16PeClipY1) && (u16Y2 < _u16PeClipY1)) || ++ ((u16Y1 > _u16PeClipY2) && (u16Y2 > _u16PeClipY2))) ++ { ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Description: for debug output register log use ++// Arguments: enable - true or false ++// ++// Return: NONE ++// ++// Notes: if any ++//------------------------------------------------------------------------------------------------- ++void MHal_GE_Debug_SetOutputLog(U16 enable) ++{ ++#ifdef DBGLOG ++ _bOutFileLog = enable; ++ if (enable) ++ { ++ _pu16OutLogAddr = (U16 *)GE_LOG_ADR; ++ memset(_pu16OutLogAddr, 0, 0x100000); ++ //write header ++ *_pu16OutLogAddr = 0xffff; ++ _pu16OutLogAddr++; ++ *_pu16OutLogAddr = 0x55AA; ++ _pu16OutLogAddr++; ++ _u16LogCount =2; ++ } ++ else ++ { ++ *_pu16OutLogAddr = 0xffff; ++ _pu16OutLogAddr++; ++ *_pu16OutLogAddr = _u16LogCount; ++ _pu16OutLogAddr++; ++ _u16LogCount = 0; ++ } ++#endif ++} ++ ++static void GE_Enable_CmdQ(void) ++{ ++ GE_WriteReg(GE_REG_FMT_BLT, GE_VAL_EN_CMDQ); ++} ++ ++static void GE_Register_Reset(void) ++{ ++/* ++#if 1 ++ GE_WaitAvailableCMDQueue(32); ++#else ++ while (((GE_Reg(GE_REG_STATUS) & GE_VAL_BUSY))){ ++ MsOS_YieldTask(); ++ } ++ while (((GE_Reg(GE_REG_STATUS) & 0xfc)>>2) < 32) ++ { ++ MsOS_YieldTask(); ++ } ++#endif ++*/ ++ ++ // GE_WriteReg(GE_REG_EN, 0); ++ GE_WriteReg(GE_REG_EN, GE_VAL_EN_PE); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = GE_VAL_EN_PE; ++#endif ++ ++ GE_WriteReg(GE_REG_STBB_TH, 0x08); ++ ++ //Set Line pattern to default. ++ //GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ //GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ _u32Reg60hFlag = 0; ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Begin PE Engine drawing, this function should be called before all PE drawing function, ++/// and it will lock PE engine resource, reset all PE register and static variable. ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_BeginDraw(void) ++{ ++ down(&g_GESem); ++ ++ GE_DEBUGINFO(printk( "MHal_GE_BeginDraw\n")); ++ ++#ifdef DYNAMIC_POWER_ON_OFF ++ MDrv_Power_ClockTurnOn(E_POWER_MODULE_GE); ++#endif ++ ++ GE_Register_Reset(); ++ ++ return GESTATUS_SUCCESS; ++} ++//------------------------------------------------------------------------------------------------- ++/// Initial PE engine ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MHal_GE_Init(void) ++{ ++ GE_DEBUGINFO(printk( "MHal_GE_Init\n")); ++ ++#ifdef MOVE_TO_USER_SPACE ++#ifdef DYNAMIC_POWER_ON_OFF ++ MDrv_Power_ClockTurnOn(E_POWER_MODULE_GE); ++#endif ++#endif ++ ++ GE_Enable_CmdQ(); ++ ++ GE_WriteReg(GE_REG_SCK_LTH0, *(U32*)&_u8TypeGE[0]); ++ GE_WriteReg(GE_REG_SCK_LTH1, *(U32*)&_u8TypeGE[4]); ++ GE_WriteReg(GE_REG_SCK_HTH0, *(U32*)&_u8TypeGE[8]); ++ GE_WriteReg(GE_REG_SCK_HTH1, *(U32*)&_u8TypeGE[12]); ++ ++#ifdef DYNAMIC_POWER_ON_OFF ++ while ( GE_Reg(GE_REG_STATUS)& GE_VAL_BUSY); ++#if MOVE_TO_USER_SPACE ++ MDrv_Power_ClockTurnOff(E_POWER_MODULE_GE); ++#endif ++#endif ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// End PE engine drawing (pair with MHal_GE_BeginDraw), this function should be called after ++/// all PE drawing function. And it will release PE engine resource. ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_EndDraw(void) ++{ ++#ifdef DYNAMIC_POWER_ON_OFF ++ GE_WaitAvailableCMDQueue(32); ++ while (GE_Reg(GE_REG_STATUS)& GE_VAL_BUSY) ++ { ++ MsOS_YieldTask(); ++ } ++ MDrv_Power_ClockTurnOff(E_POWER_MODULE_GE); ++#endif ++ ++ up(&g_GESem); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE Engine dither ++/// @param enable \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetDither(U16 enable) ++{ ++ U32 u32Value; ++ ++ GE_DEBUGINFO(printk("MDrv_SetDither\n")); ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_DITHER; ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_DITHER; ++ } ++ ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE source color key ++/// @param enable \b IN: true/false\n ++/// When enable is FALSE, do not care the other parameters.\n ++/// @param opMode \b IN: source color key mode ++/// The alpha channel does not matter\n ++/// @param fmt \b IN: source color key format ++/// @param ps_color \b IN: pointer of source color key start (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// For all RGB color, the color set as the ARGB8888 format.\n ++/// Each color component need to shift to high bit.\n ++/// Use ARGB1555 as the example, the source color key as the following:\n ++/// ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++/// *ps_color --> A0000000RRRRR000GGGGG000BBBBB000 (every character represents one bit)\n\n ++/// For GE_FMT_I8 format, the index set to b component (ps_color->b = b).\n ++/// For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++/// @param pe_color \b IN: pointer of source color key end (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetSrcColorKey(U16 enable, ++ GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, ++ void *ps_color, ++ void *pe_color) ++{ ++ U32 u32Value, u32Value2; ++ U16 u16Color0, u16Color1; ++ ++ GE_DEBUGINFO(printk("MHal_GE_SetSrcColorKey\n")); ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_SCK; ++ ++ // Color key threshold ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)ps_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_SCK_LTH0, u16Color0); ++ GE_WriteReg(GE_REG_SCK_LTH1, u16Color1); ++ ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)pe_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_SCK_HTH0, u16Color0); ++ GE_WriteReg(GE_REG_SCK_HTH1, u16Color1); ++ ++ // Color op ++ u32Value2 = GE_ReadReg(GE_REG_KEY_OP); ++ u32Value2 = (u32Value2 & ~GE_VAL_SCK_OP_TRUE) | opMode; ++ GE_WriteReg(GE_REG_KEY_OP, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~(GE_VAL_EN_SCK); ++ } ++ ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE destination color key ++/// @param enable \b IN: true/false\n ++/// When enable is FALSE, do not care the other parameters.\n ++/// @param opMode \b IN: destination color key mode\n ++/// The alpha channel does not matter\n ++/// @param fmt \b IN: destination color key format ++/// @param ps_color \b IN: pointer of destination color key start (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// For all RGB color, the color set as the ARGB8888 format.\n ++/// Each color component need to shift to high bit.\n ++/// Use ARGB1555 as the example, the source color key as the following:\n ++/// ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++/// *ps_color --> A0000000RRRRR000GGGGG000BBBBBB000 (every character represents one bit)\n\n ++/// For GE_FMT_I8 format, the index set to b component (ps_color->b = b).\n ++/// For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++/// @param pe_color \b IN: pointer of destination color key end (GE_RGB_COLOR or GE_BLINK_DATA depend on color format).\n ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetDstColorKey(U16 enable, ++ GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, ++ void *ps_color, ++ void *pe_color) ++{ ++ U32 u32Value, u32Value2; ++ U16 u16Color0, u16Color1; ++ ++ GE_DEBUGINFO(printk("MHal_GE_SetDstColorKey\n")); ++ ++ GE_WaitAvailableCMDQueue(8); ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_DCK; ++ ++ // Color key threshold ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)ps_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_DCK_LTH0, u16Color0); ++ GE_WriteReg(GE_REG_DCK_LTH1, u16Color1); ++ ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)pe_color, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_DCK_HTH0, u16Color0); ++ GE_WriteReg(GE_REG_DCK_HTH1, u16Color1); ++ ++ // Color op ++ u32Value2 = GE_ReadReg(GE_REG_KEY_OP); ++ u32Value2 = (u32Value2 & ~GE_VAL_DCK_OP_TRUE) | (opMode<<1); ++ GE_WriteReg(GE_REG_KEY_OP, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_DCK; ++ } ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE intensity : total 16 color Palette in PE ++/// @param id \b IN: id of intensity ++/// @param fmt \b IN: intensity color format (GE_FMT_ARGB8888 , GE_FMT_1BAAFGBG123433 or GE_FMT_I8) ++/// @param pColor \b IN: pointer of intensity (GE_RGB_COLOR or GE_BLINK_DATA depend on color format) ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @return GESTATUS_INVALID_INTENSITY_ID - Inavlid index (id >= 16) ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetIntensity(U32 id, GE_Buffer_Format fmt, U32 *pColor) ++{ ++ U16 u16Color0, u16Color1; ++ GE_DEBUGINFO(printk("MHal_GE_SetIntensity\n")); ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++ if (id < GE_INTENSITY_NUM) ++ { ++ GE_ConvertRGB2DBFmt(fmt, (U32 *)pColor, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_I0_C0 + (2*id), u16Color0); ++ GE_WriteReg(GE_REG_I0_C1 + (2*id), u16Color1); ++ } ++ else ++ { ++ return GESTATUS_INVALID_INTENSITY_ID; ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE raster operation ++/// @param enable \b IN: true/false ++/// @param eRopMode \b IN: raster operation ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetROP2(U16 enable, GE_ROP2_OP eRopMode) ++{ ++ U32 u32Value, u32Value2; ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_ROP; ++ ++ u32Value2 = GE_ReadReg(GE_REG_ROP2); ++ u32Value2 = (u32Value2 & ~GE_MSK_ROP2) | eRopMode; ++ GE_WriteReg(GE_REG_ROP2, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_ROP; ++ } ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++void dummyRegWrite( void ){ ++ GE_WriteReg(GE_REG_STBB_WIDTH, GE_ReadReg(GE_REG_STBB_WIDTH)); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Force PE draw line ++/// @param pline \b IN: pointer to line info ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_DrawLine(GE_DRAW_LINE_INFO *pline) ++{ ++ U32 u32Start, u32End; ++ U32 u32Width, u32Height, u32Ratio; ++ U32 u32Value, u32Value2; ++ U32 u32X1, u32X2, u32Y1, u32Y2; ++ S32 i; ++ S16 s16Dif; ++ U16 bYMajor = false; ++ U16 bInverse = false; ++ U16 u16Color0, u16Color1; ++ GE_RGB_COLOR color_s, color_e; ++ GE_BLINK_DATA *blinkData = NULL; ++ ++ GE_DEBUGINFO( printk("MHal_GE_DrawLine\n")); ++ ++ GE_WaitAvailableCMDQueue(24); ++ ++ if ((!GE_CheckInClipWindow(pline->x1, pline->y1, pline->x2, pline->y2)) && (pline->width == 1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ ++ u32X1 = pline->x1; ++ u32X2 = pline->x2; ++ u32Y1 = pline->y1; ++ u32Y2 = pline->y2; ++ ++ u32Width = u32X2 - u32X1 ; ++ u32Height = u32Y2 - u32Y1 ; ++ color_s = pline->colorRange.color_s; ++ color_e = pline->colorRange.color_e; ++ ++ if ( u32Y1 > u32Y2 ) ++ { ++ u32Height = u32Y1 - u32Y2; ++ } ++ ++ if ( u32X1 > u32X2 ) ++ { ++ u32Width = u32X1 - u32X2; ++ } ++ ++ ++ u32Value2 = GE_VAL_PRIM_LINE; ++ ++ if( (u32Height >= u32Width)||(u32Width==0)) ++ { ++ bYMajor = true; ++ } ++ ++ if (bYMajor) ++ { ++ if (pline->x1 >= pline->x2) ++ { ++ if (!GE_CheckInClipWindow(pline->x1+pline->width, pline->y1, pline->x2, pline->y2)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ else ++ { ++ if (!GE_CheckInClipWindow(pline->x1, pline->y1, pline->x2+pline->width, pline->y2)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ } ++ else ++ { ++ if (pline->y1 >= pline->y2) ++ { ++ if (!GE_CheckInClipWindow(pline->x1, pline->y1+pline->width, pline->x2, pline->y2)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ else ++ { ++ if (!GE_CheckInClipWindow(pline->x1, pline->y1, pline->x2, pline->y2+pline->width)) ++ { ++ return GESTATUS_FAIL; ++ } ++ } ++ } ++/* ++ if ( bYMajor ) ++ { ++ if ( u32X1 > u32X2) ++ { ++ u32X1 = pline->x2; ++ u32X2 = pline->x1; ++ u32Y1 = pline->y2; ++ u32Y2 = pline->y1; ++ bInverse = true; ++ } ++ if ( u32Y1 > u32Y2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; ++ } ++ else ++ { ++ if ( u32Y1 > u32Y2) ++ { ++ u32X1 = pline->x2; ++ u32X2 = pline->x1; ++ u32Y1 = pline->y2; ++ u32Y2 = pline->y1; ++ bInverse = true; ++ } ++ if ( u32X1 > u32X2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; ++ } ++*/ ++ if ( bYMajor ) ++ { ++ if ( u32X1 > u32X2) ++ { ++ bInverse = true; ++ } ++ if ( u32Y1 > u32Y2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; // @FIXME: Richard: should be Y NEG??? ++ } ++ else ++ { ++ if ( u32Y1 > u32Y2) ++ { ++ bInverse = true; ++ } ++ if ( u32X1 > u32X2) ++ u32Value2 |= GE_VAL_DRAW_DST_DIR_X_NEG; ++ } ++ ++ if ((u32Width==0)||(u32Height==0)) ++ { ++ u32Value = 0; ++ } ++ else ++ { ++ ++ if ( bYMajor ) ++ { ++ if (bInverse) ++ { ++ u32Value = (0x4000 - (U16)Divide2Fixed(u32Width, u32Height, 1, 12)) << 1; //sc ++ } ++ else ++ { ++ u32Value = (U16)Divide2Fixed(u32Width, u32Height, 1, 12) << 1; //sc ++ } ++ bInverse = FALSE; ++ } ++ else ++ { ++ if (bInverse) ++ { ++ u32Value = (0x4000 - (U16)Divide2Fixed(u32Height, u32Width, 1, 12)) << 1; //sc ++ } ++ else ++ { ++ u32Value = (U16)Divide2Fixed(u32Height, u32Width, 1, 12) << 1; //sc ++ } ++ bInverse = FALSE; ++ } ++ } ++ ++ if ( bYMajor ) ++ { ++ GE_WriteReg(GE_REG_LINE_DTA, (u32Value & GE_MSK_LINE_DTA )|GE_VAL_LINE_Y_MAJOR); ++ } ++ else ++ { ++ GE_WriteReg(GE_REG_LINE_DTA, (u32Value & GE_MSK_LINE_DTA )); ++ } ++ ++ // Start color ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355!= pline->fmt) ++ // if (pline->fmt != GE_FMT_1BAAFGBG123433) ++ { ++ GE_ConvertRGB2DBFmt(pline->fmt, (U32*)&color_s, &u16Color0, &u16Color1); ++ } ++ else ++ { ++#if 0 ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ // 1 A B Fg Bg ++ // 1 2 3 5 5 ++ // ++ // 1 B A A Fg Bg ++ // 1 2 3 4 3 3 ++ ++ blinkData =(GE_BLINK_DATA *)&color_s; ++ u16Color0 = ((((blinkData->background&0x7) | ((blinkData->foreground&0x7)<<3))<<2) | ((blinkData->Bits.BlinkAlpha&0xf)<<12)); ++ u16Color1 = (0xff00 | ((((blinkData->Bits.Blink&0x3)<<3) | (blinkData->Bits.Alpha&0x7))<<3)); ++#else ++ blinkData= (GE_BLINK_DATA *)&color_s; ++ u16Color0= (0x1F & blinkData->background) | ++ ((0x1F & blinkData->foreground) << 8); ++ u16Color1= (0x7 & blinkData->Bits.Blink) | ++ ((0x3 & blinkData->Bits.Alpha) << 3) | ++ BIT8; ++#endif ++ } ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ ++ if (bYMajor) u32Ratio = u32Height; ++ else u32Ratio = u32Width; ++ ++ if(pline->flag & GELINE_FLAG_COLOR_GRADIENT) ++ { ++ if(bInverse) ++ { ++ GE_ConvertRGB2DBFmt(pline->fmt, (U32*)&color_e, &u16Color0, &u16Color1); ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ //GE_WriteReg(GE_REG_PRI_BG_ST, (pline->color2.b & 0xff) | ((pline->color2.g & 0xff) << 8)); ++ //GE_WriteReg(GE_REG_PRI_RA_ST, (pline->color2.r & 0xff) | ((pline->color2.a & 0xff) << 8)); ++ } ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.r - color_e.r; ++ } ++ else ++ { ++ s16Dif = color_e.r - color_s.r; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio , 7, 12); ++ GE_WriteReg(GE_REG_PRI_R_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_R_DX1, u32Value >> 16); ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.g - color_e.g; ++ } ++ else ++ { ++ s16Dif = color_e.g - color_s.g; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio, 7, 12); ++ GE_WriteReg(GE_REG_PRI_G_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_G_DX1, u32Value >> 16); ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.b - color_e.b; ++ } ++ else ++ { ++ s16Dif = color_e.b - color_s.b; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio, 7, 12); ++ GE_WriteReg(GE_REG_PRI_B_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_B_DX1, u32Value >> 16); ++ ++ if(bInverse) ++ { ++ s16Dif = color_s.a - color_e.a; ++ } ++ else ++ { ++ s16Dif = color_e.a - color_s.a; ++ } ++ u32Value = Divide2Fixed(s16Dif, u32Ratio, 4, 11); ++ GE_WriteReg(GE_REG_PRI_A_DX, u32Value & 0xffff); ++ ++ u32Value2 |= GE_VAL_LINE_GRADIENT; ++ } ++ ++ GE_ASSERT(0x7FF>= u32X1, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32X2, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32Y1, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32Y2, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_WriteReg(GE_REG_PRI_V0_X, u32X1); ++ GE_WriteReg(GE_REG_PRI_V1_X, u32X2); ++ GE_WriteReg(GE_REG_PRI_V0_Y, u32Y1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, u32Y2); ++ ++ if(bYMajor) ++ { ++ u32Start = u32X1; ++ u32End = u32X2; ++ for(i=0;iwidth;i++) ++ { ++ GE_WaitAvailableCMDQueue(8); ++ GE_ASSERT(0x7FF>= u32Start, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32End, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_WriteReg(GE_REG_LENGTH, u32Height); ++ GE_WriteReg(GE_REG_PRI_V0_X, u32Start); ++ GE_WriteReg(GE_REG_PRI_V1_X, u32End); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ u32Start++; ++ u32End++; ++ } ++ } ++ else ++ { ++ u32Start = u32Y1; ++ u32End = u32Y2; ++ for (i=0;iwidth;i++) ++ { ++ GE_WaitAvailableCMDQueue(8); ++ GE_ASSERT(0x7FF>= u32Start, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_ASSERT(0x7FF>= u32End, printk("[GE DRV][%06d] out of range\n", __LINE__)); ++ GE_WriteReg(GE_REG_LENGTH, u32Width); ++ GE_WriteReg(GE_REG_PRI_V0_Y, u32Start); ++ GE_WriteReg(GE_REG_PRI_V1_Y, u32End); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ u32Start++; ++ u32End++; ++ } ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++GESTATUS MHal_GE_DrawOval(GE_OVAL_FILL_INFO* pOval) ++{ ++ S32 x, y, c_x, c_y; ++ S32 Xchange, Ychange; ++ S32 EllipseError; ++ S32 TwoASquare, TwoBSquare; ++ S32 StoppingX, StoppingY; ++ U32 Xradius, Yradius; ++ U32 u32Value2 = 0; ++ U16 u16Color0, u16Color1; ++ GE_BLINK_DATA *blinkData = NULL; ++ ++ if (!GE_CheckInClipWindow(pOval->dstBlock.x, pOval->dstBlock.y, pOval->dstBlock.x+pOval->dstBlock.width-1, pOval->dstBlock.y+pOval->dstBlock.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++ Xradius = (pOval->dstBlock.width - pOval->u32LineWidth*2) / 2; ++ Yradius = (pOval->dstBlock.height - pOval->u32LineWidth*2) / 2; ++ ++ /* center of ellipse */ ++ //c_x = pOval->dstBlock.x + Xradius + pOval->u32LineWidth/2; ++ //c_y = pOval->dstBlock.y + Yradius + pOval->u32LineWidth/2; ++ c_x = pOval->dstBlock.x + Xradius + pOval->u32LineWidth; ++ c_y = pOval->dstBlock.y + Yradius + pOval->u32LineWidth; ++ ++ TwoASquare = 2*Xradius*Xradius; ++ TwoBSquare = 2*Yradius*Yradius; ++ ++ /*1st set of points*/ ++ x = Xradius-1; /*radius zero == draw nothing*/ ++ y = 0; ++ ++ Xchange = Yradius*Yradius*(1-2*Xradius); ++ Ychange = Xradius*Xradius; ++ ++ EllipseError = 0; ++ ++ StoppingX = TwoBSquare*Xradius; ++ StoppingY = 0; ++ ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ ++ u32Value2 = GE_VAL_PRIM_LINE; ++ GE_WriteReg(GE_REG_LINE_DTA, 0); ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355!= pOval->fmt) ++ // if (pOval->fmt != GE_FMT_1BAAFGBG123433) ++ { ++ GE_ConvertRGB2DBFmt(pOval->fmt, (U32*)&pOval->color, &u16Color0, &u16Color1); ++ } ++ else ++ { ++#if 0 ++ blinkData =(GE_BLINK_DATA *)&pOval->blink_data; ++ u16Color0 = ((((blinkData->background&0x7) | ((blinkData->foreground&0x7)<<3))<<2) | ((blinkData->Bits.BlinkAlpha&0xf)<<12)); ++ u16Color1 = (0xff00 | ((((blinkData->Bits.Blink&0x3)<<3) | (blinkData->Bits.Alpha&0x7))<<3)); ++#else ++ blinkData =(GE_BLINK_DATA *)&pOval->blink_data; ++ u16Color0= (0x1F & blinkData->background) | ++ ((0x1F & blinkData->foreground) << 8); ++ u16Color1= (0x7 & blinkData->Bits.Blink) | ++ ((0x3 & blinkData->Bits.Alpha) << 3) | ++ BIT8; ++#endif ++ } ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ ++ ++ ++ ++ /*Plot 2 ellipse scan lines for iteration*/ ++ while (StoppingX > StoppingY) ++ { ++ GE_WaitAvailableCMDQueue(16); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y + y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y + y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y - y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y - y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ ++y; ++ StoppingY += TwoASquare; ++ EllipseError += Ychange; ++ Ychange += TwoASquare; ++ if (( 2*EllipseError + Xchange) > 0) ++ { ++ --x; ++ StoppingX -= TwoBSquare; ++ EllipseError += Xchange; ++ Xchange += TwoBSquare; ++ } ++ } ++ ++ /*2nd set of points*/ ++ x = 0; ++ y = Yradius-1; /*radius zero == draw nothing*/ ++ Xchange = Yradius*Yradius; ++ Ychange = Xradius*Xradius*(1-2*Yradius); ++ EllipseError = 0; ++ StoppingX = 0; ++ StoppingY = TwoASquare*Yradius; ++ ++ /*Plot 2 ellipse scan lines for iteration*/ ++ while (StoppingX < StoppingY) ++ { ++ GE_WaitAvailableCMDQueue(16); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y + y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y + y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, c_x - x); ++ GE_WriteReg(GE_REG_PRI_V1_X, c_x + x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, c_y - y); ++ GE_WriteReg(GE_REG_PRI_V1_Y, c_y - y); ++ GE_WriteReg(GE_REG_LENGTH, 2*x); ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ ++x; ++ StoppingX += TwoBSquare; ++ EllipseError += Xchange; ++ Xchange += TwoBSquare; ++ if ((2*EllipseError + Ychange) > 0) ++ { ++ --y; ++ StoppingY -= TwoASquare; ++ EllipseError += Ychange; ++ Ychange += TwoASquare; ++ } ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Force PE rectangle fill ++/// @param pfillblock \b IN: pointer to block info ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_RectFill(GE_RECT_FILL_INFO *pfillblock) ++{ ++ S16 s16Dif; ++ U32 u32Value, u32Value2; ++ GE_RGB_COLOR color_s, color_e; ++ U16 u16Color0, u16Color1; ++ GE_BLINK_DATA *blinkData = NULL; ++ ++ ++ GE_DEBUGINFO( printk("MHal_GE_RectFill\n")); ++ ++ if((pfillblock->dstBlock.width == 0) ||(pfillblock->dstBlock.height==0)) ++ { ++ GE_DEBUGINFO(printk("MHal_GE_RectFill error!! width or height equal 0!!\n")); ++ return FALSE; ++ } ++ ++ if (!GE_CheckInClipWindow(pfillblock->dstBlock.x, pfillblock->dstBlock.y, ++ pfillblock->dstBlock.x+pfillblock->dstBlock.width-1, ++ pfillblock->dstBlock.y+pfillblock->dstBlock.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(20); ++ ++ //u32Value = GE_ReadReg(GE_REG_EN); ++ //u32Value |= GE_VAL_EN_PE; ++ //GE_WriteReg(GE_REG_EN, u32Value); ++ ++ GE_WriteReg(GE_REG_PRI_V0_X, pfillblock->dstBlock.x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, pfillblock->dstBlock.y); ++ GE_WriteReg(GE_REG_PRI_V1_X, pfillblock->dstBlock.x + pfillblock->dstBlock.width - 1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, pfillblock->dstBlock.y + pfillblock->dstBlock.height - 1); ++ ++ // Start color ++ color_s = pfillblock->colorRange.color_s; ++ color_e = pfillblock->colorRange.color_e; ++ ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355!= pfillblock->fmt) ++ // if (pfillblock->fmt != GE_FMT_1BAAFGBG123433) ++ { ++ GE_ConvertRGB2DBFmt(pfillblock->fmt, (U32*)&color_s, &u16Color0, &u16Color1); ++ } ++ else ++ { ++#if 0 ++ blinkData =(GE_BLINK_DATA *)&color_s; ++ u16Color0 = ((((blinkData->background&0x7) | ((blinkData->foreground&0x7)<<3))<<2) | ((blinkData->Bits.BlinkAlpha&0xf)<<12)); ++ u16Color1 = (0xff00 | ((((blinkData->Bits.Blink&0x3)<<3) | (blinkData->Bits.Alpha&0x7))<<3)); ++#else ++ blinkData= (GE_BLINK_DATA *)&color_s; ++ u16Color0= (0x1F & blinkData->background) | ++ ((0x1F & blinkData->foreground) << 8); ++ u16Color1= (0x7 & blinkData->Bits.Blink) | ++ ((0x3 & blinkData->Bits.Alpha) << 3) | ++ BIT8; ++#endif ++ } ++ GE_WriteReg(GE_REG_PRI_BG_ST, u16Color0); ++ GE_WriteReg(GE_REG_PRI_RA_ST, u16Color1); ++ ++ ++ GE_WriteReg(GE_REG_PRI_A_DY, 0); ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ u32Value2 = GE_VAL_PRIM_RECTANGLE; ++ ++ if((pfillblock->flag & GERECT_FLAG_COLOR_GRADIENT_Y) == GERECT_FLAG_COLOR_GRADIENT_Y) ++ { ++ s16Dif = color_e.r - color_s.r; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_R_DY0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_R_DY1, u32Value >> 16); ++ ++ s16Dif = color_e.g - color_s.g; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_G_DY0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_G_DY1, u32Value >> 16); ++ ++ s16Dif = color_e.b - color_s.b; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_B_DY0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_B_DY1, u32Value >> 16); ++ ++ s16Dif = color_e.a - color_s.a; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.height - 1, 4, 11); ++ GE_WriteReg(GE_REG_PRI_A_DY, u32Value & 0xffff); ++ ++ u32Value2 |= GE_VAL_RECT_GRADIENT_V; ++ } ++ if((pfillblock->flag & GERECT_FLAG_COLOR_GRADIENT_X) == GERECT_FLAG_COLOR_GRADIENT_X) ++ { ++ s16Dif = color_e.r - color_s.r; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_R_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_R_DX1, u32Value >> 16); ++ ++ s16Dif = color_e.g - color_s.g; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_G_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_G_DX1, u32Value >> 16); ++ ++ s16Dif = color_e.b - color_s.b; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 7, 12); ++ GE_WriteReg(GE_REG_PRI_B_DX0, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_PRI_B_DX1, u32Value >> 16); ++ ++ s16Dif = color_e.a - color_s.a; ++ u32Value = Divide2Fixed(s16Dif, pfillblock->dstBlock.width - 1, 4, 11); ++ GE_WriteReg(GE_REG_PRI_A_DX, u32Value & 0xffff); ++ ++ u32Value2 |= GE_VAL_RECT_GRADIENT_H; ++ } ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ GE_WriteReg(GE_REG_CMD, u32Value2|_u32Reg60hFlag); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Reset PE line pattern ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_Line_Pattern_Reset(void) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++ u32Value = GE_ReadReg(GE_REG_LPT) | GE_VAL_LPT_RESET; ++ GE_WriteReg(GE_REG_LPT, u32Value); ++ ++ u32Value = GE_ReadReg(GE_REG_LPT) & (~GE_VAL_LPT_RESET); ++ GE_WriteReg(GE_REG_LPT, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE line pattern ++/// @param enable \b IN: true/false ++/// @param linePattern \b IN: p0-0x3F one bit represent draw(1) or not draw(0) ++/// @param repeatFactor \b IN: 0 : repeat once, 1 : repeat twice, 2: repeat 3, 3: repeat 4 ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_Set_Line_Pattern(U16 enable, U8 linePattern, U8 repeatFactor) ++{ ++ U32 u32Value, u32Value2; ++ ++ GE_WaitAvailableCMDQueue(6); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if (enable) ++ { ++ u32Value |= GE_VAL_EN_LPT; ++ u32Value2 = ((linePattern & GE_MSK_LP) | ((repeatFactor << 6) & GE_MSK_LPT_FACTOR) | GE_VAL_LPT_RESET); ++ GE_WriteReg(GE_REG_LPT, u32Value2); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_LPT; ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | GE_VAL_LPT_RESET | (0x3F))); ++ GE_WriteReg(GE_REG_LPT, (GE_VAL_LINE_LAST | (0x3F))); ++ } ++ GE_WriteReg(GE_REG_EN, u32Value); ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE Bit blt ++/// @param drawbuf \b IN: pointer to drawbuf info ++/// @param drawflag \b IN: draw flag \n ++/// GEDRAW_FLAG_DEFAULT \n ++/// GEDRAW_FLAG_SCALE \n ++/// GEDRAW_FLAG_DUPLICAPE \n ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_BitBlt(GE_DRAW_RECT *drawbuf,U32 drawflag) ++{ ++ U32 u32Width, u32Height; ++ U32 u32Value, u32Value2; ++ ++ if((!drawbuf->dstblk.width)||(!drawbuf->dstblk.height)||(!drawbuf->srcblk.width)||(!drawbuf->srcblk.height)) { ++ GE_WARN("GE bilblt: zero condition!!!!!\n"); ++ return GESTATUS_SUCCESS; // no need to do things, so it means success ++ } ++ ++ GE_DEBUGINFO( printk( "MHal_GE_BitBlt\n" ) ); ++ if (!GE_CheckInClipWindow(drawbuf->dstblk.x, drawbuf->dstblk.y, ++ drawbuf->dstblk.x+drawbuf->dstblk.width-1, ++ drawbuf->dstblk.y+drawbuf->dstblk.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(20); ++ ++ u32Value2 = GE_ReadReg(GE_REG_FMT_BLT); ++ ++ u32Width = drawbuf->srcblk.width; ++ u32Height = drawbuf->srcblk.height; ++ ++ GE_WriteReg(GE_REG_STBB_WIDTH, u32Width); ++ GE_WriteReg(GE_REG_STBB_HEIGHT,u32Height); ++ ++ // Set source coordinate ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x); ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y); ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_X_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x + drawbuf->srcblk.width - 1); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_Y_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y + drawbuf->srcblk.height - 1); ++ } ++ ++ if(drawflag&GEDRAW_FLAG_DUPLICAPE) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ else ++ { ++ _u32Reg60hFlag &= ~GE_VAL_STBB_PATCH; ++ } ++ ++ if(drawflag&GEDRAW_FLAG_SCALE) ++ { ++ u32Value = Divide2Fixed(u32Width, drawbuf->dstblk.width, 1, 12);//<< 2 ; //sc ++ GE_WriteReg(GE_REG_STBB_DX, u32Value & 0xffff); ++ u32Value = Divide2Fixed((u32Width - drawbuf->dstblk.width), 2* drawbuf->dstblk.width, 1, 12);// << 2; //sc ++ GE_WriteReg(GE_REG_STBB_INIT_DX, u32Value); ++ ++ u32Value = Divide2Fixed(u32Height, drawbuf->dstblk.height, 1, 12);// << 2 ; //sc ++ GE_WriteReg(GE_REG_STBB_DY, u32Value & 0xffff); ++ u32Value = Divide2Fixed((u32Height - drawbuf->dstblk.height), 2* drawbuf->dstblk.height, 0, 12);// << 2; //sc ++ GE_WriteReg(GE_REG_STBB_INIT_DY, u32Value); ++ ++ //scale = (U16)((float)(u32Width-1) * ((float)pbmpfmt->width / (float)u32Width));//TODO ++// u32Scale = (((U32)drawbuf->dstblk.width << 5) / u32Width * (u32Width-1)) >> 5; //sc ++// u32Width = u32Scale; //pbmpfmt->width; ++ u32Width = drawbuf->dstblk.width; ++ ++ //scale = (U16)((float)(u32Height-1) * ((float)pbmpfmt->height / (float)u32Height));//TODO ++// u32Scale = (((U32)drawbuf->dstblk.height << 5) / u32Height * (u32Height-1)) >> 5; //sc ++// u32Height = u32Scale; //pbmpfmt->height; ++ u32Height = drawbuf->dstblk.height; ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Width = drawbuf->dstblk.width; ++ u32Height = drawbuf->dstblk.height; ++ GE_WriteReg(GE_REG_STBB_DX, 0x1000); ++ GE_WriteReg(GE_REG_STBB_DY, 0x1000); ++ GE_WriteReg(GE_REG_STBB_INIT_DX, 0); ++ GE_WriteReg(GE_REG_STBB_INIT_DY, 0); ++ if ((drawbuf->dstblk.width != drawbuf->srcblk.width) || ++ (drawbuf->dstblk.height != drawbuf->srcblk.height)) ++ { ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ } ++ } ++ ++ GE_WriteReg(GE_REG_FMT_BLT, u32Value2); ++ ++ if (u32Value2 & GE_VAL_EN_STRETCH_BITBLT) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ ++ //------------------------------------------------------------ ++ // Destination coordinate ++ //------------------------------------------------------------ ++ GE_WriteReg(GE_REG_PRI_V0_X, drawbuf->dstblk.x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, drawbuf->dstblk.y); ++ GE_WriteReg(GE_REG_PRI_V1_X, drawbuf->dstblk.x + u32Width - 1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, drawbuf->dstblk.y + u32Height - 1); ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ GE_WriteReg(GE_REG_CMD, (GE_VAL_PRIM_BITBLT|_u32Reg60hFlag)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++GESTATUS MHal_GE_BitBltEx(GE_DRAW_RECT * drawbuf, U32 drawflag, GE_SCALE_INFO * ScaleInfo) ++{ ++ U32 u32Width, u32Height; ++ U32 u32Value2; ++ ++ GE_DEBUGINFO( printk( "MHal_GE_BitBltEx\n" ) ); ++ if (!GE_CheckInClipWindow(drawbuf->dstblk.x, drawbuf->dstblk.y, ++ drawbuf->dstblk.x+drawbuf->dstblk.width-1, ++ drawbuf->dstblk.y+drawbuf->dstblk.height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ GE_WaitAvailableCMDQueue(20); ++ ++ u32Value2 = GE_ReadReg(GE_REG_FMT_BLT); ++ ++ u32Width = drawbuf->srcblk.width; ++ u32Height = drawbuf->srcblk.height; ++ ++ GE_WriteReg(GE_REG_STBB_WIDTH, u32Width); ++ GE_WriteReg(GE_REG_STBB_HEIGHT,u32Height); ++ ++ // Set source coordinate ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x); ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y); ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_X_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_X, drawbuf->srcblk.x + drawbuf->srcblk.width - 1); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_Y_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_Y, drawbuf->srcblk.y + drawbuf->srcblk.height - 1); ++ } ++ ++ if(drawflag&GEDRAW_FLAG_DUPLICAPE) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ else ++ { ++ _u32Reg60hFlag &= ~GE_VAL_STBB_PATCH; ++ } ++ ++ if(drawflag&GEDRAW_FLAG_SCALE) ++ { ++ GE_WriteReg(GE_REG_STBB_DX, (ScaleInfo->u32DeltaX & 0xffff)); ++ GE_WriteReg(GE_REG_STBB_INIT_DX, (ScaleInfo->u32InitDelatX & 0xffff)); ++ GE_WriteReg(GE_REG_STBB_DY, (ScaleInfo->u32DeltaY & 0xffff)); ++ GE_WriteReg(GE_REG_STBB_INIT_DY, (ScaleInfo->u32InitDelatY & 0xffff)); ++ ++ u32Width = drawbuf->dstblk.width; ++ u32Height = drawbuf->dstblk.height; ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Width = drawbuf->dstblk.width; ++ u32Height = drawbuf->dstblk.height; ++ GE_WriteReg(GE_REG_STBB_DX, 0x1000); ++ GE_WriteReg(GE_REG_STBB_DY, 0x1000); ++ GE_WriteReg(GE_REG_STBB_INIT_DX, 0); ++ GE_WriteReg(GE_REG_STBB_INIT_DY, 0); ++ if ((drawbuf->dstblk.width != drawbuf->srcblk.width) || ++ (drawbuf->dstblk.height != drawbuf->srcblk.height)) ++ { ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ } ++ else ++ { ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ } ++ } ++ ++ GE_WriteReg(GE_REG_FMT_BLT, u32Value2); ++ ++ if (u32Value2 & GE_VAL_EN_STRETCH_BITBLT) ++ { ++ _u32Reg60hFlag |= GE_VAL_STBB_PATCH; ++ } ++ ++ //------------------------------------------------------------ ++ // Destination coordinate ++ //------------------------------------------------------------ ++ GE_WriteReg(GE_REG_PRI_V0_X, drawbuf->dstblk.x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, drawbuf->dstblk.y); ++ GE_WriteReg(GE_REG_PRI_V1_X, drawbuf->dstblk.x + u32Width - 1); ++ GE_WriteReg(GE_REG_PRI_V1_Y, drawbuf->dstblk.y + u32Height - 1); ++ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ GE_WriteReg(GE_REG_CMD, (GE_VAL_PRIM_BITBLT|_u32Reg60hFlag)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++GESTATUS MHal_GE_GetScaleBltInfo(GE_DRAW_RECT* pdrawbuf, GE_BLOCK* pSrcBlk, GE_BLOCK* pDstBlk, GE_SCALE_INFO * pScaleInfo) ++{ ++ U32 u32InitDx, u32InitDy; ++ U32 u32Temp; ++ //U32 u32Temp1; ++ U32 u32InverseDeltaX; ++ U32 u32InverseDeltaY; ++ U16 bXStartMinus_1 = FALSE; ++ U16 bYStartMinus_1 = FALSE; ++ U32 u32Temp2, u32Temp3; ++ ++ if (pdrawbuf->srcblk.width == pdrawbuf->dstblk.width) ++ { ++ pDstBlk->x = pSrcBlk->x; ++ pDstBlk->width = pSrcBlk->width; ++ pScaleInfo->u32DeltaX = 0x1000; ++ pScaleInfo->u32InitDelatX = 0; ++ } ++ else ++ { ++ pScaleInfo->u32DeltaX = Divide2Fixed(pdrawbuf->srcblk.width, pdrawbuf->dstblk.width, 1, 12);//<< 2 ; //sc ++ u32InverseDeltaX = Divide2Fixed(pdrawbuf->dstblk.width, pdrawbuf->srcblk.width, 1, 12);//<< 2 ; //sc ++ u32InitDx = Divide2Fixed((pdrawbuf->srcblk.width -pdrawbuf->dstblk.width), 2*pdrawbuf->dstblk.width,0, 12);// << 2; //sc ++ ++ if (pdrawbuf->srcblk.width > pdrawbuf->dstblk.width) ++ { ++ //Horizontal down scaling ++ //Get destination x ++ if (pSrcBlk->x == 0) ++ { ++ pDstBlk->x = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->x<<12) - (u32InitDx & 0xfff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = ((((pSrcBlk->x<<12) - (u32InitDx & 0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = (((pSrcBlk->x<<12) - (u32Temp2*pScaleInfo->u32DeltaX + u32InitDx))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) > u32InverseDeltaX) ++ { ++ pDstBlk->x = ((u32Temp & 0xfffff000)>>12)+1; ++ bXStartMinus_1 = FALSE; ++ } ++ else ++ { ++ pDstBlk->x = ((u32Temp & 0xfffff000)>>12); ++ bXStartMinus_1 = TRUE; ++ } ++ } ++ ++ //Get Destination width ++ //u32Temp = ((((pSrcBlk->x+pSrcBlk->width)<<12) - (u32InitDx & 0x1fff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = (((((pSrcBlk->x+pSrcBlk->width)<<12) - (u32InitDx & 0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = ((((pSrcBlk->x+pSrcBlk->width)<<12) - (u32Temp2*pScaleInfo->u32DeltaX + u32InitDx))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) < u32InverseDeltaX) ++ { ++ pSrcBlk->width++; ++ } ++ pDstBlk->width = ((u32Temp & 0xfffff000)>>12) - pDstBlk->x + 1; ++ ++ ++ //Get x initial delta. ++ if (bXStartMinus_1) ++ { ++ pSrcBlk->x--; ++ pSrcBlk->width++; ++ } ++ u32Temp = pDstBlk->x *pScaleInfo->u32DeltaX + u32InitDx; ++ //u32Temp = ((pDstBlk->x<<12)*pdrawbuf->srcblk.width)/pdrawbuf->dstblk.width + u32InitDx; ++ } ++ else ++ { ++ //Horizontal up scaling ++ //Get destination x ++ if (pSrcBlk->x == 0) ++ { ++ pDstBlk->x = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->x<<12) - ((~u32InitDx+1)&0xfff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = ((((pSrcBlk->x<<12) + ((~u32InitDx+1)&0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = ((((pSrcBlk->x<<12) - (u32Temp2*pScaleInfo->u32DeltaX - ((~u32InitDx+1)&0xfff))))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->x = (((u32Temp-u32InverseDeltaX)&0xfffff000)>>12)+1; ++ bXStartMinus_1 = TRUE; ++ } ++ ++ //Get Destination width ++ //u32Temp = ((((pSrcBlk->x + pSrcBlk->width)<<12) + ((~u32InitDx+1) & 0x1fff))*pdrawbuf->dstblk.width)/pdrawbuf->srcblk.width; ++ u32Temp2 = (((((pSrcBlk->x + pSrcBlk->width)<<12) + ((~u32InitDx+1)&0xfff))<<8)/pScaleInfo->u32DeltaX)>>8; ++ u32Temp3 = (((((pSrcBlk->x + pSrcBlk->width)<<12) - (u32Temp2*pScaleInfo->u32DeltaX - ((~u32InitDx+1)&0xfff))))<<12)/pScaleInfo->u32DeltaX; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->width = ((u32Temp & 0xfffff000)>>12) - pDstBlk->x + 1; ++ pSrcBlk->width++; ++ ++ ++ //Get x initial delta. ++ if (bXStartMinus_1) ++ { ++ pSrcBlk->x--; ++ pSrcBlk->width++; ++ } ++ u32Temp = pDstBlk->x *pScaleInfo->u32DeltaX - ((~u32InitDx+1)&0xfff); ++ //u32Temp = ((pDstBlk->x<<12)*pdrawbuf->srcblk.width)/pdrawbuf->dstblk.width - ((~u32InitDx+1)&0xfff); ++ } ++ ++ if (pDstBlk->x == 0) ++ { ++ pScaleInfo->u32InitDelatX = u32InitDx; ++ } ++ else ++ { ++ if (u32Temp > (pSrcBlk->x<<12)) ++ { ++ if ((u32Temp - (pSrcBlk->x<<12)) < 0x1000) ++ { ++ pScaleInfo->u32InitDelatX = (u32Temp- (pSrcBlk->x<<12)); ++ } ++ else ++ { ++ //Invalid destination X position. ++ //printk("+ ,Invalid destination X position.\n"); ++ pScaleInfo->u32InitDelatX = 0xfff; ++ } ++ } ++ else ++ { ++ //printk("- ,Invalid destination X direction.\n"); ++ pScaleInfo->u32InitDelatX = 0; ++ } ++ } ++ } ++ ++ if (pdrawbuf->srcblk.height == pdrawbuf->dstblk.height) ++ { ++ pDstBlk->y = pSrcBlk->y; ++ pDstBlk->height = pSrcBlk->height; ++ pScaleInfo->u32DeltaY = 0x1000; ++ pScaleInfo->u32InitDelatY = 0; ++ } ++ else ++ { ++ pScaleInfo->u32DeltaY = Divide2Fixed(pdrawbuf->srcblk.height, pdrawbuf->dstblk.height, 1, 12);// << 2 ; //sc ++ u32InverseDeltaY = Divide2Fixed(pdrawbuf->dstblk.height, pdrawbuf->srcblk.height, 1, 12);// << 2 ; //sc ++ u32InitDy = Divide2Fixed((pdrawbuf->srcblk.height - pdrawbuf->dstblk.height), 2*pdrawbuf->dstblk.height, 0, 12);// << 2; //sc ++ ++ ++ if (pdrawbuf->srcblk.height > pdrawbuf->dstblk.height) ++ { ++ //Vertical down scaling ++ //Get destination y ++ if (pSrcBlk->y == 0) ++ { ++ pDstBlk->y = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->y<<12) - (u32InitDy & 0xfff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = ((((pSrcBlk->y<<12) - (u32InitDy & 0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = (((pSrcBlk->y<<12) - (u32Temp2*pScaleInfo->u32DeltaY + u32InitDy))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) > u32InverseDeltaY) ++ { ++ pDstBlk->y = ((u32Temp & 0xfffff000)>>12)+1; ++ bYStartMinus_1 = FALSE; ++ } ++ else ++ { ++ pDstBlk->y = ((u32Temp & 0xfffff000)>>12); ++ bYStartMinus_1 = TRUE; ++ } ++ } ++ ++ //Get Destination height ++ //u32Temp = ((((pSrcBlk->y+pSrcBlk->height)<<12) - (u32InitDy & 0x1fff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = (((((pSrcBlk->y+pSrcBlk->height)<<12) - (u32InitDy & 0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = ((((pSrcBlk->y+pSrcBlk->height)<<12) - (u32Temp2*pScaleInfo->u32DeltaY + u32InitDy))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ if ((u32Temp & 0xfff) < u32InverseDeltaY) ++ { ++ pSrcBlk->height++; ++ } ++ pDstBlk->height = ((u32Temp & 0xfffff000)>>12) - pDstBlk->y + 1; ++ ++ //Get x initial delta. ++ if (bYStartMinus_1) ++ { ++ pSrcBlk->y--; ++ pSrcBlk->height++; ++ } ++ u32Temp = pDstBlk->y*pScaleInfo->u32DeltaY + u32InitDy; ++ //u32Temp = ((pDstBlk->y<<12)*pdrawbuf->srcblk.height)/pdrawbuf->dstblk.height + u32InitDy; ++ } ++ else ++ { ++ //Vertical up scaling ++ //Get destination y ++ if (pSrcBlk->y == 0) ++ { ++ pDstBlk->y = 0; ++ } ++ else ++ { ++ //u32Temp = (((pSrcBlk->y<<12) + ((~u32InitDy+1)&0xfff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = ((((pSrcBlk->y<<12) + ((~u32InitDy+1)&0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = ((((pSrcBlk->y<<12) - (u32Temp2*pScaleInfo->u32DeltaY - ((~u32InitDy+1)&0xfff))))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->y = (((u32Temp-u32InverseDeltaY)&0xfffff000)>>12)+1; ++ bYStartMinus_1 = TRUE; ++ } ++ ++ //Get Destination height ++ //u32Temp = ((((pSrcBlk->y + pSrcBlk->height)<<12) + ((~u32InitDy+1) & 0x1fff))*pdrawbuf->dstblk.height)/pdrawbuf->srcblk.height; ++ u32Temp2 = (((((pSrcBlk->y + pSrcBlk->height)<<12) + ((~u32InitDy+1)&0xfff))<<8)/pScaleInfo->u32DeltaY)>>8; ++ u32Temp3 = (((((pSrcBlk->y + pSrcBlk->height)<<12) - (u32Temp2*pScaleInfo->u32DeltaY - ((~u32InitDy+1)&0xfff))))<<12)/pScaleInfo->u32DeltaY; ++ u32Temp = ((u32Temp2<<12)|(u32Temp3&0xfff)); ++ pDstBlk->height = ((u32Temp & 0xfffff000)>>12) - pDstBlk->y + 1; ++ pSrcBlk->height++; ++ ++ //Get x initial delta. ++ if (bYStartMinus_1) ++ { ++ pSrcBlk->y--; ++ pSrcBlk->height++; ++ } ++ u32Temp = pDstBlk->y*pScaleInfo->u32DeltaY- ((~u32InitDy+1)&0xfff); ++ //u32Temp = ((pDstBlk->y<<12)*pdrawbuf->srcblk.height)/pdrawbuf->dstblk.height - ((~u32InitDy+1)&0xfff); ++ } ++ ++ if (pDstBlk->y == 0) ++ { ++ pScaleInfo->u32InitDelatY = u32InitDy; ++ } ++ else ++ { ++ if (u32Temp > (pSrcBlk->y<<12)) ++ { ++ if ((u32Temp - (pSrcBlk->y<<12)) < 0x1000) ++ { ++ pScaleInfo->u32InitDelatY = (u32Temp- (pSrcBlk->y<<12)); ++ } ++ else ++ { ++ //Invalid destination Y position. ++ //printk("+ ,Invalid destination Y position.\n"); ++ pScaleInfo->u32InitDelatY = 0xfff; ++ } ++ } ++ else ++ { ++ //printk("- ,Invalid destination Y direction.\n"); ++ pScaleInfo->u32InitDelatY = 0; ++ } ++ } ++ } ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE Screen to Screen bitblt ++/// @param psrcblk \b IN: pointer of source block ++/// @param pdstblk \b IN: pointer of destination block ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_ScreenCopy(GE_BLOCK *psrcblk, GE_BLOCK *pdstblk) ++{ ++ //U32 u32Addr; ++ U32 u32Scale, u32Value, u32Value2, u32Value3; ++ ++ GE_DEBUGINFO( printk( "MHal_GE_ScreenCopy\n" ) ); ++ ++ GE_WaitAvailableCMDQueue(25); ++ ++ if (!GE_CheckInClipWindow(pdstblk->x, pdstblk->y, ++ pdstblk->x+pdstblk->width-1, pdstblk->y+pdstblk->height-1)) ++ { ++ return GESTATUS_FAIL; ++ } ++ ++ //u32Value = GE_ReadReg(GE_REG_EN); ++ //u32Value |= GE_VAL_EN_PE; ++ //GE_WriteReg(GE_REG_EN, u32Value); ++ ++ u32Value2 = GE_ReadReg(GE_REG_FMT_BLT); ++ ++ GE_WriteReg(GE_REG_STBB_WIDTH, psrcblk->width); ++ GE_WriteReg(GE_REG_STBB_HEIGHT, psrcblk->height); ++ ++ // Set stretch delta ++ if(psrcblk->width != pdstblk->width) ++ { ++ u32Value = Divide2Fixed(psrcblk->width, pdstblk->width, 1, 12);// << 2; //sc ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ u32Value3 = Divide2Fixed((psrcblk->width - pdstblk->width), 2* pdstblk->width, 1, 12);// << 2; //sc ++ } ++ else ++ { ++ u32Value = 0x1000; ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ u32Value3 = 0; ++ } ++ GE_WriteReg(GE_REG_STBB_DX, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_STBB_INIT_DX,u32Value3); ++ ++ if(psrcblk->height != pdstblk->height) ++ { ++ u32Value = (U16)Divide2Fixed(psrcblk->height, pdstblk->height, 1, 12);//<<2; //sc ++ u32Value2 |= GE_VAL_EN_STRETCH_BITBLT; ++ u32Value3 = Divide2Fixed((psrcblk->height - pdstblk->height), 2* pdstblk->height, 1, 12);// << 2; //sc ++ } ++ else ++ { ++ u32Value = 0x1000; ++ u32Value2 &= ~GE_VAL_EN_STRETCH_BITBLT; ++ } ++ GE_WriteReg(GE_REG_STBB_DY, u32Value & 0xffff); ++ GE_WriteReg(GE_REG_STBB_INIT_DY,u32Value3); ++ ++ GE_WriteReg(GE_REG_FMT_BLT, u32Value2); ++ ++ // Source coordinate ++ GE_WriteReg(GE_REG_PRI_V2_X, psrcblk->x); ++ GE_WriteReg(GE_REG_PRI_V2_Y, psrcblk->y); ++ ++ if ((psrcblk->x <= pdstblk->x) && (pdstblk->x <= (psrcblk->x + psrcblk->width)) && ++ (psrcblk->y <= pdstblk->y) && (pdstblk->y <= (psrcblk->y + psrcblk->height))) ++ { ++ _u32Reg60hFlag |= (GE_VAL_DRAW_DST_DIR_X_NEG | GE_VAL_DRAW_DST_DIR_Y_NEG | GE_VAL_DRAW_SRC_DIR_X_NEG | GE_VAL_DRAW_SRC_DIR_Y_NEG); ++ } ++ if ((psrcblk->x <= (pdstblk->x + pdstblk->width)) && ((pdstblk->x + pdstblk->width) <= (psrcblk->x + psrcblk->width)) && ++ (psrcblk->y <= pdstblk->y) && (pdstblk->y <= (psrcblk->y + psrcblk->height))) ++ { ++ _u32Reg60hFlag |= (GE_VAL_DRAW_DST_DIR_Y_NEG | GE_VAL_DRAW_SRC_DIR_Y_NEG); ++ } ++ ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_X_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_X, psrcblk->x + psrcblk->width - 1); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_SRC_DIR_Y_NEG) ++ { ++ GE_WriteReg(GE_REG_PRI_V2_Y, psrcblk->y + psrcblk->height - 1); ++ } ++ ++ ++ // Set source pitch buffer information with destination buffer. ++ GE_WriteReg(GE_REG_SB_PIT, GE_ReadReg(GE_REG_DB_PIT)); ++ GE_WriteReg(GE_REG_SB_BASE0, GE_ReadReg(GE_REG_DB_BASE0)); ++ GE_WriteReg(GE_REG_SB_BASE1, GE_ReadReg(GE_REG_DB_BASE1)); ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ u32Value2 = (u32Value & GE_MSK_DB_FMT) | ((u32Value & GE_MSK_DB_FMT)>>8); ++ GE_WriteReg(GE_REG_SB_DB_MODE, u32Value2); ++ ++ ++ // Destination coordinate ++ if (_u32Reg60hFlag & GE_VAL_DRAW_DST_DIR_X_NEG) ++ { ++ u32Scale = (((U32)pdstblk->width << 5) / psrcblk->width * (psrcblk->width-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V0_X, pdstblk->x + u32Scale); ++ GE_WriteReg(GE_REG_PRI_V1_X, pdstblk->x); ++ } ++ else ++ { ++ GE_WriteReg(GE_REG_PRI_V0_X, pdstblk->x); ++ u32Scale = (((U32)pdstblk->width << 5) / psrcblk->width * (psrcblk->width-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_X, pdstblk->x + u32Scale); ++ } ++ ++ if (_u32Reg60hFlag & GE_VAL_DRAW_DST_DIR_Y_NEG) ++ { ++ u32Scale = (((U32)pdstblk->height << 5) / psrcblk->height * (psrcblk->height-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V0_Y, pdstblk->y + u32Scale); ++ GE_WriteReg(GE_REG_PRI_V1_Y, pdstblk->y); ++ } ++ else ++ { ++ GE_WriteReg(GE_REG_PRI_V0_Y, pdstblk->y); ++ u32Scale = (((U32)pdstblk->height << 5) / psrcblk->height * (psrcblk->height-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_Y, pdstblk->y + u32Scale); ++ } ++/* ++ GE_WriteReg(GE_REG_PRI_V0_X, pdstblk->x); ++ GE_WriteReg(GE_REG_PRI_V0_Y, pdstblk->y); ++ u32Scale = (((U32)pdstblk->width << 5) / psrcblk->width * (psrcblk->width-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_X, pdstblk->x + u32Scale); ++ u32Scale = (((U32)pdstblk->height << 5) / psrcblk->height * (psrcblk->height-1)) >> 5; //sc ++ GE_WriteReg(GE_REG_PRI_V1_Y, pdstblk->y + u32Scale); ++*/ ++ // @FIXME ++ // check GE_REG_SB_DB_MODE ++ ++ u32Value = GE_VAL_PRIM_BITBLT; ++ ++ GE_WriteReg(GE_REG_CMD, u32Value|_u32Reg60hFlag); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE clipping window ++/// @param v0 \b IN: left-top position ++/// @param v1 \b IN: right-down position ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetClip(GE_POINT_t* v0, GE_POINT_t* v1) ++{ ++ GE_WaitAvailableCMDQueue(8); ++ GE_WriteReg(GE_REG_CLIP_LEFT, v0->x); ++ GE_WriteReg(GE_REG_CLIP_TOP, v0->y); ++ //GE_WriteReg(GE_REG_CLIP_RIGHT, v1->x - 1); ++ //GE_WriteReg(GE_REG_CLIP_BOTTOM, v1->y - 1); ++ GE_WriteReg(GE_REG_CLIP_RIGHT, v1->x); ++ GE_WriteReg(GE_REG_CLIP_BOTTOM, v1->y); ++ _u16PeClipX1 = v0->x; ++ _u16PeClipY1 = v0->y; ++ _u16PeClipX2 = v1->x; ++ _u16PeClipY2 = v1->y; ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE rotate ++/// @param angle \b IN: rotate angle ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @note ++/// The rotate process can't perform with italic process. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetRotate(GEROTATE_ANGLE angle) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++ u32Value = GE_ReadReg(GE_REG_ROT_MIRROR); ++ u32Value &= ~GE_MSK_ROT; ++ u32Value |= (U32)angle; ++ GE_WriteReg(GE_REG_ROT_MIRROR, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE alpha source ++/// @param eMode \b IN: alpha source come from , this indicate alpha channel output source ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetAlphaSrcFrom( GE_ALPHA_SRC_FROM eMode ) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++ u32Value = GE_ReadReg(GE_REG_DB_ABL); ++ ++ u32Value = ((u32Value & (~GE_MSK_DB_ABL))| (eMode<<8)); ++ GE_WriteReg(GE_REG_DB_ABL, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Description: ++// Arguments: eMode : ABL_FROM_CONST, ABL_FROM_ASRC, ABL_FROM_ADST ++// blendcoef : COEF_ONE, COEF_CONST, COEF_ASRC, COEF_ADST ++// COEF_ZERO, COEF_1_CONST, COEF_1_ASRC, COEF_1_ADST ++// blendfactor : value : [0,0xff] ++// Return: NONE ++// ++// Notes: if any ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++/// Set PE alpha blending. Dst = A * Src + (1 - A) Dst ++/// @param blendcoef \b IN: alpha source from ++/// @param u8ConstantAlpha \b IN: Contant alpha when blendcoef is equal to COEF_CONST ++/// or COEF_1_CONST. ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetAlphaBlending(GE_BLEND_COEF blendcoef, U8 u8ConstantAlpha) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(5); ++ ++ u32Value = GE_ReadReg(GE_REG_ABL_COEF); ++ u32Value &= ~(GE_MSK_ABL_COEF); ++ u32Value |= blendcoef ; ++ GE_WriteReg(GE_REG_ABL_COEF, u32Value); ++ ++ GE_WriteReg(GE_REG_ABL_CONST, (U32)(u8ConstantAlpha&0xff)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable PE alpha blending ++/// @param enable \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_EnableAlphaBlending(U16 enable) ++{ ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(4); ++ ++#if PATCH_RD_CMD ++ u32Value = _u32Reg0hValue; ++#else ++ u32Value = GE_ReadReg(GE_REG_EN); ++#endif ++ ++ if(enable) ++ { ++ u32Value |= GE_VAL_EN_GY_ABL; ++ GE_WriteReg(GE_REG_EN, u32Value); ++ } ++ else ++ { ++ u32Value &= ~GE_VAL_EN_GY_ABL; ++ GE_WriteReg(GE_REG_EN, u32Value); ++ } ++ ++#if PATCH_RD_CMD ++ _u32Reg0hValue = u32Value; ++#endif ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable PE mirror ++/// @param isMirrorX \b IN: true/false ++/// @param isMirrorY \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @note ++/// The mirror process can't perform on the source format is GE_FMT_I1, GE_FMT_I2 or GE_FMT_I4. ++/// The mirror process can't perform with italic process. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetMirror(U16 isMirrorX, U16 isMirrorY) ++{ ++ _u32Reg60hFlag = (_u32Reg60hFlag & ~(GE_VAL_DRAW_SRC_DIR_X_NEG|GE_VAL_DRAW_SRC_DIR_Y_NEG)); ++ _u32Reg60hFlag |= ( (isMirrorX << 7) | (isMirrorY << 8) ); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable PE NearestMode ++/// @param enable \b IN: true/false ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetNearestMode(U16 enable) ++{ ++ _u32Reg60hFlag = (_u32Reg60hFlag & ~(GE_VAL_STBB_NEAREST)); ++ _u32Reg60hFlag |= (enable << 14); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE source buffer info ++/// @param bufInfo \b IN: buffer handle ++/// @param offsetofByte \b IN: start offset (should be 128 bit aligned) ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @return GESTATUS_NON_ALIGN_PITCH - The pitch is not 16 bytes alignment ++/// @return GESTATUS_NON_ALIGN_ADDRESS - The address is not 16 bytes alignment ++/// @note ++/// The buffer start address must be 128 bits alignment. ++/// In GE_FMT_I1, GE_FMT_I2 and GE_FMT_I4 format, the pitch must be 8 bits alignment. ++/// In other format, the pitch must be 128 bits alignment. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetSrcBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte) ++{ ++ U32 u32Value , u32Addr; ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++ _GE_CHECK_BUFFER_ALIGN1( ++ bufInfo->u32Addr + offsetofByte, ++ bufInfo->u32Width, ++ bufInfo->u32Height, ++ bufInfo->u32Pitch, ++ bufInfo->u32ColorFmt); ++ ++ if ((bufInfo->u32Addr + offsetofByte)%16) ++ { ++ printk(KERN_WARNING "GESTATUS_NON_ALIGN_ADDRESS(%d)\n", __LINE__); ++ return GESTATUS_NON_ALIGN_ADDRESS; ++ } ++ ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ u32Value = (u32Value & ~GE_MSK_SB_FMT) | (bufInfo->u32ColorFmt); // one-bit format ++ GE_WriteReg(GE_REG_SB_DB_MODE, u32Value); ++ ++ ++ // Set source address ++ u32Addr = (bufInfo->u32Addr + offsetofByte); ++ GE_WriteReg(GE_REG_SB_BASE0, u32Addr & 0xffff); ++ GE_WriteReg(GE_REG_SB_BASE1, u32Addr >> 16); ++ ++ // Set source pitch ++ GE_WriteReg(GE_REG_SB_PIT, (bufInfo->u32Pitch)); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set PE destination buffer info ++/// @param bufInfo \b IN: buffer handle ++/// @param offsetofByte \b IN: start offset (should be 128 bit aligned) ++/// @return GESTATUS_SUCCESS - Success ++/// @return GESTATUS_FAIL - Failure ++/// @return GESTATUS_NON_ALIGN_PITCH - The pitch is not 16 bytes alignment ++/// @return GESTATUS_NON_ALIGN_ADDRESS - The address is not 16 bytes alignment ++/// @note ++/// The buffer start address and pitch smust be 128 bits alignment. ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_SetDstBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte) ++{ ++ U32 u32Value; ++ U32 u32Addr = (bufInfo->u32Addr + offsetofByte ); ++ ++ GE_WaitAvailableCMDQueue(8); ++ ++ _GE_CHECK_BUFFER_ALIGN1( ++ bufInfo->u32Addr + offsetofByte, ++ bufInfo->u32Width, ++ bufInfo->u32Height, ++ bufInfo->u32Pitch, ++ bufInfo->u32ColorFmt); ++ ++ if (u32Addr%16) ++ { ++ printk(KERN_WARNING "GESTATUS_NON_ALIGN_ADDRESS(%d)\n", __LINE__); ++ return GESTATUS_NON_ALIGN_ADDRESS; ++ } ++ ++ // Destination Buffer ++ GE_WriteReg(GE_REG_DB_PIT, bufInfo->u32Pitch); // Pitch ++ GE_WriteReg(GE_REG_DB_BASE0, u32Addr & 0xffff); // Address ++ GE_WriteReg(GE_REG_DB_BASE1, u32Addr >> 16); // Address ++ ++ if( GE_FMT_ARGB1555==bufInfo->u32ColorFmt ) ++ bufInfo->u32ColorFmt = GE_FMT_ARGB1555_DST; ++ ++ // Destination frame buffer format ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ u32Value = (u32Value & ~GE_MSK_DB_FMT) | (bufInfo->u32ColorFmt<<8); // one-bit format ++ GE_WriteReg(GE_REG_SB_DB_MODE, u32Value); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_GetFrameBufferInfo(U32 *width, ++ U32 *height, ++ U32 *pitch, ++ U32 *fbFmt, ++ U32 *addr) ++{ ++ // TODO: width & height have not been retrieved ++ U32 u32Value; ++ ++ GE_WaitAvailableCMDQueue(31); ++ ++ u32Value = GE_ReadReg(GE_REG_DB_PIT); ++ *pitch = u32Value; ++ ++ u32Value = GE_ReadReg(GE_REG_SB_DB_MODE); ++ *fbFmt = ((u32Value & GE_MSK_DB_FMT)>>8); ++ ++ u32Value = GE_ReadReg(GE_REG_DB_BASE0); ++ *addr = u32Value; ++ u32Value = GE_ReadReg(GE_REG_DB_BASE1); ++ *addr |= (u32Value << 16); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_YUV_Set(GE_YUV_INFO* pYuvInfo) ++{ ++ U32 u32YuvInfo= 0; ++ ++ GE_ASSERT(pYuvInfo, printk("[GE DRV][%06d] NULL pointer\n", __LINE__)); ++ ++ // if (bEnable){ ++ u32YuvInfo|= (pYuvInfo->rgb2yuv_mode)? GE_VAL_RGB2YUV_255: GE_VAL_RGB2YUV_PC; ++ u32YuvInfo|= (pYuvInfo->yuv_range_out)? GE_VAL_YUV_RANGE_OUT_PC: GE_VAL_YUV_RANGE_OUT_255; ++ u32YuvInfo|= (pYuvInfo->yuv_range_in)? GE_VAL_YUV_RANGE_IN_127: GE_VAL_YUV_RANGE_IN_255; ++ u32YuvInfo|= ((pYuvInfo->yuv_mem_fmt_src & 0x3)<< GE_SHFT_YUV_MEM_FMT_SRC); ++ u32YuvInfo|= ((pYuvInfo->yuv_mem_fmt_dst & 0x3)<< GE_SHFT_YUV_MEM_FMT_DST); ++ // } ++ ++ GE_WriteReg(GE_REG_YUV, u32YuvInfo); ++ ++ return GESTATUS_SUCCESS; ++} ++ ++GESTATUS MHal_GE_YUV_Get(GE_YUV_INFO* pYuvInfo) ++{ ++ U32 u32YuvInfo; ++ ++ GE_ASSERT(pYuvInfo, printk("[GE DRV][%06d] NULL pointer\n", __LINE__)); ++ u32YuvInfo= GE_ReadReg(GE_REG_YUV); ++ pYuvInfo->rgb2yuv_mode= (u32YuvInfo & GE_VAL_RGB2YUV_255)? GE_RGB2YUV_255_MODE: GE_RGB2YUV_PC_MODE; ++ pYuvInfo->yuv_range_out= (u32YuvInfo & GE_VAL_YUV_RANGE_OUT_PC)? GE_YUV_RANGE_OUT_PC: GE_YUV_RANGE_OUT_255; ++ pYuvInfo->yuv_range_in= (u32YuvInfo & GE_VAL_YUV_RANGE_IN_127)? GE_YUV_RANGE_IN_127: GE_YUV_RANGE_IN_255; ++ pYuvInfo->yuv_mem_fmt_src= (u32YuvInfo & GE_MASK_YUV_MEM_FMT_SRC) >> GE_SHFT_YUV_MEM_FMT_SRC; ++ pYuvInfo->yuv_mem_fmt_dst= (u32YuvInfo & GE_MASK_YUV_MEM_FMT_DST) >> GE_SHFT_YUV_MEM_FMT_DST; ++ return GESTATUS_SUCCESS; ++} ++ ++//------------------------------------------------------------------------------------------------- ++void GE_ConvertRGB2DBFmt(GE_Buffer_Format Fmt, U32 *colorinfo, U16* low, U16* high) ++{ ++ GE_RGB_COLOR *color = NULL; ++ GE_BLINK_DATA *blinkData = NULL; ++ //U8 a, r, g, b; ++ ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ if (GE_FMT_1ABFGBG12355== Fmt) ++ // if (Fmt == GE_FMT_1BAAFGBG123433) ++ { ++ blinkData =(GE_BLINK_DATA *)colorinfo; ++ } ++ else ++ { ++ color =(GE_RGB_COLOR *)colorinfo; ++ } ++ ++ switch (Fmt) ++ { ++ case GE_FMT_RGB565 : ++ *low = ((color->b & 0xf8) + (color->b >> 5)) | (((color->g & 0xfc) + (color->g>>6))<<8); ++ *high = ((color->r & 0xf8) + (color->r >> 5)) | ((color->a & 0xff) << 8); ++ break; ++ case GE_FMT_ARGB1555 : ++ *low = ((color->b & 0xf8) + (color->b >> 5)) | (((color->g & 0xf8) + (color->g >> 5))<<8); ++ if (color->a > 0) ++ { ++ *high = ((color->r & 0xf8) + (color->r >> 5)) | (0xff << 8); ++ } ++ else ++ { ++ *high = ((color->r & 0xf8) + (color->r >> 5)); ++ } ++ break; ++ case GE_FMT_ARGB4444 : ++ *low = ((color->b & 0xf0) + (color->b >> 4)) | (((color->g & 0xf0) + (color->g >> 4))<<8); ++ *high = ((color->r & 0xf0) + (color->r >> 4)) | (((color->a & 0xf0) + (color->a >> 4))<<8); ++ break; ++ case GE_FMT_ARGB8888 : ++ *low =(color->b & 0xff) | ((color->g & 0xff) << 8); ++ *high =(color->r & 0xff) | ((color->a & 0xff) << 8); ++ break; ++ case GE_FMT_I8 : ++ *low = (color->b & 0xff)|((color->b & 0xff) << 8); ++ *high = (color->b & 0xff)|((color->b & 0xff) << 8); ++ break; ++ // @FIXME: Richard uses GE_FMT_1ABFGBG12355 instead ++ // 1 A B Fg Bg ++ // 1 2 3 5 5 ++ case GE_FMT_1ABFGBG12355: ++ *low = (0x1f & blinkData->background) | // Bg: 4..0 ++ ((0x1f & blinkData->foreground)<< 5) | // Fg: 9..5 ++ ((0x1f & blinkData->ctrl_flag)<< 10) | // [A, B]: [14..13, 12..10] ++ BIT15; // Bit 15 ++ *high= (0x1f & blinkData->background) | // Bg: 4..0 ++ ((0x1f & blinkData->foreground)<< 5) | // Fg: 9..5 ++ ((0x1f & blinkData->ctrl_flag)<< 10) | // [A, B]: [14..13, 12..10] ++ BIT15; // Bit 15 ++ break; ++#if 0 ++ 1 B A A Fg Bg ++ 1 2 3 4 3 3 ++ case GE_FMT_1BAAFGBG123433 : ++ *low = ((blinkData->background & 0x7)|((blinkData->foreground & 0x7) << 3)|((blinkData->ctrl_flag & 0x1ff)<<6)|(0x1 << 15)); ++ *high = ((blinkData->background & 0x7)|((blinkData->foreground & 0x7) << 3)|((blinkData->ctrl_flag & 0x1ff)<<6)|(0x1 << 15)); ++ break; ++#endif ++ case GE_FMT_YUV422: ++ printk("[GE DRV][%06d] Are you sure to draw in YUV?\n", __LINE__); ++ ++ default: ++ GE_ASSERT(0, printk("[GE DRV][%06d] Bad color format\n", __LINE__)); ++ *low =(color->b & 0xff) | ((color->g & 0xff) << 8); ++ *high =(color->r & 0xff) | ((color->a & 0xff) << 8); ++ break; ++ } ++ ++} ++ ++void MHal_GE_PowerOff(void) ++{ ++ GE_WriteReg(GE_REG_FMT_BLT, GE_VAL_EN_CMDQ); ++ GE_WriteReg(GE_REG_EN, GE_VAL_EN_PE); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Set a palette entry, I8(8-bit palette) format. ++// @param palEntry \b IN: ptr to palette data ++// @param u32Index \b IN: Palette Index, ++// @return TRUE: sucess / FALSE: fail ++// @note: Titania2 GE (support 256 entries: Index: 0-255) ++//------------------------------------------------------------------------------------------------- ++GESTATUS _MHal_GE_Palette_Set( GePaletteEntry palEntry, U32 u32Index) ++{ ++ U32 u32RegVal; ++ ++ GE_WaitAvailableCMDQueue(8); ++ u32RegVal=palEntry.u32Data; ++ ++ GE_WriteReg(PE_REG_PT_GB, (u32RegVal & 0xFFFF)); ++ GE_WriteReg(PE_REG_PT_AR,((u32RegVal>>16)& 0xFFFF)); ++ u32RegVal=GE_ReadReg(PE_REG_PT_IDX); ++ GE_WriteReg(PE_REG_PT_IDX, ((u32Index&0xFF)|0x100)); ++ GE_WriteReg(PE_REG_PT_IDX,(u32RegVal &0xFEFF)); ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Set GE palette for I8(8-bit palette) format ++/// @param pPalArray \b IN: ptr to palette entry array ++/// @param u32PalStart \b IN: Define palette entry start index for set (range: 0~255) ++/// @param u32PalEnd \b IN: Define palette entry end index for set (range: 0~255) ++/// @return TRUE: sucess / FALSE: fail ++/// @note 1: GE palette is single port SRAM, You must set palettes before you read palette table. ++/// - I8 (valid palette index: 0~255) ++/// - Example: MHal_GE_Palette_Set ( pPalArray, 32, 255) ++//------------------------------------------------------------------------------------------------- ++GESTATUS MHal_GE_Palette_Set(GePaletteEntry * pPalArray, U32 u32PalStart, U32 u32PalEnd) ++{ ++ U32 u32I; ++ GESTATUS bRet = FALSE; ++ ++ if((u32PalEnd >= GE_PALETTE_ENTRY_NUM) || (u32PalStart > u32PalEnd)) ++ { ++ return FALSE; ++ } ++ ++ for (u32I = u32PalStart; u32I<=u32PalEnd; u32I++) ++ { ++ bRet = _MHal_GE_Palette_Set(pPalArray[u32I], u32I); ++ if (bRet == FALSE) ++ break; ++ } ++ ++ return bRet; ++} ++ +diff --git a/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge.h b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge.h +new file mode 100644 +index 00000000..a2ca09a4 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge.h +@@ -0,0 +1,582 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// @file drvGE.h ++/// @brief Graphics Engine Driver Interface ++/// @author MStar Semiconductor Inc. ++/// ++/// GE is used to paint OSD ++/// ++/// Features: ++/// - BLT engine : fast and simply blt function ++/// - Pixel engine(PE) : complex blt function ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef __DRVGE_H__ ++#define __DRVGE_H__ ++ ++#define GE_PALETTE_ENTRY_NUM 256 ++ ++//------------------------------------------------------------------------------ ++// macro ++//------------------------------------------------------------------------------ ++ ++//GE return code ++/// GE DDI return value ++#define GESTATUS U32 ++/// @name GESTATUS ++/// GESTATUS return value ++/// @{ ++#define GESTATUS_SUCCESS 0x00000000 //0 ++#define GESTATUS_FAIL 0x00000001 //Bit(0) ++#define GESTATUS_NON_ALIGN_ADDRESS 0x00000002 //Bit(1) ++#define GESTATUS_NON_ALIGN_PITCH 0x00000004 //Bit(2) ++#define GESTATUS_INVALID_INTENSITY_ID 0x00000008 //Bit(3) ++#define GESTATUS_INVALID_PARAMETERS 0x00000010 //Bit(4) ++ ++/// The above lines are moved from drvGE.h ++ ++ ++//------------------------------------------------------------------------------ ++// enum ++//------------------------------------------------------------------------------ ++ ++ ++ ++//------------------------------------------------------------------------------ ++// structure ++//------------------------------------------------------------------------------ ++ ++ ++///Define Raster Operation ++typedef enum ++{ ++ /// rop_result = 0; ++ ROP2_OP_ZORE = 0, ++ /// rop_result = ~( rop_src | rop_dst ); ++ ROP2_OP_NOT_PS_OR_PD = 1, ++ /// rop_result = ((~rop_src) & rop_dst); ++ ROP2_OP_NS_AND_PD = 2, ++ /// rop_result = ~(rop_src); ++ ROP2_OP_NS = 3, ++ /// rop_result = (rop_src & (~rop_dst)); ++ ROP2_OP_PS_AND_ND = 4, ++ /// rop_result = ~(rop_dst); ++ ROP2_OP_ND = 5, ++ /// rop_result = ( rop_src ^ rop_dst); ++ ROP2_OP_PS_XOR_PD = 6, ++ /// rop_result = ~(rop_src & rop_dst); ++ ROP2_OP_NOT_PS_AND_PD = 7, ++ /// rop_result = (rop_src & rop_dst); ++ ROP2_OP_PS_AND_PD = 8, ++ /// rop_result = ~(rop_dst ^ rop_src); ++ ROP2_OP_NOT_PS_XOR_PD = 9, ++ /// rop_result = rop_dst; ++ ROP2_OP_PD = 10, ++ /// rop_result = (rop_dst | (~rop_src)); ++ ROP2_OP_NS_OR_PD = 11, ++ /// rop_result = rop_src; ++ ROP2_OP_PS = 12, ++ /// rop_result = (rop_src | (~rop_dst)); ++ ROP2_OP_PS_OR_ND = 13, ++ /// rop_result = (rop_dst | rop_src); ++ ROP2_OP_PD_OR_PS = 14, ++ /// rop_result = 0xffffff; ++ ROP2_OP_ONE = 15, ++} GE_ROP2_OP; ++ ++ ++/// Color Key Operation Mode ++typedef enum ++{ ++ /// Not equal ++ CK_OP_NOT_EQUQL = 0, ++ /// Equal ++ CK_OP_EQUQL = 1, ++} GE_COLOR_KEY_MODE; ++ ++///Define Blending Coefficient ++typedef enum ++{ ++ /// 1 ++ COEF_ONE = 0, ++ /// constant ++ COEF_CONST = 1, ++ /// source alpha ++ COEF_ASRC = 2, ++ /// destination alpha ++ COEF_ADST = 3, ++ /// 0 ++ COEF_ZERO = 4, ++ /// 1 - constant ++ COEF_1_CONST = 5, ++ /// 1 - source alpha ++ COEF_1_ASRC = 6, ++ /// 1 - destination alpha ++ COEF_1_ADST = 7, ++} GE_BLEND_COEF; ++ ++///Define Blending Source from ++typedef enum ++{ ++ /// constant ++ ABL_FROM_CONST = 0, ++ /// source alpha ++ ABL_FROM_ASRC = 1, ++ /// destination alpha ++ ABL_FROM_ADST = 2, ++} GE_ALPHA_SRC_FROM; ++ ++/// GE buffer format ++typedef enum ++{ ++ /// font mode I1 ++ GE_FMT_I1 = 0x0, ++ /// font mode I2 ++ GE_FMT_I2 = 0x1, ++ /// font mode I4 ++ GE_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ GE_FMT_I8 = 0x4, ++ /// color format for blinking display format ++ GE_FMT_1ABFGBG12355 = 0x7, ++ /// color format RGB565 ++ GE_FMT_RGB565 = 0x8, ++ /// color format ORGB1555 ++ GE_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ GE_FMT_ARGB4444 = 0xa, ++ /// color format for blinking display format ++ GE_FMT_1BAAFGBG123433 = 0xb, ++ /// color format ARGB1555 of destination buffer ++ GE_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ GE_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ GE_FMT_ARGB8888 = 0xf ++}GE_Buffer_Format; ++ ++///Define Drawing type ++typedef enum ++{ ++ /// none ++ GE_DRAW_NONE = 0, ++ /// draw line ++ GE_DRAW_LINE = 1, ++ /// rectangle fill ++ GE_DRAW_RECTANGLE = 3, ++ /// bitblt ++ GE_DRAW_BITBLT = 4, ++}GE_DRAW_TYPE; ++ ++//------------------------------------------------- ++/// Define color ++typedef struct ++{ ++ /// Blue ++ U8 b; ++ /// Green ++ U8 g; ++ /// Red ++ U8 r; ++ /// Alpha ++ U8 a; ++} GE_RGB_COLOR; ++ ++typedef struct ++{ ++ U32 Y:8; ++ U32 U:4; ++ U32 V:4; ++} GE_YUV_COLOR; ++ ++typedef struct{ ++ union{ ++ GE_RGB_COLOR rgb; ++ GE_YUV_COLOR yuv; ++ }; ++} GE_COLOR; ++ ++//------------------------------------------------- ++/// Define the start color & end color ++typedef struct ++{ ++ /// start color ++ GE_RGB_COLOR color_s; ++ /// end color ++ GE_RGB_COLOR color_e; ++} GE_COLOR_RANGE; ++ ++//------------------------------------------------- ++/// Define the position of one point. ++typedef struct GE_POINT_s ++{ ++ /// X address ++ U16 x; ++ /// Y address ++ U16 y; ++} GE_POINT_t; ++ ++//------------------------------------------------- ++/// Specify the blink data ++#if 0 ++ // 1 B A A Fg Bg ++ // 1 2 3 4 3 3 ++typedef struct ++{ ++ /// BG color (for blink mode use) ++ U8 background; ++ /// FG color (for blink mode use) ++ U8 foreground; ++ /// Control flag\n ++ union{ ++ U16 ctrl_flag; ++ struct{ ++ U16 BlinkAlpha:4; ++ U16 Alpha:3; ++ U16 Blink:2; ++ U16 reserved:7; ++ }Bits; ++ }; ++ ++} GE_BLINK_DATA; ++#else ++ // 1 A B Fg Bg ++ // 1 2 3 5 5 ++typedef struct ++{ ++ /// BG color (for blink mode use) ++ U8 background; // 5 bits ++ /// FG color (for blink mode use) ++ U8 foreground; // 5 bits ++ /// Control flag\n ++ union{ ++ U16 ctrl_flag; ++ struct{ ++ U16 Blink:3; // 3 bits ++ U16 Alpha:2; // 2 bits ++ U16 reserved1:11; ++ } Bits; ++ }; ++ ++} GE_BLINK_DATA; ++ ++#endif ++ ++/// Define the start blink color & end blink color. ++typedef struct ++{ ++ /// start blink color ++ GE_BLINK_DATA blink_data_s; ++ /// end blink color ++ GE_BLINK_DATA blink_data_e; ++} GE_BLINK_DATA_RANGE; ++ ++//------------------------------------------------- ++//------------------------------------------------- ++#define GELINE_FLAG_COLOR_CONSTANT 0x00 ++#define GELINE_FLAG_COLOR_GRADIENT 0x01 ++/// Define the attribute of line. ++typedef struct ++{ ++ /// start X address ++ U16 x1; ++ /// Start Y address ++ U16 y1; ++ /// End X address ++ U16 x2; ++ /// End Y address ++ U16 y2; ++ /// Color format ++ GE_Buffer_Format fmt; ++ union ++ { ++ /// Color ++ ///For all RGB color, the color set as the ARGB8888 format.\n ++ ///Each color component need to shift to high bit.\n ++ ///Use ARGB1555 as the example, the source color key as the following:\n ++ ///ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++ ///colorRange.color_s --> A0000000RRRRR000GGGGG000BBBBB000 (every character represents one bit)\n\n ++ ///For GE_FMT_I8 format, the index set to b component (colorRange.color_s.b = b).\n ++ GE_COLOR_RANGE colorRange; ++ ///Blink attribute ++ ///For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++ GE_BLINK_DATA_RANGE blkDataRange; ++ }; ++ /// Line width ++ U32 width; ++ /// GELINE_FLAG_COLOR_CONSTANT: Constant color\n ++ /// GELINE_FLAG_COLOR_GRADIENT: Gradient color ++ U32 flag; ++ ++} GE_DRAW_LINE_INFO; ++ ++//------------------------------------------------- ++ ++/// Define the dimension of one block ++typedef struct ++{ ++ /// X start address ++ U16 x; ++ /// Y start address ++ U16 y; ++ /// width ++ U16 width; ++ /// height ++ U16 height; ++} GE_BLOCK; ++ ++ ++//------------------------------------------------- ++ ++#define GERECT_FLAG_COLOR_CONSTANT 0x0 ++#define GERECT_FLAG_COLOR_GRADIENT_X 0x1 ++#define GERECT_FLAG_COLOR_GRADIENT_Y 0x2 ++/// Define the info. of one block. ++typedef struct ++{ ++ /// dst block info ++ GE_BLOCK dstBlock; ++ /// Color format ++ GE_Buffer_Format fmt; ++ union ++ { ++ /// Color ++ ///For all RGB color, the color set as the ARGB8888 format.\n ++ ///Each color component need to shift to high bit.\n ++ ///Use ARGB1555 as the example, the source color key as the following:\n ++ ///ARGB1555 --> ARRRRRGGGGGBBBBB (every character represents one bit)\n ++ ///color_s --> A0000000RRRRR000GGGGG000BBBBB000 (every character represents one bit)\n\n ++ ///For GE_FMT_I8 format, the index set to b component (colorRange.color_s.b = b).\n ++ GE_COLOR_RANGE colorRange; ++ ///Blink attribute ++ ///For GE_FMT_1BAAFGBG123433 foramt, the foramt set as the GE_BLINK_DATA.\n ++ GE_BLINK_DATA_RANGE blkDataRange; ++ }; ++ ++ /// GERECT_FLAG_COLOR_CONSTANT: Constant color\n ++ /// GERECT_FLAG_COLOR_GRADIENT_X: X direction gradient color\n ++ /// GERECT_FLAG_COLOR_GRADIENT_Y: Y direction gradient color\n ++ U32 flag; ++ ++} GE_RECT_FILL_INFO; ++ ++typedef struct ++{ ++ /// dst block info ++ GE_BLOCK dstBlock; ++ /// Color format ++ GE_Buffer_Format fmt; ++ union{ ++ GE_RGB_COLOR color; ++ GE_BLINK_DATA blink_data; ++ }; ++ U32 u32LineWidth; ++} GE_OVAL_FILL_INFO; ++ ++ ++//------------------------------------------------- ++typedef enum ++{ ++ GEBLINK_NONE = 0x0, ++ GEBLINK_BACKGROUND, ++ GEBLINK_FOREGROUND, ++ GEBLINK_BOTH, ++} GE_BLINK_TYPE; ++ ++ ++//------------------------------------------------- ++typedef struct ++{ ++ U8 flag; ++ U32 delta_r; ++ U32 delta_g; ++ U32 delta_b; ++} GEColorDelta; ++ ++ ++//------------------------------------------------- ++/// Define rotation angle ++typedef enum ++{ ++ /// Do not rotate ++ GEROTATE_0 = 0, ++ /// Rotate 90 degree ++ GEROTATE_90 = 1, ++ /// Rotate 180 degree ++ GEROTATE_180 = 2, ++ /// Rotate 270 degree ++ GEROTATE_270 = 3 ++} GEROTATE_ANGLE; ++ ++ ++//============================================================================= ++// GE palette information ++//============================================================================= ++/// Define the entry of palette. ++typedef union ++{ ++ /// ARGB8888 ++ struct ++ { ++ /// B8 ++ U32 u8B: 8; ++ /// G8 ++ U32 u8G: 8; ++ /// R8 ++ U32 u8R: 8; ++ /// A8 ++ U32 u8A: 8; ++ } ARGB; ++ // 32-bit direct access. ++ U32 u32Data; ++} GePaletteEntry; ++ ++ ++//============================================================================= ++// Draw Rect info ++//============================================================================= ++/// Define the bitblt source & destination block. ++typedef struct ++{ ++ /// Source block ++ GE_BLOCK srcblk; ++ /// Destination block ++ GE_BLOCK dstblk; ++}GE_DRAW_RECT; ++ ++ ++/// Define the scaling factor for X & Y direction. ++typedef struct ++{ ++ U32 u32DeltaX; ++ U32 u32DeltaY; ++ U32 u32InitDelatX; ++ U32 u32InitDelatY; ++}GE_SCALE_INFO; ++ ++//============================================================================= ++// Data Buffer info ++//============================================================================= ++/// Data buffer info. ++typedef struct ++{ ++ /// start memory address ++ U32 u32Addr; // flat address of whole memory map ++ /// width ++ U32 u32Width; ++ /// height ++ U32 u32Height; ++ /// pitch ++ U32 u32Pitch; ++ /// Color format\n ++ /// - GE_FMT_I1\n ++ /// - GE_FMT_I2\n ++ /// - GE_FMT_I4\n ++ /// - GE_FMT_I8\n ++ /// - GE_FMT_RGB565\n ++ /// - GE_FMT_ARGB1555\n ++ /// - GE_FMT_ARGB4444\n ++ /// - GE_FMT_1BAAFGBG123433\n ++ /// - GE_FMT_ARGB8888\n ++ GE_Buffer_Format u32ColorFmt; ++} GE_BUFFER_INFO; ++ ++typedef GE_BUFFER_INFO* PGE_BUFFER_INFO; ++ ++#define GEDRAW_FLAG_DEFAULT 0x0 ++#define GEDRAW_FLAG_SCALE 0x1 ++#define GEDRAW_FLAG_DUPLICAPE 0x2 ++ ++ ++#define FB_FMT_AS_DEFAULT 0xFFFF ++ ++#define GE_DMA_WIDTH 32 ++#define GE_DMA_PITCH 16 ++ ++//============================================================================= ++// YUV color setting ++//============================================================================= ++typedef U8 GE_RGB2YUV_MODE; ++#define GE_RGB2YUV_PC_MODE ((GE_RGB2YUV_MODE)0x0) // computer mode Y: 16~ 235, UV: 0~ 240 ++#define GE_RGB2YUV_255_MODE ((GE_RGB2YUV_MODE)0x1) // To 0~ 255 ++ ++typedef U8 GE_YUV_RANGE_OUT; ++#define GE_YUV_RANGE_OUT_255 ((GE_YUV_RANGE_OUT)0x0) // To 0~ 255 ++#define GE_YUV_RANGE_OUT_PC ((GE_YUV_RANGE_OUT)0x1) // To Y: 16~ 235 ++ ++typedef U8 GE_YUV_RANGE_IN; ++#define GE_YUV_RANGE_IN_255 ((GE_YUV_RANGE_IN)0x0) // UV input range, 0~ 255 ++#define GE_YUV_RANGE_IN_127 ((GE_YUV_RANGE_IN)0x1) // UV input range, -128~ 127 ++ ++typedef U8 GE_YUV_422_FMT; ++#define GE_YUV_422_FMT_UY1VY0 ((GE_YUV_422_FMT)0x00) // CbY1CrY0 ++#define GE_YUV_422_FMT_VY1UY0 ((GE_YUV_422_FMT)0x01) // CrY1CbY0 ++#define GE_YUV_422_FMT_Y1UY0V ((GE_YUV_422_FMT)0x02) // Y1CbY0Cr ++#define GE_YUV_422_FMT_Y1VY0U ((GE_YUV_422_FMT)0x03) // Y1CrY0Cb ++ ++typedef struct ++{ ++ GE_RGB2YUV_MODE rgb2yuv_mode; ++ GE_YUV_RANGE_OUT yuv_range_out; ++ GE_YUV_RANGE_IN yuv_range_in; ++ GE_YUV_422_FMT yuv_mem_fmt_src; ++ GE_YUV_422_FMT yuv_mem_fmt_dst; ++} GE_YUV_INFO; ++ ++ ++//============================================================================= ++// GE Driver Function ++//============================================================================= ++extern void MHal_GE_Init(void); ++extern void MHal_GE_PowerOff(void); ++extern GESTATUS MHal_GE_ScreenCopy(GE_BLOCK *psrcblk, GE_BLOCK *pdstblk); ++extern GESTATUS MHal_GE_GetFrameBufferInfo(U32 *width, U32 *height, U32 *pitch, U32 *fbFmt, U32 *addr); ++extern GESTATUS MHal_GE_DrawLine(GE_DRAW_LINE_INFO *pline); ++extern GESTATUS MHal_GE_DrawOval(GE_OVAL_FILL_INFO* pOval); ++extern GESTATUS MHal_GE_RectFill(GE_RECT_FILL_INFO *pfillblock); ++extern GESTATUS MHal_GE_SetClip(GE_POINT_t* v0, GE_POINT_t* v1); ++extern GESTATUS MHal_GE_SetDither(U16 enable); ++extern GESTATUS MHal_GE_SetSrcBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte); ++extern GESTATUS MHal_GE_SetDstBufferInfo(PGE_BUFFER_INFO bufInfo, U32 offsetofByte); ++extern GESTATUS MHal_GE_SetNearestMode(U16 enable); ++extern GESTATUS MHal_GE_SetMirror(U16 isMirrorX, U16 isMirrorY); ++extern GESTATUS MHal_GE_SetROP2(U16 enable, GE_ROP2_OP eRopMode); ++extern GESTATUS MHal_GE_SetRotate(GEROTATE_ANGLE angle); ++extern GESTATUS MHal_GE_SetSrcColorKey(U16 enable, GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, void *ps_color, ++ void *pe_color); ++extern GESTATUS MHal_GE_SetDstColorKey(U16 enable, GE_COLOR_KEY_MODE opMode, ++ GE_Buffer_Format fmt, void *ps_color, ++ void *pe_color); ++extern GESTATUS MHal_GE_SetAlphaSrcFrom(GE_ALPHA_SRC_FROM eMode); ++extern GESTATUS MHal_GE_SetAlphaBlending(GE_BLEND_COEF blendcoef, U8 blendfactor); ++extern GESTATUS MHal_GE_EnableAlphaBlending(U16 enable); ++extern GESTATUS MHal_GE_Line_Pattern_Reset(void); ++extern GESTATUS MHal_GE_Set_Line_Pattern(U16 enable, U8 linePattern, U8 repeatFactor); ++extern GESTATUS MHal_GE_BitBlt(GE_DRAW_RECT *drawbuf,U32 drawflag); ++extern GESTATUS MHal_GE_BitBltEx(GE_DRAW_RECT * drawbuf, U32 drawflag, GE_SCALE_INFO * ScaleInfo); ++extern GESTATUS MHal_GE_GetScaleBltInfo(GE_DRAW_RECT* pdrawbuf, GE_BLOCK* pSrcBlk, GE_BLOCK* pDstBlk, GE_SCALE_INFO * pScaleInfo); ++extern GESTATUS MHal_GE_SetIntensity(U32 id, GE_Buffer_Format fmt, U32 *pColor); ++extern GESTATUS MHal_GE_BeginDraw(void); ++extern GESTATUS MHal_GE_EndDraw(void); ++extern GESTATUS MHal_GE_YUV_Set(GE_YUV_INFO* pYuvInfo); ++extern GESTATUS MHal_GE_YUV_Get(GE_YUV_INFO* pYuvInfo); ++extern GESTATUS MHal_GE_Palette_Set(GePaletteEntry * pPalArray, U32 u32PalStart, U32 u32PalEnd); ++ ++#endif ++ +diff --git a/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_fp.c b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_fp.c +new file mode 100644 +index 00000000..9dd4d3b8 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_fp.c +@@ -0,0 +1,191 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "mach/ms_types.h" ++#include "mhal_ge.h" ++ ++ ++//******************************************************************************/ ++// This function performs integer division ++// parameter: ++// u16x: numerator ++// u16y: denominator ++// nInterger: bit count of integer ++// nFraction: bit count of fraction ++// return: a U32 value in s.nInteger.nFraction form ++//******************************************************************************/ ++U32 Divide2Fixed(U16 u16x, U16 u16y, U8 nInteger, U8 nFraction) ++{ ++ U8 neg = 0; ++ U32 mask; ++ U32 u32x; ++ U32 u32y; ++ ++ if (u16x & 0x8000) ++ { ++ u32x = 0xFFFF0000 | u16x; ++ u32x = ~u32x + 1; //convert to positive ++ neg++; ++ } ++ else ++ { ++ u32x = u16x; ++ } ++ ++ if (u16y & 0x8000) ++ { ++ u32y = 0xFFFF0000 | u16y; ++ u32y = ~u32y + 1; //convert to positive ++ neg++; ++ } ++ else ++ { ++ u32y = u16y; ++ } ++ ++ // start calculation ++ u32x = (u32x << nFraction) / u32y; ++ if (neg % 2) ++ { ++ u32x = ~u32x + 1; ++ } ++ // total bit number is: 1(s) + nInteger + nFraction ++ mask = (1 << (1 + nInteger + nFraction)) - 1; ++ u32x &= mask; ++ ++ return u32x; ++} ++ ++#if 0 ++void FixPLine_S1_11(U16 u16x, U16 u16y, LONG16_BYTE* pu16ret) ++{ ++ FLOAT_BYTE tmp; ++ U16 t, t2; ++ U8 exp; ++ ++ if(u16y==0) ++ { ++ pu16ret->u16Num = 0; ++ return; ++ } ++ tmp.fvalue = (float)u16y / (float)u16x;//TODO ++ GE_DEBUGINFO(printf("tmp: %02bx %02bx %02bx %02bx\n", tmp.u8Num[0], tmp.u8Num[1], tmp.u8Num[2], tmp.u8Num[3])); ++ ++ pu16ret->u16Num = 0; ++ if((tmp.u8Num[0]&0x80) > 0) // negative number ++ { ++ pu16ret->u8Num[0] |= 0x10; ++ } ++ ++ exp = (tmp.u8Num[0]<<1) | (tmp.u8Num[1]&0x80)>>7; ++ GE_DEBUGINFO(printf("exp = %bx\n", exp)); ++ ++ t2 = tmp.u8Num[1] & 0x7F; ++ t = 0x800 | (t2 << 4) | (tmp.u8Num[2] & 0xF0) >> 4; ++ if(exp < 127) ++ { ++ pu16ret->u16Num |= (t >> (127 - exp)); ++ } ++ else ++ { ++ pu16ret->u16Num |= (t << (exp - 127)); ++ } ++ ++ GE_DEBUGINFO(printf("FixPLine_S1_11 = %f\n", tmp.fvalue)); ++ GE_DEBUGINFO(printf("S.1.11 = %x\n", pu16ret->u16Num)); ++ ++ pu16ret->u16Num = pu16ret->u16Num << 2; ++ GE_DEBUGINFO(printf("line reg = %x\n", pu16ret->u16Num)); ++} ++ ++/******************************************************************************/ ++/******************************************************************************/ ++void FixPClr_S8_11(S16 s16color, U16 u16dis, LONG32_BYTE* pu32ret) ++{ ++ FLOAT_BYTE tmp; ++ U32 t, t2; ++ U8 exp; ++ ++ tmp.fvalue = (float)s16color / (float)u16dis;//TODO ++ ++ GE_DEBUGINFO(printf("tmp: %02bx %02bx %02bx %02bx\n", tmp.u8Num[0], tmp.u8Num[1], tmp.u8Num[2], tmp.u8Num[3])); ++ ++ pu32ret->u32Num = 0; // reset return value ++// if((tmp.u8Num[0]&0x80) > 0) // negative number ++// { ++// pu32ret->u8Num[1] = 0x8; // bit 19 ++// } ++ ++ exp = (tmp.u8Num[0]<<1) | (tmp.u8Num[1]&0x80)>>7; ++ GE_DEBUGINFO(printf("exp = %bx\n", exp)); ++ ++ t2 = tmp.u8Num[1] & 0x7F; ++ t = 0x800 | (t2 << 4) | (tmp.u8Num[2] & 0xF0) >> 4; ++ if(exp < 127) ++ { ++ pu32ret->u32Num |= (t >> (127 - exp)); ++ } ++ else ++ { ++ pu32ret->u32Num |= (t << (exp - 127)); ++ } ++ ++ if((tmp.u8Num[0]&0x80) > 0) // negative number ++ { ++ pu32ret->u32Num = 0xFFFFFFFF - pu32ret->u32Num + 1; ++ } ++ ++ GE_DEBUGINFO(printf("FixPClr_S8_11 = %f\n", tmp.fvalue)); ++ GE_DEBUGINFO(printf("S.8.11 = %Lx\n", pu32ret->u32Num)); ++ ++ pu32ret->u32Num = pu32ret->u32Num << 12; ++ GE_DEBUGINFO(printf("Color delta reg = %Lx\n", pu32ret->u32Num)); ++} ++ ++/******************************************************************************/ ++/******************************************************************************/ ++void FixPBlt_S1_15(U16 u16src, U16 u16dst, LONG16_BYTE* pu16ret) ++{ ++ U32 t2; ++ U8 exp; ++ FLOAT_BYTE tmp; ++ ++ tmp.fvalue = (float)u16src / (float)u16dst;//TODO ++ ++ GE_DEBUGINFO(printf("tmp: %02bx %02bx %02bx %02bx\n", ++ tmp.u8Num[0], tmp.u8Num[1], tmp.u8Num[2], tmp.u8Num[3])); ++ ++ exp = (tmp.u8Num[0]<<1) | (tmp.u8Num[1]&0x80)>>7; ++ GE_DEBUGINFO(printf("exp = %bx\n", exp)); ++ ++ t2 = tmp.u8Num[1] & 0x7F; ++ pu16ret->u8Num[1] = tmp.u8Num[2]; ++ pu16ret->u8Num[0] = 0x80 | t2; ++ if(exp < 127) ++ { ++ pu16ret->u16Num = (pu16ret->u16Num >> (127 - exp)); ++ } ++ else ++ { ++ pu16ret->u16Num = (pu16ret->u16Num << (exp - 127)); ++ } ++ ++ GE_DEBUGINFO(printf("FixPBlt_S1_15 = %f\n", tmp.fvalue)); ++ GE_DEBUGINFO(printf("S.1.15 = %x\n", pu16ret->u16Num)); ++} ++ ++#endif //0 +diff --git a/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_fp.h b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_fp.h +new file mode 100644 +index 00000000..fda6350f +--- /dev/null ++++ b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_fp.h +@@ -0,0 +1,33 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef DRV_FIXEDPOINT_H ++#define DRV_FIXEDPOINT_H ++ ++#include "mhal_ge_reg.h" ++ ++ ++extern U32 Divide2Fixed(U16 u16x, U16 u16y, U8 nInterger, U8 nFraction); ++ ++#if 0 ++extern void FixPLine_S1_11(MS_U16 u16x, MS_U16 u16y, LONG16_BYTE* pu16ret); ++extern void FixPClr_S8_11(MS_S16 s8color, MS_U16 u16dis, LONG32_BYTE* pu32ret); ++extern void FixPBlt_S1_15(MS_U16 u16src, MS_U16 u16dst, LONG16_BYTE* pu16ret); ++#endif ++ ++#endif +diff --git a/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_reg.h b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_reg.h +new file mode 100644 +index 00000000..b04350f0 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/ge/columbus2/mhal_ge_reg.h +@@ -0,0 +1,275 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2010 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __REGGE_H__ ++#define __REGGE_H__ ++ ++#include ++ ++#define GE_LOG_ADR 0xa1600000 ++ ++///#define REG_GE_BASE (0xA0006C00+IO_OFFSET) ++ ++#define COLUMBUS_BASE_REG_RIU_PA (0xFD000000) ++#define REG_OFFSET_SHIFT_BITS 2 ++#ifndef GET_REG_ADDR ++#define GET_REG_ADDR(x, y) (x+((y)< ++#include // for MKDEV() ++#include ++#include ++#include ++#include ++ ++#include "mach/ms_types.h" ++#include "mhal_ge.h" ++#include "mdrv_ge.h" ++ ++#define MDRV_NAME_GE "ge" ++#define MDRV_MAJOR_GE 124 ++#define MDRV_MINOR_GE 1 ++ ++static int MDrv_GE_Open(struct inode *inode, struct file *filp); ++static int MDrv_GE_Release(struct inode *inode, struct file *filp); ++static long MDrv_GE_IOCtl(struct file *filp, unsigned int cmd, unsigned long arg); ++ ++//------------------------------------------------------------------------------ ++// structure ++//------------------------------------------------------------------------------ ++struct file_operations _ge_fops = ++{ ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = MDrv_GE_IOCtl, ++ .open = MDrv_GE_Open, ++ .release = MDrv_GE_Release, ++}; ++ ++// ----------------------------------------------------------------------------- ++// Global variable ++// ----------------------------------------------------------------------------- ++struct cdev *g_pGEDev = NULL; ++struct class *g_pGEClass = NULL; ++ ++// ----------------------------------------------------------------------------- ++// Local function ++// ----------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------ ++// GE & PE Function ++//------------------------------------------------------------------------------ ++ ++void MDrv_GE_Init(unsigned long arg) ++{ ++ MHal_GE_Init(); ++} ++ ++void MDrv_GE_PowerOff(unsigned long arg) ++{ ++ MHal_GE_PowerOff(); ++} ++ ++int MDrv_GE_ScreenCopy(unsigned long arg) ++{ ++ GE_BLOCK geSrcBlk, geDstBlk; ++ ++ if (copy_from_user(&geSrcBlk, ((MS_GE_SCREEN_COPY __user *)arg)->pSrcBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ ++ if (copy_from_user(&geDstBlk, ((MS_GE_SCREEN_COPY __user *)arg)->pDstBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_ScreenCopy(&geSrcBlk, &geDstBlk)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_GetFrameBufferInfo(unsigned long arg) ++{ ++ U32 u32Width; ++ U32 u32Height; ++ U32 u32Pitch; ++ U32 u32FbFmt; ++ U32 u32Addr; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_GetFrameBufferInfo(&u32Width, &u32Height, &u32Pitch, &u32FbFmt, &u32Addr)) ++ { ++ __put_user(u32Width, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Width)); ++ __put_user(u32Height, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Height)); ++ __put_user(u32Pitch, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Pitch)); ++ __put_user(u32FbFmt, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32FbFmt)); ++ __put_user(u32Addr, &(((MS_GE_GET_FRAMEBUFFERINFO __user *)arg)->u32Addr)); ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_DrawLine(unsigned long arg) ++{ ++ GE_DRAW_LINE_INFO geDrawLineInfo; ++ ++ if (copy_from_user(&geDrawLineInfo, ((GE_DRAW_LINE_INFO __user *)arg), sizeof(GE_DRAW_LINE_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_DrawLine(&(geDrawLineInfo))) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_DrawOval(unsigned long arg) ++{ ++ GE_OVAL_FILL_INFO geOval; ++ ++ if (copy_from_user(&geOval, ((GE_OVAL_FILL_INFO __user *)arg), sizeof(GE_OVAL_FILL_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_DrawOval(&geOval)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_RectFill(unsigned long arg) ++{ ++ GE_RECT_FILL_INFO geRectFillInfo; ++ ++ if (copy_from_user(&geRectFillInfo, ((GE_RECT_FILL_INFO __user *)arg), sizeof(GE_RECT_FILL_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_RectFill(&geRectFillInfo)) ++ { ++ //printk("MDrv_GE_RectFill Success\n"); ++ return 0; ++ } ++ else ++ { ++ printk("MDrv_GE_RectFill Fail\n"); ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetClip(unsigned long arg) ++{ ++ GE_POINT_t geV0, geV1; ++ ++ if (copy_from_user(&geV0, ((MS_GE_SET_CLIP __user *)arg)->pPoint0, sizeof(GE_POINT_t))) ++ return EFAULT; ++ ++ if (copy_from_user(&geV1, ((MS_GE_SET_CLIP __user *)arg)->pPoint1, sizeof(GE_POINT_t))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetClip(&geV0, &geV1)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetDither(unsigned long arg) ++{ ++ U16 blDither; ++ ++ if (__get_user(blDither, (U16 __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetDither(blDither)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetSrcBufferInfo(unsigned long arg) ++{ ++ GE_BUFFER_INFO geBufferInfo; ++ U32 u32OffsetofByte; ++ ++ if (copy_from_user(&geBufferInfo, ((MS_GE_SET_BUFFERINFO __user *)arg)->pBufferInfo, sizeof(GE_BUFFER_INFO))) ++ return EFAULT; ++ if (__get_user(u32OffsetofByte, &(((MS_GE_SET_BUFFERINFO __user *)arg)->u32OffsetofByte))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetSrcBufferInfo(&geBufferInfo, u32OffsetofByte)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetDstBufferInfo(unsigned long arg) ++{ ++ GE_BUFFER_INFO geBufferInfo; ++ U32 u32OffsetofByte; ++ ++ if (copy_from_user(&geBufferInfo, ((MS_GE_SET_BUFFERINFO __user *)arg)->pBufferInfo, sizeof(GE_BUFFER_INFO))) ++ return EFAULT; ++ if (__get_user(u32OffsetofByte, &(((MS_GE_SET_BUFFERINFO __user *)arg)->u32OffsetofByte))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetDstBufferInfo(&geBufferInfo, u32OffsetofByte)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetNearestMode(unsigned long arg) ++{ ++ U16 bNearestMode; ++ ++ if (__get_user(bNearestMode, (U16 __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetNearestMode(bNearestMode)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetMirror(unsigned long arg) ++{ ++ MS_GE_SET_MIRROR geSetMirror; ++ ++ if (copy_from_user(&geSetMirror, (MS_GE_SET_MIRROR __user *)arg, sizeof(MS_GE_SET_MIRROR))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetMirror(geSetMirror.blIsMirrorX, geSetMirror.blIsMirrorY)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetROP2(unsigned long arg) ++{ ++ MS_GE_SET_ROP2 geSetROP2; ++ ++ if (copy_from_user(&geSetROP2, (MS_GE_SET_ROP2 __user *)arg, sizeof(MS_GE_SET_ROP2))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetROP2(geSetROP2.blEnable, geSetROP2.eRopMode)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetRotate(unsigned long arg) ++{ ++ GEROTATE_ANGLE geRotateAngle; ++ ++ if (__get_user(geRotateAngle, (GEROTATE_ANGLE __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetRotate(geRotateAngle)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetSrcColorKey(unsigned long arg) ++{ ++ U16 blEnable; ++ GE_COLOR_KEY_MODE enColorKeyMode; ++ GE_Buffer_Format enBufferFmt; ++ U32 u32PS_Color; ++ U32 u32GE_Color; ++ ++ if (__get_user(blEnable, &((MS_GE_SET_COLORKEY __user *)arg)->blEnable)) ++ return EFAULT; ++ ++ if (__get_user(enColorKeyMode, &((MS_GE_SET_COLORKEY __user *)arg)->eOPMode)) ++ return EFAULT; ++ ++ if (__get_user(enBufferFmt, &((MS_GE_SET_COLORKEY __user *)arg)->enBufferFmt)) ++ return EFAULT; ++ ++ if (__get_user(u32PS_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32PS_Color)) ++ return EFAULT; ++ ++ if (__get_user(u32GE_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32GE_Color)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetSrcColorKey(blEnable, enColorKeyMode, enBufferFmt, &u32PS_Color, &u32GE_Color)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetDstColorKey(unsigned long arg) ++{ ++ U16 blEnable; ++ GE_COLOR_KEY_MODE enColorKeyMode; ++ GE_Buffer_Format enBufferFmt; ++ U32 u32PS_Color; ++ U32 u32GE_Color; ++ ++ if (__get_user(blEnable, &((MS_GE_SET_COLORKEY __user *)arg)->blEnable)) ++ return EFAULT; ++ ++ if (__get_user(enColorKeyMode, &((MS_GE_SET_COLORKEY __user *)arg)->eOPMode)) ++ return EFAULT; ++ ++ if (__get_user(enBufferFmt, &((MS_GE_SET_COLORKEY __user *)arg)->enBufferFmt)) ++ return EFAULT; ++ ++ if (__get_user(u32PS_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32PS_Color)) ++ return EFAULT; ++ ++ if (__get_user(u32GE_Color, ((MS_GE_SET_COLORKEY __user *)arg)->pu32GE_Color)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetDstColorKey(blEnable, enColorKeyMode, enBufferFmt, &u32PS_Color, &u32GE_Color)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetAlphaSrcFrom(unsigned long arg) ++{ ++ GE_ALPHA_SRC_FROM eMode; ++ ++ if (__get_user(eMode, (GE_ALPHA_SRC_FROM __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetAlphaSrcFrom(eMode)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetAlphaBlending(unsigned long arg) ++{ ++ MS_GE_SET_ALPHABLENDING geSetAlphaBlending; ++ ++ if (copy_from_user(&geSetAlphaBlending, (MS_GE_SET_ALPHABLENDING __user *)arg, sizeof(MS_GE_SET_ALPHABLENDING))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetAlphaBlending(geSetAlphaBlending.enBlendCoef, geSetAlphaBlending.u8BlendFactor)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_EnableAlphaBlending(unsigned long arg) ++{ ++ U16 blEnable; ++ ++ if (__get_user(blEnable, (U16 __user *)arg)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_EnableAlphaBlending(blEnable)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_Line_Pattern_Reset(unsigned long arg) ++{ ++ if (GESTATUS_SUCCESS == MHal_GE_Line_Pattern_Reset()) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_Set_Line_Pattern(unsigned long arg) ++{ ++ U16 blEnable; ++ U8 u8LinePattern; ++ U8 u8RepeatFactor; ++ ++ if (__get_user(blEnable, &(((MS_GE_SET_LINEPATTERN __user *)arg)->blEnable))) ++ return EFAULT; ++ if (__get_user(u8LinePattern, &(((MS_GE_SET_LINEPATTERN __user *)arg)->u8LinePattern))) ++ return EFAULT; ++ if (__get_user(u8RepeatFactor, &(((MS_GE_SET_LINEPATTERN __user *)arg)->u8RepeatFactor))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_Set_Line_Pattern(blEnable, u8LinePattern, u8RepeatFactor)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_BitBlt(unsigned long arg) ++{ ++ GE_DRAW_RECT geDrawRect; ++ U32 u32DrawFlag; ++ ++ if (copy_from_user(&geDrawRect, ((MS_GE_SET_BITBLT __user *)arg)->pGEDrawRect, sizeof(GE_DRAW_RECT))) ++ return EFAULT; ++ if (__get_user(u32DrawFlag, &(((MS_GE_SET_BITBLT __user *)arg)->u32DrawFlag))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_BitBlt(&geDrawRect, u32DrawFlag)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_BitBltEx(unsigned long arg) ++{ ++ GE_DRAW_RECT geDrawRect; ++ U32 u32DrawFlag; ++ GE_SCALE_INFO geScaleInfo; ++ ++ if (copy_from_user(&geDrawRect, ((MS_GE_SET_BITBLTEX __user *)arg)->pDrawRect, sizeof(GE_DRAW_RECT))) ++ return EFAULT; ++ if (__get_user(u32DrawFlag, &(((MS_GE_SET_BITBLTEX __user *)arg)->u32DrawFlag))) ++ return EFAULT; ++ if (copy_from_user(&geScaleInfo, ((MS_GE_SET_BITBLTEX __user *)arg)->pScaleInfo, sizeof(GE_SCALE_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_BitBltEx(&geDrawRect, u32DrawFlag, &geScaleInfo)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_GetScaleBltInfo(unsigned long arg) ++{ ++ GE_DRAW_RECT geDrawRect; ++ GE_BLOCK geSrcBlk; ++ GE_BLOCK geDstBlk; ++ GE_SCALE_INFO geScaleInfo; ++ ++ if (copy_from_user(&geDrawRect, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pDrawRect, sizeof(GE_DRAW_RECT))) ++ return EFAULT; ++ if (copy_from_user(&geSrcBlk, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pSrcBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ if (copy_from_user(&geDstBlk, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pDstBlk, sizeof(GE_BLOCK))) ++ return EFAULT; ++ if (copy_from_user(&geScaleInfo, ((MS_GE_GET_SCALEBLTINFO __user *)arg)->pScaleInfo, sizeof(GE_SCALE_INFO))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_GetScaleBltInfo(&geDrawRect, &geSrcBlk, &geDstBlk, &geScaleInfo)) ++ { ++ unsigned long r = 0; ++ r = copy_to_user(((MS_GE_GET_SCALEBLTINFO __user *)arg)->pSrcBlk, &geSrcBlk, sizeof(GE_BLOCK)); ++ if (r) return r; ++ r = copy_to_user(((MS_GE_GET_SCALEBLTINFO __user *)arg)->pDstBlk, &geDstBlk, sizeof(GE_BLOCK)); ++ if (r) return r; ++ r = copy_to_user(((MS_GE_GET_SCALEBLTINFO __user *)arg)->pScaleInfo, &geScaleInfo, sizeof(GE_SCALE_INFO)); ++ if (r) return r; ++ ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_SetIntensity(unsigned long arg) ++{ ++ U32 u32ID; ++ GE_Buffer_Format enBufferFmt; ++ U32 u32Color; ++ ++ if (__get_user(u32ID, &(((MS_GE_SET_INTENSITY __user *)arg)->u32ID))) ++ return EFAULT; ++ if (__get_user(enBufferFmt, &(((MS_GE_SET_INTENSITY __user *)arg)->enBufferFmt))) ++ return EFAULT; ++ if (__get_user(u32Color, ((MS_GE_SET_INTENSITY __user *)arg)->pu32Color)) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_SetIntensity(u32ID, enBufferFmt, &u32Color)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_BeginDraw(unsigned long arg) ++{ ++ if (GESTATUS_SUCCESS == MHal_GE_BeginDraw()) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_EndDraw(unsigned long arg) ++{ ++ if (GESTATUS_SUCCESS == MHal_GE_EndDraw()) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_YUV_Set(unsigned long arg) ++{ ++ GE_YUV_INFO geYUVInfo; ++ if (copy_from_user(&geYUVInfo, (GE_BUFFER_INFO __user *)arg, sizeof(geYUVInfo))) ++ return EFAULT; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_YUV_Set(&geYUVInfo)) ++ { ++ return 0; ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_YUV_Get(unsigned long arg) ++{ ++ GE_YUV_INFO geYUVInfo; ++ ++ if (GESTATUS_SUCCESS == MHal_GE_YUV_Get(&geYUVInfo)) ++ { ++ return copy_to_user(( GE_BUFFER_INFO __user *)arg, &geYUVInfo, sizeof(GE_BUFFER_INFO)); ++ } ++ else ++ { ++ // The return value is not so appropriate. ++ return EFAULT; ++ } ++} ++ ++int MDrv_GE_Palette_Set(unsigned long arg) ++{ ++ GePaletteEntry *pGePalArray; ++ U32 u32PalStart; ++ U32 u32PalEnd; ++ U32 u32PalSize; ++ int iRet = 0; ++ ++ if (__get_user(u32PalStart, &((MS_GE_SET_PALETTE __user *)arg)->u32PalStart)) ++ iRet = EFAULT; ++ if (__get_user(u32PalEnd, &((MS_GE_SET_PALETTE __user *)arg)->u32PalEnd)) ++ iRet = EFAULT; ++ ++ u32PalSize = u32PalEnd - u32PalStart + 1; ++ ++ pGePalArray = kmalloc(sizeof(GePaletteEntry) * u32PalSize, GFP_KERNEL); ++ ++ if (pGePalArray) ++ { ++ if (copy_from_user(pGePalArray, ((MS_GE_SET_PALETTE __user *)arg)->pPalArray, sizeof(GePaletteEntry)*u32PalSize)) ++ { ++ iRet = EFAULT; ++ } ++ ++ if (MHal_GE_Palette_Set(pGePalArray, u32PalStart, u32PalEnd)) ++ { ++ iRet = EFAULT; ++ } ++ ++ kfree(pGePalArray); ++ } ++ else ++ { ++ iRet = EFAULT; ++ } ++ ++ return iRet; ++} ++ ++ ++// ----------------------------------------------------------------------------- ++// Device Methods ++// ----------------------------------------------------------------------------- ++ ++/* ++ * Open and close ++ */ ++ ++int MDrv_GE_Open(struct inode *inode, struct file *filp) ++{ ++ struct cdev *pDev = inode->i_cdev; ++ filp->private_data = pDev; /* for other methods */ ++ ++ printk("GE opens successfully\n"); ++ ++ return 0; /* success */ ++} ++ ++int MDrv_GE_Release(struct inode *inode, struct file *filp) ++{ ++ printk("GE closes successfully\n"); ++ ++ return 0; ++} ++ ++extern void dummyRegWrite( void ) ; ++extern void outGE_WaitAvailableCMDQueue(void); ++ ++long MDrv_GE_IOCtl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ /* ++ * extract the type and number bitfields, and don't decode ++ * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ */ ++ if (_IOC_TYPE(cmd) != MDRV_GE_IOC_MAGIC) { ++ printk("IOCtl Type Error!!! (Cmd=%x)\n",cmd); ++ return -ENOTTY; ++ } ++ if (_IOC_NR(cmd) > MDRV_GE_IOC_MAXNR) { ++ printk("IOCtl NR Error!!! (Cmd=%x)\n",cmd); ++ return -ENOTTY; ++ } ++ ++ /* ++ * the direction is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. `Type' is user-oriented, while ++ * access_ok is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ if (err) { ++ printk("IOCtl Error!!! (cmd=%x)\n",cmd); ++ return -EFAULT; ++ } ++ ++ switch(cmd) { ++ case MDRV_GE_IOC_INIT: ++ MDrv_GE_Init(arg); ++ break; ++ ++ case MDRV_GE_IOC_POWER_OFF: ++ MDrv_GE_PowerOff(arg); ++ break; ++ ++ case MDRV_GE_IOC_SCREEN_COPY: ++ retval = MDrv_GE_ScreenCopy(arg); ++ break; ++ ++ case MDRV_GE_IOC_GET_FRAMEBUFFERINFO: ++ retval = MDrv_GE_GetFrameBufferInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_DRAW_LINE: ++ retval = MDrv_GE_DrawLine(arg); ++ break; ++ ++ case MDRV_GE_IOC_DRAW_OVAL: ++ retval = MDrv_GE_DrawOval(arg); ++ break; ++ ++ case MDRV_GE_IOC_RECT_FILL: ++ MDrv_GE_RectFill(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_CLIP: ++ MDrv_GE_SetClip(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_DITHER: ++ MDrv_GE_SetDither(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_SRCBUFFERINO: ++ MDrv_GE_SetSrcBufferInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_DSTBUFFERINO: ++ MDrv_GE_SetDstBufferInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_NEARESTMODE: ++ MDrv_GE_SetNearestMode(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_MIRROR: ++ MDrv_GE_SetMirror(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ROP2: ++ MDrv_GE_SetROP2(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ROTATE: ++ MDrv_GE_SetRotate(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_SRCCOLORKEY: ++ MDrv_GE_SetSrcColorKey(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_DSTCOLORKEY: ++ MDrv_GE_SetDstColorKey(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ALPHASRCFROM: ++ MDrv_GE_SetAlphaSrcFrom(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_ALPHABLENDING: ++ MDrv_GE_SetAlphaBlending(arg); ++ break; ++ ++ case MDRV_GE_IOC_ENABLE_ALPHABLENDING: ++ MDrv_GE_EnableAlphaBlending(arg); ++ break; ++ ++ case MDRV_GE_IOC_LINEPATTERN_RESET: ++ MDrv_GE_Line_Pattern_Reset(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_LINEPATTERN: ++ MDrv_GE_Set_Line_Pattern(arg); ++ break; ++ ++ case MDRV_GE_IOC_BITBLT: ++ MDrv_GE_BitBlt(arg); ++ break; ++ ++ case MDRV_GE_IOC_BITBLTEX: ++ MDrv_GE_BitBltEx(arg); ++ break; ++ ++ case MDRV_GE_IOC_Get_SCALEBLTINFO: ++ MDrv_GE_GetScaleBltInfo(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_INTENSITY: ++ MDrv_GE_SetIntensity(arg); ++ break; ++ ++ case MDRV_GE_IOC_BEGIN_DRAW: ++ MDrv_GE_BeginDraw(arg); ++ break; ++ ++ case MDRV_GE_IOC_END_DRAW: ++ MDrv_GE_EndDraw(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_YUV: ++ MDrv_GE_YUV_Set(arg); ++ break; ++ ++ case MDRV_GE_IOC_GET_YUV: ++ MDrv_GE_YUV_Get(arg); ++ break; ++ ++ case MDRV_GE_IOC_SET_PALETTE: ++ MDrv_GE_Palette_Set(arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ printk("Unknow IOCTL %x\n",cmd); ++ return -ENOTTY; ++ } ++ ++ outGE_WaitAvailableCMDQueue(); ++ ++ dummyRegWrite() ; ++ ++ return retval; ++} ++ ++static int __init MDrv_GE_Module_Init(void) ++{ ++ int err, devno = MKDEV(MDRV_MAJOR_GE, MDRV_MINOR_GE); ++ ++ printk("GE driver inits\n"); ++ ++ /* register the 'dummy_dev' char device */ ++ g_pGEDev = cdev_alloc(); ++ cdev_init(g_pGEDev, &_ge_fops); ++ ++ g_pGEDev->owner = THIS_MODULE; ++ ++ err = cdev_add(g_pGEDev, devno, 1); ++ if (err != 0) ++ printk("dummy pci device register failed!\n"); ++ ++ /* creating your own class */ ++ g_pGEClass = class_create(THIS_MODULE, "ge"); ++ if(IS_ERR(g_pGEClass)) { ++ printk("Err: failed in creating class.\n"); ++ return -1; ++ } ++ ++ /* register your own device in sysfs, and this will cause udevd to create corresponding device node */ ++ device_create(g_pGEClass, NULL, devno, NULL, "ge"); ++ ++ // Maybe need to move to MHal_GE_Module_Init ++ MHal_GE_Init(); ++ ++ return 0; ++} ++ ++static void __exit MDrv_GE_Module_Exit(void) ++{ ++ cdev_del(g_pGEDev); ++ ++ device_destroy(g_pGEClass, MKDEV(MDRV_MAJOR_GE, MDRV_MINOR_GE)); ++ class_destroy(g_pGEClass); ++ ++ printk("GE driver exits\n"); ++} ++ ++module_init(MDrv_GE_Module_Init); ++module_exit(MDrv_GE_Module_Exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GE driver"); ++MODULE_LICENSE("MSTAR"); +diff --git a/drivers/mstar/fb/chicago/gop/Makefile b/drivers/mstar/fb/chicago/gop/Makefile +new file mode 100644 +index 00000000..2a15f500 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_MS_FB_CHICAGO) += hal/ ++ +diff --git a/drivers/mstar/fb/chicago/gop/hal/cedric_r2.h b/drivers/mstar/fb/chicago/gop/hal/cedric_r2.h +new file mode 100644 +index 00000000..dcd280ab +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/hal/cedric_r2.h +@@ -0,0 +1,439 @@ ++// $Change: 627140 $ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2012 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// cedric_QST.h ++// ++// DESCRIPTION ++// ++// ++// HISTORY ++//----------------------------------------------------------------------------- ++ ++#ifndef __CEDRIC_R2_H__ ++#define __CEDRIC_R2_H__ ++ ++ ++//------------------------------------------------------------------------------ ++// Macro ++//------------------------------------------------------------------------------ ++#include "platform.h" ++ ++#define HK_CNTROL_CAR_BACKING ++//display related ++//rtk qstart related--mailbox ++ ++#define DETECT_METHOD 1 ++// 0 for interrupt from rtk ++// 1 for polling mailbox ++ ++#define QST_ALWAYS_RUN 1 ++ ++ ++#define TOKEN_GET 0x08 ++#define CAR_MODE 0x04 ++ ++ ++#define MBX_TX (0X41) //HOSTKEEPER_MBX ++#define MBX_RX (0x42) //CARBACKING_MBX ++#define MBX_TOUCH_X (0X43) ++#define MBX_TOUCH_Y (0X44) ++ ++ ++#define CEDRIC_BASE_REG_MBX_PA GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x81980) ++#define REG_MBX_BASE GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,0X40) ++#define REG_MBX_RX GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_RX) ++#define REG_MBX_TX GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TX) ++#define REG_MBX_TOUCH_X GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TOUCH_X) ++#define REG_MBX_TOUCH_Y GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TOUCH_Y) ++ ++ ++#define LOOP_THRESHOLD 8 ++#define CarBackingState (1<<2) ++ ++ ++ ++typedef struct ++{ ++/* ++h0040 h0040 15 0 reg_mb0_0 ++*/ ++ U16 reg_mb0_0; ++ U16 u16REG_RESERVED_40; ++ ++/* ++ ++h0041 h0041 15 0 reg_mb0_1 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_1; /* 00h */ ++ struct ++ { ++ volatile U16 token :4; ++ volatile U16 touch_flag :1; ++ //#define VALID 1 ++ //#define INVALID 0 ++ volatile U16 bt_flag :1; ++ volatile U16 suspend_flag :1; ++ volatile U16 Os_flag :1; ++ volatile U16 boot_type :1; ++ volatile U16 cfg_loaded :1; ++ volatile U16 Os_reset :1; ++ volatile U16 reserve41 :5; ++ //bit 3~f reserve ++ }; ++ }; ++ U16 u16REG_RESERVED_41; ++ ++/* ++ ++h0042 h0042 15 0 reg_mb0_2 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_2; /* 00h */ ++ struct ++ { ++ volatile U16 disp_inited :1; ++ //#define DISP_INIT 1 ++ //#define DISP_NON 0 ++ ++ volatile U16 cvbs_in :1; //represent cvbs in is ok or not ++ //#define CVBS_IN_OK 1 ++ //#define CVBS_IN_NON 0 ++ ++ volatile U16 carbacking_status :1; ++ //value as enum CAR_BACKING_MODE ++ ++ volatile U16 token_switch :1; ++ //#define TOKEN_CP 0 //co processor ++ //#define TOKEN_HK 1 //host keeper ++ volatile U16 app_launch :4; ////max support 15 apps ++ ++ volatile U16 bt_call_rsp :2; // give response to ARM OS ++ ++ volatile U16 mmi_task_running :1; //mmi task exist or not ++ volatile U16 reserve42 :5; ++ ++ }; ++ }; ++ U16 u16REG_RESERVED_42; ++ ++/* ++h0043 h0043 15 0 reg_mb0_3 ++*/ ++ U16 u16MBX_TOUCH_X; ++ U16 u16REG_RESERVED_43; ++ ++/* ++h0044 h0044 15 0 reg_mb0_4 ++*/ ++ U16 u16MBX_TOUCH_Y; ++ U16 u16REG_RESERVED_44; ++ ++/* ++h0045 h0045 15 0 reg_mb0_5 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_5; /* 00h */ ++ struct ++ { ++ volatile U16 rtk_heart :1; ++ volatile U16 reserve45 :15; ++ ++ }; ++ }; ++ U16 u16REG_RESERVED_45; ++ ++/* ++h0046 h0046 15 0 reg_mb0_6 ++*/ ++ U16 reg_mb0_6; ++ U16 u16REG_RESERVED_46; ++ ++/* ++h0047 h0047 15 0 reg_mb0_7 ++*/ ++ U16 reg_mb0_7; ++ U16 u16REG_RESERVED_47; ++ ++/* ++h0048 h0048 15 0 reg_mb0_8 ++*/ ++ U16 reg_mb0_8; ++ U16 u16REG_RESERVED_48; ++ ++/* ++h0049 h0049 15 0 reg_mb0_9 ++*/ ++ U16 reg_mb0_9; ++ U16 u16REG_RESERVED_49; ++ ++/* ++h004a h004a 15 0 reg_mb0_a ++*/ ++ U16 reg_mb0_a; ++ U16 u16REG_RESERVED_4a; ++ ++/* ++h004b h004b 15 0 reg_mb0_b ++*/ ++ U16 reg_mb0_b; ++ U16 u16REG_RESERVED_4b; ++ ++/* ++h004c h004c 15 0 reg_mb0_c ++*/ ++ U16 reg_mb0_c; ++ U16 u16REG_RESERVED_4c; ++ ++/* ++h004d h004d 15 0 reg_mb0_d ++*/ ++ U16 reg_mb0_d; ++ U16 u16REG_RESERVED_4d; ++ ++/* ++h004e h004e 15 0 reg_mb0_e ++*/ ++ U16 reg_mb0_e; ++ U16 u16REG_RESERVED_4e; ++ ++/* ++h004f h004f 15 0 reg_mb0_f ++*/ ++ U16 reg_mb0_f; ++ U16 u16REG_RESERVED_4f; ++ ++/* ++h0050 h0050 15 0 reg_mb0_10 ++*/ ++ U16 reg_mb0_10; ++ U16 u16REG_RESERVED_50; ++ ++/* ++h0051 h0051 15 0 reg_mb0_11 ++*/ ++ U16 reg_mb0_11; ++ U16 u16REG_RESERVED_51; ++ ++/* ++h0052 h0052 15 0 reg_mb0_12 ++*/ ++ U16 reg_mb0_12; ++ U16 u16REG_RESERVED_52; ++ ++/* ++h0053 h0053 15 0 reg_mb0_13 ++*/ ++ U16 reg_mb0_13; ++ U16 u16REG_RESERVED_53; ++ ++/* ++h0054 h0054 15 0 reg_mb0_14 ++*/ ++ U16 reg_mb0_14; ++ U16 u16REG_RESERVED_54; ++ ++/* ++h0055 h0055 15 0 reg_mb0_15 ++*/ ++ U16 reg_mb0_15; ++ U16 u16REG_RESERVED_55; ++ ++/* ++h0056 h0056 15 0 reg_mb0_16 ++*/ ++ U16 reg_mb0_16; ++ U16 u16REG_RESERVED_56; ++ ++/* ++h0057 h0057 15 0 reg_mb0_17 ++*/ ++ U16 reg_mb0_17; ++ U16 u16REG_RESERVED_57; ++ ++/* ++h0058 h0058 15 0 reg_mb0_18 ++*/ ++ U16 reg_mb0_18; ++ U16 u16REG_RESERVED_58; ++ ++/* ++h0059 h0059 15 0 reg_mb0_19 ++*/ ++ U16 reg_mb0_19; ++ U16 u16REG_RESERVED_59; ++ ++/* ++h005A h005A 15 0 reg_mb0_1A ++*/ ++ U16 reg_mb0_1A; ++ U16 u16REG_RESERVED_5a; ++ ++/* ++h005B h005B 15 0 reg_mb0_1B ++*/ ++ U16 reg_mb0_1B; ++ U16 u16REG_RESERVED_5b; ++ ++/* ++h005C h005C 15 0 reg_mb0_1C ++*/ ++ U16 reg_mb0_1C; ++ U16 u16REG_RESERVED_5c; ++ ++/* ++h005D h005D 15 0 reg_mb0_1D ++*/ ++ U16 reg_mb0_1D; ++ U16 u16REG_RESERVED_5d; ++ ++/* ++h005E h005E 15 0 reg_mb0_1E ++*/ ++ U16 reg_mb0_1E; ++ U16 u16REG_RESERVED_5e; ++ ++/* ++h005f h005f 15 0 reg_mb0_1f ++*/ ++ U16 reg_mb0_1f; ++ U16 u16REG_RESERVED_5f; ++ ++/* ++h0060 h0060 15 0 reg_mb0_20 ++*/ ++ U16 reg_mb0_20; ++ U16 u16REG_RESERVED_60; ++ ++/* ++h0061 h0061 15 0 reg_mb0_21 ++*/ ++ U16 reg_mb0_21; ++ U16 u16REG_RESERVED_61; ++ ++/* ++h0062 h0062 15 0 reg_mb0_22 ++*/ ++ U16 reg_mb0_22; ++ U16 u16REG_RESERVED_62; ++ ++/* ++h0063 h0063 15 0 reg_mb0_23 ++*/ ++ U16 reg_mb0_23; ++ U16 u16REG_RESERVED_63; ++ ++/* ++h0064 h0064 15 0 reg_mb0_24 ++*/ ++ U16 reg_mb0_24; ++ U16 u16REG_RESERVED_64; ++ ++/* ++h0065 h0065 15 0 reg_mb0_25 ++*/ ++ U16 reg_mb0_25; ++ U16 u16REG_RESERVED_65; ++ ++/* ++h0066 h0066 15 0 reg_mb0_26 ++*/ ++ U16 reg_mb0_26; ++ U16 u16REG_RESERVED_66; ++ ++/* ++h0067 h0067 15 0 reg_mb0_27 ++*/ ++ U16 reg_mb0_27; ++ U16 u16REG_RESERVED_67; ++ ++/* ++h0068 h0068 15 0 reg_mb0_28 ++*/ ++ U16 reg_mb0_28; ++ U16 u16REG_RESERVED_68; ++ ++/* ++h0069 h0069 15 0 reg_mb0_29 ++*/ ++ U16 reg_mb0_29; ++ U16 u16REG_RESERVED_69; ++ ++/* ++h006A h006A 15 0 reg_mb0_2A ++*/ ++ U16 reg_mb0_2A; ++ U16 u16REG_RESERVED_6a; ++ ++/* ++h006B h006B 15 0 reg_mb0_2B ++*/ ++ U16 reg_mb0_2B; ++ U16 u16REG_RESERVED_6b; ++ ++/* ++h006C h006C 15 0 reg_mb0_2C ++*/ ++ U16 reg_mb0_2C; ++ U16 u16REG_RESERVED_6c; ++ ++/* ++h006D h006D 15 0 reg_mb0_2D ++*/ ++ U16 reg_mb0_2D; ++ U16 u16REG_RESERVED_6d; ++ ++/* ++h006E h006E 15 0 reg_mb0_2E ++*/ ++ U16 reg_mb0_2E; ++ U16 u16REG_RESERVED_6e; ++ ++/* ++h006F h006F 15 0 reg_mb0_2F ++*/ ++ U16 reg_mb0_2F; ++ U16 u16REG_RESERVED_6f; ++ ++/* ++*/ ++}REG_MBX_st,*PREG_MBX_st; ++ ++ ++ ++ ++enum ++{ ++ BACK, ++ FORWARD, ++ DIR_NONE, ++ DIR_NUM = DIR_NONE, ++}; ++enum ++{ ++ NON_event = 0, ++ RTOS_event, ++ USER_event, ++ GOP_refresh_event, ++}; ++ ++enum ++{ ++ HK_PREPARE, ++ HK_START , ++ HK_ALIVE, ++ USR_OP_START, ++ USR_OP_BACK, ++ USR_OP_FORWARD, ++ ++}; ++ ++ ++#endif //__CEDRIC_QST__ +\ No newline at end of file +diff --git a/drivers/mstar/fb/chicago/gop/hal/gop_c2_reg.h b/drivers/mstar/fb/chicago/gop/hal/gop_c2_reg.h +new file mode 100644 +index 00000000..1d885407 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/hal/gop_c2_reg.h +@@ -0,0 +1,294 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME gop_c2_reg.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++ ++ ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define COLUMBUS_BASE_REG_RIU_PA (0x1F000000) ++#define CLKG0_REG_BASE_PA (0x100B00) ++ ++#define RIU_BASE (0xA0000000) ++ ++ ++#define CEDRIC_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080F80) ++#define CHICAGO_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x001A80) ++ ++ ++#if defined(CONFIG_ARCH_CHICAGO) ++#define mdrv_BASE_REG_GOP_PA CHICAGO_BASE_REG_GOP_PA ++#elif defined(CONFIG_ARCH_CEDRIC) ++#define mdrv_BASE_REG_GOP_PA CEDRIC_BASE_REG_GOP_PA ++#else ++#define mdrv_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080F80) // (0xA0006A00) ++#endif ++ ++#define mdrv_BASE_REG_CHIPTOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080580) ++ ++#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120200/2)) ++#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120300/2)) ++#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120400/2)) ++#define mdrv_BASE_REG_GOP10_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120500/2)) ++#define mdrv_BASE_REG_GOP11_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120600/2)) ++#define mdrv_BASE_REG_GOP12_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120700/2)) ++#define mdrv_BASE_REG_GOP20_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120800/2)) ++#define mdrv_BASE_REG_GOP21_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120900/2)) ++#define mdrv_BASE_REG_GOP22_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120A00/2)) ++#define mdrv_BASE_REG_GOP30_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120B00/2)) ++#define mdrv_BASE_REG_GOP31_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120C00/2)) ++#define mdrv_BASE_REG_GOP32_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x120D00/2)) ++ ++#define mdrv_REG_GOP31_7E GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x7E) ++#define mdrv_REG_GOP31_7F GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x7F) ++#define mdrv_REG_GOP01_WIN GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x00) ++#define mdrv_REG_GOP31_WIN GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x00) ++#define mdrv_REG_GOP01_ALPHA GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x0A) ++#define mdrv_REG_GOP01_7F GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x7F) ++#define mdrv_REG_GOP31_ALPHA GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x0A) ++ ++#define mdrv_GWin0_Disable (0xFFFE) ++#define mdrv_GWIN0_Enable (0x1) ++ ++#define mdrv_ENABLE_CONST_ALPHA (~(0x1<<14)) ++//fomrat define ++ ++#define RGB1555_Blink 0x0000 ++#define RGB565 0x0010 ++#define ARGB4444 0x0020 ++#define _2266 0x0030 ++#define _8Bit_Palette 0x0040 ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++#define RGBA8888 0x0050 ++#elif defined(CONFIG_ARCH_CHICAGO) ++#define ARGB8888 0x0050 ++#endif ++ ++#define ARGB1555 0x0060 ++ ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++#define ARGB8888 0x0070 ++#endif ++ ++#define RGB1555_UV7Y8 0x0080 ++#define UV8Y8 0x0090 ++#define RGBA5551 0x00A0 ++#define RGBA4444 0x00B0 ++ ++//------------------------------------------------------------------------------ ++// GOP ++//------------------------------------------------------------------------------ ++// Bank 0 ++// REG_GOP_00 ++#define GOP_SOFT_RESET 0x0001 ++#define GOP_VS_INV 0x0002 ++#define GOP_HS_INV 0x0004 ++#define GOP_DISPLAY_MODE 0x0008 ++#define GOP_FIELD_INV 0x0010 ++#define GOP_TEST_PATTENR_MODE 0x0040 ++#define GOP_5541_EN 0x0080 // RGB5541 alpha mask mode enable, only for RGB1555 Data type ++#define GOP_REG_OUTPUT_READY 0x0100 ++ ++#define GOP_GENSHOT_FAST 0x0200 ++#define GOP_YUVOUT 0x0400 ++#define GOP_RGB_Transparent_color_enable 0x0800 ++ ++#define GOP_HS_MASK 0x4000 ++#define GOP_ALPHA_INV 0x8000 ++ ++#define GOP_ALPHA_MASK 0x7F00 ++#define GOP_ALPHA 0x3F00 ++#define GOP_PIXEL_ALPHA_EN 0x4000 ++ ++#define GWIN_display_mode_progress 0x0008 ++#define GWIN_display_mode_interlace 0x0000 ++ ++ ++// REG_GOP_01 ++#define GOP_DST_IP_MAIN 0x0000 ++#define GOP_DST_IP_SUB 0x0001 ++#define GOP_DST_OP 0x0002 ++#define GOP_DST_MVOP 0x0003 ++#define GOP_DST_SC1_IP_MAIN 0x0004 ++#define GOP_DST_SC1_OP 0x0005 ++ ++ ++ ++#define GOP_DMA_LEN_8 0x0000 ++#define GOP_DMA_LEN_16 0x0004 ++#define GOP_DMA_LEN_32 0x0008 ++#define GOP_DMA_LEN_ALL 0x000C ++#define GOP_MIU_TSH_1 0x0010 ++#define GOP_REGDMA_INTERVAL_START 0x0300 ++#define GOP_REGDMA_INTERVAL_END 0x5000 ++ ++// REG_GOP_02 ++#define GOP_BLINK_DISABLE 0x0000 ++#define GOP_BLINK_ENABLE 0x8000 ++ ++// REG_GOP_06 ++#define GOP_REGDMA_END 0x0034 ++ ++// REG_GOP_07 ++#define GOP_REGDMA_STR 0x0000 ++ ++//REG_GOP_0F ++ ++ ++#define AMBER3_GOP_HSYNC_PIPE_DLY 0x00E5 ++#define CEDRIC_GOP_HSYNC_PIPE_DLY 0x0070 ++#define AMBER3_GOP_HSYNC_PIPE_DLY 0x00E5 ++#define CEDRIC_GOP_HSYNC_PIPE_DLY 0x0070 ++#define CHICAGO_GOP_HSYNC_PIPE_DLY 0x000B ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++#define GOP_HSYNC_PIPE_DLY_FOR_SC1_OP 0x00A0 ++#define HSYNC_PIPE_DLY_FOR_SC0_2GOP 0x0044 ++ ++ ++ ++#if defined(CONFIG_ARCH_CHICAGO) ++#define GOP_HSYNC_PIPE_DLY CHICAGO_GOP_HSYNC_PIPE_DLY ++#elif defined(CONFIG_ARCH_CEDRIC) ++#define GOP_HSYNC_PIPE_DLY CEDRIC_GOP_HSYNC_PIPE_DLY ++#else ++#define GOP_HSYNC_PIPE_DLY CEDRIC_GOP_HSYNC_PIPE_DLY ++#endif ++ ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++ ++// REG_GOP_20 ++#define GOP_GWIN_HIGH_PRI_0 0x0000 ++#define GOP_GWIN_HIGH_PRI_1 0x0001 ++ ++ ++ ++#define GOP_STRETCH_HST 0x0000 ++ ++ ++// REG_GOP_34 ++#define GOP_STRETCH_VST 0x0000 ++ ++// REG_GOP_35 ++#define GOP_STRETCH_HRATIO 0x1000 ++ ++// REG_GOP_36 ++#define GOP_STRETCH_VRATIO 0x1000 ++ ++// REG_GOP_38 ++#define GOP_STRETCH_HINI 0x0000 ++ ++// REG_GOP_39 ++#define GOP_STRETCH_VINI 0x0000 ++ ++// REG_GOP_7E ++#define GOP_GOPG0_MUX_MASK 0x0007 ++#define GOP_GOPG0_MUX_4G 0x0000 ++#define GOP_GOPG0_MUX_2G 0x0001 ++ ++#define GOP_Layer0_MUX_MASK 0x0007 ++#define GOP_Layer0_Sel_GOP0 0x0000 ++#define GOP_Layer0_Sel_GOP1 0x0001 ++#define GOP_Layer0_Sel_GOP2 0x0002 ++#define GOP_Layer0_Sel_GOP3 0x0003 ++#define GOP_Layer0_Sel_GOP_Null 0x0004 ++ ++#define GOP_Layer1_MUX_MASK (0x0007)<<3 ++#define GOP_Layer1_Sel_GOP0 (0x0000)<<3 ++#define GOP_Layer1_Sel_GOP1 (0x0001)<<3 ++#define GOP_Layer1_Sel_GOP2 (0x0002)<<3 ++#define GOP_Layer1_Sel_GOP3 (0x0003)<<3 ++#define GOP_Layer1_Sel_GOP_Null (0x0004)<<3 ++ ++#define GOP_Layer2_MUX_MASK (0x0007)<<6 ++#define GOP_Layer2_Sel_GOP0 (0x0000)<<6 ++#define GOP_Layer2_Sel_GOP1 (0x0001)<<6 ++#define GOP_Layer2_Sel_GOP2 (0x0002)<<6 ++#define GOP_Layer2_Sel_GOP3 (0x0003)<<6 ++#define GOP_Layer2_Sel_GOP_Null (0x0004)<<6 ++ ++#define GOP_Layer3_MUX_MASK (0x0007)<<9 ++#define GOP_Layer3_Sel_GOP0 (0x0000)<<9 ++#define GOP_Layer3_Sel_GOP1 (0x0001)<<9 ++#define GOP_Layer3_Sel_GOP2 (0x0002)<<9 ++#define GOP_Layer3_Sel_GOP3 (0x0003)<<9 ++#define GOP_Layer3_Sel_GOP_Null (0x0004)<<9 ++ ++ ++ ++ ++ ++// REG_GOP_7F ++#define GOP_BANK_G0_0 0x0000 ++#define GOP_BANK_G0_1 0x0001 ++#define GOP_BANK_G1_0 0x0003 ++#define GOP_BANK_G1_1 0x0004 ++#define GOP_BANK_G2_0 0x0006 ++#define GOP_BANK_G2_1 0x0007 ++#define GOP_BANK_G3_0 0x0009 ++#define GOP_BANK_G3_1 0x000A ++#define GOP_BANK_GPD 0x0006 ++ ++#define GOP_BANK_DOUBLE_WR 0x0100 ++#define GOP_BANK_FORCE_WR 0x0200 ++ ++#define GOP_BANK_DOUBLE_WR_G0 0x0400 ++#define GOP_BANK_DOUBLE_WR_G1 0x0403 ++#define GOP_BANK_DOUBLE_WR_G2 0x0406 ++#define GOP_BANK_DOUBLE_WR_G3 0x0409 ++#define GOP_BANK_DOUBLE_WR_MSK 0x0400 ++#define GOP_BANK_SEL_MSK 0x000F ++// GOP0 Bank 1 ++// REG_GOP_00 ++#define GOP0_GWin0_Enable 0x0001 ++ ++// REG_GOP_20 ++#define GOP0_GWin1_Enable 0x0001 ++ ++ ++ ++ ++// Chip Device ID ++#define DEVICE_COLUMBUS2 (0x2E) ++#define DEVICE_AMBER3 (0x47) ++#define DEVICE_CEDRIC (0x50) ++#define DEVICE_CHICAGO (0x70) ++ ++ +diff --git a/drivers/mstar/fb/chicago/gop/hal/platform.h b/drivers/mstar/fb/chicago/gop/hal/platform.h +new file mode 100644 +index 00000000..e04d58fd +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/hal/platform.h +@@ -0,0 +1,189 @@ ++#ifndef __PLATFORM_H__ ++#define __PLATFORM_H__ ++ ++//------------------------------------------------------------------------------ ++// Include Files ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Macros ++//------------------------------------------------------------------------------ ++#define MIU0_BUS_ADDR 0x40000000 ++#define MIU1_MASK 0x00000000 //use (ADDR & MIU1_MASK) to check if ADDR is in MIU1 after calling ms_mem_bus_to_MIU() ++ ++ ++#define IO_PHYS 0x1F000000 ++#define IO_OFFSET 0xDE000000 ++#define IO_SIZE 0x00400000 ++#define IO_VIRT (IO_PHYS + IO_OFFSET) ++#define io_p2v(pa) ((pa) + IO_OFFSET) ++#define io_v2p(va) ((va) - IO_OFFSET) ++//#define IO_ADDRESS(x) io_p2v((unsigned int)x) ++ ++ ++#define PERI_PHYS 0x16000000 ++#define PERI_OFFSET 0xE6000000 ++#define PERI_SIZE 0x2000 ++#define PERI_VIRT (PERI_PHYS + PERI_OFFSET) ++#define peri_p2v(pa) ((pa) + PERI_OFFSET) ++#define peri_v2p(va) ((va) - PERI_OFFSET) ++#define PERI_ADDRESS(x) peri_p2v(x) ++ ++#define PERI_W(a,v) (*(volatile unsigned int *)PERI_ADDRESS(a)=v) ++#define PERI_R(a) (*(volatile unsigned int *)PERI_ADDRESS(a)) ++ ++#define SCU_PHYS (PERI_PHYS) ++ ++#define L2_CACHE_PHYS 0x15000000 ++#define L2_CACHE_OFFSET 0xE7003000 ++#define L2_CACHE_SIZE 0x1000 ++#define L2_CACHE_VIRT (L2_CACHE_PHYS + L2_CACHE_OFFSET) ++#define L2_CACHE_p2v(pa) ((pa) + L2_CACHE_OFFSET) ++#define L2_CACHE_v2p(va) ((va) - L2_CACHE_OFFSET) ++#define L2_CACHE_ADDRESS(x) L2_CACHE_p2v(x) ++ ++#define L2_CACHE_write(v,a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a) = (v)) ++#define L2_CACHE_read(a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a)) ++ ++ ++#define IMI_PHYS 0xE0000000 ++#define IMI_OFFSET 0x1C005000 ++#define IMI_SIZE 0x50000 ++#define IMI_VIRT (IMI_PHYS + IMI_OFFSET) ++#define imi_p2v(pa) ((pa) + IMI_OFFSET) ++#define imi_v2p(va) ((va) - IMI_OFFSET) ++#define IMI_ADDRESS(x) imi_p2v((unsigned int)x) ++ ++ ++ ++ ++// Register macros ++#define GET_REG_ADDR(x, y) ((x) + ((y) << 2)) ++ ++ ++/* read register by byte */ ++#define ms_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) ++ ++/* read register by word */ ++#define ms_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++ ++/* read register by long */ ++#define ms_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) ++ ++/* write register by byte */ ++#define ms_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) ++ ++/* write register by word */ ++#define ms_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++ ++/* write register by long */ ++#define ms_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Macros: INREGx/OUTREGx/SETREGx/CLRREGx ++// ++// This macros encapsulates basic I/O operations. ++// Memory address space operation is used on all platforms. ++// ++#define INREG8(x) ms_readb(x) ++#define OUTREG8(x, y) ms_writeb((u8)(y), x) ++#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y)) ++#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y)) ++#define INREGMSK8(x, y) (INREG8(x) & (y)) ++#define OUTREGMSK8(x, y, z) OUTREG8(x, ((INREG8(x)&~(z))|((y)&(z)))) ++ ++#define INREG16(x) ms_readw(x) ++#define OUTREG16(x, y) ms_writew((u16)(y), x) ++#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) ++#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) ++#define INREGMSK16(x, y) (INREG16(x) & (y)) ++#define OUTREGMSK16(x, y, z) OUTREG16(x, ((INREG16(x)&~(z))|((y)&(z)))) ++ ++#define INREG32(x) ms_readl(x) ++#define OUTREG32(x, y) ms_writel((u32)(y), x) ++#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y)) ++#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y)) ++#define INREGMSK32(x, y) (INREG32(x) & (y)) ++#define OUTREGMSK32(x, y, z) OUTREG32(x, ((INREG32(x)&~(z))|((y)&(z)))) ++ ++ ++#define PM_READ32(x) ((((unsigned int)INREG16(x+4)<<16)&0xFFFF0000) | (INREG16(x) & 0x0000FFFF)) ++#define PM_WRITE32(x,y) do{OUTREG16(x,(y&0x0000FFFF));OUTREG16((x+4),((y>>16)&0x0000FFFF));}while(0) ++ ++#define XTAL_26000K 26000000 ++#define XTAL_24000K 24000000 ++#define XTAL_16369K 16369000 ++#define XTAL_16367K 16367000 ++ ++#define CPU_ID_CORE0 0x0 ++#define CPU_ID_CORE1 0x1 ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Define: MSBASE_REG_RIU_PA ++// ++// Locates the RIU register base. ++// ++#define MS_BASE_REG_RIU_PA IO_PHYS ++ ++ ++ ++extern unsigned long long ms_mem_bus_to_phys(unsigned long long x); ++extern unsigned long long ms_mem_phys_to_bus(unsigned long long x); ++extern unsigned long long ms_mem_bus_to_MIU(unsigned long long x); ++extern unsigned long long ms_mem_MIU_to_bus(unsigned long long x); ++ ++typedef enum ++{ ++ DEVINFO_BOOT_TYPE_SPI=0x01, ++ DEVINFO_BOOT_TYPE_EMMC=0x02, ++ DEVINFO_BOOT_TYPE_8051=0x03, ++}DEVINFO_BOOT_TYPE; ++ ++typedef enum ++{ ++ DEVINFO_PANEL_070_DEFAULT = 0x0, ++ DEVINFO_PANEL_HSD_070I_DW1 = 0x01, ++ DEVINFO_PANEL_HSD_070P_FW3 = 0x02, ++ DEVINFO_PANEL_AT_102_03TT91 = 0x03, ++ DEVINFO_PANEL_HSD_062I_DW1 = 0x04, ++ DEVINFO_PANEL_HSD_070I_DW2 = 0x05, ++ DEVINFO_PANEL_HSD_LVDS_800480= 0x06, ++ DEVINFO_PANEL_N070ICG_LD1 =0x08, ++ DEVINFO_PANEL_HSD_062I_DW2 = 0x09, ++ DEVINFO_PANEL_HSD_070I_MODE2 = 0x0a, ++ E_PANEL_UNKNOWN = 0xFF ++}DEVINFO_PANEL_TYPE; ++ ++ ++typedef enum ++{ ++ DEVINFO_BD_MST154A_D01A_S = 0x0801, ++ DEVINFO_BD_MST786_SZDEMO = 0x0802, ++ DEVINFO_BD_MST786_CUSTOM10 = 0x0810, ++ DEVINFO_BD_MST786_CUSTOM20 = 0x0820, ++ DEVINFO_BD_MST786_CUSTOM30 = 0x0830, ++ E_BD_UNKNOWN = 0xFFFF ++}DEVINFO_BOARD_TYPE; ++ ++typedef enum ++{ ++ DEVINFO_RTK_FLAG_0 = 0x0, ++ DEVINFO_RTK_FLAG_1 = 0x01, ++ E_RTK_UNKNOWN = 0xFFFF ++}DEVINFO_RTK_FLAG; ++ ++typedef struct ++{ ++ char name[16]; ++ unsigned long start; //MIU Address ++ unsigned long length; ++ unsigned long flag0; ++ unsigned long flag1; //Kernel Virtual Address ++} MS_MEM_INFO; ++ ++ ++#endif +diff --git a/drivers/mstar/fb/chicago/gop/mdrv_gop.c b/drivers/mstar/fb/chicago/gop/mdrv_gop.c +new file mode 100644 +index 00000000..659ed9cd +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/mdrv_gop.c +@@ -0,0 +1,845 @@ ++ ++#include "mdrv_gop.h" ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++#include ++static volatile PREG_MBX_st sg_pMbxRegs = NULL; ++extern DEVINFO_RTK_FLAG ms_devinfo_rtk_flag(void); ++#endif ++U32 OALReadDeviceId(U32 devId) ++{ ++ U16 tmp = 0; ++ // need to refine for another SOC ++#if defined(CONFIG_ARCH_CHICAGO) ++ tmp = 0x70; //C4 ++#elif defined(CONFIG_ARCH_CEDRIC) ++ tmp = 0x50; //C3 ++#else ++ tmp = 0x50; //C3 ++#endif ++ return tmp; ++} ++ ++ ++ ++ ++U16 GOP_MIU_BUS(U16 MIU_BUS) ++{ ++ // A3: MIU Bus = 0x5; ++ // C2: MIU Bus = 0x3; ++ // C3: MIU Bus = 0x4; ++ // C4: MIU Bus = 0x3; ++ // Need to check with HW team ++ ++ U32 devId=0; ++ ++ devId=OALReadDeviceId(devId); ++ ++ if(DEVICE_AMBER3==devId) ++ { ++ GOPDBG("***** devId is AMBER3 *****\r\n"); ++ MIU_BUS = 5; ++ } ++ else if(DEVICE_CEDRIC==devId) ++ { ++ GOPDBG("***** devId is CEDRIC *****\r\n"); ++ MIU_BUS = 0x4; ++ } ++ else if(DEVICE_CHICAGO==devId) ++ { ++ GOPDBG("***** devId is DEVICE_CHICAGO *****\r\n"); ++ MIU_BUS = 0x3; ++ } ++ else ++ { ++ GOPDBG("***** devId UNKNOWN *****\r\n"); ++ MIU_BUS = 0x4; ++ ++ } ++ ++ GOPDBG("GOP_MIU_BUS devId is %d BUS is %d \n",devId,MIU_BUS); ++ ++ ++ return MIU_BUS; ++} ++ ++ ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr ) ++{ ++ ++ U32 FB_add = FB_Start_Addr; ++ ++ U32 s32BuffAddr=0; ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = Screen == 0 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F, (Screen == 0 ? GOP_BANK_G0_1 : GOP_BANK_G1_1)); ++#endif ++ ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ ++ GOPDBG ("GOP_Pan_Display: in \r\n"); ++ ++ // 1 GOP fetch framebuffer information ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ GOPDBG ("GOP_Pan_Display: out \r\n"); ++} ++ ++void GOP_Change_Alpha(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ //U16 FB_WIDTH=Panel_Width; ++ //U16 FB_HEIGHT=Panel_Height; ++ ++ ++ //U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ //U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ //U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ //U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ //U16 u16DispImage_HStart=0; ++ //U16 u16DispImage_HSize=FB_WIDTH; ++ //U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ //U16 u16DispImage_VStart=000; ++ //U16 u16DispImage_VSize=FB_HEIGHT; ++ //U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ //U32 s32BuffAddr=0; ++ //U32 u32TempVal=0; ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ //U16 DISPLAY_Format=Pixel_Format; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = Screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F, (Screen == 0 ? GOP_BANK_G0_0 : GOP_BANK_G1_0)); // Change to bank GOP2G_0 ++#endif ++ ++ if (Screen == 0) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ } ++ else if (Screen == 1) ++ { ++ OUTREG16(mdrv_BASE_REG_CHIPTOP_PA+BK_REG(0x40), 0x1000); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV|GOP_ALPHA); // constant alpha 0x3F, RGB565, enable ++ if(bInterlaceOut) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_interlace|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ else ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_SC1_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY_FOR_SC1_OP);//Hsync input pipe delay ++ } ++ ++ ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Setmode( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ ++ ++ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart=0; ++ U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart=000; ++ U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 MIU_BUS=0x04; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ sg_pMbxRegs = (PREG_MBX_st)IO_ADDRESS(REG_MBX_BASE); ++#endif ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ if (Screen == 0) ++ { ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ } ++ else if (Screen == 1) ++ { ++ GOP_block_0=GOP_BANK_G1_0; ++ GOP_block_1=GOP_BANK_G1_1; ++ } ++ ++ GOPDBG ("GOP_Setmode: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ ++ ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = GOP_block_0 == GOP_BANK_G0_0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,GOP_block_0); ++#endif ++ ++ // GOP Global seting ; destination, Hsync ++ if (Screen == 0) ++ { ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ ++#elif defined(CONFIG_ARCH_CHICAGO) ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_DISPLAY_MODE| GOP_GENSHOT_FAST|GOP_HS_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_DISPLAY_MODE| GWIN_display_mode_progress| GOP_GENSHOT_FAST|GOP_HS_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_DMA_LEN_16| GOP_MIU_TSH_1| GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ OUTREG16(GOP_Reg_Base+REG_GOP_20,GOP_GWIN_HIGH_PRI_0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width+0x10)>>1); // RDMA H total (unit: 2 pixels) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++#endif ++ ++ } ++ else if (Screen == 1) ++ { ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ OUTREG16(mdrv_BASE_REG_CHIPTOP_PA+BK_REG(0x40), 0x1000); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV|GOP_ALPHA); // constant alpha 0x3F, RGB565, enable ++ if(bInterlaceOut) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_interlace|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ else ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_SC1_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY_FOR_SC1_OP);//Hsync input pipe delay ++#endif ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); // Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); // Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = GOP_block_1 == GOP_BANK_G0_1 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ // GOP Global seting ; destination, Hsync ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,GOP_block_1); // Change to bank GOP2G_1 ++#endif ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ ++ if (Screen == 0) ++ { ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ //normal ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP0); ++ } ++ else ++ { ++ OUTREG16(mdrv_REG_GOP01_WIN, INREG16(mdrv_REG_GOP01_WIN) & mdrv_GWin0_Disable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP3); ++ } ++ ++#elif defined(CONFIG_ARCH_CHICAGO) ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,(GOP_GOPG0_MUX_2G<<2)|GOP_GOPG0_MUX_4G); ++ ++#endif ++ } ++ else if (Screen == 1) ++ { ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK|GOP_Layer3_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++ else ++ { ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ // OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++#endif ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++ ++void GOP_Set_OutFormat(int screen, int byuvoutput) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, (screen == 0 ? GOP_BANK_G0_0 : GOP_BANK_G1_0), 0x000F); // Change to bank GOP2G_0 ++#endif ++ ++ GOPDBG("GOP_Set_OutFormat: screen:%d, byuvoutput:%d\n", screen, byuvoutput); ++ ++ if(byuvoutput) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_YUVOUT, GOP_YUVOUT); ++ ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP_YUVOUT); ++ } ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++} ++ ++ ++ ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetConstatnAlpha: screen:%d, bEn:%d, alpha:%x\n", screen, bEn, alpha); ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, (screen == 0 ? GOP_BANK_G0_0 : GOP_BANK_G1_0), 0x000F); // Change to bank GOP2G_0 ++#endif ++ ++ // alpha inv ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : 0x8000), 0x8000); ++ ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, (screen == 0 ? GOP_BANK_G0_1 : GOP_BANK_G1_1), 0x000F); // Change to bank GOP2G_0 ++#endif ++ ++ ++ // constant or pixel alpha ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : 0x4000), 0x4000); ++ ++ // alhap value ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_0A, (bEn ? alpha : 0x0000), 0x00FF); ++ ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ ++} ++ ++ ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetColorKey: screen:%d, bEn:%d, (%x %x %x)\n", screen, bEn, u8R, u8G, u8B); ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP01_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, (screen == 0 ? GOP_BANK_G0_0 : GOP_BANK_G0_1), 0x000F); // Change to bank GOP2G_0 ++#endif ++ ++ if(bEn) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0800, 0x0800); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_24, (u8B|(u8G<<8)), 0xFFFF); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_25, u8R, 0x00FF); ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0000, 0x0800); ++ } ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++void GOP_Set_PipeDelay(int screen, int delay) ++{ ++ U16 pipe_delay = 0x00; ++ ++ U32 GOP_Reg_Base; ++ ++ U16 GOP_Reg_DB; ++ ++ ++ GOP_Reg_DB = screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = screen == 0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F,(screen == 0 ? GOP_BANK_G0_0 : GOP_BANK_G1_0), 0x000F); // Change to bank GOP2G_0 ++#endif ++ ++ if (screen == 0) ++ { ++ pipe_delay = 0x50 + delay; ++ } ++ else if (screen == 1) ++ { ++ pipe_delay = 0x2E + delay; ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F, pipe_delay); ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++} ++ ++ ++void GOP_Setmode_and_win( ++ int bResume, int Screen, ++ int H_Start, int V_Start, ++ int H_End, int V_End, ++ int Panel_Width, int Panel_Height, ++ U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, ++ int bInterlaceOut) ++{ ++ ++ ++ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart= H_Start; ++ //U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd= H_End; //u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart= bInterlaceOut ? V_Start/2 : V_Start; ++ //U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd= bInterlaceOut ? V_End/2 : V_End; //u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ FB_add = (U32)ms_mem_bus_to_MIU(FB_add); ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ sg_pMbxRegs = (PREG_MBX_st)IO_ADDRESS(REG_MBX_BASE); ++#endif ++ ++ GOPDBG("screen:%d, pixel_format:%d, binter:%d\n", Screen, Pixel_Format, bInterlaceOut); ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ if (Screen == 0) ++ { ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ } ++ else if (Screen == 1) ++ { ++ GOP_block_0=GOP_BANK_G1_0; ++ GOP_block_1=GOP_BANK_G1_1; ++ } ++ ++ GOPDBG ("GOP_Setmode: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = GOP_block_0 == GOP_BANK_G0_0 ? mdrv_BASE_REG_GOP00_PA : mdrv_BASE_REG_GOP10_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F,GOP_block_0, 0x000F); ++#endif ++ ++ if (Screen == 0) ++ { ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ ++#elif defined(CONFIG_ARCH_CHICAGO) ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_DISPLAY_MODE| GOP_GENSHOT_FAST|GOP_HS_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_DISPLAY_MODE| GWIN_display_mode_progress| GOP_GENSHOT_FAST|GOP_HS_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_DMA_LEN_16| GOP_MIU_TSH_1| GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ OUTREG16(GOP_Reg_Base+REG_GOP_20,GOP_GWIN_HIGH_PRI_0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width+0x10)>>1); // RDMA H total (unit: 2 pixels) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++#endif ++ ++ } ++ else if (Screen == 1) ++ { ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ OUTREG16(mdrv_BASE_REG_CHIPTOP_PA+BK_REG(0x40), 0x1000); ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV|GOP_ALPHA); // constant alpha 0x3F, RGB565, enable ++ if(bInterlaceOut) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_interlace|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ else ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_YUVOUT|GOP_FIELD_INV|GOP_ALPHA_INV); ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_SC1_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY_FOR_SC1_OP);//Hsync input pipe delay ++#endif ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST);// Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); // Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++#if defined(CONFIG_ARCH_CEDRIC) ++ GOP_Reg_Base = GOP_block_1 == GOP_BANK_G0_1 ? mdrv_BASE_REG_GOP01_PA : mdrv_BASE_REG_GOP11_PA; ++#elif defined(CONFIG_ARCH_CHICAGO) ++ GOP_Reg_Base = mdrv_BASE_REG_GOP_PA; ++ // GOP Global seting ; destination, Hsync ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_block_1, 0x000F); // Change to bank GOP2G_1 ++#endif ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ ++ if (Screen == 0) ++ { ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ //normal ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP0); ++ } ++ else ++ { ++ OUTREG16(mdrv_REG_GOP01_WIN, INREG16(mdrv_REG_GOP01_WIN) & mdrv_GWin0_Disable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP3); ++ } ++ ++#elif defined(CONFIG_ARCH_CHICAGO) ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,(GOP_GOPG0_MUX_2G<<2)|GOP_GOPG0_MUX_4G); ++ ++#endif ++ } ++ else if (Screen == 1) ++ { ++#if defined(CONFIG_ARCH_CEDRIC) ++ ++ if (bResume || ((sg_pMbxRegs->carbacking_status || DEVINFO_RTK_FLAG_0 == ms_devinfo_rtk_flag()) && (!sg_pMbxRegs->mmi_task_running || sg_pMbxRegs->Os_flag))) ++ { ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK|GOP_Layer3_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++ else ++ { ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) | mdrv_GWIN0_Enable) ; ++ // OUTREG16(mdrv_REG_GOP31_WIN, INREG16(mdrv_REG_GOP31_WIN) & mdrv_ENABLE_CONST_ALPHA ); ++ // OUTREG16(mdrv_REG_GOP31_ALPHA, (INREG16(mdrv_REG_GOP31_ALPHA) & (0xFF00)) |(0x80)); ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_MUX_MASK); ++ SETREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer2_Sel_GOP1); ++ } ++#endif ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ ++} ++//MODULE_LICENSE("GPL") +diff --git a/drivers/mstar/fb/chicago/gop/mdrv_gop.h b/drivers/mstar/fb/chicago/gop/mdrv_gop.h +new file mode 100644 +index 00000000..4cc11db4 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/mdrv_gop.h +@@ -0,0 +1,265 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_gop.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++ ++#include "hal/gop_c2_reg.h" ++ ++ ++#define CHIPTOP_REG_BASE_PA (0x101E00) ++#define SC_REG_BASE_PA (0x130000) ++#define LPLL_REG_BASE_PA (0x103100) ++#define CLKG0_REG_BASE_PA (0x100B00) ++#define MOD_REG_BASE_PA (0x103200) ++#define GPIO0_REG_BASE_PA (0x102B00) ++#define GPIO1_REG_BASE_PA (0x101A00) ++ ++#define GOP_DEBUG 0 ++#if (GOP_DEBUG==1) ++#define GOPDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOPDBG(fmt, arg...) ++#endif ++ ++ ++//#define GOPIO_DEBUG_ENABLE ++ ++#define GOP_DBG_LV_IOCTL 0 ++#define GOP_DBG_LV_0 1 ++ ++ ++#ifdef GOPIO_DEBUG_ENABLE ++#define GOPIO_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define GOP_DBG(dbglv, _fmt, _args...) \ ++ do \ ++ if(dbglv) \ ++ { \ ++ printk(KERN_WARNING _fmt, ## _args); \ ++ }while(0) ++ ++#else ++#define GOPIO_ASSERT(arg) ++#define GOP_DBG(dbglv, _fmt, _args...) ++ ++#endif ++ ++#define BK_REG(reg) ((reg) * 4) ++ ++/* ---------------------------------------------------------------------------- ++ * GOP_OFFSET ++ * ---------------------------------------------------------------------------- ++ */ ++#define REG_GOP_00 BK_REG(0x00) ++#define REG_GOP_01 BK_REG(0x01) ++#define REG_GOP_02 BK_REG(0x02) ++#define REG_GOP_03 BK_REG(0x03) ++#define REG_GOP_04 BK_REG(0x04) ++#define REG_GOP_05 BK_REG(0x05) ++#define REG_GOP_06 BK_REG(0x06) ++#define REG_GOP_07 BK_REG(0x07) ++#define REG_GOP_08 BK_REG(0x08) ++#define REG_GOP_09 BK_REG(0x09) ++#define REG_GOP_0A BK_REG(0x0A) ++#define REG_GOP_0B BK_REG(0x0B) ++#define REG_GOP_0C BK_REG(0x0C) ++#define REG_GOP_0D BK_REG(0x0D) ++#define REG_GOP_0E BK_REG(0x0E) ++#define REG_GOP_0F BK_REG(0x0F) ++ ++ ++#define REG_GOP_10 BK_REG(0x10) ++#define REG_GOP_11 BK_REG(0x11) ++#define REG_GOP_12 BK_REG(0x12) ++#define REG_GOP_13 BK_REG(0x13) ++#define REG_GOP_14 BK_REG(0x14) ++#define REG_GOP_15 BK_REG(0x15) ++#define REG_GOP_16 BK_REG(0x16) ++#define REG_GOP_17 BK_REG(0x17) ++#define REG_GOP_18 BK_REG(0x18) ++#define REG_GOP_19 BK_REG(0x19) ++#define REG_GOP_1A BK_REG(0x1A) ++#define REG_GOP_1B BK_REG(0x1B) ++#define REG_GOP_1C BK_REG(0x1C) ++#define REG_GOP_1D BK_REG(0x1D) ++#define REG_GOP_1E BK_REG(0x1E) ++#define REG_GOP_1F BK_REG(0x1F) ++ ++#define REG_GOP_20 BK_REG(0x20) ++#define REG_GOP_21 BK_REG(0x21) ++#define REG_GOP_22 BK_REG(0x22) ++#define REG_GOP_23 BK_REG(0x23) ++#define REG_GOP_24 BK_REG(0x24) ++#define REG_GOP_25 BK_REG(0x25) ++#define REG_GOP_26 BK_REG(0x26) ++#define REG_GOP_27 BK_REG(0x27) ++#define REG_GOP_28 BK_REG(0x28) ++#define REG_GOP_29 BK_REG(0x29) ++#define REG_GOP_2A BK_REG(0x2A) ++#define REG_GOP_2B BK_REG(0x2B) ++#define REG_GOP_2C BK_REG(0x2C) ++#define REG_GOP_2D BK_REG(0x2D) ++#define REG_GOP_2E BK_REG(0x2E) ++#define REG_GOP_2F BK_REG(0x2F) ++ ++ ++#define REG_GOP_30 BK_REG(0x30) ++#define REG_GOP_31 BK_REG(0x31) ++#define REG_GOP_32 BK_REG(0x32) ++#define REG_GOP_33 BK_REG(0x33) ++#define REG_GOP_34 BK_REG(0x34) ++#define REG_GOP_35 BK_REG(0x35) ++#define REG_GOP_36 BK_REG(0x36) ++#define REG_GOP_37 BK_REG(0x37) ++#define REG_GOP_38 BK_REG(0x38) ++#define REG_GOP_39 BK_REG(0x39) ++#define REG_GOP_3A BK_REG(0x3A) ++#define REG_GOP_3B BK_REG(0x3B) ++#define REG_GOP_3C BK_REG(0x3C) ++#define REG_GOP_3D BK_REG(0x3D) ++#define REG_GOP_3E BK_REG(0x3E) ++#define REG_GOP_3F BK_REG(0x3F) ++ ++ ++#define REG_GOP_40 BK_REG(0x40) ++#define REG_GOP_41 BK_REG(0x41) ++#define REG_GOP_42 BK_REG(0x42) ++#define REG_GOP_43 BK_REG(0x43) ++#define REG_GOP_44 BK_REG(0x44) ++#define REG_GOP_45 BK_REG(0x45) ++#define REG_GOP_46 BK_REG(0x46) ++#define REG_GOP_47 BK_REG(0x47) ++#define REG_GOP_48 BK_REG(0x48) ++#define REG_GOP_49 BK_REG(0x49) ++#define REG_GOP_4A BK_REG(0x4A) ++#define REG_GOP_4B BK_REG(0x4B) ++#define REG_GOP_4C BK_REG(0x4C) ++#define REG_GOP_4D BK_REG(0x4D) ++#define REG_GOP_4E BK_REG(0x4E) ++#define REG_GOP_4F BK_REG(0x4F) ++ ++ ++#define REG_GOP_50 BK_REG(0x50) ++#define REG_GOP_51 BK_REG(0x51) ++#define REG_GOP_52 BK_REG(0x52) ++#define REG_GOP_53 BK_REG(0x53) ++#define REG_GOP_54 BK_REG(0x54) ++#define REG_GOP_55 BK_REG(0x55) ++#define REG_GOP_56 BK_REG(0x56) ++#define REG_GOP_57 BK_REG(0x57) ++#define REG_GOP_58 BK_REG(0x58) ++#define REG_GOP_59 BK_REG(0x59) ++#define REG_GOP_5A BK_REG(0x5A) ++#define REG_GOP_5B BK_REG(0x5B) ++#define REG_GOP_5C BK_REG(0x5C) ++#define REG_GOP_5D BK_REG(0x5D) ++#define REG_GOP_5E BK_REG(0x5E) ++#define REG_GOP_5F BK_REG(0x5F) ++ ++ ++#define REG_GOP_60 BK_REG(0x60) ++#define REG_GOP_61 BK_REG(0x61) ++#define REG_GOP_62 BK_REG(0x62) ++#define REG_GOP_63 BK_REG(0x63) ++#define REG_GOP_64 BK_REG(0x64) ++#define REG_GOP_65 BK_REG(0x65) ++#define REG_GOP_66 BK_REG(0x66) ++#define REG_GOP_67 BK_REG(0x67) ++#define REG_GOP_68 BK_REG(0x68) ++#define REG_GOP_69 BK_REG(0x69) ++#define REG_GOP_6A BK_REG(0x6A) ++#define REG_GOP_6B BK_REG(0x6B) ++#define REG_GOP_6C BK_REG(0x6C) ++#define REG_GOP_6D BK_REG(0x6D) ++#define REG_GOP_6E BK_REG(0x6E) ++#define REG_GOP_6F BK_REG(0x6F) ++ ++ ++#define REG_GOP_70 BK_REG(0x70) ++#define REG_GOP_71 BK_REG(0x71) ++#define REG_GOP_72 BK_REG(0x72) ++#define REG_GOP_73 BK_REG(0x73) ++#define REG_GOP_74 BK_REG(0x74) ++#define REG_GOP_75 BK_REG(0x75) ++#define REG_GOP_76 BK_REG(0x76) ++#define REG_GOP_77 BK_REG(0x77) ++#define REG_GOP_78 BK_REG(0x78) ++#define REG_GOP_79 BK_REG(0x79) ++#define REG_GOP_7A BK_REG(0x7A) ++#define REG_GOP_7B BK_REG(0x7B) ++#define REG_GOP_7C BK_REG(0x7C) ++#define REG_GOP_7D BK_REG(0x7D) ++#define REG_GOP_7E BK_REG(0x7E) ++#define REG_GOP_7F BK_REG(0x7F) ++ ++void GOP_Setmode(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++void GOP_Change_Alpha(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr); ++void GOP_Set_OutFormat(int screen, int byuvoutput); ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha); ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B); ++void GOP_Set_PipeDelay(int screen, int delay); ++void GOP_Setmode_and_win(int bResume, int Screen, int H_Start, int V_Start, int H_End, int V_End, int Panel_Width, int Panel_Height, U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++ ++ ++ ++ +diff --git a/drivers/mstar/fb/chicago/gop/mdrv_gop_io.c b/drivers/mstar/fb/chicago/gop/mdrv_gop_io.c +new file mode 100644 +index 00000000..26eef6d5 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/mdrv_gop_io.c +@@ -0,0 +1,415 @@ ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_gop.h" ++#include "mdrv_gop_io.h" ++ ++#define MDRV_GOP_DEVICE_COUNT 1 ++#define MDRV_GOP_NAME "mstar_gop" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_GOP "mstar_gop" ++#define MDRV_MAJOR_GOP 0xea ++#define MDRV_MINOR_GOP 0x01 ++ ++ ++int mstar_gop_drv_open(struct inode *inode, struct file *filp); ++int mstar_gop_drv_release(struct inode *inode, struct file *filp); ++long mstar_gop_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mstar_gop_drv_probe(struct platform_device *pdev); ++static int mstar_gop_drv_remove(struct platform_device *pdev); ++static int mstar_gop_drv_suspend(struct platform_device *dev, pm_message_t state); ++static int mstar_gop_drv_resume(struct platform_device *dev); ++static void mstar_gop_drv_platfrom_release(struct device *device); ++#if defined (CONFIG_ARCH_CEDRIC) ++extern int mstar_sca_drv_get_h_backporch(int sc_num); ++#endif ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++}GOP_DEV; ++ ++static GOP_DEV _devGOP = ++{ ++ .s32Major = MDRV_MAJOR_GOP, ++ .s32Minor = MDRV_MINOR_GOP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_GOP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mstar_gop_drv_open, ++ .release = mstar_gop_drv_release, ++ .unlocked_ioctl = mstar_gop_drv_ioctl, ++ } ++}; ++ ++static struct class * gop_class; ++static char * gop_classname = "mstar_gop_class"; ++ ++ ++static struct platform_driver Mstar_gop_driver = { ++ .probe = mstar_gop_drv_probe, ++ .remove = mstar_gop_drv_remove, ++ .suspend = mstar_gop_drv_suspend, ++ .resume = mstar_gop_drv_resume, ++ ++ .driver = { ++ .name = "mstar_gop", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static u64 sg_mstar_device_gop_dmamask = 0xffffffffUL; ++ ++static struct platform_device sg_mdrv_gop_device = ++{ ++ .name = "mstar_gop", ++ .id = 0, ++ .dev = ++ { ++ .release = mstar_gop_drv_platfrom_release, ++ .dma_mask = &sg_mstar_device_gop_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_GOPIO_IOC_Set_BaseAddr(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_BASE_ADDR_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (GOP_SET_BASE_ADDR_CONFIG __user *)arg, sizeof(GOP_SET_BASE_ADDR_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetBase: GOP_%d, Base=%x, \n", stCfg.enGopNum, (int)stCfg.u32Base); ++ ++ GOP_Pan_Display(stCfg.enGopNum, stCfg.u32Base); ++ ++ ++ return 0; ++} ++ ++int _MDrv_GOPIO_IOC_SetMode(struct file *filp, unsigned long arg) ++{ ++ GOP_SETMODE_CONFIG stCfg; ++ int Pixel_Format, Bytes_Per_Pixel; ++ if(copy_from_user(&stCfg, (GOP_SETMODE_CONFIG __user *)arg, sizeof(GOP_SETMODE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetMode: GOP_%d, (%d, %d) FM=%d, Base=%x, interlace=%d, yuv=%d,\n", ++ stCfg.enGopNum, stCfg.u16width, stCfg.u16height, stCfg.enSrcFormat, (int)stCfg.u32BaseAddr, stCfg.bInterlace, stCfg.bYUVOutput); ++ ++ switch(stCfg.enSrcFormat) ++ { ++ case E_GOP_SRC_RGB565: ++ Pixel_Format = 0x0010; ++ Bytes_Per_Pixel = 2; ++ break; ++ ++ case E_GOP_SRC_ARGB8888: ++ Pixel_Format = 0x0050; ++ Bytes_Per_Pixel = 4; ++ break; ++ ++ case E_GOP_SRC_ABGR8888: ++ Pixel_Format = 0x0070; ++ Bytes_Per_Pixel = 4; ++ break; ++ ++ } ++ ++ ++ GOP_Setmode(FALSE, stCfg.enGopNum, stCfg.u16width, stCfg.u16height, stCfg.u32BaseAddr, Pixel_Format, Bytes_Per_Pixel, stCfg.bInterlace); ++ ++ GOP_Set_OutFormat(stCfg.enGopNum, stCfg.bYUVOutput); ++#if defined (CONFIG_ARCH_CEDRIC) ++ if(stCfg.enGopNum == E_GOP_1) ++ { ++ GOP_Set_PipeDelay(1, mstar_sca_drv_get_h_backporch(1) ); ++ } ++#endif ++ return 0; ++} ++ ++ ++int _MDrv_GOPIO_IOC_Set_Constant_Alpha(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_CONSTANT_ALPHA_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (GOP_SET_CONSTANT_ALPHA_CONFIG __user *)arg, sizeof(GOP_SET_CONSTANT_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Constant_Alpha(stCfg.enGopNum, stCfg.bEn, stCfg.u8Alpha); ++ ++ return 0; ++} ++ ++int _MDrv_GOPIO_IOC_Set_Color_Key(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_COLOR_KEY_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (GOP_SET_COLOR_KEY_CONFIG __user *)arg, sizeof(GOP_SET_COLOR_KEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Color_Key(stCfg.enGopNum, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ return 0; ++} ++ ++//============================================================================== ++long mstar_gop_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_devGOP.refCnt <= 0) ++ { ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOPIO_IOCTL refCnt =%d!!! \n", _devGOP.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(GOP_IOC_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= GOP_IOC_MAX_NR) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ switch(u32Cmd) ++ { ++ case GOP_IOC_SET_BASE_ADDR: ++ retval = _MDrv_GOPIO_IOC_Set_BaseAddr(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_MODE: ++ retval = _MDrv_GOPIO_IOC_SetMode(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_CONSTANT_ALPHA: ++ retval = _MDrv_GOPIO_IOC_Set_Constant_Alpha(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_COLOR_KEY: ++ retval = _MDrv_GOPIO_IOC_Set_Color_Key(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++static int mstar_gop_drv_probe(struct platform_device *pdev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_probe\n"); ++ ++ return 0; ++} ++ ++static int mstar_gop_drv_remove(struct platform_device *pdev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_remove\n"); ++ ++ return 0; ++} ++ ++ ++static int mstar_gop_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_suspend\n"); ++ ++ ++ return 0; ++} ++ ++ ++static int mstar_gop_drv_resume(struct platform_device *dev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_resume\n"); ++ ++ ++ return 0; ++} ++ ++static void mstar_gop_drv_platfrom_release(struct device *device) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_platfrom_release\n"); ++ ++} ++ ++ ++int mstar_gop_drv_open(struct inode *inode, struct file *filp) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOP DRIVER OPEN\n"); ++ ++ GOPIO_ASSERT(_devGOP.refCnt>=0); ++ _devGOP.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mstar_gop_drv_release(struct inode *inode, struct file *filp) ++{ ++ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOP DRIVER RELEASE\n"); ++ _devGOP.refCnt--; ++ GOPIO_ASSERT(_devGOP.refCnt>=0); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_GOPIO_ModuleInit(void) ++{ ++ int s32Ret; ++ dev_t dev; ++ int ret = 0; ++ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOPIO]_Init \n"); ++ ++ if(_devGOP.s32Major) ++ { ++ dev = MKDEV(_devGOP.s32Major, _devGOP.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_GOP_DEVICE_COUNT, MDRV_GOP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _devGOP.s32Minor, MDRV_GOP_DEVICE_COUNT, MDRV_GOP_NAME); ++ _devGOP.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] Unable to get major %d\n", _devGOP.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_devGOP.cdev, &_devGOP.fops); ++ if (0 != (s32Ret= cdev_add(&_devGOP.cdev, dev, MDRV_GOP_DEVICE_COUNT))) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_GOP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ gop_class = class_create(THIS_MODULE, gop_classname); ++ if(IS_ERR(gop_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(gop_class, NULL, dev,NULL, "mstar_gop"); ++ } ++ ++ /* initial the whole GOP Driver */ ++ ret = platform_driver_register(&Mstar_gop_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&sg_mdrv_gop_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&Mstar_gop_driver); ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] register failed\n"); ++ ++ } ++ else ++ { ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _MDrv_GOPIO_ModuleExit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ GOP_DBG(GOP_DBG_LV_0, "[GOPIO]_Exit \n"); ++ ++ cdev_del(&_devGOP.cdev); ++ device_destroy(gop_class, MKDEV(_devGOP.s32Major, _devGOP.s32Minor)); ++ class_destroy(gop_class); ++ unregister_chrdev_region(MKDEV(_devGOP.s32Major, _devGOP.s32Minor), MDRV_GOP_DEVICE_COUNT); ++ platform_driver_unregister(&Mstar_gop_driver); ++} ++ ++ ++module_init(_MDrv_GOPIO_ModuleInit); ++module_exit(_MDrv_GOPIO_ModuleExit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GOPioctrl driver"); ++MODULE_LICENSE("GOP"); ++ +diff --git a/drivers/mstar/fb/chicago/gop/mdrv_gop_io.h b/drivers/mstar/fb/chicago/gop/mdrv_gop_io.h +new file mode 100644 +index 00000000..a010fcec +--- /dev/null ++++ b/drivers/mstar/fb/chicago/gop/mdrv_gop_io.h +@@ -0,0 +1,123 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_GOP_IO_H ++#define _MDRV_GOP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_GOP_LIB_CODE {'G','O','P','\0'} ++#define MSIF_GOP_BUILDNUM {'_','0','1','\0'} ++#define MSIF_GOP_LIBVER (2) ++#define MSIF_GOP_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++#define GOP_IOC_SET_BASE_ADDR_NR (0) ++#define GOP_IOC_SET_MODE_NR (1) ++#define GOP_IOC_SET_CONSTANT_ALPHA_NR (2) ++#define GOP_IOC_SET_COLOR_KEY_NR (3) ++#define GOP_IOC_MAX_NR (4) ++ ++ ++// use 'm' as magic number ++#define GOP_IOC_MAGIC ('3') ++#define GOP_IOC_SET_BASE_ADDR _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_BASE_ADDR_NR, GOP_SET_BASE_ADDR_CONFIG) ++#define GOP_IOC_SET_MODE _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_MODE_NR, GOP_SETMODE_CONFIG) ++#define GOP_IOC_SET_CONSTANT_ALPHA _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_CONSTANT_ALPHA_NR, GOP_SET_CONSTANT_ALPHA_CONFIG) ++#define GOP_IOC_SET_COLOR_KEY _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_COLOR_KEY_NR, GOP_SET_COLOR_KEY_CONFIG) ++//============================================================================= ++// enum ++//============================================================================= ++typedef enum ++{ ++ E_GOP_0, ++ E_GOP_1, ++ E_GOP_2, ++ E_GOP_3, ++ E_GOP_MAX, ++}E_GOP_NUM_TYPE; ++ ++ ++typedef enum ++{ ++ E_GOP_SRC_RGB565, ++ E_GOP_SRC_ARGB8888, ++ E_GOP_SRC_ABGR8888, ++}E_GOP_SRC_FORMAT_TYPE; ++//============================================================================= ++// struct ++//============================================================================= ++#ifndef _MS_TYPES_H_ ++typedef unsigned char MS_U8; ++typedef unsigned short MS_U16; ++typedef unsigned long MS_U32; ++typedef unsigned long long MS_U64; ++typedef unsigned char MS_BOOL; ++typedef signed short MS_S16; ++#endif ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_U32 u32Base; ++}GOP_SET_BASE_ADDR_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ E_GOP_SRC_FORMAT_TYPE enSrcFormat; ++ MS_U16 u16width; ++ MS_U16 u16height; ++ MS_BOOL bInterlace; ++ MS_U32 u32BaseAddr; ++ MS_BOOL bYUVOutput; ++}GOP_SETMODE_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_BOOL bEn; ++ MS_U8 u8Alpha; ++}GOP_SET_CONSTANT_ALPHA_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_BOOL bEn; ++ MS_U8 u8R; ++ MS_U8 u8G; ++ MS_U8 u8B; ++}GOP_SET_COLOR_KEY_CONFIG; ++#endif //_MDRV_GFLIP_IO_H ++ ++ ++ +diff --git a/drivers/mstar/fb/chicago/mdrv_fb.c b/drivers/mstar/fb/chicago/mdrv_fb.c +new file mode 100644 +index 00000000..70778d69 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/mdrv_fb.c +@@ -0,0 +1,1039 @@ ++ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_general_fb.c ++ * DESCRIPTION For mdrv LinuxBSP Display driver, use frame buffer ++ * architecture ++ * ++ * AUTHOR Chun Fan ++ * ++ * ++ * HISTORY 2008/05/06 initial version ++ * linux/drivers/video/mdrv_general_fb.c ++ * -- mdrv frame buffer device ++ *****************************************************************************/ ++ ++ ++#define mdrv_GEN_FB_C ++ ++ ++#include "mdrv_fb.h" ++#include "ge/columbus2/mhal_ge.h" ++ ++ ++//#include "../scaler/mdrv_sca_io.h" ++/* ++ * RAM we reserve for the frame buffer. This defines the maximum screen ++ * size ++ * ++ * The default can be overridden if the driver is compiled as a module ++ */ ++ ++/* must use u_long, or it will have following message ++ * drivers/video/mdrv_general_fb.c: In function '__check_sg_videomemorysize': ++ * drivers/video/mdrv_general_fb.c:54: warning: ++ * return from incompatible pointer type ++ */ ++ /* frame buffer size */ ++static u_long sg_videomemorysize; ++ ++/* physical address, used in probe(), ioctl(), remove(), CreateGWin() */ ++/* physical address of frame buffer 1 2 */ ++dma_addr_t sg_G3D_Fb0_bus_addr1 = 0; ++ ++extern int mstar_sca_drv_get_pnl_width(void); ++extern int mstar_sca_drv_get_pnl_height(void); ++extern int mstar_sca_drv_get_pnl_refresh_rate(void); ++extern void mstar_sca_drv_init_pnl(BOOLEAN bSkipTime); ++ ++#if defined(CONFIG_MS_CLONE_SCREEN) ++#define OUTPUT_WIDTH 720 ++#define OUTPUT_HEIGHT 480 ++ ++typedef unsigned short MS_U16; ++typedef unsigned char MS_BOOL; ++ ++GE_DRAW_RECT drawbuf; ++GE_BUFFER_INFO srcbuffer; ++GE_BUFFER_INFO dstbuffer; ++GE_POINT_t stClipV0; ++GE_POINT_t stClipV1; ++MS_U16 u16output_width = 720; ++MS_U16 u16output_height = 480; ++MS_BOOL boutput_interlace = 1; ++ ++extern unsigned char IsRTKCarBacking(void); ++extern void SCA_CloneScr_GetOutputSize(MS_U16 *pu16Width, MS_U16 *pu16Height, MS_BOOL *bInterlace); ++#endif ++ ++static struct platform_device *psg_mdrv_fbdev0; ++//static DECLARE_MUTEX(mstar_panel_alloc_sem); ++ ++module_param(sg_videomemorysize, ulong, 0); ++ ++static void __init mdrvfb0_updateinfo(void) ++{ ++ ++ static int main_videomemory_size=0; ++ FBDBG("mdrvfb0_updateinfo !\n"); ++ ++ sg_mdrvfb0_default_var.xres = mstar_sca_drv_get_pnl_width();//tPanelNANOVISON_45->m_wPanelWidth; ++ sg_mdrvfb0_default_var.yres = mstar_sca_drv_get_pnl_height();//tPanelNANOVISON_45->m_wPanelHeight; ++ main_videomemory_size = (sg_mdrvfb0_default_var.xres*sg_mdrvfb0_default_var.yres * ANDROID_BYTES_PER_PIXEL * (ANDROID_NUMBER_OF_BUFFERS+1)); ++ ++ sg_mdrvfb0_default_fbmode.refresh=mstar_sca_drv_get_pnl_refresh_rate(); ++#if SUPPORT_EXTERNAL_DISPLAY ++ sg_videomemorysize = main_videomemory_size + EXTERNAL_DISPLAY_FRAMEBUFFER_SIZE; ++#else ++ sg_videomemorysize = main_videomemory_size; ++#endif ++ FBDBG ("mdrvfb0_updateinfo: LCD_PANEL_WIDTH = [%d] \r\n",sg_mdrvfb0_default_var.xres); ++ FBDBG ("mdrvfb0_updateinfo: LCD_PANEL_HEIGHT = [%d] \r\n",sg_mdrvfb0_default_var.yres); ++ FBDBG ("mdrvfb0_updateinfo: sg_videomemorysize = 0x%x \r\n",(U32)sg_videomemorysize); ++ ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb0_mmap +++------------------------------------------------------------------------------ ++| DESCRIPTION : memory map function, Let user application can get virtual ++| address to access in user space. need pass in physical address ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| vma | x | x | we use Remap-pfn-range will mark the range VM_IO ++| | | | and VM_RESERVED, and save these information in ++| | | | vma +++------------------------------------------------------------------------------ ++*/ ++ ++static int mdrvfb0_mmap(struct fb_info *pinfo, struct vm_area_struct *vma) ++{ ++ size_t size; ++ size = 0; ++ ++ MstarFB_ENTER(); ++ ++ ++ if (NULL == pinfo) ++ { ++ FBDBG("ERROR: mdrvfb0_mmap, pinfo is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ if (NULL == vma) ++ { ++ FBDBG("ERROR: mdrvfb0_mmap, vma is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_pgoff += ((sg_G3D_Fb0_bus_addr1 ) >> PAGE_SHIFT); ++ ++ FBDBG( ++ "mdrvfb0_mmap vma->vm_start=%x\n vma->vm_end=%x\n vma->vm_pgoff =%x\n", ++ (unsigned int) vma->vm_start, (unsigned int)vma->vm_end , ++ (unsigned int)vma->vm_pgoff); ++ ++ //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ ++ MstarFB_LEAVE(); ++ return 0; ++} ++ ++ ++ ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb0_ioctl +++------------------------------------------------------------------------------ ++| DESCRIPTION : IO control code. we provide some customize ioctl code, GLES, ++| and test code. now, we provide the following IOCTL command ++| G3D_GETVFRAMEVIRTUAL1 ++| G3D_GETVFRAMEVIRTUAL2 ++| G3D_GETCOMMANDQVIRTUAL ++| G3D_GETREGISTERVIRTUAL ++| G3D_GETTEXTUREVIRTUAL ++| G3D_FREETEXTUREVIRTUAL ++| SET_DISPLAY_COLOR ++| G3D_IOC_MAXNR 20 ++| ++| + define color ++| COLOR_MASK ++| WHITE_COLOR ++| ++| RETURN : When the operation is success, it return 0. ++| some ioctl will return the physical address for GLES use ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| cmd | x | | pass in the ioctl command ++|--------------------+---+---+------------------------------------------------- ++| arg | x | x | pass in/out argument, from user space or to user ++| | | | space +++------------------------------------------------------------------------------ ++*/ ++/* I reserve the unsgined long here, ++ because it is the ioctl() function template */ ++static int ++mdrvfb0_ioctl(struct fb_info *pinfo, unsigned int cmd, unsigned long arg) ++{ ++ dma_addr_t Fb0_PHY_ADD_SHOW=0;//tracy 26Nov2012 ++ int err=0, ret=0; ++ unsigned int ret_Phy=0; ++ ++ ++ if (NULL == pinfo) ++ { ++ FBDBG("ERROR:in mdrvfb0_ioctl, pinfo is NULL pointer\r\n"); ++ return -ENOTTY; ++ } ++ ++ /* don't even decode wrong cmds: better returning ENOTTY than EFAULT */ ++ if (_IOC_TYPE(cmd) != G3D_IOC_MAGIC) ++ return -ENOTTY; ++// if (_IOC_NR(cmd) > G3D_IOC_MAXNR) ++// return -ENOTTY; ++ ++ /* ++ * the type is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. Note that the type is user-oriented, while ++ * verify_area is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ err = !access_ok(VERIFY_WRITE, CAST_2_USER_VOID_P arg, _IOC_SIZE(cmd)); ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ err = !access_ok(VERIFY_READ, CAST_2_USER_VOID_P arg, _IOC_SIZE(cmd)); ++ ++ /* check if occurred error */ ++ if (err) ++ return -EFAULT; ++ ++ switch (cmd) ++ { ++ ++ ++ case G3D_GETFBPHYADDRESS1: ++ ret_Phy = sg_G3D_Fb0_bus_addr1; ++ ++ //DBG("ret_Phy=%x\r\n",ret_Phy); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ ++ ++ ++ case G3D_GETCOMMANDQVIRTUAL: ++ ++ FBDBG("in ioctl G3D_GETCOMMANDQVIRTUAL not support \r\n"); ++ ++ break; ++ ++ ++ case G3D_FREETEXTUREVIRTUAL: ++ ++ FBDBG("in ioctl G3D_FREETEXTUREVIRTUAL not support \r\n"); ++ ++ break; ++ ++ case G3D_GETREGISTERVIRTUAL: ++ ++ FBDBG("in ioctl G3D_GETREGISTERVIRTUAL not support \r\n"); ++ ++ break; ++ ++ case FBIOGET_VIDEOMEMSIZE: ++ ret_Phy = sg_videomemorysize; ++ FBDBG( "KERNEL- VIDEOMEMSIZE =0x%x" ,(u32)sg_videomemorysize); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ ++ break; ++ case FBIOGET_CURRENTBUFFERID: ++ if (pinfo->var.yoffset >= (pinfo->var.height << 1)) ++ { ++ ret_Phy = 3; ++ } ++ else if (pinfo->var.yoffset >= pinfo->var.height) ++ { ++ ret_Phy = 2; ++ } ++ else ++ { ++ ret_Phy = 1; ++ } ++ ++ ++ printk(KERN_INFO "FBIOGET_CURRENTBUFFERID BUFFERID = %d \n",ret_Phy); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ case CANCEL_USE_CALIBRATION_FRAMEBUFFER: ++ useCalibrationFrameBuffer=0; ++ printk("useCalibrationFrameBuffer = %d \n", useCalibrationFrameBuffer); ++ Fb0_PHY_ADD_SHOW = sg_G3D_Fb0_bus_addr1; ++ GOP_Pan_Display(0, Fb0_PHY_ADD_SHOW); ++ ++ break; ++ case USE_CALIBRATION_FRAMEBUFFER: ++ useCalibrationFrameBuffer=1; ++ printk("useCalibrationFrameBuffer = %d \n", useCalibrationFrameBuffer); ++ Fb0_PHY_ADD_SHOW = sg_G3D_Fb0_bus_addr1 + ((sg_mdrvfb0_default_var.xres * sg_mdrvfb0_default_var.yres * ANDROID_BYTES_PER_PIXEL)*ANDROID_NUMBER_OF_BUFFERS); ++ GOP_Pan_Display(0, Fb0_PHY_ADD_SHOW); ++ break; ++ ++ case G3D_GET_CALIBRATION_FRAMEBUFFER_IN_USE: ++ ret_Phy = useCalibrationFrameBuffer; ++ //DBG("ret_Phy=%x\r\n",ret_Phy); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ FBDBG("in default ioct\r\n"); ++ return -ENOTTY; ++ } ++ return ret; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb0_platform_release +++------------------------------------------------------------------------------ ++| DESCRIPTION : when module is unloaded, this function will be called ++| This is called when the reference count goes to zero. ++| ++| RETURN : no return value ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| device | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++ ++static void mdrvfb0_platform_release(struct device *device) ++{ ++ ++ MstarFB_ENTER(); ++ ++ if (NULL == device) ++ { ++ FBDBG("ERROR: in mdrvfb0_platform_release, \ ++ device is NULL pointer !\r\n"); ++ } ++ else ++ { ++ FBDBG("in mdrvfb0_platform_release, module unload!\n"); ++ } ++ ++ MstarFB_LEAVE(); ++} ++ ++#if 0 ++void mdrvgop_DispCreateGWin2(struct fb_info *WG) ++{ ++ ++ int xx=0; ++ xx++; ++ ++ FBDBG("fb%d: mdrv frame buffer device, of video memory\n", WG->node); ++} ++#endif ++static int mdrvfb0_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ FBDBG(" in mdrvfb0_suspend \r\n"); ++ return 0; ++} ++ ++static int mdrvfb0_resume(struct platform_device *pdev) ++{ ++ dma_addr_t Fb0_PHY_ADD_SHOW=0; ++ FBDBG(" mdrvfb0_resume \r\n"); ++ ++ if(unlikely(useCalibrationFrameBuffer)) ++ { ++ Fb0_PHY_ADD_SHOW = sg_G3D_Fb0_bus_addr1 + ((sg_mdrvfb0_default_var.xres * sg_mdrvfb0_default_var.yres * ANDROID_BYTES_PER_PIXEL)*ANDROID_NUMBER_OF_BUFFERS); ++ GOP_Setmode(TRUE, 0,sg_mdrvfb0_default_var.xres,sg_mdrvfb0_default_var.yres,Fb0_PHY_ADD_SHOW,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ } ++ else ++ { ++ GOP_Setmode(TRUE, 0,sg_mdrvfb0_default_var.xres,sg_mdrvfb0_default_var.yres,sg_G3D_Fb0_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ } ++ ++#if defined(CONFIG_MS_CLONE_SCREEN) ++ SCA_CloneScr_GetOutputSize(&u16output_width, &u16output_height, &boutput_interlace); ++ u16output_height = boutput_interlace ? u16output_height * 2 : u16output_height; ++ GOP_Setmode(TRUE, 1,(int)u16output_width, (int)u16output_height,sg_G3D_Fb0_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, (int)boutput_interlace); ++ ++ stClipV0.x = 0; ++ stClipV0.y = 0; ++ stClipV1.x = u16output_width; ++ stClipV1.y = u16output_height; ++ ++ MHal_GE_SetClip(&stClipV0, &stClipV1); ++ MHal_GE_SetSrcBufferInfo(&srcbuffer, 0); ++ MHal_GE_SetDstBufferInfo(&dstbuffer, 0); ++ MHal_GE_SetAlphaSrcFrom( ABL_FROM_ASRC ); ++#endif ++ ++ //printk("fb0 resume sleep ! \n"); ++ //msleep(5000); ++ return 0; ++} ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb0_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : Initialization. Initial HW, fill table, when load module, ++| this function will be called. ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++ ++static int mdrvfb0_probe(struct platform_device *dev) ++{ ++ struct fb_info *pinfo = NULL; ++ int retval = -ENOMEM; ++ ++ int fb_format=0; ++ ++ MstarFB_ENTER(); ++ ++ if (NULL == dev) ++ { ++ FBDBG("ERROR: in mdrvfb0_prob: dev is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ fb_format=ANDROID_FB_FORMAT; ++ ++ // static global variable, pass at probe(), used by dma alloc and dma free in ioctl(), ++ psg_mdrv_fbdev0 = dev; ++ ++// FBDBG("mdrvfb0: sg_videomemorysize is 0x%X to allocate screen memory\n",(u32)sg_videomemorysize); ++ ++ FBDBG("mdrvfb0: sg_videomemorysize is 0x%X to allocate screen memory\n",(u32)sg_videomemorysize); ++ ++ ++ /* For G3D frame buffer2 */ ++ if (!(sg_pG3D_Fb0_vir_addr1 = dma_alloc_coherent(&dev->dev, ++ PAGE_ALIGN(sg_videomemorysize), ++ &sg_G3D_Fb0_bus_addr1, ++ GFP_KERNEL))) ++ { ++ FBDBG("mdrvfb0: unable to allocate screen memory\n"); ++ return retval; ++ } ++ ++ //printk("---------1 \n"); ++ //msleep(6000); ++ // prevent initial garbage on screen ; to clean memory ++// memset(CAST_2_IOMEM_CHAR_P sg_pG3D_Fb0_vir_addr1,WHITE_COLOR, sg_videomemorysize); ++ memset(CAST_2_IOMEM_CHAR_P sg_pG3D_Fb0_vir_addr1,OTHER_COLOR, sg_videomemorysize); ++ ++// FBDBG("mdrvfb0 vir1=0x%x, phy1=0x%x\n", (u32)sg_pG3D_Fb0_vir_addr1, sg_G3D_Fb0_bus_addr1); ++ FBDBG("mdrvfb0 vir2=0x%x, phy2=0x%x\n", (u32)sg_pG3D_Fb0_vir_addr1, sg_G3D_Fb0_bus_addr1); ++ ++ sg_mdrvfb0_fix.smem_start = sg_G3D_Fb0_bus_addr1; ++ sg_mdrvfb0_fix.smem_len = sg_videomemorysize; ++ ++ pinfo = framebuffer_alloc(sizeof(struct fb_info), &dev->dev); ++ if (!pinfo) ++ goto err; ++ ++ ++ pinfo->screen_base = CAST_2_IOMEM_CHAR_P( sg_pG3D_Fb0_vir_addr1); ++ FBDBG( "sg_mdrvfb0_fix.smem_start=0x%x ",(U32) sg_mdrvfb0_fix.smem_start); ++ ++ //printk("---------2 \n"); ++ //msleep(6000); ++ ++ pinfo->fbops = &sg_mdrvfb0_ops; ++ pinfo->var = sg_mdrvfb0_default_var; ++ pinfo->fix = sg_mdrvfb0_fix; ++ pinfo->pseudo_palette = pinfo->par; ++ pinfo->par = NULL; ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ ++ ++ /* allocate color map */ ++ /* 256 is following to the vfb.c */ ++ retval = fb_alloc_cmap(&pinfo->cmap, 256, 0); ++ if (retval < 0) ++ goto err1; ++ ++ ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ pinfo->fix.type = FB_TYPE_PACKED_PIXELS; ++ pinfo->fix.visual = FB_VISUAL_TRUECOLOR; ++ pinfo->fix.line_length = sg_mdrvfb0_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ pinfo->fix.accel = FB_ACCEL_NONE; ++ pinfo->fix.ypanstep = 1; ++ ++ pinfo->var.xres = sg_mdrvfb0_default_var.xres; ++ pinfo->var.yres = sg_mdrvfb0_default_var.yres; ++ pinfo->var.xres_virtual = sg_mdrvfb0_default_var.xres; ++ pinfo->var.yres_virtual = sg_mdrvfb0_default_var.yres * ANDROID_NUMBER_OF_BUFFERS; ++ pinfo->var.bits_per_pixel = BPX; ++ pinfo->var.activate = FB_ACTIVATE_NOW; ++ pinfo->var.height = sg_mdrvfb0_default_var.yres; ++ pinfo->var.width = sg_mdrvfb0_default_var.xres; ++ pinfo->fix.smem_len = sg_videomemorysize; ++ ++ //printk("---------3 \n"); ++ //msleep(6000); ++ ++ ++ if (RGB565==fb_format) ++ { ++ ++ pinfo->var.red.offset = 11; ++ pinfo->var.red.length = 5; ++ pinfo->var.green.offset = 5; ++ pinfo->var.green.length = 6; ++ pinfo->var.blue.offset = 0; ++ pinfo->var.blue.length = 5; ++ } ++ else if(ARGB8888==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 8; ++ pinfo->var.red.length = 8; ++ pinfo->var.green.length = 8; ++ pinfo->var.blue.length = 8; ++ ++ pinfo->var.transp.offset = 24; ++ pinfo->var.red.offset = 16; ++ pinfo->var.green.offset = 8; ++ pinfo->var.blue.offset = 0; ++ } ++#if defined(CONFIG_ARCH_CEDRIC) ++ else if(RGBA8888==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 8; ++ pinfo->var.red.length = 8; ++ pinfo->var.green.length = 8; ++ pinfo->var.blue.length = 8; ++ ++ pinfo->var.transp.offset = 0; ++ pinfo->var.red.offset = 24; ++ pinfo->var.green.offset = 16; ++ pinfo->var.blue.offset = 8; ++ } ++#endif ++ else ++ { ++ ++ printk(KERN_ERR"ERROR!! mdrvfb0_probe fb_format =%d Not Support!!",fb_format); ++ while(1); ++ ++ } ++ /* register mdrvfb to fbmem.c */ ++ retval = register_framebuffer(pinfo); ++ if (retval < 0) ++ goto err2; ++ ++ platform_set_drvdata(dev, pinfo); ++ ++ //patch some setting due to our panel setting may have problems ++ { ++ struct list_head *pos; ++ struct fb_modelist *modelist; ++ ++ list_for_each(pos, &pinfo->modelist) { ++ modelist = list_entry(pos, struct fb_modelist, list); ++ modelist->mode.refresh=sg_mdrvfb0_default_fbmode.refresh; ++ } ++ } ++ ++ //printk("---------4 \n"); ++ //msleep(6000); ++ ++ /* ======================================================== */ ++ /* HW INIT related code */ ++ /* ======================================================== */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_58 , 0x1); /* power switch enable */ ++ ++ //CLRREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_57, 0x0200); /* external device power on output enable */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_57, 0x0002); /* external device power on enable */ ++ ++ /* 0. CHIPTOP Register - BIT_9 : Enable RGB output, Bit_14 reg_OP2_en */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_09 , 0x4200); /* */ ++ ++ //ms_writew( 0x0040,MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_26); //add ++ ++ /* h'28 CLK_GE clock control */ ++ /* ++ //weichun temp disable ++ CLRREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_28, 0x1F); ++ SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_28 , 0x8); ++ */ ++ /*h'2A CLK_GOPG0 clock control */ ++ /* ++ ++ */ ++ /* 2. Set CLK_ODCLK's source is LPLL */ ++ //ms_writew( 0x1C00,MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_1B); ++ ++ ++ //CLRREG16(0xA0002604 , 0x0008); ++ ++ //ms_writew(0, MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_2C ); ++ ++ /* Create GWIN, make a window to show graph, setting HW(GOP) */ ++ //mdrvgop_DispCreateGWin(); ++ ++ // FB info ++ // FB Width ++ // FB Pitch ++ // FB Height ++ // FB Starting address ++ // FB Format ++ ++ // View info ++ ++ // mdrvgop_DispCreateGWin2(pinfo); ++ //mdrvgop_DispCreateGWin(sg_G3D_Fb_bus_addr1,sg_G3D_Fb_bus_addr2,sg_mdrvfb_default_var.xres,sg_mdrvfb_default_var.yres,ANDROID_BYTES_PER_PIXEL); ++ #if (UBOOT_SHOW_LOGO==0) ++ GOP_Setmode(FALSE, 0,sg_mdrvfb0_default_var.xres,sg_mdrvfb0_default_var.yres,sg_G3D_Fb0_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ //#else ++ // GOP_Change_Alpha(FALSE, 0,sg_mdrvfb0_default_var.xres,sg_mdrvfb0_default_var.yres,sg_G3D_Fb0_bus_addr2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ #endif ++ ++#if defined(CONFIG_MS_CLONE_SCREEN) ++ SCA_CloneScr_GetOutputSize(&u16output_width, &u16output_height, &boutput_interlace); ++ u16output_height = boutput_interlace ? u16output_height * 2 : u16output_height; ++ ++ GOP_Setmode(FALSE, 1,(int)u16output_width, (int)u16output_height,sg_G3D_Fb0_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, (int)boutput_interlace); ++ ++ drawbuf.srcblk.x = 0; ++ drawbuf.srcblk.y = 0; ++ drawbuf.srcblk.width = mstar_sca_drv_get_pnl_width(); ++ drawbuf.srcblk.height = mstar_sca_drv_get_pnl_height(); ++ ++ drawbuf.dstblk.x = 0; ++ drawbuf.dstblk.y = 0; ++ drawbuf.dstblk.width = (int)u16output_width; ++ drawbuf.dstblk.height = (int)u16output_height; ++ ++ ++ srcbuffer.u32Addr = sg_G3D_Fb0_bus_addr2; ++ srcbuffer.u32ColorFmt = 0xf; ++ srcbuffer.u32Height = mstar_sca_drv_get_pnl_height(); ++ srcbuffer.u32Width = mstar_sca_drv_get_pnl_width(); ++ srcbuffer.u32Pitch = (srcbuffer.u32Width << 2); ++ ++ dstbuffer.u32Addr = sg_G3D_Fb0_bus_addr1; ++ dstbuffer.u32ColorFmt = 0xf; ++ dstbuffer.u32Height = (int)u16output_height; ++ dstbuffer.u32Width = (int)u16output_width; ++ dstbuffer.u32Pitch = (dstbuffer.u32Width << 2); ++ ++ stClipV0.x = 0; ++ stClipV0.y = 0; ++ stClipV1.x = u16output_width; ++ stClipV1.y = u16output_height; ++ ++ MHal_GE_SetClip(&stClipV0, &stClipV1); ++ ++ MHal_GE_SetSrcBufferInfo(&srcbuffer, 0); ++ MHal_GE_SetDstBufferInfo(&dstbuffer, 0); ++ MHal_GE_SetAlphaSrcFrom( ABL_FROM_ASRC ); ++#endif ++ ++// FBDBG("fb%d: mdrv frame buffer device, using %ldK of video memory\n", pinfo->node, sg_videomemorysize >> 10); ++ ++ //printk("---------5 \n"); ++ //msleep(6000); ++ MstarFB_LEAVE(); ++ return 0; ++ ++err2: ++ fb_dealloc_cmap(&pinfo->cmap); ++err1: ++ framebuffer_release(pinfo); ++err: ++ ++ dma_free_coherent(&dev->dev, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_Fb0_vir_addr1, ++ sg_G3D_Fb0_bus_addr1); ++ ++ ++ ++ ++ return retval; ++} ++ ++ ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb0_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : we free memory, release frame buffer here ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvfb0_remove(struct platform_device *dev) ++{ ++ struct fb_info *pinfo; ++ pinfo = 0; ++ ++ ++ MstarFB_ENTER(); ++ ++ ++ if (NULL == dev) ++ { ++ FBDBG("ERROR: mdrvfb0_remove: dev is NULL pointer \n"); ++ return -ENOTTY; ++ } ++ ++ pinfo = platform_get_drvdata(dev); ++ if (pinfo) ++ { ++ unregister_framebuffer(pinfo); ++ ++ dma_free_coherent(&dev->dev, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_Fb0_vir_addr1, ++ sg_G3D_Fb0_bus_addr1); ++ ++#if defined(CONFIG_ARCH_MSB251X) ++ dma_free_coherent(&dev->dev, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_Fb0_vir_addr3, ++ sg_G3D_Fb0_phy_addr3); ++#endif ++ ++ ++ ++ framebuffer_release(pinfo); ++ } ++ ++ MstarFB_LEAVE(); ++ return 0; ++} ++ ++static int mdrvfb0_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ ++ //MstarFB_ENTER(); ++ dma_addr_t Fb0_PHY_ADD_SHOW=0; ++ ++ if( unlikely(useCalibrationFrameBuffer)) ++ { ++ return 0; ++ } ++ else ++ { ++ ++ if (info->var.yoffset >= (info->var.height << 1)) ++ { ++ Fb0_PHY_ADD_SHOW = info->fix.smem_start + ((info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL) << 1); ++ } ++ else if (info->var.yoffset >= info->var.height) ++ { ++ Fb0_PHY_ADD_SHOW = info->fix.smem_start + (info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL); ++ } ++ else ++ { ++ Fb0_PHY_ADD_SHOW = info->fix.smem_start; ++ } ++ ++ GOP_Pan_Display(0, Fb0_PHY_ADD_SHOW); ++ ++#if defined(CONFIG_MS_CLONE_SCREEN) ++ if (!IsRTKCarBacking()) ++ { ++ static MS_U16 u16PreH = 480; ++ static MS_U16 u16PreW = 720; ++ static MS_BOOL bPreInterlace = 1; ++ ++ srcbuffer.u32Addr = Fb0_PHY_ADD_SHOW; ++ ++ SCA_CloneScr_GetOutputSize(&u16output_width, &u16output_height, &boutput_interlace); ++ u16output_height = boutput_interlace ? u16output_height * 2 : u16output_height; ++ ++ if (info->var.yoffset >= (info->var.height << 1)) ++ { ++ dstbuffer.u32Addr = sg_G3D_Fb0_bus_addr1 + ((u16output_width * u16output_height * ANDROID_BYTES_PER_PIXEL) << 1); ++ } ++ else if (info->var.yoffset >= info->var.height) ++ { ++ dstbuffer.u32Addr = sg_G3D_Fb0_bus_addr1 + (u16output_width * u16output_height * ANDROID_BYTES_PER_PIXEL); ++ } ++ else ++ { ++ dstbuffer.u32Addr = sg_G3D_Fb0_bus_addr1; ++ } ++ ++ ++ ++ if(u16PreW != u16output_width || u16PreH != u16output_height || bPreInterlace != boutput_interlace) ++ { ++ GOP_Setmode(FALSE, 1,(int)u16output_width, (int)u16output_height, ++ dstbuffer.u32Addr, ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, (int)boutput_interlace); ++ ++ stClipV0.x = 0; ++ stClipV0.y = 0; ++ stClipV1.x = u16output_width; ++ stClipV1.y = u16output_height; ++ ++ MHal_GE_SetClip(&stClipV0, &stClipV1); ++ } ++ u16PreW = u16output_width; ++ u16PreH = u16output_height; ++ bPreInterlace = boutput_interlace; ++ ++ drawbuf.dstblk.x = 0; ++ drawbuf.dstblk.y = 0; ++ drawbuf.dstblk.width = (int)u16output_width; ++ drawbuf.dstblk.height = (int)u16output_height; ++ ++ ++ dstbuffer.u32Height = (int)u16output_height; ++ dstbuffer.u32Width = (int)u16output_width; ++ dstbuffer.u32Pitch = (dstbuffer.u32Width << 2); ++ ++ ++ MHal_GE_SetSrcBufferInfo(&srcbuffer, 0); ++ MHal_GE_SetDstBufferInfo(&dstbuffer, 0); ++ MHal_GE_BitBlt(&drawbuf, GEDRAW_FLAG_SCALE); ++ GOP_Pan_Display(1, dstbuffer.u32Addr); ++ } ++#endif ++ ++ } ++ ++ return 0; ++} ++ ++ ++ ++ ++/* check var to see if supported by this device. Probably doesn't ++ * need modifying. ++ */ ++static int mdrvfb0_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ ++ //MstarFB_ENTER(); ++ ++ if((var->rotate & 1) != (info->var.rotate & 1)) ++ { ++ if((var->xres != info->var.yres) || ++ (var->yres != info->var.xres) || ++ (var->xres_virtual != info->var.yres) || ++ (var->yres_virtual > ++ info->var.xres * ANDROID_NUMBER_OF_BUFFERS) || ++ (var->yres_virtual < info->var.xres )) ++ { ++ return -EINVAL; ++ } ++ } ++ else ++ { ++ if((var->xres != info->var.xres) || ++ (var->yres != info->var.yres) || ++ (var->xres_virtual != info->var.xres) || ++ (var->yres_virtual > ++ info->var.yres * ANDROID_NUMBER_OF_BUFFERS) || ++ (var->yres_virtual < info->var.yres )) ++ { ++ return -EINVAL; ++ } ++ } ++ if((var->xoffset != info->var.xoffset) || ++ (var->bits_per_pixel != info->var.bits_per_pixel) || ++ (var->grayscale != info->var.grayscale)) ++ { ++ return -EINVAL; ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++ ++ ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb_init +++------------------------------------------------------------------------------ ++| DESCRIPTION : register the driver to kernel, ++| to tell it what facility or function we provide ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| ++| Variable Name : no variable +++------------------------------------------------------------------------------ ++*/ ++ ++/* register the driver to kernel, ++ to tell it what facility or function we provide */ ++static int __init mdrvfb0_init(void) ++{ ++ int ret = 0; ++ ++ MstarFB_ENTER(); ++ ++ /* register the driver into kernel */ ++ ++ // how to get the Panel type and what kind of output display device ? ++ ++ ++ //MApi_PNL_Init(tPanelNANOVISON_45); ++ #if(UBOOT_SHOW_LOGO==1) ++ mstar_sca_drv_init_pnl(TRUE); ++ #else ++ mstar_sca_drv_init_pnl(FALSE); ++ #endif ++ mdrvfb0_updateinfo(); ++ ++ ++ ++ ret = platform_driver_register(&sg_mdrvfb0_driver); ++ ++ if (!ret) ++ { /* register driver sucess */ ++ /* register device */ ++ ret = platform_device_register(&sg_mdrvfb0_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&sg_mdrvfb0_driver); ++ printk(KERN_INFO"mdrvfb0_device register failed...\n"); ++ } ++ else ++ { ++ printk(KERN_INFO"mdrvfb0_device register success...\n"); ++ } ++ } ++ ++ ++ MstarFB_LEAVE(); ++ ++ return ret; ++} ++ ++ ++void fb0_fake_imageblit(struct fb_info *info, const struct fb_image *image) ++{ ++ ++ MstarFB_ENTER(); ++ ++ sys_imageblit(info,image); ++ ++ MstarFB_LEAVE(); ++ ++} ++ ++void fb0_fake_copyarea(struct fb_info *info, const struct fb_copyarea *region) ++{ ++ ++ MstarFB_ENTER(); ++ ++ sys_copyarea(info,region); ++ ++ MstarFB_LEAVE(); ++ ++} ++ ++void fb0_fake_fillrect(struct fb_info *info, const struct fb_fillrect *rect) ++{ ++ ++ MstarFB_ENTER(); ++ ++ sys_fillrect(info,rect); ++ ++ MstarFB_LEAVE(); ++ ++} ++ ++module_init(mdrvfb0_init); /* tell kernel where the init function */ ++ ++#ifdef MODULE ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb0_exit +++------------------------------------------------------------------------------ ++| DESCRIPTION : cleanup the driver from kernel ++| ++| RETURN : no return value ++| ++| Variable Name : no variable +++------------------------------------------------------------------------------ ++*/ ++ ++static void __exit mdrvfb0_exit(void) ++{ ++ ++ MstarFB_ENTER(); ++ ++ platform_device_unregister(&sg_mdrvfb0_device); ++ ++ platform_driver_unregister(&sg_mdrvfb0_driver); ++ ++ MstarFB_LEAVE(); ++ ++} ++ ++module_exit(mdrvfb0_exit); /* tel kernel where is the clean up function */ ++ ++MODULE_LICENSE("GPL"); ++/* use GPL license to avoid Kernel to complain this driver */ ++#endif /* MODULE */ ++ ++ ++ ++ ++ ++//MODULE_LICENSE("GPL") +diff --git a/drivers/mstar/fb/chicago/mdrv_fb.h b/drivers/mstar/fb/chicago/mdrv_fb.h +new file mode 100644 +index 00000000..5aed97e2 +--- /dev/null ++++ b/drivers/mstar/fb/chicago/mdrv_fb.h +@@ -0,0 +1,369 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_fb.h ++ * DESCRIPTION ++ * Including some MACRO needed in mdrvfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/mdrvfb.h -- mdrvfb frame buffer device ++ ******************************************************************************/ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++#include "gop/mdrv_gop.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++ ++#define FB_DEBUG 1 ++#define FB_FUNBUG 1 ++#define fake_HW_acceleration 0 ++ ++ ++#if defined(CONFIG_ARCH_CHICAGO) ++#define UBOOT_SHOW_LOGO 0 ++#elif defined(CONFIG_ARCH_CEDRIC) ++#define UBOOT_SHOW_LOGO 1 ++#else ++#define UBOOT_SHOW_LOGO 1 ++#endif ++ ++ ++ ++#if (FB_DEBUG==1) ++#define FBDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define FBDBG(fmt, arg...) ++#endif ++ ++#define MstarTrace printk ++ ++#if 0 ++#if (FB_FUNBUG==1) ++#define MstarTrace printk ++#else ++#define MstarTrace if(0) printk ++#endif ++#endif ++ ++#define MstarFB_ENTER(...) MstarTrace("============ FB ============\r\n%s START\n", __func__) ++#define MstarFB_LEAVE(...) MstarTrace("%s END\n============ FB ============\r\n", __func__) ++ ++ ++ ++ ++ ++ ++#ifdef mdrv_GEN_FB_C /* in frame buffer driver */ ++#define PRIVATE_FB_DATA ++#else /* in user space */ ++#define PRIVATE_FB_DATA const ++#endif /* mdrv_GEN_FB_C */ ++ ++ ++ ++ ++ ++/* ========================================================================= */ ++/* define type cast macro */ ++#define CAST_2_USER_VOID_P (void __user *) ++#define CAST_2_USER_UINT_P (u32 __user *) ++#define CAST_2_USER_TEXTURE_INFO_P (TEXTURE_INFO __user *) ++#define CAST_2_IOMEM_CHAR_P (u8 __iomem *) ++#define CAST_2_ULONG (unsigned long) ++ ++ ++ ++/* ========================================================================= */ ++ ++/* ++ * Ioctl definitions ++ */ ++ ++/* Use 'F' as magic number. ++ in Documnentation/ioctl-number.txt says 'F' all linux/fb.h */ ++ ++#define G3D_IOC_MAGIC 'F' ++ ++ ++#define G3D_GETFBPHYADDRESS1 _IO(G3D_IOC_MAGIC, 9) ++#define G3D_GETFBPHYADDRESS2 _IO(G3D_IOC_MAGIC, 10) ++#define G3D_GETCOMMANDQVIRTUAL _IO(G3D_IOC_MAGIC, 11) ++#define G3D_GETREGISTERVIRTUAL _IO(G3D_IOC_MAGIC, 14) ++#define G3D_GETTEXTUREVIRTUAL _IO(G3D_IOC_MAGIC, 18) /* can not use 15 */ ++#define G3D_FREETEXTUREVIRTUAL _IO(G3D_IOC_MAGIC, 19) /* can not use 16 */ ++#define SET_DISPLAY_COLOR _IO(G3D_IOC_MAGIC, 20) /* FOR test case 2, display black, white, red,green, blue, blue. */ ++#define CAPTURE_SCREEN _IO(G3D_IOC_MAGIC, 21) //Edgar ++#define ENABLE_GWIN _IO(G3D_IOC_MAGIC, 22) //Edgar ++#define G3D_GETDWINPHYADDRESS1 _IO(G3D_IOC_MAGIC, 23) //Edgar ++#define DISABLE_GWIN _IO(G3D_IOC_MAGIC, 24) //Edgar ++#define G3D_GETDWINPHYADDRESS2 _IO(G3D_IOC_MAGIC, 25) //Edgar ++#define SET_ALPHA _IO(G3D_IOC_MAGIC, 26) //Edgar 21Apr2009 ++#define SET_COLORKEY _IO(G3D_IOC_MAGIC, 27) //Edgar 28Apr2009 ++#define DISABLE_COLORKEY _IO(G3D_IOC_MAGIC, 28) //Edgar 28Apr2009 ++#define CONFIG_PANEL _IO(G3D_IOC_MAGIC, 29) //Edgar 18Jun2009 ++#define SWITCH_GWIN_TO_SCALAR _IO(G3D_IOC_MAGIC, 30) //Edgar 01Jul2009 ++#define SWITCH_GWIN_TO_SCALAR _IO(G3D_IOC_MAGIC, 30) //Edgar 01Jul2009 ++#define FBIOGET_VIDEOMEMSIZE _IO(G3D_IOC_MAGIC, 31) ++#define FBIOGET_CURRENTBUFFERID _IO(G3D_IOC_MAGIC, 32) ++#define USE_CALIBRATION_FRAMEBUFFER _IO(G3D_IOC_MAGIC, 33) ++#define CANCEL_USE_CALIBRATION_FRAMEBUFFER _IO(G3D_IOC_MAGIC, 34) ++#define G3D_GET_EXTDISP_BUFFER _IO(G3D_IOC_MAGIC, 100) ++#define G3D_GET_CALIBRATION_FRAMEBUFFER_IN_USE _IOR(G3D_IOC_MAGIC, 101, int) ++ ++//#define G3D_IOC_MAXNR 34 //Edgar ++ ++static int useCalibrationFrameBuffer = 0 ; ++ ++ ++/* ========================================================================= */ ++/* define color */ ++#define COLOR_MASK 0xffff ++#define WHITE_COLOR 0xffff ++#define OTHER_COLOR 0xFF00 ++ ++ ++#define ANDROID_NUMBER_OF_BUFFERS 3 ++ ++ ++#if defined(CONFIG_ARCH_CEDRIC) ++#define ANDROID_FB_FORMAT RGBA8888 ++#elif defined(CONFIG_ARCH_CHICAGO) ++#define ANDROID_FB_FORMAT ARGB8888 ++#endif ++ ++ ++#define defult_XRES 800 // PANEL_WIDTH ++#define defult_YRES 480 //PANEL_HEIGHT ++#if (ANDROID_FB_FORMAT == RGB565) ++#define BPX 16 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 2 ++#elif ((ANDROID_FB_FORMAT == ARGB8888) || (ANDROID_FB_FORMAT == RGBA8888)) ++#define BPX 32 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 4 ++//#elif (ANDROID_FB_FORMAT == ARGB8888) ++//#define BPX 32 /* bits per pixel */ ++//#define ANDROID_BYTES_PER_PIXEL 4 ++#else ++ #ERROR("Not Support") ++#endif ++ ++#define SUPPORT_EXTERNAL_DISPLAY 1 ++#if SUPPORT_EXTERNAL_DISPLAY ++#define EXTERNAL_DISPLAY_MAX_WIDTH (720) ++#define EXTERNAL_DISPLAY_MAX_HEIGHT (576) ++#define EXTERNAL_DISPLAY_MAX_BUF_NUM (3) ++#define EXTERNAL_DISPLAY_FRAMEBUFFER_SIZE (4*EXTERNAL_DISPLAY_MAX_WIDTH*EXTERNAL_DISPLAY_MAX_HEIGHT*EXTERNAL_DISPLAY_MAX_BUF_NUM) ++#endif ++ ++/* ========================================================================= */ ++/* prototype of function */ ++ ++static s32 mdrvfb0_ioctl(struct fb_info *info, u32 cmd, unsigned long arg); ++static s32 mdrvfb0_mmap(struct fb_info *info, struct vm_area_struct *vma); ++static s32 mdrvfb0_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); ++static s32 mdrvfb0_check_var(struct fb_var_screeninfo *var, struct fb_info *info); ++void fb0_fake_fillrect(struct fb_info *info, const struct fb_fillrect *rect); ++void fb0_fake_copyarea(struct fb_info *info, const struct fb_copyarea *region); ++void fb0_fake_imageblit(struct fb_info *info, const struct fb_image *image); ++ ++ ++static struct fb_var_screeninfo sg_mdrvfb0_default_var = ++{ ++ .xres = defult_XRES, ++ .yres = defult_YRES, ++ .xres_virtual = defult_XRES, ++ .yres_virtual = defult_YRES, ++ .bits_per_pixel = BPX, ++#if (BPX == 32) ++ .transp ={0,8,0}, ++ .red = { 24, 8, 0 }, /* {offset,length,!= 0 : MSB is right} */ ++ .green = { 16, 8, 0 }, ++ .blue = { 8, 8, 0 }, ++#elif (BPX == 16) ++ .red = { 11, 5, 0 }, /* {offset,length,!= 0 : MSB is right} */ ++ .green = { 5, 6, 0 }, ++ .blue = { 0, 5, 0 }, ++#endif ++ .activate = FB_ACTIVATE_NOW, ++ .height = -1, /* =maximum, in fb.h is delcalred as _u32* */ ++ .width = -1, ++ ++ /* timing useless ? use the vfb default */ ++ .pixclock = 100000,//20000, /* pixel clock in ps (pico seconds) */ ++ .left_margin = 24,//64, /* time from sync to picture */ ++ .right_margin = 4,//64, /* time from picture to sync */ ++ .upper_margin = 6,//32, /* time from sync to picture */ ++ .lower_margin = 4,//32, ++ .hsync_len = 64, /* length of horizontal sync */ ++ .vsync_len = 2, /* length of vertical sync */ ++ .vmode = FB_VMODE_NONINTERLACED, ++ /* non interlaced, the most basical framebuffer */ ++}; ++ ++/* Device independent unchangeable information */ ++static struct fb_fix_screeninfo sg_mdrvfb0_fix = ++{ ++ .id = "mdrv FB", ++ .type = FB_TYPE_PACKED_PIXELS, /* see FB_TYPE_* */ ++ .visual = FB_VISUAL_TRUECOLOR, /* see FB_VISUAL_* */ ++ .xpanstep = 0, /* zero if no hardware panning */ ++ .ypanstep = 0, ++ .ywrapstep = 0, ++ .line_length = (defult_XRES * BPX >> 3), /* length of a line in bytes */ ++ .mmio_start=0x20000000, /* Start of Memory Mapped I/O */ ++ /* (physical address) */ ++ .mmio_len=0x10000000, /* Length of Memory Mapped I/O */ ++ .accel = FB_ACCEL_NONE, ++ /* Indicate to driver which specific chip/card we have */ ++}; ++ ++static struct fb_videomode sg_mdrvfb0_default_fbmode; ++ ++#if fake_HW_acceleration ++static struct fb_ops sg_mdrvfb0_ops = ++{ ++ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = fb0_fake_fillrect, ++ ++ /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = fb0_fake_copyarea, ++ ++ /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = fb0_fake_imageblit, ++ ++ /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ .fb_mmap = mdrvfb0_mmap, /* for non cached memory */ ++ ++ /* vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); */ ++ .fb_ioctl = mdrvfb0_ioctl, ++ ++ .fb_pan_display = mdrvfb0_pan_display, ++ ++ .fb_check_var = mdrvfb0_check_var, ++ ++}; ++#else ++static struct fb_ops sg_mdrvfb0_ops = ++{ ++ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = sys_fillrect, ++ ++ /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = sys_copyarea, ++ ++ /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = sys_imageblit, ++ ++ /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ .fb_mmap = mdrvfb0_mmap, /* for non cached memory */ ++ ++ /* vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); */ ++ .fb_ioctl = mdrvfb0_ioctl, ++ ++ .fb_pan_display = mdrvfb0_pan_display, ++ ++ .fb_check_var = mdrvfb0_check_var, ++ ++}; ++#endif ++//extern void MDrv_Scaler_Enable_GOP(BOOL); ++extern void sys_fillrect(struct fb_info *p, const struct fb_fillrect *rect); ++ ++/* virtual address in Kernel space, used in probe(), remove() */ ++//static void *sg_pG3D_Fb0_vir_addr1 = 0; /* virtual address of frame buffer 1 */ ++static void *sg_pG3D_Fb0_vir_addr1 = 0; /* virtual address of frame buffer 2 */ ++ ++#if 1 //def CONFIG_PM ++static int mdrvfb0_suspend(struct platform_device *pdev, ++ pm_message_t state); ++ ++static int mdrvfb0_resume(struct platform_device *pdev); ++#else ++#define mdrvfb0_suspend NULL ++#define mdrvfb0_resume NULL ++#endif ++ ++ ++ ++static int mdrvfb0_probe(struct platform_device *dev); ++static int mdrvfb0_remove(struct platform_device *dev); ++static void mdrvfb0_platform_release(struct device *device); ++/* device .name and driver .name must be the same, then it will call ++ probe function */ ++static struct platform_driver sg_mdrvfb0_driver = ++{ ++ .probe = mdrvfb0_probe, /* initiailize */ ++ .remove = mdrvfb0_remove, /* it free(mem), ++ release framebuffer, free irq etc. */ ++ .suspend = mdrvfb0_suspend, ++ .resume = mdrvfb0_resume, ++ ++ .driver = ++ { ++ .name = "mdrvfb0", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static u64 sg_mdrvfb0_device_lcd_dmamask = 0xffffffffUL; ++/* for 0x08000000 */ ++static struct platform_device sg_mdrvfb0_device = ++{ ++ .name = "mdrvfb0", ++ .id = 0, ++ .dev = ++ { ++ .release = mdrvfb0_platform_release, ++ .dma_mask = &sg_mdrvfb0_device_lcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ +diff --git a/drivers/mstar/fb/infinity/Makefile b/drivers/mstar/fb/infinity/Makefile +new file mode 100644 +index 00000000..20a9473d +--- /dev/null ++++ b/drivers/mstar/fb/infinity/Makefile +@@ -0,0 +1,26 @@ ++# ++# Makefile for MStar fb device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++#--------gop-------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/gop ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/gop/hal ++#--------ge--------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/ge ++EXTRA_CFLAGS += -Idrivers/mstar/fb/cedric/ge/columbus2 ++ ++#EXTRA_CFLAGS += -Idrivers/mstar/gfx ++ ++# specific options ++EXTRA_CFLAGS += ++ ++# files ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop_io.o ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop.o ++#obj-$(CONFIG_MS_FB_INFINITY) += mdrv_fb.o ++ ++obj-$(CONFIG_MS_FB_INFINITY) += infinity_fb.o ++ ++infinity_fb-objs := mdrv_fb.o \ ++ gop/mdrv_gop.o +\ No newline at end of file +diff --git a/drivers/mstar/fb/infinity/gop/Makefile b/drivers/mstar/fb/infinity/gop/Makefile +new file mode 100644 +index 00000000..852db369 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_MS_FB_CEDRIC) += hal/ ++ +diff --git a/drivers/mstar/fb/infinity/gop/hal/cedric_r2.h b/drivers/mstar/fb/infinity/gop/hal/cedric_r2.h +new file mode 100644 +index 00000000..dcd280ab +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/hal/cedric_r2.h +@@ -0,0 +1,439 @@ ++// $Change: 627140 $ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2012 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// cedric_QST.h ++// ++// DESCRIPTION ++// ++// ++// HISTORY ++//----------------------------------------------------------------------------- ++ ++#ifndef __CEDRIC_R2_H__ ++#define __CEDRIC_R2_H__ ++ ++ ++//------------------------------------------------------------------------------ ++// Macro ++//------------------------------------------------------------------------------ ++#include "platform.h" ++ ++#define HK_CNTROL_CAR_BACKING ++//display related ++//rtk qstart related--mailbox ++ ++#define DETECT_METHOD 1 ++// 0 for interrupt from rtk ++// 1 for polling mailbox ++ ++#define QST_ALWAYS_RUN 1 ++ ++ ++#define TOKEN_GET 0x08 ++#define CAR_MODE 0x04 ++ ++ ++#define MBX_TX (0X41) //HOSTKEEPER_MBX ++#define MBX_RX (0x42) //CARBACKING_MBX ++#define MBX_TOUCH_X (0X43) ++#define MBX_TOUCH_Y (0X44) ++ ++ ++#define CEDRIC_BASE_REG_MBX_PA GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x81980) ++#define REG_MBX_BASE GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,0X40) ++#define REG_MBX_RX GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_RX) ++#define REG_MBX_TX GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TX) ++#define REG_MBX_TOUCH_X GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TOUCH_X) ++#define REG_MBX_TOUCH_Y GET_REG_ADDR(CEDRIC_BASE_REG_MBX_PA,MBX_TOUCH_Y) ++ ++ ++#define LOOP_THRESHOLD 8 ++#define CarBackingState (1<<2) ++ ++ ++ ++typedef struct ++{ ++/* ++h0040 h0040 15 0 reg_mb0_0 ++*/ ++ U16 reg_mb0_0; ++ U16 u16REG_RESERVED_40; ++ ++/* ++ ++h0041 h0041 15 0 reg_mb0_1 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_1; /* 00h */ ++ struct ++ { ++ volatile U16 token :4; ++ volatile U16 touch_flag :1; ++ //#define VALID 1 ++ //#define INVALID 0 ++ volatile U16 bt_flag :1; ++ volatile U16 suspend_flag :1; ++ volatile U16 Os_flag :1; ++ volatile U16 boot_type :1; ++ volatile U16 cfg_loaded :1; ++ volatile U16 Os_reset :1; ++ volatile U16 reserve41 :5; ++ //bit 3~f reserve ++ }; ++ }; ++ U16 u16REG_RESERVED_41; ++ ++/* ++ ++h0042 h0042 15 0 reg_mb0_2 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_2; /* 00h */ ++ struct ++ { ++ volatile U16 disp_inited :1; ++ //#define DISP_INIT 1 ++ //#define DISP_NON 0 ++ ++ volatile U16 cvbs_in :1; //represent cvbs in is ok or not ++ //#define CVBS_IN_OK 1 ++ //#define CVBS_IN_NON 0 ++ ++ volatile U16 carbacking_status :1; ++ //value as enum CAR_BACKING_MODE ++ ++ volatile U16 token_switch :1; ++ //#define TOKEN_CP 0 //co processor ++ //#define TOKEN_HK 1 //host keeper ++ volatile U16 app_launch :4; ////max support 15 apps ++ ++ volatile U16 bt_call_rsp :2; // give response to ARM OS ++ ++ volatile U16 mmi_task_running :1; //mmi task exist or not ++ volatile U16 reserve42 :5; ++ ++ }; ++ }; ++ U16 u16REG_RESERVED_42; ++ ++/* ++h0043 h0043 15 0 reg_mb0_3 ++*/ ++ U16 u16MBX_TOUCH_X; ++ U16 u16REG_RESERVED_43; ++ ++/* ++h0044 h0044 15 0 reg_mb0_4 ++*/ ++ U16 u16MBX_TOUCH_Y; ++ U16 u16REG_RESERVED_44; ++ ++/* ++h0045 h0045 15 0 reg_mb0_5 ++*/ ++ union ++ { ++ volatile U16 reg_mb0_5; /* 00h */ ++ struct ++ { ++ volatile U16 rtk_heart :1; ++ volatile U16 reserve45 :15; ++ ++ }; ++ }; ++ U16 u16REG_RESERVED_45; ++ ++/* ++h0046 h0046 15 0 reg_mb0_6 ++*/ ++ U16 reg_mb0_6; ++ U16 u16REG_RESERVED_46; ++ ++/* ++h0047 h0047 15 0 reg_mb0_7 ++*/ ++ U16 reg_mb0_7; ++ U16 u16REG_RESERVED_47; ++ ++/* ++h0048 h0048 15 0 reg_mb0_8 ++*/ ++ U16 reg_mb0_8; ++ U16 u16REG_RESERVED_48; ++ ++/* ++h0049 h0049 15 0 reg_mb0_9 ++*/ ++ U16 reg_mb0_9; ++ U16 u16REG_RESERVED_49; ++ ++/* ++h004a h004a 15 0 reg_mb0_a ++*/ ++ U16 reg_mb0_a; ++ U16 u16REG_RESERVED_4a; ++ ++/* ++h004b h004b 15 0 reg_mb0_b ++*/ ++ U16 reg_mb0_b; ++ U16 u16REG_RESERVED_4b; ++ ++/* ++h004c h004c 15 0 reg_mb0_c ++*/ ++ U16 reg_mb0_c; ++ U16 u16REG_RESERVED_4c; ++ ++/* ++h004d h004d 15 0 reg_mb0_d ++*/ ++ U16 reg_mb0_d; ++ U16 u16REG_RESERVED_4d; ++ ++/* ++h004e h004e 15 0 reg_mb0_e ++*/ ++ U16 reg_mb0_e; ++ U16 u16REG_RESERVED_4e; ++ ++/* ++h004f h004f 15 0 reg_mb0_f ++*/ ++ U16 reg_mb0_f; ++ U16 u16REG_RESERVED_4f; ++ ++/* ++h0050 h0050 15 0 reg_mb0_10 ++*/ ++ U16 reg_mb0_10; ++ U16 u16REG_RESERVED_50; ++ ++/* ++h0051 h0051 15 0 reg_mb0_11 ++*/ ++ U16 reg_mb0_11; ++ U16 u16REG_RESERVED_51; ++ ++/* ++h0052 h0052 15 0 reg_mb0_12 ++*/ ++ U16 reg_mb0_12; ++ U16 u16REG_RESERVED_52; ++ ++/* ++h0053 h0053 15 0 reg_mb0_13 ++*/ ++ U16 reg_mb0_13; ++ U16 u16REG_RESERVED_53; ++ ++/* ++h0054 h0054 15 0 reg_mb0_14 ++*/ ++ U16 reg_mb0_14; ++ U16 u16REG_RESERVED_54; ++ ++/* ++h0055 h0055 15 0 reg_mb0_15 ++*/ ++ U16 reg_mb0_15; ++ U16 u16REG_RESERVED_55; ++ ++/* ++h0056 h0056 15 0 reg_mb0_16 ++*/ ++ U16 reg_mb0_16; ++ U16 u16REG_RESERVED_56; ++ ++/* ++h0057 h0057 15 0 reg_mb0_17 ++*/ ++ U16 reg_mb0_17; ++ U16 u16REG_RESERVED_57; ++ ++/* ++h0058 h0058 15 0 reg_mb0_18 ++*/ ++ U16 reg_mb0_18; ++ U16 u16REG_RESERVED_58; ++ ++/* ++h0059 h0059 15 0 reg_mb0_19 ++*/ ++ U16 reg_mb0_19; ++ U16 u16REG_RESERVED_59; ++ ++/* ++h005A h005A 15 0 reg_mb0_1A ++*/ ++ U16 reg_mb0_1A; ++ U16 u16REG_RESERVED_5a; ++ ++/* ++h005B h005B 15 0 reg_mb0_1B ++*/ ++ U16 reg_mb0_1B; ++ U16 u16REG_RESERVED_5b; ++ ++/* ++h005C h005C 15 0 reg_mb0_1C ++*/ ++ U16 reg_mb0_1C; ++ U16 u16REG_RESERVED_5c; ++ ++/* ++h005D h005D 15 0 reg_mb0_1D ++*/ ++ U16 reg_mb0_1D; ++ U16 u16REG_RESERVED_5d; ++ ++/* ++h005E h005E 15 0 reg_mb0_1E ++*/ ++ U16 reg_mb0_1E; ++ U16 u16REG_RESERVED_5e; ++ ++/* ++h005f h005f 15 0 reg_mb0_1f ++*/ ++ U16 reg_mb0_1f; ++ U16 u16REG_RESERVED_5f; ++ ++/* ++h0060 h0060 15 0 reg_mb0_20 ++*/ ++ U16 reg_mb0_20; ++ U16 u16REG_RESERVED_60; ++ ++/* ++h0061 h0061 15 0 reg_mb0_21 ++*/ ++ U16 reg_mb0_21; ++ U16 u16REG_RESERVED_61; ++ ++/* ++h0062 h0062 15 0 reg_mb0_22 ++*/ ++ U16 reg_mb0_22; ++ U16 u16REG_RESERVED_62; ++ ++/* ++h0063 h0063 15 0 reg_mb0_23 ++*/ ++ U16 reg_mb0_23; ++ U16 u16REG_RESERVED_63; ++ ++/* ++h0064 h0064 15 0 reg_mb0_24 ++*/ ++ U16 reg_mb0_24; ++ U16 u16REG_RESERVED_64; ++ ++/* ++h0065 h0065 15 0 reg_mb0_25 ++*/ ++ U16 reg_mb0_25; ++ U16 u16REG_RESERVED_65; ++ ++/* ++h0066 h0066 15 0 reg_mb0_26 ++*/ ++ U16 reg_mb0_26; ++ U16 u16REG_RESERVED_66; ++ ++/* ++h0067 h0067 15 0 reg_mb0_27 ++*/ ++ U16 reg_mb0_27; ++ U16 u16REG_RESERVED_67; ++ ++/* ++h0068 h0068 15 0 reg_mb0_28 ++*/ ++ U16 reg_mb0_28; ++ U16 u16REG_RESERVED_68; ++ ++/* ++h0069 h0069 15 0 reg_mb0_29 ++*/ ++ U16 reg_mb0_29; ++ U16 u16REG_RESERVED_69; ++ ++/* ++h006A h006A 15 0 reg_mb0_2A ++*/ ++ U16 reg_mb0_2A; ++ U16 u16REG_RESERVED_6a; ++ ++/* ++h006B h006B 15 0 reg_mb0_2B ++*/ ++ U16 reg_mb0_2B; ++ U16 u16REG_RESERVED_6b; ++ ++/* ++h006C h006C 15 0 reg_mb0_2C ++*/ ++ U16 reg_mb0_2C; ++ U16 u16REG_RESERVED_6c; ++ ++/* ++h006D h006D 15 0 reg_mb0_2D ++*/ ++ U16 reg_mb0_2D; ++ U16 u16REG_RESERVED_6d; ++ ++/* ++h006E h006E 15 0 reg_mb0_2E ++*/ ++ U16 reg_mb0_2E; ++ U16 u16REG_RESERVED_6e; ++ ++/* ++h006F h006F 15 0 reg_mb0_2F ++*/ ++ U16 reg_mb0_2F; ++ U16 u16REG_RESERVED_6f; ++ ++/* ++*/ ++}REG_MBX_st,*PREG_MBX_st; ++ ++ ++ ++ ++enum ++{ ++ BACK, ++ FORWARD, ++ DIR_NONE, ++ DIR_NUM = DIR_NONE, ++}; ++enum ++{ ++ NON_event = 0, ++ RTOS_event, ++ USER_event, ++ GOP_refresh_event, ++}; ++ ++enum ++{ ++ HK_PREPARE, ++ HK_START , ++ HK_ALIVE, ++ USR_OP_START, ++ USR_OP_BACK, ++ USR_OP_FORWARD, ++ ++}; ++ ++ ++#endif //__CEDRIC_QST__ +\ No newline at end of file +diff --git a/drivers/mstar/fb/infinity/gop/hal/gop_c2_reg.h b/drivers/mstar/fb/infinity/gop/hal/gop_c2_reg.h +new file mode 100644 +index 00000000..7ae472d9 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/hal/gop_c2_reg.h +@@ -0,0 +1,269 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME gop_c2_reg.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++ ++ ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define COLUMBUS_BASE_REG_RIU_PA (0x1F000000) ++#define CLKG0_REG_BASE_PA (0x100B00) ++ ++#define RIU_BASE (0xA0000000) ++ ++ ++#define CEDRIC_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080F80) ++#define CHICAGO_BASE_REG_GOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x001A80) ++ ++// same as cedric ++#define mdrv_BASE_REG_GOP_PA CEDRIC_BASE_REG_GOP_PA ++ ++#define mdrv_BASE_REG_CHIPTOP_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, 0x080580) ++ ++#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x123000/2)) ++#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x123000/2)) ++#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x123000/2)) ++ ++#define mdrv_REG_GOP31_7E GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x7E) ++#define mdrv_REG_GOP31_7F GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x7F) ++#define mdrv_REG_GOP01_WIN GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x00) ++#define mdrv_REG_GOP31_WIN GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x00) ++#define mdrv_REG_GOP01_ALPHA GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x0A) ++#define mdrv_REG_GOP01_7F GET_REG16_ADDR(mdrv_BASE_REG_GOP01_PA,0x7F) ++#define mdrv_REG_GOP31_ALPHA GET_REG16_ADDR(mdrv_BASE_REG_GOP31_PA,0x0A) ++ ++#define mdrv_GWin0_Disable (0xFFFE) ++#define mdrv_GWIN0_Enable (0x1) ++ ++#define mdrv_ENABLE_CONST_ALPHA (~(0x1<<14)) ++//fomrat define ++ ++#define RGB1555_Blink 0x0000 ++#define RGB565 0x0010 ++#define ARGB4444 0x0020 ++#define _2266 0x0030 ++#define _8Bit_Palette 0x0040 ++ ++#define RGBA8888 0x0050 ++ ++#define ARGB1555 0x0060 ++ ++#define ARGB8888 0x0070 ++ ++#define RGB1555_UV7Y8 0x0080 ++#define UV8Y8 0x0090 ++#define RGBA5551 0x00A0 ++#define RGBA4444 0x00B0 ++ ++//------------------------------------------------------------------------------ ++// GOP ++//------------------------------------------------------------------------------ ++// Bank 0 ++// REG_GOP_00 ++#define GOP_SOFT_RESET 0x0001 ++#define GOP_VS_INV 0x0002 ++#define GOP_HS_INV 0x0004 ++#define GOP_DISPLAY_MODE 0x0008 ++#define GOP_FIELD_INV 0x0010 ++#define GOP_TEST_PATTENR_MODE 0x0040 ++#define GOP_5541_EN 0x0080 // RGB5541 alpha mask mode enable, only for RGB1555 Data type ++#define GOP_REG_OUTPUT_READY 0x0100 ++ ++#define GOP_GENSHOT_FAST 0x0200 ++#define GOP_YUVOUT 0x0400 ++#define GOP_RGB_Transparent_color_enable 0x0800 ++ ++#define GOP_HS_MASK 0x4000 ++#define GOP_ALPHA_INV 0x8000 ++ ++#define GOP_ALPHA_MASK 0x7F00 ++#define GOP_ALPHA 0x3F00 ++#define GOP_PIXEL_ALPHA_EN 0x4000 ++ ++#define GWIN_display_mode_progress 0x0008 ++#define GWIN_display_mode_interlace 0x0000 ++ ++ ++// REG_GOP_01 ++#define GOP_DST_IP_MAIN 0x0000 ++#define GOP_DST_IP_SUB 0x0001 ++#define GOP_DST_OP 0x0002 ++#define GOP_DST_MVOP 0x0003 ++#define GOP_DST_SC1_IP_MAIN 0x0004 ++#define GOP_DST_SC1_OP 0x0005 ++ ++ ++ ++#define GOP_DMA_LEN_8 0x0000 ++#define GOP_DMA_LEN_16 0x0004 ++#define GOP_DMA_LEN_32 0x0008 ++#define GOP_DMA_LEN_ALL 0x000C ++#define GOP_MIU_TSH_1 0x0010 ++#define GOP_REGDMA_INTERVAL_START 0x0200 //cedric:0x0300 ++#define GOP_REGDMA_INTERVAL_END 0x4000 //cedirc:0x5000 ++ ++// REG_GOP_02 ++#define GOP_BLINK_DISABLE 0x0000 ++#define GOP_BLINK_ENABLE 0x8000 ++ ++// REG_GOP_06 ++#define GOP_REGDMA_END 0x0034 ++ ++// REG_GOP_07 ++#define GOP_REGDMA_STR 0x0000 ++ ++//REG_GOP_0F ++ ++ ++#define AMBER3_GOP_HSYNC_PIPE_DLY 0x00E5 ++#define CEDRIC_GOP_HSYNC_PIPE_DLY 0x0070 ++#define AMBER3_GOP_HSYNC_PIPE_DLY 0x00E5 ++#define CEDRIC_GOP_HSYNC_PIPE_DLY 0x0070 ++#define CHICAGO_GOP_HSYNC_PIPE_DLY 0x000B ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++#define GOP_HSYNC_PIPE_DLY_FOR_SC1_OP 0x00A0 ++#define HSYNC_PIPE_DLY_FOR_SC0_2GOP 0x0044 ++ ++ ++ ++// inifinity settings ++#define INIFINITY_GOP_HSYNC_PIPE_DLY 0x0000 ++#define GOP_HSYNC_PIPE_DLY INIFINITY_GOP_HSYNC_PIPE_DLY ++ ++ ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++ ++// REG_GOP_20 ++#define GOP_GWIN_HIGH_PRI_0 0x0000 ++#define GOP_GWIN_HIGH_PRI_1 0x0001 ++ ++ ++ ++#define GOP_STRETCH_HST 0x0000 ++ ++ ++// REG_GOP_34 ++#define GOP_STRETCH_VST 0x0000 ++ ++// REG_GOP_35 ++#define GOP_STRETCH_HRATIO 0x1000 ++ ++// REG_GOP_36 ++#define GOP_STRETCH_VRATIO 0x1000 ++ ++// REG_GOP_38 ++#define GOP_STRETCH_HINI 0x0000 ++ ++// REG_GOP_39 ++#define GOP_STRETCH_VINI 0x0000 ++ ++// REG_GOP_7E ++#define GOP_GOPG0_MUX_MASK 0x0007 ++#define GOP_GOPG0_MUX_4G 0x0000 ++#define GOP_GOPG0_MUX_2G 0x0001 ++ ++#define GOP_Layer0_MUX_MASK 0x0007 ++#define GOP_Layer0_Sel_GOP0 0x0000 ++#define GOP_Layer0_Sel_GOP1 0x0001 ++#define GOP_Layer0_Sel_GOP2 0x0002 ++#define GOP_Layer0_Sel_GOP3 0x0003 ++#define GOP_Layer0_Sel_GOP_Null 0x0004 ++ ++#define GOP_Layer1_MUX_MASK (0x0007)<<3 ++#define GOP_Layer1_Sel_GOP0 (0x0000)<<3 ++#define GOP_Layer1_Sel_GOP1 (0x0001)<<3 ++#define GOP_Layer1_Sel_GOP2 (0x0002)<<3 ++#define GOP_Layer1_Sel_GOP3 (0x0003)<<3 ++#define GOP_Layer1_Sel_GOP_Null (0x0004)<<3 ++ ++#define GOP_Layer2_MUX_MASK (0x0007)<<6 ++#define GOP_Layer2_Sel_GOP0 (0x0000)<<6 ++#define GOP_Layer2_Sel_GOP1 (0x0001)<<6 ++#define GOP_Layer2_Sel_GOP2 (0x0002)<<6 ++#define GOP_Layer2_Sel_GOP3 (0x0003)<<6 ++#define GOP_Layer2_Sel_GOP_Null (0x0004)<<6 ++ ++#define GOP_Layer3_MUX_MASK (0x0007)<<9 ++#define GOP_Layer3_Sel_GOP0 (0x0000)<<9 ++#define GOP_Layer3_Sel_GOP1 (0x0001)<<9 ++#define GOP_Layer3_Sel_GOP2 (0x0002)<<9 ++#define GOP_Layer3_Sel_GOP3 (0x0003)<<9 ++#define GOP_Layer3_Sel_GOP_Null (0x0004)<<9 ++ ++ ++ ++ ++ ++// REG_GOP_7F ++#define GOP_BANK_G0_0 0x0000 ++#define GOP_BANK_G0_1 0x0001 ++#define GOP_BANK_G1_0 0x0003 ++#define GOP_BANK_G1_1 0x0004 ++#define GOP_BANK_G2_0 0x0006 ++#define GOP_BANK_G2_1 0x0007 ++#define GOP_BANK_G3_0 0x0009 ++#define GOP_BANK_G3_1 0x000A ++#define GOP_BANK_GPD 0x0006 ++ ++#define GOP_BANK_DOUBLE_WR 0x0100 ++#define GOP_BANK_FORCE_WR 0x0200 ++ ++#define GOP_BANK_DOUBLE_WR_G0 0x0400 ++#define GOP_BANK_DOUBLE_WR_G1 0x0403 ++#define GOP_BANK_DOUBLE_WR_G2 0x0406 ++#define GOP_BANK_DOUBLE_WR_G3 0x0409 ++#define GOP_BANK_DOUBLE_WR_MSK 0x0400 ++#define GOP_BANK_SEL_MSK 0x000F ++// GOP0 Bank 1 ++// REG_GOP_00 ++#define GOP0_GWin0_Enable 0x0001 ++ ++// REG_GOP_20 ++#define GOP0_GWin1_Enable 0x0001 ++ ++ ++ ++ ++// Chip Device ID ++#define DEVICE_COLUMBUS2 (0x2E) ++#define DEVICE_AMBER3 (0x47) ++#define DEVICE_CEDRIC (0x50) ++#define DEVICE_CHICAGO (0x70) ++ ++ +diff --git a/drivers/mstar/fb/infinity/gop/hal/platform.h b/drivers/mstar/fb/infinity/gop/hal/platform.h +new file mode 100644 +index 00000000..e04d58fd +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/hal/platform.h +@@ -0,0 +1,189 @@ ++#ifndef __PLATFORM_H__ ++#define __PLATFORM_H__ ++ ++//------------------------------------------------------------------------------ ++// Include Files ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Macros ++//------------------------------------------------------------------------------ ++#define MIU0_BUS_ADDR 0x40000000 ++#define MIU1_MASK 0x00000000 //use (ADDR & MIU1_MASK) to check if ADDR is in MIU1 after calling ms_mem_bus_to_MIU() ++ ++ ++#define IO_PHYS 0x1F000000 ++#define IO_OFFSET 0xDE000000 ++#define IO_SIZE 0x00400000 ++#define IO_VIRT (IO_PHYS + IO_OFFSET) ++#define io_p2v(pa) ((pa) + IO_OFFSET) ++#define io_v2p(va) ((va) - IO_OFFSET) ++//#define IO_ADDRESS(x) io_p2v((unsigned int)x) ++ ++ ++#define PERI_PHYS 0x16000000 ++#define PERI_OFFSET 0xE6000000 ++#define PERI_SIZE 0x2000 ++#define PERI_VIRT (PERI_PHYS + PERI_OFFSET) ++#define peri_p2v(pa) ((pa) + PERI_OFFSET) ++#define peri_v2p(va) ((va) - PERI_OFFSET) ++#define PERI_ADDRESS(x) peri_p2v(x) ++ ++#define PERI_W(a,v) (*(volatile unsigned int *)PERI_ADDRESS(a)=v) ++#define PERI_R(a) (*(volatile unsigned int *)PERI_ADDRESS(a)) ++ ++#define SCU_PHYS (PERI_PHYS) ++ ++#define L2_CACHE_PHYS 0x15000000 ++#define L2_CACHE_OFFSET 0xE7003000 ++#define L2_CACHE_SIZE 0x1000 ++#define L2_CACHE_VIRT (L2_CACHE_PHYS + L2_CACHE_OFFSET) ++#define L2_CACHE_p2v(pa) ((pa) + L2_CACHE_OFFSET) ++#define L2_CACHE_v2p(va) ((va) - L2_CACHE_OFFSET) ++#define L2_CACHE_ADDRESS(x) L2_CACHE_p2v(x) ++ ++#define L2_CACHE_write(v,a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a) = (v)) ++#define L2_CACHE_read(a) (*(volatile unsigned int *)L2_CACHE_ADDRESS(a)) ++ ++ ++#define IMI_PHYS 0xE0000000 ++#define IMI_OFFSET 0x1C005000 ++#define IMI_SIZE 0x50000 ++#define IMI_VIRT (IMI_PHYS + IMI_OFFSET) ++#define imi_p2v(pa) ((pa) + IMI_OFFSET) ++#define imi_v2p(va) ((va) - IMI_OFFSET) ++#define IMI_ADDRESS(x) imi_p2v((unsigned int)x) ++ ++ ++ ++ ++// Register macros ++#define GET_REG_ADDR(x, y) ((x) + ((y) << 2)) ++ ++ ++/* read register by byte */ ++#define ms_readb(a) (*(volatile unsigned char *)IO_ADDRESS(a)) ++ ++/* read register by word */ ++#define ms_readw(a) (*(volatile unsigned short *)IO_ADDRESS(a)) ++ ++/* read register by long */ ++#define ms_readl(a) (*(volatile unsigned int *)IO_ADDRESS(a)) ++ ++/* write register by byte */ ++#define ms_writeb(v,a) (*(volatile unsigned char *)IO_ADDRESS(a) = (v)) ++ ++/* write register by word */ ++#define ms_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) ++ ++/* write register by long */ ++#define ms_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Macros: INREGx/OUTREGx/SETREGx/CLRREGx ++// ++// This macros encapsulates basic I/O operations. ++// Memory address space operation is used on all platforms. ++// ++#define INREG8(x) ms_readb(x) ++#define OUTREG8(x, y) ms_writeb((u8)(y), x) ++#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y)) ++#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y)) ++#define INREGMSK8(x, y) (INREG8(x) & (y)) ++#define OUTREGMSK8(x, y, z) OUTREG8(x, ((INREG8(x)&~(z))|((y)&(z)))) ++ ++#define INREG16(x) ms_readw(x) ++#define OUTREG16(x, y) ms_writew((u16)(y), x) ++#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y)) ++#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y)) ++#define INREGMSK16(x, y) (INREG16(x) & (y)) ++#define OUTREGMSK16(x, y, z) OUTREG16(x, ((INREG16(x)&~(z))|((y)&(z)))) ++ ++#define INREG32(x) ms_readl(x) ++#define OUTREG32(x, y) ms_writel((u32)(y), x) ++#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y)) ++#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y)) ++#define INREGMSK32(x, y) (INREG32(x) & (y)) ++#define OUTREGMSK32(x, y, z) OUTREG32(x, ((INREG32(x)&~(z))|((y)&(z)))) ++ ++ ++#define PM_READ32(x) ((((unsigned int)INREG16(x+4)<<16)&0xFFFF0000) | (INREG16(x) & 0x0000FFFF)) ++#define PM_WRITE32(x,y) do{OUTREG16(x,(y&0x0000FFFF));OUTREG16((x+4),((y>>16)&0x0000FFFF));}while(0) ++ ++#define XTAL_26000K 26000000 ++#define XTAL_24000K 24000000 ++#define XTAL_16369K 16369000 ++#define XTAL_16367K 16367000 ++ ++#define CPU_ID_CORE0 0x0 ++#define CPU_ID_CORE1 0x1 ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Define: MSBASE_REG_RIU_PA ++// ++// Locates the RIU register base. ++// ++#define MS_BASE_REG_RIU_PA IO_PHYS ++ ++ ++ ++extern unsigned long long ms_mem_bus_to_phys(unsigned long long x); ++extern unsigned long long ms_mem_phys_to_bus(unsigned long long x); ++extern unsigned long long ms_mem_bus_to_MIU(unsigned long long x); ++extern unsigned long long ms_mem_MIU_to_bus(unsigned long long x); ++ ++typedef enum ++{ ++ DEVINFO_BOOT_TYPE_SPI=0x01, ++ DEVINFO_BOOT_TYPE_EMMC=0x02, ++ DEVINFO_BOOT_TYPE_8051=0x03, ++}DEVINFO_BOOT_TYPE; ++ ++typedef enum ++{ ++ DEVINFO_PANEL_070_DEFAULT = 0x0, ++ DEVINFO_PANEL_HSD_070I_DW1 = 0x01, ++ DEVINFO_PANEL_HSD_070P_FW3 = 0x02, ++ DEVINFO_PANEL_AT_102_03TT91 = 0x03, ++ DEVINFO_PANEL_HSD_062I_DW1 = 0x04, ++ DEVINFO_PANEL_HSD_070I_DW2 = 0x05, ++ DEVINFO_PANEL_HSD_LVDS_800480= 0x06, ++ DEVINFO_PANEL_N070ICG_LD1 =0x08, ++ DEVINFO_PANEL_HSD_062I_DW2 = 0x09, ++ DEVINFO_PANEL_HSD_070I_MODE2 = 0x0a, ++ E_PANEL_UNKNOWN = 0xFF ++}DEVINFO_PANEL_TYPE; ++ ++ ++typedef enum ++{ ++ DEVINFO_BD_MST154A_D01A_S = 0x0801, ++ DEVINFO_BD_MST786_SZDEMO = 0x0802, ++ DEVINFO_BD_MST786_CUSTOM10 = 0x0810, ++ DEVINFO_BD_MST786_CUSTOM20 = 0x0820, ++ DEVINFO_BD_MST786_CUSTOM30 = 0x0830, ++ E_BD_UNKNOWN = 0xFFFF ++}DEVINFO_BOARD_TYPE; ++ ++typedef enum ++{ ++ DEVINFO_RTK_FLAG_0 = 0x0, ++ DEVINFO_RTK_FLAG_1 = 0x01, ++ E_RTK_UNKNOWN = 0xFFFF ++}DEVINFO_RTK_FLAG; ++ ++typedef struct ++{ ++ char name[16]; ++ unsigned long start; //MIU Address ++ unsigned long length; ++ unsigned long flag0; ++ unsigned long flag1; //Kernel Virtual Address ++} MS_MEM_INFO; ++ ++ ++#endif +diff --git a/drivers/mstar/fb/infinity/gop/mdrv_gop.c b/drivers/mstar/fb/infinity/gop/mdrv_gop.c +new file mode 100644 +index 00000000..0715c768 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/mdrv_gop.c +@@ -0,0 +1,794 @@ ++ ++#include "mdrv_gop.h" ++ ++unsigned long long ms_mem_bus_to_MIU(unsigned long long x) ++{ ++ #define MIU0_BUS_ADDR 0x40000000 ++ ++ return ((x) - MIU0_BUS_ADDR); ++} ++ ++ ++U32 OALReadDeviceId(U32 devId) ++{ ++ U16 tmp = 0; ++ // need to refine for another SOC ++ tmp = 0x50; //C3 ++ return tmp; ++} ++ ++void SwitchSubBank(int subbank) ++{ ++ unsigned long GOP_Reg_Base; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ if (subbank==1) ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,0x0001); ++ else if (subbank==0) ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,0x0000); ++ else ++ GOPDBG( "GOP: Wrong Subbank in SwitchSubBank \n"); ++} ++ ++ ++ ++U16 GOP_MIU_BUS(U16 MIU_BUS) ++{ ++ // A3: MIU Bus = 0x5; ++ // C2: MIU Bus = 0x3; ++ // C3: MIU Bus = 0x4; ++ // C4: MIU Bus = 0x3; ++ // Need to check with HW team ++ ++ U32 devId=0; ++ ++ devId=OALReadDeviceId(devId); ++ ++ if(DEVICE_AMBER3==devId) ++ { ++ GOPDBG("***** devId is AMBER3 *****\r\n"); ++ MIU_BUS = 5; ++ } ++ else if(DEVICE_CEDRIC==devId) ++ { ++ GOPDBG("***** devId is CEDRIC *****\r\n"); ++ MIU_BUS = 0x4; ++ } ++ else if(DEVICE_CHICAGO==devId) ++ { ++ GOPDBG("***** devId is DEVICE_CHICAGO *****\r\n"); ++ MIU_BUS = 0x3; ++ } ++ else ++ { ++ GOPDBG("***** devId UNKNOWN *****\r\n"); ++ MIU_BUS = 0x4; ++ ++ } ++ ++ GOPDBG("GOP_MIU_BUS devId is %d BUS is %d \n",devId,MIU_BUS); ++ ++ ++ return MIU_BUS; ++} ++ ++ ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr ) ++{ ++ ++ U32 FB_add = FB_Start_Addr; ++ ++ U32 s32BuffAddr=0; ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA ; ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ //FB_add = (U32)ms_mem_bus_to_MIU(FB_add);//old way ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//new way ++ ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ ++ GOPDBG ("GOP_Pan_Display: in \r\n"); ++ ++ // 1 GOP fetch framebuffer information ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ GOPDBG ("GOP_Pan_Display: out \r\n"); ++} ++ ++void GOP_Change_Alpha(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ //U16 FB_WIDTH=Panel_Width; ++ //U16 FB_HEIGHT=Panel_Height; ++ ++ ++ //U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ //U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ //U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ //U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ //U16 u16DispImage_HStart=0; ++ //U16 u16DispImage_HSize=FB_WIDTH; ++ //U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ //U16 u16DispImage_VStart=000; ++ //U16 u16DispImage_VSize=FB_HEIGHT; ++ //U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ //U32 s32BuffAddr=0; ++ //U32 u32TempVal=0; ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ //U16 DISPLAY_Format=Pixel_Format; ++ ++ //FB_add = (U32)ms_mem_bus_to_MIU(FB_add);//old way ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//new way ++ ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // infinity has only one screen ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Setmode( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ ++ ++ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart=0; ++ U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart=000; ++ U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 MIU_BUS=0x04; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ //FB_add = (U32)ms_mem_bus_to_MIU(FB_add);//old way ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//new way ++ ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ // infinity has only one screen ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ ++ GOPDBG ("GOP_Setmode: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // GOP Global seting ; destination, Hsync ++ // infinity has only one screen ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); // Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); // Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1); // miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010); // insert fake rdy between hs & valid rdy ++ ++ // set gop dma burst length ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, 0x1F00, 0x1F00); ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++ ++ // infinity has only one screen ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // set GOP switch from scaler initially open ++ //OUTREGMSK16(GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0001,0x0001); ++ ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null); ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Setmode_Stretch_H( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut, int StretchRatio) ++{ ++ ++ // 1. GOP Hardware initial ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Set Stretch Ratio for GOP Display ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart=0; ++ U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd=u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart=000; ++ U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd=u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 MIU_BUS=0x04; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ //FB_add = (U32)ms_mem_bus_to_MIU(FB_add);//old way ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//new way ++ ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++ GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ ++ // infinity has only one screen ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ ++ GOPDBG ("GOP_Setmode_Stretch: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode_Stretch: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode_Stretch: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode_Stretch: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode_Stretch: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode_Stretch: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ GOPDBG ("GOP_Setmode_Stretch: FB_StretchRatio = [%x] \r\n",StretchRatio); ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // GOP Global seting ; destination, Hsync ++ // infinity has only one screen ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,(Panel_Width >>1)); // Stretch Window H size (unit:2 pixel), for Stretch Ratio: Window/2/Ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); // Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO/StretchRatio); // Stretch H ratio, val=0x1000/StretchRatio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1); // miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010); // insert fake rdy between hs & valid rdy ++ ++ // set gop dma burst length ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, 0x1F00, 0x1F00); ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++ ++ // infinity has only one screen ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // set GOP switch from scaler initially open ++ //OUTREGMSK16(GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0001,0x0001); ++ ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null); ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++ ++void GOP_Set_OutFormat(int screen, int byuvoutput) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ GOPDBG("GOP_Set_OutFormat: screen:%d, byuvoutput:%d\n", screen, byuvoutput); ++ ++ if(byuvoutput) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_YUVOUT, GOP_YUVOUT); ++ ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP_YUVOUT); ++ } ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++} ++ ++ ++ ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetConstatnAlpha: screen:%d, bEn:%d, alpha:%x\n", screen, bEn, alpha); ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // alpha inv ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : 0x8000), 0x8000); ++ ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ // constant or pixel alpha ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : 0x4000), 0x4000); ++ ++ // alhap value ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_0A, (bEn ? alpha : 0x0000), 0x00FF); ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ ++} ++ ++ ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetColorKey: screen:%d, bEn:%d, (%x %x %x)\n", screen, bEn, u8R, u8G, u8B); ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ if(bEn) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0800, 0x0800); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_24, (u8B|(u8G<<8)), 0xFFFF); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_25, u8R, 0x00FF); ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0000, 0x0800); ++ } ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++void GOP_Set_PipeDelay(int screen, int delay) ++{ ++ U16 pipe_delay = 0x00; ++ ++ U32 GOP_Reg_Base; ++ ++ U16 GOP_Reg_DB; ++ ++ // infinity has only one screen ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ if (screen == 0) ++ { ++ pipe_delay = 0x50 + delay; ++ } ++ else if (screen == 1) ++ { ++ pipe_delay = 0x2E + delay; ++ } ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F, pipe_delay); ++ ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++} ++ ++ ++void GOP_Setmode_and_win( ++ int bResume, int Screen, ++ int H_Start, int V_Start, ++ int H_End, int V_End, ++ int Panel_Width, int Panel_Height, ++ U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, ++ int bInterlaceOut) ++{ ++ ++ ++ ++ // 1. GOP Hardware initail (need to check Chip top colok) ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Initial Mux for Select GOP and Sclaer(MApi_XC_ip_sel_for_gop) ++ ++ ++ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH=Panel_Width; ++ U16 FB_HEIGHT=Panel_Height; ++ ++ ++ U16 FB_Bytes_Per_Pixel=Bytes_Per_Pixel; ++ ++ U16 u16FrameBuffer_HSize=FB_WIDTH;//LCD_PANEL_WIDTH; ++ U16 u16FrameBuffer_VSize= FB_HEIGHT;//mdrvgop_Get_Panel_Height();//mdrvgop_Get_Panel_HeightYRES;//LCD_PANEL_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel=FB_Bytes_Per_Pixel; ++ ++ U16 u16DispImage_HStart= H_Start; ++ //U16 u16DispImage_HSize=FB_WIDTH; ++ U16 u16DispImage_HEnd= H_End; //u16DispImage_HStart+u16DispImage_HSize; ++ ++ U16 u16DispImage_VStart= bInterlaceOut ? V_Start/2 : V_Start; ++ //U16 u16DispImage_VSize=FB_HEIGHT; ++ U16 u16DispImage_VEnd= bInterlaceOut ? V_End/2 : V_End; //u16DispImage_VStart+u16DispImage_VSize; ++ ++ U32 s32BuffAddr=0; ++ U32 u32TempVal=0; ++ ++ U32 devId=0x50; ++ ++ ++ U16 MIU_BUS=0x04; ++ ++ U32 GOP_Reg_Base; ++ U16 GOP_Reg_DB; ++ ++ U16 GOP_block_0=GOP_BANK_G0_0; ++ U16 GOP_block_1=GOP_BANK_G0_1; ++ U16 DISPLAY_Format=Pixel_Format; ++ ++ //FB_add = (U32)ms_mem_bus_to_MIU(FB_add);//old way ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//new way ++ ++ MIU_BUS= GOP_MIU_BUS(MIU_BUS); ++ devId = OALReadDeviceId(devId); ++ ++ GOPDBG("screen:%d, pixel_format:%d, binter:%d\n", Screen, Pixel_Format, bInterlaceOut); ++ ++ GOP_Reg_DB = Screen == 0 ? GOP_BANK_DOUBLE_WR_G0 : GOP_BANK_DOUBLE_WR_G1; ++ ++ // infinity has only one screen ++ GOP_block_0=GOP_BANK_G0_0; ++ GOP_block_1=GOP_BANK_G0_1; ++ ++ ++ GOPDBG ("GOP_Setmode: LCD_PANEL_WIDTH = [%d] \r\n",Panel_Width); ++ GOPDBG ("GOP_Setmode: LCD_PANEL_HEIGHT = [%d] \r\n",Panel_Height); ++ GOPDBG ("GOP_Setmode: FB_WIDTH = [%d] \r\n",FB_WIDTH); ++ GOPDBG ("GOP_Setmode: FB_HEIGHT = [%d] \r\n",FB_HEIGHT); ++ GOPDBG ("GOP_Setmode: FB_add = [%x] \r\n",FB_add); ++ GOPDBG ("GOP_Setmode: FB_Start_Addr = [%x] \r\n",FB_Start_Addr); ++ ++ // infinity has only one screen ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // infinity has only one screen ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV); // ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV); // PerPixel alpha 0x3F, RGB8888, enable ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_DST_OP|GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY);//Hsync input pipe delay ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE); ++ ++ // GOP : Display Area global seting ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST);// Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); // Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ //1 GOP fetch framebuffer information ++ // 1.0 framebuffer Data format ++ ++ // infinity has only one screen ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN); ++ ++ ++ // 1.1 framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr=s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr=s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); // Ring block start Low address 0x21:16 ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); // Ring block start Hi address 0x22:6, page number ++ ++ // 1.2 framebuffer Pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS); // Ring block 0 line size ++ ++ // 1.4 framebuffer Size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // 1.5 frame buffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // 1.6 frame buffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ //2 GOP Display Setting ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ // 2.3 Display Area setting in Panel ++ CLRREG16(GOP_Reg_Base+REG_GOP_7E,GOP_GOPG0_MUX_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_7E,GOP_Layer1_Sel_GOP_Null|GOP_Layer0_Sel_GOP3); ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ ++} ++//MODULE_LICENSE("GPL") +diff --git a/drivers/mstar/fb/infinity/gop/mdrv_gop.h b/drivers/mstar/fb/infinity/gop/mdrv_gop.h +new file mode 100644 +index 00000000..5289dd03 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/mdrv_gop.h +@@ -0,0 +1,265 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_gop.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++ ++#include "hal/gop_c2_reg.h" ++ ++ ++#define CHIPTOP_REG_BASE_PA (0x101E00) ++#define SC_REG_BASE_PA (0x130000) ++#define LPLL_REG_BASE_PA (0x103100) ++#define CLKG0_REG_BASE_PA (0x100B00) ++#define MOD_REG_BASE_PA (0x103200) ++#define GPIO0_REG_BASE_PA (0x102B00) ++#define GPIO1_REG_BASE_PA (0x101A00) ++ ++#define GOP_DEBUG 0 ++#if (GOP_DEBUG==1) ++#define GOPDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOPDBG(fmt, arg...) ++#endif ++ ++ ++//#define GOPIO_DEBUG_ENABLE ++ ++#define GOP_DBG_LV_IOCTL 0 ++#define GOP_DBG_LV_0 1 ++ ++ ++#ifdef GOPIO_DEBUG_ENABLE ++#define GOPIO_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define GOP_DBG(dbglv, _fmt, _args...) \ ++ do \ ++ if(dbglv) \ ++ { \ ++ printk(KERN_WARNING _fmt, ## _args); \ ++ }while(0) ++ ++#else ++#define GOPIO_ASSERT(arg) ++#define GOP_DBG(dbglv, _fmt, _args...) ++ ++#endif ++ ++#define BK_REG(reg) ((reg) * 4) ++ ++/* ---------------------------------------------------------------------------- ++ * GOP_OFFSET ++ * ---------------------------------------------------------------------------- ++ */ ++#define REG_GOP_00 BK_REG(0x00) ++#define REG_GOP_01 BK_REG(0x01) ++#define REG_GOP_02 BK_REG(0x02) ++#define REG_GOP_03 BK_REG(0x03) ++#define REG_GOP_04 BK_REG(0x04) ++#define REG_GOP_05 BK_REG(0x05) ++#define REG_GOP_06 BK_REG(0x06) ++#define REG_GOP_07 BK_REG(0x07) ++#define REG_GOP_08 BK_REG(0x08) ++#define REG_GOP_09 BK_REG(0x09) ++#define REG_GOP_0A BK_REG(0x0A) ++#define REG_GOP_0B BK_REG(0x0B) ++#define REG_GOP_0C BK_REG(0x0C) ++#define REG_GOP_0D BK_REG(0x0D) ++#define REG_GOP_0E BK_REG(0x0E) ++#define REG_GOP_0F BK_REG(0x0F) ++ ++ ++#define REG_GOP_10 BK_REG(0x10) ++#define REG_GOP_11 BK_REG(0x11) ++#define REG_GOP_12 BK_REG(0x12) ++#define REG_GOP_13 BK_REG(0x13) ++#define REG_GOP_14 BK_REG(0x14) ++#define REG_GOP_15 BK_REG(0x15) ++#define REG_GOP_16 BK_REG(0x16) ++#define REG_GOP_17 BK_REG(0x17) ++#define REG_GOP_18 BK_REG(0x18) ++#define REG_GOP_19 BK_REG(0x19) ++#define REG_GOP_1A BK_REG(0x1A) ++#define REG_GOP_1B BK_REG(0x1B) ++#define REG_GOP_1C BK_REG(0x1C) ++#define REG_GOP_1D BK_REG(0x1D) ++#define REG_GOP_1E BK_REG(0x1E) ++#define REG_GOP_1F BK_REG(0x1F) ++ ++#define REG_GOP_20 BK_REG(0x20) ++#define REG_GOP_21 BK_REG(0x21) ++#define REG_GOP_22 BK_REG(0x22) ++#define REG_GOP_23 BK_REG(0x23) ++#define REG_GOP_24 BK_REG(0x24) ++#define REG_GOP_25 BK_REG(0x25) ++#define REG_GOP_26 BK_REG(0x26) ++#define REG_GOP_27 BK_REG(0x27) ++#define REG_GOP_28 BK_REG(0x28) ++#define REG_GOP_29 BK_REG(0x29) ++#define REG_GOP_2A BK_REG(0x2A) ++#define REG_GOP_2B BK_REG(0x2B) ++#define REG_GOP_2C BK_REG(0x2C) ++#define REG_GOP_2D BK_REG(0x2D) ++#define REG_GOP_2E BK_REG(0x2E) ++#define REG_GOP_2F BK_REG(0x2F) ++ ++ ++#define REG_GOP_30 BK_REG(0x30) ++#define REG_GOP_31 BK_REG(0x31) ++#define REG_GOP_32 BK_REG(0x32) ++#define REG_GOP_33 BK_REG(0x33) ++#define REG_GOP_34 BK_REG(0x34) ++#define REG_GOP_35 BK_REG(0x35) ++#define REG_GOP_36 BK_REG(0x36) ++#define REG_GOP_37 BK_REG(0x37) ++#define REG_GOP_38 BK_REG(0x38) ++#define REG_GOP_39 BK_REG(0x39) ++#define REG_GOP_3A BK_REG(0x3A) ++#define REG_GOP_3B BK_REG(0x3B) ++#define REG_GOP_3C BK_REG(0x3C) ++#define REG_GOP_3D BK_REG(0x3D) ++#define REG_GOP_3E BK_REG(0x3E) ++#define REG_GOP_3F BK_REG(0x3F) ++ ++ ++#define REG_GOP_40 BK_REG(0x40) ++#define REG_GOP_41 BK_REG(0x41) ++#define REG_GOP_42 BK_REG(0x42) ++#define REG_GOP_43 BK_REG(0x43) ++#define REG_GOP_44 BK_REG(0x44) ++#define REG_GOP_45 BK_REG(0x45) ++#define REG_GOP_46 BK_REG(0x46) ++#define REG_GOP_47 BK_REG(0x47) ++#define REG_GOP_48 BK_REG(0x48) ++#define REG_GOP_49 BK_REG(0x49) ++#define REG_GOP_4A BK_REG(0x4A) ++#define REG_GOP_4B BK_REG(0x4B) ++#define REG_GOP_4C BK_REG(0x4C) ++#define REG_GOP_4D BK_REG(0x4D) ++#define REG_GOP_4E BK_REG(0x4E) ++#define REG_GOP_4F BK_REG(0x4F) ++ ++ ++#define REG_GOP_50 BK_REG(0x50) ++#define REG_GOP_51 BK_REG(0x51) ++#define REG_GOP_52 BK_REG(0x52) ++#define REG_GOP_53 BK_REG(0x53) ++#define REG_GOP_54 BK_REG(0x54) ++#define REG_GOP_55 BK_REG(0x55) ++#define REG_GOP_56 BK_REG(0x56) ++#define REG_GOP_57 BK_REG(0x57) ++#define REG_GOP_58 BK_REG(0x58) ++#define REG_GOP_59 BK_REG(0x59) ++#define REG_GOP_5A BK_REG(0x5A) ++#define REG_GOP_5B BK_REG(0x5B) ++#define REG_GOP_5C BK_REG(0x5C) ++#define REG_GOP_5D BK_REG(0x5D) ++#define REG_GOP_5E BK_REG(0x5E) ++#define REG_GOP_5F BK_REG(0x5F) ++ ++ ++#define REG_GOP_60 BK_REG(0x60) ++#define REG_GOP_61 BK_REG(0x61) ++#define REG_GOP_62 BK_REG(0x62) ++#define REG_GOP_63 BK_REG(0x63) ++#define REG_GOP_64 BK_REG(0x64) ++#define REG_GOP_65 BK_REG(0x65) ++#define REG_GOP_66 BK_REG(0x66) ++#define REG_GOP_67 BK_REG(0x67) ++#define REG_GOP_68 BK_REG(0x68) ++#define REG_GOP_69 BK_REG(0x69) ++#define REG_GOP_6A BK_REG(0x6A) ++#define REG_GOP_6B BK_REG(0x6B) ++#define REG_GOP_6C BK_REG(0x6C) ++#define REG_GOP_6D BK_REG(0x6D) ++#define REG_GOP_6E BK_REG(0x6E) ++#define REG_GOP_6F BK_REG(0x6F) ++ ++ ++#define REG_GOP_70 BK_REG(0x70) ++#define REG_GOP_71 BK_REG(0x71) ++#define REG_GOP_72 BK_REG(0x72) ++#define REG_GOP_73 BK_REG(0x73) ++#define REG_GOP_74 BK_REG(0x74) ++#define REG_GOP_75 BK_REG(0x75) ++#define REG_GOP_76 BK_REG(0x76) ++#define REG_GOP_77 BK_REG(0x77) ++#define REG_GOP_78 BK_REG(0x78) ++#define REG_GOP_79 BK_REG(0x79) ++#define REG_GOP_7A BK_REG(0x7A) ++#define REG_GOP_7B BK_REG(0x7B) ++#define REG_GOP_7C BK_REG(0x7C) ++#define REG_GOP_7D BK_REG(0x7D) ++#define REG_GOP_7E BK_REG(0x7E) ++#define REG_GOP_7F BK_REG(0x7F) ++ ++void SwitchSubBank(int subbank); ++ ++void GOP_Setmode(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++void GOP_Setmode_Stretch_H(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut, int StretchRatio); ++ ++void GOP_Change_Alpha(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr); ++void GOP_Set_OutFormat(int screen, int byuvoutput); ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha); ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B); ++void GOP_Set_PipeDelay(int screen, int delay); ++void GOP_Setmode_and_win(int bResume, int Screen, int H_Start, int V_Start, int H_End, int V_End, int Panel_Width, int Panel_Height, U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); +diff --git a/drivers/mstar/fb/infinity/gop/mdrv_gop_io.c b/drivers/mstar/fb/infinity/gop/mdrv_gop_io.c +new file mode 100644 +index 00000000..0b86aa12 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/mdrv_gop_io.c +@@ -0,0 +1,415 @@ ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include /* for dma_alloc_coherent */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_gop.h" ++#include "mdrv_gop_io.h" ++ ++#define MDRV_GOP_DEVICE_COUNT 1 ++#define MDRV_GOP_NAME "mgop" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_GOP "mgop" ++#define MDRV_MAJOR_GOP 0xea ++#define MDRV_MINOR_GOP 0x0a ++ ++ ++int mstar_gop_drv_open(struct inode *inode, struct file *filp); ++int mstar_gop_drv_release(struct inode *inode, struct file *filp); ++long mstar_gop_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mstar_gop_drv_probe(struct platform_device *pdev); ++static int mstar_gop_drv_remove(struct platform_device *pdev); ++static int mstar_gop_drv_suspend(struct platform_device *dev, pm_message_t state); ++static int mstar_gop_drv_resume(struct platform_device *dev); ++static void mstar_gop_drv_platfrom_release(struct device *device); ++#if defined (CONFIG_ARCH_CEDRIC) ++extern int mstar_sca_drv_get_h_backporch(int sc_num); ++#endif ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++}GOP_DEV; ++ ++static GOP_DEV _devGOP = ++{ ++ .s32Major = MDRV_MAJOR_GOP, ++ .s32Minor = MDRV_MINOR_GOP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_GOP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mstar_gop_drv_open, ++ .release = mstar_gop_drv_release, ++ .unlocked_ioctl = mstar_gop_drv_ioctl, ++ } ++}; ++ ++static struct class * gop_class; ++static char * gop_classname = "mstar_gop_class"; ++ ++ ++static struct platform_driver Mstar_gop_driver = { ++ .probe = mstar_gop_drv_probe, ++ .remove = mstar_gop_drv_remove, ++ .suspend = mstar_gop_drv_suspend, ++ .resume = mstar_gop_drv_resume, ++ ++ .driver = { ++ .name = "mgop", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++static u64 sg_mstar_device_gop_dmamask = 0xffffffffUL; ++ ++static struct platform_device sg_mdrv_gop_device = ++{ ++ .name = "mgop", ++ .id = 0, ++ .dev = ++ { ++ .release = mstar_gop_drv_platfrom_release, ++ .dma_mask = &sg_mstar_device_gop_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_GOPIO_IOC_Set_BaseAddr(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_BASE_ADDR_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (GOP_SET_BASE_ADDR_CONFIG __user *)arg, sizeof(GOP_SET_BASE_ADDR_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetBase: GOP_%d, Base=%x, \n", stCfg.enGopNum, (int)stCfg.u32Base); ++ ++ GOP_Pan_Display(stCfg.enGopNum, stCfg.u32Base); ++ ++ ++ return 0; ++} ++ ++int _MDrv_GOPIO_IOC_SetMode(struct file *filp, unsigned long arg) ++{ ++ GOP_SETMODE_CONFIG stCfg; ++ int Pixel_Format, Bytes_Per_Pixel; ++ if(copy_from_user(&stCfg, (GOP_SETMODE_CONFIG __user *)arg, sizeof(GOP_SETMODE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_DBG(GOP_DBG_LV_0, "SetMode: GOP_%d, (%d, %d) FM=%d, Base=%x, interlace=%d, yuv=%d,\n", ++ stCfg.enGopNum, stCfg.u16width, stCfg.u16height, stCfg.enSrcFormat, (int)stCfg.u32BaseAddr, stCfg.bInterlace, stCfg.bYUVOutput); ++ ++ switch(stCfg.enSrcFormat) ++ { ++ case E_GOP_SRC_RGB565: ++ Pixel_Format = 0x0010; ++ Bytes_Per_Pixel = 2; ++ break; ++ ++ case E_GOP_SRC_ARGB8888: ++ Pixel_Format = 0x0050; ++ Bytes_Per_Pixel = 4; ++ break; ++ ++ case E_GOP_SRC_ABGR8888: ++ Pixel_Format = 0x0070; ++ Bytes_Per_Pixel = 4; ++ break; ++ ++ } ++ ++ ++ GOP_Setmode(FALSE, stCfg.enGopNum, stCfg.u16width, stCfg.u16height, stCfg.u32BaseAddr, Pixel_Format, Bytes_Per_Pixel, stCfg.bInterlace); ++ ++ GOP_Set_OutFormat(stCfg.enGopNum, stCfg.bYUVOutput); ++#if defined (CONFIG_ARCH_CEDRIC) ++ if(stCfg.enGopNum == E_GOP_1) ++ { ++ GOP_Set_PipeDelay(1, mstar_sca_drv_get_h_backporch(1) ); ++ } ++#endif ++ return 0; ++} ++ ++ ++int _MDrv_GOPIO_IOC_Set_Constant_Alpha(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_CONSTANT_ALPHA_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (GOP_SET_CONSTANT_ALPHA_CONFIG __user *)arg, sizeof(GOP_SET_CONSTANT_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Constant_Alpha(stCfg.enGopNum, stCfg.bEn, stCfg.u8Alpha); ++ ++ return 0; ++} ++ ++int _MDrv_GOPIO_IOC_Set_Color_Key(struct file *filp, unsigned long arg) ++{ ++ GOP_SET_COLOR_KEY_CONFIG stCfg; ++ if(copy_from_user(&stCfg, (GOP_SET_COLOR_KEY_CONFIG __user *)arg, sizeof(GOP_SET_COLOR_KEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Set_Color_Key(stCfg.enGopNum, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ return 0; ++} ++ ++//============================================================================== ++long mstar_gop_drv_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_devGOP.refCnt <= 0) ++ { ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOPIO_IOCTL refCnt =%d!!! \n", _devGOP.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(GOP_IOC_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= GOP_IOC_MAX_NR) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ switch(u32Cmd) ++ { ++ case GOP_IOC_SET_BASE_ADDR: ++ retval = _MDrv_GOPIO_IOC_Set_BaseAddr(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_MODE: ++ retval = _MDrv_GOPIO_IOC_SetMode(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_CONSTANT_ALPHA: ++ retval = _MDrv_GOPIO_IOC_Set_Constant_Alpha(filp, u32Arg); ++ break; ++ ++ case GOP_IOC_SET_COLOR_KEY: ++ retval = _MDrv_GOPIO_IOC_Set_Color_Key(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++static int mstar_gop_drv_probe(struct platform_device *pdev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_probe\n"); ++ ++ return 0; ++} ++ ++static int mstar_gop_drv_remove(struct platform_device *pdev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_remove\n"); ++ ++ return 0; ++} ++ ++ ++static int mstar_gop_drv_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_suspend\n"); ++ ++ ++ return 0; ++} ++ ++ ++static int mstar_gop_drv_resume(struct platform_device *dev) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_resume\n"); ++ ++ ++ return 0; ++} ++ ++static void mstar_gop_drv_platfrom_release(struct device *device) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] mstar_gop_drv_platfrom_release\n"); ++ ++} ++ ++ ++int mstar_gop_drv_open(struct inode *inode, struct file *filp) ++{ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOP DRIVER OPEN\n"); ++ ++ GOPIO_ASSERT(_devGOP.refCnt>=0); ++ _devGOP.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mstar_gop_drv_release(struct inode *inode, struct file *filp) ++{ ++ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] GOP DRIVER RELEASE\n"); ++ _devGOP.refCnt--; ++ GOPIO_ASSERT(_devGOP.refCnt>=0); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++int _MDrv_GOPIO_ModuleInit(void) ++{ ++ int s32Ret; ++ dev_t dev; ++ int ret = 0; ++ ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOPIO]_Init \n"); ++ ++ if(_devGOP.s32Major) ++ { ++ dev = MKDEV(_devGOP.s32Major, _devGOP.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_GOP_DEVICE_COUNT, MDRV_GOP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _devGOP.s32Minor, MDRV_GOP_DEVICE_COUNT, MDRV_GOP_NAME); ++ _devGOP.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] Unable to get major %d\n", _devGOP.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_devGOP.cdev, &_devGOP.fops); ++ if (0 != (s32Ret= cdev_add(&_devGOP.cdev, dev, MDRV_GOP_DEVICE_COUNT))) ++ { ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_GOP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ gop_class = class_create(THIS_MODULE, gop_classname); ++ if(IS_ERR(gop_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(gop_class, NULL, dev,NULL, "mgop"); ++ } ++ ++ /* initial the whole GOP Driver */ ++ ret = platform_driver_register(&Mstar_gop_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&sg_mdrv_gop_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&Mstar_gop_driver); ++ GOP_DBG(GOP_DBG_LV_0, "[GOP] register failed\n"); ++ ++ } ++ else ++ { ++ GOP_DBG(GOP_DBG_LV_IOCTL, "[GOP] register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _MDrv_GOPIO_ModuleExit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ GOP_DBG(GOP_DBG_LV_0, "[GOPIO]_Exit \n"); ++ ++ cdev_del(&_devGOP.cdev); ++ device_destroy(gop_class, MKDEV(_devGOP.s32Major, _devGOP.s32Minor)); ++ class_destroy(gop_class); ++ unregister_chrdev_region(MKDEV(_devGOP.s32Major, _devGOP.s32Minor), MDRV_GOP_DEVICE_COUNT); ++ platform_driver_unregister(&Mstar_gop_driver); ++} ++ ++ ++module_init(_MDrv_GOPIO_ModuleInit); ++module_exit(_MDrv_GOPIO_ModuleExit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GOPioctrl driver"); ++MODULE_LICENSE("GOP"); ++ +diff --git a/drivers/mstar/fb/infinity/gop/mdrv_gop_io.h b/drivers/mstar/fb/infinity/gop/mdrv_gop_io.h +new file mode 100644 +index 00000000..a010fcec +--- /dev/null ++++ b/drivers/mstar/fb/infinity/gop/mdrv_gop_io.h +@@ -0,0 +1,123 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_GOP_IO_H ++#define _MDRV_GOP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_GOP_LIB_CODE {'G','O','P','\0'} ++#define MSIF_GOP_BUILDNUM {'_','0','1','\0'} ++#define MSIF_GOP_LIBVER (2) ++#define MSIF_GOP_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++#define GOP_IOC_SET_BASE_ADDR_NR (0) ++#define GOP_IOC_SET_MODE_NR (1) ++#define GOP_IOC_SET_CONSTANT_ALPHA_NR (2) ++#define GOP_IOC_SET_COLOR_KEY_NR (3) ++#define GOP_IOC_MAX_NR (4) ++ ++ ++// use 'm' as magic number ++#define GOP_IOC_MAGIC ('3') ++#define GOP_IOC_SET_BASE_ADDR _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_BASE_ADDR_NR, GOP_SET_BASE_ADDR_CONFIG) ++#define GOP_IOC_SET_MODE _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_MODE_NR, GOP_SETMODE_CONFIG) ++#define GOP_IOC_SET_CONSTANT_ALPHA _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_CONSTANT_ALPHA_NR, GOP_SET_CONSTANT_ALPHA_CONFIG) ++#define GOP_IOC_SET_COLOR_KEY _IOWR(GOP_IOC_MAGIC, GOP_IOC_SET_COLOR_KEY_NR, GOP_SET_COLOR_KEY_CONFIG) ++//============================================================================= ++// enum ++//============================================================================= ++typedef enum ++{ ++ E_GOP_0, ++ E_GOP_1, ++ E_GOP_2, ++ E_GOP_3, ++ E_GOP_MAX, ++}E_GOP_NUM_TYPE; ++ ++ ++typedef enum ++{ ++ E_GOP_SRC_RGB565, ++ E_GOP_SRC_ARGB8888, ++ E_GOP_SRC_ABGR8888, ++}E_GOP_SRC_FORMAT_TYPE; ++//============================================================================= ++// struct ++//============================================================================= ++#ifndef _MS_TYPES_H_ ++typedef unsigned char MS_U8; ++typedef unsigned short MS_U16; ++typedef unsigned long MS_U32; ++typedef unsigned long long MS_U64; ++typedef unsigned char MS_BOOL; ++typedef signed short MS_S16; ++#endif ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_U32 u32Base; ++}GOP_SET_BASE_ADDR_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ E_GOP_SRC_FORMAT_TYPE enSrcFormat; ++ MS_U16 u16width; ++ MS_U16 u16height; ++ MS_BOOL bInterlace; ++ MS_U32 u32BaseAddr; ++ MS_BOOL bYUVOutput; ++}GOP_SETMODE_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_BOOL bEn; ++ MS_U8 u8Alpha; ++}GOP_SET_CONSTANT_ALPHA_CONFIG; ++ ++ ++typedef struct ++{ ++ E_GOP_NUM_TYPE enGopNum; ++ MS_BOOL bEn; ++ MS_U8 u8R; ++ MS_U8 u8G; ++ MS_U8 u8B; ++}GOP_SET_COLOR_KEY_CONFIG; ++#endif //_MDRV_GFLIP_IO_H ++ ++ ++ +diff --git a/drivers/mstar/fb/infinity/mdrv_fb.c b/drivers/mstar/fb/infinity/mdrv_fb.c +new file mode 100644 +index 00000000..346fa737 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/mdrv_fb.c +@@ -0,0 +1,1869 @@ ++ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_general_fb.c ++ * DESCRIPTION For mdrv LinuxBSP Display driver, use frame buffer ++ * architecture ++ * ++ * AUTHOR Chun Fan ++ * ++ * ++ * HISTORY 2008/05/06 initial version ++ * linux/drivers/video/mdrv_general_fb.c ++ * -- mdrv frame buffer device ++ *****************************************************************************/ ++ ++ ++#define mdrv_GEN_FB_C ++ ++ ++#include "mdrv_fb.h" ++#include "mdrv_fb_io.h" ++#include "mdrv_fb_st.h" ++ ++ ++/* ++ * RAM we reserve for the frame buffer. This defines the maximum screen ++ * size ++ * ++ * The default can be overridden if the driver is compiled as a module ++ */ ++/* must use u_long, or it will have following message ++ * drivers/video/mdrv_general_fb.c: In function '__check_sg_videomemorysize': ++ * drivers/video/mdrv_general_fb.c:54: warning: ++ * return from incompatible pointer type ++ */ ++ ++ ++ /* frame buffer size */ ++static u_long sg_videomemorysize=0; ++ ++/* physical address, used in probe(), ioctl(), remove(), CreateGWin() */ ++/* physical address of frame buffer 1 2 */ ++dma_addr_t sg_G3D_fb2_bus_addr1 = 0; ++ ++//extern ++extern void SwitchSubBank(int); ++ ++extern void GOP_Setmode(int,int,int,int,U32,U32,U16,int); ++extern void GOP_Change_Alpha(int,int,int,int,U32,U32,U16,int); ++extern void GOP_Pan_Display(int,U32); ++extern void GOP_Set_OutFormat(int,int); ++extern void GOP_Set_Constant_Alpha(int,int,int); ++extern void GOP_Set_Color_Key(int,int,int,int,int); ++extern void GOP_Set_PipeDelay(int,int); ++extern void GOP_Setmode_and_win(int,int,int,int,int,int,int,int,U32,U32,U16,int); ++ ++ ++//known function, close temperally ++//extern int mstar_sca_drv_get_pnl_refresh_rate(void); ++ ++//clock define, one for palette sram clock, one for scaler fclk1 ++struct clk **gop_clks;//index=1 is scl_fclk ++ ++//struct clk* gop_psram_clk; ++//struct clk* gop_scl_fclk1; ++int num_parents_clocks=0; ++ ++ ++ ++static struct platform_device *psg_mdrv_fbdev0; ++ ++FB_GOP_GWIN_CONFIG genGWinInfo={0}; ++unsigned char genGWIN=1; //record gwin is open or close ++FB_GOP_ALPHA_CONFIG genGOPALPHA={0}; ++FB_GOP_COLORKEY_CONFIG genGOPCOLORKEY={0}; ++FB_GOP_RESOLUTION_STRETCH_H_CONFIG genGOPGernelSettings={0}; ++ ++//// {B, G, R, Alpha} ++static FB_GOP_PaletteEntry DefaultPaletteEntry[GOP_PALETTE_ENTRY_NUM] = ++{ ++ {{ 0, 0, 0, 0}}, {{ 0, 0,128, 0}}, {{ 0,128, 0, 0}}, {{ 0,128,128, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0,128, 0}}, {{128,128, 0, 0}}, {{192,192,192, 0}}, ++ {{192,220,192, 0}}, {{240,202,166, 0}}, {{ 0, 32, 64, 0}}, {{ 0, 32, 96, 0}}, ++ {{ 0, 32,128, 0}}, {{ 0, 32,160, 0}}, {{ 0, 32,192, 0}}, {{ 0, 32,224, 0}}, ++ {{ 0, 64, 0, 0}}, {{ 0, 64, 32, 0}}, {{ 0, 64, 64, 0}}, {{ 0, 64, 96, 0}}, ++ {{ 0, 64,128, 0}}, {{ 0, 64,160, 0}}, {{ 0, 64,192, 0}}, {{ 0, 64,224, 0}}, ++ {{ 0, 96, 0, 0}}, {{ 0, 96, 32, 0}}, {{ 0, 96, 64, 0}}, {{ 0, 96, 96, 0}}, ++ {{ 0, 96,128, 0}}, {{ 0, 96,160, 0}}, {{ 0, 96,192, 0}}, {{ 0, 96,224, 0}}, ++ {{ 0,128, 0, 0}}, {{ 0,128, 32, 0}}, {{ 0,128, 64, 0}}, {{ 0,128, 96, 0}}, ++ {{ 0,128,128, 0}}, {{ 0,128,160, 0}}, {{ 0,128,192, 0}}, {{ 0,128,224, 0}}, ++ {{ 0,160, 0, 0}}, {{ 0,160, 32, 0}}, {{ 0,160, 64, 0}}, {{ 0,160, 96, 0}}, ++ {{ 0,160,128, 0}}, {{ 0,160,160, 0}}, {{ 0,160,192, 0}}, {{ 0,160,224, 0}}, ++ {{ 0,192, 0, 0}}, {{ 0,192, 32, 0}}, {{ 0,192, 64, 0}}, {{ 0,192, 96, 0}}, ++ {{ 0,192,128, 0}}, {{ 0,192,160, 0}}, {{ 0,192,192, 0}}, {{ 0,192,224, 0}}, ++ {{ 0,224, 0, 0}}, {{ 0,224, 32, 0}}, {{ 0,224, 64, 0}}, {{ 0,224, 96, 0}}, ++ {{ 0,224,128, 0}}, {{ 0,224,160, 0}}, {{ 0,224,192, 0}}, {{ 0,224,224, 0}}, ++ {{ 64, 0, 0, 0}}, {{ 64, 0, 32, 0}}, {{ 64, 0, 64, 0}}, {{ 64, 0, 96, 0}}, ++ {{ 64, 0,128, 0}}, {{ 64, 0,160, 0}}, {{ 64, 0,192, 0}}, {{ 64, 0,224, 0}}, ++ {{ 64, 32, 0, 0}}, {{ 64, 32, 32, 0}}, {{ 64, 32, 64, 0}}, {{ 64, 32, 96, 0}}, ++ {{ 64, 32,128, 0}}, {{ 64, 32,160, 0}}, {{ 64, 32,192, 0}}, {{ 64, 32,224, 0}}, ++ {{ 64, 64, 0, 0}}, {{ 64, 64, 32, 0}}, {{ 64, 64, 64, 0}}, {{ 64, 64, 96, 0}}, ++ {{ 64, 64,128, 0}}, {{ 64, 64,160, 0}}, {{ 64, 64,192, 0}}, {{ 64, 64,224, 0}}, ++ {{ 64, 96, 0, 0}}, {{ 64, 96, 32, 0}}, {{ 64, 96, 64, 0}}, {{ 64, 96, 96, 0}}, ++ {{ 64, 96,128, 0}}, {{ 64, 96,160, 0}}, {{ 64, 96,192, 0}}, {{ 64, 96,224, 0}}, ++ {{ 64,128, 0, 0}}, {{ 64,128, 32, 0}}, {{ 64,128, 64, 0}}, {{ 64,128, 96, 0}}, ++ {{ 64,128,128, 0}}, {{ 64,128,160, 0}}, {{ 64,128,192, 0}}, {{ 64,128,224, 0}}, ++ {{ 64,160, 0, 0}}, {{ 64,160, 32, 0}}, {{ 64,160, 64, 0}}, {{ 64,160, 96, 0}}, ++ {{ 64,160,128, 0}}, {{ 64,160,160, 0}}, {{ 64,160,192, 0}}, {{ 64,160,224, 0}}, ++ {{ 64,192, 0, 0}}, {{ 64,192, 32, 0}}, {{ 64,192, 64, 0}}, {{ 64,192, 96, 0}}, ++ {{ 64,192,128, 0}}, {{ 64,192,160, 0}}, {{ 64,192,192, 0}}, {{ 64,192,224, 0}}, ++ {{ 64,224, 0, 0}}, {{ 64,224, 32, 0}}, {{ 64,224, 64, 0}}, {{ 64,224, 96, 0}}, ++ {{ 64,224,128, 0}}, {{ 64,224,160, 0}}, {{ 64,224,192, 0}}, {{ 64,224,224, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0, 32, 0}}, {{128, 0, 64, 0}}, {{128, 0, 96, 0}}, ++ {{128, 0,128, 0}}, {{128, 0,160, 0}}, {{128, 0,192, 0}}, {{128, 0,224, 0}}, ++ {{128, 32, 0, 0}}, {{128, 32, 32, 0}}, {{128, 32, 64, 0}}, {{128, 32, 96, 0}}, ++ {{128, 32,128, 0}}, {{128, 32,160, 0}}, {{128, 32,192, 0}}, {{128, 32,224, 0}}, ++ {{128, 64, 0, 0}}, {{128, 64, 32, 0}}, {{128, 64, 64, 0}}, {{128, 64, 96, 0}}, ++ {{128, 64,128, 0}}, {{128, 64,160, 0}}, {{128, 64,192, 0}}, {{128, 64,224, 0}}, ++ {{128, 96, 0, 0}}, {{128, 96, 32, 0}}, {{128, 96, 64, 0}}, {{128, 96, 96, 0}}, ++ {{128, 96,128, 0}}, {{128, 96,160, 0}}, {{128, 96,192, 0}}, {{128, 96,224, 0}}, ++ {{128,128, 0, 0}}, {{128,128, 32, 0}}, {{128,128, 64, 0}}, {{128,128, 96, 0}}, ++ {{128,128,128, 0}}, {{128,128,160, 0}}, {{128,128,192, 0}}, {{128,128,224, 0}}, ++ {{128,160, 0, 0}}, {{128,160, 32, 0}}, {{128,160, 64, 0}}, {{128,160, 96, 0}}, ++ {{128,160,128, 0}}, {{128,160,160, 0}}, {{128,160,192, 0}}, {{128,160,224, 0}}, ++ {{128,192, 0, 0}}, {{128,192, 32, 0}}, {{128,192, 64, 0}}, {{128,192, 96, 0}}, ++ {{128,192,128, 0}}, {{128,192,160, 0}}, {{128,192,192, 0}}, {{128,192,224, 0}}, ++ {{128,224, 0, 0}}, {{128,224, 32, 0}}, {{128,224, 64, 0}}, {{128,224, 96, 0}}, ++ {{128,224,128, 0}}, {{128,224,160, 0}}, {{128,224,192, 0}}, {{128,224,224, 0}}, ++ {{192, 0, 0, 0}}, {{192, 0, 32, 0}}, {{192, 0, 64, 0}}, {{192, 0, 96, 0}}, ++ {{192, 0,128, 0}}, {{192, 0,160, 0}}, {{192, 0,192, 0}}, {{192, 0,224, 0}}, ++ {{192, 32, 0, 0}}, {{192, 32, 32, 0}}, {{192, 32, 64, 0}}, {{192, 32, 96, 0}}, ++ {{192, 32,128, 0}}, {{192, 32,160, 0}}, {{192, 32,192, 0}}, {{192, 32,224, 0}}, ++ {{192, 64, 0, 0}}, {{192, 64, 32, 0}}, {{192, 64, 64, 0}}, {{192, 64, 96, 0}}, ++ {{192, 64,128, 0}}, {{192, 64,160, 0}}, {{192, 64,192, 0}}, {{192, 64,224, 0}}, ++ {{192, 96, 0, 0}}, {{192, 96, 32, 0}}, {{192, 96, 64, 0}}, {{192, 96, 96, 0}}, ++ {{192, 96,128, 0}}, {{192, 96,160, 0}}, {{192, 96,192, 0}}, {{192, 96,224, 0}}, ++ {{192,128, 0, 0}}, {{192,128, 32, 0}}, {{192,128, 64, 0}}, {{192,128, 96, 0}}, ++ {{192,128,128, 0}}, {{192,128,160, 0}}, {{192,128,192, 0}}, {{192,128,224, 0}}, ++ {{192,160, 0, 0}}, {{192,160, 32, 0}}, {{192,160, 64, 0}}, {{192,160, 96, 0}}, ++ {{192,160,128, 0}}, {{192,160,160, 0}}, {{192,160,192, 0}}, {{192,160,224, 0}}, ++ {{192,192, 0, 0}}, {{192,192, 32, 0}}, {{192,192, 64, 0}}, {{192,192, 96, 0}}, ++ {{192,192,128, 0}}, {{192,192,160, 0}}, {{240,251,255, 0}}, {{164,160,160, 0}}, ++ {{128,128,128, 0}}, {{ 0, 0,255, 0}}, {{ 0,255, 0, 0}}, {{ 0,255,255, 0}}, ++ {{255, 0, 0, 0}}, {{255, 0,255, 0}}, {{255,255, 0, 0}}, {{255,255,255, 0}} ++ }; ++ ++FB_GOP_PaletteEntry stGOPCurrentPalInfo[GOP_PALETTE_ENTRY_NUM]={}; ++ ++ ++static const char* KEY_DMEM_FB_BUF="FB_BUFFER"; ++ ++ ++//module_param(sg_videomemorysize, ulong, 0); ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++// update global variables while init ++static void __init mdrvinfinityfb_updateinfo(void) ++{ ++ ++ static int main_videomemory_size=0; ++ ++ sg_mdrvinfinityfb_default_var.xres = 0; ++ sg_mdrvinfinityfb_default_var.yres = 0; ++ genGOPGernelSettings.u32Width=sg_mdrvinfinityfb_default_var.xres; ++ genGOPGernelSettings.u32Height=sg_mdrvinfinityfb_default_var.yres; ++ genGOPGernelSettings.enBufferNum=FB_DOUBLE_BUFFER; ++ genGOPGernelSettings.enStretchH_Ratio=FB_STRETCH_H_RATIO_1; ++ genGOPGernelSettings.u32DisplayWidth=genGOPGernelSettings.u32Width*genGOPGernelSettings.enStretchH_Ratio; ++ genGOPGernelSettings.u32DisplayHeight=genGOPGernelSettings.u32Height; ++ //GWin init, same size as screen ++ genGWinInfo.u18HStart = 0; ++ genGWinInfo.u18HEnd = genGWinInfo.u18HStart+sg_mdrvinfinityfb_default_var.xres; ++ genGWinInfo.u18VStart = 0; ++ genGWinInfo.u18VEnd = genGWinInfo.u18VStart+sg_mdrvinfinityfb_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb_default_var.xres*sg_mdrvinfinityfb_default_var.yres * ANDROID_BYTES_PER_PIXEL * (genGOPGernelSettings.enBufferNum)); ++ ++ //known function, close temperally ++ //sg_mdrvinfinityfb_default_fbmode.refresh=mstar_sca_drv_get_pnl_refresh_rate(); ++ ++ sg_videomemorysize = main_videomemory_size; ++ ++ FBDBGMORE("[FB Driver] updateinfo: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], sg_videomemorysize = 0x%x \r\n",sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,(unsigned int)sg_videomemorysize); ++ ++} ++ ++// update global variables while setting new resolution by ioctl FBIOPUT_VSCREENINFO ++static int mdrvinfinityfb_infinity_updateinfo_par(unsigned int setWidth,unsigned int setHeight) ++{ ++ ++ static int main_videomemory_size=0; ++ ++ sg_mdrvinfinityfb_default_var.xres = setWidth; ++ sg_mdrvinfinityfb_default_var.yres = setHeight; ++ genGOPGernelSettings.u32Width=sg_mdrvinfinityfb_default_var.xres; ++ genGOPGernelSettings.u32Height=sg_mdrvinfinityfb_default_var.yres; ++ genGOPGernelSettings.u32DisplayWidth=genGOPGernelSettings.u32Width*genGOPGernelSettings.enStretchH_Ratio; ++ genGOPGernelSettings.u32DisplayHeight=genGOPGernelSettings.u32Height; ++ //GWin init, same size as screen ++ genGWinInfo.u18HStart = 0; ++ genGWinInfo.u18HEnd = genGWinInfo.u18HStart+sg_mdrvinfinityfb_default_var.xres; ++ genGWinInfo.u18VStart = 0; ++ genGWinInfo.u18VEnd = genGWinInfo.u18VStart+sg_mdrvinfinityfb_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb_default_var.xres*sg_mdrvinfinityfb_default_var.yres * ANDROID_BYTES_PER_PIXEL * (genGOPGernelSettings.enBufferNum)); ++ ++ // free memory if it has ++ if(sg_videomemorysize > 0) ++ { ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ } ++ ++ sg_videomemorysize = main_videomemory_size; ++ ++ FBDBG ("[FB Driver] updateinfo_par: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], sg_videomemorysize = 0x%x \r\n",sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,(unsigned int)sg_videomemorysize); ++ ++ // allocate new memory ++ if (!(sg_pG3D_fb2_vir_addr1 = alloc_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ &sg_G3D_fb2_bus_addr1))) ++ { ++ FBDBG("[FB Driver] Error: updateinfo_par: unable to allocate screen memory\n"); ++ return -ENOMEM; ++ } ++ ++ // prevent initial garbage on screen ; to clean memory ++ memset(CAST_2_IOMEM_CHAR_P sg_pG3D_fb2_vir_addr1,OTHER_COLOR, sg_videomemorysize); ++ ++ sg_mdrvinfinityfb_fix.smem_start = sg_G3D_fb2_bus_addr1; ++ sg_mdrvinfinityfb_fix.smem_len = sg_videomemorysize; ++ ++ FBDBG("[FB Driver] vir=0x%x, phy=0x%x\n", (unsigned int)sg_pG3D_fb2_vir_addr1, sg_G3D_fb2_bus_addr1); ++ ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb_infinity_SetPalette(FB_GOP_PaletteEntry *pPalEntry, int intPalStart,int intPalEnd) ++{ ++ unsigned long GOP_Reg_Base; ++ int i=0; ++ int ret=-1; ++ //unsigned long tempval; ++ ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ //open scl0 fclk to load palette ++ if (IS_ERR(gop_clks[1])) ++ { ++ FBDBG( "[FB Driver] Error: SetPalette Fail to get gop fclk of scl!\n" ); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_clks[1]); ++ } ++ ++ //set force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0x0200 , GOP_BANK_FORCE_WR); ++ ++ /*tempval=INREGMSK16(GOP_Reg_Base+REG_GOP_3B, 0x0003); ++ if(tempval & 0x03) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_3B, 0 , 0x0003); ++ }*/ ++ ++ //set RIU mode ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0000 , 0x1000); ++ ++ FBDBGMORE("Palette value:(B,G,R,A)\n"); ++ ++ //write palette ++ for(i=intPalStart;i<=intPalEnd;i++) ++ { ++ //set palette value ++ OUTREG16(GOP_Reg_Base+REG_GOP_03, pPalEntry[i].BGRA.u8G<<8|pPalEntry[i].BGRA.u8B); ++ OUTREG16(GOP_Reg_Base+REG_GOP_04, pPalEntry[i].BGRA.u8A<<8|pPalEntry[i].BGRA.u8R); ++ //set palette index ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, i , 0x00FF); ++ //write trigger ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0100 , 0x0100); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0000 , 0x0100); ++ ++ //record in global variable ++ stGOPCurrentPalInfo[i].BGRA.u8B=pPalEntry[i].BGRA.u8B; ++ stGOPCurrentPalInfo[i].BGRA.u8G=pPalEntry[i].BGRA.u8G; ++ stGOPCurrentPalInfo[i].BGRA.u8R=pPalEntry[i].BGRA.u8R; ++ stGOPCurrentPalInfo[i].BGRA.u8A=pPalEntry[i].BGRA.u8A; ++ FBDBGMORE("(%d,%d,%d,%d)\n",stGOPCurrentPalInfo[i].BGRA.u8B,stGOPCurrentPalInfo[i].BGRA.u8G,stGOPCurrentPalInfo[i].BGRA.u8R,stGOPCurrentPalInfo[i].BGRA.u8A); ++ } ++ ++ //close force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0x0000 , GOP_BANK_FORCE_WR); ++ ++ //close clk ++ clk_disable_unprepare(gop_clks[1]); ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb_set_par(struct fb_info *info) ++{ ++ int ret = 0; ++ //unsigned long GOP_Reg_Base; ++ //MstarFB_ENTER(); ++ ++ //if use back to this to set resolution, it will set to default ++ genGOPGernelSettings.enStretchH_Ratio=FB_STRETCH_H_RATIO_1; ++ genGOPGernelSettings.enBufferNum=FB_DOUBLE_BUFFER; ++ ++ ret=mdrvinfinityfb_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start=sg_mdrvinfinityfb_fix.smem_start; ++ info->fix.smem_len=sg_mdrvinfinityfb_fix.smem_len; ++ ++ info->var.width=info->var.xres; ++ info->var.height=info->var.yres; ++ ++ info->screen_base = CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ GOP_Setmode(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ //MstarFB_LEAVE(); ++ return ret; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_mmap +++------------------------------------------------------------------------------ ++| DESCRIPTION : memory map function, Let user application can get virtual ++| address to access in user space. need pass in physical address ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| vma | x | x | we use Remap-pfn-range will mark the range VM_IO ++| | | | and VM_RESERVED, and save these information in ++| | | | vma +++------------------------------------------------------------------------------ ++*/ ++ ++static int mdrvinfinityfb_mmap(struct fb_info *pinfo, struct vm_area_struct *vma) ++{ ++ size_t size; ++ size = 0; ++ ++ //MstarFB_ENTER(); ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBG("[FB Driver] ERROR: mmap, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if (NULL == pinfo) ++ { ++ FBDBG("[FB Driver] ERROR: mmap, pinfo is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ if (NULL == vma) ++ { ++ FBDBG("[FB Driver] ERROR: mmap, vma is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_pgoff += ((sg_G3D_fb2_bus_addr1 ) >> PAGE_SHIFT); ++ ++ FBDBG( ++ "[FB Driver] mmap vma->vm_start=%x\n vma->vm_end=%x\n vma->vm_pgoff =%x\n", ++ (unsigned int) vma->vm_start, (unsigned int)vma->vm_end , ++ (unsigned int)vma->vm_pgoff); ++ ++ //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ ++ //MstarFB_LEAVE(); ++ return 0; ++} ++ ++ ++ ++// FB Ioctl Functions ++ ++int _MDrv_FBIO_IOC_Get_SUPINFO(unsigned long arg) ++{ ++ FB_GOP_SUPINF_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ // enable gwin is in GOP01 ++ ++ stCfg.bKeyAlpha = 1; ++ stCfg.bConstAlpha = 1; ++ stCfg.bPixelAlpha = 1; ++ stCfg.bColFmt[COLORFMT_ARGB8888] = 0; ++ stCfg.bColFmt[COLORFMT_RGB565] = 0; ++ stCfg.bColFmt[COLORFMT_YUV422] = 0; ++ stCfg.bColFmt[COLORFMT_I8PALETTE]= 1; ++ stCfg.u32MaxWidth = 1920; ++ stCfg.u32MaxWidth = 1080; ++ ++ if(copy_to_user((FB_GOP_SUPINF_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_SUPINF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_GWIN(unsigned long arg) ++{ ++ FB_GOP_GWIN_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ stCfg.u18HStart = genGWinInfo.u18HStart; ++ stCfg.u18HEnd = genGWinInfo.u18HEnd; ++ stCfg.u18VStart = genGWinInfo.u18VStart; ++ stCfg.u18VEnd = genGWinInfo.u18VEnd; ++ ++ ++ if(copy_to_user((FB_GOP_GWIN_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_GWIN(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_GWIN_CONFIG stCfg; ++ unsigned short MIU_BUS = 0x04; ++ unsigned short u16FrameBuffer_Bytes_Per_Pixel = ANDROID_BYTES_PER_PIXEL; ++ unsigned long u32TempVal = 0; ++ unsigned long GOP_Reg_DB=0x0400; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBG("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_GWIN, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ // gwin info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ if(copy_from_user(&stCfg, (FB_GOP_GWIN_CONFIG __user *)arg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ genGWinInfo.u18HStart = stCfg.u18HStart; ++ genGWinInfo.u18HEnd = stCfg.u18HEnd; ++ genGWinInfo.u18VStart = stCfg.u18VStart; ++ genGWinInfo.u18VEnd = stCfg.u18VEnd; ++ ++ // GOP Display Setting, GWIN ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(genGWinInfo.u18HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(genGWinInfo.u18HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,genGWinInfo.u18VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,genGWinInfo.u18VEnd); // V end line ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_EnGOP(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ unsigned char enGOP; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ // get enable/disable gwin ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x0001) && INREGMSK16(GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0001)) ++ enGOP=1; ++ else ++ enGOP=0; ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ if(copy_to_user((unsigned char __user *)arg, &enGOP, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnGOP(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ unsigned char enGOP; ++ unsigned long GOP_Reg_DB=0x0400; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBG("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_EnGOP, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ if(copy_from_user(&enGOP, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] enable GOP=%d \n",enGOP); ++ ++ genGWIN=enGOP; ++ ++ // enable/disable gop switch at scaler ++ if(enGOP) ++ OUTREGMSK16(GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0001,0x0001); ++ else ++ OUTREGMSK16(GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0000,0x0001); ++ ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ // enable/disable gwin ++ if(enGOP) ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0001,0x0001); ++ else ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0000,0x0001); ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_Alpha(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_ALPHA_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ // alpha info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ // switch to subbank01 ++ SwitchSubBank(1); ++ ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // enable/disable ++ stCfg.bEn=TRUE; ++ ++ // constant or pixel alpha ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, 0x4000)>>14) ++ stCfg.enAlphaType = PIXEL_ALPHA; ++ else ++ stCfg.enAlphaType = CONST_ALPHA; ++ ++ // alhap value ++ stCfg.u8Alpha = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_0A, 0x00FF); ++ ++ // switch back to subbank00 ++ SwitchSubBank(0); ++ ++ genGOPALPHA.bEn=stCfg.bEn; ++ genGOPALPHA.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA.u8Alpha=stCfg.u8Alpha; ++ ++ if(copy_to_user((FB_GOP_ALPHA_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Constant_Alpha(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBG("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_Constant_Alpha, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Set alpha type=%d, constant alpha value=0x%x \n", (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ ++ GOP_Set_Constant_Alpha(0, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ ++ genGOPALPHA.bEn=stCfg.bEn; ++ genGOPALPHA.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA.u8Alpha=stCfg.u8Alpha; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_Color_Key(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base; ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ // colorkey setting is in GOP00 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // enable/disable ++ stCfg.bEn = (INREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0800)>>11); ++ ++ // colorkey value ++ stCfg.u8R = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_25,0x00FF); ++ stCfg.u8G = (unsigned char)(INREGMSK16(GOP_Reg_Base+REG_GOP_24,0xFF00)>>8); ++ stCfg.u8B = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_24,0x00FF); ++ ++ genGOPCOLORKEY.bEn=stCfg.bEn; ++ genGOPCOLORKEY.u8R=stCfg.u8R; ++ genGOPCOLORKEY.u8G=stCfg.u8G; ++ genGOPCOLORKEY.u8B=stCfg.u8B; ++ ++ if(copy_to_user((FB_GOP_COLORKEY_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Color_Key(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBG("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_Color_Key, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Set ColorKey enable=%d, R=0x%x, G=0x%x, B=0x%x\n", (int)stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ GOP_Set_Color_Key(0, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ genGOPCOLORKEY.bEn=stCfg.bEn; ++ genGOPCOLORKEY.u8R=stCfg.u8R; ++ genGOPCOLORKEY.u8G=stCfg.u8G; ++ genGOPCOLORKEY.u8B=stCfg.u8B; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_imageblit(struct fb_info *info,unsigned long arg) ++{ ++ struct fb_image stCfg; ++ //struct fb_image image; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBG("[FB Driver] ERROR: _MDrv_FBIO_IOC_imageblit, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&stCfg, (struct fb_image __user *)arg, sizeof(const struct fb_image))) ++ { ++ return -EFAULT; ++ } ++ ++ if (NULL == stCfg.data) ++ { ++ FBDBG("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, fb_image.data is NULL pointer\r\n"); ++ return -EFAULT; ++ } ++ ++ FBDBGMORE( "[FB Driver] Imgblit test, dst (x,y)=(%d,%d), width=%d, height=%d, colordepth=%d \n" ,stCfg.dx,stCfg.dy,stCfg.width,stCfg.height,stCfg.depth); ++ ++ sys_imageblit(info,&stCfg); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_Palette(unsigned long arg) ++{ ++ FB_GOP_PaletteEntry stCfg[256]; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ //int i=0; ++ //struct fb_image image; ++ ++ /*if (sg_videomemorysize<1) ++ { ++ FBDBG("ERROR: _MDrv_FBIO_IOC_imageblit, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ }*/ ++ ++ if(copy_from_user(&stCfg, (FB_GOP_PaletteEntry __user *)arg, sizeof(FB_GOP_PaletteEntry)*256)) ++ { ++ return -EFAULT; ++ } ++ ++ //test palette ++ /*for(i=0;i<=255;i++) ++ { ++ FBDBG("(%d,%d,%d,%d)\n",stCfg[i].BGRA.u8B,stCfg[i].BGRA.u8G,stCfg[i].BGRA.u8R,stCfg[i].BGRA.u8A); ++ }*/ ++ ++ mdrvinfinityfb_infinity_SetPalette(stCfg,0,255); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_General_Config(unsigned long arg) ++{ ++ FB_GOP_RESOLUTION_STRETCH_H_CONFIG stCfg; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if(copy_from_user(&stCfg, (FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ stCfg.u32Height = genGOPGernelSettings.u32Height; ++ stCfg.u32Width = genGOPGernelSettings.u32Width; ++ stCfg.enBufferNum = genGOPGernelSettings.enBufferNum; ++ stCfg.u32DisplayHeight = genGOPGernelSettings.u32DisplayHeight; ++ stCfg.u32DisplayWidth = genGOPGernelSettings.u32DisplayWidth; ++ stCfg.enStretchH_Ratio = genGOPGernelSettings.enStretchH_Ratio; ++ ++ if(copy_to_user((FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_General_Config(struct fb_info *info,unsigned long arg) ++{ ++ FB_GOP_RESOLUTION_STRETCH_H_CONFIG stCfg; ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ int ret = 0; ++ ++ FBDBG("[FB Driver] %s, sg_videomemorysize=0x%x\n",__func__,(unsigned int)sg_videomemorysize); ++ ++ if(copy_from_user(&stCfg, (FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Set General_Config GOP_Width=%d, GOP_Height=%d, Display_Width=%d, Display_Height=%d, Buffer Num=%d, Stretch Ratio=%d\n",(int)stCfg.u32Width,(int)stCfg.u32Height,(int)stCfg.u32DisplayWidth,(int)stCfg.u32DisplayHeight,(int)stCfg.enBufferNum,(int)stCfg.enStretchH_Ratio); ++ ++ ///check variable valid/invalid ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //single/double buffer check ++ if((stCfg.enBufferNum!=FB_SINGLE_BUFFER)&&(stCfg.enBufferNum!=FB_DOUBLE_BUFFER)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: buffer num should be 1 or 2 !\n "); ++ return -EINVAL; ++ } ++ //stretch ratio check ++ if((stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_1)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_2)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_4)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_8)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: stretch H ratio should be 1, 2, 4 or 8 !\n "); ++ return -EINVAL; ++ } ++ //x & y should > 0 ++ if((stCfg.u32Height<1)||(stCfg.u32Width<1)||(stCfg.u32DisplayHeight<1)||(stCfg.u32DisplayWidth<1)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ //max size for display is 1920*1088 ++ if(((stCfg.u32Height * stCfg.u32Width)>(1920*1088))||((stCfg.u32DisplayHeight* stCfg.u32DisplayWidth)>(1920*1088))) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ //miu alignment ++ if(((stCfg.u32Width % DisplayPerPixel)!=0)||((stCfg.u32DisplayWidth% DisplayPerPixel)!=0)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ //Stretch H parameter check ++ if((stCfg.u32Width*stCfg.enStretchH_Ratio)!=stCfg.u32DisplayWidth) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: DisplayWidth should = Width * StretchH_Ratio!\n "); ++ return -EINVAL; ++ } ++ //Stretch V parameter check ++ if(stCfg.u32Height != stCfg.u32DisplayHeight) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: DisplayHeight should = Height!\n"); ++ return -EINVAL; ++ } ++ ++ //after checking valid parameter ++ genGOPGernelSettings.u32Width = stCfg.u32Width; ++ genGOPGernelSettings.u32Height = stCfg.u32Height; ++ genGOPGernelSettings.u32DisplayWidth = stCfg.u32DisplayWidth; ++ genGOPGernelSettings.u32DisplayHeight = stCfg.u32DisplayHeight; ++ genGOPGernelSettings.enBufferNum = stCfg.enBufferNum; ++ genGOPGernelSettings.enStretchH_Ratio = stCfg.enStretchH_Ratio; ++ ++ info->var.xres=stCfg.u32Width; ++ info->var.yres=stCfg.u32Height; ++ ++ ret=mdrvinfinityfb_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start=sg_mdrvinfinityfb_fix.smem_start; ++ info->fix.smem_len=sg_mdrvinfinityfb_fix.smem_len; ++ ++ info->var.width=info->var.xres; ++ info->var.height=info->var.yres; ++ ++ info->screen_base = CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ GOP_Setmode_Stretch_H(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0,(int)genGOPGernelSettings.enStretchH_Ratio); ++ ++ return 0; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_ioctl +++------------------------------------------------------------------------------ ++| DESCRIPTION : IO control code. we provide some customize ioctl code, GLES, ++| and test code. now, we provide the following IOCTL command ++| G3D_GETVFRAMEVIRTUAL1 ++| G3D_GETVFRAMEVIRTUAL2 ++| G3D_GETCOMMANDQVIRTUAL ++| G3D_GETREGISTERVIRTUAL ++| G3D_GETTEXTUREVIRTUAL ++| G3D_FREETEXTUREVIRTUAL ++| SET_DISPLAY_COLOR ++| G3D_IOC_MAXNR 20 ++| ++| + define color ++| COLOR_MASK ++| WHITE_COLOR ++| ++| RETURN : When the operation is success, it return 0. ++| some ioctl will return the physical address for GLES use ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| cmd | x | | pass in the ioctl command ++|--------------------+---+---+------------------------------------------------- ++| arg | x | x | pass in/out argument, from user space or to user ++| | | | space +++------------------------------------------------------------------------------ ++*/ ++/* I reserve the unsgined long here, ++ because it is the ioctl() function template */ ++static int ++mdrvinfinityfb_ioctl(struct fb_info *pinfo, unsigned int cmd, unsigned long arg) ++{ ++ int err=0, ret=0; ++ unsigned int ret_Phy=0; ++ ++ if (NULL == pinfo) ++ { ++ FBDBG("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, pinfo is NULL pointer\r\n"); ++ return -ENOTTY; ++ } ++ ++ /* don't even decode wrong cmds: better returning ENOTTY than EFAULT */ ++ if (_IOC_TYPE(cmd) != G3D_IOC_MAGIC_INFINITY) ++ return -ENOTTY; ++// if (_IOC_NR(cmd) > G3D_IOC_MAXNR) ++// return -ENOTTY; ++ ++ /* ++ * the type is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. Note that the type is user-oriented, while ++ * verify_area is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ err = !access_ok(VERIFY_WRITE, CAST_2_USER_VOID_P arg, _IOC_SIZE(cmd)); ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ err = !access_ok(VERIFY_READ, CAST_2_USER_VOID_P arg, _IOC_SIZE(cmd)); ++ ++ /* check if occurred error */ ++ if (err) ++ return -EFAULT; ++ ++ switch (cmd) ++ { ++ case IOCTL_FB_GETFBPHYADDRESS: ++ ret_Phy = sg_G3D_fb2_bus_addr1; ++ FBDBG( "[FB Driver] Phy Addr =%x\r\n",ret_Phy); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ ++ case IOCTL_FB_GETVIDEOMEMSIZE: ++ ret_Phy = sg_videomemorysize; ++ FBDBG( "[FB Driver] Kernel VideoMemSize =0x%x \n" ,(unsigned int)sg_videomemorysize); ++ ret = __put_user(ret_Phy, CAST_2_USER_UINT_P arg); ++ break; ++ ++ case IOCTL_FB_GETFBSUPPORTINF: ++ FBDBG( "[FB Driver] Get Framebuffer Support Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_SUPINFO(arg); ++ break; ++ ++ case IOCTL_FB_GETGWININFO: ++ FBDBG( "[FB Driver] Get Framebuffer GWIN Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_GWIN(arg); ++ break; ++ ++ case IOCTL_FB_SETGWININFO: ++ FBDBG( "[FB Driver] Set Framebuffer GWIN Information.\n"); ++ ret=_MDrv_FBIO_IOC_Set_GWIN(arg); ++ break; ++ ++ case IOCTL_FB_GETENABLEGOP: ++ FBDBG( "[FB Driver] Get GOP Enable/Disable.\n"); ++ ret=_MDrv_FBIO_IOC_Get_EnGOP(arg); ++ break; ++ ++ case IOCTL_FB_SETENABLEGOP: ++ FBDBG( "[FB Driver] Set GOP Enable/Disable.\n"); ++ ret=_MDrv_FBIO_IOC_Set_EnGOP(arg); ++ break; ++ ++ case IOCTL_FB_GETALPHA: ++ FBDBG( "[FB Driver] Get Alpha Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_Alpha(arg); ++ break; ++ ++ case IOCTL_FB_SETALPHA: ++ FBDBG( "[FB Driver] Set Alpha Information.\n"); ++ ret=_MDrv_FBIO_IOC_Set_Constant_Alpha(arg); ++ break; ++ ++ case IOCTL_FB_GETCOLORKEY: ++ FBDBG( "[FB Driver] Get Colorkey Information.\n"); ++ ret=_MDrv_FBIO_IOC_Get_Color_Key(arg); ++ break; ++ ++ case IOCTL_FB_SETCOLORKEY: ++ FBDBG( "[FB Driver] Set Colorkey Information.\n"); ++ ret=_MDrv_FBIO_IOC_Set_Color_Key(arg); ++ break; ++ ++ case IOCTL_FB_IMAGEBLIT: ++ FBDBG( "[FB Driver] Use Imageblit.\n"); ++ ret=_MDrv_FBIO_IOC_imageblit(pinfo,arg); ++ break; ++ case IOCTL_FB_SETPALETTE: ++ FBDBG( "[FB Driver] Set Palette.\n"); ++ ret=_MDrv_FBIO_IOC_Set_Palette(arg); ++ break; ++ case IOCTL_FB_GETGENERALCONFIG: ++ FBDBG( "[FB Driver] Set Palette.\n"); ++ ret=_MDrv_FBIO_IOC_Get_General_Config(arg); ++ break; ++ case IOCTL_FB_SETGENERALCONFIG: ++ FBDBG( "[FB Driver] Set Palette.\n"); ++ ret=_MDrv_FBIO_IOC_Set_General_Config(pinfo,arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ FBDBG("[FB Driver] in default ioct\r\n"); ++ return -ENOTTY; ++ } ++ return ret; ++} ++ ++static ssize_t gopinfo_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ return 0; ++} ++ ++ ++static ssize_t gopinfo_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "[FB/GOP Driver Information]\n"); ++ str += scnprintf(str, end - str, "[Framebuffer]\n"); ++ str += scnprintf(str, end - str, " Width : %4d pixel\n",sg_mdrvinfinityfb_default_var.xres); ++ str += scnprintf(str, end - str, " Height : %4d pixel\n",sg_mdrvinfinityfb_default_var.yres); ++ str += scnprintf(str, end - str, " BPP : %4d bytes per pixel\n",ANDROID_BYTES_PER_PIXEL); ++ str += scnprintf(str, end - str, " Memory Size : %d bytes\n",(unsigned int)sg_videomemorysize); ++ str += scnprintf(str, end - str, " Memory Phy_Addr: 0x%x\n",sg_G3D_fb2_bus_addr1); ++ str += scnprintf(str, end - str, " Memory Vir_Addr: 0x%x\n",(unsigned int)sg_pG3D_fb2_vir_addr1); ++ str += scnprintf(str, end - str, "[GOP(GWIN)]\n"); ++ if(genGWIN==0) ++ str += scnprintf(str, end - str, " GWIN Status : Close\n"); ++ else if(genGWIN==1) ++ str += scnprintf(str, end - str, " GWIN Status : Open\n"); ++ else ++ str += scnprintf(str, end - str, " GWIN Status : Unknown\n"); ++ ++ str += scnprintf(str, end - str, " H Start : %4d\n",genGWinInfo.u18HStart); ++ str += scnprintf(str, end - str, " H End : %4d\n",genGWinInfo.u18HEnd); ++ str += scnprintf(str, end - str, " V Start : %4d\n",genGWinInfo.u18VStart); ++ str += scnprintf(str, end - str, " V End : %4d\n",genGWinInfo.u18VEnd); ++ ++ if(genGOPALPHA.bEn==0) ++ str += scnprintf(str, end - str, " Alpha Status : Close\n"); ++ else if(genGOPALPHA.bEn==1) ++ str += scnprintf(str, end - str, " Alpha Status : Open\n"); ++ else ++ str += scnprintf(str, end - str, " Alpha Status : Unknown\n"); ++ ++ ++ if(genGOPALPHA.enAlphaType==PIXEL_ALPHA) ++ str += scnprintf(str, end - str, " Alpha Type : Pixel Alpha\n"); ++ else if(genGOPALPHA.enAlphaType==CONST_ALPHA) ++ { ++ str += scnprintf(str, end - str, " Alpha Type : Constant Alpha\n"); ++ str += scnprintf(str, end - str, " Alpha Value : 0x%2x\n",genGOPALPHA.u8Alpha); ++ } ++ else ++ str += scnprintf(str, end - str, " Alpha Type : wrong alpha type\n"); ++ ++ if(genGOPCOLORKEY.bEn==0) ++ str += scnprintf(str, end - str, " Colorkey Status: Close\n"); ++ else if(genGOPCOLORKEY.bEn==1) ++ { ++ str += scnprintf(str, end - str, " Colorkey Status: Open\n"); ++ str += scnprintf(str, end - str, " Red : 0x%2x\n",genGOPCOLORKEY.u8R); ++ str += scnprintf(str, end - str, " Green : 0x%2x\n",genGOPCOLORKEY.u8G); ++ str += scnprintf(str, end - str, " Blue : 0x%2x\n",genGOPCOLORKEY.u8B); ++ } ++ else ++ str += scnprintf(str, end - str, " Colorkey Status: Unknown\n"); ++ ++ ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++DEVICE_ATTR(gopinfo, 0644, gopinfo_show, gopinfo_store); ++ ++ ++//close for device tree structure ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_platform_release +++------------------------------------------------------------------------------ ++| DESCRIPTION : when module is unloaded, this function will be called ++| This is called when the reference count goes to zero. ++| ++| RETURN : no return value ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| device | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++/* ++static void mdrvinfinityfb_platform_release(struct device *device) ++{ ++ ++ MstarFB_ENTER(); ++ ++ if (NULL == device) ++ { ++ FBDBG("ERROR: in mdrvinfinityfb_platform_release, \ ++ device is NULL pointer !\r\n"); ++ } ++ else ++ { ++ FBDBG("in mdrvinfinityfb_platform_release, module unload!\n"); ++ } ++ ++ MstarFB_LEAVE(); ++} ++*/ ++#if 0 ++void mdrvgop_DispCreateGWin2(struct fb_info *WG) ++{ ++ ++ int xx=0; ++ xx++; ++ ++ FBDBG("fb%d: mdrv frame buffer device, of video memory\n", WG->node); ++} ++#endif ++static int mdrvinfinityfb_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ int clockIdxtemp=0; ++ FBDBG("[FB Driver] in mdrvinfinityfb_suspend \r\n"); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop_clks[clockIdxtemp]); ++ } ++ } ++ //clk_disable_unprepare(gop_psram_clk); ++ return 0; ++} ++ ++static int mdrvinfinityfb_resume(struct platform_device *pdev) ++{ ++ //dma_addr_t fb2_PHY_ADD_SHOW=0; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop_clks[clockIdxtemp])) ++ { ++ FBDBG( "[FB Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_clks[clockIdxtemp]); ++ } ++ } ++ } ++/* ++ if (IS_ERR(gop_psram_clk)) ++ { ++ FBDBG( "[FB Driver] Error: Fail to get gop palette sram (psram) clk!\n" ); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_psram_clk); ++ } ++*/ ++ FBDBG("[FB Driver] mdrvinfinityfb_resume \r\n"); ++ ++ GOP_Setmode(TRUE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ //set palette ++ mdrvinfinityfb_infinity_SetPalette(stGOPCurrentPalInfo,0,255); ++/* ++ if(unlikely(useCalibrationFrameBuffer)) ++ { ++ fb2_PHY_ADD_SHOW = sg_G3D_fb2_bus_addr1 + ((sg_mdrvinfinityfb_default_var.xres * sg_mdrvinfinityfb_default_var.yres * ANDROID_BYTES_PER_PIXEL)*ANDROID_NUMBER_OF_BUFFERS); ++ GOP_Setmode(TRUE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,fb2_PHY_ADD_SHOW,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ } ++ else ++ { ++ GOP_Setmode(TRUE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ } ++*/ ++ //printk("fb2 resume sleep ! \n"); ++ //msleep(5000); ++ return 0; ++} ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : Initialization. Initial HW, fill table, when load module, ++| this function will be called. ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++ ++static int mdrvinfinityfb_probe(struct platform_device *dev) ++{ ++ struct fb_info *pinfo = NULL; ++ int retval = -ENOMEM; ++ int ret=-1; ++ int fb_format=0; ++ int clockIdxtemp=0; ++ ++ num_parents_clocks = of_clk_get_parent_count(dev->dev.of_node); ++ gop_clks=kzalloc(((sizeof(struct clk *) * num_parents_clocks)),GFP_KERNEL); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ gop_clks[clockIdxtemp]= of_clk_get(dev->dev.of_node, clockIdxtemp); ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop_clks[clockIdxtemp])) ++ { ++ FBDBG( "[FB Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ //gop_psram_clk = gop_clks[0]; ++ //gop_scl_fclk1 = gop_clks[1]; ++ ++/* ++ if (IS_ERR(gop_psram_clk)) ++ { ++ FBDBG( "[FB Driver] ERROR: Fail to get gop palette sram (psram) clk!\n" ); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_psram_clk); ++ } ++*/ ++ //MstarFB_ENTER(); ++ ++ mdrvinfinityfb_updateinfo(); ++ ++ if (NULL == dev) ++ { ++ FBDBG("[FB Driver] ERROR: in mdrvinfinityfb_prob: dev is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ fb_format=ANDROID_FB_FORMAT; ++ ++ // static global variable, pass at probe(), used by dma alloc and dma free in ioctl(), ++ psg_mdrv_fbdev0 = dev; ++ ++ //FBDBG("mdrvinfinityfb: GOPmemorysize is 0x%X\n",(unsigned int)sg_videomemorysize); ++ ++ /* For G3D frame buffer2 */ ++ /* ++ if (!(sg_pG3D_fb2_vir_addr1 = alloc_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ &sg_G3D_fb2_bus_addr1))) ++ { ++ FBDBG("mdrvinfinityfb: unable to allocate screen memory\n"); ++ return retval; ++ } ++ */ ++ ++ //printk("---------1 \n"); ++ //msleep(6000); ++ // prevent initial garbage on screen ; to clean memory ++ //memset(CAST_2_IOMEM_CHAR_P sg_pG3D_fb2_vir_addr1,OTHER_COLOR, sg_videomemorysize); ++ ++ //FBDBG("[FB Driver] mdrvinfinityfb vir=0x%x, phy=0x%x\n", (unsigned int)sg_pG3D_fb2_vir_addr1, sg_G3D_fb2_bus_addr1); ++ ++ sg_mdrvinfinityfb_fix.smem_start = sg_G3D_fb2_bus_addr1; ++ sg_mdrvinfinityfb_fix.smem_len = sg_videomemorysize; ++ ++ pinfo = framebuffer_alloc(sizeof(struct fb_info), &dev->dev); ++ if (!pinfo) ++ goto err; ++ ++ ++ pinfo->screen_base = CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ //FBDBG( "[FB Driver] sg_mdrvinfinityfb_fix.smem_start=0x%x ",(unsigned int) sg_mdrvinfinityfb_fix.smem_start); ++ ++ //printk("---------2 \n"); ++ //msleep(6000); ++ ++ pinfo->fbops = &sg_mdrvinfinityfb_ops; ++ pinfo->var = sg_mdrvinfinityfb_default_var; ++ pinfo->fix = sg_mdrvinfinityfb_fix; ++ pinfo->pseudo_palette = pinfo->par; ++ pinfo->par = NULL; ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ ++ ++ /* allocate color map */ ++ /* 256 is following to the vfb.c */ ++ retval = fb_alloc_cmap(&pinfo->cmap, 256, 0); ++ if (retval < 0) ++ goto err1; ++ ++ ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ pinfo->fix.type = FB_TYPE_PACKED_PIXELS; ++ pinfo->fix.visual = FB_VISUAL_TRUECOLOR; ++ pinfo->fix.line_length = sg_mdrvinfinityfb_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ pinfo->fix.accel = FB_ACCEL_NONE; ++ pinfo->fix.ypanstep = 1; ++ ++ pinfo->var.xres = sg_mdrvinfinityfb_default_var.xres; ++ pinfo->var.yres = sg_mdrvinfinityfb_default_var.yres; ++ pinfo->var.xres_virtual = sg_mdrvinfinityfb_default_var.xres; ++ pinfo->var.yres_virtual = sg_mdrvinfinityfb_default_var.yres * ANDROID_NUMBER_OF_BUFFERS; ++ pinfo->var.bits_per_pixel = BPX; ++ pinfo->var.activate = FB_ACTIVATE_NOW; ++ pinfo->var.height = sg_mdrvinfinityfb_default_var.yres; ++ pinfo->var.width = sg_mdrvinfinityfb_default_var.xres; ++ pinfo->fix.smem_len = sg_videomemorysize; ++ ++ //printk("---------3 \n"); ++ //msleep(6000); ++ ++ ++ if (RGB565==fb_format) ++ { ++ pinfo->var.red.offset = 11; ++ pinfo->var.red.length = 5; ++ pinfo->var.green.offset = 5; ++ pinfo->var.green.length = 6; ++ pinfo->var.blue.offset = 0; ++ pinfo->var.blue.length = 5; ++ } ++ else if(ARGB8888==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 8; ++ pinfo->var.red.length = 8; ++ pinfo->var.green.length = 8; ++ pinfo->var.blue.length = 8; ++ ++ pinfo->var.transp.offset = 24; ++ pinfo->var.red.offset = 16; ++ pinfo->var.green.offset = 8; ++ pinfo->var.blue.offset = 0; ++ } ++ // same define as cedric ++ else if(RGBA8888==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 8; ++ pinfo->var.red.length = 8; ++ pinfo->var.green.length = 8; ++ pinfo->var.blue.length = 8; ++ ++ pinfo->var.transp.offset = 0; ++ pinfo->var.red.offset = 24; ++ pinfo->var.green.offset = 16; ++ pinfo->var.blue.offset = 8; ++ } ++ else if(_8Bit_Palette==fb_format) ++ { ++ pinfo->var.grayscale = 0; ++ ++ pinfo->var.transp.length = 0; ++ pinfo->var.red.length = 0; ++ pinfo->var.green.length = 0; ++ pinfo->var.blue.length = 0; ++ ++ pinfo->var.transp.offset = 0; ++ pinfo->var.red.offset = 0; ++ pinfo->var.green.offset = 0; ++ pinfo->var.blue.offset = 0; ++ } ++ else ++ { ++ FBDBG( "[FB Driver] ERROR: mdrvinfinityfb_probe fb_format =%d Not Support!!\n", fb_format); ++ while(1); ++ } ++ ++ ++ ++ ++ /* register mdrvfb to fbmem.c */ ++ retval = register_framebuffer(pinfo); ++ if (retval < 0) ++ goto err2; ++ ++ platform_set_drvdata(dev, pinfo); ++ ++ //patch some setting due to our panel setting may have problems ++ { ++ struct list_head *pos; ++ struct fb_modelist *modelist; ++ ++ list_for_each(pos, &pinfo->modelist) { ++ modelist = list_entry(pos, struct fb_modelist, list); ++ modelist->mode.refresh=sg_mdrvinfinityfb_default_fbmode.refresh; ++ } ++ } ++ ++ //printk("---------4 \n"); ++ //msleep(6000); ++ ++ /* ======================================================== */ ++ /* HW INIT related code */ ++ /* ======================================================== */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_58 , 0x1); /* power switch enable */ ++ ++ //CLRREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_57, 0x0200); /* external device power on output enable */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_57, 0x0002); /* external device power on enable */ ++ ++ /* 0. CHIPTOP Register - BIT_9 : Enable RGB output, Bit_14 reg_OP2_en */ ++ //SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_09 , 0x4200); /* */ ++ ++ //ms_writew( 0x0040,MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_26); //add ++ ++ /* h'28 CLK_GE clock control */ ++ /* ++ //weichun temp disable ++ CLRREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_28, 0x1F); ++ SETREG16(MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_28 , 0x8); ++ */ ++ /*h'2A CLK_GOPG0 clock control */ ++ /* ++ ++ */ ++ /* 2. Set CLK_ODCLK's source is LPLL */ ++ //ms_writew( 0x1C00,MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_1B); ++ ++ ++ //CLRREG16(0xA0002604 , 0x0008); ++ ++ //ms_writew(0, MS_BASE_REG_CHIPTOP_PA + REG_CHIPTOP_2C ); ++ ++ /* Create GWIN, make a window to show graph, setting HW(GOP) */ ++ //mdrvgop_DispCreateGWin(); ++ ++ // FB info ++ // FB Width ++ // FB Pitch ++ // FB Height ++ // FB Starting address ++ // FB Format ++ ++ // View info ++ ++ // mdrvgop_DispCreateGWin2(pinfo); ++ //mdrvgop_DispCreateGWin(sg_G3D_Fb_bus_addr1,sg_G3D_Fb_bus_addr2,sg_mdrvfb_default_var.xres,sg_mdrvfb_default_var.yres,ANDROID_BYTES_PER_PIXEL); ++// #if (UBOOT_SHOW_LOGO==0) ++ ++ ++ GOP_Setmode(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ //set palette ++ mdrvinfinityfb_infinity_SetPalette(DefaultPaletteEntry,0,255); ++ ++ //register sysfs ++ ret = device_create_file(&dev->dev, &dev_attr_gopinfo); ++ if (ret != 0) ++ { ++ dev_err(&dev->dev, ++ "[FB Driver] Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ else ++ { ++ FBDBGMORE("[FB Driver] device attr ok\n"); ++ } ++ ++ //set to sca2 for test Infinity in cedric ++ /* ++ #define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x123000/2)) ++ #define mdrv_BASE_REG_DIP GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x133400/2)) ++ #define mdrv_BASE_REG_CLKGEN GET_REG16_ADDR(COLUMBUS_BASE_REG_RIU_PA, (0x100B00/2)) ++ OUTREG16(mdrv_BASE_REG_GOP00_PA + (0x7E<<2),0x924); ++ OUTREG16(mdrv_BASE_REG_GOP00_PA + (0x7B<<2),0x04); ++ OUTREG16(mdrv_BASE_REG_GOP00_PA + (0x01<<2),((INREG16(mdrv_BASE_REG_GOP00_PA + (0x01<<2))&0xFFF0)|0x07)); ++ OUTREG16(mdrv_BASE_REG_DIP+ (0x10<<2),((INREG16(mdrv_BASE_REG_DIP + (0x10<<2)))&0xFFEE)|0x11); ++ OUTREG16(mdrv_BASE_REG_CLKGEN+ (0x40<<2),((INREG16(mdrv_BASE_REG_CLKGEN + (0x40<<2)))&0xFFF0)|0x04); ++ GOP_Set_OutFormat(0,1); ++ */ ++ ++ ++ //#else ++ // GOP_Change_Alpha(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++// #endif ++ ++ ++// FBDBG("fb%d: mdrv frame buffer device, using %ldK of video memory\n", pinfo->node, sg_videomemorysize >> 10); ++ ++ //printk("---------5 \n"); ++ //msleep(6000); ++ //MstarFB_LEAVE(); ++ return 0; ++ ++err2: ++ fb_dealloc_cmap(&pinfo->cmap); ++err1: ++ framebuffer_release(pinfo); ++err: ++ ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ ++ return retval; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : we free memory, release frame buffer here ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb_remove(struct platform_device *dev) ++{ ++ struct fb_info *pinfo; ++ int clockIdxtemp=0; ++ pinfo = 0; ++ ++ ++ //MstarFB_ENTER(); ++ ++ ++ if (NULL == dev) ++ { ++ FBDBG("[FB Driver] ERROR: mdrvinfinityfb_remove: dev is NULL pointer \n"); ++ return -ENOTTY; ++ } ++ ++ pinfo = platform_get_drvdata(dev); ++ if (pinfo) ++ { ++ unregister_framebuffer(pinfo); ++ ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ ++ framebuffer_release(pinfo); ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ //clk_disable_unprepare(gop_psram_clk); ++ ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop_clks[clockIdxtemp]); ++ } ++ } ++ return 0; ++} ++ ++static int mdrvinfinityfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ dma_addr_t fb2_pandisplay_PHY_ADD_SHOW=0; ++ ++ //MstarFB_ENTER(); ++ ++ //FBDBG( "mdrvinfinityfb_pan_display: var->yoffset=%x! info->var.height=%x\n ",var->yoffset,info->var.height); ++ if(genGOPGernelSettings.enBufferNum==FB_DOUBLE_BUFFER)//double buffer ++ { ++ if (var->yoffset >= info->var.height) ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start + (info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL); ++ ++ FBDBGMORE( "mdrvinfinityfb_pan_display: use buffer 1! Addr=%x\n ",fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ else ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start; ++ ++ FBDBGMORE( "mdrvinfinityfb_pan_display: use buffer 0 Addr=%x!\n ",fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ } ++ else//single buffer, always show first buffer ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start; ++ ++ FBDBGMORE( "mdrvinfinityfb_pan_display: use buffer 0 Addr=%x!\n ",fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ ++ GOP_Pan_Display(0, fb2_pandisplay_PHY_ADD_SHOW); ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++ ++//check var to see if supported by this device, defined for infinity ++static int mdrvinfinityfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //MstarFB_ENTER(); ++ ++ if((var->yres<1)||(var->xres<1)) ++ { ++ FBDBG( "[FB Driver] Error: fb_check_var: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ if((var->yres * var->xres)>(1920*1088)) ++ { ++ FBDBG( "[FB Driver] Error: fb_check_var: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ ++ if((var->xres % DisplayPerPixel)!=0) ++ { ++ FBDBG( "[FB Driver] Error: fb_check_var: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++//close for device tree structure ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvfb_init +++------------------------------------------------------------------------------ ++| DESCRIPTION : register the driver to kernel, ++| to tell it what facility or function we provide ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| ++| Variable Name : no variable +++------------------------------------------------------------------------------ ++*/ ++/* ++int _mdrvinfinityfb_init(void) ++{ ++ int ret = 0; ++ ++ MstarFB_ENTER(); ++ ++ //register the driver into kernel ++ ++ // how to get the Panel type and what kind of output display device ++ ++ ++ //MApi_PNL_Init(tPanelNANOVISON_45); ++ ++ mdrvinfinityfb_updateinfo(); ++ ++ ret = platform_driver_register(&sg_mdrvinfinityfb_driver); ++ ++ if (!ret) ++ { // register driver sucess ++ // register device ++ ret = platform_device_register(&sg_mdrvinfinityfb_device); ++ if (ret) // if register device fail, then unregister the driver. ++ { ++ platform_driver_unregister(&sg_mdrvinfinityfb_driver); ++ printk(KERN_INFO"mdrvinfinityfb_device register failed...\n"); ++ } ++ else ++ { ++ printk(KERN_INFO"mdrvinfinityfb_device register success...\n"); ++ } ++ } ++ ++ MstarFB_LEAVE(); ++ ++ return ret; ++} ++module_init(_mdrvinfinityfb_init); //tell kernel where the init function ++*/ ++ ++module_platform_driver(sg_mdrvinfinityfb_driver); ++ ++ ++#ifdef MODULE ++/* ++static void mdrvinfinityfb_platform_release(struct device *device) ++{ ++ ++ //MstarFB_ENTER(); ++ ++ if (NULL == device) ++ { ++ FBDBG("ERROR: in mdrvinfinityfb_platform_release, \ ++ device is NULL pointer !\r\n"); ++ } ++ else ++ { ++ FBDBG("in mdrvinfinityfb_platform_release, module unload!\n"); ++ } ++ ++ //MstarFB_LEAVE(); ++} ++ ++static int __init _mdrvinfinityfb_init(void) ++{ ++ int ret = 0; ++ ++ //MstarFB_ENTER(); ++ ++ //register the driver into kernel ++ ++ // how to get the Panel type and what kind of output display device ++ ++ ++ //MApi_PNL_Init(tPanelNANOVISON_45); ++ ++ mdrvinfinityfb_updateinfo(); ++ ++ ret = platform_driver_register(&sg_mdrvinfinityfb_driver); ++ ++ if (!ret) ++ { // register driver sucess ++ // register device ++ ret = platform_device_register(&sg_mdrvinfinityfb_device); ++ if (ret) // if register device fail, then unregister the driver. ++ { ++ platform_driver_unregister(&sg_mdrvinfinityfb_driver); ++ printk(KERN_INFO"mdrvinfinityfb_device register failed...\n"); ++ } ++ else ++ { ++ printk(KERN_INFO"mdrvinfinityfb_device register success...\n"); ++ } ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return ret; ++} ++module_init(_mdrvinfinityfb_init); //tell kernel where the init function ++ ++static void __exit mdrvinfinityfb_exit(void) ++{ ++ ++ //MstarFB_ENTER(); ++ ++ platform_device_unregister(&sg_mdrvinfinityfb_device); ++ ++ platform_driver_unregister(&sg_mdrvinfinityfb_driver); ++ ++ //MstarFB_LEAVE(); ++ ++} ++ ++module_exit(mdrvinfinityfb_exit); // tel kernel where is the clean up function ++*/ ++ ++MODULE_LICENSE("GPL"); ++/* use GPL license to avoid Kernel to complain this driver */ ++#endif /* MODULE */ ++ ++ ++ ++//MODULE_LICENSE("GPL") +diff --git a/drivers/mstar/fb/infinity/mdrv_fb.h b/drivers/mstar/fb/infinity/mdrv_fb.h +new file mode 100644 +index 00000000..f0b23027 +--- /dev/null ++++ b/drivers/mstar/fb/infinity/mdrv_fb.h +@@ -0,0 +1,305 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_fb.h ++ * DESCRIPTION ++ * Including some MACRO needed in mdrvfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/mdrvfb.h -- mdrvfb frame buffer device ++ ******************************************************************************/ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include /* access_ok(), and VERIFY_WRITE/READ */ ++#include /* for _IO() macro */ ++#include ++#include ++#include ++#include /* do_gettimeofday() */ ++#include "gop/mdrv_gop.h" ++//#include "gop/mdrv_gop.h" ++//#include "gop/mdrv_gop_io.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" /* for dma_alloc_coherent */ ++#include ++#include ++ ++ ++ ++ ++#define FB_DEBUG 1 //0 for no debug message, 1 for normal debug message, 2 for more message ++#define FB_FUNBUG 1 ++ ++// same define as cedric ++#define UBOOT_SHOW_LOGO 1 ++ ++ ++#if (FB_DEBUG==1) ++#define FBDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBGMORE(fmt, arg...) ++#elif (FB_DEBUG==2) ++#define FBDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBGMORE(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define FBDBG(fmt, arg...) ++#define FBDBGMORE(fmt, arg...) ++#endif ++ ++//#define MstarTrace printk ++ ++#if 0 ++#if (FB_FUNBUG==1) ++#define MstarTrace printk ++#else ++#define MstarTrace if(0) printk ++#endif ++#endif ++ ++//#define MstarFB_ENTER(...) MstarTrace("= FB =\n"); MstarTrace("%s START\n", __func__) ++//#define MstarFB_LEAVE(...) MstarTrace("%s END\n", __func__);MstarTrace("= FB =\n") ++ ++ ++#ifdef mdrv_GEN_FB_C /* in frame buffer driver */ ++#define PRIVATE_FB_DATA ++#else /* in user space */ ++#define PRIVATE_FB_DATA const ++#endif /* mdrv_GEN_FB_C */ ++ ++ ++/* ========================================================================= */ ++/* define type cast macro */ ++#define CAST_2_USER_VOID_P (void __user *) ++#define CAST_2_USER_UINT_P (unsigned int __user *) ++#define CAST_2_USER_TEXTURE_INFO_P (TEXTURE_INFO __user *) ++#define CAST_2_IOMEM_CHAR_P (u8 __iomem *) ++#define CAST_2_ULONG (unsigned long) ++ ++ ++//static int useCalibrationFrameBuffer = 0 ; ++ ++ ++/* ========================================================================= */ ++/* define color */ ++#define COLOR_MASK 0xffff ++#define WHITE_COLOR 0xffff ++#define OTHER_COLOR 0xFF00 ++ ++ ++#define ANDROID_NUMBER_OF_BUFFERS 1 ++ ++ ++// same define as cedric ++//test change to i8 ++#define ANDROID_FB_FORMAT _8Bit_Palette ++//#define ANDROID_FB_FORMAT RGBA8888 ++ ++ ++#define defult_XRES 800 // PANEL_WIDTH ++#define defult_YRES 480 //PANEL_HEIGHT ++#if (ANDROID_FB_FORMAT == RGB565) ++#define BPX 16 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 2 ++#elif ((ANDROID_FB_FORMAT == ARGB8888) || (ANDROID_FB_FORMAT == RGBA8888)) ++#define BPX 32 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 4 ++#elif (ANDROID_FB_FORMAT == _8Bit_Palette) ++#define BPX 8 /* bits per pixel */ ++#define ANDROID_BYTES_PER_PIXEL 1 ++#else ++ #ERROR("Not Support") ++#endif ++ ++ ++/* ========================================================================= */ ++/* prototype of function */ ++ ++static s32 mdrvinfinityfb_ioctl(struct fb_info *info, u32 cmd, unsigned long arg); ++static s32 mdrvinfinityfb_mmap(struct fb_info *info, struct vm_area_struct *vma); ++static s32 mdrvinfinityfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); ++static s32 mdrvinfinityfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info); ++static s32 mdrvinfinityfb_set_par(struct fb_info *info); ++ ++ ++static struct fb_var_screeninfo sg_mdrvinfinityfb_default_var = ++{ ++ .xres = defult_XRES, ++ .yres = defult_YRES, ++ .xres_virtual = defult_XRES, ++ .yres_virtual = defult_YRES, ++ .bits_per_pixel = BPX, ++#if (BPX == 32) ++ .transp ={0,8,0}, ++ .red = { 24, 8, 0 }, /* {offset,length,!= 0 : MSB is right} */ ++ .green = { 16, 8, 0 }, ++ .blue = { 8, 8, 0 }, ++#elif (BPX == 16) ++ .red = { 11, 5, 0 }, /* {offset,length,!= 0 : MSB is right} */ ++ .green = { 5, 6, 0 }, ++ .blue = { 0, 5, 0 }, ++#endif ++ .activate = FB_ACTIVATE_NOW, ++ .height = -1, /* =maximum, in fb.h is delcalred as _u32* */ ++ .width = -1, ++ ++ /* timing useless ? use the vfb default */ ++ .pixclock = 100000,//20000, /* pixel clock in ps (pico seconds) */ ++ .left_margin = 24,//64, /* time from sync to picture */ ++ .right_margin = 4,//64, /* time from picture to sync */ ++ .upper_margin = 6,//32, /* time from sync to picture */ ++ .lower_margin = 4,//32, ++ .hsync_len = 64, /* length of horizontal sync */ ++ .vsync_len = 2, /* length of vertical sync */ ++ .vmode = FB_VMODE_NONINTERLACED, ++ /* non interlaced, the most basical framebuffer */ ++}; ++ ++/* Device independent unchangeable information */ ++static struct fb_fix_screeninfo sg_mdrvinfinityfb_fix = ++{ ++ .id = "mdrv FB", ++ .type = FB_TYPE_PACKED_PIXELS, /* see FB_TYPE_* */ ++ .visual = FB_VISUAL_TRUECOLOR, /* see FB_VISUAL_* */ ++ .xpanstep = 0, /* zero if no hardware panning */ ++ .ypanstep = 0, ++ .ywrapstep = 0, ++ .line_length = (defult_XRES * BPX >> 3), /* length of a line in bytes */ ++ .mmio_start=0x20000000, /* Start of Memory Mapped I/O */ ++ /* (physical address) */ ++ .mmio_len=0x10000000, /* Length of Memory Mapped I/O */ ++ .accel = FB_ACCEL_NONE, ++ /* Indicate to driver which specific chip/card we have */ ++}; ++ ++static struct fb_videomode sg_mdrvinfinityfb_default_fbmode; ++ ++static struct fb_ops sg_mdrvinfinityfb_ops = ++{ ++ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = sys_fillrect, ++ ++ /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = sys_copyarea, ++ ++ /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = sys_imageblit, ++ ++ /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ .fb_mmap = mdrvinfinityfb_mmap, /* for non cached memory */ ++ ++ /* vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); */ ++ .fb_ioctl = mdrvinfinityfb_ioctl, ++ ++ .fb_pan_display = mdrvinfinityfb_pan_display, ++ ++ .fb_check_var = mdrvinfinityfb_check_var, ++ ++ .fb_set_par = mdrvinfinityfb_set_par, ++ ++}; ++ ++//extern void MDrv_Scaler_Enable_GOP(BOOL); ++extern void sys_fillrect(struct fb_info *p, const struct fb_fillrect *rect); ++ ++/* virtual address in Kernel space, used in probe(), remove() */ ++//static void *sg_pG3D_fb2_vir_addr1 = 0; /* virtual address of frame buffer 1 */ ++static void *sg_pG3D_fb2_vir_addr1 = 0; /* virtual address of frame buffer 2 */ ++ ++#if 1 //def CONFIG_PM ++static int mdrvinfinityfb_suspend(struct platform_device *pdev, ++ pm_message_t state); ++ ++static int mdrvinfinityfb_resume(struct platform_device *pdev); ++#else ++#define mdrvinfinityfb_suspend NULL ++#define mdrvinfinityfb_resume NULL ++#endif ++ ++ ++ ++static int mdrvinfinityfb_probe(struct platform_device *dev); ++static int mdrvinfinityfb_remove(struct platform_device *dev); ++ ++/* device .name and driver .name must be the same, then it will call ++ probe function */ ++static const struct of_device_id infinity_infinityfb_dt_ids[] = ++{ ++ { .compatible = "mstar,infinity-gop" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, infinity_infinityfb_dt_ids); ++ ++static struct platform_driver sg_mdrvinfinityfb_driver = ++{ ++ .probe = mdrvinfinityfb_probe, /* initiailize */ ++ .remove = mdrvinfinityfb_remove, /* it free(mem), ++ release framebuffer, free irq etc. */ ++ .suspend = mdrvinfinityfb_suspend, ++ .resume = mdrvinfinityfb_resume, ++ ++ .driver = ++ { ++ .name = "mdrvinfinityfb", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(infinity_infinityfb_dt_ids), ++ }, ++}; ++ ++//close for device tree structure ++#ifdef MODULE ++/* ++static void mdrvinfinityfb_platform_release(struct device *device); ++ ++static u64 sg_mdrvinfinityfb_device_lcd_dmamask = 0xffffffffUL; ++// for 0x08000000 ++ ++static struct platform_device sg_mdrvinfinityfb_device = ++{ ++ .name = "mdrvinfinityfb", ++ .id = 0, ++ .dev = ++ { ++ .release = mdrvinfinityfb_platform_release, ++ .dma_mask = &sg_mdrvinfinityfb_device_lcd_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++*/ ++#endif +diff --git a/drivers/mstar/fb/infinity3/Makefile b/drivers/mstar/fb/infinity3/Makefile +new file mode 100644 +index 00000000..d2d3a745 +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/Makefile +@@ -0,0 +1,19 @@ ++# ++# Makefile for MStar fb device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++#--------gop-------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb/infinity3/gop ++EXTRA_CFLAGS += -Idrivers/mstar/fb/infinity3/inv_color ++ ++# files ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop_io.o ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop.o ++#obj-$(CONFIG_MS_FB_INFINITY) += mdrv_fb.o ++ ++obj-$(CONFIG_MS_FB_INFINITY3) += infinity_fb.o ++ ++infinity_fb-objs := mdrv_fb.o \ ++ gop/mdrv_gop.o \ ++ inv_color/mdrv_gop0_inv_color.o +\ No newline at end of file +diff --git a/drivers/mstar/fb/infinity3/gop/gop_c2_reg.h b/drivers/mstar/fb/infinity3/gop/gop_c2_reg.h +new file mode 100644 +index 00000000..8839c0ae +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/gop/gop_c2_reg.h +@@ -0,0 +1,249 @@ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME gop_c2_reg.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define BASE_REG_RIU_PA (0x1F000000) ++ ++//GOP Base register defines ++//if there's no direct bank, the base addresses of GOP00, GOP01 and GOP02 are the same ++//I1 settings ++//#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//I3 settings ++#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123100/2)) ++#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123200/2)) ++#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123300/2)) ++ ++//MIU Bus settings ++#define MIU_BUS_INFINITY3 0x4 ++#define MIU_BUS_ALIGN MIU_BUS_INFINITY3 ++ ++ ++#define mdrv_GWin0_Disable (0xFFFE) ++#define mdrv_GWIN0_Enable (0x1) ++ ++#define mdrv_ENABLE_CONST_ALPHA (~(0x1<<14)) ++ ++//fomrat define ++#define GWIN_FMT_MASK 0x00F0 ++#define RGB1555_Blink 0x0000 ++#define RGB565 0x0010 ++#define ARGB4444 0x0020 ++#define _2266 0x0030 ++#define _8Bit_Palette 0x0040 ++#define ARGB8888 0x0050 ++#define ARGB1555 0x0060 ++#define ABGR8888 0x0070 ++#define RGB1555_UV7Y8 0x0080 ++#define UV8Y8 0x0090 ++#define RGBA5551 0x00A0 ++#define RGBA4444 0x00B0 ++ ++//------------------------------------------------------------------------------ ++// GOP ++//------------------------------------------------------------------------------ ++// Bank 0, GOPG0_0 ++ ++// REG_GOP_00 ++#define GOP_SOFT_RESET 0x0001 ++#define GOP_VS_INV 0x0002 ++#define GOP_HS_INV 0x0004 ++#define GOP_DISPLAY_MODE 0x0008 // 0:interlace, 1: progress ++#define GOP_FIELD_INV 0x0010 ++#define GOP_YUV_TRANSPARENT_COLOR_ENABLE 0x0020 ++#define GOP_TEST_PATTENR_MODE_ENABLE 0x0040 ++#define GOP_5541_EN 0x0080 // RGB5541 alpha mask mode enable, only for RGB1555 Data type ++#define GOP_REG_OUTPUT_READY 0x0100 ++#define GOP_G3D_FORMATE_NEW_MODE_ENABLE 0x0200 ++#define GOP_OUTPUT_FORMAT 0x0400 // 0:RGB out, 1:YUV out ++#define GOP_RGB_TRANSPARENT_COLOR_MASK 0x0800 ++#define GOP_DISP_HBACK_ENABLE 0x1000 // H Mirror enable; H pixel read out direction, 0:forward, 1:backward ++#define GOP_DISP_VBACK_ENABLE 0x2000 // V Mirror enable; V line read out direction, 0:down, 1:up ++#define GOP_HS_MASK 0x4000 ++#define GOP_ALPHA_INV 0x8000 ++// GOP Display Mode ++#define GWIN_display_mode_progress 0x0008 ++#define GWIN_display_mode_interlace 0x0000 ++// GOP Output Color ++#define GOP_YUVOUT 0x0400 ++#define GOP_RGBOUT 0x0000 ++// GOP RGB Transparent Color ++#define GOP_RGB_TRANSPARENT_COLOR_ENABLE 0x0800 ++#define GOP_RGB_TRANSPARENT_COLOR_DISABLE 0x0000 ++ ++ ++// REG_GOP_01 ++// GOP Destination ++#define GOP_DST_IP_MAIN 0x0000 ++#define GOP_DST_IP_SUB 0x0001 ++#define GOP_DST_OP 0x0002 ++#define GOP_DST_MVOP 0x0003 ++#define GOP_DST_SUB_MVOP 0x0004 ++#define GOP_DST_FRC 0x0006 ++// GOP interval settings ++#define GOP_REGDMA_INTERVAL_START 0x0200 //infinity:0x0200; cedric:0x0300 ++#define GOP_REGDMA_INTERVAL_END 0x4000 //infinity:0x4000; cedirc:0x5000 ++ ++ ++// REG_GOP_02 ++#define GOP_BLINK_DISABLE 0x0000 ++#define GOP_BLINK_ENABLE 0x8000 ++ ++// REG_GOP_05 ++#define GOP_PALETTE_TABLE_ADDRESS_MASK 0x00FF //palette index ++#define GOP_PALETTE_WRITE_ENABLE_MASK 0x0100 ++#define GOP_PALETTE_READ_ENABLE_MASK 0x0200 ++#define GOP_PALETTE_SRAM_CTRL_MASK 0x3000 //0:RIU mode; 1:REGDMA mode; 2,3:for external gop ++#define GOP_PALETTE_SRAM_CTRL_RIU 0x0000 ++#define GOP_PALETTE_SRAM_CTRL_REGDMA 0x1000 ++ ++ ++ ++// REG_GOP_06 ++#define GOP_REGDMA_END 0x0034 ++ ++ ++// REG_GOP_07 ++#define GOP_REGDMA_STR 0x0000 ++ ++ ++// REG_GOP_0F ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++#define GOP_HSYNC_PIPE_DLY_FOR_SC1_OP 0x00A0 ++#define HSYNC_PIPE_DLY_FOR_SC0_2GOP 0x0044 ++ ++// inifinity settings ++#define INIFINITY_GOP_HSYNC_PIPE_DLY 0x0000 ++#define GOP_HSYNC_PIPE_DLY INIFINITY_GOP_HSYNC_PIPE_DLY ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++ ++ ++// REG_GOP_19 ++#define GOP_BURST_LENGTH_MASK 0x1F00 ++#define GOP_BURST_LENGTH_MAX 0x1F00 ++#define GOP_BURST_LENGTH_AUTO 0x0000 ++ ++ ++// REG_GOP_20 ++#define GOP_GWIN_HIGH_PRI_0 0x0000 ++#define GOP_GWIN_HIGH_PRI_1 0x0001 ++ ++// REG_GOP_32 ++#define GOP_STRETCH_HST 0x0000 ++ ++// REG_GOP_34 ++#define GOP_STRETCH_VST 0x0000 ++ ++// REG_GOP_35 ++#define GOP_STRETCH_HRATIO 0x1000 ++ ++// REG_GOP_36 ++#define GOP_STRETCH_VRATIO 0x1000 ++ ++// REG_GOP_38 ++#define GOP_STRETCH_HINI 0x0000 ++ ++// REG_GOP_39 ++#define GOP_STRETCH_VINI 0x0000 ++ ++// REG_GOP_7E ++//#define GOP_GOPG0_MUX_MASK 0x0007 ++//#define GOP_GOPG0_MUX_4G 0x0000 ++//#define GOP_GOPG0_MUX_2G 0x0001 ++ ++//#define GOP_Layer0_MUX_MASK 0x0007 ++//#define GOP_Layer0_Sel_GOP0 0x0000 ++//#define GOP_Layer0_Sel_GOP1 0x0001 ++//#define GOP_Layer0_Sel_GOP2 0x0002 ++//#define GOP_Layer0_Sel_GOP3 0x0003 ++//#define GOP_Layer0_Sel_GOP_Null 0x0004 ++ ++//#define GOP_Layer1_MUX_MASK (0x0007)<<3 ++//#define GOP_Layer1_Sel_GOP0 (0x0000)<<3 ++//#define GOP_Layer1_Sel_GOP1 (0x0001)<<3 ++//#define GOP_Layer1_Sel_GOP2 (0x0002)<<3 ++//#define GOP_Layer1_Sel_GOP3 (0x0003)<<3 ++//#define GOP_Layer1_Sel_GOP_Null (0x0004)<<3 ++ ++//#define GOP_Layer2_MUX_MASK (0x0007)<<6 ++//#define GOP_Layer2_Sel_GOP0 (0x0000)<<6 ++//#define GOP_Layer2_Sel_GOP1 (0x0001)<<6 ++//#define GOP_Layer2_Sel_GOP2 (0x0002)<<6 ++//#define GOP_Layer2_Sel_GOP3 (0x0003)<<6 ++//#define GOP_Layer2_Sel_GOP_Null (0x0004)<<6 ++ ++//#define GOP_Layer3_MUX_MASK (0x0007)<<9 ++//#define GOP_Layer3_Sel_GOP0 (0x0000)<<9 ++//#define GOP_Layer3_Sel_GOP1 (0x0001)<<9 ++//#define GOP_Layer3_Sel_GOP2 (0x0002)<<9 ++//#define GOP_Layer3_Sel_GOP3 (0x0003)<<9 ++//#define GOP_Layer3_Sel_GOP_Null (0x0004)<<9 ++ ++// REG_GOP_7F ++#define GOP_BANK_G0_0 0x0000 ++#define GOP_BANK_G0_1 0x0001 ++#define GOP_BANK_G1_0 0x0003 ++#define GOP_BANK_G1_1 0x0004 ++#define GOP_BANK_G2_0 0x0006 ++#define GOP_BANK_G2_1 0x0007 ++#define GOP_BANK_G3_0 0x0009 ++#define GOP_BANK_G3_1 0x000A ++#define GOP_BANK_GPD 0x0006 ++ ++#define GOP_BANK_DOUBLE_WR 0x0100 ++#define GOP_BANK_FORCE_WR 0x0200 ++ ++#define GOP_BANK_DOUBLE_WR_G0 0x0400 ++#define GOP_BANK_DOUBLE_WR_G1 0x0403 ++#define GOP_BANK_DOUBLE_WR_G2 0x0406 ++#define GOP_BANK_DOUBLE_WR_G3 0x0409 ++#define GOP_BANK_DOUBLE_WR_MSK 0x0400 ++#define GOP_BANK_SEL_MSK 0x000F ++ ++#define GOP_BANK_GOP0_WR_ACK_MSK 0x1000 ++#define GOP_BANK_GOP1_WR_ACK_MSK 0x2000 ++#define GOP_BANK_GOP2_WR_ACK_MSK 0x4000 ++ ++// GOP0 Bank 1 ++// REG_GOP_00 ++#define GOP0_GWin0_Enable 0x0001 ++#define GOP_PIXEL_ALPHA_EN 0x4000 ++#define GOP_CONSTANT_ALPHA_EN 0x0000 ++#define GOP_ALPHA_MASK 0x4000 +diff --git a/drivers/mstar/fb/infinity3/gop/mdrv_gop.c b/drivers/mstar/fb/infinity3/gop/mdrv_gop.c +new file mode 100644 +index 00000000..a0c9703b +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/gop/mdrv_gop.c +@@ -0,0 +1,764 @@ ++#include "mdrv_gop.h" ++ ++#define PARSING_FB_FORMAT(x)(\ ++ x == _8Bit_Palette ? "Palette_I8": \ ++ x == RGB565 ? "RGB565" : \ ++ x == ARGB4444 ? "ARGB4444" : \ ++ x == ARGB8888 ? "ARGB8888" : \ ++ x == ARGB1555 ? "ARGB1555" : \ ++ x == UV8Y8 ? "UV8Y8" : \ ++ "Format_Not_Support") ++ ++#define PARSING_ALPHA_TYPE(x)(\ ++ x == 0 ? "PIXEL_ALPHA": \ ++ x == 1 ? "CONST_ALPHA": \ ++ "Wrong_Alpha_Type") ++ ++ ++void SwitchSubBank(int subbank) ++{ ++ unsigned long GOP_Reg_Base=0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ if ((subbank>=0)&&(subbank<=2)) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,subbank); ++ GOPDBG( "[GOP]%s: Switch to Subbank %d\n",__func__,subbank); ++ } ++ else ++ GOPDBG( "[GOP]%s: Wrong Subbank %d\n",__func__,subbank); ++} ++ ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr ) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U32 s32BuffAddr = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ int wait_count = 0; ++ ++ // 1. Pan display works by changing framebuffer start address ++ ++ ++ GOPDBG ("[GOP]%s: in, addr=0x%x \n",__func__,FB_Start_Addr); ++ ++ /// GOP0_1 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ // GOP fetch framebuffer information ++ // set the starting address for showing by GOP ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS; //128-bit unit = 16 bytes ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); //Ring block start Low address 0x21:16 ++ s32BuffAddr = s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); //Ring block start Hi address 0x22:6, page number ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ while((INREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_BANK_GOP0_WR_ACK_MSK)!=0))//wait double buffer write ack ++ { ++ wait_count++; ++ msleep(3); ++ if(wait_count>10) ++ { ++ break; ++ } ++ } ++ ++ GOPDBG ("[GOP]%s: out \n",__func__); ++} ++ ++void GOP_Setmode( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Hardware Initial ++ // 2. GOP Fetch Framebuffer Information ++ // 3. GOP Display Settings ++ ++ ++ //GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ GOPDBG ("[GOP]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOPDBG ("[GOP]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOPDBG ("[GOP]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOPDBG ("[GOP]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOPDBG ("[GOP]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV);//reset ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT);//set Progress mode; mask Hsync; alpha inverse; YUV output ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE);//close blink ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010);//insert fake rdy between hs & valid rdy ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY); //Hsync input pipe delay ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, GOP_BURST_LENGTH_MASK, GOP_BURST_LENGTH_MAX);// set gop dma burst length ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); //Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); //Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); //Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); //Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); //Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); //Stretch V start value ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN);//set gop format; enable gwin; alpha mode initial ++ ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS;//128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); //H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); //H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart);//V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); //V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Setmode_Stretch_H( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut, int StretchRatio) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Hardware initial ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Set Stretch Ratio for GOP Display ++ ++ ++ //GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ GOPDBG ("[GOP]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOPDBG ("[GOP]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOPDBG ("[GOP]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOPDBG ("[GOP]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOPDBG ("[GOP]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ GOPDBG ("[GOP]%s: FB_StrRatio = [%x]\n",__func__,StretchRatio); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV);//reset ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT);//set Progress mode; mask Hsync; alpha inverse; YUV output ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE);//close blink ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010);//insert fake rdy between hs & valid rdy ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY); //Hsync input pipe delay ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, GOP_BURST_LENGTH_MASK, GOP_BURST_LENGTH_MAX);// set gop dma burst length ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); // Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO/StretchRatio); // Stretch H ratio, val=0x1000/StretchRatio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN);//set gop format; enable gwin; alpha mode initial ++ ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++void GOP_Set_OutFormat(int screen, int byuvoutput) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Change Output Color Format (YUV/RGB) ++ ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ GOPDBG("[GOP]%s: screen:%d, byuvoutput:%d\n",__func__, screen, byuvoutput); ++ ++ if(byuvoutput) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_YUVOUT, GOP_YUVOUT); ++ ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP_YUVOUT); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++} ++ ++ ++ ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set Alpha Blending ++ // 2. bEn= 0:pixel alpha; 1: constant alpha; for register: pixel_alpha=1, constant_alpha=0 ++ // 3. alpha: constant alpha value ++ ++ ++ GOPDBG("[GOP]%s: screen:%d, bEn:%d, alpha:%x\n",__func__, screen, bEn, alpha); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // alpha inv ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : GOP_ALPHA_INV), GOP_ALPHA_INV);//set alpha inverse when pixel alpha ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ // constant or pixel alpha ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? GOP_CONSTANT_ALPHA_EN : GOP_PIXEL_ALPHA_EN), GOP_ALPHA_MASK); ++ ++ // alpha value ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_0A, (bEn ? alpha : 0x0000), 0x00FF);//available for constant alpha; set 0 when pixel alpha ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ ++} ++ ++ ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set RGB Color Key ++ // 2. bEn= 0: disable; 1: enable ++ // 3. u8R: red color value; u8G: green color value; u8B: blue color value ; value range: 0~255 (0x0~0xFF) ++ ++ ++ GOPDBG("[GOP]%s: screen:%d, bEn:%d, (R=%x, G=%x, B=%x)\n",__func__, screen, bEn, u8R, u8G, u8B); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ if(bEn) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_RGB_TRANSPARENT_COLOR_ENABLE, GOP_RGB_TRANSPARENT_COLOR_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_24, (u8B|(u8G<<8))); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_25, u8R, 0x00FF); ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_RGB_TRANSPARENT_COLOR_DISABLE, GOP_RGB_TRANSPARENT_COLOR_MASK); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Set_PipeDelay(int screen, int delay) ++{ ++ U16 pipe_delay = delay; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set Pipe Delay ++ ++ ++ GOPDBG("[GOP]%s: screen:%d, delay:%d\n",__func__, screen, delay); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F, pipe_delay); ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++} ++ ++void GOP_Set_Palette_RIU(int screen, int u8Index, int u8A, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base = 0; ++ ++ // 1. GOP Set Palette by RIU Mode ++ // 2. GOP Palette SRAM Clock should be opened ++ // 3. Set Force Write ++ // 4. Set RIU Mode ++ // 5. Set Palette Index, A, R, G, B Values ++ // 6. Trigger Palette Write ++ // 7. Close Force Write ++ ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ //set force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_BANK_FORCE_WR , GOP_BANK_FORCE_WR); ++ ++ //set RIU mode ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, GOP_PALETTE_SRAM_CTRL_RIU , GOP_PALETTE_SRAM_CTRL_MASK); ++ ++ //set palette value ++ OUTREG16(GOP_Reg_Base+REG_GOP_03, u8G<<8|u8B); ++ OUTREG16(GOP_Reg_Base+REG_GOP_04, u8A<<8|u8R); ++ ++ //set palette index ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, u8Index , GOP_PALETTE_TABLE_ADDRESS_MASK); ++ ++ //write trigger ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0100 , GOP_PALETTE_WRITE_ENABLE_MASK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0000 , GOP_PALETTE_WRITE_ENABLE_MASK); ++ ++ //close force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0x0000 , GOP_BANK_FORCE_WR); ++ ++} ++ ++void GOP_Set_Outputmode(int Screen, int Panel_Width, int Panel_Height,U32 FB_Start_Addr, U32 Pixel_Format, U16 Bytes_Per_Pixel) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Set Output Mode ++ // 2. GOP Fetch Framebuffer Information ++ // 3. GOP Display Settings ++ ++ GOPDBG ("[GOP]%s\n",__func__); ++ GOPDBG ("[GOP]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOPDBG ("[GOP]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOPDBG ("[GOP]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOPDBG ("[GOP]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOPDBG ("[GOP]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, DISPLAY_Format, GWIN_FMT_MASK); ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS;//128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size, use for scroll; useless in I1, I3 ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); //H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); //H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart);//V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); //V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Set_Enable_GWIN(int screen, unsigned char bEn) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ unsigned char enGOP = bEn; ++ unsigned long GOP_Reg_DB = 0x0400; ++ ++ // 1. GOP Set GWIN Enable/Disable ++ ++ GOPDBG( "[GOP]%s: Set enable_GOP = [%d]\n",__func__,enGOP); ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ // enable/disable gwin ++ if(enGOP) ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, enGOP, GOP0_GWin0_Enable); ++ else ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP0_GWin0_Enable); ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP_Get_Enable_GWIN(int screen, unsigned char *bEn) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ ++ // 1. GOP Get GWIN Enable/Disable ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP0_GWin0_Enable)) ++ { ++ *bEn = 1; ++ } ++ else ++ { ++ *bEn = 0; ++ } ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ GOPDBG( "[GOP]%s: Get enable_GOP = [%d]\n",__func__,enGOP); ++ ++} ++ ++void GOP_Get_Alpha(int screen, int *alpha_type, int *alpha_val) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ ++ // 1. GOP Get Alpha Blending ++ // 2. alpha_type= 0:pixel_alpha; 1: constant_alpha; for register: pixel_alpha=1, constant_alpha=0 ++ // 3. alpha_val: constant alpha value ++ ++ // alpha info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ // constant or pixel alpha ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_PIXEL_ALPHA_EN)==GOP_PIXEL_ALPHA_EN) ++ *alpha_type = 0; //pixel_alpha ++ else ++ *alpha_type = 1; //constant_alpha ++ ++ // alpha value ++ *alpha_val = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_0A, 0x00FF); ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ GOPDBG( "[GOP]%s: Alpha_type = [%s], Alpha_value = [%d]\n",__func__,PARSING_ALPHA_TYPE(*alpha_type),*alpha_val); ++ ++} ++ ++void GOP_Get_Color_Key(int screen, int *bEn, int *u8R, int *u8G, int *u8B) ++{ ++ unsigned long GOP_Reg_Base; ++ ++ // 1. GOP Get RGB Color Key ++ // 2. bEn= 0: disable; 1: enable ++ // 3. u8R: red color value; u8G: green color value; u8B: blue color value ; value range: 0~255 (0x0~0xFF) ++ ++ // colorkey setting is in GOP00 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // enable/disable ++ *bEn = (INREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0800)>>11); ++ ++ // colorkey value ++ *u8R = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_25,0x00FF); ++ *u8G = (unsigned char)(INREGMSK16(GOP_Reg_Base+REG_GOP_24,0xFF00)>>8); ++ *u8B = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_24,0x00FF); ++ ++ GOPDBG("[GOP]%s: screen:%d, bEn:%d, (R=%x, G=%x, B=%x)\n",__func__, screen, *bEn, *u8R, *u8G, *u8B); ++ ++} +diff --git a/drivers/mstar/fb/infinity3/gop/mdrv_gop.h b/drivers/mstar/fb/infinity3/gop/mdrv_gop.h +new file mode 100644 +index 00000000..1891b61e +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/gop/mdrv_gop.h +@@ -0,0 +1,204 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_gop.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#include ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#include "gop_c2_reg.h" ++ ++#define GOP_DEBUG 0 ++#if (GOP_DEBUG==1) ++#define GOPDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOPDBG(fmt, arg...) ++#endif ++ ++#define BK_REG(reg) ((reg) * 4) ++ ++/* ---------------------------------------------------------------------------- ++ * GOP_OFFSET ++ * ---------------------------------------------------------------------------- ++ */ ++#define REG_GOP_00 BK_REG(0x00) ++#define REG_GOP_01 BK_REG(0x01) ++#define REG_GOP_02 BK_REG(0x02) ++#define REG_GOP_03 BK_REG(0x03) ++#define REG_GOP_04 BK_REG(0x04) ++#define REG_GOP_05 BK_REG(0x05) ++#define REG_GOP_06 BK_REG(0x06) ++#define REG_GOP_07 BK_REG(0x07) ++#define REG_GOP_08 BK_REG(0x08) ++#define REG_GOP_09 BK_REG(0x09) ++#define REG_GOP_0A BK_REG(0x0A) ++#define REG_GOP_0B BK_REG(0x0B) ++#define REG_GOP_0C BK_REG(0x0C) ++#define REG_GOP_0D BK_REG(0x0D) ++#define REG_GOP_0E BK_REG(0x0E) ++#define REG_GOP_0F BK_REG(0x0F) ++ ++#define REG_GOP_10 BK_REG(0x10) ++#define REG_GOP_11 BK_REG(0x11) ++#define REG_GOP_12 BK_REG(0x12) ++#define REG_GOP_13 BK_REG(0x13) ++#define REG_GOP_14 BK_REG(0x14) ++#define REG_GOP_15 BK_REG(0x15) ++#define REG_GOP_16 BK_REG(0x16) ++#define REG_GOP_17 BK_REG(0x17) ++#define REG_GOP_18 BK_REG(0x18) ++#define REG_GOP_19 BK_REG(0x19) ++#define REG_GOP_1A BK_REG(0x1A) ++#define REG_GOP_1B BK_REG(0x1B) ++#define REG_GOP_1C BK_REG(0x1C) ++#define REG_GOP_1D BK_REG(0x1D) ++#define REG_GOP_1E BK_REG(0x1E) ++#define REG_GOP_1F BK_REG(0x1F) ++ ++#define REG_GOP_20 BK_REG(0x20) ++#define REG_GOP_21 BK_REG(0x21) ++#define REG_GOP_22 BK_REG(0x22) ++#define REG_GOP_23 BK_REG(0x23) ++#define REG_GOP_24 BK_REG(0x24) ++#define REG_GOP_25 BK_REG(0x25) ++#define REG_GOP_26 BK_REG(0x26) ++#define REG_GOP_27 BK_REG(0x27) ++#define REG_GOP_28 BK_REG(0x28) ++#define REG_GOP_29 BK_REG(0x29) ++#define REG_GOP_2A BK_REG(0x2A) ++#define REG_GOP_2B BK_REG(0x2B) ++#define REG_GOP_2C BK_REG(0x2C) ++#define REG_GOP_2D BK_REG(0x2D) ++#define REG_GOP_2E BK_REG(0x2E) ++#define REG_GOP_2F BK_REG(0x2F) ++ ++#define REG_GOP_30 BK_REG(0x30) ++#define REG_GOP_31 BK_REG(0x31) ++#define REG_GOP_32 BK_REG(0x32) ++#define REG_GOP_33 BK_REG(0x33) ++#define REG_GOP_34 BK_REG(0x34) ++#define REG_GOP_35 BK_REG(0x35) ++#define REG_GOP_36 BK_REG(0x36) ++#define REG_GOP_37 BK_REG(0x37) ++#define REG_GOP_38 BK_REG(0x38) ++#define REG_GOP_39 BK_REG(0x39) ++#define REG_GOP_3A BK_REG(0x3A) ++#define REG_GOP_3B BK_REG(0x3B) ++#define REG_GOP_3C BK_REG(0x3C) ++#define REG_GOP_3D BK_REG(0x3D) ++#define REG_GOP_3E BK_REG(0x3E) ++#define REG_GOP_3F BK_REG(0x3F) ++ ++#define REG_GOP_40 BK_REG(0x40) ++#define REG_GOP_41 BK_REG(0x41) ++#define REG_GOP_42 BK_REG(0x42) ++#define REG_GOP_43 BK_REG(0x43) ++#define REG_GOP_44 BK_REG(0x44) ++#define REG_GOP_45 BK_REG(0x45) ++#define REG_GOP_46 BK_REG(0x46) ++#define REG_GOP_47 BK_REG(0x47) ++#define REG_GOP_48 BK_REG(0x48) ++#define REG_GOP_49 BK_REG(0x49) ++#define REG_GOP_4A BK_REG(0x4A) ++#define REG_GOP_4B BK_REG(0x4B) ++#define REG_GOP_4C BK_REG(0x4C) ++#define REG_GOP_4D BK_REG(0x4D) ++#define REG_GOP_4E BK_REG(0x4E) ++#define REG_GOP_4F BK_REG(0x4F) ++ ++#define REG_GOP_50 BK_REG(0x50) ++#define REG_GOP_51 BK_REG(0x51) ++#define REG_GOP_52 BK_REG(0x52) ++#define REG_GOP_53 BK_REG(0x53) ++#define REG_GOP_54 BK_REG(0x54) ++#define REG_GOP_55 BK_REG(0x55) ++#define REG_GOP_56 BK_REG(0x56) ++#define REG_GOP_57 BK_REG(0x57) ++#define REG_GOP_58 BK_REG(0x58) ++#define REG_GOP_59 BK_REG(0x59) ++#define REG_GOP_5A BK_REG(0x5A) ++#define REG_GOP_5B BK_REG(0x5B) ++#define REG_GOP_5C BK_REG(0x5C) ++#define REG_GOP_5D BK_REG(0x5D) ++#define REG_GOP_5E BK_REG(0x5E) ++#define REG_GOP_5F BK_REG(0x5F) ++ ++#define REG_GOP_60 BK_REG(0x60) ++#define REG_GOP_61 BK_REG(0x61) ++#define REG_GOP_62 BK_REG(0x62) ++#define REG_GOP_63 BK_REG(0x63) ++#define REG_GOP_64 BK_REG(0x64) ++#define REG_GOP_65 BK_REG(0x65) ++#define REG_GOP_66 BK_REG(0x66) ++#define REG_GOP_67 BK_REG(0x67) ++#define REG_GOP_68 BK_REG(0x68) ++#define REG_GOP_69 BK_REG(0x69) ++#define REG_GOP_6A BK_REG(0x6A) ++#define REG_GOP_6B BK_REG(0x6B) ++#define REG_GOP_6C BK_REG(0x6C) ++#define REG_GOP_6D BK_REG(0x6D) ++#define REG_GOP_6E BK_REG(0x6E) ++#define REG_GOP_6F BK_REG(0x6F) ++ ++#define REG_GOP_70 BK_REG(0x70) ++#define REG_GOP_71 BK_REG(0x71) ++#define REG_GOP_72 BK_REG(0x72) ++#define REG_GOP_73 BK_REG(0x73) ++#define REG_GOP_74 BK_REG(0x74) ++#define REG_GOP_75 BK_REG(0x75) ++#define REG_GOP_76 BK_REG(0x76) ++#define REG_GOP_77 BK_REG(0x77) ++#define REG_GOP_78 BK_REG(0x78) ++#define REG_GOP_79 BK_REG(0x79) ++#define REG_GOP_7A BK_REG(0x7A) ++#define REG_GOP_7B BK_REG(0x7B) ++#define REG_GOP_7C BK_REG(0x7C) ++#define REG_GOP_7D BK_REG(0x7D) ++#define REG_GOP_7E BK_REG(0x7E) ++#define REG_GOP_7F BK_REG(0x7F) ++ ++//global functions ++void SwitchSubBank(int subbank); ++void GOP_Setmode(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++void GOP_Setmode_Stretch_H(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut, int StretchRatio); ++void GOP_Pan_Display(int Screen, U32 FB_Start_Addr); ++void GOP_Set_OutFormat(int screen, int byuvoutput); ++void GOP_Set_Constant_Alpha(int screen, int bEn, int alpha); ++void GOP_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B); ++void GOP_Set_PipeDelay(int screen, int delay); ++void GOP_Set_Palette_RIU(int screen, int u8Index, int u8A, int u8R, int u8G, int u8B); ++void GOP_Set_Outputmode(int Screen, int Panel_Width, int Panel_Height,U32 FB_Start_Addr, U32 Pixel_Format, U16 Bytes_Per_Pixel); ++void GOP_Set_Enable_GWIN(int screen, unsigned char bEn); ++void GOP_Get_Enable_GWIN(int screen, unsigned char *bEn); ++void GOP_Get_Alpha(int screen, int *alpha_type, int *alpha_val); ++void GOP_Get_Color_Key(int screen, int *bEn, int *u8R, int *u8G, int *u8B); +diff --git a/drivers/mstar/fb/infinity3/inv_color/mdrv_gop0_inv_color.c b/drivers/mstar/fb/infinity3/inv_color/mdrv_gop0_inv_color.c +new file mode 100644 +index 00000000..06874b03 +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/inv_color/mdrv_gop0_inv_color.c +@@ -0,0 +1,371 @@ ++#include "mdrv_gop0_inv_color.h" ++ ++void GOP0_invColor_init(void) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ int output_YUV_mode=0x0002; ++ int complementary_color_mode=0x0008; ++ ++ // 1. GOP Set inverse color init settings ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ ++ // set gop output mode YUV ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BASE_SETTINGS, output_YUV_mode, GOP0_invColor_gop_output_mode); ++ ++ // set inverse color mode to complementary color mode ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BASE_SETTINGS, complementary_color_mode, GOP0_invColor_color_mode); ++ ++} ++ ++void GOP0_invColor_Enable(unsigned char bEn) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ ++ // 1. GOP Set inverse color Enable/Disable ++ ++ GOP0_invColor_DBG( "[GOP0_invColor]%s: Set enable_GOP = [%d]\n",__func__,bEn); ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ ++ // enable/disable inverse color ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BASE_SETTINGS, bEn, GOP0_invColor_enable_mask); ++ ++} ++ ++void GOP0_invColor_Set_UpdateMode(unsigned char bMode) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ ++ // 1. GOP Set inverse color update inverse table mode ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ ++ // set inverse color update mode, 1:by cpu, 0:by engine ++ if(bMode) ++ { ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BASE_SETTINGS, GOP0_invColor_update_mode, GOP0_invColor_update_mode); ++ } ++ else ++ { ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BASE_SETTINGS, 0, GOP0_invColor_update_mode); ++ } ++ ++} ++ ++void GOP0_invColor_Set_Y_Threshold(int AE_Y_Thres) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ ++ // 1. GOP Set Y threshold to do inverse color or not ++ ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: Set Y Threshold = [%d]\n",__func__,AE_Y_Thres); ++ ++ // set AE_Y_Thres ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BASE_SETTINGS, (AE_Y_Thres<<8),GOP0_invColor_AE_Y_Threshold_mask); ++ ++} ++ ++void GOP0_invColor_Set_AE_Config(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ int real_blk_width = AE_Blk_Width; // register setting is real_size-1 ++ int AE_Blk_x_num = 0; ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ AE_Blk_x_num = AE_x_res / real_blk_width; //real x blk num ++ ++ // 1. GOP Set AE config ++ ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: reg AE_Blk_Width = [%d]\n",__func__,AE_Blk_Width-1); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: reg AE_Blk_Height = [%d]\n",__func__,AE_Blk_Height-1); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: reg AE_Blk_x_num = [%d]\n",__func__,AE_Blk_x_num-1); ++ ++ // set AE_Blk_Width ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BLK_WIDTH, AE_Blk_Width-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_Height ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BLK_HEIGHT, AE_Blk_Height-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_x_num ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_AE_X_BLK_NUM, (AE_Blk_x_num-1)<<8,GOP0_invColor_AE_X_BLK_NUM_mask); // reg_val=real_size-1 ++ ++} ++ ++void GOP0_invColor_Set_AE_Config_Scaling(int AE_Blk_Width, int AE_Blk_Height, int AE_x_blk_num) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ ++ // 1. GOP Set AE config ++ ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: reg AE_Blk_Width = [%d]\n",__func__,AE_Blk_Width-1); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: reg AE_Blk_Height = [%d]\n",__func__,AE_Blk_Height-1); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: reg AE_x_blk_num = [%d]\n",__func__,AE_x_blk_num-1); ++ ++ // set AE_Blk_Width ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BLK_WIDTH, AE_Blk_Width-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_Height ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BLK_HEIGHT, AE_Blk_Height-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_x_num ++ OUTREGMSK16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_AE_X_BLK_NUM, (AE_x_blk_num-1)<<8,GOP0_invColor_AE_X_BLK_NUM_mask); // reg_val=real_size-1 ++ ++} ++ ++ ++void GOP0_invColor_Set_Crop_Config(int crop_x_cor, int crop_y_cor, int AE_Blk_Width, int AE_Blk_Height, int AE_x_res) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ int real_blk_width = AE_Blk_Width+1; // register setting is real_size-1 ++ int real_blk_height = AE_Blk_Height+1;// register setting is real_size-1 ++ int x_offset=0; ++ int y_offset=0; ++ int invTable_idx_offset=0; ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ // x_offset = crop_x_offset % ae_blk_w ++ x_offset = crop_x_cor % real_blk_width; ++ // y_offset = crop_y_offset % ae_blk_h ++ y_offset = crop_y_cor % real_blk_height; ++ // index offset = floor(crop_y_offset / ae_blk_h) x (reg_blk_num_x_m1+1) + floor (crop_x_offset / ae_blk_w) ++ invTable_idx_offset= (crop_y_cor / real_blk_height)*(AE_x_res / real_blk_width)+(crop_x_cor / real_blk_width); ++ ++ // 1. GOP Set crop config: x_offset, y_offset & index_offset ++ ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: x_offset = [%d]\n",__func__,x_offset); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: y_offset = [%d]\n",__func__,y_offset); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: idx_offset = [%d]\n",__func__,invTable_idx_offset); ++ ++ // set x_offset ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_X_PIX_OFFSET, x_offset); ++ ++ // set y_offset ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_Y_PIX_OFFSET, y_offset); ++ ++ // set invTable_idx_offset ++ OUTREG16(GOP0_invColor_Reg_Base+GOP0_invColor_REG_BLK_INDEX_OFFSET, invTable_idx_offset); ++ ++} ++ ++int GOP0_invColor_Engine_Update_Done(void) ++{ ++ unsigned long GOP0_invColor_Reg_Update = 0; ++ unsigned char bDone=0; ++ ++ GOP0_invColor_Reg_Update=mdrv_BASE_REG_GOP0_invColor_AE_Update_Done; ++ ++ if(INREGMSK16(GOP0_invColor_Reg_Update+GOP0_invColor_REG_AE_Update_Done, GOP0_invColor_AE_Update_Done_mask)!=0) ++ { ++ bDone=1; ++ //if get ready, clear it after read ++ OUTREGMSK16(GOP0_invColor_Reg_Update+GOP0_invColor_REG_AE_Update_Done, 0 , GOP0_invColor_AE_Update_Done_mask); ++ } ++ else ++ { ++ bDone=0; ++ } ++ ++ return bDone; ++} ++ ++int GOP0_invColor_CPU_Upate_InvTable(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res, int AE_y_res) ++{ ++ unsigned long GOP0_invColor_Reg_Base = 0; ++ unsigned char *invTable; ++ unsigned char *invTable_rot; ++ int retry_count=0; ++ int blk_origin_num_x=0; ++ int blk_origin_num_y=0; ++ int total_index_used=0; ++ int reg_index_used=0; ++ int num_invTbl_per_regidx=32; ++ int temp_idx=0; ++ int temp_count=0; ++ int temp_data1=0; ++ int temp_data2=0; ++ int temp_x_idx=0; ++ int temp_y_idx=0; ++ ++ ++ GOP0_invColor_Reg_Base = mdrv_BASE_REG_GOP0_invColor; ++ ++ // 1. Count Needed Settings ++ ++ blk_origin_num_x = AE_x_res / AE_Blk_Width; ++ blk_origin_num_y = AE_y_res / AE_Blk_Height; ++ if((blk_origin_num_x>128)||(blk_origin_num_y>90)) ++ { ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: Error! blk_num too big!!! x_num=%d, y_num=%d\n",__func__,blk_origin_num_x,blk_origin_num_y); ++ return FALSE; ++ } ++ total_index_used = blk_origin_num_x * blk_origin_num_y; ++ reg_index_used = total_index_used / num_invTbl_per_regidx; ++ if((total_index_used % num_invTbl_per_regidx)!=0)// if total_index in use is not 32 align, then reg_idx +1 ++ { ++ reg_index_used++; ++ } ++ ++ //assign memory ++ invTable=kmalloc((reg_index_used*num_invTbl_per_regidx) * sizeof(unsigned char),GFP_KERNEL); ++ if (!invTable) ++ { ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: Error! kmalloc error\n",__func__); ++ return FALSE; ++ } ++ invTable_rot=kmalloc((reg_index_used*num_invTbl_per_regidx) * sizeof(unsigned char),GFP_KERNEL); ++ if (!invTable_rot) ++ { ++ kfree(invTable); ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: Error! kmalloc error\n",__func__); ++ return FALSE; ++ } ++ ++ ++ // 2. Wait Inverse HW Engine write AE Inverse Table Done with Interrupt Trigger and then clean Interrupt ++ ++ while(!GOP0_invColor_Engine_Update_Done()) ++ { ++ mdelay(30); ++ if(retry_count>10) ++ { ++ GOP0_invColor_DBG ("[GOP0_invColor]%s: Error! wait no ack\n",__func__); ++ return FALSE; ++ } ++ retry_count++; ++ } ++ ++ ++ // 3. Read Inverse Table ++ ++ for(temp_idx=0;temp_idx>temp_count)& 0x1); ++ } ++ for(temp_count=0;temp_count<16;temp_count++) ++ { ++ invTable[(temp_idx * num_invTbl_per_regidx)+temp_count+16]= ((temp_data2>>temp_count)& 0x1); ++ } ++ } ++ ++ // 4. Do Transpose for Rotate Case ++ ++ for(temp_y_idx=0;temp_y_idx ++#include ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#define GET_REG8_ADDR_GOP0_invColor(x, y) (x+(y)*2) ++#define GET_REG16_ADDR_GOP0_invColor(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define BASE_REG_RIU_PA_GOP0_invColor (0x1F000000) ++ ++//GOP Base register defines ++ ++//inverse color base address ++#define mdrv_BASE_REG_GOP0_invColor GET_REG16_ADDR_GOP0_invColor(BASE_REG_RIU_PA_GOP0_invColor, (0x121A00/2)) ++ ++//inverse color engine update done flag address ++#define mdrv_BASE_REG_GOP0_invColor_AE_Update_Done GET_REG16_ADDR_GOP0_invColor(BASE_REG_RIU_PA_GOP0_invColor, (0x121800/2)) ++#define GOP0_invColor_REG_AE_Update_Done BK_REG_GOP0_invColor(0x0A) ++#define GOP0_invColor_AE_Update_Done_mask 0x0040 ++ ++#define BK_REG_GOP0_invColor(reg) ((reg) * 4) ++ ++//-------------------------------------------------------------------------------------------------- ++// Defines ++//-------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------ ++// inverse color settings for GOP0 ++//------------------------------------------------------------------------------ ++ ++#define GOP0_invColor_REG_BASE_SETTINGS BK_REG_GOP0_invColor(0x31) ++#define GOP0_invColor_enable_mask 0x0001 // 1:enable, 0:disable ++#define GOP0_invColor_gop_output_mode 0x0002 // 1:YUV, 0:RGB ++#define GOP0_invColor_update_mode 0x0004 // 1:by cpu, 0:by engine ++#define GOP0_invColor_color_mode 0x0008 // 1.complementary color, 0:user define ++#define GOP0_invColor_AE_Y_Threshold_mask 0xFF00 ++ ++#define GOP0_invColor_REG_USER_COLOR_RG BK_REG_GOP0_invColor(0x32) ++#define GOP0_invColor_user_color_R_mask 0x00FF ++#define GOP0_invColor_user_color_G_mask 0xFF00 ++ ++#define GOP0_invColor_REG_USER_COLOR_B BK_REG_GOP0_invColor(0x33) ++#define GOP0_invColor_user_color_B_mask 0x00FF ++ ++#define GOP0_invColor_REG_AE_X_BLK_NUM BK_REG_GOP0_invColor(0x33) ++#define GOP0_invColor_AE_X_BLK_NUM_mask 0x7F00 ++ ++#define GOP0_invColor_REG_X_PIX_OFFSET BK_REG_GOP0_invColor(0x34) ++ ++#define GOP0_invColor_REG_Y_PIX_OFFSET BK_REG_GOP0_invColor(0x35) ++ ++#define GOP0_invColor_REG_BLK_INDEX_OFFSET BK_REG_GOP0_invColor(0x36) ++ ++#define GOP0_invColor_REG_BLK_WIDTH BK_REG_GOP0_invColor(0x37) ++ ++#define GOP0_invColor_REG_BLK_HEIGHT BK_REG_GOP0_invColor(0x38) ++ ++#define GOP0_invColor_REG_SRAM_SETTINGS BK_REG_GOP0_invColor(0x39) ++#define GOP0_invColor_SRAM_ADDR_mask 0x01FF ++#define GOP0_invColor_SRAM_WRITE_enable 0x0200 ++#define GOP0_invColor_SRAM_READ_enable 0x0400 ++#define GOP0_invColor_SRAM_CPU_UPDATE_DONE 0x0800 ++ ++#define GOP0_invColor_REG_SRAM_WRITE_DATA1 BK_REG_GOP0_invColor(0x3A) ++ ++#define GOP0_invColor_REG_SRAM_WRITE_DATA2 BK_REG_GOP0_invColor(0x3B) ++ ++#define GOP0_invColor_REG_SRAM_READ_DATA1 BK_REG_GOP0_invColor(0x3C) ++ ++#define GOP0_invColor_REG_SRAM_READ_DATA2 BK_REG_GOP0_invColor(0x3D) ++ ++ ++#define GOP0_invColor_DEBUG 0 ++#if (GOP0_invColor_DEBUG==1) ++#define GOP0_invColor_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOP0_invColor_DBG(fmt, arg...) ++#endif ++ ++//global functions ++void GOP0_invColor_init(void); ++void GOP0_invColor_Enable(unsigned char bEn); ++void GOP0_invColor_Set_UpdateMode(unsigned char bMode); ++void GOP0_invColor_Set_Y_Threshold(int AE_Y_Thres); ++void GOP0_invColor_Set_AE_Config(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res); ++void GOP0_invColor_Set_AE_Config_Scaling(int AE_Blk_Width, int AE_Blk_Height, int AE_x_blk_num); ++void GOP0_invColor_Set_Crop_Config(int crop_x_cor, int crop_y_cor, int AE_Blk_Width, int AE_Blk_Height, int AE_x_res); ++int GOP0_invColor_CPU_Upate_InvTable(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res, int AE_y_res); ++void GOP0_invColor_Debug_Mode(void); ++void GOP0_invColor_DebugMode_UpdateInvTable(void); +diff --git a/drivers/mstar/fb/infinity3/mdrv_fb.c b/drivers/mstar/fb/infinity3/mdrv_fb.c +new file mode 100644 +index 00000000..e0c8a2f9 +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/mdrv_fb.c +@@ -0,0 +1,2036 @@ ++ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_general_fb.c ++ * DESCRIPTION For mdrv LinuxBSP Display driver, use frame buffer ++ * architecture ++ * ++ * AUTHOR Chun Fan ++ * ++ * ++ * HISTORY 2008/05/06 initial version ++ * linux/drivers/video/mdrv_general_fb.c ++ * -- mdrv frame buffer device ++ *****************************************************************************/ ++ ++ ++#define mdrv_GEN_FB_C ++ ++#include "mdrv_fb.h" ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++// update global variables while init/probe ++static void __init mdrvinfinityfb_updateinfo(void) ++{ ++ static int main_videomemory_size=0; ++ ++ //default settings for Stretch mode ++ genGOPGernelSettings.u32Width=sg_mdrvinfinityfb_default_var.xres; ++ genGOPGernelSettings.u32Height=sg_mdrvinfinityfb_default_var.yres; ++ genGOPGernelSettings.enBufferNum=FB_DOUBLE_BUFFER; ++ genGOPGernelSettings.enStretchH_Ratio=FB_STRETCH_H_RATIO_1; ++ genGOPGernelSettings.u32DisplayWidth=genGOPGernelSettings.u32Width*genGOPGernelSettings.enStretchH_Ratio; ++ genGOPGernelSettings.u32DisplayHeight=genGOPGernelSettings.u32Height; ++ ++ //default settings for global structure of fb_var_screeninfo ++ sg_mdrvinfinityfb_default_var.xres = 0; ++ sg_mdrvinfinityfb_default_var.yres = 0; ++ sg_mdrvinfinityfb_default_var.xres_virtual = sg_mdrvinfinityfb_default_var.xres; ++ sg_mdrvinfinityfb_default_var.yres_virtual = sg_mdrvinfinityfb_default_var.yres * (genGOPGernelSettings.enBufferNum);//double buffer for pan display ++ sg_mdrvinfinityfb_default_var.width = sg_mdrvinfinityfb_default_var.xres; ++ sg_mdrvinfinityfb_default_var.height = sg_mdrvinfinityfb_default_var.yres; ++ ++ //GWin init, same size as screen ++ genGWinInfo.u18HStart = 0; ++ genGWinInfo.u18HEnd = genGWinInfo.u18HStart + sg_mdrvinfinityfb_default_var.xres; ++ genGWinInfo.u18VStart = 0; ++ genGWinInfo.u18VEnd = genGWinInfo.u18VStart + sg_mdrvinfinityfb_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb_default_var.xres * sg_mdrvinfinityfb_default_var.yres * ANDROID_BYTES_PER_PIXEL * (genGOPGernelSettings.enBufferNum)); ++ ++ ++ sg_videomemorysize = main_videomemory_size; ++ ++ //default settings for global structure of fb_fix_screeninfo ++ sg_mdrvinfinityfb_fix.smem_start = sg_G3D_fb2_bus_addr1; ++ sg_mdrvinfinityfb_fix.smem_len = sg_videomemorysize; ++ sg_mdrvinfinityfb_fix.line_length = sg_mdrvinfinityfb_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ sg_mdrvinfinityfb_fix.ypanstep = 1; ++ ++ FBDBGMORE("[FB Driver] updateinfo: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], GOPmemorysize = 0x%x \r\n",sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,(unsigned int)sg_videomemorysize); ++ ++} ++ ++// update global variables while setting new resolution by ioctl FBIOPUT_VSCREENINFO ++static int mdrvinfinityfb_infinity_updateinfo_par(unsigned int setWidth,unsigned int setHeight) ++{ ++ ++ static int main_videomemory_size=0; ++ ++ //update settings for global structure of fb_var_screeninfo ++ sg_mdrvinfinityfb_default_var.xres = setWidth; ++ sg_mdrvinfinityfb_default_var.yres = setHeight; ++ sg_mdrvinfinityfb_default_var.xres_virtual = sg_mdrvinfinityfb_default_var.xres; ++ sg_mdrvinfinityfb_default_var.yres_virtual = sg_mdrvinfinityfb_default_var.yres * (genGOPGernelSettings.enBufferNum);//double buffer for pan display ++ sg_mdrvinfinityfb_default_var.width = sg_mdrvinfinityfb_default_var.xres; ++ sg_mdrvinfinityfb_default_var.height = sg_mdrvinfinityfb_default_var.yres; ++ ++ //update settings for global structure of Stetch mode ++ genGOPGernelSettings.u32Width=sg_mdrvinfinityfb_default_var.xres; ++ genGOPGernelSettings.u32Height=sg_mdrvinfinityfb_default_var.yres; ++ genGOPGernelSettings.u32DisplayWidth=genGOPGernelSettings.u32Width*genGOPGernelSettings.enStretchH_Ratio; ++ genGOPGernelSettings.u32DisplayHeight=genGOPGernelSettings.u32Height; ++ ++ //GWin init, same size as screen ++ genGWinInfo.u18HStart = 0; ++ genGWinInfo.u18HEnd = genGWinInfo.u18HStart + sg_mdrvinfinityfb_default_var.xres; ++ genGWinInfo.u18VStart = 0; ++ genGWinInfo.u18VEnd = genGWinInfo.u18VStart + sg_mdrvinfinityfb_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb_default_var.xres * sg_mdrvinfinityfb_default_var.yres * ANDROID_BYTES_PER_PIXEL * (genGOPGernelSettings.enBufferNum)); ++ ++ // free memory if it has ++ if(sg_videomemorysize > 0) ++ { ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ } ++ ++ sg_videomemorysize = main_videomemory_size; ++ ++ FBDBG ("[FB Driver] updateinfo_par: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], GOPmemorysize = 0x%x \r\n",sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,(unsigned int)sg_videomemorysize); ++ ++ // allocate new memory ++ if (!(sg_pG3D_fb2_vir_addr1 = alloc_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ &sg_G3D_fb2_bus_addr1))) ++ { ++ FBDBGERR("[FB Driver] Error: updateinfo_par: unable to allocate screen memory\n"); ++ return -ENOMEM; ++ } ++ ++ // prevent initial garbage on screen ; to clean memory ++ memset(CAST_2_IOMEM_CHAR_P sg_pG3D_fb2_vir_addr1,0, sg_videomemorysize); ++ ++ //update settings for global structure of fb_fix_screeninfo ++ sg_mdrvinfinityfb_fix.smem_start = sg_G3D_fb2_bus_addr1; ++ sg_mdrvinfinityfb_fix.smem_len = sg_videomemorysize; ++ sg_mdrvinfinityfb_fix.line_length = sg_mdrvinfinityfb_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ FBDBG("[FB Driver] vir=0x%x, phy=0x%x\n", (unsigned int)sg_pG3D_fb2_vir_addr1, sg_G3D_fb2_bus_addr1); ++ ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb_infinity_SetPalette(FB_GOP_PaletteEntry *pPalEntry, int intPalStart,int intPalEnd) ++{ ++ int i = 0; ++ int ret = -1; ++ ++ //open scl0 fclk to load palette ++ if (IS_ERR(gop_clks[1])) ++ { ++ FBDBGERR( "[FB Driver] Error: SetPalette Fail to get gop fclk of scl!\n" ); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_clks[1]); ++ } ++ ++ FBDBGMORE("Palette value:(B,G,R,A)\n"); ++ ++ //write palette ++ for(i=intPalStart;i<=intPalEnd;i++) ++ { ++ GOP_Set_Palette_RIU(0, i, pPalEntry[i].BGRA.u8A, pPalEntry[i].BGRA.u8R, pPalEntry[i].BGRA.u8G, pPalEntry[i].BGRA.u8B); ++ ++ //record in global variable ++ stGOPCurrentPalInfo[i].BGRA.u8B=pPalEntry[i].BGRA.u8B; ++ stGOPCurrentPalInfo[i].BGRA.u8G=pPalEntry[i].BGRA.u8G; ++ stGOPCurrentPalInfo[i].BGRA.u8R=pPalEntry[i].BGRA.u8R; ++ stGOPCurrentPalInfo[i].BGRA.u8A=pPalEntry[i].BGRA.u8A; ++ FBDBGMORE("(%d,%d,%d,%d)\n",stGOPCurrentPalInfo[i].BGRA.u8B,stGOPCurrentPalInfo[i].BGRA.u8G,stGOPCurrentPalInfo[i].BGRA.u8R,stGOPCurrentPalInfo[i].BGRA.u8A); ++ } ++ ++ //close clk ++ clk_disable_unprepare(gop_clks[1]); ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb_set_par(struct fb_info *info) ++{ ++ int ret = 0; ++ FBDBG( "[FB Driver] Test I3!\n" ); ++ ++ //Stretch mode settings, if use back to this to set resolution, it will set to default ++ genGOPGernelSettings.enStretchH_Ratio=FB_STRETCH_H_RATIO_1; ++ genGOPGernelSettings.enBufferNum=FB_DOUBLE_BUFFER; ++ ++ ret=mdrvinfinityfb_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start = sg_mdrvinfinityfb_fix.smem_start; ++ info->fix.smem_len = sg_mdrvinfinityfb_fix.smem_len; ++ ++ info->var.width = info->var.xres; ++ info->var.height = info->var.yres; ++ ++ info->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ //GOP_Setmode(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ GOP_Set_Outputmode(0, sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL); ++ ++ return ret; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_mmap +++------------------------------------------------------------------------------ ++| DESCRIPTION : memory map function, Let user application can get virtual ++| address to access in user space. need pass in physical address ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| vma | x | x | we use Remap-pfn-range will mark the range VM_IO ++| | | | and VM_RESERVED, and save these information in ++| | | | vma +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb_mmap(struct fb_info *pinfo, struct vm_area_struct *vma) ++{ ++ size_t size; ++ size = 0; ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: mmap, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if (NULL == pinfo) ++ { ++ FBDBGERR("[FB Driver] ERROR: mmap, pinfo is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ if (NULL == vma) ++ { ++ FBDBGERR("[FB Driver] ERROR: mmap, vma is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_pgoff += ((sg_G3D_fb2_bus_addr1 ) >> PAGE_SHIFT); ++ ++ FBDBG( ++ "[FB Driver] mmap vma->vm_start=%x\n vma->vm_end=%x\n vma->vm_pgoff =%x\n", ++ (unsigned int) vma->vm_start, (unsigned int)vma->vm_end , ++ (unsigned int)vma->vm_pgoff); ++ ++ //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ return 0; ++} ++ ++//sw update inverse color's inverse table thread when rotate case happens ++static int mdrvinfinityfb_SWupdate_InvTable(void *arg) ++{ ++ int ret=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ ++ ret=GOP0_invColor_CPU_Upate_InvTable(genAE_info.u32AEBlkWidth, ++ genAE_info.u32AEBlkHeight, ++ genAE_info.u32AEDisplayWidth, ++ genAE_info.u32AEDisplayHeight); ++ if(!ret)//if update wrong, break ++ { ++ FBDBGERR("[FB Driver] ERROR: mdrvinfinityfb_SWupdate_InvTable wrong!\n"); ++ genTreadisError=1; ++ break; ++ } ++ ++ ++ } ++ ++ return 0; ++ ++} ++ ++static int mdrvinfinityfb_SWupdate_InvTable_debugmode(void *arg) ++{ ++ ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ ++ GOP0_invColor_DebugMode_UpdateInvTable(); ++ msleep(1000); ++ } ++ ++ return 0; ++ ++} ++ ++ ++//check whether need doing sw update inverse color's inverse table or not ++static void mdrvinfinityfb_checkInvTable_UpdateMode(void) ++{ ++ int idx=0; ++ int ret; ++ ++ if((genInv_Color==1) && (genSC_info.bRotateEn==1)) ++ { ++ idx=1; ++ } ++ else ++ { ++ idx=0; ++ } ++ ++ if(genTreadisError==1) ++ { ++ pSWupdateInvThread=NULL; ++ genTreadisError=0; ++ } ++ ++ if(idx==1)//enable thread ++ { ++ if(pSWupdateInvThread==NULL) ++ { ++ pSWupdateInvThread = kthread_create(mdrvinfinityfb_SWupdate_InvTable,(void *)&pSWupdateInvThread,"GOP0_SWupdate_InvColor"); ++ if (IS_ERR(pSWupdateInvThread)) ++ { ++ ret = PTR_ERR(pSWupdateInvThread); ++ pSWupdateInvThread = NULL; ++ FBDBGERR("[FB Driver] ERROR: mdrvinfinityfb_checkInvTable_UpdateMode wrong! Create thread fail! ret=%d\n",ret); ++ } ++ else ++ { ++ wake_up_process(pSWupdateInvThread); ++ } ++ ++ } ++ } ++ else if (idx==0 && (pSWupdateInvThread!=NULL))//disable thread ++ { ++ kthread_stop(pSWupdateInvThread); ++ pSWupdateInvThread = NULL; ++ } ++ ++} ++ ++//sw patch for inverse color hw error ++static int mdrvinfinityfb_InverseColor_RefineBlkHeightMode(int u32ScalerWidth, int u32BlkHeight) ++{ ++ if((u32ScalerWidth<=1040)&&(u32ScalerWidth>=976)) ++ { ++ u32BlkHeight=u32BlkHeight*2; ++ } ++ else if((u32ScalerWidth<=960)&&(u32ScalerWidth>=912)) ++ { ++ u32BlkHeight=u32BlkHeight*3; ++ } ++ else if((u32ScalerWidth<=896)&&(u32ScalerWidth>=480)) ++ { ++ u32BlkHeight=u32BlkHeight*2; ++ } ++ else if((u32ScalerWidth<=464)&&(u32ScalerWidth>=400)) ++ { ++ u32BlkHeight=u32BlkHeight*3; ++ } ++ else if((u32ScalerWidth<=384)&&(u32ScalerWidth>=272)) ++ { ++ u32BlkHeight=u32BlkHeight*4; ++ } ++ else if(u32ScalerWidth==256) ++ { ++ u32BlkHeight=u32BlkHeight*8; ++ } ++ ++ return u32BlkHeight; ++} ++ ++ ++// FB Ioctl Functions ++ ++int _MDrv_FBIO_IOC_Get_SUPINFO(unsigned long arg) ++{ ++ FB_GOP_SUPINF_CONFIG stCfg; ++ ++ // enable gwin is in GOP01 ++ ++ stCfg.bKeyAlpha = 1; ++ stCfg.bConstAlpha = 1; ++ stCfg.bPixelAlpha = 1; ++ stCfg.bColFmt[COLORFMT_ARGB8888] = 0; ++ stCfg.bColFmt[COLORFMT_RGB565] = 0; ++ stCfg.bColFmt[COLORFMT_YUV422] = 0; ++ stCfg.bColFmt[COLORFMT_I8PALETTE]= 1; ++ stCfg.u32MaxWidth = 1920; ++ stCfg.u32MaxHeight= 1080; ++ ++ if(copy_to_user((FB_GOP_SUPINF_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_SUPINF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_GWIN(unsigned long arg) ++{ ++ FB_GOP_GWIN_CONFIG stCfg; ++ ++ stCfg.u18HStart = genGWinInfo.u18HStart; ++ stCfg.u18HEnd = genGWinInfo.u18HEnd; ++ stCfg.u18VStart = genGWinInfo.u18VStart; ++ stCfg.u18VEnd = genGWinInfo.u18VEnd; ++ ++ if(copy_to_user((FB_GOP_GWIN_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_GWIN(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ FB_GOP_GWIN_CONFIG stCfg; ++ unsigned short MIU_BUS = 0x04; ++ unsigned short u16FrameBuffer_Bytes_Per_Pixel = ANDROID_BYTES_PER_PIXEL; ++ unsigned long u32TempVal = 0; ++ unsigned long GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G0; ++ int Panel_Width = 0; ++ int Panel_Height = 0; ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_GWIN, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&stCfg, (FB_GOP_GWIN_CONFIG __user *)arg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ Panel_Width = (int)(stCfg.u18HEnd-stCfg.u18HStart+1); ++ Panel_Height = (int)(stCfg.u18VEnd-stCfg.u18VStart+1); ++ ++ /// GOP0_0 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP00_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ ++ // gwin info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP01_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(1); ++ } ++ ++ genGWinInfo.u18HStart = stCfg.u18HStart; ++ genGWinInfo.u18HEnd = stCfg.u18HEnd; ++ genGWinInfo.u18VStart = stCfg.u18VStart; ++ genGWinInfo.u18VEnd = stCfg.u18VEnd; ++ ++ // GOP Display Setting, GWIN ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(genGWinInfo.u18HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(genGWinInfo.u18HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,genGWinInfo.u18VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,genGWinInfo.u18VEnd); // V end line ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP01_PA==mdrv_BASE_REG_GOP00_PA) ++ { ++ SwitchSubBank(0); ++ } ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_EnGOP(unsigned long arg) ++{ ++ unsigned char enGOP; ++ ++ GOP_Get_Enable_GWIN(0, &enGOP); ++ ++ //remove check scaler's switch later in I3 ++ if(enGOP && INREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0001)) ++ enGOP=1; ++ else ++ enGOP=0; ++ ++ if(copy_to_user((unsigned char __user *)arg, &enGOP, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnGOP(unsigned long arg) ++{ ++ unsigned char enGOP; ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_EnGOP, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&enGOP, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] enable GOP=%d \n",enGOP); ++ ++ // record in global variable ++ genGWIN=enGOP; ++ ++ // this switch will let scaler handle, remove later in I3 ++ // enable/disable gop switch at scaler ++ if(enGOP) ++ OUTREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0001,0x0001); ++ else ++ OUTREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_60,0x0000,0x0001); ++ ++ GOP_Set_Enable_GWIN(0,enGOP); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_Alpha(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ int alpha_type = 0; ++ int alpha_value = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // get alpha blending settings from register ++ GOP_Get_Alpha(0,&alpha_type,&alpha_value); ++ ++ // copy result from register ++ stCfg.bEn = genGOPALPHA.bEn; ++ stCfg.enAlphaType = (FB_GOP_ALPHA_TYPE)alpha_type; ++ stCfg.u8Alpha = (unsigned char)alpha_value; ++ ++ // record settings in global variables ++ genGOPALPHA.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA.u8Alpha=stCfg.u8Alpha; ++ ++ if(copy_to_user((FB_GOP_ALPHA_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Constant_Alpha(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_Constant_Alpha, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Set alpha enable=%d, type=%d, constant alpha value=0x%x \n",(int)stCfg.bEn, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ ++ if(stCfg.bEn) ++ { ++ GOP_Set_Constant_Alpha(0, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ } ++ else ++ { ++ GOP_Set_Constant_Alpha(0, CONST_ALPHA, 0);//close alpha blending, let gop always shows ++ } ++ ++ genGOPALPHA.bEn=stCfg.bEn; ++ genGOPALPHA.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA.u8Alpha=stCfg.u8Alpha; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_Color_Key(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ int Enable = 0; ++ int Red = 0; ++ int Green = 0; ++ int Blue = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP_Get_Color_Key(0,&Enable,&Red,&Green,&Blue); ++ ++ // enable/disable ++ stCfg.bEn = (unsigned char)Enable; ++ ++ // colorkey value ++ stCfg.u8R = (unsigned char)Red; ++ stCfg.u8G = (unsigned char)Green; ++ stCfg.u8B = (unsigned char)Blue; ++ ++ genGOPCOLORKEY.bEn=stCfg.bEn; ++ genGOPCOLORKEY.u8R=stCfg.u8R; ++ genGOPCOLORKEY.u8G=stCfg.u8G; ++ genGOPCOLORKEY.u8B=stCfg.u8B; ++ ++ if(copy_to_user((FB_GOP_COLORKEY_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Color_Key(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_Color_Key, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Set ColorKey enable=%d, R=0x%x, G=0x%x, B=0x%x\n", (int)stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ GOP_Set_Color_Key(0, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ genGOPCOLORKEY.bEn=stCfg.bEn; ++ genGOPCOLORKEY.u8R=stCfg.u8R; ++ genGOPCOLORKEY.u8G=stCfg.u8G; ++ genGOPCOLORKEY.u8B=stCfg.u8B; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_imageblit(struct fb_info *info,unsigned long arg) ++{ ++ int ret = 0; ++ ++// this ioctl is unused, the same fuction can be accessed by fb_ops -> fb_imageblit ++#if 0 ++ struct fb_image stCfg; ++ int i = 0; ++ ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: _MDrv_FBIO_IOC_imageblit, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&stCfg, (struct fb_image __user *)arg, sizeof(const struct fb_image))) ++ { ++ return -EFAULT; ++ } ++ ++ if (NULL == stCfg.data) ++ { ++ FBDBGERR("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, fb_image.data is NULL pointer\r\n"); ++ return -EFAULT; ++ } ++ ++ ++ if (stCfg.fg_color>255) ++ { ++ FBDBGERR("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.bg_color>255) ++ { ++ FBDBGERR("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.width>1920) ++ { ++ FBDBGERR("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ if (stCfg.height>1920) ++ { ++ FBDBGERR("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR ) ++ { ++ for(i=0;i<(stCfg.width*stCfg.height);i++) ++ { ++ if(stCfg.data[i]>255) ++ { ++ ret = 1; ++ } ++ } ++ if(ret) ++ { ++ FBDBGERR("[FB Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ } ++ ++ ++ FBDBGMORE( "[FB Driver] Imgblit test, dst (x,y)=(%d,%d), width=%d, height=%d, colordepth=%d \n" ,stCfg.dx,stCfg.dy,stCfg.width,stCfg.height,stCfg.depth); ++ ++ sys_imageblit(info,&stCfg); ++#endif ++ ++ return ret; ++} ++ ++int _MDrv_FBIO_IOC_Set_Palette(unsigned long arg) ++{ ++ FB_GOP_PaletteEntry stCfg[256]; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_PaletteEntry __user *)arg, sizeof(FB_GOP_PaletteEntry)*256)) ++ { ++ return -EFAULT; ++ } ++ ++ mdrvinfinityfb_infinity_SetPalette(stCfg,0,255); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_General_Config(unsigned long arg) ++{ ++ FB_GOP_RESOLUTION_STRETCH_H_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ stCfg.u32Height = genGOPGernelSettings.u32Height; ++ stCfg.u32Width = genGOPGernelSettings.u32Width; ++ stCfg.enBufferNum = genGOPGernelSettings.enBufferNum; ++ stCfg.u32DisplayHeight = genGOPGernelSettings.u32DisplayHeight; ++ stCfg.u32DisplayWidth = genGOPGernelSettings.u32DisplayWidth; ++ stCfg.enStretchH_Ratio = genGOPGernelSettings.enStretchH_Ratio; ++ ++ if(copy_to_user((FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_General_Config(struct fb_info *info,unsigned long arg) ++{ ++ FB_GOP_RESOLUTION_STRETCH_H_CONFIG stCfg; ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ int max_x_res=2560; ++ int max_y_res=2048; ++ int ret = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] Set General_Config GOP_Width=%d, GOP_Height=%d, Display_Width=%d, Display_Height=%d, Buffer Num=%d, Stretch Ratio=%d\n",(int)stCfg.u32Width,(int)stCfg.u32Height,(int)stCfg.u32DisplayWidth,(int)stCfg.u32DisplayHeight,(int)stCfg.enBufferNum,(int)stCfg.enStretchH_Ratio); ++ ++ ///check variable valid/invalid ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //single/double buffer check ++ if((stCfg.enBufferNum!=FB_SINGLE_BUFFER)&&(stCfg.enBufferNum!=FB_DOUBLE_BUFFER)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: buffer num should be 1 or 2 !\n "); ++ return -EINVAL; ++ } ++ //stretch ratio check ++ if((stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_1)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_2)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_4)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_8)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: stretch H ratio should be 1, 2, 4 or 8 !\n "); ++ return -EINVAL; ++ } ++ //x & y should > 0 ++ if((stCfg.u32Height<1)||(stCfg.u32Width<1)||(stCfg.u32DisplayHeight<1)||(stCfg.u32DisplayWidth<1)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ //x & y should < 1920 ++ if((stCfg.u32Height>1920)||(stCfg.u32Width>1920)||(stCfg.u32DisplayHeight>1920)||(stCfg.u32DisplayWidth>1920)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: buffer x or y size should be < 1920 !\n "); ++ return -EINVAL; ++ } ++ //max size for display is 1920*1088 ++ if(((stCfg.u32Height * stCfg.u32Width)>(max_x_res*max_y_res))||((stCfg.u32DisplayHeight* stCfg.u32DisplayWidth)>(max_x_res*max_y_res))) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ //miu alignment ++ if(((stCfg.u32Width % DisplayPerPixel)!=0)||((stCfg.u32DisplayWidth% DisplayPerPixel)!=0)) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ //Stretch H parameter check ++ if((stCfg.u32Width*stCfg.enStretchH_Ratio)!=stCfg.u32DisplayWidth) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: DisplayWidth should = Width * StretchH_Ratio!\n "); ++ return -EINVAL; ++ } ++ //Stretch V parameter check ++ if(stCfg.u32Height != stCfg.u32DisplayHeight) ++ { ++ FBDBG( "[FB Driver] Error: Set_General_Config: DisplayHeight should = Height!\n"); ++ return -EINVAL; ++ } ++ ++ //after checking valid parameter, save to global variable ++ genGOPGernelSettings.u32Width = stCfg.u32Width; ++ genGOPGernelSettings.u32Height = stCfg.u32Height; ++ genGOPGernelSettings.u32DisplayWidth = stCfg.u32DisplayWidth; ++ genGOPGernelSettings.u32DisplayHeight = stCfg.u32DisplayHeight; ++ genGOPGernelSettings.enBufferNum = stCfg.enBufferNum; ++ genGOPGernelSettings.enStretchH_Ratio = stCfg.enStretchH_Ratio; ++ ++ info->var.xres=stCfg.u32Width; ++ info->var.yres=stCfg.u32Height; ++ ++ ret=mdrvinfinityfb_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start=sg_mdrvinfinityfb_fix.smem_start; ++ info->fix.smem_len=sg_mdrvinfinityfb_fix.smem_len; ++ ++ info->var.width=info->var.xres; ++ info->var.height=info->var.yres; ++ ++ info->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ GOP_Setmode_Stretch_H(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0,(int)genGOPGernelSettings.enStretchH_Ratio); ++ ++ return ret; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnInvColor(unsigned long arg) ++{ ++ unsigned char enInvColor; ++ int ret=0; ++ ++ if (sg_videomemorysize<1) ++ { ++ FBDBGERR("[FB Driver] ERROR: _MDrv_FBIO_IOC_Set_EnInvColor, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&enInvColor, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] enable inverse color=%d \n",(int)enInvColor); ++ ++ // record in global variable ++ genInv_Color=enInvColor; ++ ++ GOP0_invColor_Enable(enInvColor); ++ ++ //check whether do sw update inverse color ++ mdrvinfinityfb_checkInvTable_UpdateMode(); ++ ++ if(enInvColor==1) ++ { ++ GOP0_invColor_Debug_Mode(); ++ ++ if(pSWupdateInvDebugThread==NULL) ++ { ++ pSWupdateInvDebugThread = kthread_create(mdrvinfinityfb_SWupdate_InvTable_debugmode,(void *)&pSWupdateInvDebugThread,"GOP0_debug_SWupdate_InvColor"); ++ if (IS_ERR(pSWupdateInvDebugThread)) ++ { ++ ret=PTR_ERR(pSWupdateInvDebugThread); ++ pSWupdateInvDebugThread = NULL; ++ FBDBGERR("[FB Driver] ERROR: debug mode! Create thread fail!%d\n",ret); ++ } ++ else ++ { ++ wake_up_process(pSWupdateInvDebugThread); ++ } ++ } ++ } ++ else if((enInvColor==0)&&(pSWupdateInvDebugThread!=NULL)) ++ { ++ kthread_stop(pSWupdateInvDebugThread); ++ pSWupdateInvDebugThread = NULL; ++ } ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_AEinfoConfig(unsigned long arg) ++{ ++ FB_GOP_INVCOLOR_AE_CONFIG stAECfg; ++ unsigned long tempcorpAEwidth=0; ++ unsigned long tempcorpAEheight=0; ++ int tempAEblkwidth=0; ++ int tempAEblkheight=0; ++ int tempAEblkxnum=0; ++ ++ if(copy_from_user(&stAECfg, (FB_GOP_INVCOLOR_AE_CONFIG __user *)arg, sizeof(FB_GOP_INVCOLOR_AE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] set AE config, AExres=%d, AEyres=%d, AEblkW=%d, AEblkH=%d\n", ++ (int)stAECfg.u32AEDisplayWidth,(int)stAECfg.u32AEDisplayHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight); ++ ++ // record in global variable ++ genAE_info.u32AEDisplayWidth = stAECfg.u32AEDisplayWidth; ++ genAE_info.u32AEDisplayHeight = stAECfg.u32AEDisplayHeight; ++ genAE_info.u32AEBlkWidth = stAECfg.u32AEBlkWidth; ++ genAE_info.u32AEBlkHeight = stAECfg.u32AEBlkHeight; ++ ++ // when scaling happens, change AE block size with this scale ++ if(genSC_info.bScalingEn) ++ { ++ if((genAE_info.u32AEBlkWidth!=0)&&(genAE_info.u32AEBlkHeight!=0)&&(genAE_info.u32AEDisplayWidth!=0)&&(genAE_info.u32AEDisplayHeight!=0)) ++ { ++ if(genSC_info.bCropEn)//if do crop, should add crop information to calculate scaling ratio ++ { ++ if(genSC_info.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempcorpAEwidth=genSC_info.u32CropYend-genSC_info.u32CropYstart; ++ tempcorpAEheight=genSC_info.u32CropXend-genSC_info.u32CropXstart; ++ tempAEblkwidth=((int)genAE_info.u32AEBlkWidth*(int)genSC_info.u32ScalerHeight/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info.u32AEBlkHeight*(int)genSC_info.u32ScalerWidth/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info.u32AEDisplayHeight/(int)genAE_info.u32AEBlkHeight); ++ GOP0_invColor_Set_AE_Config_Scaling(tempAEblkheight,tempAEblkwidth,tempAEblkxnum); ++ } ++ else ++ { ++ tempcorpAEwidth=genSC_info.u32CropXend-genSC_info.u32CropXstart; ++ tempcorpAEheight=genSC_info.u32CropYend-genSC_info.u32CropYstart; ++ tempAEblkwidth=((int)genAE_info.u32AEBlkWidth*(int)genSC_info.u32ScalerWidth/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info.u32AEBlkHeight*(int)genSC_info.u32ScalerHeight/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info.u32AEDisplayHeight/(int)genAE_info.u32AEBlkHeight); ++ GOP0_invColor_Set_AE_Config_Scaling(tempAEblkwidth,tempAEblkheight,tempAEblkxnum); ++ } ++ } ++ else// if no crop, calculate the scaling ratio directly ++ { ++ if(genSC_info.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempAEblkwidth=((int)genAE_info.u32AEBlkWidth*(int)genSC_info.u32ScalerHeight/(int)genAE_info.u32AEDisplayWidth); ++ tempAEblkheight=((int)genAE_info.u32AEBlkHeight*(int)genSC_info.u32ScalerWidth/(int)genAE_info.u32AEDisplayHeight); ++ tempAEblkxnum=((int)genAE_info.u32AEDisplayHeight/(int)genAE_info.u32AEBlkHeight); ++ GOP0_invColor_Set_AE_Config_Scaling(tempAEblkheight,tempAEblkwidth,tempAEblkxnum); ++ } ++ else ++ { ++ tempAEblkwidth=((int)genAE_info.u32AEBlkWidth*(int)genSC_info.u32ScalerWidth/(int)genAE_info.u32AEDisplayWidth); ++ tempAEblkheight=((int)genAE_info.u32AEBlkHeight*(int)genSC_info.u32ScalerHeight/(int)genAE_info.u32AEDisplayHeight); ++ tempAEblkxnum=((int)genAE_info.u32AEDisplayHeight/(int)genAE_info.u32AEBlkHeight); ++ GOP0_invColor_Set_AE_Config_Scaling(tempAEblkwidth,tempAEblkheight,tempAEblkxnum); ++ } ++ } ++ } ++ else ++ { ++ FBDBGERR( "[FB Driver] Error: _MDrv_FBIO_IOC_Set_AEinfoConfig fail2!!! No AE info\n"); ++ return -EFAULT; ++ } ++ } ++ else//if disable scaling, set original settings ++ { ++ if(genSC_info.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP0_invColor_Set_AE_Config((int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP0_invColor_Set_AE_Config((int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEDisplayWidth); ++ } ++ } ++ ++ if(genSC_info.bCropEn)//if crop enable, reset crop information when AE info change ++ { ++ if(genSC_info.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP0_invColor_Set_Crop_Config((int)genSC_info.u32CropXstart,(int)genSC_info.u32CropYstart,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP0_invColor_Set_Crop_Config((int)genSC_info.u32CropXstart,(int)genSC_info.u32CropYstart,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEDisplayWidth); ++ } ++ } ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_YThres(unsigned long arg) ++{ ++ unsigned long YThres; ++ ++ if(copy_from_user(&YThres, (unsigned long __user *)arg, sizeof(unsigned long))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] set Y threshold=%d \n",(int)YThres); ++ ++ // record in global variable ++ genY_Thres=YThres; ++ ++ GOP0_invColor_Set_Y_Threshold((int)YThres); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_ScalerinfoConfig(unsigned long arg) ++{ ++ FB_GOP_INVCOLOR_SCALER_CONFIG stSclCfg; ++ unsigned long tempcorpAEwidth=0; ++ unsigned long tempcorpAEheight=0; ++ int tempAEblkwidth=0; ++ int tempAEblkheight=0; ++ int tempAEblkxnum=0; ++ int tempAEblkynum=0; ++ ++ if(copy_from_user(&stSclCfg, (FB_GOP_INVCOLOR_SCALER_CONFIG __user *)arg, sizeof(FB_GOP_INVCOLOR_SCALER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FBDBG( "[FB Driver] set Scl config, CropEn=%d, ScalingEn=%d, RotateEn=%d\n", ++ (int)stSclCfg.bCropEn,(int)stSclCfg.bScalingEn,(int)stSclCfg.bRotateEn); ++ ++ if((stSclCfg.u32ScalerWidth<1)||(stSclCfg.u32ScalerWidth>1920)) ++ { ++ FBDBGERR( "[FB Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! parameter wrong\n"); ++ return -EFAULT; ++ } ++ if((stSclCfg.u32ScalerHeight<1)||(stSclCfg.u32ScalerHeight>1920)) ++ { ++ FBDBGERR( "[FB Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! parameter wrong\n"); ++ return -EFAULT; ++ } ++ ++ // record in global variable ++ genSC_info.bCropEn = stSclCfg.bCropEn; ++ genSC_info.bScalingEn = stSclCfg.bScalingEn; ++ genSC_info.u32ScalerWidth = stSclCfg.u32ScalerWidth; ++ genSC_info.u32ScalerHeight= stSclCfg.u32ScalerHeight; ++ genSC_info.u32CropXstart = stSclCfg.u32CropXstart; ++ genSC_info.u32CropXend = stSclCfg.u32CropXend; ++ genSC_info.u32CropYstart = stSclCfg.u32CropYstart; ++ genSC_info.u32CropYend = stSclCfg.u32CropYend; ++ // rotate will be get from ISP driver ++ //genSC_info.bRotateEn = stSclCfg.bRotateEn; ++ //genSC_info.enRotateA = stSclCfg.enRotateA; ++ ++ if(stSclCfg.bCropEn) ++ { ++ if((genAE_info.u32AEBlkWidth!=0)&&(genAE_info.u32AEBlkHeight!=0)&&(genAE_info.u32AEDisplayWidth!=0)&&(genAE_info.u32AEDisplayHeight!=0)) ++ { ++ if(genSC_info.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP0_invColor_Set_Crop_Config((int)stSclCfg.u32CropXstart,(int)stSclCfg.u32CropYstart,(int)genAE_info.u32AEBlkHeight,(int)genAE_info.u32AEBlkWidth,(int)genAE_info.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP0_invColor_Set_Crop_Config((int)stSclCfg.u32CropXstart,(int)stSclCfg.u32CropYstart,(int)genAE_info.u32AEBlkWidth,(int)genAE_info.u32AEBlkHeight,(int)genAE_info.u32AEDisplayWidth); ++ } ++ } ++ else ++ { ++ FBDBGERR( "[FB Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! No AE info\n"); ++ return -EFAULT; ++ } ++ } ++ ++ // when scaling happens, change AE block size with this scale ++ if(stSclCfg.bScalingEn) ++ { ++ if((genAE_info.u32AEBlkWidth!=0)&&(genAE_info.u32AEBlkHeight!=0)&&(genAE_info.u32AEDisplayWidth!=0)&&(genAE_info.u32AEDisplayHeight!=0)) ++ { ++ if(stSclCfg.bCropEn)//if do crop, should add crop information to calculate scaling ratio ++ { ++ if(genSC_info.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempcorpAEwidth=genSC_info.u32CropYend-genSC_info.u32CropYstart; ++ tempcorpAEheight=genSC_info.u32CropXend-genSC_info.u32CropXstart; ++ tempAEblkwidth=((int)genAE_info.u32AEBlkWidth*(int)genSC_info.u32ScalerHeight/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info.u32AEBlkHeight*(int)genSC_info.u32ScalerWidth/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info.u32AEDisplayHeight/(int)genAE_info.u32AEBlkHeight); ++ tempAEblkynum=((int)genAE_info.u32AEDisplayWidth/(int)genAE_info.u32AEBlkWidth); ++ if(tempAEblkheight > 0) ++ { ++ while(((genSC_info.u32ScalerWidth%tempAEblkheight)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkheight++; ++ if(tempAEblkheight>genSC_info.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info.u32ScalerWidth%tempAEblkwidth)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkwidth++; ++ if(tempAEblkwidth>genSC_info.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info.u32ScalerWidth%tempAEblkheight)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkheight++; ++ if(tempAEblkheight>genSC_info.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info.u32ScalerWidth%tempAEblkwidth)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkwidth++; ++ if(tempAEblkwidth>genSC_info.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++DEVICE_ATTR(gopinfo, 0644, gopinfo_show, gopinfo_store); ++ ++ ++static int mdrvinfinityfb_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ int clockIdxtemp=0; ++ FBDBG("[FB Driver] in mdrvinfinityfb_suspend \r\n"); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop_clks[clockIdxtemp]); ++ } ++ } ++ //clk_disable_unprepare(gop_psram_clk); ++ return 0; ++} ++ ++static int mdrvinfinityfb_resume(struct platform_device *pdev) ++{ ++ //dma_addr_t fb2_PHY_ADD_SHOW=0; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ // open all needed clocks ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop_clks[clockIdxtemp])) ++ { ++ FBDBGERR( "[FB Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ FBDBG("[FB Driver] mdrvinfinityfb_resume \r\n"); ++ ++ GOP_Setmode(TRUE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ //set palette ++ mdrvinfinityfb_infinity_SetPalette(stGOPCurrentPalInfo,0,255); ++ ++ return 0; ++} ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : Initialization. Initial HW, fill table, when load module, ++| this function will be called. ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb_probe(struct platform_device *dev) ++{ ++ struct fb_info *pinfo = NULL; ++ int retval = -ENOMEM; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ if (NULL == dev) ++ { ++ FBDBGERR("[FB Driver] ERROR: in mdrvinfinityfb_prob: dev is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ // open all needed clocks ++ num_parents_clocks = of_clk_get_parent_count(dev->dev.of_node); ++ gop_clks=kzalloc(((sizeof(struct clk *) * num_parents_clocks)),GFP_KERNEL); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ gop_clks[clockIdxtemp]= of_clk_get(dev->dev.of_node, clockIdxtemp); ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop_clks[clockIdxtemp])) ++ { ++ FBDBGERR( "[FB Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ // init global variable ++ mdrvinfinityfb_updateinfo(); ++ ++ pinfo = framebuffer_alloc(sizeof(struct fb_info), &dev->dev); ++ if (!pinfo) ++ goto err; ++ ++ // copy data for register framebuffer ++ pinfo->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1); ++ pinfo->fbops = &sg_mdrvinfinityfb_ops; ++ pinfo->var = sg_mdrvinfinityfb_default_var; ++ pinfo->fix = sg_mdrvinfinityfb_fix; ++ pinfo->pseudo_palette = pinfo->par; ++ pinfo->par = NULL; ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ ++ // allocate color map ++ // 256 is following to the vfb.c ++ retval = fb_alloc_cmap(&pinfo->cmap, 256, 0); ++ if (retval < 0) ++ goto err1; ++ ++ // register our fb to fbmem.c ++ retval = register_framebuffer(pinfo); ++ if (retval < 0) ++ goto err2; ++ ++ // set data to device ++ platform_set_drvdata(dev, pinfo); ++ ++ // set gop register settings ++ GOP_Setmode(FALSE, 0,sg_mdrvinfinityfb_default_var.xres,sg_mdrvinfinityfb_default_var.yres,sg_G3D_fb2_bus_addr1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ // set gop inverse color init settings ++ GOP0_invColor_init(); ++ ++ // set init palette ++ mdrvinfinityfb_infinity_SetPalette(DefaultPaletteEntry,0,255); ++ ++ // register sysfs ++ ret = device_create_file(&dev->dev, &dev_attr_gopinfo); ++ if (ret != 0) ++ { ++ dev_err(&dev->dev, ++ "[FB Driver] Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ else ++ { ++ FBDBGMORE("[FB Driver] device attr ok\n"); ++ } ++ ++ return 0; ++ ++err2: ++ fb_dealloc_cmap(&pinfo->cmap); ++err1: ++ framebuffer_release(pinfo); ++err: ++ ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ ++ return retval; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : we free memory, release frame buffer here ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb_remove(struct platform_device *dev) ++{ ++ struct fb_info *pinfo; ++ int clockIdxtemp=0; ++ pinfo = 0; ++ ++ if (NULL == dev) ++ { ++ FBDBGERR("[FB Driver] ERROR: mdrvinfinityfb_remove: dev is NULL pointer \n"); ++ return -ENOTTY; ++ } ++ ++ pinfo = platform_get_drvdata(dev); ++ if (pinfo) ++ { ++ unregister_framebuffer(pinfo); ++ ++ free_dmem(KEY_DMEM_FB_BUF, ++ PAGE_ALIGN(sg_videomemorysize), ++ sg_pG3D_fb2_vir_addr1, ++ sg_G3D_fb2_bus_addr1); ++ ++ framebuffer_release(pinfo); ++ } ++ ++ // close all clocks ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop_clks[clockIdxtemp]); ++ } ++ } ++ return 0; ++} ++ ++static int mdrvinfinityfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ dma_addr_t fb2_pandisplay_PHY_ADD_SHOW=0; ++ ++ FBDBGMORE( "[FB Driver]%s: var->yoffset=%x! info->var.height=%x\n ",__func__,var->yoffset,info->var.height); ++ ++ if(genGOPGernelSettings.enBufferNum==FB_DOUBLE_BUFFER)//double buffer ++ { ++ if (var->yoffset >= info->var.height) ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start + (info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL); ++ ++ FBDBGMORE( "[FB Driver]%s: use buffer 1! Addr=%x\n ",__func__,fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ else ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start; ++ ++ FBDBGMORE( "[FB Driver]%s: use buffer 0 Addr=%x!\n ",__func__,fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ } ++ else ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start; ++ ++ FBDBGMORE( "mdrvinfinityfb_pan_display: use buffer 0 Addr=%x!\n ",fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ ++ GOP_Pan_Display(0, fb2_pandisplay_PHY_ADD_SHOW); ++ ++ return 0; ++} ++ ++ ++//check var to see if supported by this device, defined for infinity ++static int mdrvinfinityfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ int max_x_res=2560; ++ int max_y_res=2048; ++ ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //MstarFB_ENTER(); ++ ++ if((var->yres<1)||(var->xres<1)) ++ { ++ FBDBGERR( "[FB Driver] Error: fb_check_var: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ if((var->yres * var->xres)>(max_x_res*max_y_res)) ++ { ++ FBDBGERR( "[FB Driver] Error: fb_check_var: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ ++ if((var->xres % DisplayPerPixel)!=0) ++ { ++ FBDBGERR( "[FB Driver] Error: fb_check_var: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++module_platform_driver(sg_mdrvinfinityfb_driver); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/fb/infinity3/mdrv_fb.h b/drivers/mstar/fb/infinity3/mdrv_fb.h +new file mode 100644 +index 00000000..85f64355 +--- /dev/null ++++ b/drivers/mstar/fb/infinity3/mdrv_fb.h +@@ -0,0 +1,330 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_fb.h ++ * DESCRIPTION ++ * Including some MACRO needed in mdrvfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/mdrvfb.h -- mdrvfb frame buffer device ++ ******************************************************************************/ ++ ++//-------------------------------------------------------------------------------------------------- ++// Includes ++//-------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include //for dma_alloc_coherent ++#include ++#include //seems do not need this ++#include ++#include ++#include ++#include ++#include //access_ok(), and VERIFY_WRITE/READ ++#include //for _IO() macro ++#include ++#include ++#include ++#include //do_gettimeofday() ++#include "gop/mdrv_gop.h" ++#include "inv_color/mdrv_gop0_inv_color.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" //for dma_alloc_coherent ++#include ++#include ++#include ++ ++#include "mdrv_fb_io.h" ++#include "mdrv_fb_st.h" ++#include "mdrv_isp_io_st.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Defines ++//-------------------------------------------------------------------------------------------------- ++#define FB_DEBUG 0 //0 for only error message, 1 for normal debug message, 2 for more message ++ ++#if (FB_DEBUG==0) ++#define FBDBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBG(fmt, arg...) ++#define FBDBGMORE(fmt, arg...) ++#elif (FB_DEBUG==1) ++#define FBDBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBGMORE(fmt, arg...) ++#elif (FB_DEBUG==2) ++#define FBDBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FBDBGMORE(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define FBDBGERR(fmt, arg...) ++#define FBDBG(fmt, arg...) ++#define FBDBGMORE(fmt, arg...) ++#endif ++ ++#define CAST_2_USER_VOID_P (void __user *) ++#define CAST_2_USER_UINT_P (unsigned int __user *) ++#define CAST_2_IOMEM_CHAR_P (u8 __iomem *) ++ ++#define ANDROID_NUMBER_OF_BUFFERS 1 ++#define ANDROID_FB_FORMAT _8Bit_Palette ++#define defult_XRES 0 //init value for xres of fb_var_screeninfo, do not assign value while init ++#define defult_YRES 0 //init value for yres of fb_var_screeninfo, do not assign value while init ++#if (ANDROID_FB_FORMAT == RGB565) ++#define BPX 16 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 2 ++#elif ((ANDROID_FB_FORMAT == ARGB8888) || (ANDROID_FB_FORMAT == ABGR8888)) ++#define BPX 32 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 4 ++#elif (ANDROID_FB_FORMAT == _8Bit_Palette) ++#define BPX 8 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 1 ++#else ++ #ERROR("Not Support") ++#endif ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Functions ++//-------------------------------------------------------------------------------------------------- ++static int mdrvinfinityfb_ioctl(struct fb_info *info, u32 cmd, unsigned long arg); ++static int mdrvinfinityfb_mmap(struct fb_info *info, struct vm_area_struct *vma); ++static int mdrvinfinityfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); ++static int mdrvinfinityfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info); ++static int mdrvinfinityfb_set_par(struct fb_info *info); ++static int mdrvinfinityfb_suspend(struct platform_device *pdev,pm_message_t state); ++static int mdrvinfinityfb_resume(struct platform_device *pdev); ++static int mdrvinfinityfb_probe(struct platform_device *dev); ++static int mdrvinfinityfb_remove(struct platform_device *dev); ++ ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++struct clk **gop_clks; /* clock define, one for palette sram clock, one for scaler fclk1 *///index=1 is scl_fclk ++int num_parents_clocks = 0; /* number of clocks*/ ++static void *sg_pG3D_fb2_vir_addr1 = 0; /* virtual address of frame buffer */ ++static u_long sg_videomemorysize = 0; /* frame buffer size */ ++dma_addr_t sg_G3D_fb2_bus_addr1 = 0; /* physical address of frame buffer */ ++ ++FB_GOP_GWIN_CONFIG genGWinInfo ={0}; /* global variable to record gwin information */ ++unsigned char genGWIN = 1; /* global variable to record gwin is open or close *///open:1; close:0 ++FB_GOP_ALPHA_CONFIG genGOPALPHA ={0}; /* global variable to record alpha blending information */ ++FB_GOP_COLORKEY_CONFIG genGOPCOLORKEY ={0}; /* global variable to record color key information */ ++ ++unsigned char genInv_Color = 0; /* global variable to record inverse color is open or close *///open:1; close:0 ++FB_GOP_INVCOLOR_AE_CONFIG genAE_info ={0}; /* global variable to record AE information */ ++unsigned long genY_Thres = 0; /* global variable to record Y Threshold */ ++FB_GOP_INVCOLOR_SCALER_CONFIG genSC_info ={0}; /* global variable to record Scaler information */ ++ ++FB_GOP_RESOLUTION_STRETCH_H_CONFIG genGOPGernelSettings={0}; /* global variable to record Stretch mode information */ ++ ++static struct task_struct *pSWupdateInvThread=NULL; ++unsigned char genTreadisError = 0; ++ ++static struct task_struct *pSWupdateInvDebugThread=NULL; ++ ++//// {B, G, R, Alpha} ++static FB_GOP_PaletteEntry DefaultPaletteEntry[GOP_PALETTE_ENTRY_NUM] = ++{ ++ {{ 0, 0, 0, 0}}, {{ 0, 0,128, 0}}, {{ 0,128, 0, 0}}, {{ 0,128,128, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0,128, 0}}, {{128,128, 0, 0}}, {{192,192,192, 0}}, ++ {{192,220,192, 0}}, {{240,202,166, 0}}, {{ 0, 32, 64, 0}}, {{ 0, 32, 96, 0}}, ++ {{ 0, 32,128, 0}}, {{ 0, 32,160, 0}}, {{ 0, 32,192, 0}}, {{ 0, 32,224, 0}}, ++ {{ 0, 64, 0, 0}}, {{ 0, 64, 32, 0}}, {{ 0, 64, 64, 0}}, {{ 0, 64, 96, 0}}, ++ {{ 0, 64,128, 0}}, {{ 0, 64,160, 0}}, {{ 0, 64,192, 0}}, {{ 0, 64,224, 0}}, ++ {{ 0, 96, 0, 0}}, {{ 0, 96, 32, 0}}, {{ 0, 96, 64, 0}}, {{ 0, 96, 96, 0}}, ++ {{ 0, 96,128, 0}}, {{ 0, 96,160, 0}}, {{ 0, 96,192, 0}}, {{ 0, 96,224, 0}}, ++ {{ 0,128, 0, 0}}, {{ 0,128, 32, 0}}, {{ 0,128, 64, 0}}, {{ 0,128, 96, 0}}, ++ {{ 0,128,128, 0}}, {{ 0,128,160, 0}}, {{ 0,128,192, 0}}, {{ 0,128,224, 0}}, ++ {{ 0,160, 0, 0}}, {{ 0,160, 32, 0}}, {{ 0,160, 64, 0}}, {{ 0,160, 96, 0}}, ++ {{ 0,160,128, 0}}, {{ 0,160,160, 0}}, {{ 0,160,192, 0}}, {{ 0,160,224, 0}}, ++ {{ 0,192, 0, 0}}, {{ 0,192, 32, 0}}, {{ 0,192, 64, 0}}, {{ 0,192, 96, 0}}, ++ {{ 0,192,128, 0}}, {{ 0,192,160, 0}}, {{ 0,192,192, 0}}, {{ 0,192,224, 0}}, ++ {{ 0,224, 0, 0}}, {{ 0,224, 32, 0}}, {{ 0,224, 64, 0}}, {{ 0,224, 96, 0}}, ++ {{ 0,224,128, 0}}, {{ 0,224,160, 0}}, {{ 0,224,192, 0}}, {{ 0,224,224, 0}}, ++ {{ 64, 0, 0, 0}}, {{ 64, 0, 32, 0}}, {{ 64, 0, 64, 0}}, {{ 64, 0, 96, 0}}, ++ {{ 64, 0,128, 0}}, {{ 64, 0,160, 0}}, {{ 64, 0,192, 0}}, {{ 64, 0,224, 0}}, ++ {{ 64, 32, 0, 0}}, {{ 64, 32, 32, 0}}, {{ 64, 32, 64, 0}}, {{ 64, 32, 96, 0}}, ++ {{ 64, 32,128, 0}}, {{ 64, 32,160, 0}}, {{ 64, 32,192, 0}}, {{ 64, 32,224, 0}}, ++ {{ 64, 64, 0, 0}}, {{ 64, 64, 32, 0}}, {{ 64, 64, 64, 0}}, {{ 64, 64, 96, 0}}, ++ {{ 64, 64,128, 0}}, {{ 64, 64,160, 0}}, {{ 64, 64,192, 0}}, {{ 64, 64,224, 0}}, ++ {{ 64, 96, 0, 0}}, {{ 64, 96, 32, 0}}, {{ 64, 96, 64, 0}}, {{ 64, 96, 96, 0}}, ++ {{ 64, 96,128, 0}}, {{ 64, 96,160, 0}}, {{ 64, 96,192, 0}}, {{ 64, 96,224, 0}}, ++ {{ 64,128, 0, 0}}, {{ 64,128, 32, 0}}, {{ 64,128, 64, 0}}, {{ 64,128, 96, 0}}, ++ {{ 64,128,128, 0}}, {{ 64,128,160, 0}}, {{ 64,128,192, 0}}, {{ 64,128,224, 0}}, ++ {{ 64,160, 0, 0}}, {{ 64,160, 32, 0}}, {{ 64,160, 64, 0}}, {{ 64,160, 96, 0}}, ++ {{ 64,160,128, 0}}, {{ 64,160,160, 0}}, {{ 64,160,192, 0}}, {{ 64,160,224, 0}}, ++ {{ 64,192, 0, 0}}, {{ 64,192, 32, 0}}, {{ 64,192, 64, 0}}, {{ 64,192, 96, 0}}, ++ {{ 64,192,128, 0}}, {{ 64,192,160, 0}}, {{ 64,192,192, 0}}, {{ 64,192,224, 0}}, ++ {{ 64,224, 0, 0}}, {{ 64,224, 32, 0}}, {{ 64,224, 64, 0}}, {{ 64,224, 96, 0}}, ++ {{ 64,224,128, 0}}, {{ 64,224,160, 0}}, {{ 64,224,192, 0}}, {{ 64,224,224, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0, 32, 0}}, {{128, 0, 64, 0}}, {{128, 0, 96, 0}}, ++ {{128, 0,128, 0}}, {{128, 0,160, 0}}, {{128, 0,192, 0}}, {{128, 0,224, 0}}, ++ {{128, 32, 0, 0}}, {{128, 32, 32, 0}}, {{128, 32, 64, 0}}, {{128, 32, 96, 0}}, ++ {{128, 32,128, 0}}, {{128, 32,160, 0}}, {{128, 32,192, 0}}, {{128, 32,224, 0}}, ++ {{128, 64, 0, 0}}, {{128, 64, 32, 0}}, {{128, 64, 64, 0}}, {{128, 64, 96, 0}}, ++ {{128, 64,128, 0}}, {{128, 64,160, 0}}, {{128, 64,192, 0}}, {{128, 64,224, 0}}, ++ {{128, 96, 0, 0}}, {{128, 96, 32, 0}}, {{128, 96, 64, 0}}, {{128, 96, 96, 0}}, ++ {{128, 96,128, 0}}, {{128, 96,160, 0}}, {{128, 96,192, 0}}, {{128, 96,224, 0}}, ++ {{128,128, 0, 0}}, {{128,128, 32, 0}}, {{128,128, 64, 0}}, {{128,128, 96, 0}}, ++ {{128,128,128, 0}}, {{128,128,160, 0}}, {{128,128,192, 0}}, {{128,128,224, 0}}, ++ {{128,160, 0, 0}}, {{128,160, 32, 0}}, {{128,160, 64, 0}}, {{128,160, 96, 0}}, ++ {{128,160,128, 0}}, {{128,160,160, 0}}, {{128,160,192, 0}}, {{128,160,224, 0}}, ++ {{128,192, 0, 0}}, {{128,192, 32, 0}}, {{128,192, 64, 0}}, {{128,192, 96, 0}}, ++ {{128,192,128, 0}}, {{128,192,160, 0}}, {{128,192,192, 0}}, {{128,192,224, 0}}, ++ {{128,224, 0, 0}}, {{128,224, 32, 0}}, {{128,224, 64, 0}}, {{128,224, 96, 0}}, ++ {{128,224,128, 0}}, {{128,224,160, 0}}, {{128,224,192, 0}}, {{128,224,224, 0}}, ++ {{192, 0, 0, 0}}, {{192, 0, 32, 0}}, {{192, 0, 64, 0}}, {{192, 0, 96, 0}}, ++ {{192, 0,128, 0}}, {{192, 0,160, 0}}, {{192, 0,192, 0}}, {{192, 0,224, 0}}, ++ {{192, 32, 0, 0}}, {{192, 32, 32, 0}}, {{192, 32, 64, 0}}, {{192, 32, 96, 0}}, ++ {{192, 32,128, 0}}, {{192, 32,160, 0}}, {{192, 32,192, 0}}, {{192, 32,224, 0}}, ++ {{192, 64, 0, 0}}, {{192, 64, 32, 0}}, {{192, 64, 64, 0}}, {{192, 64, 96, 0}}, ++ {{192, 64,128, 0}}, {{192, 64,160, 0}}, {{192, 64,192, 0}}, {{192, 64,224, 0}}, ++ {{192, 96, 0, 0}}, {{192, 96, 32, 0}}, {{192, 96, 64, 0}}, {{192, 96, 96, 0}}, ++ {{192, 96,128, 0}}, {{192, 96,160, 0}}, {{192, 96,192, 0}}, {{192, 96,224, 0}}, ++ {{192,128, 0, 0}}, {{192,128, 32, 0}}, {{192,128, 64, 0}}, {{192,128, 96, 0}}, ++ {{192,128,128, 0}}, {{192,128,160, 0}}, {{192,128,192, 0}}, {{192,128,224, 0}}, ++ {{192,160, 0, 0}}, {{192,160, 32, 0}}, {{192,160, 64, 0}}, {{192,160, 96, 0}}, ++ {{192,160,128, 0}}, {{192,160,160, 0}}, {{192,160,192, 0}}, {{192,160,224, 0}}, ++ {{192,192, 0, 0}}, {{192,192, 32, 0}}, {{192,192, 64, 0}}, {{192,192, 96, 0}}, ++ {{192,192,128, 0}}, {{192,192,160, 0}}, {{240,251,255, 0}}, {{164,160,160, 0}}, ++ {{128,128,128, 0}}, {{ 0, 0,255, 0}}, {{ 0,255, 0, 0}}, {{ 0,255,255, 0}}, ++ {{255, 0, 0, 0}}, {{255, 0,255, 0}}, {{255,255, 0, 0}}, {{255,255,255, 0}} ++ }; ++ ++ ++FB_GOP_PaletteEntry stGOPCurrentPalInfo[GOP_PALETTE_ENTRY_NUM]={}; ++ ++ ++static const char* KEY_DMEM_FB_BUF="FB_BUFFER"; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct fb_var_screeninfo sg_mdrvinfinityfb_default_var = ++{ ++ .xres = defult_XRES, /* visible resolution*/ //display x size ++ .yres = defult_YRES, //display y size ++ .xres_virtual = defult_XRES, /* virtual resolution*/ //framebuffer x size ++ .yres_virtual = defult_YRES, //framebuffer y size ++ .xoffset = 0, /* offset from virtual to visible */ ++ .yoffset = 0, ++ ++ .bits_per_pixel = BPX, ++ ++#if (ANDROID_FB_FORMAT == _8Bit_Palette) ++ .grayscale = 0, ++ .transp = {0,0,0}, ++ .red = {0,0,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {0,0,0}, ++ .blue = {0,0,0}, ++#elif (ANDROID_FB_FORMAT == RGB565) //Data: R G B, 5 6 5 ++ .red = {11,5,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {5,6,0}, ++ .blue = {0,5,0}, ++#elif (ANDROID_FB_FORMAT == ARGB8888) //Data: R G B A, 8 8 8 8 ++ .grayscale = 0, ++ .transp = {0,8,0}, ++ .red = {24,8,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {16,8,0}, ++ .blue = {8,8,0}, ++#endif ++ ++ .activate = FB_ACTIVATE_NOW, ++ .height = defult_XRES, /* height of picture in mm */ ++ .width = defult_YRES, /* width of picture in mm */ ++ ++ /* timing settings, useless here*/ ++ .pixclock = 100000, /* pixel clock in ps (pico seconds) */ ++ .left_margin = 24, /* time from sync to picture */ ++ .right_margin = 4, /* time from picture to sync */ ++ .upper_margin = 6, /* time from sync to picture */ ++ .lower_margin = 4, ++ .hsync_len = 64, /* length of horizontal sync */ ++ .vsync_len = 2, /* length of vertical sync */ ++ .vmode = FB_VMODE_NONINTERLACED, ++}; ++ ++/* Device independent unchangeable information */ ++static struct fb_fix_screeninfo sg_mdrvinfinityfb_fix = ++{ ++ .id = "FB_gop0", /* identification string eg "TT Builtin"*/ ++ .smem_start = 0, /* Start of frame buffer mem*/ ++ .smem_len = 0, /* Length of frame buffer mem*/ ++ .type = FB_TYPE_PACKED_PIXELS, /* see FB_TYPE_*/ ++ .visual = FB_VISUAL_TRUECOLOR, /* see FB_VISUAL_*/ ++ .xpanstep = 0, /* zero if no hardware panning*/ ++ .ypanstep = 1, /* zero if no hardware panning*/ ++ .ywrapstep = 0, /* zero if no hardware ywrap*/ ++ .line_length = (defult_XRES * ANDROID_BYTES_PER_PIXEL), /* length of a line in bytes*/ ++ .mmio_start = 0x20000000, /* Start of Memory Mapped I/O*/ ++ /* (physical address)*/ ++ .mmio_len = 0x10000000, /* Length of Memory Mapped I/O*/ ++ .accel = FB_ACCEL_NONE, /* Type of acceleration available*/ ++}; ++ ++static struct fb_ops sg_mdrvinfinityfb_ops = ++{ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = sys_fillrect, /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = sys_copyarea, /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = sys_imageblit, /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ ++ .fb_mmap = mdrvinfinityfb_mmap, /* for non cached memory */ ++ .fb_ioctl = mdrvinfinityfb_ioctl, ++ .fb_pan_display = mdrvinfinityfb_pan_display, ++ .fb_check_var = mdrvinfinityfb_check_var, ++ .fb_set_par = mdrvinfinityfb_set_par, ++}; ++ ++ ++static const struct of_device_id infinity_infinityfb_dt_ids[] = ++{ ++ { .compatible = "mstar,infinity-gop" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, infinity_infinityfb_dt_ids); ++ ++static struct platform_driver sg_mdrvinfinityfb_driver = ++{ ++ .probe = mdrvinfinityfb_probe, /* initiailize */ ++ .remove = mdrvinfinityfb_remove, /* it free(mem), release framebuffer, free irq etc. */ ++ .suspend = mdrvinfinityfb_suspend, ++ .resume = mdrvinfinityfb_resume, ++ ++ .driver = ++ { ++ .name = "mdrvinfinityfb", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(infinity_infinityfb_dt_ids), ++ }, ++}; +diff --git a/drivers/mstar/fb1/Kconfig b/drivers/mstar/fb1/Kconfig +new file mode 100644 +index 00000000..0d7ce764 +--- /dev/null ++++ b/drivers/mstar/fb1/Kconfig +@@ -0,0 +1,14 @@ ++config MS_FB ++ tristate "FB driver" ++ default y ++ select FB ++ select FB_SYS_FILLRECT ++ select FB_SYS_COPYAREA ++ select FB_SYS_IMAGEBLIT ++ select FB_SYS_FOPS ++ help ++ ++config MS_FB1_INFINITY3 ++ tristate "FB driver (GOP1) support for iNfinity3" ++ depends on MS_FB ++ depends on ARCH_INFINITY3 +\ No newline at end of file +diff --git a/drivers/mstar/fb1/Makefile b/drivers/mstar/fb1/Makefile +new file mode 100644 +index 00000000..a4686a4e +--- /dev/null ++++ b/drivers/mstar/fb1/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MS_FB1_INFINITY3) += infinity3/ +diff --git a/drivers/mstar/fb1/infinity3/Makefile b/drivers/mstar/fb1/infinity3/Makefile +new file mode 100644 +index 00000000..5dd494b6 +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/Makefile +@@ -0,0 +1,19 @@ ++# ++# Makefile for MStar fb device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++#--------gop-------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb1/infinity3/gop1 ++EXTRA_CFLAGS += -Idrivers/mstar/fb1/infinity3/inv_color ++ ++# files ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop_io.o ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop.o ++#obj-$(CONFIG_MS_FB_INFINITY) += mdrv_fb.o ++ ++obj-$(CONFIG_MS_FB1_INFINITY3) += infinity_fb1.o ++ ++infinity_fb1-objs := mdrv_fb1.o \ ++ gop1/mdrv_gop1.o \ ++ inv_color/mdrv_gop1_inv_color.o +\ No newline at end of file +diff --git a/drivers/mstar/fb1/infinity3/gop1/gop_c2_reg.h b/drivers/mstar/fb1/infinity3/gop1/gop_c2_reg.h +new file mode 100644 +index 00000000..6c1b854e +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/gop1/gop_c2_reg.h +@@ -0,0 +1,249 @@ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME gop_c2_reg.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define BASE_REG_RIU_PA (0x1F000000) ++ ++//GOP Base register defines ++//if there's no direct bank, the base addresses of GOP00, GOP01 and GOP02 are the same ++//I1 settings ++//#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//I3 settings for gop1(at scl2) ++#define mdrv_BASE_REG_GOP10_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123400/2)) ++#define mdrv_BASE_REG_GOP11_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123500/2)) ++#define mdrv_BASE_REG_GOP12_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123600/2)) ++ ++//MIU Bus settings ++#define MIU_BUS_INFINITY3 0x4 ++#define MIU_BUS_ALIGN MIU_BUS_INFINITY3 ++ ++ ++#define mdrv_GWin0_Disable (0xFFFE) ++#define mdrv_GWIN0_Enable (0x1) ++ ++#define mdrv_ENABLE_CONST_ALPHA (~(0x1<<14)) ++ ++//fomrat define ++#define GWIN_FMT_MASK 0x00F0 ++#define RGB1555_Blink 0x0000 ++#define RGB565 0x0010 ++#define ARGB4444 0x0020 ++#define _2266 0x0030 ++#define _8Bit_Palette 0x0040 ++#define ARGB8888 0x0050 ++#define ARGB1555 0x0060 ++#define ABGR8888 0x0070 ++#define RGB1555_UV7Y8 0x0080 ++#define UV8Y8 0x0090 ++#define RGBA5551 0x00A0 ++#define RGBA4444 0x00B0 ++ ++//------------------------------------------------------------------------------ ++// GOP ++//------------------------------------------------------------------------------ ++// Bank 0, GOPG0_0 ++ ++// REG_GOP_00 ++#define GOP_SOFT_RESET 0x0001 ++#define GOP_VS_INV 0x0002 ++#define GOP_HS_INV 0x0004 ++#define GOP_DISPLAY_MODE 0x0008 // 0:interlace, 1: progress ++#define GOP_FIELD_INV 0x0010 ++#define GOP_YUV_TRANSPARENT_COLOR_ENABLE 0x0020 ++#define GOP_TEST_PATTENR_MODE_ENABLE 0x0040 ++#define GOP_5541_EN 0x0080 // RGB5541 alpha mask mode enable, only for RGB1555 Data type ++#define GOP_REG_OUTPUT_READY 0x0100 ++#define GOP_G3D_FORMATE_NEW_MODE_ENABLE 0x0200 ++#define GOP_OUTPUT_FORMAT 0x0400 // 0:RGB out, 1:YUV out ++#define GOP_RGB_TRANSPARENT_COLOR_MASK 0x0800 ++#define GOP_DISP_HBACK_ENABLE 0x1000 // H Mirror enable; H pixel read out direction, 0:forward, 1:backward ++#define GOP_DISP_VBACK_ENABLE 0x2000 // V Mirror enable; V line read out direction, 0:down, 1:up ++#define GOP_HS_MASK 0x4000 ++#define GOP_ALPHA_INV 0x8000 ++// GOP Display Mode ++#define GWIN_display_mode_progress 0x0008 ++#define GWIN_display_mode_interlace 0x0000 ++// GOP Output Color ++#define GOP_YUVOUT 0x0400 ++#define GOP_RGBOUT 0x0000 ++// GOP RGB Transparent Color ++#define GOP_RGB_TRANSPARENT_COLOR_ENABLE 0x0800 ++#define GOP_RGB_TRANSPARENT_COLOR_DISABLE 0x0000 ++ ++ ++// REG_GOP_01 ++// GOP Destination ++#define GOP_DST_IP_MAIN 0x0000 ++#define GOP_DST_IP_SUB 0x0001 ++#define GOP_DST_OP 0x0002 ++#define GOP_DST_MVOP 0x0003 ++#define GOP_DST_SUB_MVOP 0x0004 ++#define GOP_DST_FRC 0x0006 ++// GOP interval settings ++#define GOP_REGDMA_INTERVAL_START 0x0200 //infinity:0x0200; cedric:0x0300 ++#define GOP_REGDMA_INTERVAL_END 0x4000 //infinity:0x4000; cedirc:0x5000 ++ ++ ++// REG_GOP_02 ++#define GOP_BLINK_DISABLE 0x0000 ++#define GOP_BLINK_ENABLE 0x8000 ++ ++// REG_GOP_05 ++#define GOP_PALETTE_TABLE_ADDRESS_MASK 0x00FF //palette index ++#define GOP_PALETTE_WRITE_ENABLE_MASK 0x0100 ++#define GOP_PALETTE_READ_ENABLE_MASK 0x0200 ++#define GOP_PALETTE_SRAM_CTRL_MASK 0x3000 //0:RIU mode; 1:REGDMA mode; 2,3:for external gop ++#define GOP_PALETTE_SRAM_CTRL_RIU 0x0000 ++#define GOP_PALETTE_SRAM_CTRL_REGDMA 0x1000 ++ ++ ++ ++// REG_GOP_06 ++#define GOP_REGDMA_END 0x0034 ++ ++ ++// REG_GOP_07 ++#define GOP_REGDMA_STR 0x0000 ++ ++ ++// REG_GOP_0F ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++#define GOP_HSYNC_PIPE_DLY_FOR_SC1_OP 0x00A0 ++#define HSYNC_PIPE_DLY_FOR_SC0_2GOP 0x0044 ++ ++// inifinity settings ++#define INIFINITY_GOP_HSYNC_PIPE_DLY 0x0000 ++#define GOP_HSYNC_PIPE_DLY INIFINITY_GOP_HSYNC_PIPE_DLY ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++ ++ ++// REG_GOP_19 ++#define GOP_BURST_LENGTH_MASK 0x1F00 ++#define GOP_BURST_LENGTH_MAX 0x1F00 ++#define GOP_BURST_LENGTH_AUTO 0x0000 ++ ++ ++// REG_GOP_20 ++#define GOP_GWIN_HIGH_PRI_0 0x0000 ++#define GOP_GWIN_HIGH_PRI_1 0x0001 ++ ++// REG_GOP_32 ++#define GOP_STRETCH_HST 0x0000 ++ ++// REG_GOP_34 ++#define GOP_STRETCH_VST 0x0000 ++ ++// REG_GOP_35 ++#define GOP_STRETCH_HRATIO 0x1000 ++ ++// REG_GOP_36 ++#define GOP_STRETCH_VRATIO 0x1000 ++ ++// REG_GOP_38 ++#define GOP_STRETCH_HINI 0x0000 ++ ++// REG_GOP_39 ++#define GOP_STRETCH_VINI 0x0000 ++ ++// REG_GOP_7E ++//#define GOP_GOPG0_MUX_MASK 0x0007 ++//#define GOP_GOPG0_MUX_4G 0x0000 ++//#define GOP_GOPG0_MUX_2G 0x0001 ++ ++//#define GOP_Layer0_MUX_MASK 0x0007 ++//#define GOP_Layer0_Sel_GOP0 0x0000 ++//#define GOP_Layer0_Sel_GOP1 0x0001 ++//#define GOP_Layer0_Sel_GOP2 0x0002 ++//#define GOP_Layer0_Sel_GOP3 0x0003 ++//#define GOP_Layer0_Sel_GOP_Null 0x0004 ++ ++//#define GOP_Layer1_MUX_MASK (0x0007)<<3 ++//#define GOP_Layer1_Sel_GOP0 (0x0000)<<3 ++//#define GOP_Layer1_Sel_GOP1 (0x0001)<<3 ++//#define GOP_Layer1_Sel_GOP2 (0x0002)<<3 ++//#define GOP_Layer1_Sel_GOP3 (0x0003)<<3 ++//#define GOP_Layer1_Sel_GOP_Null (0x0004)<<3 ++ ++//#define GOP_Layer2_MUX_MASK (0x0007)<<6 ++//#define GOP_Layer2_Sel_GOP0 (0x0000)<<6 ++//#define GOP_Layer2_Sel_GOP1 (0x0001)<<6 ++//#define GOP_Layer2_Sel_GOP2 (0x0002)<<6 ++//#define GOP_Layer2_Sel_GOP3 (0x0003)<<6 ++//#define GOP_Layer2_Sel_GOP_Null (0x0004)<<6 ++ ++//#define GOP_Layer3_MUX_MASK (0x0007)<<9 ++//#define GOP_Layer3_Sel_GOP0 (0x0000)<<9 ++//#define GOP_Layer3_Sel_GOP1 (0x0001)<<9 ++//#define GOP_Layer3_Sel_GOP2 (0x0002)<<9 ++//#define GOP_Layer3_Sel_GOP3 (0x0003)<<9 ++//#define GOP_Layer3_Sel_GOP_Null (0x0004)<<9 ++ ++// REG_GOP_7F ++#define GOP_BANK_G0_0 0x0000 ++#define GOP_BANK_G0_1 0x0001 ++#define GOP_BANK_G1_0 0x0003 ++#define GOP_BANK_G1_1 0x0004 ++#define GOP_BANK_G2_0 0x0006 ++#define GOP_BANK_G2_1 0x0007 ++#define GOP_BANK_G3_0 0x0009 ++#define GOP_BANK_G3_1 0x000A ++#define GOP_BANK_GPD 0x0006 ++ ++#define GOP_BANK_DOUBLE_WR 0x0100 ++#define GOP_BANK_FORCE_WR 0x0200 ++ ++#define GOP_BANK_DOUBLE_WR_G0 0x0400 ++#define GOP_BANK_DOUBLE_WR_G1 0x0403 ++#define GOP_BANK_DOUBLE_WR_G2 0x0406 ++#define GOP_BANK_DOUBLE_WR_G3 0x0409 ++#define GOP_BANK_DOUBLE_WR_MSK 0x0400 ++#define GOP_BANK_SEL_MSK 0x000F ++ ++#define GOP_BANK_GOP0_WR_ACK_MSK 0x1000 ++#define GOP_BANK_GOP1_WR_ACK_MSK 0x2000 ++#define GOP_BANK_GOP2_WR_ACK_MSK 0x4000 ++ ++// GOP0 Bank 1 ++// REG_GOP_00 ++#define GOP0_GWin0_Enable 0x0001 ++#define GOP_PIXEL_ALPHA_EN 0x4000 ++#define GOP_CONSTANT_ALPHA_EN 0x0000 ++#define GOP_ALPHA_MASK 0x4000 +diff --git a/drivers/mstar/fb1/infinity3/gop1/mdrv_gop1.c b/drivers/mstar/fb1/infinity3/gop1/mdrv_gop1.c +new file mode 100644 +index 00000000..8b2651e2 +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/gop1/mdrv_gop1.c +@@ -0,0 +1,764 @@ ++#include "mdrv_gop1.h" ++ ++#define PARSING_FB_FORMAT(x)(\ ++ x == _8Bit_Palette ? "Palette_I8": \ ++ x == RGB565 ? "RGB565" : \ ++ x == ARGB4444 ? "ARGB4444" : \ ++ x == ARGB8888 ? "ARGB8888" : \ ++ x == ARGB1555 ? "ARGB1555" : \ ++ x == UV8Y8 ? "UV8Y8" : \ ++ "Format_Not_Support") ++ ++#define PARSING_ALPHA_TYPE(x)(\ ++ x == 0 ? "PIXEL_ALPHA": \ ++ x == 1 ? "CONST_ALPHA": \ ++ "Wrong_Alpha_Type") ++ ++ ++void GOP1_SwitchSubBank(int subbank) ++{ ++ unsigned long GOP_Reg_Base=0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ if ((subbank>=0)&&(subbank<=2)) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,subbank); ++ GOP1DBG( "[GOP1]%s: Switch to Subbank %d\n",__func__,subbank); ++ } ++ else ++ GOP1DBG( "[GOP1]%s: Wrong Subbank %d\n",__func__,subbank); ++} ++ ++void GOP1_Pan_Display(int Screen, U32 FB_Start_Addr ) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U32 s32BuffAddr = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ int wait_count = 0; ++ ++ // 1. Pan display works by changing framebuffer start address ++ ++ ++ GOP1DBG ("[GOP1]%s: in, addr=0x%x \n",__func__,FB_Start_Addr); ++ ++ /// GOP0_1 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ // GOP fetch framebuffer information ++ // set the starting address for showing by GOP ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS; //128-bit unit = 16 bytes ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); //Ring block start Low address 0x21:16 ++ s32BuffAddr = s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); //Ring block start Hi address 0x22:6, page number ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ while((INREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_BANK_GOP1_WR_ACK_MSK)!=0))//wait double buffer write ack ++ { ++ wait_count++; ++ msleep(3); ++ if(wait_count>10) ++ { ++ break; ++ } ++ } ++ ++ GOP1DBG ("[GOP1]%s: out \n",__func__); ++} ++ ++void GOP1_Setmode( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Hardware Initial ++ // 2. GOP Fetch Framebuffer Information ++ // 3. GOP Display Settings ++ ++ ++ //GOP1DBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ GOP1DBG ("[GOP1]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOP1DBG ("[GOP1]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOP1DBG ("[GOP1]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOP1DBG ("[GOP1]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOP1DBG ("[GOP1]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV);//reset ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT);//set Progress mode; mask Hsync; alpha inverse; YUV output ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE);//close blink ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010);//insert fake rdy between hs & valid rdy ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY); //Hsync input pipe delay ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, GOP_BURST_LENGTH_MASK, GOP_BURST_LENGTH_MAX);// set gop dma burst length ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); //Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); //Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); //Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); //Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); //Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); //Stretch V start value ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN);//set gop format; enable gwin; alpha mode initial ++ ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS;//128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); //H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); //H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart);//V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); //V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP1_Setmode_Stretch_H( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut, int StretchRatio) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Hardware initial ++ // 2. GOP fetch framebuffer information ++ // 3. GOP Display Setting ++ // 4. Set Stretch Ratio for GOP Display ++ ++ ++ //GOPDBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ GOP1DBG ("[GOP]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOP1DBG ("[GOP]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOP1DBG ("[GOP]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOP1DBG ("[GOP]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOP1DBG ("[GOP]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ GOP1DBG ("[GOP]%s: FB_StrRatio = [%x]\n",__func__,StretchRatio); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV);//reset ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT);//set Progress mode; mask Hsync; alpha inverse; YUV output ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE);//close blink ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010);//insert fake rdy between hs & valid rdy ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY); //Hsync input pipe delay ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, GOP_BURST_LENGTH_MASK, GOP_BURST_LENGTH_MAX);// set gop dma burst length ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); // Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); // Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); // Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); // Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO/StretchRatio); // Stretch H ratio, val=0x1000/StretchRatio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); // Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); // Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); // Stretch V start value ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN);//set gop format; enable gwin; alpha mode initial ++ ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS; // 128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); // V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++void GOP1_Set_OutFormat(int screen, int byuvoutput) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Change Output Color Format (YUV/RGB) ++ ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ GOP1DBG("[GOP1]%s: screen:%d, byuvoutput:%d\n",__func__, screen, byuvoutput); ++ ++ if(byuvoutput) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_YUVOUT, GOP_YUVOUT); ++ ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP_YUVOUT); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++} ++ ++ ++ ++void GOP1_Set_Constant_Alpha(int screen, int bEn, int alpha) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set Alpha Blending ++ // 2. bEn= 0:pixel alpha; 1: constant alpha; for register: pixel_alpha=1, constant_alpha=0 ++ // 3. alpha: constant alpha value ++ ++ ++ GOP1DBG("[GOP1]%s: screen:%d, bEn:%d, alpha:%x\n",__func__, screen, bEn, alpha); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ // alpha inv ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : GOP_ALPHA_INV), GOP_ALPHA_INV);//set alpha inverse when pixel alpha ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ // constant or pixel alpha ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? GOP_CONSTANT_ALPHA_EN : GOP_PIXEL_ALPHA_EN), GOP_ALPHA_MASK); ++ ++ // alpha value ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_0A, (bEn ? alpha : 0x0000), 0x00FF);//available for constant alpha; set 0 when pixel alpha ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ ++} ++ ++ ++void GOP1_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set RGB Color Key ++ // 2. bEn= 0: disable; 1: enable ++ // 3. u8R: red color value; u8G: green color value; u8B: blue color value ; value range: 0~255 (0x0~0xFF) ++ ++ ++ GOP1DBG("[GOP1]%s: screen:%d, bEn:%d, (R=%x, G=%x, B=%x)\n",__func__, screen, bEn, u8R, u8G, u8B); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ if(bEn) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_RGB_TRANSPARENT_COLOR_ENABLE, GOP_RGB_TRANSPARENT_COLOR_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_24, (u8B|(u8G<<8))); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_25, u8R, 0x00FF); ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_RGB_TRANSPARENT_COLOR_DISABLE, GOP_RGB_TRANSPARENT_COLOR_MASK); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP1_Set_PipeDelay(int screen, int delay) ++{ ++ U16 pipe_delay = delay; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set Pipe Delay ++ ++ ++ GOP1DBG("[GOP1]%s: screen:%d, delay:%d\n",__func__, screen, delay); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F, pipe_delay); ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++} ++ ++void GOP1_Set_Palette_RIU(int screen, int u8Index, int u8A, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base = 0; ++ ++ // 1. GOP Set Palette by RIU Mode ++ // 2. GOP Palette SRAM Clock should be opened ++ // 3. Set Force Write ++ // 4. Set RIU Mode ++ // 5. Set Palette Index, A, R, G, B Values ++ // 6. Trigger Palette Write ++ // 7. Close Force Write ++ ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ //set force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_BANK_FORCE_WR , GOP_BANK_FORCE_WR); ++ ++ //set RIU mode ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, GOP_PALETTE_SRAM_CTRL_RIU , GOP_PALETTE_SRAM_CTRL_MASK); ++ ++ //set palette value ++ OUTREG16(GOP_Reg_Base+REG_GOP_03, u8G<<8|u8B); ++ OUTREG16(GOP_Reg_Base+REG_GOP_04, u8A<<8|u8R); ++ ++ //set palette index ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, u8Index , GOP_PALETTE_TABLE_ADDRESS_MASK); ++ ++ //write trigger ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0100 , GOP_PALETTE_WRITE_ENABLE_MASK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0000 , GOP_PALETTE_WRITE_ENABLE_MASK); ++ ++ //close force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0x0000 , GOP_BANK_FORCE_WR); ++ ++} ++ ++void GOP1_Set_Outputmode(int Screen, int Panel_Width, int Panel_Height,U32 FB_Start_Addr, U32 Pixel_Format, U16 Bytes_Per_Pixel) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Set Output Mode ++ // 2. GOP Fetch Framebuffer Information ++ // 3. GOP Display Settings ++ ++ GOP1DBG ("[GOP1]%s\n",__func__); ++ GOP1DBG ("[GOP1]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOP1DBG ("[GOP1]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOP1DBG ("[GOP1]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOP1DBG ("[GOP1]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOP1DBG ("[GOP1]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, DISPLAY_Format, GWIN_FMT_MASK); ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS;//128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size, use for scroll; useless in I1, I3 ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); //H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); //H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart);//V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); //V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP1_Set_Enable_GWIN(int screen, unsigned char bEn) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ unsigned char enGOP = bEn; ++ unsigned long GOP_Reg_DB = 0x0400; ++ ++ // 1. GOP Set GWIN Enable/Disable ++ ++ GOP1DBG( "[GOP1]%s: Set enable_GOP = [%d]\n",__func__,enGOP); ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ // enable/disable gwin ++ if(enGOP) ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, enGOP, GOP0_GWin0_Enable); ++ else ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP0_GWin0_Enable); ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP1_Get_Enable_GWIN(int screen, unsigned char *bEn) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ ++ // 1. GOP Get GWIN Enable/Disable ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP0_GWin0_Enable)) ++ { ++ *bEn = 1; ++ } ++ else ++ { ++ *bEn = 0; ++ } ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ GOP1DBG( "[GOP1]%s: Get enable_GOP = [%d]\n",__func__,enGOP); ++ ++} ++ ++void GOP1_Get_Alpha(int screen, int *alpha_type, int *alpha_val) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ ++ // 1. GOP Get Alpha Blending ++ // 2. alpha_type= 0:pixel_alpha; 1: constant_alpha; for register: pixel_alpha=1, constant_alpha=0 ++ // 3. alpha_val: constant alpha value ++ ++ // alpha info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ // constant or pixel alpha ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_PIXEL_ALPHA_EN)==GOP_PIXEL_ALPHA_EN) ++ *alpha_type = 0; //pixel_alpha ++ else ++ *alpha_type = 1; //constant_alpha ++ ++ // alpha value ++ *alpha_val = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_0A, 0x00FF); ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ GOP1DBG( "[GOP1]%s: Alpha_type = [%s], Alpha_value = [%d]\n",__func__,PARSING_ALPHA_TYPE(*alpha_type),*alpha_val); ++ ++} ++ ++void GOP1_Get_Color_Key(int screen, int *bEn, int *u8R, int *u8G, int *u8B) ++{ ++ unsigned long GOP_Reg_Base; ++ ++ // 1. GOP Get RGB Color Key ++ // 2. bEn= 0: disable; 1: enable ++ // 3. u8R: red color value; u8G: green color value; u8B: blue color value ; value range: 0~255 (0x0~0xFF) ++ ++ // colorkey setting is in GOP00 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP10_PA; ++ ++ // enable/disable ++ *bEn = (INREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0800)>>11); ++ ++ // colorkey value ++ *u8R = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_25,0x00FF); ++ *u8G = (unsigned char)(INREGMSK16(GOP_Reg_Base+REG_GOP_24,0xFF00)>>8); ++ *u8B = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_24,0x00FF); ++ ++ GOP1DBG("[GOP1]%s: screen:%d, bEn:%d, (R=%x, G=%x, B=%x)\n",__func__, screen, *bEn, *u8R, *u8G, *u8B); ++ ++} +diff --git a/drivers/mstar/fb1/infinity3/gop1/mdrv_gop1.h b/drivers/mstar/fb1/infinity3/gop1/mdrv_gop1.h +new file mode 100644 +index 00000000..e4672105 +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/gop1/mdrv_gop1.h +@@ -0,0 +1,204 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_gop.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#include ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#include "gop_c2_reg.h" ++ ++#define GOP1_DEBUG 0 ++#if (GOP1_DEBUG==1) ++#define GOP1DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOP1DBG(fmt, arg...) ++#endif ++ ++#define BK_REG(reg) ((reg) * 4) ++ ++/* ---------------------------------------------------------------------------- ++ * GOP_OFFSET ++ * ---------------------------------------------------------------------------- ++ */ ++#define REG_GOP_00 BK_REG(0x00) ++#define REG_GOP_01 BK_REG(0x01) ++#define REG_GOP_02 BK_REG(0x02) ++#define REG_GOP_03 BK_REG(0x03) ++#define REG_GOP_04 BK_REG(0x04) ++#define REG_GOP_05 BK_REG(0x05) ++#define REG_GOP_06 BK_REG(0x06) ++#define REG_GOP_07 BK_REG(0x07) ++#define REG_GOP_08 BK_REG(0x08) ++#define REG_GOP_09 BK_REG(0x09) ++#define REG_GOP_0A BK_REG(0x0A) ++#define REG_GOP_0B BK_REG(0x0B) ++#define REG_GOP_0C BK_REG(0x0C) ++#define REG_GOP_0D BK_REG(0x0D) ++#define REG_GOP_0E BK_REG(0x0E) ++#define REG_GOP_0F BK_REG(0x0F) ++ ++#define REG_GOP_10 BK_REG(0x10) ++#define REG_GOP_11 BK_REG(0x11) ++#define REG_GOP_12 BK_REG(0x12) ++#define REG_GOP_13 BK_REG(0x13) ++#define REG_GOP_14 BK_REG(0x14) ++#define REG_GOP_15 BK_REG(0x15) ++#define REG_GOP_16 BK_REG(0x16) ++#define REG_GOP_17 BK_REG(0x17) ++#define REG_GOP_18 BK_REG(0x18) ++#define REG_GOP_19 BK_REG(0x19) ++#define REG_GOP_1A BK_REG(0x1A) ++#define REG_GOP_1B BK_REG(0x1B) ++#define REG_GOP_1C BK_REG(0x1C) ++#define REG_GOP_1D BK_REG(0x1D) ++#define REG_GOP_1E BK_REG(0x1E) ++#define REG_GOP_1F BK_REG(0x1F) ++ ++#define REG_GOP_20 BK_REG(0x20) ++#define REG_GOP_21 BK_REG(0x21) ++#define REG_GOP_22 BK_REG(0x22) ++#define REG_GOP_23 BK_REG(0x23) ++#define REG_GOP_24 BK_REG(0x24) ++#define REG_GOP_25 BK_REG(0x25) ++#define REG_GOP_26 BK_REG(0x26) ++#define REG_GOP_27 BK_REG(0x27) ++#define REG_GOP_28 BK_REG(0x28) ++#define REG_GOP_29 BK_REG(0x29) ++#define REG_GOP_2A BK_REG(0x2A) ++#define REG_GOP_2B BK_REG(0x2B) ++#define REG_GOP_2C BK_REG(0x2C) ++#define REG_GOP_2D BK_REG(0x2D) ++#define REG_GOP_2E BK_REG(0x2E) ++#define REG_GOP_2F BK_REG(0x2F) ++ ++#define REG_GOP_30 BK_REG(0x30) ++#define REG_GOP_31 BK_REG(0x31) ++#define REG_GOP_32 BK_REG(0x32) ++#define REG_GOP_33 BK_REG(0x33) ++#define REG_GOP_34 BK_REG(0x34) ++#define REG_GOP_35 BK_REG(0x35) ++#define REG_GOP_36 BK_REG(0x36) ++#define REG_GOP_37 BK_REG(0x37) ++#define REG_GOP_38 BK_REG(0x38) ++#define REG_GOP_39 BK_REG(0x39) ++#define REG_GOP_3A BK_REG(0x3A) ++#define REG_GOP_3B BK_REG(0x3B) ++#define REG_GOP_3C BK_REG(0x3C) ++#define REG_GOP_3D BK_REG(0x3D) ++#define REG_GOP_3E BK_REG(0x3E) ++#define REG_GOP_3F BK_REG(0x3F) ++ ++#define REG_GOP_40 BK_REG(0x40) ++#define REG_GOP_41 BK_REG(0x41) ++#define REG_GOP_42 BK_REG(0x42) ++#define REG_GOP_43 BK_REG(0x43) ++#define REG_GOP_44 BK_REG(0x44) ++#define REG_GOP_45 BK_REG(0x45) ++#define REG_GOP_46 BK_REG(0x46) ++#define REG_GOP_47 BK_REG(0x47) ++#define REG_GOP_48 BK_REG(0x48) ++#define REG_GOP_49 BK_REG(0x49) ++#define REG_GOP_4A BK_REG(0x4A) ++#define REG_GOP_4B BK_REG(0x4B) ++#define REG_GOP_4C BK_REG(0x4C) ++#define REG_GOP_4D BK_REG(0x4D) ++#define REG_GOP_4E BK_REG(0x4E) ++#define REG_GOP_4F BK_REG(0x4F) ++ ++#define REG_GOP_50 BK_REG(0x50) ++#define REG_GOP_51 BK_REG(0x51) ++#define REG_GOP_52 BK_REG(0x52) ++#define REG_GOP_53 BK_REG(0x53) ++#define REG_GOP_54 BK_REG(0x54) ++#define REG_GOP_55 BK_REG(0x55) ++#define REG_GOP_56 BK_REG(0x56) ++#define REG_GOP_57 BK_REG(0x57) ++#define REG_GOP_58 BK_REG(0x58) ++#define REG_GOP_59 BK_REG(0x59) ++#define REG_GOP_5A BK_REG(0x5A) ++#define REG_GOP_5B BK_REG(0x5B) ++#define REG_GOP_5C BK_REG(0x5C) ++#define REG_GOP_5D BK_REG(0x5D) ++#define REG_GOP_5E BK_REG(0x5E) ++#define REG_GOP_5F BK_REG(0x5F) ++ ++#define REG_GOP_60 BK_REG(0x60) ++#define REG_GOP_61 BK_REG(0x61) ++#define REG_GOP_62 BK_REG(0x62) ++#define REG_GOP_63 BK_REG(0x63) ++#define REG_GOP_64 BK_REG(0x64) ++#define REG_GOP_65 BK_REG(0x65) ++#define REG_GOP_66 BK_REG(0x66) ++#define REG_GOP_67 BK_REG(0x67) ++#define REG_GOP_68 BK_REG(0x68) ++#define REG_GOP_69 BK_REG(0x69) ++#define REG_GOP_6A BK_REG(0x6A) ++#define REG_GOP_6B BK_REG(0x6B) ++#define REG_GOP_6C BK_REG(0x6C) ++#define REG_GOP_6D BK_REG(0x6D) ++#define REG_GOP_6E BK_REG(0x6E) ++#define REG_GOP_6F BK_REG(0x6F) ++ ++#define REG_GOP_70 BK_REG(0x70) ++#define REG_GOP_71 BK_REG(0x71) ++#define REG_GOP_72 BK_REG(0x72) ++#define REG_GOP_73 BK_REG(0x73) ++#define REG_GOP_74 BK_REG(0x74) ++#define REG_GOP_75 BK_REG(0x75) ++#define REG_GOP_76 BK_REG(0x76) ++#define REG_GOP_77 BK_REG(0x77) ++#define REG_GOP_78 BK_REG(0x78) ++#define REG_GOP_79 BK_REG(0x79) ++#define REG_GOP_7A BK_REG(0x7A) ++#define REG_GOP_7B BK_REG(0x7B) ++#define REG_GOP_7C BK_REG(0x7C) ++#define REG_GOP_7D BK_REG(0x7D) ++#define REG_GOP_7E BK_REG(0x7E) ++#define REG_GOP_7F BK_REG(0x7F) ++ ++//global functions ++void GOP1_SwitchSubBank(int subbank); ++void GOP1_Setmode(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++void GOP1_Setmode_Stretch_H(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut, int StretchRatio); ++void GOP1_Pan_Display(int Screen, U32 FB_Start_Addr); ++void GOP1_Set_OutFormat(int screen, int byuvoutput); ++void GOP1_Set_Constant_Alpha(int screen, int bEn, int alpha); ++void GOP1_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B); ++void GOP1_Set_PipeDelay(int screen, int delay); ++void GOP1_Set_Palette_RIU(int screen, int u8Index, int u8A, int u8R, int u8G, int u8B); ++void GOP1_Set_Outputmode(int Screen, int Panel_Width, int Panel_Height,U32 FB_Start_Addr, U32 Pixel_Format, U16 Bytes_Per_Pixel); ++void GOP1_Set_Enable_GWIN(int screen, unsigned char bEn); ++void GOP1_Get_Enable_GWIN(int screen, unsigned char *bEn); ++void GOP1_Get_Alpha(int screen, int *alpha_type, int *alpha_val); ++void GOP1_Get_Color_Key(int screen, int *bEn, int *u8R, int *u8G, int *u8B); +diff --git a/drivers/mstar/fb1/infinity3/inv_color/mdrv_gop1_inv_color.c b/drivers/mstar/fb1/infinity3/inv_color/mdrv_gop1_inv_color.c +new file mode 100644 +index 00000000..581e37ee +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/inv_color/mdrv_gop1_inv_color.c +@@ -0,0 +1,370 @@ ++#include "mdrv_gop1_inv_color.h" ++ ++void GOP1_invColor_init(void) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ int output_YUV_mode=0x0002; ++ int complementary_color_mode=0x0008; ++ ++ // 1. GOP Set inverse color init settings ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ ++ // set gop output mode YUV ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BASE_SETTINGS, output_YUV_mode, GOP1_invColor_gop_output_mode); ++ ++ // set inverse color mode to complementary color mode ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BASE_SETTINGS, complementary_color_mode, GOP1_invColor_color_mode); ++ ++} ++ ++void GOP1_invColor_Enable(unsigned char bEn) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ ++ // 1. GOP Set inverse color Enable/Disable ++ ++ GOP1_invColor_DBG( "[GOP1_invColor]%s: Set enable_GOP = [%d]\n",__func__,bEn); ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ ++ // enable/disable inverse color ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BASE_SETTINGS, bEn, GOP1_invColor_enable_mask); ++ ++} ++ ++void GOP1_invColor_Set_UpdateMode(unsigned char bMode) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ ++ // 1. GOP Set inverse color update inverse table mode ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ ++ // set inverse color update mode, 1:by cpu, 0:by engine ++ if(bMode) ++ { ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BASE_SETTINGS, GOP1_invColor_update_mode, GOP1_invColor_update_mode); ++ } ++ else ++ { ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BASE_SETTINGS, 0, GOP1_invColor_update_mode); ++ } ++ ++} ++ ++void GOP1_invColor_Set_Y_Threshold(int AE_Y_Thres) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ ++ // 1. GOP Set Y threshold to do inverse color or not ++ ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: Set Y Threshold = [%d]\n",__func__,AE_Y_Thres); ++ ++ // set AE_Y_Thres ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BASE_SETTINGS, (AE_Y_Thres<<8),GOP1_invColor_AE_Y_Threshold_mask); ++ ++} ++ ++void GOP1_invColor_Set_AE_Config(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ int real_blk_width = AE_Blk_Width; // register setting is real_size-1 ++ int AE_Blk_x_num = 0; ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ AE_Blk_x_num = AE_x_res / real_blk_width; //real x blk num ++ ++ // 1. GOP Set AE config ++ ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: reg AE_Blk_Width = [%d]\n",__func__,AE_Blk_Width-1); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: reg AE_Blk_Height = [%d]\n",__func__,AE_Blk_Height-1); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: reg AE_Blk_x_num = [%d]\n",__func__,AE_Blk_x_num-1); ++ ++ // set AE_Blk_Width ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BLK_WIDTH, AE_Blk_Width-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_Height ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BLK_HEIGHT, AE_Blk_Height-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_x_num ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_AE_X_BLK_NUM, (AE_Blk_x_num-1)<<8,GOP1_invColor_AE_X_BLK_NUM_mask); // reg_val=real_size-1 ++ ++} ++ ++void GOP1_invColor_Set_AE_Config_Scaling(int AE_Blk_Width, int AE_Blk_Height, int AE_x_blk_num) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ ++ // 1. GOP Set AE config ++ ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: reg AE_Blk_Width = [%d]\n",__func__,AE_Blk_Width-1); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: reg AE_Blk_Height = [%d]\n",__func__,AE_Blk_Height-1); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: reg AE_x_blk_num = [%d]\n",__func__,AE_x_blk_num-1); ++ ++ // set AE_Blk_Width ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BLK_WIDTH, AE_Blk_Width-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_Height ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BLK_HEIGHT, AE_Blk_Height-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_x_num ++ OUTREGMSK16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_AE_X_BLK_NUM, (AE_x_blk_num-1)<<8,GOP1_invColor_AE_X_BLK_NUM_mask); // reg_val=real_size-1 ++ ++} ++ ++ ++void GOP1_invColor_Set_Crop_Config(int crop_x_cor, int crop_y_cor, int AE_Blk_Width, int AE_Blk_Height, int AE_x_res) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ int real_blk_width = AE_Blk_Width+1; // register setting is real_size-1 ++ int real_blk_height = AE_Blk_Height+1;// register setting is real_size-1 ++ int x_offset=0; ++ int y_offset=0; ++ int invTable_idx_offset=0; ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ // x_offset = crop_x_offset % ae_blk_w ++ x_offset = crop_x_cor % real_blk_width; ++ // y_offset = crop_y_offset % ae_blk_h ++ y_offset = crop_y_cor % real_blk_height; ++ // index offset = floor(crop_y_offset / ae_blk_h) x (reg_blk_num_x_m1+1) + floor (crop_x_offset / ae_blk_w) ++ invTable_idx_offset= (crop_y_cor / real_blk_height)*(AE_x_res / real_blk_width)+(crop_x_cor / real_blk_width); ++ ++ // 1. GOP Set crop config: x_offset, y_offset & index_offset ++ ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: x_offset = [%d]\n",__func__,x_offset); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: y_offset = [%d]\n",__func__,y_offset); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: idx_offset = [%d]\n",__func__,invTable_idx_offset); ++ ++ // set x_offset ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_X_PIX_OFFSET, x_offset); ++ ++ // set y_offset ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_Y_PIX_OFFSET, y_offset); ++ ++ // set invTable_idx_offset ++ OUTREG16(GOP1_invColor_Reg_Base+GOP1_invColor_REG_BLK_INDEX_OFFSET, invTable_idx_offset); ++ ++} ++ ++int GOP1_invColor_Engine_Update_Done(void) ++{ ++ unsigned long GOP1_invColor_Reg_Update = 0; ++ unsigned char bDone=0; ++ ++ GOP1_invColor_Reg_Update=mdrv_BASE_REG_GOP1_invColor_AE_Update_Done; ++ ++ if(INREGMSK16(GOP1_invColor_Reg_Update+GOP1_invColor_REG_AE_Update_Done, GOP1_invColor_AE_Update_Done_mask)!=0) ++ { ++ bDone=1; ++ //if get ready, clear it after read ++ OUTREGMSK16(GOP1_invColor_Reg_Update+GOP1_invColor_REG_AE_Update_Done, 0 , GOP1_invColor_AE_Update_Done_mask); ++ } ++ else ++ { ++ bDone=0; ++ } ++ ++ return bDone; ++} ++ ++int GOP1_invColor_CPU_Upate_InvTable(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res, int AE_y_res) ++{ ++ unsigned long GOP1_invColor_Reg_Base = 0; ++ unsigned char *invTable; ++ unsigned char *invTable_rot; ++ int retry_count=0; ++ int blk_origin_num_x=0; ++ int blk_origin_num_y=0; ++ int total_index_used=0; ++ int reg_index_used=0; ++ int num_invTbl_per_regidx=32; ++ int temp_idx=0; ++ int temp_count=0; ++ int temp_data1=0; ++ int temp_data2=0; ++ int temp_x_idx=0; ++ int temp_y_idx=0; ++ ++ ++ GOP1_invColor_Reg_Base = mdrv_BASE_REG_GOP1_invColor; ++ ++ // 1. Count Needed Settings ++ ++ blk_origin_num_x = AE_x_res / AE_Blk_Width; ++ blk_origin_num_y = AE_y_res / AE_Blk_Height; ++ if((blk_origin_num_x>128)||(blk_origin_num_y>90)) ++ { ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: Error! blk_num too big!!! x_num=%d, y_num=%d\n",__func__,blk_origin_num_x,blk_origin_num_y); ++ return FALSE; ++ } ++ total_index_used = blk_origin_num_x * blk_origin_num_y; ++ reg_index_used = total_index_used / num_invTbl_per_regidx; ++ if((total_index_used % num_invTbl_per_regidx)!=0)// if total_index in use is not 32 align, then reg_idx +1 ++ { ++ reg_index_used++; ++ } ++ ++ //assign memory ++ invTable=kmalloc((reg_index_used*num_invTbl_per_regidx) * sizeof(unsigned char),GFP_KERNEL); ++ if (!invTable) ++ { ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: Error! kmalloc error\n",__func__); ++ return FALSE; ++ } ++ invTable_rot=kmalloc((reg_index_used*num_invTbl_per_regidx) * sizeof(unsigned char),GFP_KERNEL); ++ if (!invTable_rot) ++ { ++ kfree(invTable); ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: Error! kmalloc error\n",__func__); ++ return FALSE; ++ } ++ ++ // 2. Wait Inverse HW Engine write AE Inverse Table Done with Interrupt Trigger and then clean Interrupt ++ ++ while(!GOP1_invColor_Engine_Update_Done()) ++ { ++ mdelay(30); ++ if(retry_count>10) ++ { ++ GOP1_invColor_DBG ("[GOP1_invColor]%s: Error! wait no ack\n",__func__); ++ return FALSE; ++ } ++ retry_count++; ++ } ++ ++ ++ // 3. Read Inverse Table ++ ++ for(temp_idx=0;temp_idx>temp_count)& 0x1); ++ } ++ for(temp_count=0;temp_count<16;temp_count++) ++ { ++ invTable[(temp_idx * num_invTbl_per_regidx)+temp_count+16]= ((temp_data2>>temp_count)& 0x1); ++ } ++ } ++ ++ // 4. Do Transpose for Rotate Case ++ ++ for(temp_y_idx=0;temp_y_idx ++#include ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#define GET_REG8_ADDR_GOP1_invColor(x, y) (x+(y)*2) ++#define GET_REG16_ADDR_GOP1_invColor(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define BASE_REG_RIU_PA_GOP1_invColor (0x1F000000) ++ ++//GOP Base register defines ++ ++//inverse color base address ++#define mdrv_BASE_REG_GOP1_invColor GET_REG16_ADDR_GOP1_invColor(BASE_REG_RIU_PA_GOP1_invColor, (0x121A00/2)) ++ ++//inverse color engine update done flag address ++#define mdrv_BASE_REG_GOP1_invColor_AE_Update_Done GET_REG16_ADDR_GOP1_invColor(BASE_REG_RIU_PA_GOP1_invColor, (0x121800/2)) ++#define GOP1_invColor_REG_AE_Update_Done BK_REG_GOP1_invColor(0x0A) ++#define GOP1_invColor_AE_Update_Done_mask 0x0080 ++ ++#define BK_REG_GOP1_invColor(reg) ((reg) * 4) ++ ++//-------------------------------------------------------------------------------------------------- ++// Defines ++//-------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------ ++// inverse color settings for GOP1 ++//------------------------------------------------------------------------------ ++ ++#define GOP1_invColor_REG_BASE_SETTINGS BK_REG_GOP1_invColor(0x3E) ++#define GOP1_invColor_enable_mask 0x0001 // 1:enable, 0:disable ++#define GOP1_invColor_gop_output_mode 0x0002 // 1:YUV, 0:RGB ++#define GOP1_invColor_update_mode 0x0004 // 1:by cpu, 0:by engine ++#define GOP1_invColor_color_mode 0x0008 // 1.complementary color, 0:user define ++#define GOP1_invColor_AE_Y_Threshold_mask 0xFF00 ++ ++#define GOP1_invColor_REG_USER_COLOR_RG BK_REG_GOP1_invColor(0x3F) ++#define GOP1_invColor_user_color_R_mask 0x00FF ++#define GOP1_invColor_user_color_G_mask 0xFF00 ++ ++#define GOP1_invColor_REG_USER_COLOR_B BK_REG_GOP1_invColor(0x44) ++#define GOP1_invColor_user_color_B_mask 0x00FF ++ ++#define GOP1_invColor_REG_AE_X_BLK_NUM BK_REG_GOP1_invColor(0x44) ++#define GOP1_invColor_AE_X_BLK_NUM_mask 0x7F00 ++ ++#define GOP1_invColor_REG_X_PIX_OFFSET BK_REG_GOP1_invColor(0x45) ++ ++#define GOP1_invColor_REG_Y_PIX_OFFSET BK_REG_GOP1_invColor(0x46) ++ ++#define GOP1_invColor_REG_BLK_INDEX_OFFSET BK_REG_GOP1_invColor(0x47) ++ ++#define GOP1_invColor_REG_BLK_WIDTH BK_REG_GOP1_invColor(0x49) ++ ++#define GOP1_invColor_REG_BLK_HEIGHT BK_REG_GOP1_invColor(0x4A) ++ ++#define GOP1_invColor_REG_SRAM_SETTINGS BK_REG_GOP1_invColor(0x4B) ++#define GOP1_invColor_SRAM_ADDR_mask 0x01FF ++#define GOP1_invColor_SRAM_WRITE_enable 0x0200 ++#define GOP1_invColor_SRAM_READ_enable 0x0400 ++#define GOP1_invColor_SRAM_CPU_UPDATE_DONE 0x0800 ++ ++#define GOP1_invColor_REG_SRAM_WRITE_DATA1 BK_REG_GOP1_invColor(0x4C) ++ ++#define GOP1_invColor_REG_SRAM_WRITE_DATA2 BK_REG_GOP1_invColor(0x4D) ++ ++#define GOP1_invColor_REG_SRAM_READ_DATA1 BK_REG_GOP1_invColor(0x4E) ++ ++#define GOP1_invColor_REG_SRAM_READ_DATA2 BK_REG_GOP1_invColor(0x4F) ++ ++ ++#define GOP1_invColor_DEBUG 0 ++#if (GOP1_invColor_DEBUG==1) ++#define GOP1_invColor_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOP1_invColor_DBG(fmt, arg...) ++#endif ++ ++//global functions ++void GOP1_invColor_init(void); ++void GOP1_invColor_Enable(unsigned char bEn); ++void GOP1_invColor_Set_UpdateMode(unsigned char bMode); ++void GOP1_invColor_Set_Y_Threshold(int AE_Y_Thres); ++void GOP1_invColor_Set_AE_Config(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res); ++void GOP1_invColor_Set_AE_Config_Scaling(int AE_Blk_Width, int AE_Blk_Height, int AE_x_blk_num); ++void GOP1_invColor_Set_Crop_Config(int crop_x_cor, int crop_y_cor, int AE_Blk_Width, int AE_Blk_Height, int AE_x_res); ++int GOP1_invColor_CPU_Upate_InvTable(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res, int AE_y_res); ++void GOP1_invColor_Debug_Mode(void); ++void GOP1_invColor_DebugMode_UpdateInvTable(void); +\ No newline at end of file +diff --git a/drivers/mstar/fb1/infinity3/mdrv_fb1.c b/drivers/mstar/fb1/infinity3/mdrv_fb1.c +new file mode 100644 +index 00000000..dfc47793 +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/mdrv_fb1.c +@@ -0,0 +1,1979 @@ ++ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_general_fb.c ++ * DESCRIPTION For mdrv LinuxBSP Display driver, use frame buffer ++ * architecture ++ * ++ * AUTHOR Chun Fan ++ * ++ * ++ * HISTORY 2008/05/06 initial version ++ * linux/drivers/video/mdrv_general_fb.c ++ * -- mdrv frame buffer device ++ *****************************************************************************/ ++ ++ ++#define mdrv_GEN_FB_C ++ ++#include "mdrv_fb1.h" ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++// update global variables while init/probe ++static void __init mdrvinfinityfb1_updateinfo(void) ++{ ++ static int main_videomemory_size=0; ++ ++ //default settings for Stretch mode ++ genGOPGernelSettings_gop1.u32Width=sg_mdrvinfinityfb1_default_var.xres; ++ genGOPGernelSettings_gop1.u32Height=sg_mdrvinfinityfb1_default_var.yres; ++ genGOPGernelSettings_gop1.enBufferNum=FB_DOUBLE_BUFFER; ++ genGOPGernelSettings_gop1.enStretchH_Ratio=FB_STRETCH_H_RATIO_1; ++ genGOPGernelSettings_gop1.u32DisplayWidth=genGOPGernelSettings_gop1.u32Width*genGOPGernelSettings_gop1.enStretchH_Ratio; ++ genGOPGernelSettings_gop1.u32DisplayHeight=genGOPGernelSettings_gop1.u32Height; ++ ++ //default settings for global structure of fb_var_screeninfo ++ sg_mdrvinfinityfb1_default_var.xres = 0; ++ sg_mdrvinfinityfb1_default_var.yres = 0; ++ sg_mdrvinfinityfb1_default_var.xres_virtual = sg_mdrvinfinityfb1_default_var.xres; ++ sg_mdrvinfinityfb1_default_var.yres_virtual = sg_mdrvinfinityfb1_default_var.yres * (genGOPGernelSettings_gop1.enBufferNum);//double buffer for pan display ++ sg_mdrvinfinityfb1_default_var.width = sg_mdrvinfinityfb1_default_var.xres; ++ sg_mdrvinfinityfb1_default_var.height = sg_mdrvinfinityfb1_default_var.yres; ++ ++ //GWin init, same size as screen ++ genGWinInfo_gop1.u18HStart = 0; ++ genGWinInfo_gop1.u18HEnd = genGWinInfo_gop1.u18HStart + sg_mdrvinfinityfb1_default_var.xres; ++ genGWinInfo_gop1.u18VStart = 0; ++ genGWinInfo_gop1.u18VEnd = genGWinInfo_gop1.u18VStart + sg_mdrvinfinityfb1_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb1_default_var.xres * sg_mdrvinfinityfb1_default_var.yres * ANDROID_BYTES_PER_PIXEL * (genGOPGernelSettings_gop1.enBufferNum)); ++ ++ ++ sg_videomemorysize_gop1 = main_videomemory_size; ++ ++ //default settings for global structure of fb_fix_screeninfo ++ sg_mdrvinfinityfb1_fix.smem_start = sg_G3D_fb2_bus_addr1_gop1; ++ sg_mdrvinfinityfb1_fix.smem_len = sg_videomemorysize_gop1; ++ sg_mdrvinfinityfb1_fix.line_length = sg_mdrvinfinityfb1_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ sg_mdrvinfinityfb1_fix.ypanstep = 1; ++ ++ FB1DBGMORE("[FB1 Driver] updateinfo: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], GOPmemorysize = 0x%x \r\n",sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,(unsigned int)sg_videomemorysize_gop1); ++ ++} ++ ++// update global variables while setting new resolution by ioctl FBIOPUT_VSCREENINFO ++static int mdrvinfinityfb1_infinity_updateinfo_par(unsigned int setWidth,unsigned int setHeight) ++{ ++ ++ static int main_videomemory_size=0; ++ ++ //update settings for global structure of fb_var_screeninfo ++ sg_mdrvinfinityfb1_default_var.xres = setWidth; ++ sg_mdrvinfinityfb1_default_var.yres = setHeight; ++ sg_mdrvinfinityfb1_default_var.xres_virtual = sg_mdrvinfinityfb1_default_var.xres; ++ sg_mdrvinfinityfb1_default_var.yres_virtual = sg_mdrvinfinityfb1_default_var.yres * (genGOPGernelSettings_gop1.enBufferNum);//double buffer for pan display ++ sg_mdrvinfinityfb1_default_var.width = sg_mdrvinfinityfb1_default_var.xres; ++ sg_mdrvinfinityfb1_default_var.height = sg_mdrvinfinityfb1_default_var.yres; ++ ++ //update settings for global structure of Stetch mode ++ genGOPGernelSettings_gop1.u32Width=sg_mdrvinfinityfb1_default_var.xres; ++ genGOPGernelSettings_gop1.u32Height=sg_mdrvinfinityfb1_default_var.yres; ++ genGOPGernelSettings_gop1.u32DisplayWidth=genGOPGernelSettings_gop1.u32Width*genGOPGernelSettings_gop1.enStretchH_Ratio; ++ genGOPGernelSettings_gop1.u32DisplayHeight=genGOPGernelSettings_gop1.u32Height; ++ ++ //GWin init, same size as screen ++ genGWinInfo_gop1.u18HStart = 0; ++ genGWinInfo_gop1.u18HEnd = genGWinInfo_gop1.u18HStart + sg_mdrvinfinityfb1_default_var.xres; ++ genGWinInfo_gop1.u18VStart = 0; ++ genGWinInfo_gop1.u18VEnd = genGWinInfo_gop1.u18VStart + sg_mdrvinfinityfb1_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb1_default_var.xres * sg_mdrvinfinityfb1_default_var.yres * ANDROID_BYTES_PER_PIXEL * (genGOPGernelSettings_gop1.enBufferNum)); ++ ++ // free memory if it has ++ if(sg_videomemorysize_gop1 > 0) ++ { ++ free_dmem(KEY_DMEM_FB1_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop1), ++ sg_pG3D_fb2_vir_addr1_gop1, ++ sg_G3D_fb2_bus_addr1_gop1); ++ } ++ ++ sg_videomemorysize_gop1 = main_videomemory_size; ++ ++ FB1DBG ("[FB1 Driver] updateinfo_par: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], GOPmemorysize = 0x%x \r\n",sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,(unsigned int)sg_videomemorysize_gop1); ++ ++ // allocate new memory ++ if (!(sg_pG3D_fb2_vir_addr1_gop1 = alloc_dmem(KEY_DMEM_FB1_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop1), ++ &sg_G3D_fb2_bus_addr1_gop1))) ++ { ++ FB1DBGERR("[FB1 Driver] Error: updateinfo_par: unable to allocate screen memory\n"); ++ return -ENOMEM; ++ } ++ ++ // prevent initial garbage on screen ; to clean memory ++ memset(CAST_2_IOMEM_CHAR_P sg_pG3D_fb2_vir_addr1_gop1,0, sg_videomemorysize_gop1); ++ ++ //update settings for global structure of fb_fix_screeninfo ++ sg_mdrvinfinityfb1_fix.smem_start = sg_G3D_fb2_bus_addr1_gop1; ++ sg_mdrvinfinityfb1_fix.smem_len = sg_videomemorysize_gop1; ++ sg_mdrvinfinityfb1_fix.line_length = sg_mdrvinfinityfb1_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ FB1DBG("[FB1 Driver] vir=0x%x, phy=0x%x\n", (unsigned int)sg_pG3D_fb2_vir_addr1_gop1, sg_G3D_fb2_bus_addr1_gop1); ++ ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb1_infinity_SetPalette(FB_GOP_PaletteEntry *pPalEntry, int intPalStart,int intPalEnd) ++{ ++ int i = 0; ++ int ret = -1; ++ ++ //open scl0 fclk to load palette ++ if (IS_ERR(gop1_clks[1])) ++ { ++ FB1DBGERR( "[FB1 Driver] Error: SetPalette Fail to get gop fclk of scl!\n" ); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop1_clks[1]); ++ } ++ ++ FB1DBGMORE("Palette value:(B,G,R,A)\n"); ++ ++ //write palette ++ for(i=intPalStart;i<=intPalEnd;i++) ++ { ++ GOP1_Set_Palette_RIU(0, i, pPalEntry[i].BGRA.u8A, pPalEntry[i].BGRA.u8R, pPalEntry[i].BGRA.u8G, pPalEntry[i].BGRA.u8B); ++ ++ //record in global variable ++ stGOPCurrentPalInfo_GOP1[i].BGRA.u8B=pPalEntry[i].BGRA.u8B; ++ stGOPCurrentPalInfo_GOP1[i].BGRA.u8G=pPalEntry[i].BGRA.u8G; ++ stGOPCurrentPalInfo_GOP1[i].BGRA.u8R=pPalEntry[i].BGRA.u8R; ++ stGOPCurrentPalInfo_GOP1[i].BGRA.u8A=pPalEntry[i].BGRA.u8A; ++ FB1DBGMORE("(%d,%d,%d,%d)\n",stGOPCurrentPalInfo_GOP1[i].BGRA.u8B,stGOPCurrentPalInfo_GOP1[i].BGRA.u8G,stGOPCurrentPalInfo_GOP1[i].BGRA.u8R,stGOPCurrentPalInfo_GOP1[i].BGRA.u8A); ++ } ++ ++ //close clk ++ clk_disable_unprepare(gop1_clks[1]); ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb1_set_par(struct fb_info *info) ++{ ++ int ret = 0; ++ FB1DBG( "[FB1 Driver] Test I3!\n" ); ++ ++ //Stretch mode settings, if use back to this to set resolution, it will set to default ++ genGOPGernelSettings_gop1.enStretchH_Ratio=FB_STRETCH_H_RATIO_1; ++ genGOPGernelSettings_gop1.enBufferNum=FB_DOUBLE_BUFFER; ++ ++ ret=mdrvinfinityfb1_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start = sg_mdrvinfinityfb1_fix.smem_start; ++ info->fix.smem_len = sg_mdrvinfinityfb1_fix.smem_len; ++ ++ info->var.width = info->var.xres; ++ info->var.height = info->var.yres; ++ ++ info->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1_gop1); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ //GOP_Setmode(FALSE, 0,sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,sg_G3D_fb2_bus_addr1_gop1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ GOP1_Set_Outputmode(0, sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,sg_G3D_fb2_bus_addr1_gop1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL); ++ ++ return ret; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb1_mmap +++------------------------------------------------------------------------------ ++| DESCRIPTION : memory map function, Let user application can get virtual ++| address to access in user space. need pass in physical address ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| vma | x | x | we use Remap-pfn-range will mark the range VM_IO ++| | | | and VM_RESERVED, and save these information in ++| | | | vma +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb1_mmap(struct fb_info *pinfo, struct vm_area_struct *vma) ++{ ++ size_t size; ++ size = 0; ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: mmap, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if (NULL == pinfo) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: mmap, pinfo is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ if (NULL == vma) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: mmap, vma is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_pgoff += ((sg_G3D_fb2_bus_addr1_gop1 ) >> PAGE_SHIFT); ++ ++ FB1DBG( ++ "[FB1 Driver] mmap vma->vm_start=%x\n vma->vm_end=%x\n vma->vm_pgoff =%x\n", ++ (unsigned int) vma->vm_start, (unsigned int)vma->vm_end , ++ (unsigned int)vma->vm_pgoff); ++ ++ //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ return 0; ++} ++ ++//sw update inverse color's inverse table thread when rotate case happens ++static int mdrvinfinityfb1_SWupdate_InvTable(void *arg) ++{ ++ int ret=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ ++ ret=GOP1_invColor_CPU_Upate_InvTable(genAE_info_gop1.u32AEBlkWidth, ++ genAE_info_gop1.u32AEBlkHeight, ++ genAE_info_gop1.u32AEDisplayWidth, ++ genAE_info_gop1.u32AEDisplayHeight); ++ if(!ret)//if update wrong, break ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: mdrvinfinityfb1_SWupdate_InvTable wrong!\n"); ++ genTreadisError_gop1=1; ++ break; ++ } ++ ++ ++ } ++ ++ return 0; ++ ++} ++ ++static int mdrvinfinityfb1_SWupdate_InvTable_debugmode(void *arg) ++{ ++ ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ ++ GOP1_invColor_DebugMode_UpdateInvTable(); ++ msleep(1000); ++ } ++ ++ return 0; ++ ++} ++ ++ ++//check whether need doing sw update inverse color's inverse table or not ++static void mdrvinfinityfb1_checkInvTable_UpdateMode(void) ++{ ++ int idx=0; ++ int ret; ++ ++ if((genInv_Color_gop1==1) && (genSC_info_gop1.bRotateEn==1)) ++ { ++ idx=1; ++ } ++ else ++ { ++ idx=0; ++ } ++ ++ if(genTreadisError_gop1==1) ++ { ++ pSWupdateInvThread_gop1=NULL; ++ genTreadisError_gop1=0; ++ } ++ ++ if(idx==1)//enable thread ++ { ++ if(pSWupdateInvThread_gop1==NULL) ++ { ++ pSWupdateInvThread_gop1 = kthread_create(mdrvinfinityfb1_SWupdate_InvTable,(void *)&pSWupdateInvThread_gop1,"GOP1_SWupdate_InvColor"); ++ if (IS_ERR(pSWupdateInvThread_gop1)) ++ { ++ ret = PTR_ERR(pSWupdateInvThread_gop1); ++ pSWupdateInvThread_gop1 = NULL; ++ FB1DBGERR("[FB1 Driver] ERROR: mdrvinfinityfb1_checkInvTable_UpdateMode wrong! Create thread fail! ret=%d\n",ret); ++ } ++ else ++ { ++ wake_up_process(pSWupdateInvThread_gop1); ++ } ++ } ++ } ++ else if (idx==0 && (pSWupdateInvThread_gop1!=NULL))//disable thread ++ { ++ kthread_stop(pSWupdateInvThread_gop1); ++ pSWupdateInvThread_gop1 = NULL; ++ } ++ ++} ++ ++ ++ ++// FB Ioctl Functions ++ ++int _MDrv_FBIO_IOC_Get_SUPINFO_GOP1(unsigned long arg) ++{ ++ FB_GOP_SUPINF_CONFIG stCfg; ++ ++ // enable gwin is in GOP01 ++ ++ stCfg.bKeyAlpha = 1; ++ stCfg.bConstAlpha = 1; ++ stCfg.bPixelAlpha = 1; ++ stCfg.bColFmt[COLORFMT_ARGB8888] = 0; ++ stCfg.bColFmt[COLORFMT_RGB565] = 0; ++ stCfg.bColFmt[COLORFMT_YUV422] = 0; ++ stCfg.bColFmt[COLORFMT_I8PALETTE]= 1; ++ stCfg.u32MaxWidth = 1920; ++ stCfg.u32MaxHeight= 1080; ++ ++ if(copy_to_user((FB_GOP_SUPINF_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_SUPINF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_GWIN_GOP1(unsigned long arg) ++{ ++ FB_GOP_GWIN_CONFIG stCfg; ++ ++ stCfg.u18HStart = genGWinInfo_gop1.u18HStart; ++ stCfg.u18HEnd = genGWinInfo_gop1.u18HEnd; ++ stCfg.u18VStart = genGWinInfo_gop1.u18VStart; ++ stCfg.u18VEnd = genGWinInfo_gop1.u18VEnd; ++ ++ if(copy_to_user((FB_GOP_GWIN_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_GWIN_GOP1(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ FB_GOP_GWIN_CONFIG stCfg; ++ unsigned short MIU_BUS = 0x04; ++ unsigned short u16FrameBuffer_Bytes_Per_Pixel = ANDROID_BYTES_PER_PIXEL; ++ unsigned long u32TempVal = 0; ++ unsigned long GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G1; ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: _MDrv_FBIO_IOC_Set_GWIN, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ // gwin info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP11_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(1); ++ } ++ ++ if(copy_from_user(&stCfg, (FB_GOP_GWIN_CONFIG __user *)arg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ genGWinInfo_gop1.u18HStart = stCfg.u18HStart; ++ genGWinInfo_gop1.u18HEnd = stCfg.u18HEnd; ++ genGWinInfo_gop1.u18VStart = stCfg.u18VStart; ++ genGWinInfo_gop1.u18VEnd = stCfg.u18VEnd; ++ ++ // GOP Display Setting, GWIN ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(genGWinInfo_gop1.u18HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(genGWinInfo_gop1.u18HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,genGWinInfo_gop1.u18VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,genGWinInfo_gop1.u18VEnd); // V end line ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP11_PA==mdrv_BASE_REG_GOP10_PA) ++ { ++ GOP1_SwitchSubBank(0); ++ } ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_EnGOP_GOP1(unsigned long arg) ++{ ++ unsigned char enGOP; ++ ++ GOP1_Get_Enable_GWIN(0, &enGOP); ++ ++ //remove check scaler's switch later in I3 ++ if(enGOP && INREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_64,0x0001)) ++ enGOP=1; ++ else ++ enGOP=0; ++ ++ if(copy_to_user((unsigned char __user *)arg, &enGOP, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnGOP_GOP1(unsigned long arg) ++{ ++ unsigned char enGOP; ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: _MDrv_FBIO_IOC_Set_EnGOP, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&enGOP, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] enable GOP=%d \n",enGOP); ++ ++ // record in global variable ++ genGWIN_gop1=enGOP; ++ ++ // this switch will let scaler handle, remove later in I3 ++ // enable/disable gop switch at scaler ++ if(enGOP) ++ OUTREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_64,0x0001,0x0001); ++ else ++ OUTREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_64,0x0000,0x0001); ++ ++ GOP1_Set_Enable_GWIN(0,enGOP); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_Alpha_GOP1(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ int alpha_type = 0; ++ int alpha_value = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // get alpha blending settings from register ++ GOP1_Get_Alpha(0,&alpha_type,&alpha_value); ++ ++ // copy result from register ++ stCfg.bEn = genGOPALPHA_gop1.bEn; ++ stCfg.enAlphaType = (FB_GOP_ALPHA_TYPE)alpha_type; ++ stCfg.u8Alpha = (unsigned char)alpha_value; ++ ++ // record settings in global variables ++ genGOPALPHA_gop1.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA_gop1.u8Alpha=stCfg.u8Alpha; ++ ++ if(copy_to_user((FB_GOP_ALPHA_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Constant_Alpha_GOP1(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: _MDrv_FBIO_IOC_Set_Constant_Alpha, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] Set alpha enable=%d, type=%d, constant alpha value=0x%x \n",(int)stCfg.bEn, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ ++ if(stCfg.bEn) ++ { ++ GOP1_Set_Constant_Alpha(0, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ } ++ else ++ { ++ GOP1_Set_Constant_Alpha(0, CONST_ALPHA, 0);//close alpha blending, let gop always shows ++ } ++ ++ genGOPALPHA_gop1.bEn=stCfg.bEn; ++ genGOPALPHA_gop1.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA_gop1.u8Alpha=stCfg.u8Alpha; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_Color_Key_GOP1(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ int Enable = 0; ++ int Red = 0; ++ int Green = 0; ++ int Blue = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP1_Get_Color_Key(0,&Enable,&Red,&Green,&Blue); ++ ++ // enable/disable ++ stCfg.bEn = (unsigned char)Enable; ++ ++ // colorkey value ++ stCfg.u8R = (unsigned char)Red; ++ stCfg.u8G = (unsigned char)Green; ++ stCfg.u8B = (unsigned char)Blue; ++ ++ genGOPCOLORKEY_gop1.bEn=stCfg.bEn; ++ genGOPCOLORKEY_gop1.u8R=stCfg.u8R; ++ genGOPCOLORKEY_gop1.u8G=stCfg.u8G; ++ genGOPCOLORKEY_gop1.u8B=stCfg.u8B; ++ ++ if(copy_to_user((FB_GOP_COLORKEY_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Color_Key_GOP1(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: _MDrv_FBIO_IOC_Set_Color_Key, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] Set ColorKey enable=%d, R=0x%x, G=0x%x, B=0x%x\n", (int)stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ GOP1_Set_Color_Key(0, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ genGOPCOLORKEY_gop1.bEn=stCfg.bEn; ++ genGOPCOLORKEY_gop1.u8R=stCfg.u8R; ++ genGOPCOLORKEY_gop1.u8G=stCfg.u8G; ++ genGOPCOLORKEY_gop1.u8B=stCfg.u8B; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_imageblit_GOP1(struct fb_info *info,unsigned long arg) ++{ ++ int ret = 0; ++ ++// this ioctl is unused, the same fuction can be accessed by fb_ops -> fb_imageblit ++#if 0 ++ struct fb_image stCfg; ++ int i = 0; ++ ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: _MDrv_FBIO_IOC_imageblit, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&stCfg, (struct fb_image __user *)arg, sizeof(const struct fb_image))) ++ { ++ return -EFAULT; ++ } ++ ++ if (NULL == stCfg.data) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR:in mdrvinfinityfb1_ioctl, fb_image.data is NULL pointer\r\n"); ++ return -EFAULT; ++ } ++ ++ ++ if (stCfg.fg_color>255) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.bg_color>255) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.width>1920) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ if (stCfg.height>1920) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR ) ++ { ++ for(i=0;i<(stCfg.width*stCfg.height);i++) ++ { ++ if(stCfg.data[i]>255) ++ { ++ ret = 1; ++ } ++ } ++ if(ret) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ } ++ ++ FB1DBGMORE( "[FB1 Driver] Imgblit test, dst (x,y)=(%d,%d), width=%d, height=%d, colordepth=%d \n" ,stCfg.dx,stCfg.dy,stCfg.width,stCfg.height,stCfg.depth); ++ ++ sys_imageblit(info,&stCfg); ++#endif ++ ++ return ret; ++} ++ ++int _MDrv_FBIO_IOC_Set_Palette_GOP1(unsigned long arg) ++{ ++ FB_GOP_PaletteEntry stCfg[256]; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_PaletteEntry __user *)arg, sizeof(FB_GOP_PaletteEntry)*256)) ++ { ++ return -EFAULT; ++ } ++ ++ mdrvinfinityfb1_infinity_SetPalette(stCfg,0,255); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_General_Config_GOP1(unsigned long arg) ++{ ++ FB_GOP_RESOLUTION_STRETCH_H_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ stCfg.u32Height = genGOPGernelSettings_gop1.u32Height; ++ stCfg.u32Width = genGOPGernelSettings_gop1.u32Width; ++ stCfg.enBufferNum = genGOPGernelSettings_gop1.enBufferNum; ++ stCfg.u32DisplayHeight = genGOPGernelSettings_gop1.u32DisplayHeight; ++ stCfg.u32DisplayWidth = genGOPGernelSettings_gop1.u32DisplayWidth; ++ stCfg.enStretchH_Ratio = genGOPGernelSettings_gop1.enStretchH_Ratio; ++ ++ if(copy_to_user((FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_General_Config_GOP1(struct fb_info *info,unsigned long arg) ++{ ++ FB_GOP_RESOLUTION_STRETCH_H_CONFIG stCfg; ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ int max_x_res=2560; ++ int max_y_res=2048; ++ int ret = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_RESOLUTION_STRETCH_H_CONFIG __user *)arg, sizeof(FB_GOP_RESOLUTION_STRETCH_H_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] Set General_Config GOP_Width=%d, GOP_Height=%d, Display_Width=%d, Display_Height=%d, Buffer Num=%d, Stretch Ratio=%d\n",(int)stCfg.u32Width,(int)stCfg.u32Height,(int)stCfg.u32DisplayWidth,(int)stCfg.u32DisplayHeight,(int)stCfg.enBufferNum,(int)stCfg.enStretchH_Ratio); ++ ++ ///check variable valid/invalid ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //single/double buffer check ++ if((stCfg.enBufferNum!=FB_SINGLE_BUFFER)&&(stCfg.enBufferNum!=FB_DOUBLE_BUFFER)) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: buffer num should be 1 or 2 !\n "); ++ return -EINVAL; ++ } ++ //stretch ratio check ++ if((stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_1)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_2)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_4)&&(stCfg.enStretchH_Ratio!=FB_STRETCH_H_RATIO_8)) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: stretch H ratio should be 1, 2, 4 or 8 !\n "); ++ return -EINVAL; ++ } ++ //x & y should > 0 ++ if((stCfg.u32Height<1)||(stCfg.u32Width<1)||(stCfg.u32DisplayHeight<1)||(stCfg.u32DisplayWidth<1)) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ //x & y should < 1920 ++ if((stCfg.u32Height>1920)||(stCfg.u32Width>1920)||(stCfg.u32DisplayHeight>1920)||(stCfg.u32DisplayWidth>1920)) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: buffer x or y size should be < 1920 !\n "); ++ return -EINVAL; ++ } ++ //max size for display is 1920*1088 ++ if(((stCfg.u32Height * stCfg.u32Width)>(max_x_res*max_y_res))||((stCfg.u32DisplayHeight* stCfg.u32DisplayWidth)>(max_x_res*max_y_res))) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ //miu alignment ++ if(((stCfg.u32Width % DisplayPerPixel)!=0)||((stCfg.u32DisplayWidth% DisplayPerPixel)!=0)) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ //Stretch H parameter check ++ if((stCfg.u32Width*stCfg.enStretchH_Ratio)!=stCfg.u32DisplayWidth) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: DisplayWidth should = Width * StretchH_Ratio!\n "); ++ return -EINVAL; ++ } ++ //Stretch V parameter check ++ if(stCfg.u32Height != stCfg.u32DisplayHeight) ++ { ++ FB1DBG( "[FB1 Driver] Error: Set_General_Config: DisplayHeight should = Height!\n"); ++ return -EINVAL; ++ } ++ ++ //after checking valid parameter, save to global variable ++ genGOPGernelSettings_gop1.u32Width = stCfg.u32Width; ++ genGOPGernelSettings_gop1.u32Height = stCfg.u32Height; ++ genGOPGernelSettings_gop1.u32DisplayWidth = stCfg.u32DisplayWidth; ++ genGOPGernelSettings_gop1.u32DisplayHeight = stCfg.u32DisplayHeight; ++ genGOPGernelSettings_gop1.enBufferNum = stCfg.enBufferNum; ++ genGOPGernelSettings_gop1.enStretchH_Ratio = stCfg.enStretchH_Ratio; ++ ++ info->var.xres=stCfg.u32Width; ++ info->var.yres=stCfg.u32Height; ++ ++ ret=mdrvinfinityfb1_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start=sg_mdrvinfinityfb1_fix.smem_start; ++ info->fix.smem_len=sg_mdrvinfinityfb1_fix.smem_len; ++ ++ info->var.width=info->var.xres; ++ info->var.height=info->var.yres; ++ ++ info->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1_gop1); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ GOP1_Setmode_Stretch_H(FALSE, 0,sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,sg_G3D_fb2_bus_addr1_gop1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0,(int)genGOPGernelSettings_gop1.enStretchH_Ratio); ++ ++ return ret; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnInvColor_GOP1(unsigned long arg) ++{ ++ unsigned char enInvColor; ++ int ret=0; ++ ++ if (sg_videomemorysize_gop1<1) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: _MDrv_FBIO_IOC_Set_EnInvColor, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&enInvColor, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] enable inverse color=%d \n",enInvColor); ++ ++ // record in global variable ++ genInv_Color_gop1=enInvColor; ++ ++ GOP1_invColor_Enable(enInvColor); ++ ++ //check whether do sw update inverse color ++ mdrvinfinityfb1_checkInvTable_UpdateMode(); ++ ++ if(enInvColor==1) ++ { ++ GOP1_invColor_Debug_Mode(); ++ ++ if(pSWupdateInvDebugThread_gop1==NULL) ++ { ++ pSWupdateInvDebugThread_gop1 = kthread_create(mdrvinfinityfb1_SWupdate_InvTable_debugmode,(void *)&pSWupdateInvDebugThread_gop1,"GOP1_debug_SWupdate_InvColor"); ++ if (IS_ERR(pSWupdateInvDebugThread_gop1)) ++ { ++ ret=PTR_ERR(pSWupdateInvDebugThread_gop1); ++ pSWupdateInvDebugThread_gop1 = NULL; ++ FB1DBGERR("[FB1 Driver] ERROR: debug mode! Create thread fail!%d\n",ret); ++ } ++ else ++ { ++ wake_up_process(pSWupdateInvDebugThread_gop1); ++ } ++ } ++ } ++ else if((enInvColor==0)&&(pSWupdateInvDebugThread_gop1!=NULL)) ++ { ++ kthread_stop(pSWupdateInvDebugThread_gop1); ++ pSWupdateInvDebugThread_gop1 = NULL; ++ } ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_AEinfoConfig_GOP1(unsigned long arg) ++{ ++ FB_GOP_INVCOLOR_AE_CONFIG stAECfg; ++ unsigned long tempcorpAEwidth=0; ++ unsigned long tempcorpAEheight=0; ++ int tempAEblkwidth=0; ++ int tempAEblkheight=0; ++ int tempAEblkxnum=0; ++ ++ if(copy_from_user(&stAECfg, (FB_GOP_INVCOLOR_AE_CONFIG __user *)arg, sizeof(FB_GOP_INVCOLOR_AE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] set AE config, AExres=%d, AEyres=%d, AEblkW=%d, AEblkH=%d\n", ++ (int)stAECfg.u32AEDisplayWidth,(int)stAECfg.u32AEDisplayHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight); ++ ++ // record in global variable ++ genAE_info_gop1.u32AEDisplayWidth = stAECfg.u32AEDisplayWidth; ++ genAE_info_gop1.u32AEDisplayHeight = stAECfg.u32AEDisplayHeight; ++ genAE_info_gop1.u32AEBlkWidth = stAECfg.u32AEBlkWidth; ++ genAE_info_gop1.u32AEBlkHeight = stAECfg.u32AEBlkHeight; ++ ++ // when scaling happens, change AE block size with this scale ++ if(genSC_info_gop1.bScalingEn) ++ { ++ if((genAE_info_gop1.u32AEBlkWidth!=0)&&(genAE_info_gop1.u32AEBlkHeight!=0)&&(genAE_info_gop1.u32AEDisplayWidth!=0)&&(genAE_info_gop1.u32AEDisplayHeight!=0)) ++ { ++ if(genSC_info_gop1.bCropEn)//if do crop, should add crop information to calculate scaling ratio ++ { ++ if(genSC_info_gop1.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempcorpAEwidth=genSC_info_gop1.u32CropYend-genSC_info_gop1.u32CropYstart; ++ tempcorpAEheight=genSC_info_gop1.u32CropXend-genSC_info_gop1.u32CropXstart; ++ tempAEblkwidth=((int)genAE_info_gop1.u32AEBlkWidth*(int)genSC_info_gop1.u32ScalerHeight/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info_gop1.u32AEBlkHeight*(int)genSC_info_gop1.u32ScalerWidth/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info_gop1.u32AEDisplayHeight/(int)genAE_info_gop1.u32AEBlkHeight); ++ GOP1_invColor_Set_AE_Config_Scaling(tempAEblkheight,tempAEblkwidth,tempAEblkxnum); ++ } ++ else ++ { ++ tempcorpAEwidth=genSC_info_gop1.u32CropXend-genSC_info_gop1.u32CropXstart; ++ tempcorpAEheight=genSC_info_gop1.u32CropYend-genSC_info_gop1.u32CropYstart; ++ tempAEblkwidth=((int)genAE_info_gop1.u32AEBlkWidth*(int)genSC_info_gop1.u32ScalerWidth/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info_gop1.u32AEBlkHeight*(int)genSC_info_gop1.u32ScalerHeight/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info_gop1.u32AEDisplayHeight/(int)genAE_info_gop1.u32AEBlkHeight); ++ GOP1_invColor_Set_AE_Config_Scaling(tempAEblkwidth,tempAEblkheight,tempAEblkxnum); ++ } ++ } ++ else// if no crop, calculate the scaling ratio directly ++ { ++ if(genSC_info_gop1.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempAEblkwidth=((int)genAE_info_gop1.u32AEBlkWidth*(int)genSC_info_gop1.u32ScalerHeight/(int)genAE_info_gop1.u32AEDisplayWidth); ++ tempAEblkheight=((int)genAE_info_gop1.u32AEBlkHeight*(int)genSC_info_gop1.u32ScalerWidth/(int)genAE_info_gop1.u32AEDisplayHeight); ++ tempAEblkxnum=((int)genAE_info_gop1.u32AEDisplayHeight/(int)genAE_info_gop1.u32AEBlkHeight); ++ GOP1_invColor_Set_AE_Config_Scaling(tempAEblkheight,tempAEblkwidth,tempAEblkxnum); ++ } ++ else ++ { ++ tempAEblkwidth=((int)genAE_info_gop1.u32AEBlkWidth*(int)genSC_info_gop1.u32ScalerWidth/(int)genAE_info_gop1.u32AEDisplayWidth); ++ tempAEblkheight=((int)genAE_info_gop1.u32AEBlkHeight*(int)genSC_info_gop1.u32ScalerHeight/(int)genAE_info_gop1.u32AEDisplayHeight); ++ tempAEblkxnum=((int)genAE_info_gop1.u32AEDisplayHeight/(int)genAE_info_gop1.u32AEBlkHeight); ++ GOP1_invColor_Set_AE_Config_Scaling(tempAEblkwidth,tempAEblkheight,tempAEblkxnum); ++ } ++ } ++ } ++ else ++ { ++ FB1DBGERR( "[FB1 Driver] Error: _MDrv_FBIO_IOC_Set_AEinfoConfig fail2!!! No AE info\n"); ++ return -EFAULT; ++ } ++ } ++ else//if disable scaling, set original settings ++ { ++ if(genSC_info_gop1.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP1_invColor_Set_AE_Config((int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP1_invColor_Set_AE_Config((int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEDisplayWidth); ++ } ++ } ++ ++ if(genSC_info_gop1.bCropEn)//if crop enable, reset crop information when AE info change ++ { ++ if(genSC_info_gop1.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP1_invColor_Set_Crop_Config((int)genSC_info_gop1.u32CropXstart,(int)genSC_info_gop1.u32CropYstart,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP1_invColor_Set_Crop_Config((int)genSC_info_gop1.u32CropXstart,(int)genSC_info_gop1.u32CropYstart,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEDisplayWidth); ++ } ++ } ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_YThres_GOP1(unsigned long arg) ++{ ++ unsigned long YThres; ++ ++ if(copy_from_user(&YThres, (unsigned long __user *)arg, sizeof(unsigned long))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] set Y threshold=%d \n",(int)YThres); ++ ++ // record in global variable ++ genY_Thres_gop1=YThres; ++ ++ GOP1_invColor_Set_Y_Threshold((int)YThres); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_ScalerinfoConfig_GOP1(unsigned long arg) ++{ ++ FB_GOP_INVCOLOR_SCALER_CONFIG stSclCfg; ++ unsigned long tempcorpAEwidth=0; ++ unsigned long tempcorpAEheight=0; ++ int tempAEblkwidth=0; ++ int tempAEblkheight=0; ++ int tempAEblkxnum=0; ++ int tempAEblkynum=0; ++ ++ if(copy_from_user(&stSclCfg, (FB_GOP_INVCOLOR_SCALER_CONFIG __user *)arg, sizeof(FB_GOP_INVCOLOR_SCALER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB1DBG( "[FB1 Driver] set Scl config, CropEn=%d, ScalingEn=%d, RotateEn=%d\n", ++ (int)stSclCfg.bCropEn,(int)stSclCfg.bScalingEn,(int)stSclCfg.bRotateEn); ++ ++ if((stSclCfg.u32ScalerWidth<1)||(stSclCfg.u32ScalerWidth>1920)) ++ { ++ FB1DBGERR( "[FB1 Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! parameter wrong\n"); ++ return -EFAULT; ++ } ++ if((stSclCfg.u32ScalerHeight<1)||(stSclCfg.u32ScalerHeight>1920)) ++ { ++ FB1DBGERR( "[FB1 Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! parameter wrong\n"); ++ return -EFAULT; ++ } ++ ++ // record in global variable ++ genSC_info_gop1.bCropEn = stSclCfg.bCropEn; ++ genSC_info_gop1.bScalingEn = stSclCfg.bScalingEn; ++ genSC_info_gop1.u32ScalerWidth = stSclCfg.u32ScalerWidth; ++ genSC_info_gop1.u32ScalerHeight= stSclCfg.u32ScalerHeight; ++ genSC_info_gop1.u32CropXstart = stSclCfg.u32CropXstart; ++ genSC_info_gop1.u32CropXend = stSclCfg.u32CropXend; ++ genSC_info_gop1.u32CropYstart = stSclCfg.u32CropYstart; ++ genSC_info_gop1.u32CropYend = stSclCfg.u32CropYend; ++ // rotate will be get from ISP driver ++ //genSC_info_gop1.bRotateEn = stSclCfg.bRotateEn; ++ //genSC_info_gop1.enRotateA = stSclCfg.enRotateA; ++ ++ if(stSclCfg.bCropEn) ++ { ++ if((genAE_info_gop1.u32AEBlkWidth!=0)&&(genAE_info_gop1.u32AEBlkHeight!=0)&&(genAE_info_gop1.u32AEDisplayWidth!=0)&&(genAE_info_gop1.u32AEDisplayHeight!=0)) ++ { ++ if(genSC_info_gop1.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP1_invColor_Set_Crop_Config((int)stSclCfg.u32CropXstart,(int)stSclCfg.u32CropYstart,(int)genAE_info_gop1.u32AEBlkHeight,(int)genAE_info_gop1.u32AEBlkWidth,(int)genAE_info_gop1.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP1_invColor_Set_Crop_Config((int)stSclCfg.u32CropXstart,(int)stSclCfg.u32CropYstart,(int)genAE_info_gop1.u32AEBlkWidth,(int)genAE_info_gop1.u32AEBlkHeight,(int)genAE_info_gop1.u32AEDisplayWidth); ++ } ++ } ++ else ++ { ++ FB1DBGERR( "[FB1 Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! No AE info\n"); ++ return -EFAULT; ++ } ++ } ++ ++// when scaling happens, change AE block size with this scale ++ if(stSclCfg.bScalingEn) ++ { ++ if((genAE_info_gop1.u32AEBlkWidth!=0)&&(genAE_info_gop1.u32AEBlkHeight!=0)&&(genAE_info_gop1.u32AEDisplayWidth!=0)&&(genAE_info_gop1.u32AEDisplayHeight!=0)) ++ { ++ if(stSclCfg.bCropEn)//if do crop, should add crop information to calculate scaling ratio ++ { ++ if(genSC_info_gop1.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempcorpAEwidth=genSC_info_gop1.u32CropYend-genSC_info_gop1.u32CropYstart; ++ tempcorpAEheight=genSC_info_gop1.u32CropXend-genSC_info_gop1.u32CropXstart; ++ tempAEblkwidth=((int)genAE_info_gop1.u32AEBlkWidth*(int)genSC_info_gop1.u32ScalerHeight/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info_gop1.u32AEBlkHeight*(int)genSC_info_gop1.u32ScalerWidth/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info_gop1.u32AEDisplayHeight/(int)genAE_info_gop1.u32AEBlkHeight); ++ tempAEblkynum=((int)genAE_info_gop1.u32AEDisplayWidth/(int)genAE_info_gop1.u32AEBlkWidth); ++ if(tempAEblkheight > 0) ++ { ++ while(((genSC_info_gop1.u32ScalerWidth%tempAEblkheight)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkheight++; ++ if(tempAEblkheight>genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info_gop1.u32ScalerWidth%tempAEblkwidth)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkwidth++; ++ if(tempAEblkwidth>genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info_gop1.u32ScalerWidth%tempAEblkheight)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkheight++; ++ if(tempAEblkheight>genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info_gop1.u32ScalerWidth%tempAEblkwidth)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkwidth++; ++ if(tempAEblkwidth>genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop1.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop1.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop1.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++DEVICE_ATTR(gop1info, 0644, gop1info_show, gop1info_store); ++ ++ ++static int mdrvinfinityfb1_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ int clockIdxtemp=0; ++ FB1DBG("[FB1 Driver] in mdrvinfinityfb1_suspend \r\n"); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop1 ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop1_clks[clockIdxtemp]); ++ } ++ } ++ //clk_disable_unprepare(gop_psram_clk); ++ return 0; ++} ++ ++static int mdrvinfinityfb1_resume(struct platform_device *pdev) ++{ ++ //dma_addr_t fb2_PHY_ADD_SHOW=0; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ // open all needed clocks ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop1 ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop1_clks[clockIdxtemp])) ++ { ++ FB1DBGERR( "[FB1 Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop1_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop1_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ FB1DBG("[FB1 Driver] mdrvinfinityfb1_resume \r\n"); ++ ++ GOP1_Setmode(TRUE, 0,sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,sg_G3D_fb2_bus_addr1_gop1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ //set palette ++ mdrvinfinityfb1_infinity_SetPalette(stGOPCurrentPalInfo_GOP1,0,255); ++ ++ return 0; ++} ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb1_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : Initialization. Initial HW, fill table, when load module, ++| this function will be called. ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb1_probe(struct platform_device *dev) ++{ ++ struct fb_info *pinfo = NULL; ++ int retval = -ENOMEM; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ if (NULL == dev) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: in mdrvinfinityfb1_prob: dev is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ // open all needed clocks ++ num_parents_clocks_gop1 = of_clk_get_parent_count(dev->dev.of_node); ++ gop1_clks=kzalloc(((sizeof(struct clk *) * num_parents_clocks_gop1)),GFP_KERNEL); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop1 ; clockIdxtemp++) ++ { ++ gop1_clks[clockIdxtemp]= of_clk_get(dev->dev.of_node, clockIdxtemp); ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop1_clks[clockIdxtemp])) ++ { ++ FB1DBGERR( "[FB1 Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop1_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop1_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ // init global variable ++ mdrvinfinityfb1_updateinfo(); ++ ++ pinfo = framebuffer_alloc(sizeof(struct fb_info), &dev->dev); ++ if (!pinfo) ++ goto err; ++ ++ // copy data for register framebuffer ++ pinfo->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1_gop1); ++ pinfo->fbops = &sg_mdrvinfinityfb1_ops; ++ pinfo->var = sg_mdrvinfinityfb1_default_var; ++ pinfo->fix = sg_mdrvinfinityfb1_fix; ++ pinfo->pseudo_palette = pinfo->par; ++ pinfo->par = NULL; ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ ++ // allocate color map ++ // 256 is following to the vfb.c ++ retval = fb_alloc_cmap(&pinfo->cmap, 256, 0); ++ if (retval < 0) ++ goto err1; ++ ++ // register our fb to fbmem.c ++ retval = register_framebuffer(pinfo); ++ if (retval < 0) ++ goto err2; ++ ++ // set data to device ++ platform_set_drvdata(dev, pinfo); ++ ++ // set gop register settings ++ GOP1_Setmode(FALSE, 0,sg_mdrvinfinityfb1_default_var.xres,sg_mdrvinfinityfb1_default_var.yres,sg_G3D_fb2_bus_addr1_gop1,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ // set gop inverse color init settings ++ GOP1_invColor_init(); ++ ++ // set init palette ++ mdrvinfinityfb1_infinity_SetPalette(DefaultPaletteEntry,0,255); ++ ++ // register sysfs ++ ret = device_create_file(&dev->dev, &dev_attr_gop1info); ++ if (ret != 0) ++ { ++ dev_err(&dev->dev, ++ "[FB1 Driver] Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ else ++ { ++ FB1DBGMORE("[FB1 Driver] device attr ok\n"); ++ } ++ ++ return 0; ++ ++err2: ++ fb_dealloc_cmap(&pinfo->cmap); ++err1: ++ framebuffer_release(pinfo); ++err: ++ ++ free_dmem(KEY_DMEM_FB1_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop1), ++ sg_pG3D_fb2_vir_addr1_gop1, ++ sg_G3D_fb2_bus_addr1_gop1); ++ ++ return retval; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb1_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : we free memory, release frame buffer here ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb1_remove(struct platform_device *dev) ++{ ++ struct fb_info *pinfo; ++ int clockIdxtemp=0; ++ pinfo = 0; ++ ++ if (NULL == dev) ++ { ++ FB1DBGERR("[FB1 Driver] ERROR: mdrvinfinityfb1_remove: dev is NULL pointer \n"); ++ return -ENOTTY; ++ } ++ ++ pinfo = platform_get_drvdata(dev); ++ if (pinfo) ++ { ++ unregister_framebuffer(pinfo); ++ ++ free_dmem(KEY_DMEM_FB1_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop1), ++ sg_pG3D_fb2_vir_addr1_gop1, ++ sg_G3D_fb2_bus_addr1_gop1); ++ ++ framebuffer_release(pinfo); ++ } ++ ++ // close all clocks ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop1 ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop1_clks[clockIdxtemp]); ++ } ++ } ++ return 0; ++} ++ ++static int mdrvinfinityfb1_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ dma_addr_t fb2_pandisplay_PHY_ADD_SHOW=0; ++ ++ FB1DBGMORE( "[FB1 Driver]%s: var->yoffset=%x! info->var.height=%x\n ",__func__,var->yoffset,info->var.height); ++ ++ if(genGOPGernelSettings_gop1.enBufferNum==FB_DOUBLE_BUFFER)//double buffer ++ { ++ if (var->yoffset >= info->var.height) ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start + (info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL); ++ ++ FB1DBGMORE( "[FB1 Driver]%s: use buffer 1! Addr=%x\n ",__func__,fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ else ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start; ++ ++ FB1DBGMORE( "[FB1 Driver]%s: use buffer 0 Addr=%x!\n ",__func__,fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ } ++ else ++ { ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start; ++ ++ FB1DBGMORE( "mdrvinfinityfb_pan_display: use buffer 0 Addr=%x!\n ",fb2_pandisplay_PHY_ADD_SHOW); ++ } ++ ++ GOP1_Pan_Display(0, fb2_pandisplay_PHY_ADD_SHOW); ++ ++ return 0; ++} ++ ++ ++//check var to see if supported by this device, defined for infinity ++static int mdrvinfinityfb1_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ int max_x_res=2560; ++ int max_y_res=2048; ++ ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //MstarFB_ENTER(); ++ ++ if((var->yres<1)||(var->xres<1)) ++ { ++ FB1DBGERR( "[FB1 Driver] Error: fb_check_var: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ if((var->yres * var->xres)>(max_x_res*max_y_res)) ++ { ++ FB1DBGERR( "[FB1 Driver] Error: fb_check_var: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ ++ if((var->xres % DisplayPerPixel)!=0) ++ { ++ FB1DBGERR( "[FB1 Driver] Error: fb_check_var: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++module_platform_driver(sg_mdrvinfinityfb1_driver); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/fb1/infinity3/mdrv_fb1.h b/drivers/mstar/fb1/infinity3/mdrv_fb1.h +new file mode 100644 +index 00000000..052aa043 +--- /dev/null ++++ b/drivers/mstar/fb1/infinity3/mdrv_fb1.h +@@ -0,0 +1,330 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_fb.h ++ * DESCRIPTION ++ * Including some MACRO needed in mdrvfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/mdrvfb.h -- mdrvfb frame buffer device ++ ******************************************************************************/ ++ ++//-------------------------------------------------------------------------------------------------- ++// Includes ++//-------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include //for dma_alloc_coherent ++#include ++#include //seems do not need this ++#include ++#include ++#include ++#include ++#include //access_ok(), and VERIFY_WRITE/READ ++#include //for _IO() macro ++#include ++#include ++#include ++#include //do_gettimeofday() ++#include "gop1/mdrv_gop1.h" ++#include "inv_color/mdrv_gop1_inv_color.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" //for dma_alloc_coherent ++#include ++#include ++#include ++ ++#include "mdrv_fb_io.h" ++#include "mdrv_fb_st.h" ++#include "mdrv_isp_io_st.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Defines ++//-------------------------------------------------------------------------------------------------- ++#define FB1_DEBUG 0 //0 for only error message, 1 for normal debug message, 2 for more message ++ ++#if (FB1_DEBUG==0) ++#define FB1DBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB1DBG(fmt, arg...) ++#define FB1DBGMORE(fmt, arg...) ++#elif (FB1_DEBUG==1) ++#define FB1DBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB1DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB1DBGMORE(fmt, arg...) ++#elif (FB1_DEBUG==2) ++#define FB1DBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB1DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB1DBGMORE(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define FB1DBGERR(fmt, arg...) ++#define FB1DBG(fmt, arg...) ++#define FB1DBGMORE(fmt, arg...) ++#endif ++ ++#define CAST_2_USER_VOID_P (void __user *) ++#define CAST_2_USER_UINT_P (unsigned int __user *) ++#define CAST_2_IOMEM_CHAR_P (u8 __iomem *) ++ ++#define ANDROID_NUMBER_OF_BUFFERS 1 ++#define ANDROID_FB_FORMAT _8Bit_Palette ++#define defult_XRES 0 //init value for xres of fb_var_screeninfo, do not assign value while init ++#define defult_YRES 0 //init value for yres of fb_var_screeninfo, do not assign value while init ++#if (ANDROID_FB_FORMAT == RGB565) ++#define BPX 16 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 2 ++#elif ((ANDROID_FB_FORMAT == ARGB8888) || (ANDROID_FB_FORMAT == ABGR8888)) ++#define BPX 32 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 4 ++#elif (ANDROID_FB_FORMAT == _8Bit_Palette) ++#define BPX 8 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 1 ++#else ++ #ERROR("Not Support") ++#endif ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Functions ++//-------------------------------------------------------------------------------------------------- ++static int mdrvinfinityfb1_ioctl(struct fb_info *info, u32 cmd, unsigned long arg); ++static int mdrvinfinityfb1_mmap(struct fb_info *info, struct vm_area_struct *vma); ++static int mdrvinfinityfb1_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); ++static int mdrvinfinityfb1_check_var(struct fb_var_screeninfo *var, struct fb_info *info); ++static int mdrvinfinityfb1_set_par(struct fb_info *info); ++static int mdrvinfinityfb1_suspend(struct platform_device *pdev,pm_message_t state); ++static int mdrvinfinityfb1_resume(struct platform_device *pdev); ++static int mdrvinfinityfb1_probe(struct platform_device *dev); ++static int mdrvinfinityfb1_remove(struct platform_device *dev); ++ ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++struct clk **gop1_clks; /* clock define, one for palette sram clock, one for scaler fclk1 *///index=1 is scl_fclk ++int num_parents_clocks_gop1 = 0; /* number of clocks*/ ++static void *sg_pG3D_fb2_vir_addr1_gop1 = 0; /* virtual address of frame buffer */ ++static u_long sg_videomemorysize_gop1 = 0; /* frame buffer size */ ++dma_addr_t sg_G3D_fb2_bus_addr1_gop1 = 0; /* physical address of frame buffer */ ++ ++FB_GOP_GWIN_CONFIG genGWinInfo_gop1 ={0}; /* global variable to record gwin information */ ++unsigned char genGWIN_gop1 = 1; /* global variable to record gwin is open or close *///open:1; close:0 ++FB_GOP_ALPHA_CONFIG genGOPALPHA_gop1 ={0}; /* global variable to record alpha blending information */ ++FB_GOP_COLORKEY_CONFIG genGOPCOLORKEY_gop1 ={0}; /* global variable to record color key information */ ++ ++unsigned char genInv_Color_gop1 = 0; /* global variable to record inverse color is open or close *///open:1; close:0 ++FB_GOP_INVCOLOR_AE_CONFIG genAE_info_gop1 ={0}; /* global variable to record AE information */ ++unsigned long genY_Thres_gop1 = 0; /* global variable to record Y Threshold */ ++FB_GOP_INVCOLOR_SCALER_CONFIG genSC_info_gop1 ={0}; /* global variable to record Scaler information */ ++ ++FB_GOP_RESOLUTION_STRETCH_H_CONFIG genGOPGernelSettings_gop1={0}; /* global variable to record Stretch mode information */ ++ ++static struct task_struct *pSWupdateInvThread_gop1=NULL; ++unsigned char genTreadisError_gop1 = 0; ++ ++static struct task_struct *pSWupdateInvDebugThread_gop1=NULL; ++ ++//// {B, G, R, Alpha} ++static FB_GOP_PaletteEntry DefaultPaletteEntry[GOP_PALETTE_ENTRY_NUM] = ++{ ++ {{ 0, 0, 0, 0}}, {{ 0, 0,128, 0}}, {{ 0,128, 0, 0}}, {{ 0,128,128, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0,128, 0}}, {{128,128, 0, 0}}, {{192,192,192, 0}}, ++ {{192,220,192, 0}}, {{240,202,166, 0}}, {{ 0, 32, 64, 0}}, {{ 0, 32, 96, 0}}, ++ {{ 0, 32,128, 0}}, {{ 0, 32,160, 0}}, {{ 0, 32,192, 0}}, {{ 0, 32,224, 0}}, ++ {{ 0, 64, 0, 0}}, {{ 0, 64, 32, 0}}, {{ 0, 64, 64, 0}}, {{ 0, 64, 96, 0}}, ++ {{ 0, 64,128, 0}}, {{ 0, 64,160, 0}}, {{ 0, 64,192, 0}}, {{ 0, 64,224, 0}}, ++ {{ 0, 96, 0, 0}}, {{ 0, 96, 32, 0}}, {{ 0, 96, 64, 0}}, {{ 0, 96, 96, 0}}, ++ {{ 0, 96,128, 0}}, {{ 0, 96,160, 0}}, {{ 0, 96,192, 0}}, {{ 0, 96,224, 0}}, ++ {{ 0,128, 0, 0}}, {{ 0,128, 32, 0}}, {{ 0,128, 64, 0}}, {{ 0,128, 96, 0}}, ++ {{ 0,128,128, 0}}, {{ 0,128,160, 0}}, {{ 0,128,192, 0}}, {{ 0,128,224, 0}}, ++ {{ 0,160, 0, 0}}, {{ 0,160, 32, 0}}, {{ 0,160, 64, 0}}, {{ 0,160, 96, 0}}, ++ {{ 0,160,128, 0}}, {{ 0,160,160, 0}}, {{ 0,160,192, 0}}, {{ 0,160,224, 0}}, ++ {{ 0,192, 0, 0}}, {{ 0,192, 32, 0}}, {{ 0,192, 64, 0}}, {{ 0,192, 96, 0}}, ++ {{ 0,192,128, 0}}, {{ 0,192,160, 0}}, {{ 0,192,192, 0}}, {{ 0,192,224, 0}}, ++ {{ 0,224, 0, 0}}, {{ 0,224, 32, 0}}, {{ 0,224, 64, 0}}, {{ 0,224, 96, 0}}, ++ {{ 0,224,128, 0}}, {{ 0,224,160, 0}}, {{ 0,224,192, 0}}, {{ 0,224,224, 0}}, ++ {{ 64, 0, 0, 0}}, {{ 64, 0, 32, 0}}, {{ 64, 0, 64, 0}}, {{ 64, 0, 96, 0}}, ++ {{ 64, 0,128, 0}}, {{ 64, 0,160, 0}}, {{ 64, 0,192, 0}}, {{ 64, 0,224, 0}}, ++ {{ 64, 32, 0, 0}}, {{ 64, 32, 32, 0}}, {{ 64, 32, 64, 0}}, {{ 64, 32, 96, 0}}, ++ {{ 64, 32,128, 0}}, {{ 64, 32,160, 0}}, {{ 64, 32,192, 0}}, {{ 64, 32,224, 0}}, ++ {{ 64, 64, 0, 0}}, {{ 64, 64, 32, 0}}, {{ 64, 64, 64, 0}}, {{ 64, 64, 96, 0}}, ++ {{ 64, 64,128, 0}}, {{ 64, 64,160, 0}}, {{ 64, 64,192, 0}}, {{ 64, 64,224, 0}}, ++ {{ 64, 96, 0, 0}}, {{ 64, 96, 32, 0}}, {{ 64, 96, 64, 0}}, {{ 64, 96, 96, 0}}, ++ {{ 64, 96,128, 0}}, {{ 64, 96,160, 0}}, {{ 64, 96,192, 0}}, {{ 64, 96,224, 0}}, ++ {{ 64,128, 0, 0}}, {{ 64,128, 32, 0}}, {{ 64,128, 64, 0}}, {{ 64,128, 96, 0}}, ++ {{ 64,128,128, 0}}, {{ 64,128,160, 0}}, {{ 64,128,192, 0}}, {{ 64,128,224, 0}}, ++ {{ 64,160, 0, 0}}, {{ 64,160, 32, 0}}, {{ 64,160, 64, 0}}, {{ 64,160, 96, 0}}, ++ {{ 64,160,128, 0}}, {{ 64,160,160, 0}}, {{ 64,160,192, 0}}, {{ 64,160,224, 0}}, ++ {{ 64,192, 0, 0}}, {{ 64,192, 32, 0}}, {{ 64,192, 64, 0}}, {{ 64,192, 96, 0}}, ++ {{ 64,192,128, 0}}, {{ 64,192,160, 0}}, {{ 64,192,192, 0}}, {{ 64,192,224, 0}}, ++ {{ 64,224, 0, 0}}, {{ 64,224, 32, 0}}, {{ 64,224, 64, 0}}, {{ 64,224, 96, 0}}, ++ {{ 64,224,128, 0}}, {{ 64,224,160, 0}}, {{ 64,224,192, 0}}, {{ 64,224,224, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0, 32, 0}}, {{128, 0, 64, 0}}, {{128, 0, 96, 0}}, ++ {{128, 0,128, 0}}, {{128, 0,160, 0}}, {{128, 0,192, 0}}, {{128, 0,224, 0}}, ++ {{128, 32, 0, 0}}, {{128, 32, 32, 0}}, {{128, 32, 64, 0}}, {{128, 32, 96, 0}}, ++ {{128, 32,128, 0}}, {{128, 32,160, 0}}, {{128, 32,192, 0}}, {{128, 32,224, 0}}, ++ {{128, 64, 0, 0}}, {{128, 64, 32, 0}}, {{128, 64, 64, 0}}, {{128, 64, 96, 0}}, ++ {{128, 64,128, 0}}, {{128, 64,160, 0}}, {{128, 64,192, 0}}, {{128, 64,224, 0}}, ++ {{128, 96, 0, 0}}, {{128, 96, 32, 0}}, {{128, 96, 64, 0}}, {{128, 96, 96, 0}}, ++ {{128, 96,128, 0}}, {{128, 96,160, 0}}, {{128, 96,192, 0}}, {{128, 96,224, 0}}, ++ {{128,128, 0, 0}}, {{128,128, 32, 0}}, {{128,128, 64, 0}}, {{128,128, 96, 0}}, ++ {{128,128,128, 0}}, {{128,128,160, 0}}, {{128,128,192, 0}}, {{128,128,224, 0}}, ++ {{128,160, 0, 0}}, {{128,160, 32, 0}}, {{128,160, 64, 0}}, {{128,160, 96, 0}}, ++ {{128,160,128, 0}}, {{128,160,160, 0}}, {{128,160,192, 0}}, {{128,160,224, 0}}, ++ {{128,192, 0, 0}}, {{128,192, 32, 0}}, {{128,192, 64, 0}}, {{128,192, 96, 0}}, ++ {{128,192,128, 0}}, {{128,192,160, 0}}, {{128,192,192, 0}}, {{128,192,224, 0}}, ++ {{128,224, 0, 0}}, {{128,224, 32, 0}}, {{128,224, 64, 0}}, {{128,224, 96, 0}}, ++ {{128,224,128, 0}}, {{128,224,160, 0}}, {{128,224,192, 0}}, {{128,224,224, 0}}, ++ {{192, 0, 0, 0}}, {{192, 0, 32, 0}}, {{192, 0, 64, 0}}, {{192, 0, 96, 0}}, ++ {{192, 0,128, 0}}, {{192, 0,160, 0}}, {{192, 0,192, 0}}, {{192, 0,224, 0}}, ++ {{192, 32, 0, 0}}, {{192, 32, 32, 0}}, {{192, 32, 64, 0}}, {{192, 32, 96, 0}}, ++ {{192, 32,128, 0}}, {{192, 32,160, 0}}, {{192, 32,192, 0}}, {{192, 32,224, 0}}, ++ {{192, 64, 0, 0}}, {{192, 64, 32, 0}}, {{192, 64, 64, 0}}, {{192, 64, 96, 0}}, ++ {{192, 64,128, 0}}, {{192, 64,160, 0}}, {{192, 64,192, 0}}, {{192, 64,224, 0}}, ++ {{192, 96, 0, 0}}, {{192, 96, 32, 0}}, {{192, 96, 64, 0}}, {{192, 96, 96, 0}}, ++ {{192, 96,128, 0}}, {{192, 96,160, 0}}, {{192, 96,192, 0}}, {{192, 96,224, 0}}, ++ {{192,128, 0, 0}}, {{192,128, 32, 0}}, {{192,128, 64, 0}}, {{192,128, 96, 0}}, ++ {{192,128,128, 0}}, {{192,128,160, 0}}, {{192,128,192, 0}}, {{192,128,224, 0}}, ++ {{192,160, 0, 0}}, {{192,160, 32, 0}}, {{192,160, 64, 0}}, {{192,160, 96, 0}}, ++ {{192,160,128, 0}}, {{192,160,160, 0}}, {{192,160,192, 0}}, {{192,160,224, 0}}, ++ {{192,192, 0, 0}}, {{192,192, 32, 0}}, {{192,192, 64, 0}}, {{192,192, 96, 0}}, ++ {{192,192,128, 0}}, {{192,192,160, 0}}, {{240,251,255, 0}}, {{164,160,160, 0}}, ++ {{128,128,128, 0}}, {{ 0, 0,255, 0}}, {{ 0,255, 0, 0}}, {{ 0,255,255, 0}}, ++ {{255, 0, 0, 0}}, {{255, 0,255, 0}}, {{255,255, 0, 0}}, {{255,255,255, 0}} ++ }; ++ ++ ++FB_GOP_PaletteEntry stGOPCurrentPalInfo_GOP1[GOP_PALETTE_ENTRY_NUM]={}; ++ ++ ++static const char* KEY_DMEM_FB1_BUF="FB1_BUFFER"; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct fb_var_screeninfo sg_mdrvinfinityfb1_default_var = ++{ ++ .xres = defult_XRES, /* visible resolution*/ //display x size ++ .yres = defult_YRES, //display y size ++ .xres_virtual = defult_XRES, /* virtual resolution*/ //framebuffer x size ++ .yres_virtual = defult_YRES, //framebuffer y size ++ .xoffset = 0, /* offset from virtual to visible */ ++ .yoffset = 0, ++ ++ .bits_per_pixel = BPX, ++ ++#if (ANDROID_FB_FORMAT == _8Bit_Palette) ++ .grayscale = 0, ++ .transp = {0,0,0}, ++ .red = {0,0,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {0,0,0}, ++ .blue = {0,0,0}, ++#elif (ANDROID_FB_FORMAT == RGB565) //Data: R G B, 5 6 5 ++ .red = {11,5,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {5,6,0}, ++ .blue = {0,5,0}, ++#elif (ANDROID_FB_FORMAT == ARGB8888) //Data: R G B A, 8 8 8 8 ++ .grayscale = 0, ++ .transp = {0,8,0}, ++ .red = {24,8,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {16,8,0}, ++ .blue = {8,8,0}, ++#endif ++ ++ .activate = FB_ACTIVATE_NOW, ++ .height = defult_XRES, /* height of picture in mm */ ++ .width = defult_YRES, /* width of picture in mm */ ++ ++ /* timing settings, useless here*/ ++ .pixclock = 100000, /* pixel clock in ps (pico seconds) */ ++ .left_margin = 24, /* time from sync to picture */ ++ .right_margin = 4, /* time from picture to sync */ ++ .upper_margin = 6, /* time from sync to picture */ ++ .lower_margin = 4, ++ .hsync_len = 64, /* length of horizontal sync */ ++ .vsync_len = 2, /* length of vertical sync */ ++ .vmode = FB_VMODE_NONINTERLACED, ++}; ++ ++/* Device independent unchangeable information */ ++static struct fb_fix_screeninfo sg_mdrvinfinityfb1_fix = ++{ ++ .id = "FB1_gop1", /* identification string eg "TT Builtin"*/ ++ .smem_start = 0, /* Start of frame buffer mem*/ ++ .smem_len = 0, /* Length of frame buffer mem*/ ++ .type = FB_TYPE_PACKED_PIXELS, /* see FB_TYPE_*/ ++ .visual = FB_VISUAL_TRUECOLOR, /* see FB_VISUAL_*/ ++ .xpanstep = 0, /* zero if no hardware panning*/ ++ .ypanstep = 1, /* zero if no hardware panning*/ ++ .ywrapstep = 0, /* zero if no hardware ywrap*/ ++ .line_length = (defult_XRES * ANDROID_BYTES_PER_PIXEL), /* length of a line in bytes*/ ++ .mmio_start = 0x20000000, /* Start of Memory Mapped I/O*/ ++ /* (physical address)*/ ++ .mmio_len = 0x10000000, /* Length of Memory Mapped I/O*/ ++ .accel = FB_ACCEL_NONE, /* Type of acceleration available*/ ++}; ++ ++static struct fb_ops sg_mdrvinfinityfb1_ops = ++{ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = sys_fillrect, /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = sys_copyarea, /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = sys_imageblit, /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ ++ .fb_mmap = mdrvinfinityfb1_mmap, /* for non cached memory */ ++ .fb_ioctl = mdrvinfinityfb1_ioctl, ++ .fb_pan_display = mdrvinfinityfb1_pan_display, ++ .fb_check_var = mdrvinfinityfb1_check_var, ++ .fb_set_par = mdrvinfinityfb1_set_par, ++}; ++ ++ ++static const struct of_device_id infinity_infinityfb1_dt_ids[] = ++{ ++ { .compatible = "mstar,infinity-gop1" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, infinity_infinityfb1_dt_ids); ++ ++static struct platform_driver sg_mdrvinfinityfb1_driver = ++{ ++ .probe = mdrvinfinityfb1_probe, /* initiailize */ ++ .remove = mdrvinfinityfb1_remove, /* it free(mem), release framebuffer, free irq etc. */ ++ .suspend = mdrvinfinityfb1_suspend, ++ .resume = mdrvinfinityfb1_resume, ++ ++ .driver = ++ { ++ .name = "mdrvinfinityfb1", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(infinity_infinityfb1_dt_ids), ++ }, ++}; +diff --git a/drivers/mstar/fb2/Kconfig b/drivers/mstar/fb2/Kconfig +new file mode 100644 +index 00000000..0e668d47 +--- /dev/null ++++ b/drivers/mstar/fb2/Kconfig +@@ -0,0 +1,14 @@ ++config MS_FB ++ tristate "FB driver" ++ default y ++ select FB ++ select FB_SYS_FILLRECT ++ select FB_SYS_COPYAREA ++ select FB_SYS_IMAGEBLIT ++ select FB_SYS_FOPS ++ help ++ ++config MS_FB2_INFINITY3 ++ tristate "FB driver (GOP2) support for iNfinity3" ++ depends on MS_FB ++ depends on ARCH_INFINITY3 +\ No newline at end of file +diff --git a/drivers/mstar/fb2/Makefile b/drivers/mstar/fb2/Makefile +new file mode 100644 +index 00000000..b7c43fff +--- /dev/null ++++ b/drivers/mstar/fb2/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MS_FB2_INFINITY3) += infinity3/ +diff --git a/drivers/mstar/fb2/infinity3/Makefile b/drivers/mstar/fb2/infinity3/Makefile +new file mode 100644 +index 00000000..f6c2f0b5 +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/Makefile +@@ -0,0 +1,19 @@ ++# ++# Makefile for MStar fb device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++#--------gop-------- ++EXTRA_CFLAGS += -Idrivers/mstar/fb2/infinity3/gop2 ++EXTRA_CFLAGS += -Idrivers/mstar/fb2/infinity3/inv_color ++ ++# files ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop_io.o ++#obj-$(CONFIG_MS_FB_INFINITY) += gop/mdrv_gop.o ++#obj-$(CONFIG_MS_FB_INFINITY) += mdrv_fb.o ++ ++obj-$(CONFIG_MS_FB2_INFINITY3) += infinity_fb2.o ++ ++infinity_fb2-objs := mdrv_fb2.o \ ++ gop2/mdrv_gop2.o \ ++ inv_color/mdrv_gop2_inv_color.o +\ No newline at end of file +diff --git a/drivers/mstar/fb2/infinity3/gop2/gop_c2_reg.h b/drivers/mstar/fb2/infinity3/gop2/gop_c2_reg.h +new file mode 100644 +index 00000000..2cdecddb +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/gop2/gop_c2_reg.h +@@ -0,0 +1,249 @@ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME gop_c2_reg.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#define GET_REG8_ADDR(x, y) (x+(y)*2) ++#define GET_REG16_ADDR(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define BASE_REG_RIU_PA (0x1F000000) ++ ++//GOP Base register defines ++//if there's no direct bank, the base addresses of GOP00, GOP01 and GOP02 are the same ++//I1 settings ++//#define mdrv_BASE_REG_GOP00_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//#define mdrv_BASE_REG_GOP01_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//#define mdrv_BASE_REG_GOP02_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123000/2)) ++//I3 settings for gop1(at scl2) ++#define mdrv_BASE_REG_GOP20_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123700/2)) ++#define mdrv_BASE_REG_GOP21_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123800/2)) ++#define mdrv_BASE_REG_GOP22_PA GET_REG16_ADDR(BASE_REG_RIU_PA, (0x123900/2)) ++ ++//MIU Bus settings ++#define MIU_BUS_INFINITY3 0x4 ++#define MIU_BUS_ALIGN MIU_BUS_INFINITY3 ++ ++ ++#define mdrv_GWin0_Disable (0xFFFE) ++#define mdrv_GWIN0_Enable (0x1) ++ ++#define mdrv_ENABLE_CONST_ALPHA (~(0x1<<14)) ++ ++//fomrat define ++#define GWIN_FMT_MASK 0x00F0 ++#define RGB1555_Blink 0x0000 ++#define RGB565 0x0010 ++#define ARGB4444 0x0020 ++#define _2266 0x0030 ++#define _8Bit_Palette 0x0040 ++#define ARGB8888 0x0050 ++#define ARGB1555 0x0060 ++#define ABGR8888 0x0070 ++#define RGB1555_UV7Y8 0x0080 ++#define UV8Y8 0x0090 ++#define RGBA5551 0x00A0 ++#define RGBA4444 0x00B0 ++ ++//------------------------------------------------------------------------------ ++// GOP ++//------------------------------------------------------------------------------ ++// Bank 0, GOPG0_0 ++ ++// REG_GOP_00 ++#define GOP_SOFT_RESET 0x0001 ++#define GOP_VS_INV 0x0002 ++#define GOP_HS_INV 0x0004 ++#define GOP_DISPLAY_MODE 0x0008 // 0:interlace, 1: progress ++#define GOP_FIELD_INV 0x0010 ++#define GOP_YUV_TRANSPARENT_COLOR_ENABLE 0x0020 ++#define GOP_TEST_PATTENR_MODE_ENABLE 0x0040 ++#define GOP_5541_EN 0x0080 // RGB5541 alpha mask mode enable, only for RGB1555 Data type ++#define GOP_REG_OUTPUT_READY 0x0100 ++#define GOP_G3D_FORMATE_NEW_MODE_ENABLE 0x0200 ++#define GOP_OUTPUT_FORMAT 0x0400 // 0:RGB out, 1:YUV out ++#define GOP_RGB_TRANSPARENT_COLOR_MASK 0x0800 ++#define GOP_DISP_HBACK_ENABLE 0x1000 // H Mirror enable; H pixel read out direction, 0:forward, 1:backward ++#define GOP_DISP_VBACK_ENABLE 0x2000 // V Mirror enable; V line read out direction, 0:down, 1:up ++#define GOP_HS_MASK 0x4000 ++#define GOP_ALPHA_INV 0x8000 ++// GOP Display Mode ++#define GWIN_display_mode_progress 0x0008 ++#define GWIN_display_mode_interlace 0x0000 ++// GOP Output Color ++#define GOP_YUVOUT 0x0400 ++#define GOP_RGBOUT 0x0000 ++// GOP RGB Transparent Color ++#define GOP_RGB_TRANSPARENT_COLOR_ENABLE 0x0800 ++#define GOP_RGB_TRANSPARENT_COLOR_DISABLE 0x0000 ++ ++ ++// REG_GOP_01 ++// GOP Destination ++#define GOP_DST_IP_MAIN 0x0000 ++#define GOP_DST_IP_SUB 0x0001 ++#define GOP_DST_OP 0x0002 ++#define GOP_DST_MVOP 0x0003 ++#define GOP_DST_SUB_MVOP 0x0004 ++#define GOP_DST_FRC 0x0006 ++// GOP interval settings ++#define GOP_REGDMA_INTERVAL_START 0x0200 //infinity:0x0200; cedric:0x0300 ++#define GOP_REGDMA_INTERVAL_END 0x4000 //infinity:0x4000; cedirc:0x5000 ++ ++ ++// REG_GOP_02 ++#define GOP_BLINK_DISABLE 0x0000 ++#define GOP_BLINK_ENABLE 0x8000 ++ ++// REG_GOP_05 ++#define GOP_PALETTE_TABLE_ADDRESS_MASK 0x00FF //palette index ++#define GOP_PALETTE_WRITE_ENABLE_MASK 0x0100 ++#define GOP_PALETTE_READ_ENABLE_MASK 0x0200 ++#define GOP_PALETTE_SRAM_CTRL_MASK 0x3000 //0:RIU mode; 1:REGDMA mode; 2,3:for external gop ++#define GOP_PALETTE_SRAM_CTRL_RIU 0x0000 ++#define GOP_PALETTE_SRAM_CTRL_REGDMA 0x1000 ++ ++ ++ ++// REG_GOP_06 ++#define GOP_REGDMA_END 0x0034 ++ ++ ++// REG_GOP_07 ++#define GOP_REGDMA_STR 0x0000 ++ ++ ++// REG_GOP_0F ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++#define GOP_HSYNC_PIPE_DLY_FOR_SC1_OP 0x00A0 ++#define HSYNC_PIPE_DLY_FOR_SC0_2GOP 0x0044 ++ ++// inifinity settings ++#define INIFINITY_GOP_HSYNC_PIPE_DLY 0x0000 ++#define GOP_HSYNC_PIPE_DLY INIFINITY_GOP_HSYNC_PIPE_DLY ++ ++#define GOP_HSYNC_PIPE_DLY_FOR_IP_SUB 0x0080 ++ ++ ++// REG_GOP_19 ++#define GOP_BURST_LENGTH_MASK 0x1F00 ++#define GOP_BURST_LENGTH_MAX 0x1F00 ++#define GOP_BURST_LENGTH_AUTO 0x0000 ++ ++ ++// REG_GOP_20 ++#define GOP_GWIN_HIGH_PRI_0 0x0000 ++#define GOP_GWIN_HIGH_PRI_1 0x0001 ++ ++// REG_GOP_32 ++#define GOP_STRETCH_HST 0x0000 ++ ++// REG_GOP_34 ++#define GOP_STRETCH_VST 0x0000 ++ ++// REG_GOP_35 ++#define GOP_STRETCH_HRATIO 0x1000 ++ ++// REG_GOP_36 ++#define GOP_STRETCH_VRATIO 0x1000 ++ ++// REG_GOP_38 ++#define GOP_STRETCH_HINI 0x0000 ++ ++// REG_GOP_39 ++#define GOP_STRETCH_VINI 0x0000 ++ ++// REG_GOP_7E ++//#define GOP_GOPG0_MUX_MASK 0x0007 ++//#define GOP_GOPG0_MUX_4G 0x0000 ++//#define GOP_GOPG0_MUX_2G 0x0001 ++ ++//#define GOP_Layer0_MUX_MASK 0x0007 ++//#define GOP_Layer0_Sel_GOP0 0x0000 ++//#define GOP_Layer0_Sel_GOP1 0x0001 ++//#define GOP_Layer0_Sel_GOP2 0x0002 ++//#define GOP_Layer0_Sel_GOP3 0x0003 ++//#define GOP_Layer0_Sel_GOP_Null 0x0004 ++ ++//#define GOP_Layer1_MUX_MASK (0x0007)<<3 ++//#define GOP_Layer1_Sel_GOP0 (0x0000)<<3 ++//#define GOP_Layer1_Sel_GOP1 (0x0001)<<3 ++//#define GOP_Layer1_Sel_GOP2 (0x0002)<<3 ++//#define GOP_Layer1_Sel_GOP3 (0x0003)<<3 ++//#define GOP_Layer1_Sel_GOP_Null (0x0004)<<3 ++ ++//#define GOP_Layer2_MUX_MASK (0x0007)<<6 ++//#define GOP_Layer2_Sel_GOP0 (0x0000)<<6 ++//#define GOP_Layer2_Sel_GOP1 (0x0001)<<6 ++//#define GOP_Layer2_Sel_GOP2 (0x0002)<<6 ++//#define GOP_Layer2_Sel_GOP3 (0x0003)<<6 ++//#define GOP_Layer2_Sel_GOP_Null (0x0004)<<6 ++ ++//#define GOP_Layer3_MUX_MASK (0x0007)<<9 ++//#define GOP_Layer3_Sel_GOP0 (0x0000)<<9 ++//#define GOP_Layer3_Sel_GOP1 (0x0001)<<9 ++//#define GOP_Layer3_Sel_GOP2 (0x0002)<<9 ++//#define GOP_Layer3_Sel_GOP3 (0x0003)<<9 ++//#define GOP_Layer3_Sel_GOP_Null (0x0004)<<9 ++ ++// REG_GOP_7F ++#define GOP_BANK_G0_0 0x0000 ++#define GOP_BANK_G0_1 0x0001 ++#define GOP_BANK_G1_0 0x0003 ++#define GOP_BANK_G1_1 0x0004 ++#define GOP_BANK_G2_0 0x0006 ++#define GOP_BANK_G2_1 0x0007 ++#define GOP_BANK_G3_0 0x0009 ++#define GOP_BANK_G3_1 0x000A ++#define GOP_BANK_GPD 0x0006 ++ ++#define GOP_BANK_DOUBLE_WR 0x0100 ++#define GOP_BANK_FORCE_WR 0x0200 ++ ++#define GOP_BANK_DOUBLE_WR_G0 0x0400 ++#define GOP_BANK_DOUBLE_WR_G1 0x0403 ++#define GOP_BANK_DOUBLE_WR_G2 0x0406 ++#define GOP_BANK_DOUBLE_WR_G3 0x0409 ++#define GOP_BANK_DOUBLE_WR_MSK 0x0400 ++#define GOP_BANK_SEL_MSK 0x000F ++ ++#define GOP_BANK_GOP0_WR_ACK_MSK 0x1000 ++#define GOP_BANK_GOP1_WR_ACK_MSK 0x2000 ++#define GOP_BANK_GOP2_WR_ACK_MSK 0x4000 ++ ++// GOP0 Bank 1 ++// REG_GOP_00 ++#define GOP0_GWin0_Enable 0x0001 ++#define GOP_PIXEL_ALPHA_EN 0x4000 ++#define GOP_CONSTANT_ALPHA_EN 0x0000 ++#define GOP_ALPHA_MASK 0x4000 +diff --git a/drivers/mstar/fb2/infinity3/gop2/mdrv_gop2.c b/drivers/mstar/fb2/infinity3/gop2/mdrv_gop2.c +new file mode 100644 +index 00000000..a34f43ee +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/gop2/mdrv_gop2.c +@@ -0,0 +1,624 @@ ++#include "mdrv_gop2.h" ++ ++#define PARSING_FB_FORMAT(x)(\ ++ x == _8Bit_Palette ? "Palette_I8": \ ++ x == RGB565 ? "RGB565" : \ ++ x == ARGB4444 ? "ARGB4444" : \ ++ x == ARGB8888 ? "ARGB8888" : \ ++ x == ARGB1555 ? "ARGB1555" : \ ++ x == UV8Y8 ? "UV8Y8" : \ ++ "Format_Not_Support") ++ ++#define PARSING_ALPHA_TYPE(x)(\ ++ x == 0 ? "PIXEL_ALPHA": \ ++ x == 1 ? "CONST_ALPHA": \ ++ "Wrong_Alpha_Type") ++ ++ ++void GOP2_SwitchSubBank(int subbank) ++{ ++ unsigned long GOP_Reg_Base=0; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ if ((subbank>=0)&&(subbank<=2)) ++ { ++ OUTREG16(GOP_Reg_Base+REG_GOP_7F,subbank); ++ GOP2DBG( "[GOP2]%s: Switch to Subbank %d\n",__func__,subbank); ++ } ++ else ++ GOP2DBG( "[GOP2]%s: Wrong Subbank %d\n",__func__,subbank); ++} ++ ++void GOP2_Pan_Display(int Screen, U32 FB_Start_Addr ) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U32 s32BuffAddr = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. Pan display works by changing framebuffer start address ++ ++ ++ GOP2DBG ("[GOP2]%s: in, addr=0x%x \n",__func__,FB_Start_Addr); ++ ++ /// GOP0_1 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ // GOP fetch framebuffer information ++ // set the starting address for showing by GOP ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS; //128-bit unit = 16 bytes ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); //Ring block start Low address 0x21:16 ++ s32BuffAddr = s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); //Ring block start Hi address 0x22:6, page number ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ GOP2DBG ("[GOP2]%s: out \n",__func__); ++} ++ ++void GOP2_Setmode( ++ int bResume, int Screen, ++ int Panel_Width,int Panel_Height,U32 FB_Start_Addr, ++ U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Hardware Initial ++ // 2. GOP Fetch Framebuffer Information ++ // 3. GOP Display Settings ++ ++ ++ //GOP2DBG ("GOP_Setmode Screen is %x.\r\n",Screen); ++ GOP2DBG ("[GOP2]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOP2DBG ("[GOP2]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOP2DBG ("[GOP2]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOP2DBG ("[GOP2]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOP2DBG ("[GOP2]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GOP_SOFT_RESET|GOP_FIELD_INV);//reset ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,GWIN_display_mode_progress|GOP_HS_MASK|GOP_ALPHA_INV|GOP_YUVOUT);//set Progress mode; mask Hsync; alpha inverse; YUV output ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,GOP_REGDMA_INTERVAL_START|GOP_REGDMA_INTERVAL_END); ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,GOP_BLINK_DISABLE);//close blink ++ OUTREG16(GOP_Reg_Base+REG_GOP_0A,0x0010);//insert fake rdy between hs & valid rdy ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F,GOP_HSYNC_PIPE_DLY); //Hsync input pipe delay ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_19, GOP_BURST_LENGTH_MASK, GOP_BURST_LENGTH_MAX);// set gop dma burst length ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ OUTREG16(GOP_Reg_Base+REG_GOP_32,GOP_STRETCH_HST); //Stretch Window H coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_34,GOP_STRETCH_VST); //Stretch Window V coordinate ++ OUTREG16(GOP_Reg_Base+REG_GOP_35,GOP_STRETCH_HRATIO); //Stretch H ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_36,GOP_STRETCH_VRATIO); //Stretch V ratio ++ OUTREG16(GOP_Reg_Base+REG_GOP_38,GOP_STRETCH_HINI); //Stretch H start value ++ OUTREG16(GOP_Reg_Base+REG_GOP_39,GOP_STRETCH_VINI); //Stretch V start value ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_00,DISPLAY_Format|GOP0_GWin0_Enable|GOP_PIXEL_ALPHA_EN);//set gop format; enable gwin; alpha mode initial ++ ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS;//128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); //H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); //H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart);//V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); //V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++ ++ ++void GOP2_Set_OutFormat(int screen, int byuvoutput) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Change Output Color Format (YUV/RGB) ++ ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ GOP2DBG("[GOP2]%s: screen:%d, byuvoutput:%d\n",__func__, screen, byuvoutput); ++ ++ if(byuvoutput) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_YUVOUT, GOP_YUVOUT); ++ ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP_YUVOUT); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++} ++ ++ ++ ++void GOP2_Set_Constant_Alpha(int screen, int bEn, int alpha) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set Alpha Blending ++ // 2. bEn= 0:pixel alpha; 1: constant alpha; for register: pixel_alpha=1, constant_alpha=0 ++ // 3. alpha: constant alpha value ++ ++ ++ GOP2DBG("[GOP2]%s: screen:%d, bEn:%d, alpha:%x\n",__func__, screen, bEn, alpha); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ // alpha inv ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? 0x0000 : GOP_ALPHA_INV), GOP_ALPHA_INV);//set alpha inverse when pixel alpha ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ // constant or pixel alpha ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, (bEn ? GOP_CONSTANT_ALPHA_EN : GOP_PIXEL_ALPHA_EN), GOP_ALPHA_MASK); ++ ++ // alpha value ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_0A, (bEn ? alpha : 0x0000), 0x00FF);//available for constant alpha; set 0 when pixel alpha ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ ++} ++ ++ ++void GOP2_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set RGB Color Key ++ // 2. bEn= 0: disable; 1: enable ++ // 3. u8R: red color value; u8G: green color value; u8B: blue color value ; value range: 0~255 (0x0~0xFF) ++ ++ ++ GOP2DBG("[GOP2]%s: screen:%d, bEn:%d, (R=%x, G=%x, B=%x)\n",__func__, screen, bEn, u8R, u8G, u8B); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ if(bEn) ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_RGB_TRANSPARENT_COLOR_ENABLE, GOP_RGB_TRANSPARENT_COLOR_MASK); ++ OUTREG16(GOP_Reg_Base+REG_GOP_24, (u8B|(u8G<<8))); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_25, u8R, 0x00FF); ++ } ++ else ++ { ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_RGB_TRANSPARENT_COLOR_DISABLE, GOP_RGB_TRANSPARENT_COLOR_MASK); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP2_Set_PipeDelay(int screen, int delay) ++{ ++ U16 pipe_delay = delay; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ ++ // 1. GOP Set Pipe Delay ++ ++ ++ GOP2DBG("[GOP2]%s: screen:%d, delay:%d\n",__func__, screen, delay); ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ OUTREG16(GOP_Reg_Base+REG_GOP_0F, pipe_delay); ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR); ++} ++ ++void GOP2_Set_Palette_RIU(int screen, int u8Index, int u8A, int u8R, int u8G, int u8B) ++{ ++ U32 GOP_Reg_Base = 0; ++ ++ // 1. GOP Set Palette by RIU Mode ++ // 2. GOP Palette SRAM Clock should be opened ++ // 3. Set Force Write ++ // 4. Set RIU Mode ++ // 5. Set Palette Index, A, R, G, B Values ++ // 6. Trigger Palette Write ++ // 7. Close Force Write ++ ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ //set force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_BANK_FORCE_WR , GOP_BANK_FORCE_WR); ++ ++ //set RIU mode ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, GOP_PALETTE_SRAM_CTRL_RIU , GOP_PALETTE_SRAM_CTRL_MASK); ++ ++ //set palette value ++ OUTREG16(GOP_Reg_Base+REG_GOP_03, u8G<<8|u8B); ++ OUTREG16(GOP_Reg_Base+REG_GOP_04, u8A<<8|u8R); ++ ++ //set palette index ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, u8Index , GOP_PALETTE_TABLE_ADDRESS_MASK); ++ ++ //write trigger ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0100 , GOP_PALETTE_WRITE_ENABLE_MASK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_05, 0x0000 , GOP_PALETTE_WRITE_ENABLE_MASK); ++ ++ //close force write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0x0000 , GOP_BANK_FORCE_WR); ++ ++} ++ ++void GOP2_Set_Outputmode(int Screen, int Panel_Width, int Panel_Height,U32 FB_Start_Addr, U32 Pixel_Format, U16 Bytes_Per_Pixel) ++{ ++ U32 FB_add = FB_Start_Addr; ++ U16 FB_WIDTH = Panel_Width; ++ U16 FB_HEIGHT = Panel_Height; ++ U16 FB_Bytes_Per_Pixel = Bytes_Per_Pixel; ++ U16 u16FrameBuffer_HSize = FB_WIDTH; ++ U16 u16FrameBuffer_VSize = FB_HEIGHT; ++ U16 u16FrameBuffer_Bytes_Per_Pixel = FB_Bytes_Per_Pixel; ++ U16 u16DispImage_HStart = 0; ++ U16 u16DispImage_HSize = FB_WIDTH; ++ U16 u16DispImage_HEnd = u16DispImage_HStart+u16DispImage_HSize; ++ U16 u16DispImage_VStart = 0; ++ U16 u16DispImage_VSize = FB_HEIGHT; ++ U16 u16DispImage_VEnd = u16DispImage_VStart+u16DispImage_VSize; ++ U32 s32BuffAddr = 0; ++ U32 u32TempVal = 0; ++ U32 GOP_Reg_Base = 0; ++ U16 GOP_Reg_DB = 0; ++ U16 MIU_BUS = MIU_BUS_ALIGN; ++ U16 DISPLAY_Format = Pixel_Format; ++ ++ // 1. GOP Set Output Mode ++ // 2. GOP Fetch Framebuffer Information ++ // 3. GOP Display Settings ++ ++ GOP2DBG ("[GOP2]%s\n",__func__); ++ GOP2DBG ("[GOP2]%s: FB_Width = [%d]\n",__func__,FB_WIDTH); ++ GOP2DBG ("[GOP2]%s: FB_Height = [%d]\n",__func__,FB_HEIGHT); ++ GOP2DBG ("[GOP2]%s: FB_addr = [0x%x]\n",__func__,FB_add); ++ GOP2DBG ("[GOP2]%s: FB_Format = [%s]\n",__func__,PARSING_FB_FORMAT(DISPLAY_Format)); ++ GOP2DBG ("[GOP2]%s: FB_BPP = [%d]\n",__func__,FB_Bytes_Per_Pixel); ++ ++ FB_add = (U32)Chip_Phys_to_MIU(FB_add);//map physical address to MIU address ++ ++ /// GOP0_0 settings ++ GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ ++ ++ /// GOP0_1 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ // gwin global settings ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, DISPLAY_Format, GWIN_FMT_MASK); ++ ++ // framebuffer settings ++ // framebuffer starting address ++ s32BuffAddr = FB_add; ++ s32BuffAddr = s32BuffAddr&0xFFFFFFFF; ++ s32BuffAddr = s32BuffAddr>>MIU_BUS;//128-bit unit = 16 bytes ++ OUTREG16(GOP_Reg_Base+REG_GOP_01,(s32BuffAddr&0xFFFF)); ++ s32BuffAddr=s32BuffAddr>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_02,(s32BuffAddr&0xFFFF)); ++ ++ // framebuffer pitch ++ OUTREG16(GOP_Reg_Base+REG_GOP_09,(u16FrameBuffer_HSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS);//bytes per line for gop framebuffer ++ ++ // framebuffer size, use for scroll; useless in I1, I3 ++ u32TempVal=(u16FrameBuffer_HSize*u16FrameBuffer_VSize*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_10,u32TempVal&0xFFFF); ++ u32TempVal=u32TempVal>>0x10; ++ OUTREG16(GOP_Reg_Base+REG_GOP_11,u32TempVal); ++ ++ // framebuffer V start offset (line) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0C,0); ++ OUTREG16(GOP_Reg_Base+REG_GOP_0D,0); ++ ++ // framebuffer H start offset (pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,0); ++ ++ ++ // GOP display settings ++ // GWIN display area in panel : : H start postion and end information ++ u32TempVal=(u16DispImage_HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); //H start ++ u32TempVal=(u16DispImage_HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); //H end ++ ++ // GWIN display area in panel : V start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,u16DispImage_VStart);//V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,u16DispImage_VEnd); //V end line ++ ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ // Double Buffer Write ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP2_Set_Enable_GWIN(int screen, unsigned char bEn) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ unsigned char enGOP = bEn; ++ unsigned long GOP_Reg_DB = 0x0400; ++ ++ // 1. GOP Set GWIN Enable/Disable ++ ++ GOP2DBG( "[GOP2]%s: Set enable_GOP = [%d]\n",__func__,enGOP); ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ // enable/disable gwin ++ if(enGOP) ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, enGOP, GOP0_GWin0_Enable); ++ else ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_00, 0, GOP0_GWin0_Enable); ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++} ++ ++void GOP2_Get_Enable_GWIN(int screen, unsigned char *bEn) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ ++ // 1. GOP Get GWIN Enable/Disable ++ ++ // enable gwin is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP0_GWin0_Enable)) ++ { ++ *bEn = 1; ++ } ++ else ++ { ++ *bEn = 0; ++ } ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ GOP2DBG( "[GOP2]%s: Get enable_GOP = [%d]\n",__func__,enGOP); ++ ++} ++ ++void GOP2_Get_Alpha(int screen, int *alpha_type, int *alpha_val) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ ++ // 1. GOP Get Alpha Blending ++ // 2. alpha_type= 0:pixel_alpha; 1: constant_alpha; for register: pixel_alpha=1, constant_alpha=0 ++ // 3. alpha_val: constant alpha value ++ ++ // alpha info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ // constant or pixel alpha ++ if(INREGMSK16(GOP_Reg_Base+REG_GOP_00, GOP_PIXEL_ALPHA_EN)==GOP_PIXEL_ALPHA_EN) ++ *alpha_type = 0; //pixel_alpha ++ else ++ *alpha_type = 1; //constant_alpha ++ ++ // alpha value ++ *alpha_val = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_0A, 0x00FF); ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ GOP2DBG( "[GOP2]%s: Alpha_type = [%s], Alpha_value = [%d]\n",__func__,PARSING_ALPHA_TYPE(*alpha_type),*alpha_val); ++ ++} ++ ++void GOP2_Get_Color_Key(int screen, int *bEn, int *u8R, int *u8G, int *u8B) ++{ ++ unsigned long GOP_Reg_Base; ++ ++ // 1. GOP Get RGB Color Key ++ // 2. bEn= 0: disable; 1: enable ++ // 3. u8R: red color value; u8G: green color value; u8B: blue color value ; value range: 0~255 (0x0~0xFF) ++ ++ // colorkey setting is in GOP00 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ // enable/disable ++ *bEn = (INREGMSK16(GOP_Reg_Base+REG_GOP_00,0x0800)>>11); ++ ++ // colorkey value ++ *u8R = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_25,0x00FF); ++ *u8G = (unsigned char)(INREGMSK16(GOP_Reg_Base+REG_GOP_24,0xFF00)>>8); ++ *u8B = (unsigned char)INREGMSK16(GOP_Reg_Base+REG_GOP_24,0x00FF); ++ ++ GOP2DBG("[GOP2]%s: screen:%d, bEn:%d, (R=%x, G=%x, B=%x)\n",__func__, screen, *bEn, *u8R, *u8G, *u8B); ++ ++} +diff --git a/drivers/mstar/fb2/infinity3/gop2/mdrv_gop2.h b/drivers/mstar/fb2/infinity3/gop2/mdrv_gop2.h +new file mode 100644 +index 00000000..ebcbebaf +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/gop2/mdrv_gop2.h +@@ -0,0 +1,202 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_gop.h ++ * DESCRIPTION ++ * Including some MACRO needed in msb250xfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/msb250xfb.h -- msb250xfb frame buffer device ++ ******************************************************************************/ ++ ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#include "gop_c2_reg.h" ++ ++#define GOP2_DEBUG 0 ++#if (GOP2_DEBUG==1) ++#define GOP2DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOP2DBG(fmt, arg...) ++#endif ++ ++#define BK_REG(reg) ((reg) * 4) ++ ++/* ---------------------------------------------------------------------------- ++ * GOP_OFFSET ++ * ---------------------------------------------------------------------------- ++ */ ++#define REG_GOP_00 BK_REG(0x00) ++#define REG_GOP_01 BK_REG(0x01) ++#define REG_GOP_02 BK_REG(0x02) ++#define REG_GOP_03 BK_REG(0x03) ++#define REG_GOP_04 BK_REG(0x04) ++#define REG_GOP_05 BK_REG(0x05) ++#define REG_GOP_06 BK_REG(0x06) ++#define REG_GOP_07 BK_REG(0x07) ++#define REG_GOP_08 BK_REG(0x08) ++#define REG_GOP_09 BK_REG(0x09) ++#define REG_GOP_0A BK_REG(0x0A) ++#define REG_GOP_0B BK_REG(0x0B) ++#define REG_GOP_0C BK_REG(0x0C) ++#define REG_GOP_0D BK_REG(0x0D) ++#define REG_GOP_0E BK_REG(0x0E) ++#define REG_GOP_0F BK_REG(0x0F) ++ ++#define REG_GOP_10 BK_REG(0x10) ++#define REG_GOP_11 BK_REG(0x11) ++#define REG_GOP_12 BK_REG(0x12) ++#define REG_GOP_13 BK_REG(0x13) ++#define REG_GOP_14 BK_REG(0x14) ++#define REG_GOP_15 BK_REG(0x15) ++#define REG_GOP_16 BK_REG(0x16) ++#define REG_GOP_17 BK_REG(0x17) ++#define REG_GOP_18 BK_REG(0x18) ++#define REG_GOP_19 BK_REG(0x19) ++#define REG_GOP_1A BK_REG(0x1A) ++#define REG_GOP_1B BK_REG(0x1B) ++#define REG_GOP_1C BK_REG(0x1C) ++#define REG_GOP_1D BK_REG(0x1D) ++#define REG_GOP_1E BK_REG(0x1E) ++#define REG_GOP_1F BK_REG(0x1F) ++ ++#define REG_GOP_20 BK_REG(0x20) ++#define REG_GOP_21 BK_REG(0x21) ++#define REG_GOP_22 BK_REG(0x22) ++#define REG_GOP_23 BK_REG(0x23) ++#define REG_GOP_24 BK_REG(0x24) ++#define REG_GOP_25 BK_REG(0x25) ++#define REG_GOP_26 BK_REG(0x26) ++#define REG_GOP_27 BK_REG(0x27) ++#define REG_GOP_28 BK_REG(0x28) ++#define REG_GOP_29 BK_REG(0x29) ++#define REG_GOP_2A BK_REG(0x2A) ++#define REG_GOP_2B BK_REG(0x2B) ++#define REG_GOP_2C BK_REG(0x2C) ++#define REG_GOP_2D BK_REG(0x2D) ++#define REG_GOP_2E BK_REG(0x2E) ++#define REG_GOP_2F BK_REG(0x2F) ++ ++#define REG_GOP_30 BK_REG(0x30) ++#define REG_GOP_31 BK_REG(0x31) ++#define REG_GOP_32 BK_REG(0x32) ++#define REG_GOP_33 BK_REG(0x33) ++#define REG_GOP_34 BK_REG(0x34) ++#define REG_GOP_35 BK_REG(0x35) ++#define REG_GOP_36 BK_REG(0x36) ++#define REG_GOP_37 BK_REG(0x37) ++#define REG_GOP_38 BK_REG(0x38) ++#define REG_GOP_39 BK_REG(0x39) ++#define REG_GOP_3A BK_REG(0x3A) ++#define REG_GOP_3B BK_REG(0x3B) ++#define REG_GOP_3C BK_REG(0x3C) ++#define REG_GOP_3D BK_REG(0x3D) ++#define REG_GOP_3E BK_REG(0x3E) ++#define REG_GOP_3F BK_REG(0x3F) ++ ++#define REG_GOP_40 BK_REG(0x40) ++#define REG_GOP_41 BK_REG(0x41) ++#define REG_GOP_42 BK_REG(0x42) ++#define REG_GOP_43 BK_REG(0x43) ++#define REG_GOP_44 BK_REG(0x44) ++#define REG_GOP_45 BK_REG(0x45) ++#define REG_GOP_46 BK_REG(0x46) ++#define REG_GOP_47 BK_REG(0x47) ++#define REG_GOP_48 BK_REG(0x48) ++#define REG_GOP_49 BK_REG(0x49) ++#define REG_GOP_4A BK_REG(0x4A) ++#define REG_GOP_4B BK_REG(0x4B) ++#define REG_GOP_4C BK_REG(0x4C) ++#define REG_GOP_4D BK_REG(0x4D) ++#define REG_GOP_4E BK_REG(0x4E) ++#define REG_GOP_4F BK_REG(0x4F) ++ ++#define REG_GOP_50 BK_REG(0x50) ++#define REG_GOP_51 BK_REG(0x51) ++#define REG_GOP_52 BK_REG(0x52) ++#define REG_GOP_53 BK_REG(0x53) ++#define REG_GOP_54 BK_REG(0x54) ++#define REG_GOP_55 BK_REG(0x55) ++#define REG_GOP_56 BK_REG(0x56) ++#define REG_GOP_57 BK_REG(0x57) ++#define REG_GOP_58 BK_REG(0x58) ++#define REG_GOP_59 BK_REG(0x59) ++#define REG_GOP_5A BK_REG(0x5A) ++#define REG_GOP_5B BK_REG(0x5B) ++#define REG_GOP_5C BK_REG(0x5C) ++#define REG_GOP_5D BK_REG(0x5D) ++#define REG_GOP_5E BK_REG(0x5E) ++#define REG_GOP_5F BK_REG(0x5F) ++ ++#define REG_GOP_60 BK_REG(0x60) ++#define REG_GOP_61 BK_REG(0x61) ++#define REG_GOP_62 BK_REG(0x62) ++#define REG_GOP_63 BK_REG(0x63) ++#define REG_GOP_64 BK_REG(0x64) ++#define REG_GOP_65 BK_REG(0x65) ++#define REG_GOP_66 BK_REG(0x66) ++#define REG_GOP_67 BK_REG(0x67) ++#define REG_GOP_68 BK_REG(0x68) ++#define REG_GOP_69 BK_REG(0x69) ++#define REG_GOP_6A BK_REG(0x6A) ++#define REG_GOP_6B BK_REG(0x6B) ++#define REG_GOP_6C BK_REG(0x6C) ++#define REG_GOP_6D BK_REG(0x6D) ++#define REG_GOP_6E BK_REG(0x6E) ++#define REG_GOP_6F BK_REG(0x6F) ++ ++#define REG_GOP_70 BK_REG(0x70) ++#define REG_GOP_71 BK_REG(0x71) ++#define REG_GOP_72 BK_REG(0x72) ++#define REG_GOP_73 BK_REG(0x73) ++#define REG_GOP_74 BK_REG(0x74) ++#define REG_GOP_75 BK_REG(0x75) ++#define REG_GOP_76 BK_REG(0x76) ++#define REG_GOP_77 BK_REG(0x77) ++#define REG_GOP_78 BK_REG(0x78) ++#define REG_GOP_79 BK_REG(0x79) ++#define REG_GOP_7A BK_REG(0x7A) ++#define REG_GOP_7B BK_REG(0x7B) ++#define REG_GOP_7C BK_REG(0x7C) ++#define REG_GOP_7D BK_REG(0x7D) ++#define REG_GOP_7E BK_REG(0x7E) ++#define REG_GOP_7F BK_REG(0x7F) ++ ++//global functions ++void GOP2_SwitchSubBank(int subbank); ++void GOP2_Setmode(int bResume, int Screen,int Panel_Width,int Panel_Height,U32 FB_Start_Addr,U32 Pixel_Format,U16 Bytes_Per_Pixel, int bInterlaceOut); ++void GOP2_Pan_Display(int Screen, U32 FB_Start_Addr); ++void GOP2_Set_OutFormat(int screen, int byuvoutput); ++void GOP2_Set_Constant_Alpha(int screen, int bEn, int alpha); ++void GOP2_Set_Color_Key(int screen, int bEn, int u8R, int u8G, int u8B); ++void GOP2_Set_PipeDelay(int screen, int delay); ++void GOP2_Set_Palette_RIU(int screen, int u8Index, int u8A, int u8R, int u8G, int u8B); ++void GOP2_Set_Outputmode(int Screen, int Panel_Width, int Panel_Height,U32 FB_Start_Addr, U32 Pixel_Format, U16 Bytes_Per_Pixel); ++void GOP2_Set_Enable_GWIN(int screen, unsigned char bEn); ++void GOP2_Get_Enable_GWIN(int screen, unsigned char *bEn); ++void GOP2_Get_Alpha(int screen, int *alpha_type, int *alpha_val); ++void GOP2_Get_Color_Key(int screen, int *bEn, int *u8R, int *u8G, int *u8B); +diff --git a/drivers/mstar/fb2/infinity3/inv_color/mdrv_gop2_inv_color.c b/drivers/mstar/fb2/infinity3/inv_color/mdrv_gop2_inv_color.c +new file mode 100644 +index 00000000..8de0ba4a +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/inv_color/mdrv_gop2_inv_color.c +@@ -0,0 +1,422 @@ ++#include "mdrv_gop2_inv_color.h" ++ ++void GOP2_invColor_init(void) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ int output_YUV_mode=0x0002; ++ int complementary_color_mode=0x0008; ++ ++ // 1. GOP Set inverse color init settings ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ ++ // set gop output mode YUV ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BASE_SETTINGS, output_YUV_mode, GOP2_invColor_gop_output_mode); ++ ++ // set inverse color mode to complementary color mode ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BASE_SETTINGS, complementary_color_mode, GOP2_invColor_color_mode); ++ ++} ++ ++void GOP2_invColor_Enable(unsigned char bEn) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ ++ // 1. GOP Set inverse color Enable/Disable ++ ++ GOP2_invColor_DBG( "[GOP2_invColor]%s: Set enable_GOP = [%d]\n",__func__,bEn); ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ ++ // enable/disable inverse color ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BASE_SETTINGS, bEn, GOP2_invColor_enable_mask); ++ ++} ++ ++void GOP2_invColor_Set_UpdateMode(unsigned char bMode) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ ++ // 1. GOP Set inverse color update inverse table mode ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ ++ // set inverse color update mode, 1:by cpu, 0:by engine ++ if(bMode) ++ { ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BASE_SETTINGS, GOP2_invColor_update_mode, GOP2_invColor_update_mode); ++ } ++ else ++ { ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BASE_SETTINGS, 0, GOP2_invColor_update_mode); ++ } ++ ++} ++ ++void GOP2_invColor_Set_Y_Threshold(int AE_Y_Thres) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ ++ // 1. GOP Set Y threshold to do inverse color or not ++ ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: Set Y Threshold = [%d]\n",__func__,AE_Y_Thres); ++ ++ // set AE_Y_Thres ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BASE_SETTINGS, (AE_Y_Thres<<8),GOP2_invColor_AE_Y_Threshold_mask); ++ ++} ++ ++void GOP2_invColor_Set_AE_Config(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ int real_blk_width = AE_Blk_Width; // register setting is real_size-1 ++ int AE_Blk_x_num = 0; ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ AE_Blk_x_num = AE_x_res / real_blk_width; //real x blk num ++ ++ // 1. GOP Set AE config ++ ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: reg AE_Blk_Width = [%d]\n",__func__,AE_Blk_Width-1); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: reg AE_Blk_Height = [%d]\n",__func__,AE_Blk_Height-1); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: reg AE_Blk_x_num = [%d]\n",__func__,AE_Blk_x_num-1); ++ ++ // set AE_Blk_Width ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BLK_WIDTH, AE_Blk_Width-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_Height ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BLK_HEIGHT, AE_Blk_Height-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_x_num ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_AE_X_BLK_NUM, (AE_Blk_x_num-1)<<8,GOP2_invColor_AE_X_BLK_NUM_mask); // reg_val=real_size-1 ++ ++} ++ ++void GOP2_invColor_Set_AE_Config_Scaling(int AE_Blk_Width, int AE_Blk_Height, int AE_x_blk_num) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ ++ // 1. GOP Set AE config ++ ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: reg AE_Blk_Width = [%d]\n",__func__,AE_Blk_Width-1); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: reg AE_Blk_Height = [%d]\n",__func__,AE_Blk_Height-1); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: reg AE_x_blk_num = [%d]\n",__func__,AE_x_blk_num-1); ++ ++ // set AE_Blk_Width ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BLK_WIDTH, AE_Blk_Width-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_Height ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BLK_HEIGHT, AE_Blk_Height-1); // reg_val=real_size-1 ++ ++ // set AE_Blk_x_num ++ OUTREGMSK16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_AE_X_BLK_NUM, (AE_x_blk_num-1)<<8,GOP2_invColor_AE_X_BLK_NUM_mask); // reg_val=real_size-1 ++ ++} ++ ++ ++void GOP2_invColor_Set_Crop_Config(int crop_x_cor, int crop_y_cor, int AE_Blk_Width, int AE_Blk_Height, int AE_x_res) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ int real_blk_width = AE_Blk_Width+1; // register setting is real_size-1 ++ int real_blk_height = AE_Blk_Height+1;// register setting is real_size-1 ++ int x_offset=0; ++ int y_offset=0; ++ int invTable_idx_offset=0; ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ // x_offset = crop_x_offset % ae_blk_w ++ x_offset = crop_x_cor % real_blk_width; ++ // y_offset = crop_y_offset % ae_blk_h ++ y_offset = crop_y_cor % real_blk_height; ++ // index offset = floor(crop_y_offset / ae_blk_h) x (reg_blk_num_x_m1+1) + floor (crop_x_offset / ae_blk_w) ++ invTable_idx_offset= (crop_y_cor / real_blk_height)*(AE_x_res / real_blk_width)+(crop_x_cor / real_blk_width); ++ ++ // 1. GOP Set crop config: x_offset, y_offset & index_offset ++ ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: x_offset = [%d]\n",__func__,x_offset); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: y_offset = [%d]\n",__func__,y_offset); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: idx_offset = [%d]\n",__func__,invTable_idx_offset); ++ ++ // set x_offset ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_X_PIX_OFFSET, x_offset); ++ ++ // set y_offset ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_Y_PIX_OFFSET, y_offset); ++ ++ // set invTable_idx_offset ++ OUTREG16(GOP2_invColor_Reg_Base+GOP2_invColor_REG_BLK_INDEX_OFFSET, invTable_idx_offset); ++ ++} ++ ++int GOP2_invColor_Engine_Update_Done(void) ++{ ++ unsigned long GOP2_invColor_Reg_Update = 0; ++ unsigned char bDone=0; ++ ++ GOP2_invColor_Reg_Update=mdrv_BASE_REG_GOP2_invColor_AE_Update_Done; ++ ++ if(INREGMSK16(GOP2_invColor_Reg_Update+GOP2_invColor_REG_AE_Update_Done, GOP2_invColor_AE_Update_Done_mask)!=0) ++ { ++ bDone=1; ++ //if get ready, clear it after read ++ OUTREGMSK16(GOP2_invColor_Reg_Update+GOP2_invColor_REG_AE_Update_Done, 0 , GOP2_invColor_AE_Update_Done_mask); ++ } ++ else ++ { ++ bDone=0; ++ } ++ ++ return bDone; ++} ++ ++int GOP2_invColor_CPU_Upate_InvTable(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res, int AE_y_res) ++{ ++ unsigned long GOP2_invColor_Reg_Base = 0; ++ unsigned char *invTable; ++ unsigned char *invTable_rot; ++ int retry_count=0; ++ int blk_origin_num_x=0; ++ int blk_origin_num_y=0; ++ int total_index_used=0; ++ int reg_index_used=0; ++ int num_invTbl_per_regidx=32; ++ int temp_idx=0; ++ int temp_count=0; ++ int temp_data1=0; ++ int temp_data2=0; ++ int temp_x_idx=0; ++ int temp_y_idx=0; ++ ++ ++ GOP2_invColor_Reg_Base = mdrv_BASE_REG_GOP2_invColor; ++ ++ // 1. Count Needed Settings ++ ++ blk_origin_num_x = AE_x_res / AE_Blk_Width; ++ blk_origin_num_y = AE_y_res / AE_Blk_Height; ++ if((blk_origin_num_x>128)||(blk_origin_num_y>90)) ++ { ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: Error! blk_num too big!!! x_num=%d, y_num=%d\n",__func__,blk_origin_num_x,blk_origin_num_y); ++ return FALSE; ++ } ++ total_index_used = blk_origin_num_x * blk_origin_num_y; ++ reg_index_used = total_index_used / num_invTbl_per_regidx; ++ if((total_index_used % num_invTbl_per_regidx)!=0)// if total_index in use is not 32 align, then reg_idx +1 ++ { ++ reg_index_used++; ++ } ++ ++ //assign memory ++ invTable=kmalloc((reg_index_used*num_invTbl_per_regidx) * sizeof(unsigned char),GFP_KERNEL); ++ if (!invTable) ++ { ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: Error! kmalloc error\n",__func__); ++ return FALSE; ++ } ++ invTable_rot=kmalloc((reg_index_used*num_invTbl_per_regidx) * sizeof(unsigned char),GFP_KERNEL); ++ if (!invTable_rot) ++ { ++ kfree(invTable); ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: Error! kmalloc error\n",__func__); ++ return FALSE; ++ } ++ ++ // 2. Wait Inverse HW Engine write AE Inverse Table Done with Interrupt Trigger and then clean Interrupt ++ ++ while(!GOP2_invColor_Engine_Update_Done()) ++ { ++ mdelay(30); ++ if(retry_count>10) ++ { ++ GOP2_invColor_DBG ("[GOP2_invColor]%s: Error! wait no ack\n",__func__); ++ return FALSE; ++ } ++ retry_count++; ++ } ++ ++ ++ // 3. Read Inverse Table ++ ++ for(temp_idx=0;temp_idx>temp_count)& 0x1); ++ } ++ for(temp_count=0;temp_count<16;temp_count++) ++ { ++ invTable[(temp_idx * num_invTbl_per_regidx)+temp_count+16]= ((temp_data2>>temp_count)& 0x1); ++ } ++ } ++ ++ // 4. Do Transpose for Rotate Case ++ ++ for(temp_y_idx=0;temp_y_idx ++#include ++#include ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#define GET_REG8_ADDR_GOP2_invColor(x, y) (x+(y)*2) ++#define GET_REG16_ADDR_GOP2_invColor(x, y) (x+(y)*4) ++ ++ ++ ++/* ========================================================================= */ ++/* Define HW base address */ ++#define BASE_REG_RIU_PA_GOP2_invColor (0x1F000000) ++ ++//GOP Base register defines ++ ++//inverse color base address ++#define mdrv_BASE_REG_GOP2_invColor GET_REG16_ADDR_GOP2_invColor(BASE_REG_RIU_PA_GOP2_invColor, (0x121A00/2)) ++ ++//inverse color engine update done flag address ++#define mdrv_BASE_REG_GOP2_invColor_AE_Update_Done GET_REG16_ADDR_GOP2_invColor(BASE_REG_RIU_PA_GOP2_invColor, (0x121800/2)) ++#define GOP2_invColor_REG_AE_Update_Done BK_REG_GOP2_invColor(0x0A) ++#define GOP2_invColor_AE_Update_Done_mask 0x0100 ++ ++#define BK_REG_GOP2_invColor(reg) ((reg) * 4) ++ ++//-------------------------------------------------------------------------------------------------- ++// Defines ++//-------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------ ++// inverse color settings for GOP2 ++//------------------------------------------------------------------------------ ++ ++#define GOP2_invColor_REG_BASE_SETTINGS BK_REG_GOP2_invColor(0x6C) ++#define GOP2_invColor_enable_mask 0x0001 // 1:enable, 0:disable ++#define GOP2_invColor_gop_output_mode 0x0002 // 1:YUV, 0:RGB ++#define GOP2_invColor_update_mode 0x0004 // 1:by cpu, 0:by engine ++#define GOP2_invColor_color_mode 0x0008 // 1.complementary color, 0:user define ++#define GOP2_invColor_AE_Y_Threshold_mask 0xFF00 ++ ++#define GOP2_invColor_REG_USER_COLOR_RG BK_REG_GOP2_invColor(0x6E) ++#define GOP2_invColor_user_color_R_mask 0x00FF ++#define GOP2_invColor_user_color_G_mask 0xFF00 ++ ++#define GOP2_invColor_REG_USER_COLOR_B BK_REG_GOP2_invColor(0x6F) ++#define GOP2_invColor_user_color_B_mask 0x00FF ++ ++#define GOP2_invColor_REG_AE_X_BLK_NUM BK_REG_GOP2_invColor(0x6F) ++#define GOP2_invColor_AE_X_BLK_NUM_mask 0x7F00 ++ ++#define GOP2_invColor_REG_X_PIX_OFFSET BK_REG_GOP2_invColor(0x75) ++ ++#define GOP2_invColor_REG_Y_PIX_OFFSET BK_REG_GOP2_invColor(0x76) ++ ++#define GOP2_invColor_REG_BLK_INDEX_OFFSET BK_REG_GOP2_invColor(0x77) ++ ++#define GOP2_invColor_REG_BLK_WIDTH BK_REG_GOP2_invColor(0x78) ++ ++#define GOP2_invColor_REG_BLK_HEIGHT BK_REG_GOP2_invColor(0x79) ++ ++#define GOP2_invColor_REG_SRAM_SETTINGS BK_REG_GOP2_invColor(0x7A) ++#define GOP2_invColor_SRAM_ADDR_mask 0x01FF ++#define GOP2_invColor_SRAM_WRITE_enable 0x0200 ++#define GOP2_invColor_SRAM_READ_enable 0x0400 ++#define GOP2_invColor_SRAM_CPU_UPDATE_DONE 0x0800 ++ ++#define GOP2_invColor_REG_SRAM_WRITE_DATA1 BK_REG_GOP2_invColor(0x7B) ++ ++#define GOP2_invColor_REG_SRAM_WRITE_DATA2 BK_REG_GOP2_invColor(0x7C) ++ ++#define GOP2_invColor_REG_SRAM_READ_DATA1 BK_REG_GOP2_invColor(0x7D) ++ ++#define GOP2_invColor_REG_SRAM_READ_DATA2 BK_REG_GOP2_invColor(0x7E) ++ ++ ++#define GOP2_invColor_DEBUG 0 ++#if (GOP2_invColor_DEBUG==1) ++#define GOP2_invColor_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define GOP2_invColor_DBG(fmt, arg...) ++#endif ++ ++//global functions ++void GOP2_invColor_init(void); ++void GOP2_invColor_Enable(unsigned char bEn); ++void GOP2_invColor_Set_UpdateMode(unsigned char bMode); ++void GOP2_invColor_Set_Y_Threshold(int AE_Y_Thres); ++void GOP2_invColor_Set_AE_Config(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res); ++void GOP2_invColor_Set_AE_Config_Scaling(int AE_Blk_Width, int AE_Blk_Height, int AE_x_blk_num); ++void GOP2_invColor_Set_Crop_Config(int crop_x_cor, int crop_y_cor, int AE_Blk_Width, int AE_Blk_Height, int AE_x_res); ++int GOP2_invColor_CPU_Upate_InvTable(int AE_Blk_Width, int AE_Blk_Height, int AE_x_res, int AE_y_res); ++void GOP2_invColor_Debug_Mode(void); ++void GOP2_invColor_DebugMode_UpdateInvTable(void); ++void GOP2_invColor_Debug_Mode_SWupdate_InvTable(int datasize, unsigned char *invTable); +diff --git a/drivers/mstar/fb2/infinity3/mdrv_fb2.c b/drivers/mstar/fb2/infinity3/mdrv_fb2.c +new file mode 100644 +index 00000000..84df8135 +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/mdrv_fb2.c +@@ -0,0 +1,1899 @@ ++ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_general_fb.c ++ * DESCRIPTION For mdrv LinuxBSP Display driver, use frame buffer ++ * architecture ++ * ++ * AUTHOR Chun Fan ++ * ++ * ++ * HISTORY 2008/05/06 initial version ++ * linux/drivers/video/mdrv_general_fb.c ++ * -- mdrv frame buffer device ++ *****************************************************************************/ ++ ++ ++#define mdrv_GEN_FB_C ++ ++#include "mdrv_fb2.h" ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ if(0!=msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ ++ *addr=dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length=size; ++ dmem.kvirt=(unsigned long long)((uintptr_t)virt); ++ dmem.phys=(unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++// update global variables while init/probe ++static void __init mdrvinfinityfb2_updateinfo(void) ++{ ++ static int main_videomemory_size=0; ++ ++ //default settings for global structure of fb_var_screeninfo ++ sg_mdrvinfinityfb2_default_var.xres = 0; ++ sg_mdrvinfinityfb2_default_var.yres = 0; ++ sg_mdrvinfinityfb2_default_var.xres_virtual = sg_mdrvinfinityfb2_default_var.xres; ++ sg_mdrvinfinityfb2_default_var.yres_virtual = sg_mdrvinfinityfb2_default_var.yres * (ANDROID_NUMBER_OF_BUFFERS+1);//double buffer for pan display ++ sg_mdrvinfinityfb2_default_var.width = sg_mdrvinfinityfb2_default_var.xres; ++ sg_mdrvinfinityfb2_default_var.height = sg_mdrvinfinityfb2_default_var.yres; ++ ++ //GWin init, same size as screen ++ genGWinInfo_gop2.u18HStart = 0; ++ genGWinInfo_gop2.u18HEnd = genGWinInfo_gop2.u18HStart + sg_mdrvinfinityfb2_default_var.xres; ++ genGWinInfo_gop2.u18VStart = 0; ++ genGWinInfo_gop2.u18VEnd = genGWinInfo_gop2.u18VStart + sg_mdrvinfinityfb2_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb2_default_var.xres * sg_mdrvinfinityfb2_default_var.yres * ANDROID_BYTES_PER_PIXEL * (ANDROID_NUMBER_OF_BUFFERS+1)); ++ ++ ++ sg_videomemorysize_gop2 = main_videomemory_size; ++ ++ //default settings for global structure of fb_fix_screeninfo ++ sg_mdrvinfinityfb2_fix.smem_start = sg_G3D_fb2_bus_addr1_gop2; ++ sg_mdrvinfinityfb2_fix.smem_len = sg_videomemorysize_gop2; ++ sg_mdrvinfinityfb2_fix.line_length = sg_mdrvinfinityfb2_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ sg_mdrvinfinityfb2_fix.ypanstep = 1; ++ ++ FB2DBGMORE("[FB2 Driver] updateinfo: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], GOPmemorysize = 0x%x \r\n",sg_mdrvinfinityfb2_default_var.xres,sg_mdrvinfinityfb2_default_var.yres,(unsigned int)sg_videomemorysize_gop2); ++ ++} ++ ++// update global variables while setting new resolution by ioctl FBIOPUT_VSCREENINFO ++static int mdrvinfinityfb2_infinity_updateinfo_par(unsigned int setWidth,unsigned int setHeight) ++{ ++ ++ static int main_videomemory_size=0; ++ ++ //update settings for global structure of fb_var_screeninfo ++ sg_mdrvinfinityfb2_default_var.xres = setWidth; ++ sg_mdrvinfinityfb2_default_var.yres = setHeight; ++ sg_mdrvinfinityfb2_default_var.xres_virtual = sg_mdrvinfinityfb2_default_var.xres; ++ sg_mdrvinfinityfb2_default_var.yres_virtual = sg_mdrvinfinityfb2_default_var.yres * (ANDROID_NUMBER_OF_BUFFERS+1);//double buffer for pan display ++ sg_mdrvinfinityfb2_default_var.width = sg_mdrvinfinityfb2_default_var.xres; ++ sg_mdrvinfinityfb2_default_var.height = sg_mdrvinfinityfb2_default_var.yres; ++ ++ //GWin init, same size as screen ++ genGWinInfo_gop2.u18HStart = 0; ++ genGWinInfo_gop2.u18HEnd = genGWinInfo_gop2.u18HStart + sg_mdrvinfinityfb2_default_var.xres; ++ genGWinInfo_gop2.u18VStart = 0; ++ genGWinInfo_gop2.u18VEnd = genGWinInfo_gop2.u18VStart + sg_mdrvinfinityfb2_default_var.yres; ++ main_videomemory_size = (sg_mdrvinfinityfb2_default_var.xres * sg_mdrvinfinityfb2_default_var.yres * ANDROID_BYTES_PER_PIXEL * (ANDROID_NUMBER_OF_BUFFERS+1)); ++ ++ // free memory if it has ++ if(sg_videomemorysize_gop2 > 0) ++ { ++ free_dmem(KEY_DMEM_FB2_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop2), ++ sg_pG3D_fb2_vir_addr1_gop2, ++ sg_G3D_fb2_bus_addr1_gop2); ++ } ++ ++ sg_videomemorysize_gop2 = main_videomemory_size; ++ ++ FB2DBG ("[FB2 Driver] updateinfo_par: GOP_WIDTH = [%d], GOP_HEIGHT = [%d], GOPmemorysize = 0x%x \r\n",sg_mdrvinfinityfb2_default_var.xres,sg_mdrvinfinityfb2_default_var.yres,(unsigned int)sg_videomemorysize_gop2); ++ ++ // allocate new memory ++ if (!(sg_pG3D_fb2_vir_addr1_gop2 = alloc_dmem(KEY_DMEM_FB2_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop2), ++ &sg_G3D_fb2_bus_addr1_gop2))) ++ { ++ FB2DBGERR("[FB2 Driver] Error: updateinfo_par: unable to allocate screen memory\n"); ++ return -ENOMEM; ++ } ++ ++ // prevent initial garbage on screen ; to clean memory ++ memset(CAST_2_IOMEM_CHAR_P sg_pG3D_fb2_vir_addr1_gop2,0, sg_videomemorysize_gop2); ++ ++ //update settings for global structure of fb_fix_screeninfo ++ sg_mdrvinfinityfb2_fix.smem_start = sg_G3D_fb2_bus_addr1_gop2; ++ sg_mdrvinfinityfb2_fix.smem_len = sg_videomemorysize_gop2; ++ sg_mdrvinfinityfb2_fix.line_length = sg_mdrvinfinityfb2_default_var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ FB2DBG("[FB2 Driver] vir=0x%x, phy=0x%x\n", (unsigned int)sg_pG3D_fb2_vir_addr1_gop2, sg_G3D_fb2_bus_addr1_gop2); ++ ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb2_infinity_SetPalette(FB_GOP_PaletteEntry *pPalEntry, int intPalStart,int intPalEnd) ++{ ++ int i = 0; ++ int ret = -1; ++ ++ //open scl0 fclk to load palette ++ if (IS_ERR(gop2_clks[1])) ++ { ++ FB2DBGERR( "[FB2 Driver] Error: SetPalette Fail to get gop fclk of scl!\n" ); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop2_clks[1]); ++ } ++ ++ FB2DBGMORE("Palette value:(B,G,R,A)\n"); ++ ++ //write palette ++ for(i=intPalStart;i<=intPalEnd;i++) ++ { ++ GOP2_Set_Palette_RIU(0, i, pPalEntry[i].BGRA.u8A, pPalEntry[i].BGRA.u8R, pPalEntry[i].BGRA.u8G, pPalEntry[i].BGRA.u8B); ++ ++ //record in global variable ++ stGOPCurrentPalInfo_GOP2[i].BGRA.u8B=pPalEntry[i].BGRA.u8B; ++ stGOPCurrentPalInfo_GOP2[i].BGRA.u8G=pPalEntry[i].BGRA.u8G; ++ stGOPCurrentPalInfo_GOP2[i].BGRA.u8R=pPalEntry[i].BGRA.u8R; ++ stGOPCurrentPalInfo_GOP2[i].BGRA.u8A=pPalEntry[i].BGRA.u8A; ++ FB2DBGMORE("(%d,%d,%d,%d)\n",stGOPCurrentPalInfo_GOP2[i].BGRA.u8B,stGOPCurrentPalInfo_GOP2[i].BGRA.u8G,stGOPCurrentPalInfo_GOP2[i].BGRA.u8R,stGOPCurrentPalInfo_GOP2[i].BGRA.u8A); ++ } ++ ++ //close clk ++ clk_disable_unprepare(gop2_clks[1]); ++ ++ return 0; ++} ++ ++static int mdrvinfinityfb2_set_par(struct fb_info *info) ++{ ++ int ret = 0; ++ FB2DBG( "[FB2 Driver] Test I3!\n" ); ++ ++ ret=mdrvinfinityfb2_infinity_updateinfo_par(info->var.xres,info->var.yres); ++ ++ info->fix.smem_start = sg_mdrvinfinityfb2_fix.smem_start; ++ info->fix.smem_len = sg_mdrvinfinityfb2_fix.smem_len; ++ ++ info->var.width = info->var.xres; ++ info->var.height = info->var.yres; ++ ++ info->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1_gop2); ++ info->fix.line_length = info->var.xres * ANDROID_BYTES_PER_PIXEL; ++ ++ //GOP_Setmode(FALSE, 0,sg_mdrvinfinityfb2_default_var.xres,sg_mdrvinfinityfb2_default_var.yres,sg_G3D_fb2_bus_addr1_gop2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ GOP2_Set_Outputmode(0, sg_mdrvinfinityfb2_default_var.xres,sg_mdrvinfinityfb2_default_var.yres,sg_G3D_fb2_bus_addr1_gop2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL); ++ ++ return ret; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb2_mmap +++------------------------------------------------------------------------------ ++| DESCRIPTION : memory map function, Let user application can get virtual ++| address to access in user space. need pass in physical address ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pinfo | x | | default function type. we only check if NULL ++|--------------------+---+---+------------------------------------------------- ++| vma | x | x | we use Remap-pfn-range will mark the range VM_IO ++| | | | and VM_RESERVED, and save these information in ++| | | | vma +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb2_mmap(struct fb_info *pinfo, struct vm_area_struct *vma) ++{ ++ size_t size; ++ size = 0; ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: mmap, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if (NULL == pinfo) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: mmap, pinfo is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ if (NULL == vma) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: mmap, vma is NULL pointer !\n"); ++ return -ENOTTY; ++ } ++ ++ size = vma->vm_end - vma->vm_start; ++ ++ vma->vm_pgoff += ((sg_G3D_fb2_bus_addr1_gop2 ) >> PAGE_SHIFT); ++ ++ FB2DBG( ++ "[FB2 Driver] mmap vma->vm_start=%x\n vma->vm_end=%x\n vma->vm_pgoff =%x\n", ++ (unsigned int) vma->vm_start, (unsigned int)vma->vm_end , ++ (unsigned int)vma->vm_pgoff); ++ ++ //vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ /* Remap-pfn-range will mark the range VM_IO and VM_RESERVED */ ++ if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, size, vma->vm_page_prot)) ++ return -EAGAIN; ++ ++ return 0; ++} ++ ++//sw update inverse color's inverse table thread when rotate case happens ++static int mdrvinfinityfb2_SWupdate_InvTable(void *arg) ++{ ++ int ret=0; ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ ++ ret=GOP2_invColor_CPU_Upate_InvTable(genAE_info_gop2.u32AEBlkWidth, ++ genAE_info_gop2.u32AEBlkHeight, ++ genAE_info_gop2.u32AEDisplayWidth, ++ genAE_info_gop2.u32AEDisplayHeight); ++ if(!ret)//if update wrong, break ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: mdrvinfinityfb2_SWupdate_InvTable wrong!\n"); ++ genTreadisError_gop2=1; ++ break; ++ } ++ ++ ++ } ++ ++ return 0; ++ ++} ++ ++static int mdrvinfinityfb2_SWupdate_InvTable_debugmode(void *arg) ++{ ++ ++ while(1) ++ { ++ if (kthread_should_stop()) break; ++ ++ GOP2_invColor_DebugMode_UpdateInvTable(); ++ msleep(1000); ++ } ++ ++ return 0; ++ ++} ++ ++ ++//check whether need doing sw update inverse color's inverse table or not ++static void mdrvinfinityfb2_checkInvTable_UpdateMode(void) ++{ ++ int idx=0; ++ int ret; ++ ++ if((genInv_Color_gop2==1) && (genSC_info_gop2.bRotateEn==1)) ++ { ++ idx=1; ++ } ++ else ++ { ++ idx=0; ++ } ++ ++ if(genTreadisError_gop2==1) ++ { ++ pSWupdateInvThread_gop2=NULL; ++ genTreadisError_gop2=0; ++ } ++ ++ if(idx==1)//enable thread ++ { ++ if(pSWupdateInvThread_gop2==NULL) ++ { ++ pSWupdateInvThread_gop2 = kthread_create(mdrvinfinityfb2_SWupdate_InvTable,(void *)&pSWupdateInvThread_gop2,"GOP2_SWupdate_InvColor"); ++ if (IS_ERR(pSWupdateInvThread_gop2)) ++ { ++ ret = PTR_ERR(pSWupdateInvThread_gop2); ++ pSWupdateInvThread_gop2 = NULL; ++ FB2DBGERR("[FB2 Driver] ERROR: mdrvinfinityfb2_checkInvTable_UpdateMode wrong! Create thread fail! ret=%d\n",ret); ++ } ++ else ++ { ++ wake_up_process(pSWupdateInvThread_gop2); ++ } ++ } ++ } ++ else if (idx==0 && (pSWupdateInvThread_gop2!=NULL))//disable thread ++ { ++ kthread_stop(pSWupdateInvThread_gop2); ++ pSWupdateInvThread_gop2 = NULL; ++ } ++ ++} ++ ++ ++ ++// FB Ioctl Functions ++ ++int _MDrv_FBIO_IOC_Get_SUPINFO_GOP2(unsigned long arg) ++{ ++ FB_GOP_SUPINF_CONFIG stCfg; ++ ++ // enable gwin is in GOP01 ++ ++ stCfg.bKeyAlpha = 1; ++ stCfg.bConstAlpha = 1; ++ stCfg.bPixelAlpha = 1; ++ stCfg.bColFmt[COLORFMT_ARGB8888] = 0; ++ stCfg.bColFmt[COLORFMT_RGB565] = 0; ++ stCfg.bColFmt[COLORFMT_YUV422] = 0; ++ stCfg.bColFmt[COLORFMT_I8PALETTE]= 1; ++ stCfg.u32MaxWidth = 1920; ++ stCfg.u32MaxHeight= 1080; ++ ++ if(copy_to_user((FB_GOP_SUPINF_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_SUPINF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_GWIN_GOP2(unsigned long arg) ++{ ++ FB_GOP_GWIN_CONFIG stCfg; ++ ++ stCfg.u18HStart = genGWinInfo_gop2.u18HStart; ++ stCfg.u18HEnd = genGWinInfo_gop2.u18HEnd; ++ stCfg.u18VStart = genGWinInfo_gop2.u18VStart; ++ stCfg.u18VEnd = genGWinInfo_gop2.u18VEnd; ++ ++ if(copy_to_user((FB_GOP_GWIN_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_GWIN_GOP2(unsigned long arg) ++{ ++ unsigned long GOP_Reg_Base = 0; ++ FB_GOP_GWIN_CONFIG stCfg; ++ unsigned short MIU_BUS = 0x04; ++ unsigned short u16FrameBuffer_Bytes_Per_Pixel = ANDROID_BYTES_PER_PIXEL; ++ unsigned long u32TempVal = 0; ++ unsigned long GOP_Reg_DB = GOP_BANK_DOUBLE_WR_G2; ++ int Panel_Width = 0; ++ int Panel_Height = 0; ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: _MDrv_FBIO_IOC_Set_GWIN, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&stCfg, (FB_GOP_GWIN_CONFIG __user *)arg, sizeof(FB_GOP_GWIN_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ Panel_Width = (int)(stCfg.u18HEnd-stCfg.u18HStart+1); ++ Panel_Height = (int)(stCfg.u18VEnd-stCfg.u18VStart+1); ++ ++ /// GOP0_0 settings ++ GOP_Reg_Base = mdrv_BASE_REG_GOP20_PA; ++ ++ // GOP global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_0E,(Panel_Width >>1)+1);//miu efficiency = Stretch Window H size (unit:2 pixel) /2 +1 ++ ++ // GOP display area global settings ++ OUTREG16(GOP_Reg_Base+REG_GOP_30,Panel_Width >>1); //Stretch Window H size (unit:2 pixel) ++ OUTREG16(GOP_Reg_Base+REG_GOP_31,Panel_Height); //Stretch window V size ++ ++ // gwin info is in GOP01 ++ GOP_Reg_Base = mdrv_BASE_REG_GOP21_PA; ++ ++ // switch to subbank01 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(1); ++ } ++ ++ genGWinInfo_gop2.u18HStart = stCfg.u18HStart; ++ genGWinInfo_gop2.u18HEnd = stCfg.u18HEnd; ++ genGWinInfo_gop2.u18VStart = stCfg.u18VStart; ++ genGWinInfo_gop2.u18VEnd = stCfg.u18VEnd; ++ ++ // GOP Display Setting, GWIN ++ // 2.1 GWIN display area in panel : : H Start postion and end information ++ u32TempVal=(genGWinInfo_gop2.u18HStart*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_04,u32TempVal); // H start ++ u32TempVal=(genGWinInfo_gop2.u18HEnd*u16FrameBuffer_Bytes_Per_Pixel)>>MIU_BUS; ++ OUTREG16(GOP_Reg_Base+REG_GOP_05,u32TempVal); // H end ++ ++ // 2.2 GWIN display area in panel : V Start postion and end information ++ OUTREG16(GOP_Reg_Base+REG_GOP_06,genGWinInfo_gop2.u18VStart); // V start line ++ OUTREG16(GOP_Reg_Base+REG_GOP_08,genGWinInfo_gop2.u18VEnd); // V end line ++ ++ // switch back to subbank00 if there's no direct bank ++ if(mdrv_BASE_REG_GOP21_PA==mdrv_BASE_REG_GOP20_PA) ++ { ++ GOP2_SwitchSubBank(0); ++ } ++ ++ //write gop register ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, GOP_Reg_DB, (GOP_BANK_DOUBLE_WR_MSK|GOP_BANK_SEL_MSK)); ++ OUTREGMSK16(GOP_Reg_Base+REG_GOP_7F, 0, GOP_BANK_DOUBLE_WR_MSK); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_EnGOP_GOP2(unsigned long arg) ++{ ++ unsigned char enGOP; ++ ++ GOP2_Get_Enable_GWIN(0, &enGOP); ++ ++ //remove check scaler's switch later in I3 ++ if(enGOP && INREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_68,0x0001)) ++ enGOP=1; ++ else ++ enGOP=0; ++ ++ if(copy_to_user((unsigned char __user *)arg, &enGOP, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_EnGOP_GOP2(unsigned long arg) ++{ ++ unsigned char enGOP; ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: _MDrv_FBIO_IOC_Set_EnGOP, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&enGOP, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] enable GOP=%d \n",enGOP); ++ ++ // record in global variable ++ genGWIN_gop2=enGOP; ++ ++ // this switch will let scaler handle, remove later in I3 ++ // enable/disable gop switch at scaler ++ if(enGOP) ++ OUTREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_68,0x0001,0x0001); ++ else ++ OUTREGMSK16(GET_REG16_ADDR(BASE_REG_RIU_PA, (0x121A00/2))+REG_GOP_68,0x0000,0x0001); ++ ++ GOP2_Set_Enable_GWIN(0,enGOP); ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Get_Alpha_GOP2(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ int alpha_type = 0; ++ int alpha_value = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ // get alpha blending settings from register ++ GOP2_Get_Alpha(0,&alpha_type,&alpha_value); ++ ++ // copy result from register ++ stCfg.bEn = genGOPALPHA_gop2.bEn; ++ stCfg.enAlphaType = (FB_GOP_ALPHA_TYPE)alpha_type; ++ stCfg.u8Alpha = (unsigned char)alpha_value; ++ ++ // record settings in global variables ++ genGOPALPHA_gop2.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA_gop2.u8Alpha=stCfg.u8Alpha; ++ ++ if(copy_to_user((FB_GOP_ALPHA_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Constant_Alpha_GOP2(unsigned long arg) ++{ ++ FB_GOP_ALPHA_CONFIG stCfg; ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: _MDrv_FBIO_IOC_Set_Constant_Alpha, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_ALPHA_CONFIG __user *)arg, sizeof(FB_GOP_ALPHA_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] Set alpha enable=%d, type=%d, constant alpha value=0x%x \n",(int)stCfg.bEn, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ ++ if(stCfg.bEn) ++ { ++ GOP2_Set_Constant_Alpha(0, (int)stCfg.enAlphaType, stCfg.u8Alpha); ++ } ++ else ++ { ++ GOP2_Set_Constant_Alpha(0, CONST_ALPHA, 0);//close alpha blending, let gop always shows ++ } ++ ++ genGOPALPHA_gop2.bEn=stCfg.bEn; ++ genGOPALPHA_gop2.enAlphaType=stCfg.enAlphaType; ++ genGOPALPHA_gop2.u8Alpha=stCfg.u8Alpha; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Get_Color_Key_GOP2(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ int Enable = 0; ++ int Red = 0; ++ int Green = 0; ++ int Blue = 0; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ GOP2_Get_Color_Key(0,&Enable,&Red,&Green,&Blue); ++ ++ // enable/disable ++ stCfg.bEn = (unsigned char)Enable; ++ ++ // colorkey value ++ stCfg.u8R = (unsigned char)Red; ++ stCfg.u8G = (unsigned char)Green; ++ stCfg.u8B = (unsigned char)Blue; ++ ++ genGOPCOLORKEY_gop2.bEn=stCfg.bEn; ++ genGOPCOLORKEY_gop2.u8R=stCfg.u8R; ++ genGOPCOLORKEY_gop2.u8G=stCfg.u8G; ++ genGOPCOLORKEY_gop2.u8B=stCfg.u8B; ++ ++ if(copy_to_user((FB_GOP_COLORKEY_CONFIG __user *)arg, &stCfg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _MDrv_FBIO_IOC_Set_Color_Key_GOP2(unsigned long arg) ++{ ++ FB_GOP_COLORKEY_CONFIG stCfg; ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: _MDrv_FBIO_IOC_Set_Color_Key, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ if(copy_from_user(&stCfg, (FB_GOP_COLORKEY_CONFIG __user *)arg, sizeof(FB_GOP_COLORKEY_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] Set ColorKey enable=%d, R=0x%x, G=0x%x, B=0x%x\n", (int)stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ ++ GOP2_Set_Color_Key(0, stCfg.bEn, stCfg.u8R, stCfg.u8G, stCfg.u8B); ++ genGOPCOLORKEY_gop2.bEn=stCfg.bEn; ++ genGOPCOLORKEY_gop2.u8R=stCfg.u8R; ++ genGOPCOLORKEY_gop2.u8G=stCfg.u8G; ++ genGOPCOLORKEY_gop2.u8B=stCfg.u8B; ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_imageblit_GOP2(struct fb_info *info,unsigned long arg) ++{ ++ int ret = 0; ++ ++// this ioctl is unused, the same fuction can be accessed by fb_ops -> fb_imageblit ++#if 0 ++ struct fb_image stCfg; ++ int i = 0; ++ ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: _MDrv_FBIO_IOC_imageblit, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&stCfg, (struct fb_image __user *)arg, sizeof(const struct fb_image))) ++ { ++ return -EFAULT; ++ } ++ ++ if (NULL == stCfg.data) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR:in mdrvinfinityfb2_ioctl, fb_image.data is NULL pointer\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.fg_color>255) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.bg_color>255) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (stCfg.width>1920) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ if (stCfg.height>1920) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ ++ if (info->fix.visual == FB_VISUAL_TRUECOLOR || info->fix.visual == FB_VISUAL_DIRECTCOLOR ) ++ { ++ for(i=0;i<(stCfg.width*stCfg.height);i++) ++ { ++ if(stCfg.data[i]>255) ++ { ++ ret = 1; ++ } ++ } ++ if(ret) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR:in mdrvinfinityfb_ioctl, parameter wrong\r\n"); ++ return -EFAULT; ++ } ++ } ++ ++ FB2DBGMORE( "[FB2 Driver] Imgblit test, dst (x,y)=(%d,%d), width=%d, height=%d, colordepth=%d \n" ,stCfg.dx,stCfg.dy,stCfg.width,stCfg.height,stCfg.depth); ++ ++ sys_imageblit(info,&stCfg); ++#endif ++ ++ return ret; ++} ++ ++int _MDrv_FBIO_IOC_Set_Palette_GOP2(unsigned long arg) ++{ ++ FB_GOP_PaletteEntry stCfg[256]; ++ ++ if(copy_from_user(&stCfg, (FB_GOP_PaletteEntry __user *)arg, sizeof(FB_GOP_PaletteEntry)*256)) ++ { ++ return -EFAULT; ++ } ++ ++ mdrvinfinityfb2_infinity_SetPalette(stCfg,0,255); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_EnInvColor_GOP2(unsigned long arg) ++{ ++ unsigned char enInvColor; ++ int ret=0; ++ ++ if (sg_videomemorysize_gop2<1) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: _MDrv_FBIO_IOC_Set_EnInvColor, memory is not set! Please use ioctl FBIOPUT_VSCREENINFO first!\n"); ++ return -ENOMEM; ++ } ++ ++ if(copy_from_user(&enInvColor, (unsigned char __user *)arg, sizeof(unsigned char))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] enable inverse color=%d \n",enInvColor); ++ ++ // record in global variable ++ genInv_Color_gop2=enInvColor; ++ ++ GOP2_invColor_Enable(enInvColor); ++ ++ //check whether do sw update inverse color ++ mdrvinfinityfb2_checkInvTable_UpdateMode(); ++ ++ if(enInvColor==1) ++ { ++ GOP2_invColor_Debug_Mode(); ++ ++ if(pSWupdateInvDebugThread_gop2==NULL) ++ { ++ pSWupdateInvDebugThread_gop2 = kthread_create(mdrvinfinityfb2_SWupdate_InvTable_debugmode,(void *)&pSWupdateInvDebugThread_gop2,"GOP2_debug_SWupdate_InvColor"); ++ if (IS_ERR(pSWupdateInvDebugThread_gop2)) ++ { ++ ret=PTR_ERR(pSWupdateInvDebugThread_gop2); ++ pSWupdateInvDebugThread_gop2 = NULL; ++ FB2DBGERR("[FB2 Driver] ERROR: debug mode! Create thread fail!%d\n",ret); ++ } ++ else ++ { ++ wake_up_process(pSWupdateInvDebugThread_gop2); ++ } ++ } ++ } ++ else if((enInvColor==0)&&(pSWupdateInvDebugThread_gop2!=NULL)) ++ { ++ kthread_stop(pSWupdateInvDebugThread_gop2); ++ pSWupdateInvDebugThread_gop2 = NULL; ++ } ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_AEinfoConfig_GOP2(unsigned long arg) ++{ ++ FB_GOP_INVCOLOR_AE_CONFIG stAECfg; ++ unsigned long tempcorpAEwidth=0; ++ unsigned long tempcorpAEheight=0; ++ int tempAEblkwidth=0; ++ int tempAEblkheight=0; ++ int tempAEblkxnum=0; ++ ++ if(copy_from_user(&stAECfg, (FB_GOP_INVCOLOR_AE_CONFIG __user *)arg, sizeof(FB_GOP_INVCOLOR_AE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] set AE config, AExres=%d, AEyres=%d, AEblkW=%d, AEblkH=%d\n", ++ (int)stAECfg.u32AEDisplayWidth,(int)stAECfg.u32AEDisplayHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight); ++ ++ // record in global variable ++ genAE_info_gop2.u32AEDisplayWidth = stAECfg.u32AEDisplayWidth; ++ genAE_info_gop2.u32AEDisplayHeight = stAECfg.u32AEDisplayHeight; ++ genAE_info_gop2.u32AEBlkWidth = stAECfg.u32AEBlkWidth; ++ genAE_info_gop2.u32AEBlkHeight = stAECfg.u32AEBlkHeight; ++ ++ // when scaling happens, change AE block size with this scale ++ if(genSC_info_gop2.bScalingEn) ++ { ++ if((genAE_info_gop2.u32AEBlkWidth!=0)&&(genAE_info_gop2.u32AEBlkHeight!=0)&&(genAE_info_gop2.u32AEDisplayWidth!=0)&&(genAE_info_gop2.u32AEDisplayHeight!=0)) ++ { ++ if(genSC_info_gop2.bCropEn)//if do crop, should add crop information to calculate scaling ratio ++ { ++ if(genSC_info_gop2.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempcorpAEwidth=genSC_info_gop2.u32CropYend-genSC_info_gop2.u32CropYstart; ++ tempcorpAEheight=genSC_info_gop2.u32CropXend-genSC_info_gop2.u32CropXstart; ++ tempAEblkwidth=((int)genAE_info_gop2.u32AEBlkWidth*(int)genSC_info_gop2.u32ScalerHeight/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info_gop2.u32AEBlkHeight*(int)genSC_info_gop2.u32ScalerWidth/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info_gop2.u32AEDisplayHeight/(int)genAE_info_gop2.u32AEBlkHeight); ++ GOP2_invColor_Set_AE_Config_Scaling(tempAEblkheight,tempAEblkwidth,tempAEblkxnum); ++ } ++ else ++ { ++ tempcorpAEwidth=genSC_info_gop2.u32CropXend-genSC_info_gop2.u32CropXstart; ++ tempcorpAEheight=genSC_info_gop2.u32CropYend-genSC_info_gop2.u32CropYstart; ++ tempAEblkwidth=((int)genAE_info_gop2.u32AEBlkWidth*(int)genSC_info_gop2.u32ScalerWidth/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info_gop2.u32AEBlkHeight*(int)genSC_info_gop2.u32ScalerHeight/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info_gop2.u32AEDisplayHeight/(int)genAE_info_gop2.u32AEBlkHeight); ++ GOP2_invColor_Set_AE_Config_Scaling(tempAEblkwidth,tempAEblkheight,tempAEblkxnum); ++ } ++ } ++ else// if no crop, calculate the scaling ratio directly ++ { ++ if(genSC_info_gop2.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempAEblkwidth=((int)genAE_info_gop2.u32AEBlkWidth*(int)genSC_info_gop2.u32ScalerHeight/(int)genAE_info_gop2.u32AEDisplayWidth); ++ tempAEblkheight=((int)genAE_info_gop2.u32AEBlkHeight*(int)genSC_info_gop2.u32ScalerWidth/(int)genAE_info_gop2.u32AEDisplayHeight); ++ tempAEblkxnum=((int)genAE_info_gop2.u32AEDisplayHeight/(int)genAE_info_gop2.u32AEBlkHeight); ++ GOP2_invColor_Set_AE_Config_Scaling(tempAEblkheight,tempAEblkwidth,tempAEblkxnum); ++ } ++ else ++ { ++ tempAEblkwidth=((int)genAE_info_gop2.u32AEBlkWidth*(int)genSC_info_gop2.u32ScalerWidth/(int)genAE_info_gop2.u32AEDisplayWidth); ++ tempAEblkheight=((int)genAE_info_gop2.u32AEBlkHeight*(int)genSC_info_gop2.u32ScalerHeight/(int)genAE_info_gop2.u32AEDisplayHeight); ++ tempAEblkxnum=((int)genAE_info_gop2.u32AEDisplayHeight/(int)genAE_info_gop2.u32AEBlkHeight); ++ GOP2_invColor_Set_AE_Config_Scaling(tempAEblkwidth,tempAEblkheight,tempAEblkxnum); ++ } ++ } ++ } ++ else ++ { ++ FB2DBGERR( "[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_AEinfoConfig fail2!!! No AE info\n"); ++ return -EFAULT; ++ } ++ } ++ else//if disable scaling, set original settings ++ { ++ if(genSC_info_gop2.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP2_invColor_Set_AE_Config((int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP2_invColor_Set_AE_Config((int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEDisplayWidth); ++ } ++ } ++ ++ if(genSC_info_gop2.bCropEn)//if crop enable, reset crop information when AE info change ++ { ++ if(genSC_info_gop2.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP2_invColor_Set_Crop_Config((int)genSC_info_gop2.u32CropXstart,(int)genSC_info_gop2.u32CropYstart,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP2_invColor_Set_Crop_Config((int)genSC_info_gop2.u32CropXstart,(int)genSC_info_gop2.u32CropYstart,(int)stAECfg.u32AEBlkWidth,(int)stAECfg.u32AEBlkHeight,(int)stAECfg.u32AEDisplayWidth); ++ } ++ } ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_YThres_GOP2(unsigned long arg) ++{ ++ unsigned long YThres; ++ ++ if(copy_from_user(&YThres, (unsigned long __user *)arg, sizeof(unsigned long))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] set Y threshold=%d \n",(int)YThres); ++ ++ // record in global variable ++ genY_Thres_gop2=YThres; ++ ++ GOP2_invColor_Set_Y_Threshold((int)YThres); ++ ++ return 0; ++} ++ ++int _MDrv_FBIO_IOC_Set_ScalerinfoConfig_GOP2(unsigned long arg) ++{ ++ FB_GOP_INVCOLOR_SCALER_CONFIG stSclCfg; ++ unsigned long tempcorpAEwidth=0; ++ unsigned long tempcorpAEheight=0; ++ int tempAEblkwidth=0; ++ int tempAEblkheight=0; ++ int tempAEblkxnum=0; ++ int tempAEblkynum=0; ++ ++ if(copy_from_user(&stSclCfg, (FB_GOP_INVCOLOR_SCALER_CONFIG __user *)arg, sizeof(FB_GOP_INVCOLOR_SCALER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ FB2DBG( "[FB2 Driver] set Scl config, CropEn=%d, ScalingEn=%d, RotateEn=%d\n", ++ (int)stSclCfg.bCropEn,(int)stSclCfg.bScalingEn,(int)stSclCfg.bRotateEn); ++ ++ if((stSclCfg.u32ScalerWidth<1)||(stSclCfg.u32ScalerWidth>1920)) ++ { ++ FB2DBGERR( "[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! parameter wrong\n"); ++ return -EFAULT; ++ } ++ if((stSclCfg.u32ScalerHeight<1)||(stSclCfg.u32ScalerHeight>1920)) ++ { ++ FB2DBGERR( "[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! parameter wrong\n"); ++ return -EFAULT; ++ } ++ ++ // record in global variable ++ genSC_info_gop2.bCropEn = stSclCfg.bCropEn; ++ genSC_info_gop2.bScalingEn = stSclCfg.bScalingEn; ++ genSC_info_gop2.u32ScalerWidth = stSclCfg.u32ScalerWidth; ++ genSC_info_gop2.u32ScalerHeight= stSclCfg.u32ScalerHeight; ++ genSC_info_gop2.u32CropXstart = stSclCfg.u32CropXstart; ++ genSC_info_gop2.u32CropXend = stSclCfg.u32CropXend; ++ genSC_info_gop2.u32CropYstart = stSclCfg.u32CropYstart; ++ genSC_info_gop2.u32CropYend = stSclCfg.u32CropYend; ++ // rotate will be get from ISP driver ++ //genSC_info_gop2.bRotateEn = stSclCfg.bRotateEn; ++ //genSC_info_gop2.enRotateA = stSclCfg.enRotateA; ++ ++ if(stSclCfg.bCropEn) ++ { ++ if((genAE_info_gop2.u32AEBlkWidth!=0)&&(genAE_info_gop2.u32AEBlkHeight!=0)&&(genAE_info_gop2.u32AEDisplayWidth!=0)&&(genAE_info_gop2.u32AEDisplayHeight!=0)) ++ { ++ if(genSC_info_gop2.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ GOP2_invColor_Set_Crop_Config((int)stSclCfg.u32CropXstart,(int)stSclCfg.u32CropYstart,(int)genAE_info_gop2.u32AEBlkHeight,(int)genAE_info_gop2.u32AEBlkWidth,(int)genAE_info_gop2.u32AEDisplayHeight); ++ } ++ else ++ { ++ GOP2_invColor_Set_Crop_Config((int)stSclCfg.u32CropXstart,(int)stSclCfg.u32CropYstart,(int)genAE_info_gop2.u32AEBlkWidth,(int)genAE_info_gop2.u32AEBlkHeight,(int)genAE_info_gop2.u32AEDisplayWidth); ++ } ++ } ++ else ++ { ++ FB2DBGERR( "[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_ScalerinfoConfig fail!!! No AE info\n"); ++ return -EFAULT; ++ } ++ } ++ ++ // when scaling happens, change AE block size with this scale ++ if(stSclCfg.bScalingEn) ++ { ++ if((genAE_info_gop2.u32AEBlkWidth!=0)&&(genAE_info_gop2.u32AEBlkHeight!=0)&&(genAE_info_gop2.u32AEDisplayWidth!=0)&&(genAE_info_gop2.u32AEDisplayHeight!=0)) ++ { ++ if(stSclCfg.bCropEn)//if do crop, should add crop information to calculate scaling ratio ++ { ++ if(genSC_info_gop2.bRotateEn)//if do rotate, switch AE's W and H ++ { ++ tempcorpAEwidth=genSC_info_gop2.u32CropYend-genSC_info_gop2.u32CropYstart; ++ tempcorpAEheight=genSC_info_gop2.u32CropXend-genSC_info_gop2.u32CropXstart; ++ tempAEblkwidth=((int)genAE_info_gop2.u32AEBlkWidth*(int)genSC_info_gop2.u32ScalerHeight/(int)tempcorpAEwidth); ++ tempAEblkheight=((int)genAE_info_gop2.u32AEBlkHeight*(int)genSC_info_gop2.u32ScalerWidth/(int)tempcorpAEheight); ++ tempAEblkxnum=((int)genAE_info_gop2.u32AEDisplayHeight/(int)genAE_info_gop2.u32AEBlkHeight); ++ tempAEblkynum=((int)genAE_info_gop2.u32AEDisplayWidth/(int)genAE_info_gop2.u32AEBlkWidth); ++ if(tempAEblkheight > 0) ++ { ++ while(((genSC_info_gop2.u32ScalerWidth%tempAEblkheight)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkheight++; ++ if(tempAEblkheight>genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info_gop2.u32ScalerWidth%tempAEblkwidth)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkwidth++; ++ if(tempAEblkwidth>genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info_gop2.u32ScalerWidth%tempAEblkheight)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkheight++; ++ if(tempAEblkheight>genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num 0) ++ { ++ while(((genSC_info_gop2.u32ScalerWidth%tempAEblkwidth)!=0))//find proper blk_width, scaler's width mod blk_width should be 0 ++ { ++ tempAEblkwidth++; ++ if(tempAEblkwidth>genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ } ++ if(tempAEblkynum > 0) ++ { ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkheight=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkwidth*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num genSC_info_gop2.u32ScalerWidth) ++ { ++ tempAEblkwidth=genSC_info_gop2.u32ScalerWidth; ++ break; ++ } ++ } ++ while(genSC_info_gop2.u32ScalerHeight>(tempAEblkheight*tempAEblkynum))//find proper blk_height, add 1 if blk_H * blk_y_num (128*90*4)) ++ { ++ FB2DBG( "[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_SW_InvTable fail, max size is 128*90 \n"); ++ return -EFAULT; ++ } ++ ++ if(swinvTable.size<1) ++ { ++ FB2DBG( "[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_SW_InvTable fail, min size is 1 \n"); ++ return -EFAULT; ++ } ++ ++ invTableSize=(swinvTable.size/4); ++ invColTable=kmalloc(invTableSize*sizeof(unsigned char),GFP_KERNEL); ++ if (!invColTable) ++ { ++ FB2DBGERR("[FB2 Driver] Error: _MDrv_FBIO_IOC_Set_SW_InvTable: unable to kmalloc\n"); ++ return -ENOMEM; ++ } ++ memset(invColTable,0, invTableSize*sizeof(unsigned char)); ++ ++ ++ for(i=0;i buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++ ++} ++ ++DEVICE_ATTR(gop2info, 0644, gop2info_show, gop2info_store); ++ ++ ++static int mdrvinfinityfb2_suspend(struct platform_device *pdev, ++ pm_message_t state) ++{ ++ int clockIdxtemp=0; ++ FB2DBG("[FB2 Driver] in mdrvinfinityfb2_suspend \r\n"); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop2 ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop2_clks[clockIdxtemp]); ++ } ++ } ++ //clk_disable_unprepare(gop_psram_clk); ++ return 0; ++} ++ ++static int mdrvinfinityfb2_resume(struct platform_device *pdev) ++{ ++ //dma_addr_t fb2_PHY_ADD_SHOW=0; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ // open all needed clocks ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop2 ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop2_clks[clockIdxtemp])) ++ { ++ FB2DBGERR( "[FB2 Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop2_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop2_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ FB2DBG("[FB2 Driver] mdrvinfinityfb2_resume \r\n"); ++ ++ GOP2_Setmode(TRUE, 0,sg_mdrvinfinityfb2_default_var.xres,sg_mdrvinfinityfb2_default_var.yres,sg_G3D_fb2_bus_addr1_gop2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ //set palette ++ mdrvinfinityfb2_infinity_SetPalette(stGOPCurrentPalInfo_GOP2,0,255); ++ ++ return 0; ++} ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb2_probe +++------------------------------------------------------------------------------ ++| DESCRIPTION : Initialization. Initial HW, fill table, when load module, ++| this function will be called. ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb2_probe(struct platform_device *dev) ++{ ++ struct fb_info *pinfo = NULL; ++ int retval = -ENOMEM; ++ int ret=-1; ++ int clockIdxtemp=0; ++ ++ if (NULL == dev) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: in mdrvinfinityfb2_prob: dev is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ // open all needed clocks ++ num_parents_clocks_gop2 = of_clk_get_parent_count(dev->dev.of_node); ++ gop2_clks=kzalloc(((sizeof(struct clk *) * num_parents_clocks_gop2)),GFP_KERNEL); ++ ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop2 ; clockIdxtemp++) ++ { ++ gop2_clks[clockIdxtemp]= of_clk_get(dev->dev.of_node, clockIdxtemp); ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ if (IS_ERR(gop2_clks[clockIdxtemp])) ++ { ++ FB2DBGERR( "[FB2 Driver] ERROR: Fail to get gop clk! Clock idx=%d\n",clockIdxtemp); ++ kfree(gop2_clks); ++ return ret; ++ } ++ else ++ { ++ clk_prepare_enable(gop2_clks[clockIdxtemp]); ++ } ++ } ++ } ++ ++ // init global variable ++ mdrvinfinityfb2_updateinfo(); ++ ++ pinfo = framebuffer_alloc(sizeof(struct fb_info), &dev->dev); ++ if (!pinfo) ++ goto err; ++ ++ // copy data for register framebuffer ++ pinfo->screen_base = (char *)CAST_2_IOMEM_CHAR_P( sg_pG3D_fb2_vir_addr1_gop2); ++ pinfo->fbops = &sg_mdrvinfinityfb2_ops; ++ pinfo->var = sg_mdrvinfinityfb2_default_var; ++ pinfo->fix = sg_mdrvinfinityfb2_fix; ++ pinfo->pseudo_palette = pinfo->par; ++ pinfo->par = NULL; ++ pinfo->flags = FBINFO_FLAG_DEFAULT; ++ ++ // allocate color map ++ // 256 is following to the vfb.c ++ retval = fb_alloc_cmap(&pinfo->cmap, 256, 0); ++ if (retval < 0) ++ goto err1; ++ ++ // register our fb to fbmem.c ++ retval = register_framebuffer(pinfo); ++ if (retval < 0) ++ goto err2; ++ ++ // set data to device ++ platform_set_drvdata(dev, pinfo); ++ ++ // set gop register settings ++ GOP2_Setmode(FALSE, 0,sg_mdrvinfinityfb2_default_var.xres,sg_mdrvinfinityfb2_default_var.yres,sg_G3D_fb2_bus_addr1_gop2,ANDROID_FB_FORMAT,ANDROID_BYTES_PER_PIXEL, 0); ++ ++ // set gop inverse color init settings ++ GOP2_invColor_init(); ++ ++ // set init palette ++ mdrvinfinityfb2_infinity_SetPalette(DefaultPaletteEntry,0,255); ++ ++ // register sysfs ++ ret = device_create_file(&dev->dev, &dev_attr_gop2info); ++ if (ret != 0) ++ { ++ dev_err(&dev->dev, ++ "[FB2 Driver] Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ else ++ { ++ FB2DBGMORE("[FB2 Driver] device attr ok\n"); ++ } ++ ++ return 0; ++ ++err2: ++ fb_dealloc_cmap(&pinfo->cmap); ++err1: ++ framebuffer_release(pinfo); ++err: ++ ++ free_dmem(KEY_DMEM_FB2_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop2), ++ sg_pG3D_fb2_vir_addr1_gop2, ++ sg_G3D_fb2_bus_addr1_gop2); ++ ++ return retval; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : mdrvinfinityfb2_remove +++------------------------------------------------------------------------------ ++| DESCRIPTION : we free memory, release frame buffer here ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| dev | x | | default function type. we only check if NULL +++------------------------------------------------------------------------------ ++*/ ++static int mdrvinfinityfb2_remove(struct platform_device *dev) ++{ ++ struct fb_info *pinfo; ++ int clockIdxtemp=0; ++ pinfo = 0; ++ ++ if (NULL == dev) ++ { ++ FB2DBGERR("[FB2 Driver] ERROR: mdrvinfinityfb2_remove: dev is NULL pointer \n"); ++ return -ENOTTY; ++ } ++ ++ pinfo = platform_get_drvdata(dev); ++ if (pinfo) ++ { ++ unregister_framebuffer(pinfo); ++ ++ free_dmem(KEY_DMEM_FB2_BUF, ++ PAGE_ALIGN(sg_videomemorysize_gop2), ++ sg_pG3D_fb2_vir_addr1_gop2, ++ sg_G3D_fb2_bus_addr1_gop2); ++ ++ framebuffer_release(pinfo); ++ } ++ ++ // close all clocks ++ for(clockIdxtemp = 0 ; clockIdxtemp < num_parents_clocks_gop2 ; clockIdxtemp++) ++ { ++ if(clockIdxtemp!=1)//index=1 is scl_fclk, only open when load palette ++ { ++ clk_disable_unprepare(gop2_clks[clockIdxtemp]); ++ } ++ } ++ return 0; ++} ++ ++static int mdrvinfinityfb2_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ dma_addr_t fb2_pandisplay_PHY_ADD_SHOW=0; ++ int fb_size = 0; ++ int fb_index = 0; ++ FB2DBGMORE( "[FB2 Driver]%s: var->yoffset=%x! info->var.height=%x\n ",__func__,var->yoffset,info->var.height); ++ ++ fb_size = (info->var.width * info->var.height * ANDROID_BYTES_PER_PIXEL); ++ fb_index = (var->yoffset/info->var.height); ++ FB2DBGMORE( "[FB2 Driver]%s: fb_size = 0x%x, fb_index = %d\n", __func__, fb_size, fb_index); ++ ++ if(fb_index > ANDROID_NUMBER_OF_BUFFERS) { ++ FB2DBGMORE( "[FB2 Driver]%s: fb_index = %d invalid!! reset as %d\n", __func__, fb_index, ANDROID_NUMBER_OF_BUFFERS); ++ fb_index = ANDROID_NUMBER_OF_BUFFERS; ++ } ++ ++ fb2_pandisplay_PHY_ADD_SHOW = info->fix.smem_start + fb_size * fb_index; ++ FB2DBGMORE( "[FB2 Driver]%s: use buffer %d! Addr = %x\n ", __func__, fb_index, fb2_pandisplay_PHY_ADD_SHOW); ++ ++ GOP2_Pan_Display(0, fb2_pandisplay_PHY_ADD_SHOW); ++ ++ return 0; ++} ++ ++ ++//check var to see if supported by this device, defined for infinity ++static int mdrvinfinityfb2_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ int MiuBusLen=128;//miu bus length in iNfinity ++ int DisplayPerPixel=0; ++ int max_x_res=2560; ++ int max_y_res=2048; ++ ++ DisplayPerPixel=MiuBusLen/(ANDROID_BYTES_PER_PIXEL*8); ++ ++ //MstarFB_ENTER(); ++ ++ if((var->yres<1)||(var->xres<1)) ++ { ++ FB2DBGERR( "[FB2 Driver] Error: fb_check_var: buffer x or y size should be > 0 !\n "); ++ return -EINVAL; ++ } ++ if((var->yres * var->xres)>(max_x_res*max_y_res)) ++ { ++ FB2DBGERR( "[FB2 Driver] Error: fb_check_var: total buffer size should be lower than 1920*1088!\n "); ++ return -EINVAL; ++ } ++ ++ if((var->xres % DisplayPerPixel)!=0) ++ { ++ FB2DBGERR( "[FB2 Driver] Error: fb_check_var: Display Per Pixel for Buffer Width should be %d!\n ",DisplayPerPixel); ++ return -EINVAL; ++ } ++ ++ //MstarFB_LEAVE(); ++ ++ return 0; ++} ++ ++module_platform_driver(sg_mdrvinfinityfb2_driver); ++ ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/fb2/infinity3/mdrv_fb2.h b/drivers/mstar/fb2/infinity3/mdrv_fb2.h +new file mode 100644 +index 00000000..f5ab2ac0 +--- /dev/null ++++ b/drivers/mstar/fb2/infinity3/mdrv_fb2.h +@@ -0,0 +1,328 @@ ++ ++/****************************************************************************** ++ *----------------------------------------------------------------------------- ++ * ++ * Copyright (c) 2011 MStar Semiconductor, Inc. All rights reserved. ++ * ++ *----------------------------------------------------------------------------- ++ * FILE NAME mdrv_fb.h ++ * DESCRIPTION ++ * Including some MACRO needed in mdrvfb.c ++ * Defined CLRREG16(), SETREG16() ++ * (refer to include/asm-arm/arch-msb25xx/io.h) ++ * Defined used MASK and setting value ++ * Defined CHIPTOP, OP2, VOP, GOP Base Addres in Physical Address ++ * and theirs offset (drvop2.h and drvgop.h) ++ * Declared Boot_splash array. the image content shown in boot ++ * (boot_splasy.h) ++ * refering sources list ++ * drvop2.h and drvgop.h ++ * boot_splasy.h ++ * ++ * AUTHOR Chun Fan ++ * ++ * HISTORY ++ * 2008/05/06 Chun initial version ++ * 2008/10/02 Chun add MSB251x code, add CONFIG_ARCH_MSB251X ++ * add some IP base address Macro ++ * BK_LPLL_BASE, BK_DAC_BASE, ++ * and OP2_DITH_REG_BASE ++ * ++ * linux/drivers/video/mdrvfb.h -- mdrvfb frame buffer device ++ ******************************************************************************/ ++ ++//-------------------------------------------------------------------------------------------------- ++// Includes ++//-------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include //for dma_alloc_coherent ++#include ++#include //seems do not need this ++#include ++#include ++#include ++#include ++#include //access_ok(), and VERIFY_WRITE/READ ++#include //for _IO() macro ++#include ++#include ++#include ++#include //do_gettimeofday() ++#include "gop2/mdrv_gop2.h" ++#include "inv_color/mdrv_gop2_inv_color.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" //for dma_alloc_coherent ++#include ++#include ++#include ++ ++#include "mdrv_fb_io.h" ++#include "mdrv_fb_st.h" ++#include "mdrv_isp_io_st.h" ++ ++//-------------------------------------------------------------------------------------------------- ++// Defines ++//-------------------------------------------------------------------------------------------------- ++#define FB2_DEBUG 0 //0 for only error message, 1 for normal debug message, 2 for more message ++ ++#if (FB2_DEBUG==0) ++#define FB2DBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB2DBG(fmt, arg...) ++#define FB2DBGMORE(fmt, arg...) ++#elif (FB2_DEBUG==1) ++#define FB2DBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB2DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB2DBGMORE(fmt, arg...) ++#elif (FB2_DEBUG==2) ++#define FB2DBGERR(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB2DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#define FB2DBGMORE(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define FB2DBGERR(fmt, arg...) ++#define FB2DBG(fmt, arg...) ++#define FB2DBGMORE(fmt, arg...) ++#endif ++ ++#define CAST_2_USER_VOID_P (void __user *) ++#define CAST_2_USER_UINT_P (unsigned int __user *) ++#define CAST_2_IOMEM_CHAR_P (u8 __iomem *) ++ ++#define ANDROID_NUMBER_OF_BUFFERS 4 ++#define ANDROID_FB_FORMAT _8Bit_Palette ++#define defult_XRES 0 //init value for xres of fb_var_screeninfo, do not assign value while init ++#define defult_YRES 0 //init value for yres of fb_var_screeninfo, do not assign value while init ++#if (ANDROID_FB_FORMAT == RGB565) ++#define BPX 16 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 2 ++#elif ((ANDROID_FB_FORMAT == ARGB8888) || (ANDROID_FB_FORMAT == ABGR8888)) ++#define BPX 32 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 4 ++#elif (ANDROID_FB_FORMAT == _8Bit_Palette) ++#define BPX 8 //bits per pixel ++#define ANDROID_BYTES_PER_PIXEL 1 ++#else ++ #ERROR("Not Support") ++#endif ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Functions ++//-------------------------------------------------------------------------------------------------- ++static int mdrvinfinityfb2_ioctl(struct fb_info *info, u32 cmd, unsigned long arg); ++static int mdrvinfinityfb2_mmap(struct fb_info *info, struct vm_area_struct *vma); ++static int mdrvinfinityfb2_pan_display(struct fb_var_screeninfo *var, struct fb_info *info); ++static int mdrvinfinityfb2_check_var(struct fb_var_screeninfo *var, struct fb_info *info); ++static int mdrvinfinityfb2_set_par(struct fb_info *info); ++static int mdrvinfinityfb2_suspend(struct platform_device *pdev,pm_message_t state); ++static int mdrvinfinityfb2_resume(struct platform_device *pdev); ++static int mdrvinfinityfb2_probe(struct platform_device *dev); ++static int mdrvinfinityfb2_remove(struct platform_device *dev); ++ ++//-------------------------------------------------------------------------------------------------- ++// Global variable ++//-------------------------------------------------------------------------------------------------- ++struct clk **gop2_clks; /* clock define, one for palette sram clock, one for scaler fclk1 *///index=1 is scl_fclk ++int num_parents_clocks_gop2 = 0; /* number of clocks*/ ++static void *sg_pG3D_fb2_vir_addr1_gop2 = 0; /* virtual address of frame buffer */ ++static u_long sg_videomemorysize_gop2 = 0; /* frame buffer size */ ++dma_addr_t sg_G3D_fb2_bus_addr1_gop2 = 0; /* physical address of frame buffer */ ++ ++FB_GOP_GWIN_CONFIG genGWinInfo_gop2 ={0}; /* global variable to record gwin information */ ++unsigned char genGWIN_gop2 = 1; /* global variable to record gwin is open or close *///open:1; close:0 ++FB_GOP_ALPHA_CONFIG genGOPALPHA_gop2 ={0}; /* global variable to record alpha blending information */ ++FB_GOP_COLORKEY_CONFIG genGOPCOLORKEY_gop2 ={0}; /* global variable to record color key information */ ++ ++unsigned char genInv_Color_gop2 = 0; /* global variable to record inverse color is open or close *///open:1; close:0 ++FB_GOP_INVCOLOR_AE_CONFIG genAE_info_gop2 ={0}; /* global variable to record AE information */ ++unsigned long genY_Thres_gop2 = 0; /* global variable to record Y Threshold */ ++FB_GOP_INVCOLOR_SCALER_CONFIG genSC_info_gop2 ={0}; /* global variable to record Scaler information */ ++ ++static struct task_struct *pSWupdateInvThread_gop2=NULL; ++unsigned char genTreadisError_gop2 = 0; ++ ++static struct task_struct *pSWupdateInvDebugThread_gop2=NULL; ++ ++//// {B, G, R, Alpha} ++static FB_GOP_PaletteEntry DefaultPaletteEntry[GOP_PALETTE_ENTRY_NUM] = ++{ ++ {{ 0, 0, 0, 0}}, {{ 0, 0,128, 0}}, {{ 0,128, 0, 0}}, {{ 0,128,128, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0,128, 0}}, {{128,128, 0, 0}}, {{192,192,192, 0}}, ++ {{192,220,192, 0}}, {{240,202,166, 0}}, {{ 0, 32, 64, 0}}, {{ 0, 32, 96, 0}}, ++ {{ 0, 32,128, 0}}, {{ 0, 32,160, 0}}, {{ 0, 32,192, 0}}, {{ 0, 32,224, 0}}, ++ {{ 0, 64, 0, 0}}, {{ 0, 64, 32, 0}}, {{ 0, 64, 64, 0}}, {{ 0, 64, 96, 0}}, ++ {{ 0, 64,128, 0}}, {{ 0, 64,160, 0}}, {{ 0, 64,192, 0}}, {{ 0, 64,224, 0}}, ++ {{ 0, 96, 0, 0}}, {{ 0, 96, 32, 0}}, {{ 0, 96, 64, 0}}, {{ 0, 96, 96, 0}}, ++ {{ 0, 96,128, 0}}, {{ 0, 96,160, 0}}, {{ 0, 96,192, 0}}, {{ 0, 96,224, 0}}, ++ {{ 0,128, 0, 0}}, {{ 0,128, 32, 0}}, {{ 0,128, 64, 0}}, {{ 0,128, 96, 0}}, ++ {{ 0,128,128, 0}}, {{ 0,128,160, 0}}, {{ 0,128,192, 0}}, {{ 0,128,224, 0}}, ++ {{ 0,160, 0, 0}}, {{ 0,160, 32, 0}}, {{ 0,160, 64, 0}}, {{ 0,160, 96, 0}}, ++ {{ 0,160,128, 0}}, {{ 0,160,160, 0}}, {{ 0,160,192, 0}}, {{ 0,160,224, 0}}, ++ {{ 0,192, 0, 0}}, {{ 0,192, 32, 0}}, {{ 0,192, 64, 0}}, {{ 0,192, 96, 0}}, ++ {{ 0,192,128, 0}}, {{ 0,192,160, 0}}, {{ 0,192,192, 0}}, {{ 0,192,224, 0}}, ++ {{ 0,224, 0, 0}}, {{ 0,224, 32, 0}}, {{ 0,224, 64, 0}}, {{ 0,224, 96, 0}}, ++ {{ 0,224,128, 0}}, {{ 0,224,160, 0}}, {{ 0,224,192, 0}}, {{ 0,224,224, 0}}, ++ {{ 64, 0, 0, 0}}, {{ 64, 0, 32, 0}}, {{ 64, 0, 64, 0}}, {{ 64, 0, 96, 0}}, ++ {{ 64, 0,128, 0}}, {{ 64, 0,160, 0}}, {{ 64, 0,192, 0}}, {{ 64, 0,224, 0}}, ++ {{ 64, 32, 0, 0}}, {{ 64, 32, 32, 0}}, {{ 64, 32, 64, 0}}, {{ 64, 32, 96, 0}}, ++ {{ 64, 32,128, 0}}, {{ 64, 32,160, 0}}, {{ 64, 32,192, 0}}, {{ 64, 32,224, 0}}, ++ {{ 64, 64, 0, 0}}, {{ 64, 64, 32, 0}}, {{ 64, 64, 64, 0}}, {{ 64, 64, 96, 0}}, ++ {{ 64, 64,128, 0}}, {{ 64, 64,160, 0}}, {{ 64, 64,192, 0}}, {{ 64, 64,224, 0}}, ++ {{ 64, 96, 0, 0}}, {{ 64, 96, 32, 0}}, {{ 64, 96, 64, 0}}, {{ 64, 96, 96, 0}}, ++ {{ 64, 96,128, 0}}, {{ 64, 96,160, 0}}, {{ 64, 96,192, 0}}, {{ 64, 96,224, 0}}, ++ {{ 64,128, 0, 0}}, {{ 64,128, 32, 0}}, {{ 64,128, 64, 0}}, {{ 64,128, 96, 0}}, ++ {{ 64,128,128, 0}}, {{ 64,128,160, 0}}, {{ 64,128,192, 0}}, {{ 64,128,224, 0}}, ++ {{ 64,160, 0, 0}}, {{ 64,160, 32, 0}}, {{ 64,160, 64, 0}}, {{ 64,160, 96, 0}}, ++ {{ 64,160,128, 0}}, {{ 64,160,160, 0}}, {{ 64,160,192, 0}}, {{ 64,160,224, 0}}, ++ {{ 64,192, 0, 0}}, {{ 64,192, 32, 0}}, {{ 64,192, 64, 0}}, {{ 64,192, 96, 0}}, ++ {{ 64,192,128, 0}}, {{ 64,192,160, 0}}, {{ 64,192,192, 0}}, {{ 64,192,224, 0}}, ++ {{ 64,224, 0, 0}}, {{ 64,224, 32, 0}}, {{ 64,224, 64, 0}}, {{ 64,224, 96, 0}}, ++ {{ 64,224,128, 0}}, {{ 64,224,160, 0}}, {{ 64,224,192, 0}}, {{ 64,224,224, 0}}, ++ {{128, 0, 0, 0}}, {{128, 0, 32, 0}}, {{128, 0, 64, 0}}, {{128, 0, 96, 0}}, ++ {{128, 0,128, 0}}, {{128, 0,160, 0}}, {{128, 0,192, 0}}, {{128, 0,224, 0}}, ++ {{128, 32, 0, 0}}, {{128, 32, 32, 0}}, {{128, 32, 64, 0}}, {{128, 32, 96, 0}}, ++ {{128, 32,128, 0}}, {{128, 32,160, 0}}, {{128, 32,192, 0}}, {{128, 32,224, 0}}, ++ {{128, 64, 0, 0}}, {{128, 64, 32, 0}}, {{128, 64, 64, 0}}, {{128, 64, 96, 0}}, ++ {{128, 64,128, 0}}, {{128, 64,160, 0}}, {{128, 64,192, 0}}, {{128, 64,224, 0}}, ++ {{128, 96, 0, 0}}, {{128, 96, 32, 0}}, {{128, 96, 64, 0}}, {{128, 96, 96, 0}}, ++ {{128, 96,128, 0}}, {{128, 96,160, 0}}, {{128, 96,192, 0}}, {{128, 96,224, 0}}, ++ {{128,128, 0, 0}}, {{128,128, 32, 0}}, {{128,128, 64, 0}}, {{128,128, 96, 0}}, ++ {{128,128,128, 0}}, {{128,128,160, 0}}, {{128,128,192, 0}}, {{128,128,224, 0}}, ++ {{128,160, 0, 0}}, {{128,160, 32, 0}}, {{128,160, 64, 0}}, {{128,160, 96, 0}}, ++ {{128,160,128, 0}}, {{128,160,160, 0}}, {{128,160,192, 0}}, {{128,160,224, 0}}, ++ {{128,192, 0, 0}}, {{128,192, 32, 0}}, {{128,192, 64, 0}}, {{128,192, 96, 0}}, ++ {{128,192,128, 0}}, {{128,192,160, 0}}, {{128,192,192, 0}}, {{128,192,224, 0}}, ++ {{128,224, 0, 0}}, {{128,224, 32, 0}}, {{128,224, 64, 0}}, {{128,224, 96, 0}}, ++ {{128,224,128, 0}}, {{128,224,160, 0}}, {{128,224,192, 0}}, {{128,224,224, 0}}, ++ {{192, 0, 0, 0}}, {{192, 0, 32, 0}}, {{192, 0, 64, 0}}, {{192, 0, 96, 0}}, ++ {{192, 0,128, 0}}, {{192, 0,160, 0}}, {{192, 0,192, 0}}, {{192, 0,224, 0}}, ++ {{192, 32, 0, 0}}, {{192, 32, 32, 0}}, {{192, 32, 64, 0}}, {{192, 32, 96, 0}}, ++ {{192, 32,128, 0}}, {{192, 32,160, 0}}, {{192, 32,192, 0}}, {{192, 32,224, 0}}, ++ {{192, 64, 0, 0}}, {{192, 64, 32, 0}}, {{192, 64, 64, 0}}, {{192, 64, 96, 0}}, ++ {{192, 64,128, 0}}, {{192, 64,160, 0}}, {{192, 64,192, 0}}, {{192, 64,224, 0}}, ++ {{192, 96, 0, 0}}, {{192, 96, 32, 0}}, {{192, 96, 64, 0}}, {{192, 96, 96, 0}}, ++ {{192, 96,128, 0}}, {{192, 96,160, 0}}, {{192, 96,192, 0}}, {{192, 96,224, 0}}, ++ {{192,128, 0, 0}}, {{192,128, 32, 0}}, {{192,128, 64, 0}}, {{192,128, 96, 0}}, ++ {{192,128,128, 0}}, {{192,128,160, 0}}, {{192,128,192, 0}}, {{192,128,224, 0}}, ++ {{192,160, 0, 0}}, {{192,160, 32, 0}}, {{192,160, 64, 0}}, {{192,160, 96, 0}}, ++ {{192,160,128, 0}}, {{192,160,160, 0}}, {{192,160,192, 0}}, {{192,160,224, 0}}, ++ {{192,192, 0, 0}}, {{192,192, 32, 0}}, {{192,192, 64, 0}}, {{192,192, 96, 0}}, ++ {{192,192,128, 0}}, {{192,192,160, 0}}, {{240,251,255, 0}}, {{164,160,160, 0}}, ++ {{128,128,128, 0}}, {{ 0, 0,255, 0}}, {{ 0,255, 0, 0}}, {{ 0,255,255, 0}}, ++ {{255, 0, 0, 0}}, {{255, 0,255, 0}}, {{255,255, 0, 0}}, {{255,255,255, 0}} ++ }; ++ ++ ++FB_GOP_PaletteEntry stGOPCurrentPalInfo_GOP2[GOP_PALETTE_ENTRY_NUM]={}; ++ ++ ++static const char* KEY_DMEM_FB2_BUF="FB2_BUFFER"; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure ++//------------------------------------------------------------------------------------------------- ++static struct fb_var_screeninfo sg_mdrvinfinityfb2_default_var = ++{ ++ .xres = defult_XRES, /* visible resolution*/ //display x size ++ .yres = defult_YRES, //display y size ++ .xres_virtual = defult_XRES, /* virtual resolution*/ //framebuffer x size ++ .yres_virtual = defult_YRES, //framebuffer y size ++ .xoffset = 0, /* offset from virtual to visible */ ++ .yoffset = 0, ++ ++ .bits_per_pixel = BPX, ++ ++#if (ANDROID_FB_FORMAT == _8Bit_Palette) ++ .grayscale = 0, ++ .transp = {0,0,0}, ++ .red = {0,0,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {0,0,0}, ++ .blue = {0,0,0}, ++#elif (ANDROID_FB_FORMAT == RGB565) //Data: R G B, 5 6 5 ++ .red = {11,5,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {5,6,0}, ++ .blue = {0,5,0}, ++#elif (ANDROID_FB_FORMAT == ARGB8888) //Data: R G B A, 8 8 8 8 ++ .grayscale = 0, ++ .transp = {0,8,0}, ++ .red = {24,8,0}, /* {offset,length,!= 0 : MSB is right} */ ++ .green = {16,8,0}, ++ .blue = {8,8,0}, ++#endif ++ ++ .activate = FB_ACTIVATE_NOW, ++ .height = defult_XRES, /* height of picture in mm */ ++ .width = defult_YRES, /* width of picture in mm */ ++ ++ /* timing settings, useless here*/ ++ .pixclock = 100000, /* pixel clock in ps (pico seconds) */ ++ .left_margin = 24, /* time from sync to picture */ ++ .right_margin = 4, /* time from picture to sync */ ++ .upper_margin = 6, /* time from sync to picture */ ++ .lower_margin = 4, ++ .hsync_len = 64, /* length of horizontal sync */ ++ .vsync_len = 2, /* length of vertical sync */ ++ .vmode = FB_VMODE_NONINTERLACED, ++}; ++ ++/* Device independent unchangeable information */ ++static struct fb_fix_screeninfo sg_mdrvinfinityfb2_fix = ++{ ++ .id = "FB2_gop2", /* identification string eg "TT Builtin"*/ ++ .smem_start = 0, /* Start of frame buffer mem*/ ++ .smem_len = 0, /* Length of frame buffer mem*/ ++ .type = FB_TYPE_PACKED_PIXELS, /* see FB_TYPE_*/ ++ .visual = FB_VISUAL_TRUECOLOR, /* see FB_VISUAL_*/ ++ .xpanstep = 0, /* zero if no hardware panning*/ ++ .ypanstep = ANDROID_NUMBER_OF_BUFFERS, /* zero if no hardware panning*/ ++ .ywrapstep = 0, /* zero if no hardware ywrap*/ ++ .line_length = (defult_XRES * ANDROID_BYTES_PER_PIXEL), /* length of a line in bytes*/ ++ .mmio_start = 0x20000000, /* Start of Memory Mapped I/O*/ ++ /* (physical address)*/ ++ .mmio_len = 0x10000000, /* Length of Memory Mapped I/O*/ ++ .accel = FB_ACCEL_NONE, /* Type of acceleration available*/ ++}; ++ ++static struct fb_ops sg_mdrvinfinityfb2_ops = ++{ ++ .owner = THIS_MODULE, ++ ++ /* the folloing 3 function also refert to fb_sys_fops.ko */ ++ .fb_fillrect = sys_fillrect, /* Generic fillrect function, provide by Linux kernel, refer to sysfillrect.ko */ ++ .fb_copyarea = sys_copyarea, /* Generic copyarea function, provide by Linux kernel, refer to syscopyarea.ko */ ++ .fb_imageblit = sys_imageblit, /* Generic imgblt function, provide by Linux kernel, refer to sysimgblt.ko */ ++ ++ .fb_mmap = mdrvinfinityfb2_mmap, /* for non cached memory */ ++ .fb_ioctl = mdrvinfinityfb2_ioctl, ++ .fb_pan_display = mdrvinfinityfb2_pan_display, ++ .fb_check_var = mdrvinfinityfb2_check_var, ++ .fb_set_par = mdrvinfinityfb2_set_par, ++}; ++ ++ ++static const struct of_device_id infinity_infinityfb2_dt_ids[] = ++{ ++ { .compatible = "mstar,infinity-gop2" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, infinity_infinityfb2_dt_ids); ++ ++static struct platform_driver sg_mdrvinfinityfb2_driver = ++{ ++ .probe = mdrvinfinityfb2_probe, /* initiailize */ ++ .remove = mdrvinfinityfb2_remove, /* it free(mem), release framebuffer, free irq etc. */ ++ .suspend = mdrvinfinityfb2_suspend, ++ .resume = mdrvinfinityfb2_resume, ++ ++ .driver = ++ { ++ .name = "mdrvinfinityfb2", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(infinity_infinityfb2_dt_ids), ++ }, ++}; +diff --git a/drivers/mstar/flash_isp/Kconfig b/drivers/mstar/flash_isp/Kconfig +new file mode 100644 +index 00000000..3df2a682 +--- /dev/null ++++ b/drivers/mstar/flash_isp/Kconfig +@@ -0,0 +1,62 @@ ++config MS_FLASH_ISP ++ ++ select MTD ++ #select MTD_CHAR ++ #select MTD_BLKDEVS ++ #select NFTL ++ #select NFTL_RW ++ #select MTD_OOPS ++ ++ #select MTD_COMPLEX_MAPPINGS ++ #select MTD_BLOCK2MTD ++ #select MTD_CMDLINE_PARTS ++ #select SCSI_LOWLEVEL ++ #select AUTOFS_FS ++ ++ #select FAT_FS ++ #select MSDOS_FS ++ #select VFAT_FS ++ ++ #select MTD_DEBUG ++ #select MTD_DEBUG_VERBOSE ++ #select MTD_CONCAT ++ #select MTD_PARTITIONS ++ #select MTD_NAND ++ #select JFFS2_FS ++ #select JFFS2_FS_DEBUG ++ #select JFFS2_FS_WRITEBUFFER ++ ++bool "Serial Flash driver" ++default n ++---help--- ++ Enable compilation option for Serial Flash. ++ FSP support Quadread/Daulread/write with BDMA. ++ ++if MS_FLASH_ISP ++config MS_FLASH_ISP_MXP_PARTS ++ bool ++ default y ++ ++choice ++ prompt "Target select" ++ default MS_FLASH_ISP_INFINITY ++ ++config MS_FLASH_ISP_CEDRIC ++ bool "support for Cedric" ++ depends on ARCH_CEDRIC ++ ++config MS_FLASH_ISP_CHICAGO ++ bool "support for Chicago" ++ depends on ARCH_CHICAGO ++ ++config MS_FLASH_ISP_INFINITY ++ bool "support for iNfinity" ++ depends on ARCH_INFINITY ++ ++config MS_FLASH_ISP_INFINITY3 ++ bool "support for iNfinity3" ++ depends on ARCH_INFINITY3 ++endchoice ++endif ++ ++ +diff --git a/drivers/mstar/flash_isp/Makefile b/drivers/mstar/flash_isp/Makefile +new file mode 100644 +index 00000000..5bd01c96 +--- /dev/null ++++ b/drivers/mstar/flash_isp/Makefile +@@ -0,0 +1,18 @@ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/flash_isp ++EXTRA_CFLAGS += -Idrivers/mstar/flash_isp/include ++EXTRA_CFLAGS += -Idrivers/mstar/flash_isp/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_FLASH_ISP) += drvSERFLASH.o mtd_serflash.o drvDeviceInfo.o ++obj-$(CONFIG_MS_FLASH_ISP) += $(CONFIG_MSTAR_CHIP_NAME)/halSERFLASH.o ++obj-$(CONFIG_MS_FLASH_ISP_MXP_PARTS) += part_mxp.o mxp_flash.o ++ ++ ++ +diff --git a/drivers/mstar/flash_isp/drvDeviceInfo.c b/drivers/mstar/flash_isp/drvDeviceInfo.c +new file mode 100644 +index 00000000..d06c1b66 +--- /dev/null ++++ b/drivers/mstar/flash_isp/drvDeviceInfo.c +@@ -0,0 +1,1193 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "MsTypes.h" ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++ ++ ++ ++// ++// Sprcial Block Table (List) ++// ++ ++ST_SPECIAL_BLOCKS _stSpecialBlocks_EN25F10 = ++{ ++ .u16Start = 0, // Start block# of special block size ++ .u16End = 3, // End block# of special block size ++ .au32SizeList = // List of special size;Total size must be equal to block size ++ { ++ SIZE_32KB, ++ SIZE_32KB, ++ SIZE_32KB, ++ SIZE_32KB, ++ } ++}; ++ ++ST_SPECIAL_BLOCKS _stSpecialBlocks_EN25B32B = ++{ ++ .u16Start = 0, // Start block# of special block size ++ .u16End = 4, // End block# of special block size ++ .au32SizeList = // List of special size;Total size must be equal to block size ++ { ++ SIZE_4KB, ++ SIZE_4KB, ++ SIZE_8KB, ++ SIZE_16KB, ++ SIZE_32KB, ++ } ++}; ++ ++ST_SPECIAL_BLOCKS _stSpecialBlocks_EN25B64B = ++{ ++ .u16Start = 0, // Start block# of special block size ++ .u16End = 4, // End block# of special block size ++ .au32SizeList = // List of special size;Total size must be equal to block size ++ { ++ SIZE_4KB, ++ SIZE_4KB, ++ SIZE_8KB, ++ SIZE_16KB, ++ SIZE_32KB, ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++// Write Protect Table (List) ++//------------------------------------------------------------------------------------------------- ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X32[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x003F0000, 0x003FFFFF }, ++ { BITS(5:2, 2), 0x003E0000, 0x003FFFFF }, ++ { BITS(5:2, 3), 0x003C0000, 0x003FFFFF }, ++ { BITS(5:2, 4), 0x00380000, 0x003FFFFF }, ++ { BITS(5:2, 5), 0x00300000, 0x003FFFFF }, ++ { BITS(5:2, 6), 0x00200000, 0x003FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0000FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x007E0000, 0x007FFFFF }, ++ { BITS(5:2, 2), 0x007C0000, 0x007FFFFF }, ++ { BITS(5:2, 3), 0x00780000, 0x007FFFFF }, ++ { BITS(5:2, 4), 0x00700000, 0x007FFFFF }, ++ { BITS(5:2, 5), 0x00600000, 0x007FFFFF }, ++ { BITS(5:2, 6), 0x00400000, 0x007FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032K_CMP0[]= ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x003F0000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x003E0000, 0x003FFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x003C0000, 0x003FFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00380000, 0x003FFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00300000, 0x003FFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00200000, 0x003FFFFF }, // 32-63 ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // 0 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x001FFFFF }, // 00-31 ++ { BITS(6:2, 0x1F), 0x00000000, 0x003FFFFF }, // 0-63 ++ { BITS(6:2, 0x11), 0x003FF000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x003FE000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x003FC000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x003F8000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032K_CMP1[]= ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x01), 0x00000000, 0x003EFFFF }, // 00-62 ++ { BITS(6:2, 0x02), 0x00000000, 0x003DFFFF }, // 00-61 ++ { BITS(6:2, 0x03), 0x00000000, 0x003BFFFF }, // 00-59 ++ { BITS(6:2, 0x04), 0x00000000, 0x0037FFFF }, // 00-55 ++ { BITS(6:2, 0x05), 0x00000000, 0x002FFFFF }, // 00-47 ++ { BITS(6:2, 0x06), 0x00000000, 0x001FFFFF }, // 00-31 ++ { BITS(6:2, 0x09), 0x00010000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x0A), 0x00020000, 0x003FFFFF }, // 02-63 ++ { BITS(6:2, 0x0B), 0x00040000, 0x003FFFFF }, // 04-63 ++ { BITS(6:2, 0x0C), 0x00080000, 0x003FFFFF }, // 08-63 ++ { BITS(6:2, 0x0D), 0x00100000, 0x003FFFFF }, // 16-63 ++ { BITS(6:2, 0x0E), 0x00200000, 0x003FFFFF }, // 32-63 ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x11), 0x00000000, 0x003FEFFF }, // 00-63 ++ { BITS(6:2, 0x12), 0x00000000, 0x003FDFFF }, // 00-63 ++ { BITS(6:2, 0x13), 0x00000000, 0x003FBFFF }, // 00-62 ++ { BITS(6:2, 0x14), 0x00000000, 0x003F7FFF }, // 00-62 ++ { BITS(6:2, 0x19), 0x00001000, 0x003FFFFF }, // 00-63 ++ { BITS(6:2, 0x1A), 0x00002000, 0x003FFFFF }, // 00-63 ++ { BITS(6:2, 0x1B), 0x00004000, 0x00003FFF }, // 00-63 ++ { BITS(6:2, 0x1C), 0x00008000, 0x003FFFFF }, // 00-63 ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q32_CMP0[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x003F0000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x02), 0x003E0000, 0x003FFFFF }, // 62-63 ++ { BITS(6:2, 0x03), 0x003C0000, 0x003FFFFF }, // 60-63 ++ { BITS(6:2, 0x04), 0x00380000, 0x003FFFFF }, // 56-63 ++ { BITS(6:2, 0x05), 0x00300000, 0x003FFFFF }, // 48-63 ++ { BITS(6:2, 0x06), 0x00200000, 0x003FFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // 00 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // 00-01 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // 00-03 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // 00-07 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // 00-15 ++ { BITS(6:2, 0x0E), 0x00000000, 0x001FFFFF }, // 00-31 ++ ++ { BITS(6:2, 0x11), 0x003FF000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x12), 0x003EE000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x13), 0x003FC000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x14), 0x003F8000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x15), 0x003F8000, 0x003FFFFF }, // 63 ++ { BITS(6:2, 0x16), 0x003F8000, 0x003FFFFF }, // 63 ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 00 ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 00 ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 00 ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1D), 0x00000000, 0x00007FFF }, // 00 ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, // 00 ++ ++ { BITS(6:2, 0x07), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x0F), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x17), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x1F), 0x00000000, 0x003FFFFF }, // ALL ++ ++ { BITS(6:2, 0x18), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x10), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x08), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q32_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x01), 0x00000000, 0x003EFFFF }, // 00-62 ++ { BITS(6:2, 0x02), 0x00000000, 0x003DFFFF }, // 00-61 ++ { BITS(6:2, 0x03), 0x00000000, 0x003BFFFF }, // 00-59 ++ { BITS(6:2, 0x04), 0x00000000, 0x0037FFFF }, // 00-55 ++ { BITS(6:2, 0x05), 0x00000000, 0x002FFFFF }, // 00-47 ++ { BITS(6:2, 0x06), 0x00000000, 0x001FFFFF }, // 00-31 ++ ++ { BITS(6:2, 0x09), 0x00010000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x0A), 0x00020000, 0x003FFFFF }, // 02-63 ++ { BITS(6:2, 0x0B), 0x00040000, 0x003FFFFF }, // 04-63 ++ { BITS(6:2, 0x0C), 0x00080000, 0x003FFFFF }, // 08-63 ++ { BITS(6:2, 0x0D), 0x00100000, 0x003FFFFF }, // 16-63 ++ { BITS(6:2, 0x0E), 0x00200000, 0x003FFFFF }, // 32-63 ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x003FEFFF }, // 00-62 ++ { BITS(6:2, 0x12), 0x00000000, 0x003FDFFF }, // 00-62 ++ { BITS(6:2, 0x13), 0x00000000, 0x003FBFFF }, // 00-62 ++ { BITS(6:2, 0x14), 0x00000000, 0x003F7FFF }, // 00-62 ++ { BITS(6:2, 0x15), 0x00000000, 0x003F7FFF }, // 00-62 ++ { BITS(6:2, 0x16), 0x00000000, 0x003F7FFF }, // 00-62 ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1A), 0x00002000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1B), 0x00004000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1C), 0x00008000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1D), 0x00008000, 0x003FFFFF }, // 01-63 ++ { BITS(6:2, 0x1E), 0x00008000, 0x003FFFFF }, // 01-63 ++ ++ { BITS(6:2, 0x07), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x0F), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x17), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ ++ { BITS(6:2, 0x18), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x10), 0x00000000, 0x003FFFFF }, // ALL ++ { BITS(6:2, 0x08), 0x00000000, 0x003FFFFF }, // ALL ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q16_CMP0[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, // NONE ++ { BITS(6:2, 0x01), 0x001F0000, 0x001FFFFF }, // Upper 1/32 ++ { BITS(6:2, 0x02), 0x001E0000, 0x001FFFFF }, // Upper 1/16 ++ { BITS(6:2, 0x03), 0x001C0000, 0x001FFFFF }, // Upper 1/8 ++ { BITS(6:2, 0x04), 0x00180000, 0x001FFFFF }, // Upper 1/4 ++ { BITS(6:2, 0x05), 0x00100000, 0x001FFFFF }, // Upper 1/2 ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // Lower 1/32 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // Lower 1/16 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // Lower 1/8 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // Lower 1/4 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // Lower 1/2 ++ { BITS(6:2, 0x0E), 0x00000000, 0x001FFFFF }, // ALL ++ ++ { BITS(6:2, 0x11), 0x001FF000, 0x001FFFFF }, // 4KB Top Block ++ { BITS(6:2, 0x12), 0x001EE000, 0x001FFFFF }, // 8KB Top Block ++ { BITS(6:2, 0x13), 0x001FC000, 0x001FFFFF }, // 16KB Top Block ++ { BITS(6:2, 0x14), 0x001F8000, 0x001FFFFF }, // 32KB Top Block ++ ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, // 4KB Bottom Block ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, // 8KB Bottom Block ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, // 16KB Bottom Block ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, // 32KB Bottom Block ++ ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q128_CMP0[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(6:2, 0x01), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(6:2, 0x02), 0x00F80000, 0x00FFFFFF }, ++ { BITS(6:2, 0x03), 0x00F00000, 0x00FFFFFF }, ++ { BITS(6:2, 0x04), 0x00E00000, 0x00FFFFFF }, ++ { BITS(6:2, 0x05), 0x00C00000, 0x00FFFFFF }, ++ { BITS(6:2, 0x06), 0x00800000, 0x0000FFFF }, ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 0x0A), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 0x0B), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 0x0C), 0x00000000, 0x001FFFFF }, ++ { BITS(6:2, 0x0D), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0x0E), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0x0F), 0x00000000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00FFF000, 0x00FFFFFF }, ++ { BITS(6:2, 0x12), 0x00FEE000, 0x00FFFFFF }, ++ { BITS(6:2, 0x13), 0x00FFC000, 0x00FFFFFF }, ++ { BITS(6:2, 0x14), 0x00FF8000, 0x00FFFFFF }, ++ { BITS(6:2, 0x16), 0x00FF8000, 0x00FFFFFF }, ++ ++ { BITS(6:2, 0x19), 0x00000000, 0x00000FFF }, ++ { BITS(6:2, 0x1A), 0x00000000, 0x00001FFF }, ++ { BITS(6:2, 0x1B), 0x00000000, 0x00003FFF }, ++ { BITS(6:2, 0x1C), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0x1E), 0x00000000, 0x00007FFF }, ++}; ++ ++#if 0//researved for GD25Q16 flash ++ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q16_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x001FFFFF }, // 2M ALL ++ { BITS(6:2, 0x01), 0x00000000, 0x001EFFFF }, // 1984KB Lower 31/32 ++ { BITS(6:2, 0x02), 0x00000000, 0x001DFFFF }, // 1920KB Lower 15/16 ++ { BITS(6:2, 0x03), 0x00000000, 0x001BFFFF }, // 1792KB Lower 7/8 ++ { BITS(6:2, 0x04), 0x00000000, 0x0017FFFF }, // 1536KB Lower 3/4 ++ { BITS(6:2, 0x05), 0x00000000, 0x001FFFFF }, // 1M Lower 1/2 ++ ++ ++ { BITS(6:2, 0x09), 0x00000000, 0x0000FFFF }, // 1984KB Upper 31/32 ++ { BITS(6:2, 0x0A), 0x00000000, 0x0001FFFF }, // 1920KB Upper 15/16 ++ { BITS(6:2, 0x0B), 0x00000000, 0x0003FFFF }, // 1792KB Upper 7/8 ++ { BITS(6:2, 0x0C), 0x00000000, 0x0007FFFF }, // 1536KB Upper 3/4 ++ { BITS(6:2, 0x0D), 0x00000000, 0x000FFFFF }, // 1M Upper 1/2 ++ ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x001FEFFF }, // 2044KB L - 511/512 ++ { BITS(6:2, 0x12), 0x00000000, 0x001FDFFF }, // 2040KB L - 255/256 ++ { BITS(6:2, 0x13), 0x00000000, 0x001FBFFF }, // 2032KB L - 127/128 ++ { BITS(6:2, 0x14), 0x00000000, 0x001F7FFF }, // 2016KB L - 63/64 ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x001FFFFF }, // 2044KB U - 511/512 ++ { BITS(6:2, 0x1A), 0x00002000, 0x001FFFFF }, // 2040KB U - 255/256 ++ { BITS(6:2, 0x1B), 0x00004000, 0x001FFFFF }, // 2032KB U - 127/128 ++ { BITS(6:2, 0x1C), 0x00008000, 0x001FFFFF }, // 2016KB U - 63/64 ++ ++ ++}; ++#endif ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q64CV_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x007FFFFF }, ++ { BITS(6:2, 0x01), 0x00000000, 0x007DFFFF }, ++ { BITS(6:2, 0x02), 0x00000000, 0x007BFFFF }, ++ { BITS(6:2, 0x03), 0x00000000, 0x0077FFFF }, ++ { BITS(6:2, 0x04), 0x00000000, 0x006FFFFF }, ++ { BITS(6:2, 0x05), 0x00000000, 0x005FFFFF }, ++ { BITS(6:2, 0x06), 0x00000000, 0x003FFFFF }, ++ ++ { BITS(6:2, 0x09), 0x00020000, 0x007FFFFF }, ++ { BITS(6:2, 0x0A), 0x00040000, 0x007FFFFF }, ++ { BITS(6:2, 0x0B), 0x00080000, 0x007FFFFF }, ++ { BITS(6:2, 0x0C), 0x00100000, 0x007FFFFF }, ++ { BITS(6:2, 0x0D), 0x00200000, 0x007FFFFF }, ++ { BITS(6:2, 0x0E), 0x00400000, 0x007FFFFF }, ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x007FEFFF }, ++ { BITS(6:2, 0x12), 0x00000000, 0x007FDFFF }, ++ { BITS(6:2, 0x13), 0x00000000, 0x007FBFFF }, ++ { BITS(6:2, 0x14), 0x00000000, 0x007F7FFF }, ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x007FFFFF }, ++ { BITS(6:2, 0x1A), 0x00002000, 0x007FFFFF }, ++ { BITS(6:2, 0x1B), 0x00004000, 0x007FFFFF }, ++ { BITS(6:2, 0x1C), 0x00008000, 0x007FFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q32BV_CMP1[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 0x00), 0x00000000, 0x003FFFFF }, ++ { BITS(6:2, 0x01), 0x00000000, 0x003EFFFF }, ++ { BITS(6:2, 0x02), 0x00000000, 0x003DFFFF }, ++ { BITS(6:2, 0x03), 0x00000000, 0x003BFFFF }, ++ { BITS(6:2, 0x04), 0x00000000, 0x0037FFFF }, ++ { BITS(6:2, 0x05), 0x00000000, 0x002FFFFF }, ++ { BITS(6:2, 0x06), 0x00000000, 0x001FFFFF }, ++ ++ { BITS(6:2, 0x09), 0x00010000, 0x003FFFFF }, ++ { BITS(6:2, 0x0A), 0x00020000, 0x003FFFFF }, ++ { BITS(6:2, 0x0B), 0x00040000, 0x003FFFFF }, ++ { BITS(6:2, 0x0C), 0x00080000, 0x003FFFFF }, ++ { BITS(6:2, 0x0D), 0x00100000, 0x003FFFFF }, ++ { BITS(6:2, 0x0E), 0x00200000, 0x003FFFFF }, ++ { BITS(6:2, 0x1F), 0xFFFFFFFF, 0xFFFFFFFF }, ++ ++ { BITS(6:2, 0x11), 0x00000000, 0x003FEFFF }, ++ { BITS(6:2, 0x12), 0x00000000, 0x003FDFFF }, ++ { BITS(6:2, 0x13), 0x00000000, 0x003FBFFF }, ++ { BITS(6:2, 0x14), 0x00000000, 0x003F7FFF }, ++ ++ { BITS(6:2, 0x19), 0x00001000, 0x003FFFFF }, ++ { BITS(6:2, 0x1A), 0x00002000, 0x003FFFFF }, ++ { BITS(6:2, 0x1B), 0x00004000, 0x003FFFFF }, ++ { BITS(6:2, 0x1C), 0x00008000, 0x003FFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x007E0000, 0x007FFFFF }, ++ { BITS(5:2, 2), 0x007C0000, 0x007FFFFF }, ++ { BITS(5:2, 3), 0x00780000, 0x007FFFFF }, ++ { BITS(5:2, 4), 0x00700000, 0x007FFFFF }, ++ { BITS(5:2, 5), 0x00600000, 0x007FFFFF }, ++ { BITS(5:2, 6), 0x00400000, 0x007FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00000000, 0x001EFFFF },//1, 31 ++ { BITS(5:2, 2), 0x00000000, 0x001DFFFF },//2, 30~31 ++ { BITS(5:2, 3), 0x00000000, 0x001BFFFF },//3, 28~31 ++ { BITS(5:2, 4), 0x00000000, 0x0017FFFF },//4, 24~31 ++ { BITS(5:2, 5), 0x00000000, 0x000FFFFF },//5, 16~31 ++ { BITS(5:2, 6), 0x00000000, 0x001FFFFF },//6, all ++ { BITS(5:2, 7), 0x00000000, 0x001FFFFF },//7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF },//8, 31 ++ { BITS(5:2, 9), 0x001FFFFF, 0x00010000 },//9, 30~31 ++ { BITS(5:2, 10), 0x001FFFFF, 0x00020000 },//10, 28~31 ++ { BITS(5:2, 11), 0x001FFFFF, 0x00040000 },//11, 24~31 ++ { BITS(5:2, 12), 0x001FFFFF, 0x00080000 },//12, 16~31 ++ { BITS(5:2, 13), 0x001FFFFF, 0x00100000 },//13, all ++ { BITS(5:2, 14), 0x001FFFFF, 0x00000000 },//14, all ++ { BITS(5:2, 15), 0x001FFFFF, 0x00000000 },//15, all ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, none ++}; ++ ++#define FROM_BLK(x, blk_size) ((x) * (blk_size)) ++#define TO_BLK(x, blk_size) (((x) + 1) * (blk_size) - 1) ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X40[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 1), FROM_BLK(7, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 2), FROM_BLK(6, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 3), FROM_BLK(4, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, ++ { BITS(5:2,10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, ++ { BITS(5:2,11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, ++ { BITS(5:2,15), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L8005[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 7), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 7, 00~15 ++ { BITS(4:2, 6), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 6, 00~15 ++ { BITS(4:2, 5), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 5, 00~15 ++ { BITS(4:2, 4), FROM_BLK( 8, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 4, 08~15 ++ { BITS(4:2, 3), FROM_BLK( 12, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 3, 12~15 ++ { BITS(4:2, 2), FROM_BLK( 14, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 2, 14~15 ++ { BITS(4:2, 1), FROM_BLK( 15, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 1, 15~15 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L3205D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 0~62 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 0~61 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 0~59 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 0~55 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 0~47 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L3206E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 0~62 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 0~61 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 0~59 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 0~55 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 0~47 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_SST25VF032B[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(2:0, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(2:0, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(2:0, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(2:0, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(2:0, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(2:0, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(2:0, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 00~63 ++ { BITS(2:0, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6405D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(125, SIZE_64KB) }, // 0~125 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(123, SIZE_64KB) }, // 0~123 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(119, SIZE_64KB) }, // 0~119 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(111, SIZE_64KB) }, // 0~111 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(95, SIZE_64KB) }, // 0~95 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 64~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 96~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 126~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 0~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L1606E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(31, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 31~31 ++ { BITS(5:2, 2), FROM_BLK(30, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 30~31 ++ { BITS(5:2, 3), FROM_BLK(28, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 28~31 ++ { BITS(5:2, 4), FROM_BLK(24, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 24~31 ++ { BITS(5:2, 5), FROM_BLK(16, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 16~31 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 0~15 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(23, SIZE_64KB) }, // 0~23 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(27, SIZE_64KB) }, // 0~27 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(29, SIZE_64KB) }, // 0~29 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(30, SIZE_64KB) }, // 0~30 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6406E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(125, SIZE_64KB) }, // 0~125 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(123, SIZE_64KB) }, // 0~123 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(119, SIZE_64KB) }, // 0~119 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(111, SIZE_64KB) }, // 0~111 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(95, SIZE_64KB) }, // 0~95 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 64~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 96~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 126~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 0~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++// New MXIC Flash with the same RDID as MX25L6405D ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 064~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 096~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 126~127 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 000~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6455E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 14, 0~127 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 13, 0~127 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 12, 0~127 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 11, 0~127 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 10, 0~127 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 9, 0~127 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 8, 0~127 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, 0~127 ++ { BITS(5:2, 6), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 6, 64~127 ++ { BITS(5:2, 5), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 5, 96~127 ++ { BITS(5:2, 4), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 4, 112~127 ++ { BITS(5:2, 3), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 3, 120~127 ++ { BITS(5:2, 2), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 2, 124~127 ++ { BITS(5:2, 1), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 1, 126~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 15, 0~127 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L4006E[] = ++{ ++ //BPX, Lower Bound Upper Bound ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(4:2, 1), FROM_BLK(7, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 1, 7 ++ { BITS(4:2, 2), FROM_BLK(6, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 2, 6-7 ++ { BITS(4:2, 3), FROM_BLK(4, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 3, 4-7 ++ { BITS(4:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(4:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q32A[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 00~62 ++ { BITS(5:2, 2), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 00~61 ++ { BITS(5:2, 3), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 00~59 ++ { BITS(5:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 00~55 ++ { BITS(5:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 00~47 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 00~31 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 00~63 ++ { BITS(5:2, 9), FROM_BLK(1, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 01~63 ++ { BITS(5:2, 10), FROM_BLK(2, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 02~63 ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 04~63 ++ { BITS(5:2, 12), FROM_BLK(8, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 08~63 ++ { BITS(5:2, 13), FROM_BLK(16, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 16~63 ++ { BITS(5:2, 14), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 00~63 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(0, SIZE_64KB), TO_BLK(126, SIZE_64KB) }, // 00~126 ++ { BITS(5:2, 2), FROM_BLK(0, SIZE_64KB), TO_BLK(125, SIZE_64KB) }, // 00~125 ++ { BITS(5:2, 3), FROM_BLK(0, SIZE_64KB), TO_BLK(123, SIZE_64KB) }, // 00~123 ++ { BITS(5:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(119, SIZE_64KB) }, // 00~119 ++ { BITS(5:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(111, SIZE_64KB) }, // 00~111 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(95, SIZE_64KB) }, // 00~95 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 9), FROM_BLK(1, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 10), FROM_BLK(2, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 12), FROM_BLK(8, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 13), FROM_BLK(16, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 14), FROM_BLK(32, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 00~127 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_M25PX16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(31, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 2), FROM_BLK(30, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 3), FROM_BLK(28, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 4), FROM_BLK(24, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 5), FROM_BLK(16, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), FROM_BLK(0, SIZE_64KB), TO_BLK(254, SIZE_64KB) }, // 00~254 ++ { BITS(5:2, 2), FROM_BLK(0, SIZE_64KB), TO_BLK(253, SIZE_64KB) }, // 00~253 ++ { BITS(5:2, 3), FROM_BLK(0, SIZE_64KB), TO_BLK(251, SIZE_64KB) }, // 00~251 ++ { BITS(5:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(247, SIZE_64KB) }, // 00~247 ++ { BITS(5:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(239, SIZE_64KB) }, // 00~239 ++ { BITS(5:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(223, SIZE_64KB) }, // 00~223 ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 00~255 ++ { BITS(5:2, 9), FROM_BLK(1, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 01~255 ++ { BITS(5:2, 10), FROM_BLK(2, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 02~255 ++ { BITS(5:2, 11), FROM_BLK(4, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 04~255 ++ { BITS(5:2, 12), FROM_BLK(8, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 08~255 ++ { BITS(5:2, 13), FROM_BLK(16, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 16~255 ++ { BITS(5:2, 14), FROM_BLK(32, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 32~255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 00~255 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++/* ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F32[] = ++{ ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++*/ ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12805D[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 8), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 128~255 ++ { BITS(5:2, 7), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 192~255 ++ { BITS(5:2, 6), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 224~255 ++ { BITS(5:2, 5), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 240~255 ++ { BITS(5:2, 4), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 248~255 ++ { BITS(5:2, 3), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 252~255 ++ { BITS(5:2, 2), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 254~255 ++ { BITS(5:2, 1), FROM_BLK(255, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 0~255 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F40[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(4:2, 1), FROM_BLK(7, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 1, 7 ++ { BITS(4:2, 2), FROM_BLK(6, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 2, 6-7 ++ { BITS(4:2, 3), FROM_BLK(4, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 3, 4-7 ++ { BITS(4:2, 4), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(4:2, 5), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 7, all ++}; ++ ++// New MXIC Flash with the same RDID as MX25L12805D ++ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 14, 0~255 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 13, 0~255 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 12, 0~255 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 11, 0~255 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 10, 0~255 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 9, 0~255 ++ { BITS(5:2, 8), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 8, 0~255 ++ { BITS(5:2, 7), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 7, 128~255 ++ { BITS(5:2, 6), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 6, 192~255 ++ { BITS(5:2, 5), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 5, 224~255 ++ { BITS(5:2, 4), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 4, 240~255 ++ { BITS(5:2, 3), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 3, 248~255 ++ { BITS(5:2, 2), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 2, 252~255 ++ { BITS(5:2, 1), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 1, 254~255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 15, 0~255 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++// NOTE: AT26DF321 could protect each sector independently and BITS(5:2, 1)~BITS(5:2, 14) is no change for protection. ++// This table is just used to figure out the lower bound and upper bound (no such param in function argument). ++ST_WRITE_PROTECT _pstWriteProtectTable_AT26DF321[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(62, SIZE_64KB) }, // 0~62 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(61, SIZE_64KB) }, // 0~61 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(59, SIZE_64KB) }, // 0~59 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(55, SIZE_64KB) }, // 0~55 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(47, SIZE_64KB) }, // 0~47 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_AT25DF321[] = ++{ ++ { BITS(5:2, 0), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL128P[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 7), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 7, 128~255 ++ { BITS(5:2, 6), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 6, 192~255 ++ { BITS(5:2, 5), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 5, 224~255 ++ { BITS(5:2, 4), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 4, 240~255 ++ { BITS(5:2, 3), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 3, 248~255 ++ { BITS(5:2, 2), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 2, 252~255 ++ { BITS(5:2, 1), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 1, 254~255 ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, // 15, 0~255 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL008A[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 7), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 7, 00~15 ++ { BITS(5:2, 6), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 6, 00~15 ++ { BITS(5:2, 5), FROM_BLK( 0, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 5, 00~15 ++ { BITS(5:2, 4), FROM_BLK( 8, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 4, 08~15 ++ { BITS(5:2, 3), FROM_BLK( 12, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 3, 12~15 ++ { BITS(5:2, 2), FROM_BLK( 14, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 2, 14~15 ++ { BITS(5:2, 1), FROM_BLK( 15, SIZE_64KB), TO_BLK( 15, SIZE_64KB) }, // 1, 15~15 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25P16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 1), 0x001F0000, 0x001FFFFF },//1, 31 ++ { BITS(4:2, 2), 0x001E0000, 0x001FFFFF },//2, 30~31 ++ { BITS(4:2, 3), 0x001C0000, 0x001FFFFF },//3, 28~31 ++ { BITS(4:2, 4), 0x00180000, 0x001FFFFF },//4, 24~31 ++ { BITS(4:2, 5), 0x00100000, 0x001FFFFF },//5, 16~31 ++ { BITS(4:2, 6), 0x00000000, 0x001FFFFF },//6, all ++ { BITS(4:2, 7), 0x00000000, 0x001FFFFF },//7, all ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, none ++}; ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 1), 0x001F0000, 0x001FFFFF },//1, 31 ++ { BITS(4:2, 2), 0x001E0000, 0x001FFFFF },//2, 30~31 ++ { BITS(4:2, 3), 0x001C0000, 0x001FFFFF },//3, 28~31 ++ { BITS(4:2, 4), 0x00180000, 0x001FFFFF },//4, 24~31 ++ { BITS(4:2, 5), 0x00100000, 0x001FFFFF },//5, 16~31 ++ { BITS(4:2, 6), 0x00000000, 0x001FFFFF },//6, all ++ { BITS(4:2, 7), 0x00000000, 0x001FFFFF },//7, all ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F32[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00000000, 0x003EFFFF },//0~62 ++ { BITS(5:2, 2), 0x00000000, 0x003DFFFF },//0~61 ++ { BITS(5:2, 3), 0x00000000, 0x003BFFFF },//0~59 ++ { BITS(5:2, 4), 0x00000000, 0x0037FFFF },//0~55 ++ { BITS(5:2, 5), 0x00000000, 0x002FFFFF },//0~47 ++ { BITS(5:2, 6), 0x00000000, 0x001FFFFF },//0~31 ++ { BITS(5:2, 7), 0x00000000, 0x003FFFFF },//all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF },//none ++ { BITS(5:2, 9), 0x003FFFFF, 0x00010000 },//63~1 ++ { BITS(5:2, 10), 0x003FFFFF, 0x00020000 },//63~2 ++ { BITS(5:2, 11), 0x003FFFFF, 0x00040000 },//63~4 ++ { BITS(5:2, 12), 0x003FFFFF, 0x00080000 },//63~8 ++ { BITS(5:2, 13), 0x003FFFFF, 0x00100000 },//63~16 ++ { BITS(5:2, 14), 0x003FFFFF, 0x00200000 },//63~32 ++ { BITS(5:2, 15), 0x00000000, 0x003FFFFF },//all ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//none ++ ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25Q80[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(6:2, 1), 0x000F0000, 0x000FFFFF }, ++ { BITS(6:2, 2), 0x000E0000, 0x000FFFFF }, ++ { BITS(6:2, 3), 0x000C0000, 0x000FFFFF }, ++ { BITS(6:2, 4), 0x00080000, 0x000FFFFF }, ++ { BITS(6:2, 9), 0x00000000, 0x0000FFFF }, ++ { BITS(6:2, 10), 0x00000000, 0x0001FFFF }, ++ { BITS(6:2, 11), 0x00000000, 0x0003FFFF }, ++ { BITS(6:2, 12), 0x00000000, 0x0007FFFF }, ++ { BITS(6:2, 15), 0x00000000, 0x000FFFFF }, ++ { BITS(6:2, 17), 0x000FF000, 0x000FFFFF }, ++ { BITS(6:2, 18), 0x000FE000, 0x000FFFFF }, ++ { BITS(6:2, 19), 0x000FC000, 0x000FFFFF }, ++ { BITS(6:2, 20), 0x000F8000, 0x000FFFFF }, ++ { BITS(6:2, 25), 0x00000000, 0x00000FFF }, ++ { BITS(6:2, 26), 0x00000000, 0x00001FFF }, ++ { BITS(6:2, 27), 0x00000000, 0x00003FFF }, ++ { BITS(6:2, 28), 0x00000000, 0x00007FFF }, ++ { BITS(6:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_W25X80[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x000F0000, 0x000FFFFF }, ++ { BITS(5:2, 2), 0x000E0000, 0x000FFFFF }, ++ { BITS(5:2, 3), 0x000C0000, 0x000FFFFF }, ++ { BITS(5:2, 4), 0x00080000, 0x000FFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0000FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0001FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_EN25F80[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 1), 0x000F0000, 0x000FFFFF },//1, 15 ++ { BITS(4:2, 2), 0x000E0000, 0x000FFFFF },//2, 14~15 ++ { BITS(4:2, 3), 0x000C0000, 0x000FFFFF },//3, 12~15 ++ { BITS(4:2, 4), 0x00080000, 0x000FFFFF },//4, 8~15 ++ { BITS(4:2, 5), 0x00000000, 0x000FFFFF },//5, all ++ { BITS(4:2, 6), 0x00000000, 0x000FFFFF },//6, all ++ { BITS(4:2, 7), 0x00000000, 0x000FFFFF },//7, all ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF },//0, NONE ++ ++}; ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_ZB25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x007F0000, 0x007FFFFF }, ++ { BITS(5:2, 2), 0x007E0000, 0x007FFFFF }, ++ { BITS(5:2, 3), 0x007C0000, 0x007FFFFF }, ++ { BITS(5:2, 4), 0x00780000, 0x007FFFFF }, ++ { BITS(5:2, 5), 0x00700000, 0x007FFFFF }, ++ { BITS(5:2, 6), 0x00600000, 0x007FFFFF }, ++ { BITS(5:2, 7), 0x00400000, 0x007FFFFF }, ++ { BITS(5:2, 8), 0x00200000, 0x007FFFFF }, ++ { BITS(5:2, 9), 0x00100000, 0x007FFFFF }, ++ { BITS(5:2, 10), 0x00080000, 0x007FFFFF }, ++ { BITS(5:2, 11), 0x00040000, 0x007FFFFF }, ++ { BITS(5:2, 12), 0x00020000, 0x007FFFFF }, ++ { BITS(5:2, 13), 0x00010000, 0x007FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++static ST_WRITE_PROTECT _pstWriteProtectTable_ZB25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 1), 0x00FC0000, 0x00FFFFFF }, ++ { BITS(5:2, 2), 0x00F80000, 0x00FFFFFF }, ++ { BITS(5:2, 3), 0x00F00000, 0x00FFFFFF }, ++ { BITS(5:2, 4), 0x00E00000, 0x00FFFFFF }, ++ { BITS(5:2, 5), 0x00C00000, 0x00FFFFFF }, ++ { BITS(5:2, 6), 0x00800000, 0x00FFFFFF }, ++ { BITS(5:2, 7), 0x00000000, 0x00FFFFFF }, ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 9), 0x00000000, 0x0003FFFF }, ++ { BITS(5:2, 10), 0x00000000, 0x0007FFFF }, ++ { BITS(5:2, 11), 0x00000000, 0x000FFFFF }, ++ { BITS(5:2, 12), 0x00000000, 0x001FFFFF }, ++ { BITS(5:2, 13), 0x00000000, 0x003FFFFF }, ++ { BITS(5:2, 14), 0x00000000, 0x007FFFFF }, ++ { BITS(5:2, 15), 0x00000000, 0x00FFFFFF }, ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_PM25LQ032C[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 0~63 ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 0~31 ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 0~15 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 0~7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 0~3 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 0~1 ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 0~0 ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 32~63 ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 48~63 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 56~63 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 60~63 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 62~63 ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 63 ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // none ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_M25P16[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(4:2, 1), FROM_BLK(31, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 1, 7 ++ { BITS(4:2, 2), FROM_BLK(30, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 2, 6-7 ++ { BITS(4:2, 3), FROM_BLK(28, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 3, 4-7 ++ { BITS(4:2, 4), FROM_BLK(24, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 4, all ++ { BITS(4:2, 5), FROM_BLK(16, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 6), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_N25Q32[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_N25Q64[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 1), FROM_BLK(127, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 2), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 3), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 4), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 5), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 6), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 7), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 8), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++ { BITS(5:2, 9), FROM_BLK(0, SIZE_64KB), TO_BLK(0, SIZE_64KB) }, // 1, 7 ++ { BITS(5:2, 10), FROM_BLK(0, SIZE_64KB), TO_BLK(1, SIZE_64KB) }, // 2, 6-7 ++ { BITS(5:2, 11), FROM_BLK(0, SIZE_64KB), TO_BLK(3, SIZE_64KB) }, // 3, 4-7 ++ { BITS(5:2, 12), FROM_BLK(0, SIZE_64KB), TO_BLK(7, SIZE_64KB) }, // 4, all ++ { BITS(5:2, 13), FROM_BLK(0, SIZE_64KB), TO_BLK(15, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 14), FROM_BLK(0, SIZE_64KB), TO_BLK(31, SIZE_64KB) }, // 7, all ++ { BITS(5:2, 15), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, all ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_N25Q128[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(5:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, ++ { BITS(5:2, 1), FROM_BLK(255, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 2), FROM_BLK(254, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 3), FROM_BLK(252, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 4), FROM_BLK(248, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 5), FROM_BLK(240, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 6), FROM_BLK(224, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 7), FROM_BLK(192, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 8), FROM_BLK(128, SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 9), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 10), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 11), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 12), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 13), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 14), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++ { BITS(5:2, 15), FROM_BLK(0 , SIZE_64KB), TO_BLK(255, SIZE_64KB) }, ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 6), FROM_BLK(32, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 1, 126~127 ++ { BITS(4:2, 5), FROM_BLK(48, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 2, 124~127 ++ { BITS(4:2, 4), FROM_BLK(56, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 3, 120~127 ++ { BITS(4:2, 3), FROM_BLK(60, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 4, 112~127 ++ { BITS(4:2, 2), FROM_BLK(62, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 5, 096~127 ++ { BITS(4:2, 1), FROM_BLK(63, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 6, 064~127 ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(63, SIZE_64KB) }, // 7, 000~127 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++ST_WRITE_PROTECT _pstWriteProtectTable_S25FL064[] = ++{ ++ // BPX, Lower Bound Upper Bound ++ { BITS(4:2, 6), FROM_BLK(126, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 1, 126~127 ++ { BITS(4:2, 5), FROM_BLK(124, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 2, 124~127 ++ { BITS(4:2, 4), FROM_BLK(120, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 3, 120~127 ++ { BITS(4:2, 3), FROM_BLK(112, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 4, 112~127 ++ { BITS(4:2, 2), FROM_BLK(96, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 5, 096~127 ++ { BITS(4:2, 1), FROM_BLK(64, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 6, 064~127 ++ { BITS(4:2, 7), FROM_BLK(0, SIZE_64KB), TO_BLK(127, SIZE_64KB) }, // 7, 000~127 ++ { BITS(4:2, 0), 0xFFFFFFFF, 0xFFFFFFFF }, // 0, none ++}; ++ ++// ++// Flash Info Table (List) ++// ++hal_SERFLASH_t _hal_SERFLASH_table[] = // Need to Add more sample for robust ++{ ++ /**********************************************************************/ ++ /* 01. u16FlashType */ ++ /* 02. u8MID */ ++ /* 03. u8DID0 */ ++ /* 04. u8DID1 */ ++ /* 05. pWriteProtectTable */ ++ /* 06. pSpecialBlocks */ ++ /* 07. u32FlashSize */ ++ /* 08. u32NumBLK */ ++ /* 09. u32BlockSize */ ++ /* 10. u16PageSize */ ++ /* 11. u16MaxChipWrDoneTimeout */ ++ /* 12. u8WrsrBlkProtect */ ++ /* 13. u16DevSel */ ++ /* 14. u16SpiEndianSel */ ++ /* 15. Support 2XREAD(SPI CMD is 0xBB) */ ++ /**********************************************************************/ ++ { FLASH_IC_UNKNOWN, 0xFF, 0xFF, 0xFF, NULL, NULL, 0x1000000, 64, SIZE_64KB, 256, 50, BITS(2:0, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, FALSE}, ++ { FLASH_IC_SST25VF032B, MID_SST, 0x25, 0x4A, _pstWriteProtectTable_SST25VF032B, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(2:0, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L1655D, MID_MXIC, 0x26, 0x15, NULL, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_MX25L3255D, MID_MXIC, 0x9E, 0x16, NULL, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_MX25L6455E, MID_MXIC, 0x26, 0x17, _pstWriteProtectTable_MX25L6455E, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MX25L12855E, MID_MXIC, 0x26, 0x18, _pstWriteProtectTable_MX25L12845E, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MX25L3205D, MID_MXIC, 0x20, 0x16, _pstWriteProtectTable_MX25L3205D, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L4006E, MID_MXIC, 0x20, 0x13, _pstWriteProtectTable_MX25L4006E, NULL, 0x80000, 8, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L6405D, MID_MXIC, 0x20, 0x17, _pstWriteProtectTable_MX25L6405D, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L1606E, MID_MXIC, 0x20, 0x15, _pstWriteProtectTable_MX25L1606E, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_MX25L12805D, MID_MXIC, 0x20, 0x18, _pstWriteProtectTable_MX25L12805D, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, TRUE, TRUE}, ++ { FLASH_IC_MX25L3206E, MID_MXIC, 0x20, 0x15, _pstWriteProtectTable_MX25L3206E, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE }, ++ { FLASH_IC_MX25L8005, MID_MXIC, 0x20, 0x14, _pstWriteProtectTable_MX25L8005, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MX25L8006E, MID_MXIC, 0x20, 0x14, NULL, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE,TRUE }, ++ { FLASH_IC_MX25L6406E, MID_MXIC, 0x20, 0x17, _pstWriteProtectTable_MX25L6406E, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, TRUE , TRUE}, ++ { FLASH_IC_MX25L25645G, MID_MXIC, 0x20, 0x19, NULL, NULL, 0x2000000, 512, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_W25Q16, MID_WB, 0x40, 0x15, NULL, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_W25Q80, MID_WB, 0x40, 0x14, _pstWriteProtectTable_W25Q80, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25X32, MID_WB, 0x30, 0x16, _pstWriteProtectTable_W25X32, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_W25X40, MID_WB, 0x30, 0x13, _pstWriteProtectTable_W25X40, NULL, 0x80000, 8, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, FALSE, TRUE}, ++ { FLASH_IC_W25Q32, MID_WB, 0x40, 0x16, _pstWriteProtectTable_W25X32, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25X64, MID_WB, 0x30, 0x17, _pstWriteProtectTable_W25X64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE , TRUE}, ++ { FLASH_IC_W25X80, MID_WB, 0x30, 0x14, _pstWriteProtectTable_W25X80, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE }, ++ { FLASH_IC_W25Q64, MID_WB, 0x40, 0x17, _pstWriteProtectTable_W25X64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_W25Q128, MID_WB, 0x40, 0x18, _pstWriteProtectTable_W25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_AT25DF321A, MID_ATMEL, 0x47, 0x01, _pstWriteProtectTable_AT25DF321, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE }, ++ { FLASH_IC_AT26DF321, MID_ATMEL, 0x47, 0x00, _pstWriteProtectTable_AT26DF321, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_STM25P32, MID_ST, 0x20, 0x16, NULL, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25B32B, MID_EON, 0x20, 0x16, NULL, &_stSpecialBlocks_EN25B32B, 0x400000, 68, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25B64B, MID_EON, 0x20, 0x17, NULL, &_stSpecialBlocks_EN25B64B, 0x800000, 132, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25Q32A, MID_EON, 0x30, 0x16, _pstWriteProtectTable_EN25Q32A, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_EN25Q64, MID_EON, 0x30, 0x17, _pstWriteProtectTable_EN25Q64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25Q128, MID_EON, 0x30, 0x18, _pstWriteProtectTable_EN25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_S25FL128P, MID_SPAN, 0x20, 0x18, _pstWriteProtectTable_S25FL128P, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_S25FL008A, MID_SPAN, 0x20, 0x13, _pstWriteProtectTable_S25FL008A, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_XTALI, E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F10, MID_EON, 0x31, 0x11, NULL, &_stSpecialBlocks_EN25F10, 0x20000, 4, SIZE_32KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F16, MID_EON, 0x31, 0x15, _pstWriteProtectTable_EN25F16, NULL, 0x200000, 32, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F32, MID_EON, 0x31, 0x16, _pstWriteProtectTable_EN25F32, NULL, 0x400000, 64, SIZE_64KB, 256, 384, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F40, MID_EON, 0x31, 0x13, _pstWriteProtectTable_EN25F40, NULL, 0x80000, 8, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25F80, MID_EON, 0x31, 0x14, _pstWriteProtectTable_EN25F80, NULL, 0x100000, 16, SIZE_64KB, 256, 384, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25P16, MID_EON, 0x20, 0x15, _pstWriteProtectTable_EN25P16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_EN25QH16, MID_EON, 0x70, 0x15, _pstWriteProtectTable_EN25Q16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_S25FL032P, MID_SPAN, 0x02, 0x15, _pstWriteProtectTable_S25FL032, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(4:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_S25FL064P, MID_SPAN, 0x02, 0x16, _pstWriteProtectTable_S25FL064, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(4:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_S25FL032K, MID_SPAN, 0x40, 0x16, _pstWriteProtectTable_S25FL032K_CMP0, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_PM25LQ032C, MID_PMC, 0x46, 0x15, _pstWriteProtectTable_PM25LQ032C, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE , TRUE}, ++ { FLASH_IC_GD25Q32, MID_GD, 0x40, 0x16, _pstWriteProtectTable_GD25Q32_CMP0, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25Q16, MID_GD, 0x40, 0x15, _pstWriteProtectTable_GD25Q16_CMP0, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25S80, MID_GD, 0x40, 0x14, NULL, NULL, 0x100000, 16, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_GD25Q64, MID_GD, 0x40, 0x17, NULL, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25Q128, MID_GD, 0x40, 0x18, _pstWriteProtectTable_GD25Q128_CMP0, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(6:2, 0x1F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_GD25Q256C, MID_GD, 0x40, 0x19, NULL, NULL, 0x2000000, 512, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MICRON_M25P16, MID_MICRON, 0x20, 0x15, _pstWriteProtectTable_M25P16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(4:2, 0x07), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_MICRON_N25Q32, MID_MICRON, 0xBA, 0x16, _pstWriteProtectTable_N25Q32, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_D_MODE}, TRUE , TRUE}, ++ { FLASH_IC_MICRON_N25Q64, MID_MICRON, 0xBA, 0x17, _pstWriteProtectTable_N25Q64, NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_D_MODE}, TRUE, TRUE }, ++ { FLASH_IC_MICRON_N25Q128, MID_MICRON, 0xBA, 0x18, _pstWriteProtectTable_N25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_D_MODE}, TRUE, TRUE }, ++ { FLASH_IC_NUMONYX_M25PX16, MID_NUMONYX,0x73, 0x15, _pstWriteProtectTable_M25PX16, NULL, 0x200000, 32, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_DUAL_D_MODE }, TRUE, TRUE}, ++ { FLASH_IC_A25LM032, MID_AM, 0x30, 0x16, NULL, NULL, 0x400000, 64, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_54M , E_FAST_MODE }, FALSE, TRUE}, ++ { FLASH_IC_ZB25Q128, MID_ST, 0x70, 0x18, _pstWriteProtectTable_ZB25Q128, NULL, 0x1000000, 256, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_ST, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++ { FLASH_IC_ZB25Q64 , MID_EON, 0x70, 0x17, _pstWriteProtectTable_ZB25Q64 , NULL, 0x800000, 128, SIZE_64KB, 256, 50, BITS(5:2, 0x0F), ISP_DEV_PMC, ISP_SPI_ENDIAN_LITTLE, {E_SPI_86M , E_DUAL_AD_MODE}, TRUE, TRUE}, ++}; ++ +diff --git a/drivers/mstar/flash_isp/drvDeviceInfo.h b/drivers/mstar/flash_isp/drvDeviceInfo.h +new file mode 100644 +index 00000000..027afc89 +--- /dev/null ++++ b/drivers/mstar/flash_isp/drvDeviceInfo.h +@@ -0,0 +1,227 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file drvDeviceInfo.h ++/// @brief Serial Flash Device Information ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRV_DEVICE_INFO_H_ ++#define _DRV_DEVICE_INFO_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++#define FLASH_IC_UNKNOWN 0x0000UL ++// SST ++#define FLASH_IC_SST25VF080B 0x0100UL // 1M SST ++#define FLASH_IC_SST25VF016B 0x0101UL // 2M ++#define FLASH_IC_SST25VF032B 0x0102UL // 2M ++ ++#define FLASH_IC_PM25LV080 0x0200UL // 1M PMC ++#define FLASH_IC_PM25LV016 0x0201UL // 2M ++#define FLASH_IC_PM25LQ032C 0x0202UL // 4M ++ ++#define FLASH_IC_ST25P80_A 0x0300UL // 1M ST ++#define FLASH_IC_ST25P16_A 0x0301UL // 2M ++#define FLASH_IC_STM25P32 0x0302UL // 4M ++//ATMEL ++#define FLASH_IC_AT26DF081A 0x0400UL // 1M ATMEL ++#define FLASH_IC_AT26DF161 0x0401UL // 2M ++#define FLASH_IC_AT26DF321 0x0402UL // 4M ++#define FLASH_IC_AT25DF321A 0x0403UL // 4M ++ ++// MXIC ++#define FLASH_IC_MX25L8005 0x0500UL // 1M MXIC ++#define FLASH_IC_MX25L1655D 0x0501UL // 2M for secure option ++#define FLASH_IC_MX25L1606E 0x0502UL // 2M ++#define FLASH_IC_MX25L1605A 0x0503UL // 2M ++#define FLASH_IC_MX25L3206E 0x0504UL // 4M ++#define FLASH_IC_MX25L3205D 0x0505UL // 4M ++#define FLASH_IC_MX25L6405D 0x0506UL // 8M ++#define FLASH_IC_MX25L6406E 0x0507UL // 8M ++#define FLASH_IC_MX25L12805D 0x0508UL // 16M ++#define FLASH_IC_MX25L12845E 0x0509UL // 16M ++#define FLASH_IC_MX25L6445E 0x050AUL // 8M ++#define FLASH_IC_MX25L6455E 0x050BUL // 8M ++#define FLASH_IC_MX25L12855E 0x050CUL // 16M ++#define FLASH_IC_MX25L4006E 0x050DUL // 512K MXIC ++#define FLASH_IC_MX25L8006E 0x050EUL // 1M MXIC ++#define FLASH_IC_MX25L3255D 0x0512UL // 4M for secure option ++#define FLASH_IC_MX25L25645G 0x0513UL // 32M ++ ++// NX ++#define FLASH_IC_NX25P80 0x0600UL // 1M NX ++#define FLASH_IC_NX25P16 0x0601UL // 2M ++ ++// WINB ++#define FLASH_IC_W25X80 0x0700UL // 1M WINB ++#define FLASH_IC_W25Q80 0x0701UL // 1M ++#define FLASH_IC_W25Q16 0x0702UL // 2M ++#define FLASH_IC_W25X16 0x0703UL // 2M ++#define FLASH_IC_W25X32 0x0704UL // 4M ++#define FLASH_IC_W25Q32 0x0705UL // 4M ++#define FLASH_IC_W25X64 0x0706UL // 8M ++#define FLASH_IC_W25Q64 0x0707UL // 8M ++#define FLASH_IC_W25Q64CV 0x0708UL // 8M ++#define FLASH_IC_W25Q128 0x0709UL // 16M ++#define FLASH_IC_W25Q32BV 0x070AUL // 4M ++#define FLASH_IC_W25X40 0x070BUL // 512K WINB ++ ++//SPANSION ++#define FLASH_IC_S25FL008A 0x0800UL // 1M SPANSION ++#define FLASH_IC_S25FL016A 0x0801UL // 2M ++#define FLASH_IC_S25FL128P 0x0802UL // 16M ++#define FLASH_IC_S25FL032P 0x0803UL // 4M ++#define FLASH_IC_S25FL064P 0x0804UL // 8M ++#define FLASH_IC_S25FL032K 0x0805UL // 4M ++#define FLASH_IC_S25FL032 0x0804UL // 4M ++ ++// EON ++#define FLASH_IC_EN25F10 0x0900UL // 128K for secure boot ++#define FLASH_IC_EN25F16 0x0901UL // 2M ++#define FLASH_IC_EN25F32 0x0902UL // 4M ++#define FLASH_IC_EN25F80 0x0903UL // 1M ++#define FLASH_IC_EN25B20T 0x0904UL // 2M EON ++#define FLASH_IC_EN25B20B 0x0905UL // 2M ++#define FLASH_IC_EN25B10T 0x0906UL // 1M ++#define FLASH_IC_EN25B10B 0x0907UL // 1M ++#define FLASH_IC_EN25B32B 0x0908UL // 4M (Bottom Boot) ++#define FLASH_IC_EN25Q32 0x0909UL // 4M ++#define FLASH_IC_EN25Q32A 0x090AUL // 4M ++#define FLASH_IC_EN25Q64 0x090BUL // 4M ++#define FLASH_IC_EN25B64B 0x090CUL // 4M ++#define FLASH_IC_EN25Q128 0x090DUL // 16M ++#define FLASH_IC_EN25P16 0x090EUL // 2M ++#define FLASH_IC_EN25F40 0x090AUL // 512k ++#define FLASH_IC_EN25QH16 0x090BUL // 2M ++ ++// ESMT ++#define FLASH_IC_ESMT_F25L016A 0x0A00UL // 2M ++// GD ++#define FLASH_IC_GD25Q32 0x0B00UL // 4M ++#define FLASH_IC_GD25Q16 0x0B01UL // 2MByte ++#define FLASH_IC_GD25S80 0x0B02UL ++#define FLASH_IC_GD25Q64 0x0B03UL // 8M ++#define FLASH_IC_GD25Q128 0x0B05UL //16M ++#define FLASH_IC_GD25Q256C 0x0B06UL //32M ++ ++// AM ++#define FLASH_IC_A25LM032 0x0D00UL ++ ++// MICRON ++#define FLASH_IC_MICRON_M25P16 0x0E00UL // 2M ++#define FLASH_IC_MICRON_N25Q32 0x0E01UL // 4M ++#define FLASH_IC_MICRON_N25Q64 0x0E02UL // 8M ++#define FLASH_IC_MICRON_N25Q128 0x0E03UL // 16M ++#define FLASH_IC_NUMONYX_M25PX16 0x0E04UL // 2M ++ ++ ++//ZB ++#define FLASH_IC_ZB25Q64 0x1002UL // 8M ++#define FLASH_IC_ZB25Q128 0x1003UL // 16M ++ ++ ++// Flash Manufacture ID ++#define MID_MXIC 0xC2UL ++#define MID_WB 0xEFUL ++#define MID_EON 0x1CUL ++#define MID_ST 0x20UL ++#define MID_SST 0xBFUL ++#define MID_PMC 0x9DUL ++#define MID_ATMEL 0x1FUL ++#define MID_SPAN 0x01UL ++#define MID_GD 0xC8UL ++#define MID_MICRON 0x20UL ++#define MID_NUMONYX 0x20UL ++#define MID_AM 0x37UL ++ ++// Flash Storage Size ++#define SIZE_1KB 0x400UL ++#define SIZE_2KB 0x800UL ++#define SIZE_4KB 0x1000UL ++#define SIZE_8KB 0x2000UL ++#define SIZE_16KB 0x4000UL ++#define SIZE_32KB 0x8000UL ++#define SIZE_64KB 0x10000UL ++#define SIZE_128KB 0x20000UL ++#define SIZE_256KB 0x40000UL ++#define SIZE_512KB 0x80000UL ++#define SIZE_1MB 0x100000UL ++#define SIZE_2MB 0x200000UL ++#define SIZE_4MB 0x400000UL ++#define SIZE_8MB 0x800000UL ++#define SIZE_16MB 0x1000000UL ++ ++// ISP_DEV_SEL ++#define ISP_DEV_PMC BITS(2:0, 0) ++#define ISP_DEV_NEXTFLASH BITS(2:0, 1) ++#define ISP_DEV_ST BITS(2:0, 2) ++#define ISP_DEV_SST BITS(2:0, 3) ++#define ISP_DEV_ATMEL BITS(2:0, 4) ++ ++// ISP_SPI_ENDIAN_SEL ++#define ISP_SPI_ENDIAN_BIG BITS(0:0, 1) ++#define ISP_SPI_ENDIAN_LITTLE BITS(0:0, 0) ++ ++typedef struct ++{ ++ MS_U8 u8BlockProtectBits; // Block Protection Bits ++ MS_U32 u32LowerBound; ++ MS_U32 u32UpperBound; ++} ST_WRITE_PROTECT; ++ ++typedef struct ++{ ++ MS_U16 u16Start; // Start block # of special block size ++ MS_U16 u16End; // End block # of special block size ++ MS_U32 au32SizeList[8]; // List of special block sizes. Total size must be equal to FLASH_BLOCK_SIZE ++} ST_SPECIAL_BLOCKS; ++ ++ ++typedef struct ++{ ++ MS_U16 u16FlashType; // flash type ++ MS_U8 u8MID; // Manufacture ID ++ MS_U8 u8DID0; // Device ID (memory type) ++ MS_U8 u8DID1; // Device ID (memory capacity) ++ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ ST_SPECIAL_BLOCKS *pSpecialBlocks; ++ ++ MS_U32 u32FlashSize; // Flash Size ++ MS_U32 u32NumSec; // NUMBER_OF_SERFLASH_SECTORS // number of sectors ++ MS_U32 u32SecSize; // SERFLASH_SECTOR_SIZE // sector size ++ MS_U16 u16PageSize; // SERFLASH_PAGE_SIZE // page size ++ MS_U16 u16MaxChipWrDoneTimeout; // SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT // max timeout for chip write done ++ MS_U8 u8WrsrBlkProtect; // SERFLASH_WRSR_BLK_PROTECT // BP bits @ Serial Flash Status Register ++ MS_U16 u16DevSel; // ISP_DEV_SEL // reg_device_select ++ MS_U16 u16SpiEndianSel; // ISP_SPI_ENDIAN_SEL // reg_endian_sel_spi ++ MS_U16 u16SPIMaxClk[2]; ++ MS_BOOL b2XREAD; ++ MS_BOOL b4XREAD; ++} hal_SERFLASH_t; ++ ++#endif //_DRV_DEVICE_INFO_H_ ++ +diff --git a/drivers/mstar/flash_isp/drvSERFLASH.c b/drivers/mstar/flash_isp/drvSERFLASH.c +new file mode 100644 +index 00000000..34207e5e +--- /dev/null ++++ b/drivers/mstar/flash_isp/drvSERFLASH.c +@@ -0,0 +1,1077 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file drvSERFLASH.c ++/// @brief Serial Flash Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include "drvSERFLASH.h" ++ ++// Common Definition ++//#include "MsDevice.h" ++//#include "MsTypes.h" ++ ++// Internal Definition ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++//#include "drvBDMA.h" ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++#define VER_CHECK_HEADER 'M','S','V','C','0','0' ++#define SERFLASH_LIB_ID 'F','1' // F1: libFLASH.a ++#define SERFLASH_INTERFACE_VER '0','1' ++#define SERFLASH_BUILD_VER '0','0','0','1' ++#define CHANGE_LIST_NUM '0','0','0','9','1','9','9','6' ++#define PRODUCT_NAME 'A','E' // AE: T2 ++#define CUSTOMER_NAME '0' // 0: Mstar ++#define DEVELOP_STAGE 'B','L','E','G' ++#define OS_VERSION '0','0' ++#define CHECK_SUM 'T' ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local & Global Variables ++//////////////////////////////////////////////////////////////////////////////// ++//static MSIF_Version _drv_spif_version = { ++// .DDI = { SPIF_DRV_VERSION }, ++//}; ++ ++static SERFLASH_Info _SERFLASHInfo; ++static SERFLASH_DrvStatus _SERFLASHDrvStatus; ++ ++/// Ask 51 to select flash ++ms_Mcu_ChipSelect_CB McuChipSelectCB = NULL; ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++#define DRV_FLASH_MS(x) (5955 * x) ++#define FLASH_WAIT_TIME (DRV_FLASH_MS(100)*0x200UL) ++#define FLASH_IS_TIMEOUT(x) ((x) ? FALSE : TRUE) ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++#ifdef CONFIG_FLASH_ISP_READFUNC_MAP ++extern MS_BOOL HAL_DMA_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++extern MS_BOOL HAL_MAP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++MS_BOOL MDrv_MAP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ //MS_U8 *pu8BufAddr = (MS_U8*)MS_PA2KSEG0((MS_U32)pu8Data); // Physical Address to Virtual Address, cache. ++ ++ MS_ASSERT( u32FlashSize > 0 ); ++ MS_ASSERT( u32FlashAddr + u32FlashSize <= _SERFLASHInfo.u32TotalSize ); ++ //ASSERT( u32Addr%4 == 0 ); ++ //ASSERT( u32Size%4 == 0 ); ++ MS_ASSERT( user_buffer != NULL ); ++ //#ifdef MCU_MIPS ++ //MS_ASSERT( user_buffer & (0x80000000) ); ++ //#endif ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (int)u32FlashSize, user_buffer)); ++ return HAL_MAP_Read(u32FlashAddr, u32FlashSize, user_buffer); ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Get the information of Serial Flash ++/// @return the pointer to the driver information ++//------------------------------------------------------------------------------------------------- ++const SERFLASH_Info *MDrv_SERFLASH_GetInfo(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("MDrv_SERFLASH_GetInfo()\n" ++ "\tu32AccessWidth = %d\n" ++ "\tu32TotalSize = %d\n" ++ "\tu32SecNum = %d\n" ++ "\tu32SecSize = %d\n", ++ (int)(_SERFLASHInfo.u32AccessWidth), ++ (int)(_SERFLASHInfo.u32TotalSize), ++ (int)(_SERFLASHInfo.u32SecNum), ++ (int)(_SERFLASHInfo.u32SecSize) ++ ) ++ ); ++ ++ return &_SERFLASHInfo; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Show the SERFLASH driver version ++/// @param ppVersion \b OUT: output SERFLASH driver version ++/// @return TRUE : succeed ++/// @return FALSE : failed ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetLibVer(const MSIF_Version **ppVersion) ++{ ++// if (!ppVersion) ++// return FALSE; ++// ++// *ppVersion = &_drv_spif_version; ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Get Serial Flash driver status ++/// @param pDrvStatus \b OUT: poniter to store the returning driver status ++/// @return TRUE : succeed ++/// @return FALSE : failed to get the driver status ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetStatus(SERFLASH_DrvStatus* pDrvStatus) ++{ ++ memcpy(pDrvStatus, &_SERFLASHDrvStatus, sizeof(_SERFLASHDrvStatus)); ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : Set detailed level of Parallel Flash driver debug message ++/// @param u8DbgLevel \b IN debug level for Serial Flash driver ++/// @return TRUE : succeed ++/// @return FALSE : failed to set the debug level ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_SetDbgLevel(MS_U8 u8DbgLevel) ++{ ++ _u8SERFLASHDbgLevel = u8DbgLevel; ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------ ++/// Description : HK ask 8051 to select flash chip by call back function ++/// @param ms_Mcu_ChipSelect_CB \b IN call back function ++/// @return TRUE : succeed ++/// @return NULL : ++//------------------------------------------------------------------------------ ++void MDrv_SERFLASH_SetMcuCSCallBack(ms_Mcu_ChipSelect_CB ChipSel_cb) ++{ ++ McuChipSelectCB = ChipSel_cb; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash type by reading the MID and DID ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash type ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectType(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_DetectType(); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash Size ++/// @param u32FlashSize \b OUT: u32 ptr to store flash size ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash size ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_DetectSize(u32FlashSize); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enable Flash 2XREAD mode, if support ++/// @param b2XMode \b IN: ENABLE/DISABLE ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Set2XRead(MS_BOOL b2XMode) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_Set2XREAD(b2XMode); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set ckg_spi which flash supports (please ref. the spec. before using this function) ++/// @param SPI_DrvCKG \b IN: enumerate the ckg_spi ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not. It is safty to run at 43M (Default). ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetCKG(SPI_DrvCKG eCKGspi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_SetCKG(eCKGspi); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set clock div such that spi clock = mcu clock /clock_div. ++/// @param SPI_DrvClkDiv \b IN: enumerate the clock_div ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivspi) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ HAL_SERFLASH_ClkDiv(eClkDivspi); ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set XIU/RIU mode (Default : XIU) ++/// @param bXiuRiu \b IN: 1 for XIU, 0 for RIU ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note XIU mode is faster than RIU mode. It is stable to run by XIU (Default) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_SetMode(bXiuRiu); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set active flash among multi-spi flashes ++/// @param u8FlashIndex \b IN: The Flash index, 0 for external #1 spi flash, 1 for external #2 spi flash ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note For Secure booting = 0, please check hw_strapping or e-fuse (the board needs to jump) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ MS_ASSERT((u8FlashIndex < 4)); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ Ret = HAL_SERFLASH_ChipSelect(u8FlashIndex); ++ return Ret; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Initialize Serial Flash ++/// @return None ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_Init(void) ++{ ++ _u8SERFLASHDbgLevel = E_SERFLASH_DBGLV_ERR; // init debug level first //SERFLASH_DBGLV_DEBUG ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++#if 0 ++ // ++ // 1. HAL init ++ // ++ MS_U32 u32PMBank, u32PMBankSize; ++ MS_U32 u32NonPMBank, u32NonPMBankSize; ++ MS_U32 u32FlashBank0, u32FlashBank0Size; ++ ++ if (!MDrv_MMIO_GetBASE( &u32PMBank, &u32PMBankSize, MS_MODULE_ISP)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("IOMap failure to get DRV_MMIO_NONPM_BANK\n")); ++ } ++ ++ if (!MDrv_MMIO_GetBASE( &u32NonPMBank, &u32NonPMBankSize, MS_MODULE_MHEG5)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("IOMap failure to get DRV_MMIO_NONPM_BANK\n")); ++ } ++ ++ if (!MDrv_MMIO_GetBASE( &u32FlashBank0, &u32FlashBank0Size, MS_MODULE_FLASH)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("IOMap failure to get DRV_MMIO_NONPM_BANK\n")); ++ } ++ ++#endif ++ ++ HAL_SERFLASH_Config(); ++ ++ HAL_SERFLASH_Init(); ++ ++ HAL_SERFLASH_DetectType(); ++ ++ // ++ // 2. init SERFLASH_Info ++ // ++ _SERFLASHInfo.u32AccessWidth = 1; ++ _SERFLASHInfo.u32SecNum = NUMBER_OF_SERFLASH_SECTORS; ++ _SERFLASHInfo.u32SecSize = SERFLASH_SECTOR_SIZE; ++ //_SERFLASHInfo.u32TotalSize = (NUMBER_OF_SERFLASH_SECTORS * SERFLASH_SECTOR_SIZE); ++ HAL_SERFLASH_DetectSize(&_SERFLASHInfo.u32TotalSize); ++ // ++ // 3. init other data structure of Serial Flash driver ++ // ++ _SERFLASHDrvStatus.bIsBusy = FALSE; ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase all sectors in Serial Flash ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_EraseChip(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return HAL_SERFLASH_EraseChip(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start block index of a flash address ++/// @param u32FlashAddr \b IN: flash address ++/// @param pu32BlockIndex \b IN: poniter to store the returning block index ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_ASSERT(u32FlashAddr < _SERFLASHInfo.u32TotalSize); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %p)\n", __FUNCTION__, (int)u32FlashAddr, pu32BlockIndex)); ++ ++ return HAL_SERFLASH_AddressToBlock(u32FlashAddr, pu32BlockIndex); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start address of a block index ++/// @param u32BlockIndex \b IN: block index ++/// @param pu32FlashAddr \b IN: pointer to store the returning flash address ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ MS_ASSERT(u32BlockIndex < _SERFLASHInfo.u32SecNum); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %p)\n", __FUNCTION__, (int)u32BlockIndex, pu32FlashAddr)); ++ ++ return HAL_SERFLASH_BlockToAddress(u32BlockIndex, pu32FlashAddr); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors given starting address and size in Serial Flash ++/// @param u32StartAddr \b IN: start address at block boundry ++/// @param u32EraseSize \b IN: size to erase ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, MS_BOOL bWait) ++{ ++ MS_U32 u32StartBlock; ++ MS_U32 u32EndBlock; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, ++ (unsigned int)u32StartAddr, (unsigned int)u32EraseSize, (int)bWait)); ++ ++ if ( FALSE == MDrv_SERFLASH_AddressToBlock(u32StartAddr, &u32StartBlock) ++ || FALSE == MDrv_SERFLASH_AddressToBlock(u32StartAddr + u32EraseSize - 1, &u32EndBlock) ++ ) ++ { ++ return FALSE; ++ } ++ ++ return MDrv_SERFLASH_BlockErase(u32StartBlock, u32EndBlock, bWait); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors in Serial Flash ++/// @param u32StartBlock \b IN: start block ++/// @param u32EndBlock \b IN: end block ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock 0 ); ++ MS_ASSERT( u32FlashAddr + u32FlashSize <= _SERFLASHInfo.u32TotalSize ); ++ //ASSERT( u32Addr%4 == 0 ); ++ //ASSERT( u32Size%4 == 0 ); ++ MS_ASSERT( user_buffer != NULL ); ++ //#ifdef MCU_MIPS ++ //MS_ASSERT( user_buffer & (0x80000000) ); ++ //#endif ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (int)u32FlashSize, user_buffer)); ++ ++#ifdef CONFIG_FLASH_ISP_READFUNC_MAP ++ return HAL_MAP_Read(u32FlashAddr, u32FlashSize, user_buffer); ++#else ++ return HAL_SERFLASH_Read(u32FlashAddr, u32FlashSize, user_buffer); ++#endif ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnable \b IN: TRUE/FALSE: enable/disable protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, (int)bEnable)); ++ return HAL_SERFLASH_WriteProtect(bEnable); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Enable_All_Range(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_WriteProtect_Area(TRUE, 0 << 2); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Disables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_All_Range(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_WriteProtect_Disable_Range_Set(0, _SERFLASHInfo.u32TotalSize); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set flash disable lower bound and size ++/// @param u32DisableLowerBound \b IN: the lower bound to disable write protect ++/// @param u32DisableSize \b IN: size to disable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_Range_Set(MS_U32 u32DisableLowerBound, MS_U32 u32DisableSize) ++{ ++ MS_U32 u32EnableLowerBound; ++ MS_U32 u32EnableUpperBound; ++ MS_U8 u8BlockProtectBit; ++ ++ MS_U32 u32DisableUpperBound; ++ MS_U32 u32FlashIndexMax; ++ ++ EN_WP_AREA_EXISTED_RTN enWpAreaExistedRtn; ++ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ _SERFLASHDrvStatus.bIsBusy = TRUE; ++ ++ u32DisableUpperBound = u32DisableLowerBound + u32DisableSize - 1; ++ u32FlashIndexMax = _SERFLASHInfo.u32TotalSize - 1; ++ ++ ++ if ( u32DisableLowerBound > u32FlashIndexMax ++ || u32DisableUpperBound > u32FlashIndexMax ++ || u32DisableLowerBound > u32DisableUpperBound ++ ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk(" = FALSE, u32DisableLowerBound(0x%08X), u32DisableUpperBound(0x%08X), u32FlashIndexMax(0x%08X)\n", (int)u32DisableLowerBound, (int)u32DisableUpperBound, (int)u32FlashIndexMax)); ++ ++ return FALSE; ++ } ++ ++ ++ // Step 1. decide u32DisableUpperBound // TODO: review, prefer to unprotect the end of the flash ++ if ( u32DisableUpperBound != u32FlashIndexMax ++ && u32DisableLowerBound != 0 ++ ) ++ { ++ u32DisableUpperBound = u32FlashIndexMax; ++ } ++ ++ ++ // Step 2. decide u32EnableLowerBound & u32EnableUpperBound ++ if ( u32DisableUpperBound > (u32FlashIndexMax - _SERFLASHInfo.u32SecSize) ++ && u32DisableLowerBound == 0 ++ ) ++ { ++ // i.e. no protect ++ u32EnableLowerBound = 0xFFFFFFFFUL; ++ u32EnableUpperBound = 0xFFFFFFFFUL; ++ } ++ else if (u32DisableLowerBound == 0) ++ { ++ u32EnableUpperBound = u32FlashIndexMax; ++ u32EnableLowerBound = u32DisableUpperBound + 1; ++ } ++ else // i.e. (u32DisableUpperBound == u32FlashIndexMax) because of Step 1 ++ { ++ u32EnableUpperBound = u32DisableLowerBound - 1; ++ u32EnableLowerBound = 0; ++ } ++ ++ ++ // Step 3. get u8BlockProtectBit ++ enWpAreaExistedRtn = HAL_SERFLASH_WP_Area_Existed(u32EnableUpperBound, u32EnableLowerBound, &u8BlockProtectBit); ++ ++ switch (enWpAreaExistedRtn) ++ { ++ case WP_AREA_NOT_AVAILABLE: ++ case WP_TABLE_NOT_SUPPORT: ++ u8BlockProtectBit = 0; ++ break; ++ ++ default: ++ /* DO NOTHING */ ++ break; ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return HAL_SERFLASH_WriteProtect_Area(FALSE, u8BlockProtectBit); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnableAllArea \b IN: enable or disable protection ++/// @param u8BlockProtectBits \b IN: block protection bits which stand for the area to enable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, (int)bEnableAllArea, u8BlockProtectBits)); ++ return HAL_SERFLASH_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read ID from Serial Flash ++/// @param pu8FlashID \b OUT: Virtual data ptr to store the read ID ++/// @param u32IDSize \b IN: size in Bytes ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadID(MS_U8 *pu8FlashID, MS_U32 u32IDSize) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%p, %d)\n", __FUNCTION__, pu8FlashID, (int)u32IDSize)); ++ return HAL_SERFLASH_ReadID(pu8FlashID, u32IDSize); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read data from Serial Flash to DRAM in DMA mode ++/// @param u32FlashStart \b IN: src start address in flash (0 ~ flash size-1) ++/// @param u32DRAMStart \b IN: dst start address in DRAM (16B-aligned) (0 ~ DRAM size-1) ++/// @param u32Size \b IN: size in Bytes (8B-aligned) (>=8) ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++//MS_BOOL MDrv_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRAMStart, MS_U32 u32Size) ++//{ ++// MS_ASSERT( u32FlashStart+u32Size <= _SERFLASHInfo.u32TotalSize); ++// MS_ASSERT( u32DRAMStart%8 ==0 ); ++// MS_ASSERT( u32Size%8 ==0 ); ++// MS_ASSERT( u32Size>=8 ); ++// ++// DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++// return HAL_SERFLASH_DMA(u32FlashStart, u32DRAMStart, u32Size); ++//} ++ ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister(MS_U8 *pu8StatusReg) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_ReadStatusReg(pu8StatusReg); ++} ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register2 in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register (high-byte) ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_ReadStatusReg2(pu8StatusReg); ++} ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Write Status Register in Serial Flash ++/// @param u16StatusReg \b IN: Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteStatusRegister(MS_U16 u16StatusReg) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ return HAL_SERFLASH_WriteStatusReg(u16StatusReg); ++} ++ ++////------- ------------------------------------------------------------------------------------------ ++///// Description : Handle for BDMA copy data from ONLY Flash src to other dst ++///// @param u32FlashAddr \b IN: Physical Source address in spi flash ++///// @param u32DramAddr \b IN: Physical Dst address ++///// @param u32Len \b IN: data length ++///// @param eDstDev \b IN: The Dst Device of Flash BDMA ++///// @param u8OpCfg \b IN: u8OpCfg: default is SPIDMA_OPCFG_DEF ++///// - Bit0: inverse mode --> SPIDMA_OPCFG_INV_COPY ++///// - Bit2: Copy & CRC check in wait mode --> SPIDMA_OPCFG_CRC_COPY ++///// - Bit3: Copy without waiting --> SPIDMA_OPCFG_NOWAIT_COPY ++///// @return \b MS_BOOL ++///// [NONOS_SUPPORT] ++///// [fw : drvBDMA ] ++////------------------------------------------------------------------------------------------------- ++//MS_BOOL MDrv_SERFLASH_CopyHnd(MS_PHYADDR u32FlashAddr, ++// MS_PHYADDR u32DstAddr, ++// MS_U32 u32Len, ++// SPIDMA_Dev eDstDev, ++// MS_U8 u8OpCfg) ++//{ ++// #define BDMA_DEV_FLASH 5 ++// MS_U16 CpyType = ((BDMA_DEV_FLASH & 0x0F) | _LShift((eDstDev &0x0F), 8)); ++// MS_U32 u32Delay = FLASH_WAIT_TIME; ++// ++// while (!HAL_SERFLASH_CheckWriteDone()) ++// { ++// if (FLASH_IS_TIMEOUT(u32Delay)) ++// { ++// printk("%s() : DMA flash is busy!\n",__FUNCTION__); ++// return FALSE; ++// } ++// u32Delay--; ++// } ++// ++// return MDrv_BDMA_CopyHnd(u32FlashAddr, u32DstAddr, u32Len, (BDMA_CpyType) CpyType, u8OpCfg); ++//} ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Switch SPI as GPIO Input ++/// @param bSwitch \b IN: 1 for GPIO, 0 for NORMAL ++/// @note Not allowed in interrupt context ++/// @note For project's power consumption ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ HAL_SERFLASH_SetGPIO(bSwitch); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// FSP ++//------------------------------------------------------------------------------------------------- ++/* ++MS_BOOL MDrv_FSP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ MS_U32 Index; ++ ++#define FSP_READ_SIZE 4 ++ ++ for(Index = 0; Index < u32FlashSize; ) ++ { ++ HAL_SERFLASH_ReadWordFlashByFSP(u32FlashAddr+Index, user_buffer+Index); ++ Index += FSP_READ_SIZE; ++ } ++ ++ return 1; ++} ++ ++MS_BOOL MDrv_FSP_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ MS_U32 Index; ++ MS_U32 u32ProgData; ++ ++#define FSP_WRITE_SIZE 4 ++ ++ for(Index = 0; Index < u32FlashSize; ) ++ { ++ u32ProgData = (*(user_buffer + Index))|(*(user_buffer + Index + 1)<<8)|(*(user_buffer + Index + 2)<<16)|(*(user_buffer + Index + 3)<<24); ++ HAL_SERFLASH_ProgramFlashByFSP(u32FlashAddr+Index, u32ProgData); ++ Index += FSP_WRITE_SIZE; ++ } ++ ++ return 1; ++} ++ ++ ++MS_BOOL MDrv_FSP_ReadStatusRegister(MS_U8 *pu8StatusReg) ++{ ++ *pu8StatusReg = HAL_SERFLASH_ReadStatusByFSP(); ++ ++ return 1; ++} ++ ++MS_BOOL MDrv_FSP_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, E_FSP_ERASE eERASE) ++{ ++ MS_U32 Index; ++ ++ switch ( eERASE ) ++ { ++ case E_FSP_ERASE_4K: ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseSectorByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_4K; ++ } ++ } ++ break; ++ case E_FSP_ERASE_32K: ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseBlock32KByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_32K; ++ } ++ } ++ break; ++ case E_FSP_ERASE_64K: ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseBlock64KByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_64K; ++ } ++ } ++ break; ++ default : ++ { ++ for(Index = 0; Index < u32EraseSize; ) ++ { ++ HAL_SERFLASH_EraseBlock64KByFSP(u32StartAddr + Index); ++ Index += (MS_U32)E_FSP_ERASE_64K; ++ } ++ } ++ break; ++ } ++ return 1; ++} ++*/ ++ ++MS_BOOL MDrv_SERFLASH_QPI_ENABLE(MS_BOOL bEnable) ++{ ++ return HAL_QPI_Enable( bEnable); ++} ++ ++MS_BOOL MDrv_SERFLASH_QPI_REST(MS_BOOL bEnable) ++{ ++ return HAL_QPI_RESET( bEnable); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// WRAPPER FOR CHAKRA ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_FLASH_QPI_ENALBE(MS_BOOL bEnable) ++{ ++ return MDrv_SERFLASH_QPI_ENABLE( bEnable); ++} ++ ++MS_BOOL MDrv_FLASH_QPI_REST(MS_BOOL bEnable) ++{ ++ return MDrv_SERFLASH_QPI_REST( bEnable); ++} ++ ++MS_BOOL MDrv_FLASH_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s( 0x%x, 0x%x, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (unsigned int)u32FlashSize, user_buffer)); ++ return MDrv_SERFLASH_Write(u32FlashAddr, u32FlashSize, user_buffer); ++ ++} ++ ++MS_BOOL MDrv_FLASH_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s( 0x%x, 0x%x, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, (unsigned int)u32FlashSize, user_buffer)); ++ return MDrv_SERFLASH_Read(u32FlashAddr, u32FlashSize, user_buffer); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect(MS_BOOL bEnable) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, (int)bEnable)); ++ return MDrv_SERFLASH_WriteProtect(bEnable); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Enable_All_Range(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_WriteProtect_Enable_All_Range(); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_All_Range(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_WriteProtect_Disable_All_Range(); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_Range_Set(MS_U32 DisableLowerBound, MS_U32 DisableSize) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%x, 0x%x)\n", __FUNCTION__, (unsigned int)DisableLowerBound, (unsigned int)DisableSize)); ++ return MDrv_SERFLASH_WriteProtect_Disable_Range_Set(DisableLowerBound, DisableSize); ++} ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 BlockProtectBits) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02x)\n", __FUNCTION__, (int)bEnableAllArea, BlockProtectBits)); ++ return MDrv_SERFLASH_WriteProtect_Area(bEnableAllArea, BlockProtectBits); ++} ++ ++MS_BOOL MDrv_FLASH_ReadStatusRegister(MS_U8 *pu8StatusReg) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%p)\n", __FUNCTION__, pu8StatusReg)); ++ return MDrv_SERFLASH_ReadStatusRegister(pu8StatusReg); ++} ++ ++MS_BOOL MDrv_FLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%p)\n", __FUNCTION__, pu8StatusReg)); ++ return MDrv_SERFLASH_ReadStatusRegister2(pu8StatusReg); ++} ++ ++MS_BOOL MDrv_FLASH_WriteStatusRegister(MS_U16 u16StatusReg) ++{ ++ return MDrv_SERFLASH_WriteStatusRegister(u16StatusReg); ++} ++MS_BOOL MDrv_FLASH_DetectType(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_DetectType(); ++} ++ ++MS_BOOL MDrv_FLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_DetectSize(u32FlashSize); ++} ++MS_BOOL MDrv_FLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, %p)\n", __FUNCTION__, (unsigned int)u32FlashAddr, pu16BlockIndex)); ++ return MDrv_SERFLASH_AddressToBlock(u32FlashAddr, pu32BlockIndex); ++} ++ ++MS_BOOL MDrv_FLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%04x, %p)\n", __FUNCTION__, u16BlockIndex, pu32FlashAddr)); ++ return MDrv_SERFLASH_BlockToAddress(u32BlockIndex, pu32FlashAddr); ++} ++ ++MS_BOOL MDrv_FLASH_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, MS_BOOL bWait) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartAddr, (unsigned int)u32Size, (int)bWait)); ++ return MDrv_SERFLASH_AddressErase(u32StartAddr, u32EraseSize, bWait); ++} ++ ++MS_BOOL MDrv_FLASH_BlockErase(MS_U16 u16StartBlock, MS_U16 u16EndBlock, MS_BOOL bWait) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%04x, 0x%04x, %d)\n", __FUNCTION__, u16StartBlock, u16EndBlock, (int)bWait)); ++ return MDrv_SERFLASH_BlockErase(u16StartBlock, u16EndBlock, bWait); ++} ++ ++MS_BOOL MDrv_FLASH_CheckWriteDone(void) ++{ ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ return MDrv_SERFLASH_CheckWriteDone(); ++} ++ ++ ++//MS_BOOL MsOS_In_Interrupt (void) ++inline MS_BOOL MS_SERFLASH_IN_INTERRUPT (void) ++{ ++ return FALSE; ++} ++ ++//MS_S32 MsOS_CreateMutex ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag) ++inline MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag) ++{ ++ return 1; ++} ++ ++//MS_BOOL MsOS_DeleteMutex (MS_S32 s32MutexId) ++inline MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId) ++{ ++ return TRUE; ++} ++ ++//MS_BOOL MsOS_ObtainMutex (MS_S32 s32MutexId, MS_U32 u32WaitMs) ++inline MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs) ++{ ++ return TRUE; ++} ++ ++//MS_BOOL MsOS_ReleaseMutex (MS_S32 s32MutexId) ++inline MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId) ++{ ++ return TRUE; ++} ++ +diff --git a/drivers/mstar/flash_isp/drvSERFLASH.h b/drivers/mstar/flash_isp/drvSERFLASH.h +new file mode 100644 +index 00000000..295fa95e +--- /dev/null ++++ b/drivers/mstar/flash_isp/drvSERFLASH.h +@@ -0,0 +1,512 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file drvSERFLASH.h ++/// @brief Serial Flash Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRV_SERFLASH_H_ ++#define _DRV_SERFLASH_H_ ++ ++//#include ++//#include "drvBDMA.h" ++#include "MsTypes.h" ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MSIF_SPIF_LIB_CODE {'S','P','I','F'} //Lib code ++#define MSIF_SPIF_LIBVER {'0','1'} //LIB version ++#define MSIF_SPIF_BUILDNUM {'0','1'} //Build Number ++#define MSIF_SPIF_CHANGELIST {'0','0','1','1','4','5','3','4'} //P4 ChangeList Number ++ ++//------------------------------------------------------------------------------------------------- ++// Version String Definition ++//------------------------------------------------------------------------------------------------- ++// Move from MsVersion.h ++#define MSIF_TAG {'M','S','I','F'} // MSIF ++#define MSIF_CLASS {'0','0'} // DRV/API (DDI) ++#define MSIF_CUS 0x0000UL // MStar Common library ++#define MSIF_MOD 0x0000UL // MStar Common library ++#define MSIF_CHIP 0x000FUL ++#define MSIF_CPU '1' ++#define MSIF_OS '0' ++ ++#define SPIF_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_TAG, /* 'MSIF' */ \ ++ MSIF_CLASS, /* '00' */ \ ++ MSIF_CUS, /* 0x0000 */ \ ++ MSIF_MOD, /* 0x0000 */ \ ++ MSIF_CHIP, \ ++ MSIF_CPU, \ ++ MSIF_SPIF_LIB_CODE, /* IP__ */ \ ++ MSIF_SPIF_LIBVER, /* 0.0 ~ Z.Z */ \ ++ MSIF_SPIF_BUILDNUM, /* 00 ~ 99 */ \ ++ MSIF_SPIF_CHANGELIST, /* CL# */ \ ++ MSIF_OS ++ ++/// Operation cfg ++#define SPIDMA_CFG_ADDR_DIR_BIT (0) ++#define SPIDMA_CFG_REFLECT_BIT (1) ++#define SPIDMA_CFG_CRCCOPY_BIT (2) ++#define SPIDMA_CFG_NOWAITCOPY_BIT (3) ++ ++#define SPIDMA_OPCFG_DEF (0) ++#define SPIDMA_OPCFG_INV_COPY _LShift(1, SPIDMA_CFG_ADDR_DIR_BIT) ++#define SPIDMA_OPCFG_CRC_REFLECT _LShift(1, SPIDMA_CFG_REFLECT_BIT) //bit reflection of each input byte ++#define SPIDMA_OPCFG_CRC_COPY _LShift(1, SPIDMA_CFG_CRCCOPY_BIT) //copy then crc check ++#define SPIDMA_OPCFG_NOWAIT_COPY _LShift(1, SPIDMA_CFG_NOWAITCOPY_BIT) //copy then quit ++ ++#define MS_ASSERT(condition) // ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++/// Serial Flash information structure ++typedef struct ++{ ++ MS_U32 u32AccessWidth; //data access width in bytes ++ MS_U32 u32TotalSize; //total size in bytes ++ MS_U32 u32SecNum; //number of sectors ++ MS_U32 u32SecSize; //sector size in bytes ++} SERFLASH_Info; ++ ++typedef struct ++{ ++ MS_BOOL bIsBusy; ++} SERFLASH_DrvStatus; ++ ++typedef enum ++{ ++ E_SERFLASH_DBGLV_NONE, //disable all the debug message ++ E_SERFLASH_DBGLV_INFO, //information ++ E_SERFLASH_DBGLV_NOTICE, //normal but significant condition ++ E_SERFLASH_DBGLV_WARNING, //warning conditions ++ E_SERFLASH_DBGLV_ERR, //error conditions ++ E_SERFLASH_DBGLV_CRIT, //critical conditions ++ E_SERFLASH_DBGLV_ALERT, //action must be taken immediately ++ E_SERFLASH_DBGLV_EMERG, //system is unusable ++ E_SERFLASH_DBGLV_DEBUG //debug-level messages ++} SERFLASH_DbgLv; ++ ++typedef enum _SPIDMA_Dev ++{ ++ E_SPIDMA_DEV_MIU0, ++ E_SPIDMA_DEV_MIU1, ++ E_SPIDMA_DEV_DMDMCU = 6, ++ E_SPIDMA_DEV_VDMCU, ++ E_SPIDMA_DEV_DSP, ++ E_SPIDMA_DEV_TSP, ++ E_SPIDMA_DEV_1KSRAM_HK51, ++ E_SPIDMA_DEV_NOT_SUPPORT ++}SPIDMA_Dev; ++ ++typedef enum _SPI_DrvCKG ++{ ++ E_SPI_XTALI = 0, ++ E_SPI_27M, ++ E_SPI_36M, ++ E_SPI_43M, ++ E_SPI_54M, ++ E_SPI_72M, ++ E_SPI_86M, ++ E_SPI_108M, ++ E_SPI_24M = 15, // T3 only ++ E_SPI_HALCKG_NOT_SUPPORT ++}SPI_DrvCKG; ++ ++typedef enum _SPI_DrvClkDiv ++{ ++ E_SPI_DIV2 ++ ,E_SPI_DIV4 ++ ,E_SPI_DIV8 ++ ,E_SPI_DIV16 ++ ,E_SPI_DIV32 ++ ,E_SPI_DIV64 ++ ,E_SPI_DIV128 ++ ,E_SPI_ClkDiv_NOT_SUPPORT ++}SPI_DrvClkDiv; ++ ++typedef enum _E_FSP_ERASE ++{ ++ E_FSP_ERASE_4K = 0x1000, ++ E_FSP_ERASE_32K = 0x8000, ++ E_FSP_ERASE_64K = 0x10000, ++}E_FSP_ERASE; ++ ++///SPI CS callback ++typedef void (*ms_Mcu_ChipSelect_CB)(void); ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get the information of Serial Flash ++/// @return the pointer to the driver information ++//------------------------------------------------------------------------------------------------- ++const SERFLASH_Info *MDrv_SERFLASH_GetInfo(void); ++ ++//------------------------------------------------------------------------------ ++/// Description : Show the SERFLASH driver version ++/// @param ppVersion \b OUT: output NORF driver version ++/// @return TRUE : succeed ++/// @return FALSE : failed ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetLibVer(const MSIF_Version **ppVersion); ++ ++//------------------------------------------------------------------------------ ++/// Description : Get Serial Flash driver status ++/// @param pDrvStatus \b OUT: poniter to store the returning driver status ++/// @return TRUE : succeed ++/// @return FALSE : failed to get the driver status ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_GetStatus(SERFLASH_DrvStatus* pDrvStatus); ++ ++//------------------------------------------------------------------------------ ++/// Description : Set detailed level of Parallel Flash driver debug message ++/// @param u8DbgLevel \b IN debug level for Serial Flash driver ++/// @return TRUE : succeed ++/// @return FALSE : failed to set the debug level ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_SERFLASH_SetDbgLevel(MS_U8 u8DbgLevel); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash type by reading the MID and DID ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash type ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectType(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Detect flash Size ++/// @return TRUE : succeed ++/// @return FALSE : unknown flash size ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enable Flash 2XREAD mode, if support ++/// @param b2XMode \b IN: ENABLE/DISABLE ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Set2XRead(MS_BOOL b2XMode); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set ckg_spi which flash supports (please ref. the spec. before using this function) ++/// @param SPI_DrvCKG \b IN: enumerate the ckg_spi ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note Please ref. sprc. to confirm Flash support or not. It is safty to run at 43M (Default). ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetCKG(SPI_DrvCKG eCKGspi); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set XIU/RIU mode (Default : XIU) ++/// @param bXiuRiu \b IN: 1 for XIU, 0 for RIU ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note XIU mode is faster than RIU mode. It is stable to run by XIU (Default) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set active flash among multi-spi flashes ++/// @param u8FlashIndex \b IN: The Flash index, 0 for external #1 spi flash, 1 for external #2 spi flash ++/// @return TRUE : succeed ++/// @return FALSE : not succeed ++/// @note For Secure booting = 0, please check hw_strapping or e-fuse (the board needs to jump) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++ ++//------------------------------------------------------------------------------------------------- ++/// Initialize Serial Flash ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_Init(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read ID from Serial Flash ++/// @param pu8FlashID \b OUT: Virtual data ptr to store the read ID ++/// @param u32IDSize \b IN: size in Bytes ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadID(MS_U8 *pu8FlashID, MS_U32 u32IDSize); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read data from Serial Flash ++/// @param u32FlashAddr \b IN: Flash Address ++/// @param u32FlashSize \b IN: Flash Size Data in Bytes ++/// @param user_buffer \b OUT: Virtual Buffer Address ptr to store flash read data ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase all sectors in Serial Flash ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_EraseChip(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start block index of a flash address ++/// @param u32FlashAddr \b IN: flash address ++/// @param pu32BlockIndex \b IN: poniter to store the returning block index ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Get flash start address of a block index ++/// @param u32BlockIndex \b IN: block index ++/// @param pu32FlashAddr \b IN: pointer to store the returning flash address ++/// @return TRUE : succeed ++/// @return FALSE : illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors given starting address and size in Serial Flash ++/// @param u32StartAddr \b IN: start address at block boundry ++/// @param u32EraseSize \b IN: size to erase ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, MS_BOOL bWait); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain sectors in Serial Flash ++/// @param u32StartBlock \b IN: start block ++/// @param u32EndBlock \b IN: end block ++/// @param bWait \b IN: wait write done or not ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Erase certain 4K sectors in Serial Flash ++/// @param u32StartBlock \b IN: start address ++/// @param u32EndBlock \b IN: end address ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_SectorErase(MS_U32 u32StartAddr, MS_U32 u32EndAddr); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Check write done in Serial Flash ++/// @return TRUE : done ++/// @return FALSE : not done ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_CheckWriteDone(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Write data to Serial Flash ++/// @param u32FlashAddr \b IN: start address (4-B aligned) ++/// @param u32FlashSize \b IN: size in Bytes (4-B aligned) ++/// @param user_buffer \b IN: Virtual Buffer Address ptr to flash write data ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Read data from Serial Flash to DRAM in DMA mode ++/// @param u32FlashStart \b IN: src start address in flash (0 ~ flash size-1) ++/// @param u32DRAMStart \b IN: dst start address in DRAM (16B-aligned) (0 ~ DRAM size-1) ++/// @param u32Size \b IN: size in Bytes (8B-aligned) (>=8) ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++/// @note ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRAMStart, MS_U32 u32Size); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnable \b IN: TRUE/FALSE: enable/disable protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect(MS_BOOL bEnable); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Enables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Enable_All_Range(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Disables all range of flash write protection ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_All_Range(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Set flash disable lower bound and size ++/// @param u32DisableLowerBound \b IN: the lower bound to disable write protect ++/// @param u32DisableSize \b IN: size to disable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout or illegal parameters ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Disable_Range_Set(MS_U32 u32DisableLowerBound, MS_U32 u32DisableSize); ++ ++//------------------------------------------------------------------------------------------------- ++/// Description : Protect blocks in Serial Flash ++/// @param bEnableAllArea \b IN: enable or disable protection ++/// @param u8BlockProtectBits \b IN: block protection bits which stand for the area to enable write protect ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister(MS_U8 *pu8StatusReg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Read Status Register2 in Serial Flash ++/// @param pu8StatusReg \b OUT: ptr to Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register (high-byte) ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Write Status Register in Serial Flash ++/// @param u16StatusReg \b IN: Status Register value ++/// @return TRUE : succeed ++/// @return FALSE : fail before timeout ++/// @note Not allowed in interrupt context ++/// @note For Specific Flash IC with 16-bit status register ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_WriteStatusRegister(MS_U16 u16StatusReg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Handle for BDMA copy data from ONLY Flash src to other dst ++/// @param u32FlashAddr \b IN: Physical Source address in spi flash ++/// @param u32DramAddr \b IN: Physical Dst address ++/// @param u32Len \b IN: data length ++/// @param eDstDev \b IN: The Dst Device of Flash BDMA ++/// @param u8OpCfg \b IN: u8OpCfg: default is SPIDMA_OPCFG_DEF ++/// - Bit0: inverse mode --> SPIDMA_OPCFG_INV_COPY ++/// - Bit2: Copy & CRC check in wait mode --> SPIDMA_OPCFG_CRC_COPY ++/// - Bit3: Copy without waiting --> SPIDMA_OPCFG_NOWAIT_COPY ++/// @return \b MS_BOOL ++/// [NONOS_SUPPORT] ++/// [fw : drvBDMA ] ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_SERFLASH_CopyHnd(MS_PHYADDR u32FlashAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, SPIDMA_Dev eDstDev, MS_U8 u8OpCfg); ++ ++//------- ------------------------------------------------------------------------------------------ ++/// Description : Switch SPI as GPIO Input ++/// @param bSwitch \b IN: 1 for GPIO, 0 for NORMAL ++/// @note Not allowed in interrupt context ++/// @note For project's power consumption ++/// [NONOS_SUPPORT] ++//------------------------------------------------------------------------------------------------- ++void MDrv_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++ ++//------------------------------------------------------------------------------------------------- ++// WRAPPER FOR CHAKRA ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MDrv_FLASH_Write(MS_U32 u32FlashAddr,MS_U32 u32FlashSize,MS_U8 * user_buffer); ++MS_BOOL MDrv_FLASH_Read(MS_U32 u32FlashAddr,MS_U32 u32FlashSize,MS_U8 * user_buffer); ++MS_BOOL MDrv_FLASH_WriteProtect(MS_BOOL bEnable); ++ ++MS_BOOL MDrv_FLASH_WriteProtect_Enable_All_Range(void); ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_All_Range(void); ++MS_BOOL MDrv_FLASH_WriteProtect_Disable_Range_Set(MS_U32 DisableLowerBound, MS_U32 DisableSize); ++MS_BOOL MDrv_FLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 BlockProtectBits); ++MS_BOOL MDrv_FLASH_ReadStatusRegister(MS_U8 *pu8StatusReg); ++MS_BOOL MDrv_FLASH_ReadStatusRegister2(MS_U8 *pu8StatusReg); ++MS_BOOL MDrv_FLASH_WriteStatusRegister(MS_U16 u16StatusReg); ++ ++MS_BOOL MDrv_FLASH_DetectType(void); ++MS_BOOL MDrv_FLASH_DetectSize(MS_U32 *u32FlashSize); ++MS_BOOL MDrv_FLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++MS_BOOL MDrv_FLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++MS_BOOL MDrv_FLASH_AddressErase(MS_U32 u32StartAddr,MS_U32 u32EraseSize,MS_BOOL bWait); ++MS_BOOL MDrv_FLASH_BlockErase(MS_U16 u16StartBlock,MS_U16 u16EndBlock,MS_BOOL bWait); ++MS_BOOL MDrv_FLASH_CheckWriteDone(void); ++ ++//Flash Self-Programming (FSP) ++ ++//MS_BOOL MDrv_FSP_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++//MS_BOOL MDrv_FSP_Write(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++MS_BOOL MDrv_FSP_ReadStatusRegister(MS_U8 *pu8StatusReg); ++MS_BOOL MDrv_FSP_AddressErase(MS_U32 u32StartAddr, MS_U32 u32EraseSize, E_FSP_ERASE eERASE); ++ ++ ++extern ms_Mcu_ChipSelect_CB McuChipSelectCB; ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _DRV_SERFLASH_H_ +diff --git a/drivers/mstar/flash_isp/include/MsTypes.h b/drivers/mstar/flash_isp/include/MsTypes.h +new file mode 100644 +index 00000000..abed67ee +--- /dev/null ++++ b/drivers/mstar/flash_isp/include/MsTypes.h +@@ -0,0 +1,210 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsTypes.h ++/// @brief MStar General Data Types ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_TYPES_H_ ++#define _MS_TYPES_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// data type unsigned char, data length 1 byte ++typedef unsigned char MS_U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short MS_U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned long MS_U32; // 4 bytes ++/// data type unsigned int, data length 8 byte ++typedef unsigned long long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed long MS_S32; // 4 bytes ++/// data type signed int, data length 8 byte ++typedef signed long long MS_S64; // 8 bytes ++/// data type float, data length 4 byte ++typedef float MS_FLOAT; // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++/// data type hardware physical address ++typedef unsigned long MS_PHYADDR; // 32bit physical address ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++/// definition for MS_BOOL ++typedef unsigned char MS_BOOL; ++/// definition for VOID ++//typedef void VOID; ++/// definition for FILEID ++typedef MS_S32 FILEID; ++ ++//[TODO] use MS_U8, ... instead ++// data type for 8051 code ++//typedef MS_U16 WORD; ++//typedef MS_U8 BYTE; ++ ++ ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++ ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++///Define MS FB Format, to share with GE,GOP ++/// FIXME THE NAME NEED TO BE REFINED, AND MUST REMOVE UNNESSARY FMT ++typedef enum ++{ ++ /// color format I1 ++ E_MS_FMT_I1 = 0x0, ++ /// color format I2 ++ E_MS_FMT_I2 = 0x1, ++ /// color format I4 ++ E_MS_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ E_MS_FMT_I8 = 0x4, ++ /// color format blinking display ++ E_MS_FMT_FaBaFgBg2266 = 0x6, ++ /// color format for blinking display format ++ E_MS_FMT_1ABFgBg12355 = 0x7, ++ /// color format RGB565 ++ E_MS_FMT_RGB565 = 0x8, ++ /// color format ARGB1555 ++ /// @note [URANUS] ARGB1555 is only RGB555 ++ E_MS_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ E_MS_FMT_ARGB4444 = 0xa, ++ /// color format ARGB1555 DST ++ E_MS_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ E_MS_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ E_MS_FMT_ARGB8888 = 0xf, ++ /// color format RGBA5551 ++ E_MS_FMT_RGBA5551 = 0x10, ++ /// color format RGBA4444 ++ E_MS_FMT_RGBA4444 = 0x11, ++ /// color format ABGR8888 ++ E_MS_FMT_ABGR8888 = 0x1f, ++ ++ E_MS_FMT_GENERIC = 0xFFFF, ++ ++} MS_ColorFormat; ++ ++ ++typedef union _MSIF_Version ++{ ++ struct _DDI ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 model; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 change[8]; ++ MS_U8 os; ++ } MS_DDI; ++ struct _MW ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 mod; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 changelist[8]; ++ MS_U8 os; ++ } MW; ++ struct _APP ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U8 id[4]; ++ MS_U8 quality; ++ MS_U8 version[4]; ++ MS_U8 time[6]; ++ MS_U8 changelist[8]; ++ MS_U8 reserve[3]; ++ } APP; ++} MSIF_Version; ++ ++typedef struct _MS_SW_VERSION_INFO ++{ ++ char UtopiaBspVersion[8]; //Utopia BSP Version ++ char MajorVersion[4]; //Major Version Number ++ char MinorVersion[4]; //Minor Version Number ++ char ChangeList_API[16]; //Sync Perforce Change List Number in API Folder ++ char ChangeList_DRV[16]; //Sync Perforce Change List Number in DRV Folder ++ char ChangeList_HAL[16]; //Sync Perforce Change List Number in HAL Folder ++ ++} MS_SW_VERSION_INFO; ++ ++/// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/mstar/flash_isp/infinity3/halSERFLASH.c b/drivers/mstar/flash_isp/infinity3/halSERFLASH.c +new file mode 100644 +index 00000000..2497c6b2 +--- /dev/null ++++ b/drivers/mstar/flash_isp/infinity3/halSERFLASH.c +@@ -0,0 +1,4872 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include ++#include ++#include ++ ++// Common Definition ++#include "../include/ms_platform.h" ++#include "../include/ms_msys.h" ++ ++ ++// Internal Definition ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#include "regSERFLASH.h" ++#include "halSERFLASH.h" ++ ++ ++ ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++#if 0 ++ //Both read and write via IRUISP ++ #define CONFIG_RIUISP 1 ++ #define XIUREAD_MODE 0 //not use ++#else ++ ++//Select FSP read function ++ //#define CONFIG_FSP_READ_RIUOP 1 ++ //#define CONFIG_FSP_READ_BDMA 1 ++ #define CONFIG_FSP_READ_DIRERECT 1 ++ ++//Select FSP write function ++ //#define CONFIG_FSP_WRITE_RIUOP 1 ++ //#define CONFIG_FSP_WRITE_RIUOP_BRUST 1 ++ #define CONFIG_FSP_WRITE_BDMA 1 ++ ++#endif ++ ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++#define WRITE_BYTE(_reg, _val) {(*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++#define WRITE_WORD(_reg, _val) {(*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#define WRITE_LONG(_reg, _val) {(*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#define WRITE_WORD_MASK(_reg, _val, _mask) {(*((volatile MS_U16*)(_reg))) = ((*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask)); } ++//#define WRITE_WORD_MASK(_reg, _val, _mask) {*((volatile MS_U16*)(_reg)) = (*((volatile MS_U16*)(_reg))) & ~(_mask)) | ((MS_U16)(_val) & (_mask); } ++ ++ ++// XIU_ADDR ++// #define SFSH_XIU_REG32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) ++ ++//#define SFSH_XIU_READ32(addr) (*((volatile MS_U32 *)(_hal_isp.u32XiuBaseAddr + ((addr)<<2)))) // TODO: check AEON 32 byte access order issue ++// ++ ++// ISP_CMD ++// #define ISP_REG16(addr) (*((volatile MS_U16 *)(_hal_isp.u32IspBaseAddr + ((addr)<<2)))) ++ ++#define ISP_READ(addr) READ_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2)) ++#define ISP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val)) ++#define ISP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32IspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define FSP_READ(addr) READ_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2)) ++#define FSP_WRITE(addr, val) WRITE_WORD(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val)) ++#define FSP_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32FspBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define QSPI_READ(addr) READ_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2)) ++#define QSPI_WRITE(addr, val) WRITE_WORD(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val)) ++#define QSPI_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32QspiBaseAddr + ((addr)<<2), (val), (mask)) ++ ++#define SPI_FLASH_CMD(u8FLASHCmd) ISP_WRITE(REG_ISP_SPI_COMMAND, (MS_U8)u8FLASHCmd) ++#define SPI_WRITE_DATA(u8Data) ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)u8Data) ++#define SPI_READ_DATA() READ_BYTE(_hal_isp.u32IspBaseAddr + ((REG_ISP_SPI_RDATA)<<2)) ++ ++//#define MHEG5_READ(addr) READ_WORD(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2)) ++//#define MHEG5_WRITE(addr, val) WRITE_WORD((_hal_isp.u32Mheg5BaseAddr + (addr << 2)), (val)) ++//#define MHEG5_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32Mheg5BaseAddr + ((addr)<<2), (val), (mask)) ++ ++// PIU_DMA ++#define PIU_READ(addr) READ_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2)) ++#define PIU_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val)) ++#define PIU_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PiuBaseAddr + ((addr)<<2), (val), (mask)) ++ ++//// PM_SLEEP CMD. ++//#define PM_READ(addr) READ_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2)) ++//#define PM_WRITE(addr, val) WRITE_WORD(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val)) ++//#define PM_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++//#define PM_GPIO_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32PMGPIOBaseAddr+ ((addr)<<2), (val), (mask)) ++ ++// CLK_GEN ++//#define CLK_READ(addr) READ_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2)) ++//#define CLK_WRITE(addr, val) WRITE_WORD(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val)) ++//#define CLK_WRITE_MASK(addr, val, mask) WRITE_WORD_MASK(_hal_isp.u32CLK0BaseAddr + ((addr)<<2), (val), (mask)) ++ ++//MS_U32<->MS_U16 ++#define LOU16(u32Val) ((MS_U16)(u32Val)) ++#define HIU16(u32Val) ((MS_U16)((u32Val) >> 16)) ++ ++//serial flash mutex wait time ++#define SERFLASH_MUTEX_WAIT_TIME 3000 ++ ++// Time-out system ++#if !defined (MSOS_TYPE_NOS) && !defined(MSOS_TYPE_LINUX) ++ #define SERFLASH_SAFETY_FACTOR 10 ++ ++ #define SER_FLASH_TIME(_stamp, _msec) { (_stamp) = MsOS_GetSystemTime() + (_msec); } ++ #define SER_FLASH_EXPIRE(_stamp) ( (MsOS_GetSystemTime() > (_stamp)) ? 1 : 0 ) ++ ++#else // defined (MSOS_TYPE_NOS) ++ #define SERFLASH_SAFETY_FACTOR 3000*30 ++ #define SER_FLASH_TIME(_stamp) (do_gettimeofday(&_stamp)) ++ #define SER_FLASH_EXPIRE(_stamp,_msec) (_Hal_GetMsTime(_stamp, _msec)) ++#endif ++ ++#define MAX_READY_WAIT_JIFFIES 40*HZ ++ ++#define CHK_NUM_WAITDONE 2000 ++#define SINGLE_WRITE_LENGTH 4 ++#define SINGLE_READ_LENGTH 8 ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++// MS_U32 u32XiuBaseAddr; // REG_SFSH_XIU_BASE ++// MS_U32 u32Mheg5BaseAddr; ++ MS_U32 u32IspBaseAddr; // REG_ISP_BASE ++ MS_U32 u32FspBaseAddr; // REG_FSP_BASE ++ MS_U32 u32QspiBaseAddr; // REG_QSPI_BASE ++// MS_U32 u32PiuBaseAddr; // REG_PIU_BASE ++// MS_U32 u32PMBaseAddr; // REG_PM_BASE ++// MS_U32 u32CLK0BaseAddr; // REG_PM_BASE ++ MS_U32 u32BdmaBaseAddr; // for supernova.lite ++// MS_U32 u32RiuBaseAddr; ++// MS_U32 u32PMGPIOBaseAddr; ++} hal_isp_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++hal_SERFLASH_t _hal_SERFLASH; ++MS_U8 _u8SERFLASHDbgLevel; ++MS_BOOL _bFSPMode = 0; ++MS_BOOL _bXIUMode = 0; // default XIU mode, set 0 to RIU mode ++MS_BOOL bDetect = FALSE; // initial flasg : true and false ++MS_BOOL _bIBPM = FALSE; // Individual Block Protect mode : true and false ++MS_BOOL _bWPPullHigh = 0; // WP pin pull high or can control info ++MS_BOOL _bHasEAR = FALSE; // Extended Address Register mode supported ++MS_U8 _u8RegEAR = 0xFF; // Extended Address Register value ++MS_U8 u8Mode; ++ ++MS_U32 pu8BDMA_phys = 0; ++MS_U32 pu8BDMA_virt = 0; ++MS_U32 pu8BDMA_bus = 0; ++MS_U32 BASE_FLASH_OFFSET = 0; ++ ++ ++SPI_READ_MODE gReadMode = E_FAST_MODE; ++MS_BOOL gQuadSupport = 0; //extern on MTD ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static MS_S32 _s32SERFLASH_Mutex; ++// ++// Spi Clk Table (List) ++// ++/* ++static MS_U16 _hal_ckg_spi_pm[] = { ++ PM_SPI_CLK_XTALI ++ ,PM_SPI_CLK_54MHZ ++ ,PM_SPI_CLK_86MHZ ++ ,PM_SPI_CLK_108MHZ ++}; ++ ++static MS_U16 _hal_ckg_spi_nonpm[] = { ++ CLK0_CKG_SPI_XTALI ++ ,CLK0_CKG_SPI_54MHZ ++ ,CLK0_CKG_SPI_86MHZ ++ ,CLK0_CKG_SPI_108MHZ ++}; ++*/ ++static hal_isp_t _hal_isp = ++{ ++ //.u32XiuBaseAddr = BASEADDR_XIU, ++ //.u32Mheg5BaseAddr = BASEADDR_RIU + BK_MHEG5, ++ .u32IspBaseAddr = BASE_REG_ISP_ADDR, ++ .u32FspBaseAddr = BASE_REG_FSP_ADDR, ++ .u32QspiBaseAddr = BASE_REG_QSPI_ADDR, ++ //.u32PiuBaseAddr = BASEADDR_RIU + BK_PIU, ++ //.u32PMBaseAddr = BASEADDR_RIU + BK_PMSLP, ++ //.u32CLK0BaseAddr = BASEADDR_NonPMBankRIU + BK_CLK0, ++ .u32BdmaBaseAddr = BASE_REG_BDMACh0_ADDR, ++ // .u32RiuBaseAddr= IO_ADDRESS(MS_BASE_REG_RIU_PA), ++ //.u32PMGPIOBaseAddr=BASEADDR_RIU+BK_PMGPIO, ++}; ++ ++// For linux, thread sync is handled by mtd. So, these functions are empty. ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++//static spinlock_t _gtSpiLock; ++//static MS_U32 _gtSpiFlag; ++/// Suspend type ++/*typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++extern void *high_memory; ++extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);*/ ++void (*_HAL_FSP_Write_Callback_Func)(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++extern MS_BOOL MS_SERFLASH_IN_INTERRUPT (void); ++extern MS_S32 MS_SERFLASH_CREATE_MUTEX ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++extern MS_BOOL MS_SERFLASH_DELETE_MUTEX(MS_S32 s32MutexId); ++extern MS_BOOL MS_SERFLASH_OBTAIN_MUTEX (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++extern MS_BOOL MS_SERFLASH_RELEASE_MUTEX (MS_S32 s32MutexId); ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void); ++static void _HAL_ISP_Enable(void); ++static void _HAL_ISP_Disable(void); ++static void _HAL_ISP_2XMode(MS_BOOL bEnable); ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void); ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void); ++#ifdef CONFIG_RIUISP ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void); ++//static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr,MS_U32 u32Size,MS_U8 * pu8Data); ++#endif ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_EraseChip(void); ++MS_BOOL HAL_FSP_CheckWriteDone(void); ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++ ++void HAL_FSP_Entry(void); ++void HAL_FSP_Exit(void); ++void _HAL_BDMA_INIT(void); ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++//BDMA_Result MDrv_BDMA_CopyHnd(MS_PHYADDR u32SrcAddr, MS_PHYADDR u32DstAddr, MS_U32 u32Len, BDMA_CpyType eCpyType, MS_U8 u8OpCfg) ++//{ ++// return -1; ++//} ++ ++static MS_BOOL _Hal_GetMsTime( struct timeval tPreTime, MS_U32 u32Fac) ++{ ++ MS_U32 u32NsTime = 0; ++ struct timeval time_st; ++ do_gettimeofday(&time_st); ++ u32NsTime = ((time_st.tv_sec - tPreTime.tv_sec) * 1000) + ((time_st.tv_usec - tPreTime.tv_usec)/1000); ++ if(u32NsTime > u32Fac) ++ return TRUE; ++ return FALSE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// check if pm51 on SPI ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : ++//------------------------------------------------------------------------------------------------- ++/*static MS_BOOL _HAL_SERFLASH_Check51RunMode(void) ++{ ++ MS_U8 u8PM51RunMode; ++ u8PM51RunMode = PM_READ(REG_PM_CHK_51MODE); ++ if((u8PM51RunMode & PM_51_ON_SPI)) ++ return FALSE; ++ else ++ return TRUE; ++}*/ ++ ++void HAL_SERFLASH_SelectReadMode(SPI_READ_MODE eReadMode) ++{ ++ switch(eReadMode) ++ { ++ case E_SINGLE_MODE://1-1-1 mode (SPI COMMAND is 0x03) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_FAST_MODE://1-1-1 mode (SPI COMMAND is 0x0B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_ENABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_D_MODE: //1-1-2 mode (SPI COMMAND is 0x3B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_2XREAD_MASK); ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_FAST_DISABLE, SFSH_CHIP_FAST_MASK); ++ break; ++ case E_DUAL_AD_MODE: //1-2-2 mode (SPI COMMAND is 0xBB) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_2XREAD_ENABLE, SFSH_CHIP_2XREAD_MASK); ++ break; ++ case E_QUAD_MODE: //1-1-4 mode (SPI COMMAND is 0x6B) ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE, SFSH_CHIP_4XREAD_ENABLE , SFSH_CHIP_4XREAD_MASK); ++ break; ++ ++ case E_RIUISP_MODE: ++ default: ++ break; ++ } ++ ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Software reset spi_burst ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If no spi reset, it may cause BDMA fail. ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SPI_Rest(void) ++{ ++ // mark for A3 ++ #if 1 ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_RESET, SFSH_CHIP_RESET_MASK); ++ ISP_WRITE_MASK(REG_ISP_CHIP_RST, SFSH_CHIP_NOTRESET, SFSH_CHIP_RESET_MASK); ++ ++ // Call the callback function to switch back the chip selection. ++ if(McuChipSelectCB != NULL ) ++ { ++ (*McuChipSelectCB)(); ++ } ++ #endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Enable ISP engine, the XIU mode does not work ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Enable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0xAAAA); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Disable RIU ISP engine ++// @return TRUE : succeed ++// @return FALSE : fail ++// @note : If Disable ISP engine, the XIU mode works ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_Disable(void) ++{ ++ ISP_WRITE(REG_ISP_PASSWORD, 0x5555); ++ _HAL_SPI_Rest(); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_2XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_ENABLE,SFSH_CHIP_2XREAD_MASK); ++ } ++ else // off 2Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_2XREAD_DISABLE,SFSH_CHIP_2XREAD_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Enable/Disable address and data dual mode (SPI command is 0xBB) ++// @return TRUE : succeed ++// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++static void _HAL_ISP_4XMode(MS_BOOL bEnable) ++{ ++ if(bEnable) // on 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_ENABLE,SFSH_CHIP_4XREAD_MASK); ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_WP_NOT_GPIO, PM_SPI_WP_GPIO_MASK); ++ } ++ else // off 4Xmode ++ { ++ QSPI_WRITE_MASK(REG_ISP_SPI_MODE,SFSH_CHIP_4XREAD_DISABLE,SFSH_CHIP_4XREAD_MASK); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Cmd Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteCmdRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_CMDRDY) & ISP_SPI_WR_CMDRDY_MASK) == ISP_SPI_WR_CMDRDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Cmd Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Write Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_WR_DATARDY) & ISP_SPI_WR_DATARDY_MASK) == ISP_SPI_WR_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Write Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for SPI Read Data Ready ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitReadDataRdy(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ if ( (ISP_READ(REG_ISP_SPI_RD_DATARDY) & ISP_SPI_RD_DATARDY_MASK) == ISP_SPI_RD_DATARDY ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for SPI Read Data Ready fails!\n")); ++ } ++ ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Wait for Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_WaitWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ ++ struct timeval time_st; ++ SER_FLASH_TIME(time_st); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ return FALSE; ++ } ++ ++ do ++ { ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ break; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("Wait for Write to be done fails!\n")); ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ return bRet; ++} ++#ifdef CONFIG_RIUISP ++ ++//------------------------------------------------------------------------------------------------- ++// Check Write/Erase to be done ++// @return TRUE : succeed ++// @return FALSE : fail before timeout ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL _HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_RDSR); // RDSR ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto _HAL_SERFLASH_CheckWriteDone_return; ++ } ++ ++ if ( (ISP_READ(REG_ISP_SPI_RDATA) & SF_SR_WIP_MASK) == 0 ) // WIP = 0 write done ++ { ++ bRet = TRUE; ++ } ++ ++_HAL_SERFLASH_CheckWriteDone_return: ++ ++ return bRet; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Enable/Disable flash HW WP ++/// @param bEnable \b IN: enable or disable HW protection ++//------------------------------------------------------------------------------------------------- ++static void _HAL_SERFLASH_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) ++{ ++ extern void msFlash_ActiveFlash_Set_HW_WP(MS_BOOL bEnable) __attribute__ ((weak)); ++ ++ if (msFlash_ActiveFlash_Set_HW_WP != NULL) ++ { ++ msFlash_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ else ++ { ++ /*if(FlashSetHWWPCB != NULL ) ++ { ++ (*FlashSetHWWPCB)(bEnable); ++ }*/ ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ALERT, printk("msFlash_ActiveFlash_Set_HW_WP() is not defined in this system\n")); ++ // ASSERT(msFlash_ActiveFlash_Set_HW_WP != NULL); ++ } ++ ++ return; ++} ++ ++#if defined (MCU_AEON) ++//Aeon SPI Address is 64K bytes windows ++static MS_BOOL _HAL_SetAeon_SPIMappingAddr(MS_U32 u32addr) ++{ ++ MS_U16 u16MHEGAddr = (MS_U16)((_hal_isp.u32XiuBaseAddr + u32addr) >> 16); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32addr, (int)u16MHEGAddr)); ++ MHEG5_WRITE(REG_SPI_BASE, u16MHEGAddr); ++ ++ return TRUE; ++} ++#endif ++ ++#ifdef CONFIG_RIUISP ++ ++static MS_BOOL _HAL_SERFLASH_RIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ MS_BOOL bRet = FALSE; ++ //MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ // 0x0B fast Read : HW doesn't support now ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Read_return; ++ } ++ ++ *(pu8Data + u32I) = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ } ++ //--- Flush OCP memory -------- ++ // MsOS_FlushMemory(); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_Read_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ ++ ++ return bRet; ++} ++ ++ ++/* ++static MS_BOOL _HAL_SERFLASH_XIURead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U8 *pu8ReadBuf = pu8Data; ++ MS_U32 u32Value, u32AliSize; ++ MS_U32 u32AliAddr, u32RemSize = u32Size; ++ MS_U32 u32pos; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ _HAL_ISP_Enable(); ++ ++ do{ ++ if(_HAL_SERFLASH_WaitWriteDone()) break; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ }while(1); ++ ++ _HAL_ISP_Disable(); ++ ++ // 4-BYTE Aligment for 32 bit CPU Aligment ++ u32AliAddr = (u32Addr & 0xFFFFFFFC); ++ u32pos = u32AliAddr >> 2; ++ ++#if defined (MCU_AEON) ++ //write SPI mapping address ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ //---- Read first data for not aligment address ------ ++ if(u32AliAddr < u32Addr) ++ { ++ u32Value = SFSH_XIU_READ32(u32pos); ++ u32pos++; ++ for(u32I = 0; (u32I < 4) && (u32RemSize > 0); u32I++) ++ { ++ if(u32AliAddr >= u32Addr) ++ { ++ *pu8ReadBuf++ = (MS_U8)(u32Value & 0xFF); ++ u32RemSize--; ++ } ++ u32Value >>= 8; ++ u32AliAddr++; ++ } ++ } ++ //----Read datum for aligment address------ ++ u32AliSize = (u32RemSize & 0xFFFFFFFC); ++ for( u32I = 0; u32I < u32AliSize; u32I += 4) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ ++ // only indirect mode ++ u32Value = SFSH_XIU_READ32(u32pos); ++ ++ *pu8ReadBuf++ = ( u32Value >> 0) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 8) & 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 16)& 0xFF; ++ *pu8ReadBuf++ = ( u32Value >> 24)& 0xFF; ++ ++ u32pos++; ++ u32AliAddr += 4; ++ } ++ ++ //--- Read remain datum -------- ++ if(u32RemSize > u32AliSize) ++ { ++#if defined (MCU_AEON) ++ if((u32AliAddr & 0xFFFF) == 0) ++ _HAL_SetAeon_SPIMappingAddr(u32AliAddr); ++#endif ++ u32Value = SFSH_XIU_READ32(u32pos); ++ } ++ while(u32RemSize > u32AliSize) ++ { ++ *pu8ReadBuf++ = (u32Value & 0xFF); ++ u32Value >>= 8; ++ u32AliSize++; ++ } ++ //--- Flush OCP memory -------- ++ //MsOS_FlushMemory(); ++ ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++#if defined (MCU_AEON) ++ //restore default value ++ _HAL_SetAeon_SPIMappingAddr(0); ++#endif ++ return bRet; ++} ++*/ ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetCKG() ++/// @brief \b Function \b Description: This function is used to set ckg_spi dynamically ++/// @param \b eCkgSpi : enumerate the ckg_spi ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++// // NON-PM Doman ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_OFF,CLK0_CLK_SWITCH_MASK); // run @ 12M ++// ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[0],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[2],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[3],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// ++// default: ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,_hal_ckg_spi_nonpm[1],CLK0_CKG_SPI_MASK); // set ckg_spi ++// break; ++// } ++// ++// ++// CLK_WRITE_MASK(REG_CLK0_CKG_SPI,CLK0_CLK_SWITCH_ON,CLK0_CLK_SWITCH_MASK); // run @ ckg_spi ++// // PM Doman ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_OFF,PM_SPI_CLK_SWITCH_MASK); // run @ 12M ++// switch (eCkgSpi) ++// { ++// case E_SPI_XTALI: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[0],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_54M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_86M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[2],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// case E_SPI_108M: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[3],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// ++// default: ++// PM_WRITE_MASK(REG_PM_CKG_SPI,_hal_ckg_spi_pm[1],PM_SPI_CLK_SEL_MASK); // set ckg_spi ++// break; ++// } ++// PM_WRITE_MASK(REG_PM_CKG_SPI,PM_SPI_CLK_SWITCH_ON,PM_SPI_CLK_SWITCH_MASK); // run @ ckg_spi ++// ++ ++ Ret = TRUE; ++ return Ret; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ClkDiv() ++/// @brief \b Function \b Description: This function is used to set clock div dynamically ++/// @param \b eCkgSpi : enumerate the clk_div ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully , and is restricted to Flash ability ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi) ++{ ++ switch (eClkDivSpi) ++ { ++ case E_SPI_DIV2: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV2); ++ break; ++ case E_SPI_DIV4: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV4); ++ break; ++ case E_SPI_DIV8: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV8); ++ break; ++ case E_SPI_DIV16: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV16); ++ break; ++ case E_SPI_DIV32: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV32); ++ break; ++ case E_SPI_DIV64: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV64); ++ break; ++ case E_SPI_DIV128: ++ ISP_WRITE(REG_ISP_SPI_CLKDIV,ISP_SPI_CLKDIV128); ++ break; ++ case E_SPI_ClkDiv_NOT_SUPPORT: ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ break; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_SetMode() ++/// @brief \b Function \b Description: This function is used to set RIU/XIU dynamically ++/// @param \b bXiuRiu : Enable for XIU (Default) Disable for RIU(Optional) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : XIU is faster than RIU, but is sensitive to ckg. ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ _bXIUMode = bXiuRiu; ++ Ret = TRUE; ++ return Ret; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ if(!bDetect) ++ { ++ HAL_SERFLASH_DetectType(); ++ } ++ MS_ASSERT(_hal_SERFLASH.b2XREAD); // check hw support or not ++ if(_hal_SERFLASH.b2XREAD) ++ { ++ _HAL_ISP_2XMode(b2XMode); ++ } ++ else ++ { ++ //UNUSED(b2XMode); ++ printk("%s This flash does not support 2XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_Set2XREAD() ++/// @brief \b Function \b Description: This function is used to set 2XREAD dynamically ++/// @param \b b2XMode : ENABLE for 2XREAD DISABLE for NORMAL ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++/// @param \b : Please use this function carefully, and needs Flash support ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT(_hal_SERFLASH.b4XREAD); // check hw support or not ++ printk("[SerFlash]TODO: correct Quad mode GPIO\n"); ++ //PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++ if(_hal_SERFLASH.b4XREAD) ++ { ++ _HAL_ISP_4XMode(b4XMode); ++ } ++ else ++ { ++ //UNUSED(b4XMode); ++ printk("%s This flash does not support 4XREAD!!!\n", __FUNCTION__); ++ } ++ ++ return TRUE; ++} ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_SERFLASH_ChipSelect() ++/// @brief \b Function \b Description: set active flash among multi-spi flashes ++/// @param \b u8FlashIndex : flash index (0 or 1) ++/// @param \b NONE : ++/// @param \b TRUE: Success FALSE: Fail ++/// @param \b NONE : ++//////////////////////////////////////////////////////////////////////////////// ++MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex) ++{ ++ MS_BOOL Ret = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u8FlashIndex)); ++ switch (u8FlashIndex) ++ { ++ case FLASH_ID0: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT1,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID1: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT2,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID2: ++ QSPI_WRITE_MASK(REG_ISP_SPI_CHIP_SELE,SFSH_CHIP_SELE_EXT3,SFSH_CHIP_SELE_MASK); ++ Ret = TRUE; ++ break; ++ case FLASH_ID3: ++ //UNUSED(u8FlashIndex); //Reserved ++ default: ++ //UNUSED(u8FlashIndex); //Invalid flash ID ++ Ret = FALSE; ++ break; ++ } ++ WAIT_SFSH_CS_STAT(); // wait for chip select done ++ return Ret; ++} ++ ++void HAL_SERFLASH_Config(void) ++{ ++#if 0 ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32PMRegBaseAddr, (int)u32NonPMRegBaseAddr, (int)u32XiuBaseAddr)); ++ _hal_isp.u32XiuBaseAddr = u32XiuBaseAddr; ++ _hal_isp.u32Mheg5BaseAddr = u32NonPMRegBaseAddr + BK_MHEG5; ++ _hal_isp.u32IspBaseAddr = u32PMRegBaseAddr + BK_ISP; ++ _hal_isp.u32FspBaseAddr = u32PMRegBaseAddr + BK_FSP; ++ _hal_isp.u32QspiBaseAddr = u32PMRegBaseAddr + BK_QSPI; ++ _hal_isp.u32PiuBaseAddr = u32PMRegBaseAddr + BK_PIU; ++ _hal_isp.u32PMBaseAddr = u32PMRegBaseAddr + BK_PMSLP; ++ _hal_isp.u32CLK0BaseAddr = u32NonPMRegBaseAddr + BK_CLK0; ++ _hal_isp.u32RiuBaseAddr = u32PMRegBaseAddr; ++#endif ++ ++} ++ ++ ++void HAL_SERFLASH_Init(void) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ _s32SERFLASH_Mutex = MS_SERFLASH_CREATE_MUTEX(E_MSOS_FIFO, "Mutex SERFLASH", MSOS_PROCESS_SHARED); ++ MS_ASSERT(_s32SERFLASH_Mutex >= 0); ++#ifdef CONFIG_RIUISP ++ ++#ifdef MCU_AEON ++ ISP_WRITE(REG_ISP_SPI_CLKDIV, 1<<2); // cpu clock / div4 ++#else// MCU_MIPS @ 720 Mhz for T8 ++ /* output clk=mcu_clk/SPI_DIV */ ++ //set mcu_clk to 110Mhz ++ //WRITE_WORD_MASK(GET_REG_ADDR(BASE_REG_CHIPTOP_ADDR, 0x22),BITS(11:10, 2),BMASK(11:10)); // set ckg_spi ++ HAL_SERFLASH_ClkDiv(E_SPI_DIV8); ++#endif ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, 0x0); //mark for A3 ++ ISP_WRITE(REG_ISP_SPI_ENDIAN, ISP_SPI_ENDIAN_SEL); ++#else ++ /* spi_clk determind FSP and BDMA output frequency */ ++ /* it's set at IPL stage or clk platform default, so don't set at this time*/ ++ // set spi_clk ++ //HAL_SERFLASH_SetCKG(E_SPI_54M); ++ ++ _HAL_ISP_Disable(); ++ ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_DESEL_TWO, SFSH_CS_DESEL_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_SETUP_TWO , SFSH_CS_SETUP_MASK); ++ QSPI_WRITE_MASK(REG_SPI_CS_TIME, SFSH_CS_HOLD_TWO , SFSH_CS_HOLD_MASK); ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++#endif ++} ++ ++void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch) ++{ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_NOTICE, printk("%s() Chicago TODO\n", __FUNCTION__)); ++ ++ ++// MS_U32 u32PmGPIObase = _hal_isp.u32PMBaseAddr + 0x200; ++// ++// if(bSwitch)// The PAD of the SPI set as GPIO IN. ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_IS_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_IS_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++// else ++// { ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_NOT_GPIO, PM_SPI_GPIO_MASK); ++// PM_WRITE_MASK(REG_PM_SPI_IS_GPIO, PM_SPI_HOLD_NOT_GPIO, PM_SPI_HOLD_GPIO_MASK); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICZ_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPICK_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDI_OEN)<<2))|(BIT(0)))); ++// WRITE_BYTE( u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2), (READ_BYTE(u32PmGPIObase + ((REG_PM_GPIO_SPIDO_OEN)<<2))|(BIT(0)))); ++// } ++ ++} ++extern hal_SERFLASH_t _hal_SERFLASH_table[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L6445E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_MX25L12845E[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_GD25Q32_CMP1[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_S25FL032K_CMP1[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_W25Q64CV_CMP1[]; ++extern ST_WRITE_PROTECT _pstWriteProtectTable_W25Q32BV_CMP1[]; ++ ++ ++MS_BOOL HAL_SERFLASH_DetectType(void) ++{ ++ #define READ_ID_SIZE 3 ++ #define READ_REMS4_SIZE 2 ++ ++ MS_U8 u8FlashId[READ_ID_SIZE]; ++ MS_U8 u8FlashREMS4[READ_REMS4_SIZE]; ++ MS_U32 u32Index; ++ MS_U8 u8Status0, u8Status1; ++ ++ memset(&_hal_SERFLASH, 0, sizeof(_hal_SERFLASH)); ++ ++ if (HAL_SERFLASH_ReadID(u8FlashId, sizeof(u8FlashId))== TRUE) ++ { ++ if(u8FlashId[0]==0xFF && u8FlashId[1]==0xFF && u8FlashId[2]==0xFF) ++ { ++ bDetect = FALSE; ++ return bDetect; ++ } ++ ++ /* find current serial flash */ ++ for (u32Index = 0; _hal_SERFLASH_table[u32Index].u8MID != 0; u32Index++) ++ { ++ ++ if ( (_hal_SERFLASH_table[u32Index].u8MID == u8FlashId[0]) ++ && (_hal_SERFLASH_table[u32Index].u8DID0 == u8FlashId[1]) ++ && (_hal_SERFLASH_table[u32Index].u8DID1 == u8FlashId[2]) ++ ) ++ { ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[u32Index]), sizeof(_hal_SERFLASH)); ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L6405D||_hal_SERFLASH.u16FlashType == FLASH_IC_MX25L12805D) ++ { ++ if (HAL_SERFLASH_ReadREMS4(u8FlashREMS4,READ_REMS4_SIZE)== TRUE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] MXIC REMS: 0x%02X,0x%02X\n", u8FlashREMS4[0], u8FlashREMS4[1]) ); ++ ++ // patch : MXIC 6405D vs 6445E(MXIC 12805D vs 12845E) ++ if( u8FlashREMS4[0] == 0xC2) ++ { ++ if( u8FlashREMS4[1] == 0x16) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L6445E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L6445E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ if( u8FlashREMS4[1] == 0x17) ++ { ++ _hal_SERFLASH.u16FlashType = FLASH_IC_MX25L12845E; ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_MX25L12845E; ++ _hal_SERFLASH.u16SPIMaxClk[1] = E_QUAD_MODE; ++ } ++ ++ } ++ } ++ } ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Flash is detected (0x%04X, 0x%02X, 0x%02X, 0x%02X) ver1.1\n", ++ _hal_SERFLASH.u16FlashType, ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1 ++ ) ++ ); ++ bDetect = TRUE; ++ break; ++ } ++ else ++ { ++ continue; ++ } ++ } ++ ++ // printf("[%x]\n",_hal_SERFLASH.u16FlashType); ++ // customization for GigaDevice ++ ++ if( _hal_SERFLASH.u8MID == MID_GD ) ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_GD25Q32_CMP1; ++ } ++ ++ if( _hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K ) ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_S25FL032K_CMP1; ++ } ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_W25Q64CV_CMP1; ++ } ++ ++ if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV) ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ ++ _hal_SERFLASH.u8WrsrBlkProtect = BITS(6:2, 0x00); ++ _hal_SERFLASH.pWriteProtectTable = _pstWriteProtectTable_W25Q32BV_CMP1; ++ } ++ if(_hal_SERFLASH.u32FlashSize >= 0x2000000) ++ { ++ if((_hal_SERFLASH.u8MID == MID_MXIC)||(_hal_SERFLASH.u8MID == MID_GD)) ++ { ++ _bHasEAR = TRUE; // support EAR mode ++ } ++ } ++ ++ // If the Board uses a unknown flash type, force setting a secure flash type for booting. //FLASH_IC_MX25L6405D ++ if( bDetect != TRUE ) ++ { ++ #if 1 ++ memcpy(&_hal_SERFLASH, &(_hal_SERFLASH_table[0]), sizeof(_hal_SERFLASH)); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("[FSP] Unknown flash type (0x%02X, 0x%02X, 0x%02X) and use default flash type 0x%04X\n", ++ _hal_SERFLASH.u8MID, ++ _hal_SERFLASH.u8DID0, ++ _hal_SERFLASH.u8DID1, ++ _hal_SERFLASH.u16FlashType ++ ) ++ ); ++ #else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, ++ printk("Unsupport flash type (0x%02X, 0x%02X, 0x%02X), please add flash info to serial flash driver\n", ++ u8FlashId[0], ++ u8FlashId[1], ++ u8FlashId[2] ++ ) ++ ); ++ MS_ASSERT(0); ++ #endif ++ bDetect = TRUE; ++ } ++ ++ } ++ ++ ++#ifdef CONFIG_RIUISP ++ ++ ISP_WRITE(REG_ISP_DEV_SEL, ISP_DEV_SEL); ++ ++#else ++ ++ //check norflaash support to 4Xmode or 2xmode ++ if( _hal_SERFLASH.u16SPIMaxClk[1]==E_QUAD_MODE && gQuadSupport==0 ) ++ gReadMode = E_DUAL_D_MODE; ++ else ++ gReadMode = _hal_SERFLASH.u16SPIMaxClk[1]; ++ ++ HAL_SERFLASH_SetCKG(_hal_SERFLASH.u16SPIMaxClk[0]); ++ ++ ++ switch ( gReadMode ) ++ { ++ case E_SINGLE_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 READ NORMAL MODE\n")); ++ break; ++ case E_FAST_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-1 FAST_READ MODE\n")); ++ break; ++ case E_DUAL_D_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-2 DUAL_FAST_READ MODE\n")); ++ break; ++ case E_DUAL_AD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-2-2 2xIO_READ MODE\n")); ++ break; ++ case E_QUAD_MODE: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_INFO, printk("[FSP] 1-1-4 QUAD_READ MODE\n")); ++ HAL_QUAD_Enable(1); ++ break; ++ default: ++ break; ++ } ++ ++#endif ++ ++ ++ return bDetect; ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ do{ ++ ++ *u32FlashSize = _hal_SERFLASH.u32FlashSize; ++ Ret = TRUE; ++ ++ }while(0); ++ ++ return Ret; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_EraseChip(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_EraseChip_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_CE); // CHIP_ERASE ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_EraseChip_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()\n", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_EraseChip(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex) ++{ ++ MS_U32 u32NextAddr; ++ MS_BOOL bRet = FALSE; ++ ++ if (_hal_SERFLASH.pSpecialBlocks == NULL) ++ { ++ *pu32BlockIndex = u32FlashAddr / SERFLASH_SECTOR_SIZE; ++ ++ bRet = TRUE; ++ } ++ else ++ { ++ // TODO: review, optimize this flow ++ for (u32NextAddr = 0, *pu32BlockIndex = 0; *pu32BlockIndex < NUMBER_OF_SERFLASH_SECTORS; (*pu32BlockIndex)++) ++ { ++ // outside the special block ++ if ( *pu32BlockIndex < _hal_SERFLASH.pSpecialBlocks->u16Start ++ || *pu32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End ++ ) ++ { ++ u32NextAddr += SERFLASH_SECTOR_SIZE; // i.e. normal block size ++ } ++ // inside the special block ++ else ++ { ++ u32NextAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[*pu32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32NextAddr > u32FlashAddr) ++ { ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr) ++{ ++ if ( _hal_SERFLASH.pSpecialBlocks == NULL ++ || u32BlockIndex <= _hal_SERFLASH.pSpecialBlocks->u16Start ++ ) ++ { ++ *pu32FlashAddr = u32BlockIndex * SERFLASH_SECTOR_SIZE; ++ } ++ else ++ { ++ MS_U32 u32Index; ++ ++ *pu32FlashAddr = _hal_SERFLASH.pSpecialBlocks->u16Start * SERFLASH_SECTOR_SIZE; ++ ++ for (u32Index = _hal_SERFLASH.pSpecialBlocks->u16Start; ++ u32Index < u32BlockIndex && u32Index <= _hal_SERFLASH.pSpecialBlocks->u16End; ++ u32Index++ ++ ) ++ { ++ *pu32FlashAddr += _hal_SERFLASH.pSpecialBlocks->au32SizeList[u32Index - _hal_SERFLASH.pSpecialBlocks->u16Start]; ++ } ++ ++ if (u32BlockIndex > _hal_SERFLASH.pSpecialBlocks->u16End + 1) ++ { ++ *pu32FlashAddr += (u32BlockIndex - _hal_SERFLASH.pSpecialBlocks->u16End - 1) * SERFLASH_SECTOR_SIZE; ++ } ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ if( u32StartBlock > u32EndBlock || u32EndBlock >= _hal_SERFLASH.u32NumSec ) ++ { ++ printk("%s (0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32StartBlock, (int)u32EndBlock, bWait); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_64BE); // BLOCK_ERASE ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if (HAL_SERFLASH_BlockToAddress(u32I, &u32FlashAddr) == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if(bWait == TRUE ) ++ { ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ printk("%s : Wait Write Done Fail!!!\n", __FUNCTION__ ); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ } ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ return HAL_FSP_BlockErase(u32StartBlock, u32EndBlock, bWait); ++#endif ++} ++ ++MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s ENTRY fails!\n", __FUNCTION__)); ++ return bRet; ++ } ++ ++ if( u32SectorAddress > _hal_SERFLASH.u32FlashSize ) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s (0x%08X)\n", __FUNCTION__, (int)u32SectorAddress)); ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SE); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32SectorAddress) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_BlockErase_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_BlockErase_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++#else ++ bRet = HAL_FSP_SectorErase(u32SectorAddress,FLASH_ERASE_04K); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_CheckWriteDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_CheckWriteDone(); ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() = %d\n", __FUNCTION__, bRet)); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_CheckWriteDone(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U16 u16I, u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ MS_BOOL b2XREAD = FALSE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ b2XREAD = (BIT(2) & ISP_READ(REG_ISP_SPI_MODE))? 1 : 0; ++ _HAL_ISP_2XMode(DISABLE); ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ if( u32Size > SERFLASH_PAGE_SIZE) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE; //write SERFLASH_PAGE_SIZE bytes one time ++ } ++ else ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ ISP_WRITE(REG_ISP_SPI_ADDR_L, LOU16(u32Addr)); ++ ISP_WRITE(REG_ISP_SPI_ADDR_H, (MS_U8)HIU16(u32Addr)); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_PP); // PAGE_PROG ++ ++ // Improve flash write speed ++ if(u16WriteBytes == 256) ++ { ++ // Write 256 bytes to flash ++ MS_U8 u8Index = 0; ++ ++ do{ ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u8Index));//SPI_WRITE_DATA( *(u8Buf + u8Index) ); ++ ++ u8Index++; ++ ++ if( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ ++ }while(u8Index != 0); ++ } ++ else ++ { ++ ++ for ( u16I = 0; u16I < u16WriteBytes; u16I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)*(u8Buf + u16I));//SPI_WRITE_DATA( *(u8Buf + u16I) ); ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ ++HAL_SERFLASH_Write_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ // restore the 2x READ setting. ++ HAL_SERFLASH_SelectReadMode(_hal_SERFLASH.u16SPIMaxClk[1]); ++ ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ #if defined(CONFIG_FSP_WRITE_RIUOP) ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ #elif defined(CONFIG_FSP_WRITE_BDMA) ++ HAL_FSP_Entry(); ++ bRet = HAL_FSP_Write_BDMA(u32Addr, u32Size, pu8Data); ++ HAL_FSP_Exit(); ++ ++ #else ++ #error "FSP write" ++ #endif ++ ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL Ret = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++#ifdef CONFIG_RIUISP ++ /*if( _bXIUMode ) ++ { ++ Ret = _HAL_SERFLASH_XIURead( u32Addr, u32Size, pu8Data); ++ } ++ else// RIU mode*/ ++ { ++ Ret = _HAL_SERFLASH_RIURead( u32Addr, u32Size, pu8Data); ++ } ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ ++ HAL_SERFLASH_SelectReadMode(gReadMode); ++ ++ #ifdef CONFIG_FSP_READ_DIRERECT ++ if(!BASE_FLASH_OFFSET) ++ { ++ BASE_FLASH_OFFSET = (MS_U32)ioremap(MS_SPI_ADDR, 0x2000000); ++ //printk("[SER flash]MS_SPI_ADDR=(0x%08X)\n",(int)BASE_FLASH_OFFSET); ++ } ++ if(BASE_FLASH_OFFSET) ++ { ++ MS_U32 u32ReadSize = 0; ++ if (u32Addr < 0x1000000) ++ { ++ if (_u8RegEAR) // switch back to bottom 16MB ++ HAL_FSP_WriteExtAddrReg(0); ++ u32ReadSize = u32Size > (0x1000000 - u32Addr) ? (0x1000000 - u32Addr) : u32Size; ++ memcpy((void *)pu8Data, (const void *)(BASE_FLASH_OFFSET+u32Addr), u32ReadSize); ++ u32Size = u32Size - u32ReadSize; ++ } ++ if (u32Size) ++ { ++ MS_U8 u8EAR = 0; ++ ++ u32Addr += u32ReadSize; ++ u8EAR = u32Addr >> 24; ++ if (u8EAR) ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ memcpy((void *)pu8Data+u32ReadSize,(const void *)(BASE_FLASH_OFFSET+(u32Addr&0xFFFFFF)), u32Size); ++ } ++ } ++ Ret = TRUE; ++ #elif defined(CONFIG_FSP_READ_RIUOP) ++ Ret = HAL_FSP_Read(u32Addr, u32Size, pu8Data); ++ #else ++ #error "FPS READ" ++ #endif ++ ++#endif ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return Ret; ++} ++EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits) ++{ ++ ST_WRITE_PROTECT *pWriteProtectTable; ++ MS_U8 u8Index; ++ MS_BOOL bPartialBoundFitted; ++ MS_BOOL bEndOfTable; ++ MS_U32 u32PartialFittedLowerBound = u32UpperBound; ++ MS_U32 u32PartialFittedUpperBound = u32LowerBound; ++ ++ ++ if (NULL == _hal_SERFLASH.pWriteProtectTable) ++ { ++ return WP_TABLE_NOT_SUPPORT; ++ } ++ ++ ++ for (u8Index = 0, bEndOfTable = FALSE, bPartialBoundFitted = FALSE; FALSE == bEndOfTable; u8Index++) ++ { ++ pWriteProtectTable = &(_hal_SERFLASH.pWriteProtectTable[u8Index]); ++ ++ if ( 0xFFFFFFFF == pWriteProtectTable->u32LowerBound ++ && 0xFFFFFFFF == pWriteProtectTable->u32UpperBound ++ ) ++ { ++ bEndOfTable = TRUE; ++ } ++ ++ if ( pWriteProtectTable->u32LowerBound == u32LowerBound ++ && pWriteProtectTable->u32UpperBound == u32UpperBound ++ ) ++ { ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ ++ return WP_AREA_EXACTLY_AVAILABLE; ++ } ++ else if (u32LowerBound <= pWriteProtectTable->u32LowerBound && pWriteProtectTable->u32UpperBound <= u32UpperBound) ++ { ++ // ++ // u32PartialFittedUpperBound & u32PartialFittedLowerBound would be initialized first time when bPartialBoundFitted == FALSE (init value) ++ // 1. first match: FALSE == bPartialBoundFitted ++ // 2. better match: (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ // ++ ++ if ( FALSE == bPartialBoundFitted ++ || (pWriteProtectTable->u32UpperBound - pWriteProtectTable->u32LowerBound) > (u32PartialFittedUpperBound - u32PartialFittedLowerBound) ++ ) ++ { ++ u32PartialFittedUpperBound = pWriteProtectTable->u32UpperBound; ++ u32PartialFittedLowerBound = pWriteProtectTable->u32LowerBound; ++ *pu8BlockProtectBits = pWriteProtectTable->u8BlockProtectBits; ++ } ++ ++ bPartialBoundFitted = TRUE; ++ } ++ } ++ ++ if (TRUE == bPartialBoundFitted) ++ { ++ return WP_AREA_PARTIALLY_AVAILABLE; ++ } ++ else ++ { ++ return WP_AREA_NOT_AVAILABLE; ++ } ++} ++ ++ ++MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ udelay(bEnableAllArea ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (TRUE == bEnableAllArea) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, u8BlockProtectBits); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ // programming sector protection ++ { ++ int i; ++ MS_U32 u32FlashAddr; ++ ++ // search write protect table ++ for (i = 0; ++ 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32LowerBound && 0xFFFFFFFF != _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound; // the end of write protect table ++ i++ ++ ) ++ { ++ // if found, write ++ if (u8BlockProtectBits == _hal_SERFLASH.pWriteProtectTable[i].u8BlockProtectBits) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("u8BlockProtectBits = 0x%X, u32LowerBound = 0x%X, u32UpperBound = 0x%X\n", ++ (unsigned int)u8BlockProtectBits, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound, ++ (unsigned int)_hal_SERFLASH.pWriteProtectTable[i].u32UpperBound ++ ) ++ ); ++ for (u32FlashAddr = 0; u32FlashAddr < _hal_SERFLASH.u32FlashSize; u32FlashAddr += _hal_SERFLASH.u32SecSize) ++ { ++ if (_hal_SERFLASH.pWriteProtectTable[i].u32LowerBound <= (u32FlashAddr + _hal_SERFLASH.u32SecSize - 1) && ++ u32FlashAddr <= _hal_SERFLASH.pWriteProtectTable[i].u32UpperBound) ++ { ++ continue; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x39); // unprotect sector ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (u32FlashAddr >> 16) & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ((MS_U16)u32FlashAddr) >> 8); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, u32FlashAddr & 0xFF); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ } ++ break; ++ } ++ } ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_Flash_WriteProtect_Area_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | u8BlockProtectBits); // [4:2] or [5:2] protect blocks ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_Flash_WriteProtect_Area_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnableAllArea)// _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d, 0x%02X)\n", __FUNCTION__, bEnableAllArea, u8BlockProtectBits)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ //MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect_Area(bEnableAllArea, u8BlockProtectBits); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/*spasion flash DYB unlock*/ ++ ++MS_BOOL HAL_SERFLASH_SPSNDYB_UNLOCK(MS_U32 u32StartBlock, MS_U32 u32EndBlock) ++{ ++//u32StartBlock, u32EndBlock --> 0~285 ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32I; ++ MS_U32 u32FlashAddr = 0; ++ MS_U8 dybStatusReg=0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG,printk("%s ENTRY \n", __FUNCTION__)); ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //MsOS_DelayTask(20); // when disable WP, delay more time ++ udelay(20); ++ _HAL_ISP_Enable(); ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ for( u32I = u32StartBlock; u32I <= u32EndBlock; u32I++) ++ { ++ bRet = FALSE; ++ dybStatusReg=0; ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE1); // DYB write ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ if(u32I<=31) ++ u32FlashAddr = u32I * 4096; ++ else ++ u32FlashAddr = (u32I -30) * 64 * 1024; ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF);//0xFF --> unlock; 0x00-->lock ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); ++ //read DYB status register to check the result ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xE0); // DYB read ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr)>>8); //MSB , 4th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, HIU16(u32FlashAddr) & 0xFF);//3th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) >> 8);//2th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, LOU16(u32FlashAddr) & 0xFF);//1th byte ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ ++ dybStatusReg = (MS_U8)ISP_READ(REG_ISP_SPI_RDATA);//SPI_READ_DATA(); ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x5555); // disable trigger mode ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ if(dybStatusReg != 0xFF ) ++ { ++ bRet = FALSE; ++ goto HAL_SPSNFLASH_DYB_UNLOCK_return; ++ } ++ else ++ bRet = TRUE; ++ } ++ ++HAL_SPSNFLASH_DYB_UNLOCK_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ _HAL_ISP_Disable(); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable) ++{ ++// Note: Temporarily don't call this function until MSTV_Tool ready ++ MS_BOOL bRet = FALSE; ++ ++#ifdef CONFIG_RIUISP ++ ++ MS_U8 u8Status0, u8Status1; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(DISABLE); ++ //udelay(bEnable ? 5 : 20); //mark for A3 ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if (bEnable) ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SERFLASH_WRSR_BLK_PROTECT); // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT); // SF_SR_SRWD: SRWD Status Register Write Protect ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ ++ } ++ else ++ { ++ if (_hal_SERFLASH.u8MID == MID_ATMEL) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0 << 2); // [4:2] or [5:2] protect blocks // SPRL 1 -> 0 ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WRSR); // WRSR ++ } ++ ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(6:2, 0x1F)); // [6:2] protect blocks ++ ++ if ( _HAL_SERFLASH_WaitWriteDone() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x40); ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, SF_SR_SRWD); // [4:2] or [5:2] protect blocks ++ } ++ ++ } ++ ++ bRet = _HAL_SERFLASH_WaitWriteDone(); ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ if ((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV))//MSB S8-S15 ++ { ++ HAL_SERFLASH_ReadStatusReg(&u8Status0); ++ HAL_SERFLASH_ReadStatusReg2(&u8Status1); ++ HAL_SERFLASH_WriteStatusReg(((u8Status1 << 8)|u8Status0|0x4000));//CMP = 1 ++ udelay(40); ++ } ++ ++ if (bEnable) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++#else ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ MS_ASSERT( MS_SERFLASH_IN_INTERRUPT() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteProtect(bEnable); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ // HW doesn't support ReadID on MX/ST flash; use trigger mode instead. ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ MS_U32 u32I; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDID); // RDID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ for ( u32I = 0; u32I < u32Size; u32I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadID_return; ++ } ++ ++ u8ptr[u32I] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32I])); ++ } ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_ReadID_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ++ bRet = HAL_FSP_ReadID(pu8Data, u32Size); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_U64 HAL_SERFLASH_ReadUID(void) ++{ ++ #define READ_UID_SIZE 8 ++ MS_U8 u8I = 0; ++ MS_U8 u8ptr[READ_UID_SIZE]; ++ MS_U8 u8Size = READ_UID_SIZE; ++ ++ MS_U64 u64FlashUId = 0; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if(!_HAL_SERFLASH_WaitWriteDone()) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ // SFSH_RIU_REG16(REG_SFSH_SPI_COMMAND) = ISP_SPI_CMD_RDID; // RDID ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // enable trigger mode ++ ++ if(_hal_SERFLASH.u16FlashType == FLASH_IC_EN25QH16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x5A); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0; u8I < 2; u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x80); //start address ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ else if( _hal_SERFLASH.u16FlashType == FLASH_IC_W25Q16) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x4B); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ for(u8I = 0;u8I < 4;u8I++) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0xFF); // RDUID ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ } ++ } ++ else ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_READ); // READ ++ ++ for ( u8I = 0; u8I < u8Size; u8I++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_READUID_RETURN; ++ } ++ ++ u8ptr[u8I] = ISP_READ(REG_ISP_SPI_RDATA); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s, %d 0x%02X\n",__FUNCTION__, u8I, u8ptr[u8I])); ++ } ++ ++ for(u8I = 0;u8I < 8;u8I++) ++ { ++ u64FlashUId <<= 8; ++ u64FlashUId += u8ptr[u8I]; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ ++HAL_SERFLASH_READUID_RETURN: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++ ++ return u64FlashUId; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++#ifdef CONFIG_RIUISP ++ MS_BOOL bRet = FALSE; ++ ++ MS_U32 u32Index; ++ MS_U8 *u8ptr = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteCmdRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_REMS4); // READ_REMS4 for new MXIC Flash ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_WDATA_DUMMY); ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, 0x00); // if ADD is 0x00, MID first. if ADD is 0x01, DID first ++ if ( _HAL_SERFLASH_WaitWriteDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ for ( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ { ++ ISP_WRITE(REG_ISP_SPI_RDREQ, ISP_SPI_RDREQ); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadREMS4_return; ++ } ++ ++ u8ptr[u32Index] = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", u8ptr[u32Index])); ++ } ++ ++ bRet = TRUE; ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++HAL_SERFLASH_ReadREMS4_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++#else ++ return HAL_FSP_ReadREMS4(pu8Data, u32Size); ++#endif ++ ++ ++} ++ ++MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRAMStart, MS_U32 u32Size) ++{ ++ ++ ++ MS_BOOL bRet = FALSE; ++#if 0 ++ MS_U32 u32Timer; ++ ++ MS_U32 u32Timeout = SERFLASH_SAFETY_FACTOR*u32Size/(108*1000/4/8); ++ ++ u32Timeout=u32Timeout; //to make compiler happy ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, 0x%08X, %d)\n", __FUNCTION__, (int)u32FlashStart, (int)u32DRAMStart, (int)u32Size)); ++ ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ #if 0 // TODO: review ++ if (MDrv_SYS_GetChipRev() == 0x00) ++ { ++ // DMA program can't run on DRAM, but in flash ONLY ++ return FALSE; ++ } ++ #endif // TODO: review ++ // [URANUS_REV_A][OBSOLETE] // TODO: <-@@@ CHIP SPECIFIC ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ ISP_WRITE_MASK(REG_ISP_CHIP_SEL, SFSH_CHIP_SEL_RIU, SFSH_CHIP_SEL_MODE_SEL_MASK); // For DMA only ++ ++ _HAL_ISP_Disable(); ++ ++ // SFSH_RIU_REG16(REG_SFSH_SPI_CLK_DIV) = 0x02; // 108MHz div3 (max. 50MHz for this ST flash) for FAST_READ ++ ++ PIU_WRITE(REG_PIU_DMA_SIZE_L, LOU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_SIZE_H, HIU16(u32Size)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_L, LOU16(u32DRAMStart)); ++ PIU_WRITE(REG_PIU_DMA_DRAMSTART_H, HIU16(u32DRAMStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_L, LOU16(u32FlashStart)); ++ PIU_WRITE(REG_PIU_DMA_SPISTART_H, HIU16(u32FlashStart)); ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) = 0 << 5; // 0: little-endian 1: big-endian ++ // SFSH_PIU_REG16(REG_SFSH_DMA_CMD) |= 1; // trigger ++ PIU_WRITE(REG_PIU_DMA_CMD, PIU_DMA_CMD_LE | PIU_DMA_CMD_FIRE); // trigger ++ ++ // Wait for DMA to be done ++ SER_FLASH_TIME(u32Timer); ++ do ++ { ++ if ( (PIU_READ(REG_PIU_DMA_STATUS) & PIU_DMA_DONE_MASK) == PIU_DMA_DONE ) // finished ++ { ++ bRet = TRUE; ++ break; ++ } ++ } while (!SER_FLASH_EXPIRE(u32Timer,u32Timeout)); ++ ++ if (bRet == FALSE) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("DMA timeout!\n")); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0xFF; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR); // RDSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_ReadStatusReg(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ *pu8StatusReg = 0x00; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSR2); // RDSR2 ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_ReadStatusReg_return; ++ } ++ ++ *pu8StatusReg = ISP_READ(REG_ISP_SPI_RDATA); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk(" 0x%02X", *pu8StatusReg)); ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_ReadStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ // MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ bRet = HAL_FSP_ReadStatusReg2(pu8StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = FALSE; ++#ifdef CONFIG_RIUISP ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WRSR); // WRSR ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg & 0xFF )); // LSB ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ ++ if((_hal_SERFLASH.u8MID == MID_GD) || (_hal_SERFLASH.u16FlashType == FLASH_IC_S25FL032K) ++ ||(_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q64CV) || (_hal_SERFLASH.u16FlashType == FLASH_IC_W25Q32BV)) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, (MS_U8)(u16StatusReg >> 8 )); // MSB ++ //printf("write_StatusReg=[%x]\n",u16StatusReg); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteStatusReg_return; ++ } ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteStatusReg_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("\n")); ++#else ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ bRet = HAL_FSP_WriteStatusReg(u16StatusReg); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++#endif ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_EnterIBPM(void) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_WPSEL); // WPSEL ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDSCUR); // Read Security Register ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_EnableIBPM_return; ++ } ++ ++ if((ISP_READ(REG_ISP_SPI_RDATA) & BIT(7)) == BIT(7)) ++ { ++ bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, ++ printk("MXIC Security Register 0x%02X\n", ISP_READ(REG_ISP_SPI_RDATA))); ++ } ++ ++HAL_SPI_EnableIBPM_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return bRet; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBLK); // Single Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_SBULK); // Single Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++#if defined (MS_DEBUG) ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_SingleBlockLock_return; ++ } ++ ++ if( bLock ) ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0xFF ) ++ bRet = TRUE; ++ } ++ else ++ { ++ if( ISP_READ(REG_ISP_SPI_RDATA) == 0x00 ) ++ bRet = TRUE; ++ } ++#else//No Ceck ++ bRet = TRUE; ++#endif ++ ++HAL_SPI_SingleBlockLock_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bLock)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ return bRet; ++ } ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ udelay(bLock ? 5 : 20); // when disable WP, delay more time ++ ++ _HAL_ISP_Enable(); ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_COMMAND, ISP_SPI_CMD_WREN); // WREN ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ if( bLock ) ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBLK); // Gang Block Lock Protection ++ } ++ else ++ { ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_GBULK); // Gang Block unLock Protection ++ } ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SERFLASH_WriteProtect_return; ++ } ++ ++ bRet = TRUE; ++ ++HAL_SERFLASH_WriteProtect_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ if (bLock) // _REVIEW_ ++ { ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bLock); ++ } ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++} ++ ++MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr) ++{ ++ MS_U8 u8Val = 0xA5; ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return u8Val; ++ } ++ ++ if ( _bIBPM != TRUE ) ++ { ++ printk("%s not in Individual Block Protect Mode\n", __FUNCTION__); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ return u8Val; ++ } ++ ++ _HAL_ISP_Enable(); ++ ++ if ( !_HAL_SERFLASH_WaitWriteDone() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ if ( _HAL_SERFLASH_WaitWriteCmdRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x3333); // Enable trigger mode ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, ISP_SPI_CMD_RDBLOCK); // Read Block Lock Status ++ ++ if ( !_HAL_SERFLASH_WaitWriteDataRdy() ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x10)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x08)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_WDATA, BITS(7:0, ((u32FlashAddr >> 0x00)&0xFF))); ++ if(!_HAL_SERFLASH_WaitWriteDataRdy()) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ ISP_WRITE(REG_ISP_SPI_RDREQ, 0x01); // SPI read request ++ ++ if ( _HAL_SERFLASH_WaitReadDataRdy() == FALSE ) ++ { ++ goto HAL_SPI_ReadBlockStatus_return; ++ } ++ ++ u8Val = ISP_READ(REG_ISP_SPI_RDATA); ++ ++HAL_SPI_ReadBlockStatus_return: ++ ++ ISP_WRITE(REG_ISP_SPI_CECLR, ISP_SPI_CECLR); // SPI CEB dis ++ ++ ISP_WRITE(REG_ISP_TRIGGER_MODE, 0x2222); // disable trigger mode ++ ++ _HAL_ISP_Disable(); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return u8Val; ++} ++ ++ ++/*static MS_U32 _Get_Time(void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++}*/ ++ ++/* ++ ++//FSP command , note that it cannot be access only by PM51 if secure boot on. ++MS_U8 HAL_SERFLASH_ReadStatusByFSP(void) ++{ ++ MS_U8 u8datget; ++ MS_BOOL bRet = FALSE; ++ bRet=HAL_FSP_ReadStatusReg(&u8datget); ++ if(!bRet) ++ printk("Read status failed \n"); ++ return u8datget ; ++} ++ ++void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf) ++{ ++#define HAL_FSP_READ_SIZE 4 ++ if(!HAL_FSP_Read(u32Addr,HAL_FSP_READ_SIZE,pu8Buf)) ++ printk("HAL_FSP_Read Fail:Addr is %x pu8Buf is :%x\n",(unsigned int)u32Addr, (unsigned int)pu8Buf); ++ ++} ++ ++void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize) ++{ ++ MS_U32 i; ++ MS_U32 u32FlashData = 0; ++ ++ while(HAL_SERFLASH_ReadStatusByFSP()==0x01) ++ { ++ printk("device is busy\n"); ++ } ++ for(i=0;i>(u8index*8)); ++ if(!HAL_FSP_Write(u32Addr,HAL_FSP_WRITE_SIZE, &pu8Write_Data)) ++ printk("HAL_FSP_WRITE Fail:Addr is %x pu8Buf is :%x\n",(int)u32Addr, (int)pu8Write_Data); ++ } ++ ++}*/ ++ ++static MS_BOOL _HAL_FSP_WaitDone(void) ++{ ++ MS_BOOL bRet = FALSE; ++ //struct timeval time_st; ++ unsigned long deadline; ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do{ ++ if ( (FSP_READ(REG_FSP_DONE_FLAG) & REG_FSP_DONE_FLAG_MASK) == REG_FSP_DONE ) ++ { ++ bRet = TRUE; ++ break; ++ } ++ //}while (!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR )); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ FSP_WRITE_MASK(REG_FSP_DONE_CLR,REG_FSP_CLR,REG_FSP_DONE_CLR_MASK); ++ ++ return bRet; ++} ++ ++ ++ ++MS_U8 HAL_FSP_ReadBufs(MS_U8 u8Idx) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: return (MS_U8)((FSP_READ(REG_FSP_RDB0) & 0x00FF) >> 0); ++ break; ++ case 1: return (MS_U8)((FSP_READ(REG_FSP_RDB1) & 0xFF00) >> 8); ++ break; ++ case 2: return (MS_U8)((FSP_READ(REG_FSP_RDB2) & 0x00FF) >> 0); ++ break; ++ case 3: return (MS_U8)((FSP_READ(REG_FSP_RDB3) & 0xFF00) >> 8); ++ break; ++ case 4: return (MS_U8)((FSP_READ(REG_FSP_RDB4) & 0x00FF) >> 0); ++ break; ++ case 5: return (MS_U8)((FSP_READ(REG_FSP_RDB5) & 0xFF00) >> 8); ++ break; ++ case 6: return (MS_U8)((FSP_READ(REG_FSP_RDB6) & 0x00FF) >> 0); ++ break; ++ case 7: return (MS_U8)((FSP_READ(REG_FSP_RDB7) & 0xFF00) >> 8); ++ break; ++ case 8: return (MS_U8)((FSP_READ(REG_FSP_RDB8) & 0x00FF) >> 0); ++ break; ++ case 9: return (MS_U8)((FSP_READ(REG_FSP_RDB9) & 0xFF00) >> 8); ++ break; ++ } ++ return -1; ++} ++ ++void HAL_FSP_WriteBufs(MS_U8 u8Idx, MS_U8 u8Data) ++{ ++ switch ( u8Idx ) ++ { ++ case 0: ++ FSP_WRITE_MASK(REG_FSP_WDB0,REG_FSP_WDB0_DATA(u8Data),REG_FSP_WDB0_MASK); ++ break; ++ case 1: ++ FSP_WRITE_MASK(REG_FSP_WDB1,REG_FSP_WDB1_DATA(u8Data),REG_FSP_WDB1_MASK); ++ break; ++ case 2: ++ FSP_WRITE_MASK(REG_FSP_WDB2,REG_FSP_WDB2_DATA(u8Data),REG_FSP_WDB2_MASK); ++ break; ++ case 3: ++ FSP_WRITE_MASK(REG_FSP_WDB3,REG_FSP_WDB3_DATA(u8Data),REG_FSP_WDB3_MASK); ++ break; ++ case 4: ++ FSP_WRITE_MASK(REG_FSP_WDB4,REG_FSP_WDB4_DATA(u8Data),REG_FSP_WDB4_MASK); ++ break; ++ case 5: ++ FSP_WRITE_MASK(REG_FSP_WDB5,REG_FSP_WDB5_DATA(u8Data),REG_FSP_WDB5_MASK); ++ break; ++ case 6: ++ FSP_WRITE_MASK(REG_FSP_WDB6,REG_FSP_WDB6_DATA(u8Data),REG_FSP_WDB6_MASK); ++ break; ++ case 7: ++ FSP_WRITE_MASK(REG_FSP_WDB7,REG_FSP_WDB7_DATA(u8Data),REG_FSP_WDB7_MASK); ++ break; ++ case 8: ++ FSP_WRITE_MASK(REG_FSP_WDB8,REG_FSP_WDB8_DATA(u8Data),REG_FSP_WDB8_MASK); ++ break; ++ case 9: ++ FSP_WRITE_MASK(REG_FSP_WDB9,REG_FSP_WDB9_DATA(u8Data),REG_FSP_WDB9_MASK); ++ break; ++ default: ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("HAL_FSP_WriteBufs fails\n")); ++ break; ++ } ++} ++ ++void HAL_FSP_Entry(void) ++{ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("[FSP] %s ENTRY fails!\n", __FUNCTION__); ++ return; ++ } ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE); ++ if (gReadMode==E_QUAD_MODE) ++ { ++ HAL_QUAD_Enable(0); ++ } ++} ++ ++void HAL_FSP_Exit(void) ++{ ++ if (gReadMode==E_QUAD_MODE) ++ HAL_QUAD_Enable(1); ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++} ++ ++ ++MS_BOOL HAL_FSP_EraseChip(void) ++{ ++ MS_BOOL bRet = TRUE; ++ //DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s()\n", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_CE); ++ HAL_FSP_WriteBufs(2,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(1),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Erase Chip Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++static MS_BOOL _HAL_FSP_BlockErase(MS_U32 u32FlashAddr, EN_FLASH_ERASE eSize) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8EAR = u32FlashAddr >> 24; ++ // DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printf("%s(0x%08X, 0x%08X)\n", __FUNCTION__, (int)u32FlashAddr, (int)eSize)); ++ if (u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,eSize); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32FlashAddr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32FlashAddr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32FlashAddr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(4),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Block Erase Timeout !!!!offset:0x%lx cmd:0x%x \r\n", u32FlashAddr, eSize); ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx; ++ MS_U32 u32FlashAddr = 0; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08x, 0x%08x, %d)\n", __FUNCTION__, (unsigned int)u32StartBlock, (unsigned int)u32EndBlock, (int)bWait)); ++ MS_ASSERT( u32StartBlock<=u32EndBlock && u32EndBlock>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB0 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ ++ u32quotient = (u32Size / REG_FSP_MAX_WRITEDATA_SIZE); ++ u32remainder = (u32Size % REG_FSP_MAX_WRITEDATA_SIZE); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ ++ for( u32I = 0; u32I < u32quotient; u32I++ ) ++ { ++ for( u32J = 0; u32J < u32Size; u32J++ ) ++ { ++ HAL_FSP_WriteBufs(u32J,*(pu8Data+u32J)); ++ } ++ pu8Data += u32I; ++ u32Size = REG_FSP_MAX_WRITEDATA_SIZE; ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(u32J), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER, REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB1 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ } ++ ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ do ++ { ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]WB2 Write command Fail!!!!\r\n"); ++ return bRet; ++ } ++ ++ u8Status = HAL_FSP_ReadBufs(0); ++ }while(u8Status & FLASH_OIP); ++ u32Size = FLASH_PAGE_SIZE; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Enable Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ HAL_FSP_WriteBufs(0,SPI_CMD_QPI_RST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] QPI Reset Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] %s %d\n", __FUNCTION__, bEnable)); ++ if(_hal_SERFLASH.u8MID == MID_MXIC) ++ { ++ if(bEnable) ++ u8data = SF_SR_QUALD; ++ else ++ u8data = 0; ++ bRet = HAL_FSP_WriteStatusReg(u8data); ++ } ++ else if(_hal_SERFLASH.u8MID == MID_GD) ++ { ++ MS_U8 u8status[3]={0xff,0xff,0xff,}; ++ if(bEnable) ++ u8data = BITS(1:1, 1); ++ else ++ u8data = BITS(1:1, 0); ++ ++ bRet = HAL_FSP_WriteStatus(0x31, 1, &u8data); ++ bRet = HAL_FSP_ReadStatus(0x35, 1, u8status); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("[FSP] GD status2:0x%x 0x%x 0x%x\n",u8status[0], u8status[1], u8status[2])); ++ } ++ ++ return bRet; ++} ++ ++void HAL_FSP_Write_Egine(MS_U32 u32Write_Addr, MS_U8 u8Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Write_Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Write_Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,(MS_U8)((u32Write_Addr>>0x00)&0xFF)); ++ for( u32I = 0; u32I < u8Size; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs((5 + u8Size),SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((4+u8Size)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP]PP FAIL Timeout !!!!\r\n"); ++ } ++} ++ ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++// MS_U32 u32I; ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32J; ++ MS_U32 u32quotient; ++ MS_U8 u8BufSize = REG_FSP_WRITEDATA_SIZE; ++ MS_U8 u8dat_align=0; ++ MS_U8 u8addr_align=0; ++ MS_U8 u8remainder=0; ++ MS_U8 u8writebytes=0; ++ ++ u8addr_align=((MS_U8)(u32Addr))&0xF; ++ u8dat_align=u8addr_align%4; ++ if(u8dat_align) ++ { ++ u8writebytes = 4-u8dat_align; ++ HAL_FSP_Write_Egine(u32Addr,u8writebytes,pu8Data); ++ u32Addr += u8writebytes; ++ pu8Data += u8writebytes; ++ } ++ u32quotient = ((u32Size-u8writebytes) / u8BufSize); ++ u8remainder = ((u32Size-u8writebytes) % u8BufSize); ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8BufSize,pu8Data); ++ u32Addr += u8BufSize; ++ pu8Data += u8BufSize; ++ } ++ ++ if(u8remainder) ++ { ++ HAL_FSP_Write_Egine(u32Addr,u8remainder,pu8Data); ++ u32Addr += u8remainder; ++ pu8Data += u8remainder; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ HAL_FSP_WriteBufs(0, SPI_CMD_READ); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ /*Lost first byte in using normal read command;Dummy Byte for Fast Read*/ ++ //HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ u32Addr += u32Idx; ++ u32Size = u8BufSize; ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32Idx, u32J; ++ MS_U32 u32quotient; ++ MS_U32 u32remainder; ++ MS_U8 u8BufSize = REG_FSP_READDATA_SIZE; ++ ++ u32quotient = (u32Size / u8BufSize); ++ u32remainder = (u32Size % u8BufSize); ++ if(u32remainder) ++ { ++ u32quotient++; ++ u32Size = u32remainder; ++ } ++ else ++ u32Size = u8BufSize; ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_FASTREAD); ++ HAL_FSP_WriteBufs(1,(MS_U8)((u32Addr>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u32Addr>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u32Addr>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(4, 0x00); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(5),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ ++ for(u32J = 0; u32J < u32quotient; u32J++) ++ { ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_ENABLE_BURST); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(0),REG_FSP_WBF_SIZE0_MASK); ++ if(!bRet) ++ { ++ printk("[FSP] RIU Read Burst FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Idx = 0; u32Idx < u32Size; u32Idx++ ) ++ *(pu8Data + u32Idx) = HAL_FSP_ReadBufs(u32Idx); ++ pu8Data += u32Idx; ++ if(u32remainder && (u32remainder != u8BufSize)) ++ { ++ u32Size = u8BufSize; ++ u32remainder = u8BufSize; ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ } ++ ++ } ++ QSPI_WRITE(REG_SPI_BURST_WRITE,REG_SPI_DISABLE_BURST); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnableAllArea)); ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnableAllArea ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ if (bEnableAllArea) ++ { // SF_SR_SRWD: SRWD Status Register Write Protect ++ HAL_FSP_WriteBufs(2,(MS_U8)(SF_SR_SRWD | SERFLASH_WRSR_BLK_PROTECT)); ++ } ++ else ++ { ++ // [4:2] or [5:2] protect blocks ++ HAL_FSP_WriteBufs(2,(SF_SR_SRWD | u8BlockProtectBits)); ++ } ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect Area FAIL Timeout !!!!\r\n"); ++ } ++ if( bEnableAllArea ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnableAllArea); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8Status; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(%d)\n", __FUNCTION__, bEnable)); ++ ++ u8Status = SF_SR_SRWD; ++ if (gReadMode==E_QUAD_MODE) ++ u8Status |= SF_SR_QUALD; ++ if (bEnable) ++ u8Status |= SERFLASH_WRSR_BLK_PROTECT; ++ ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(0); ++ //MsOS_DelayTask(bEnable ? 5 : 20); ++ udelay(20); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2, u8Status); ++ HAL_FSP_WriteBufs(3,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Protect FAIL Timeout !!!!\r\n"); ++ } ++ ++ if( bEnable ) ++ _HAL_SERFLASH_ActiveFlash_Set_HW_WP(bEnable); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 *u8ptr = pu8Data; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() in\n", __FUNCTION__)); ++ ++ HAL_SERFLASH_SelectReadMode(E_SINGLE_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0, SPI_CMD_RDID); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read ID FAIL Timeout !!!!\r\n"); ++ } ++ *(u8ptr + 0) = HAL_FSP_ReadBufs(0); ++ *(u8ptr + 1) = HAL_FSP_ReadBufs(1); ++ *(u8ptr + 2) = HAL_FSP_ReadBufs(2); ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s() out\n", __FUNCTION__)); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8StatusReg = 0xFF; ++ HAL_FSP_WriteBufs(0,SPI_CMD_RDSR2); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(1),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read status2 FAIL Timeout !!!!\r\n"); ++ } ++ ++ *pu8StatusReg = HAL_FSP_ReadBufs(0); ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U32 u32Index; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ ++ MS_ASSERT( MsOS_In_Interrupt() == FALSE ); ++ MS_ASSERT(_HAL_SERFLASH_Check51RunMode()); ++ ++ if (FALSE == MS_SERFLASH_OBTAIN_MUTEX(_s32SERFLASH_Mutex, SERFLASH_MUTEX_WAIT_TIME)) ++ { ++ printk("%s ENTRY fails!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HAL_SERFLASH_SelectReadMode(E_FAST_MODE);//set normal mode(1-1-1) ++ ++ HAL_FSP_WriteBufs(0,ISP_SPI_CMD_REMS); ++ HAL_FSP_WriteBufs(1,0); //dummy ++ HAL_FSP_WriteBufs(2,0); //dummy ++ HAL_FSP_WriteBufs(3,0); // start address ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(4),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u32Size),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Read REMS4 FAIL Timeout !!!!\r\n"); ++ } ++ for( u32Index = 0; u32Index < u32Size; u32Index++ ) ++ *(pu8Data + u32Index) = HAL_FSP_ReadBufs(u32Index); ++ ++ MS_SERFLASH_RELEASE_MUTEX(_s32SERFLASH_Mutex); ++ ++ return bRet; ++ ++} ++ ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg) ++{ ++ MS_BOOL bRet = TRUE; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WRSR); ++ HAL_FSP_WriteBufs(2,(MS_U8)((u16StatusReg>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(3,(MS_U8)((u16StatusReg>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(3),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] Write Status FAIL Timeout !!!!\r\n"); ++ } ++ ++ return bRet; ++} ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ *pu8Data = 0xFF; ++ HAL_FSP_WriteBufs(0,u8CMD); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(0),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(u8CountData),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_OFF,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_OFF,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] ReadStatus FAIL Timeout !!!!\r\n"); ++ } ++ ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ *(pu8Data+u32I) = HAL_FSP_ReadBufs(u32I); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U32 u32I; ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,u8CMD); ++ for( u32I = 0; u32I < u8CountData; u32I++ ) ++ { ++ HAL_FSP_WriteBufs((5+u32I),*(pu8Data+u32I)); ++ } ++ HAL_FSP_WriteBufs(2+u8CountData,SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1((1+u8CountData)),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(1),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(1),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_ON,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD,REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] WriteStatus FAIL Timeout !!!!\r\n"); ++ } ++ return bRet; ++} ++ ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg) ++{ ++ MS_BOOL bRet = TRUE; ++ ++ if (!_bHasEAR) ++ return FALSE; ++ else if (u8ExtAddrReg == _u8RegEAR) ++ return TRUE; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s()", __FUNCTION__)); ++ HAL_FSP_WriteBufs(0,SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1,SPI_CMD_WREAR); ++ HAL_FSP_WriteBufs(2,u8ExtAddrReg); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE0(1),REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE1(2),REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE,REG_FSP_WBF_SIZE2(0),REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE0(0),REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE1(0),REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE,REG_FSP_RBF_SIZE2(0),REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_ENABLE,REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_NRESET,REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_INT,REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_2NDCMD_ON,REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_3THCMD_OFF,REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL,REG_FSP_FSCHK_ON,REG_FSP_FSCHK_MASK); ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE,REG_FSP_TRIGGER_MASK); ++ bRet &= _HAL_FSP_WaitDone(); ++ if (bRet) ++ { ++ _u8RegEAR = u8ExtAddrReg; ++ } ++ return bRet; ++} ++ ++#ifndef CONFIG_RIUISP ++ ++ ++ ++ ++void _HAL_BDMA_INIT(void) ++{ ++ MSYS_DMEM_INFO mem_info; ++ ++ mem_info.length = 0x100; ++ strcpy(mem_info.name, "BDMA_FSP_WBUFF"); ++ ++ if(!msys_request_dmem(&mem_info) ) ++ { ++ pu8BDMA_phys = mem_info.phys; ++ pu8BDMA_virt = mem_info.kvirt; ++ pu8BDMA_bus = pu8BDMA_phys&0x1FFFFFFF; ++ printk("[Ser flash] phys=0x%08x, virt=0x%08x, bus=0x%08x\n", (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_bus); ++ } ++ else ++ { ++ printk("[Ser flash] BDMA request buffer failed"); ++ } ++ ++ //printk("[Ser flash] BDMA vaddr=0x%x,paddr=0x%x bus=0x%x len=0x%x\n", (unsigned int)pu8BDMA_virt, (unsigned int)pu8BDMA_phys, (unsigned int)pu8BDMA_bus , (unsigned int)mem_info.length); ++ ++} ++/* ++static bool _HAL_BDMA_FlashToMem(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet; ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x12<<2)), 0X4035); ++ ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x14<<2)), (u32Src_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x15<<2)), (u32Src_off >> 16)); ++ ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x16<<2)), (u32Dst_off & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x17<<2)), (u32Dst_off >> 16)); ++ // Set Size ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x18<<2)), (u32Len & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x19<<2)), (u32Len >> 16)); ++ ++ // Trigger ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x10<<2)), 1); ++ ++ SER_FLASH_TIME(time_st); ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x11)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x11<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ } while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ return bRet; ++} ++ ++ ++static bool _HAL_BDMA_READ(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ ++ ++ MS_BOOL bRet; ++ ++ ++ //printk("[Ser flash] %s off=0x%x, len=0x%x\n", __FUNCTION__, (unsigned int)u32Addr, (unsigned int)u32Size); ++ ++ if(pu8BDMA_phys==0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_phys==0) ++ return FALSE; ++ ++ bRet = _HAL_BDMA_FlashToMem( u32Addr, pu8BDMA_phys&0x0FFFFFFF, u32Size); ++ if(bRet == TRUE) ++ memcpy((void *)pu8Data,(const void *) pu8BDMA_virt, u32Size); ++ ++ return bRet; ++ ++} ++ ++*/ ++void DumpMemory(MS_U32 u32Addr, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ ++ printk("Address 0x%p:", (void*)u32Addr); ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ printk(" %02x", *pdata); ++ pdata++; ++ } ++ printk("\n"); ++} ++ ++MS_BOOL CompareMemory(MS_U32 u32Addr, MS_U32 u32Addr2, MS_U32 u32Size) ++{ ++ MS_U8* pdata = (MS_U8*)u32Addr; ++ MS_U8* pdata2 = (MS_U8*)u32Addr2; ++ ++ while( (MS_U32)pdata != (u32Addr+u32Size)) ++ { ++ if(*pdata != *pdata2) ++ { ++ DumpMemory(u32Addr, u32Size); ++ DumpMemory(u32Addr2, u32Size); ++ ++ return FALSE; ++ } ++ pdata++,pdata2++; ++ } ++ return TRUE; ++} ++ ++ ++static MS_BOOL _HAL_PP_BDMAToFSP(MS_U32 u32Src_off, MS_U32 u32Dst_off, MS_U32 u32Len) ++{ ++ //struct timeval time_st; ++ MS_U16 u16data; ++ MS_BOOL bRet=FALSE; ++ unsigned long deadline; ++ MS_U8 u8EAR = u32Dst_off >> 24; ++ ++ if(u32Len>256) ++ return FALSE; ++ if((u8EAR == 0) && ((u32Dst_off + u32Len) > 0x1000000)) ++ { ++ printk("[FSP] PP BDMA cross the 16MB boundary\r\n"); ++ return FALSE; ++ } ++ if(u8EAR != _u8RegEAR) ++ { ++ HAL_FSP_WriteExtAddrReg(u8EAR); ++ } ++ ++ if(pu8BDMA_virt == 0) ++ _HAL_BDMA_INIT(); ++ if(pu8BDMA_virt == 0) ++ { ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_ERR, printk("%s, remap BDMA buffer failed)\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ memcpy((void *)pu8BDMA_virt, (const void *)u32Src_off, u32Len); ++ Chip_Flush_Cache_Range(pu8BDMA_virt, u32Len); ++ ++ // printk(" %s(0x%08X, %3d)\n", __FUNCTION__, (int)u32Dst_off, (int)u32Len); ++ ++ ++ ++ ++ /*BDMA */ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 0x00); ++ ++ //Set source and destination path ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x2<<2)), 0X2B40); //MIU to FSP(0xB) ++ // Set start address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x4<<2)), (pu8BDMA_bus & 0x0000FFFF)); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x5<<2)), (pu8BDMA_bus >> 16)); ++ // Set end address ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x6<<2)), 0x0); ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x7<<2)), 0x0); ++ // Set Size ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x8<<2)), (u32Len & 0x0000FFFF)); ++ //WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x9<<2)), (u32Len >> 16)); ++ ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x0<<2)), 1); // Trigger ++ ++ ++ /*FSP*/ ++ HAL_FSP_WriteBufs(0, SPI_CMD_WREN); ++ HAL_FSP_WriteBufs(1, SPI_CMD_PP); ++ HAL_FSP_WriteBufs(2, (MS_U8)((u32Dst_off>>0x10)&0xFF)); ++ HAL_FSP_WriteBufs(3, (MS_U8)((u32Dst_off>>0x08)&0xFF)); ++ HAL_FSP_WriteBufs(4, (MS_U8)((u32Dst_off>>0x00)&0xFF)); ++ HAL_FSP_WriteBufs(5, 0x00); //dummy ++ HAL_FSP_WriteBufs(6, SPI_CMD_RDSR); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE0(1), REG_FSP_WBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE1(5), REG_FSP_WBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_SIZE, REG_FSP_WBF_SIZE2(1), REG_FSP_WBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE0(0), REG_FSP_RBF_SIZE0_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE1(0), REG_FSP_RBF_SIZE1_MASK); ++ FSP_WRITE_MASK(REG_FSP_RBF_SIZE, REG_FSP_RBF_SIZE2(1), REG_FSP_RBF_SIZE2_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_ENABLE, REG_FSP_ENABLE_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_NRESET, REG_FSP_RESET_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_INT, REG_FSP_INT_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_2NDCMD_ON, REG_FSP_2NDCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD_ON, REG_FSP_3THCMD_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_3THCMD, REG_FSP_RDSR_MASK); ++ FSP_WRITE_MASK(REG_FSP_CTRL, REG_FSP_FSCHK_ON, REG_FSP_FSCHK_MASK); ++ ++ //set FSP Outside replace ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, u32Len&0x00FFFFFF); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_REPLACED(5), REG_FSP_WBF_REPLACED_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_MODE(1), REG_FSP_WBF_MODE_MASK); ++ FSP_WRITE_MASK(REG_FSP_WBF_OUTSIDE, REG_FSP_WBF_OUTSIDE_ENABLE, REG_FSP_WBF_OUTSIDE_ENABLE_MASK); ++ ++ FSP_WRITE_MASK(REG_FSP_TRIGGER,REG_FSP_FIRE, REG_FSP_TRIGGER_MASK); ++ ++ //check BDMA done ++ //SER_FLASH_TIME(time_st); ++ deadline = jiffies + MAX_READY_WAIT_JIFFIES; ++ do ++ { ++ ++ //check done ++ u16data = READ_WORD(_hal_isp.u32BdmaBaseAddr + ((0x1)<<2)); ++ if(u16data & 8) ++ { ++ //clear done ++ WRITE_WORD((_hal_isp.u32BdmaBaseAddr + (0x1<<2)), 8); ++ bRet = TRUE; ++ break; ++ } ++ //} while(!SER_FLASH_EXPIRE(time_st, SERFLASH_SAFETY_FACTOR)); ++ } while (!time_after_eq(jiffies, deadline)); ++ ++ if(bRet == FALSE) ++ { ++ printk("Wait for BDMA Done fails!\n"); ++ } ++ ++ //check FSP done ++ bRet = _HAL_FSP_WaitDone(); ++ if(!bRet) ++ { ++ printk("[FSP] BDMA2FSP FAIL Timeout !!!!\r\n"); ++ } ++ ++ //reset ++ FSP_WRITE(REG_FSP_WBF_SIZE_OUTSIDE, 0x0); ++ FSP_WRITE(REG_FSP_WBF_OUTSIDE, 0x0); ++ ++ //CompareMemory(u32Src_off, u32Dst_off+0xF4000000, u32Len); ++ ++ return bRet; ++} ++ ++ ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data) ++{ ++ MS_BOOL bRet = FALSE; ++ MS_U16 u16Rem, u16WriteBytes; ++ MS_U8 *u8Buf = pu8Data; ++ ++ DEBUG_SER_FLASH(E_SERFLASH_DBGLV_DEBUG, printk("%s(0x%08X, %4d, %p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data)); ++ //printk("%s(0x%08X, %d, 0x%p)\n", __FUNCTION__, (int)u32Addr, (int)u32Size, pu8Data); ++ ++ u16Rem = u32Addr % SERFLASH_PAGE_SIZE; ++ ++ if (u16Rem) ++ { ++ u16WriteBytes = SERFLASH_PAGE_SIZE - u16Rem; ++ if (u32Size < u16WriteBytes) ++ { ++ u16WriteBytes = u32Size; ++ } ++ ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++ while(u32Size) ++ { ++ u16WriteBytes =(u32Size>SERFLASH_PAGE_SIZE) ? SERFLASH_PAGE_SIZE:u32Size; ++ ++ bRet = _HAL_PP_BDMAToFSP((MS_U32)u8Buf, u32Addr, u16WriteBytes); ++ ++ if ( bRet == TRUE ) ++ { ++ u32Addr += u16WriteBytes; ++ u8Buf += u16WriteBytes; ++ u32Size -= u16WriteBytes; ++ } ++ else ++ { ++ goto HAL_SERFLASH_Write_return; ++ } ++ } ++ ++HAL_SERFLASH_Write_return: ++ ++ return bRet; ++} ++ ++#endif +diff --git a/drivers/mstar/flash_isp/infinity3/halSERFLASH.h b/drivers/mstar/flash_isp/infinity3/halSERFLASH.h +new file mode 100644 +index 00000000..e0cd6ac4 +--- /dev/null ++++ b/drivers/mstar/flash_isp/infinity3/halSERFLASH.h +@@ -0,0 +1,171 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_SERFLASH_H_ ++#define _HAL_SERFLASH_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// Flash IC ++ ++ ++ ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define MSOS_TYPE_LINUX 1 ++ ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++#define NUMBER_OF_SERFLASH_SECTORS (_hal_SERFLASH.u32NumSec) ++#define SERFLASH_SECTOR_SIZE (_hal_SERFLASH.u32SecSize) ++#define SERFLASH_PAGE_SIZE (_hal_SERFLASH.u16PageSize) ++#define SERFLASH_MAX_CHIP_WR_DONE_TIMEOUT (_hal_SERFLASH.u16MaxChipWrDoneTimeout) ++#define SERFLASH_WRSR_BLK_PROTECT (_hal_SERFLASH.u8WrsrBlkProtect) ++#define ISP_DEV_SEL (_hal_SERFLASH.u16DevSel) ++#define ISP_SPI_ENDIAN_SEL (_hal_SERFLASH.u16SpiEndianSel) ++ ++ ++#define DEBUG_SER_FLASH(debug_level, x) do { if (_u8SERFLASHDbgLevel >= (debug_level)) (x); } while(0) ++#define WAIT_SFSH_CS_STAT() {while(ISP_READ(REG_ISP_SPI_CHIP_SELE_BUSY) == SFSH_CHIP_SELE_SWITCH){}} ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ FLASH_ID0 = 0x00, ++ FLASH_ID1 = 0x01, ++ FLASH_ID2 = 0x02, ++ FLASH_ID3 = 0x03 ++} EN_FLASH_ID; ++ ++typedef enum ++{ ++ WP_AREA_EXACTLY_AVAILABLE, ++ WP_AREA_PARTIALLY_AVAILABLE, ++ WP_AREA_NOT_AVAILABLE, ++ WP_TABLE_NOT_SUPPORT, ++} EN_WP_AREA_EXISTED_RTN; ++ ++typedef enum ++{ ++ FLASH_ERASE_04K = SPI_CMD_SE, ++ FLASH_ERASE_32K = SPI_CMD_32BE, ++ FLASH_ERASE_64K = SPI_CMD_64BE ++} EN_FLASH_ERASE; ++ ++ ++typedef enum ++{ ++ E_SINGLE_MODE, ++ E_FAST_MODE, ++ E_DUAL_D_MODE, ++ E_DUAL_AD_MODE, ++ E_QUAD_MODE, ++ E_RIUISP_MODE=0xFF ++}SPI_READ_MODE; ++ ++typedef enum ++{ ++ E_2PINS, ++ E_4PINS ++}SPI_PAD_SUPPORT; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++extern MS_BOOL HAL_SERFLASH_SetCKG(SPI_DrvCKG eCkgSpi); ++extern void HAL_SERFLASH_ClkDiv(SPI_DrvClkDiv eClkDivSpi); ++extern MS_BOOL HAL_SERFLASH_SetMode(MS_BOOL bXiuRiu); ++extern MS_BOOL HAL_SERFLASH_Set2XREAD(MS_BOOL b2XMode); ++extern MS_BOOL HAL_SERFLASH_Set4XREAD(MS_BOOL b4XMode); ++extern MS_BOOL HAL_SERFLASH_ChipSelect(MS_U8 u8FlashIndex); ++extern void HAL_SERFLASH_Config(void); ++extern void HAL_SERFLASH_Init(void); ++extern void HAL_SERFLASH_SetGPIO(MS_BOOL bSwitch); ++extern MS_BOOL HAL_SERFLASH_DetectType(void); ++extern MS_BOOL HAL_SERFLASH_DetectSize(MS_U32 *u32FlashSize); ++extern MS_BOOL HAL_SERFLASH_EraseChip(void); ++extern MS_BOOL HAL_SERFLASH_AddressToBlock(MS_U32 u32FlashAddr, MS_U32 *pu32BlockIndex); ++extern MS_BOOL HAL_SERFLASH_BlockToAddress(MS_U32 u32BlockIndex, MS_U32 *pu32FlashAddr); ++extern MS_BOOL HAL_SERFLASH_BlockErase(MS_U32 u32StartBlock,MS_U32 u32EndBlock,MS_BOOL bWait); ++extern MS_BOOL HAL_SERFLASH_SectorErase(MS_U32 u32SectorAddress); ++extern MS_BOOL HAL_SERFLASH_CheckWriteDone(void); ++extern MS_BOOL HAL_SERFLASH_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern MS_BOOL HAL_SERFLASH_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++extern EN_WP_AREA_EXISTED_RTN HAL_SERFLASH_WP_Area_Existed(MS_U32 u32UpperBound, MS_U32 u32LowerBound, MS_U8 *pu8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++extern MS_BOOL HAL_SERFLASH_WriteProtect(MS_BOOL bEnable); ++extern MS_BOOL HAL_SERFLASH_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadREMS4(MS_U8 * pu8Data, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_DMA(MS_U32 u32FlashStart, MS_U32 u32DRAMStart, MS_U32 u32Size); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_ReadStatusReg2(MS_U8 *pu8StatusReg); ++extern MS_BOOL HAL_SERFLASH_WriteStatusReg(MS_U16 u16StatusReg); ++//#if MXIC_ONLY ++extern MS_BOOL HAL_SPI_EnterIBPM(void); ++extern MS_BOOL HAL_SPI_SingleBlockLock(MS_PHYADDR u32FlashAddr, MS_BOOL bLock); ++extern MS_BOOL HAL_SPI_GangBlockLock(MS_BOOL bLock); ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++//#endif//MXIC_ONLY ++// DON'T USE THESE DIRECTLY ++extern MS_U8 _u8SERFLASHDbgLevel; ++extern MS_BOOL _bIBPM; ++ ++extern MS_U8 HAL_SERFLASH_ReadStatusByFSP(void); ++extern void HAL_SERFLASH_ReadWordFlashByFSP(MS_U32 u32Addr, MS_U8 *pu8Buf); ++extern void HAL_SERFLASH_CheckEmptyByFSP(MS_U32 u32Addr, MS_U32 u32ChkSize); ++extern void HAL_SERFLASH_EraseSectorByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock32KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_EraseBlock64KByFSP(MS_U32 u32Addr); ++extern void HAL_SERFLASH_ProgramFlashByFSP(MS_U32 u32Addr, MS_U32 u32Data); ++ ++extern MS_U8 HAL_SPI_ReadBlockStatus(MS_PHYADDR u32FlashAddr); ++ ++ ++MS_BOOL HAL_FSP_BlockErase(MS_U32 u32StartBlock, MS_U32 u32EndBlock, MS_BOOL bWait); ++MS_BOOL HAL_FSP_BurstRead(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Read(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_SectorErase(MS_U32 u32SectorAddress,MS_U8 u8cmd); ++MS_BOOL HAL_FSP_Write(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_Write_Burst(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++MS_BOOL HAL_FSP_WriteProtect_Area(MS_BOOL bEnableAllArea, MS_U8 u8BlockProtectBits); ++MS_BOOL HAL_FSP_WriteProtect(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadID(MS_U8 *pu8Data, MS_U32 u32Size); ++MS_BOOL HAL_FSP_ReadStatusReg(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_ReadStatusReg2(MS_U8 *pu8StatusReg); ++MS_BOOL HAL_FSP_WriteStatusReg(MS_U16 u16StatusReg); ++MS_BOOL HAL_FSP_WriteExtAddrReg(MS_U8 u8ExtAddrReg); ++MS_BOOL HAL_QPI_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_QPI_RESET(MS_BOOL bEnable); ++ ++MS_BOOL HAL_FSP_Write_BDMA(MS_U32 u32Addr, MS_U32 u32Size, MS_U8 *pu8Data); ++ ++MS_BOOL HAL_QUAD_Enable(MS_BOOL bEnable); ++MS_BOOL HAL_FSP_ReadStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++MS_BOOL HAL_FSP_WriteStatus(MS_U8 u8CMD, MS_U8 u8CountData, MS_U8* pu8Data); ++ ++ ++#endif // _HAL_SERFLASH_H_ +diff --git a/drivers/mstar/flash_isp/infinity3/regSERFLASH.h b/drivers/mstar/flash_isp/infinity3/regSERFLASH.h +new file mode 100644 +index 00000000..1c55c63d +--- /dev/null ++++ b/drivers/mstar/flash_isp/infinity3/regSERFLASH.h +@@ -0,0 +1,498 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file regSERFLASH.h ++/// @brief Serial Flash Register Definition ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_SERFLASH_H_ ++#define _REG_SERFLASH_H_ ++//#include "mach/platform.h" ++ ++ ++//#include "mhal_chiptop_reg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++ ++// !!! Uranus Serial Flash Notes: !!! ++// - The clock of DMA & Read via XIU operations must be < 3*CPU clock ++// - The clock of DMA & Read via XIU operations are determined by only REG_ISP_CLK_SRC; other operations by REG_ISP_CLK_SRC only ++// - DMA program can't run on DRAM, but in flash ONLY ++// - DMA from SPI to DRAM => size/DRAM start/DRAM end must be 8-B aligned ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++// BASEADDR & BK ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define MS_SPI_ADDR 0x14000000 ++#define MS_SPI_IO_SIZE 0x1000000 ++ ++ ++#define BASE_REG_ISP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x000800) ++#define BASE_REG_FSP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001600) ++#define BASE_REG_QSPI_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x001700) ++#define BASE_REG_CHIPTOP_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x101E00) ++#define BASE_REG_BDMACh0_ADDR GET_BASE_ADDR_BY_BANK(IO_ADDRESS(MS_BASE_REG_RIU_PA), 0x100200) ++ ++ ++//----- Chip flash ------------------------- ++//#define REG_SPI_BASE 0x7F ++ ++//Bit operation ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++// ISP_CMD ++ ++#define REG_ISP_PASSWORD 0x00 // ISP / XIU read / DMA mutual exclusive ++#define REG_ISP_SPI_COMMAND 0x01 ++ // please refer to the serial flash datasheet ++ #define ISP_SPI_CMD_READ BITS(7:0, 0x03) ++ #define ISP_SPI_CMD_FASTREAD BITS(7:0, 0x0B) ++ #define ISP_SPI_CMD_RDID BITS(7:0, 0x9F) ++ #define ISP_SPI_CMD_WREN BITS(7:0, 0x06) ++ #define ISP_SPI_CMD_WRDI BITS(7:0, 0x04) ++ #define ISP_SPI_CMD_SE BITS(7:0, 0x20) ++ #define ISP_SPI_CMD_32BE BITS(7:0, 0x52) ++ #define ISP_SPI_CMD_64BE BITS(7:0, 0xD8) ++ #define ISP_SPI_CMD_CE BITS(7:0, 0xC7) ++ #define ISP_SPI_CMD_PP BITS(7:0, 0x02) ++ #define ISP_SPI_CMD_RDSR BITS(7:0, 0x05) ++ #define ISP_SPI_CMD_RDSR2 BITS(7:0, 0x35) // support for new WinBond Flash ++ #define ISP_SPI_CMD_WRSR BITS(7:0, 0x01) ++ #define ISP_SPI_CMD_DP BITS(7:0, 0xB9) ++ #define ISP_SPI_CMD_RDP BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_RES BITS(7:0, 0xAB) ++ #define ISP_SPI_CMD_REMS BITS(7:0, 0x90) ++ #define ISP_SPI_CMD_REMS4 BITS(7:0, 0xCF) // support for new MXIC Flash ++ #define ISP_SPI_CMD_PARALLEL BITS(7:0, 0x55) ++ #define ISP_SPI_CMD_EN4K BITS(7:0, 0xA5) ++ #define ISP_SPI_CMD_EX4K BITS(7:0, 0xB5) ++ /* MXIC Individual Block Protection Mode */ ++ #define ISP_SPI_CMD_WPSEL BITS(7:0, 0x68) ++ #define ISP_SPI_CMD_SBLK BITS(7:0, 0x36) ++ #define ISP_SPI_CMD_SBULK BITS(7:0, 0x39) ++ #define ISP_SPI_CMD_RDSCUR BITS(7:0, 0x2B) ++ #define ISP_SPI_CMD_RDBLOCK BITS(7:0, 0x3C) ++ #define ISP_SPI_CMD_GBLK BITS(7:0, 0x7E) ++ #define ISP_SPI_CMD_GBULK BITS(7:0, 0x98) ++#define REG_ISP_SPI_ADDR_L 0x02 // A[15:0] ++#define REG_ISP_SPI_ADDR_H 0x03 // A[23:16] ++#define REG_ISP_SPI_WDATA 0x04 ++ #define ISP_SPI_WDATA_DUMMY BITS(7:0, 0xFF) ++#define REG_ISP_SPI_RDATA 0x05 ++#define REG_ISP_SPI_CLKDIV 0x06 // clock = CPU clock / this div ++ #define ISP_SPI_CLKDIV2 BIT(0) ++ #define ISP_SPI_CLKDIV4 BIT(2) ++ #define ISP_SPI_CLKDIV8 BIT(6) ++ #define ISP_SPI_CLKDIV16 BIT(7) ++ #define ISP_SPI_CLKDIV32 BIT(8) ++ #define ISP_SPI_CLKDIV64 BIT(9) ++ #define ISP_SPI_CLKDIV128 BIT(10) ++#define REG_ISP_DEV_SEL 0x07 ++#define REG_ISP_SPI_CECLR 0x08 ++ #define ISP_SPI_CECLR BITS(0:0, 1) ++#define REG_ISP_SPI_RDREQ 0x0C ++ #define ISP_SPI_RDREQ BITS(0:0, 1) ++#define REG_ISP_SPI_ENDIAN 0x0F ++#define REG_ISP_SPI_RD_DATARDY 0x15 ++ #define ISP_SPI_RD_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_RD_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_DATARDY 0x16 ++ #define ISP_SPI_WR_DATARDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_DATARDY BITS(0:0, 1) ++#define REG_ISP_SPI_WR_CMDRDY 0x17 ++ #define ISP_SPI_WR_CMDRDY_MASK BMASK(0:0) ++ #define ISP_SPI_WR_CMDRDY BITS(0:0, 1) ++#define REG_ISP_TRIGGER_MODE 0x2a ++#define REG_ISP_CHIP_SEL 0x36 ++ #define SFSH_CHIP_SEL_MASK BMASK(6:0) ++ #define SFSH_CHIP_SEL_FLASH1 BIT(0) ++ #define SFSH_CHIP_SEL_FLASH2 BIT(1) ++ #define SFSH_CHIP_SEL_SPI_DEV1 BIT(2) ++ #define SFSH_CHIP_SEL_SPI_DEV2 BIT(3) ++ #define SFSH_CHIP_SEL_SPI_DEV3 BIT(4) ++ #define SFSH_CHIP_SEL_SPI_DEV4 BIT(5) ++ #define SFSH_CHIP_SEL_SPI_DEV5 BIT(6) ++// #define SFSH_CHIP_SEC_MASK BMASK(7:0) // 0x00FF // TODO: review this define ++ #define SFSH_CHIP_SEL_MODE_SEL_MASK BMASK(7:7) ++ #define SFSH_CHIP_SEL_RIU BITS(7:7, 1) // 0x0080 ++ #define SFSH_CHIP_SEL_XIU BITS(7:7, 0) // 0x0000 ++#define REG_ISP_CHIP_RST 0x3F // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define SFSH_CHIP_RESET_MASK BMASK(2:2) ++ #define SFSH_CHIP_RESET BITS(2:2, 0) ++ #define SFSH_CHIP_NOTRESET BITS(2:2, 1) ++ ++#define REG_SPI_CS_TIME 0x71 ++ #define SFSH_CS_DESEL_MASK BMASK(3:0) ++ #define SFSH_CS_DESEL_TWO BITS(3:0, 1) ++ #define SFSH_CS_SETUP_MASK BMASK(7:4) ++ #define SFSH_CS_SETUP_TWO BITS(7:4, 1) ++ #define SFSH_CS_HOLD_MASK BMASK(11:8) ++ #define SFSH_CS_HOLD_TWO BITS(11:8, 1) ++ ++#define REG_ISP_SPI_MODE 0x72 ++ #define SFSH_CHIP_FAST_MASK BMASK(3:0) // SPI CMD [0x0B] ++ #define SFSH_CHIP_FAST_ENABLE BITS(3:0, 1) ++ #define SFSH_CHIP_FAST_DISABLE BITS(0:0, 0) ++ #define SFSH_CHIP_2XREAD_MASK BMASK(3:0) // SPI CMD [0xBB] ++ #define SFSH_CHIP_2XREAD_ENABLE BITS(3:0, 3) ++ #define SFSH_CHIP_2XREAD_DISABLE BITS(3:0, 0) ++ #define SFSH_CHIP_4XREAD_MASK BMASK(3:0) // SPI CMD [0xEB] ++ #define SFSH_CHIP_4XREAD_ENABLE BITS(3:0, 10)////// ++ #define SFSH_CHIP_4XREAD_DISABLE BITS(3:0, 0) ++#define REG_ISP_SPI_CHIP_SELE 0x7A ++ #define SFSH_CHIP_SELE_MASK BMASK(1:0) // only for secure booting = 0; ++ #define SFSH_CHIP_SELE_EXT1 BITS(1:0, 0) ++ #define SFSH_CHIP_SELE_EXT2 BITS(1:0, 1) ++ #define SFSH_CHIP_SELE_EXT3 BITS(1:0, 2) ++#define REG_ISP_SPI_CHIP_SELE_BUSY 0x7B ++ #define SFSH_CHIP_SELE_BUSY_MASK BMASK(0:0) ++ #define SFSH_CHIP_SELE_SWITCH BITS(0:0, 1) ++ #define SFSH_CHIP_SELE_DONE BITS(0:0, 0) ++ ++// PIU_DMA ++ ++#define REG_PIU_DMA_STATUS 0x10 // [1]done [2]busy [8:15]state ++ #define PIU_DMA_DONE_MASK BMASK(0:0) ++ #define PIU_DMA_DONE BITS(0:0, 1) ++ #define PIU_DMA_BUSY_MASK BMASK(1:1) ++ #define PIU_DMA_BUSY BITS(1:1, 1) ++ #define PIU_DMA_STATE_MASK BMASK(15:8) ++#define REG_PIU_SPI_CLK_SRC 0x26 // SPI clock source [0]:gate [1]:inv [4:2]:clk_sel 000:Xtal clock 001:27MHz 010:36MHz 011:43.2MHz 100:54MHz 101:72MHz 110:86MHz 111:108MHz [5]:0:xtal 1:clk_Sel ++ #define PIU_SPI_RESET_MASK BMASK(8:8) ++ #define PIU_SPI_RESET BITS(8:8, 1) ++ #define PIU_SPI_NOTRESET BITS(8:8, 0) ++ #define PSCS_DISABLE_MASK BMASK(0:0) ++ #define PSCS_INVERT_MASK BMASK(1:1) ++ #define PSCS_CLK_SEL_MASK BMASK(4:2) ++ #define PSCS_CLK_SEL_XTAL BITS(4:2, 0) ++ #define PSCS_CLK_SEL_27MHZ BITS(4:2, 1) ++ #define PSCS_CLK_SEL_36MHZ BITS(4:2, 2) ++ #define PSCS_CLK_SEL_43MHZ BITS(4:2, 3) ++ #define PSCS_CLK_SEL_54MHZ BITS(4:2, 4) ++ #define PSCS_CLK_SEL_72MHZ BITS(4:2, 5) ++ #define PSCS_CLK_SEL_86MHZ BITS(4:2, 6) ++ #define PSCS_CLK_SEL_108MHZ BITS(4:2, 7) ++ #define PSCS_CLK_SRC_SEL_MASK BMASK(5:5) ++ #define PSCS_CLK_SRC_SEL_XTAL BITS(5:5, 0) ++ #define PSCS_CLK_SRC_SEL_CLK BITS(5:5, 1) ++#define REG_PIU_DMA_SPISTART_L 0x70 // [15:0] ++#define REG_PIU_DMA_SPISTART_H 0x71 // [23:16] ++#define REG_PIU_DMA_DRAMSTART_L 0x72 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_DRAMSTART_H 0x73 // [23:16] ++#define REG_PIU_DMA_SIZE_L 0x74 // [15:0] in unit of B; must be 8B aligned ++#define REG_PIU_DMA_SIZE_H 0x75 // [23:16] ++#define REG_PIU_DMA_CMD 0x76 ++ #define PIU_DMA_CMD_FIRE 0x0001 ++ #define PIU_DMA_CMD_LE 0x0000 ++ #define PIU_DMA_CMD_BE 0x0020 ++ ++// Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++ #define SF_SR_SRWD BITS(7:7, 1) ++ #define SF_SR_QUALD BITS(6:6, 1) ++ ++// PM_SLEEP CMD. ++#define REG_PM_CKG_SPI 0x20 // Ref spec. before using these setting. ++ #define PM_SPI_CLK_SEL_MASK BMASK(13:10) ++ #define PM_SPI_CLK_XTALI BITS(13:10, 0) ++ #define PM_SPI_CLK_54MHZ BITS(13:10, 4) ++ #define PM_SPI_CLK_86MHZ BITS(13:10, 6) ++ #define PM_SPI_CLK_108MHZ BITS(13:10, 7) ++ #define PM_SPI_CLK_SWITCH_MASK BMASK(14:14) ++ #define PM_SPI_CLK_SWITCH_OFF BITS(14:14, 0) ++ #define PM_SPI_CLK_SWITCH_ON BITS(14:14, 1) ++ ++#define REG_PM_SPI_WPN 0x01 ++ #define PM_SPI_WPN_SWITCH_MASK BMASK(0:0) ++ #define PM_SPI_WPN_SWITCH_OUT BITS(0:0, 0) ++ #define PM_SPI_WPN_SWITCH_IN BITS(0:0, 1) ++ #define PM_SPI_WPN_OUT_DAT_MASK BMASK(1:1) ++ #define PM_SPI_WPN_OUT_HIGH BITS(1:1, 1) ++ #define PM_SPI_WPN_OUT_LOW BITS(1:1, 0) ++ ++ ++#define REG_PM_CHK_51MODE 0x53 ++ #define PM_51_ON_SPI BITS(0:0, 0x1) ++ #define PM_51_ONT_ON_SPI BITS(0:0, 0x0) ++// For Power Consumption ++ ++#define REG_PM_GPIO_SPICZ_OEN 0x17 ++#define REG_PM_GPIO_SPICK_OEN 0x18 ++#define REG_PM_GPIO_SPIDI_OEN 0x19 ++#define REG_PM_GPIO_SPIDO_OEN 0x1A ++#define REG_PM_SPI_IS_GPIO 0x35 ++#define PM_SPI_GPIO_MASK BMASK(3:0) ++#define PM_SPI_IS_GPIO BITS(3:0, 0xF) ++#define PM_SPI_NOT_GPIO BITS(3:0, 0x0) ++#define PM_SPI_HOLD_GPIO_MASK BMASK(14:14) ++#define PM_SPI_HOLD_IS_GPIO BITS(14:14, 1) ++#define PM_SPI_HOLD_NOT_GPIO BITS(14:14, 0) ++#define PM_SPI_WP_GPIO_MASK BMASK(7:7) ++#define PM_SPI_WP_IS_GPIO BITS(7:7, 1) ++#define PM_SPI_WP_NOT_GPIO BITS(7:7, 0) ++ ++#define REG_PM_GPIO_WPN 0x01 ++#define REG_PM_GPIO_HOLD 0x02 ++#define PM_SPI_GPIO_OEN_MASK BMASK(0:0) ++#define PM_SPI_GPIO_OEN_EN BITS(0:0, 0) ++#define PM_SPI_GPIO_OEN_DIS BITS(0:0, 1) ++#define PM_SPI_GPIO_HIGH_MASK BMASK(1:1) ++#define PM_SPI_GPIO_HIGH BITS(1:1, 1) ++ ++// CLK_GEN0 ++#define REG_CLK0_CKG_SPI 0x16 ++#define CLK0_CKG_SPI_MASK BMASK(4:2) ++#define CLK0_CKG_SPI_XTALI BITS(4:2, 0) ++#define CLK0_CKG_SPI_54MHZ BITS(4:2, 4) ++#define CLK0_CKG_SPI_86MHZ BITS(4:2, 6) ++#define CLK0_CKG_SPI_108MHZ BITS(4:2, 7) ++#define CLK0_CLK_SWITCH_MASK BMASK(5:5) ++#define CLK0_CLK_SWITCH_OFF BITS(5:5, 0) ++#define CLK0_CLK_SWITCH_ON BITS(5:5, 1) ++ ++// please refer to the serial flash datasheet ++#define SPI_CMD_READ (0x03) ++#define SPI_CMD_FASTREAD (0x0B) ++#define SPI_CMD_RDID (0x9F) ++#define SPI_CMD_WREN (0x06) ++#define SPI_CMD_WRDI (0x04) ++#define SPI_CMD_SE (0x20) ++#define SPI_CMD_32BE (0x52) ++#define SPI_CMD_64BE (0xD8) ++#define SPI_CMD_CE (0xC7) ++#define SPI_CMD_PP (0x02) ++#define SPI_CMD_RDSR (0x05) ++#define SPI_CMD_RDSR2 (0x15) ++// support for new WinBond Flash ++#define SPI_CMD_WRSR (0x01) ++#define SPI_CMD_QPI (0x35) ++#define SPI_CMD_QPI_RST (0xF5) ++#define SPI_WRIET_BUSY (0x01) ++ // support for 256Mb up MIX flash ++#define SPI_CMD_WREAR (0xC5) ++ ++ // FSP Register ++#define REG_FSP_WDB0 0x60 ++#define REG_FSP_WDB0_MASK BMASK(7:0) ++#define REG_FSP_WDB0_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB1 0x60 ++#define REG_FSP_WDB1_MASK BMASK(15:8) ++#define REG_FSP_WDB1_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB2 0x61 ++#define REG_FSP_WDB2_MASK BMASK(7:0) ++#define REG_FSP_WDB2_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB3 0x61 ++#define REG_FSP_WDB3_MASK BMASK(15:8) ++#define REG_FSP_WDB3_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB4 0x62 ++#define REG_FSP_WDB4_MASK BMASK(7:0) ++#define REG_FSP_WDB4_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB5 0x62 ++#define REG_FSP_WDB5_MASK BMASK(15:8) ++#define REG_FSP_WDB5_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB6 0x63 ++#define REG_FSP_WDB6_MASK BMASK(7:0) ++#define REG_FSP_WDB6_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB7 0x63 ++#define REG_FSP_WDB7_MASK BMASK(15:8) ++#define REG_FSP_WDB7_DATA(d) BITS(15:8, d) ++#define REG_FSP_WDB8 0x64 ++#define REG_FSP_WDB8_MASK BMASK(7:0) ++#define REG_FSP_WDB8_DATA(d) BITS(7:0, d) ++#define REG_FSP_WDB9 0x64 ++#define REG_FSP_WDB9_MASK BMASK(15:8) ++#define REG_FSP_WDB9_DATA(d) BITS(15:8, d) ++#define REG_FSP_RDB0 0x65 ++#define REG_FSP_RDB1 0x65 ++#define REG_FSP_RDB2 0x66 ++#define REG_FSP_RDB3 0x66 ++#define REG_FSP_RDB4 0x67 ++#define REG_FSP_RDB5 0x67 ++#define REG_FSP_RDB6 0x68 ++#define REG_FSP_RDB7 0x68 ++#define REG_FSP_RDB8 0x69 ++#define REG_FSP_RDB9 0x69 ++ ++#define FSP_OFFSET 0x60 ++#define REG_FSP_WD0 (FSP_OFFSET+0x00) ++#define REG_FSP_WD0_MASK BMASK(7:0) ++ #define FSP_WD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD1 (FSP_OFFSET+0x00) ++#define REG_FSP_WD1_MASK BMASK(15:8) ++ #define FSP_WD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD2 (FSP_OFFSET+0x01) ++#define REG_FSP_WD2_MASK BMASK(7:0) ++ #define FSP_WD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD3 (FSP_OFFSET+0x01) ++#define REG_FSP_WD3_MASK BMASK(15:8) ++ #define FSP_WD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD4 (FSP_OFFSET+0x02) ++#define REG_FSP_WD4_MASK BMASK(7:0) ++ #define FSP_WD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD5 (FSP_OFFSET+0x02) ++#define REG_FSP_WD5_MASK BMASK(15:8) ++ #define FSP_WD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD6 (FSP_OFFSET+0x03) ++#define REG_FSP_WD6_MASK BMASK(7:0) ++ #define FSP_WD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD7 (FSP_OFFSET+0x03) ++#define REG_FSP_WD7_MASK BMASK(15:8) ++ #define FSP_WD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_WD8 (FSP_OFFSET+0x04) ++#define REG_FSP_WD8_MASK BMASK(7:0) ++ #define FSP_WD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_WD9 (FSP_OFFSET+0x04) ++#define REG_FSP_WD9_MASK BMASK(15:8) ++ #define FSP_WD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_RD0 (FSP_OFFSET+0x05) ++#define REG_FSP_RD0_MASK BMASK(7:0) ++ #define FSP_RD0(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD1 (FSP_OFFSET+0x05) ++#define REG_FSP_RD1_MASK BMASK(15:8) ++ #define FSP_RD1(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD2 (FSP_OFFSET+0x06) ++#define REG_FSP_RD2_MASK BMASK(7:0) ++ #define FSP_RD2(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD3 (FSP_OFFSET+0x06) ++#define REG_FSP_RD3_MASK BMASK(15:8) ++ #define FSP_RD3(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD4 (FSP_OFFSET+0x07) ++#define REG_FSP_RD4_MASK BMASK(7:0) ++ #define FSP_RD4(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD5 (FSP_OFFSET+0x07) ++#define REG_FSP_RD5_MASK BMASK(15:8) ++ #define FSP_RD5(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD6 (FSP_OFFSET+0x08) ++#define REG_FSP_RD6_MASK BMASK(7:0) ++ #define FSP_RD6(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD7 (FSP_OFFSET+0x08) ++#define REG_FSP_RD7_MASK BMASK(15:8) ++ #define FSP_RD7(byte) BITS(15:8,(byte)) ++#define REG_FSP_RD8 (FSP_OFFSET+0x09) ++#define REG_FSP_RD8_MASK BMASK(7:0) ++ #define FSP_RD8(byte) BITS(7:0,(byte)) ++#define REG_FSP_RD9 (FSP_OFFSET+0x09) ++#define REG_FSP_RD9_MASK BMASK(15:8) ++ #define FSP_RD9(byte) BITS(15:8,(byte)) ++ ++#define REG_FSP_WBF_SIZE 0x6a ++#define REG_FSP_WBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_WBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_WBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_WBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_WBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_WBF_SIZE2(s) BITS(11:8,s) ++#define REG_FSP_RBF_SIZE 0x6b ++#define REG_FSP_RBF_SIZE0_MASK BMASK(3:0) ++#define REG_FSP_RBF_SIZE0(s) BITS(3:0,s) ++#define REG_FSP_RBF_SIZE1_MASK BMASK(7:4) ++#define REG_FSP_RBF_SIZE1(s) BITS(7:4,s) ++#define REG_FSP_RBF_SIZE2_MASK BMASK(11:8) ++#define REG_FSP_RBF_SIZE2(s) BITS(11:8,s) ++ ++#define REG_FSP_CTRL 0x6c ++#define REG_FSP_ENABLE_MASK BMASK(0:0) ++#define REG_FSP_ENABLE BITS(0:0,1) ++#define REG_FSP_DISABLE BITS(0:0,0) ++#define REG_FSP_RESET_MASK BMASK(1:1) ++#define REG_FSP_RESET BITS(1:1,0) ++#define REG_FSP_NRESET BITS(1:1,1) ++#define REG_FSP_INT_MASK BMASK(2:2) ++#define REG_FSP_INT BITS(2:2,1) ++#define REG_FSP_INT_OFF BITS(2:2,0) ++#define REG_FSP_CHK_MASK BMASK(3:3) ++#define REG_FSP_CHK BITS(3:3,1) ++#define REG_FSP_CHK_OFF BITS(3:3,0) ++#define REG_FSP_RDSR_MASK BMASK(12:11) ++#define REG_FSP_1STCMD BITS(12:11,0) ++#define REG_FSP_2NDCMD BITS(12:11,1) ++#define REG_FSP_3THCMD BITS(12:11,2) ++#define REG_FSP_FSCHK_MASK BMASK(13:13) ++#define REG_FSP_FSCHK_ON BITS(13:13,1) ++#define REG_FSP_FSCHK_OFF BITS(13:13,0) ++#define REG_FSP_3THCMD_MASK BMASK(14:14) ++#define REG_FSP_3THCMD_ON BITS(14:14,1) ++#define REG_FSP_3THCMD_OFF BITS(14:14,0) ++#define REG_FSP_2NDCMD_MASK BMASK(15:15) ++#define REG_FSP_2NDCMD_ON BITS(15:15,1) ++#define REG_FSP_2NDCMD_OFF BITS(15:15,0) ++#define REG_FSP_TRIGGER 0x6d ++#define REG_FSP_TRIGGER_MASK BMASK(0:0) ++#define REG_FSP_FIRE BITS(0:0,1) ++#define REG_FSP_DONE_FLAG 0x6e ++#define REG_FSP_DONE_FLAG_MASK BMASK(0:0) ++#define REG_FSP_DONE BITS(0:0,1) ++#define REG_FSP_DONE_CLR 0x6f ++#define REG_FSP_DONE_CLR_MASK BMASK(0:0) ++#define REG_FSP_CLR BITS(0:0,1) ++ ++#define REG_FSP_WBF_SIZE_OUTSIDE 0x78 ++#define REG_FSP_WBF_OUTSIDE 0x79 ++#define REG_FSP_WBF_REPLACED_MASK BMASK(7:0) ++#define REG_FSP_WBF_REPLACED(s) BITS(7:0,s) ++#define REG_FSP_WBF_MODE_MASK BMASK(11:8) ++#define REG_FSP_WBF_MODE(s) BITS(11:8,s) ++#define REG_FSP_WBF_OUTSIDE_ENABLE_MASK BMASK(12:12) ++#define REG_FSP_WBF_OUTSIDE_ENABLE BITS(12:12,1) ++#define REG_FSP_WBF_OUTSIDE_DISABLE BITS(12:12,0) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_MASK BMASK(13:13) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_ENABLE BITS(13:13,1) ++#define REG_FSP_WBF_OUTSIDE_TXTIMEOUT_DISABLE BITS(13:13,0) ++#define REG_FSP_WBF_OUTSIDE_SRC_MASK BMASK(15:14) ++#define REG_FSP_WBF_OUTSIDE_SRC(s) BITS(15:14,s) ++ ++ ++ ++ ++ // Serial Flash Register // please refer to the serial flash datasheet ++#define SF_SR_WIP_MASK BMASK(0:0) ++#define SF_SR_WEL_MASK BMASK(1:1) ++#define SF_SR_BP_MASK BMASK(5:2) ++ // BMASK(4:2) is normal case but SERFLASH_TYPE_MX25L6405 use BMASK(5:2) ++#define SF_SR_PROG_ERASE_ERR_MASK BMASK(6:6) ++#define SF_SR_SRWD_MASK BMASK(7:7) ++#define SF_SR_SRWD BITS(7:7, 1) ++#define REG_FSP_WRITEDATA_SIZE 0x4 ++#define REG_FSP_MAX_WRITEDATA_SIZE 0xA ++#define REG_FSP_READDATA_SIZE 0xA ++#define FLASH_PAGE_SIZE 256 ++#define FLASH_OIP 1 ++ ++ ++ ++//QSPI ++#define REG_SPI_BURST_WRITE 0x0A ++#define REG_SPI_DISABLE_BURST 0x02 ++#define REG_SPI_ENABLE_BURST 0x01 ++ ++ ++#endif // _REG_SERFLASH_H_ +diff --git a/drivers/mstar/flash_isp/mtd_serflash.c b/drivers/mstar/flash_isp/mtd_serflash.c +new file mode 100644 +index 00000000..4605efb1 +--- /dev/null ++++ b/drivers/mstar/flash_isp/mtd_serflash.c +@@ -0,0 +1,750 @@ ++//********************************************************************* ++// ++// MODULE NAME: ++// mtd_serflash.c ++// ++// DESCRIPTION: ++// This file is an agent between mtd layer and spi flash driver ++// ++// PUBLIC PROCEDURES: ++// Name Title ++// ----------------------- -------------------------------------- ++// int xxx_proc declare in its corresponding header file ++// ++// LOCAL PROCEDURES: ++// Name Title ++// ----------------------- -------------------------------------- ++// get_prnt_cnvs the local procedure in the file ++// ++// Written by Tao.Zhou@MSTAR Inc. ++//--------------------------------------------------------------------- ++// ++//******************************************************************** ++//-------------------------------------------------------------------- ++// GENERAL INCLUDE ++//-------------------------------------------------------------------- ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++#include ++#endif ++#include "drvSERFLASH.h" ++#include "drvDeviceInfo.h" ++#ifdef CONFIG_MS_FLASH_ISP_MXP_PARTS ++#include "part_mxp.h" ++#endif ++#include ++#include ++#include ++#include ++#include //for reading strapping ++ ++#define CONFIG_DISABLE_WRITE_PROTECT ++#define CONFIG_MTD_PARTITIONS ++ ++/* Flash opcodes. */ ++#define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ ++#define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ ++//#define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ ++#define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ ++#define OPCODE_RDID 0x9f /* Read JEDEC ID */ ++ ++/* Define max times to check status register before we give up. */ ++#define MAX_READY_WAIT_COUNT 100000 ++#define CMD_SIZE 4 ++ ++//#ifdef CONFIG_MTD_PARTITIONS ++#define mtd_has_partitions() (1) ++//#else ++//#define mtd_has_partitions() (0) ++//#endif ++ ++//#define DEBUG(x...) printk(x...) ++ ++extern int parse_mtd_partitions(struct mtd_info *master, const char *const *types, ++ struct mtd_partition **pparts, ++ struct mtd_part_parser_data *data); ++ ++/****************************************************************************/ ++ ++struct serflash ++{ ++ struct mutex lock; ++ struct mtd_info mtd; ++ unsigned partitioned:1; ++ u8 erase_opcode; ++}; ++ ++static inline struct serflash *mtd_to_serflash(struct mtd_info *mtd) ++{ ++ return container_of(mtd, struct serflash, mtd); ++} ++ ++/* Erase flash fully or part of it */ ++static int serflash_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ ++ struct serflash *flash = mtd_to_serflash(mtd); ++ uint64_t addr_temp, len_temp; ++ ++ //printk(KERN_WARNING"%s: addr 0x%08x, len %ld\n", __func__, (u32)instr->addr, (long int)instr->len); ++ ++ /* sanity checks */ ++ if (!instr->len) ++ return 0; ++ ++ /* range and alignment check */ ++ if (instr->addr + instr->len > mtd->size) ++ return -EINVAL; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ /* mod = do_div(x,y); ++ result = x; */ ++ addr_temp = instr->addr; ++ len_temp = instr->len; ++ if ((do_div(addr_temp , mtd->erasesize) != 0) ||(do_div(len_temp, mtd->erasesize) != 0)) ++ { ++ return -EINVAL; ++ } ++#else ++ if ((instr->addr % mtd->erasesize) != 0 || (instr->len % mtd->erasesize) != 0) ++ return -EINVAL; ++#endif ++ ++ mutex_lock(&flash->lock); ++ ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ /*write protect false before erase*/ ++ if (!MDrv_SERFLASH_WriteProtect(0)) ++ { ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++#endif ++ /* erase the whole chip */ ++ if (instr->len == mtd->size && !MDrv_SERFLASH_EraseChip()) ++ { ++ instr->state = MTD_ERASE_FAILED; ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ else if (!MDrv_SERFLASH_AddressErase(instr->addr, instr->len, 1)) ++ { ++ instr->state = MTD_ERASE_FAILED; ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ ++ instr->state = MTD_ERASE_DONE; ++ ++ mtd_erase_callback(instr); ++ ++ return 0; ++} ++ ++/* ++ * Read an address range from the flash chip. The address range ++ * may be any size provided it is within the physical boundaries. ++ */ ++static int serflash_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct serflash *flash = mtd_to_serflash(mtd); ++ ++ //printk(KERN_WARNING "%s %s 0x%08x, len %zd\n", __func__, "from", (u32)from, len); ++ ++ /* sanity checks */ ++ if (!len) ++ return 0; ++ ++ if (from + len > flash->mtd.size) ++ return -EINVAL; ++ ++ mutex_lock(&flash->lock); ++ ++#if 0 ++ /* Wait till previous write/erase is done. */ ++ if (wait_till_ready(flash)) ++ { ++ /* REVISIT status return?? */ ++ mutex_unlock(&flash->lock); ++ return 1; ++ } ++#endif ++ ++ if (MDrv_SERFLASH_Read(from, len, (unsigned char *)buf)) ++ { ++ *retlen = len; ++ } ++ else ++ { ++ *retlen = 0; ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ ++ mutex_unlock(&flash->lock); ++ ++ return 0; ++} ++ ++/* ++ * Write an address range to the flash chip. Data must be written in ++ * FLASH_PAGESIZE chunks. The address range may be any size provided ++ * it is within the physical boundaries. ++ */ ++static int serflash_write(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct serflash *flash = mtd_to_serflash(mtd); ++ ++ //printk(KERN_WARNING "%s %s 0x%08x, len %zd\n",__func__, "to", (u32)to, len); ++ ++ if (retlen) ++ *retlen = 0; ++ ++ /* sanity checks */ ++ if (!len) ++ return(0); ++ ++ if (to + len > flash->mtd.size) ++ return -EINVAL; ++ ++ mutex_lock(&flash->lock); ++ ++#if 0 ++ /* Wait until finished previous write command. */ ++ if (wait_till_ready(flash)) ++ { ++ mutex_unlock(&flash->lock); ++ return 1; ++ } ++#endif ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ ++ if (!MDrv_SERFLASH_WriteProtect(0)) ++ { ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++#endif ++//modified by daniel.lee 2010/0514 ++ /* ++ if (!MDrv_SERFLASH_BlockErase(erase_start, erase_end, TRUE)) ++ { ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++ */ ++ if (MDrv_SERFLASH_Write(to, len, (unsigned char *)buf)) ++ { ++ if (retlen) ++ *retlen = len; ++ } ++ else ++ { ++ if (retlen) ++ *retlen = 0; ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ return -EIO; ++ } ++#ifndef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(1); ++#endif ++ mutex_unlock(&flash->lock); ++ ++ return 0; ++} ++ ++ ++ ++#define MSTAR_SERFLASH_SIZE (8 * 1024 * 1024) ++ ++ ++#define SERFLASH_PART_PARTITION_0_OFFSET 0 ++#define SERFLASH_PART_PARTITION_0_SIZE (32+512+32) * 1024 ++ ++#define SERFLASH_PART_PARTITION_1_OFFSET (SERFLASH_PART_PARTITION_0_OFFSET + SERFLASH_PART_PARTITION_0_SIZE) ++#define SERFLASH_PART_PARTITION_1_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_PARTITION_2_OFFSET (SERFLASH_PART_PARTITION_1_OFFSET + SERFLASH_PART_PARTITION_1_SIZE) ++#define SERFLASH_PART_PARTITION_2_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_PARTITION_3_OFFSET (SERFLASH_PART_PARTITION_2_OFFSET + SERFLASH_PART_PARTITION_2_SIZE) ++#define SERFLASH_PART_PARTITION_3_SIZE MSTAR_SERFLASH_SIZE - SERFLASH_PART_PARTITION_3_OFFSET ++ ++#if 0 ++#define SERFLASH_PART_PARTITION_TBL_OFFSET 0 ++#define SERFLASH_PART_PARTITION_TBL_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_LINUX_BOOT_PARAM_OFFSET (SERFLASH_PART_PARTITION_TBL_OFFSET + SERFLASH_PART_PARTITION_TBL_SIZE) ++#define SERFLASH_PART_LINUX_BOOT_PARAM_SIZE 512 * 1024 ++ ++#define SERFLASH_PART_KERNEL_OFFSET (SERFLASH_PART_LINUX_BOOT_PARAM_OFFSET + SERFLASH_PART_LINUX_BOOT_PARAM_SIZE) ++#define SERFLASH_PART_KERNEL_SIZE 1536 * 1024 ++ ++#define SERFLASH_PART_ROOTFS_OFFSET (SERFLASH_PART_KERNEL_OFFSET + SERFLASH_PART_KERNEL_SIZE) ++#define SERFLASH_PART_ROOTFS_SIZE 2560 * 1024 ++ ++#define SERFLASH_PART_CONF_OFFSET (SERFLASH_PART_ROOTFS_OFFSET + SERFLASH_PART_ROOTFS_SIZE) ++#define SERFLASH_PART_CONF_SIZE 64 * 1024 ++ ++ ++#define SERFLASH_PART_CHAKRA_BOOT_PARAM_OFFSET (NAND_PART_KERNEL_OFFSET + NAND_PART_KERNEL_SIZE) ++#define SERFLASH_PART_CHAKRA_BOOT_PARAM_SIZE SZ_512KB ++ ++#define SERFLASH_PART_CHAKRA_BIN_OFFSET (NAND_PART_CHAKRA_BOOT_PARAM_OFFSET + NAND_PART_CHAKRA_BOOT_PARAM_SIZE) ++#define SERFLASH_PART_CHAKRA_BIN_PARAM_SIZE SZ_8MB ++ ++#define SERFLASH_PART_SUBSYSTEM_OFFSET (NAND_PART_CONF_OFFSET + NAND_PART_CONF_SIZE) ++#define SERFLASH_PART_SUBSYSTEM_SIZE SZ_2MB ++ ++#define SERFLASH_PART_FONT_OFFSET (NAND_PART_SUBSYSTEM_OFFSET + NAND_PART_SUBSYSTEM_SIZE) ++#define SERFLASH_PART_FONT_SIZE SZ_4MB ++ ++#define SERFLASH_PART_OPT_OFFSET (NAND_PART_FONT_OFFSET + NAND_PART_FONT_SIZE) ++#define SERFLASH_PART_OPT_SIZE SZ_8MB ++ ++#define SERFLASH_PART_APPLICATION_OFFSET (NAND_PART_OPT_OFFSET + NAND_PART_OPT_SIZE) ++#define SERFLASH_PART_APPLICATION_SIZE (MSTAR_NAND_SIZE - NAND_PART_APPLICATION_OFFSET) ++#endif ++// ++//#if ( (NAND_PART_APPLICATION_OFFSET) >= MSTAR_SERFLASH_SIZE) ++// #error "Error: NAND partition is not correct!!!" ++//#endif ++ ++static const struct mtd_partition serflash_partition_info[] = ++{ ++ ++ { ++ .name = "DATA",//"boot", ++ .offset = 0x00300000,//SERFLASH_PART_PARTITION_0_OFFSET, ++ .size = 0x00080000,//SERFLASH_PART_PARTITION_0_SIZE ++ .mask_flags = 0 ++ }, ++ { ++ .name = "SYSTEM",//"boot", ++ .offset = 0x00380000,//SERFLASH_PART_PARTITION_0_OFFSET, ++ .size = 0x00400000,//SERFLASH_PART_PARTITION_0_SIZE ++ .mask_flags = 0 ++ }, ++ { ++ .name = "EXT",//"boot", ++ .offset = 0x00780000,//SERFLASH_PART_PARTITION_0_OFFSET, ++ .size = 0x00880000,//SERFLASH_PART_PARTITION_0_SIZE ++ .mask_flags = 0 ++ }, ++ ++}; ++ ++#define SERFLASH_NUM_PARTITIONS ARRAY_SIZE(serflash_partition_info) ++ ++ ++extern int mxp_init_nor_flash(void); ++extern hal_SERFLASH_t _hal_SERFLASH; ++extern MS_BOOL bDetect; ++extern MS_BOOL gQuadSupport; ++ ++/* ++ * board specific setup should have ensured the SPI clock used here ++ * matches what the READ command supports, at least until this driver ++ * understands FAST_READ (for clocks over 25 MHz). ++ */ ++static int serflash_probe(struct platform_device *pdev) ++{ ++ struct serflash *flash; ++ int num_parents, i; ++ struct clk **spi_clks; ++ MS_U32 u32Val; ++ u32 u32Ret; ++ ++ if(Chip_Get_Storage_Type()!= MS_STORAGE_NOR) ++ return 0; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_probe] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_prepare_enable(spi_clks[i]); ++ } ++ } ++ kfree(spi_clks); ++ } ++ ++ if(!of_property_read_u32(pdev->dev.of_node, "quadread", (u32 *)&u32Val)) ++ { ++ gQuadSupport = u32Val; ++ }else{ ++ gQuadSupport = 0; ++ //printk( "[serflash_probe] not search quadread on DTS\n" ); ++ } ++ ++ //if(gQuadSupport) ++ //printk( "[serflash_probe] DTS support Quad Read\n" ); ++ ++ // jedec_probe() will read id, so initialize hardware first ++ MDrv_SERFLASH_Init(); ++ ++ /* Platform data helps sort out which chip type we have, as ++ * well as how this board partitions it. If we don't have ++ * a chip ID, try the JEDEC id commands; they'll work for most ++ * newer chips, even if we don't recognize the particular chip. ++ */ ++ ++ //bDetect is the global variable from halserflash.c ++ if(bDetect == FALSE) ++ { ++ printk(KERN_WARNING"[FSP] found no flash_info!!"); ++ return -ENODEV; ++ } ++ ++ ++ flash = kzalloc(sizeof *flash, GFP_KERNEL); ++ if (!flash) ++ return -ENOMEM; ++ ++ mutex_init(&flash->lock); ++ ++ flash->mtd.priv = flash; ++ flash->mtd.name ="NOR_FLASH"; ++ flash->mtd.type = MTD_NORFLASH; ++ flash->mtd.writesize = 1; ++ flash->mtd.writebufsize = flash->mtd.writesize; ++ flash->mtd.flags = MTD_CAP_NORFLASH; ++ MDrv_SERFLASH_DetectSize(&u32Val); ++ flash->mtd.size = u32Val; ++ flash->mtd._erase = serflash_erase; ++ flash->mtd._read = serflash_read; ++ flash->mtd._write = serflash_write; ++ flash->erase_opcode = OPCODE_SE; ++ flash->mtd.erasesize = (_hal_SERFLASH.u32SecSize); ++ ++ ++#ifdef CONFIG_DISABLE_WRITE_PROTECT ++ MDrv_SERFLASH_WriteProtect(0); ++#endif ++ ++ //dev_info(&spi->dev, "%s (%d Kbytes)\n", info->name, ++ //flash->mtd.size / 1024); ++ ++ printk(KERN_WARNING ++ "mtd .name = %s, .size = 0x%.8x (%uMiB)\n" ++ " .erasesize = 0x%.8x .numeraseregions = %d\n", ++ flash->mtd.name, ++ (unsigned int)flash->mtd.size, (unsigned int)flash->mtd.size / (1024*1024), ++ (unsigned int)flash->mtd.erasesize, ++ flash->mtd.numeraseregions); ++ ++ if (flash->mtd.numeraseregions) ++ for (i = 0; i < flash->mtd.numeraseregions; i++) ++ printk(KERN_WARNING ++ "mtd.eraseregions[%d] = { .offset = 0x%.8x, " ++ ".erasesize = 0x%.8x (%uKiB), " ++ ".numblocks = %d }\n", ++ i, (u32)flash->mtd.eraseregions[i].offset, ++ (unsigned int)flash->mtd.eraseregions[i].erasesize, ++ flash->mtd.eraseregions[i].erasesize / 1024, ++ (unsigned int)flash->mtd.eraseregions[i].numblocks); ++ ++ ++ /* partitions should match sector boundaries; and it may be good to ++ * use readonly partitions for writeprotected sectors (BP2..BP0). ++ */ ++ if (mtd_has_partitions()) ++ { ++ struct mtd_partition *parts = NULL; ++ int nr_parts = 0; ++#ifdef CONFIG_MTD_CMDLINE_PARTS ++ static const char *part_probes[] = { "cmdlinepart", NULL, }; ++#endif ++ ++#ifdef CONFIG_MS_FLASH_ISP_MXP_PARTS ++ printk(KERN_WARNING"MXP_PARTS!!\n"); ++ if(mxp_init_nor_flash()>=0) ++ { ++ int j=0; ++ nr_parts=mxp_get_total_record_count(); ++ parts=kmalloc(sizeof(struct mtd_partition)*nr_parts,GFP_KERNEL); ++ if(NULL==parts)BUG(); ++ ++ for(i=0; ipartitioned = 1; ++ if(j>0) ++ { ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ u32Ret = mtd_device_register(&flash->mtd, parts, j); ++#else ++ u32Ret = add_mtd_partitions(&flash->mtd, parts, j); ++#endif ++ if(!u32Ret)//success ++ { ++ kfree(parts); ++ return u32Ret; ++ } ++ } ++ kfree(parts); ++ parts = NULL; ++ } ++ printk(KERN_WARNING"MXP NOT FOUND!!\n"); ++#endif //end CONFIG_MS_FLASH_ISP_MXP_PARTS ++ ++ ++#ifdef CONFIG_MTD_CMDLINE_PARTS ++ nr_parts = parse_mtd_partitions(&flash->mtd,part_probes, &parts, 0); ++#endif ++ ++ if (nr_parts > 0) ++ { ++ for (i = 0; i < nr_parts; i++) ++ { ++ printk(KERN_WARNING "partitions[%d] = " ++ "{.name = %s, .offset = 0x%.8x, " ++ ".size = 0x%.8x (%uKiB) }\n", ++ i, parts[i].name, ++ (unsigned int)(parts[i].offset), ++ (unsigned int)(parts[i].size), ++ (unsigned int)(parts[i].size / 1024)); ++ } ++ flash->partitioned = 1; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ u32Ret = mtd_device_register(&flash->mtd, parts, nr_parts); ++#else ++ u32Ret = add_mtd_partitions(&flash->mtd, parts, nr_parts); ++#endif ++ } ++ else ++ { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ u32Ret = mtd_device_register(&flash->mtd, serflash_partition_info, SERFLASH_NUM_PARTITIONS); ++#else ++ u32Ret = add_mtd_partitions(&flash->mtd, serflash_partition_info, SERFLASH_NUM_PARTITIONS); ++#endif ++ } ++ if(!u32Ret) //success ++ { ++ return u32Ret; ++ } ++ ++ } ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++ return mtd_device_register(&flash->mtd, NULL, NULL); ++#else ++ return add_mtd_device(&flash->mtd) == 1 ? -ENODEV : 0; ++#endif ++} ++ ++ ++static int serflash_cleanup(struct platform_device *pdev) ++{ ++#if 0 ++ struct serflash *flash = mtd->priv; ++ int status; ++ ++ /* Clean up MTD stuff. */ ++ if (mtd_has_partitions() && flash->partitioned) ++ status = del_mtd_partitions(&flash->mtd); ++ else ++ status = del_mtd_device(&flash->mtd); ++ if (status == 0) ++ kfree(flash); ++#endif ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **spi_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_cleanup] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_disable_unprepare(spi_clks[i]); ++ } ++ } ++ kfree(spi_clks); ++ } ++#endif ++ return 0; ++} ++ ++#if defined (CONFIG_OF) ++static struct of_device_id flashisp_of_device_ids[] = { ++ {.compatible = "mtd-flashisp"}, ++ {}, ++}; ++#endif ++ ++#ifdef CONFIG_PM ++static int serflash_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **spi_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_suspend] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_disable_unprepare(spi_clks[i]); ++ } ++ } ++ kfree(spi_clks); ++ } ++#endif ++ return 0; ++} ++ ++static int serflash_resume(struct platform_device *pdev) ++{ ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **spi_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents) ++ { ++ spi_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(spi_clks==NULL) ++ { ++ printk( "[serflash_probe] kzalloc Fail!\n" ); ++ return -1; ++ } ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ spi_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(spi_clks[i])) ++ { ++ printk( "[serflash_cleanup] Fail to get clk!\n" ); ++ kfree(spi_clks); ++ return -1; ++ } ++ else ++ { ++ clk_prepare_enable(spi_clks[i]); ++ } ++ } ++ kfree(spi_clks); ++ } ++#endif ++ return 0; ++} ++#endif ++ ++static struct platform_driver platram_driver = { ++ .probe = serflash_probe, ++ .remove = serflash_cleanup, ++#ifdef CONFIG_PM ++ .suspend = serflash_suspend, ++ .resume = serflash_resume, ++#endif ++ .driver = { ++ .name = "mtd-flashisp", ++#if defined(CONFIG_OF) ++ .of_match_table = flashisp_of_device_ids, ++#endif ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++ ++module_platform_driver(platram_driver); ++ ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Tao.Zhou"); ++MODULE_DESCRIPTION("MTD Mstar driver for spi flash chips"); ++ +diff --git a/drivers/mstar/flash_isp/mxp_flash.c b/drivers/mstar/flash_isp/mxp_flash.c +new file mode 100644 +index 00000000..3f369861 +--- /dev/null ++++ b/drivers/mstar/flash_isp/mxp_flash.c +@@ -0,0 +1,132 @@ ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++#include ++#endif ++#include ++#include "part_mxp.h" ++#include "MsTypes.h" ++ ++ ++#ifdef CONFIG_MS_FLASH_ISP ++static mxp_manager* nor_flash_mxp=NULL; ++ ++//#define NOR_FLASH_MXP_TABLE_BASE 0x0020000 ++#define NOR_FLASH_MXP_TABLE_SIZE 0x1000 ++ ++extern MS_BOOL MDrv_SERFLASH_Read(MS_U32 u32FlashAddr, MS_U32 u32FlashSize, MS_U8 *user_buffer); ++ ++static int nor_flash_mxp_read_bytes(int offset,void* buf,int len) ++{ ++ ++ if (!MDrv_SERFLASH_Read(offset,len,buf)) ++ { ++ printk("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++ ++static int nor_flash_mxp_write_bytes(int offset,void* buf,int len) ++{ ++#if 0 ++ int ret; ++ ret = spi_flash_erase(norflash, NOR_FLASH_MXP_TABLE_BASE, NOR_FLASH_MXP_TABLE_SIZE); ++ if (ret) { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ return -1; ++ } ++ ++ ret = spi_flash_write(norflash, NOR_FLASH_MXP_TABLE_BASE+offset, len, buf); ++ if (ret) { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ return -1; ++ } ++#endif ++ return 0; ++} ++ ++static int nor_flash_mxp_update_byte(int offset, char byte) ++{ ++ int ret=-1; ++#if 0 ++ char b; ++ if(spi_flash_read(norflash, (NOR_FLASH_MXP_TABLE_BASE+offset), (size_t)1, &b)) ++ { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ goto DONE; ++ ++ } ++ ++ printf("[nor_flash_mxp_update_byte] 0x%08X: 0x%02X -> 0x%02X\n",(NOR_FLASH_MXP_TABLE_BASE+offset),b,byte); ++ if( (((char)(byte^b)) & (char)(~b)) >0 ) ++ { ++ printf(" using general page flash write\n"); ++ return nor_flash_mxp_write_bytes(offset,&byte,1); ++ } ++ ++ printf(" using single byte flash write\n"); ++ if(spi_flash_write(norflash, NOR_FLASH_MXP_TABLE_BASE+offset, 1, &byte)) { ++ printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ goto DONE; ++ } ++ ++ ret=0; ++ ++ ++DONE: ++#endif ++ ++ return ret; ++ ++} ++ ++int mxp_init_nor_flash(void) ++{ ++ int ret=-1; ++ //printk(KERN_WARNING"[mxp_init_nor_flash]\n"); ++ if(nor_flash_mxp==NULL) ++ { ++ nor_flash_mxp=kmalloc(sizeof(mxp_manager),GFP_KERNEL); ++ if(nor_flash_mxp==NULL) ++ { ++ printk(KERN_ERR "ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++ goto DONE; ++ } ++ ++ //printk(KERN_WARNING"nor_flash_mxp allocated success!!\n"); ++ ++ } ++ else ++ { ++ return 1; ++ } ++ ++// if(norflash==NULL) ++// { ++// norflash = spi_flash_probe(0, 0, 1000000, SPI_MODE_3); ++// if (!norflash) { ++// printf("ERROR!! [%s]: %d\n",__FUNCTION__,__LINE__); ++// goto DONE; ++// } ++// } ++ ++ nor_flash_mxp->read_table_bytes=nor_flash_mxp_read_bytes; ++ nor_flash_mxp->write_table_bytes=nor_flash_mxp_write_bytes; ++ nor_flash_mxp->update_table_byte=nor_flash_mxp_update_byte; ++ ++ if(0!=mxp_init(NOR_FLASH_MXP_TABLE_SIZE,nor_flash_mxp)) ++ { ++ printk(KERN_ERR "ERROR!! [%s] can't find mxp table\n",__FUNCTION__); ++ goto DONE; ++ } ++ ++ ret=0; ++DONE: ++ return ret; ++ ++} ++#endif ++ ++ +diff --git a/drivers/mstar/flash_isp/part_mxp.c b/drivers/mstar/flash_isp/part_mxp.c +new file mode 100644 +index 00000000..2fcd7c33 +--- /dev/null ++++ b/drivers/mstar/flash_isp/part_mxp.c +@@ -0,0 +1,303 @@ ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,39) ++#include ++#endif ++#include ++#include "part_mxp.h" ++ ++#define MXP_ALLOC(x) kmalloc(x,GFP_KERNEL) ++#define MXP_FREE(x) kfree(x) ++#define MXP_MSG(format,...) printk(format, ##__VA_ARGS__) ++ ++static int mxp_table_size=0; ++static int mxp_record_count=0; ++static mxp_manager* mxp; ++static mxp_record* mxp_parts=NULL; ++static const int mxp_offset[] = {0x3000/*12K*/, 0x20000/*128K*/, 0x40000/*256K*/, 0x80000/*512K*/}; ++int mxp_base; ++ ++static int chk_magic_seq(int seq) ++{ ++ ++ if( mxp_parts[seq].magic_prefix[0]=='M' && ++ mxp_parts[seq].magic_prefix[1]=='X' && ++ mxp_parts[seq].magic_prefix[2]=='P' && ++ mxp_parts[seq].magic_prefix[3]=='T' && ++ mxp_parts[seq].magic_suffix[0]=='T' && ++ mxp_parts[seq].magic_suffix[1]=='P' && ++ mxp_parts[seq].magic_suffix[2]=='X' && ++ mxp_parts[seq].magic_suffix[3]=='M' ) ++ { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++static void fill_init_record(mxp_record* rec) ++{ ++ rec->magic_prefix[0]='M'; ++ rec->magic_prefix[1]='X'; ++ rec->magic_prefix[2]='P'; ++ rec->magic_prefix[3]='T'; ++ rec->magic_suffix[0]='T'; ++ rec->magic_suffix[1]='P'; ++ rec->magic_suffix[2]='X'; ++ rec->magic_suffix[3]='M'; ++ rec->type=MXP_PART_TYPE_TAG; ++ rec->status=MXP_PART_STATUS_EMPTY; ++ rec->format=MXP_PART_FORMAT_NONE; ++ rec->version=1; ++ memset(rec->backup,0x00,sizeof(rec->backup)); ++ memset(rec->name,0x00,sizeof(rec->name)); ++ ++} ++ ++int mxp_init(int size,mxp_manager* manager) ++{ ++ int i=0,j=0; ++ mxp_table_size=size; ++ mxp=manager; ++ ++ if(mxp_parts!=NULL) ++ { ++ MXP_FREE(mxp_parts); ++ } ++ ++ mxp_parts=MXP_ALLOC(mxp_table_size); ++ if(!mxp_parts) ++ { ++ MXP_MSG("ERROR!! Failed to allocate memory with mxp_table_size:%d\n",mxp_table_size); ++ return -1; ++ } ++ ++ for(i=0; iread_table_bytes(mxp_base,mxp_parts,mxp_table_size); ++ ++ if(0==mxp_check_table_magic()) ++ { ++ MXP_MSG("MXP found at mxp_offset[%d]=0x%08X, size=0x%X\n", i, mxp_offset[i], mxp_table_size); ++ for(j=0; jwrite_table_bytes(mxp_base,mxp_parts,mxp_table_size); ++ ++} ++ ++ ++int mxp_get_total_record_count(void) ++{ ++ return mxp_record_count; ++} ++ ++int mxp_save_table(void) ++{ ++ return mxp->write_table_bytes(mxp_base,mxp_parts,mxp_table_size); ++} ++ ++// ++int mxp_save_table_from_mem(u32 mem_address) ++{ ++// mxp_record* recs=(mxp_record*)((void *)mem_address); ++ int count=(mxp_table_size/sizeof(mxp_record)); ++ if((0!=chk_magic_seq(0)) || (0!=chk_magic_seq(count-1))) ++ { ++ MXP_MSG("ERROR!! The head & tail record does not have correct magic word. mem_address=0x%08X!!\n",mem_address); ++ return -1; ++ } ++ return mxp->write_table_bytes(mxp_base,(void*)mem_address,mxp_table_size); ++} ++// ++// ++ ++ ++int mxp_set_record(mxp_record* part) ++{ ++// mxp_record found; ++ ++ int count=mxp_table_size/sizeof(mxp_record); ++ int index=mxp_get_record_index((char *)(part->name)); ++ if(-1==index) //not found ++ { ++ if(mxp_record_count < (count-1)) ++ { ++ index=mxp_record_count; ++ } ++ else ++ { ++ MXP_MSG("ERROR!! No vancacy to add new mxp:%s\n",part->name); ++ return -2; ++ } ++ } ++ ++ ++ MXP_MSG("set mxp:%s to index %d\n",part->name,index); ++ memcpy(&mxp_parts[index],part,sizeof(mxp_record)); ++ ++ ++ mxp_save_table(); ++ ++ return 0; ++ ++} ++ ++//0:success -1:error ++int mxp_get_record_by_index(int index,mxp_record* part) ++{ ++ ++ if(index>=mxp_record_count) ++ { ++ MXP_MSG("ERROR!! index:%d is out of bound:%d\n",index,mxp_record_count); ++ return -1; ++ } ++ memcpy(part,&mxp_parts[index],sizeof(mxp_record)); ++ return 0; ++ ++} ++ ++ ++int mxp_delete_record_by_index(int index) ++{ ++ ++ if(index>=mxp_record_count) ++ { ++ MXP_MSG("ERROR!! index:%d is out of bound:%d\n",index,mxp_record_count); ++ return -1; ++ } ++ memcpy(&mxp_parts[index],&mxp_parts[index+1],(mxp_table_size-sizeof(mxp_record)*(index+1))); ++ ++ mxp_record_count-=1; ++ return 0; ++ ++} ++ ++int mxp_set_record_status(int index,int status) ++{ ++ if(index>=mxp_record_count) ++ { ++ MXP_MSG("ERROR!! index:%d is out of bound:%d\n",index,mxp_record_count); ++ return -1; ++ } ++ mxp_parts[index].status=status; ++ mxp->update_table_byte(mxp_base+((sizeof(mxp_record)*(index))+(sizeof(mxp_record)-5)),status); ++ return 0; ++} ++ ++//0~n:success -1:not found ++int mxp_get_record_index(char* name) ++{ ++ int i=0; ++ for(i=0;i<(mxp_record_count);i++) ++ { ++// mxp->read_bytes(sizeof(mxp_record)*(i+1),&mxp_parts[i+1],sizeof(mxp_record)); ++ ++ if(0==strcmp((const char*)(mxp_parts[i].name),((const char*)name))) ++ { ++// memcpy(part,&mxp_parts[i+1],sizeof(mxp_record)); ++ return i; ++ } ++ } ++ ++ return -1; ++ ++} ++ ++//0 -1:not found ++int mxp_get_record_by_name(char* name,mxp_record* part) ++{ ++ int i=0; ++ for(i=0;i<(mxp_record_count);i++) ++ { ++ ++ if(0==strcmp((const char*)(mxp_parts[i].name),((const char*)name))) ++ { ++ memcpy(part,&mxp_parts[i],sizeof(mxp_record)); ++ return 0; ++ } ++ } ++ ++ return -1; ++ ++} ++ ++int mxp_load_table(void){ ++ ++ int count=mxp_table_size/sizeof(mxp_record); ++ int i=0; ++ ++ if(mxp_parts!=NULL) ++ { ++ MXP_FREE(mxp_parts); ++ mxp_parts=NULL; ++ } ++ ++ mxp_record_count=0; ++ mxp_parts=MXP_ALLOC(mxp_table_size); ++ if(!mxp_parts) ++ { ++ MXP_MSG("ERROR!! Failed to allocate memory with mxp_table_size:%d\n",mxp_table_size); ++ return -1; ++ } ++ memset(mxp_parts,0xFF,mxp_table_size); ++ ++ for(i=0;iread_table_bytes(mxp_base+sizeof(mxp_record)*i,&mxp_parts[i],sizeof(mxp_record)); ++ ++ if(mxp_parts[i].type==MXP_PART_TYPE_TAG) ++ { ++ break; ++ } ++ } ++ ++ mxp_record_count=i; ++ ++ // read last part ++ mxp->read_table_bytes(mxp_base+sizeof(mxp_record)*(count-1),&mxp_parts[count-1],sizeof(mxp_record)); ++ ++ return 0; ++ ++} +diff --git a/drivers/mstar/flash_isp/part_mxp.h b/drivers/mstar/flash_isp/part_mxp.h +new file mode 100644 +index 00000000..7bd195ce +--- /dev/null ++++ b/drivers/mstar/flash_isp/part_mxp.h +@@ -0,0 +1,89 @@ ++#ifndef _PART_MXP_H_ ++#define _PART_MXP_H_ ++ ++ ++#define MXP_PART_MAGIC_PREFIX "MXPT" ++#define MXP_PART_MAGIC_SUFFIX "TPXM" ++ ++#define MXP_STORAGE_TYPE_FLASH 0x01 ++ ++#define MXP_PART_TYPE_TAG 0x00 ++#define MXP_PART_TYPE_NORMAL 0x01 ++#define MXP_PART_TYPE_MTD 0x02 ++ ++#define MXP_PART_FORMAT_NONE 0x00 ++ ++ ++#define MXP_PART_STATUS_UPGRADING 0xF7 ++#define MXP_PART_STATUS_READY 0xF6 ++#define MXP_PART_STATUS_ACTIVE 0xF5 ++#define MXP_PART_STATUS_INACTIVE 0xF4 ++#define MXP_PART_STATUS_EMPTY 0x00 ++ ++typedef struct { ++ ++ u8 magic_prefix[4];//MXPT ++ u8 version; ++ u8 type; ++ u8 format; ++ u8 padding; ++ u64 start; ++ u64 size; ++ u32 block; ++ u32 block_count; ++ u8 name[16]; //should be 0 terminated ++ u8 backup[16]; //should be 0 terminated ++ u8 hash[32]; ++ u8 reserved[23]; ++ u32 crc32; ++ u8 status; ++ u8 magic_suffix[4];//TPXM ++ ++} mxp_record; ++ ++typedef struct { ++ u8 type; ++ u64 size; ++}mxp_storage_info; ++ ++typedef struct{ ++ int (*read_table_bytes)(int offset_from_flash,void* buf,int len); ++ int (*write_table_bytes)(int offset_from_flash,void* buf,int len); ++ int (*update_table_byte)(int offset_from_flash,char b); ++ int (*get_storage_info)(mxp_storage_info* info); ++}mxp_manager; ++ ++ ++//0:success -1:error ++int mxp_set_record_status(int index,int status); ++ ++//0:success -1:error ++int mxp_init(int size,mxp_manager* manager); ++ ++//0:success -1:error ++int mxp_check_record_magic(int index); ++ ++//0:success -1:error ++int mxp_check_table_magic(void); ++ ++//0:success -1:error ++int mxp_init_table(void); ++ ++//0:success -1:error ++int mxp_get_total_record_count(void); ++ ++//0:success -1:error ++int mxp_set_record(mxp_record* rec); ++ ++//0:success -1:error ++int mxp_get_record_by_index(int index,mxp_record* rec); ++int mxp_delete_record_by_index(int index); ++//0~n:success -1:not found ++int mxp_get_record_index(char* name); ++ ++ ++int mxp_save_table(void); ++int mxp_load_table(void); ++ ++ ++#endif +diff --git a/drivers/mstar/gpio/Kconfig b/drivers/mstar/gpio/Kconfig +new file mode 100644 +index 00000000..0c911480 +--- /dev/null ++++ b/drivers/mstar/gpio/Kconfig +@@ -0,0 +1,8 @@ ++config MS_GPIO ++ tristate "GPIO driver" ++ default y ++ help ++ ++config MS_SW_I2C ++ tristate "SW I2C via GPIO support" ++ depends on MS_GPIO +diff --git a/drivers/mstar/gpio/Makefile b/drivers/mstar/gpio/Makefile +new file mode 100644 +index 00000000..0c143974 +--- /dev/null ++++ b/drivers/mstar/gpio/Makefile +@@ -0,0 +1,17 @@ ++# ++# Makefile for MStar GPIO device drivers. ++# ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++# general options ++##EXTRA_CFLAGS += -Idrivers/mstar/common ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/gpio ++EXTRA_CFLAGS += -Idrivers/mstar/gpio/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++ ++# specific options ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_GPIO) += mdrv_gpio.o mdrv_gpio_io.o $(CONFIG_MSTAR_CHIP_NAME)/mhal_gpio.o ++obj-$(CONFIG_MS_SW_I2C) += ms_gpioi2c.o mdrv_sw_iic.o +diff --git a/drivers/mstar/gpio/cedric/Makefile b/drivers/mstar/gpio/cedric/Makefile +new file mode 100644 +index 00000000..b5ddd70f +--- /dev/null ++++ b/drivers/mstar/gpio/cedric/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for MStar GPIO HAL drivers. ++# ++ ++ ++ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++include $(TOP_DIR)/modules.mk ++endif ++ ++ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/mstar/common ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/gpio ++EXTRA_CFLAGS += -Idrivers/mstar/gpio/$(CONFIG_MSTAR_CHIP_NAME) ++ ++# files ++#obj-$(CONFIG_MSTAR_GPIO) += mhal_gpio.o +diff --git a/drivers/mstar/gpio/cedric/mhal_gpio.c b/drivers/mstar/gpio/cedric/mhal_gpio.c +new file mode 100644 +index 00000000..c20b7dc6 +--- /dev/null ++++ b/drivers/mstar/gpio/cedric/mhal_gpio.c +@@ -0,0 +1,1759 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if 1 ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++/* ++#define BIT0 BIT(0) ++#define BIT1 BIT(1) ++#define BIT2 BIT(2) ++#define BIT3 BIT(3) ++#define BIT4 BIT(4) ++#define BIT5 BIT(5) ++#define BIT6 BIT(6) ++#define BIT7 BIT(7) ++*/ ++ // Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++#define GPIO0_PAD PAD_PM_GPIO0 ++#define GPIO0_OEN 0x0f08, BIT0 ++#define GPIO0_IN 0x0f10, BIT0 ++#define GPIO0_OUT 0x0f0c, BIT0 ++ ++#define GPIO1_PAD PAD_PM_GPIO1 ++#define GPIO1_OEN 0x0f08, BIT1 ++#define GPIO1_IN 0x0f10, BIT1 ++#define GPIO1_OUT 0x0f0c, BIT1 ++ ++#define GPIO2_PAD PAD_PM_IIC_SDA ++#define GPIO2_OEN 0x0f08, BIT2 ++#define GPIO2_IN 0x0f10, BIT2 ++#define GPIO2_OUT 0x0f0c, BIT2 ++ ++#define GPIO3_PAD PAD_PM_IIC_SCL ++#define GPIO3_OEN 0x0f08, BIT3 ++#define GPIO3_IN 0x0f10, BIT3 ++#define GPIO3_OUT 0x0f0c, BIT3 ++ ++#define GPIO4_PAD PAD_PM_MIIC_SDA ++#define GPIO4_OEN 0x0f08, BIT4 ++#define GPIO4_IN 0x0f10, BIT4 ++#define GPIO4_OUT 0x0f0c, BIT4 ++ ++#define GPIO5_PAD PAD_PM_MIIC_SCL ++#define GPIO5_OEN 0x0f08, BIT5 ++#define GPIO5_IN 0x0f10, BIT5 ++#define GPIO5_OUT 0x0f0c, BIT5 ++ ++#define GPIO6_PAD PAD_PM_SPI_CK ++#define GPIO6_OEN 0x0f08, BIT6 ++#define GPIO6_IN 0x0f10, BIT6 ++#define GPIO6_OUT 0x0f0c, BIT6 ++ ++#define GPIO7_PAD PAD_PM_SPI_CZ0 ++#define GPIO7_OEN 0x0f08, BIT7 ++#define GPIO7_IN 0x0f10, BIT7 ++#define GPIO7_OUT 0x0f0c, BIT7 ++ ++#define GPIO8_PAD PAD_PM_SPI_GPIO ++#define GPIO8_OEN 0x0f09, BIT0 ++#define GPIO8_IN 0x0f11, BIT0 ++#define GPIO8_OUT 0x0f0d, BIT0 ++ ++#define GPIO9_PAD PAD_PM_SPI_DI ++#define GPIO9_OEN 0x0f09, BIT1 ++#define GPIO9_IN 0x0f11, BIT1 ++#define GPIO9_OUT 0x0f0d, BIT1 ++ ++#define GPIO10_PAD PAD_PM_SPI_DO ++#define GPIO10_OEN 0x0f09, BIT2 ++#define GPIO10_IN 0x0f11, BIT2 ++#define GPIO10_OUT 0x0f0d, BIT2 ++ ++#define GPIO11_PAD PAD_ONOFF ++#define GPIO11_OEN 0x0f09, BIT3 ++#define GPIO11_IN 0x0f11, BIT3 ++#define GPIO11_OUT 0x0f0d, BIT3 ++ ++#define GPIO12_PAD PAD_CHRGDET ++#define GPIO12_OEN 0x0f09, BIT4 ++#define GPIO12_IN 0x0f11, BIT4 ++#define GPIO12_OUT 0x0f0d, BIT4 ++ ++#define GPIO13_PAD PAD_32K_OUT ++#define GPIO13_OEN 0x0f09, BIT5 ++#define GPIO13_IN 0x0f11, BIT5 ++#define GPIO13_OUT 0x0f0d, BIT5 ++ ++#define GPIO14_PAD PAD_IRIN ++#define GPIO14_OEN 0x0f09, BIT6 ++#define GPIO14_IN 0x0f11, BIT6 ++#define GPIO14_OUT 0x0f0d, BIT6 ++ ++#define GPIO15_PAD PAD_CEC ++#define GPIO15_OEN 0x0f09, BIT7 ++#define GPIO15_IN 0x0f11, BIT7 ++#define GPIO15_OUT 0x0f0d, BIT7 ++ ++#define GPIO16_PAD PAD_PM_SD0_CDZ ++#define GPIO16_OEN 0x0f0a, BIT0 ++#define GPIO16_IN 0x0f12, BIT0 ++#define GPIO16_OUT 0x0f0e, BIT0 ++ ++#define GPIO17_PAD PAD_PM_SD1_CDZ ++#define GPIO17_OEN 0x0f0a, BIT1 ++#define GPIO17_IN 0x0f12, BIT1 ++#define GPIO17_OUT 0x0f0e, BIT1 ++ ++#define GPIO18_PAD PAD_PM_SD2_CDZ ++#define GPIO18_OEN 0x0f0a, BIT2 ++#define GPIO18_IN 0x0f12, BIT2 ++#define GPIO18_OUT 0x0f0e, BIT2 ++ ++#define GPIO19_PAD PAD_PM_SD_GPIO ++#define GPIO19_OEN 0x0f0a, BIT3 ++#define GPIO19_IN 0x0f12, BIT3 ++#define GPIO19_OUT 0x0f0e, BIT3 ++ ++#define GPIO20_PAD PAD_HOTPLUG ++#define GPIO20_OEN 0x0f0a, BIT4 ++#define GPIO20_IN 0x0f12, BIT4 ++#define GPIO20_OUT 0x0f0e, BIT4 ++ ++#define GPIO21_PAD PAD_BATOK ++#define GPIO21_OEN 0x0f0a, BIT5 ++#define GPIO21_IN 0x0f12, BIT5 ++#define GPIO21_OUT 0x0f0e, BIT5 ++ ++#define GPIO22_PAD PAD_PMIC_CHIPEN ++#define GPIO22_OEN 0x0f0a, BIT6 ++#define GPIO22_IN 0x0f12, BIT6 ++#define GPIO22_OUT 0x0f0e, BIT6 ++ ++#define GPIO23_PAD PAD_PMIC_STDBYN ++#define GPIO23_OEN 0x0f0a, BIT7 ++#define GPIO23_IN 0x0f12, BIT7 ++#define GPIO23_OUT 0x0f0e, BIT7 ++ ++#define GPIO24_PAD PAD_PMIC_INT ++#define GPIO24_OEN 0x0f0b, BIT0 ++#define GPIO24_IN 0x0f13, BIT0 ++#define GPIO24_OUT 0x0f0f, BIT0 ++ ++#define GPIO25_PAD PAD_SD0_D1 ++#define GPIO25_OEN 0x102b7A, BIT1 ++#define GPIO25_IN 0x102b7A, BIT2 ++#define GPIO25_OUT 0x102b7A, BIT0 ++ ++#define GPIO26_PAD PAD_SD0_D0 ++#define GPIO26_OEN 0x102b79, BIT1 ++#define GPIO26_IN 0x102b79, BIT2 ++#define GPIO26_OUT 0x102b79, BIT0 ++ ++#define GPIO27_PAD PAD_SD0_CLK ++#define GPIO27_OEN 0x102b7C, BIT1 ++#define GPIO27_IN 0x102b7C, BIT2 ++#define GPIO27_OUT 0x102b7C, BIT0 ++ ++#define GPIO28_PAD PAD_SD0_CMD ++#define GPIO28_OEN 0x102b7B, BIT1 ++#define GPIO28_IN 0x102b7B, BIT2 ++#define GPIO28_OUT 0x102b7B, BIT0 ++ ++#define GPIO29_PAD PAD_SD0_D3 ++#define GPIO29_OEN 0x102b7E, BIT1 ++#define GPIO29_IN 0x102b7E, BIT2 ++#define GPIO29_OUT 0x102b7E, BIT0 ++ ++#define GPIO30_PAD PAD_SD0_D2 ++#define GPIO30_OEN 0x102b7D, BIT1 ++#define GPIO30_IN 0x102b7D, BIT2 ++#define GPIO30_OUT 0x102b7D, BIT0 ++ ++#define GPIO31_PAD PAD_SD1_D1 ++#define GPIO31_OEN 0x102b80, BIT1 ++#define GPIO31_IN 0x102b80, BIT2 ++#define GPIO31_OUT 0x102b80, BIT0 ++ ++#define GPIO32_PAD PAD_SD1_D0 ++#define GPIO32_OEN 0x102b7F, BIT1 ++#define GPIO32_IN 0x102b7F, BIT2 ++#define GPIO32_OUT 0x102b7F, BIT0 ++ ++#define GPIO33_PAD PAD_SD1_CLK ++#define GPIO33_OEN 0x102b82, BIT1 ++#define GPIO33_IN 0x102b82, BIT2 ++#define GPIO33_OUT 0x102b82, BIT0 ++ ++#define GPIO34_PAD PAD_SD1_CMD ++#define GPIO34_OEN 0x102b81, BIT1 ++#define GPIO34_IN 0x102b81, BIT2 ++#define GPIO34_OUT 0x102b81, BIT0 ++ ++#define GPIO35_PAD PAD_SD1_D3 ++#define GPIO35_OEN 0x102b84, BIT1 ++#define GPIO35_IN 0x102b84, BIT2 ++#define GPIO35_OUT 0x102b84, BIT0 ++ ++#define GPIO36_PAD PAD_SD1_D2 ++#define GPIO36_OEN 0x102b83, BIT1 ++#define GPIO36_IN 0x102b83, BIT2 ++#define GPIO36_OUT 0x102b83, BIT0 ++ ++#define GPIO37_PAD PAD_A_GPS_EVENT ++#define GPIO37_OEN 0x102b31, BIT1 ++#define GPIO37_IN 0x102b31, BIT2 ++#define GPIO37_OUT 0x102b31, BIT0 ++ ++#define GPIO38_PAD PAD_AFE1_SGN ++#define GPIO38_OEN 0x102b32, BIT1 ++#define GPIO38_IN 0x102b32, BIT2 ++#define GPIO38_OUT 0x102b32, BIT0 ++ ++#define GPIO39_PAD PAD_AFE1_MAG ++#define GPIO39_OEN 0x102b33, BIT1 ++#define GPIO39_IN 0x102b33, BIT2 ++#define GPIO39_OUT 0x102b33, BIT0 ++ ++#define GPIO40_PAD PAD_RFSPI_CZ1 ++#define GPIO40_OEN 0x102b39, BIT1 ++#define GPIO40_IN 0x102b39, BIT2 ++#define GPIO40_OUT 0x102b39, BIT0 ++ ++#define GPIO41_PAD PAD_AFE0_SGN ++#define GPIO41_OEN 0x102b34, BIT1 ++#define GPIO41_IN 0x102b34, BIT2 ++#define GPIO41_OUT 0x102b34, BIT0 ++ ++#define GPIO42_PAD PAD_AFE0_MAG ++#define GPIO42_OEN 0x102b35, BIT1 ++#define GPIO42_IN 0x102b35, BIT2 ++#define GPIO42_OUT 0x102b35, BIT0 ++ ++#define GPIO43_PAD PAD_RFSPI_CLK ++#define GPIO43_OEN 0x102b38, BIT1 ++#define GPIO43_IN 0x102b38, BIT2 ++#define GPIO43_OUT 0x102b38, BIT0 ++ ++#define GPIO44_PAD PAD_RFSPI_DATA ++#define GPIO44_OEN 0x102b37, BIT1 ++#define GPIO44_IN 0x102b37, BIT2 ++#define GPIO44_OUT 0x102b37, BIT0 ++ ++#define GPIO45_PAD PAD_RFSPI_CZ0 ++#define GPIO45_OEN 0x102b36, BIT1 ++#define GPIO45_IN 0x102b36, BIT2 ++#define GPIO45_OUT 0x102b36, BIT0 ++ ++#define GPIO46_PAD PAD_BTI_RX_TX ++#define GPIO46_OEN 0x102b06, BIT1 ++#define GPIO46_IN 0x102b06, BIT2 ++#define GPIO46_OUT 0x102b06, BIT0 ++ ++#define GPIO47_PAD PAD_BTI_DATA1 ++#define GPIO47_OEN 0x102b05, BIT1 ++#define GPIO47_IN 0x102b05, BIT2 ++#define GPIO47_OUT 0x102b05, BIT0 ++ ++#define GPIO48_PAD PAD_BTI_DATA0 ++#define GPIO48_OEN 0x102b04, BIT1 ++#define GPIO48_IN 0x102b04, BIT2 ++#define GPIO48_OUT 0x102b04, BIT0 ++ ++#define GPIO49_PAD PAD_BT_CLK_24M ++#define GPIO49_OEN 0x102b03, BIT1 ++#define GPIO49_IN 0x102b03, BIT2 ++#define GPIO49_OUT 0x102b03, BIT0 ++ ++#define GPIO50_PAD PAD_BT_SPI_SCLK ++#define GPIO50_OEN 0x102b02, BIT1 ++#define GPIO50_IN 0x102b02, BIT2 ++#define GPIO50_OUT 0x102b02, BIT0 ++ ++#define GPIO51_PAD PAD_BT_SPI_SDATA ++#define GPIO51_OEN 0x102b01, BIT1 ++#define GPIO51_IN 0x102b01, BIT2 ++#define GPIO51_OUT 0x102b01, BIT0 ++ ++#define GPIO52_PAD PAD_BT_SPI_SENB ++#define GPIO52_OEN 0x102b00, BIT1 ++#define GPIO52_IN 0x102b00, BIT2 ++#define GPIO52_OUT 0x102b00, BIT0 ++ ++#define GPIO53_PAD PAD_BT_CHIP_EN ++#define GPIO53_OEN 0x102b07, BIT1 ++#define GPIO53_IN 0x102b07, BIT2 ++#define GPIO53_OUT 0x102b07, BIT0 ++ ++#define GPIO54_PAD PAD_SR_D0 ++#define GPIO54_OEN 0x102b97, BIT1 ++#define GPIO54_IN 0x102b97, BIT2 ++#define GPIO54_OUT 0x102b97, BIT0 ++ ++#define GPIO55_PAD PAD_SR_D1 ++#define GPIO55_OEN 0x102b96, BIT1 ++#define GPIO55_IN 0x102b96, BIT2 ++#define GPIO55_OUT 0x102b96, BIT0 ++ ++#define GPIO56_PAD PAD_SR_D2 ++#define GPIO56_OEN 0x102b99, BIT1 ++#define GPIO56_IN 0x102b99, BIT2 ++#define GPIO56_OUT 0x102b99, BIT0 ++ ++#define GPIO57_PAD PAD_SR_D3 ++#define GPIO57_OEN 0x102b98, BIT1 ++#define GPIO57_IN 0x102b98, BIT2 ++#define GPIO57_OUT 0x102b98, BIT0 ++ ++#define GPIO58_PAD PAD_SR_D4 ++#define GPIO58_OEN 0x102b9B, BIT1 ++#define GPIO58_IN 0x102b9B, BIT2 ++#define GPIO58_OUT 0x102b9B, BIT0 ++ ++#define GPIO59_PAD PAD_SR_D5 ++#define GPIO59_OEN 0x102b9A, BIT1 ++#define GPIO59_IN 0x102b9A, BIT2 ++#define GPIO59_OUT 0x102b9A, BIT0 ++ ++#define GPIO60_PAD PAD_SR_D6 ++#define GPIO60_OEN 0x102b9D, BIT1 ++#define GPIO60_IN 0x102b9D, BIT2 ++#define GPIO60_OUT 0x102b9D, BIT0 ++ ++#define GPIO61_PAD PAD_SR_D7 ++#define GPIO61_OEN 0x102b9C, BIT1 ++#define GPIO61_IN 0x102b9C, BIT2 ++#define GPIO61_OUT 0x102b9C, BIT0 ++ ++#define GPIO62_PAD PAD_SR_PCLK ++#define GPIO62_OEN 0x102bA3, BIT1 ++#define GPIO62_IN 0x102bA3, BIT2 ++#define GPIO62_OUT 0x102bA3, BIT0 ++ ++#define GPIO63_PAD PAD_SR_HSYNC ++#define GPIO63_OEN 0x102b9F, BIT1 ++#define GPIO63_IN 0x102b9F, BIT2 ++#define GPIO63_OUT 0x102b9F, BIT0 ++ ++#define GPIO64_PAD PAD_SR_STROBE ++#define GPIO64_OEN 0x102b9E, BIT1 ++#define GPIO64_IN 0x102b9E, BIT2 ++#define GPIO64_OUT 0x102b9E, BIT0 ++ ++#define GPIO65_PAD PAD_SR_VSYNC ++#define GPIO65_OEN 0x102bA0, BIT1 ++#define GPIO65_IN 0x102bA0, BIT2 ++#define GPIO65_OUT 0x102bA0, BIT0 ++ ++#define GPIO66_PAD PAD_SR_RST ++#define GPIO66_OEN 0x102bA1, BIT1 ++#define GPIO66_IN 0x102bA1, BIT2 ++#define GPIO66_OUT 0x102bA1, BIT0 ++ ++#define GPIO67_PAD PAD_SR_PWRDN ++#define GPIO67_OEN 0x102bA2, BIT1 ++#define GPIO67_IN 0x102bA2, BIT2 ++#define GPIO67_OUT 0x102bA2, BIT0 ++ ++#define GPIO68_PAD PAD_GPIO33 ++#define GPIO68_OEN 0x102b2A, BIT1 ++#define GPIO68_IN 0x102b2A, BIT2 ++#define GPIO68_OUT 0x102b2A, BIT0 ++ ++#define GPIO69_PAD PAD_GPIO32 ++#define GPIO69_OEN 0x102b29, BIT1 ++#define GPIO69_IN 0x102b29, BIT2 ++#define GPIO69_OUT 0x102b29, BIT0 ++ ++#define GPIO70_PAD PAD_GPIO31 ++#define GPIO70_OEN 0x102b28, BIT1 ++#define GPIO70_IN 0x102b28, BIT2 ++#define GPIO70_OUT 0x102b28, BIT0 ++ ++#define GPIO71_PAD PAD_GPIO30 ++#define GPIO71_OEN 0x102b27, BIT1 ++#define GPIO71_IN 0x102b27, BIT2 ++#define GPIO71_OUT 0x102b27, BIT0 ++ ++#define GPIO72_PAD PAD_GPIO29 ++#define GPIO72_OEN 0x102b26, BIT1 ++#define GPIO72_IN 0x102b26, BIT2 ++#define GPIO72_OUT 0x102b26, BIT0 ++ ++#define GPIO73_PAD PAD_GPIO28 ++#define GPIO73_OEN 0x102b25, BIT1 ++#define GPIO73_IN 0x102b25, BIT2 ++#define GPIO73_OUT 0x102b25, BIT0 ++ ++#define GPIO74_PAD PAD_GPIO27 ++#define GPIO74_OEN 0x102b24, BIT1 ++#define GPIO74_IN 0x102b24, BIT2 ++#define GPIO74_OUT 0x102b24, BIT0 ++ ++#define GPIO75_PAD PAD_GPIO26 ++#define GPIO75_OEN 0x102b23, BIT1 ++#define GPIO75_IN 0x102b23, BIT2 ++#define GPIO75_OUT 0x102b23, BIT0 ++ ++#define GPIO76_PAD PAD_GPIO25 ++#define GPIO76_OEN 0x102b22, BIT1 ++#define GPIO76_IN 0x102b22, BIT2 ++#define GPIO76_OUT 0x102b22, BIT0 ++ ++#define GPIO77_PAD PAD_GPIO24 ++#define GPIO77_OEN 0x102b21, BIT1 ++#define GPIO77_IN 0x102b21, BIT2 ++#define GPIO77_OUT 0x102b21, BIT0 ++ ++#define GPIO78_PAD PAD_UART_RX1 ++#define GPIO78_OEN 0x102bB0, BIT1 ++#define GPIO78_IN 0x102bB0, BIT2 ++#define GPIO78_OUT 0x102bB0, BIT0 ++ ++#define GPIO79_PAD PAD_UART_TX1 ++#define GPIO79_OEN 0x102bB1, BIT1 ++#define GPIO79_IN 0x102bB1, BIT2 ++#define GPIO79_OUT 0x102bB1, BIT0 ++ ++#define GPIO80_PAD PAD_UART_RX2 ++#define GPIO80_OEN 0x102bB3, BIT1 ++#define GPIO80_IN 0x102bB3, BIT2 ++#define GPIO80_OUT 0x102bB3, BIT0 ++ ++#define GPIO81_PAD PAD_UART_TX2 ++#define GPIO81_OEN 0x102bB2, BIT1 ++#define GPIO81_IN 0x102bB2, BIT2 ++#define GPIO81_OUT 0x102bB2, BIT0 ++ ++#define GPIO82_PAD PAD_UART_RX3 ++#define GPIO82_OEN 0x102bB5, BIT1 ++#define GPIO82_IN 0x102bB5, BIT2 ++#define GPIO82_OUT 0x102bB5, BIT0 ++ ++#define GPIO83_PAD PAD_UART_TX3 ++#define GPIO83_OEN 0x102bB4, BIT1 ++#define GPIO83_IN 0x102bB4, BIT2 ++#define GPIO83_OUT 0x102bB4, BIT0 ++ ++#define GPIO84_PAD PAD_UART_RX4 ++#define GPIO84_OEN 0x102bB7, BIT1 ++#define GPIO84_IN 0x102bB7, BIT2 ++#define GPIO84_OUT 0x102bB7, BIT0 ++ ++#define GPIO85_PAD PAD_UART_TX4 ++#define GPIO85_OEN 0x102bB6, BIT1 ++#define GPIO85_IN 0x102bB6, BIT2 ++#define GPIO85_OUT 0x102bB6, BIT0 ++ ++#define GPIO86_PAD PAD_UART_CTS2 ++#define GPIO86_OEN 0x102bBD, BIT1 ++#define GPIO86_IN 0x102bBD, BIT2 ++#define GPIO86_OUT 0x102bBD, BIT0 ++ ++#define GPIO87_PAD PAD_UART_RTS2 ++#define GPIO87_OEN 0x102bBC, BIT1 ++#define GPIO87_IN 0x102bBC, BIT2 ++#define GPIO87_OUT 0x102bBC, BIT0 ++ ++#define GPIO88_PAD PAD_GPIO34 ++#define GPIO88_OEN 0x102b2B, BIT1 ++#define GPIO88_IN 0x102b2B, BIT2 ++#define GPIO88_OUT 0x102b2B, BIT0 ++ ++#define GPIO89_PAD PAD_GPIO35 ++#define GPIO89_OEN 0x102b2C, BIT1 ++#define GPIO89_IN 0x102b2C, BIT2 ++#define GPIO89_OUT 0x102b2C, BIT0 ++ ++#define GPIO90_PAD PAD_GPIO36 ++#define GPIO90_OEN 0x102b2D, BIT1 ++#define GPIO90_IN 0x102b2D, BIT2 ++#define GPIO90_OUT 0x102b2D, BIT0 ++ ++#define GPIO91_PAD PAD_GPIO37 ++#define GPIO91_OEN 0x102b2E, BIT1 ++#define GPIO91_IN 0x102b2E, BIT2 ++#define GPIO91_OUT 0x102b2E, BIT0 ++ ++#define GPIO92_PAD PAD_GPIO38 ++#define GPIO92_OEN 0x102b2F, BIT1 ++#define GPIO92_IN 0x102b2F, BIT2 ++#define GPIO92_OUT 0x102b2F, BIT0 ++ ++#define GPIO93_PAD PAD_MPIF_CS1Z ++#define GPIO93_OEN 0x102b5D, BIT1 ++#define GPIO93_IN 0x102b5D, BIT2 ++#define GPIO93_OUT 0x102b5D, BIT0 ++ ++#define GPIO94_PAD PAD_MPIF_CS0Z ++#define GPIO94_OEN 0x102b5E, BIT1 ++#define GPIO94_IN 0x102b5E, BIT2 ++#define GPIO94_OUT 0x102b5E, BIT0 ++ ++#define GPIO95_PAD PAD_MPIF_D0 ++#define GPIO95_OEN 0x102b58, BIT1 ++#define GPIO95_IN 0x102b58, BIT2 ++#define GPIO95_OUT 0x102b58, BIT0 ++ ++#define GPIO96_PAD PAD_MPIF_D1 ++#define GPIO96_OEN 0x102b59, BIT1 ++#define GPIO96_IN 0x102b59, BIT2 ++#define GPIO96_OUT 0x102b59, BIT0 ++ ++#define GPIO97_PAD PAD_MPIF_D2 ++#define GPIO97_OEN 0x102b5A, BIT1 ++#define GPIO97_IN 0x102b5A, BIT2 ++#define GPIO97_OUT 0x102b5A, BIT0 ++ ++#define GPIO98_PAD PAD_MPIF_D3 ++#define GPIO98_OEN 0x102b5B, BIT1 ++#define GPIO98_IN 0x102b5B, BIT2 ++#define GPIO98_OUT 0x102b5B, BIT0 ++ ++#define GPIO99_PAD PAD_MPIF_CK ++#define GPIO99_OEN 0x102b5F, BIT1 ++#define GPIO99_IN 0x102b5F, BIT2 ++#define GPIO99_OUT 0x102b5F, BIT0 ++ ++#define GPIO100_PAD PAD_MPIF_BUSY ++#define GPIO100_OEN 0x102b5C, BIT1 ++#define GPIO100_IN 0x102b5C, BIT2 ++#define GPIO100_OUT 0x102b5C, BIT0 ++ ++#define GPIO101_PAD PAD_MIIC0_SDA ++#define GPIO101_OEN 0x102b3B, BIT1 ++#define GPIO101_IN 0x102b3B, BIT2 ++#define GPIO101_OUT 0x102b3B, BIT0 ++ ++#define GPIO102_PAD PAD_MIIC0_SCL ++#define GPIO102_OEN 0x102b3C, BIT1 ++#define GPIO102_IN 0x102b3C, BIT2 ++#define GPIO102_OUT 0x102b3C, BIT0 ++ ++#define GPIO103_PAD PAD_GPIO23 ++#define GPIO103_OEN 0x102b20, BIT1 ++#define GPIO103_IN 0x102b20, BIT2 ++#define GPIO103_OUT 0x102b20, BIT0 ++ ++#define GPIO104_PAD PAD_GPIO22 ++#define GPIO104_OEN 0x102b1F, BIT1 ++#define GPIO104_IN 0x102b1F, BIT2 ++#define GPIO104_OUT 0x102b1F, BIT0 ++ ++#define GPIO105_PAD PAD_GPIO21 ++#define GPIO105_OEN 0x102b1E, BIT1 ++#define GPIO105_IN 0x102b1E, BIT2 ++#define GPIO105_OUT 0x102b1E, BIT0 ++ ++#define GPIO106_PAD PAD_GPIO20 ++#define GPIO106_OEN 0x102b1D, BIT1 ++#define GPIO106_IN 0x102b1D, BIT2 ++#define GPIO106_OUT 0x102b1D, BIT0 ++ ++#define GPIO107_PAD PAD_GPIO19 ++#define GPIO107_OEN 0x102b1C, BIT1 ++#define GPIO107_IN 0x102b1C, BIT2 ++#define GPIO107_OUT 0x102b1C, BIT0 ++ ++#define GPIO108_PAD PAD_GPIO18 ++#define GPIO108_OEN 0x102b1B, BIT1 ++#define GPIO108_IN 0x102b1B, BIT2 ++#define GPIO108_OUT 0x102b1B, BIT0 ++ ++#define GPIO109_PAD PAD_GPIO17 ++#define GPIO109_OEN 0x102b1A, BIT1 ++#define GPIO109_IN 0x102b1A, BIT2 ++#define GPIO109_OUT 0x102b1A, BIT0 ++ ++#define GPIO110_PAD PAD_GPIO16 ++#define GPIO110_OEN 0x102b19, BIT1 ++#define GPIO110_IN 0x102b19, BIT2 ++#define GPIO110_OUT 0x102b19, BIT0 ++ ++#define GPIO111_PAD PAD_GPIO15 ++#define GPIO111_OEN 0x102b18, BIT1 ++#define GPIO111_IN 0x102b18, BIT2 ++#define GPIO111_OUT 0x102b18, BIT0 ++ ++#define GPIO112_PAD PAD_GPIO14 ++#define GPIO112_OEN 0x102b17, BIT1 ++#define GPIO112_IN 0x102b17, BIT2 ++#define GPIO112_OUT 0x102b17, BIT0 ++ ++#define GPIO113_PAD PAD_GPIO13 ++#define GPIO113_OEN 0x102b16, BIT1 ++#define GPIO113_IN 0x102b16, BIT2 ++#define GPIO113_OUT 0x102b16, BIT0 ++ ++#define GPIO114_PAD PAD_GPIO12 ++#define GPIO114_OEN 0x102b15, BIT1 ++#define GPIO114_IN 0x102b15, BIT2 ++#define GPIO114_OUT 0x102b15, BIT0 ++ ++#define GPIO115_PAD PAD_GPIO11 ++#define GPIO115_OEN 0x102b14, BIT1 ++#define GPIO115_IN 0x102b14, BIT2 ++#define GPIO115_OUT 0x102b14, BIT0 ++ ++#define GPIO116_PAD PAD_GPIO10 ++#define GPIO116_OEN 0x102b13, BIT1 ++#define GPIO116_IN 0x102b13, BIT2 ++#define GPIO116_OUT 0x102b13, BIT0 ++ ++#define GPIO117_PAD PAD_GPIO9 ++#define GPIO117_OEN 0x102b12, BIT1 ++#define GPIO117_IN 0x102b12, BIT2 ++#define GPIO117_OUT 0x102b12, BIT0 ++ ++#define GPIO118_PAD PAD_GPIO8 ++#define GPIO118_OEN 0x102b11, BIT1 ++#define GPIO118_IN 0x102b11, BIT2 ++#define GPIO118_OUT 0x102b11, BIT0 ++ ++#define GPIO119_PAD PAD_GPIO7 ++#define GPIO119_OEN 0x102b10, BIT1 ++#define GPIO119_IN 0x102b10, BIT2 ++#define GPIO119_OUT 0x102b10, BIT0 ++ ++#define GPIO120_PAD PAD_GPIO6 ++#define GPIO120_OEN 0x102b0F, BIT1 ++#define GPIO120_IN 0x102b0F, BIT2 ++#define GPIO120_OUT 0x102b0F, BIT0 ++ ++#define GPIO121_PAD PAD_GPIO5 ++#define GPIO121_OEN 0x102b0E, BIT1 ++#define GPIO121_IN 0x102b0E, BIT2 ++#define GPIO121_OUT 0x102b0E, BIT0 ++ ++#define GPIO122_PAD PAD_GPIO4 ++#define GPIO122_OEN 0x102b0D, BIT1 ++#define GPIO122_IN 0x102b0D, BIT2 ++#define GPIO122_OUT 0x102b0D, BIT0 ++ ++#define GPIO123_PAD PAD_GPIO3 ++#define GPIO123_OEN 0x102b0C, BIT1 ++#define GPIO123_IN 0x102b0C, BIT2 ++#define GPIO123_OUT 0x102b0C, BIT0 ++ ++#define GPIO124_PAD PAD_GPIO2 ++#define GPIO124_OEN 0x102b0B, BIT1 ++#define GPIO124_IN 0x102b0B, BIT2 ++#define GPIO124_OUT 0x102b0B, BIT0 ++ ++#define GPIO125_PAD PAD_GPIO1 ++#define GPIO125_OEN 0x102b0A, BIT1 ++#define GPIO125_IN 0x102b0A, BIT2 ++#define GPIO125_OUT 0x102b0A, BIT0 ++ ++#define GPIO126_PAD PAD_GPIO0 ++#define GPIO126_OEN 0x102b09, BIT1 ++#define GPIO126_IN 0x102b09, BIT2 ++#define GPIO126_OUT 0x102b09, BIT0 ++ ++#define GPIO127_PAD PAD_TESTPIN ++#define GPIO127_OEN 0x0, BIT0 ++#define GPIO127_IN 0x0, BIT0 ++#define GPIO127_OUT 0x0, BIT0 ++ ++#define GPIO128_PAD PAD_SPDIF_OUT ++#define GPIO128_OEN 0x102b94, BIT1 ++#define GPIO128_IN 0x102b94, BIT2 ++#define GPIO128_OUT 0x102b94, BIT0 ++ ++#define GPIO129_PAD PAD_IIS_TRX_BCK ++#define GPIO129_OEN 0x102b51, BIT1 ++#define GPIO129_IN 0x102b51, BIT2 ++#define GPIO129_OUT 0x102b51, BIT0 ++ ++#define GPIO130_PAD PAD_IIS_TRX_WS ++#define GPIO130_OEN 0x102b50, BIT1 ++#define GPIO130_IN 0x102b50, BIT2 ++#define GPIO130_OUT 0x102b50, BIT0 ++ ++#define GPIO131_PAD PAD_IIS_TRX_OUT ++#define GPIO131_OEN 0x102b53, BIT1 ++#define GPIO131_IN 0x102b53, BIT2 ++#define GPIO131_OUT 0x102b53, BIT0 ++ ++#define GPIO132_PAD PAD_IIS_TRX_IN ++#define GPIO132_OEN 0x102b52, BIT1 ++#define GPIO132_IN 0x102b52, BIT2 ++#define GPIO132_OUT 0x102b52, BIT0 ++ ++#define GPIO133_PAD PAD_UART_RX5 ++#define GPIO133_OEN 0x102bB9, BIT1 ++#define GPIO133_IN 0x102bB9, BIT2 ++#define GPIO133_OUT 0x102bB9, BIT0 ++ ++#define GPIO134_PAD PAD_UART_TX5 ++#define GPIO134_OEN 0x102bB8, BIT1 ++#define GPIO134_IN 0x102bB8, BIT2 ++#define GPIO134_OUT 0x102bB8, BIT0 ++ ++#define GPIO135_PAD PAD_UART_CTS1 ++#define GPIO135_OEN 0x102bBB, BIT1 ++#define GPIO135_IN 0x102bBB, BIT2 ++#define GPIO135_OUT 0x102bBB, BIT0 ++ ++#define GPIO136_PAD PAD_UART_RTS1 ++#define GPIO136_OEN 0x102bBA, BIT1 ++#define GPIO136_IN 0x102bBA, BIT2 ++#define GPIO136_OUT 0x102bBA, BIT0 ++ ++#define GPIO137_PAD PAD_TCON_GPIO8 ++#define GPIO137_OEN 0x102bAE, BIT1 ++#define GPIO137_IN 0x102bAE, BIT2 ++#define GPIO137_OUT 0x102bAE, BIT0 ++ ++#define GPIO138_PAD PAD_TCON_GPIO7 ++#define GPIO138_OEN 0x102bAD, BIT1 ++#define GPIO138_IN 0x102bAD, BIT2 ++#define GPIO138_OUT 0x102bAD, BIT0 ++ ++#define GPIO139_PAD PAD_TCON_GPIO6 ++#define GPIO139_OEN 0x102bAC, BIT1 ++#define GPIO139_IN 0x102bAC, BIT2 ++#define GPIO139_OUT 0x102bAC, BIT0 ++ ++#define GPIO140_PAD PAD_TCON_GPIO5 ++#define GPIO140_OEN 0x102bAB, BIT1 ++#define GPIO140_IN 0x102bAB, BIT2 ++#define GPIO140_OUT 0x102bAB, BIT0 ++ ++#define GPIO141_PAD PAD_TCON_GPIO4 ++#define GPIO141_OEN 0x102bAA, BIT1 ++#define GPIO141_IN 0x102bAA, BIT2 ++#define GPIO141_OUT 0x102bAA, BIT0 ++ ++#define GPIO142_PAD PAD_TCON_GPIO3 ++#define GPIO142_OEN 0x102bA9, BIT1 ++#define GPIO142_IN 0x102bA9, BIT2 ++#define GPIO142_OUT 0x102bA9, BIT0 ++ ++#define GPIO143_PAD PAD_TCON_GPIO2 ++#define GPIO143_OEN 0x102bA8, BIT1 ++#define GPIO143_IN 0x102bA8, BIT2 ++#define GPIO143_OUT 0x102bA8, BIT0 ++ ++#define GPIO144_PAD PAD_TCON_GPIO1 ++#define GPIO144_OEN 0x102bA7, BIT1 ++#define GPIO144_IN 0x102bA7, BIT2 ++#define GPIO144_OUT 0x102bA7, BIT0 ++ ++#define GPIO145_PAD PAD_TCON_GPIO0 ++#define GPIO145_OEN 0x102bA6, BIT1 ++#define GPIO145_IN 0x102bA6, BIT2 ++#define GPIO145_OUT 0x102bA6, BIT0 ++ ++#define GPIO146_PAD PAD_TTL_GPIO11 ++#define GPIO146_OEN 0x102b49, BIT1 ++#define GPIO146_IN 0x102b49, BIT2 ++#define GPIO146_OUT 0x102b49, BIT0 ++ ++#define GPIO147_PAD PAD_TTL_GPIO10 ++#define GPIO147_OEN 0x102b48, BIT1 ++#define GPIO147_IN 0x102b48, BIT2 ++#define GPIO147_OUT 0x102b48, BIT0 ++ ++#define GPIO148_PAD PAD_TTL_GPIO9 ++#define GPIO148_OEN 0x102b47, BIT1 ++#define GPIO148_IN 0x102b47, BIT2 ++#define GPIO148_OUT 0x102b47, BIT0 ++ ++#define GPIO149_PAD PAD_TTL_GPIO8 ++#define GPIO149_OEN 0x102b46, BIT1 ++#define GPIO149_IN 0x102b46, BIT2 ++#define GPIO149_OUT 0x102b46, BIT0 ++ ++#define GPIO150_PAD PAD_TTL_GPIO7 ++#define GPIO150_OEN 0x102b45, BIT1 ++#define GPIO150_IN 0x102b45, BIT2 ++#define GPIO150_OUT 0x102b45, BIT0 ++ ++#define GPIO151_PAD PAD_TTL_GPIO6 ++#define GPIO151_OEN 0x102b44, BIT1 ++#define GPIO151_IN 0x102b44, BIT2 ++#define GPIO151_OUT 0x102b44, BIT0 ++ ++#define GPIO152_PAD PAD_TTL_GPIO5 ++#define GPIO152_OEN 0x102b43, BIT1 ++#define GPIO152_IN 0x102b43, BIT2 ++#define GPIO152_OUT 0x102b43, BIT0 ++ ++#define GPIO153_PAD PAD_TTL_GPIO4 ++#define GPIO153_OEN 0x102b42, BIT1 ++#define GPIO153_IN 0x102b42, BIT2 ++#define GPIO153_OUT 0x102b42, BIT0 ++ ++#define GPIO154_PAD PAD_TTL_GPIO3 ++#define GPIO154_OEN 0x102b41, BIT1 ++#define GPIO154_IN 0x102b41, BIT2 ++#define GPIO154_OUT 0x102b41, BIT0 ++ ++#define GPIO155_PAD PAD_TTL_GPIO2 ++#define GPIO155_OEN 0x102b40, BIT1 ++#define GPIO155_IN 0x102b40, BIT2 ++#define GPIO155_OUT 0x102b40, BIT0 ++ ++#define GPIO156_PAD PAD_TTL_GPIO1 ++#define GPIO156_OEN 0x102b3F, BIT1 ++#define GPIO156_IN 0x102b3F, BIT2 ++#define GPIO156_OUT 0x102b3F, BIT0 ++ ++#define GPIO157_PAD PAD_TTL_GPIO0 ++#define GPIO157_OEN 0x102b3E, BIT1 ++#define GPIO157_IN 0x102b3E, BIT2 ++#define GPIO157_OUT 0x102b3E, BIT0 ++ ++#define GPIO158_PAD PAD_NAND_WPZ ++#define GPIO158_OEN 0x102b6A, BIT1 ++#define GPIO158_IN 0x102b6A, BIT2 ++#define GPIO158_OUT 0x102b6A, BIT0 ++ ++#define GPIO159_PAD PAD_NAND_WEZ ++#define GPIO159_OEN 0x102b72, BIT1 ++#define GPIO159_IN 0x102b72, BIT2 ++#define GPIO159_OUT 0x102b72, BIT0 ++ ++#define GPIO160_PAD PAD_NAND_ALE ++#define GPIO160_OEN 0x102b70, BIT1 ++#define GPIO160_IN 0x102b70, BIT2 ++#define GPIO160_OUT 0x102b70, BIT0 ++ ++#define GPIO161_PAD PAD_NAND_CLE ++#define GPIO161_OEN 0x102b71, BIT1 ++#define GPIO161_IN 0x102b71, BIT2 ++#define GPIO161_OUT 0x102b71, BIT0 ++ ++#define GPIO162_PAD PAD_NAND_CE3Z ++#define GPIO162_OEN 0x102b6F, BIT1 ++#define GPIO162_IN 0x102b6F, BIT2 ++#define GPIO162_OUT 0x102b6F, BIT0 ++ ++#define GPIO163_PAD PAD_NAND_CE2Z ++#define GPIO163_OEN 0x102b6E, BIT1 ++#define GPIO163_IN 0x102b6E, BIT2 ++#define GPIO163_OUT 0x102b6E, BIT0 ++ ++#define GPIO164_PAD PAD_NAND_CE1Z ++#define GPIO164_OEN 0x102b6D, BIT1 ++#define GPIO164_IN 0x102b6D, BIT2 ++#define GPIO164_OUT 0x102b6D, BIT0 ++ ++#define GPIO165_PAD PAD_NAND_CE0Z ++#define GPIO165_OEN 0x102b6C, BIT1 ++#define GPIO165_IN 0x102b6C, BIT2 ++#define GPIO165_OUT 0x102b6C, BIT0 ++ ++#define GPIO166_PAD PAD_NAND_REZ ++#define GPIO166_OEN 0x102b73, BIT1 ++#define GPIO166_IN 0x102b73, BIT2 ++#define GPIO166_OUT 0x102b73, BIT0 ++ ++#define GPIO167_PAD PAD_NAND_RBZ ++#define GPIO167_OEN 0x102b6B, BIT1 ++#define GPIO167_IN 0x102b6B, BIT2 ++#define GPIO167_OUT 0x102b6B, BIT0 ++ ++#define GPIO168_PAD PAD_NAND_DA0 ++#define GPIO168_OEN 0x102b62, BIT1 ++#define GPIO168_IN 0x102b62, BIT2 ++#define GPIO168_OUT 0x102b62, BIT0 ++ ++#define GPIO169_PAD PAD_NAND_DA1 ++#define GPIO169_OEN 0x102b63, BIT1 ++#define GPIO169_IN 0x102b63, BIT2 ++#define GPIO169_OUT 0x102b63, BIT0 ++ ++#define GPIO170_PAD PAD_NAND_DA2 ++#define GPIO170_OEN 0x102b64, BIT1 ++#define GPIO170_IN 0x102b64, BIT2 ++#define GPIO170_OUT 0x102b64, BIT0 ++ ++#define GPIO171_PAD PAD_NAND_DA3 ++#define GPIO171_OEN 0x102b65, BIT1 ++#define GPIO171_IN 0x102b65, BIT2 ++#define GPIO171_OUT 0x102b65, BIT0 ++ ++#define GPIO172_PAD PAD_NAND_DQS ++#define GPIO172_OEN 0x102b74, BIT1 ++#define GPIO172_IN 0x102b74, BIT2 ++#define GPIO172_OUT 0x102b74, BIT0 ++ ++#define GPIO173_PAD PAD_NAND_DA4 ++#define GPIO173_OEN 0x102b66, BIT1 ++#define GPIO173_IN 0x102b66, BIT2 ++#define GPIO173_OUT 0x102b66, BIT0 ++ ++#define GPIO174_PAD PAD_NAND_DA5 ++#define GPIO174_OEN 0x102b67, BIT1 ++#define GPIO174_IN 0x102b67, BIT2 ++#define GPIO174_OUT 0x102b67, BIT0 ++ ++#define GPIO175_PAD PAD_NAND_DA6 ++#define GPIO175_OEN 0x102b68, BIT1 ++#define GPIO175_IN 0x102b68, BIT2 ++#define GPIO175_OUT 0x102b68, BIT0 ++ ++#define GPIO176_PAD PAD_NAND_DA7 ++#define GPIO176_OEN 0x102b69, BIT1 ++#define GPIO176_IN 0x102b69, BIT2 ++#define GPIO176_OUT 0x102b69, BIT0 ++ ++#define GPIO177_PAD PAD_SD2_D1 ++#define GPIO177_OEN 0x102b86, BIT1 ++#define GPIO177_IN 0x102b86, BIT2 ++#define GPIO177_OUT 0x102b86, BIT0 ++ ++#define GPIO178_PAD PAD_SD2_D0 ++#define GPIO178_OEN 0x102b85, BIT1 ++#define GPIO178_IN 0x102b85, BIT2 ++#define GPIO178_OUT 0x102b85, BIT0 ++ ++#define GPIO179_PAD PAD_SD2_CLK ++#define GPIO179_OEN 0x102b88, BIT1 ++#define GPIO179_IN 0x102b88, BIT2 ++#define GPIO179_OUT 0x102b88, BIT0 ++ ++#define GPIO180_PAD PAD_SD2_CMD ++#define GPIO180_OEN 0x102b87, BIT1 ++#define GPIO180_IN 0x102b87, BIT2 ++#define GPIO180_OUT 0x102b87, BIT0 ++ ++#define GPIO181_PAD PAD_SD2_D3 ++#define GPIO181_OEN 0x102b8A, BIT1 ++#define GPIO181_IN 0x102b8A, BIT2 ++#define GPIO181_OUT 0x102b8A, BIT0 ++ ++#define GPIO182_PAD PAD_SD2_D2 ++#define GPIO182_OEN 0x102b89, BIT1 ++#define GPIO182_IN 0x102b89, BIT2 ++#define GPIO182_OUT 0x102b89, BIT0 ++ ++ ++ ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), ++ __GPIO(110), __GPIO(111), __GPIO(112), __GPIO(113), __GPIO(114), ++ __GPIO(115), __GPIO(116), __GPIO(117), __GPIO(118), __GPIO(119), ++ __GPIO(120), __GPIO(121), __GPIO(122), __GPIO(123), __GPIO(124), ++ __GPIO(125), __GPIO(126), __GPIO(127), __GPIO(128), __GPIO(129), ++ __GPIO(130), __GPIO(131), __GPIO(132), __GPIO(133), __GPIO(134), ++ __GPIO(135), __GPIO(136), __GPIO(137), __GPIO(138), __GPIO(139), ++ __GPIO(140), __GPIO(141), __GPIO(142), __GPIO(143), __GPIO(144), ++ __GPIO(145), __GPIO(146), __GPIO(147), __GPIO(148), __GPIO(149), ++ __GPIO(150), __GPIO(151), __GPIO(152), __GPIO(153), __GPIO(154), ++ __GPIO(155), __GPIO(156), __GPIO(157), __GPIO(158), __GPIO(159), ++ __GPIO(160), __GPIO(161), __GPIO(162), __GPIO(163), __GPIO(164), ++ __GPIO(165), __GPIO(166), __GPIO(167), __GPIO(168), __GPIO(169), ++ __GPIO(170), __GPIO(171), __GPIO(172), __GPIO(173), __GPIO(174), ++ __GPIO(175), __GPIO(176), __GPIO(177), __GPIO(178), __GPIO(179), ++ __GPIO(180), __GPIO(181), __GPIO(182), ++ ++}; ++#endif ++ ++#define MS_INT_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x80C80) ++#define MS_BACH1_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x89580) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++ MHal_GPIO_REG(REG_ALL_PAD_IN) &= ~BIT0; ++} ++ ++void MHal_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_GPIO_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_GPIO_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++void MHal_GPIO_PAD_32K_OUT(U8 u8Enable) ++{ ++ if (u8Enable) ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,ENABLE,BIT3); ++ else ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT3); ++} ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++ case PAD_PM_GPIO0: ++ case PAD_PM_GPIO1: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT0); ++ break; ++ ++ case PAD_PM_IIC_SDA: ++ case PAD_PM_IIC_SCL: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT2); ++ break; ++ ++ case PAD_PM_MIIC_SDA: ++ case PAD_PM_MIIC_SCL: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT4); ++ break; ++ ++ case PAD_PM_SPI_CK: ++ case PAD_PM_SPI_CZ0: ++ case PAD_PM_SPI_GPIO: ++ case PAD_PM_SPI_DI: ++ case PAD_PM_SPI_DO: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT5|BIT6|BIT7); ++ break; ++ ++ case PAD_ONOFF: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT1); ++ break; ++ ++ case PAD_CHRGDET: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT2); ++ break; ++ ++ case PAD_32K_OUT: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT3); ++ break; ++ ++ case PAD_IRIN: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT3); ++ break; ++ ++ case PAD_CEC: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_00,DISABLE,BIT1); ++ break; ++ ++ case PAD_PM_SD0_CDZ: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT4); ++ break; ++ ++ case PAD_PM_SD1_CDZ: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT5); ++ break; ++ ++ case PAD_PM_SD2_CDZ: ++ MHal_GPIO_WriteRegBit(REG_PMGPIO_01,DISABLE,BIT6); ++ break; ++ ++ case PAD_SD0_D1: ++ case PAD_SD0_D0: ++ case PAD_SD0_CLK: ++ case PAD_SD0_CMD: ++ case PAD_SD0_D3: ++ case PAD_SD0_D2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_04,DISABLE,BIT0); ++ break; ++ ++ case PAD_SD1_D1: ++ case PAD_SD1_D0: ++ case PAD_SD1_CLK: ++ case PAD_SD1_CMD: ++ case PAD_SD1_D3: ++ case PAD_SD1_D2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_04,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_A_GPS_EVENT: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT6); ++ break; ++ ++ case PAD_AFE1_SGN: ++ case PAD_AFE1_MAG: ++ case PAD_RFSPI_CZ1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT6); ++ break; ++ ++ case PAD_AFE0_SGN: ++ case PAD_AFE0_MAG: ++ case PAD_RFSPI_CZ0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT7); ++ break; ++ ++ case PAD_RFSPI_CLK: ++ case PAD_RFSPI_DATA: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT6|BIT7); ++ break; ++ ++ case PAD_BTI_RX_TX: ++ case PAD_BTI_DATA1: ++ case PAD_BTI_DATA0: ++ case PAD_BT_CLK_24M: ++ case PAD_BT_SPI_SCLK: ++ case PAD_BT_SPI_SDATA: ++ case PAD_BT_SPI_SENB: ++ case PAD_BT_CHIP_EN: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT1); ++ break; ++ ++ case PAD_SR_D0: ++ case PAD_SR_D1: ++ case PAD_SR_D2: ++ case PAD_SR_D3: ++ case PAD_SR_D4: ++ case PAD_SR_D5: ++ case PAD_SR_D6: ++ case PAD_SR_D7: ++ case PAD_SR_PCLK: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT0); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT4); ++ break; ++ ++ case PAD_SR_HSYNC: ++ case PAD_SR_STROBE: ++ case PAD_SR_VSYNC: ++ case PAD_SR_RST: ++ case PAD_SR_PWRDN: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT0); ++ break; ++ ++ case PAD_GPIO33: ++ case PAD_GPIO32: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO31: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT7); ++ break; ++ ++ case PAD_GPIO30: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT6); ++ break; ++ ++ case PAD_GPIO29: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT5); ++ break; ++ ++ case PAD_GPIO28: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT4); ++ OUTREGMSK16(GET_REG_ADDR(MS_BACH1_BASE, 0x16),0x01,0x01); ++ break; ++ ++ case PAD_GPIO27: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_GPIO26: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_GPIO25: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_GPIO24: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ break; ++ ++ case PAD_UART_RX1: ++ case PAD_UART_TX1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT2); ++ break; ++ ++ case PAD_UART_RX2: ++ case PAD_UART_TX2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT3); ++ break; ++ ++ case PAD_UART_RX3: ++ case PAD_UART_TX3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT4); ++ break; ++ ++ case PAD_UART_RX4: ++ case PAD_UART_TX4: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT5); ++ break; ++ ++ case PAD_UART_CTS2: ++ case PAD_UART_RTS2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_CS1Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_03,DISABLE,BIT0); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_CS0Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT4|BIT6); ++ break; ++ ++ case PAD_MPIF_D0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_D1: ++ case PAD_MPIF_D2: ++ case PAD_MPIF_D3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_CK: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_MPIF_BUSY: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT4|BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT7); ++ break; ++ ++ case PAD_MIIC0_SDA: ++ case PAD_MIIC0_SCL: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT2); ++ break; ++ ++ case PAD_GPIO23: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT6); ++ break; ++ ++ case PAD_GPIO13: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT3); ++ break; ++ ++ case PAD_GPIO10: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT0); ++ break; ++ ++ case PAD_GPIO9: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT2); ++ break; ++ ++ case PAD_GPIO8: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,DISABLE,BIT0); ++ break; ++ ++ case PAD_GPIO6: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO5: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT5); ++ break; ++ ++ case PAD_GPIO4: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT4); ++ break; ++ ++ case PAD_GPIO3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT3); ++ break; ++ ++ case PAD_GPIO2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT2); ++ break; ++ ++ case PAD_GPIO1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT1); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT1); ++ break; ++ ++ case PAD_GPIO0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT0); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2A,DISABLE,BIT0); ++ break; ++ ++ case PAD_SPDIF_OUT: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_05,DISABLE,BIT6); ++ break; ++ ++ case PAD_IIS_TRX_BCK: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_IIS_TRX_WS: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_IIS_TRX_OUT: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_IIS_TRX_IN: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_00,DISABLE,BIT2|BIT3|BIT5|BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT3|BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT2|BIT3); ++ break; ++ ++ case PAD_UART_RX5: ++ case PAD_UART_TX5: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_06,DISABLE,BIT6); ++ break; ++ ++ case PAD_UART_CTS1: ++ case PAD_UART_RTS1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_01,DISABLE,BIT5); ++ break; ++ ++ case PAD_TCON_GPIO7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT7); ++ break; ++ ++ case PAD_TCON_GPIO5: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT0); ++ break; ++ ++ case PAD_TCON_GPIO3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT2); ++ break; ++ ++ case PAD_TCON_GPIO2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT6); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT2); ++ break; ++ ++ case PAD_TCON_GPIO1: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT1); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT2); ++ break; ++ ++ case PAD_TCON_GPIO0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT3); ++ break; ++ ++ case PAD_TTL_GPIO11: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO10: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO9: ++ case PAD_TTL_GPIO8: ++ case PAD_TTL_GPIO7: ++ case PAD_TTL_GPIO6: ++ case PAD_TTL_GPIO5: ++ case PAD_TTL_GPIO4: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_22,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_TTL_GPIO1: ++ case PAD_TTL_GPIO0: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT5); ++ break; ++ ++ case PAD_NAND_WPZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_ALE: ++ case PAD_NAND_CLE: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_CE3Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT1); ++ break; ++ ++ case PAD_NAND_CE2Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_2C,DISABLE,BIT0); ++ break; ++ ++ case PAD_NAND_CE1Z: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT7); ++ break; ++ ++ case PAD_NAND_CE0Z: ++ case PAD_NAND_REZ: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_RBZ: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_NAND_DQS: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ break; ++ ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT6); ++ break; ++ ++ case PAD_SD2_D1: ++ case PAD_SD2_D0: ++ case PAD_SD2_CLK: ++ case PAD_SD2_CMD: ++ case PAD_SD2_D3: ++ case PAD_SD2_D2: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_04,DISABLE,BIT4); ++ break; ++ ++ case PAD_PM_SD_GPIO: ++ case PAD_HOTPLUG: ++ case PAD_BATOK: ++ case PAD_PMIC_CHIPEN: ++ case PAD_PMIC_STDBYN: ++ case PAD_PMIC_INT: ++ case PAD_GPIO34: ++ case PAD_GPIO35: ++ case PAD_GPIO36: ++ case PAD_GPIO37: ++ case PAD_GPIO38: ++ case PAD_GPIO22: ++ case PAD_GPIO21: ++ case PAD_GPIO20: ++ case PAD_GPIO19: ++ case PAD_GPIO18: ++ case PAD_GPIO17: ++ case PAD_GPIO16: ++ case PAD_GPIO15: ++ case PAD_GPIO14: ++ case PAD_GPIO12: ++ case PAD_GPIO11: ++ case PAD_TESTPIN: ++ case PAD_TCON_GPIO8: ++ case PAD_TCON_GPIO6: ++ case PAD_TCON_GPIO4: ++ default: ++ break; ++ } ++} ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_GPIO_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO7: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_26,DISABLE,BIT7); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_GPIO_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break; ++ default: ++ break; ++ } ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u8IndexGPIO) ++ { ++ case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/mstar/gpio/cedric/mhal_gpio.h b/drivers/mstar/gpio/cedric/mhal_gpio.h +new file mode 100644 +index 00000000..b2cc867a +--- /dev/null ++++ b/drivers/mstar/gpio/cedric/mhal_gpio.h +@@ -0,0 +1,62 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define IO_PHYS 0x1F000000 ++#define MS_BASE_REG_RIU_PA IO_PHYS ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk); ++extern U8 MHal_GPIO_ReadRegBit(U32 u32Reg, U8 u8BitMsk); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/cedric/mhal_gpio_reg.h b/drivers/mstar/gpio/cedric/mhal_gpio_reg.h +new file mode 100644 +index 00000000..8d7523e3 +--- /dev/null ++++ b/drivers/mstar/gpio/cedric/mhal_gpio_reg.h +@@ -0,0 +1,79 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++#define GPIO_UNIT_NUM 198 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define REG_MIPS_BASE 0xFD000000//Use 8 bit addressing ++ ++#define REG_ALL_PAD_IN (0x101ea0) //set all pads (except SPI) as input ++#define REG_LVDS_BASE (0x103200) ++#define REG_LVDS_BANK REG_LVDS_BASE ++ ++ ++////8 bit define ++#define REG_PMGPIO_00 0x0f00 ++#define REG_PMGPIO_01 0x0f01 ++#define REG_GPIO1_00 0x101A00////0 ++#define REG_GPIO1_01 0x101A01 ++#define REG_GPIO1_02 0x101A02////1 ++#define REG_GPIO1_03 0x101A03 ++#define REG_GPIO1_04 0x101A04////2 ++#define REG_GPIO1_05 0x101A05 ++#define REG_GPIO1_06 0x101A06////3 ++#define REG_GPIO1_07 0x101A07 ++#define REG_GPIO1_20 0x101A20 ////10 ++#define REG_GPIO1_21 0x101A21 ++#define REG_GPIO1_22 0x101A22 ////11 ++#define REG_GPIO1_23 0x101A23 ++#define REG_GPIO1_24 0x101A24 ////12 ++#define REG_GPIO1_25 0x101A25 ++#define REG_GPIO1_26 0x101A26 ////13 ++#define REG_GPIO1_27 0x101A27 ++#define REG_GPIO1_2A 0x101A2A ////15 ++#define REG_GPIO1_2B 0x101A2B ++#define REG_GPIO1_2C 0x101A2C ////16 ++#define REG_GPIO1_2D 0x101A2D ++ ++ ++ ++ ++#define GPIO_OEN 0 //set o to nake output ++#define GPIO_ODN 1 ++ ++#define IN_HIGH 1 //input high ++#define IN_LOW 0 //input low ++ ++#define OUT_HIGH 1 //output high ++#define OUT_LOW 0 //output low ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_MIPS_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/infinity/Makefile b/drivers/mstar/gpio/infinity/Makefile +new file mode 100644 +index 00000000..f3ae0df0 +--- /dev/null ++++ b/drivers/mstar/gpio/infinity/Makefile +@@ -0,0 +1,20 @@ ++# ++# Makefile for MStar GPIO HAL drivers. ++# ++ ++ ++ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++include $(TOP_DIR)/modules.mk ++endif ++ ++ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/mstar/common ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/gpio ++EXTRA_CFLAGS += -Idrivers/mstar/gpio/$(CONFIG_MSTAR_CHIP_NAME) ++ ++# files ++#obj-$(CONFIG_MSTAR_GPIO) += mhal_gpio.o +diff --git a/drivers/mstar/gpio/infinity/mhal_gpio.c b/drivers/mstar/gpio/infinity/mhal_gpio.c +new file mode 100644 +index 00000000..5967c185 +--- /dev/null ++++ b/drivers/mstar/gpio/infinity/mhal_gpio.c +@@ -0,0 +1,1103 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if 1 ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++//infinity gpio reg start ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103c00, BIT5 ++#define GPIO0_IN 0x103c00, BIT0 ++#define GPIO0_OUT 0x103c00, BIT4 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103c02, BIT5 ++#define GPIO1_IN 0x103c02, BIT0 ++#define GPIO1_OUT 0x103c02, BIT4 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103c04, BIT5 ++#define GPIO2_IN 0x103c04, BIT0 ++#define GPIO2_OUT 0x103c04, BIT4 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103c06, BIT5 ++#define GPIO3_IN 0x103c06, BIT0 ++#define GPIO3_OUT 0x103c06, BIT4 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103c08, BIT5 ++#define GPIO4_IN 0x103c08, BIT0 ++#define GPIO4_OUT 0x103c08, BIT4 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103c0a, BIT5 ++#define GPIO5_IN 0x103c0a, BIT0 ++#define GPIO5_OUT 0x103c0a, BIT4 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103c0c, BIT5 ++#define GPIO6_IN 0x103c0c, BIT0 ++#define GPIO6_OUT 0x103c0c, BIT4 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103c0e, BIT5 ++#define GPIO7_IN 0x103c0e, BIT0 ++#define GPIO7_OUT 0x103c0e, BIT4 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103c10, BIT5 ++#define GPIO8_IN 0x103c10, BIT0 ++#define GPIO8_OUT 0x103c10, BIT4 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103c12, BIT5 ++#define GPIO9_IN 0x103c12, BIT0 ++#define GPIO9_OUT 0x103c12, BIT4 ++ ++#define GPIO10_PAD PAD_GPIO10 ++#define GPIO10_OEN 0x103c14, BIT5 ++#define GPIO10_IN 0x103c14, BIT0 ++#define GPIO10_OUT 0x103c14, BIT4 ++ ++#define GPIO11_PAD PAD_GPIO11 ++#define GPIO11_OEN 0x103c16, BIT5 ++#define GPIO11_IN 0x103c16, BIT0 ++#define GPIO11_OUT 0x103c16, BIT4 ++ ++#define GPIO12_PAD PAD_GPIO12 ++#define GPIO12_OEN 0x103c18, BIT5 ++#define GPIO12_IN 0x103c18, BIT0 ++#define GPIO12_OUT 0x103c18, BIT4 ++ ++#define GPIO13_PAD PAD_GPIO13 ++#define GPIO13_OEN 0x103c1a, BIT5 ++#define GPIO13_IN 0x103c1a, BIT0 ++#define GPIO13_OUT 0x103c1a, BIT4 ++ ++#define GPIO14_PAD PAD_GPIO14 ++#define GPIO14_OEN 0x103c1c, BIT5 ++#define GPIO14_IN 0x103c1c, BIT0 ++#define GPIO14_OUT 0x103c1c, BIT4 ++ ++#define GPIO15_PAD PAD_GPIO15 ++#define GPIO15_OEN 0x103c1e, BIT5 ++#define GPIO15_IN 0x103c1e, BIT0 ++#define GPIO15_OUT 0x103c1e, BIT4 ++ ++#define GPIO16_PAD PAD_PWM0 ++#define GPIO16_OEN 0x103c20, BIT5 ++#define GPIO16_IN 0x103c20, BIT0 ++#define GPIO16_OUT 0x103c20, BIT4 ++ ++#define GPIO17_PAD PAD_PWM1 ++#define GPIO17_OEN 0x103c22, BIT5 ++#define GPIO17_IN 0x103c22, BIT0 ++#define GPIO17_OUT 0x103c22, BIT4 ++ ++#define GPIO18_PAD PAD_FUART_RX ++#define GPIO18_OEN 0x103c28, BIT5 ++#define GPIO18_IN 0x103c28, BIT0 ++#define GPIO18_OUT 0x103c28, BIT4 ++ ++#define GPIO19_PAD PAD_FUART_TX ++#define GPIO19_OEN 0x103c2a, BIT5 ++#define GPIO19_IN 0x103c2a, BIT0 ++#define GPIO19_OUT 0x103c2a, BIT4 ++ ++#define GPIO20_PAD PAD_FUART_CTS ++#define GPIO20_OEN 0x103c2c, BIT5 ++#define GPIO20_IN 0x103c2c, BIT0 ++#define GPIO20_OUT 0x103c2c, BIT4 ++ ++#define GPIO21_PAD PAD_FUART_RTS ++#define GPIO21_OEN 0x103c2e, BIT5 ++#define GPIO21_IN 0x103c2e, BIT0 ++#define GPIO21_OUT 0x103c2e, BIT4 ++ ++#define GPIO22_PAD PAD_UART0_RX ++#define GPIO22_OEN 0x103c30, BIT5 ++#define GPIO22_IN 0x103c30, BIT0 ++#define GPIO22_OUT 0x103c30, BIT4 ++ ++#define GPIO23_PAD PAD_UART0_TX ++#define GPIO23_OEN 0x103c32, BIT5 ++#define GPIO23_IN 0x103c32, BIT0 ++#define GPIO23_OUT 0x103c32, BIT4 ++ ++#define GPIO24_PAD PAD_UART1_RX ++#define GPIO24_OEN 0x103c34, BIT5 ++#define GPIO24_IN 0x103c34, BIT0 ++#define GPIO24_OUT 0x103c34, BIT4 ++ ++#define GPIO25_PAD PAD_UART1_TX ++#define GPIO25_OEN 0x103c36, BIT5 ++#define GPIO25_IN 0x103c36, BIT0 ++#define GPIO25_OUT 0x103c36, BIT4 ++ ++#define GPIO26_PAD PAD_SR_IO00 ++#define GPIO26_OEN 0x103c40, BIT5 ++#define GPIO26_IN 0x103c40, BIT0 ++#define GPIO26_OUT 0x103c40, BIT4 ++ ++#define GPIO27_PAD PAD_SR_IO01 ++#define GPIO27_OEN 0x103c42, BIT5 ++#define GPIO27_IN 0x103c42, BIT0 ++#define GPIO27_OUT 0x103c42, BIT4 ++ ++#define GPIO28_PAD PAD_SR_IO02 ++#define GPIO28_OEN 0x103c44, BIT5 ++#define GPIO28_IN 0x103c44, BIT0 ++#define GPIO28_OUT 0x103c44, BIT4 ++ ++#define GPIO29_PAD PAD_SR_IO03 ++#define GPIO29_OEN 0x103c46, BIT5 ++#define GPIO29_IN 0x103c46, BIT0 ++#define GPIO29_OUT 0x103c46, BIT4 ++ ++#define GPIO30_PAD PAD_SR_IO04 ++#define GPIO30_OEN 0x103c48, BIT5 ++#define GPIO30_IN 0x103c48, BIT0 ++#define GPIO30_OUT 0x103c48, BIT4 ++ ++#define GPIO31_PAD PAD_SR_IO05 ++#define GPIO31_OEN 0x103c4a, BIT5 ++#define GPIO31_IN 0x103c4a, BIT0 ++#define GPIO31_OUT 0x103c4a, BIT4 ++ ++#define GPIO32_PAD PAD_SR_IO06 ++#define GPIO32_OEN 0x103c4c, BIT5 ++#define GPIO32_IN 0x103c4c, BIT0 ++#define GPIO32_OUT 0x103c4c, BIT4 ++ ++#define GPIO33_PAD PAD_SR_IO07 ++#define GPIO33_OEN 0x103c4e, BIT5 ++#define GPIO33_IN 0x103c4e, BIT0 ++#define GPIO33_OUT 0x103c4e, BIT4 ++ ++#define GPIO34_PAD PAD_SR_IO08 ++#define GPIO34_OEN 0x103c50, BIT5 ++#define GPIO34_IN 0x103c50, BIT0 ++#define GPIO34_OUT 0x103c50, BIT4 ++ ++#define GPIO35_PAD PAD_SR_IO09 ++#define GPIO35_OEN 0x103c52, BIT5 ++#define GPIO35_IN 0x103c52, BIT0 ++#define GPIO35_OUT 0x103c52, BIT4 ++ ++#define GPIO36_PAD PAD_SR_IO10 ++#define GPIO36_OEN 0x103c54, BIT5 ++#define GPIO36_IN 0x103c54, BIT0 ++#define GPIO36_OUT 0x103c54, BIT4 ++ ++#define GPIO37_PAD PAD_SR_IO11 ++#define GPIO37_OEN 0x103c56, BIT5 ++#define GPIO37_IN 0x103c56, BIT0 ++#define GPIO37_OUT 0x103c56, BIT4 ++ ++#define GPIO38_PAD PAD_SR_IO12 ++#define GPIO38_OEN 0x103c58, BIT5 ++#define GPIO38_IN 0x103c58, BIT0 ++#define GPIO38_OUT 0x103c58, BIT4 ++ ++#define GPIO39_PAD PAD_SR_IO13 ++#define GPIO39_OEN 0x103c5a, BIT5 ++#define GPIO39_IN 0x103c5a, BIT0 ++#define GPIO39_OUT 0x103c5a, BIT4 ++ ++#define GPIO40_PAD PAD_SR_IO14 ++#define GPIO40_OEN 0x103c5c, BIT5 ++#define GPIO40_IN 0x103c5c, BIT0 ++#define GPIO40_OUT 0x103c5c, BIT4 ++ ++#define GPIO41_PAD PAD_SR_IO15 ++#define GPIO41_OEN 0x103c5e, BIT5 ++#define GPIO41_IN 0x103c5e, BIT0 ++#define GPIO41_OUT 0x103c5e, BIT4 ++ ++#define GPIO42_PAD PAD_SR_IO16 ++#define GPIO42_OEN 0x103c60, BIT5 ++#define GPIO42_IN 0x103c60, BIT0 ++#define GPIO42_OUT 0x103c60, BIT4 ++ ++#define GPIO43_PAD PAD_SR_IO17 ++#define GPIO43_OEN 0x103c62, BIT5 ++#define GPIO43_IN 0x103c62, BIT0 ++#define GPIO43_OUT 0x103c62, BIT4 ++ ++#define GPIO44_PAD PAD_NAND_CEZ ++#define GPIO44_OEN 0x103c80, BIT5 ++#define GPIO44_IN 0x103c80, BIT0 ++#define GPIO44_OUT 0x103c80, BIT4 ++ ++#define GPIO45_PAD PAD_NAND_ALE ++#define GPIO45_OEN 0x103c82, BIT5 ++#define GPIO45_IN 0x103c82, BIT0 ++#define GPIO45_OUT 0x103c82, BIT4 ++ ++#define GPIO46_PAD PAD_NAND_CLE ++#define GPIO46_OEN 0x103c84, BIT5 ++#define GPIO46_IN 0x103c84, BIT0 ++#define GPIO46_OUT 0x103c84, BIT4 ++ ++#define GPIO47_PAD PAD_NAND_WEZ ++#define GPIO47_OEN 0x103c86, BIT5 ++#define GPIO47_IN 0x103c86, BIT0 ++#define GPIO47_OUT 0x103c86, BIT4 ++ ++#define GPIO48_PAD PAD_NAND_WPZ ++#define GPIO48_OEN 0x103c88, BIT5 ++#define GPIO48_IN 0x103c88, BIT0 ++#define GPIO48_OUT 0x103c88, BIT4 ++ ++#define GPIO49_PAD PAD_NAND_REZ ++#define GPIO49_OEN 0x103c8a, BIT5 ++#define GPIO49_IN 0x103c8a, BIT0 ++#define GPIO49_OUT 0x103c8a, BIT4 ++ ++#define GPIO50_PAD PAD_NAND_RBZ ++#define GPIO50_OEN 0x103c8c, BIT5 ++#define GPIO50_IN 0x103c8c, BIT0 ++#define GPIO50_OUT 0x103c8c, BIT4 ++ ++#define GPIO51_PAD PAD_NAND_DA0 ++#define GPIO51_OEN 0x103c8e, BIT5 ++#define GPIO51_IN 0x103c8e, BIT0 ++#define GPIO51_OUT 0x103c8e, BIT4 ++ ++#define GPIO52_PAD PAD_NAND_DA1 ++#define GPIO52_OEN 0x103c90, BIT5 ++#define GPIO52_IN 0x103c90, BIT0 ++#define GPIO52_OUT 0x103c90, BIT4 ++ ++#define GPIO53_PAD PAD_NAND_DA2 ++#define GPIO53_OEN 0x103c92, BIT5 ++#define GPIO53_IN 0x103c92, BIT0 ++#define GPIO53_OUT 0x103c92, BIT4 ++ ++#define GPIO54_PAD PAD_NAND_DA3 ++#define GPIO54_OEN 0x103c94, BIT5 ++#define GPIO54_IN 0x103c94, BIT0 ++#define GPIO54_OUT 0x103c94, BIT4 ++ ++#define GPIO55_PAD PAD_NAND_DA4 ++#define GPIO55_OEN 0x103c96, BIT5 ++#define GPIO55_IN 0x103c96, BIT0 ++#define GPIO55_OUT 0x103c96, BIT4 ++ ++#define GPIO56_PAD PAD_NAND_DA5 ++#define GPIO56_OEN 0x103c98, BIT5 ++#define GPIO56_IN 0x103c98, BIT0 ++#define GPIO56_OUT 0x103c98, BIT4 ++ ++#define GPIO57_PAD PAD_NAND_DA6 ++#define GPIO57_OEN 0x103c9a, BIT5 ++#define GPIO57_IN 0x103c9a, BIT0 ++#define GPIO57_OUT 0x103c9a, BIT4 ++ ++#define GPIO58_PAD PAD_NAND_DA7 ++#define GPIO58_OEN 0x103c9c, BIT5 ++#define GPIO58_IN 0x103c9c, BIT0 ++#define GPIO58_OUT 0x103c9c, BIT4 ++ ++#define GPIO59_PAD PAD_SD_CLK ++#define GPIO59_OEN 0x103ca0, BIT5 ++#define GPIO59_IN 0x103ca0, BIT0 ++#define GPIO59_OUT 0x103ca0, BIT4 ++ ++#define GPIO60_PAD PAD_SD_CMD ++#define GPIO60_OEN 0x103ca2, BIT5 ++#define GPIO60_IN 0x103ca2, BIT0 ++#define GPIO60_OUT 0x103ca2, BIT4 ++ ++#define GPIO61_PAD PAD_SD_D0 ++#define GPIO61_OEN 0x103ca4, BIT5 ++#define GPIO61_IN 0x103ca4, BIT0 ++#define GPIO61_OUT 0x103ca4, BIT4 ++ ++#define GPIO62_PAD PAD_SD_D1 ++#define GPIO62_OEN 0x103ca6, BIT5 ++#define GPIO62_IN 0x103ca6, BIT0 ++#define GPIO62_OUT 0x103ca6, BIT4 ++ ++#define GPIO63_PAD PAD_SD_D2 ++#define GPIO63_OEN 0x103ca8, BIT5 ++#define GPIO63_IN 0x103ca8, BIT0 ++#define GPIO63_OUT 0x103ca8, BIT4 ++ ++#define GPIO64_PAD PAD_SD_D3 ++#define GPIO64_OEN 0x103caa, BIT5 ++#define GPIO64_IN 0x103caa, BIT0 ++#define GPIO64_OUT 0x103caa, BIT4 ++ ++#define GPIO65_PAD PAD_I2C0_SCL ++#define GPIO65_OEN 0x103cc0, BIT5 ++#define GPIO65_IN 0x103cc0, BIT0 ++#define GPIO65_OUT 0x103cc0, BIT4 ++ ++#define GPIO66_PAD PAD_I2C0_SDA ++#define GPIO66_OEN 0x103cc2, BIT5 ++#define GPIO66_IN 0x103cc2, BIT0 ++#define GPIO66_OUT 0x103cc2, BIT4 ++ ++#define GPIO67_PAD PAD_I2C1_SCL ++#define GPIO67_OEN 0x103cc4, BIT5 ++#define GPIO67_IN 0x103cc4, BIT0 ++#define GPIO67_OUT 0x103cc4, BIT4 ++ ++#define GPIO68_PAD PAD_I2C1_SDA ++#define GPIO68_OEN 0x103cc6, BIT5 ++#define GPIO68_IN 0x103cc6, BIT0 ++#define GPIO68_OUT 0x103cc6, BIT4 ++ ++#define GPIO69_PAD PAD_SPI0_CZ ++#define GPIO69_OEN 0x103ce0, BIT5 ++#define GPIO69_IN 0x103ce0, BIT0 ++#define GPIO69_OUT 0x103ce0, BIT4 ++ ++#define GPIO70_PAD PAD_SPI0_CK ++#define GPIO70_OEN 0x103ce2, BIT5 ++#define GPIO70_IN 0x103ce2, BIT0 ++#define GPIO70_OUT 0x103ce2, BIT4 ++ ++#define GPIO71_PAD PAD_SPI0_DI ++#define GPIO71_OEN 0x103ce4, BIT5 ++#define GPIO71_IN 0x103ce4, BIT0 ++#define GPIO71_OUT 0x103ce4, BIT4 ++ ++#define GPIO72_PAD PAD_SPI0_DO ++#define GPIO72_OEN 0x103ce6, BIT5 ++#define GPIO72_IN 0x103ce6, BIT0 ++#define GPIO72_OUT 0x103ce6, BIT4 ++ ++#define GPIO73_PAD PAD_SPI1_CZ ++#define GPIO73_OEN 0x103ce8, BIT5 ++#define GPIO73_IN 0x103ce8, BIT0 ++#define GPIO73_OUT 0x103ce8, BIT4 ++ ++#define GPIO74_PAD PAD_SPI1_CK ++#define GPIO74_OEN 0x103cea, BIT5 ++#define GPIO74_IN 0x103cea, BIT0 ++#define GPIO74_OUT 0x103cea, BIT4 ++ ++#define GPIO75_PAD PAD_SPI1_DI ++#define GPIO75_OEN 0x103cec, BIT5 ++#define GPIO75_IN 0x103cec, BIT0 ++#define GPIO75_OUT 0x103cec, BIT4 ++ ++#define GPIO76_PAD PAD_SPI1_DO ++#define GPIO76_OEN 0x103cee, BIT5 ++#define GPIO76_IN 0x103cee, BIT0 ++#define GPIO76_OUT 0x103cee, BIT4 ++//infinity pm gpio ++#define GPIO77_PAD PAD_PM_SD_CDZ ++#define GPIO77_OEN 0x0f8e, BIT0 ++#define GPIO77_IN 0x0f8e, BIT2 ++#define GPIO77_OUT 0x0f8e, BIT1 ++ ++#define GPIO78_PAD PAD_PM_IRIN ++#define GPIO78_OEN 0x0f28, BIT0 ++#define GPIO78_IN 0x0f28, BIT2 ++#define GPIO78_OUT 0x0f28, BIT1 ++ ++#define GPIO79_PAD PAD_PM_GPIO0 ++#define GPIO79_OEN 0x0f00, BIT0 ++#define GPIO79_IN 0x0f00, BIT2 ++#define GPIO79_OUT 0x0f00, BIT1 ++ ++#define GPIO80_PAD PAD_PM_GPIO1 ++#define GPIO80_OEN 0x0f02, BIT0 ++#define GPIO80_IN 0x0f02, BIT2 ++#define GPIO80_OUT 0x0f02, BIT1 ++ ++#define GPIO81_PAD PAD_PM_GPIO2 ++#define GPIO81_OEN 0x0f04, BIT0 ++#define GPIO81_IN 0x0f04, BIT2 ++#define GPIO81_OUT 0x0f04, BIT1 ++ ++#define GPIO82_PAD PAD_PM_GPIO3 ++#define GPIO82_OEN 0x0f06, BIT0 ++#define GPIO82_IN 0x0f06, BIT2 ++#define GPIO82_OUT 0x0f06, BIT1 ++ ++#define GPIO83_PAD PAD_PM_GPIO4 ++#define GPIO83_OEN 0x0f08, BIT0 ++#define GPIO83_IN 0x0f08, BIT2 ++#define GPIO83_OUT 0x0f08, BIT1 ++ ++#define GPIO84_PAD PAD_PM_GPIO5 ++#define GPIO84_OEN 0x0f0a, BIT0 ++#define GPIO84_IN 0x0f0a, BIT2 ++#define GPIO84_OUT 0x0f0a, BIT1 ++ ++#define GPIO85_PAD PAD_PM_GPIO6 ++#define GPIO85_OEN 0x0f0c, BIT0 ++#define GPIO85_IN 0x0f0c, BIT2 ++#define GPIO85_OUT 0x0f0c, BIT1 ++ ++#define GPIO86_PAD PAD_PM_GPIO7 ++#define GPIO86_OEN 0x0f0e, BIT0 ++#define GPIO86_IN 0x0f0e, BIT2 ++#define GPIO86_OUT 0x0f0e, BIT1 ++ ++#define GPIO87_PAD PAD_PM_GPIO8 ++#define GPIO87_OEN 0x0f10, BIT0 ++#define GPIO87_IN 0x0f10, BIT2 ++#define GPIO87_OUT 0x0f10, BIT1 ++ ++#define GPIO88_PAD PAD_PM_GPIO9 ++#define GPIO88_OEN 0x0f12, BIT0 ++#define GPIO88_IN 0x0f12, BIT2 ++#define GPIO88_OUT 0x0f12, BIT1 ++ ++#define GPIO89_PAD PAD_PM_GPIO10 ++#define GPIO89_OEN 0x0f14, BIT0 ++#define GPIO89_IN 0x0f14, BIT2 ++#define GPIO89_OUT 0x0f14, BIT1 ++ ++#define GPIO90_PAD PAD_PM_SPI_CZ ++#define GPIO90_OEN 0x0f30, BIT0 ++#define GPIO90_IN 0x0f30, BIT2 ++#define GPIO90_OUT 0x0f30, BIT1 ++ ++#define GPIO91_PAD PAD_PM_SPI_CK ++#define GPIO91_OEN 0x0f32, BIT0 ++#define GPIO91_IN 0x0f32, BIT2 ++#define GPIO91_OUT 0x0f32, BIT1 ++ ++#define GPIO92_PAD PAD_PM_SPI_DI ++#define GPIO92_OEN 0x0f34, BIT0 ++#define GPIO92_IN 0x0f34, BIT2 ++#define GPIO92_OUT 0x0f34, BIT1 ++ ++#define GPIO93_PAD PAD_PM_SPI_DO ++#define GPIO93_OEN 0x0f36, BIT0 ++#define GPIO93_IN 0x0f36, BIT2 ++#define GPIO93_OUT 0x0f36, BIT1 ++ ++#define GPIO94_PAD PAD_PM_SPI_WPZ ++#define GPIO94_OEN 0x0f88, BIT0 ++#define GPIO94_IN 0x0f88, BIT2 ++#define GPIO94_OUT 0x0f88, BIT1 ++ ++#define GPIO95_PAD PAD_PM_SPI_HLD ++#define GPIO95_OEN 0x0f8a, BIT0 ++#define GPIO95_IN 0x0f8a, BIT2 ++#define GPIO95_OUT 0x0f8a, BIT1 ++ ++#define GPIO96_PAD PAD_PM_LED0 ++#define GPIO96_OEN 0x0f94, BIT0 ++#define GPIO96_IN 0x0f94, BIT2 ++#define GPIO96_OUT 0x0f94, BIT1 ++ ++#define GPIO97_PAD PAD_PM_LED1 ++#define GPIO97_OEN 0x0f96, BIT0 ++#define GPIO97_IN 0x0f96, BIT2 ++#define GPIO97_OUT 0x0f96, BIT1 ++//SAR GPIO ++#define GPIO98_PAD PAD_SAR_GPIO0 ++#define GPIO98_OEN 0x1423, BIT0 ++#define GPIO98_IN 0x1425, BIT0 ++#define GPIO98_OUT 0x1424, BIT0 ++ ++#define GPIO99_PAD PAD_SAR_GPIO1 ++#define GPIO99_OEN 0x1423, BIT1 ++#define GPIO99_IN 0x1425, BIT1 ++#define GPIO99_OUT 0x1424, BIT1 ++ ++#define GPIO100_PAD PAD_SAR_GPIO2 ++#define GPIO100_OEN 0x1423, BIT2 ++#define GPIO100_IN 0x1425, BIT2 ++#define GPIO100_OUT 0x1424, BIT2 ++ ++#define GPIO101_PAD PAD_SAR_GPIO3 ++#define GPIO101_OEN 0x1423, BIT3 ++#define GPIO101_IN 0x1425, BIT3 ++#define GPIO101_OUT 0x1424, BIT3 ++//ETH GPIO ++#define GPIO102_PAD PAD_ETH_RN ++#define GPIO102_OEN 0x33ee, BIT4 ++#define GPIO102_IN 0x33f0, BIT4 ++#define GPIO102_OUT 0x33f0, BIT0 ++ ++#define GPIO103_PAD PAD_ETH_RP ++#define GPIO103_OEN 0x33ee, BIT5 ++#define GPIO103_IN 0x33f0, BIT5 ++#define GPIO103_OUT 0x33f0, BIT1 ++ ++#define GPIO104_PAD PAD_ETH_TN ++#define GPIO104_OEN 0x33ee, BIT6 ++#define GPIO104_IN 0x33f0, BIT6 ++#define GPIO104_OUT 0x33f0, BIT2 ++ ++#define GPIO105_PAD PAD_ETH_TP ++#define GPIO105_OEN 0x33ee, BIT7 ++#define GPIO105_IN 0x33f0, BIT7 ++#define GPIO105_OUT 0x33f0, BIT3 ++//USB GPIO ++#define GPIO106_PAD PAD_USB_DM ++#define GPIO106_OEN 0x14210a, BIT4 ++#define GPIO106_IN 0x142131, BIT5 ++#define GPIO106_OUT 0x14210a, BIT2 ++ ++#define GPIO107_PAD PAD_USB_DP ++#define GPIO107_OEN 0x14210a, BIT5 ++#define GPIO107_IN 0x142131, BIT4 ++#define GPIO107_OUT 0x14210a, BIT3 ++//infinity gpio reg end ++ ++U32 gChipBaseAddr=0xFD203C00; ++U32 gPmSleepBaseAddr=0xFD001E00; ++U32 gSarBaseAddr=0xFD002800; ++U32 gRIUBaseAddr=0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), ++}; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++// printk("MHal_GPIO_Init gBaseAddr=%x\n",gPadBaseAddr); ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_CHIPTOP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_CHIPTOP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_CHIPTOP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_CHIPTOP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_CHIPTOP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_CHIPTOP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_CHIPTOP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_PM_SLEEP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_PM_SLEEP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_PM_SLEEP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_SAR_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_SAR_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_SAR_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO0: ++ case PAD_GPIO1: ++ case PAD_GPIO2: ++ case PAD_GPIO3: ++ //MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE,DISABLE,BIT0|BIT1); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2S_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO4: ++ case PAD_GPIO5: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO6: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO7: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO8: ++ case PAD_GPIO9: ++ case PAD_GPIO10: ++ case PAD_GPIO11: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO14: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE,BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO15: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE,BIT6); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_PWM0: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ ++ case PAD_PWM1: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ break; ++ case PAD_FUART_RX: ++ case PAD_FUART_TX: ++ case PAD_FUART_CTS: ++ case PAD_FUART_RTS: ++ //MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_UART0_RX: ++ case PAD_UART0_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_UART1_RX: ++ case PAD_UART1_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO00: ++ case PAD_SR_IO01: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO02: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO03: ++ case PAD_SR_IO04: ++ case PAD_SR_IO05: ++ case PAD_SR_IO06: ++ case PAD_SR_IO07: ++ case PAD_SR_IO08: ++ case PAD_SR_IO09: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO10: ++ case PAD_SR_IO11: ++ case PAD_SR_IO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SR_IO13: ++ case PAD_SR_IO14: ++ case PAD_SR_IO15: ++ case PAD_SR_IO16: ++ case PAD_SR_IO17: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ break; ++ case PAD_NAND_ALE: ++ break; ++ case PAD_NAND_CLE: ++ case PAD_NAND_CEZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_WPZ: ++ case PAD_NAND_REZ: ++ case PAD_NAND_RBZ: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_SD_MODE,DISABLE,BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_SD_CLK: ++ case PAD_SD_CMD: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SD_D0: ++ case PAD_SD_D1: ++ case PAD_SD_D2: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SD_D3: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SDIO_MODE,DISABLE,BIT0); ++ break; ++ case PAD_I2C0_SCL: ++ case PAD_I2C0_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_I2C1_SCL: ++ case PAD_I2C1_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ break; ++ ++ case PAD_SPI0_CZ: ++ case PAD_SPI0_CK: ++ case PAD_SPI0_DI: ++ case PAD_SPI0_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SPI1_CZ: ++ case PAD_SPI1_CK: ++ case PAD_SPI1_DI: ++ case PAD_SPI1_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_PM_IRIN: ++ MHal_PM_SLEEP_WriteRegBit(REG_IRIN_MODE,ENABLE,BIT4); ++ break; ++ case PAD_SAR_GPIO0: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT0); ++ break; ++ case PAD_SAR_GPIO1: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT1); ++ break; ++ case PAD_SAR_GPIO2: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT2); ++ break; ++ case PAD_SAR_GPIO3: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT3); ++ break; ++ default: ++ break; ++ ++ } ++} ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++/* case PAD_GPIO7: ++ MHal_CHIPTOP_WriteRegBit(1,DISABLE,BIT7); ++ MHal_CHIPTOP_WriteRegBit(2,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break;*/ ++ default: ++ break; ++ } ++} ++ ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ //160 is PMSLEEP virtual irq start ++ if(u8IndexGPIO==PAD_PM_IRIN) ++ return INT_PMSLEEP_IRIN + 160; ++ else if(u8IndexGPIO>=PAD_PM_GPIO0 && u8IndexGPIO<=PAD_PM_GPIO10) ++ return (u8IndexGPIO - PAD_PM_GPIO0 + (INT_PMSLEEP_GPIO_0+160)); ++ else ++ return -1; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u8IndexGPIO) ++ { ++/* case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++*/ ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/mstar/gpio/infinity/mhal_gpio.h b/drivers/mstar/gpio/infinity/mhal_gpio.h +new file mode 100644 +index 00000000..3eaa33e3 +--- /dev/null ++++ b/drivers/mstar/gpio/infinity/mhal_gpio.h +@@ -0,0 +1,61 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk); ++extern U8 MHal_GPIO_ReadRegBit(U32 u32Reg, U8 u8BitMsk); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/infinity/mhal_gpio_reg.h b/drivers/mstar/gpio/infinity/mhal_gpio_reg.h +new file mode 100644 +index 00000000..48343252 +--- /dev/null ++++ b/drivers/mstar/gpio/infinity/mhal_gpio_reg.h +@@ -0,0 +1,65 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++////8 bit define ++//CHIPTOP ++#define REG_FUART_MODE 0x06 ++#define REG_UART0_MODE 0x06 ++#define REG_UART1_MODE 0x07 ++#define REG_SR_MODE 0x0C ++#define REG_SR_I2C_MODE 0x0C ++#define REG_PWM0_MODE 0x0E ++#define REG_PWM1_MODE 0x0E ++#define REG_PWM2_MODE 0x0E ++#define REG_PWM3_MODE 0x0E ++#define REG_NAND_MODE 0x10 ++#define REG_SD_MODE 0x10 ++#define REG_SDIO_MODE 0x11 ++#define REG_I2C0_MODE 0x12 ++#define REG_I2C1_MODE 0x12 ++#define REG_SPI0_MODE 0x18 ++#define REG_SPI1_MODE 0x18 ++#define REG_EJ_MODE 0x1E ++#define REG_ETH_MODE 0x1E ++#define REG_CCIR_MODE 0x1E ++#define REG_TTL_MODE 0x1E ++#define REG_I2S_MODE 0x1F ++#define REG_DMIC_MODE 0x1F ++#define REG_TEST_IN_MODE 0x24 ++#define REG_TEST_OUT_MODE 0x24 ++#define REG_ALL_PAD_IN 0xA1 ++ ++//PMSLEEP ++#define REG_PMLOCK_L_MODE 0x24 ++#define REG_PMLOCK_H_MODE 0x25 ++#define REG_IRIN_MODE 0x38 ++ ++//SAR ++#define REG_SAR_MODE 0x22 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/infinity3/mhal_gpio.c b/drivers/mstar/gpio/infinity3/mhal_gpio.c +new file mode 100644 +index 00000000..360014f0 +--- /dev/null ++++ b/drivers/mstar/gpio/infinity3/mhal_gpio.c +@@ -0,0 +1,1249 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mhal_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "ms_platform.h" ++#include "gpio.h" ++#include "irqs.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#if 1 ++#define _CONCAT( a, b ) a##b ++#define CONCAT( a, b ) _CONCAT( a, b ) ++ ++// Dummy ++#define GPIO999_OEN 0, 0 ++#define GPIO999_OUT 0, 0 ++#define GPIO999_IN 0, 0 ++ ++#define GPIO0_PAD PAD_GPIO0 ++#define GPIO0_OEN 0x103c00, BIT5 ++#define GPIO0_IN 0x103c00, BIT0 ++#define GPIO0_OUT 0x103c00, BIT4 ++ ++#define GPIO1_PAD PAD_GPIO1 ++#define GPIO1_OEN 0x103c02, BIT5 ++#define GPIO1_IN 0x103c02, BIT0 ++#define GPIO1_OUT 0x103c02, BIT4 ++ ++#define GPIO2_PAD PAD_GPIO2 ++#define GPIO2_OEN 0x103c04, BIT5 ++#define GPIO2_IN 0x103c04, BIT0 ++#define GPIO2_OUT 0x103c04, BIT4 ++ ++#define GPIO3_PAD PAD_GPIO3 ++#define GPIO3_OEN 0x103c06, BIT5 ++#define GPIO3_IN 0x103c06, BIT0 ++#define GPIO3_OUT 0x103c06, BIT4 ++ ++#define GPIO4_PAD PAD_GPIO4 ++#define GPIO4_OEN 0x103c08, BIT5 ++#define GPIO4_IN 0x103c08, BIT0 ++#define GPIO4_OUT 0x103c08, BIT4 ++ ++#define GPIO5_PAD PAD_GPIO5 ++#define GPIO5_OEN 0x103c0a, BIT5 ++#define GPIO5_IN 0x103c0a, BIT0 ++#define GPIO5_OUT 0x103c0a, BIT4 ++ ++#define GPIO6_PAD PAD_GPIO6 ++#define GPIO6_OEN 0x103c0c, BIT5 ++#define GPIO6_IN 0x103c0c, BIT0 ++#define GPIO6_OUT 0x103c0c, BIT4 ++ ++#define GPIO7_PAD PAD_GPIO7 ++#define GPIO7_OEN 0x103c0e, BIT5 ++#define GPIO7_IN 0x103c0e, BIT0 ++#define GPIO7_OUT 0x103c0e, BIT4 ++ ++#define GPIO8_PAD PAD_GPIO8 ++#define GPIO8_OEN 0x103c10, BIT5 ++#define GPIO8_IN 0x103c10, BIT0 ++#define GPIO8_OUT 0x103c10, BIT4 ++ ++#define GPIO9_PAD PAD_GPIO9 ++#define GPIO9_OEN 0x103c12, BIT5 ++#define GPIO9_IN 0x103c12, BIT0 ++#define GPIO9_OUT 0x103c12, BIT4 ++ ++#define GPIO10_PAD PAD_GPIO10 ++#define GPIO10_OEN 0x103c14, BIT5 ++#define GPIO10_IN 0x103c14, BIT0 ++#define GPIO10_OUT 0x103c14, BIT4 ++ ++#define GPIO11_PAD PAD_GPIO11 ++#define GPIO11_OEN 0x103c16, BIT5 ++#define GPIO11_IN 0x103c16, BIT0 ++#define GPIO11_OUT 0x103c16, BIT4 ++ ++#define GPIO12_PAD PAD_GPIO12 ++#define GPIO12_OEN 0x103c18, BIT5 ++#define GPIO12_IN 0x103c18, BIT0 ++#define GPIO12_OUT 0x103c18, BIT4 ++ ++#define GPIO13_PAD PAD_GPIO13 ++#define GPIO13_OEN 0x103c1a, BIT5 ++#define GPIO13_IN 0x103c1a, BIT0 ++#define GPIO13_OUT 0x103c1a, BIT4 ++ ++#define GPIO14_PAD PAD_GPIO14 ++#define GPIO14_OEN 0x103c1c, BIT5 ++#define GPIO14_IN 0x103c1c, BIT0 ++#define GPIO14_OUT 0x103c1c, BIT4 ++ ++#define GPIO15_PAD PAD_GPIO15 ++#define GPIO15_OEN 0x103c1e, BIT5 ++#define GPIO15_IN 0x103c1e, BIT0 ++#define GPIO15_OUT 0x103c1e, BIT4 ++ ++#define GPIO16_PAD PAD_FUART_RX ++#define GPIO16_OEN 0x103c28, BIT5 ++#define GPIO16_IN 0x103c28, BIT0 ++#define GPIO16_OUT 0x103c28, BIT4 ++ ++#define GPIO17_PAD PAD_FUART_TX ++#define GPIO17_OEN 0x103c2a, BIT5 ++#define GPIO17_IN 0x103c2a, BIT0 ++#define GPIO17_OUT 0x103c2a, BIT4 ++ ++#define GPIO18_PAD PAD_FUART_CTS ++#define GPIO18_OEN 0x103c2c, BIT5 ++#define GPIO18_IN 0x103c2c, BIT0 ++#define GPIO18_OUT 0x103c2c, BIT4 ++ ++#define GPIO19_PAD PAD_FUART_RTS ++#define GPIO19_OEN 0x103c2e, BIT5 ++#define GPIO19_IN 0x103c2e, BIT0 ++#define GPIO19_OUT 0x103c2e, BIT4 ++ ++#define GPIO20_PAD PAD_I2C0_SCL ++#define GPIO20_OEN 0x103cc0, BIT5 ++#define GPIO20_IN 0x103cc0, BIT0 ++#define GPIO20_OUT 0x103cc0, BIT4 ++ ++#define GPIO21_PAD PAD_I2C0_SDA ++#define GPIO21_OEN 0x103cc2, BIT5 ++#define GPIO21_IN 0x103cc2, BIT0 ++#define GPIO21_OUT 0x103cc2, BIT4 ++ ++#define GPIO22_PAD PAD_I2C1_SCL ++#define GPIO22_OEN 0x103cc4, BIT5 ++#define GPIO22_IN 0x103cc4, BIT0 ++#define GPIO22_OUT 0x103cc4, BIT4 ++ ++#define GPIO23_PAD PAD_I2C1_SDA ++#define GPIO23_OEN 0x103cc6, BIT5 ++#define GPIO23_IN 0x103cc6, BIT0 ++#define GPIO23_OUT 0x103cc6, BIT4 ++ ++#define GPIO24_PAD PAD_SR_IO00 ++#define GPIO24_OEN 0x103c40, BIT5 ++#define GPIO24_IN 0x103c40, BIT0 ++#define GPIO24_OUT 0x103c40, BIT4 ++ ++#define GPIO25_PAD PAD_SR_IO01 ++#define GPIO25_OEN 0x103c42, BIT5 ++#define GPIO25_IN 0x103c42, BIT0 ++#define GPIO25_OUT 0x103c42, BIT4 ++ ++#define GPIO26_PAD PAD_SR_IO02 ++#define GPIO26_OEN 0x103c44, BIT5 ++#define GPIO26_IN 0x103c44, BIT0 ++#define GPIO26_OUT 0x103c44, BIT4 ++ ++#define GPIO27_PAD PAD_SR_IO03 ++#define GPIO27_OEN 0x103c46, BIT5 ++#define GPIO27_IN 0x103c46, BIT0 ++#define GPIO27_OUT 0x103c46, BIT4 ++ ++#define GPIO28_PAD PAD_SR_IO04 ++#define GPIO28_OEN 0x103c48, BIT5 ++#define GPIO28_IN 0x103c48, BIT0 ++#define GPIO28_OUT 0x103c48, BIT4 ++ ++#define GPIO29_PAD PAD_SR_IO05 ++#define GPIO29_OEN 0x103c4a, BIT5 ++#define GPIO29_IN 0x103c4a, BIT0 ++#define GPIO29_OUT 0x103c4a, BIT4 ++ ++#define GPIO30_PAD PAD_SR_IO06 ++#define GPIO30_OEN 0x103c4c, BIT5 ++#define GPIO30_IN 0x103c4c, BIT0 ++#define GPIO30_OUT 0x103c4c, BIT4 ++ ++#define GPIO31_PAD PAD_SR_IO07 ++#define GPIO31_OEN 0x103c4e, BIT5 ++#define GPIO31_IN 0x103c4e, BIT0 ++#define GPIO31_OUT 0x103c4e, BIT4 ++ ++#define GPIO32_PAD PAD_SR_IO08 ++#define GPIO32_OEN 0x103c50, BIT5 ++#define GPIO32_IN 0x103c50, BIT0 ++#define GPIO32_OUT 0x103c50, BIT4 ++ ++#define GPIO33_PAD PAD_SR_IO09 ++#define GPIO33_OEN 0x103c52, BIT5 ++#define GPIO33_IN 0x103c52, BIT0 ++#define GPIO33_OUT 0x103c52, BIT4 ++ ++#define GPIO34_PAD PAD_SR_IO10 ++#define GPIO34_OEN 0x103c54, BIT5 ++#define GPIO34_IN 0x103c54, BIT0 ++#define GPIO34_OUT 0x103c54, BIT4 ++ ++#define GPIO35_PAD PAD_SR_IO11 ++#define GPIO35_OEN 0x103c56, BIT5 ++#define GPIO35_IN 0x103c56, BIT0 ++#define GPIO35_OUT 0x103c56, BIT4 ++ ++#define GPIO36_PAD PAD_SR_IO12 ++#define GPIO36_OEN 0x103c58, BIT5 ++#define GPIO36_IN 0x103c58, BIT0 ++#define GPIO36_OUT 0x103c58, BIT4 ++ ++#define GPIO37_PAD PAD_SR_IO13 ++#define GPIO37_OEN 0x103c5a, BIT5 ++#define GPIO37_IN 0x103c5a, BIT0 ++#define GPIO37_OUT 0x103c5a, BIT4 ++ ++#define GPIO38_PAD PAD_SR_IO14 ++#define GPIO38_OEN 0x103c5c, BIT5 ++#define GPIO38_IN 0x103c5c, BIT0 ++#define GPIO38_OUT 0x103c5c, BIT4 ++ ++#define GPIO39_PAD PAD_SR_IO15 ++#define GPIO39_OEN 0x103c5e, BIT5 ++#define GPIO39_IN 0x103c5e, BIT0 ++#define GPIO39_OUT 0x103c5e, BIT4 ++ ++#define GPIO40_PAD PAD_SR_IO16 ++#define GPIO40_OEN 0x103c60, BIT5 ++#define GPIO40_IN 0x103c60, BIT0 ++#define GPIO40_OUT 0x103c60, BIT4 ++ ++#define GPIO41_PAD PAD_SR_IO17 ++#define GPIO41_OEN 0x103c62, BIT5 ++#define GPIO41_IN 0x103c62, BIT0 ++#define GPIO41_OUT 0x103c62, BIT4 ++ ++#define GPIO42_PAD PAD_NAND_ALE ++#define GPIO42_OEN 0x103c82, BIT5 ++#define GPIO42_IN 0x103c82, BIT0 ++#define GPIO42_OUT 0x103c82, BIT4 ++ ++#define GPIO43_PAD PAD_NAND_CLE ++#define GPIO43_OEN 0x103c84, BIT5 ++#define GPIO43_IN 0x103c84, BIT0 ++#define GPIO43_OUT 0x103c84, BIT4 ++ ++#define GPIO44_PAD PAD_NAND_CEZ ++#define GPIO44_OEN 0x103c80, BIT5 ++#define GPIO44_IN 0x103c80, BIT0 ++#define GPIO44_OUT 0x103c80, BIT4 ++ ++#define GPIO45_PAD PAD_NAND_WEZ ++#define GPIO45_OEN 0x103c86, BIT5 ++#define GPIO45_IN 0x103c86, BIT0 ++#define GPIO45_OUT 0x103c86, BIT4 ++ ++#define GPIO46_PAD PAD_NAND_WPZ ++#define GPIO46_OEN 0x103c88, BIT5 ++#define GPIO46_IN 0x103c88, BIT0 ++#define GPIO46_OUT 0x103c88, BIT4 ++ ++#define GPIO47_PAD PAD_NAND_REZ ++#define GPIO47_OEN 0x103c8a, BIT5 ++#define GPIO47_IN 0x103c8a, BIT0 ++#define GPIO47_OUT 0x103c8a, BIT4 ++ ++#define GPIO48_PAD PAD_NAND_RBZ ++#define GPIO48_OEN 0x103c8c, BIT5 ++#define GPIO48_IN 0x103c8c, BIT0 ++#define GPIO48_OUT 0x103c8c, BIT4 ++ ++#define GPIO49_PAD PAD_NAND_DA0 ++#define GPIO49_OEN 0x103c8e, BIT5 ++#define GPIO49_IN 0x103c8e, BIT0 ++#define GPIO49_OUT 0x103c8e, BIT4 ++ ++#define GPIO50_PAD PAD_NAND_DA1 ++#define GPIO50_OEN 0x103c90, BIT5 ++#define GPIO50_IN 0x103c90, BIT0 ++#define GPIO50_OUT 0x103c90, BIT4 ++ ++#define GPIO51_PAD PAD_NAND_DA2 ++#define GPIO51_OEN 0x103c92, BIT5 ++#define GPIO51_IN 0x103c92, BIT0 ++#define GPIO51_OUT 0x103c92, BIT4 ++ ++#define GPIO52_PAD PAD_NAND_DA3 ++#define GPIO52_OEN 0x103c94, BIT5 ++#define GPIO52_IN 0x103c94, BIT0 ++#define GPIO52_OUT 0x103c94, BIT4 ++ ++#define GPIO53_PAD PAD_NAND_DA4 ++#define GPIO53_OEN 0x103c96, BIT5 ++#define GPIO53_IN 0x103c96, BIT0 ++#define GPIO53_OUT 0x103c96, BIT4 ++ ++#define GPIO54_PAD PAD_NAND_DA5 ++#define GPIO54_OEN 0x103c98, BIT5 ++#define GPIO54_IN 0x103c98, BIT0 ++#define GPIO54_OUT 0x103c98, BIT4 ++ ++#define GPIO55_PAD PAD_NAND_DA6 ++#define GPIO55_OEN 0x103c9a, BIT5 ++#define GPIO55_IN 0x103c9a, BIT0 ++#define GPIO55_OUT 0x103c9a, BIT4 ++ ++#define GPIO56_PAD PAD_NAND_DA7 ++#define GPIO56_OEN 0x103c9c, BIT5 ++#define GPIO56_IN 0x103c9c, BIT0 ++#define GPIO56_OUT 0x103c9c, BIT4 ++ ++#define GPIO57_PAD PAD_UART0_RX ++#define GPIO57_OEN 0x103c30, BIT5 ++#define GPIO57_IN 0x103c30, BIT0 ++#define GPIO57_OUT 0x103c30, BIT4 ++ ++#define GPIO58_PAD PAD_UART0_TX ++#define GPIO58_OEN 0x103c32, BIT5 ++#define GPIO58_IN 0x103c32, BIT0 ++#define GPIO58_OUT 0x103c32, BIT4 ++ ++#define GPIO59_PAD PAD_UART1_RX ++#define GPIO59_OEN 0x103c34, BIT5 ++#define GPIO59_IN 0x103c34, BIT0 ++#define GPIO59_OUT 0x103c34, BIT4 ++ ++#define GPIO60_PAD PAD_UART1_TX ++#define GPIO60_OEN 0x103c36, BIT5 ++#define GPIO60_IN 0x103c36, BIT0 ++#define GPIO60_OUT 0x103c36, BIT4 ++ ++#define GPIO61_PAD PAD_SPI0_CZ ++#define GPIO61_OEN 0x103ce0, BIT5 ++#define GPIO61_IN 0x103ce0, BIT0 ++#define GPIO61_OUT 0x103ce0, BIT4 ++ ++#define GPIO62_PAD PAD_SPI0_CK ++#define GPIO62_OEN 0x103ce2, BIT5 ++#define GPIO62_IN 0x103ce2, BIT0 ++#define GPIO62_OUT 0x103ce2, BIT4 ++ ++#define GPIO63_PAD PAD_SPI0_DI ++#define GPIO63_OEN 0x103ce4, BIT5 ++#define GPIO63_IN 0x103ce4, BIT0 ++#define GPIO63_OUT 0x103ce4, BIT4 ++ ++#define GPIO64_PAD PAD_SPI0_DO ++#define GPIO64_OEN 0x103ce6, BIT5 ++#define GPIO64_IN 0x103ce6, BIT0 ++#define GPIO64_OUT 0x103ce6, BIT4 ++ ++#define GPIO65_PAD PAD_SPI1_CZ ++#define GPIO65_OEN 0x103ce8, BIT5 ++#define GPIO65_IN 0x103ce8, BIT0 ++#define GPIO65_OUT 0x103ce8, BIT4 ++ ++#define GPIO66_PAD PAD_SPI1_CK ++#define GPIO66_OEN 0x103cea, BIT5 ++#define GPIO66_IN 0x103cea, BIT0 ++#define GPIO66_OUT 0x103cea, BIT4 ++ ++#define GPIO67_PAD PAD_SPI1_DI ++#define GPIO67_OEN 0x103cec, BIT5 ++#define GPIO67_IN 0x103cec, BIT0 ++#define GPIO67_OUT 0x103cec, BIT4 ++ ++#define GPIO68_PAD PAD_SPI1_DO ++#define GPIO68_OEN 0x103cee, BIT5 ++#define GPIO68_IN 0x103cee, BIT0 ++#define GPIO68_OUT 0x103cee, BIT4 ++ ++#define GPIO69_PAD PAD_PWM0 ++#define GPIO69_OEN 0x103c20, BIT5 ++#define GPIO69_IN 0x103c20, BIT0 ++#define GPIO69_OUT 0x103c20, BIT4 ++ ++#define GPIO70_PAD PAD_PWM1 ++#define GPIO70_OEN 0x103c22, BIT5 ++#define GPIO70_IN 0x103c22, BIT0 ++#define GPIO70_OUT 0x103c22, BIT4 ++ ++#define GPIO71_PAD PAD_SD_CLK ++#define GPIO71_OEN 0x103ca0, BIT5 ++#define GPIO71_IN 0x103ca0, BIT0 ++#define GPIO71_OUT 0x103ca0, BIT4 ++ ++#define GPIO72_PAD PAD_SD_CMD ++#define GPIO72_OEN 0x103ca2, BIT5 ++#define GPIO72_IN 0x103ca2, BIT0 ++#define GPIO72_OUT 0x103ca2, BIT4 ++ ++#define GPIO73_PAD PAD_SD_D0 ++#define GPIO73_OEN 0x103ca4, BIT5 ++#define GPIO73_IN 0x103ca4, BIT0 ++#define GPIO73_OUT 0x103ca4, BIT4 ++ ++#define GPIO74_PAD PAD_SD_D1 ++#define GPIO74_OEN 0x103ca6, BIT5 ++#define GPIO74_IN 0x103ca6, BIT0 ++#define GPIO74_OUT 0x103ca6, BIT4 ++ ++#define GPIO75_PAD PAD_SD_D2 ++#define GPIO75_OEN 0x103ca8, BIT5 ++#define GPIO75_IN 0x103ca8, BIT0 ++#define GPIO75_OUT 0x103ca8, BIT4 ++ ++#define GPIO76_PAD PAD_SD_D3 ++#define GPIO76_OEN 0x103caa, BIT5 ++#define GPIO76_IN 0x103caa, BIT0 ++#define GPIO76_OUT 0x103caa, BIT4 ++//pm gpio ++#define GPIO77_PAD PAD_PM_SD_CDZ ++#define GPIO77_OEN 0x0f8e, BIT0 ++#define GPIO77_IN 0x0f8e, BIT2 ++#define GPIO77_OUT 0x0f8e, BIT1 ++ ++#define GPIO78_PAD PAD_PM_IRIN ++#define GPIO78_OEN 0x0f28, BIT0 ++#define GPIO78_IN 0x0f28, BIT2 ++#define GPIO78_OUT 0x0f28, BIT1 ++ ++#define GPIO79_PAD PAD_PM_GPIO0 ++#define GPIO79_OEN 0x0f00, BIT0 ++#define GPIO79_IN 0x0f00, BIT2 ++#define GPIO79_OUT 0x0f00, BIT1 ++ ++#define GPIO80_PAD PAD_PM_GPIO1 ++#define GPIO80_OEN 0x0f02, BIT0 ++#define GPIO80_IN 0x0f02, BIT2 ++#define GPIO80_OUT 0x0f02, BIT1 ++ ++#define GPIO81_PAD PAD_PM_GPIO2 ++#define GPIO81_OEN 0x0f04, BIT0 ++#define GPIO81_IN 0x0f04, BIT2 ++#define GPIO81_OUT 0x0f04, BIT1 ++ ++#define GPIO82_PAD PAD_PM_GPIO3 ++#define GPIO82_OEN 0x0f06, BIT0 ++#define GPIO82_IN 0x0f06, BIT2 ++#define GPIO82_OUT 0x0f06, BIT1 ++ ++#define GPIO83_PAD PAD_PM_GPIO4 ++#define GPIO83_OEN 0x0f08, BIT0 ++#define GPIO83_IN 0x0f08, BIT2 ++#define GPIO83_OUT 0x0f08, BIT1 ++ ++#define GPIO84_PAD PAD_PM_GPIO5 ++#define GPIO84_OEN 0x0f0a, BIT0 ++#define GPIO84_IN 0x0f0a, BIT2 ++#define GPIO84_OUT 0x0f0a, BIT1 ++ ++#define GPIO85_PAD PAD_PM_GPIO6 ++#define GPIO85_OEN 0x0f0c, BIT0 ++#define GPIO85_IN 0x0f0c, BIT2 ++#define GPIO85_OUT 0x0f0c, BIT1 ++ ++#define GPIO86_PAD PAD_PM_GPIO7 ++#define GPIO86_OEN 0x0f0e, BIT0 ++#define GPIO86_IN 0x0f0e, BIT2 ++#define GPIO86_OUT 0x0f0e, BIT1 ++ ++#define GPIO87_PAD PAD_PM_GPIO8 ++#define GPIO87_OEN 0x0f10, BIT0 ++#define GPIO87_IN 0x0f10, BIT2 ++#define GPIO87_OUT 0x0f10, BIT1 ++ ++#define GPIO88_PAD PAD_PM_GPIO9 ++#define GPIO88_OEN 0x0f12, BIT0 ++#define GPIO88_IN 0x0f12, BIT2 ++#define GPIO88_OUT 0x0f12, BIT1 ++ ++#define GPIO89_PAD PAD_PM_GPIO10 ++#define GPIO89_OEN 0x0f14, BIT0 ++#define GPIO89_IN 0x0f14, BIT2 ++#define GPIO89_OUT 0x0f14, BIT1 ++ ++#define GPIO90_PAD PAD_PM_SPI_CZ ++#define GPIO90_OEN 0x0f30, BIT0 ++#define GPIO90_IN 0x0f30, BIT2 ++#define GPIO90_OUT 0x0f30, BIT1 ++ ++#define GPIO91_PAD PAD_PM_SPI_CK ++#define GPIO91_OEN 0x0f32, BIT0 ++#define GPIO91_IN 0x0f32, BIT2 ++#define GPIO91_OUT 0x0f32, BIT1 ++ ++#define GPIO92_PAD PAD_PM_SPI_DI ++#define GPIO92_OEN 0x0f34, BIT0 ++#define GPIO92_IN 0x0f34, BIT2 ++#define GPIO92_OUT 0x0f34, BIT1 ++ ++#define GPIO93_PAD PAD_PM_SPI_DO ++#define GPIO93_OEN 0x0f36, BIT0 ++#define GPIO93_IN 0x0f36, BIT2 ++#define GPIO93_OUT 0x0f36, BIT1 ++ ++#define GPIO94_PAD PAD_PM_SPI_WPZ ++#define GPIO94_OEN 0x0f88, BIT0 ++#define GPIO94_IN 0x0f88, BIT2 ++#define GPIO94_OUT 0x0f88, BIT1 ++ ++#define GPIO95_PAD PAD_PM_SPI_HLD ++#define GPIO95_OEN 0x0f8a, BIT0 ++#define GPIO95_IN 0x0f8a, BIT2 ++#define GPIO95_OUT 0x0f8a, BIT1 ++ ++#define GPIO96_PAD PAD_PM_LED0 ++#define GPIO96_OEN 0x0f94, BIT0 ++#define GPIO96_IN 0x0f94, BIT2 ++#define GPIO96_OUT 0x0f94, BIT1 ++ ++#define GPIO97_PAD PAD_PM_LED1 ++#define GPIO97_OEN 0x0f96, BIT0 ++#define GPIO97_IN 0x0f96, BIT2 ++#define GPIO97_OUT 0x0f96, BIT1 ++//SAR GPIO ++#define GPIO98_PAD PAD_SAR_GPIO0 ++#define GPIO98_OEN 0x1423, BIT0 ++#define GPIO98_IN 0x1425, BIT0 ++#define GPIO98_OUT 0x1424, BIT0 ++ ++#define GPIO99_PAD PAD_SAR_GPIO1 ++#define GPIO99_OEN 0x1423, BIT1 ++#define GPIO99_IN 0x1425, BIT1 ++#define GPIO99_OUT 0x1424, BIT1 ++ ++#define GPIO100_PAD PAD_SAR_GPIO2 ++#define GPIO100_OEN 0x1423, BIT2 ++#define GPIO100_IN 0x1425, BIT2 ++#define GPIO100_OUT 0x1424, BIT2 ++ ++#define GPIO101_PAD PAD_SAR_GPIO3 ++#define GPIO101_OEN 0x1423, BIT3 ++#define GPIO101_IN 0x1425, BIT3 ++#define GPIO101_OUT 0x1424, BIT3 ++//ETH GPIO ++#define GPIO102_PAD PAD_ETH_RN ++#define GPIO102_OEN 0x33e2, BIT4 ++#define GPIO102_IN 0x33e4, BIT4 ++#define GPIO102_OUT 0x33e4, BIT0 ++ ++#define GPIO103_PAD PAD_ETH_RP ++#define GPIO103_OEN 0x33e2, BIT5 ++#define GPIO103_IN 0x33e4, BIT5 ++#define GPIO103_OUT 0x33e4, BIT1 ++ ++#define GPIO104_PAD PAD_ETH_TN ++#define GPIO104_OEN 0x33e2, BIT6 ++#define GPIO104_IN 0x33e4, BIT6 ++#define GPIO104_OUT 0x33e4, BIT2 ++ ++#define GPIO105_PAD PAD_ETH_TP ++#define GPIO105_OEN 0x33e2, BIT7 ++#define GPIO105_IN 0x33e4, BIT7 ++#define GPIO105_OUT 0x33e4, BIT3 ++ ++ ++//USB GPIO ++#define GPIO106_PAD PAD_USB_DM ++#define GPIO106_OEN 0x14210a, BIT4 ++#define GPIO106_IN 0x142131, BIT5 ++#define GPIO106_OUT 0x14210a, BIT2 ++ ++#define GPIO107_PAD PAD_USB_DP ++#define GPIO107_OEN 0x14210a, BIT5 ++#define GPIO107_IN 0x142131, BIT4 ++#define GPIO107_OUT 0x14210a, BIT3 ++ ++#define GPIO108_PAD PAD_DM_P1 ++#define GPIO108_OEN 0x14290a, BIT4 ++#define GPIO108_IN 0x142931, BIT5 ++#define GPIO108_OUT 0x14290a, BIT2 ++ ++#define GPIO109_PAD PAD_DP_P1 ++#define GPIO109_OEN 0x14290a, BIT5 ++#define GPIO109_IN 0x142931, BIT4 ++#define GPIO109_OUT 0x142924, BIT3 ++ ++U32 gChipBaseAddr=0xFD203C00; ++U32 gPmSleepBaseAddr=0xFD001C00; ++U32 gSarBaseAddr=0xFD002800; ++U32 gRIUBaseAddr=0xFD000000; ++ ++#define MHal_CHIPTOP_REG(addr) (*(volatile U8*)(gChipBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_PM_SLEEP_REG(addr) (*(volatile U8*)(gPmSleepBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_SAR_GPIO_REG(addr) (*(volatile U8*)(gSarBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++#define MHal_RIU_REG(addr) (*(volatile U8*)(gRIUBaseAddr + (((addr) & ~1)<<1) + (addr & 1))) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++static const struct gpio_setting ++{ ++ U32 r_oen; ++ U8 m_oen; ++ U32 r_out; ++ U8 m_out; ++ U32 r_in; ++ U8 m_in; ++} gpio_table[] = ++{ ++#define __GPIO__(_x_) { CONCAT(CONCAT(GPIO, _x_), _OEN), \ ++ CONCAT(CONCAT(GPIO, _x_), _OUT), \ ++ CONCAT(CONCAT(GPIO, _x_), _IN) } ++#define __GPIO(_x_) __GPIO__(_x_) ++ ++// ++// !! WARNING !! DO NOT MODIFIY !!!! ++// ++// These defines order must match following ++// 1. the PAD name in GPIO excel ++// 2. the perl script to generate the package header file ++// ++ //__GPIO(999), // 0 is not used ++ ++ __GPIO(0), __GPIO(1), __GPIO(2), __GPIO(3), __GPIO(4), ++ __GPIO(5), __GPIO(6), __GPIO(7), __GPIO(8), __GPIO(9), ++ __GPIO(10), __GPIO(11), __GPIO(12), __GPIO(13), __GPIO(14), ++ __GPIO(15), __GPIO(16), __GPIO(17), __GPIO(18), __GPIO(19), ++ __GPIO(20), __GPIO(21), __GPIO(22), __GPIO(23), __GPIO(24), ++ __GPIO(25), __GPIO(26), __GPIO(27), __GPIO(28), __GPIO(29), ++ __GPIO(30), __GPIO(31), __GPIO(32), __GPIO(33), __GPIO(34), ++ __GPIO(35), __GPIO(36), __GPIO(37), __GPIO(38), __GPIO(39), ++ __GPIO(40), __GPIO(41), __GPIO(42), __GPIO(43), __GPIO(44), ++ __GPIO(45), __GPIO(46), __GPIO(47), __GPIO(48), __GPIO(49), ++ __GPIO(50), __GPIO(51), __GPIO(52), __GPIO(53), __GPIO(54), ++ __GPIO(55), __GPIO(56), __GPIO(57), __GPIO(58), __GPIO(59), ++ __GPIO(60), __GPIO(61), __GPIO(62), __GPIO(63), __GPIO(64), ++ __GPIO(65), __GPIO(66), __GPIO(67), __GPIO(68), __GPIO(69), ++ __GPIO(70), __GPIO(71), __GPIO(72), __GPIO(73), __GPIO(74), ++ __GPIO(75), __GPIO(76), __GPIO(77), __GPIO(78), __GPIO(79), ++ __GPIO(80), __GPIO(81), __GPIO(82), __GPIO(83), __GPIO(84), ++ __GPIO(85), __GPIO(86), __GPIO(87), __GPIO(88), __GPIO(89), ++ __GPIO(90), __GPIO(91), __GPIO(92), __GPIO(93), __GPIO(94), ++ __GPIO(95), __GPIO(96), __GPIO(97), __GPIO(98), __GPIO(99), ++ __GPIO(100), __GPIO(101), __GPIO(102), __GPIO(103), __GPIO(104), ++ __GPIO(105), __GPIO(106), __GPIO(107), __GPIO(108), __GPIO(109), ++ ++}; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//the functions of this section set to initialize ++void MHal_GPIO_Init(void) ++{ ++// printk("MHal_GPIO_Init gBaseAddr=%x\n",gPadBaseAddr); ++ MHal_CHIPTOP_REG(REG_ALL_PAD_IN) &= ~BIT7; ++} ++ ++void MHal_CHIPTOP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_CHIPTOP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_CHIPTOP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_CHIPTOP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_CHIPTOP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_CHIPTOP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_CHIPTOP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_PM_SLEEP_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_PM_SLEEP_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_PM_SLEEP_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegBit(U32 u32Reg, U8 u8BitMsk) ++{ ++ return ((MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk)? 1 : 0); ++} ++ ++U8 MHal_PM_SLEEP_ReadRegMsk(U32 u32Reg, U8 u8BitMsk) ++{ ++ return (MHal_PM_SLEEP_REG(u32Reg)&u8BitMsk); ++} ++ ++void MHal_SAR_GPIO_WriteRegBit(U32 u32Reg, U8 u8Enable, U8 u8BitMsk) ++{ ++ if(u8Enable) ++ MHal_SAR_GPIO_REG(u32Reg) |= u8BitMsk; ++ else ++ MHal_SAR_GPIO_REG(u32Reg) &= (~u8BitMsk); ++} ++ ++void MHal_FuartPAD_DisableFunction(void) ++{ ++ //reg_fuart_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_FUART_MODE, BIT0|BIT1) == BIT0 ){ ++ printk("[gpio] Disable FUART function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE, DISABLE, BIT0|BIT1); ++ } ++ //reg_spi0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_SPI0_MODE, BIT0|BIT1) == (BIT0|BIT1) ){ ++ printk("[gpio] Disable SPI0 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE, DISABLE, BIT0|BIT1); ++ } ++ //reg_EJ_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_EJ_MODE, BIT0|BIT1) == BIT0 ){ ++ printk("[gpio] Disable EJ_MODE function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE, BIT1|BIT0); ++ } ++} ++ ++void MHal_SPI0PAD_DisableFunction(void) ++{ ++ //REG_TEST_IN_MODE ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ ++ //spi0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_SPI0_MODE, BIT1|BIT0) == BIT0 ){ ++ printk("[gpio] Disable SPI0 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE, DISABLE, BIT0|BIT1); ++ } ++ ++ //reg_EJ_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_EJ_MODE,BIT1|BIT0) == BIT1 ){ ++ printk("[gpio] Disable EJ_MODE function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_EJ_MODE,DISABLE,BIT1|BIT0); ++ } ++} ++ ++void MHal_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ //printk("[gpio]MHal_GPIO_Pad_Set %d\n", u8IndexGPIO); ++ switch(u8IndexGPIO) ++ { ++ case PAD_GPIO0: ++ case PAD_GPIO1: ++ case PAD_GPIO2: ++ case PAD_GPIO3: ++ //MHal_CHIPTOP_WriteRegBit(REG_FUART_MODE,DISABLE,BIT0|BIT1); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2S_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO4: ++ case PAD_GPIO5: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO6: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_DMIC_MODE,DISABLE,BIT0); ++ break; ++ case PAD_GPIO7: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO8: ++ case PAD_GPIO9: ++ case PAD_GPIO10: ++ case PAD_GPIO11: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO14: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE,BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_GPIO15: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE,BIT6); ++ //MHal_CHIPTOP_WriteRegBit(REG_ETH_MODE,DISABLE,BIT2); ++ break; ++ case PAD_PWM0: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ ++ case PAD_PWM1: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE,BIT3|BIT2); ++ break; ++ ++ case PAD_FUART_RX: ++ //PWM0 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM0_MODE, BIT1|BIT0) == (BIT1|BIT0) ){ ++ printk("[gpio] Disable PWM0 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM0_MODE,DISABLE, BIT1|BIT0); ++ } ++ //reg_uart0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART0_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART0 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE, DISABLE, BIT0|BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_FUART_TX: ++ //PWM1 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM1_MODE, BIT3|BIT2) == (BIT3|BIT2) ){ ++ printk("[gpio] Disable PWM1 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM1_MODE,DISABLE, BIT3|BIT2); ++ } ++ ++ //reg_uart0_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART0_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART0 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE, DISABLE, BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_FUART_CTS: ++ //PWM2 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM2_MODE, BIT5|BIT4) == (BIT4) ){ ++ printk("[gpio] Disable PWM2 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM2_MODE,DISABLE, BIT4); ++ } ++ ++ //reg_uart1_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART1_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART1 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE, DISABLE, BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_FUART_RTS: ++ //PWM3 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM3_MODE, BIT7|BIT6) == (BIT7|BIT6) ){ ++ printk("[gpio] Disable PWM3 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM3_MODE,DISABLE, BIT7|BIT6); ++ } ++ ++ //reg_uart1_mode ++ if( MHal_CHIPTOP_ReadRegMsk(REG_UART1_MODE, BIT0|BIT1) == BIT1 ){ ++ printk("[gpio] Disable UART1 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE, DISABLE, BIT1); ++ } ++ MHal_FuartPAD_DisableFunction(); ++ break; ++ ++ case PAD_UART0_RX: ++ case PAD_UART0_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART0_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_UART1_RX: ++ case PAD_UART1_TX: ++ //MHal_CHIPTOP_WriteRegBit(REG_UART1_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO00: ++ case PAD_SR_IO01: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C0_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SR_IO02: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO03: ++ case PAD_SR_IO04: ++ case PAD_SR_IO05: ++ case PAD_SR_IO06: ++ case PAD_SR_IO07: ++ case PAD_SR_IO08: ++ case PAD_SR_IO09: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_CCIR_MODE,DISABLE,BIT4); ++ break; ++ case PAD_SR_IO10: ++ case PAD_SR_IO11: ++ case PAD_SR_IO12: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SR_IO13: ++ case PAD_SR_IO14: ++ case PAD_SR_IO15: ++ case PAD_SR_IO16: ++ case PAD_SR_IO17: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SR_MODE,DISABLE,BIT2|BIT1|BIT0); ++ break; ++ case PAD_NAND_ALE: ++ break; ++ case PAD_NAND_CLE: ++ case PAD_NAND_CEZ: ++ case PAD_NAND_WEZ: ++ case PAD_NAND_WPZ: ++ case PAD_NAND_REZ: ++ case PAD_NAND_RBZ: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_SD_MODE,DISABLE,BIT2); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_NAND_DA0: ++ case PAD_NAND_DA1: ++ case PAD_NAND_DA2: ++ case PAD_NAND_DA3: ++ case PAD_NAND_DA4: ++ case PAD_NAND_DA5: ++ case PAD_NAND_DA6: ++ case PAD_NAND_DA7: ++ //MHal_CHIPTOP_WriteRegBit(REG_NAND_MODE,DISABLE,BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_SD_CLK: ++ case PAD_SD_CMD: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_SD_D0: ++ case PAD_SD_D1: ++ case PAD_SD_D2: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ break; ++ case PAD_SD_D3: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_OUT_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_SDIO_MODE,DISABLE,BIT0); ++ break; ++ case PAD_I2C0_SCL: ++ case PAD_I2C0_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_TEST_IN_MODE,DISABLE,BIT1|BIT0); ++ break; ++ case PAD_I2C1_SCL: ++ case PAD_I2C1_SDA: ++ //MHal_CHIPTOP_WriteRegBit(REG_I2C1_MODE,DISABLE,BIT5|BIT4); ++ break; ++ ++ case PAD_SPI0_CZ: ++ //PWM4 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT1|BIT0) == BIT1 ){ ++ printk("[gpio] Disable PWM4 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT1); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI0_CK: ++ //PWM5 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT3|BIT2) == BIT3 ){ ++ printk("[gpio] Disable PWM5 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT3); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI0_DI: ++ //PWM6 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT5|BIT4) == BIT5 ){ ++ printk("[gpio] Disable PWM6 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT5); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI0_DO: ++ //PWM7 ++ if( MHal_CHIPTOP_ReadRegMsk(REG_PWM4_MODE, BIT7|BIT6) == BIT7 ){ ++ printk("[gpio] Disable PWM7 function\n"); ++ MHal_CHIPTOP_WriteRegBit(REG_PWM4_MODE,DISABLE, BIT7); ++ } ++ MHal_SPI0PAD_DisableFunction(); ++ break; ++ ++ case PAD_SPI1_CZ: ++ case PAD_SPI1_CK: ++ case PAD_SPI1_DI: ++ case PAD_SPI1_DO: ++ //MHal_CHIPTOP_WriteRegBit(REG_SPI1_MODE,DISABLE,BIT5|BIT4); ++ //MHal_CHIPTOP_WriteRegBit(REG_TTL_MODE,DISABLE,BIT6); ++ break; ++ case PAD_PM_IRIN: ++ MHal_PM_SLEEP_WriteRegBit(REG_IRIN_MODE,ENABLE,BIT4); ++ break; ++ case PAD_PM_GPIO4: ++ MHal_PM_SLEEP_WriteRegBit(REG_PMLOCK_L_MODE,ENABLE,0xBE); ++ MHal_PM_SLEEP_WriteRegBit(REG_PMLOCK_H_MODE,ENABLE,0xBA); ++ break; ++ case PAD_PM_LED0: ++ case PAD_PM_LED1: ++ if( MHal_PM_SLEEP_ReadRegMsk(0x50,BIT4|BIT5) == BIT4 ){ ++ printk("[gpio] Disable ethernet ACK/LINK led\n"); ++ MHal_PM_SLEEP_WriteRegBit(0x50,DISABLE,BIT4); ++ } ++ break; ++ case PAD_SAR_GPIO0: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT0); ++ break; ++ case PAD_SAR_GPIO1: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT1); ++ break; ++ case PAD_SAR_GPIO2: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT2); ++ break; ++ case PAD_SAR_GPIO3: ++ MHal_SAR_GPIO_WriteRegBit(REG_SAR_MODE,DISABLE,BIT3); ++ break; ++ default: ++ break; ++ ++ } ++} ++void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++} ++ ++void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) |= gpio_table[u8IndexGPIO].m_oen; ++} ++ ++U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_in)&gpio_table[u8IndexGPIO].m_in)? 1 : 0); ++} ++ ++U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return ((MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen)&gpio_table[u8IndexGPIO].m_oen)? 1 : 0); ++} ++ ++void MHal_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) |= gpio_table[u8IndexGPIO].m_out; ++} ++ ++void MHal_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_oen) &= (~gpio_table[u8IndexGPIO].m_oen); ++ MHal_RIU_REG(gpio_table[u8IndexGPIO].r_out) &= (~gpio_table[u8IndexGPIO].m_out); ++} ++ ++void MHal_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ switch(u8IndexGPIO) ++ { ++/* case PAD_GPIO7: ++ MHal_CHIPTOP_WriteRegBit(1,DISABLE,BIT7); ++ MHal_CHIPTOP_WriteRegBit(2,ENABLE,BIT0); ++ break; ++ case PAD_GPIO8: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT1); ++ break; ++ case PAD_GPIO9: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT2); ++ break; ++ case PAD_GPIO13: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT3); ++ break; ++ case PAD_GPIO28: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT4); ++ break; ++ case PAD_GPIO29: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_21,DISABLE,BIT2); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT5); ++ break; ++ case PAD_GPIO30: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT6); ++ break; ++ case PAD_GPIO31: ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT5); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_02,DISABLE,BIT3); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_20,DISABLE,BIT4); ++ MHal_CHIPTOP_WriteRegBit(REG_GPIO1_25,ENABLE,BIT7); ++ break;*/ ++ default: ++ break; ++ } ++} ++ ++int MHal_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ //160 is PMSLEEP virtual irq start ++ if(u8IndexGPIO==PAD_PM_IRIN) ++ return INT_PMSLEEP_IRIN + 160; ++ else if(u8IndexGPIO>=PAD_PM_GPIO0 && u8IndexGPIO<=PAD_PM_GPIO10) ++ return (u8IndexGPIO - PAD_PM_GPIO0 + (INT_PMSLEEP_GPIO_0+160)); ++ ++ else if(u8IndexGPIO>=PAD_SAR_GPIO0 && u8IndexGPIO<=PAD_SAR_GPIO3) ++ return (u8IndexGPIO - PAD_SAR_GPIO0 + (INT_FIQ_SAR_GPIO_0)+GIC_SGI_NR+GIC_PPI_NR); ++ else ++ return -1; ++} ++ ++void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++/* ++IdxGPIO GPIOx IdxFIQ ++70 --GPIO31 -- 63 -- ext_gpio_int[7] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++71 --GPIO30 -- 58 -- ext_gpio_int[6] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++72 --GPIO29 -- 57 -- ext_gpio_int[5] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++73 -- GPIO28 -- 56 -- ext_gpio_int[4] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++113 --GPIO13 -- 55 -- ext_gpio_int[3] -- reg_hst0_fiq_polarity_63_48_ -- [h00b,h00b] ++117 --GPIO9 -- 47 -- ext_gpio_int[2] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++118 --GPIO8 -- 43 -- ext_gpio_int[1] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++119 --GPIO7 -- 39 -- ext_gpio_int[0] -- reg_hst0_fiq_polarity_47_32_ -- [h00a,h00a] ++*/ ++ ++ switch(u8IndexGPIO) ++ { ++/* case 119: //INT_FIQ_EXT_GPIO0 ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 118: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 11); //Set To Raising edge trigger ++ break; ++ case 117: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0a), 1 << 15); //Set To Raising edge trigger ++ break; ++ case 113: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 7); //Set To Raising edge trigger ++ break; ++ case 73: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 8); //Set To Raising edge trigger ++ break; ++ case 72: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 9); //Set To Raising edge trigger ++ break; ++ case 71: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 10); //Set To Raising edge trigger ++ break; ++ case 70: ++ if(reverse==0) ++ SETREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Falling edge trigger ++ else ++ CLRREG16(GET_REG_ADDR(MS_INT_BASE, 0x0b), 1 << 15); //Set To Raising edge trigger ++ break; ++*/ ++ default: ++ break; ++ } ++} ++ ++ ++ +diff --git a/drivers/mstar/gpio/infinity3/mhal_gpio.h b/drivers/mstar/gpio/infinity3/mhal_gpio.h +new file mode 100644 +index 00000000..e08b843b +--- /dev/null ++++ b/drivers/mstar/gpio/infinity3/mhal_gpio.h +@@ -0,0 +1,59 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_GPIO_H_ ++#define _HAL_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++//#define BIT(_bit_) (1 << (_bit_)) ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//the functions of this section set to initialize ++extern void MHal_GPIO_Init(void); ++extern void MHal_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Oen(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pad_Odn(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_Level(U8 u8IndexGPIO); ++extern U8 MHal_GPIO_Pad_InOut(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Pull_Low(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_High(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MHal_Enable_GPIO_INT(U8 u8IndexGPIO); ++extern int MHal_GPIO_To_Irq(U8 u8IndexGPIO); ++extern void MHal_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++extern void MHal_GPIO_PAD_32K_OUT(U8 u8Enable); ++ ++#endif // _HAL_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/infinity3/mhal_gpio_reg.h b/drivers/mstar/gpio/infinity3/mhal_gpio_reg.h +new file mode 100644 +index 00000000..af6e1a3b +--- /dev/null ++++ b/drivers/mstar/gpio/infinity3/mhal_gpio_reg.h +@@ -0,0 +1,66 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_GPIO_H_ ++#define _REG_GPIO_H_ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++////8 bit define ++//CHIPTOP ++#define REG_FUART_MODE 0x06 ++#define REG_UART0_MODE 0x06 ++#define REG_UART1_MODE 0x07 ++#define REG_SR_MODE 0x0C ++#define REG_SR_I2C_MODE 0x0C ++#define REG_PWM0_MODE 0x0E ++#define REG_PWM1_MODE 0x0E ++#define REG_PWM2_MODE 0x0E ++#define REG_PWM3_MODE 0x0E ++#define REG_PWM4_MODE 0x0F ++#define REG_NAND_MODE 0x10 ++#define REG_SD_MODE 0x10 ++#define REG_SDIO_MODE 0x11 ++#define REG_I2C0_MODE 0x12 ++#define REG_I2C1_MODE 0x12 ++#define REG_SPI0_MODE 0x18 ++#define REG_SPI1_MODE 0x18 ++#define REG_EJ_MODE 0x1E ++#define REG_ETH_MODE 0x1E ++#define REG_CCIR_MODE 0x1E ++#define REG_TTL_MODE 0x1E ++#define REG_I2S_MODE 0x1F ++#define REG_DMIC_MODE 0x1F ++#define REG_TEST_IN_MODE 0x24 ++#define REG_TEST_OUT_MODE 0x24 ++#define REG_ALL_PAD_IN 0xA1 ++ ++//PMSLEEP ++#define REG_PMLOCK_L_MODE 0x24 ++#define REG_PMLOCK_H_MODE 0x25 ++#define REG_IRIN_MODE 0x38 ++ ++//SAR ++#define REG_SAR_MODE 0x22 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#endif // _REG_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/infinity3/mhal_pinmux.c b/drivers/mstar/gpio/infinity3/mhal_pinmux.c +new file mode 100644 +index 00000000..e6796929 +--- /dev/null ++++ b/drivers/mstar/gpio/infinity3/mhal_pinmux.c +@@ -0,0 +1,635 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information¡±) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include "mhal_gpio_reg.h" ++#include "mhal_gpio.h" ++#include "ms_platform.h" ++ ++#include "padmux.h" ++#include "gpio.h" ++ ++typedef struct stPadmux ++{ ++ U16 padID; ++ U16 base; ++ U16 offset; ++ U16 mask; ++ U16 val; ++ U16 mode; ++} ST_PADMUX; ++ ++ST_PADMUX padmux_table[]= ++{ ++ {PAD_GPIO0, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO0, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO0, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO1, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO1, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO1, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO2, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO2, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO2, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO3, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT6, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode4 */ ++ {PAD_GPIO3, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_FUART_MODE}, /* FUART mode2 */ ++ {PAD_GPIO3, CHIPTOP_BASE_ADDR, REG_I2S_MODE, BIT10, BIT10, PINMUX_FOR_I2S_MODE}, /* I2S mode1 */ ++ ++ {PAD_GPIO4, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode3 */ ++ {PAD_GPIO4, CHIPTOP_BASE_ADDR, REG_DMIC_MODE, BIT8, BIT8, PINMUX_FOR_DMIC_MODE}, /* DMIC mode */ ++ ++ {PAD_GPIO5, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode3 */ ++ {PAD_GPIO5, CHIPTOP_BASE_ADDR, REG_DMIC_MODE, BIT8, BIT8, PINMUX_FOR_DMIC_MODE}, /* DMIC mode */ ++ ++ {PAD_GPIO6, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9|BIT8, PINMUX_FOR_UART1_MODE}, /* UART1 mode3 */ ++ {PAD_GPIO6, CHIPTOP_BASE_ADDR, REG_DMIC_MODE, BIT8, BIT8, PINMUX_FOR_DMIC_MODE}, /* DMIC mode */ ++ ++ {PAD_GPIO7, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9|BIT8, PINMUX_FOR_UART1_MODE}, /* UART1 mode3 */ ++ {PAD_GPIO7, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO8, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO8, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO9, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO9, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO10, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO10, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO11, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode2 */ ++ {PAD_GPIO11, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO12, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO12, CHIPTOP_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode2 */ ++ {PAD_GPIO12, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO13, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO13, CHIPTOP_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode2 */ ++ {PAD_GPIO13, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO14, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO14, CHIPTOP_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode1 */ ++ {PAD_GPIO14, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_GPIO15, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode2 */ ++ {PAD_GPIO15, CHIPTOP_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode1 */ ++ {PAD_GPIO15, CHIPTOP_BASE_ADDR, REG_ETH_MODE, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, /* ETH mode */ ++ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_UART0_MODE}, /* UART0 mode2 */ ++ {PAD_FUART_RX, CHIPTOP_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode3 */ ++ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_UART0_MODE}, /* UART0 mode2 */ ++ {PAD_FUART_TX, CHIPTOP_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT3|BIT2, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode3 */ ++ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_UART1_MODE}, /* UART1 mode2 */ ++ {PAD_FUART_CTS, CHIPTOP_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode2 */ ++ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode3 */ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_FUART_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_FUART_MODE}, /* FUART mode1 */ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_UART1_MODE}, /* UART1 mode2 */ ++ {PAD_FUART_RTS, CHIPTOP_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode2 */ ++ ++ {PAD_I2C0_SCL, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode1 */ ++ {PAD_I2C0_SCL, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ ++ {PAD_I2C0_SDA, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode1 */ ++ {PAD_I2C0_SDA, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ ++ {PAD_I2C1_SCL, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode1 */ ++ {PAD_I2C1_SCL, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ ++ {PAD_I2C1_SDA, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode1 */ ++ {PAD_I2C1_SDA, CHIPTOP_BASE_ADDR, REG_SR_I2C_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode3 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode3 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO00, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode3 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode3 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO01, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO02, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO03, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO04, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO05, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO06, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO07, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO08, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO09, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO10, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO11, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ {PAD_SR_IO12, CHIPTOP_BASE_ADDR, REG_CCIR_MODE, BIT4, BIT4, PINMUX_FOR_CCIR_MODE}, /* CCIR mode */ ++ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO13, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO14, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2, PINMUX_FOR_SR_MODE}, /* SR mode4 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO15, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO16, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT0, PINMUX_FOR_SR_MODE}, /* SR mode1 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1, PINMUX_FOR_SR_MODE}, /* SR mode2 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT1|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode3 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT0, PINMUX_FOR_SR_MODE}, /* SR mode5 */ ++ {PAD_SR_IO17, CHIPTOP_BASE_ADDR, REG_SR_MODE, BIT2|BIT1|BIT0, BIT2|BIT1, PINMUX_FOR_SR_MODE}, /* SR mode6 */ ++ ++ {PAD_NAND_ALE, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_ALE, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_CLE, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_CEZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_WEZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_WPZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_REZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_SD_MODE}, /* SD mode1 */ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_RBZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA0, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA0, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT1, BIT1, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA0, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA1, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA1, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA2, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA2, CHIPTOP_BASE_ADDR, REG_PWM2_MODE, BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_PWM2_MODE}, /* PWM2 mode3 */ ++ {PAD_NAND_DA2, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA3, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA3, CHIPTOP_BASE_ADDR, REG_PWM3_MODE, BIT7|BIT6, BIT7|BIT6, PINMUX_FOR_PWM3_MODE}, /* PWM3 mode3 */ ++ {PAD_NAND_DA3, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_PWM4_MODE}, /* PWM4 mode1 */ ++ {PAD_NAND_DA4, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10 BIT10, PINMUX_FOR_PWM5_MODE}, /* PWM5 mode1 */ ++ {PAD_NAND_DA5, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT12, PINMUX_FOR_PWM6_MODE}, /* PWM6 mode1 */ ++ {PAD_NAND_DA6, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_NAND_MODE, BIT0, BIT0, PINMUX_FOR_NAND_MODE}, /* Nand mode1 */ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_EMMC_MODE, BIT0, BIT0, PINMUX_FOR_EMMC_MODE}, /* EMMC mode1 */ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT14, PINMUX_FOR_PWM7_MODE}, /* PWM7 mode1 */ ++ {PAD_NAND_DA7, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART0_RX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode1 */ ++ {PAD_UART0_RX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART0_TX, CHIPTOP_BASE_ADDR, REG_UART0_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_UART0_MODE}, /* UART0 mode1 */ ++ {PAD_UART0_TX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART1_RX, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_UART1_MODE},/* UART1 mode1 */ ++ {PAD_UART1_RX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_UART1_TX, CHIPTOP_BASE_ADDR, REG_UART1_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_UART1_MODE},/* UART1 mode1 */ ++ {PAD_UART1_TX, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_PWM4_MODE, BIT9|BIT8, BIT9, PINMUX_FOR_PWM4_MODE}, /* PWM4 mode2 */ ++ {PAD_SPI0_CZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_PWM5_MODE, BIT11|BIT10 BIT11, PINMUX_FOR_PWM5_MODE}, /* PWM5 mode2 */ ++ {PAD_SPI0_CK, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_PWM6_MODE, BIT13|BIT12, BIT13, PINMUX_FOR_PWM6_MODE}, /* PWM6 mode2 */ ++ {PAD_SPI0_DI, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_EJ_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_EJ_MODE}, /* EJ mode2 */ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_SPI0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_SPI0_MODE}, /* SPI0 mode1 */ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_PWM7_MODE, BIT15|BIT14, BIT15, PINMUX_FOR_PWM7_MODE}, /* PWM7 mode2 */ ++ {PAD_SPI0_DO, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_CZ, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_CZ, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_CK, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_CK, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_DI, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_DI, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_SPI1_DO, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode1 */ ++ {PAD_SPI1_DO, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode2 */ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode2 */ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, /* PWM0 mode1 */ ++ {PAD_PWM0, CHIPTOP_BASE_ADDR, REG_TTL_MODE, BIT6, BIT6, PINMUX_FOR_TTL_MODE}, /* TTL mode1 */ ++ ++ {PAD_PWM1, CHIPTOP_BASE_ADDR, REG_I2C0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_I2C0_MODE}, /* I2C0 mode2 */ ++ {PAD_PWM1, CHIPTOP_BASE_ADDR, REG_I2C1_MODE, BIT5|BIT4, BIT5, PINMUX_FOR_I2C1_MODE}, /* I2C1 mode2 */ ++ {PAD_PWM1, CHIPTOP_BASE_ADDR, REG_PWM1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM1_MODE}, /* PWM1 mode1 */ ++ ++ {PAD_SD_CLK, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_CLK, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_CMD, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_CMD, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D0, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D0, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D0, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D1, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D1, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D1, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D2, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D2, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D2, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_SD_D3, CHIPTOP_BASE_ADDR, REG_SPI1_MODE, BIT6|BIT5|BIT4, BIT5|BIT4, PINMUX_FOR_SPI1_MODE}, /* SPI1 mode3 */ ++ {PAD_SD_D3, CHIPTOP_BASE_ADDR, REG_SDIO_MODE, BIT8, BIT8, PINMUX_FOR_SDIO_MODE}, /* SDIO mode1 */ ++ {PAD_SD_D3, CHIPTOP_BASE_ADDR, REG_SD_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_SD_MODE}, /* SD mode2 */ ++ ++ {PAD_PM_SD_CDZ, PMSLEEP_BASE_ADDR, REG_SD_CDZ_MODE, BIT14, BIT14, PINMUX_FOR_SD_MODE}, ++ ++ /* PAD_PM_IRIN special case*/ ++ ++ {PAD_PM_GPIO0, PMSLEEP_BASE_ADDR, REG_PM_PWM0_MODE, BIT1|BIT0, BIT0, PINMUX_FOR_PWM0_MODE}, ++ ++ {PAD_PM_GPIO1, PMSLEEP_BASE_ADDR, REG_PM_PWM1_MODE, BIT3|BIT2, BIT2, PINMUX_FOR_PWM1_MODE}, ++ ++ {PAD_PM_GPIO2, PMSLEEP_BASE_ADDR, REG_PM_PWM2_MODE, BIT7|BIT6, BIT6, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_PM_GPIO3, PMSLEEP_BASE_ADDR, REG_PM_PWM3_MODE, BIT9|BIT8, BIT8, PINMUX_FOR_PWM3_MODE}, ++ ++ /* PAD_PM_GPIO4 special case */ ++ ++ {PAD_PM_GPIO5, PMSLEEP_BASE_ADDR, REG_PM_PWM1_MODE, BIT3|BIT2, BIT3, PINMUX_FOR_PWM1_MODE}, ++ ++ {PAD_PM_GPIO6, PMSLEEP_BASE_ADDR, REG_PM_PWM0_MODE, BIT1|BIT0, BIT1, PINMUX_FOR_PWM0_MODE}, ++ ++ /* PM_GPIO7 - only config as GPIO mode */ ++ ++ {PAD_PM_GPIO8, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3|BIT2, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_GPIO9, PMSLEEP_BASE_ADDR, REG_PM_PWM2_MODE, BIT7|BIT6, BIT7, PINMUX_FOR_PWM2_MODE}, ++ ++ {PAD_PM_GPIO10, PMSLEEP_BASE_ADDR, REG_PM_PWM3_MODE,BIT9|BIT8, BIT9, PINMUX_FOR_PWM3_MODE}, ++ ++ {PAD_PM_SPI_CZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_CK, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_DI, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_DO, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO, BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_WPZ, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT3, BIT3, PINMUX_FOR_PMSPI_MODE}, ++ ++ {PAD_PM_SPI_HLD, PMSLEEP_BASE_ADDR, REG_SPI_IS_GPIO,BIT7|BIT6, BIT6, PINMUX_FOR_SPI1_MODE}, ++ ++ {PAD_PM_LED0, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ ++ {PAD_PM_LED1, PMSLEEP_BASE_ADDR, REG_LED_MODE, BIT5|BIT4, BIT4, PINMUX_FOR_LED_MODE}, ++ ++ {PAD_SAR_GPIO0, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT0, BIT0, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO1, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT1, BIT1, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO2, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT2, BIT2, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_SAR_GPIO3, PM_SAR_BASE_ADDR, REG_SAR_MODE, BIT3, BIT3, PINMUX_FOR_SAR_MODE}, ++ ++ {PAD_ETH_RN, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT0, BIT0, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_RP, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT1, BIT1, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_TN, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT2, BIT2, PINMUX_FOR_ETH_MODE}, ++ ++ {PAD_ETH_TP, ALBANY2_BASE_ADDR, REG_ETH_GPIO_EN, BIT3, BIT3, PINMUX_FOR_ETH_MODE}, ++}; ++ ++ ++S32 halCheckPin(U32 padID) ++{ ++ if (GPIO_NR <= padID) ++ return FALSE; ++ ++ return TRUE; ++} ++/* ++S32 halPadGetVal(U32 padID, U32* mode) ++{ ++ U8 i = 0; ++ U8 fgModeIsFind = 0; ++ ++ if (FALSE == halCheckPin(padID)) ++ { ++ return FALSE; ++ } ++ ++ mode = PINMUX_FOR_GPIO_MODE; ++ ++ switch(padID) ++ { ++ case PAD_PM_GPIO4: ++ if( INREG16(PMSLEEP_BASE_ADDR<<9 + REG_GPIO_PM_LOCK<<2) == 0xBABE ) ++ { ++ return TRUE; ++ } ++ else ++ { ++ mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ } ++ ++ case PAD_PM_GPIO7: ++ return TRUE; ++ ++ case PAD_PM_SPI_CZ: ++ mode = PINMUX_FOR_UNKNOWN_MODE; ++ return FALSE; ++ ++ case PAD_PM_IRIN: ++ if( INREG16(PMSLEEP_BASE_ADDR<<9 + REG_IR_IS_GPIO<<2)&BIT4 == BIT4 ) ++ { ++ mode = PINMUX_FOR_GPIO_MODE; ++ } ++ else ++ { ++ mode = PINMUX_FOR_IRIN_MODE; ++ } ++ return TRUE; ++ ++ default: ++ for(i=0; i ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "mst_devid.h" ++ ++#include "mdrv_gpio.h" ++#include "mhal_gpio_reg.h" ++#include "mhal_gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++#if 0//reserved ++static struct semaphore pm_gpio_mutex ; ++#define _MUTEX_INIT() init_MUTEX( &pm_gpio_mutex ) ++#define _MUTEX_LOCK() down( &pm_gpio_mutex ) ++#define _MUTEX_UNLOCK() up( &pm_gpio_mutex ) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// GPIO chiptop initialization ++/// @return None ++/// @note Called only once at system initialization ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Init(void) ++{ ++ MHal_GPIO_Init(); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Init); ++ ++//------------------------------------------------------------------------------------------------- ++/// select one pad to set ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pad_Set(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Set); ++ ++//------------------------------------------------------------------------------------------------- ++/// enable output for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pad_Oen(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pad_Oen(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Oen); ++ ++//------------------------------------------------------------------------------------------------- ++/// enable input for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pad_Odn(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pad_Odn(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Odn); ++ ++//------------------------------------------------------------------------------------------------- ++/// read data from selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO) ++{ ++ return MHal_GPIO_Pad_Level(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pad_Read); ++ ++//------------------------------------------------------------------------------------------------- ++/// read pad direction for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_GPIO_Pad_InOut(U8 u8IndexGPIO) ++{ ++ return MHal_GPIO_Pad_InOut(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pad_InOut); ++ ++//------------------------------------------------------------------------------------------------- ++/// output pull high for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pull_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pull_High(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pull_High); ++ ++//------------------------------------------------------------------------------------------------- ++/// output pull low for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Pull_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Pull_Low(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Pull_Low); ++ ++//------------------------------------------------------------------------------------------------- ++/// output set high for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Set_High(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Set_High(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Set_High); ++ ++//------------------------------------------------------------------------------------------------- ++/// output set low for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Set_Low(U8 u8IndexGPIO) ++{ ++ MHal_GPIO_Set_Low(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Set_Low); ++ ++//------------------------------------------------------------------------------------------------- ++/// enable GPIO int for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_Enable_GPIO_INT(U8 u8IndexGPIO) ++{ ++ MHal_Enable_GPIO_INT(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_Enable_GPIO_INT); ++ ++int MDrv_GPIO_To_Irq(U8 u8IndexGPIO) ++{ ++ return MHal_GPIO_To_Irq(u8IndexGPIO); ++} ++EXPORT_SYMBOL(MDrv_GPIO_To_Irq); ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// set GPIO int polarity for selected one pad ++/// @param u8IndexGPIO \b IN: pad index ++/// @return None ++/// @note ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse) ++{ ++ MHal_GPIO_Set_POLARITY(u8IndexGPIO,reverse); ++} ++EXPORT_SYMBOL(MDrv_GPIO_Set_POLARITY); ++ ++ +diff --git a/drivers/mstar/gpio/mdrv_gpio.h b/drivers/mstar/gpio/mdrv_gpio.h +new file mode 100644 +index 00000000..28fb8788 +--- /dev/null ++++ b/drivers/mstar/gpio/mdrv_gpio.h +@@ -0,0 +1,62 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file mdrv_gpio.h ++/// @brief GPIO Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRV_GPIO_H_ ++#define _DRV_GPIO_H_ ++ ++#include ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++void MDrv_GPIO_Init(void); ++void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); ++void MDrv_GPIO_Pad_Oen(U8 u8IndexGPIO); ++void MDrv_GPIO_Pad_Odn(U8 u8IndexGPIO); ++U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO); ++U8 MDrv_GPIO_Pad_InOut(U8 u8IndexGPIO); ++void MDrv_GPIO_Pull_High(U8 u8IndexGPIO); ++void MDrv_GPIO_Pull_Low(U8 u8IndexGPIO); ++void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++void MDrv_Enable_GPIO_INT(U8 u8IndexGPIO); ++int MDrv_GPIO_To_Irq(U8 u8IndexGPIO); ++void MDrv_GPIO_PAD_32K_OUT(U8 u8Enable); ++void MDrv_GPIO_Set_POLARITY(U8 u8IndexGPIO,U8 reverse); ++ ++#endif // _DRV_GPIO_H_ ++ +diff --git a/drivers/mstar/gpio/mdrv_gpio_io.c b/drivers/mstar/gpio/mdrv_gpio_io.c +new file mode 100644 +index 00000000..0a65c45e +--- /dev/null ++++ b/drivers/mstar/gpio/mdrv_gpio_io.c +@@ -0,0 +1,278 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file mdrv_gpio_io.c ++/// @brief GPIO Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#include "mst_devid.h" ++ ++#include "mdrv_gpio_io.h" ++#include "mhal_gpio_reg.h" ++#include "mhal_gpio.h" ++#include "mdrv_gpio.h" ++#include "ms_platform.h" ++#include "gpio.h" ++ ++ ++//#include "mdrv_probe.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#define GPIO_DBG_ENABLE 0 ++ ++#if GPIO_DBG_ENABLE ++#define GPIO_DBG(_f) (_f) ++#else ++#define GPIO_DBG(_f) ++#endif ++ ++#if 0 ++#define LINE_DBG() printf("GPIO %d\n", __LINE__) ++#else ++#define LINE_DBG() ++#endif ++ ++#define GPIO_PRINT(fmt, args...) //printk("\n[GPIO][%05d] " fmt, __LINE__, ## args) ++ ++typedef struct ++{ ++ S32 s32MajorGPIO; ++ S32 s32MinorGPIO; ++ struct cdev cDevice; ++ struct file_operations GPIOFop; ++ struct fasync_struct *async_queue; /* asynchronous readers */ ++} GPIO_ModHandle_t; ++ ++ ++#define MOD_GPIO_DEVICE_COUNT 1 ++#define MOD_GPIO_NAME "ModGPIO" ++ ++#define MDRV_NAME_GPIO "gpio" ++#define MDRV_MAJOR_GPIO 0x9b ++#define MDRV_MINOR_GPIO 0x00 ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++static struct device *dev; ++ ++//static struct class *gpio_class; ++ ++static int mstar_gpio_request(struct gpio_chip *chip, unsigned offset) ++{ ++ MDrv_GPIO_Pad_Set(offset); ++ GPIO_PRINT("[mstar-gpio]mstar_gpio_request offset=%d\n",offset); ++ return 0; ++} ++ ++static void mstar_gpio_free(struct gpio_chip *chip, unsigned offset) ++{ ++ GPIO_PRINT("[mstar-gpio]mstar_gpio_free\n"); ++} ++ ++static void mstar_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ++{ ++ if(value==0) ++ MDrv_GPIO_Pull_Low(offset); ++ else ++ MDrv_GPIO_Pull_High(offset); ++ GPIO_PRINT("[mstar-gpio]mstar_gpio_set\n"); ++} ++ ++static int mstar_gpio_get(struct gpio_chip *chip, unsigned offset) ++{ ++ GPIO_PRINT("[mstar-gpio]mstar_gpio_get\n"); ++ return MDrv_GPIO_Pad_Read(offset); ++} ++ ++static int mstar_gpio_direction_input(struct gpio_chip *chip, unsigned offset) ++{ ++ GPIO_PRINT("[mstar-gpio]mstar_gpio_direction_input\n"); ++ MDrv_GPIO_Pad_Odn(offset); ++ return 0; ++} ++ ++static int mstar_gpio_direction_output(struct gpio_chip *chip, unsigned offset, ++ int value) ++{ ++ MDrv_GPIO_Pad_Oen(offset); ++ if(value==0) ++ MDrv_GPIO_Pull_Low(offset); ++ else ++ MDrv_GPIO_Pull_High(offset); ++ GPIO_PRINT("[mstar-gpio]mstar_gpio_direction_output\n"); ++ return 0; ++} ++ ++static int mstar_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++{ ++ int irq = MDrv_GPIO_To_Irq(offset); ++ //MDrv_Enable_GPIO_INT(offset); ++ //GPIO_PRINT("[mstar-gpio]mstar_gpio_to_irq,but not set reg\n"); ++ pr_err("[Mstar GPIO] gpio(%d) to irq(%d)\n", offset, irq); ++ return irq; ++} ++ ++static struct gpio_chip mstar_gpio_chip = { ++ .label = "gpio", ++ .request = mstar_gpio_request, ++ .free = mstar_gpio_free, ++ .direction_input = mstar_gpio_direction_input, ++ .get = mstar_gpio_get, ++ .direction_output = mstar_gpio_direction_output, ++ .set = mstar_gpio_set, ++ .to_irq = mstar_gpio_to_irq, ++ .base = 0, ++}; ++ ++ ++static const struct of_device_id mstar_gpio_of_match[] = { ++ { .compatible = "mstar,gpio" }, ++ { }, ++}; ++ ++static int mstar_gpio_probe(struct platform_device *pdev) ++{ ++ const struct of_device_id *match; ++ int ret; ++/* ++ struct resource *res; ++ void __iomem *base; ++ int gpionum; ++ struct device_node *node = pdev->dev.of_node; ++*/ ++ dev = &pdev->dev; ++ GPIO_PRINT("\n++[mstar-gpio]mstar_gpio_probe start\n"); ++/* ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gPadBaseAddr=(U32)base; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gChipBaseAddr=(U32)base; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gPmGpioBaseAddr=(U32)base; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 3); ++ base = (void *)(IO_ADDRESS(res->start)); ++ gPmSleepBaseAddr=(U32)base; ++ GPIO_PRINT("gPadBaseAddr=%x\n",gPadBaseAddr); ++ GPIO_PRINT("gChipBaseAddr=%x\n",gChipBaseAddr); ++ GPIO_PRINT("gPmGpioBaseAddr=%x\n",gPmGpioBaseAddr); ++*/ ++ match = of_match_device(mstar_gpio_of_match, &pdev->dev); ++ if (!match) { ++ printk("Error:[mstar-gpio] No device match found\n"); ++ return -ENODEV; ++ } ++// of_property_read_u32(node, "gpio-num", &gpionum); ++ ++ mstar_gpio_chip.ngpio = GPIO_NR; ++ mstar_gpio_chip.of_node = pdev->dev.of_node; ++ ret = gpiochip_add(&mstar_gpio_chip); ++ if (ret < 0) { ++ printk("[mstar-gpio]gpio_add err\n"); ++ return ret; ++ } ++ ++ GPIO_PRINT("--[mstar-gpio]mstar_gpio_probe end\n"); ++ ++ MDrv_GPIO_Init(); ++ printk(KERN_WARNING"GPIO: probe end"); ++ return 0; ++} ++ ++static struct platform_driver mstar_gpio_driver = { ++ .driver = { ++ .name = "gpio", ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_gpio_of_match, ++ }, ++ .probe = mstar_gpio_probe, ++}; ++ ++ ++ ++void __mod_gpio_init(void) ++{ ++ //GPIO chiptop initialization ++ MDrv_GPIO_Init(); ++} ++ ++ ++static int __init mstar_gpio_init(void) ++{ ++ return platform_driver_register(&mstar_gpio_driver); ++} ++postcore_initcall(mstar_gpio_init); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("GPIO driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/gpio/mdrv_sw_iic.c b/drivers/mstar/gpio/mdrv_sw_iic.c +new file mode 100644 +index 00000000..7ad378ef +--- /dev/null ++++ b/drivers/mstar/gpio/mdrv_sw_iic.c +@@ -0,0 +1,696 @@ ++// $Change: 592421 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file mdrv_iic.c ++/// @brief IIC Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++ ++#include ++#include ++ ++#include "mdrv_sw_iic.h" ++#include "mdrv_gpio.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++//#define OPEN_SWI2C_DEBUG ++ ++#ifdef OPEN_SWI2C_DEBUG ++#define swi2cDbg printk ++#else ++#define swi2cDbg(...) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++// for SW I2C ++#define _INPUT 1 ++#define _OUTPUT 0 ++#define _HIGH 1 ++#define _LOW 0 ++#define SWIIC_READ 0 ++#define SWIIC_WRITE 1 ++#define I2C_CHECK_PIN_DUMMY 3200/*6000*//*3200*/ ++#define I2C_ACKNOWLEDGE _LOW ++#define I2C_NON_ACKNOWLEDGE _HIGH ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++I2C_BusCfg_t g_I2CBusCfg[SW_IIC_NUM_OF_MAX]; ++int gpioi2c_delay_us = 20; //default ++int access_dummy_time = 1; //default ++ ++#define SWIIC_SCL_PIN(chNum, x) \ ++ ((x == _INPUT) ? MDrv_GPIO_Pad_Odn(g_I2CBusCfg[chNum].u8PadSCL) : MDrv_GPIO_Pad_Oen(g_I2CBusCfg[chNum].u8PadSCL)) ++ ++#define SWIIC_SDA_PIN(chNum, x) \ ++ ((x == _INPUT) ? MDrv_GPIO_Pad_Odn(g_I2CBusCfg[chNum].u8PadSDA) : MDrv_GPIO_Pad_Oen(g_I2CBusCfg[chNum].u8PadSDA)) ++ ++#define SWIIC_SCL_OUT(chNum, x) \ ++ ((x == _HIGH) ? MDrv_GPIO_Pull_High(g_I2CBusCfg[chNum].u8PadSCL) : MDrv_GPIO_Pull_Low(g_I2CBusCfg[chNum].u8PadSCL)) ++ ++#define SWIIC_SDA_OUT(chNum, x) \ ++ ((x == _HIGH) ? MDrv_GPIO_Pull_High(g_I2CBusCfg[chNum].u8PadSDA) : MDrv_GPIO_Pull_Low(g_I2CBusCfg[chNum].u8PadSDA)); ++ ++#define GET_SWIIC_SCL(chNum) MDrv_GPIO_Pad_Read(g_I2CBusCfg[chNum].u8PadSCL) ++ ++#define GET_SWIIC_SDA(chNum) MDrv_GPIO_Pad_Read(g_I2CBusCfg[chNum].u8PadSDA) ++ ++//#define SWII_DELAY(chNum) (_I2CBus[chNum].DefDelay) ++ ++#define _SDA_HIGH(chNum) SWIIC_SDA_PIN(chNum, _INPUT) ++#define _SDA_LOW(chNum) do { SWIIC_SDA_OUT(chNum, _LOW); SWIIC_SDA_PIN(chNum, _OUTPUT); } while(0) ++ ++#define _SCL_HIGH(chNum) SWIIC_SCL_PIN(chNum, _INPUT) ++#define _SCL_LOW(chNum) do { SWIIC_SCL_OUT(chNum, _LOW); SWIIC_SCL_PIN(chNum, _OUTPUT); } while(0) ++ ++ ++#define DISABLE 0 ++#define ENABLE 1 ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++void MDrv_SW_IIC_Delay(U8 u8ChIIC) ++{ ++/* ++ //U32 volatile u32Loop = DELAY_CYCLES(g_I2CBusCfg[u8ChIIC].u16SpeedKHz) / 2; ++ U32 volatile u32Loop=gpioi2c_delay_param; ++ ++ while(u32Loop--) ++ { ++ __asm__ __volatile__ ("mov r0, r0"); ++ } ++*/ ++ udelay(gpioi2c_delay_us); ++ ++} ++ ++void MDrv_SW_IIC_SCL(U8 u8ChIIC, U8 u8Data) ++{ ++ if ( u8Data == _HIGH ) ++ { ++ SWIIC_SCL_PIN(u8ChIIC, _INPUT); //set to input ++ } ++ else ++ { ++ SWIIC_SCL_OUT(u8ChIIC, _LOW); ++ SWIIC_SCL_PIN(u8ChIIC, _OUTPUT); ++ } ++} ++ ++void MDrv_SW_IIC_SDA(U8 u8ChIIC, U8 u8Data) ++{ ++ if ( u8Data == _HIGH ) ++ { ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); //set to input ++ } ++ else ++ { ++ //printk(KERN_INFO "SWIIC_SDA_OUT(u8ChIIC, _LOW)\r\n"); ++ SWIIC_SDA_OUT(u8ChIIC, _LOW); ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); //set to output ++ } ++} ++ ++void MDrv_SW_IIC_SCL_Chk(U8 u8ChIIC, U16 bSet) ++{ ++ U16 u16Dummy; // loop dummy ++ ++ if (bSet == _HIGH) // if set pin high ++ { ++ SWIIC_SCL_PIN(u8ChIIC, _INPUT); ++ u16Dummy = I2C_CHECK_PIN_DUMMY; // initialize dummy ++ ++ while ((GET_SWIIC_SCL(u8ChIIC) == _LOW) && (u16Dummy--)); ++ } ++ else ++ { ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); // set SCL pin ++ SWIIC_SCL_PIN(u8ChIIC, _OUTPUT); ++ } ++} ++ ++void MDrv_SW_IIC_SDA_Chk(U8 u8ChIIC, U16 bSet) ++{ ++ U16 u16Dummy; // loop dummy ++ ++ if (bSet == _HIGH) // if set pin high ++ { ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ u16Dummy = I2C_CHECK_PIN_DUMMY; // initialize dummy ++ while ((GET_SWIIC_SDA(u8ChIIC) == _LOW) && (u16Dummy--));// check SDA pull high ++ } ++ else ++ { ++ MDrv_SW_IIC_SDA(u8ChIIC, _LOW); // set SDA pin ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SW I2C: start signal. ++// ++// SCL ________ ++// \_________ ++// SDA _____ ++// \____________ ++// ++// Return value: None ++//------------------------------------------------------------------------------------------------- ++U16 MDrv_SW_IIC_Start(U8 u8ChIIC) ++{ ++ ++ U16 bStatus = TRUE; // success status ++ ++ //printk(KERN_INFO "u8ChIIC = %d \r\n", u8ChIIC); ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ // check pin error ++ SWIIC_SCL_PIN(u8ChIIC, _INPUT); ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ if ((GET_SWIIC_SCL(u8ChIIC) == _LOW) || (GET_SWIIC_SDA(u8ChIIC) == _LOW)) ++ { ++ SWIIC_SCL_PIN(u8ChIIC, _OUTPUT); ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ bStatus = FALSE; ++ } ++ else // success ++ { ++ MDrv_SW_IIC_SDA(u8ChIIC, _LOW); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ } ++ ++ return bStatus; //vain ++} ++ ++//------------------------------------------------------------------------------------------------- ++// SW I2C: stop signal. ++// ++// ____________ ++// SCL _______/ ++// _________ ++// SDA __________/ ++//------------------------------------------------------------------------------------------------- ++void MDrv_SW_IIC_Stop(U8 u8ChIIC) ++{ ++ _SCL_LOW(u8ChIIC); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ _SDA_LOW(u8ChIIC); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++// _SCL_HIGH(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); // <20091212 takerest> fix SCL pin error ++ MDrv_SW_IIC_Delay(u8ChIIC); ++// _SDA_HIGH(u8ChIIC); ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _HIGH); // <20091212 takerest> fix SDA pin error ++ MDrv_SW_IIC_Delay(u8ChIIC); ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Send 1 bytes data ++///@param u8data \b IN: 1 byte data to send ++//------------------------------------------------------------------------------------------------- ++static U16 _IIC_SendByte(U8 u8ChIIC, U8 u8data, U8 u8Delay4Ack ) // Be used int IIC_SendByte ++{ ++ U8 u8Mask = 0x80; ++ U16 bAck; // acknowledge bit ++ ++ while ( u8Mask ) ++ { ++ if (u8data & u8Mask) ++ { ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _HIGH); ++ } ++ else ++ { ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, _LOW); ++ } ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ #if 0//(EXTRA_DELAY_CYCLE) ++ if(SWII_DELAY(u8ChIIC) == 2) ++ { ++ MDrv_SW_IIC_DelayEx(u8ChIIC, 8); ++ } ++ #endif ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); // clock ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ u8Mask >>= 1; // next ++ } ++ ++ // recieve acknowledge ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ if( u8Delay4Ack > 0 ) ++ { ++ udelay( u8Delay4Ack ); ++ } ++ else ++ { ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ } ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ ++ bAck = GET_SWIIC_SDA(u8ChIIC); // recieve acknowlege ++// SWIIC_SDA(u8ChIIC, bAck); //for I2c waveform sharp ++// SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ MDrv_SW_IIC_SDA(u8ChIIC, (U8)bAck); //for I2c waveform sharp ++ SWIIC_SDA_PIN(u8ChIIC, _OUTPUT); ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ return (bAck); ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Send 1 bytes data, this function will retry 5 times until success. ++///@param u8data \b IN: 1 byte data to send ++///@return BOOLEAN: ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++U16 MDrv_SW_IIC_SendByte(U8 u8ChIIC, U8 u8data, U8 u8Delay4Ack ) ++{ ++ U8 u8I; ++ ++ //printk(KERN_INFO "send byte u8data = 0x%x \r\n", u8data); ++ ++ for(u8I=0;u8IFailed\n"); ++ continue; ++ } ++ ++ if ( MDrv_SW_IIC_SendByte(u8ChIIC, u8SlaveAdr, u8Delay4Ack) == TRUE ) //I2C_ACKNOWLEDGE) // check acknowledge ++ { ++ return TRUE; ++ } ++ MDrv_SW_IIC_Stop(u8ChIIC); ++ } ++ ++ //printk(KERN_INFO "MDrv_SW_IIC_SendByte u8SlaveAdr = 0x%x\r\n", u8SlaveAdr); ++ return FALSE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Get 1 bytes data ++///@param u16Ack \b IN: acknowledge ++///@return U8: \b OUT: get data from the device ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++U8 MDrv_SW_IIC_GetByte (U8 u8ChIIC, U16 u16Ack) ++{ ++ U8 u8Receive = 0; ++ U8 u8Mask = 0x80; ++ ++ SWIIC_SDA_PIN(u8ChIIC, _INPUT); ++ ++ while ( u8Mask ) ++ { ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ if (GET_SWIIC_SDA(u8ChIIC) == _HIGH) ++ { ++ u8Receive |= u8Mask; ++ } ++ u8Mask >>= 1; // next ++ ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ ++ #if 0//(EXTRA_DELAY_CYCLE) ++ if(SWII_DELAY(u8ChIIC) == 2) ++ { ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_DelayEx(u8ChIIC, 8); ++ } ++ #endif ++ } ++ if (u16Ack) ++ { ++ // acknowledge ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, I2C_ACKNOWLEDGE); ++ } ++ else ++ { ++ // non-acknowledge ++ MDrv_SW_IIC_SDA_Chk(u8ChIIC, I2C_NON_ACKNOWLEDGE); ++ } ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL_Chk(u8ChIIC, _HIGH); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_SCL(u8ChIIC, _LOW); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ MDrv_SW_IIC_Delay(u8ChIIC); ++ ++ return u8Receive; ++} ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Write bytes, be able to write 1 byte or several bytes to several register offsets in same slave address. ++///@param u8SlaveID \b IN: Slave ID (Address) ++///@param u8AddrCnt \b IN: register NO to write, this parameter is the NO of register offsets in pu8addr buffer, ++///it should be 0 when *pu8Addr = NULL. ++///@param *pu8Addr \b IN: pointer to a buffer containing target register offsets to write ++///@param u32BufLen \b IN: Data length (in byte) to write ++///@param *pu8Buf \b IN: pointer to the data buffer for write ++///@return BOOLEAN: ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++S32 MDrv_SW_IIC_Write(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf) ++{ ++ U8 u8Dummy; // loop dummy ++ S32 s32RetCountIIC; ++ ++ //check if sw i2c channel is disabled ++ if(g_I2CBusCfg[u8ChIIC].u8Enable == DISABLE) ++ return -1; ++ ++ u8Dummy = access_dummy_time; ++ s32RetCountIIC = u32BufLen; ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_Lock(); ++ #endif ++ ++ //printk(KERN_INFO "u8AddrCnt = %d u32BufLen = %d\r\n" , u8AddrCnt, u32BufLen); ++ while (u8Dummy--) ++ { ++ if (MDrv_SW_IIC_AccessStart(u8ChIIC, u8SlaveID, SWIIC_WRITE) == FALSE) ++ { ++ s32RetCountIIC = -2; ++ swi2cDbg(":write slave address failed,err=%d\r\n",s32RetCountIIC); ++ //OALMSG(1, (L":write slave address failed,err=%d\r\n",s32RetCountIIC)); ++ ++ goto SW_IIC_Write_End; ++ } ++ ++ while( u8AddrCnt ) ++ { ++ u8AddrCnt--; ++ if ( MDrv_SW_IIC_SendByte(u8ChIIC, *pu8Addr, 0) == FALSE ) ++ { ++ s32RetCountIIC = -3; ++ swi2cDbg(":write register address failed,err=%d\r\n",s32RetCountIIC); ++ goto SW_IIC_Write_End; ++ } ++ pu8Addr++; ++ } ++ while (u32BufLen) // loop of writting data ++ { ++ u32BufLen-- ; ++ if ( MDrv_SW_IIC_SendByte(u8ChIIC, *pu8Buf, 0) == FALSE ) ++ { ++ s32RetCountIIC = -4; ++ swi2cDbg(":write data failed,err=%d\r\n",s32RetCountIIC); ++ goto SW_IIC_Write_End; ++ } ++ pu8Buf++; // next byte pointer ++ } ++ ++ break; ++ } ++ ++SW_IIC_Write_End: ++ MDrv_SW_IIC_Stop(u8ChIIC); ++ ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_UnLock(); ++ #endif ++ return s32RetCountIIC; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++///SW I2C: Read bytes, be able to read 1 byte or several bytes from several register offsets in same slave address. ++///@param u8SlaveID \b IN: Slave ID (Address) ++///@param u8AddrCnt \b IN: register NO to read, this parameter is the NO of register offsets in pu8addr buffer, ++///it should be 0 when *paddr = NULL. ++///@param *pu8Addr \b IN: pointer to a buffer containing target register offsets to read ++///@param u32BufLen \b IN: Data length (in byte) to read ++///@param *pu8Buf \b IN: pointer to retun data buffer. ++///@return BOOLEAN: ++///- TRUE: Success ++///- FALSE: Fail ++//------------------------------------------------------------------------------------------------- ++S32 MDrv_SW_IIC_Read(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf) ++{ ++ U8 u8Dummy; // loop dummy ++ S32 s32RetCountIIC; ++ ++ //check if sw i2c channel is disabled ++ if(g_I2CBusCfg[u8ChIIC].u8Enable == DISABLE) ++ return -1; ++ ++ u8Dummy = access_dummy_time; ++ s32RetCountIIC = u32BufLen; ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_Lock(); ++ #endif ++ ++ while (u8Dummy--) ++ { ++ if( u8AddrCnt > 0 ) ++ { ++ if (MDrv_SW_IIC_AccessStart(u8ChIIC, u8SlaveID, SWIIC_WRITE) == FALSE) ++ { ++ s32RetCountIIC = -2; ++ swi2cDbg(":write slave address failed,err=%d\r\n",s32RetCountIIC); ++ //printk(KERN_INFO "%s:write slave address failed,err=%d\n",__FUNCTION__,s32RetCountIIC); ++ goto SW_IIC_Read_End; ++ } ++ ++ while( u8AddrCnt ) ++ { ++ u8AddrCnt--; ++ //printk(KERN_INFO "%s:pu8Addr=0x%02x\n",__FUNCTION__,*pu8Addr); ++ if (MDrv_SW_IIC_SendByte(u8ChIIC, *pu8Addr, 0) == FALSE) ++ { ++ s32RetCountIIC = -3; ++ swi2cDbg(":write register address failed,err=%d\r\n",s32RetCountIIC); ++ //printk(KERN_INFO "%s:write register address failed,err=%d\n",__FUNCTION__,s32RetCountIIC); ++ goto SW_IIC_Read_End; ++ } ++ pu8Addr++; ++ } ++ } ++ ++ if (MDrv_SW_IIC_AccessStart(u8ChIIC, u8SlaveID, SWIIC_READ) == FALSE) ++ { ++ s32RetCountIIC = -4; ++ swi2cDbg(":write slave address failed,err=%d\r\n",s32RetCountIIC); ++ //printk(KERN_INFO "%s:write slave address failed,err=%d\n",__FUNCTION__,s32RetCountIIC); ++ goto SW_IIC_Read_End; ++ } ++ ++ while (u32BufLen--) // loop to burst read ++ { ++ *pu8Buf = MDrv_SW_IIC_GetByte(u8ChIIC, (U16)u32BufLen); // receive byte ++ //printk(KERN_INFO "%s:pu8Buf=0x%02x\n",__FUNCTION__,*pu8Buf); ++ pu8Buf++; // next byte pointer ++ } ++ ++ break; ++ } ++ ++SW_IIC_Read_End: ++ MDrv_SW_IIC_Stop(u8ChIIC); ++ ++ #ifdef SWI2C_LOCK ++ MDrv_SW_IIC_UnLock(); ++ #endif ++ return s32RetCountIIC; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC Set Speed by Index ++/// @param u8ChIIC \b IN: channel index ++/// @param u8Speed \b IN: u8Speed index ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MDrv_SW_IIC_SetSpeed(U8 u8ChIIC, U8 u8Speed) ++{ ++ ++ //switch(SWII_DELAY(u8ChIIC)) ++ switch(u8Speed) ++ { ++ case 1: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 400; //KHz ++ break; ++ case 2: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 300; //KHz ++ break; ++ case 3: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 200; //KHz ++ break; ++ case 4: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 100; //KHz ++ break; ++ default: ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = 100; //KHz ++ break; ++ } ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC Bus Enable or Disable ++/// @param u8ChIIC \b IN: channel index ++/// @param bEnable \b IN: enable ++/// @return None ++//------------------------------------------------------------------------------------------------- ++void MDrv_SW_IIC_Enable( U8 u8ChIIC, U8 bEnable ) ++{ ++ g_I2CBusCfg[u8ChIIC].u8Enable = bEnable; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC Bus Configuration ++/// @param pBusCfg \b IN: clock selection ++/// @return None ++//------------------------------------------------------------------------------------------------- ++U16 MDrv_SW_IIC_ConfigBus(I2C_BusCfg_t* pBusCfg) ++{ ++ U8 u8ChIIC; ++ ++ ++ swi2cDbg("[%s] Channel index = %d \r\n",__FUNCTION__,pBusCfg->u8ChIdx); ++ swi2cDbg("[%s] Channel PadSCL = %d \r\n",__FUNCTION__,pBusCfg->u8PadSCL); ++ swi2cDbg("[%s] Channel PadSDA = %d \r\n",__FUNCTION__,pBusCfg->u8PadSDA); ++ swi2cDbg("[%s] Channel SpeedKHz = %d \r\n",__FUNCTION__,pBusCfg->u16SpeedKHz); ++ swi2cDbg("[%s] Channel Enable = %d \r\n",__FUNCTION__,pBusCfg->u8Enable); ++ u8ChIIC = pBusCfg->u8ChIdx; ++ g_I2CBusCfg[u8ChIIC].u8ChIdx = pBusCfg->u8ChIdx; ++ g_I2CBusCfg[u8ChIIC].u8PadSCL = pBusCfg->u8PadSCL; ++ g_I2CBusCfg[u8ChIIC].u8PadSDA = pBusCfg->u8PadSDA; ++ g_I2CBusCfg[u8ChIIC].u16SpeedKHz = pBusCfg->u16SpeedKHz; ++ g_I2CBusCfg[u8ChIIC].u8Enable = pBusCfg->u8Enable; ++ pBusCfg++; ++ ++ return TRUE; ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// IIC master initialization ++/// @return None ++/// @note Hardware IIC. Called only once at system initialization ++//------------------------------------------------------------------------------------------------- ++void MDrv_IIC_Init(void) ++{ ++ U8 u8ChIIC; ++ for(u8ChIIC=0;u8ChIIC ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++#define SW_IIC_NUM_OF_MAX (5) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++struct I2C_BusCfg ++{ ++ U8 u8ChIdx; ///Channel index ++ U8 u8PadSCL; ///Pad(Gpio) number for SCL ++ U8 u8PadSDA; ///Pad(Gpio) number for SDA ++ U16 u16SpeedKHz; ///Speed in KHz ++ U8 u8Enable; ///Enable ++} ; ++//} __attribute__ ((packed)); ++ ++typedef struct I2C_BusCfg I2C_BusCfg_t; ++extern int gpioi2c_delay_us; ++extern int access_dummy_time; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++// for software IIC ++void MDrv_SW_IIC_SetSpeed(U8 u8ChIIC, U8 u8Speed); ++void MDrv_SW_IIC_Delay(U8 u8ChIIC); ++void MDrv_SW_IIC_SCL(U8 u8ChIIC, U8 u8Data); ++void MDrv_SW_IIC_SDA(U8 u8ChIIC, U8 u8Data); ++void MDrv_SW_IIC_SCL_Chk(U8 u8ChIIC, U16 bSet); ++void MDrv_SW_IIC_SDA_Chk(U8 u8ChIIC, U16 bSet); ++U16 MDrv_SW_IIC_Start(U8 u8ChIIC); ++void MDrv_SW_IIC_Stop(U8 u8ChIIC); ++U16 MDrv_SW_IIC_SendByte(U8 u8ChIIC, U8 u8data, U8 u8Delay4Ack); ++U16 MDrv_SW_IIC_AccessStart(U8 u8ChIIC, U8 u8SlaveAdr, U8 u8Trans); ++U8 MDrv_SW_IIC_GetByte (U8 u8ChIIC, U16 u16Ack); ++S32 MDrv_SW_IIC_Write(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf); ++S32 MDrv_SW_IIC_Read(U8 u8ChIIC, U8 u8SlaveID, U8 u8AddrCnt, U8* pu8Addr, U32 u32BufLen, U8* pu8Buf); ++#if (defined(CONFIG_MSTAR_TITANIA)||defined(CONFIG_MSTAR_TITANIA2)) ++#else ++void MDrv_SW_IIC_Enable( U8 u8ChIIC, U8 bEnable ); ++#endif ++U16 MDrv_SW_IIC_ConfigBus(I2C_BusCfg_t* pBusCfg); ++void MDrv_IIC_Init(void); ++ ++#endif // _DRV_IIC_H_ +diff --git a/drivers/mstar/gpio/ms_gpioi2c.c b/drivers/mstar/gpio/ms_gpioi2c.c +new file mode 100644 +index 00000000..787a9cda +--- /dev/null ++++ b/drivers/mstar/gpio/ms_gpioi2c.c +@@ -0,0 +1,232 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "mdrv_sw_iic.h" ++#include "ms_msys.h" ++ ++#define GPIO_I2C_READ 0x01 ++#define GPIO_I2C_WRITE 0x03 ++ ++struct cdev ms_gpioi2c_cdev; ++int ms_gpioi2c_major; ++int ms_gpioi2c_minor_start=0; ++int ms_gpioi2c_dev_count=3; ++ ++static ssize_t access_retry_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ access_dummy_time = simple_strtoul(buf, NULL, 10); ++ printk("\naccess_dummy_time=%d\n", access_dummy_time); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t access_retry_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", access_dummy_time); ++ return (str - buf); ++} ++DEVICE_ATTR(access_retry, 0644, access_retry_show, access_retry_store); ++ ++static ssize_t gpioi2c_delay_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ gpioi2c_delay_us = simple_strtoul(buf, NULL, 10); ++ printk("\ngpioi2c_delay_us=%d\n", gpioi2c_delay_us); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t gpioi2c_delay_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", gpioi2c_delay_us); ++ return (str - buf); ++} ++DEVICE_ATTR(gpioi2c_delay, 0644, gpioi2c_delay_show, gpioi2c_delay_store); ++ ++ ++unsigned char gpio_i2c_read(unsigned char devaddress, unsigned char address) ++{ ++ int rxdata; ++ ++ MDrv_SW_IIC_Start(0); ++ MDrv_SW_IIC_SendByte(0, devaddress, 0); ++ MDrv_SW_IIC_SendByte(0, address, 0); ++ MDrv_SW_IIC_Start(0); ++ MDrv_SW_IIC_SendByte(0, (devaddress | 1), 0); ++ rxdata = MDrv_SW_IIC_GetByte(0, FALSE); ++ MDrv_SW_IIC_Stop(0); ++ return rxdata; ++} ++EXPORT_SYMBOL(gpio_i2c_read); ++ ++void gpio_i2c_write(unsigned char devaddress, unsigned char address, unsigned char data) ++{ ++ MDrv_SW_IIC_Start(0); ++ MDrv_SW_IIC_SendByte(0, devaddress, 0); ++ MDrv_SW_IIC_SendByte(0, address, 0); ++ MDrv_SW_IIC_SendByte(0, data, 0); ++ MDrv_SW_IIC_Stop(0); ++} ++EXPORT_SYMBOL(gpio_i2c_write); ++ ++ ++long gpioi2c_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ unsigned int val; ++ char device_addr, reg_addr; ++ short reg_val; ++ ++ switch(cmd) ++ { ++ case GPIO_I2C_READ: ++ //printk("GPIO_I2C_READ arg=0x%08X\n", *(unsigned int *)arg); ++ val = *(unsigned int *)arg; ++ device_addr = (val&0xff000000)>>24; ++ reg_addr = (val&0xff0000)>>16; ++ ++ reg_val = gpio_i2c_read(device_addr, reg_addr); ++ *(unsigned int *)arg = (val&0xffff0000)|reg_val; ++ ++ break; ++ ++ case GPIO_I2C_WRITE: ++ //printk("GPIO_I2C_WRITE arg=0x%08X\n", *(unsigned int *)arg); ++ val = *(unsigned int *)arg; ++ device_addr = (val&0xff000000)>>24; ++ reg_addr = (val&0xff0000)>>16; ++ ++ reg_val = val&0xffff; ++ gpio_i2c_write(device_addr, reg_addr, reg_val); ++ ++ break; ++ ++ default: ++ return -1; ++ } ++ return 0; ++} ++ ++ ++int gpioi2c_open(struct inode * inode, struct file * file) ++{ ++ return 0; ++} ++int gpioi2c_close(struct inode * inode, struct file * file) ++{ ++ return 0; ++} ++ ++static struct file_operations gpioi2c_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gpioi2c_ioctl, ++ .open = gpioi2c_open, ++ .release = gpioi2c_close, ++}; ++ ++static int ms_gpioi2c_probe(struct platform_device *pdev) ++{ ++ int err, sda, scl; ++ dev_t dev; ++ I2C_BusCfg_t gpioi2c_cfg; ++ struct device* gpioi2c_dev; ++ ++ MDrv_IIC_Init(); ++ ++ if(0 != of_property_read_u32(pdev->dev.of_node, "sda-gpio", &sda)) ++ return -EINVAL; ++ ++ if(0 != of_property_read_u32(pdev->dev.of_node, "scl-gpio", &scl)) ++ return -EINVAL; ++ ++ gpioi2c_cfg.u8ChIdx = 0; ++ gpioi2c_cfg.u8PadSDA = sda; ++ gpioi2c_cfg.u8PadSCL = scl; ++ gpioi2c_cfg.u16SpeedKHz = 100; //gpioi2c no used ++ gpioi2c_cfg.u8Enable = ENABLE; ++ ++ MDrv_SW_IIC_ConfigBus(&gpioi2c_cfg); ++ ++ if (0 != (err = alloc_chrdev_region(&dev, ms_gpioi2c_minor_start, ms_gpioi2c_dev_count, "mstar_gpioi2c"))) ++ return err; ++ ++ ms_gpioi2c_major = MAJOR(dev); ++ ++ cdev_init(&ms_gpioi2c_cdev, &gpioi2c_fops); ++ ms_gpioi2c_cdev.owner=THIS_MODULE; ++ ++ if(0 != (err = cdev_add(&ms_gpioi2c_cdev, dev, ms_gpioi2c_dev_count))) ++ return err; ++ ++ gpioi2c_dev = device_create(msys_get_sysfs_class(), NULL, dev, NULL, "gpioi2c"); ++ ++ device_create_file(gpioi2c_dev, &dev_attr_gpioi2c_delay); ++ device_create_file(gpioi2c_dev, &dev_attr_access_retry); ++ ++ printk("[ms_gpioi2c] sda-gpio=%d, scl-gpio=%d\n", sda, scl); ++ ++ return err; ++} ++ ++static int ms_gpioi2c_remove(struct platform_device *pdev) ++{ ++ printk("[ms_gpioi2c] removed\n"); ++ ++ cdev_del(&ms_gpioi2c_cdev); ++ unregister_chrdev_region(MKDEV(ms_gpioi2c_major, ms_gpioi2c_minor_start), ms_gpioi2c_dev_count); ++ device_destroy(msys_get_sysfs_class(), MKDEV(ms_gpioi2c_major, ms_gpioi2c_dev_count)); ++ ++ return 0; ++} ++ ++static const struct of_device_id ms_gpioi2c_of_match_table[] = { ++ { .compatible = "mstar,infinity-gpioi2c" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_gpioi2c_of_match_table); ++ ++static struct platform_driver ms_gpioi2c_driver = { ++ .remove = ms_gpioi2c_remove, ++ .probe = ms_gpioi2c_probe, ++ .driver = { ++ .name = "ms_gpioi2c_driver", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_gpioi2c_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_gpioi2c_driver); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms_sw_iic driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/i2c/Kconfig b/drivers/mstar/i2c/Kconfig +new file mode 100644 +index 00000000..c49f92d9 +--- /dev/null ++++ b/drivers/mstar/i2c/Kconfig +@@ -0,0 +1,19 @@ ++config MS_I2C ++ tristate "Mstar I2C driver" ++ help ++ MStar I2C driver function ++ ++config MS_I2C_CEDRIC ++ tristate "I2C driver support for Cedric" ++ depends on MS_I2C ++ depends on ARCH_CEDRIC ++ ++config MS_I2C_INFINITY ++ tristate "I2C driver support for iNfinity" ++ depends on MS_I2C ++ depends on ARCH_INFINITY ++ ++config MS_I2C_INFINITY3 ++ tristate "I2C driver support for iNfinity3" ++ depends on MS_I2C ++ depends on ARCH_INFINITY3 +diff --git a/drivers/mstar/i2c/Makefile b/drivers/mstar/i2c/Makefile +new file mode 100644 +index 00000000..eddf9a83 +--- /dev/null ++++ b/drivers/mstar/i2c/Makefile +@@ -0,0 +1,23 @@ ++# ++# Makefile for MStar IIC device drivers. ++# ++ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++# general options ++# EXTRA_CFLAGS += -Idrivers/mstar/common ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/i2c ++EXTRA_CFLAGS += -Idrivers/mstar/i2c/$(CONFIG_MSTAR_CHIP_NAME) ++ ++ ++# specific options ++EXTRA_CFLAGS += -DTITANIA ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# files ++obj-$(CONFIG_MS_I2C_CEDRIC) += ms_iic.o $(CONFIG_MSTAR_CHIP_NAME)/mhal_iic.o ++obj-$(CONFIG_MS_I2C_INFINITY) +=ms_iic.o $(CONFIG_MSTAR_CHIP_NAME)/mhal_iic.o ++obj-$(CONFIG_MS_I2C_INFINITY3) +=ms_iic.o $(CONFIG_MSTAR_CHIP_NAME)/mhal_iic.o ++ ++# export header files ++EXPORT_H_FILES += mdrv_iic_io.h +diff --git a/drivers/mstar/i2c/cedric/Makefile b/drivers/mstar/i2c/cedric/Makefile +new file mode 100644 +index 00000000..240c4cef +--- /dev/null ++++ b/drivers/mstar/i2c/cedric/Makefile +@@ -0,0 +1,23 @@ ++# ++# Makefile for MStar IIC HAL drivers. ++# ++ ++ ++#ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++#include $(TOP_DIR)/modules.mk ++#endif ++ ++ ++#CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/mstar/common ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/i2c ++EXTRA_CFLAGS += -Idrivers/mstar/i2c/cedric3 ++ ++# specific options ++#EXTRA_CFLAGS += -Iinclude/asm-mips/titania ++ ++# files ++#obj-$(CONFIG_MSTAR_IIC) += mhal_iic.o +diff --git a/drivers/mstar/i2c/cedric/mhal_iic.c b/drivers/mstar/i2c/cedric/mhal_iic.c +new file mode 100644 +index 00000000..1b0a7276 +--- /dev/null ++++ b/drivers/mstar/i2c/cedric/mhal_iic.c +@@ -0,0 +1,1702 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (3) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __FUNCTION__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase = 0; ++static U32 _gMChipIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase = u32Base; ++ _gMChipIO_MapBase=u32ChipBase; ++ //HWI2C_HAL_INFO("HWI2C IOMap base:%16lx Reg offset:%4x\n", u32Base, (U16)HWI2C_REG_BASE); ++ printk("\n HWI2C IOMap base:%x \n", u32Base); ++ printk("\n HWI2C u32ChipBase base:%x \n", u32ChipBase); ++ ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ //return ((volatile U16*)(_gMIO_MapBase))[u32RegAddr]; ++ return (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase, u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ //((volatile U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val; ++ //HAL_HWI2C_WriteByte(u32RegAddr,LOWBYTE(u16Val)); ++ //HAL_HWI2C_WriteByte(u32RegAddr+1,HIBYTE(u16Val)); ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u8Mask: %x bEnable: %x\n", _gMIO_MapBase, u32RegAddr, u8Mask, bEnable); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, u32MiuAddr); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port); ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ return TRUE; ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet; ++ HWI2C_HAL_FUNC(); ++ ++ //if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ // return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,TRUE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ {//port 2 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(int ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ ++ } ++ else if(ePort==1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else ++ { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ break; ++ } ++ } ++ } ++ } ++ HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_ERR("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_ERR("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++#endif +diff --git a/drivers/mstar/i2c/cedric/mhal_iic.h b/drivers/mstar/i2c/cedric/mhal_iic.h +new file mode 100644 +index 00000000..923b1081 +--- /dev/null ++++ b/drivers/mstar/i2c/cedric/mhal_iic.h +@@ -0,0 +1,283 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @author MStar Semiconductor Inc. ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(int ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/mstar/i2c/cedric/mhal_iic_reg.h b/drivers/mstar/i2c/cedric/mhal_iic_reg.h +new file mode 100644 +index 00000000..340614e6 +--- /dev/null ++++ b/drivers/mstar/i2c/cedric/mhal_iic_reg.h +@@ -0,0 +1,293 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_GPIO1_REG_BASE+ (0x01*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT2) ++ #define CHIP_MIIC0_PAD_MSK (__BIT2) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT1) ++ #define CHIP_MIIC1_PAD_MSK (__BIT1) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE ++ #define CHIP_DDCR_PAD_0 (0) ++ #define CHIP_DDCR_PAD_1 (__BIT1) ++ #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/mstar/i2c/infinity/Makefile b/drivers/mstar/i2c/infinity/Makefile +new file mode 100644 +index 00000000..240c4cef +--- /dev/null ++++ b/drivers/mstar/i2c/infinity/Makefile +@@ -0,0 +1,23 @@ ++# ++# Makefile for MStar IIC HAL drivers. ++# ++ ++ ++#ifeq ($(MAKE_TYPE), MODULE_STANDALONE) ++#include $(TOP_DIR)/modules.mk ++#endif ++ ++ ++#CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++# EXTRA_CFLAGS += -Idrivers/mstar/common ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/i2c ++EXTRA_CFLAGS += -Idrivers/mstar/i2c/cedric3 ++ ++# specific options ++#EXTRA_CFLAGS += -Iinclude/asm-mips/titania ++ ++# files ++#obj-$(CONFIG_MSTAR_IIC) += mhal_iic.o +diff --git a/drivers/mstar/i2c/infinity/mhal_iic.c b/drivers/mstar/i2c/infinity/mhal_iic.c +new file mode 100644 +index 00000000..ceb6dedf +--- /dev/null ++++ b/drivers/mstar/i2c/infinity/mhal_iic.c +@@ -0,0 +1,1740 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __FUNCTION__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase = 0; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase = u32Base; ++ _gMChipIO_MapBase=u32ChipBase; ++ _gMClkIO_MapBase=u32ClkBase; ++ //HWI2C_HAL_INFO("HWI2C IOMap base:%16lx Reg offset:%4x\n", u32Base, (U16)HWI2C_REG_BASE); ++// printk(" HWI2C IOMap base:%x \n", u32Base); ++// printk("HWI2C u32ChipBase base:%x\n ", u32ChipBase); ++// printk(" HWI2C u32ClkBase base:%x \n", u32ClkBase); ++ ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ //return ((volatile U16*)(_gMIO_MapBase))[u32RegAddr]; ++ return (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase, u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMIO_MapBase, u32RegAddr,(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ //((volatile U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val; ++ //HAL_HWI2C_WriteByte(u32RegAddr,LOWBYTE(u16Val)); ++ //HAL_HWI2C_WriteByte(u32RegAddr+1,HIBYTE(u16Val)); ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u8Mask: %x bEnable: %x\n", _gMIO_MapBase, u32RegAddr, u8Mask, bEnable); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ //return ((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)]; ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ //((volatile U8*)(_gMIO_MapBase))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMClkIO_MapBase, u32RegAddr); ++ //return ((volatile U16*)(_gMIO_MapBase))[u32RegAddr]; ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ if (!u32RegAddr) ++ { ++ HWI2C_HAL_ERR("%s reg error!\n", __FUNCTION__); ++ return FALSE; ++ } ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx u32RegAddr:%16lx\n", _gMClkIO_MapBase, u32RegAddr,(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ //((volatile U16*)(_gMIO_MapBase))[u32RegAddr] = u16Val; ++ //HAL_HWI2C_WriteByte(u32RegAddr,LOWBYTE(u16Val)); ++ //HAL_HWI2C_WriteByte(u32RegAddr+1,HIBYTE(u16Val)); ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%8lx\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, u32MiuAddr); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port); ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ return TRUE; ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet; ++ HWI2C_HAL_FUNC(); ++ ++ //if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ // return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,TRUE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ {//port 2 : bank register address 0x111A00 ++ *pu16Offset = (U16)0x200; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ {//port 2 : bank register address 0x111B00 ++ *pu16Offset = (U16)0x300; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_1)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(int ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ //HAL_HWI2C_WriteClkByteMask((0x37*2), 0x08, 0x09); ++ } ++ else if(ePort==1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ //HAL_HWI2C_WriteClkByteMask((0x37*2), 0x800, 0x900); ++ } ++ else ++ { ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ break; ++ } ++ } ++ } ++ } ++ HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_ERR("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_ERR("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++#endif +diff --git a/drivers/mstar/i2c/infinity/mhal_iic.h b/drivers/mstar/i2c/infinity/mhal_iic.h +new file mode 100644 +index 00000000..bfac8d27 +--- /dev/null ++++ b/drivers/mstar/i2c/infinity/mhal_iic.h +@@ -0,0 +1,283 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @author MStar Semiconductor Inc. ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(HAL_HWI2C_PORT ePort, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(int ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/mstar/i2c/infinity/mhal_iic_reg.h b/drivers/mstar/i2c/infinity/mhal_iic_reg.h +new file mode 100644 +index 00000000..2a7d1606 +--- /dev/null ++++ b/drivers/mstar/i2c/infinity/mhal_iic_reg.h +@@ -0,0 +1,293 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_GPIO1_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) //0x1EDC ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE ++ #define CHIP_DDCR_PAD_0 (0) ++ #define CHIP_DDCR_PAD_1 (__BIT1) ++ #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/mstar/i2c/infinity3/Makefile b/drivers/mstar/i2c/infinity3/Makefile +new file mode 100644 +index 00000000..3bd6bb2d +--- /dev/null ++++ b/drivers/mstar/i2c/infinity3/Makefile +@@ -0,0 +1,3 @@ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/i2c +diff --git a/drivers/mstar/i2c/infinity3/mhal_iic.c b/drivers/mstar/i2c/infinity3/mhal_iic.c +new file mode 100644 +index 00000000..9ad111d5 +--- /dev/null ++++ b/drivers/mstar/i2c/infinity3/mhal_iic.c +@@ -0,0 +1,1786 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef _HAL_IIC_C_ ++#define _HAL_IIC_C_ ++ ++#include "ms_platform.h" ++#include "mhal_iic.h" ++#include "mhal_iic_reg.h" ++#include "../ms_iic.h" ++ ++#if 0 // For GPIO (emac orange led) trigger debug ++#include "infinity/gpio.h" ++extern void MDrv_GPIO_Set_Low(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Set_High(U8 u8IndexGPIO); ++#endif ++ ++#define LOWBYTE(w) ((w) & 0x00ff) ++#define HIBYTE(w) (((w) >> 8) & 0x00ff) ++ ++ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++/////////////////////////////////////////////////////////////////////////////// ++#define HWI2C_HAL_RETRY_TIMES (5) ++#define HWI2C_HAL_WAIT_TIMEOUT 65535////30000//(1500) ++#define HWI2C_HAL_FUNC() //{printk("=============%s\n", __func__);} ++#define HWI2C_HAL_INFO(x, args...) //{printk(x, ##args);} ++#define HWI2C_HAL_ERR(x, args...) {printk(x, ##args);} ++#ifndef UNUSED ++#define UNUSED(x) ((x)=(x)) ++#endif ++ ++#define HWI2C_DMA_CMD_DATA_LEN 7 ++#define HWI2C_DMA_WAIT_TIMEOUT (30000) ++#define HWI2C_DMA_WRITE 0 ++#define HWI2C_DMA_READ 1 ++#define _PA2VA(x) (U32)MsOS_PA2KSEG1((x)) ++#define _VA2PA(x) (U32)MsOS_VA2PA((x)) ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local variable ++//////////////////////////////////////////////////////////////////////////////// ++static U32 _gMIO_MapBase[HAL_HWI2C_PORTS] = {0}; ++static U32 _gMChipIO_MapBase = 0; ++static U32 _gMClkIO_MapBase = 0; ++static BOOL g_bLastByte[HAL_HWI2C_PORTS]; ++static U32 g_u32DmaPhyAddr[HAL_HWI2C_PORTS]; ++static HAL_HWI2C_PortCfg g_stPortCfg[HAL_HWI2C_PORTS]; ++static U16 g_u16DmaDelayFactor[HAL_HWI2C_PORTS]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Function Declaration ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Function ++//////////////////////////////////////////////////////////////////////////////// ++ ++U32 MsOS_PA2KSEG1(U32 addr) ++{ ++ return ((U32)(((U32)addr) | 0xa0000000)); ++} ++U32 MsOS_VA2PA(U32 addr) ++{ ++ return ((U32)(((U32)addr) & 0x1fffffff)); ++} ++ ++void HAL_HWI2C_ExtraDelay(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetIOMapBase ++/// @brief \b Function \b Description: Dump bdma all register ++/// @param \b None : ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_SetIOMapBase(U8 u8Port, U32 u32Base,U32 u32ChipBase,U32 u32ClkBase) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ _gMIO_MapBase[u8Port] = u32Base; ++ _gMChipIO_MapBase = u32ChipBase; ++ _gMClkIO_MapBase = u32ClkBase; ++ ++ HWI2C_HAL_INFO(" _gMIO_MapBase[%d]: %x \n", u8Port, u32Base); ++ HWI2C_HAL_INFO(" _gMChipIO_MapBase: %x\n", u32ChipBase); ++ HWI2C_HAL_INFO(" _gMClkIO_MapBase: %x \n", u32ClkBase); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U8 ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_ReadByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr,(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U16 ++//////////////////////////////////////////////////////////////////////////////// ++U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x\n", _gMIO_MapBase[u8Port], u32RegAddr); ++ return (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Read4Byte ++/// @brief \b Function \b Description: read 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b None : ++/// @param \b U32 ++//////////////////////////////////////////////////////////////////////////////// ++U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return (HAL_HWI2C_Read2Byte(u32RegAddr) | HAL_HWI2C_Read2Byte(u32RegAddr+2) << 16); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByte ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x, u8Val:%2x\n", _gMIO_MapBase[u8Port], u32RegAddr, u8Val); ++ ++ //((volatile U8*)(_gMIO_MapBase[u8Port]))[(u32RegAddr << 1) - (u32RegAddr & 1)] = u8Val; ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write2Byte ++/// @brief \b Function \b Description: write 2 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u16Val : 2 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u32RegAddr&(~0xFF), &u8Port)) ++ return FALSE; ++ u32RegAddr &= 0xFF; ++ ++// HWI2C_HAL_INFO("HWI2C IOMap base:%16lx u32RegAddr:%4x\n", _gMIO_MapBase[u8Port], u16Val); ++ HWI2C_HAL_INFO("HWI2C IOMap base:%8x u32RegAddr:%8x u16Val:%4x\n", _gMIO_MapBase[u8Port], u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMIO_MapBase[u8Port]+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Write4Byte ++/// @brief \b Function \b Description: write 4 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u32Val : 4 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ HAL_HWI2C_Write2Byte(u32RegAddr, u32Val & 0x0000FFFF); ++ HAL_HWI2C_Write2Byte(u32RegAddr+2, u32Val >> 16); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteRegBit ++/// @brief \b Function \b Description: write 1 Byte data ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable) ++{ ++ U8 u8Val = 0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = HAL_HWI2C_ReadByte(u32RegAddr); ++ u8Val = (bEnable) ? (u8Val | u8Mask) : (u8Val & ~u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ HWI2C_HAL_INFO("read back u32RegAddr:%x\n", HAL_HWI2C_ReadByte(u32RegAddr)); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_WriteByteMask ++/// @brief \b Function \b Description: write data with mask bits ++/// @param \b u32RegAddr: register address ++/// @param \b u8Val : 1 byte data ++/// @param \b u8Mask : mask bits ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ u8Val = (HAL_HWI2C_ReadByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++ ++U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr) ++{ ++ U16 u16value; ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr,(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ ++ u16value = (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++ HWI2C_HAL_INFO("u16value===:%4x\n", u16value); ++ return ((u32RegAddr & 0xFF) % 2)? HIBYTE(u16value) : LOWBYTE(u16value); ++} ++ ++BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val) ++{ ++ U16 u16value; ++ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ if((u32RegAddr & 0xFF) % 2) ++ { ++ u16value = (((U16)u8Val) << 8)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF); ++ } ++ else ++ { ++ u16value = ((U16)u8Val)|((*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) & 0xFF00); ++ } ++ ++ (*(volatile U32*)(_gMChipIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16value; ++ return TRUE; ++} ++ ++BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask) ++{ ++ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap chipbase:%8x u32RegAddr:%8x\n", _gMChipIO_MapBase, u32RegAddr); ++ ++ u8Val = (HAL_HWI2C_ReadChipByte(u32RegAddr) & ~u8Mask) | (u8Val & u8Mask); ++ HAL_HWI2C_WriteChipByte(u32RegAddr, u8Val); ++ return TRUE; ++} ++ ++U16 HAL_HWI2C_ReadClk2Byte(U32 u32RegAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ return (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_HWI2C_WriteClk2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x u32RegAddr:%4x\n", _gMClkIO_MapBase, u32RegAddr, u16Val); ++ ++ (*(volatile U32*)(_gMClkIO_MapBase+((u32RegAddr & 0xFFFFFF00) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++BOOL HAL_HWI2C_WriteClkByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ HWI2C_HAL_FUNC(); ++ HWI2C_HAL_INFO("HWI2C IOMap clkbase:%8x u32RegAddr:%8x\n", _gMClkIO_MapBase, u32RegAddr); ++ ++ u16Val = (HAL_HWI2C_ReadClk2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ HAL_HWI2C_WriteClk2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++//##################### ++// ++// MIIC STD Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnINT ++/// @brief \b Function \b Description: Enable Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_INT, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnDMA ++/// @brief \b Function \b Description: Enable DMA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnDMA(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ //pr_err("[%s] u16PortOffset: %#x, bEnable: %#x \n", __func__, u16PortOffset, bEnable); ++ //if(u16PortOffset == 0x100) ++ // bEnable = FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_DMA, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnClkStretch ++/// @brief \b Function \b Description: Enable Clock Stretch ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnClkStretch(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_CLKSTR, bEnable); ++} ++ ++#if 0//RFU ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnTimeoutINT ++/// @brief \b Function \b Description: Enable Timeout Interrupt ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnTimeoutINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_TMTINT, bEnable); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnFilter ++/// @brief \b Function \b Description: Enable Filter ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnFilter(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_FILTER, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_EnPushSda ++/// @brief \b Function \b Description: Enable push current for SDA ++/// @param \b bEnable : TRUE: Enable, FALSE: Disable ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_EnPushSda(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_EN_PUSH1T, bEnable); ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// Static or Internal use ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetINT ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b bEnable : TRUE: enable INT, FALSE: disable INT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetINT(U16 u16PortOffset, BOOL bEnable) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_INTEN, bEnable); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Reset ++/// @brief \b Function \b Description: Reset HWI2C DMA ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_MiuReset ++/// @brief \b Function \b Description: Reset HWI2C DMA MIU ++/// @param \b bReset : TRUE: Not Reset FALSE: Reset ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_MiuReset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIURST, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuPri ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Priority ++/// @param \b eMiuPri : E_HAL_HWI2C_DMA_PRI_LOW, E_HAL_HWI2C_DMA_PRI_HIGH ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuPri(U16 u16PortOffset, HAL_HWI2C_DMA_MIUPRI eMiuPri) ++{ ++ BOOL bHighPri; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuPri>=E_HAL_HWI2C_DMA_PRI_MAX) ++ return FALSE; ++ bHighPri = (eMiuPri==E_HAL_HWI2C_DMA_PRI_HIGH)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CFG+u16PortOffset, _DMA_CFG_MIUPRI, bHighPri); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuAddr ++/// @brief \b Function \b Description: Set HWI2C DMA MIU Address ++/// @param \b u32MiuAddr : MIU Address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuAddr(U16 u16PortOffset, U32 u32MiuAddr) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_u32DmaPhyAddr[u8Port] = u32MiuAddr; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_MIU_ADR+u16PortOffset, Chip_Phys_to_MIU(u32MiuAddr)); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Trigger ++/// @brief \b Function \b Description: Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_Trigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL_TRIG+u16PortOffset, _DMA_CTL_TRIG, TRUE); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReTrigger ++/// @brief \b Function \b Description: Re-Trigger HWI2C DMA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_ReTrigger(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RETRIG, TRUE); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrStop ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b bEnable : TRUE: with STOP, FALSE: without STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrStop(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bTxNoStop; ++ ++ HWI2C_HAL_FUNC(); ++ bTxNoStop = (bEnable)? FALSE : TRUE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_TXNOSTOP, bTxNoStop); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetReadMode ++/// @brief \b Function \b Description: Control HWI2C DMA Transfer Format with or w/o STOP ++/// @param \b eReadMode : E_HAL_HWI2C_DMA_READ_NOSTOP, E_HAL_HWI2C_DMA_READ_STOP ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetReadMode(U16 u16PortOffset, HAL_HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_HAL_FUNC(); ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, FALSE); ++ else ++ if(eReadMode==E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ return HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset, TRUE); ++ else ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetRdWrt ++/// @brief \b Function \b Description: Control HWI2C DMA Read or Write ++/// @param \b bRdWrt : TRUE: read ,FALSE: write ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetRdWrt(U16 u16PortOffset, BOOL bRdWrt) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_RDWTCMD, bRdWrt); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetMiuChannel ++/// @brief \b Function \b Description: Control HWI2C DMA MIU channel ++/// @param \b u8MiuCh : E_HAL_HWI2C_DMA_MIU_CH0 , E_HAL_HWI2C_DMA_MIU_CH1 ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetMiuChannel(U16 u16PortOffset, HAL_HWI2C_DMA_MIUCH eMiuCh) ++{ ++ BOOL bMiuCh1; ++ ++ HWI2C_HAL_FUNC(); ++ if(eMiuCh>=E_HAL_HWI2C_DMA_MIU_MAX) ++ return FALSE; ++ bMiuCh1 = (eMiuCh==E_HAL_HWI2C_DMA_MIU_CH1)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_CTL+u16PortOffset, _DMA_CTL_MIUCHSEL, bMiuCh1); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_TxfrDone ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_TxfrDone(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_TXR+u16PortOffset, _DMA_TXR_DONE, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_IsTxfrDone ++/// @brief \b Function \b Description: Check HWI2C DMA Tx done or not ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: DMA TX Done, FALSE: DMA TX Not Done ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_IsTxfrDone(U16 u16PortOffset, U8 u8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ //########################## ++ // ++ // [Note] : IMPORTANT !!! ++ // Need to put some delay here, ++ // Otherwise, reading data will fail ++ // ++ //########################## ++ if(u8Port>=HAL_HWI2C_PORTS) ++ return FALSE; ++ HAL_HWI2C_ExtraDelay(g_u16DmaDelayFactor[u8Port]); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_DMA_TXR+u16PortOffset) & _DMA_TXR_DONE) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetTxfrCmd ++/// @brief \b Function \b Description: Set Transfer HWI2C DMA Command & Length ++/// @param \b pu8CmdBuf : data pointer ++/// @param \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE: cmd len in range, FALSE: cmd len out of range ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetTxfrCmd(U16 u16PortOffset, U8 u8CmdLen, U8* pu8CmdBuf) ++{ ++ U8 k,u8CmdData; ++ U32 u32RegAdr; ++ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ for( k=0 ; (k \b u8CmdLen : command length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetCmdLen(U16 u16PortOffset, U8 u8CmdLen) ++{ ++ HWI2C_HAL_FUNC(); ++ if(u8CmdLen>HWI2C_DMA_CMD_DATA_LEN) ++ return FALSE; ++ HAL_HWI2C_WriteByte(REG_HWI2C_DMA_CMDLEN+u16PortOffset, u8CmdLen&_DMA_CMDLEN_MSK); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetDataLen ++/// @brief \b Function \b Description: Set HWI2C DMA data length ++/// @param \b u32DataLen : data length ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetDataLen(U16 u16PortOffset, U32 u32DataLen) ++{ ++ U32 u32DataLenSet; ++ ++ HWI2C_HAL_FUNC(); ++ u32DataLenSet = u32DataLen; ++ return HAL_HWI2C_Write4Byte(REG_HWI2C_DMA_DATLEN+u16PortOffset, u32DataLenSet); ++} ++ ++#if 0 //will be used later ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetTxfrCnt ++/// @brief \b Function \b Description: Get MIIC DMA Transfer Count ++/// @param \b u32TxfrCnt : transfer count ++/// @param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++static U32 HAL_HWI2C_DMA_GetTxfrCnt(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_Read4Byte(REG_HWI2C_DMA_TXFRCNT+u16PortOffset); ++} ++#endif ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_GetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b None : ++/// @param \b None : ++/// @param \b E_HAL_HWI2C_DMA_ADDR_10BIT(10 bits mode), ++/// \b E_HAL_HWI2C_DMA_ADDR_NORMAL(7 bits mode) ++//////////////////////////////////////////////////////////////////////////////// ++static HAL_HWI2C_DMA_ADDRMODE HAL_HWI2C_DMA_GetAddrMode(U16 u16PortOffset) ++{ ++ HAL_HWI2C_DMA_ADDRMODE eAddrMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_DMA_SLVCFG+u16PortOffset) & _DMA_10BIT_MODE) ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_10BIT; ++ else ++ eAddrMode = E_HAL_HWI2C_DMA_ADDR_NORMAL; ++ return eAddrMode; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetSlaveAddr ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address ++/// @param \b u32TxfrCnt : slave device address ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetSlaveAddr(U16 u16PortOffset, U16 u16SlaveAddr) ++{ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_DMA_GetAddrMode(u16PortOffset)==E_HAL_HWI2C_DMA_ADDR_10BIT) ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_10BIT_MSK); ++ else ++ return HAL_HWI2C_Write2Byte(REG_HWI2C_DMA_SLVADR+u16PortOffset, u16SlaveAddr&_DMA_SLVADR_NORML_MSK); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_SetAddrMode ++/// @brief \b Function \b Description: Set MIIC DMA Slave Device Address length mode ++/// @param \b eAddrMode : E_HAL_HWI2C_DMA_ADDR_NORMAL, E_HAL_HWI2C_DMA_ADDR_10BIT ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++static BOOL HAL_HWI2C_DMA_SetAddrMode(U16 u16PortOffset, HAL_HWI2C_DMA_ADDRMODE eAddrMode) ++{ ++ BOOL b10BitMode; ++ ++ HWI2C_HAL_FUNC(); ++ if(eAddrMode>=E_HAL_HWI2C_DMA_ADDR_MAX) ++ return FALSE; ++ b10BitMode = (eAddrMode==E_HAL_HWI2C_DMA_ADDR_10BIT)? TRUE : FALSE; ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_DMA_SLVCFG+u16PortOffset, _DMA_10BIT_MODE, b10BitMode); ++} ++ ++static BOOL HAL_HWI2C_DMA_SetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8SrcData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ //memcpy((void*)pMiuData,(void*)pu8SrcData,u32Length); ++ ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy(pMiuData,pu8SrcData,u32Length); ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_GetMiuData(U16 u16PortOffset, U32 u32Length, U8* pu8DstData) ++{ ++ U32 u32PhyAddr = 0; ++ U8 *pMiuData = 0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ //u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ //pMiuData = (U8*)_PA2VA((U32)u32PhyAddr); ++ u32PhyAddr = g_u32DmaPhyAddr[u8Port]; ++ pMiuData = HWI2C_DMA[u8Port].i2c_virt_addr; ++ memcpy((void*)pu8DstData,(void*)pMiuData,u32Length); ++ return TRUE; ++} ++ ++static BOOL HAL_HWI2C_DMA_WaitDone(U16 u16PortOffset, U8 u8ReadWrite) ++{ ++ U16 volatile u16Timeout = HWI2C_DMA_WAIT_TIMEOUT; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //################ ++ // ++ // IMPORTANT HERE !!! ++ // ++ //################ ++ //MsOS_FlushMemory(); ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ ++ ++ //get port index for delay factor ++ if(FALSE == HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ HWI2C_HAL_ERR("[DMA]: Get Port Idx By Offset Error!\n"); ++ return FALSE; ++ } ++ //clear transfer dine first for savfty ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //set command : 0 for Write, 1 for Read ++ HAL_HWI2C_DMA_SetRdWrt(u16PortOffset,u8ReadWrite); ++ //issue write trigger ++ HAL_HWI2C_DMA_Trigger(u16PortOffset); ++ //check transfer done ++ while(u16Timeout--) ++ { ++ if(HAL_HWI2C_DMA_IsTxfrDone(u16PortOffset,u8Port)) ++ { ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ HWI2C_HAL_INFO("[DMA]: Transfer DONE!\n"); ++ if(HAL_HWI2C_Get_SendAck(u16PortOffset)){ ++ return TRUE; ++ } else { ++ return FALSE; ++ } ++ } ++ } ++ HWI2C_HAL_ERR("[DMA]: Transfer NOT Completely!\n"); ++ return FALSE; ++} ++ ++static BOOL HAL_HWI2C_DMA_SetDelayFactor(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ { ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ switch(eClkSel)//use Xtal = 24M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ g_u16DmaDelayFactor[u8Port]=1; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ g_u16DmaDelayFactor[u8Port]=2; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ g_u16DmaDelayFactor[u8Port]=3; break; ++ default: ++ g_u16DmaDelayFactor[u8Port]=5; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC STD Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_Chip ++/// @brief \b Function \b Description: Init HWI2C chip ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Init_Chip(void) ++{ ++ BOOL bRet = TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ //not set all pads (except SPI) as input ++ //bRet &= HAL_HWI2C_WriteRegBit(CHIP_REG_ALLPADIN, CHIP_ALLPAD_IN, FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_IsMaster ++/// @brief \b Function \b Description: Check if Master I2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Master, FALSE: Slave ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_IsMaster(void) ++{ ++ HWI2C_HAL_FUNC(); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Master_Enable ++/// @brief \b Function \b Description: Master I2C enable ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset) ++{ ++ U8 u8Port=0; ++ BOOL bRet = TRUE; ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ ++ //(1) clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ //(2) reset standard master iic ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ //(3) configuration ++ HAL_HWI2C_EnINT(u16PortOffset,TRUE); ++ HAL_HWI2C_EnClkStretch(u16PortOffset,TRUE); ++ HAL_HWI2C_EnFilter(u16PortOffset,TRUE); ++ HAL_HWI2C_EnPushSda(u16PortOffset,TRUE); ++ #if 0 ++ HAL_HWI2C_EnTimeoutINT(u16PortOffset,TRUE); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x100); ++ #endif ++ //(4) Disable DMA ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ //bRet = HAL_HWI2C_DMA_Enable(u16PortOffset,FALSE); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetPortRegOffset ++/// @brief \b Function \b Description: Set HWI2C port register offset ++/// @param \b ePort : HWI2C port number ++/// @param \b pu16Offset : port register offset ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u8Port==HAL_HWI2C_PORT0) ++ {//port 0 : bank register address 0x111800 ++ *pu16Offset = (U16)0x00; ++ } ++ else if(u8Port==HAL_HWI2C_PORT1) ++ {//port 1 : bank register address 0x111900 ++ *pu16Offset = (U16)0x100; ++ } ++ else ++ { ++ *pu16Offset = (U16)0x00; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByRegOffset ++/// @brief \b Function \b Description: Get HWI2C port index by register offset ++/// @param \b u16Offset : port register offset ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if(u16Offset==(U16)0x00) ++ {//port 0 : bank register address 0x11800 ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if(u16Offset==(U16)0x100) ++ {//port 1 : bank register address 0x11900 ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if(u16Offset==(U16)0x200) ++ {//port 2 : bank register address 0x11A00 ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if(u16Offset==(U16)0x300) ++ {//port 3 : bank register address 0x11B00 ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetPortIdxByPort ++/// @brief \b Function \b Description: Get HWI2C port index by port number ++/// @param \b ePort : port number ++/// @param \b pu8Port : port index ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ if((ePort>=E_HAL_HWI2C_PORT0_0)&&(ePort<=E_HAL_HWI2C_PORT0_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT1_0)&&(ePort<=E_HAL_HWI2C_PORT1_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT1; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT2_0)&&(ePort<=E_HAL_HWI2C_PORT2_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT2; ++ } ++ else if((ePort>=E_HAL_HWI2C_PORT3_0)&&(ePort<=E_HAL_HWI2C_PORT3_7)) ++ { ++ *pu8Port = HAL_HWI2C_PORT3; ++ } ++ else ++ { ++ *pu8Port = HAL_HWI2C_PORT0; ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SelectPort ++/// @brief \b Function \b Description: Select HWI2C port ++/// @param \b None : HWI2C port ++/// @param param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort) ++{ ++ U8 u8Value1=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(ePort==E_HAL_HWI2C_PORT0_0) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_1) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_2) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT0_3) ++ { ++ u8Value1 = CHIP_MIIC0_PAD_3; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC0, u8Value1, CHIP_MIIC0_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_0) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_0; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_1) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_1; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else if(ePort==E_HAL_HWI2C_PORT1_2) ++ { ++ u8Value1 = CHIP_MIIC1_PAD_2; ++ HAL_HWI2C_WriteChipByteMask(CHIP_REG_HWI2C_MIIC1, u8Value1, CHIP_MIIC1_PAD_MSK); ++ } ++ else ++ { ++ HWI2C_HAL_ERR("[%s]: Port(%d) not support\n", __func__, ePort); ++ return FALSE; ++ } ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SetClk ++/// @brief \b Function \b Description: Set I2C clock ++/// @param \b u8Clk: clock rate ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel) ++{ ++ U16 u16ClkHCnt=0,u16ClkLCnt=0; ++ U16 u16StpCnt=0,u16SdaCnt=0,u16SttCnt=0,u16LchCnt=0; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(eClkSel>=E_HAL_HWI2C_CLKSEL_NOSUP) ++ return FALSE; ++ ++ switch(eClkSel)//use Xtal = 12M Hz ++ { ++ case E_HAL_HWI2C_CLKSEL_HIGH: // 400 KHz ++ u16ClkHCnt = 9; u16ClkLCnt = 13; break; ++ case E_HAL_HWI2C_CLKSEL_NORMAL: //300 KHz ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ case E_HAL_HWI2C_CLKSEL_SLOW: //200 KHz ++ u16ClkHCnt = 25; u16ClkLCnt = 27; break; ++ case E_HAL_HWI2C_CLKSEL_VSLOW: //100 KHz ++ u16ClkHCnt = 55; u16ClkLCnt = 57; break; ++ case E_HAL_HWI2C_CLKSEL_USLOW: //50 KHz ++ u16ClkHCnt = 115; u16ClkLCnt = 117; break; ++ case E_HAL_HWI2C_CLKSEL_UVSLOW: //25 KHz ++ u16ClkHCnt = 235; u16ClkLCnt = 237; break; ++ default: ++ u16ClkHCnt = 15; u16ClkLCnt = 17; break; ++ } ++ u16SttCnt=38; u16StpCnt=38; u16SdaCnt=5; u16LchCnt=5; ++ ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKH_CNT+u16PortOffset, u16ClkHCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_CKL_CNT+u16PortOffset, u16ClkLCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STP_CNT+u16PortOffset, u16StpCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_SDA_CNT+u16PortOffset, u16SdaCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_STT_CNT+u16PortOffset, u16SttCnt); ++ HAL_HWI2C_Write2Byte(REG_HWI2C_LTH_CNT+u16PortOffset, u16LchCnt); ++ //HAL_HWI2C_Write2Byte(REG_HWI2C_TMT_CNT+u16PortOffset, 0x0000); ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Start ++/// @brief \b Function \b Description: Send start condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Start(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //reset I2C ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_START+u16PortOffset, _CMD_START, TRUE); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ //udelay(5); ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Stop ++/// @brief \b Function \b Description: Send Stop condition ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Stop(U16 u16PortOffset) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //udelay(5); ++ HAL_HWI2C_WriteRegBit(REG_HWI2C_CMD_STOP+u16PortOffset, _CMD_STOP, TRUE); ++ while((!HAL_HWI2C_Is_Idle(u16PortOffset))&&(!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ return (u16Count)? TRUE:FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_ReadRdy ++/// @brief \b Function \b Description: Start byte reading ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset) ++{ ++ U8 u8Value=0; ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ u8Value = (g_bLastByte[u8Port])? (_RDATA_CFG_TRIG|_RDATA_CFG_ACKBIT) : (_RDATA_CFG_TRIG); ++ g_bLastByte[u8Port] = FALSE; ++ return HAL_HWI2C_WriteByte(REG_HWI2C_RDATA_CFG+u16PortOffset, u8Value); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_SendData ++/// @brief \b Function \b Description: Send 1 byte data to SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteByte(REG_HWI2C_WDATA+u16PortOffset, u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_RecvData ++/// @brief \b Function \b Description: Receive 1 byte data from SDA ++/// @param \b None : ++/// @param \b None : ++/// @param \b U8 : ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_RecvData(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_ReadByte(REG_HWI2C_RDATA+u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Get_SendAck ++/// @brief \b Function \b Description: Get ack after sending data ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE: Valid ack, FALSE: No ack ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_WDATA_GET+u16PortOffset) & _WDATA_GET_ACKBIT) ? FALSE : TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_NoAck ++/// @brief \b Function \b Description: generate no ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = TRUE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Ack ++/// @brief \b Function \b Description: generate ack pulse ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Ack(U16 u16PortOffset) ++{ ++ U8 u8Port; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)==FALSE) ++ return FALSE; ++ g_bLastByte[u8Port] = FALSE; ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_GetStae ++/// @brief \b Function \b Description: Get i2c Current State ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b HWI2C current status ++//////////////////////////////////////////////////////////////////////////////// ++U8 HAL_HWI2C_GetState(U16 u16PortOffset) ++{ ++ ++ U8 cur_state = HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset) & _CUR_STATE_MSK; ++ HWI2C_HAL_FUNC(); ++ ++ if (cur_state <= 0) // 0: idle ++ return E_HAL_HWI2C_STATE_IDEL; ++ else if (cur_state <= 2) // 1~2:start ++ return E_HAL_HWI2C_STATE_START; ++ else if (cur_state <= 6) // 3~6:write ++ return E_HAL_HWI2C_STATE_WRITE; ++ else if (cur_state <= 10) // 7~10:read ++ return E_HAL_HWI2C_STATE_READ; ++ else if (cur_state <= 11) // 11:interrupt ++ return E_HAL_HWI2C_STATE_INT; ++ else if (cur_state <= 12) // 12:wait ++ return E_HAL_HWI2C_STATE_WAIT; ++ else // 13~15:stop ++ return E_HAL_HWI2C_STATE_STOP; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_Idle ++/// @brief \b Function \b Description: Check if i2c is idle ++/// @param \b u16PortOffset: HWI2C Port Offset ++/// @param \b None ++/// @param \b TRUE : idle, FALSE : not idle ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return ((HAL_HWI2C_GetState(u16PortOffset)==E_HAL_HWI2C_STATE_IDEL) ? TRUE : FALSE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Is_INT ++/// @brief \b Function \b Description: Check if i2c is interrupted ++/// @param \b u8Status : queried status ++/// @param \b u8Ch: Channel 0/1 ++/// @param \b None ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ return (HAL_HWI2C_ReadByte(REG_HWI2C_INT_CTL+u16PortOffset) & _INT_CTL) ? TRUE : FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Clear_INT ++/// @brief \b Function \b Description: Enable interrupt for HWI2C ++/// @param \b None : ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset) ++{ ++ HWI2C_HAL_FUNC(); ++ ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_INT_CTL+u16PortOffset, _INT_CTL, TRUE); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Reset ++/// @brief \b Function \b Description: Reset HWI2C state machine ++/// @param \b bReset : TRUE: Reset FALSE: Not reset ++/// @param \b None : ++/// @param \b TRUE: Ok, FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ HWI2C_HAL_FUNC(); ++ return HAL_HWI2C_WriteRegBit(REG_HWI2C_MIIC_CFG+u16PortOffset, _MIIC_CFG_RESET, bReset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Send_Byte ++/// @brief \b Function \b Description: Send one byte ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ U8 u8Retry = HWI2C_HAL_RETRY_TIMES; ++ U32 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ //HWI2C_HAL_ERR("Send byte 0x%X !\n", u8Data); ++ ++ while(u8Retry--) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_SendData(u16PortOffset,u8Data)) ++ { ++ u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ while(u16Count--) ++ { ++ if (HAL_HWI2C_Is_INT(u16PortOffset)) ++ { ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (HAL_HWI2C_Get_SendAck(u16PortOffset)) ++ { ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ //break; ++ } ++ } ++ } ++ //pr_err("REG_HWI2C_INT_STATUS %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_INT_STATUS+u16PortOffset)); ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ //MDrv_GPIO_Set_High(72); ++ // check if in Idle state ++ if(HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)==0) ++ { ++ //pr_err("## START bit"); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } else { ++ //pr_err("REG_HWI2C_CUR_STATE %#x\n", HAL_HWI2C_ReadByte(REG_HWI2C_CUR_STATE+u16PortOffset)); ++ HAL_HWI2C_Stop(u16PortOffset); ++ udelay(2); ++ // reset I2C IP ++ HAL_HWI2C_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_Reset(u16PortOffset,FALSE); ++ udelay(2); ++ HAL_HWI2C_Start(u16PortOffset); ++ udelay(2); ++ } ++ //MDrv_GPIO_Set_Low(72); ++ } ++ //HWI2C_HAL_ERR("Send byte 0x%X fail!\n", u8Data); ++ return FALSE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Recv_Byte ++/// @brief \b Function \b Description: Init HWI2C driver and auto generate ACK ++/// @param *pData \b Out: received data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ U16 u16Count = HWI2C_HAL_WAIT_TIMEOUT; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pData) ++ return FALSE; ++ ++ HAL_HWI2C_ReadRdy(u16PortOffset); ++ while((!HAL_HWI2C_Is_INT(u16PortOffset))&&(u16Count > 0)) ++ u16Count--; ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ if (u16Count) ++ { ++ //get data before clear int and stop ++ *pData = HAL_HWI2C_RecvData(u16PortOffset); ++ HWI2C_HAL_INFO("Recv byte =%x\n",*pData); ++ //clear interrupt ++ HAL_HWI2C_Clear_INT(u16PortOffset); ++ #if 1 ++ HAL_HWI2C_ExtraDelay(1); ++ #else ++ MsOS_DelayTaskUs(1); ++ #endif ++ return TRUE; ++ } ++ HWI2C_HAL_INFO("Recv byte fail!\n"); ++ return FALSE; ++} ++ ++//##################### ++// ++// MIIC DMA Related Functions ++// External ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Enable ++/// @brief \b Function \b Description: Enable HWI2C DMA ++/// @param \b bEnable : TRUE: enable DMA, FALSE: disable DMA ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ bRet &= HAL_HWI2C_DMA_SetINT(u16PortOffset,bEnable); ++ bRet &= HAL_HWI2C_EnDMA(u16PortOffset,bEnable); ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_Init ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b pstCfg : Init structure ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg) ++{ ++ U8 u8Port = 0; ++ BOOL bRet=TRUE; ++ ++ HWI2C_HAL_FUNC(); ++ ++ //check pointer ++ if(!pstPortCfg) ++ { ++ HWI2C_HAL_ERR("Port cfg null pointer!\n"); ++ return FALSE; ++ } ++ //(1) clear interrupt ++ HAL_HWI2C_DMA_TxfrDone(u16PortOffset); ++ //(2) reset DMA ++ //(2-1) reset DMA engine ++ HAL_HWI2C_DMA_Reset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_Reset(u16PortOffset,FALSE); ++ //(2-2) reset MIU module in DMA engine ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,TRUE); ++ HAL_HWI2C_DMA_MiuReset(u16PortOffset,FALSE); ++ //(3) default configursation ++ bRet &= HAL_HWI2C_DMA_SetAddrMode(u16PortOffset,pstPortCfg->eDmaAddrMode); ++ bRet &= HAL_HWI2C_DMA_SetMiuPri(u16PortOffset,pstPortCfg->eDmaMiuPri); ++ bRet &= HAL_HWI2C_DMA_SetMiuChannel(u16PortOffset,pstPortCfg->eDmaMiuCh); ++ bRet &= HAL_HWI2C_DMA_SetMiuAddr(u16PortOffset,pstPortCfg->u32DmaPhyAddr); ++ bRet &= HAL_HWI2C_DMA_Enable(u16PortOffset,pstPortCfg->bDmaEnable); ++ bRet &= HAL_HWI2C_DMA_SetDelayFactor(u16PortOffset,pstPortCfg->eSpeed); ++ //(4) backup configuration info ++ if(HAL_HWI2C_GetPortIdxByOffset(u16PortOffset,&u8Port)) ++ { ++ memcpy(&g_stPortCfg[u8Port], pstPortCfg, sizeof(HAL_HWI2C_PortCfg)); ++ } ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_WriteBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: No data for writing!\n"); ++ return FALSE; ++ } ++ ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command if length 0 , cmd buffer will not be used ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ //set data to dram ++ if(HAL_HWI2C_DMA_SetMiuData(u16PortOffset,0,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_W]: Set MIU data error!\n"); ++ return FALSE; ++ } ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ //HWI2C_HAL_ERR("[DMA_W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_DMA_ReadBytes ++/// @brief \b Function \b Description: Initialize HWI2C DMA ++/// @param \b u16SlaveCfg : slave id ++/// @param \b uAddrCnt : address size in bytes ++/// @param \b pRegAddr : address pointer ++/// @param \b uSize : data size in bytes ++/// @param \b pData : data pointer ++/// @param \b None : ++/// @param \b TRUE : ok, FALSE : fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveAddr = LOW_BYTE(u16SlaveCfg)>>1; ++ U8 u8Port = HIGH_BYTE(u16SlaveCfg); ++ HAL_HWI2C_ReadMode eReadMode; ++ ++ HWI2C_HAL_FUNC(); ++ ++ if (!pRegAddr) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Null address!\n"); ++ return FALSE; ++ } ++ if (!pData) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: No data for reading!\n"); ++ return FALSE; ++ } ++ if (u8Port>=HAL_HWI2C_PORTS) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Port failure!\n"); ++ return FALSE; ++ } ++ ++ eReadMode = g_stPortCfg[u8Port].eReadMode; ++ if(eReadMode>=E_HAL_HWI2C_READ_MODE_MAX) ++ { ++ HWI2C_HAL_ERR("[DMA_R]: Read mode failure!\n"); ++ return FALSE; ++ } ++ ++ if(eReadMode!=E_HAL_HWI2C_READ_MODE_DIRECT) ++ { ++ //set transfer read mode ++ HAL_HWI2C_DMA_SetReadMode(u16PortOffset,eReadMode); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ ++ //################# ++ // Set WRITE command ++ //################# ++ //set command buffer ++ if(HAL_HWI2C_DMA_SetTxfrCmd(u16PortOffset,(U8)uAddrCnt,pRegAddr)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Set command buffer error!\n"); ++ return FALSE; ++ } ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,0); ++ ++ //################## ++ // Trigger to WRITE ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_WRITE)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:W]: Transfer command error!\n"); ++ return FALSE; ++ } ++ } ++ ++ ++ //################# ++ // Set READ command ++ //################# ++ //set transfer with stop ++ HAL_HWI2C_DMA_SetTxfrStop(u16PortOffset,TRUE); ++ //set slave address ++ HAL_HWI2C_DMA_SetSlaveAddr(u16PortOffset,u8SlaveAddr); ++ //set command length to 0 ++ HAL_HWI2C_DMA_SetCmdLen(u16PortOffset,0); ++ //set command length for reading ++ HAL_HWI2C_DMA_SetDataLen(u16PortOffset,uSize); ++ //################## ++ // Trigger to READ ++ if(HAL_HWI2C_DMA_WaitDone(u16PortOffset,HWI2C_DMA_READ)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Transfer command error!\n"); ++ return FALSE; ++ } ++ //get data to dram ++ if(HAL_HWI2C_DMA_GetMiuData(u16PortOffset,uSize,pData)==FALSE) ++ { ++ HWI2C_HAL_ERR("[DMA_R:R]: Get MIU data error!\n"); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++ ++//##################### ++// ++// MIIC Miscellaneous Functions ++// ++//##################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: HAL_HWI2C_Init_ExtraProc ++/// @brief \b Function \b Description: Do extral procedure after initialization ++/// @param \b None : ++/// @param param \b None : ++/// @param \b None : ++//////////////////////////////////////////////////////////////////////////////// ++void HAL_HWI2C_Init_ExtraProc(void) ++{ ++ HWI2C_HAL_FUNC(); ++ //Extra procedure TODO ++} ++#endif +diff --git a/drivers/mstar/i2c/infinity3/mhal_iic.h b/drivers/mstar/i2c/infinity3/mhal_iic.h +new file mode 100644 +index 00000000..d62d20f4 +--- /dev/null ++++ b/drivers/mstar/i2c/infinity3/mhal_iic.h +@@ -0,0 +1,283 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_HWI2C_H_ ++#define _HAL_HWI2C_H_ ++ ++#ifdef _HAL_IIC_C_ ++#define _extern_HAL_IIC_ ++#else ++#define _extern_HAL_IIC_ extern ++#endif ++ ++#include ++#include "mdrv_types.h" ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @file halHWI2C.h ++/// @author MStar Semiconductor Inc. ++/// @brief MIIC control functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++//v: value n: shift n bits ++//v: value n: shift n bits ++#define _LShift(v, n) ((v) << (n)) ++#define _RShift(v, n) ((v) >> (n)) ++ ++#define HIGH_BYTE(val) (U8)_RShift((val), 8) ++#define LOW_BYTE(val) ((U8)((val) & 0xFF)) ++ ++#define __BIT(x) ((U8)_LShift(1, x)) ++#define __BIT0 __BIT(0) ++#define __BIT1 __BIT(1) ++#define __BIT2 __BIT(2) ++#define __BIT3 __BIT(3) ++#define __BIT4 __BIT(4) ++#define __BIT5 __BIT(5) ++#define __BIT6 __BIT(6) ++#define __BIT7 __BIT(7) ++#if 0 ++////////////////////////////////////////////////////////////////////////////////////// ++typedef unsigned int BOOL; // 1 byte ++/// data type unsigned char, data length 1 byte ++typedef unsigned char U8; // 1 byte ++/// data type unsigned short, data length 2 byte ++typedef unsigned short U16; // 2 bytes ++/// data type unsigned int, data length 4 byte ++typedef unsigned int U32; // 4 bytes ++/// data type unsigned int64, data length 8 byte ++typedef unsigned long MS_U64; // 8 bytes ++/// data type signed char, data length 1 byte ++typedef signed char MS_S8; // 1 byte ++/// data type signed short, data length 2 byte ++typedef signed short MS_S16; // 2 bytes ++/// data type signed int, data length 4 byte ++typedef signed int MS_S32; // 4 bytes ++/// data type signed int64, data length 8 byte ++typedef signed long MS_S64; // 8 bytes ++///////////////////////////////////////////////////////////////////////////////// ++#endif ++ ++#define HWI2C_SET_RW_BIT(bRead, val) ((bRead) ? ((val) | __BIT0) : ((val) & ~__BIT0)) ++ ++#define HAL_HWI2C_PORTS 4 ++#define HAL_HWI2C_PORT0 0 ++#define HAL_HWI2C_PORT1 1 ++#define HAL_HWI2C_PORT2 2 ++#define HAL_HWI2C_PORT3 3 ++ ++typedef enum _HAL_HWI2C_STATE ++{ ++ E_HAL_HWI2C_STATE_IDEL = 0, ++ E_HAL_HWI2C_STATE_START, ++ E_HAL_HWI2C_STATE_WRITE, ++ E_HAL_HWI2C_STATE_READ, ++ E_HAL_HWI2C_STATE_INT, ++ E_HAL_HWI2C_STATE_WAIT, ++ E_HAL_HWI2C_STATE_STOP ++} HAL_HWI2C_STATE; ++ ++ ++typedef enum _HAL_HWI2C_PORT ++{ ++ E_HAL_HWI2C_PORT0_0 = 0, //disable port 0 ++ E_HAL_HWI2C_PORT0_1, ++ E_HAL_HWI2C_PORT0_2, ++ E_HAL_HWI2C_PORT0_3, ++ E_HAL_HWI2C_PORT0_4, ++ E_HAL_HWI2C_PORT0_5, ++ E_HAL_HWI2C_PORT0_6, ++ E_HAL_HWI2C_PORT0_7, ++ ++ E_HAL_HWI2C_PORT1_0, //disable port 1 ++ E_HAL_HWI2C_PORT1_1, ++ E_HAL_HWI2C_PORT1_2, ++ E_HAL_HWI2C_PORT1_3, ++ E_HAL_HWI2C_PORT1_4, ++ E_HAL_HWI2C_PORT1_5, ++ E_HAL_HWI2C_PORT1_6, ++ E_HAL_HWI2C_PORT1_7, ++ ++ E_HAL_HWI2C_PORT2_0, //disable port 2 ++ E_HAL_HWI2C_PORT2_1, ++ E_HAL_HWI2C_PORT2_2, ++ E_HAL_HWI2C_PORT2_3, ++ E_HAL_HWI2C_PORT2_4, ++ E_HAL_HWI2C_PORT2_5, ++ E_HAL_HWI2C_PORT2_6, ++ E_HAL_HWI2C_PORT2_7, ++ ++ E_HAL_HWI2C_PORT3_0, //disable port 3 ++ E_HAL_HWI2C_PORT3_1, ++ E_HAL_HWI2C_PORT3_2, ++ E_HAL_HWI2C_PORT3_3, ++ E_HAL_HWI2C_PORT3_4, ++ E_HAL_HWI2C_PORT3_5, ++ E_HAL_HWI2C_PORT3_6, ++ E_HAL_HWI2C_PORT3_7, ++ ++ E_HAL_HWI2C_PORT_NOSUP ++}HAL_HWI2C_PORT; ++ ++typedef enum _HAL_HWI2C_CLKSEL ++{ ++ E_HAL_HWI2C_CLKSEL_HIGH = 0, ++ E_HAL_HWI2C_CLKSEL_NORMAL, ++ E_HAL_HWI2C_CLKSEL_SLOW, ++ E_HAL_HWI2C_CLKSEL_VSLOW, ++ E_HAL_HWI2C_CLKSEL_USLOW, ++ E_HAL_HWI2C_CLKSEL_UVSLOW, ++ E_HAL_HWI2C_CLKSEL_NOSUP ++}HAL_HWI2C_CLKSEL; ++ ++typedef enum _HAL_HWI2C_CLK ++{ ++ E_HAL_HWI2C_CLK_DIV4 = 1, //750K@12MHz ++ E_HAL_HWI2C_CLK_DIV8, //375K@12MHz ++ E_HAL_HWI2C_CLK_DIV16, //187.5K@12MHz ++ E_HAL_HWI2C_CLK_DIV32, //93.75K@12MHz ++ E_HAL_HWI2C_CLK_DIV64, //46.875K@12MHz ++ E_HAL_HWI2C_CLK_DIV128, //23.4375K@12MHz ++ E_HAL_HWI2C_CLK_DIV256, //11.71875K@12MHz ++ E_HAL_HWI2C_CLK_DIV512, //5.859375K@12MHz ++ E_HAL_HWI2C_CLK_DIV1024, //2.9296875K@12MHz ++ E_HAL_HWI2C_CLK_NOSUP ++}HAL_HWI2C_CLK; ++ ++typedef enum { ++ E_HAL_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HAL_HWI2C_READ_MODE_MAX ++} HAL_HWI2C_ReadMode; ++ ++typedef enum _HAL_HWI2C_DMA_ADDRMODE ++{ ++ E_HAL_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HAL_HWI2C_DMA_ADDR_10BIT, ++ E_HAL_HWI2C_DMA_ADDR_MAX, ++}HAL_HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HAL_HWI2C_DMA_MIUPRI ++{ ++ E_HAL_HWI2C_DMA_PRI_LOW = 0, ++ E_HAL_HWI2C_DMA_PRI_HIGH, ++ E_HAL_HWI2C_DMA_PRI_MAX, ++}HAL_HWI2C_DMA_MIUPRI; ++ ++typedef enum _HAL_HWI2C_DMA_MIUCH ++{ ++ E_HAL_HWI2C_DMA_MIU_CH0 = 0, ++ E_HAL_HWI2C_DMA_MIU_CH1, ++ E_HAL_HWI2C_DMA_MIU_MAX, ++}HAL_HWI2C_DMA_MIUCH; ++ ++typedef struct _HAL_HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HAL_HWI2C_PinCfg; ++ ++typedef struct _HAL_HWI2C_PortCfg //Synchronize with drvHWI2C.h ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HAL_HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HAL_HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HAL_HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HAL_HWI2C_PORT ePort; /// number ++ HAL_HWI2C_CLKSEL eSpeed; /// clock speed ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HAL_HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HAL_HWI2C_CfgInit //Synchronize with drvHWI2C.h ++{ ++ HAL_HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HAL_HWI2C_PinCfg sI2CPin; /// pin info ++ HAL_HWI2C_CLKSEL eSpeed; /// speed ++ HAL_HWI2C_PORT ePort; /// port ++ HAL_HWI2C_ReadMode eReadMode; /// read mode ++ ++}HAL_HWI2C_CfgInit; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern function ++//////////////////////////////////////////////////////////////////////////////// ++_extern_HAL_IIC_ U32 MsOS_PA2KSEG1(U32 addr); ++_extern_HAL_IIC_ U32 MsOS_VA2PA(U32 addr); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_ExtraDelay(U32 u32Us); ++_extern_HAL_IIC_ void HAL_HWI2C_SetIOMapBase(U8 u8Port,U32 u32Base,U32 u32ChipBase,U32 u32ClkBase); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadByte(U32 u32RegAddr); ++_extern_HAL_IIC_ U16 HAL_HWI2C_Read2Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ U32 HAL_HWI2C_Read4Byte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByte(U32 u32RegAddr, U8 u8Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write2Byte(U32 u32RegAddr, U16 u16Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Write4Byte(U32 u32RegAddr, U32 u32Val); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteRegBit(U32 u32RegAddr, U8 u8Mask, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Init_Chip(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_IsMaster(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Master_Enable(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetPortRegOffset(U8 u8Port, U16* pu16Offset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByOffset(U16 u16Offset, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_GetPortIdxByPort(HAL_HWI2C_PORT ePort, U8* pu8Port); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SelectPort(HAL_HWI2C_PORT ePort); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SetClk(U16 u16PortOffset, HAL_HWI2C_CLKSEL eClkSel); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Start(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Stop(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_ReadRdy(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_SendData(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ U8 HAL_HWI2C_RecvData(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Get_SendAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_NoAck(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Ack(U16 u16PortOffset); ++_extern_HAL_IIC_ U8 HAL_HWI2C_GetState(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_Idle(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Is_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Clear_INT(U16 u16PortOffset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++ ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Init(U16 u16PortOffset, HAL_HWI2C_PortCfg* pstPortCfg); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_Enable(U16 u16PortOffset, BOOL bEnable); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_ReadBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_DMA_WriteBytes(U16 u16PortOffset, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++ ++_extern_HAL_IIC_ void HAL_HWI2C_Init_ExtraProc(void); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByteMask(U32 u32RegAddr, U8 u8Val, U8 u8Mask); ++_extern_HAL_IIC_ U8 HAL_HWI2C_ReadChipByte(U32 u32RegAddr); ++_extern_HAL_IIC_ BOOL HAL_HWI2C_WriteChipByte(U32 u32RegAddr, U8 u8Val); ++ ++ ++#endif //_MHAL_HWI2C_H_ ++ +diff --git a/drivers/mstar/i2c/infinity3/mhal_iic_reg.h b/drivers/mstar/i2c/infinity3/mhal_iic_reg.h +new file mode 100644 +index 00000000..7c92d36b +--- /dev/null ++++ b/drivers/mstar/i2c/infinity3/mhal_iic_reg.h +@@ -0,0 +1,298 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _REG_IIC_H_ ++#define _REG_IIC_H_ ++ ++#define _bit15 0x8000 ++#define _bit14 0x4000 ++#define _bit13 0x2000 ++#define _bit12 0x1000 ++#define _bit11 0x0800 ++#define _bit10 0x0400 ++#define _bit9 0x0200 ++#define _bit8 0x0100 ++#define _bit7 0x0080 ++#define _bit6 0x0040 ++#define _bit5 0x0020 ++#define _bit4 0x0010 ++#define _bit3 0x0008 ++#define _bit2 0x0004 ++#define _bit1 0x0002 ++#define _bit0 0x0001 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Hardware Capability ++//------------------------------------------------------------------------------------------------- ++//#define IIC_UNIT_NUM 2 ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define MHal_IIC_DELAY() { udelay(1000); udelay(1000); udelay(1000); udelay(1000); udelay(1000); }//delay 5ms ++ ++#define REG_IIC_BASE 0xFD223600 // 0xBF200000 + (0x8D80*4) //The 4th port ++ ++#define REG_IIC_CTRL 0x00 ++#define REG_IIC_CLK_SEL 0x01 ++#define REG_IIC_WDATA 0x02 ++#define REG_IIC_RDATA 0x03 ++#define REG_IIC_STATUS 0x04 // reset, clear and status ++#define MHal_IIC_REG(addr) (*(volatile U32*)(REG_IIC_BASE + ((addr)<<2))) ++ ++#define REG_CHIP_BASE 0xFD203C00 ++#define REG_IIC_ALLPADIN 0x50 ++#define REG_IIC_MODE 0x57 ++#define REG_DDCR_GPIO_SEL 0x70 ++#define MHal_CHIP_REG(addr) (*(volatile U32*)(REG_CHIP_BASE + ((addr)<<2))) ++ ++ ++//the definitions of GPIO reg set to initialize ++#define REG_ARM_BASE 0xFD000000//Use 8 bit addressing ++//#define REG_ALL_PAD_IN ((0x0f50<<1) ) //set all pads (except SPI) as input ++#define REG_ALL_PAD_IN (0x101ea1) //set all pads (except SPI) as input ++ ++//the definitions of GPIO reg set to make output ++#define PAD_DDCR_CK 173 ++#define REG_PAD_DDCR_CK_SET (0x101eae) ++#define REG_PAD_DDCR_CK_OEN (0x102b87) ++#define REG_PAD_DDCR_CK_IN (0x102b87) ++#define REG_PAD_DDCR_CK_OUT (0x102b87) ++#define PAD_DDCR_DA 172 ++#define REG_PAD_DDCR_DA_SET (0x101eae) ++#define REG_PAD_DDCR_DA_OEN (0x102b86) ++#define REG_PAD_DDCR_DA_IN (0x102b86) ++#define REG_PAD_DDCR_DA_OUT (0x102b86) ++ ++#define PAD_TGPIO2 181 ++#define REG_PAD_TGPIO2_SET ++#define REG_PAD_TGPIO2_OEN (0x102b8f) ++#define REG_PAD_TGPIO2_IN (0x102b8f) ++#define REG_PAD_TGPIO2_OUT (0x102b8f) ++#define PAD_TGPIO3 182 ++#define REG_PAD_TGPIO3_SET ++#define REG_PAD_TGPIO3_OEN (0x102b90) ++#define REG_PAD_TGPIO3_IN (0x102b90) ++#define REG_PAD_TGPIO3_OUT (0x102b90) ++ ++#define PAD_I2S_OUT_SD1 101 ++#define REG_PAD_I2S_OUT_SD1_SET ++#define REG_PAD_I2S_OUT_SD1_OEN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_IN (0x102b3f) ++#define REG_PAD_I2S_OUT_SD1_OUT (0x102b3f) ++#define PAD_SPDIF_IN 95 ++#define REG_PAD_SPDIF_IN_SET ++#define REG_PAD_SPDIF_IN_OEN (0x102b39) ++#define REG_PAD_SPDIF_IN_IN (0x102b39) ++#define REG_PAD_SPDIF_IN_OUT (0x102b39) ++ ++#define PAD_I2S_IN_WS 92 ++#define REG_PAD_I2S_IN_WS_SET ++#define REG_PAD_I2S_IN_WS_OEN (0x102b36) ++#define REG_PAD_I2S_IN_WS_IN (0x102b36) ++#define REG_PAD_I2S_IN_WS_OUT (0x102b36) ++#define PAD_I2S_IN_BCK 93 ++#define REG_PAD_I2S_IN_BCK_SET ++#define REG_PAD_I2S_IN_BCK_OEN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_IN (0x102b37) ++#define REG_PAD_I2S_IN_BCK_OUT (0x102b37) ++ ++#define PAD_I2S_OUT_SD3 103 ++#define REG_PAD_I2S_OUT_SD3_SET ++#define REG_PAD_I2S_OUT_SD3_OEN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_IN (0x102b41) ++#define REG_PAD_I2S_OUT_SD3_OUT (0x102b41) ++#define PAD_I2S_OUT_SD2 102 ++#define REG_PAD_I2S_OUT_SD2_SET ++#define REG_PAD_I2S_OUT_SD2_OEN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_IN (0x102b40) ++#define REG_PAD_I2S_OUT_SD2_OUT (0x102b40) ++ ++#define PAD_GPIO_PM9 9 ++#define REG_PAD_GPIO_PM9_SET ++#define REG_PAD_GPIO_PM9_OEN (0x0f12) ++#define REG_PAD_GPIO_PM9_IN (0x0f12) ++#define REG_PAD_GPIO_PM9_OUT (0x0f12) ++#define PAD_GPIO_PM8 8 ++#define REG_PAD_GPIO_PM8_SET ++#define REG_PAD_GPIO_PM8_OEN (0x0f10) ++#define REG_PAD_GPIO_PM8_IN (0x0f10) ++#define REG_PAD_GPIO_PM8_OUT (0x0f10) ++ ++#define MHal_GPIO_REG(addr) (*(volatile U8*)(REG_ARM_BASE + (((addr) & ~1)<<1) + (addr & 1))) ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ U32 SclOenReg; ++ U8 SclOenBit; ++ ++ U32 SclOutReg; ++ U8 SclOutBit; ++ ++ U32 SclInReg; ++ U8 SclInBit; ++ ++ U32 SdaOenReg; ++ U8 SdaOenBit; ++ ++ U32 SdaOutReg; ++ U8 SdaOutBit; ++ ++ U32 SdaInReg; ++ U8 SdaInBit; ++ ++ U8 DefDelay; ++}IIC_Bus_t; ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++//############################ ++// ++//IP bank address : for pad mux in chiptop ++// ++//############################ ++#define CHIP_REG_BASE 0//(0x101E00) ++#define CHIP_GPIO1_REG_BASE 0//(0x101A00) ++ ++//for port 0 ++#define CHIP_REG_HWI2C_MIIC0 (CHIP_GPIO1_REG_BASE+ (0x09*2)) ++ #define CHIP_MIIC0_PAD_0 (0) ++ #define CHIP_MIIC0_PAD_1 (__BIT0) ++ #define CHIP_MIIC0_PAD_2 (__BIT1) ++ #define CHIP_MIIC0_PAD_3 (__BIT0|__BIT1) ++ #define CHIP_MIIC0_PAD_MSK (__BIT0|__BIT1) ++ ++//for port 1 ++#define CHIP_REG_HWI2C_MIIC1 (CHIP_REG_BASE+ (0x09*2)) //0x1EDC ++ #define CHIP_MIIC1_PAD_0 (0) ++ #define CHIP_MIIC1_PAD_1 (__BIT4) ++ #define CHIP_MIIC1_PAD_2 (__BIT4) ++ #define CHIP_MIIC1_PAD_3 (__BIT4|__BIT5) ++ #define CHIP_MIIC1_PAD_MSK (__BIT4|__BIT5) ++ ++//for port 2 ++#define CHIP_REG_HWI2C_MIIC2 (CHIP_REG_BASE+ (0x6E*2)) //0x1EDC ++ #define CHIP_MIIC2_PAD_0 (0) ++ #define CHIP_MIIC2_PAD_1 (__BIT2) ++ #define CHIP_MIIC2_PAD_MSK (__BIT2) ++ ++//for port 3 ++#define CHIP_REG_HWI2C_DDCR (CHIP_REG_BASE+ (0x57*2)) //0x1EAE ++ #define CHIP_DDCR_PAD_0 (0) ++ #define CHIP_DDCR_PAD_1 (__BIT1) ++ #define CHIP_DDCR_PAD_MSK (__BIT1|__BIT0) ++ ++//pad mux configuration ++#define CHIP_REG_ALLPADIN (CHIP_REG_BASE+0xA0) ++ #define CHIP_ALLPAD_IN (__BIT0) ++ ++#define CHIP_REG_DDCRMOD (CHIP_REG_BASE+0xAE) ++ ++//############################ ++// ++//IP bank address : for independent port ++// ++//############################ ++//Standard mode ++#define HWI2C_REG_BASE 0//(0x111800) //0x1(11800) + offset ==> default set to port 0 ++#define REG_HWI2C_MIIC_CFG (HWI2C_REG_BASE+0x00*2) ++ #define _MIIC_CFG_RESET (__BIT0) ++ #define _MIIC_CFG_EN_DMA (__BIT1) ++ #define _MIIC_CFG_EN_INT (__BIT2) ++ #define _MIIC_CFG_EN_CLKSTR (__BIT3) ++ #define _MIIC_CFG_EN_TMTINT (__BIT4) ++ #define _MIIC_CFG_EN_FILTER (__BIT5) ++ #define _MIIC_CFG_EN_PUSH1T (__BIT6) ++ #define _MIIC_CFG_RESERVED (__BIT7) ++#define REG_HWI2C_CMD_START (HWI2C_REG_BASE+0x01*2) ++ #define _CMD_START (__BIT0) ++#define REG_HWI2C_CMD_STOP (HWI2C_REG_BASE+0x01*2+1) ++ #define _CMD_STOP (__BIT0) ++#define REG_HWI2C_WDATA (HWI2C_REG_BASE+0x02*2) ++#define REG_HWI2C_WDATA_GET (HWI2C_REG_BASE+0x02*2+1) ++ #define _WDATA_GET_ACKBIT (__BIT0) ++#define REG_HWI2C_RDATA (HWI2C_REG_BASE+0x03*2) ++#define REG_HWI2C_RDATA_CFG (HWI2C_REG_BASE+0x03*2+1) ++ #define _RDATA_CFG_TRIG (__BIT0) ++ #define _RDATA_CFG_ACKBIT (__BIT1) ++#define REG_HWI2C_INT_CTL (HWI2C_REG_BASE+0x04*2) ++ #define _INT_CTL (__BIT0) //write this register to clear int ++#define REG_HWI2C_CUR_STATE (HWI2C_REG_BASE+0x05*2) //For Debug ++ #define _CUR_STATE_MSK (__BIT4|__BIT3|__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_INT_STATUS (HWI2C_REG_BASE+0x05*2+1) //For Debug ++ #define _INT_STARTDET (__BIT0) ++ #define _INT_STOPDET (__BIT1) ++ #define _INT_RXDONE (__BIT2) ++ #define _INT_TXDONE (__BIT3) ++ #define _INT_CLKSTR (__BIT4) ++ #define _INT_SCLERR (__BIT5) ++ #define _INT_TIMEOUT (__BIT6) ++#define REG_HWI2C_STP_CNT (HWI2C_REG_BASE+0x08*2) ++#define REG_HWI2C_CKH_CNT (HWI2C_REG_BASE+0x09*2) ++#define REG_HWI2C_CKL_CNT (HWI2C_REG_BASE+0x0A*2) ++#define REG_HWI2C_SDA_CNT (HWI2C_REG_BASE+0x0B*2) ++#define REG_HWI2C_STT_CNT (HWI2C_REG_BASE+0x0C*2) ++#define REG_HWI2C_LTH_CNT (HWI2C_REG_BASE+0x0D*2) ++#define REG_HWI2C_TMT_CNT (HWI2C_REG_BASE+0x0E*2) ++#define REG_HWI2C_SCLI_DELAY (HWI2C_REG_BASE+0x0F*2) ++ #define _SCLI_DELAY (__BIT2|__BIT1|__BIT0) ++ ++ ++//DMA mode ++#define REG_HWI2C_DMA_CFG (HWI2C_REG_BASE+0x20*2) ++ #define _DMA_CFG_RESET (__BIT1) ++ #define _DMA_CFG_INTEN (__BIT2) ++ #define _DMA_CFG_MIURST (__BIT3) ++ #define _DMA_CFG_MIUPRI (__BIT4) ++#define REG_HWI2C_DMA_MIU_ADR (HWI2C_REG_BASE+0x21*2) // 4 bytes ++#define REG_HWI2C_DMA_CTL (HWI2C_REG_BASE+0x23*2) ++// #define _DMA_CTL_TRIG (__BIT0) ++// #define _DMA_CTL_RETRIG (__BIT1) ++ #define _DMA_CTL_TXNOSTOP (__BIT5) //miic transfer format, 1: S+data..., 0: S+data...+P ++ #define _DMA_CTL_RDWTCMD (__BIT6) //miic transfer format, 1:read, 0:write ++ #define _DMA_CTL_MIUCHSEL (__BIT7) //0: miu0, 1:miu1 ++#define REG_HWI2C_DMA_TXR (HWI2C_REG_BASE+0x24*2) ++ #define _DMA_TXR_DONE (__BIT0) ++#define REG_HWI2C_DMA_CMDDAT0 (HWI2C_REG_BASE+0x25*2) // 8 bytes ++#define REG_HWI2C_DMA_CMDDAT1 (HWI2C_REG_BASE+0x25*2+1) ++#define REG_HWI2C_DMA_CMDDAT2 (HWI2C_REG_BASE+0x26*2) ++#define REG_HWI2C_DMA_CMDDAT3 (HWI2C_REG_BASE+0x26*2+1) ++#define REG_HWI2C_DMA_CMDDAT4 (HWI2C_REG_BASE+0x27*2) ++#define REG_HWI2C_DMA_CMDDAT5 (HWI2C_REG_BASE+0x27*2+1) ++#define REG_HWI2C_DMA_CMDDAT6 (HWI2C_REG_BASE+0x28*2) ++#define REG_HWI2C_DMA_CMDDAT7 (HWI2C_REG_BASE+0x28*2+1) ++#define REG_HWI2C_DMA_CMDLEN (HWI2C_REG_BASE+0x29*2) ++ #define _DMA_CMDLEN_MSK (__BIT2|__BIT1|__BIT0) ++#define REG_HWI2C_DMA_DATLEN (HWI2C_REG_BASE+0x2A*2) // 4 bytes ++#define REG_HWI2C_DMA_TXFRCNT (HWI2C_REG_BASE+0x2C*2) // 4 bytes ++#define REG_HWI2C_DMA_SLVADR (HWI2C_REG_BASE+0x2E*2) ++ #define _DMA_SLVADR_10BIT_MSK 0x3FF //10 bits ++ #define _DMA_SLVADR_NORML_MSK 0x7F //7 bits ++#define REG_HWI2C_DMA_SLVCFG (HWI2C_REG_BASE+0x2E*2+1) ++ #define _DMA_10BIT_MODE (__BIT2) ++#define REG_HWI2C_DMA_CTL_TRIG (HWI2C_REG_BASE+0x2F*2) ++ #define _DMA_CTL_TRIG (__BIT0) ++#define REG_HWI2C_DMA_CTL_RETRIG (HWI2C_REG_BASE+0x2F*2+1) ++ #define _DMA_CTL_RETRIG (__BIT0) ++ ++ ++/**************************&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&**********************************/ ++ ++#endif // _REG_IIC_H_ ++ +diff --git a/drivers/mstar/i2c/ms_iic.c b/drivers/mstar/i2c/ms_iic.c +new file mode 100644 +index 00000000..55e9191d +--- /dev/null ++++ b/drivers/mstar/i2c/ms_iic.c +@@ -0,0 +1,1484 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file mdrv_iic.c ++/// @brief IIC Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include "MsCommon.h" ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include "mst_devid.h" ++#include ++#include ++ ++#include "ms_iic.h" ++#include "mhal_iic_reg.h" ++#include "mhal_iic.h" ++#include "ms_platform.h" ++#define I2C_ACCESS_DUMMY_TIME 5//3 ++///////////////////////////////////////////&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//////////////////////////////////////////////// ++///////////////////////////////////////////&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//////////////////////////////////////////////// ++///////////////////////////////////////////&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&//////////////////////////////////////////////// ++// Local defines & local structures ++//////////////////////////////////////////////////////////////////////////////// ++//define hwi2c ports ++#define HWI2C_PORTS HAL_HWI2C_PORTS ++#define HWI2C_PORT0 HAL_HWI2C_PORT0 ++#define HWI2C_PORT1 HAL_HWI2C_PORT1 ++#define HWI2C_PORT2 HAL_HWI2C_PORT2 ++#define HWI2C_PORT3 HAL_HWI2C_PORT3 ++#define HWI2C_STARTDLY 5 //us ++#define HWI2C_STOPDLY 5 //us ++//define mutex ++static DEFINE_MUTEX(i2cMutex); ++I2C_DMA HWI2C_DMA[HWI2C_PORTM]; ++ ++#define HWI2C_MUTEX_CREATE(_P_) //g_s32HWI2CMutex[_P_] = MsOS_CreateMutex(E_MSOS_FIFO, (char*)gu8HWI2CMutexName[_P_] , MSOS_PROCESS_SHARED) ++#define HWI2C_MUTEX_LOCK(_P_) //OS_OBTAIN_MUTEX(g_s32HWI2CMutex[_P_],MSOS_WAIT_FOREVER) ++#define HWI2C_MUTEX_UNLOCK(_P_) //OS_RELEASE_MUTEX(g_s32HWI2CMutex[_P_]) ++#define HWI2C_MUTEX_DELETE(_P_) //OS_DELETE_MUTEX(g_s32HWI2CMutex[_P_]) ++#define MsOS_DelayTaskUs(x) udelay(x) ++#define MS_DEBUG_MSG(x) x ++ ++//static MS_S32 g_s32HWI2CMutex[HWI2C_PORTM] = {-1,-1,-1,-1}; ++//static char gu8HWI2CMutexName[HWI2C_PORTM][13] = {"HWI2CMUTEXP0","HWI2CMUTEXP1","HWI2CMUTEXP2","HWI2CMUTEXP3"}; ++ ++#if 0 ++#define HWI2C_DBG_FUNC() if (_geDbgLv >= E_HWI2C_DBGLV_ALL) \ ++ {MS_DEBUG_MSG(printk("\t==== %s ====\n", __FUNCTION__);)} ++#define HWI2C_DBG_INFO(x, args...) if (_geDbgLv >= E_HWI2C_DBGLV_INFO ) \ ++ {MS_DEBUG_MSG(printk(x, ##args);)} ++#define HWI2C_DBG_ERR(x, args...) if (_geDbgLv >= E_HWI2C_DBGLV_ERR_ONLY) \ ++ {MS_DEBUG_MSG(printk(x, ##args);)} ++ {MS_DEBUG_MSG(printf(x, ##args);)} ++#else ++#define HWI2C_DBG_FUNC() //printk("\t########################## %s ################################\n", __FUNCTION__) ++#define HWI2C_DBG_INFO(x, args...) //printk(x, ##args) ++#define HWI2C_DBG_ERR(x, args...) printk(x, ##args) ++#endif ++ ++ ++//#define I2C_ACCESS_DUMMY_TIME 50 ++//////////////////////////////////////////////////////////////////////////////// ++// Local & Global Variables ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++struct mstar_i2c_dev { ++ struct device *dev; ++ struct i2c_adapter adapter; ++ struct clk *div_clk; ++ struct clk *fast_clk; ++ struct reset_control *rst; ++ void __iomem *base; ++ void __iomem *chipbase; ++ void __iomem *clkbase; ++ int cont_id; ++ bool irq_disabled; ++ int is_dvc; ++ struct completion msg_complete; ++ int msg_err; ++ u8 *msg_buf; ++ size_t msg_buf_remaining; ++ int msg_read; ++ u32 bus_clk_rate; ++ bool is_suspended; ++ int i2cgroup; ++ int i2cpadmux; ++}; ++ ++static BOOL _gbInit = FALSE; ++//static HWI2C_DbgLv _geDbgLv = E_HWI2C_DBGLV_ERR_ONLY; ++static HWI2C_State _geState = E_HWI2C_IDLE; ++static U32 g_u32StartDelay = HWI2C_STARTDLY, g_u32StopDelay = HWI2C_STOPDLY; ++static HWI2C_ReadMode g_HWI2CReadMode[HWI2C_PORTS]; ++//static HWI2C_PORT g_HWI2CPort[HWI2C_PORTS]; ++static U16 g_u16DelayFactor[HWI2C_PORTS]; ++static BOOL g_bDMAEnable[HWI2C_PORTS]; ++//static U8 g_HWI2CPortIdx = HWI2C_PORT0; ++//////////////////////////////////////////////////////////////////////////////// ++// Local Function ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDrv_HWI2C_Send_Byte HAL_HWI2C_Send_Byte ++#define _MDrv_HWI2C_Recv_Byte HAL_HWI2C_Recv_Byte ++ ++#if 0 ++static void _MDrv_HWI2C_DelayUs(U32 u32Us) ++{ ++ // volatile is necessary to avoid optimization ++ U32 volatile u32Dummy = 0; ++ //U32 u32Loop; ++ U32 volatile u32Loop; ++ ++ u32Loop = (U32)(50 * u32Us); ++ while (u32Loop--) ++ { ++ u32Dummy++; ++ } ++} ++ ++BOOL MDrv_MMIO_GetBASE(U32 *u32Baseaddr, U32 *u32Basesize, U32 u32Module) ++{ ++ ++ return TRUE ; ++} ++#endif ++ ++ ++BOOL MDrv_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data) ++{ ++ return HAL_HWI2C_Send_Byte(u16PortOffset, u8Data); ++} ++ ++BOOL MDrv_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData) ++{ ++ return HAL_HWI2C_Recv_Byte(u16PortOffset, pData); ++} ++ ++ ++BOOL MDrv_HWI2C_NoAck(U16 u16PortOffset) ++{ ++ return HAL_HWI2C_NoAck(u16PortOffset); ++} ++ ++ ++BOOL MDrv_HWI2C_Reset(U16 u16PortOffset, BOOL bReset) ++{ ++ return HAL_HWI2C_Reset(u16PortOffset, bReset); ++} ++ ++ ++BOOL _MDrv_HWI2C_GetPortRegOffset(U8 u8Port, U16 *pu16Offset) ++{ ++ HWI2C_DBG_FUNC(); ++ ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ return HAL_HWI2C_SetPortRegOffset(u8Port,pu16Offset); ++} ++ ++BOOL _MDrv_HWI2C_ReadBytes(U8 u8Port, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveID = LOW_BYTE(u16SlaveCfg); ++ U16 u16Offset = 0x00; ++ U16 u16Dummy = I2C_ACCESS_DUMMY_TIME; // loop dummy ++ BOOL bComplete = FALSE; ++ U32 uAddrCntBkp,uSizeBkp; ++ U8 *pRegAddrBkp,*pDataBkp; ++ ++ HWI2C_DBG_FUNC(); ++ ++ _geState = E_HWI2C_READ_DATA; ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_DBG_ERR("Read bytes error!\n"); ++ return FALSE; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ _geState = E_HWI2C_DMA_READ_DATA; ++ return HAL_HWI2C_DMA_ReadBytes(u16Offset, u16SlaveCfg, uAddrCnt, pRegAddr, uSize, pData); ++ } ++ ++ //start access routines ++ uAddrCntBkp = uAddrCnt; ++ pRegAddrBkp = pRegAddr; ++ uSizeBkp = uSize; ++ pDataBkp = pData; ++ ++ while (u16Dummy--) ++ { ++ if((g_HWI2CReadMode[u8Port]!=E_HWI2C_READ_MODE_DIRECT) && (uAddrCnt>0)&& (pRegAddr)) ++ { ++ HAL_HWI2C_Start(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StartDelay); ++ ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,HWI2C_SET_RW_BIT(FALSE, u8SlaveID))) ++ goto end; ++ ++ while(uAddrCnt--) ++ { ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,*pRegAddr)) ++ goto end; ++ pRegAddr++; ++ } ++ ++ if(g_HWI2CReadMode[u8Port]==E_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START) ++ { ++ HAL_HWI2C_Stop(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StopDelay); ++ } ++ else ++ { ++ HAL_HWI2C_Reset(u16Offset,TRUE); ++ HAL_HWI2C_Reset(u16Offset,FALSE); ++ } ++ } ++ ++ //Very important to add delay to support all clock speeds ++ //Strongly recommend that do not remove this delay routine ++ HAL_HWI2C_ExtraDelay(g_u16DelayFactor[u8Port]); ++ HAL_HWI2C_Start(u16Offset); ++ ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StartDelay); ++ ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,HWI2C_SET_RW_BIT(TRUE, u8SlaveID))) ++ goto end; ++ ++ while(uSize) ++ { ++ /////////////////////////////////// ++ // ++ // must set ACK/NAK before read ready ++ // ++ uSize--; ++ if (uSize==0) ++ HAL_HWI2C_NoAck(u16Offset); ++ if (_MDrv_HWI2C_Recv_Byte(u16Offset,pData)==FALSE) ++ goto end; ++ pData++; ++ } ++ bComplete = TRUE; ++ ++ end: ++ HAL_HWI2C_Stop(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StopDelay); ++ if(u16Dummy&&(bComplete==FALSE)) ++ { ++ uAddrCnt = uAddrCntBkp; ++ pRegAddr = pRegAddrBkp; ++ uSize = uSizeBkp; ++ pData = pDataBkp; ++ continue; ++ } ++ break; ++ } ++ _geState = E_HWI2C_IDLE; ++ HAL_HWI2C_Reset(u16Offset,TRUE); ++ HAL_HWI2C_Reset(u16Offset,FALSE); ++ ++ return bComplete; ++} ++ ++BOOL _MDrv_HWI2C_WriteBytes(U8 u8Port, U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ U8 u8SlaveID = LOW_BYTE(u16SlaveCfg); ++ U16 u16Offset = 0x00; ++ ++ U16 u16Dummy = I2C_ACCESS_DUMMY_TIME; // loop dummy ++ BOOL bComplete = FALSE; ++ U32 uAddrCntBkp,uSizeBkp; ++ U8 *pRegAddrBkp,*pDataBkp; ++ ++ HWI2C_DBG_FUNC(); ++ ++ _geState = E_HWI2C_WRITE_DATA; ++ if (!pRegAddr) ++ uAddrCnt = 0; ++ if (!pData) ++ uSize = 0; ++ ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //no meaning operation ++ if (!uSize) ++ { ++ HWI2C_DBG_ERR("Write bytes error!\n"); ++ return FALSE; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ _geState = E_HWI2C_DMA_WRITE_DATA; ++ return HAL_HWI2C_DMA_WriteBytes(u16Offset, u16SlaveCfg, uAddrCnt, pRegAddr, uSize, pData); ++ } ++ ++ //start access routines ++ uAddrCntBkp = uAddrCnt; ++ pRegAddrBkp = pRegAddr; ++ uSizeBkp = uSize; ++ pDataBkp = pData; ++ while(u16Dummy--) ++ { ++ HAL_HWI2C_Start(u16Offset); ++ MsOS_DelayTaskUs(g_u32StartDelay); ++ ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset,HWI2C_SET_RW_BIT(FALSE, u8SlaveID))) ++ {HWI2C_DBG_ERR("HWI2C_SET_RW_BIT error!\n"); ++ goto end; ++ } ++ while(uAddrCnt) ++ { ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset, *pRegAddr)) ++ {HWI2C_DBG_ERR("pRegAddr error!\n"); ++ goto end; ++ } ++ uAddrCnt--; ++ pRegAddr++; ++ } ++ ++ while(uSize) ++ { ++ if (!_MDrv_HWI2C_Send_Byte(u16Offset, *pData)) ++ {HWI2C_DBG_ERR("pData error!\n"); ++ goto end; ++ } ++ uSize--; ++ pData++; ++ } ++ bComplete = TRUE; ++ ++ end: ++ HAL_HWI2C_Stop(u16Offset); ++ //add extral delay by user configuration ++ MsOS_DelayTaskUs(g_u32StopDelay); ++ if(u16Dummy&&(bComplete==FALSE)) ++ { ++ uAddrCnt = uAddrCntBkp; ++ pRegAddr = pRegAddrBkp; ++ uSize = uSizeBkp; ++ pData = pDataBkp; ++ continue; ++ } ++ break; ++ } ++ _geState = E_HWI2C_IDLE; ++ HAL_HWI2C_Reset(u16Offset,TRUE); ++ HAL_HWI2C_Reset(u16Offset,FALSE); ++ return bComplete; ++} ++ ++static BOOL _MDrv_HWI2C_SelectPort(HWI2C_PORT ePort) ++{ ++ U16 u16Offset = 0x00; ++ U8 u8Port = 0x00; ++ BOOL bRet=TRUE; ++ ++ HWI2C_DBG_FUNC(); ++ ++ //(1) Get port index by port number ++ if(!HAL_HWI2C_GetPortIdxByPort((HAL_HWI2C_PORT)ePort,&u8Port)) ++ return FALSE; ++ ++ //(2) Set pad mux for port number ++ bRet &= HAL_HWI2C_SelectPort((HAL_HWI2C_PORT)ePort); ++ ++ //(3) configure port register offset ==> important ++ bRet &= _MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset); ++ ++ //(4) master init ++ bRet &= HAL_HWI2C_Master_Enable(u16Offset); ++ ++ return bRet; ++} ++ ++static BOOL _MDrv_HWI2C_SetClk(U8 u8Port, HWI2C_CLKSEL eClk) ++{ ++ U16 u16Offset = 0x00; ++ ++ HWI2C_DBG_FUNC(); ++ HWI2C_DBG_INFO("Port%d clk: %u\n", u8Port, eClk); ++ ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //check support clock speed ++ if (eClk >= E_HWI2C_NOSUP) ++ { ++ HWI2C_DBG_ERR("Clock [%u] is not supported!\n",eClk); ++ return FALSE; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ g_u16DelayFactor[u8Port] = (U16)(1<<(eClk)); ++ HWI2C_DBG_INFO("Port%d clk: %u offset:%d\n", u8Port, eClk, u16Offset); ++ ++ return HAL_HWI2C_SetClk(u16Offset,(HAL_HWI2C_CLKSEL)eClk); ++} ++ ++static BOOL _MDrv_HWI2C_SetReadMode(U8 u8Port, HWI2C_ReadMode eReadMode) ++{ ++ HWI2C_DBG_FUNC(); ++ HWI2C_DBG_INFO("Port%d Readmode: %u\n", u8Port, eReadMode); ++ //check support port index ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ if(eReadMode>=E_HWI2C_READ_MODE_MAX) ++ return FALSE; ++ g_HWI2CReadMode[u8Port] = eReadMode; ++ return TRUE; ++} ++ ++static BOOL _MDrv_HWI2C_InitPort(HWI2C_UnitCfg *psCfg) ++{ ++ U8 u8PortIdx = 0, u8Port = 0; ++ U16 u16Offset = 0x00; ++ BOOL bRet = TRUE; ++ HWI2C_PortCfg stPortCfg; ++ ++ HWI2C_DBG_FUNC(); ++ ++ //(1) set default value for port variables ++ for(u8PortIdx=0; u8PortIdx < HWI2C_PORTS; u8PortIdx++) ++ { ++ stPortCfg = psCfg->sCfgPort[u8PortIdx]; ++ if(stPortCfg.bEnable) ++ { ++ if(HAL_HWI2C_GetPortIdxByPort(stPortCfg.ePort,&u8Port) && _MDrv_HWI2C_SelectPort(stPortCfg.ePort)) ++ { ++ //set clock speed ++ bRet &= _MDrv_HWI2C_SetClk(u8Port, stPortCfg.eSpeed); ++ //set read mode ++ bRet &= _MDrv_HWI2C_SetReadMode(u8Port, stPortCfg.eReadMode); ++ //get port index ++ bRet &= _MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset); ++ //master init ++ bRet &= HAL_HWI2C_Master_Enable(u16Offset); ++ //dma init ++ bRet &= HAL_HWI2C_DMA_Init(u16Offset,(HAL_HWI2C_PortCfg*)&stPortCfg); ++ g_bDMAEnable[u8Port] = stPortCfg.bDmaEnable; ++ //dump port information ++ pr_debug("Port:%u Index=%u\n",u8Port,stPortCfg.ePort); ++ pr_debug("Enable=%u\n",stPortCfg.bEnable); ++ pr_debug("DmaReadMode:%u\n",stPortCfg.eReadMode); ++ pr_debug("Speed:%u\n",stPortCfg.eSpeed); ++ pr_debug("DmaEnable:%u\n",stPortCfg.bDmaEnable); ++ pr_debug("DmaAddrMode:%u\n",stPortCfg.eDmaAddrMode); ++ pr_debug("DmaMiuCh:%u\n",stPortCfg.eDmaMiuCh); ++ pr_debug("DmaMiuPri:%u\n",stPortCfg.eDmaMiuPri); ++ pr_debug("DmaPhyAddr:%x\n",stPortCfg.u32DmaPhyAddr); ++ } ++ } ++ } ++ ++ //(2) check initialized port : override above port configuration ++ if(HAL_HWI2C_GetPortIdxByPort(psCfg->ePort,&u8Port) && _MDrv_HWI2C_SelectPort(psCfg->ePort)) ++ { ++ //set clock speed ++ bRet &=_MDrv_HWI2C_SetClk(u8Port,psCfg->eSpeed); ++ //set read mode ++ bRet &=_MDrv_HWI2C_SetReadMode(u8Port,psCfg->eReadMode); ++ //get port index ++ //configure port register offset ==> important ++ bRet &= _MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset); ++ //master init ++ bRet &= HAL_HWI2C_Master_Enable(u16Offset); ++ } ++ ++ //(3) dump allocated port information ++ /*for(u8PortIdx=0; u8PortIdx < HWI2C_PORTS; u8PortIdx++) ++ { ++ HWI2C_DBG_INFO("HWI2C Allocated Port[%d] = 0x%02X\n",u8PortIdx,g_HWI2CPort[u8PortIdx]); ++ }*/ ++ ++ return bRet; ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Global Functions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_Init ++/// @brief \b Function \b Description: Init HWI2C driver ++/// @param psCfg \b IN: hw I2C config ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_Init(HWI2C_UnitCfg *psCfg) ++{ ++ BOOL bRet = TRUE; ++ U8 u8Port=0; ++ ++ HWI2C_DBG_FUNC(); ++ ++ HAL_HWI2C_SetIOMapBase(psCfg->eGroup,psCfg->eBaseAddr,psCfg->eChipAddr,psCfg->eClkAddr); ++ ++ //(2) Initialize pad mux and basic settings ++ pr_debug("Pinreg:%x bit:%u enable:%u speed:%u\n",psCfg->sI2CPin.u32Reg, psCfg->sI2CPin.u8BitPos, psCfg->sI2CPin.bEnable,psCfg->eSpeed); ++ bRet &= HAL_HWI2C_Init_Chip(); ++ //(3) Initialize all port ++ bRet &= _MDrv_HWI2C_InitPort(psCfg); ++ //(4) Check final result ++ if (!bRet) ++ { ++ HWI2C_DBG_ERR("I2C init fail!\n"); ++ } ++ ++ //(5) Extra procedure to do after initialization ++ HAL_HWI2C_Init_ExtraProc(); ++ ++ g_u32StartDelay = HWI2C_STARTDLY; ++ g_u32StopDelay = HWI2C_STOPDLY; ++ pr_debug("START default delay %d(us)\n",(int)g_u32StartDelay); ++ pr_debug("STOP default delay %d(us)\n",(int)g_u32StopDelay); ++ _gbInit = TRUE; ++ ++ pr_debug("HWI2C_MUTEX_CREATE!\n"); ++ for(u8Port=0;u8Port<(U8)HWI2C_PORTS;u8Port++) ++ { ++ HWI2C_MUTEX_CREATE(u8Port); ++ } ++ pr_debug("HWI2C(%d): initialized\n", psCfg->eGroup); ++ return bRet; ++} ++ ++void MDrv_HW_IIC_Init(void *base,void *chipbase,int i2cgroup,void *clkbase, int i2cpadmux) ++{ ++ HWI2C_UnitCfg pHwbuscfg[1]; ++ U8 j; ++ ++ memset(pHwbuscfg, 0, sizeof(HWI2C_UnitCfg)); ++ ++ ++ HWI2C_DMA[i2cgroup].i2c_virt_addr = dma_alloc_coherent(NULL, 4096, &HWI2C_DMA[i2cgroup].i2c_dma_addr, GFP_KERNEL); ++ //We only initialze sCfgPort[0] ++ for(j = 0 ; j < 1 ; j++) ++ { ++ pHwbuscfg[0].sCfgPort[j].bEnable = TRUE; ++ //use default pad mode 1 ++ if(i2cgroup==0) ++ { ++ if(i2cpadmux == 1) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_1; ++ if(i2cpadmux == 2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_2; ++ if(i2cpadmux == 3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT0_3; ++ }else if(i2cgroup==1) { ++ if(i2cpadmux == 1) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_1; ++ if(i2cpadmux == 2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_2; ++ if(i2cpadmux == 3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT1_3; ++ }else if(i2cgroup==2) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT2_1; ++ else if(i2cgroup==3) ++ pHwbuscfg[0].sCfgPort[j].ePort = E_HAL_HWI2C_PORT3_1; ++ pHwbuscfg[0].sCfgPort[j].eSpeed= E_HWI2C_NORMAL; //E_HAL_HWI2C_CLKSEL_VSLOW;//pIIC_Param->u8ClockIIC;// ++ pHwbuscfg[0].sCfgPort[j].eReadMode = E_HWI2C_READ_MODE_DIRECT;//pIIC_Param->u8IICReadMode;// ++ if(i2cgroup==0) ++ pHwbuscfg[0].sCfgPort[j].bDmaEnable = FALSE; //Use default setting ++ else ++ pHwbuscfg[0].sCfgPort[j].bDmaEnable = TRUE; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].eDmaAddrMode = E_HWI2C_DMA_ADDR_NORMAL; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].eDmaMiuPri = E_HWI2C_DMA_PRI_LOW; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].eDmaMiuCh = E_HWI2C_DMA_MIU_CH0; //Use default setting ++ pHwbuscfg[0].sCfgPort[j].u32DmaPhyAddr = HWI2C_DMA[i2cgroup].i2c_dma_addr; //Use default setting ++ j++; ++ } ++ ++ pHwbuscfg[0].sI2CPin.bEnable = FALSE; ++ pHwbuscfg[0].sI2CPin.u8BitPos = 0; ++ pHwbuscfg[0].sI2CPin.u32Reg = 0; ++ pHwbuscfg[0].eSpeed = E_HWI2C_NORMAL; //E_HAL_HWI2C_CLKSEL_VSLOW;//pIIC_Param->u8ClockIIC;// ++ pHwbuscfg[0].ePort = pHwbuscfg[0].sCfgPort[0].ePort; /// port ++ pHwbuscfg[0].eReadMode = E_HWI2C_READ_MODE_DIRECT; //pIIC_Param->u8IICReadMode;// ++ pHwbuscfg[0].eBaseAddr=(U32)base; ++ pHwbuscfg[0].eChipAddr=(U32)chipbase; ++ pHwbuscfg[0].eClkAddr=(U32)clkbase; ++ pHwbuscfg[0].eGroup=i2cgroup; ++ ++ MDrv_HWI2C_Init(&pHwbuscfg[0]); ++} ++EXPORT_SYMBOL(MDrv_HW_IIC_Init); ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_Start ++/// @brief \b Function \b Description: send start bit ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_Start(U16 u16PortOffset) ++{ ++ HWI2C_DBG_FUNC(); ++ return HAL_HWI2C_Start(u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_Stop ++/// @brief \b Function \b Description: send stop bit ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_Stop(U16 u16PortOffset) ++{ ++ HWI2C_DBG_FUNC(); ++ return HAL_HWI2C_Stop(u16PortOffset); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_GetPortIndex ++/// @brief \b Function \b Description: Get port index from port number ++/// @param ePort \b IN: port number ++/// @param ePort \b OUT: pointer to port index ++/// @return \b U8: Port Index ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_GetPortIndex(HWI2C_PORT ePort, U8* pu8Port) ++{ ++ BOOL bRet=TRUE; ++ ++ HWI2C_DBG_FUNC(); ++ ++ //(1) Get port index by port number ++ bRet &= HAL_HWI2C_GetPortIdxByPort((HAL_HWI2C_PORT)ePort, pu8Port); ++ HWI2C_DBG_INFO("ePort:0x%02X, u8Port:0x%02X\n",(U8)ePort,(U8)*pu8Port); ++ ++ return bRet; ++} ++ ++//################### ++// ++// Multi-Port Support: Port 0 ++// ++//################### ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_SelectPort ++/// @brief \b Function \b Description: Decide port index and pad mux for port number ++/// @param ePort \b IN: port number ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_SelectPort(HWI2C_PORT ePort) ++{ ++ HWI2C_DBG_FUNC(); ++ if(ePort >= E_HWI2C_PORT_NOSUP) ++ return FALSE; ++ return _MDrv_HWI2C_SelectPort(ePort); ++} ++#if 0 ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_SetClk ++/// @brief \b Function \b Description: Set HW I2C clock ++/// @param eClk \b IN: clock rate ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_SetClk(HWI2C_CLKSEL eClk) ++{ ++ HWI2C_DBG_FUNC(); ++ return _MDrv_HWI2C_SetClk(g_HWI2CPortIdx, eClk); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_SetReadMode ++/// @brief \b Function \b Description: Set HW I2C Read Mode ++/// @param eClk \b IN: ReadMode ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_SetReadMode(HWI2C_ReadMode eReadMode) ++{ ++ return _MDrv_HWI2C_SetReadMode(g_HWI2CPortIdx, eReadMode); ++} ++#endif ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_ReadByte ++/// @brief \b Function \b Description: read 1 byte data ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param u8RegAddr \b IN: target register address ++/// @param pData \b Out: read 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_ReadByte(U16 u16SlaveCfg, U8 u8RegAddr, U8 *pData) ++{ ++ HWI2C_DBG_FUNC(); ++ return MDrv_HWI2C_ReadBytes(u16SlaveCfg, 1, &u8RegAddr, 1, pData); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_ReadByte ++/// @brief \b Function \b Description: write 1 byte data ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param u8RegAddr \b IN: target register address ++/// @param u8Data \b IN: 1 byte data ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_WriteByte(U16 u16SlaveCfg, U8 u8RegAddr, U8 u8Data) ++{ ++ HWI2C_DBG_FUNC(); ++ return MDrv_HWI2C_WriteBytes(u16SlaveCfg, 1, &u8RegAddr, 1, &u8Data); ++} ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_WriteBytes ++/// @brief \b Function \b Description: Init HWI2C driver ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param uAddrCnt \b IN: register address count ++/// @param pRegAddr \b IN: pointer to targert register address ++/// @param uSize \b IN: data length ++/// @param pData \b IN: data array ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_WriteBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ BOOL bRet; ++ U8 u8Port; ++ ++ u8Port = HIGH_BYTE(u16SlaveCfg); ++ //u8Port = g_HWI2CPortIdx; ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //HWI2C_MUTEX_LOCK(u8Port); ++ //mutex_lock(&i2cMutex); ++ bRet = _MDrv_HWI2C_WriteBytes(u8Port,u16SlaveCfg,uAddrCnt,pRegAddr,uSize,pData); ++ //HWI2C_MUTEX_UNLOCK(u8Port); ++ //mutex_unlock(&i2cMutex); ++ return bRet; ++} ++EXPORT_SYMBOL(MDrv_HWI2C_WriteBytes); ++ ++//////////////////////////////////////////////////////////////////////////////// ++/// @brief \b Function \b Name: MDrv_HWI2C_ReadBytes ++/// @brief \b Function \b Description: Init HWI2C driver ++/// @param u16SlaveCfg \b IN: [15:8]: Channel number [7:0]:Slave ID ++/// @param uAddrCnt \b IN: register address count ++/// @param pRegAddr \b IN: pointer to targert register address ++/// @param uSize \b IN: data length ++/// @param pData \b Out: read data aray ++/// @return \b TRUE: Success FALSE: Fail ++//////////////////////////////////////////////////////////////////////////////// ++BOOL MDrv_HWI2C_ReadBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData) ++{ ++ BOOL bRet; ++ U8 u8Port; ++ ++ u8Port = HIGH_BYTE(u16SlaveCfg); ++ //u8Port = g_HWI2CPortIdx; ++ if(u8Port>=HWI2C_PORTS) ++ { ++ HWI2C_DBG_ERR("Port index is %d >= max supported ports %d !\n", u8Port, HWI2C_PORTS); ++ return FALSE; ++ } ++ //HWI2C_MUTEX_LOCK(u8Port); ++ //mutex_lock(&i2cMutex); ++ bRet = _MDrv_HWI2C_ReadBytes(u8Port,u16SlaveCfg,uAddrCnt,pRegAddr,uSize,pData); ++ //HWI2C_MUTEX_UNLOCK(u8Port); ++ //mutex_unlock(&i2cMutex); ++ return bRet; ++} ++EXPORT_SYMBOL(MDrv_HWI2C_ReadBytes); ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_xfer_read +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function is called by ms_i2c_xfer, ++| used to read data from i2c bus ++| 1. send start ++| 2. send address + R (read bit), and wait ack ++| 3. just set start_byte_read, ++| loop ++| 4. wait interrupt is arised, then clear interrupt and read byte in ++| 5. Auto generate NACK by IP, ++| 6. the master does not acknowledge the final byte it receives. ++| This tells the slave that its transmission is done ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pmsg | x | | pass in the slave id (addr) and R/W flag ++|--------------------+---+---+------------------------------------------------- ++| pbuf | x | | the message buffer, the buffer used to fill ++| | | | data readed ++|--------------------+---+---+------------------------------------------------- ++| length | x | | the byte to be readed from slave +++------------------------------------------------------------------------------ ++*/ ++char errBuf[4096]; ++char *perrBuf; ++ ++static int ++ms_i2c_xfer_read(u8 u8Port, struct i2c_msg *pmsg, u8 *pbuf, int length) ++{ ++ BOOL ret = FALSE; ++ u32 u32i = 0; ++ U16 u16Offset = 0x00; ++ ++ if (NULL == pmsg) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_read: pmsg is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ if (NULL == pbuf) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_read: pbuf is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ //pr_err("I2C read DMA: port = %#x\n", u8Port); ++ ret = MDrv_HWI2C_ReadBytes((u8Port<< 8)|(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)), length, pbuf, length, pbuf); ++ if(ret==FALSE) ++ { ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_read: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ return -ETIMEDOUT; ++ } else { ++ return 0; ++ } ++ } ++ /* ***** 1. Send start bit ***** */ ++ if(!MDrv_HWI2C_Start(u16Offset)) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_read: Send Start error \r\n"); ++ return -ETIMEDOUT; ++ ++ } ++ // Delay for 1 SCL cycle 10us -> 4000T ++ udelay(2); ++ //LOOP_DELAY(8000); //20us ++ ++ /* ***** 2. Send slave id + read bit ***** */ ++ if (!MDrv_HWI2C_Send_Byte(u16Offset, ((pmsg->addr & I2C_BYTE_MASK) << 1) | ++ ((pmsg->flags & I2C_M_RD) ? 1 : 0))) ++ { ++ ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_read: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ ++ return -ETIMEDOUT; ++ } ++ udelay(1); ++ ++ /* Read data */ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ /* ***** 6. Read byte data from slave ***** */ ++ if ((length-1) == u32i) ++ { ++ MDrv_HWI2C_NoAck(u16Offset); ++ } ++ ret = MDrv_HWI2C_Recv_Byte(u16Offset, pbuf); ++ pbuf++; ++ } ++ ++ return 0; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_xfer_write +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function is called by ms_i2c_xfer ++| used to write data to i2c bus the procedure is as following ++ ++| 1. send start ++| 2. send address, and wait ack and clear interrupt in wait_ack() ++| loop ++| 3. send byte ++| 4. wait interrupt is arised, then clear interrupt ++| and check if recieve ACK ++| ++| RETURN : When the operation is success, it return 0. ++| Otherwise Negative number will be returned. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| pmsg | x | | pass in the slave id (addr) and R/W flag ++|--------------------+---+---+------------------------------------------------- ++| pbuf | x | | the message buffer, the buffer used to fill ++| | | | data readed ++|--------------------+---+---+------------------------------------------------- ++| length | x | | the byte to be writen from slave +++------------------------------------------------------------------------------ ++*/ ++static int ++ms_i2c_xfer_write(u8 u8Port, struct i2c_msg *pmsg, u8 *pbuf, int length) ++{ ++ u32 u32i = 0; ++ U16 u16Offset = 0x00; ++ int ret = FALSE; ++ ++ if (NULL == pmsg) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_write: pmsg is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ if (NULL == pbuf) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_write: pbuf is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(u8Port,&u16Offset)) ++ { ++ HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ if(g_bDMAEnable[u8Port]) ++ { ++ //pr_err("I2C write DMA: port = %#x\n", u8Port); ++ ret = MDrv_HWI2C_WriteBytes((u8Port<< 8)|(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)), length, pbuf, length, pbuf); ++ if(ret==FALSE) ++ { ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_write: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ return -ETIMEDOUT; ++ }else{ ++ return 0; ++ } ++ } ++ ++ ++ /* ***** 1. Send start bit ***** */ ++ if(!MDrv_HWI2C_Start(u16Offset)) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer_write: Send Start error \r\n"); ++ return -ETIMEDOUT; ++ } ++ // Delay for 1 SCL cycle 10us -> 4000T ++ //LOOP_DELAY(8000); //20us ++ udelay(2); ++ ++ /* ***** 2. Send slave id + read bit ***** */ ++ if (!MDrv_HWI2C_Send_Byte(u16Offset, ((pmsg->addr & I2C_BYTE_MASK) << 1) | ++ ((pmsg->flags & I2C_M_RD) ? 1 : 0))) ++ { ++ ++ perrBuf = &errBuf[0]; ++ memset(errBuf,0,4096); ++ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ perrBuf += sprintf(perrBuf,"%#x ", *pbuf); ++ pbuf++; ++ } ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_write: Slave dev NAK, Addr: %#x, Data: %s \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),errBuf); ++ return -ETIMEDOUT; ++ } ++ ++ /* ***** 3. Send register address and data to write ***** */ ++ /* we send register is first buffer */ ++ for (u32i = 0; u32i < length; u32i++) ++ { ++ /* ***** 4. Write high byte data to slave ***** */ ++ if(MDrv_HWI2C_Send_Byte(u16Offset, *pbuf)) ++ { ++ pbuf++; ++ } ++ else ++ { ++ pr_info("ERROR: Bus[%d] in ms_i2c_xfer_write: Slave data NAK, Addr: %#x, Data: %#x \r\n", (u16Offset/256),(((pmsg->addr & I2C_BYTE_MASK) << 1) | ((pmsg->flags & I2C_M_RD) ? 1 : 0)),*pbuf); ++ return -ETIMEDOUT; ++ } ++ } ++ ++ return ret; ++} ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_xfer +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function will be called by i2c-core.c i2c-transfer() ++| i2c_master_send(), and i2c_master_recv() ++| We implement the I2C communication protocol here ++| Generic i2c master transfer entrypoint. ++| ++| RETURN : When the operation is success, it return the number of message ++| requrested. Negative number when error occurs. ++| +++------------------------------------------------------------------------------ ++| Variable Name |IN |OUT| Usage ++|--------------------+---+---+------------------------------------------------- ++| padap | x | | the adaptor which the communication will be ++| | | | procceed ++|--------------------+---+---+------------------------------------------------- ++| pmsg | x | | the message buffer, the buffer with message to ++| | | | be sent or used to fill data readed ++|--------------------+---+---+------------------------------------------------- ++| num | x | | number of message to be transfer +++------------------------------------------------------------------------------ ++*/ ++static int ++ms_i2c_xfer(struct i2c_adapter *padap, struct i2c_msg *pmsg, int num) ++{ ++ int i, err; ++ U16 u16Offset = 0x00; ++ ++ HWI2C_DBG_INFO("ms_i2c_xfer: processing %d messages:\n", num); ++ ++ i = 0; ++ err = 0; ++ ++ if (NULL == padap) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer: adap is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ if (NULL == pmsg) ++ { ++ printk(KERN_INFO ++ "ERROR: in ms_i2c_xfer: pmsg is NULL pointer \r\n"); ++ return -ENOTTY; ++ } ++ ++ //configure port register offset ==> important ++ if(!_MDrv_HWI2C_GetPortRegOffset(padap->nr,&u16Offset)) ++ { ++ HWI2C_DBG_ERR("Port index error!\n"); ++ return FALSE; ++ } ++ ++ mutex_lock(&i2cMutex); ++ MDrv_HWI2C_Reset(u16Offset,TRUE); ++ udelay(1); ++ MDrv_HWI2C_Reset(u16Offset,FALSE); ++ udelay(1); ++ ++/* in i2c-master_send or recv, the num is always 1, */ ++/* but use i2c_transfer() can set multiple message */ ++ ++ for (i = 0; i < num; i++) ++ { ++#if 0 ++ printk(KERN_INFO " #%d: %sing %d byte%s %s 0x%02x\n", i, ++ pmsg->flags & I2C_M_RD ? "read" : "writ", ++ pmsg->len, pmsg->len > 1 ? "s" : "", ++ pmsg->flags & I2C_M_RD ? "from" : "to", pmsg->addr); ++#endif ++ /* do Read/Write */ ++ if (pmsg->len && pmsg->buf) /* sanity check */ ++ { ++ if (pmsg->flags & I2C_M_RD) ++ err = ms_i2c_xfer_read(padap->nr, pmsg, pmsg->buf, pmsg->len); ++ else ++ err = ms_i2c_xfer_write(padap->nr, pmsg, pmsg->buf, pmsg->len); ++ ++ //MDrv_HWI2C_Stop(u16Offset); ++ ++ if (err) ++ { ++ mutex_unlock(&i2cMutex); ++ return err; ++ } ++ } ++ pmsg++; /* next message */ ++ } ++ ++ /* ***** 6. Send stop bit ***** */ ++ /* finish the read/write, then issues the stop condition (P). ++ * for repeat start, diposit stop, two start and one stop only ++ */ ++ MDrv_HWI2C_Stop(u16Offset); ++ mutex_unlock(&i2cMutex); ++ return i; ++} ++ ++ ++/* +++------------------------------------------------------------------------------ ++| FUNCTION : ms_i2c_func +++------------------------------------------------------------------------------ ++| DESCRIPTION : This function is returned list of supported functionality. ++| ++| RETURN : return list of supported functionality ++| ++| Variable : no variable +++------------------------------------------------------------------------------ ++*/ ++static u32 ms_i2c_func(struct i2c_adapter *padapter) ++{ ++ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; ++} ++ ++/* implement the i2c transfer function in algorithm structure */ ++static struct i2c_algorithm sg_ms_i2c_algorithm = ++{ ++ .master_xfer = ms_i2c_xfer, ++ .functionality = ms_i2c_func, ++}; ++ ++/* Match table for of_platform binding */ ++static const struct of_device_id mstar_i2c_of_match[] = { ++ { .compatible = "mstar,i2c", 0}, ++ {}, ++}; ++ ++static int mstar_i2c_probe(struct platform_device *pdev) ++{ ++ struct mstar_i2c_dev *i2c_dev; ++ struct resource *res; ++ void __iomem *base; ++ void __iomem *chipbase; ++ void __iomem *clkbase; ++ struct device_node *node = pdev->dev.of_node; ++ int ret = 0; ++ int i2cgroup = 0; ++ int i2cpadmux = 1; ++ int num_parents, i; ++ struct clk **iic_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ if(num_parents < 0) ++ { ++ printk( "[%s] Fail to get parent count! Error Number : %d\n", __func__, num_parents); ++ return -1; ++ } ++ iic_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ if(!iic_clks) ++ return -ENOMEM; ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(iic_clks[i])) ++ { ++ printk( "[%s] Fail to get clk!\n", __func__); ++ kfree(iic_clks); ++ return -ENOENT; ++ } ++ else ++ { ++ clk_prepare_enable(iic_clks[i]); ++ if(i == 0) ++ clk_set_rate(iic_clks[i], 12000000); ++ } ++ } ++ kfree(iic_clks); ++ ++ HWI2C_DBG_INFO(" mstar_i2c_probe\n"); ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if(!res) ++ return -ENOENT; ++ base = (void *)(IO_ADDRESS(res->start)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if(!res) ++ return -ENOENT; ++ chipbase = (void *)(IO_ADDRESS(res->start)); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ if(!res) ++ return -ENOENT; ++ clkbase = (void *)(IO_ADDRESS(res->start)); ++ ++ i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); ++ if (!i2c_dev) ++ return -ENOMEM; ++ ++ i2c_dev->base = base; ++ i2c_dev->chipbase = chipbase; ++ i2c_dev->adapter.algo = &sg_ms_i2c_algorithm; ++ i2c_dev->cont_id = pdev->id; ++ i2c_dev->dev = &pdev->dev; ++ i2c_dev->clkbase = clkbase; ++ ++ of_property_read_u32(node, "i2c-group", &i2cgroup); ++ //i2cgroup = of_alias_get_id(pdev->dev.of_node, "iic"); ++ HWI2C_DBG_INFO("i2cgroup=%d\n",i2cgroup); ++ i2c_dev->i2cgroup = i2cgroup; ++ ++ of_property_read_u32(node, "i2c-padmux", &i2cpadmux); ++ HWI2C_DBG_INFO("i2cpadmux=%d\n",i2cpadmux); ++ i2c_dev->i2cpadmux = i2cpadmux; ++ ++ if (pdev->dev.of_node) { ++ const struct of_device_id *match; ++ match = of_match_device(mstar_i2c_of_match, &pdev->dev); ++ //i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, ++ // "mstar,cedric-i2c-dvc"); ++ } else if (pdev->id == 3) { ++ i2c_dev->is_dvc = 1; ++ } ++ init_completion(&i2c_dev->msg_complete); ++ ++ platform_set_drvdata(pdev, i2c_dev); ++ ++ MDrv_HW_IIC_Init(i2c_dev->base,i2c_dev->chipbase,i2cgroup,clkbase, i2cpadmux); ++ ++ //i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); ++ i2c_dev->adapter.owner = THIS_MODULE; ++ i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; ++ //strlcpy(i2c_dev->adapter.name, "Mstar I2C adapter", ++ // sizeof(i2c_dev->adapter.name)); ++ scnprintf(i2c_dev->adapter.name, sizeof(i2c_dev->adapter.name), ++ "Mstar I2C adapter %d", i2cgroup); ++ i2c_dev->adapter.algo = &sg_ms_i2c_algorithm; ++ ++ i2c_dev->adapter.dev.parent = &pdev->dev; ++ i2c_dev->adapter.nr = i2cgroup; ++ i2c_dev->adapter.dev.of_node = pdev->dev.of_node; ++ HWI2C_DBG_INFO(" i2c_dev->adapter.nr=%d\n",i2c_dev->adapter.nr); ++ i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); ++ ++ ret = i2c_add_numbered_adapter(&i2c_dev->adapter); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to add I2C adapter\n"); ++ goto out; ++ } ++ ++ return 0; ++ ++out: ++ //clk_unprepare(i2c_dev->div_clk); ++ return ret; ++} ++ ++static int mstar_i2c_remove(struct platform_device *pdev) ++{ ++ struct mstar_i2c_dev *i2c_dev = platform_get_drvdata(pdev); ++ i2c_del_adapter(&i2c_dev->adapter); ++ return 0; ++} ++ ++#if 0 ++static int mstar_i2c_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct mstar_i2c_dev *i2c_dev = platform_get_drvdata(pdev); ++ ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **iic_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ iic_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ //disable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(iic_clks[i])) ++ { ++ printk( "[iic_clks] Fail to get clk!\n" ); ++ kfree(iic_clks); ++ return -1; ++ } ++ else ++ { ++ clk_disable_unprepare(iic_clks[i]); ++ } ++ } ++ kfree(iic_clks); ++#endif ++ ++ i2c_lock_adapter(&i2c_dev->adapter); ++ i2c_dev->is_suspended = true; ++ i2c_unlock_adapter(&i2c_dev->adapter); ++ ++ return 0; ++} ++ ++static int mstar_i2c_resume(struct platform_device *pdev) ++{ ++ struct mstar_i2c_dev *i2c_dev = platform_get_drvdata(pdev); ++ ++ //int ret; ++#if defined(CONFIG_OF) ++ int num_parents, i; ++ struct clk **iic_clks; ++ ++ num_parents = of_clk_get_parent_count(pdev->dev.of_node); ++ iic_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ //enable all clk ++ for(i = 0; i < num_parents; i++) ++ { ++ iic_clks[i] = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(iic_clks[i])) ++ { ++ printk( "[iic_clks] Fail to get clk!\n" ); ++ kfree(iic_clks); ++ return -1; ++ } ++ else ++ { ++ clk_prepare_enable(iic_clks[i]); ++ if(i == 0) ++ clk_set_rate(iic_clks[i], 12000000); ++ } ++ kfree(iic_clks); ++ } ++#endif ++ ++ i2c_lock_adapter(&i2c_dev->adapter); ++ ++ MDrv_HW_IIC_Init(i2c_dev->base,i2c_dev->chipbase,i2c_dev->i2cgroup,i2c_dev->clkbase, i2c_dev->i2cpadmux); ++ ++ i2c_dev->is_suspended = false; ++ ++ i2c_unlock_adapter(&i2c_dev->adapter); ++ ++ return 0; ++} ++#endif ++MODULE_DEVICE_TABLE(of, mstar_i2c_of_match); ++ ++ ++static struct platform_driver mstar_i2c_driver = { ++ .probe = mstar_i2c_probe, ++ .remove = mstar_i2c_remove, ++#if 0 ++ .suspend = mstar_i2c_suspend, ++ .resume = mstar_i2c_resume, ++#endif ++ .driver = { ++ .name = "mstar-i2c", ++ .owner = THIS_MODULE, ++ .of_match_table = mstar_i2c_of_match, ++ }, ++}; ++ ++static int __init mstar_i2c_init_driver(void) ++{ ++ return platform_driver_register(&mstar_i2c_driver); ++} ++ ++static void __exit mstar_i2c_exit_driver(void) ++{ ++ platform_driver_unregister(&mstar_i2c_driver); ++} ++ ++subsys_initcall(mstar_i2c_init_driver); ++module_exit(mstar_i2c_exit_driver); ++ ++MODULE_DESCRIPTION("MStar I2C Bus Controller driver"); ++MODULE_AUTHOR("MSTAR"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/i2c/ms_iic.h b/drivers/mstar/i2c/ms_iic.h +new file mode 100644 +index 00000000..c522eb82 +--- /dev/null ++++ b/drivers/mstar/i2c/ms_iic.h +@@ -0,0 +1,250 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file mdrv_iic.h ++/// @brief IIC Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRV_IIC_H_ ++#define _DRV_IIC_H_ ++ ++#include "ms_types.h" ++ ++#define IIC_NUM_OF_MAX (20) ++#define I2C_BYTE_MASK 0xFF ++ ++#define IIC_NUM_OF_HW (1) ++#define MDRV_NAME_IIC "iic" ++#define MDRV_MAJOR_IIC 0x8a ++#define MDRV_MINOR_IIC 0x00 ++#define HWI2C_PORTM 4 //maximum support ports ++//////////////////////////////////////////////////////////////////////////////// ++// Define & data type ++//////////////////////////////////////////////////////////////////////////////// ++#define MSIF_HWI2C_LIB_CODE {'H','I','2','C'} //Lib code ++#define MSIF_HWI2C_LIBVER {'0','6'} //LIB version ++#define MSIF_HWI2C_BUILDNUM {'0','6'} //Build Number ++#define MSIF_HWI2C_CHANGELIST {'0','0','5','4','9','6','1','5'} //P4 ChangeList Number ++ ++#define HWI2C_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_TAG, /* 'MSIF' */ \ ++ MSIF_CLASS, /* '00' */ \ ++ MSIF_CUS, /* 0x0000 */ \ ++ MSIF_MOD, /* 0x0000 */ \ ++ MSIF_CHIP, \ ++ MSIF_CPU, \ ++ MSIF_HWI2C_LIB_CODE, /* IP__ */ \ ++ MSIF_HWI2C_LIBVER, /* 0.0 ~ Z.Z */ \ ++ MSIF_HWI2C_BUILDNUM, /* 00 ~ 99 */ \ ++ MSIF_HWI2C_CHANGELIST, /* CL# */ \ ++ MSIF_OS ++ ++/// debug level ++typedef enum _HWI2C_DbgLv ++{ ++ E_HWI2C_DBGLV_NONE, /// no debug message ++ E_HWI2C_DBGLV_ERR_ONLY, /// show error only ++ E_HWI2C_DBGLV_INFO, /// show error & informaiton ++ E_HWI2C_DBGLV_ALL /// show error, information & funciton name ++}HWI2C_DbgLv; ++ ++/// I2C select master port ++typedef enum _HWI2C_PORT ++{ ++ E_HWI2C_PORT_0 = 0, /// port 0_0 //disable port 0 ++ E_HWI2C_PORT0_1, /// port 0_1 ++ E_HWI2C_PORT0_2, /// port 0_2 ++ E_HWI2C_PORT0_3, /// port 0_3 ++ E_HWI2C_PORT0_4, /// port 0_4 ++ E_HWI2C_PORT0_5, /// port 0_5 ++ E_HWI2C_PORT0_6, /// port 0_6 ++ E_HWI2C_PORT0_7, /// port 0_7 ++ ++ E_HWI2C_PORT_1 = 8, /// port 1_0 //disable port 1 ++ E_HWI2C_PORT1_1, /// port 1_1 ++ E_HWI2C_PORT1_2, /// port 1_2 ++ E_HWI2C_PORT1_3, /// port 1_3 ++ E_HWI2C_PORT1_4, /// port 1_4 ++ E_HWI2C_PORT1_5, /// port 1_5 ++ E_HWI2C_PORT1_6, /// port 1_6 ++ E_HWI2C_PORT1_7, /// port 1_7 ++ ++ E_HWI2C_PORT_2 = 16,/// port 2_0 //disable port 2 ++ E_HWI2C_PORT2_1, /// port 2_1 ++ E_HWI2C_PORT2_2, /// port 2_2 ++ E_HWI2C_PORT2_3, /// port 2_3 ++ E_HWI2C_PORT2_4, /// port 2_4 ++ E_HWI2C_PORT2_5, /// port 2_5 ++ E_HWI2C_PORT2_6, /// port 2_6 ++ E_HWI2C_PORT2_7, /// port 2_7 ++ ++ E_HWI2C_PORT_3 = 24,/// port 3_0 //disable port 3 ++ E_HWI2C_PORT3_1, /// port 3_1 ++ E_HWI2C_PORT3_2, /// port 3_2 ++ E_HWI2C_PORT3_3, /// port 3_3 ++ E_HWI2C_PORT3_4, /// port 3_4 ++ E_HWI2C_PORT3_5, /// port 3_5 ++ E_HWI2C_PORT3_6, /// port 3_6 ++ E_HWI2C_PORT3_7, /// port 3_7 ++ ++ E_HWI2C_PORT_NOSUP /// non-support port ++}HWI2C_PORT; ++ ++/// I2C clock speed select ++typedef enum _HWI2C_CLKSEL ++{ ++ E_HWI2C_HIGH = 0, /// high speed ++ E_HWI2C_NORMAL, /// normal speed ++ E_HWI2C_SLOW, /// slow speed ++ E_HWI2C_VSLOW, /// very slow ++ E_HWI2C_USLOW, /// ultra slow ++ E_HWI2C_UVSLOW, /// ultra-very slow ++ E_HWI2C_NOSUP /// non-support speed ++}HWI2C_CLKSEL; ++ ++/// I2C state ++typedef enum _HWI2C_State ++{ ++ E_HWI2C_IDLE, /// idle state ++ E_HWI2C_READ_DATA, /// read data state ++ E_HWI2C_WRITE_DATA, /// write data state ++ E_HWI2C_DMA_READ_DATA, /// DMA read data state ++ E_HWI2C_DMA_WRITE_DATA /// DMA write data state ++}HWI2C_State; ++ ++typedef enum { ++ E_HWI2C_READ_MODE_DIRECT, ///< first transmit slave address + reg address and then start receive the data */ ++ E_HWI2C_READ_MODE_DIRECTION_CHANGE, ///< slave address + reg address in write mode, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HWI2C_READ_MODE_DIRECTION_CHANGE_STOP_START, ///< slave address + reg address in write mode + stop, direction change to read mode, repeat start slave address in read mode, data from device ++ E_HWI2C_READ_MODE_MAX ++} HWI2C_ReadMode; ++ ++typedef enum _HWI2C_DMA_ADDRMODE ++{ ++ E_HWI2C_DMA_ADDR_NORMAL = 0, ++ E_HWI2C_DMA_ADDR_10BIT, ++ E_HWI2C_DMA_ADDR_MAX, ++}HWI2C_DMA_ADDRMODE; ++ ++typedef enum _HWI2C_DMA_READMODE ++{ ++ E_HWI2C_DMA_READ_NOSTOP = 0, ++ E_HWI2C_DMA_READ_STOP, ++ E_HWI2C_DMA_READ_MAX, ++}HWI2C_DMA_READMODE; ++ ++typedef enum _HWI2C_DMA_MIUPRI ++{ ++ E_HWI2C_DMA_PRI_LOW = 0, ++ E_HWI2C_DMA_PRI_HIGH, ++ E_HWI2C_DMA_PRI_MAX, ++}HWI2C_DMA_MIUPRI; ++ ++typedef enum _HWI2C_DMA_MIUCH ++{ ++ E_HWI2C_DMA_MIU_CH0 = 0, ++ E_HWI2C_DMA_MIU_CH1, ++ E_HWI2C_DMA_MIU_MAX, ++}HWI2C_DMA_MIUCH; ++ ++/// I2C master pin config ++typedef struct _HWI2C_PinCfg ++{ ++ U32 u32Reg; /// register ++ U8 u8BitPos; /// bit position ++ BOOL bEnable; /// enable or disable ++}HWI2C_PinCfg; ++ ++/// I2C port config ++typedef struct _HWI2C_PortCfg ++{ ++ U32 u32DmaPhyAddr; /// DMA physical address ++ HWI2C_DMA_ADDRMODE eDmaAddrMode; /// DMA address mode ++ HWI2C_DMA_MIUPRI eDmaMiuPri; /// DMA miu priroity ++ HWI2C_DMA_MIUCH eDmaMiuCh; /// DMA miu channel ++ BOOL bDmaEnable; /// DMA enable ++ ++ HWI2C_PORT ePort; /// number ++ HWI2C_CLKSEL eSpeed; /// clock speed ++ HWI2C_ReadMode eReadMode; /// read mode ++ BOOL bEnable; /// enable ++ ++}HWI2C_PortCfg; ++ ++/// I2C Configuration for initialization ++typedef struct _HWI2C_UnitCfg ++{ ++ HWI2C_PortCfg sCfgPort[4]; /// port cfg info ++ HWI2C_PinCfg sI2CPin; /// pin info ++ HWI2C_CLKSEL eSpeed; /// speed ++ HWI2C_PORT ePort; /// port ++ HWI2C_ReadMode eReadMode; /// read mode ++ int eGroup; /// port ++ U32 eBaseAddr; ++ U32 eChipAddr; ++ U32 eClkAddr; ++}HWI2C_UnitCfg; ++ ++/// I2C information ++typedef struct _HWI2C_Info ++{ ++ U32 u32IOMap; /// base address ++ HWI2C_UnitCfg sUnitCfg; /// configuration ++}HWI2C_Info; ++ ++/// I2C status ++typedef struct _HWI2C_Status ++{ ++ U8 u8DbgLevel; /// debug level ++ BOOL bIsInit; /// initialized ++ BOOL bIsMaster; /// master ++ HWI2C_State eState; /// state ++}HWI2C_Status; ++ ++typedef struct _I2C_DMA ++{ ++ dma_addr_t i2c_dma_addr; ++ u8 *i2c_virt_addr; ++}I2C_DMA; ++ ++extern I2C_DMA HWI2C_DMA[HWI2C_PORTM]; ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Extern Function ++//////////////////////////////////////////////////////////////////////////////// ++void MDrv_HW_IIC_Init(void *base,void *chipbase,int i2cgroup,void *clkbase, int i2cpadmux); ++BOOL MDrv_HWI2C_Init(HWI2C_UnitCfg *psCfg); ++BOOL MDrv_HWI2C_WriteBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++BOOL MDrv_HWI2C_ReadBytes(U16 u16SlaveCfg, U32 uAddrCnt, U8 *pRegAddr, U32 uSize, U8 *pData); ++//BOOL MDrv_HWI2C_SetClk(HWI2C_CLKSEL eClk); ++ ++ ++BOOL MDrv_HWI2C_Start(U16 u16PortOffset); ++BOOL MDrv_HWI2C_Stop(U16 u16PortOffset); ++BOOL MDrv_HWI2C_Send_Byte(U16 u16PortOffset, U8 u8Data); ++BOOL MDrv_HWI2C_Recv_Byte(U16 u16PortOffset, U8 *pData); ++BOOL MDrv_HWI2C_NoAck(U16 u16PortOffset); ++BOOL _MDrv_HWI2C_GetPortRegOffset(U8 u8Port, U16 *pu16Offset); ++BOOL MDrv_HWI2C_Reset(U16 u16PortOffset, BOOL bReset); ++ ++ ++ ++#endif // _DRV_IIC_H_ ++ +diff --git a/drivers/mstar/include/_ms_private.h b/drivers/mstar/include/_ms_private.h +new file mode 100644 +index 00000000..beda5f68 +--- /dev/null ++++ b/drivers/mstar/include/_ms_private.h +@@ -0,0 +1,38 @@ ++#ifndef __MS_PRIVATE__ ++#define __MS_PRIVATE__ ++ ++ ++struct ms_chip ++{ ++ void (*chip_flush_miu_pipe)(void); ++ void (*chip_flush_memory)(void); ++ void (*chip_read_memory)(void); ++ int (*cache_outer_is_enabled)(void); ++ void (*cache_flush_all)(void); ++ void (*cache_clean_range_va_pa)(unsigned long, unsigned long,unsigned long); ++ void (*cache_flush_range_va_pa)(unsigned long, unsigned long,unsigned long); ++ void (*cache_clean_range)(unsigned long, unsigned long); ++ void (*cache_flush_range)(unsigned long, unsigned long); ++ void (*cache_invalidate_range)(unsigned long, unsigned long); ++ u64 (*phys_to_miu)(u64); ++ u64 (*miu_to_phys)(u64); ++ ++ int (*chip_get_device_id)(void); ++ char* (*chip_get_platform_name)(void); ++ int (*chip_get_revision)(void); ++ ++ const char* (*chip_get_API_version)(void); ++ ++ int (*chip_get_boot_dev_type)(void); ++ unsigned long long (*chip_get_riu_phys)(void); ++ int (*chip_get_riu_size)(void); ++ int (*chip_get_storage_type)(void); ++ int (*chip_get_package_type)(void); ++ ++ int (*chip_function_set)(int functionId, int param); ++ ++ u64 (*chip_get_us_ticks)(void); ++}; ++ ++ ++#endif +diff --git a/drivers/mstar/include/cedric/gpio.h b/drivers/mstar/include/cedric/gpio.h +new file mode 100644 +index 00000000..f81ebbda +--- /dev/null ++++ b/drivers/mstar/include/cedric/gpio.h +@@ -0,0 +1,187 @@ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_PM_GPIO0 0 ++#define PAD_PM_GPIO1 1 ++#define PAD_PM_IIC_SDA 2 ++#define PAD_PM_IIC_SCL 3 ++#define PAD_PM_MIIC_SDA 4 ++#define PAD_PM_MIIC_SCL 5 ++#define PAD_PM_SPI_CK 6 ++#define PAD_PM_SPI_CZ0 7 ++#define PAD_PM_SPI_GPIO 8 ++#define PAD_PM_SPI_DI 9 ++#define PAD_PM_SPI_DO 10 ++#define PAD_ONOFF 11 ++#define PAD_CHRGDET 12 ++#define PAD_32K_OUT 13 ++#define PAD_IRIN 14 ++#define PAD_CEC 15 ++#define PAD_PM_SD0_CDZ 16 ++#define PAD_PM_SD1_CDZ 17 ++#define PAD_PM_SD2_CDZ 18 ++#define PAD_PM_SD_GPIO 19 ++#define PAD_HOTPLUG 20 ++#define PAD_BATOK 21 ++#define PAD_PMIC_CHIPEN 22 ++#define PAD_PMIC_STDBYN 23 ++#define PAD_PMIC_INT 24 ++#define PAD_SD0_D1 25 ++#define PAD_SD0_D0 26 ++#define PAD_SD0_CLK 27 ++#define PAD_SD0_CMD 28 ++#define PAD_SD0_D3 29 ++#define PAD_SD0_D2 30 ++#define PAD_SD1_D1 31 ++#define PAD_SD1_D0 32 ++#define PAD_SD1_CLK 33 ++#define PAD_SD1_CMD 34 ++#define PAD_SD1_D3 35 ++#define PAD_SD1_D2 36 ++#define PAD_A_GPS_EVENT 37 ++#define PAD_AFE1_SGN 38 ++#define PAD_AFE1_MAG 39 ++#define PAD_RFSPI_CZ1 40 ++#define PAD_AFE0_SGN 41 ++#define PAD_AFE0_MAG 42 ++#define PAD_RFSPI_CLK 43 ++#define PAD_RFSPI_DATA 44 ++#define PAD_RFSPI_CZ0 45 ++#define PAD_BTI_RX_TX 46 ++#define PAD_BTI_DATA1 47 ++#define PAD_BTI_DATA0 48 ++#define PAD_BT_CLK_24M 49 ++#define PAD_BT_SPI_SCLK 50 ++#define PAD_BT_SPI_SDATA 51 ++#define PAD_BT_SPI_SENB 52 ++#define PAD_BT_CHIP_EN 53 ++#define PAD_SR_D0 54 ++#define PAD_SR_D1 55 ++#define PAD_SR_D2 56 ++#define PAD_SR_D3 57 ++#define PAD_SR_D4 58 ++#define PAD_SR_D5 59 ++#define PAD_SR_D6 60 ++#define PAD_SR_D7 61 ++#define PAD_SR_PCLK 62 ++#define PAD_SR_HSYNC 63 ++#define PAD_SR_STROBE 64 ++#define PAD_SR_VSYNC 65 ++#define PAD_SR_RST 66 ++#define PAD_SR_PWRDN 67 ++#define PAD_GPIO33 68 ++#define PAD_GPIO32 69 ++#define PAD_GPIO31 70 ++#define PAD_GPIO30 71 ++#define PAD_GPIO29 72 ++#define PAD_GPIO28 73 ++#define PAD_GPIO27 74 ++#define PAD_GPIO26 75 ++#define PAD_GPIO25 76 ++#define PAD_GPIO24 77 ++#define PAD_UART_RX1 78 ++#define PAD_UART_TX1 79 ++#define PAD_UART_RX2 80 ++#define PAD_UART_TX2 81 ++#define PAD_UART_RX3 82 ++#define PAD_UART_TX3 83 ++#define PAD_UART_RX4 84 ++#define PAD_UART_TX4 85 ++#define PAD_UART_CTS2 86 ++#define PAD_UART_RTS2 87 ++#define PAD_GPIO34 88 ++#define PAD_GPIO35 89 ++#define PAD_GPIO36 90 ++#define PAD_GPIO37 91 ++#define PAD_GPIO38 92 ++#define PAD_MPIF_CS1Z 93 ++#define PAD_MPIF_CS0Z 94 ++#define PAD_MPIF_D0 95 ++#define PAD_MPIF_D1 96 ++#define PAD_MPIF_D2 97 ++#define PAD_MPIF_D3 98 ++#define PAD_MPIF_CK 99 ++#define PAD_MPIF_BUSY 100 ++#define PAD_MIIC0_SDA 101 ++#define PAD_MIIC0_SCL 102 ++#define PAD_GPIO23 103 ++#define PAD_GPIO22 104 ++#define PAD_GPIO21 105 ++#define PAD_GPIO20 106 ++#define PAD_GPIO19 107 ++#define PAD_GPIO18 108 ++#define PAD_GPIO17 109 ++#define PAD_GPIO16 110 ++#define PAD_GPIO15 111 ++#define PAD_GPIO14 112 ++#define PAD_GPIO13 113 ++#define PAD_GPIO12 114 ++#define PAD_GPIO11 115 ++#define PAD_GPIO10 116 ++#define PAD_GPIO9 117 ++#define PAD_GPIO8 118 ++#define PAD_GPIO7 119 ++#define PAD_GPIO6 120 ++#define PAD_GPIO5 121 ++#define PAD_GPIO4 122 ++#define PAD_GPIO3 123 ++#define PAD_GPIO2 124 ++#define PAD_GPIO1 125 ++#define PAD_GPIO0 126 ++#define PAD_TESTPIN 127 ++#define PAD_SPDIF_OUT 128 ++#define PAD_IIS_TRX_BCK 129 ++#define PAD_IIS_TRX_WS 130 ++#define PAD_IIS_TRX_OUT 131 ++#define PAD_IIS_TRX_IN 132 ++#define PAD_UART_RX5 133 ++#define PAD_UART_TX5 134 ++#define PAD_UART_CTS1 135 ++#define PAD_UART_RTS1 136 ++#define PAD_TCON_GPIO8 137 ++#define PAD_TCON_GPIO7 138 ++#define PAD_TCON_GPIO6 139 ++#define PAD_TCON_GPIO5 140 ++#define PAD_TCON_GPIO4 141 ++#define PAD_TCON_GPIO3 142 ++#define PAD_TCON_GPIO2 143 ++#define PAD_TCON_GPIO1 144 ++#define PAD_TCON_GPIO0 145 ++#define PAD_TTL_GPIO11 146 ++#define PAD_TTL_GPIO10 147 ++#define PAD_TTL_GPIO9 148 ++#define PAD_TTL_GPIO8 149 ++#define PAD_TTL_GPIO7 150 ++#define PAD_TTL_GPIO6 151 ++#define PAD_TTL_GPIO5 152 ++#define PAD_TTL_GPIO4 153 ++#define PAD_TTL_GPIO3 154 ++#define PAD_TTL_GPIO2 155 ++#define PAD_TTL_GPIO1 156 ++#define PAD_TTL_GPIO0 157 ++#define PAD_NAND_WPZ 158 ++#define PAD_NAND_WEZ 159 ++#define PAD_NAND_ALE 160 ++#define PAD_NAND_CLE 161 ++#define PAD_NAND_CE3Z 162 ++#define PAD_NAND_CE2Z 163 ++#define PAD_NAND_CE1Z 164 ++#define PAD_NAND_CE0Z 165 ++#define PAD_NAND_REZ 166 ++#define PAD_NAND_RBZ 167 ++#define PAD_NAND_DA0 168 ++#define PAD_NAND_DA1 169 ++#define PAD_NAND_DA2 170 ++#define PAD_NAND_DA3 171 ++#define PAD_NAND_DQS 172 ++#define PAD_NAND_DA4 173 ++#define PAD_NAND_DA5 174 ++#define PAD_NAND_DA6 175 ++#define PAD_NAND_DA7 176 ++#define PAD_SD2_D1 177 ++#define PAD_SD2_D0 178 ++#define PAD_SD2_CLK 179 ++#define PAD_SD2_CMD 180 ++#define PAD_SD2_D3 181 ++#define PAD_SD2_D2 182 ++#endif +diff --git a/drivers/mstar/include/cedric/irqs.h b/drivers/mstar/include/cedric/irqs.h +new file mode 100644 +index 00000000..de02f9b0 +--- /dev/null ++++ b/drivers/mstar/include/cedric/irqs.h +@@ -0,0 +1,204 @@ ++/*------------------------------------------------------------------------------ ++ Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++------------------------------------------------------------------------------*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQ_CEDRIC_H ++#define __IRQ_CEDRIC_H ++ ++/*------------------------------------------------------------------------------ ++ Constant ++-------------------------------------------------------------------------------*/ ++/* ++ * 1. Need to use GIC for the SMP & ARM CA9 global timer & ARM TWD timer ++ * 2. The GIC pins are not connected correctly in Cedric so the irqchip must be implmeneted ++ * 3. Shift the interrupt from 2048 ++ */ ++ ++ ++#define INT_START 2048//to avoid GIC ID ++/* FIQ Definition */ ++#define FIQ_START INT_START ++#define INT_FIQ_TIMER0 (FIQ_START + 0) ++#define INT_FIQ_TIMER1 (FIQ_START + 1) ++#define INT_FIQ_WDT (FIQ_START + 2) ++#define INT_FIQ_TOP1 (FIQ_START + 3) ++#define INT_FIQ_TOP0 (FIQ_START + 4) ++#define INT_FIQ_DUMMY05 (FIQ_START + 5) ++#define INT_FIQ_DUMMY06 (FIQ_START + 6) ++#define INT_FIQ_DUMMY07 (FIQ_START + 7) ++#define INT_FIQ_USB (FIQ_START + 8) ++#define INT_FIQ_UHC (FIQ_START + 9) ++#define INT_FIQ_DUMMY10 (FIQ_START + 10) ++#define INT_FIQ_DUMMY11 (FIQ_START + 11) ++#define INT_FIQ_DUMMY12 (FIQ_START + 12) ++#define INT_FIQ_DUMMY13 (FIQ_START + 13) ++#define INT_FIQ_DUMMY14 (FIQ_START + 14) ++#define INT_FIQ_TSP2AEON (FIQ_START + 15) ++#define INT_FIQ_DUMMY16 (FIQ_START + 16) ++#define INT_FIQ_DUMMY17 (FIQ_START + 17) ++#define INT_FIQ_DUMMY18 (FIQ_START + 18) ++#define INT_FIQ_XIU_TIME_OUT (FIQ_START + 19) ++#define INT_FIQ_DUMMY20 (FIQ_START + 20) ++#define INT_FIQ_VE_F0 (FIQ_START + 21) ++#define INT_FIQ_VE_F1 (FIQ_START + 22) ++#define INT_FIQ_DUMMY23 (FIQ_START + 23) ++#define INT_FIQ_DUMMY24 (FIQ_START + 24) ++#define INT_FIQ_VE_VSYNC_IN (FIQ_START + 25) ++#define INT_FIQ_HDMITX_EDGE (FIQ_START + 26) ++#define INT_FIQ_IR (FIQ_START + 27) ++#define INT_FIQ_AFEC_VSYNC (FIQ_START + 28) ++#define INT_FIQ_DUMMY29 (FIQ_START + 29) ++#define INT_FIQ_DUMMY30 (FIQ_START + 30) ++#define INT_FIQ_AU_SYSTEM_EDGE (FIQ_START + 31) ++#define INT_FIQ_IR_RC (FIQ_START + 32) ++#define INT_FIQ_DUMMY33 (FIQ_START + 33) ++#define INT_FIQ_IR_IN (FIQ_START + 34) ++#define INT_FIQ_DUMMY35 (FIQ_START + 35) ++#define INT_FIQ_HST0TO3 (FIQ_START + 36) ++#define INT_FIQ_HST0TO2 (FIQ_START + 37) ++#define INT_FIQ_HST0TO1 (FIQ_START + 38) ++#define INT_FIQ_EXT_GPIO0 (FIQ_START + 39) ++#define INT_FIQ_HST1TO3 (FIQ_START + 40) ++#define INT_FIQ_HST1TO2 (FIQ_START + 41) ++#define INT_FIQ_HST1TO0 (FIQ_START + 42) ++#define INT_FIQ_EXT_GPIO1 (FIQ_START + 43) ++#define INT_FIQ_HST2TO3 (FIQ_START + 44) ++#define INT_FIQ_HST2TO1 (FIQ_START + 45) ++#define INT_FIQ_HST2TO0 (FIQ_START + 46) ++#define INT_FIQ_EXT_GPIO2 (FIQ_START + 47) ++#define INT_FIQ_HST3TO2 (FIQ_START + 48) ++#define INT_FIQ_HST3TO1 (FIQ_START + 49) ++#define INT_FIQ_HST3TO0 (FIQ_START + 50) ++#define INT_FIQ_USB1 (FIQ_START + 51) ++#define INT_FIQ_UHC1 (FIQ_START + 52) ++#define INT_FIQ_USB2 (FIQ_START + 53) ++#define INT_FIQ_UHC2 (FIQ_START + 54) ++#define INT_FIQ_EXT_GPIO3 (FIQ_START + 55) ++#define INT_FIQ_EXT_GPIO4 (FIQ_START + 56) ++#define INT_FIQ_EXT_GPIO5 (FIQ_START + 57) ++#define INT_FIQ_EXT_GPIO6 (FIQ_START + 58) ++#define INT_FIQ_PWM_RP_L (FIQ_START + 59) ++#define INT_FIQ_PWM_FP_L (FIQ_START + 60) ++#define INT_FIQ_PWM_RP_R (FIQ_START + 61) ++#define INT_FIQ_PWM_FP_R (FIQ_START + 62) ++#define INT_FIQ_EXT_GPIO7 (FIQ_START + 63) ++#define FIQ_END (FIQ_START + 64) ++ ++ ++/* IRQ Definition */ ++#define IRQ_START (FIQ_END) ++#define INT_IRQ_UART0 (IRQ_START + 0) ++#define INT_IRQ_PMU (IRQ_START + 1) ++#define INT_IRQ_ROT (IRQ_START + 2) ++#define INT_IRQ_MVD (IRQ_START + 3) ++#define INT_IRQ_DISP2 (IRQ_START + 4) ++#define INT_IRQ_OTG (IRQ_START + 5) ++#define INT_IRQ_USB (IRQ_START + 6) ++#define INT_IRQ_UHC (IRQ_START + 7) ++#define INT_IRQ_VP6 (IRQ_START + 8) ++#define INT_IRQ_AUDIO_ATOP (IRQ_START + 9) ++#define INT_IRQ_DISP (IRQ_START + 10) ++#define INT_IRQ_SDIO2RIU (IRQ_START + 11) ++#define INT_IRQ_SDIO1_2RIU (IRQ_START + 12) ++#define INT_IRQ_SDIO2_2RIU (IRQ_START + 13) ++#define INT_IRQ_COMB (IRQ_START + 14) ++#define INT_IRQ_ISP (IRQ_START + 15) ++#define INT_IRQ_TSP2HK (IRQ_START + 16) ++#define INT_IRQ_AUX_ADCDONE (IRQ_START + 17) ++#define INT_IRQ_AUX_PENDET (IRQ_START + 18) ++#define INT_IRQ_DC (IRQ_START + 19) ++#define INT_IRQ_GOP (IRQ_START + 20) ++#define INT_IRQ_RTC (IRQ_START + 21) ++#define INT_IRQ_COMBO_WDT (IRQ_START + 22) ++#define INT_IRQ_DIPW (IRQ_START + 23) ++#define INT_IRQ_SAR (IRQ_START + 24) ++#define INT_IRQ_AUX_KEY (IRQ_START + 25) ++#define INT_IRQ_HDMI_TX (IRQ_START + 26) ++#define INT_IRQ_SCM (IRQ_START + 27) ++#define INT_IRQ_VBI (IRQ_START + 28) ++#define INT_IRQ_MVD2MIPS (IRQ_START + 29) ++#define INT_IRQ_GPD (IRQ_START + 30) ++#define INT_IRQ_FCIE (IRQ_START + 31) ++#define INT_IRQ_HVD (IRQ_START + 32) ++#define INT_IRQ_USB1 (IRQ_START + 33) ++#define INT_IRQ_UHC1 (IRQ_START + 34) ++#define INT_IRQ_MIU (IRQ_START + 35) ++#define INT_IRQ_USB2 (IRQ_START + 36) ++#define INT_IRQ_UHC2 (IRQ_START + 37) ++#define INT_IRQ_AEON2HI (IRQ_START + 38) ++#define INT_IRQ_UART1 (IRQ_START + 39) ++#define INT_IRQ_UART2 (IRQ_START + 40) ++#define INT_IRQ_UART3 (IRQ_START + 41) ++#define INT_IRQ_MPIF (IRQ_START + 42) ++#define INT_IRQ_AU_SYSTEM (IRQ_START + 43) ++#define INT_IRQ_DISP1 (IRQ_START + 44) ++#define INT_IRQ_JPD (IRQ_START + 45) ++#define INT_IRQ_ICP (IRQ_START + 46) ++#define INT_IRQ_MFE (IRQ_START + 47) ++#define INT_IRQ_BDMA0 (IRQ_START + 48) ++#define INT_IRQ_BDMA1 (IRQ_START + 49) ++#define INT_IRQ_FUART0 (IRQ_START + 50) ++#define INT_IRQ_URDMA0 (IRQ_START + 51) ++#define INT_IRQ_CMDQ (IRQ_START + 52) ++#define INT_IRQ_G3D2MCU (IRQ_START + 53) ++#define INT_IRQ_CEC (IRQ_START + 54) ++#define INT_IRQ_SSI (IRQ_START + 55) ++#define INT_IRQ_FUART1 (IRQ_START + 56) ++#define INT_IRQ_COMBO_MISC_TIMER (IRQ_START + 57) ++#define INT_IRQ_COMBO_TIMERS (IRQ_START + 58) ++#define INT_IRQ_GE (IRQ_START + 59) ++#define INT_IRQ_IIC1_DMA (IRQ_START + 60) ++#define INT_IRQ_IIC1 (IRQ_START + 61) ++#define INT_IRQ_IIC0_DMA (IRQ_START + 62) ++#define INT_IRQ_IIC0 (IRQ_START + 63) ++#define IRQ_END (IRQ_START + 64) ++ ++#define PMU_START (IRQ_END) ++#define INT_PMU_GPIO00 (PMU_START + 0) ++#define INT_PMU_GPIO01 (PMU_START + 1) ++#define INT_PMU_GPIO02 (PMU_START + 2) ++#define INT_PMU_GPIO03 (PMU_START + 3) ++#define INT_PMU_GPIO04 (PMU_START + 4) ++#define INT_PMU_GPIO05 (PMU_START + 5) ++#define INT_PMU_GPIO06 (PMU_START + 6) ++#define INT_PMU_GPIO07 (PMU_START + 7) ++#define INT_PMU_GPIO08 (PMU_START + 8) ++#define INT_PMU_GPIO09 (PMU_START + 9) ++#define INT_PMU_GPIO10 (PMU_START + 10) ++#define INT_PMU_GPIO11 (PMU_START + 11) ++#define INT_PMU_GPIO12 (PMU_START + 12) ++#define INT_PMU_GPIO13 (PMU_START + 13) ++#define INT_PMU_GPIO14 (PMU_START + 14) ++#define INT_PMU_GPIO15 (PMU_START + 15) ++#define INT_PMU_SD_DETECT0 (PMU_START + 16) ++#define INT_PMU_SD_DETECT1 (PMU_START + 17) ++#define INT_PMU_SD_DETECT2 (PMU_START + 18) ++#define INT_PMU_SD_DETECT3 (PMU_START + 19) ++#define INT_PMU_DUMMY20 (PMU_START + 20) ++#define INT_PMU_KEY0 (PMU_START + 21) ++#define INT_PMU_TP (PMU_START + 22) ++#define INT_PMU_RTC (PMU_START + 23) ++#define INT_PMU_IR (PMU_START + 24) ++#define INT_PMU_CEC (PMU_START + 25) ++#define INT_PMU_ONOFF_PULSE (PMU_START + 26) ++#define INT_PMU_KEYOFF_PULSE (PMU_START + 27) ++#define INT_PMU_ADAPTOR_PLUG (PMU_START + 28) ++#define INT_PMU_ADAPTOR_UNPLUG (PMU_START + 29) ++#define INT_PMU_NO_BAT (PMU_START + 30) ++#define INT_PMU_RIU_CKSUM_PROT (PMU_START + 31) ++#define PMU_END (PMU_START + 32) ++ ++ ++#define CEDRIC_NR_IRQS (PMU_END) ++ ++#define CEDRIC_NR_GPIO_IRQ (32) ++ ++//for GIC_ID ++#define GIC_ID_LEGACY_FIQ 0x1C ++#define GIC_ID_LEGACY_IRQ 0x1F ++#define GIC_ID_LOCAL_TIMER_IRQ 0x1D ++ ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/mstar/include/cedric/registers.h b/drivers/mstar/include/cedric/registers.h +new file mode 100644 +index 00000000..b259583c +--- /dev/null ++++ b/drivers/mstar/include/cedric/registers.h +@@ -0,0 +1,164 @@ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++//#define GET_REG_ADDR(x, y) (x+((y)<<2)) ++ ++#define BASE_REG_CHIPTOP_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x80F00) ++#define BASE_REG_CHIPGPIO1_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x80D00) ++#define BASE_REG_CHIPGPIO_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x81580) ++#define BASE_REG_PWM_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x81900) ++#define BASE_REG_PMMISC_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x01700) ++#define BASE_REG_CLKGEN0_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x080580) ++#define BASE_REG_CLKGEN1_PA GET_REG_ADDR(BASE_REG_RIU_PA, 0x081980) ++ ++ ++/*CHIPTOP register*/ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++ ++#endif +diff --git a/drivers/mstar/include/chicago/irqs.h b/drivers/mstar/include/chicago/irqs.h +new file mode 100644 +index 00000000..824c5a1b +--- /dev/null ++++ b/drivers/mstar/include/chicago/irqs.h +@@ -0,0 +1,131 @@ ++/*------------------------------------------------------------------------------ ++ Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++------------------------------------------------------------------------------*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __ARCH_ARM_ASM_IRQS_H ++#define __ARCH_ARM_ASM_IRQS_H ++/*----------------------------------------------------------------------------- ++ Include Files ++------------------------------------------------------------------------------*/ ++ ++ ++/*------------------------------------------------------------------------------ ++ Constant ++-------------------------------------------------------------------------------*/ ++ ++#define INT_START 0 ++ ++/* FIQ Definition */ ++#define FIQ_START INT_START ++#define INT_FIQ_WDT (FIQ_START + 0) ++#define INT_FIQ_TIMER0 (FIQ_START + 1) ++#define INT_FIQ_TIMER1 (FIQ_START + 2) ++#define INT_FIQ_TIMER2 (FIQ_START + 3) ++#define INT_FIQ_TIMER3 (FIQ_START + 4) ++#define INT_FIQ_TIMER4 (FIQ_START + 5) ++#define INT_FIQ_GDMA (FIQ_START + 6) ++#define INT_FIQ_GPS_DCD (FIQ_START + 7) ++#define INT_FIQ_DUMMY08 (FIQ_START + 8) ++#define INT_FIQ_SARADC (FIQ_START + 9) ++#define INT_FIQ_DUMMY10 (FIQ_START + 10) ++#define INT_FIQ_DUMMY11 (FIQ_START + 11) ++#define INT_FIQ_DUMMY12 (FIQ_START + 12) ++#define INT_FIQ_DUMMY13 (FIQ_START + 13) ++#define INT_FIQ_DUMMY14 (FIQ_START + 14) ++#define INT_FIQ_DUMMY15 (FIQ_START + 15) ++#define INT_FIQ_DUMMY16 (FIQ_START + 16) ++#define INT_FIQ_DUMMY17 (FIQ_START + 17) ++#define INT_FIQ_DUMMY18 (FIQ_START + 18) ++#define INT_FIQ_DUMMY19 (FIQ_START + 19) ++#define INT_FIQ_DUMMY20 (FIQ_START + 20) ++#define INT_FIQ_DUMMY21 (FIQ_START + 21) ++#define INT_FIQ_DUMMY22 (FIQ_START + 22) ++#define INT_FIQ_DUMMY23 (FIQ_START + 23) ++#define INT_FIQ_DUMMY24 (FIQ_START + 24) ++#define INT_FIQ_DUMMY25 (FIQ_START + 25) ++#define INT_FIQ_DUMMY26 (FIQ_START + 26) ++#define INT_FIQ_DUMMY27 (FIQ_START + 27) ++#define INT_FIQ_DUMMY28 (FIQ_START + 28) ++#define INT_FIQ_DUMMY29 (FIQ_START + 29) ++#define INT_FIQ_DUMMY30 (FIQ_START + 30) ++#define INT_FIQ_DUMMY31 (FIQ_START + 31) ++#define FIQ_END (FIQ_START + 32) ++ ++/* IRQ Definition */ ++#define IRQ_START (FIQ_END) ++#define INT_IRQ_PMU (IRQ_START + 0) ++#define INT_FIQ_DUMMY01 (IRQ_START + 1) ++#define INT_IRQ_AUDIO_2 (IRQ_START + 2) ++#define INT_IRQ_AUDIO_1 (IRQ_START + 3) ++#define INT_IRQ_GOP (IRQ_START + 4) ++#define INT_IRQ_IPM (IRQ_START + 5) ++#define INT_IRQ_DISP (IRQ_START + 6) ++#define INT_IRQ_JPD (IRQ_START + 7) ++#define INT_IRQ_UHC (IRQ_START + 8) ++#define INT_IRQ_OTG (IRQ_START + 9) ++#define INT_IRQ_USB (IRQ_START + 10) ++#define INT_IRQ_GPS_SIGP (IRQ_START + 11) ++#define INT_IRQ_GE (IRQ_START + 12) ++#define INT_IRQ_UART0 (IRQ_START + 13) ++#define INT_IRQ_SDIO (IRQ_START + 14) ++#define INT_IRQ_FCIE (IRQ_START + 15) ++#define INT_IRQ_IIC (IRQ_START + 16) ++#define INT_IRQ_MIU (IRQ_START + 17) ++#define INT_IRQ_DW_SSI_DMA (IRQ_START + 18) ++#define INT_IRQ_DW_SSI (IRQ_START + 19) ++#define INT_IRQ_UART3 (IRQ_START + 20) ++#define INT_IRQ_UART2 (IRQ_START + 21) ++#define INT_IRQ_UART1 (IRQ_START + 22) ++#define INT_IRQ_UART3_DMA (IRQ_START + 23) ++#define INT_IRQ_COMBO_TIMER (IRQ_START + 24) ++#define INT_IRQ_CPUIF (IRQ_START + 25) ++#define INT_IRQ_UART2_DMA (IRQ_START + 26) ++#define INT_IRQ_GPS_DCD (IRQ_START + 27) ++#define INT_IRQ_COMBO_WDT (IRQ_START + 28) ++#define INT_IRQ_AUX_PENDET (IRQ_START + 29) ++#define INT_IRQ_ADCDONE (IRQ_START + 30) ++#define INT_IRQ_KEY0 (IRQ_START + 31) ++#define IRQ_END (IRQ_START + 32) ++ ++#define PMU_START (IRQ_END) ++#define INT_PMU_BUCK2_OCP_DEBOUNCE (PMU_START + 0) ++#define INT_PMU_BUCK1_OCP_DEBOUNCE (PMU_START + 1) ++#define INT_PMU_OVER_VOLTAGE (PMU_START + 2) ++#define INT_PMU_OTP_DEBOUNCE (PMU_START + 3) ++#define INT_PMU_LDO_ERR (PMU_START + 4) ++#define INT_PMU_IRQ_PGA (PMU_START + 5) ++#define INT_PMU_IRQ_OCP (PMU_START + 6) ++#define INT_PMU_NO_BAT (PMU_START + 7) ++#define INT_PMU_BAT_LOW (PMU_START + 8) ++#define INT_PMU_ADAPTOR_PLUG (PMU_START + 9) ++#define INT_PMU_ADAPTOR_UNPLUG (PMU_START + 10) ++#define INT_PMU_KEYOFF_PULSE (PMU_START + 11) ++#define INT_PMU_ONOFF_PULSE (PMU_START + 12) ++#define INT_PMU_RTC (PMU_START + 13) ++#define INT_PMU_TOUCH_DETECT (PMU_START + 14) ++#define INT_PMU_SAR_KEY_DETECT (PMU_START + 15) ++#define INT_PMU_GPIO00 (PMU_START + 16) ++#define INT_PMU_GPIO01 (PMU_START + 17) ++#define INT_PMU_GPIO02 (PMU_START + 18) ++#define INT_PMU_GPIO03 (PMU_START + 19) ++#define INT_PMU_GPIO04 (PMU_START + 20) ++#define INT_PMU_GPIO05 (PMU_START + 21) ++#define INT_PMU_GPIO06 (PMU_START + 22) ++#define INT_PMU_WORKLED (PMU_START + 23) ++#define INT_PMU_DUMMY24 (PMU_START + 24) ++#define INT_PMU_DUMMY25 (PMU_START + 25) ++#define INT_PMU_DUMMY26 (PMU_START + 26) ++#define INT_PMU_DUMMY27 (PMU_START + 27) ++#define INT_PMU_SD_DETECT (PMU_START + 28) ++#define INT_PMU_DUMMY29 (PMU_START + 29) ++#define INT_PMU_RIU_CKSUM_PROT (PMU_START + 30) ++#define INT_PMU_DUMMY31 (PMU_START + 31) ++#define PMU_END (PMU_START + 32) ++ ++#define CHICAGO_NR_IRQS (PMU_END) ++ ++ ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/mstar/include/chicago/registers.h b/drivers/mstar/include/chicago/registers.h +new file mode 100644 +index 00000000..a2a7ef8c +--- /dev/null ++++ b/drivers/mstar/include/chicago/registers.h +@@ -0,0 +1,158 @@ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_PADTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0B00) ++#define BASE_REG_PIUMISC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3C00) ++#define BASE_REG_PM_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3F00) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2B00) ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++//#define GET_REG_ADDR(x, y) (x+((y)<<2)) ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++ ++#endif +diff --git a/drivers/mstar/include/infinity/gpio.h b/drivers/mstar/include/infinity/gpio.h +new file mode 100644 +index 00000000..50743a88 +--- /dev/null ++++ b/drivers/mstar/include/infinity/gpio.h +@@ -0,0 +1,106 @@ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO10 10 ++#define PAD_GPIO11 11 ++#define PAD_GPIO12 12 ++#define PAD_GPIO13 13 ++#define PAD_GPIO14 14 ++#define PAD_GPIO15 15 ++#define PAD_PWM0 16 ++#define PAD_PWM1 17 ++#define PAD_FUART_RX 18 ++#define PAD_FUART_TX 19 ++#define PAD_FUART_CTS 20 ++#define PAD_FUART_RTS 21 ++#define PAD_UART0_RX 22 ++#define PAD_UART0_TX 23 ++#define PAD_UART1_RX 24 ++#define PAD_UART1_TX 25 ++#define PAD_SR_IO00 26 ++#define PAD_SR_IO01 27 ++#define PAD_SR_IO02 28 ++#define PAD_SR_IO03 29 ++#define PAD_SR_IO04 30 ++#define PAD_SR_IO05 31 ++#define PAD_SR_IO06 32 ++#define PAD_SR_IO07 33 ++#define PAD_SR_IO08 34 ++#define PAD_SR_IO09 35 ++#define PAD_SR_IO10 36 ++#define PAD_SR_IO11 37 ++#define PAD_SR_IO12 38 ++#define PAD_SR_IO13 39 ++#define PAD_SR_IO14 40 ++#define PAD_SR_IO15 41 ++#define PAD_SR_IO16 42 ++#define PAD_SR_IO17 43 ++#define PAD_NAND_CEZ 44 ++#define PAD_NAND_ALE 45 ++#define PAD_NAND_CLE 46 ++#define PAD_NAND_WEZ 47 ++#define PAD_NAND_WPZ 48 ++#define PAD_NAND_REZ 49 ++#define PAD_NAND_RBZ 50 ++#define PAD_NAND_DA0 51 ++#define PAD_NAND_DA1 52 ++#define PAD_NAND_DA2 53 ++#define PAD_NAND_DA3 54 ++#define PAD_NAND_DA4 55 ++#define PAD_NAND_DA5 56 ++#define PAD_NAND_DA6 57 ++#define PAD_NAND_DA7 58 ++#define PAD_SD_CLK 59 ++#define PAD_SD_CMD 60 ++#define PAD_SD_D0 61 ++#define PAD_SD_D1 62 ++#define PAD_SD_D2 63 ++#define PAD_SD_D3 64 ++#define PAD_I2C0_SCL 65 ++#define PAD_I2C0_SDA 66 ++#define PAD_I2C1_SCL 67 ++#define PAD_I2C1_SDA 68 ++#define PAD_SPI0_CZ 69 ++#define PAD_SPI0_CK 70 ++#define PAD_SPI0_DI 71 ++#define PAD_SPI0_DO 72 ++#define PAD_SPI1_CZ 73 ++#define PAD_SPI1_CK 74 ++#define PAD_SPI1_DI 75 ++#define PAD_SPI1_DO 76 ++#define PAD_PM_SD_CDZ 77 ++#define PAD_PM_IRIN 78 ++#define PAD_PM_GPIO0 79 ++#define PAD_PM_GPIO1 80 ++#define PAD_PM_GPIO2 81 ++#define PAD_PM_GPIO3 82 ++#define PAD_PM_GPIO4 83 ++#define PAD_PM_GPIO5 84 ++#define PAD_PM_GPIO6 85 ++#define PAD_PM_GPIO7 86 ++#define PAD_PM_GPIO8 87 ++#define PAD_PM_GPIO9 88 ++#define PAD_PM_GPIO10 89 ++#define PAD_PM_SPI_CZ 90 ++#define PAD_PM_SPI_CK 91 ++#define PAD_PM_SPI_DI 92 ++#define PAD_PM_SPI_DO 93 ++#define PAD_PM_SPI_WPZ 94 ++#define PAD_PM_SPI_HLD 95 ++#define PAD_PM_LED0 96 ++#define PAD_PM_LED1 97 ++#define PAD_SAR_GPIO0 98 ++#define PAD_SAR_GPIO1 99 ++#define PAD_SAR_GPIO2 100 ++#define PAD_SAR_GPIO3 101 ++#endif +diff --git a/drivers/mstar/include/infinity/irqs.h b/drivers/mstar/include/infinity/irqs.h +new file mode 100644 +index 00000000..328174f4 +--- /dev/null ++++ b/drivers/mstar/include/infinity/irqs.h +@@ -0,0 +1,170 @@ ++/*------------------------------------------------------------------------------ ++ Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++------------------------------------------------------------------------------*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++/* [GIC] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : ARM_INTERNAL ++ ID 64 - 127 : MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : MS_FIQ ++ [PMSLEEP] ++ ID 0 - 31 : MS_PM_IRQ ++*/ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_DUMMY_03 (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_POWER_0_NG (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_POWER_1_NG (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DUMMY_09 (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_DUMMY_10 (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_DUMMY_11 (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_PM_ERROR_RESP (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_WAKE_ON_LAN (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_DUMMY_14 (GIC_SPI_MS_IRQ_START + 14) ++#define INT_IRQ_DUMMY_15 (GIC_SPI_MS_IRQ_START + 15) ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_FCIE (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_VHE (GIC_SPI_MS_IRQ_START + 21) ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) //? ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) //? ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) //? ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_DUMMY_52 (GIC_SPI_MS_IRQ_START + 52) ++#define INT_IRQ_DUMMY_53 (GIC_SPI_MS_IRQ_START + 53) ++#define INT_IRQ_DUMMY_54 (GIC_SPI_MS_IRQ_START + 54) ++#define INT_IRQ_DUMMY_55 (GIC_SPI_MS_IRQ_START + 55) ++#define INT_IRQ_DUMMY_56 (GIC_SPI_MS_IRQ_START + 56) ++#define INT_IRQ_DUMMY_57 (GIC_SPI_MS_IRQ_START + 57) ++#define INT_IRQ_DUMMY_58 (GIC_SPI_MS_IRQ_START + 58) ++#define INT_IRQ_DUMMY_59 (GIC_SPI_MS_IRQ_START + 59) ++#define INT_IRQ_DUMMY_60 (GIC_SPI_MS_IRQ_START + 60) ++#define INT_IRQ_DUMMY_61 (GIC_SPI_MS_IRQ_START + 61) ++#define INT_IRQ_DUMMY_62 (GIC_SPI_MS_IRQ_START + 62) ++#define INT_IRQ_DUMMY_63 (GIC_SPI_MS_IRQ_START + 63) ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_IR (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_DVI_CK_DET (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_5 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_6 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_GPIO_10 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_GPIO_11 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_GPIO_12 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_GPIO_13 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_GPIO_14 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_GPIO_15 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_GPIO_16 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_GPIO_17 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_GPIO_18 (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_GPIO_19 (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_GPIO_22 (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_GPIO_23 (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_GPIO_28 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_GPIO_29 (PMSLEEP_FIQ_START + 31) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 32) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/mstar/include/infinity/mcm_id.h b/drivers/mstar/include/infinity/mcm_id.h +new file mode 100644 +index 00000000..1ddad4a7 +--- /dev/null ++++ b/drivers/mstar/include/infinity/mcm_id.h +@@ -0,0 +1,32 @@ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_MCU51 0 ++#define MCM_ID_URDMA 1 ++#define MCM_ID_BDMA 2 ++#define MCM_ID_VHE 3 ++#define MCM_ID_MFE 4 ++#define MCM_ID_JPE 5 ++#define MCM_ID_BACH 6 ++#define MCM_ID_AESDMA 7 ++#define MCM_ID_UHC 8 ++#define MCM_ID_EMAC 9 ++#define MCM_ID_CMDQ 10 ++#define MCM_ID_ISP_DNR 11 ++#define MCM_ID_ISP_DMA 12 ++#define MCM_ID_GOP 13 ++#define MCM_ID_SC_DNR 14 ++#define MCM_ID_SC_DNR_SAD 15 ++#define MCM_ID_SC_CROP 16 ++#define MCM_ID_SC1_FRM 17 ++#define MCM_ID_SC1_SNP 18 ++#define MCM_ID_SC1_DBG 19 ++#define MCM_ID_SC2_FRM 20 ++#define MCM_ID_SC3_FRM 21 ++#define MCM_ID_FCIE 22 ++#define MCM_ID_SDIO 23 ++#define MCM_ID_SC1_SNPI 24 ++#define MCM_ID_SC2_SNPI 25 ++#define MCM_ID_ALL 99 ++ ++#endif +diff --git a/drivers/mstar/include/infinity/reg_clks.h b/drivers/mstar/include/infinity/reg_clks.h +new file mode 100644 +index 00000000..26981e1f +--- /dev/null ++++ b/drivers/mstar/include/infinity/reg_clks.h +@@ -0,0 +1,402 @@ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_4 */ ++/* CLK FILENAME: I1\20151127\iNfinity_Clock_Table_20151127.xls */ ++/* REG FILENAME: I1\20151127\iNfinity_reg_CLKGEN_20151127.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP_PSRAM_OFFSET (0) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_OFFSET (10) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCIE_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_FCIE_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FCLK2_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/mstar/include/infinity/registers.h b/drivers/mstar/include/infinity/registers.h +new file mode 100644 +index 00000000..6005b357 +--- /dev/null ++++ b/drivers/mstar/include/infinity/registers.h +@@ -0,0 +1,198 @@ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define INFINITY_MIU0_BASE 0x20000000 ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x10000 ++ ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++ ++#endif +diff --git a/drivers/mstar/include/infinity3/gpio.h b/drivers/mstar/include/infinity3/gpio.h +new file mode 100644 +index 00000000..0978fc4e +--- /dev/null ++++ b/drivers/mstar/include/infinity3/gpio.h +@@ -0,0 +1,117 @@ ++#ifndef ___GPIO_H ++#define ___GPIO_H ++ ++#define PAD_GPIO0 0 ++#define PAD_GPIO1 1 ++#define PAD_GPIO2 2 ++#define PAD_GPIO3 3 ++#define PAD_GPIO4 4 ++#define PAD_GPIO5 5 ++#define PAD_GPIO6 6 ++#define PAD_GPIO7 7 ++#define PAD_GPIO8 8 ++#define PAD_GPIO9 9 ++#define PAD_GPIO10 10 ++#define PAD_GPIO11 11 ++#define PAD_GPIO12 12 ++#define PAD_GPIO13 13 ++#define PAD_GPIO14 14 ++#define PAD_GPIO15 15 ++#define PAD_FUART_RX 16 ++#define PAD_FUART_TX 17 ++#define PAD_FUART_CTS 18 ++#define PAD_FUART_RTS 19 ++#define PAD_I2C0_SCL 20 ++#define PAD_I2C0_SDA 21 ++#define PAD_I2C1_SCL 22 ++#define PAD_I2C1_SDA 23 ++#define PAD_SR_IO00 24 ++#define PAD_SR_IO01 25 ++#define PAD_SR_IO02 26 ++#define PAD_SR_IO03 27 ++#define PAD_SR_IO04 28 ++#define PAD_SR_IO05 29 ++#define PAD_SR_IO06 30 ++#define PAD_SR_IO07 31 ++#define PAD_SR_IO08 32 ++#define PAD_SR_IO09 33 ++#define PAD_SR_IO10 34 ++#define PAD_SR_IO11 35 ++#define PAD_SR_IO12 36 ++#define PAD_SR_IO13 37 ++#define PAD_SR_IO14 38 ++#define PAD_SR_IO15 39 ++#define PAD_SR_IO16 40 ++#define PAD_SR_IO17 41 ++#define PAD_NAND_ALE 42 ++#define PAD_NAND_CLE 43 ++#define PAD_NAND_CEZ 44 ++#define PAD_NAND_WEZ 45 ++#define PAD_NAND_WPZ 46 ++#define PAD_NAND_REZ 47 ++#define PAD_NAND_RBZ 48 ++#define PAD_NAND_DA0 49 ++#define PAD_NAND_DA1 50 ++#define PAD_NAND_DA2 51 ++#define PAD_NAND_DA3 52 ++#define PAD_NAND_DA4 53 ++#define PAD_NAND_DA5 54 ++#define PAD_NAND_DA6 55 ++#define PAD_NAND_DA7 56 ++#define PAD_UART0_RX 57 ++#define PAD_UART0_TX 58 ++#define PAD_UART1_RX 59 ++#define PAD_UART1_TX 60 ++#define PAD_SPI0_CZ 61 ++#define PAD_SPI0_CK 62 ++#define PAD_SPI0_DI 63 ++#define PAD_SPI0_DO 64 ++#define PAD_SPI1_CZ 65 ++#define PAD_SPI1_CK 66 ++#define PAD_SPI1_DI 67 ++#define PAD_SPI1_DO 68 ++#define PAD_PWM0 69 ++#define PAD_PWM1 70 ++#define PAD_SD_CLK 71 ++#define PAD_SD_CMD 72 ++#define PAD_SD_D0 73 ++#define PAD_SD_D1 74 ++#define PAD_SD_D2 75 ++#define PAD_SD_D3 76 ++#define PAD_PM_SD_CDZ 77 ++#define PAD_PM_IRIN 78 ++#define PAD_PM_GPIO0 79 ++#define PAD_PM_GPIO1 80 ++#define PAD_PM_GPIO2 81 ++#define PAD_PM_GPIO3 82 ++#define PAD_PM_GPIO4 83 ++#define PAD_PM_GPIO5 84 ++#define PAD_PM_GPIO6 85 ++#define PAD_PM_GPIO7 86 ++#define PAD_PM_GPIO8 87 ++#define PAD_PM_GPIO9 88 ++#define PAD_PM_GPIO10 89 ++#define PAD_PM_SPI_CZ 90 ++#define PAD_PM_SPI_CK 91 ++#define PAD_PM_SPI_DI 92 ++#define PAD_PM_SPI_DO 93 ++#define PAD_PM_SPI_WPZ 94 ++#define PAD_PM_SPI_HLD 95 ++#define PAD_PM_LED0 96 ++#define PAD_PM_LED1 97 ++#define PAD_SAR_GPIO0 98 ++#define PAD_SAR_GPIO1 99 ++#define PAD_SAR_GPIO2 100 ++#define PAD_SAR_GPIO3 101 ++#define PAD_ETH_RN 102 ++#define PAD_ETH_RP 103 ++#define PAD_ETH_TN 104 ++#define PAD_ETH_TP 105 ++#define PAD_USB_DM 106 ++#define PAD_USB_DP 107 ++#define PAD_DM_P1 108 ++#define PAD_DP_P1 109 ++ ++#define GPIO_NR 110 ++#define PAD_UNKNOWN 0xFF ++#endif +diff --git a/drivers/mstar/include/infinity3/irqs.h b/drivers/mstar/include/infinity3/irqs.h +new file mode 100644 +index 00000000..b9f9c4d9 +--- /dev/null ++++ b/drivers/mstar/include/infinity3/irqs.h +@@ -0,0 +1,237 @@ ++/*------------------------------------------------------------------------------ ++ Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++------------------------------------------------------------------------------*/ ++/*------------------------------------------------------------------------------ ++ ++------------------------------------------------------------------------------*/ ++ ++#ifndef __IRQS_H ++#define __IRQS_H ++ ++/* [GIC irqchip] ++ ID 0 - 15 : SGI ++ ID 16 - 31 : PPI ++ ID 32 - 63 : SPI:ARM_INTERNAL ++ ID 64 - 127 : SPI:MS_IRQ (GIC_HWIRQ_MS_START) ++ ID 128 - 159 : SPI:MS_FIQ ++ [PMSLEEP irqchip] ++ ID 0 - 31 : MS_PM_IRQ */ ++ ++#define GIC_SGI_NR 16 ++#define GIC_PPI_NR 16 ++#define GIC_SPI_ARM_INTERNAL_NR 32 ++#define GIC_HWIRQ_MS_START (GIC_SGI_NR + GIC_PPI_NR + GIC_SPI_ARM_INTERNAL_NR) ++ ++ ++/* The folloing list are used in dtsi and get number by of_irq, ++if need to get the interrupt number for request_irq(), manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+X=32+X */ ++ ++//NOTE(Spade): We count from GIC_SPI_ARM_INTERNAL because interrupt delcaration in dts is from SPI 0 ++/* MS_NON_PM_IRQ 32-95 */ ++#define GIC_SPI_MS_IRQ_START GIC_SPI_ARM_INTERNAL_NR ++#define INT_IRQ_NONPM_TO_MCU51 (GIC_SPI_MS_IRQ_START + 0) ++#define INT_IRQ_FIQ_FROM_PM (GIC_SPI_MS_IRQ_START + 1) ++#define INT_IRQ_PM_SLEEP (GIC_SPI_MS_IRQ_START + 2) ++#define INT_IRQ_DUMMY_03 (GIC_SPI_MS_IRQ_START + 3) ++#define INT_IRQ_DUMMY_04 (GIC_SPI_MS_IRQ_START + 4) ++#define INT_IRQ_FSP (GIC_SPI_MS_IRQ_START + 5) ++#define INT_IRQ_DUMMY_06 (GIC_SPI_MS_IRQ_START + 6) ++#define INT_IRQ_POWER_0_NG (GIC_SPI_MS_IRQ_START + 7) ++#define INT_IRQ_POWER_1_NG (GIC_SPI_MS_IRQ_START + 8) ++#define INT_IRQ_DUMMY_09 (GIC_SPI_MS_IRQ_START + 9) ++#define INT_IRQ_DUMMY_10 (GIC_SPI_MS_IRQ_START + 10) ++#define INT_IRQ_DUMMY_11 (GIC_SPI_MS_IRQ_START + 11) ++#define INT_IRQ_PM_ERROR_RESP (GIC_SPI_MS_IRQ_START + 12) ++#define INT_IRQ_WAKE_ON_LAN (GIC_SPI_MS_IRQ_START + 13) ++#define INT_IRQ_DUMMY_14 (GIC_SPI_MS_IRQ_START + 14) ++#define INT_IRQ_DUMMY_15 (GIC_SPI_MS_IRQ_START + 15) ++#define INT_IRQ_IRQ_FROM_PM (GIC_SPI_MS_IRQ_START + 16) ++#define INT_IRQ_CMDQ (GIC_SPI_MS_IRQ_START + 17) ++#define INT_IRQ_FCIE (GIC_SPI_MS_IRQ_START + 18) ++#define INT_IRQ_SDIO (GIC_SPI_MS_IRQ_START + 19) ++#define INT_IRQ_SC_TOP (GIC_SPI_MS_IRQ_START + 20) ++#define INT_IRQ_VHE (GIC_SPI_MS_IRQ_START + 21) ++#define INT_IRQ_PS (GIC_SPI_MS_IRQ_START + 22) //? ++#define INT_IRQ_WADR_ERROR (GIC_SPI_MS_IRQ_START + 23) //? ++#define INT_IRQ_PM (GIC_SPI_MS_IRQ_START + 24) ++#define INT_IRQ_ISP (GIC_SPI_MS_IRQ_START + 25) ++#define INT_IRQ_EMAC (GIC_SPI_MS_IRQ_START + 26) ++#define INT_IRQ_HEMCU (GIC_SPI_MS_IRQ_START + 27) //? ++#define INT_IRQ_MFE (GIC_SPI_MS_IRQ_START + 28) ++#define INT_IRQ_JPE (GIC_SPI_MS_IRQ_START + 29) ++#define INT_IRQ_USB (GIC_SPI_MS_IRQ_START + 30) ++#define INT_IRQ_UHC (GIC_SPI_MS_IRQ_START + 31) ++#define INT_IRQ_OTG (GIC_SPI_MS_IRQ_START + 32) ++#define INT_IRQ_MIPI_CSI2 (GIC_SPI_MS_IRQ_START + 33) ++#define INT_IRQ_UART_0 (GIC_SPI_MS_IRQ_START + 34) ++#define INT_IRQ_UART_1 (GIC_SPI_MS_IRQ_START + 35) ++#define INT_IRQ_MIIC_0 (GIC_SPI_MS_IRQ_START + 36) ++#define INT_IRQ_MIIC_1 (GIC_SPI_MS_IRQ_START + 37) ++#define INT_IRQ_MSPI_0 (GIC_SPI_MS_IRQ_START + 38) ++#define INT_IRQ_MSPI_1 (GIC_SPI_MS_IRQ_START + 39) ++#define INT_IRQ_BDMA_0 (GIC_SPI_MS_IRQ_START + 40) ++#define INT_IRQ_BDMA_1 (GIC_SPI_MS_IRQ_START + 41) ++#define INT_IRQ_BACH (GIC_SPI_MS_IRQ_START + 42) ++#define INT_IRQ_KEYPAD (GIC_SPI_MS_IRQ_START + 43) ++#define INT_IRQ_RTC (GIC_SPI_MS_IRQ_START + 44) ++#define INT_IRQ_SAR (GIC_SPI_MS_IRQ_START + 45) ++#define INT_IRQ_IMI (GIC_SPI_MS_IRQ_START + 46) ++#define INT_IRQ_FUART (GIC_SPI_MS_IRQ_START + 47) ++#define INT_IRQ_URDMA (GIC_SPI_MS_IRQ_START + 48) ++#define INT_IRQ_MIU (GIC_SPI_MS_IRQ_START + 49) ++#define INT_IRQ_GOP (GIC_SPI_MS_IRQ_START + 50) ++#define INT_IRQ_RIU_ERROR_RESP (GIC_SPI_MS_IRQ_START + 51) ++#define INT_IRQ_CMDQ1 (GIC_SPI_MS_IRQ_START + 52) //I3 New ++#define INT_IRQ_CMDQ2 (GIC_SPI_MS_IRQ_START + 53) //I3 New ++#define INT_IRQ_USB_INT_P1 (GIC_SPI_MS_IRQ_START + 54) //I3 New ++#define INT_IRQ_UHC_INT_P1 (GIC_SPI_MS_IRQ_START + 55) //I3 New ++#define INT_IRQ_IVE_INT (GIC_SPI_MS_IRQ_START + 56) //I3 New ++#define INT_IRQ_LDC_IRQ (GIC_SPI_MS_IRQ_START + 57) //I3 New ++#define INT_IRQ_SC1_TOP_INT (GIC_SPI_MS_IRQ_START + 58) //I3 New ++#define INT_IRQ_SC2_TOP_INT (GIC_SPI_MS_IRQ_START + 59) //I3 New ++#define INT_IRQ_DUMMY_60 (GIC_SPI_MS_IRQ_START + 60) ++#define INT_IRQ_DUMMY_61 (GIC_SPI_MS_IRQ_START + 61) ++#define INT_IRQ_DUMMY_62 (GIC_SPI_MS_IRQ_START + 62) ++#define INT_IRQ_DUMMY_63 (GIC_SPI_MS_IRQ_START + 63) ++#define GIC_SPI_MS_IRQ_END (GIC_SPI_MS_IRQ_START + 64) ++#define GIC_SPI_MS_IRQ_NR (GIC_SPI_MS_IRQ_END - GIC_SPI_MS_IRQ_START) ++ ++/* MS_NON_PM_FIQ 96-127 */ ++#define GIC_SPI_MS_FIQ_START GIC_SPI_MS_IRQ_END ++#define INT_FIQ_TIMER_0 (GIC_SPI_MS_FIQ_START + 0) ++#define INT_FIQ_TIMER_1 (GIC_SPI_MS_FIQ_START + 1) ++#define INT_FIQ_WDT (GIC_SPI_MS_FIQ_START + 2) ++#define INT_FIQ_IR (GIC_SPI_MS_FIQ_START + 3) ++#define INT_FIQ_IR_RC (GIC_SPI_MS_FIQ_START + 4) ++#define INT_FIQ_POWER_0_NG (GIC_SPI_MS_FIQ_START + 5) ++#define INT_FIQ_POWER_1_NG (GIC_SPI_MS_FIQ_START + 6) ++#define INT_FIQ_POWER_2_NG (GIC_SPI_MS_FIQ_START + 7) ++#define INT_FIQ_PM_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 8) ++#define INT_FIQ_DUMMY_09 (GIC_SPI_MS_FIQ_START + 9) ++#define INT_FIQ_DUMMY_10 (GIC_SPI_MS_FIQ_START + 10) ++#define INT_FIQ_DUMMY_11 (GIC_SPI_MS_FIQ_START + 11) ++#define INT_FIQ_TIMER_2 (GIC_SPI_MS_FIQ_START + 12) ++#define INT_FIQ_DUMMY_13 (GIC_SPI_MS_FIQ_START + 13) ++#define INT_FIQ_DUMMY_14 (GIC_SPI_MS_FIQ_START + 14) ++#define INT_FIQ_DUMMY_15 (GIC_SPI_MS_FIQ_START + 15) ++#define INT_FIQ_FIQ_FROM_PM (GIC_SPI_MS_FIQ_START + 16) ++#define INT_FIQ_MCU51_TO_ARM (GIC_SPI_MS_FIQ_START + 17) ++#define INT_FIQ_ARM_TO_MCU51 (GIC_SPI_MS_FIQ_START + 18) ++#define INT_FIQ_DUMMY_19 (GIC_SPI_MS_FIQ_START + 19) ++#define INT_FIQ_DUMMY_20 (GIC_SPI_MS_FIQ_START + 20) ++#define INT_FIQ_LAN_ESD (GIC_SPI_MS_FIQ_START + 21) ++#define INT_FIQ_XIU_TIMEOUT (GIC_SPI_MS_FIQ_START + 22) ++#define INT_FIQ_SD_CDZ (GIC_SPI_MS_FIQ_START + 23) ++#define INT_FIQ_SAR_GPIO_0 (GIC_SPI_MS_FIQ_START + 24) ++#define INT_FIQ_SAR_GPIO_1 (GIC_SPI_MS_FIQ_START + 25) ++#define INT_FIQ_SAR_GPIO_2 (GIC_SPI_MS_FIQ_START + 26) ++#define INT_FIQ_SAR_GPIO_3 (GIC_SPI_MS_FIQ_START + 27) ++#define INT_FIQ_SPI0_GPIO_0 (GIC_SPI_MS_FIQ_START + 28) ++#define INT_FIQ_SPI0_GPIO_1 (GIC_SPI_MS_FIQ_START + 29) ++#define INT_FIQ_SPI0_GPIO_2 (GIC_SPI_MS_FIQ_START + 30) ++#define INT_FIQ_SPI0_GPIO_3 (GIC_SPI_MS_FIQ_START + 31) ++#define GIC_SPI_MS_FIQ_END (GIC_SPI_MS_FIQ_START + 32) ++#define GIC_SPI_MS_FIQ_NR (GIC_SPI_MS_FIQ_END - GIC_SPI_MS_FIQ_START) ++ ++ ++ ++/* Not used in dtsi, ++if need to get the interrupt number for request_irq(), use gpio_to_irq() to obtain irq number. ++Or manual calculate the number is ++GIC_SGI_NR+GIC_PPI_NR+GIC_SPI_ARM_INTERNAL_NR+GIC_SPI_MS_IRQ_NR+GIC_SPI_MS_FIQ_NR+X=160+X */ ++/* MS_PM_SLEEP_FIQ 0-31 */ ++#define PMSLEEP_FIQ_START 0 ++#define INT_PMSLEEP_IR (PMSLEEP_FIQ_START + 0) ++#define INT_PMSLEEP_DVI_CK_DET (PMSLEEP_FIQ_START + 1) ++#define INT_PMSLEEP_GPIO_0 (PMSLEEP_FIQ_START + 2) ++#define INT_PMSLEEP_GPIO_1 (PMSLEEP_FIQ_START + 3) ++#define INT_PMSLEEP_GPIO_2 (PMSLEEP_FIQ_START + 4) ++#define INT_PMSLEEP_GPIO_3 (PMSLEEP_FIQ_START + 5) ++#define INT_PMSLEEP_GPIO_4 (PMSLEEP_FIQ_START + 6) ++#define INT_PMSLEEP_GPIO_5 (PMSLEEP_FIQ_START + 7) ++#define INT_PMSLEEP_GPIO_6 (PMSLEEP_FIQ_START + 8) ++#define INT_PMSLEEP_GPIO_7 (PMSLEEP_FIQ_START + 9) ++#define INT_PMSLEEP_GPIO_8 (PMSLEEP_FIQ_START + 10) ++#define INT_PMSLEEP_GPIO_9 (PMSLEEP_FIQ_START + 11) ++#define INT_PMSLEEP_GPIO_10 (PMSLEEP_FIQ_START + 12) ++#define INT_PMSLEEP_DUMMY_13 (PMSLEEP_FIQ_START + 13) ++#define INT_PMSLEEP_DUMMY_14 (PMSLEEP_FIQ_START + 14) ++#define INT_PMSLEEP_DUMMY_15 (PMSLEEP_FIQ_START + 15) ++#define INT_PMSLEEP_DUMMY_16 (PMSLEEP_FIQ_START + 16) ++#define INT_PMSLEEP_DUMMY_17 (PMSLEEP_FIQ_START + 17) ++#define INT_PMSLEEP_DUMMY_18 (PMSLEEP_FIQ_START + 18) ++#define INT_PMSLEEP_DUMMY_19 (PMSLEEP_FIQ_START + 19) ++#define INT_PMSLEEP_DUMMY_20 (PMSLEEP_FIQ_START + 20) ++#define INT_PMSLEEP_DUMMY_21 (PMSLEEP_FIQ_START + 21) ++#define INT_PMSLEEP_IRIN (PMSLEEP_FIQ_START + 22) ++#define INT_PMSLEEP_UART_RX (PMSLEEP_FIQ_START + 23) ++#define INT_PMSLEEP_DUMMY_24 (PMSLEEP_FIQ_START + 24) ++#define INT_PMSLEEP_DUMMY_25 (PMSLEEP_FIQ_START + 25) ++#define INT_PMSLEEP_SPI_CZ (PMSLEEP_FIQ_START + 26) ++#define INT_PMSLEEP_SPI_CK (PMSLEEP_FIQ_START + 27) ++#define INT_PMSLEEP_SPI_DI (PMSLEEP_FIQ_START + 28) ++#define INT_PMSLEEP_SPI_DO (PMSLEEP_FIQ_START + 29) ++#define INT_PMSLEEP_DUMMY_30 (PMSLEEP_FIQ_START + 30) ++#define INT_PMSLEEP_DUMMY_31 (PMSLEEP_FIQ_START + 31) ++#define INT_PMSLEEP_DUMMY_32 (PMSLEEP_FIQ_START + 32) ++#define INT_PMSLEEP_DUMMY_33 (PMSLEEP_FIQ_START + 33) ++#define INT_PMSLEEP_DUMMY_34 (PMSLEEP_FIQ_START + 34) ++#define INT_PMSLEEP_DUMMY_35 (PMSLEEP_FIQ_START + 35) ++#define INT_PMSLEEP_DUMMY_36 (PMSLEEP_FIQ_START + 36) ++#define INT_PMSLEEP_DUMMY_37 (PMSLEEP_FIQ_START + 37) ++#define INT_PMSLEEP_DUMMY_38 (PMSLEEP_FIQ_START + 38) ++#define INT_PMSLEEP_DUMMY_39 (PMSLEEP_FIQ_START + 39) ++#define INT_PMSLEEP_DUMMY_40 (PMSLEEP_FIQ_START + 40) ++#define INT_PMSLEEP_DUMMY_41 (PMSLEEP_FIQ_START + 41) ++#define INT_PMSLEEP_DUMMY_42 (PMSLEEP_FIQ_START + 42) ++#define INT_PMSLEEP_DUMMY_43 (PMSLEEP_FIQ_START + 43) ++#define INT_PMSLEEP_DUMMY_44 (PMSLEEP_FIQ_START + 44) ++#define INT_PMSLEEP_DUMMY_45 (PMSLEEP_FIQ_START + 45) ++#define INT_PMSLEEP_DUMMY_46 (PMSLEEP_FIQ_START + 46) ++#define INT_PMSLEEP_DUMMY_47 (PMSLEEP_FIQ_START + 47) ++#define INT_PMSLEEP_DUMMY_48 (PMSLEEP_FIQ_START + 48) ++#define INT_PMSLEEP_DUMMY_49 (PMSLEEP_FIQ_START + 49) ++#define INT_PMSLEEP_DUMMY_50 (PMSLEEP_FIQ_START + 50) ++#define INT_PMSLEEP_DUMMY_51 (PMSLEEP_FIQ_START + 51) ++#define INT_PMSLEEP_DUMMY_52 (PMSLEEP_FIQ_START + 52) ++#define INT_PMSLEEP_DUMMY_53 (PMSLEEP_FIQ_START + 53) ++#define INT_PMSLEEP_DUMMY_54 (PMSLEEP_FIQ_START + 54) ++#define INT_PMSLEEP_DUMMY_55 (PMSLEEP_FIQ_START + 55) ++#define INT_PMSLEEP_DUMMY_56 (PMSLEEP_FIQ_START + 56) ++#define INT_PMSLEEP_DUMMY_57 (PMSLEEP_FIQ_START + 57) ++#define INT_PMSLEEP_DUMMY_58 (PMSLEEP_FIQ_START + 58) ++#define INT_PMSLEEP_DUMMY_59 (PMSLEEP_FIQ_START + 59) ++#define INT_PMSLEEP_DUMMY_60 (PMSLEEP_FIQ_START + 60) ++#define INT_PMSLEEP_DUMMY_61 (PMSLEEP_FIQ_START + 61) ++#define INT_PMSLEEP_DUMMY_62 (PMSLEEP_FIQ_START + 62) ++#define INT_PMSLEEP_DUMMY_63 (PMSLEEP_FIQ_START + 63) ++#define INT_PMSLEEP_DUMMY_64 (PMSLEEP_FIQ_START + 64) ++#define INT_PMSLEEP_DUMMY_65 (PMSLEEP_FIQ_START + 65) ++#define INT_PMSLEEP_DUMMY_66 (PMSLEEP_FIQ_START + 66) ++#define INT_PMSLEEP_DUMMY_67 (PMSLEEP_FIQ_START + 67) ++#define INT_PMSLEEP_DUMMY_68 (PMSLEEP_FIQ_START + 68) ++#define INT_PMSLEEP_DUMMY_69 (PMSLEEP_FIQ_START + 69) ++#define INT_PMSLEEP_DUMMY_70 (PMSLEEP_FIQ_START + 70) ++#define INT_PMSLEEP_DUMMY_71 (PMSLEEP_FIQ_START + 71) ++#define INT_PMSLEEP_DUMMY_72 (PMSLEEP_FIQ_START + 72) ++#define INT_PMSLEEP_DUMMY_73 (PMSLEEP_FIQ_START + 73) ++#define INT_PMSLEEP_DUMMY_74 (PMSLEEP_FIQ_START + 74) ++#define INT_PMSLEEP_DUMMY_75 (PMSLEEP_FIQ_START + 75) ++#define INT_PMSLEEP_DUMMY_76 (PMSLEEP_FIQ_START + 76) ++#define INT_PMSLEEP_DUMMY_77 (PMSLEEP_FIQ_START + 77) ++#define PMSLEEP_FIQ_END (PMSLEEP_FIQ_START + 78) ++#define PMSLEEP_FIQ_NR (PMSLEEP_FIQ_END - PMSLEEP_FIQ_START) ++ ++#define PMSLEEP_IRQ_START PMSLEEP_FIQ_END ++#define INT_PMSLEEP_IRQ_DUMMY_00 (PMSLEEP_IRQ_START + 0) ++#define INT_PMSLEEP_IRQ_SAR (PMSLEEP_IRQ_START + 1) ++#define INT_PMSLEEP_IRQ_WOL (PMSLEEP_IRQ_START + 2) ++#define INT_PMSLEEP_IRQ_DUMMY_03 (PMSLEEP_IRQ_START + 3) ++#define INT_PMSLEEP_IRQ_RTC (PMSLEEP_IRQ_START + 4) ++#define INT_PMSLEEP_IRQ_DUMMY_05 (PMSLEEP_IRQ_START + 5) ++#define INT_PMSLEEP_IRQ_SAR_GPIO (PMSLEEP_IRQ_START + 6) ++#define INT_PMSLEEP_IRQ_DUMMY_07 (PMSLEEP_IRQ_START + 7) ++#define PMSLEEP_IRQ_END (PMSLEEP_IRQ_START + 8) ++#define PMSLEEP_IRQ_NR (PMSLEEP_IRQ_END - PMSLEEP_IRQ_START) ++#endif // __ARCH_ARM_ASM_IRQS_H +diff --git a/drivers/mstar/include/infinity3/mcm_id.h b/drivers/mstar/include/infinity3/mcm_id.h +new file mode 100644 +index 00000000..1ddad4a7 +--- /dev/null ++++ b/drivers/mstar/include/infinity3/mcm_id.h +@@ -0,0 +1,32 @@ ++#ifndef ___MCM_ID_H ++#define ___MCM_ID_H ++ ++#define MCM_ID_MCU51 0 ++#define MCM_ID_URDMA 1 ++#define MCM_ID_BDMA 2 ++#define MCM_ID_VHE 3 ++#define MCM_ID_MFE 4 ++#define MCM_ID_JPE 5 ++#define MCM_ID_BACH 6 ++#define MCM_ID_AESDMA 7 ++#define MCM_ID_UHC 8 ++#define MCM_ID_EMAC 9 ++#define MCM_ID_CMDQ 10 ++#define MCM_ID_ISP_DNR 11 ++#define MCM_ID_ISP_DMA 12 ++#define MCM_ID_GOP 13 ++#define MCM_ID_SC_DNR 14 ++#define MCM_ID_SC_DNR_SAD 15 ++#define MCM_ID_SC_CROP 16 ++#define MCM_ID_SC1_FRM 17 ++#define MCM_ID_SC1_SNP 18 ++#define MCM_ID_SC1_DBG 19 ++#define MCM_ID_SC2_FRM 20 ++#define MCM_ID_SC3_FRM 21 ++#define MCM_ID_FCIE 22 ++#define MCM_ID_SDIO 23 ++#define MCM_ID_SC1_SNPI 24 ++#define MCM_ID_SC2_SNPI 25 ++#define MCM_ID_ALL 99 ++ ++#endif +diff --git a/drivers/mstar/include/infinity3/padmux.h b/drivers/mstar/include/infinity3/padmux.h +new file mode 100644 +index 00000000..fb3d85bf +--- /dev/null ++++ b/drivers/mstar/include/infinity3/padmux.h +@@ -0,0 +1,41 @@ ++#ifndef ___PADMUX_H ++#define ___PADMUX_H ++ ++#define PINMUX_FOR_GPIO_MODE 0x00 ++#define PINMUX_FOR_I2C0_MODE 0x01 ++#define PINMUX_FOR_I2C1_MODE 0x02 ++#define PINMUX_FOR_SPI0_MODE 0x03 ++#define PINMUX_FOR_SPI1_MODE 0x04 ++#define PINMUX_FOR_FUART_MODE 0x05 ++#define PINMUX_FOR_UART0_MODE 0x06 ++#define PINMUX_FOR_UART1_MODE 0x07 ++#define PINMUX_FOR_SD_MODE 0x08 ++#define PINMUX_FOR_SDIO_MODE 0x09 ++#define PINMUX_FOR_NAND_MODE 0x0a ++#define PINMUX_FOR_EMMC_MODE 0x0b ++#define PINMUX_FOR_IRIN_MODE 0x0c ++#define PINMUX_FOR_SAR_MODE 0x0d ++#define PINMUX_FOR_SR_MODE 0x0e ++#define PINMUX_FOR_TTL_MODE 0x0f ++#define PINMUX_FOR_PWM0_MODE 0x10 ++#define PINMUX_FOR_PWM1_MODE 0x11 ++#define PINMUX_FOR_PWM2_MODE 0x12 ++#define PINMUX_FOR_PWM3_MODE 0x13 ++#define PINMUX_FOR_PWM4_MODE 0x14 ++#define PINMUX_FOR_PWM5_MODE 0x15 ++#define PINMUX_FOR_PWM6_MODE 0x16 ++#define PINMUX_FOR_PWM7_MODE 0x17 ++#define PINMUX_FOR_I2S_MODE 0x18 ++#define PINMUX_FOR_ETH_MODE 0x19 ++#define PINMUX_FOR_CCIR_MODE 0x1a ++#define PINMUX_FOR_DMIC_MODE 0x1b ++#define PINMUX_FOR_EJ_MODE 0x1c ++#define PINMUX_FOR_PMSPI_MODE 0x1d ++#define PINMUX_FOR_LED_MODE 0x1e ++#define PINMUX_FOR_UNKNOWN_MODE 0xFF ++ ++S32 halPadGetVal(U32 padID, U32* mode); ++S32 halPadSetVal(U32 padID, U32 mode); ++S32 halCheckPin(U32 padID); ++ ++#endif +diff --git a/drivers/mstar/include/infinity3/reg_clks.h b/drivers/mstar/include/infinity3/reg_clks.h +new file mode 100644 +index 00000000..cb6ff6c0 +--- /dev/null ++++ b/drivers/mstar/include/infinity3/reg_clks.h +@@ -0,0 +1,432 @@ ++#ifndef __REG_CLKS_H ++#define __REG_CLKS_H ++ ++/* generated by CLK_DT_GEN_5 */ ++/* CLK FILENAME: I3\iNfinity3e_Clock_Table_20161111_v0p2.xls */ ++/* REG FILENAME: I3\20161109\iNfinity3e_reg_CLKGEN.xls, I3\20161109\iNfinity3e_reg_pm_sleep.xls, I3\20161109\iNfinity3e_reg_block.xls */ ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_SC_GP_CTRL_BASE 0x1F226600 ++#define REG_PM_SLEEP_CKG_BASE 0x1F001C00 ++ ++ ++//====SPECIAL_CKG_REG============================================== ++#define REG_CKG_EMAC_RX_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_OFFSET (0) ++ ++#define REG_CKG_EMAC_RX_REF_BASE (REG_SC_GP_CTRL_BASE+0x22*4) ++#define REG_CKG_EMAC_RX_REF_OFFSET (8) ++ ++#define REG_CKG_EMAC_TX_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_OFFSET (0) ++ ++#define REG_CKG_EMAC_TX_REF_BASE (REG_SC_GP_CTRL_BASE+0x23*4) ++#define REG_CKG_EMAC_TX_REF_OFFSET (8) ++ ++#define REG_CKG_GOP0_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP0_PSRAM_OFFSET (0) ++ ++#define REG_CKG_GOP1_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP1_PSRAM_OFFSET (4) ++ ++#define REG_CKG_GOP2_PSRAM_BASE (REG_SC_GP_CTRL_BASE+0x21*4) ++#define REG_CKG_GOP2_PSRAM_OFFSET (8) ++ ++#define REG_CKG_IMI_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_IMI_OFFSET (0) ++ ++#define REG_CKG_NLM_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_CKG_NLM_OFFSET (8) ++ ++#define REG_NLM_CLK_GATE_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_GATE_RD_OFFSET (13) ++ ++#define REG_NLM_CLK_SEL_RD_BASE (REG_SC_GP_CTRL_BASE+0x20*4) ++#define REG_NLM_CLK_SEL_RD_OFFSET (12) ++ ++#define REG_SC_SPARE_HI_BASE (REG_SC_GP_CTRL_BASE+0x31*4) ++#define REG_SC_SPARE_HI_OFFSET (0) ++ ++#define REG_SC_SPARE_LO_BASE (REG_SC_GP_CTRL_BASE+0x30*4) ++#define REG_SC_SPARE_LO_OFFSET (0) ++ ++#define REG_SC_TEST_IN_SEL_BASE (REG_SC_GP_CTRL_BASE+0x32*4) ++#define REG_SC_TEST_IN_SEL_OFFSET (0) ++ ++ ++ ++//====PM_CKG_REG============================================== ++#define REG_CKG_AV_LNK_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_AV_LNK_OFFSET (4) ++ ++#define REG_CKG_CEC_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_CEC_OFFSET (0) ++ ++#define REG_CKG_CEC_RX_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_CEC_RX_OFFSET (0) ++ ++#define REG_CKG_DDC_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_DDC_OFFSET (0) ++ ++#define REG_CKG_DVI_RAW0_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW0_OFFSET (4) ++ ++#define REG_CKG_DVI_RAW1_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_DVI_RAW1_OFFSET (8) ++ ++#define REG_CKG_DVI_RAW2_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_DVI_RAW2_OFFSET (0) ++ ++#define REG_CKG_HOTPLUG_BASE (REG_PM_SLEEP_CKG_BASE+0x24*4) ++#define REG_CKG_HOTPLUG_OFFSET (12) ++ ++#define REG_CKG_IR_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_IR_OFFSET (5) ++ ++#define REG_CKG_KREF_BASE (REG_PM_SLEEP_CKG_BASE+0x23*4) ++#define REG_CKG_KREF_OFFSET (12) ++ ++#define REG_CKG_MCU_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_MCU_PM_OFFSET (0) ++ ++#define REG_CKG_MIIC_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_MIIC_OFFSET (12) ++ ++#define REG_CKG_PM_SLEEP_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_PM_SLEEP_OFFSET (10) ++ ++#define REG_CKG_RTC_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_RTC_OFFSET (0) ++ ++#define REG_CKG_SAR_BASE (REG_PM_SLEEP_CKG_BASE+0x22*4) ++#define REG_CKG_SAR_OFFSET (5) ++ ++#define REG_CKG_SCDC_P0_BASE (REG_PM_SLEEP_CKG_BASE+0x26*4) ++#define REG_CKG_SCDC_P0_OFFSET (4) ++ ++#define REG_CKG_SD_BASE (REG_PM_SLEEP_CKG_BASE+0x21*4) ++#define REG_CKG_SD_OFFSET (10) ++ ++#define REG_CKG_SPI_PM_BASE (REG_PM_SLEEP_CKG_BASE+0x20*4) ++#define REG_CKG_SPI_PM_OFFSET (8) ++ ++ ++ ++//====NORMAL_CKG_REG============================================== ++#define REG_CKG_123M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_123M_2DIGPM_OFFSET (4) ++ ++#define REG_CKG_144M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_144M_2DIGPM_OFFSET (3) ++ ++#define REG_CKG_172M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_172M_2DIGPM_OFFSET (2) ++ ++#define REG_CKG_216M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_216M_2DIGPM_OFFSET (1) ++ ++#define REG_CKG_86M_2DIGPM_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_86M_2DIGPM_OFFSET (5) ++ ++#define REG_CKG_AESDMA_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_AESDMA_OFFSET (0) ++ ++#define REG_CKG_BDMA_BASE (REG_CKG_BASE+0x60*4) ++#define REG_CKG_BDMA_OFFSET (0) ++ ++#define REG_CKG_BIST_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_OFFSET (0) ++ ++#define REG_CKG_BIST_PM_BASE (REG_CKG_BASE+0x02*4) ++#define REG_CKG_BIST_PM_OFFSET (8) ++ ++#define REG_CKG_BIST_SC_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_SC_GP_OFFSET (0) ++ ++#define REG_CKG_BIST_VHE_GP_BASE (REG_CKG_BASE+0x03*4) ++#define REG_CKG_BIST_VHE_GP_OFFSET (8) ++ ++#define REG_CKG_BOOT_BASE (REG_CKG_BASE+0x08*4) ++#define REG_CKG_BOOT_OFFSET (0) ++ ++#define REG_CKG_CSI_MAC_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_CSI_MAC_OFFSET (0) ++ ++#define REG_CKG_DDR_SYN_BASE (REG_CKG_BASE+0x19*4) ++#define REG_CKG_DDR_SYN_OFFSET (0) ++ ++#define REG_CKG_ECC_BASE (REG_CKG_BASE+0x44*4) ++#define REG_CKG_ECC_OFFSET (0) ++ ++#define REG_CKG_EMAC_AHB_BASE (REG_CKG_BASE+0x42*4) ++#define REG_CKG_EMAC_AHB_OFFSET (0) ++ ++#define REG_CKG_FCIE_BASE (REG_CKG_BASE+0x43*4) ++#define REG_CKG_FCIE_OFFSET (0) ++ ++#define REG_CKG_FCLK1_BASE (REG_CKG_BASE+0x64*4) ++#define REG_CKG_FCLK1_OFFSET (0) ++ ++#define REG_CKG_FCLK2_BASE (REG_CKG_BASE+0x65*4) ++#define REG_CKG_FCLK2_OFFSET (0) ++ ++#define REG_CKG_FUART_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART_OFFSET (0) ++ ++#define REG_CKG_FUART0_SYNTH_IN_BASE (REG_CKG_BASE+0x34*4) ++#define REG_CKG_FUART0_SYNTH_IN_OFFSET (4) ++ ++#define REG_CKG_GOP_BASE (REG_CKG_BASE+0x67*4) ++#define REG_CKG_GOP_OFFSET (0) ++ ++#define REG_CKG_HEMCU_216M_BASE (REG_CKG_BASE+0x6D*4) ++#define REG_CKG_HEMCU_216M_OFFSET (0) ++ ++#define REG_CKG_IDCLK_BASE (REG_CKG_BASE+0x63*4) ++#define REG_CKG_IDCLK_OFFSET (0) ++ ++#define REG_CKG_ISP_BASE (REG_CKG_BASE+0x61*4) ++#define REG_CKG_ISP_OFFSET (8) ++ ++#define REG_CKG_IVE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_IVE_OFFSET (8) ++ ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++#define REG_CKG_JPE_OFFSET (0) ++ ++#define REG_CKG_LIVE_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_LIVE_OFFSET (8) ++ ++#define REG_CKG_MAC_LPTX_BASE (REG_CKG_BASE+0x6C*4) ++#define REG_CKG_MAC_LPTX_OFFSET (8) ++ ++#define REG_CKG_MCU_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_MCU_OFFSET (0) ++ ++#define REG_CKG_MFE_BASE (REG_CKG_BASE+0x69*4) ++#define REG_CKG_MFE_OFFSET (0) ++ ++#define REG_CKG_MIIC0_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC0_OFFSET (0) ++ ++#define REG_CKG_MIIC1_BASE (REG_CKG_BASE+0x37*4) ++#define REG_CKG_MIIC1_OFFSET (8) ++ ++#define REG_CKG_MIU_BASE (REG_CKG_BASE+0x17*4) ++#define REG_CKG_MIU_OFFSET (0) ++ ++#define REG_CKG_MIU_BOOT_BASE (REG_CKG_BASE+0x20*4) ++#define REG_CKG_MIU_BOOT_OFFSET (0) ++ ++#define REG_CKG_MIU_REC_BASE (REG_CKG_BASE+0x18*4) ++#define REG_CKG_MIU_REC_OFFSET (0) ++ ++#define REG_CKG_MSPI0_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI0_OFFSET (0) ++ ++#define REG_CKG_MSPI1_BASE (REG_CKG_BASE+0x33*4) ++#define REG_CKG_MSPI1_OFFSET (8) ++ ++#define REG_CKG_NS_BASE (REG_CKG_BASE+0x6B*4) ++#define REG_CKG_NS_OFFSET (0) ++ ++#define REG_CKG_ODCLK_BASE (REG_CKG_BASE+0x66*4) ++#define REG_CKG_ODCLK_OFFSET (0) ++ ++#define REG_CKG_RIUBRDG_BASE (REG_CKG_BASE+0x01*4) ++#define REG_CKG_RIUBRDG_OFFSET (8) ++ ++#define REG_CKG_SDIO_BASE (REG_CKG_BASE+0x45*4) ++#define REG_CKG_SDIO_OFFSET (0) ++ ++#define REG_CKG_SPI_BASE (REG_CKG_BASE+0x32*4) ++#define REG_CKG_SPI_OFFSET (0) ++ ++#define REG_CKG_SR_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_OFFSET (0) ++ ++#define REG_CKG_SR_MCLK_BASE (REG_CKG_BASE+0x62*4) ++#define REG_CKG_SR_MCLK_OFFSET (8) ++ ++#define REG_CKG_TCK_BASE (REG_CKG_BASE+0x30*4) ++#define REG_CKG_TCK_OFFSET (0) ++ ++#define REG_CKG_UART0_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART0_OFFSET (0) ++ ++#define REG_CKG_UART1_BASE (REG_CKG_BASE+0x31*4) ++#define REG_CKG_UART1_OFFSET (8) ++ ++#define REG_CKG_VHE_BASE (REG_CKG_BASE+0x68*4) ++#define REG_CKG_VHE_OFFSET (0) ++ ++#define REG_CKG_XTALI_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_OFFSET (0) ++ ++#define REG_CKG_XTALI_SC_GP_BASE (REG_CKG_BASE+0x00*4) ++#define REG_CKG_XTALI_SC_GP_OFFSET (4) ++ ++#define REG_CLKGEN0_RESERVED0_BASE (REG_CKG_BASE+0x7E*4) ++#define REG_CLKGEN0_RESERVED0_OFFSET (0) ++ ++#define REG_CLKGEN0_RESERVED1_BASE (REG_CKG_BASE+0x7F*4) ++#define REG_CLKGEN0_RESERVED1_OFFSET (0) ++ ++#define REG_MPLL_123_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_123_EN_RD_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_123_FORCE_OFF_OFFSET (12) ++ ++#define REG_MPLL_123_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_123_FORCE_ON_OFFSET (12) ++ ++#define REG_MPLL_124_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_124_EN_RD_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_124_FORCE_OFF_OFFSET (13) ++ ++#define REG_MPLL_124_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_124_FORCE_ON_OFFSET (13) ++ ++#define REG_MPLL_144_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_144_EN_RD_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_144_FORCE_OFF_OFFSET (11) ++ ++#define REG_MPLL_144_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_144_FORCE_ON_OFFSET (11) ++ ++#define REG_MPLL_172_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_172_EN_RD_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_172_FORCE_OFF_OFFSET (10) ++ ++#define REG_MPLL_172_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_172_FORCE_ON_OFFSET (10) ++ ++#define REG_MPLL_216_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_216_EN_RD_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_216_FORCE_OFF_OFFSET (9) ++ ++#define REG_MPLL_216_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_216_FORCE_ON_OFFSET (9) ++ ++#define REG_MPLL_288_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_288_EN_RD_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_288_FORCE_OFF_OFFSET (8) ++ ++#define REG_MPLL_288_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_288_FORCE_ON_OFFSET (8) ++ ++#define REG_MPLL_345_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_345_EN_RD_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_345_FORCE_OFF_OFFSET (7) ++ ++#define REG_MPLL_345_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_345_FORCE_ON_OFFSET (7) ++ ++#define REG_MPLL_432_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_432_EN_RD_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_432_FORCE_OFF_OFFSET (6) ++ ++#define REG_MPLL_432_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_432_FORCE_ON_OFFSET (6) ++ ++#define REG_MPLL_86_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_MPLL_86_EN_RD_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_MPLL_86_FORCE_OFF_OFFSET (14) ++ ++#define REG_MPLL_86_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_MPLL_86_FORCE_ON_OFFSET (14) ++ ++#define REG_PLL_GATER_FORCE_OFF_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_OFF_LOCK_OFFSET (1) ++ ++#define REG_PLL_GATER_FORCE_ON_LOCK_BASE (REG_CKG_BASE+0x70*4) ++#define REG_PLL_GATER_FORCE_ON_LOCK_OFFSET (0) ++ ++#define REG_PLL_RV1_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_PLL_RV1_FORCE_OFF_OFFSET (15) ++ ++#define REG_PLL_RV1_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_PLL_RV1_FORCE_ON_OFFSET (15) ++ ++#define REG_UART_STNTHESIZER_ENABLE_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_ENABLE_OFFSET (8) ++ ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_BASE (REG_CKG_BASE+0x36*4) ++#define REG_UART_STNTHESIZER_FIX_NF_FREQ_OFFSET (0) ++ ++#define REG_UART_STNTHESIZER_SW_RSTZ_BASE (REG_CKG_BASE+0x34*4) ++#define REG_UART_STNTHESIZER_SW_RSTZ_OFFSET (9) ++ ++#define REG_UPLL_320_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_320_EN_RD_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_320_FORCE_OFF_OFFSET (1) ++ ++#define REG_UPLL_320_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_320_FORCE_ON_OFFSET (1) ++ ++#define REG_UPLL_384_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UPLL_384_EN_RD_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UPLL_384_FORCE_OFF_OFFSET (0) ++ ++#define REG_UPLL_384_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UPLL_384_FORCE_ON_OFFSET (0) ++ ++#define REG_UTMI_160_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_160_EN_RD_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_160_FORCE_OFF_OFFSET (2) ++ ++#define REG_UTMI_160_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_160_FORCE_ON_OFFSET (2) ++ ++#define REG_UTMI_192_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_192_EN_RD_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_192_FORCE_OFF_OFFSET (3) ++ ++#define REG_UTMI_192_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_192_FORCE_ON_OFFSET (3) ++ ++#define REG_UTMI_240_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_240_EN_RD_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_240_FORCE_OFF_OFFSET (4) ++ ++#define REG_UTMI_240_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_240_FORCE_ON_OFFSET (4) ++ ++#define REG_UTMI_480_EN_RD_BASE (REG_CKG_BASE+0x73*4) ++#define REG_UTMI_480_EN_RD_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_OFF_BASE (REG_CKG_BASE+0x72*4) ++#define REG_UTMI_480_FORCE_OFF_OFFSET (5) ++ ++#define REG_UTMI_480_FORCE_ON_BASE (REG_CKG_BASE+0x71*4) ++#define REG_UTMI_480_FORCE_ON_OFFSET (5) ++ ++ ++#endif +diff --git a/drivers/mstar/include/infinity3/registers.h b/drivers/mstar/include/infinity3/registers.h +new file mode 100644 +index 00000000..3e2e3e6a +--- /dev/null ++++ b/drivers/mstar/include/infinity3/registers.h +@@ -0,0 +1,215 @@ ++#ifndef ___REGS_H ++#define ___REGS_H ++ ++#include "ms_types.h" ++ ++#define MIU0_BASE 0x20000000 ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define SPI_PHYS 0x14000000 ++#define SPI_VIRT (SPI_PHYS+SPI_OFFSET) //from IO_ADDRESS(x) ++#define SPI_OFFSET (MS_IO_OFFSET) ++#define SPI_SIZE 0x02000000 ++ ++#define GIC_PHYS 0x16000000 ++#define GIC_VIRT (GIC_PHYS+GIC_OFFSET) //from IO_ADDRESS(x) ++#define GIC_OFFSET (MS_IO_OFFSET) ++#define GIC_SIZE 0x4000 ++ ++#define IMI_PHYS 0xA0000000 ++#define IMI_VIRT 0xF9000000 ++#define IMI_OFFSET (IMI_VIRT-IMI_PHYS) ++#define IMI_SIZE 0x10000 ++ ++ ++ ++#define BASE_REG_RIU_PA 0x1F000000 ++#define BK_REG(reg) ((reg) << 2) ++ ++#define BASE_REG_CHIPTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101E00) ++#define BASE_REG_PMSLEEP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0E00) ++#define BASE_REG_PMGPIO_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x0F00) ++#define BASE_REG_PMRTC_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1200) ++#define BASE_REG_PMSAR_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1400) ++#define BASE_REG_PMTOP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x1E00) ++#define BASE_REG_INTRCTL_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100900) ++#define BASE_REG_DIDKEY_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x3800) ++#define BASE_REG_MIU_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x101200) ++#define BASE_REG_MCM_DIG_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113000) ++#define BASE_REG_MCM_SC_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113200) ++#define BASE_REG_MCM_VHE_GP_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x113400) ++#define BASE_REG_UPLL0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142000) ++#define BASE_REG_UTMI0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142100) ++#define BASE_REG_USB0_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x142300) ++#define BASE_REG_EFUSE_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x2000) ++#define BASE_REG_MAILBOX_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100400) ++#define BASE_REG_BDMA1_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x100220) ++#define BASE_REG_CLKGEN_PA GET_BASE_ADDR_BY_BANK(BASE_REG_RIU_PA, 0x103800) ++ ++ ++#define REG_ADDR_STATUS (BASE_REG_PMRTC_PA + REG_ID_04) ++#define FORCE_UBOOT_BIT BIT15 ++ ++ ++#define REG_ID_00 BK_REG(0x00) ++#define REG_ID_01 BK_REG(0x01) ++#define REG_ID_02 BK_REG(0x02) ++#define REG_ID_03 BK_REG(0x03) ++#define REG_ID_04 BK_REG(0x04) ++#define REG_ID_05 BK_REG(0x05) ++#define REG_ID_06 BK_REG(0x06) ++#define REG_ID_07 BK_REG(0x07) ++#define REG_ID_08 BK_REG(0x08) ++#define REG_ID_09 BK_REG(0x09) ++#define REG_ID_0A BK_REG(0x0A) ++#define REG_ID_0B BK_REG(0x0B) ++#define REG_ID_0C BK_REG(0x0C) ++#define REG_ID_0D BK_REG(0x0D) ++#define REG_ID_0E BK_REG(0x0E) ++#define REG_ID_0F BK_REG(0x0F) ++ ++ ++#define REG_ID_10 BK_REG(0x10) ++#define REG_ID_11 BK_REG(0x11) ++#define REG_ID_12 BK_REG(0x12) ++#define REG_ID_13 BK_REG(0x13) ++#define REG_ID_14 BK_REG(0x14) ++#define REG_ID_15 BK_REG(0x15) ++#define REG_ID_16 BK_REG(0x16) ++#define REG_ID_17 BK_REG(0x17) ++#define REG_ID_18 BK_REG(0x18) ++#define REG_ID_19 BK_REG(0x19) ++#define REG_ID_1A BK_REG(0x1A) ++#define REG_ID_1B BK_REG(0x1B) ++#define REG_ID_1C BK_REG(0x1C) ++#define REG_ID_1D BK_REG(0x1D) ++#define REG_ID_1E BK_REG(0x1E) ++#define REG_ID_1F BK_REG(0x1F) ++ ++#define REG_ID_20 BK_REG(0x20) ++#define REG_ID_21 BK_REG(0x21) ++#define REG_ID_22 BK_REG(0x22) ++#define REG_ID_23 BK_REG(0x23) ++#define REG_ID_24 BK_REG(0x24) ++#define REG_ID_25 BK_REG(0x25) ++#define REG_ID_26 BK_REG(0x26) ++#define REG_ID_27 BK_REG(0x27) ++#define REG_ID_28 BK_REG(0x28) ++#define REG_ID_29 BK_REG(0x29) ++#define REG_ID_2A BK_REG(0x2A) ++#define REG_ID_2B BK_REG(0x2B) ++#define REG_ID_2C BK_REG(0x2C) ++#define REG_ID_2D BK_REG(0x2D) ++#define REG_ID_2E BK_REG(0x2E) ++#define REG_ID_2F BK_REG(0x2F) ++ ++ ++#define REG_ID_30 BK_REG(0x30) ++#define REG_ID_31 BK_REG(0x31) ++#define REG_ID_32 BK_REG(0x32) ++#define REG_ID_33 BK_REG(0x33) ++#define REG_ID_34 BK_REG(0x34) ++#define REG_ID_35 BK_REG(0x35) ++#define REG_ID_36 BK_REG(0x36) ++#define REG_ID_37 BK_REG(0x37) ++#define REG_ID_38 BK_REG(0x38) ++#define REG_ID_39 BK_REG(0x39) ++#define REG_ID_3A BK_REG(0x3A) ++#define REG_ID_3B BK_REG(0x3B) ++#define REG_ID_3C BK_REG(0x3C) ++#define REG_ID_3D BK_REG(0x3D) ++#define REG_ID_3E BK_REG(0x3E) ++#define REG_ID_3F BK_REG(0x3F) ++ ++ ++#define REG_ID_40 BK_REG(0x40) ++#define REG_ID_41 BK_REG(0x41) ++#define REG_ID_42 BK_REG(0x42) ++#define REG_ID_43 BK_REG(0x43) ++#define REG_ID_44 BK_REG(0x44) ++#define REG_ID_45 BK_REG(0x45) ++#define REG_ID_46 BK_REG(0x46) ++#define REG_ID_47 BK_REG(0x47) ++#define REG_ID_48 BK_REG(0x48) ++#define REG_ID_49 BK_REG(0x49) ++#define REG_ID_4A BK_REG(0x4A) ++#define REG_ID_4B BK_REG(0x4B) ++#define REG_ID_4C BK_REG(0x4C) ++#define REG_ID_4D BK_REG(0x4D) ++#define REG_ID_4E BK_REG(0x4E) ++#define REG_ID_4F BK_REG(0x4F) ++ ++ ++#define REG_ID_50 BK_REG(0x50) ++#define REG_ID_51 BK_REG(0x51) ++#define REG_ID_52 BK_REG(0x52) ++#define REG_ID_53 BK_REG(0x53) ++#define REG_ID_54 BK_REG(0x54) ++#define REG_ID_55 BK_REG(0x55) ++#define REG_ID_56 BK_REG(0x56) ++#define REG_ID_57 BK_REG(0x57) ++#define REG_ID_58 BK_REG(0x58) ++#define REG_ID_59 BK_REG(0x59) ++#define REG_ID_5A BK_REG(0x5A) ++#define REG_ID_5B BK_REG(0x5B) ++#define REG_ID_5C BK_REG(0x5C) ++#define REG_ID_5D BK_REG(0x5D) ++#define REG_ID_5E BK_REG(0x5E) ++#define REG_ID_5F BK_REG(0x5F) ++ ++ ++#define REG_ID_60 BK_REG(0x60) ++#define REG_ID_61 BK_REG(0x61) ++#define REG_ID_62 BK_REG(0x62) ++#define REG_ID_63 BK_REG(0x63) ++#define REG_ID_64 BK_REG(0x64) ++#define REG_ID_65 BK_REG(0x65) ++#define REG_ID_66 BK_REG(0x66) ++#define REG_ID_67 BK_REG(0x67) ++#define REG_ID_68 BK_REG(0x68) ++#define REG_ID_69 BK_REG(0x69) ++#define REG_ID_6A BK_REG(0x6A) ++#define REG_ID_6B BK_REG(0x6B) ++#define REG_ID_6C BK_REG(0x6C) ++#define REG_ID_6D BK_REG(0x6D) ++#define REG_ID_6E BK_REG(0x6E) ++#define REG_ID_6F BK_REG(0x6F) ++ ++ ++#define REG_ID_70 BK_REG(0x70) ++#define REG_ID_71 BK_REG(0x71) ++#define REG_ID_72 BK_REG(0x72) ++#define REG_ID_73 BK_REG(0x73) ++#define REG_ID_74 BK_REG(0x74) ++#define REG_ID_75 BK_REG(0x75) ++#define REG_ID_76 BK_REG(0x76) ++#define REG_ID_77 BK_REG(0x77) ++#define REG_ID_78 BK_REG(0x78) ++#define REG_ID_79 BK_REG(0x79) ++#define REG_ID_7A BK_REG(0x7A) ++#define REG_ID_7B BK_REG(0x7B) ++#define REG_ID_7C BK_REG(0x7C) ++#define REG_ID_7D BK_REG(0x7D) ++#define REG_ID_7E BK_REG(0x7E) ++#define REG_ID_7F BK_REG(0x7F) ++ ++typedef enum ++{ ++ MS_I3_PACKAGE_UNKNOWN =0x00, ++ MS_I3_PACKAGE_QFN_DDR2_32MB, ++ MS_I3_PACKAGE_QFN_DDR2_64MB, ++ MS_I3_PACKAGE_BGA_128MB, ++ MS_I3_PACKAGE_BGA_256MB, ++ MS_I3_PACKAGE_QFN_DDR3_128MB, ++ MS_I3_PACKAGE_EXTENDED=0x30, ++ MS_I3_PACKAGE_DDR3_1866_128MB =0x30, ++ MS_I3_PACKAGE_DDR3_1866_256MB, ++ MS_I3_PACKAGE_FPGA_128MB =0x90, ++} MS_I3_PACKAGE_TYPE; ++ ++ ++#endif +diff --git a/drivers/mstar/include/mdrv_API_version.h b/drivers/mstar/include/mdrv_API_version.h +new file mode 100644 +index 00000000..612bc115 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_API_version.h +@@ -0,0 +1 @@ ++#define KL_API_VERSION "1.0.0" +diff --git a/drivers/mstar/include/mdrv_crypto_io.h b/drivers/mstar/include/mdrv_crypto_io.h +new file mode 100644 +index 00000000..ddfc6a5a +--- /dev/null ++++ b/drivers/mstar/include/mdrv_crypto_io.h +@@ -0,0 +1,34 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++/////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_aesdma_io.h ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef _MDRV_AESDMA_IO_H ++#define _MDRV_AESDMA_IO_H ++ ++#define IOCTL_AESDMA_GSESSION (102) ++#define IOCTL_AESDMA_FSESSION (103) ++#define IOCTL_AESDMA_CRYPT (104) ++ ++#define CIOCGSESSION _IO('c', IOCTL_AESDMA_GSESSION) ++#define CIOCFSESSION _IO('c', IOCTL_AESDMA_FSESSION) ++#define CIOCCRYPT _IO('c', IOCTL_AESDMA_CRYPT) ++ ++ ++#endif +diff --git a/drivers/mstar/include/mdrv_crypto_io_st.h b/drivers/mstar/include/mdrv_crypto_io_st.h +new file mode 100644 +index 00000000..943e128d +--- /dev/null ++++ b/drivers/mstar/include/mdrv_crypto_io_st.h +@@ -0,0 +1,133 @@ ++#ifndef _MDRV_AESDMA_IO_ST_H ++#define _MDRV_AESDMA_IO_ST_H ++ ++#include ++#ifndef __KERNEL__ ++#define __user ++#endif ++ ++/* API extensions for linux */ ++#define CRYPTO_HMAC_MAX_KEY_LEN 512 ++#define CRYPTO_CIPHER_MAX_KEY_LEN 64 ++ ++/* All the supported algorithms ++ */ ++ ++enum cryptodev_crypto_op_t { ++ CRYPTO_RIJNDAEL128_CBC = 1, ++ CRYPTO_AES_CBC = CRYPTO_RIJNDAEL128_CBC, ++ CRYPTO_SHA1 = 2, ++ CRYPTO_AES_CTR = 3, ++ CRYPTO_AES_ECB = 4, ++ CRYPTO_SHA2_256, ++ CRYPTO_ALGORITHM_ALL, /* Keep updated - see below */ ++ /*CRYPTO_RIJNDAEL128_CBC = 1, ++ CRYPTO_AES_CBC = CRYPTO_RIJNDAEL128_CBC, ++ CRYPTO_AES_CTR = 2, ++ CRYPTO_AES_ECB = 3, ++ CRYPTO_DES_CBC = 4, ++ CRYPTO_DES_CTR = 5, ++ CRYPTO_DES_ECB = 6, ++ CRYPTO_TDES_CBC = 7, ++ CRYPTO_TDES_CTR = 8, ++ CRYPTO_TDES_ECB = 9, ++ CRYPTO_SHA1 = 10, ++ CRYPTO_SHA2_256 = 11, ++ CRYPTO_ARC4 = 12, ++ CRYPTO_MD5 = 13, ++ CRYPTO_CAMELLIA_CBC = 101, ++ CRYPTO_BLF_CBC = 102, ++ CRYPTO_ALGORITHM_ALL,*/ /* Keep updated - see below */ ++}; ++#define CRYPTO_ALGORITHM_MAX (CRYPTO_ALGORITHM_ALL - 1) ++ ++/* Values for ciphers */ ++#define DES_BLOCK_LEN 8 ++#define DES3_BLOCK_LEN 8 ++#define RIJNDAEL128_BLOCK_LEN 16 ++#define AES_BLOCK_LEN RIJNDAEL128_BLOCK_LEN ++#define CAMELLIA_BLOCK_LEN 16 ++#define BLOWFISH_BLOCK_LEN 8 ++#define SKIPJACK_BLOCK_LEN 8 ++#define CAST128_BLOCK_LEN 8 ++ ++/* the maximum of the above */ ++#define EALG_MAX_BLOCK_LEN 16 ++ ++/* Values for hashes/MAC */ ++#define AALG_MAX_RESULT_LEN 64 ++ ++/* maximum length of verbose alg names (depends on CRYPTO_MAX_ALG_NAME) */ ++#define CRYPTODEV_MAX_ALG_NAME 64 ++ ++#define HASH_MAX_LEN 64 ++ ++/* input of CIOCGSESSION */ ++struct session_op { ++ /* Specify either cipher or mac ++ */ ++ __u32 cipher; /* cryptodev_crypto_op_t */ ++ __u32 mac; /* cryptodev_crypto_op_t */ ++ ++ __u32 keylen; ++ __u8 __user *key; ++ __u32 mackeylen; ++ __u8 __user *mackey; ++ ++ __u32 ses; /* session identifier */ ++}; ++ ++struct session_info_op { ++ __u32 ses; /* session identifier */ ++ ++ /* verbose names for the requested ciphers */ ++ struct alg_info { ++ char cra_name[CRYPTODEV_MAX_ALG_NAME]; ++ char cra_driver_name[CRYPTODEV_MAX_ALG_NAME]; ++ } cipher_info, hash_info; ++ ++ __u16 alignmask; /* alignment constraints */ ++ __u32 flags; /* SIOP_FLAGS_* */ ++}; ++ ++/* If this flag is set then this algorithm uses ++ * a driver only available in kernel (software drivers, ++ * or drivers based on instruction sets do not set this flag). ++ * ++ * If multiple algorithms are involved (as in AEAD case), then ++ * if one of them is kernel-driver-only this flag will be set. ++ */ ++#define SIOP_FLAG_KERNEL_DRIVER_ONLY 1 ++#define COP_ENCRYPT 0 ++#define COP_DECRYPT 1 ++/* input of CIOCCRYPT */ ++struct crypt_op { ++ __u32 ses; /* session identifier */ ++ __u16 op; /* COP_ENCRYPT or COP_DECRYPT */ ++ __u16 flags; /* see COP_FLAG_* */ ++ __u32 len; /* length of source data */ ++ __u8 __user *src; /* source data */ ++ __u8 __user *dst; /* pointer to output data */ ++ /* pointer to output data for hash/MAC operations */ ++ __u8 __user *mac; ++ /* initialization vector for encryption operations */ ++ __u8 __user *iv; ++}; ++ ++/* struct crypt_op flags */ ++#define COP_FLAG_NONE (0 << 0) /* totally no flag */ ++#define COP_FLAG_UPDATE (1 << 0) /* multi-update hash mode */ ++#define COP_FLAG_FINAL (1 << 1) /* multi-update final hash mode */ ++#define COP_FLAG_WRITE_IV (1 << 2) /* update the IV during operation */ ++#define COP_FLAG_NO_ZC (1 << 3) /* do not zero-copy */ ++#define COP_FLAG_AEAD_TLS_TYPE (1 << 4) /* authenticate and encrypt using the ++ * TLS protocol rules */ ++#define COP_FLAG_AEAD_SRTP_TYPE (1 << 5) /* authenticate and encrypt using the ++ * SRTP protocol rules */ ++#define COP_FLAG_RESET (1 << 6) /* multi-update reset the state. ++ * should be used in combination ++ * with COP_FLAG_UPDATE */ ++#define CRK_MAXPARAM 8 ++#define CRK_ALGORITHM_MAX (CRK_ALGORITHM_ALL-1) ++ ++#endif +\ No newline at end of file +diff --git a/drivers/mstar/include/mdrv_device_id.h b/drivers/mstar/include/mdrv_device_id.h +new file mode 100644 +index 00000000..a6028583 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_device_id.h +@@ -0,0 +1,62 @@ ++#ifndef __MDRV_DEVICE_ID_H__ ++#define __MDRV_DEVICE_ID_H__ ++ ++typedef enum ++{ ++CHIP_REVISION_U01=0x00, ++CHIP_REVISION_U02, ++CHIP_REVISION_U03, ++CHIP_REVISION_U04, ++CHIP_REVISION_U05, ++CHIP_REVISION_U06, ++CHIP_REVISION_U07, ++CHIP_REVISION_U08, ++CHIP_REVISION_U09, ++CHIP_REVISION_U0A, ++CHIP_REVISION_U0B, ++CHIP_REVISION_U0C, ++CHIP_REVISION_U0D, ++CHIP_REVISION_U0E, ++CHIP_REVISION_U0F, ++CHIP_REVISION_U10, ++CHIP_REVISION_U11, ++CHIP_REVISION_U12, ++CHIP_REVISION_U13, ++CHIP_REVISION_U14, ++CHIP_REVISION_U15, ++CHIP_REVISION_U16, ++CHIP_REVISION_U17, ++CHIP_REVISION_U18, ++CHIP_REVISION_U19, ++CHIP_REVISION_U1A, ++CHIP_REVISION_U1B, ++CHIP_REVISION_U1C, ++CHIP_REVISION_U1D, ++CHIP_REVISION_U1E, ++CHIP_REVISION_U1F, ++CHIP_REVISION_END=0xFF ++ ++}MS_CHIP_REVISION; ++ ++ ++ ++typedef enum ++{ ++DEVICE_ID_CEDRIC = (0x50), ++DEVICE_ID_CHICAGO = (0x70), ++DEVICE_ID_INFINITY = (0xAE), ++DEVICE_ID_END=0xFFFFFFFF ++}MS_DEVICE_ID; ++ ++#define PLATFORM_NAME_CEDRIC "C3" ++#define PLATFORM_NAME_CHICAGO "C4" ++#define PLATFORM_NAME_INFINITY "I1" ++#define PLATFORM_NAME_INFINITY3 "I3" ++ ++ ++ ++#define KERNEL_310_VER "3.10" ++#define KERNEL_318_VER "3.18" ++ ++ ++#endif +diff --git a/drivers/mstar/include/mdrv_dip_io.h b/drivers/mstar/include/mdrv_dip_io.h +new file mode 100644 +index 00000000..c2d8d350 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_dip_io.h +@@ -0,0 +1,62 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_DIP_IO_H ++#define _MDRV_DIP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_DIP_LIB_CODE {'D','I','P','\0'} ++#define MSIF_DIP_BUILDNUM {'_','0','1','\0'} ++#define MSIF_DIP_LIBVER (2) ++#define MSIF_DIP_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++ ++#define IOCTL_DIP_SET_INTERRUP_NR (0) ++#define IOCTL_DIP_SET_CONFIG_NR (1) ++#define IOCTL_DIP_SET_WONCE_BASE_CONFIG_NR (2) ++#define IOCTL_DIP_GET_INTERRUPT_STATUS_NR (3) ++#define IOCTL_DIP_MAX_NR (4) ++ ++ ++// use 'm' as magic number ++#define IOCTL_DIP_MAGIC ('3') ++ ++ ++#define IOCTL_DIP_SET_INTERRUPT _IO(IOCTL_DIP_MAGIC, IOCTL_DIP_SET_INTERRUP_NR) ++#define IOCTL_DIP_SET_CONFIG _IO(IOCTL_DIP_MAGIC, IOCTL_DIP_SET_CONFIG_NR) ++#define IOCTL_DIP_SET_WONCE_BASE_CONFIG _IO(IOCTL_DIP_MAGIC, IOCTL_DIP_SET_WONCE_BASE_CONFIG_NR) ++#define IOCTL_DIP_GET_INTERRUPT_STATUS _IO(IOCTL_DIP_MAGIC, IOCTL_DIP_GET_INTERRUPT_STATUS_NR) ++ ++ ++#endif //_MDRV_GFLIP_IO_H ++ ++ ++ +diff --git a/drivers/mstar/include/mdrv_dip_io_st.h b/drivers/mstar/include/mdrv_dip_io_st.h +new file mode 100644 +index 00000000..6b0bbe1f +--- /dev/null ++++ b/drivers/mstar/include/mdrv_dip_io_st.h +@@ -0,0 +1,104 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_DIP_IO_ST_H ++#define _MDRV_DIP_IO_ST_H ++ ++ ++//============================================================================= ++// enum ++//============================================================================= ++typedef enum ++{ ++ DIP_DEST_FMT_YC422, ++ DIP_DEST_FMT_RGB565, ++ DIP_DEST_FMT_ARGB8888, ++ DIP_DEST_FMT_YC420_MVOP, ++ DIP_DEST_FMT_YC420_MFE, ++}DIP_DEST_FMT_TYPE; ++ ++ ++typedef enum ++{ ++ DIP_TRIGGER_LOOP = 0, ++ DIP_TRIGGER_ONCE, ++}DIP_TRIGGER_TYPE; ++ ++//============================================================================= ++// struct ++//============================================================================= ++typedef struct ++{ ++ unsigned char bEn; ++ unsigned long u32DIPW_Signal_PID; ++}DIP_INTERRUPT_CONFIG; ++ ++typedef struct ++{ ++ unsigned short x; ++ unsigned short y; /// ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Capability ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++struct GPIO_Reg ++{ ++ U32 u32Reg; ++ U8 u8Enable; ++ U8 u8BitMsk; ++} __attribute__ ((packed)); ++ ++typedef struct GPIO_Reg GPIO_Reg_t; ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define IOCTL_GPIO_INIT_NR (0) ++#define IOCTL_GPIO_SET_NR (1) ++#define IOCTL_GPIO_OEN_NR (2) ++#define IOCTL_GPIO_ODN_NR (3) ++#define IOCTL_GPIO_READ_NR (4) ++#define IOCTL_GPIO_PULL_HIGH_NR (5) ++#define IOCTL_GPIO_PULL_LOW_NR (6) ++#define IOCTL_GPIO_INOUT_NR (7) ++#define IOCTL_GPIO_WREGB_NR (8) ++ ++#define GPIO_IOC_MAGIC 'g' ++#define IOCTL_GPIO_INIT _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_INIT_NR) ++#define IOCTL_GPIO_SET _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_SET_NR) ++#define IOCTL_GPIO_OEN _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_OEN_NR) ++#define IOCTL_GPIO_ODN _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_ODN_NR) ++#define IOCTL_GPIO_READ _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_READ_NR) ++#define IOCTL_GPIO_PULL_HIGH _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_PULL_HIGH_NR) ++#define IOCTL_GPIO_PULL_LOW _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_PULL_LOW_NR) ++#define IOCTL_GPIO_INOUT _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_INOUT_NR) ++#define IOCTL_GPIO_WREGB _IO(GPIO_IOC_MAGIC, IOCTL_GPIO_WREGB_NR) ++ ++#define GPIO_IOC_MAXNR 9 ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++void __mod_gpio_init(void); ++ +diff --git a/drivers/mstar/include/mdrv_hvsp_io.h b/drivers/mstar/include/mdrv_hvsp_io.h +new file mode 100644 +index 00000000..b452f3e3 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_hvsp_io.h +@@ -0,0 +1,127 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_hvsp_io.h ++ * @brief HVSP Driver IOCTL interface ++ */ ++ ++/** ++ * \defgroup hvsp_group HVSP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/clk ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W:control clk by explain. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckcrop ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print vsync count,err times W: if 0 close ptgen ,if echo 1 open check crop ,echo 2 open check hvsp and dma count ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ptgen ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W: if 0 close ptgen ,if echo 1 open static ptgen ,echo 2 open dynamic ptgen,echo 3 open scl time gen ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_H ++#define _MDRV_HVSP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++ ++#define IOCTL_HVSP_SET_IN_CONFIG_NR (0) ///< The IOCTL NR definition,IOCTL_HVSP_SET_IN_CONFIG ++#define IOCTL_HVSP_SET_OUT_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OUT_CONFIG ++#define IOCTL_HVSP_SET_SCALING_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_HVSP_SET_SCALING_CONFIG ++#define IOCTL_HVSP_REQ_MEM_CONFIG_NR (3) ///< The IOCTL NR definition,IOCTL_HVSP_REQ_MEM_CONFIG ++#define IOCTL_HVSP_SET_MISC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_HVSP_SET_MISC_CONFIG ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG_NR (5) ///< The IOCTL NR definition,IOCTL_HVSP_SET_POST_CROP_CONFIG ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ++#define IOCTL_HVSP_GET_INFORM_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_HVSP_GET_INFORM_CONFIG ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_HVSP_RELEASE_MEM_CONFIG ++#define IOCTL_HVSP_SET_OSD_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OSD_CONFIG ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_HVSP_SET_FB_MANAGE_CONFIG ++#define IOCLT_HVSP_GET_VERSION_CONFIG_NR (11) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_MAX_NR (12) ///< The Max IOCTL NR for hvsp driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_HVSP_MAGIC ('1')///< The Type definition of IOCTL for hvsp driver ++/** ++* Used to set Input MUX,capture window, use ST_IOCTL_HVSP_INPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_IN_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_IN_CONFIG_NR) ++/** ++* Used to set output configuration, use ST_IOCTL_HVSP_OUTPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OUT_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OUT_CONFIG_NR) ++/** ++* Used to set HVSP configuration and set post crop ,line,frame buffer size, use ST_IOCTL_HVSP_SCALING_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_SCALING_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_SCALING_CONFIG_NR) ++/** ++* Used to allocate DNR buffer and set framebuffer configuration, use ST_IOCTL_HVSP_REQ_MEM_CONFIG. ++*/ ++#define IOCTL_HVSP_REQ_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_REQ_MEM_CONFIG_NR) ++/** ++* Used to set register without interface, use ST_IOCTL_HVSP_MISC_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_MISC_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_MISC_CONFIG_NR) ++/** ++* Used to set post crop if need, use ST_IOCTL_HVSP_POSTCROP_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_POST_CROP_CONFIG_NR) ++/** ++* Used to get mutiinst private id, use ST_IOCTL_HVSP_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR) ++/** ++* Used to get display size and crop information, use ST_IOCTL_HVSP_SCINFORM_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_INFORM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_INFORM_CONFIG_NR) ++/** ++* Used to releace DNR buffer, use void. ++*/ ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_RELEASE_MEM_CONFIG_NR) ++/** ++* Used to Set OSD Configuration, use ST_IOCTL_HVSP_OSD_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OSD_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OSD_CONFIG_NR) ++/** ++* Used to Set FB Configuration,debug, use ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_HVSP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_VERSION_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCLT_HVSP_GET_VERSION_CONFIG_NR) ++ ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/mstar/include/mdrv_hvsp_io_i3.h b/drivers/mstar/include/mdrv_hvsp_io_i3.h +new file mode 100644 +index 00000000..412c190b +--- /dev/null ++++ b/drivers/mstar/include/mdrv_hvsp_io_i3.h +@@ -0,0 +1,137 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_hvsp_io.h ++ * @brief HVSP Driver IOCTL interface ++ */ ++ ++/** ++ * \defgroup hvsp_group HVSP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/clk ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W:control clk by explain. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckcrop ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print vsync count,err times W: if 0 close ptgen ,if echo 1 open check crop ,echo 2 open check hvsp and dma count ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ptgen ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:print explain W: if 0 close ptgen ,if echo 1 open static ptgen ,echo 2 open dynamic ptgen,echo 3 open scl time gen ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_H ++#define _MDRV_HVSP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++ ++#define IOCTL_HVSP_SET_IN_CONFIG_NR (0) ///< The IOCTL NR definition,IOCTL_HVSP_SET_IN_CONFIG ++#define IOCTL_HVSP_SET_OUT_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OUT_CONFIG ++#define IOCTL_HVSP_SET_SCALING_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_HVSP_SET_SCALING_CONFIG ++#define IOCTL_HVSP_REQ_MEM_CONFIG_NR (3) ///< The IOCTL NR definition,IOCTL_HVSP_REQ_MEM_CONFIG ++#define IOCTL_HVSP_SET_MISC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_HVSP_SET_MISC_CONFIG ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG_NR (5) ///< The IOCTL NR definition,IOCTL_HVSP_SET_POST_CROP_CONFIG ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ++#define IOCTL_HVSP_GET_INFORM_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_HVSP_GET_INFORM_CONFIG ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_HVSP_RELEASE_MEM_CONFIG ++#define IOCTL_HVSP_SET_OSD_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_HVSP_SET_OSD_CONFIG ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_HVSP_SET_FB_MANAGE_CONFIG ++#define IOCTL_HVSP_SET_PRIMASK_CONFIG_NR (11) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG_NR (12) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCLT_HVSP_GET_VERSION_CONFIG_NR (13) ///< The IOCTL NR definition, IOCLT_HVSP_GET_VERSION_CONFIG_NR ++#define IOCTL_HVSP_MAX_NR (IOCLT_HVSP_GET_VERSION_CONFIG_NR+1) ///< The Max IOCTL NR for hvsp driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_HVSP_MAGIC ('1')///< The Type definition of IOCTL for hvsp driver ++/** ++* Used to set Input MUX,capture window, use ST_IOCTL_HVSP_INPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_IN_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_IN_CONFIG_NR) ++/** ++* Used to set output configuration, use ST_IOCTL_HVSP_OUTPUT_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OUT_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OUT_CONFIG_NR) ++/** ++* Used to set HVSP configuration and set post crop ,line,frame buffer size, use ST_IOCTL_HVSP_SCALING_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_SCALING_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_SCALING_CONFIG_NR) ++/** ++* Used to allocate DNR buffer and set framebuffer configuration, use ST_IOCTL_HVSP_REQ_MEM_CONFIG. ++*/ ++#define IOCTL_HVSP_REQ_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_REQ_MEM_CONFIG_NR) ++/** ++* Used to set register without interface, use ST_IOCTL_HVSP_MISC_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_MISC_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_MISC_CONFIG_NR) ++/** ++* Used to set post crop if need, use ST_IOCTL_HVSP_POSTCROP_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_POST_CROP_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_POST_CROP_CONFIG_NR) ++/** ++* Used to get mutiinst private id, use ST_IOCTL_HVSP_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_PRIVATE_ID_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_PRIVATE_ID_CONFIG_NR) ++/** ++* Used to get display size and crop information, use ST_IOCTL_HVSP_SCINFORM_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_INFORM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_GET_INFORM_CONFIG_NR) ++/** ++* Used to releace DNR buffer, use void. ++*/ ++#define IOCTL_HVSP_RELEASE_MEM_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_RELEASE_MEM_CONFIG_NR) ++/** ++* Used to Set OSD Configuration, use ST_IOCTL_HVSP_OSD_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_OSD_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_OSD_CONFIG_NR) ++/** ++* Used to Set FB Configuration,debug, use ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_FB_MANAGE_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_FB_MANAGE_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_HVSP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_HVSP_GET_VERSION_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCLT_HVSP_GET_VERSION_CONFIG_NR) ++/** ++* Used to Set MASK Configuration, use ST_IOCTL_HVSP_PRIMASK_CONFIG. ++*/ ++#define IOCTL_HVSP_SET_PRIMASK_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_SET_PRIMASK_CONFIG_NR) ++/** ++* Used to Set MASK Trigger, use ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG. ++*/ ++#define IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG _IO(IOCTL_HVSP_MAGIC, IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG_NR) ++ ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/mstar/include/mdrv_hvsp_io_i3_st.h b/drivers/mstar/include/mdrv_hvsp_io_i3_st.h +new file mode 100644 +index 00000000..248aa5d9 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_hvsp_io_i3_st.h +@@ -0,0 +1,331 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_hvsp_io_st.h ++ * @brief hvsp Driver IOCTL parameter interface ++ */ ++ ++ /** ++ * \ingroup hvsp_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_HVSP_IO_ST_H ++#define _MDRV_HVSP_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++#define IOCTL_HVSP_VERSION 0x0100 ++ ++ ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to setup the input source of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_SRC_ISP, ///< input source: ISP ++ E_IOCTL_HVSP_SRC_BT656, ///< input source: BT656 ++ E_IOCTL_HVSP_SRC_DRAM, ///< input source: DRAM ++ E_IOCTL_HVSP_SRC_HVSP, ///< input source: HVSP1 ++ E_IOCTL_HVSP_SRC_PAT_TGEN, ///< input source: PATGEN ++ E_IOCTL_HVSP_SRC_NUM, ///< The max number of input source ++}EN_IOCTL_HVSP_SRC_TYPE; ++ ++/** ++* Used to setup the color format of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_COLOR_RGB, ///< color format:RGB ++ E_IOCTL_HVSP_COLOR_YUV444, ///< color format:YUV444 ++ E_IOCTL_HVSP_COLOR_YUV422, ///< color format:YUV422 ++ E_IOCTL_HVSP_COLOR_YUV420, ///< color format:YUV420 ++ E_IOCTL_HVSP_COLOR_NUM, ///< The max number of color format ++}EN_IOCTL_HVSP_COLOR_TYPE; ++ ++/** ++* Used to setup the IPR/W status of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_MCNR_YCM_R = 0x1, ///< IP only read ++ E_IOCTL_HVSP_MCNR_YCM_W = 0x2, ///< IP only write ++ E_IOCTL_HVSP_MCNR_YCM_RW = 0x3, ///< IP R/W ++ E_IOCTL_HVSP_MCNR_CIIR_R = 0x4, ///< IP only read ++ E_IOCTL_HVSP_MCNR_CIIR_W = 0x8, ///< IP only write ++ E_IOCTL_HVSP_MCNR_CIIR_RW = 0xC, ///< IP R/W ++ E_IOCTL_HVSP_MCNR_NON = 0x10, ///< IP none open ++}EN_IOCTL_HVSP_MCNR_TYPE; ++ ++/** ++* Used to setup the OSD locate of hvsp device ++*/ ++typedef enum ++{ ++ E_IOCTL_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ E_IOCTL_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_IOCTL_HVSP_OSD_LOC_TYPE; ++ ++/** ++* Used to setup the FB locate of hvsp device ++*/ ++typedef enum ++{ ++ EN_IOCTL_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_IOCTL_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_IOCTL_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_IOCTL_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++ EN_IOCTL_HVSP_FBMG_SET_PRVCROP_ON = 0x1000, ++ EN_IOCTL_HVSP_FBMG_SET_PRVCROP_OFF = 0x2000, ++ EN_IOCTL_HVSP_FBMG_SET_CIIR_ON = 0x4000, ++ EN_IOCTL_HVSP_FBMG_SET_CIIR_OFF = 0x8000, ++}EN_IOCTL_HVSP_FBMG_SET_TYPE; ++//============================================================================= ++// struct ++//============================================================================= ++/** ++* Used to get HVSP drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_VERSION_CONFIG; ++ ++/** ++* Used to setup the crop size of hvsp device ++*/ ++typedef struct ++{ ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop width size ++ unsigned short u16Height; ///< crop height size ++}__attribute__ ((__packed__))ST_IOCTL_HVSP_WINDOW_CONFIG; ++ ++/** ++* Used to setup the HVSP timing gen of hvsp device ++*/ ++typedef struct ++{ ++ unsigned char bInterlace; ///< is interlace or progressive ++ unsigned short u16Htotal; ///< Htt ++ unsigned short u16Vtotal; ///< Vtt ++ unsigned short u16Vfrequency; ///< Vfreq ++}ST_IOCTL_HVSPTIMING_CONFIG; ++ ++//============================================================================= ++// struct for IOCTL_HVSP_SET_IN_CONFIG ++/** ++* Used to setup the input mux ,input capture window of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ EN_IOCTL_HVSP_SRC_TYPE enSrcType; ///< Input source type ++ EN_IOCTL_HVSP_COLOR_TYPE enColor; ///< color type ++ ST_IOCTL_HVSP_WINDOW_CONFIG stCaptureWin; ///< Input Source Size(input src is scl capture win ++ ST_IOCTL_HVSPTIMING_CONFIG stTimingCfg; ///< Input Timing ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_INPUT_CONFIG; ++ ++ ++// struct for IOCTL_HVSP_SET_OUT_CONFIG ++/** ++* Used to setup the output config of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ EN_IOCTL_HVSP_COLOR_TYPE enColor; ///< color type ++ ST_IOCTL_HVSP_WINDOW_CONFIG stDisplayWin; ///< display window size ++ ST_IOCTL_HVSPTIMING_CONFIG stTimingCfg; ///< output timing ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_OUTPUT_CONFIG; ++/** ++* Used to set CLK mux of hvsp device ++*/ ++typedef struct ++{ ++ struct clk* idclk; ///< idclk ++ struct clk* fclk1; ///< fclk (SC1 SC2 ++ struct clk* fclk2; ///< fclk (SC3 ++ struct clk* odclk; ///< odclk (display Lpll ++}ST_IOCTL_HVSP_CLK_CONFIG; ++// sturct for IOCTL_HVSP_SET_SCALING_CONFIG ++/** ++* Used to setup the crop and HVSP123 scaling configuration of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Src_Width; ///< post crop IN width ++ unsigned short u16Src_Height; ///< post crop IN height ++ unsigned short u16Dsp_Width; ///< after HVSP width ++ unsigned short u16Dsp_Height; ///< after HVSP height ++ unsigned char bCropEn; ///< Is post crop En ++ ST_IOCTL_HVSP_WINDOW_CONFIG stCropWin; ///< post crop size ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_SCALING_CONFIG; ++ ++//IOCTL_HVSP_REQ_MEM_CONFIG ++/** ++* Used to allocate the buffer and setup framebuffer configuration of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned short u16Vsize; ///< framebuffer height ++ unsigned short u16Pitch; ///< framebuffer width ++ unsigned long u32MemSize; ///< height*width *2(YUV422) *2(2frame) ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_REQ_MEM_CONFIG; ++ ++//IOCTL_HVSP_SET_MISC_CONFIG ++/** ++* Used to setup the register of hvsp device ++*/ ++typedef struct ++{ ++ unsigned char u8Cmd; ///< register value ++ unsigned long u32Size; ///< number ++ unsigned long u32Addr; ///< bank&addr ++}__attribute__ ((__packed__))ST_IOCTL_HVSP_MISC_CONFIG; ++ ++//IOCTL HVSP_SET_POST_CROP_CONFIG ++/** ++* Used to setup the post crop of hvsp device if need ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned char bCropEn; ///< post crop En ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop frame width ++ unsigned short u16Height; ///< crop frame height ++ unsigned char bFmCntEn; ///< Is use CMDQ to set ++ unsigned char u8FmCnt; ///< when frame count ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_HVSP_POSTCROP_CONFIG; ++ ++//IOCTL HVSP_SET_POST_CROP_CONFIG ++/** ++* Used to get resolution information of hvsp device ++*/ ++typedef struct ++{ ++ unsigned short u16X; ///< x vs input src ++ unsigned short u16Y; ///< y vs input src ++ unsigned short u16Width; ///< display width ++ unsigned short u16Height; ///< display height ++ unsigned short u16crop2inWidth; ///< framebuffer width ++ unsigned short u16crop2inHeight;///< framebuffer height ++ unsigned short u16crop2OutWidth; ///< after crop width ++ unsigned short u16crop2OutHeight;///< after crop height ++}ST_IOCTL_HVSP_SCINFORM_CONFIG; ++ ++//IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ++/** ++* Used to get private ID of hvsp device ++*/ ++typedef struct ++{ ++ signed long s32Id; ///< private ID ++}ST_IOCTL_HVSP_PRIVATE_ID_CONFIG; ++ ++//IOCTL_HVSP_PRIMASK_CONFIG ++/** ++* Used to set MASK of hvsp device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned char bMask; /// ++#include ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ IVE_IOC_ERROR_NONE = 0x0000, ++ IVE_IOC_ERROR_IN_OUT_SIZE_DIFFERENT = 0x1000, ++ IVE_IOC_ERROR_IMG_TOO_SMALL = 0x1001, ++ IVE_IOC_ERROR_PROC_CONFIG = 0x1002, ++ IVE_IOC_ERROR_BUSY = 0x1003, ++ IVE_IOC_ERROR_MEMROY_FAILURE = 0x1004, ++ IVE_IOC_ERROR_CLK = 0x1005 ++} IVE_IOC_ERROR; ++ ++typedef enum ++{ ++ IVE_IOC_OP_TYPE_FILTER = 0x00, ++ IVE_IOC_OP_TYPE_CSC = 0x01, ++ IVE_IOC_OP_TYPE_FILTER_AND_CSC = 0x02, ++ IVE_IOC_OP_TYPE_SOBEL = 0x03, ++ IVE_IOC_OP_TYPE_MAG_AND_ANG = 0x04, ++ IVE_IOC_OP_TYPE_ORD_STA_FILTER = 0x05, ++ IVE_IOC_OP_TYPE_BERNSEN = 0x06, ++ IVE_IOC_OP_TYPE_DILATE = 0x07, ++ IVE_IOC_OP_TYPE_ERODE = 0x08, ++ IVE_IOC_OP_TYPE_THRESH = 0x09, ++ IVE_IOC_OP_TYPE_THRESH_S16 = 0x0A, ++ IVE_IOC_OP_TYPE_THRESH_U16 = 0x0B, ++ IVE_IOC_OP_TYPE_AND = 0x0C, ++ IVE_IOC_OP_TYPE_OR = 0x0D, ++ IVE_IOC_OP_TYPE_XOR = 0x0E, ++ IVE_IOC_OP_TYPE_ADD = 0x0F, ++ IVE_IOC_OP_TYPE_SUB = 0x10, ++ IVE_IOC_OP_TYPE_16BIT_TO_8BIT = 0x11, ++ IVE_IOC_OP_TYPE_MAP = 0x12, ++ IVE_IOC_OP_TYPE_HISTOGRAM = 0x13, ++ IVE_IOC_OP_TYPE_INTEGRAL = 0x14, ++ IVE_IOC_OP_TYPE_SAD = 0x15, ++ IVE_IOC_OP_TYPE_NCC = 0x16, ++ IVE_IOC_OP_TYPE_LBP = 0x18 ++} IVE_IOC_OP_TYPE; ++ ++typedef enum ++{ ++ IVE_IOC_IMAGE_FORMAT_B8C1 = 0x00, ++ IVE_IOC_IMAGE_FORMAT_B8C3_PLAN = 0x02, ++ IVE_IOC_IMAGE_FORMAT_B16C1 = 0x03, ++ IVE_IOC_IMAGE_FORMAT_B8C3_PACK = 0x04, ++ IVE_IOC_IMAGE_FORMAT_420SP = 0x05, ++ IVE_IOC_IMAGE_FORMAT_422SP = 0x06, ++ IVE_IOC_IMAGE_FORMAT_B32C1 = 0x80, // dummy enum for destination buffer ++ IVE_IOC_IMAGE_FORMAT_B64C1 = 0x81 // dummy enum for destination buffer ++} IVE_IOC_IMAGE_FORMAT; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SOBEL_BOTH = 0x00, ++ IVE_IOC_MODE_SOBEL_HORIZONTAL = 0x01, ++ IVE_IOC_MODE_SOBEL_VERTICAL = 0x02, ++} IVE_IOC_MODE_SOBEL; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_MAG_AND_ANG_ONLY_MAG = 0x00, ++ IVE_IOC_MODE_MAG_AND_ANG_BOTH = 0x01 ++} IVE_IOC_MODE_MAG_AND_ANG; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_ORD_STAT_FILTER_MEDIAN = 0x00, ++ IVE_IOC_MODE_ORD_STAT_FILTER_MAX = 0x01, ++ IVE_IOC_MODE_ORD_STAT_FILTER_MIN = 0x02, ++ ++} IVE_IOC_MODE_ORD_STAT_FILTER; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_BERNSEN_NORMAL_3X3 = 0x00, ++ IVE_IOC_MODE_BERNSEN_NORMAL_5X5 = 0x01, ++ IVE_IOC_MODE_BERNSEN_THRESH_3X3 = 0x02, ++ IVE_IOC_MODE_BERNSEN_THRESH_5X5 = 0x03 ++} IVE_IOC_MODE_BERNSEN; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_THRESH_BINARY = 0x00, ++ IVE_IOC_MODE_THRESH_TRUNC = 0x01, ++ IVE_IOC_MODE_THRESH_TO_MINVAL = 0x02, ++ IVE_IOC_MODE_THRESH_MIN_MID_MAX = 0x03, ++ IVE_IOC_MODE_THRESH_ORI_MID_MAX = 0x04, ++ IVE_IOC_MODE_THRESH_MIN_MID_ORI = 0x05, ++ IVE_IOC_MODE_THRESH_MIN_ORI_MAX = 0x06, ++ IVE_IOC_MODE_THRESH_ORI_MID_ORI = 0x07 ++} IVE_IOC_MODE_THRESH; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_THRESH_S16_TO_S8_MIN_MID_MAX = 0x00, ++ IVE_IOC_MODE_THRESH_S16_TO_S8_MIN_ORI_MAX = 0x01, ++ IVE_IOC_MODE_THRESH_S16_TO_U8_MIN_MID_MAX = 0x02, ++ IVE_IOC_MODE_THRESH_S16_TO_U8_MIN_ORI_MAX = 0x03, ++ ++} IVE_IOC_MODE_THRESH_S16; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_THRESH_U16_TO_U8_MIN_MID_MAX = 0x00, ++ IVE_IOC_MODE_THRESH_U16_TO_U8_MIN_ORI_MAX = 0x01, ++ ++} IVE_IOC_MODE_THRESH_U16; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SUB_ABS = 0x00, ++ IVE_IOC_MODE_SUB_SHIFT = 0x01, ++} IVE_IOC_MODE_SUB; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_S16_TO_S8 = 0x00, ++ IVE_IOC_MODE_S16_TO_U8_ABS = 0x01, ++ IVE_IOC_MODE_S16_TO_U8_BIAS = 0x02, ++ IVE_IOC_MODE_U16_TO_U8 = 0x03, ++ ++} IVE_IOC_MODE_16_TO_8; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_INTEGRAL_BOTH = 0x00, ++ IVE_IOC_MODE_INTEGRAL_SUM = 0x01, ++ IVE_IOC_MODE_INTEGRAL_SQUARE_SUM = 0x02 ++} IVE_IOC_MODE_INTEGRAL; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SAD_BLOCK_4X4 = 0x00, ++ IVE_IOC_MODE_SAD_BLOCK_8X8 = 0x01, ++ IVE_IOC_MODE_SAD_BLOCK_16X16 = 0x02, ++ ++} IVE_IOC_MODE_SAD_BLOCK; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_SAD_OUT_CTRL_16BIT_BOTH = 0x00, ++ IVE_IOC_MODE_SAD_OUT_CTRL_8BIT_BOTH = 0x01, ++ IVE_IOC_MODE_SAD_OUT_CTRL_16BIT_SAD = 0x02, ++ IVE_IOC_MODE_SAD_OUT_CTRL_8BIT_SAD = 0x03, ++ IVE_IOC_MODE_SAD_OUT_CTRL_THRESH = 0x04 ++} IVE_IOC_MODE_SAD_OUT; ++ ++typedef enum ++{ ++ IVE_IOC_MODE_LBP_COMP_NORMAL = 0x00, ++ IVE_IOC_MODE_LBP_COMP_ABS = 0x01, ++ ++} IVE_IOC_MODE_LBP; ++ ++typedef struct ++{ ++ IVE_IOC_IMAGE_FORMAT format; ++ ++ __u16 width; ++ __u16 height; ++ void* address[3]; ++ __u16 stride[3]; ++} ive_ioc_image; ++ ++typedef struct ++{ ++ __u8 mask[25]; ++ __u8 shift; ++} ive_ioc_coeff_filter; ++ ++typedef struct ++{ ++ __u8 clamp_low; ++ __u8 clamp_high; ++} ive_ioc_coeff_csc_clamp; ++ ++typedef struct ++{ ++ __u16 coeff[9]; ++ __u16 offset[3]; ++ ive_ioc_coeff_csc_clamp clamp[3]; ++} ive_ioc_coeff_csc; ++ ++typedef struct ++{ ++ ive_ioc_coeff_filter filter; ++ ive_ioc_coeff_csc csc; ++} ive_ioc_coeff_filter_csc; ++ ++ ++typedef struct ++{ ++ IVE_IOC_MODE_SOBEL mode; ++ __u8 mask[25]; ++} ive_ioc_coeff_sobel; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_MAG_AND_ANG mode; ++ __u8 mask[25]; ++ __u16 thresh; ++} ive_ioc_coeff_mag_and_ang; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_ORD_STAT_FILTER mode; ++} ive_ioc_coeff_ord_stat_filter; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_BERNSEN mode; ++ __u16 thresh; ++} ive_ioc_coeff_bernsen; ++ ++typedef struct ++{ ++ __u8 mask[25]; ++} ive_ioc_coeff_dilate; ++ ++typedef struct ++{ ++ __u8 mask[25]; ++} ive_ioc_coeff_erode; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_THRESH mode; ++ __u16 low; ++ __u16 high; ++ __u8 min; ++ __u8 mid; ++ __u8 max; ++} ive_ioc_coeff_thresh; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_THRESH_S16 mode; ++ __u16 low; ++ __u16 high; ++ __u8 min; ++ __u8 mid; ++ __u8 max; ++} ive_ioc_coeff_thresh_s16; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_THRESH_U16 mode; ++ __u16 low; ++ __u16 high; ++ __u8 min; ++ __u8 mid; ++ __u8 max; ++} ive_ioc_coeff_thresh_u16; ++ ++typedef struct ++{ ++ __u16 weight_x; ++ __u16 weight_y; ++} ive_ioc_coeff_add; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_SUB mode; ++} ive_ioc_coeff_sub; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_16_TO_8 mode; ++ __u16 denominator; ++ __u8 numerator; ++ __s8 bias; ++} ive_ioc_coeff_16to8; ++ ++typedef struct ++{ ++ __u8 map[256]; ++} ive_ioc_coeff_map; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_INTEGRAL mode; ++} ive_ioc_coeff_integral; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_SAD_BLOCK block_mode; ++ IVE_IOC_MODE_SAD_OUT out_mode; ++ __u16 thresh; ++ __u8 min; ++ __u8 max; ++} ive_ioc_coeff_sad; ++ ++typedef struct ++{ ++ __u64 numerator; ++ __u64 sum1; ++ __u64 sum2; ++} ive_ioc_coeff_ncc; ++ ++typedef struct ++{ ++ IVE_IOC_MODE_LBP mode; ++ __u16 thresh; ++} ive_ioc_coeff_lbp; ++ ++typedef struct ++{ ++ IVE_IOC_OP_TYPE op_type; ++ ++ ive_ioc_image input; ++ ive_ioc_image output; ++ ++ union ++ { ++ ive_ioc_coeff_filter coeff_filter; ++ ive_ioc_coeff_csc coeff_csc; ++ ive_ioc_coeff_filter_csc coeff_filter_csc; ++ ive_ioc_coeff_sobel coeff_sobel; ++ ive_ioc_coeff_mag_and_ang coeff_mag_and_ang; ++ ive_ioc_coeff_ord_stat_filter coeff_ord_stat_filter; ++ ive_ioc_coeff_bernsen coeff_bernsen; ++ ive_ioc_coeff_dilate coeff_dilate; ++ ive_ioc_coeff_erode coeff_erode; ++ ive_ioc_coeff_thresh coeff_thresh; ++ ive_ioc_coeff_thresh_s16 coeff_thresh_s16; ++ ive_ioc_coeff_thresh_u16 coeff_thresh_u16; ++ ive_ioc_coeff_add coeff_add; ++ ive_ioc_coeff_sub coeff_sub; ++ ive_ioc_coeff_16to8 coeff_16to8; ++ ive_ioc_coeff_map coeff_map; ++ ive_ioc_coeff_integral coeff_integral; ++ ive_ioc_coeff_sad coeff_sad; ++ ive_ioc_coeff_ncc *coeff_ncc; ++ ive_ioc_coeff_lbp coeff_lbp; ++ }; ++} ive_ioc_config; ++ ++#endif //_MDRV_IVE_IO_ST_H_ +diff --git a/drivers/mstar/include/mdrv_jpe_io.h b/drivers/mstar/include/mdrv_jpe_io.h +new file mode 100644 +index 00000000..e5d9bf3c +--- /dev/null ++++ b/drivers/mstar/include/mdrv_jpe_io.h +@@ -0,0 +1,44 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_JPE_IO_H_ ++#define _MDRV_JPE_IO_H_ ++ ++#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ ++#define IOC_JPE_VOID 0x20000000 /* no parameters */ ++#define IOC_JPE_OUT 0x40000000 /* copy out parameters */ ++#define IOC_JPE_IN 0x80000000 /* copy in parameters */ ++#define IOC_JPE_INOUT (IOC_JPE_IN|IOC_JPE_OUT) ++ ++#define _IO_JPE(x,y) (IOC_JPE_VOID|((x)<<8)|(y)) ++#define _IOR_JPE(x,y,t) (IOC_JPE_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++#define _IOW_JPE(x,y,t) (IOC_JPE_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++ ++//JPE IOC COMMANDS ++#define JPE_IOC_MAGIC 'J' ++// Initialize *pJpeInfo ++#define JPE_IOC_INIT _IO_JPE(JPE_IOC_MAGIC, 0) ++// Set up JPE RIU and fire JPE ++#define JPE_IOC_ENCODE_FRAME _IO_JPE(JPE_IOC_MAGIC, 1) ++// Get output buffer status ++#define JPE_IOC_GETBITS _IOR_JPE(JPE_IOC_MAGIC, 2, __u32) ++// ++#define JPE_IOC_GET_CAPS _IOR_JPE(JPE_IOC_MAGIC, 3, __u32) ++// ++#define JPE_IOC_SET_OUTBUF _IOR_JPE(JPE_IOC_MAGIC, 4, __u32) ++ ++#endif // _MDRV_JPE_IO_H_ +\ No newline at end of file +diff --git a/drivers/mstar/include/mdrv_jpe_io_st.h b/drivers/mstar/include/mdrv_jpe_io_st.h +new file mode 100644 +index 00000000..d84fbcc0 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_jpe_io_st.h +@@ -0,0 +1,134 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2009-2010 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_JPE_IO_ST_H_ ++#define _MDRV_JPE_IO_ST_H_ ++ ++#include ++#include ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ JPE_IBUF_ROW_MODE = 0x0, ++ JPE_IBUF_FRAME_MODE = 0x1 ++} JpeInBufMode_e; ++ ++typedef enum ++{ ++ JPE_RAW_YUYV = 0x0, ++ JPE_RAW_YVYU = 0x1, ++ JPE_RAW_NV12 = 0x3, ++ JPE_RAW_NV21 = 0x4, ++} JpeRawFormat_e; ++ ++typedef enum ++{ ++ JPE_CODEC_JPEG = 0x1, ++ JPE_CODEC_H263I = 0x2, //! obsolete ++ JPE_CODEC_ENCODE_DCT = 0x4, //! obsolete ++} JpeCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_IDLE_STATE = 0, ++ JPE_BUSY_STATE = 1, ++ JPE_FRAME_DONE_STATE = 2, ++ JPE_OUTBUF_FULL_STATE = 3, ++ JPE_INBUF_FULL_STATE = 4 ++} JpeState_e; ++ ++typedef enum ++{ ++ JPE_IOC_RET_SUCCESS = 0, ++ JPE_IOC_RET_BAD_QTABLE = 1, ++ JPE_IOC_RET_BAD_QP = 2, ++ JPE_IOC_RET_BAD_BITSOFFSET = 3, ++ JPE_IOC_RET_BAD_BANKNUM = 4, ++ JPE_IOC_RET_BAD_INBUF = 5, ++ JPE_IOC_RET_BAD_OUTBUF = 6, ++ JPE_IOC_RET_BAD_NULLPTR = 7, ++ JPE_IOC_RET_BAD_BANKCNT = 8, ++ JPE_IOC_RET_BAD_LASTZZ = 9, ++ JPE_IOC_RET_UNKOWN_COMMAND = 10, ++ JPE_IOC_RET_BAD_VIRTUAL_MEM = 11, ++ JPE_IOC_RET_NEED_DRIVER_INIT = 12, ++ JPE_IOC_RET_FMT_NOT_SUPPORT = 13, ++ JPE_IOC_RET_HW_IS_RUNNING = 14, ++ JPE_IOC_RET_FAIL = 15 ++} JPE_IOC_RET_STATUS_e; ++ ++typedef enum ++{ ++ JPE_COLOR_PLAN_LUMA = 0, ++ JPE_COLOR_PLAN_CHROMA = 1, ++ JPE_COLOR_PLAN_MAX = 2 ++} JPE_COLOR_PLAN_e; ++ ++typedef struct ++{ ++ __u32 __u32JpeId; ++ __u32 nRefYLogAddrAlign[2]; ++ __u32 nRefCLogAddrAlign[2]; ++ __u32 nOutBufSLogAddrAlign; ++ __u8 nSclHandShakeSupport; ++ __u8 nCodecSupport; ++ __u8 nBufferModeSupport; ++} JpeCaps_t, *pJpeCaps; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; ++ unsigned long nOutputSize; ++ JpeState_e eState; ++} JpeBitstreamInfo_t, *pJpeBitstreamInfo; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nSize; ++} JpeBufInfo_t; ++ ++typedef struct ++{ ++ JpeInBufMode_e eInBufMode; ++ JpeRawFormat_e eRawFormat; ++ JpeCodecFormat_e eCodecFormat; ++ __u32 nWidth; ++ __u32 nHeight; ++ __u16 YQTable[64]; ++ __u16 CQTable[64]; ++ __u16 nQScale; ++ JpeBufInfo_t InBuf[JPE_COLOR_PLAN_MAX]; ++ JpeBufInfo_t OutBuf; ++ __u32 nJpeOutBitOffset; ++} JpeCfg_t; ++ ++ ++typedef struct JpeEncOutbuf_t ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; // Original buffer Size ++ unsigned long nOutputSize; // Output Size ++ JpeState_e eState; ++} JpeEncOutbuf_t; ++ ++#endif //_MDRV_JPE_IO_ST_H_ +\ No newline at end of file +diff --git a/drivers/mstar/include/mdrv_mfe_io.h b/drivers/mstar/include/mdrv_mfe_io.h +new file mode 100644 +index 00000000..b0e50ce8 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_mfe_io.h +@@ -0,0 +1,118 @@ ++ ++#ifndef _MDRV_MMFE_IO_H_ ++#define _MDRV_MMFE_IO_H_ ++ ++/* definition of structures */ ++ ++#define MEMORY_USER 0 ++#define MEMORY_MMAP 1 ++ ++#define PIXFMT_TILED 0 ++#define PIXFMT_PLANE 1 ++ ++typedef struct mmfe_reqbuf { ++ int i_vq; ++ int i_memory; ++ int i_pic_w, i_pic_h; ++ int i_count; ++} mmfe_reqbuf; ++ ++typedef struct mmfe_buffer { ++ int i_vq; ++ int i_vb; ++ int i_memory; ++ int i_planes; ++ struct { ++ union { ++ unsigned int addr; ++ void* uptr; ++ }; ++ int size; ++ int used; ++ } planes[4]; ++ long long timecode; ++} mmfe_buffer; ++ ++#define MVIDPARAMS_PIXELS 0 ++#define MVIDPARAMS_FRAMERATE 1 ++#define MVIDPARAMS_MOTION 2 ++#define MVIDPARAMS_BITRATE 3 ++#define MVIDPARAMS_GOP 4 ++#define MVIDPARAMS_AVC 5 ++ ++#define RC_METHOD_CBR 0 ++#define RC_METHOD_VBR 1 ++#define RC_METHOD_CONST 2 ++ ++#define MV_BLOCK_4x4 (1<<0) ++#define MV_BLOCK_8x4 (1<<1) ++#define MV_BLOCK_4x8 (1<<2) ++#define MV_BLOCK_8x8 (1<<3) ++#define MV_BLOCK_16x8 (1<<4) ++#define MV_BLOCK_8x16 (1<<5) ++#define MV_BLOCK_16x16 (1<<6) ++#define MV_BLOCK_SKIP (1<<7) ++ ++typedef struct mmfe_params { ++ int i_params; ++ union { ++ unsigned char bytes[60]; ++ struct { ++ int i_pict_w; /* picture width */ ++ int i_pict_h; /* picture height */ ++ int i_pixfmt; /* pixel format */ ++ } pixels; ++ struct { ++ int i_num; /* numerator of frame-rate */ ++ int i_den; /* denominator of frame-rate */ ++ } framerate; ++ struct { ++ int i_dmv_x; /* dMV x-direction (8~16) */ ++ int i_dmv_y; /* dMV y-direction (8/16) */ ++ int i_subpel; /* subpel: 0-integral,1-half,2-quarter */ ++ unsigned int i_mv_block[2]; /* motion block flags */ ++ } motion; ++ struct { ++ int i_pframes; /* p-frames count per i-frame */ ++ int i_bframes; /* b-frames count per i/p-frame */ ++ } gop; ++ struct { ++ int i_method; /* constant bit-rate/variable bit-rate/constant quality */ ++ int i_kbps; /* bps/1024 */ ++ int i_qp; /* qp-value */ ++ } bitrate; ++ struct { ++ int i_profile; /* avc profile value */ ++ int i_level; /* avc level value */ ++ int i_num_ref_frames; /* reference frame count */ ++ int b_cabac; /* entropy: cabac/cavlc */ ++ int b_constrained_intra_pred; /* contrained intra pred */ ++ int b_deblock_filter_control; /* deblock filter control */ ++ int i_disable_deblocking_idc; /* disable deblocking idc */ ++ int i_alpha_c0_offset; /* offset alpha div2 */ ++ int i_beta_offset; /* offset beta div2 */ ++ int b_multiple_slices; /* multi-slices */ ++ } avc; ++ }; ++} mmfe_params; ++ ++typedef struct mmfe_control { ++ int i_control; ++ int i_value; ++} mmfe_control; ++ ++/* definition of ioctl codes */ ++ ++#define IOCTL_MFE_S_PARM _IOWR('m', 0,struct mmfe_params) ++#define IOCTL_MFE_G_PARM _IOWR('m', 1,struct mmfe_params) ++#define IOCTL_MFE_S_CTRL _IOWR('m', 2,struct mmfe_control) ++#define IOCTL_MFE_G_CTRL _IOWR('m', 3,struct mmfe_control) ++#define IOCTL_MFE_STREAMON _IO('m', 4) ++#define IOCTL_MFE_STREAMOFF _IO('m', 5) ++#define IOCTL_MFE_REQBUF _IOWR('m', 6,struct mmfe_reqbuf) ++#define IOCTL_MFE_S_PICT _IOWR('m', 7,struct mmfe_buffer) ++#define IOCTL_MFE_G_BITS _IOWR('m', 8,struct mmfe_buffer) ++#define IOCTL_MFE_FLUSH _IO('m', 9) ++ ++#endif//_MDRV_MMFE_IO_H_ ++ +diff --git a/drivers/mstar/include/mdrv_mmfe_io.h b/drivers/mstar/include/mdrv_mmfe_io.h +new file mode 100644 +index 00000000..27b745fc +--- /dev/null ++++ b/drivers/mstar/include/mdrv_mmfe_io.h +@@ -0,0 +1,62 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! @file mdrv_mmfe_io.h ++//! @author MStar Semiconductior Inc. ++//! @brief MFEv5 Driver IOCTL User's Interface. ++//! \defgroup mmfe_group MFEv5 driver ++//! @{ ++#ifndef _MDRV_MMFE_IO_H_ ++#define _MDRV_MMFE_IO_H_ ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Header Files ++//////////////////////////////////////////////////////////////////////////////// ++#include ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Magic Number of MFEv5 driver. ++#define MAGIC_MMFE ('m') ++//! Use to Query version number of user interface. ++#define IOCTL_MMFE_VERSION _IOWR(MAGIC_MMFE, 0,unsigned int) ++//! Use to set parameters out of streaming. ++#define IOCTL_MMFE_S_PARM _IOWR(MAGIC_MMFE, 1,mmfe_parm) ++//! Use to get parameters any time. ++#define IOCTL_MMFE_G_PARM _IOWR(MAGIC_MMFE, 2,mmfe_parm) ++//! Use to transit the state to streaming-on. ++#define IOCTL_MMFE_STREAMON _IO(MAGIC_MMFE, 3) ++//! Use to transit the state to streaming-off. ++#define IOCTL_MMFE_STREAMOFF _IO(MAGIC_MMFE, 4) ++//! Use to set control during streaming. ++#define IOCTL_MMFE_S_CTRL _IOWR(MAGIC_MMFE, 5,mmfe_ctrl) ++//! Use to get control during streaming. ++#define IOCTL_MMFE_G_CTRL _IOWR(MAGIC_MMFE, 6,mmfe_ctrl) ++//! Use to encode a picture during streaming. ++#define IOCTL_MMFE_S_PICT _IOWR(MAGIC_MMFE, 7,mmfe_buff) ++//! Use to acquire the output bits of last coded picture. ++#define IOCTL_MMFE_G_BITS _IOWR(MAGIC_MMFE, 8,mmfe_buff) ++//! Use to encode a picture and acquire the output at the same time. ++#define IOCTL_MMFE_ENCODE _IOWR(MAGIC_MMFE, 9,mmfe_buff[2]) ++//! Use to put user data. ++#define IOCTL_MMFE_S_DATA _IOWR(MAGIC_MMFE,10,mmfe_buff) ++ ++#endif//_MDRV_MMFE_IO_H_ ++//! @} ++ +diff --git a/drivers/mstar/include/mdrv_mmfe_st.h b/drivers/mstar/include/mdrv_mmfe_st.h +new file mode 100644 +index 00000000..8c1c814e +--- /dev/null ++++ b/drivers/mstar/include/mdrv_mmfe_st.h +@@ -0,0 +1,290 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! @file mdrv_mmfe_st.h ++//! @author MStar Semiconductior Inc. ++//! @brief MFEv5 Driver IOCTL User's Interface. ++//! \ingroup mmfe_group MFEv5 driver ++//! @{ ++#ifndef _MDRV_MMFE_ST_H_ ++#define _MDRV_MMFE_ST_H_ ++ ++#define MMFEIF_MAJ 1 //!< major version: Major number of driver-I/F version. ++#define MMFEIF_MIN 2 //!< minor version: Minor number of driver-I/F version. ++#define MMFEIF_EXT 1 //!< extended code: Extended number of version. It should increase when "mdrv_mmfe_io.h/mdrv_mmfe_st.h" changed. ++ ++//! User Interface version number. ++#define MMFEIF_VERSION_ID ((MMFEIF_MAJ<<22)|(MMFEIF_MIN<<12)|(MMFEIF_EXT)) ++//! Acquire version number. ++#define MMFEIF_GET_VER(v) (((v)>>12)) ++//! Acquire major version number. ++#define MMFEIF_GET_MJR(v) (((v)>>22)&0x3FF) ++//! Acquire minor version number. ++#define MMFEIF_GET_MNR(v) (((v)>>12)&0x3FF) ++//! Acquire extended number. ++#define MMFEIF_GET_EXT(v) (((v)>> 0)&0xFFF) ++ ++//! mmfe_pixfmt indicates pixels formats ++enum mmfe_pixfmt { ++ MMFE_PIXFMT_NV12=0, //!< pixel format NV12. ++ MMFE_PIXFMT_NV21, //!< pixel format NV21. ++ MMFE_PIXFMT_YUYV, //!< pixel format YUYV. ++ MMFE_PIXFMT_YVYU, //!< pixel format YVYU. ++}; ++ ++//! mmfe_subpel indicates interpolation granularity ++enum mmfe_subpel ++{ ++ MMFE_SUBPEL_INT=0, //!< subpel integral. ++ MMFE_SUBPEL_HALF, //!< subpel half. ++ MMFE_SUBPEL_QUATER, //!< subpel quater. ++}; ++ ++#define MMFE_MVBLK_4x4 (1<<0) //!< bit-field of 4x4 block ++#define MMFE_MVBLK_8x4 (1<<1) //!< bit-field of 8x4 block ++#define MMFE_MVBLK_4x8 (1<<2) //!< bit-field of 4x8 block ++#define MMFE_MVBLK_8x8 (1<<3) //!< bit-field of 8x8 block ++#define MMFE_MVBLK_16x8 (1<<4) //!< bit-field of 16x8 block ++#define MMFE_MVBLK_8x16 (1<<5) //!< bit-field of 8x16 block ++#define MMFE_MVBLK_16x16 (1<<6) //!< bit-field of 16x16 block ++#define MMFE_MVBLK_SKIP (1<<7) //!< bit-field of skip ++#define MMFE_AVC_PROFILE_BP 66 //!< H.264 Base Line Profile ++#define MMFE_AVC_PROFILE_MP 77 //!< H.264 Main Profile ++#define MMFE_AVC_LEVEL_3 30 //!< H.264 Level-3.0 ++#define MMFE_AVC_LEVEL_31 31 //!< H.264 Level-3.1 ++#define MMFE_AVC_LEVEL_32 32 //!< H.264 Level-3.2 ++#define MMFE_AVC_LEVEL_4 40 //!< H.264 Level-4.0 ++ ++//! mmfe_parm is used to apply/query configs out of streaming period. ++typedef union mmfe_parm ++{ ++ //! indicating parameter type. ++ enum mmfe_parm_e ++ { ++ MMFE_PARM_IDX = 0, //!< parameters of streamid: query stream-id. ++ MMFE_PARM_RES, //!< parameters of resource: including image's resolution and format ++ MMFE_PARM_FPS, //!< parameters of fps: fraction of framerate. ++ MMFE_PARM_GOP, //!< parameters of gop: ip frame period. ++ MMFE_PARM_BPS, //!< parameters of bps: bit per second. ++ MMFE_PARM_MOT, //!< parameters of motion: interpolation granularity, mv-partition. ++ MMFE_PARM_AVC, //!< parameters of avc: codec settings. ++ MMFE_PARM_VUI, //!< parameters of vui: vui params. ++ MMFE_PARM_LTR, //!< parameters of ltr: long term reference. ++ } type; //!< indicating which kind of mmfe_parm is. ++ ++ //! set res parameter out of streaming. ++ struct mmfe_parm_idx ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_IDX. ++ int i_stream; //!< stream-id. ++ } idx; ++ ++ //! set res parameter out of streaming. ++ struct mmfe_parm_res ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_RES. ++ int i_pict_w; //!< picture width. ++ int i_pict_h; //!< picture height. ++ enum mmfe_pixfmt i_pixfmt; //!< pixel format. ++ int i_outlen; //!< output length: '<0' mmap-mode, '>=0' user-mode. ++ int i_flags; //!< flags. ++#define STREAM_ID_DEFAULT 0xFFFF ++ int i_strid; //!< stream id, use STREAM_ID_DEFAULT as older naming ++ } res; //!< used to set resource parameters. ++ ++ //! set fps parameter out of streaming. ++ struct mmfe_parm_fps ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_FPS. ++ int i_num; //!< numerator of fps. ++ int i_den; //!< denominator of fps. ++ } fps; //!< used to set fraction of frame rate. ++ ++ //! set mot parameter out of streaming. ++ struct mmfe_parm_mot ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_MOT. ++ int i_dmv_x; //!< x-dir dmv. ++ int i_dmv_y; //!< y-dir dmv. ++ enum mmfe_subpel i_subpel; //!< interpolation granularity. ++ unsigned int i_mvblks[2]; //!< mv-partitions. ++ } mot; //!< used to set motion configuration. ++ ++ //! set gop parameter out of streaming. ++ struct mmfe_parm_gop ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_GOP. ++ int i_pframes; //!< p-frames count per i-frame ++ int i_bframes; //!< b-frames count per i/p-frame ++ } gop; //!< used to set gop structure. ++ ++ //! set bps parameter out of streaming. ++ struct mmfe_parm_bps ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_BPS. ++ int i_method; //!< rate-control method. ++ int i_ref_qp; //!< ref. QP. ++ int i_bps; //!< bitrate. ++ } bps; //!< used to set bit rate controller. ++ ++ //! set avc parameter out of streaming. ++ struct mmfe_parm_avc ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_AVC. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_num_ref_frames; //!< ref.frames count. ++ unsigned char i_poc_type; //!< poc_type: support 0,2. ++ unsigned char b_cabac; //!< entropy: cabac/cavlc. ++ unsigned char b_constrained_intra_pred; //!< contrained intra pred. ++ unsigned char b_deblock_filter_control; //!< deblock filter control. ++ unsigned char i_disable_deblocking_idc; //!< disable deblocking idc. ++ signed char i_alpha_c0_offset; //!< offset alpha div2. ++ signed char i_beta_offset; //!< offset beta div2. ++ } avc; //!< used to set codec configuration. ++ ++ //! set avc parameter out of streaming. ++ struct mmfe_parm_vui ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_VUI. ++ int b_video_full_range; ++ int b_timing_info_pres; ++ } vui; //!< used to set codec configuration. ++ ++ //! set ltr parameter out of streaming. ++ struct mmfe_parm_ltr ++ { ++ enum mmfe_parm_e i_type; //!< i_type MUST be MMFE_PARM_LTR. ++ int b_long_term_reference; //!< toggle ltr mode ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set ltr configuration. ++ ++ unsigned char byte[64]; //!< dummy bytes ++ ++} mmfe_parm; ++ ++//! mmfe_ctrl is used to apply/query control configs during streaming period. ++typedef union mmfe_ctrl ++{ ++ //! indicating control type. ++ enum mmfe_ctrl_e ++ { ++ MMFE_CTRL_SEQ = 0, //!< control of sequence: includes resolution, pixel format and frame-rate. ++ MMFE_CTRL_AVC, //!< control of avc codec settings. ++ MMFE_CTRL_ROI, //!< control of roi setting changing. ++ MMFE_CTRL_SPL, //!< control of slice spliting. ++ MMFE_CTRL_LTR, //!< control of long term reference. ++ } type; //!< indicating which kind of mmfe_ctrl is. ++ ++ //! set seq parameter during streaming. ++ struct mmfe_ctrl_seq ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_SEQ. ++ enum mmfe_pixfmt i_pixfmt; //!< pixel-format ++ short i_pixelw; //!< pixels in width ++ short i_pixelh; //!< pixels in height ++ short n_fps; //!< numerator of frame-rate ++ short d_fps; //!< denominator of frame-rate ++ } seq; //!< used to start new sequence. ++ ++ //! set avc parameter during streaming. ++ struct mmfe_ctrl_avc ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_AVC. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_num_ref_frames; //!< ref.frames count. ++ unsigned char i_poc_type; //!< poc_type: support 0,2. ++ unsigned char b_cabac; //!< entropy: cabac/cavlc. ++ unsigned char b_constrained_intra_pred; //!< Constrained intra pred. ++ unsigned char b_deblock_filter_control; //!< deblock filter control. ++ unsigned char i_disable_deblocking_idc; //!< disable deblocking idc. ++ signed char i_alpha_c0_offset; //!< offset alpha div2. ++ signed char i_beta_offset; //!< offset beta div2. ++ } avc; //!< used to set avc codec setting. ++ ++ //! set roi parameter during streaming. ++ struct mmfe_ctrl_roi ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_ROI. ++ short i_index; //!< roi index. ++ short i_dqp; //!< roi delta-qp: 0-disable roi, negative value. ++ unsigned short i_mbx; //!< roi rectangle position-X. ++ unsigned short i_mby; //!< roi rectangle position-Y. ++ unsigned short i_mbw; //!< roi rectangle-W. ++ unsigned short i_mbh; //!< roi rectangle-H. ++ } roi; //!< used to set roi region and dqp. ++ ++ //! set spl parameter during streaming. ++ struct mmfe_ctrl_spl ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_SPL. ++ int i_rows; //!< slice split by mb-rows. ++ int i_bits; //!< slice split by bitcnt. ++ } spl; //!< used to set slice splitting. ++ ++ //! set ltr parameter during streaming. ++ struct mmfe_ctrl_ltr ++ { ++ enum mmfe_ctrl_e i_type; //!< i_type MUST be MMFE_CTRL_LTR. ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set long term reference. ++ ++ unsigned char byte[64]; //!< dummy bytes ++} mmfe_ctrl; ++ ++#define MMFE_FLAGS_IDR (1<< 0) //!< request IDR. ++#define MMFE_FLAGS_DISPOSABLE (1<< 1) //!< request unref-pic. ++#define MMFE_FLAGS_NIGHT_MODE (1<< 2) //!< night mode. ++#define MMFE_FLAGS_LTR_PFRAME (1<< 4) //!< LTR P-frame flag. ++#define MMFE_FLAGS_SOP (1<<30) //!< start of picture. ++#define MMFE_FLAGS_EOP (1<<31) //!< end of picture. ++#define MMFE_MEMORY_USER (0) //!< user mode. (pass pointer) ++#define MMFE_MEMORY_MMAP (1) //!< mmap mode. (pass physic address) ++ ++//! mmfe_buff is used to exchange video/obits buffer between user and driver during streaming period. ++typedef struct mmfe_buff ++{ ++ int i_index; //!< index of buffer: '-1' invalid, '>=0' valid. ++ int i_flags; //!< flags for request/reports. ++ short i_memory; //!< memory mode of user/mmap. ++ short i_width; //!< pixels in width. (if buffer is image) ++ short i_height; //!< pixels in height. (if buffer is image) ++ short i_stride; //!< pixels in stride. (if buffer is image) ' ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Magic Number of MFEv5 driver. ++#define MAGIC_MVHE ('v') ++//! Use to Query version number of user interface. ++#define IOCTL_MVHE_VERSION _IOWR(MAGIC_MVHE, 0,unsigned int) ++//! Use to set parameters out of streaming. ++#define IOCTL_MVHE_S_PARM _IOWR(MAGIC_MVHE, 1,mvhe_parm) ++//! Use to get parameters any time. ++#define IOCTL_MVHE_G_PARM _IOWR(MAGIC_MVHE, 2,mvhe_parm) ++//! Use to transit the state to streaming-on. ++#define IOCTL_MVHE_STREAMON _IO(MAGIC_MVHE, 3) ++//! Use to transit the state to streaming-off. ++#define IOCTL_MVHE_STREAMOFF _IO(MAGIC_MVHE, 4) ++//! Use to set control during streaming. ++#define IOCTL_MVHE_S_CTRL _IOWR(MAGIC_MVHE, 5,mvhe_ctrl) ++//! Use to get control during streaming. ++#define IOCTL_MVHE_G_CTRL _IOWR(MAGIC_MVHE, 6,mvhe_ctrl) ++//! Use to encode a picture during streaming. ++#define IOCTL_MVHE_S_PICT _IOWR(MAGIC_MVHE, 7,mvhe_buff) ++//! Use to acquire the output bits of last coded picture. ++#define IOCTL_MVHE_G_BITS _IOWR(MAGIC_MVHE, 8,mvhe_buff) ++//! Use to encode a picture and acquire the output at the same time. ++#define IOCTL_MVHE_ENCODE _IOWR(MAGIC_MVHE, 9,mvhe_buff[2]) ++//! Use to put user data. ++#define IOCTL_MVHE_S_DATA _IOWR(MAGIC_MVHE,10,mvhe_buff) ++ ++#endif//_MDIV_MVHE_IO_H_ ++//! @} ++ +diff --git a/drivers/mstar/include/mdrv_mvhe_st.h b/drivers/mstar/include/mdrv_mvhe_st.h +new file mode 100644 +index 00000000..0fb466ec +--- /dev/null ++++ b/drivers/mstar/include/mdrv_mvhe_st.h +@@ -0,0 +1,315 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! @file mdrv_mvhe_st.h ++//! @author MStar Semiconductior Inc. ++//! @brief VHE Driver IOCTL User's Interface. ++//! \ingroup mvhe_group VHE driver ++//! @{ ++#ifndef _MDRV_MVHE_ST_H_ ++#define _MDRV_MVHE_ST_H_ ++ ++#define MVHEIF_MAJ 1 //!< major version: Major number of driver-I/F version. ++#define MVHEIF_MIN 2 //!< minor version: Minor number of driver-I/F version. ++#define MVHEIF_EXT 1 //!< extended code: Extended number of version. It should increase when "mdrv_mvhe_io.h/mdrv_mvhe_st.h" changed. ++ ++//! User Interface version number. ++#define MVHEIF_VERSION_ID ((MVHEIF_MAJ<<22)|(MVHEIF_MIN<<12)|(MVHEIF_EXT)) ++//! Acquire version number. ++#define MVHEIF_GET_VER(v) (((v)>>12)) ++//! Acquire major version number. ++#define MVHEIF_GET_MJR(v) (((v)>>22)&0x3FF) ++//! Acquire minor version number. ++#define MVHEIF_GET_MNR(v) (((v)>>12)&0x3FF) ++//! Acquire extended number. ++#define MVHEIF_GET_EXT(v) (((v)>> 0)&0xFFF) ++ ++//! mvhe_pixfmt indicates pixels formats ++enum mvhe_pixfmt ++{ ++ MVHE_PIXFMT_NV12=0, //!< pixel format NV12. ++ MVHE_PIXFMT_NV21, //!< pixel format NV21. ++ MVHE_PIXFMT_YUYV, //!< pixel format YUYV. ++ MVHE_PIXFMT_YVYU, //!< pixel format YVYU. ++}; ++ ++#define MVHE_HEVC_PROFILE_MAIN 1 //!< hevc main profile ++#define MVHE_HEVC_PROFILE_MAIN10 2 //!< hevc main10 profile ++#define MVHE_HEVC_LEVEL_1 30 //!< hevc level 1.0 ++#define MVHE_HEVC_LEVEL_2 60 //!< hevc level 2.0 ++#define MVHE_HEVC_LEVEL_2_1 63 //!< hevc level 2.1 ++#define MVHE_HEVC_LEVEL_3 90 //!< hevc level 3.0 ++#define MVHE_HEVC_LEVEL_3_1 93 //!< hevc level 3.1 ++#define MVHE_HEVC_LEVEL_4 120 //!< hevc level 4.0 ++#define MVHE_HEVC_LEVEL_4_1 124 //!< hevc level 4.1 ++#define MVHE_HEVC_LEVEL_5 150 //!< hevc level 5.0 ++#define MVHE_HEVC_LEVEL_5_1 153 //!< hevc level 5.1 ++#define MVHE_HEVC_LEVEL_5_2 156 //!< hevc level 5.2 ++#define MVHE_HEVC_LEVEL_6 180 //!< hevc level 6.0 ++#define MVHE_HEVC_LEVEL_6_1 183 //!< hevc level 6.1 ++#define MVHE_HEVC_LEVEL_6_2 186 //!< hevc level 6.2 ++#define MVHE_FLAGS_CMPRY (1<< 0) ++#define MVHE_FLAGS_COMPR (MVHE_FLAGS_CMPRY) ++ ++//! mvhe_parm is used to apply/query configs out of streaming period. ++typedef union mvhe_parm ++{ ++ //! mvhe_parm_e indicates parameter type. ++ enum mvhe_parm_e ++ { ++ MVHE_PARM_IDX=0, //!< parameters of streamid: query stream-id. ++ MVHE_PARM_RES, //!< parameters of resource: including image's resolution and format ++ MVHE_PARM_FPS, //!< parameters of fps: fraction of framerate. ++ MVHE_PARM_GOP, //!< parameters of gop: ip frame period. ++ MVHE_PARM_BPS, //!< parameters of bps: bit per second. ++ MVHE_PARM_HEVC, //!< parameters of hevc: codec settings. ++ MVHE_PARM_VUI, //!< parameters of vui: vui params. ++ MVHE_PARM_LTR, //!< parameters of ltr: long term reference. ++ MVHE_PARM_PEN, //!< parameters of pen: penalty params. ++ } type; //!< indicating which kind of mvhe_parm is. ++ ++ //! get ver parameter out of streaming. ++ struct mvhe_parm_idx ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MMFE_PARM_IDX. ++ unsigned int i_stream; //!< stream-id. ++ } idx; //!< used to get version/id parameters. ++ ++ //! set res parameters out of streaming. ++ struct mvhe_parm_res ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_RES. ++ int i_pict_w; //!< picture width. ++ int i_pict_h; //!< picture height. ++ enum mvhe_pixfmt i_pixfmt; //!< pixel format. ++ int i_outlen; //!< output length: '<0' mmap-out, '=0' default, '>0' aligned to 512K ++ int i_flags; //!< flags. ++#define STREAM_ID_DEFAULT 0xFFFF ++ int i_strid; //!< stream id, use STREAM_ID_DEFAULT as older naming ++ } res; //!< used to set resource parameters. ++ ++ //! set fps parameters out of streaming. ++ struct mvhe_parm_fps ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_FPS. ++ int i_num; //!< numerator of fps. ++ int i_den; //!< denominator of fps. ++ } fps; //!< used to set fraction of frame rate. ++ ++ //! set gop parameters out of streaming. ++ struct mvhe_parm_gop ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_GOP. ++ int i_pframes; //!< p-frames count per i-frame. ++ int i_bframes; //!< b-frames count per i/p-frame. ++ } gop; //!< used to set gop structure. ++ ++ //! set bps parameters out of streaming. ++ struct mvhe_parm_bps ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_BPS. ++ int i_method; //!< rate-control method. ++ int i_ref_qp; //!< ref. QP. ++ int i_bps; //!< bitrate. ++ } bps; //!< used to set bit rate controller. ++ ++ //! set hevc parameters out of streaming. ++ struct mvhe_parm_hevc ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_HEVC. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_log2_max_cb_size; //!< max ctb size. ++ unsigned char i_log2_min_cb_size; //!< min ctb size. ++ unsigned char i_log2_max_tr_size; //!< max trb size. ++ unsigned char i_log2_min_tr_size; //!< min trb size. ++ unsigned char i_tr_depth_intra; //!< tr depth intra. ++ unsigned char i_tr_depth_inter; //!< tr depth inter. ++ unsigned char b_scaling_list_enable; //!< scaling list enable. ++ unsigned char b_ctu_qp_delta_enable; //!< ctu dqp enable. ++ unsigned char b_sao_enable; //!< sao enable. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ unsigned char b_strong_intra_smoothing; //!< strong intra smoothing. ++ unsigned char b_constrained_intra_pred; //!< intra prediction constrained. ++ unsigned char b_deblocking_override_enable; //!< deblocking override enable. ++ unsigned char b_deblocking_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } hevc; //!< used to set codec configuration. ++ ++ //! set vui parameter out of streaming. ++ struct mvhe_parm_vui ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_VUI. ++ int b_video_full_range; ++ int b_timing_info_pres; ++ } vui; //!< used to set codec configuration. ++ ++ //! set ltr parameter out of streaming. ++ struct mvhe_parm_ltr ++ { ++ enum mvhe_parm_e i_type; //!< i_type MUST be MVHE_PARM_LTR. ++ int b_long_term_reference; //!< toggle ltr mode ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set ltr configuration. ++ ++ unsigned char byte[64]; //!< dummy bytes ++} mvhe_parm; ++ ++//! mvhe_ctrl is used to apply/query control configs during streaming period. ++typedef union mvhe_ctrl ++{ ++ //! mvhe_ctrl_e indicates control type. ++ enum mvhe_ctrl_e ++ { ++ MVHE_CTRL_SEQ=0,//!< control of sequence: includes resolution, pixel format and frame-rate. ++ MVHE_CTRL_HEVC, //!< control of hevc codec settings. ++ MVHE_CTRL_ROI, //!< control of roi setting changing. ++ MVHE_CTRL_SPL, //!< control of slice spliting. ++ MVHE_CTRL_DBK, //!< control of deblocking. ++ MVHE_CTRL_BAC, //!< control of cabac_init. ++ MVHE_CTRL_LTR, //!< control of long term reference. ++ } type; //!< indicating which kind of mvhe_ctrl is. ++ ++ //! set seq control during streaming. ++ struct mvhe_ctrl_seq ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_SEQ. ++ enum mvhe_pixfmt i_pixfmt; //!< pixel-format ++ short i_pixelw; //!< pixels in width. ++ short i_pixelh; //!< pixels in height. ++ short n_fps; //!< numerator of frame-rate. ++ short d_fps; //!< denominator of frame-rate. ++ } seq; //!< used to start new sequence. ++ ++ //! set hevc control during streaming. ++ struct mvhe_ctrl_hevc ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_SEQ. ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_log2_max_cb_size; //!< max ctb size. ++ unsigned char i_log2_min_cb_size; //!< min ctb size. ++ unsigned char i_log2_max_tr_size; //!< max trb size. ++ unsigned char i_log2_min_tr_size; //!< min trb size. ++ unsigned char i_tr_depth_intra; //!< tr depth intra. ++ unsigned char i_tr_depth_inter; //!< tr depth inter. ++ unsigned char b_scaling_list_enable; //!< scaling list enable. ++ unsigned char b_ctu_qp_delta_enable; //!< ctu dqp enable. ++ unsigned char b_sao_enable; //!< sao enable. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ unsigned char b_strong_intra_smoothing; //!< strong intra smoothing. ++ unsigned char b_constrained_intra_pred; //!< intra prediction constrained. ++ unsigned char b_deblocking_override_enable; //!< deblocking override enable. ++ unsigned char b_deblocking_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } hevc; //!< used to set hevc codec setting. ++ ++ //! set roi control during streaming. ++ struct mvhe_ctrl_roi ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_ROI. ++ short i_index; //!< roi index. ++ short i_dqp; //!< dqp: -15~0, =0: disable, !=0: enable. ++ unsigned short i_cbx; //!< roi region posotion-X. (in CTB unit) ++ unsigned short i_cby; //!< roi region posotion-Y. (in CTB unit) ++ unsigned short i_cbw; //!< roi region rectangle-W. (in CTB unit) ++ unsigned short i_cbh; //!< roi region rectangle-H. (in CTB unit) ++ } roi; //!< used to set roi region and dqp. ++ ++ //! set spl control during streaming. ++ struct mvhe_ctrl_spl ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_SPL. ++ int i_rows; //!< split slice by cb-rows. ++ int i_bits; //!< split slice by cb-bits. ++ } spl; //!< used to set slice splitting. ++ ++ //! set dbk control during streaming. ++ struct mvhe_ctrl_dbk { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_DBK. ++ unsigned char b_override; //!< override deblocking setting. ++ unsigned char b_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } dbk; //!< used to set deblocking splitting. ++ ++ //! set bac control during streaming. ++ struct mvhe_ctrl_bac ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_BAC. ++ int b_init; //!< cabac_init_flag: 0,1 ++ } bac; //!< used to set cabac_init. ++ ++ //! set ltr parameter during streaming. ++ struct mvhe_ctrl_ltr ++ { ++ enum mvhe_ctrl_e i_type; //!< i_type MUST be MVHE_CTRL_LTR. ++ int b_enable_pred; //!< ltr mode, means LTR P-frame can be ref.; 0: P ref. I, 1: P ref. P ++ int i_ltr_period; //!< ltr period ++ } ltr; //!< used to set long term reference. ++ ++ unsigned char byte[64]; //!< dummy bytes ++} mvhe_ctrl; ++ ++#define MVHE_FLAGS_IDR (1<< 0) //!< request IDR. ++#define MVHE_FLAGS_DISPOSABLE (1<< 1) //!< request unref-pic. ++#define MVHE_FLAGS_NIGHT_MODE (1<< 2) //!< night mode. ++#define MVHE_FLAGS_LTR_PFRAME (1<< 4) //!< LTR P-frame flag. ++#define MVHE_FLAGS_SOP (1<<30) //!< start of picture. ++#define MVHE_FLAGS_EOP (1<<31) //!< end of picture. ++#define MVHE_MEMORY_USER (0) //!< user mode. (pass pointer) ++#define MVHE_MEMORY_MMAP (1) //!< mmap mode. (pass physic address) ++ ++//! mvhe_buff is used to exchange video/obits buffer between user and driver during streaming period. ++typedef struct mvhe_buff ++{ ++ int i_index; //!< index of buffer: '-1' invalid, '>=0' valid. ++ int i_flags; //!< flags for request/reports. ++ short i_memory; //!< memory mode of user/mmap. ++ short i_width; //!< pixels in width. (if buffer is image) ++ short i_height; //!< pixels in height. (if buffer is image) ++ short i_stride; //!< pixels in stride. (if buffer is image) ' ++ ++//////////////////////////////////////////////////////////////////////////////// ++// Definitions ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! Magic Number of RQCT. ++#define MAGIC_RQCT ('q') ++//! Use to Query version number of user interface. ++#define IOCTL_RQCT_VERSION _IOWR(MAGIC_RQCT, 0,unsigned int) ++//! Use to set rq-control during streaming. ++#define IOCTL_RQCT_S_CONF _IOWR(MAGIC_RQCT, 1,rqct_conf) ++//! Use to get rq-control during streaming. ++#define IOCTL_RQCT_G_CONF _IOWR(MAGIC_RQCT, 2,rqct_conf) ++ ++#endif//_MDRV_RQCT_IO_H_ ++//! @} +diff --git a/drivers/mstar/include/mdrv_rqct_st.h b/drivers/mstar/include/mdrv_rqct_st.h +new file mode 100644 +index 00000000..a7fe404d +--- /dev/null ++++ b/drivers/mstar/include/mdrv_rqct_st.h +@@ -0,0 +1,137 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//! @file mdrv_rqct_st.h ++//! @author MStar Semiconductior Inc. ++//! @brief VHE Driver IOCTL User's Interface. ++//! \ingroup rqct_group VHE driver ++//! @{ ++#ifndef _MDRV_RQCT_ST_H_ ++#define _MDRV_RQCT_ST_H_ ++ ++#define RQCTIF_MAJ 1 //!< major version: Major number of driver-I/F version. ++#define RQCTIF_MIN 1 //!< minor version: Minor number of driver-I/F version. ++#define RQCTIF_EXT 1 //!< extended code: Extended number of version. It should increase when "mdrv_rqct_io.h/mdrv_rqct_st.h" changed. ++ ++//! RQCT Interface version number. ++#define RQCTIF_VERSION_ID ((RQCTIF_MAJ<<22)|(RQCTIF_MIN<<12)|(RQCTIF_EXT)) ++//! Acquire version number. ++#define RQCTIF_GET_VER(v) (((v)>>12)) ++//! Acquire major version number. ++#define RQCTIF_GET_MJR(v) (((v)>>22)&0x3FF) ++//! Acquire minor version number. ++#define RQCTIF_GET_MNR(v) (((v)>>12)&0x3FF) ++//! Acquire extended number. ++#define RQCTIF_GET_EXT(v) (((v)>> 0)&0xFFF) ++ ++//! rqct-method : support 3 types - CQP, CBR, VBR. ++enum rqct_method ++{ ++ RQCT_METHOD_CQP=0, //!< constant QP. ++ RQCT_METHOD_CBR, //!< constant bitrate. ++ RQCT_METHOD_VBR, //!< variable bitrate. ++}; ++ ++//! mvhe_superfrm_mode indicates super frame mechanism ++enum rqct_superfrm_mode ++{ ++ RQCT_SUPERFRM_NONE=0, //!< super frame mode none. ++ RQCT_SUPERFRM_DISCARD, //!< super frame mode discard. ++ RQCT_SUPERFRM_REENCODE, //!< super frame mode reencode. ++}; ++ ++//! rqct_conf is used to apply/query rq-configs during streaming period. ++typedef union rqct_conf ++{ ++ //! rqct-config type. ++ enum rqct_conf_e ++ { ++ RQCT_CONF_SEQ=0, //!< set sequence rate-control. ++ RQCT_CONF_DQP, //!< set delta-qp between I/P. ++ RQCT_CONF_QPR, //!< set range-qp. ++ RQCT_CONF_LOG, //!< turn on/off rqct log message. ++ RQCT_CONF_PEN, //!< penalties for mfe. ++ RQCT_CONF_SPF, //!< super frame settings. ++ RQCT_CONF_LTR, //!< long term reference setting ++ RQCT_CONF_END, //!< endof rqct-conf-enum. ++ } type; //!< indicating config. type. ++ ++ //! set rqct seq. config. ++ struct _seq ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_SEQ. ++ enum rqct_method i_method; //!< indicating rqct-method. ++ int i_period; //!< ip-period. ++ int i_leadqp; //!< leadqp. ++ int i_btrate; //!< btrate. ++ } seq; //!< rqct configs of seq. setting. ++ ++ //! set rqct lt config ++ struct _ltr ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CONF_LTR. ++ int i_period; //!< ltr period ++ } ltr; ++ ++ //! set rqct dqp. config. ++ struct _dqp ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_DQP. ++ int i_dqp; //!< dif-qp between I/P. ++ } dqp; //!< rqct configs of dqp. setting. ++ ++ //! set rqct qpr. config. ++ struct _qpr ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_QPR. ++ int i_iupperq; //!< I frame upperq. ++ int i_ilowerq; //!< I frame lowerq. ++ int i_pupperq; //!< P frame upperq. ++ int i_plowerq; //!< P frame lowerq. ++ } qpr; //!< rqct configs of dqp. setting. ++ ++ //! set rqct log. config. ++ struct _log ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_LOG. ++ int b_logm; //!< switch of log-message. ++ } log; //!< rqct configs of dqp. setting. ++ ++ //! set rqct pen. config. ++ struct _pen ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be RQCT_CFG_PEN. ++ short b_i16pln; //!< enable intra16 planar. ++ short i_peni4x; //!< penalty intra4x4. ++ short i_peni16; //!< penalty intra16. ++ short i_penint; //!< penalty inter. ++ short i_penYpl; //!< penalty planar luma. ++ short i_penCpl; //!< penalty planar cbcr. ++ } pen; //!< rqct configs of dqp. setting. ++ ++ struct _spf ++ { ++ enum rqct_conf_e i_type; //!< i_type MUST be MVHE_PARM_SPF. ++ enum rqct_superfrm_mode i_spfrm; ++ int i_IFrmBitsThr; ++ int i_PFrmBitsThr; ++ int i_BFrmBitsThr; ++ } spf; //!< used to set super frame skip mode configuration. ++} rqct_conf; ++ ++#endif//_MDRV_RQCT_ST_H_ ++//! @} +diff --git a/drivers/mstar/include/mdrv_sca_io.h b/drivers/mstar/include/mdrv_sca_io.h +new file mode 100644 +index 00000000..b96cbee0 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_sca_io.h +@@ -0,0 +1,171 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_SCA_IO_H ++#define _MDRV_SCA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++#include "mdrv_sca_st.h" ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++#define MSIF_SCA_LIB_CODE {'S','C','A','\0'} ++#define MSIF_SCA_BUILDNUM {'_','0','1','\0'} ++#define MSIF_SCA_LIBVER (2) ++#define MSIF_SCA_CHANGELIST (677450) ++ ++//IO Ctrl defines: ++#define IOCTL_SCA_CONNECT_NR (0) ++#define IOCTL_SCA_DISCONNECT_NR (1) ++#define IOCTL_SCA_SET_TIMING_WINDOW_NR (2) ++#define IOCTL_SCA_SET_MVOP_NR (3) ++#define IOCTL_SCA_SET_DISPLAY_MUTE_NR (4) ++#define IOCTL_SCA_YPBPR_VGA_MODE_MON_PAR_NR (5) ++#define IOCTL_SCA_GET_MODE_NR (6) ++#define IOCTL_SCA_SET_VE_NR (7) ++#define IOCTL_SCA_SET_WINDOW_ONOFF_NR (8) ++#define IOCTL_SCA_SET_COLOR_KEY_NR (9) ++#define IOCTL_SCA_SET_MVOP_BASEADDR_NR (10) ++#define IOCTL_SCA_GET_MVOP_BASEADDR_NR (11) ++#define IOCTL_SCA_CHANGE_WINDOW_NR (12) ++#define IOCTL_SCA_SET_PICTURE_NR (13) ++#define IOCTL_SCA_GET_PICTURE_NR (14) ++#define IOCTL_SCA_SET_OUTPUT_TIMING_NR (15) ++#define IOCTL_SCA_CALIBRATION_NR (16) ++#define IOCTL_SCA_LOAD_ADC_SETTING_NR (17) ++#define IOCTL_SCA_AVD_CONNECT_NR (18) ++#define IOCTL_SCA_AVD_CHEKC_VIDEO_STD_NR (19) ++#define IOCTL_SCA_SET_CONSTANTAPLHA_VALUE_NR (20) ++#define IOCTL_SCA_GET_LIB_VER_NR (21) ++#define IOCTL_SCA_SET_DISP_INTR_NR (22) ++#define IOCTL_SCA_GET_DISP_INTR_NR (23) ++#define IOCTL_SCA_RW_REGISTER_NR (24) ++#define IOCTL_SCA_GET_ACE_INFO_NR (25) ++#define IOCTL_SCA_GET_DLC_INFO_NR (26) ++#define IOCTL_SCA_GET_DISP_PATH_CONFIG_NR (27) ++#define IOCTL_SCA_SET_MIRRORCONFIG_NR (28) ++#define IOCTL_SCA_SET_PQ_BIN_NR (29) ++#define IOCTL_SCA_SET_DIP_CONFIG_NR (30) ++#define IOCTL_SCA_GET_DISP_INTR_STATUS_NR (31) ++#define IOCTL_SCA_SET_HDMITX_CONFIG_NR (32) ++#define IOCTL_SCA_SET_DIP_WONCE_TRIG_BASE_NR (33) ++#define IOCTL_SCA_SET_FREEZE_CONFIG_NR (34) ++#define IOCTL_SCA_INIT_MST701_NR (35) ++#define IOCTL_SCA_GEOMETRY_CALIBRATION_NR (36) ++#define IOCTL_SCA_LOAD_GEOMETRY_SETTING_NR (37) ++#define IOCTL_SCA_SET_ANALOG_POLLING_CONFIG_NR (38) ++#define IOCTL_SCA_SET_CLONE_SCREEN_CONFIG_NR (39) ++#define IOCTL_SCA_GET_CLONE_SCREEN_CONFIG_NR (40) ++#define IOCTL_SCA_SET_PNL_SCC_CONFIG_NR (41) ++#define IOCTL_SCA_SET_CONSTANTALPHA_STATE_NR (42) ++#define IOCTL_SCA_SET_PNL_TIMING_CONFIG_NR (43) ++#define IOCTL_SCA_GET_MONITOR_STATUS_CONFIG_NR (44) ++#define IOCTL_SCA_SET_USER_DISPLAY_CONFIG_NR (45) ++#define IOCTL_SCA_SET_DISPLAY_MUTE_COLOR_NR (46) ++#define IOCTL_SCA_SET_CLONE_SCREEN_RATIO_NR (47) ++#define IOCTL_SCA_SET_DLC_INIT_CONFIG_NR (48) ++#define IOCTL_SCA_SET_DLC_ONOFF_CONFIG_NR (49) ++#define IOCTL_SCA_SET_UEVENT_CONFIG_NR (50) ++#define IOCTL_SCA_SET_CVBSOUT_DAC_CONFIG_NR (51) ++#define IOCTL_SCA_SET_USER_DIPLAY_CONFIG_EX_NR (52) ++#define IOCTL_SCA_SET_CAMERA_INPUTTIMING_CONFIG_NR (53) ++#ifdef __BOOT_PNL__//paul_test ++#define IOCTL_SCA_SET_PQ_BIN_IBC_NR (54) ++#define IOCTL_SCA_SET_PQ_BIN_ICC_NR (55) ++#define IOCTL_SCA_SET_PQ_BIN_IHC_NR (56) ++#define IOCTL_SCA_MAX_NR (57) ++#else ++#define IOCTL_SCA_MAX_NR (54) ++#endif ++ ++ ++ ++ ++// use 'm' as magic number ++#define IOCTL_SCA_MAGIC ('2') ++ ++#define IOCTL_SCA_CONNECT _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_CONNECT_NR) ++#define IOCTL_SCA_DISCONNECT _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_DISCONNECT_NR) ++#define IOCTL_SCA_SET_TIMING_WINDOW _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_TIMING_WINDOW_NR) ++#define IOCTL_SCA_SET_MVOP _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_MVOP_NR) ++#define IOCTL_SCA_SET_DISPLAY_MUTE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DISPLAY_MUTE_NR) ++#define IOCTL_SCA_YPBPR_VGA_MODE_MON_PAR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_YPBPR_VGA_MODE_MON_PAR_NR) ++#define IOCTL_SCA_GET_MODE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_MODE_NR) ++#define IOCTL_SCA_SET_VE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_VE_NR) ++#define IOCTL_SCA_SET_WINDOW_ONOFF _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_WINDOW_ONOFF_NR) ++#define IOCTL_SCA_SET_COLOR_KEY _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_COLOR_KEY_NR) ++#define IOCTL_SCA_SET_MVOP_BASEADDR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_MVOP_BASEADDR_NR) ++#define IOCTL_SCA_GET_MVOP_BASEADDR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_MVOP_BASEADDR_NR) ++#define IOCTL_SCA_CHANGE_WINDOW _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_CHANGE_WINDOW_NR) ++#define IOCTL_SCA_SET_PICTURE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PICTURE_NR) ++#define IOCTL_SCA_GET_PICTURE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_PICTURE_NR) ++#define IOCTL_SCA_SET_OUTPUT_TIMING _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_OUTPUT_TIMING_NR) ++#define IOCTL_SCA_CALIBRATION _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_CALIBRATION_NR) ++#define IOCTL_SCA_LOAD_ADC_SETTING _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_LOAD_ADC_SETTING_NR) ++#define IOCTL_SCA_AVD_CONNECT _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_AVD_CONNECT_NR) ++#define IOCTL_SCA_AVD_CHECK_VIDEO_STD _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_AVD_CHEKC_VIDEO_STD_NR) ++#define IOCTL_SCA_GET_LIB_VER _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_LIB_VER_NR) ++#define IOCTL_SCA_SET_CONSTANTALPHA_VALUE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CONSTANTAPLHA_VALUE_NR) ++#define IOCTL_SCA_SET_DISP_INTR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DISP_INTR_NR) ++#define IOCTL_SCA_GET_DISP_INTR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DISP_INTR_NR) ++#define IOCTL_SCA_RW_REGISTER _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_RW_REGISTER_NR) ++#define IOCTL_SCA_GET_ACE_INFO _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_ACE_INFO_NR) ++#define IOCTL_SCA_GET_DLC_INFO _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DLC_INFO_NR) ++#define IOCTL_SCA_GET_DISP_PATH_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DISP_PATH_CONFIG_NR) ++#define IOCTL_SCA_SET_MIRROR_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_MIRRORCONFIG_NR) ++#define IOCTL_SCA_SET_PQ_BIN _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_NR) ++#define IOCTL_SCA_SET_DIP_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DIP_CONFIG_NR) ++#define IOCTL_SCA_GET_DISP_INTR_STATUS _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_DISP_INTR_STATUS_NR) ++#define IOCTL_SCA_SET_HDMITX_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_HDMITX_CONFIG_NR) ++#define IOCTL_SCA_SET_DIP_WONCE_BASE_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DIP_WONCE_TRIG_BASE_NR) ++#define IOCTL_SCA_SET_FREEZE_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_FREEZE_CONFIG_NR) ++#define IOCTL_SCA_INIT_MST701 _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_INIT_MST701_NR) ++#define IOCTL_SCA_GEOMETRY_CALIBRATION _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GEOMETRY_CALIBRATION_NR) ++#define IOCTL_SCA_LOAD_GEOMETRY_SETTING _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_LOAD_GEOMETRY_SETTING_NR) ++#define IOCTL_SCA_SET_ANALOG_POLLING_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_ANALOG_POLLING_CONFIG_NR) ++#define IOCTL_SCA_SET_CLONE_SCREEN_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CLONE_SCREEN_CONFIG_NR) ++#define IOCTL_SCA_GET_CLONE_SCREEN_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_CLONE_SCREEN_CONFIG_NR) ++#define IOCTL_SCA_SET_PNL_SSC_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PNL_SCC_CONFIG_NR) ++#define IOCTL_SCA_SET_CONSTANTALPHA_STATE _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CONSTANTALPHA_STATE_NR) ++#define IOCTL_SCA_SET_PNL_TIMING_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PNL_TIMING_CONFIG_NR) ++#define IOCTL_SCA_GET_MONITOR_STATUS_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_GET_MONITOR_STATUS_CONFIG_NR) ++#define IOCTL_SCA_SET_USER_DISPLAY_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_USER_DISPLAY_CONFIG_NR) ++#define IOCTL_SCA_SET_DISPLAY_MUTE_COLOR _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DISPLAY_MUTE_COLOR_NR) ++#define IOCTL_SCA_SET_CLONE_SCREEN_RATIO _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CLONE_SCREEN_RATIO_NR) ++#define IOCTL_SCA_SET_DLC_INIT_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DLC_INIT_CONFIG_NR) ++#define IOCTL_SCA_SET_DLC_ONOFF_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_DLC_ONOFF_CONFIG_NR) ++#define IOCTL_SCA_SET_UEVENT_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_UEVENT_CONFIG_NR) ++#define IOCTL_SCA_SET_CVBSOUT_DAC_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CVBSOUT_DAC_CONFIG_NR) ++#define IOCTL_SCA_SET_USER_DISPLAY_CONFIG_EX _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_USER_DIPLAY_CONFIG_EX_NR) ++#define IOCTL_SCA_SET_CAMERA_INPUTTIMING_CONFIG _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_CAMERA_INPUTTIMING_CONFIG_NR) ++#ifdef __BOOT_PNL__//paul_test ++#define IOCTL_SCA_SET_PQ_BIN_IBC _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_IBC_NR) ++#define IOCTL_SCA_SET_PQ_BIN_ICC _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_ICC_NR) ++#define IOCTL_SCA_SET_PQ_BIN_IHC _IO(IOCTL_SCA_MAGIC, IOCTL_SCA_SET_PQ_BIN_IHC_NR) ++#endif ++ ++#endif //_MDRV_GFLIP_IO_H +diff --git a/drivers/mstar/include/mdrv_sca_st.h b/drivers/mstar/include/mdrv_sca_st.h +new file mode 100644 +index 00000000..ea90793b +--- /dev/null ++++ b/drivers/mstar/include/mdrv_sca_st.h +@@ -0,0 +1,945 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// @file mdrv_sca_io.h ++// @brief GFlip KMD Driver Interface ++// @author MStar Semiconductor Inc. ++////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_SCA_ST_H ++#define _MDRV_SCA_ST_H ++ ++#if !defined(MS_U8) && !defined(MS_BOOL) ++#define MS_U8 unsigned char ++#define MS_U16 unsigned short ++#define MS_U32 unsigned long ++#define MS_U64 unsigned long long ++#define MS_BOOL unsigned char ++#define MS_S16 signed short ++#endif ++ ++//============================================================================= ++// structure & Enum ++//============================================================================= ++typedef enum ++{ ++ SCA_DEST_MAIN = 0, ++ SCA_DEST_SUB = 1, ++ SCA_DEST_MAIN_1 = 2, ++ SCA_DEST_MAIN_2 = 3, ++ SCA_DEST_SUB_2 = 4, ++ SCA_DEST_CVBSO = 5, ++ SCA_DEST_HDMITx = 6, ++ SCA_DEST_NUM, ++}SCA_DEST_TYPE; ++ ++ ++typedef enum ++{ ++ SCA_SRC_VGA, ++ SCA_SRC_YPBPR, ++ SCA_SRC_CVBS, ++ SCA_SRC_CVBS2, ++ SCA_SRC_CVBS3, ++ SCA_SRC_SVIDEO, // Add S-video input source // ++ SCA_SRC_DTV, ++ SCA_SRC_SC0_VOP, ++ SCA_SRC_SC1_VOP, ++ SCA_SRC_SC2_VOP, ++ SCA_SRC_BT656, ++ SCA_SRC_BT656_1, ++ SCA_SRC_CAMERA, ++ SCA_SRC_NUM, ++}SCA_SRC_TYPE; ++ ++typedef enum ++{ ++ SCA_MVOP_INPUT_DRAM, ++ SCA_MVOP_INPUT_H264, ++ SCA_MVOP_INPUT_MVD, ++ SCA_MVOP_INPUT_RVD, ++ SCA_MVOP_INPUT_CLIP, ++ SCA_MVOP_INPUT_JPD, ++ SCA_MVOP_INPUT_HVD_3DLR, ++ SCA_MVOP_INPUT_MVD_3DLR, ++ SCA_MVOP_INPUT_UNKNOWN, ++} SCA_MVOP_INPUT_SEL; ++ ++ ++typedef enum ++{ ++ SCA_MODE_PARSING_SUPPORT, ++ SCA_MODE_PARSING_UNSUPPORT, ++ SCA_MODE_PARSING_FAIL, ++}SCA_PARSING_MODE_STATUS; ++ ++typedef enum ++{ ++ SCA_VE_OUTPUT_NTSC, ++ SCA_VE_OUTPUT_PAL, ++}SCA_VE_OUTPUT_STD; ++ ++ ++typedef enum ++{ ++ SCA_MVOP_TILE_8x32, ++ SCA_MVOP_TILE_16x32, ++ SCA_MVOP_TILE_NONE, ++}SCA_MVOP_TILE_TYPE; ++ ++typedef enum ++{ ++ SCA_MODE_MONITOR_NOSYNC = 0, ///< Input timing stable, no input sync detected ++ SCA_MODE_MONITOR_STABLE_SUPPORT_MODE, ///< Input timing stable, has stable input sync and support this timing ++ SCA_MODE_MONITOR_STABLE_UN_SUPPORT_MODE, ///< Input timing stable, has stable input sync but this timing is not supported ++ SCA_MODE_MONITOR_UNSTABLE, ///< Timing change, has to wait InfoFrame if HDMI input ++}SCA_MODE_MOINITOR_STATUS; ++ ++ ++typedef enum ++{ ++ SCA_PICTURE_BRIGHTNESS = 0x01, ++ SCA_PICTURE_CONTRAST = 0x02, ++ SCA_PICTURE_HUE = 0x04, ++ SCA_PICTURE_SATURATION = 0x08, ++ SCA_PICTURE_SHARPNESS = 0x10, ++ SCA_PICTURE_COLOR_TEMPERATURE = 0x20, ++}SCA_PICTURE_TYPE; ++ ++typedef enum ++{ ++ SCA_COLOR_TEMP_COOL, ++ SCA_COLOR_TEMP_NORMAL, ++ SCA_COLOR_TEMP_WARM, ++}SCA_COLOR_TEMPERATURE_TYPE; ++ ++typedef enum ++{ ++ SCA_OUTPUT_480_I_60, ++ SCA_OUTPUT_480_P_60, ++ SCA_OUTPUT_576_I_50, ++ SCA_OUTPUT_576_P_50, ++ SCA_OUTPUT_720_P_50, ++ SCA_OUTPUT_720_P_60, ++ SCA_OUTPUT_1080_P_50, ++ SCA_OUTPUT_1080_P_60, ++ SCA_OUTPUT_480_P_30, ++ SCA_OUTPUT_720_P_30, ++}SCA_OUTPUT_TIMING_TYPE; ++ ++typedef enum ++{ ++ SCA_REG_R_BYTE, ++ SCA_REG_W_BYTE, ++ SCA_REG_XC_R2BYTEMSK, ++ SCA_REG_XC_W2BYTEMSK, ++}SCA_RW_REG_TYPE; ++ ++ ++typedef enum ++{ ++ SCA_DISP_PRI_NONE = 0, ++ SCA_DISP_PRI_NORMAL = 1, ++ SCA_DISP_PRI_CAR_BACK = 2, ++}SCA_DISP_PRIORITY_TYPE; ++ ++typedef enum ++{ ++ SCA_PQ_BIN_ID_STD_MAIN = 0x0, ++ SCA_PQ_BIN_ID_STD_SUB = 0x1, ++ SCA_PQ_BIN_ID_STD_SC1_MAIN = 0x2, ++ SCA_PQ_BIN_ID_STD_SC2_MAIN = 0x3, ++ SCA_PQ_BIN_ID_STD_SC2_SUB = 0x4, ++ SCA_PQ_BIN_ID_EXT_MAIN = 0x5, ++ SCA_PQ_BIN_ID_EXT_SUB = 0x6, ++ SCA_PQ_BIN_ID_EXT_SC1_MAIN = 0x7, ++ SCA_PQ_BIN_ID_EXT_SC2_MAIN = 0x8, ++ SCA_PQ_BIN_ID_EXT_SC2_SUB = 0x9, ++ SCA_PQ_BIN_ID_NUM, ++ SCA_PQ_BIN_ID_NONE = 0xFF, ++}SCA_PQ_BIN_ID_TYPE; ++ ++typedef enum ++{ ++ SCA_DIP_DEST_FMT_YC422, ++ SCA_DIP_DEST_FMT_RGB565, ++ SCA_DIP_DEST_FMT_ARGB8888, ++ SCA_DIP_DEST_FMT_YC420_MVOP, ++ SCA_DIP_DEST_FMT_YC420_MFE, ++}SCA_DIP_DEST_FMT_TYPE; ++ ++typedef enum ++{ ++ SCA_DIP_TRIGGER_LOOP = 0, ++ SCA_DIP_TRIGGER_ONCE, ++}SCA_DIP_TRIGGER_TYPE; ++ ++typedef enum ++{ ++ SCA_HDMITX_OUT_HDMI, ++ SCA_HDMITX_OUT_HDMI_HDCP, ++}SCA_HDMITX_MODE_TYPE; ++ ++typedef enum ++{ ++ SCA_HDMITX_480_I_60, ++ SCA_HDMITX_480_P_60, ++ SCA_HDMITX_576_I_50, ++ SCA_HDMITX_576_P_50, ++ SCA_HDMITX_720_P_50, ++ SCA_HDMITX_720_P_60, ++ SCA_HDMITX_1080_I_50, ++ SCA_HDMITX_1080_I_60, ++ SCA_HDMITX_1080_P_50, ++ SCA_HDMITX_1080_P_60, ++ SCA_HDMITX_1080_P_30, ++ SCA_HDMITX_1080_P_25, ++ SCA_HDMITX_1080_P_24, ++}SCA_HDMITX_OUTPUT_TIMINE_TYPE; ++ ++typedef enum ++{ ++ SCA_HDMITX_OUTPUT_COLOR_RGB, ++ SCA_HDMITX_OUTPUT_COLOR_YUV, ++}SCA_HDMITX_OUTPUT_COLOR_TYPE; ++ ++typedef enum ++{ ++ SCA_CLONE_SCREEN_NONE, ++ SCA_CLONE_SCREEN_GOP, ++}SCA_CLONE_SCREEN_TYPE; ++ ++ ++typedef enum ++{ ++ SCA_DISPLAY_MUTE_BLACK, ++ SCA_DISPLAY_MUTE_WHITE, ++ SCA_DISPLAY_MUTE_BLUE, ++ SCA_DISPLAY_MUTE_RED, ++ SCA_DISPLAY_MUTE_GREEN, ++}SCA_DISPLAY_MUTE_COLOR_TYPE; ++ ++ ++//------------------------------------------------------------------------------ ++typedef struct ++{ ++ SCA_SRC_TYPE enSrcType; ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bAutoDetect; ++ SCA_DISP_PRIORITY_TYPE enPriType; ++ MS_U32 dwUID; ++}SCA_CONNECT_CONFIG, *PSCA_CONNECT_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16HSize; ++ MS_U16 u16VSize; ++ MS_U32 u32YOffset; ++ MS_U32 u32UVOffset; ++ MS_BOOL bSD; ++ MS_BOOL bYUV422; ++ MS_BOOL bProgressive; ++ MS_BOOL bUV7bit; ++ MS_BOOL bDramRdContd; ++ MS_BOOL bField; ++ MS_BOOL b422pack; ++ MS_U16 u16StripSize; ++ SCA_MVOP_INPUT_SEL enInputSel; ++}SCA_MVOP_IN_CONFIG, *PSCA_MVOP_IN_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16HorSize; ++ MS_U16 u16VerSize; ++ MS_U16 u16FrameRate; ++ MS_U8 u8AspectRate; ++ MS_U8 u8Interlace; ++}SCA_MVOP_OUT_CONFIG, *PSCA_MVOP_OUT_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_MVOP_TILE_TYPE enTileType; ++ SCA_MVOP_IN_CONFIG stInConfig; ++ SCA_MVOP_OUT_CONFIG stOutConfig; ++}SCA_MVOP_CONFIG, *PSCA_MVOP_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bUpdate; ++ MS_U16 u16InputVTotal; ++ MS_BOOL bInterlace; ++ MS_U16 u16InputVFreq; ++}SCA_TIMING_CONFIG, *PSCA_TIMING_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 x; ++ MS_U16 y; /// valid, valid -> none) ++ MS_U8 INT_F1_CSOG :1; ++ MS_U8 INT_F2_ATS_READY :1; ///< scaler dosen't have this interrupt now ++ MS_U8 INT_F1_ATS_READY :1; ++ MS_U8 INT_F2_ATP_READY :1; ///< auto phase ready interrupt ++ MS_U8 INT_F1_ATP_READY :1; ++ MS_U8 INT_F2_ATG_READY :1; ///< scaler dosen't have this interrupt now ++ MS_U8 INT_F1_ATG_READY :1; ++}SCA_DISP_INTR_CONFIG; ++ ++typedef struct ++{ ++ #define SCA_NUM 3 ++ SCA_DISP_INTR_CONFIG stIntrConfig[SCA_NUM]; ++ MS_BOOL bIntrConfig_DIPW; ++ MS_U32 u32DIPW_Signal_PID; ++}SCA_DISP_INTR_SETTING; ++ ++typedef struct ++{ ++ #define SCA_NUM 3 ++ SCA_DISP_INTR_CONFIG stDisp_Intr_Status[SCA_NUM]; ++ MS_U8 u8DIPW_Status; ++}SCA_DISP_INTR_STATUS; ++ ++typedef struct ++{ ++ SCA_RW_REG_TYPE enType; ++ MS_U32 u32addr; ++ MS_U16 u16value; ++ MS_U16 u16mask; ++}SCA_RW_REGISTER_CONFIG, *PSCA_RW_REGISTER_CONFIG; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ MS_U16 u16version; ++ MS_U16 u16contrast; ++ MS_U16 u16r_gain; ++ MS_U16 u16g_gain; ++ MS_U16 u16b_gain; ++ MS_U16 u16saturation; ++ MS_U16 u16hue; ++ MS_U16 u16color_correct_xy_r; ++ MS_U16 u16color_correct_xy_g; ++ MS_U16 u16color_correct_xy_b; ++ MS_U16 u16color_correct_offset_r; ++ MS_U16 u16color_correct_offset_g; ++ MS_U16 u16color_correct_offset_b; ++}SCA_ACE_INFO_CONFIG, *PSCA_ACE_INFO_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32CmdBufAddr; ++ MS_U16 u16CmdBufLen; ++ MS_U16 u16DataLen; ++ MS_U16 u16PNL_Width; ++ MS_U16 u16PNL_Height; ++}SCA_DLC_INFO_CONFIG, *PSCA_DLC_INFO_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bChanged; ++ MS_BOOL bDisConnect; ++ SCA_DISP_PRIORITY_TYPE enPriType; ++ SCA_DEST_TYPE enDestType; ++ SCA_SRC_TYPE enSrcType; ++ MS_U32 dwUID; ++}SCA_DISP_PATH_CONFIG, *PSCA_DISP_PATH_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ SCA_DEST_TYPE enDestType; ++}SCA_MIRROR_CONFIG, *PSCA_MIRROR_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_PQ_BIN_ID_TYPE enPQBinIDType; ++ MS_U32 u32PQBin_Addr; ++ MS_U32 u32PQBin_Size; ++}SCA_PQ_BIN_INFO; ++ ++typedef struct ++{ ++ SCA_PQ_BIN_INFO stPQBinInfo[SCA_PQ_BIN_ID_NUM]; ++}SCA_PQ_BIN_CONFIG, *PSCA_PQ_BIN_CONFIG; ++typedef struct { ++ MS_U16 u16value; ++ MS_BOOL bnegative;//0=add ,1=minus ++}SCA_PQ_adj; ++ ++typedef struct { ++ MS_BOOL icc_en; ++ SCA_PQ_adj icc_gain_R; ++ SCA_PQ_adj icc_gain_G; ++ SCA_PQ_adj icc_gain_B; ++ SCA_PQ_adj icc_gain_Y; ++ SCA_PQ_adj icc_gain_M; ++ SCA_PQ_adj icc_gain_C; ++ SCA_PQ_adj icc_gain_F; ++ SCA_PQ_adj icc_gain_NC; ++}SCA_PQ_ICC_CFG,*PSCA_PQ_ICC_CFG; ++ ++typedef struct { ++ MS_BOOL ibc_en; ++ SCA_PQ_adj ibc_gain_R;//RGB...no use positive ++ SCA_PQ_adj ibc_gain_G; ++ SCA_PQ_adj ibc_gain_B; ++ SCA_PQ_adj ibc_gain_Y; ++ SCA_PQ_adj ibc_gain_M; ++ SCA_PQ_adj ibc_gain_C; ++ SCA_PQ_adj ibc_gain_F; ++}SCA_PQ_IBC_CFG,*PSCA_PQ_IBC_CFG; ++ ++typedef struct { ++ MS_BOOL ihc_en; ++ SCA_PQ_adj ihc_gain_R;//RGB...=max3F+P/N ++ SCA_PQ_adj ihc_gain_G; ++ SCA_PQ_adj ihc_gain_B; ++ SCA_PQ_adj ihc_gain_Y; ++ SCA_PQ_adj ihc_gain_M; ++ SCA_PQ_adj ihc_gain_C; ++ SCA_PQ_adj ihc_gain_F; ++}SCA_PQ_IHC_CFG,*PSCA_PQ_IHC_CFG; ++ ++ ++ ++ ++ ++typedef struct ++{ ++ SCA_DIP_DEST_FMT_TYPE enDestFmtType; ++ MS_BOOL bClipEn; ++ SCA_WINDOW_TYPE stClipWin; ++ MS_U8 u8FrameNum; ++ MS_U32 u32BuffAddress; ++ MS_U32 u32BuffSize; ++ MS_U32 u32C_BuffAddress; ++ MS_U32 u32C_BuffSize; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++ MS_BOOL bTriggle; ++ SCA_DIP_TRIGGER_TYPE enTrigMode; ++}SCA_DIP_CONFIG, *PSCA_DIP_CONFIG; ++ ++ ++typedef struct ++{ ++ MS_U32 u32BuffAddress; ++ MS_U32 u32C_BuffAddress; ++ MS_BOOL bTrig; ++}SCA_DIP_WONCE_BASE_CONFIG, *PSCA_DIP_WONCE_BASE_CONFIG; ++ ++typedef struct ++{ ++ SCA_HDMITX_OUTPUT_TIMINE_TYPE enHDMITx_OutputTiming; ++ SCA_HDMITX_MODE_TYPE enHDMITx_Mode; ++ SCA_HDMITX_OUTPUT_COLOR_TYPE enHDMITx_ColorType; ++ MS_BOOL bEn; ++}SCA_HDMITX_CONFIG, *PSCA_HDMITX_CONFIG; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bEn; ++}SCA_FREEZE_CONFIG, *PSCA_FREEZE_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bFroceInit; ++ MS_U32 u32MST701Bin_Addr; ++ MS_U32 u32MST701Bin_Bytes; ++}SCA_MST701_CONFIG, *PSCA_MST701_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_SRC_TYPE enSrcType; ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bSuccess; ++ MS_U8 u8ModeIndex; ++ MS_U16 u16Hstart; ++ MS_U16 u16Vstart; ++ MS_U16 u16Phase; ++ MS_U16 u16Htotal; ++}SCA_GEOMETRY_CALI_CONFIG, *PSCA_GEOMETRY_CALI_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16SableCnt; ++ MS_U16 u16NoSyncCnt; ++ MS_U32 u32PollingPeriod; //ms ++}SCA_ANALOG_POLLING_CONFIG, *PSCA_ANALOG_POLLING_CONFIG; ++ ++typedef struct ++{ ++ SCA_CLONE_SCREEN_TYPE enCloneScreenType; ++}SCA_CLONE_SCREEN_CONFIG, *PSCA_CLONE_SCREEN_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Modulation; ++ MS_U16 u16Deviation; ++ MS_BOOL bEn; ++}SCA_PNL_SSC_CONFIG, *PSCA_PNL_SSC_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Htt; ++ MS_U16 u16H_Active; ++ MS_U16 u16HSync_Width; ++ MS_U16 u16HSync_Fporch; ++ MS_U16 u16HSync_Bporch; ++ MS_U16 u16Vtt; ++ MS_U16 u16V_Active; ++ MS_U16 u16VSync_Width; ++ MS_U16 u16VSync_Fporch; ++ MS_U16 u16VSync_Bporch; ++ MS_U16 u16DCLK_MHz; ++}SCA_PNL_TIMING_CONFIG, *PSCA_PNL_TIMING_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ SCA_SRC_TYPE enSrcType; ++ MS_BOOL bSetModeDone; ++}SCA_MONITOR_STATUS_CONFIG, *PSCA_MONITOR_STATUS_CONFIG; ++ ++typedef struct ++{ ++ SCA_SRC_TYPE enSrcType; ++ MS_BOOL bEn; ++ MS_U16 u16H_Overscan; ++ MS_U16 u16V_Overscan; ++ MS_S16 s16H_Offset; ++ MS_S16 s16V_Offset; ++ MS_BOOL bCVBS_NTSC; ++}SCA_USER_DISPLAY_CONFIG, *PSCA_USER_DISPLAY_CONFIG; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ SCA_SRC_TYPE enSrcType; ++ MS_BOOL bEn; ++ MS_U16 u16H_Overscan; ++ MS_U16 u16V_Overscan; ++ MS_S16 s16H_Offset; ++ MS_S16 s16V_Offset; ++ MS_BOOL bCVBS_NTSC; ++}SCA_USER_DISPLAY_CONFIG_EX, *PSCA_USER_DISPLAY_CONFIG_EX; ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ SCA_DISPLAY_MUTE_COLOR_TYPE enColorType; ++}SCA_DISPLAY_MUTE_COLOR_CONFIG, *PSCA_DISPLAY_MUTE_COLOR_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U16 u16H_ratio; ++ MS_U16 u16V_ratio; ++}SCA_CLONE_SCREEN_DISPLAY_RATIO_CONFIG, *PSCA_CLONE_SCREEN_DISPLAY_RATIO_CONFIG; ++ ++typedef struct ++{ ++ ++ ++ MS_U8 ucLumaCurve[16]; ++ MS_U8 ucLumaCurve2_a[16]; ++ MS_U8 ucLumaCurve2_b[16]; ++ MS_U8 ucDlcHistogramLimitCurve[17]; ++ ++ MS_U8 u8_L_L_U; ++ MS_U8 u8_L_L_D; ++ MS_U8 u8_L_H_U; ++ MS_U8 u8_L_H_D; ++ MS_U8 u8_S_L_U; ++ MS_U8 u8_S_L_D; ++ MS_U8 u8_S_H_U; ++ MS_U8 u8_S_H_D; ++ ++ MS_U8 ucDlcPureImageMode; ++ MS_U8 ucDlcLevelLimit; ++ MS_U8 ucDlcAvgDelta; ++ MS_U8 ucDlcAvgDeltaStill; ++ MS_U8 ucDlcFastAlphaBlending; ++ MS_U8 ucDlcYAvgThresholdL; ++ MS_U8 ucDlcYAvgThresholdH; ++ MS_U8 ucDlcBLEPoint; ++ MS_U8 ucDlcWLEPoint; ++ MS_U8 bEnableBLE; ++ MS_U8 bEnableWLE; ++ ++ MS_U8 ucDlcYAvgThresholdM; ++ MS_U8 ucDlcCurveMode; ++ MS_U8 ucDlcCurveModeMixAlpha; ++ ++ MS_U8 ucDlcAlgorithmMode; ++ ++ MS_U8 ucDlcSepPointH; ++ MS_U8 ucDlcSepPointL; ++ MS_U16 uwDlcBleStartPointTH; ++ MS_U16 uwDlcBleEndPointTH; ++ MS_U8 ucDlcCurveDiff_L_TH; ++ MS_U8 ucDlcCurveDiff_H_TH; ++ MS_U16 uwDlcBLESlopPoint_1; ++ MS_U16 uwDlcBLESlopPoint_2; ++ MS_U16 uwDlcBLESlopPoint_3; ++ MS_U16 uwDlcBLESlopPoint_4; ++ MS_U16 uwDlcBLESlopPoint_5; ++ MS_U16 uwDlcDark_BLE_Slop_Min; ++ MS_U8 ucDlcCurveDiffCoringTH; ++ MS_U8 ucDlcAlphaBlendingMin; ++ MS_U8 ucDlcAlphaBlendingMax; ++ MS_U8 ucDlcFlicker_alpha; ++ MS_U8 ucDlcYAVG_L_TH; ++ MS_U8 ucDlcYAVG_H_TH; ++ MS_U8 ucDlcDiffBase_L; ++ MS_U8 ucDlcDiffBase_M; ++ MS_U8 ucDlcDiffBase_H; ++ ++ MS_U8 bCGCCGainCtrl; ++ MS_U8 ucCGCCGain_offset; ++ MS_U8 ucCGCChroma_GainLimitH; ++ MS_U8 ucCGCChroma_GainLimitL; ++ MS_U8 ucCGCYCslope; ++ MS_U8 ucCGCYth; ++}SCA_DLC_INIT_CONFIG, *PSCA_DLC_INIT_CONFIG; ++ ++ ++typedef struct ++{ ++ SCA_DEST_TYPE enDestType; ++ MS_BOOL bDLCOnOff; ++ MS_BOOL bUserControl; ++}SCA_DLC_ONOFF_CONFIG, *PSCA_DLC_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U16 u16Size; ++ MS_U8 u8Msg[64]; ++}SCA_UEVENT_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++}SCA_CVBSOUT_DAC_CONFIG, *PSCA_CVBSOUT_DAC_CONFIG; ++ ++ ++typedef struct ++{ ++ MS_U16 u16x; ++ MS_U16 u16y; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++ MS_U16 u16Vtotal; ++ MS_U16 u16VFreq; ++ MS_BOOL bInterlace; ++}SCA_CAMERA_INPUTTIMING_CONFIG, *PSCA_CAMERA_INPUTTIMING_CONFIG; ++#endif //_MDRV_GFLIP_IO_H +diff --git a/drivers/mstar/include/mdrv_scldma_io.h b/drivers/mstar/include/mdrv_scldma_io.h +new file mode 100644 +index 00000000..21f4876c +--- /dev/null ++++ b/drivers/mstar/include/mdrv_scldma_io.h +@@ -0,0 +1,148 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_scldma_io.h ++ * @brief SCLDMA Driver IOCTL interface ++ */ ++ ++ ++/** ++ * \defgroup scldma_group SCLDMA driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/cksnp ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count ,W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma2.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmR ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmW ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_H ++#define _MDRV_SCLDMA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR (0) ///< The IOCTL NR definition, SET_IN_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR (1) ///< The IOCTL NR definition, SET_IN_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR (2) ///< The IOCTL NR definition, SET_OUT_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR (3) ///< The IOCTL NR definition, SET_OUT_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR (4) ///< The IOCTL NR definition, GET_IN_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR (5) ///< The IOCTL NR definition, GET_OUT_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition, GET_PRIVATE_ID_CONFIG ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG_NR (7) ///< The IOCTL NR definition, SET_LOCK_CONFIG ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR (8) ///< The IOCTL NR definition, SET_UNLOCK_CONFIG ++#define IOCLT_SCLDMA_GET_VERSION_CONFIG_NR (9) ///< The IOCTL NR definition, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR (10) ///< The IOCTL NR definition, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR (12) ///< The IOCTL NR definition, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR ++#define IOCTL_SCLDMA_MAX_NR (13) ///< The Max IOCTL NR for scldma driver ++ ++// use 'm' as magic number ++#define IOCTL_SCLDMA_MAGIC ('2') ///< The Type definition of IOCTL for scldma driver ++ ++/** ++* Used to set parameters of in buffer configurate ,buffer address and number,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_R device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set parameters of out buffer configurate,buffer address and number ,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_W device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_R device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_W device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to peek queue information and set read flag , use ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG. ++*/ ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR) ++/** ++* Used to get mutiinst parameters of private id configurate ,use ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of lock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_LOCK_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of unlock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_SCLDMA_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_VERSION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR) ++/** ++* Used to get DMA information, use ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR) ++ ++#endif // ++ ++/** @} */ // end of scldma_group +diff --git a/drivers/mstar/include/mdrv_scldma_io_i3.h b/drivers/mstar/include/mdrv_scldma_io_i3.h +new file mode 100644 +index 00000000..4f92fffb +--- /dev/null ++++ b/drivers/mstar/include/mdrv_scldma_io_i3.h +@@ -0,0 +1,148 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_scldma_io_i3.h ++ * @brief SCLDMA Driver IOCTL interface ++ */ ++ ++ ++/** ++ * \defgroup scldma_group SCLDMA driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma1.0/cksnp ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count ,W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma2.0/ckfrm ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmR ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * sysfs Node: /sys/devices/platform/mscldma3.0/ckfrmW ++ * ++ * sysfs R/W mode: R/W ++ * ++ * sysfs Usage & Description: R:check trig off count and dma line count W: if 0 reset scldma status ,if echo 1 all reset ++ * ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_H ++#define _MDRV_SCLDMA_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR (0) ///< The IOCTL NR definition, SET_IN_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR (1) ///< The IOCTL NR definition, SET_IN_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR (2) ///< The IOCTL NR definition, SET_OUT_BUFFER_CONFIG ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR (3) ///< The IOCTL NR definition, SET_OUT_TRIGGER_CONFIG ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR (4) ///< The IOCTL NR definition, GET_IN_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR (5) ///< The IOCTL NR definition, GET_OUT_ACTIVE_BUFFER_CONFIG ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR (6) ///< The IOCTL NR definition, GET_PRIVATE_ID_CONFIG ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG_NR (7) ///< The IOCTL NR definition, SET_LOCK_CONFIG ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR (8) ///< The IOCTL NR definition, SET_UNLOCK_CONFIG ++#define IOCLT_SCLDMA_GET_VERSION_CONFIG_NR (9) ///< The IOCTL NR definition, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR (10) ///< The IOCTL NR definition, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR (12) ///< The IOCTL NR definition, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR ++#define IOCTL_SCLDMA_MAX_NR (13) ///< The Max IOCTL NR for scldma driver ++ ++// use 'm' as magic number ++#define IOCTL_SCLDMA_MAGIC ('2') ///< The Type definition of IOCTL for scldma driver ++ ++/** ++* Used to set parameters of in buffer configurate ,buffer address and number,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_R device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set parameters of out buffer configurate,buffer address and number ,dma mode,color mode,resolution, use ST_IOCTL_SCLDMA_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG_NR) ++ ++/** ++* Used to trigger DMA_W device, use ST_IOCTL_SCLDMA_TRIGGER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_R device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to set Rpoint(by OMX) and get Wpoint with warning flag,it's like buffer control in DMA_W device, use ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG_NR) ++ ++/** ++* Used to peek queue information and set read flag , use ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG. ++*/ ++#define IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG_NR) ++/** ++* Used to get mutiinst parameters of private id configurate ,use ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of lock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_LOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_LOCK_CONFIG_NR) ++ ++/** ++* Used to set mutiinst parameters of unlock configurate, use ST_IOCTL_SCLDMA_LOCK_CONFIG. ++*/ ++#define IOCTL_SCLDMA_SET_UNLOCK_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_SET_UNLOCK_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_SCLDMA_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_VERSION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCLT_SCLDMA_GET_VERSION_CONFIG_NR) ++/** ++* Used to get DMA information, use ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG. ++*/ ++#define IOCTL_SCLDMA_GET_INFORMATION_CONFIG _IO(IOCTL_SCLDMA_MAGIC, IOCTL_SCLDMA_GET_INFORMATION_CONFIG_NR) ++ ++#endif // ++ ++/** @} */ // end of scldma_group +diff --git a/drivers/mstar/include/mdrv_scldma_io_i3_st.h b/drivers/mstar/include/mdrv_scldma_io_i3_st.h +new file mode 100644 +index 00000000..63db6b25 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_scldma_io_i3_st.h +@@ -0,0 +1,265 @@ ++/////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++/** ++ * @file mdrv_scldma_io_i3_st.h ++ * @brief scldma Driver IOCTL parameter interface ++ */ ++ ++ /** ++ * \ingroup scldma_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_SCLDMA_IO_ST_H ++#define _MDRV_SCLDMA_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++// library information ++//1.0.1:for clean scldma. ++//1.1.1:for add buffer queue handler and swring mode. ++//1.1.3:refine for 1.1.1 scl test OK,stabilize not yet. ++#define IOCTL_SCLDMA_VERSION 0x0113 ///< H:Major L:minor H3:Many Change H2:adjust Struct L1:add struct L0:adjust driver ++#define IOCTL_SCLDMA_BUFFER_QUEUE_OFFSET sizeof(ST_IOCTL_SCLDMA_FRAME_BUFFER_CONFIG)/// v) ? 1 : 0; \ ++}) ++ ++ ++#define CHK_VERCHK_VERSION_LESS_EQU(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) <= v) ? 1 : 0; \ ++}) ++ ++#define CHK_VERCHK_VERSION_GREATER_EQU(pvar, v) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ unsigned char bV; \ ++ bV = ((*p & VERCHK_VERSION_MASK) >= v) ? 1 : 0; \ ++}) ++ ++ ++#define CHK_VERCHK_SIZE(pvar,s) \ ++({ \ ++ unsigned int *p = (unsigned int *)pvar; \ ++ (*p == s ) ? 1 : 0; \ ++}) ++ ++ ++#define VERCHK_ERR(_fmt, _args...) \ ++ do \ ++ { \ ++ printk(KERN_WARNING _fmt, ## _args); \ ++ }while(0); ++ ++#endif +diff --git a/drivers/mstar/include/mdrv_video.h b/drivers/mstar/include/mdrv_video.h +new file mode 100644 +index 00000000..7a9a5022 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_video.h +@@ -0,0 +1,38 @@ ++ ++#ifndef _MDRV_VIDEO_H_ ++#define _MDRV_VIDEO_H_ ++ ++/* ++ * NOTE: ++ * This is old version naming of MFE driver. It wiil be deprecated in the future. ++ * ++ */ ++ ++/* definition of structures */ ++ ++#ifndef _MDRV_MMFE_IO_H_ ++ ++#include ++ ++#endif//_MDRV_MMFE_IO_H_ ++ ++typedef mmfe_reqbuf mvideo_reqbuf; ++typedef mmfe_buffer mvideo_buffer; ++typedef mmfe_params mvideo_params; ++typedef mmfe_control mvideo_control; ++ ++/* definition of ioctl codes */ ++ ++#define MVIDIOC_S_PARM IOCTL_MFE_S_PARM ++#define MVIDIOC_G_PARM IOCTL_MFE_G_PARM ++#define MVIDIOC_S_CTRL IOCTL_MFE_S_CTRL ++#define MVIDIOC_G_CTRL IOCTL_MFE_G_CTRL ++#define MVIDIOC_STREAMON IOCTL_MFE_STREAMON ++#define MVIDIOC_STREAMOFF IOCTL_MFE_STREAMOFF ++#define MVIDIOC_REQBUF IOCTL_MFE_REQBUF ++#define MVIDIOC_S_PICT IOCTL_MFE_S_PICT ++#define MVIDIOC_G_BITS IOCTL_MFE_G_BITS ++#define MVIDIOC_FLUSH IOCTL_MFE_FLUSH ++ ++#endif//_MDRV_VIDEO_H_ ++ +diff --git a/drivers/mstar/include/mdrv_vip_io.h b/drivers/mstar/include/mdrv_vip_io.h +new file mode 100644 +index 00000000..6bc3e7bb +--- /dev/null ++++ b/drivers/mstar/include/mdrv_vip_io.h +@@ -0,0 +1,189 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_vip_io.h ++ * @brief VIP Driver IOCTL interface ++ */ ++ ++/** ++ * \defgroup vip_group VIP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mvip1.0/bypass ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: W:echo 1 open bypass ,echo 0 close. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckPQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 PQ already setting check , echo 2 Auto test PQ ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckCMDQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 CMDQ already setting check , echo 2 Auto test CMDQ ++ * ++ * @{ ++ */ ++#ifndef _MDRV_VIP_IO_H ++#define _MDRV_VIP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_VIP_SET_DNR_CONFIG_NR (0) ///< The IOCTL NR definition,IOCTL_VIP_SET_DNR_CONFIG ++#define IOCTL_VIP_SET_PEAKING_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_VIP_SET_PEAKING_CONFIG ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR (3) ///< The IOCTL NR definition,IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ++#define IOCTL_VIP_SET_DLC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_CONFIG ++#define IOCTL_VIP_SET_LCE_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_VIP_SET_LCE_CONFIG ++#define IOCTL_VIP_SET_UVC_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_VIP_SET_UVC_CONFIG ++#define IOCTL_VIP_SET_IHC_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_CONFIG ++#define IOCTL_VIP_SET_ICE_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_VIP_SET_ICE_CONFIG ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG ++#define IOCTL_VIP_SET_IBC_CONFIG_NR (11) ///< The IOCTL NR definition,IOCTL_VIP_SET_IBC_CONFIG ++#define IOCTL_VIP_SET_FCC_CONFIG_NR (12) ///< The IOCTL NR definition,IOCTL_VIP_SET_FCC_CONFIG ++#define IOCTL_VIP_SET_VIP_CONFIG_NR (13) ///< The IOCTL NR definition,IOCTL_VIP_SET_VIP_CONFIG ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG_NR (14) ///< The IOCTL NR definition,IOCTL_VIP_CMDQ_WRITE_CONFIG ++#define IOCTL_VIP_SET_LDC_CONFIG_NR (15) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_CONFIG ++#define IOCTL_VIP_SET_LDC_MD_CONFIG_NR (16) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_MD_CONFIG ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR (17) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_DMAP_CONFIG ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR (18) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_SRAM_CONFIG ++#define IOCTL_VIP_SET_ACK_CONFIG_NR (19) ///< The IOCTL NR definition,IOCTL_VIP_SET_ACK_CONFIG ++#define IOCTL_VIP_SET_NLM_CONFIG_NR (20) ///< The IOCTL NR definition,IOCTL_VIP_SET_NLM_CONFIG ++#define IOCTL_VIP_SNR_CONFIG_NR (21) ///< The IOCTL NR definition,IOCTL_VIP_SNR_CONFIG ++#define IOCTL_VIP_SET_VTRACK_CONFIG_NR (22) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_CONFIG ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR (23) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ++#define IOCLT_VIP_GET_VERSION_CONFIG_NR (24) ///< The IOCTL NR definition, IOCLT_VIP_GET_VERSION_CONFIG_NR ++#define IOCLT_VIP_SET_ALLVIP_CONFIG_NR (25) ///< The IOCTL NR for vip driver ++#define IOCTL_VIP_MAX_NR (26) ///< The Max IOCTL NR for vip driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_VIP_MAGIC ('3') ///< The Type definition of IOCTL for vip driver ++/** ++* Used to set CMDQ cmd, use ST_IOCTL_VIP_CMDQ_CONFIG. ++*/ ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_CMDQ_WRITE_CONFIG_NR) ++/** ++* Used to set DNR, use ST_IOCTL_VIP_DNR_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DNR_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DNR_CONFIG_NR) ++/** ++* Used to set LDC, use ST_IOCTL_VIP_LDC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_CONFIG_NR) ++/** ++* Used to set LDC mode, use ST_IOCTL_VIP_LDC_MD_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_MD_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_MD_CONFIG_NR) ++/** ++* Used to set LDC DMAP address, use ST_IOCTL_VIP_LDC_DMAP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR) ++/** ++* Used to set LDC SRAM address, use ST_IOCTL_VIP_LDC_SRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR) ++/** ++* Used to set PK, use ST_IOCTL_VIP_PEAKING_CONFIG. ++*/ ++#define IOCTL_VIP_SET_PEAKING_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_PEAKING_CONFIG_NR) ++/** ++* Used to set DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR) ++/** ++* Used to get DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT. ++*/ ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR) ++/** ++* Used to set DLC, use ST_IOCTL_VIP_DLC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_CONFIG_NR) ++/** ++* Used to set LCE, use ST_IOCTL_VIP_LCE_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LCE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LCE_CONFIG_NR) ++/** ++* Used to set UVC, use ST_IOCTL_VIP_UVC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_UVC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_UVC_CONFIG_NR) ++/** ++* Used to set IHC, use ST_IOCTL_VIP_IHC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_CONFIG_NR) ++/** ++* Used to set ICE, use ST_IOCTL_VIP_ICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ICE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ICE_CONFIG_NR) ++/** ++* Used to set IHCICC, use ST_IOCTL_VIP_IHCICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR) ++/** ++* Used to set IBC, use ST_IOCTL_VIP_IBC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IBC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IBC_CONFIG_NR) ++/** ++* Used to set FCC, use ST_IOCTL_VIP_FCC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_FCC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_FCC_CONFIG_NR) ++/** ++* Used to set ACK, use ST_IOCTL_VIP_ACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ACK_CONFIG_NR) ++/** ++* Used to set NLM, use ST_IOCTL_VIP_NLM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_NLM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_NLM_CONFIG_NR) ++/** ++* Used to set SNR, use ST_IOCTL_VIP_SNR_CONFIG. ++*/ ++#define IOCTL_VIP_SET_SNR_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SNR_CONFIG_NR) ++/** ++* Used to set VIPLB, use ST_IOCTL_VIP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VIP_CONFIG_NR) ++/** ++* Used to set VTRACK, use ST_IOCTL_VIP_VTRACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VTRACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VTRACK_CONFIG_NR) ++/** ++* Used to set VTACK ON, use ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR) ++/** ++* Used to get version, use ST_IOCTL_VIP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_VIP_GET_VERSION_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_GET_VERSION_CONFIG_NR) ++/** ++* Used to set all vip config, use ST_IOCTL_VIP_AllSET_CONFIG. ++*/ ++#define IOCLT_VIP_SET_ALLVIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_SET_ALLVIP_CONFIG_NR) ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/mstar/include/mdrv_vip_io_i3.h b/drivers/mstar/include/mdrv_vip_io_i3.h +new file mode 100644 +index 00000000..1395f6a0 +--- /dev/null ++++ b/drivers/mstar/include/mdrv_vip_io_i3.h +@@ -0,0 +1,195 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++ * @file mdrv_vip_io.h ++ * @brief VIP Driver IOCTL interface ++ */ ++ ++/** ++ * \defgroup vip_group VIP driver ++ * \note ++ * ++ * sysfs Node: /sys/devices/platform/mvip1.0/bypass ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: W:echo 1 open bypass ,echo 0 close. ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckPQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 PQ already setting check , echo 2 Auto test PQ ++ * ++ * sysfs Node: /sys/devices/platform/mhvsp1.0/ckCMDQ ++ * ++ * sysfs R/W mode: W ++ * ++ * sysfs Usage & Description: echo 1 CMDQ already setting check , echo 2 Auto test CMDQ ++ * ++ * @{ ++ */ ++#ifndef _MDRV_VIP_IO_H ++#define _MDRV_VIP_IO_H ++ ++//============================================================================= ++// Includs ++//============================================================================= ++ ++ ++//============================================================================= ++// IOCTRL defines ++//============================================================================= ++#define IOCTL_VIP_SET_PEAKING_CONFIG_NR (1) ///< The IOCTL NR definition,IOCTL_VIP_SET_PEAKING_CONFIG ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR (2) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR (3) ///< The IOCTL NR definition,IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ++#define IOCTL_VIP_SET_DLC_CONFIG_NR (4) ///< The IOCTL NR definition,IOCTL_VIP_SET_DLC_CONFIG ++#define IOCTL_VIP_SET_LCE_CONFIG_NR (6) ///< The IOCTL NR definition,IOCTL_VIP_SET_LCE_CONFIG ++#define IOCTL_VIP_SET_UVC_CONFIG_NR (7) ///< The IOCTL NR definition,IOCTL_VIP_SET_UVC_CONFIG ++#define IOCTL_VIP_SET_IHC_CONFIG_NR (8) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_CONFIG ++#define IOCTL_VIP_SET_ICE_CONFIG_NR (9) ///< The IOCTL NR definition,IOCTL_VIP_SET_ICE_CONFIG ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR (10) ///< The IOCTL NR definition,IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG ++#define IOCTL_VIP_SET_IBC_CONFIG_NR (11) ///< The IOCTL NR definition,IOCTL_VIP_SET_IBC_CONFIG ++#define IOCTL_VIP_SET_FCC_CONFIG_NR (12) ///< The IOCTL NR definition,IOCTL_VIP_SET_FCC_CONFIG ++#define IOCTL_VIP_SET_VIP_CONFIG_NR (13) ///< The IOCTL NR definition,IOCTL_VIP_SET_VIP_CONFIG ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG_NR (14) ///< The IOCTL NR definition,IOCTL_VIP_CMDQ_WRITE_CONFIG ++#define IOCTL_VIP_SET_LDC_CONFIG_NR (15) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_CONFIG ++#define IOCTL_VIP_SET_LDC_MD_CONFIG_NR (16) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_MD_CONFIG ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR (17) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_DMAP_CONFIG ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR (18) ///< The IOCTL NR definition,IOCTL_VIP_SET_LDC_SRAM_CONFIG ++#define IOCTL_VIP_SET_ACK_CONFIG_NR (19) ///< The IOCTL NR definition,IOCTL_VIP_SET_ACK_CONFIG ++#define IOCTL_VIP_SET_NLM_CONFIG_NR (20) ///< The IOCTL NR definition,IOCTL_VIP_SET_NLM_CONFIG ++#define IOCTL_VIP_SET_VTRACK_CONFIG_NR (22) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_CONFIG ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR (23) ///< The IOCTL NR definition,IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ++#define IOCTL_VIP_AIP_CONFIG_NR (24) ///< The IOCTL NR definition,IOCTL_VIP_AIP_CONFIG ++#define IOCTL_VIP_AIP_SRAM_CONFIG_NR (25) ///< The IOCTL NR definition,IOCTL_VIP_AIP_SRAM_CONFIG ++#define IOCTL_VIP_SET_MCNR_CONFIG_NR (26) ///< The IOCTL NR definition,IOCTL_VIP_SET_MCNR_CONFIG ++#define IOCLT_VIP_GET_VERSION_CONFIG_NR (27) ///< The IOCTL NR definition, IOCLT_VIP_GET_VERSION_CONFIG_NR ++#define IOCLT_VIP_SET_ALLVIP_CONFIG_NR (IOCLT_VIP_GET_VERSION_CONFIG_NR+1) ///< The IOCTL NR for vip driver ++#define IOCTL_VIP_MAX_NR (IOCLT_VIP_SET_ALLVIP_CONFIG_NR+1) ///< The Max IOCTL NR for vip driver ++ ++ ++// use 'm' as magic number ++#define IOCTL_VIP_MAGIC ('3') ///< The Type definition of IOCTL for vip driver ++/** ++* Used to set CMDQ cmd, use ST_IOCTL_VIP_CMDQ_CONFIG. ++*/ ++#define IOCTL_VIP_CMDQ_WRITE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_CMDQ_WRITE_CONFIG_NR) ++/** ++* Used to set LDC, use ST_IOCTL_VIP_LDC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_CONFIG_NR) ++/** ++* Used to set LDC mode, use ST_IOCTL_VIP_LDC_MD_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_MD_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_MD_CONFIG_NR) ++/** ++* Used to set LDC DMAP address, use ST_IOCTL_VIP_LDC_DMAP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_DMAP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_DMAP_CONFIG_NR) ++/** ++* Used to set LDC SRAM address, use ST_IOCTL_VIP_LDC_SRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LDC_SRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LDC_SRAM_CONFIG_NR) ++/** ++* Used to set PK, use ST_IOCTL_VIP_PEAKING_CONFIG. ++*/ ++#define IOCTL_VIP_SET_PEAKING_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_PEAKING_CONFIG_NR) ++/** ++* Used to set DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG_NR) ++/** ++* Used to get DLC hist, use ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT. ++*/ ++#define IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT_NR) ++/** ++* Used to set DLC, use ST_IOCTL_VIP_DLC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_DLC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_DLC_CONFIG_NR) ++/** ++* Used to set LCE, use ST_IOCTL_VIP_LCE_CONFIG. ++*/ ++#define IOCTL_VIP_SET_LCE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_LCE_CONFIG_NR) ++/** ++* Used to set UVC, use ST_IOCTL_VIP_UVC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_UVC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_UVC_CONFIG_NR) ++/** ++* Used to set IHC, use ST_IOCTL_VIP_IHC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_CONFIG_NR) ++/** ++* Used to set ICE, use ST_IOCTL_VIP_ICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ICE_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ICE_CONFIG_NR) ++/** ++* Used to set IHCICC, use ST_IOCTL_VIP_IHCICC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG_NR) ++/** ++* Used to set IBC, use ST_IOCTL_VIP_IBC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_IBC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_IBC_CONFIG_NR) ++/** ++* Used to set FCC, use ST_IOCTL_VIP_FCC_CONFIG. ++*/ ++#define IOCTL_VIP_SET_FCC_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_FCC_CONFIG_NR) ++/** ++* Used to set ACK, use ST_IOCTL_VIP_ACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_ACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_ACK_CONFIG_NR) ++/** ++* Used to set NLM, use ST_IOCTL_VIP_NLM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_NLM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_NLM_CONFIG_NR) ++/** ++* Used to set VIPLB, use ST_IOCTL_VIP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VIP_CONFIG_NR) ++/** ++* Used to set VTRACK, use ST_IOCTL_VIP_VTRACK_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VTRACK_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VTRACK_CONFIG_NR) ++/** ++* Used to set VTACK ON, use ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG. ++*/ ++#define IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG_NR) ++/** ++* Used to set AIP, use ST_IOCTL_VIP_AIP_CONFIG. ++*/ ++#define IOCTL_VIP_SET_AIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_AIP_CONFIG_NR) ++/** ++* Used to set AIP, use ST_IOCTL_VIP_AIP_SRAM_CONFIG. ++*/ ++#define IOCTL_VIP_SET_AIP_SRAM_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_AIP_SRAM_CONFIG_NR) ++/** ++* Used to set MCNR , use ST_IOCTL_VIP_MCNR_CONFIG. ++*/ ++#define IOCTL_VIP_SET_MCNR_CONFIG _IO(IOCTL_VIP_MAGIC, IOCTL_VIP_SET_MCNR_CONFIG_NR) ++ ++/** ++* Used to get version, use ST_IOCTL_VIP_GET_VERSION_CONFIG. ++*/ ++#define IOCTL_VIP_GET_VERSION_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_GET_VERSION_CONFIG_NR) ++/** ++* Used to set all vip config, use ST_IOCTL_VIP_AllSET_CONFIG. ++*/ ++#define IOCLT_VIP_SET_ALLVIP_CONFIG _IO(IOCTL_VIP_MAGIC, IOCLT_VIP_SET_ALLVIP_CONFIG_NR) ++#endif // ++/** @} */ // end of hvsp_group +diff --git a/drivers/mstar/include/mdrv_vip_io_i3_st.h b/drivers/mstar/include/mdrv_vip_io_i3_st.h +new file mode 100644 +index 00000000..4ca9242c +--- /dev/null ++++ b/drivers/mstar/include/mdrv_vip_io_i3_st.h +@@ -0,0 +1,1307 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++/** ++ * @file mdrv_vip_io_st.h ++ * @brief vip Driver IOCTL parameter interface ++ */ ++ ++ /** ++ * \ingroup vip_group ++ * @{ ++ */ ++ ++#ifndef _MDRV_VIP_IO_ST_H ++#define _MDRV_VIP_IO_ST_H ++ ++//============================================================================= ++// Defines ++//============================================================================= ++#define VIP_LCE_CURVE_SECTION_NUM 16 ///< VIP_LCE_CURVE_SECTION_NUM ++#define VIP_PEAKING_BAND_NUM 8 ///< VIP_PEAKING_BAND_NUM ++#define VIP_PEAKING_ADP_Y_LUT_NUM 8 ///< VIP_PEAKING_ADP_Y_LUT_NUM ++#define VIP_PEAKING_BAND_TERM_NUM 16 ///< VIP_PEAKING_BAND_TERM_NUM ++#define VIP_DLC_HISTOGRAM_SECTION_NUM 7 ///< VIP_DLC_HISTOGRAM_SECTION_NUM ++#define VIP_DLC_HISTOGRAM_REPORT_NUM 8 ///< VIP_DLC_HISTOGRAM_REPORT_NUM ++#define VIP_DLC_LUMA_SECTION_NUM 64 ///< VIP_DLC_LUMA_SECTION_NUM ++#define VIP_IHC_COLOR_NUM 16 ///< VIP_IHC_COLOR_NUM ++#define VIP_IHC_USER_COLOR_NUM 16 ///< VIP_IHC_USER_COLOR_NUM ++#define VIP_ICE_COLOR_NUM 16 ///< VIP_ICE_COLOR_NUM ++#define VIP_IBC_COLOR_NUM 16 ///< VIP_IBC_COLOR_NUM ++#define VIP_FCC_YWIN_LUT_ENTRY_NUM 17 ///< VIP_FCC_YWIN_LUT_ENTRY_NUM ++#define VIP_NLM_DISTWEIGHT_NUM 9 ///< VIP_NLM_DISTWEIGHT_NUM ++#define VIP_NLM_WEIGHT_NUM 32 ///< VIP_NLM_WEIGHT_NUM ++#define VIP_NLM_LUMAGAIN_NUM 64 ///< VIP_NLM_LUMAGAIN_NUM ++#define VIP_NLM_POSTLUMA_NUM 16 ///< VIP_NLM_POSTLUMA_NUM ++#define VIP_CMDQ_MEM_256K 0x0040000 ///< VIP_CMDQ_MEM_164K ++#define VIP_CMDQ_MEM_196K 0x0030000 ///< VIP_CMDQ_MEM_164K ++#define VIP_CMDQ_MEM_164K 0x0028000 ///< VIP_CMDQ_MEM_164K ++#define VIP_CMDQ_MEM_128K 0x0020000 ///< VIP_CMDQ_MEM_128K ++#define VIP_CMDQ_MEM_64K 0x0010000 ///< VIP_CMDQ_MEM_64K ++#define VIP_CMDQ_MEM_32K 0x0008000 ///< VIP_CMDQ_MEM_32K ++#define VIP_CMDQ_MEM_16K 0x0004000 ///< VIP_CMDQ_MEM_16K ++#define VIP_CMDQ_MEM_TEST 0x0001000 ///< VIP_CMDQ_MEM_TEST ++#define VIP_VTRACK_KEY_SETTING_LENGTH 8 ///< VIP_VTRACK_KEY_SETTING_LENGTH ++#define VIP_VTRACK_SETTING_LENGTH 23 ///< VIP_VTRACK_SETTING_LENGTH ++ ++// ++//1.0.1:for clean vip. ++#define IOCTL_VIP_VERSION 0x0101 ///< H:Major L:minor H3:Many Change H2:adjust Struct L1:add struct L0:adjust driver ++//============================================================================= ++// enum ++//============================================================================= ++/** ++* Used to setup vsrc of vip device ++*/ ++typedef enum ++{ ++ E_VIP_SRC_ISP, ///< VIP src ISP ++ E_VIP_SRC_BT656,///< VIP src BT656 ++ E_VIP_SRC_DRAM, ///< VIP src DRAM ++ E_VIP_SRC_NUM, ///< VIP src max number ++}__attribute__ ((__packed__))EN_VIP_SRC_TYPE; ++ ++/** ++* Used to setup LCE AVE of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_LCE_Y_AVE_5X11 = 0x0, ///< mask 0x10 ++ EN_VIP_LCE_Y_AVE_5X7 = 0x10, ///< mask 0x10 ++}__attribute__ ((__packed__))EN_VIP_LCE_Y_AVE_SEL_TYPE; ++ ++ ++/** ++* Used to setup UVC_ADP_Y_INPUT_SEL of vip device ++*/ ++typedef enum ++{ ++ E_VIP_UVC_ADP_Y_INPUT_SEL_UVC_LOCATE = 0x0, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_RGB_Y_OUTPUT = 0x40, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_DLC_Y_INPUT = 0x80, ///< mask 0xC0 ++ E_VIP_UVC_ADP_Y_INPUT_SEL_RGB_Y_INPUT = 0xC0, ///< mask 0xC0 ++}__attribute__ ((__packed__))EN_VIP_UVC_ADP_Y_INPUT_SEL_TYPE; ++ ++/** ++* Used to setup LDC_BYPASS of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_MENULOAD, ///< no bypass ++ E_VIP_LDC_BYPASS, ///< bypass ++ E_VIP_LDC_BYPASS_TYPE_NUM, ///< no use ++}__attribute__ ((__packed__))EN_VIP_LDC_BYPASS_TYPE; ++/** ++* Used to setup LDCLCBANKMODE of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_LDCLCBANKMODE_64, ///< 64p ++ EN_VIP_LDCLCBANKMODE_128, ///< 128p ++}__attribute__ ((__packed__))EN_VIP_LDCLCBANKMODE_TYPE; ++ ++/** ++* Used to setup VIP_LDC_422_444 of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_422_444_DUPLICATE = 0x1, ///< mask 0x3 ++ E_VIP_LDC_422_444_QUARTER = 0x2, ///< mask 0x3 ++ E_VIP_LDC_422_444_AVERAGE = 0x3, ///< mask 0x3 ++}__attribute__ ((__packed__))EN_VIP_LDC_422_444_TYPE; ++/** ++* Used to setup VIP_LDC_444_422 of vip device ++*/ ++typedef enum ++{ ++ E_VIP_LDC_444_422_DROP = 0x0, ///< mask 0x1C ++ E_VIP_LDC_444_422_AVERAGE = 0x4, ///< mask 0x1C ++}__attribute__ ((__packed__))EN_VIP_LDC_444_422_TYPE; ++/** ++* Used to VIP_NLM_Average of vip device ++*/ ++typedef enum ++{ ++ E_VIP_NLM_Average_3x3_mode = 0x0, ///< mask 0x2 ++ E_VIP_NLM_Average_5x5_mode = 0x2, ///< mask 0x2 ++}__attribute__ ((__packed__))EN_VIP_NLM_Average_TYPE; ++/** ++* Used to NLM_DSW of vip device ++*/ ++typedef enum ++{ ++ E_VIP_NLM_DSW_16x8_mode = 0x0, ///< mask 0x20 ++ E_VIP_NLM_DSW_32x16_mode = 0x20, ///< mask 0x20 ++}__attribute__ ((__packed__))EN_VIP_NLM_DSW_TYPE; ++/** ++* Used to VIP_FCC_Y of vip device ++*/ ++typedef enum ++{ ++ E_VIP_FCC_Y_DIS_CR_DOWN, ///< cr down ++ E_VIP_FCC_Y_DIS_CR_UP, ///< cr up ++ E_VIP_FCC_Y_DIS_CB_DOWN, ///< cb down ++ E_VIP_FCC_Y_DIS_CB_UP, ///< cb up ++ E_VIP_FCC_Y_DIS_NUM, ///< 4type ++}__attribute__ ((__packed__))EN_VIP_FCC_Y_DIS_TYPE; ++/** ++* Used to setup IHC_ICE_ADP_Y of vip device ++*/ ++typedef enum ++{ ++ E_VIP_IHC_ICE_ADP_Y_SECTION_0, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_1, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_2, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_3, ///< section ++ E_VIP_IHC_ICE_ADP_Y_SECTION_NUM, ///< section ++}__attribute__ ((__packed__))EN_VIP_IHC_ICE_ADP_Y_SECTION_TYPE; ++/** ++* Used to setup suspend of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_ACK_CONFIG = 0x1, ///< ACK ++ EN_VIP_IBC_CONFIG = 0x2, ///< IBC ++ EN_VIP_IHCICC_CONFIG = 0x4, ///< ICCIHC ++ EN_VIP_ICC_CONFIG = 0x8, ///< ICE ++ EN_VIP_IHC_CONFIG = 0x10, ///< IHC ++ EN_VIP_FCC_CONFIG = 0x20, ///< FCC ++ EN_VIP_UVC_CONFIG = 0x40, ///< UVC ++ EN_VIP_DLC_HISTOGRAM_CONFIG = 0x80, ///< HIST ++ EN_VIP_DLC_CONFIG = 0x100, ///< DLC ++ EN_VIP_LCE_CONFIG = 0x200, ///< LCE ++ EN_VIP_PEAKING_CONFIG = 0x400, ///< PK ++ EN_VIP_NLM_CONFIG = 0x800, ///< NLM ++ EN_VIP_LDC_MD_CONFIG = 0x1000, ///< LDCMD ++ EN_VIP_LDC_DMAP_CONFIG = 0x2000, ///< LDCDMAP ++ EN_VIP_LDC_SRAM_CONFIG = 0x4000, ///< LDC SRAM ++ EN_VIP_LDC_CONFIG = 0x8000, ///< LDC ++ EN_VIP_CONFIG = 0x40000, ///< 19 bit to control 19 IOCTL ++}__attribute__ ((__packed__))EN_VIP_CONFIG_TYPE; ++/** ++* Used to setup the vtrack status of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_VTRACK_ENABLE_ON, ///< Vtrack on ++ EN_VIP_IOCTL_VTRACK_ENABLE_OFF, ///< Vtrack off ++ EN_VIP_IOCTL_VTRACK_ENABLE_DEBUG, ///< Vtrack debug ++}EN_VIP_IOCTL_VTRACK_ENABLE_TYPE; ++/** ++* Used to setup the AIP of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_AIP_YEE = 0, ///< yee ++ EN_VIP_IOCTL_AIP_YEE_AC_LUT, ///< yee ac lut ++ EN_VIP_IOCTL_AIP_WDR_GLOB, ///< wdr glob ++ EN_VIP_IOCTL_AIP_WDR_LOC, ///< wdr loc ++ EN_VIP_IOCTL_AIP_MXNR, ///< mxnr ++ EN_VIP_IOCTL_AIP_UVADJ, ///< uvadj ++ EN_VIP_IOCTL_AIP_XNR, ///< xnr ++ EN_VIP_IOCTL_AIP_YCUVM, ///< ycuvm ++ EN_VIP_IOCTL_AIP_COLORTRAN, ///< ct ++ EN_VIP_IOCTL_AIP_GAMMA, ///< gamma ++ EN_VIP_IOCTL_AIP_422TO444, ///< 422to444 ++ EN_VIP_IOCTL_AIP_YUVTORGB, ///< yuv2rgb ++ EN_VIP_IOCTL_AIP_GM10TO12, ///< 10 to 12 ++ EN_VIP_IOCTL_AIP_CCM, ///< ccm ++ EN_VIP_IOCTL_AIP_HSV, ///< hsv ++ EN_VIP_IOCTL_AIP_GM12TO10, ///< gm12to10 ++ EN_VIP_IOCTL_AIP_RGBTOYUV, ///< rgb2yuv ++ EN_VIP_IOCTL_AIP_444TO422, ///< 4442422 ++ EN_VIP_IOCTL_AIP_NUM, ///< Num ++}EN_VIP_IOCTL_AIP_TYPE; ++ ++/** ++* Used to setup the AIP SRAM of vip device ++*/ ++typedef enum ++{ ++ EN_VIP_IOCTL_AIP_SRAM_GAMMA_Y, ///< gamma y ++ EN_VIP_IOCTL_AIP_SRAM_GAMMA_U, ///< gamma u ++ EN_VIP_IOCTL_AIP_SRAM_GAMMA_V, ///< gamma v ++ EN_VIP_IOCTL_AIP_SRAM_GM10to12_R, ///< gamma R ++ EN_VIP_IOCTL_AIP_SRAM_GM10to12_G, ///< gamma G ++ EN_VIP_IOCTL_AIP_SRAM_GM10to12_B, ///< gamma B ++ EN_VIP_IOCTL_AIP_SRAM_GM12to10_R, ///< gamma R ++ EN_VIP_IOCTL_AIP_SRAM_GM12to10_G, ///< gamma G ++ EN_VIP_IOCTL_AIP_SRAM_GM12to10_B, ///< gamma B ++ EN_VIP_IOCTL_AIP_SRAM_WDR, ///< wdr ++ EN_VIP_IOCTL_AIP_SRAM_NUM, ///< wdr ++}EN_VIP_IOCTL_AIP_SRAM_TYPE; ++ ++//============================================================================= ++// struct ++//============================================================================= ++ ++/** ++* Used to get VIP drvier version ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned int u32Version; ///< version ++ unsigned int VerChk_Size; ///< VerChk Size ++}__attribute__ ((__packed__)) ST_IOCTL_VIP_VERSION_CONFIG; ++ ++/** ++* Used to setup CMDQ be used of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< enable CMDQ ++ unsigned char u8framecnt; ///< assign framecount ++}ST_IOCTL_VIP_FC_CONFIG; ++/** ++* Used to setup AIP config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32Viraddr; ///< AIP setting ++ EN_VIP_IOCTL_AIP_TYPE enAIPType; ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_AIP_CONFIG; ++/** ++* Used to setup AIP SRAM config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ unsigned long u32Viraddr; ///< AIP setting ++ EN_VIP_IOCTL_AIP_SRAM_TYPE enAIPType; ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_AIP_SRAM_CONFIG; ++ ++/** ++* Used to setup MCNR config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned char bEnMCNR; ++ unsigned char bEnCIIR; ++ unsigned long u32Viraddr; ///< MCNR setting ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_MCNR_CONFIG; ++ ++ ++/** ++* Used to setup LDC onoff of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLdc_path_sel; ///< reg_ldc_path_sel ++ unsigned char bEn_ldc; ///< reg_en_ldc(nonuse just bypass) ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_OnOffCONFIG; ++/** ++* Used to setup LDC mode of vip device ++*/ ++typedef struct ++{ ++ EN_VIP_LDC_422_444_TYPE en422to444; ///< reg_422to444_md ++ EN_VIP_LDC_444_422_TYPE en444to422; ///< reg_444to422_md ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_422_444_CONFIG; ++ ++/** ++* Used to setup LDC config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_LDC_OnOffCONFIG stEn; ///< be bypass ++ ST_IOCTL_VIP_LDC_422_444_CONFIG stmd; ///< set mode ++ EN_VIP_LDCLCBANKMODE_TYPE enLDCType; ///< LDC 64p or 128p ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_CONFIG; ++ ++/** ++* Used to setup LDC mode of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned char u8FBidx; ///< reg_ldc_fb_sw_idx ++ unsigned char u8FBrwdiff; ///< reg_ldc_fb_hw_rw_diff ++ unsigned char bEnSWMode; ///< reg_ldc_fb_sw_mode ++ EN_VIP_LDC_BYPASS_TYPE enbypass; ///< reg_ldc_ml_bypass ++ EN_VIP_LDCLCBANKMODE_TYPE enLDCType;///< LDC 64p or 128p ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_MD_CONFIG; ++/** ++* Used to setup LDC DMAP address of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32DMAPaddr; ///< reg_ldc_dmap_st_addr ++ unsigned short u16DMAPWidth; ///< reg_ldc_dmap_pitch ++ unsigned char u8DMAPoffset; ///< reg_ldc_dmap_blk_xstart ++ unsigned char bEnPowerSave; ///< reg_ldc_en_power_saving_mode ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_DMAP_CONFIG; ++ ++/** ++* Used to setup SRAM address of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ unsigned long u32loadhoraddr; ///< reg_ldc_load_st_addr0 ++ unsigned short u16SRAMhorstr; ///< reg_ldc_sram_st_addr0 ++ unsigned short u16SRAMhoramount; ///< reg_ldc_load_amount0 ++ unsigned long u32loadveraddr; ///< reg_ldc_load_st_addr1 ++ unsigned short u16SRAMverstr; ///< reg_ldc_sram_st_addr1 ++ unsigned short u16SRAMveramount; ///< reg_ldc_load_amount1 ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LDC_SRAM_CONFIG; ++ ++/** ++* Used to setup NLM setting of vip device ++*/ ++typedef struct ++{ ++ unsigned char bNlm_en; ///< reg_nlm_en ++ EN_VIP_NLM_Average_TYPE enAvgmode; ///< reg_nlm_avg_mode :0:3x3 1:5x5 ++ unsigned char bnlm_bdry_en; ///< reg_nlm_bdry_en ++ unsigned char bnlm_post_luma_adap_en; ///< reg_nlm_post_luma_adap_en ++ unsigned char bnlm_luma_adap_en; ///< reg_nlm_luma_adap_en ++ unsigned char bnlm_dsw_adap_en; ///< reg_nlm_dsw_adap_en ++ unsigned char bnlmdsw_lpf_en; ///< reg_nlm_dsw_lpf_en ++ unsigned char bnlm_region_adap_en; ///< reg_nlm_region_adap_en ++ EN_VIP_NLM_DSW_TYPE u8nlm_region_adap_size_config; ///< reg_nlm_region_adap_size_config 0:16x8 1:32x16 ++ unsigned char bnlm_histIIR_en; ///< reg_nlm_histiir_adap_en ++ unsigned char bnlm_bypass_en; ///< reg_nlm_bypass_en ++ unsigned char u8nlm_fin_gain; ///< reg_nlm_fin_gain ++ unsigned char u8nlm_histIIR; ///< reg_nlm_histiir_adap_ratio ++ unsigned char u8nlm_sad_shift; ///< reg_nlm_sad_shift ++ unsigned char u8nlm_sad_gain; ///< reg_nlm_sad_gain ++ unsigned char u8nlm_dsw_ratio; ///< reg_nlm_dsw_ratio ++ unsigned char u8nlm_dsw_offset; ///< reg_nlm_dsw_offset ++ unsigned char u8nlm_dsw_shift; ///< reg_nlm_dsw_shift ++ unsigned char u8nlm_weight_lut[VIP_NLM_WEIGHT_NUM]; ///< reg_nlm_weight_lut0-31 ,Qmap has adjust register squence ++ unsigned char u8nlm_luma_adap_gain_lut[VIP_NLM_LUMAGAIN_NUM]; ///< reg_nlm_luma_adap_gain_lut0-63,adjust register squence ++ unsigned char u8nlm_post_luma_adap_gain_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_nlm_post_luma_adap_gain_lut0-15,adjust register squence ++ unsigned char u8nlm_dist_weight_7x7_lut[VIP_NLM_DISTWEIGHT_NUM]; ///< reg_nlm_dist_weight_7x7_lut0-8,adjust register squence ++ unsigned char u8nlm_main_snr_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_main_snr_lut ++ unsigned char u8nlm_wb_snr_lut[VIP_NLM_POSTLUMA_NUM]; ///< reg_wb_snr_lut ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_MAIN_CONFIG; ++/** ++* Used to setup NLM autodown load of vip device ++*/ ++typedef struct ++{ ++ unsigned char bEn; ///< enable auto downlaod ++ unsigned long u32Baseadr; ///< auto download phy addr ++ unsigned long u32viradr; ///< disable auto download need virtual ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_SRAM_CONFIG; ++/** ++* Used to setup NLM config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_NLM_MAIN_CONFIG stNLM; ///< NLM setting ++ ST_IOCTL_VIP_NLM_SRAM_CONFIG stSRAM; ///< Autodownload ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_NLM_CONFIG; ++ ++ ++/** ++* Used to setup 422to444 of vip device ++*/ ++typedef struct ++{ ++ unsigned char bvip_422to444_en; ///< reg_vip_422to444_en ++ unsigned char u8vip_422to444_md; ///< reg_vip_422to444_md ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_422_444_CONFIG; ++ ++/** ++* Used to setup bypass MACE of vip device ++*/ ++typedef struct ++{ ++ unsigned char bvip_fun_bypass_en; ///< reg_vip_fun_bypass_en :except DNR,SNR,NLM,LDC ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_BYPASS_CONFIG; ++ ++/** ++* Used to setup the LB of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8vps_sram_act; ///< reg_vps_sram_act ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LINEBUFFER_CONFIG; ++/** ++* Used to setup mix vip of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_422_444_CONFIG st422_444; ///< 422 to 444 ++ ST_IOCTL_VIP_BYPASS_CONFIG stBypass; ///< bypass ++ ST_IOCTL_VIP_LINEBUFFER_CONFIG stLB; ///< VIP Mixed ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_CONFIG; ++ ++/** ++* Used to setup PK HLPF of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8main_y_lpf_coef; ///< reg_main_y_lpf_coef ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_HLPF_CONFIG; ++ ++/** ++* Used to setup PK HLPF dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char hlpf_dither_en; ///< reg_hlpf_dither_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_HLPF_DITHER_CONFIG; ++ ++/** ++* Used to setup PK VLPF of vip device ++*/ ++typedef struct ++{ ++ unsigned char main_v_lpf_coef; ///< reg_main_v_lpf_coef_1,2 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_VLPF_COEF_CONFIG; ++ ++/** ++* Used to PK VLPF dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char vlpf_dither_en; ///< reg_vlpf_dither_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_VLPF_DITHER_CONFIG; ++ ++ ++/** ++* Used to setup PK onoff of vip device ++*/ ++typedef struct ++{ ++ unsigned char bpost_peaking_en; ///< reg_main_post_peaking_en ++ unsigned char u8vps_sram_act; ///< reg_vps_sram_act ++ unsigned char u8band6_dia_filter_sel; ///< reg_main_band6_dia_filter_sel ++ unsigned char u8peaking_ac_yee_mode; ///< reg_peaking_ac_yee_mode ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ONOFFCONFIG; ++ ++/** ++* Used to setup PK band of vip device ++*/ ++typedef struct ++{ ++ unsigned char bBand_En[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_peaking_en 1-8 ++ unsigned char u8Band_COEF_STEP[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coef_step 1-8 ++ unsigned char u8Band_COEF[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coef 1-8 ++ unsigned char u8peaking_term[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_main_peaking_term1_select 1-16 ++ unsigned char u8Band_Over[VIP_PEAKING_BAND_NUM]; ///< reg_band1_overshoot_limit 1-8 ++ unsigned char u8Band_Under[VIP_PEAKING_BAND_NUM]; ///< reg_band1_undershoot_limit 1-8 ++ unsigned char u8Band_coring_thrd[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_coring_thrd 1-8 ++ unsigned char u8alpha_thrd; ///< reg_main_alpha_thrd ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_BAND_CONFIG; ++ ++/** ++* Used to setup pk adptive of vip device ++*/ ++typedef struct ++{ ++ unsigned char badaptive_en[VIP_PEAKING_BAND_NUM]; ///< reg_main_band1_adaptive_en 1-8 ++ unsigned char u8hor_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_hor_lut_0-15 ++ unsigned char u8ver_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_ver_lut_0-15 ++ unsigned char u8low_diff_thrd_and_adaptive_gain_step[VIP_PEAKING_BAND_TERM_NUM]; ///< alternation(reg_band1_adaptive_gain_step, reg_band1_low_diff_thrd) 1-8 ++ unsigned char u8dia_lut[VIP_PEAKING_BAND_TERM_NUM]; ///< reg_dia_lut_0-15 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ADPTIVE_CONFIG; ++ ++/** ++* Used to setup PK preCoring of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8coring_thrd_1; ///< reg_main_coring_thrd_1 ++ unsigned char u8coring_thrd_2; ///< reg_main_coring_thrd_2 ++ unsigned char u8coring_thrd_step; ///< reg_main_coring_thrd_step ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_PCORING_CONFIG; ++ ++/** ++* Used to setup pk ADP_Y of vip device ++*/ ++typedef struct ++{ ++ unsigned char bcoring_adp_y_en; ///< reg_main_coring_adp_y_en ++ unsigned char bcoring_adp_y_alpha_lpf_en; ///< reg_main_coring_adp_y_alpha_lpf_en ++ unsigned char u8coring_y_low_thrd; ///< reg_main_coring_y_low_thrd ++ unsigned char u8coring_adp_y_step; ///< reg_main_coring_adp_y_step ++ unsigned char u8coring_adp_y_alpha_lut[VIP_PEAKING_ADP_Y_LUT_NUM]; ///< reg_main_coring_adp_y_alpha_lut_0-7 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_ADP_Y_CONFIG; ++ ++/** ++* Used to setup PK gain of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8osd_sharpness_ctrl ; ///< reg_main_osd_sharpness_ctrl ++ unsigned char bosd_sharpness_sep_hv_en; ///< reg_main_osd_sharpness_sep_hv_en ++ unsigned char u8osd_sharpness_ctrl_h ; ///< reg_main_osd_sharpness_ctrl_h ++ unsigned char u8osd_sharpness_ctrl_v ; ///< reg_main_osd_sharpness_ctrl_v ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_GAIN_CONFIG; ++ ++/** ++* Used to setup PK adpy gain of vip device ++*/ ++typedef struct ++{ ++ unsigned char bpk_adp_y_en; ///< reg_main_coring_adp_y_en ++ unsigned char bpk_adp_y_alpha_lpf_en; ///< reg_main_coring_adp_y_alpha_lpf_en ++ unsigned char u8pk_y_low_thrd; ///< reg_main_coring_y_low_thrd ++ unsigned char u8pk_adp_y_step; ///< reg_main_coring_adp_y_step ++ unsigned char u8pk_adp_y_alpha_lut[VIP_PEAKING_ADP_Y_LUT_NUM]; ///< reg_main_coring_adp_y_alpha_lut_0-7 ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_GAIN_ADP_Y_CONFIG; ++ ++/** ++* Used to setup pk yc gain of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16Dlc_in_y_gain; ///< reg_dlc_in_y_gain 16bit ++ unsigned short u16Dlc_in_y_offset; ///< reg_dlc_in_y_offset 16 bit ++ unsigned short u16Dlc_in_c_gain; ///< reg_dlc_in_c_gain 16 bit ++ unsigned short u16Dlc_in_c_offset; ///< reg_dlc_in_c_offset 16 bit ++ unsigned short u16Dlc_out_y_gain; ///< reg_dlc_out_y_gain 16 bit ++ unsigned short u16Dlc_out_y_offset;///< reg_dlc_out_y_offset 16 bit ++ unsigned short u16Dlc_out_c_gain; ///< reg_dlc_out_c_gain 16 bit ++ unsigned short u16Dlc_out_c_offset;///< reg_dlc_out_c_offset 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_YC_GAIN_OFFSET_CONFIG; ++ ++/** ++* Used to setup pk config of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_HLPF_CONFIG stHLPF; ///< HLPF ++ ST_IOCTL_VIP_HLPF_DITHER_CONFIG stHLPFDith; ///< HDither ++ ST_IOCTL_VIP_VLPF_COEF_CONFIG stVLPFcoef1; ///< VLPF coef1 ++ ST_IOCTL_VIP_VLPF_COEF_CONFIG stVLPFcoef2; ///< VLPF coef2 ++ ST_IOCTL_VIP_VLPF_DITHER_CONFIG stVLPFDith; ///< VDither ++ ST_IOCTL_VIP_PEAKING_ONOFFCONFIG stOnOff; ///< pkonoff ++ ST_IOCTL_VIP_PEAKING_BAND_CONFIG stBand; ///< pkband ++ ST_IOCTL_VIP_PEAKING_ADPTIVE_CONFIG stAdp; ///< pk adp ++ ST_IOCTL_VIP_PEAKING_PCORING_CONFIG stPcor; ///< pk precore ++ ST_IOCTL_VIP_PEAKING_ADP_Y_CONFIG stAdpY; ///< pk adp y ++ ST_IOCTL_VIP_PEAKING_GAIN_CONFIG stGain; ///< pk gain ++ ST_IOCTL_VIP_PEAKING_GAIN_ADP_Y_CONFIG stGainAdpY; ///< pk Y gain ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_PEAKING_CONFIG; ++ ++ ++/** ++* Used to setup LCE of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_En; ///< LCE en ++ unsigned char u8ControlNum; ///< vip control guard pipe number ++ ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_ONOFF_CONFIG; ++ ++ ++/** ++* Used to setup LCE dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_Dither_En; ///< LCE dither ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_DITHER_CONFIG; ++ ++/** ++* Used to setup LCE config of vip device ++*/ ++typedef struct ++{ ++ unsigned char bLCE_sodc_alpha_en; ///< reg_main_lce_sodc_alpha_en ++ unsigned char bLce_dering_alpha_en; ///< reg_main_lce_dering_alpha_en ++ EN_VIP_LCE_Y_AVE_SEL_TYPE enLce_y_ave_sel; ///< reg_main_lce_y_ave_sel (1'b1: 5x7; 1'b0:5x11) ++ unsigned char bLce_3curve_en; ///< reg_lce_3curve_en ++ unsigned char u8Lce_std_slop1; ///< reg_main_lce_std_slop1 ++ unsigned char u8Lce_std_slop2; ///< reg_main_lce_std_slop2 ++ unsigned char u8Lce_std_th1; ///< reg_main_lce_std_th1 ++ unsigned char u8Lce_std_th2; ///< reg_main_lce_std_th2 ++ unsigned char u8Lce_gain_min; ///< reg_main_lce_gain_min ++ unsigned char u8Lce_gain_max; ///< reg_main_lce_gain_max ++ unsigned char u8Lce_sodc_low_alpha; ///< reg_main_lce_sodc_low_alpha ++ unsigned char u8Lce_sodc_low_th; ///< reg_main_lce_sodc_low_th ++ unsigned char u8Lce_sodc_slop; ///< reg_main_lce_sodc_slop ++ unsigned char u8Lce_diff_gain; ///< reg_main_lce_diff_gain ++ unsigned char u8Lce_gain_complex; ///< reg_main_lce_gain_complex ++ unsigned char u8Lce_dsw_minsadgain; ///< reg_dsptch_lce_dsw_minsadgain ++ unsigned char u8Lce_dsw_gain; ///< reg_dsptch_lce_dsw_gian ++ unsigned char u8LCE_dsw_thrd; ///< reg_dsptch_lce_dsw_thrd ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_SETTING_CONFIG; ++ ++/** ++* Used to setup LCE curve of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8Curve_Thread[4]; ///< reg_main_lce_curve_a-d ++ unsigned short u16Curve1[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut1_08-f8 (lsb|msb) 16bit ++ unsigned short u16Curve2[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut2_08-f8 (lsb|msb) 16bit ++ unsigned short u16Curve3[VIP_LCE_CURVE_SECTION_NUM]; ///< reg_lce_curve_lut3_08-f8 (lsb|msb) 16bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_CRUVE_CONFIG; ++ ++/** ++* Used to setup LCE of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_LCE_ONOFF_CONFIG stOnOff; ///< bEn ++ ST_IOCTL_VIP_LCE_DITHER_CONFIG stDITHER; ///< dither ++ ST_IOCTL_VIP_LCE_SETTING_CONFIG stSet; ///< config ++ ST_IOCTL_VIP_LCE_CRUVE_CONFIG stCurve; ///< curve ++ // VerChk_Version & VerChk_Size must be the latest 2 parameter and ++ // the order can't be changed ++ unsigned int VerChk_Size; ///< VerChk Size ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_LCE_CONFIG; ++ ++/** ++* Used to setup DLC prog of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8VARCP[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_curve_fit_var_cp1 -64 ++ unsigned char u8Tbln0; ///< reg_main_curve_table_n0 ++ unsigned char u8Tbln0LSB; ///< reg_main_curve_table_n0_LSB ++ unsigned char u8Tbln0sign; ///< reg_main_curve_table_n0_sign ++ unsigned short u16Tbl64; ///< reg_main_curve_table64 16 bit ++ unsigned char u8Tbl64LSB; ///< reg_main_curve_table64_LSB ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_PROG_CONFIG; ++ ++//IOCTL_VIP_SET_DLC_CURVE_CONFIG ++/** ++* Used to setup DLC curve config of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8InLuma[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_main_curve_table0-63 ++ unsigned char u8InLumaLSB[VIP_DLC_LUMA_SECTION_NUM]; ///< reg_main_curve_table0-63 LSB ++ ST_IOCTL_VIP_DLC_PROG_CONFIG ProgCfg; ///< dlc proc ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_CURVE_CONFIG; ++ ++/** ++* Used to DLC enable of vip device ++*/ ++typedef struct ++{ ++ unsigned char bcurve_fit_var_pw_en; ///< reg_main_curve_fit_var_pw_en ++ ST_IOCTL_VIP_DLC_CURVE_CONFIG stCurve; ///< curve config ++ unsigned char bcurve_fit_en; ///< reg_main_curve_fit_en ++ unsigned char bstatistic_en; ///< reg_main_statistic_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_ENABLE_CONFIG; ++ ++/** ++* Used to setup dic dither of vip device ++*/ ++typedef struct ++{ ++ unsigned char bDLCdither_en; ///< bdlc dither ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_DITHER_CONFIG; ++ ++/** ++* Used to setup DLC range of vip device ++*/ ++typedef struct ++{ ++ unsigned char u8brange_en; ///< brange ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_EN_CONFIG; ++ ++/** ++* Used to setup DLC H of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16statistic_h_start; ///< reg_main_statistic_h_start 16 bit ++ unsigned short u16statistic_h_end; ///< reg_main_statistic_h_end 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_H_CONFIG; ++ ++/** ++* Used to setup DLC V of vip device ++*/ ++typedef struct ++{ ++ unsigned short u16statistic_v_start; ///< reg_main_statistic_v_start 16 bit ++ unsigned short u16statistic_v_end; ///< reg_main_statistic_v_end 16 bit ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_HISTOGRAM_V_CONFIG; ++ ++/** ++* Used to setup DLC PC of vip device ++*/ ++typedef struct ++{ ++ unsigned char bhis_y_rgb_mode_en; ///< reg_his_y_rgb_mode_en ++ unsigned char bcurve_fit_rgb_en; ///< reg_main_curve_fit_rgb_en ++} __attribute__ ((__packed__)) ST_IOCTL_VIP_DLC_PC_CONFIG; ++/** ++* Used to setup DLC of vip device ++*/ ++typedef struct ++{ ++ unsigned int VerChk_Version ; ///< VerChk version ++ ST_IOCTL_VIP_FC_CONFIG stFCfg; ///< CMDQ ++ ST_IOCTL_VIP_YC_GAIN_OFFSET_CONFIG stGainOffset; ///< Gain ++ ST_IOCTL_VIP_DLC_ENABLE_CONFIG stEn; ///< EN ++ ST_IOCTL_VIP_DLC_DITHER_CONFIG stDither; ///< Dither ++ ST_IOCTL_VIP_DLC_HISTOGRAM_EN_CONFIG sthist; ///< hist ++ ST_IOCTL_VIP_DLC_HISTOGRAM_H_CONFIG stHistH; ///>16)&0x0000FFFF));}while(0) ++ ++#define XTAL_26000K 26000000 ++#define XTAL_24000K 24000000 ++#define XTAL_16369K 16369000 ++#define XTAL_16367K 16367000 ++ ++//typedef struct ++//{ ++// unsigned char tagPrefix[3]; ++// unsigned char headerVersion[1]; ++// unsigned char libType[2]; ++// unsigned char chip[2]; ++// unsigned char changelist[8]; ++// unsigned char component[12]; ++// unsigned char reserved[1]; ++// unsigned char tagSuffix[3]; ++// unsigned char* extension; ++// ++// ++//} MS_VERSION; ++ ++#define STR_HELPER(x) #x ++#define STR(x) STR_HELPER(x) ++ ++ ++struct MS_BIN_OPTION ++{ ++ u8 name[8]; ++ u8 args[8]; ++}; ++ ++typedef enum ++{ ++ MS_BOOT_DEV_NONE=0x00, ++ MS_BOOT_DEV_SPI=0x01, ++ MS_BOOT_DEV_EMMC=0x02, ++ MS_BOOT_DEV_8051=0x03, ++} MS_BOOT_DEV_TYPE; ++ ++typedef enum ++{ ++ MS_STORAGE_UNKNOWN =0x00, ++ MS_STORAGE_NOR, ++ MS_STORAGE_NAND, ++ MS_STORAGE_EMMC, ++ MS_STORAGE_SPINAND_ECC, ++ MS_STORAGE_SPINAND_NOECC, ++} MS_STORAGE_TYPE; ++ ++extern void Chip_Flush_MIU_Pipe(void); ++extern void Chip_Flush_Memory(void); ++extern void Chip_Read_Memory(void); ++ ++extern int Chip_Cache_Outer_Is_Enabled(void); ++extern void Chip_Flush_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++extern void Chip_Clean_Cache_Range_VA_PA(unsigned long u32VAddr,unsigned long u32PAddr,unsigned long u32Size); ++extern void Chip_Flush_Cache_Range(unsigned long u32Addr, unsigned long u32Size); ++extern void Chip_Clean_Cache_Range(unsigned long u32Addr, unsigned long u32Size); ++extern void Chip_Inv_Cache_Range(unsigned long u32Addr, unsigned long u32Size); ++extern void Chip_Flush_CacheAll(void); ++ ++extern u64 Chip_Phys_to_MIU(u64 phys); ++extern u64 Chip_MIU_to_Phys(u64 miu); ++ ++extern char* Chip_Get_Platform_Name(void); ++extern int Chip_Get_Device_ID(void); ++extern int Chip_Get_Revision(void); ++ ++extern int Chip_Boot_Get_Dev_Type(void); ++extern unsigned long long Chip_Get_RIU_Phys(void); ++extern int Chip_Get_RIU_Size(void); ++extern int Chip_Function_Set(int function_id, int param); ++ ++extern int Chip_Get_Storage_Type(void); ++extern int Chip_Get_Package_Type(void); ++extern u64 Chip_Get_US_Ticks(void); ++ ++typedef enum ++{ ++ CHIP_FUNC_UART_ENABLE_LINE=0x0001, ++ CHIP_FUNC_UART_DISABLE_LINE, ++ CHIP_FUNC_IR_ENABLE, ++ CHIP_FUNC_USB_VBUS_CONTROL, ++ CHIP_FUNC_MCM_DISABLE_ID, ++ CHIP_FUNC_MCM_ENABLE_ID, ++ CHIP_FUNC_END, ++ CHIP_FUNC_DUMMY=0xFFFF ++}EN_CHIP_FUNC_ID; ++ ++ ++#endif +diff --git a/drivers/mstar/include/ms_types.h b/drivers/mstar/include/ms_types.h +new file mode 100644 +index 00000000..be42c29a +--- /dev/null ++++ b/drivers/mstar/include/ms_types.h +@@ -0,0 +1,21 @@ ++//------------------------------------------------------------------------------ ++// ++// Copyright (c) 2010 MStar Semiconductor, Inc. All rights reserved. ++// ++//------------------------------------------------------------------------------ ++// FILE ++// ++// DESCRIPTION ++// This header file defines some utilities. ++// ++// HISTORY ++// ++//------------------------------------------------------------------------------ ++#ifndef __MS_TYPE_H__ ++#define __MS_TYPE_H__ ++ ++#include "mdrv_types.h" ++ ++ ++#endif // __MS_TYPE_H__ ++ +diff --git a/drivers/mstar/ir/IR_MSTAR_DTV.h b/drivers/mstar/ir/IR_MSTAR_DTV.h +new file mode 100644 +index 00000000..cbc743ef +--- /dev/null ++++ b/drivers/mstar/ir/IR_MSTAR_DTV.h +@@ -0,0 +1,261 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (��MStar Confidential Information��) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef IR_FORMAT_H ++#define IR_FORMAT_H ++ ++#define XTAL_CLOCK_FREQ 24000000 ++ ++//------------------------------------------------------------------------------------------- ++// Customer IR Specification parameter define (Please modify them by IR SPEC) ++//------------------------------------------------------------------------------------------- ++#ifdef CONFIG_MSTAR_PM_SWIR ++#define IR_MODE_SEL IR_MODE_SWDECODE_MODE//IR_TYPE_SWDECODE_MODE//IR_TYPE_RAWDATA_MODE ++#else ++#define IR_MODE_SEL IR_MODE_FULLDECODE_MODE ++#endif ++// IR Header code define ++#define IR_HEADER_CODE0 0x80 // Custom 0 ++#define IR_HEADER_CODE1 0x7F // Custom 1 ++ ++// IR Timing define ++#define IR_HEADER_CODE_TIME 9000 // us ++#define IR_OFF_CODE_TIME 4500 // us ++#define IR_OFF_CODE_RP_TIME 2500 // us ++#define IR_LOGI_01H_TIME 560 // us ++#define IR_LOGI_0_TIME 1120 // us ++#define IR_LOGI_1_TIME 2240 // us ++#define IR_TIMEOUT_CYC 140000 // us ++ ++// IR Format define ++#define IRKEY_DUMY 0xFF ++#define IRDA_KEY_MAPPING_POWER IRKEY_POWER ++// ++//typedef enum _IrCommandType ++//{ ++// IRKEY_TV_RADIO = 0x0C, ++// IRKEY_CHANNEL_LIST = 0x10, ++// IRKEY_CHANNEL_FAV_LIST = 0x08, ++// IRKEY_CHANNEL_RETURN = 0x5C, ++// IRKEY_CHANNEL_PLUS = 0x1F, ++// IRKEY_CHANNEL_MINUS = 0x19, ++// ++// IRKEY_AUDIO = 0x44, ++// IRKEY_VOLUME_PLUS = 0x16, ++// IRKEY_VOLUME_MINUS = 0x15, ++// ++// IRKEY_UP = 0x52, ++// IRKEY_POWER = 0x46, ++// IRKEY_EXIT = 0x1B, ++// IRKEY_MENU = 0x07, ++// IRKEY_DOWN = 0x13, ++// IRKEY_LEFT = 0x06, ++// IRKEY_SELECT = 0x0F, ++// IRKEY_RIGHT = 0x1A, ++// ++// IRKEY_NUM_0 = 0x50, ++// IRKEY_NUM_1 = 0x49, ++// IRKEY_NUM_2 = 0x55, ++// IRKEY_NUM_3 = 0x59, ++// IRKEY_NUM_4 = 0x4D, ++// IRKEY_NUM_5 = 0x51, ++// IRKEY_NUM_6 = 0x5D, ++// IRKEY_NUM_7 = 0x48, ++// IRKEY_NUM_8 = 0x54, ++// IRKEY_NUM_9 = 0x58, ++// ++// IRKEY_MUTE = 0x5A, ++// IRKEY_PAGE_UP = 0x03, ++// IRKEY_PAGE_DOWN = 0x05, ++// IRKEY_CLOCK = 0x5F, ++// ++// IRKEY_INFO = 0x14, ++// IRKEY_RED = 0x47, ++// IRKEY_GREEN = 0x4B, ++// IRKEY_YELLOW = 0x57, ++// IRKEY_BLUE = 0x5B, ++// IRKEY_MTS = 0x41, ++// IRKEY_NINE_LATTICE = IRKEY_DUMY, ++// IRKEY_TTX = 0x0A, ++// IRKEY_CC = 0x09, ++// IRKEY_INPUT_SOURCE = 0x04, ++// IRKEY_CRADRD = IRKEY_DUMY-1, ++//// IRKEY_PICTURE = 0x40, ++// IRKEY_ZOOM = 0x4C, ++// IRKEY_DASH = 0x4E, ++// IRKEY_SLEEP = 0x45, ++// IRKEY_EPG = 0x4A, ++// IRKEY_PIP = 0x40, ++// ++// IRKEY_MIX = 0x1C, ++// IRKEY_INDEX = 0x18, ++// IRKEY_HOLD = 0x00, ++// IRKEY_PREVIOUS = 0x0E, ++// IRKEY_NEXT = 0x12, ++// IRKEY_BACKWARD = 0x02, ++// IRKEY_FORWARD = 0x1E, ++// IRKEY_PLAY = 0x01, ++// IRKEY_RECORD = 0x0D, ++// IRKEY_STOP = 0x11, ++// IRKEY_PAUSE = 0x1D, ++// ++// IRKEY_SIZE = 0x43, ++// IRKEY_REVEAL = 0x4F, ++// IRKEY_SUBCODE = 0x53, ++//}IrCommandType; ++//------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------- ++// IR system parameter define for H/W setting (Please don't modify them) ++//------------------------------------------------------------------------------------------- ++#define IR_CKDIV_NUM ((XTAL_CLOCK_FREQ+500000)/1000000) ++#define IR_CKDIV_NUM_BOOT XTAL_CLOCK_FREQ ++#define IR_CLK_BOOT (XTAL_CLOCK_FREQ/1000000) ++#define IR_CLK IR_CLK_BOOT ++ ++#define irGetMinCnt_BOOT(time, tolerance) ((u32)(((double)time*((double)IR_CLK_BOOT)/(IR_CKDIV_NUM_BOOT+1))*((double)1-tolerance))) ++#define irGetMaxCnt_BOOT(time, tolerance) ((u32)(((double)time*((double)IR_CLK_BOOT)/(IR_CKDIV_NUM_BOOT+1))*((double)1+tolerance))) ++#define irGetMinCnt(time, tolerance) ((u32)(((double)time*((double)IR_CLK)/(IR_CKDIV_NUM+1))*((double)1-tolerance))) ++#define irGetMaxCnt(time, tolerance) ((u32)(((double)time*((double)IR_CLK)/(IR_CKDIV_NUM+1))*((double)1+tolerance))) ++ ++#define irGetCnt_BOOT(time) ((u32)((double)time*((double)IR_CLK_BOOT)/(IR_CKDIV_NUM_BOOT+1))) ++#define irGetCnt(time) ((u32)((double)time*((double)IR_CLK)/(IR_CKDIV_NUM+1))) ++ ++// 12Mhz ++#define IR_RP_TIMEOUT_BOOT irGetCnt_BOOT(IR_TIMEOUT_CYC) ++#define IR_HDC_UPB_BOOT irGetMaxCnt_BOOT(IR_HEADER_CODE_TIME, 0.2) ++#define IR_HDC_LOB_BOOT irGetMinCnt_BOOT(IR_HEADER_CODE_TIME, 0.2) ++#define IR_OFC_UPB_BOOT irGetMaxCnt_BOOT(IR_OFF_CODE_TIME, 0.2) ++#define IR_OFC_LOB_BOOT irGetMinCnt_BOOT(IR_OFF_CODE_TIME, 0.2) ++#define IR_OFC_RP_UPB_BOOT irGetMaxCnt_BOOT(IR_OFF_CODE_RP_TIME, 0.2) ++#define IR_OFC_RP_LOB_BOOT irGetMinCnt_BOOT(IR_OFF_CODE_RP_TIME, 0.2) ++#define IR_LG01H_UPB_BOOT irGetMaxCnt_BOOT(IR_LOGI_01H_TIME, 0.35) ++#define IR_LG01H_LOB_BOOT irGetMinCnt_BOOT(IR_LOGI_01H_TIME, 0.3) ++#define IR_LG0_UPB_BOOT irGetMaxCnt_BOOT(IR_LOGI_0_TIME, 0.2) ++#define IR_LG0_LOB_BOOT irGetMinCnt_BOOT(IR_LOGI_0_TIME, 0.2) ++#define IR_LG1_UPB_BOOT irGetMaxCnt_BOOT(IR_LOGI_1_TIME, 0.2) ++#define IR_LG1_LOB_BOOT irGetMinCnt_BOOT(IR_LOGI_1_TIME, 0.2) ++ ++// 90Mhz ++#define IR_RP_TIMEOUT irGetCnt(IR_TIMEOUT_CYC) ++#define IR_HDC_UPB irGetMaxCnt(IR_HEADER_CODE_TIME, 0.2) ++#define IR_HDC_LOB irGetMinCnt(IR_HEADER_CODE_TIME, 0.2) ++#define IR_OFC_UPB irGetMaxCnt(IR_OFF_CODE_TIME, 0.2) ++#define IR_OFC_LOB irGetMinCnt(IR_OFF_CODE_TIME, 0.2) ++#define IR_OFC_RP_UPB irGetMaxCnt(IR_OFF_CODE_RP_TIME, 0.2) ++#define IR_OFC_RP_LOB irGetMinCnt(IR_OFF_CODE_RP_TIME, 0.2) ++#define IR_LG01H_UPB irGetMaxCnt(IR_LOGI_01H_TIME, 0.35) ++#define IR_LG01H_LOB irGetMinCnt(IR_LOGI_01H_TIME, 0.3) ++#define IR_LG0_UPB irGetMaxCnt(IR_LOGI_0_TIME, 0.2) ++#define IR_LG0_LOB irGetMinCnt(IR_LOGI_0_TIME, 0.2) ++#define IR_LG1_UPB irGetMaxCnt(IR_LOGI_1_TIME, 0.2) ++#define IR_LG1_LOB irGetMinCnt(IR_LOGI_1_TIME, 0.2) ++ ++//------------------------------------------------------------------------------------------- ++ ++#include ++ ++/* ++ * Jimmy Hsu ++ * this is the remote control that comes with the mstar smart tv ++ * which based on STAOS standard. ++ */ ++static struct rc_map_table mstar_tv[] = { ++ { 0x0046, KEY_POWER }, ++ { 0x0050, KEY_0 }, ++ { 0x0049, KEY_1 }, ++ { 0x0055, KEY_2 }, ++ { 0x0059, KEY_3 }, ++ { 0x004D, KEY_4 }, ++ { 0x0051, KEY_5 }, ++ { 0x005D, KEY_6 }, ++ { 0x0048, KEY_7 }, ++ { 0x0054, KEY_8 }, ++ { 0x0058, KEY_9 }, ++ { 0x0047, KEY_RED }, ++ { 0x004B, KEY_GREEN }, ++ { 0x0057, KEY_YELLOW }, ++ { 0x005B, KEY_BLUE }, ++ { 0x0052, KEY_UP }, ++ { 0x0013, KEY_DOWN }, ++ { 0x0006, KEY_LEFT }, ++ { 0x001A, KEY_RIGHT }, ++ { 0x000F, KEY_ENTER }, ++ { 0x001F, KEY_CHANNELUP }, ++ { 0x0019, KEY_CHANNELDOWN }, ++ { 0x0016, KEY_VOLUMEUP }, ++ { 0x0015, KEY_VOLUMEDOWN }, ++ { 0x0003, KEY_PAGEUP }, ++ { 0x0005, KEY_PAGEDOWN }, ++ { 0x0017, KEY_HOME}, ++ { 0x0007, KEY_MENU }, ++ { 0x001B, KEY_BACK }, ++ { 0x005A, KEY_MUTE }, ++ { 0x000D, KEY_RECORD }, // DVR ++ { 0x0042, KEY_HELP }, // GUIDE ++ { 0x0014, KEY_INFO }, ++ { 0x0040, KEY_KP0 }, // WINDOW ++ { 0x0004, KEY_KP1 }, // TV_INPUT ++ { 0x000E, KEY_REWIND }, ++ { 0x0012, KEY_FORWARD }, ++ { 0x0002, KEY_PREVIOUSSONG }, ++ { 0x001E, KEY_NEXTSONG }, ++ { 0x0001, KEY_PLAY }, ++ { 0x001D, KEY_PAUSE }, ++ { 0x0011, KEY_STOP }, ++ { 0x0044, KEY_AUDIO }, // (C)SOUND_MODE ++ { 0x0056, KEY_CAMERA }, // (C)PICTURE_MODE ++ { 0x004C, KEY_ZOOM }, // (C)ASPECT_RATIO ++ { 0x005C, KEY_CHANNEL }, // (C)CHANNEL_RETURN ++ { 0x0045, KEY_SLEEP }, // (C)SLEEP ++ { 0x004A, KEY_EPG }, // (C)EPG ++ { 0x0010, KEY_LIST }, // (C)LIST ++ { 0x0053, KEY_SUBTITLE }, // (C)SUBTITLE ++ { 0x0041, KEY_FN_F1 }, // (C)MTS ++ { 0x004E, KEY_FN_F2 }, // (C)FREEZE ++ { 0x000A, KEY_FN_F3 }, // (C)TTX ++ { 0x0009, KEY_FN_F4 }, // (C)CC ++ { 0x001C, KEY_FN_F5 }, // (C)TV_SETTING ++ { 0x0008, KEY_FN_F6 }, // (C)SCREENSHOT ++ { 0x000B, KEY_F1 }, // MSTAR_BALANCE ++ { 0x0018, KEY_F2 }, // MSTAR_INDEX ++ { 0x0000, KEY_F3 }, // MSTAR_HOLD ++ { 0x000C, KEY_F4 }, // MSTAR_UPDATE ++ { 0x004F, KEY_F5 }, // MSTAR_REVEAL ++ { 0x005E, KEY_F6 }, // MSTAR_SUBCODE ++ { 0x0043, KEY_F7 }, // MSTAR_SIZE ++ { 0x005F, KEY_F8 }, // MSTAR_CLOCK ++ { 0x00FE, KEY_POWER2 }, // FAKE_POWER ++ { 0x00FF, KEY_OK }, // KEY_OK ++ ++ // 2nd IR controller. ++}; ++ ++#define MS_IR_MAP_NAME "rc-mstar-dtv" ++#define MS_IR_VENDOR_ID 0x3697 ++ ++static struct rc_map_list ms_rc_map = { ++ .map = { ++ .scan = mstar_tv, ++ .size = ARRAY_SIZE(mstar_tv), ++ .rc_type = RC_TYPE_UNKNOWN, /* Legacy IR type */ ++ .name = MS_IR_MAP_NAME, ++ } ++}; ++ ++#endif ++ +diff --git a/drivers/mstar/ir/Kconfig b/drivers/mstar/ir/Kconfig +new file mode 100644 +index 00000000..faa5a75a +--- /dev/null ++++ b/drivers/mstar/ir/Kconfig +@@ -0,0 +1,46 @@ ++config MS_IR ++ ++tristate "IR Remote Control Receiver" ++ ++help ++ Titania IrDA driver function ++ ++#=================================================== ++# FANTASY PROTOCOL ++#=================================================== ++if MS_IR ++ ++config MS_IR_FANTASY_MODE ++ bool "Support fantasy protocol" ++ default n ++ help ++ Support fantasy protocol ++ ++config MS_IR_INPUT_DEVICE ++ bool "IR input layer device" ++ default n ++ select VIDEO_IR ++ help ++ Use MStar IR driver as input layer device like keyboard, ++ This depend on VIDEO_IR and will auto enable it. ++ ++config IR_SUPPLY_RNG ++bool "Supply to random number generator device" ++default n ++help ++ Supply to random number generator device ++ ++config MS_IR_MULTIPLE_MODE ++ bool "Support multiple protocol" ++ default n ++ help ++ Support multiple protocol ++ ++config MSTAR_PM_SWIR ++bool "Support PM receive SWIR decode" ++default n ++help ++ Support PM receive SWIR decode ++ ++endif ++ +diff --git a/drivers/mstar/ir/Makefile b/drivers/mstar/ir/Makefile +new file mode 100644 +index 00000000..5a79d36c +--- /dev/null ++++ b/drivers/mstar/ir/Makefile +@@ -0,0 +1,10 @@ ++# ++# Makefile for the kernel IrDA char device drivers. ++# ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/ir ++EXTRA_CFLAGS += -Iinclude/linux ++ ++obj-$(CONFIG_MS_IR) += kdrv_ir.o ++kdrv_ir-y += ms_ir.o ++ +diff --git a/drivers/mstar/ir/ms_ir.c b/drivers/mstar/ir/ms_ir.c +new file mode 100644 +index 00000000..ecd9c085 +--- /dev/null ++++ b/drivers/mstar/ir/ms_ir.c +@@ -0,0 +1,1813 @@ ++/* ++ * ms_ir.c ++ * ++ * Created on: 2015å¹´7月1æ—¥ ++ * Author: Administrator ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include //added ++#include //added ++#include //added ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include "ms_ir.h" ++#include "ms_platform.h" ++ ++#ifndef IR_TYPE_SEL ++#define IR_TYPE_SEL IR_TYPE_MSTAR_DTV ++#endif ++ ++#if(IR_TYPE_SEL == IR_TYPE_MSTAR_DTV) ++#include "IR_MSTAR_DTV.h" ++#else ++#error "undefined IR_TYPE_SEL" ++#endif ++ ++ ++#define MS_IR_INPUT_NAME "Mstar IR" ++ ++#define IRFLAG_IRENABLE 0x00000001 ++#define IRFLAG_HWINITED 0x00000002 ++ ++#define REG(addr) (*(volatile u32 *)(addr + (u32)ms_ir->membase)) ++#define IR_PRINT(fmt, args...) //printk(KERN_EMERG "IR: [%05d] " fmt, __LINE__, ## args) ++ ++static int ms_ir_probe(struct platform_device *); ++static int ms_ir_remove(struct platform_device *); ++static int ms_ir_suspend(struct platform_device *, pm_message_t state); ++static int ms_ir_resume(struct platform_device *); ++static BOOL _MDrv_IR_GetKey(U8 *pu8Key, U8 *pu8System, U8 *pu8Flag); ++static void _MDrv_IR_ClearFIFO(void); ++// ++//#ifdef CONFIG_MSTAR_SOFTWARE_IR_MODULE ++//extern int take_over_by_software_ir(unsigned char, unsigned char, unsigned char, struct input_dev *, struct ir_input_state *); ++//extern int software_ir_enable(); ++//extern int take_over_by_software_ir_dfb(unsigned char, unsigned char); ++//extern int software_ir_processing_undone(); ++//extern int set_software_ir_processing_undone(); ++//#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Macros ++//------------------------------------------------------------------------------------------------- ++#define IR_PRINT(fmt, args...) //printk(KERN_EMERG "IR: [%05d] " fmt, __LINE__, ## args) ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++ ++static U8 bIRPass = 0; ++static u8 _u8IRHeaderCode0 = IR_HEADER_CODE0; ++static u8 _u8IRHeaderCode1 = IR_HEADER_CODE1; ++static u8 ir_irq_depth; ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++#ifndef IR2_HEADER_CODE0 ++#define IR2_HEADER_CODE0 0xff ++#endif ++#ifndef IR2_HEADER_CODE1 ++#define IR2_HEADER_CODE1 0xff ++#endif ++static u8 _u8IR2HeaderCode0 = IR2_HEADER_CODE0; ++static u8 _u8IR2HeaderCode1 = IR2_HEADER_CODE1; ++#endif ++ ++#define IR_RAW_DATA_NUM 4 ++//#define IR_FILTER_REPEAT_NUM 1 ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++#define IR_SWDECODE_MODE_BUF_LEN 100 ++#endif ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++#if(IR_TYPE_SEL != IR_TYPE_RCMM) ++static u32 _u32IRData[IR_SWDECODE_MODE_BUF_LEN]; ++static u32 _u32IRCount=0; ++#endif ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structurs ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_IR_KEY_PROPERTY_INIT, ++ E_IR_KEY_PROPERTY_1st, ++ E_IR_KEY_PROPERTY_FOLLOWING ++} IRKeyProperty; ++ ++struct MS_IR_DEVICE ++{ ++ struct rc_dev *dev; ++ unsigned char __iomem *membase; /* read/write[bwl] */ ++ int irq_in; ++ int irq_rc; ++ int protocol; ++ struct fasync_struct *async_queue; /* asynchronous readers */ ++ struct completion key_completion; ++ struct work_struct key_dispatch_work; ++ unsigned int IRFlag; ++}; ++ ++ ++static struct MS_IR_DEVICE *ms_ir; ++ ++ ++//#ifdef CONFIG_MSTAR_SOFTWARE_IR_MODULE ++//u8 u8Key_for_mdrv_software_ir = 0; ++//u8 u8RepeatFlag_for_mdrv_software_ir = 0; ++//#endif ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Forward declaration ++//-------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++#if (IR_MODE_SEL == IR_MODE_RAWDATA_MODE) ++static u8 _u8IRRawModeBuf[IR_RAW_DATA_NUM]; ++static u32 _u8IRRawModeCount; ++static unsigned long _ulPrevKeyTime; ++#endif ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++ ++#if(IR_TYPE_SEL == IR_TYPE_RCMM) ++#define MAX_RCBYTE_LEN 4 ++static BOOL StartDecodeFlag = FALSE; ++static u8 RCBitsCnt; ++static u32 tgbits = 0; ++static u8 RCByte[MAX_RCBYTE_LEN]; ++static u8 _u8IrPreRcmmData[MAX_RCBYTE_LEN]; ++static U16 u16CustomerID; ++static BOOL UpDataFlage = FALSE; ++static u8 RCMode; ++static unsigned long _ulPrevKeyTime; ++#endif ++ ++static u32 _u32IRData[IR_SWDECODE_MODE_BUF_LEN]; ++ ++#if (IR_TYPE_SEL == IR_TYPE_MSTAR_DTV) ++static u8 _u8IRHeadReceived=0; ++static u8 _u8IRRepeateDetect=0; ++static u8 _u8IRRepeated=0; ++static u8 _u8IRRepeatedNum=0; ++static u8 _u8IRType=0; ++ ++#elif (IR_TYPE_SEL == IR_TYPE_CUS08_RC5) ++static U16 _u16IrRc5Data=0; // for store shift ir data ++static U16 _u16PreIrRc5Data=0; // for store previous ir data ++static u8 _u8IrRc5Bits=0; // for store bit count ++static u8 _u8IrRc5LastBit=0;//IR_RC5_LAST_BIT; // for store bit var ++static unsigned long _ulPrevKeyTime; ++ ++#elif (IR_TYPE_SEL == IR_TYPE_CUS21SH) ++static u8 _u8IRReceiveDetect = 0; ++static u8 _u8IRRepeateDetect = 0; ++static U16 _u16IRKeyMap = 0; ++static BOOL _bKeyValueHit = FALSE; ++ ++///////// ++u8 g_bIrDetect;//!> 16) & 0x0F); ++ ++ REG(REG_IR_CKDIV_NUM_KEY_DATA) = IR_CKDIV_NUM; // clock divider ++} ++ ++#define MaxQueue 100 ++static struct queue ++{ ++ u32 item[MaxQueue]; ++ int front; ++ int rear; ++} q; ++ ++static DEFINE_SEMAPHORE(queue_lock); ++ ++ ++static void enqueue(u32 data) ++{ ++ if (down_trylock(&queue_lock)) ++ return; ++ ++ if (q.rear == ((q.front + 1) % MaxQueue)) ++ { ++ IR_PRINT("queue is full \n"); ++ } ++ else ++ { ++ q.rear = (q.rear + 1) % MaxQueue; ++ q.item[q.rear] = data; ++ } ++ ++ up(&queue_lock); ++} ++ ++ ++static u32 dequeue(void) ++{ ++ u32 data = 0xFFFF; ++ ++ down(&queue_lock); ++ ++ if (q.front == q.rear) ++ { ++ IR_PRINT("queue is empty \n"); ++ } ++ else ++ { ++ q.front = (q.front + 1) % MaxQueue; ++ data = q.item[q.front]; ++ } ++ ++ up(&queue_lock); ++ return data; ++} ++ ++static unsigned long _MDrv_IR_GetSystemTime(void) ++{ ++ return((unsigned long)((jiffies)*(1000/HZ))); ++ //return 0; ++} ++ ++static void key_dispatch(struct work_struct *work) ++{ ++ static u32 prev_scancode = 0xFFFF; ++ struct MS_IR_DEVICE *ir; ++ ++ printk("[KEY_INPUT]:key_dispatch thread start\n"); ++ //daemonize("ir_key_dispatch"); ++ ++ ir=container_of( work, struct MS_IR_DEVICE, key_dispatch_work); ++ ++ while(1) ++ { ++ int ret; ++ u32 scancode; ++ ++ try_to_freeze(); ++ ++ //IR_PRINT("xxxxx 0\n"); ++ if (prev_scancode == 0xFFFF) ++ { ++ //IR_PRINT("xxxxx 1\n"); ++ ret = wait_for_completion_interruptible(&ir->key_completion); ++ } ++ else ++ { ++ //IR_PRINT("xxxxx 2\n"); ++ // Depend on different IR to wait timeout. ++ // or IR_TYPE_MSTAR_DTV, 150 is better, because ISR need such time to get another ir key. ++ // ++ // NOTE: ++ // Too small, you will find the repeat function in android don't work. (up immediately) ++ // It will become down->up->down->down.....(not continue down) ++ // In input driver(2.6.35), over REP_DELAY(250 msecs) will auto-repeat, and every REP_PERIOD(33 msecs) will send repeat key. ++ // In input driver(3.0.20), over REP_DELAY(500 msecs) will auto-repeat, and every REP_PERIOD(125 msecs) will send repeat key. ++ // In android, over DEFAULT_LONG_PRESS_TIMEOUT(500 mesc) will auto-repeat, and every KEY_REPEAT_DELAY(50 mesc) will send repeat key. ++ ret = wait_for_completion_interruptible_timeout(&ir->key_completion, msecs_to_jiffies(150)); ++ } ++ if (ret < 0) ++ { ++ IR_PRINT("completion interruptible\n"); ++ continue; ++ } ++ ++ scancode = dequeue(); ++ if ((prev_scancode != 0xFFFF) && (scancode == 0xFFFF)) ++ { ++ //IR_PRINT("xxxxx 3\n"); ++ rc_keyup(ir->dev); ++ } ++ else if ((prev_scancode != 0xFFFF) && (scancode != 0xFFFF)) ++ { ++ //IR_PRINT("xxxxx 4\n"); ++ if ((scancode != prev_scancode)) ++ { ++ //IR_PRINT("xxxxx 5\n"); ++ rc_keyup(ir->dev); ++ ++ rc_keydown_notimeout(ir->dev,ir->protocol, scancode, 0); ++ ++ } ++ } ++ else if ((prev_scancode == 0xFFFF) && (scancode != 0xFFFF)) ++ { ++ ++ rc_keydown_notimeout(ir->dev,ir->protocol, scancode, 0); ++ ++ } ++ ++ //IR_PRINT("xxxxx 7, scancode=%d\n", scancode); ++ prev_scancode = scancode; ++ } ++ printk(" key_dispatch thread end\n"); ++ ++ return; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// ISR when receive IR key. ++/// @return None ++//------------------------------------------------------------------------------------------------- ++irqreturn_t _MDrv_IR_ISR(int irq, void *dev_id) ++//irqreturn_t _MDrv_IR_ISR(int irq, void *dev_id, struct pt_regs *regs) ++{ ++ ++ u8 u8Key=0, u8RepeatFlag=0; ++ u8 u8System = 0; ++ BOOL bHaveKey = FALSE; ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++ #if(IR_TYPE_SEL == IR_TYPE_RCMM) ++ U16 u16IrCounter; ++ static unsigned long PreTime; ++ u16IrCounter = ((REG(REG_IR_SHOT_CNT_H_FIFO_STATUS)&0xF) << 16) | ((REG(REG_IR_SHOT_CNT_L))&0xFFFF); ++ if ((_MDrv_IR_GetSystemTime() - PreTime > IR_TIMEOUT_CYC/1000))//reset ++ { ++ RCBitsCnt = 0; ++ _u8PrevKeyCode = 0xff; ++ } ++ //i++; ++ //if(i % 2) ++ // printk("%d:%d\n",i,u16IrCounter); ++ //return IRQ_HANDLED; ++ ++ if(P25_MIN < u16IrCounter && u16IrCounter < P25_MAX) ++ { ++ tgbits = 0x00; ++ RCByte[0] = 0x00; ++ RCByte[1] = 0x00; ++ RCByte[2] = 0x00; ++ RCByte[3] = 0x00; ++ RCBitsCnt = 0; ++ RCMode = 0; ++ ++ StartDecodeFlag = TRUE; ++ //printk("START\n"); ++ //head code start ++ } ++ else if( (P16_MIN < u16IrCounter && u16IrCounter < P16_MAX) && StartDecodeFlag) //! it is 00 bit sequence ++ { ++ tgbits = 0x00; ++ //printk("00\n"); ++ //_u32IrRcmmData <<= 2; ++ //_u32IrRcmmData |= tgbits; ++ RCByte[RCBitsCnt>>3] <<= 2; ++ RCByte[RCBitsCnt>>3] |= tgbits; ++ RCBitsCnt += 2; ++ } ++ else if( (P22_MIN < u16IrCounter && u16IrCounter< P22_MAX) && StartDecodeFlag) //! it is 01 bit sequence ++ { ++ tgbits = 0x01; ++ //printk("01\n"); ++ //_u32IrRcmmData <<= 2; ++ //_u32IrRcmmData |= tgbits; ++ RCByte[RCBitsCnt>>3] <<= 2; ++ RCByte[RCBitsCnt>>3] |= tgbits; ++ RCBitsCnt += 2; ++ } ++ else if( (P28_MIN < u16IrCounter && u16IrCounter < P28_MAX) && StartDecodeFlag) //! it is 10 bit sequence ++ { ++ tgbits = 0x02; ++ //printk("10\n"); ++ //_u32IrRcmmData <<= 2; ++ //_u32IrRcmmData |= tgbits; ++ RCByte[RCBitsCnt>>3] <<= 2; ++ RCByte[RCBitsCnt>>3] |= tgbits; ++ RCBitsCnt += 2; ++ ++ } ++ else if( (P34_MIN < u16IrCounter && u16IrCounter < P34_MAX) && StartDecodeFlag) //! it is 11 bit sequence ++ { ++ tgbits = 0x03; ++ //printk("11\n"); ++ //_u32IrRcmmData <<= 2; ++ //_u32IrRcmmData |= tgbits; ++ RCByte[RCBitsCnt>>3] <<= 2; ++ RCByte[RCBitsCnt>>3] |= tgbits; ++ RCBitsCnt += 2; ++ } ++ else ++ { ++ StartDecodeFlag = FALSE; ++ RCBitsCnt = 0; ++ UpDataFlage = FALSE; ++ tgbits = 0x00; ++ RCByte[0] = 0x00; ++ RCByte[1] = 0x00; ++ RCByte[2] = 0x00; ++ RCByte[3] = 0x00; ++ } ++ ++ if(RCBitsCnt == 24) ++ { ++ if(RCByte[0] & 0x20) ++ { ++ RCMode |= RCMMOEM_LONGID_MODE; ++ ++ tgbits = (RCByte[1]&0x0C) >> 2; ++ RCMode |= 1<>2) == 0x03 ) ++ { ++ RCMode |= RCMMOEM_SHORTID_MODE; ++ ++ tgbits = (RCByte[1]&0x0C) >> 2; ++ RCMode |= 1<= 32) ++ { ++ if( (RCMode & RC_MODE) || (RCMode & JOYSTICK_MODE) ) ++ { ++ StartDecodeFlag = FALSE; ++ UpDataFlage = TRUE; ++ } ++ else ++ { ++ RCBitsCnt = 0; ++ u16CustomerID = 0; ++ RCMode = 0; ++ UpDataFlage = FALSE; ++ tgbits = 0x00; ++ RCByte[0] = 0x00; ++ RCByte[1] = 0x00; ++ RCByte[2] = 0x00; ++ RCByte[3] = 0x00; ++ } ++ } ++ PreTime = _MDrv_IR_GetSystemTime(); ++ ++#elif (IR_TYPE_SEL == IR_TYPE_CUS08_RC5) ++ ++ U16 u16IrCounter,u16N_Shot; ++ ++ u16IrCounter=((REG(REG_IR_SHOT_CNT_H_FIFO_STATUS)&0xF) << 16) | ((REG(REG_IR_SHOT_CNT_L))&0xFFFF); ++ u16N_Shot=(REG(REG_IR_SHOT_CNT_H_FIFO_STATUS))&0x10; ++ ++ if ((u16IrCounter > ONE_BIT_UB) || (u16IrCounter < HALF_BIT_LB)) // if ir counter so big, then reset and return ++ { ++ _u8IrRc5LastBit = TRUE; ++ _u16IrRc5Data = 0; ++ _u8IrRc5Bits = 0; ++ } ++ else ++ { ++ if (u16IrCounter >= HALF_BIT_LB && u16IrCounter <= HALF_BIT_UB) //detect ++ { ++ _u8IrRc5Bits++; ++ if (_u8IrRc5LastBit) ++ { ++ _u8IrRc5LastBit = FALSE; ++ _u16IrRc5Data <<= 1; ++ if (u16N_Shot==0) // Is nshot ++ _u16IrRc5Data |= 1; ++ } ++ else ++ { ++ _u8IrRc5LastBit = TRUE; ++ } ++ } ++ else if (u16IrCounter >= ONE_BIT_LB && u16IrCounter <= ONE_BIT_UB) ++ { ++ if (_u8IrRc5LastBit) ++ { ++ _u16IrRc5Data <<= 1; ++ if (u16N_Shot==0) // Is nshot ++ _u16IrRc5Data |= 1; ++ _u8IrRc5Bits += 2; ++ } ++ else //error stste ++ { ++ _u16IrRc5Data = 0; ++ _u8IrRc5Bits = 0; ++ } ++ } ++ ++ if (_u8IrRc5Bits == IR_RC5_DATA_BITS) ++ { ++ if(u16N_Shot==0) ++ { ++ _u16IrRc5Data <<= 1; ++ _u8IrRc5Bits++; ++ } ++ } ++ } ++ ++ #elif (IR_TYPE_SEL == IR_TYPE_MSTAR_DTV) ++ static unsigned long ulPreTime; ++ u32 tmp; ++ ++ if ((_MDrv_IR_GetSystemTime() - ulPreTime > IR_TIMEOUT_CYC/1000))//||_u8IRRepeated) //timeout or not handler yet ++ { ++ _u32IRCount = 0; ++ _u8IRRepeateDetect=0; ++ _u8IRRepeated=0; ++ _u8IRRepeatedNum=0; ++ _u8IRHeadReceived=0; ++ } ++ if (_u32IRCount (IR_HDC_LOB))//Head received ++ { ++ _u32IRCount=0; ++ _u8IRHeadReceived=1; ++ } ++ /* ++ printk("\n[%d][%d][%d]\n",tmp,IR_OFC_RP_LOB,IR_OFC_RP_UPB); ++ //eg haier repeate: tmp|IR_OFC_RP_LOB|IR_OFC_RP_UPB ++ [92715][1846][2769] ++ [4655][1846][2769] ++ [2047][1846][2769] ++ ++ //eg mstar dtv repeate tmp|IR_OFC_RP_LOB|IR_OFC_RP_UPB ++ [97137][1846][2769] ++ [2581][1846][2769] ++ so mstar dtv has no IR_OFC_UPB code ++ */ ++ if(_u8IRHeadReceived)//begin data received ++ { ++ _u32IRData[_u32IRCount++] = tmp; ++ if(_u8IRRepeateDetect) ++ { ++ if( tmp>(IR_OFC_RP_LOB) && tmp<(IR_OFC_RP_UPB) ) ++ { ++ if(_u32IRCount<4)//for quickly change ir ++ { ++ _u8IRRepeated=1; ++ _u8IRHeadReceived=0; ++ } ++ } ++ } ++ ++ } ++ ++ } ++ ulPreTime = _MDrv_IR_GetSystemTime(); ++ ++#elif (IR_TYPE_SEL == IR_TYPE_CUS21SH) ++ ++ u32 tmp; ++ ++ #if (1) ++ tmp = 0; ++ tmp |= ((REG(REG_IR_SHOT_CNT_H_FIFO_STATUS) & 0xF) << 16); ++ tmp |= (REG(REG_IR_SHOT_CNT_L) & 0xFFFF); ++ ++ ++ if(tmp >= 420L && tmp < 4000L) ++ { ++ if(tmp >=1580L && tmp < 4000L) ++ { ++ _u16IRKeyMap|=(1<<_u32IRCount); ++ } ++ _u32IRCount++; ++ //ReceivingMode=TRUE; ++ RxInProcess=TRUE; ++ //RxTimeOutCount = _MDrv_IR_GetSystemTime(); ++ //ResetKeyoffTimer(); ++ } ++ else if(tmp >= 4000L) ++ { ++ _bExpectedTCome = FALSE; ++ SetToStandbyMode = TRUE; ++ ReceivingMode = TRUE; ++ _u32IRCount=0; ++ _u16IRKeyMap=0; ++ } ++ ++ ++ //if(BufIdx >= 15) ++ //printk("IR: %s:%d %x,%x\n",__FUNCTION__,__LINE__,_u32IRCount,_u16IRKeyMap); ++ #else ++ ++ #endif ++ ++ #else ++ static unsigned long ulPreTime; ++ if (_MDrv_IR_GetSystemTime() - ulPreTime > IR_TIMEOUT_CYC/1000) //timeout ++ { ++ _u32IRCount = 0; ++ } ++ ++ if (_u32IRCount async_queue) ++ kill_fasync(&ms_ir->async_queue, SIGIO, POLL_IN); ++ } ++ ++ IR_PRINT("HaveKey=%d, KEY=%d, RepeatFalg=%d\n", bHaveKey, u8Key, u8RepeatFlag); ++ ++ ++ if (ms_ir && bHaveKey) ++ { ++#ifdef CONFIG_MSTAR_SOFTWARE_IR_MODULE ++ if (software_ir_enable()) ++ { ++ take_over_by_software_ir(u8Key, u8System, u8RepeatFlag, ir->dev, &ir->ir); ++ } ++ else ++ { ++#endif ++ enqueue((u8System << 8) | u8Key); ++ complete(&ms_ir->key_completion); ++#ifdef CONFIG_MSTAR_SOFTWARE_IR_MODULE ++ } ++#endif ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++ ++static int ir_input_init(void) ++{ ++ int err = 0; ++ struct rc_dev *dev; ++ ++ ++ rc_map_register(&ms_rc_map); ++ ++ ++ dev=rc_allocate_device(); ++ if (!dev) ++ { ++ return -ENOMEM; ++ } ++ ++ ms_ir->dev=dev; ++ ms_ir->protocol=RC_TYPE_UNKNOWN; ++ ++ dev->driver_name = "ir"; ++ dev->map_name = MS_IR_MAP_NAME; ++ dev->driver_type = RC_DRIVER_IR_RAW; ++ dev->input_name = MS_IR_INPUT_NAME; ++ dev->input_phys = "/dev/ir"; ++ dev->input_id.bustype = BUS_I2C; ++ dev->input_id.vendor = MS_IR_VENDOR_ID; ++ dev->input_id.product = 0x0001; ++ dev->input_id.version = 1; ++ ++ err = rc_register_device(dev); ++ ++ if (err) ++ { ++ rc_free_device(dev); ++ return err; ++ } ++ ++ clear_bit(EV_REP, dev->input_dev->evbit); ++ ++ ++ init_completion(&ms_ir->key_completion); ++ ++ INIT_WORK(&ms_ir->key_dispatch_work,key_dispatch); ++ key_dispatch_workqueue = create_workqueue("keydispatch_wq"); ++ ++ return 0; ++} ++ ++ ++#if (IR_MODE_SEL == IR_MODE_FULLDECODE_MODE) ++//------------------------------------------------------------------------------------------------- ++/// Get IR key. It is a non-blocking function. ++/// @param pu8Key \b IN: Return IR key value. ++/// @param pu8Flag \b IN: Return IR repeat code. ++/// ++/// @return TRUE: Success ++/// @return FALSE: No key or repeat key is faster than the specified period ++//------------------------------------------------------------------------------------------------- ++static BOOL _MDrv_IR_GetKey(U8 *pu8Key, U8 *pu8System, U8 *pu8Flag) ++{ ++#ifndef CONFIG_MS_IR_INPUT_DEVICE ++ static unsigned long _ulPrevKeyRepeatTime; ++#endif ++ static BOOL _bCheckQuickRepeat; ++ BOOL bRet=FALSE; ++ *pu8System = 0; ++ ++ if(REG(REG_IR_SHOT_CNT_H_FIFO_STATUS) & IR_FIFO_EMPTY) ++ { ++ _bCheckQuickRepeat = 0; ++ return FALSE; ++ } ++ ++ if(((_MDrv_IR_GetSystemTime() - _ulPrevKeyTime) >= IR_TIMEOUT_CYC/1000)) ++ { ++ *pu8Key = REG(REG_IR_CKDIV_NUM_KEY_DATA) >> 8; ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0001; //read ++ ++ mdelay(10); ++ ++ _u8PrevKeyCode = *pu8Key; ++ *pu8Flag = 0; ++ _ulPrevKeyTime = _MDrv_IR_GetSystemTime(); ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_INIT; ++ _bCheckQuickRepeat = 0; ++ _MDrv_IR_ClearFIFO(); ++ return TRUE; ++ } ++ else ++ { ++ if(_bCheckQuickRepeat==0) ++ { ++ _bCheckQuickRepeat = 1; ++ _ulPrevKeyTime = _MDrv_IR_GetSystemTime(); ++ _MDrv_IR_ClearFIFO(); ++ return FALSE; ++ } ++ *pu8Key = REG(REG_IR_CKDIV_NUM_KEY_DATA) >> 8; ++ *pu8Flag = (REG(REG_IR_SHOT_CNT_H_FIFO_STATUS) & IR_RPT_FLAG)? 1 : 0; ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0001; //read ++ bRet = FALSE; ++ _ulPrevKeyTime = _MDrv_IR_GetSystemTime(); ++ if ( (*pu8Flag == 1) && ( *pu8Key == _u8PrevKeyCode )) ++ { ++ bRet = TRUE; ++ ++ } ++ } ++ //printk("*pu8Key=%d",*pu8Key); ++ ++ // Empty the FIFO ++ _MDrv_IR_ClearFIFO(); ++ return bRet; ++ ++} ++ ++ ++#if((IR_MODE_SEL==IR_MODE_RAWDATA_MODE) || (IR_MODE_SEL==IR_MODE_FULLDECODE_MODE)) ++static void _MDrv_IR_ClearFIFO(void) ++{ ++ unsigned long i; ++ ++ // Empty the FIFO ++ for(i=0; i<8; i++) ++ { ++ U8 u8Garbage; ++ ++ if(REG(REG_IR_SHOT_CNT_H_FIFO_STATUS) & IR_FIFO_EMPTY) ++ break; ++ ++ u8Garbage = REG(REG_IR_CKDIV_NUM_KEY_DATA) >> 8; ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0001; //read ++ } ++ ++} ++#endif ++ ++ ++#elif (IR_MODE_SEL == IR_MODE_RAWDATA_MODE) ++//------------------------------------------------------------------------------------------------- ++/// Get IR key. ++/// @param pu8Key \b IN: Return IR key value. ++/// @param pu8Flag \b IN: Return IR repeat code. ++/// ++/// @return TRUE: Success ++/// @return FALSE: Failure ++//------------------------------------------------------------------------------------------------- ++#if 0 ++static unsigned long _ulPrevKeyRepeatTime; ++static BOOL _bCheckQuickRepeat; ++static BOOL msIR_GetRawKey(U8 *pu8key,U8 *pu8flag,BOOL bChkCCode) ++{ ++ U8 u8IRRawModeDone; ++ U8 u8IRRawModeCount; ++ U8 k; ++ ++ u8IRRawModeCount = 0; ++ ++ *pu8key = 0xFF; ++ *pu8flag = (REG(REG_IR_SHOT_CNT_H_FIFO_STATUS) & IR_RPT_FLAG)? 1 : 0; ++ ++ for(k=0;k> 8; ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0001; //read ++ u8IRRawModeCount++; ++ } ++ REG(REG_IR_SEPR_BIT_FIFO_CTRL) |= 0x8000; //IMPORTANT!!! ++ ++ if ( u8IRRawModeCount >= 4 ) ++ u8IRRawModeDone = 1; ++ ++ if (u8IRRawModeDone) ++ { ++ u8IRRawModeDone = 0; ++ if(bChkCCode==TRUE) ++ { ++ if ( (_u8IRRawModeBuf[0] == _u8IRHeaderCode0) && (_u8IRRawModeBuf[1] == _u8IRHeaderCode1) ) ++ { ++ if(_u8IRRawModeBuf[2] == (U8)(~_u8IRRawModeBuf[3])) ++ { ++ *pu8key = _u8IRRawModeBuf[2]; ++ return TRUE; ++ } ++ } ++ } ++ else ++ { ++ *pu8key = _u8IRRawModeBuf[2]; //driectly assign key with index==2 ++ return TRUE; ++ } ++ u8IRRawModeCount = 0; ++ } ++ return FALSE; ++} ++ ++static BOOL _MDrv_IR_GetKey(U8 *pu8Key, U8 *pu8System, U8 *pu8Flag) ++{ ++ unsigned long i; ++ BOOL bRet=FALSE; ++ *pu8System = 0; ++ ++ if(REG(REG_IR_SHOT_CNT_H_FIFO_STATUS) & IR_FIFO_EMPTY) ++ { ++ _bCheckQuickRepeat = 0; ++ return FALSE; ++ } ++ ++ if(((_MDrv_IR_GetSystemTime() - _ulPrevKeyTime) >= IR_TIMEOUT_CYC/1000)) ++ { ++ *pu8Key = REG(REG_IR_CKDIV_NUM_KEY_DATA) >> 8; ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0001; //read ++ #ifdef __arm__ ++ __udelay(1000*10); ++ #else ++ udelay(1000*10); ++ #endif ++ msIR_GetRawKey(pu8Key,pu8Flag,TRUE); ++ _u8PrevKeyCode = *pu8Key; ++ *pu8Flag = 0; ++ _ulPrevKeyTime = _MDrv_IR_GetSystemTime(); ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_INIT; ++ _bCheckQuickRepeat = 0; ++ _MDrv_IR_ClearFIFO(); ++ return TRUE; ++ } ++ else ++ { ++ if(_bCheckQuickRepeat==0) ++ { ++ _bCheckQuickRepeat = 1; ++ _ulPrevKeyTime = _MDrv_IR_GetSystemTime(); ++ _MDrv_IR_ClearFIFO(); ++ return FALSE; ++ } ++ ++ msIR_GetRawKey(pu8Key,pu8Flag,TRUE); ++ bRet = FALSE; ++ _ulPrevKeyTime = _MDrv_IR_GetSystemTime(); ++ if ( (*pu8Flag == 1) && ( *pu8Key == _u8PrevKeyCode )) ++ { ++ i = _MDrv_IR_GetSystemTime(); ++ if( _ePrevKeyProperty == E_IR_KEY_PROPERTY_INIT) ++ { ++ _u8PrevKeyCode = *pu8Key; ++ _ulPrevKeyRepeatTime = i; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_1st; ++ } ++ else if(_ePrevKeyProperty == E_IR_KEY_PROPERTY_1st) ++ { ++ if( (i - _ulPrevKeyRepeatTime) > _u32_1stDelayTimeMs) ++ { ++ _ulPrevKeyRepeatTime = i; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_FOLLOWING; ++ bRet = TRUE; ++ } ++ } ++ else //E_IR_KEY_PROPERTY_FOLLOWING ++ { ++ if( (i - _ulPrevKeyRepeatTime) > _u32_2ndDelayTimeMs) ++ { ++ _ulPrevKeyRepeatTime = i; ++ bRet = TRUE; ++ } ++ } ++ } ++ } ++ ++ // Empty the FIFO ++ _MDrv_IR_ClearFIFO(); ++ return bRet; ++ ++} ++#else ++static BOOL _MDrv_IR_GetKey(U8 *pu8Key, U8 *pu8System, U8 *pu8Flag) ++{ ++ BOOL bRet = FALSE; ++ ++ u32 i, j; ++ *pu8System = 0; ++ ++ for (j=0; j> 8; ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0001; //read ++ ++ for(i=0;i<5;i++); //Delay ++ ++ if(_u8IRRawModeCount == IR_RAW_DATA_NUM) ++ { ++ _u8IRRawModeCount = 0; ++ if( (_u8IRRawModeBuf[0]==_u8IRHeaderCode0) && ++ (_u8IRRawModeBuf[1]==_u8IRHeaderCode1) ) ++ { ++ if(_u8IRRawModeBuf[2] == (U8)(~_u8IRRawModeBuf[3])) ++ { ++ //if (!MDrv_SYS_GetDisplayControllerSeparated()) ++ *pu8Key = _MDrv_IR_ParseKey(_u8IRRawModeBuf[2]); // translate for MIPS ++ ++ //TODO: Implement repeat code later. ++ *pu8Flag = 0; ++ bRet = TRUE; ++ break; ++ } ++ } ++ } ++ } ++ ++ // Empty the FIFO ++ _MDrv_IR_ClearFIFO(); ++ ++ return bRet; ++} ++#endif ++ ++#elif(IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++//------------------------------------------------------------------------------------------------- ++/// Get IR key. ++/// @param pu8Key \b IN: Return IR key value. ++/// @param pu8Flag \b IN: Return IR repeat code. ++/// ++/// @return TRUE: Success ++/// @return FALSE: Failure ++//------------------------------------------------------------------------------------------------- ++static BOOL _MDrv_IR_GetKey(U8 *pu8Key, U8 *pu8System, U8 *pu8Flag) ++{ ++ BOOL bRet = FALSE; ++ ++#if(IR_TYPE_SEL == IR_TYPE_RCMM) ++ unsigned long i; ++#else ++//#if ((IR_TYPE_SEL != IR_TYPE_CUS21SH) && (IR_TYPE_SEL != IR_TYPE_TOSHIBA)) ++ //#if (IR_TYPE_SEL != IR_TYPE_CUS08_RC5) ++ U32 u8Byte, u8Bit; ++ ++ U8 u8IRSwModeBuf[IR_RAW_DATA_NUM]; ++ ++ U32 *pu32IRData = NULL; ++ *pu8System = 0; ++ //#else ++ //unsigned long i; ++ //#endif ++//#endif ++#endif ++ ++#if(IR_TYPE_SEL == IR_TYPE_RCMM) ++ ++ if(UpDataFlage) ++ { ++ //printk("GetKey\n"); ++ UpDataFlage = FALSE; ++ ++ switch(RCMode) ++ { ++ case RCMMOEM_LONGID_MODE|RC_MODE: ++ { ++ if((_u8IrPreRcmmData[0] == RCByte[0]) && (_u8IrPreRcmmData[1] == RCByte[1]) && (_u8IrPreRcmmData[2] == RCByte[2]) && (_u8IrPreRcmmData[3] == RCByte[3])) ++ { ++ *pu8Flag = TRUE; ++ } ++ ++ u16CustomerID = ((RCByte[0] & 0x1F) << 4) | ((RCByte[1] & 0xF0) >> 4); ++ ++ if(u16CustomerID == 0x007D) ++ { ++ *pu8Key = RCByte[3]; ++ if(*pu8Key>=30 && *pu8Key<=132) ++ *pu8Key = RCByte[3]+111; ++ //printk("0x%x:,%d\n",*pu8Key,*pu8Key); ++ *pu8System = (RCByte[2] & 0x7F); ++ ++ _u8IrPreRcmmData[0] = RCByte[0]; ++ _u8IrPreRcmmData[1] = RCByte[1]; ++ _u8IrPreRcmmData[2] = RCByte[2]; ++ _u8IrPreRcmmData[3] = RCByte[3]; ++ ++ RCByte[0] = 0x0000; ++ RCByte[1] = 0x0000; ++ RCByte[2] = 0x0000; ++ RCByte[3] = 0x0000; ++ ++ RCMode = 0; ++ RCBitsCnt = 0; ++ bRet = TRUE; ++ } ++ ++ break; ++ } ++ case RCMMOEM_LONGID_MODE|KEYBOARD_MODE: ++ { ++ if((_u8IrPreRcmmData[0] == RCByte[0]) && (_u8IrPreRcmmData[1] == RCByte[1]) && (_u8IrPreRcmmData[2] == RCByte[2])) ++ { ++ *pu8Flag = TRUE; ++ } ++ ++ u16CustomerID = ((RCByte[0] & 0x1F) << 4) | ((RCByte[1] & 0xF0) >> 4); ++ if(u16CustomerID == 0x007D) ++ { ++ if(_u8PrevKeyCode==61) ++ { ++ *pu8Key = (RCByte[2] & 0x7F) + 0x3D; ++ if(*pu8Key>=97&&*pu8Key<=99) ++ *pu8Key += 150; ++ } ++ else ++ { ++ *pu8Key = RCByte[2] & 0x7F; ++ } ++ //printk("0x%x:,%d\n",*pu8Key,*pu8Key); ++ _u8IrPreRcmmData[0] = RCByte[0]; ++ _u8IrPreRcmmData[1] = RCByte[1]; ++ _u8IrPreRcmmData[2] = RCByte[2]; ++ ++ RCByte[0] = 0x0000; ++ RCByte[1] = 0x0000; ++ RCByte[2] = 0x0000; ++ RCByte[3] = 0x0000; ++ ++ RCBitsCnt = 0; ++ bRet = TRUE; ++ } ++ ++ ++ break; ++ } ++ ++ case RCMMOEM_LONGID_MODE|MOUSE_MODE: ++ break; ++ case RCMMOEM_LONGID_MODE|JOYSTICK_MODE: ++ break; ++ default: ++ bRet = FALSE; ++ break; ++ } ++ ++ } ++ ++ if(bRet) ++ { ++ //printk("_u8PrevKeyCode=%d,*pu8Key=%d,_ePrevKeyProperty=%d",_u8PrevKeyCode,*pu8Key,_ePrevKeyProperty); ++ if (_u8PrevKeyCode != *pu8Key) ++ { ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_INIT; ++ } ++ if ((_u8PrevKeyCode == (*pu8Key + 61))||(_u8PrevKeyCode == (*pu8Key + 211))) ++ { ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_1st; ++ } ++ ++ i = _MDrv_IR_GetSystemTime(); ++ if( _ePrevKeyProperty == E_IR_KEY_PROPERTY_INIT) ++ { ++ _u8PrevKeyCode = *pu8Key; ++ _ulPrevKeyTime = i; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_1st; ++ } ++ else if(_ePrevKeyProperty == E_IR_KEY_PROPERTY_1st) ++ { ++ //printk("i=%ld,_ulPrevKeyTime=%ld",i,_ulPrevKeyTime); ++ if( (i - _ulPrevKeyTime) > 150) ++ { ++ _ulPrevKeyTime = i; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_FOLLOWING; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ else //E_IR_KEY_PROPERTY_FOLLOWING ++ { ++ if( (i - _ulPrevKeyTime) > 150) ++ { ++ _ulPrevKeyTime = i; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ } ++ ++ return bRet; ++ ++#elif (IR_TYPE_SEL == IR_TYPE_CUS08_RC5) ++ ++ if(_u8IrRc5Bits > IR_RC5_DATA_BITS) ++ { ++ if ((_u16IrRc5Data&0xF000)==0x3000) ++ { ++ if(_u16PreIrRc5Data==_u16IrRc5Data) ++ *pu8Flag = TRUE; ++ ++ *pu8Key = _u16IrRc5Data&0x3F; ++ *pu8System = (_u16IrRc5Data&0x3C0)>>6; ++ _u16PreIrRc5Data=_u16IrRc5Data; ++ _u8IrRc5Bits=0; ++ bRet = TRUE; ++ } ++ } ++ ++ if(bRet) ++ { ++ if ( (_u8PrevKeyCode != *pu8Key) || (!*pu8Flag) ) ++ { ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_INIT; ++ } ++ ++ i = _MDrv_IR_GetSystemTime(); ++ if( _ePrevKeyProperty == E_IR_KEY_PROPERTY_INIT) ++ { ++ _u8PrevKeyCode = *pu8Key; ++ _ulPrevKeyTime = i; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_1st; ++ } ++ else if(_ePrevKeyProperty == E_IR_KEY_PROPERTY_1st) ++ { ++ if( (i - _ulPrevKeyTime) > _u32_1stDelayTimeMs) ++ { ++ _ulPrevKeyTime = i; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_FOLLOWING; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ else //E_IR_KEY_PROPERTY_FOLLOWING ++ { ++ if( (i - _ulPrevKeyTime) > _u32_2ndDelayTimeMs) ++ { ++ _ulPrevKeyTime = i; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ } ++ ++ return bRet; ++ ++#elif (IR_TYPE_SEL == IR_TYPE_CUS21SH) ++ ++ #if (1) ++ bRet = FALSE; ++ ++ if(_u32IRCount == 15) ++ { ++ if(_MDrv_SH_IR_GetKey(pu8Key, pu8System, pu8Flag)) ++ { ++ bRet = TRUE; ++ } ++ _u32IRCount = 0; ++ _u16IRKeyMap = 0; ++ } ++ #else ++ //printk("Linux: %s:%s:%d \n",__FILE__,__FUNCTION__,__LINE__); ++ bRet = FALSE; ++ ++ for( u8Byte=0; u8Byte<16/*IR_RAW_DATA_NUM*/; u8Byte++) ++ { ++ u8IRSwModeBuf[u8Byte] = 0; ++ } ++ ++ if (_u32IRCount< 32)//3+IR_RAW_DATA_NUM*8) ++ return FALSE; //not complete yet ++ ++ DEBUG_IR(printk("_u32IRCount=%d", _u32IRCount)); ++ for( u8Byte=0; u8Byte<_u32IRCount; u8Byte++) ++ { ++ DEBUG_IR(printk(" 0x%x", _u32IRData[u8Byte])); ++ } ++ printk("\n"); ++ printk("_u16IRKeyMap:0x%x \n",_u16IRKeyMap); ++ ++ if(_bKeyValueHit == FALSE) ++ { ++ *pu8Key = _MDrv_IR_CUS21SH_ParseKey(_u16IRKeyMap); // translate for SH ++ ++ printk("_u16IRKeyMap:0x%x ==> *pu8Key:%x\n",_u16IRKeyMap,*pu8Key); ++ //TODO: Implement repeat code later. ++ *pu8Flag = 0; ++ //_bKeyValueHit = 1; ++ bRet = TRUE; ++ } ++ #endif ++ ++ return bRet; ++ ++#else ++ for( u8Byte=0; u8Byte IR_HDC_LOB && _u32IRData[1] > IR_OFC_LOB+IR_LG01H_LOB && _u32IRData[1] < REG_IR_OFC_UPB+IR_LG01H_UPB ) ++ { ++ pu32IRData = &_u32IRData[2]; ++ DEBUG_IR(printk(" H1 ")); ++ } ++ else if( _u32IRData[1] > IR_HDC_LOB && _u32IRData[2] > IR_OFC_LOB+IR_LG01H_LOB && _u32IRData[2] < REG_IR_OFC_UPB+IR_LG01H_UPB ) ++ { ++ pu32IRData = &_u32IRData[3]; ++ DEBUG_IR(printk(" H2 ")); ++ } ++ else ++ { ++ DEBUG_IR(printk(" invalid leader code\n")); ++ bRet = FALSE; ++ goto done; ++ } ++ ++ for( u8Byte=0; u8Byte>= 1; ++ ++ if( u32BitLen > IR_LG0_LOB && u32BitLen < IR_LG0_UPB ) //0 ++ { ++ u8IRSwModeBuf[u8Byte] |= 0x00; ++ } ++ else if (u32BitLen > IR_LG1_LOB && u32BitLen < IR_LG1_UPB) //1 ++ { ++ u8IRSwModeBuf[u8Byte] |= 0x80; ++ } ++ else ++ { ++ DEBUG_IR(printk(" invalid waveform,0x%x\n",u32BitLen)); ++ bRet = FALSE; ++ goto done; ++ } ++ } ++ } ++ ++ if(u8IRSwModeBuf[0] == _u8IRHeaderCode0) ++ { ++ if(u8IRSwModeBuf[1] == _u8IRHeaderCode1) ++ { ++ if(u8IRSwModeBuf[2] == (u8)~u8IRSwModeBuf[3]) ++ { ++ *pu8Key = u8IRSwModeBuf[2]; ++ *pu8Flag = 0; ++ bRet = TRUE; ++ #if (IR_TYPE_SEL == IR_TYPE_MSTAR_DTV) ++ _u8PrevKeyCode = *pu8Key; ++ _u8PrevSystemCode = *pu8System; ++ _u8IRRepeateDetect = 1; ++ _u8IRHeadReceived = 0; ++ _u8IRType = 0; ++ #endif ++ ++ goto done; ++ } ++ } ++ } ++ if(u8IRSwModeBuf[0] == _u8IR2HeaderCode0) ++ { ++ if(u8IRSwModeBuf[1] == _u8IR2HeaderCode1) ++ { ++ if(u8IRSwModeBuf[2] == (u8)~u8IRSwModeBuf[3]) ++ { ++ *pu8Key = u8IRSwModeBuf[2]; ++ *pu8Flag = 0; ++ bRet = TRUE; ++ #if (IR_TYPE_SEL == IR_TYPE_MSTAR_DTV) ++ _u8PrevKeyCode = *pu8Key; ++ _u8PrevSystemCode = *pu8System; ++ _u8IRRepeateDetect = 1; ++ _u8IRHeadReceived = 0; ++ _u8IRType = 0; ++ #endif ++ ++ goto done; ++ } ++ } ++ } ++ DEBUG_IR(printk(" invalid data\n")); ++ bRet = FALSE; ++ ++done: ++ _u32IRCount = 0; ++ return bRet; ++#endif ++} ++#endif ++ ++static int ms_ir_init(int bResumeInit) ++{ ++ ++ int result; ++ ir_irq_depth = 1; ++ _u8PrevSystemCode = 0; ++ ++ ++#if (IR_MODE_SEL == IR_MODE_RAWDATA_MODE) ++ _u8IRRawModeCount = 0; ++#endif ++ ++ printk("[ms_ir_init]%d\n",__LINE__); ++ ++#if (IR_MODE_SEL == IR_MODE_SWDECODE_MODE) ++#if(IR_TYPE_SEL != IR_TYPE_RCMM) ++ _u32IRCount = 0; ++#endif ++ ++#endif ++ ++ ++#if (IR_MODE_SEL == IR_MODE_RAWDATA_MODE) ++ { ++ REG(REG_IR_CTRL) = IR_TIMEOUT_CHK_EN | ++ IR_INV | ++ IR_LG01H_CHK_EN | ++ IR_LDCCHK_EN | ++ IR_EN; ++ } ++#else ++ { ++ REG(REG_IR_CTRL) = IR_TIMEOUT_CHK_EN | ++ IR_INV | ++ IR_RPCODE_EN | ++ IR_LG01H_CHK_EN | ++ IR_DCODE_PCHK_EN | ++ IR_CCODE_CHK_EN | ++ IR_LDCCHK_EN | ++ IR_EN; ++ } ++#endif ++ ++ _MDrv_IR_Timing(); ++ REG(REG_IR_CCODE) = ((u16)_u8IRHeaderCode1<<8) | _u8IRHeaderCode0; ++ REG(REG_IR_SEPR_BIT_FIFO_CTRL) = 0xF00; ++ REG(REG_IR_GLHRM_NUM) = 0x804; ++#if (IR_MODE_SEL==IR_MODE_FULLDECODE_MODE) ++ REG(REG_IR_GLHRM_NUM) |= (0x3 <<12); ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0020; //wakeup key sel ++#elif (IR_MODE_SEL==IR_MODE_RAWDATA_MODE) ++ REG(REG_IR_GLHRM_NUM) |= (0x2 <<12); ++ REG(REG_IR_FIFO_RD_PULSE) |= 0x0020; //wakeup key sel ++#else ++ REG(REG_IR_GLHRM_NUM) |= (0x1 <<12); ++#if(IR_TYPE_SEL == IR_TYPE_RCMM) ++ ++ REG(REG_IR_SEPR_BIT_FIFO_CTRL) |= 0x1 <<12; ++ ++#else ++ #ifdef IR_INT_NP_EDGE_TRIG //for N/P edge trigger ++ REG(REG_IR_SEPR_BIT_FIFO_CTRL) |= 0x3 <<12; ++ #else ++ REG(REG_IR_SEPR_BIT_FIFO_CTRL) |= 0x2 <<12; ++ #endif ++#endif ++#endif ++ ++ ++#if((IR_MODE_SEL==IR_MODE_RAWDATA_MODE) || (IR_MODE_SEL==IR_MODE_FULLDECODE_MODE)) ++ // Empty the FIFO ++ _MDrv_IR_ClearFIFO(); ++#endif ++ ++ _u32_1stDelayTimeMs = 0; ++ _u32_2ndDelayTimeMs = 0; ++ _ePrevKeyProperty = E_IR_KEY_PROPERTY_INIT; ++ memset(&_KeyReceived, 0 , sizeof(_KeyReceived) ); ++ if(!bResumeInit) ++ { ++#ifdef CONFIG_MSTAR_PM_SWIR ++ //result = request_irq(E_FIQ_IR, MDrv_SWIR_PM51_ISR, SA_INTERRUPT, "IR", NULL); //Doyle change ISR ++#else ++ result = request_irq(ms_ir->irq_in, _MDrv_IR_ISR, IRQF_SHARED, "IR", ms_ir); ++#endif ++ ir_irq_depth = 0; ++ if (result) ++ { ++ printk(KERN_ERR"IR IRQ registration ERROR!!\n"); ++ ++ return -1; ++ } ++ ++ } ++ ++ Chip_Function_Set(CHIP_FUNC_IR_ENABLE,0); ++ ++ ++ irq_get_chip(ms_ir->irq_in)->irq_unmask(irq_get_irq_data(ms_ir->irq_in)); ++ ++ ++ ++ ++#ifdef CONFIG_MSTAR_PM_SWIR ++ MBX_Result MbxResult=E_MBX_UNKNOW_ERROR; ++ ++ extern int MDrv_MBX_NotifyMsgRecCbFunc(void *); ++ ++ if( E_MBX_SUCCESS != MDrv_MBX_Init(SWIR_FILEOPS, E_MBX_CPU_MIPS, E_MBX_ROLE_HK, IR_MBX_TIMEOUT)) ++ { ++ swir_pm_status = -1; ++ } ++ else ++ { ++ MDrv_MBX_Enable(SWIR_FILEOPS, TRUE); ++ swir_pm_status = 1; ++ ++ MbxResult = MDrv_MBX_RegisterMSG(SWIR_FILEOPS, E_MBX_CLASS_IRKEY_NOWAIT, IR_MBX_QUEUESIZE); ++ ++ MDrv_MBX_NotifyMsgRecCbFunc(MDrv_PMSWIR_ReceiveMsg); ++ ++ ++ ++ //send msg to PM to unlock interrupt mask ++ MBX_Msg MB_Command; ++ MS_U8 password[] = {'M', 'S', 'T', 'A', 'R'}; ++ int i; ++ ++ memset((void*)&MB_Command, 0, sizeof(MBX_Msg)); ++ MB_Command.eRoleID = E_MBX_ROLE_PM; ++ MB_Command.eMsgType = E_MBX_MSG_TYPE_INSTANT; ++ MB_Command.u8Ctrl = 0; ++ MB_Command.u8MsgClass = E_MBX_CLASS_IRKEY_NOWAIT; ++ MB_Command.u8Index = E_IR_CPUTo51_CMD_SWIR_INT; ++ MB_Command.u8ParameterCount = sizeof(password); ++ for(i = 0; i < sizeof(password); i++) ++ MB_Command.u8Parameters[i] = password[i]; ++ MbxResult = MDrv_MBX_SendMsg(SWIR_FILEOPS, &MB_Command); ++ } ++#endif ++ ++ printk("[MDrv_IR_Init]%d\n",__LINE__); ++ ++ ++ return 0; ++} ++ ++static int ms_ir_probe(struct platform_device *pdev) ++{ ++ ++ int retval=-1; ++ int irq;// = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ int irq_rc;// = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ struct resource *mem; ++ ++ ms_ir = devm_kzalloc(&pdev->dev, sizeof(*ms_ir), GFP_KERNEL); ++ if (!ms_ir) ++ { ++ retval=-ENOMEM; ++ goto DONE; ++ } ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ irq_rc = irq_of_parse_and_map(pdev->dev.of_node, 1); ++ ++ if (!irq) ++ { ++ printk(KERN_ERR"IR irq error!!"); ++ return -1; ++ } ++ ++ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ ms_ir->membase = (void *)(IO_ADDRESS(mem->start)); ++ ++ ms_ir->irq_in=irq; ++ ms_ir->irq_rc=irq_rc; ++ ++ platform_set_drvdata(pdev, &ms_ir); ++ ++ if((retval=ir_input_init())<0) goto DONE; ++ if((retval=ms_ir_init(0))<0) goto DONE; ++ ms_ir->IRFlag |= (IRFLAG_IRENABLE|IRFLAG_HWINITED); ++ ++DONE: ++ ++ printk(KERN_INFO"IR init done!! retval=%d\n",retval); ++ ++ return retval; ++} ++ ++ ++static int ms_ir_remove(struct platform_device *pdev) ++{ ++ ++ struct MS_IR_DEVICE *ir=platform_get_drvdata(pdev); ++ ++ destroy_workqueue(key_dispatch_workqueue); ++ rc_unregister_device(ir->dev); ++ rc_free_device(ir->dev); ++ return 0; ++} ++ ++void MDrv_IR_EnableIR(U8 bEnable) ++{ ++ //irqreturn_t isrStatus; ++ bIRPass = !bEnable; ++ if (bEnable) ++ { ++ //isrStatus = request_irq(E_FIQ_IR, _MDrv_IR_ISR, SA_INTERRUPT, "IR", NULL); ++ if(ir_irq_depth > 0){ ++ ++ irq_get_chip(ms_ir->irq_in)->irq_unmask(irq_get_irq_data(ms_ir->irq_in)); ++ ir_irq_depth--; ++ } ++ } ++ else ++ { ++ ++ ++ irq_get_chip(ms_ir->irq_in)->irq_mask(irq_get_irq_data(ms_ir->irq_in)); ++ ir_irq_depth++; ++ //free_irq(E_FIQ_IR, NULL); ++ } ++} ++ ++ ++static int ms_ir_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct MS_IR_DEVICE *ir=platform_get_drvdata(pdev); ++ if(ir && (ir->IRFlag&IRFLAG_HWINITED)) ++ { ++ if(ir->IRFlag & IRFLAG_IRENABLE) ++ { ++ MDrv_IR_EnableIR(0); ++ } ++ } ++ return 0; ++} ++ ++static int ms_ir_resume(struct platform_device *pdev) ++{ ++ struct MS_IR_DEVICE *ir=platform_get_drvdata(pdev); ++ if(ir && (ir->IRFlag&IRFLAG_HWINITED)) ++ { ++ ms_ir_init(1); ++ if(ir->IRFlag & IRFLAG_IRENABLE) ++ { ++ MDrv_IR_EnableIR(1); ++ } ++ } ++ return 0; ++} ++ ++ ++ ++static int __init ms_ir_module_init(void) ++{ ++ int retval=0; ++ retval = platform_driver_register(&ms_ir_driver); ++ ++ return retval; ++} ++ ++static void __exit ms_ir_module_exit(void) ++{ ++ platform_driver_unregister(&ms_ir_driver); ++} ++ ++ ++module_init(ms_ir_module_init); ++module_exit(ms_ir_module_exit); ++ ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("IR driver"); ++MODULE_LICENSE("GPL"); ++ ++ ++ +diff --git a/drivers/mstar/ir/ms_ir.h b/drivers/mstar/ir/ms_ir.h +new file mode 100644 +index 00000000..c86e2e4b +--- /dev/null ++++ b/drivers/mstar/ir/ms_ir.h +@@ -0,0 +1,427 @@ ++/* ++ * ms_ir.h ++ * ++ * Created on: 2015å¹´7月1æ—¥ ++ * Author: Administrator ++ */ ++ ++#ifndef _MS_IR_H_ ++#define _MS_IR_H_ ++#include "ms_types.h" ++ ++#define IR_TYPE_OLD 0 ++#define IR_TYPE_NEW 1 ++#define IR_TYPE_MSTAR_DTV 2 ++#define IR_TYPE_MSTAR_RAW 3 ++#define IR_TYPE_RC_V16 4 ++#define IR_TYPE_CUS03_DTV 5 ++#define IR_TYPE_MSTAR_FANTASY 6 ++#define IR_TYPE_MSTAR_SZ1 7 ++#define IR_TYPE_CUS08_RC5 8 ++#define IR_TYPE_CUS21SH 9 ++#define IR_TYPE_RCMM 10 ++ ++ ++#define IR_MODE_FULLDECODE_MODE 1 ++#define IR_MODE_RAWDATA_MODE 2 ++#define IR_MODE_SWDECODE_MODE 3 ++#define IR_MODE_SWDECODE_KON_MODE 4 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++#define IR_MAX_BUF_DPH 2 ++#define IR_MAX_BUF_LEN 256 ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//#if 0 ++//typedef enum ++//{ ++// KEYCODE_TV_RADIO, ++// KEYCODE_CHANNEL_LIST, ++// KEYCODE_CHANNEL_FAV_LIST, ++// KEYCODE_CHANNEL_RETURN, ++// KEYCODE_CHANNEL_PLUS, ++// KEYCODE_CHANNEL_MINUS, ++// ++// KEYCODE_AUDIO, ++// KEYCODE_VOLUME_PLUS, ++// KEYCODE_VOLUME_MINUS, ++// ++// KEYCODE_UP, ++// KEYCODE_POWER, ++// KEYCODE_EXIT, ++// KEYCODE_MENU, ++// KEYCODE_DOWN, ++// KEYCODE_LEFT, ++// KEYCODE_SELECT, ++// KEYCODE_RIGHT, ++// ++// KEYCODE_NUMERIC_0, ++// KEYCODE_NUMERIC_1, ++// KEYCODE_NUMERIC_2, ++// KEYCODE_NUMERIC_3, ++// KEYCODE_NUMERIC_4, ++// KEYCODE_NUMERIC_5, ++// KEYCODE_NUMERIC_6, ++// KEYCODE_NUMERIC_7, ++// KEYCODE_NUMERIC_8, ++// KEYCODE_NUMERIC_9, ++// ++// KEYCODE_MUTE, ++// KEYCODE_PAGE_UP, ++// KEYCODE_PAGE_DOWN, ++// KEYCODE_CLOCK, ++// ++// KEYCODE_INFO, ++// KEYCODE_RED, ++// KEYCODE_GREEN, ++// KEYCODE_YELLOW, ++// KEYCODE_BLUE, ++// KEYCODE_MTS, ++// KEYCODE_NINE_LATTICE, ++// KEYCODE_TTX, ++// KEYCODE_CC, ++// KEYCODE_INPUT_SOURCE, ++// KEYCODE_CRADRD, ++//// KEYCODE_PICTURE, ++// KEYCODE_ZOOM, ++// KEYCODE_DASH, ++// KEYCODE_SLEEP, ++// KEYCODE_EPG, ++// KEYCODE_PIP, ++// ++// KEYCODE_MIX, ++// KEYCODE_INDEX, ++// KEYCODE_HOLD, ++// KEYCODE_PREVIOUS, ++// KEYCODE_NEXT, ++// KEYCODE_BACKWARD, ++// KEYCODE_FORWARD, ++// KEYCODE_PLAY, ++// KEYCODE_RECORD, ++// KEYCODE_STOP, ++// KEYCODE_PAUSE, ++// ++// KEYCODE_SIZE, ++// KEYCODE_REVEAL, ++// KEYCODE_SUBCODE, ++// ++// KEYCODE_DUMMY, ++// KEYCODE_NUM, ++//} EN_KEY; ++//#else ++//// This is copyed from Chakra. To make sure the key code is same in Linux & Chakra for OBAMA. ++//typedef enum ++//{ ++// KEYCODE_CHANNEL_FAV_LIST = 0x00, //IR_KEY_FAV ++// KEYCODE_CHANNEL_RETURN = 0x01, //IR_KEY_FLASHBK ++// KEYCODE_CHANNEL_PLUS = 0x02, //IR_KEY_CH_UP ++// KEYCODE_CHANNEL_MINUS = 0x03, //IR_KEY_CH_DOWN ++// ++// KEYCODE_AUDIO = 0x04, //IR_KEY_SOUND ++// KEYCODE_VOLUME_PLUS = 0x05, //IR_KEY_VOL_UP ++// KEYCODE_VOLUME_MINUS = 0x06, //IR_KEY_VOL_DOWN ++// ++// KEYCODE_UP = 0x07, //IR_KEY_UP_ARROW ++// KEYCODE_POWER = 0x08, //IR_KEY_POWER ++// KEYCODE_EXIT = 0x09, //IR_KEY_EXIT ++// KEYCODE_MENU = 0x0A, //IR_KEY_MENU ++// KEYCODE_DOWN = 0x0B, //IR_KEY_DOWN_ARROW ++// KEYCODE_LEFT = 0x0C, //IR_KEY_LEFT_ARROW ++// KEYCODE_SELECT = 0x0D, //IR_KEY_ENTER ++// KEYCODE_BACK = 0x0E, //IR_KEY_BACK ++// KEYCODE_RIGHT = 0x0F, //IR_KEY_RIGHT_ARROW ++// ++// KEYCODE_NUMERIC_0 = 0x10, //IR_KEY_0 ++// KEYCODE_NUMERIC_1 = 0x11, //IR_KEY_1 ++// KEYCODE_NUMERIC_2 = 0x12, //IR_KEY_2 ++// KEYCODE_NUMERIC_3 = 0x13, //IR_KEY_3 ++// KEYCODE_NUMERIC_4 = 0x14, //IR_KEY_4 ++// KEYCODE_NUMERIC_5 = 0x15, //IR_KEY_5 ++// KEYCODE_NUMERIC_6 = 0x16, //IR_KEY_6 ++// KEYCODE_NUMERIC_7 = 0x17, //IR_KEY_7 ++// KEYCODE_NUMERIC_8 = 0x18, //IR_KEY_8 ++// KEYCODE_NUMERIC_9 = 0x19, //IR_KEY_9 ++// ++// KEYCODE_MUTE = 0x1A, //IR_KEY_MUTE ++// ++// KEYCODE_INFO = 0x1B, //IR_KEY_INFO ++// KEYCODE_RED = 0x1C, //IR_KEY_RED ++// KEYCODE_GREEN = 0x1D, //IR_KEY_GREEN ++// KEYCODE_MTS = 0x1E, //IR_KEY_SAP ++// KEYCODE_SUBTITLE = 0x1F, ++// ++// KEYCODE_INPUT_SOURCE = 0x20, //IR_KEY_INPUT ++// KEYCODE_PICTURE = 0x21, //IR_KEY_PICTURE ++// ++// KEYCODE_SOUND = 0x22, ++// ++// KEYCODE_ZOOM = 0x23, //IR_KEY_RATIO ++// KEYCODE_DASH = 0x24, //IR_KEY_DASH ++// KEYCODE_SLEEP = 0x25, //IR_KEY_TIMER ++// KEYCODE_EPG = 0x26, ++// ++// KEYCODE_HOLD = 0x27, //IR_KEY_HOLD ++// ++// KEYCODE_ADJUST = 0x28, //IR_KEY_ADJST ++// KEYCODE_TV_INPUT = 0x29, ++// ++// KEYCODE_P_CHECK = 0x2C, ++// KEYCODE_S_CHECK = 0x2D, ++// KEYCODE_POWERONLY = 0x2E, ++// KEYCODE_BRIGHTNESS_PLUS = 0x31, ++// KEYCODE_BRIGHTNESS_MINUS = 0x32, ++// ++// // TTX keys ++// KEYCODE_YELLOW = 0x33, ++// KEYCODE_BLUE = 0x34, ++// KEYCODE_TTX = 0x35, ++// KEYCODE_SIZE = 0x36, ++// KEYCODE_MIX = 0x37, ++// KEYCODE_INDEX = 0x38, ++// KEYCODE_TV_RADIO = 0x39, ++// KEYCODE_REVEAL = 0x3A, ++// KEYCODE_CHANNEL_LIST = 0x3B, ++// KEYCODE_TIME = 0x3C, // prevent to display TIME window when press TIME key ( no teletext channel ) ++// KEYCODE_CLOCK = 0x3D, ++// KEYCODE_TTX_MODE = 0x3E, ++// KEYCODE_UPDATE = 0x3F, // add UPDATE key ++// ++// DSC_KEY_PWRON = 0x40, ++// DSC_KEY_PWROFF = 0x41, ++// DSC_KEY_ARC4X3 = 0x42, ++// DSC_KEY_ARC16X9 = 0x43, ++// DSC_KEY_ARCZOOM = 0x44, ++// DSC_KEY_TV = 0x45, ++// DSC_KEY_VIDEO1 = 0x46, ++// DSC_KEY_VIDEO2 = 0x47, ++// DSC_KEY_VIDEO3 = 0x48, ++// DSC_KEY_COMP1 = 0x49, ++// DSC_KEY_COMP2 = 0x4A, ++// DSC_KEY_RGBPC = 0x4B, ++// DSC_KEY_RGBDTV = 0x4C, ++// DSC_KEY_RGBDVI = 0x4D, ++// DSC_KEY_HDMI1 = 0x4E, ++// DSC_KEY_HDMI2 = 0x4F, ++// DSC_KEY_MULTI_PIP = 0x50, ++// DSC_KEY_MULTIMEDIA = 0x51, ++// DSC_KEY_DVIPC = 0x52, ++// ++// KEYCODE_MMI = 0x5C, ++// KEYCODE_MMI_ENTER_MENU = 0x5D, ++// ++// KEYCODE_UARTDEBUGPORT = 0x5E, ++// ++// KEYCODE_PAUSE = 0x60, ++// KEYCODE_PLAY = 0x61, ++// KEYCODE_RECORD = 0x62, ++// KEYCODE_STOP = 0x63, ++// KEYCODE_SUBCODE = 0x69, ++// KEYCODE_DA = 0x6A, ++// KEYCODE_SUBPAGE = 0x6B, ++// KEYCODE_DVD = 0x6C, ++// ++// KEYCODE_DTV = 0x82, ++// KEYCODE_TV = 0x83, ++// KEYCODE_SCART = 0x84, ++// KEYCODE_COMPONENT = 0x85, ++// KEYCODE_PC = 0x86, ++// KEYCODE_HDMI = 0x87, ++// KEYCODE_AV = 0x88, ++// KEYCODE_SV = 0x89, ++// KEYCODE_FREEZE = 0x8A, //IR_KEY_FREEZE ++// KEYCODE_FORWARD = 0x8B, ++// KEYCODE_BACKWARD = 0x8C, ++// KEYCODE_NEXT = 0x8D, ++// KEYCODE_PREVIOUS = 0x8E, ++// KEYCODE_PAGE_UP = 0x8F, ++// KEYCODE_PAGE_DOWN = 0x90, ++// KEYCODE_CC = 0x91, ++// KEYCODE_VOLUME = 0x92, ++// KEYCODE_PIP = 0x93, ++// KEYCODE_CRADRD = 0x94, ++// KEYCODE_NINE_LATTICE = 0x95, ++// ++// KEYCODE_DUMMY = 0xFF, ++// KEYCODE_NULL = 0xFF ++//} EN_KEY; ++//#endif ++ ++typedef enum ++{ ++ EN_SHOT_P = 0x01, /// 2'b01: only pshot edge detect for counter ++ EN_SHOT_N = 0x02, /// 2'b10: only nshot edge detect for counter ++ EN_SHOT_PN = 0x03, /// 2'b11/2'b00: both pshot/nshot edge detect for counter ++ EN_SHOT_INVLD, /// Invalid for value greater than 2'b11 ++ ++} EN_SHOT_SEL; ++ ++typedef enum ++{ ++ E_IR_PROTOCOL_NONE=0, ++ E_IR_PROTOCOL_NEC, ++ E_IR_PROTOCOL_RC5, ++ E_IR_PROTOCOL_PZ_OCN, ++ E_IR_PROTOCOL_MAX, ++} IR_PROCOCOL_TYPE; ++ ++typedef struct ++{ ++ U32 u32_1stDelayTimeMs; ++ U32 u32_2ndDelayTimeMs; ++ U8 data3; ++} MS_IR_DelayTime, *PMS_IR_DelayTime; ++ ++typedef struct ++{ ++ U8 u8Key; ++ U8 u8System; ++ U8 u8Flag; ++ U8 u8Valid; ++} MS_IR_KeyInfo, *PMS_IR_KeyInfo; ++ ++typedef struct ++{ ++ unsigned long time; ++} MS_IR_LastKeyTime, *PMS_IR_LastKeyTime; ++ ++typedef struct ++{ ++ U8 u8KeyIn; ++ U8 u8KeyOut; ++} MS_IR_KeyValue, *PMS_IR_KeyValue; ++ ++/// define IR key code time & bounds ++typedef struct ++{ ++ S16 s16Time; ///key code time ++ S8 s8UpBnd; ///upper bound ++ S8 s8LoBnd; ///low bound ++} MS_IR_TimeBnd, *PMS_IR_TimeBnd; ++ ++/// define IR key code time tail ++typedef struct ++{ ++ U32 gu32KeyMin; /// Min Tail Time for key ++ U32 gu32KeyMax; /// Max Tail Time for key ++ U32 gu32RptMin; /// Min Tail Time for Rpt ++ U32 gu32RptMax; /// Max Tail Time for Rpt ++} MS_IR_TimeTail, *PMS_IR_TimeTail; ++ ++/// define IR time parameters ++typedef struct ++{ ++ MS_IR_TimeBnd tHdr; /// header code time ++ MS_IR_TimeBnd tOff; /// off code time ++ MS_IR_TimeBnd tOffRpt; /// off code repeat time ++ MS_IR_TimeBnd tLg01Hg; /// logical 0/1 high time ++ MS_IR_TimeBnd tLg0; /// logical 0 time ++ MS_IR_TimeBnd tLg1; /// logical 1 time ++ MS_IR_TimeBnd tSepr; /// Separate time ++ U32 u32TimeoutCyc; /// Timeout cycle count ++ U16 u16RCBitTime; /// RC Bit Time ++ MS_IR_TimeTail tTail; /// Tail Time for sw shot mode ++} MS_IR_TimeCfg, *PMS_IR_TimeCfg; ++ ++/// define IR configuration parameters ++typedef struct ++{ ++ U8 u8DecMode; /// IR mode selection ++ U8 u8ExtFormat; /// IR extention format ++ U8 u8Ctrl0; /// IR enable control 0 ++ U8 u8Ctrl1; /// IR enable control 1 ++ U8 u8Clk_mhz; /// IR required clock ++ U8 u8HdrCode0; /// IR Header code 0 ++ U8 u8HdrCode1; /// IR Header code 1 ++ U8 u8CCodeBytes; /// Customer codes: 1 or 2 bytes ++ U8 u8CodeBits; /// Code bits: 1~128 bits ++ U8 u8KeySelect; /// IR select Nth key N(1~16) ++ U16 u16GlhrmNum; /// Glitch Remove Number ++ EN_SHOT_SEL enShotSel; /// Shot selection for SW decoder ++ BOOL bInvertPolar; /// Invert the polarity for input IR signal ++ ++} MS_IR_InitCfg, *PMS_IR_InitCfg; ++ ++/// define Ping-Pong Buffer structure for IR SW shot count ++typedef struct ++{ ++ U8 u8RdIdx; //Read Index ++ U8 u8WtIdx; //Write Index ++ U32 u32Length; //Data Length for Read Index buffer ++ U32 u32Buffer[IR_MAX_BUF_DPH][IR_MAX_BUF_LEN]; //Ping-Pong Buffer ++} MS_IR_ShotInfo, *PMS_IR_ShotInfo; ++ ++/// define HeaderInfo for sw mode change headercode in apps ++typedef struct ++{ ++ U8 _u8IRHeaderCode0; //IRHeaderCode0 ++ U8 _u8IRHeaderCode1; //IRHeaderCode1 ++ U8 _u8IR2HeaderCode0; //IR2HeaderCode0 ++ U8 _u8IR2HeaderCode1; //IR2HeaderCode1 ++}MS_MultiIR_HeaderInfo, *PMS_MultiIR_HeaderInfo; ++ ++/// define used protocol for multiple protocol mode ++typedef struct ++{ ++ IR_PROCOCOL_TYPE eProtocol; ++ void *pNextProtCfg; ++} MS_MultiProtocolCfg, *PMS_MultiProtocolCfg; ++ ++ ++typedef struct ++{ ++ unsigned int CustomerCode; //Set multi Customer Code ++ unsigned int IR_Protocol; //IR_Protocol: 1:NEC, 2:RAW, 3:SW ++ unsigned char Enable; //Enable ++ unsigned int bResult; // return status ++}MS_IR_MutliCustomerCode, *PMS_IR_MutliCustomerCode; ++ ++ ++ ++#define REG_IR_CTRL (0x0040*4) ++ #define IR_SEPR_EN 0x0200 ++ #define IR_TIMEOUT_CHK_EN 0x0100 ++ #define IR_INV 0x80 ++ #define IR_INT_MASK 0x40 ++ #define IR_RPCODE_EN 0x20 ++ #define IR_LG01H_CHK_EN 0x10 ++ #define IR_DCODE_PCHK_EN 0x08 ++ #define IR_CCODE_CHK_EN 0x04 ++ #define IR_LDCCHK_EN 0x02 ++ #define IR_EN 0x01 ++#define REG_IR_HDC_UPB (0x0041*4) ++#define REG_IR_HDC_LOB (0x0042*4) ++#define REG_IR_OFC_UPB (0x0043*4) ++#define REG_IR_OFC_LOB (0x0044*4) ++#define REG_IR_OFC_RP_UPB (0x0045*4) ++#define REG_IR_OFC_RP_LOB (0x0046*4) ++#define REG_IR_LG01H_UPB (0x0047*4) ++#define REG_IR_LG01H_LOB (0x0048*4) ++#define REG_IR_LG0_UPB (0x0049*4) ++#define REG_IR_LG0_LOB (0x004A*4) ++#define REG_IR_LG1_UPB (0x004B*4) ++#define REG_IR_LG1_LOB (0x004C*4) ++#define REG_IR_SEPR_UPB (0x004D*4) ++#define REG_IR_SEPR_LOB (0x004E*4) ++#define REG_IR_TIMEOUT_CYC_L (0x004F*4) ++#define REG_IR_TIMEOUT_CYC_H_CODE_BYTE (0x0050*4) ++ #define IR_CCB_CB 0x1F00//ir_ccode_byte:1+ir_code_bit_num:32 ++#define REG_IR_SEPR_BIT_FIFO_CTRL (0x0051*4) ++#define REG_IR_CCODE (0x0052*4) ++#define REG_IR_GLHRM_NUM (0x0053*4) ++#define REG_IR_CKDIV_NUM_KEY_DATA (0x0054*4) ++#define REG_IR_SHOT_CNT_L (0x0055*4) ++#define REG_IR_SHOT_CNT_H_FIFO_STATUS (0x0056*4) ++ #define IR_RPT_FLAG 0x0100 ++ #define IR_FIFO_EMPTY 0x0200 ++#define REG_IR_FIFO_RD_PULSE (0x0058*4) ++#define REG_IR_CCODE1 (0x0060*4) ++#define REG_IR_CCODE1_CHK_EN (0x0061*4) ++ ++ ++ ++#endif /* DRIVERS_MSTAR_IR_MS_IR_H_ */ +diff --git a/drivers/mstar/ircut/Kconfig b/drivers/mstar/ircut/Kconfig +new file mode 100644 +index 00000000..8a4113d5 +--- /dev/null ++++ b/drivers/mstar/ircut/Kconfig +@@ -0,0 +1,9 @@ ++config MS_IRCUT ++ tristate "ircut driver" ++ help ++ Say Y here to enable the driver for the ircut. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mdrv_ircut. +diff --git a/drivers/mstar/ircut/Makefile b/drivers/mstar/ircut/Makefile +new file mode 100644 +index 00000000..4903888a +--- /dev/null ++++ b/drivers/mstar/ircut/Makefile +@@ -0,0 +1,5 @@ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_MS_IRCUT) += ms_ircut.o +diff --git a/drivers/mstar/ircut/ms_ircut.c b/drivers/mstar/ircut/ms_ircut.c +new file mode 100644 +index 00000000..91932544 +--- /dev/null ++++ b/drivers/mstar/ircut/ms_ircut.c +@@ -0,0 +1,185 @@ ++#include ++#include ++#include ++#include ++#include /* for MODULE_ALIAS_MISCDEV */ ++#include ++#include ++#include ++#include ++#include ++#include /* kmalloc, kfree */ ++#include /* class_create */ ++#include /* kobject_uevent */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "irqs.h" ++#include "gpio.h" ++#include "mdrv_types.h" ++ ++extern U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Set(U8 u8IndexGPIO); ++extern void MDrv_GPIO_Pad_Odn(U8 u8IndexGPIO); ++ ++ ++//#define IRCUT_DEBUG 1 ++u32 mGpioNum=78; ++u32 mIntNum=182; ++#ifdef IRCUT_DEBUG ++#define IRCUT_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define IRCUT_DBG(fmt, arg...) ++#endif ++#define IRCUT_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++ ++static const struct of_device_id ms_ircut_of_match_table[] = { ++ { .compatible = "mstar,infinity-ircut" }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, ms_ircut_of_match_table); ++static irqreturn_t ircut_handler(int irq, struct uio_info *dev_info) ++{ ++ struct irq_data *data; ++ int level; ++ ++ level= MDrv_GPIO_Pad_Read(mGpioNum); ++ IRCUT_DBG("ms_ircut_level=%d\n",level); ++ IRCUT_DBG("ms_ircut_level irq=%d\n",irq); ++ data = irq_get_irq_data(irq); ++ //data->chip->irq_set_type(data, level?1:0); ++ if(!data) ++ return -ENODEV; ++ data->chip->irq_set_type(data, level?IRQ_TYPE_EDGE_FALLING:IRQ_TYPE_EDGE_RISING); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ms_ircut_probe(struct platform_device *pdev) ++{ ++ //struct resource *res; ++ int ret = 0; ++ struct uio_info *info; ++ const struct of_device_id *match; ++ struct device_node *node = pdev->dev.of_node; ++ struct irq_data *data; ++ int level; ++ ++ IRCUT_DBG("ms_ircut_probe\n"); ++ ++ match = of_match_device(ms_ircut_of_match_table, &pdev->dev); ++ if (!match) { ++ printk("Error:[infinity-ircut] No device match found\n"); ++ return -ENODEV; ++ } ++ ++ if (of_property_read_u32(node, "ircut-gpio-num", &mGpioNum)) { ++ pr_err("%s get failed\n", "ircut-gpio-num"); ++ return -ENODEV; ++ } ++ IRCUT_DBG("11111111 u8GpioNum=%d\n",mGpioNum); ++ ++ MDrv_GPIO_Pad_Set(mGpioNum); ++ MDrv_GPIO_Pad_Odn(mGpioNum); ++ info = kzalloc(sizeof(struct uio_info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ ++ /*res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) ++ { ++ IRCUT_ERR("[%s]: failed to get IORESOURCE_IRQ\n", __func__); ++ return -ENODEV; ++ } ++ info->irq=res->start; ++ ++ IRCUT_DBG("info->irq=%ld\n",info->irq); ++*/ ++ info->mem[0].addr = (unsigned long)kmalloc(1024,GFP_KERNEL); ++ ++ if(info->mem[0].addr == 0) ++ { ++ IRCUT_ERR("Invalid memory resource\n"); ++ kfree(info); ++ return -ENOMEM; ++ } ++ ++ info->mem[0].memtype = UIO_MEM_LOGICAL; ++ info->mem[0].size = 1024; ++ info->version = "0.1"; ++ info->name="ircut"; ++ info->irq=irq_of_parse_and_map(pdev->dev.of_node, 0); ++ info->irq_flags = IRQF_SHARED; ++ info->handler = ircut_handler; ++ mIntNum=(int)info->irq; ++ ret = uio_register_device(&pdev->dev, info); ++ if (ret) ++ { ++ IRCUT_ERR("uio_register failed %d\n",ret); ++ //iounmap(info->mem[0].internal_addr); ++ // printk("uio_register failed %d\n",ret); ++ kfree(info); ++ return -ENODEV; ++ } ++ platform_set_drvdata(pdev, info); ++ ++ level= MDrv_GPIO_Pad_Read(mGpioNum); ++ IRCUT_DBG("ms_ircut_probe,level=%d,info->irq=%ld\n",level,info->irq); ++ ++ data = irq_get_irq_data(mIntNum); ++ data->chip->irq_set_type(data, level?1:0); ++ ++ return 0; ++} ++ ++static int ms_ircut_remove(struct platform_device *pdev) ++{ ++ //uio_unregister_device(&ircut_info); ++ IRCUT_DBG("ms_ircut_remove\n"); ++ return 0; ++} ++#ifdef CONFIG_PM ++static int ms_ircut_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ //uio_unregister_device(&ircut_info); ++ IRCUT_DBG("ms_ircut_suspend\n"); ++ return 0; ++} ++ ++static int ms_ircut_resume(struct platform_device *pdev) ++{ ++ //uio_unregister_device(&ircut_info); ++ IRCUT_DBG("ms_ircut_resume\n"); ++ MDrv_GPIO_Pad_Set(mGpioNum); ++ MDrv_GPIO_Pad_Odn(mGpioNum); ++ return 0; ++} ++#endif ++ ++ ++ ++static struct platform_driver ms_ircut_driver = { ++ .probe = ms_ircut_probe, ++ .remove = ms_ircut_remove, ++#ifdef CONFIG_PM ++ .suspend = ms_ircut_suspend, ++ .resume = ms_ircut_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "infinity-ircut", ++ .of_match_table = ms_ircut_of_match_table, ++ }, ++}; ++module_platform_driver(ms_ircut_driver); ++ ++MODULE_AUTHOR("MStar Semiconductor, Inc."); ++MODULE_DESCRIPTION("ms ircut Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:ms-ircut"); +diff --git a/drivers/mstar/irqchip/Kconfig b/drivers/mstar/irqchip/Kconfig +new file mode 100644 +index 00000000..e69de29b +diff --git a/drivers/mstar/irqchip/Makefile b/drivers/mstar/irqchip/Makefile +new file mode 100644 +index 00000000..9c0efe66 +--- /dev/null ++++ b/drivers/mstar/irqchip/Makefile +@@ -0,0 +1,4 @@ ++obj-$(CONFIG_ARCH_CEDRIC) += cedric/ ++obj-$(CONFIG_ARCH_INFINITY) += infinity/ ++obj-$(CONFIG_ARCH_CHICAGO) += chicago/ ++obj-$(CONFIG_ARCH_INFINITY3) += infinity3/ +\ No newline at end of file +diff --git a/drivers/mstar/irqchip/cedric/Makefile b/drivers/mstar/irqchip/cedric/Makefile +new file mode 100644 +index 00000000..f07f1409 +--- /dev/null ++++ b/drivers/mstar/irqchip/cedric/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/irqchip ++ ++obj-y += irqchip.o +\ No newline at end of file +diff --git a/drivers/mstar/irqchip/cedric/irqchip.c b/drivers/mstar/irqchip/cedric/irqchip.c +new file mode 100644 +index 00000000..f2551a37 +--- /dev/null ++++ b/drivers/mstar/irqchip/cedric/irqchip.c +@@ -0,0 +1,804 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "cedric/irqs.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++ ++#define CEDRIC_INTR_AUDIO_FIRST 1 ++#define CEDRIC_INTR_TO_CORE0 1 ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define PERI_PHYS 0x16000000 ++ ++#define INT_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x80C80) ++#define PMU_INT_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x00700) //PM_SLEEP ++ ++#define CPU_ID_CORE0 0x0 ++#define CPU_ID_CORE1 0x1 ++//#define printk(...) ++ ++ ++#define GIC_DIST_SET_EANBLE (PERI_PHYS + 0x1100) ++#define CASCADE_PMU_INT 1 ++ ++ ++static DEFINE_SPINLOCK(cedric_irq_controller_lock); ++ ++static bool fiq_merged=false; ++ ++ ++static void chip_irq_clear(unsigned int irq) ++{ ++ unsigned short tmp; ++ unsigned long int flags; ++ spin_lock_irqsave(&cedric_irq_controller_lock,flags); ++#if CASCADE_PMU_INT ++ if(irq>127) //PMU ++ { ++ unsigned int pm_tmp,bit_mask; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x74)); ++ bit_mask= (0x01 << (irq - 128)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x74),bit_mask); ++ ++ }while(0!= (bit_mask & PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x78)))); ++ ++ } ++ else //HOST ++#endif ++ { ++ ++ /* only FIQ can clear */ ++ if(irq > 47) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0F)); ++ tmp |= 0x01 << (irq - 48); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0F),tmp); ++ } ++ else if(irq > 31) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0E)); ++ tmp |= 0x01 << (irq - 32); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0E),tmp); ++ } ++ else if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0D)); ++ tmp |= 0x01 << (irq - 16); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0D),tmp); ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0C)); ++ tmp |= (0x01 << irq); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0C),tmp); ++ } ++ } ++ spin_unlock_irqrestore(&cedric_irq_controller_lock,flags); ++ ++} ++ ++/* Clear FIQ (Clear is not supported for IRQ) */ ++static void ms_irq_ack(struct irq_data *data) ++{ ++ ++ chip_irq_clear(data->irq-INT_START); ++ ++} ++ ++static void chip_irq_mask(unsigned int irq) ++{ ++ unsigned short tmp; ++ unsigned long int flags; ++ spin_lock_irqsave(&cedric_irq_controller_lock,flags); ++ ++#if CASCADE_PMU_INT ++ if(irq>127) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70)); ++ pm_tmp|=(0x01 << (irq - 128)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x70),pm_tmp); ++ ++ }while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70))); ++ ++ ++ } ++ else //HOST ++#endif ++ { ++ if(irq > 111) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x17)); ++ tmp |= (0x01) << (irq - 112); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x17),tmp); ++ } ++ else if(irq > 95) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x16)); ++ tmp |= (0x01) << (irq - 96); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x16),tmp); ++ } ++ else if(irq > 79) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x15)); ++ tmp |= (0x01) << (irq - 80); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x15),tmp); ++ } ++ else if(irq > 63) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x14)); ++ tmp |= (0x01) << (irq - 64); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x14),tmp); ++ } ++ else if(irq > 47) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x07)); ++ tmp |= (0x01) << (irq - 48); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x07),tmp); ++ } ++ else if(irq > 31) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x06)); ++ tmp |= (0x01) << (irq - 32); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x06),tmp); ++ } ++ else if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x05)); ++ tmp |= (0x01) << (irq - 16); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x05),tmp); ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x04)); ++ tmp |= (0x01)<irq-INT_START); ++} ++ ++static void chip_irq_unmask(unsigned int irq) ++{ ++ unsigned short tmp; ++ unsigned long int flags; ++ spin_lock_irqsave(&cedric_irq_controller_lock,flags); ++ ++#if CASCADE_PMU_INT ++ if(irq>127) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70)); ++ pm_tmp &= ~(0x01 << (irq - 128)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x70),pm_tmp); ++ ++ }while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70))); ++ ++ ++ } ++ else //HOST ++#endif ++ { ++ if(irq > 111) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x17)); ++ tmp &= ~( 0x01 << (irq - 112)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x17),tmp); ++ } ++ else if(irq > 95) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x16)); ++ tmp &= ~( 0x01 << (irq - 96)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x16),tmp); ++ } ++ else if(irq > 79) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x15)); ++ tmp &= ~( 0x01 << (irq - 80)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x15),tmp); ++ } ++ else if(irq > 63) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x14)); ++ tmp &= ~( 0x01 << (irq - 64)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x14),tmp); ++ } ++ else if(irq > 47) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x07)); ++ tmp &= ~( 0x01 << (irq - 48)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x07),tmp); ++ } ++ else if(irq > 31) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x06)); ++ tmp &= ~( 0x01 << (irq - 32)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x06),tmp); ++ } ++ else if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x05)); ++ tmp &= ~( 0x01 << (irq - 16)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x05),tmp); ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x04)); ++ tmp &= ~( 0x01 << irq); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x04),tmp); ++ } ++ ++ } ++ spin_unlock_irqrestore(&cedric_irq_controller_lock,flags); ++ ++} ++/* Un-Mask IRQ/FIQ */ ++static void ms_irq_unmask(struct irq_data *data) { ++ ++ chip_irq_unmask(data->irq-INT_START); ++ ++} ++ ++static void ms_irq_disable(struct irq_data *data) { ++ ++ ms_irq_mask(data); ++} ++ ++//static unsigned char chip_irq_get_polarity(unsigned int irq) ++//{ ++// unsigned short tmp; ++// ++//#if CASCADE_PMU_INT ++// if(irq>127) //PMU ++// { ++// ++// unsigned int pm_tmp; ++// ++// pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a)); ++// pm_tmp &= (0x01 << (irq - 128)); ++// ++// return ( pm_tmp > 0 )? 1:0; ++// ++// } ++// else //HOST ++//#endif ++// { ++// if(irq > 111) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x1b)); ++// return ((tmp & ( 0x01 << (irq - 112) )) > 0 )? 1:0; ++// } ++// else if(irq > 95) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x1a)); ++// return ((tmp & ( 0x01 << (irq - 96) )) > 0 )? 1:0; ++// } ++// else if(irq > 79) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x19)); ++// return ((tmp & ( 0x01 << (irq - 80) )) > 0 )? 1:0; ++// } ++// else if(irq > 63) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x18)); ++// return ((tmp & ( 0x01 << (irq - 64) )) > 0 )? 1:0; ++// } ++// else if(irq > 47) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0b)); ++// return ((tmp & ( 0x01 << (irq - 48) )) > 0 )? 1:0; ++// } ++// else if(irq > 31) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0a)); ++// return ((tmp & ( 0x01 << (irq - 32) )) > 0 )? 1:0; ++// } ++// else if(irq > 15) ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x09)); ++// return ((tmp & ( 0x01 << (irq - 16) )) > 0 )? 1:0; ++// } ++// else ++// { ++// tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x08)); ++// return ((tmp & ( 0x01 << irq )) > 0 )? 1:0; ++// } ++// ++// } ++//} ++ ++ ++static void chip_irq_set_polarity(unsigned int irq,unsigned char polarity) ++{ ++ unsigned long int flags; ++ spin_lock_irqsave(&cedric_irq_controller_lock,flags); ++ if(polarity>0) //reverse ++ { ++#if CASCADE_PMU_INT ++ if(irq>127) //PMU ++ { ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a)); ++ pm_tmp |= (0x01 << (irq - 128)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x7a),pm_tmp); ++ ++ }while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a))); ++ ++ ++ ++ } ++ else //HOST ++#endif ++ { ++ if(irq > 111) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x1b),( 0x01 << (irq - 112) )); ++ } ++ else if(irq > 95) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x1a),( 0x01 << (irq - 96) )); ++ } ++ else if(irq > 79) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x19),( 0x01 << (irq - 80) )); ++ } ++ else if(irq > 63) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x18),( 0x01 << (irq - 64) )); ++ } ++ else if(irq > 47) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x0b),( 0x01 << (irq - 47) )); ++ } ++ else if(irq > 31) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x0a),( 0x01 << (irq - 32) )); ++ } ++ else if(irq > 15) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x09),( 0x01 << (irq - 16) )); ++ } ++ else ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x08),( 0x01 << irq )); ++ } ++ ++ } ++ } ++ else ++ { ++ ++#if CASCADE_PMU_INT ++ if(irq>127) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a)); ++ pm_tmp &= ~(0x01 << (irq - 128)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x7a),pm_tmp); ++ ++ }while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a))); ++ } ++ else //HOST ++#endif ++ { ++ if(irq > 111) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x1b),( 0x01 << (irq - 112) )); ++ } ++ else if(irq > 95) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x1a),( 0x01 << (irq - 96) )); ++ } ++ else if(irq > 79) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x19),( 0x01 << (irq - 80) )); ++ } ++ else if(irq > 63) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x18),( 0x01 << (irq - 64) )); ++ } ++ else if(irq > 47) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x0b),( 0x01 << (irq - 47) )); ++ } ++ else if(irq > 31) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x0a),( 0x01 << (irq - 32) )); ++ } ++ else if(irq > 15) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x09),( 0x01 << (irq - 16) )); ++ } ++ else ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x08),( 0x01 << irq )); ++ } ++ ++ } ++ ++ } ++ spin_unlock_irqrestore(&cedric_irq_controller_lock,flags); ++} ++ ++static int ms_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++{ ++ //use a very simple implementation here... ++ return irq_get_chip(GIC_ID_LEGACY_IRQ)->irq_set_affinity(irq_get_irq_data(GIC_ID_LEGACY_IRQ),dest,force); ++} ++ ++ ++static int ms_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ ++ if(flow_type & (IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)) ++ { ++ chip_irq_set_polarity(data->irq,0); ++ } ++ else ++ { ++ chip_irq_set_polarity(data->irq,1); ++ } ++ ++ return 0; ++} ++//static unsigned char ms_irq_get_polarity(struct irq_data *data) ++//{ ++// ++// return chip_irq_get_polarity(data->irq-INT_START); ++//} ++// ++// ++// ++//static void ms_irq_set_polarity(struct irq_data *data,unsigned char polarity) ++//{ ++// ++// chip_irq_set_polarity(data->irq-INT_START,polarity); ++//} ++ ++ ++static unsigned int __find_int_nr(unsigned base, unsigned int status_reg_offset, unsigned int bank_nr, unsigned int intr_start, unsigned int intr_max) ++{ ++ unsigned int i=0, status=0, intr=0, intr_idx=0; ++ ++ intr=intr_start; ++ ++ for(i=0;i= 1000) ++ { ++ printk(KERN_ERR "[irqchip-cedric] LEVEL0 IRQ raised but can not be found!!\n"); ++ //BUG(); ++ err = 0; ++ } ++ } ++ ++ chained_irq_exit(chip, desc); ++ ++} ++ ++ ++ ++ ++static struct irq_chip ms_irq_chip = { ++ .name = "Cedric IRQCHIP", ++ .irq_ack = ms_irq_ack, ++ .irq_mask = ms_irq_mask, ++ .irq_unmask = ms_irq_unmask, ++ .irq_disable = ms_irq_disable, ++ .irq_set_type = ms_irq_set_type, ++ .irq_set_affinity=ms_irq_set_affinity, ++}; ++ ++ ++static struct irq_domain *cedric_irq_domain; ++ ++static struct irq_domain_ops ms_irq_domain_ops = { ++// .map = ms_irq_domain_map, ++ .xlate = irq_domain_xlate_onecell, ++}; ++ ++ ++ ++static int __init ms_irq_of_init(struct device_node *np, struct device_node *interrupt_parent) ++{ ++ ++ int irq_base=0; ++ int irq=0; ++ int temp=0; ++ ++ ++ //mask all host0 IRQ ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x17),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x16),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x15),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x14),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x07),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x06),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x05),0xFFFF); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x04),0xFFFF); ++ ++ SETREG16(GET_REG_ADDR(GET_REG_ADDR(MS_BASE_REG_RIU_PA, 0x080E80),0x37), 0x20); ++ fiq_merged=true; ++ ++ ++ ++ ++ irq_base = irq_alloc_descs(-1, INT_START, ((PMU_END-INT_START)+1), 0); ++ BUG_ON(irq_base < 0); ++ ++ cedric_irq_domain = irq_domain_add_legacy(np, ((PMU_END-INT_START)+1), irq_base, INT_START, &ms_irq_domain_ops, NULL); ++ ++ ++ ++ { ++ gic_init_bases(0,29,_gic_dist_base_addr,_gic_cpu_base_addr,0,NULL); ++ ++ ++ temp=INREG32(GIC_DIST_SET_EANBLE+((GIC_ID_LEGACY_IRQ/32)*4)); ++ temp= temp | (0x1 << (GIC_ID_LEGACY_IRQ % 32)); ++ OUTREG32(GIC_DIST_SET_EANBLE+((GIC_ID_LEGACY_IRQ/32)*4),temp); ++ ++#if defined(CONFIG_HAVE_ARM_TWD) ++ temp=INREG32(GIC_DIST_SET_EANBLE+((GIC_ID_LOCAL_TIMER_IRQ/32)*4)); ++ temp= temp | (0x1 << (GIC_ID_LOCAL_TIMER_IRQ % 32)); ++ OUTREG32(GIC_DIST_SET_EANBLE+((GIC_ID_LOCAL_TIMER_IRQ/32)*4),temp); ++#endif ++ ++ ++ irq_set_chained_handler(GIC_ID_LEGACY_IRQ, ms_irq_handle_cascade_host0_irq); ++ ++ #if defined(CEDRIC_INTR_TO_CORE0) ++ irq_set_affinity(GIC_ID_LEGACY_IRQ,cpumask_of(CPU_ID_CORE0)); ++ #endif ++ ++ ++ ++ for(irq=FIQ_START;irq ++//#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "chicago/irqs.h" ++#include "chicago/registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++ ++ ++#define MS_BASE_REG_RIU_PA 0x1F000000 ++#define PERI_PHYS 0x16000000 ++ ++#define INT_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x001580) ++#define PMU_INT_BASE GET_REG_ADDR(MS_BASE_REG_RIU_PA,0x001F80) //PMU ++ ++//#define printk(...) ++ ++ ++ ++ ++static DEFINE_SPINLOCK(irq_controller_lock); ++ ++ ++static void chip_irq_clear(unsigned int irq) ++{ ++ unsigned short tmp; ++ ++ if(irq>63) //PMU ++ { ++ unsigned int pm_tmp,bit_mask; ++ //printk(KERN_INFO"%s %d\n",__func__ , irq); ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x74)); ++ bit_mask= (0x01 << (irq - 64)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x74),bit_mask); ++ ++ } ++ while(0!= (bit_mask & PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x78)))); ++ } ++ else //HOST ++ { ++ ++ /* only FIQ can clear */ ++ if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x1D)); ++ tmp |= 0x01 << (irq - 16); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x05),tmp); ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x1C)); ++ tmp |= (0x01 << irq); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x04),tmp); ++ } ++ } ++ ++ ++} ++ ++/* Clear FIQ (Clear is not supported for IRQ) */ ++static void ms_irq_ack(struct irq_data *data) ++{ ++ ++ chip_irq_clear(data->irq-INT_START); ++ ++} ++ ++static void chip_irq_mask(unsigned int irq) ++{ ++ unsigned short tmp; ++ ++ if(irq>63) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ //printk(KERN_INFO"%s %d\n",__func__ , irq); ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70)); ++ pm_tmp|=(0x01 << (irq - 64)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x70),pm_tmp); ++ ++ } ++ while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70))); ++ ++ ++ } ++ else //HOST ++ ++ { ++ if(irq > 47) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0D)); ++ tmp |= (0x01) << (irq - 48); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0D),tmp); ++ } ++ else if(irq > 31) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0C)); ++ tmp |= (0x01) << (irq - 32); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0C),tmp); ++ } ++ else if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x01)); ++ tmp |= (0x01) << (irq - 16); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x01),tmp); ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x00)); ++ tmp |= (0x01)<irq-INT_START); ++} ++ ++static void chip_irq_unmask(unsigned int irq) ++{ ++ unsigned short tmp; ++ ++ if(irq>63) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ //printk(KERN_INFO"%s %d\n",__func__ , irq); ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70)); ++ pm_tmp &= ~(0x01 << (irq - 64)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x70),pm_tmp); ++ ++ } ++ while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x70))); ++ ++ ++ } ++ else //HOST ++ ++ { ++ ++ if(irq > 47) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0D)); ++ tmp &= ~( 0x01 << (irq - 48)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0D),tmp); ++ } ++ else if(irq > 31) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0C)); ++ tmp &= ~( 0x01 << (irq - 32)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x0C),tmp); ++ } ++ else if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x01)); ++ tmp &= ~( 0x01 << (irq - 16)); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x01),tmp); ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x00)); ++ tmp &= ~( 0x01 << irq); ++ OUTREG16(GET_REG_ADDR(INT_BASE, 0x00),tmp); ++ } ++ ++ } ++} ++/* Un-Mask IRQ/FIQ */ ++static void ms_irq_unmask(struct irq_data *data) ++{ ++ ++ ++ //printk(KERN_INFO"UN Mask IRQ/FIQ:%d\n", (data->irq-INT_START)); ++ ++ chip_irq_unmask(data->irq-INT_START); ++ ++} ++ ++static void ms_irq_disable(struct irq_data *data) ++{ ++ ++ ms_irq_mask(data); ++} ++ ++ ++#if 0 ++unsigned char chip_irq_get_polarity(unsigned int irq) ++{ ++ unsigned short tmp; ++ ++ if(irq>63) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a)); ++ pm_tmp &= (0x01 << (irq - 64)); ++ ++ return ( pm_tmp > 0 )? 1:0; ++ ++ } ++ else //HOST ++ { ++ ++ if(irq > 47) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x15)); ++ return ((tmp & ( 0x01 << (irq - 48) )) > 0 )? 1:0; ++ } ++ else if(irq > 31) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x14)); ++ return ((tmp & ( 0x01 << (irq - 32) )) > 0 )? 1:0; ++ } ++ else if(irq > 15) ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0B)); ++ return ((tmp & ( 0x01 << (irq - 16) )) > 0 )? 1:0; ++ } ++ else ++ { ++ tmp = INREG16(GET_REG_ADDR(INT_BASE, 0x0A)); ++ return ((tmp & ( 0x01 << irq )) > 0 )? 1:0; ++ } ++ ++ } ++} ++#endif ++ ++static void chip_irq_set_polarity(unsigned int irq,unsigned char polarity) ++{ ++ ++ if(polarity>0) ++ { ++ if(irq>63) //PMU ++ { ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a)); ++ pm_tmp |= (0x01 << (irq - 64)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x7a),pm_tmp); ++ ++ } ++ while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a))); ++ ++ ++ ++ } ++ else //HOST ++ { ++ if(irq > 47) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x15),( 0x01 << (irq - 47) )); ++ } ++ else if(irq > 31) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x14),( 0x01 << (irq - 32) )); ++ } ++ else if(irq > 15) ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x0B),( 0x01 << (irq - 16) )); ++ } ++ else ++ { ++ SETREG16(GET_REG_ADDR(INT_BASE, 0x0A),( 0x01 << irq )); ++ } ++ ++ } ++ } ++ else ++ { ++ ++ if(irq>63) //PMU ++ { ++ ++ unsigned int pm_tmp; ++ ++ pm_tmp=PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a)); ++ pm_tmp &= ~(0x01 << (irq - 64)); ++ ++ do ++ { ++ PM_WRITE32(GET_REG_ADDR(PMU_INT_BASE, 0x7a),pm_tmp); ++ ++ } ++ while(pm_tmp!= PM_READ32(GET_REG_ADDR(PMU_INT_BASE, 0x7a))); ++ } ++ else //HOST ++ { ++ if(irq > 47) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x0b),( 0x01 << (irq - 47) )); ++ } ++ else if(irq > 31) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x0a),( 0x01 << (irq - 32) )); ++ } ++ else if(irq > 15) ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x09),( 0x01 << (irq - 16) )); ++ } ++ else ++ { ++ CLRREG16(GET_REG_ADDR(INT_BASE, 0x08),( 0x01 << irq )); ++ } ++ ++ } ++ ++ } ++} ++ ++//#if defined(CONFIG_SMP) ++//static int ms_irq_set_affinity(struct irq_data *data, const struct cpumask *dest, bool force) ++//{ ++// //use a very simple implementation here... ++// return irq_get_chip(GIC_ID_LEGACY_IRQ)->irq_set_affinity(irq_get_irq_data(GIC_ID_LEGACY_IRQ),dest,force); ++// ++// ++//} ++//#endif ++ ++ ++ ++ ++static int ms_irq_set_type(struct irq_data *data, unsigned int flow_type) ++{ ++ ++ if(flow_type & (IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)) ++ { ++ chip_irq_set_polarity(data->irq,0); ++ } ++ else ++ { ++ chip_irq_set_polarity(data->irq,1); ++ } ++ ++ return 0; ++} ++ ++#if 0 ++static unsigned char ms_irq_get_polarity(struct irq_data *data) ++{ ++ ++ return chip_irq_get_polarity(data->irq-INT_START); ++} ++ ++ ++ ++static void ms_irq_set_polarity(struct irq_data *data,unsigned char polarity) ++{ ++ ++ chip_irq_set_polarity(data->irq-INT_START,polarity); ++ ++} ++#endif ++ ++ ++static unsigned int __find_pm_int_nr(unsigned int intr_start) ++{ ++ unsigned int i=0, status=0, intr_idx=0; ++ ++ status=PM_READ32(GET_REG_ADDR(PMU_INT_BASE,0x78)); ++ ++ // status length must be 32 ++ for(i=0; i<32; i++) ++ { ++ if(0!=(status & (1< ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "infinity/irqs.h" ++#include "infinity/registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++static DEFINE_SPINLOCK(infinity_irq_controller_lock); ++ ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++ ++static void ms_pm_sleep_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT6); ++ } ++} ++ ++static void ms_pm_sleep_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ } ++} ++ ++static void ms_pm_sleep_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ } ++ else ++ return; ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++} ++ ++static int ms_pm_sleep_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ if(type) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ if(type) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ if(type) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ else ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ } ++ return 0; ++} ++ ++static void ms_eoi_irq(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ /* NOTE: only clear if it is FIQ */ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[ms_irq_eoi] Unknown ID %lu from GIC\n", d->hwirq); ++ } ++} ++ ++static void ms_mask_irq(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_HWIRQ_MS_START; ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[ms_irq_mask] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++} ++ ++static void ms_unmask_irq(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_HWIRQ_MS_START; ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[ms_irq_unmask] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++} ++ ++static void set_irq_polarity(struct irq_data *d, bool pol) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_HWIRQ_MS_START; ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (pol == true) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (pol == true) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[ms_irq_set_polarity] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++} ++ ++void ms_mask_irq_all(void) ++{ ++ /* mask FIQ 0 - 31 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_44) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_45) , 0xFFFF ); ++ ++ /* mask IRQ 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_54) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_55) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_56) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_57) , 0xFFFF ); ++} ++ ++void ms_unmask_irq_all(void) ++{ ++ /* unmask FIQ 0 - 31 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_44) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_45) , 0 ); ++ ++ /* unmask IRQ 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_54) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_55) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_56) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_57) , 0 ); ++} ++ ++static int ms_set_type_irq(struct irq_data *data, unsigned int flow_type) ++{ ++ ++ if(flow_type & (IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)) ++ { ++ set_irq_polarity(data,0); ++ } ++ else ++ { ++ set_irq_polarity(data,1); ++ } ++ ++ return 0; ++} ++ ++static void ms_handle_cascade_pm_irq(unsigned int irq, struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ struct irq_chip *chip = irq_get_chip(irq); ++ unsigned int final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ ++ chained_irq_enter(chip, desc); ++ ++ spin_lock(&infinity_irq_controller_lock); ++ { ++ for(i=0;i<32;i++) ++ { ++ if(0 !=(final_status & (1< ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "infinity3/irqs.h" ++#include "infinity3/registers.h" ++ ++#include "_ms_private.h" ++#include "ms_platform.h" ++#include "ms_types.h" ++ ++ ++static DEFINE_SPINLOCK(infinity_irq_controller_lock); ++ ++ ++/* _ _ _ _ _ _ _ _ _ _ */ ++/* | | */ ++/* | PM_SLEEP_IRQ(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | MS_FIQ (32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_fiq */ ++/* | | */ ++/* | MS_IRQ (64) | */ ++/* |_ _ _ _ _ _ _ _ _ _| ms_irq */ ++/* | | */ ++/* | ARM_INTERNAL(32) | */ ++/* |_ _ _ _ _ _ _ _ _ _| gic_spi */ ++/* | | */ ++/* | PPI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* | | */ ++/* | SGI (16) | */ ++/* |_ _ _ _ _ _ _ _ _ _| */ ++/* */ ++ ++ ++static void ms_pm_sleep_irq_ack(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_02, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT6); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ ++ } ++} ++ ++static void ms_pm_sleep_irq_mask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ ++} ++ ++static void ms_pm_sleep_irq_unmask(struct irq_data *d) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_00, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT4); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_08, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ else ++ return; ++ ++ CLRREG16(BASE_REG_INTRCTL_PA + REG_ID_54, BIT2); ++} ++ ++static int ms_pm_sleep_irq_set_type(struct irq_data *d, unsigned int type) ++{ ++ U16 pmsleep_fiq; ++ ++ pmsleep_fiq = d->hwirq; ++ ++ if(pmsleep_fiq == INT_PMSLEEP_IR) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT0); ++ } ++ else if(pmsleep_fiq == INT_PMSLEEP_DVI_CK_DET) ++ { ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ else ++ CLRREG16(BASE_REG_PMSLEEP_PA + REG_ID_03, BIT1); ++ } ++ else if(pmsleep_fiq < PMSLEEP_FIQ_END) ++ { ++ pmsleep_fiq -= 2/*first 2 pm_sleep_irqs are not gpio*/; ++ if(type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ else ++ CLRREG16(BASE_REG_PMGPIO_PA + (pmsleep_fiq << 2), BIT7); ++ } ++ else if(pmsleep_fiq < PMSLEEP_IRQ_END) ++ { ++ if(type&IRQ_TYPE_LEVEL_LOW) ++ SETREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ else ++ CLRREG8(BASE_REG_PMSLEEP_PA + REG_ID_09, 1<<(pmsleep_fiq-PMSLEEP_IRQ_START) ); ++ } ++ return 0; ++} ++ ++static void ms_eoi_irq(struct irq_data *d) ++{ ++ s16 ms_fiq; ++ ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ /* NOTE: only clear if it is FIQ */ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_4C + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_fiq >= GIC_SPI_MS_FIQ_NR ) ++ { ++ pr_err("[ms_irq_eoi] Unknown ID %lu from GIC\n", d->hwirq); ++ } ++} ++ ++static void ms_mask_irq(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_HWIRQ_MS_START; ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[ms_irq_mask] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++} ++ ++static void ms_unmask_irq(struct irq_data *d) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ ms_irq = d->hwirq - GIC_HWIRQ_MS_START; ++ ms_fiq = d->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ if( d->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return; ++ } ++ else if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_44 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_54 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[ms_irq_unmask] Unknown hwirq %lu from GIC\n", d->hwirq); ++ } ++} ++ ++void ms_mask_irq_all(void) ++{ ++ /* mask FIQ 0 - 31 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_44) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_45) , 0xFFFF ); ++ ++ /* mask IRQ 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_54) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_55) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_56) , 0xFFFF ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_57) , 0xFFFF ); ++} ++ ++void ms_unmask_irq_all(void) ++{ ++ /* unmask FIQ 0 - 31 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_44) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_45) , 0 ); ++ ++ /* unmask IRQ 0 - 63 */ ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_54) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_55) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_56) , 0 ); ++ OUTREG16( (BASE_REG_INTRCTL_PA + REG_ID_57) , 0 ); ++} ++ ++static int ms_set_type_irq(struct irq_data *data, unsigned int flow_type) ++{ ++ s16 ms_irq; ++ s16 ms_fiq; ++ ++ if( (flow_type&IRQ_TYPE_EDGE_BOTH)==IRQ_TYPE_EDGE_BOTH) ++ { ++ pr_err("could not support IRQ_TYPE_EDGE_BOTH mode 0x%x\n",flow_type); ++ return 0; ++ } ++ ++ if( data->hwirq < GIC_HWIRQ_MS_START ) ++ { ++ return 0; ++ } ++ ++ ms_irq = data->hwirq - GIC_HWIRQ_MS_START; ++ ms_fiq = data->hwirq - GIC_HWIRQ_MS_START - GIC_SPI_MS_IRQ_NR; ++ ++ if( ms_fiq >= 0 && ms_fiq < GIC_SPI_MS_FIQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_EDGE_FALLING) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_48 + (ms_fiq/16)*4 ) , (1 << (ms_fiq%16)) ); ++ } ++ else if( ms_irq >=0 && ms_irq < GIC_SPI_MS_IRQ_NR ) ++ { ++ if (flow_type&IRQ_TYPE_LEVEL_LOW) ++ SETREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ else ++ CLRREG16( (BASE_REG_INTRCTL_PA + REG_ID_58 + (ms_irq/16)*4 ) , (1 << (ms_irq%16)) ); ++ } ++ else ++ { ++ pr_err("[ms_irq_set_polarity] Unknown hwirq %lu from GIC\n", data->hwirq); ++ } ++ ++ return 0; ++} ++ ++static void ms_handle_cascade_pm_irq(unsigned int irq, struct irq_desc *desc) ++{ ++ unsigned int cascade_irq = 0xFFFFFFFF, i; ++ struct irq_chip *chip = irq_get_chip(irq); ++ unsigned int fiq_final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_04) | (INREG16(BASE_REG_PMSLEEP_PA + REG_ID_05)<<16); ++ unsigned int irq_final_status = INREG16(BASE_REG_PMSLEEP_PA + REG_ID_0E)& 0xFF; ++ ++ if(!chip) ++ BUG(); ++ ++ chained_irq_enter(chip, desc); ++ ++ spin_lock(&infinity_irq_controller_lock); ++ { ++ for(i=0;i ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef U8 ++#define U8 u8 ++#endif ++ ++#ifndef U16 ++#define U16 u16 ++#endif ++ ++#ifndef U32 ++#define U32 u32 ++#endif ++ ++#if defined(__cplusplus) && defined(__GNUC__) && (__GNUC__>=4) && (__GNUC_MINOR__>=6) ++#define opaque_enum(e) enum e : int ++#else ++#define opaque_enum(e) enum e ++#endif ++#define typedef_opaque_enum(e1, e2) \ ++ opaque_enum(e1); \ ++ typedef enum e1 e2 ++ ++ ++#endif ++ +diff --git a/drivers/mstar/isp/cedric/drv_isp.c b/drivers/mstar/isp/cedric/drv_isp.c +new file mode 100644 +index 00000000..a5e95e42 +--- /dev/null ++++ b/drivers/mstar/isp/cedric/drv_isp.c +@@ -0,0 +1,1077 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __DRV_ISP_C__ ++#define __DRV_ISP_C__ ++ ++/*--------------------------------------------------------------------------*/ ++/* INCLUDE FILE */ ++/*--------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "ms_msys.h" ++#include "hal_isp.h" ++ ++/*--------------------------------------------------------------------------*/ ++ ++////////////////////////////////////////////////////////// ++ ++/*--------------------------------------------------------------------------*/ ++/* CONSTANT DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++#define ISP_DBG 0 ++#if ISP_DBG ++#define DBG_INFO(fmt, _args...) \ ++ do { \ ++ printk(KERN_WARNING "[ISP] ""%s(%d): " fmt "\n", __FUNCTION__, __LINE__, ##_args); \ ++ } while (0) ++#else ++#define DBG_INFO(fmt, arg...) {} ++#endif ++ ++ ++/*--------------------------------------------------------------------------*/ ++/* MACRO DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++#define ISP_BIN_ATTR(_a,_b) \ ++ struct bin_attribute _a##_attr = { \ ++ .attr = { .name = __stringify(_a), \ ++ .mode = _b, }, \ ++ .size = 0, \ ++ .read = _a##_read, \ ++ .write = _a##_write, \ ++} ++ ++#define C_IN(lock) local_irq_save(flags) ++#define C_OUT(lock) local_irq_restore(flags) ++ ++/*--------------------------------------------------------------------------*/ ++/* DATA TYPE DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++typedef struct { ++ unsigned int u4PhyAddr; ++ unsigned int u4VirAddr; ++ unsigned long u4Stat[9*2]; ++} EIS_STS_t; ++ ++typedef struct EIS_VDOS_t { ++ int width; ++ int height; ++ int pitch; ++ int size; ++ //int phyAddr; ++ unsigned char data[5*1024*1024]; ++} eEIS_VDOS_t; ++ ++typedef struct { ++ u32 frame_cnt; ++ u8 sysfs_int; ++ u8 vsync_start; ++ u8 vsync_end; ++ u8 ae; ++ u8 awb; ++ u8 af; ++ u8 isp_busy; ++ u8 isp_idle; ++ u8 isp_fifofull; ++ u8 wdma_fifofull; ++ u8 rdma_done; ++ u8 wdma_done; ++ u8 eis; ++ ++ void *pISPRegs[8]; ++ unsigned long AE_Lum[64]; // 8x8 windows ++ unsigned long AE_Hist[64]; // 8x8 windows ++ unsigned long AF_Stat[60]; // 5 windows ++ unsigned long AWB_Stat[80]; // 5 windows ++ ++ EIS_STS_t EIS_Stat; ++ ++ // FIXJASON ++ eEIS_VDOS_t EIS_VDOS; ++ ++} ISP_INT_DATA; ++ ++static volatile ISP_INT_DATA isp_int; ++//static DEFINE_SPINLOCK(isp_lock); ++ ++/*--------------------------------------------------------------------------*/ ++/* VARIABLE DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++irqreturn_t isp_ISR(int num, void *priv); ++static int isp_probe(struct platform_device* pdev); ++static int isp_suspend(struct platform_device *pdev, pm_message_t state); ++static int isp_resume(struct platform_device *pdev); ++int isp_create_bin_file(struct device *dev); ++ ++static struct of_device_id isp_dt_ids[] = { ++ {.compatible = "isp"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, isp_dt_ids); ++ ++#if 1 ++static struct platform_device *isp_device; ++#else ++void *ISP_REGS[] = {0x1F2A0C00,0x1F2A0E00,0x1F2A1000,0x1F2A1200,0x1F2A1400,0x1F2A1600,0x1F2A1800,0x1F2A1A00}; ++static struct platform_device isp_device = ++{ ++ .name = "isp", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(ISP_REGS), ++ .resource = ISP_REGS, ++}; ++#endif ++ ++static struct platform_driver isp_driver = ++{ ++ .probe = isp_probe, ++ .suspend = isp_suspend, ++ .resume = isp_resume, ++ .driver = { ++ .name = "isp", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(isp_dt_ids), ++ }, ++}; ++ ++ ++ ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_WDMA_FIFO_FULL); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_FIFO_FULL); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_RDMA_DONE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_WDMA_DONE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_IDLE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_BUSY); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_VSTART); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_VEND); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_awb); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_af); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_eis); // FIXJASON, still not used ++ ++static struct kobject *kobj_isp = NULL; //, *kobj_vs_sr, *kobj_ve_sr, ++//*kobj_ae, *kobj_awb, *kobj_af, *kobj_busy, *kobj_idle; ++ ++ ++/*--------------------------------------------------------------------------*/ ++/* LOCAL FUNCTION PROTOTYPE DECLARATION AND DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++extern int msys_request_dmem(MSYS_DMEM_INFO *mem_info); ++static int isp_probe(struct platform_device* pdev) { ++ int irq, i; ++ unsigned int u4Banks[8]; ++ printk(KERN_NOTICE "[ISP] = isp_probe\n"); ++ ++#if 1 ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4Banks, 8); ++ for (i = 0; i < 8; i++) { ++ printk(KERN_INFO "[ISP:%d] IO remap addr:0x%08x\n", i, (unsigned int)ioremap(u4Banks[i], 0x200)); ++ isp_int.pISPRegs[i] = (void*)ioremap(u4Banks[i], 0x200); ++ } ++#else ++ struct resource *r; ++ for (i = 0; i < 8; i++) { ++ r = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ printk(KERN_INFO "[ISP:%d of %d] IO remap addr:0x%08x\n", i, pdev->num_resources, (unsigned int)ioremap(r->start, resource_size(r))); ++ isp_int.pISPRegs[i] = (void *)ioremap(r->start, resource_size(r)); ++ } ++#endif ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ printk(KERN_INFO "[ISP] Request IRQ: %d\n", irq); ++ if (request_irq(irq, isp_ISR, IRQ_TYPE_EDGE_RISING, "isp interrupt", (void*)&isp_int) == 0) ++ { ++ printk(KERN_INFO "[ISP] isp interrupt registered\n"); ++ } ++ else ++ { ++ printk(KERN_INFO "[ISP] isp interrupt failed"); ++ } ++ ++ SETREG8((0x1F000000+(0x112B00*2)+(0x16*4)),0x01); //set GPIO28 to GPIO function ++ CLRREG16((0x1F000000+(0x101A00*2)+(0x12*4)),(0x0001<<12)); //set GPIO28 pad mux to GPIO ++ CLRREG16((0x1F000000+(0x102B00*2)+(0x12*4)),(0x0001<<9)); //GPIO28 OEN ++ SETREG16((0x1F000000+(0x102B00*2)+(0x12*4)),(0x0001<<8)); //GPIO28 pull ligh ++ isp_device = pdev; ++ ++ return 0; ++} ++ ++static int isp_suspend(struct platform_device *pdev, pm_message_t state) { ++ printk(KERN_NOTICE "[ISP] = isp_suspend\n"); ++ if (!pdev) ++ DBG_INFO("isp_suspend with NULL pdev %d", isp_int.frame_cnt); ++ ++ isp_int.sysfs_int = false; ++ HalISPClkEnable(false); ++ return 0; ++} ++ ++static int isp_resume(struct platform_device *pdev) { ++ HalISPDisableInt(); ++ HalISPClkEnable(true); ++ isp_int.sysfs_int = false; ++ printk(KERN_NOTICE "[ISP] = isp_resume\n"); ++ return 0; ++} ++ ++irqreturn_t isp_ISR(int num, void *priv) { ++ volatile u32 clear = 0; ++ volatile u32 clear2 = 0; ++ volatile u32 status; ++ volatile u32 status2; ++ volatile u32 vsync_pos; ++ volatile u32 mipi_if; ++ ++ HalISPMaskInt(); ++ status = HalISPGetIntStatus(); ++ status2 = HalISPGetIntStatus2(); ++ vsync_pos = HalISPGetVsyncPol(); ++ mipi_if = HalISPGetMIPI(); ++ ++ if (status == 0 && status2 == 0) { ++ printk(KERN_ERR "[ISP] False interrupt? mask1 0x%04x, mask2 0x%04x\n", status, status2); ++ HalISPMaskClear1(0xffff); ++ HalISPMaskClear2(0xffff); ++ //while(1); ++ return IRQ_HANDLED; ++ } ++ // else ++ // printk(KERN_ERR "[ISP] True interrupt, mask1 0x%04x, mask2 0x%04x\n", status, status2); ++ ++ if (isp_int.sysfs_int == false) { ++ DBG_INFO("isp_int.sysfs_int == false"); ++ HalISPDisableInt(); ++ return IRQ_HANDLED; ++ } ++ ++ // DBG_INFO("raw status 0x%04x, 0x%04x, status2 0x%04x, mipi 0x%04x, vsync_pol 0x%04x, frame %d, sysfs %d\n", ++ // HalISPGetRawInt(), HalISPGetIntStatus(), status2, ++ // mipi_if, vsync_pos, isp_int.frame_cnt, ++ // isp_int.sysfs_int); ++ ++ //return IRQ_HANDLED; ++ ++ //////////////////////////////////////////// ++ // Vsync Start // ++ //////////////////////////////////////////// ++ if (mipi_if) { ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_ISPIF_VSYNC)) { ++ HalISPClearInt(&clear, INT_ISPIF_VSYNC); ++ DBG_INFO("MIPI VSYNC ACTIVE %d", isp_int.frame_cnt); ++ isp_int.vsync_start = true; ++ isp_int.frame_cnt++; ++ wake_up_interruptible_all(&isp_wq_VSTART); ++ } ++ } ++ else { ++ // parallel ++#if 0 ++ // if ((ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == true) || ++ // (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == false)){ ++ // ++ // if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == true) { ++ // DBG_INFO("Parallel INT_PAD_VSYNC_RISING %d", isp_int.frame_cnt); ++ // HalISPClearInt(&clear, INT_PAD_VSYNC_FALLING); ++ // } else if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == false) { ++ // DBG_INFO("Parallel INT_PAD_VSYNC_FALLING %d", isp_int.frame_cnt); ++ // HalISPClearInt(&clear, INT_PAD_VSYNC_RISING); ++ // } ++#else ++ if ((ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == true) || ++ (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == false)){ ++ // if ((ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == true) || ++ // (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == false)){ ++ ++ // if (ISP_CHECKBITS(HalISPGetRawInt(), INT_PAD_VSYNC_RISING)) { ++ // HalISPClearInt(&clear, INT_PAD_VSYNC_FALLING); ++ // } else if (ISP_CHECKBITS(HalISPGetRawInt(), INT_PAD_VSYNC_FALLING)) { ++ // DBG_INFO("Parallel INT_PAD_VSYNC_FALLING %d", isp_int.frame_cnt); ++ // HalISPClearInt(&clear, INT_PAD_VSYNC_RISING); ++ // } ++#endif ++ // printk(KERN_ERR "raw status 0x%04x, 0x%04x, status2 0x%04x, vsync start %d\n", ++ // HalISPGetRawInt(), HalISPGetIntStatus(), status2, isp_int.vsync_start); ++ ++ isp_int.frame_cnt++; ++ if (isp_int.vsync_start == false) { ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == true) { ++ if (isp_int.frame_cnt%600==0) ++ DBG_INFO("Parallel INT_PAD_VSYNC_RISING %d", isp_int.frame_cnt); ++ HalISPClearInt(&clear, INT_PAD_VSYNC_RISING); ++ } else if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == false) { ++ if (isp_int.frame_cnt%600==0) ++ DBG_INFO("Parallel INT_PAD_VSYNC_FALLING %d", isp_int.frame_cnt); ++ HalISPClearInt(&clear, INT_PAD_VSYNC_FALLING); ++ } ++ isp_int.vsync_start = true; ++ wake_up_interruptible_all(&isp_wq_VSTART); ++ } else { ++ //DBG_INFO("Parallel Vsync Start ---FALSE---"); ++ } ++ } ++ } ++ ++ ++ ////////////////////////////////////////////// ++ // statistics // ++ ////////////////////////////////////////////// ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_AE_DONE)) { ++ DBG_INFO("INT_AE_DONE %d", isp_int.frame_cnt); ++ HalISPGetAEStat(isp_int.AE_Lum); ++ HalISPGetAEHist(isp_int.AE_Hist); ++ HalISPClearInt(&clear, INT_AE_DONE); ++ isp_int.ae = true; ++ wake_up_interruptible_all(&isp_wq_ae); ++ } ++ ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_AWB_DONE)) { ++ DBG_INFO("INT_AWB_DONE %d", isp_int.frame_cnt); ++ HalISPGetAWBStat(isp_int.AWB_Stat); ++ HalISPClearInt(&clear, INT_AWB_DONE); ++ isp_int.awb = true; ++ wake_up_interruptible_all(&isp_wq_awb); ++ } ++ ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_AF_DONE)) { ++ DBG_INFO("INT_AF_DONE %d", isp_int.frame_cnt); ++ HalISPGetAFStat(isp_int.AF_Stat); ++ HalISPClearInt(&clear, INT_AF_DONE); ++ isp_int.af = true; ++ wake_up_interruptible_all(&isp_wq_af); ++ } ++ ++ //////////////////////////////////////////// ++ // ISP statis // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_ISP_BUSY)) { ++ HalISPClearInt(&clear, INT_ISP_BUSY); ++ DBG_INFO("INT_ISP_BUSY %d", isp_int.frame_cnt); ++ isp_int.isp_busy = true; ++ wake_up_interruptible_all(&isp_wq_ISP_BUSY); ++ } ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_ISP_IDLE)) { ++ HalISPClearInt(&clear, INT_ISP_IDLE); ++ DBG_INFO("INT_ISP_IDLE %d", isp_int.frame_cnt); ++ isp_int.isp_idle = true; ++ wake_up_interruptible_all(&isp_wq_ISP_IDLE); ++ } ++ ++ //////////////////////////////////////////// ++ // Vsync end // ++ //////////////////////////////////////////// ++ ++#if 0 ++ // if (!mipi_if ) { ++ // if ((ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == false) || ++ // (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == true)) { ++ // if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == false) ++ // HalISPClearInt(&clear, INT_PAD_VSYNC_FALLING); ++ // if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == true) ++ // HalISPClearInt(&clear, INT_PAD_VSYNC_RISING); ++#else ++ if (!mipi_if ) { ++ if ((ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == false) || ++ (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == true)) { ++ // if ((ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == false) || ++ // (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == true)) { ++ ++#endif ++ // printk(KERN_ERR "raw status 0x%04x, 0x%04x, status2 0x%04x, vsync end %d\n", ++ // HalISPGetRawInt(), HalISPGetIntStatus(), status2, isp_int.vsync_end); ++ ++ if (isp_int.vsync_end == false) { ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_RISING) && vsync_pos == false) { ++ HalISPClearInt(&clear, INT_PAD_VSYNC_RISING); ++ if (isp_int.frame_cnt%600==0) ++ DBG_INFO("Parallel Vsync End INT_PAD_VSYNC_RISING %d", isp_int.frame_cnt); ++ } ++ else if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_PAD_VSYNC_FALLING) && vsync_pos == true) { ++ HalISPClearInt(&clear, INT_PAD_VSYNC_FALLING); ++ if (isp_int.frame_cnt%600==0) ++ DBG_INFO("Parallel Vsync End INT_PAD_VSYNC_FALLING %d", isp_int.frame_cnt); ++ } ++ isp_int.vsync_end = true; ++ wake_up_interruptible_all(&isp_wq_VEND); ++ } else { ++ //DBG_INFO("Parallel Vsync End ---FALSE---"); ++ } ++ } ++ } ++ ++ ++ //////////////////////////////////////////// ++ // DMA // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_WDMA_DONE) && isp_int.wdma_done == false) { ++ HalISPClearInt(&clear, INT_WDMA_DONE); ++ HalISPClearInt(&clear, INT_PAD_VSYNC_RISING); ++ HalISPClearInt(&clear, INT_PAD_VSYNC_FALLING); ++ DBG_INFO("INT_WDMA_DONE %d", isp_int.frame_cnt); ++ isp_int.wdma_done = true; ++ wake_up_interruptible_all(&isp_wq_WDMA_DONE); ++ } else { ++ //DBG_INFO("INT_WDMA_DONE %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_RDMA_DONE) && isp_int.rdma_done == false) { ++ HalISPClearInt(&clear, INT_RDMA_DONE); ++ DBG_INFO("INT_RDMA_DONE %d", isp_int.frame_cnt); ++ isp_int.rdma_done = true; ++ wake_up_interruptible_all(&isp_wq_RDMA_DONE); ++ } else { ++ //DBG_INFO("INT_RDMA_DONE %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ //////////////////////////////////////////// ++ // FIFO Full // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_ISP_FIFO_FULL) ++ //&& isp_int.isp_fifofull == false ++ ) ++ { ++ HalISPClearInt(&clear, INT_ISP_FIFO_FULL); ++ DBG_INFO("INT_ISP_FIFO_FULL %d", isp_int.frame_cnt); ++ isp_int.isp_fifofull = true; ++ wake_up_interruptible_all(&isp_wq_ISP_FIFO_FULL); ++ } else { ++ //DBG_INFO("INT_ISP_FIFO_FULL %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ if (ISP_CHECKBITS(HalISPGetIntStatus(), INT_WDMA_FIFO_FULL) && ++ isp_int.wdma_fifofull == false) { ++ HalISPClearInt(&clear, INT_WDMA_FIFO_FULL); ++ DBG_INFO("INT_WDMA_FIFO_FULL %d", isp_int.frame_cnt); ++ isp_int.wdma_fifofull = true; ++ wake_up_interruptible_all(&isp_wq_WDMA_FIFO_FULL); ++ } else { ++ //DBG_INFO("INT_WDMA_FIFO_FULL %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ if (ISP_CHECKBITS(HalISPGetIntStatus2(), INT2_VDOS_EVERYLINE)) { ++ HalISPClearInt2(&clear2, INT2_VDOS_EVERYLINE); ++ DBG_INFO("INT2_VDOS_EVERYLINE %d", isp_int.frame_cnt); ++ } ++ if (ISP_CHECKBITS(HalISPGetIntStatus2(), INT2_VDOS_LINE0)) { ++ HalISPClearInt2(&clear2, INT2_VDOS_LINE0); ++ DBG_INFO("INT2_VDOS_LINE0 %d", isp_int.frame_cnt); ++ } ++ if (ISP_CHECKBITS(HalISPGetIntStatus2(), INT2_VDOS_LINE1)) { ++ HalISPClearInt2(&clear2, INT2_VDOS_LINE1); ++ DBG_INFO("INT2_VDOS_LINE1 %d", isp_int.frame_cnt); ++ } ++ if (ISP_CHECKBITS(HalISPGetIntStatus2(), INT2_VDOS_LINE2)) { ++ HalISPClearInt2(&clear2, INT2_VDOS_LINE2); ++ DBG_INFO("INT2_VDOS_LINE2 %d", isp_int.frame_cnt); ++ ++ //HalISPGetVDOSWidth( &(isp_int.EIS_VDOS.width) ); ++ //HalISPGetVDOSHight( &(isp_int.EIS_VDOS.height) ); ++ HalISPGetVDOSPitch( &(isp_int.EIS_VDOS.pitch) ); ++ HalISPGetVDOSSize( &(isp_int.EIS_VDOS.size), isp_int.EIS_VDOS.pitch ); ++ HalISPGetVDOSData( (unsigned long*)isp_int.EIS_VDOS.data, isp_int.EIS_VDOS.size ); ++ //printk(KERN_INFO "isp_int.EIS_VDOS.width(%d) isp_int.EIS_VDOS.height(%d)\n", isp_int.EIS_VDOS.width, isp_int.EIS_VDOS.height); ++ //printk(KERN_INFO "isp_int.EIS_VDOS.pitch(%d) isp_int.EIS_VDOS.size(%d)\n", isp_int.EIS_VDOS.pitch, isp_int.EIS_VDOS.size); ++ ++ isp_int.eis = true; ++ wake_up_interruptible_all(&isp_wq_eis); ++ } ++ ++ HalISPMaskClear1(clear); ++ HalISPMaskClear2(clear2); ++ if (isp_int.frame_cnt%600==0) { ++ DBG_INFO("end of ISR, status:0x%04x, clear:0x%04x", HalISPGetIntStatus(), clear); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int isp_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ DBG_INFO("buff in %d, out %d\n", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } ++ return data_size; ++} ++ ++static int isp_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ MSYS_DMEM_INFO EIS_MemInfo; ++ if (buf && size >= 1) { ++ memset((void*)&isp_int, 0, sizeof(ISP_INT_DATA)); ++ isp_int.sysfs_int = (buf[0] & 0x01); ++ ++ EIS_MemInfo.length = sizeof(unsigned long)*9*2; ++ msys_request_dmem(&EIS_MemInfo); ++ isp_int.EIS_Stat.u4PhyAddr = EIS_MemInfo.phys; ++ isp_int.EIS_Stat.u4VirAddr = EIS_MemInfo.kvirt; ++ ++ printk(KERN_NOTICE "[isp_write] P:%x, V:%x\n", ++ isp_int.EIS_Stat.u4PhyAddr, ++ isp_int.EIS_Stat.u4VirAddr); ++ } else { ++ memset((void*)&isp_int, 0, sizeof(ISP_INT_DATA)); ++ isp_int.sysfs_int = false; ++ } ++ ++ if (isp_int.sysfs_int == true) ++ HalISPEnableInt(); ++ ++ DBG_INFO("[%s] isp_int.sysfs_int %d\n", __FUNCTION__, ++ isp_int.sysfs_int); ++ ++ return size; ++} ++ ++static int vs_sr_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_VSTART, isp_int.vsync_start == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.vsync_start = false; ++ C_OUT(isp_lock); ++ return -ERESTARTSYS; ++ } ++ C_IN(isp_lock); ++ isp_int.vsync_start = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ // FIXJASON ++ // jason print something... ++ ++ return data_size; ++} ++ ++static int vs_sr_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int ve_sr_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 4; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_VEND, isp_int.vsync_end == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.vsync_end = false; ++ C_OUT(isp_lock); ++ return -ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.vsync_end = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ ++ return data_size; ++} ++static int ve_sr_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++ ++static int ae_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int lum_size, hist_size; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae, isp_int.ae == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.ae = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae = false; ++ C_OUT(isp_lock); ++ ++ HalISPGetAEStatSize(&lum_size); ++ HalISPGetAEHistSize(&hist_size); ++ if (buf && size >= lum_size+hist_size) { ++ memcpy((void *)buf, (void *)isp_int.AE_Lum, lum_size); ++ memcpy((void *)(buf+lum_size), (void *)isp_int.AE_Hist, hist_size); ++ //DBG_INFO("buff in %d, out %d", size, lum_size+hist_size); ++ } else ++ lum_size = hist_size = 0; ++ ++ return lum_size+hist_size; ++} ++static int ae_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int awb_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ u32 awb_size; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_awb, isp_int.awb == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.awb = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.awb = false; ++ C_OUT(isp_lock); ++ ++ ++ ++ HalISPGetAWBStatSize(&awb_size); ++ if (buf && size >= awb_size) { ++ //DBG_INFO("buff in %d, out %d", size, awb_size); ++ memcpy((void *)buf, (void *)isp_int.AWB_Stat, awb_size); ++ } else ++ awb_size = 0; ++ ++ return awb_size; ++} ++static int awb_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int af_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ u32 af_size; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_af, isp_int.af == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.af = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.af = false; ++ C_OUT(isp_lock); ++ ++ HalISPGetAFStatSize(&af_size); ++ if (buf && size >= af_size) { ++ //DBG_INFO("buff in %d, out %d", size, af_size); ++ memcpy((void *)buf, (void *)isp_int.AF_Stat, af_size); ++ } else ++ af_size = 0; ++ ++ return af_size; ++} ++static int af_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int busy_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_BUSY, isp_int.isp_busy == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_busy = false; ++ C_OUT(isp_lock); ++ ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_busy = false; ++ C_OUT(isp_lock); ++ ++ ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ ++ return data_size; ++} ++static int busy_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int idle_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_IDLE, isp_int.isp_idle == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_idle = false; ++ C_OUT(isp_lock); ++ ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_idle = false; ++ C_OUT(isp_lock); ++ ++ ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ ++ return data_size; ++} ++static int idle_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++/// isp fifo full ++static int isp_fifofull_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_FIFO_FULL, isp_int.isp_fifofull == true)) ++ { ++ ++ C_IN(isp_lock); ++ isp_int.isp_fifofull = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_fifofull = false; ++ C_OUT(isp_lock); ++ ++ ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++static int isp_fifofull_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++// wdma fifo full ++static int wdma_fifofull_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_WDMA_FIFO_FULL, isp_int.wdma_fifofull == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.wdma_fifofull = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.wdma_fifofull = false; ++ C_OUT(isp_lock); ++ ++ ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++static int wdma_fifofull_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++ ++// wdma done ++static int wdma_done_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_WDMA_DONE, isp_int.wdma_done == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.wdma_done = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.wdma_done = false; ++ C_OUT(isp_lock); ++ ++ ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ ++ return data_size; ++} ++static int wdma_done_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++// rdma done ++static int rdma_done_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_RDMA_DONE, isp_int.rdma_done == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.rdma_done = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ C_IN(isp_lock); ++ isp_int.rdma_done = false; ++ C_OUT(isp_lock); ++ ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ ++ return data_size; ++} ++static int rdma_done_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++// eis vdos ++static int eis_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { // FIXJASON ++ unsigned long flags; ++ isp_int.EIS_VDOS.size = 0; ++ if (wait_event_interruptible(isp_wq_eis, isp_int.eis == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.eis = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.eis = false; ++ C_OUT(isp_lock); ++ ++ HalISPGetVDOSPitch( &(isp_int.EIS_VDOS.pitch) ); ++ HalISPGetVDOSSize( &(isp_int.EIS_VDOS.size), isp_int.EIS_VDOS.pitch ); ++ if (buf && size >= isp_int.EIS_VDOS.size) { ++ //DBG_INFO("buff in %d, out %d", size, isp_int.EIS_VDOS.size); ++ memcpy((void *)buf, (void *)isp_int.EIS_VDOS.data, isp_int.EIS_VDOS.size); ++ } else ++ isp_int.EIS_VDOS.size = 0; ++ ++ return isp_int.EIS_VDOS.size; ++} ++static int eis_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { // FIXJASON ++ DBG_INFO(); ++ return size; ++} ++ ++ ++ ++static ISP_BIN_ATTR(isp, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(vs_sr, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ve_sr, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(awb, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(af, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(busy, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(idle, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(isp_fifofull, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(wdma_fifofull, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(wdma_done, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(rdma_done, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(eis, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); // FIXJASON ++ ++int isp_create_bin_file(struct device *dev) ++{ ++ int error = -EINVAL; ++ if (dev != NULL) { ++ kobj_isp = &dev->kobj; ++ printk(KERN_INFO "[%s] start", __FUNCTION__); ++ ++ error = sysfs_create_link(&dev->parent->kobj, kobj_isp, "isp0"); ++ error = sysfs_create_bin_file(kobj_isp, &isp_attr); ++ error = sysfs_create_bin_file(kobj_isp, &vs_sr_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ve_sr_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_attr); ++ error = sysfs_create_bin_file(kobj_isp, &awb_attr); ++ error = sysfs_create_bin_file(kobj_isp, &af_attr); ++ error = sysfs_create_bin_file(kobj_isp, &busy_attr); ++ error = sysfs_create_bin_file(kobj_isp, &idle_attr); ++ error = sysfs_create_bin_file(kobj_isp, &isp_fifofull_attr); ++ error = sysfs_create_bin_file(kobj_isp, &wdma_fifofull_attr); ++ error = sysfs_create_bin_file(kobj_isp, &wdma_done_attr); ++ error = sysfs_create_bin_file(kobj_isp, &rdma_done_attr); ++ error = sysfs_create_bin_file(kobj_isp, &eis_attr); // FIXJASON ++ } ++ printk(KERN_INFO "[%s] end", __FUNCTION__); ++ return error; ++} ++ ++void isp_remove_bin_file(void) ++{ ++ sysfs_remove_bin_file(kobj_isp, &isp_attr); ++ sysfs_remove_bin_file(kobj_isp, &vs_sr_attr); ++ sysfs_remove_bin_file(kobj_isp, &ve_sr_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_attr); ++ sysfs_remove_bin_file(kobj_isp, &awb_attr); ++ sysfs_remove_bin_file(kobj_isp, &af_attr); ++ sysfs_remove_bin_file(kobj_isp, &busy_attr); ++ sysfs_remove_bin_file(kobj_isp, &idle_attr); ++ sysfs_remove_bin_file(kobj_isp, &isp_fifofull_attr); ++ sysfs_remove_bin_file(kobj_isp, &wdma_fifofull_attr); ++ sysfs_remove_bin_file(kobj_isp, &wdma_done_attr); ++ sysfs_remove_bin_file(kobj_isp, &rdma_done_attr); ++ sysfs_remove_bin_file(kobj_isp, &eis_attr); // FIXJASON ++ ++ // DBG_INFO("[%s] end", __FUNCTION__); ++} ++ ++ ++static int __init mstar_isp_init(void) ++{ ++ int ret; ++ memset((void*)&isp_int, 0, sizeof(isp_int)); ++ isp_int.sysfs_int = false; ++ ++ printk(KERN_INFO "[ISP] %s\n", __FUNCTION__); ++ ret = platform_driver_register(&isp_driver); ++ if(!ret) ++ { ++ printk(KERN_INFO "[ISP] register driver success"); ++ //ret = platform_device_register(&isp_device); ++ //ret = platform_device_register(isp_device); ++ if(!ret) ++ { ++ printk(KERN_INFO "[ISP] register device success"); ++// isp_create_bin_file(&isp_device.dev); ++ isp_create_bin_file(&isp_device->dev); ++// printk(KERN_INFO "[ISP] Request IRQ: %d\n", INT_IRQ_ISP); ++// if (request_irq(INT_IRQ_ISP, isp_ISR, IRQ_TYPE_EDGE_RISING, "isp interrupt", (void*)&isp_int) == 0) ++// { ++// printk(KERN_INFO "[ISP] isp interrupt registered\n"); ++// } ++// else ++// { ++// printk(KERN_INFO "[ISP] isp interrupt failed"); ++// } ++ } else { ++ printk(KERN_INFO "[ISP] register device fail"); ++ platform_driver_unregister(&isp_driver); ++ } ++ } ++ ++ return 0; ++} ++ ++ ++static void __exit mstar_isp_exit(void) ++{ ++ printk(KERN_INFO "[ISP] exit"); ++ platform_driver_unregister(&isp_driver); ++ isp_remove_bin_file(); ++} ++ ++module_init(mstar_isp_init); ++module_exit(mstar_isp_exit); ++ ++#endif//__DRV_ISP_C__ +diff --git a/drivers/mstar/isp/cedric/hal_isp.c b/drivers/mstar/isp/cedric/hal_isp.c +new file mode 100644 +index 00000000..02f536a3 +--- /dev/null ++++ b/drivers/mstar/isp/cedric/hal_isp.c +@@ -0,0 +1,258 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "MsTypes.h" ++ ++#include "hal_isp.h" ++ ++static volatile u32 *isp_cpu_int = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x2b*4); ++static volatile u32 *isp_raw_int = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x2c*4); ++static volatile u32 *isp_cpu_int2 = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x2f*4); ++ ++// FIXJASON ++//static volatile u32 *isp_int_force = ++// (volatile u32*)(RIUBASE_ISP_0 + 0x29*4); ++ ++static volatile u32 *isp_int_mask = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x28*4); ++static volatile u32 *isp_int_mask2 = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x2d*4); ++ ++static volatile u32 *isp_int_clear = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x2a*4); ++static volatile u32 *isp_int_clear2 = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x2e*4); ++ ++static volatile u32 *isp_vsync_pol = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x10*4); ++static volatile u32 *isp_sif = ++ (volatile u32*)(RIUBASE_ISP_0 + 0x05*4); ++ ++static volatile u32 *isp_aests = (volatile u32*)(RIUBASE_ISP_4 + 0x40*4); // 0x7f ++static volatile u32 *isp_aehist = (volatile u32*)(RIUBASE_ISP_4 + 0x00*4);// 0x3f ++static volatile u32 *isp_awbsts = (volatile u32*)(RIUBASE_ISP_3 + 0x18*4);// 0x3f ++static volatile u32 *isp_afsts = (volatile u32*)(RIUBASE_ISP_5 + 0x18*4); // 0x35 ++ ++#if 1 // FIXJASON ++//static volatile u32 *isp_vdos_width = (volatile u32*)(RIUBASE_ISP_0 + 0x6E*4); ++//static volatile u32 *isp_vdos_height = (volatile u32*)(RIUBASE_ISP_0 + 0x6F*4); ++ ++static volatile u32 *isp_vdos_pitch = (volatile u32*)(RIUBASE_ISP_6 + 0x21*4); ++static volatile u32 *isp_vdos_addr = (volatile u32*)(RIUBASE_ISP_6 + 0x28*4); ++#endif ++ ++ ++inline void HalISPMaskInt(void) { ++ *(u32*)isp_int_mask |= ++ *(u32*)isp_cpu_int; ++ *(u32*)isp_int_mask2 |= ++ (*(u32*)isp_cpu_int2 & 0x0f); ++ ++// printk(KERN_INFO "[ISP] %s(%d): mask 0x%04x, cpu 0x%04x, clear 0x%04x, force 0x%04x", __FUNCTION__, __LINE__, ++// *(u32*)isp_int_mask, ++// *(u32*)isp_cpu_int, ++// *(u32*)isp_int_clear, ++// *(u32*)isp_int_force); ++} ++ ++inline void HalISPDisableInt() { ++ *(volatile u32*)isp_int_mask = 0xffff; ++ *(volatile u32*)isp_int_mask2 = 0x000f; ++ *(volatile u32*)isp_int_clear = 0xffff; ++ *(volatile u32*)isp_int_clear2 = 0x000f; ++} ++ ++inline void HalISPEnableInt() { ++ *(volatile u32*)isp_int_mask = 0x000b; ++ *(volatile u32*)isp_int_mask2 = 0x0000; ++ *(volatile u32*)isp_int_clear = 0x000b; ++ *(volatile u32*)isp_int_clear2 = 0x0000; ++} ++ ++inline void HalISPMaskIntAll() { ++ *(volatile u32*)isp_int_mask = 0xffff; ++ *(volatile u32*)isp_int_mask2 = 0x000f; ++ ++ *(volatile u32*)isp_int_clear = 0xffff; ++ *(volatile u32*)isp_int_clear2 = 0x000f; ++} ++ ++ ++inline void HalISPMaskClear1(u32 clear) { ++ *(volatile u32*)isp_int_clear |= clear; ++ *(volatile u32*)isp_int_clear = 0x000b; ++ *(volatile u32*)isp_int_mask &= ~clear; ++ *(volatile u32*)isp_int_mask |= 0x000b; ++} ++inline void HalISPMaskClear2(u32 clear) { ++ *(volatile u32*)isp_int_clear2 |= clear; ++ *(volatile u32*)isp_int_clear2 = 0; ++ *(volatile u32*)isp_int_mask2 &= ~clear; ++} ++ ++inline void HalISPClearInt(volatile u32 *clear, ISP_INT_STATUS int_num) { ++ *clear |= (0x01<> VSYNC_BIT) & 0x01); ++} ++ ++inline u32 HalISPGetMIPI(void) { ++ return (*isp_sif) & 0x01; ++} ++ ++inline void HalISPGetAEStatSize(volatile int *size) { ++ *size = 0x40*4; ++} ++ ++inline void HalISPGetAEStat(volatile unsigned long *Stat) { ++ if (Stat) ++ memcpy((void *)Stat, (void *)isp_aests, 0x40*4); ++} ++ ++inline void HalISPGetAEHistSize(volatile int *size) { ++ *size = 0x40*4; ++} ++ ++inline void HalISPGetAEHist(volatile unsigned long *Stat) { ++ if (Stat) ++ memcpy((void *)Stat, (void *)isp_aehist, 0x40*4); ++} ++ ++inline void HalISPGetAWBStatSize(volatile int *size) { ++ if (size) ++ *size = 20*4; ++} ++ ++inline void HalISPGetAWBStat(volatile unsigned long *Stat) { ++ int i = 0; ++ unsigned long value = 0, LSB = 0, MSB = 0; ++// printk(KERN_INFO "[%s]", __FUNCTION__); ++// printk(KERN_INFO "u32 %d, long long %d", sizeof(u32), sizeof(long long)); ++ if (Stat) ++ for (i = 0; i < 20*2; i+=2) { ++ LSB = *(u32 *)(isp_awbsts+i)&0xffff; ++ MSB = *(u32 *)(isp_awbsts+(i+1))&0xffff; ++ value = LSB | (MSB << 16); ++// printk(KERN_INFO "Stat: 0x%04x 0x%04x:0x%04x 0x%04x:0x%04x", ++// (u32)value, ++// isp_awbsts+i, ++// LSB, //*(u32 *)(isp_awbsts+i)&0xffff, ++// isp_awbsts+(i+1), ++// MSB);//*(u32 *)(isp_awbsts+(i+1))&0xffff); ++ *((u32*)Stat+i/2) = value; ++ } ++} ++ ++inline void HalISPGetAFStatSize(volatile int *size) { ++ if (size) ++ *size = 15 * 4; ++} ++ ++inline void HalISPGetAFStat(volatile unsigned long *Stat) { ++ int i = 0; ++ unsigned long value = 0, LSB = 0, MSB = 0; ++ if (Stat) ++ for (i = 0; i < 15*2; i+=2) { ++ LSB = *(u32 *)(isp_afsts+i)&0xffff; ++ MSB = *(u32 *)(isp_afsts+(i+1))&0xffff; ++ value = LSB | (MSB << 16); ++ *(u32 *)(Stat+i/2) = value; ++ } ++} ++ ++#if 1 // FIXJASON ++//inline void HalISPGetVDOSWidth(volatile int *pWidth) { ++// if (pWidth) ++// *pWidth = *(int *)isp_vdos_width; ++//} ++ ++//inline void HalISPGetVDOSHight(volatile int *pHeight) { ++// if (pHeight) ++// *pHeight = *(int *)isp_vdos_height; ++//} ++ ++inline void HalISPGetVDOSPitch(volatile int *pPitch) { ++ if (pPitch) ++ *pPitch = *(int *)isp_vdos_pitch; ++} ++ ++inline void HalISPGetVDOSSize(volatile int *pSize, volatile int Pitch) { ++ if (pSize) ++ *pSize = Pitch * 24; // pitch * 3 * 8bytes ++} ++ ++inline void HalISPGetVDOSData(volatile unsigned long *pAddr, volatile int Size) { ++ if (pAddr) ++ memcpy((void *)pAddr, (void *)isp_vdos_addr, Size); ++} ++#endif ++ ++ ++ +diff --git a/drivers/mstar/isp/cedric/hal_isp.h b/drivers/mstar/isp/cedric/hal_isp.h +new file mode 100644 +index 00000000..fa2cd5e3 +--- /dev/null ++++ b/drivers/mstar/isp/cedric/hal_isp.h +@@ -0,0 +1,125 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef __HAL_ISP_H__ ++#define __HAL_ISP_H__ ++#include "ms_platform.h" ++/*--------------------------------------------------------------------------*/ ++/* INCLUDE FILE */ ++/*--------------------------------------------------------------------------*/ ++#define RIUBASE_ISP_OFFSET_0 (0xA8300<<2) ++#define RIUBASE_ISP_OFFSET_1 (0xA8380<<2) ++#define RIUBASE_ISP_OFFSET_2 (0xA8400<<2) ++#define RIUBASE_ISP_OFFSET_3 (0xA8480<<2) ++#define RIUBASE_ISP_OFFSET_4 (0xA8500<<2) ++#define RIUBASE_ISP_OFFSET_5 (0xA8580<<2) ++#define RIUBASE_ISP_OFFSET_6 (0xA8600<<2) ++#define RIUBASE_ISP_OFFSET_7 (0xA8680<<2) ++ ++#define INFINITY_MIU0_BASE 0x20000000 ++ ++#define IO_PHYS 0x1F000000 ++#define IO_VIRT (IO_PHYS+IO_OFFSET)//from IO_ADDRESS(x) ++#define IO_OFFSET (MS_IO_OFFSET) ++#define IO_SIZE 0x00400000 ++ ++#define RIUBASE_ISP_0 (IO_VIRT + RIUBASE_ISP_OFFSET_0) ++#define RIUBASE_ISP_1 (IO_VIRT + RIUBASE_ISP_OFFSET_1) ++#define RIUBASE_ISP_2 (IO_VIRT + RIUBASE_ISP_OFFSET_2) ++#define RIUBASE_ISP_3 (IO_VIRT + RIUBASE_ISP_OFFSET_3) ++#define RIUBASE_ISP_4 (IO_VIRT + RIUBASE_ISP_OFFSET_4) ++#define RIUBASE_ISP_5 (IO_VIRT + RIUBASE_ISP_OFFSET_5) ++#define RIUBASE_ISP_6 (IO_VIRT + RIUBASE_ISP_OFFSET_6) ++#define RIUBASE_ISP_7 (IO_VIRT + RIUBASE_ISP_OFFSET_7) ++ ++typedef enum { ++ INT_SR_VREF_RISING = 0, ++ INT_SR_VREF_FALLING = 1, ++ INT_STROBE_DONE = 2, ++ INT_DB_UPDATE_DONE = 3, ++ INT_AF_DONE = 4, ++ INT_ISP_FIFO_FULL = 5, ++ INT_ISP_BUSY = 6, ++ INT_ISP_IDLE = 7, ++ INT_AWB_DONE = 8, ++ INT_WDMA_DONE = 9, ++ INT_RDMA_DONE = 10, ++ INT_WDMA_FIFO_FULL = 11, ++ INT_PAD_VSYNC_RISING = 12, ++ INT_PAD_VSYNC_FALLING = 13, ++ INT_ISPIF_VSYNC = 14, ++ INT_AE_DONE = 15, ++} ISP_INT_STATUS; ++ ++typedef enum { ++ INT2_VDOS_EVERYLINE = 0, ++ INT2_VDOS_LINE0 = 1, ++ INT2_VDOS_LINE1 = 2, ++ INT2_VDOS_LINE2 = 3 ++} ISP_INT2_STATUS; ++ ++#define VSYNC_BIT 9 ++#define MIPI_BIT 0 ++#define ISP_CHECKBITS(a, b) ((a) & ((u32)0x01 << (b))) ++#define ISP_SETBIT(a, b) (a) |= (((u32)0x01 << (b))) ++#define ISP_CLEARBIT(a, b) (a) &= (~((u32)0x01 << (b))) ++ ++ ++void HalISPMaskInt(void); ++void HalISPMaskIntAll(void); ++ ++void HalISPDisableInt(void); ++ ++void HalISPEnableInt(void); ++ ++void HalISPMaskClear1(u32); ++void HalISPMaskClear2(u32); ++void HalISPClearInt(volatile u32 *clear, ISP_INT_STATUS int_num); ++void HalISPClearInt2(volatile u32 *clear, ISP_INT2_STATUS int_num); ++void HalISPClearMask(ISP_INT_STATUS int_num); ++void HalISPClearMask2(ISP_INT_STATUS int_num); ++void HalISPClearMaskAll(void); ++void HalISPClearIntAll(void); ++ ++void HalISPClkEnable(bool enable); ++u32 HalISPGetIntStatus(void); ++u32 HalISPGetIntStatus2(void); ++u32 HalISPGetRawInt(void); ++u32 HalISPGetVsyncPol(void); ++u32 HalISPGetMIPI(void); ++void HalISPGetAEStatSize(volatile int *size); ++void HalISPGetAEStat(volatile unsigned long *Stat); ++void HalISPGetAEHistSize(volatile int *size); ++void HalISPGetAEHist(volatile unsigned long *Stat); ++void HalISPGetAWBStatSize(volatile int *size); ++void HalISPGetAWBStat(volatile unsigned long *Stat); ++void HalISPGetAFStatSize(volatile int *size); ++void HalISPGetAFStat(volatile unsigned long *Stat); ++ ++#if 1 // FIXJASON ++//void HalISPGetVDOSWidth(volatile int *pWidth); ++//void HalISPGetVDOSHight(volatile int *pHeight); ++void HalISPGetVDOSPitch(volatile int *pPitch); ++void HalISPGetVDOSSize(volatile int *pSize, volatile int Pitch); ++void HalISPGetVDOSData(volatile unsigned long *pAddr, volatile int Size); ++#endif ++ ++ ++ ++#endif //__HAL_ISP_H__ ++ +diff --git a/drivers/mstar/isp/infinity/Makefile b/drivers/mstar/isp/infinity/Makefile +new file mode 100644 +index 00000000..3e95baa0 +--- /dev/null ++++ b/drivers/mstar/isp/infinity/Makefile +@@ -0,0 +1,13 @@ ++# ++# Makefile for MStar ISP drivers. ++# ++ ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Iarch/arm/include ++# # MsTypes.h ++EXTRA_CFLAGS += -Iinclude/linux ++ ++# files ++obj-$(CONFIG_MS_ISP_INFINITY) += hal_isp.o drv_isp.o i2c.o +diff --git a/drivers/mstar/isp/infinity/MsTypes.h b/drivers/mstar/isp/infinity/MsTypes.h +new file mode 100644 +index 00000000..f0945956 +--- /dev/null ++++ b/drivers/mstar/isp/infinity/MsTypes.h +@@ -0,0 +1,53 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __MS_TYPES_H__ ++#define __MS_TYPES_H__ ++ ++#include ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef U8 ++#define U8 u8 ++#endif ++ ++#ifndef U16 ++#define U16 u16 ++#endif ++ ++#ifndef U32 ++#define U32 u32 ++#endif ++ ++#if defined(__cplusplus) && defined(__GNUC__) && (__GNUC__>=4) && (__GNUC_MINOR__>=6) ++#define opaque_enum(e) enum e : int ++#else ++#define opaque_enum(e) enum e ++#endif ++#define typedef_opaque_enum(e1, e2) \ ++ opaque_enum(e1); \ ++ typedef enum e1 e2 ++ ++#endif ++ +diff --git a/drivers/mstar/isp/infinity/drv_isp.c b/drivers/mstar/isp/infinity/drv_isp.c +new file mode 100644 +index 00000000..dd88ba18 +--- /dev/null ++++ b/drivers/mstar/isp/infinity/drv_isp.c +@@ -0,0 +1,3124 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __DRV_ISP_C__ ++#define __DRV_ISP_C__ ++ ++#define ISP_DBG 0 ++#if ISP_DBG ++#define DEBUG ++#endif ++ ++/*--------------------------------------------------------------------------*/ ++/* INCLUDE FILE */ ++/*--------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++//#include ++#include ++ ++#include ++#include ++ ++#include "ms_msys.h" ++#include "hal_isp.h" ++#include "i2c.h" ++#include "../../gpio/mdrv_gpio.h" ++ ++/*--------------------------------------------------------------------------*/ ++ ++////////////////////////////////////////////////////////// ++ ++/*--------------------------------------------------------------------------*/ ++/* CONSTANT DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++//#define TIMMING_DBG_MSG ++ ++#if ISP_DBG ++#define DBG_INFO pr_debug ++#define DBG_INFO_1 pr_debug ++#define DBG_INFO_2 pr_debug ++#else ++#define DBG_INFO(fmt, arg...) {} ++#define DBG_INFO_1 DBG_INFO ++#define DBG_INFO_2 DBG_INFO ++#endif ++ ++/*--------------------------------------------------------------------------*/ ++/* MACRO DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++#define ISP_BIN_ATTR(_a,_b) \ ++ struct bin_attribute _a##_attr = { \ ++ .attr = { .name = __stringify(_a), \ ++ .mode = _b, }, \ ++ .size = 0, \ ++ .read = _a##_read, \ ++ .write = _a##_write, \ ++} ++ ++#define DEV_ATTR(_name,_mode,_size) \ ++ struct bin_attribute _name##_attr = { \ ++ .attr = { .name = __stringify(_name), \ ++ .mode = _mode, }, \ ++ .size = _size, \ ++ .read = _name##_read, \ ++ .write = _name##_write, \ ++} ++ ++#define C_IN(lock) local_irq_save(flags) ++#define C_OUT(lock) local_irq_restore(flags) ++ ++#define AE_RING_BUFF_NUM 3 ++#define AWB_RING_BUFF_NUM 3 ++#define AE_AWB_WIN_SIZE (128*90) ++#define AE_HIST_R_SIZE 80 ++#define AE_HIST_G_SIZE 80 ++#define AE_HIST_B_SIZE 80 ++#define AE_HIST_WIN0_SIZE 256 ++#define AE_HIST_WIN1_SIZE 256 ++//R,G,B,Y 4bytes statistics ++#define AE_STATIS_SIZE (AE_AWB_WIN_SIZE*4) ++#define AE_TOTAL_STATIS_SIZE (AE_HIST_R_SIZE+AE_HIST_G_SIZE+AE_HIST_B_SIZE+AE_HIST_WIN0_SIZE+AE_HIST_WIN1_SIZE+AE_STATIS_SIZE) ++ ++//Each row block's start address(Red) MUST be 16-byte align ++#define AWB_STATIS_SIZE (AE_AWB_WIN_SIZE*3) ++#define MOT_STATIS_SIZE (16*16*8) ++//#define DNR_FB_SIZE (((1920+191)/192) * ((1080+15)>>4) * 256 * 16) ++/*--------------------------------------------------------------------------*/ ++/* DATA TYPE DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++typedef struct { ++ unsigned int u4PhyAddr; ++ unsigned int u4VirAddr; ++ unsigned long u4Stat[9*2]; ++} EIS_STS_t; ++ ++typedef struct EIS_VDOS_t { ++ int width; ++ int height; ++ int pitch; ++ int size; ++ //int phyAddr; ++ //unsigned char data[5*1024*1024]; ++} eEIS_VDOS_t; ++ ++typedef enum ++{ ++ WDMA_SRC_BAYER_RAW = 0, ++ WDMA_SRC_ISP_OUTPUT_0 = 1, ++ WDMA_SRC_ISP_OUTPUT_1 = 2, ++ WDMA_SRC_ISP_VIDEO_STABILIZATION=3, ++}WDMA_SRC; ++ ++typedef enum ++{ ++ WDMA_REQ_WAIT = 0, ++ WDMA_REQ_PROC = 1, ++ WDMA_REQ_DONE = 2, ++}WDMA_REQ_STATUS; ++ ++typedef struct ++{ ++ u32 uSourceSel; ++ u32 uBufferPhysAddr; ++ u32 uReqStatus; //WDMA_SRC ++}__attribute__((packed, aligned(1))) WDMA_CFG; ++ ++#define ISP_STATUS_FRAME_DROP_ENABLE 0x01 ++typedef struct ++{ ++ u32 bActive; //Active data state ++ u32 u4FrameCnt; //frame count ++ u32 bIspInputEnable; ++ u32 u4OBCInValid; ++ u32 u4OBC_a; ++ u32 u4OBC_b; ++ u32 uIspStatusSet; // isp status set from user space ++ u32 uIspStatusReport; //isp satus get from kernel space ++ WDMA_CFG wdma_cfg; ++}__attribute__((packed, aligned(1))) FRAME_STATE; ++ ++#define I2C_RW_DONE 0 ++#define I2C_RW_WAIT 1 ++#define I2C_RW_ERROR 2 ++typedef struct ++{ ++ app_i2c_cfg cfg; ++ u32 status; ++ u32 num_i2c_data; //number of available i2c data in array ++ I2C_ARRAY i2c_data[16]; ++}__attribute__((packed, aligned(1))) ISP_K_I2C_RW; ++ ++typedef struct ++{ ++ FRAME_STATE frame_state; ++ ISP_K_I2C_RW i2c_rw; ++}__attribute__((packed, aligned(1))) ISP_SHARE_DATA; ++ ++typedef struct ++{ ++ u32 frame_interval; ++ u32 fps; ++ u32 prev_tick_count; ++}__attribute__((packed, aligned(1))) FPS_INFO; ++ ++typedef struct _isp_ccm_coff ++{ ++ s16 dirty; ++ s16 ccm[9]; ++}isp_ccm_coff; ++ ++typedef struct { ++ u32 frame_cnt; ++ u8 sysfs_int; ++ u8 vsync_start; ++ u8 vsync_end; ++ u8 ae; ++ u8 ae_win0; ++ u8 ae_row_int; ++ u8 awb; ++ u8 af; ++ u8 isp_busy; ++ u8 isp_idle; ++ u8 isp_fifofull; ++ u8 wdma_fifofull; ++ u8 rdma_done; ++ u8 wdma_done; ++ u8 eis; ++ u8 scl_fe; ++ ++ unsigned long AE_Lum[64]; // 8x8 windows ++ unsigned long AE_Hist[64]; // 8x8 windows ++ unsigned long AF_Stat[5*3]; // 5 windows *( R+G+B) ++ unsigned long AWB_Stat[80]; // 5 windows ++ ++ ++ //FRAME_STATE *FrameState; ++ ISP_SHARE_DATA *share_data; ++ ++ //eEIS_VDOS_t EIS_VDOS; ++ u32 isp_int_count[ISP_INT_MAX]; ++ u32 isp_int2_count[ISP_INT2_MAX]; ++ u32 isp_int3_count[ISP_INT3_MAX]; ++ ++ struct timespec isp_int_time[ISP_INT_MAX]; ++ struct timespec isp_int2_time[ISP_INT2_MAX]; ++ struct timespec isp_int3_time[ISP_INT3_MAX]; ++ ++ u8 hw_frame_cnt; ++ u32 int_cnt; ++ ++ FPS_INFO fps; ++ ++ isp_ccm_coff rgb_ccm; ++ isp_ccm_coff yuv_ccm; ++} ISP_INT_DATA; ++ ++typedef struct{ ++ u32 int_cnt; ++ u32 frame_interval; ++}ISP_IOCTL_INFO; ++ ++typedef struct { ++ char data[AE_AWB_WIN_SIZE]; ++ struct list_head list; ++ int status; ++}__attribute__((packed, aligned(1))) AWB_STATIS_DATA; ++ ++typedef struct ++{ ++ u32 data_offset; //offset to AE statistic data ++ u32 fcount; //frame count ++}__attribute__((packed, aligned(1))) ae_isr_data; ++ ++typedef struct ++{ ++ u32 data_offset; //offset to AWB statistic data ++ u32 fcount; //frame count ++}__attribute__((packed, aligned(1))) awb_isr_data; ++ ++ ++typedef struct { ++ void *pISPRegs[8]; ++ void *pCSIRegs; ++ MSYS_DMEM_INFO Base_Meminfo; ++ MSYS_DMEM_INFO DNR_FB_Meminfo[2]; ++ MSYS_DMEM_INFO ShareData_Meminfo; ++ //unsigned int AE_BuffNum; ++ //unsigned int AWB_BuffNum; ++ unsigned int AE_Size; ++ unsigned int AWB_Size; ++ unsigned int MOT_Size; ++ //volatile int AE_WriteIdx; ++ //volatile int AE_ReadIdx; ++ //volatile int AWB_WriteIdx; ++ //volatile int AWB_ReadIdx; ++ volatile u8 IsWriteIQtbl; ++ ++ //unsigned long AE_Offset[AE_RING_BUFF_NUM]; ++ // unsigned long AWB_Offset[AWB_RING_BUFF_NUM]; ++ unsigned long AE_Offset; ++ unsigned long AWB_Offset; ++ unsigned long IQ_tblOffset[IQ_MEM_NUM]; ++ unsigned int IQ_tblSize[IQ_MEM_NUM]; ++ unsigned int MOT_Offset; ++} ISP_MEM_BUFF; ++ ++typedef enum ++{ ++ ISP_INFO_ID_AE=0, ++ ISP_INFO_ID_AWB, ++ ISP_INFO_ID_IQ, ++ ISP_INFO_ID_MAX, ++}ISP_INFO_ID; ++ ++typedef struct _isp_dev_data ++{ ++ struct miscdevice isp_dev; ++ struct device * sysfs_dev; //for node /sys/class/mstar/ ++ struct clk *clk_isp; //isp clock ++ struct clk *clk_sr; //pclk ++ struct clk *clk_sr_mclk; //sensor mclk ++ struct clk *clk_csi_mac; ++ ISP_INT_DATA *isp_int; ++ ISP_MEM_BUFF *isp_mem; ++ char isp_info_str[ISP_INFO_ID_MAX][1024]; ++}isp_dev_data; ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++static ISP_INT_DATA isp_int; ++static ISP_MEM_BUFF isp_mem; ++//static i2c_handle_t isp_i2c; ++ ++// ISP watchdog timer ++#define MAX_WATCHDOG_TIME (5) ++#define WATCHDOG_KICK (99) ++#define WATCHDOG_STOP (88) ++#define WATCHDOG_UPDATE (77) ++static struct timer_list isp_watchdog_timer; ++atomic_t isp_watchdog_counter = ATOMIC_INIT(0); ++static unsigned int isp_watchdog_update_counter = 0; ++DEFINE_SPINLOCK(isp_watchdog_lock); ++ ++void isp_watchdog_callback( unsigned long data ) ++{ ++ atomic_dec(&isp_watchdog_counter); ++ ++ // disable ISP HW ++ if(atomic_read(&isp_watchdog_counter) == 0) { ++ pr_err("watchdog timeout and disable ISP HW\n"); ++ IspDisable(); ++ } ++ ++ // kick timer until counter is 0 ++ if(atomic_read(&isp_watchdog_counter) > 0) ++ mod_timer( &isp_watchdog_timer, jiffies + msecs_to_jiffies(1000) ); ++} ++ ++void reset_isp_int(ISP_INT_DATA *p_isp_int) //reset isp_int struct ++{ ++ //p_isp_int->frame_cnt = 0; ++ p_isp_int->sysfs_int = 0; ++ p_isp_int->vsync_start = 0; ++ p_isp_int->vsync_end = 0; ++ p_isp_int->ae = 0; ++ p_isp_int->ae_win0 = 0; ++ p_isp_int->awb = 0; ++ p_isp_int->af = 0; ++ p_isp_int->isp_busy = 0; ++ p_isp_int->isp_idle = 0; ++ p_isp_int->isp_fifofull = 0; ++ p_isp_int->wdma_fifofull = 0; ++ p_isp_int->rdma_done = 0; ++ p_isp_int->wdma_done = 0; ++ p_isp_int->eis = 0; ++ ++ memset(p_isp_int->AE_Lum,0,sizeof(unsigned long)*64); ++ memset(p_isp_int->AE_Hist,0,sizeof(unsigned long)*64); ++ memset(p_isp_int->AF_Stat,0,sizeof(unsigned long)*60); ++ memset(p_isp_int->AWB_Stat,0,sizeof(unsigned long)*80); ++ //memset(&p_isp_int->EIS_VDOS,0,sizeof(eEIS_VDOS_t)); ++ ++ p_isp_int->share_data->frame_state.bIspInputEnable = true; ++} ++ ++void isp_enable_input(u32 enable) ++{ ++ if(enable) ++ { ++ isp_int.share_data->frame_state.bIspInputEnable = true; ++ IspInputEnable(enable); ++ } ++ else ++ {//do not disable input immediately , to disable isp input when frame blanking (vsync end interrupt) ++ isp_int.share_data->frame_state.bIspInputEnable = false; ++ } ++} ++#if 1 ++void isp_async(u32 enable) ++{ ++ IspAsyncEnable(enable); ++} ++ ++void fps_init(FPS_INFO *info) ++{ ++ memset(info,sizeof(FPS_INFO),0); ++} ++ ++u32 fps_update(FPS_INFO *info) ++{ ++ u32 dt; ++ struct timespec ts; ++ getnstimeofday(&ts); ++ ++ if(ts.tv_nsec>info->prev_tick_count) ++ { ++ dt = ts.tv_nsec - info->prev_tick_count; ++ } ++ else ++ { ++ dt = 0xFFFFFFFF - info->prev_tick_count + ts.tv_nsec; ++ } ++ ++ if(dt<1000000*500) //dt < 500ms ++ { ++ info->frame_interval = dt; ++ } ++ ++ info->prev_tick_count = ts.tv_nsec; ++ info->fps = 1000000000/dt; ++ return info->fps; ++} ++ ++#ifdef TIMMING_DBG_MSG ++void print_timestamp(char* msg) ++{ ++ struct timespec ts; ++ getnstimeofday(&ts); ++ printk("%d:%lu:%s\r\n", isp_int.frame_cnt, (ts.tv_sec * 1000000)+(ts.tv_nsec/1000), msg); ++} ++#else ++#define print_timestamp(a) ++#endif ++ ++#endif ++ ++typedef struct ++{ ++ u64 count; ++ spinlock_t lock; ++ u8 frame_end; //frame end interrupt flag ++ u8 frame_start; ++ ++ u32 fs_int_count; //frame start interrput count ++ u32 vc0_int_count; //virtual channel 0 count ++ ++ wait_queue_head_t *p_wq_fe; ++ wait_queue_head_t *p_wq_fs; ++ ++ //HAL ++ void* reg_base; ++ void* hal_handle; ++ ++ u32 csi_err_int_count[CSI_ERR_INT_MAX]; ++ struct device *sysfs_dev; ++}csi_dev_data; ++ ++/*--------------------------------------------------------------------------*/ ++/* VARIABLE DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++irqreturn_t isp_ISR(int num, void *priv); ++static int isp_probe(struct platform_device* pdev); ++static int isp_remove(struct platform_device* pdev ); ++static int isp_suspend(struct platform_device *pdev, pm_message_t state); ++static int isp_resume(struct platform_device *pdev); ++int isp_create_bin_file(struct device *dev); ++int isp_create_bin_file_(struct device *dev); ++ ++static struct of_device_id isp_dt_ids[] = { ++ {.compatible = "isp"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, isp_dt_ids); ++ ++irqreturn_t csi_ISR(int num, void *priv); ++static int csi_probe(struct platform_device* pdev); ++static int csi_remove(struct platform_device* pdev ); ++static int csi_suspend(struct platform_device *pdev, pm_message_t state); ++static int csi_resume(struct platform_device *pdev); ++ ++static struct of_device_id csi_dt_ids[] = { ++ {.compatible = "csi"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, csi_dt_ids); ++ ++static struct platform_device *isp_device; ++ ++static struct platform_driver isp_driver = ++{ ++ .probe = isp_probe, ++ .remove = isp_remove, ++ .suspend = isp_suspend, ++ .resume = isp_resume, ++ .driver = { ++ .name = "isp", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(isp_dt_ids), ++ }, ++}; ++ ++static struct platform_driver csi_driver = ++{ ++ .probe = csi_probe, ++ .remove = csi_remove, ++ .suspend = csi_suspend, ++ .resume = csi_resume, ++ .driver = { ++ .name = "csi", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(csi_dt_ids), ++ }, ++}; ++ ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_WDMA_FIFO_FULL); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_FIFO_FULL); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_RDMA_DONE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_WDMA_DONE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_IDLE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_BUSY); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_VSTART); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_VEND); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae_win0); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae_win1); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae_row_int); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_awb); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_af); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_eis); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_sw_int_in); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_sw_int_out); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_scl_fe); ++ ++//CSI// ++static DECLARE_WAIT_QUEUE_HEAD(csi_wq_fe); ++static DECLARE_WAIT_QUEUE_HEAD(csi_wq_fs); ++ ++static struct kobject *kobj_isp = NULL; ++ ++ ++/*--------------------------------------------------------------------------*/ ++/* LOCAL FUNCTION PROTOTYPE DECLARATION AND DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++extern int msys_request_dmem(MSYS_DMEM_INFO *mem_info); ++#if 0 ++unsigned short pPGscript[][3]={ {1, 0x0018, 0x03e4 }, ++ {0, 0x0118, 0x3ba6 }, ++ {0, 0x011C, 0x0e36 }, ++ {1, 0x0000, 0x003b }, ++ {1, 0x0014, 0x0438 }, ++ {1, 0x0020, 0x04b1 }, ++ {1, 0x0024, 0x00e5 }, ++ {1, 0x0028, 0x08fc }, ++ {1, 0x002C, 0x0078 }, ++ {1, 0x0030, 0x0671 }, ++ {1, 0x0034, 0xffe7 }, ++ {1, 0x0038, 0x08ef }, ++ {1, 0x003C, 0xffb2 }, ++ {1, 0x0004, 0x03f2 }, ++ {1, 0x0008, 0x02bf }, ++ {1, 0x000C, 0x0001 }, ++ {1, 0x0010, 0x0000 }, ++ {1, 0x0040, 0x4f7c }, ++ {1, 0x0044, 0x8b60 }, ++ {1, 0x0048, 0x5b85 }, ++ {1, 0x004C, 0xc117 }, ++ {1, 0x0050, 0x8c5c }, ++ {1, 0x0054, 0x2967 }, ++ {1, 0x0058, 0xfbbf }, ++ {1, 0x005C, 0x6bbe }, ++ {1, 0x0060, 0xbd18 }, ++ {1, 0x0064, 0xbe21 }, ++ {1, 0x0068, 0x491f }, ++ {1, 0x006C, 0x6905 }, ++ {1, 0x0070, 0x4cc9 }, ++ {1, 0x0074, 0xa03d }, ++ {1, 0x0078, 0x4f24 }, ++ {1, 0x007C, 0x17ff }, ++ {1, 0x0080, 0x859c }, ++ {1, 0x0084, 0xb985 }, ++ {1, 0x0088, 0x4fd5 }, ++ {1, 0x008C, 0x5130 }, ++ {1, 0x0090, 0x49f7 }, ++ {1, 0x0094, 0x4f94 }, ++ {1, 0x0098, 0x3f23 }, ++ {1, 0x009C, 0xf8de }, ++ {1, 0x00A0, 0xa66a }, ++ {1, 0x00A4, 0xb0cc }, ++ {1, 0x00A8, 0x3245 }, ++ {1, 0x00AC, 0xf117 }, ++ {1, 0x00B0, 0x144b }, ++ {1, 0x00B4, 0x3e8b }, ++ {1, 0x00B8, 0xb33b }, ++ {1, 0x00BC, 0xd409 }, ++ {1, 0x00C0, 0x0154 }, ++ {1, 0x00C4, 0x7df2 }, ++ {1, 0x00C8, 0x418f }, ++ {1, 0x00CC, 0x0f85 }, ++ {1, 0x00D0, 0x5070 }, ++ {1, 0x00D4, 0x6b92 }, ++ {1, 0x00D8, 0x46c7 }, ++ {1, 0x00DC, 0xae71 }, ++ {1, 0x00E0, 0xe421 }, ++ {1, 0x00E4, 0x8a81 }, ++ {1, 0x00E8, 0xc88e }, ++ {1, 0x00EC, 0xcc36 }, ++ {1, 0x00F0, 0x9e25 }, ++ {1, 0x00F4, 0xd7b0 }, ++ {1, 0x00F8, 0x7f37 }, ++ {1, 0x00FC, 0x2263 }, ++ {1, 0x01A0, 0x0080 }, ++ {1, 0x01E4, 0x0800 }, ++ {1, 0x01E8, 0x0901 }, ++ {1, 0x01EC, 0x68f5 }, ++ {1, 0x01F0, 0x0036 }, ++ {1, 0x0120, 0x0000 }, ++ {1, 0x0124, 0x0004 }, ++ {1, 0x0128, 0x0017 }, ++ {1, 0x012C, 0x001d }, ++ {1, 0x0130, 0x0735 }, ++ {1, 0x0134, 0x042e }, ++ {1, 0x0100, 0x0102 }, ++ {1, 0x0104, 0x0064 }, ++ {1, 0x01C0, 0xac00 }, ++ {1, 0x01C4, 0x0001 }, ++ {1, 0x01C8, 0x00fa }, ++ {1, 0x01CC, 0xe428 }, ++ {1, 0x01D0, 0x5a30 }, ++ {1, 0x01D4, 0x67ca }, ++ {1, 0x01D8, 0x0000 }, ++ {1, 0x01DC, 0x002d }, ++ {1, 0x01E0, 0x0093 }, ++ {3, 0x0000, 0x200d },//0x200d },//Statistics disable ++ {3, 0x0004, 0x0b0e }, ++ {3, 0x0008, 0x4154 }, ++ {3, 0x000C, 0x0555 }, ++ {3, 0x0010, 0x0618 }, ++ {3, 0x0014, 0x02d8 }, ++ {3, 0x0018, 0x8070 }, ++ {3, 0x001C, 0x000c }, ++ {3, 0x0020, 0x7800 }, ++ {3, 0x0024, 0x000c }, ++ {3, 0x0028, 0x0f06 }, ++ {3, 0x002C, 0x2302 }, ++ {3, 0x0030, 0x3c0d }, ++ {3, 0x0034, 0x0f04 }, ++ {3, 0x0080, 0x1002 }, ++ {3, 0x0084, 0x0000 }, ++ {3, 0x0088, 0x0000 }, ++ {3, 0x008C, 0x443c }, ++ {3, 0x0090, 0x003d }, ++ {3, 0x00C0, 0x3152 }, ++ {3, 0x00C4, 0x3337 }, ++ {3, 0x00C8, 0xba78 }, ++ {3, 0x00CC, 0x040f }, ++ {3, 0x00D0, 0x6bbc }, ++ {3, 0x00D4, 0x59cf }, ++ {3, 0x00D8, 0x72a5 }, ++ {3, 0x00DC, 0x713a }, ++ {3, 0x00E0, 0xfc00 }, ++ {3, 0x00E4, 0x0003 }, ++ {3, 0x00E8, 0x1c00 }, ++ {3, 0x00EC, 0x0006 }, ++ {3, 0x00F0, 0x1887 }, ++ {3, 0x00F4, 0x7b00 }, ++ {3, 0x00F8, 0x8bdf }, ++ {3, 0x00FC, 0x000c }, ++ {3, 0x0108, 0x0004 }, ++ {3, 0x010C, 0x001e }, ++ {5, 0x0000, 0x0001 }, ++ {5, 0x0008, 0x002f }, ++ {5, 0x000C, 0x0024 }, ++ {5, 0x0010, 0x001e }, ++ {5, 0x0014, 0x0004 }, ++ {5, 0x0018, 0x0043 }, ++ {5, 0x001C, 0x0068 }, ++ {5, 0x0020, 0x002b }, ++ {5, 0x0024, 0x002f }, ++ {5, 0x0028, 0x01d4 }, ++ {5, 0x002C, 0x002b }, ++ {5, 0x0030, 0x0007 }, ++ {5, 0x0034, 0x0007 }, ++ {5, 0x0038, 0x0074 }, ++ {5, 0x003C, 0x00a9 }, ++ {5, 0x0040, 0x001e }, ++ {5, 0x0044, 0x0064 }, ++ {5, 0x0048, 0x0200 }, ++ {5, 0x004C, 0x0200 }, ++ {5, 0x0050, 0x00d5 }, ++ {5, 0x0054, 0x011e }, ++ {0, 0x00C8, 0x0000 }, ++ {0, 0x00CC, 0x0400 }, ++ {0, 0x00D0, 0x0000 }, ++ {0, 0x00D4, 0x0000 }, ++ {0, 0x00D8, 0x0000 }, ++ {0, 0x00DC, 0x0400 }, ++ {0, 0x00E0, 0x0000 }, ++ {0, 0x00E4, 0x0000 }, ++ {0, 0x00E8, 0x0000 }, ++ {0, 0x00EC, 0x0400 }, ++ {0, 0x00F0, 0x0191 }, ++ {0, 0x00F4, 0x01c2 }, ++ {0, 0x00F8, 0x1e87 }, ++ {0, 0x00FC, 0x1fb7 }, ++ {0, 0x0100, 0x0107 }, ++ {0, 0x0104, 0x0204 }, ++ {0, 0x0108, 0x0064 }, ++ {0, 0x010C, 0x1f68 }, ++ {0, 0x0110, 0x1ed6 }, ++ {0, 0x0114, 0x01c2 }, ++ {0, 0x00C0, 0x0004 }, ++ {0, 0x0180, 0x0001 }, ++ {0, 0x01C4, 0x0d07 }, ++ {0, 0x01C8, 0x2701 }, ++ {0, 0x01CC, 0x040d }, ++ {0, 0x01C0, 0x5601 }, ++ {0, 0x01A8, 0x0010 }, ++ {0, 0x01AC, 0x0003 }, ++ {0, 0x01B0, 0x0003 }, ++ {0, 0x01B4, 0x0002 }, ++ {0, 0x01B8, 0x000c }, ++ {0, 0x01BC, 0x0007 }, ++ {7, 0x0004, 0x04ff }, ++ {7, 0x0008, 0x031f }, ++ {7, 0x000C, 0x0106 }, ++ {7, 0x0010, 0x2864 }, ++ {7, 0x0014, 0x001f }, ++ {7, 0x0018, 0x000f }, ++ {7, 0x001C, 0x0000 }, ++ {7, 0x0020, 0x0000 }, ++ {7, 0x0000, 0x0003 }, ++ {0, 0x0010, 0x0210 }, ++ {0, 0x0040, 0x1700 }, ++ {0, 0x0044, 0x0000 }, ++ {0, 0x0048, 0x0000 }, ++ {0, 0x004C, 0x0000 }, ++ {0, 0x0050, 0x04ff }, ++ {0, 0x0054, 0x031f }, ++ {0, 0x0068, 0x0001 }, ++ {0, 0x0198, 0x0088 }, ++ {0, 0x0004, 0x8103 }, ++ {0, 0x0008, 0xc000 }, ++ {0, 0x0000, 0x0001 }, ++ {0, 0x0058, 0x0000 }, ++ {0, 0x005C, 0x0000 }, ++ {0, 0x0060, 0x04ff }, ++ {0, 0x0064, 0x031f }, ++ {6, 0x0080, 0x0291 },//0x0291 },//WDMA disable ++ {6, 0x0084, 0x00a0 }, ++ {6, 0x00A0, 0x7c00 }, ++ {6, 0x00A4, 0x0008 }, ++ {6, 0x00B0, 0x08f0 }, ++ {6, 0x00C0, 0x0100 }, ++ {6, 0x0000, 0x0300 }, ++ {6, 0x0004, 0x0078 }, ++ {6, 0x0020, 0x0000 }, ++ {6, 0x0024, 0x0000 }, ++ {6, 0x0030, 0x01f4 }, ++ {6, 0x0034, 0x003f }, ++ {6, 0x0040, 0x0000 }}; ++ ++ ++static int isp_testscript(void) ++{ ++ unsigned int script_len, i, value; ++ unsigned int *address; ++ //MSYS_DMEM_INFO raw_meminfo; ++ //unsigned long ae_phyaddr, awb_phyaddr, u4PhyAddr; ++ //unsigned long long ae_viraddr, awb_viraddr; ++ ++ printk(KERN_INFO "[ISP]: test script\n"); ++ ++ //raw_meminfo.length = 1280*800*2; ++ //msys_request_dmem(&raw_meminfo); ++ ++ //ae_phyaddr = (unsigned long)isp_mem.Base_Meminfo.phys + isp_mem.AE_Offset[0]; ++ //awb_phyaddr = (unsigned long)isp_mem.Base_Meminfo.phys + isp_mem.AWB_Offset[0]; ++ //ae_viraddr = isp_mem.Base_Meminfo.kvirt+ isp_mem.AE_Offset[0]; ++ //awb_viraddr = isp_mem.Base_Meminfo.kvirt + isp_mem.AWB_Offset[0]; ++ ++ //u4PhyAddr = raw_meminfo.phys; ++ //u4VirAddr = raw_meminfo.kvirt; ++ ++ //printk(KERN_INFO "[ISP]: raw address phyiscal = 0x%08x, virtual = 0x%08x\n", u4PhyAddr, u4VirAddr); ++ //printk(KERN_INFO "[ISP]: ae address phyiscal = 0x%08x, virtual64 = 0x%llx\n", ae_phyaddr, ae_viraddr); ++ //printk(KERN_INFO "[ISP]: awb address phyiscal = 0x%08x, virtual64 = 0x%llx\n", awb_phyaddr, awb_viraddr); ++ ++ script_len = sizeof(pPGscript)/(sizeof(unsigned short)*3); ++ ++ printk(KERN_INFO "[ISP]: script length = %d\n", script_len); ++ for (i = 0; i < script_len; i++) { ++ ++ address = (unsigned int*)(isp_mem.pISPRegs[pPGscript[i][0]] + pPGscript[i][1]); ++ ++ if(pPGscript[i][0] == 3 && pPGscript[i][1] == 0x0018) { ++ ++ //u4PhyAddr = ae_phyaddr; ++ value = (0x281F4000>>4) & 0xFFFF;//(0x281F4000>>4) & 0xFFFF;//(u4PhyAddr>>4) & 0xFFFF; ++ ++ printk(KERN_INFO "[ISP]: wdma base_L = 0x%08x\n", value); ++ ++ } ++ else if(pPGscript[i][0] == 3 && pPGscript[i][1] == 0x001C) { ++ //u4PhyAddr = ae_phyaddr; ++ value = (0x281F4000>>20) & 0xFFFF;//(0x281F4000>>20) & 0xFFFF;//(u4PhyAddr>>20) & 0xFFFF; ++ printk(KERN_INFO "[ISP]: wdma base_H = 0x%08x\n", value); ++ ++ } ++ else if(pPGscript[i][0] == 3 && pPGscript[i][1] == 0x0020) { ++ ++ //u4PhyAddr = awb_phyaddr; ++ value = (0x281FF6F0>>4) & 0xFFFF;//(0x281FF6F0>>4) & 0xFFFF;//(u4PhyAddr>>4) & 0xFFFF; ++ ++ printk(KERN_INFO "[ISP]: wdma base_L = 0x%08x\n", value); ++ ++ } ++ else if(pPGscript[i][0] == 3 && pPGscript[i][1] == 0x0024) { ++ //u4PhyAddr = awb_phyaddr; ++ value = (0x281FF6F0>>20) & 0xFFFF;//(0x281FF6F0>>20) & 0xFFFF;//(u4PhyAddr>>20) & 0xFFFF; ++ printk(KERN_INFO "[ISP]: wdma base_H = 0x%08x\n", value); ++ ++ } ++ else if(pPGscript[i][0] == 6 && pPGscript[i][1] == 0x00A0) { ++ //u4PhyAddr = raw_meminfo.phys; ++ value = (0x28000000>>4) & 0xFFFF;//(0x28000000>>4) & 0xFFFF;//(u4PhyAddr>>4) & 0xFFFF; ++ ++ printk(KERN_INFO "[ISP]: wdma base_L = 0x%08x\n", value); ++ ++ } ++ else if(pPGscript[i][0] == 6 && pPGscript[i][1] == 0x00A4) { ++ //u4PhyAddr = raw_meminfo.phys; ++ value = (0x28000000>>20) & 0xFFFF;//(0x28000000>>20) & 0xFFFF;//(u4PhyAddr>>20) & 0xFFFF; ++ printk(KERN_INFO "[ISP]: wdma base_H = 0x%08x\n", value); ++ ++ } ++ else { ++ value = pPGscript[i][2]; ++ } ++ ++ //printk(KERN_INFO "[ISP]: script %d addr:0x%08x value:0x%04x\n", i, (unsigned int)address, value); ++ ++ *address = value; ++ ++ } ++ ++ ++ return 0; ++} ++#endif ++ ++#if 0 ++static void isp_write_iq_tbl(void) ++{ ++ if(isp_mem.IsWriteIQtbl == 1){ ++ HalISPMLoadWriteAllTable((unsigned long)isp_mem.Base_Meminfo.phys, isp_mem.IQ_tblOffset); ++ //HalISPMLoadWriteData(IQ_MEM_ALSC_RGAIN, isp_mem.Base_Meminfo.phys+isp_mem.IQ_tblOffset[IQ_MEM_ALSC_RGAIN]); ++ isp_mem.IsWriteIQtbl = 0; ++ } ++ ++} ++#endif ++ ++static void isp_ae_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + isp_mem.AE_Offset,isp_mem.AE_Size); ++} ++ ++static int isp_set_ae_base(void) ++{ ++ u32 phy_addr; ++ u32 virt_addr; ++ ++ phy_addr = (unsigned long)isp_mem.Base_Meminfo.phys + isp_mem.AE_Offset; ++ virt_addr = (unsigned long)isp_mem.Base_Meminfo.kvirt + isp_mem.AE_Offset; ++ ++ DBG_INFO("ISP_BASE = 0x%X, AE offset = 0x%X\n",(unsigned int)isp_mem.Base_Meminfo.phys,(unsigned int)isp_mem.AE_Offset); ++ HalISPSetAeBaseAddr(phy_addr); ++ ++ return 0; ++} ++ ++static void isp_awb_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + isp_mem.AWB_Offset,isp_mem.AWB_Size); ++} ++ ++static int isp_set_awb_base(void) ++{ ++ u32 phy_addr; ++ u32 virt_addr; ++ ++ phy_addr = (unsigned long)isp_mem.Base_Meminfo.phys + isp_mem.AWB_Offset; ++ virt_addr = (unsigned long)isp_mem.Base_Meminfo.kvirt + isp_mem.AWB_Offset; ++ ++ DBG_INFO("set awb_base[%d]:0x%08x , virt = 0x%.8X", isp_mem.AWB_WriteIdx, phy_addr, virt_addr); ++ HalISPSetAwbBaseAddr(phy_addr); ++ ++ return 0; ++} ++ ++static int isp_set_mot_base(void) ++{ ++ u32 phys_addr; ++ phys_addr = (unsigned long)isp_mem.Base_Meminfo.phys + isp_mem.MOT_Offset; ++ HalISPSetMotBaseAddr(phys_addr); ++ return 0; ++} ++ ++#if 1 ++//set DNR frame buffer address ++static int isp_set_dnr_fb_base(MSYS_DMEM_INFO *mem_info,int id) ++{ ++ u32 phys_addr; ++ phys_addr = (unsigned long)mem_info->phys; ++ DBG_INFO("DNR_%d PHYS=0x%llX,VIRT=0x%llX\n",id,mem_info->phys,mem_info->kvirt); ++ HalISPSetDnrFbAddr(phys_addr,id); ++ return 0; ++} ++#endif ++ ++static u32 isp_get16bytes_size(u32 size) ++{ ++ u32 result_size; ++ result_size = ((size%16)==0)?size:(size/16 + 1)*16; ++ return result_size; ++} ++ ++#if 0 ++extern MS_PACKAGE_TYPE Chip_Get_Package_Type(void); ++static unsigned int get_dnr_buffer_size(void) ++{ ++ MS_PACKAGE_TYPE pkg_type = 0;//Chip_Get_Package_Type(); ++ unsigned int img_w; ++ unsigned int img_h; ++ ++#if 0 // 1 to use /Chip_Get_Package_Type() ++ pkg_type = Chip_Get_Package_Type(); ++#else ++ extern unsigned long totalram_pages; ++ pr_debug("\n\n SYSTEM Total Pages = 0x%X \n\n",(unsigned int)totalram_pages); ++ if(totalram_pages > 0x4000) //if DRAM size > 64MB ++ pkg_type = MS_PACKAGE_BGA; ++ else ++ pkg_type = MS_PACKAGE_QFP; ++#endif ++ ++ switch(pkg_type) ++ { ++ case MS_PACKAGE_QFP: ++ img_w = 1280; ++ img_h = 720; ++ return img_w*img_h*2; ++ break; ++ default: ++ case MS_PACKAGE_BGA: ++ img_w = 1920; ++ img_h = 1088; ++ return (((img_w+191)/192) * ((img_h+15)>>4) * 256 * 16); ++ break; ++ } ++} ++#else ++long g_isp_flag = ISP_FLAG_ENABLE_ROT | ISP_FLAG_ENABLE_DNR; ++long g_isp_max_res = 1; //max resolutioin, 0:1280x720 1:1920x1080 ++static unsigned int get_dnr_buffer_size(void) ++{ ++ u32 width = 1920; ++ u32 height = 1080; ++ switch(g_isp_max_res) ++ { ++ case 0: //1270x720 ++ width = 1280; ++ height = 720; ++ break; ++ case 1://1920x1080 ++ width = 1920; ++ height = 1080; ++ break; ++ } ++ pr_info("[ISP] max_res= %dx%d\n",width,height); ++ return (((width+191)/192) * ((height+15)>>4) * 256 * 16); ++} ++static unsigned int get_dnr_buffer_num(void) ++{ ++ if(g_isp_flag&ISP_FLAG_ENABLE_DNR) ++ { ++ return (g_isp_flag&ISP_FLAG_ENABLE_ROT)?2:1; ++ } ++ else ++ return 0; ++} ++#endif ++ ++static int isp_init_buff(void) { ++ int i, base; ++ pr_debug("[ISP] isp_init_buff\n"); ++ ++ //isp_mem.AE_BuffNum = AE_RING_BUFF_NUM; ++ isp_mem.AE_Size = AE_TOTAL_STATIS_SIZE; ++ //isp_mem.AWB_BuffNum = AWB_RING_BUFF_NUM; ++ isp_mem.AWB_Size = AWB_STATIS_SIZE; ++ isp_mem.MOT_Size = MOT_STATIS_SIZE; ++ ++ isp_mem.IQ_tblSize[IQ_MEM_ALSC_RGAIN] = isp_get16bytes_size(IQ_LEN_ALSC_GAIN)* 2;//IQ_LEN_ALSC_GAIN*2; ++ isp_mem.IQ_tblSize[IQ_MEM_ALSC_GGAIN] = isp_get16bytes_size(IQ_LEN_ALSC_GAIN)* 2;//IQ_LEN_ALSC_GAIN*2; ++ isp_mem.IQ_tblSize[IQ_MEM_ALSC_BGAIN] = isp_get16bytes_size(IQ_LEN_ALSC_GAIN)* 2;//IQ_LEN_ALSC_GAIN*2; ++ ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA12TO10_RTBL] = IQ_LEN_GAMMA_12TO10*2; ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA12TO10_GTBL] = IQ_LEN_GAMMA_12TO10*2; ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA12TO10_BTBL] = IQ_LEN_GAMMA_12TO10*2; ++ ++ isp_mem.IQ_tblSize[IQ_MEM_DEFECT_PIXEL_POS] = IQ_LEN_DEFECT_PIXEL*2; ++ ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA10TO12_RTBL] = IQ_LEN_GAMMA_10TO12*2; ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA10TO12_GTBL] = IQ_LEN_GAMMA_10TO12*2; ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA10TO12_BTBL] = IQ_LEN_GAMMA_10TO12*2; ++ ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA_CORR_RTBL] = IQ_LEN_GAMMA_CORRECT*2; ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA_CORR_GTBL] = IQ_LEN_GAMMA_CORRECT*2; ++ isp_mem.IQ_tblSize[IQ_MEM_GAMMA_CORR_BTBL] = IQ_LEN_GAMMA_CORRECT*2; ++ ++ ++ isp_mem.Base_Meminfo.length = isp_mem.AE_Size; ++ isp_mem.Base_Meminfo.length +=isp_mem.AWB_Size; ++ isp_mem.Base_Meminfo.length += isp_mem.MOT_Size; ++ ++ DBG_INFO("isp ae_size: %d, awb_size: %d", isp_mem.AE_Size, isp_mem.AWB_Size); ++ ++ for (i = 0; i < IQ_MEM_NUM; i++) { ++ isp_mem.Base_Meminfo.length += isp_mem.IQ_tblSize[i]; ++ } ++ sprintf(isp_mem.Base_Meminfo.name,"ISP_base"); ++ msys_request_dmem(&isp_mem.Base_Meminfo); ++ ++ DBG_INFO("mem base phyaddr:0x%08x, viraddr:0x%08x, len:%d", (unsigned int)isp_mem.Base_Meminfo.phys, ++ (unsigned int)isp_mem.Base_Meminfo.kvirt,isp_mem.Base_Meminfo.length); ++ ++ ////////// isp share data //////////////// ++ sprintf(isp_mem.ShareData_Meminfo.name, "ISP_SHARE_DATA"); ++#if 0 ++ isp_mem.ShareData_Meminfo.length = sizeof(ISP_SHARE_DATA); ++ msys_request_dmem(&isp_mem.ShareData_Meminfo); ++ isp_int.share_data = (ISP_SHARE_DATA *)((u32)isp_mem.ShareData_Meminfo.kvirt); ++#else ++ isp_int.share_data = kmalloc(sizeof(ISP_SHARE_DATA),GFP_KERNEL); ++ isp_mem.ShareData_Meminfo.kvirt = (unsigned long)isp_int.share_data; ++ isp_mem.ShareData_Meminfo.phys = virt_to_phys(isp_int.share_data); ++ isp_mem.ShareData_Meminfo.length = sizeof(ISP_SHARE_DATA); ++ ++ DBG_INFO("FrameState phyaddr:0x%08llx, viraddr:0x%08llx, len:%#x\n", ++ isp_mem.ShareData_Meminfo.phys, ++ isp_mem.ShareData_Meminfo.kvirt, isp_mem.ShareData_Meminfo.length); ++#endif ++ ++ DBG_INFO(KERN_NOTICE "FrameState phyaddr:0x%08llx, viraddr:0x%08llx, len:%d\n", ++ isp_mem.ShareData_Meminfo.phys, ++ isp_mem.ShareData_Meminfo.kvirt, isp_mem.ShareData_Meminfo.length); ++ ++ base = 0; ++ isp_mem.AE_Offset = 0; ++ base += isp_mem.AE_Size; ++ isp_mem.AWB_Offset = base; ++ base += isp_mem.AWB_Size; ++ ++ //DBG_INFO("IQ vOffset[%d]:0x%08x", 0, (u32)isp_mem.IQ_tblOffset[0]); ++ for (i = 0; i < IQ_MEM_NUM; i++) { ++ isp_mem.IQ_tblOffset[i] = base; ++ base += isp_mem.IQ_tblSize[i]; ++ //DBG_INFO("IQ vOffset[%d]:0x%08x", i, (u32)isp_mem.IQ_tblOffset[i]); ++ } ++ ++ isp_mem.MOT_Offset = base; ++ base += isp_mem.MOT_Size; ++ ++ //isp_mem.AE_WriteIdx = 0;//AE_RING_BUFF_NUM; ++ //isp_mem.AE_ReadIdx = 0; ++ //isp_mem.AWB_WriteIdx = 0;//AWB_RING_BUFF_NUM; ++ //isp_mem.AWB_ReadIdx = 0; ++ isp_mem.IsWriteIQtbl = 0; ++ ++ isp_set_ae_base(); ++ ++ isp_set_awb_base(); ++ ++ isp_set_mot_base(); ++ ++#if 1 ++ { ++ ////////////////////////// ++ // request DNR frame buffer // ++ ////////////////////////// ++ int num_dnr_buf = get_dnr_buffer_num(); ++ if(num_dnr_buf==1) ++ { ++ int err = 0; ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[0]; ++ sprintf(info->name,"ISP_DNR_%d",0); ++ info->length = get_dnr_buffer_size(); ++ //pr_info("ISP DNR buffer#%d size = 0x%X\n",0,info->length); ++ if(msys_request_dmem(info)) ++ { ++ pr_err("ISP failed to request DNR frame buffer. err=0x%X\n",err); ++ } ++ else ++ { ++ isp_set_dnr_fb_base(info,0); ++ isp_set_dnr_fb_base(info,1); ++ } ++ } ++ else if(num_dnr_buf==2) ++ { ++ for(i=0;i<2;++i) ++ { ++ int err = 0; ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[i]; ++ sprintf(info->name,"ISP_DNR_%d",i); ++ info->length = get_dnr_buffer_size(); ++ //pr_info("ISP DNR buffer#%d size = 0x%X\n",i,info->length); ++ if(msys_request_dmem(info)) ++ { ++ pr_err("ISP failed to request DNR frame buffer. err=0x%X\n",err); ++ break; ++ } ++ isp_set_dnr_fb_base(info,i); ++ } ++ } ++ } ++#endif ++ return 0; ++} ++ ++static int isp_restore_buff(void) ++{ ++ int i; ++ ++ isp_set_ae_base(); ++ isp_set_awb_base(); ++ isp_set_mot_base(); ++ ++ for(i=0;i<2;++i) ++ { ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[i]; ++ isp_set_dnr_fb_base(info,i); ++ } ++ ++ return 0; ++} ++static int isp_open(struct inode *inode, struct file *fp) ++{ ++ fp->private_data = isp_device->dev.platform_data; ++ return 0; ++} ++ ++static int isp_release(struct inode *inode, struct file *fp) ++{ ++ fp->private_data = 0; ++ return 0; ++} ++static ssize_t isp_fread(struct file *fp, char __user *buf, size_t size, loff_t *ppos) ++{ ++ return 0; ++} ++ ++static ssize_t isp_fwrite(struct file *fp,const char __user *buf, size_t size, loff_t *ppos) ++{ ++ return 0; ++} ++ ++static long isp_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) ++{ ++ //int err= 0; ++ isp_dev_data *data = (isp_dev_data*) fp->private_data; ++ struct clk *_clk=0; ++ ++ pr_debug("ISP IOCTL +\n"); ++ if (_IOC_TYPE(cmd) != ISP_IOCTL_MAGIC) return -ENOTTY; ++ switch(cmd) ++ { ++ case IOCTL_ISP_CLOCK_CTL: ++ { ++ isp_ioctl_clock_ctl ctl; ++ ++ if(copy_from_user((void*)&ctl, (void __user *)arg, sizeof(ctl))) ++ { ++ BUG(); ++ } ++ ++ pr_info("ISP CLK CTL : id=%d rate=%d enable=%d\n",ctl.id,ctl.rate,ctl.enable); ++ ++ switch(ctl.id) ++ { ++ case CLK_ID_ISP: //ISP ++ _clk = data->clk_isp; ++ break; ++ case CLK_ID_SR: ++ _clk = data->clk_sr; ++ break; ++ case CLK_ID_SR_MCLK: ++ _clk = data->clk_sr_mclk; ++ break; ++ case CLK_ID_CSI_MAC: ++ _clk = data->clk_csi_mac; ++ break; ++ } ++ ++ if(!_clk) ++ return -1; ++ ++ if(ctl.rate>0) ++ clk_set_rate(_clk,ctl.rate); ++ ++ if(ctl.enable) ++ clk_prepare_enable(_clk); ++ else ++ clk_disable_unprepare(_clk); ++ } ++ break; ++ case IOCTL_ISP_IQ_RGBCCM: ++ { ++ if(copy_from_user((void*)&isp_int.rgb_ccm.ccm, (void __user *)arg, sizeof(isp_int.rgb_ccm.ccm))) ++ { ++ BUG(); ++ } ++ isp_int.rgb_ccm.dirty = 1; ++ }break; ++ case IOCTL_ISP_IQ_YUVCCM: ++ { ++ if(copy_from_user((void*)&isp_int.yuv_ccm.ccm, (void __user *)arg, sizeof(isp_int.yuv_ccm.ccm))) ++ { ++ BUG(); ++ } ++ isp_int.yuv_ccm.dirty = 1; ++ }break; ++ case IOCTL_ISP_GET_ISP_FLAG: ++ { ++ isp_ioctl_isp_flag isp_flag; ++ isp_flag.flag = g_isp_flag; ++ if(copy_to_user((void __user *)arg,(void*)&isp_flag,sizeof(isp_flag))) ++ { ++ BUG(); ++ } ++ }break; ++ case IOCTL_ISP_GET_INFO: ++ { ++ ISP_IOCTL_INFO info; ++ info.int_cnt = isp_int.int_cnt; ++ info.frame_interval = isp_int.fps.frame_interval; ++ ++ if(copy_to_user((void __user *)arg,(void*)&info,sizeof(info))) ++ { ++ BUG(); ++ } ++ }break; ++ } ++ pr_debug("ISP IOCTL -\n"); ++ return 0; ++} ++ ++struct file_operations isp_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = isp_open, ++ .release = isp_release, ++ .read = isp_fread, ++ .write = isp_fwrite, ++ //.compat_ioctl = isp_ioctl, ++ .unlocked_ioctl = isp_ioctl, ++}; ++ ++#define MAJOR_ISP_NUM 234 ++#define MINOR_ISP_NUM 128 ++#define MINOR_CSI_NUM 127 ++static int isp_probe(struct platform_device* pdev) ++{ ++ int err; ++ int irq; ++ unsigned int i, u4IO_PHY_BASE; ++ unsigned int u4Banks[8]; ++ isp_dev_data *data; ++ ++ pr_debug("[ISP] = isp_probe\n"); ++ ++ isp_int.int_cnt = 0; ++ ++ data = kzalloc(sizeof(isp_dev_data),GFP_KERNEL); ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4Banks, 8); ++ for (i = 0; i < 8; i++) { ++ isp_mem.pISPRegs[i] = (void*)ioremap(BANK_TO_ADDR32(u4Banks[i])+u4IO_PHY_BASE, BANK_SIZE); ++ } ++ ++ //enable clocks ++ //ISP ++ data->clk_isp = of_clk_get(pdev->dev.of_node, 0); ++ clk_set_rate(data->clk_isp,123000000); ++ clk_prepare_enable(data->clk_isp); ++ ++ data->clk_sr_mclk = of_clk_get(pdev->dev.of_node, 1); ++ clk_set_rate(data->clk_sr_mclk,12000000); ++ clk_prepare_enable(data->clk_sr_mclk); ++ ++ data->clk_sr = of_clk_get(pdev->dev.of_node, 2); ++ clk_set_rate(data->clk_sr,86000000); ++ clk_prepare_enable(data->clk_sr); ++ ++ data->clk_csi_mac = of_clk_get(pdev->dev.of_node, 3); ++ ++ data->isp_int = &isp_int; ++ data->isp_mem = &isp_mem; ++ fps_init(&data->isp_int->fps); //initial frame interval count ++ ++ // init register and disable interrupt ++ HalInitRegs((void**)isp_mem.pISPRegs); ++ HalISPDisableInt(); ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ pr_debug("[ISP] Request IRQ: %d\n", irq); ++ if (request_irq(irq, isp_ISR, 0, "isp interrupt", (void*)&isp_int) == 0) ++ pr_debug("[ISP] isp interrupt registered\n"); ++ else ++ pr_err("[ISP] isp interrupt failed"); ++ ++ SETREG8((u4IO_PHY_BASE+(0x112B00*2)+(0x16*4)),0x01); //set GPIO28 to GPIO function ++ CLRREG16((u4IO_PHY_BASE+(0x101A00*2)+(0x12*4)),(0x0001<<12)); //set GPIO28 pad mux to GPIO ++ CLRREG16((u4IO_PHY_BASE+(0x102B00*2)+(0x12*4)),(0x0001<<9)); //GPIO28 OEN ++ SETREG16((u4IO_PHY_BASE+(0x102B00*2)+(0x12*4)),(0x0001<<8)); //GPIO28 pull ligh ++ isp_device = pdev; ++ //isp_create_bin_file(&isp_device->dev); ++ ++ //allocate statistics data and menload table memory ++ isp_init_buff(); ++ ++ // enable interrupt ++ HalISPEnableInt(); ++ isp_int.sysfs_int = true; // turn on IRQ handler ++ isp_int.rgb_ccm.dirty = 0; ++ isp_int.yuv_ccm.dirty = 0; ++ // setup kernel i2c ++ //isp_i2c_init(isp_mem.pISPRegs[i]); ++ data->isp_dev.minor = MISC_DYNAMIC_MINOR; ++ data->isp_dev.name = "isp"; ++ data->isp_dev.fops = &isp_fops; ++ data->isp_dev.parent = &pdev->dev; ++ misc_register(&data->isp_dev); ++ ++ data->sysfs_dev = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR_ISP_NUM, MINOR_ISP_NUM), NULL, "isp0"); ++ isp_create_bin_file(data->sysfs_dev); ++ //err = sysfs_create_link(&data->sysfs_dev->kobj,&isp_device->dev.kobj, "files"); //create symlink for older firmware version ++ err = sysfs_create_link(&pdev->dev.parent->kobj,&data->sysfs_dev->kobj, "isp0"); //create symlink for older firmware version ++ ++ data->sysfs_dev->platform_data = pdev->dev.platform_data = (void*)data; ++ ++ //TEST CODE ++ MDrv_GPIO_Pull_High(0); ++ ++ return 0; ++} ++ ++static int isp_remove(struct platform_device* pdev) ++{ ++ isp_dev_data *data = dev_get_platdata(&pdev->dev); ++ clk_disable_unprepare(data->clk_isp); ++ clk_put(data->clk_isp); ++ clk_disable_unprepare(data->clk_sr); ++ clk_put(data->clk_sr); ++ clk_disable_unprepare(data->clk_sr_mclk); ++ clk_put(data->clk_sr_mclk); ++ ++ misc_deregister(&data->isp_dev); ++ device_destroy(msys_get_sysfs_class(),MKDEV(MAJOR_ISP_NUM, MINOR_ISP_NUM)); ++ kfree(data); ++ return 0; ++} ++ ++static int isp_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ isp_dev_data *data = dev_get_platdata(&pdev->dev); ++ ++ pr_info("[ISP] = isp_suspend\n"); ++ if (!pdev) ++ { ++ pr_info("isp_suspend with NULL pdev %d", isp_int.frame_cnt); ++ return 0; ++ } ++ isp_int.sysfs_int = false; ++ //HalISPClkEnable(false); ++ ++ if(data->clk_isp) clk_disable_unprepare(data->clk_isp); ++ if(data->clk_sr) clk_disable_unprepare(data->clk_sr); ++ if(data->clk_sr_mclk) clk_disable_unprepare(data->clk_sr_mclk); ++ ++ return 0; ++} ++ ++static int isp_resume(struct platform_device *pdev) ++{ ++ isp_dev_data *data = dev_get_platdata(&pdev->dev); ++ HalISPDisableInt(); ++ ++ isp_int.sysfs_int = false; ++ pr_info("[ISP] = isp_resume\n"); ++ ++ HalInitRegs((void**)data->isp_mem->pISPRegs); ++ isp_restore_buff(); //recover isp registers which contain buffer address , ++ ++ if(data->clk_isp) clk_prepare_enable(data->clk_isp); ++ if(data->clk_sr) clk_prepare_enable(data->clk_sr); ++ if(data->clk_sr_mclk) clk_prepare_enable(data->clk_sr_mclk); ++ ++ HalISPEnableInt(); // enable interrupt ++ ++ return 0; ++} ++ ++void isp_apply_iq_at_vend(void) ++{ ++ if(isp_int.rgb_ccm.dirty) ++ { ++ HalISPSetRGBCCM(isp_int.rgb_ccm.ccm); ++ isp_int.rgb_ccm.dirty = 0;; ++ print_timestamp("K_CCM1"); ++ } ++ ++ if(isp_int.yuv_ccm.dirty) ++ { ++ HalISPSetYUVCCM(isp_int.yuv_ccm.ccm); ++ isp_int.yuv_ccm.dirty = 0; ++ print_timestamp("K_CCM2"); ++ } ++ ++ if (isp_int.share_data->frame_state.u4OBCInValid == true){ ++ HalISPSetOBC(isp_int.share_data->frame_state.u4OBC_a, isp_int.share_data->frame_state.u4OBC_b); ++ isp_int.share_data->frame_state.u4OBCInValid = false; ++ print_timestamp("K_OBC"); ++ } ++ ++} ++ ++#define INC_TIME_REC(name) getnstimeofday(&isp_int.isp_int_time[name]) ++#define INC_TIME_REC2(name) getnstimeofday(&isp_int.isp_int_time2[name]) ++#define INC_TIME_REC3(name) getnstimeofday(&isp_int.isp_int_time3[name])) ++ ++#if 0 ++#define INC_COUNT(name) (isp_int.isp_int_count[name]++) ++#define INC_COUNT2(name) (isp_int.isp_int2_count[name]++) ++#define INC_COUNT3(name) (isp_int.isp_int3_count[name]++) ++#else ++#define INC_COUNT(name) {isp_int.isp_int_count[name]++;\ ++ getnstimeofday(&isp_int.isp_int_time[name]);} ++#define INC_COUNT2(name) {isp_int.isp_int2_count[name]++;\ ++ getnstimeofday(&isp_int.isp_int2_time[name]);} ++#define INC_COUNT3(name) {isp_int.isp_int3_count[name]++;\ ++ getnstimeofday(&isp_int.isp_int3_time[name]);} ++#endif ++ ++irqreturn_t isp_ISR(int num, void *priv) ++{ ++ volatile u32 u4Clear = 0; ++ volatile u32 u4Clear2 = 0; ++ volatile u32 u4Clear3 = 0; ++ ++ volatile u32 u4Status; ++ volatile u32 u4Status2; ++ volatile u32 u4Status3; ++ ++ volatile u32 u4VsyncPol; ++ volatile u32 u4MIPI; ++ ++ isp_int.int_cnt++; ++ ++ u4Status = HalISPGetIntStatus1(); ++ HalISPMaskInt1(u4Status); ++ u4Status2 = HalISPGetIntStatus2(); ++ HalISPMaskInt2(u4Status2); ++ u4Status3 = HalISPGetIntStatus3(); ++ HalISPMaskInt3(u4Status3); ++ ++ u4VsyncPol = HalISPGetVsyncPol(); ++ u4MIPI = HalISPGetMIPI(); ++ DBG_INFO(KERN_NOTICE "[ISP] -s- sta=0x%X\n",u4Status); ++ ++ if (u4Status == 0 && u4Status2 == 0 && u4Status3 == 0) { ++ pr_err("[ISP] False interrupt? mask1 0x%04x, mask2 0x%04x, mask3 0x%04x\n", u4Status, u4Status2, u4Status3); ++ return IRQ_HANDLED; ++ } ++ ++#if 0 ++ if (isp_int.sysfs_int == false) { ++ DBG_INFO_1("isp_int.sysfs_int == false"); ++ HalISPDisableInt(); ++ return IRQ_HANDLED; ++ } ++#endif ++ ++ DBG_INFO("c=%d sta=0x%x\n", isp_int.frame_cnt, u4Status); ++ ++ //////////////////////////////////////////// ++ // Vsync Start // ++ //////////////////////////////////////////// ++ //all sensor use ISP vsync as Frame start ++ if (ISP_CHECKBITS(u4Status, INT_ISPIF_VSYNC)){ ++ HalISPClearInt(&u4Clear, INT_ISPIF_VSYNC); ++ INC_COUNT(INT_ISPIF_VSYNC); ++ isp_int.vsync_start = true; ++ isp_int.frame_cnt++; ++ isp_int.share_data->frame_state.u4FrameCnt = isp_int.frame_cnt; ++ isp_int.share_data->frame_state.bActive = true; ++ isp_int.hw_frame_cnt = (HalISPGetFrameDoneCount()+ 1) & 0x7F; //get frame done count in VSync and return it at frame end interrupt ++ fps_update(&isp_int.fps); ++ wake_up_interruptible_all(&isp_wq_VSTART); ++ DBG_INFO_1("MIPI VSYNC ACTIVE %d", isp_int.frame_cnt); ++ pr_debug("VS\n"); ++ ++ //TEST CODE ++ //MDrv_GPIO_Set_High(0); ++ print_timestamp("K_VS");//TEST CODE ++ } ++ ++ ////////////////////////////////////////////// ++ // statistics // ++ ////////////////////////////////////////////// ++ if (ISP_CHECKBITS(u4Status, INT_AE_DONE)){ ++ isp_ae_cache_invalidate(); ++ DBG_INFO_1("INT_AE_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear, INT_AE_DONE); ++ INC_COUNT(INT_AE_DONE); ++ isp_int.ae = true; ++ wake_up_interruptible_all(&isp_wq_ae); ++ ++ //TEST CODE ++ //MDrv_GPIO_Set_Low(0); ++ } ++ ++ // AE WIN0/1 Int Row ++ if (ISP_CHECKBITS(u4Status3, INT3_AE_WIN0_DONE)) { ++ DBG_INFO_1("INT3_AE_WIN0_DONE %d\n", isp_int.frame_cnt); ++ isp_int.ae_win0 = true; ++ HalISPClearInt(&u4Clear3, INT3_AE_WIN0_DONE); ++ wake_up_interruptible_all(&isp_wq_ae_win0); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_AE_BLK_ROW_INT_DONE)) { ++ DBG_INFO_1("INT3_AE_BLK_ROW_INT_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_AE_BLK_ROW_INT_DONE); ++ INC_COUNT3(INT3_AE_BLK_ROW_INT_DONE); ++ isp_int.ae_row_int= true; ++ wake_up_interruptible_all(&isp_wq_ae_row_int); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_AWB_DONE)) { ++ isp_awb_cache_invalidate(); //invalid cache data ++ DBG_INFO_1("INT_AWB_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear, INT_AWB_DONE); ++ INC_COUNT(INT_AWB_DONE); ++ isp_int.awb = true; ++ wake_up_interruptible_all(&isp_wq_awb); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_AF_DONE)) { ++ DBG_INFO_1("INT_AF_DONE %d", isp_int.frame_cnt); ++ HalISPGetAFStat(isp_int.AF_Stat); ++ HalISPClearInt(&u4Clear, INT_AF_DONE); ++ INC_COUNT(INT_AF_DONE); ++ isp_int.af = true; ++ wake_up_interruptible_all(&isp_wq_af); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_SW_INT_INPUT_DONE)) { ++ DBG_INFO_1("INT3_SW_INT_INPUT_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_SW_INT_INPUT_DONE); ++ INC_COUNT3(INT3_SW_INT_INPUT_DONE); ++ wake_up_interruptible_all(&isp_wq_sw_int_in); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_SW_INT_OUTPUT_DONE)) { ++ DBG_INFO_1("INT3_SW_INT_OUTPUT_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_SW_INT_OUTPUT_DONE); ++ INC_COUNT3(INT3_SW_INT_OUTPUT_DONE); ++ wake_up_interruptible_all(&isp_wq_sw_int_out); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_ISP_BUSY)) { ++ HalISPClearInt(&u4Clear, INT_ISP_BUSY); ++ INC_COUNT(INT_ISP_BUSY); ++ DBG_INFO_1("INT_ISP_BUSY %d", isp_int.frame_cnt); ++ isp_int.isp_busy = true; ++ wake_up_interruptible_all(&isp_wq_ISP_BUSY); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_ISP_IDLE)) { ++ HalISPClearInt(&u4Clear, INT_ISP_IDLE); ++ INC_COUNT(INT_ISP_IDLE); ++ DBG_INFO_1("INT_ISP_IDLE %d", isp_int.frame_cnt); ++ isp_int.isp_idle = true; ++ wake_up_interruptible_all(&isp_wq_ISP_IDLE); ++ } ++ ++ ////////////////////////////// ++ // Vsync end // ++ ////////////////////////////// ++ ++ if (!u4MIPI){ ++ if ((ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_RISING) && u4VsyncPol == false) || (ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_FALLING) && u4VsyncPol == true)){ ++ if (isp_int.vsync_end == false){ ++ if (ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_RISING) && u4VsyncPol == false ){ ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_RISING); ++ INC_COUNT(INT_PAD_VSYNC_RISING); ++ IspInputEnable(isp_int.share_data->frame_state.bIspInputEnable); ++ if (isp_int.frame_cnt%30==0) ++ DBG_INFO_1("Parallel Vsync End INT_PAD_VSYNC_RISING %d", isp_int.frame_cnt); ++ } ++ else if (ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_FALLING) && u4VsyncPol == true){ ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_FALLING); ++ INC_COUNT(INT_PAD_VSYNC_FALLING); ++ IspInputEnable(isp_int.share_data->frame_state.bIspInputEnable); ++ if (isp_int.frame_cnt%30==0) ++ DBG_INFO_1("Parallel Vsync End INT_PAD_VSYNC_FALLING %d", isp_int.frame_cnt); ++ } ++ ++ pr_debug("VE\n"); ++ DBG_INFO_1(KERN_NOTICE "Parallel VSYNC End...%d %d\n", isp_int.share_data->frame_state.bActive, isp_int.share_data->frame_state.u4FrameCnt); ++ isp_int.vsync_end = true; ++ isp_int.share_data->frame_state.bActive = false; ++ isp_apply_iq_at_vend(); ++ wake_up_interruptible_all(&isp_wq_VEND); ++ // Using menuload to write IQ table to SRAMs ++ //isp_write_iq_tbl(); ++ }else{ ++ //DBG_INFO("Parallel Vsync End ---FALSE---"); ++ } ++ } ++ } ++ ++ //////////////////////////////////////////// ++ // DMA // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(u4Status, INT_WDMA_DONE) && isp_int.wdma_done == false) { ++ HalISPClearInt(&u4Clear, INT_WDMA_DONE); ++ INC_COUNT(INT_WDMA_DONE); ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_RISING); ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_FALLING); ++ DBG_INFO_1("INT_WDMA_DONE %d", isp_int.frame_cnt); ++ isp_int.wdma_done = true; ++ wake_up_interruptible_all(&isp_wq_WDMA_DONE); ++ } else { ++ //DBG_INFO("INT_WDMA_DONE %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_RDMA_DONE) && isp_int.rdma_done == false) { ++ HalISPClearInt(&u4Clear, INT_RDMA_DONE); ++ INC_COUNT(INT_RDMA_DONE); ++ DBG_INFO_1("INT_RDMA_DONE %d", isp_int.frame_cnt); ++ isp_int.rdma_done = true; ++ wake_up_interruptible_all(&isp_wq_RDMA_DONE); ++ } else { ++ //DBG_INFO("INT_RDMA_DONE %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ //////////////////////////////////////////// ++ // FIFO Full // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(u4Status, INT_ISP_FIFO_FULL)) ++ { ++ HalISPClearInt(&u4Clear, INT_ISP_FIFO_FULL); ++ INC_COUNT(INT_ISP_FIFO_FULL); ++ //DBG_INFO_1("INT_ISP_FIFO_FULL %d", isp_int.frame_cnt); ++ pr_debug("isp fifo full %d", isp_int.frame_cnt); ++ isp_int.isp_fifofull = true; ++ IspReset(); //force ISP reset , when ISP FIFO FULL happen ++ wake_up_interruptible_all(&isp_wq_ISP_FIFO_FULL); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_WDMA_FIFO_FULL) && isp_int.wdma_fifofull == false){ ++ HalISPClearInt(&u4Clear, INT_WDMA_FIFO_FULL); ++ INC_COUNT(INT_WDMA_FIFO_FULL); ++ DBG_INFO_1("INT_WDMA_FIFO_FULL %d", isp_int.frame_cnt); ++ isp_int.wdma_fifofull = true; ++ wake_up_interruptible_all(&isp_wq_WDMA_FIFO_FULL); ++ } ++ ++ if (ISP_CHECKBITS(u4Status2, INT2_VDOS_LINE2)) { ++ HalISPClearInt(&u4Clear2, INT2_VDOS_LINE2); ++ INC_COUNT2(INT2_VDOS_LINE2); ++ DBG_INFO_1("INT2_VDOS_LINE2 %d", isp_int.frame_cnt); ++ isp_int.eis = true; ++ wake_up_interruptible_all(&isp_wq_eis); ++ } ++ ++ HalISPMaskClear1(u4Clear); ++ HalISPMaskClear2(u4Clear2); ++ HalISPMaskClear3(u4Clear3); ++ if (isp_int.frame_cnt%1200==0){ ++ pr_debug("end of ISR, u4Status:0x%04x/0x%04x/0x%04x, u4Clear:0x%04x/0x%04x/0x%04x", u4Status, u4Status2, u4Status3, u4Clear, u4Clear2, u4Clear3); ++ } ++ return IRQ_HANDLED; ++} ++ ++static ssize_t isp_watchdog_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ int watchdog_counter = atomic_read(&isp_watchdog_counter); ++ data_size = sizeof(watchdog_counter); ++ if (buf && size >= data_size) { ++ memcpy((void *)buf, (void *)&watchdog_counter, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++ ++} ++ ++static ssize_t isp_watchdog_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int cmd, watchdogCNT; ++ cmd = watchdogCNT = 0; ++ ++ sscanf(buf,"%d %d\n", &cmd, &watchdogCNT); ++ //pr_info("cmd = %d, watchdogCNT = %d\n", cmd, watchdogCNT); ++ // update watchdog timer counter ++ if(cmd == WATCHDOG_UPDATE) { ++ atomic_set(&isp_watchdog_counter, isp_watchdog_update_counter); ++ } ++ // initial timer and set isp_watchdog_counter to MAX_WATCHDOG_TIME ++ if(cmd == WATCHDOG_KICK) { ++ if(watchdogCNT != 0) { ++ atomic_set(&isp_watchdog_counter, watchdogCNT); ++ isp_watchdog_update_counter = watchdogCNT; ++ }else{ ++ atomic_set(&isp_watchdog_counter, MAX_WATCHDOG_TIME); ++ isp_watchdog_update_counter = MAX_WATCHDOG_TIME; ++ } ++ mod_timer( &isp_watchdog_timer, jiffies + msecs_to_jiffies(1000) ); ++ } ++ ++ // initial timer and set isp_watchdog_counter to MAX_WATCHDOG_TIME ++ if(cmd == WATCHDOG_STOP) { ++ del_timer_sync(&isp_watchdog_timer); ++ atomic_set(&isp_watchdog_counter, 0); ++ } ++ return size; ++} ++ ++static int isp_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ typedef struct { ++ unsigned long u4BaseAddr; ++ u32 u4Size; ++ } FRAMEINFO_MEM; ++ ++ FRAMEINFO_MEM frameinfo; ++ frameinfo.u4BaseAddr = isp_mem.ShareData_Meminfo.phys + offsetof(ISP_SHARE_DATA,frame_state); ++ frameinfo.u4Size = sizeof(FRAME_STATE); ++ data_size = sizeof(FRAMEINFO_MEM); ++ if (buf && size >= data_size) { ++ DBG_INFO("buff in %d, out %d\n", size, data_size); ++ memcpy((void *)buf, (void *)&frameinfo, data_size); ++ } ++ return data_size; ++} ++ ++static int isp_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if (buf && size >= 1) { ++ reset_isp_int(&isp_int); ++ isp_int.sysfs_int = (buf[0] & 0x01); ++ } else { ++ //memset((void*)&isp_int, 0, sizeof(ISP_INT_DATA)); ++ reset_isp_int(&isp_int); ++ isp_int.sysfs_int = false; ++ } ++ ++ if (isp_int.sysfs_int == true) ++ HalISPEnableInt(); ++ else ++ HalISPDisableInt(); ++ ++ return size; ++} ++ ++static int vs_sr_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_VSTART, isp_int.vsync_start == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.vsync_start = false; ++ C_OUT(isp_lock); ++ return -ERESTARTSYS; ++ } ++ C_IN(isp_lock); ++ isp_int.vsync_start = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++ ++static int vs_sr_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++typedef struct ++{ ++ u32 frame_cnt; ++ u32 hw_frame_cnt; ++}__attribute__((packed, aligned(1))) ve_isr_data; //vsync end isr data ++ ++static int ve_sr_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ ve_isr_data ve_data; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_VEND, isp_int.vsync_end == true)){ ++ C_IN(isp_lock); ++ isp_int.vsync_end = false; ++ C_OUT(isp_lock); ++ return -ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.vsync_end = false; ++ ve_data.frame_cnt = isp_int.frame_cnt; ++ ve_data.hw_frame_cnt = isp_int.hw_frame_cnt; ++ C_OUT(isp_lock); ++ ++ if (buf){ ++ size = size>sizeof(ve_data)?sizeof(ve_data):size; ++ memcpy((void*)buf,(void*)&ve_data,size); ++ } ++ return size; ++} ++ ++static int ve_sr_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae, isp_int.ae == true)){ ++ C_IN(isp_lock); ++ isp_int.ae = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae = false; ++ C_OUT(isp_lock); ++ ++ // TODO ++ DBG_INFO_2("ae virtual offset[%d]: 0x%08x", isp_mem.AE_ReadIdx, (u32)isp_mem.AE_Offset[isp_mem.AE_ReadIdx]); ++ ++ if(buf){ ++ ae_isr_data ae_data; ++ ae_data.data_offset = isp_mem.AE_Offset; ++ ae_data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(ae_data)?sizeof(ae_data):size; ++ memcpy((void*)buf,(void*)&ae_data,size); ++ }else { ++ size= 0; ++ } ++ ++ return size; ++} ++static int ae_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_win0_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae_win0, isp_int.ae_win0 == true)){ ++ C_IN(isp_lock); ++ isp_int.ae_win0 = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae_win0 = false; ++ C_OUT(isp_lock); ++ ++ DBG_INFO_2("ae virtual offset[%d]: 0x%08x", isp_mem.AE_ReadIdx, (u32)isp_mem.AE_Offset[isp_mem.AE_ReadIdx]); ++ ++ if(buf){ ++ ae_isr_data ae_data; ++ ae_data.data_offset = isp_mem.AE_Offset; ++ ae_data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(ae_data)?sizeof(ae_data):size; ++ memcpy((void*)buf,(void*)&ae_data,size); ++ } ++ ++ return size; ++} ++ ++static int ae_win0_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_win1_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int ae_win1_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_row_int_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae_row_int, isp_int.ae_row_int== true)){ ++ C_IN(isp_lock); ++ isp_int.ae_row_int = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae_row_int = false; ++ C_OUT(isp_lock); ++ ++ if(buf){ ++ ae_isr_data ae_data; ++ ae_data.data_offset = isp_mem.AE_Offset; ++ ae_data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(ae_data)?sizeof(ae_data):size; ++ memcpy((void*)buf,(void*)&ae_data,size); ++ } ++ else { ++ size= 0; ++ } ++ return size; ++} ++ ++static int ae_row_int_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int sw_int_in_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int sw_int_in_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int sw_int_out_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int sw_int_out_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int awb_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ awb_isr_data awb_data; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_awb, isp_int.awb == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.awb = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.awb = false; ++ C_OUT(isp_lock); ++ ++ DBG_INFO_2("awb virtual offset[%d]: 0x%08x", isp_mem.AWB_ReadIdx, (u32)isp_mem.AWB_Offset[isp_mem.AWB_ReadIdx]); ++ ++ if (buf) { ++ awb_data.data_offset = isp_mem.AWB_Offset; ++ awb_data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(awb_data)?sizeof(awb_data):size; ++ memcpy((void*)buf,(void*)&awb_data, size); ++ } else { ++ size = 0; ++ } ++ ++ return size; ++} ++ ++static int awb_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int af_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ u32 af_size = sizeof(isp_int.AF_Stat); ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_af, isp_int.af == true)){ ++ C_IN(isp_lock); ++ isp_int.af = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.af = false; ++ C_OUT(isp_lock); ++ ++ if (buf && size >= af_size) { ++ memcpy((void *)buf, (void *)isp_int.AF_Stat, af_size); ++ } else ++ af_size = 0; ++ ++ return af_size; ++} ++static int af_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int busy_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_BUSY, isp_int.isp_busy == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_busy = false; ++ C_OUT(isp_lock); ++ ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_busy = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++ ++static int busy_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int idle_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_IDLE, isp_int.isp_idle == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_idle = false; ++ C_OUT(isp_lock); ++ ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_idle = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++static int idle_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++/// isp fifo full ++static int isp_fifofull_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_FIFO_FULL, isp_int.isp_fifofull == true)) ++ { ++ ++ C_IN(isp_lock); ++ isp_int.isp_fifofull = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_fifofull = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++static int isp_fifofull_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++// wdma fifo full ++static int wdma_fifofull_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_WDMA_FIFO_FULL, isp_int.wdma_fifofull == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.wdma_fifofull = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.wdma_fifofull = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++ ++static int wdma_fifofull_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// wdma done ++static int wdma_done_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_WDMA_DONE, isp_int.wdma_done == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.wdma_done = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.wdma_done = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ //DBG_INFO("buff in %d, out %d", size, data_size); ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++ ++static int wdma_done_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// rdma done ++static int rdma_done_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_RDMA_DONE, isp_int.rdma_done == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.rdma_done = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ C_IN(isp_lock); ++ isp_int.rdma_done = false; ++ C_OUT(isp_lock); ++ ++ data_size = sizeof(isp_int.frame_cnt); ++ if (buf && size >= data_size) { ++ memcpy((void *)buf, (void *)&isp_int.frame_cnt, data_size); ++ } else ++ data_size = 0; ++ ++ return data_size; ++} ++ ++static int rdma_done_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// eis vdos ++static int eis_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ // FIXJASON ++ unsigned long flags; ++ ++ if (wait_event_interruptible(isp_wq_eis, isp_int.eis == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.eis = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.eis = false; ++ C_OUT(isp_lock); ++ ++ return 0; ++} ++static int eis_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ // FIXJASON ++ DBG_INFO(); ++ return size; ++} ++ ++static int iq_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ unsigned short *pData; ++ ++ if (buf && size >= 1) { ++ //Temp using ++ if(buf[0] == 1) { ++ isp_mem.IsWriteIQtbl = buf[0]; ++ ++ } ++ else if(buf[0] == 2) { ++ isp_mem.IsWriteIQtbl = 1; ++ } ++ else if(buf[0] == 3) { ++ pData = (unsigned short*)((uintptr_t)(isp_mem.Base_Meminfo.kvirt+isp_mem.IQ_tblOffset[IQ_MEM_ALSC_BGAIN])); ++ } ++ } ++ ++ return size; ++} ++ ++// iq ++typedef struct { ++ u32 u4BaseAddr; ++ u32 u4Size; ++ u32 u4IqTblOffset[IQ_MEM_NUM]; ++ u32 u4IqTblSize[IQ_MEM_NUM]; ++} ISP_KERNEL_MEM; ++ ++static int iq_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ if (buf && size >= sizeof(ISP_KERNEL_MEM)) ++ { ++ ISP_KERNEL_MEM *mem_info = (ISP_KERNEL_MEM*) buf; ++ mem_info->u4BaseAddr = isp_mem.Base_Meminfo.phys; ++ mem_info->u4Size = isp_mem.Base_Meminfo.length; ++ memcpy(mem_info->u4IqTblOffset, (void *)isp_mem.IQ_tblOffset, sizeof(isp_mem.IQ_tblOffset)); ++ memcpy(mem_info->u4IqTblSize, (void *)isp_mem.IQ_tblSize, sizeof(isp_mem.IQ_tblSize)); ++ } ++ return sizeof(ISP_KERNEL_MEM); ++} ++ ++// motion statistic ++static int mot_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if (buf && size >= isp_mem.MOT_Size) ++ { ++ memcpy( buf, (unsigned char*)((uintptr_t)(isp_mem.Base_Meminfo.kvirt+isp_mem.MOT_Offset)) ,isp_mem.MOT_Size); ++ return isp_mem.MOT_Size; ++ } ++ return 0; ++} ++static int mot_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// SCL vsync end ++static int scl_fe_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_scl_fe, isp_int.scl_fe == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.scl_fe = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.scl_fe = false; ++ C_OUT(isp_lock); ++ ++ return 0; ++} ++ ++static int scl_fe_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++void isp_to_scl_ve_isr(void) ++{ ++ print_timestamp("K_ISP2SCL"); ++} ++ ++void scl_ve_isr(void) ++{ ++ print_timestamp("K_SCL_DONE"); ++ if (!isp_int.scl_fe){ ++ isp_int.scl_fe = true; ++ wake_up_interruptible_all(&isp_wq_scl_fe); ++ } ++} ++ ++#if 0 ++//sensor i2c ++typedef struct ++{ ++ u32 cmd; ++ u32 data_len; ++ char data[1]; ++}__attribute__((packed, aligned(1))) isp_i2c_k_cmd; //kernel i2c command ++#define I2C_K_CMD_GET_BUFFER 0x00 ++#define I2C_K_CMD_WRITE 0x01 ++#define I2C_K_CMD_READ 0x02 ++ ++static int i2c_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++static int i2c_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ i2c_handle_t* handle = (i2c_handle_t*) attr->private; ++ if (buf && size >= sizeof(ISP_K_I2C_RW)) ++ { ++ ISP_K_I2C_RW *cmd = (ISP_K_I2C_RW*)buf; ++ memcpy(handle->req.data,cmd->i2c_data,sizeof(I2C_ARRAY)*cmd->num_i2c_data); //copy i2c data for write ++ handle->req.ndata = cmd->num_i2c_data; ++ handle->req.mode = cmd->cfg.mode; ++ handle->req.fmt = cmd->cfg.fmt; ++ handle->req.slave_addr = cmd->cfg.address; ++ handle->req.speed = cmd->cfg.speed; ++ handle->req.status = I2C_REQ_STATUS_WAIT; ++ pr_debug("i2cK, %d data, slave addr=0x%x",cmd->num_i2c_data,cmd->cfg.address); ++ } ++ return 0; ++} ++#endif ++ ++#if 0 ++//share memory address get ++typedef struct ++{ ++ u32 id; ++ u8 data[1]; ++}share_mem_ctl; ++ ++typedef enum ++{ ++ SHARE_FRAME_STATE = 0, ++ SHARE_I2C = 1, ++}ISP_SHARE_MEM_ID; ++ ++static int share_mem_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ share_mem_ctl *ctl = (share_mem_ctl*)buf; ++ //printk("%s+\n",__FUNCTION__); ++ printk("ctl id = %d\n",ctl->id); ++ switch(ctl->id) ++ { ++ case SHARE_FRAME_STATE: ++ printk("get share frame stat\n"); ++ break; ++ case SHARE_I2C: ++ printk("get share i2c\n"); ++ break; ++ } ++ printk("return size =%d\n", size); ++ return size/2; ++} ++ ++static int share_mem_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++#endif ++ ++static ISP_BIN_ATTR(isp, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(isp_watchdog, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(vs_sr, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ve_sr, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae_win0, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae_win1, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae_row_int, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(awb, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(af, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(busy, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(idle, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(isp_fifofull, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(wdma_fifofull, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(wdma_done, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(rdma_done, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(eis, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(sw_int_in, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(sw_int_out, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(iq, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mot, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(scl_fe, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++//static ISP_BIN_ATTR(i2c, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++//static ISP_BIN_ATTR(share_mem, S_IRUSR |S_IRGRP |S_IROTH); ++//static ISP_BIN_ATTR(share_mem,S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++ ++static ssize_t isp_ints_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%s : %d\n","frame_count",isp_int.frame_cnt); ++ str += scnprintf(str, end - str, "%s : %d\n","frame_interval(ns)",isp_int.fps.frame_interval); ++#if 0 ++ str += scnprintf(str, end - str, "%s : %d\n","SR_VREF_RISING",isp_int.isp_int_count[INT_SR_VREF_RISING]); ++ str += scnprintf(str, end - str, "%s : %d\n","SR_VREF_FALLING",isp_int.isp_int_count[INT_SR_VREF_FALLING]); ++ str += scnprintf(str, end - str, "%s : %d\n","STROBE_DONE",isp_int.isp_int_count[INT_STROBE_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","DB_UPDATE_DONE",isp_int.isp_int_count[INT_DB_UPDATE_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AF_DONE",isp_int.isp_int_count[INT_AF_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_FIFO_FUL",isp_int.isp_int_count[INT_ISP_FIFO_FULL]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_BUSY",isp_int.isp_int_count[INT_ISP_BUSY]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_IDLE",isp_int.isp_int_count[INT_ISP_IDLE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AWB_DONE",isp_int.isp_int_count[INT_AWB_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","WDMA_DONE",isp_int.isp_int_count[INT_WDMA_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","RDMA_DONE",isp_int.isp_int_count[INT_RDMA_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","WDMA_FIFO_FULL",isp_int.isp_int_count[INT_WDMA_FIFO_FULL]); ++ str += scnprintf(str, end - str, "%s : %d\n","PAD_VSYNC_RISING",isp_int.isp_int_count[INT_PAD_VSYNC_RISING]); ++ str += scnprintf(str, end - str, "%s : %d\n","PAD_VSYNC_FALLING",isp_int.isp_int_count[INT_PAD_VSYNC_FALLING]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISPIF_VSYNC",isp_int.isp_int_count[INT_ISPIF_VSYNC]); ++ str += scnprintf(str, end - str, "%s : %d\n","AE_DONE",isp_int.isp_int_count[INT_AE_DONE]); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_EVERYLINE",isp_int.isp_int2_count[INT2_VDOS_EVERYLINE]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE0",isp_int.isp_int2_count[INT2_VDOS_LINE0]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE1 ",isp_int.isp_int2_count[INT2_VDOS_LINE1]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE2",isp_int.isp_int2_count[INT2_VDOS_LINE2]); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","AE_WIN0_DONE",isp_int.isp_int3_count[INT3_AE_WIN0_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AE_WIN1_DONE",isp_int.isp_int3_count[INT3_AE_WIN1_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AE_BLK_ROW_INT_DONE",isp_int.isp_int3_count[INT3_AE_BLK_ROW_INT_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","MENULOAD_DONE",isp_int.isp_int3_count[INT3_MENULOAD_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","SW_INT_INPUT_DONE",isp_int.isp_int3_count[INT3_SW_INT_INPUT_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","SW_INT_OUTPUT_DONE",isp_int.isp_int3_count[INT3_SW_INT_OUTPUT_DONE]); ++#else ++ str += scnprintf(str, end - str, "%s : %d\n","SR_VREF_RISING",isp_int.isp_int_count[INT_SR_VREF_RISING]); ++ str += scnprintf(str, end - str, "%s : %d\n","SR_VREF_FALLING",isp_int.isp_int_count[INT_SR_VREF_FALLING]); ++ str += scnprintf(str, end - str, "%s : %d\n","STROBE_DONE",isp_int.isp_int_count[INT_STROBE_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","DB_UPDATE_DONE",isp_int.isp_int_count[INT_DB_UPDATE_DONE]); ++ ++ //AF_DONE ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","AF_DONE" ++ ,isp_int.isp_int_count[INT_AF_DONE] ++ ,(unsigned int)isp_int.isp_int_time[INT_AF_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_AF_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_FIFO_FUL",isp_int.isp_int_count[INT_ISP_FIFO_FULL]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_BUSY",isp_int.isp_int_count[INT_ISP_BUSY]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_IDLE",isp_int.isp_int_count[INT_ISP_IDLE]); ++ ++ //AWB ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","AWB_DONE" ++ ,isp_int.isp_int_count[INT_AWB_DONE] ++ ,(unsigned int)isp_int.isp_int_time[INT_AWB_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_AWB_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","WDMA_DONE",isp_int.isp_int_count[INT_WDMA_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","RDMA_DONE",isp_int.isp_int_count[INT_RDMA_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","WDMA_FIFO_FULL",isp_int.isp_int_count[INT_WDMA_FIFO_FULL]); ++ ++ //PAD_VSYNC_RISING ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","PAD_VSYNC_RISING" ++ ,isp_int.isp_int_count[INT_PAD_VSYNC_RISING] ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_RISING].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_RISING].tv_nsec); ++ ++ //PAD_VSYNC_FALLING ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","PAD_VSYNC_FALLING" ++ ,isp_int.isp_int_count[INT_PAD_VSYNC_FALLING] ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_FALLING].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_FALLING].tv_nsec); ++ ++ //ISPIF_VSYNC ++ str += scnprintf(str, end - str,"%s : %d ,%u.%09u\n","ISPIF_VSYNC" ++ ,isp_int.isp_int_count[INT_ISPIF_VSYNC] ++ ,(unsigned int)isp_int.isp_int_time[INT_ISPIF_VSYNC].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_ISPIF_VSYNC].tv_nsec); ++ ++ //AE_DONE ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","AE_DONE " ++ ,isp_int.isp_int_count[INT_AE_DONE] ++ ,(unsigned int)isp_int.isp_int_time[INT_AE_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_AE_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_EVERYLINE",isp_int.isp_int2_count[INT2_VDOS_EVERYLINE]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE0",isp_int.isp_int2_count[INT2_VDOS_LINE0]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE1 ",isp_int.isp_int2_count[INT2_VDOS_LINE1]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE2",isp_int.isp_int2_count[INT2_VDOS_LINE2]); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","AE_WIN0_DONE",isp_int.isp_int3_count[INT3_AE_WIN0_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AE_WIN1_DONE",isp_int.isp_int3_count[INT3_AE_WIN1_DONE]); ++ ++ //INT3_AE_BLK_ROW_INT_DONE ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","INT3_AE_BLK_ROW_INT_DONE" ++ ,isp_int.isp_int3_count[INT3_AE_BLK_ROW_INT_DONE] ++ ,(unsigned int)isp_int.isp_int3_time[INT3_AE_BLK_ROW_INT_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int3_time[INT3_AE_BLK_ROW_INT_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","MENULOAD_DONE",isp_int.isp_int3_count[INT3_MENULOAD_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","SW_INT_INPUT_DONE",isp_int.isp_int3_count[INT3_SW_INT_INPUT_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","SW_INT_OUTPUT_DONE",isp_int.isp_int3_count[INT3_SW_INT_OUTPUT_DONE]); ++#endif ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++DEVICE_ATTR(isp_ints, 0444, isp_ints_show, NULL); ++ ++static ssize_t isp_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ int n=0; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ for(n=0;nisp_info_str[n]); ++ return (str - buf); ++} ++DEVICE_ATTR(isp_info, 0444, isp_info_show, NULL); ++ ++static ssize_t isp_fps_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "%d\n",1000000000/isp_int.fps.frame_interval); ++ return (str - buf); ++} ++DEVICE_ATTR( isp_fps, 0444, isp_fps_show, NULL); ++ ++static ssize_t csi_ints_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ csi_dev_data *data = (csi_dev_data*) dev->platform_data; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ //frame ++ str += scnprintf(str, end - str, "%s : %d\n","FS_INTS",data->fs_int_count); ++ str += scnprintf(str, end - str, "%s : %d\n","VC0_INTS",data->vc0_int_count); ++ //csi error ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_DT",data->csi_err_int_count[ERR_INT_DT]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_PA_LENS",data->csi_err_int_count[ERR_INT_PA_LENS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_PH_LENS",data->csi_err_int_count[ERR_INT_PH_LENS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_ECC_ONEBIT",data->csi_err_int_count[ERR_INT_ECC_ONEBIT]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_FRAME_START",data->csi_err_int_count[ERR_INT_FRAME_START]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_FRAME_END",data->csi_err_int_count[ERR_INT_FRAME_END]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_ECC_TWOBIT",data->csi_err_int_count[ERR_INT_ECC_TWOBIT]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_CRC",data->csi_err_int_count[ERR_INT_CRC]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_PA_WC_EQ0",data->csi_err_int_count[ERR_INT_PA_WC_EQ0]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_RAW10_LENS",data->csi_err_int_count[ERR_INT_RAW10_LENS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_CON_FE",data->csi_err_int_count[ERR_INT_CON_FE]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_CON_FS",data->csi_err_int_count[ERR_INT_CON_FS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_LE",data->csi_err_int_count[ERR_INT_LE]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_LS",data->csi_err_int_count[ERR_INT_LS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_OVERRUN",data->csi_err_int_count[ERR_INT_OVERRUN]); ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(csi_ints, 0444, csi_ints_show, NULL); ++ ++// CSI debug interrupts // ++static ssize_t csi_dbg_mask_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ csi_dev_data *data = (csi_dev_data*) dev->platform_data; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "csi dbg mask = 0x%x",HalCsi_ErrIntMaskGet(data->hal_handle)); ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t csi_dbg_mask_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ csi_dev_data *data = (csi_dev_data*) dev->platform_data; ++ if(buf && count>0){ ++ long mask = 0; ++ if( !kstrtol(buf,0,&mask) ){ ++ pr_debug("new mask=0x%X\n",(unsigned int)mask); ++ HalCsi_ErrIntMaskSet(data->hal_handle,mask); ++ } ++ } ++ return count; ++} ++ ++DEVICE_ATTR(csi_dbg_mask, 0644, csi_dbg_mask_show, csi_dbg_mask_store); ++ ++// CSI // ++static int csi_fe_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ csi_dev_data *data = (csi_dev_data*) attr->private; ++ if (wait_event_interruptible(*data->p_wq_fe, data->frame_end == true)) ++ { ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_end = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ return - ERESTARTSYS; ++ } ++ ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_end = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ ++ if (buf && size >= sizeof(data->count) ) { ++ memcpy((void *)buf, (void *)&data->count, sizeof(data->count)); ++ return sizeof(data->count); ++ } ++ ++ return 0; ++} ++ ++static int csi_fe_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int csi_fs_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ csi_dev_data *data = (csi_dev_data*) attr->private; ++ if (wait_event_interruptible(*data->p_wq_fs, data->frame_start == true)){ ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_start = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ return - ERESTARTSYS; ++ } ++ ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_start = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ ++ if (buf && size >= sizeof(data->count) ) { ++ memcpy((void *)buf, (void *)&data->count, sizeof(data->count)); ++ return sizeof(data->count); ++ } ++ ++ return 0; ++} ++ ++static int csi_fs_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// CSI // ++static ISP_BIN_ATTR(csi_fe, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(csi_fs, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++ ++int isp_create_bin_file(struct device *dev) ++{ ++ int error = -EINVAL; ++ if (dev != NULL) { ++ kobj_isp = &dev->kobj; ++ //error = sysfs_create_link(&dev->parent->kobj, kobj_isp, "isp0"); ++ //error = sysfs_create_link(&dev->kobj, kobj_isp, "isp0"); ++ error = sysfs_create_bin_file(kobj_isp, &isp_attr); ++ error = sysfs_create_bin_file(kobj_isp, &isp_watchdog_attr); ++ error = sysfs_create_bin_file(kobj_isp, &vs_sr_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ve_sr_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_win0_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_win1_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_row_int_attr); ++ error = sysfs_create_bin_file(kobj_isp, &awb_attr); ++ error = sysfs_create_bin_file(kobj_isp, &af_attr); ++ error = sysfs_create_bin_file(kobj_isp, &busy_attr); ++ error = sysfs_create_bin_file(kobj_isp, &idle_attr); ++ error = sysfs_create_bin_file(kobj_isp, &isp_fifofull_attr); ++ error = sysfs_create_bin_file(kobj_isp, &wdma_fifofull_attr); ++ error = sysfs_create_bin_file(kobj_isp, &wdma_done_attr); ++ error = sysfs_create_bin_file(kobj_isp, &rdma_done_attr); ++ error = sysfs_create_bin_file(kobj_isp, &eis_attr); ++ error = sysfs_create_bin_file(kobj_isp, &sw_int_in_attr); ++ error = sysfs_create_bin_file(kobj_isp, &sw_int_out_attr); ++ error = sysfs_create_bin_file(kobj_isp, &iq_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mot_attr); ++ error = sysfs_create_bin_file(kobj_isp, &scl_fe_attr); ++ ++ //i2c_attr.private = (void*) &isp_i2c; ++ //error = sysfs_create_bin_file(kobj_isp, &i2c_attr); ++ ++ //share_mem_attr.private = 0; ++ //error = sysfs_create_bin_file(kobj_isp, &share_mem_attr); ++ ++ error = device_create_file(dev,&dev_attr_isp_ints); ++ error = device_create_file(dev,&dev_attr_isp_info); ++ error = device_create_file(dev,&dev_attr_isp_fps); ++ } ++ //pr_debug("[%s] end\n", __FUNCTION__); ++ return error; ++} ++ ++void isp_remove_bin_file(void) ++{ ++ sysfs_remove_bin_file(kobj_isp, &isp_attr); ++ sysfs_remove_bin_file(kobj_isp, &isp_watchdog_attr); ++ sysfs_remove_bin_file(kobj_isp, &vs_sr_attr); ++ sysfs_remove_bin_file(kobj_isp, &ve_sr_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_win0_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_win1_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_row_int_attr); ++ sysfs_remove_bin_file(kobj_isp, &awb_attr); ++ sysfs_remove_bin_file(kobj_isp, &af_attr); ++ sysfs_remove_bin_file(kobj_isp, &busy_attr); ++ sysfs_remove_bin_file(kobj_isp, &idle_attr); ++ sysfs_remove_bin_file(kobj_isp, &isp_fifofull_attr); ++ sysfs_remove_bin_file(kobj_isp, &wdma_fifofull_attr); ++ sysfs_remove_bin_file(kobj_isp, &wdma_done_attr); ++ sysfs_remove_bin_file(kobj_isp, &rdma_done_attr); ++ sysfs_remove_bin_file(kobj_isp, &eis_attr); // FIXJASON ++ sysfs_remove_bin_file(kobj_isp, &sw_int_in_attr); ++ sysfs_remove_bin_file(kobj_isp, &sw_int_out_attr); ++ sysfs_remove_bin_file(kobj_isp, &iq_attr); ++ //sysfs_remove_bin_file(kobj_isp, &share_mem_attr); ++ //sysfs_remove_bin_file(kobj_isp, &i2c_attr); ++ // DBG_INFO("[%s] end", __FUNCTION__); ++} ++ ++ ++int csi_create_bin_file(struct device *dev) ++{ ++ csi_dev_data *data = dev_get_platdata(dev); ++ int error = -EINVAL; ++ if (dev != NULL) { ++ //frame end ++ csi_fe_attr.private = (void*) data; ++ error = sysfs_create_bin_file(&dev->kobj, &csi_fe_attr); ++ ++ //frame start ++ csi_fs_attr.private = (void*) data; ++ error = sysfs_create_bin_file(&dev->kobj, &csi_fs_attr); ++ ++ //CSI error report interrupt ++ error = device_create_file(dev, &dev_attr_csi_dbg_mask); ++ //CSI interrupt counter ++ error = device_create_file(dev,&dev_attr_csi_ints); ++ } ++ return error; ++} ++ ++void csi_remove_bin_file(struct device *dev) ++{ ++ sysfs_remove_bin_file(&dev->kobj, &csi_fs_attr); ++ sysfs_remove_bin_file(&dev->kobj, &csi_fe_attr); ++} ++ ++static int csi_probe(struct platform_device* pdev) ++{ ++ int err; ++ int irq, u4IO_PHY_BASE; ++ unsigned int u4Bank; ++ csi_dev_data *data; ++ data = kzalloc(sizeof(csi_dev_data),GFP_KERNEL); ++ ++ of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); //get custom property, OPR base address ++ of_property_read_u32(pdev->dev.of_node, "banks", &u4Bank); //get custom property, CSI OPR bank offset ++ ++ data->reg_base = (void*)ioremap(BANK_TO_ADDR32(u4Bank)+u4IO_PHY_BASE, 0x200); ++ pr_debug("[%s] IO remap phys:0x%.8x virt: 0x%.8x\n", __FUNCTION__, ++ BANK_TO_ADDR32(u4Bank)+u4IO_PHY_BASE, ++ (u32) data->reg_base ); //(u32) isp_mem.pCSIRegs ); ++ ++ csi_create_bin_file(&pdev->dev); ++ ++ data->sysfs_dev = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR_ISP_NUM, MINOR_CSI_NUM), NULL, "csi0"); ++ isp_create_bin_file(data->sysfs_dev); ++ err = sysfs_create_link(&pdev->dev.parent->kobj,&data->sysfs_dev->kobj, "csi0"); //create symlink for older firmware version ++ ++ //TODO, init status ++ data->lock = __SPIN_LOCK_UNLOCKED("csi_lock"); ++ data->count = 0; ++ data->frame_end = false; ++ ++ //data->p_wq_fe = &csi_wq_fe; //notify csi frame end ++ data->p_wq_fe = &isp_wq_VEND; //notify isp frame end ++ //data->p_wq_fs = &csi_wq_fs; //notify csi frame start ++ data->p_wq_fs = &isp_wq_VSTART; //notify ISP frame start ++ ++ //TODO: CSI clock enable ++ data->hal_handle = HalCsi_Open(data->reg_base); ++ HalCsi_RegInit(data->hal_handle); ++ ++ pdev->dev.platform_data = (void*)data; ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); //get device IRQ#0 ++ pr_debug("request IRQ#%d\n",irq); ++ ++ if (request_irq(irq, csi_ISR, 0, "csi interrupt", (void*)data) == 0) ++ pr_debug("csi interrupt registered.\n"); ++ else ++ pr_err("failed to request IRQ#%d\n",irq); ++ ++ return 0; ++} ++ ++static int csi_remove(struct platform_device* pdev) ++{ ++ csi_dev_data *data = (csi_dev_data *)pdev->dev.platform_data; ++ HalCsi_Close(data->hal_handle); ++ iounmap(data->reg_base); ++ kfree(data); ++ csi_remove_bin_file(&pdev->dev); ++ device_destroy(msys_get_sysfs_class(),MKDEV(MAJOR_ISP_NUM, MINOR_CSI_NUM)); ++ return 0; ++} ++ ++static int csi_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ csi_dev_data *data = (csi_dev_data *)pdev->dev.platform_data; ++ HalCsi_RegUninit(data->hal_handle); ++ return 0; ++} ++ ++static int csi_resume(struct platform_device *pdev) ++{ ++ csi_dev_data *data = (csi_dev_data *)pdev->dev.platform_data; ++ HalCsi_RegInit(data->hal_handle); ++ return 0; ++} ++ ++#define INC_CSI_ERR_COUNT(name) (data->csi_err_int_count[name]++) ++irqreturn_t csi_ISR(int num, void *priv) ++{ ++ csi_dev_data *data = (csi_dev_data*)priv; ++ void* hal = data->hal_handle; ++ ++ u32 rpt_clear = 0; ++ u32 err_clear = 0; ++ u32 rpt_status = HalCsi_GetRptIntStatus(hal); ++ u32 err_status = HalCsi_GetErrorIntStatus(hal); ++ HalCsi_MaskRptInt(hal,rpt_status); ++ HalCsi_MaskErrorInt(hal,err_status); ++#if 0 ++ if(ISP_CHECKBITS(rpt_status,RPT_INT_FRAME)) //frame start interrupt ++ { ++ isp_int.vsync_start= true; //notify ISP fs ++ isp_int.frame_cnt++; ++ ISP_SETBIT(rpt_clear,RPT_INT_FRAME); ++ data->fs_int_count++; ++ wake_up_interruptible_all(data->p_wq_fs); ++ DBG_INFO_1( "[%s] FRAME INT \n", __FUNCTION__); ++ } ++#endif ++ if(ISP_CHECKBITS(rpt_status,RPT_INT_VC0)){ //frame end interrupt ++ print_timestamp("K_VE");//TEST CODE ++ isp_int.vsync_end = true; //notify ISP fe ++ isp_int.share_data->frame_state.bActive = false; ++ isp_apply_iq_at_vend(); ++ IspInputEnable(isp_int.share_data->frame_state.bIspInputEnable); ++ ISP_SETBIT(rpt_clear,RPT_INT_VC0); ++ data->vc0_int_count++; ++ wake_up_interruptible_all(data->p_wq_fe); ++ // Using menuload to write IQ table to SRAMs ++ //isp_write_iq_tbl(); ++ data->count++; ++ //record csi frame end interrupt time to PAD_FAILLING ++ getnstimeofday(&isp_int.isp_int_time[INT_PAD_VSYNC_FALLING]); ++ DBG_INFO( "[%s] VC0 INT %lld \n", __FUNCTION__,data->count); ++ } ++ ++ if(err_status){ ++ if(ISP_CHECKBITS(err_status,ERR_INT_DT)){ //frame end interrupt ++ ISP_SETBIT(err_clear,ERR_INT_DT); ++ INC_CSI_ERR_COUNT(ERR_INT_DT); ++ DBG_INFO_1( "[%s] ERR_INT_DT %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_PA_LENS)){ //frame end interrupt ++ ISP_SETBIT(err_clear,ERR_INT_PA_LENS); ++ INC_CSI_ERR_COUNT(ERR_INT_PA_LENS); ++ DBG_INFO_1( "[%s] ERR_INT_PA_LENS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_PH_LENS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_PH_LENS); ++ INC_CSI_ERR_COUNT(ERR_INT_PH_LENS); ++ DBG_INFO_1( "[%s] ERR_INT_PH_LENS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_ECC_ONEBIT)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_ECC_ONEBIT); ++ INC_CSI_ERR_COUNT(ERR_INT_ECC_ONEBIT); ++ DBG_INFO_1( "[%s] ERR_INT_ECC_ONEBIT %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_FRAME_START)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_FRAME_START); ++ INC_CSI_ERR_COUNT(ERR_INT_FRAME_START); ++ DBG_INFO_1( "[%s] ERR_INT_FRAME_START %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_FRAME_END)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_FRAME_END); ++ INC_CSI_ERR_COUNT(ERR_INT_FRAME_END); ++ DBG_INFO_1( "[%s] ERR_INT_FRAME_START %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_ECC_TWOBIT)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_ECC_TWOBIT); ++ INC_CSI_ERR_COUNT(ERR_INT_ECC_TWOBIT); ++ DBG_INFO_1( "[%s] ERR_INT_FRAME_START %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_CRC)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_CRC); ++ INC_CSI_ERR_COUNT(ERR_INT_CRC); ++ DBG_INFO_1( "[%s] ERR_INT_CRC %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_PA_WC_EQ0)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_PA_WC_EQ0); ++ INC_CSI_ERR_COUNT(ERR_INT_PA_WC_EQ0); ++ DBG_INFO_1( "[%s] ERR_INT_PA_WC_EQ0 %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_RAW10_LENS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_RAW10_LENS); ++ INC_CSI_ERR_COUNT(ERR_INT_RAW10_LENS); ++ DBG_INFO_1( "[%s] ERR_INT_RAW10_LENS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_CON_FE)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_CON_FE); ++ INC_CSI_ERR_COUNT(ERR_INT_CON_FE); ++ DBG_INFO_1( "[%s] ERR_INT_CON_FE %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_CON_FS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_CON_FS); ++ INC_CSI_ERR_COUNT(ERR_INT_CON_FS); ++ DBG_INFO_1( "[%s] ERR_INT_CON_FS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_LE)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_LE); ++ INC_CSI_ERR_COUNT(ERR_INT_LE); ++ DBG_INFO_1( "[%s] ERR_INT_LE %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_LS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_LS); ++ INC_CSI_ERR_COUNT(ERR_INT_LS); ++ DBG_INFO_1( "[%s] ERR_INT_LS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_OVERRUN)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_OVERRUN); ++ INC_CSI_ERR_COUNT(ERR_INT_OVERRUN); ++ DBG_INFO_1( "[%s] ERR_INT_OVERRUN %lld \n", __FUNCTION__,data->count); ++ } ++ } ++ ++ //clear ISR ++ HalCsi_ClearRptInt(hal,rpt_clear); //clear and unmask interrupt ++ ++ //clear Error ISR ++ HalCsi_ClearErrorInt(hal,err_clear); //clear and unmask interrupt ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init mstar_isp_init(void) ++{ ++ int ret; ++ memset((void*)&isp_int, 0, sizeof(isp_int)); ++ isp_int.sysfs_int = false; ++ ++ ret = platform_driver_register(&isp_driver); ++ if(!ret) ++ { ++ printk(KERN_INFO "[ISP] register driver success"); ++ } ++ else ++ { ++ pr_err("[ISP] register driver fail"); ++ platform_driver_unregister(&isp_driver); ++ return ret; ++ } ++ ++ ret = platform_driver_register(&csi_driver); ++ if(!ret) ++ { ++ printk(KERN_INFO "[CSI] register driver success"); ++ } ++ else ++ { ++ pr_err("[CSI] register driver fail"); ++ platform_driver_unregister(&csi_driver); ++ return ret; ++ } ++ // setup watchdog timer ++ setup_timer( &isp_watchdog_timer, isp_watchdog_callback, 0 ); ++ return 0; ++} ++ ++static void __exit mstar_isp_exit(void) ++{ ++ // remove isp watchdog timer ++ del_timer(&isp_watchdog_timer); ++ platform_driver_unregister(&isp_driver); ++ isp_remove_bin_file(); ++ pr_debug("[ISP] exit"); ++} ++ ++//isp resolution parameter ++static int __init isp_res_early_init(char *opt) ++{ ++ long res = 1; ++ if(!kstrtol(opt,10,&res)) ++ { ++ g_isp_max_res = res; ++ } ++ else ++ { ++ printk("Invaild param : isp_res=%s\n",opt); ++ } ++ return 0; ++} ++early_param("isp_res", isp_res_early_init); ++ ++//isp flags ++static int __init isp_flag_early_init(char *opt) ++{ ++ long flag = ISP_FLAG_ENABLE_DNR | ISP_FLAG_ENABLE_ROT; ++ if(!kstrtol(opt,16,&flag)) ++ { ++ g_isp_flag = flag; ++ } ++ return 0; ++} ++early_param("isp_flag", isp_flag_early_init); ++ ++module_init(mstar_isp_init); ++module_exit(mstar_isp_exit); ++ ++#endif//__DRV_ISP_C__ +diff --git a/drivers/mstar/isp/infinity/hal_isp.c b/drivers/mstar/isp/infinity/hal_isp.c +new file mode 100644 +index 00000000..9f3c96db +--- /dev/null ++++ b/drivers/mstar/isp/infinity/hal_isp.c +@@ -0,0 +1,1056 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "MsTypes.h" ++#include "ms_platform.h" ++ ++#include "hal_isp.h" ++#define PAD16BITS u32 :16 ++#define RSVD(ss,ee) u32 rsvd_##ss##_##ee[(ee) - (ss) + 1] ++ ++ //////////////////////////isp0////////////////////////////// ++ typedef struct { ++ u32 reg_en_isp :1 ; //0x00 ++ u32 reg_en_sensor :1 ; ++ u32 reg_en_isp_obc :1 ; ++ // h0000 h0000 3 3 reg_en_isp_wbg0 0 0 1 b0 rw Enable White Balance (before Denoise) ++ // # 1'b0: Disable ++ // # 1'b1: Enable ++ // ( double buffer register ) ISP_TOP 0 1 1 1 r0a0 White ++ // h0000 h0000 4 4 reg_en_isp_wbg1 0 0 1 b0 rw Enable White Balance (after Denoise) ++ // # 1'b0: Disable ++ // # 1'b1: Enable ++ // ( double buffer register ) ISP_TOP 0 1 1 1 r0a0 White ++ u32 reg_en_isp_wbg0 :1; // [3] ++ u32 reg_en_isp_wbg1 :1; // [4] ++ u32 /* reserved */ :11; ++ PAD16BITS; ++ ++ u32 reg_isp_sw_rstz :1 ; //0x01[0] ++ u32 reg_sensor_sw_rstz :1 ; ++ u32 reg_sen_pwdn :1 ; ++ u32 reg_en_isp_clk_sensor_delay :1 ; ++ u32 reg_en_isp_lsc :1 ; ++ u32 :2 ; ++ u32 reg_en_isp_denoise :1 ; // [7] ++ u32 :4 ; ++ u32 reg_en_sensor_clk :1 ; // [12] ++ u32 :2 ; ++ u32 reg_load_reg :1 ; // [15] ++ PAD16BITS; ++ ++ } __attribute__((packed, aligned(1))) isp_block_cfg; ++ ++ typedef struct { ++ u32 :14 ; //0x02 ++ u32 reg_db_batch_done :1; // [14] ++ u32 reg_db_batch_mode :1; // [15] ++ PAD16BITS; ++ ++ u32 reg_fire_mode :4 ; //0x03 ++ u32 /* reserved */ :4 ; ++ u32 reg_sensor1_rst :1 ; // [8] ++ u32 reg_sensor1_pwrdn :1 ; ++ u32 reg_sensor2_rst :1 ; ++ u32 reg_sensor2_pwrdn :1 ; ++ u32 /* reserved */ :4 ; ++ PAD16BITS; ++ } __attribute__((packed, aligned(1))) isp_camsensor_ctl; ++ ++ typedef struct { ++ u32 reg_isp_if_rmux_sel :1 /* isp_dp source mux ++ # 1'b0: from sensor_if ++ # 1'b1: from RDMA ++ */; //0x04 ++ u32 /* reserved */ :3 ; ++ u32 reg_isp_if_wmux_sel :3 /* WDMA source mux ++ # 2'd0: from sensor_if ++ # 2'd1: from isp_dp output ++ # 2'd2: from isp_dp down-sample ++ */; ++ u32 /* reserved */ :1; ++ u32 reg_isp_if_rvs_sel :1 /* isp_dp source mux ++ # 1'b0: from rmux ++ # 1'b1: from sensor freerun vs ++ */; ++ u32 reg_isp_icp_ack_tie1 :1 ; ++ u32 /* reserved */ :5; ++ u32 reg_isp_if_state_rst :1 ; ++ PAD16BITS; ++ ++ ++ //0x14 ++ u32 reg_isp_if_src_sel :1; // isp_if source mux: ++ #define ISP0_IF_SRC_PARALLEL 0x0 // 1'b0: from sensor ++ #define ISP0_IF_SRC_CSI 0x01 // 1'b1: from csi ++ u32 reg_isp2cmdq_vs_sel :1; // [1] ++ u32 :2; ++ u32 reg_isp_if_hs_mode_en :1 ; /* ISP FIFO handshaking mode enable */ ++ u32 /* reserved */ :3; ++ u32 reg_isp_if_dp_vc :2 ; /* isp_dp crop virtual channel selection */ ++ u32 /* reserved */ :2; ++ u32 reg_isp_if_wdma_vc :2 ; /* WDMA crop virtual channel selection */ ++ u32 /* reserved */ :2; ++ PAD16BITS; ++ ++ RSVD(0x06, 0x06); ++ ++ u32 reg_isp_sensor_mask :1; //0x07 ++ u32 reg_isp_if_de_mode :1; ++ u32 :14; ++ PAD16BITS; ++ } __attribute__((packed, aligned(1))) isp_src_cfg; ++ ++ typedef struct { ++ isp_block_cfg block_cfg; ++ isp_camsensor_ctl camsensor_ctl; ++ isp_src_cfg src_cfg; ++} __attribute__((packed, aligned(1))) isp0_cfg_t; ++ ++typedef struct { ++ u32 reg_c_irq_mask :16;//Interrupt Mask ++ PAD16BITS; ++ u32 reg_c_irq_force :16;//Force Interrupt Enable ++ PAD16BITS; ++ u32 reg_c_irq_clr :16;//Interrupt Clear ++ PAD16BITS; ++ u32 reg_irq_final_status:16;//Status of Interrupt on CPU side ++ PAD16BITS; ++ u32 reg_irq_raw_status:16;//Status ++ PAD16BITS; ++}isp_int1; ++ ++typedef struct { ++ u32 reg_c_irq_mask:4; ++ u32 :4; ++ u32 reg_c_irq_force:4; ++ u32 :4; ++ PAD16BITS; ++ ++ u32 reg_c_irq_clr:4; ++ u32 :12; ++ PAD16BITS; ++ ++ u32 reg_irq_final_status:4; ++ u32 :12; ++ PAD16BITS; ++ ++ u32 reg_irq_raw_status:4; ++ u32 :12; ++ PAD16BITS; ++ ++} isp_int2; ++ ++typedef struct { ++ u32 reg_c_irq_mask:8; //New Interrupt Mask ++ u32 :8; ++ PAD16BITS; ++ u32 reg_c_irq_force:8; //New Force Interrupt Enable ++ u32 reg_c_irq_clr:8; //New Interrupt Clear ++ PAD16BITS; ++ u32 reg_irq_final_status:8; //New Status of Interrupt on CPU side ++ u32 :8; ++ PAD16BITS; ++ u32 reg_irq_raw_status:8; //New Status of Interrupt on CPU side ++ u32 :8; ++ PAD16BITS; ++} isp_int3; ++ ++//static volatile u32 *isp_cpu_int; ++//static volatile u32 *isp_cpu_int2; ++//static volatile u32 *isp_cpu_int3; ++// ++//static volatile u32 *isp_int_mask; ++//static volatile u32 *isp_int_mask2; ++//static volatile u32 *isp_int_mask3; ++// ++//static volatile u32 *isp_int_clear; ++//static volatile u32 *isp_int_clear2; ++//static volatile u32 *isp_int_clear3; ++ ++static volatile isp_int1 *pISP_INT1; ++static volatile isp_int2 *pISP_INT2; ++static volatile isp_int3 *pISP_INT3; ++ ++static volatile u32 *isp_vsync_pol; ++static volatile u32 *isp_sif; ++ ++typedef struct { ++ u32 u4Low :16; ++ u32 :16; ++ u32 u4High:10; ++ u32 :22; ++} ISP_STS_ADDR_T; ++ ++typedef struct { ++ ISP_STS_ADDR_T *ae_statis_base ; ++ ISP_STS_ADDR_T *awb_statis_base; ++ ISP_STS_ADDR_T *dnr_fb_base_0 ; ++ ISP_STS_ADDR_T *dnr_fb_base_1 ; ++ ISP_STS_ADDR_T *mot_fb_base ; ++} ISP_MIU_STS_BASE; ++ ++static volatile ISP_MIU_STS_BASE isp_miu_bases; ++//static volatile u32 *isp_afsts; // 0x35 ++ ++typedef struct { ++ u32 reg_isp_load_sram_id :4;//0x00 //Load to the needed sram id ++ u32 reg_isp_sram_read_id :4;//Read the needed sram data ++ u32 reg_isp_sram_rw :1;//Read or write srams. 1: write ++ u32 reg_isp_miu2sram_en :1;//Enable miu loader. 1: enable ++ u32 reg_isp_load_register_non_full :1;//If it is full, the bit is 0 (16 entries) ++ u32 reg_isp_load_done :1;//load done ++ u32 reg_isp_load_wait_hardware_ready_en :1;//wait hardware not busy ++ u32 reg_isp_load_water_level :2;//wait fifo space == 4, 1: wait space == 8, 2: wait space == 12, 3: wait fifo empty (16) ++ u32 reg_isp_load_sw_rst :1;//software reset ++ PAD16BITS; ++ ++ u32 reg_isp_load_amount :16;//0x01 //How many 16-bits data minus one ++ PAD16BITS; ++ ++ u32 reg_isp_sram_st_addr :16;//0x02 //Load data from the sram address ++ PAD16BITS; ++ ++ u32 reg_isp_load_st_addr_l :16; //0x03 ++ PAD16BITS; ++ u32 reg_isp_load_st_addr_h :16; //0x04 //Load data from MIU 16-byte address ++ PAD16BITS; ++ ++ u32 reg_isp_sram_rd_addr :16; //0x05 //Read sram data from set address from set sram ++ PAD16BITS; ++ ++ u32 reg_isp_sram_read_data :16; //0x06 //Sram read data from corresponding address and sram ++ PAD16BITS; ++ ++ u32 reg_isp_load_register_w1r :1;//0x07 //Fire write register control into register queue ++ u32 reg_isp_load_st_w1r :1;//Fire load sram ++ u32 reg_isp_sram_read_w1r :1;//Fire read sram ++ u32 reg_isp_load_start_error_clear_w1r :1;//clear error flag ++ u32 :12; ++ PAD16BITS; ++ ++ u32 reg_isp_load_start_error :1;//0x08 //Frame start when loading is not finished yet ++ u32 :15; ++ PAD16BITS; ++} isp4_miu_mload_t; ++ ++ ++typedef struct { ++ u32 null:1; ++ u32 blinking:1; ++ u32 embedded:1; ++ u32 :5; ++ u32 :6; ++ u32 YUV4228B:1; ++ u32 :1; ++ PAD16BITS; ++ ++ u32 :8; //16:23 ++ u32 :2; ++ u32 RAW8:1; ++ u32 RAW10:1; ++ u32 RAW12:1; ++ u32 :3; ++ PAD16BITS; ++ ++ PAD16BITS; ++ PAD16BITS; ++}__attribute__((packed, aligned(1))) csi_dt; ++ ++typedef struct { ++ ++ //0x0000 ++ u32 :1; ++ u32 reg_ecc_off :1; ++ u32 reg_lane_en :4; ++ u32 reg_rm_err_sot:1; ++ u32 reg_fun_md :2; ++ u32 reg_vc_en :4; ++ u32 reg_rm_err_fs :1; ++ u32 reg_uy_vy_sel :1; ++ u32 :1; ++ PAD16BITS; ++ #define CSI_LAN0_EN 0x01 ++ #define CSI_LAN1_EN 0x02 ++ #define CSI_LAN2_EN 0x04 ++ #define CSI_LAN3_EN 0x08 ++ #define CSI_VC0_EN 0x01 ++ #define CSI_VC1_EN 0x02 ++ #define CSI_VC3_EN 0x04 ++ #define CSI_VC4_EN 0x08 ++ ++ //0x0004 ++ u32 reg_vc0_hs_mode:3; ++ u32 reg_vc1_hs_mode:3; ++ u32 reg_vc2_hs_mode:3; ++ u32 reg_vc3_hs_mode:3; ++ u32 reg_debug_sel :4; ++ PAD16BITS; ++ ++ //0x0008 ++ u32 reg_vc0_vs_mode:3; ++ u32 reg_vc1_vs_mode:3; ++ u32 reg_vc2_vs_mode:3; ++ u32 reg_vc3_vs_mode:3; ++ u32 reg_debug_en :1; ++ u32 :3; ++ PAD16BITS; ++ #define CSI_V_SYNC_MODE_FS 0x00 ++ #define CSI_V_SYNC_MODE_FE 0x01 ++ ++ //0x000C ++ u32 reg_mac_err_int_mask:15; ++ u32 :1; ++ PAD16BITS; ++ ++ //0x0010 ++ u32 reg_mac_err_int_force:15; ++ u32 :1; ++ PAD16BITS; ++ ++ //0x0014 ++ u32 reg_mac_err_int_clr:15; ++ u32 :1; ++ PAD16BITS; ++ ++ //0x0018 ++ u32 reg_mac_rpt_int_mask:7; ++ u32 :9; ++ PAD16BITS; ++ #define CSI_LINE_INT 0x01 ++ #define CSI_FRAME_INT 0x02 ++ #define CSI_VC3_FE_INT 0x08 ++ #define CSI_VC2_FE_INT 0x10 ++ #define CSI_VC1_FE_INT 0x20 ++ #define CSI_VC0_INT 0x40 //FS or FE depend on reg_mac_rpt_int_src[1] selection ++ ++ u32 reg_mac_rpt_int_force:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_mac_rpt_int_clr:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_phy_int_mask:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_phy_int_force:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_phy_int_clr:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_mac_err_int_src:15; ++ u32 :1; ++ PAD16BITS; ++ ++ u32 reg_mac_err_int_raw_src:15; ++ u32 :1; ++ PAD16BITS; ++ ++ u32 reg_mac_rpt_int_src:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_mac_rpt_int_raw_src:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_phy_int_src:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_phy_int_raw_src:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_frm_num:16; ++ PAD16BITS; ++ ++ u32 reg_line_num:16; ++ PAD16BITS; ++ ++ u32 reg_g8spd_wc:16; ++ PAD16BITS; ++ ++ u32 reg_g8spd_dt:8; ++ u32 :8; ++ PAD16BITS; ++ ++ u32 reg_mac_idle:1; ++ u32 :15; ++ PAD16BITS; ++ ++ u32 reg_1frame_trig:1; ++ u32 :15; ++ PAD16BITS; ++ ++ u32 reg_ckg_csi_mac:6; ++ u32 :2; ++ u32 reg_ckg_csi_mac_lptx:5; ++ u32 :3; ++ PAD16BITS; ++ ++ u32 reg_ckg_ns:5; ++ u32 :11; ++ PAD16BITS; ++ ++ u32 reg_csi_mac_reserved:16; ++ PAD16BITS; ++ ++ u32 reg_csi_mac_reserved1:16; ++ PAD16BITS; ++ ++ u32 reg_csi_mac_reserved2:16; ++ PAD16BITS; ++ ++ csi_dt reg_dt_en; ++ ++ u32 reg_sw_rst :1; ++ u32 reg_mac_en :1; ++ u32 reg_dont_care_dt:1; ++ u32 :13; ++ PAD16BITS; ++ ++ u32 reg_raw_l_sot_sel:2; ++ u32 reg_sot_sel :1; ++ u32 reg_eot_sel :1; ++ u32 reg_rpt_fnum_cond:1; ++ u32 reg_rpt_lnum_cond:1; ++ u32 :10; ++ PAD16BITS; ++ #define CSI_RPT_FS 0x0 //report frame start ++ #define CSI_RTP_FE 0x01 //report frame end ++ ++ u32 reg_clk_lane_fsm_sts_int_mask:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_force:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_clr:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_src:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_raw_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_mask:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_force:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_clr:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_raw_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_mask:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_force:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_clr:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_raw_src:16; ++ PAD16BITS; ++} __attribute__((packed, aligned(1))) csi_mac; ++ ++static volatile isp4_miu_mload_t *isp_miu; ++ ++static volatile u32 *isp_vdos_pitch; ++static volatile u32 *isp_vdos_addr; ++ ++static volatile void *RIUBASE_ISP[8] = {0}; ++ ++#if 1 ++static volatile u32 u4DefDisable[3] = ++{ ++ ISP_SHIFTBITS(INT_DB_UPDATE_DONE)|ISP_SHIFTBITS(INT_SR_VREF_RISING)|ISP_SHIFTBITS(INT_SR_VREF_FALLING)|ISP_SHIFTBITS(INT_ISP_BUSY)|ISP_SHIFTBITS(INT_ISP_IDLE), ++ ISP_SHIFTBITS(INT2_VDOS_EVERYLINE)|ISP_SHIFTBITS(INT2_VDOS_LINE0)|ISP_SHIFTBITS(INT2_VDOS_LINE1), ++ ISP_SHIFTBITS(INT3_AE_WIN1_DONE)|ISP_SHIFTBITS(INT3_MENULOAD_DONE)|ISP_SHIFTBITS(INT3_SW_INT_INPUT_DONE)|ISP_SHIFTBITS(INT3_SW_INT_OUTPUT_DONE) ++}; ++#else ++static volatile u32 u4DefDisable[3] = ++{ ++ ISP_SHIFTBITS(INT_DB_UPDATE_DONE)|ISP_SHIFTBITS(INT_SR_VREF_RISING)|ISP_SHIFTBITS(INT_SR_VREF_FALLING) ++ |ISP_SHIFTBITS(INT_PAD_VSYNC_RISING)|ISP_SHIFTBITS(INT_PAD_VSYNC_FALLING) ++ |ISP_SHIFTBITS(INT_ISP_FIFO_FULL)|ISP_SHIFTBITS(INT_ISP_BUSY) |ISP_SHIFTBITS(INT_ISP_IDLE) ++ |ISP_SHIFTBITS(INT_WDMA_DONE)|ISP_SHIFTBITS(INT_RDMA_DONE) |ISP_SHIFTBITS(INT_WDMA_FIFO_FULL) ++ |ISP_SHIFTBITS(INT_AF_DONE)|ISP_SHIFTBITS(INT_AWB_DONE) |ISP_SHIFTBITS(INT_AE_DONE) ++ |ISP_SHIFTBITS(INT_ISPIF_VSYNC) ++ , ++ ISP_SHIFTBITS(INT2_VDOS_EVERYLINE)|ISP_SHIFTBITS(INT2_VDOS_LINE0)|ISP_SHIFTBITS(INT2_VDOS_LINE1)|ISP_SHIFTBITS(INT2_VDOS_LINE2), ++ ISP_SHIFTBITS(INT3_AE_WIN0_DONE)|ISP_SHIFTBITS(INT3_AE_WIN1_DONE)|ISP_SHIFTBITS(INT3_MENULOAD_DONE)|ISP_SHIFTBITS(INT3_SW_INT_INPUT_DONE)|ISP_SHIFTBITS(INT3_SW_INT_OUTPUT_DONE) ++}; ++#endif ++ ++inline void HalInitRegs(void **pRegs) ++{ ++ int i = 0; ++ for (i = 0; i < 8; i++) ++ RIUBASE_ISP[i] = (void*)pRegs[i]; ++ ++ // disable double buffer ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x1*4) |= (1<<15); ++ // init frame cnt ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x7a*4) = 0; ++ ++ // structured INT ++ pISP_INT1 = (volatile isp_int1*)(RIUBASE_ISP[0] + 0x28*4); ++ pISP_INT2 = (volatile isp_int2*)(RIUBASE_ISP[0] + 0x2d*4); ++ pISP_INT3 = (volatile isp_int3*)(RIUBASE_ISP[0] + 0x25*4); ++ ++ // polarity & interface ++ isp_vsync_pol = ++ (volatile u32*)(RIUBASE_ISP[0] + 0x10*4); ++ isp_sif = ++ (volatile u32*)(RIUBASE_ISP[0] + 0x05*4); ++ ++ // statistics output address ++ isp_miu_bases.ae_statis_base = (ISP_STS_ADDR_T *)(RIUBASE_ISP[3] + 0x06*4); ++ isp_miu_bases.awb_statis_base = (ISP_STS_ADDR_T *)(RIUBASE_ISP[3] + 0x08*4); ++ isp_miu_bases.dnr_fb_base_0 = (ISP_STS_ADDR_T *)(RIUBASE_ISP[3] + 0x38*4); ++ isp_miu_bases.dnr_fb_base_1 = (ISP_STS_ADDR_T *)(RIUBASE_ISP[3] + 0x3a*4); ++ isp_miu_bases.mot_fb_base = (ISP_STS_ADDR_T *)(RIUBASE_ISP[3] + 0x3e*4); ++ //isp_afsts = (volatile u32*)(RIUBASE_ISP[5] + 0x18*4); // 0x35 ++ ++ // menuload ++ isp_miu = (isp4_miu_mload_t *)(RIUBASE_ISP[4]); ++ ++ // vdos ++ isp_vdos_pitch = (volatile u32*)(RIUBASE_ISP[6] + 0x21*4); ++ isp_vdos_addr = (volatile u32*)(RIUBASE_ISP[6] + 0x28*4); ++ ++ // disable clock gating ++ (*(u16*)(RIUBASE_ISP[0] + 0x64*4)) &= ~0x0004; ++ ++} ++ ++inline void HalISPDisableInt() ++{ ++ pISP_INT1->reg_c_irq_mask = 0xffff; ++ pISP_INT2->reg_c_irq_mask = 0x000f; ++ pISP_INT3->reg_c_irq_mask = 0x00ff; ++} ++ ++inline void HalISPEnableInt() ++{ ++ pISP_INT1->reg_c_irq_mask = u4DefDisable[0]; ++ pISP_INT2->reg_c_irq_mask = u4DefDisable[1]; ++ pISP_INT3->reg_c_irq_mask = u4DefDisable[2]; ++ ++ pISP_INT1->reg_c_irq_clr = 0xffff & ~(u4DefDisable[0]); ++ pISP_INT1->reg_c_irq_clr = 0; ++ pISP_INT2->reg_c_irq_clr = 0x00ff & ~(u4DefDisable[1]); ++ pISP_INT2->reg_c_irq_clr = 0; ++ pISP_INT3->reg_c_irq_clr = 0x00ff & ~(u4DefDisable[2]); ++ pISP_INT3->reg_c_irq_clr = 0; ++ ++} ++ ++inline void HalISPMaskIntAll() ++{ ++ pISP_INT1->reg_c_irq_mask = 0xffff; ++ pISP_INT2->reg_c_irq_mask = 0x000f; ++ pISP_INT3->reg_c_irq_mask = 0x00ff; ++ ++ pISP_INT1->reg_c_irq_clr = 0xffff & ~(u4DefDisable[0]); ++ pISP_INT2->reg_c_irq_clr = 0x000f & ~(u4DefDisable[1]); ++ pISP_INT3->reg_c_irq_clr = 0x003f & ~(u4DefDisable[2]); ++} ++ ++inline u32 HalISPGetIntStatus1() ++{ ++ return (~pISP_INT1->reg_c_irq_mask) & pISP_INT1->reg_irq_final_status; ++} ++ ++inline u32 HalISPGetIntStatus2() ++{ ++ return (~pISP_INT2->reg_c_irq_mask) & pISP_INT2->reg_irq_final_status; ++} ++ ++inline u32 HalISPGetIntStatus3() ++{ ++ return (~pISP_INT3->reg_c_irq_mask) & pISP_INT3->reg_irq_final_status; ++} ++ ++inline void HalISPMaskClear1(u32 clear) ++{ ++ pISP_INT1->reg_c_irq_clr |= clear; ++ pISP_INT1->reg_c_irq_clr = 0; ++ //pISP_INT1->reg_c_irq_mask &= ~(clear & ~u4DefDisable[0]); ++ pISP_INT1->reg_c_irq_mask = u4DefDisable[0]; ++} ++ ++inline void HalISPMaskClear2(u32 clear) ++{ ++ pISP_INT2->reg_c_irq_clr |= clear; ++ pISP_INT2->reg_c_irq_clr = 0; ++ //pISP_INT2->reg_c_irq_mask &= ~(clear & ~u4DefDisable[1]); ++ pISP_INT2->reg_c_irq_mask = u4DefDisable[1]; ++} ++ ++inline void HalISPMaskClear3(u32 clear) ++{ ++ pISP_INT3->reg_c_irq_clr |= clear; ++ pISP_INT3->reg_c_irq_clr = 0; ++ //pISP_INT3->reg_c_irq_mask &= ~(clear & ~u4DefDisable[2]); ++ pISP_INT3->reg_c_irq_mask = u4DefDisable[2]; ++} ++ ++inline void HalISPMaskInt1(u32 mask) ++{ ++ pISP_INT1->reg_c_irq_mask |= (mask|u4DefDisable[0]); ++} ++ ++inline void HalISPMaskInt2(u32 mask) ++{ ++ pISP_INT2->reg_c_irq_mask |= (mask|u4DefDisable[1]); ++} ++ ++inline void HalISPMaskInt3(u32 mask) ++{ ++ pISP_INT3->reg_c_irq_mask |= (mask|u4DefDisable[2]); ++} ++ ++inline void HalISPClearInt(volatile u32 *clear, ISP_INT_STATUS int_num) ++{ ++ *clear |= (0x01<reg_c_irq_mask = pISP_INT1->reg_c_irq_clr; ++ pISP_INT1->reg_c_irq_clr = 0; ++ pISP_INT2->reg_c_irq_mask = pISP_INT2->reg_c_irq_clr; ++ pISP_INT2->reg_c_irq_clr = 0; ++ pISP_INT3->reg_c_irq_mask = pISP_INT3->reg_c_irq_clr; ++ pISP_INT3->reg_c_irq_clr = 0; ++} ++ ++inline void HalISPClkEnable(bool enable) ++{ ++ if (enable == false) ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x66*4) |= (u16)0x04; // 0x35 ++ else ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x66*4) &= ~((u16)0x04); ++} ++ ++inline u32 HalISPGetVsyncPol() ++{ ++ return (((*isp_vsync_pol) >> VSYNC_BIT) & 0x01); ++} ++ ++inline u32 HalISPGetMIPI(void) ++{ ++ return (*isp_sif) & 0x01; ++} ++ ++inline void HalISPGetAFStat(volatile unsigned long *Stat) ++{ ++ int i = 0; ++ volatile u32* isp_afsts = (volatile u32*)(RIUBASE_ISP[5] + 0x18*4); ++ unsigned long value = 0, LSB = 0, MSB = 0; ++ if (Stat) ++ for (i = 0; i < 15*2; i+=2) { ++ LSB = *(u32 *)(isp_afsts+i)&0xffff; ++ MSB = *(u32 *)(isp_afsts+(i+1))&0xffff; ++ value = LSB | (MSB << 16); ++ Stat[i/2] = value; ++ } ++} ++ ++inline void HalISPGetVDOSPitch(volatile int *pPitch) ++{ ++ if (pPitch) ++ *pPitch = *(int *)isp_vdos_pitch; ++} ++ ++inline void HalISPGetVDOSSize(volatile int *pSize, volatile int Pitch) ++{ ++ if (pSize) ++ *pSize = Pitch * 24; // pitch * 3 * 8bytes ++} ++ ++inline void HalISPGetVDOSData(volatile unsigned long *pAddr, volatile int Size) ++{ ++ if (pAddr) ++ memcpy((void *)pAddr, (void *)isp_vdos_addr, Size); ++} ++ ++inline void HalISPSetAeBaseAddr(volatile unsigned long Addr) ++{ ++ Addr = Chip_Phys_to_MIU(Addr); ++ isp_miu_bases.ae_statis_base->u4Low = Addr>>4; ++ isp_miu_bases.ae_statis_base->u4High = Addr>>20; ++ ++ pr_debug("[ISP] AeBaseAddr 0x%08x, H:0x%04x, L:0x%04x\n", (unsigned int)Addr, (unsigned int)isp_miu_bases.ae_statis_base->u4High, ++ (unsigned int)isp_miu_bases.ae_statis_base->u4Low); ++} ++ ++inline void HalISPSetAwbBaseAddr(volatile unsigned long Addr) ++{ ++ Addr = Chip_Phys_to_MIU(Addr); ++ isp_miu_bases.awb_statis_base->u4Low = Addr>>4; ++ isp_miu_bases.awb_statis_base->u4High = Addr>>20; ++ ++ pr_debug("[ISP] AwbBaseAddr 0x%08x, H:0x%04x, L:0x%04x\n", (unsigned int)Addr, (unsigned int)isp_miu_bases.awb_statis_base->u4High, ++ (unsigned int)isp_miu_bases.awb_statis_base->u4Low); ++} ++ ++//set motion detection statisic buffer address ++inline void HalISPSetMotBaseAddr(volatile unsigned long Addr) ++{ ++ if(Addr & 0x0F) ++ { ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ Addr = Chip_Phys_to_MIU(Addr); ++ isp_miu_bases.mot_fb_base->u4Low = Addr>>4; ++ isp_miu_bases.mot_fb_base->u4High = Addr>>20; ++ pr_debug("set motion base addr = 0x%X\n",(uint32_t)Addr); ++} ++ ++inline void HalISPSetDnrFbAddr(unsigned long Addr, int id) ++{ ++ volatile ISP_STS_ADDR_T *base=0; ++ if(Addr & 0x0F){ ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ Addr = Chip_Phys_to_MIU(Addr); ++ if(id==0) ++ base = isp_miu_bases.dnr_fb_base_0; ++ else if(id==1) ++ base = isp_miu_bases.dnr_fb_base_1; ++ ++ base->u4Low = (Addr>>4) & 0xFFFF; ++ base->u4High = (Addr>>20) & 0xFFF; ++ ++ pr_debug("set DNR fb addr = 0x%X\n",(uint32_t)Addr); ++} ++ ++ ++//Loading Data From DRAM to SRAMs ++inline void HalISPMLoadWriteData(volatile unsigned int Sram_Id, volatile unsigned long Addr) ++{ ++ Addr = Chip_Phys_to_MIU(Addr); ++ ++ printk(KERN_INFO "[ISP] HalISPMLoadWriteData addr:0x%08x\n", (u32)Addr); ++ ++ //Enable the engine by turning on the register ++ isp_miu->reg_isp_miu2sram_en = 1; ++ //Set SW reset as 0 and 1 ++ isp_miu->reg_isp_load_sw_rst = 0; ++ isp_miu->reg_isp_load_sw_rst = 1; ++ //Set SW read write mode as 1 (write) ++ isp_miu->reg_isp_sram_rw = 1;// 1:write ++ //Set SRAM ID ++ isp_miu->reg_isp_load_sram_id = Sram_Id; ++ //Set MIU 16-byte start address ++ isp_miu->reg_isp_load_st_addr_l = (Addr>>4) & 0xFFFF; ++ isp_miu->reg_isp_load_st_addr_h = (Addr>>20) & 0xFFFF; ++ //Set data amount (2-byte) ++ //The number should be set as length - 1 ++ isp_miu->reg_isp_load_amount = IQ_LEN_ALSC_GAIN - 1; ++ //Set destination SRAM start SRAM address (2-byte) ++ isp_miu->reg_isp_sram_st_addr = 0x0000; ++ //Set SRAM loading parameter by setting write-one-clear ++ isp_miu->reg_isp_load_register_w1r = 1; ++ isp_miu->reg_isp_load_register_w1r = 0; ++ //Fire Loading by setting write-one-clear ++ isp_miu->reg_isp_load_st_w1r = 1; ++ ++ ++} ++ ++//Loading All table From DRAM to SRAMs ++inline void HalISPMLoadWriteAllTable(volatile unsigned long Addr, volatile unsigned long *offset) ++{ ++ ++ u32 pTableSize[IQ_MEM_NUM] = {IQ_LEN_ALSC_GAIN, IQ_LEN_ALSC_GAIN, IQ_LEN_ALSC_GAIN, ++ IQ_LEN_GAMMA_12TO10, IQ_LEN_GAMMA_12TO10, IQ_LEN_GAMMA_12TO10, ++ IQ_LEN_DEFECT_PIXEL, ++ IQ_LEN_GAMMA_10TO12, IQ_LEN_GAMMA_10TO12, IQ_LEN_GAMMA_10TO12, ++ IQ_LEN_GAMMA_CORRECT, IQ_LEN_GAMMA_CORRECT, IQ_LEN_GAMMA_CORRECT}; ++ ++ u32 i, k; ++ unsigned long tbl_addr; ++ ++ Addr = Chip_Phys_to_MIU(Addr); ++ ++ //Enable the engine by turning on the register ++ isp_miu->reg_isp_miu2sram_en = 1; ++ //Set SW reset as 0 and 1 ++ isp_miu->reg_isp_load_sw_rst = 0; //this register is active low, set 0 to reset ++ isp_miu->reg_isp_load_sw_rst = 1; ++ //Set SW read write mode as 1 (write) ++ ++ for(i = 0; i < IQ_MEM_NUM; i++) { ++ tbl_addr = Addr + offset[i]; ++ ++ isp_miu->reg_isp_sram_rw = 1;// 1:write ++ //Set SRAM ID ++ isp_miu->reg_isp_load_sram_id = i; ++ //Set MIU 16-byte start address ++ isp_miu->reg_isp_load_st_addr_l = (tbl_addr>>4) & 0xFFFF; ++ isp_miu->reg_isp_load_st_addr_h = (tbl_addr>>20) & 0xFFFF; ++ //Set data amount (2-byte) ++ //The number should be set as length - 1 ++ isp_miu->reg_isp_load_amount = pTableSize[i] - 1; ++ //Set destination SRAM start SRAM address (2-byte) ++ isp_miu->reg_isp_sram_st_addr = 0x0000; ++ //Set SRAM loading parameter by setting write-one-clear ++ isp_miu->reg_isp_load_register_w1r = 1; ++ //write 0, HW is not working, same as dummy command ++ for(k = 0; k < 32; k++) { ++ isp_miu->reg_isp_load_register_w1r = 0; ++ } ++ ++ } ++ ++ //Fire Loading by setting write-one-clear ++ isp_miu->reg_isp_load_st_w1r = 1; ++ ++} ++ ++//Read one u16 Data From SRAMs for debug ++inline void HalISPMLoadReadData(volatile unsigned int Sram_Id, volatile unsigned short Offset, volatile unsigned short *Data) ++{ ++ //Enable the engine by turning on the register ++ isp_miu->reg_isp_miu2sram_en = 1; ++ ++ //Set sram read write mode to 0 (read) ++ isp_miu->reg_isp_sram_rw = 0; ++ //Set SRAM ID ++ isp_miu->reg_isp_load_sram_id = Sram_Id; ++ ++ //Set destination SRAM read 2-byte address ++ isp_miu->reg_isp_sram_rd_addr = Offset; ++ ++ //Fire data read by setting write-one-clear ++ isp_miu->reg_isp_load_register_w1r = 1; ++ isp_miu->reg_isp_load_register_w1r = 0; ++ //Fire again due to CDC problems ++ isp_miu->reg_isp_sram_read_w1r = 1; ++ ++ *Data = isp_miu->reg_isp_sram_read_data; ++ ++} ++ ++inline u8 HalISPGetFrameDoneCount(void) ++{ ++ u16 val = *(u16*)(RIUBASE_ISP[0] + 0x7A*4); ++ return (val >> 8) & 0x7F; ++} ++ ++inline void IspReset(void) ++{ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ isp0->block_cfg.reg_isp_sw_rstz = 0; ++ isp0->block_cfg.reg_sensor_sw_rstz = 0; ++ udelay(1); ++ isp0->block_cfg.reg_sensor_sw_rstz = 1; ++ isp0->block_cfg.reg_isp_sw_rstz = 1; ++} ++ ++inline void IspDisable(void) ++{ ++ *(volatile u32*)(RIUBASE_ISP[0]) = 0; ++ IspReset(); ++} ++ ++inline void IspInputEnable(u32 enable) ++{ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ isp0->src_cfg.reg_isp_sensor_mask = enable?0:1; ++} ++ ++inline void IspAsyncEnable(u32 enable) ++{ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ isp0->src_cfg.reg_isp_icp_ack_tie1 = enable?1:0; ++} ++ ++inline void HalISPSetOBC(int u4OBC_a, int u4OBC_b) ++{ ++ *(volatile u32*)(RIUBASE_ISP[1] + 0x00*4) &= ~(0x0ff); ++ *(volatile u32*)(RIUBASE_ISP[1] + 0x00*4) |= (u4OBC_a&(0x0ff)); ++ *(volatile u32*)(RIUBASE_ISP[1] + 0x05*4) &= ~(0x0fffff); ++ *(volatile u32*)(RIUBASE_ISP[1] + 0x05*4) |= (u4OBC_b&(0x0fffff)); ++} ++ ++typedef struct { ++ u32 val :13; //0x32 ++ u32 /* reserved */ :3; ++ u32 padding :16; ++} __attribute__((packed, aligned(1))) isp_ccm_coeff; ++ ++void HalISPSetRGBCCM(const s16 *ccm_coeff) ++{ ++ int n=0; ++ volatile isp_ccm_coeff* coeff = (volatile isp_ccm_coeff*)(((char*)RIUBASE_ISP[0]) + 0x33*4); ++ for(n=0;n<9;++n) ++ { ++ coeff[n].val = ccm_coeff[n]&0x1FFF; ++ } ++} ++ ++void HalISPSetYUVCCM(const s16 *ccm_coeff) ++{ ++ int n=0; ++ volatile isp_ccm_coeff* coeff = (volatile isp_ccm_coeff*)(((char*)RIUBASE_ISP[0]) + 0x3d*4); ++ for(n=0;n<9;++n) ++ { ++ coeff[n].val = ccm_coeff[n]&0x1FFF; ++ } ++} ++ ++/////////////////////////////// CSI ////////////////////////////////// ++typedef struct ++{ ++ csi_mac *reg; ++}hal_csi_handle; ++ ++inline void* HalCsi_Open(void* reg_base) ++{ ++ hal_csi_handle *hnd = kzalloc(sizeof(hal_csi_handle),GFP_KERNEL); ++ hnd->reg = (csi_mac*) reg_base; ++ return (void*) hnd; ++} ++ ++inline void HalCsi_Close(void **handle) ++{ ++ kfree(*handle); ++ *handle = NULL; ++} ++ ++inline void HalCsi_RegInit(void* handle) ++{ ++#if 1 ++ hal_csi_handle *hnd = (hal_csi_handle*)handle; ++ //enable frame start and virtual channel 0 frame end interrupt ++ //hnd->reg->reg_mac_rpt_int_mask = 0x7F&(~(CSI_FRAME_INT|CSI_VC0_INT)); ++ hnd->reg->reg_mac_rpt_int_mask = 0x7F&(~(CSI_VC0_INT)); //enable vc0 interrupt only ++ hnd->reg->reg_rpt_fnum_cond = CSI_RPT_FS; ++ ++ //enable virtual channel 0 ++ hnd->reg->reg_lane_en = CSI_LAN0_EN | CSI_LAN1_EN; ++ hnd->reg->reg_vc_en = CSI_VC0_EN; ++ hnd->reg->reg_vc0_vs_mode = CSI_V_SYNC_MODE_FE; ++ //hnd->reg->reg_vc0_vs_mode = CSI_V_SYNC_MODE_FS; ++ ++ //CSI h-sync bug fix ++ hnd->reg->reg_vc0_hs_mode = 0x03; ++ ++ //CSI pattern gen test setting ++ hnd->reg->reg_dt_en.blinking = 0x0; ++ //hnd->reg->reg_dt_en.blinking = 0x1; ++ hnd->reg->reg_sw_rst = 0; ++ hnd->reg->reg_mac_en= 0x1; ++ hnd->reg->reg_dont_care_dt = 0x0; ++ hnd->reg->reg_mac_err_int_mask = 0x7FFF; //enable/disable csi error report interrupt ++#endif ++ ++} ++ ++inline void HalCsi_RegUninit(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ //mask all rpt interrupt ++ hnd->reg->reg_mac_rpt_int_mask = 0x7F; ++ //disable all virtual channels ++ hnd->reg->reg_vc_en = 0; ++} ++ ++inline u32 HalCsi_GetRptIntStatus(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ return hnd->reg->reg_mac_rpt_int_src; ++} ++ ++inline void HalCsi_MaskRptInt(void* handle,u32 mask) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_rpt_int_mask |= mask; ++} ++ ++//HAL , clear report interrupt ++inline void HalCsi_ClearRptInt(void* handle, u32 clear) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_rpt_int_clr |= clear; ++ hnd->reg->reg_mac_rpt_int_clr = 0; ++ hnd->reg->reg_mac_rpt_int_mask &= ~clear; ++} ++ ++inline u32 HalCsi_GetErrorIntStatus(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ return hnd->reg->reg_mac_err_int_src; ++} ++ ++inline void HalCsi_MaskErrorInt(void* handle,u32 mask) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_err_int_mask |= mask; ++} ++ ++//HAL , clear report interrupt ++inline void HalCsi_ClearErrorInt(void* handle, u32 clear) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_err_int_clr |= clear; ++ hnd->reg->reg_mac_err_int_clr = 0; ++ hnd->reg->reg_mac_err_int_mask &= ~clear; ++} ++ ++inline void HalCsi_ErrIntMaskSet(void* handle, u32 mask) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_err_int_mask = mask & 0x7FFF; ++} ++ ++inline u32 HalCsi_ErrIntMaskGet(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ return hnd->reg->reg_mac_err_int_mask; ++} +diff --git a/drivers/mstar/isp/infinity/hal_isp.h b/drivers/mstar/isp/infinity/hal_isp.h +new file mode 100644 +index 00000000..ed2f9870 +--- /dev/null ++++ b/drivers/mstar/isp/infinity/hal_isp.h +@@ -0,0 +1,194 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef __HAL_ISP_H__ ++#define __HAL_ISP_H__ ++#include "ms_platform.h" ++ ++ ++typedef enum { ++ INT_SR_VREF_RISING = 0, ++ INT_SR_VREF_FALLING = 1, ++ INT_STROBE_DONE = 2, ++ INT_DB_UPDATE_DONE = 3, ++ INT_AF_DONE = 4, ++ INT_ISP_FIFO_FULL = 5, ++ INT_ISP_BUSY = 6, ++ INT_ISP_IDLE = 7, ++ INT_AWB_DONE = 8, ++ INT_WDMA_DONE = 9, ++ INT_RDMA_DONE = 10, ++ INT_WDMA_FIFO_FULL = 11, ++ INT_PAD_VSYNC_RISING = 12, ++ INT_PAD_VSYNC_FALLING = 13, ++ INT_ISPIF_VSYNC = 14, ++ INT_AE_DONE = 15, ++ ISP_INT_MAX, ++} ISP_INT_STATUS; ++ ++typedef enum { ++ INT2_VDOS_EVERYLINE = 0, ++ INT2_VDOS_LINE0 = 1, ++ INT2_VDOS_LINE1 = 2, ++ INT2_VDOS_LINE2 = 3, ++ ISP_INT2_MAX, ++} ISP_INT2_STATUS; ++ ++typedef enum { ++ INT3_AE_WIN0_DONE = 0, ++ INT3_AE_WIN1_DONE = 1, ++ INT3_AE_BLK_ROW_INT_DONE = 2, ++ INT3_MENULOAD_DONE = 3, ++ INT3_SW_INT_INPUT_DONE = 4, ++ INT3_SW_INT_OUTPUT_DONE = 5, ++ ISP_INT3_MAX, ++} ISP_INT3_STATUS; ++ ++//Memnuload IQ Table ++typedef enum { ++ IQ_MEM_ALSC_RGAIN = 0, ++ IQ_MEM_ALSC_GGAIN = 1, ++ IQ_MEM_ALSC_BGAIN = 2, ++ IQ_MEM_GAMMA12TO10_RTBL = 3, ++ IQ_MEM_GAMMA12TO10_GTBL = 4, ++ IQ_MEM_GAMMA12TO10_BTBL = 5, ++ IQ_MEM_DEFECT_PIXEL_POS = 6, ++ IQ_MEM_GAMMA10TO12_RTBL = 7, ++ IQ_MEM_GAMMA10TO12_GTBL = 8, ++ IQ_MEM_GAMMA10TO12_BTBL = 9, ++ IQ_MEM_GAMMA_CORR_RTBL = 10, ++ IQ_MEM_GAMMA_CORR_GTBL = 11, ++ IQ_MEM_GAMMA_CORR_BTBL = 12, ++ ++ IQ_MEM_NUM = 13, ++ ++} IQ_MEM_ID; ++ ++#define VSYNC_BIT 9 ++#define MIPI_BIT 0 ++#define ISP_SHIFTBITS(a) (0x01<<(a)) ++#define ISP_CHECKBITS(a, b) ((a) & ((u32)0x01 << (b))) ++#define ISP_SETBIT(a, b) (a) |= (((u32)0x01 << (b))) ++#define ISP_CLEARBIT(a, b) (a) &= (~((u32)0x01 << (b))) ++ ++#define IQ_LEN_ALSC_GAIN (4209) ++#define IQ_LEN_GAMMA_12TO10 (256) ++#define IQ_LEN_DEFECT_PIXEL (2048) ++#define IQ_LEN_GAMMA_10TO12 (256) ++#define IQ_LEN_GAMMA_CORRECT (256) ++ ++ ++void HalInitRegs(void **pRegs); ++void HalISPMaskInt(void); ++void HalISPMaskIntAll(void); ++void HalISPClearMaskAll(void); ++void HalISPClearIntAll(void); ++void HalISPDisableInt(void); ++void HalISPEnableInt(void); ++ ++void HalISPMaskClear1(u32); ++void HalISPMaskClear2(u32); ++void HalISPMaskClear3(u32); ++ ++void HalISPClearInt(volatile u32 *clear, ISP_INT_STATUS int_num); ++ ++void HalISPMaskInt1(u32 mask); ++void HalISPMaskInt2(u32 mask); ++void HalISPMaskInt3(u32 mask); ++ ++void HalISPClearMask1(ISP_INT_STATUS int_num); ++void HalISPClearMask2(ISP_INT2_STATUS int_num); ++void HalISPClearMask3(ISP_INT3_STATUS int_num); ++ ++u32 HalISPGetIntStatus1(void); ++u32 HalISPGetIntStatus2(void); ++u32 HalISPGetIntStatus3(void); ++ ++void HalISPClkEnable(bool enable); ++u32 HalISPGetRawInt(void); ++u32 HalISPGetVsyncPol(void); ++u32 HalISPGetMIPI(void); ++ ++void HalISPGetAFStat(volatile unsigned long *Stat); ++ ++void HalISPGetVDOSPitch(volatile int *pPitch); ++void HalISPGetVDOSSize(volatile int *pSize, volatile int Pitch); ++void HalISPGetVDOSData(volatile unsigned long *pAddr, volatile int Size); ++ ++void HalISPSetAeBaseAddr(volatile unsigned long Addr); ++void HalISPSetAwbBaseAddr(volatile unsigned long Addr); ++void HalISPSetMotBaseAddr(volatile unsigned long Addr); ++void HalISPSetDnrFbAddr(unsigned long phys_addr, int id); ++ ++void HalISPMLoadWriteData(volatile unsigned int Sram_Id,volatile unsigned long Addr); ++void HalISPMLoadWriteAllTable(volatile unsigned long Addr, volatile unsigned long *offset); ++void HalISPMLoadReadData(volatile unsigned int Sram_Id, volatile unsigned short Offset, volatile unsigned short *Data); ++u8 HalISPGetFrameDoneCount(void); ++void IspReset(void); ++void IspDisable(void); ++void IspInputEnable(u32 enable); ++void IspAsyncEnable(u32 enable); ++void HalISPSetOBC(int u4OBC_a, int u4OBC_b); ++void HalISPSetRGBCCM(const s16 *ccm_coff); ++void HalISPSetYUVCCM(const s16 *ccm_coff); ++//// CSI //// ++typedef enum ++{ ++ RPT_INT_LINE = 0, ++ RPT_INT_FRAME = 1, ++ RPT_INT_VC0 = 6, ++ RPT_INT_VC1 = 5, ++ RPT_INT_VC2 = 4, ++ RPT_INT_VC4 = 3 ++}CSI_RPT_INT_STATUS; ++ ++//// CSI Error//// ++typedef enum ++{ ++ ERR_INT_DT = 0, ++ ERR_INT_PA_LENS = 1, ++ ERR_INT_PH_LENS = 2, ++ ERR_INT_ECC_ONEBIT = 3, ++ ERR_INT_FRAME_START = 4, ++ ERR_INT_FRAME_END = 5, ++ ERR_INT_ECC_TWOBIT = 6, ++ ERR_INT_CRC = 7, ++ ERR_INT_PA_WC_EQ0 = 8, ++ ERR_INT_RAW10_LENS = 9, ++ ERR_INT_CON_FE = 10, ++ ERR_INT_CON_FS = 11, ++ ERR_INT_LE = 12, ++ ERR_INT_LS = 13, ++ ERR_INT_OVERRUN = 14, ++ CSI_ERR_INT_MAX = 15, ++}CSI_ERR_INT_STATUS; ++ ++void* HalCsi_Open(void* reg_base); ++void HalCsi_Close(void **handle); ++void HalCsi_RegInit(void* handle); ++void HalCsi_RegUninit(void* handle); ++void HalCsi_ClrRptInt(void* handle); ++u32 HalCsi_GetRptIntStatus(void* handle); ++void HalCsi_MaskRptInt(void* handle,u32 mask); ++void HalCsi_ClearRptInt(void* handle, u32 clear); ++u32 HalCsi_GetErrorIntStatus(void* handle); ++void HalCsi_MaskErrorInt(void* handle,u32 mask); ++void HalCsi_ClearErrorInt(void* handle, u32 clear); ++void HalCsi_ErrIntMaskSet(void* handle,u32 mask); ++u32 HalCsi_ErrIntMaskGet(void* handle); ++#endif //__HAL_ISP_H__ +diff --git a/drivers/mstar/isp/infinity/i2c.c b/drivers/mstar/isp/infinity/i2c.c +new file mode 100644 +index 00000000..0ded34ea +--- /dev/null ++++ b/drivers/mstar/isp/infinity/i2c.c +@@ -0,0 +1,114 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_msys.h" ++#include "i2c.h" ++ ++ ++#define I2C_BUSY 1 ++#define I2C_IDLE 0 ++typedef struct ++{ ++ unsigned long al; ++ unsigned long ah; ++}addr64; ++i2c_handle_t* isp_i2c_init(u32 virt_reg_base) ++{ ++ i2c_handle_t* handle = (i2c_handle_t*) kzalloc(sizeof(i2c_handle_t),GFP_KERNEL); ++ handle->i2c_reg = (isp7_i2c_cfg_t*) virt_reg_base; ++ return handle; ++} ++ ++int isp_i2c_release(i2c_handle_t* handle) ++{ ++ kfree(handle); ++ return 0; ++} ++ ++ static int wait_i2c_done(i2c_handle_t* handle, int ms) ++{ ++ int status = 1, count = 0, interval = 20; // us ++ int timeout = ms/interval; ++ timeout = 625000000; // 1000ms@600MHz ++ do { ++ status = handle->i2c_reg->reg_m2s_status; ++ if (status != I2C_BUSY) ++ break; ++ count++; ++ } while (status == I2C_BUSY && count < timeout); ++ ++ if (count == timeout){ ++ pr_debug("%d: I2C Timeout!\n", ms); ++ return -1; ++ } else ++ return 0; ++} ++ ++int isp_i2c_array_tx(i2c_handle_t* handle, app_i2c_cfg* cfg, I2C_ARRAY *pdata, int ndata) { ++ unsigned short i, reg, rc, data; ++ short rw_addr = cfg->address; ++ volatile isp7_i2c_cfg_t *i2c_reg = handle->i2c_reg; ++ ++ for (i = 0; i < ndata; i++) { ++ reg = pdata[i].reg; ++ data = pdata[i].data; ++ ++ switch(cfg->fmt) { ++ default: ++ case I2C_FMT_A8D8: ++ i2c_reg->reg_sen_m2s_rw_d = data&0xff; ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = 0; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | ((reg&0xff) << 8); ++ break; ++ case I2C_FMT_A16D8: ++ i2c_reg->reg_sen_m2s_rw_d = data&0xff; ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = reg&0x00ff; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | (reg&0xff00); ++ break; ++ case I2C_FMT_A8D16: ++ i2c_reg->reg_sen_m2s_rw_d = ((data&0xff00) >> 8) | ((data&0x00ff) << 8); ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = 0; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | ((reg&0xff) << 8); ++ break; ++ case I2C_FMT_A16D16: ++ i2c_reg->reg_sen_m2s_rw_d = ((data&0xff00) >> 8) | ((data&0x00ff) << 8); ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = reg&0x00ff; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | (reg&0xff00); ++ break; ++ ++ } ++ ++ rc = wait_i2c_done(handle, handle->timeout); ++ ++ } ++ ++ return 0; ++ ++} ++ ++int isp_i2c_request(i2c_handle_t* handle,i2c_request *req) ++{ ++ app_i2c_cfg cfg; ++ cfg.address = req->slave_addr; ++ cfg.fmt = req->fmt; ++ cfg.speed = req->speed; ++ cfg.mode = req->mode; ++ if(!isp_i2c_array_tx(handle,&cfg,req->data,req->ndata)) ++ { ++ req->status = I2C_REQ_STATUS_DONE; ++ return 0; ++ } ++ else ++ { ++ req->status = I2C_REQ_STATUS_ERROR; ++ return -1; ++ } ++} +\ No newline at end of file +diff --git a/drivers/mstar/isp/infinity/i2c.h b/drivers/mstar/isp/infinity/i2c.h +new file mode 100644 +index 00000000..8b550a7d +--- /dev/null ++++ b/drivers/mstar/isp/infinity/i2c.h +@@ -0,0 +1,135 @@ ++#ifndef _I2C_H ++#define _I2C_H ++ ++#ifndef PAD16BITS ++#define PAD16BITS u32:16 ++#endif ++ ++struct __i2c_handle_t; ++ ++typedef struct { ++ unsigned short reg; ++ unsigned short data; ++} __attribute__((packed, aligned(1))) I2C_ARRAY; ++ ++/* ++typedef enum { ++ I2C_RW_R, ++ I2C_RW_W, ++} I2C_RW; ++ ++typedef struct { ++ I2C_RW rw; ++ unsigned short reg; ++ unsigned short data; ++} __attribute__((packed, aligned(1))) I2C_CPX_ARRAY; ++*/ ++ ++typedef enum { ++ I2C_FMT_A8D8, ++ I2C_FMT_A16D8, ++ I2C_FMT_A8D16, ++ I2C_FMT_A16D16, ++ I2C_FMT_END ++} ISP_I2C_FMT; ++ ++typedef enum { ++ I2C_LEGACY_MODE, ++ I2C_NORMAL_MODE ++} ISP_I2C_MODE; ++ ++ ++typedef struct { ++ ISP_I2C_MODE mode; ++ ISP_I2C_FMT fmt; ++ u32 speed; ++ u16 address; ++ u16 reserved; ++} __attribute__((packed, aligned(1))) app_i2c_cfg; ++ ++ ///////////////////////isp i2c/////////////////////// ++typedef struct { ++ u32 reg_i2c_en :1 ; //h78 ++ u32 /* reserved */ :7; ++ u32 reg_i2c_rstz :1 ; //h78 ++ u32 /* reserved */ :7; ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_2nd_reg_adr :8 ; //h79 ++ u32 /* reserved */ :8; ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_sw_ctrl :1 ; //h7a ++ u32 reg_sen_m2s_mode :1 ; //h7a ++ u32 reg_sen_m2s_cmd_bl :1 ; //h7a ++ u32 reg_sen_m2s_reg_adr_mode :1 ; //h7a ++ u32 /* reserved */ :10; ++ u32 reg_sda_i :1 ; //h7a ++ u32 reg_m2s_status :1 ; //h7a ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_cmd :16; //h7b ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_rw_d :16; //h7c ++ PAD16BITS; ++ ++ u32 reg_sen_prescale :10; //h7d ++ u32 /* reserved */ :6; ++ PAD16BITS; ++ ++ u32 reg_sen_sw_scl_oen :1 ; //h7e ++ u32 reg_sen_sw_sda_oen :1 ; //h7e ++ u32 /* reserved */ :14; ++ PAD16BITS; ++ ++ u32 reg_sen_rd :16; //h7f ++ PAD16BITS; ++} __attribute__((packed, aligned(1))) isp7_i2c_cfg_t; ++ ++#define I2C_REQ_STATUS_WAIT 0x00 ++#define I2C_REQ_STATUS_DONE 0x01 ++#define I2C_REQ_STATUS_ERROR 0x02 ++typedef struct ++{ ++ u32 tag; ++ u32 status; ++ u32 mode; ++ u32 fmt; ++ u32 speed; ++ u32 slave_addr; ++ u32 active_frame_id; //the frame number which will apply this data ++ u32 ndata; ++ I2C_ARRAY data[16]; ++}__attribute__((packed, aligned(1))) i2c_request; ++ ++typedef struct __i2c_handle_t { ++ int version; ++#if 0 ++ pi2c_setmode i2c_setmode; ++ pi2c_setfmt i2c_setfmt; ++ pi2c_setspeed i2c_setspeed; ++ pi2c_tx i2c_tx; ++ pi2c_rx i2c_rx; ++ pi2c_array_tx i2c_array_tx; ++ pi2c_array_tx2 i2c_array_tx2; ++ pi2c_array_rx i2c_array_rx; ++ pi2c_array_rx2 i2c_array_rx2; ++ pi2c_array_rw i2c_array_rw; ++ pi2c_array_rw2 i2c_array_rw2; ++ pi2c_get_status i2c_get_status; ++ pi2c_reset i2c_reset; ++ pi2c_enable i2c_enable; ++ pi2c_settimeout i2c_settimeout; ++#endif ++ int timeout; ++ volatile isp7_i2c_cfg_t *i2c_reg; ++ i2c_request req; ++ //MSYS_DMEM_INFO req_buf_info; ++} __attribute__((packed, aligned(1))) i2c_handle_t; ++ ++i2c_handle_t* isp_i2c_init(u32 virt_reg_base); ++int isp_i2c_release(i2c_handle_t* handle); ++int isp_i2c_array_tx(i2c_handle_t* handle, app_i2c_cfg* cfg, I2C_ARRAY *pdata, int ndata); ++int isp_i2c_request(i2c_handle_t* handle,i2c_request *req); ++#endif +diff --git a/drivers/mstar/isp/infinity3/Makefile b/drivers/mstar/isp/infinity3/Makefile +new file mode 100644 +index 00000000..eafe2518 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/Makefile +@@ -0,0 +1,13 @@ ++# ++# Makefile for MStar ISP drivers. ++# ++ ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Iarch/arm/include ++# # MsTypes.h ++EXTRA_CFLAGS += -Iinclude/linux ++ ++# files ++obj-$(CONFIG_MS_ISP_INFINITY3) += hal_isp.o drv_isp.o drv_fpga.o #i2c.o +diff --git a/drivers/mstar/isp/infinity3/MsTypes.h b/drivers/mstar/isp/infinity3/MsTypes.h +new file mode 100644 +index 00000000..b547bf26 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/MsTypes.h +@@ -0,0 +1,52 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __MS_TYPES_H__ ++#define __MS_TYPES_H__ ++ ++#include ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef U8 ++#define U8 u8 ++#endif ++ ++#ifndef U16 ++#define U16 u16 ++#endif ++ ++#ifndef U32 ++#define U32 u32 ++#endif ++ ++#if defined(__cplusplus) && defined(__GNUC__) && (__GNUC__>=4) && (__GNUC_MINOR__>=6) ++#define opaque_enum(e) enum e : int ++#else ++#define opaque_enum(e) enum e ++#endif ++#define typedef_opaque_enum(e1, e2) \ ++ opaque_enum(e1); \ ++ typedef enum e1 e2 ++ ++#endif +diff --git a/drivers/mstar/isp/infinity3/drv_fpga.c b/drivers/mstar/isp/infinity3/drv_fpga.c +new file mode 100644 +index 00000000..42a8b256 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/drv_fpga.c +@@ -0,0 +1,131 @@ ++#include "drv_fpga.h" ++#define BANK_BASE_ADDR (0x1F000000) ++unsigned int getTvtoolBankAddrVal(u32 bank, u8 offset) { ++ void __iomem *phys_addr; ++ phys_addr = (void __iomem *)IO_ADDRESS((BANK_BASE_ADDR + bank*0x200 + offset*0x04)); ++ return readl(phys_addr); ++} ++ ++unsigned int setTvtoolBankAddrVal(u32 bank, u8 offset, u16 val) { ++ void __iomem *phys_addr; ++ phys_addr = (void __iomem *)IO_ADDRESS((BANK_BASE_ADDR + bank*0x200 + (offset>>1)*0x04)); ++ writel(val, phys_addr); ++ return 0; ++} ++ ++void fpgaInit(void) ++{ ++ // ISP setting ++ //SET CCM and GAMMA ++ setTvtoolBankAddrVal(0x1302,0x64, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x66, 0x0400); ++ setTvtoolBankAddrVal(0x1302,0x68, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x6a, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x6c, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x6e, 0x0400); ++ setTvtoolBankAddrVal(0x1302,0x70, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x72, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x74, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0x76, 0x0400); ++ setTvtoolBankAddrVal(0x1302,0x78, 0x0191); //0x3C: CMC enable ++ setTvtoolBankAddrVal(0x1302,0x7a, 0x01c2); ++ setTvtoolBankAddrVal(0x1302,0x7c, 0x1e87); ++ setTvtoolBankAddrVal(0x1302,0x7e, 0x1fb7); ++ setTvtoolBankAddrVal(0x1302,0x80, 0x0107); ++ setTvtoolBankAddrVal(0x1302,0x82, 0x0204); ++ setTvtoolBankAddrVal(0x1302,0x84, 0x0064); ++ setTvtoolBankAddrVal(0x1302,0x86, 0x1f68); ++ setTvtoolBankAddrVal(0x1302,0x88, 0x1ed6); ++ setTvtoolBankAddrVal(0x1302,0x8a, 0x01c2); ++ setTvtoolBankAddrVal(0x1302,0x60, 0x0000); ++ setTvtoolBankAddrVal(0x1302,0xe2, 0x0d07); ++ setTvtoolBankAddrVal(0x1302,0xe4, 0x2701); ++ setTvtoolBankAddrVal(0x1302,0xe6, 0x040d); ++ setTvtoolBankAddrVal(0x1302,0xe0, 0x5601); //CFAI enable , DEMOSAIC ++ setTvtoolBankAddrVal(0x1302,0x22, 0x0002); //bayer ID ++ setTvtoolBankAddrVal(0x1038,0xC2, 0x0001); //0x61, enable isp clk ++ setTvtoolBankAddrVal(0x1038,0xC4, 0x010C); //0x62, enable pclk 86MHz ++ //swch 4 ++ setTvtoolBankAddrVal(0x1302,0x02, 0x0000); //0x00, reset ISP ++ setTvtoolBankAddrVal(0x1302,0x02, 0x8003); //0x01, disable double buffer ++ setTvtoolBankAddrVal(0x1302,0x08, 0x0210); //0x01, isp output async mode = 1,isp_if_rmux = RDMA, isp_wdma_mux=isp_dp ++ setTvtoolBankAddrVal(0x1302,0x0A, 0x0000); //0x0A, reg_isp_if_src_sel from sensor ++ setTvtoolBankAddrVal(0x1302,0x28, 0x04FF); //0x14, isp crop width 1280 ++ setTvtoolBankAddrVal(0x1302,0x2A, 0x02CF); //0x15, isp crop height 720 ++ setTvtoolBankAddrVal(0x1302,0x20, 0x1500); //0x10, sensor formate 10 bits , RGB , reg_sensor_hsync_polarity=low active ++ setTvtoolBankAddrVal(0x1302,0x00, 0x0003); //0x00, enable ISP ++ ++ setTvtoolBankAddrVal(0x1308,0x40, 0x0291); //0x20, enable wdma , pack mode = 16 ++ setTvtoolBankAddrVal(0x1302,0x2C, 0x0000); //0x16, wdma start x 0 ++ setTvtoolBankAddrVal(0x1302,0x2E, 0x0000); //0x17, wdma start y 0 ++ setTvtoolBankAddrVal(0x1302,0x30, 0x04FF); //0x18, wdma width 1280 ++ setTvtoolBankAddrVal(0x1302,0x32, 0x02CF); //0x19, wdma height 720 ++ setTvtoolBankAddrVal(0x1308,0x42, 0x00A0); //0x21, wdma pitch ++ setTvtoolBankAddrVal(0x1308,0x50, 0x0000); //0x29, wdma dest low addr ++ setTvtoolBankAddrVal(0x1308,0x52, 0x0040); //0x29, wdma dest high addr at 16MB ++ setTvtoolBankAddrVal(0x1308,0x60, 0x0100); //0x30, wdma trigger ++ ++ /////// ISP SENSOR ///// ++ //MCLK=12M ++ //PCLK=24M ++ //VSYNC=31ms,for reset ++ ++ //wriu -w 0x101E0a 0x2000 //reg_sr_i2c_mode,bit13,14 ++ setTvtoolBankAddrVal(0x101E, 0x0c, 0x0014); // bit [0,1,2] reg_sr_mode,[4,5]reg_i2c_mode ++ setTvtoolBankAddrVal(0x101E, 0xa0, 0x0000); // allpad_in ++ setTvtoolBankAddrVal(0x1038, 0xc2, 0x0001); // ISP CLK=123.4Mhz ++ setTvtoolBankAddrVal(0x1038, 0xc4, 0x0800); // MCLK=12Mhz ++ ++ setTvtoolBankAddrVal(0x1309, 0xF0, 0x0101); //reg_i2c enable ++ setTvtoolBankAddrVal(0x1309, 0xF2, 0x0000); //reg_sen_m2s_2nd_reg_adr ++ setTvtoolBankAddrVal(0x1309, 0xF4, 0x0000); //reg_sen_m2s_reg_adr_mode 8=16bit series mode ; eg_sen_m2s_cmd_bl 16bit ++ setTvtoolBankAddrVal(0x1309, 0xFA, 0x0200); //0x0038 //reg_sen_prescale ++ ++ setTvtoolBankAddrVal(0x1302, 0x20, 0x5500); ++ //RST H, PWR H ++ setTvtoolBankAddrVal(0x1302, 0x06, 0x0100); ++ mdelay(100); ++ setTvtoolBankAddrVal(0x1302, 0x06, 0x0000); ++ mdelay(100); ++ setTvtoolBankAddrVal(0x1302, 0x06, 0x0100); ++ ++ //read ID from 0x1c,0x1d ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x1c61); //check 0x1309fe=0x7f(High byte) ++ mdelay(300); ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x1d61); //check 0x1309fe=0xa2(Low byte) ++ mdelay(300); ++ ++ setTvtoolBankAddrVal(0x1309, 0xf8, 0x0054); //clock ++ setTvtoolBankAddrVal(0x1309, 0xf2, 0x0000); ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x5c60); ++ mdelay(300); ++ ++ setTvtoolBankAddrVal(0x1309, 0xf8, 0x000f); //clock ++ setTvtoolBankAddrVal(0x1309, 0xf2, 0x0000); ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x1160); ++ mdelay(300); ++ ++ //write sensor slave=0x60 , reg=0x97, data=0x0A , DISABLE COLOR BAR ++ setTvtoolBankAddrVal(0x1309, 0xf8, 0x0000); //disable color bar ++ setTvtoolBankAddrVal(0x1309, 0xf2, 0x0000); ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x9760); ++ mdelay(300); ++ ++ //write sensor slave=0x60 , reg=0x12, data=0x00 , DISABLE COLOR BAR ++ setTvtoolBankAddrVal(0x1309, 0xf8, 0x0000); //disable color bar ++ setTvtoolBankAddrVal(0x1309, 0xf2, 0x0000); ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x1260); ++ mdelay(300); ++ ++ //write sensor slave=0x60 , reg=0x97, data=0x0A , DISABLE COLOR BAR ++ setTvtoolBankAddrVal(0x1309, 0xf8, 0x0000); //disable color bar ++ setTvtoolBankAddrVal(0x1309, 0xf2, 0x0000); ++ setTvtoolBankAddrVal(0x1309, 0xf6, 0x9760); ++ mdelay(300); ++ ++#if 0 ++ int i; ++ for (i=0;i<0x80;i++) ++ pr_err("bank 0x1302, offset %#x, val = %#x\n", i, getTvtoolBankAddrVal(0x1302,i)); ++#endif ++} +diff --git a/drivers/mstar/isp/infinity3/drv_fpga.h b/drivers/mstar/isp/infinity3/drv_fpga.h +new file mode 100644 +index 00000000..b0708631 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/drv_fpga.h +@@ -0,0 +1,11 @@ ++#ifndef __FPGA_REG__ ++#define __FPGA_REG__ ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++unsigned int getTvtoolBankAddrVal(u32 bank, u8 offset); ++unsigned int setTvtoolBankAddrVal(u32 bank, u8 offset, u16 val); ++void fpgaInit(void); ++#endif +diff --git a/drivers/mstar/isp/infinity3/drv_isp.c b/drivers/mstar/isp/infinity3/drv_isp.c +new file mode 100644 +index 00000000..88684c0a +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/drv_isp.c +@@ -0,0 +1,3373 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __DRV_ISP_C__ ++#define __DRV_ISP_C__ ++ ++#define ISP_DBG 0 ++#if ISP_DBG ++#define DEBUG ++#endif ++ ++// FPGA ISP IP verifiy ++//#define FPGA_VERIFY ++ ++/*--------------------------------------------------------------------------*/ ++/* INCLUDE FILE */ ++/*--------------------------------------------------------------------------*/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++//#include ++#include ++ ++#include ++#include ++ ++#include "ms_msys.h" ++#include "hal_isp.h" ++#include "i2c.h" ++#if defined(FPGA_VERIFY) ++#include "drv_fpga.h" ++#endif ++/*--------------------------------------------------------------------------*/ ++ ++////////////////////////////////////////////////////////// ++ ++/*--------------------------------------------------------------------------*/ ++/* CONSTANT DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++#if ISP_DBG ++#define DBG_INFO pr_debug ++#define DBG_INFO_1 pr_debug ++#define DBG_INFO_2 pr_debug ++#else ++#define DBG_INFO(fmt, arg...) {} ++#define DBG_INFO_1 DBG_INFO ++#define DBG_INFO_2 DBG_INFO ++#endif ++ ++ ++/*--------------------------------------------------------------------------*/ ++/* MACRO DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++#define ISP_BIN_ATTR(_a,_b) \ ++ struct bin_attribute _a##_attr = { \ ++ .attr = { .name = __stringify(_a), \ ++ .mode = _b, }, \ ++ .size = 0, \ ++ .read = _a##_read, \ ++ .write = _a##_write, \ ++} ++ ++#define DEV_ATTR(_name,_mode,_size) \ ++ struct bin_attribute _name##_attr = { \ ++ .attr = { .name = __stringify(_name), \ ++ .mode = _mode, }, \ ++ .size = _size, \ ++ .read = _name##_read, \ ++ .write = _name##_write, \ ++} ++ ++#define C_IN(lock) local_irq_save(flags) ++#define C_OUT(lock) local_irq_restore(flags) ++ ++//--------- ISP 3A statistics buffer ---------// ++#define AE_WIN_SIZE (128*90) ++#define AWB_WIN_SIZE (128*90) ++#define AE_HIST_R_SIZE 80 ++#define AE_HIST_G_SIZE 80 ++#define AE_HIST_B_SIZE 80 ++#define AE_HIST_WIN0_SIZE 256 ++#define AE_HIST_WIN1_SIZE 256 ++//R,G,B,Y 4bytes statistics ++#define AE_STATIS_SIZE (AE_WIN_SIZE*4) ++#define HISTO_STATIS_SIZE (AE_HIST_R_SIZE+AE_HIST_G_SIZE+AE_HIST_B_SIZE+AE_HIST_WIN0_SIZE+AE_HIST_WIN1_SIZE) ++#define AF_STATIS_SIZE (60*4) ++#define AWB_STATIS_SIZE (AWB_WIN_SIZE*3) ++#define MOT_STATIS_SIZE (168*168) //for 2688x2688 image ++#define RGBIR_STATIS_SIZE (256*4) //for 2688x2688 image ++ ++typedef struct ++{ ++ char ae[AE_STATIS_SIZE] __attribute__((aligned(16))); ++ char awb[AWB_STATIS_SIZE] __attribute__((aligned(16))); ++ char af[AF_STATIS_SIZE] __attribute__((aligned(16))); ++ char histo[HISTO_STATIS_SIZE] __attribute__((aligned(16))); //histogram ++ char mot[MOT_STATIS_SIZE] __attribute__((aligned(16))); //motion detection ++ char rgbir[RGBIR_STATIS_SIZE] __attribute__((aligned(16))); ++}__attribute__((packed, aligned(16))) ISP_STATIS_MEM; ++ ++//#define DNR_FB_SIZE (((1920+191)/192) * ((1080+15)>>4) * 256 * 16) ++/*--------------------------------------------------------------------------*/ ++/* DATA TYPE DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++typedef struct ++{ ++ u32 frame_interval; ++ u32 fps; ++ u32 prev_tick_count; ++}__attribute__((packed, aligned(1))) FPS_INFO; ++ ++typedef struct _isp_ccm_coff ++{ ++ s16 dirty; ++ s16 ccm[9]; ++}isp_ccm_coff; ++ ++typedef struct _isp_ae_dgain ++{ ++ s16 dirty; ++ s16 enable; ++ u32 gain; ++}isp_ae_dgain; ++ ++typedef struct _isp_fifo_mask ++{ ++ s16 dirty; ++ s16 enable; ++}isp_fifo_mask; ++ ++typedef struct { ++ u32 frame_cnt; ++ u8 sysfs_int; ++ u8 vsync_start; ++ u8 vsync_end; ++ u8 ae; ++ u8 ae_win0; ++ u8 ae_row_int; ++ u8 awb; ++ u8 epoll_event; ++ u8 af; ++ u8 isp_busy; ++ u8 isp_idle; ++ u8 isp_fifofull; ++ u8 wdma_fifofull; ++ u8 rdma_done; ++ u8 wdma_done; ++ u8 eis; ++ u8 scl_fe; ++ ++ unsigned long AE_Lum[64]; // 8x8 windows ++ unsigned long AE_Hist[64]; // 8x8 windows ++ unsigned long AF_Stat[5*3]; // 5 windows *( R+G+B) ++ unsigned long AWB_Stat[80]; // 5 windows ++ ++ //FRAME_STATE *FrameState; ++ ISP_SHARE_DATA *share_data; ++ ++ u32 isp_int_count[ISP_INT_MAX]; ++ u32 isp_int2_count[ISP_INT2_MAX]; ++ u32 isp_int3_count[ISP_INT3_MAX]; ++ ++ struct timespec isp_int_time[ISP_INT_MAX]; ++ struct timespec isp_int2_time[ISP_INT2_MAX]; ++ struct timespec isp_int3_time[ISP_INT3_MAX]; ++ ++ u8 hw_frame_cnt; ++ u32 int_cnt; ++ ++ FPS_INFO fps; ++ isp_ccm_coff rgb_ccm; //RGB2YUV matrix ++ isp_ccm_coff yuv_ccm; //CCM ++ isp_ae_dgain dgain; //AE dgain ++ isp_isr_ae_img_info ae_img_info; //ae statistic block setting ++ isp_fifo_mask fifo_mask; ++} ISP_INT_DATA; ++ ++typedef struct { ++ void *pISPRegs[10]; ++ void *pCSIRegs; ++ MSYS_DMEM_INFO Base_Meminfo; ++ MSYS_DMEM_INFO DNR_FB_Meminfo[2]; ++ MSYS_DMEM_INFO ShareData_Meminfo; ++} ISP_MEM_BUFF; ++ ++typedef enum ++{ ++ ISP_INFO_ID_AE=0, ++ ISP_INFO_ID_AWB, ++ ISP_INFO_ID_IQ, ++ ISP_INFO_ID_MAX, ++}ISP_INFO_ID; ++ ++typedef struct _isp_dev_data ++{ ++ struct miscdevice isp_dev; ++ struct device * sysfs_dev; //for node /sys/class/mstar/ ++ struct clk *clk_isp; //isp clock ++ struct clk *clk_sr; //pclk ++ struct clk *clk_sr_mclk; //sensor mclk ++ struct clk *clk_csi_mac; ++ ISP_INT_DATA *isp_int; ++ ISP_MEM_BUFF *isp_mem; ++ char isp_info_str[ISP_INFO_ID_MAX][1024]; ++}isp_dev_data; ++ ++#define BANK_TO_ADDR32(b) (b<<9) ++#define BANK_SIZE 0x200 ++ ++static ISP_INT_DATA isp_int; ++static ISP_MEM_BUFF isp_mem; ++//static i2c_handle_t isp_i2c; ++ ++void reset_isp_int(ISP_INT_DATA *p_isp_int) //reset isp_int struct ++{ ++ //p_isp_int->frame_cnt = 0; ++ p_isp_int->sysfs_int = 0; ++ p_isp_int->vsync_start = 0; ++ p_isp_int->vsync_end = 0; ++ p_isp_int->ae = 0; ++ p_isp_int->ae_win0 = 0; ++ p_isp_int->ae_row_int = 0; ++ p_isp_int->awb = 0; ++ p_isp_int->epoll_event = 0; ++ p_isp_int->af = 0; ++ p_isp_int->isp_busy = 0; ++ p_isp_int->isp_idle = 0; ++ p_isp_int->isp_fifofull = 0; ++ p_isp_int->wdma_fifofull = 0; ++ p_isp_int->rdma_done = 0; ++ p_isp_int->wdma_done = 0; ++ p_isp_int->eis = 0; ++ ++ memset(p_isp_int->AE_Lum,0,sizeof(p_isp_int->AE_Lum)); ++ memset(p_isp_int->AE_Hist,0,sizeof(p_isp_int->AE_Hist)); ++ memset(p_isp_int->AF_Stat,0,sizeof(p_isp_int->AF_Stat)); ++ memset(p_isp_int->AWB_Stat,0,sizeof(p_isp_int->AF_Stat)); ++ ++ p_isp_int->share_data->frame_state.bIspInputEnable = true; ++} ++ ++void isp_async(u32 enable) ++{ ++ IspAsyncEnable(enable); ++} ++ ++void fps_init(FPS_INFO *info) ++{ ++ memset(info,0,sizeof(FPS_INFO)); ++} ++ ++u32 fps_update(FPS_INFO *info) ++{ ++ u32 dt; ++ struct timespec ts; ++ getnstimeofday(&ts); ++ ++ if(ts.tv_nsec>info->prev_tick_count) ++ { ++ dt = ts.tv_nsec - info->prev_tick_count; ++ } ++ else ++ { ++ dt = 0xFFFFFFFF - info->prev_tick_count + ts.tv_nsec; ++ } ++ ++ if(dt<1000000*500) //dt < 500ms ++ { ++ info->frame_interval = dt; ++ } ++ ++ info->prev_tick_count = ts.tv_nsec; ++ info->fps = 1000000000/dt; ++ return info->fps; ++} ++//#define TIMING_DBG_MSG ++#ifdef TIMING_DBG_MSG ++void print_timestamp(char* msg) ++{ ++ struct timespec ts; ++ getnstimeofday(&ts); ++ printk("%d:%lu:%s\r\n", isp_int.frame_cnt, (ts.tv_sec * 1000000)+(ts.tv_nsec/1000), msg); ++} ++#else ++#define print_timestamp(a) ++#endif ++ ++typedef struct ++{ ++ u64 count; ++ spinlock_t lock; ++ u8 frame_end; //frame end interrupt flag ++ u8 frame_start; ++ ++ u32 fs_int_count; //frame start interrput count ++ u32 vc0_int_count; //virtual channel 0 count ++ ++ wait_queue_head_t *p_wq_fe; ++ wait_queue_head_t *p_wq_fs; ++ ++ //HAL ++ void* reg_base; ++ void* hal_handle; ++ ++ u32 csi_err_int_count[CSI_ERR_INT_MAX]; ++ struct device *sysfs_dev; ++}csi_dev_data; ++ ++/*--------------------------------------------------------------------------*/ ++/* VARIABLE DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++irqreturn_t isp_ISR(int num, void *priv); ++static int isp_probe(struct platform_device* pdev); ++static int isp_remove(struct platform_device* pdev ); ++static int isp_suspend(struct platform_device *pdev, pm_message_t state); ++static int isp_resume(struct platform_device *pdev); ++int isp_create_bin_file(struct device *dev); ++int isp_create_bin_file_(struct device *dev); ++ ++static struct of_device_id isp_dt_ids[] = { ++ {.compatible = "isp"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, isp_dt_ids); ++ ++irqreturn_t csi_ISR(int num, void *priv); ++static int csi_probe(struct platform_device* pdev); ++static int csi_remove(struct platform_device* pdev ); ++static int csi_suspend(struct platform_device *pdev, pm_message_t state); ++static int csi_resume(struct platform_device *pdev); ++ ++static struct of_device_id csi_dt_ids[] = { ++ {.compatible = "csi"}, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, csi_dt_ids); ++ ++static struct platform_device *isp_device; ++ ++static struct platform_driver isp_driver = ++{ ++ .probe = isp_probe, ++ .remove = isp_remove, ++ .suspend = isp_suspend, ++ .resume = isp_resume, ++ .driver = { ++ .name = "isp", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(isp_dt_ids), ++ }, ++}; ++ ++static struct platform_driver csi_driver = ++{ ++ .probe = csi_probe, ++ .remove = csi_remove, ++ .suspend = csi_suspend, ++ .resume = csi_resume, ++ .driver = { ++ .name = "csi", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(csi_dt_ids), ++ }, ++}; ++ ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_WDMA_FIFO_FULL); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_FIFO_FULL); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_RDMA_DONE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_WDMA_DONE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_IDLE); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ISP_BUSY); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_VSTART); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_VEND); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae_win0); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae_win1); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_ae_row_int); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_awb); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_af); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_eis); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_sw_int_in); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_sw_int_out); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_hit_line_count1); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_hit_line_count2); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_hit_line_count3); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_hdr_histo_done); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_rgbir_histo_done); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_awb_row_done); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_histo_row_done); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_scl_fe); ++static DECLARE_WAIT_QUEUE_HEAD(isp_wq_epoll_event); ++ ++//CSI// ++static DECLARE_WAIT_QUEUE_HEAD(csi_wq_fe); ++static DECLARE_WAIT_QUEUE_HEAD(csi_wq_fs); ++ ++static struct kobject *kobj_isp = NULL; ++ ++ ++/*--------------------------------------------------------------------------*/ ++/* LOCAL FUNCTION PROTOTYPE DECLARATION AND DEFINITION */ ++/*--------------------------------------------------------------------------*/ ++ ++extern int msys_request_dmem(MSYS_DMEM_INFO *mem_info); ++extern void Drv_SCLIRQ_SetDropFrameFromISP(unsigned char u8Count); ++ ++#define member_size(type, member) sizeof(((type *)0)->member) ++static void isp_ae_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,ae),member_size(ISP_STATIS_MEM,ae)); ++} ++ ++static void isp_awb_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,awb),member_size(ISP_STATIS_MEM,awb)); ++} ++ ++static void isp_af_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,af),member_size(ISP_STATIS_MEM,af)); ++} ++ ++static void isp_mot_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,mot),member_size(ISP_STATIS_MEM,mot)); ++} ++ ++static void isp_histo_cache_invalidate(void) ++{ ++ Chip_Inv_Cache_Range((unsigned long)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,histo),member_size(ISP_STATIS_MEM,histo)); ++} ++ ++#if 1 ++//set DNR frame buffer address ++static int isp_set_dnr_fb_base(MSYS_DMEM_INFO *mem_info,int id) ++{ ++ u32 phys_addr; ++ phys_addr = (unsigned long)mem_info->phys; ++ DBG_INFO("DNR_%d PHYS=0x%llX,VIRT=0x%llX\n",id,mem_info->phys,mem_info->kvirt); ++ HalISPSetDnrFbAddr(phys_addr,id); ++ return 0; ++} ++#endif ++ ++u32 g_isp_flag = ISP_FB_ROT | ISP_FB_DNR; ++u32 g_isp_max_res = 3; //max resolutioin, 0:1280x720 1:1920x1080, 2:2048x1536, 3:2688x1520 ++static unsigned int get_dnr_buffer_size(void) ++{ ++ u32 width = 2688; ++ u32 height = 1520; ++ switch(g_isp_max_res) ++ { ++ case 0: //1270x720 ++ width = 1280; ++ height = 720; ++ break; ++ case 1://1920x1080 ++ width = 1920; ++ height = 1080; ++ break; ++ case 2://2048x1536 , 3M ++ width = 2048; ++ height = 1536; ++ break; ++ case 3://2688x1520 , 4M ++ width = 2688; ++ height = 1520; ++ break; ++ case 4://2688x1520 , 4M ++ width = 2688; ++ height = 1520; ++ break; ++ case 5://2592x1944 , 5M ++ width = 2592; ++ height = 1944; ++ } ++ pr_info("[ISP] max_res= %dx%d\n",width,height); ++ return (((width+191)/192) * ((height+15)>>4) * 256 * 16); ++} ++static unsigned int get_dnr_buffer_num(void) ++{ ++ if(g_isp_flag&ISP_FB_DNR) ++ { ++ return (g_isp_flag&ISP_FB_ROT)?2:1; ++ } ++ else ++ return 0; ++} ++ ++static int IspInitDnrFB(u32 nImgW,u32 nImgH,u32 nNum) ++{ ++ int i; ++ int ret=0; ++ int nBufSize = (((nImgW+191)/192) * ((nImgH+15)>>4) * 256 * 16); ++ ++ if(nNum>get_dnr_buffer_num()) ++ { ++ pr_info("[ISP]DNR buffer number exceed max number. num=%d buffers\n",nNum); ++ return -1; ++ } ++ ++ if(nBufSize>get_dnr_buffer_size()) ++ { ++ pr_info("[ISP]DNR buffer size exceed max size. size=%d bytes\n",nBufSize); ++ return -1; ++ } ++ ++ for(i=0;i<2;++i) ++ { ++ if(isp_mem.DNR_FB_Meminfo[i].phys) ++ { ++ msys_release_dmem(&isp_mem.DNR_FB_Meminfo[i]); ++ memset(&isp_mem.DNR_FB_Meminfo[i],0,sizeof(isp_mem.DNR_FB_Meminfo[i])); ++ } ++ } ++ ++ if(nNum==1)//only DNR buffer ++ { ++ int err = 0; ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[0]; ++ sprintf(info->name,"ISP_DNR_%d",0); ++ info->length = nBufSize; ++ pr_info("ISP DNR buffer#%d size = 0x%X\n",0,info->length); ++ if(msys_request_dmem(info)) ++ { ++ pr_err("ISP failed to request DNR frame buffer. err=0x%X\n",err); ++ ret = -1; ++ } ++ else ++ { ++ isp_set_dnr_fb_base(info,0); ++ isp_set_dnr_fb_base(info,1); ++ HalISPSetDnrUbound((unsigned long)(info->phys+info->length)); ++ } ++ } ++ else if(nNum==2)//DNR + ROT buffer ++ { ++ unsigned long max_addr = 0; ++ for(i=0;i<2;++i) ++ { ++ int err = 0; ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[i]; ++ sprintf(info->name,"ISP_DNR_%d",i); ++ info->length = nBufSize; ++ pr_info("ISP DNR buffer#%d size = 0x%X\n",i,info->length); ++ if(msys_request_dmem(info)) ++ { ++ pr_err("ISP failed to request DNR frame buffer. err=0x%X\n",err); ++ ret = -1; ++ break; ++ } ++ isp_set_dnr_fb_base(info,i); ++ max_addr = max_addr > info->phys ? max_addr:info->phys; ++ HalISPSetDnrUbound((unsigned long)(max_addr+info->length)); ++ } ++ } ++ return ret; ++} ++ ++static int isp_init_buff(void) { ++ //int i; ++ pr_debug("[ISP] isp_init_buff\n"); ++ isp_mem.Base_Meminfo.length = sizeof(ISP_STATIS_MEM); ++ ++ sprintf(isp_mem.Base_Meminfo.name,"ISP_base"); ++ if(0 > msys_request_dmem(&isp_mem.Base_Meminfo)) ++ { ++ pr_err("ISP failed to request Base_Meminfo buffer.\n"); ++ return -1; ++ } ++ ++ DBG_INFO("mem base phyaddr:0x%08x, viraddr:0x%08x, len:%d", (unsigned int)isp_mem.Base_Meminfo.phys, ++ (unsigned int)isp_mem.Base_Meminfo.kvirt,isp_mem.Base_Meminfo.length); ++ ++ ////////// isp share data //////////////// ++ sprintf(isp_mem.ShareData_Meminfo.name, "ISP_SHARE_DATA"); ++ isp_int.share_data = kmalloc(sizeof(ISP_SHARE_DATA),GFP_KERNEL); ++ memset(isp_int.share_data, 0, sizeof(ISP_SHARE_DATA)); ++ isp_mem.ShareData_Meminfo.kvirt = (unsigned long)isp_int.share_data; ++ isp_mem.ShareData_Meminfo.phys = virt_to_phys(isp_int.share_data); ++ isp_mem.ShareData_Meminfo.length = sizeof(ISP_SHARE_DATA); ++ ++ pr_info("ShareData_Meminfo phyaddr:0x%08llx, viraddr:0x%08llx, len:%#x\n", ++ isp_mem.ShareData_Meminfo.phys, ++ isp_mem.ShareData_Meminfo.kvirt, isp_mem.ShareData_Meminfo.length); ++ ++ HalISPSetAeBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,ae), offsetof(ISP_STATIS_MEM,awb)); ++ HalISPSetAwbBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,awb), offsetof(ISP_STATIS_MEM,af)-offsetof(ISP_STATIS_MEM,awb)); ++ HalISPSetAfBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,af), offsetof(ISP_STATIS_MEM,histo)-offsetof(ISP_STATIS_MEM,af)); ++ HalISPSetHistoBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,histo), offsetof(ISP_STATIS_MEM,mot)-offsetof(ISP_STATIS_MEM,histo)); ++ HalISPSetMotBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,mot), offsetof(ISP_STATIS_MEM,rgbir)-offsetof(ISP_STATIS_MEM,mot)); ++ HalISPSetRgbIRBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,rgbir), sizeof(ISP_STATIS_MEM)-offsetof(ISP_STATIS_MEM,rgbir)); ++ ++ pr_info("AE Base: virt=0x%X size=0x%X\n",(unsigned int)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,ae), offsetof(ISP_STATIS_MEM,awb)); ++ pr_info("AWB Base: virt=0x%X size=0x%X\n",(unsigned int)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,awb), offsetof(ISP_STATIS_MEM,af)-offsetof(ISP_STATIS_MEM,awb)); ++ pr_info("AF Base: virt=0x%X size=0x%X\n",(unsigned int)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,af), offsetof(ISP_STATIS_MEM,histo)-offsetof(ISP_STATIS_MEM,af)); ++ pr_info("HISTO Base: virt=0x%X size=0x%X\n",(unsigned int)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,histo), offsetof(ISP_STATIS_MEM,mot)-offsetof(ISP_STATIS_MEM,histo)); ++ pr_info("MOT Base: virt=0x%X size=0x%X\n",(unsigned int)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,mot), offsetof(ISP_STATIS_MEM,rgbir)-offsetof(ISP_STATIS_MEM,mot)); ++ pr_info("RGBIR Base: virt=0x%X size=0x%X\n",(unsigned int)isp_mem.Base_Meminfo.kvirt + offsetof(ISP_STATIS_MEM,rgbir), sizeof(ISP_STATIS_MEM)-offsetof(ISP_STATIS_MEM,rgbir)); ++ ++#if 0 ++ { ++ ////////////////////////// ++ // request DNR frame buffer // ++ ////////////////////////// ++ int i; ++ int num_dnr_buf = get_dnr_buffer_num(); ++ if(num_dnr_buf==1) ++ { ++ int err = 0; ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[0]; ++ sprintf(info->name,"ISP_DNR_%d",0); ++ info->length = get_dnr_buffer_size(); ++ //pr_info("ISP DNR buffer#%d size = 0x%X\n",0,info->length); ++ if(msys_request_dmem(info)) ++ { ++ pr_err("ISP failed to request DNR frame buffer. err=0x%X\n",err); ++ } ++ else ++ { ++ isp_set_dnr_fb_base(info,0); ++ isp_set_dnr_fb_base(info,1); ++ } ++ } ++ else if(num_dnr_buf==2) ++ { ++ for(i=0;i<2;++i) ++ { ++ int err = 0; ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[i]; ++ sprintf(info->name,"ISP_DNR_%d",i); ++ info->length = get_dnr_buffer_size(); ++ //pr_info("ISP DNR buffer#%d size = 0x%X\n",i,info->length); ++ if(msys_request_dmem(info)) ++ { ++ pr_err("ISP failed to request DNR frame buffer. err=0x%X\n",err); ++ break; ++ } ++ isp_set_dnr_fb_base(info,i); ++ } ++ } ++ } ++#endif ++ return 0; ++} ++ ++static int isp_restore_buff(void) ++{ ++ int i; ++ ++ HalISPSetAeBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,ae), offsetof(ISP_STATIS_MEM,awb)); ++ HalISPSetAwbBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,awb), offsetof(ISP_STATIS_MEM,af)-offsetof(ISP_STATIS_MEM,awb)); ++ HalISPSetAfBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,af), offsetof(ISP_STATIS_MEM,histo)-offsetof(ISP_STATIS_MEM,af)); ++ HalISPSetHistoBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,histo), offsetof(ISP_STATIS_MEM,mot)-offsetof(ISP_STATIS_MEM,histo)); ++ HalISPSetMotBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,mot), offsetof(ISP_STATIS_MEM,rgbir)-offsetof(ISP_STATIS_MEM,mot)); ++ HalISPSetRgbIRBaseAddr((unsigned long)isp_mem.Base_Meminfo.phys + offsetof(ISP_STATIS_MEM,rgbir), sizeof(ISP_STATIS_MEM)-offsetof(ISP_STATIS_MEM,rgbir)); ++ ++ for(i=0;i<2;++i) ++ { ++ MSYS_DMEM_INFO *info = &isp_mem.DNR_FB_Meminfo[i]; ++ isp_set_dnr_fb_base(info,i); ++ } ++ ++ return 0; ++} ++static int isp_open(struct inode *inode, struct file *fp) ++{ ++ fp->private_data = isp_device->dev.platform_data; ++ return 0; ++} ++ ++static int isp_release(struct inode *inode, struct file *fp) ++{ ++ fp->private_data = 0; ++ return 0; ++} ++static ssize_t isp_fread(struct file *fp, char __user *buf, size_t size, loff_t *ppos) ++{ ++ return 0; ++} ++ ++static ssize_t isp_fwrite(struct file *fp,const char __user *buf, size_t size, loff_t *ppos) ++{ ++ return 0; ++} ++ ++static long isp_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) ++{ ++ isp_dev_data *data = (isp_dev_data*) fp->private_data; ++ struct clk *_clk=0; ++ ++ pr_debug("ISP IOCTL +\n"); ++ if (_IOC_TYPE(cmd) != ISP_IOCTL_MAGIC) return -ENOTTY; ++ switch(cmd) ++ { ++ case IOCTL_ISP_CLOCK_CTL: ++ { ++ isp_ioctl_clock_ctl ctl; ++ ++ if(copy_from_user((void*)&ctl, (void __user *)arg, sizeof(ctl))) ++ { ++ BUG(); ++ } ++ ++ pr_info("ISP CLK CTL : id=%d rate=%d enable=%d\n",ctl.id,ctl.rate,ctl.enable); ++ ++ switch(ctl.id) ++ { ++ case CLK_ID_ISP: //ISP ++ _clk = data->clk_isp; ++ break; ++ case CLK_ID_SR: ++ _clk = data->clk_sr; ++ break; ++ case CLK_ID_SR_MCLK: ++ _clk = data->clk_sr_mclk; ++ break; ++ case CLK_ID_CSI_MAC: ++ _clk = data->clk_csi_mac; ++ break; ++ } ++ ++ if(!_clk) ++ return -1; ++ ++ if(ctl.rate>0) ++ clk_set_rate(_clk,ctl.rate); ++ ++ if(ctl.enable) ++ clk_prepare_enable(_clk); ++ else ++ clk_disable_unprepare(_clk); ++ } ++ break; ++ case IOCTL_ISP_IQ_RGBCCM: ++ { ++ if(copy_from_user((void*)&isp_int.rgb_ccm.ccm, (void __user *)arg, sizeof(isp_int.rgb_ccm.ccm))) ++ { ++ BUG(); ++ } ++ isp_int.rgb_ccm.dirty = 1; ++ }break; ++ case IOCTL_ISP_IQ_YUVCCM: ++ { ++ if(copy_from_user((void*)&isp_int.yuv_ccm.ccm, (void __user *)arg, sizeof(isp_int.yuv_ccm.ccm))) ++ { ++ BUG(); ++ } ++ isp_int.yuv_ccm.dirty = 1; ++ }break; ++ case IOCTL_ISP_GET_ISP_FLAG: ++ { ++ isp_ioctl_isp_flag isp_flag; ++ isp_flag.flag = g_isp_flag; ++ if(copy_to_user((void __user *)arg,(void*)&isp_flag,sizeof(isp_flag))) ++ { ++ BUG(); ++ } ++ }break; ++ case IOCTL_ISP_GET_MEM_INFO: ++ { ++ isp_ioctl_mem_info info; ++ if(copy_from_user((void*)&info, (void __user *)arg, sizeof(info))) ++ { ++ BUG(); ++ } ++ info.phy_addr = data->isp_mem->Base_Meminfo.phys; ++ switch(info.mem_id) ++ { ++ case ISP_GET_MEM_INFO_BASE: ++ info.blk_offset = 0; ++ info.blk_size = sizeof(ISP_STATIS_MEM); ++ break; ++ case ISP_GET_MEM_INFO_AE: ++ info.blk_offset = offsetof(ISP_STATIS_MEM,ae); ++ info.blk_size = member_size(ISP_STATIS_MEM,ae); ++ break; ++ case ISP_GET_MEM_INFO_AWB: ++ info.blk_offset = offsetof(ISP_STATIS_MEM,awb); ++ info.blk_size = member_size(ISP_STATIS_MEM,awb); ++ break; ++ case ISP_GET_MEM_INFO_AF: ++ info.blk_offset = offsetof(ISP_STATIS_MEM,af); ++ info.blk_size = member_size(ISP_STATIS_MEM,af); ++ break; ++ case ISP_GET_MEM_INFO_MOT: ++ info.blk_offset = offsetof(ISP_STATIS_MEM,mot); ++ info.blk_size = member_size(ISP_STATIS_MEM,mot); ++ break; ++ case ISP_GET_MEM_INFO_HISTO: ++ info.blk_offset = offsetof(ISP_STATIS_MEM,histo); ++ info.blk_size = member_size(ISP_STATIS_MEM,histo); ++ break; ++ case ISP_GET_MEM_INFO_RGBIR: ++ info.blk_offset = offsetof(ISP_STATIS_MEM,rgbir); ++ info.blk_size = member_size(ISP_STATIS_MEM,rgbir); ++ break; ++ } ++ if(copy_to_user((void __user *)arg,(void*)&info,sizeof(info))) ++ { ++ BUG(); ++ } ++ }break; ++ case IOCTL_ISP_GET_AE_IMG_INFO: ++ { ++ isp_isr_ae_img_info info; ++ ++ info.img_w= isp_int.ae_img_info.img_w; ++ info.img_h= isp_int.ae_img_info.img_h; ++ info.blk_h= isp_int.ae_img_info.blk_h; ++ info.blk_w= isp_int.ae_img_info.blk_w; ++ info.rot= isp_int.ae_img_info.rot; ++ ++ if(copy_to_user((void __user *)arg,(void*)&info,sizeof(info))) ++ { ++ BUG(); ++ } ++ }break; ++ case IOCTL_ISP_UPDATE_AE_IMG_INFO: ++ { ++ isp_isr_ae_img_info info; ++ if(copy_from_user((void*)&info, (void __user *)arg, sizeof(info))) ++ { ++ BUG(); ++ } ++ isp_int.ae_img_info.img_w = info.img_w; ++ isp_int.ae_img_info.img_h = info.img_h; ++ isp_int.ae_img_info.blk_h = info.blk_h; ++ isp_int.ae_img_info.blk_w = info.blk_w; ++ isp_int.ae_img_info.rot = info.rot; ++ ++#if 0 ++ //printk("##########isp_int.ae_img_info.img_w= %d\n",isp_int.ae_img_info.img_w); ++ //printk("##########isp_int.ae_img_info.img_h= %d\n",isp_int.ae_img_info.img_h); ++ //printk("##########isp_int.ae_img_info.blk_h= %d\n",isp_int.ae_img_info.blk_h); ++ //printk("##########isp_int.ae_img_info.blk_w= %d\n",isp_int.ae_img_info.blk_w); ++ //printk("##########isp_int.ae_img_info.rot= %d\n",isp_int.ae_img_info.rot); ++#endif ++ }break; ++ case IOCTL_ISP_SET_AE_DGAIN: ++ { ++ isp_ioctl_ae_dgian gain; ++ if(copy_from_user((void*)&gain, (void __user *)arg, sizeof(gain))) ++ { ++ BUG(); ++ } ++ isp_int.dgain.enable = gain.enable; ++ isp_int.dgain.gain = gain.dgain; ++ isp_int.dgain.dirty = 1; ++ }break; ++ case IOCTL_ISP_SET_FIFO_MASK: ++ { ++ isp_ioctl_fifo_mask mask; ++ unsigned long flags; ++ spinlock_t lock; ++ spin_lock_init(&lock); ++ ++ if(copy_from_user((void*)&mask, (void __user *)arg, sizeof(mask))) ++ { ++ BUG(); ++ } ++ ++ spin_lock_irqsave(&lock,flags); ++ if(!isp_int.fifo_mask.enable) //if enable mask ++ { ++ //IspInputEnable(0); //enable fifo mask immediately ++ isp_int.fifo_mask.dirty = 1; ++ } ++ else ++ { ++ IspInputEnable(1); //enable isp input immediately ++ isp_int.fifo_mask.dirty = 1; ++ } ++ C_OUT(isp_lock); ++ spin_unlock_irqrestore(&lock,flags); ++ }break; ++ case IOCTL_ISP_TRIGGER_WDMA: ++ { ++ isp_ioctl_trigger_wdma_attr attr; ++ ++ memset((void *)&attr,0,sizeof(attr)); ++ ++ if(copy_from_user((void*)&attr, (void __user *)arg, sizeof(attr))) ++ { ++ BUG(); ++ } ++ ++#if 0 ++ //printk("attr.width=%d\n",attr.width); ++ //printk("attr.height=%d\n",attr.height); ++ //printk("attr.x=%d\n",attr.x); ++ //printk("attr.y=%d\n",attr.y); ++ //printk("attr.wdma_path=%d\n",attr.wdma_path); ++ //printk("attr.buf_addr_phy=0x%x\n",attr.buf_addr_phy); ++ //printk("attr.buf_addr_vir=0x%x\n",attr.buf_addr_kvir); ++#endif ++ HalISPWdmaTrigger(attr); ++ ++ if(wait_event_interruptible_timeout(isp_wq_WDMA_DONE, isp_int.wdma_done == true,100)){ ++ Chip_Inv_Cache_Range(attr.buf_addr_kvir,attr.width*attr.height*2); ++ pr_debug("!!!!!!! WDMA DONE!!!!!!!!\n"); ++ }else{ ++ ++ pr_debug("!!!!!!! WDMA TIMEOUT !!!!!\n"); ++ return -1; ++ } ++ }break; ++ case IOCTL_ISP_SKIP_FRAME: ++ { ++ isp_ioctl_trigger_skip_attr attr; ++ ++ memset((void *)&attr,0,sizeof(attr)); ++ ++ if(copy_from_user((void*)&attr, (void __user *)arg, sizeof(attr))) ++ { ++ BUG(); ++ } ++ ++ Drv_SCLIRQ_SetDropFrameFromISP(attr.skip_cnt); ++ pr_debug("!!!!!skip frame:%d\n",attr.skip_cnt); ++ ++ }break; ++ case IOCTL_ISP_INIT: ++ { ++ isp_ioctl_isp_init param; ++ if(copy_from_user((void*)¶m, (void __user *)arg, sizeof(param))) ++ { ++ BUG(); ++ } ++ ++ if(param.nDnrFlag&ISP_FB_DNR)//only DNR -> 1 buffer, DNR+ROT -> 2 buffer ++ return IspInitDnrFB(param.nRawW,param.nRawH,(param.nDnrFlag&ISP_FB_ROT)?2:1); ++ }break; ++ } ++ pr_debug("ISP IOCTL -\n"); ++ return 0; ++} ++u32 isp_get_ae_img_info(isp_isr_ae_img_info *info) ++{ ++ info->img_w= isp_int.ae_img_info.img_w; ++ info->img_h= isp_int.ae_img_info.img_h; ++ info->blk_h= isp_int.ae_img_info.blk_h; ++ info->blk_w= isp_int.ae_img_info.blk_w; ++ info->rot= isp_int.ae_img_info.rot; ++ ++ return 0; ++} ++ ++//------------ Frame start signal device ---------------------- ++DEFINE_SPINLOCK(g_IspFsLock); ++static struct list_head gIspFsWqList = LIST_HEAD_INIT(gIspFsWqList); ++typedef struct ++{ ++ struct list_head list; ++ wait_queue_head_t waitq; ++ //int id; ++ unsigned int fcount; ++ int ready; ++}IspIrqLink_t; ++ ++static int isp_fs_open(struct inode *inode, struct file *fp) ++{ ++ unsigned long flags; ++ //static int open_cnt=0; ++ IspIrqLink_t *data = kmalloc(sizeof(IspIrqLink_t),GFP_KERNEL); ++ if(!data) ++ return -ENOENT; ++ memset((void*)data,0,sizeof(IspIrqLink_t)); ++ init_waitqueue_head(&data->waitq); ++ spin_lock_irqsave(&g_IspFsLock,flags); ++ list_add(&data->list,&gIspFsWqList); ++ spin_unlock_irqrestore(&g_IspFsLock,flags); ++ ++ fp->private_data = (void*) data; ++ pr_info("isp_fs open \n"); ++ return 0; ++} ++ ++static int isp_fs_release(struct inode *inode, struct file *fp) ++{ ++ unsigned long flags; ++ IspIrqLink_t *data = (IspIrqLink_t*)fp->private_data; ++ ++ spin_lock_irqsave(&g_IspFsLock,flags); ++ list_del(&data->list); ++ spin_unlock_irqrestore(&g_IspFsLock,flags); ++ ++ pr_info("isp_fs close \n"); ++ ++ kfree(data); ++ return 0; ++} ++ ++static ssize_t isp_fs_fread(struct file *fp, char __user *buf, size_t size, loff_t *ppos) ++{ ++ IspIrqLink_t *data = (IspIrqLink_t*)fp->private_data; ++ memcpy(buf, (void*)&data->fcount, size>sizeof(data->fcount)?sizeof(data->fcount):size); ++ return 0; ++} ++ ++unsigned int isp_fs_poll(struct file *fp, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ IspIrqLink_t *data = (IspIrqLink_t*)fp->private_data; ++ poll_wait(fp, &data->waitq, wait); ++ if(data->ready) ++ { ++ data->ready = 0; ++ mask |= POLLIN|POLLRDNORM; ++ } ++ return mask; ++} ++ ++struct file_operations isp_fs_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = isp_fs_open, ++ .release = isp_fs_release, ++ .read = isp_fs_fread, ++ .write = 0, ++ .unlocked_ioctl = 0, ++ .poll = isp_fs_poll, ++}; ++ ++struct miscdevice g_isp_fs_dev; ++static void AddFsNode(void) ++{ ++ g_isp_fs_dev.minor = MISC_DYNAMIC_MINOR; ++ g_isp_fs_dev.name = "isp_fs"; ++ g_isp_fs_dev.fops = &isp_fs_fops; ++ g_isp_fs_dev.parent = 0; ++ misc_register(&g_isp_fs_dev); ++} ++ ++//------------ AE signal device ---------------------- ++DEFINE_SPINLOCK(g_IspAeLock); ++static struct list_head gIspAeWqList = LIST_HEAD_INIT(gIspAeWqList); ++static int isp_ae_open(struct inode *inode, struct file *fp) ++{ ++ unsigned long flags; ++ IspIrqLink_t *data = kmalloc(sizeof(IspIrqLink_t),GFP_KERNEL); ++ if(!data) ++ return -ENOENT; ++ memset((void*)data,0,sizeof(IspIrqLink_t)); ++ //add wait queue to fs list ++ init_waitqueue_head(&data->waitq); ++ spin_lock_irqsave(&g_IspAeLock,flags); ++ list_add(&data->list,&gIspAeWqList); ++ spin_unlock_irqrestore(&g_IspAeLock,flags); ++ ++ fp->private_data = (void*) data; ++ pr_debug("isp_ae open\n"); ++ return 0; ++} ++ ++static int isp_ae_release(struct inode *inode, struct file *fp) ++{ ++ unsigned long flags; ++ IspIrqLink_t *data = (IspIrqLink_t*)fp->private_data; ++ ++ spin_lock_irqsave(&g_IspAeLock,flags); ++ list_del(&data->list); ++ spin_unlock_irqrestore(&g_IspAeLock,flags); ++ ++ pr_debug("isp_ae close\n"); ++ kfree(data); ++ return 0; ++} ++ ++static ssize_t isp_ae_fread(struct file *fp, char __user *buf, size_t size, loff_t *ppos) ++{ ++ IspIrqLink_t *data = (IspIrqLink_t*)fp->private_data; ++ memcpy(buf, (void*)&data->fcount, size>sizeof(data->fcount)?sizeof(data->fcount):size); ++ return 0; ++} ++ ++unsigned int isp_ae_poll(struct file *fp, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ IspIrqLink_t *data = (IspIrqLink_t*)fp->private_data; ++ poll_wait(fp, &data->waitq, wait); ++ if(data->ready) ++ { ++ data->ready = 0; ++ mask |= POLLIN|POLLRDNORM; ++ } ++ return mask; ++} ++ ++struct file_operations isp_ae_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = isp_ae_open, ++ .release = isp_ae_release, ++ .read = isp_ae_fread, ++ .write = 0, ++ .unlocked_ioctl = 0, ++ .poll = isp_ae_poll, ++}; ++ ++struct miscdevice g_isp_ae_dev; ++static void AddAeNode(void) ++{ ++ g_isp_ae_dev.minor = MISC_DYNAMIC_MINOR; ++ g_isp_ae_dev.name = "isp_ae"; ++ g_isp_ae_dev.fops = &isp_ae_fops; ++ g_isp_ae_dev.parent = 0; ++ misc_register(&g_isp_ae_dev); ++} ++ ++//------------------------------------------- ++ ++unsigned int isp_poll(struct file *filp, poll_table *wait) ++{ ++ unsigned int mask = 0; ++ ++ poll_wait(filp, &isp_wq_epoll_event, wait); ++ ++ if(isp_int.epoll_event == true) ++ { ++ isp_int.epoll_event = false; ++ mask |= POLLIN; ++ } ++ return mask; ++} ++ ++struct file_operations isp_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = isp_open, ++ .release = isp_release, ++ .read = isp_fread, ++ .write = isp_fwrite, ++ .unlocked_ioctl = isp_ioctl, ++ .poll = isp_poll, ++}; ++ ++#define MAJOR_ISP_NUM 234 ++#define MINOR_ISP_NUM 128 ++#define MINOR_CSI_NUM 127 ++static int isp_probe(struct platform_device* pdev) ++{ ++ int err, ret; ++ int irq; ++ unsigned int i, u4IO_PHY_BASE; ++ unsigned int u4Banks[10]; ++ isp_dev_data *data; ++ ++ pr_debug("[ISP] = isp_probe\n"); ++ ++ memset(&isp_int,0,sizeof(isp_int)); ++ isp_int.int_cnt = 0; ++ ++ data = kzalloc(sizeof(isp_dev_data),GFP_KERNEL); ++ if(NULL == data) ++ return -ENOENT; ++ ret = of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); ++ if(ret != 0) ++ pr_err("[ISP] read node error!\n"); ++ ret = of_property_read_u32_array(pdev->dev.of_node, "banks", (unsigned int*)u4Banks, 10); ++ if(ret != 0) ++ pr_err("[ISP] read node error!\n"); ++ for (i = 0; i < 10; i++) { ++ isp_mem.pISPRegs[i] = (void*)ioremap(BANK_TO_ADDR32(u4Banks[i])+u4IO_PHY_BASE, BANK_SIZE); ++ } ++ ret = of_property_read_u32(pdev->dev.of_node, "isp-flag", &g_isp_flag); ++ if(ret != 0) ++ pr_err("[ISP] read node error!\n"); ++ ret = of_property_read_u32(pdev->dev.of_node, "isp-res", &g_isp_max_res); ++ if(ret != 0) ++ pr_err("[ISP] read node error!\n"); ++ ++ //enable clocks ++ //ISP ++ data->clk_isp = of_clk_get(pdev->dev.of_node, 0); ++ clk_set_rate(data->clk_isp,123000000); ++ clk_prepare_enable(data->clk_isp); ++ ++ data->clk_sr_mclk = of_clk_get(pdev->dev.of_node, 1); ++ clk_set_rate(data->clk_sr_mclk,12000000); ++ clk_prepare_enable(data->clk_sr_mclk); ++ ++ data->clk_sr = of_clk_get(pdev->dev.of_node, 2); ++ clk_set_rate(data->clk_sr,86000000); ++ clk_prepare_enable(data->clk_sr); ++ ++ data->clk_csi_mac = of_clk_get(pdev->dev.of_node, 3); ++ ++ data->isp_int = &isp_int; ++ data->isp_mem = &isp_mem; ++ fps_init(&data->isp_int->fps); //initial frame interval count ++ ++ // init register and disable interrupt ++ HalInitRegs((void**)isp_mem.pISPRegs); ++ HalISPDisableInt(); ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ pr_debug("[ISP] Request IRQ: %d\n", irq); ++ if (request_irq(irq, isp_ISR, 0, "isp interrupt", (void*)&isp_int) == 0) ++ pr_debug("[ISP] isp interrupt registered\n"); ++ else ++ pr_err("[ISP] isp interrupt failed"); ++ ++ SETREG8((u4IO_PHY_BASE+(0x112B00*2)+(0x16*4)),0x01); //set GPIO28 to GPIO function ++ CLRREG16((u4IO_PHY_BASE+(0x101A00*2)+(0x12*4)),(0x0001<<12)); //set GPIO28 pad mux to GPIO ++ CLRREG16((u4IO_PHY_BASE+(0x102B00*2)+(0x12*4)),(0x0001<<9)); //GPIO28 OEN ++ SETREG16((u4IO_PHY_BASE+(0x102B00*2)+(0x12*4)),(0x0001<<8)); //GPIO28 pull ligh ++ isp_device = pdev; ++ ++ //allocate statistics data and menload table memory ++ isp_init_buff(); ++ ++ // enable interrupt ++ HalISPEnableInt(); ++ isp_int.sysfs_int = true; // turn on IRQ handler ++ isp_int.yuv_ccm.dirty = 0; ++ ++ isp_int.dgain.dirty = 0; ++ isp_int.dgain.enable = 0; ++ isp_int.dgain.gain = 1024; ++ ++ // setup kernel i2c ++ data->isp_dev.minor = MISC_DYNAMIC_MINOR; ++ data->isp_dev.name = "isp"; ++ data->isp_dev.fops = &isp_fops; ++ data->isp_dev.parent = &pdev->dev; ++ misc_register(&data->isp_dev); ++ ++ AddFsNode(); ++ AddAeNode(); ++ ++ data->sysfs_dev = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR_ISP_NUM, MINOR_ISP_NUM), NULL, "isp0"); ++ isp_create_bin_file(data->sysfs_dev); ++ err = sysfs_create_link(&pdev->dev.parent->kobj,&data->sysfs_dev->kobj, "isp0"); //create symlink for older firmware version ++ ++ data->sysfs_dev->platform_data = pdev->dev.platform_data = (void*)data; ++ ++ return 0; ++} ++ ++static int isp_remove(struct platform_device* pdev) ++{ ++ isp_dev_data *data = dev_get_platdata(&pdev->dev); ++ clk_disable_unprepare(data->clk_isp); ++ clk_put(data->clk_isp); ++ clk_disable_unprepare(data->clk_sr); ++ clk_put(data->clk_sr); ++ clk_disable_unprepare(data->clk_sr_mclk); ++ clk_put(data->clk_sr_mclk); ++ ++ misc_deregister(&data->isp_dev); ++ device_destroy(msys_get_sysfs_class(),MKDEV(MAJOR_ISP_NUM, MINOR_ISP_NUM)); ++ kfree(data); ++ return 0; ++} ++ ++static int isp_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ if (!pdev) ++ { ++ return -EINVAL; ++ //pr_info("isp_suspend with NULL pdev %d", isp_int.frame_cnt); ++ } ++ else ++ { ++ isp_dev_data *data = dev_get_platdata(&pdev->dev); ++ pr_info("[ISP] = isp_suspend\n"); ++ isp_int.sysfs_int = false; ++ ++ if(data->clk_isp) ++ clk_disable_unprepare(data->clk_isp); ++ if(data->clk_sr) ++ clk_disable_unprepare(data->clk_sr); ++ if(data->clk_sr_mclk) ++ clk_disable_unprepare(data->clk_sr_mclk); ++ } ++ return 0; ++} ++ ++static int isp_resume(struct platform_device *pdev) ++{ ++ isp_dev_data *data; ++ ++ if(!pdev) ++ return -EINVAL; ++ ++ data = dev_get_platdata(&pdev->dev); ++ HalISPDisableInt(); ++ ++ isp_int.sysfs_int = false; ++ pr_info("[ISP] = isp_resume\n"); ++ ++ HalInitRegs((void**)data->isp_mem->pISPRegs); ++ isp_restore_buff(); //recover isp registers which contain buffer address , ++ ++ if(data->clk_isp) clk_prepare_enable(data->clk_isp); ++ if(data->clk_sr) clk_prepare_enable(data->clk_sr); ++ if(data->clk_sr_mclk) clk_prepare_enable(data->clk_sr_mclk); ++ ++ HalISPEnableInt(); // enable interrupt ++ return 0; ++} ++ ++void isp_apply_iq_at_vend(void) ++{ ++ if(isp_int.yuv_ccm.dirty) ++ { ++ HalISPSetYUVCCM(isp_int.yuv_ccm.ccm); ++ isp_int.yuv_ccm.dirty = 0; ++ print_timestamp("K_CCM2"); ++ } ++ ++ if(isp_int.dgain.dirty) ++ { ++ HalIspSetAEDgain(isp_int.dgain.enable,isp_int.dgain.gain); ++ } ++ ++#if 0 ++ if (isp_int.share_data->frame_state.u4OBCInValid == true){ ++ HalISPSetOBC(isp_int.share_data->frame_state.u4OBC_a, isp_int.share_data->frame_state.u4OBC_b); ++ isp_int.share_data->frame_state.u4OBCInValid = false; ++ print_timestamp("K_OBC"); ++ } ++#endif ++} ++ ++#define INC_TIME_REC(name) getnstimeofday(&isp_int.isp_int_time[name]) ++#define INC_TIME_REC2(name) getnstimeofday(&isp_int.isp_int_time2[name]) ++#define INC_TIME_REC3(name) getnstimeofday(&isp_int.isp_int_time3[name])) ++ ++#define INC_COUNT(name) {isp_int.isp_int_count[name]++;\ ++ getnstimeofday(&isp_int.isp_int_time[name]);} ++#define INC_COUNT2(name) {isp_int.isp_int2_count[name]++;\ ++ getnstimeofday(&isp_int.isp_int2_time[name]);} ++#define INC_COUNT3(name) {isp_int.isp_int3_count[name]++;\ ++ getnstimeofday(&isp_int.isp_int3_time[name]);} ++ ++irqreturn_t isp_ISR(int num, void *priv) ++{ ++ volatile u32 u4Clear = 0; ++ volatile u32 u4Clear2 = 0; ++ volatile u32 u4Clear3 = 0; ++ ++ volatile u32 u4Status; ++ volatile u32 u4Status2; ++ volatile u32 u4Status3; ++ ++ //volatile u32 u4VsyncPol; ++ //volatile u32 u4MIPI; ++ ++ isp_int.int_cnt++; ++ ++ u4Status = HalISPGetIntStatus1(); ++ //HalISPMaskInt1(u4Status); ++ u4Status2 = HalISPGetIntStatus2(); ++ //HalISPMaskInt2(u4Status2); ++ u4Status3 = HalISPGetIntStatus3(); ++ //HalISPMaskInt3(u4Status3); ++ ++ //u4VsyncPol = HalISPGetVsyncPol(); ++ ++ //u4MIPI = HalISPGetMIPI(); ++ ++ if (u4Status == 0 && u4Status2 == 0 && u4Status3 == 0) { ++ pr_err("[ISP] False interrupt? mask1 0x%04x, mask2 0x%04x, mask3 0x%04x\n", u4Status, u4Status2, u4Status3); ++ return IRQ_HANDLED; ++ } ++ ++#if 0 ++ pr_info("c=%d sta=0x%x\n", isp_int.frame_cnt, u4Status); ++#endif ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_SW_INT_INPUT_DONE)) { ++ DBG_INFO_1("INT3_SW_INT_INPUT_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_SW_INT_INPUT_DONE); ++ INC_COUNT3(INT3_SW_INT_INPUT_DONE); ++ //if(isp_int.fifo_mask.dirty) ++ //{ ++ // IspInputEnable(~isp_int.fifo_mask.enable); ++ // isp_int.fifo_mask.dirty = 0; ++ // if(!isp_int.fifo_mask.enable) pr_debug("ISP OFF\n"); ++ //} ++ isp_int.vsync_end = true; ++ isp_int.share_data->frame_state.bActive = false; ++ //isp_apply_iq_at_vend(); ++ isp_mot_cache_invalidate(); ++ wake_up_interruptible_all(&isp_wq_VEND); ++ wake_up_interruptible_all(&isp_wq_sw_int_in); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= FRAME_END_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } ++ ++ //////////////////////////////////////////// ++ // Vsync Start // ++ //////////////////////////////////////////// ++ //all sensor use ISP vsync as Frame start ++ if (ISP_CHECKBITS(u4Status, INT_ISPIF_VSYNC)){ ++ HalISPClearInt(&u4Clear, INT_ISPIF_VSYNC); ++ INC_COUNT(INT_ISPIF_VSYNC); ++ isp_int.vsync_start = true; ++ isp_int.frame_cnt++; ++ isp_int.share_data->frame_state.u4FrameCnt = isp_int.frame_cnt; ++ isp_int.share_data->frame_state.bActive = true; ++ isp_int.hw_frame_cnt = (HalISPGetFrameDoneCount()+ 1) & 0x7F; //get frame done count in VSync and return it at frame end interrupt ++ fps_update(&isp_int.fps); ++ wake_up_interruptible_all(&isp_wq_VSTART); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= FRAME_START_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ DBG_INFO_1("MIPI VSYNC ACTIVE %d", isp_int.frame_cnt); ++ pr_debug("VS\n"); ++ ++ //TEST CODE ++ print_timestamp("K_VS");//TEST CODE ++ ++ //isp_fs poll support ++ { ++ unsigned long flag; ++ struct list_head *pos; ++ IspIrqLink_t *elm; ++ spin_lock_irqsave(&g_IspFsLock,flag); ++ list_for_each(pos,&gIspFsWqList) ++ { ++ elm = list_entry(pos,IspIrqLink_t,list); ++ elm->ready = 1; ++ elm->fcount = isp_int.frame_cnt; ++ wake_up_interruptible_all(&elm->waitq); ++ } ++ spin_unlock_irqrestore(&g_IspFsLock,flag); ++ } ++ } ++ ++ ////////////////////////////////////////////// ++ // statistics // ++ ////////////////////////////////////////////// ++ if (ISP_CHECKBITS(u4Status, INT_AE_DONE)){ ++ pr_debug("AE\n"); ++ isp_ae_cache_invalidate(); ++ DBG_INFO_1("INT_AE_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear, INT_AE_DONE); ++ INC_COUNT(INT_AE_DONE); ++ isp_int.ae = true; ++ wake_up_interruptible_all(&isp_wq_ae); ++ } ++ ++ // AE WIN0/1 Int Row ++ if (ISP_CHECKBITS(u4Status3, INT3_AE_WIN0_DONE)) { ++ pr_debug("AE_WIN0\n"); ++ DBG_INFO_1("INT3_AE_WIN0_DONE %d\n", isp_int.frame_cnt); ++ isp_int.ae_win0 = true; ++ HalISPClearInt(&u4Clear3, INT3_AE_WIN0_DONE); ++ wake_up_interruptible_all(&isp_wq_ae_win0); ++ ++ //isp_ae poll support ++ { ++ unsigned long flag; ++ struct list_head *pos; ++ IspIrqLink_t *elm; ++ spin_lock_irqsave(&g_IspAeLock,flag); ++ list_for_each(pos,&gIspAeWqList) ++ { ++ elm = list_entry(pos,IspIrqLink_t,list); ++ elm->ready = 1; ++ elm->fcount = isp_int.frame_cnt; ++ wake_up_interruptible_all(&elm->waitq); ++ } ++ spin_unlock_irqrestore(&g_IspAeLock,flag); ++ } ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_AE_BLK_ROW_INT_DONE)) { ++ pr_debug("AE_ROW\n"); ++ DBG_INFO_1("INT3_AE_BLK_ROW_INT_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_AE_BLK_ROW_INT_DONE); ++ INC_COUNT3(INT3_AE_BLK_ROW_INT_DONE); ++ isp_int.ae_row_int= true; ++ wake_up_interruptible_all(&isp_wq_ae_row_int); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= AE_DONE_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_AWB_DONE)) { ++ isp_awb_cache_invalidate(); //invalid cache data ++ DBG_INFO_1("INT_AWB_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear, INT_AWB_DONE); ++ INC_COUNT(INT_AWB_DONE); ++ isp_int.awb = true; ++ wake_up_interruptible_all(&isp_wq_awb); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= AWB_DONE_EVENT ; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_AF_DONE)) { ++ isp_af_cache_invalidate(); ++ DBG_INFO_1("INT_AF_DONE %d", isp_int.frame_cnt); ++ HalISPGetAFStat(isp_int.AF_Stat); ++ HalISPClearInt(&u4Clear, INT_AF_DONE); ++ INC_COUNT(INT_AF_DONE); ++ isp_int.af = true; ++ wake_up_interruptible_all(&isp_wq_af); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= AF_DONE_EVENT ; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_HIT_LINE_COUNT1)) { ++ DBG_INFO_1("INT3_HIT_LINE_COUNT1 %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_HIT_LINE_COUNT1); ++ INC_COUNT3(INT3_HIT_LINE_COUNT1); ++ wake_up_interruptible_all(&isp_wq_hit_line_count1); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_HIT_LINE_COUNT2)) { ++ DBG_INFO_1("INT3_HIT_LINE_COUNT2 %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_HIT_LINE_COUNT2); ++ INC_COUNT3(INT3_HIT_LINE_COUNT2); ++ wake_up_interruptible_all(&isp_wq_hit_line_count2); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_HIT_LINE_COUNT3)) { ++ DBG_INFO_1("INT3_HIT_LINE_COUNT3 %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_HIT_LINE_COUNT3); ++ INC_COUNT3(INT3_HIT_LINE_COUNT3); ++ //wake_up_interruptible_all(&isp_wq_hit_line_count3); ++ isp_int.isp_idle = true; ++ wake_up_interruptible_all(&isp_wq_ISP_IDLE); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= IDLE_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_HDR_HISTO_DONE)) { ++ DBG_INFO_1("INT3_HDR_HISTO_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_HDR_HISTO_DONE); ++ INC_COUNT3(INT3_HDR_HISTO_DONE); ++ isp_histo_cache_invalidate(); ++ wake_up_interruptible_all(&isp_wq_hdr_histo_done); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_RGBIR_HISTO_DONE)) { ++ DBG_INFO_1("INT3_RGBIR_HISTO_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_RGBIR_HISTO_DONE); ++ INC_COUNT3(INT3_RGBIR_HISTO_DONE); ++ isp_histo_cache_invalidate(); ++ wake_up_interruptible_all(&isp_wq_rgbir_histo_done); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_AWB_ROW_DONE)) { ++ DBG_INFO_1("INT3_AWB_ROW_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_AWB_ROW_DONE); ++ INC_COUNT3(INT3_AWB_ROW_DONE); ++ wake_up_interruptible_all(&isp_wq_awb_row_done); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_HISTO_ROW_DONE)) { ++ DBG_INFO_1("INT3_HISTO_ROW_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_HISTO_ROW_DONE); ++ INC_COUNT3(INT3_HISTO_ROW_DONE); ++ wake_up_interruptible_all(&isp_wq_histo_row_done); ++ } ++ ++ if (ISP_CHECKBITS(u4Status3, INT3_SW_INT_OUTPUT_DONE)) { ++ DBG_INFO_1("INT3_SW_INT_OUTPUT_DONE %d", isp_int.frame_cnt); ++ HalISPClearInt(&u4Clear3, INT3_SW_INT_OUTPUT_DONE); ++ INC_COUNT3(INT3_SW_INT_OUTPUT_DONE); ++ ++ if(isp_int.fifo_mask.dirty) ++ { ++ IspInputEnable(~isp_int.fifo_mask.enable); ++ isp_int.fifo_mask.dirty = 0; ++ if(!isp_int.fifo_mask.enable) pr_debug("ISP OFF\n"); ++ } ++ isp_apply_iq_at_vend(); ++ wake_up_interruptible_all(&isp_wq_sw_int_out); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_ISP_BUSY)) { ++ HalISPClearInt(&u4Clear, INT_ISP_BUSY); ++ INC_COUNT(INT_ISP_BUSY); ++ DBG_INFO_1("INT_ISP_BUSY %d", isp_int.frame_cnt); ++ isp_int.isp_busy = true; ++ wake_up_interruptible_all(&isp_wq_ISP_BUSY); ++ print_timestamp("K_BUSY");//TEST CODE ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_ISP_IDLE)) { ++ HalISPClearInt(&u4Clear, INT_ISP_IDLE); ++ INC_COUNT(INT_ISP_IDLE); ++ DBG_INFO_1("INT_ISP_IDLE %d", isp_int.frame_cnt); ++ //isp_int.isp_idle = true; ++ //wake_up_interruptible_all(&isp_wq_ISP_IDLE); ++ print_timestamp("K_IDLE");//TEST CODE ++ } ++ ++ ////////////////////////////// ++ // Vsync end // ++ ////////////////////////////// ++ ++#if 0 ++ if(ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_RISING)) ++ { ++ INC_COUNT(INT_PAD_VSYNC_RISING); ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_RISING); ++ } ++ ++ if(ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_FALLING)) ++ { ++ INC_COUNT(INT_PAD_VSYNC_FALLING); ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_FALLING); ++ } ++ ++ if (!u4MIPI){ ++ if ((ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_RISING) && u4VsyncPol == false) || (ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_FALLING) && u4VsyncPol == true)){ ++ if (isp_int.vsync_end == false){ ++ if (ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_RISING) && u4VsyncPol == false ){ ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_RISING); ++ //INC_COUNT(INT_PAD_VSYNC_RISING); ++ //if(isp_int.fifo_mask.dirty) ++ //{ ++ // IspInputEnable(~isp_int.fifo_mask.enable); ++ // isp_int.fifo_mask.dirty = 0; ++ //} ++ if (isp_int.frame_cnt%30==0) ++ DBG_INFO_1("Parallel Vsync End INT_PAD_VSYNC_RISING %d", isp_int.frame_cnt); ++ } ++ else if (ISP_CHECKBITS(u4Status, INT_PAD_VSYNC_FALLING) && u4VsyncPol == true){ ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_FALLING); ++ //INC_COUNT(INT_PAD_VSYNC_FALLING); ++ //if(isp_int.fifo_mask.dirty) ++ //{ ++ // IspInputEnable(~isp_int.fifo_mask.enable); ++ // isp_int.fifo_mask.dirty = 0; ++ //} ++ if (isp_int.frame_cnt%30==0) ++ DBG_INFO_1("Parallel Vsync End INT_PAD_VSYNC_FALLING %d", isp_int.frame_cnt); ++ } ++ ++ DBG_INFO_1(KERN_NOTICE "Parallel VSYNC End...%d %d\n", isp_int.share_data->frame_state.bActive, isp_int.share_data->frame_state.u4FrameCnt); ++ isp_int.vsync_end = true; ++ isp_int.share_data->frame_state.bActive = false; ++ isp_apply_iq_at_vend(); ++ isp_mot_cache_invalidate(); ++ wake_up_interruptible_all(&isp_wq_VEND); ++ // Using menuload to write IQ table to SRAMs ++ pr_debug("VE\n"); ++ //isp_write_iq_tbl(); ++ }else{ ++ //DBG_INFO("Parallel Vsync End ---FALSE---"); ++ } ++ } ++ } ++#endif ++ //////////////////////////////////////////// ++ // DMA // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(u4Status, INT_WDMA_DONE) && isp_int.wdma_done == false) { ++ HalISPClearInt(&u4Clear, INT_WDMA_DONE); ++ INC_COUNT(INT_WDMA_DONE); ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_RISING); ++ HalISPClearInt(&u4Clear, INT_PAD_VSYNC_FALLING); ++ DBG_INFO_1("INT_WDMA_DONE %d", isp_int.frame_cnt); ++ isp_int.wdma_done = true; ++ wake_up_interruptible_all(&isp_wq_WDMA_DONE); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= WDMA_DONE_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } else { ++ //DBG_INFO("INT_WDMA_DONE %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_RDMA_DONE) && isp_int.rdma_done == false) { ++ HalISPClearInt(&u4Clear, INT_RDMA_DONE); ++ INC_COUNT(INT_RDMA_DONE); ++ DBG_INFO_1("INT_RDMA_DONE %d", isp_int.frame_cnt); ++ isp_int.rdma_done = true; ++ wake_up_interruptible_all(&isp_wq_RDMA_DONE); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= RDMA_DONE_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } else { ++ //DBG_INFO("INT_RDMA_DONE %d, --FALSE--", isp_int.frame_cnt); ++ } ++ ++ //////////////////////////////////////////// ++ // FIFO Full // ++ //////////////////////////////////////////// ++ if (ISP_CHECKBITS(u4Status, INT_ISP_FIFO_FULL)) ++ { ++ HalISPClearInt(&u4Clear, INT_ISP_FIFO_FULL); ++ INC_COUNT(INT_ISP_FIFO_FULL); ++ //DBG_INFO_1("INT_ISP_FIFO_FULL %d", isp_int.frame_cnt); ++ pr_debug("isp fifo full %d", isp_int.frame_cnt); ++ isp_int.isp_fifofull = true; ++ IspReset(); //force ISP reset , when ISP FIFO FULL happen ++ wake_up_interruptible_all(&isp_wq_ISP_FIFO_FULL); ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= FIFO_FULL_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++ } ++ ++ if (ISP_CHECKBITS(u4Status, INT_WDMA_FIFO_FULL) && isp_int.wdma_fifofull == false){ ++ HalISPClearInt(&u4Clear, INT_WDMA_FIFO_FULL); ++ INC_COUNT(INT_WDMA_FIFO_FULL); ++ DBG_INFO_1("INT_WDMA_FIFO_FULL %d", isp_int.frame_cnt); ++ isp_int.wdma_fifofull = true; ++ wake_up_interruptible_all(&isp_wq_WDMA_FIFO_FULL); ++ } ++ ++ if (ISP_CHECKBITS(u4Status2, INT2_VDOS_LINE2)) { ++ HalISPClearInt(&u4Clear2, INT2_VDOS_LINE2); ++ INC_COUNT2(INT2_VDOS_LINE2); ++ DBG_INFO_1("INT2_VDOS_LINE2 %d", isp_int.frame_cnt); ++ isp_int.eis = true; ++ wake_up_interruptible_all(&isp_wq_eis); ++ } ++ ++ HalISPMaskClear1(u4Clear); ++ HalISPMaskClear2(u4Clear2); ++ HalISPMaskClear3(u4Clear3); ++ if (isp_int.frame_cnt%1200==0){ ++ pr_debug("end of ISR, u4Status:0x%04x/0x%04x/0x%04x, u4Clear:0x%04x/0x%04x/0x%04x", u4Status, u4Status2, u4Status3, u4Clear, u4Clear2, u4Clear3); ++ } ++ return IRQ_HANDLED; ++} ++ ++static int isp_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ typedef struct { ++ unsigned long u4BaseAddr; ++ u32 u4Size; ++ } FRAMEINFO_MEM; ++ ++ FRAMEINFO_MEM frameinfo; ++ frameinfo.u4BaseAddr = isp_mem.ShareData_Meminfo.phys; ++ frameinfo.u4Size = sizeof(ISP_SHARE_DATA); ++ data_size = sizeof(FRAMEINFO_MEM); ++ if (buf && size >= data_size) { ++ DBG_INFO("buff in %d, out %d\n", size, data_size); ++ memcpy((void *)buf, (void *)&frameinfo, data_size); ++ } ++ return data_size; ++} ++ ++static int isp_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if (buf && size >= 1) { ++ reset_isp_int(&isp_int); ++ isp_int.sysfs_int = (buf[0] & 0x01); ++ } else { ++ //memset((void*)&isp_int, 0, sizeof(ISP_INT_DATA)); ++ reset_isp_int(&isp_int); ++ isp_int.sysfs_int = false; ++ } ++ ++ if (isp_int.sysfs_int == true) ++ HalISPEnableInt(); ++ else ++ HalISPDisableInt(); ++ ++#if defined(FPGA_VERIFY) ++ fpgaInit(); ++#endif ++ ++ return size; ++} ++ ++static int vs_sr_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_VSTART, isp_int.vsync_start == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.vsync_start = false; ++ C_OUT(isp_lock); ++ return -ERESTARTSYS; ++ } ++ C_IN(isp_lock); ++ isp_int.vsync_start = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++ ++static int vs_sr_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++//typedef struct ++//{ ++// u32 frame_cnt; ++// u32 hw_frame_cnt; ++//}__attribute__((packed, aligned(1))) ve_isr_data; //vsync end isr data ++ ++static int ve_sr_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ ve_isr_data ve_data; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_VEND, isp_int.vsync_end == true)){ ++ C_IN(isp_lock); ++ isp_int.vsync_end = false; ++ C_OUT(isp_lock); ++ return -ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.vsync_end = false; ++ ve_data.frame_cnt = isp_int.frame_cnt; ++ ve_data.hw_frame_cnt = isp_int.hw_frame_cnt; ++ C_OUT(isp_lock); ++ ++ if (buf){ ++ size = size>sizeof(ve_data)?sizeof(ve_data):size; ++ memcpy((void*)buf,(void*)&ve_data,size); ++ } ++ return size; ++} ++ ++static int ve_sr_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae, isp_int.ae == true)){ ++ C_IN(isp_lock); ++ isp_int.ae = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae = false; ++ C_OUT(isp_lock); ++ ++ // TODO ++ //DBG_INFO_2("ae virtual offset[%d]: 0x%08x", isp_mem.AE_ReadIdx, (u32)isp_mem.AE_Offset[isp_mem.AE_ReadIdx]); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++static int ae_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_win0_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae_win0, isp_int.ae_win0 == true)){ ++ C_IN(isp_lock); ++ isp_int.ae_win0 = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae_win0 = false; ++ C_OUT(isp_lock); ++ ++ //DBG_INFO_2("ae virtual offset[%d]: 0x%08x", isp_mem.AE_ReadIdx, (u32)isp_mem.AE_Offset[isp_mem.AE_ReadIdx]); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++ ++static int ae_win0_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_win1_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int ae_win1_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int ae_row_int_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ae_row_int, isp_int.ae_row_int== true)){ ++ C_IN(isp_lock); ++ isp_int.ae_row_int = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.ae_row_int = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++ ++static int ae_row_int_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int sw_int_in_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int sw_int_in_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int sw_int_out_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int sw_int_out_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int awb_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_awb, isp_int.awb == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.awb = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.awb = false; ++ C_OUT(isp_lock); ++ ++ //DBG_INFO_2("awb virtual offset[%d]: 0x%08x", isp_mem.AWB_ReadIdx, (u32)isp_mem.AWB_Offset[isp_mem.AWB_ReadIdx]); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++ ++static int awb_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int af_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_af, isp_int.af == true)){ ++ C_IN(isp_lock); ++ isp_int.af = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.af = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++static int af_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++static int busy_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ //int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_BUSY, isp_int.isp_busy == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_busy = false; ++ C_OUT(isp_lock); ++ ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_busy = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return size; ++} ++ ++static int busy_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int idle_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_IDLE, isp_int.isp_idle == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_idle = false; ++ C_OUT(isp_lock); ++ ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_idle = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return data_size; ++} ++static int idle_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++/// isp fifo full ++static int isp_fifofull_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_ISP_FIFO_FULL, isp_int.isp_fifofull == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.isp_fifofull = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.isp_fifofull = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ ++ return data_size; ++} ++static int isp_fifofull_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ DBG_INFO(); ++ return size; ++} ++ ++// wdma fifo full ++static int wdma_fifofull_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) { ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_WDMA_FIFO_FULL, isp_int.wdma_fifofull == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.wdma_fifofull = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.wdma_fifofull = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return data_size; ++} ++ ++static int wdma_fifofull_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// wdma done ++static int wdma_done_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_WDMA_DONE, isp_int.wdma_done == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.wdma_done = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.wdma_done = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return data_size; ++} ++ ++static int wdma_done_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// rdma done ++static int rdma_done_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = 0; ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_RDMA_DONE, isp_int.rdma_done == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.rdma_done = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ C_IN(isp_lock); ++ isp_int.rdma_done = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return data_size; ++} ++ ++static int rdma_done_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// eis vdos ++static int eis_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ // FIXJASON ++ unsigned long flags; ++ ++ if (wait_event_interruptible(isp_wq_eis, isp_int.eis == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.eis = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.eis = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return 0; ++} ++static int eis_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ // FIXJASON ++ DBG_INFO(); ++ return size; ++} ++ ++// SCL vsync end ++static int scl_fe_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ if (wait_event_interruptible(isp_wq_scl_fe, isp_int.scl_fe == true)) ++ { ++ C_IN(isp_lock); ++ isp_int.scl_fe = false; ++ C_OUT(isp_lock); ++ return - ERESTARTSYS; ++ } ++ ++ C_IN(isp_lock); ++ isp_int.scl_fe = false; ++ C_OUT(isp_lock); ++ ++ if(buf) ++ { ++ isp_isr_event_data data; ++ data.fcount = isp_int.frame_cnt; ++ size = size>sizeof(data)?sizeof(data):size; ++ memcpy((void*)buf,(void*)&data,size); ++ } ++ else ++ { ++ size= 0; ++ } ++ ++ return 0; ++} ++ ++static int scl_fe_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++void DrvISPMLoadWriteData(volatile unsigned int Sram_Id, volatile unsigned long Addr, size_t size) ++{ ++ return HalISPMLoadWriteData(Sram_Id, Addr, size); ++} ++ ++void DrvISPMLoadReadData(ISP_MLOAD_ID Sram_Id, volatile unsigned short *table, size_t size) ++{ ++ // only for gamma10to10 read ++ switch (Sram_Id){ ++ case eMLOAD_ID_LN_GMA10TO10_R: ++ case eMLOAD_ID_LN_GMA10TO10_G: ++ case eMLOAD_ID_LN_GMA10TO10_B: ++ wait_event_interruptible(isp_wq_ISP_IDLE, isp_int.isp_idle == true); ++ // wait 8 line buffer time 8 * 30 us ++ udelay(300); ++ break; ++ default: ++ break; ++ } ++ return HalISPMLoadReadData(Sram_Id, table, size); ++} ++ ++static int mload_ALSC_R_TBL_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = ALSC_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_ALSC_R_TBL, (unsigned short*)buf, ALSC_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_ALSC_R_TBL_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ //pr_info("[%s] called, offset = %#llx , size = %#x", __func__, offset, size); ++ if(offset == 0) ++ { ++ //pr_info("memset mload_virt_addr\n"); ++ memset(mload_virt_addr,0, ALSC_TBL_SIZE*2); ++ } ++ memcpy(mload_virt_addr+offset, buf, size); ++ ++ if(offset+size == ((ALSC_TBL_SIZE-1)*2)) ++ { ++ //pr_info("[DrvISPMLoadWriteData] called, offset = %llx , size = %#x", offset, size); ++ DrvISPMLoadWriteData(eMLOAD_ID_ALSC_R_TBL, mload_dma_addr, ALSC_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_ALSC_G_TBL_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = ALSC_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_ALSC_G_TBL, (unsigned short*)buf, ALSC_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_ALSC_G_TBL_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ //pr_info("[%s] called, offset = %#llx , size = %#x", __func__, offset, size); ++ if(offset == 0) ++ { ++ //pr_info("memset mload_virt_addr\n"); ++ memset(mload_virt_addr,0, ALSC_TBL_SIZE*2); ++ } ++ memcpy(mload_virt_addr+offset, buf, size); ++ ++ if(offset+size == ((ALSC_TBL_SIZE-1)*2)) ++ { ++ //pr_info("[DrvISPMLoadWriteData] called, offset = %llx , size = %#x", offset, size); ++ DrvISPMLoadWriteData(eMLOAD_ID_ALSC_G_TBL, mload_dma_addr, ALSC_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_ALSC_B_TBL_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = ALSC_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_ALSC_B_TBL, (unsigned short*)buf, ALSC_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_ALSC_B_TBL_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ //pr_info("[%s] called, offset = %#llx , size = %#x", __func__, offset, size); ++ if(offset == 0) ++ { ++ //pr_info("memset mload_virt_addr\n"); ++ memset(mload_virt_addr,0, ALSC_TBL_SIZE*2); ++ } ++ memcpy(mload_virt_addr+offset, buf, size); ++ ++ if(offset+size == ((ALSC_TBL_SIZE-1)*2)) ++ { ++ //pr_info("[DrvISPMLoadWriteData] called, offset = %llx , size = %#x", offset, size); ++ DrvISPMLoadWriteData(eMLOAD_ID_ALSC_B_TBL, mload_dma_addr, ALSC_TBL_SIZE); ++ } ++ return size; ++} ++ ++ ++static int mload_LN_GMA12TO10_R_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = GAMMA_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_LN_GMA12TO10_R, (unsigned short*)buf, GAMMA_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_LN_GMA12TO10_R_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, GAMMA_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, GAMMA_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_LN_GMA12TO10_R, mload_dma_addr, GAMMA_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_LN_GMA12TO10_G_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = GAMMA_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_LN_GMA12TO10_G, (unsigned short*)buf, GAMMA_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_LN_GMA12TO10_G_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, GAMMA_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, GAMMA_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_LN_GMA12TO10_G, mload_dma_addr, GAMMA_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_LN_GMA12TO10_B_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = GAMMA_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_LN_GMA12TO10_B, (unsigned short*)buf, GAMMA_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_LN_GMA12TO10_B_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, GAMMA_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, GAMMA_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_LN_GMA12TO10_B, mload_dma_addr, GAMMA_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_DP_TBL_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = DEFECTPIX_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_DP_TBL, (unsigned short*)buf, DEFECTPIX_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_DP_TBL_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, DEFECTPIX_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, DEFECTPIX_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_DP_TBL, mload_dma_addr, DEFECTPIX_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_LN_GMA10TO10_R_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = GAMMA_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_LN_GMA10TO10_R, (unsigned short*)buf, GAMMA_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_LN_GMA10TO10_R_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, GAMMA_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, GAMMA_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_LN_GMA10TO10_R, mload_dma_addr, GAMMA_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_LN_GMA10TO10_G_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = GAMMA_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_LN_GMA10TO10_G, (unsigned short*)buf, GAMMA_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_LN_GMA10TO10_G_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, GAMMA_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, GAMMA_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_LN_GMA10TO10_G, mload_dma_addr, GAMMA_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_LN_GMA10TO10_B_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = GAMMA_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_LN_GMA10TO10_B, (unsigned short*)buf, GAMMA_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_LN_GMA10TO10_B_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0, GAMMA_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, GAMMA_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_LN_GMA10TO10_B, mload_dma_addr, GAMMA_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_FPN_OFFSET_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ int data_size = FPN_OFFSET_TBL_SIZE*2; ++ memset(buf, 0, data_size); ++ DrvISPMLoadReadData(eMLOAD_ID_FPN_OFFSET, (unsigned short*)buf, FPN_OFFSET_TBL_SIZE); ++ return data_size; ++} ++ ++static int mload_FPN_OFFSET_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ if(offset == 0) ++ { ++ memset(mload_virt_addr,0,FPN_OFFSET_TBL_SIZE*2); ++ memcpy(mload_virt_addr,buf, FPN_OFFSET_TBL_SIZE*2); ++ DrvISPMLoadWriteData(eMLOAD_ID_FPN_OFFSET, mload_dma_addr, FPN_OFFSET_TBL_SIZE); ++ } ++ return size; ++} ++ ++static int mload_ALL_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ return 0; ++} ++ ++static int mload_ALL_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ //pr_info("[%s] called, offset = %#llx , size = %#x", __func__, offset, size); ++ if(offset == 0) ++ { ++ //pr_info("memset mload_virt_addr\n"); ++ memset(mload_virt_addr,0, sizeof(MLoadLayout)); ++ } ++ memcpy(mload_virt_addr+offset, buf, size); ++ ++ if(offset+size == sizeof(MLoadLayout)) ++ { ++ //pr_info("[HalISPMLoadWriteAllTable] called\n"); ++ HalISPMLoadWriteAllTable(mload_dma_addr); ++ } ++ return size; ++} ++ ++ ++void isp_to_scl_ve_isr(void) ++{ ++ print_timestamp("K_ISP2SCL"); ++} ++ ++void scl_ve_isr(void) ++{ ++ print_timestamp("K_SCL_VE"); ++ if (!isp_int.scl_fe){ ++ isp_int.scl_fe = true; ++ wake_up_interruptible_all(&isp_wq_scl_fe); ++ } ++ isp_int.share_data->isp_ints_state.u32IspInt1 |= SCL_VEND_EVENT; ++ isp_int.epoll_event = true; ++ wake_up_interruptible_all(&isp_wq_epoll_event); ++} ++ ++void scl_vs_isr(void) ++{ ++ print_timestamp("K_SCL_VS"); ++ ++} ++ ++static ISP_BIN_ATTR(isp, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(vs_sr, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ve_sr, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae_win0, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae_win1, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(ae_row_int, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(awb, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(af, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(busy, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(idle, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(isp_fifofull, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(wdma_fifofull, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(wdma_done, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(rdma_done, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(eis, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(sw_int_in, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(sw_int_out, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(scl_fe, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_ALSC_R_TBL, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_ALSC_G_TBL, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_ALSC_B_TBL, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_LN_GMA12TO10_R, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_LN_GMA12TO10_G, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_LN_GMA12TO10_B, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_DP_TBL, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_LN_GMA10TO10_R, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_LN_GMA10TO10_G, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_LN_GMA10TO10_B, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_FPN_OFFSET, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(mload_ALL, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++ ++static ssize_t isp_ints_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%s : %d\n","frame_count",isp_int.frame_cnt); ++ str += scnprintf(str, end - str, "%s : %d\n","frame_interval(ns)",isp_int.fps.frame_interval); ++ str += scnprintf(str, end - str, "%s : %d\n","SR_VREF_RISING",isp_int.isp_int_count[INT_SR_VREF_RISING]); ++ str += scnprintf(str, end - str, "%s : %d\n","SR_VREF_FALLING",isp_int.isp_int_count[INT_SR_VREF_FALLING]); ++ str += scnprintf(str, end - str, "%s : %d\n","STROBE_DONE",isp_int.isp_int_count[INT_STROBE_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","DB_UPDATE_DONE",isp_int.isp_int_count[INT_DB_UPDATE_DONE]); ++ ++ //AF_DONE ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","AF_DONE" ++ ,isp_int.isp_int_count[INT_AF_DONE] ++ ,(unsigned int)isp_int.isp_int_time[INT_AF_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_AF_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_FIFO_FUL",isp_int.isp_int_count[INT_ISP_FIFO_FULL]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_BUSY",isp_int.isp_int_count[INT_ISP_BUSY]); ++ str += scnprintf(str, end - str, "%s : %d\n","ISP_IDLE",isp_int.isp_int_count[INT_ISP_IDLE]); ++ ++ //AWB ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","AWB_DONE" ++ ,isp_int.isp_int_count[INT_AWB_DONE] ++ ,(unsigned int)isp_int.isp_int_time[INT_AWB_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_AWB_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","WDMA_DONE",isp_int.isp_int_count[INT_WDMA_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","RDMA_DONE",isp_int.isp_int_count[INT_RDMA_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","WDMA_FIFO_FULL",isp_int.isp_int_count[INT_WDMA_FIFO_FULL]); ++ ++ //PAD_VSYNC_RISING ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","PAD_VSYNC_RISING" ++ ,isp_int.isp_int_count[INT_PAD_VSYNC_RISING] ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_RISING].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_RISING].tv_nsec); ++ ++ //PAD_VSYNC_FALLING ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","PAD_VSYNC_FALLING" ++ ,isp_int.isp_int_count[INT_PAD_VSYNC_FALLING] ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_FALLING].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_PAD_VSYNC_FALLING].tv_nsec); ++ ++ //ISPIF_VSYNC ++ str += scnprintf(str, end - str,"%s : %d ,%u.%09u\n","ISPIF_VSYNC" ++ ,isp_int.isp_int_count[INT_ISPIF_VSYNC] ++ ,(unsigned int)isp_int.isp_int_time[INT_ISPIF_VSYNC].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_ISPIF_VSYNC].tv_nsec); ++ ++ //AE_DONE ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","AE_DONE " ++ ,isp_int.isp_int_count[INT_AE_DONE] ++ ,(unsigned int)isp_int.isp_int_time[INT_AE_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int_time[INT_AE_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_EVERYLINE",isp_int.isp_int2_count[INT2_VDOS_EVERYLINE]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE0",isp_int.isp_int2_count[INT2_VDOS_LINE0]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE1 ",isp_int.isp_int2_count[INT2_VDOS_LINE1]); ++ str += scnprintf(str, end - str, "%s : %d\n","VDOS_LINE2",isp_int.isp_int2_count[INT2_VDOS_LINE2]); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","AE_WIN0_DONE",isp_int.isp_int3_count[INT3_AE_WIN0_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AE_WIN1_DONE",isp_int.isp_int3_count[INT3_AE_WIN1_DONE]); ++ ++ //INT3_AE_BLK_ROW_INT_DONE ++ str += scnprintf(str, end - str, "%s : %d ,%u.%09u\n","INT3_AE_BLK_ROW_INT_DONE" ++ ,isp_int.isp_int3_count[INT3_AE_BLK_ROW_INT_DONE] ++ ,(unsigned int)isp_int.isp_int3_time[INT3_AE_BLK_ROW_INT_DONE].tv_sec ++ ,(unsigned int)isp_int.isp_int3_time[INT3_AE_BLK_ROW_INT_DONE].tv_nsec); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","MENULOAD_DONE",isp_int.isp_int3_count[INT3_MENULOAD_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","SW_INT_INPUT_DONE",isp_int.isp_int3_count[INT3_SW_INT_INPUT_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","SW_INT_OUTPUT_DONE",isp_int.isp_int3_count[INT3_SW_INT_OUTPUT_DONE]); ++ ++ str += scnprintf(str, end - str, "%s : %d\n","HIT_LINE_COUNT1",isp_int.isp_int3_count[INT3_HIT_LINE_COUNT1]); ++ str += scnprintf(str, end - str, "%s : %d\n","HIT_LINE_COUNT2",isp_int.isp_int3_count[INT3_HIT_LINE_COUNT2]); ++ str += scnprintf(str, end - str, "%s : %d\n","HIT_LINE_COUNT3",isp_int.isp_int3_count[INT3_HIT_LINE_COUNT3]); ++ str += scnprintf(str, end - str, "%s : %d\n","HDR_HISTO_DONE",isp_int.isp_int3_count[INT3_HDR_HISTO_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","RGBIR_HISTO_DONE",isp_int.isp_int3_count[INT3_RGBIR_HISTO_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","AWB_ROW_DONE",isp_int.isp_int3_count[INT3_AWB_ROW_DONE]); ++ str += scnprintf(str, end - str, "%s : %d\n","HISTO_ROW_DONE",isp_int.isp_int3_count[INT3_HISTO_ROW_DONE]); ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++DEVICE_ATTR(isp_ints, 0444, isp_ints_show, NULL); ++ ++static ssize_t isp_info_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ //isp_dev_data *data = (isp_dev_data*) dev->platform_data; ++ int n=0; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ for(n=0;nisp_info_str[n]); ++ return (str - buf); ++} ++DEVICE_ATTR(isp_info, 0444, isp_info_show, NULL); ++ ++static ssize_t isp_fps_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "%d\n",1000000000/isp_int.fps.frame_interval); ++ return (str - buf); ++} ++DEVICE_ATTR( isp_fps, 0444, isp_fps_show, NULL); ++ ++static ssize_t csi_ints_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ csi_dev_data *data = (csi_dev_data*) dev->platform_data; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ //frame ++ str += scnprintf(str, end - str, "%s : %d\n","FS_INTS",data->fs_int_count); ++ str += scnprintf(str, end - str, "%s : %d\n","VC0_INTS",data->vc0_int_count); ++ //csi error ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_DT",data->csi_err_int_count[ERR_INT_DT]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_PA_LENS",data->csi_err_int_count[ERR_INT_PA_LENS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_PH_LENS",data->csi_err_int_count[ERR_INT_PH_LENS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_ECC_ONEBIT",data->csi_err_int_count[ERR_INT_ECC_ONEBIT]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_FRAME_START",data->csi_err_int_count[ERR_INT_FRAME_START]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_FRAME_END",data->csi_err_int_count[ERR_INT_FRAME_END]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_ECC_TWOBIT",data->csi_err_int_count[ERR_INT_ECC_TWOBIT]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_CRC",data->csi_err_int_count[ERR_INT_CRC]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_PA_WC_EQ0",data->csi_err_int_count[ERR_INT_PA_WC_EQ0]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_RAW10_LENS",data->csi_err_int_count[ERR_INT_RAW10_LENS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_CON_FE",data->csi_err_int_count[ERR_INT_CON_FE]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_CON_FS",data->csi_err_int_count[ERR_INT_CON_FS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_LE",data->csi_err_int_count[ERR_INT_LE]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_LS",data->csi_err_int_count[ERR_INT_LS]); ++ str += scnprintf(str, end - str, "%s : %d\n","ERR_INT_OVERRUN",data->csi_err_int_count[ERR_INT_OVERRUN]); ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(csi_ints, 0444, csi_ints_show, NULL); ++ ++// CSI debug interrupts // ++static ssize_t csi_dbg_mask_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ csi_dev_data *data = (csi_dev_data*) dev->platform_data; ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "csi dbg mask = 0x%x",HalCsi_ErrIntMaskGet(data->hal_handle)); ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t csi_dbg_mask_store(struct device *dev, struct device_attribute *attr,const char *buf, size_t count) ++{ ++ csi_dev_data *data = (csi_dev_data*) dev->platform_data; ++ if(buf && count>0){ ++ long mask = 0; ++ if( !kstrtol(buf,0,&mask) ){ ++ pr_debug("new mask=0x%X\n",(unsigned int)mask); ++ HalCsi_ErrIntMaskSet(data->hal_handle,mask); ++ } ++ } ++ return count; ++} ++ ++DEVICE_ATTR(csi_dbg_mask, 0644, csi_dbg_mask_show, csi_dbg_mask_store); ++ ++// CSI // ++static int csi_fe_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ csi_dev_data *data = (csi_dev_data*) attr->private; ++ if (wait_event_interruptible(*data->p_wq_fe, data->frame_end == true)) ++ { ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_end = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ return - ERESTARTSYS; ++ } ++ ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_end = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ ++ if (buf && size >= sizeof(data->count) ) { ++ memcpy((void *)buf, (void *)&data->count, sizeof(data->count)); ++ return sizeof(data->count); ++ } ++ ++ return 0; ++} ++ ++static int csi_fe_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++static int csi_fs_read(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ unsigned long flags; ++ csi_dev_data *data = (csi_dev_data*) attr->private; ++ if (wait_event_interruptible(*data->p_wq_fs, data->frame_start == true)){ ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_start = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ return - ERESTARTSYS; ++ } ++ ++ spin_lock_irqsave(&data->lock,flags); ++ data->frame_start = false; ++ spin_unlock_irqrestore(&data->lock,flags); ++ ++ if (buf && size >= sizeof(data->count) ) { ++ memcpy((void *)buf, (void *)&data->count, sizeof(data->count)); ++ return sizeof(data->count); ++ } ++ ++ return 0; ++} ++ ++static int csi_fs_write(struct file *fd, struct kobject *kobj, struct bin_attribute *attr, char *buf, loff_t offset, size_t size) ++{ ++ DBG_INFO(); ++ return size; ++} ++ ++// CSI // ++static ISP_BIN_ATTR(csi_fe, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++static ISP_BIN_ATTR(csi_fs, S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); ++ ++int isp_create_bin_file(struct device *dev) ++{ ++ int error = -EINVAL; ++ if (dev != NULL) { ++ kobj_isp = &dev->kobj; ++ error = sysfs_create_bin_file(kobj_isp, &isp_attr); ++ error = sysfs_create_bin_file(kobj_isp, &vs_sr_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ve_sr_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_win0_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_win1_attr); ++ error = sysfs_create_bin_file(kobj_isp, &ae_row_int_attr); ++ error = sysfs_create_bin_file(kobj_isp, &awb_attr); ++ error = sysfs_create_bin_file(kobj_isp, &af_attr); ++ error = sysfs_create_bin_file(kobj_isp, &busy_attr); ++ error = sysfs_create_bin_file(kobj_isp, &idle_attr); ++ error = sysfs_create_bin_file(kobj_isp, &isp_fifofull_attr); ++ error = sysfs_create_bin_file(kobj_isp, &wdma_fifofull_attr); ++ error = sysfs_create_bin_file(kobj_isp, &wdma_done_attr); ++ error = sysfs_create_bin_file(kobj_isp, &rdma_done_attr); ++ error = sysfs_create_bin_file(kobj_isp, &eis_attr); ++ error = sysfs_create_bin_file(kobj_isp, &sw_int_in_attr); ++ error = sysfs_create_bin_file(kobj_isp, &sw_int_out_attr); ++ error = sysfs_create_bin_file(kobj_isp, &scl_fe_attr); ++ error = device_create_file(dev,&dev_attr_isp_ints); ++ error = device_create_file(dev,&dev_attr_isp_info); ++ error = device_create_file(dev,&dev_attr_isp_fps); ++ error = sysfs_create_bin_file(kobj_isp, &mload_ALSC_R_TBL_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_ALSC_G_TBL_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_ALSC_B_TBL_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_LN_GMA12TO10_R_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_LN_GMA12TO10_G_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_LN_GMA12TO10_B_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_DP_TBL_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_LN_GMA10TO10_R_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_LN_GMA10TO10_G_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_LN_GMA10TO10_B_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_FPN_OFFSET_attr); ++ error = sysfs_create_bin_file(kobj_isp, &mload_ALL_attr); ++ } ++ return error; ++} ++ ++void isp_remove_bin_file(void) ++{ ++ sysfs_remove_bin_file(kobj_isp, &isp_attr); ++ sysfs_remove_bin_file(kobj_isp, &vs_sr_attr); ++ sysfs_remove_bin_file(kobj_isp, &ve_sr_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_win0_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_win1_attr); ++ sysfs_remove_bin_file(kobj_isp, &ae_row_int_attr); ++ sysfs_remove_bin_file(kobj_isp, &awb_attr); ++ sysfs_remove_bin_file(kobj_isp, &af_attr); ++ sysfs_remove_bin_file(kobj_isp, &busy_attr); ++ sysfs_remove_bin_file(kobj_isp, &idle_attr); ++ sysfs_remove_bin_file(kobj_isp, &isp_fifofull_attr); ++ sysfs_remove_bin_file(kobj_isp, &wdma_fifofull_attr); ++ sysfs_remove_bin_file(kobj_isp, &wdma_done_attr); ++ sysfs_remove_bin_file(kobj_isp, &rdma_done_attr); ++ sysfs_remove_bin_file(kobj_isp, &eis_attr); ++ sysfs_remove_bin_file(kobj_isp, &sw_int_in_attr); ++ sysfs_remove_bin_file(kobj_isp, &sw_int_out_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_ALSC_R_TBL_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_ALSC_G_TBL_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_ALSC_B_TBL_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_LN_GMA12TO10_R_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_LN_GMA12TO10_G_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_LN_GMA12TO10_B_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_DP_TBL_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_LN_GMA10TO10_R_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_LN_GMA10TO10_G_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_LN_GMA10TO10_B_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_FPN_OFFSET_attr); ++ sysfs_remove_bin_file(kobj_isp, &mload_ALL_attr); ++} ++ ++ ++int csi_create_bin_file(struct device *dev) ++{ ++ int error = -EINVAL; ++ if(!dev) ++ return error; ++ ++ if(dev != NULL) ++ { ++ csi_dev_data *data = dev_get_platdata(dev); ++ //frame end ++ csi_fe_attr.private = (void*)data; ++ error = sysfs_create_bin_file(&dev->kobj, &csi_fe_attr); ++ ++ //frame start ++ csi_fs_attr.private = (void*)data; ++ error = sysfs_create_bin_file(&dev->kobj, &csi_fs_attr); ++ ++ //CSI error report interrupt ++ error = device_create_file(dev, &dev_attr_csi_dbg_mask); ++ //CSI interrupt counter ++ error = device_create_file(dev, &dev_attr_csi_ints); ++ } ++ return error; ++} ++ ++void csi_remove_bin_file(struct device *dev) ++{ ++ sysfs_remove_bin_file(&dev->kobj, &csi_fs_attr); ++ sysfs_remove_bin_file(&dev->kobj, &csi_fe_attr); ++} ++ ++static int csi_probe(struct platform_device* pdev) ++{ ++ int err, ret; ++ int irq, u4IO_PHY_BASE; ++ unsigned int u4Bank; ++ csi_dev_data *data; ++ data = kzalloc(sizeof(csi_dev_data),GFP_KERNEL); ++ if(!data) ++ return -ENOENT; ++ ++ ret = of_property_read_u32(pdev->dev.of_node, "io_phy_addr", &u4IO_PHY_BASE); //get custom property, OPR base address ++ if(ret != 0) ++ pr_err("[ISP] read node error!\n"); ++ ret = of_property_read_u32(pdev->dev.of_node, "banks", &u4Bank); //get custom property, CSI OPR bank offset ++ if(ret != 0) ++ pr_err("[ISP] read node error!\n"); ++ ++ data->reg_base = (void*)ioremap(BANK_TO_ADDR32(u4Bank)+u4IO_PHY_BASE, 0x200); ++ pr_debug("[%s] IO remap phys:0x%.8x virt: 0x%.8x\n", __FUNCTION__, ++ BANK_TO_ADDR32(u4Bank)+u4IO_PHY_BASE, ++ (u32) data->reg_base ); //(u32) isp_mem.pCSIRegs ); ++ ++ data->sysfs_dev = device_create(msys_get_sysfs_class(), NULL, MKDEV(MAJOR_ISP_NUM, MINOR_CSI_NUM), NULL, "csi0"); ++ csi_create_bin_file(data->sysfs_dev); ++ err = sysfs_create_link(&pdev->dev.parent->kobj,&data->sysfs_dev->kobj, "csi0"); //create symlink for older firmware version ++ data->sysfs_dev->platform_data = pdev->dev.platform_data = (void*)data; ++ ++ //TODO, init status ++ data->lock = __SPIN_LOCK_UNLOCKED("csi_lock"); ++ data->count = 0; ++ data->frame_end = false; ++ ++ data->p_wq_fe = &isp_wq_VEND; //notify isp frame end ++ data->p_wq_fs = &isp_wq_VSTART; //notify ISP frame start ++ ++ //TODO: CSI clock enable ++ data->hal_handle = HalCsi_Open(data->reg_base); ++ if(!data->hal_handle) ++ return -ENOENT; ++ HalCsi_RegInit(data->hal_handle); ++ ++ pdev->dev.platform_data = (void*)data; ++ ++ irq = irq_of_parse_and_map(pdev->dev.of_node, 0); //get device IRQ#0 ++ pr_debug("request IRQ#%d\n",irq); ++ ++ if (request_irq(irq, csi_ISR, 0, "csi interrupt", (void*)data) == 0) ++ pr_debug("csi interrupt registered.\n"); ++ else ++ pr_err("failed to request IRQ#%d\n",irq); ++ ++ return 0; ++} ++ ++static int csi_remove(struct platform_device* pdev) ++{ ++ csi_dev_data *data = (csi_dev_data *)pdev->dev.platform_data; ++ HalCsi_Close(data->hal_handle); ++ iounmap(data->reg_base); ++ kfree(data); ++ csi_remove_bin_file(&pdev->dev); ++ device_destroy(msys_get_sysfs_class(),MKDEV(MAJOR_ISP_NUM, MINOR_CSI_NUM)); ++ return 0; ++} ++ ++static int csi_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ csi_dev_data *data = (csi_dev_data *)pdev->dev.platform_data; ++ HalCsi_RegUninit(data->hal_handle); ++ return 0; ++} ++ ++static int csi_resume(struct platform_device *pdev) ++{ ++ csi_dev_data *data = (csi_dev_data *)pdev->dev.platform_data; ++ HalCsi_RegInit(data->hal_handle); ++ return 0; ++} ++ ++#define INC_CSI_ERR_COUNT(name) (data->csi_err_int_count[name]++) ++irqreturn_t csi_ISR(int num, void *priv) ++{ ++ csi_dev_data *data = (csi_dev_data*)priv; ++ void* hal = data->hal_handle; ++ ++ u32 rpt_clear = 0; ++ u32 err_clear = 0; ++ u32 rpt_status = HalCsi_GetRptIntStatus(hal); ++ u32 err_status = HalCsi_GetErrorIntStatus(hal); ++ HalCsi_MaskRptInt(hal,rpt_status); ++ HalCsi_MaskErrorInt(hal,err_status); ++#if 0 ++ if(ISP_CHECKBITS(rpt_status,RPT_INT_FRAME)) //frame start interrupt ++ { ++ isp_int.vsync_start= true; //notify ISP fs ++ isp_int.frame_cnt++; ++ ISP_SETBIT(rpt_clear,RPT_INT_FRAME); ++ data->fs_int_count++; ++ wake_up_interruptible_all(data->p_wq_fs); ++ DBG_INFO_1( "[%s] FRAME INT \n", __FUNCTION__); ++ } ++#endif ++ if(ISP_CHECKBITS(rpt_status,RPT_INT_VC0)){ //frame end interrupt ++ print_timestamp("K_VE");//TEST CODE ++ isp_int.vsync_end = true; //notify ISP fe ++ isp_int.share_data->frame_state.bActive = false; ++ isp_apply_iq_at_vend(); ++ if(isp_int.fifo_mask.dirty) ++ { ++ IspInputEnable(~isp_int.fifo_mask.enable); ++ isp_int.fifo_mask.dirty = 0; ++ } ++ ISP_SETBIT(rpt_clear,RPT_INT_VC0); ++ data->vc0_int_count++; ++ wake_up_interruptible_all(data->p_wq_fe); ++ // Using menuload to write IQ table to SRAMs ++ //isp_write_iq_tbl(); ++ data->count++; ++ ++ //record csi frame end interrupt time to PAD_FAILLING ++ getnstimeofday(&isp_int.isp_int_time[INT_PAD_VSYNC_FALLING]); ++ ++ DBG_INFO( "[%s] VC0 INT %lld \n", __FUNCTION__,data->count); ++ } ++ ++ if(err_status){ ++ if(ISP_CHECKBITS(err_status,ERR_INT_DT)){ //frame end interrupt ++ ISP_SETBIT(err_clear,ERR_INT_DT); ++ INC_CSI_ERR_COUNT(ERR_INT_DT); ++ DBG_INFO_1( "[%s] ERR_INT_DT %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_PA_LENS)){ //frame end interrupt ++ ISP_SETBIT(err_clear,ERR_INT_PA_LENS); ++ INC_CSI_ERR_COUNT(ERR_INT_PA_LENS); ++ DBG_INFO_1( "[%s] ERR_INT_PA_LENS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_PH_LENS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_PH_LENS); ++ INC_CSI_ERR_COUNT(ERR_INT_PH_LENS); ++ DBG_INFO_1( "[%s] ERR_INT_PH_LENS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_ECC_ONEBIT)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_ECC_ONEBIT); ++ INC_CSI_ERR_COUNT(ERR_INT_ECC_ONEBIT); ++ DBG_INFO_1( "[%s] ERR_INT_ECC_ONEBIT %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_FRAME_START)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_FRAME_START); ++ INC_CSI_ERR_COUNT(ERR_INT_FRAME_START); ++ DBG_INFO_1( "[%s] ERR_INT_FRAME_START %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_FRAME_END)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_FRAME_END); ++ INC_CSI_ERR_COUNT(ERR_INT_FRAME_END); ++ DBG_INFO_1( "[%s] ERR_INT_FRAME_START %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_ECC_TWOBIT)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_ECC_TWOBIT); ++ INC_CSI_ERR_COUNT(ERR_INT_ECC_TWOBIT); ++ DBG_INFO_1( "[%s] ERR_INT_FRAME_START %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_CRC)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_CRC); ++ INC_CSI_ERR_COUNT(ERR_INT_CRC); ++ DBG_INFO_1( "[%s] ERR_INT_CRC %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_PA_WC_EQ0)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_PA_WC_EQ0); ++ INC_CSI_ERR_COUNT(ERR_INT_PA_WC_EQ0); ++ DBG_INFO_1( "[%s] ERR_INT_PA_WC_EQ0 %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_RAW10_LENS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_RAW10_LENS); ++ INC_CSI_ERR_COUNT(ERR_INT_RAW10_LENS); ++ DBG_INFO_1( "[%s] ERR_INT_RAW10_LENS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_CON_FE)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_CON_FE); ++ INC_CSI_ERR_COUNT(ERR_INT_CON_FE); ++ DBG_INFO_1( "[%s] ERR_INT_CON_FE %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_CON_FS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_CON_FS); ++ INC_CSI_ERR_COUNT(ERR_INT_CON_FS); ++ DBG_INFO_1( "[%s] ERR_INT_CON_FS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_LE)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_LE); ++ INC_CSI_ERR_COUNT(ERR_INT_LE); ++ DBG_INFO_1( "[%s] ERR_INT_LE %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_LS)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_LS); ++ INC_CSI_ERR_COUNT(ERR_INT_LS); ++ DBG_INFO_1( "[%s] ERR_INT_LS %lld \n", __FUNCTION__,data->count); ++ } ++ if(ISP_CHECKBITS(err_status,ERR_INT_OVERRUN)) //frame end interrupt ++ { ++ ISP_SETBIT(err_clear,ERR_INT_OVERRUN); ++ INC_CSI_ERR_COUNT(ERR_INT_OVERRUN); ++ DBG_INFO_1( "[%s] ERR_INT_OVERRUN %lld \n", __FUNCTION__,data->count); ++ } ++ } ++ ++ //clear ISR ++ HalCsi_ClearRptInt(hal,rpt_clear); //clear and unmask interrupt ++ ++ //clear Error ISR ++ HalCsi_ClearErrorInt(hal,err_clear); //clear and unmask interrupt ++ ++ return IRQ_HANDLED; ++} ++ ++static int __init mstar_isp_init(void) ++{ ++ int ret; ++ memset((void*)&isp_int, 0, sizeof(isp_int)); ++ isp_int.sysfs_int = false; ++ ++ ret = platform_driver_register(&isp_driver); ++ if(!ret) ++ { ++ printk(KERN_INFO "[ISP] register driver success"); ++ } ++ else ++ { ++ pr_err("[ISP] register driver fail"); ++ platform_driver_unregister(&isp_driver); ++ return ret; ++ } ++ ++ ret = platform_driver_register(&csi_driver); ++ if(!ret) ++ { ++ printk(KERN_INFO "[CSI] register driver success"); ++ } ++ else ++ { ++ pr_err("[CSI] register driver fail"); ++ platform_driver_unregister(&csi_driver); ++ return ret; ++ } ++ return 0; ++} ++ ++static void __exit mstar_isp_exit(void) ++{ ++ platform_driver_unregister(&isp_driver); ++ isp_remove_bin_file(); ++ pr_debug("[ISP] exit"); ++} ++ ++//isp resolution parameter ++static int __init isp_res_early_init(char *opt) ++{ ++ long res = 1; ++ if(!kstrtol(opt,10,&res)) ++ { ++ g_isp_max_res = res; ++ } ++ else ++ { ++ printk("Invaild param : isp_res=%s\n",opt); ++ } ++ return 0; ++} ++early_param("isp_res", isp_res_early_init); ++ ++//isp flags ++static int __init isp_flag_early_init(char *opt) ++{ ++ long flag = ISP_FB_DNR | ISP_FB_ROT; ++ if(!kstrtol(opt,16,&flag)) ++ { ++ g_isp_flag = flag; ++ } ++ return 0; ++} ++early_param("isp_flag", isp_flag_early_init); ++ ++module_init(mstar_isp_init); ++module_exit(mstar_isp_exit); ++ ++#endif//__DRV_ISP_C__ +diff --git a/drivers/mstar/isp/infinity3/hal_isp.c b/drivers/mstar/isp/infinity3/hal_isp.c +new file mode 100644 +index 00000000..11406cc9 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/hal_isp.c +@@ -0,0 +1,1186 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "MsTypes.h" ++#include "ms_platform.h" ++ ++#include "infinity3e_reg_isp0.h" ++#include "infinity3e_reg_isp1.h" ++#include "infinity3e_reg_isp2.h" ++#include "infinity3e_reg_isp3.h" ++#include "infinity3e_reg_isp4.h" ++#include "infinity3e_reg_isp5.h" ++#include "infinity3e_reg_isp6.h" ++#include "infinity3e_reg_isp7.h" ++#include "infinity3e_reg_isp8.h" ++#include "infinity3e_reg_isp9.h" ++ ++#include ++#include ++ ++#include "hal_isp.h" ++ ++#define PAD16BITS u32 :16 ++#define RSVD(ss,ee) u32 rsvd_##ss##_##ee[(ee) - (ss) + 1] ++typedef infinity3e_reg_isp0 isp0_cfg_t; ++ ++static volatile infinity3e_reg_isp0 *pISP_INT; ++ ++static volatile infinity3e_reg_isp3 *isp_miu_bases; ++static volatile infinity3e_reg_isp8 *isp_rgbir_miu_bases; ++ ++//static volatile u32 *isp_afsts; // 0x35 ++ ++typedef struct { ++ u32 null:1; ++ u32 blinking:1; ++ u32 embedded:1; ++ u32 :5; ++ u32 :6; ++ u32 YUV4228B:1; ++ u32 :1; ++ PAD16BITS; ++ u32 :8; //16:23 ++ u32 :2; ++ u32 RAW8:1; ++ u32 RAW10:1; ++ u32 RAW12:1; ++ u32 :3; ++ PAD16BITS; ++ PAD16BITS; ++ PAD16BITS; ++}__attribute__((packed, aligned(1))) csi_dt; ++ ++typedef struct { ++ //0x0000 ++ u32 :1; ++ u32 reg_ecc_off :1; ++ u32 reg_lane_en :4; ++ u32 reg_rm_err_sot:1; ++ u32 reg_fun_md :2; ++ u32 reg_vc_en :4; ++ u32 reg_rm_err_fs :1; ++ u32 reg_uy_vy_sel :1; ++ u32 :1; ++ PAD16BITS; ++#define CSI_LAN0_EN 0x01 ++#define CSI_LAN1_EN 0x02 ++#define CSI_LAN2_EN 0x04 ++#define CSI_LAN3_EN 0x08 ++#define CSI_VC0_EN 0x01 ++#define CSI_VC1_EN 0x02 ++#define CSI_VC3_EN 0x04 ++#define CSI_VC4_EN 0x08 ++ ++ //0x0004 ++ u32 reg_vc0_hs_mode:3; ++ u32 reg_vc1_hs_mode:3; ++ u32 reg_vc2_hs_mode:3; ++ u32 reg_vc3_hs_mode:3; ++ u32 reg_debug_sel :4; ++ PAD16BITS; ++ ++ //0x0008 ++ u32 reg_vc0_vs_mode:3; ++ u32 reg_vc1_vs_mode:3; ++ u32 reg_vc2_vs_mode:3; ++ u32 reg_vc3_vs_mode:3; ++ u32 reg_debug_en :1; ++ u32 :3; ++ PAD16BITS; ++#define CSI_V_SYNC_MODE_FS 0x00 ++#define CSI_V_SYNC_MODE_FE 0x01 ++ ++ //0x000C ++ u32 reg_mac_err_int_mask:15; ++ u32 :1; ++ PAD16BITS; ++ ++ //0x0010 ++ u32 reg_mac_err_int_force:15; ++ u32 :1; ++ PAD16BITS; ++ ++ //0x0014 ++ u32 reg_mac_err_int_clr:15; ++ u32 :1; ++ PAD16BITS; ++ ++ //0x0018 ++ u32 reg_mac_rpt_int_mask:7; ++ u32 :9; ++ PAD16BITS; ++#define CSI_LINE_INT 0x01 ++#define CSI_FRAME_INT 0x02 ++#define CSI_VC3_FE_INT 0x08 ++#define CSI_VC2_FE_INT 0x10 ++#define CSI_VC1_FE_INT 0x20 ++#define CSI_VC0_INT 0x40 //FS or FE depend on reg_mac_rpt_int_src[1] selection ++ ++ u32 reg_mac_rpt_int_force:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_mac_rpt_int_clr:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_phy_int_mask:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_phy_int_force:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_phy_int_clr:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_mac_err_int_src:15; ++ u32 :1; ++ PAD16BITS; ++ ++ u32 reg_mac_err_int_raw_src:15; ++ u32 :1; ++ PAD16BITS; ++ ++ u32 reg_mac_rpt_int_src:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_mac_rpt_int_raw_src:7; ++ u32 :9; ++ PAD16BITS; ++ ++ u32 reg_phy_int_src:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_phy_int_raw_src:10; ++ u32 :6; ++ PAD16BITS; ++ ++ u32 reg_frm_num:16; ++ PAD16BITS; ++ ++ u32 reg_line_num:16; ++ PAD16BITS; ++ ++ u32 reg_g8spd_wc:16; ++ PAD16BITS; ++ ++ u32 reg_g8spd_dt:8; ++ u32 :8; ++ PAD16BITS; ++ ++ u32 reg_mac_idle:1; ++ u32 :15; ++ PAD16BITS; ++ ++ u32 reg_1frame_trig:1; ++ u32 :15; ++ PAD16BITS; ++ ++ u32 reg_ckg_csi_mac:6; ++ u32 :2; ++ u32 reg_ckg_csi_mac_lptx:5; ++ u32 :3; ++ PAD16BITS; ++ ++ u32 reg_ckg_ns:5; ++ u32 :11; ++ PAD16BITS; ++ ++ u32 reg_csi_mac_reserved:16; ++ PAD16BITS; ++ ++ u32 reg_csi_mac_reserved1:16; ++ PAD16BITS; ++ ++ u32 reg_csi_mac_reserved2:16; ++ PAD16BITS; ++ ++ csi_dt reg_dt_en; ++ ++ u32 reg_sw_rst :1; ++ u32 reg_mac_en :1; ++ u32 reg_dont_care_dt:1; ++ u32 :13; ++ PAD16BITS; ++ ++ u32 reg_raw_l_sot_sel:2; ++ u32 reg_sot_sel :1; ++ u32 reg_eot_sel :1; ++ u32 reg_rpt_fnum_cond:1; ++ u32 reg_rpt_lnum_cond:1; ++ u32 :10; ++ PAD16BITS; ++#define CSI_RPT_FS 0x0 //report frame start ++#define CSI_RTP_FE 0x01 //report frame end ++ ++ u32 reg_clk_lane_fsm_sts_int_mask:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_force:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_clr:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_src:16; ++ PAD16BITS; ++ ++ u32 reg_clk_lane_fsm_sts_int_raw_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_mask:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_force:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_clr:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane0_fsm_sts_int_raw_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_mask:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_force:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_clr:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_src:16; ++ PAD16BITS; ++ ++ u32 reg_data_lane1_fsm_sts_int_raw_src:16; ++ PAD16BITS; ++ } __attribute__((packed, aligned(1))) csi_mac; ++ ++static volatile infinity3e_reg_isp4 *isp_miu; ++ ++static volatile u32 *isp_vdos_pitch; ++static volatile u32 *isp_vdos_addr; ++ ++static volatile void *RIUBASE_ISP[10] = {0}; ++ ++// mload variable ++dma_addr_t mload_dma_addr = 0; ++u8 *mload_virt_addr = NULL; ++static DEFINE_MUTEX(mloadMutex); ++u32 pTableSize[eMLOAD_ID_NUM] = { ++ ALSC_TBL_SIZE, //eMLOAD_ID_ALSC_R_TBL = 0 ++ ALSC_TBL_SIZE, //eMLOAD_ID_ALSC_G_TBL = 1 ++ ALSC_TBL_SIZE, //eMLOAD_ID_ALSC_B_TBL = 2 ++ GAMMA_TBL_SIZE, //eMLOAD_ID_LN_GMA12TO10_R = 3 ++ GAMMA_TBL_SIZE, //eMLOAD_ID_LN_GMA12TO10_G = 4 ++ GAMMA_TBL_SIZE, //eMLOAD_ID_LN_GMA12TO10_B = 5 ++ DEFECTPIX_TBL_SIZE, //eMLOAD_ID_DP_TBL = 6 ++ 0, ++ 0, ++ 0, ++ GAMMA_TBL_SIZE, //eMLOAD_ID_LN_GMA10TO10_R = 10 ++ GAMMA_TBL_SIZE, // eMLOAD_ID_LN_GMA10TO10_G = 11 ++ GAMMA_TBL_SIZE, //eMLOAD_ID_LN_GMA10TO10_B = 12 ++ 0, ++ FPN_OFFSET_TBL_SIZE, //eMLOAD_ID_FPN_OFFSET 14 ++}; ++ ++// memory offset in dma memory address ++u32 tblOffset[eMLOAD_ID_NUM] = { ++ offsetof(MLoadLayout,alsc_r), ++ offsetof(MLoadLayout,alsc_g), ++ offsetof(MLoadLayout,alsc_b), ++ offsetof(MLoadLayout,gamma12to10_r), ++ offsetof(MLoadLayout,gamma12to10_g), ++ offsetof(MLoadLayout,gamma12to10_b), ++ offsetof(MLoadLayout,dpc), ++ 0, ++ 0, ++ 0, ++ offsetof(MLoadLayout,gamma10to10_r), ++ offsetof(MLoadLayout,gamma10to10_g), ++ offsetof(MLoadLayout,gamma10to10_b), ++ 0, ++ offsetof(MLoadLayout,fpn), ++}; ++ ++static volatile u32 u4DefDisable[3] = ++{ ++ //interrupt group 0 ++ ISP_SHIFTBITS(INT_DB_UPDATE_DONE)|ISP_SHIFTBITS(INT_SR_VREF_RISING)|ISP_SHIFTBITS(INT_SR_VREF_FALLING)|ISP_SHIFTBITS(INT_ISP_BUSY)|ISP_SHIFTBITS(INT_ISP_IDLE)|ISP_SHIFTBITS(INT_PAD_VSYNC_RISING)|ISP_SHIFTBITS(INT_PAD_VSYNC_FALLING), ++ //interrupt group 1 ++ ISP_SHIFTBITS(INT2_VDOS_EVERYLINE)|ISP_SHIFTBITS(INT2_VDOS_LINE0)|ISP_SHIFTBITS(INT2_VDOS_LINE1)|ISP_SHIFTBITS(INT2_VDOS_LINE2), ++ //interrupt group 2 ++ ISP_SHIFTBITS(INT3_AE_WIN1_DONE)|ISP_SHIFTBITS(INT3_MENULOAD_DONE) ++ //|ISP_SHIFTBITS(INT3_SW_INT_OUTPUT_DONE) ++ //|ISP_SHIFTBITS(INT3_SW_INT_INPUT_DONE) ++ //|ISP_SHIFTBITS(INT3_HIT_LINE_COUNT1)|ISP_SHIFTBITS(INT3_HIT_LINE_COUNT2)|ISP_SHIFTBITS(INT3_HIT_LINE_COUNT3) ++ |ISP_SHIFTBITS(INT3_AWB_ROW_DONE)|ISP_SHIFTBITS(INT3_HISTO_ROW_DONE) ++ |ISP_SHIFTBITS(INT3_RESERVED0)|ISP_SHIFTBITS(INT3_RESERVED1)|ISP_SHIFTBITS(INT3_RESERVED2) ++}; ++ ++inline void HalInitRegs(void **pRegs) ++{ ++ int i = 0; ++ for (i = 0; i < 10; i++) ++ RIUBASE_ISP[i] = (void*)pRegs[i]; ++ ++ // disable double buffer ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x1*4) |= (1<<15); ++ // init frame cnt ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x7a*4) = 0; ++ ++ // structured INT ++ pISP_INT = (volatile infinity3e_reg_isp0*)(RIUBASE_ISP[0]); ++ ++ // statistics output address ++ isp_miu_bases = (volatile infinity3e_reg_isp3*)(RIUBASE_ISP[3]); ++ isp_rgbir_miu_bases = (volatile infinity3e_reg_isp8*)(RIUBASE_ISP[8]); ++ // menuload ++ isp_miu = (infinity3e_reg_isp4 *)(RIUBASE_ISP[4]); ++ ++ // vdos ++ isp_vdos_pitch = (volatile u32*)(RIUBASE_ISP[6] + 0x21*4); ++ isp_vdos_addr = (volatile u32*)(RIUBASE_ISP[6] + 0x28*4); ++ ++ // disable clock gating ++ (*(u16*)(RIUBASE_ISP[0] + 0x64*4)) &= ~0x0004; ++ ++ mload_virt_addr = mloadInit(sizeof(MLoadLayout)); ++ pr_info("mload_size = %d\n", sizeof(MLoadLayout)); ++ pr_info("mload_virt_addr = %p\n", mload_virt_addr); ++ pr_info("mload_dma_addr = %#x\n", mload_dma_addr); ++} ++ ++inline void HalISPDisableInt() ++{ ++ pISP_INT->reg_c_irq_mask = 0xffff; ++ pISP_INT->reg_c_irq_mask2 = 0x000f; ++ pISP_INT->reg_c_irq_mask3 = 0x00ff; ++} ++ ++inline void HalISPEnableInt() ++{ ++ pISP_INT->reg_c_irq_mask = u4DefDisable[0]; ++ pISP_INT->reg_c_irq_mask2 = u4DefDisable[1]; ++ pISP_INT->reg_c_irq_mask3 = u4DefDisable[2]; ++ ++ pISP_INT->reg_c_irq_clr = 0xffff & ~(u4DefDisable[0]); ++ pISP_INT->reg_c_irq_clr = 0; ++ pISP_INT->reg_c_irq_clr2 = 0x00ff & ~(u4DefDisable[1]); ++ pISP_INT->reg_c_irq_clr2 = 0; ++ pISP_INT->reg_c_irq_clr3 = 0x00ff & ~(u4DefDisable[2]); ++ pISP_INT->reg_c_irq_clr3 = 0; ++ ++} ++ ++#if 0 ++inline void HalISPMaskIntAll() ++{ ++ pISP_INT->reg_c_irq_mask = 0xffff; ++ pISP_INT->reg_c_irq_mask2 = 0x000f; ++ pISP_INT->reg_c_irq_mask3 = 0x00ff; ++ ++ pISP_INT->reg_c_irq_clr = 0xffff & ~(u4DefDisable[0]); ++ pISP_INT->reg_c_irq_clr2 = 0x000f & ~(u4DefDisable[1]); ++ pISP_INT->reg_c_irq_clr3 = 0x003f & ~(u4DefDisable[2]); ++} ++#endif ++ ++inline u32 HalISPGetIntStatus1() ++{ ++ return (~pISP_INT->reg_c_irq_mask) & pISP_INT->reg_irq_final_status; ++} ++ ++inline u32 HalISPGetIntStatus2() ++{ ++ return (~pISP_INT->reg_c_irq_mask2) & pISP_INT->reg_irq_final_status2; ++} ++ ++inline u32 HalISPGetIntStatus3() ++{ ++ return (~pISP_INT->reg_c_irq_mask3) & pISP_INT->reg_irq_final_status3; ++} ++ ++inline void HalISPMaskClear1(u32 clear) ++{ ++ pISP_INT->reg_c_irq_clr |= clear; ++ pISP_INT->reg_c_irq_clr = 0; ++ //pISP_INT->reg_c_irq_mask = u4DefDisable[0]; ++} ++ ++inline void HalISPMaskClear2(u32 clear) ++{ ++ pISP_INT->reg_c_irq_clr2 |= clear; ++ pISP_INT->reg_c_irq_clr2 = 0; ++ //pISP_INT->reg_c_irq_mask2 = u4DefDisable[1]; ++} ++ ++inline void HalISPMaskClear3(u32 clear) ++{ ++ pISP_INT->reg_c_irq_clr3 |= clear; ++ pISP_INT->reg_c_irq_clr3 = 0; ++ //pISP_INT->reg_c_irq_mask3 = u4DefDisable[2]; ++} ++ ++inline void HalISPMaskInt1(u32 mask) ++{ ++ pISP_INT->reg_c_irq_mask |= (mask|u4DefDisable[0]); ++} ++ ++inline void HalISPMaskInt2(u32 mask) ++{ ++ pISP_INT->reg_c_irq_mask2 |= (mask|u4DefDisable[1]); ++} ++ ++inline void HalISPMaskInt3(u32 mask) ++{ ++ pISP_INT->reg_c_irq_mask3 |= (mask|u4DefDisable[2]); ++} ++ ++inline void HalISPClearInt(volatile u32 *clear, ISP_INT_STATUS int_num) ++{ ++ *clear |= (0x01<reg_c_irq_mask = pISP_INT->reg_c_irq_clr; ++ pISP_INT->reg_c_irq_clr = 0; ++ pISP_INT->reg_c_irq_mask2 = pISP_INT->reg_c_irq_clr2; ++ pISP_INT->reg_c_irq_clr2 = 0; ++ pISP_INT->reg_c_irq_mask3 = pISP_INT->reg_c_irq_clr3; ++ pISP_INT->reg_c_irq_clr3 = 0; ++} ++#endif ++ ++inline void HalISPClkEnable(bool enable) ++{ ++ if (enable == false) ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x66*4) |= (u16)0x04; // 0x35 ++ else ++ *(volatile u32*)(RIUBASE_ISP[0] + 0x66*4) &= ~((u16)0x04); ++} ++ ++inline u32 HalISPGetVsyncPol() ++{ ++ return (pISP_INT->reg_sensor_vsync_polarity & 0x01); ++} ++ ++inline u32 HalISPGetMIPI(void) ++{ ++ return (pISP_INT->reg_isp_if_src_sel & 0x01); ++} ++ ++inline void HalISPGetAFStat(volatile unsigned long *Stat) ++{ ++ int i = 0; ++ volatile u32* isp_afsts = (volatile u32*)(RIUBASE_ISP[5] + 0x18*4); ++ unsigned long value = 0, LSB = 0, MSB = 0; ++ if (Stat) ++ for (i = 0; i < 15*2; i+=2) { ++ LSB = *(u32 *)(isp_afsts+i)&0xffff; ++ MSB = *(u32 *)(isp_afsts+(i+1))&0xffff; ++ value = LSB | (MSB << 16); ++ Stat[i/2] = value; ++ } ++} ++ ++inline void HalISPGetVDOSPitch(volatile int *pPitch) ++{ ++ if (pPitch) ++ *pPitch = *(int *)isp_vdos_pitch; ++} ++ ++inline void HalISPGetVDOSSize(volatile int *pSize, volatile int Pitch) ++{ ++ if (pSize) ++ *pSize = Pitch * 24; // pitch * 3 * 8bytes ++} ++ ++inline void HalISPGetVDOSData(volatile unsigned long *pAddr, volatile int Size) ++{ ++ if (pAddr) ++ memcpy((void *)pAddr, (void *)isp_vdos_addr, Size); ++} ++ ++inline void HalISPSetAeBaseAddr(unsigned long Addr,unsigned int size) ++{ ++ unsigned long MiuAddr = Chip_Phys_to_MIU(Addr); ++ isp_miu_bases->reg_ae_statis_base = MiuAddr>>4; ++ isp_miu_bases->reg_ae_statis_base_1 = MiuAddr>>20; ++ //set dma upper bound ++ MiuAddr = Chip_Phys_to_MIU(Addr+size); ++ isp_miu_bases->reg_ae_max_wadr = MiuAddr >> 4; ++ isp_miu_bases->reg_ae_max_wadr_1 = MiuAddr >> 20; ++} ++ ++inline void HalISPSetAwbBaseAddr(volatile unsigned long Addr,unsigned int size) ++{ ++ unsigned long MiuAddr = Chip_Phys_to_MIU(Addr); ++ isp_miu_bases->reg_awb_statis_base = MiuAddr>>4; ++ isp_miu_bases->reg_awb_statis_base_1 = MiuAddr>>20; ++ //set dma upper bound ++ MiuAddr = Chip_Phys_to_MIU(Addr+size); ++ isp_miu_bases->reg_awb_max_wadr = MiuAddr >> 4; ++ isp_miu_bases->reg_awb_max_wadr_1 = MiuAddr >> 20; ++} ++ ++inline void HalISPSetAfBaseAddr(volatile unsigned long Addr,unsigned int size) ++{ ++ volatile infinity3e_reg_isp5 *isp5 = (infinity3e_reg_isp5*) RIUBASE_ISP[5]; ++ unsigned long MiuAddr = Chip_Phys_to_MIU(Addr); ++ isp5->reg_af_dma_addr = MiuAddr>>4; ++ isp5->reg_af_dma_addr_1 = MiuAddr>>20; ++ //set dma upper bound ++ MiuAddr = Chip_Phys_to_MIU(Addr+size); ++ isp5->reg_af_max_wadr = MiuAddr >> 4; ++ isp5->reg_af_max_wadr_1 = MiuAddr >> 20; ++} ++ ++//set motion detection statisic buffer address ++inline void HalISPSetMotBaseAddr(volatile unsigned long Addr,unsigned int size) ++{ ++ unsigned long MiuAddr = Chip_Phys_to_MIU(Addr); ++ if(Addr & 0x0F) ++ { ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ isp_miu_bases->reg_mot_fb_base = MiuAddr>>4; ++ isp_miu_bases->reg_mot_fb_base_1 = MiuAddr>>20; ++} ++ ++inline void HalISPSetHistoBaseAddr(unsigned long Addr,unsigned int size) ++{ ++ unsigned long MiuAddr = Chip_Phys_to_MIU(Addr); ++ if(Addr & 0x0F) ++ { ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ isp_miu_bases->reg_histo_statis_base = MiuAddr>>4; ++ isp_miu_bases->reg_histo_statis_base_1 = MiuAddr>>20; ++ //set dma upper bound ++ MiuAddr = Chip_Phys_to_MIU(Addr+size); ++ isp_miu_bases->reg_histo_max_wadr = MiuAddr >> 4; ++ isp_miu_bases->reg_histo_max_wadr_1 = MiuAddr >> 20; ++} ++ ++inline void HalISPSetRgbIRBaseAddr(unsigned long Addr,unsigned int size) ++{ ++ unsigned long MiuAddr = Chip_Phys_to_MIU(Addr); ++ if(Addr & 0x0F) ++ { ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ isp_rgbir_miu_bases->reg_miu_base_addr = MiuAddr>>4; ++ isp_rgbir_miu_bases->reg_miu_base_addr_1 = MiuAddr>>20; ++ //set dma upper bound ++ MiuAddr = Chip_Phys_to_MIU(Addr+size); ++ isp_rgbir_miu_bases->reg_rgbir_awb_max_addr = MiuAddr >> 4; ++ isp_rgbir_miu_bases->reg_rgbir_awb_max_addr_1 = MiuAddr >> 20; ++} ++ ++inline void HalISPSetDnrFbAddr(unsigned long Addr, int id) ++{ ++ if(Addr & 0x0F){ ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ Addr = Chip_Phys_to_MIU(Addr); ++ if(id==0) { ++ isp_miu_bases->reg_dnr_fb_base_0 = (Addr>>4) & 0xFFFF; ++ isp_miu_bases->reg_dnr_fb_base_0_1 = (Addr>>20) & 0xFFF; ++ } else if(id==1) { ++ isp_miu_bases->reg_dnr_fb_base_1 = (Addr>>4) & 0xFFFF; ++ isp_miu_bases->reg_dnr_fb_base_1_1 = (Addr>>20) & 0xFFF; ++ } ++ pr_debug("set DNR fb addr = 0x%X\n",(uint32_t)Addr); ++} ++ ++inline void HalISPSetDnrUbound(unsigned long Addr) ++{ ++ if(Addr & 0x0F) ++ { ++ pr_err("%s : Buffer address is not 16 bytes aligment.\r\n",__FUNCTION__); ++ } ++ Addr = Chip_Phys_to_MIU(Addr); ++ isp_miu_bases->reg_dnr_wdma_uaddr = (Addr>>4) & 0xFFFF; ++ isp_miu_bases->reg_dnr_wdma_uaddr_1 = (Addr>>20) & 0xFFF; ++} ++#if 1 ++inline void waitMloadDone(void) ++{ ++ int i,time_out = 1, us_count = 50000; ++ ++ for(i = 0; i < us_count; i++) { ++ if(isp_miu->reg_isp_load_done) { ++ time_out = 0; ++ break; ++ } ++ udelay(1); ++ } ++ if (time_out) { ++ pr_err("[%s] Wait %d us, TimeOut: %d, Done:%d, Status: %d, full:%d\n", __FUNCTION__, ++ us_count, time_out, ++ isp_miu->reg_isp_load_done, ++ isp_miu->reg_isp_load_start_error, ++ isp_miu->reg_isp_load_register_non_full); ++ } ++} ++ ++//Loading Data From DRAM to SRAMs ++inline void HalISPMLoadWriteData(ISP_MLOAD_ID Sram_Id, volatile unsigned long Addr, size_t size) ++{ ++ u32 k; ++ ++ Addr = Chip_Phys_to_MIU(Addr); ++ ++ //printk(KERN_INFO "[ISP] HalISPMLoadWriteData addr:0x%08x\n", (u32)Addr); ++ ++ mutex_lock(&mloadMutex); ++ //Enable the engine by turning on the register ++ isp_miu->reg_isp_miu2sram_en = 1; ++ //Set SW reset as 0 and 1 ++ isp_miu->reg_isp_load_sw_rst = 0; ++ isp_miu->reg_isp_load_sw_rst = 1; ++ isp_miu->reg_isp_load_wait_hardware_ready_en = 1; ++ isp_miu->reg_isp_load_water_level = 0; ++ ++ //Set SW read write mode as 1 (write) ++ isp_miu->reg_isp_sram_rw = 1;// 1:write ++ //Set SRAM ID ++ isp_miu->reg_isp_load_sram_id = Sram_Id; ++ //Set MIU 16-byte start address ++ isp_miu->reg_isp_load_st_addr = (Addr>>4) & 0xFFFF; ++ isp_miu->reg_isp_load_st_addr_1 = (Addr>>20) & 0xFFFF; ++ //Set data amount (2-byte) ++ //The number should be set as length - 1 ++ isp_miu->reg_isp_load_amount = size - 1; ++ //Set destination SRAM start SRAM address (2-byte) ++ isp_miu->reg_isp_sram_st_addr = 0x0000; ++ //Set SRAM loading parameter by setting write-one-clear ++ isp_miu->reg_isp_load_register_w1r = 1; ++ //write 0, HW is not working, same as dummy command ++ for(k = 0; k < 32; k++) { ++ isp_miu->reg_isp_load_register_w1r = 0; ++ } ++ //Enable the engine by turning on the register ++ //isp_miu->reg_isp_miu2sram_en = 1; ++ //Fire Loading by setting write-one-clear ++ isp_miu->reg_isp_load_st_w1r = 1; ++ ++ waitMloadDone(); ++ isp_miu->reg_isp_miu2sram_en = 0; ++ ++ ++ mutex_unlock(&mloadMutex); ++} ++ ++//Loading All table From DRAM to SRAMs ++inline void HalISPMLoadWriteAllTable(volatile unsigned long Addr) ++{ ++ u32 i,k; ++ unsigned long tbl_addr = 0; ++ ++ Addr = Chip_Phys_to_MIU(Addr); ++ ++ mutex_lock(&mloadMutex); ++ //Enable the engine by turning on the register ++ isp_miu->reg_isp_miu2sram_en = 1; ++ //Set SW reset as 0 and 1 ++ isp_miu->reg_isp_load_sw_rst = 0; //this register is active low, set 0 to reset ++ isp_miu->reg_isp_load_sw_rst = 1; ++ //Set SW read write mode as 1 (write) ++ ++ for(i = 0; i < eMLOAD_ID_NUM; i++) { ++ if(pTableSize[i]==0) ++ { ++ continue; ++ } ++ // get offset ++ tbl_addr = Addr + tblOffset[i]; ++ ++ pr_debug("MLOAD[%d] tbl_addr = %#lX \n", i, tbl_addr); ++ ++ isp_miu->reg_isp_sram_rw = 1;// 1:write ++ //Set SRAM ID ++ isp_miu->reg_isp_load_sram_id = i; ++ //Set MIU 16-byte start address ++ isp_miu->reg_isp_load_st_addr = (tbl_addr>>4) & 0xFFFF; ++ isp_miu->reg_isp_load_st_addr_1 = (tbl_addr>>20) & 0xFFFF; ++ //Set data amount (2-byte) ++ //The number should be set as length - 1 ++ isp_miu->reg_isp_load_amount = pTableSize[i] - 1; ++ //Set destination SRAM start SRAM address (2-byte) ++ isp_miu->reg_isp_sram_st_addr = 0x0000; ++ //Set SRAM loading parameter by setting write-one-clear ++ isp_miu->reg_isp_load_register_w1r = 1; ++ //write 0, HW is not working, same as dummy command ++ for(k = 0; k < 32; k++) { ++ isp_miu->reg_isp_load_register_w1r = 0; ++ } ++ } ++ ++ //Fire Loading by setting write-one-clear ++ isp_miu->reg_isp_load_st_w1r = 1; ++ ++ waitMloadDone(); ++ isp_miu->reg_isp_miu2sram_en = 0; ++ ++ mutex_unlock(&mloadMutex); ++} ++ ++//#define ISP_SENSOR_MASK ++//Read one u16 Data From SRAMs for debug ++inline void HalISPMLoadReadData(ISP_MLOAD_ID Sram_Id, volatile unsigned short *table, size_t size) ++{ ++ int i, k; ++#if defined(ISP_SENSOR_MASK) ++ volatile infinity3e_reg_isp0 *isp0 = (volatile infinity3e_reg_isp0*)RIUBASE_ISP[0]; ++#endif ++ mutex_lock(&mloadMutex); ++ ++#if defined(ISP_SENSOR_MASK) ++ // only for gamma10to10 read ++ switch (Sram_Id){ ++ case eMLOAD_ID_LN_GMA10TO10_R: ++ case eMLOAD_ID_LN_GMA10TO10_G: ++ case eMLOAD_ID_LN_GMA10TO10_B: ++ isp0->reg_isp_sensor_mask = 1; ++ break; ++ default: ++ break; ++ } ++#endif ++ ++ isp_miu->reg_isp_miu2sram_en = 1; ++ isp_miu->reg_isp_sram_rw = 0; ++ ++ for(i = 0; i < size; i++) { ++ isp_miu->reg_isp_sram_read_id = Sram_Id; ++ ++ isp_miu->reg_isp_sram_rd_addr = i; ++ isp_miu->reg_isp_sram_read_w1r = 1; ++ ++ //write 0, HW is not working, same as dummy command ++ for(k = 0; k < 32; k++) { ++ isp_miu->reg_isp_sram_read_w1r = 0; ++ } ++ ++ //Read data from register, only 16 bits data ++ table[i] = isp_miu->reg_isp_sram_read_data; ++ //pr_info("table[%d] = %#x, %p \n", i, table[i], &table[i]); ++ } ++ ++ isp_miu->reg_isp_sram_rw = 1; ++ isp_miu->reg_isp_miu2sram_en = 0; ++ ++#if defined(ISP_SENSOR_MASK) ++ if(isp0->reg_isp_sensor_mask) ++ isp0->reg_isp_sensor_mask = 0; ++#endif ++ ++ mutex_unlock(&mloadMutex); ++} ++ ++#endif ++ ++inline u8 HalISPGetFrameDoneCount(void) ++{ ++ //u16 val = *(u16*)(RIUBASE_ISP[0] + 0x7A*4); ++ //return (val >> 8) & 0x7F; ++ return pISP_INT->reg_isp_frm_done_cnt; ++} ++ ++inline void IspReset(void) ++{ ++ volatile infinity3e_reg_isp0 *isp0 = (volatile infinity3e_reg_isp0*)RIUBASE_ISP[0]; ++ u32 fifo_mask = isp0->reg_isp_sensor_mask; ++ isp0->reg_isp_sensor_mask = 1;//fifo gating ++ isp0->reg_isp_sw_rstz = 0; ++ isp0->reg_sensor_sw_rstz = 0; ++ udelay(1); ++ isp0->reg_sensor_sw_rstz = 1; ++ isp0->reg_isp_sw_rstz = 1; ++ isp0->reg_isp_sensor_mask = fifo_mask;//fifo gating ++} ++ ++inline void IspInputEnable(u32 enable) ++{ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ //isp0->reg_isp_sensor_mask = enable?0:1; ++ if(enable) ++ { ++ isp0->reg_isp_sensor_mask = 0; ++ isp0->reg_isp_icp_ack_tie1 = 0; ++ } ++ else ++ { ++ isp0->reg_isp_sensor_mask = 1; ++ isp0->reg_isp_icp_ack_tie1 = 1; ++ } ++} ++ ++inline void IspAsyncEnable(u32 enable) ++{ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ isp0->reg_isp_icp_ack_tie1 = enable?1:0; ++} ++ ++inline void HalIspSetAEDgain(u32 enable,u32 gain) ++{ ++ volatile infinity3e_reg_isp1 *isp1 = (volatile infinity3e_reg_isp1*) RIUBASE_ISP[1]; ++ isp1->reg_isp_ae_en = enable?1:0; ++ isp1->reg_isp_ae_gain = gain; ++} ++ ++typedef struct { ++ u32 val :13; //0x32 ++ u32 /* reserved */ :3; ++ u32 padding :16; ++} __attribute__((packed, aligned(1))) isp_ccm_coeff; ++ ++ ++void HalISPSetYUVCCM(const s16 *ccm_coeff) ++{ ++ int n=0; ++ volatile isp_ccm_coeff* coeff = (volatile isp_ccm_coeff*)(((char*)RIUBASE_ISP[0]) + 0x3d*4); ++ for(n=0;n<9;++n) ++ { ++ coeff[n].val = ccm_coeff[n]&0x1FFF; ++ } ++} ++ ++void HalISPGetImageSize(u32* width,u32* high) ++{ ++ *width = 1920; ++ *high = 1080; ++} ++ ++void HalISPGetAeBlkSize(u32* x,u32* y) ++{ ++ *x = 15; ++ *y = 12; ++} ++ ++u32 HalISPGetRotEn(void) ++{ ++ return 0; ++} ++ ++u32 HalISPVDOSInit(void){ ++ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ infinity3e_reg_isp6 *isp6 = (infinity3e_reg_isp6*)RIUBASE_ISP[6]; ++ ++ ++ isp0->reg_vdos_sblock_blk = 3; ++ isp0->reg_vdos_x_st = 800; ++ isp0->reg_vdos_y_st = 100; ++ isp0->reg_vdos_sblock_width = 170; ++ isp0->reg_vdos_sblock_height = 170; ++ isp0->reg_isp_icp_ack_tie1 = 0; ++ ++ isp0->reg_isp_wdma_crop_start_x = 0; ++ isp0->reg_isp_wdma_crop_start_y = 0; ++ ++ isp0->reg_isp_wdma_crop_width=1021; // 170 * 3 + 512 -1 = 1021 ++ isp0->reg_isp_wdma_crop_high=2; ++ ++ ++ isp0->reg_load_reg = 0; ++ isp0->reg_vdos_yc_en = 0; ++ isp6->reg_isp_wdma_align_en = 1; ++ ++ #if 0 ++ isp6->reg_isp_rdma_pitch = ((1021+7)>>3)*1; ++ isp6->reg_isp_wdma_pitch = ((1021+7)>>3)*1; ++ #elif 0 ++ isp6->reg_isp_rdma_pitch = (((1021+32)>>5)<<5)>>3; ++ isp6->reg_isp_wdma_pitch = (((1021+32)>>5)<<5)>>3; ++ #elif 1 ++ isp6->reg_isp_rdma_pitch = (((1021+8)>>3)<<3)>>3; ++ isp6->reg_isp_wdma_pitch = (((1021+8)>>3)<<3)>>3; ++ #endif ++ ++ isp0->reg_vdos_en =1; ++ return 0; ++} ++ ++#define LIMIT_BITS(x, bits) ((x) > ((1<<(bits))-1) ? (((1<<(bits))-1)) : (x)) ++ ++u32 HalISPWdmaTrigger(isp_ioctl_trigger_wdma_attr wdma_attr) ++{ ++ ++ int wdma_buf; ++ ++ isp0_cfg_t *isp0 = (isp0_cfg_t*)RIUBASE_ISP[0]; ++ infinity3e_reg_isp6 *isp6 = (infinity3e_reg_isp6*)RIUBASE_ISP[6]; ++ ++ ////////////////////////////////////////////////////////// Reset WDMA ++ isp6->reg_isp_wdma_en = 0; ++ isp6->reg_isp_wdma_wreq_rst = 1; ++ isp0->reg_dbgwr_swrst = 0; ++ isp6->reg_isp_wdma_wreq_rst = 0; ++ isp0->reg_dbgwr_swrst = 1; ++ /////////////////////////////////////////////////////////// ++ ++ isp6->reg_isp_rdma_en=0; ++ isp6->reg_isp_wdma_en=0; ++ ++ wdma_buf = wdma_attr.buf_addr_phy >> 4; ++ isp6->reg_isp_wdma_base = (wdma_buf & 0xffff); ++ isp6->reg_isp_wdma_base_1 = (wdma_buf >> 16) & 0x7ff; ++ ++ ++ isp0->reg_isp_wdma_crop_start_x = wdma_attr.x; ++ isp0->reg_isp_wdma_crop_start_y = wdma_attr.y; ++ isp0->reg_isp_wdma_crop_width = wdma_attr.width; ++ isp0->reg_isp_wdma_crop_high = wdma_attr.height; ++ ++ switch (wdma_attr.wdma_path) { ++ case ISP_WDMA_SIF: ++ pr_debug("--------ISP_WDMA_SIF--------\n"); ++ isp0->reg_isp_if_wmux_sel = 0; ++ isp0->reg_dspl2wdma_en = 0; ++ ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ isp6->reg_isp_wdma_pitch = ((wdma_attr.width + 7) >> 3) *1; ++ break; ++ case ISP_WDMA_ISP: ++ pr_debug("--------ISP_WDMA_ISP--------\n"); ++ isp0->reg_isp_if_wmux_sel = 1; ++ isp0->reg_dspl2wdma_en = 0; ++ ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ isp6->reg_isp_wdma_pitch = ((wdma_attr.width + 7) >> 3) *1; ++ break; ++ case ISP_WDMA_ISPDS: ++ pr_debug("--------ISP_WDMA_ISPDS--------\n"); ++ isp0->reg_isp_if_wmux_sel = 2; ++ isp0->reg_dspl2wdma_en = 1; ++ ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ isp6->reg_isp_wdma_pitch = ((wdma_attr.width + 7) >> 3) *1; ++ break; ++ case ISP_WDMA_ISPSWAPYC: ++ pr_debug("--------ISP_WDMA_ISPSWAPYC--------\n"); ++ isp0->reg_isp_if_wmux_sel = 3; ++ isp0->reg_dspl2wdma_en = 0; ++ ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ isp6->reg_isp_wdma_pitch = ((wdma_attr.width + 7) >> 3) *1; ++ break; ++ // FIXJASON ++ case ISP_WDMA_VDOS: ++ printk("--------ISP_WDMA_VDOS--------\n"); ++ HalISPVDOSInit(); ++ isp0->reg_isp_if_wmux_sel = 4; ++ isp0->reg_dspl2wdma_en = 0; ++ ++ //isp6->reg_isp_wdma_mode = 0; //PITCH_8BITS ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ ++ break; ++ case ISP_WDMA_DEFAULT_SIF: //Use ISP crop range ++ pr_debug("--------ISP_WDMA_DEFAULT_SIF--------\n"); ++ isp0->reg_isp_wdma_crop_start_x = isp0->reg_isp_crop_start_x; ++ isp0->reg_isp_wdma_crop_start_y = isp0->reg_isp_crop_start_y; ++ isp0->reg_isp_wdma_crop_width = isp0->reg_isp_crop_width; ++ isp0->reg_isp_wdma_crop_high = isp0->reg_isp_crop_high; ++ ++ isp0->reg_isp_if_wmux_sel = 0; ++ isp0->reg_dspl2wdma_en = 0; ++ ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ isp6->reg_isp_wdma_pitch = ((wdma_attr.width + 7) >> 3) *1; ++ break; ++ case ISP_WDMA_DEFAULT_YC: //Use ISP crop range ++ pr_debug("--------ISP_WDMA_DEFAULT_YC--------\n"); ++ isp0->reg_isp_wdma_crop_start_x = 0; ++ isp0->reg_isp_wdma_crop_start_y = 0; ++ isp0->reg_isp_wdma_crop_width = isp0->reg_isp_crop_width; ++ isp0->reg_isp_wdma_crop_high = isp0->reg_isp_crop_high; ++ ++ isp0->reg_isp_if_wmux_sel = 3; ++ isp0->reg_dspl2wdma_en = 0; ++ ++ isp6->reg_isp_wdma_mode = 2; //PITCH_16BITS ++ isp6->reg_isp_wdma_pitch = ((wdma_attr.width + 7) >> 3) *1; ++ break; ++ default: ++ return -1; ++ } ++ ++ ++ ++ ++ isp6->reg_isp_wdma_auto = 1; ++ ++ isp6->reg_isp_wdma_en = 1; ++ ++ ++ isp6->reg_isp_wdma_wreq_hpri_set=1; ++ isp6->reg_isp_wdma_wreq_thrd = LIMIT_BITS(0x0, 3); ++ isp6->reg_isp_wdma_wreq_hpri = LIMIT_BITS(0x1,4); ++ isp6->reg_isp_wdma_wreq_max = LIMIT_BITS(0xf, 4); ++ ++ isp6->reg_isp_wdma_trigger_mode = 1; ++ isp6->reg_isp_wdma_trigger = 1; //Trigger WDMA ++ ++ return 0; ++} ++ ++/////////////////////////////// CSI ////////////////////////////////// ++typedef struct ++{ ++ volatile csi_mac *reg; ++}hal_csi_handle; ++ ++inline void* HalCsi_Open(void* reg_base) ++{ ++ hal_csi_handle *hnd = kzalloc(sizeof(hal_csi_handle),GFP_KERNEL); ++ if(hnd) ++ hnd->reg = (csi_mac*) reg_base; ++ return (void*) hnd; ++} ++ ++inline void HalCsi_Close(void **handle) ++{ ++ kfree(*handle); ++ *handle = NULL; ++} ++ ++inline void HalCsi_RegInit(void* handle) ++{ ++ hal_csi_handle *hnd = (hal_csi_handle*)handle; ++ //enable frame start and virtual channel 0 frame end interrupt ++ hnd->reg->reg_mac_rpt_int_mask = 0x7F&(~(CSI_VC0_INT)); //enable vc0 interrupt only ++ hnd->reg->reg_rpt_fnum_cond = CSI_RPT_FS; ++ ++ //enable virtual channel 0 ++ hnd->reg->reg_lane_en = CSI_LAN0_EN | CSI_LAN1_EN; ++ hnd->reg->reg_vc_en = CSI_VC0_EN; ++ hnd->reg->reg_vc0_vs_mode = CSI_V_SYNC_MODE_FE; ++ //hnd->reg->reg_vc0_vs_mode = CSI_V_SYNC_MODE_FS; ++ ++ //CSI h-sync bug fix ++ hnd->reg->reg_vc0_hs_mode = 0x03; ++ ++ //CSI pattern gen test setting ++ hnd->reg->reg_dt_en.blinking = 0x0; ++ //hnd->reg->reg_dt_en.blinking = 0x1; ++ hnd->reg->reg_sw_rst = 0; ++ hnd->reg->reg_mac_en= 0x1; ++ hnd->reg->reg_dont_care_dt = 0x0; ++ hnd->reg->reg_mac_err_int_mask = 0x7FFF; //enable/disable csi error report interrupt ++} ++ ++inline void HalCsi_RegUninit(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ //mask all rpt interrupt ++ hnd->reg->reg_mac_rpt_int_mask = 0x7F; ++ //disable all virtual channels ++ hnd->reg->reg_vc_en = 0; ++} ++ ++inline u32 HalCsi_GetRptIntStatus(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ return hnd->reg->reg_mac_rpt_int_src; ++} ++ ++inline void HalCsi_MaskRptInt(void* handle,u32 mask) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_rpt_int_mask |= mask; ++} ++ ++//HAL , clear report interrupt ++inline void HalCsi_ClearRptInt(void* handle, u32 clear) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_rpt_int_clr |= clear; ++ hnd->reg->reg_mac_rpt_int_clr = 0; ++ hnd->reg->reg_mac_rpt_int_mask &= ~clear; ++} ++ ++inline u32 HalCsi_GetErrorIntStatus(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ return hnd->reg->reg_mac_err_int_src; ++} ++ ++inline void HalCsi_MaskErrorInt(void* handle,u32 mask) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_err_int_mask |= mask; ++} ++ ++//HAL , clear report interrupt ++inline void HalCsi_ClearErrorInt(void* handle, u32 clear) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_err_int_clr |= clear; ++ hnd->reg->reg_mac_err_int_clr = 0; ++ hnd->reg->reg_mac_err_int_mask &= ~clear; ++} ++ ++inline void HalCsi_ErrIntMaskSet(void* handle, u32 mask) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ hnd->reg->reg_mac_err_int_mask = mask & 0x7FFF; ++} ++ ++inline u32 HalCsi_ErrIntMaskGet(void* handle) ++{ ++ hal_csi_handle *hnd = (void*)handle; ++ return hnd->reg->reg_mac_err_int_mask; ++} ++ ++u8 * mloadInit(size_t mloadLayoutSize) ++{ ++ return (u8*)dma_alloc_coherent(NULL, mloadLayoutSize, &mload_dma_addr, GFP_KERNEL); ++} ++ ++void mloadDeInit(void *dmaBuf, size_t mloadLayoutSize) ++{ ++ if(mload_dma_addr) ++ dma_free_coherent(NULL, mloadLayoutSize, dmaBuf, mload_dma_addr); ++} +diff --git a/drivers/mstar/isp/infinity3/hal_isp.h b/drivers/mstar/isp/infinity3/hal_isp.h +new file mode 100644 +index 00000000..b306d13b +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/hal_isp.h +@@ -0,0 +1,243 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef __HAL_ISP_H__ ++#define __HAL_ISP_H__ ++#include "ms_platform.h" ++ ++/////////////// MIU MenuLoad /////////// ++#define GAMMA_TBL_SIZE (256) ++#define ALSC_TBL_SIZE (4209) ++#define DEFECTPIX_TBL_SIZE (512) ++#define FPN_OFFSET_TBL_SIZE (2816) ++ ++#define MLOAD_DMA_SIZE (4096*4) ++extern dma_addr_t mload_dma_addr; ++extern u8 *mload_virt_addr; ++ ++typedef enum { ++ INT_SR_VREF_RISING = 0, ++ INT_SR_VREF_FALLING = 1, ++ INT_STROBE_DONE = 2, ++ INT_DB_UPDATE_DONE = 3, ++ INT_AF_DONE = 4, ++ INT_ISP_FIFO_FULL = 5, ++ INT_ISP_BUSY = 6, ++ INT_ISP_IDLE = 7, ++ INT_AWB_DONE = 8, ++ INT_WDMA_DONE = 9, ++ INT_RDMA_DONE = 10, ++ INT_WDMA_FIFO_FULL = 11, ++ INT_PAD_VSYNC_RISING = 12, ++ INT_PAD_VSYNC_FALLING = 13, ++ INT_ISPIF_VSYNC = 14, ++ INT_AE_DONE = 15, ++ ISP_INT_MAX, ++} ISP_INT_STATUS; ++ ++typedef enum { ++ INT2_VDOS_EVERYLINE = 0, ++ INT2_VDOS_LINE0 = 1, ++ INT2_VDOS_LINE1 = 2, ++ INT2_VDOS_LINE2 = 3, ++ ISP_INT2_MAX, ++} ISP_INT2_STATUS; ++ ++typedef enum { ++ INT3_AE_WIN0_DONE = 0, ++ INT3_AE_WIN1_DONE = 1, ++ INT3_AE_BLK_ROW_INT_DONE = 2, ++ INT3_MENULOAD_DONE = 3, ++ INT3_SW_INT_INPUT_DONE = 4, ++ INT3_SW_INT_OUTPUT_DONE = 5, ++ INT3_HIT_LINE_COUNT1 = 6, ++ INT3_HIT_LINE_COUNT2 = 7, ++ INT3_HIT_LINE_COUNT3 = 8, ++ INT3_HDR_HISTO_DONE = 9, ++ INT3_RGBIR_HISTO_DONE = 10, ++ INT3_AWB_ROW_DONE = 11, ++ INT3_HISTO_ROW_DONE = 12, ++ INT3_RESERVED0 = 13, ++ INT3_RESERVED1 = 14, ++ INT3_RESERVED2 = 15, ++ ISP_INT3_MAX, ++} ISP_INT3_STATUS; ++ ++//Memnuload IQ Table ++typedef enum { ++ eMLOAD_ID_ALSC_R_TBL = 0, ++ eMLOAD_ID_ALSC_G_TBL = 1, ++ eMLOAD_ID_ALSC_B_TBL = 2, ++ ++ eMLOAD_ID_LN_GMA12TO10_R = 3, ++ eMLOAD_ID_LN_GMA12TO10_G = 4, ++ eMLOAD_ID_LN_GMA12TO10_B = 5, ++ ++ eMLOAD_ID_DP_TBL=6, ++ ++ eMLOAD_ID_LN_GMA10TO10_R = 10, ++ eMLOAD_ID_LN_GMA10TO10_G = 11, ++ eMLOAD_ID_LN_GMA10TO10_B = 12, ++ ++ eMLOAD_ID_FPN_OFFSET = 14, ++ ++ eMLOAD_ID_NUM = 15 ++ ++} ISP_MLOAD_ID; ++ ++typedef struct ++{ ++ u16 alsc_r[ALSC_TBL_SIZE] __attribute__((aligned(16))); ++ u16 alsc_g[ALSC_TBL_SIZE] __attribute__((aligned(16))); ++ u16 alsc_b[ALSC_TBL_SIZE] __attribute__((aligned(16))); ++ u16 gamma12to10_r[GAMMA_TBL_SIZE] __attribute__((aligned(16))); ++ u16 gamma12to10_g[GAMMA_TBL_SIZE] __attribute__((aligned(16))); ++ u16 gamma12to10_b[GAMMA_TBL_SIZE] __attribute__((aligned(16))); ++ u16 dpc[DEFECTPIX_TBL_SIZE] __attribute__((aligned(16))); ++ u16 gamma10to10_r[GAMMA_TBL_SIZE] __attribute__((aligned(16))); ++ u16 gamma10to10_g[GAMMA_TBL_SIZE] __attribute__((aligned(16))); ++ u16 gamma10to10_b[GAMMA_TBL_SIZE] __attribute__((aligned(16))); ++ u16 fpn[FPN_OFFSET_TBL_SIZE] __attribute__((aligned(16))); ++ char dummy[16] __attribute__((aligned(16))); ++}__attribute__((aligned(16))) MLoadLayout; ++ ++#ifndef member_size ++#define member_size(type, member) sizeof(((type *)0)->member) ++#endif ++#ifndef offsetof ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++#endif ++ ++#define VSYNC_BIT 9 ++#define MIPI_BIT 0 ++#define ISP_SHIFTBITS(a) (0x01<<(a)) ++#define ISP_CHECKBITS(a, b) ((a) & ((u32)0x01 << (b))) ++#define ISP_SETBIT(a, b) (a) |= (((u32)0x01 << (b))) ++#define ISP_CLEARBIT(a, b) (a) &= (~((u32)0x01 << (b))) ++ ++void HalInitRegs(void **pRegs); ++void HalISPMaskInt(void); ++void HalISPMaskIntAll(void); ++void HalISPClearMaskAll(void); ++void HalISPClearIntAll(void); ++void HalISPDisableInt(void); ++void HalISPEnableInt(void); ++ ++void HalISPMaskClear1(u32); ++void HalISPMaskClear2(u32); ++void HalISPMaskClear3(u32); ++ ++void HalISPClearInt(volatile u32 *clear, ISP_INT_STATUS int_num); ++ ++void HalISPMaskInt1(u32 mask); ++void HalISPMaskInt2(u32 mask); ++void HalISPMaskInt3(u32 mask); ++ ++void HalISPClearMask1(ISP_INT_STATUS int_num); ++void HalISPClearMask2(ISP_INT2_STATUS int_num); ++void HalISPClearMask3(ISP_INT3_STATUS int_num); ++ ++u32 HalISPGetIntStatus1(void); ++u32 HalISPGetIntStatus2(void); ++u32 HalISPGetIntStatus3(void); ++ ++void HalISPClkEnable(bool enable); ++u32 HalISPGetRawInt(void); ++u32 HalISPGetVsyncPol(void); ++u32 HalISPGetMIPI(void); ++ ++void HalISPGetAFStat(volatile unsigned long *Stat); ++ ++void HalISPGetVDOSPitch(volatile int *pPitch); ++void HalISPGetVDOSSize(volatile int *pSize, volatile int Pitch); ++void HalISPGetVDOSData(volatile unsigned long *pAddr, volatile int Size); ++ ++void HalISPSetAeBaseAddr(unsigned long Addr,unsigned int size); ++void HalISPSetAwbBaseAddr(unsigned long Addr,unsigned int size); ++void HalISPSetMotBaseAddr(unsigned long Addr,unsigned int size); ++void HalISPSetDnrFbAddr(unsigned long phys_addr, int id); ++void HalISPSetAfBaseAddr(unsigned long Addr,unsigned int size); ++void HalISPSetHistoBaseAddr(unsigned long Addr,unsigned int size); ++void HalISPSetRgbIRBaseAddr(unsigned long Addr,unsigned int size); ++void HalISPSetDnrUbound(unsigned long Addr); ++ ++void HalISPMLoadWriteData(ISP_MLOAD_ID Sram_Id,volatile unsigned long Addr, size_t size); ++void HalISPMLoadWriteAllTable(volatile unsigned long Addr); ++void HalISPMLoadReadData(ISP_MLOAD_ID Sram_Id, volatile unsigned short *table, size_t size); ++u8 HalISPGetFrameDoneCount(void); ++void IspReset(void); ++void IspDisable(void); ++void IspInputEnable(u32 enable); ++void IspAsyncEnable(u32 enable); ++void HalISPSetOBC(int u4OBC_a, int u4OBC_b); ++void HalIspSetAEDgain(u32 enable,u32 gain); ++void HalISPSetYUVCCM(const s16 *ccm_coff); ++void HalISPGetImageSize(u32* width,u32* height); ++void HalISPGetAeBlkSize(u32* x,u32* y); ++u32 HalISPGetRotEn(void); ++u32 HalISPWdmaTrigger(isp_ioctl_trigger_wdma_attr wdma_attr); ++u32 HalISPVDOSInit(void); ++ ++//// CSI //// ++typedef enum ++{ ++ RPT_INT_LINE = 0, ++ RPT_INT_FRAME = 1, ++ RPT_INT_VC0 = 6, ++ RPT_INT_VC1 = 5, ++ RPT_INT_VC2 = 4, ++ RPT_INT_VC4 = 3 ++}CSI_RPT_INT_STATUS; ++ ++//// CSI Error//// ++typedef enum ++{ ++ ERR_INT_DT = 0, ++ ERR_INT_PA_LENS = 1, ++ ERR_INT_PH_LENS = 2, ++ ERR_INT_ECC_ONEBIT = 3, ++ ERR_INT_FRAME_START = 4, ++ ERR_INT_FRAME_END = 5, ++ ERR_INT_ECC_TWOBIT = 6, ++ ERR_INT_CRC = 7, ++ ERR_INT_PA_WC_EQ0 = 8, ++ ERR_INT_RAW10_LENS = 9, ++ ERR_INT_CON_FE = 10, ++ ERR_INT_CON_FS = 11, ++ ERR_INT_LE = 12, ++ ERR_INT_LS = 13, ++ ERR_INT_OVERRUN = 14, ++ CSI_ERR_INT_MAX = 15, ++}CSI_ERR_INT_STATUS; ++ ++void* HalCsi_Open(void* reg_base); ++void HalCsi_Close(void **handle); ++void HalCsi_RegInit(void* handle); ++void HalCsi_RegUninit(void* handle); ++void HalCsi_ClrRptInt(void* handle); ++u32 HalCsi_GetRptIntStatus(void* handle); ++void HalCsi_MaskRptInt(void* handle,u32 mask); ++void HalCsi_ClearRptInt(void* handle, u32 clear); ++u32 HalCsi_GetErrorIntStatus(void* handle); ++void HalCsi_MaskErrorInt(void* handle,u32 mask); ++void HalCsi_ClearErrorInt(void* handle, u32 clear); ++void HalCsi_ErrIntMaskSet(void* handle,u32 mask); ++u32 HalCsi_ErrIntMaskGet(void* handle); ++u8 * mloadInit(size_t mloadLayoutSize); ++void mloadDeInit(void *dmaBuf, size_t mloadLayoutSize); ++#endif //__HAL_ISP_H__ +diff --git a/drivers/mstar/isp/infinity3/i2c.c b/drivers/mstar/isp/infinity3/i2c.c +new file mode 100644 +index 00000000..0ded34ea +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/i2c.c +@@ -0,0 +1,114 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_msys.h" ++#include "i2c.h" ++ ++ ++#define I2C_BUSY 1 ++#define I2C_IDLE 0 ++typedef struct ++{ ++ unsigned long al; ++ unsigned long ah; ++}addr64; ++i2c_handle_t* isp_i2c_init(u32 virt_reg_base) ++{ ++ i2c_handle_t* handle = (i2c_handle_t*) kzalloc(sizeof(i2c_handle_t),GFP_KERNEL); ++ handle->i2c_reg = (isp7_i2c_cfg_t*) virt_reg_base; ++ return handle; ++} ++ ++int isp_i2c_release(i2c_handle_t* handle) ++{ ++ kfree(handle); ++ return 0; ++} ++ ++ static int wait_i2c_done(i2c_handle_t* handle, int ms) ++{ ++ int status = 1, count = 0, interval = 20; // us ++ int timeout = ms/interval; ++ timeout = 625000000; // 1000ms@600MHz ++ do { ++ status = handle->i2c_reg->reg_m2s_status; ++ if (status != I2C_BUSY) ++ break; ++ count++; ++ } while (status == I2C_BUSY && count < timeout); ++ ++ if (count == timeout){ ++ pr_debug("%d: I2C Timeout!\n", ms); ++ return -1; ++ } else ++ return 0; ++} ++ ++int isp_i2c_array_tx(i2c_handle_t* handle, app_i2c_cfg* cfg, I2C_ARRAY *pdata, int ndata) { ++ unsigned short i, reg, rc, data; ++ short rw_addr = cfg->address; ++ volatile isp7_i2c_cfg_t *i2c_reg = handle->i2c_reg; ++ ++ for (i = 0; i < ndata; i++) { ++ reg = pdata[i].reg; ++ data = pdata[i].data; ++ ++ switch(cfg->fmt) { ++ default: ++ case I2C_FMT_A8D8: ++ i2c_reg->reg_sen_m2s_rw_d = data&0xff; ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = 0; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | ((reg&0xff) << 8); ++ break; ++ case I2C_FMT_A16D8: ++ i2c_reg->reg_sen_m2s_rw_d = data&0xff; ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = reg&0x00ff; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | (reg&0xff00); ++ break; ++ case I2C_FMT_A8D16: ++ i2c_reg->reg_sen_m2s_rw_d = ((data&0xff00) >> 8) | ((data&0x00ff) << 8); ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = 0; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | ((reg&0xff) << 8); ++ break; ++ case I2C_FMT_A16D16: ++ i2c_reg->reg_sen_m2s_rw_d = ((data&0xff00) >> 8) | ((data&0x00ff) << 8); ++ i2c_reg->reg_sen_m2s_2nd_reg_adr = reg&0x00ff; ++ i2c_reg->reg_sen_m2s_cmd = (rw_addr) | (reg&0xff00); ++ break; ++ ++ } ++ ++ rc = wait_i2c_done(handle, handle->timeout); ++ ++ } ++ ++ return 0; ++ ++} ++ ++int isp_i2c_request(i2c_handle_t* handle,i2c_request *req) ++{ ++ app_i2c_cfg cfg; ++ cfg.address = req->slave_addr; ++ cfg.fmt = req->fmt; ++ cfg.speed = req->speed; ++ cfg.mode = req->mode; ++ if(!isp_i2c_array_tx(handle,&cfg,req->data,req->ndata)) ++ { ++ req->status = I2C_REQ_STATUS_DONE; ++ return 0; ++ } ++ else ++ { ++ req->status = I2C_REQ_STATUS_ERROR; ++ return -1; ++ } ++} +\ No newline at end of file +diff --git a/drivers/mstar/isp/infinity3/i2c.h b/drivers/mstar/isp/infinity3/i2c.h +new file mode 100644 +index 00000000..8b550a7d +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/i2c.h +@@ -0,0 +1,135 @@ ++#ifndef _I2C_H ++#define _I2C_H ++ ++#ifndef PAD16BITS ++#define PAD16BITS u32:16 ++#endif ++ ++struct __i2c_handle_t; ++ ++typedef struct { ++ unsigned short reg; ++ unsigned short data; ++} __attribute__((packed, aligned(1))) I2C_ARRAY; ++ ++/* ++typedef enum { ++ I2C_RW_R, ++ I2C_RW_W, ++} I2C_RW; ++ ++typedef struct { ++ I2C_RW rw; ++ unsigned short reg; ++ unsigned short data; ++} __attribute__((packed, aligned(1))) I2C_CPX_ARRAY; ++*/ ++ ++typedef enum { ++ I2C_FMT_A8D8, ++ I2C_FMT_A16D8, ++ I2C_FMT_A8D16, ++ I2C_FMT_A16D16, ++ I2C_FMT_END ++} ISP_I2C_FMT; ++ ++typedef enum { ++ I2C_LEGACY_MODE, ++ I2C_NORMAL_MODE ++} ISP_I2C_MODE; ++ ++ ++typedef struct { ++ ISP_I2C_MODE mode; ++ ISP_I2C_FMT fmt; ++ u32 speed; ++ u16 address; ++ u16 reserved; ++} __attribute__((packed, aligned(1))) app_i2c_cfg; ++ ++ ///////////////////////isp i2c/////////////////////// ++typedef struct { ++ u32 reg_i2c_en :1 ; //h78 ++ u32 /* reserved */ :7; ++ u32 reg_i2c_rstz :1 ; //h78 ++ u32 /* reserved */ :7; ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_2nd_reg_adr :8 ; //h79 ++ u32 /* reserved */ :8; ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_sw_ctrl :1 ; //h7a ++ u32 reg_sen_m2s_mode :1 ; //h7a ++ u32 reg_sen_m2s_cmd_bl :1 ; //h7a ++ u32 reg_sen_m2s_reg_adr_mode :1 ; //h7a ++ u32 /* reserved */ :10; ++ u32 reg_sda_i :1 ; //h7a ++ u32 reg_m2s_status :1 ; //h7a ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_cmd :16; //h7b ++ PAD16BITS; ++ ++ u32 reg_sen_m2s_rw_d :16; //h7c ++ PAD16BITS; ++ ++ u32 reg_sen_prescale :10; //h7d ++ u32 /* reserved */ :6; ++ PAD16BITS; ++ ++ u32 reg_sen_sw_scl_oen :1 ; //h7e ++ u32 reg_sen_sw_sda_oen :1 ; //h7e ++ u32 /* reserved */ :14; ++ PAD16BITS; ++ ++ u32 reg_sen_rd :16; //h7f ++ PAD16BITS; ++} __attribute__((packed, aligned(1))) isp7_i2c_cfg_t; ++ ++#define I2C_REQ_STATUS_WAIT 0x00 ++#define I2C_REQ_STATUS_DONE 0x01 ++#define I2C_REQ_STATUS_ERROR 0x02 ++typedef struct ++{ ++ u32 tag; ++ u32 status; ++ u32 mode; ++ u32 fmt; ++ u32 speed; ++ u32 slave_addr; ++ u32 active_frame_id; //the frame number which will apply this data ++ u32 ndata; ++ I2C_ARRAY data[16]; ++}__attribute__((packed, aligned(1))) i2c_request; ++ ++typedef struct __i2c_handle_t { ++ int version; ++#if 0 ++ pi2c_setmode i2c_setmode; ++ pi2c_setfmt i2c_setfmt; ++ pi2c_setspeed i2c_setspeed; ++ pi2c_tx i2c_tx; ++ pi2c_rx i2c_rx; ++ pi2c_array_tx i2c_array_tx; ++ pi2c_array_tx2 i2c_array_tx2; ++ pi2c_array_rx i2c_array_rx; ++ pi2c_array_rx2 i2c_array_rx2; ++ pi2c_array_rw i2c_array_rw; ++ pi2c_array_rw2 i2c_array_rw2; ++ pi2c_get_status i2c_get_status; ++ pi2c_reset i2c_reset; ++ pi2c_enable i2c_enable; ++ pi2c_settimeout i2c_settimeout; ++#endif ++ int timeout; ++ volatile isp7_i2c_cfg_t *i2c_reg; ++ i2c_request req; ++ //MSYS_DMEM_INFO req_buf_info; ++} __attribute__((packed, aligned(1))) i2c_handle_t; ++ ++i2c_handle_t* isp_i2c_init(u32 virt_reg_base); ++int isp_i2c_release(i2c_handle_t* handle); ++int isp_i2c_array_tx(i2c_handle_t* handle, app_i2c_cfg* cfg, I2C_ARRAY *pdata, int ndata); ++int isp_i2c_request(i2c_handle_t* handle,i2c_request *req); ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp0.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp0.h +new file mode 100644 +index 00000000..1de30874 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp0.h +@@ -0,0 +1,2354 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP0__ ++#define __INFINITY3E_REG_ISP0__ ++typedef struct { ++ // h0000, bit: 0 ++ /* Enable ISP Engine ++ # 1’b0: Disable and Reset to the Initial State ++ # 1’b1: Enable ++ ( double buffer register )*/ ++ #define offset_of_reg_en_isp (0) ++ #define mask_of_reg_en_isp (0x1) ++ unsigned int reg_en_isp:1; ++ ++ // h0000, bit: 1 ++ /* Enable Sensor ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( double buffer register )*/ ++ #define offset_of_reg_en_sensor (0) ++ #define mask_of_reg_en_sensor (0x2) ++ unsigned int reg_en_sensor:1; ++ ++ // h0000, bit: 2 ++ /* Enable Optical Black Correction ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( double buffer register )*/ ++ #define offset_of_reg_en_isp_obc (0) ++ #define mask_of_reg_en_isp_obc (0x4) ++ unsigned int reg_en_isp_obc:1; ++ ++ // h0000, bit: 3 ++ /* Enable White Balance (before Denoise) ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( double buffer register )*/ ++ #define offset_of_reg_en_isp_wbg0 (0) ++ #define mask_of_reg_en_isp_wbg0 (0x8) ++ unsigned int reg_en_isp_wbg0:1; ++ ++ // h0000, bit: 4 ++ /* Enable White Balance (after Denoise) ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( double buffer register )*/ ++ #define offset_of_reg_en_isp_wbg1 (0) ++ #define mask_of_reg_en_isp_wbg1 (0x10) ++ unsigned int reg_en_isp_wbg1:1; ++ ++ // h0000, bit: 5 ++ /* Enable static defect pixel correction ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( double buffer register )*/ ++ #define offset_of_reg_en_isp_sdc (0) ++ #define mask_of_reg_en_isp_sdc (0x20) ++ unsigned int reg_en_isp_sdc:1; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 0 ++ /* Software Reset for ISP ++ # Low Active ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_sw_rstz (2) ++ #define mask_of_reg_isp_sw_rstz (0x1) ++ unsigned int reg_isp_sw_rstz:1; ++ ++ // h0001, bit: 1 ++ /* Software Reset for Sensor ++ # Low Active ++ ( single buffer register )*/ ++ #define offset_of_reg_sensor_sw_rstz (2) ++ #define mask_of_reg_sensor_sw_rstz (0x2) ++ unsigned int reg_sensor_sw_rstz:1; ++ ++ // h0001, bit: 2 ++ /* Power Down Sensor ++ # 1'b0: Disable ++ # 1'b1: Power Down ++ ( single buffer register ) ++ no-used*/ ++ #define offset_of_reg_sen_pwdn (2) ++ #define mask_of_reg_sen_pwdn (0x4) ++ unsigned int reg_sen_pwdn:1; ++ ++ // h0001, bit: 3 ++ /* Enable CLK_sensor delay for isp_if module ++ # 1'b0: Disable ++ # 1'b1 Enable ++ ( single buffer register )*/ ++ #define offset_of_reg_en_isp_clk_sensor_delay (2) ++ #define mask_of_reg_en_isp_clk_sensor_delay (0x8) ++ unsigned int reg_en_isp_clk_sensor_delay:1; ++ ++ // h0001, bit: 4 ++ /* Enable Lens Shading Compensation ++ # 1'b0: Disable ++ # 1'b1: Enable ++ (double buffer register )*/ ++ #define offset_of_reg_en_isp_lsc (2) ++ #define mask_of_reg_en_isp_lsc (0x10) ++ unsigned int reg_en_isp_lsc:1; ++ ++ // h0001, bit: 6 ++ /* */ ++ unsigned int :2; ++ ++ // h0001, bit: 7 ++ /* Enable Denoise ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( dobule buffer register )*/ ++ #define offset_of_reg_en_isp_denoise (2) ++ #define mask_of_reg_en_isp_denoise (0x80) ++ unsigned int reg_en_isp_denoise:1; ++ ++ // h0001, bit: 11 ++ /* */ ++ unsigned int :4; ++ ++ // h0001, bit: 12 ++ /* Enable isp2pad_sr_clk ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( single buffer register ) ++ (no-used)*/ ++ #define offset_of_reg_en_sensor_clk (2) ++ #define mask_of_reg_en_sensor_clk (0x1000) ++ unsigned int reg_en_sensor_clk:1; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0001, bit: 15 ++ /* Always Load Double Buffer Register (Type 2 ) ++ ( single buffer register )*/ ++ #define offset_of_reg_load_reg (2) ++ #define mask_of_reg_load_reg (0x8000) ++ unsigned int reg_load_reg:1; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 13 ++ /* */ ++ unsigned int :14; ++ ++ // h0002, bit: 14 ++ /* double buffer register set done at batch mode*/ ++ #define offset_of_reg_db_batch_done (4) ++ #define mask_of_reg_db_batch_done (0x4000) ++ unsigned int reg_db_batch_done:1; ++ ++ // h0002, bit: 15 ++ /* double buffer register batch mode*/ ++ #define offset_of_reg_db_batch_mode (4) ++ #define mask_of_reg_db_batch_mode (0x8000) ++ unsigned int reg_db_batch_mode:1; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 3 ++ /* [2] b3_atv_fix*/ ++ #define offset_of_reg_fire_mode (6) ++ #define mask_of_reg_fire_mode (0xf) ++ unsigned int reg_fire_mode:4; ++ ++ // h0003, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0003, bit: 8 ++ /* reset sensor 1*/ ++ #define offset_of_reg_sensor1_rst (6) ++ #define mask_of_reg_sensor1_rst (0x100) ++ unsigned int reg_sensor1_rst:1; ++ ++ // h0003, bit: 9 ++ /* power down sensor 1*/ ++ #define offset_of_reg_sensor1_pwrdn (6) ++ #define mask_of_reg_sensor1_pwrdn (0x200) ++ unsigned int reg_sensor1_pwrdn:1; ++ ++ // h0003, bit: 10 ++ /* reset sensor 2*/ ++ #define offset_of_reg_sensor2_rst (6) ++ #define mask_of_reg_sensor2_rst (0x400) ++ unsigned int reg_sensor2_rst:1; ++ ++ // h0003, bit: 11 ++ /* power down sensor 2*/ ++ #define offset_of_reg_sensor2_pwrdn (6) ++ #define mask_of_reg_sensor2_pwrdn (0x800) ++ unsigned int reg_sensor2_pwrdn:1; ++ ++ // h0003, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 0 ++ /* isp_dp source mux ++ # 1'b0: from sensor_if ++ # 1'b1: from RDMA*/ ++ #define offset_of_reg_isp_if_rmux_sel (8) ++ #define mask_of_reg_isp_if_rmux_sel (0x1) ++ unsigned int reg_isp_if_rmux_sel:1; ++ ++ // h0004, bit: 3 ++ /* */ ++ unsigned int :3; ++ ++ // h0004, bit: 6 ++ /* WDMA source mux ++ # 3'd0: from sensor_if ++ # 3'd1: from isp_dp output ++ # 3'd2: from isp_dp down-sample ++ # 3'd3: from isp_dp output ++ # 3'd4: from video stabilization ++ # 3'd7: from RGB-IR I data*/ ++ #define offset_of_reg_isp_if_wmux_sel (8) ++ #define mask_of_reg_isp_if_wmux_sel (0x70) ++ unsigned int reg_isp_if_wmux_sel:3; ++ ++ // h0004, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0004, bit: 8 ++ /* isp_dp source mux ++ # 1'b0: from rmux ++ # 1'b1: from sensor freerun vs*/ ++ #define offset_of_reg_isp_if_rvs_sel (8) ++ #define mask_of_reg_isp_if_rvs_sel (0x100) ++ unsigned int reg_isp_if_rvs_sel:1; ++ ++ // h0004, bit: 9 ++ /* ICP ack tie 1 enable*/ ++ #define offset_of_reg_isp_icp_ack_tie1 (8) ++ #define mask_of_reg_isp_icp_ack_tie1 (0x200) ++ unsigned int reg_isp_icp_ack_tie1:1; ++ ++ // h0004, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0004, bit: 15 ++ /* ISP IF status reset*/ ++ #define offset_of_reg_isp_if_state_rst (8) ++ #define mask_of_reg_isp_if_state_rst (0x8000) ++ unsigned int reg_isp_if_state_rst:1; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 0 ++ /* isp_if source mux: ++ # 1'b0: from sensor ++ # 1'b1: from csi*/ ++ #define offset_of_reg_isp_if_src_sel (10) ++ #define mask_of_reg_isp_if_src_sel (0x1) ++ unsigned int reg_isp_if_src_sel:1; ++ ++ // h0005, bit: 1 ++ /* Isp to cmdq vsync select ++ # 1'b0: DVP mode, from vsync pad ++ # 1'b1: use isp re-generate vsync*/ ++ #define offset_of_reg_isp2cmdq_vs_sel (10) ++ #define mask_of_reg_isp2cmdq_vs_sel (0x2) ++ unsigned int reg_isp2cmdq_vs_sel:1; ++ ++ // h0005, bit: 2 ++ /* reg_wdma_src_sel ++ # 1'b0: from FPN output ++ # 1'b1: from sensor*/ ++ #define offset_of_reg_wdma_src_sel (10) ++ #define mask_of_reg_wdma_src_sel (0x4) ++ unsigned int reg_wdma_src_sel:1; ++ ++ // h0005, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h0005, bit: 4 ++ /* ISP FIFO handshaking mode enable*/ ++ #define offset_of_reg_isp_if_hs_mode_en (10) ++ #define mask_of_reg_isp_if_hs_mode_en (0x10) ++ unsigned int reg_isp_if_hs_mode_en:1; ++ ++ // h0005, bit: 7 ++ /* */ ++ unsigned int :3; ++ ++ // h0005, bit: 9 ++ /* isp_dp crop virtual channel selection*/ ++ #define offset_of_reg_isp_if_dp_vc (10) ++ #define mask_of_reg_isp_if_dp_vc (0x300) ++ unsigned int reg_isp_if_dp_vc:2; ++ ++ // h0005, bit: 11 ++ /* */ ++ unsigned int :2; ++ ++ // h0005, bit: 13 ++ /* WDMA crop virtual channel selection*/ ++ #define offset_of_reg_isp_if_wdma_vc (10) ++ #define mask_of_reg_isp_if_wdma_vc (0x3000) ++ unsigned int reg_isp_if_wdma_vc:2; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 0 ++ /* Mask sensor/csi ready to ISP_IF*/ ++ #define offset_of_reg_isp_sensor_mask (14) ++ #define mask_of_reg_isp_sensor_mask (0x1) ++ unsigned int reg_isp_sensor_mask:1; ++ ++ // h0007, bit: 1 ++ /* Ready only mode*/ ++ #define offset_of_reg_isp_if_de_mode (14) ++ #define mask_of_reg_isp_if_de_mode (0x2) ++ unsigned int reg_isp_if_de_mode:1; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 0 ++ /* Enable Software Flash Strobe ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( single buffer register )*/ ++ #define offset_of_reg_en_sw_strobe (16) ++ #define mask_of_reg_en_sw_strobe (0x1) ++ unsigned int reg_en_sw_strobe:1; ++ ++ // h0008, bit: 1 ++ /* Software Strobe Setting ++ ( single buffer register )*/ ++ #define offset_of_reg_sw_strobe (16) ++ #define mask_of_reg_sw_strobe (0x2) ++ unsigned int reg_sw_strobe:1; ++ ++ // h0008, bit: 3 ++ /* */ ++ unsigned int :2; ++ ++ // h0008, bit: 4 ++ /* Strobe Polarity ++ # 1'b0: high active ++ # 1'b1: low active*/ ++ #define offset_of_reg_strobe_polarity (16) ++ #define mask_of_reg_strobe_polarity (0x10) ++ unsigned int reg_strobe_polarity:1; ++ ++ // h0008, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 14 ++ /* Start Strobe after reference strobe start (unit:256xPCLK) ++ ( single buffer register )*/ ++ #define offset_of_reg_strobe_start (18) ++ #define mask_of_reg_strobe_start (0x7fff) ++ unsigned int reg_strobe_start:15; ++ ++ // h0009, bit: 15 ++ /* Reference Start for strobe signal ++ # 1'b0 : vertical active start ++ # 1'b1 : vertical blanking start ++ ( single buffer register )*/ ++ #define offset_of_reg_strobe_ref (18) ++ #define mask_of_reg_strobe_ref (0x8000) ++ unsigned int reg_strobe_ref:1; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 14 ++ /* End Strobe after reference strobe start (unit:256xPCLK) ++ ( single buffer register )*/ ++ #define offset_of_reg_strobe_end (20) ++ #define mask_of_reg_strobe_end (0x7fff) ++ unsigned int reg_strobe_end:15; ++ ++ // h000a, bit: 15 ++ /* Enable Output Strobe Signal By Hardware Control ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( single buffer register )*/ ++ #define offset_of_reg_en_hw_strobe (20) ++ #define mask_of_reg_en_hw_strobe (0x8000) ++ unsigned int reg_en_hw_strobe:1; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 3 ++ /* Hardware Flash Strobe Counter to count sensor frame number ++ ( single buffer register )*/ ++ #define offset_of_reg_hw_strobe_cnt (22) ++ #define mask_of_reg_hw_strobe_cnt (0xf) ++ unsigned int reg_hw_strobe_cnt:4; ++ ++ // h000b, bit: 13 ++ /* */ ++ unsigned int :10; ++ ++ // h000b, bit: 14 ++ /* Reference END for Hardware Long Strobe ++ # 1'b0: vertical active start ++ # 1'b1: vertical blanking start ++ ( single buffer register )*/ ++ #define offset_of_reg_hw_long_strobe_end_ref (22) ++ #define mask_of_reg_hw_long_strobe_end_ref (0x4000) ++ unsigned int reg_hw_long_strobe_end_ref:1; ++ ++ // h000b, bit: 15 ++ /* Hardware Flash Strobe Mode ++ # 1'b0: short strobe ++ # 1'b1: long strobe (enable several frames) ++ ( single buffer register )*/ ++ #define offset_of_reg_hw_strobe_mode (22) ++ #define mask_of_reg_hw_strobe_mode (0x8000) ++ unsigned int reg_hw_strobe_mode:1; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 14 ++ /* */ ++ #define offset_of_reg_isp_bist_fail_read (26) ++ #define mask_of_reg_isp_bist_fail_read (0xffff) ++ unsigned int reg_isp_bist_fail_read:16; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 14 ++ /* */ ++ #define offset_of_reg_isp_bist_fail_read_1 (28) ++ #define mask_of_reg_isp_bist_fail_read_1 (0xffff) ++ unsigned int reg_isp_bist_fail_read_1:16; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 14 ++ /* */ ++ #define offset_of_reg_isp_bist_fail_read_2 (30) ++ #define mask_of_reg_isp_bist_fail_read_2 (0xffff) ++ unsigned int reg_isp_bist_fail_read_2:16; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 0 ++ /* Master Mode Definition between ISP and Sensor ++ # 1'b0: Sensor: clk_sensor --> ISP: clk_sensor ++ # 1'b1: ISP: clk_sensor --> Sensor: clk_sensor ++ ( single buffer register ) ++ (no-used)*/ ++ #define offset_of_reg_isp_master_mode (32) ++ #define mask_of_reg_isp_master_mode (0x1) ++ unsigned int reg_isp_master_mode:1; ++ ++ // h0010, bit: 1 ++ /* Sensor Clock Polarity ++ # 1'b0: positive edge trigger ++ # 1'b1: negative edge trigger ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_clk_sensor_polarity (32) ++ #define mask_of_reg_isp_clk_sensor_polarity (0x2) ++ unsigned int reg_isp_clk_sensor_polarity:1; ++ ++ // h0010, bit: 3 ++ /* Left shift sensor input data ++ # 2'b00 : no shift ++ # 2'b01 : shift 2bit ++ # 2'b10 : shift 4bit ++ # 2'b11 : shift 6bit*/ ++ #define offset_of_reg_isp_sensor_format_left_sht (32) ++ #define mask_of_reg_isp_sensor_format_left_sht (0xc) ++ unsigned int reg_isp_sensor_format_left_sht:2; ++ ++ // h0010, bit: 5 ++ /* Delay Unit for CLK_Sensor ++ # 2'b00: Delay 1 unit ++ # 2'b01: Delay 2 unit ++ # 2'b10: Delay 3 unit ++ # 2'b11: Delay 4 unit ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_clk_sensor_delay (32) ++ #define mask_of_reg_isp_clk_sensor_delay (0x30) ++ unsigned int reg_isp_clk_sensor_delay:2; ++ ++ // h0010, bit: 6 ++ /* */ ++ unsigned int :1; ++ ++ // h0010, bit: 7 ++ /* swap sensor input data*/ ++ #define offset_of_reg_isp_sensor_bit_swap (32) ++ #define mask_of_reg_isp_sensor_bit_swap (0x80) ++ unsigned int reg_isp_sensor_bit_swap:1; ++ ++ // h0010, bit: 8 ++ /* Sensor Hsync Polarity ++ # 1'b0: high active ++ # 1'b1: low active ++ ( single buffer register )*/ ++ #define offset_of_reg_sensor_hsync_polarity (32) ++ #define mask_of_reg_sensor_hsync_polarity (0x100) ++ unsigned int reg_sensor_hsync_polarity:1; ++ ++ // h0010, bit: 9 ++ /* Sensor Vsync Polarity ++ # 1'b0: high active ++ # 1'b1: low active ++ ( single buffer register )*/ ++ #define offset_of_reg_sensor_vsync_polarity (32) ++ #define mask_of_reg_sensor_vsync_polarity (0x200) ++ unsigned int reg_sensor_vsync_polarity:1; ++ ++ // h0010, bit: 11 ++ /* Sensor Format ++ # 2'b00: 8 bit ++ # 2'b01: 10bit ++ # 2'b10: 16bit ++ # 2'b11: 12bit*/ ++ #define offset_of_reg_isp_sensor_format (32) ++ #define mask_of_reg_isp_sensor_format (0xc00) ++ unsigned int reg_isp_sensor_format:2; ++ ++ // h0010, bit: 12 ++ /* Sensor Input Format ++ # 1'b0: YUV 422 format ++ # 1'b1: RGB pattern ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_sensor_rgb_in (32) ++ #define mask_of_reg_isp_sensor_rgb_in (0x1000) ++ unsigned int reg_isp_sensor_rgb_in:1; ++ ++ // h0010, bit: 13 ++ /* */ ++ unsigned int :1; ++ ++ // h0010, bit: 14 ++ /* Sensor 8 bit to 12 bit mode ++ # 2'b00: {[7:0], [7:4]} ++ # 2'b01: {[7:0], 4'b0} ++ # 2'b10: {[11:4], [11:8]} ++ # 2'b11: {[11:4], 4'b0} ++ Sensor 10 bit to 12 bit mode ++ # 2'b00: {[9:0], [9:8]} ++ # 2'b01: {[9:0], 2'b0} ++ # 2'b10: {[11:2], [11:10]} ++ # 2'b11: {[11:2], 2'b0}*/ ++ #define offset_of_reg_isp_sensor_format_ext_mode (32) ++ #define mask_of_reg_isp_sensor_format_ext_mode (0xc000) ++ unsigned int reg_isp_sensor_format_ext_mode:2; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 1 ++ /* RGB Raw Data Organization ++ # 2'h0: [R G R G ...; G B G B ...] ++ # 2'h1: [G R G R ...; B G B G ...] ++ # 2'h2: [B G B G ...; G R G R ...] ++ # 2'h3: [G B G B ...; R G R G ...] ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_sensor_array (34) ++ #define mask_of_reg_isp_sensor_array (0x3) ++ unsigned int reg_isp_sensor_array:2; ++ ++ // h0011, bit: 3 ++ /* */ ++ unsigned int :2; ++ ++ // h0011, bit: 4 ++ /* Sensor Input Priority as YUV input ++ # 1'b0: [ C Y C Y ...] ++ # 1'b1: [ Y C Y C ...] ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_sensor_yuv_order (34) ++ #define mask_of_reg_isp_sensor_yuv_order (0x10) ++ unsigned int reg_isp_sensor_yuv_order:1; ++ ++ // h0011, bit: 5 ++ /* */ ++ unsigned int :1; ++ ++ // h0011, bit: 6 ++ /* Sensor Input Format ++ # 1'b0: separate Y/C mode ++ # 1'b1: YC 16bit mode*/ ++ #define offset_of_reg_isp_sensor_yc16bit (34) ++ #define mask_of_reg_isp_sensor_yc16bit (0x40) ++ unsigned int reg_isp_sensor_yc16bit:1; ++ ++ // h0011, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0011, bit: 9 ++ /* Sensor vsync pulse delay ++ # 2'd0: vsync falling edge ++ # 2'd1: vsync rising edge delay 2 line ++ # 2'd2: vsync rising edge delay 1 line ++ # 2'd3: vsync rising edge*/ ++ #define offset_of_reg_isp_sensor_vs_dly (34) ++ #define mask_of_reg_isp_sensor_vs_dly (0x300) ++ unsigned int reg_isp_sensor_vs_dly:2; ++ ++ // h0011, bit: 11 ++ /* */ ++ unsigned int :2; ++ ++ // h0011, bit: 12 ++ /* Sensor hsync pulse delay ++ # 1'b0: hsync rising edge ++ # 1'b1: hsync falling edge*/ ++ #define offset_of_reg_isp_sensor_hs_dly (34) ++ #define mask_of_reg_isp_sensor_hs_dly (0x1000) ++ unsigned int reg_isp_sensor_hs_dly:1; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 11 ++ /* X Start Position for Crop Window ++ If Sensor is YUV input, this setting must be even ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_crop_start_x (36) ++ #define mask_of_reg_isp_crop_start_x (0xfff) ++ unsigned int reg_isp_crop_start_x:12; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 11 ++ /* Y Start Position for Crop Window ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_crop_start_y (38) ++ #define mask_of_reg_isp_crop_start_y (0xfff) ++ unsigned int reg_isp_crop_start_y:12; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 11 ++ /* Crop Window Width (maximum = 3264) ++ If Sensor is YUV input, this setting must be odd (0 base) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_crop_width (40) ++ #define mask_of_reg_isp_crop_width (0xfff) ++ unsigned int reg_isp_crop_width:12; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 11 ++ /* Crop Window High (maximum = 2448) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_crop_high (42) ++ #define mask_of_reg_isp_crop_high (0xfff) ++ unsigned int reg_isp_crop_high:12; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 11 ++ /* WDMA X Start Position for Crop Window ++ If Sensor is YUV input, this setting must be even ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wdma_crop_start_x (44) ++ #define mask_of_reg_isp_wdma_crop_start_x (0xfff) ++ unsigned int reg_isp_wdma_crop_start_x:12; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 11 ++ /* WDMA Y Start Position for Crop Window ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wdma_crop_start_y (46) ++ #define mask_of_reg_isp_wdma_crop_start_y (0xfff) ++ unsigned int reg_isp_wdma_crop_start_y:12; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 14 ++ /* WDMA Crop Window Width (maximum = 3264) ++ If Sensor is YUV input, this setting must be odd (0 base) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wdma_crop_width (48) ++ #define mask_of_reg_isp_wdma_crop_width (0xffff) ++ unsigned int reg_isp_wdma_crop_width:16; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 11 ++ /* WDMA Crop Window High (maximum = 2448) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wdma_crop_high (50) ++ #define mask_of_reg_isp_wdma_crop_high (0xfff) ++ unsigned int reg_isp_wdma_crop_high:12; ++ ++ // h0019, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 0 ++ /* 1'b1 : enable , rdma_width = crop_width + crop startx ++ 1'b0 : disable, rdma_width = crop_width*/ ++ #define offset_of_reg_isp_rdma_cpx_enable (52) ++ #define mask_of_reg_isp_rdma_cpx_enable (0x1) ++ unsigned int reg_isp_rdma_cpx_enable:1; ++ ++ // h001a, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 2 ++ /* RGB-IR format ++ #3'd0: R0 ++ #3'd1: G0 ++ #3'd2: B0 ++ #3'd3: G1 ++ #3'd4: G2 ++ #3'd5: I0 ++ #3'd6: G3 ++ #3'd7: I1*/ ++ #define offset_of_reg_isp_rgbir_format (54) ++ #define mask_of_reg_isp_rgbir_format (0x7) ++ unsigned int reg_isp_rgbir_format:3; ++ ++ // h001b, bit: 14 ++ /* */ ++ unsigned int :13; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* 32 bits for sw used (can't be reset)*/ ++ #define offset_of_reg_isp_sw_used (56) ++ #define mask_of_reg_isp_sw_used (0xffff) ++ unsigned int reg_isp_sw_used:16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* 32 bits for sw used (can't be reset)*/ ++ #define offset_of_reg_isp_sw_used_1 (58) ++ #define mask_of_reg_isp_sw_used_1 (0xffff) ++ unsigned int reg_isp_sw_used_1:16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 14 ++ /* isp debug out*/ ++ #define offset_of_reg_isp_debug (60) ++ #define mask_of_reg_isp_debug (0xffff) ++ unsigned int reg_isp_debug:16; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 7 ++ /* isp debug out*/ ++ #define offset_of_reg_isp_debug_1 (62) ++ #define mask_of_reg_isp_debug_1 (0xff) ++ unsigned int reg_isp_debug_1:8; ++ ++ // h001f, bit: 10 ++ /* */ ++ unsigned int :3; ++ ++ // h001f, bit: 11 ++ /* Hardware Debug Signal Sets Selector : ++ 0 : from ISP_TOP ++ 1 : from ISP_DP*/ ++ #define offset_of_reg_isp_debug_mux (62) ++ #define mask_of_reg_isp_debug_mux (0x800) ++ unsigned int reg_isp_debug_mux:1; ++ ++ // h001f, bit: 14 ++ /* Hardware Debug Signal Sets Selector*/ ++ #define offset_of_reg_isp_debug_sel (62) ++ #define mask_of_reg_isp_debug_sel (0xf000) ++ unsigned int reg_isp_debug_sel:4; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 11 ++ /* Sensor Line Counter*/ ++ #define offset_of_reg_isp_sensor_line_cnt (64) ++ #define mask_of_reg_isp_sensor_line_cnt (0xfff) ++ unsigned int reg_isp_sensor_line_cnt:12; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 0 ++ /* ISP Status*/ ++ #define offset_of_reg_isp_busy (66) ++ #define mask_of_reg_isp_busy (0x1) ++ unsigned int reg_isp_busy:1; ++ ++ // h0021, bit: 3 ++ /* */ ++ unsigned int :3; ++ ++ // h0021, bit: 4 ++ /* Sensor Input Vsync*/ ++ #define offset_of_reg_isp_sensor_vsync (66) ++ #define mask_of_reg_isp_sensor_vsync (0x10) ++ unsigned int reg_isp_sensor_vsync:1; ++ ++ // h0021, bit: 5 ++ /* Sensor Input Hsync*/ ++ #define offset_of_reg_isp_sensor_hsync (66) ++ #define mask_of_reg_isp_sensor_hsync (0x20) ++ unsigned int reg_isp_sensor_hsync:1; ++ ++ // h0021, bit: 13 ++ /* */ ++ unsigned int :8; ++ ++ // h0021, bit: 14 ++ /* Internal parallel to dma FIFO full*/ ++ #define offset_of_reg_parallel2dma_fifo_ful (66) ++ #define mask_of_reg_parallel2dma_fifo_ful (0x4000) ++ unsigned int reg_parallel2dma_fifo_ful:1; ++ ++ // h0021, bit: 15 ++ /* Internal FIFO between Sensor and ISP full*/ ++ #define offset_of_reg_isp_fifo_ful (66) ++ #define mask_of_reg_isp_fifo_ful (0x8000) ++ unsigned int reg_isp_fifo_ful:1; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 11 ++ /* */ ++ unsigned int :12; ++ ++ // h0023, bit: 12 ++ /* Polarity for isp_debug_clk ++ # 1'b0: normal ++ # 1'b1: invert clock*/ ++ #define offset_of_reg_isp_fpga_clk_polarity (70) ++ #define mask_of_reg_isp_fpga_clk_polarity (0x1000) ++ unsigned int reg_isp_fpga_clk_polarity:1; ++ ++ // h0023, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 3 ++ /* */ ++ unsigned int :4; ++ ++ // h0024, bit: 4 ++ /* Capture Enable (only for FPGA Debug Mode) ++ # 1'b0: disable ++ # 1'b1: enable*/ ++ #define offset_of_reg_capture_en (72) ++ #define mask_of_reg_capture_en (0x10) ++ unsigned int reg_capture_en:1; ++ ++ // h0024, bit: 5 ++ /* Read Data Priority for FPGA operating ++ # 1'b0: normal ++ # 1'b1: inverse*/ ++ #define offset_of_reg_fpga_read_mode (72) ++ #define mask_of_reg_fpga_read_mode (0x20) ++ unsigned int reg_fpga_read_mode:1; ++ ++ // h0024, bit: 6 ++ /* Enable dma mclk ++ # 1'b0: disable ++ # 1'b1: enable*/ ++ #define offset_of_reg_dbgsen_oen (72) ++ #define mask_of_reg_dbgsen_oen (0x40) ++ unsigned int reg_dbgsen_oen:1; ++ ++ // h0024, bit: 14 ++ /* */ ++ unsigned int :9; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* Interrupt Mask*/ ++ #define offset_of_reg_c_irq_mask (80) ++ #define mask_of_reg_c_irq_mask (0xffff) ++ unsigned int reg_c_irq_mask:16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 14 ++ /* Force Interrupt Enable*/ ++ #define offset_of_reg_c_irq_force (82) ++ #define mask_of_reg_c_irq_force (0xffff) ++ unsigned int reg_c_irq_force:16; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 14 ++ /* Interrupt Clear*/ ++ #define offset_of_reg_c_irq_clr (84) ++ #define mask_of_reg_c_irq_clr (0xffff) ++ unsigned int reg_c_irq_clr:16; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 14 ++ /* Status of Interrupt on CPU side*/ ++ #define offset_of_reg_irq_final_status (86) ++ #define mask_of_reg_irq_final_status (0xffff) ++ unsigned int reg_irq_final_status:16; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 14 ++ /* Status of Interrupt on IP side ++ # [0]: Sensor Source VREF rising edge ++ # [1]: Sensor Source VREF falling edge ++ # [2] Hardware Flash Strobe done ++ # [3] Update double buffer register done ++ # [4]: AF Statistic done ++ # [5]: ISP internal FIFO full ++ # [6]: ISP busy rising edge ++ # [7]: ISP busy falling edge ++ # [8]: AWB Statistic done ++ # [9]: WDMA done ++ # [10]: RDMA done ++ #[11]: WDMA FIFO full ++ #[12]: PAD2ISP_VSYNC rising edge ++ #[13]: PAD2ISP_VSYNC falling edge ++ #[14]: isp_if vsync pulse ++ #[15]: AE Statistic done*/ ++ #define offset_of_reg_irq_raw_status (88) ++ #define mask_of_reg_irq_raw_status (0xffff) ++ unsigned int reg_irq_raw_status:16; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 3 ++ /* New Interrupt Mask*/ ++ #define offset_of_reg_c_irq_mask2 (90) ++ #define mask_of_reg_c_irq_mask2 (0xf) ++ unsigned int reg_c_irq_mask2:4; ++ ++ // h002d, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h002d, bit: 11 ++ /* New Force Interrupt Enable*/ ++ #define offset_of_reg_c_irq_force2 (90) ++ #define mask_of_reg_c_irq_force2 (0xf00) ++ unsigned int reg_c_irq_force2:4; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 3 ++ /* New Interrupt Clear*/ ++ #define offset_of_reg_c_irq_clr2 (92) ++ #define mask_of_reg_c_irq_clr2 (0xf) ++ unsigned int reg_c_irq_clr2:4; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 3 ++ /* New Status of Interrupt on CPU side*/ ++ #define offset_of_reg_irq_final_status2 (94) ++ #define mask_of_reg_irq_final_status2 (0xf) ++ unsigned int reg_irq_final_status2:4; ++ ++ // h002f, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h002f, bit: 11 ++ /* New Status of Interrupt on IP side ++ [0] vdos every line ++ [1] vdos line #0 ++ [2] vdos line #1 ++ [3] vdos line #2*/ ++ #define offset_of_reg_irq_raw_status2 (94) ++ #define mask_of_reg_irq_raw_status2 (0xf00) ++ unsigned int reg_irq_raw_status2:4; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 2 ++ /* YUV444 to YUV422 filter mode*/ ++ #define offset_of_reg_c_filter (96) ++ #define mask_of_reg_c_filter (0x7) ++ unsigned int reg_c_filter:3; ++ ++ // h0030, bit: 3 ++ /* reg_ipm_h_mirror*/ ++ #define offset_of_reg_ipm_h_mirror (96) ++ #define mask_of_reg_ipm_h_mirror (0x8) ++ unsigned int reg_ipm_h_mirror:1; ++ ++ // h0030, bit: 4 ++ /* reg_44to42_dith_en*/ ++ #define offset_of_reg_44to42_dith_en (96) ++ #define mask_of_reg_44to42_dith_en (0x10) ++ unsigned int reg_44to42_dith_en:1; ++ ++ // h0030, bit: 5 ++ /* reg_rgb2yuv_dith_en*/ ++ #define offset_of_reg_rgb2yuv_dith_en (96) ++ #define mask_of_reg_rgb2yuv_dith_en (0x20) ++ unsigned int reg_rgb2yuv_dith_en:1; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 0 ++ /* reg_isp_r2y_cmc_en*/ ++ #define offset_of_reg_isp_r2y_cmc_en (120) ++ #define mask_of_reg_isp_r2y_cmc_en (0x1) ++ unsigned int reg_isp_r2y_cmc_en:1; ++ ++ // h003c, bit: 1 ++ /* reg_isp_r2y_y_sub_16_en*/ ++ #define offset_of_reg_isp_r2y_y_sub_16_en (120) ++ #define mask_of_reg_isp_r2y_y_sub_16_en (0x2) ++ unsigned int reg_isp_r2y_y_sub_16_en:1; ++ ++ // h003c, bit: 2 ++ /* reg_isp_r2y_r_sub_16_en*/ ++ #define offset_of_reg_isp_r2y_r_sub_16_en (120) ++ #define mask_of_reg_isp_r2y_r_sub_16_en (0x4) ++ unsigned int reg_isp_r2y_r_sub_16_en:1; ++ ++ // h003c, bit: 3 ++ /* reg_isp_r2y_b_sub_16_en*/ ++ #define offset_of_reg_isp_r2y_b_sub_16_en (120) ++ #define mask_of_reg_isp_r2y_b_sub_16_en (0x8) ++ unsigned int reg_isp_r2y_b_sub_16_en:1; ++ ++ // h003c, bit: 4 ++ /* reg_isp_r2y_y_add_16_post_en*/ ++ #define offset_of_reg_isp_r2y_y_add_16_post_en (120) ++ #define mask_of_reg_isp_r2y_y_add_16_post_en (0x10) ++ unsigned int reg_isp_r2y_y_add_16_post_en:1; ++ ++ // h003c, bit: 5 ++ /* reg_isp_r2y_r_add_16_post_en*/ ++ #define offset_of_reg_isp_r2y_r_add_16_post_en (120) ++ #define mask_of_reg_isp_r2y_r_add_16_post_en (0x20) ++ unsigned int reg_isp_r2y_r_add_16_post_en:1; ++ ++ // h003c, bit: 6 ++ /* reg_isp_r2y_b_add_16_post_en*/ ++ #define offset_of_reg_isp_r2y_b_add_16_post_en (120) ++ #define mask_of_reg_isp_r2y_b_add_16_post_en (0x40) ++ unsigned int reg_isp_r2y_b_add_16_post_en:1; ++ ++ // h003c, bit: 7 ++ /* reg_isp_r2y_cb_add_128_post_en*/ ++ #define offset_of_reg_isp_r2y_cb_add_128_post_en (120) ++ #define mask_of_reg_isp_r2y_cb_add_128_post_en (0x80) ++ unsigned int reg_isp_r2y_cb_add_128_post_en:1; ++ ++ // h003c, bit: 8 ++ /* reg_isp_r2y_cr_add_128_post_en*/ ++ #define offset_of_reg_isp_r2y_cr_add_128_post_en (120) ++ #define mask_of_reg_isp_r2y_cr_add_128_post_en (0x100) ++ unsigned int reg_isp_r2y_cr_add_128_post_en:1; ++ ++ // h003c, bit: 9 ++ /* reg_isp_r2y_rran*/ ++ #define offset_of_reg_isp_r2y_rran (120) ++ #define mask_of_reg_isp_r2y_rran (0x200) ++ unsigned int reg_isp_r2y_rran:1; ++ ++ // h003c, bit: 10 ++ /* reg_isp_r2y_gran*/ ++ #define offset_of_reg_isp_r2y_gran (120) ++ #define mask_of_reg_isp_r2y_gran (0x400) ++ unsigned int reg_isp_r2y_gran:1; ++ ++ // h003c, bit: 11 ++ /* reg_isp_r2y_bran*/ ++ #define offset_of_reg_isp_r2y_bran (120) ++ #define mask_of_reg_isp_r2y_bran (0x800) ++ unsigned int reg_isp_r2y_bran:1; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 12 ++ /* Coefficient 11 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_11 (122) ++ #define mask_of_reg_isp_r2y_coeff_11 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_11:13; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 12 ++ /* Coefficient 12 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_12 (124) ++ #define mask_of_reg_isp_r2y_coeff_12 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_12:13; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 12 ++ /* Coefficient 13 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_13 (126) ++ #define mask_of_reg_isp_r2y_coeff_13 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_13:13; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 12 ++ /* Coefficient 21 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_21 (128) ++ #define mask_of_reg_isp_r2y_coeff_21 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_21:13; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 12 ++ /* Coefficient 22 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_22 (130) ++ #define mask_of_reg_isp_r2y_coeff_22 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_22:13; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 12 ++ /* Coefficient 23 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_23 (132) ++ #define mask_of_reg_isp_r2y_coeff_23 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_23:13; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 12 ++ /* Coefficient 31 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_31 (134) ++ #define mask_of_reg_isp_r2y_coeff_31 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_31:13; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 12 ++ /* Coefficient 32 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_32 (136) ++ #define mask_of_reg_isp_r2y_coeff_32 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_32:13; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 12 ++ /* Coefficient 33 for RGB to YUV (s2.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_r2y_coeff_33 (138) ++ #define mask_of_reg_isp_r2y_coeff_33 (0x1fff) ++ unsigned int reg_isp_r2y_coeff_33:13; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 0 ++ /* Enable signal for gamma_10to10*/ ++ #define offset_of_reg_isp_gamma_10to10_en (140) ++ #define mask_of_reg_isp_gamma_10to10_en (0x1) ++ unsigned int reg_isp_gamma_10to10_en:1; ++ ++ // h0046, bit: 1 ++ /* Enable signal for gamma_10to10 gat max*/ ++ #define offset_of_reg_isp_gamma_10to10_max_en (140) ++ #define mask_of_reg_isp_gamma_10to10_max_en (0x2) ++ unsigned int reg_isp_gamma_10to10_max_en:1; ++ ++ // h0046, bit: 11 ++ /* Enable signal for gamma_10to10 max_data*/ ++ #define offset_of_reg_isp_gamma_10to10_max_data (140) ++ #define mask_of_reg_isp_gamma_10to10_max_data (0xffc) ++ unsigned int reg_isp_gamma_10to10_max_data:10; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 0 ++ /* Enable CCM keep hue function*/ ++ #define offset_of_reg_isp_cc_keep_hue_en (144) ++ #define mask_of_reg_isp_cc_keep_hue_en (0x1) ++ unsigned int reg_isp_cc_keep_hue_en:1; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 14 ++ /* CCM keep hue threshold*/ ++ #define offset_of_reg_isp_cc_hue_th (146) ++ #define mask_of_reg_isp_cc_hue_th (0xffff) ++ unsigned int reg_isp_cc_hue_th:16; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 14 ++ /* New Interrupt Mask*/ ++ #define offset_of_reg_c_irq_mask3 (148) ++ #define mask_of_reg_c_irq_mask3 (0xffff) ++ unsigned int reg_c_irq_mask3:16; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 14 ++ /* New Force Interrupt Enable*/ ++ #define offset_of_reg_c_irq_force3 (150) ++ #define mask_of_reg_c_irq_force3 (0xffff) ++ unsigned int reg_c_irq_force3:16; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 14 ++ /* New Interrupt Clear*/ ++ #define offset_of_reg_c_irq_clr3 (152) ++ #define mask_of_reg_c_irq_clr3 (0xffff) ++ unsigned int reg_c_irq_clr3:16; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 14 ++ /* New Status of Interrupt on CPU side*/ ++ #define offset_of_reg_irq_final_status3 (154) ++ #define mask_of_reg_irq_final_status3 (0xffff) ++ unsigned int reg_irq_final_status3:16; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* New Status of Interrupt on IP side ++ #[0]: Histogram window0 statistic done ++ #[1]: Histogram window1 statistic done ++ #[2]: AE block row count requal req_ae_int_row_num ++ #[3]: menuload done ++ #[4]: input line count equal reg_sw_specify_int_line ++ #[5]: output count equal reg_sw_specify_int_line ++ #[6]: hit input line count1 ++ #[7]: hit input line count2 ++ #[8]: hit input line count3 ++ #[9]: hdr histogram done ++ #[10]: rgbir histogram done ++ #[11]: awb row done ++ #[12]: histogram row done ++ #[13]: Reserved ++ #[14]: Reserved ++ #[15]: Reserved*/ ++ #define offset_of_reg_irq_raw_status3 (156) ++ #define mask_of_reg_irq_raw_status3 (0xffff) ++ unsigned int reg_irq_raw_status3:16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 0 ++ /* Gamma Correction Dither Enable*/ ++ #define offset_of_reg_gamma_c_dith_en (164) ++ #define mask_of_reg_gamma_c_dith_en (0x1) ++ unsigned int reg_gamma_c_dith_en:1; ++ ++ // h0052, bit: 14 ++ /* The 35th Gamma Table*/ ++ #define offset_of_reg_gamma_ctl_reserved (164) ++ #define mask_of_reg_gamma_ctl_reserved (0xfffe) ++ unsigned int reg_gamma_ctl_reserved:15; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 0 ++ /* */ ++ #define offset_of_reg_edge_enable (192) ++ #define mask_of_reg_edge_enable (0x1) ++ unsigned int reg_edge_enable:1; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 11 ++ /* blank space for m5x5 window engine for the last two lines*/ ++ #define offset_of_reg_blank_space (194) ++ #define mask_of_reg_blank_space (0xfff) ++ unsigned int reg_blank_space:12; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 0 ++ /* no-used*/ ++ #define offset_of_reg_rdpath_en (196) ++ #define mask_of_reg_rdpath_en (0x1) ++ unsigned int reg_rdpath_en:1; ++ ++ // h0062, bit: 1 ++ /* no-used*/ ++ #define offset_of_reg_wrpath_en (196) ++ #define mask_of_reg_wrpath_en (0x2) ++ unsigned int reg_wrpath_en:1; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* REV for m3isp*/ ++ #define offset_of_reg_reserved1_m3isp (198) ++ #define mask_of_reg_reserved1_m3isp (0xffff) ++ unsigned int reg_reserved1_m3isp:16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 0 ++ /* */ ++ unsigned int :1; ++ ++ // h0064, bit: 1 ++ /* no-used*/ ++ #define offset_of_reg_isp_dbgw_en (200) ++ #define mask_of_reg_isp_dbgw_en (0x2) ++ unsigned int reg_isp_dbgw_en:1; ++ ++ // h0064, bit: 2 ++ /* */ ++ #define offset_of_reg_isp_dp_gated_clk_en (200) ++ #define mask_of_reg_isp_dp_gated_clk_en (0x4) ++ unsigned int reg_isp_dp_gated_clk_en:1; ++ ++ // h0064, bit: 3 ++ /* denoise function*/ ++ #define offset_of_reg_m3isp_rawdn_gated_clk_en (200) ++ #define mask_of_reg_m3isp_rawdn_gated_clk_en (0x8) ++ unsigned int reg_m3isp_rawdn_gated_clk_en:1; ++ ++ // h0064, bit: 4 ++ /* no-used*/ ++ #define offset_of_reg_m3isp_kernel_gated_clk_en (200) ++ #define mask_of_reg_m3isp_kernel_gated_clk_en (0x10) ++ unsigned int reg_m3isp_kernel_gated_clk_en:1; ++ ++ // h0064, bit: 5 ++ /* no-used*/ ++ #define offset_of_reg_isp_dp_gated_clk_mode (200) ++ #define mask_of_reg_isp_dp_gated_clk_mode (0x20) ++ unsigned int reg_isp_dp_gated_clk_mode:1; ++ ++ // h0064, bit: 6 ++ /* */ ++ unsigned int :1; ++ ++ // h0064, bit: 7 ++ /* 0: vsync double buffer ++ 1: frame end double buffer*/ ++ #define offset_of_reg_latch_mode (200) ++ #define mask_of_reg_latch_mode (0x80) ++ unsigned int reg_latch_mode:1; ++ ++ // h0064, bit: 8 ++ /* */ ++ #define offset_of_reg_sensor_hsync (200) ++ #define mask_of_reg_sensor_hsync (0x100) ++ unsigned int reg_sensor_hsync:1; ++ ++ // h0064, bit: 9 ++ /* */ ++ #define offset_of_reg_sensor_vsync (200) ++ #define mask_of_reg_sensor_vsync (0x200) ++ unsigned int reg_sensor_vsync:1; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 0 ++ /* no-used*/ ++ #define offset_of_reg_rdpath_swrst (202) ++ #define mask_of_reg_rdpath_swrst (0x1) ++ unsigned int reg_rdpath_swrst:1; ++ ++ // h0065, bit: 1 ++ /* no-used*/ ++ #define offset_of_reg_wrpath_swrst (202) ++ #define mask_of_reg_wrpath_swrst (0x2) ++ unsigned int reg_wrpath_swrst:1; ++ ++ // h0065, bit: 2 ++ /* wdma/rdma sw reset*/ ++ #define offset_of_reg_dbgwr_swrst (202) ++ #define mask_of_reg_dbgwr_swrst (0x4) ++ unsigned int reg_dbgwr_swrst:1; ++ ++ // h0065, bit: 3 ++ /* Mask mload rst when sw rst enable ++ 0 : no mask (default) ++ 1 : mask*/ ++ #define offset_of_reg_mask_mload_mif_rst (202) ++ #define mask_of_reg_mask_mload_mif_rst (0x8) ++ unsigned int reg_mask_mload_mif_rst:1; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 0 ++ /* 0: isp_dp reset by vsync ++ 1: isp_dp not reset by vsync*/ ++ #define offset_of_reg_isp_dp_rstz_mode (204) ++ #define mask_of_reg_isp_dp_rstz_mode (0x1) ++ unsigned int reg_isp_dp_rstz_mode:1; ++ ++ // h0066, bit: 1 ++ /* rawdn_clk force disable*/ ++ #define offset_of_reg_m3isp_rawdn_clk_force_dis (204) ++ #define mask_of_reg_m3isp_rawdn_clk_force_dis (0x2) ++ unsigned int reg_m3isp_rawdn_clk_force_dis:1; ++ ++ // h0066, bit: 2 ++ /* isp_dp_clk force disable*/ ++ #define offset_of_reg_isp_dp_clk_force_dis (204) ++ #define mask_of_reg_isp_dp_clk_force_dis (0x4) ++ unsigned int reg_isp_dp_clk_force_dis:1; ++ ++ // h0066, bit: 3 ++ /* Raw data down sample to DMA enable ++ (double buffer register)*/ ++ #define offset_of_reg_dspl2wdma_en (204) ++ #define mask_of_reg_dspl2wdma_en (0x8) ++ unsigned int reg_dspl2wdma_en:1; ++ ++ // h0066, bit: 6 ++ /* down-sampling mode ++ 0 : whole image ++ 1 : 1/4 ++ 2 : 1/16 ++ 3 : 1/64 ++ 4 : 1/256*/ ++ #define offset_of_reg_dsp_mode (204) ++ #define mask_of_reg_dsp_mode (0x70) ++ unsigned int reg_dsp_mode:3; ++ ++ // h0066, bit: 7 ++ /* 0: Enable isp2icp frame end reset ++ 1: Disable*/ ++ #define offset_of_reg_fend_rstz_mode (204) ++ #define mask_of_reg_fend_rstz_mode (0x80) ++ unsigned int reg_fend_rstz_mode:1; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 3 ++ /* hsync pipe delay for YC mode(atv mode)*/ ++ #define offset_of_reg_hs_pipe (208) ++ #define mask_of_reg_hs_pipe (0xf) ++ unsigned int reg_hs_pipe:4; ++ ++ // h0068, bit: 4 ++ /* Mask hsync pipe delay for YC mode(atv mode)*/ ++ #define offset_of_reg_s2p_hs_mask (208) ++ #define mask_of_reg_s2p_hs_mask (0x10) ++ unsigned int reg_s2p_hs_mask:1; ++ ++ // h0068, bit: 5 ++ /* hsync pipe delay polarity for YC mode ++ # 1'b0: high active ++ # 1'b1: low active*/ ++ #define offset_of_reg_s2p_hs_pol (208) ++ #define mask_of_reg_s2p_hs_pol (0x20) ++ unsigned int reg_s2p_hs_pol:1; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 0 ++ /* Video stabilization enable*/ ++ #define offset_of_reg_vdos_en (212) ++ #define mask_of_reg_vdos_en (0x1) ++ unsigned int reg_vdos_en:1; ++ ++ // h006a, bit: 1 ++ /* Video stabilization mode: ++ 0: bayer mode ++ 1: yc mode*/ ++ #define offset_of_reg_vdos_yc_en (212) ++ #define mask_of_reg_vdos_yc_en (0x2) ++ unsigned int reg_vdos_yc_en:1; ++ ++ // h006a, bit: 3 ++ /* */ ++ unsigned int :2; ++ ++ // h006a, bit: 4 ++ /* Video stabilization Y/G first flag ++ 0: first pix is NOT Y/G ++ 1: first pix is Y/G*/ ++ #define offset_of_reg_vdos_byer_mode (212) ++ #define mask_of_reg_vdos_byer_mode (0x10) ++ unsigned int reg_vdos_byer_mode:1; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 2 ++ /* Number of blanking lines for sram dump*/ ++ #define offset_of_reg_vdos_sblock_blk (214) ++ #define mask_of_reg_vdos_sblock_blk (0x7) ++ unsigned int reg_vdos_sblock_blk:3; ++ ++ // h006b, bit: 7 ++ /* */ ++ unsigned int :5; ++ ++ // h006b, bit: 14 ++ /* */ ++ #define offset_of_reg_vdos_dummy (214) ++ #define mask_of_reg_vdos_dummy (0xff00) ++ unsigned int reg_vdos_dummy:8; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 12 ++ /* Video stabilization X crop start, > 0*/ ++ #define offset_of_reg_vdos_x_st (216) ++ #define mask_of_reg_vdos_x_st (0x1fff) ++ unsigned int reg_vdos_x_st:13; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 11 ++ /* Video stabilization Y crop start, > 0*/ ++ #define offset_of_reg_vdos_y_st (218) ++ #define mask_of_reg_vdos_y_st (0xfff) ++ unsigned int reg_vdos_y_st:12; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 11 ++ /* Video stabilization sub block width*/ ++ #define offset_of_reg_vdos_sblock_width (220) ++ #define mask_of_reg_vdos_sblock_width (0xfff) ++ unsigned int reg_vdos_sblock_width:12; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 11 ++ /* Video stabilization sub block height*/ ++ #define offset_of_reg_vdos_sblock_height (222) ++ #define mask_of_reg_vdos_sblock_height (0xfff) ++ unsigned int reg_vdos_sblock_height:12; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 0 ++ /* Enable CFA Interpolation (Demosaic) ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( single buffer register )*/ ++ #define offset_of_reg_cfai_en (224) ++ #define mask_of_reg_cfai_en (0x1) ++ unsigned int reg_cfai_en:1; ++ ++ // h0070, bit: 1 ++ /* Enable CFAI Data Bypass (output = m33) ++ # 1'b0: Disable ++ # 1'b1: Enable ++ ( single buffer register )*/ ++ #define offset_of_reg_cfai_bypass (224) ++ #define mask_of_reg_cfai_bypass (0x2) ++ unsigned int reg_cfai_bypass:1; ++ ++ // h0070, bit: 2 ++ /* demosaic noise reduction average g enable ++ 0: disable ++ 1: enable (use average g for blending)*/ ++ #define offset_of_reg_cfai_dnr_gavg_ref_en (224) ++ #define mask_of_reg_cfai_dnr_gavg_ref_en (0x4) ++ unsigned int reg_cfai_dnr_gavg_ref_en:1; ++ ++ // h0070, bit: 3 ++ /* emosaic noise reduction enable ++ 0: disable ++ 1: enable */ ++ #define offset_of_reg_cfai_dnr_en (224) ++ #define mask_of_reg_cfai_dnr_en (0x8) ++ unsigned int reg_cfai_dnr_en:1; ++ ++ // h0070, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0070, bit: 10 ++ /* demosaic noise reduction rb channel blending ratio*/ ++ #define offset_of_reg_cfai_dnr_rb_ratio (224) ++ #define mask_of_reg_cfai_dnr_rb_ratio (0x700) ++ unsigned int reg_cfai_dnr_rb_ratio:3; ++ ++ // h0070, bit: 11 ++ /* */ ++ unsigned int :1; ++ ++ // h0070, bit: 14 ++ /* demosaic noise reduction g channel blending ratio*/ ++ #define offset_of_reg_cfai_dnr_g_ratio (224) ++ #define mask_of_reg_cfai_dnr_g_ratio (0x7000) ++ unsigned int reg_cfai_dnr_g_ratio:3; ++ ++ // h0070, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 3 ++ /* Demosaic DVH Edge Wieghting Adjust Slope ++ (u4)*/ ++ #define offset_of_reg_demosaic_dvh_slope (226) ++ #define mask_of_reg_demosaic_dvh_slope (0xf) ++ unsigned int reg_demosaic_dvh_slope:4; ++ ++ // h0071, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0071, bit: 11 ++ /* Demosaic DVH Edge Wieghting Threshold ++ (u4)*/ ++ #define offset_of_reg_demosaic_dvh_thrd (226) ++ #define mask_of_reg_demosaic_dvh_thrd (0xf00) ++ unsigned int reg_demosaic_dvh_thrd:4; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 3 ++ /* Demosaic Complex Region Wieghting Adjust Slope ++ (u0.4)*/ ++ #define offset_of_reg_demosaic_cpxwei_slope (228) ++ #define mask_of_reg_demosaic_cpxwei_slope (0xf) ++ unsigned int reg_demosaic_cpxwei_slope:4; ++ ++ // h0072, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0072, bit: 14 ++ /* Demosaic Complex Region Wieghting Threshold ++ (u8)*/ ++ #define offset_of_reg_demosaic_cpxwei_thrd (228) ++ #define mask_of_reg_demosaic_cpxwei_thrd (0xff00) ++ unsigned int reg_demosaic_cpxwei_thrd:8; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 3 ++ /* Neighbor Check Slope M (u2.2) ++ for reduce the false color on high freq. horizontal / vertical line with width 1*/ ++ #define offset_of_reg_nb_slope_m (230) ++ #define mask_of_reg_nb_slope_m (0xf) ++ unsigned int reg_nb_slope_m:4; ++ ++ // h0073, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0073, bit: 11 ++ /* Neighbor Check Slope S (u3.1) ++ for reduce the false color on high freq. horizontal / vertical line with width 1*/ ++ #define offset_of_reg_nb_slope_s (230) ++ #define mask_of_reg_nb_slope_s (0xf00) ++ unsigned int reg_nb_slope_s:4; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 0 ++ /* False color suppression enable ++ 0: disable ++ 1: enable */ ++ #define offset_of_reg_rgb_falsecolor_en (232) ++ #define mask_of_reg_rgb_falsecolor_en (0x1) ++ unsigned int reg_rgb_falsecolor_en:1; ++ ++ // h0074, bit: 1 ++ /* minmax rounding enable*/ ++ #define offset_of_reg_rgb_falsecolor_minmax_round (232) ++ #define mask_of_reg_rgb_falsecolor_minmax_round (0x2) ++ unsigned int reg_rgb_falsecolor_minmax_round:1; ++ ++ // h0074, bit: 3 ++ /* */ ++ unsigned int :2; ++ ++ // h0074, bit: 6 ++ /* blending ratio*/ ++ #define offset_of_reg_rgb_falsecolor_color_ratio (232) ++ #define mask_of_reg_rgb_falsecolor_color_ratio (0x70) ++ unsigned int reg_rgb_falsecolor_color_ratio:3; ++ ++ // h0074, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0074, bit: 10 ++ /* blending ratio*/ ++ #define offset_of_reg_rgb_falsecolor_r_ratio (232) ++ #define mask_of_reg_rgb_falsecolor_r_ratio (0x700) ++ unsigned int reg_rgb_falsecolor_r_ratio:3; ++ ++ // h0074, bit: 11 ++ /* */ ++ unsigned int :1; ++ ++ // h0074, bit: 14 ++ /* blending ratio*/ ++ #define offset_of_reg_rgb_falsecolor_b_ratio (232) ++ #define mask_of_reg_rgb_falsecolor_b_ratio (0x7000) ++ unsigned int reg_rgb_falsecolor_b_ratio:3; ++ ++ // h0074, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 6 ++ /* isp frame start count (vsync)*/ ++ #define offset_of_reg_isp_frm_init_cnt (244) ++ #define mask_of_reg_isp_frm_init_cnt (0x7f) ++ unsigned int reg_isp_frm_init_cnt:7; ++ ++ // h007a, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h007a, bit: 14 ++ /* isp frame done count*/ ++ #define offset_of_reg_isp_frm_done_cnt (244) ++ #define mask_of_reg_isp_frm_done_cnt (0x7f00) ++ unsigned int reg_isp_frm_done_cnt:7; ++ ++ // h007a, bit: 15 ++ /* Clear isp frame init/done count*/ ++ #define offset_of_reg_isp_clr_frm_cnt (244) ++ #define mask_of_reg_isp_clr_frm_cnt (0x8000) ++ unsigned int reg_isp_clr_frm_cnt:1; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 11 ++ /* input HSYNC count*/ ++ #define offset_of_reg_input_hs_cnt (246) ++ #define mask_of_reg_input_hs_cnt (0xfff) ++ unsigned int reg_input_hs_cnt:12; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 11 ++ /* input DE count*/ ++ #define offset_of_reg_input_de_cnt (248) ++ #define mask_of_reg_input_de_cnt (0xfff) ++ unsigned int reg_input_de_cnt:12; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 11 ++ /* SW specify interrupt line number*/ ++ #define offset_of_reg_sw_specify_int_line (252) ++ #define mask_of_reg_sw_specify_int_line (0xfff) ++ unsigned int reg_sw_specify_int_line:12; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 7 ++ /* debug status*/ ++ #define offset_of_reg_debug_status_out (254) ++ #define mask_of_reg_debug_status_out (0xff) ++ unsigned int reg_debug_status_out:8; ++ ++ // h007f, bit: 14 ++ /* clear debug status*/ ++ #define offset_of_reg_debug_status_clr (254) ++ #define mask_of_reg_debug_status_clr (0xff00) ++ unsigned int reg_debug_status_clr:8; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp0; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp1.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp1.h +new file mode 100644 +index 00000000..149232b4 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp1.h +@@ -0,0 +1,2170 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP1__ ++#define __INFINITY3E_REG_ISP1__ ++typedef struct { ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 11 ++ /* X Center Position for Lens Shading Compensation ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_lsc_center_x (2) ++ #define mask_of_reg_isp_lsc_center_x (0xfff) ++ unsigned int reg_isp_lsc_center_x:12; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 11 ++ /* Y Center Position for Lens Shading Compensation ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_lsc_center_y (4) ++ #define mask_of_reg_isp_lsc_center_y (0xfff) ++ unsigned int reg_isp_lsc_center_y:12; ++ ++ // h0002, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 4 ++ /* Shift Factor for Lens Shading Compensation ++ # 4'b0000: No shift ++ # 4'b0001: Shift Right 1 bit ++ # 4'b0010: Shift Right 2 bit ++ # 4'b0011: Shift Right 3 bit ++ # 4'b0100: Shift Right 4 bit ++ # 4'b0101: Shift Right 5 bit ++ # 4'b0110: Shift Right 6 bit ++ # 4'b0111: Shift Right 7 bit ++ # 4'b1000: Shift Right 8 bit ++ # 4'b1001: Shift Right 9 bit ++ # 4'b1010: Shift Right 10 bit ++ # 4'b1011: Shift Right 11 bit ++ # 4'b1100: Shift Right 12 bit ++ # 4'b1101: Shift Right 13 bit ++ # 4'b1110: Shift Right 14 bit ++ # 4'b1111: Shift Right 15 bit ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_shift (6) ++ #define mask_of_reg_isp_lsc_shift (0x1f) ++ unsigned int reg_isp_lsc_shift:5; ++ ++ // h0003, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 0 ++ /* obc dither enable*/ ++ #define offset_of_reg_obc_dith_en (8) ++ #define mask_of_reg_obc_dith_en (0x1) ++ unsigned int reg_obc_dith_en:1; ++ ++ // h0004, bit: 1 ++ /* lsc dither enable*/ ++ #define offset_of_reg_lsc_dith_en (8) ++ #define mask_of_reg_lsc_dith_en (0x2) ++ unsigned int reg_lsc_dith_en:1; ++ ++ // h0004, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 9 ++ /* Enable 12-bits to 10-bits Gamma at bayer domain*/ ++ #define offset_of_reg_gm12to10_max_data (12) ++ #define mask_of_reg_gm12to10_max_data (0x3ff) ++ unsigned int reg_gm12to10_max_data:10; ++ ++ // h0006, bit: 11 ++ /* */ ++ unsigned int :2; ++ ++ // h0006, bit: 12 ++ /* Enable 12-bits to 10-bits Gamma at bayer domain*/ ++ #define offset_of_reg_gm12to10_en (12) ++ #define mask_of_reg_gm12to10_en (0x1000) ++ unsigned int reg_gm12to10_en:1; ++ ++ // h0006, bit: 13 ++ /* Enable 12-bits to 10-bits Gamma at bayer domain*/ ++ #define offset_of_reg_gm12to10_max_en (12) ++ #define mask_of_reg_gm12to10_max_en (0x2000) ++ unsigned int reg_gm12to10_max_en:1; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 0 ++ /* White Balance Gain Dither Enable*/ ++ #define offset_of_reg_wbg_dith_en (14) ++ #define mask_of_reg_wbg_dith_en (0x1) ++ unsigned int reg_wbg_dith_en:1; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 12 ++ /* White Balance Gain for R channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_r_gain (16) ++ #define mask_of_reg_isp_wbg_r_gain (0x1fff) ++ unsigned int reg_isp_wbg_r_gain:13; ++ ++ // h0008, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 10 ++ /* White Balance Offset for R channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_r_offset (18) ++ #define mask_of_reg_isp_wbg_r_offset (0x7ff) ++ unsigned int reg_isp_wbg_r_offset:11; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 12 ++ /* White Balance Gain for Gr channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_gr_gain (20) ++ #define mask_of_reg_isp_wbg_gr_gain (0x1fff) ++ unsigned int reg_isp_wbg_gr_gain:13; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 10 ++ /* White Balance Offset for Gr channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_gr_offset (22) ++ #define mask_of_reg_isp_wbg_gr_offset (0x7ff) ++ unsigned int reg_isp_wbg_gr_offset:11; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 12 ++ /* White Balance Gain for B channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_b_gain (24) ++ #define mask_of_reg_isp_wbg_b_gain (0x1fff) ++ unsigned int reg_isp_wbg_b_gain:13; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 10 ++ /* White Balance Offset for B channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_b_offset (26) ++ #define mask_of_reg_isp_wbg_b_offset (0x7ff) ++ unsigned int reg_isp_wbg_b_offset:11; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 12 ++ /* White Balance Gain for Gb channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_gb_gain (28) ++ #define mask_of_reg_isp_wbg_gb_gain (0x1fff) ++ unsigned int reg_isp_wbg_gb_gain:13; ++ ++ // h000e, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 10 ++ /* White Balance Offset for Gb channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg_gb_offset (30) ++ #define mask_of_reg_isp_wbg_gb_offset (0x7ff) ++ unsigned int reg_isp_wbg_gb_offset:11; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 7 ++ /* Gain Table 0 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_0 (32) ++ #define mask_of_reg_isp_lsc_r_gain_table_0 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_0:8; ++ ++ // h0010, bit: 14 ++ /* Gain Table 1 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_1 (32) ++ #define mask_of_reg_isp_lsc_r_gain_table_1 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_1:8; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 7 ++ /* Gain Table 2 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_2 (34) ++ #define mask_of_reg_isp_lsc_r_gain_table_2 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_2:8; ++ ++ // h0011, bit: 14 ++ /* Gain Table 3 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_3 (34) ++ #define mask_of_reg_isp_lsc_r_gain_table_3 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_3:8; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 7 ++ /* Gain Table 4 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_4 (36) ++ #define mask_of_reg_isp_lsc_r_gain_table_4 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_4:8; ++ ++ // h0012, bit: 14 ++ /* Gain Table 5 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_5 (36) ++ #define mask_of_reg_isp_lsc_r_gain_table_5 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_5:8; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 7 ++ /* Gain Table 6 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_6 (38) ++ #define mask_of_reg_isp_lsc_r_gain_table_6 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_6:8; ++ ++ // h0013, bit: 14 ++ /* Gain Table 7 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_7 (38) ++ #define mask_of_reg_isp_lsc_r_gain_table_7 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_7:8; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 7 ++ /* Gain Table 8 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_8 (40) ++ #define mask_of_reg_isp_lsc_r_gain_table_8 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_8:8; ++ ++ // h0014, bit: 14 ++ /* Gain Table 9 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_9 (40) ++ #define mask_of_reg_isp_lsc_r_gain_table_9 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_9:8; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 7 ++ /* Gain Table 10 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_10 (42) ++ #define mask_of_reg_isp_lsc_r_gain_table_10 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_10:8; ++ ++ // h0015, bit: 14 ++ /* Gain Table 11 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_11 (42) ++ #define mask_of_reg_isp_lsc_r_gain_table_11 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_11:8; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 7 ++ /* Gain Table 12 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:0] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_12 (44) ++ #define mask_of_reg_isp_lsc_r_gain_table_12 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_12:8; ++ ++ // h0016, bit: 14 ++ /* Gain Table 13 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_13 (44) ++ #define mask_of_reg_isp_lsc_r_gain_table_13 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_13:8; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 7 ++ /* Gain Table 14 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_14 (46) ++ #define mask_of_reg_isp_lsc_r_gain_table_14 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_14:8; ++ ++ // h0017, bit: 14 ++ /* Gain Table 15 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_15 (46) ++ #define mask_of_reg_isp_lsc_r_gain_table_15 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_15:8; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 7 ++ /* Gain Table 16 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_16 (48) ++ #define mask_of_reg_isp_lsc_r_gain_table_16 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_16:8; ++ ++ // h0018, bit: 14 ++ /* Gain Table 17 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_17 (48) ++ #define mask_of_reg_isp_lsc_r_gain_table_17 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_17:8; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 7 ++ /* Gain Table 18 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_18 (50) ++ #define mask_of_reg_isp_lsc_r_gain_table_18 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_18:8; ++ ++ // h0019, bit: 14 ++ /* Gain Table 19 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_19 (50) ++ #define mask_of_reg_isp_lsc_r_gain_table_19 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_19:8; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 7 ++ /* Gain Table 20 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_20 (52) ++ #define mask_of_reg_isp_lsc_r_gain_table_20 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_20:8; ++ ++ // h001a, bit: 14 ++ /* Gain Table 21 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_21 (52) ++ #define mask_of_reg_isp_lsc_r_gain_table_21 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_21:8; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 7 ++ /* Gain Table 22 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_22 (54) ++ #define mask_of_reg_isp_lsc_r_gain_table_22 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_22:8; ++ ++ // h001b, bit: 14 ++ /* Gain Table 23 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_23 (54) ++ #define mask_of_reg_isp_lsc_r_gain_table_23 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_23:8; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 7 ++ /* Gain Table 24 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_24 (56) ++ #define mask_of_reg_isp_lsc_r_gain_table_24 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_24:8; ++ ++ // h001c, bit: 14 ++ /* Gain Table 25 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_25 (56) ++ #define mask_of_reg_isp_lsc_r_gain_table_25 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_25:8; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 7 ++ /* Gain Table 26 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_26 (58) ++ #define mask_of_reg_isp_lsc_r_gain_table_26 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_26:8; ++ ++ // h001d, bit: 14 ++ /* Gain Table 27 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_27 (58) ++ #define mask_of_reg_isp_lsc_r_gain_table_27 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_27:8; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 7 ++ /* Gain Table 28 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_28 (60) ++ #define mask_of_reg_isp_lsc_r_gain_table_28 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_28:8; ++ ++ // h001e, bit: 14 ++ /* Gain Table 29 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_29 (60) ++ #define mask_of_reg_isp_lsc_r_gain_table_29 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_29:8; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 7 ++ /* Gain Table 30 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_30 (62) ++ #define mask_of_reg_isp_lsc_r_gain_table_30 (0xff) ++ unsigned int reg_isp_lsc_r_gain_table_30:8; ++ ++ // h001f, bit: 14 ++ /* Gain Table 31 for R Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_r_gain_table_31 (62) ++ #define mask_of_reg_isp_lsc_r_gain_table_31 (0xff00) ++ unsigned int reg_isp_lsc_r_gain_table_31:8; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 7 ++ /* Gain Table 0 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_0 (64) ++ #define mask_of_reg_isp_lsc_g_gain_table_0 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_0:8; ++ ++ // h0020, bit: 14 ++ /* Gain Table 1 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_1 (64) ++ #define mask_of_reg_isp_lsc_g_gain_table_1 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_1:8; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 7 ++ /* Gain Table 2 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_2 (66) ++ #define mask_of_reg_isp_lsc_g_gain_table_2 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_2:8; ++ ++ // h0021, bit: 14 ++ /* Gain Table 3 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_3 (66) ++ #define mask_of_reg_isp_lsc_g_gain_table_3 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_3:8; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 7 ++ /* Gain Table 4 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_4 (68) ++ #define mask_of_reg_isp_lsc_g_gain_table_4 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_4:8; ++ ++ // h0022, bit: 14 ++ /* Gain Table 5 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_5 (68) ++ #define mask_of_reg_isp_lsc_g_gain_table_5 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_5:8; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 7 ++ /* Gain Table 6 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_6 (70) ++ #define mask_of_reg_isp_lsc_g_gain_table_6 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_6:8; ++ ++ // h0023, bit: 14 ++ /* Gain Table 7 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_7 (70) ++ #define mask_of_reg_isp_lsc_g_gain_table_7 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_7:8; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 7 ++ /* Gain Table 8 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_8 (72) ++ #define mask_of_reg_isp_lsc_g_gain_table_8 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_8:8; ++ ++ // h0024, bit: 14 ++ /* Gain Table 9 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_9 (72) ++ #define mask_of_reg_isp_lsc_g_gain_table_9 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_9:8; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 7 ++ /* Gain Table 10 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_10 (74) ++ #define mask_of_reg_isp_lsc_g_gain_table_10 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_10:8; ++ ++ // h0025, bit: 14 ++ /* Gain Table 11 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_11 (74) ++ #define mask_of_reg_isp_lsc_g_gain_table_11 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_11:8; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 7 ++ /* Gain Table 12 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_12 (76) ++ #define mask_of_reg_isp_lsc_g_gain_table_12 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_12:8; ++ ++ // h0026, bit: 14 ++ /* Gain Table 13 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_13 (76) ++ #define mask_of_reg_isp_lsc_g_gain_table_13 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_13:8; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 7 ++ /* Gain Table 14 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_14 (78) ++ #define mask_of_reg_isp_lsc_g_gain_table_14 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_14:8; ++ ++ // h0027, bit: 14 ++ /* Gain Table 15 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_15 (78) ++ #define mask_of_reg_isp_lsc_g_gain_table_15 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_15:8; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 7 ++ /* Gain Table 16 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_16 (80) ++ #define mask_of_reg_isp_lsc_g_gain_table_16 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_16:8; ++ ++ // h0028, bit: 14 ++ /* Gain Table 17 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_17 (80) ++ #define mask_of_reg_isp_lsc_g_gain_table_17 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_17:8; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 7 ++ /* Gain Table 18 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_18 (82) ++ #define mask_of_reg_isp_lsc_g_gain_table_18 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_18:8; ++ ++ // h0029, bit: 14 ++ /* Gain Table 19 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_19 (82) ++ #define mask_of_reg_isp_lsc_g_gain_table_19 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_19:8; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 7 ++ /* Gain Table 20 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_20 (84) ++ #define mask_of_reg_isp_lsc_g_gain_table_20 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_20:8; ++ ++ // h002a, bit: 14 ++ /* Gain Table 21 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_21 (84) ++ #define mask_of_reg_isp_lsc_g_gain_table_21 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_21:8; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 7 ++ /* Gain Table 22 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_22 (86) ++ #define mask_of_reg_isp_lsc_g_gain_table_22 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_22:8; ++ ++ // h002b, bit: 14 ++ /* Gain Table 23 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_23 (86) ++ #define mask_of_reg_isp_lsc_g_gain_table_23 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_23:8; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 7 ++ /* Gain Table 24 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_24 (88) ++ #define mask_of_reg_isp_lsc_g_gain_table_24 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_24:8; ++ ++ // h002c, bit: 14 ++ /* Gain Table 25 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_25 (88) ++ #define mask_of_reg_isp_lsc_g_gain_table_25 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_25:8; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 7 ++ /* Gain Table 26 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_26 (90) ++ #define mask_of_reg_isp_lsc_g_gain_table_26 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_26:8; ++ ++ // h002d, bit: 14 ++ /* Gain Table 27 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_27 (90) ++ #define mask_of_reg_isp_lsc_g_gain_table_27 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_27:8; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 7 ++ /* Gain Table 28 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_28 (92) ++ #define mask_of_reg_isp_lsc_g_gain_table_28 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_28:8; ++ ++ // h002e, bit: 14 ++ /* Gain Table 29 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_29 (92) ++ #define mask_of_reg_isp_lsc_g_gain_table_29 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_29:8; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 7 ++ /* Gain Table 30 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_30 (94) ++ #define mask_of_reg_isp_lsc_g_gain_table_30 (0xff) ++ unsigned int reg_isp_lsc_g_gain_table_30:8; ++ ++ // h002f, bit: 14 ++ /* Gain Table 31 for G Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_g_gain_table_31 (94) ++ #define mask_of_reg_isp_lsc_g_gain_table_31 (0xff00) ++ unsigned int reg_isp_lsc_g_gain_table_31:8; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 7 ++ /* Gain Table 0 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_0 (96) ++ #define mask_of_reg_isp_lsc_b_gain_table_0 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_0:8; ++ ++ // h0030, bit: 14 ++ /* Gain Table 1 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_1 (96) ++ #define mask_of_reg_isp_lsc_b_gain_table_1 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_1:8; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 7 ++ /* Gain Table 2 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_2 (98) ++ #define mask_of_reg_isp_lsc_b_gain_table_2 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_2:8; ++ ++ // h0031, bit: 14 ++ /* Gain Table 3 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_3 (98) ++ #define mask_of_reg_isp_lsc_b_gain_table_3 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_3:8; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 7 ++ /* Gain Table 4 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_4 (100) ++ #define mask_of_reg_isp_lsc_b_gain_table_4 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_4:8; ++ ++ // h0032, bit: 14 ++ /* Gain Table 5 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_5 (100) ++ #define mask_of_reg_isp_lsc_b_gain_table_5 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_5:8; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 7 ++ /* Gain Table 6 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_6 (102) ++ #define mask_of_reg_isp_lsc_b_gain_table_6 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_6:8; ++ ++ // h0033, bit: 14 ++ /* Gain Table 7 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_7 (102) ++ #define mask_of_reg_isp_lsc_b_gain_table_7 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_7:8; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 7 ++ /* Gain Table 8 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_8 (104) ++ #define mask_of_reg_isp_lsc_b_gain_table_8 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_8:8; ++ ++ // h0034, bit: 14 ++ /* Gain Table 9 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_9 (104) ++ #define mask_of_reg_isp_lsc_b_gain_table_9 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_9:8; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 7 ++ /* Gain Table 10 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_10 (106) ++ #define mask_of_reg_isp_lsc_b_gain_table_10 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_10:8; ++ ++ // h0035, bit: 14 ++ /* Gain Table 11 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_11 (106) ++ #define mask_of_reg_isp_lsc_b_gain_table_11 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_11:8; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 7 ++ /* Gain Table 12 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_12 (108) ++ #define mask_of_reg_isp_lsc_b_gain_table_12 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_12:8; ++ ++ // h0036, bit: 14 ++ /* Gain Table 13 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_13 (108) ++ #define mask_of_reg_isp_lsc_b_gain_table_13 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_13:8; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 7 ++ /* Gain Table 14 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_14 (110) ++ #define mask_of_reg_isp_lsc_b_gain_table_14 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_14:8; ++ ++ // h0037, bit: 14 ++ /* Gain Table 15 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_15 (110) ++ #define mask_of_reg_isp_lsc_b_gain_table_15 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_15:8; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 7 ++ /* Gain Table 16 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_16 (112) ++ #define mask_of_reg_isp_lsc_b_gain_table_16 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_16:8; ++ ++ // h0038, bit: 14 ++ /* Gain Table 17 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_17 (112) ++ #define mask_of_reg_isp_lsc_b_gain_table_17 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_17:8; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 7 ++ /* Gain Table 18 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_18 (114) ++ #define mask_of_reg_isp_lsc_b_gain_table_18 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_18:8; ++ ++ // h0039, bit: 14 ++ /* Gain Table 19 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_19 (114) ++ #define mask_of_reg_isp_lsc_b_gain_table_19 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_19:8; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 7 ++ /* Gain Table 20 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_20 (116) ++ #define mask_of_reg_isp_lsc_b_gain_table_20 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_20:8; ++ ++ // h003a, bit: 14 ++ /* Gain Table 21 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_21 (116) ++ #define mask_of_reg_isp_lsc_b_gain_table_21 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_21:8; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 7 ++ /* Gain Table 22 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_22 (118) ++ #define mask_of_reg_isp_lsc_b_gain_table_22 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_22:8; ++ ++ // h003b, bit: 14 ++ /* Gain Table 23 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_23 (118) ++ #define mask_of_reg_isp_lsc_b_gain_table_23 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_23:8; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 7 ++ /* Gain Table 24 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_24 (120) ++ #define mask_of_reg_isp_lsc_b_gain_table_24 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_24:8; ++ ++ // h003c, bit: 14 ++ /* Gain Table 25 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_25 (120) ++ #define mask_of_reg_isp_lsc_b_gain_table_25 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_25:8; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 7 ++ /* Gain Table 26 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_26 (122) ++ #define mask_of_reg_isp_lsc_b_gain_table_26 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_26:8; ++ ++ // h003d, bit: 14 ++ /* Gain Table 27 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_27 (122) ++ #define mask_of_reg_isp_lsc_b_gain_table_27 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_27:8; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 7 ++ /* Gain Table 28 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_28 (124) ++ #define mask_of_reg_isp_lsc_b_gain_table_28 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_28:8; ++ ++ // h003e, bit: 14 ++ /* Gain Table 29 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_29 (124) ++ #define mask_of_reg_isp_lsc_b_gain_table_29 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_29:8; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 7 ++ /* Gain Table 30 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_30 (126) ++ #define mask_of_reg_isp_lsc_b_gain_table_30 (0xff) ++ unsigned int reg_isp_lsc_b_gain_table_30:8; ++ ++ // h003f, bit: 14 ++ /* Gain Table 31 for B Lens Shading Compensation ++ # [7:0] Interval Gain Base, (.8) ++ # [15:8] Interval Gain Slop (.8) ++ ( single buffer register )*/ ++ #define offset_of_reg_isp_lsc_b_gain_table_31 (126) ++ #define mask_of_reg_isp_lsc_b_gain_table_31 (0xff00) ++ unsigned int reg_isp_lsc_b_gain_table_31:8; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 0 ++ /* 1'b1 : Enable Green Equalization 1'b0 : disable (default)*/ ++ #define offset_of_reg_isp_geq_enable (128) ++ #define mask_of_reg_isp_geq_enable (0x1) ++ unsigned int reg_isp_geq_enable:1; ++ ++ // h0040, bit: 3 ++ /* */ ++ unsigned int :3; ++ ++ // h0040, bit: 13 ++ /* Green Equalization threshold*/ ++ #define offset_of_reg_isp_geq_th (128) ++ #define mask_of_reg_isp_geq_th (0x3ff0) ++ unsigned int reg_isp_geq_th:10; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 9 ++ /* Green Equalization statistic threshold*/ ++ #define offset_of_reg_isp_geq_th_stat (130) ++ #define mask_of_reg_isp_geq_th_stat (0x3ff) ++ unsigned int reg_isp_geq_th_stat:10; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 14 ++ /* Green Equalization statistic max count*/ ++ #define offset_of_reg_o_isp_geq_max_count (132) ++ #define mask_of_reg_o_isp_geq_max_count (0xffff) ++ unsigned int reg_o_isp_geq_max_count:16; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 3 ++ /* Green Equalization statistic max group*/ ++ #define offset_of_reg_o_isp_geq_max_group (134) ++ #define mask_of_reg_o_isp_geq_max_group (0xf) ++ unsigned int reg_o_isp_geq_max_group:4; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 2 ++ /* Green Equalization absolute value shift (abs shift)*/ ++ #define offset_of_reg_isp_geq_abs_shift (136) ++ #define mask_of_reg_isp_geq_abs_shift (0x7) ++ unsigned int reg_isp_geq_abs_shift:3; ++ ++ // h0044, bit: 7 ++ /* */ ++ unsigned int :5; ++ ++ // h0044, bit: 10 ++ /* Green Equalization absolute value shift2 (abs shift)*/ ++ #define offset_of_reg_isp_geq_abs_shift2 (136) ++ #define mask_of_reg_isp_geq_abs_shift2 (0x700) ++ unsigned int reg_isp_geq_abs_shift2:3; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 9 ++ /* Green Equalization threshold2*/ ++ #define offset_of_reg_isp_geq_th2 (138) ++ #define mask_of_reg_isp_geq_th2 (0x3ff) ++ unsigned int reg_isp_geq_th2:10; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 9 ++ /* Green Equalization threshold max value*/ ++ #define offset_of_reg_isp_geq_th_max (140) ++ #define mask_of_reg_isp_geq_th_max (0x3ff) ++ unsigned int reg_isp_geq_th_max:10; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 0 ++ /* 1'b1 : Enable Crosstalk 1'b0 : disable (default)*/ ++ #define offset_of_reg_ci_anti_ct_en (142) ++ #define mask_of_reg_ci_anti_ct_en (0x1) ++ unsigned int reg_ci_anti_ct_en:1; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 7 ++ /* Crosstalk threshold*/ ++ #define offset_of_reg_ci_anti_ct_th (144) ++ #define mask_of_reg_ci_anti_ct_th (0xff) ++ unsigned int reg_ci_anti_ct_th:8; ++ ++ // h0048, bit: 14 ++ /* Crosstalk absolute value shift (abs shift)*/ ++ #define offset_of_reg_ci_anti_ct_sft (144) ++ #define mask_of_reg_ci_anti_ct_sft (0xff00) ++ unsigned int reg_ci_anti_ct_sft:8; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 0 ++ /* 1'b1 : Enable Green Equalization 1'b0 : disable (default)*/ ++ #define offset_of_reg_isp_snr_geq_enable (146) ++ #define mask_of_reg_isp_snr_geq_enable (0x1) ++ unsigned int reg_isp_snr_geq_enable:1; ++ ++ // h0049, bit: 2 ++ /* Green Equalization absolute value shift (abs shift)*/ ++ #define offset_of_reg_isp_snr_geq_abs_shift (146) ++ #define mask_of_reg_isp_snr_geq_abs_shift (0x6) ++ unsigned int reg_isp_snr_geq_abs_shift:2; ++ ++ // h0049, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h0049, bit: 11 ++ /* Green Equalization threshold*/ ++ #define offset_of_reg_isp_snr_geq_th (146) ++ #define mask_of_reg_isp_snr_geq_th (0xff0) ++ unsigned int reg_isp_snr_geq_th:8; ++ ++ // h0049, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 7 ++ /* Green Equalization statistic threshold*/ ++ #define offset_of_reg_isp_snr_geq_th_stat (148) ++ #define mask_of_reg_isp_snr_geq_th_stat (0xff) ++ unsigned int reg_isp_snr_geq_th_stat:8; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 14 ++ /* Green Equalization statistic max count*/ ++ #define offset_of_reg_o_isp_snr_geq_max_count (150) ++ #define mask_of_reg_o_isp_snr_geq_max_count (0xffff) ++ unsigned int reg_o_isp_snr_geq_max_count:16; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 3 ++ /* Green Equalization statistic max group*/ ++ #define offset_of_reg_o_isp_snr_geq_max_group (152) ++ #define mask_of_reg_o_isp_snr_geq_max_group (0xf) ++ unsigned int reg_o_isp_snr_geq_max_group:4; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 7 ++ /* SNR active threshold (R pixel)*/ ++ #define offset_of_reg_snr_std_low_thrd_r_pix (160) ++ #define mask_of_reg_snr_std_low_thrd_r_pix (0xff) ++ unsigned int reg_snr_std_low_thrd_r_pix:8; ++ ++ // h0050, bit: 14 ++ /* SNR active threshold (B pixel)*/ ++ #define offset_of_reg_snr_std_low_thrd_b_pix (160) ++ #define mask_of_reg_snr_std_low_thrd_b_pix (0xff00) ++ unsigned int reg_snr_std_low_thrd_b_pix:8; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 3 ++ /* SNR strength F2 (R pixel)*/ ++ #define offset_of_reg_snr_strength_gain_r_pix (162) ++ #define mask_of_reg_snr_strength_gain_r_pix (0xf) ++ unsigned int reg_snr_strength_gain_r_pix:4; ++ ++ // h0051, bit: 4 ++ /* */ ++ unsigned int :1; ++ ++ // h0051, bit: 7 ++ /* SNR alpha step (R pixel)*/ ++ #define offset_of_reg_snr_alpha_step_r_pix (162) ++ #define mask_of_reg_snr_alpha_step_r_pix (0xe0) ++ unsigned int reg_snr_alpha_step_r_pix:3; ++ ++ // h0051, bit: 11 ++ /* SNR strength F2 (B pixel)*/ ++ #define offset_of_reg_snr_strength_gain_b_pix (162) ++ #define mask_of_reg_snr_strength_gain_b_pix (0xf00) ++ unsigned int reg_snr_strength_gain_b_pix:4; ++ ++ // h0051, bit: 12 ++ /* */ ++ unsigned int :1; ++ ++ // h0051, bit: 14 ++ /* SNR alpha step (B pixel)*/ ++ #define offset_of_reg_snr_alpha_step_b_pix (162) ++ #define mask_of_reg_snr_alpha_step_b_pix (0xe000) ++ unsigned int reg_snr_alpha_step_b_pix:3; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 14 ++ /* SNR Alpha LUT (R pixel)*/ ++ #define offset_of_reg_snr_table_r_pix (164) ++ #define mask_of_reg_snr_table_r_pix (0xffff) ++ unsigned int reg_snr_table_r_pix:16; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* SNR Alpha LUT (R pixel)*/ ++ #define offset_of_reg_snr_table_r_pix_1 (166) ++ #define mask_of_reg_snr_table_r_pix_1 (0xffff) ++ unsigned int reg_snr_table_r_pix_1:16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* SNR Alpha LUT (R pixel)*/ ++ #define offset_of_reg_snr_table_r_pix_2 (168) ++ #define mask_of_reg_snr_table_r_pix_2 (0xffff) ++ unsigned int reg_snr_table_r_pix_2:16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* SNR Alpha LUT (R pixel)*/ ++ #define offset_of_reg_snr_table_r_pix_3 (170) ++ #define mask_of_reg_snr_table_r_pix_3 (0xffff) ++ unsigned int reg_snr_table_r_pix_3:16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* SNR Alpha LUT (B pixel)*/ ++ #define offset_of_reg_snr_table_b_pix (172) ++ #define mask_of_reg_snr_table_b_pix (0xffff) ++ unsigned int reg_snr_table_b_pix:16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* SNR Alpha LUT (B pixel)*/ ++ #define offset_of_reg_snr_table_b_pix_1 (174) ++ #define mask_of_reg_snr_table_b_pix_1 (0xffff) ++ unsigned int reg_snr_table_b_pix_1:16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* SNR Alpha LUT (B pixel)*/ ++ #define offset_of_reg_snr_table_b_pix_2 (176) ++ #define mask_of_reg_snr_table_b_pix_2 (0xffff) ++ unsigned int reg_snr_table_b_pix_2:16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* SNR Alpha LUT (B pixel)*/ ++ #define offset_of_reg_snr_table_b_pix_3 (178) ++ #define mask_of_reg_snr_table_b_pix_3 (0xffff) ++ unsigned int reg_snr_table_b_pix_3:16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 5 ++ /* Noise masking gain F2 (R pixel)*/ ++ #define offset_of_reg_snr_nm_gain_r_pix (192) ++ #define mask_of_reg_snr_nm_gain_r_pix (0x3f) ++ unsigned int reg_snr_nm_gain_r_pix:6; ++ ++ // h0060, bit: 7 ++ /* */ ++ unsigned int :2; ++ ++ // h0060, bit: 13 ++ /* Noise masking gain F2 (B pixel)*/ ++ #define offset_of_reg_snr_nm_gain_b_pix (192) ++ #define mask_of_reg_snr_nm_gain_b_pix (0x3f00) ++ unsigned int reg_snr_nm_gain_b_pix:6; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 3 ++ /* Noise masking max threshold bound (R pixel)*/ ++ #define offset_of_reg_snr_nm_max_thrd_r_pix (194) ++ #define mask_of_reg_snr_nm_max_thrd_r_pix (0xf) ++ unsigned int reg_snr_nm_max_thrd_r_pix:4; ++ ++ // h0061, bit: 7 ++ /* Noise masking min threshold bound (R pixel)*/ ++ #define offset_of_reg_snr_nm_min_thrd_r_pix (194) ++ #define mask_of_reg_snr_nm_min_thrd_r_pix (0xf0) ++ unsigned int reg_snr_nm_min_thrd_r_pix:4; ++ ++ // h0061, bit: 11 ++ /* Noise masking max threshold bound (B pixel)*/ ++ #define offset_of_reg_snr_nm_max_thrd_b_pix (194) ++ #define mask_of_reg_snr_nm_max_thrd_b_pix (0xf00) ++ unsigned int reg_snr_nm_max_thrd_b_pix:4; ++ ++ // h0061, bit: 14 ++ /* Noise masking min threshold bound (B pixel)*/ ++ #define offset_of_reg_snr_nm_min_thrd_b_pix (194) ++ #define mask_of_reg_snr_nm_min_thrd_b_pix (0xf000) ++ unsigned int reg_snr_nm_min_thrd_b_pix:4; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 11 ++ /* obc line cnt number1 for interrupt*/ ++ #define offset_of_reg_isp_obc_line_cnt1 (200) ++ #define mask_of_reg_isp_obc_line_cnt1 (0xfff) ++ unsigned int reg_isp_obc_line_cnt1:12; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 11 ++ /* obc line cnt number2 for interrupt*/ ++ #define offset_of_reg_isp_obc_line_cnt2 (202) ++ #define mask_of_reg_isp_obc_line_cnt2 (0xfff) ++ unsigned int reg_isp_obc_line_cnt2:12; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 11 ++ /* obc line cnt number3 for interrupt*/ ++ #define offset_of_reg_isp_obc_line_cnt3 (204) ++ #define mask_of_reg_isp_obc_line_cnt3 (0xfff) ++ unsigned int reg_isp_obc_line_cnt3:12; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 7 ++ /* Shift Base for Optical Black Correction ++ input pixel is R, ++ formula: Cout = (Cin – reg_isp_obc_r_ofst) * b ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_r_ofst (206) ++ #define mask_of_reg_isp_obc_r_ofst (0xff) ++ unsigned int reg_isp_obc_r_ofst:8; ++ ++ // h0067, bit: 14 ++ /* Shift Base for Optical Black Correction ++ input pixel is GR, ++ formula: Cout = (Cin – reg_isp_obc_gr_ofst) * b ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_gr_ofst (206) ++ #define mask_of_reg_isp_obc_gr_ofst (0xff00) ++ unsigned int reg_isp_obc_gr_ofst:8; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 7 ++ /* Global Gain Table for Lens Shading Compensation ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_lsc_glb_gain (208) ++ #define mask_of_reg_isp_lsc_glb_gain (0xff) ++ unsigned int reg_isp_lsc_glb_gain:8; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 7 ++ /* Shift Base for Optical Black Correction ++ input pixel is GB, ++ formula: Cout = (Cin – reg_isp_obc_gb_ofst) * b ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_gb_ofst (210) ++ #define mask_of_reg_isp_obc_gb_ofst (0xff) ++ unsigned int reg_isp_obc_gb_ofst:8; ++ ++ // h0069, bit: 14 ++ /* Shift Base for Optical Black Correction ++ input pixel is B, ++ formula: Cout = (Cin – reg_isp_obc_b_ofst) * b ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_b_ofst (210) ++ #define mask_of_reg_isp_obc_b_ofst (0xff00) ++ unsigned int reg_isp_obc_b_ofst:8; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 13 ++ /* Shift Gain for Optical Black Correction ++ formula: Cout = (Cin – ofst) * b ++ input pixel is R, ++ b = reg_isp_obc_r_gain ++ precision 4.10 ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_r_gain (212) ++ #define mask_of_reg_isp_obc_r_gain (0x3fff) ++ unsigned int reg_isp_obc_r_gain:14; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 13 ++ /* Shift Gain for Optical Black Correction ++ formula: Cout = (Cin – ofst) * b ++ input pixel is GR, ++ b = reg_isp_obc_gr_gain ++ precision 4.10 ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_gr_gain (214) ++ #define mask_of_reg_isp_obc_gr_gain (0x3fff) ++ unsigned int reg_isp_obc_gr_gain:14; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 13 ++ /* Shift Gain for Optical Black Correction ++ formula: Cout = (Cin – ofst) * b ++ input pixel is GB, ++ b = reg_isp_obc_gb_gain ++ precision 4.10 ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_gb_gain (216) ++ #define mask_of_reg_isp_obc_gb_gain (0x3fff) ++ unsigned int reg_isp_obc_gb_gain:14; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 13 ++ /* Shift Gain for Optical Black Correction ++ formula: Cout = (Cin – ofst) * b ++ input pixel is b, ++ b = reg_isp_obc_b_gain ++ precision 4.10 ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_obc_b_gain (218) ++ #define mask_of_reg_isp_obc_b_gain (0x3fff) ++ unsigned int reg_isp_obc_b_gain:14; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 0 ++ /* 1'b1: Enable AE gain ++ 1'b0: Disable(default)*/ ++ #define offset_of_reg_isp_ae_en (220) ++ #define mask_of_reg_isp_ae_en (0x1) ++ unsigned int reg_isp_ae_en:1; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 13 ++ /* AE gain ++ out = in * reg_isp_ae_gain ++ precision 4.10 ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_ae_gain (222) ++ #define mask_of_reg_isp_ae_gain (0x3fff) ++ unsigned int reg_isp_ae_gain:14; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 0 ++ /* SNR enable F2*/ ++ #define offset_of_reg_snr_en (224) ++ #define mask_of_reg_snr_en (0x1) ++ unsigned int reg_snr_en:1; ++ ++ // h0070, bit: 1 ++ /* mean filter R/G/B use separate param enable ++ 0: disable ++ 1: enable */ ++ #define offset_of_reg_mean_rgb_sep_en (224) ++ #define mask_of_reg_mean_rgb_sep_en (0x2) ++ unsigned int reg_mean_rgb_sep_en:1; ++ ++ // h0070, bit: 2 ++ /* noise masking R/G/B use separate param enable ++ 0: disable ++ 1: enable */ ++ #define offset_of_reg_nm_rgb_sep_en (224) ++ #define mask_of_reg_nm_rgb_sep_en (0x4) ++ unsigned int reg_nm_rgb_sep_en:1; ++ ++ // h0070, bit: 7 ++ /* */ ++ unsigned int :5; ++ ++ // h0070, bit: 14 ++ /* SNR active threshold*/ ++ #define offset_of_reg_snr_std_low_thrd (224) ++ #define mask_of_reg_snr_std_low_thrd (0xff00) ++ unsigned int reg_snr_std_low_thrd:8; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 3 ++ /* SNR strength F2*/ ++ #define offset_of_reg_snr_strength_gain (226) ++ #define mask_of_reg_snr_strength_gain (0xf) ++ unsigned int reg_snr_strength_gain:4; ++ ++ // h0071, bit: 4 ++ /* */ ++ unsigned int :1; ++ ++ // h0071, bit: 7 ++ /* SNR alpha step*/ ++ #define offset_of_reg_snr_alpha_step (226) ++ #define mask_of_reg_snr_alpha_step (0xe0) ++ unsigned int reg_snr_alpha_step:3; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* SNR Alpha LUT*/ ++ #define offset_of_reg_snr_table (228) ++ #define mask_of_reg_snr_table (0xffff) ++ unsigned int reg_snr_table:16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* SNR Alpha LUT*/ ++ #define offset_of_reg_snr_table_1 (230) ++ #define mask_of_reg_snr_table_1 (0xffff) ++ unsigned int reg_snr_table_1:16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* SNR Alpha LUT*/ ++ #define offset_of_reg_snr_table_2 (232) ++ #define mask_of_reg_snr_table_2 (0xffff) ++ unsigned int reg_snr_table_2:16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* SNR Alpha LUT*/ ++ #define offset_of_reg_snr_table_3 (234) ++ #define mask_of_reg_snr_table_3 (0xffff) ++ unsigned int reg_snr_table_3:16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 0 ++ /* Noise masking enable F2*/ ++ #define offset_of_reg_snr_nm_filter_en (236) ++ #define mask_of_reg_snr_nm_filter_en (0x1) ++ unsigned int reg_snr_nm_filter_en:1; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 5 ++ /* Noise masking gain F2*/ ++ #define offset_of_reg_snr_nm_gain (238) ++ #define mask_of_reg_snr_nm_gain (0x3f) ++ unsigned int reg_snr_nm_gain:6; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 3 ++ /* Noise masking max threshold bound*/ ++ #define offset_of_reg_snr_nm_max_thrd (240) ++ #define mask_of_reg_snr_nm_max_thrd (0xf) ++ unsigned int reg_snr_nm_max_thrd:4; ++ ++ // h0078, bit: 7 ++ /* Noise masking min threshold bound*/ ++ #define offset_of_reg_snr_nm_min_thrd (240) ++ #define mask_of_reg_snr_nm_min_thrd (0xf0) ++ unsigned int reg_snr_nm_min_thrd:4; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 0 ++ /* Spike NR Enable F2.*/ ++ #define offset_of_reg_spike_nr_en (242) ++ #define mask_of_reg_spike_nr_en (0x1) ++ unsigned int reg_spike_nr_en:1; ++ ++ // h0079, bit: 7 ++ /* */ ++ unsigned int :7; ++ ++ // h0079, bit: 11 ++ /* Spike NR Coefficient.*/ ++ #define offset_of_reg_spike_nr_coef (242) ++ #define mask_of_reg_spike_nr_coef (0xf00) ++ unsigned int reg_spike_nr_coef:4; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 7 ++ /* Spike NR P threshold 0.*/ ++ #define offset_of_reg_p_thrd (244) ++ #define mask_of_reg_p_thrd (0xff) ++ unsigned int reg_p_thrd:8; ++ ++ // h007a, bit: 12 ++ /* Spike NR P threshold 1.*/ ++ #define offset_of_reg_p_thrd_1 (244) ++ #define mask_of_reg_p_thrd_1 (0x1f00) ++ unsigned int reg_p_thrd_1:5; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 7 ++ /* Spike NR P threshold 2.*/ ++ #define offset_of_reg_p_thrd_2 (246) ++ #define mask_of_reg_p_thrd_2 (0xff) ++ unsigned int reg_p_thrd_2:8; ++ ++ // h007b, bit: 14 ++ /* Spike NR P threshold 3.*/ ++ #define offset_of_reg_p_thrd_3 (246) ++ #define mask_of_reg_p_thrd_3 (0xff00) ++ unsigned int reg_p_thrd_3:8; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 2 ++ /* Spike NR D11_21 Step.*/ ++ #define offset_of_reg_d_11_21_step (248) ++ #define mask_of_reg_d_11_21_step (0x7) ++ unsigned int reg_d_11_21_step:3; ++ ++ // h007c, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h007c, bit: 6 ++ /* Spike NR D31 Step.*/ ++ #define offset_of_reg_d_31_step (248) ++ #define mask_of_reg_d_31_step (0x70) ++ unsigned int reg_d_31_step:3; ++ ++ // h007c, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h007c, bit: 10 ++ /* Spike NR YP22 Step.*/ ++ #define offset_of_reg_yp_22_step (248) ++ #define mask_of_reg_yp_22_step (0x700) ++ unsigned int reg_yp_22_step:3; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp1; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp2.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp2.h +new file mode 100644 +index 00000000..3c0cddcd +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp2.h +@@ -0,0 +1,1762 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP2__ ++#define __INFINITY3E_REG_ISP2__ ++typedef struct { ++ // h0000, bit: 0 ++ /* DPC enable*/ ++ #define offset_of_reg_dpc_en (0) ++ #define mask_of_reg_dpc_en (0x1) ++ unsigned int reg_dpc_en:1; ++ ++ // h0000, bit: 2 ++ /* DPC mode*/ ++ #define offset_of_reg_dpc_mode (0) ++ #define mask_of_reg_dpc_mode (0x6) ++ unsigned int reg_dpc_mode:2; ++ ++ // h0000, bit: 3 ++ /* DPC awb-gain enable*/ ++ #define offset_of_reg_dpc_awbg_en (0) ++ #define mask_of_reg_dpc_awbg_en (0x8) ++ unsigned int reg_dpc_awbg_en:1; ++ ++ // h0000, bit: 4 ++ /* DPC edge mode enable*/ ++ #define offset_of_reg_dpc_edge_mode (0) ++ #define mask_of_reg_dpc_edge_mode (0x10) ++ unsigned int reg_dpc_edge_mode:1; ++ ++ // h0000, bit: 5 ++ /* DPC light enable*/ ++ #define offset_of_reg_dpc_light_en (0) ++ #define mask_of_reg_dpc_light_en (0x20) ++ unsigned int reg_dpc_light_en:1; ++ ++ // h0000, bit: 6 ++ /* DPC dark enable*/ ++ #define offset_of_reg_dpc_dark_en (0) ++ #define mask_of_reg_dpc_dark_en (0x40) ++ unsigned int reg_dpc_dark_en:1; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :9; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 11 ++ /* DPC threshold R */ ++ #define offset_of_reg_dpc_th_r (2) ++ #define mask_of_reg_dpc_th_r (0xfff) ++ unsigned int reg_dpc_th_r:12; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 11 ++ /* DPC threshold Gr */ ++ #define offset_of_reg_dpc_th_gr (4) ++ #define mask_of_reg_dpc_th_gr (0xfff) ++ unsigned int reg_dpc_th_gr:12; ++ ++ // h0002, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 11 ++ /* DPC threshold Gb */ ++ #define offset_of_reg_dpc_th_gb (6) ++ #define mask_of_reg_dpc_th_gb (0xfff) ++ unsigned int reg_dpc_th_gb:12; ++ ++ // h0003, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 11 ++ /* DPC threshold B*/ ++ #define offset_of_reg_dpc_th_b (8) ++ #define mask_of_reg_dpc_th_b (0xfff) ++ unsigned int reg_dpc_th_b:12; ++ ++ // h0004, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 0 ++ /* DPC cluster light-R enable*/ ++ #define offset_of_reg_dpc_cluster_lr_en (10) ++ #define mask_of_reg_dpc_cluster_lr_en (0x1) ++ unsigned int reg_dpc_cluster_lr_en:1; ++ ++ // h0005, bit: 1 ++ /* DPC cluster light-Gr enable*/ ++ #define offset_of_reg_dpc_cluster_lgr_en (10) ++ #define mask_of_reg_dpc_cluster_lgr_en (0x2) ++ unsigned int reg_dpc_cluster_lgr_en:1; ++ ++ // h0005, bit: 2 ++ /* DPC cluster light-Gb enable*/ ++ #define offset_of_reg_dpc_cluster_lgb_en (10) ++ #define mask_of_reg_dpc_cluster_lgb_en (0x4) ++ unsigned int reg_dpc_cluster_lgb_en:1; ++ ++ // h0005, bit: 3 ++ /* DPC cluster light-B enable*/ ++ #define offset_of_reg_dpc_cluster_lb_en (10) ++ #define mask_of_reg_dpc_cluster_lb_en (0x8) ++ unsigned int reg_dpc_cluster_lb_en:1; ++ ++ // h0005, bit: 4 ++ /* DPC cluster light mode off*/ ++ #define offset_of_reg_dpc_cluster_mode_loff (10) ++ #define mask_of_reg_dpc_cluster_mode_loff (0x10) ++ unsigned int reg_dpc_cluster_mode_loff:1; ++ ++ // h0005, bit: 7 ++ /* */ ++ unsigned int :3; ++ ++ // h0005, bit: 8 ++ /* DPC cluster dark-R enable*/ ++ #define offset_of_reg_dpc_cluster_dr_en (10) ++ #define mask_of_reg_dpc_cluster_dr_en (0x100) ++ unsigned int reg_dpc_cluster_dr_en:1; ++ ++ // h0005, bit: 9 ++ /* DPC cluster dark-Gr enable*/ ++ #define offset_of_reg_dpc_cluster_dgr_en (10) ++ #define mask_of_reg_dpc_cluster_dgr_en (0x200) ++ unsigned int reg_dpc_cluster_dgr_en:1; ++ ++ // h0005, bit: 10 ++ /* DPC cluster dark-Gb enable*/ ++ #define offset_of_reg_dpc_cluster_dgb_en (10) ++ #define mask_of_reg_dpc_cluster_dgb_en (0x400) ++ unsigned int reg_dpc_cluster_dgb_en:1; ++ ++ // h0005, bit: 11 ++ /* DPC cluster dark-B enable*/ ++ #define offset_of_reg_dpc_cluster_db_en (10) ++ #define mask_of_reg_dpc_cluster_db_en (0x800) ++ unsigned int reg_dpc_cluster_db_en:1; ++ ++ // h0005, bit: 12 ++ /* DPC cluster dark mode off*/ ++ #define offset_of_reg_dpc_cluster_mode_doff (10) ++ #define mask_of_reg_dpc_cluster_mode_doff (0x1000) ++ unsigned int reg_dpc_cluster_mode_doff:1; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 1 ++ /* DPC threshold selection*/ ++ #define offset_of_reg_dpc_th_sel (12) ++ #define mask_of_reg_dpc_th_sel (0x3) ++ unsigned int reg_dpc_th_sel:2; ++ ++ // h0006, bit: 2 ++ /* DPC light threshold adjust*/ ++ #define offset_of_reg_dpc_light_th_adj (12) ++ #define mask_of_reg_dpc_light_th_adj (0x4) ++ unsigned int reg_dpc_light_th_adj:1; ++ ++ // h0006, bit: 3 ++ /* DPC dark threshold adjust*/ ++ #define offset_of_reg_dpc_dark_th_adj (12) ++ #define mask_of_reg_dpc_dark_th_adj (0x8) ++ unsigned int reg_dpc_dark_th_adj:1; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 3 ++ /* DPC light threshold source*/ ++ #define offset_of_reg_dpc_th_light_src (14) ++ #define mask_of_reg_dpc_th_light_src (0xf) ++ unsigned int reg_dpc_th_light_src:4; ++ ++ // h0007, bit: 7 ++ /* DPC light threshold base*/ ++ #define offset_of_reg_dpc_th_light_base (14) ++ #define mask_of_reg_dpc_th_light_base (0xf0) ++ unsigned int reg_dpc_th_light_base:4; ++ ++ // h0007, bit: 11 ++ /* DPC dark threshold source*/ ++ #define offset_of_reg_dpc_th_dark_src (14) ++ #define mask_of_reg_dpc_th_dark_src (0xf00) ++ unsigned int reg_dpc_th_dark_src:4; ++ ++ // h0007, bit: 14 ++ /* DPC dark threshold base*/ ++ #define offset_of_reg_dpc_th_dark_base (14) ++ #define mask_of_reg_dpc_th_dark_base (0xf000) ++ unsigned int reg_dpc_th_dark_base:4; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 7 ++ /* DPC neighbor smooth parameter*/ ++ #define offset_of_reg_dpc_nei_smooth (16) ++ #define mask_of_reg_dpc_nei_smooth (0xff) ++ unsigned int reg_dpc_nei_smooth:8; ++ ++ // h0008, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 11 ++ /* DPC neighbor delta threshold*/ ++ #define offset_of_reg_dpc_nei_delta_th (18) ++ #define mask_of_reg_dpc_nei_delta_th (0xfff) ++ unsigned int reg_dpc_nei_delta_th:12; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 3 ++ /* DPC neighbor delta shift parameter x0 */ ++ #define offset_of_reg_dpc_nei_delta_sft_x0 (20) ++ #define mask_of_reg_dpc_nei_delta_sft_x0 (0xf) ++ unsigned int reg_dpc_nei_delta_sft_x0:4; ++ ++ // h000a, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h000a, bit: 11 ++ /* DPC neighbor delta shift parameter x1*/ ++ #define offset_of_reg_dpc_nei_delta_sft_x1 (20) ++ #define mask_of_reg_dpc_nei_delta_sft_x1 (0xf00) ++ unsigned int reg_dpc_nei_delta_sft_x1:4; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 3 ++ /* DPC neighbor delta shift parameter x2*/ ++ #define offset_of_reg_dpc_nei_delta_sft_x2 (22) ++ #define mask_of_reg_dpc_nei_delta_sft_x2 (0xf) ++ unsigned int reg_dpc_nei_delta_sft_x2:4; ++ ++ // h000b, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h000b, bit: 11 ++ /* DPC neighbor delta shift parameter x3*/ ++ #define offset_of_reg_dpc_nei_delta_sft_x3 (22) ++ #define mask_of_reg_dpc_nei_delta_sft_x3 (0xf00) ++ unsigned int reg_dpc_nei_delta_sft_x3:4; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 3 ++ /* DPC neighbor delta shift parameter x4*/ ++ #define offset_of_reg_dpc_nei_delta_sft_x4 (24) ++ #define mask_of_reg_dpc_nei_delta_sft_x4 (0xf) ++ unsigned int reg_dpc_nei_delta_sft_x4:4; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 7 ++ /* DPC neighbor delta gain0*/ ++ #define offset_of_reg_dpc_nei_delta_gain0 (26) ++ #define mask_of_reg_dpc_nei_delta_gain0 (0xff) ++ unsigned int reg_dpc_nei_delta_gain0:8; ++ ++ // h000d, bit: 14 ++ /* DPC neighbor delta gain1*/ ++ #define offset_of_reg_dpc_nei_delta_gain1 (26) ++ #define mask_of_reg_dpc_nei_delta_gain1 (0xff00) ++ unsigned int reg_dpc_nei_delta_gain1:8; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 7 ++ /* DPC neighbor delta gain2*/ ++ #define offset_of_reg_dpc_nei_delta_gain2 (28) ++ #define mask_of_reg_dpc_nei_delta_gain2 (0xff) ++ unsigned int reg_dpc_nei_delta_gain2:8; ++ ++ // h000e, bit: 14 ++ /* DPC neighbor delta gain3*/ ++ #define offset_of_reg_dpc_nei_delta_gain3 (28) ++ #define mask_of_reg_dpc_nei_delta_gain3 (0xff00) ++ unsigned int reg_dpc_nei_delta_gain3:8; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 7 ++ /* DPC neighbor delta gain4*/ ++ #define offset_of_reg_dpc_nei_delta_gain4 (30) ++ #define mask_of_reg_dpc_nei_delta_gain4 (0xff) ++ unsigned int reg_dpc_nei_delta_gain4:8; ++ ++ // h000f, bit: 14 ++ /* DPC neighbor delta gain5*/ ++ #define offset_of_reg_dpc_nei_delta_gain5 (30) ++ #define mask_of_reg_dpc_nei_delta_gain5 (0xff00) ++ unsigned int reg_dpc_nei_delta_gain5:8; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 11 ++ /* DPC color ratio light-R parameter*/ ++ #define offset_of_reg_dpc_color_ratio_lr (32) ++ #define mask_of_reg_dpc_color_ratio_lr (0xfff) ++ unsigned int reg_dpc_color_ratio_lr:12; ++ ++ // h0010, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 11 ++ /* DPC color ratio light-Gr parameter*/ ++ #define offset_of_reg_dpc_color_ratio_lgr (34) ++ #define mask_of_reg_dpc_color_ratio_lgr (0xfff) ++ unsigned int reg_dpc_color_ratio_lgr:12; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 11 ++ /* DPC color ratio lightGb parameter*/ ++ #define offset_of_reg_dpc_color_ratio_lgb (36) ++ #define mask_of_reg_dpc_color_ratio_lgb (0xfff) ++ unsigned int reg_dpc_color_ratio_lgb:12; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 11 ++ /* DPC color ratio light-B parameter*/ ++ #define offset_of_reg_dpc_color_ratio_lb (38) ++ #define mask_of_reg_dpc_color_ratio_lb (0xfff) ++ unsigned int reg_dpc_color_ratio_lb:12; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 11 ++ /* DPC color ratio light-off parameter*/ ++ #define offset_of_reg_dpc_color_ratio_loff (40) ++ #define mask_of_reg_dpc_color_ratio_loff (0xfff) ++ unsigned int reg_dpc_color_ratio_loff:12; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 11 ++ /* DPC color ratio dark-R parameter*/ ++ #define offset_of_reg_dpc_color_ratio_dr (42) ++ #define mask_of_reg_dpc_color_ratio_dr (0xfff) ++ unsigned int reg_dpc_color_ratio_dr:12; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 11 ++ /* DPC color ratio dark-Gr parameter*/ ++ #define offset_of_reg_dpc_color_ratio_dgr (44) ++ #define mask_of_reg_dpc_color_ratio_dgr (0xfff) ++ unsigned int reg_dpc_color_ratio_dgr:12; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 11 ++ /* DPC color ratio dark-Gb parameter*/ ++ #define offset_of_reg_dpc_color_ratio_dgb (46) ++ #define mask_of_reg_dpc_color_ratio_dgb (0xfff) ++ unsigned int reg_dpc_color_ratio_dgb:12; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 11 ++ /* DPC color ratio dark-B parameter*/ ++ #define offset_of_reg_dpc_color_ratio_db (48) ++ #define mask_of_reg_dpc_color_ratio_db (0xfff) ++ unsigned int reg_dpc_color_ratio_db:12; ++ ++ // h0018, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 11 ++ /* DPC color ratio dark-off parameter*/ ++ #define offset_of_reg_dpc_color_ratio_doff (50) ++ #define mask_of_reg_dpc_color_ratio_doff (0xfff) ++ unsigned int reg_dpc_color_ratio_doff:12; ++ ++ // h0019, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add00 (52) ++ #define mask_of_reg_dpc_light_th_add00 (0xff) ++ unsigned int reg_dpc_light_th_add00:8; ++ ++ // h001a, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add01 (52) ++ #define mask_of_reg_dpc_light_th_add01 (0xff00) ++ unsigned int reg_dpc_light_th_add01:8; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add02 (54) ++ #define mask_of_reg_dpc_light_th_add02 (0xff) ++ unsigned int reg_dpc_light_th_add02:8; ++ ++ // h001b, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add03 (54) ++ #define mask_of_reg_dpc_light_th_add03 (0xff00) ++ unsigned int reg_dpc_light_th_add03:8; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add04 (56) ++ #define mask_of_reg_dpc_light_th_add04 (0xff) ++ unsigned int reg_dpc_light_th_add04:8; ++ ++ // h001c, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add05 (56) ++ #define mask_of_reg_dpc_light_th_add05 (0xff00) ++ unsigned int reg_dpc_light_th_add05:8; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add06 (58) ++ #define mask_of_reg_dpc_light_th_add06 (0xff) ++ unsigned int reg_dpc_light_th_add06:8; ++ ++ // h001d, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add07 (58) ++ #define mask_of_reg_dpc_light_th_add07 (0xff00) ++ unsigned int reg_dpc_light_th_add07:8; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add08 (60) ++ #define mask_of_reg_dpc_light_th_add08 (0xff) ++ unsigned int reg_dpc_light_th_add08:8; ++ ++ // h001e, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add09 (60) ++ #define mask_of_reg_dpc_light_th_add09 (0xff00) ++ unsigned int reg_dpc_light_th_add09:8; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add10 (62) ++ #define mask_of_reg_dpc_light_th_add10 (0xff) ++ unsigned int reg_dpc_light_th_add10:8; ++ ++ // h001f, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add11 (62) ++ #define mask_of_reg_dpc_light_th_add11 (0xff00) ++ unsigned int reg_dpc_light_th_add11:8; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add12 (64) ++ #define mask_of_reg_dpc_light_th_add12 (0xff) ++ unsigned int reg_dpc_light_th_add12:8; ++ ++ // h0020, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add13 (64) ++ #define mask_of_reg_dpc_light_th_add13 (0xff00) ++ unsigned int reg_dpc_light_th_add13:8; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add14 (66) ++ #define mask_of_reg_dpc_light_th_add14 (0xff) ++ unsigned int reg_dpc_light_th_add14:8; ++ ++ // h0021, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add15 (66) ++ #define mask_of_reg_dpc_light_th_add15 (0xff00) ++ unsigned int reg_dpc_light_th_add15:8; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add16 (68) ++ #define mask_of_reg_dpc_light_th_add16 (0xff) ++ unsigned int reg_dpc_light_th_add16:8; ++ ++ // h0022, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add17 (68) ++ #define mask_of_reg_dpc_light_th_add17 (0xff00) ++ unsigned int reg_dpc_light_th_add17:8; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add18 (70) ++ #define mask_of_reg_dpc_light_th_add18 (0xff) ++ unsigned int reg_dpc_light_th_add18:8; ++ ++ // h0023, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add19 (70) ++ #define mask_of_reg_dpc_light_th_add19 (0xff00) ++ unsigned int reg_dpc_light_th_add19:8; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add20 (72) ++ #define mask_of_reg_dpc_light_th_add20 (0xff) ++ unsigned int reg_dpc_light_th_add20:8; ++ ++ // h0024, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add21 (72) ++ #define mask_of_reg_dpc_light_th_add21 (0xff00) ++ unsigned int reg_dpc_light_th_add21:8; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add22 (74) ++ #define mask_of_reg_dpc_light_th_add22 (0xff) ++ unsigned int reg_dpc_light_th_add22:8; ++ ++ // h0025, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add23 (74) ++ #define mask_of_reg_dpc_light_th_add23 (0xff00) ++ unsigned int reg_dpc_light_th_add23:8; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add24 (76) ++ #define mask_of_reg_dpc_light_th_add24 (0xff) ++ unsigned int reg_dpc_light_th_add24:8; ++ ++ // h0026, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add25 (76) ++ #define mask_of_reg_dpc_light_th_add25 (0xff00) ++ unsigned int reg_dpc_light_th_add25:8; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add26 (78) ++ #define mask_of_reg_dpc_light_th_add26 (0xff) ++ unsigned int reg_dpc_light_th_add26:8; ++ ++ // h0027, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add27 (78) ++ #define mask_of_reg_dpc_light_th_add27 (0xff00) ++ unsigned int reg_dpc_light_th_add27:8; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add28 (80) ++ #define mask_of_reg_dpc_light_th_add28 (0xff) ++ unsigned int reg_dpc_light_th_add28:8; ++ ++ // h0028, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add29 (80) ++ #define mask_of_reg_dpc_light_th_add29 (0xff00) ++ unsigned int reg_dpc_light_th_add29:8; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 7 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add30 (82) ++ #define mask_of_reg_dpc_light_th_add30 (0xff) ++ unsigned int reg_dpc_light_th_add30:8; ++ ++ // h0029, bit: 14 ++ /* DPC light threshold add*/ ++ #define offset_of_reg_dpc_light_th_add31 (82) ++ #define mask_of_reg_dpc_light_th_add31 (0xff00) ++ unsigned int reg_dpc_light_th_add31:8; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add00 (84) ++ #define mask_of_reg_dpc_dark_th_add00 (0xff) ++ unsigned int reg_dpc_dark_th_add00:8; ++ ++ // h002a, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add01 (84) ++ #define mask_of_reg_dpc_dark_th_add01 (0xff00) ++ unsigned int reg_dpc_dark_th_add01:8; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add02 (86) ++ #define mask_of_reg_dpc_dark_th_add02 (0xff) ++ unsigned int reg_dpc_dark_th_add02:8; ++ ++ // h002b, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add03 (86) ++ #define mask_of_reg_dpc_dark_th_add03 (0xff00) ++ unsigned int reg_dpc_dark_th_add03:8; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add04 (88) ++ #define mask_of_reg_dpc_dark_th_add04 (0xff) ++ unsigned int reg_dpc_dark_th_add04:8; ++ ++ // h002c, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add05 (88) ++ #define mask_of_reg_dpc_dark_th_add05 (0xff00) ++ unsigned int reg_dpc_dark_th_add05:8; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add06 (90) ++ #define mask_of_reg_dpc_dark_th_add06 (0xff) ++ unsigned int reg_dpc_dark_th_add06:8; ++ ++ // h002d, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add07 (90) ++ #define mask_of_reg_dpc_dark_th_add07 (0xff00) ++ unsigned int reg_dpc_dark_th_add07:8; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add08 (92) ++ #define mask_of_reg_dpc_dark_th_add08 (0xff) ++ unsigned int reg_dpc_dark_th_add08:8; ++ ++ // h002e, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add09 (92) ++ #define mask_of_reg_dpc_dark_th_add09 (0xff00) ++ unsigned int reg_dpc_dark_th_add09:8; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add10 (94) ++ #define mask_of_reg_dpc_dark_th_add10 (0xff) ++ unsigned int reg_dpc_dark_th_add10:8; ++ ++ // h002f, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add11 (94) ++ #define mask_of_reg_dpc_dark_th_add11 (0xff00) ++ unsigned int reg_dpc_dark_th_add11:8; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add12 (96) ++ #define mask_of_reg_dpc_dark_th_add12 (0xff) ++ unsigned int reg_dpc_dark_th_add12:8; ++ ++ // h0030, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add13 (96) ++ #define mask_of_reg_dpc_dark_th_add13 (0xff00) ++ unsigned int reg_dpc_dark_th_add13:8; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add14 (98) ++ #define mask_of_reg_dpc_dark_th_add14 (0xff) ++ unsigned int reg_dpc_dark_th_add14:8; ++ ++ // h0031, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add15 (98) ++ #define mask_of_reg_dpc_dark_th_add15 (0xff00) ++ unsigned int reg_dpc_dark_th_add15:8; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add16 (100) ++ #define mask_of_reg_dpc_dark_th_add16 (0xff) ++ unsigned int reg_dpc_dark_th_add16:8; ++ ++ // h0032, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add17 (100) ++ #define mask_of_reg_dpc_dark_th_add17 (0xff00) ++ unsigned int reg_dpc_dark_th_add17:8; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add18 (102) ++ #define mask_of_reg_dpc_dark_th_add18 (0xff) ++ unsigned int reg_dpc_dark_th_add18:8; ++ ++ // h0033, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add19 (102) ++ #define mask_of_reg_dpc_dark_th_add19 (0xff00) ++ unsigned int reg_dpc_dark_th_add19:8; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add20 (104) ++ #define mask_of_reg_dpc_dark_th_add20 (0xff) ++ unsigned int reg_dpc_dark_th_add20:8; ++ ++ // h0034, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add21 (104) ++ #define mask_of_reg_dpc_dark_th_add21 (0xff00) ++ unsigned int reg_dpc_dark_th_add21:8; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add22 (106) ++ #define mask_of_reg_dpc_dark_th_add22 (0xff) ++ unsigned int reg_dpc_dark_th_add22:8; ++ ++ // h0035, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add23 (106) ++ #define mask_of_reg_dpc_dark_th_add23 (0xff00) ++ unsigned int reg_dpc_dark_th_add23:8; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add24 (108) ++ #define mask_of_reg_dpc_dark_th_add24 (0xff) ++ unsigned int reg_dpc_dark_th_add24:8; ++ ++ // h0036, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add25 (108) ++ #define mask_of_reg_dpc_dark_th_add25 (0xff00) ++ unsigned int reg_dpc_dark_th_add25:8; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add26 (110) ++ #define mask_of_reg_dpc_dark_th_add26 (0xff) ++ unsigned int reg_dpc_dark_th_add26:8; ++ ++ // h0037, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add27 (110) ++ #define mask_of_reg_dpc_dark_th_add27 (0xff00) ++ unsigned int reg_dpc_dark_th_add27:8; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add28 (112) ++ #define mask_of_reg_dpc_dark_th_add28 (0xff) ++ unsigned int reg_dpc_dark_th_add28:8; ++ ++ // h0038, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add29 (112) ++ #define mask_of_reg_dpc_dark_th_add29 (0xff00) ++ unsigned int reg_dpc_dark_th_add29:8; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 7 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add30 (114) ++ #define mask_of_reg_dpc_dark_th_add30 (0xff) ++ unsigned int reg_dpc_dark_th_add30:8; ++ ++ // h0039, bit: 14 ++ /* DPC dark threshold add*/ ++ #define offset_of_reg_dpc_dark_th_add31 (114) ++ #define mask_of_reg_dpc_dark_th_add31 (0xff00) ++ unsigned int reg_dpc_dark_th_add31:8; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 7 ++ /* BNR LPF weight1 parameter*/ ++ #define offset_of_reg_bnr_lpf_w1 (128) ++ #define mask_of_reg_bnr_lpf_w1 (0xff) ++ unsigned int reg_bnr_lpf_w1:8; ++ ++ // h0040, bit: 14 ++ /* BNR LPF weight2 parameter*/ ++ #define offset_of_reg_bnr_lpf_w2 (128) ++ #define mask_of_reg_bnr_lpf_w2 (0xff00) ++ unsigned int reg_bnr_lpf_w2:8; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 7 ++ /* BNR LPF weight3 parameter*/ ++ #define offset_of_reg_bnr_lpf_w3 (130) ++ #define mask_of_reg_bnr_lpf_w3 (0xff) ++ unsigned int reg_bnr_lpf_w3:8; ++ ++ // h0041, bit: 11 ++ /* BNR LPF shift parameter*/ ++ #define offset_of_reg_bnr_lpf_sft (130) ++ #define mask_of_reg_bnr_lpf_sft (0xf00) ++ unsigned int reg_bnr_lpf_sft:4; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 0 ++ /* BNR enable*/ ++ #define offset_of_reg_bnr_en (132) ++ #define mask_of_reg_bnr_en (0x1) ++ unsigned int reg_bnr_en:1; ++ ++ // h0042, bit: 1 ++ /* BNR LPF enable*/ ++ #define offset_of_reg_bnr_lpf_en (132) ++ #define mask_of_reg_bnr_lpf_en (0x2) ++ unsigned int reg_bnr_lpf_en:1; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 11 ++ /* BNR LW parameter*/ ++ #define offset_of_reg_bnr_lw (134) ++ #define mask_of_reg_bnr_lw (0xfff) ++ unsigned int reg_bnr_lw:12; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 3 ++ /* BNR WD*/ ++ #define offset_of_reg_bnr_wd (136) ++ #define mask_of_reg_bnr_wd (0xf) ++ unsigned int reg_bnr_wd:4; ++ ++ // h0044, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0044, bit: 14 ++ /* BNR gain all*/ ++ #define offset_of_reg_bnr_gain_all (136) ++ #define mask_of_reg_bnr_gain_all (0xff00) ++ unsigned int reg_bnr_gain_all:8; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 7 ++ /* BNR gain direction*/ ++ #define offset_of_reg_bnr_gain_dir (138) ++ #define mask_of_reg_bnr_gain_dir (0xff) ++ unsigned int reg_bnr_gain_dir:8; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 11 ++ /* BNR clip*/ ++ #define offset_of_reg_bnr_clip (140) ++ #define mask_of_reg_bnr_clip (0xfff) ++ unsigned int reg_bnr_clip:12; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 11 ++ /* BNR detail lw*/ ++ #define offset_of_reg_bnr_detail_lw (142) ++ #define mask_of_reg_bnr_detail_lw (0xfff) ++ unsigned int reg_bnr_detail_lw:12; ++ ++ // h0047, bit: 14 ++ /* BNR detail wd*/ ++ #define offset_of_reg_bnr_detail_wd (142) ++ #define mask_of_reg_bnr_detail_wd (0xf000) ++ unsigned int reg_bnr_detail_wd:4; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 11 ++ /* AWB gain R */ ++ #define offset_of_reg_awb_gain_r (144) ++ #define mask_of_reg_awb_gain_r (0xfff) ++ unsigned int reg_awb_gain_r:12; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 11 ++ /* AWB gain gr*/ ++ #define offset_of_reg_awb_gain_gr (146) ++ #define mask_of_reg_awb_gain_gr (0xfff) ++ unsigned int reg_awb_gain_gr:12; ++ ++ // h0049, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 11 ++ /* AWB gain gb*/ ++ #define offset_of_reg_awb_gain_gb (148) ++ #define mask_of_reg_awb_gain_gb (0xfff) ++ unsigned int reg_awb_gain_gb:12; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 11 ++ /* AWB gain b*/ ++ #define offset_of_reg_awb_gain_b (150) ++ #define mask_of_reg_awb_gain_b (0xfff) ++ unsigned int reg_awb_gain_b:12; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 11 ++ /* AWB gain R for 2nd*/ ++ #define offset_of_reg_awb_gain_r_f1 (152) ++ #define mask_of_reg_awb_gain_r_f1 (0xfff) ++ unsigned int reg_awb_gain_r_f1:12; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 11 ++ /* AWB gain gr for 2nd*/ ++ #define offset_of_reg_awb_gain_gr_f1 (154) ++ #define mask_of_reg_awb_gain_gr_f1 (0xfff) ++ unsigned int reg_awb_gain_gr_f1:12; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 11 ++ /* AWB gain gb for 2nd*/ ++ #define offset_of_reg_awb_gain_gb_f1 (156) ++ #define mask_of_reg_awb_gain_gb_f1 (0xfff) ++ unsigned int reg_awb_gain_gb_f1:12; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 11 ++ /* AWB gain b for 2nd*/ ++ #define offset_of_reg_awb_gain_b_f1 (158) ++ #define mask_of_reg_awb_gain_b_f1 (0xfff) ++ unsigned int reg_awb_gain_b_f1:12; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 0 ++ /* New sorting enable*/ ++ #define offset_of_reg_dpc_sort_en (160) ++ #define mask_of_reg_dpc_sort_en (0x1) ++ unsigned int reg_dpc_sort_en:1; ++ ++ // h0050, bit: 1 ++ /* New sorting R enable*/ ++ #define offset_of_reg_dpc_sort_r_en (160) ++ #define mask_of_reg_dpc_sort_r_en (0x2) ++ unsigned int reg_dpc_sort_r_en:1; ++ ++ // h0050, bit: 2 ++ /* New sorting GR enable*/ ++ #define offset_of_reg_dpc_sort_gr_en (160) ++ #define mask_of_reg_dpc_sort_gr_en (0x4) ++ unsigned int reg_dpc_sort_gr_en:1; ++ ++ // h0050, bit: 3 ++ /* New sorting GB enable*/ ++ #define offset_of_reg_dpc_sort_gb_en (160) ++ #define mask_of_reg_dpc_sort_gb_en (0x8) ++ unsigned int reg_dpc_sort_gb_en:1; ++ ++ // h0050, bit: 4 ++ /* New sorting B enable*/ ++ #define offset_of_reg_dpc_sort_b_en (160) ++ #define mask_of_reg_dpc_sort_b_en (0x10) ++ unsigned int reg_dpc_sort_b_en:1; ++ ++ // h0050, bit: 5 ++ /* New sorting 1x3 mode enable*/ ++ #define offset_of_reg_dpc_sort_1x3_mode_en (160) ++ #define mask_of_reg_dpc_sort_1x3_mode_en (0x20) ++ unsigned int reg_dpc_sort_1x3_mode_en:1; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 3 ++ /* New sorting luma table shift x0 */ ++ #define offset_of_reg_dpc_sort_lumtbl_x0 (162) ++ #define mask_of_reg_dpc_sort_lumtbl_x0 (0xf) ++ unsigned int reg_dpc_sort_lumtbl_x0:4; ++ ++ // h0051, bit: 7 ++ /* New sorting luma table shift x1 */ ++ #define offset_of_reg_dpc_sort_lumtbl_x1 (162) ++ #define mask_of_reg_dpc_sort_lumtbl_x1 (0xf0) ++ unsigned int reg_dpc_sort_lumtbl_x1:4; ++ ++ // h0051, bit: 11 ++ /* New sorting luma table shift x2*/ ++ #define offset_of_reg_dpc_sort_lumtbl_x2 (162) ++ #define mask_of_reg_dpc_sort_lumtbl_x2 (0xf00) ++ unsigned int reg_dpc_sort_lumtbl_x2:4; ++ ++ // h0051, bit: 14 ++ /* New sorting luma table shift x3*/ ++ #define offset_of_reg_dpc_sort_lumtbl_x3 (162) ++ #define mask_of_reg_dpc_sort_lumtbl_x3 (0xf000) ++ unsigned int reg_dpc_sort_lumtbl_x3:4; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 3 ++ /* New sorting luma table shift x4*/ ++ #define offset_of_reg_dpc_sort_lumtbl_x4 (164) ++ #define mask_of_reg_dpc_sort_lumtbl_x4 (0xf) ++ unsigned int reg_dpc_sort_lumtbl_x4:4; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 11 ++ /* New sorting luma table light 0*/ ++ #define offset_of_reg_dpc_sort_lumtbl_l0 (166) ++ #define mask_of_reg_dpc_sort_lumtbl_l0 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_l0:12; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 11 ++ /* New sorting luma table light 1*/ ++ #define offset_of_reg_dpc_sort_lumtbl_l1 (168) ++ #define mask_of_reg_dpc_sort_lumtbl_l1 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_l1:12; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 11 ++ /* New sorting luma table light 2*/ ++ #define offset_of_reg_dpc_sort_lumtbl_l2 (170) ++ #define mask_of_reg_dpc_sort_lumtbl_l2 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_l2:12; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 11 ++ /* New sorting luma table light 3*/ ++ #define offset_of_reg_dpc_sort_lumtbl_l3 (172) ++ #define mask_of_reg_dpc_sort_lumtbl_l3 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_l3:12; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 11 ++ /* New sorting luma table light 4*/ ++ #define offset_of_reg_dpc_sort_lumtbl_l4 (174) ++ #define mask_of_reg_dpc_sort_lumtbl_l4 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_l4:12; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 11 ++ /* New sorting luma table light 5*/ ++ #define offset_of_reg_dpc_sort_lumtbl_l5 (176) ++ #define mask_of_reg_dpc_sort_lumtbl_l5 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_l5:12; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 11 ++ /* New sorting luma table dark 0*/ ++ #define offset_of_reg_dpc_sort_lumtbl_d0 (178) ++ #define mask_of_reg_dpc_sort_lumtbl_d0 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_d0:12; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 11 ++ /* New sorting luma table dark 1*/ ++ #define offset_of_reg_dpc_sort_lumtbl_d1 (180) ++ #define mask_of_reg_dpc_sort_lumtbl_d1 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_d1:12; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 11 ++ /* New sorting luma table dark 2*/ ++ #define offset_of_reg_dpc_sort_lumtbl_d2 (182) ++ #define mask_of_reg_dpc_sort_lumtbl_d2 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_d2:12; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 11 ++ /* New sorting luma table dark 3*/ ++ #define offset_of_reg_dpc_sort_lumtbl_d3 (184) ++ #define mask_of_reg_dpc_sort_lumtbl_d3 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_d3:12; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 11 ++ /* New sorting luma table dark 4*/ ++ #define offset_of_reg_dpc_sort_lumtbl_d4 (186) ++ #define mask_of_reg_dpc_sort_lumtbl_d4 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_d4:12; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 11 ++ /* New sorting luma table dark 5*/ ++ #define offset_of_reg_dpc_sort_lumtbl_d5 (188) ++ #define mask_of_reg_dpc_sort_lumtbl_d5 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_d5:12; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 11 ++ /* New sorting luma table second 0*/ ++ #define offset_of_reg_dpc_sort_lumtbl_s0 (190) ++ #define mask_of_reg_dpc_sort_lumtbl_s0 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_s0:12; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 11 ++ /* New sorting luma table second 1*/ ++ #define offset_of_reg_dpc_sort_lumtbl_s1 (192) ++ #define mask_of_reg_dpc_sort_lumtbl_s1 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_s1:12; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 11 ++ /* New sorting luma table second 2*/ ++ #define offset_of_reg_dpc_sort_lumtbl_s2 (194) ++ #define mask_of_reg_dpc_sort_lumtbl_s2 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_s2:12; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 11 ++ /* New sorting luma table second 3*/ ++ #define offset_of_reg_dpc_sort_lumtbl_s3 (196) ++ #define mask_of_reg_dpc_sort_lumtbl_s3 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_s3:12; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 11 ++ /* New sorting luma table second 4*/ ++ #define offset_of_reg_dpc_sort_lumtbl_s4 (198) ++ #define mask_of_reg_dpc_sort_lumtbl_s4 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_s4:12; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 11 ++ /* New sorting luma table second 5*/ ++ #define offset_of_reg_dpc_sort_lumtbl_s5 (200) ++ #define mask_of_reg_dpc_sort_lumtbl_s5 (0xfff) ++ unsigned int reg_dpc_sort_lumtbl_s5:12; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 14 ++ /* register test dummy 0*/ ++ #define offset_of_reg_dummy_0 (202) ++ #define mask_of_reg_dummy_0 (0xffff) ++ unsigned int reg_dummy_0:16; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* register test dummy 1*/ ++ #define offset_of_reg_dummy_1 (204) ++ #define mask_of_reg_dummy_1 (0xffff) ++ unsigned int reg_dummy_1:16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp2; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp3.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp3.h +new file mode 100644 +index 00000000..24b1b710 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp3.h +@@ -0,0 +1,1734 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP3__ ++#define __INFINITY3E_REG_ISP3__ ++typedef struct { ++ // h0000, bit: 0 ++ /* ISP statistic enable*/ ++ #define offset_of_reg_isp_statis_en (0) ++ #define mask_of_reg_isp_statis_en (0x1) ++ unsigned int reg_isp_statis_en:1; ++ ++ // h0000, bit: 1 ++ /* Trigger of ISP statistic one frame mode*/ ++ #define offset_of_reg_statis_once_trig (0) ++ #define mask_of_reg_statis_once_trig (0x2) ++ unsigned int reg_statis_once_trig:1; ++ ++ // h0000, bit: 2 ++ /* ISP statistic AE enable*/ ++ #define offset_of_reg_isp_statis_ae_en (0) ++ #define mask_of_reg_isp_statis_ae_en (0x4) ++ unsigned int reg_isp_statis_ae_en:1; ++ ++ // h0000, bit: 3 ++ /* ISP statistic AWB enable*/ ++ #define offset_of_reg_isp_statis_awb_en (0) ++ #define mask_of_reg_isp_statis_awb_en (0x8) ++ unsigned int reg_isp_statis_awb_en:1; ++ ++ // h0000, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0000, bit: 14 ++ /* AE block row number for interrupt*/ ++ #define offset_of_reg_ae_int_row_num (0) ++ #define mask_of_reg_ae_int_row_num (0x7f00) ++ unsigned int reg_ae_int_row_num:7; ++ ++ // h0000, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 9 ++ /* AE block width minus one*/ ++ #define offset_of_reg_ae_blksize_x_m1 (2) ++ #define mask_of_reg_ae_blksize_x_m1 (0x3ff) ++ unsigned int reg_ae_blksize_x_m1:10; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 9 ++ /* AE block height minus one*/ ++ #define offset_of_reg_ae_blksize_y_m1 (4) ++ #define mask_of_reg_ae_blksize_y_m1 (0x3ff) ++ unsigned int reg_ae_blksize_y_m1:10; ++ ++ // h0002, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 6 ++ /* AE Horizontal block number minus one*/ ++ #define offset_of_reg_ae_blknum_x_m1 (6) ++ #define mask_of_reg_ae_blknum_x_m1 (0x7f) ++ unsigned int reg_ae_blknum_x_m1:7; ++ ++ // h0003, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0003, bit: 14 ++ /* AE vertical block number minus one*/ ++ #define offset_of_reg_ae_blknum_y_m1 (6) ++ #define mask_of_reg_ae_blknum_y_m1 (0x7f00) ++ unsigned int reg_ae_blknum_y_m1:7; ++ ++ // h0003, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 11 ++ /* AE horizontal block pixel offset*/ ++ #define offset_of_reg_ae_blk_h_offset (8) ++ #define mask_of_reg_ae_blk_h_offset (0xfff) ++ unsigned int reg_ae_blk_h_offset:12; ++ ++ // h0004, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 11 ++ /* AE veritcal block pixel offset*/ ++ #define offset_of_reg_ae_blk_v_offset (10) ++ #define mask_of_reg_ae_blk_v_offset (0xfff) ++ unsigned int reg_ae_blk_v_offset:12; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 14 ++ /* AE statistic frame buffer (unit : 16bytes) ++ Offset 0~4 : Red histogram ++ Offset 5~9 : Green histogram ++ Offset 10~14 : Blue histogram ++ Offset 15~30 : WIn0 histogram ++ Offset 31~46 : WIn1 histogram ++ Offset 47~ : R/G/B/Y block average*/ ++ #define offset_of_reg_ae_statis_base (12) ++ #define mask_of_reg_ae_statis_base (0xffff) ++ unsigned int reg_ae_statis_base:16; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 10 ++ /* AE statistic frame buffer (unit : 16bytes) ++ Offset 0~4 : Red histogram ++ Offset 5~9 : Green histogram ++ Offset 10~14 : Blue histogram ++ Offset 15~30 : WIn0 histogram ++ Offset 31~46 : WIn1 histogram ++ Offset 47~ : R/G/B/Y block average*/ ++ #define offset_of_reg_ae_statis_base_1 (14) ++ #define mask_of_reg_ae_statis_base_1 (0x7ff) ++ unsigned int reg_ae_statis_base_1:11; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 14 ++ /* AWB statistic frame buffer (unit : 16bytes)*/ ++ #define offset_of_reg_awb_statis_base (16) ++ #define mask_of_reg_awb_statis_base (0xffff) ++ unsigned int reg_awb_statis_base:16; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 10 ++ /* AWB statistic frame buffer (unit : 16bytes)*/ ++ #define offset_of_reg_awb_statis_base_1 (18) ++ #define mask_of_reg_awb_statis_base_1 (0x7ff) ++ unsigned int reg_awb_statis_base_1:11; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 14 ++ /* Histo statistic frame buffer (unit : 16bytes)*/ ++ #define offset_of_reg_histo_statis_base (20) ++ #define mask_of_reg_histo_statis_base (0xffff) ++ unsigned int reg_histo_statis_base:16; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 10 ++ /* Histo statistic frame buffer (unit : 16bytes)*/ ++ #define offset_of_reg_histo_statis_base_1 (22) ++ #define mask_of_reg_histo_statis_base_1 (0x7ff) ++ unsigned int reg_histo_statis_base_1:11; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 1 ++ /* AWB write miu burst length x4*/ ++ #define offset_of_reg_statis_awb_mi_lenx4 (28) ++ #define mask_of_reg_statis_awb_mi_lenx4 (0x3) ++ unsigned int reg_statis_awb_mi_lenx4:2; ++ ++ // h000e, bit: 7 ++ /* AWB write miu mask period between each burst*/ ++ #define offset_of_reg_statis_awb_mi_mask_cycx16 (28) ++ #define mask_of_reg_statis_awb_mi_mask_cycx16 (0xfc) ++ unsigned int reg_statis_awb_mi_mask_cycx16:6; ++ ++ // h000e, bit: 9 ++ /* Block average write miu burst length x4*/ ++ #define offset_of_reg_statis_avg_mi_lenx4 (28) ++ #define mask_of_reg_statis_avg_mi_lenx4 (0x300) ++ unsigned int reg_statis_avg_mi_lenx4:2; ++ ++ // h000e, bit: 14 ++ /* Block average write miu mask period between each burst*/ ++ #define offset_of_reg_statis_avg_mi_mask_cycx16 (28) ++ #define mask_of_reg_statis_avg_mi_mask_cycx16 (0xfc00) ++ unsigned int reg_statis_avg_mi_mask_cycx16:6; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 1 ++ /* Histogram write miu burst length x4*/ ++ #define offset_of_reg_statis_histo_mi_lenx4 (30) ++ #define mask_of_reg_statis_histo_mi_lenx4 (0x3) ++ unsigned int reg_statis_histo_mi_lenx4:2; ++ ++ // h000f, bit: 7 ++ /* Histogram write miu mask period between each burst*/ ++ #define offset_of_reg_statis_histo_mi_mask_cycx16 (30) ++ #define mask_of_reg_statis_histo_mi_mask_cycx16 (0xfc) ++ unsigned int reg_statis_histo_mi_mask_cycx16:6; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 14 ++ /* AE average statistic max miu write address*/ ++ #define offset_of_reg_ae_max_wadr (32) ++ #define mask_of_reg_ae_max_wadr (0xffff) ++ unsigned int reg_ae_max_wadr:16; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 10 ++ /* AE average statistic max miu write address*/ ++ #define offset_of_reg_ae_max_wadr_1 (34) ++ #define mask_of_reg_ae_max_wadr_1 (0x7ff) ++ unsigned int reg_ae_max_wadr_1:11; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 14 ++ /* AWB statistic max miu write address*/ ++ #define offset_of_reg_awb_max_wadr (36) ++ #define mask_of_reg_awb_max_wadr (0xffff) ++ unsigned int reg_awb_max_wadr:16; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 10 ++ /* AWB statistic max miu write address*/ ++ #define offset_of_reg_awb_max_wadr_1 (38) ++ #define mask_of_reg_awb_max_wadr_1 (0x7ff) ++ unsigned int reg_awb_max_wadr_1:11; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 14 ++ /* Histogram statistic max miu write address*/ ++ #define offset_of_reg_histo_max_wadr (40) ++ #define mask_of_reg_histo_max_wadr (0xffff) ++ unsigned int reg_histo_max_wadr:16; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 10 ++ /* Histogram statistic max miu write address*/ ++ #define offset_of_reg_histo_max_wadr_1 (42) ++ #define mask_of_reg_histo_max_wadr_1 (0x7ff) ++ unsigned int reg_histo_max_wadr_1:11; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 14 ++ /* AE block average divisor A minus one*/ ++ #define offset_of_reg_ae_div_a_m1 (48) ++ #define mask_of_reg_ae_div_a_m1 (0xffff) ++ unsigned int reg_ae_div_a_m1:16; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 14 ++ /* AE block average divisor B minus one*/ ++ #define offset_of_reg_ae_div_b_m1 (50) ++ #define mask_of_reg_ae_div_b_m1 (0xffff) ++ unsigned int reg_ae_div_b_m1:16; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 14 ++ /* AE block average divisor C minus one*/ ++ #define offset_of_reg_ae_div_c_m1 (52) ++ #define mask_of_reg_ae_div_c_m1 (0xffff) ++ unsigned int reg_ae_div_c_m1:16; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 14 ++ /* AE block average divisor D minus one*/ ++ #define offset_of_reg_ae_div_d_m1 (54) ++ #define mask_of_reg_ae_div_d_m1 (0xffff) ++ unsigned int reg_ae_div_d_m1:16; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* AE block average divisor E minus one*/ ++ #define offset_of_reg_ae_div_e_m1 (56) ++ #define mask_of_reg_ae_div_e_m1 (0xffff) ++ unsigned int reg_ae_div_e_m1:16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* AE block average divisor F minuso one*/ ++ #define offset_of_reg_ae_div_f_m1 (58) ++ #define mask_of_reg_ae_div_f_m1 (0xffff) ++ unsigned int reg_ae_div_f_m1:16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 3 ++ /* AE accumulation shift register*/ ++ #define offset_of_reg_ae_acc_sft (60) ++ #define mask_of_reg_ae_acc_sft (0xf) ++ unsigned int reg_ae_acc_sft:4; ++ ++ // h001e, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 0 ++ /* ALSC enable*/ ++ #define offset_of_reg_en_alsc (64) ++ #define mask_of_reg_en_alsc (0x1) ++ unsigned int reg_en_alsc:1; ++ ++ // h0020, bit: 1 ++ /* */ ++ unsigned int :1; ++ ++ // h0020, bit: 2 ++ /* ALSC dither enable*/ ++ #define offset_of_reg_alsc_dither_en (64) ++ #define mask_of_reg_alsc_dither_en (0x4) ++ unsigned int reg_alsc_dither_en:1; ++ ++ // h0020, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h0020, bit: 5 ++ /* ALSC x block mode : (blk size) ++ 0: 8 ++ 1: 16 ++ 2: 32 ++ 3: 64*/ ++ #define offset_of_reg_alsc_x_blk_mode (64) ++ #define mask_of_reg_alsc_x_blk_mode (0x30) ++ unsigned int reg_alsc_x_blk_mode:2; ++ ++ // h0020, bit: 7 ++ /* ALSC y block mode : (blk size) ++ 0: 8 ++ 1: 16 ++ 2: 32 ++ 3: 64*/ ++ #define offset_of_reg_alsc_y_blk_mode (64) ++ #define mask_of_reg_alsc_y_blk_mode (0xc0) ++ unsigned int reg_alsc_y_blk_mode:2; ++ ++ // h0020, bit: 10 ++ /* ALSC debug mode enable ([0]:R; [1]:G;[2]:B)*/ ++ #define offset_of_reg_alsc_dbg_en (64) ++ #define mask_of_reg_alsc_dbg_en (0x700) ++ unsigned int reg_alsc_dbg_en:3; ++ ++ // h0020, bit: 12 ++ /* ALSC debug gain right shift*/ ++ #define offset_of_reg_alsc_dbg_shift (64) ++ #define mask_of_reg_alsc_dbg_shift (0x1800) ++ unsigned int reg_alsc_dbg_shift:2; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 11 ++ /* ALSC horizontal offset*/ ++ #define offset_of_reg_alsc_offsetx (66) ++ #define mask_of_reg_alsc_offsetx (0xfff) ++ unsigned int reg_alsc_offsetx:12; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 11 ++ /* ALSC vertical offset*/ ++ #define offset_of_reg_alsc_offsety (68) ++ #define mask_of_reg_alsc_offsety (0xfff) ++ unsigned int reg_alsc_offsety:12; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 7 ++ /* ALSC gain table width minus one*/ ++ #define offset_of_reg_alsc_gtbl_width_m1 (70) ++ #define mask_of_reg_alsc_gtbl_width_m1 (0xff) ++ unsigned int reg_alsc_gtbl_width_m1:8; ++ ++ // h0023, bit: 14 ++ /* ALSC gain table height minus one*/ ++ #define offset_of_reg_alsc_gtbl_height_m1 (70) ++ #define mask_of_reg_alsc_gtbl_height_m1 (0xff00) ++ unsigned int reg_alsc_gtbl_height_m1:8; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 7 ++ /* ALSC gain table pitch*/ ++ #define offset_of_reg_alsc_gtbl_pitch (72) ++ #define mask_of_reg_alsc_gtbl_pitch (0xff) ++ unsigned int reg_alsc_gtbl_pitch:8; ++ ++ // h0024, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 14 ++ /* ALSC interpolation coefficients*/ ++ #define offset_of_reg_coef_buf_wd (74) ++ #define mask_of_reg_coef_buf_wd (0xffff) ++ unsigned int reg_coef_buf_wd:16; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 14 ++ /* ALSC interpolation coefficients*/ ++ #define offset_of_reg_coef_buf_wd_1 (76) ++ #define mask_of_reg_coef_buf_wd_1 (0xffff) ++ unsigned int reg_coef_buf_wd_1:16; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 5 ++ /* ALSC coefficient table address ++ H : 0~32 ++ V : 0~32*/ ++ #define offset_of_reg_coef_buf_adr (78) ++ #define mask_of_reg_coef_buf_adr (0x3f) ++ unsigned int reg_coef_buf_adr:6; ++ ++ // h0027, bit: 6 ++ /* */ ++ unsigned int :1; ++ ++ // h0027, bit: 7 ++ /* ALSC coefficient table select : ++ 0 : Horizontal ++ 1 : Vertical*/ ++ #define offset_of_reg_coef_buf_sel_v (78) ++ #define mask_of_reg_coef_buf_sel_v (0x80) ++ unsigned int reg_coef_buf_sel_v:1; ++ ++ // h0027, bit: 8 ++ /* ALSC coefficient table write*/ ++ #define offset_of_reg_coef_buf_we (78) ++ #define mask_of_reg_coef_buf_we (0x100) ++ unsigned int reg_coef_buf_we:1; ++ ++ // h0027, bit: 9 ++ /* ALSC coefficient table read*/ ++ #define offset_of_reg_coef_buf_re (78) ++ #define mask_of_reg_coef_buf_re (0x200) ++ unsigned int reg_coef_buf_re:1; ++ ++ // h0027, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* ALSC interpolation coefficients*/ ++ #define offset_of_reg_coef_buf_rd (80) ++ #define mask_of_reg_coef_buf_rd (0xffff) ++ unsigned int reg_coef_buf_rd:16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 14 ++ /* ALSC interpolation coefficients*/ ++ #define offset_of_reg_coef_buf_rd_1 (82) ++ #define mask_of_reg_coef_buf_rd_1 (0xffff) ++ unsigned int reg_coef_buf_rd_1:16; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 2 ++ /* ALSC table maping ++ 3'b000: no rotation ++ 3'b001: clockwise 90 ++ 3'b010: clockwise 180 ++ 3'b011: clockwise 270 ++ 3'b100: horizontal mirror ++ 3'b101: vertical mirror*/ ++ #define offset_of_reg_asymlsc_orientation (84) ++ #define mask_of_reg_asymlsc_orientation (0x7) ++ unsigned int reg_asymlsc_orientation:3; ++ ++ // h002a, bit: 14 ++ /* */ ++ unsigned int :13; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 11 ++ /* ALSC table scalar (input frame height mapping to 1920)*/ ++ #define offset_of_reg_asymlsc_scale_x (86) ++ #define mask_of_reg_asymlsc_scale_x (0xfff) ++ unsigned int reg_asymlsc_scale_x:12; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 11 ++ /* ALSC table scalar (input frame height mapping to 1080)*/ ++ #define offset_of_reg_asymlsc_scale_y (88) ++ #define mask_of_reg_asymlsc_scale_y (0xfff) ++ unsigned int reg_asymlsc_scale_y:12; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 0 ++ /* DNR enable*/ ++ #define offset_of_reg_dnr_en (96) ++ #define mask_of_reg_dnr_en (0x1) ++ unsigned int reg_dnr_en:1; ++ ++ // h0030, bit: 1 ++ /* DNR luma adaptive enable*/ ++ #define offset_of_reg_dnr_lum_en (96) ++ #define mask_of_reg_dnr_lum_en (0x2) ++ unsigned int reg_dnr_lum_en:1; ++ ++ // h0030, bit: 2 ++ /* DNR luma adaptive shift bits: ++ 0: 3-bits ++ 1: 4-bits*/ ++ #define offset_of_reg_dnr_lum_sh (96) ++ #define mask_of_reg_dnr_lum_sh (0x4) ++ unsigned int reg_dnr_lum_sh:1; ++ ++ // h0030, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h0030, bit: 4 ++ /* DNR motion filter enable*/ ++ #define offset_of_reg_dnr_filter_en (96) ++ #define mask_of_reg_dnr_filter_en (0x10) ++ unsigned int reg_dnr_filter_en:1; ++ ++ // h0030, bit: 6 ++ /* DNR motion filter mode*/ ++ #define offset_of_reg_dnr_filter_mode (96) ++ #define mask_of_reg_dnr_filter_mode (0x60) ++ unsigned int reg_dnr_filter_mode:2; ++ ++ // h0030, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0030, bit: 10 ++ /* DNR Div 0 for motion filter*/ ++ #define offset_of_reg_dnr_filter_div0 (96) ++ #define mask_of_reg_dnr_filter_div0 (0x700) ++ unsigned int reg_dnr_filter_div0:3; ++ ++ // h0030, bit: 11 ++ /* */ ++ unsigned int :1; ++ ++ // h0030, bit: 13 ++ /* DNR Div 1 for motion filter*/ ++ #define offset_of_reg_dnr_filter_div1 (96) ++ #define mask_of_reg_dnr_filter_div1 (0x3000) ++ unsigned int reg_dnr_filter_div1:2; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 14 ++ /* DNR luma adaptive table*/ ++ #define offset_of_reg_dnr_lum_table (98) ++ #define mask_of_reg_dnr_lum_table (0xffff) ++ unsigned int reg_dnr_lum_table:16; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 14 ++ /* DNR luma adaptive table*/ ++ #define offset_of_reg_dnr_lum_table_1 (100) ++ #define mask_of_reg_dnr_lum_table_1 (0xffff) ++ unsigned int reg_dnr_lum_table_1:16; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 0 ++ /* DNR table select*/ ++ #define offset_of_reg_nr_table_sel (102) ++ #define mask_of_reg_nr_table_sel (0x1) ++ unsigned int reg_nr_table_sel:1; ++ ++ // h0033, bit: 1 ++ /* DNR non-dither method enable*/ ++ #define offset_of_reg_dnr_nondither_method (102) ++ #define mask_of_reg_dnr_nondither_method (0x2) ++ unsigned int reg_dnr_nondither_method:1; ++ ++ // h0033, bit: 2 ++ /* DNR non-dither method select*/ ++ #define offset_of_reg_dnr_nondither_method_mode (102) ++ #define mask_of_reg_dnr_nondither_method_mode (0x4) ++ unsigned int reg_dnr_nondither_method_mode:1; ++ ++ // h0033, bit: 4 ++ /* DNR rounding mode for blending*/ ++ #define offset_of_reg_round_mode (102) ++ #define mask_of_reg_round_mode (0x18) ++ unsigned int reg_round_mode:2; ++ ++ // h0033, bit: 7 ++ /* */ ++ unsigned int :3; ++ ++ // h0033, bit: 12 ++ /* DNR sticky solver threshold*/ ++ #define offset_of_reg_sticky_solver_th (102) ++ #define mask_of_reg_sticky_solver_th (0x1f00) ++ unsigned int reg_sticky_solver_th:5; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :2; ++ ++ // h0033, bit: 15 ++ /* DNR sticky solver enable*/ ++ #define offset_of_reg_sticky_solver_en (102) ++ #define mask_of_reg_sticky_solver_en (0x8000) ++ unsigned int reg_sticky_solver_en:1; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* DNR table*/ ++ #define offset_of_reg_dnr_tabley (104) ++ #define mask_of_reg_dnr_tabley (0xffff) ++ unsigned int reg_dnr_tabley:16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 14 ++ /* DNR table*/ ++ #define offset_of_reg_dnr_tabley_1 (106) ++ #define mask_of_reg_dnr_tabley_1 (0xffff) ++ unsigned int reg_dnr_tabley_1:16; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* DNR table*/ ++ #define offset_of_reg_dnr_tabley_2 (108) ++ #define mask_of_reg_dnr_tabley_2 (0xffff) ++ unsigned int reg_dnr_tabley_2:16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* DNR table*/ ++ #define offset_of_reg_dnr_tabley_3 (110) ++ #define mask_of_reg_dnr_tabley_3 (0xffff) ++ unsigned int reg_dnr_tabley_3:16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 14 ++ /* DNR frame buffer base address 0*/ ++ #define offset_of_reg_dnr_fb_base_0 (112) ++ #define mask_of_reg_dnr_fb_base_0 (0xffff) ++ unsigned int reg_dnr_fb_base_0:16; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 10 ++ /* DNR frame buffer base address 0*/ ++ #define offset_of_reg_dnr_fb_base_0_1 (114) ++ #define mask_of_reg_dnr_fb_base_0_1 (0x7ff) ++ unsigned int reg_dnr_fb_base_0_1:11; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* DNR frame buffer base address 1*/ ++ #define offset_of_reg_dnr_fb_base_1 (116) ++ #define mask_of_reg_dnr_fb_base_1 (0xffff) ++ unsigned int reg_dnr_fb_base_1:16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 10 ++ /* DNR frame buffer base address 1*/ ++ #define offset_of_reg_dnr_fb_base_1_1 (118) ++ #define mask_of_reg_dnr_fb_base_1_1 (0x7ff) ++ unsigned int reg_dnr_fb_base_1_1:11; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 3 ++ /* Pitch width/192*/ ++ #define offset_of_reg_dnr_fb_pitch_in_tile (120) ++ #define mask_of_reg_dnr_fb_pitch_in_tile (0xf) ++ unsigned int reg_dnr_fb_pitch_in_tile:4; ++ ++ // h003c, bit: 7 ++ /* DNR write dma miu high priority threshold*/ ++ #define offset_of_reg_dnr_wdma_pri_thd (120) ++ #define mask_of_reg_dnr_wdma_pri_thd (0xf0) ++ unsigned int reg_dnr_wdma_pri_thd:4; ++ ++ // h003c, bit: 11 ++ /* DNR read dma miu high priority threshold*/ ++ #define offset_of_reg_dnr_rdma_pri_thd (120) ++ #define mask_of_reg_dnr_rdma_pri_thd (0xf00) ++ unsigned int reg_dnr_rdma_pri_thd:4; ++ ++ // h003c, bit: 12 ++ /* DNR read dma miu high priority enable*/ ++ #define offset_of_reg_dnr_rdma_hpri_en (120) ++ #define mask_of_reg_dnr_rdma_hpri_en (0x1000) ++ unsigned int reg_dnr_rdma_hpri_en:1; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 0 ++ /* Motion (SAD) enable*/ ++ #define offset_of_reg_motion_en (122) ++ #define mask_of_reg_motion_en (0x1) ++ unsigned int reg_motion_en:1; ++ ++ // h003d, bit: 4 ++ /* Motion MIU store burst byte count ++ (1count=16bytes, MIU defaule=128 bytes)*/ ++ #define offset_of_reg_mot_burst_cnt (122) ++ #define mask_of_reg_mot_burst_cnt (0x1e) ++ unsigned int reg_mot_burst_cnt:4; ++ ++ // h003d, bit: 7 ++ /* */ ++ unsigned int :3; ++ ++ // h003d, bit: 14 ++ /* Motion threshold*/ ++ #define offset_of_reg_motion_thrd (122) ++ #define mask_of_reg_motion_thrd (0xff00) ++ unsigned int reg_motion_thrd:8; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* Motion frame buffer base address*/ ++ #define offset_of_reg_mot_fb_base (124) ++ #define mask_of_reg_mot_fb_base (0xffff) ++ unsigned int reg_mot_fb_base:16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 10 ++ /* Motion frame buffer base address*/ ++ #define offset_of_reg_mot_fb_base_1 (126) ++ #define mask_of_reg_mot_fb_base_1 (0x7ff) ++ unsigned int reg_mot_fb_base_1:11; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 14 ++ /* DNR dma write address upper bound*/ ++ #define offset_of_reg_dnr_wdma_uaddr (128) ++ #define mask_of_reg_dnr_wdma_uaddr (0xffff) ++ unsigned int reg_dnr_wdma_uaddr:16; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 10 ++ /* DNR dma write address upper bound*/ ++ #define offset_of_reg_dnr_wdma_uaddr_1 (130) ++ #define mask_of_reg_dnr_wdma_uaddr_1 (0x7ff) ++ unsigned int reg_dnr_wdma_uaddr_1:11; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0041, bit: 15 ++ /* DNR dma write address over upper bound (clear by reg_dnr_en)*/ ++ #define offset_of_reg_dnr_wdma_adr_over_max (130) ++ #define mask_of_reg_dnr_wdma_adr_over_max (0x8000) ++ unsigned int reg_dnr_wdma_adr_over_max:1; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 1 ++ /* DNR output frame selection: ++ 2'd0: Previous frame ++ 2'd1: Current frame ++ 2'd2: Debug data*/ ++ #define offset_of_reg_dnr_ofrm_sel (132) ++ #define mask_of_reg_dnr_ofrm_sel (0x3) ++ unsigned int reg_dnr_ofrm_sel:2; ++ ++ // h0042, bit: 2 ++ /* ROT output first frame selection: ++ 1'b0: Black frame ++ 1'b1: Current frame*/ ++ #define offset_of_reg_rot_ofrm_sel (132) ++ #define mask_of_reg_rot_ofrm_sel (0x4) ++ unsigned int reg_rot_ofrm_sel:1; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :13; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 0 ++ /* ROT enable*/ ++ #define offset_of_reg_rot_en (134) ++ #define mask_of_reg_rot_en (0x1) ++ unsigned int reg_rot_en:1; ++ ++ // h0043, bit: 4 ++ /* ROT output rate control */ ++ #define offset_of_reg_rot_rate_cyc (134) ++ #define mask_of_reg_rot_rate_cyc (0x1e) ++ unsigned int reg_rot_rate_cyc:4; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 14 ++ /* dnr wdma status*/ ++ #define offset_of_reg_dnr_wdma_status (136) ++ #define mask_of_reg_dnr_wdma_status (0xffff) ++ unsigned int reg_dnr_wdma_status:16; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 14 ++ /* dnr wdma status*/ ++ #define offset_of_reg_dnr_rdma_status (138) ++ #define mask_of_reg_dnr_rdma_status (0xffff) ++ unsigned int reg_dnr_rdma_status:16; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 7 ++ /* */ ++ unsigned int :8; ++ ++ // h0050, bit: 14 ++ /* AWB block row number for interrupt*/ ++ #define offset_of_reg_awb_int_row_num (160) ++ #define mask_of_reg_awb_int_row_num (0x7f00) ++ unsigned int reg_awb_int_row_num:7; ++ ++ // h0050, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 9 ++ /* AWB block width minus one*/ ++ #define offset_of_reg_awb_blksize_x_m1 (162) ++ #define mask_of_reg_awb_blksize_x_m1 (0x3ff) ++ unsigned int reg_awb_blksize_x_m1:10; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 9 ++ /* AWB block height minus one*/ ++ #define offset_of_reg_awb_blksize_y_m1 (164) ++ #define mask_of_reg_awb_blksize_y_m1 (0x3ff) ++ unsigned int reg_awb_blksize_y_m1:10; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 6 ++ /* AWB horizontal block number minus one*/ ++ #define offset_of_reg_awb_blknum_x_m1 (166) ++ #define mask_of_reg_awb_blknum_x_m1 (0x7f) ++ unsigned int reg_awb_blknum_x_m1:7; ++ ++ // h0053, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0053, bit: 14 ++ /* AWB vertical block number minus one*/ ++ #define offset_of_reg_awb_blknum_y_m1 (166) ++ #define mask_of_reg_awb_blknum_y_m1 (0x7f00) ++ unsigned int reg_awb_blknum_y_m1:7; ++ ++ // h0053, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 11 ++ /* AWB horizontal block pixel offset*/ ++ #define offset_of_reg_awb_blk_h_offset (168) ++ #define mask_of_reg_awb_blk_h_offset (0xfff) ++ unsigned int reg_awb_blk_h_offset:12; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 11 ++ /* AWB veritcal block pixel offset*/ ++ #define offset_of_reg_awb_blk_v_offset (170) ++ #define mask_of_reg_awb_blk_v_offset (0xfff) ++ unsigned int reg_awb_blk_v_offset:12; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 9 ++ /* AWB horizontal block pixel valid minus one*/ ++ #define offset_of_reg_awb_blk_valid_x_m1 (172) ++ #define mask_of_reg_awb_blk_valid_x_m1 (0x3ff) ++ unsigned int reg_awb_blk_valid_x_m1:10; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 9 ++ /* AWB vertical block pixel valid minus one*/ ++ #define offset_of_reg_awb_blk_valid_y_m1 (174) ++ #define mask_of_reg_awb_blk_valid_y_m1 (0x3ff) ++ unsigned int reg_awb_blk_valid_y_m1:10; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* AWB block average divisor A minus one*/ ++ #define offset_of_reg_awb_div_a_m1 (176) ++ #define mask_of_reg_awb_div_a_m1 (0xffff) ++ unsigned int reg_awb_div_a_m1:16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* AWB block average divisor B minus one*/ ++ #define offset_of_reg_awb_div_b_m1 (178) ++ #define mask_of_reg_awb_div_b_m1 (0xffff) ++ unsigned int reg_awb_div_b_m1:16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* AWB block average divisor C minus one*/ ++ #define offset_of_reg_awb_div_c_m1 (180) ++ #define mask_of_reg_awb_div_c_m1 (0xffff) ++ unsigned int reg_awb_div_c_m1:16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* AWB block average divisor D minus one*/ ++ #define offset_of_reg_awb_div_d_m1 (182) ++ #define mask_of_reg_awb_div_d_m1 (0xffff) ++ unsigned int reg_awb_div_d_m1:16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* AWB block average divisor E minus one*/ ++ #define offset_of_reg_awb_div_e_m1 (184) ++ #define mask_of_reg_awb_div_e_m1 (0xffff) ++ unsigned int reg_awb_div_e_m1:16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* AWB block average divisor F minus one*/ ++ #define offset_of_reg_awb_div_f_m1 (186) ++ #define mask_of_reg_awb_div_f_m1 (0xffff) ++ unsigned int reg_awb_div_f_m1:16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 3 ++ /* AWB accumulation shift register*/ ++ #define offset_of_reg_awb_acc_sft (188) ++ #define mask_of_reg_awb_acc_sft (0xf) ++ unsigned int reg_awb_acc_sft:4; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 1 ++ /* */ ++ unsigned int :2; ++ ++ // h0060, bit: 2 ++ /* Window0 histogram enable*/ ++ #define offset_of_reg_histo_win0_en (192) ++ #define mask_of_reg_histo_win0_en (0x4) ++ unsigned int reg_histo_win0_en:1; ++ ++ // h0060, bit: 3 ++ /* Window1 histogram enable*/ ++ #define offset_of_reg_histo_win1_en (192) ++ #define mask_of_reg_histo_win1_en (0x8) ++ unsigned int reg_histo_win1_en:1; ++ ++ // h0060, bit: 7 ++ /* */ ++ unsigned int :4; ++ ++ // h0060, bit: 14 ++ /* Histogram block row number for interrupt*/ ++ #define offset_of_reg_histo_int_row_num (192) ++ #define mask_of_reg_histo_int_row_num (0x7f00) ++ unsigned int reg_histo_int_row_num:7; ++ ++ // h0060, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 9 ++ /* Histogram block width minus one*/ ++ #define offset_of_reg_histo_blksize_x_m1 (194) ++ #define mask_of_reg_histo_blksize_x_m1 (0x3ff) ++ unsigned int reg_histo_blksize_x_m1:10; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 9 ++ /* Histogram block height minus one*/ ++ #define offset_of_reg_histo_blksize_y_m1 (196) ++ #define mask_of_reg_histo_blksize_y_m1 (0x3ff) ++ unsigned int reg_histo_blksize_y_m1:10; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 6 ++ /* Histogram horizontal block number minus one*/ ++ #define offset_of_reg_histo_blknum_x_m1 (198) ++ #define mask_of_reg_histo_blknum_x_m1 (0x7f) ++ unsigned int reg_histo_blknum_x_m1:7; ++ ++ // h0063, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0063, bit: 14 ++ /* Histogram vertical block number minus one*/ ++ #define offset_of_reg_histo_blknum_y_m1 (198) ++ #define mask_of_reg_histo_blknum_y_m1 (0x7f00) ++ unsigned int reg_histo_blknum_y_m1:7; ++ ++ // h0063, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 11 ++ /* Histogram horizontal block pixel offset*/ ++ #define offset_of_reg_histo_blk_h_offset (200) ++ #define mask_of_reg_histo_blk_h_offset (0xfff) ++ unsigned int reg_histo_blk_h_offset:12; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 11 ++ /* Histogram veritcal block pixel offset*/ ++ #define offset_of_reg_histo_blk_v_offset (202) ++ #define mask_of_reg_histo_blk_v_offset (0xfff) ++ unsigned int reg_histo_blk_v_offset:12; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* Histogram block average divisor A minus one*/ ++ #define offset_of_reg_histo_div_a_m1 (208) ++ #define mask_of_reg_histo_div_a_m1 (0xffff) ++ unsigned int reg_histo_div_a_m1:16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* Histogram block average divisor B minus one*/ ++ #define offset_of_reg_histo_div_b_m1 (210) ++ #define mask_of_reg_histo_div_b_m1 (0xffff) ++ unsigned int reg_histo_div_b_m1:16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* Histogram block average divisor C minus one*/ ++ #define offset_of_reg_histo_div_c_m1 (212) ++ #define mask_of_reg_histo_div_c_m1 (0xffff) ++ unsigned int reg_histo_div_c_m1:16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* Histogram block average divisor D minus one*/ ++ #define offset_of_reg_histo_div_d_m1 (214) ++ #define mask_of_reg_histo_div_d_m1 (0xffff) ++ unsigned int reg_histo_div_d_m1:16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* Histogram block average divisor E minus one*/ ++ #define offset_of_reg_histo_div_e_m1 (216) ++ #define mask_of_reg_histo_div_e_m1 (0xffff) ++ unsigned int reg_histo_div_e_m1:16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* Histogram block average divisor F minus one*/ ++ #define offset_of_reg_histo_div_f_m1 (218) ++ #define mask_of_reg_histo_div_f_m1 (0xffff) ++ unsigned int reg_histo_div_f_m1:16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 3 ++ /* Histogram accumulation shift register*/ ++ #define offset_of_reg_histo_acc_sft (220) ++ #define mask_of_reg_histo_acc_sft (0xf) ++ unsigned int reg_histo_acc_sft:4; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 6 ++ /* Horizontal block offset of histogram window0*/ ++ #define offset_of_reg_histo_stawin_x_offset_0 (224) ++ #define mask_of_reg_histo_stawin_x_offset_0 (0x7f) ++ unsigned int reg_histo_stawin_x_offset_0:7; ++ ++ // h0070, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0070, bit: 14 ++ /* Horizontal block number minus one of histogram window0*/ ++ #define offset_of_reg_histo_stawin_x_size_m1_0 (224) ++ #define mask_of_reg_histo_stawin_x_size_m1_0 (0x7f00) ++ unsigned int reg_histo_stawin_x_size_m1_0:7; ++ ++ // h0070, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 6 ++ /* Vertical block offset of histogram window0*/ ++ #define offset_of_reg_histo_stawin_y_offset_0 (226) ++ #define mask_of_reg_histo_stawin_y_offset_0 (0x7f) ++ unsigned int reg_histo_stawin_y_offset_0:7; ++ ++ // h0071, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0071, bit: 14 ++ /* Vertical block number minus one of histogram window0*/ ++ #define offset_of_reg_histo_stawin_y_size_m1_0 (226) ++ #define mask_of_reg_histo_stawin_y_size_m1_0 (0x7f00) ++ unsigned int reg_histo_stawin_y_size_m1_0:7; ++ ++ // h0071, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 6 ++ /* Horizontal block offset of histogram window1*/ ++ #define offset_of_reg_histo_stawin_x_offset_1 (228) ++ #define mask_of_reg_histo_stawin_x_offset_1 (0x7f) ++ unsigned int reg_histo_stawin_x_offset_1:7; ++ ++ // h0072, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0072, bit: 14 ++ /* Horizontal block number minus one of histogram window1*/ ++ #define offset_of_reg_histo_stawin_x_size_m1_1 (228) ++ #define mask_of_reg_histo_stawin_x_size_m1_1 (0x7f00) ++ unsigned int reg_histo_stawin_x_size_m1_1:7; ++ ++ // h0072, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 6 ++ /* Vertical block offset of histogram window1*/ ++ #define offset_of_reg_histo_stawin_y_offset_1 (230) ++ #define mask_of_reg_histo_stawin_y_offset_1 (0x7f) ++ unsigned int reg_histo_stawin_y_offset_1:7; ++ ++ // h0073, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0073, bit: 14 ++ /* Vertical block number minus one of histogram window1*/ ++ #define offset_of_reg_histo_stawin_y_size_m1_1 (230) ++ #define mask_of_reg_histo_stawin_y_size_m1_1 (0x7f00) ++ unsigned int reg_histo_stawin_y_size_m1_1:7; ++ ++ // h0073, bit: 15 ++ /* */ ++ unsigned int :1; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 0 ++ /* Histogram window0 roi mode*/ ++ #define offset_of_reg_histo_roi_0_mode (232) ++ #define mask_of_reg_histo_roi_0_mode (0x1) ++ unsigned int reg_histo_roi_0_mode:1; ++ ++ // h0074, bit: 1 ++ /* Histogram window1 roi mode*/ ++ #define offset_of_reg_histo_roi_1_mode (232) ++ #define mask_of_reg_histo_roi_1_mode (0x2) ++ unsigned int reg_histo_roi_1_mode:1; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 3 ++ /* AE source selection ++ 4'b0000: from wb pre-gain ++ 4'b0001: from wb pre-gain multiply LS gain ++ 4'b0010: from wb pre-gain multiply CS gain ++ 4'b0011: from wb pre-gain multiply LS and CS gain ++ 4'b0100: from wb pre-gain multiply post-WB gain ++ 4'b0101: from wb pre-gain multiply LS and post-WB gain ++ 4'b0110: from wb pre-gain multiply CS and post-WB gain ++ 4'b0111: from wb pre-gain multiply LS, CS and post-WB ++ gain ++ 4'b1000: from CS output ++ 4'b1100: from WB post-gain output*/ ++ #define offset_of_reg_isp_ae_in_mode (234) ++ #define mask_of_reg_isp_ae_in_mode (0xf) ++ unsigned int reg_isp_ae_in_mode:4; ++ ++ // h0075, bit: 7 ++ /* AWB source selection ++ 4'b0000: from wb pre-gain ++ 4'b0001: from wb pre-gain multiply LS gain ++ 4'b0010: from wb pre-gain multiply CS gain ++ 4'b0011: from wb pre-gain multiply LS and CS gain ++ 4'b1000: from CS output*/ ++ #define offset_of_reg_isp_awb_in_mode (234) ++ #define mask_of_reg_isp_awb_in_mode (0xf0) ++ unsigned int reg_isp_awb_in_mode:4; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp3; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp4.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp4.h +new file mode 100644 +index 00000000..d8e0c075 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp4.h +@@ -0,0 +1,1102 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP4__ ++#define __INFINITY3E_REG_ISP4__ ++typedef struct { ++ // h0000, bit: 3 ++ /* Load to the needed sram id*/ ++ #define offset_of_reg_isp_load_sram_id (0) ++ #define mask_of_reg_isp_load_sram_id (0xf) ++ unsigned int reg_isp_load_sram_id:4; ++ ++ // h0000, bit: 7 ++ /* Read the needed sram data*/ ++ #define offset_of_reg_isp_sram_read_id (0) ++ #define mask_of_reg_isp_sram_read_id (0xf0) ++ unsigned int reg_isp_sram_read_id:4; ++ ++ // h0000, bit: 8 ++ /* Read or write srams. 1: write*/ ++ #define offset_of_reg_isp_sram_rw (0) ++ #define mask_of_reg_isp_sram_rw (0x100) ++ unsigned int reg_isp_sram_rw:1; ++ ++ // h0000, bit: 9 ++ /* Enable miu loader. 1: enable*/ ++ #define offset_of_reg_isp_miu2sram_en (0) ++ #define mask_of_reg_isp_miu2sram_en (0x200) ++ unsigned int reg_isp_miu2sram_en:1; ++ ++ // h0000, bit: 10 ++ /* If it is full, the bit is 0 (16 entries)*/ ++ #define offset_of_reg_isp_load_register_non_full (0) ++ #define mask_of_reg_isp_load_register_non_full (0x400) ++ unsigned int reg_isp_load_register_non_full:1; ++ ++ // h0000, bit: 11 ++ /* 1: load done*/ ++ #define offset_of_reg_isp_load_done (0) ++ #define mask_of_reg_isp_load_done (0x800) ++ unsigned int reg_isp_load_done:1; ++ ++ // h0000, bit: 12 ++ /* 1: wait hardware not busy*/ ++ #define offset_of_reg_isp_load_wait_hardware_ready_en (0) ++ #define mask_of_reg_isp_load_wait_hardware_ready_en (0x1000) ++ unsigned int reg_isp_load_wait_hardware_ready_en:1; ++ ++ // h0000, bit: 14 ++ /* 0: wait fifo space == 4, 1: wait space == 8, 2: wait space == 12, 3: wait fifo empty (16)*/ ++ #define offset_of_reg_isp_load_water_level (0) ++ #define mask_of_reg_isp_load_water_level (0x6000) ++ unsigned int reg_isp_load_water_level:2; ++ ++ // h0000, bit: 15 ++ /* 0: software reset*/ ++ #define offset_of_reg_isp_load_sw_rst (0) ++ #define mask_of_reg_isp_load_sw_rst (0x8000) ++ unsigned int reg_isp_load_sw_rst:1; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 14 ++ /* How many 16-bits data minus one*/ ++ #define offset_of_reg_isp_load_amount (2) ++ #define mask_of_reg_isp_load_amount (0xffff) ++ unsigned int reg_isp_load_amount:16; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 14 ++ /* Load data from the sram address*/ ++ #define offset_of_reg_isp_sram_st_addr (4) ++ #define mask_of_reg_isp_sram_st_addr (0xffff) ++ unsigned int reg_isp_sram_st_addr:16; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 14 ++ /* Load data from MIU 16-byte address*/ ++ #define offset_of_reg_isp_load_st_addr (6) ++ #define mask_of_reg_isp_load_st_addr (0xffff) ++ unsigned int reg_isp_load_st_addr:16; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 14 ++ /* Load data from MIU 16-byte address*/ ++ #define offset_of_reg_isp_load_st_addr_1 (8) ++ #define mask_of_reg_isp_load_st_addr_1 (0xffff) ++ unsigned int reg_isp_load_st_addr_1:16; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 14 ++ /* Read sram data from set address from set sram*/ ++ #define offset_of_reg_isp_sram_rd_addr (10) ++ #define mask_of_reg_isp_sram_rd_addr (0xffff) ++ unsigned int reg_isp_sram_rd_addr:16; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 14 ++ /* Sram read data from corresponding address and sram*/ ++ #define offset_of_reg_isp_sram_read_data (12) ++ #define mask_of_reg_isp_sram_read_data (0xffff) ++ unsigned int reg_isp_sram_read_data:16; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 0 ++ /* Fire write register control into register queue*/ ++ #define offset_of_reg_isp_load_register_w1r (14) ++ #define mask_of_reg_isp_load_register_w1r (0x1) ++ unsigned int reg_isp_load_register_w1r:1; ++ ++ // h0007, bit: 1 ++ /* Fire load sram*/ ++ #define offset_of_reg_isp_load_st_w1r (14) ++ #define mask_of_reg_isp_load_st_w1r (0x2) ++ unsigned int reg_isp_load_st_w1r:1; ++ ++ // h0007, bit: 2 ++ /* Fire read sram*/ ++ #define offset_of_reg_isp_sram_read_w1r (14) ++ #define mask_of_reg_isp_sram_read_w1r (0x4) ++ unsigned int reg_isp_sram_read_w1r:1; ++ ++ // h0007, bit: 3 ++ /* clear error flag*/ ++ #define offset_of_reg_isp_load_start_error_clear_w1r (14) ++ #define mask_of_reg_isp_load_start_error_clear_w1r (0x8) ++ unsigned int reg_isp_load_start_error_clear_w1r:1; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 0 ++ /* 1: Frame start when loading is not finished yet*/ ++ #define offset_of_reg_isp_load_start_error (16) ++ #define mask_of_reg_isp_load_start_error (0x1) ++ unsigned int reg_isp_load_start_error:1; ++ ++ // h0008, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 0 ++ /* fpn enable*/ ++ #define offset_of_reg_fpn_en (128) ++ #define mask_of_reg_fpn_en (0x1) ++ unsigned int reg_fpn_en:1; ++ ++ // h0040, bit: 1 ++ /* 0: statis for every frame set 1: statis for just first frame set*/ ++ #define offset_of_reg_fpn_mode (128) ++ #define mask_of_reg_fpn_mode (0x2) ++ unsigned int reg_fpn_mode:1; ++ ++ // h0040, bit: 2 ++ /* 0:don’t clear sum result 1: clear sum result*/ ++ #define offset_of_reg_fpn_sum_clr (128) ++ #define mask_of_reg_fpn_sum_clr (0x4) ++ unsigned int reg_fpn_sum_clr:1; ++ ++ // h0040, bit: 3 ++ /* SW setting eable*/ ++ #define offset_of_reg_sw_offset_on (128) ++ #define mask_of_reg_sw_offset_on (0x8) ++ unsigned int reg_sw_offset_on:1; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 11 ++ /* ob start x */ ++ #define offset_of_reg_fpn_start_x (130) ++ #define mask_of_reg_fpn_start_x (0xfff) ++ unsigned int reg_fpn_start_x:12; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 11 ++ /* ob start xy*/ ++ #define offset_of_reg_fpn_start_y (132) ++ #define mask_of_reg_fpn_start_y (0xfff) ++ unsigned int reg_fpn_start_y:12; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 11 ++ /* ob width*/ ++ #define offset_of_reg_fpn_width (134) ++ #define mask_of_reg_fpn_width (0xfff) ++ unsigned int reg_fpn_width:12; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 4 ++ /* ob height*/ ++ #define offset_of_reg_fpn_height (136) ++ #define mask_of_reg_fpn_height (0x1f) ++ unsigned int reg_fpn_height:5; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 14 ++ /* pre-offset for pixels at active area*/ ++ #define offset_of_reg_fpn_preoffset (138) ++ #define mask_of_reg_fpn_preoffset (0x7fff) ++ unsigned int reg_fpn_preoffset:15; ++ ++ // h0045, bit: 15 ++ /* sign of pre-offset */ ++ #define offset_of_reg_fpn_preoffset_sign (138) ++ #define mask_of_reg_fpn_preoffset_sign (0x8000) ++ unsigned int reg_fpn_preoffset_sign:1; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 14 ++ /* midium pixel and pavg diff threshould*/ ++ #define offset_of_reg_fpn_diff_th (140) ++ #define mask_of_reg_fpn_diff_th (0xffff) ++ unsigned int reg_fpn_diff_th:16; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 11 ++ /* compare ratio*/ ++ #define offset_of_reg_fpn_cmp_ratio (142) ++ #define mask_of_reg_fpn_cmp_ratio (0xfff) ++ unsigned int reg_fpn_cmp_ratio:12; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 4 ++ /* statis frame number*/ ++ #define offset_of_reg_fpn_frame_num (144) ++ #define mask_of_reg_fpn_frame_num (0x1f) ++ unsigned int reg_fpn_frame_num:5; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 14 ++ /* SW offset setting write data*/ ++ #define offset_of_reg_sw_offset_wd (146) ++ #define mask_of_reg_sw_offset_wd (0xffff) ++ unsigned int reg_sw_offset_wd:16; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 11 ++ /* SW offset setting write address*/ ++ #define offset_of_reg_sw_offset_a (148) ++ #define mask_of_reg_sw_offset_a (0xfff) ++ unsigned int reg_sw_offset_a:12; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 0 ++ /* SW offset setting write control*/ ++ #define offset_of_reg_sw_offset_we (150) ++ #define mask_of_reg_sw_offset_we (0x1) ++ unsigned int reg_sw_offset_we:1; ++ ++ // h004b, bit: 1 ++ /* SW setting eable*/ ++ #define offset_of_reg_sw_offset_re (150) ++ #define mask_of_reg_sw_offset_re (0x2) ++ unsigned int reg_sw_offset_re:1; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 14 ++ /* SW setting read data*/ ++ #define offset_of_reg_sw_offset_rd (152) ++ #define mask_of_reg_sw_offset_rd (0xffff) ++ unsigned int reg_sw_offset_rd:16; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp4; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp5.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp5.h +new file mode 100644 +index 00000000..8232b9e0 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp5.h +@@ -0,0 +1,1448 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP5__ ++#define __INFINITY3E_REG_ISP5__ ++typedef struct { ++ // h0000, bit: 1 ++ /* */ ++ #define offset_of_reg_statis_af_mi_lenx4 (0) ++ #define mask_of_reg_statis_af_mi_lenx4 (0x3) ++ unsigned int reg_statis_af_mi_lenx4:2; ++ ++ // h0000, bit: 7 ++ /* */ ++ #define offset_of_reg_statis_af_mi_mask_cyclex16 (0) ++ #define mask_of_reg_statis_af_mi_mask_cyclex16 (0xfc) ++ unsigned int reg_statis_af_mi_mask_cyclex16:6; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 0 ++ /* */ ++ #define offset_of_reg_af_kr_sign (2) ++ #define mask_of_reg_af_kr_sign (0x1) ++ unsigned int reg_af_kr_sign:1; ++ ++ // h0001, bit: 1 ++ /* */ ++ #define offset_of_reg_af_kgr_sign (2) ++ #define mask_of_reg_af_kgr_sign (0x2) ++ unsigned int reg_af_kgr_sign:1; ++ ++ // h0001, bit: 2 ++ /* */ ++ #define offset_of_reg_af_kgb_sign (2) ++ #define mask_of_reg_af_kgb_sign (0x4) ++ unsigned int reg_af_kgb_sign:1; ++ ++ // h0001, bit: 3 ++ /* */ ++ #define offset_of_reg_af_kb_sign (2) ++ #define mask_of_reg_af_kb_sign (0x8) ++ unsigned int reg_af_kb_sign:1; ++ ++ // h0001, bit: 4 ++ /* */ ++ #define offset_of_reg_rgbir2x2_g_loc (2) ++ #define mask_of_reg_rgbir2x2_g_loc (0x10) ++ unsigned int reg_rgbir2x2_g_loc:1; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 7 ++ /* */ ++ #define offset_of_reg_af_kr_value (4) ++ #define mask_of_reg_af_kr_value (0xff) ++ unsigned int reg_af_kr_value:8; ++ ++ // h0002, bit: 14 ++ /* */ ++ #define offset_of_reg_af_kgr_value (4) ++ #define mask_of_reg_af_kgr_value (0xff00) ++ unsigned int reg_af_kgr_value:8; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 7 ++ /* */ ++ #define offset_of_reg_af_kgb_value (6) ++ #define mask_of_reg_af_kgb_value (0xff) ++ unsigned int reg_af_kgb_value:8; ++ ++ // h0003, bit: 14 ++ /* */ ++ #define offset_of_reg_af_kb_value (6) ++ #define mask_of_reg_af_kb_value (0xff00) ++ unsigned int reg_af_kb_value:8; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 0 ++ /* */ ++ #define offset_of_reg_high_image_pipe_en (8) ++ #define mask_of_reg_high_image_pipe_en (0x1) ++ unsigned int reg_high_image_pipe_en:1; ++ ++ // h0004, bit: 1 ++ /* */ ++ #define offset_of_reg_low_image_pipe_en (8) ++ #define mask_of_reg_low_image_pipe_en (0x2) ++ unsigned int reg_low_image_pipe_en:1; ++ ++ // h0004, bit: 2 ++ /* */ ++ #define offset_of_reg_luma_image_pipe_en (8) ++ #define mask_of_reg_luma_image_pipe_en (0x4) ++ unsigned int reg_luma_image_pipe_en:1; ++ ++ // h0004, bit: 3 ++ /* */ ++ #define offset_of_reg_sobelv_en (8) ++ #define mask_of_reg_sobelv_en (0x8) ++ unsigned int reg_sobelv_en:1; ++ ++ // h0004, bit: 4 ++ /* */ ++ #define offset_of_reg_sobelh_en (8) ++ #define mask_of_reg_sobelh_en (0x10) ++ unsigned int reg_sobelh_en:1; ++ ++ // h0004, bit: 5 ++ /* */ ++ #define offset_of_reg_high_iir_mem_frame_clr (8) ++ #define mask_of_reg_high_iir_mem_frame_clr (0x20) ++ unsigned int reg_high_iir_mem_frame_clr:1; ++ ++ // h0004, bit: 6 ++ /* */ ++ #define offset_of_reg_low_iir_mem_frame_clr (8) ++ #define mask_of_reg_low_iir_mem_frame_clr (0x40) ++ unsigned int reg_low_iir_mem_frame_clr:1; ++ ++ // h0004, bit: 14 ++ /* */ ++ unsigned int :9; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 9 ++ /* */ ++ #define offset_of_reg_high_1st_low_clip (10) ++ #define mask_of_reg_high_1st_low_clip (0x3ff) ++ unsigned int reg_high_1st_low_clip:10; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 9 ++ /* */ ++ #define offset_of_reg_high_1st_high_clip (12) ++ #define mask_of_reg_high_1st_high_clip (0x3ff) ++ unsigned int reg_high_1st_high_clip:10; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 9 ++ /* */ ++ #define offset_of_reg_high_iir_b0 (14) ++ #define mask_of_reg_high_iir_b0 (0x3ff) ++ unsigned int reg_high_iir_b0:10; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 10 ++ /* */ ++ #define offset_of_reg_high_iir_b1 (16) ++ #define mask_of_reg_high_iir_b1 (0x7ff) ++ unsigned int reg_high_iir_b1:11; ++ ++ // h0008, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 9 ++ /* */ ++ #define offset_of_reg_high_iir_b2 (18) ++ #define mask_of_reg_high_iir_b2 (0x3ff) ++ unsigned int reg_high_iir_b2:10; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 7 ++ /* */ ++ #define offset_of_reg_high_iir_a1 (20) ++ #define mask_of_reg_high_iir_a1 (0xff) ++ unsigned int reg_high_iir_a1:8; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 7 ++ /* */ ++ #define offset_of_reg_high_iir_a2 (22) ++ #define mask_of_reg_high_iir_a2 (0xff) ++ unsigned int reg_high_iir_a2:8; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 9 ++ /* */ ++ #define offset_of_reg_high_2nd_low_clip (24) ++ #define mask_of_reg_high_2nd_low_clip (0x3ff) ++ unsigned int reg_high_2nd_low_clip:10; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 9 ++ /* */ ++ #define offset_of_reg_high_2nd_high_clip (26) ++ #define mask_of_reg_high_2nd_high_clip (0x3ff) ++ unsigned int reg_high_2nd_high_clip:10; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af0_h_start (28) ++ #define mask_of_reg_high_af0_h_start (0xfff) ++ unsigned int reg_high_af0_h_start:12; ++ ++ // h000e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af0_h_end (30) ++ #define mask_of_reg_high_af0_h_end (0xfff) ++ unsigned int reg_high_af0_h_end:12; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af0_v_start (32) ++ #define mask_of_reg_high_af0_v_start (0xfff) ++ unsigned int reg_high_af0_v_start:12; ++ ++ // h0010, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af0_v_end (34) ++ #define mask_of_reg_high_af0_v_end (0xfff) ++ unsigned int reg_high_af0_v_end:12; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af1_h_start (36) ++ #define mask_of_reg_high_af1_h_start (0xfff) ++ unsigned int reg_high_af1_h_start:12; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af1_h_end (38) ++ #define mask_of_reg_high_af1_h_end (0xfff) ++ unsigned int reg_high_af1_h_end:12; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af1_v_start (40) ++ #define mask_of_reg_high_af1_v_start (0xfff) ++ unsigned int reg_high_af1_v_start:12; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af1_v_end (42) ++ #define mask_of_reg_high_af1_v_end (0xfff) ++ unsigned int reg_high_af1_v_end:12; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af2_h_start (44) ++ #define mask_of_reg_high_af2_h_start (0xfff) ++ unsigned int reg_high_af2_h_start:12; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af2_h_end (46) ++ #define mask_of_reg_high_af2_h_end (0xfff) ++ unsigned int reg_high_af2_h_end:12; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af2_v_start (48) ++ #define mask_of_reg_high_af2_v_start (0xfff) ++ unsigned int reg_high_af2_v_start:12; ++ ++ // h0018, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af2_v_end (50) ++ #define mask_of_reg_high_af2_v_end (0xfff) ++ unsigned int reg_high_af2_v_end:12; ++ ++ // h0019, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af3_h_start (52) ++ #define mask_of_reg_high_af3_h_start (0xfff) ++ unsigned int reg_high_af3_h_start:12; ++ ++ // h001a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af3_h_end (54) ++ #define mask_of_reg_high_af3_h_end (0xfff) ++ unsigned int reg_high_af3_h_end:12; ++ ++ // h001b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af3_v_start (56) ++ #define mask_of_reg_high_af3_v_start (0xfff) ++ unsigned int reg_high_af3_v_start:12; ++ ++ // h001c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af3_v_end (58) ++ #define mask_of_reg_high_af3_v_end (0xfff) ++ unsigned int reg_high_af3_v_end:12; ++ ++ // h001d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af4_h_start (60) ++ #define mask_of_reg_high_af4_h_start (0xfff) ++ unsigned int reg_high_af4_h_start:12; ++ ++ // h001e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af4_h_end (62) ++ #define mask_of_reg_high_af4_h_end (0xfff) ++ unsigned int reg_high_af4_h_end:12; ++ ++ // h001f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af4_v_start (64) ++ #define mask_of_reg_high_af4_v_start (0xfff) ++ unsigned int reg_high_af4_v_start:12; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af4_v_end (66) ++ #define mask_of_reg_high_af4_v_end (0xfff) ++ unsigned int reg_high_af4_v_end:12; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af5_h_start (68) ++ #define mask_of_reg_high_af5_h_start (0xfff) ++ unsigned int reg_high_af5_h_start:12; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af5_h_end (70) ++ #define mask_of_reg_high_af5_h_end (0xfff) ++ unsigned int reg_high_af5_h_end:12; ++ ++ // h0023, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af5_v_start (72) ++ #define mask_of_reg_high_af5_v_start (0xfff) ++ unsigned int reg_high_af5_v_start:12; ++ ++ // h0024, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af5_v_end (74) ++ #define mask_of_reg_high_af5_v_end (0xfff) ++ unsigned int reg_high_af5_v_end:12; ++ ++ // h0025, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af6_h_start (76) ++ #define mask_of_reg_high_af6_h_start (0xfff) ++ unsigned int reg_high_af6_h_start:12; ++ ++ // h0026, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af6_h_end (78) ++ #define mask_of_reg_high_af6_h_end (0xfff) ++ unsigned int reg_high_af6_h_end:12; ++ ++ // h0027, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af6_v_start (80) ++ #define mask_of_reg_high_af6_v_start (0xfff) ++ unsigned int reg_high_af6_v_start:12; ++ ++ // h0028, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af6_v_end (82) ++ #define mask_of_reg_high_af6_v_end (0xfff) ++ unsigned int reg_high_af6_v_end:12; ++ ++ // h0029, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af7_h_start (84) ++ #define mask_of_reg_high_af7_h_start (0xfff) ++ unsigned int reg_high_af7_h_start:12; ++ ++ // h002a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af7_h_end (86) ++ #define mask_of_reg_high_af7_h_end (0xfff) ++ unsigned int reg_high_af7_h_end:12; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af7_v_start (88) ++ #define mask_of_reg_high_af7_v_start (0xfff) ++ unsigned int reg_high_af7_v_start:12; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af7_v_end (90) ++ #define mask_of_reg_high_af7_v_end (0xfff) ++ unsigned int reg_high_af7_v_end:12; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af8_h_start (92) ++ #define mask_of_reg_high_af8_h_start (0xfff) ++ unsigned int reg_high_af8_h_start:12; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af8_h_end (94) ++ #define mask_of_reg_high_af8_h_end (0xfff) ++ unsigned int reg_high_af8_h_end:12; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af8_v_start (96) ++ #define mask_of_reg_high_af8_v_start (0xfff) ++ unsigned int reg_high_af8_v_start:12; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af8_v_end (98) ++ #define mask_of_reg_high_af8_v_end (0xfff) ++ unsigned int reg_high_af8_v_end:12; ++ ++ // h0031, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af9_h_start (100) ++ #define mask_of_reg_high_af9_h_start (0xfff) ++ unsigned int reg_high_af9_h_start:12; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af9_h_end (102) ++ #define mask_of_reg_high_af9_h_end (0xfff) ++ unsigned int reg_high_af9_h_end:12; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af9_v_start (104) ++ #define mask_of_reg_high_af9_v_start (0xfff) ++ unsigned int reg_high_af9_v_start:12; ++ ++ // h0034, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 11 ++ /* */ ++ #define offset_of_reg_high_af9_v_end (106) ++ #define mask_of_reg_high_af9_v_end (0xfff) ++ unsigned int reg_high_af9_v_end:12; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 9 ++ /* */ ++ #define offset_of_reg_low_1st_low_clip (108) ++ #define mask_of_reg_low_1st_low_clip (0x3ff) ++ unsigned int reg_low_1st_low_clip:10; ++ ++ // h0036, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 9 ++ /* */ ++ #define offset_of_reg_low_1st_high_clip (110) ++ #define mask_of_reg_low_1st_high_clip (0x3ff) ++ unsigned int reg_low_1st_high_clip:10; ++ ++ // h0037, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 9 ++ /* */ ++ #define offset_of_reg_low_iir_b0 (112) ++ #define mask_of_reg_low_iir_b0 (0x3ff) ++ unsigned int reg_low_iir_b0:10; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 10 ++ /* */ ++ #define offset_of_reg_low_iir_b1 (114) ++ #define mask_of_reg_low_iir_b1 (0x7ff) ++ unsigned int reg_low_iir_b1:11; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 9 ++ /* */ ++ #define offset_of_reg_low_iir_b2 (116) ++ #define mask_of_reg_low_iir_b2 (0x3ff) ++ unsigned int reg_low_iir_b2:10; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 7 ++ /* */ ++ #define offset_of_reg_low_iir_a1 (118) ++ #define mask_of_reg_low_iir_a1 (0xff) ++ unsigned int reg_low_iir_a1:8; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 7 ++ /* */ ++ #define offset_of_reg_low_iir_a2 (120) ++ #define mask_of_reg_low_iir_a2 (0xff) ++ unsigned int reg_low_iir_a2:8; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 9 ++ /* */ ++ #define offset_of_reg_low_2nd_low_clip (122) ++ #define mask_of_reg_low_2nd_low_clip (0x3ff) ++ unsigned int reg_low_2nd_low_clip:10; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 9 ++ /* */ ++ #define offset_of_reg_low_2nd_high_clip (124) ++ #define mask_of_reg_low_2nd_high_clip (0x3ff) ++ unsigned int reg_low_2nd_high_clip:10; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 9 ++ /* */ ++ #define offset_of_reg_luma_low_clip (126) ++ #define mask_of_reg_luma_low_clip (0x3ff) ++ unsigned int reg_luma_low_clip:10; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 9 ++ /* */ ++ #define offset_of_reg_luma_high_clip (128) ++ #define mask_of_reg_luma_high_clip (0x3ff) ++ unsigned int reg_luma_high_clip:10; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelv_1st_low_clip (130) ++ #define mask_of_reg_sobelv_1st_low_clip (0x3ff) ++ unsigned int reg_sobelv_1st_low_clip:10; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelv_1st_high_clip (132) ++ #define mask_of_reg_sobelv_1st_high_clip (0x3ff) ++ unsigned int reg_sobelv_1st_high_clip:10; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelv_2nd_low_clip (134) ++ #define mask_of_reg_sobelv_2nd_low_clip (0x3ff) ++ unsigned int reg_sobelv_2nd_low_clip:10; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelv_2nd_high_clip (136) ++ #define mask_of_reg_sobelv_2nd_high_clip (0x3ff) ++ unsigned int reg_sobelv_2nd_high_clip:10; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelh_1st_low_clip (138) ++ #define mask_of_reg_sobelh_1st_low_clip (0x3ff) ++ unsigned int reg_sobelh_1st_low_clip:10; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelh_1st_high_clip (140) ++ #define mask_of_reg_sobelh_1st_high_clip (0x3ff) ++ unsigned int reg_sobelh_1st_high_clip:10; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelh_2nd_low_clip (142) ++ #define mask_of_reg_sobelh_2nd_low_clip (0x3ff) ++ unsigned int reg_sobelh_2nd_low_clip:10; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 9 ++ /* */ ++ #define offset_of_reg_sobelh_2nd_high_clip (144) ++ #define mask_of_reg_sobelh_2nd_high_clip (0x3ff) ++ unsigned int reg_sobelh_2nd_high_clip:10; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 14 ++ /* */ ++ #define offset_of_reg_af_dma_addr (146) ++ #define mask_of_reg_af_dma_addr (0xffff) ++ unsigned int reg_af_dma_addr:16; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 10 ++ /* */ ++ #define offset_of_reg_af_dma_addr_1 (148) ++ #define mask_of_reg_af_dma_addr_1 (0x7ff) ++ unsigned int reg_af_dma_addr_1:11; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 14 ++ /* */ ++ #define offset_of_reg_af_max_wadr (150) ++ #define mask_of_reg_af_max_wadr (0xffff) ++ unsigned int reg_af_max_wadr:16; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 10 ++ /* */ ++ #define offset_of_reg_af_max_wadr_1 (152) ++ #define mask_of_reg_af_max_wadr_1 (0x7ff) ++ unsigned int reg_af_max_wadr_1:11; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 0 ++ /* */ ++ #define offset_of_reg_af_filter_int (154) ++ #define mask_of_reg_af_filter_int (0x1) ++ unsigned int reg_af_filter_int:1; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp5; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp6.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp6.h +new file mode 100644 +index 00000000..e12866a8 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp6.h +@@ -0,0 +1,1580 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP6__ ++#define __INFINITY3E_REG_ISP6__ ++typedef struct { ++ // h0000, bit: 0 ++ /* ISP RDMA enable*/ ++ #define offset_of_reg_isp_rdma_en (0) ++ #define mask_of_reg_isp_rdma_en (0x1) ++ unsigned int reg_isp_rdma_en:1; ++ ++ // h0000, bit: 1 ++ /* */ ++ unsigned int :1; ++ ++ // h0000, bit: 2 ++ /* ISP DMA ring buffer mode enable*/ ++ #define offset_of_reg_isp_dma_ring_buf_en (0) ++ #define mask_of_reg_isp_dma_ring_buf_en (0x4) ++ unsigned int reg_isp_dma_ring_buf_en:1; ++ ++ // h0000, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h0000, bit: 4 ++ /* ISP RDMA auto vsync trigger mode*/ ++ #define offset_of_reg_isp_rdma_auto (0) ++ #define mask_of_reg_isp_rdma_auto (0x10) ++ unsigned int reg_isp_rdma_auto:1; ++ ++ // h0000, bit: 6 ++ /* */ ++ unsigned int :2; ++ ++ // h0000, bit: 7 ++ /* ISP RDMA high priority set*/ ++ #define offset_of_reg_isp_rdma_rreq_hpri_set (0) ++ #define mask_of_reg_isp_rdma_rreq_hpri_set (0x80) ++ unsigned int reg_isp_rdma_rreq_hpri_set:1; ++ ++ // h0000, bit: 9 ++ /* ISP RDMA depack mode: ++ 2'd0: 8-bit ++ 2'd1: 10-bit ++ 2'd2: 16-bit ++ 2'd3: 12-bit*/ ++ #define offset_of_reg_isp_rdma_mode (0) ++ #define mask_of_reg_isp_rdma_mode (0x300) ++ unsigned int reg_isp_rdma_mode:2; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0000, bit: 15 ++ /* ISP RDMA MIU request reset*/ ++ #define offset_of_reg_isp_rdma_rreq_rst (0) ++ #define mask_of_reg_isp_rdma_rreq_rst (0x8000) ++ unsigned int reg_isp_rdma_rreq_rst:1; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 11 ++ /* ISP RDMA pitch*/ ++ #define offset_of_reg_isp_rdma_pitch (2) ++ #define mask_of_reg_isp_rdma_pitch (0xfff) ++ unsigned int reg_isp_rdma_pitch:12; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 3 ++ /* Ring buffer of 2^(ring_buf_sz+1) lines memory space (2~1024 lines)*/ ++ #define offset_of_reg_isp_dma_ring_buf_sz (4) ++ #define mask_of_reg_isp_dma_ring_buf_sz (0xf) ++ unsigned int reg_isp_dma_ring_buf_sz:4; ++ ++ // h0002, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 14 ++ /* ISP RDMA MIU base address*/ ++ #define offset_of_reg_isp_rdma_base (16) ++ #define mask_of_reg_isp_rdma_base (0xffff) ++ unsigned int reg_isp_rdma_base:16; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 10 ++ /* ISP RDMA MIU base address*/ ++ #define offset_of_reg_isp_rdma_base_1 (18) ++ #define mask_of_reg_isp_rdma_base_1 (0x7ff) ++ unsigned int reg_isp_rdma_base_1:11; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 2 ++ /* ISP RDMA MIU request threshold*/ ++ #define offset_of_reg_isp_rdma_rreq_thrd (24) ++ #define mask_of_reg_isp_rdma_rreq_thrd (0x7) ++ unsigned int reg_isp_rdma_rreq_thrd:3; ++ ++ // h000c, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h000c, bit: 7 ++ /* ISP RDMA MIU high priority threshold*/ ++ #define offset_of_reg_isp_rdma_rreq_hpri (24) ++ #define mask_of_reg_isp_rdma_rreq_hpri (0xf0) ++ unsigned int reg_isp_rdma_rreq_hpri:4; ++ ++ // h000c, bit: 11 ++ /* ISP RDMA MIU burst number*/ ++ #define offset_of_reg_isp_rdma_rreq_max (24) ++ #define mask_of_reg_isp_rdma_rreq_max (0xf00) ++ unsigned int reg_isp_rdma_rreq_max:4; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 5 ++ /* ISP RDMA output blanking*/ ++ #define offset_of_reg_isp_rdma_tg_hblk (26) ++ #define mask_of_reg_isp_rdma_tg_hblk (0x3f) ++ unsigned int reg_isp_rdma_tg_hblk:6; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 0 ++ /* ISP RDMA start trigger*/ ++ #define offset_of_reg_isp_rdma_trigger (32) ++ #define mask_of_reg_isp_rdma_trigger (0x1) ++ unsigned int reg_isp_rdma_trigger:1; ++ ++ // h0010, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 7 ++ /* */ ++ #define offset_of_reg_sw_rst_mode (46) ++ #define mask_of_reg_sw_rst_mode (0xff) ++ unsigned int reg_sw_rst_mode:8; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 0 ++ /* ISP RDMA valid data msb align at 16bit mode*/ ++ #define offset_of_reg_isp_rdma_msb_align (48) ++ #define mask_of_reg_isp_rdma_msb_align (0x1) ++ unsigned int reg_isp_rdma_msb_align:1; ++ ++ // h0018, bit: 2 ++ /* ISP RDMA valid data mode at 16bit mode ++ 2'd0: 8-bit ++ 2'd1:10-bit ++ 2'd2: 16-bit ++ 2'd3: 12-bit*/ ++ #define offset_of_reg_isp_rdma_valid_mode (48) ++ #define mask_of_reg_isp_rdma_valid_mode (0x6) ++ unsigned int reg_isp_rdma_valid_mode:2; ++ ++ // h0018, bit: 14 ++ /* */ ++ unsigned int :13; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 0 ++ /* ISP RDMA end of frame status*/ ++ #define offset_of_reg_isp_rdma_eof_read (62) ++ #define mask_of_reg_isp_rdma_eof_read (0x1) ++ unsigned int reg_isp_rdma_eof_read:1; ++ ++ // h001f, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 0 ++ /* ISP WDMA enable*/ ++ #define offset_of_reg_isp_wdma_en (64) ++ #define mask_of_reg_isp_wdma_en (0x1) ++ unsigned int reg_isp_wdma_en:1; ++ ++ // h0020, bit: 2 ++ /* */ ++ unsigned int :2; ++ ++ // h0020, bit: 3 ++ /* ISP WDMA MIU wbe mask*/ ++ #define offset_of_reg_isp_wdma_wbe_mask (64) ++ #define mask_of_reg_isp_wdma_wbe_mask (0x8) ++ unsigned int reg_isp_wdma_wbe_mask:1; ++ ++ // h0020, bit: 4 ++ /* ISP WDMA auto vsync trigger mode*/ ++ #define offset_of_reg_isp_wdma_auto (64) ++ #define mask_of_reg_isp_wdma_auto (0x10) ++ unsigned int reg_isp_wdma_auto:1; ++ ++ // h0020, bit: 6 ++ /* */ ++ unsigned int :2; ++ ++ // h0020, bit: 7 ++ /* ISP WDMA high priority set*/ ++ #define offset_of_reg_isp_wdma_wreq_hpri_set (64) ++ #define mask_of_reg_isp_wdma_wreq_hpri_set (0x80) ++ unsigned int reg_isp_wdma_wreq_hpri_set:1; ++ ++ // h0020, bit: 9 ++ /* ISP WDMA pack mode: ++ 2'd0: 8-bit ++ 2'd1: 10-bit ++ 2'd2: 16-bit ++ 2'd3: 12-bit*/ ++ #define offset_of_reg_isp_wdma_mode (64) ++ #define mask_of_reg_isp_wdma_mode (0x300) ++ unsigned int reg_isp_wdma_mode:2; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0020, bit: 15 ++ /* ISP WDMA MIU request reset*/ ++ #define offset_of_reg_isp_wdma_wreq_rst (64) ++ #define mask_of_reg_isp_wdma_wreq_rst (0x8000) ++ unsigned int reg_isp_wdma_wreq_rst:1; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 12 ++ /* ISP WDMA pitch*/ ++ #define offset_of_reg_isp_wdma_pitch (66) ++ #define mask_of_reg_isp_wdma_pitch (0x1fff) ++ unsigned int reg_isp_wdma_pitch:13; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0025, bit: 15 ++ /* ISP WDMA height limit enable*/ ++ #define offset_of_reg_isp_wdma_height_en (74) ++ #define mask_of_reg_isp_wdma_height_en (0x8000) ++ unsigned int reg_isp_wdma_height_en:1; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 14 ++ /* ISP WDMA write limit address*/ ++ #define offset_of_reg_isp_wdma_w_limit_adr (76) ++ #define mask_of_reg_isp_wdma_w_limit_adr (0xffff) ++ unsigned int reg_isp_wdma_w_limit_adr:16; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 10 ++ /* ISP WDMA write limit address*/ ++ #define offset_of_reg_isp_wdma_w_limit_adr_1 (78) ++ #define mask_of_reg_isp_wdma_w_limit_adr_1 (0x7ff) ++ unsigned int reg_isp_wdma_w_limit_adr_1:11; ++ ++ // h0027, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0027, bit: 15 ++ /* ISP WDMA write limit enable*/ ++ #define offset_of_reg_isp_wdma_w_limit_en (78) ++ #define mask_of_reg_isp_wdma_w_limit_en (0x8000) ++ unsigned int reg_isp_wdma_w_limit_en:1; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* ISP WDMA MIU base address*/ ++ #define offset_of_reg_isp_wdma_base (80) ++ #define mask_of_reg_isp_wdma_base (0xffff) ++ unsigned int reg_isp_wdma_base:16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 10 ++ /* ISP WDMA MIU base address*/ ++ #define offset_of_reg_isp_wdma_base_1 (82) ++ #define mask_of_reg_isp_wdma_base_1 (0x7ff) ++ unsigned int reg_isp_wdma_base_1:11; ++ ++ // h0029, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 2 ++ /* ISP WDMA MIU request threshold (*4+1)*/ ++ #define offset_of_reg_isp_wdma_wreq_thrd (88) ++ #define mask_of_reg_isp_wdma_wreq_thrd (0x7) ++ unsigned int reg_isp_wdma_wreq_thrd:3; ++ ++ // h002c, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h002c, bit: 7 ++ /* ISP WDMA MIU high priority threshold*/ ++ #define offset_of_reg_isp_wdma_wreq_hpri (88) ++ #define mask_of_reg_isp_wdma_wreq_hpri (0xf0) ++ unsigned int reg_isp_wdma_wreq_hpri:4; ++ ++ // h002c, bit: 11 ++ /* ISP WDMA MIU burst number*/ ++ #define offset_of_reg_isp_wdma_wreq_max (88) ++ #define mask_of_reg_isp_wdma_wreq_max (0xf00) ++ unsigned int reg_isp_wdma_wreq_max:4; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 0 ++ /* ISP WDMA start trigger*/ ++ #define offset_of_reg_isp_wdma_trigger (96) ++ #define mask_of_reg_isp_wdma_trigger (0x1) ++ unsigned int reg_isp_wdma_trigger:1; ++ ++ // h0030, bit: 1 ++ /* ISP WDMA start trigger vsync aligned mode*/ ++ #define offset_of_reg_isp_wdma_trigger_mode (96) ++ #define mask_of_reg_isp_wdma_trigger_mode (0x2) ++ unsigned int reg_isp_wdma_trigger_mode:1; ++ ++ // h0030, bit: 7 ++ /* */ ++ unsigned int :6; ++ ++ // h0030, bit: 8 ++ /* ISP WDMA input auto-align enable*/ ++ #define offset_of_reg_isp_wdma_align_en (96) ++ #define mask_of_reg_isp_wdma_align_en (0x100) ++ unsigned int reg_isp_wdma_align_en:1; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :7; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 0 ++ /* ISP WDMA valid data msb align at 16bit mode*/ ++ #define offset_of_reg_isp_wdma_msb_align (98) ++ #define mask_of_reg_isp_wdma_msb_align (0x1) ++ unsigned int reg_isp_wdma_msb_align:1; ++ ++ // h0031, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 0 ++ /* ISP WDMA end of frame status*/ ++ #define offset_of_reg_isp_wdma_eof_read (126) ++ #define mask_of_reg_isp_wdma_eof_read (0x1) ++ unsigned int reg_isp_wdma_eof_read:1; ++ ++ // h003f, bit: 7 ++ /* */ ++ unsigned int :7; ++ ++ // h003f, bit: 8 ++ /* ISP WDMA LB full status*/ ++ #define offset_of_reg_isp_wdma_lb_full_read (126) ++ #define mask_of_reg_isp_wdma_lb_full_read (0x100) ++ unsigned int reg_isp_wdma_lb_full_read:1; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h003f, bit: 15 ++ /* ISP WDMA status clear*/ ++ #define offset_of_reg_isp_wdma_status_clr (126) ++ #define mask_of_reg_isp_wdma_status_clr (0x8000) ++ unsigned int reg_isp_wdma_status_clr:1; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 0 ++ /* ISP DMA mclk req force active*/ ++ #define offset_of_reg_mreq_always_active (128) ++ #define mask_of_reg_mreq_always_active (0x1) ++ unsigned int reg_mreq_always_active:1; ++ ++ // h0040, bit: 1 ++ /* ISP DMA mclk req force off*/ ++ #define offset_of_reg_mreq_force_off (128) ++ #define mask_of_reg_mreq_force_off (0x2) ++ unsigned int reg_mreq_force_off:1; ++ ++ // h0040, bit: 2 ++ /* ISP DMA mclk req wdma mode*/ ++ #define offset_of_reg_mreq_wdma_mode (128) ++ #define mask_of_reg_mreq_wdma_mode (0x4) ++ unsigned int reg_mreq_wdma_mode:1; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :13; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 0 ++ /* Post White Balance Gain Dither Enable*/ ++ #define offset_of_reg_wbg1_dith_en (142) ++ #define mask_of_reg_wbg1_dith_en (0x1) ++ unsigned int reg_wbg1_dith_en:1; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 12 ++ /* Post White Balance Gain for R channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_r_gain (144) ++ #define mask_of_reg_isp_wbg1_r_gain (0x1fff) ++ unsigned int reg_isp_wbg1_r_gain:13; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 10 ++ /* Post White Balance Offset for R channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_r_offset (146) ++ #define mask_of_reg_isp_wbg1_r_offset (0x7ff) ++ unsigned int reg_isp_wbg1_r_offset:11; ++ ++ // h0049, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 12 ++ /* Post White Balance Gain for Gr channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_gr_gain (148) ++ #define mask_of_reg_isp_wbg1_gr_gain (0x1fff) ++ unsigned int reg_isp_wbg1_gr_gain:13; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 10 ++ /* Post White Balance Offset for Gr channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_gr_offset (150) ++ #define mask_of_reg_isp_wbg1_gr_offset (0x7ff) ++ unsigned int reg_isp_wbg1_gr_offset:11; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 12 ++ /* Post White Balance Gain for B channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_b_gain (152) ++ #define mask_of_reg_isp_wbg1_b_gain (0x1fff) ++ unsigned int reg_isp_wbg1_b_gain:13; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 10 ++ /* Post White Balance Offset for B channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_b_offset (154) ++ #define mask_of_reg_isp_wbg1_b_offset (0x7ff) ++ unsigned int reg_isp_wbg1_b_offset:11; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 12 ++ /* Post White Balance Gain for Gb channel (3.10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_gb_gain (156) ++ #define mask_of_reg_isp_wbg1_gb_gain (0x1fff) ++ unsigned int reg_isp_wbg1_gb_gain:13; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :3; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 10 ++ /* Post White Balance Offset for Gb channel (s10) ++ ( double buffer register )*/ ++ #define offset_of_reg_isp_wbg1_gb_offset (158) ++ #define mask_of_reg_isp_wbg1_gb_offset (0x7ff) ++ unsigned int reg_isp_wbg1_gb_offset:11; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 0 ++ /* HSV Adjust enable*/ ++ #define offset_of_reg_hsv_adj_en (160) ++ #define mask_of_reg_hsv_adj_en (0x1) ++ unsigned int reg_hsv_adj_en:1; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 7 ++ /* HSV hue adjust LUT parameter x0*/ ++ #define offset_of_reg_hue_adj_lut_x0 (162) ++ #define mask_of_reg_hue_adj_lut_x0 (0xff) ++ unsigned int reg_hue_adj_lut_x0:8; ++ ++ // h0051, bit: 14 ++ /* HSV hue adjust LUT parameter x1*/ ++ #define offset_of_reg_hue_adj_lut_x1 (162) ++ #define mask_of_reg_hue_adj_lut_x1 (0xff00) ++ unsigned int reg_hue_adj_lut_x1:8; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 7 ++ /* HSV hue adjust LUT parameter x2*/ ++ #define offset_of_reg_hue_adj_lut_x2 (164) ++ #define mask_of_reg_hue_adj_lut_x2 (0xff) ++ unsigned int reg_hue_adj_lut_x2:8; ++ ++ // h0052, bit: 14 ++ /* HSV hue adjust LUT parameter x3*/ ++ #define offset_of_reg_hue_adj_lut_x3 (164) ++ #define mask_of_reg_hue_adj_lut_x3 (0xff00) ++ unsigned int reg_hue_adj_lut_x3:8; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 7 ++ /* HSV hue adjust LUT parameter x4*/ ++ #define offset_of_reg_hue_adj_lut_x4 (166) ++ #define mask_of_reg_hue_adj_lut_x4 (0xff) ++ unsigned int reg_hue_adj_lut_x4:8; ++ ++ // h0053, bit: 14 ++ /* HSV hue adjust LUT parameter x5*/ ++ #define offset_of_reg_hue_adj_lut_x5 (166) ++ #define mask_of_reg_hue_adj_lut_x5 (0xff00) ++ unsigned int reg_hue_adj_lut_x5:8; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 7 ++ /* HSV hue adjust LUT parameter x6*/ ++ #define offset_of_reg_hue_adj_lut_x6 (168) ++ #define mask_of_reg_hue_adj_lut_x6 (0xff) ++ unsigned int reg_hue_adj_lut_x6:8; ++ ++ // h0054, bit: 14 ++ /* HSV hue adjust LUT parameter x7*/ ++ #define offset_of_reg_hue_adj_lut_x7 (168) ++ #define mask_of_reg_hue_adj_lut_x7 (0xff00) ++ unsigned int reg_hue_adj_lut_x7:8; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 7 ++ /* HSV hue adjust LUT parameter x8*/ ++ #define offset_of_reg_hue_adj_lut_x8 (170) ++ #define mask_of_reg_hue_adj_lut_x8 (0xff) ++ unsigned int reg_hue_adj_lut_x8:8; ++ ++ // h0055, bit: 14 ++ /* HSV hue adjust LUT parameter x9*/ ++ #define offset_of_reg_hue_adj_lut_x9 (170) ++ #define mask_of_reg_hue_adj_lut_x9 (0xff00) ++ unsigned int reg_hue_adj_lut_x9:8; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 7 ++ /* HSV hue adjust LUT parameter x10*/ ++ #define offset_of_reg_hue_adj_lut_x10 (172) ++ #define mask_of_reg_hue_adj_lut_x10 (0xff) ++ unsigned int reg_hue_adj_lut_x10:8; ++ ++ // h0056, bit: 14 ++ /* HSV hue adjust LUT parameter x11*/ ++ #define offset_of_reg_hue_adj_lut_x11 (172) ++ #define mask_of_reg_hue_adj_lut_x11 (0xff00) ++ unsigned int reg_hue_adj_lut_x11:8; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 7 ++ /* HSV hue adjust LUT parameter x12*/ ++ #define offset_of_reg_hue_adj_lut_x12 (174) ++ #define mask_of_reg_hue_adj_lut_x12 (0xff) ++ unsigned int reg_hue_adj_lut_x12:8; ++ ++ // h0057, bit: 14 ++ /* HSV hue adjust LUT parameter x13*/ ++ #define offset_of_reg_hue_adj_lut_x13 (174) ++ #define mask_of_reg_hue_adj_lut_x13 (0xff00) ++ unsigned int reg_hue_adj_lut_x13:8; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 7 ++ /* HSV hue adjust LUT parameter x14*/ ++ #define offset_of_reg_hue_adj_lut_x14 (176) ++ #define mask_of_reg_hue_adj_lut_x14 (0xff) ++ unsigned int reg_hue_adj_lut_x14:8; ++ ++ // h0058, bit: 14 ++ /* HSV hue adjust LUT parameter x15*/ ++ #define offset_of_reg_hue_adj_lut_x15 (176) ++ #define mask_of_reg_hue_adj_lut_x15 (0xff00) ++ unsigned int reg_hue_adj_lut_x15:8; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 7 ++ /* HSV hue adjust LUT parameter x16*/ ++ #define offset_of_reg_hue_adj_lut_x16 (178) ++ #define mask_of_reg_hue_adj_lut_x16 (0xff) ++ unsigned int reg_hue_adj_lut_x16:8; ++ ++ // h0059, bit: 14 ++ /* HSV hue adjust LUT parameter x17*/ ++ #define offset_of_reg_hue_adj_lut_x17 (178) ++ #define mask_of_reg_hue_adj_lut_x17 (0xff00) ++ unsigned int reg_hue_adj_lut_x17:8; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 7 ++ /* HSV hue adjust LUT parameter x18*/ ++ #define offset_of_reg_hue_adj_lut_x18 (180) ++ #define mask_of_reg_hue_adj_lut_x18 (0xff) ++ unsigned int reg_hue_adj_lut_x18:8; ++ ++ // h005a, bit: 14 ++ /* HSV hue adjust LUT parameter x19*/ ++ #define offset_of_reg_hue_adj_lut_x19 (180) ++ #define mask_of_reg_hue_adj_lut_x19 (0xff00) ++ unsigned int reg_hue_adj_lut_x19:8; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 7 ++ /* HSV hue adjust LUT parameter x20*/ ++ #define offset_of_reg_hue_adj_lut_x20 (182) ++ #define mask_of_reg_hue_adj_lut_x20 (0xff) ++ unsigned int reg_hue_adj_lut_x20:8; ++ ++ // h005b, bit: 14 ++ /* HSV hue adjust LUT parameter x21*/ ++ #define offset_of_reg_hue_adj_lut_x21 (182) ++ #define mask_of_reg_hue_adj_lut_x21 (0xff00) ++ unsigned int reg_hue_adj_lut_x21:8; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 7 ++ /* HSV hue adjust LUT parameter x22*/ ++ #define offset_of_reg_hue_adj_lut_x22 (184) ++ #define mask_of_reg_hue_adj_lut_x22 (0xff) ++ unsigned int reg_hue_adj_lut_x22:8; ++ ++ // h005c, bit: 14 ++ /* HSV hue adjust LUT parameter x23*/ ++ #define offset_of_reg_hue_adj_lut_x23 (184) ++ #define mask_of_reg_hue_adj_lut_x23 (0xff00) ++ unsigned int reg_hue_adj_lut_x23:8; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 7 ++ /* HSV sat adjust LUT parameter x0*/ ++ #define offset_of_reg_sat_adj_lut_x0 (186) ++ #define mask_of_reg_sat_adj_lut_x0 (0xff) ++ unsigned int reg_sat_adj_lut_x0:8; ++ ++ // h005d, bit: 14 ++ /* HSV sat adjust LUT parameter x1*/ ++ #define offset_of_reg_sat_adj_lut_x1 (186) ++ #define mask_of_reg_sat_adj_lut_x1 (0xff00) ++ unsigned int reg_sat_adj_lut_x1:8; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 7 ++ /* HSV sat adjust LUT parameter x2*/ ++ #define offset_of_reg_sat_adj_lut_x2 (188) ++ #define mask_of_reg_sat_adj_lut_x2 (0xff) ++ unsigned int reg_sat_adj_lut_x2:8; ++ ++ // h005e, bit: 14 ++ /* HSV sat adjust LUT parameter x3*/ ++ #define offset_of_reg_sat_adj_lut_x3 (188) ++ #define mask_of_reg_sat_adj_lut_x3 (0xff00) ++ unsigned int reg_sat_adj_lut_x3:8; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 7 ++ /* HSV sat adjust LUT parameter x4*/ ++ #define offset_of_reg_sat_adj_lut_x4 (190) ++ #define mask_of_reg_sat_adj_lut_x4 (0xff) ++ unsigned int reg_sat_adj_lut_x4:8; ++ ++ // h005f, bit: 14 ++ /* HSV sat adjust LUT parameter x5*/ ++ #define offset_of_reg_sat_adj_lut_x5 (190) ++ #define mask_of_reg_sat_adj_lut_x5 (0xff00) ++ unsigned int reg_sat_adj_lut_x5:8; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 7 ++ /* HSV sat adjust LUT parameter x6*/ ++ #define offset_of_reg_sat_adj_lut_x6 (192) ++ #define mask_of_reg_sat_adj_lut_x6 (0xff) ++ unsigned int reg_sat_adj_lut_x6:8; ++ ++ // h0060, bit: 14 ++ /* HSV sat adjust LUT parameter x7*/ ++ #define offset_of_reg_sat_adj_lut_x7 (192) ++ #define mask_of_reg_sat_adj_lut_x7 (0xff00) ++ unsigned int reg_sat_adj_lut_x7:8; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 7 ++ /* HSV sat adjust LUT parameter x8*/ ++ #define offset_of_reg_sat_adj_lut_x8 (194) ++ #define mask_of_reg_sat_adj_lut_x8 (0xff) ++ unsigned int reg_sat_adj_lut_x8:8; ++ ++ // h0061, bit: 14 ++ /* HSV sat adjust LUT parameter x9*/ ++ #define offset_of_reg_sat_adj_lut_x9 (194) ++ #define mask_of_reg_sat_adj_lut_x9 (0xff00) ++ unsigned int reg_sat_adj_lut_x9:8; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 7 ++ /* HSV sat adjust LUT parameter x10*/ ++ #define offset_of_reg_sat_adj_lut_x10 (196) ++ #define mask_of_reg_sat_adj_lut_x10 (0xff) ++ unsigned int reg_sat_adj_lut_x10:8; ++ ++ // h0062, bit: 14 ++ /* HSV sat adjust LUT parameter x11*/ ++ #define offset_of_reg_sat_adj_lut_x11 (196) ++ #define mask_of_reg_sat_adj_lut_x11 (0xff00) ++ unsigned int reg_sat_adj_lut_x11:8; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 7 ++ /* HSV sat adjust LUT parameter x12*/ ++ #define offset_of_reg_sat_adj_lut_x12 (198) ++ #define mask_of_reg_sat_adj_lut_x12 (0xff) ++ unsigned int reg_sat_adj_lut_x12:8; ++ ++ // h0063, bit: 14 ++ /* HSV sat adjust LUT parameter x13*/ ++ #define offset_of_reg_sat_adj_lut_x13 (198) ++ #define mask_of_reg_sat_adj_lut_x13 (0xff00) ++ unsigned int reg_sat_adj_lut_x13:8; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 7 ++ /* HSV sat adjust LUT parameter x14*/ ++ #define offset_of_reg_sat_adj_lut_x14 (200) ++ #define mask_of_reg_sat_adj_lut_x14 (0xff) ++ unsigned int reg_sat_adj_lut_x14:8; ++ ++ // h0064, bit: 14 ++ /* HSV sat adjust LUT parameter x15*/ ++ #define offset_of_reg_sat_adj_lut_x15 (200) ++ #define mask_of_reg_sat_adj_lut_x15 (0xff00) ++ unsigned int reg_sat_adj_lut_x15:8; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 7 ++ /* HSV sat adjust LUT parameter x16*/ ++ #define offset_of_reg_sat_adj_lut_x16 (202) ++ #define mask_of_reg_sat_adj_lut_x16 (0xff) ++ unsigned int reg_sat_adj_lut_x16:8; ++ ++ // h0065, bit: 14 ++ /* HSV sat adjust LUT parameter x17*/ ++ #define offset_of_reg_sat_adj_lut_x17 (202) ++ #define mask_of_reg_sat_adj_lut_x17 (0xff00) ++ unsigned int reg_sat_adj_lut_x17:8; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 7 ++ /* HSV sat adjust LUT parameter x18*/ ++ #define offset_of_reg_sat_adj_lut_x18 (204) ++ #define mask_of_reg_sat_adj_lut_x18 (0xff) ++ unsigned int reg_sat_adj_lut_x18:8; ++ ++ // h0066, bit: 14 ++ /* HSV sat adjust LUT parameter x19*/ ++ #define offset_of_reg_sat_adj_lut_x19 (204) ++ #define mask_of_reg_sat_adj_lut_x19 (0xff00) ++ unsigned int reg_sat_adj_lut_x19:8; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 7 ++ /* HSV sat adjust LUT parameter x20*/ ++ #define offset_of_reg_sat_adj_lut_x20 (206) ++ #define mask_of_reg_sat_adj_lut_x20 (0xff) ++ unsigned int reg_sat_adj_lut_x20:8; ++ ++ // h0067, bit: 14 ++ /* HSV sat adjust LUT parameter x21*/ ++ #define offset_of_reg_sat_adj_lut_x21 (206) ++ #define mask_of_reg_sat_adj_lut_x21 (0xff00) ++ unsigned int reg_sat_adj_lut_x21:8; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 7 ++ /* HSV sat adjust LUT parameter x22*/ ++ #define offset_of_reg_sat_adj_lut_x22 (208) ++ #define mask_of_reg_sat_adj_lut_x22 (0xff) ++ unsigned int reg_sat_adj_lut_x22:8; ++ ++ // h0068, bit: 14 ++ /* HSV sat adjust LUT parameter x23*/ ++ #define offset_of_reg_sat_adj_lut_x23 (208) ++ #define mask_of_reg_sat_adj_lut_x23 (0xff00) ++ unsigned int reg_sat_adj_lut_x23:8; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 7 ++ /* HSV val adjust LUT parameter x0*/ ++ #define offset_of_reg_val_adj_lut_x0 (210) ++ #define mask_of_reg_val_adj_lut_x0 (0xff) ++ unsigned int reg_val_adj_lut_x0:8; ++ ++ // h0069, bit: 14 ++ /* HSV val adjust LUT parameter x1*/ ++ #define offset_of_reg_val_adj_lut_x1 (210) ++ #define mask_of_reg_val_adj_lut_x1 (0xff00) ++ unsigned int reg_val_adj_lut_x1:8; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 7 ++ /* HSV val adjust LUT parameter x2*/ ++ #define offset_of_reg_val_adj_lut_x2 (212) ++ #define mask_of_reg_val_adj_lut_x2 (0xff) ++ unsigned int reg_val_adj_lut_x2:8; ++ ++ // h006a, bit: 14 ++ /* HSV val adjust LUT parameter x3*/ ++ #define offset_of_reg_val_adj_lut_x3 (212) ++ #define mask_of_reg_val_adj_lut_x3 (0xff00) ++ unsigned int reg_val_adj_lut_x3:8; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 7 ++ /* HSV val adjust LUT parameter x4*/ ++ #define offset_of_reg_val_adj_lut_x4 (214) ++ #define mask_of_reg_val_adj_lut_x4 (0xff) ++ unsigned int reg_val_adj_lut_x4:8; ++ ++ // h006b, bit: 14 ++ /* HSV val adjust LUT parameter x5*/ ++ #define offset_of_reg_val_adj_lut_x5 (214) ++ #define mask_of_reg_val_adj_lut_x5 (0xff00) ++ unsigned int reg_val_adj_lut_x5:8; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 7 ++ /* HSV val adjust LUT parameter x6*/ ++ #define offset_of_reg_val_adj_lut_x6 (216) ++ #define mask_of_reg_val_adj_lut_x6 (0xff) ++ unsigned int reg_val_adj_lut_x6:8; ++ ++ // h006c, bit: 14 ++ /* HSV val adjust LUT parameter x7*/ ++ #define offset_of_reg_val_adj_lut_x7 (216) ++ #define mask_of_reg_val_adj_lut_x7 (0xff00) ++ unsigned int reg_val_adj_lut_x7:8; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 7 ++ /* HSV val adjust LUT parameter x8*/ ++ #define offset_of_reg_val_adj_lut_x8 (218) ++ #define mask_of_reg_val_adj_lut_x8 (0xff) ++ unsigned int reg_val_adj_lut_x8:8; ++ ++ // h006d, bit: 14 ++ /* HSV val adjust LUT parameter x9*/ ++ #define offset_of_reg_val_adj_lut_x9 (218) ++ #define mask_of_reg_val_adj_lut_x9 (0xff00) ++ unsigned int reg_val_adj_lut_x9:8; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 7 ++ /* HSV val adjust LUT parameter x10*/ ++ #define offset_of_reg_val_adj_lut_x10 (220) ++ #define mask_of_reg_val_adj_lut_x10 (0xff) ++ unsigned int reg_val_adj_lut_x10:8; ++ ++ // h006e, bit: 14 ++ /* HSV val adjust LUT parameter x11*/ ++ #define offset_of_reg_val_adj_lut_x11 (220) ++ #define mask_of_reg_val_adj_lut_x11 (0xff00) ++ unsigned int reg_val_adj_lut_x11:8; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 7 ++ /* HSV val adjust LUT parameter x12*/ ++ #define offset_of_reg_val_adj_lut_x12 (222) ++ #define mask_of_reg_val_adj_lut_x12 (0xff) ++ unsigned int reg_val_adj_lut_x12:8; ++ ++ // h006f, bit: 14 ++ /* HSV val adjust LUT parameter x13*/ ++ #define offset_of_reg_val_adj_lut_x13 (222) ++ #define mask_of_reg_val_adj_lut_x13 (0xff00) ++ unsigned int reg_val_adj_lut_x13:8; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 7 ++ /* HSV val adjust LUT parameter x14*/ ++ #define offset_of_reg_val_adj_lut_x14 (224) ++ #define mask_of_reg_val_adj_lut_x14 (0xff) ++ unsigned int reg_val_adj_lut_x14:8; ++ ++ // h0070, bit: 14 ++ /* HSV val adjust LUT parameter x15*/ ++ #define offset_of_reg_val_adj_lut_x15 (224) ++ #define mask_of_reg_val_adj_lut_x15 (0xff00) ++ unsigned int reg_val_adj_lut_x15:8; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 7 ++ /* HSV val adjust LUT parameter x16*/ ++ #define offset_of_reg_val_adj_lut_x16 (226) ++ #define mask_of_reg_val_adj_lut_x16 (0xff) ++ unsigned int reg_val_adj_lut_x16:8; ++ ++ // h0071, bit: 14 ++ /* HSV val adjust LUT parameter x17*/ ++ #define offset_of_reg_val_adj_lut_x17 (226) ++ #define mask_of_reg_val_adj_lut_x17 (0xff00) ++ unsigned int reg_val_adj_lut_x17:8; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 7 ++ /* HSV val adjust LUT parameter x18*/ ++ #define offset_of_reg_val_adj_lut_x18 (228) ++ #define mask_of_reg_val_adj_lut_x18 (0xff) ++ unsigned int reg_val_adj_lut_x18:8; ++ ++ // h0072, bit: 14 ++ /* HSV val adjust LUT parameter x19*/ ++ #define offset_of_reg_val_adj_lut_x19 (228) ++ #define mask_of_reg_val_adj_lut_x19 (0xff00) ++ unsigned int reg_val_adj_lut_x19:8; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 7 ++ /* HSV val adjust LUT parameter x20*/ ++ #define offset_of_reg_val_adj_lut_x20 (230) ++ #define mask_of_reg_val_adj_lut_x20 (0xff) ++ unsigned int reg_val_adj_lut_x20:8; ++ ++ // h0073, bit: 14 ++ /* HSV val adjust LUT parameter x21*/ ++ #define offset_of_reg_val_adj_lut_x21 (230) ++ #define mask_of_reg_val_adj_lut_x21 (0xff00) ++ unsigned int reg_val_adj_lut_x21:8; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 7 ++ /* HSV val adjust LUT parameter x22*/ ++ #define offset_of_reg_val_adj_lut_x22 (232) ++ #define mask_of_reg_val_adj_lut_x22 (0xff) ++ unsigned int reg_val_adj_lut_x22:8; ++ ++ // h0074, bit: 14 ++ /* HSV val adjust LUT parameter x23*/ ++ #define offset_of_reg_val_adj_lut_x23 (232) ++ #define mask_of_reg_val_adj_lut_x23 (0xff00) ++ unsigned int reg_val_adj_lut_x23:8; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp6; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp7.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp7.h +new file mode 100644 +index 00000000..355384fe +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp7.h +@@ -0,0 +1,1145 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP7__ ++#define __INFINITY3E_REG_ISP7__ ++typedef struct { ++ // h0000, bit: 0 ++ /* timing generator enable*/ ++ #define offset_of_reg_pat_tgen_en (0) ++ #define mask_of_reg_pat_tgen_en (0x1) ++ unsigned int reg_pat_tgen_en:1; ++ ++ // h0000, bit: 1 ++ /* data generator enable*/ ++ #define offset_of_reg_pat_dgen_en (0) ++ #define mask_of_reg_pat_dgen_en (0x2) ++ unsigned int reg_pat_dgen_en:1; ++ ++ // h0000, bit: 2 ++ /* hsync generator*/ ++ #define offset_of_reg_pat_hsgen_en (0) ++ #define mask_of_reg_pat_hsgen_en (0x4) ++ unsigned int reg_pat_hsgen_en:1; ++ ++ // h0000, bit: 3 ++ /* data generator reset*/ ++ #define offset_of_reg_pat_dgen_rst (0) ++ #define mask_of_reg_pat_dgen_rst (0x8) ++ unsigned int reg_pat_dgen_rst:1; ++ ++ // h0000, bit: 5 ++ /* bayer format*/ ++ #define offset_of_reg_pat_sensor_array (0) ++ #define mask_of_reg_pat_sensor_array (0x30) ++ unsigned int reg_pat_sensor_array:2; ++ ++ // h0000, bit: 7 ++ /* */ ++ unsigned int :2; ++ ++ // h0000, bit: 10 ++ /* data enable valid rate control*/ ++ #define offset_of_reg_pat_de_rate (0) ++ #define mask_of_reg_pat_de_rate (0x700) ++ unsigned int reg_pat_de_rate:3; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 11 ++ /* image width minus one*/ ++ #define offset_of_reg_pat_img_width_m1 (2) ++ #define mask_of_reg_pat_img_width_m1 (0xfff) ++ unsigned int reg_pat_img_width_m1:12; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 11 ++ /* image height minus one*/ ++ #define offset_of_reg_pat_img_height_m1 (4) ++ #define mask_of_reg_pat_img_height_m1 (0xfff) ++ unsigned int reg_pat_img_height_m1:12; ++ ++ // h0002, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 7 ++ /* vsync pulse position, line number before v-active*/ ++ #define offset_of_reg_pat_vs_line (6) ++ #define mask_of_reg_pat_vs_line (0xff) ++ unsigned int reg_pat_vs_line:8; ++ ++ // h0003, bit: 14 ++ /* hsync pulse position, pixel number before v-active*/ ++ #define offset_of_reg_pat_hs_pxl (6) ++ #define mask_of_reg_pat_hs_pxl (0xff00) ++ unsigned int reg_pat_hs_pxl:8; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 7 ++ /* H-blanking time (x2)*/ ++ #define offset_of_reg_pat_hblank (8) ++ #define mask_of_reg_pat_hblank (0xff) ++ unsigned int reg_pat_hblank:8; ++ ++ // h0004, bit: 14 ++ /* V-blanking time*/ ++ #define offset_of_reg_pat_vblank (8) ++ #define mask_of_reg_pat_vblank (0xff00) ++ unsigned int reg_pat_vblank:8; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 11 ++ /* pattern block width minus one*/ ++ #define offset_of_reg_pat_blk_width_m1 (10) ++ #define mask_of_reg_pat_blk_width_m1 (0xfff) ++ unsigned int reg_pat_blk_width_m1:12; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 11 ++ /* pattern block height minus one*/ ++ #define offset_of_reg_pat_blk_height_m1 (12) ++ #define mask_of_reg_pat_blk_height_m1 (0xfff) ++ unsigned int reg_pat_blk_height_m1:12; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 2 ++ /* initial color bar index*/ ++ #define offset_of_reg_pat_color_init_idx (14) ++ #define mask_of_reg_pat_color_init_idx (0x7) ++ unsigned int reg_pat_color_init_idx:3; ++ ++ // h0007, bit: 3 ++ /* */ ++ unsigned int :1; ++ ++ // h0007, bit: 5 ++ /* color bar value percentage*/ ++ #define offset_of_reg_pat_color_percent (14) ++ #define mask_of_reg_pat_color_percent (0x30) ++ unsigned int reg_pat_color_percent:2; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 7 ++ /* frame pattern change rate*/ ++ #define offset_of_reg_pat_frm_chg_rate (16) ++ #define mask_of_reg_pat_frm_chg_rate (0xff) ++ unsigned int reg_pat_frm_chg_rate:8; ++ ++ // h0008, bit: 11 ++ /* pattern shift pixel number when frame change*/ ++ #define offset_of_reg_pat_frm_chg_x (16) ++ #define mask_of_reg_pat_frm_chg_x (0xf00) ++ unsigned int reg_pat_frm_chg_x:4; ++ ++ // h0008, bit: 14 ++ /* pattern shift line number when frame change*/ ++ #define offset_of_reg_pat_frm_chg_y (16) ++ #define mask_of_reg_pat_frm_chg_y (0xf000) ++ unsigned int reg_pat_frm_chg_y:4; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 0 ++ /* i2c clock enable*/ ++ #define offset_of_reg_i2c_en (240) ++ #define mask_of_reg_i2c_en (0x1) ++ unsigned int reg_i2c_en:1; ++ ++ // h0078, bit: 7 ++ /* */ ++ unsigned int :7; ++ ++ // h0078, bit: 8 ++ /* i2c resetz*/ ++ #define offset_of_reg_i2c_rstz (240) ++ #define mask_of_reg_i2c_rstz (0x100) ++ unsigned int reg_i2c_rstz:1; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :7; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 7 ++ /* 2nd Register Address for 16 bit register address series mode ++ (single buffer)*/ ++ #define offset_of_reg_sen_m2s_2nd_reg_adr (242) ++ #define mask_of_reg_sen_m2s_2nd_reg_adr (0xff) ++ unsigned int reg_sen_m2s_2nd_reg_adr:8; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 0 ++ /* M2S Signal Control ++ # 1'b0: by HW ++ # 1'b1: by SW ++ ( single buffer register)*/ ++ #define offset_of_reg_sen_m2s_sw_ctrl (244) ++ #define mask_of_reg_sen_m2s_sw_ctrl (0x1) ++ unsigned int reg_sen_m2s_sw_ctrl:1; ++ ++ // h007a, bit: 1 ++ /* M2S mode. ++ # 1'b1: OmniVision SIF. ++ # 1'b0: Others. ++ ( single buffer register )*/ ++ #define offset_of_reg_sen_m2s_mode (244) ++ #define mask_of_reg_sen_m2s_mode (0x2) ++ unsigned int reg_sen_m2s_mode:1; ++ ++ // h007a, bit: 2 ++ /* M2S burst command length. ++ # 1'b0: length is 1. ++ # 1'b1: length is 2. ++ ( single buffer register )*/ ++ #define offset_of_reg_sen_m2s_cmd_bl (244) ++ #define mask_of_reg_sen_m2s_cmd_bl (0x4) ++ unsigned int reg_sen_m2s_cmd_bl:1; ++ ++ // h007a, bit: 3 ++ /* M2S Register Address Mode ++ # 1'b0 : 8 bit mode ++ # 1'b1 : 16 bit series mode ++ (single buffer register)*/ ++ #define offset_of_reg_sen_m2s_reg_adr_mode (244) ++ #define mask_of_reg_sen_m2s_reg_adr_mode (0x8) ++ unsigned int reg_sen_m2s_reg_adr_mode:1; ++ ++ // h007a, bit: 13 ++ /* */ ++ unsigned int :10; ++ ++ // h007a, bit: 14 ++ /* M2S SDA Input ++ ( single buffer register )*/ ++ #define offset_of_reg_sda_i (244) ++ #define mask_of_reg_sda_i (0x4000) ++ unsigned int reg_sda_i:1; ++ ++ // h007a, bit: 15 ++ /* M2S Status ++ # 1'b0: Idle ++ # 1'b1: Busy ++ ( single buffer register )*/ ++ #define offset_of_reg_m2s_status (244) ++ #define mask_of_reg_m2s_status (0x8000) ++ unsigned int reg_m2s_status:1; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* M2S command ++ # [0]: 1: read, 0: write. ++ # [7:1]: Slave address. ++ # [15:8]: Register address for 8 bit mode / first register address for 16 bit series mode ++ ( single buffer register )*/ ++ #define offset_of_reg_sen_m2s_cmd (246) ++ #define mask_of_reg_sen_m2s_cmd (0xffff) ++ unsigned int reg_sen_m2s_cmd:16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* M2S Write data. ++ # [7:0]: The first byte of Write data. ++ # [15:8]: The second byte of Write data. ++ Not valid if reg_sen_m2s_cmd_bl is 0. ++ ( single buffer register )*/ ++ #define offset_of_reg_sen_m2s_rw_d (248) ++ #define mask_of_reg_sen_m2s_rw_d (0xffff) ++ unsigned int reg_sen_m2s_rw_d:16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 9 ++ /* Factor of division for generating M2S clock. ++ Must be programmed less than SYSCLK /(4*M2S_frequency) minus 1 ++ ( single buffer register )*/ ++ #define offset_of_reg_sen_prescale (250) ++ #define mask_of_reg_sen_prescale (0x3ff) ++ unsigned int reg_sen_prescale:10; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 0 ++ /* M2S scl control ++ # 1'b0: scl low ++ # 1'b1: scl high*/ ++ #define offset_of_reg_sen_sw_scl_oen (252) ++ #define mask_of_reg_sen_sw_scl_oen (0x1) ++ unsigned int reg_sen_sw_scl_oen:1; ++ ++ // h007e, bit: 1 ++ /* M2S sda control ++ # 1'b0: sda output low ++ # 1'b1: sda input or sda output high*/ ++ #define offset_of_reg_sen_sw_sda_oen (252) ++ #define mask_of_reg_sen_sw_sda_oen (0x2) ++ unsigned int reg_sen_sw_sda_oen:1; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :14; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* M2S Read data. ++ # [7:0]: The first byte of Read data. ++ # [15:8]: The second byte of Read data. ++ Not valid if reg_sen_m2s_cmd_bl is 0. ++ ( single buffer register )*/ ++ #define offset_of_reg_sen_rd (254) ++ #define mask_of_reg_sen_rd (0xffff) ++ unsigned int reg_sen_rd:16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp7; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp8.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp8.h +new file mode 100644 +index 00000000..d7166cbb +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp8.h +@@ -0,0 +1,1168 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP8__ ++#define __INFINITY3E_REG_ISP8__ ++typedef struct { ++ // h0000, bit: 0 ++ /* RGB-IR enable*/ ++ #define offset_of_reg_rgbir_en (0) ++ #define mask_of_reg_rgbir_en (0x1) ++ unsigned int reg_rgbir_en:1; ++ ++ // h0000, bit: 1 ++ /* 4X4 mode*/ ++ #define offset_of_reg_mode4x4 (0) ++ #define mask_of_reg_mode4x4 (0x2) ++ unsigned int reg_mode4x4:1; ++ ++ // h0000, bit: 2 ++ /* 2X2 used IR_mode*/ ++ #define offset_of_reg_ir_mode (0) ++ #define mask_of_reg_ir_mode (0x4) ++ unsigned int reg_ir_mode:1; ++ ++ // h0000, bit: 3 ++ /* remove-IR offset enable*/ ++ #define offset_of_reg_ir_offset_en (0) ++ #define mask_of_reg_ir_offset_en (0x8) ++ unsigned int reg_ir_offset_en:1; ++ ++ // h0000, bit: 4 ++ /* IR histogram enable*/ ++ #define offset_of_reg_hist_ir_en (0) ++ #define mask_of_reg_hist_ir_en (0x10) ++ unsigned int reg_hist_ir_en:1; ++ ++ // h0000, bit: 5 ++ /* I Monitor enable*/ ++ #define offset_of_reg_imonitor_en (0) ++ #define mask_of_reg_imonitor_en (0x20) ++ unsigned int reg_imonitor_en:1; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 3 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_ratio_by_y_shift_0 (8) ++ #define mask_of_reg_ir_oft_ratio_by_y_shift_0 (0xf) ++ unsigned int reg_ir_oft_ratio_by_y_shift_0:4; ++ ++ // h0004, bit: 7 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_ratio_by_y_shift_1 (8) ++ #define mask_of_reg_ir_oft_ratio_by_y_shift_1 (0xf0) ++ unsigned int reg_ir_oft_ratio_by_y_shift_1:4; ++ ++ // h0004, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_ratio_by_y_shift_2 (8) ++ #define mask_of_reg_ir_oft_ratio_by_y_shift_2 (0xf00) ++ unsigned int reg_ir_oft_ratio_by_y_shift_2:4; ++ ++ // h0004, bit: 14 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_ratio_by_y_shift_3 (8) ++ #define mask_of_reg_ir_oft_ratio_by_y_shift_3 (0xf000) ++ unsigned int reg_ir_oft_ratio_by_y_shift_3:4; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 3 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_ratio_by_y_shift_4 (10) ++ #define mask_of_reg_ir_oft_ratio_by_y_shift_4 (0xf) ++ unsigned int reg_ir_oft_ratio_by_y_shift_4:4; ++ ++ // h0005, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_r_ratio_by_y_0 (12) ++ #define mask_of_reg_ir_oft_r_ratio_by_y_0 (0xfff) ++ unsigned int reg_ir_oft_r_ratio_by_y_0:12; ++ ++ // h0006, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_r_ratio_by_y_1 (14) ++ #define mask_of_reg_ir_oft_r_ratio_by_y_1 (0xfff) ++ unsigned int reg_ir_oft_r_ratio_by_y_1:12; ++ ++ // h0007, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_r_ratio_by_y_2 (16) ++ #define mask_of_reg_ir_oft_r_ratio_by_y_2 (0xfff) ++ unsigned int reg_ir_oft_r_ratio_by_y_2:12; ++ ++ // h0008, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_r_ratio_by_y_3 (18) ++ #define mask_of_reg_ir_oft_r_ratio_by_y_3 (0xfff) ++ unsigned int reg_ir_oft_r_ratio_by_y_3:12; ++ ++ // h0009, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_r_ratio_by_y_4 (20) ++ #define mask_of_reg_ir_oft_r_ratio_by_y_4 (0xfff) ++ unsigned int reg_ir_oft_r_ratio_by_y_4:12; ++ ++ // h000a, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_r_ratio_by_y_5 (22) ++ #define mask_of_reg_ir_oft_r_ratio_by_y_5 (0xfff) ++ unsigned int reg_ir_oft_r_ratio_by_y_5:12; ++ ++ // h000b, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_g_ratio_by_y_0 (24) ++ #define mask_of_reg_ir_oft_g_ratio_by_y_0 (0xfff) ++ unsigned int reg_ir_oft_g_ratio_by_y_0:12; ++ ++ // h000c, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_g_ratio_by_y_1 (26) ++ #define mask_of_reg_ir_oft_g_ratio_by_y_1 (0xfff) ++ unsigned int reg_ir_oft_g_ratio_by_y_1:12; ++ ++ // h000d, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_g_ratio_by_y_2 (28) ++ #define mask_of_reg_ir_oft_g_ratio_by_y_2 (0xfff) ++ unsigned int reg_ir_oft_g_ratio_by_y_2:12; ++ ++ // h000e, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_g_ratio_by_y_3 (30) ++ #define mask_of_reg_ir_oft_g_ratio_by_y_3 (0xfff) ++ unsigned int reg_ir_oft_g_ratio_by_y_3:12; ++ ++ // h000f, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_g_ratio_by_y_4 (32) ++ #define mask_of_reg_ir_oft_g_ratio_by_y_4 (0xfff) ++ unsigned int reg_ir_oft_g_ratio_by_y_4:12; ++ ++ // h0010, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_g_ratio_by_y_5 (34) ++ #define mask_of_reg_ir_oft_g_ratio_by_y_5 (0xfff) ++ unsigned int reg_ir_oft_g_ratio_by_y_5:12; ++ ++ // h0011, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_b_ratio_by_y_0 (36) ++ #define mask_of_reg_ir_oft_b_ratio_by_y_0 (0xfff) ++ unsigned int reg_ir_oft_b_ratio_by_y_0:12; ++ ++ // h0012, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_b_ratio_by_y_1 (38) ++ #define mask_of_reg_ir_oft_b_ratio_by_y_1 (0xfff) ++ unsigned int reg_ir_oft_b_ratio_by_y_1:12; ++ ++ // h0013, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_b_ratio_by_y_2 (40) ++ #define mask_of_reg_ir_oft_b_ratio_by_y_2 (0xfff) ++ unsigned int reg_ir_oft_b_ratio_by_y_2:12; ++ ++ // h0014, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_b_ratio_by_y_3 (42) ++ #define mask_of_reg_ir_oft_b_ratio_by_y_3 (0xfff) ++ unsigned int reg_ir_oft_b_ratio_by_y_3:12; ++ ++ // h0015, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_b_ratio_by_y_4 (44) ++ #define mask_of_reg_ir_oft_b_ratio_by_y_4 (0xfff) ++ unsigned int reg_ir_oft_b_ratio_by_y_4:12; ++ ++ // h0016, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 11 ++ /* 4X4 Remove-IR ratio*/ ++ #define offset_of_reg_ir_oft_b_ratio_by_y_5 (46) ++ #define mask_of_reg_ir_oft_b_ratio_by_y_5 (0xfff) ++ unsigned int reg_ir_oft_b_ratio_by_y_5:12; ++ ++ // h0017, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 14 ++ /* dummy bits*/ ++ #define offset_of_reg_ir_dummy (48) ++ #define mask_of_reg_ir_dummy (0xffff) ++ unsigned int reg_ir_dummy:16; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 11 ++ /* 4x4 compare ratio*/ ++ #define offset_of_reg_ir_oft_cmp_ratio (50) ++ #define mask_of_reg_ir_oft_cmp_ratio (0xfff) ++ unsigned int reg_ir_oft_cmp_ratio:12; ++ ++ // h0019, bit: 14 ++ /* 4x4 dirH/dirV scaler*/ ++ #define offset_of_reg_ir_dir_scaler (50) ++ #define mask_of_reg_ir_dir_scaler (0xf000) ++ unsigned int reg_ir_dir_scaler:4; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 11 ++ /* Histogram block offsetx*/ ++ #define offset_of_reg_hist_offsetx (68) ++ #define mask_of_reg_hist_offsetx (0xfff) ++ unsigned int reg_hist_offsetx:12; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 11 ++ /* Histogram block offsety*/ ++ #define offset_of_reg_hist_offsety (70) ++ #define mask_of_reg_hist_offsety (0xfff) ++ unsigned int reg_hist_offsety:12; ++ ++ // h0023, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 7 ++ /* Block Width= (reg_hist_blk_width + 1)*/ ++ #define offset_of_reg_hist_blk_width (72) ++ #define mask_of_reg_hist_blk_width (0xff) ++ unsigned int reg_hist_blk_width:8; ++ ++ // h0024, bit: 14 ++ /* Block Height= (reg_hist_blk_height + 1)*/ ++ #define offset_of_reg_hist_blk_height (72) ++ #define mask_of_reg_hist_blk_height (0xff00) ++ unsigned int reg_hist_blk_height:8; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 7 ++ /* ROI offsetx (unit: ROI)*/ ++ #define offset_of_reg_roi_offsetx (74) ++ #define mask_of_reg_roi_offsetx (0xff) ++ unsigned int reg_roi_offsetx:8; ++ ++ // h0025, bit: 14 ++ /* ROI offsety (unit: ROI)*/ ++ #define offset_of_reg_roi_offsety (74) ++ #define mask_of_reg_roi_offsety (0xff00) ++ unsigned int reg_roi_offsety:8; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 6 ++ /* ROI X size = (reg_roi_sizex + 1) ROI*/ ++ #define offset_of_reg_roi_sizex (76) ++ #define mask_of_reg_roi_sizex (0x7f) ++ unsigned int reg_roi_sizex:7; ++ ++ // h0026, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0026, bit: 14 ++ /* ROI Y size = (reg_roi_sizey + 1) ROI*/ ++ #define offset_of_reg_roi_sizey (76) ++ #define mask_of_reg_roi_sizey (0xff00) ++ unsigned int reg_roi_sizey:8; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 14 ++ /* Hist = (sum_ir * reg_roi_div) >> (16+4)*/ ++ #define offset_of_reg_roi_div (78) ++ #define mask_of_reg_roi_div (0xffff) ++ unsigned int reg_roi_div:16; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* MIU Base address (total 256 bytes)*/ ++ #define offset_of_reg_miu_base_addr (80) ++ #define mask_of_reg_miu_base_addr (0xffff) ++ unsigned int reg_miu_base_addr:16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 14 ++ /* MIU Base address (total 256 bytes)*/ ++ #define offset_of_reg_miu_base_addr_1 (82) ++ #define mask_of_reg_miu_base_addr_1 (0xffff) ++ unsigned int reg_miu_base_addr_1:16; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 14 ++ /* MIU AWB Max address*/ ++ #define offset_of_reg_rgbir_awb_max_addr (84) ++ #define mask_of_reg_rgbir_awb_max_addr (0xffff) ++ unsigned int reg_rgbir_awb_max_addr:16; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 10 ++ /* MIU AWB Max address*/ ++ #define offset_of_reg_rgbir_awb_max_addr_1 (86) ++ #define mask_of_reg_rgbir_awb_max_addr_1 (0x7ff) ++ unsigned int reg_rgbir_awb_max_addr_1:11; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 1 ++ /* MIU AWB Lenx4*/ ++ #define offset_of_reg_rgbir_awb_mi_lenx4 (88) ++ #define mask_of_reg_rgbir_awb_mi_lenx4 (0x3) ++ unsigned int reg_rgbir_awb_mi_lenx4:2; ++ ++ // h002c, bit: 3 ++ /* */ ++ unsigned int :2; ++ ++ // h002c, bit: 9 ++ /* MIU AWB Mask CycX16*/ ++ #define offset_of_reg_rgbir_awb_mi_mask_cycx16 (88) ++ #define mask_of_reg_rgbir_awb_mi_mask_cycx16 (0x3f0) ++ unsigned int reg_rgbir_awb_mi_mask_cycx16:6; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :6; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp8; ++#endif +diff --git a/drivers/mstar/isp/infinity3/infinity3e_reg_isp9.h b/drivers/mstar/isp/infinity3/infinity3e_reg_isp9.h +new file mode 100644 +index 00000000..4b9516a6 +--- /dev/null ++++ b/drivers/mstar/isp/infinity3/infinity3e_reg_isp9.h +@@ -0,0 +1,1312 @@ ++// Generate Time: 2016-10-11 16:57:25.127600 ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2016 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef __INFINITY3E_REG_ISP9__ ++#define __INFINITY3E_REG_ISP9__ ++typedef struct { ++ // h0000, bit: 0 ++ /* HDR 16to12 gain enable*/ ++ #define offset_of_reg_hdr_16to12_gain_en (0) ++ #define mask_of_reg_hdr_16to12_gain_en (0x1) ++ unsigned int reg_hdr_16to12_gain_en:1; ++ ++ // h0000, bit: 1 ++ /* HDR 16to12 gain smooth enable*/ ++ #define offset_of_reg_hdr_16to12_gbl_smooth_en (0) ++ #define mask_of_reg_hdr_16to12_gbl_smooth_en (0x2) ++ unsigned int reg_hdr_16to12_gbl_smooth_en:1; ++ ++ // h0000, bit: 5 ++ /* HDR 16to12 gain base*/ ++ #define offset_of_reg_hdr_16to12_gain_base (0) ++ #define mask_of_reg_hdr_16to12_gain_base (0x3c) ++ unsigned int reg_hdr_16to12_gain_base:4; ++ ++ // h0000, bit: 14 ++ /* */ ++ unsigned int :10; ++ ++ // h0000 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0001, bit: 14 ++ /* HDR 16to12 gain low bound*/ ++ #define offset_of_reg_hdr_16to12_gain_lw (2) ++ #define mask_of_reg_hdr_16to12_gain_lw (0xffff) ++ unsigned int reg_hdr_16to12_gain_lw:16; ++ ++ // h0001 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0002, bit: 14 ++ /* HDR 16to12 gain high bound*/ ++ #define offset_of_reg_hdr_16to12_gain_hi (4) ++ #define mask_of_reg_hdr_16to12_gain_hi (0xffff) ++ unsigned int reg_hdr_16to12_gain_hi:16; ++ ++ // h0002 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0003, bit: 14 ++ /* HDR 16to12 offset for R*/ ++ #define offset_of_reg_hdr_16to12_offset_r (6) ++ #define mask_of_reg_hdr_16to12_offset_r (0xffff) ++ unsigned int reg_hdr_16to12_offset_r:16; ++ ++ // h0003 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0004, bit: 14 ++ /* HDR 16to12 offset for G*/ ++ #define offset_of_reg_hdr_16to12_offset_g (8) ++ #define mask_of_reg_hdr_16to12_offset_g (0xffff) ++ unsigned int reg_hdr_16to12_offset_g:16; ++ ++ // h0004 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0005, bit: 14 ++ /* HDR 16to12 offset for B*/ ++ #define offset_of_reg_hdr_16to12_offset_b (10) ++ #define mask_of_reg_hdr_16to12_offset_b (0xffff) ++ unsigned int reg_hdr_16to12_offset_b:16; ++ ++ // h0005 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0006, bit: 3 ++ /* HDR 16to12 curve x 0*/ ++ #define offset_of_reg_hdr_16to12_curve_x_0 (12) ++ #define mask_of_reg_hdr_16to12_curve_x_0 (0xf) ++ unsigned int reg_hdr_16to12_curve_x_0:4; ++ ++ // h0006, bit: 7 ++ /* HDR 16to12 curve x 1*/ ++ #define offset_of_reg_hdr_16to12_curve_x_1 (12) ++ #define mask_of_reg_hdr_16to12_curve_x_1 (0xf0) ++ unsigned int reg_hdr_16to12_curve_x_1:4; ++ ++ // h0006, bit: 11 ++ /* HDR 16to12 curve x 2*/ ++ #define offset_of_reg_hdr_16to12_curve_x_2 (12) ++ #define mask_of_reg_hdr_16to12_curve_x_2 (0xf00) ++ unsigned int reg_hdr_16to12_curve_x_2:4; ++ ++ // h0006, bit: 14 ++ /* HDR 16to12 curve x 3*/ ++ #define offset_of_reg_hdr_16to12_curve_x_3 (12) ++ #define mask_of_reg_hdr_16to12_curve_x_3 (0xf000) ++ unsigned int reg_hdr_16to12_curve_x_3:4; ++ ++ // h0006 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0007, bit: 3 ++ /* HDR 16to12 curve x 4*/ ++ #define offset_of_reg_hdr_16to12_curve_x_4 (14) ++ #define mask_of_reg_hdr_16to12_curve_x_4 (0xf) ++ unsigned int reg_hdr_16to12_curve_x_4:4; ++ ++ // h0007, bit: 7 ++ /* HDR 16to12 curve x 5*/ ++ #define offset_of_reg_hdr_16to12_curve_x_5 (14) ++ #define mask_of_reg_hdr_16to12_curve_x_5 (0xf0) ++ unsigned int reg_hdr_16to12_curve_x_5:4; ++ ++ // h0007, bit: 11 ++ /* HDR 16to12 curve x 6*/ ++ #define offset_of_reg_hdr_16to12_curve_x_6 (14) ++ #define mask_of_reg_hdr_16to12_curve_x_6 (0xf00) ++ unsigned int reg_hdr_16to12_curve_x_6:4; ++ ++ // h0007, bit: 14 ++ /* HDR 16to12 curve x 7*/ ++ #define offset_of_reg_hdr_16to12_curve_x_7 (14) ++ #define mask_of_reg_hdr_16to12_curve_x_7 (0xf000) ++ unsigned int reg_hdr_16to12_curve_x_7:4; ++ ++ // h0007 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0008, bit: 3 ++ /* HDR 16to12 curve x 8*/ ++ #define offset_of_reg_hdr_16to12_curve_x_8 (16) ++ #define mask_of_reg_hdr_16to12_curve_x_8 (0xf) ++ unsigned int reg_hdr_16to12_curve_x_8:4; ++ ++ // h0008, bit: 7 ++ /* HDR 16to12 curve x 9*/ ++ #define offset_of_reg_hdr_16to12_curve_x_9 (16) ++ #define mask_of_reg_hdr_16to12_curve_x_9 (0xf0) ++ unsigned int reg_hdr_16to12_curve_x_9:4; ++ ++ // h0008, bit: 11 ++ /* HDR 16to12 curve x 10*/ ++ #define offset_of_reg_hdr_16to12_curve_x_10 (16) ++ #define mask_of_reg_hdr_16to12_curve_x_10 (0xf00) ++ unsigned int reg_hdr_16to12_curve_x_10:4; ++ ++ // h0008, bit: 14 ++ /* HDR 16to12 curve x 11*/ ++ #define offset_of_reg_hdr_16to12_curve_x_11 (16) ++ #define mask_of_reg_hdr_16to12_curve_x_11 (0xf000) ++ unsigned int reg_hdr_16to12_curve_x_11:4; ++ ++ // h0008 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0009, bit: 3 ++ /* HDR 16to12 curve x 12*/ ++ #define offset_of_reg_hdr_16to12_curve_x_12 (18) ++ #define mask_of_reg_hdr_16to12_curve_x_12 (0xf) ++ unsigned int reg_hdr_16to12_curve_x_12:4; ++ ++ // h0009, bit: 7 ++ /* HDR 16to12 curve x 13*/ ++ #define offset_of_reg_hdr_16to12_curve_x_13 (18) ++ #define mask_of_reg_hdr_16to12_curve_x_13 (0xf0) ++ unsigned int reg_hdr_16to12_curve_x_13:4; ++ ++ // h0009, bit: 11 ++ /* HDR 16to12 curve x 14*/ ++ #define offset_of_reg_hdr_16to12_curve_x_14 (18) ++ #define mask_of_reg_hdr_16to12_curve_x_14 (0xf00) ++ unsigned int reg_hdr_16to12_curve_x_14:4; ++ ++ // h0009, bit: 14 ++ /* HDR 16to12 curve x 15*/ ++ #define offset_of_reg_hdr_16to12_curve_x_15 (18) ++ #define mask_of_reg_hdr_16to12_curve_x_15 (0xf000) ++ unsigned int reg_hdr_16to12_curve_x_15:4; ++ ++ // h0009 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000a, bit: 3 ++ /* HDR 16to12 curve x 16*/ ++ #define offset_of_reg_hdr_16to12_curve_x_16 (20) ++ #define mask_of_reg_hdr_16to12_curve_x_16 (0xf) ++ unsigned int reg_hdr_16to12_curve_x_16:4; ++ ++ // h000a, bit: 7 ++ /* HDR 16to12 curve x 17*/ ++ #define offset_of_reg_hdr_16to12_curve_x_17 (20) ++ #define mask_of_reg_hdr_16to12_curve_x_17 (0xf0) ++ unsigned int reg_hdr_16to12_curve_x_17:4; ++ ++ // h000a, bit: 11 ++ /* HDR 16to12 curve x 18*/ ++ #define offset_of_reg_hdr_16to12_curve_x_18 (20) ++ #define mask_of_reg_hdr_16to12_curve_x_18 (0xf00) ++ unsigned int reg_hdr_16to12_curve_x_18:4; ++ ++ // h000a, bit: 14 ++ /* HDR 16to12 curve x 19*/ ++ #define offset_of_reg_hdr_16to12_curve_x_19 (20) ++ #define mask_of_reg_hdr_16to12_curve_x_19 (0xf000) ++ unsigned int reg_hdr_16to12_curve_x_19:4; ++ ++ // h000a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000b, bit: 14 ++ /* HDR 16to12 curve 0*/ ++ #define offset_of_reg_hdr_16to12_curve_0 (22) ++ #define mask_of_reg_hdr_16to12_curve_0 (0xffff) ++ unsigned int reg_hdr_16to12_curve_0:16; ++ ++ // h000b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000c, bit: 14 ++ /* HDR 16to12 curve 1*/ ++ #define offset_of_reg_hdr_16to12_curve_1 (24) ++ #define mask_of_reg_hdr_16to12_curve_1 (0xffff) ++ unsigned int reg_hdr_16to12_curve_1:16; ++ ++ // h000c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000d, bit: 14 ++ /* HDR 16to12 curve 2*/ ++ #define offset_of_reg_hdr_16to12_curve_2 (26) ++ #define mask_of_reg_hdr_16to12_curve_2 (0xffff) ++ unsigned int reg_hdr_16to12_curve_2:16; ++ ++ // h000d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000e, bit: 14 ++ /* HDR 16to12 curve 3*/ ++ #define offset_of_reg_hdr_16to12_curve_3 (28) ++ #define mask_of_reg_hdr_16to12_curve_3 (0xffff) ++ unsigned int reg_hdr_16to12_curve_3:16; ++ ++ // h000e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h000f, bit: 14 ++ /* HDR 16to12 curve 4*/ ++ #define offset_of_reg_hdr_16to12_curve_4 (30) ++ #define mask_of_reg_hdr_16to12_curve_4 (0xffff) ++ unsigned int reg_hdr_16to12_curve_4:16; ++ ++ // h000f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0010, bit: 14 ++ /* HDR 16to12 curve 5*/ ++ #define offset_of_reg_hdr_16to12_curve_5 (32) ++ #define mask_of_reg_hdr_16to12_curve_5 (0xffff) ++ unsigned int reg_hdr_16to12_curve_5:16; ++ ++ // h0010 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0011, bit: 14 ++ /* HDR 16to12 curve 6*/ ++ #define offset_of_reg_hdr_16to12_curve_6 (34) ++ #define mask_of_reg_hdr_16to12_curve_6 (0xffff) ++ unsigned int reg_hdr_16to12_curve_6:16; ++ ++ // h0011 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0012, bit: 14 ++ /* HDR 16to12 curve 7*/ ++ #define offset_of_reg_hdr_16to12_curve_7 (36) ++ #define mask_of_reg_hdr_16to12_curve_7 (0xffff) ++ unsigned int reg_hdr_16to12_curve_7:16; ++ ++ // h0012 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0013, bit: 14 ++ /* HDR 16to12 curve 8*/ ++ #define offset_of_reg_hdr_16to12_curve_8 (38) ++ #define mask_of_reg_hdr_16to12_curve_8 (0xffff) ++ unsigned int reg_hdr_16to12_curve_8:16; ++ ++ // h0013 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0014, bit: 14 ++ /* HDR 16to12 curve 9*/ ++ #define offset_of_reg_hdr_16to12_curve_9 (40) ++ #define mask_of_reg_hdr_16to12_curve_9 (0xffff) ++ unsigned int reg_hdr_16to12_curve_9:16; ++ ++ // h0014 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0015, bit: 14 ++ /* HDR 16to12 curve 10*/ ++ #define offset_of_reg_hdr_16to12_curve_10 (42) ++ #define mask_of_reg_hdr_16to12_curve_10 (0xffff) ++ unsigned int reg_hdr_16to12_curve_10:16; ++ ++ // h0015 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0016, bit: 14 ++ /* HDR 16to12 curve 11*/ ++ #define offset_of_reg_hdr_16to12_curve_11 (44) ++ #define mask_of_reg_hdr_16to12_curve_11 (0xffff) ++ unsigned int reg_hdr_16to12_curve_11:16; ++ ++ // h0016 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0017, bit: 14 ++ /* HDR 16to12 curve 12*/ ++ #define offset_of_reg_hdr_16to12_curve_12 (46) ++ #define mask_of_reg_hdr_16to12_curve_12 (0xffff) ++ unsigned int reg_hdr_16to12_curve_12:16; ++ ++ // h0017 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0018, bit: 14 ++ /* HDR 16to12 curve 13*/ ++ #define offset_of_reg_hdr_16to12_curve_13 (48) ++ #define mask_of_reg_hdr_16to12_curve_13 (0xffff) ++ unsigned int reg_hdr_16to12_curve_13:16; ++ ++ // h0018 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0019, bit: 14 ++ /* HDR 16to12 curve 14*/ ++ #define offset_of_reg_hdr_16to12_curve_14 (50) ++ #define mask_of_reg_hdr_16to12_curve_14 (0xffff) ++ unsigned int reg_hdr_16to12_curve_14:16; ++ ++ // h0019 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001a, bit: 14 ++ /* HDR 16to12 curve 15*/ ++ #define offset_of_reg_hdr_16to12_curve_15 (52) ++ #define mask_of_reg_hdr_16to12_curve_15 (0xffff) ++ unsigned int reg_hdr_16to12_curve_15:16; ++ ++ // h001a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001b, bit: 14 ++ /* HDR 16to12 curve 16*/ ++ #define offset_of_reg_hdr_16to12_curve_16 (54) ++ #define mask_of_reg_hdr_16to12_curve_16 (0xffff) ++ unsigned int reg_hdr_16to12_curve_16:16; ++ ++ // h001b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001c, bit: 14 ++ /* HDR 16to12 curve 17*/ ++ #define offset_of_reg_hdr_16to12_curve_17 (56) ++ #define mask_of_reg_hdr_16to12_curve_17 (0xffff) ++ unsigned int reg_hdr_16to12_curve_17:16; ++ ++ // h001c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001d, bit: 14 ++ /* HDR 16to12 curve 18*/ ++ #define offset_of_reg_hdr_16to12_curve_18 (58) ++ #define mask_of_reg_hdr_16to12_curve_18 (0xffff) ++ unsigned int reg_hdr_16to12_curve_18:16; ++ ++ // h001d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001e, bit: 14 ++ /* HDR 16to12 curve 19*/ ++ #define offset_of_reg_hdr_16to12_curve_19 (60) ++ #define mask_of_reg_hdr_16to12_curve_19 (0xffff) ++ unsigned int reg_hdr_16to12_curve_19:16; ++ ++ // h001e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h001f, bit: 14 ++ /* HDR 16to12 curve 20*/ ++ #define offset_of_reg_hdr_16to12_curve_20 (62) ++ #define mask_of_reg_hdr_16to12_curve_20 (0xffff) ++ unsigned int reg_hdr_16to12_curve_20:16; ++ ++ // h001f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0020, bit: 0 ++ /* Histogram enable*/ ++ #define offset_of_reg_hdr_16to12_hist_en (64) ++ #define mask_of_reg_hdr_16to12_hist_en (0x1) ++ unsigned int reg_hdr_16to12_hist_en:1; ++ ++ // h0020, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0020 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0021, bit: 11 ++ /* Histogram block offsetx*/ ++ #define offset_of_reg_hdr_16to12_hist_offsetx (66) ++ #define mask_of_reg_hdr_16to12_hist_offsetx (0xfff) ++ unsigned int reg_hdr_16to12_hist_offsetx:12; ++ ++ // h0021, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0021 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0022, bit: 11 ++ /* Histogram block offsety*/ ++ #define offset_of_reg_hdr_16to12_hist_offsety (68) ++ #define mask_of_reg_hdr_16to12_hist_offsety (0xfff) ++ unsigned int reg_hdr_16to12_hist_offsety:12; ++ ++ // h0022, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0022 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0023, bit: 7 ++ /* Block Width= (reg_hist_blk_width + 1)*/ ++ #define offset_of_reg_hdr_16to12_hist_blk_width (70) ++ #define mask_of_reg_hdr_16to12_hist_blk_width (0xff) ++ unsigned int reg_hdr_16to12_hist_blk_width:8; ++ ++ // h0023, bit: 14 ++ /* Block Height= (reg_hist_blk_height + 1)*/ ++ #define offset_of_reg_hdr_16to12_hist_blk_height (70) ++ #define mask_of_reg_hdr_16to12_hist_blk_height (0xff00) ++ unsigned int reg_hdr_16to12_hist_blk_height:8; ++ ++ // h0023 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0024, bit: 7 ++ /* ROI offsetx (unit: ROI)*/ ++ #define offset_of_reg_hdr_16to12_roi_offsetx (72) ++ #define mask_of_reg_hdr_16to12_roi_offsetx (0xff) ++ unsigned int reg_hdr_16to12_roi_offsetx:8; ++ ++ // h0024, bit: 14 ++ /* ROI offsety (unit: ROI)*/ ++ #define offset_of_reg_hdr_16to12_roi_offsety (72) ++ #define mask_of_reg_hdr_16to12_roi_offsety (0xff00) ++ unsigned int reg_hdr_16to12_roi_offsety:8; ++ ++ // h0024 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0025, bit: 6 ++ /* ROI X size = (reg_roi_sizex + 1) ROI*/ ++ #define offset_of_reg_hdr_16to12_roi_sizex (74) ++ #define mask_of_reg_hdr_16to12_roi_sizex (0x7f) ++ unsigned int reg_hdr_16to12_roi_sizex:7; ++ ++ // h0025, bit: 7 ++ /* */ ++ unsigned int :1; ++ ++ // h0025, bit: 14 ++ /* ROI Y size = (reg_roi_sizey + 1) ROI*/ ++ #define offset_of_reg_hdr_16to12_roi_sizey (74) ++ #define mask_of_reg_hdr_16to12_roi_sizey (0xff00) ++ unsigned int reg_hdr_16to12_roi_sizey:8; ++ ++ // h0025 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0026, bit: 14 ++ /* Hist = (sum_ir * reg_roi_div) >> (16+4)*/ ++ #define offset_of_reg_hdr_16to12_roi_div (76) ++ #define mask_of_reg_hdr_16to12_roi_div (0xffff) ++ unsigned int reg_hdr_16to12_roi_div:16; ++ ++ // h0026 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0027, bit: 14 ++ /* MIU Base address (total 256 bytes)*/ ++ #define offset_of_reg_hdr_16to12_miu_base_addr (78) ++ #define mask_of_reg_hdr_16to12_miu_base_addr (0xffff) ++ unsigned int reg_hdr_16to12_miu_base_addr:16; ++ ++ // h0027 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0028, bit: 14 ++ /* MIU Base address (total 256 bytes)*/ ++ #define offset_of_reg_hdr_16to12_miu_base_addr_1 (80) ++ #define mask_of_reg_hdr_16to12_miu_base_addr_1 (0xffff) ++ unsigned int reg_hdr_16to12_miu_base_addr_1:16; ++ ++ // h0028 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0029, bit: 1 ++ /* Histogram arbiter mi lenx4*/ ++ #define offset_of_reg_hdr_16to12_mi_lenx4 (82) ++ #define mask_of_reg_hdr_16to12_mi_lenx4 (0x3) ++ unsigned int reg_hdr_16to12_mi_lenx4:2; ++ ++ // h0029, bit: 7 ++ /* Histogram arbiter mi mask cycx4*/ ++ #define offset_of_reg_hdr_16to12_mi_mask_cycx4 (82) ++ #define mask_of_reg_hdr_16to12_mi_mask_cycx4 (0xfc) ++ unsigned int reg_hdr_16to12_mi_mask_cycx4:6; ++ ++ // h0029, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0029 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002a, bit: 14 ++ /* Histogram arbiter max wadr*/ ++ #define offset_of_reg_hdr_16to12_max_wadr (84) ++ #define mask_of_reg_hdr_16to12_max_wadr (0xffff) ++ unsigned int reg_hdr_16to12_max_wadr:16; ++ ++ // h002a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002b, bit: 10 ++ /* Histogram arbiter max wadr*/ ++ #define offset_of_reg_hdr_16to12_max_wadr_1 (86) ++ #define mask_of_reg_hdr_16to12_max_wadr_1 (0x7ff) ++ unsigned int reg_hdr_16to12_max_wadr_1:11; ++ ++ // h002b, bit: 14 ++ /* */ ++ unsigned int :5; ++ ++ // h002b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h002f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h002f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0030, bit: 0 ++ /* Decompressor enable*/ ++ #define offset_of_reg_decomp_en (96) ++ #define mask_of_reg_decomp_en (0x1) ++ unsigned int reg_decomp_en:1; ++ ++ // h0030, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0030 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0031, bit: 14 ++ /* Decomp factor 0 range 0*/ ++ #define offset_of_reg_decomp_r0_f0 (98) ++ #define mask_of_reg_decomp_r0_f0 (0xffff) ++ unsigned int reg_decomp_r0_f0:16; ++ ++ // h0031 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0032, bit: 3 ++ /* Decomp factor 1 range 0*/ ++ #define offset_of_reg_decomp_r0_f1 (100) ++ #define mask_of_reg_decomp_r0_f1 (0xf) ++ unsigned int reg_decomp_r0_f1:4; ++ ++ // h0032, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0032 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0033, bit: 14 ++ /* Decomp factor 2 range 0*/ ++ #define offset_of_reg_decomp_r0_f2 (102) ++ #define mask_of_reg_decomp_r0_f2 (0xffff) ++ unsigned int reg_decomp_r0_f2:16; ++ ++ // h0033 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0034, bit: 14 ++ /* Decomp factor 0 range 1*/ ++ #define offset_of_reg_decomp_r1_f0 (104) ++ #define mask_of_reg_decomp_r1_f0 (0xffff) ++ unsigned int reg_decomp_r1_f0:16; ++ ++ // h0034 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0035, bit: 3 ++ /* Decomp factor 1 range 1*/ ++ #define offset_of_reg_decomp_r1_f1 (106) ++ #define mask_of_reg_decomp_r1_f1 (0xf) ++ unsigned int reg_decomp_r1_f1:4; ++ ++ // h0035, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0035 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0036, bit: 14 ++ /* Decomp factor 2 range 1*/ ++ #define offset_of_reg_decomp_r1_f2 (108) ++ #define mask_of_reg_decomp_r1_f2 (0xffff) ++ unsigned int reg_decomp_r1_f2:16; ++ ++ // h0036 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0037, bit: 14 ++ /* Decomp factor 0 range 2*/ ++ #define offset_of_reg_decomp_r2_f0 (110) ++ #define mask_of_reg_decomp_r2_f0 (0xffff) ++ unsigned int reg_decomp_r2_f0:16; ++ ++ // h0037 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0038, bit: 3 ++ /* Decomp factor 1 range 2*/ ++ #define offset_of_reg_decomp_r2_f1 (112) ++ #define mask_of_reg_decomp_r2_f1 (0xf) ++ unsigned int reg_decomp_r2_f1:4; ++ ++ // h0038, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h0038 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0039, bit: 14 ++ /* Decomp factor 2 range 2*/ ++ #define offset_of_reg_decomp_r2_f2 (114) ++ #define mask_of_reg_decomp_r2_f2 (0xffff) ++ unsigned int reg_decomp_r2_f2:16; ++ ++ // h0039 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003a, bit: 14 ++ /* Decomp factor 0 range 3*/ ++ #define offset_of_reg_decomp_r3_f0 (116) ++ #define mask_of_reg_decomp_r3_f0 (0xffff) ++ unsigned int reg_decomp_r3_f0:16; ++ ++ // h003a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003b, bit: 3 ++ /* Decomp factor 1 range 3*/ ++ #define offset_of_reg_decomp_r3_f1 (118) ++ #define mask_of_reg_decomp_r3_f1 (0xf) ++ unsigned int reg_decomp_r3_f1:4; ++ ++ // h003b, bit: 14 ++ /* */ ++ unsigned int :12; ++ ++ // h003b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003c, bit: 14 ++ /* Decomp factor 2 range 3*/ ++ #define offset_of_reg_decomp_r3_f2 (120) ++ #define mask_of_reg_decomp_r3_f2 (0xffff) ++ unsigned int reg_decomp_r3_f2:16; ++ ++ // h003c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003d, bit: 14 ++ /* Decomp range 0*/ ++ #define offset_of_reg_decomp_range0 (122) ++ #define mask_of_reg_decomp_range0 (0xffff) ++ unsigned int reg_decomp_range0:16; ++ ++ // h003d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003e, bit: 14 ++ /* Decomp range 1*/ ++ #define offset_of_reg_decomp_range1 (124) ++ #define mask_of_reg_decomp_range1 (0xffff) ++ unsigned int reg_decomp_range1:16; ++ ++ // h003e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h003f, bit: 14 ++ /* Decomp range 2*/ ++ #define offset_of_reg_decomp_range2 (126) ++ #define mask_of_reg_decomp_range2 (0xffff) ++ unsigned int reg_decomp_range2:16; ++ ++ // h003f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0040, bit: 0 ++ /* Histogram by pixel enable*/ ++ #define offset_of_reg_histo_p_en (128) ++ #define mask_of_reg_histo_p_en (0x1) ++ unsigned int reg_histo_p_en:1; ++ ++ // h0040, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0040 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0041, bit: 11 ++ /* Histogram by pixel horizontal offset*/ ++ #define offset_of_reg_histo_p_x_offset (130) ++ #define mask_of_reg_histo_p_x_offset (0xfff) ++ unsigned int reg_histo_p_x_offset:12; ++ ++ // h0041, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0041 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0042, bit: 11 ++ /* Histogram by pixel vertical offset*/ ++ #define offset_of_reg_histo_p_y_offset (132) ++ #define mask_of_reg_histo_p_y_offset (0xfff) ++ unsigned int reg_histo_p_y_offset:12; ++ ++ // h0042, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0042 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0043, bit: 11 ++ /* Histogram by pixel horizontal size minus1*/ ++ #define offset_of_reg_histo_p_x_size_m1 (134) ++ #define mask_of_reg_histo_p_x_size_m1 (0xfff) ++ unsigned int reg_histo_p_x_size_m1:12; ++ ++ // h0043, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0043 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0044, bit: 11 ++ /* Histogram by pixel vertical size minus 1*/ ++ #define offset_of_reg_histo_p_y_size_m1 (136) ++ #define mask_of_reg_histo_p_y_size_m1 (0xfff) ++ unsigned int reg_histo_p_y_size_m1:12; ++ ++ // h0044, bit: 14 ++ /* */ ++ unsigned int :4; ++ ++ // h0044 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0045, bit: 7 ++ /* Histogram by pixel Ratio R*/ ++ #define offset_of_reg_histo_p_ratio_r (138) ++ #define mask_of_reg_histo_p_ratio_r (0xff) ++ unsigned int reg_histo_p_ratio_r:8; ++ ++ // h0045, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0045 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0046, bit: 7 ++ /* Histogram by pixel Ratio G*/ ++ #define offset_of_reg_histo_p_ratio_g (140) ++ #define mask_of_reg_histo_p_ratio_g (0xff) ++ unsigned int reg_histo_p_ratio_g:8; ++ ++ // h0046, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0046 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0047, bit: 7 ++ /* Histogram by pixel Ratio B*/ ++ #define offset_of_reg_histo_p_ratio_b (142) ++ #define mask_of_reg_histo_p_ratio_b (0xff) ++ unsigned int reg_histo_p_ratio_b:8; ++ ++ // h0047, bit: 14 ++ /* */ ++ unsigned int :8; ++ ++ // h0047 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0048, bit: 0 ++ /* Histogram by pixel SW mode enable*/ ++ #define offset_of_reg_histo_p_sw_en (144) ++ #define mask_of_reg_histo_p_sw_en (0x1) ++ unsigned int reg_histo_p_sw_en:1; ++ ++ // h0048, bit: 14 ++ /* */ ++ unsigned int :15; ++ ++ // h0048 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0049, bit: 0 ++ /* Histogram by pixel SW mode inverse chip enable*/ ++ #define offset_of_reg_histo_p_sw_ce_n (146) ++ #define mask_of_reg_histo_p_sw_ce_n (0x1) ++ unsigned int reg_histo_p_sw_ce_n:1; ++ ++ // h0049, bit: 7 ++ /* */ ++ unsigned int :7; ++ ++ // h0049, bit: 14 ++ /* Histogram by pixel SW mode address*/ ++ #define offset_of_reg_histo_p_sw_adr (146) ++ #define mask_of_reg_histo_p_sw_adr (0xff00) ++ unsigned int reg_histo_p_sw_adr:8; ++ ++ // h0049 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004a, bit: 14 ++ /* Histogram by pixel R SRAM read data*/ ++ #define offset_of_reg_histo_p_r_sram_rd (148) ++ #define mask_of_reg_histo_p_r_sram_rd (0xffff) ++ unsigned int reg_histo_p_r_sram_rd:16; ++ ++ // h004a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004b, bit: 4 ++ /* Histogram by pixel R SRAM read data*/ ++ #define offset_of_reg_histo_p_r_sram_rd_1 (150) ++ #define mask_of_reg_histo_p_r_sram_rd_1 (0x1f) ++ unsigned int reg_histo_p_r_sram_rd_1:5; ++ ++ // h004b, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h004b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004c, bit: 14 ++ /* Histogram by pixel G SRAM read data*/ ++ #define offset_of_reg_histo_p_g_sram_rd (152) ++ #define mask_of_reg_histo_p_g_sram_rd (0xffff) ++ unsigned int reg_histo_p_g_sram_rd:16; ++ ++ // h004c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004d, bit: 4 ++ /* Histogram by pixel G SRAM read data*/ ++ #define offset_of_reg_histo_p_g_sram_rd_1 (154) ++ #define mask_of_reg_histo_p_g_sram_rd_1 (0x1f) ++ unsigned int reg_histo_p_g_sram_rd_1:5; ++ ++ // h004d, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h004d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004e, bit: 14 ++ /* Histogram by pixel B SRAM read data*/ ++ #define offset_of_reg_histo_p_b_sram_rd (156) ++ #define mask_of_reg_histo_p_b_sram_rd (0xffff) ++ unsigned int reg_histo_p_b_sram_rd:16; ++ ++ // h004e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h004f, bit: 4 ++ /* Histogram by pixel B SRAM read data*/ ++ #define offset_of_reg_histo_p_b_sram_rd_1 (158) ++ #define mask_of_reg_histo_p_b_sram_rd_1 (0x1f) ++ unsigned int reg_histo_p_b_sram_rd_1:5; ++ ++ // h004f, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h004f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0050, bit: 14 ++ /* Histogram by pixel Y SRAM read data*/ ++ #define offset_of_reg_histo_p_y_sram_rd (160) ++ #define mask_of_reg_histo_p_y_sram_rd (0xffff) ++ unsigned int reg_histo_p_y_sram_rd:16; ++ ++ // h0050 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0051, bit: 4 ++ /* Histogram by pixel Y SRAM read data*/ ++ #define offset_of_reg_histo_p_y_sram_rd_1 (162) ++ #define mask_of_reg_histo_p_y_sram_rd_1 (0x1f) ++ unsigned int reg_histo_p_y_sram_rd_1:5; ++ ++ // h0051, bit: 14 ++ /* */ ++ unsigned int :11; ++ ++ // h0051 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0052, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0052 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0053, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0053 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0054, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0054 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0055, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0055 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0056, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0056 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0057, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0057 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0058, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0058 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0059, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0059 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h005f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h005f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0060, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0060 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0061, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0061 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0062, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0062 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0063, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0063 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0064, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0064 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0065, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0065 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0066, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0066 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0067, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0067 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0068, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0068 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0069, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0069 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h006f, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h006f ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0070, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0070 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0071, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0071 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0072, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0072 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0073, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0073 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0074, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0074 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0075, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0075 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0076, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0076 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0077, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0077 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0078, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0078 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h0079, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h0079 ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007a, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007a ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007b, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007b ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007c, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007c ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007d, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007d ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007e, bit: 14 ++ /* */ ++ unsigned int :16; ++ ++ // h007e ++ unsigned int /* padding 16 bit */:16; ++ ++ // h007f, bit: 14 ++ /* For opr test*/ ++ #define offset_of_reg_hdr_16to12_dummy (254) ++ #define mask_of_reg_hdr_16to12_dummy (0xffff) ++ unsigned int reg_hdr_16to12_dummy:16; ++ ++ // h007f ++ unsigned int /* padding 16 bit */:16; ++ ++} __attribute__((packed, aligned(1))) infinity3e_reg_isp9; ++#endif +diff --git a/drivers/mstar/ive/Kconfig b/drivers/mstar/ive/Kconfig +new file mode 100644 +index 00000000..14d36d6e +--- /dev/null ++++ b/drivers/mstar/ive/Kconfig +@@ -0,0 +1,3 @@ ++config MS_IVE ++ tristate "Mstar IVE driver" ++ help +diff --git a/drivers/mstar/ive/Makefile b/drivers/mstar/ive/Makefile +new file mode 100644 +index 00000000..50e6c06f +--- /dev/null ++++ b/drivers/mstar/ive/Makefile +@@ -0,0 +1,15 @@ ++# ++# Makefile for MStar Infinity3 IVE device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/ive ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++ccflags-$(CONFIG_MS_IVE) += -DMSOS_TYPE_LINUX_KERNEL ++ ++# files ++obj-$(CONFIG_MS_IVE) += mstar_ive.o ++mstar_ive-y := mdrv_ive.o \ ++ hal_ive.o \ ++ drv_ive.o \ ++ hal_ive_simulate.o +diff --git a/drivers/mstar/ive/drv_ive.c b/drivers/mstar/ive/drv_ive.c +new file mode 100644 +index 00000000..1ed90e4d +--- /dev/null ++++ b/drivers/mstar/ive/drv_ive.c +@@ -0,0 +1,597 @@ ++#include "mdrv_ive.h" ++#include "drv_ive.h" ++#include "hal_ive.h" ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++ ++#define MINMUN_WIDTH 16 ++#define MINMUN_HEIGHT 5 ++ ++typedef struct { ++ struct list_head list; ++ ive_file_data *file_data; ++} ive_request_data; ++ ++/******************************************************************************************************************* ++ * drv_ive_extract_request ++ * Extract a request from waiting list ++ * The request is removed from list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * ++ * Return: ++ * File data of IVE driver ++ */ ++static ive_file_data* drv_ive_extract_request(ive_drv_handle *handle) ++{ ++ struct platform_device *pdev = handle->pdev; ++ ive_request_data *list_data = NULL; ++ ive_file_data *file_data = NULL; ++ ++ if (list_empty(&handle->request_list)) ++ { ++ return NULL; ++ } ++ ++ list_data = list_first_entry(&handle->request_list, ive_request_data, list); ++ if (list_data != NULL) { ++ list_del(handle->request_list.next); ++ file_data = list_data->file_data; ++ IVE_MSG(IVE_MSG_DBG, "extract: 0x%p, 0x%p\n", list_data, file_data); ++ devm_kfree(&pdev->dev, list_data); ++ } else { ++ IVE_MSG(IVE_MSG_DBG, "extract: 0x%p\n", list_data); ++ } ++ ++ return file_data; ++} ++ ++ ++/******************************************************************************************************************* ++ * drv_ive_get_request ++ * Get a request from waiting list ++ * The request is still kpet in list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * ++ * Return: ++ * File data of IVE driver ++ */ ++static ive_file_data* drv_ive_get_request(ive_drv_handle *handle) ++{ ++ ive_request_data *list_data = NULL; ++ ++ if (list_empty(&handle->request_list)) ++ { ++ return NULL; ++ } ++ ++ list_data = list_first_entry(&handle->request_list, ive_request_data, list); ++ if (list_data != NULL) { ++ IVE_MSG(IVE_MSG_DBG, "get: 0x%p, 0x%p\n", list_data, list_data->file_data); ++ return list_data->file_data; ++ } else { ++ IVE_MSG(IVE_MSG_DBG, "get: 0x%p\n", list_data); ++ } ++ ++ return NULL; ++} ++ ++/******************************************************************************************************************* ++ * drv_ive_add_request ++ * Add a request to waiting list ++ * ++ * Parameters: ++ * ive_drv_handle: driver handle ++ * file_data: File data of IVE driver ++ * ++ * Return: ++ * none ++ */ ++static ive_request_data* drv_ive_add_request(ive_drv_handle *handle, ive_file_data *file_data) ++{ ++ struct platform_device *pdev = handle->pdev; ++ ive_request_data *list_data; ++ ++ list_data = devm_kcalloc(&pdev->dev, 1, sizeof(ive_request_data), GFP_KERNEL); ++ if (list_data == NULL) { ++ return NULL; ++ } ++ ++ list_data->file_data = file_data; ++ ++ IVE_MSG(IVE_MSG_DBG, "add: 0x%p, 0x%p\n", list_data, file_data); ++ ++ if (list_data != NULL) { ++ list_add_tail(&list_data->list, &handle->request_list); ++ } ++ ++ return list_data; ++} ++ ++/******************************************************************************************************************* ++ * drv_ive_check_config ++ * Check the configuration ++ * ++ * Parameters: ++ * config: IO configuration ++ * ++ * Return: ++ * standard return enum ++ */ ++static IVE_IOC_ERROR drv_ive_check_config(ive_ioc_config *config) ++{ ++ switch (config->op_type) ++ { ++ case IVE_IOC_OP_TYPE_SAD: ++ break; ++ ++ case IVE_IOC_OP_TYPE_NCC: ++ case IVE_IOC_OP_TYPE_MAP: ++ case IVE_IOC_OP_TYPE_HISTOGRAM: ++ return IVE_IOC_ERROR_NONE; ++ ++ default: ++ if (config->input.width != config->output.width || config->input.height != config->output.height) { ++ IVE_MSG(IVE_MSG_ERR, "Input and output size are not the same\n"); ++ return IVE_IOC_ERROR_IN_OUT_SIZE_DIFFERENT; ++ } ++ break; ++ } ++ ++ if (config->input.width < MINMUN_WIDTH || config->input.height < MINMUN_HEIGHT) { ++ IVE_MSG(IVE_MSG_ERR, "The minimum withd/height is %d\n", MINMUN_WIDTH); ++ return IVE_IOC_ERROR_IMG_TOO_SMALL; ++ } ++ ++ return IVE_IOC_ERROR_NONE; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_sync_image ++ * Sync image ++ * ++ * Parameters: ++ * handle: device handle ++ * image: image ++ * direct: DMA directon ++ * ++ * Return: ++ * None ++ */ ++static void ive_drv_sync_image(ive_drv_handle *handle, ive_ioc_image *image, enum dma_data_direction direct) ++{ ++ int i, size, byte_per_pixel; ++ ++ // IVE_MSG(IVE_MSG_DBG, "sync buffer %p, format 0x%x\n", image->address[0], image->format); ++ ++ switch (image->format) ++ { ++ case IVE_IOC_IMAGE_FORMAT_B8C1: ++ byte_per_pixel = sizeof(u8); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B16C1: ++ byte_per_pixel = sizeof(u16); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B32C1: ++ byte_per_pixel = sizeof(u32); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B64C1: ++ byte_per_pixel = sizeof(u64); ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B8C3_PACK: ++ byte_per_pixel = sizeof(u8) * 3; ++ IVE_MSG(IVE_MSG_DBG, "case %d: byte_per_pixel = %d (%d)", image->format, byte_per_pixel, sizeof(u64) ); ++ break; ++ ++ case IVE_IOC_IMAGE_FORMAT_B8C3_PLAN: ++ size = image->stride[0] * image->height * sizeof(u8); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[0], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[1], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[2], size, direct); ++ return; ++ ++ case IVE_IOC_IMAGE_FORMAT_420SP: ++ size = image->stride[0] * image->height * sizeof(u8); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[0], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[1], size/2, direct); ++ return; ++ ++ case IVE_IOC_IMAGE_FORMAT_422SP: ++ size = image->stride[0] * image->height * sizeof(u8); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[0], size, direct); ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[1], size, direct); ++ return; ++ ++ default: ++ return; ++ } ++ ++ // sync for single channel, HW use multi channel to represent multi inputs ++ for (i=0; i<3; i++) ++ { ++ if (image->address[i] != NULL) ++ { ++ size = image->stride[i] * image->height * byte_per_pixel; ++ dma_sync_single_for_device(NULL, (dma_addr_t)image->address[i], size, direct); ++ IVE_MSG(IVE_MSG_DBG, "sync buffer %p, format %x, size %d * %d * %d = %d\n", image->address[i], image->format, image->stride[i], image->height, byte_per_pixel, size); ++ } ++ } ++ ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_set_images ++ * Set & sync input/output images ++ * ++ * Parameters: ++ * handle: device handle ++ * config: configuration ++ * ++ * Return: ++ * None ++ */ ++static void ive_drv_set_images(ive_drv_handle *handle, ive_ioc_config *config) ++{ ++ ive_hal_set_images(&handle->hal_handle, &config->input, &config->output); ++ ++ switch (config->op_type) ++ { ++ case IVE_IOC_OP_TYPE_NCC: ++ ive_drv_sync_image(handle, &config->input, DMA_TO_DEVICE); ++ break; ++ ++ default: ++ ive_drv_sync_image(handle, &config->input, DMA_TO_DEVICE); ++ ive_drv_sync_image(handle, &config->output, DMA_FROM_DEVICE); ++ break; ++ } ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_drv_isr_handler ++ * ISR handler ++ * ++ * Parameters: ++ * irq: interrupt number ++ * handle: device handle ++ * ++ * Return: ++ * None ++ */ ++IVE_DRV_STATE ive_drv_isr_handler(int irq, ive_drv_handle *handle) ++{ ++ IVE_MSG(IVE_MSG_DBG, "Interrupt: 0x%X\n", ive_hal_get_irq(&handle->hal_handle)); ++ ++ // IVE_HAL_IRQ_MASK_FRAME_DONE ++ if(ive_hal_get_irq_check(&handle->hal_handle, IVE_HAL_IRQ_MASK_FRAME_DONE)) { ++ handle->dev_state = IVE_DRV_STATE_DONE; ++ ++ // Clear IRQ ++ ive_hal_clear_irq(&handle->hal_handle, IVE_HAL_IRQ_MASK_FRAME_DONE); ++ ++ return IVE_DRV_STATE_DONE; ++ } ++ ++ return IVE_DRV_STATE_PROCESSING; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_init ++ * Init IVEG settings ++ * ++ * Parameters: ++ * handle: device handle ++ * pdev: platform device ++ * base_addr0: base addr of HW register bank 0 ++ * base_addr1: base addr of HW register bank 1 ++ * ++ * Return: ++ * none ++ */ ++int ive_drv_init(ive_drv_handle *handle, struct platform_device *pdev, phys_addr_t base_addr0, phys_addr_t base_addr1) ++{ ++ IVE_MSG(IVE_MSG_DBG, "name: %s, addr 0x%08X, 0x%08X\n", pdev->name, base_addr0, base_addr1); ++ ++ memset(handle, 0, sizeof(ive_drv_handle)); ++ ++ ive_hal_init(&handle->hal_handle, base_addr0, base_addr1); ++ INIT_LIST_HEAD(&handle->request_list); ++ IVE_MSG(IVE_MSG_DBG, "list_empty = %d\n", list_empty(&handle->request_list)); ++ ++ handle->pdev = pdev; ++ handle->dev_state = IVE_DRV_STATE_READY; ++ ++ // create working buffer ++ // Here we assume kmalloc() has 16 byte alignment ++ handle->work_buffer = devm_kmalloc(&handle->pdev->dev, sizeof(ive_work_buffer), GFP_KERNEL); ++ if (handle->work_buffer == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "can't allocate working buffer\n"); ++ return -ENOMEM; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "work buffer = 0x%p\n", handle->work_buffer); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_release ++ * Release IVEG settings ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * none ++ */ ++void ive_drv_release(ive_drv_handle *handle) ++{ ++ devm_kfree(&handle->pdev->dev, handle->work_buffer); ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_start ++ * Start HW engine ++ * ++ * Parameters: ++ * handle: device handle ++ * config: IVE configurations ++ * ++ * Return: ++ * none ++ */ ++static void ive_drv_start(ive_drv_handle *handle, ive_ioc_config *config) ++{ ++ IVE_MSG(IVE_MSG_DBG, "op_type: 0x%X\n", config->op_type); ++ ++ ive_hal_sw_reset(&handle->hal_handle); ++ ++ ive_hal_set_operation(&handle->hal_handle, config->op_type); ++ ive_drv_set_images(handle, config); ++ ++ switch (config->op_type) { ++ case IVE_IOC_OP_TYPE_FILTER: ++ ive_hal_set_coeff_filter(&handle->hal_handle, &config->coeff_filter); ++ break; ++ ++ case IVE_IOC_OP_TYPE_CSC: ++ ive_hal_set_coeff_csc(&handle->hal_handle, &config->coeff_csc); ++ break; ++ ++ case IVE_IOC_OP_TYPE_FILTER_AND_CSC: ++ ive_hal_set_coeff_filter(&handle->hal_handle, &config->coeff_filter_csc.filter); ++ ive_hal_set_coeff_csc(&handle->hal_handle, &config->coeff_filter_csc.csc); ++ break; ++ ++ case IVE_IOC_OP_TYPE_SOBEL: ++ ive_hal_set_coeff_sobel(&handle->hal_handle, &config->coeff_sobel); ++ break; ++ ++ case IVE_IOC_OP_TYPE_MAG_AND_ANG: ++ ive_hal_set_coeff_mag_and_ang(&handle->hal_handle, &config->coeff_mag_and_ang); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ORD_STA_FILTER: ++ ive_hal_set_coeff_ord_stat_filter(&handle->hal_handle, &config->coeff_ord_stat_filter); ++ break; ++ ++ case IVE_IOC_OP_TYPE_BERNSEN: ++ ive_hal_set_coeff_bernsen(&handle->hal_handle, &config->coeff_bernsen); ++ break; ++ ++ case IVE_IOC_OP_TYPE_DILATE: ++ ive_hal_set_coeff_dilate(&handle->hal_handle, &config->coeff_dilate); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ERODE: ++ ive_hal_set_coeff_erode(&handle->hal_handle, &config->coeff_erode); ++ break; ++ ++ case IVE_IOC_OP_TYPE_THRESH: ++ ive_hal_set_coeff_thresh(&handle->hal_handle, &config->coeff_thresh); ++ break; ++ ++ case IVE_IOC_OP_TYPE_THRESH_S16: ++ ive_hal_set_coeff_thresh_s16(&handle->hal_handle, &config->coeff_thresh_s16); ++ break; ++ ++ case IVE_IOC_OP_TYPE_THRESH_U16: ++ ive_hal_set_coeff_thresh_u16(&handle->hal_handle, &config->coeff_thresh_u16); ++ break; ++ ++ case IVE_IOC_OP_TYPE_ADD: ++ ive_hal_set_coeff_add(&handle->hal_handle, &config->coeff_add); ++ break; ++ ++ case IVE_IOC_OP_TYPE_SUB: ++ ive_hal_set_coeff_sub(&handle->hal_handle, &config->coeff_sub); ++ break; ++ ++ case IVE_IOC_OP_TYPE_16BIT_TO_8BIT: ++ ive_hal_set_coeff_16to8(&handle->hal_handle, &config->coeff_16to8); ++ break; ++ ++ case IVE_IOC_OP_TYPE_MAP: ++ memcpy(handle->work_buffer->map_buffer, config->coeff_map.map, sizeof(config->coeff_map.map)); ++ handle->work_buffer_dma = dma_map_single(NULL, handle->work_buffer, sizeof(ive_work_buffer), DMA_TO_DEVICE); ++ dma_sync_single_for_device(NULL, handle->work_buffer_dma, sizeof(ive_work_buffer), DMA_TO_DEVICE); ++ ive_hal_set_coeff_map(&handle->hal_handle, (void*)handle->work_buffer_dma); ++ break; ++ ++ case IVE_IOC_OP_TYPE_INTEGRAL: ++ ive_hal_set_coeff_integral(&handle->hal_handle, &config->coeff_integral); ++ break; ++ ++ case IVE_IOC_OP_TYPE_SAD: ++ ive_hal_set_coeff_sad(&handle->hal_handle, &config->coeff_sad); ++ break; ++ ++ case IVE_IOC_OP_TYPE_NCC: ++ handle->work_buffer_dma = dma_map_single(NULL, handle->work_buffer, sizeof(ive_work_buffer), DMA_FROM_DEVICE); ++ dma_sync_single_for_device(NULL, handle->work_buffer_dma, sizeof(ive_work_buffer), DMA_FROM_DEVICE); ++ ive_hal_set_coeff_ncc(&handle->hal_handle, (void*)handle->work_buffer_dma); ++ break; ++ ++ case IVE_IOC_OP_TYPE_LBP: ++ ive_hal_set_coeff_lbp(&handle->hal_handle, &config->coeff_lbp); ++ break; ++ ++ default: ++ break; ++ } ++ ++ ive_hal_clear_irq(&handle->hal_handle, IVE_HAL_IRQ_MASK_ALL); ++ ive_hal_set_irq_mask(&handle->hal_handle, IVE_HAL_IRQ_MASK_FRAME_DONE); ++ ++ ive_hal_start(&handle->hal_handle); ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_start_proc ++ * Start IVE process image ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * IVE_IOC_ERROR ++ */ ++IVE_IOC_ERROR ive_drv_process(ive_drv_handle *handle, ive_file_data *file_data) ++{ ++ IVE_IOC_ERROR ret = IVE_IOC_ERROR_NONE; ++#if 0 // multi instance test ++ static int pause_count = 0; ++#endif ++ ++ ret = drv_ive_check_config(&file_data->ioc_config); ++ if (ret != IVE_IOC_ERROR_NONE) { ++ return ret; ++ } ++ ++ file_data->state = IVE_FILE_STATE_IN_QUEUE; ++ if (drv_ive_add_request(handle, file_data) == NULL) { ++ return IVE_IOC_ERROR_MEMROY_FAILURE; ++ } ++ ++ ++ // do nothing if hw is not ready ++ if ((handle->dev_state != IVE_DRV_STATE_READY) ++#if 0 // multi instance test ++ || (pause_count++ < 10) ++#endif ++ ) ++ { ++ IVE_MSG(IVE_MSG_DBG, "HW is busy\n"); ++ return IVE_IOC_ERROR_NONE; ++ } ++ ++ file_data = drv_ive_get_request(handle); ++ if (file_data == NULL) { ++ IVE_MSG(IVE_MSG_DBG, "no more request in queue\n"); ++ return IVE_IOC_ERROR_MEMROY_FAILURE; ++ } ++ ++ file_data->state = IVE_FILE_STATE_PROCESSING; ++ handle->dev_state = IVE_DRV_STATE_PROCESSING; ++ ++ IVE_MSG(IVE_MSG_DBG, "process: %p\n", file_data->ioc_config.input.address[0]); ++ ++ ive_drv_start(handle, &file_data->ioc_config); ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_post_process ++ * Post process after IVE HW done ++ * ++ * Parameters: ++ * handle: device handle ++ * ++ * Return: ++ * IVE_IOC_ERROR ++ */ ++ive_file_data* ive_drv_post_process(ive_drv_handle *handle) ++{ ++ ive_file_data *previous_file_data, *next_file_data; ++ ++ previous_file_data = drv_ive_extract_request(handle); ++ next_file_data = drv_ive_get_request(handle); ++ ++ switch(handle->hal_handle.reg_bank1.op_type) ++ { ++ case IVE_IOC_OP_TYPE_MAP: ++ dma_unmap_single(NULL, handle->work_buffer_dma, sizeof(ive_work_buffer), DMA_TO_DEVICE); ++ break; ++ ++ case IVE_IOC_OP_TYPE_NCC: ++ dma_unmap_single(NULL, handle->work_buffer_dma, sizeof(ive_work_buffer), DMA_FROM_DEVICE); ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (previous_file_data != NULL) { ++ ive_drv_copy_work_buffer(handle, &(previous_file_data->work_buffer)); ++ previous_file_data->state = IVE_FILE_STATE_DONE; ++ } ++ ++ if (next_file_data == NULL) { ++ IVE_MSG(IVE_MSG_DBG, "no more request in queue\n"); ++ handle->dev_state = IVE_DRV_STATE_READY; ++ } else { ++ IVE_MSG(IVE_MSG_DBG, "process: 0x%p, 0x%p, 0x%p\n", next_file_data->ioc_config.input.address[0], next_file_data->ioc_config.input.address[1], next_file_data->ioc_config.output.address[0]); ++ next_file_data->state = IVE_FILE_STATE_PROCESSING; ++ ive_drv_start(handle, &next_file_data->ioc_config); ++ } ++ ++ return previous_file_data; ++} ++ ++/******************************************************************************************************************* ++ * ive_drv_copy_work_buffer ++ * Copy work buffer from drv to file data ++ * ++ * Parameters: ++ * handle: device handle ++ * work_buffer: destination ++ * ++ * Return: ++ * none ++ */ ++void ive_drv_copy_work_buffer(ive_drv_handle *handle, ive_work_buffer *work_buffer) ++{ ++ memcpy(work_buffer, handle->work_buffer, sizeof(ive_work_buffer)); ++} +diff --git a/drivers/mstar/ive/drv_ive.h b/drivers/mstar/ive/drv_ive.h +new file mode 100644 +index 00000000..5de8286c +--- /dev/null ++++ b/drivers/mstar/ive/drv_ive.h +@@ -0,0 +1,16 @@ ++#ifndef _IVE_DRV_H_ ++#define _IVE_DRV_H_ ++ ++#include ++#include "mdrv_ive_data.h" ++#include "hal_ive.h" ++#include "mdrv_ive_io_st.h" ++ ++IVE_DRV_STATE ive_drv_isr_handler(int irq, ive_drv_handle *handle); ++ ++int ive_drv_init(ive_drv_handle *handle, struct platform_device *pdev, phys_addr_t base_addr0, phys_addr_t base_addr1); ++void ive_drv_release(ive_drv_handle *handle); ++IVE_IOC_ERROR ive_drv_process(ive_drv_handle *handle, ive_file_data *file_data); ++ive_file_data* ive_drv_post_process(ive_drv_handle *handle); ++void ive_drv_copy_work_buffer(ive_drv_handle *handle, ive_work_buffer *work_buffer); ++#endif +diff --git a/drivers/mstar/ive/hal_ive.c b/drivers/mstar/ive/hal_ive.c +new file mode 100644 +index 00000000..cb5f169f +--- /dev/null ++++ b/drivers/mstar/ive/hal_ive.c +@@ -0,0 +1,832 @@ ++#include "mdrv_ive.h" ++#include "hal_ive.h" ++#include "hal_ive_simulate.h" ++#include "ms_platform.h" ++ ++#define ADDR_LOW(addr) (((u32)(addr))&0x0000FFFF) ++#define ADDR_HIGH(addr) ((((u32)(addr))&0xFFFF0000)>>16) ++ ++#if 1 ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) ms_writew(val,((uint)base+(idx)*4)) ++#else ++#define REGR(base,idx) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val) do{IVE_MSG(IVE_MSG_DBG, "write 0x%08X = 0x%04X\n", ((uint)base+(idx)*4), val); ms_writew(val,((uint)base+(idx)*4));} while(0) ++#endif ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// IRQ API // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * ive_hal_init ++ * init IVE HAL layer ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * base_addr0: base address 0 ++ * base_addr1: base address 1 ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_init(ive_hal_handle *handle, phys_addr_t base_addr0, phys_addr_t base_addr1) ++{ ++ memset(handle, 0, sizeof(ive_hal_handle)); ++ handle->base_addr0 = base_addr0; ++ handle->base_addr1 = base_addr1; ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_irq_mask ++ * Set interrupt trigger mask ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwize mask, defined in IveHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_irq_mask(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask) ++{ ++ handle->reg_bank0.irq_mask = ~mask; ++ REGW(handle->base_addr0, 0x10, handle->reg_bank0.reg10); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_clear_irq ++ * Clear triggered interrupt ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwize mask, defined in IveHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_clear_irq(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask) ++{ ++ handle->reg_bank0.woc_irq_clr = mask; ++ REGW(handle->base_addr0, 0x15, handle->reg_bank0.reg15); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_get_irq_check ++ * Check current IRQ status ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwise mask to be checked ++ * ++ * Return: ++ * Checked result, bitwise ++ */ ++IVE_HAL_IRQ_MASK ive_hal_get_irq_check(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask) ++{ ++#if !defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = REGR(handle->base_addr0, 0x13); ++#else // defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = IVE_HAL_IRQ_MASK_FRAME_DONE; ++#endif // defined(IVE_SW_SIMULATE) ++ ++ return handle->reg_bank0.irq_final_status & mask; ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_get_irq ++ * Get current interrupt trigger status ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: Bitwize mask, defined in IveHalIrqEvent_e ++ * ++ * Return: ++ * Bitwize status ++ */ ++u16 ive_hal_get_irq(ive_hal_handle *handle) ++{ ++#if !defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = REGR(handle->base_addr0, 0x13); ++#else // defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.irq_final_status = IVE_HAL_IRQ_MASK_FRAME_DONE; ++#endif // defined(IVE_SW_SIMULATE) ++ ++ return handle->reg_bank0.irq_final_status; ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_operation ++ * Set operation of IVE HW ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * op_type: operation type ++ * op_mode: operation mode ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_operation(ive_hal_handle *handle, IVE_IOC_OP_TYPE op_type) ++{ ++ handle->reg_bank1.op_type = op_type; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_images ++ * Set input & output image ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * input: input image ++ * output: output image ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_images(ive_hal_handle *handle, ive_ioc_image *input, ive_ioc_image *output) ++{ ++ u64 input_addr0 = Chip_Phys_to_MIU((uintptr_t)input->address[0]); ++ u64 input_addr1 = Chip_Phys_to_MIU((uintptr_t)input->address[1]); ++ u64 input_addr2 = Chip_Phys_to_MIU((uintptr_t)input->address[2]); ++ u64 output_addr0 = Chip_Phys_to_MIU((uintptr_t)output->address[0]); ++ u64 output_addr1 = Chip_Phys_to_MIU((uintptr_t)output->address[1]); ++ u64 output_addr2 = Chip_Phys_to_MIU((uintptr_t)output->address[2]); ++ ++ handle->reg_bank1.infmt = input->format; ++ handle->reg_bank1.outfmt = output->format; ++ ++ handle->reg_bank1.frame_width = input->width -1; ++ handle->reg_bank1.frame_height = input->height -1; ++ ++ handle->reg_bank1.src1_addr_low = ADDR_LOW( input_addr0); ++ handle->reg_bank1.src1_addr_high = ADDR_HIGH(input_addr0); ++ handle->reg_bank1.src2_addr_low = ADDR_LOW( input_addr1); ++ handle->reg_bank1.src2_addr_high = ADDR_HIGH(input_addr1); ++ handle->reg_bank1.src3_addr_low = ADDR_LOW( input_addr2); ++ handle->reg_bank1.src3_addr_high = ADDR_HIGH(input_addr2); ++ handle->reg_bank1.src1_stride = input->stride[0] -1; ++ handle->reg_bank1.src2_stride = input->stride[1] -1; ++ handle->reg_bank1.src3_stride = input->stride[2] -1; ++ ++ handle->reg_bank1.dst1_addr_low = ADDR_LOW( output_addr0); ++ handle->reg_bank1.dst1_addr_high = ADDR_HIGH(output_addr0); ++ handle->reg_bank1.dst2_addr_low = ADDR_LOW( output_addr1); ++ handle->reg_bank1.dst2_addr_high = ADDR_HIGH(output_addr1); ++ handle->reg_bank1.dst3_addr_low = ADDR_LOW( output_addr2); ++ handle->reg_bank1.dst3_addr_high = ADDR_HIGH(output_addr2); ++ handle->reg_bank1.dst1_stride = output->stride[0] -1; ++ handle->reg_bank1.dst2_stride = output->stride[1] -1; ++ handle->reg_bank1.dst3_stride = output->stride[2] -1; ++ ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x06, handle->reg_bank1.reg06); ++ REGW(handle->base_addr1, 0x07, handle->reg_bank1.reg07); ++ REGW(handle->base_addr1, 0x08, handle->reg_bank1.reg08); ++ REGW(handle->base_addr1, 0x09, handle->reg_bank1.reg09); ++ REGW(handle->base_addr1, 0x0A, handle->reg_bank1.reg0A); ++ REGW(handle->base_addr1, 0x0B, handle->reg_bank1.reg0B); ++ REGW(handle->base_addr1, 0x0C, handle->reg_bank1.reg0C); ++ REGW(handle->base_addr1, 0x0D, handle->reg_bank1.reg0D); ++ REGW(handle->base_addr1, 0x0E, handle->reg_bank1.reg0E); ++ REGW(handle->base_addr1, 0x0F, handle->reg_bank1.reg0F); ++ REGW(handle->base_addr1, 0x10, handle->reg_bank1.reg10); ++ REGW(handle->base_addr1, 0x11, handle->reg_bank1.reg11); ++ REGW(handle->base_addr1, 0x12, handle->reg_bank1.reg12); ++ REGW(handle->base_addr1, 0x13, handle->reg_bank1.reg13); ++ REGW(handle->base_addr1, 0x14, handle->reg_bank1.reg14); ++ REGW(handle->base_addr1, 0x15, handle->reg_bank1.reg15); ++ REGW(handle->base_addr1, 0x16, handle->reg_bank1.reg16); ++ REGW(handle->base_addr1, 0x17, handle->reg_bank1.reg17); ++ REGW(handle->base_addr1, 0x18, handle->reg_bank1.reg18); ++ REGW(handle->base_addr1, 0x19, handle->reg_bank1.reg19); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_mask ++ * Set mask coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * mask: mask coefficient ++ * ++ * Return: ++ * none ++ */ ++static void ive_hal_set_coeff_mask(ive_hal_handle *handle, u8 *mask, u8 shift) ++{ ++ handle->reg_bank1.mask0 = mask[0]; ++ handle->reg_bank1.mask1 = mask[1]; ++ handle->reg_bank1.mask2 = mask[2]; ++ handle->reg_bank1.mask3 = mask[3]; ++ handle->reg_bank1.mask4 = mask[4]; ++ handle->reg_bank1.mask5 = mask[5]; ++ handle->reg_bank1.mask6 = mask[6]; ++ handle->reg_bank1.mask7 = mask[7]; ++ handle->reg_bank1.mask8 = mask[8]; ++ handle->reg_bank1.mask9 = mask[9]; ++ handle->reg_bank1.mask10 = mask[10]; ++ handle->reg_bank1.mask11 = mask[11]; ++ handle->reg_bank1.mask12 = mask[12]; ++ handle->reg_bank1.mask13 = mask[13]; ++ handle->reg_bank1.mask14 = mask[14]; ++ handle->reg_bank1.mask15 = mask[15]; ++ handle->reg_bank1.mask16 = mask[16]; ++ handle->reg_bank1.mask17 = mask[17]; ++ handle->reg_bank1.mask18 = mask[18]; ++ handle->reg_bank1.mask19 = mask[19]; ++ handle->reg_bank1.mask20 = mask[20]; ++ handle->reg_bank1.mask21 = mask[21]; ++ handle->reg_bank1.mask22 = mask[22]; ++ handle->reg_bank1.mask23 = mask[23]; ++ handle->reg_bank1.mask24 = mask[24]; ++ handle->reg_bank1.shift = shift; ++ ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x1C, handle->reg_bank1.reg1C); ++ REGW(handle->base_addr1, 0x1D, handle->reg_bank1.reg1D); ++ REGW(handle->base_addr1, 0x1E, handle->reg_bank1.reg1E); ++ REGW(handle->base_addr1, 0x1F, handle->reg_bank1.reg1F); ++ REGW(handle->base_addr1, 0x20, handle->reg_bank1.reg20); ++ REGW(handle->base_addr1, 0x21, handle->reg_bank1.reg21); ++ REGW(handle->base_addr1, 0x22, handle->reg_bank1.reg22); ++ REGW(handle->base_addr1, 0x23, handle->reg_bank1.reg23); ++ REGW(handle->base_addr1, 0x24, handle->reg_bank1.reg24); ++ REGW(handle->base_addr1, 0x25, handle->reg_bank1.reg25); ++ REGW(handle->base_addr1, 0x26, handle->reg_bank1.reg26); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_filter ++ * Set filter coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_filter(ive_hal_handle *handle, ive_ioc_coeff_filter *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, coeff->shift); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_csc ++ * Set CSC coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: CSC coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_csc(ive_hal_handle *handle, ive_ioc_coeff_csc *coeff) ++{ ++ handle->reg_bank1.csc_coeff0 = coeff->coeff[0]; ++ handle->reg_bank1.csc_coeff1 = coeff->coeff[1]; ++ handle->reg_bank1.csc_coeff2 = coeff->coeff[2]; ++ handle->reg_bank1.csc_coeff3 = coeff->coeff[3]; ++ handle->reg_bank1.csc_coeff4 = coeff->coeff[4]; ++ handle->reg_bank1.csc_coeff5 = coeff->coeff[5]; ++ handle->reg_bank1.csc_coeff6 = coeff->coeff[6]; ++ handle->reg_bank1.csc_coeff7 = coeff->coeff[7]; ++ handle->reg_bank1.csc_coeff8 = coeff->coeff[8]; ++ ++ handle->reg_bank1.csc_offset0 = coeff->offset[0]; ++ handle->reg_bank1.csc_offset1 = coeff->offset[1]; ++ handle->reg_bank1.csc_offset2 = coeff->offset[2]; ++ ++ handle->reg_bank1.csc_clamp0_low = coeff->clamp[0].clamp_low; ++ handle->reg_bank1.csc_clamp0_high = coeff->clamp[0].clamp_high; ++ handle->reg_bank1.csc_clamp1_low = coeff->clamp[1].clamp_low; ++ handle->reg_bank1.csc_clamp1_high = coeff->clamp[1].clamp_high; ++ handle->reg_bank1.csc_clamp2_low = coeff->clamp[2].clamp_low; ++ handle->reg_bank1.csc_clamp2_high = coeff->clamp[2].clamp_high; ++ ++ REGW(handle->base_addr1, 0x30, handle->reg_bank1.reg30); ++ REGW(handle->base_addr1, 0x31, handle->reg_bank1.reg31); ++ REGW(handle->base_addr1, 0x32, handle->reg_bank1.reg32); ++ REGW(handle->base_addr1, 0x33, handle->reg_bank1.reg33); ++ REGW(handle->base_addr1, 0x34, handle->reg_bank1.reg34); ++ REGW(handle->base_addr1, 0x35, handle->reg_bank1.reg35); ++ REGW(handle->base_addr1, 0x36, handle->reg_bank1.reg36); ++ REGW(handle->base_addr1, 0x37, handle->reg_bank1.reg37); ++ REGW(handle->base_addr1, 0x38, handle->reg_bank1.reg38); ++ REGW(handle->base_addr1, 0x39, handle->reg_bank1.reg39); ++ REGW(handle->base_addr1, 0x3A, handle->reg_bank1.reg3A); ++ REGW(handle->base_addr1, 0x3B, handle->reg_bank1.reg3B); ++ REGW(handle->base_addr1, 0x3C, handle->reg_bank1.reg3C); ++ REGW(handle->base_addr1, 0x3D, handle->reg_bank1.reg3D); ++ REGW(handle->base_addr1, 0x3E, handle->reg_bank1.reg3E); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_sobel ++ * Set sobel coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_sobel(ive_hal_handle *handle, ive_ioc_coeff_sobel *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++ ++ handle->reg_bank1.outfmt = coeff->mode; ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_mag_and_ang ++ * Set mag and ang coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_mag_and_ang(ive_hal_handle *handle, ive_ioc_coeff_mag_and_ang *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++ ++ handle->reg_bank1.outfmt = coeff->mode; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh; ++ ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_ord_stat_filter ++ * Set order statistics filter coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_ord_stat_filter(ive_hal_handle *handle, ive_ioc_coeff_ord_stat_filter *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_bernsen ++ * Set bernsen coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_bernsen(ive_hal_handle *handle, ive_ioc_coeff_bernsen *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_dilate ++ * Set dilate coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_dilate(ive_hal_handle *handle, ive_ioc_coeff_dilate *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_erode ++ * Set erode coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_erode(ive_hal_handle *handle, ive_ioc_coeff_erode *coeff) ++{ ++ ive_hal_set_coeff_mask(handle, coeff->mask, 0); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_thresh ++ * Set thresh coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_thresh(ive_hal_handle *handle, ive_ioc_coeff_thresh *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->mid; ++ handle->reg_bank1.mask2 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->low; ++ handle->reg_bank1.thresh_16bit_2 = coeff->high; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_thresh_s16 ++ * Set thresh s16 coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_thresh_s16(ive_hal_handle *handle, ive_ioc_coeff_thresh_s16 *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->mid; ++ handle->reg_bank1.mask2 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->low; ++ handle->reg_bank1.thresh_16bit_2 = coeff->high; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_thresh_u16 ++ * Set thresh u16 coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_thresh_u16(ive_hal_handle *handle, ive_ioc_coeff_thresh_u16 *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->mid; ++ handle->reg_bank1.mask2 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->low; ++ handle->reg_bank1.thresh_16bit_2 = coeff->high; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x1B, handle->reg_bank1.reg1B); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++ REGW(handle->base_addr1, 0x29, handle->reg_bank1.reg29); ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_add ++ * Set add coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_add(ive_hal_handle *handle, ive_ioc_coeff_add *coeff) ++{ ++ handle->reg_bank1.add_weight_x = coeff->weight_x; ++ handle->reg_bank1.add_weight_y = coeff->weight_y; ++ ++ REGW(handle->base_addr1, 0x2B, handle->reg_bank1.reg2B); ++ REGW(handle->base_addr1, 0x2C, handle->reg_bank1.reg2C); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_sub ++ * Set sub coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_sub(ive_hal_handle *handle, ive_ioc_coeff_sub *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_16to8 ++ * Set 16 to 8 coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_16to8(ive_hal_handle *handle, ive_ioc_coeff_16to8 *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.fraction = (u16)(((u32)coeff->numerator << 16) / (u32)coeff->denominator); ++ handle->reg_bank1.mask0 = coeff->bias; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x2A, handle->reg_bank1.reg2A); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_map ++ * Set map coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_map(ive_hal_handle *handle, void *map_addr) ++{ ++ u64 miu_addr = Chip_Phys_to_MIU((uintptr_t)map_addr); ++ ++ handle->reg_bank1.src1_addr_low = ADDR_LOW( miu_addr); ++ handle->reg_bank1.src1_addr_high = ADDR_HIGH(miu_addr); ++ ++ REGW(handle->base_addr1, 0x08, handle->reg_bank1.reg08); ++ REGW(handle->base_addr1, 0x09, handle->reg_bank1.reg09); ++} ++ ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_integral ++ * Set integral coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_integral(ive_hal_handle *handle, ive_ioc_coeff_integral *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_sad ++ * Set SAD coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_sad(ive_hal_handle *handle, ive_ioc_coeff_sad *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->block_mode; ++ handle->reg_bank1.outfmt = coeff->out_mode; ++ handle->reg_bank1.mask0 = coeff->min; ++ handle->reg_bank1.mask1 = coeff->max; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x05, handle->reg_bank1.reg05); ++ REGW(handle->base_addr1, 0x1A, handle->reg_bank1.reg1A); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_lbp ++ * Set LBP coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_ncc(ive_hal_handle *handle, void *output_addr) ++{ ++ u64 miu_addr = Chip_Phys_to_MIU((uintptr_t)output_addr); ++ ++ handle->reg_bank1.dst1_addr_low = ADDR_LOW( miu_addr); ++ handle->reg_bank1.dst1_addr_high = ADDR_HIGH(miu_addr); ++ // handle->reg_bank1.dst1_stride = handle->reg_bank1.src1_stride; ++ ++ REGW(handle->base_addr1, 0x0A, handle->reg_bank1.reg0A); ++ REGW(handle->base_addr1, 0x0B, handle->reg_bank1.reg0B); ++ // REGW(handle->base_addr1, 0x15, handle->reg_bank1.reg15); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_set_coeff_lbp ++ * Set LBP coefficient ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * coeff: coefficient ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_set_coeff_lbp(ive_hal_handle *handle, ive_ioc_coeff_lbp *coeff) ++{ ++ handle->reg_bank1.op_mode = coeff->mode; ++ handle->reg_bank1.thresh_16bit_1 = coeff->thresh-1; ++ ++ REGW(handle->base_addr1, 0x04, handle->reg_bank1.reg04); ++ REGW(handle->base_addr1, 0x28, handle->reg_bank1.reg28); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_start ++ * start IVE HW engine to process images ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * ++ * Return: ++ * none ++ */ ++ void ive_hal_start(ive_hal_handle *handle) ++{ ++#if !defined(IVE_SW_SIMULATE) ++ handle->reg_bank0.sw_fire = 1; ++ ++ REGW(handle->base_addr0, 0x00, handle->reg_bank0.reg00); ++ ++ handle->reg_bank0.sw_fire = 0; // write one clear ++#else // !defined(IVE_SW_SIMULATE) ++ ive_hal_run_simulate(handle); ++#endif // defined(IVE_SW_SIMULATE) ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_sw_reset ++ * reset IVE HW engine ++ * ++ * Parameters: ++ * handle: IVE HAL handle ++ * ++ * Return: ++ * none ++ */ ++void ive_hal_sw_reset(ive_hal_handle *handle) ++{ ++ handle->reg_bank0.sw_rst = 1; ++ ++ REGW(handle->base_addr0, 0x02, handle->reg_bank0.reg02); ++ ++ handle->reg_bank0.sw_rst = 0; // write one clear ++ ++ memset(&handle->reg_bank0, 0, sizeof(handle->reg_bank0)); ++ memset(&handle->reg_bank1, 0, sizeof(handle->reg_bank1)); ++} ++ ++void ive_hal_reg_dump(ive_hal_handle *handle) ++{ ++ IVE_MSG(IVE_MSG_DBG, "clock reg = 0x%04x\n", REGR(0x1F207000, 0x6A)); ++ ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x00, REGR(handle->base_addr0, 0x00)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x01, REGR(handle->base_addr0, 0x01)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x02, REGR(handle->base_addr0, 0x02)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x10, REGR(handle->base_addr0, 0x10)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x11, REGR(handle->base_addr0, 0x11)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x12, REGR(handle->base_addr0, 0x12)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x13, REGR(handle->base_addr0, 0x13)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x14, REGR(handle->base_addr0, 0x14)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x15, REGR(handle->base_addr0, 0x15)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x16, REGR(handle->base_addr0, 0x16)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x17, REGR(handle->base_addr0, 0x17)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x18, REGR(handle->base_addr0, 0x18)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x20, REGR(handle->base_addr0, 0x20)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x21, REGR(handle->base_addr0, 0x21)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x22, REGR(handle->base_addr0, 0x22)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x23, REGR(handle->base_addr0, 0x23)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x24, REGR(handle->base_addr0, 0x24)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x25, REGR(handle->base_addr0, 0x25)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x30, REGR(handle->base_addr0, 0x30)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x31, REGR(handle->base_addr0, 0x31)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x40, REGR(handle->base_addr0, 0x40)); ++ IVE_MSG(IVE_MSG_DBG, "bank 0 reg 0x%02X = 0x%04x\n", 0x41, REGR(handle->base_addr0, 0x41)); ++ ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x00, REGR(handle->base_addr1, 0x00)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x01, REGR(handle->base_addr1, 0x01)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x02, REGR(handle->base_addr1, 0x02)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x03, REGR(handle->base_addr1, 0x03)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x04, REGR(handle->base_addr1, 0x04)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x05, REGR(handle->base_addr1, 0x05)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x06, REGR(handle->base_addr1, 0x06)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x07, REGR(handle->base_addr1, 0x07)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x08, REGR(handle->base_addr1, 0x08)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x09, REGR(handle->base_addr1, 0x09)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0A, REGR(handle->base_addr1, 0x0A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0B, REGR(handle->base_addr1, 0x0B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0C, REGR(handle->base_addr1, 0x0C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0D, REGR(handle->base_addr1, 0x0D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0E, REGR(handle->base_addr1, 0x0E)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x0F, REGR(handle->base_addr1, 0x0F)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x10, REGR(handle->base_addr1, 0x10)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x11, REGR(handle->base_addr1, 0x11)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x12, REGR(handle->base_addr1, 0x12)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x13, REGR(handle->base_addr1, 0x13)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x14, REGR(handle->base_addr1, 0x14)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x15, REGR(handle->base_addr1, 0x15)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x16, REGR(handle->base_addr1, 0x16)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x17, REGR(handle->base_addr1, 0x17)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x18, REGR(handle->base_addr1, 0x18)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x19, REGR(handle->base_addr1, 0x19)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1A, REGR(handle->base_addr1, 0x1A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1B, REGR(handle->base_addr1, 0x1B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1C, REGR(handle->base_addr1, 0x1C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1D, REGR(handle->base_addr1, 0x1D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1E, REGR(handle->base_addr1, 0x1E)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x1F, REGR(handle->base_addr1, 0x1F)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x20, REGR(handle->base_addr1, 0x20)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x21, REGR(handle->base_addr1, 0x21)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x22, REGR(handle->base_addr1, 0x22)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x23, REGR(handle->base_addr1, 0x23)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x24, REGR(handle->base_addr1, 0x24)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x25, REGR(handle->base_addr1, 0x25)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x26, REGR(handle->base_addr1, 0x26)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x27, REGR(handle->base_addr1, 0x27)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x28, REGR(handle->base_addr1, 0x28)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x29, REGR(handle->base_addr1, 0x29)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2A, REGR(handle->base_addr1, 0x2A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2B, REGR(handle->base_addr1, 0x2B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2C, REGR(handle->base_addr1, 0x2C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2D, REGR(handle->base_addr1, 0x2D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2E, REGR(handle->base_addr1, 0x2E)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x2F, REGR(handle->base_addr1, 0x2F)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x30, REGR(handle->base_addr1, 0x30)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x31, REGR(handle->base_addr1, 0x31)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x32, REGR(handle->base_addr1, 0x32)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x33, REGR(handle->base_addr1, 0x33)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x34, REGR(handle->base_addr1, 0x34)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x35, REGR(handle->base_addr1, 0x35)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x36, REGR(handle->base_addr1, 0x36)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x37, REGR(handle->base_addr1, 0x37)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x38, REGR(handle->base_addr1, 0x38)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x39, REGR(handle->base_addr1, 0x39)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3A, REGR(handle->base_addr1, 0x3A)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3B, REGR(handle->base_addr1, 0x3B)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3C, REGR(handle->base_addr1, 0x3C)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3D, REGR(handle->base_addr1, 0x3D)); ++ IVE_MSG(IVE_MSG_DBG, "bank 1 reg 0x%02X = 0x%04x\n", 0x3E, REGR(handle->base_addr1, 0x3E)); ++} +diff --git a/drivers/mstar/ive/hal_ive.h b/drivers/mstar/ive/hal_ive.h +new file mode 100644 +index 00000000..83c91bee +--- /dev/null ++++ b/drivers/mstar/ive/hal_ive.h +@@ -0,0 +1,61 @@ ++#ifndef _HAL_IVE_H_ ++#define _HAL_IVE_H_ ++ ++#include ++#include "hal_ive_reg.h" ++#include "mdrv_ive_io_st.h" ++ ++typedef enum ++{ ++ IVE_HAL_IRQ_MASK_FRAME_DONE = 0x00000001, // bit 0, frame done ++ IVE_HAL_IRQ_MASK_Y_CNT_HIT_0 = 0x00000002, // bit 1, Y line counter 0 hit ++ IVE_HAL_IRQ_MASK_Y_CNT_HIT_1 = 0x00000004, // bit 2, Y line counter 1 hit ++ IVE_HAL_IRQ_MASK_Y_CNT_HIT_2 = 0x00000008, // bit 3, Y line counter 2 hit ++ IVE_HAL_IRQ_MASK_ALL = 0xF000000F // ALL bits ++} IVE_HAL_IRQ_MASK; ++ ++typedef struct ++{ ++ phys_addr_t base_addr0; ++ ive_hal_reg_bank0 reg_bank0; ++ ++ phys_addr_t base_addr1; ++ ive_hal_reg_bank1 reg_bank1; ++} ive_hal_handle; ++ ++void ive_hal_init(ive_hal_handle *handle, phys_addr_t base_addr0, phys_addr_t base_addr1); ++ ++void ive_hal_set_irq_mask(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask); ++void ive_hal_clear_irq(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask); ++IVE_HAL_IRQ_MASK ive_hal_get_irq_check(ive_hal_handle *handle, IVE_HAL_IRQ_MASK mask); ++u16 ive_hal_get_irq(ive_hal_handle *handle); ++ ++void ive_hal_set_operation(ive_hal_handle *handle, IVE_IOC_OP_TYPE op_type); ++void ive_hal_set_images(ive_hal_handle *handle, ive_ioc_image *input, ive_ioc_image *output); ++ ++void ive_hal_set_coeff_filter(ive_hal_handle *handle, ive_ioc_coeff_filter *coeff); ++void ive_hal_set_coeff_csc(ive_hal_handle *handle, ive_ioc_coeff_csc *coeff); ++void ive_hal_set_coeff_sobel(ive_hal_handle *handle, ive_ioc_coeff_sobel *coeff); ++void ive_hal_set_coeff_mag_and_ang(ive_hal_handle *handle, ive_ioc_coeff_mag_and_ang *coeff); ++void ive_hal_set_coeff_ord_stat_filter(ive_hal_handle *handle, ive_ioc_coeff_ord_stat_filter *coeff); ++void ive_hal_set_coeff_bernsen(ive_hal_handle *handle, ive_ioc_coeff_bernsen *coeff); ++void ive_hal_set_coeff_dilate(ive_hal_handle *handle, ive_ioc_coeff_dilate *coeff); ++void ive_hal_set_coeff_erode(ive_hal_handle *handle, ive_ioc_coeff_erode *coeff); ++void ive_hal_set_coeff_thresh(ive_hal_handle *handle, ive_ioc_coeff_thresh *coeff); ++void ive_hal_set_coeff_thresh_s16(ive_hal_handle *handle, ive_ioc_coeff_thresh_s16 *coeff); ++void ive_hal_set_coeff_thresh_u16(ive_hal_handle *handle, ive_ioc_coeff_thresh_u16 *coeff); ++void ive_hal_set_coeff_add(ive_hal_handle *handle, ive_ioc_coeff_add *coeff); ++void ive_hal_set_coeff_sub(ive_hal_handle *handle, ive_ioc_coeff_sub *coeff); ++void ive_hal_set_coeff_16to8(ive_hal_handle *handle, ive_ioc_coeff_16to8 *coeff); ++void ive_hal_set_coeff_map(ive_hal_handle *handle, void *map_addr); ++void ive_hal_set_coeff_integral(ive_hal_handle *handle, ive_ioc_coeff_integral *coeff); ++void ive_hal_set_coeff_sad(ive_hal_handle *handle, ive_ioc_coeff_sad *coeff); ++void ive_hal_set_coeff_ncc(ive_hal_handle *handle, void *output_addr); ++void ive_hal_set_coeff_lbp(ive_hal_handle *handle, ive_ioc_coeff_lbp *coeff); ++ ++void ive_hal_start(ive_hal_handle *handle); ++void ive_hal_sw_reset(ive_hal_handle *handle); ++ ++void ive_hal_reg_dump(ive_hal_handle *handle); ++ ++#endif // _HAL_IVE_H_ +diff --git a/drivers/mstar/ive/hal_ive_reg.h b/drivers/mstar/ive/hal_ive_reg.h +new file mode 100644 +index 00000000..0cbc02a6 +--- /dev/null ++++ b/drivers/mstar/ive/hal_ive_reg.h +@@ -0,0 +1,761 @@ ++#ifndef _HAL_IVE_REG_H_ ++#define _HAL_IVE_REG_H_ ++ ++#include ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 sw_fire:1; ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 opr_upd_mode:1; ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 sw_rst:1; ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_mask:8; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_force:8; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_raw_status:8; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_final_status:8; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 irq_sel:8; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 woc_irq_clr:8; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 y_cnt_hit_set0:11; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 y_cnt_hit_set1:11; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 y_cnt_hit_set2:11; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_mask:8; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_force:8; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_raw_status:8; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_final_status:8; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cmq_trig_sel:1; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 woc_cmq_trig_clr:8; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 bist_fail_rd_low:16; ++ }; ++ u16 reg30; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 bist_fail_rd_high:16; ++ }; ++ u16 reg31; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cycle_count_low:16; ++ }; ++ u16 reg40; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 cycle_count_high:16; ++ }; ++ u16 reg41; ++ }; ++} ive_hal_reg_bank0; ++ ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 nxt_cmd_addr_low:16; // not used ++ }; ++ u16 reg00; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 nxt_cmd_addr_high:16; // not used ++ }; ++ u16 reg01; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 task_id:16; // not used ++ }; ++ u16 reg02; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 bpp:8; // not used ++ }; ++ u16 reg03; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 op_type:8; ++ u16 op_mode:8; ++ }; ++ u16 reg04; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 infmt:8; ++ u16 outfmt:8; ++ }; ++ u16 reg05; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 frame_width:16; ++ }; ++ u16 reg06; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 frame_height:16; ++ }; ++ u16 reg07; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src1_addr_low:16; ++ }; ++ u16 reg08; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src1_addr_high:16; ++ }; ++ u16 reg09; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst1_addr_low:16; ++ }; ++ u16 reg0A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst1_addr_high:16; ++ }; ++ u16 reg0B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src2_addr_low:16; ++ }; ++ u16 reg0C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src2_addr_high:16; ++ }; ++ u16 reg0D; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst2_addr_low:16; ++ }; ++ u16 reg0E; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst2_addr_high:16; ++ }; ++ u16 reg0F; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src3_addr_low:16; ++ }; ++ u16 reg10; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src3_addr_high:16; ++ }; ++ u16 reg11; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst3_addr_low:16; ++ }; ++ u16 reg12; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst3_addr_high:16; ++ }; ++ u16 reg13; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src1_stride:16; ++ }; ++ u16 reg14; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst1_stride:16; ++ }; ++ u16 reg15; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src2_stride:16; ++ }; ++ u16 reg16; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst2_stride:16; ++ }; ++ u16 reg17; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 src3_stride:16; ++ }; ++ u16 reg18; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 dst3_stride:16; ++ }; ++ u16 reg19; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask0:8; ++ u16 mask1:8; ++ }; ++ u16 reg1A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask2:8; ++ u16 mask3:8; ++ }; ++ u16 reg1B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask4:8; ++ u16 mask5:8; ++ }; ++ u16 reg1C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask6:8; ++ u16 mask7:8; ++ }; ++ u16 reg1D; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask8:8; ++ u16 mask9:8; ++ }; ++ u16 reg1E; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask10:8; ++ u16 mask11:8; ++ }; ++ u16 reg1F; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask12:8; ++ u16 mask13:8; ++ }; ++ u16 reg20; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask14:8; ++ u16 mask15:8; ++ }; ++ u16 reg21; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask16:8; ++ u16 mask17:8; ++ }; ++ u16 reg22; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask18:8; ++ u16 mask19:8; ++ }; ++ u16 reg23; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask20:8; ++ u16 mask21:8; ++ }; ++ u16 reg24; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask22:8; ++ u16 mask23:8; ++ }; ++ u16 reg25; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 mask24:8; ++ u16 shift:8; ++ }; ++ u16 reg26; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 thresh_16bit_1:16; ++ }; ++ u16 reg28; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 thresh_16bit_2:16; ++ }; ++ u16 reg29; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 fraction:16; ++ }; ++ u16 reg2A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 add_weight_x:16; ++ }; ++ u16 reg2B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 add_weight_y:16; ++ }; ++ u16 reg2C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff0:12; ++ }; ++ u16 reg30; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff1:12; ++ }; ++ u16 reg31; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff2:12; ++ }; ++ u16 reg32; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff3:12; ++ }; ++ u16 reg33; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff4:12; ++ }; ++ u16 reg34; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff5:12; ++ }; ++ u16 reg35; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff6:12; ++ }; ++ u16 reg36; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff7:12; ++ }; ++ u16 reg37; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_coeff8:12; ++ }; ++ u16 reg38; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_offset0:12; ++ }; ++ u16 reg39; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_offset1:12; ++ }; ++ u16 reg3A; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_offset2:12; ++ }; ++ u16 reg3B; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_clamp0_low:8; ++ u16 csc_clamp0_high:8; ++ }; ++ u16 reg3C; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_clamp1_low:8; ++ u16 csc_clamp1_high:8; ++ }; ++ u16 reg3D; ++ }; ++ ++ union ++ { ++ struct ++ { ++ u16 csc_clamp2_low:8; ++ u16 csc_clamp2_high:8; ++ }; ++ u16 reg3E; ++ }; ++ ++} ive_hal_reg_bank1; ++ ++#endif // _HAL_IVE_REG_H_ +diff --git a/drivers/mstar/ive/hal_ive_simulate.c b/drivers/mstar/ive/hal_ive_simulate.c +new file mode 100644 +index 00000000..6c8e7970 +--- /dev/null ++++ b/drivers/mstar/ive/hal_ive_simulate.c +@@ -0,0 +1,164 @@ ++#include "mdrv_ive.h" ++#include "hal_ive_simulate.h" ++ ++#include ++#include ++#include ++#include ++// #include ++ ++struct ive_simulation { ++ struct list_head list; ++ struct work_struct work_queue; ++ ive_dev_data *dev_data; ++}; ++ ++#if defined(IVE_SW_SIMULATE) ++ ++// We declare the function here because this API should not extern by default ++void mdrv_ive_drv_isr_post_proc(struct work_struct *wq); ++ ++// Static work queue data ++#define DATA_SIZE (10) ++static struct ive_simulation g_list_data[DATA_SIZE]; ++static LIST_HEAD(g_work_queue_list); ++ ++/******************************************************************************************************************* ++ * __get_work_queue_data ++ * Get a work queue data for simulation ++ * We need the paired API because work buffer can't free before work queue done ++ * Therefor a static linked list to prepared the work queue structure & relative data ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * work queue data ++ */ ++static struct ive_simulation* __get_work_queue_data(void) ++{ ++ int i; ++ ++ struct ive_simulation *list_data = NULL; ++ ++ // init g_work_queue_list ++ if (list_empty(&g_work_queue_list)) { ++ memset(g_list_data, 0, sizeof(g_list_data)); ++ IVE_MSG(IVE_MSG_DBG, "add work queue list\n"); ++ for (i=0; ilist, &g_work_queue_list); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_op_simulate ++ * A dummy simulation function. ++ * There is nothing to do because work queue is a kernel thread and has no way ++ * to get data from user space. ++ * ++ * Parameters: ++ * handle: hal handle ++ * ++ * Return: ++ * none ++ */ ++static void ive_hal_op_simulate(ive_hal_handle *handle) ++{ ++#define BLOCK_SIZE (64*1024) ++ ++ int i, length = handle->reg_bank1.frame_width * handle->reg_bank1.frame_height; ++ void *user_src0, *user_src1, *user_dst; ++ u16 weight_x, weight_y; ++ ++ weight_x = handle->reg_bank1.add_weight_x; ++ weight_y = handle->reg_bank1.add_weight_y; ++ ++ user_src0 = (void*)(handle->reg_bank1.src1_addr_high<<16 | handle->reg_bank1.src1_addr_low); ++ user_src1 = (void*)(handle->reg_bank1.src2_addr_high<<16 | handle->reg_bank1.src2_addr_low); ++ user_dst = (void*)(handle->reg_bank1.dst1_addr_high<<16 | handle->reg_bank1.dst1_addr_low); ++ ++ IVE_MSG(IVE_MSG_DBG, "0x%p, 0x%p, 0x%p (%d x %d)\n", user_src0, user_src1, user_dst, handle->reg_bank1.frame_width, handle->reg_bank1.frame_height); ++ ++ for (i=0; idev_data; ++ ++ ive_hal_op_simulate(&dev_data->drv_handle.hal_handle); ++ ++ ive_drv_isr_handler(0, &dev_data->drv_handle); ++ mdrv_ive_drv_isr_post_proc(&dev_data->work_queue); ++ ++ __return_work_queue_data(simulation); ++} ++ ++/******************************************************************************************************************* ++ * ive_hal_run_simulate ++ * A simulation for HW start. ++ * ++ * Parameters: ++ * handle: hal handle ++ * ++ * Return: ++ * none ++ */ ++ void ive_hal_run_simulate(ive_hal_handle *handle) ++{ ++ ive_drv_handle *drv_handle = container_of(handle, ive_drv_handle, hal_handle); ++ ive_dev_data *dev_data = container_of(drv_handle, ive_dev_data, drv_handle); ++ // struct ive_simulation *simulation = kzalloc(sizeof(struct ive_simulation), GFP_KERNEL); ++ struct ive_simulation *simulation = __get_work_queue_data(); ++ ++ IVE_MSG(IVE_MSG_DBG, "run simulation, dev_data = 0x%p\n", dev_data); ++ ++ simulation->dev_data = dev_data; ++ INIT_WORK(&simulation->work_queue, mdrv_ive_drv_isr_simulate); ++ schedule_work(&simulation->work_queue); ++} ++#endif +diff --git a/drivers/mstar/ive/hal_ive_simulate.h b/drivers/mstar/ive/hal_ive_simulate.h +new file mode 100644 +index 00000000..dc809970 +--- /dev/null ++++ b/drivers/mstar/ive/hal_ive_simulate.h +@@ -0,0 +1,9 @@ ++#ifndef _HAL_IVE_SIMULATE_H_ ++#define _HAL_IVE_SIMULATE_H_ ++ ++#include ++#include "hal_ive.h" ++ ++void ive_hal_run_simulate(ive_hal_handle *handle); ++ ++#endif // _HAL_IVE_SIMULATE_H_ +\ No newline at end of file +diff --git a/drivers/mstar/ive/mdrv_ive.c b/drivers/mstar/ive/mdrv_ive.c +new file mode 100644 +index 00000000..1ea53038 +--- /dev/null ++++ b/drivers/mstar/ive/mdrv_ive.c +@@ -0,0 +1,753 @@ ++#include "mdrv_ive.h" ++ ++// #include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include "mdrv_ive_io.h" ++#include "mdrv_ive_io_st.h" ++#include "drv_ive.h" ++ ++#define MDRV_IVE_DEVICE_COUNT (1) // How many device will be installed ++#define MDRV_IVE_NAME "mstar_ive" ++#define MDRV_IVE_MINOR (0) ++#define MDRV_IVE_CLASS_NAME "mstar_ive_class" ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Data Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Clock Enable ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_init ++ * init device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++static int mdrv_ive_clock_init(ive_dev_data *dev_data) ++{ ++ int i, ret = 0; ++ struct clk *clk_parent; ++ ++ IVE_MSG(IVE_MSG_DBG, "init clock\n"); ++ ++ dev_data->clk_num = of_clk_get_parent_count(dev_data->pdev->dev.of_node); ++ if (dev_data->clk_num <= 0) { ++ IVE_MSG(IVE_MSG_ERR, "incorrect clock number (%d)\n", dev_data->clk_num); ++ return -1; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data->clk_num = %d\n", dev_data->clk_num); ++ ++ dev_data->clk = devm_kcalloc(&dev_data->pdev->dev, 1, (sizeof(struct clk *) * dev_data->clk_num), GFP_KERNEL); ++ if (dev_data->clk == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "can't allocate buffer for clock\n"); ++ return -1; ++ } ++ ++ for (i=0; iclk_num; i++) { ++ dev_data->clk[i] = of_clk_get(dev_data->pdev->dev.of_node, i); ++ if (IS_ERR(dev_data->clk[i])) { ++ IVE_MSG(IVE_MSG_ERR, "can't get clock %s\n", of_clk_get_parent_name(dev_data->pdev->dev.of_node, i)); ++ ret = -1; ++ goto ERROR; ++ } ++ ++ if (i == 0) ++ { ++ clk_parent = clk_get_parent_by_index(dev_data->clk[i], 0); ++ if(IS_ERR(clk_parent)) ++ { ++ IVE_MSG(IVE_MSG_ERR, "can't get parent clock\n"); ++ ret = -1; ++ goto ERROR; ++ } ++ ++ /* Set clock parent */ ++ if (clk_set_parent(dev_data->clk[i], clk_parent)) ++ { ++ IVE_MSG(IVE_MSG_ERR, "can't set parent clock\n"); ++ ret = -1; ++ goto ERROR; ++ } ++ } ++ } ++ ++ return ret; ++ ++ERROR: ++ devm_kfree(&dev_data->pdev->dev, dev_data->clk); ++ dev_data->clk = NULL; ++ dev_data->clk_num = 0; ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_release ++ * release device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * none ++ */ ++static void mdrv_ive_clock_release(ive_dev_data *dev_data) ++{ ++ int i; ++ ++ IVE_MSG(IVE_MSG_DBG, "release clock\n"); ++ ++ ++ for (i=0; iclk_num; i++) { ++ clk_put(dev_data->clk[i]); ++ } ++ ++ devm_kfree(&dev_data->pdev->dev, dev_data->clk); ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_en ++ * enable device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++static int mdrv_ive_clock_en(ive_dev_data *dev_data) ++{ ++ int i, ret = 0; ++ ++ IVE_MSG(IVE_MSG_DBG, "enable clock\n"); ++ ++ for (i=0; iclk_num; i++) { ++ ret = clk_prepare_enable(dev_data->clk[i]); ++ if (ret) { ++ IVE_MSG(IVE_MSG_ERR, "can't enable clock\n"); ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_clock_dis ++ * disable device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, othes: failed ++ */ ++static void mdrv_ive_clock_dis(ive_dev_data *dev_data) ++{ ++ int i = 0; ++ ++ IVE_MSG(IVE_MSG_DBG, "disable clock\n"); ++ ++ for (i=0; iclk_num; i++) { ++ clk_disable_unprepare(dev_data->clk[i]); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// File operations ++//------------------------------------------------------------------------------------------------- ++ ++void mdrv_ive_drv_isr_post_proc(struct work_struct *wq) ++{ ++ ive_dev_data *dev_data = container_of(wq, ive_dev_data, work_queue); ++ ive_file_data *file_data; ++ ++ // Enter cirtical section ++ mutex_lock(&dev_data->mutex); ++ ++ file_data = ive_drv_post_process(&dev_data->drv_handle); ++ ++ mdrv_ive_clock_dis(dev_data); ++ ++ // Leave critical section ++ mutex_unlock(&dev_data->mutex); ++ ++ if (file_data == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "isr post process get NULL of file_data!!\n"); ++ return; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "post porcess 0x%p\n", &file_data->wait_queue); ++ ++ // set ready and wake up waiting thread/process ++ wake_up_interruptible(&file_data->wait_queue); ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_isr ++ * ISR handler ++ * ++ * Parameters: ++ * irq: IRQ ++ * dev_data: Device data which is assigned from request_irq() ++ * ++ * Return: ++ * Always IRQ_HANDLED to stop parsing ISR ++ */ ++irqreturn_t mdrv_ive_drv_isr(int irq, void* data) ++{ ++ ive_dev_data *dev_data = (ive_dev_data*)data; ++ IVE_DRV_STATE state; ++ ++ state = ive_drv_isr_handler(irq, &dev_data->drv_handle); ++ switch(state) { ++ case IVE_DRV_STATE_DONE: ++ INIT_WORK(&dev_data->work_queue, mdrv_ive_drv_isr_post_proc); ++ schedule_work(&dev_data->work_queue); ++ return IRQ_HANDLED; ++ ++ default: ++ return IRQ_NONE; ++ } ++ ++ return IRQ_NONE; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_open ++ * File open handler ++ * The device can has a instance at the same time, and the open ++ * operator also enable the clock and request q ISR. ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_ive_drv_open(struct inode *inode, struct file *filp) ++{ ++ ive_dev_data *dev_data = container_of(inode->i_cdev, ive_dev_data, cdev); ++ ive_file_data *file_data; ++ int err; ++ ++ // allocate buffer ++ file_data = devm_kcalloc(&dev_data->pdev->dev, 1, sizeof(ive_file_data), GFP_KERNEL); ++ if (file_data == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "error: can't allocate buffer\n"); ++ return -ENOSPC; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "filp: 0x%p, file_data: 0x%p\n", filp, file_data); ++ ++ // Assgin dev_data and keep file_data in the file structure ++ file_data->state = IVE_FILE_STATE_READY; ++ file_data->dev_data = dev_data; ++ filp->private_data = file_data; ++ ++ // Init wait queue ++ init_waitqueue_head(&file_data->wait_queue); ++ ++ // Enable clock ++ err = mdrv_ive_clock_en(dev_data); ++ if (err != 0) { ++ err = -EIO; ++ goto ERROR_1; ++ } ++ ++ return 0; ++ ++ERROR_1: ++ devm_kfree(&dev_data->pdev->dev, file_data); ++ ++ return err; ++ ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_release ++ * File close handler ++ * The operator will release clock & ISR ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_ive_drv_release(struct inode *inode, struct file *filp) ++{ ++ ive_file_data *file_data = (ive_file_data*)filp->private_data; ++ ive_dev_data *dev_data = file_data->dev_data; ++ ++ IVE_MSG(IVE_MSG_DBG, "filp: 0x%p\n", filp); ++ ++ // Release memory ++ devm_kfree(&dev_data->pdev->dev, file_data); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_ioctl_process ++ * IOCTL handler for IVE_IOC_PROCESS ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of ive_ioc_config from userspace ++ * ++ * Return: ++ * IVE_IOC_RET ++ */ ++static IVE_IOC_ERROR mdrv_ive_drv_ioctl_process(ive_file_data *file_data, unsigned long arg) ++{ ++ if (file_data->state != IVE_FILE_STATE_READY) { ++ IVE_MSG(IVE_MSG_ERR, "One file can request once at the same time only\n"); ++ return IVE_IOC_ERROR_BUSY; ++ } ++ ++ if (copy_from_user(&file_data->ioc_config, (void*)arg, sizeof(ive_ioc_config)) != 0) { ++ IVE_MSG(IVE_MSG_ERR, "Can't copy config from user space\n"); ++ return IVE_IOC_ERROR_PROC_CONFIG; ++ } ++ ++ file_data->user_io_config = (ive_ioc_config*)arg; ++ ++ return ive_drv_process(&(file_data->dev_data->drv_handle), file_data); ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_ioctl ++ * IOCTL handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * cmd: command ++ * arg: argument from user space ++ * ++ * Return: ++ * standard return value ++ */ ++long mdrv_ive_drv_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ ive_file_data *file_data = (ive_file_data*)filp->private_data; ++ ive_dev_data *dev_data = file_data->dev_data; ++ IVE_IOC_ERROR err = IVE_IOC_ERROR_NONE; ++ ++ IVE_MSG(IVE_MSG_DBG, "filp: 0x%p, command: 0x%X\n", filp, cmd); ++ ++ // Enter cirtical section ++ mutex_lock(&dev_data->mutex); ++ ++ if (mdrv_ive_clock_en(dev_data)) { ++ err = IVE_IOC_ERROR_CLK; ++ goto RETURN; ++ } ++ ++ switch(cmd) { ++ case IVE_IOC_PROCESS: ++ err = mdrv_ive_drv_ioctl_process(file_data, arg); ++ break; ++ ++ default: ++ err = ESRCH; ++ break; ++ } ++ ++RETURN: ++ ++ // Leave critical section ++ mutex_unlock(&dev_data->mutex); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_ioctl ++ * poll handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * wait: wait queue ++ * ++ * Return: ++ * only 0 or POLLIN | POLLRDNORM ++ */ ++static unsigned int mdrv_ive_drv_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ive_file_data *file_data = (ive_file_data*)filp->private_data; ++ ++ IVE_MSG(IVE_MSG_DBG, "polling 0x%p 0x%X\n", &file_data->wait_queue, file_data->state); ++ ++ if (file_data->state == IVE_FILE_STATE_READY) ++ { ++ return POLLIN | POLLRDNORM; ++ } ++ ++ poll_wait(filp, &file_data->wait_queue, wait); ++ ++ switch(file_data->state) ++ { ++ case IVE_FILE_STATE_DONE: ++ switch (file_data->ioc_config.op_type) ++ { ++ case IVE_IOC_OP_TYPE_NCC: ++ if (copy_to_user(file_data->user_io_config->coeff_ncc, &file_data->work_buffer.ncc_buffer, sizeof(ive_ioc_coeff_ncc)) != 0) ++ { ++ IVE_MSG(IVE_MSG_ERR, "Can't copy data back to user's structure\n"); ++ } ++ ++ file_data->state = IVE_FILE_STATE_READY; ++ ++ IVE_MSG(IVE_MSG_DBG, "NCC result %lld, %lld, %lld\n", file_data->work_buffer.ncc_buffer.numerator, file_data->work_buffer.ncc_buffer.sum1, file_data->work_buffer.ncc_buffer.sum2); ++ break; ++ ++ default: ++ file_data->state = IVE_FILE_STATE_READY; ++ break; ++ } ++ ++ return POLLIN | POLLRDNORM; ++ ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Platform functions ++//------------------------------------------------------------------------------------------------- ++ ++// Use a struct to gather all global variable ++static struct ++{ ++ int major; // cdev major number ++ int minor_star; // begining of cdev minor number ++ int reg_count; // registered count ++ struct class *class; // class pointer ++} g_ive_drv = {0, 0, 0, NULL}; ++ ++static const struct file_operations ive_fops = { ++ .owner = THIS_MODULE, ++ .open = mdrv_ive_drv_open, ++ .release = mdrv_ive_drv_release, ++ .unlocked_ioctl = mdrv_ive_drv_ioctl, ++ .poll = mdrv_ive_drv_poll, ++}; ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_probe ++ * Platform device prob handler ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_probe(struct platform_device *pdev) ++{ ++ int err; ++ ive_dev_data *dev_data; ++ struct resource *res0, *res1; ++ struct device *dev; ++ ++ // create drv data buffer ++ dev_data = devm_kcalloc(&pdev->dev, 1, sizeof(ive_dev_data), GFP_KERNEL); ++ if (dev_data == NULL) { ++ IVE_MSG(IVE_MSG_ERR, "can't allocate dev data buffer\n"); ++ return -ENOMEM; ++ } ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p (size = %d)\n", dev_data, sizeof(ive_dev_data)); ++ // Get base address ++ res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (res0 == NULL || res1 == NULL ) { ++ IVE_MSG(IVE_MSG_ERR, "can't find base address\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ mutex_init(&dev_data->mutex); ++ ++ // Init dev_data ++ dev_data->pdev = pdev; ++ if (ive_drv_init(&dev_data->drv_handle, pdev, res0->start, res1->start) < 0) ++ { ++ IVE_MSG(IVE_MSG_ERR, "can't init driver\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ // Init clock ++ if (mdrv_ive_clock_init(dev_data)) { ++ IVE_MSG(IVE_MSG_ERR, "can't init clock\n"); ++ err = -ENODEV; ++ goto ERROR_1; ++ } ++ ++ // Retrieve IRQ ++ dev_data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if (dev_data->irq == 0) { ++ IVE_MSG(IVE_MSG_ERR, "can't find IRQ\n"); ++ err = -ENODEV; ++ goto ERROR_2; ++ } ++ ++ // Register a ISR ++ err = request_irq(dev_data->irq, mdrv_ive_drv_isr, IRQ_TYPE_LEVEL_HIGH, "ive isr", dev_data); ++ if (err != 0) { ++ IVE_MSG(IVE_MSG_ERR, "isp interrupt failed (irq: %d, errno:%d)\n", dev_data->irq, err); ++ err = -ENODEV; ++ goto ERROR_2; ++ } ++ ++ // Add cdev ++ cdev_init(&dev_data->cdev, &ive_fops); ++ err= cdev_add(&dev_data->cdev, MKDEV(g_ive_drv.major, g_ive_drv.minor_star + g_ive_drv.reg_count), 1); ++ if (err) { ++ IVE_MSG(IVE_MSG_ERR, "Unable add a character device\n"); ++ goto ERROR_3; ++ } ++ ++ // Create a instance in class ++ dev = device_create(g_ive_drv.class, ++ NULL, ++ MKDEV(g_ive_drv.major, g_ive_drv.minor_star + g_ive_drv.reg_count), ++ dev_data, ++ MDRV_IVE_NAME"%d", g_ive_drv.minor_star + g_ive_drv.reg_count); ++ if (IS_ERR(dev)) { ++ IVE_MSG(IVE_MSG_ERR, "can't create device\n"); ++ err = -ENODEV; ++ goto ERROR_4; ++ } ++ ++ // Increase registered count ++ g_ive_drv.reg_count++; ++ ++ dev_set_drvdata(&pdev->dev, dev_data); ++ ++ return 0; ++ ++ERROR_4: ++ cdev_del(&dev_data->cdev); ++ ++ERROR_3: ++ free_irq(dev_data->irq, dev_data); ++ ++ERROR_2: ++ mdrv_ive_clock_release(dev_data); ++ ++ERROR_1: ++ devm_kfree(&dev_data->pdev->dev, dev_data); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_remove ++ * Platform device remove handler ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_remove(struct platform_device *pdev) ++{ ++ ive_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ mdrv_ive_clock_release(dev_data); ++ ++ free_irq(dev_data->irq, dev_data); ++ ++ ive_drv_release(&dev_data->drv_handle); ++ ++ device_destroy(g_ive_drv.class, dev_data->cdev.dev); ++ cdev_del(&dev_data->cdev); ++ ++ devm_kfree(&dev_data->pdev->dev, dev_data); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_suspend ++ * Platform device suspend handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ ive_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_ive_drv_resume ++ * Platform device resume handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platfrom device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_ive_drv_resume(struct platform_device *pdev) ++{ ++ ive_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ IVE_MSG(IVE_MSG_DBG, "dev_data: 0x%p\n", dev_data); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data strucure for device driver ++//------------------------------------------------------------------------------------------------- ++static const struct of_device_id mdrv_iveg_match[] = { ++ { ++ .compatible = "mstar,infinity3-ive", ++ /*.data = NULL,*/ ++ }, ++ {}, ++}; ++ ++ ++static struct platform_driver mdrv_ive_driver = { ++ .probe = mdrv_ive_drv_probe, ++ .remove = mdrv_ive_drv_remove, ++ .suspend = mdrv_ive_drv_suspend, ++ .resume = mdrv_ive_drv_resume, ++ ++ .driver = { ++ .of_match_table = of_match_ptr(mdrv_iveg_match), ++ .name = "mstar_ive", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * _mdrv_ive_module_init ++ * module init function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_ive_module_init(void) ++{ ++ int err; ++ dev_t dev; ++ ++ IVE_MSG(IVE_MSG_DBG, "Moudle Init\n"); ++ ++ // Allocate cdev id ++ err = alloc_chrdev_region(&dev, MDRV_IVE_MINOR, MDRV_IVE_DEVICE_COUNT, MDRV_IVE_NAME); ++ if (err) { ++ IVE_MSG(IVE_MSG_ERR, "Unable allocate cdev id\n"); ++ return err; ++ } ++ ++ g_ive_drv.major = MAJOR(dev); ++ g_ive_drv.minor_star = MINOR(dev); ++ g_ive_drv.reg_count = 0; ++ ++ // Register device class ++ g_ive_drv.class = class_create(THIS_MODULE, MDRV_IVE_CLASS_NAME); ++ if (IS_ERR(g_ive_drv.class)) { ++ IVE_MSG(IVE_MSG_ERR, "Failed at class_create().Please exec [mknod] before operate the device/n"); ++ err = PTR_ERR(g_ive_drv.class); ++ goto ERR_RETURN_1; ++ } ++ ++ // Register platform driver ++ err = platform_driver_register(&mdrv_ive_driver); ++ if (err != 0) { ++ goto ERR_RETURN_2; ++ } ++ ++ return 0; ++ ++ERR_RETURN_2: ++ class_destroy(g_ive_drv.class); ++ ++ERR_RETURN_1: ++ unregister_chrdev_region(MKDEV(g_ive_drv.major, g_ive_drv.minor_star), MDRV_IVE_DEVICE_COUNT); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_ive_module_exit ++ * module exit function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++void mdrv_ive_module_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ IVE_MSG(IVE_MSG_DBG, "Modules Exit\n"); ++ ++ platform_driver_unregister(&mdrv_ive_driver); ++ class_destroy(g_ive_drv.class); ++ unregister_chrdev_region(MKDEV(g_ive_drv.major, g_ive_drv.minor_star), MDRV_IVE_DEVICE_COUNT); ++} ++ ++module_init(mdrv_ive_module_init); ++module_exit(mdrv_ive_module_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("IVE ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/ive/mdrv_ive.h b/drivers/mstar/ive/mdrv_ive.h +new file mode 100644 +index 00000000..5d94ba9a +--- /dev/null ++++ b/drivers/mstar/ive/mdrv_ive.h +@@ -0,0 +1,59 @@ ++#include ++#include ++#include ++#include ++ ++#include "mdrv_ive_data.h" ++#include "hal_ive.h" ++#include "mdrv_ive_io_st.h" ++ ++#ifndef _MDRV_IVE_H_ ++#define _MDRV_IVE_H_ ++ ++// SW simulation for driver debug without real HW ++// #define IVE_SW_SIMULATE ++ ++// Defines reference kern levels of printfk ++#define IVE_MSG_ERR 3 ++#define IVE_MSG_WRN 4 ++#define IVE_MSG_DBG 5 ++ ++#define IVE_MSG_LEVL IVE_MSG_WRN ++ ++ ++#define IVE_MSG_ENABLE ++ ++#if defined(IVE_MSG_ENABLE) ++#define IVE_MSG_FUNC_ENABLE ++ ++#define IVE_STRINGIFY(x) #x ++#define IVE_TOSTRING(x) IVE_STRINGIFY(x) ++ ++#if defined(IVE_MSG_FUNC_ENABLE) ++#define IVE_MSG_TITLE "[IVE, %s] " ++#define IVE_MSG_FUNC __func__ ++#else // NOT defined(IVE_MSG_FUNC_ENABLE) ++#define IVE_MSG_TITLE "[IVE] %s" ++#define IVE_MSG_FUNC "" ++#endif // NOT defined(IVE_MSG_FUNC_ENABLE) ++ ++#define IVE_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define IVE_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= IVE_MSG_LEVL) { \ ++ printk(KERN_SOH IVE_TOSTRING(dbglv) IVE_MSG_TITLE _fmt, IVE_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++#else // NOT defined(IVE_MSG_ENABLE) ++#define IVE_ASSERT(arg) ++#define IVE_MSG(dbglv, _fmt, _args...) ++#endif // NOT defined(IVE_MSG_ENABLE) ++ ++#endif //_MDRV_IVE_H_ +diff --git a/drivers/mstar/ive/mdrv_ive_data.h b/drivers/mstar/ive/mdrv_ive_data.h +new file mode 100644 +index 00000000..dead5da6 +--- /dev/null ++++ b/drivers/mstar/ive/mdrv_ive_data.h +@@ -0,0 +1,82 @@ ++#include "hal_ive.h" ++#include "mdrv_ive_io_st.h" ++ ++#ifndef _MDRV_IVE_DATA_H_ ++#define _MDRV_IVE_DATA_H_ ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++// Driver Data Structure ++// ++// Enum and structure fo IVE dirver ++// We declare enum & structure here because enum and structures are ++// shared in all three layers (mdrv, drv, and hal_simulation) ++// ++// It is not good way for modulization, but most members of structure are not pointer ++// because it can simplify the memory managent ++// and container_of() is a key funtion to access data strucure in operators ++// ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * There are 2 state enumeration ++ * IVE_DRV_STATE: indicate the state of HW ++ * IVE_FILE_STATE: indicate the state of File ++ * ++ * File and HW has different state because it support multi instance ++ * and file request may be queued if HW is busy ++ */ ++typedef enum ++{ ++ IVE_DRV_STATE_READY = 0, ++ IVE_DRV_STATE_PROCESSING = 1, ++ IVE_DRV_STATE_DONE = 2 ++} IVE_DRV_STATE; ++ ++typedef enum ++{ ++ IVE_FILE_STATE_READY = 0, ++ IVE_FILE_STATE_PROCESSING = 1, ++ IVE_FILE_STATE_DONE = 2, ++ IVE_FILE_STATE_IN_QUEUE = 3 ++} IVE_FILE_STATE; ++ ++typedef union ++{ ++ ive_ioc_coeff_ncc ncc_buffer; ++ __u8 map_buffer[256]; ++} ive_work_buffer; ++ ++// Data structure for driver ++typedef struct ++{ ++ struct platform_device *pdev; // platform device data ++ ive_hal_handle hal_handle; // HAL handle for real HW configuration ++ IVE_DRV_STATE dev_state; // HW state ++ struct list_head request_list; // request list to queue waiting requst ++ ive_work_buffer *work_buffer; // working buffer ++ dma_addr_t work_buffer_dma;// working buffer pysical address ++} ive_drv_handle; ++ ++// Device data ++typedef struct { ++ struct platform_device *pdev; // platform device data ++ struct cdev cdev; // character device ++ struct clk **clk; // clock ++ int clk_num; // clock number ++ unsigned int irq; // IRQ number ++ ive_drv_handle drv_handle; // device handle ++ struct work_struct work_queue; // work queue for post process after ISR ++ struct mutex mutex; // for critical section ++} ive_dev_data; ++ ++// File private data ++typedef struct{ ++ ive_dev_data *dev_data; // Device data ++ ive_ioc_config ioc_config; // IO configuation, i.e. one device file can service one request at the same time ++ IVE_FILE_STATE state; // File state ++ wait_queue_head_t wait_queue; // Wait queue for polling operation ++ ive_ioc_config *user_io_config;// IO configuation pointer from user space ++ ive_work_buffer work_buffer; ++} ive_file_data; ++ ++#endif //_MDRV_IVE_DATA_H_ +\ No newline at end of file +diff --git a/drivers/mstar/jpe/Kconfig b/drivers/mstar/jpe/Kconfig +new file mode 100644 +index 00000000..8951354f +--- /dev/null ++++ b/drivers/mstar/jpe/Kconfig +@@ -0,0 +1,3 @@ ++config MS_JPE ++ tristate "Mstar JPE driver" ++ help +diff --git a/drivers/mstar/jpe/Makefile b/drivers/mstar/jpe/Makefile +new file mode 100644 +index 00000000..8577874c +--- /dev/null ++++ b/drivers/mstar/jpe/Makefile +@@ -0,0 +1,25 @@ ++# ++# Makefile for MStar Infinity JPE device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/jpe ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++ccflags-$(CONFIG_MS_JPE) += -DMSOS_TYPE_LINUX_KERNEL ++ ++# files ++ ++#----------------------- drv ----------------------- ++EXTRA_CFLAGS += -Idrivers/mstar/jpe/drv/jpe/inc ++EXTRA_CFLAGS += -Idrivers/mstar/jpe/drv/jpe/pub ++ ++#----------------------- hal ----------------------- ++EXTRA_CFLAGS += -Idrivers/mstar/jpe/hal/jpe/inc ++EXTRA_CFLAGS += -Idrivers/mstar/jpe/hal/jpe/pub ++ ++#--------------------- sources --------------------- ++obj-$(CONFIG_MS_JPE) += mstar_jpe.o ++mstar_jpe-y := mdrv_jpe.o \ ++ jpe_scatter.o \ ++ hal/jpe/src/hal_jpe.o \ ++ drv/jpe/src/drv_jpe.o +diff --git a/drivers/mstar/jpe/drv/jpe/inc/drv_clkgen_cmu.h b/drivers/mstar/jpe/drv/jpe/inc/drv_clkgen_cmu.h +new file mode 100644 +index 00000000..0801c907 +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/drv_clkgen_cmu.h +@@ -0,0 +1,8 @@ ++ ++#include "drv_clkgen_cmu_types.h" ++#include "drv_clkgen_cmu_forward.h" ++#include "drv_clkgen_cmu_api.h" ++#ifdef __I_SW__ ++//#include "hal_clkgen.h" ++#endif ++ +diff --git a/drivers/mstar/jpe/drv/jpe/inc/drv_jpe.h b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe.h +new file mode 100644 +index 00000000..00f23392 +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe.h +@@ -0,0 +1,36 @@ ++#ifndef _JPE_DRV_H_ ++#define _JPE_DRV_H_ ++ ++#include "hal_jpe.h" ++#include "mdrv_jpe_io_st.h" ++ ++#define MAX_BANK_NUM 4 ++#define BistreamInfo_t JpeBitstreamInfo_t ++#define pBistreamInfo pJpeBitstreamInfo ++ ++typedef enum ++{ ++ JPE_DEV_INIT = 0, ++ JPE_DEV_BUSY, ++ JPE_DEV_ENC_DONE, ++ JPE_DEV_OUTBUF_FULL, ++ JPE_DEV_INBUF_FULL ++} JpeDevStatus_e; ++ ++typedef struct ++{ ++ JpeHalHandle_t jpeHalHandle; ++ JpeCfg_t jpeCfg; ++ JpeDevStatus_e ejpeDevStatus; ++ u32 nEncodeSize; ++} JpeHandle_t, *pJpeHandle; ++ ++void JpeIsrHandler(int eIntNum, JpeHandle_t *jpeHandle); ++ ++void DrvJpeReset(JpeHandle_t *jpeHandle); ++JPE_IOC_RET_STATUS_e DrvJpeInit(JpeHandle_t *jpeHandle, pJpeCfg pJpeCfg); ++JPE_IOC_RET_STATUS_e DrvJpeEncodeOneFrame(JpeHandle_t *jpeHandle,JpeHalOutBufCfg_t* jpeHalBuf); ++JPE_IOC_RET_STATUS_e DrvJpeSetOutBuf(JpeHandle_t *jpeHandle, JpeBufInfo_t *jpeBuf); ++JPE_IOC_RET_STATUS_e DrvJpeGetCaps(JpeHandle_t *jpeHandle, JpeCaps_t *pCaps); ++ ++#endif +diff --git a/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_dct.h b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_dct.h +new file mode 100644 +index 00000000..4cbc3f6c +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_dct.h +@@ -0,0 +1,17 @@ ++#ifndef DRV_JPE_DCT_H ++#define DRV_JPE_DCT_H ++ ++#include "drv_jpe.h" ++ ++ ++#if defined(_FPGA_) || defined(_UDMA_) || defined(_HIF_) ++ #include "fpgaapi.h" ++#endif ++#if defined(MSTAR_JPD_IDCT) ++#include "udma_share.h" ++JPE_IOC_RET_STATUS_e JpeDctInit(void); // Initialize DCT-reuse mode reg settings. ++JPE_IOC_RET_STATUS_e JpeDctFire(MEMMAP_t* pMemMap); // Fire JPE. ++JPE_IOC_RET_STATUS_e JpeDctDoneCheck(MEMMAP_t* pMemMap); // Check JPE frame down, and then clean int flag. ++JPE_IOC_RET_STATUS_e JpeDctSwitchToJPD(void); // Switch to JPD mode for later JPD IDCT-reuse phase. ++#endif ++#endif // DRV_JPE_dCT_H +diff --git a/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_ms_dprintf.h b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_ms_dprintf.h +new file mode 100644 +index 00000000..b651f51f +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_ms_dprintf.h +@@ -0,0 +1,109 @@ ++#ifndef DRV_JPE_MS_DPRINTF_H ++#define DRV_JPE_MS_DPRINTF_H ++ ++#if !defined(DEBUG_LEVEL) ++#define DEBUG_LEVEL 0 ++#endif ++ ++#ifdef _MSC_VER ++ ++#if DEBUG_LEVEL == 0 ++ ++//static __inline void ms_dprintf(int level, const char *fmt, ...) {} ++ ++#include ++#include ++//#include ++ ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if(level <= 1) return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++ fprintf(stdout, "%s", msg); ++ va_end(ap); ++} ++ ++#else /* DEBUG_LEVEL */ ++ ++#include ++#include ++//#include ++ ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if (level > DEBUG_LEVEL) ++ return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++#ifdef WINCE ++ fprintf(stderr, "%s", msg); ++#else ++ OutputDebugStringA(msg); ++#endif ++ va_end(ap); ++} ++ ++#endif /* DEBUG_LEVEL */ ++ ++#else /* _MSC_VER */ ++ ++#if DEBUG_LEVEL == 0 ++ ++#define ms_dprintf(arg...) ((void) 0) ++ ++#else /* DEBUG_LEVEL */ ++ ++#ifdef MIPSDEV ++ ++#include ++ ++#define ms_dprintf(level, fmt, arg...) \ ++ do { \ ++ if (level <= DEBUG_LEVEL) diag_printf(fmt, ##arg); \ ++ } while (0) ++#elif defined __I_SW__ ++#include ++#include ++#include "sys_sys_isw_uart.h" // send_trace ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if (level > DEBUG_LEVEL) ++ return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++ send_msg(msg); ++ va_end(ap); ++} ++ ++ ++#else /* MIPSDEV */ ++ ++#if 1 ++#define ms_dprintf(level, fmt, arg...) ++#else ++#define ms_dprintf(level, fmt, arg...) \ ++ do { \ ++ if (level <= DEBUG_LEVEL) printf(fmt, ##arg); \ ++ } while (0) ++#endif ++ ++#endif /* MIPSDEV */ ++ ++#endif /* DEBUG_LEVEL */ ++ ++#endif /* _MSC_VER */ ++ ++#endif /* MS_DPRINTF_H */ +diff --git a/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_test_big5.h b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_test_big5.h +new file mode 100644 +index 00000000..7614a673 +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_test_big5.h +@@ -0,0 +1,23 @@ ++#ifdef __VER_JPE__ ++ ++extern int testJpeBurn_B5( CLI_t *pCli, char *p ); ++extern int testJpeISR_B5( CLI_t *pCli, char *p ); ++extern int testJpeReshoot_B5( CLI_t *pCli, char *p ); ++extern int testJpeStop_B5( CLI_t *pCli, char *p ); ++extern int testJpeIdleCnt_B5( CLI_t *pCli, char *p ); ++extern int testJpeMulitiOutbuf_B5( CLI_t *pCli, char *p ); ++extern int testJpeSignalObuf_B5( CLI_t *pCli, char *p ); ++extern int testJpeFrame422_B5( CLI_t *pCli, char *p ); ++extern int testJpeFrame420_B5( CLI_t *pCli, char *p ); ++extern int testJpeRow422_B5( CLI_t *pCli, char *p ); ++extern int testJpeRow420_B5( CLI_t *pCli, char *p ); ++extern int testJpeRing422_B5( CLI_t *pCli, char *p ); ++extern int testJpeRing420_B5( CLI_t *pCli, char *p ); ++extern int testH263QcifFrame_B5( CLI_t *pCli, char *p ); ++extern int testH263QcifRow_B5( CLI_t *pCli, char *p ); ++extern int testH263QcifRing_B5( CLI_t *pCli, char *p ); ++extern int testH263CifFrame_B5( CLI_t *pCli, char *p ); ++extern int testH263CifRow_B5( CLI_t *pCli, char *p ); ++extern int testGetYCBufInfo_B5( CLI_t *pcli, char *p ); ++#endif ++ +diff --git a/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_types.h b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_types.h +new file mode 100644 +index 00000000..a41582bf +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/drv_jpe_types.h +@@ -0,0 +1,6 @@ ++#ifndef _JPE_DRV_TYPES_H_ ++#define _JPE_DRV_TYPES_H_ ++ ++#include "drv_jpe_pub.h" ++ ++#endif +diff --git a/drivers/mstar/jpe/drv/jpe/inc/ms_dprintf.h b/drivers/mstar/jpe/drv/jpe/inc/ms_dprintf.h +new file mode 100644 +index 00000000..df5e1305 +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/inc/ms_dprintf.h +@@ -0,0 +1,109 @@ ++#ifndef MS_DPRINTF_H ++#define MS_DPRINTF_H ++ ++#if !defined(DEBUG_LEVEL) ++#define DEBUG_LEVEL 0 ++#endif ++ ++#ifdef _MSC_VER ++ ++#if DEBUG_LEVEL == 0 ++ ++//static __inline void ms_dprintf(int level, const char *fmt, ...) {} ++ ++#include ++#include ++//#include ++ ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if(level <= 1) return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++ fprintf(stdout, "%s", msg); ++ va_end(ap); ++} ++ ++#else /* DEBUG_LEVEL */ ++ ++#include ++#include ++//#include ++ ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if (level > DEBUG_LEVEL) ++ return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++#ifdef WINCE ++ fprintf(stderr, "%s", msg); ++#else ++ OutputDebugStringA(msg); ++#endif ++ va_end(ap); ++} ++ ++#endif /* DEBUG_LEVEL */ ++ ++#else /* _MSC_VER */ ++ ++#if DEBUG_LEVEL == 0 ++ ++#define ms_dprintf(arg...) ((void) 0) ++ ++#else /* DEBUG_LEVEL */ ++ ++#ifdef MIPSDEV ++ ++#include ++ ++#define ms_dprintf(level, fmt, arg...) \ ++ do { \ ++ if (level <= DEBUG_LEVEL) diag_printf(fmt, ##arg); \ ++ } while (0) ++#elif defined __I_SW__ ++#include ++#include ++#include "sys_sys_isw_uart.h" // send_trace ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if (level > DEBUG_LEVEL) ++ return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++ send_msg(msg); ++ va_end(ap); ++} ++ ++ ++#else /* MIPSDEV */ ++ ++#if 1 ++#define ms_dprintf(level, fmt, arg...) ++#else ++#define ms_dprintf(level, fmt, arg...) \ ++ do { \ ++ if (level <= DEBUG_LEVEL) printf(fmt, ##arg); \ ++ } while (0) ++#endif ++ ++#endif /* MIPSDEV */ ++ ++#endif /* DEBUG_LEVEL */ ++ ++#endif /* _MSC_VER */ ++ ++#endif /* MS_DPRINTF_H */ +diff --git a/drivers/mstar/jpe/drv/jpe/src/drv_jpe.c b/drivers/mstar/jpe/drv/jpe/src/drv_jpe.c +new file mode 100644 +index 00000000..fb217db1 +--- /dev/null ++++ b/drivers/mstar/jpe/drv/jpe/src/drv_jpe.c +@@ -0,0 +1,411 @@ ++#include ++#include ++#include ++#include ++#include ++#include "hal_jpe.h" ++#include "drv_jpe.h" ++#include "mdrv_jpe.h" ++ ++/******************************************************************************************************************* ++ * _DrvJpeCheckCfg ++ * Config check ++ * ++ * Parameters: ++ * pJpeCgfg: JPEG configurations ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e _DrvJpeCheckCfg(JpeCfg_t *pCfg) ++{ ++ int align; ++ ++ // Support JPEG only ++ if(pCfg->eCodecFormat != JPE_CODEC_JPEG) ++ return JPE_IOC_RET_FMT_NOT_SUPPORT; ++ ++ // Alignment check ++ align = (pCfg->eRawFormat == JPE_RAW_NV12 || pCfg->eRawFormat == JPE_RAW_NV21) ? 16 : 8; ++ if(pCfg->nWidth % align) ++ { ++ JPE_MSG(JPE_MSG_ERR, "source width is not aligned to %d\n", align); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ if(pCfg->nHeight % align) ++ { ++ JPE_MSG(JPE_MSG_ERR, "source height is not aligned to %d\n", align); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ // Input buffer check ++ if(pCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr == 0 || pCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize == 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Input buffer is not assigned\n"); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/******************************************************************************************************************* ++ * _DrvJpeSetInBuf ++ * Assign an input buffer. ++ * This is a static wrapper function because upper layer use only one pointer as a input buffer point. ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * jpeBuf: input buffer ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++//static JPE_IOC_RET_STATUS_e _DrvJpeSetInBuf(JpeHandle_t *jpeHandle, JpeBufInfo_t *jpeBuf) ++static JPE_IOC_RET_STATUS_e _DrvJpeSetInBuf(JpeHandle_t *jpeHandle, JpeCfg_t *pJpeCfg) ++{ ++ u32 size; ++ JpeHalInBufCfg_t inBufCfg; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "set 0x%08lX, size %ld as input buffer\n", pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr, pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize); ++ ++ // Set input buffer ++ switch(jpeHandle->jpeCfg.eRawFormat) ++ { ++ case JPE_RAW_YUYV: ++ case JPE_RAW_YVYU: ++ if(jpeHandle->jpeCfg.eInBufMode == JPE_IBUF_FRAME_MODE) ++ { ++ inBufCfg.nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ inBufCfg.nInBufYAddr[1] = 0; ++ inBufCfg.nInBufCAddr[0] = 0; ++ inBufCfg.nInBufCAddr[1] = 0; ++ } ++ else if(jpeHandle->jpeCfg.eInBufMode == JPE_IBUF_ROW_MODE) ++ { ++ // Assume the user allocate big enough buffer and scaler also follow the same order ++ // If not, we may change the IF to follow the behavior of scaler ++ size = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize / 2; ++ inBufCfg.nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ inBufCfg.nInBufYAddr[1] = inBufCfg.nInBufYAddr[0] + size; ++ inBufCfg.nInBufCAddr[0] = 0; ++ inBufCfg.nInBufCAddr[1] = 0; ++ } ++ else ++ { ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ break; ++ case JPE_RAW_NV12: ++ case JPE_RAW_NV21: ++ if(jpeHandle->jpeCfg.eInBufMode == JPE_IBUF_FRAME_MODE) ++ { ++// size = ((jpeHandle->jpeCfg.nWidth+0x0f)&~0x0f) * ((jpeHandle->jpeCfg.nHeight+0x0f)&~0x0f); ++ inBufCfg.nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ inBufCfg.nInBufYAddr[1] = 0; ++ inBufCfg.nInBufCAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr; ++ inBufCfg.nInBufCAddr[1] = 0; ++ } ++ else if(jpeHandle->jpeCfg.eInBufMode == JPE_IBUF_ROW_MODE) ++ { ++ // Assume the user allocate big enough buffer and scaler also follow the same order ++ // If not, we may change the IF to follow the behavior of scaler ++ size = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize / 4; ++ inBufCfg.nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ inBufCfg.nInBufYAddr[1] = inBufCfg.nInBufYAddr[0] + size; ++ inBufCfg.nInBufCAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr; ++ inBufCfg.nInBufCAddr[1] = inBufCfg.nInBufCAddr[0] + size; ++ } ++ else ++ { ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ break; ++ } ++ HalJpeSetInBuf(&jpeHandle->jpeHalHandle, &inBufCfg); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/******************************************************************************************************************* ++ * JpeIsrHandler ++ * ISR handler ++ * ++ * Parameters: ++ * eIntNum: interrupt number ++ * jpeHandle: device handle ++ * ++ * Return: ++ * None ++ */ ++void JpeIsrHandler(int eIntNum, JpeHandle_t *jpeHandle) ++{ ++ JPE_MSG(JPE_MSG_DEBUG, "Interrupt: %X\n", HalJpeGetIrq(&jpeHandle->jpeHalHandle)); ++ ++ /* JPE_IRQ_BSPOBUF_FULL */ ++ if(HalJpeGetIrqCheck(&jpeHandle->jpeHalHandle,JPE_HAL_IRQ_BSPOBUF0_FULL)) ++ { ++ /* Status update */ ++ jpeHandle->nEncodeSize = HalJpeGetOutputByteSize(&jpeHandle->jpeHalHandle,0); ++ jpeHandle->ejpeDevStatus = JPE_DEV_OUTBUF_FULL; ++ ++ /* Clear IRQ */ ++ HalJpeClearIrq(&jpeHandle->jpeHalHandle,JPE_HAL_IRQ_BSPOBUF0_FULL); ++ } ++ ++ /* JPE_IRQ_BSPOBUF1_FULL */ ++ if(HalJpeGetIrqCheck(&jpeHandle->jpeHalHandle,JPE_HAL_IRQ_BSPOBUF1_FULL)) ++ { ++ /* Status update */ ++ jpeHandle->nEncodeSize = HalJpeGetOutputByteSize(&jpeHandle->jpeHalHandle,1); ++ jpeHandle->ejpeDevStatus = JPE_DEV_OUTBUF_FULL; ++ ++ /* Clear IRQ */ ++ HalJpeClearIrq(&jpeHandle->jpeHalHandle,JPE_HAL_IRQ_BSPOBUF1_FULL); ++ } ++ ++ /* JPE_IRQ_FRAME_DONE */ ++ if(HalJpeGetIrqCheck(&jpeHandle->jpeHalHandle,JPE_HAL_IRQ_FRAME_DONE)) ++ { ++ /* Status update */ ++ jpeHandle->nEncodeSize = HalJpeGetOutputByteSize(&jpeHandle->jpeHalHandle,0); ++ jpeHandle->ejpeDevStatus = JPE_DEV_ENC_DONE; ++ ++// JPE_MSG(JPE_MSG_DEBUG, "size = %d\n", jpeHandle->nEncodeSize); ++ ++ /* Clear IRQ */ ++ HalJpeClearIrq(&jpeHandle->jpeHalHandle,JPE_HAL_IRQ_FRAME_DONE); ++ } ++} ++ ++/******************************************************************************************************************* ++ * DrvJpeReset ++ * Reset low level driver & variables ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * ++ * Return: ++ * none ++ */ ++void DrvJpeReset(JpeHandle_t *jpeHandle) ++{ ++ /* Reset HAL JPE */ ++// HalJpeSoftReset(&jpeHandle->jpeHalHandle); ++ ++ /* Reset variables */ ++ jpeHandle->ejpeDevStatus = JPE_DEV_INIT; ++ jpeHandle->nEncodeSize = 0; ++} ++ ++/******************************************************************************************************************* ++ * DrvJpeInit ++ * Init JPEG settings ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * pJpeCgfg: JPEG configurations ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++JPE_IOC_RET_STATUS_e DrvJpeInit(JpeHandle_t *jpeHandle, pJpeCfg pJpeCfg) ++{ ++ JPE_IOC_RET_STATUS_e ret = JPE_IOC_RET_SUCCESS; ++ ++ /* HW reset */ ++ DrvJpeReset(jpeHandle); ++ ++ ret = _DrvJpeCheckCfg(pJpeCfg); ++ if(ret != JPE_IOC_RET_SUCCESS) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "some parameter settings are wrong...\n"); ++ return ret; ++ } ++ ++ memcpy((void*)&jpeHandle->jpeCfg, pJpeCfg, sizeof(JpeCfg_t)); ++ ++ /* Force output mode as single buffer mode because it is simpler ++ * and has the same overhead as toggled output buffer ++ */ ++// HalJpeSetOutputMode(&jpeHandle->jpeHalHandle,JPE_HAL_OBUF_SINGLE_MODE); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/******************************************************************************************************************* ++ * DrvJpeSetOutBuf ++ * Assign a output buffer. ++ * Output buffer setting is separated from normal config because driver support virtual memory as output buffer. ++ * I.e. the upper layer can assign smaller buffer and assign again when previous buffer is full ++ * ++ * This implementation for virtual memory does not introduce the toggle buffer because single buffer is simpler and ++ * the same overhead. ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * jpeBuf: output buffer ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++JPE_IOC_RET_STATUS_e DrvJpeSetOutBuf(JpeHandle_t *jpeHandle, JpeBufInfo_t *jpeBuf) ++{ ++ JpeHalOutBufCfg_t jpeHalBuf; ++ ++ jpeHalBuf.nOutBufAddr[0] = jpeBuf->nAddr; ++ jpeHalBuf.nOutBufSize[0] = jpeBuf->nSize; ++ jpeHalBuf.nOutBufSize[1] = 0; ++ jpeHalBuf.nOutBufAddr[1] = 0; ++ ++ jpeHalBuf.nJpeOutBitOffset = jpeHandle->jpeCfg.nJpeOutBitOffset; ++ ++ HalJpeSetOutBuf(&jpeHandle->jpeHalHandle,&jpeHalBuf); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/******************************************************************************************************************* ++ * DrvJpeSetQTable ++ * Calculate & assign quantization tables ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * q_table_y: Q table for Y ++ * q_table_c: Q table for C ++ * size: size of Q table ++ * q_scale: Quantization scale, a value which is 100-based value, default is 50 ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e DrvJpeSetQTable(JpeHandle_t *jpeHandle, const u16 *q_table_y, const u16 *q_table_c, u32 size, const u16 q_scale) ++{ ++ u16 *y_table, *c_table; ++ JPE_IOC_RET_STATUS_e ret = JPE_IOC_RET_SUCCESS; ++ int i; ++ ++ y_table = kcalloc(size, sizeof(u16), GFP_KERNEL); ++ c_table = kcalloc(size, sizeof(u16), GFP_KERNEL); ++ ++ for(i=0; ijpeHalHandle,y_table, c_table, size) != 0) ++ { ++ ret = JPE_IOC_RET_BAD_QTABLE; ++ } ++ ++ kfree(y_table); ++ kfree(c_table); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/******************************************************************************************************************* ++ * DrvJpeEncodeOneFrame ++ * Start JPE to encode one frame into a JPEG ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++JPE_IOC_RET_STATUS_e DrvJpeEncodeOneFrame(JpeHandle_t *jpeHandle, JpeHalOutBufCfg_t* jpeHalBuf) ++{ ++ JPE_IOC_RET_STATUS_e ret; ++ ++ /* Can't trigger HW if it is triggered */ ++ if(jpeHandle->ejpeDevStatus != JPE_DEV_INIT && jpeHandle->ejpeDevStatus != JPE_DEV_ENC_DONE) ++ { ++ return JPE_IOC_RET_HW_IS_RUNNING; ++ } ++ ++ /* HW reset */ ++// HalJpeSoftReset(); ++ ++ HalJpeSoftReset(&jpeHandle->jpeHalHandle); ++ ++ HalJpeSetOutputMode(&jpeHandle->jpeHalHandle, JPE_HAL_OBUF_SINGLE_MODE); ++ ++ HalJpeSetOutBuf(&jpeHandle->jpeHalHandle, jpeHalBuf); ++ /* Clear IRQ */ ++ HalJpeClearIrq(&jpeHandle->jpeHalHandle, JPE_HAL_IRQ_ALL); ++ ++ /* Set image dimension */ ++ HalJpeSetPicDim(&jpeHandle->jpeHalHandle, jpeHandle->jpeCfg.nWidth, jpeHandle->jpeCfg.nHeight); ++ ++ /* Set codec mode */ ++ HalJpeSetCodecFormat(&jpeHandle->jpeHalHandle, jpeHandle->jpeCfg.eCodecFormat); ++ ++ /* Set YUV format */ ++ HalJpeSetRawFormat(&jpeHandle->jpeHalHandle, jpeHandle->jpeCfg.eRawFormat); ++ ++ /* Set input mode */ ++ HalJpeSetInputMode(&jpeHandle->jpeHalHandle, jpeHandle->jpeCfg.eInBufMode); ++ ++ /* Quantization table */ ++ ret = DrvJpeSetQTable(jpeHandle, jpeHandle->jpeCfg.YQTable, jpeHandle->jpeCfg.CQTable, ARRAY_SIZE(jpeHandle->jpeCfg.YQTable), jpeHandle->jpeCfg.nQScale); ++ if(ret != JPE_IOC_RET_SUCCESS) ++ { ++ return ret; ++ } ++ ++ /* Set input buffer */ ++ if(jpeHandle->jpeCfg.InBuf[JPE_COLOR_PLAN_LUMA].nAddr != 0 && jpeHandle->jpeCfg.InBuf[JPE_COLOR_PLAN_LUMA].nSize != 0) ++ { ++ _DrvJpeSetInBuf(jpeHandle, &jpeHandle->jpeCfg); ++ } ++ else ++ { ++ /* unlike the output buffer, this is a only place to set input buffer ++ * So we return error if buffer is not assigned ++ */ ++ JPE_MSG(JPE_MSG_DEBUG, "Illegal input buffer addr 0x%08lX, size %ld\n", jpeHandle->jpeCfg.InBuf[JPE_COLOR_PLAN_LUMA].nAddr, jpeHandle->jpeCfg.InBuf[JPE_COLOR_PLAN_LUMA].nSize); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ /* Remvoe IRQ mask, and only 3 bits are meaningful */ ++ HalJpeSetIrqMask(&jpeHandle->jpeHalHandle,0); ++ ++ /* Enable HW */ ++ HalJpeSetEnable(&jpeHandle->jpeHalHandle); ++ jpeHandle->ejpeDevStatus = JPE_DEV_BUSY; ++ ++ return JPE_IOC_RET_SUCCESS; ++ ++} ++ ++/******************************************************************************************************************* ++ * DrvJpeGetCaps ++ * Start JPE to encode one frame into a JPEG ++ * ++ * Parameters: ++ * jpeHandle: device handle ++ * pCaps: JPE capabilities ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++JPE_IOC_RET_STATUS_e DrvJpeGetCaps(JpeHandle_t *jpeHandle, JpeCaps_t *pCaps) ++{ ++ ++ if(pCaps == 0) return JPE_IOC_RET_BAD_NULLPTR; ++ ++ pCaps->nBufferModeSupport = HalJpeGetBufferModeSupportInfo(); ++ pCaps->nCodecSupport = HalJpeGetCodecSupportInfo(); ++ pCaps->nOutBufSLogAddrAlign = HalJpeGetOutBufSLogAddrAlignInfo(); ++ pCaps->nRefCLogAddrAlign[0] = HalJpeGetRefCLogAddrAlignInfo(0); ++ pCaps->nRefCLogAddrAlign[1] = HalJpeGetRefCLogAddrAlignInfo(1); ++ pCaps->nRefYLogAddrAlign[0] = HalJpeGetRefYLogAddrAlignInfo(0); ++ pCaps->nRefYLogAddrAlign[1] = HalJpeGetRefYLogAddrAlignInfo(1); ++ pCaps->nSclHandShakeSupport = HalJpeGetSclHandShakeSupportInfo(); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ +diff --git a/drivers/mstar/jpe/hal/jpe/inc/_hal_jpe_platform.h b/drivers/mstar/jpe/hal/jpe/inc/_hal_jpe_platform.h +new file mode 100644 +index 00000000..63cbefc2 +--- /dev/null ++++ b/drivers/mstar/jpe/hal/jpe/inc/_hal_jpe_platform.h +@@ -0,0 +1,12 @@ ++#ifndef _HAL_JPE_PLATFORM_H_ ++#define _HAL_JPE_PLATFORM_H_ ++ ++#if defined(_FPGA_) || defined(_UDMA_) || defined(_HIF_) ++//#define REG_BANK_JPD 0x1100 ++#define REG_BANK_JPE 0x1000 ++#endif ++//#define JPE_BASE_ADDRESS 0x74001A00 ++#define MIU_BYTES_UNIT 4 ++ ++#endif ++ +diff --git a/drivers/mstar/jpe/hal/jpe/inc/_hal_jpe_reg.h b/drivers/mstar/jpe/hal/jpe/inc/_hal_jpe_reg.h +new file mode 100644 +index 00000000..304fd817 +--- /dev/null ++++ b/drivers/mstar/jpe/hal/jpe/inc/_hal_jpe_reg.h +@@ -0,0 +1,854 @@ ++#ifndef _JPE_REG_H_ ++#define _JPE_REG_H_ ++ ++#ifndef WIN32 ++//#include "comype.h" ++//#include "kernel.h" ++#endif ++#define ADD_JPDE_0_1 //support HW multi-obuf mode ++#define ADD_JPDE_1_1 //support Jpeg YUV420 encode mode ++#define JPE_MIAW 27//25//24 ++#define ADDR_HI_BITS ((JPE_MIAW-6)-16) ++#define OUTBUF_HI_BITS (JPE_MIAW-16) ++#define ADDR_MASK (0xffffffff>>(32-(JPE_MIAW-6))) ++#define DMA_BOUND 27 ++#define DMA_HI_BITS (DMA_BOUND-16) ++#define LAST_FRAME_AVGQP_HI_BITS (24-16) ++#define BITCOUNT_HI_BITS (23-16) ++ ++ ++typedef struct ++{ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGFrameStartSw:1; // frame start (1T clk_mfe) (write one clear) ++ u16 nRegJpeGSoftRstz:1; // software reset; 0/1: reset/not reset ++ u16 nRegJpeGEncMode:1; // 0/1: JPEG/H263 ++#if defined(ADD_JPDE_1_1) ++ u16 nRegJpeGEncFormat:1; // 0/1: YUV420/YUV422 ++ u16 nRegJpeGFrameIdx:2; ++ u16 nReg0000Dummy:2; ++#else ++ u16 nReg0000Dummy:5; ++#endif ++ u16 nRegJpeGQscale:5; // frame level qscale: [H263]: 1 ~ 31 ++ u16 nRegJpeGMreq:1; // mreq_jpe; miu clock gating enable ++ u16 nRegJpeGDctOnlyEn:1; // 0: normal function, 1: DCT only to accelerate SW encoding ++ u16 nRegJpeGMode:1; //0/1: JPE/JPD ++ } tReg00; ++ u16 nReg00; ++ } uReg00; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGPicWidth:12; // picture width ++ } tReg01; ++ u16 nReg01; ++ } uReg01; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGPicHeight:12; // picture height ++ }tReg02; ++ u16 nReg02; ++ } uReg02; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegMfeGErModeDummy:2; ++ u16 nRegMfeGErMbyDummy:2; ++ u16 nRegMfeGPackedModeDummy:1; ++ u16 nRegMfeGQmodeDummy:1; ++ u16 nRegJpeGTbcMode:1; // table mode; 0: SW control, 1: HW control ++ u16 nRegMfeGFldpicEnDummy:1; ++ } tReg03; ++ u16 nReg03; ++ } uReg03; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr0Low:16; ++ } tReg06; ++ u16 nReg06; ++ } uReg06; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr0High:ADDR_HI_BITS; // Y buffer base address0 ++ } tReg07; ++ u16 nReg07; ++ } uReg07; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr1Low:16; // Y buffer base address1 ++ } tReg08; ++ u16 nReg08; ++ } uReg08; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr1High:ADDR_HI_BITS; // Y buffer base address1 ++ }tReg09; ++ u16 nReg09; ++ } uReg09; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr0Low:16; // C buffer base address0 ++ }tReg0a; ++ u16 nReg0a; ++ } uReg0a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr0High:ADDR_HI_BITS; // C buffer base address0 ++ }tReg0b; ++ u16 nReg0b; ++ } uReg0b; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr1Low:16; // C buffer base address1 ++ }tReg0c; ++ u16 nReg0c; ++ } uReg0c; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr1High:ADDR_HI_BITS; // C buffer base address1 ++ }tReg0d; ++ u16 nReg0d; ++ } uReg0d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGFsvsWptr:8; //fsvs to jpe write pointer ++ }tReg0f; ++ u16 nReg0f; ++ } uReg0f; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGRowDownCnt:8; //row_done counter in clk_jpe domain ++ }tReg10; ++ u16 nReg10; ++ } uReg10; ++ ++ union ++ { ++ struct ++ { // clock gating ++ //[0]: clock gating: clk_jpe (used by JPE); 0: clk_jpe enable, 1: clk_jpe disable ++ //[1]: clock gating: clk_jpd (used by JPD); 0: clk_jpd enable, 1: clk_jpd disable ++ //[2]: clock gating: clk_miu0 (used by JPE); 0: clk_miu0 enable, 1: clk_miu0 disable ++ //[3]: clock gating: clk_miu1 (used by JPD); 0: clk_miu1 enable, 1: clk_miu1 disable ++ //[4]: clock gating: clk_viu (used by JPE); 0: clk_viu enable, 1: clk_viu disable" ++ u16 nRegJpeGClkGateEn:5; //0x0a : gating jpd, 0x15 : gating jpe ++ }tReg16; ++ u16 nReg16; ++ } uReg16; ++ ++ // [JPEG] ++ union ++ { ++ struct ++ { ++ u16 nRegMfeGJpeEncModeDummy:2; ++ u16 nRegJpeGJpeBuffermode:1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode ++ u16 nRegJpeSAutoRstWaitCnt:6; // the waiting count for regen_soft_rstz and regen_fs_sw generation ++ u16 nRegJpeGJpeFsvsMode:2; // JPE fsvs generation mode; 0/1/2/3: pure sw/sw+hw/hw wo auto-restart/hw with auto-restart, but fsvs function is removed... ++ u16 nReg18Dummy:4; ++ u16 nRegJpeGViuSoftRstz:1; //viu software reset; 0/1: reset/not reset ++ }tReg18; ++ u16 nReg18; ++ } uReg18; ++ ++ ++ // [IRQ & important IP status checkings] ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqMask:8; // 0/1: irq not-mask/mask ++ }tReg1c; ++ u16 nReg1c; ++ } uReg1c; ++ ++ union ++ { ++ struct ++ { ++ #if 0 ++ u16 nRegJpeGIrqClr0:1; // 0/1: not clear interrupt/clear interrupt 0 (write one clear) ++ u16 nRegJpeGIrqClr1:1; // 0/1: not clear interrupt/clear interrupt 1 (write one clear) ++ u16 nRegJpeGIrqClr2:1; // 0/1: not clear interrupt/clear interrupt 2 (write one clear) ++ u16 nRegJpeGIrqClr3:1; // 0/1: not clear interrupt/clear interrupt 3 (write one clear) ++ u16 nRegJpeGIrqClr4:1; // 0/1: not clear interrupt/clear interrupt 4 (write one clear) ++ u16 nRegJpeGIrqClr5:1; // 0/1: not clear interrupt/clear interrupt 5 (write one clear) ++ u16 nRegJpeGIrqClr6:1; // 0/1: not clear interrupt/clear interrupt 6 (write one clear) ++ u16 nRegJpeGIrqClr7:1; // 0/1: not clear interrupt/clear interrupt 7 (write one clear) ++ u16 nRegJpeGIrqClr8:1; // 0/1: not clear interrupt/clear interrupt 8 (write one clear) ++ #else ++ u16 nRegJpeGIrqClr:9; // bitwise 0/1: not clear interrupt/clear interrupt 8 (write one clear) ++ #endif ++ u16 nRegJpeGSwrstSafe:1; // to indicate there're no miu activities that need to pay attention to ++ u16 nRegJpeGLastDoneZ:1; // to indicate all miu data has been written ++ }tReg1d; ++ u16 nReg1d; ++ } uReg1d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqCpu:8; // status of interrupt on CPU side ({1'b0, netrigger, fs_fail_irq, txipime_out, bspobuf_full_irq, img_buf_full_irq, marb_bspobuf_ful, frame_done_irq}) ++ }tReg1e; ++ u16 nReg1e; ++ } uReg1e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqIp:8; // status of interrupt on IP side ({1'b0, netrigger, fs_fail_irq, txipime_out, bspobuf_full_irq, img_buf_full_irq, marb_bspobuf_ful, frame_done_irq}) ++ }tReg1f; ++ u16 nReg1f; ++ } uReg1f; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqForce:8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt ++ }tReg20; ++ u16 nReg20; ++ } uReg20; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGSramSdEn:3; //SRAM SD enable ++ }tReg21; ++ u16 nReg21; ++ } uReg21; ++ ++ // [TXIP PIPELINE ] ++ // QUAN ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSQuanIdxLast:6; //the index of the last non-zero coefficient in the zig-zag order ++ u16 nRegJpeSQuanIdxSwlast:1; //software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable ++ }tReg2c; ++ u16 nReg2c; ++ } uReg2c; ++ ++ // TXIP control & debug ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipMbx:9; //txip mbx ++ u16 nRegJpeSTxipSngMb:1; //0/1: disable/enable txip controller stop-and-go mechanism using (txip_mbx == reg_mfe_g_debugrig_mbx) & (txip_mby == reg_mfe_g_debugrig_mby) ++ u16 nRegJpeSTxipSngSet:1; //txip controller stop-and-go mechanism using this register bit: 0/1: go/stop ++ u16 nRegJpeSTxipDbfFullHaltEn:1; //txip controller stop-and-go mechanism using double buffer fullness as criterion; 0/1: disable/enable ++ }tReg2d; ++ u16 nReg2d; ++ } uReg2d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipMby:9; // txip mby ++ }tReg2e; ++ u16 nReg2e; ++ } uReg2e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegMfeSTxipIrfshMbE1Dummy:11; ++ u16 nRegJpeSTxipTimeoutEn:1; // txip time out enable ++ u16 nRegJpeSTxipWaitMode:1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count ++ }tReg32; ++ u16 nReg32; ++ } uReg32; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipIdlecnt:16; //wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) ++ }tReg33; ++ u16 nReg33; ++ } uReg33; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipTimeout:16; // txip timeout count (x 64T) ++ }tReg34; ++ u16 nReg34; ++ }uReg34; ++ ++ // [ECDB PIPELINE] ++ // ECDB control & debug ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSEcdbMbx:9; // ecdb mbx ++ }tReg35; ++ u16 nReg35; ++ }uReg35; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSEcdbMby:9; // ecdb mby ++ }tReg36; ++ u16 nReg36; ++ }uReg36; ++ ++ // BSP/BSPOBUF ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufSetAdr:1; // set bsp obuf start address(write one clear) ++ u16 nRegJpeSBspFdcOffset:5; // bsp's fdc offset ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeObuffullIrqAtFrameEnd:1; // [JPDE_0_1] keep obuf full irq at frame end ++ u16 nRegJpeObufToggleObuf0Status:1; // [JPDE_0_1] toggle buf0 status(write one clear) ++ u16 nRegJpeObufToggleObuf1Status:1; // [JPDE_0_1] toggle buf1 status(write one clear) ++ u16 nRegJpeObufHwEn:1; // [JPDE_0_1] enable HW obuf automatic mechanism ++ u16 nRegJpeObufUpdateAdr:1; // [JPDE_0_1] update obuf address(write one clear) ++ u16 nRegJpeObufAdrRchkSe1:2; // [JPDE_0_1] obuf adr read back check selection: 0/1/2/3: s0/e0/s1/e1 ++ u16 nRegJpeObufAdrRchkEn:1; // [JPDE_0_1] enable bspobuf adr read back check through reg_jpe_s_bspobuf_wptr ++#endif ++ }tReg3b; ++ u16 nReg3b; ++ }uReg3b; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeSBspobufAdrLow:16; // bsp obuf start address (4 byte unit) ++#else ++ u16 nRegJpeSBspobufSadrLow:16; // bsp obuf start address (4 byte unit) ++#endif ++ }tReg3c; ++ u16 nReg3c; ++ }uReg3c; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeSBspobufAdrHigh:OUTBUF_HI_BITS; // bsp obuf start address (4 byte unit) ++ u16 nRegJpeSBspobufDummyBit:(16-OUTBUF_HI_BITS-2); ++ u16 nRegJpeSBspobufId:2; ++#else ++ u16 nRegJpeSBspobufSadrHigh:OUTBUF_HI_BITS; // bsp obuf start address (4 byte unit) ++#endif ++ }tReg3d; ++ u16 nReg3d; ++ }uReg3d; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeSBspspobufWriteIdAdr:1; // [JPDE_0_1] write to this address to enable writing of bspobuf address ++#else ++ u16 nRegJpeSBspobufEadrLow:16; // bsp obuf end address (4 byte unit) ++#endif ++ }tReg3e; ++ u16 nReg3e; ++ }uReg3e; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nReg3fReserved; ++#else ++ u16 nRegJpeSBspobufEadrHigh:OUTBUF_HI_BITS; // bsp obuf end address (4 byte unit) ++#endif ++ }tReg3f; ++ u16 nReg3f; ++ }uReg3f; ++ ++ union ++ { ++ struct ++ { ++ ++ u16 nRegJpeSBspByteIdx:2; // last encoded byte index in 4-byte MIU ++#ifdef ADD_JPDE_0_1 ++#if 0 // Old one and not the same as spec ++ u16 nRegJpeObufIdx:2; // HW obuf index(0->1->2->3->0->1¡K) ++ // SW obuf index(00->01->11->10->00...) ++ u16 nRegJpeObuf0Status:1; ++ u16 nRegJpeObuf1Status:1; ++ // reg_jpe_s_obuf_adr_status:6 {fifo_not_full, fifo_not_empty, enable_obufadr_update, obufadr_update_cnt[2:0]} ++ u16 nRegJpeObufAdrUpdateCnt:3; ++ u16 nRegJpeEnableObufAdrUpdate:1; ++ u16 nRegJpeFifoNotEmpty:1; ++ u16 nRegJpeFifoNotFull:1; ++#else ++ u16 nRegJpeSObufIdx:2; // HW obuf index(0->1->2->3->0->1¡K) ++ u16 nRegJpeSObufSwIdx:2; // SW obuf index(00->01->11->10->00...) ++ u16 RegJpeSObufAdrStatus:6; // {fifo_not_full, fifo_not_empty, enable_obufadr_update, obufadr_update_cnt[2:0]} ++#endif ++#endif ++ }tReg42; ++ u16 nReg42; ++ }uReg42; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufWptrLow:16; // bspobuf write pointer (4 byte unit) ++ }tReg44; ++ u16 nReg44; ++ }uReg44; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufWptrHigh:OUTBUF_HI_BITS; // bspobuf write pointer (4 byte unit) ++ }tReg45; ++ u16 nReg45; ++ }uReg45; ++ ++ // [Table Control] ++ union ++ { ++ struct ++ { ++ u16 nRegMfeSFdcAckDummy:1; ++ u16 nRegMfeSFdcDoneClrDummy:1; ++ u16 nRegMfeSFdcDoneDummy:1; ++ u16 nReg48Dummy:8; ++ u16 nRegMfeSFdcBsVldDummy:1; ++ u16 nRegJpeSTbcEn:1; // set for table read & write ; 1: enable, 0: disable (write one clear) ++ }tReg48; ++ u16 nReg48; ++ }uReg48; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTbcRw:1; // table mode; 0: read, 1: write ++ u16 nRegJpeSTbcDoneClr:1; // table done clear (write one clear) ++ u16 nRegJpeSTbcDone:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg_mfe_sbc_rdata ++ u16 nReg49Dummy:5; ++ u16 nRegJpeSTbcAdr:8; // table address ++ ++ }tReg49; ++ u16 nReg49; ++ }uReg49; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTbcWdata:8; // table write data ++ }tReg4a; ++ u16 nReg4a; ++ }uReg4a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTbcRdata:8; // table read data ++ }tReg4b; ++ u16 nReg4b; ++ }uReg4b; ++ ++ // [Miu Arbiter] ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrBurstThd:5; //miu read burst bunch up threshold ++ u16 nRegJpeSDmaMrTimeout:3; //miu read burst timeout ++ u16 nRegJpeSDmaMwBurstThd:5; //miu write burst bunch up threshold ++ u16 nRegJpeSDmaMwTimeout:3; //miu write burst timeout ++ }tReg54; ++ u16 nReg54; ++ }uReg54; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrpriorityThd:7; //hardware mfe2mi_rpriority threshold ++ u16 nRegJpeSDmaMrpriorityType:1; //hardware mfe2mi_rpriority threshold ++ u16 nRegJpeSDmaMwpriorityThd:7; //hardware mfe2mi_wpriority threshold ++ u16 nRegJpeSDmaMwpriorityType:1; ++ }tReg55; ++ u16 nReg55; ++ }uReg55; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_jpe_s_dma_mrpriority_sw:2; //mfe2mi_rpriority software programmable ++ u16 reg5600_dummy:1; ++ u16 reg_jpe_s_dma_mr_nwait_mw:1; //miu read not wait mi2mfe_wrdy ++ u16 reg_jpe_s_dma_mwpriority_sw:2; //mfe2mi_wpriority software programmable ++ u16 reg5601_dummy:1; ++ u16 reg_jpe_s_dma_mw_nwait_mr:1; //miu read not wait mi2mfe_wrdy ++ u16 reg_jpe_s_dma_mr_pending:4; //miu read not wait mi2mfe_wrdy ++ u16 reg_jpe_s_dma_32b_ad_nswap:1; //32bits miu address not swap. only for 32bits mode ++ u16 reg_jpe_s_dma_miu_wmode:1; //0/1: original miu protocol/new miu protocol(wd_en) ++ }tReg56; ++ u16 nReg56; ++ }uReg56; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrlastThd:5; //auto mfe2mi_rlast threshold ++ u16 nRegJpeSDmaMwlastThd:5; //auto mfe2mi_wlast threshold ++ u16 nReg5700Dummy:2; ++ u16 nRegJpeSDmaBurstSplit:4; //0: disable; N: MIU Request IDLE ¡§N¡¨ cycles with every last signal ++ }tReg57; ++ u16 nReg57; ++ }uReg57; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaUbound0Low:16; //miu write protection, miu upper bound 0 (BSP obuf) ++ }tReg58; ++ u16 nReg58; ++ }uReg58; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaUbound0High:DMA_HI_BITS; //miu write protection, miu upper bound 0 (BSP obuf) ++ }tReg59; ++ u16 nReg59; ++ }uReg59; ++ ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaLbound0Low:16; // miu write protection, miu lower bound 0 ++ }tReg5a; ++ u16 nReg5a; ++ }uReg5a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaLbound0High:DMA_HI_BITS; // miu write protection, miu lower bound 0 ++ u16 nReg5bDummy:((16-DMA_HI_BITS)-2); // miu write protection, miu lower bound 0 ++ u16 nRegJpeSDmaMiuOff:1; //miu write protection, miu off ++ u16 nRegJpeSDmaMiuBoundErr:1; ++ }tReg5b; ++ u16 nReg5b; ++ }uReg5b; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrRdffPriorThd:4; // 4¡¦hx: high priority when rdff depth < {xxx,2¡¦b00} ++ u16 nRegJpeSDmaMrRdffPriorMask:4; //Read data fifo depth priority initial mask, 0:disable, 1:release the mask after 8 requests ++ u16 nRegJpeSDmaMlastStallOld:1; //jpde2mi Last in stall state 0:Guarantee jpde2mi Last, 1:No jpde2mi Last in Stall State ++ u16 nRegJpeSDmaRsv5c:7; //reserved registers ++ }tReg5c; ++ u16 nReg5c; ++ }uReg5c; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMreqAlwaysActive:1; //0:dynamic mreq, 1:always set mreq = 1 ++ u16 nRegJpeSDmaMreqModeSel:1; //mreq mode selection 0:clk_miu enabled dynamically, 1:clk_miu enabled from Enstart -> Frame_done ++ u16 nRegJpeSDmaMiuBoundEn:4; //miu write protection, miu bound enable for write port 0 ~ 3 ++ }tReg5d; ++ u16 nReg5d; ++ }uReg5d; ++ ++ union { ++ struct { ++ u16 nRegGJpeYPitch:8; // Y frame buffer pitch ++ u16 nRegGJpeCPitch:8; // C frame buffer pitch ++ }tReg5e; ++ u16 nReg5e; ++ }uReg5e; ++ ++ union { ++ struct { ++ u16 nRegSJpeYuvldrRlastThd:4; // YUV loader MIU burst read interval ++ u16 nRegSJpeYuvldrMrprioritySw:2; // YUV loader MIU read priority SW programmable ++ u16 nRegSJpeYuvldrMrpriorityThd:7; // YUV loader MIU read priority setting threshold ++ u16 nRegSJpeYuvldrMrpriorityType:1; // YUV loader MIU read priority type ++ u16 nRegSJpeYuvldrImiEn:1; // YUV loader IMI enable ++ u16 nRegSJpeYuvldrCWwap:1; // YUV loader Chroma swap ++ }tReg5f; ++ u16 nReg5f; ++ }uReg5f; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufWlastThd:4; // BSP obuf MIU burst write interval ++ u16 nRegJpeSBspobufMwpriorityWw:2; // BSP obuf MIU write priority SW programmable ++ u16 nRegJpeSBspobufMwpriorityThd:7; // BSP obuf MIU write priority setting threshold ++ u16 nRegJpeSBspobufMwpriorityType:1; // BSP obuf MIU write priority type ++ }tReg60; ++ u16 nReg60; ++ }uReg60; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSYuvldrImiBound:9; // YUV loader IMI bound (unit: Macro) ++ }tReg61; ++ u16 nReg61; ++ }uReg61; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeTlb:1; // YUV loader IMI bound (unit: Macro) ++ }tReg64; ++ u16 nReg64; ++ }uReg64; ++ ++ // [Debug] ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGPatGenInit:16; // pattern generation initial value ++ }tReg6f; ++ u16 nReg6f; ++ }uReg6f; ++ ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugMode:5; // debug mode ++ u16 nRegJpeGPatGenEn:1; //enable pattern generation ++ u16 nRegJpeGDebugTrigCycle:10; // wait (8 * reg_mfe_g_debugrig_cycle) cycles ++ ++ }tReg70; ++ u16 nReg70; ++ }uReg70; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugTrigMbx:9; // debug trigger mbx ++ }tReg71; ++ u16 nReg71; ++ }uReg71; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugTrigMby:9; // debug trigger mby ++ }tReg72; ++ u16 nReg72; ++ }uReg72; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugTrig:1; // reg trigger (write one clear) ++ u16 nRegJpeGDebugTrigMode:2; // debug trigger mode; 0/1/2/3: regrigger/3rd stage (mbx, mby)/frame start ++ u16 nRegJpeGDebugEn:1; // debug enable ++ u16 nRegJpeGCrcMode:4; //'h0: Disable,¡¥hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf ++ u16 nRegJpeGDebugTcycleChkEn:1; //enable total cycle check ++ u16 nRegJpeGDebugTcycleChkSel:1; //select total cycle and report it on reg_mfe_g_crc_result[15:0] ++ u16 nRegJpeGRowDownIrqEn: 1; //row done irq enable; 0: disable, 1: enable ++ u16 nRegJpeGVsIrqEn: 1; //vs irq enable; 0: disable, 1: enable ++ }tReg73; ++ u16 nReg73; ++ }uReg73; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugState0:16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, ++ }tReg74; ++ u16 nReg74; ++ }uReg74; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGSwBufferMode:1; //0/1: hw/sw buffer mode, but not work anymore... ++ u16 nRegJpeGSwRowDone:1; //sw row done (1T clk_jpe) (write one clear) ++ u16 nRegJpeGSwVsync:1; //sw vsync (1T clk_jpe) (write one clear), but not work anymore... ++ }tReg75; ++ u16 nReg75; ++ }uReg75; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult0:16; // CRC64[15..0] ++ }tReg76; ++ u16 nReg76; ++ }uReg76; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult1:16; // CRC64[31..16] ++ }tReg77; ++ u16 nReg77; ++ }uReg77; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult2:16; // CRC64[47..32] ++ }tReg78; ++ u16 nReg78; ++ }uReg78; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult3:16; // CRC64[63..48] ++ }tReg79; ++ u16 nReg79; ++ }uReg79; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBistFail0:16; ++ }tReg7a; ++ u16 nReg7a; ++ }uReg7a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugOutLow:16; ++ }tReg7b; ++ u16 nReg7b; ++ }uReg7b; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugOutHigh:(21-16); ++ }tReg7c; ++ u16 nReg7c; ++ }uReg7c; ++ ++ //Reserved ++ union ++ { ++ struct ++ { ++ u16 nRegJpeRsv0:16; //reserved registers ++ }tReg7d; ++ u16 nReg7d; ++ }uReg7d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeRsv1:16; //reserved registers ++ }tReg7e; ++ u16 nReg7e; ++ }uReg7e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeRsv2:16; //reserved registers ++ }tReg7f; ++ u16 nReg7f; ++ }uReg7f; ++ ++} JpeReg_t, *pJpeReg_t; ++ ++ ++ ++#endif ++ +diff --git a/drivers/mstar/jpe/hal/jpe/inc/hal_jpe.h b/drivers/mstar/jpe/hal/jpe/inc/hal_jpe.h +new file mode 100644 +index 00000000..76a19e00 +--- /dev/null ++++ b/drivers/mstar/jpe/hal/jpe/inc/hal_jpe.h +@@ -0,0 +1,205 @@ ++#ifndef _Jpe_HAL_H_ ++#define _Jpe_HAL_H_ ++ ++//#include "vm_types.ht" ++//#include ++#include ++#include ++#include "_hal_jpe_platform.h" ++#include "hal_ext_int_pub.h" ++#include "_hal_jpe_reg.h" ++ ++#if defined(_FPGA_) || defined(_UDMA_) || defined(_HIF_) ++#include "fpgaapi.h" ++#endif ++ ++//typedef int bool; ++//typedef unsigned short U16; ++ ++#define JPE_HAL_ALLOC_MEM_FAIL 0 ++#define JPE_HAL_ALLOC_MEM_SUCCESS 1 ++ ++typedef enum ++{ ++ JPE_HAL_QLEVEL_1 = 0, ++ JPE_HAL_QLEVEL_2, ++ JPE_HAL_QLEVEL_3, ++ JPE_HAL_QLEVEL_4, ++ JPE_HAL_QLEVEL_5, ++ JPE_HAL_QLEVEL_6, ++}JpeHalQLevel_e; ++ ++typedef enum ++{ ++ JPE_HAL_IRQ_FRAME_DONE = 0x00000001, // bit 0, jpe_framedone ++ JPE_HAL_IRQ_BSPOBUF0_FULL = 0x00000002, // bit 1, jpe_bspobuf0_full, SW mode: buf full; HW mode: buf0 full ++ JPE_HAL_IRQ_IMGBUF_FULL = 0x00000004, // bit 2, img_buf_full_irq ++ JPE_HAL_IRQ_BSPOBUF1_FULL = 0x00000008, // bit 3, jpe_bspobuf1_full, SW mode: not used; HW mode: buf1 full ++ JPE_HAL_IRQ_FS_FAIL = 0x00000020, // bit 5, fs_fail_irq ++ JPE_HAL_IRQ_LESS_ROW_DONE = 0x00000080, // bit 7, less_row_down_irq ++ JPE_HAL_IRQ_IMI_OVERFLOW = 0x00000100, // bit 8, jpe2scl_imi_overflow_int ++ JPE_HAL_IRQ_TXIP_TIMEOUT = 0x10000000, // bit 4 when reg_jpe_g_vs_irq_en = 0, txip_time_out_irq ++ JPE_HAL_IRQ_VS = 0x20000000, // bit 4 when reg_jpe_g_vs_irq_en = 1, vs ++ JPE_HAL_IRQ_NET_TRIGGER = 0x40000000, // bit 4 when reg_jpe_g_row_down_irq_en = 0, net_trigger ++ JPE_HAL_IRQ_VIU_ROW_DONE = 0x80000000, // bit 6 when reg_jpe_g_row_down_irq_en = 1, viu2jpe_row_done_jpe ++ JPE_HAL_IRQ_ALL = 0xF00001AF // ALL bits ++}JpeHalIrqEvent_e; ++ ++typedef enum ++{ ++ JPE_OBUF_0=0, ++ JPE_OBUF_1=1, ++} JpeHalOBufOdr_e; ++ ++typedef enum ++{ ++ JPE_FSVS_SW_MODE=0, ++ JPE_FSVS_SW_HW_MODE, ++ JPE_FSVS_HW_MODE, ++ JPE_FSVS_HW_WO_RESTART_MODE, ++ JPE_FSVS_HW_WI_RESTART_MODE, ++ JPE_FSVS_INVALID, ++} JpeFsVsGenerationMode_e; ++ ++typedef enum ++{ ++ JPE_HAL_OBUF_SINGLE_MODE = 0x0, ++ JPE_HAL_OBUF_MULTI_MODE = 0x1 ++} JpeHalOutBufMode_e; ++ ++typedef enum ++{ ++ JPE_HAL_BUFFER_ROW_MODE = 0x0, ++ JPE_HAL_BUFFER_FRAME_MODE = 0x1 ++} JpeHalInBufMode_e; ++ ++typedef enum ++{ ++ JPE_HAL_CODEC_JPEG = 0x1, ++ JPE_HAL_CODEC_H263I = 0x2, ++ JPE_HAL_CODEC_ENCODE_DCT = 0x4, ++} JpeHalCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_HAL_SCL_HANDSHAKE_OFF = 0, ++ JPE_HAL_SCL_HANDSHAKE_ON ++} JpeHalSclHandShake_e; ++ ++typedef enum ++{ ++ JPE_HAL_RAW_YUYV = 0x0, ++ JPE_HAL_RAW_YVYU = 0x1, ++ JPE_HAL_RAW_NV12 = 0x3, ++ JPE_HAL_RAW_NV21 = 0x4, ++} JpeHalRawFormat_e; ++ ++typedef struct ++{ ++ u32 nInBufYAddr[2]; ++ u32 nInBufCAddr[2]; ++} JpeHalInBufCfg_t, *pJpeHalInBufCfg; ++ ++ ++typedef struct ++{ ++ u32 nOutBufAddr[2]; ++ u32 nOutBufSize[2]; ++ u32 nJpeOutBitOffset; ++} JpeHalOutBufCfg_t, *pJpeHalOutBufCfg; ++ ++typedef struct ++{ ++ u32 nBaseAddr; ++ u32 nSize; ++ JpeReg_t* pJpeReg; ++} JpeHalHandle_t, *pJpeHalHandle; ++ ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// IRQ API // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++void HalJpeSetIrqMask(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask); ++void HalJpeClearIrq(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask); ++JpeHalIrqEvent_e HalJpeGetIrqCheck(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask); ++u16 HalJpeGetIrq(JpeHalHandle_t* handle); ++//JpeHalIrqEvent_e HalJpeGetIrqEvent(u16 u16IrqReg, JpeHalIrqEvent_e IrqEventMask); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Quantization Tables Setting // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++int HalJpeSetQTable(JpeHalHandle_t* handle,const u16 *q_table_y, const u16 *q_table_c, u32 size); ++int HalJpeReadQTable(JpeHalHandle_t* handle,u16 *q_table_y, u16 *q_table_c, u32 *size); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Configurations // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++void HalJpeSetJpeMode(JpeHalHandle_t* handle,u32 bUseJPE); ++void HalJpeSetCodecFormat(JpeHalHandle_t* handle,JpeHalCodecFormat_e format); ++void HalJpeSetRawFormat(JpeHalHandle_t* handle,JpeHalRawFormat_e format); ++void HalJpeSetPicDim(JpeHalHandle_t* handle,u32 width, u32 height); ++void HalJpeToggleOutBuf(JpeHalHandle_t* handle,u32 nObufIdx); ++void HalJpeSetInputMode(JpeHalHandle_t* handle,JpeHalInBufMode_e mode); ++void HalJpeSetOutputMode(JpeHalHandle_t* handle,JpeHalOutBufMode_e mode); ++void HalJpeSetInBuf(JpeHalHandle_t* handle,pJpeHalInBufCfg ptInBufCfg); ++void HalJpeSetOutBuf(JpeHalHandle_t* handle,pJpeHalOutBufCfg ptOutBufCfg); ++void HalJpeSetDctMbAddr(JpeHalHandle_t* handle,u32 PhyAddr); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Controls // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++void HalJpeSoftReset(JpeHalHandle_t *handle); ++void HalJpeSetEnable(JpeHalHandle_t *handle); ++void HalJpeHwRowCounterReset(JpeHalHandle_t *handle); ++void HalJpeSetSWRowDown(JpeHalHandle_t *handle); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Status // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++bool HalJpeResetSafe(JpeHalHandle_t *handle); ++u32 HalJpeGetOutputByteSize(JpeHalHandle_t *handle,u32 nObufSel); ++u16 HalJpeGetRowDownCnt(JpeHalHandle_t *handle); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// TXIP? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++void HalJpeStop(JpeHalHandle_t *handle,bool opt); ++u16 HalJpeGetRowCount(JpeHalHandle_t *handle); ++void HalJpeIdleCount(JpeHalHandle_t *handle,u16 nIdleCount); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Debugs? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++void HalJpeSetCycleReport(JpeHalHandle_t *handle,u16 mode); ++void HalJpeSetCrc(JpeHalHandle_t *handle,u16 mode); ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Capabilities? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++u8 HalJpeGetBufferModeSupportInfo(void); ++u8 HalJpeGetSclHandShakeSupportInfo(void); ++u8 HalJpeGetCodecSupportInfo(void); ++u32 HalJpeGetOutBufSLogAddrAlignInfo(void); ++u32 HalJpeGetOutBufELogAddrAlignInfo(void); ++u32 HalJpeGetRefYLogAddrAlignInfo(u8 bufID); ++u32 HalJpeGetRefCLogAddrAlignInfo(u8 bufID); ++ ++#endif ++ +diff --git a/drivers/mstar/jpe/hal/jpe/inc/hal_jpe_ms_dprintf.h b/drivers/mstar/jpe/hal/jpe/inc/hal_jpe_ms_dprintf.h +new file mode 100644 +index 00000000..64e5938f +--- /dev/null ++++ b/drivers/mstar/jpe/hal/jpe/inc/hal_jpe_ms_dprintf.h +@@ -0,0 +1,74 @@ ++#ifndef DRV_JPE_MS_DPRINTF_H ++#define DRV_JPE_MS_DPRINTF_H ++ ++#if !defined(DEBUG_LEVEL) ++#define DEBUG_LEVEL 0 ++#endif ++ ++////////////////////////////////////// Define for Microsoft platform /////////////////////////////// ++#if defined(_MSC_VER) ++#include ++#include ++//#include ++ ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if (level > DEBUG_LEVEL) ++ return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++#ifdef WINCE ++ fprintf(stderr, "%s", msg); ++#else ++ OutputDebugStringA(msg); ++#endif ++ va_end(ap); ++} ++ ++ ++////////////////////////////////////// Define for MISP platform /////////////////////////////// ++#elif defined(MIPSDEV) ++#include ++ ++#define ms_dprintf(level, fmt, arg...) \ ++ do { \ ++ if (level <= DEBUG_LEVEL) diag_printf(fmt, ##arg); \ ++ } while (0) ++ ++ ++////////////////////////////////////// Define for ?? platform /////////////////////////////// ++#elif defined(__I_SW__) ++#include ++#include ++#include "sys_sys_isw_uart.h" // send_trace ++static __inline void ms_dprintf(int level, const char *fmt, ...) ++{ ++ va_list ap; ++ char msg[2048]; ++ ++ if (level > DEBUG_LEVEL) ++ return; ++ ++ va_start(ap, fmt); ++ vsprintf(msg, fmt, ap); ++ send_msg(msg); ++ va_end(ap); ++} ++ ++ ++////////////////////////////////////// Define for Linux pletform /////////////////////////////// ++#elif defined(__linux__) ++#include "mdrv_jpe.h" ++#define ms_dprintf JPE_MSG ++ ++ ++////////////////////////////////////// Define for ??? /////////////////////////////// ++#else ++#define ms_dprintf(level, fmt, arg...) ++#endif /* _MSC_VER */ ++ ++#endif /* MS_DPRINTF_H */ +diff --git a/drivers/mstar/jpe/hal/jpe/pub/hal_ext_int_pub.h b/drivers/mstar/jpe/hal/jpe/pub/hal_ext_int_pub.h +new file mode 100644 +index 00000000..84b040a5 +--- /dev/null ++++ b/drivers/mstar/jpe/hal/jpe/pub/hal_ext_int_pub.h +@@ -0,0 +1,190 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (¡§MStar Confidential Information¡¨) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/** ++* @file hal_ext_int-pub.h ++* @version ++* @brief External interrupt controller header file ++* ++*/ ++ ++#ifndef __HAL_EXT_INT_PUB_H__ ++#define __HAL_EXT_INT_PUB_H__ ++ ++/*=============================================================*/ ++// Include files ++/*=============================================================*/ ++//#include "vm_types.ht" ++#include ++#include ++ ++/*=============================================================*/ ++// Extern definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Macro definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Data type definition ++/*=============================================================*/ ++typedef enum ++{ ++ EXT_INT_NUM_0=0, ++ EXT_INT_NUM_1, ++ EXT_INT_NUM_2, ++ EXT_INT_NUM_3, ++ EXT_INT_NUM_4, ++ EXT_INT_NUM_5, ++ EXT_INT_NUM_6, ++ EXT_INT_NUM_7, ++ EXT_INT_NUM_8, ++ EXT_INT_NUM_9, ++ EXT_INT_NUM_10, ++ EXT_INT_NUM_11, ++ EXT_INT_NUM_12, ++ EXT_INT_NUM_13, ++ EXT_INT_NUM_14, ++ EXT_INT_NUM_15, ++ EXT_INT_NUM_MAX ++} ExtIntNumber_e; ++ ++/** ++ * clock division factor type for debounce ++ */ ++typedef enum ++{ ++ EXT_INT_CLK_DIV_2=0, ++ EXT_INT_CLK_DIV_4, ++ EXT_INT_CLK_DIV_8, ++ EXT_INT_CLK_DIV_16, ++ EXT_INT_CLK_DIV_32, ++ EXT_INT_CLK_DIV_64, ++ EXT_INT_CLK_DIV_128, ++ EXT_INT_CLK_DIV_256, ++ EXT_INT_CLK_DIV_MAX ++} ExtIntClkDiv_e; ++ ++/** ++ * Mapping of internal interrupt controller ++ */ ++typedef enum ++{ ++ EXT_INT_MAP_1=0, ++ EXT_INT_MAP_2, ++ EXT_INT_MAP_3, ++ EXT_INT_MAP_4, ++ EXT_INT_MAP_5, ++ EXT_INT_MAP_6, ++ EXT_INT_MAP_7, ++ EXT_INT_MAP_8, ++ EXT_INT_MAP_MAX ++} ExtIntMap_e; ++ ++/** ++ * Polarity of the interrupt line ++ */ ++typedef enum ++{ ++ EXT_INT_POLARITY_NORMAL=0, /// normal polarity (rising edge/high level) ++ EXT_INT_POLARITY_REVERSE, /// reverse polarity (falling edge/low level) ++ EXT_INT_POLARITY_MAX ++} ExtIntPolarity_e; ++ ++/** ++ * Mode type ++ */ ++typedef enum ++{ ++ EXT_INT_MODE_BYPASS=0, /// bypass mode ++ EXT_INT_MODE_SHORT_PULSE, /// short pulse mode ++ EXT_INT_MODE_DEBOUNCE, /// debounce mode ++ EXT_INT_MODE_DEBOUNCE_BOTH_EDGE, /// debounce + both edge detector mode ++ EXT_INT_MODE_MAX ++} ExtIntMode_e; ++ ++/** ++ * Ack type ++ */ ++typedef enum ++{ ++ EXT_INT_CLEAR_PRE=0, /// auto-clear before isr invocation ++ EXT_INT_CLEAR_POST, /// auto-clear after isr invocation ++ EXT_INT_CLEAR_MANUAL, /// manual clear ++ EXT_INT_CLEAR_MAX ++} ExtIntClear_e; ++ ++/** ++ * GPIO pull type ++ */ ++typedef enum ++{ ++ EXT_INT_PULL_DISABLE=0, /// disable pull functionaility ++ EXT_INT_PULL_DOWN, /// pull-down this GPIO ++ EXT_INT_PULL_UP, /// pull-up this GPIO ++ EXT_INT_PULL_DEFAULT, /// don't care ++ EXT_INT_PULL_MAX ++} ExtIntPull_e; ++ ++/** ++ * Debounce type ++ */ ++typedef enum ++{ ++ EXT_INT_DEBOUNCE_0=0, /// disable debounce functionaility ++ EXT_INT_DEBOUNCE_1, /// debounce 1 clock ++ EXT_INT_DEBOUNCE_2, /// debounce 2 clocks ++ EXT_INT_DEBOUNCE_3, /// debounce 3 clocks ++ EXT_INT_DEBOUNCE_4, /// debounce 4 clocks ++ EXT_INT_DEBOUNCE_5, /// debounce 5 clocks ++ EXT_INT_DEBOUNCE_6, /// debounce 6 clocks ++ EXT_INT_DEBOUNCE_7, /// debounce 7 clocks ++ EXT_INT_DEBOUNCE_MAX ++} ExtIntDebounce_e; ++ ++/** ++ * Interrupt Service Routine type ++ */ ++//typedef void (*PfnExtIntISR)(void); ++typedef irqreturn_t (*PfnExtIntISR)(int eIntNum, void* dev_id); ++ ++ ++/** ++ * Interrupt control parameters ++ */ ++typedef struct ++{ ++ ExtIntMap_e eMap; ++ ExtIntPolarity_e ePolarity; ++ ExtIntMode_e eMode; ++ ExtIntClear_e eClear; ++ ExtIntPull_e ePull; ++ ExtIntDebounce_e eDebounce; ++ PfnExtIntISR pfnIsr; ++} ExtIntParam_t; ++ ++/*=============================================================*/ ++// Variable definition ++/*=============================================================*/ ++ ++/*=============================================================*/ ++// Global function definition ++/*=============================================================*/ ++ ++#endif // __HAL_EXT_INT_PUB_H__ ++ +diff --git a/drivers/mstar/jpe/hal/jpe/src/hal_jpe.c b/drivers/mstar/jpe/hal/jpe/src/hal_jpe.c +new file mode 100644 +index 00000000..15205ca9 +--- /dev/null ++++ b/drivers/mstar/jpe/hal/jpe/src/hal_jpe.c +@@ -0,0 +1,1399 @@ ++//#include ++#include ++//#include ++#include "ms_platform.h" ++#include "hal_jpe.h" ++#include "_hal_jpe_reg.h" ++#include "_hal_jpe_platform.h" ++//#include "hal_drv_util.h" ++//#include "hal_miu_arb.h" ++//#include "sys_sys_arm.h" ++//#include "hal_int_ctrl.h" ++//#include "sys_MsWrapper_cus_os_int_ctrl.h" ++#define IMG_CAP_DBG_LEVEL (_CUS2 | LEVEL_5)/* Trace Filter of image capture */ ++ ++#define TRACE ++#define DEBUG_LEVEL 0 ++#include "hal_jpe_ms_dprintf.h" ++ ++//volatile JpeReg_t jpe_reg; ++#define TIME_OUT_CNT 10 ++ ++//#define IOBASE 0xFD000000 ++//#define JPEBASE 0x132000 ++//#define LPLLBASE 0x103300 ++ ++//static u16 ++//reg_ld(u32 addr) { ++// return *((volatile u16*)addr); ++//} ++ ++//static void ++//reg_st(u32 addr, u16 val) { ++// *((volatile u16*)addr) = val; ++//} ++ ++#define REGW(base,idx,val,cmt) ms_writew(val,((uint)base+(idx)*4)) ++#define REGR(base,idx,cmt) ms_readw(((uint)base+(idx)*4)) ++ ++//#if 0 ++//#define REGR(idx,cmt) reg_ld(IOBASE+((JPEBASE)*2+(idx)*4)) ++//#define REGW(idx,val,cmt) reg_st(IOBASE+((JPEBASE)*2+(idx)*4),val) ++//#define REGR_LPLL(idx,cmt) reg_ld(IOBASE+((LPLLBASE)*2+(idx)*4)) ++//#define REGW_LPLL(idx,val,cmt) reg_st(IOBASE+((LPLLBASE)*2+(idx)*4),val) ++//#else ++//#define REGR(idx,cmt) reg_ld(IOBASE+((JPEBASE)*2+(idx)*4)) ++//#define REGW(idx,val,cmt) do {reg_st(IOBASE+((JPEBASE)*2+(idx)*4),val); JPE_MSG(1, "Write %04X to reg %02X (%0X), %s", val, idx, idx*2, cmt);} while(0) ++//#define REGR_LPLL(idx,cmt) reg_ld(IOBASE+((LPLLBASE)*2+(idx)*4)) ++//#define REGW_LPLL(idx,val,cmt) do {reg_st(IOBASE+((LPLLBASE)*2+(idx)*4),val); JPE_MSG(1, "Write "cmt, val, idx);} while(0) ++//#endif ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// IRQ API // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeIrqMaskConvertEnumerate2Real ++ * Convert enumerated mask to real mask. ++ * The converter simplifies the IF of IRQ and can handle the mux of bits in the IRQ mask ++ * ++ * Parameters: ++ * mask: enumerated mask ++ * ++ * Return: ++ * Real bitwise mask ++ */ ++static u16 _HalJpeIrqMaskConvertEnumerate2Real(JpeReg_t* pJpeReg,JpeHalIrqEvent_e mask) ++{ ++ u16 real_mask = (u16)(mask & 0xFFFF); ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 0 ++ if(mask & JPE_HAL_IRQ_TXIP_TIMEOUT && !pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ real_mask |= 0x0010; ++ } ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 1 ++ if(mask & JPE_HAL_IRQ_VS && pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ real_mask |= 0x0010; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 0 ++ if(mask & JPE_HAL_IRQ_NET_TRIGGER && !pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ real_mask |= 0x0040; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 1 ++ if(mask & JPE_HAL_IRQ_VIU_ROW_DONE && pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ real_mask |= 0x0040; ++ } ++ ++ return real_mask; ++} ++ ++/******************************************************************************************************************* ++ * _HalJpeIrqMaskConvertReal2Enumerate ++ * Convert real mask to enumated mask. ++ * The converter simplifies the IF of IRQ and can handle the mux of bits in the IRQ mask ++ * ++ * Parameters: ++ * mask: real bitwise mask ++ * ++ * Return: ++ * Enumerated IRQ ++ */ ++static JpeHalIrqEvent_e _HalJpeIrqMaskConvertReal2Enumerate( JpeReg_t* pJpeReg,u16 mask) ++{ ++ JpeHalIrqEvent_e enumerate = (u16)(mask & 0xFFAF); ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 0 ++ if(mask & 0x0010 && !pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_TXIP_TIMEOUT; ++ } ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 1 ++ if(mask & 0x0010 && pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_VS; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 0 ++ if(mask & 0x0040 && !pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_NET_TRIGGER; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 1 ++ if(mask & 0x0040 && pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_VIU_ROW_DONE; ++ } ++ ++ return enumerate; ++} ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetIrqMask ++ * Set interrupt trigger mask ++ * ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetIrqMask(JpeHalHandle_t* handle, JpeHalIrqEvent_e mask) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg1c.tReg1c.nRegJpeGIrqMask = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg,mask); ++ REGW(nBaseAddr,0x1c, pJpeReg->uReg1c.nReg1c, "[%x] reg[%x] : irq mask\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeClearIrq ++ * Clear triggered interrupt ++ * ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void HalJpeClearIrq(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr,0x1d, "[%x] reg[%x] :IRQ register\n"); ++ ++ pJpeReg->uReg1d.tReg1d.nRegJpeGIrqClr = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg,mask); ++ REGW(nBaseAddr,0x1d, pJpeReg->uReg1d.nReg1d, "[%x] reg[%x] : Clear IRQ\n"); ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr,0x1d, "[%x] reg[%x] :IRQ register\n"); // HW is write-one-clear, so update again ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrqCheck ++ * Check current IRQ status ++ * ++ * Parameters: ++ * mask: Bitwise mask to be checked ++ * ++ * Return: ++ * Checked result, bitwise ++ */ ++JpeHalIrqEvent_e HalJpeGetIrqCheck(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ ++ u16 reg_value; ++ reg_value = REGR(nBaseAddr,0x1e, "[%x] reg[%x] :IRQ cpu and ip status\n"); ++ ++ return _HalJpeIrqMaskConvertReal2Enumerate(pJpeReg,reg_value) & mask; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrq ++ * Get current interrupt trigger status ++ * ++ * Return: ++ * Bitwise status ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++u16 HalJpeGetIrq(JpeHalHandle_t* handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ u16 u16Reg; ++ u16Reg = REGR(nBaseAddr, 0x1e, "[%x] reg[%x] :IRQ cpu and ip status\n"); ++ ++ return u16Reg; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrqEvent ++ * IRQ bit mask check ++ * ++ * Parameters: ++ * u16IrqReg: Bitwise IRQ status ++ * IrqEventMask: Bitwise mask ++ * ++ * Return: ++ * none ++ */ ++//JpeHalIrqEvent_e HalJpeGetIrqEvent(u16 u16IrqReg, JpeHalIrqEvent_e IrqEventMask) ++//{ ++// return _HalJpeIrqMaskConvertReal2Enumerate(u16IrqReg) & IrqEventMask; ++//} ++ ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Quntization Tables Setting // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeQTableEntryRead ++ * Read a entry of Q table ++ * ++ * Parameters: ++ * index: Q table index ++ * value: the pointer of value address ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++static int _HalJpeQTableEntryRead(JpeReg_t* pJpeReg,u32 nBaseAddr,u16 index, u16 *value) ++{ ++ int retry = TIME_OUT_CNT; ++ ++ ++ //read data ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcRw = 0; ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 1; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcAdr = index; ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table address\n"); ++ REGW(nBaseAddr,0x48, pJpeReg->uReg48.nReg48, "[%x] reg[%x] : table read enable\n"); ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 0; // write one clear ++ ++ while(retry-- > 0) { ++ pJpeReg->uReg49.nReg49 = REGR(nBaseAddr,0x49, "[%x] reg[%x] : table write enable\n"); ++ if(pJpeReg->uReg49.tReg49.nRegJpeSTbcDone) { ++ // Clear done ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 1; ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 0; ++ ++ // Get value ++ *value = REGR(nBaseAddr,0x4b, "[%x] reg[%x] : table read enable\n"); ++ break; ++ } ++ } ++ ++ return retry; ++} ++ ++/******************************************************************************************************************* ++ * _HalJpeQTableEntryWrite ++ * Write a entry of Q table ++ * ++ * Parameters: ++ * index: Q table index ++ * value: Quantization value ++ * ++ * Return: ++ * >=0: success ++ * <=0: failed ++ */ ++static int _HalJpeQTableEntryWrite(JpeReg_t* pJpeReg,u32 nBaseAddr,u16 index, u16 value) ++{ ++ int retry = TIME_OUT_CNT; ++ ++ // Set value ++ pJpeReg->uReg4a.tReg4a.nRegJpeSTbcWdata = value; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcRw = 1; ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 1; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcAdr = index; ++ REGW(nBaseAddr,0x4a, pJpeReg->uReg4a.nReg4a, "[%x] reg[%x] : table write data\n"); ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table address\n"); ++ REGW(nBaseAddr,0x48, pJpeReg->uReg48.nReg48, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 0; // write one clear ++ ++ // Wait for set done ++ while(retry-- > 0) { ++ pJpeReg->uReg49.nReg49 = REGR(nBaseAddr,0x49, "[%x] reg[%x] : table write enable\n"); ++ if(pJpeReg->uReg49.tReg49.nRegJpeSTbcDone) { ++ // Clear done ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 1; ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 0; ++ break; ++ } ++ } ++ ++ return retry; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetQTable ++ * Update Q table ++ * ++ * Parameters: ++ * q_table_y: Q table for Y ++ * q_table_c: Q table for CbCr ++ * size: table size ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++int HalJpeSetQTable(JpeHalHandle_t* handle,const u16 *q_table_y, const u16 *q_table_c, u32 size) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ u16 value_w, value_r; ++ int i, retry, ret = 0; ++ ++ // Switch SW mode to update Q table ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 0; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=0\n"); ++ ++ // ? ++ // jpe_reg.uReg48.nReg48 = 0; ++ ++ // Udate Y table ++ for(i=0; i 0) { ++ value_w = q_table_y[((i&0x7)<<3)|(i>>3)]; ++ ++ // Write ++ if(_HalJpeQTableEntryWrite(pJpeReg,nBaseAddr,i, value_w) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i, &value_r) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Compare ++ if(value_r == value_w) ++ break; ++ } ++ } ++ ++ // Udate C table ++ for(i=0; i 0) { ++ value_w = q_table_c[((i&0x7)<<3)|(i>>3)]; ++ ++ // Write ++ if(_HalJpeQTableEntryWrite(pJpeReg,nBaseAddr,i+64, value_w) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i+64, &value_r) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Compare ++ if(value_r == value_w) ++ break; ++ } ++ } ++ ++ // update Index last identyfier ++ // The default size of Quantization table is 64, but JPE can accept that size smaller than 64 and ++ // treat others as 0 ( I guess...) ++ pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxLast = size; ++ pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxSwlast = (size < 63) ? 1 : 0; ++ REGW(nBaseAddr,0x2c, pJpeReg->uReg2c.nReg2c, "[%x] reg[%x] : Last zigzag\n"); ++ ++RETURN: ++ // Switch to hw mode ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 1; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=1\n"); ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeReadQTable ++ * Read Q table set last time ++ * ++ * Parameters: ++ * q_table_y: Q table for Y ++ * q_table_c: Q table for CbCr ++ * size: table size ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++int HalJpeReadQTable(JpeHalHandle_t* handle,u16 *q_table_y, u16 *q_table_c, u32 *size) ++{ ++ int i, ret = 0; ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ // Switch SW mode to read Q table ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 0; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=0\n"); ++ ++ // Is the size of table smaller than 64? ++ if(pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxSwlast) { ++ *size = pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxLast; ++ } else { ++ *size = 64; ++ } ++ ++ // ? ++ // jpe_reg.uReg48.nReg48 = 0; ++ ++ // Udate Y table ++ for(i=0; i<*size; i++) { ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i, q_table_y+i) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ } ++ ++ // Udate C table ++ for(i=0; i<*size; i++) { ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i+64, q_table_c+i) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ } ++ ++RETURN: ++ // Switch to hw mode ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 1; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=1\n"); ++ ++ return ret; ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Configurations // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeSetJpeMode ++ * Config JPEG Mode ++ * ++ * Parameters: ++ * bUseJPE: 1 is JPEG encoder, 0 is JPEG decoder ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetJpeMode(JpeHalHandle_t* handle,u32 bUseJPE) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ if (bUseJPE) ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 0; ++ else ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 1; ++ ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : Set JPE mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetCodecFormat ++ * Config the encode froamt of HW codec ++ * ++ * Parameters: ++ * format: JPE_HAL_CODEC_JPEG: JPEG Mode ++ * JPE_HAL_CODEC_H263I: HW not support ++ * JPE_HAL_CODEC_ENCODE_DCT: SW not implemented yet ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetCodecFormat(JpeHalHandle_t* handle,JpeHalCodecFormat_e format) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ switch(format) { ++ case JPE_HAL_CODEC_JPEG: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 0; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 0; ++ break; ++ ++ case JPE_HAL_CODEC_H263I: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 1; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 0; ++ break; ++ ++ case JPE_HAL_CODEC_ENCODE_DCT: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 0; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 1; ++ break; ++ } ++ ++ REGW(nBaseAddr,0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : Codec mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetEncFormat ++ * Config the RAW format for HW codec ++ * ++ * Parameters: ++ * format: JPE_HAL_RAW_YUYV: 422 YUYV ++ * JPE_HAL_RAW_YVYU: 422 YVYU ++ * JPE_HAL_RAW_NV12: 420 NV12 ++ * JPE_HAL_RAW_NV21: 420 NV21 ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetRawFormat(JpeHalHandle_t* handle,JpeHalRawFormat_e format) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ switch(format) { ++ case JPE_HAL_RAW_YUYV: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 1; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 0; ++ break; ++ ++ case JPE_HAL_RAW_YVYU: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 1; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 1; ++ break; ++ ++ case JPE_HAL_RAW_NV12: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 0; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 0; ++ break; ++ ++ case JPE_HAL_RAW_NV21: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 0; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 1; ++ break; ++ } ++ ++ REGW(nBaseAddr,0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : YUV format\n"); ++ REGW(nBaseAddr,0x5F, pJpeReg->uReg5f.nReg5f, "[%x] reg[%x] : YUV format\n"); ++} ++ ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetPicDim ++ * Config the input dimension (for encoder only?) ++ * ++ * Parameters: ++ * width: Image width in pixel ++ * height: Image height in pixel ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetPicDim(JpeHalHandle_t* handle,u32 width, u32 height) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg01.tReg01.nRegJpeGPicWidth = width; // (width+15)&~15; ++ pJpeReg->uReg02.tReg02.nRegJpeGPicHeight = (height+7)&~7; ++ pJpeReg->uReg5e.tReg5e.nRegGJpeYPitch = (width+15) / 16; ++ pJpeReg->uReg5e.tReg5e.nRegGJpeCPitch = (width+15) / 16; ++ REGW(nBaseAddr,0x01, pJpeReg->uReg01.nReg01, "[%x] reg[%x] : picture width\n"); ++ REGW(nBaseAddr,0x02, pJpeReg->uReg02.nReg02, "[%x] reg[%x] : picture height\n"); ++ REGW(nBaseAddr,0x5E, pJpeReg->uReg5e.nReg5e, "[%x] reg[%x] : picture pitch\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeToggleOutBuf ++ * Toggle output buffer ++ * ++ * Parameters: ++ * nObufIdx: new output buffer index ++ * ++ * Return: ++ * none ++ */ ++void HalJpeToggleOutBuf(JpeHalHandle_t* handle,u32 nObufIdx) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ if (nObufIdx==0) ++ { ++ ms_dprintf(0,"nRegJpeObufToggleObuf_0\n"); ++ pJpeReg->uReg3b.nReg3b = REGR(nBaseAddr,0x3b, "[%x] reg[%x] : SW read buffer 0\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : SW read buffer 0\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ } ++ else ++ { ++ ms_dprintf(0,"nRegJpeObufToggleObuf_1\n"); ++ pJpeReg->uReg3b.nReg3b = REGR(nBaseAddr,0x3b, "[%x] reg[%x] : SW read buffer 1\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : SW read buffer 1\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ } ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetInputMode ++ * Config the operation mode of input buffer ++ * ++ * Parameters: ++ * mode: JPE_HAL_BUFFER_ROW_MODE: Double buffer mode (for ROW of IMI?) ++ * Others: Normal (single) frame mode (for MIU?) ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetInputMode(JpeHalHandle_t* handle,JpeHalInBufMode_e mode) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ if(mode == JPE_HAL_BUFFER_ROW_MODE) ++ pJpeReg->uReg18.tReg18.nRegJpeGJpeBuffermode = 0; ++ else ++ pJpeReg->uReg18.tReg18.nRegJpeGJpeBuffermode = 1; ++ REGW(nBaseAddr,0x18, pJpeReg->uReg18.nReg18, "[%x] reg[%x] : input buffer mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetOutputMode ++ * Config the operation mode of output buffer ++ * ++ * Parameters: ++ * mode: JPE_HAL_OBUF_SINGLE_MODE: All outputs are written to only one buffer ++ * JPE_HAL_OBUF_MULTI_MODE: Outputs are written to may buffers ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetOutputMode(JpeHalHandle_t *handle,JpeHalOutBufMode_e mode) ++{ ++ // End of config?? ++ uint nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufHwEn = mode; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : output buffer mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetInBuf ++ * Config input & output address ++ * ++ * Parameters: ++ * ptInBufCfg: Input buffer configuration ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetInBuf(JpeHalHandle_t* handle,pJpeHalInBufCfg ptInBufCfg) ++{ ++ u32 addr; ++ uint nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ //assert((ptBufInfo->nInBufYAddr[0]&0xFF)==0); ++ //assert((ptBufInfo->nInBufYAddr[1]&0xFF)==0); ++ //assert((ptBufInfo->nInBufCAddr[0]&0xFF)==0); ++ //assert((ptBufInfo->nInBufCAddr[1]&0xFF)==0); ++ ++ // Y0 ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufYAddr[0]); ++ pJpeReg->uReg06.tReg06.nRegJpeGBufYAdr0Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg07.tReg07.nRegJpeGBufYAdr0High = addr>>(8+16); ++ ++ // Y1 ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufYAddr[1]); ++ pJpeReg->uReg08.tReg08.nRegJpeGBufYAdr1Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg09.tReg09.nRegJpeGBufYAdr1High = addr>>(8+16); ++ ++ // C0 ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufCAddr[0]); ++ pJpeReg->uReg0a.tReg0a.nRegJpeGBufCAdr0Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg0b.tReg0b.nRegJpeGBufCAdr0High = addr>>(8+16); ++ ++ // C1 ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufCAddr[1]); ++ pJpeReg->uReg0c.tReg0c.nRegJpeGBufCAdr1Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg0d.tReg0d.nRegJpeGBufCAdr1High = addr>>(8+16); ++ ++ // Input buffers ++ // ++ REGW(nBaseAddr,0x06, pJpeReg->uReg06.nReg06, "[%x] reg[%x] : Y0_low\n"); ++ REGW(nBaseAddr,0x07, pJpeReg->uReg07.nReg07, "[%x] reg[%x] : Y0_high\n"); ++ REGW(nBaseAddr,0x08, pJpeReg->uReg08.nReg08, "[%x] reg[%x] : Y1_low\n"); ++ REGW(nBaseAddr,0x09, pJpeReg->uReg09.nReg09, "[%x] reg[%x] : Y1 high\n"); ++ REGW(nBaseAddr,0x0a, pJpeReg->uReg0a.nReg0a, "[%x] reg[%x] : C0_low\n"); ++ REGW(nBaseAddr,0x0b, pJpeReg->uReg0b.nReg0b, "[%x] reg[%x] : C0_high\n"); ++ REGW(nBaseAddr,0x0c, pJpeReg->uReg0c.nReg0c, "[%x] reg[%x] : C1_low\n"); ++ REGW(nBaseAddr,0x0d, pJpeReg->uReg0d.nReg0d, "[%x] reg[%x] : C1_high\n"); ++} ++ ++/******************************************************************************************************************* ++ * _HalJpeSetOutBuf ++ * Set output buffer ++ * ++ * Parameters: ++ * addr: physical address ++ * id: index of addres ++ * 0: start of 1st address ++ * 1: end of 1st address ++ * 2: start of 2nd address ++ * 3: end of 2nd address ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSetOutBuf(JpeReg_t* pJpeReg,u32 nBaseAddr,u32 addr, u32 id) ++{ ++ addr = Chip_Phys_to_MIU(addr); ++ ++ // Write address info ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (addr>>2)&0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = addr>>(2+16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = id; ++ REGW(nBaseAddr,0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr,0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ ++ // Enable write action? ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr,0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++ // jpe_reg.uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 0; ++ // REGW(0x3e, jpe_reg.uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write disable\n"); ++} ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetOutBuf ++ * Config input & output address ++ * ++ * Parameters: ++ * ptBufCfg: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetOutBuf(JpeHalHandle_t* handle,pJpeHalOutBufCfg ptOutBufCfg) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ // Start to config Output buffer ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspFdcOffset = ptOutBufCfg->nJpeOutBitOffset; ++#if defined(ADD_JPDE_0_1) ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ ++ // Start to config output buffer (write one clear) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; // HW is write-one-clear ++#endif ++ ++ ++ // Set 1st address ++ if(ptOutBufCfg->nOutBufAddr[0] != 0 && ptOutBufCfg->nOutBufSize[0] != 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "Set[0] 0x%08X, size %d\n", ptOutBufCfg->nOutBufAddr[0], ptOutBufCfg->nOutBufSize[0]); ++ _HalJpeSetOutBuf(pJpeReg, nBaseAddr, ptOutBufCfg->nOutBufAddr[0], 0); ++ _HalJpeSetOutBuf(pJpeReg, nBaseAddr, ptOutBufCfg->nOutBufAddr[0] + ptOutBufCfg->nOutBufSize[0]-1, 1); ++ ++ } ++ ++ // Set 2nd address ++ if(ptOutBufCfg->nOutBufAddr[1] != 0 && ptOutBufCfg->nOutBufSize[1] != 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "Set[1] 0x%08X, size %d\n", ptOutBufCfg->nOutBufAddr[1], ptOutBufCfg->nOutBufSize[1]); ++ _HalJpeSetOutBuf(pJpeReg,nBaseAddr,ptOutBufCfg->nOutBufAddr[1], 2); ++ _HalJpeSetOutBuf(pJpeReg,nBaseAddr,ptOutBufCfg->nOutBufAddr[1] + ptOutBufCfg->nOutBufSize[1]-1, 3); ++ } ++ ++ // Set configured address ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : buffer mode\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; // HW is write-one-clear ++ ++ ++#if defined(ADD_JPDE_0_1) ++ // Stop configuring output buffer (write one clear) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; // HW is write-one-clear ++#endif ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetDctMbAddr ++ * ??? ++ * ++ * Parameters: ++ * PhyAddr: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetDctMbAddr(JpeHalHandle_t* handle,u32 PhyAddr) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ u32 nMiuStartAddr, nMiuEndAddr, nY0MiuAddr; ++ ++ nMiuStartAddr = PhyAddr; ++ nMiuEndAddr = PhyAddr+768; ++ nY0MiuAddr = PhyAddr; ++ ++ REGW(nBaseAddr,0x06,(nY0MiuAddr>>8)&0xFFFF, "[%x] reg[%x] : Y0_low\n"); ++ REGW(nBaseAddr,0x07, nY0MiuAddr>>(8+16), "[%x] reg[%x] : Y0_high\n"); ++ // Output buffer ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspFdcOffset = 0; ++#if defined(ADD_JPDE_0_1) ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; ++#endif ++ ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (nMiuStartAddr>>2)&0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = nMiuStartAddr>>(2+16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = 0; ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr,0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr,0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ REGW(nBaseAddr,0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (nMiuEndAddr>>2)&0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = nMiuEndAddr>>(2+16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = 1; ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr,0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr,0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ REGW(nBaseAddr,0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : buffer mode\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; // HW is write-one-clear ++} ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Controls // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeSoftReset ++ * Reset JPEG engine ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSoftReset(JpeReg_t* pJpeReg,u32 nBaseAddr) ++{ ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 0; // Assure JPE is running. ++ pJpeReg->uReg00.tReg00.nRegJpeGSoftRstz =0; ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ ++ // delay for lower MCM frequence ++ // Repeated write to replace udelay(1) becase 1 us is too long ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ ++ pJpeReg->uReg00.tReg00.nRegJpeGSoftRstz = 1; ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 1\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSoftReset ++ * SW reset JPEG engine & internal variables ++ * ++ * Parameters: ++ * handle: HAL handle ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSoftReset(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++#define _UPDATE_REG_VAR(nBaseAddr,reg_no) pJpeReg->uReg##reg_no.nReg##reg_no = REGR(nBaseAddr,0x##reg_no, "\n");//REGR(0x##reg_no, "\n"); ++ // SW reset at first ++ _HalJpeSoftReset(pJpeReg,nBaseAddr); ++ ++ // Sync all HW setting to jpe_reg ++ _UPDATE_REG_VAR(nBaseAddr,00); ++ _UPDATE_REG_VAR(nBaseAddr,01); ++ _UPDATE_REG_VAR(nBaseAddr,02); ++ _UPDATE_REG_VAR(nBaseAddr,03); ++ _UPDATE_REG_VAR(nBaseAddr,06); ++ _UPDATE_REG_VAR(nBaseAddr,07); ++ _UPDATE_REG_VAR(nBaseAddr,08); ++ _UPDATE_REG_VAR(nBaseAddr,09); ++ _UPDATE_REG_VAR(nBaseAddr,0a); ++ _UPDATE_REG_VAR(nBaseAddr,0b); ++ _UPDATE_REG_VAR(nBaseAddr,0c); ++ _UPDATE_REG_VAR(nBaseAddr,0d); ++ _UPDATE_REG_VAR(nBaseAddr,0f); ++ _UPDATE_REG_VAR(nBaseAddr,10); ++ _UPDATE_REG_VAR(nBaseAddr,16); ++ _UPDATE_REG_VAR(nBaseAddr,18); ++ _UPDATE_REG_VAR(nBaseAddr,1c); ++ _UPDATE_REG_VAR(nBaseAddr,1d); ++ _UPDATE_REG_VAR(nBaseAddr,1e); ++ _UPDATE_REG_VAR(nBaseAddr,1f); ++ _UPDATE_REG_VAR(nBaseAddr,20); ++ _UPDATE_REG_VAR(nBaseAddr,21); ++ _UPDATE_REG_VAR(nBaseAddr,2c); ++ _UPDATE_REG_VAR(nBaseAddr,2d); ++ _UPDATE_REG_VAR(nBaseAddr,2e); ++ _UPDATE_REG_VAR(nBaseAddr,32); ++ _UPDATE_REG_VAR(nBaseAddr,33); ++ _UPDATE_REG_VAR(nBaseAddr,34); ++ _UPDATE_REG_VAR(nBaseAddr,35); ++ _UPDATE_REG_VAR(nBaseAddr,36); ++ _UPDATE_REG_VAR(nBaseAddr,3b); ++ _UPDATE_REG_VAR(nBaseAddr,3c); ++ _UPDATE_REG_VAR(nBaseAddr,3d); ++ _UPDATE_REG_VAR(nBaseAddr,3e); ++ _UPDATE_REG_VAR(nBaseAddr,42); ++ _UPDATE_REG_VAR(nBaseAddr,44); ++ _UPDATE_REG_VAR(nBaseAddr,45); ++ _UPDATE_REG_VAR(nBaseAddr,48); ++ _UPDATE_REG_VAR(nBaseAddr,49); ++ _UPDATE_REG_VAR(nBaseAddr,4a); ++ _UPDATE_REG_VAR(nBaseAddr,4b); ++ _UPDATE_REG_VAR(nBaseAddr,54); ++ _UPDATE_REG_VAR(nBaseAddr,55); ++ _UPDATE_REG_VAR(nBaseAddr,56); ++ _UPDATE_REG_VAR(nBaseAddr,57); ++ _UPDATE_REG_VAR(nBaseAddr,58); ++ _UPDATE_REG_VAR(nBaseAddr,59); ++ _UPDATE_REG_VAR(nBaseAddr,5a); ++ _UPDATE_REG_VAR(nBaseAddr,5b); ++ _UPDATE_REG_VAR(nBaseAddr,5c); ++ _UPDATE_REG_VAR(nBaseAddr,5d); ++ _UPDATE_REG_VAR(nBaseAddr,5e); ++ _UPDATE_REG_VAR(nBaseAddr,5f); ++ _UPDATE_REG_VAR(nBaseAddr,60); ++ _UPDATE_REG_VAR(nBaseAddr,61); ++ _UPDATE_REG_VAR(nBaseAddr,64); ++ _UPDATE_REG_VAR(nBaseAddr,6f); ++ _UPDATE_REG_VAR(nBaseAddr,70); ++ _UPDATE_REG_VAR(nBaseAddr,71); ++ _UPDATE_REG_VAR(nBaseAddr,72); ++ _UPDATE_REG_VAR(nBaseAddr,73); ++ _UPDATE_REG_VAR(nBaseAddr,74); ++ _UPDATE_REG_VAR(nBaseAddr,75); ++ _UPDATE_REG_VAR(nBaseAddr,76); ++ _UPDATE_REG_VAR(nBaseAddr,77); ++ _UPDATE_REG_VAR(nBaseAddr,78); ++ _UPDATE_REG_VAR(nBaseAddr,79); ++ _UPDATE_REG_VAR(nBaseAddr,7a); ++ _UPDATE_REG_VAR(nBaseAddr,7b); ++ _UPDATE_REG_VAR(nBaseAddr,7c); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetEnable ++ * Enable JPEG enging ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetEnable(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 1; ++ REGW(nBaseAddr,0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : frame start\n"); ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 0; // write-one-clear ++} ++ ++/******************************************************************************************************************* ++ * HalJpeHwRowCounterReset ++ * SW reset JPEG VIU? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeHwRowCounterReset(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg18.tReg18.nRegJpeGViuSoftRstz=0; ++ REGW(nBaseAddr,0x18,pJpeReg->uReg18.nReg18, "[%x] reg[%x] : VIU reset 0\n"); ++ pJpeReg->uReg18.tReg18.nRegJpeGViuSoftRstz=1; ++ REGW(nBaseAddr,0x18, pJpeReg->uReg18.nReg18, "[%x] reg[%x] : VIU reset 1\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetSwVsnc ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetSWRowDown(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg75.tReg75.nRegJpeGSwRowDone = 1; ++ REGW(nBaseAddr,0x75, pJpeReg->uReg75.nReg75,"[%x] reg[%x] :SW Row Down\n"); ++ pJpeReg->uReg75.tReg75.nRegJpeGSwRowDone = 0; // write one clear ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Status // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeResetSafe ++ * to indicate there're no MIU activities that need to pay attention to ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * true: MIU accesse is active ++ * false: no MIU activity ++ */ ++bool HalJpeResetSafe(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr,0x1d, "[%x] reg[%x] :reset safe\n"); ++ ++ ms_dprintf(0, "uReg1d.tReg1d.nRegJpeGSwrstSafe is %d\n", pJpeReg->uReg1d.tReg1d.nRegJpeGSwrstSafe); ++ ++ return (pJpeReg->uReg1d.tReg1d.nRegJpeGSwrstSafe == 1) ? true : false; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetOutputByteSize ++ * Retrive the output size ++ * ++ * Parameters: ++ * nObufSel: buffer index ++ * ++ * Return: ++ * Output buffer size ++ */ ++u32 HalJpeGetOutputByteSize(JpeHalHandle_t *handle,u32 nObufSel) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ u16 u16Reg1, u16Reg2, u16Reg3; ++ u32 wptr, oBufSadr; ++ u16 u16Reg; ++ //u16 i; ++ ++ u16Reg = REGR(nBaseAddr,0x3b, "[%x] reg[%x] : obuf status\n"); ++ pJpeReg->uReg3b.nReg3b = u16Reg; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkEn = 1; ++/* ++ for (i=0; i<4; i++) { ++ jpe_reg.uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = i; ++ REGW(0x3b, jpe_reg.uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ _ReadRegJpe(0x44, &u16Reg1, "[%x] reg[%x] : wptr low\n"); ++ _ReadRegJpe(0x45, &u16Reg2, "[%x] reg[%x] : wptr high\n"); ++ oBufSadr = ((u16Reg2<<16) | u16Reg1)<<2; ++ ms_dprintf(1,"Obuf%d %d %d(s=0,e=1) = 0x%08x\n",i,i>>1, i&1, oBufSadr); ++ } ++*/ ++ //obuf adr read back check selection(0/1/2/3:s0/e0/s1/e1) ++ if (nObufSel == JPE_OBUF_0) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = 0; //s0 ++ else ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = 2; //s1 ++ ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ u16Reg1 = REGR(nBaseAddr,0x44, "[%x] reg[%x] : wptr low\n"); ++ u16Reg2 = REGR(nBaseAddr,0x45, "[%x] reg[%x] : wptr high\n"); ++ oBufSadr = ((u16Reg2<<16) | u16Reg1)<<2; ++ ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkEn = 0; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ u16Reg1 = REGR(nBaseAddr,0x44, "[%x] reg[%x] : wptr low\n"); ++ u16Reg2 = REGR(nBaseAddr,0x45, "[%x] reg[%x] : wptr high\n"); ++ wptr = ((u16Reg2<<16) | u16Reg1)<<2; ++ ++ u16Reg3 = REGR(nBaseAddr,0x42, "[%x] reg[%x] : last bytes in miu\n"); ++ ++ u16Reg3 &= 3; ++ u16Reg3 += 1; ++ ++ return wptr - oBufSadr + u16Reg3; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRowDownCnt ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++u16 HalJpeGetRowDownCnt(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ u16 u16Reg; ++ u16Reg = REGR(nBaseAddr,0x10, "[%x] reg[%x] :Row down count\n"); ++ return u16Reg&0x0F; ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// TXIP? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeStop ++ * ??? ++ * ++ * Parameters: ++ * opt: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeStop(JpeHalHandle_t *handle,bool opt) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg2d.tReg2d.nRegJpeSTxipSngSet = opt; ++ REGW(nBaseAddr,0x2d, pJpeReg->uReg2d.nReg2d, "[%x] reg[%x] : stop\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRowCount ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++u16 HalJpeGetRowCount(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg2e.nReg2e = REGR(nBaseAddr,0x2e, "[%x] reg[%x] :Row count\n"); ++ return pJpeReg->uReg2e.nReg2e; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeIdleCount ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeIdleCount(JpeHalHandle_t *handle,u16 nIdleCount) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg32.tReg32.nRegJpeSTxipWaitMode = 0; ++ pJpeReg->uReg33.tReg33.nRegJpeSTxipIdlecnt = nIdleCount; ++ ++ REGW(nBaseAddr,0x32, pJpeReg->uReg32.nReg32, "[%x] reg[%x] : wait mode\n"); ++ REGW(nBaseAddr,0x33, pJpeReg->uReg33.nReg33, "[%x] reg[%x] : idle count\n"); ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Debugs? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeSetCycleReport ++ * ??? ++ * ++ * Parameters: ++ * mode: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetCycleReport(JpeHalHandle_t *handle,u16 mode) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++#ifdef CYCLE_REPORT ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkEn = 1; ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkSel = 1; ++#else ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkEn = 0; ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkSel = 0; ++#endif ++ REGW(nBaseAddr,0x73, pJpeReg->uReg73.nReg73, "[%x] reg[%x] : cycle report\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetCrc ++ * ??? ++ * ++ * Parameters: ++ * mode: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetCrc(JpeHalHandle_t *handle,u16 mode) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = handle->pJpeReg; ++ pJpeReg->uReg73.tReg73.nRegJpeGCrcMode = 0x2; ++ REGW(nBaseAddr,0x73, pJpeReg->uReg73.nReg73, "[%x] reg[%x] : crc mode\n"); ++} ++ ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Capibilities? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeGetBufferModeSupportInfo ++ * Capability of supported mode of current JPEG HW ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The bitwise combination of supported mode ++ */ ++u8 HalJpeGetBufferModeSupportInfo(void) ++{ ++ return JPE_HAL_BUFFER_ROW_MODE|JPE_HAL_BUFFER_FRAME_MODE; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetSclHandShakeSupportInfo ++ * Capability of scaler data handshake ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * JpeHalSclHandShake_e ++ */ ++u8 HalJpeGetSclHandShakeSupportInfo(void) ++{ ++ return JPE_HAL_SCL_HANDSHAKE_ON; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetCodecSupportInfo ++ * Capability of supported codec format ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The bitwize combination of supported codec mode ++ */ ++u8 HalJpeGetCodecSupportInfo(void) ++{ ++ return JPE_HAL_CODEC_JPEG; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetOutBufSLogAddrAlignInfo ++ * Alignment of output buffer address (start) ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetOutBufSLogAddrAlignInfo(void) ++{ ++ return 4; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetOutBufELogAddrAlignInfo ++ * Alignment of output buffer address (end) ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetOutBufELogAddrAlignInfo(void) ++{ ++ return 4; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRefCLogAddrAlignInfo ++ * Alignment of input buffer address (Y) ++ * ++ * Parameters: ++ * bufID: not use.... ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetRefYLogAddrAlignInfo(u8 bufID) ++{ ++ return 256; ++ ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRefCLogAddrAlignInfo ++ * Alignment of input buffer address (C) ++ * ++ * Parameters: ++ * bufID: not use.... ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetRefCLogAddrAlignInfo(u8 bufID) ++{ ++ return 256; ++} ++ +diff --git a/drivers/mstar/jpe/jpe_scatter.c b/drivers/mstar/jpe/jpe_scatter.c +new file mode 100644 +index 00000000..574527b8 +--- /dev/null ++++ b/drivers/mstar/jpe/jpe_scatter.c +@@ -0,0 +1,365 @@ ++#include ++ ++#include "mdrv_jpe.h" ++#include "jpe_scatter.h" ++ ++#if SCATTER_USED ++ ++struct jpe_scatter* jpe_scatter_create(struct device *dev, unsigned long addr, u32 size, enum dma_data_direction dir) ++{ ++ int i, j, k; ++ struct page **pages = NULL; ++ u32 page_num; ++ u32 offset, scatter_size; ++ int entries; ++ int page_write = (dir==DMA_TO_DEVICE) ? 0 : 1; ++ ++ struct jpe_scatter *scatter; ++ ++ // Allocate container ++ scatter = kcalloc(1, sizeof(struct jpe_scatter), GFP_KERNEL); ++ if(scatter == NULL) ++ return NULL; ++ ++ // Init values ++ scatter->addr = addr; ++ scatter->dir = dir; ++ scatter->orig_size = size; ++ // INIT_LIST_HEAD(&scatter->list); ++ ++ // Cacluate the offset ++ offset = addr & ~PAGE_MASK; ++ page_num = (offset + size + PAGE_SIZE-1) / PAGE_SIZE; ++ //addr &= PAGE_MASK; ++ ++ // Alloacte page lists ++ pages = kcalloc(1, sizeof(struct page*)*page_num, GFP_KERNEL); ++ if(pages == NULL) ++ goto ERROR; ++ ++ // Get pages ++ down_read(¤t->mm->mmap_sem); ++ entries = get_user_pages(current, current->mm, addr&PAGE_MASK, page_num, page_write, 0, pages, NULL); ++ up_read(¤t->mm->mmap_sem); ++ if(entries <= 0) { ++ JPE_MSG(JPE_MSG_DEBUG, "0x%08lX has no user pages, assume the addr is physical address\n", addr); ++ ++ scatter->entries = 0; // Zero means the address is physical address ++ ++ // Allocate & init state ++ scatter->state = kmalloc(sizeof(JpeState_e), GFP_KERNEL); ++ if(scatter->state == NULL) ++ goto ERROR; ++ scatter->state[0] = JPE_IDLE_STATE; ++ ++ goto RETURN_1; ++ } ++ ++ // Allocate & init scatter list ++ scatter->scatter = kmalloc(sizeof(struct scatterlist)*entries, GFP_KERNEL); ++ if(scatter->scatter == NULL) ++ goto ERROR; ++ sg_init_table(scatter->scatter, entries); ++ ++#if 0 // debug ++ for(i=0; i scatter_size) { ++ size -= scatter_size; ++ } else { ++ scatter_size = size; ++ size = 0; ++ } ++ ++ // Set consecutive pages into one scatter entry ++ sg_set_page(scatter->scatter+k, pages[i], scatter_size, offset); ++ ++ offset = 0; // only fist scatter has offset ++ } ++ ++ // Scatter list is finish ++ scatter->entries = k; ++ sg_mark_end(scatter->scatter+k); ++ ++ // Allocate & init state array ++ scatter->state = kmalloc(sizeof(JpeState_e)*k, GFP_KERNEL); ++ if(scatter->state == NULL) ++ goto ERROR; ++ for(i=0; istate[i] = JPE_IDLE_STATE; ++ } ++ ++ // Dma map, and we may need to handle return values... ++ dma_map_sg(dev, scatter->scatter, scatter->entries, scatter->dir); ++ ++ goto RETURN_2; ++ ++//////////////////////////////// ++RETURN_1: ++ if(scatter->scatter != NULL) ++ kfree(scatter->scatter); ++ ++RETURN_2: ++ if(pages != NULL) ++ kfree(pages); ++ ++ JPE_MSG(JPE_MSG_DEBUG, "jpe_sccater_create() cretaed success\n"); ++ ++ return scatter; ++ ++ERROR: ++ if(pages != NULL) ++ kfree(pages); ++ ++ if(scatter->scatter != NULL) ++ kfree(scatter->scatter); ++ ++ if(scatter->state != NULL) ++ kfree(scatter->state); ++ ++ kfree(scatter); ++ ++ return NULL; ++} ++ ++static void jpe_scatter_unmap(struct device *dev, struct jpe_scatter *scatter) ++{ ++ // umap and free scatter list ++ if(scatter->scatter != NULL) { ++ dma_unmap_sg(dev, scatter->scatter, scatter->entries, scatter->dir); ++ kfree(scatter->scatter); ++ scatter->scatter = NULL; ++ scatter->entries = 0; ++ } ++} ++ ++void jpe_scatter_release(struct device *dev, struct jpe_scatter *scatter) ++{ ++ // umap and free scatter list ++ jpe_scatter_unmap(dev, scatter); ++ ++ // Free status array ++ if(scatter->state != NULL) ++ kfree(scatter->state); ++ ++ kfree(scatter); ++} ++ ++void jpe_scatter_list_add(struct list_head *scatter_head, struct jpe_scatter *scatter) ++{ ++ list_add_tail(&scatter->list, scatter_head); ++} ++ ++void jpe_scatter_list_release(struct device *dev, struct list_head *scatter_head) ++{ ++ struct jpe_scatter *entry, *temp; ++ ++ // release all entries ++ list_for_each_entry_safe(entry, temp, scatter_head, list) { ++ list_del(&entry->list); ++ jpe_scatter_release(dev, entry); ++ } ++} ++ ++int jpe_scatter_frag_get(struct list_head *scatter_head, unsigned long *addr, unsigned long *size) ++{ ++ int i; ++ struct jpe_scatter *entry; ++ struct scatterlist *sg; ++ ++ list_for_each_entry(entry, scatter_head, list) { ++ // Is a physical address? ++ if(entry->entries == 0) { ++ if(entry->state[0] == JPE_IDLE_STATE) { ++ entry->state[0] = JPE_BUSY_STATE; ++ *addr = entry->addr; ++ *size = entry->orig_size; ++ JPE_MSG(JPE_MSG_DEBUG, "return phy addr 0x%08lX, size %ld\n", *addr, *size); ++ return 0; ++ } ++ ++ } else { // scatter fragments ++ // for(i=0; ientries; i++) { ++ for_each_sg(entry->scatter, sg, entry->entries, i) { ++ //JPE_MSG(JPE_MSG_DEBUG, "state[%d] = %X\n", i, entry->state[i]); ++ if(entry->state[i] == JPE_IDLE_STATE) { ++ entry->state[i] = JPE_BUSY_STATE; ++ *addr = sg_dma_address(sg); ++ *size = sg_dma_len(sg); ++ JPE_MSG(JPE_MSG_DEBUG, "return frag addr 0x%08lX, size %ld\n", *addr, *size); ++ return 0; ++ } ++ } ++ } ++ } ++ ++ JPE_MSG(JPE_MSG_ERR, "jpe_scatter_frag_get() did not find any idel buffer/fragment\n"); ++ ++ // Did not found any idle fragment ++ return -ENOMEM; ++} ++ ++int jpe_scatter_frag_set(struct device *dev, struct list_head *scatter_head, unsigned long addr, unsigned long size, JpeState_e new_state) ++{ ++ int i; ++ struct jpe_scatter *entry, *temp; ++ struct scatterlist *sg; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "addr 0x%08lX status set as %X\n", addr, new_state); ++ ++ list_for_each_entry_safe(entry, temp, scatter_head, list) { ++ // Is a physical address? ++ if(entry->entries == 0) { ++ if(entry->addr == addr) { ++ entry->output_size = size; ++ entry->state[0] = new_state; ++ return 0; ++ } ++ ++ } else { // scatter fragments ++ // for(i=0; ientries; i++) { ++ for_each_sg(entry->scatter, sg, entry->entries, i) { ++ // JPE_MSG(JPE_MSG_DEBUG, "fragment addr %08X = %08lX\n", sg_dma_address(sg), addr); ++ if(sg_dma_address(sg) == addr) { ++ // If frame done or all fragments are filled, release the scatter ++ if(new_state == JPE_FRAME_DONE_STATE || ++ (new_state == JPE_OUTBUF_FULL_STATE && i == entry->entries - 1/*sg_is_last(sg_next(sg))*/) ) { ++ jpe_scatter_unmap(dev, entry); // Unmap the DMA addr ++ entry->entries = 0; // Not scatter anyomre, so set entry as 0 ++ entry->output_size += size; ++ entry->state[0] = new_state; // Update new state for the access latter by jpe_scatter_ready_buf_get ++ return 0; ++ } else { ++ // Update statue only ++ entry->output_size += size; ++ entry->state[i] = new_state; ++ return 0; ++ } ++ } ++ } ++ } ++ } ++ ++ JPE_MSG(JPE_MSG_ERR, "jpe_scatter_frag_set() did not find the address 0x%08lX\n", addr); ++ ++ // Did not found the address ++ return -ENOMEM; ++} ++ ++int jpe_scatter_ready_buf_get(struct device *dev, struct list_head *scatter_head, unsigned long *addr, unsigned long *orig_size, unsigned long *output_size, JpeState_e *state) ++{ ++ struct jpe_scatter *entry, *temp; ++ ++ list_for_each_entry_safe(entry, temp, scatter_head, list) { ++ // Is ready buffer? ++ if(entry->entries != 0 || (entry->state[0] != JPE_FRAME_DONE_STATE && entry->state[0] != JPE_OUTBUF_FULL_STATE) ) ++ continue; ++ ++ // Assign return infomation ++ *addr = entry->addr; ++ *orig_size = entry->orig_size; ++ *output_size = entry->output_size; ++ *state = entry->state[0]; ++ ++ // Remove the entry from the list ++ list_del(&entry->list); ++ ++ return 0; ++ } ++ ++ JPE_MSG(JPE_MSG_ERR, "jpe_scatter_ready_buf_get() found no ready buffer\n"); ++ ++ // Did not found the address ++ return -ENOMEM; ++} ++ ++bool jpe_scatter_ready_buf_check(struct device *dev, struct list_head *scatter_head) ++{ ++ struct jpe_scatter *entry, *temp; ++ ++ list_for_each_entry_safe(entry, temp, scatter_head, list) { ++ // Is ready buffer? ++ if(entry->entries != 0 || (entry->state[0] != JPE_FRAME_DONE_STATE && entry->state[0] != JPE_OUTBUF_FULL_STATE) ) ++ continue; ++ ++ return 1; ++ } ++ ++ // Did not found the address ++ return 0; ++} ++ ++#endif ++ ++#if 0 ++static void scatter_test(struct device *dev, u32 addr, u32 size) ++{ ++ struct jpe_scatter *scatter; ++ struct list_head scatter_head; ++ int i; ++ unsigned long frag_addr, frag_size; ++ ++ JPE_MSG(JPE_MSG_ERR, "%s start, addr = 0x%X (0x%X), size = %d\n", __func__, addr, virt_to_phys((void*)addr), size); ++ ++ INIT_LIST_HEAD(&scatter_head); ++ ++ // Create a scatter ++ scatter = jpe_sccater_create(dev, addr, size, DMA_BIDIRECTIONAL); ++ if(scatter == NULL) { ++ JPE_MSG(JPE_MSG_ERR, "jpe_sccater_create() return NULL!!\n"); ++ return; ++ } ++ ++ jpe_scatter_list_add(&scatter_head, scatter); ++ ++ JPE_MSG(JPE_MSG_ERR, "Parese all fragments in all buffers added\n" ); ++ for(i=0; ; i++) { ++ // Get a idle fragment ++ if(jpe_scatter_frag_get(&scatter_head, &frag_addr, &frag_size, JPE_BUSY_STATE) != 0) { ++ JPE_MSG(JPE_MSG_ERR, "Run out fragments...\n"); ++ break; ++ } ++ ++ JPE_MSG(JPE_MSG_ERR, "sg[%d] frag = %08lX, %ld\n", i, frag_addr, frag_size ); ++ ++ // Set the fragment is full ++ if(jpe_scatter_frag_set(dev, &scatter_head, frag_addr, JPE_OUTBUF_FULL_STATE) != 0) { ++ JPE_MSG(JPE_MSG_ERR, "Can't set fragment?? Is hould no happen in test\n"); ++ break; ++ } ++ } ++ ++ if(jpe_scatter_ready_buf_get(dev, &scatter_head, &frag_addr, &frag_size) == 0) { ++ JPE_MSG(JPE_MSG_ERR, "Get ready addr = 0x%08lX, size = %ld\n", frag_addr, frag_size); ++ } else { ++ JPE_MSG(JPE_MSG_ERR, "Can't get ready buffer!!\n"); ++ } ++ ++ jpe_scatter_list_release(dev, &scatter_head); ++ ++ JPE_MSG(JPE_MSG_ERR, "%s end\n", __func__); ++} ++#endif +diff --git a/drivers/mstar/jpe/jpe_scatter.h b/drivers/mstar/jpe/jpe_scatter.h +new file mode 100644 +index 00000000..a41d5bf6 +--- /dev/null ++++ b/drivers/mstar/jpe/jpe_scatter.h +@@ -0,0 +1,35 @@ ++#ifndef __JPE_SCATTER_H__ ++#define __JPE_SCATTER_H__ ++ ++#include ++#include ++#include ++ ++#include "mdrv_jpe_io_st.h" ++ ++#define SCATTER_USED (0) ++ ++#if SCATTER_USED ++struct jpe_scatter ++{ ++ struct list_head list; // list head ++ unsigned long addr; // Address form userspace, it maybe a virtual or physical one ++ unsigned long orig_size; // Original buffer Size ++ unsigned long output_size; // Output Size ++ struct scatterlist *scatter; // Scatterlist pointer ++ JpeState_e *state; // A array to keep the state of fragments in a scatter list ++ int entries; // How many entries (fragments) in the scatter list ++ enum dma_data_direction dir; // Direction of data ++}; ++ ++struct jpe_scatter* jpe_scatter_create(struct device *dev, unsigned long addr, u32 size, enum dma_data_direction dir); ++void jpe_scatter_release(struct device *dev, struct jpe_scatter *scatter); ++void jpe_scatter_list_add(struct list_head *scatter_head, struct jpe_scatter *scatter); ++void jpe_scatter_list_release(struct device *dev, struct list_head *scatter_head); ++int jpe_scatter_frag_get(struct list_head *scatter_head, unsigned long *addr, unsigned long *size); ++int jpe_scatter_frag_set(struct device *dev, struct list_head *scatter_head, unsigned long addr, unsigned long size, JpeState_e new_state); ++int jpe_scatter_ready_buf_get(struct device *dev, struct list_head *scatter_head, unsigned long *addr, unsigned long *orig_size, unsigned long *proc_size, JpeState_e *state); ++bool jpe_scatter_ready_buf_check(struct device *dev, struct list_head *scatter_head); ++#endif ++ ++#endif //__JPE_SCATTER_H__ +diff --git a/drivers/mstar/jpe/mdrv_jpe.c b/drivers/mstar/jpe/mdrv_jpe.c +new file mode 100644 +index 00000000..203a99fb +--- /dev/null ++++ b/drivers/mstar/jpe/mdrv_jpe.c +@@ -0,0 +1,1261 @@ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "mdrv_jpe.h" ++#include "mdrv_jpe_io.h" ++#include "mdrv_jpe_io_st.h" ++#include "drv_jpe.h" ++#include "jpe_scatter.h" ++#include "ms_msys.h" ++ ++#define MDRV_JPE_DEVICE_COUNT 1 // How many device will be installed ++#define MDRV_JPE_NAME "mstar_jpe" ++#define MDRV_JPE_MINOR 0 ++#define MDRV_JPE_CLASS_NAME "mstar_jpe_class" ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Data Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct jpe_dev_data ++{ ++ struct platform_device *pdev; // Platform device ++ struct cdev cdev; // Character device ++ int ref_count; // Reference count, how many file instances opened ++ JpeHandle_t jpe_handle; ++// int clk_ref_count; ++ int hw_enable; ++// int jpe_on; ++ struct jpe_file_data *cur_file; ++ void __iomem *regs; // I/O register base address ++ struct clk* clk; // Clock ++ unsigned int irq; // IRQ number ++ unsigned int iobase; ++// spinlock_t lock; ++ struct semaphore jpe_sem; ++ wait_queue_head_t jpe_wqh; ++// void* dev_data; // driver data ++} jpe_dev_data; ++ ++struct jpe_enc_outbuf ++{ ++// struct list_head list; ++// unsigned long data; ++ unsigned long addr; ++ unsigned long orig_size; // Original buffer Size ++ unsigned long output_size; // Output Size ++ JpeState_e eState; ++}; ++ ++typedef struct jpe_file_data ++{ ++ jpe_dev_data *dev_data; ++// JpeHandle_t jpe_handle; ++ JpeCfg_t jpeCfg; ++#if SCATTER_USED ++ struct list_head outbuf_scatter_head; // Scatter list wrapper header for output buffer ++#else ++ struct jpe_enc_outbuf enc_outbuf; ++#endif ++ unsigned long nOutBufAddr; ++ wait_queue_head_t wait_queue; ++ JpeHalOutBufCfg_t jpeHalBuf; ++ unsigned long nToggleOutBuf[2]; ++ u32 nToggleOutBufIdx; ++} jpe_file_data; ++ ++//------------------------------------------------------------------------------------------------- ++// Clock Enable ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_clock_on ++ * enable device clock ++ * ++ * Parameters: ++ * dev_data: device data ++ * ++ * Return: ++ * 0: OK, others: failed ++ */ ++static int mdrv_jpe_clock_on(jpe_dev_data *dev_data) ++{ ++ int num_parents, i; ++ struct clk **jpe_clks; ++ struct clk *clk_parent; ++ u32 clk_select; ++ int err; ++ ++ num_parents = of_clk_get_parent_count(dev_data->pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ jpe_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ for(i = 0; i < num_parents; i++) ++ { ++ jpe_clks[i] = of_clk_get(dev_data->pdev->dev.of_node, i); ++ if (IS_ERR(jpe_clks[i])) ++ { ++ JPE_MSG(JPE_MSG_ERR, "can't get clock node from %s\n", dev_data->pdev->dev.of_node->full_name); ++ kfree(jpe_clks); ++ return -1; ++ } ++ else ++ { ++ if(i == 0) ++ { ++ /* Get Clock select */ ++ if(of_property_read_u32(dev_data->pdev->dev.of_node, "clk-select", &clk_select) != 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "failed to read clk-select\n"); ++ return -1; ++ } ++ JPE_MSG(JPE_MSG_DEBUG, "clk-select = %d\n", clk_select); ++ /* Get parent clock */ ++ clk_parent = clk_get_parent_by_index(jpe_clks[i], clk_select); ++ if(IS_ERR(clk_parent)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "can't get parent clock\n"); ++ return -1; ++ } ++ /* Set clock parent */ ++ err = clk_set_parent(jpe_clks[i], clk_parent); ++ if(err != 0) ++ return err; ++ dev_data->clk = jpe_clks[i]; ++ } ++ clk_prepare_enable(jpe_clks[i]); ++ } ++ } ++ kfree(jpe_clks); ++ } ++ return 0; ++} ++ ++static int mdrv_jpe_clock_off(jpe_dev_data *dev_data) ++{ ++ int num_parents, i; ++ struct clk **jpe_clks; ++ ++ num_parents = of_clk_get_parent_count(dev_data->pdev->dev.of_node); ++ if(num_parents > 0) ++ { ++ jpe_clks = kzalloc((sizeof(struct clk *) * num_parents), GFP_KERNEL); ++ ++ for(i = 0; i < num_parents; i++) ++ { ++ jpe_clks[i] = of_clk_get(dev_data->pdev->dev.of_node, i); ++ if (IS_ERR(jpe_clks[i])) ++ { ++ JPE_MSG(JPE_MSG_ERR, "can't get clock node from %s\n", dev_data->pdev->dev.of_node->full_name); ++ kfree(jpe_clks); ++ return -1; ++ } ++ else ++ { ++ if(i == 0) ++ { ++ dev_data->clk = NULL; ++ } ++ clk_disable_unprepare(jpe_clks[i]); ++ clk_put(jpe_clks[i]); ++ } ++ } ++ kfree(jpe_clks); ++ } ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// File operations ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_isr ++ * ISR handler ++ * ++ * Parameters: ++ * irq: IRQ ++ * dev_data: Device data which is assigned from request_irq() ++ * ++ * Return: ++ * Always IRQ_HANDLED to stop parsing ISR ++ */ ++irqreturn_t mdrv_jpe_drv_isr(int irq, void* dev_data) ++{ ++ jpe_dev_data* _dev_data = (jpe_dev_data*)dev_data; ++ jpe_file_data *file_data = _dev_data->cur_file; ++#if SCATTER_USED ++ JpeBufInfo_t out_buf; ++// u32 next_toggle_idx = file_data->nToggleOutBufIdx; ++ unsigned long addr, size; ++#endif ++ ++ /* Call IRQ handler */ ++ JpeIsrHandler(irq, &_dev_data->jpe_handle); ++ ++ switch(_dev_data->jpe_handle.ejpeDevStatus) ++ { ++ case JPE_DEV_OUTBUF_FULL: ++#if SCATTER_USED ++ /* Update scatter status */ ++ jpe_scatter_frag_set(&file_data->dev_data->pdev->dev, ++ &file_data->outbuf_scatter_head, ++ file_data->nOutBufAddr, // file_data->nToggleOutBuf[file_data->nToggleOutBufIdx], ++ file_data->jpe_handle.nEncodeSize, ++ JPE_OUTBUF_FULL_STATE); ++ ++ /* Clear processed fragment */ ++ file_data->nOutBufAddr = 0; ++// file_data->nToggleOutBuf[file_data->nToggleOutBufIdx] = 0; ++ ++ /* Try to get next fragment */ ++ if(jpe_scatter_frag_get(&file_data->outbuf_scatter_head, &addr, &size) != 0) ++ { ++ /* there is no more fragment!! */ ++ /* Wake up waiting thread/process */ ++ wake_up_interruptible(&file_data->wait_queue); ++ break; ++ } ++ ++ /* config setting of output buffer */ ++ out_buf.nAddr = addr; ++ out_buf.nSize = size; ++ ++ /* Set output buffer */ ++ DrvJpeSetOutBuf(&file_data->jpe_handle, &out_buf); ++ ++ /* Update status */ ++ file_data->jpe_handle.ejpeDevStatus = JPE_DEV_BUSY; ++ file_data->nOutBufAddr = addr; ++#else ++ JPE_MSG(JPE_MSG_WARNING, "JPE_DEV_OUTBUF_FULL!!\n"); ++ file_data->enc_outbuf.addr = file_data->nOutBufAddr; ++ file_data->enc_outbuf.output_size = _dev_data->jpe_handle.nEncodeSize; ++ file_data->enc_outbuf.eState = JPE_OUTBUF_FULL_STATE; ++ ++ /* Clear filled buffer address */ ++ file_data->nOutBufAddr = 0; ++ ++ /* Wake up waiting thread/process */ ++ wake_up_interruptible(&file_data->wait_queue); ++ ++ /* Enter critical section */ ++ down(&_dev_data->jpe_sem); ++ _dev_data->cur_file = NULL; ++ /* Leave critical section */ ++ up(&_dev_data->jpe_sem); ++ wake_up(&_dev_data->jpe_wqh); ++ ++#endif ++ break; ++ ++ case JPE_DEV_ENC_DONE: ++ /* Update scatter status */ ++#if SCATTER_USED ++ jpe_scatter_frag_set(&file_data->dev_data->pdev->dev, ++ &file_data->outbuf_scatter_head, ++ file_data->nOutBufAddr, ++ file_data->jpe_handle.nEncodeSize, ++ JPE_FRAME_DONE_STATE); ++#else ++ file_data->enc_outbuf.addr = file_data->nOutBufAddr; ++ file_data->enc_outbuf.output_size = _dev_data->jpe_handle.nEncodeSize; ++ file_data->enc_outbuf.eState = JPE_FRAME_DONE_STATE; ++#endif ++ ++ /* Clear filled buffer address */ ++ file_data->nOutBufAddr = 0; ++ ++ /* Wake up waiting thread/process */ ++ wake_up_interruptible(&file_data->wait_queue); ++ ++ /* Enter critical section */ ++// spin_lock(&_dev_data->lock); ++ down(&_dev_data->jpe_sem); ++// file_data->dev_data->jpe_on = 0; ++ _dev_data->cur_file = NULL; ++ /* Leave critical section */ ++// spin_unlock(&_dev_data->lock); ++ up(&_dev_data->jpe_sem); ++ wake_up(&_dev_data->jpe_wqh); ++ break; ++ ++ default: ++ break; ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_open ++ * File open handler ++ * The device can has a instance at the same time, and the open ++ * operator also enable the clock and request q ISR. ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_jpe_drv_open(struct inode *inode, struct file *filp) ++{ ++ jpe_dev_data *dev_data; ++ jpe_file_data *file_data; ++ int err; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "try to open a jpe handle\n"); ++ ++ dev_data = container_of(inode->i_cdev, struct jpe_dev_data, cdev); ++ ++ /* Enter critical section */ ++// spin_lock(&dev_data->lock); ++ /* Only one file can be create at the same time!! */ ++// if(dev_data->ref_count != 0) ++// { ++// spin_unlock(&dev_data->lock); // leave critical section at first ++// JPE_MSG(JPE_MSG_ERR, "error: user can open only one instance at the same time!!\n"); ++// return -EMFILE; ++// } ++ /* Increase instance */ ++// dev_data->ref_count++; ++ /* Leave critical section */ ++// spin_unlock(&dev_data->lock); ++ ++ /* allocate buffer */ ++ file_data = kmalloc(sizeof(jpe_file_data), GFP_KERNEL); ++ if(file_data == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "error: can't allocate buffer\n"); ++ err = -ENOSPC; ++ goto ERROR_3; ++ } ++ ++ /* Assgin dev_data and keep file_data in the file structure */ ++#if SCATTER_USED ++ INIT_LIST_HEAD(&file_data->outbuf_scatter_head); ++#else ++ file_data->enc_outbuf.addr = 0; ++ file_data->enc_outbuf.orig_size = 0; ++ file_data->enc_outbuf.output_size = 0; ++ file_data->enc_outbuf.eState = JPE_IDLE_STATE; ++#endif ++ file_data->dev_data = dev_data; ++// dev_data->jpe_handle.jpeHalHandle.nBaseAddr= dev_data->iobase; ++// dev_data->jpe_handle.jpeHalHandle.pJpeReg = kzalloc(sizeof(JpeReg_t), GFP_KERNEL); ++ filp->private_data = file_data; ++ /* Initialize wait queue */ ++ init_waitqueue_head(&file_data->wait_queue); ++ ++ /* Reset JPE DRV */ ++ //DrvJpeReset(&file_data->jpe_handle); ++ ++ /* Enable clock */ ++ down(&dev_data->jpe_sem); ++// if( dev_data->clk_ref_count == 0) ++// { ++// dev_data->clk_ref_count++; ++// mdrv_jpe_clock_on(dev_data); ++// } ++// if (!dev_data->ref_count) ++// { ++ if(!dev_data->hw_enable) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "file(%p): open jpe hw\n", file_data); ++// dev_data->jpe_handle.jpeHalHandle.nBaseAddr= dev_data->iobase; ++// dev_data->jpe_handle.jpeHalHandle.pJpeReg = kzalloc(sizeof(JpeReg_t), GFP_KERNEL); ++ mdrv_jpe_clock_on(dev_data); ++ /* Register a ISR */ ++ err = request_irq(dev_data->irq, mdrv_jpe_drv_isr, IRQ_TYPE_LEVEL_HIGH, "isp interrupt", dev_data); ++ if(err != 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "isp interrupt failed (irq: %d, errno:%d)\n", file_data->dev_data->irq, err); ++ up(&dev_data->jpe_sem); ++ goto ERROR_1; ++ } ++ dev_data->hw_enable = 1; ++ } ++// } ++ /* Increase instance */ ++ dev_data->ref_count++; ++ up(&dev_data->jpe_sem); ++ ++ return 0; ++ ++ERROR_1: ++ clk_disable_unprepare(dev_data->clk); ++ clk_put(dev_data->clk); ++//ERROR_2: ++ kfree(file_data); ++ERROR_3: ++// dev_data->clk = NULL; ++// dev_data->irq = 0; ++// dev_data->ref_count--; ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_release ++ * File close handler ++ * The operator will release clock & ISR ++ * ++ * Parameters: ++ * inode: inode ++ * filp: file structure ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_jpe_drv_release(struct inode *inode, struct file *filp) ++{ ++ jpe_file_data *file_data = (jpe_file_data*)filp->private_data; ++ jpe_dev_data *dev_data = file_data->dev_data; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "relese a jpe handle\n"); ++ ++ /* Reset JPE DRV */ ++// DrvJpeReset(&dev_data->jpe_handle); ++ ++#if SCATTER_USED ++ /* Release scatter list */ ++ jpe_scatter_list_release(&file_data->dev_data->pdev->dev, &file_data->outbuf_scatter_head); ++#endif ++ ++ /* Free a ISR */ ++// free_irq(dev_data->irq, dev_data); ++ ++// spin_lock(&dev_data->lock); ++// /* Reduce the reference count */ ++// dev_data->ref_count--; ++// spin_unlock(&dev_data->lock); ++ ++ ++ down(&dev_data->jpe_sem); ++ /* Reduce the reference count */ ++ dev_data->ref_count--; ++// if( file_data->dev_data->clk_ref_count > 0) ++// { ++// file_data->dev_data->clk_ref_count--; ++// mdrv_jpe_clock_off(file_data->dev_data); ++// } ++ if(!dev_data->ref_count && dev_data->hw_enable) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "file(%p): close jpe hw\n", file_data); ++ /* Free a ISR */ ++ free_irq(dev_data->irq, dev_data); ++ mdrv_jpe_clock_off(dev_data); ++ dev_data->hw_enable = 0; ++// kfree(dev_data->jpe_handle.jpeHalHandle.pJpeReg); ++ } ++ up(&dev_data->jpe_sem); ++ ++ /* Release memory */ ++// kfree(file_data->jpe_handle.jpeHalHandle.pJpeReg); ++ kfree(file_data); ++ ++ return 0; ++} ++ ++#ifdef JPE_MSG_ENABLE ++// g_param_list is a private data for mdrv_jpe_drv_show_ioctl_cmd() ++#define DEF_2_STR(d) {d, #d} ++struct ++{ ++ unsigned int cmd; ++ char *name; ++} ++g_param_list[] = ++{ ++ DEF_2_STR(JPE_IOC_INIT), ++ DEF_2_STR(JPE_IOC_ENCODE_FRAME), ++ DEF_2_STR(JPE_IOC_GETBITS), ++ DEF_2_STR(JPE_IOC_GET_CAPS), ++ DEF_2_STR(JPE_IOC_SET_OUTBUF) ++}; ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_show_ioctl_cmd ++ * Debug function to show the string of ioctl command ++ * ++ * Parameters: ++ * filp: file structure ++ * cmd: command ++ * arg: argument ++ * ++ * Return: ++ * none ++ */ ++static void mdrv_jpe_drv_show_ioctl_cmd(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int i; ++ ++ for(i=0; iprivate_data); ++ return; ++ } ++ } ++ ++ JPE_MSG(JPE_MSG_DEBUG, "ioctl cmd 0x%X, file %p\n", cmd, filp->private_data); ++} ++#endif ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_ioctl_get_caps ++ * IOCTL handler for JPE_IOC_GET_CAPS. ++ * This command provide the capabilities of JPE ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of JpeCaps_t from user-space ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e mdrv_jpe_drv_ioctl_get_caps(jpe_file_data *file_data, unsigned long arg) ++{ ++ JpeCaps_t caps; ++ int err; ++ jpe_dev_data *dev_data = file_data->dev_data; ++ ++ /* Get capability */ ++ err = DrvJpeGetCaps(&dev_data->jpe_handle, &caps); ++ if(err != JPE_IOC_RET_SUCCESS) ++ { ++ return err; ++ } ++ ++ /* Copy to user-space */ ++ err = copy_to_user((void*)arg, &caps, sizeof(caps)); ++ if(err != 0) ++ { ++ err = JPE_IOC_RET_FAIL; ++ } ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_ioctl_get_bit_info ++ * IOCTL handler for JPE_IOC_GETBITS ++ * User uses this command to get the processed (encoded) buffer ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of JpeBitstreamInfo_t from user-space ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e mdrv_jpe_drv_ioctl_get_bit_info(jpe_file_data *file_data, unsigned long arg) ++{ ++ JpeBitstreamInfo_t bit_info; ++ JPE_IOC_RET_STATUS_e ret = JPE_IOC_RET_SUCCESS; ++ int err; ++ ++#if SCATTER_USED ++ /* Get one ready */ ++ err = jpe_scatter_ready_buf_get(&file_data->dev_data->pdev->dev, &file_data->outbuf_scatter_head, ++ &bit_info.nAddr, &bit_info.nOrigSize, &bit_info.nOutputSize, &bit_info.eState); ++ if(err != 0) ++ { ++ return JPE_IOC_RET_BAD_OUTBUF; ++ } ++#else ++ if (file_data->enc_outbuf.eState == JPE_FRAME_DONE_STATE || bit_info.nAddr || bit_info.nOutputSize) ++ { ++ bit_info.nAddr = file_data->enc_outbuf.addr; ++ bit_info.nOrigSize = file_data->enc_outbuf.orig_size; ++ bit_info.nOutputSize = file_data->enc_outbuf.output_size; ++ bit_info.eState = file_data->enc_outbuf.eState; ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_ERR, "found no ready buffer\n"); ++ return JPE_IOC_RET_BAD_OUTBUF; ++ } ++#endif ++ ++ /* Copy to user-space */ ++ err = copy_to_user((void*)arg, &bit_info, sizeof(bit_info)); ++ if(err != 0) ++ { ++ ret = JPE_IOC_RET_FAIL; ++ } ++ ++#if SCATTER_USED ++ /* Change the status if all ready buffers are pumped out */ ++ if(!jpe_scatter_ready_buf_check(&file_data->dev_data->pdev->dev, &file_data->outbuf_scatter_head) && file_data->jpe_handle.ejpeDevStatus == JPE_DEV_ENC_DONE) ++ { ++ file_data->jpe_handle.ejpeDevStatus = JPE_DEV_INIT; ++ } ++#endif ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * _mdrv_jpe_drv_ioctl_check_inbuf ++ * This function use get_user_pages & scatter to check whether the input buffer is virtual memory ++ * because HW cna't accept a fragmented input buffer. ++ * ++ * Parameters: ++ * file_data: file private data ++ * in_buf: input buffer information ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e _mdrv_jpe_drv_ioctl_check_inbuf(jpe_file_data *file_data, JpeCfg_t *pJpeCfg) ++{ ++#if SCATTER_USED ++ struct jpe_scatter *scatter; ++ int err = JPE_IOC_RET_SUCCESS; ++#endif ++ ++#if SCATTER_USED ++ if(pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr != 0 && pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize != 0) ++ { ++ scatter = jpe_scatter_create(&file_data->dev_data->pdev->dev, in_buf->nAddr, in_buf->nSize, DMA_TO_DEVICE); ++ if(scatter == NULL || scatter->entries > 1) ++ { ++ /* create failed or a virtual-fragmented memory */ ++ JPE_MSG(JPE_MSG_ERR, "Address 0x%08lX (size:%ld) is fragment memory from malloc and JPE input doesn't support it\n", in_buf->nAddr, in_buf->nSize); ++ err = JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ /* Free allocated scatter because this is for check only */ ++ if(scatter != NULL) ++ jpe_scatter_release(&file_data->dev_data->pdev->dev, scatter); ++ } ++#endif ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/******************************************************************************************************************* ++ * _mdrv_jpe_drv_ioctl_set_outbuf ++ * Private IOCTL handler for JPE_IOC_SET_OUTBUF ++ * User uses this command to set output buffer. ++ * This function would not handle the data of user-space ++ * ++ * Parameters: ++ * file_data: file private data ++ * out_buf: output buffer information ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e _mdrv_jpe_drv_ioctl_set_outbuf(jpe_file_data *file_data, JpeBufInfo_t *out_buf) ++{ ++#if SCATTER_USED ++ struct jpe_scatter *scatter; ++#endif ++ jpe_dev_data *dev_data = file_data->dev_data; ++ int err = JPE_IOC_RET_SUCCESS; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "process output buffer\n"); ++ ++ /* Is a legal buffer? */ ++ if(out_buf->nAddr == 0 || out_buf->nSize == 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "The buffer is not legal\n"); ++ err = JPE_IOC_RET_BAD_INBUF; ++ goto RETURN; ++ } ++ ++#if SCATTER_USED ++ /* Process output buffer */ ++ scatter = jpe_scatter_create(&file_data->dev_data->pdev->dev, out_buf->nAddr, out_buf->nSize, DMA_FROM_DEVICE); ++ if(scatter == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "can't create scatter for 0x%08lX (size:%ld)\n", out_buf->nAddr, out_buf->nSize ); ++ err = JPE_IOC_RET_BAD_OUTBUF; ++ goto RETURN; ++ } ++ ++ /* Add to list */ ++ jpe_scatter_list_add(&file_data->outbuf_scatter_head, scatter); ++ ++ /* Assign the output buffer info to HW if it is not assign and HW is idle */ ++ if(file_data->nOutBufAddr == 0 && ++ (file_data->jpe_handle.ejpeDevStatus == JPE_DEV_INIT || ++ file_data->jpe_handle.ejpeDevStatus == JPE_DEV_OUTBUF_FULL)) ++ { ++ ++ /* Replace & get a fragment from scatter */ ++ if(jpe_scatter_frag_get(&file_data->outbuf_scatter_head, &out_buf->nAddr, &out_buf->nSize) != 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "can't get fragment\n"); ++ jpe_scatter_list_release(&file_data->dev_data->pdev->dev, &file_data->outbuf_scatter_head); ++ err = JPE_IOC_RET_BAD_INBUF; ++ goto RETURN; ++ } ++ JPE_MSG(JPE_MSG_DEBUG, "get fragment 0x%08lX, size %ld", out_buf->nAddr, out_buf->nSize); ++ ++ /* Set output buffer */ ++ file_data->jpeHalBuf.nOutBufAddr[0] = out_buf->nAddr; ++ file_data->jpeHalBuf.nOutBufSize[0] = out_buf->nSize; ++ file_data->jpeHalBuf.nOutBufSize[1] = 0; ++ file_data->jpeHalBuf.nOutBufAddr[1] = 0; ++ file_data->jpeHalBuf.nJpeOutBitOffset = file_data->jpe_handle.jpeCfg.nJpeOutBitOffset; ++ ++ /* Change the state */ ++ file_data->nOutBufAddr = out_buf->nAddr; ++ if(file_data->jpe_handle.ejpeDevStatus == JPE_DEV_OUTBUF_FULL) ++ { ++ file_data->jpe_handle.ejpeDevStatus = JPE_DEV_BUSY; ++ } ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "no assignment to HW because addr is 0x%08lX or state is %d\n", file_data->nOutBufAddr, file_data->jpe_handle.ejpeDevStatus); ++ } ++#else ++ file_data->enc_outbuf.addr = out_buf->nAddr; ++ file_data->enc_outbuf.orig_size = out_buf->nSize; ++ file_data->enc_outbuf.output_size = 0; ++ file_data->enc_outbuf.eState = JPE_IDLE_STATE; ++ JPE_MSG(JPE_MSG_DEBUG, "enc_outbuf, addr: 0x%08X, orig_size:%ld\n", ++ (__u32)(file_data->enc_outbuf.addr), file_data->enc_outbuf.orig_size); ++ /* Set output buffer */ ++ file_data->jpeHalBuf.nOutBufAddr[0] = out_buf->nAddr; ++ file_data->jpeHalBuf.nOutBufSize[0] = out_buf->nSize; ++ file_data->jpeHalBuf.nOutBufSize[1] = 0; ++ file_data->jpeHalBuf.nOutBufAddr[1] = 0; ++ file_data->jpeHalBuf.nJpeOutBitOffset = dev_data->jpe_handle.jpeCfg.nJpeOutBitOffset; ++ JPE_MSG(JPE_MSG_DEBUG, "jpeHalBuf, nOutBufAddr[0]: 0x%08X, nOutBufSize[0]:%d\n", ++ file_data->jpeHalBuf.nOutBufAddr[0], file_data->jpeHalBuf.nOutBufSize[0]); ++ ++#endif ++ ++RETURN: ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_ioctl_set_outbuf ++ * IOCTL handler for JPE_IOC_SET_OUTBUF ++ * This is a wrapper of _mdrv_jpe_drv_ioctl_check_inbuf ++ * to handler the data from user-space ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of JpeBufInfo_t from user-space ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e mdrv_jpe_drv_ioctl_set_outbuf(jpe_file_data *file_data, unsigned long arg) ++{ ++ JpeBufInfo_t out_buf; ++ int err; ++ ++ if(copy_from_user(&out_buf, (void*)arg, sizeof(JpeBufInfo_t)) != 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "Can't allocate & copy data from user-space\n"); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ err = _mdrv_jpe_drv_ioctl_set_outbuf(file_data, &out_buf); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_ioctl_init ++ * IOCTL handler for JPE_IOC_INIT ++ * User uses this command to reset & init JPE encoder. User has to call this function again ++ * before starting to encode another frame. ++ * ++ * Parameters: ++ * file_data: file private data ++ * arg: argument, a pointer of JpeCfg_t from user-space ++ * ++ * Return: ++ * JPE_IOC_RET_STATUS_e ++ */ ++static JPE_IOC_RET_STATUS_e mdrv_jpe_drv_ioctl_init(jpe_file_data *file_data, unsigned long arg) ++{ ++ int err = JPE_IOC_RET_SUCCESS; ++ JpeCfg_t jpe_cfg; ++// jpe_dev_data *dev_data = file_data->dev_data; ++// struct jpe_scatter *scatter; ++// unsigned long addr, size; ++ JpeBufInfo_t out_buf; ++ ++ /* Copy configure from user-space */ ++ if(copy_from_user(&jpe_cfg, (void*)arg, sizeof(JpeCfg_t)) != 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "Can't allocate & copy data from user-space\n"); ++ err = JPE_IOC_RET_BAD_INBUF; ++ goto RETURN; ++ } ++ ++ /* Check input buffer */ ++ err = _mdrv_jpe_drv_ioctl_check_inbuf(file_data, &jpe_cfg); ++ if(err != JPE_IOC_RET_SUCCESS) ++ { ++ goto RETURN; ++ } ++ ++ /* Clear output buffer info because lower ioctl function would not process buffer directly. */ ++ out_buf.nAddr = jpe_cfg.OutBuf.nAddr; ++ out_buf.nSize = jpe_cfg.OutBuf.nSize; ++ jpe_cfg.OutBuf.nAddr = 0; ++ jpe_cfg.OutBuf.nSize = 0; ++ ++ /* Run lower ioctl function */ ++// err = DrvJpeInit(&dev_data->jpe_handle, &jpe_cfg); ++ memcpy(&file_data->jpeCfg, &jpe_cfg, sizeof(JpeCfg_t)); ++ ++ /* Process output buffer if assigned */ ++ if(err == JPE_IOC_RET_SUCCESS && out_buf.nAddr != 0 && out_buf.nSize != 0) ++ { ++ err = _mdrv_jpe_drv_ioctl_set_outbuf(file_data, &out_buf); ++ } ++ ++RETURN: ++// devm_kfree(&file_data->dev_data->pdev->dev, jpe_cfg); ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_ioctl ++ * IOCTL handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * cmd: command ++ * arg: argument from user-space ++ * ++ * Return: ++ * standard return value ++ */ ++long mdrv_jpe_drv_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ jpe_file_data *file_data = (jpe_file_data*)filp->private_data; ++ jpe_dev_data *dev_data = file_data->dev_data; ++ JPE_IOC_RET_STATUS_e err = JPE_IOC_RET_SUCCESS; ++ ++ // Should we do that? ++ if(file_data == NULL || dev_data->ref_count <= 0) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "driver refCnt = %d!!! \n", dev_data->ref_count); ++ return -EFAULT; ++ } ++ ++#ifdef JPE_MSG_ENABLE ++ // Show Command ++ mdrv_jpe_drv_show_ioctl_cmd(filp, cmd, arg); ++#endif ++ ++ switch(cmd) ++ { ++ case JPE_IOC_INIT: ++ err = mdrv_jpe_drv_ioctl_init(file_data, arg); ++ break; ++ ++ case JPE_IOC_ENCODE_FRAME: ++ if (dev_data->cur_file) ++ { ++ JPE_MSG(JPE_MSG_DEBUG, "file(%p): into waiting queue for hw free\n", file_data); ++ wait_event(dev_data->jpe_wqh, dev_data->cur_file == NULL); ++ JPE_MSG(JPE_MSG_DEBUG, "file(%p): leave waiting queue\n", file_data); ++ } ++ /* Enter critical section */ ++// spin_lock(&dev_data->lock); ++ down(&dev_data->jpe_sem); ++ dev_data->cur_file = file_data; ++ /* Leave critical section */ ++// spin_unlock(&dev_data->lock); ++ up(&dev_data->jpe_sem); ++ JPE_MSG(JPE_MSG_DEBUG, "[in]JPE_IOC_ENCODE_FRAME\n"); ++ /* Run lower ioctl function */ ++ err = DrvJpeInit(&dev_data->jpe_handle, &file_data->jpeCfg); ++ err = DrvJpeEncodeOneFrame(&dev_data->jpe_handle, &file_data->jpeHalBuf); ++ JPE_MSG(JPE_MSG_DEBUG, "[out]JPE_IOC_ENCODE_FRAME\n"); ++ break; ++ ++ case JPE_IOC_SET_OUTBUF: ++ err = mdrv_jpe_drv_ioctl_set_outbuf(file_data, arg); ++ break; ++ ++ case JPE_IOC_GETBITS: ++ err = mdrv_jpe_drv_ioctl_get_bit_info(file_data, arg); ++ break; ++ ++ case JPE_IOC_GET_CAPS: ++ mdrv_jpe_drv_ioctl_get_caps(file_data, arg); ++ break; ++ ++ default: ++ err = JPE_IOC_RET_FAIL; ++// (int)DrvJpeIoctl(&file_data->jpe_handle, cmd, arg); ++ break; ++ } ++ ++// JPE_MSG(JPE_MSG_DEBUG, "ioctl result = %d\n", err); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_ioctl ++ * poll handler entry for file operator ++ * ++ * Parameters: ++ * filp: pointer of file structure ++ * wait: wait queue ++ * ++ * Return: ++ * only 0 or POLLIN | POLLRDNORM ++ */ ++static unsigned int mdrv_jpe_drv_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ jpe_file_data *file_data = (jpe_file_data*)filp->private_data; ++ jpe_dev_data *dev_data = file_data->dev_data; ++ ++ poll_wait(filp, &file_data->wait_queue, wait); ++ ++ switch(dev_data->jpe_handle.ejpeDevStatus) ++ { ++ case JPE_DEV_ENC_DONE: ++ case JPE_DEV_OUTBUF_FULL: ++ return POLLIN | POLLRDNORM; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Platform functions ++//------------------------------------------------------------------------------------------------- ++ ++// Use a struct to gather all global variable ++static struct ++{ ++ int major; // cdev major number ++ int minor_star; // beginning of cdev minor number ++ int reg_count; // registered count ++ struct class *class; // class pointer ++} g_jpe_drv = {0, 0, 0, NULL}; ++ ++static const struct file_operations jpe_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = mdrv_jpe_drv_open, ++ .release = mdrv_jpe_drv_release, ++ .unlocked_ioctl = mdrv_jpe_drv_ioctl, ++ .poll = mdrv_jpe_drv_poll, ++}; ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_probe ++ * Platform device probe handler ++ * ++ * Parameters: ++ * pdev: platform device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_jpe_drv_probe(struct platform_device *pdev) ++{ ++ int err; ++ jpe_dev_data *dev_data; ++ struct resource *res; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "mdrv_jpe_drv_probe\n"); ++ ++ // create drv data buffer ++ dev_data = devm_kcalloc(&pdev->dev, 1, sizeof(jpe_dev_data), GFP_KERNEL); ++ if(dev_data == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "can't allocate buffer\n"); ++ return -ENOMEM; ++ } ++ ++ /* Initialize spin lock */ ++// spin_lock_init(&dev_data->lock); ++ ++ /* Initialize semaphore */ ++ sema_init(&dev_data->jpe_sem, MDRV_JPE_DEVICE_COUNT); ++ ++ /* Initialize wait queue */ ++ init_waitqueue_head(&dev_data->jpe_wqh); ++ ++ /* Keep platform device info */ ++ dev_data->pdev = pdev; ++ ++ /* Initialize current file pointer */ ++ dev_data->cur_file = NULL; ++ ++ /* memory-mapped IO registers */ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ dev_data->iobase = (uint)res->start; ++#if 0 ++ dev_data->regs = devm_ioremap_resource(&pdev->dev, res); ++ if(IS_ERR(dev_data->regs)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Cannot find register base address\n"); ++ return PTR_ERR(dev_data->regs); ++ } ++#endif ++ ++ /* Initialize jpe HW handle register */ ++ dev_data->jpe_handle.jpeHalHandle.nBaseAddr= dev_data->iobase; ++ dev_data->jpe_handle.jpeHalHandle.pJpeReg = kzalloc(sizeof(JpeReg_t), GFP_KERNEL); ++ ++ /* IRQ registration */ ++ dev_data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); ++ if(dev_data->irq < 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Cannot find IRQ\n"); ++ return -ENODEV; ++ } ++ ++ /* Add cdev */ ++ cdev_init(&dev_data->cdev, &jpe_fops); ++ err= cdev_add(&dev_data->cdev, MKDEV(g_jpe_drv.major, g_jpe_drv.minor_star + g_jpe_drv.reg_count), 1); ++ if(err) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Unable add a character device\n"); ++ return err; ++ } ++ ++ /* Create a instance in class */ ++ device_create(g_jpe_drv.class, ++ NULL, ++ MKDEV(g_jpe_drv.major, g_jpe_drv.minor_star + g_jpe_drv.reg_count), ++ dev_data, ++ MDRV_JPE_NAME"%d", g_jpe_drv.minor_star + g_jpe_drv.reg_count); ++ ++ /* Increase registered count */ ++ g_jpe_drv.reg_count++; ++ ++ dev_set_drvdata(&pdev->dev, dev_data); ++ ++ return 0; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_remove ++ * Platform device remove handler ++ * ++ * Parameters: ++ * pdev: platform device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_jpe_drv_remove(struct platform_device *pdev) ++{ ++ jpe_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ JPE_MSG(JPE_MSG_DEBUG, "mdrv_jpe_drv_remove\n"); ++ ++ kfree(dev_data->jpe_handle.jpeHalHandle.pJpeReg); ++ device_destroy(g_jpe_drv.class, dev_data->cdev.dev); ++ cdev_del(&dev_data->cdev); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_suspend ++ * Platform device suspend handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platform device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_jpe_drv_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ jpe_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ JPE_MSG(JPE_MSG_DEBUG, "into suspend\n"); ++ ++ down(&dev_data->jpe_sem); ++// if(dev_data->clk_ref_count > 0){ ++// dev_data->clk_ref_count--; ++// mdrv_jpe_clock_off(dev_data); ++// } ++ if(dev_data->hw_enable) ++ { ++ mdrv_jpe_clock_off(dev_data); ++ dev_data->hw_enable = 0; ++ } ++ up(&dev_data->jpe_sem); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_drv_resume ++ * Platform device resume handler, but nothing to do here ++ * ++ * Parameters: ++ * pdev: platform device ++ * ++ * Return: ++ * standard return value ++ */ ++static int mdrv_jpe_drv_resume(struct platform_device *pdev) ++{ ++ jpe_dev_data *dev_data = dev_get_drvdata(&pdev->dev); ++ ++ JPE_MSG(JPE_MSG_DEBUG, "into resume\n"); ++ ++ down(&dev_data->jpe_sem); ++// if(dev_data->clk_ref_count == 0){ ++// dev_data->clk_ref_count++; ++// mdrv_jpe_clock_on(dev_data); ++// } ++ if (!dev_data->hw_enable) ++ { ++ mdrv_jpe_clock_on(dev_data); ++ dev_data->hw_enable = 1; ++ } ++ up(&dev_data->jpe_sem); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure for device driver ++//------------------------------------------------------------------------------------------------- ++static const struct of_device_id mdrv_jpeg_match[] = ++{ ++ { ++ .compatible = "mstar,cedric-jpe", ++ /*.data = NULL,*/ ++ }, ++ { ++ .compatible = "mstar,infinity-jpe", ++ /*.data = NULL,*/ ++ }, ++ {}, ++}; ++ ++ ++static struct platform_driver mdrv_jpe_driver = ++{ ++ .probe = mdrv_jpe_drv_probe, ++ .remove = mdrv_jpe_drv_remove, ++ .suspend = mdrv_jpe_drv_suspend, ++ .resume = mdrv_jpe_drv_resume, ++ ++ .driver = ++ { ++ .of_match_table = of_match_ptr(mdrv_jpeg_match), ++ .name = "mstar_jpe", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++ ++/******************************************************************************************************************* ++ * _mdrv_jpe_module_init ++ * module init function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_jpe_module_init(void) ++{ ++ int err; ++ dev_t dev; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "Module Init\n"); ++ ++ /* Allocate cdev id */ ++ err = alloc_chrdev_region(&dev, MDRV_JPE_MINOR, MDRV_JPE_DEVICE_COUNT, MDRV_JPE_NAME); ++ if(err) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Unable allocate cdev id\n"); ++ return err; ++ } ++ ++ g_jpe_drv.major = MAJOR(dev); ++ g_jpe_drv.minor_star = MINOR(dev); ++ g_jpe_drv.reg_count = 0; ++ ++ /* Register device class */ ++// g_jpe_drv.class = class_create(THIS_MODULE, MDRV_JPE_CLASS_NAME); ++ g_jpe_drv.class = msys_get_sysfs_class(); ++ if(IS_ERR(g_jpe_drv.class)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Failed at class_create().Please exec [mknod] before operate the device\n"); ++ err = PTR_ERR(g_jpe_drv.class); ++ goto ERR_RETURN; ++ } ++ ++ /* Register platform driver */ ++ err = platform_driver_register(&mdrv_jpe_driver); ++ if(err == 0) ++ { ++ return 0; ++ } ++ ++// class_destroy(g_jpe_drv.class); ++ ++ERR_RETURN: ++ unregister_chrdev_region(MKDEV(g_jpe_drv.major, g_jpe_drv.minor_star), MDRV_JPE_DEVICE_COUNT); ++ ++ return err; ++} ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_module_exit ++ * module exit function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++void mdrv_jpe_module_exit(void) ++{ ++ /* de-initial the who GFLIPDriver */ ++ JPE_MSG(JPE_MSG_ERR, "Module Exit\n"); ++ ++// class_destroy(g_jpe_drv.class); ++ unregister_chrdev_region(MKDEV(g_jpe_drv.major, g_jpe_drv.minor_star), MDRV_JPE_DEVICE_COUNT); ++ platform_driver_unregister(&mdrv_jpe_driver); ++} ++ ++module_init(mdrv_jpe_module_init); ++module_exit(mdrv_jpe_module_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("JPE ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/jpe/mdrv_jpe.h b/drivers/mstar/jpe/mdrv_jpe.h +new file mode 100644 +index 00000000..bf28d9f7 +--- /dev/null ++++ b/drivers/mstar/jpe/mdrv_jpe.h +@@ -0,0 +1,51 @@ ++#include ++ ++// Defines reference kern levels of printfk ++#define JPE_MSG_ERR 3 ++#define JPE_MSG_WARNING 4 ++#define JPE_MSG_DEBUG 5 ++ ++#define JPE_MSG_LEVEL JPE_MSG_WARNING ++ ++ ++#define JPE_MSG_ENABLE ++ ++#ifdef JPE_MSG_ENABLE ++#define JPE_MSG_FUNC_ENABLE ++ ++#define JPE_STRINGIFY(x) #x ++#define JPE_TOSTRING(x) JPE_STRINGIFY(x) ++ ++#ifdef JPE_MSG_FUNC_ENABLE ++#define JPE_MSG_TITLE "[JPE, %s] " ++#define JPE_MSG_FUNC __func__ ++#else ++#define JPE_MSG_TITLE "[JPE] %s" ++#define JPE_MSG_FUNC "" ++#endif ++ ++#define JPE_ASSERT(_con) \ ++ do {\ ++ if (!(_con)) {\ ++ printk(KERN_CRIT "BUG at %s:%d assert(%s)\n",\ ++ __FILE__, __LINE__, #_con);\ ++ BUG();\ ++ }\ ++ } while (0) ++ ++#define JPE_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= JPE_MSG_LEVEL) { \ ++ printk(KERN_SOH JPE_TOSTRING(dbglv) JPE_MSG_TITLE _fmt, JPE_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++#else ++#define JPE_ASSERT(arg) ++#define JPE_MSG(dbglv, _fmt, _args...) ++ ++#endif ++ ++ ++ ++ ++ ++ +diff --git a/drivers/mstar/jpe2/Makefile b/drivers/mstar/jpe2/Makefile +new file mode 100644 +index 00000000..212897a8 +--- /dev/null ++++ b/drivers/mstar/jpe2/Makefile +@@ -0,0 +1,29 @@ ++# ++# Makefile for MStar Infinity JPE device drivers. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/cam_os_wrapper/pub ++EXTRA_CFLAGS += -Idrivers/mstar/jpe2 ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++ccflags-$(CONFIG_MS_JPE) += -DMSOS_TYPE_LINUX_KERNEL ++ ++# files ++ ++#----------------------- drv ----------------------- ++EXTRA_CFLAGS += -Idrivers/mstar/jpe2/drv/inc ++EXTRA_CFLAGS += -Idrivers/mstar/jpe2/drv/pub ++EXTRA_CFLAGS += -Idrivers/mstar/jpe2/ ++ ++#----------------------- hal ----------------------- ++EXTRA_CFLAGS += -Idrivers/mstar/jpe2/hal/pub ++ ++#--------------------- sources --------------------- ++obj-$(CONFIG_MS_JPE) += mstar_jpe.o ++mstar_jpe-y := hal/src/hal_jpe_ios.o \ ++ hal/src/hal_jpe_ops.o \ ++ drv/src/common/drv_jpe_ctx.o \ ++ drv/src/common/drv_jpe_dev.o \ ++ drv/src/linux/drv_jpe_module.o \ ++ ../cam_os_wrapper/src/cam_os_wrapper.o ++# drv/src/common/cam_os_wrapper.o +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/inc/_drv_jpe_ctx.h b/drivers/mstar/jpe2/drv/inc/_drv_jpe_ctx.h +new file mode 100644 +index 00000000..193ac321 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/inc/_drv_jpe_ctx.h +@@ -0,0 +1,25 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef ___DRV_JPE_CTX_H__ ++#define ___DRV_JPE_CTX_H__ ++ ++#include "drv_jpe_io_st_kernel.h" ++ ++JpeCtx_t* JpeCtxAcquire(JpeDev_t* pDev); ++ ++#endif // ___DRV_JPE_CTX_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/inc/_drv_jpe_dev.h b/drivers/mstar/jpe2/drv/inc/_drv_jpe_dev.h +new file mode 100644 +index 00000000..6c7d3067 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/inc/_drv_jpe_dev.h +@@ -0,0 +1,29 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef ___DRV_JPE_DEV_H__ ++#define ___DRV_JPE_DEV_H__ ++ ++#include "drv_jpe_io_st_kernel.h" ++ ++int JpeDevRegister(JpeDev_t*, JpeCtx_t*); ++int JpeDevUnregister(JpeDev_t*, JpeCtx_t*); ++int JpeDevPowerOn(JpeDev_t*, int); ++int JpeDevPushJob(JpeDev_t*, JpeCtx_t*); ++int JpeDevIsrFnx(JpeDev_t*); ++ ++#endif // ___DRV_JPE_DEV_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/jpe.mak b/drivers/mstar/jpe2/drv/jpe.mak +new file mode 100644 +index 00000000..c6d696e2 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/jpe.mak +@@ -0,0 +1,37 @@ ++ ++#------------------------------------------------------------------------------ ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------ ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++ ++JPE_PLATFORM = linux ++#JPE_PLATFORM = rtk ++ ++PATH_C +=\ ++ $(PATH_jpe)/src/common\ ++ $(PATH_jpe)/src/$(JPE_PLATFORM)\ ++ $(PATH_jpe)/test/common\ ++ $(PATH_jpe)/test/$(JPE_PLATFORM) ++ ++PATH_H +=\ ++ $(PATH_jpe)/inc\ ++ $(PATH_jpe_hal)/inc\ ++ $(PATH_jpe_hal)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_jpe)/pub\ ++ $(PATH_jpe)/test/common\ ++ $(PATH_jpe)/test/$(JPE_PLATFORM) ++ ++#------------------------------------------------------------------------------ ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------ ++ ++SRC_C_LIST = \ ++ drv_jpe_ctx.c\ ++ drv_jpe_dev.c\ ++ drv_jpe_module.c\ ++ drv_jpe_enc.c\ ++ jpe_test_i_sw.c\ ++ util_pattern.c\ ++ md5.c +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/pub/drv_jpe_io.h b/drivers/mstar/jpe2/drv/pub/drv_jpe_io.h +new file mode 100644 +index 00000000..578b05f3 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/pub/drv_jpe_io.h +@@ -0,0 +1,47 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __DRV_JPE_IO_H__ ++#define __DRV_JPE_IO_H__ ++ ++#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ ++#define IOC_JPE_VOID 0x20000000 /* no parameters */ ++#define IOC_JPE_OUT 0x40000000 /* copy out parameters */ ++#define IOC_JPE_IN 0x80000000 /* copy in parameters */ ++#define IOC_JPE_INOUT (IOC_JPE_IN|IOC_JPE_OUT) ++ ++#define _IO_JPE(x,y) (IOC_JPE_VOID|((x)<<8)|(y)) ++#define _IOR_JPE(x,y,t) (IOC_JPE_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++#define _IOW_JPE(x,y,t) (IOC_JPE_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++ ++//JPE IOC COMMANDS ++#define JPE_IOC_MAGIC 'J' ++// Initialize *pJpeInfo ++#define JPE_IOC_INIT _IO_JPE(JPE_IOC_MAGIC, 0) ++// Set up JPE RIU and fire JPE ++#define JPE_IOC_ENCODE_FRAME _IO_JPE(JPE_IOC_MAGIC, 1) ++// Get output buffer status ++#define JPE_IOC_GETBITS _IOR_JPE(JPE_IOC_MAGIC, 2, u32) ++// ++#define JPE_IOC_GET_CAPS _IOR_JPE(JPE_IOC_MAGIC, 3, u32) ++// ++#define JPE_IOC_SET_OUTBUF _IOR_JPE(JPE_IOC_MAGIC, 4, u32) ++ ++// 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++#define JPE_IOC_SET_CLOCKRATE _IOW_JPE(JPE_IOC_MAGIC, 5, u32) ++ ++#endif // __DRV_JPE_IO_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/pub/drv_jpe_io_st.h b/drivers/mstar/jpe2/drv/pub/drv_jpe_io_st.h +new file mode 100644 +index 00000000..1ccc5688 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/pub/drv_jpe_io_st.h +@@ -0,0 +1,141 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __JPE_DRV_IO_ST_H__ ++#define __JPE_DRV_IO_ST_H__ ++ ++#if defined(__linux__) ++typedef unsigned char u8; ++typedef unsigned short u16; ++typedef unsigned int u32; ++typedef unsigned long long u64; ++#endif // #if defined(__linux__) ++ ++// NOTE: JpeCfg_t and JpeEncOutbuf_t should sync with the definition in hal_jpe_ops.h ++typedef enum ++{ ++ JPE_IBUF_ROW_MODE = 0x0, ++ JPE_IBUF_FRAME_MODE = 0x1 ++} JpeInBufMode_e; ++ ++typedef enum ++{ ++ JPE_RAW_YUYV = 0x0, ++ JPE_RAW_YVYU = 0x1, ++ JPE_RAW_NV12 = 0x3, ++ JPE_RAW_NV21 = 0x4, ++} JpeRawFormat_e; ++ ++typedef enum ++{ ++ JPE_CODEC_JPEG = 0x1, ++ JPE_CODEC_H263I = 0x2, //! obsolete ++ JPE_CODEC_ENCODE_DCT = 0x4, //! obsolete ++} JpeCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_IDLE_STATE = 0, ++ JPE_BUSY_STATE = 1, ++ JPE_FRAME_DONE_STATE = 2, ++ JPE_OUTBUF_FULL_STATE = 3, ++ JPE_INBUF_FULL_STATE = 4 ++} JpeState_e; ++ ++typedef enum ++{ ++ JPE_IOC_RET_SUCCESS = 0, ++ JPE_IOC_RET_BAD_QTABLE = 1, ++ JPE_IOC_RET_BAD_QP = 2, ++ JPE_IOC_RET_BAD_BITSOFFSET = 3, ++ JPE_IOC_RET_BAD_BANKNUM = 4, ++ JPE_IOC_RET_BAD_INBUF = 5, ++ JPE_IOC_RET_BAD_OUTBUF = 6, ++ JPE_IOC_RET_BAD_NULLPTR = 7, ++ JPE_IOC_RET_BAD_BANKCNT = 8, ++ JPE_IOC_RET_BAD_LASTZZ = 9, ++ JPE_IOC_RET_UNKOWN_COMMAND = 10, ++ JPE_IOC_RET_BAD_VIRTUAL_MEM = 11, ++ JPE_IOC_RET_NEED_DRIVER_INIT = 12, ++ JPE_IOC_RET_FMT_NOT_SUPPORT = 13, ++ JPE_IOC_RET_HW_IS_RUNNING = 14, ++ JPE_IOC_RET_FAIL = 15 ++} JPE_IOC_RET_STATUS_e; ++ ++typedef enum ++{ ++ JPE_COLOR_PLAN_LUMA = 0, ++ JPE_COLOR_PLAN_CHROMA = 1, ++ JPE_COLOR_PLAN_MAX = 2 ++} JPE_COLOR_PLAN_e; ++ ++typedef struct ++{ ++ u32 u32JpeId; ++ u32 nRefYLogAddrAlign[2]; ++ u32 nRefCLogAddrAlign[2]; ++ u32 nOutBufSLogAddrAlign; ++ u8 nSclHandShakeSupport; ++ u8 nCodecSupport; ++ u8 nBufferModeSupport; ++} JpeCaps_t, *pJpeCaps; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; ++ unsigned long nOutputSize; ++ JpeState_e eState; ++} JpeBitstreamInfo_t, *pJpeBitstreamInfo; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nSize; ++} JpeBufInfo_t; ++ ++typedef struct ++{ ++ JpeInBufMode_e eInBufMode; ++ JpeRawFormat_e eRawFormat; ++ JpeCodecFormat_e eCodecFormat; ++ u32 nWidth; ++ u32 nHeight; ++ u16 YQTable[64]; ++ u16 CQTable[64]; ++ u16 nQScale; ++ JpeBufInfo_t InBuf[JPE_COLOR_PLAN_MAX]; ++ JpeBufInfo_t OutBuf; ++ u32 nJpeOutBitOffset; ++} JpeCfg_t; ++ ++ ++typedef struct JpeEncOutbuf_t ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; // Original buffer Size ++ unsigned long nOutputSize; // Output Size ++ JpeState_e eState; ++} JpeEncOutbuf_t; ++ ++ ++/* NOTE: remove below definition when move this file to linux-3.18\drivers\mstar\include\ */ ++#if defined(__I_SW__) || defined(__KERNEL__) ++#include "drv_jpe_io_st_kernel.h" ++#endif ++ ++#endif // __JPE_DRV_IO_ST_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/pub/drv_jpe_io_st_kernel.h b/drivers/mstar/jpe2/drv/pub/drv_jpe_io_st_kernel.h +new file mode 100644 +index 00000000..b5e28047 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/pub/drv_jpe_io_st_kernel.h +@@ -0,0 +1,110 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __JPE_DRV_IO_ST_KERNEL_H__ ++#define __JPE_DRV_IO_ST_KERNEL_H__ ++ ++#if defined(__KERNEL__) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++ ++#elif defined(__I_SW__) ++#include "sys_MsWrapper_cus_os_util.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#include "sys_MsWrapper_cus_os_mem.h" ++#include "sys_MsWrapper_cus_os_int_ctrl.h" ++#include "sys_MsWrapper_cus_os_int_pub.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_Rtk_Vmrtkho.h" ++#include "sys_sys_isw_uart.h" ++#include "hal_int_ctrl_pub.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "vm_types.ht" ++#include "cam_os_wrapper.h" ++ ++#endif // if defined(__KERNEL__) ++ ++#define JPE_STREAM_NR 5 ++ ++typedef struct JpeDev_t JpeDev_t; ++typedef struct JpeCtx_t JpeCtx_t; ++ ++struct JpeCtx_t ++{ ++ void (*release)(void*); ++ CamOsMutex_t m_stream; ++ ++ // TODO: is it possible to ignore below 2 arguments? ++ JpeCfg_t tJpeCfg; ++ JpeEncOutbuf_t tEncOutBuf; ++ ++ JpeDev_t* p_device; ++ void* p_handle; ++ int i_state; ++ int i_index; ++ ++ unsigned short nClkSelect; ++ ++ /* user data buffer */ ++ unsigned char* p_usrdt; ++}; ++ ++typedef struct JpeDevUser_t ++{ ++ struct JpeCtx_t* pCtx; ++} JpeDevUser_t; ++ ++ ++struct JpeDev_t ++{ ++#if defined(__KERNEL__) ++ struct platform_device *pPlatformDev; // Platform device ++ struct cdev tCharDev; // Character device ++ struct device tDevice; ++ struct device *pDevice; ++#define JPE_CLOCKS_NR 4 ++ struct clk *pClock[JPE_CLOCKS_NR]; ++ int nClockIdx; ++ int nClockRate; ++ int nRefCount; // Reference count, how many file instances opened ++ unsigned int irq; // IRQ number ++#endif ++ ++ CamOsMutex_t m_mutex; ++ CamOsTsem_t m_wqh; ++ CamOsTsem_t tGetBitsSem; ++ ++ JpeDevUser_t user[JPE_STREAM_NR]; ++ ++ /* ... */ ++ void* p_asicip; ++ ++ int i_state; ++ int i_users; ++ /* statistic */ ++ int i_counts[JPE_STREAM_NR][5]; ++ int i_thresh; ++}; ++ ++#endif // __JPE_DRV_IO_ST_KERNEL_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/pub/drv_jpe_module.h b/drivers/mstar/jpe2/drv/pub/drv_jpe_module.h +new file mode 100644 +index 00000000..92a0375f +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/pub/drv_jpe_module.h +@@ -0,0 +1,38 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __DRV_JPE_MODULE_H__ ++#define __DRV_JPE_MODULE_H__ ++ ++#include "drv_jpe_io.h" ++#include "drv_jpe_io_st_kernel.h" ++ ++#define JPE_OFFSET 0x00264000 ++ ++#if defined(__I_SW__) // #if defined(__I_SW__) ++JpeDev_t* JpeProbe(JpeDev_t* pDev); ++JpeCtx_t* JpeOpen(JpeDev_t* pDev, JpeCtx_t* pCtx); ++JPE_IOC_RET_STATUS_e JpeRelease(JpeDev_t* pDev, JpeCtx_t* pCtx); ++JPE_IOC_RET_STATUS_e JpeRemove(JpeDev_t* pDev); ++JPE_IOC_RET_STATUS_e JpeCtxActions(JpeCtx_t*, unsigned int, void*); ++ ++#elif defined(__KERNEL__) ++JPE_IOC_RET_STATUS_e JpeCtxActions(JpeCtx_t*, unsigned int, void*); ++ ++#endif // #if defined(__I_SW__) ++ ++#endif // __DRV_JPE_MODULE_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/pub/linux/mdrv_jpe_io.h b/drivers/mstar/jpe2/drv/pub/linux/mdrv_jpe_io.h +new file mode 100644 +index 00000000..e5d9bf3c +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/pub/linux/mdrv_jpe_io.h +@@ -0,0 +1,44 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_JPE_IO_H_ ++#define _MDRV_JPE_IO_H_ ++ ++#define IOCPARM_MASK 0x7f /* parameters must be < 128 bytes */ ++#define IOC_JPE_VOID 0x20000000 /* no parameters */ ++#define IOC_JPE_OUT 0x40000000 /* copy out parameters */ ++#define IOC_JPE_IN 0x80000000 /* copy in parameters */ ++#define IOC_JPE_INOUT (IOC_JPE_IN|IOC_JPE_OUT) ++ ++#define _IO_JPE(x,y) (IOC_JPE_VOID|((x)<<8)|(y)) ++#define _IOR_JPE(x,y,t) (IOC_JPE_OUT|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++#define _IOW_JPE(x,y,t) (IOC_JPE_IN|(((long)sizeof(t)&IOCPARM_MASK)<<16)|((x)<<8)|(y)) ++ ++//JPE IOC COMMANDS ++#define JPE_IOC_MAGIC 'J' ++// Initialize *pJpeInfo ++#define JPE_IOC_INIT _IO_JPE(JPE_IOC_MAGIC, 0) ++// Set up JPE RIU and fire JPE ++#define JPE_IOC_ENCODE_FRAME _IO_JPE(JPE_IOC_MAGIC, 1) ++// Get output buffer status ++#define JPE_IOC_GETBITS _IOR_JPE(JPE_IOC_MAGIC, 2, __u32) ++// ++#define JPE_IOC_GET_CAPS _IOR_JPE(JPE_IOC_MAGIC, 3, __u32) ++// ++#define JPE_IOC_SET_OUTBUF _IOR_JPE(JPE_IOC_MAGIC, 4, __u32) ++ ++#endif // _MDRV_JPE_IO_H_ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/pub/linux/mdrv_jpe_io_st.h b/drivers/mstar/jpe2/drv/pub/linux/mdrv_jpe_io_st.h +new file mode 100644 +index 00000000..d84fbcc0 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/pub/linux/mdrv_jpe_io_st.h +@@ -0,0 +1,134 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2009-2010 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_JPE_IO_ST_H_ ++#define _MDRV_JPE_IO_ST_H_ ++ ++#include ++#include ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ JPE_IBUF_ROW_MODE = 0x0, ++ JPE_IBUF_FRAME_MODE = 0x1 ++} JpeInBufMode_e; ++ ++typedef enum ++{ ++ JPE_RAW_YUYV = 0x0, ++ JPE_RAW_YVYU = 0x1, ++ JPE_RAW_NV12 = 0x3, ++ JPE_RAW_NV21 = 0x4, ++} JpeRawFormat_e; ++ ++typedef enum ++{ ++ JPE_CODEC_JPEG = 0x1, ++ JPE_CODEC_H263I = 0x2, //! obsolete ++ JPE_CODEC_ENCODE_DCT = 0x4, //! obsolete ++} JpeCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_IDLE_STATE = 0, ++ JPE_BUSY_STATE = 1, ++ JPE_FRAME_DONE_STATE = 2, ++ JPE_OUTBUF_FULL_STATE = 3, ++ JPE_INBUF_FULL_STATE = 4 ++} JpeState_e; ++ ++typedef enum ++{ ++ JPE_IOC_RET_SUCCESS = 0, ++ JPE_IOC_RET_BAD_QTABLE = 1, ++ JPE_IOC_RET_BAD_QP = 2, ++ JPE_IOC_RET_BAD_BITSOFFSET = 3, ++ JPE_IOC_RET_BAD_BANKNUM = 4, ++ JPE_IOC_RET_BAD_INBUF = 5, ++ JPE_IOC_RET_BAD_OUTBUF = 6, ++ JPE_IOC_RET_BAD_NULLPTR = 7, ++ JPE_IOC_RET_BAD_BANKCNT = 8, ++ JPE_IOC_RET_BAD_LASTZZ = 9, ++ JPE_IOC_RET_UNKOWN_COMMAND = 10, ++ JPE_IOC_RET_BAD_VIRTUAL_MEM = 11, ++ JPE_IOC_RET_NEED_DRIVER_INIT = 12, ++ JPE_IOC_RET_FMT_NOT_SUPPORT = 13, ++ JPE_IOC_RET_HW_IS_RUNNING = 14, ++ JPE_IOC_RET_FAIL = 15 ++} JPE_IOC_RET_STATUS_e; ++ ++typedef enum ++{ ++ JPE_COLOR_PLAN_LUMA = 0, ++ JPE_COLOR_PLAN_CHROMA = 1, ++ JPE_COLOR_PLAN_MAX = 2 ++} JPE_COLOR_PLAN_e; ++ ++typedef struct ++{ ++ __u32 __u32JpeId; ++ __u32 nRefYLogAddrAlign[2]; ++ __u32 nRefCLogAddrAlign[2]; ++ __u32 nOutBufSLogAddrAlign; ++ __u8 nSclHandShakeSupport; ++ __u8 nCodecSupport; ++ __u8 nBufferModeSupport; ++} JpeCaps_t, *pJpeCaps; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; ++ unsigned long nOutputSize; ++ JpeState_e eState; ++} JpeBitstreamInfo_t, *pJpeBitstreamInfo; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nSize; ++} JpeBufInfo_t; ++ ++typedef struct ++{ ++ JpeInBufMode_e eInBufMode; ++ JpeRawFormat_e eRawFormat; ++ JpeCodecFormat_e eCodecFormat; ++ __u32 nWidth; ++ __u32 nHeight; ++ __u16 YQTable[64]; ++ __u16 CQTable[64]; ++ __u16 nQScale; ++ JpeBufInfo_t InBuf[JPE_COLOR_PLAN_MAX]; ++ JpeBufInfo_t OutBuf; ++ __u32 nJpeOutBitOffset; ++} JpeCfg_t; ++ ++ ++typedef struct JpeEncOutbuf_t ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; // Original buffer Size ++ unsigned long nOutputSize; // Output Size ++ JpeState_e eState; ++} JpeEncOutbuf_t; ++ ++#endif //_MDRV_JPE_IO_ST_H_ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/src/common/cam_os_wrapper.c b/drivers/mstar/jpe2/drv/src/common/cam_os_wrapper.c +new file mode 100644 +index 00000000..f57c0ff7 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/src/common/cam_os_wrapper.c +@@ -0,0 +1,1806 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.c ++/// @brief Cam OS Wrapper Source File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#ifdef CAM_OS_RTK ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "sys_sys.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#include "sys_MsWrapper_cus_os_util.h" ++#include "sys_sys_isw_uart.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef void *CamOsThreadEntry_t(void *); ++ ++typedef struct ++{ ++ MsTaskId_e eHandleObj; ++ CamOsThreadEntry_t *ptEntry; ++ void *pArg; ++ Ms_Flag_t tExitFlag; ++ void *pStack; ++} CamOsThreadHandleRtk_t, *pCamOsThreadHandleRtk; ++ ++typedef struct ++{ ++ Ms_Flag_t tFlag; /* or semaphore if supported */ ++ Ms_Mutex_t tMutex; ++ u32 nSemval; ++} CamOsTsemRtk_t, *pCamOsTsemRtk; ++ ++static Ms_Mutex_t _gtMemLock; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(Ms_Flag_t), "CamOsMutex_t size define not enough!"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemRtk_t), "CamOsTsem_t size define not enough!"); ++ ++#elif defined(CAM_OS_LINUX_USER) ++#define _GNU_SOURCE ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_verchk.h" ++#include ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++typedef struct ++{ ++ pthread_cond_t tCondition; ++ pthread_mutex_t tMutex; ++ u32 nSemval; ++} CamOsTsemLU_t, *pCamOsTsemLU; ++ ++// TODO remove extern pthread_setname_np and pthread_getname_np ++extern int pthread_setname_np(pthread_t tTargetThread, const char *szTargetName); ++extern int pthread_getname_np(pthread_t tThread, char *szName, size_t nLen); ++ ++static pthread_mutex_t _gtMemLock = PTHREAD_MUTEX_INITIALIZER; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(pthread_mutex_t), "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLU_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef struct ++{ ++ struct semaphore tSem; ++ struct mutex tMutex; ++ u32 nSemval; ++} CamOsTsemLK_t, *pCamOsTsemLK; ++ ++typedef s32 CamOsThreadEntry_t(void *); ++ ++struct mutex _gtMemLock; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(struct mutex), "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLK_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++ ++#endif ++ ++typedef struct MemoryList_t ++{ ++ struct CamOsListHead_t tList; ++ void *pPtr; ++ void *pMemifoPtr; ++ char *szName; ++} MemoryList_t; ++ ++static MemoryList_t _gtMemList; ++ ++static s32 _gnDmemDbgListInited = 0; ++ ++void CamOsDebug(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ va_list tArgs; ++ char nLineStr[256]; ++ ++ va_start(tArgs, szFmt); ++ vsprintf(nLineStr, szFmt, tArgs); ++ send_msg(nLineStr); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_USER) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vfprintf(stderr, szFmt, tArgs); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vprintk(szFmt, tArgs); ++ va_end(tArgs); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static char* _CamOsAdvance(char* pBuf) { ++ ++ char* pNewBuf = pBuf; ++ ++ /* Skip over nonwhite space */ ++ while ((*pNewBuf != ' ') && (*pNewBuf != '\t') && ++ (*pNewBuf != '\n') && (*pNewBuf != '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ /* Skip white space */ ++ while ((*pNewBuf == ' ') || (*pNewBuf == '\t') || ++ (*pNewBuf == '\n') || (*pNewBuf == '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ return pNewBuf; ++} ++ ++static s32 _CamOsVsscanf(char* szBuf, char* szFmt, va_list tArgp) ++{ ++ char* pFmt; ++ char* pBuf; ++ char* pnSval; ++ int* pnIval; ++ double* pdbDval; ++ float* pfFval; ++ s32 nCount = 0; ++ ++ pBuf = szBuf; ++ ++ for (pFmt = szFmt; *pFmt; pFmt++) { ++ if (*pFmt == '%') ++ switch (*++pFmt) { ++ case 'd': ++ pnIval = va_arg(tArgp, int *); ++ sscanf(pBuf, "%d", pnIval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ case 'f': ++ pfFval = va_arg(tArgp, float *); ++ sscanf(pBuf, "%f", pfFval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ case 'l': ++ pdbDval = va_arg(tArgp, double *); ++ sscanf(pBuf, "%lf", pdbDval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ case 's': ++ pnSval = va_arg(tArgp, char *); ++ sscanf(pBuf, "%s", pnSval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ default: ++ break; ++ } ++ } ++ return nCount; ++} ++ ++static s32 _CamOsVfscanf(const char *szFmt, va_list tArgp) ++{ ++ s32 nCount; ++ ++ nCount = _CamOsVsscanf(wait_for_command(), (char *)szFmt, tArgp); ++ return nCount; ++} ++#endif ++ ++s32 CamOsScanf(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start (tArgp, szFmt); ++ nCount = _CamOsVfscanf (szFmt, tArgp); ++ va_end (tArgp); ++ UartSendTrace("\n"); ++ return nCount; ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start (tArgp, szFmt); ++ nCount = vfscanf (stdin, szFmt, tArgp); ++ va_end (tArgp); ++ return nCount; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++} ++ ++s32 CamOsGetChar(void) ++{ ++#ifdef CAM_OS_RTK ++ s32 Ret; ++ Ret = get_char(); ++ UartSendTrace("\n"); ++ return Ret; ++#elif defined(CAM_OS_LINUX_USER) ++ return getchar(); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++} ++ ++void CamOsMsSleep(u32 nMsec) ++{ ++#ifdef CAM_OS_RTK ++ MsSleep(RTK_MS_TO_TICK(nMsec)); ++#elif defined(CAM_OS_LINUX_USER) ++ usleep((useconds_t)nMsec * 1000); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ msleep(nMsec); ++#endif ++} ++ ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ u32 nTmp = VM_RTK_TICK_TO_MS(MsGetOsTick()); ++ ptRes->nSec = nTmp / 1000; ++ ptRes->nNanoSec = (nTmp % 1000) * 1000000; ++#elif defined(CAM_OS_LINUX_USER) ++ clock_gettime(CLOCK_MONOTONIC, (struct timespec *)ptRes); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ getrawmonotonic((struct timespec *)ptRes); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static void _CamOSThreadEntry(void *pEntryData) ++{ ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)pEntryData; ++ ++ ptTaskHandle->ptEntry(ptTaskHandle->pArg); ++ ++ MsFlagSetbits(&ptTaskHandle->tExitFlag, 0x00000001); ++} ++ ++static void _CamOsThreadEmptyParser(vm_msg_t *ptMessage) ++{ ++ ++} ++#endif ++ ++CamOsRet_e CamOsThreadCreate(CamOsThread *pThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = NULL; ++ MsTaskCreateArgs_t tTaskArgs = {0}; ++ u32 nPrio = 100; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority >= 0) && (ptAttrb->nPriority < 100)) ++ { ++ nPrio = ptAttrb->nPriority * 2; ++ } ++ nStkSz = (ptAttrb->nStackSize)? ptAttrb->nStackSize : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ } ++ ++ *pThread = (void*) - 1; ++ do ++ { ++ if(!(ptTaskHandle = MsCallocateMem(sizeof(CamOsThreadHandleRtk_t)))) ++ { ++ CamOsDebug("%s : Allocate ptHandle fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ ptTaskHandle->ptEntry = pfnStartRoutine; ++ ptTaskHandle->pArg = pArg; ++ if(!(ptTaskHandle->pStack = MsAllocateMem((nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT))) ++ { ++ CamOsDebug("%s : Allocate stack fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ memset(&ptTaskHandle->tExitFlag, 0, sizeof(Ms_Flag_t)); ++ MsFlagInit(&ptTaskHandle->tExitFlag); ++ //VEN_TEST_CHECK_RESULT((pTaskHandle->exit_flag.FlagId >> 0) && (pTaskHandle->exit_flag.FlagState == RTK_FLAG_INITIALIZED)); ++ ++ tTaskArgs.Priority = (nPrio >= 0 && nPrio <= 200) ? nPrio : 100; ++ tTaskArgs.StackSize = (nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ tTaskArgs.pStackTop = (u32*)ptTaskHandle->pStack; ++ tTaskArgs.AppliInit = &_CamOSThreadEntry; ++ tTaskArgs.AppliParser = _CamOsThreadEmptyParser; ++ tTaskArgs.pInitArgs = ptTaskHandle; ++ tTaskArgs.TaskId = &ptTaskHandle->eHandleObj; ++ tTaskArgs.ImmediatelyStart = TRUE; ++ tTaskArgs.TimeSliceMax = 10; ++ tTaskArgs.TimeSliceLeft = 10; ++ strcpy(tTaskArgs.TaskName, "CamOS"); ++ ++ if(MS_OK != MsCreateTask(&tTaskArgs)) ++ { ++ CamOsDebug("%s : Create task fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *pThread = ptTaskHandle; ++ } ++ while(0); ++ ++ if(!*pThread) ++ { ++ if(ptTaskHandle) ++ { ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsReleaseMemory(ptTaskHandle); ++ } ++ } ++ ++ //CamOsDebug("%s get taskid: %d priority: %d\n\r", __FUNCTION__, (u32)pTaskHandle->eHandleObj, TaskArgs.Priority); ++#elif defined(CAM_OS_LINUX_USER) ++ struct sched_param tSched; ++ pthread_t tThreadHandle = NULL; ++ pthread_attr_t tAttr; ++ if(ptAttrb != NULL) ++ { ++ pthread_attr_init(&tAttr); ++ pthread_attr_getschedparam(&tAttr, &tSched); ++ pthread_attr_setinheritsched(&tAttr, PTHREAD_EXPLICIT_SCHED); ++ pthread_attr_setschedpolicy(&tAttr, SCHED_RR); ++ ++ if((ptAttrb->nPriority >= 0) && (ptAttrb->nPriority < 100)) ++ { ++ tSched.sched_priority = ptAttrb->nPriority; ++ } ++ ++ pthread_attr_setschedparam(&tAttr, &tSched); ++ if(0 != ptAttrb->nStackSize) ++ { ++ pthread_attr_setstacksize(&tAttr, (size_t) ptAttrb->nStackSize); ++ eRet = CAM_OS_FAIL; ++ } ++ pthread_create(&tThreadHandle, &tAttr, pfnStartRoutine, pArg); ++ pthread_attr_destroy(&tAttr); ++ } ++ else ++ { ++ pthread_create(&tThreadHandle, NULL, pfnStartRoutine, pArg); ++ } ++ ++ *pThread = (CamOsThread *)tThreadHandle; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle; ++ struct sched_param tSche = { .sched_priority = 0 }; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority >= 0) && (ptAttrb->nPriority < 100)) ++ { ++ tSche.sched_priority = ptAttrb->nPriority; ++ } ++ nStkSz = ptAttrb->nStackSize; ++ } ++ tpThreadHandle = kthread_run((CamOsThreadEntry_t *)pfnStartRoutine, pArg, "CAMOS"); ++ sched_setscheduler(tpThreadHandle, SCHED_RR, &tSche); ++ *pThread = (CamOsThread *)tpThreadHandle; ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadJoin(CamOsThread thread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)thread; ++ if(ptTaskHandle) ++ { ++ MsFlagWait(&ptTaskHandle->tExitFlag, 0x00000001, RTK_FLAG_WAITMODE_AND | RTK_FLAG_WAITMODE_CLR); ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsDeleteTask(ptTaskHandle->eHandleObj); ++ ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsReleaseMemory(ptTaskHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_join(tThreadHandle, NULL); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadStop(CamOsThread thread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle = (struct task_struct *)thread; ++ if(tpThreadHandle) ++ { ++ if(0 != kthread_stop((struct task_struct *)thread)) ++ { ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadShouldStop(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(kthread_should_stop()) ++ { ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_FAIL; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadSetName(CamOsThread thread, const char *szName) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ // TODO RTK not support set task name dynamic. ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_setname_np(tThreadHandle, szName); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadGetName(CamOsThread thread, const char *szName, u32 nLen) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_getname_np(tThreadHandle, (char *)szName, nLen); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++u32 CamOsThreadGetID() ++{ ++#ifdef CAM_OS_RTK ++ return MsCurrTask(); ++#elif defined(CAM_OS_LINUX_USER) ++ return (u32)syscall(__NR_gettid); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return current->tgid; ++#endif ++} ++ ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsInitMutex(ptHandle)) ++ { ++ CamOsDebug("%s : Init mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != pthread_mutex_init(ptHandle, NULL)) ++ { ++ fprintf(stderr, "%s : Init mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_init(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ // Do Nothing in RTK ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ pthread_mutex_destroy(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsMutexLock(ptHandle)) ++ { ++ CamOsDebug("%s : Lock mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != (nErr = pthread_mutex_lock(ptHandle))) ++ { ++ fprintf(stderr, "%s : Lock mutex fail, err %d\n\r", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_lock(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsMutexUnlock(ptHandle)) ++ { ++ CamOsDebug("%s : Unlock mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != (nErr = pthread_mutex_unlock(ptHandle))) ++ { ++ fprintf(stderr, "%s : Unlock mutex fail, err %d\n\r", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_unlock(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagInit(&ptHandle->tFlag); ++ MsInitMutex(&ptHandle->tMutex); ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(0 != pthread_cond_init(&ptHandle->tCondition, NULL)) ++ { ++ return CAM_OS_FAIL; ++ } ++ if(0 != pthread_mutex_init(&ptHandle->tMutex, NULL)) ++ { ++ return CAM_OS_FAIL; ++ } ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ sema_init(&ptHandle->tSem, nVal); ++ mutex_init(&ptHandle->tMutex); ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagDestroy(&ptHandle->tFlag); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_cond_destroy(&ptHandle->tCondition); ++ pthread_mutex_destroy(&ptHandle->tMutex); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++void CamOsTsemUp(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ MsMutexUnlock(&ptHandle->tMutex); ++ MsFlagSetbits(&ptHandle->tFlag, 0x00000001); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ mutex_unlock(&ptHandle->tMutex); ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemDown(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ MsMutexUnlock(&ptHandle->tMutex); ++ MsFlagWait(&ptHandle->tFlag, 0x00000001, MS_FLAG_WAITMODE_OR); ++ MsMutexLock(&ptHandle->tMutex); ++ } ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ MsMutexUnlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ } ++ ptHandle->nSemval--; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ down(&ptHandle->tSem); ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval--; ++ mutex_unlock(&ptHandle->tMutex); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ MsMutexUnlock(&ptHandle->tMutex); ++ nErr = MsFlagTimedWait(&ptHandle->tFlag, 1, (MS_FLAG_WAITMODE_OR), RTK_MS_TO_TICK(nMsec)); ++ /*time out*/ ++ MsMutexLock(&ptHandle->tMutex); ++ if(!nErr) ++ { ++ break; ++ } ++ } ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ MsMutexUnlock(&ptHandle->tMutex); ++ if(!nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ struct timeval tCurrTime; ++ u32 nMicDelay; ++ ++ if(ptHandle) ++ { ++ gettimeofday(&tCurrTime, NULL); ++ /** convert timeval to timespec and add delay in milliseconds for the timeout */ ++ nMicDelay = ((nMsec * 1000 + tCurrTime.tv_usec)); ++ tFinalTime.tv_sec = tCurrTime.tv_sec + (nMicDelay / 1000000); ++ tFinalTime.tv_nsec = (nMicDelay % 1000000) * 1000; ++ pthread_mutex_lock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ if(nErr != 0) ++ { ++ ptHandle->nSemval--; ++ } ++ } ++ ptHandle->nSemval--; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ eRet = CAM_OS_OK; ++ else if(nErr == ETIMEDOUT) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec)); ++ mutex_lock(&ptHandle->tMutex); ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ mutex_unlock(&ptHandle->tMutex); ++ if(nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemSignal(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagSetbits(&ptHandle->tFlag, 0x00000001); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemWait(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagWait(&ptHandle->tFlag, 0x00000001, MS_FLAG_WAITMODE_OR); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ down(&ptHandle->tSem); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemTimedWait(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = MsFlagTimedWait(&ptHandle->tFlag, 1, (MS_FLAG_WAITMODE_OR), RTK_MS_TO_TICK(nMsec)); ++ if(!nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ struct timeval tCurrTime; ++ u32 nMicDelay; ++ ++ if(ptHandle) ++ { ++ gettimeofday(&tCurrTime, NULL); ++ /** convert timeval to timespec and add delay in milliseconds for the timeout */ ++ nMicDelay = ((nMsec * 1000 + tCurrTime.tv_usec)); ++ tFinalTime.tv_sec = tCurrTime.tv_sec + (nMicDelay / 1000000); ++ tFinalTime.tv_nsec = (nMicDelay % 1000000) * 1000; ++ ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ eRet = CAM_OS_OK; ++ else if(nErr == ETIMEDOUT) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec)); ++ if(nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++u32 CamOsTsemGetValue(CamOsTsem_t *ptTsem) ++{ ++ s32 eRet = 0; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemReset(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ MsMutexUnlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ sema_init(&ptHandle->tSem, 0); ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ mutex_unlock(&ptHandle->tMutex); ++ } ++#endif ++} ++ ++void* CamOsMemAlloc(u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsAllocateMem(nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return malloc(nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return kzalloc(nSize, GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemCalloc(u32 nNum, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsCallocateMem(nNum * nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return calloc(nNum, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return kzalloc(nSize, GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemRealloc(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsMemoryReAllocate(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return realloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ void *pAddr = kzalloc(nSize, GFP_KERNEL); ++ if(pPtr && pAddr) ++ { ++ memcpy(pAddr, pPtr, nSize); ++ kfree(pPtr); ++ } ++ return pAddr; ++#endif ++} ++ ++void CamOsMemRelease(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ if(pPtr) ++ { ++ MsReleaseMemory(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(pPtr) ++ { ++ free(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(pPtr) ++ { ++ kfree(pPtr); ++ } ++#endif ++} ++ ++static s32 _CheckDmemInfoListInited(void) ++{ ++#ifdef CAM_OS_RTK ++ if(!_gnDmemDbgListInited) ++ { ++ if(CUS_OS_OK != MsInitMutex(&_gtMemLock)) ++ { ++ CamOsDebug("%s : Init mutex fail\n\r", __FUNCTION__); ++ } ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(!_gnDmemDbgListInited) ++ { ++ pthread_mutex_init(&_gtMemLock, NULL); ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(!_gnDmemDbgListInited) ++ { ++ mutex_init(&_gtMemLock); ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#endif ++ ++ return 0; ++} ++ ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppUserPtr, ++ u32 *pMiuAddr, ++ u64 *lpPhysAddr) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ u8 nAllocSucc = TRUE; ++ *ppUserPtr = MsAllocateNonCacheMemExt(nSize, 12); ++ nAllocSucc &= MsIsHeapMemory(*ppUserPtr); ++ ++ if((u32)*ppUserPtr & ((1 << 6) - 1)) ++ { ++ nAllocSucc &= FALSE; ++ MsReleaseMemory(*ppUserPtr); ++ } ++ ++ if(nAllocSucc == TRUE) ++ { ++ *lpPhysAddr = (u32)MsVA2PA(*ppUserPtr); ++ *pMiuAddr = (u32) * lpPhysAddr - (u32)&Image__RAM__Base; ++ } ++ else ++ { ++ *ppUserPtr = 0; ++ *lpPhysAddr = (u64)0; ++ *pMiuAddr = 0; ++ eRet = CAM_OS_FAIL; ++ } ++ ++ /*CamOsDebug("%s 0x%08X 0x%08X 0x%08X\r\n", ++ __FUNCTION__, ++ (u32)*ppUserPtr, ++ (u32)*phys_addr, ++ (u32)*miu_addr);*/ ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ MemoryList_t* ptNewEntry = (MemoryList_t*) MsAllocateMem(sizeof(MemoryList_t)); ++ ptNewEntry->pPtr = *ppUserPtr; ++ ptNewEntry->pMemifoPtr = NULL; ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysFd = -1; ++ s32 nMemFd = -1; ++ MSYS_DMEM_INFO * ptMsysMem = NULL; ++ unsigned char* pMmapPtr = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ fprintf(stderr, "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ break; ++ } ++ ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/mem failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ ptMsysMem = (MSYS_DMEM_INFO *) malloc(sizeof(MSYS_DMEM_INFO)); ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ FILL_VERCHK_TYPE(*ptMsysMem, ptMsysMem->VerChk_Version, ++ ptMsysMem->VerChk_Size, IOCTL_MSYS_VERSION); ++ ++ ptMsysMem->length = nSize; ++ snprintf(ptMsysMem->name, sizeof(ptMsysMem->name), "%s", szName); ++ ++ if(ioctl(nMsysFd, IOCTL_MSYS_REQUEST_DMEM, ptMsysMem)) ++ { ++ ptMsysMem->length = 0; ++ fprintf(stderr, "%s [%s][%d]Request Direct Memory Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ tAddrInfo.addr = ptMsysMem->phys; ++ *lpPhysAddr = ptMsysMem->phys; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s [%s][%d]IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ *pMiuAddr = (u32)tAddrInfo.addr; ++ pMmapPtr = mmap(0, ptMsysMem->length, PROT_READ | PROT_WRITE, MAP_SHARED, ++ nMemFd, ptMsysMem->phys); ++ if(pMmapPtr == (void *) - 1) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s failed!! physAddr<0x%x> size<0x%x> errno<%d, %s> \r\n", ++ __FUNCTION__, ++ (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length, errno, strerror(errno)); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ *ppUserPtr = pMmapPtr; ++ ++ fprintf(stderr, "%s <%s> physAddr<0x%x> size<%d> \r\n", ++ __FUNCTION__, ++ szName, (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ MemoryList_t* tpNewEntry = (MemoryList_t*) malloc(sizeof(MemoryList_t)); ++ tpNewEntry->pPtr = pMmapPtr; ++ tpNewEntry->pMemifoPtr = (void *) ptMsysMem; ++ tpNewEntry->szName = strdup(szName); ++ CAM_OS_LIST_ADD_TAIL(&(tpNewEntry->tList), &_gtMemList.tList); ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++ if(nMemFd >= 0) ++ { ++ close(nMemFd); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *ptDmem = NULL; ++ MemoryList_t* ptNewEntry; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ printk(KERN_WARNING "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ break; ++ } ++ ++ if(0 == (ptDmem = (MSYS_DMEM_INFO *)kzalloc(sizeof(MSYS_DMEM_INFO), GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s kzalloc MSYS_DMEM_INFO fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ snprintf(ptDmem->name, 15, szName); ++ ptDmem->length = nSize; ++ ++ if(0 != msys_request_dmem(ptDmem)) ++ { ++ printk(KERN_WARNING "%s msys_request_dmem fail\n", __FUNCTION__); ++ kfree(ptDmem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *ppUserPtr = (void *)(u32)ptDmem->phys; ++ *pMiuAddr = Chip_Phys_to_MIU(ptDmem->phys); ++ *lpPhysAddr = ptDmem->phys; ++ ++ printk(KERN_INFO "%s <%s> physAddr<0x%08X> size<%d> \r\n", ++ __FUNCTION__, ++ szName, (u32)ptDmem->phys, ++ (u32)ptDmem->length); ++ ++ mutex_lock(&_gtMemLock); ++ ptNewEntry = (MemoryList_t*) kzalloc(sizeof(MemoryList_t), GFP_KERNEL); ++ ptNewEntry->pPtr = (void *)(u32)ptDmem->phys; ++ ptNewEntry->pMemifoPtr = (void *) ptDmem; ++ ptNewEntry->szName = (char *)kzalloc(strlen(szName), GFP_KERNEL); ++ strcpy(ptNewEntry->szName, szName); ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemRelease(void* pUserPtr, u32 nSize) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++#ifdef CAM_OS_RTK ++ if(pUserPtr) ++ { ++ MsReleaseMemory(pUserPtr); ++ CamOsDebug("%s do release\n\r", __FUNCTION__); ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ free(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ free(ptTmp); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysfd = -1; ++ s32 nErr = 0; ++ MSYS_DMEM_INFO *pMsysMem = NULL; ++ ++ do ++ { ++ if(0 > (nMsysfd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ nErr = munmap(pUserPtr, nSize); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <%p> size<%d> err<%d> errno<%d, %s> \r\n", ++ __FUNCTION__, ++ pUserPtr, (u32)nSize, nErr, errno, strerror(errno)); ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ pMsysMem = (MSYS_DMEM_INFO *) ptTmp->pMemifoPtr; ++ break; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(pMsysMem == NULL) ++ { ++ fprintf(stderr, "%s find Msys_DMEM_Info node failed!! <%p> \r\n", __FUNCTION__, pUserPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(ioctl(nMsysfd, IOCTL_MSYS_RELEASE_DMEM, pMsysMem)) ++ { ++ fprintf(stderr, "%s : IOCTL_MSYS_RELEASE_DMEM error physAddr<0x%x>\n", __FUNCTION__, (u32)pMsysMem->phys); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ if(pMsysMem) ++ { ++ free(pMsysMem); ++ pMsysMem = NULL; ++ } ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ free(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ free(ptTmp); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysfd >= 0) ++ { ++ close(nMsysfd); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *tpDmem = NULL; ++ ++ do ++ { ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ printk("search tmp->ptr: %08X %s\n", (u32)ptTmp->pPtr, ptTmp->szName); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ tpDmem = ptTmp->pMemifoPtr; ++ printk("search(2) pdmem->name: %s\n", tpDmem->name); ++ break; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(tpDmem == NULL) ++ { ++ printk(KERN_WARNING "%s find Msys_DMEM_Info node failed!! <%p> \r\n", __FUNCTION__, pUserPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ msys_release_dmem(tpDmem); ++ ++ if(tpDmem) ++ { ++ kfree(tpDmem); ++ tpDmem = NULL; ++ } ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ kfree(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ kfree(ptTmp); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemStat(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++#ifdef CAM_OS_RTK ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ CamOsDebug("%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ fprintf(stderr, "%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ printk(KERN_WARNING "%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_set)(const char *szKey, const char *szValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error \n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set = dlsym(pLibHandle, "property_set"); ++ if(NULL == dlsym_property_set) ++ { ++ fprintf(stderr, "%s : dlsym property_set failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set(szKey, szValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsPropertyGet(const char *szKey, char *szValue, const char *szDefaultValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_get)(const char *szKey, char *szValue, const char *szDefaultValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error \n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ dlsym_property_get = dlsym(pLibHandle, "property_get"); ++ if(NULL == dlsym_property_get) ++ { ++ fprintf(stderr, "%s : dlsym property_get failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_get(szKey, szValue, szDefaultValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/src/common/drv_jpe_ctx.c b/drivers/mstar/jpe2/drv/src/common/drv_jpe_ctx.c +new file mode 100644 +index 00000000..1430781f +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/src/common/drv_jpe_ctx.c +@@ -0,0 +1,504 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "hal_jpe_ios.h" ++#include "hal_jpe_ops.h" ++#include "drv_jpe_io.h" ++#include "drv_jpe_io_st_kernel.h" ++#include "_drv_jpe_dev.h" ++ ++#if defined(__linux__) ++#include ++#else ++static unsigned long copy_from_user(void *to, const void *from, unsigned long n) ++{ ++ memcpy(to, from, n); ++ return 0; ++} ++static unsigned long copy_to_user (void * to, const void * from, unsigned long n) ++{ ++ memcpy(to, from, n); ++ return 0; ++} ++ ++#endif ++ ++//============================================================================= ++// Description: ++// IOCTL handler for JPE_IOC_SET_OUTBUF ++// Author: ++// Albert.Liao. ++// Input: ++// pCtx: JPEG user context ++// arg: a pointer of JpeBufInfo_t from user-space ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++static JPE_IOC_RET_STATUS_e _JpeCtxSetOutputBuffer(JpeCtx_t* pCtxIn, unsigned long nArg) ++{ ++ int nRet; ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ JpeCtx_t* pCtx = pCtxIn; ++ JpeCfg_t* pJpeCfg = &pCtx->tJpeCfg; ++ JpeBufInfo_t tOutBuf; ++ ++ if((!pJpeCfg) || (0 == nArg)) ++ { ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ CamOsMutexLock(&pCtx->m_stream); ++ nRet = (int)copy_from_user(&tOutBuf, (const void *)nArg, sizeof(JpeBufInfo_t)); ++ ++ /* Is a legal buffer? */ ++ if(nRet || tOutBuf.nAddr == 0 || tOutBuf.nSize == 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "The buffer is not legal\n"); ++ eStatus = JPE_IOC_RET_BAD_OUTBUF; ++ CamOsMutexUnlock(&pCtx->m_stream); ++ goto RETURN; ++ } ++ ++ /* Set output buffer */ ++ pCtx->tEncOutBuf.nAddr = tOutBuf.nAddr; ++ pCtx->tEncOutBuf.nOrigSize = tOutBuf.nSize; ++ ++ pJpeCfg->OutBuf.nAddr = tOutBuf.nAddr; ++ pJpeCfg->OutBuf.nSize = tOutBuf.nSize; ++ ++ // The actual configuration will be applied when encode ++ CamOsMutexUnlock(&pCtx->m_stream); ++ ++RETURN: ++ return eStatus; ++} ++ ++ ++//============================================================================= ++// Description: ++// Release JPEG user context structure ++// Author: ++// Albert.Liao. ++// Input: ++// pCtxIn: JPEG user context ++// Output: ++// void ++//============================================================================= ++static void _JpeCtxRelease(void* pCtxIn) ++{ ++ JpeCtx_t* pCtx = pCtxIn; ++ JpeOpsCB_t* pOpsCB = pCtx->p_handle; ++ ++ CamOsMutexLock(&pCtx->m_stream); ++ pCtx->i_state = JPE_CTX_STATE_NULL; ++ if(pOpsCB) ++ { ++// if(pOpsCB->release) ++// pOpsCB->release(pOpsCB); ++ CamOsMemRelease(pOpsCB); ++ pCtx->p_handle = NULL; ++ } ++ CamOsMutexUnlock(&pCtx->m_stream); ++ ++ CamOsMutexDestroy(&pCtx->m_stream); ++ ++ CamOsMemRelease(pCtx->p_usrdt); ++ CamOsMemRelease(pCtx); ++} ++ ++ ++//============================================================================= ++// Description: ++// IOCTL handler for JPE_IOC_INIT ++// User uses this command to reset & init JPE encoder. User has to call this function again ++// before starting to encode another frame. ++// Author: ++// Albert.Liao. ++// Input: ++// pCtx: JPEG user context ++// arg: a pointer of JpeCfg_t from user-space ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++static JPE_IOC_RET_STATUS_e _JpeCtxIoctlInit(JpeCtx_t* pCtxIn, unsigned long nArg) ++{ ++ int nRet; ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ JpeCtx_t* pCtx = pCtxIn; ++ JpeOpsCB_t* pOpsCB = pCtx->p_handle; ++ JpeCfg_t* pJpeCfg = (JpeCfg_t *)nArg; ++ ++ if(0 == nArg) ++ return JPE_IOC_RET_FAIL; ++ ++ CamOsMutexLock(&pCtx->m_stream); ++ nRet = (int)copy_from_user(pJpeCfg, (void *)nArg, sizeof(JpeCaps_t)); ++ if(0 != nRet) ++ { ++ CamOsMutexUnlock(&pCtx->m_stream); ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ pCtx->i_state = JPE_CTX_STATE_IDLE; ++ nRet = pOpsCB->init(pOpsCB, pJpeCfg); ++ if(JPE_IOC_RET_SUCCESS == nRet) ++ { ++ memcpy(&pCtxIn->tJpeCfg, pJpeCfg, sizeof(JpeCfg_t)); ++ } ++ pCtx->tEncOutBuf.nAddr = pJpeCfg->OutBuf.nAddr; ++ pCtx->tEncOutBuf.nOrigSize = pJpeCfg->OutBuf.nSize; ++ eStatus = nRet; ++ CamOsMutexUnlock(&pCtx->m_stream); ++ ++ ++ return eStatus; ++} ++ ++ ++//============================================================================= ++// Description: ++// IOCTL handler for JPE_IOC_GET_CAPS ++// This command provide the capabilities of JPE ++// Author: ++// Albert.Liao. ++// Input: ++// pCtx: JPEG user context ++// arg: a pointer of JpeCaps_t from user-space ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++static JPE_IOC_RET_STATUS_e _JpeCtxGetCapbilities(JpeCtx_t* pCtxIn, unsigned long nArg) ++{ ++ int nRet = 0; ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ JpeCtx_t* pCtx = pCtxIn; ++ JpeCaps_t tCaps; ++ JpeOpsCB_t *pOpsCB = pCtx->p_handle; ++ ++ if(0 == nArg) ++ return JPE_IOC_RET_FAIL; ++ ++ memset(&tCaps, 0, sizeof(JpeCaps_t)); ++ CamOsMutexLock(&pCtx->m_stream); ++ /* Get capability */ ++ ++ eStatus = pOpsCB->getCaps(pOpsCB, &tCaps); ++ if(eStatus != JPE_IOC_RET_SUCCESS) ++ { ++ CamOsMutexUnlock(&pCtx->m_stream); ++ return eStatus; ++ } ++ ++ /* Copy to user-space */ ++ nRet = (int)copy_to_user((void *)(nArg), &tCaps, sizeof(JpeCaps_t)); ++ if(0 != nRet) ++ eStatus = JPE_IOC_RET_FAIL; ++ ++ CamOsMutexUnlock(&pCtx->m_stream); ++ return eStatus; ++} ++ ++ ++//============================================================================= ++// Description: ++// IOCTL handler for JPE_IOC_GETBITS ++// User uses this command to get the processed (encoded) buffer ++// Author: ++// Albert.Liao. ++// Input: ++// pCtx: JPEG user context ++// arg: a pointer of JpeBitstreamInfo_t from user-space ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++static JPE_IOC_RET_STATUS_e _JpeCtxGetBitInfo(JpeCtx_t* pCtxIn, unsigned long nArg) ++{ ++ int nRet; ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ JpeCtx_t* pCtx = pCtxIn; ++ JpeBitstreamInfo_t tStreamInfo; ++ ++ if(0 == nArg) ++ return JPE_IOC_RET_FAIL; ++ ++ memset(&tStreamInfo, 0, sizeof(JpeBitstreamInfo_t)); ++ ++ CamOsMutexLock(&pCtx->m_stream); ++ if(pCtx->tEncOutBuf.eState == JPE_FRAME_DONE_STATE && pCtx->tEncOutBuf.nAddr && pCtx->tEncOutBuf.nOutputSize) ++ { ++ tStreamInfo.nAddr = pCtx->tEncOutBuf.nAddr; ++ tStreamInfo.nOrigSize = pCtx->tEncOutBuf.nOrigSize; ++ tStreamInfo.nOutputSize = pCtx->tEncOutBuf.nOutputSize; ++ tStreamInfo.eState = pCtx->tEncOutBuf.eState; ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_ERR, "ERROR!! tEncOutBuf.addr:0x%x, tEncOutBuf.size:%ld\n", \ ++ (unsigned int)pCtx->tEncOutBuf.nAddr, pCtx->tEncOutBuf.nOutputSize); ++ ++ switch(pCtx->tEncOutBuf.eState) ++ { ++ case JPE_IDLE_STATE: ++ JPE_MSG(JPE_MSG_ERR, "eState=%s\n", JPE_TOSTRING(JPE_IDLE_STATE)); ++ break; ++ case JPE_BUSY_STATE: ++ JPE_MSG(JPE_MSG_ERR, "eState=%s\n", JPE_TOSTRING(JPE_BUSY_STATE)); ++ break; ++ case JPE_FRAME_DONE_STATE: ++ JPE_MSG(JPE_MSG_ERR, "eState=%s\n", JPE_TOSTRING(JPE_FRAME_DONE_STATE)); ++ break; ++ case JPE_OUTBUF_FULL_STATE: ++ JPE_MSG(JPE_MSG_ERR, "eState=%s\n", JPE_TOSTRING(JPE_OUTBUF_FULL_STATE)); ++ break; ++ case JPE_INBUF_FULL_STATE: ++ JPE_MSG(JPE_MSG_ERR, "eState=%s\n", JPE_TOSTRING(JPE_INBUF_FULL_STATE)); ++ break; ++ } ++ ++ CamOsMutexUnlock(&pCtx->m_stream); ++ return JPE_IOC_RET_HW_IS_RUNNING; ++ } ++ ++ /* Copy to user-space */ ++ nRet = (int)copy_to_user((void *)nArg, &tStreamInfo, sizeof(JpeBitstreamInfo_t)); ++ if(0 != nRet) ++ eStatus = JPE_IOC_RET_BAD_OUTBUF; ++ ++ CamOsMutexUnlock(&pCtx->m_stream); ++ return eStatus; ++} ++ ++ ++ ++//============================================================================= ++// Description: ++// IOCTL handler for JPE_IOC_ENCODE_FRAME ++// This command is used to encode JPEG image accroding to JpeCfg_t ++// Author: ++// Albert.Liao. ++// Input: ++// pCtx: JPEG user context ++// arg: a pointer of JpeBitstreamInfo_t from user-space ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++static JPE_IOC_RET_STATUS_e _JpeCtxEncodeFrame(JpeCtx_t* pCtxIn, unsigned long nArg) ++{ ++ int nRet; ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ ++ JpeCtx_t* pCtx = pCtxIn; ++ JpeDev_t* pDev = pCtx->p_device; ++ JpeOpsCB_t* pOpsCB = pCtx->p_handle; ++ JpeOps_t* pOps = pCtx->p_handle; ++ JpeCfg_t* pJpeCfg = (JpeCfg_t *)&pCtxIn->tJpeCfg; ++ JpeBitstreamInfo_t tStreamInfo; ++ ++ memset(&tStreamInfo, 0, sizeof(JpeBitstreamInfo_t)); ++ ++ CamOsMutexLock(&pCtx->m_stream); ++ do ++ { ++ if(JPE_CTX_STATE_IDLE == pCtx->i_state) ++ { ++ // If MIU address translation is need. It will be translate in HAL layer. ++ pOps->nClkSelect = pCtxIn->nClkSelect; ++ eStatus = pOpsCB->setConf(pOpsCB, pJpeCfg); ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ { ++ JPE_MSG(JPE_MSG_ERR, "pOpsCB->set_conf err\n"); ++ break; ++ } ++ ++ pCtx->i_state = JPE_CTX_STATE_BUSY; ++ ++ // When this function return, the raw data is already encoded as a JPEG image ++ eStatus = JpeDevPushJob(pDev, pCtx); ++ if(eStatus) ++ { ++ JPE_MSG(JPE_MSG_ERR, "jpeDevPushJob err\n"); ++ pCtx->i_state = JPE_CTX_STATE_IDLE; ++ break; ++ } ++ ++ if(nArg) ++ { ++ tStreamInfo.nAddr = pCtx->tEncOutBuf.nAddr; ++ tStreamInfo.nOrigSize = pCtx->tEncOutBuf.nOrigSize; ++ tStreamInfo.nOutputSize = pCtx->tEncOutBuf.nOutputSize; ++ tStreamInfo.eState = pCtx->tEncOutBuf.eState; ++ ++ /* Copy to user-space */ ++ nRet = (int)copy_to_user((void*)nArg, (void*)&tStreamInfo, sizeof(JpeBitstreamInfo_t)); ++ if(0 != nRet) ++ eStatus = JPE_IOC_RET_FAIL; ++ } ++ ++ pCtx->i_state = JPE_CTX_STATE_IDLE; ++ } ++ } ++ while(0); ++ CamOsMutexUnlock(&pCtx->m_stream); ++ return eStatus; ++} ++ ++ ++//============================================================================= ++// Description: ++// Create a new JPE user context. ++// User should use this context to do all JPEG encode related operations. ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// Output: ++// pCtx: JPEG user context ++//============================================================================= ++JpeCtx_t* JpeCtxAcquire(JpeDev_t* pDev) ++{ ++ JpeCtx_t* pCtx = NULL; ++ JpeOps_t* pOps = NULL; ++ JpeOpsCB_t* pOpsCB = NULL; ++ ++ int id = 0; ++ pCtx = CamOsMemCalloc(1, sizeof(JpeCtx_t)); ++ if((pDev == NULL) || (pCtx == NULL)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "> CamOsMemCalloc Fail \n"); ++ if(pCtx) ++ { ++ CamOsMemRelease(pCtx); ++ pCtx = NULL; ++ } ++ return pCtx; ++ } ++ ++ pCtx->p_usrdt = NULL; ++ ++ do ++ { ++ pOpsCB = JpeOpsAcquire(id); ++ if(pOpsCB == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "> JpeOpsAcquire Fail \n"); ++ break; ++ } ++ ++ pOps = (JpeOps_t*)pOpsCB; ++ pOps->pEncOutBuf = &pCtx->tEncOutBuf; ++ pCtx->p_usrdt = CamOsMemCalloc(1, JPE_USER_DATA_SIZE); ++ if(pCtx->p_usrdt == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "> CamOsMemCalloc Fail \n"); ++ break; ++ } ++ ++ CamOsMutexInit(&pCtx->m_stream); ++ pCtx->i_state = JPE_CTX_STATE_NULL; ++ pCtx->release = _JpeCtxRelease; ++ pCtx->p_handle = pOpsCB; ++ return pCtx; ++ } ++ while(0); ++ ++ if (pCtx->p_usrdt) ++ { ++ CamOsMemRelease(pCtx->p_usrdt); ++ pCtx->p_usrdt = NULL; ++ } ++ if(pOpsCB) ++ { ++// if(pOpsCB->release) ++// pOpsCB->release(pOpsCB); ++ CamOsMemRelease(pOpsCB); ++ pCtx->p_handle = NULL; ++ } ++ if(pCtx) ++ { ++ CamOsMemRelease(pCtx); ++ pCtx = NULL; ++ } ++ return pCtx; ++} ++ ++ ++//============================================================================= ++// Description: ++// Handle all JPEG encode related operations. ++// Author: ++// Albert.Liao. ++// Input: ++// pCtx: JPEG user context ++// cmd: command number ++// arg: a pointer from user-space, this pointer may be the address of JpeBufInfo_t, JpeCfg_t, JpeCaps_t, JpeBitstreamInfo_t ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++JPE_IOC_RET_STATUS_e JpeCtxActions(JpeCtx_t* pCtx, unsigned int cmd, void* arg) ++{ ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ switch(cmd) ++ { ++ case JPE_IOC_INIT: ++ eStatus = _JpeCtxIoctlInit(pCtx, (unsigned long)arg); ++ break; ++ ++ case JPE_IOC_SET_CLOCKRATE: ++ { ++ int nClkSelect = (int)(arg); ++ ++ // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ if((nClkSelect>=0) && (nClkSelect<4)) ++ { ++ pCtx->nClkSelect = nClkSelect; ++ eStatus = JPE_IOC_RET_SUCCESS; ++ } ++ else ++ { ++ eStatus = JPE_IOC_RET_FAIL; ++ } ++ } ++ break; ++ ++ case JPE_IOC_SET_OUTBUF: ++ eStatus = _JpeCtxSetOutputBuffer(pCtx, (unsigned long)arg); ++ break; ++ ++ case JPE_IOC_ENCODE_FRAME: ++ eStatus = _JpeCtxEncodeFrame(pCtx, (unsigned long)arg); ++ break; ++ ++ case JPE_IOC_GETBITS: ++ eStatus = _JpeCtxGetBitInfo(pCtx, (unsigned long)arg); ++ break; ++ ++ case JPE_IOC_GET_CAPS: ++ eStatus = _JpeCtxGetCapbilities(pCtx, (unsigned long)arg); ++ break; ++ ++ default: ++ eStatus = JPE_IOC_RET_FAIL; ++ break; ++ } ++ return eStatus; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/src/common/drv_jpe_dev.c b/drivers/mstar/jpe2/drv/src/common/drv_jpe_dev.c +new file mode 100644 +index 00000000..9dce7516 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/src/common/drv_jpe_dev.c +@@ -0,0 +1,129 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "hal_jpe_ios.h" ++#include "hal_jpe_ops.h" ++#include "drv_jpe_io_st_kernel.h" ++ ++static u32 _GetTime(void) ++{ ++ CamOsTimespec_t tTime; ++ CamOsGetMonotonicTime(&tTime); ++ return ((tTime.nSec*1000000+ tTime.nNanoSec/1000)/1000); ++} ++ ++ ++int JpeDevRegister(JpeDev_t* pDev, JpeCtx_t* pCtx) ++{ ++ int i = 0; ++ CamOsMutexLock(&pDev->m_mutex); ++ pCtx->i_index = -1; ++ while(i < JPE_STREAM_NR) ++ { ++ if(pDev->user[i++].pCtx) ++ continue; ++ pDev->user[--i].pCtx = pCtx; ++ pCtx->p_device = pDev; ++ pCtx->i_index = i; ++ break; ++ } ++ CamOsMutexUnlock(&pDev->m_mutex); ++ return pCtx->i_index; ++} ++ ++ ++JPE_IOC_RET_STATUS_e JpeDevUnregister(JpeDev_t* pDev, JpeCtx_t* pCtx) ++{ ++ if((!pDev) || (!pCtx)) ++ { ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ CamOsMutexLock(&pDev->m_mutex); ++ pDev->user[pCtx->i_index].pCtx = NULL; ++ pCtx->p_device = NULL; ++ pCtx->i_index = -1; ++ CamOsMutexUnlock(&pDev->m_mutex); ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++ ++int JpeDevPushJob(JpeDev_t* pDev, JpeCtx_t* pCtxIn) ++{ ++ JpeOpsCB_t* pOpsCB = pCtxIn->p_handle; ++ JpeOps_t* pOps = pCtxIn->p_handle; ++ JpeIos_t* pIos = pDev->p_asicip; ++ JpeIosCB_t* pIosCB = pDev->p_asicip; ++ JpeJob_t* pJob = pOpsCB->jpeJob(pOpsCB); ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ int otmr, itmr, id = pCtxIn->i_index; ++ ++ if((!pOps) || (!pJob) || (!pIosCB)) ++ { ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ otmr = _GetTime(); ++ CamOsTsemDown(&pDev->tGetBitsSem); ++ itmr = _GetTime(); ++ pDev->i_state = JPE_DEV_STATE_BUSY; ++ ++ eStatus = pIosCB->encFire(pIosCB, &pOps->tJpeHalHandle, pJob); ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ { ++ CamOsTsemUp(&pDev->tGetBitsSem); ++ return (int)eStatus; ++ } ++ CamOsTsemWait(&pDev->m_wqh); ++ //CamOsTsemTimedWait(&pDev->m_wqh, 100*1000); ++ ++ // After encode done, we should change ++ // Below 2 arguments remain the same. ++ pCtxIn->tEncOutBuf.nOutputSize = pIos->nEncodeSize; ++ pCtxIn->tEncOutBuf.eState = pIos->eJpeDevStatus; ++ ++ itmr = _GetTime() - itmr; ++ CamOsTsemUp(&pDev->tGetBitsSem); ++ otmr = _GetTime() - otmr; ++ ++ //CamOsDebug("itmr:%d, otmr:%d \n", itmr, otmr); ++ ++ // TODO: update below counter value to /proc ++ if(otmr > pDev->i_thresh && pDev->i_thresh > 0) ++ pDev->i_counts[id][0]++; ++ if(otmr > pDev->i_counts[id][1]) ++ pDev->i_counts[id][1] = otmr; ++ if(itmr > pDev->i_counts[id][2]) ++ pDev->i_counts[id][2] = itmr; ++ if(pJob->i_tick > pDev->i_counts[id][3]) ++ pDev->i_counts[id][3] = pJob->i_tick; ++ return eStatus; ++} ++ ++ ++int JpeDevIsrFnx(JpeDev_t* pDev) ++{ ++ JpeIosCB_t* pIosCB = pDev->p_asicip; ++ ++ if(!pIosCB->isrFunc(pIosCB, 0)) ++ { ++ pDev->i_state = JPE_DEV_STATE_IDLE; ++ CamOsTsemSignal(&pDev->m_wqh); ++ } ++ ++ return 0; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/src/linux/drv_jpe_module.c b/drivers/mstar/jpe2/drv/src/linux/drv_jpe_module.c +new file mode 100644 +index 00000000..94296b32 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/src/linux/drv_jpe_module.c +@@ -0,0 +1,724 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include "ms_msys.h" ++ ++#include "hal_jpe_ios.h" ++#include "hal_jpe_ops.h" ++#include "_drv_jpe_dev.h" ++#include "_drv_jpe_ctx.h" ++#include "drv_jpe_module.h" ++ ++#define MDRV_JPE_DEVICE_COUNT 1 // How many device will be installed ++#define MDRV_JPE_NAME "mstar_jpe" ++#define MDRV_JPE_MINOR 0 ++#define MDRV_JPE_CLASS_NAME "mstar_jpe_class" ++ ++#define JPE_CLOCK_ON 1 ++#define JPE_CLOCK_OFF 0 ++ ++static JpeDev_t* _gpDev = NULL; ++ ++//============================================================================= ++// Description: ++// ISR handler ++// Author: ++// Albert.Liao. ++// Input: ++// irq: IRQ ++// dev_data: Device data which is assigned from request_irq() ++// Output: ++// Always IRQ_HANDLED to stop parsing IS ++//============================================================================= ++irqreturn_t _JpeIsr(int irq, void* pDevData) ++{ ++ JpeDev_t* pDev = (JpeDev_t*)pDevData; ++ ++ if(pDev) ++ { ++ JpeDevIsrFnx(pDev); ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_ERR, "pDev==NULL, JPE device is removed\n"); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++ ++//============================================================================= ++// _DevPowserOn ++// Turn on/off clock ++// ++// Parameters: ++// pdev: platform device ++// bOn: use 1 to turn on clock, and use 0 to turn off clock ++// ++// Return: ++// standard return value ++//============================================================================= ++static JPE_IOC_RET_STATUS_e _DevPowserOn(JpeDev_t* pDev, int bOn) ++{ ++ int i = 0; ++ int nRet; ++ struct clk* pClock; ++ ++ if(!pDev) ++ return JPE_IOC_RET_FAIL; ++ ++ if(JPE_CLOCK_ON == bOn) ++ { ++ while (i < JPE_CLOCKS_NR && (pClock = pDev->pClock[i++])) ++ clk_prepare_enable(pClock); ++ pClock = pDev->pClock[0]; ++ nRet = clk_set_rate(pClock, pDev->nClockRate); ++ if(nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "clk_set_rate() Fail, ret=%d\n", nRet); ++ return JPE_IOC_RET_FAIL; ++ } ++ nRet = clk_prepare_enable(pClock); ++ if(nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "clk_prepare_enable() Fail, ret=%d\n", nRet); ++ return JPE_IOC_RET_FAIL; ++ } ++ pDev->i_users++; ++ } ++ else ++ { ++ pClock = pDev->pClock[0]; ++ clk_set_parent(pClock, clk_get_parent_by_index(pClock, 0)); ++ while (i < JPE_CLOCKS_NR && (pClock = pDev->pClock[i++])) ++ clk_disable_unprepare(pClock); ++ pDev->i_users--; ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++//============================================================================= ++// Description: ++// File open handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// pCtx: JPEG user handle ++// Output: ++// 0: success ++// ++//============================================================================= ++int JpeOpen(struct inode *inode, struct file *filp) ++{ ++ JpeDev_t* pDev = NULL; ++ JpeCtx_t* pCtx = NULL; ++ int nRet, nStatus = 0; ++ ++ pDev = container_of(inode->i_cdev, JpeDev_t, tCharDev); ++ if(!pDev) ++ { ++ JPE_MSG(JPE_MSG_ERR, "pDev==NULL\n"); ++ goto _OpenErr; ++ } ++ ++ pCtx = JpeCtxAcquire(pDev); ++ if(pCtx == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "JpeCtxAcquire Fail\n"); ++ nStatus = -ENODEV; ++ return nStatus; ++ //goto _OpenErr; ++ } ++ ++ // After success register, pDev->user[0].pCtx = pCtx ++ nRet = JpeDevRegister(pDev, pCtx); ++ if(0 > nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "JpeDevRegister Fail, ret=%d\n", nRet); ++ nStatus = -EUSERS; ++ goto _OpenErr; ++ } ++ ++ pDev->nRefCount++; ++ filp->private_data = pCtx; ++ ++ nRet = _DevPowserOn(pDev, JPE_CLOCK_ON); ++ if(nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "clk_set_rate() Fail, ret=%d\n", nRet); ++ nStatus = -ENODEV; ++ goto _OpenErr; ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++ ++_OpenErr: ++ JPE_MSG(JPE_MSG_ERR, "JpeOpen Fail \n"); ++ pCtx->release(pCtx); ++ ++ return nStatus; ++} ++ ++ ++//============================================================================= ++// Description: ++// File close handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// pCtx: JPEG user handle ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++int JpeRelease(struct inode *inode, struct file *filp) ++{ ++ JpeDev_t* pDev = NULL; ++ JpeCtx_t* pCtx = NULL; ++ JPE_IOC_RET_STATUS_e eStatus; ++ int nRet; ++ ++ pCtx = filp->private_data; ++ if (NULL == pCtx) ++ { ++ return -ENOMEDIUM; ++ } ++ ++ pDev = pCtx->p_device; ++ ++ nRet = _DevPowserOn(pDev, JPE_CLOCK_OFF); ++ if(nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "clk_set_rate() Fail, ret=%d\n", nRet); ++ return -ENODEV; ++ } ++ ++ eStatus = JpeDevUnregister(pDev, pCtx); ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ { ++ JPE_MSG(JPE_MSG_ERR, "JpeDevUnregister Fail ret=%d\n", nRet); ++ return -ENOMEDIUM; ++ } ++ ++ if(pCtx->release) ++ { ++ pCtx->release(pCtx); ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++ ++//============================================================================= ++// Description: ++// IOCTL handler entry for file operator ++// Author: ++// Albert.Liao. ++// Input: ++// filp: pointer of file structure ++// cmd: command ++// arg: argument from user-space ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++long JpeIoctl(struct file *pFilp, unsigned int nCmd, unsigned long nArg) ++{ ++ JpeCtx_t* pCtx = (JpeCtx_t*)pFilp->private_data; ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++#if 0 ++ switch(nCmd) ++ { ++ case JPE_IOC_INIT: ++ JPE_MSG(JPE_MSG_ERR, "JpeIoctl command = JPE_IOC_INIT\n"); ++ break; ++ case JPE_IOC_ENCODE_FRAME: ++ JPE_MSG(JPE_MSG_ERR, "JpeIoctl command = JPE_IOC_ENCODE_FRAME\n"); ++ break; ++ case JPE_IOC_GETBITS: ++ JPE_MSG(JPE_MSG_ERR, "JpeIoctl command = JPE_IOC_GETBITS\n"); ++ break; ++ case JPE_IOC_GET_CAPS: ++ JPE_MSG(JPE_MSG_ERR, "JpeIoctl command = JPE_IOC_GET_CAPS\n"); ++ break; ++ case JPE_IOC_SET_OUTBUF: ++ JPE_MSG(JPE_MSG_ERR, "JpeIoctl command = JPE_IOC_SET_OUTBUF\n"); ++ break; ++ } ++#endif ++ ++ switch(nCmd) ++ { ++ case JPE_IOC_INIT: ++ //_DumpConfig((JpeCfg_t *)nArg); ++ eStatus = JpeCtxActions(pCtx, JPE_IOC_INIT, (void *)nArg); ++ break; ++ ++ case JPE_IOC_SET_CLOCKRATE: ++ { ++ int nRet = 0, nClkSelect = (int)(nArg); ++ JpeDev_t* pDev = pCtx->p_device; ++ struct clk* pClock; ++ ++ // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ if((nClkSelect>=0) && (nClkSelect<4)) ++ { ++ pClock = pDev->pClock[0]; ++ if(pClock) ++ { ++ pDev->nClockRate = clk_get_rate(clk_get_parent_by_index(pClock, nClkSelect)); ++ nRet = clk_set_rate(pClock, pDev->nClockRate); ++ if(nRet) ++ { ++ eStatus = JPE_IOC_RET_FAIL; ++ } ++ } ++ } ++ break; ++ } ++ case JPE_IOC_ENCODE_FRAME: ++ eStatus = JpeCtxActions(pCtx, JPE_IOC_ENCODE_FRAME, (void *)nArg); ++ break; ++ ++ case JPE_IOC_SET_OUTBUF: ++ { ++ JpeBufInfo_t *pOutBuf = NULL; ++ pOutBuf = (JpeBufInfo_t *)nArg; ++ //JPE_MSG(JPE_MSG_ERR, "pOutBuf nAddr=0x%x, size=%d\n", (int)pOutBuf->nAddr, (int)pOutBuf->nSize); ++ eStatus = JpeCtxActions(pCtx, JPE_IOC_SET_OUTBUF, (void *)nArg); ++ break; ++ } ++ ++ case JPE_IOC_GETBITS: ++ eStatus = JpeCtxActions(pCtx, JPE_IOC_GETBITS, (void *)nArg); ++ //_DumpBitInfo((JpeBitstreamInfo_t *)nArg); ++ break; ++ ++ case JPE_IOC_GET_CAPS: ++ eStatus = JpeCtxActions(pCtx, JPE_IOC_GET_CAPS, (void *)nArg); ++ break; ++ ++ default: ++ eStatus = JPE_IOC_RET_FAIL; ++ break; ++ } ++ ++ // For linux ioctl usage, ++ // If error happens, return value is always -1, and the actual error code is stored in errno ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ eStatus = -eStatus; ++ ++ return eStatus; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Platform functions ++//------------------------------------------------------------------------------------------------- ++ ++// Use a struct to gather all global variable ++static struct ++{ ++ int major; // cdev major number ++ int minor_start; // beginning of cdev minor number ++ int reg_count; // registered count ++ struct class *class; // class pointer ++} g_jpe_drv = {0, 0, 0, NULL}; ++ ++static const struct file_operations jpe_fops = ++{ ++ .owner = THIS_MODULE, ++ .open = JpeOpen, ++ .release = JpeRelease, ++ .unlocked_ioctl = JpeIoctl, ++}; ++ ++//static void _JpeDevRelease(struct device* dev) {} ++ ++//============================================================================= ++// Description: ++// Platform device probe handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// Output: ++// JpeDev_t: JPEG hardware device handle ++//============================================================================= ++//JpeDev_t* JpeProbe(JpeDev_t* pDev) ++static int JpeProbe(struct platform_device *pPlatformDev) ++{ ++ int i; ++ JpeDev_t* pDev = NULL; ++ JpeIosCB_t* mios = NULL; ++ JpeRegIndex_t mregs; ++ ++ dev_t dev; ++ struct resource *pResource; ++ struct clk* pClock; ++ ++ int nErr = 0; ++ JPE_IOC_RET_STATUS_e eStatus; ++ ++ if(_gpDev) ++ return 0; ++ ++ /* Allocate cdev id */ ++ nErr = alloc_chrdev_region(&dev, MDRV_JPE_MINOR, MDRV_JPE_DEVICE_COUNT, MDRV_JPE_NAME); ++ if(nErr) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Unable allocate cdev id\n"); ++ return nErr; ++ } ++ ++ g_jpe_drv.major = MAJOR(dev); ++ g_jpe_drv.minor_start = MINOR(dev); ++ g_jpe_drv.reg_count = 0; ++ ++ /* Register device class */ ++ g_jpe_drv.class = (struct class *)msys_get_sysfs_class(); ++ if(IS_ERR(g_jpe_drv.class)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Failed at class_create().Please exec [mknod] before operate the device\n"); ++ nErr = PTR_ERR(g_jpe_drv.class); ++ return nErr; ++ } ++ ++ do ++ { ++ pDev = CamOsMemCalloc(1, sizeof(JpeDev_t)); ++ if(pDev == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Create Mdev Fail \n"); ++ goto _ProbeErr; ++ } ++ ++ pDev->pPlatformDev = pPlatformDev; ++ ++ CamOsMutexInit(&pDev->m_mutex); ++ CamOsTsemInit(&pDev->tGetBitsSem, 1); ++ CamOsTsemInit(&pDev->m_wqh, JPE_DEV_STATE_IDLE); ++ ++ pDev->p_asicip = JpeIosAcquire("jpe"); ++ mios = pDev->p_asicip; ++ if(mios == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Create Mios Fail \n"); ++ goto _ProbeErr; ++ } ++ ++ /* memory-mapped IO registers */ ++ pResource = platform_get_resource(pPlatformDev, IORESOURCE_MEM, 0); ++ if(!pResource) ++ { ++ goto _ProbeErr; ++ } ++ ++ mregs.i_id = 0; ++ mregs.base = (void*)IO_ADDRESS(pResource->start); ++ mregs.size = (int)(pResource->end - pResource->start); ++ ++ eStatus = mios->setBank(mios, &mregs); ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ { ++ JPE_MSG(JPE_MSG_ERR, "> set_bank Fail \n"); ++ goto _ProbeErr; ++ } ++ ++ /* IRQ registration */ ++ pDev->irq = irq_of_parse_and_map(pPlatformDev->dev.of_node, 0); ++ if(pDev->irq == 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Cannot find IRQ\n"); ++ goto _ProbeErr; ++ } ++ ++ pClock = clk_get(&pPlatformDev->dev, "CKG_jpe"); ++ if (IS_ERR(pClock)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "clk_get failed\n"); ++ goto _ProbeErr; ++ } ++ pDev->pClock[0] = pClock; ++ pDev->nClockIdx = 0; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ pDev->nClockRate = clk_get_rate(clk_get_parent_by_index(pClock, pDev->nClockIdx)); ++ JPE_MSG(JPE_MSG_ERR, "set base=0x%x irq=%d, nClockRate=%d\n", (u32)mregs.base, pDev->irq, (u32)pDev->nClockRate); ++ for (i = 1; i < JPE_CLOCKS_NR; i++) ++ { ++ pClock = of_clk_get(pPlatformDev->dev.of_node, i); ++ if (IS_ERR(pClock)) ++ break; ++ pDev->pClock[i] = pClock; ++ } ++ ++ /* Add cdev */ ++ cdev_init(&pDev->tCharDev, &jpe_fops); ++ pDev->tCharDev.owner = THIS_MODULE; ++ nErr = cdev_add(&pDev->tCharDev, MKDEV(g_jpe_drv.major, g_jpe_drv.minor_start + g_jpe_drv.reg_count), 1); ++ if(nErr) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Unable add a character device\n"); ++ goto _ProbeErr; ++ } ++ ++ /* Create a instance in class */ ++ device_create(g_jpe_drv.class, ++ NULL, ++ MKDEV(g_jpe_drv.major, g_jpe_drv.minor_start + g_jpe_drv.reg_count), ++ pDev, ++ MDRV_JPE_NAME"%d", g_jpe_drv.minor_start + g_jpe_drv.reg_count); ++ ++ /* Increase registered count */ ++ g_jpe_drv.reg_count++; ++ ++ // Register a ISR ++ //nRet = request_irq(pDev->irq, _JpeIsr, IRQF_SHARED, "jpe interrupt", pDev); ++ nErr = request_irq(pDev->irq, _JpeIsr, IRQ_TYPE_LEVEL_HIGH, "jpe interrupt", pDev); ++ if (nErr) ++ { ++ JPE_MSG(JPE_MSG_ERR, "request_irq() failed (%d)\n", nErr); ++ goto _ProbeErr; ++ } ++ ++ dev_set_drvdata(&pPlatformDev->dev, pDev); ++ ++ _gpDev = pDev; ++ } ++ while(0); ++ ++ return nErr; ++ ++//TODO: fix me ++_ProbeErr: ++ if(mios != NULL) ++ CamOsMemRelease(mios); ++ if(pDev != NULL) ++ CamOsMemRelease(pDev); ++ return -ENODEV; ++} ++ ++ ++//============================================================================= ++// Description: ++// File close handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++static int JpeRemove(struct platform_device *pPlatformDev) ++{ ++ JpeDev_t* pDev = NULL; ++ JpeIosCB_t* pIos = NULL; ++ ++ pDev = dev_get_drvdata(&pPlatformDev->dev); ++ ++ if(pDev) ++ { ++ CamOsMutexDestroy(&pDev->m_mutex); ++ CamOsTsemDeinit(&pDev->m_wqh); ++ CamOsTsemDeinit(&pDev->tGetBitsSem); ++ pIos = pDev->p_asicip; ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_ERR, "pDev==NULL, %s fail\n", __func__); ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ if(pIos) ++ { ++ // TODO: Should I do irq mask??? ++ //pIos->irqMask(pIos, 0xFF); ++ pIos->release(pIos); ++ } ++ ++ free_irq(pDev->irq, pDev); ++ ++ // TODO: check g_jpe_drv.reg_count before destory device ++ device_destroy(g_jpe_drv.class, pDev->tCharDev.dev); ++ cdev_del(&pDev->tCharDev); ++ ++ CamOsMemRelease(pDev); ++ ++ unregister_chrdev_region(MKDEV(g_jpe_drv.major, g_jpe_drv.minor_start), MDRV_JPE_DEVICE_COUNT); ++ ++ _gpDev = NULL; ++ return JPE_IOC_RET_SUCCESS; ++ ++} ++ ++ ++//============================================================================= ++// JpeSuspend ++// Platform device suspend handler, but nothing to do here ++// ++// Parameters: ++// pPlatformDev: platform device ++// state: don't use ++// ++// Return: ++// standard return value ++//============================================================================= ++static int JpeSuspend(struct platform_device *pPlatformDev, pm_message_t state) ++{ ++ int nRet; ++ JpeDev_t* pDev = NULL; ++ ++ pDev = dev_get_drvdata(&pPlatformDev->dev); ++ ++ CamOsTsemDown(&pDev->tGetBitsSem); ++ if(pDev->i_users > 0) ++ { ++ nRet = _DevPowserOn(pDev, JPE_CLOCK_OFF); ++ if(nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Power can not turn off, ret=%d\n", nRet); ++ return -ENODEV; ++ } ++ } ++ ++ return 0; ++} ++ ++ ++//============================================================================= ++// JpeResume ++// Platform device resume handler, but nothing to do here ++// ++// Parameters: ++// pPlatformDev: platform device ++// ++// Return: ++// standard return value ++//============================================================================= ++static int JpeResume(struct platform_device *pPlatformDev) ++{ ++ int nRet; ++ JpeDev_t* pDev = NULL; ++ ++ pDev = dev_get_drvdata(&pPlatformDev->dev); ++ ++ if(pDev->i_users > 0) ++ { ++ nRet = _DevPowserOn(pDev, JPE_CLOCK_ON); ++ if(nRet) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Power can not turn on, ret=%d\n", nRet); ++ CamOsTsemUp(&pDev->tGetBitsSem); ++ return -ENODEV; ++ } ++ } ++ CamOsTsemUp(&pDev->tGetBitsSem); ++ ++ return 0; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Data structure for device driver ++//------------------------------------------------------------------------------------------------- ++static const struct of_device_id mdrv_jpeg_match[] = ++{ ++ { ++ .compatible = "mstar,cedric-jpe", ++ /*.data = NULL,*/ ++ }, ++ { ++ .compatible = "mstar,infinity-jpe", ++ /*.data = NULL,*/ ++ }, ++ {}, ++}; ++ ++ ++static struct platform_driver mdrv_jpe_driver = ++{ ++ .probe = JpeProbe, ++ .remove = JpeRemove, ++ .suspend = JpeSuspend, ++ .resume = JpeResume, ++ ++ .driver = ++ { ++ .of_match_table = of_match_ptr(mdrv_jpeg_match), ++ .name = "mstar_jpe", ++ .owner = THIS_MODULE, ++ } ++}; ++ ++ ++/******************************************************************************************************************* ++ * _mdrv_jpe_module_init ++ * module init function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++int mdrv_jpe_module_init(void) ++{ ++ JPE_MSG(JPE_MSG_DEBUG, "Module Init\n"); ++ /* Register platform driver */ ++ return platform_driver_register(&mdrv_jpe_driver); ++} ++ ++ ++ ++/******************************************************************************************************************* ++ * mdrv_jpe_module_exit ++ * module exit function ++ * ++ * Parameters: ++ * N/A ++ * ++ * Return: ++ * standard return value ++ */ ++void mdrv_jpe_module_exit(void) ++{ ++ /* de-initial the who GFLIPDriver */ ++ JPE_MSG(JPE_MSG_ERR, "Module Exit\n"); ++ platform_driver_unregister(&mdrv_jpe_driver); ++} ++ ++module_init(mdrv_jpe_module_init); ++module_exit(mdrv_jpe_module_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("JPE ioctrl driver"); ++MODULE_LICENSE("GPL"); +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/src/rtk/drv_jpe_module.c b/drivers/mstar/jpe2/drv/src/rtk/drv_jpe_module.c +new file mode 100644 +index 00000000..2d9ddd44 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/src/rtk/drv_jpe_module.c +@@ -0,0 +1,215 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "hal_jpe_ios.h" ++#include "hal_jpe_ops.h" ++#include "drv_jpe_io_st_kernel.h" ++#include "_drv_jpe_dev.h" ++#include "_drv_jpe_ctx.h" ++#include "drv_jpe_module.h" ++ ++static JpeDev_t* _gpDev = NULL; ++ ++//============================================================================= ++// Description: ++// ISR handler ++// Author: ++// Albert.Liao. ++// Input: ++// none. ++// Output: ++// none. ++//============================================================================= ++static void _JpeIsr() ++{ ++ if(_gpDev) ++ { ++ JpeDevIsrFnx(_gpDev); ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_ERR, "_gpDev==NULL, JPE device is removed\n"); ++ } ++} ++ ++ ++//============================================================================= ++// Description: ++// File open handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// pCtx: JPEG user handle ++// Output: ++// pCtx: a new JPEG user handle ++//============================================================================= ++JpeCtx_t* JpeOpen(JpeDev_t* pDev, JpeCtx_t* pCtx) ++{ ++ pCtx = JpeCtxAcquire(pDev); ++ if(pCtx == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "JpeCtxAcquire Fail \n"); ++ return pCtx; ++ } ++ ++ if(0 <= JpeDevRegister(pDev, pCtx)) ++ { ++ return pCtx; ++ } ++ ++ JPE_MSG(JPE_MSG_ERR, "JpeDevRegister Fail \n"); ++ pCtx->release(pCtx); ++ ++ return pCtx; ++} ++ ++ ++//============================================================================= ++// Description: ++// File close handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// pCtx: JPEG user handle ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++JPE_IOC_RET_STATUS_e JpeRelease(JpeDev_t* pDev, JpeCtx_t* pCtx) ++{ ++ JPE_IOC_RET_STATUS_e eStatus; ++ ++ eStatus = JpeDevUnregister(pDev, pCtx); ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ { ++ JPE_MSG(JPE_MSG_ERR, "JpeDevUnregister Fail \n"); ++ return eStatus; ++ } ++ ++ if(pCtx) ++ { ++ pCtx->release(pCtx); ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++ ++//============================================================================= ++// Description: ++// Platform device probe handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// Output: ++// JpeDev_t: JPEG hardware device handle ++//============================================================================= ++JpeDev_t* JpeProbe(JpeDev_t* pDev) ++{ ++ JpeIosCB_t* mios = NULL; ++ JpeRegIndex_t mregs; ++ MsIntInitParam_u uInitParam; ++ unsigned long res_base = JPE_OFFSET + IO_START_ADDRESS; ++ ++ int res_size = 0x100; ++ JPE_IOC_RET_STATUS_e eStatus; ++ ++ if(_gpDev) ++ return _gpDev; ++ ++ do ++ { ++ pDev = CamOsMemCalloc(1, sizeof(JpeDev_t)); ++ if(pDev == NULL) ++ { ++ JPE_MSG(JPE_MSG_ERR, "> Create Mdev Fail \n"); ++ break; ++ } ++ CamOsMutexInit(&pDev->m_mutex); ++ CamOsTsemInit(&pDev->tGetBitsSem, 1); ++ CamOsTsemInit(&pDev->m_wqh, JPE_DEV_STATE_IDLE); ++ ++ pDev->p_asicip = JpeIosAcquire("jpe"); ++ mios = pDev->p_asicip; ++ ++ mregs.i_id = 0; ++ mregs.base = (unsigned long*)res_base; ++ mregs.size = res_size; ++ ++ eStatus = mios->setBank(mios, &mregs); ++ if(JPE_IOC_RET_SUCCESS != eStatus) ++ { ++ JPE_MSG(JPE_MSG_ERR, "> set_bank Fail \n"); ++ } ++ uInitParam.intc.eMap = INTC_MAP_IRQ; ++ uInitParam.intc.ePriority = INTC_PRIORITY_7; ++ uInitParam.intc.pfnIsr = _JpeIsr; ++ MsInitInterrupt(&uInitParam, MS_INT_NUM_IRQ_JPE); ++ MsUnmaskInterrupt(MS_INT_NUM_IRQ_JPE); ++ ++ _gpDev = pDev; ++ return pDev; ++ } ++ while(0); ++ ++ return _gpDev; ++} ++ ++ ++//============================================================================= ++// Description: ++// File close handler ++// Author: ++// Albert.Liao. ++// Input: ++// pDev: JPEG hardware device handle ++// Output: ++// JPE_IOC_RET_SUCCESS: Success ++// JPE_IOC_RET_FAIL: Failure ++//============================================================================= ++JPE_IOC_RET_STATUS_e JpeRemove(JpeDev_t* pDev) ++{ ++ JpeIosCB_t* pIos = NULL; ++ ++ if(pDev) ++ { ++ CamOsMutexDestroy(&pDev->m_mutex); ++ CamOsTsemDeinit(&pDev->m_wqh); ++ CamOsTsemDeinit(&pDev->tGetBitsSem); ++ pIos = pDev->p_asicip; ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_ERR, "pDev==NULL, %s fail\n", __func__); ++ } ++ ++ MsMaskInterrupt(MS_INT_NUM_IRQ_JPE); ++ MsClearInterrupt(MS_INT_NUM_IRQ_JPE); ++ ++ if(pIos) ++ { ++ pIos->release(pIos); ++ } ++ ++ MsReleaseMemory(pDev); ++ ++ _gpDev = NULL; ++ return JPE_IOC_RET_SUCCESS; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/drv_jpe_enc.c b/drivers/mstar/jpe2/drv/test/common/drv_jpe_enc.c +new file mode 100644 +index 00000000..5b3881bf +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/drv_jpe_enc.c +@@ -0,0 +1,366 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__linux__) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "drv_jpe_enc.h" ++#include "cam_os_wrapper.h" ++#include ++ ++#elif defined(__I_SW__) ++#include "cam_os_wrapper.h" ++#include "drv_jpe_io.h" ++#include "drv_jpe_io_st.h" ++#include "drv_jpe_module.h" ++#include "drv_jpe_enc.h" ++ ++#endif ++ ++#define JPE_STRINGIFY(x) #x ++#define JPE_TOSTRING(x) JPE_STRINGIFY(x) ++ ++ ++#if 0 ++static void _DumpCapabilities(JpeCaps_t *pCaps) ++{ ++ if(pCaps) ++ { ++ CamOsDebug("u32JpeId = %d\n", pCaps->u32JpeId); ++ CamOsDebug("nRefYLogAddrAlign[0] = %d\n", pCaps->nRefYLogAddrAlign[0]); ++ CamOsDebug("nRefYLogAddrAlign[1] = %d\n", pCaps->nRefYLogAddrAlign[1]); ++ CamOsDebug("nRefCLogAddrAlign[0] = %d\n", pCaps->nRefCLogAddrAlign[0]); ++ CamOsDebug("nRefCLogAddrAlign[1] = %d\n", pCaps->nRefCLogAddrAlign[1]); ++ CamOsDebug("nOutBufSLogAddrAlign = %d\n", pCaps->nOutBufSLogAddrAlign); ++ CamOsDebug("nSclHandShakeSupport = %d\n", pCaps->nSclHandShakeSupport); ++ CamOsDebug("nCodecSupport = %d\n", pCaps->nCodecSupport); ++ ++ if(JPE_IBUF_FRAME_MODE == pCaps->nBufferModeSupport) ++ { ++ CamOsDebug("nBufferModeSupport = %s\n", JPE_TOSTRING(JPE_IBUF_FRAME_MODE)); ++ } ++ else ++ { ++ CamOsDebug("nBufferModeSupport = %s\n", JPE_TOSTRING(JPE_IBUF_ROW_MODE)); ++ } ++ } ++} ++ ++static void _DumpBitInfo(JpeBitstreamInfo_t *pBitInfo) ++{ ++ if(pBitInfo) ++ { ++ CamOsDebug("pBitInfo nAddr=%p, nOrigSize=%d nOutputSize=%d\n", pBitInfo->nAddr, pBitInfo->nOrigSize, pBitInfo->nOutputSize); ++ switch(pBitInfo->eState) ++ { ++ case JPE_IDLE_STATE: ++ CamOsDebug("eState=%d %s\n", pBitInfo->eState, JPE_TOSTRING(JPE_IDLE_STATE)); ++ break; ++ case JPE_BUSY_STATE: ++ CamOsDebug("eState=%d %s\n", pBitInfo->eState, JPE_TOSTRING(JPE_BUSY_STATE)); ++ break; ++ case JPE_FRAME_DONE_STATE: ++ CamOsDebug("eState=%d %s\n", pBitInfo->eState, JPE_TOSTRING(JPE_FRAME_DONE_STATE)); ++ break; ++ case JPE_OUTBUF_FULL_STATE: ++ CamOsDebug("eState=%d %s\n", pBitInfo->eState, JPE_TOSTRING(JPE_OUTBUF_FULL_STATE)); ++ break; ++ case JPE_INBUF_FULL_STATE: ++ CamOsDebug("eState=%d %s\n", pBitInfo->eState, JPE_TOSTRING(JPE_INBUF_FULL_STATE)); ++ break; ++ } ++ } ++} ++#endif ++ ++#if 0 ++static void _DumpConfig(JpeCfg_t *pJpeCfg) ++{ ++ if(pJpeCfg) ++ { ++ switch(pJpeCfg->eInBufMode) ++ { ++ case JPE_IBUF_ROW_MODE: ++ CamOsDebug("eInBufMode=%s\n", JPE_TOSTRING(JPE_IBUF_ROW_MODE)); ++ break; ++ case JPE_IBUF_FRAME_MODE: ++ CamOsDebug("eInBufMode=%s\n", JPE_TOSTRING(JPE_IBUF_FRAME_MODE)); ++ break; ++ } ++ ++ switch(pJpeCfg->eRawFormat) ++ { ++ case JPE_RAW_YUYV: ++ CamOsDebug("eRawFormat=%s\n", JPE_TOSTRING(JPE_RAW_YUYV)); ++ break; ++ case JPE_RAW_YVYU: ++ CamOsDebug("eRawFormat=%s\n", JPE_TOSTRING(JPE_RAW_YVYU)); ++ break; ++ case JPE_RAW_NV12: ++ CamOsDebug("eRawFormat=%s\n", JPE_TOSTRING(JPE_RAW_NV12)); ++ break; ++ case JPE_RAW_NV21: ++ CamOsDebug("eRawFormat=%s\n", JPE_TOSTRING(JPE_RAW_NV21)); ++ break; ++ } ++ ++ CamOsDebug("eCodecFormat = %d\n", pJpeCfg->eCodecFormat); ++ CamOsDebug("nWidth, nHeight = %d,%d \n", pJpeCfg->nWidth, pJpeCfg->nHeight); ++ CamOsDebug("nQScale = %d \n", pJpeCfg->nQScale); ++ CamOsDebug("InBuf[0].nAddr = 0x%x\n", (int)pJpeCfg->InBuf[0].nAddr); ++ CamOsDebug("InBuf[0].nSize = 0x%x\n", (int)pJpeCfg->InBuf[0].nSize); ++ CamOsDebug("InBuf[1].nAddr = 0x%x\n", (int)pJpeCfg->InBuf[1].nAddr); ++ CamOsDebug("InBuf[1].nSize = 0x%x\n", (int)pJpeCfg->InBuf[1].nSize); ++ CamOsDebug("OutBuf.nAddr = 0x%x\n", (int)pJpeCfg->OutBuf.nAddr); ++ CamOsDebug("OutBuf.nSize = 0x%x\n", (int)pJpeCfg->OutBuf.nSize); ++ } ++} ++#endif ++ ++ ++// input/output buffer should be allocated and assigned before invoke encoder ++#if defined(__linux__) ++void JpeEncode(JpeParam_t* pParam, int nDev) ++{ ++ /* validate params */ ++ int nRet = JPE_IOC_RET_SUCCESS; ++ JpeCaps_t tCaps; ++ JpeBufInfo_t tOutBuf; ++ JpeBitstreamInfo_t tBitInfo; ++ JpeCfg_t *pJpeCfg = &pParam->tJpeCfg; ++ ++#if 0 ++ CamOsDebug("Input Buffer Address : 0x%08x \n", (unsigned int)pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr); ++ CamOsDebug("Output Buffer Address : 0x%08x \n", (unsigned int)pJpeCfg->OutBuf.nAddr); ++ CamOsDebug("Current JPEG Config\n"); ++ _DumpConfig(pJpeCfg); ++#endif ++ ++ do ++ { ++ if(nDev <= 0) ++ { ++ CamOsDebug("invalid nDev\n"); ++ return; ++ } ++ ++ tOutBuf.nAddr = pJpeCfg->OutBuf.nAddr; ++ tOutBuf.nSize = pJpeCfg->OutBuf.nSize; ++ ++ do ++ { ++ nRet = ioctl(nDev, JPE_IOC_GET_CAPS, &tCaps); ++ if(nRet != JPE_IOC_RET_SUCCESS) ++ { ++ CamOsDebug("> JPE_IOC_GET_CAPS Fail , err %d\n", nRet); ++ break; ++ } ++ ++ nRet = ioctl(nDev, JPE_IOC_INIT, pJpeCfg); ++ if(nRet != JPE_IOC_RET_SUCCESS) ++ { ++ CamOsDebug("> JPE_IOC_INIT Fail , err %d\n", nRet); ++ break; ++ } ++ ++#if JPE_DRIVER_VER == 2 ++ { ++ unsigned long nClkSelect = 0; ++ nClkSelect = pParam->nClkSelect; ++ nRet = ioctl(nDev, JPE_IOC_SET_CLOCKRATE, nClkSelect); ++ if(nRet != JPE_IOC_RET_SUCCESS) ++ { ++ CamOsDebug("> JPE_IOC_SET_CLOCKRATE Fail , err %d\n", nRet); ++ break; ++ } ++ } ++#endif ++ ++ /* assign a output buffer */ ++ nRet = ioctl(nDev, JPE_IOC_SET_OUTBUF, &tOutBuf); ++ if(nRet != JPE_IOC_RET_SUCCESS) ++ { ++ CamOsDebug("> JPE_IOC_SET_OUTBUF Fail , err %d\n", nRet); ++ break; ++ } ++ ++ /* HW would continue to encode automatically if previous status is JPE_OUTBUF_FULL_STATE ++ * and JPE_IOC_SET_OUTBUF is set. So JPE_IOC_ENCODE_FRAME is set in the beginning for frame ++ */ ++ /* compress one frame */ ++ nRet = ioctl(nDev, JPE_IOC_ENCODE_FRAME, NULL); ++ if(nRet != JPE_IOC_RET_SUCCESS) ++ { ++ CamOsDebug("> JPE_IOC_ENCODE_FRAME Fail , err %d\n", nRet); ++ break; ++ } ++ ++//TODO: Remove poll operation when new JPE driver is applied ++#if JPE_DRIVER_VER == 1 ++POLL_AGAIN: ++ { ++ int nMaxPollCount = 0; ++ struct pollfd pfd; ++ ++ pfd.fd = nDev; ++ pfd.events = POLLIN | POLLRDNORM; ++ nRet = poll(&pfd, 1, 20); // wait 20ms second. ++ if(nRet == -1) ++ { ++ CamOsDebug("Polling error!!\n"); ++ } ++ else if(nRet == 0) ++ { ++ usleep(5000); // 5ms ++ if(nMaxPollCount<3) ++ { ++ nMaxPollCount++; ++ goto POLL_AGAIN; ++ } ++ CamOsDebug("Polling timeout!! Already try %d times\n", nMaxPollCount); ++ } ++ else if(pfd.revents & (POLLIN | POLLRDNORM)) ++ { ++ CamOsDebug("Data Generated!!\n"); ++ } ++ else ++ { ++ CamOsDebug("Unexpected result!!\n"); ++ } ++ } ++#endif ++ ++ nRet = ioctl(nDev, JPE_IOC_GETBITS, &tBitInfo); ++ if (nRet) ++ { ++ CamOsDebug("%s: JPE_IOC_GETBITS error(%d)\n", __func__, nRet); ++ break; ++ } ++ ++#if 0 ++ CamOsDebug(" tBitInfo is \n"); ++ _DumpBitInfo(&tBitInfo); ++ CamOsDebug(" Encode END\n"); ++#endif ++ pParam->nEncodeSize = tBitInfo.nOutputSize; ++ ++ } ++ while(0); ++ ++ close(nDev); ++ } ++ while(0); ++} ++#endif ++ ++ ++ ++#if defined(__I_SW__) ++void JpeEncode(JpeParam_t* pParam, JpeDev_t* pDev) ++{ ++ /* validate params */ ++ int nRet; ++ JpeCaps_t tCaps; ++ JpeBufInfo_t tOutBuf; ++ JpeBitstreamInfo_t tBitInfo; ++ JpeCfg_t *pJpeCfg = &pParam->tJpeCfg; ++ JpeCtx_t* pCtx = NULL; ++ ++#if 0 ++ CamOsDebug("Input Buffer Address : 0x%08x \n", (unsigned int)pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr); ++ CamOsDebug("Output Buffer Address : 0x%08x \n", (unsigned int)pJpeCfg->OutBuf.nAddr); ++ CamOsDebug("Current JPEG Config\n"); ++ _DumpConfig(pJpeCfg); ++#endif ++ ++ do ++ { ++ if(pDev == NULL) ++ { ++ CamOsDebug("pDev == NULL\n"); ++ break; ++ } ++ ++ pCtx = JpeOpen(pDev, pCtx); ++ if(pCtx == NULL) ++ { ++ CamOsDebug("pCtx == NULL\n"); ++ break; ++ } ++ ++ pCtx->nClkSelect = pParam->nClkSelect; ++ tOutBuf.nAddr = pJpeCfg->OutBuf.nAddr; ++ tOutBuf.nSize = pJpeCfg->OutBuf.nSize; ++ ++ do ++ { ++ nRet = JpeCtxActions(pCtx, JPE_IOC_GET_CAPS, &tCaps); ++ if(JPE_IOC_RET_SUCCESS != nRet) ++ { ++ CamOsDebug("> JPE_IOC_GET_CAPS Fail , err %d\n", nRet); ++ break; ++ } ++ ++ nRet = JpeCtxActions(pCtx, JPE_IOC_INIT, pJpeCfg); ++ if(JPE_IOC_RET_SUCCESS != nRet) ++ { ++ CamOsDebug("> JPE_IOC_INIT Fail , err %d\n", nRet); ++ //_DumpConfig(pJpeCfg); ++ break; ++ } ++ ++ nRet = JpeCtxActions(pCtx, JPE_IOC_SET_OUTBUF, &tOutBuf); ++ if(JPE_IOC_RET_SUCCESS != nRet) ++ { ++ CamOsDebug("> JPE_IOC_SET_OUTBUF Fail , err %d\n", nRet); ++ break; ++ } ++ ++ nRet = JpeCtxActions(pCtx, JPE_IOC_ENCODE_FRAME, &tBitInfo); ++ if(JPE_IOC_RET_SUCCESS != nRet) ++ { ++ CamOsDebug("> JPE_IOC_ENCODE_FRAME Fail , err %d\n", nRet); ++ break; ++ } ++ ++ // If user need get encode data in other function. ++ if(JPE_IOC_RET_SUCCESS != JpeCtxActions(pCtx, JPE_IOC_GETBITS, &tBitInfo)) ++ { ++ CamOsDebug("> JPE_IOC_GETBITS Fail , err %d\n", nRet); ++ break; ++ } ++#if 0 ++ CamOsDebug(" tBitInfo is \n"); ++ _DumpBitInfo(&tBitInfo); ++ CamOsDebug(" Encode END\n"); ++#endif ++ pParam->nEncodeSize = tBitInfo.nOutputSize; ++ ++ } ++ while(0); ++ JpeRelease(pDev, pCtx); ++ } ++ while(0); ++} ++#endif +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/drv_jpe_enc.h b/drivers/mstar/jpe2/drv/test/common/drv_jpe_enc.h +new file mode 100644 +index 00000000..29d67ba7 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/drv_jpe_enc.h +@@ -0,0 +1,44 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __DRV_JPE_ENC_H__ ++#define __DRV_JPE_ENC_H__ ++ ++#define JPE_DRIVER_VER 1 ++//#define JPE_DRIVER_VER 2 ++ ++#if JPE_DRIVER_VER == 1 ++#include "mdrv_jpe_io.h" ++#include "mdrv_jpe_io_st.h" ++#else ++#include "drv_jpe_io.h" ++#include "drv_jpe_io_st.h" ++#endif ++ ++typedef struct ++{ ++ JpeCfg_t tJpeCfg; ++ int nEncodeSize; ++ unsigned short nClkSelect; ++} JpeParam_t; ++ ++#if defined(__I_SW__) ++void JpeEncode(JpeParam_t* pParam, JpeDev_t* pDev); ++#else ++void JpeEncode(JpeParam_t* pParam, int nDev); ++#endif ++#endif // __DRV_JPE_ENC_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/jpegenc_marker.c b/drivers/mstar/jpe2/drv/test/common/jpegenc_marker.c +new file mode 100644 +index 00000000..bd9f1837 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/jpegenc_marker.c +@@ -0,0 +1,508 @@ ++#include ++#include ++#include ++ ++#include "list.h" ++#include "jpegenc_marker.h" ++ ++#define JPG_BOOL_TRUE 1 ++#define JPG_BOOL_FALSE 0 ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Internal structure for JPEG headers // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++typedef struct omx_jpegenc_marker ++{ ++ struct list_head node; ++ u16 size; ++ void *data; ++} omx_jpegenc_marker; ++ ++#pragma pack(push) /* push current alignment to stack */ ++#pragma pack(1) /* set alignment to 1 byte boundary */ ++ ++typedef struct omx_jpegenc_marker_soi ++{ ++ u16 marker; // Start of image marker (FFD8) ++} omx_jpegenc_marker_soi; ++ ++typedef struct omx_jpegenc_marker_app0_jfif ++{ ++ u16 marker; // App0 marker (FFE0) ++ u16 length; // Header length ++ u8 identifier[5]; // "JFIF" string ++ u8 version[2]; // JFIF version ++ u8 density_unit; // 0 = no unit, 1 = pixels per inch, 2 = pixels per centimeter ++ u16 density_x; // Horizontal pixel density. Must not be zero. ++ u16 density_y; // Vertical pixel density. Must not be zero. ++ u8 thumbnail_wdith; // Horizontal pixel count of the following embedded RGB thumbnail. May be zero ++ u8 thumbnail_height; // Vertical pixel count of the following embedded RGB thumbnail. May be zero ++} omx_jpegenc_marker_app0_jfif; ++ ++typedef struct omx_jpegenc_marker_dqt_8 ++{ ++ u16 marker; // Define quantization table marker (FFDB) ++ u16 length; // Hheader length ++ u8 index:4; // Quantization table destination identifier ++ u8 precision:4; // Quantization table element precision. 0 = 8bit, 1 = 16bit ++ u8 dqt_data[64]; // Quantization table entries, 8 bit width ++} omx_jpegenc_marker_dqt_8; ++ ++typedef struct omx_jpegenc_marker_dqt_16 ++{ ++ u16 marker; // Define quantization table marker (FFDB) ++ u16 length; // Hheader length ++ u8 index:4; // Quantization table destination identifier ++ u8 precision:4; // Quantization table element precision. 0: 8bit, 1: 16bit ++ u16 dqt_data[64]; // Quantization table entries, 16 bit width ++} omx_jpegenc_marker_dqt_16; ++ ++typedef struct omx_jpegenc_marker_sof0_yuv ++{ ++ u16 marker; // Baseline DCT marker (FFC0) ++ u16 length; // Hheader length ++ u8 sample_precision; // Sample precision ++ u16 height; // Number of lines ++ u16 width; // Number of samples per line ++ u8 num_components; // Number of image components in frame, yuv is 3 ++ struct ++ { // Conpoment info ++ u8 index; // Component identifier ++ u8 sampling_x:4; // Horizontal sampling factor ++ u8 sampling_y:4; // Vertical sampling factor ++ u8 dqt_idx; // Quantization table destination selector ++ } components[3]; ++} omx_jpegenc_marker_sof0_yuv; ++ ++typedef struct omx_jpegenc_marker_dht_baseline_dc ++{ ++ u16 marker; // Define Huffman table marker (FFC4) ++ u16 length; // Header length ++ u8 index:4; // Huffman table destination identifier ++ u8 class:4; // Table class – 0 = DC table or lossless table, 1 = AC table. ++ u8 code_length[16]; // Number of Huffman codes of length ++ u8 code_table[12]; // Value associated with each Huffman code ++} omx_jpegenc_marker_dht_baseline_dc; ++ ++typedef struct omx_jpegenc_marker_dht_baseline_ac ++{ ++ u16 marker; // Define Huffman table marker (FFC4) ++ u16 length; // Header length ++ u8 index:4; // Huffman table destination identifier ++ u8 class:4; // Table class – 0 = DC table or lossless table, 1 = AC table. ++ u8 code_length[16]; // Number of Huffman codes of length ++ u8 code_table[162]; // Value associated with each Huffman code ++} omx_jpegenc_marker_dht_baseline_ac; ++ ++typedef struct omx_jpegenc_marker_sos_baseline ++{ ++ u16 marker; // Start of scan marker (FFDA) ++ u16 length; // Header length ++ u8 num_components; // Number of image components in scan ++ struct ++ { ++ u8 component_select; // Scan component selector ++ u8 ac_select:4; // AC entropy coding table destination selector ++ u8 dc_select:4; // DC entropy coding table destination selector ++ } select[3]; ++ u8 start_select; // Start of spectral or predictor selection ++ u8 end_select; // End of spectral selection ++ u8 al:4; // Successive approximation bit position high ++ u8 ah:4; // Successive approximation bit position low or point transform ++} omx_jpegenc_marker_sos_baseline; ++ ++#pragma pack(pop) /* push current alignment to stack */ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Macros // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++#if BYTE_ORDER == BIG_ENDIAN ++#define BIG_E_ASSIGN_U16(v) (v) ++ ++#elif BYTE_ORDER == LITTLE_ENDIAN || BYTE_ORDER == PDP_ENDIAN ++static inline u16 _bit_e_assign_u16(u16 v) { return ((v<<8)&0xFF00) | ((v>>8)&0x00FF); } ++#define BIG_E_ASSIGN_U16(v) ((((v)<<8)&0xFF00) | (((v)>>8)&0x00FF))// _bit_e_assign_u16((u16)(v)) ++ ++#else ++#error Unknow endian type.... ++#endif ++ ++#define GET_MARKER(m) (((u16*)((m)->data))[0]) ++#define GET_LENGTH(m) (((u16*)((m)->data))[1]) ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// internal functions // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++static omx_jpegenc_marker* omx_jpegenc_marker_alloc(size_t size, const void* data) ++{ ++ omx_jpegenc_marker *marker; ++ ++ // Allocate buffer ++ marker = malloc(sizeof(omx_jpegenc_marker) + size); ++ if(marker == NULL) ++ return NULL; ++ //JPE_DEBUG(DEB_LEV_PARAMS, "%s()line-%d malloc: %p, size=%u\n", __func__, __LINE__, marker, sizeof(omx_jpegenc_marker) + size); ++ ++ // Assign marker data pointer, force the pointer after marker ++ marker->data = (void*)(&marker[1]);; ++ marker->size = size; ++ ++ // Copy data ++ if(data != NULL) ++ { ++ memcpy(marker->data, data, size); ++ } ++ ++ return marker; ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// internal baseline functions // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++static bool omx_jpegenc_marker_baseline_add_soi(struct list_head *head) ++{ ++ omx_jpegenc_marker *marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_soi), NULL); ++ omx_jpegenc_marker_soi *soi; ++ ++ if(marker == NULL) return JPG_BOOL_FALSE; ++ soi = (omx_jpegenc_marker_soi*)marker->data; ++ ++ // Init SOI data ++ soi->marker = BIG_E_ASSIGN_U16(JPEG_MARKER_SOI); ++ ++ // Add to list ++ list_add_tail(&marker->node, head); ++ ++ return JPG_BOOL_TRUE; ++} ++ ++static const omx_jpegenc_marker_app0_jfif __omx_jpegenc_marker_app0_jfif = { ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_APP0), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_app0_jfif)-2), ++ .identifier = "JFIF", ++ .version = {1, 1}, ++ .density_unit = 2, ++ .density_x = BIG_E_ASSIGN_U16(118), ++ .density_y = BIG_E_ASSIGN_U16(118), ++ .thumbnail_wdith = 0, ++ .thumbnail_height = 0 ++}; ++ ++static bool omx_jpegenc_marker_baseline_add_app0(struct list_head *head) ++{ ++ omx_jpegenc_marker *marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_app0_jfif), &__omx_jpegenc_marker_app0_jfif); ++ ++ if(marker == NULL) ++ return JPG_BOOL_FALSE; ++ ++ list_add_tail(&marker->node, head); ++ ++ return JPG_BOOL_TRUE; ++} ++ ++static const u8 zig_zag_idx[64] = ++{ ++ 0, ++ 1, 8, ++ 16, 9, 2, ++ 3, 10, 17, 24, ++ 32, 25, 18, 11, 4, ++ 5, 12, 19, 26, 33, 40, ++ 48, 41, 34, 27, 20, 13, 6, ++ 7, 14, 21, 28, 35, 42, 49, 56, ++ 57, 50, 43, 36, 29, 22, 15, ++ 23, 30, 37, 44, 51, 58, ++ 59, 52, 45, 38, 31, ++ 39, 46, 53, 60, ++ 61, 54, 47, ++ 55, 62, ++ 63 ++}; ++static bool omx_jpegenc_marker_baseline_add_dqt(struct list_head *head, u16 *y_table, u16 *c_table, u16 scale) ++{ ++ omx_jpegenc_marker *marker; ++ omx_jpegenc_marker_dqt_8 *dqt; ++ u8 i, j; ++ u16 *table = y_table; ++ ++ for(i=0; i<2; i++, table=c_table) ++ { ++ // Assign marker data pointer, force the pointer after marker ++ marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_dqt_8), NULL); ++ if(marker == NULL) return JPG_BOOL_FALSE; ++ dqt = (omx_jpegenc_marker_dqt_8*)marker->data; ++ ++ // Init DQT ++ dqt->marker = BIG_E_ASSIGN_U16(JPEG_MARKER_DQT); ++ dqt->length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_dqt_8)-2); ++ dqt->index = i; ++ dqt->precision = 0; // 8 bit ++ ++ for(j=0; j<64; j++) ++ { ++ dqt->dqt_data[j] = (u8)(((unsigned long)table[zig_zag_idx[j]]*(unsigned long)scale+50)/100); ++ dqt->dqt_data[j] = dqt->dqt_data[j] ? dqt->dqt_data[j] : 1; ++ } ++ ++ // Add to list ++ list_add_tail(&marker->node, head); ++ } ++ ++ return JPG_BOOL_TRUE; ++} ++ ++static const omx_jpegenc_marker_sof0_yuv __omx_jpegenc_marker_sof0_yuv = ++{ ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_SOF0), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_sof0_yuv)-2), ++ .sample_precision = 8, ++ .width = 0, ++ .height = 0, ++ .num_components = 3, ++ .components = { {1,1,2,0}, {2,1,1,1}, {3,1,1,1}} ++}; ++ ++static bool omx_jpegenc_marker_baseline_add_sof(struct list_head *head, bool yuv422, u16 width, u16 height) ++{ ++ omx_jpegenc_marker *marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_sof0_yuv), &__omx_jpegenc_marker_sof0_yuv); ++ omx_jpegenc_marker_sof0_yuv *sof; ++ ++ if(marker == NULL) ++ return JPG_BOOL_FALSE; ++ ++ sof = (omx_jpegenc_marker_sof0_yuv*)marker->data; ++ ++ // Init SOf data ++ sof->height = BIG_E_ASSIGN_U16(height); ++ sof->width = BIG_E_ASSIGN_U16(width); ++ ++ if(yuv422) ++ { ++ sof->components[0].sampling_x = 1; ++ } ++ else ++ { ++ sof->components[0].sampling_x = 2; ++ } ++ ++ // Add to list ++ list_add_tail(&marker->node, head); ++ ++ return JPG_BOOL_TRUE; ++} ++ ++static const omx_jpegenc_marker_dht_baseline_dc __omx_jpegenc_marker_dht_baseline_dc_y = ++{ ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_DHT), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_dht_baseline_dc)-2), ++ .index = 0, ++ .class = 0, ++ .code_length = {0x00, 0x01, 0x05, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, ++ .code_table = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B} ++}; ++ ++static const omx_jpegenc_marker_dht_baseline_ac __omx_jpegenc_marker_dht_baseline_ac_y = ++{ ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_DHT), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_dht_baseline_ac)-2), ++ .index = 0, ++ .class = 1, ++ .code_length = {0x00, 0x02, 0x01, 0x03, 0x03, 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D}, ++ .code_table = {0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, ++ 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, ++ 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, ++ 0x29, 0x2A, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, ++ 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, ++ 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, ++ 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, ++ 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, ++ 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, ++ 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, ++ 0xF9, 0xFA} ++}; ++ ++static const omx_jpegenc_marker_dht_baseline_dc __omx_jpegenc_marker_dht_baseline_dc_c = ++{ ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_DHT), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_dht_baseline_dc)-2), ++ .index = 1, ++ .class = 0, ++ .code_length = {0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00}, ++ .code_table = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B} ++}; ++ ++static const omx_jpegenc_marker_dht_baseline_ac __omx_jpegenc_marker_dht_baseline_ac_c = ++{ ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_DHT), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_dht_baseline_ac)-2), ++ .index = 1, ++ .class = 1, ++ .code_length = {0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, 0x01, 0x02, 0x77}, ++ .code_table = {0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, ++ 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, 0x33, 0x52, 0xF0, ++ 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, 0x19, 0x1A, 0x26, ++ 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, ++ 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, ++ 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, ++ 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, ++ 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, ++ 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, ++ 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, ++ 0xF9, 0xFA} ++}; ++ ++static bool omx_jpegenc_marker_baseline_add_dht(struct list_head *head) ++{ ++ omx_jpegenc_marker *marker; ++ ++ // Allocate buffer for DC DHT of Y ++ marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_dht_baseline_dc), &__omx_jpegenc_marker_dht_baseline_dc_y); ++ if(marker == NULL) return JPG_BOOL_FALSE; ++ list_add_tail(&marker->node, head); ++ ++ // Allocate buffer for AC DHT of Y ++ marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_dht_baseline_ac), &__omx_jpegenc_marker_dht_baseline_ac_y); ++ if(marker == NULL) return JPG_BOOL_FALSE; ++ list_add_tail(&marker->node, head); ++ ++ // Allocate buffer for DC DHT of C ++ marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_dht_baseline_dc), &__omx_jpegenc_marker_dht_baseline_dc_c); ++ if(marker == NULL) return JPG_BOOL_FALSE; ++ list_add_tail(&marker->node, head); ++ ++ // Allocate buffer for AC DHT of C ++ marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_dht_baseline_ac), &__omx_jpegenc_marker_dht_baseline_ac_c); ++ if(marker == NULL) return JPG_BOOL_FALSE; ++ list_add_tail(&marker->node, head); ++ ++ return JPG_BOOL_TRUE; ++} ++ ++static const omx_jpegenc_marker_sos_baseline __omx_jpegenc_marker_sos_baseline = ++{ ++ .marker = BIG_E_ASSIGN_U16(JPEG_MARKER_SOS), ++ .length = BIG_E_ASSIGN_U16(sizeof(omx_jpegenc_marker_sos_baseline)-2), ++ .num_components = 3, ++ .select = {{1,0,0}, {2,1,1}, {3,1,1}}, ++ .start_select = 0, ++ .end_select = 0x3F, ++ .al = 0, ++ .ah = 0 ++}; ++ ++static bool omx_jpegenc_marker_baseline_add_sos(struct list_head *head) ++{ ++ omx_jpegenc_marker *marker = omx_jpegenc_marker_alloc(sizeof(omx_jpegenc_marker_sos_baseline), &__omx_jpegenc_marker_sos_baseline);; ++ ++ if(marker == NULL) ++ return JPG_BOOL_FALSE; ++ ++ list_add_tail(&marker->node, head); ++ ++ return JPG_BOOL_TRUE; ++} ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// External functions // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++void omx_jpegenc_marker_init(struct list_head *head) ++{ ++ INIT_LIST_HEAD(head); ++} ++ ++void omx_jpegenc_marker_release(struct list_head *head) ++{ ++ struct omx_jpegenc_marker *marker, *temp; ++ ++ // Release all buffers ++ list_for_each_entry_safe(marker, temp, head, node) ++ { ++ list_del(&marker->node); ++ free(marker); ++ //JPE_DEBUG(DEB_LEV_PARAMS, "%s()line-%d free: %p\n", __func__, __LINE__, marker); ++ } ++} ++ ++void* omx_jpegenc_marker_create_app_n(struct list_head *head, JPEG_MARKER_TYPE type, u16 size) ++{ ++ struct omx_jpegenc_marker *mk; ++ omx_jpegenc_marker *marker = omx_jpegenc_marker_alloc(size+4, NULL); ++ ++ if(marker == NULL) ++ return NULL; ++ ++ ((u16*)(marker->data))[0] = BIG_E_ASSIGN_U16(type); ++ ((u16*)(marker->data))[1] = BIG_E_ASSIGN_U16(size+2); // The size should be the total length - marker length ++ ++ ++ list_for_each_entry(mk, head, node) ++ { ++ if( GET_MARKER(mk) == BIG_E_ASSIGN_U16(JPEG_MARKER_APP0)) ++ { ++ list_add(&marker->node, &mk->node); ++ break; ++ } ++ } ++ ++ return marker->data + 4; ++} ++ ++int omx_jpegenc_marker_size(struct list_head *head) ++{ ++ omx_jpegenc_marker *marker; ++ int size = 0; ++ ++ list_for_each_entry(marker, head, node) ++ { ++ size += marker->size; ++ } ++ ++ return size; ++} ++ ++int omx_jpegenc_marker_dump(struct list_head *head, u8 *data) ++{ ++ omx_jpegenc_marker *marker; ++ int size = 0; ++ ++ list_for_each_entry(marker, head, node) ++ { ++ memcpy(data + size, marker->data, marker->size); ++ size += marker->size; ++ } ++ ++ return size; ++} ++ ++bool omx_jpegenc_marker_create_baseline(struct list_head *head, bool yuv422, u16 width, u16 height, u16 *dqt_table_y, u16 *dqt_table_c, u16 dqt_scale) ++{ ++ // SOS (FFD8) ++ if(!omx_jpegenc_marker_baseline_add_soi(head)) return JPG_BOOL_FALSE; ++ ++ // APP0 (FFE0) ++ if(!omx_jpegenc_marker_baseline_add_app0(head)) return JPG_BOOL_FALSE; ++ ++ // DQT (FFEB) x 2 ++ if(!omx_jpegenc_marker_baseline_add_dqt(head, dqt_table_y, dqt_table_c, dqt_scale)) return JPG_BOOL_FALSE; ++ ++ // SOF0 (FFC0) ++ if(!omx_jpegenc_marker_baseline_add_sof(head, yuv422, width, height)) return JPG_BOOL_FALSE; ++ ++ // DHT (FFC4) x 4 ++ if(!omx_jpegenc_marker_baseline_add_dht(head)) return JPG_BOOL_FALSE; ++ ++ // SOS (FFDA) ++ if(!omx_jpegenc_marker_baseline_add_sos(head)) return JPG_BOOL_FALSE; ++ ++ return JPG_BOOL_TRUE; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/jpegenc_marker.h b/drivers/mstar/jpe2/drv/test/common/jpegenc_marker.h +new file mode 100644 +index 00000000..f2abe349 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/jpegenc_marker.h +@@ -0,0 +1,198 @@ ++#ifndef _OMX_JPEGENC_MARKER_H_ ++#define _OMX_JPEGENC_MARKER_H_ ++ ++#include ++#include ++//#include ++ ++//#include ++//#include ++ ++#include "sys_MsWrapper_cus_os_msg.h" ++ ++#define MAX_QUANT_TABLE (2) ++#define QUANT_TABLE_SIZE (64) ++ ++ ++//--------------------------------------------------------------------------- ++// Structure and enum. ++//--------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ JPE_IBUF_ROW_MODE = 0x0, ++ JPE_IBUF_FRAME_MODE = 0x1 ++} JpeInBufMode_e; ++ ++typedef enum ++{ ++ JPE_COLOR_PLAN_LUMA = 0, ++ JPE_COLOR_PLAN_CHROMA = 1, ++ JPE_COLOR_PLAN_MAX = 2 ++} JPE_COLOR_PLAN; ++ ++typedef enum ++{ ++ JPE_RAW_YUYV = 0x0, ++ JPE_RAW_YVYU = 0x1, ++ JPE_RAW_NV12 = 0x3, ++ JPE_RAW_NV21 = 0x4, ++} JpeRawFormat_e; ++ ++typedef enum ++{ ++ JPE_CODEC_JPEG = 0x1, ++ JPE_CODEC_H263I = 0x2, ++ JPE_CODEC_ENCODE_DCT = 0x4, ++} JpeCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_IDLE_STATE = 0, ++ JPE_BUSY_STATE = 1, ++ JPE_FRAME_DONE_STATE = 2, ++ JPE_OUTBUF_FULL_STATE = 3, ++ JPE_INBUF_FULL_STATE = 4 ++} JpeState_e; ++ ++typedef enum ++{ ++ JPE_IOC_RET_SUCCESS = 0, ++ JPE_IOC_RET_BAD_QTABLE = 1, ++ JPE_IOC_RET_BAD_QP = 2, ++ JPE_IOC_RET_BAD_BITSOFFSET = 3, ++ JPE_IOC_RET_BAD_BANKNUM = 4, ++ JPE_IOC_RET_BAD_INBUF = 5, ++ JPE_IOC_RET_BAD_OUTBUF = 6, ++ JPE_IOC_RET_BAD_NULLPTR = 7, ++ JPE_IOC_RET_BAD_BANKCNT = 8, ++ JPE_IOC_RET_BAD_LASTZZ = 9, ++ JPE_IOC_RET_UNKOWN_COMMAND = 10, ++ JPE_IOC_RET_BAD_VIRTUAL_MEM = 11, ++ JPE_IOC_RET_NEED_DRIVER_INIT = 12, ++ JPE_IOC_RET_FMT_NOT_SUPPORT = 13, ++ JPE_IOC_RET_HW_IS_RUNNING = 14, ++ JPE_IOC_RET_FAIL = 15 ++} JPE_IOC_RET_STATUS_e; ++ ++typedef struct ++{ ++ u32 u32JpeId; ++ u32 nRefYLogAddrAlign[2]; ++ u32 nRefCLogAddrAlign[2]; ++ u32 nOutBufSLogAddrAlign; ++ u8 nSclHandShakeSupport; ++ u8 nCodecSupport; ++ u8 nBufferModeSupport; ++ ++} JpeCaps_t, *pJpeCaps; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; ++ unsigned long nOutputSize; ++ JpeState_e eState; ++} JpeBitstreamInfo_t, *pJpeBitstreamInfo; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nSize; ++} JpeBufInfo_t, *pJpeBufInfo; ++ ++typedef struct ++{ ++ JpeInBufMode_e eInBufMode; ++ JpeRawFormat_e eRawFormat; ++ JpeCodecFormat_e eCodecFormat; ++ ++ u32 nWidth; ++ u32 nHeight; ++ ++ u16 YQTable[64]; ++ u16 CQTable[64]; ++ u16 nQScale; ++ ++ JpeBufInfo_t InBuf[JPE_COLOR_PLAN_MAX]; ++ ++ JpeBufInfo_t OutBuf; ++ ++ u32 nJpeOutBitOffset; ++} JpeCfg_t, *pJpeCfg; ++ ++ ++#include "list.h" ++ ++typedef enum { ++ JPEG_MARKER_SOF0 = 0xFFC0, ++ JPEG_MARKER_SOF1 = 0xFFC1, ++ JPEG_MARKER_SOF2 = 0xFFC2, ++ JPEG_MARKER_SOF3 = 0xFFC3, ++ ++ JPEG_MARKER_SOF5 = 0xFFC5, ++ JPEG_MARKER_SOF6 = 0xFFC6, ++ JPEG_MARKER_SOF7 = 0xFFC7, ++ ++ JPEG_MARKER_JPG = 0xFFC8, ++ JPEG_MARKER_SOF9 = 0xFFC9, ++ JPEG_MARKER_SOF10 = 0xFFCA, ++ JPEG_MARKER_SOF11 = 0xFFCB, ++ ++ JPEG_MARKER_SOF13 = 0xFFCD, ++ JPEG_MARKER_SOF14 = 0xFFCE, ++ JPEG_MARKER_SOF15 = 0xFFCF, ++ ++ JPEG_MARKER_DHT = 0xFFC4, ++ ++ JPEG_MARKER_DAC = 0xFFCC, ++ ++ JPEG_MARKER_RST0 = 0xFFD0, ++ JPEG_MARKER_RST1 = 0xFFD1, ++ JPEG_MARKER_RST2 = 0xFFD2, ++ JPEG_MARKER_RST3 = 0xFFD3, ++ JPEG_MARKER_RST4 = 0xFFD4, ++ JPEG_MARKER_RST5 = 0xFFD5, ++ JPEG_MARKER_RST6 = 0xFFD6, ++ JPEG_MARKER_RST7 = 0xFFD7, ++ ++ JPEG_MARKER_SOI = 0xFFD8, ++ JPEG_MARKER_EOI = 0xFFD9, ++ JPEG_MARKER_SOS = 0xFFDA, ++ JPEG_MARKER_DQT = 0xFFDB, ++ JPEG_MARKER_DNL = 0xFFDC, ++ JPEG_MARKER_DRI = 0xFFDD, ++ JPEG_MARKER_DHP = 0xFFDE, ++ JPEG_MARKER_EXP = 0xFFDF, ++ ++ JPEG_MARKER_APP0 = 0xFFE0, ++ JPEG_MARKER_APP1 = 0xFFE1, ++ JPEG_MARKER_APP2 = 0xFFE2, ++ JPEG_MARKER_APP3 = 0xFFE3, ++ JPEG_MARKER_APP4 = 0xFFE4, ++ JPEG_MARKER_APP5 = 0xFFE5, ++ JPEG_MARKER_APP6 = 0xFFE6, ++ JPEG_MARKER_APP7 = 0xFFE7, ++ JPEG_MARKER_APP8 = 0xFFE8, ++ JPEG_MARKER_APP9 = 0xFFE9, ++ JPEG_MARKER_APP10 = 0xFFEA, ++ JPEG_MARKER_APP11 = 0xFFEB, ++ JPEG_MARKER_APP12 = 0xFFEC, ++ JPEG_MARKER_APP13 = 0xFFED, ++ JPEG_MARKER_APP14 = 0xFFEE, ++ JPEG_MARKER_APP15 = 0xFFEF, ++ ++ JPEG_MARKER_JPG0 = 0xFFF0, ++ JPEG_MARKER_JPG8 = 0xFFF8, ++ JPEG_MARKER_JPG13 = 0xFFFD, ++ JPEG_MARKER_COM = 0xFFFE ++} JPEG_MARKER_TYPE; ++ ++void omx_jpegenc_marker_init(struct list_head *head); ++void omx_jpegenc_marker_release(struct list_head *head); ++void* omx_jpegenc_marker_create_app_n(struct list_head *head, JPEG_MARKER_TYPE type, u16 size); ++int omx_jpegenc_marker_size(struct list_head *head); ++int omx_jpegenc_marker_dump(struct list_head *head, u8 *data); ++bool omx_jpegenc_marker_create_baseline(struct list_head *head, bool yuv422, u16 width, u16 height, u16 *dqt_table_y, u16 *dqt_table_c, u16 dqt_scale); ++ ++#endif // _OMX_JPEGENC_MARKER_H_ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/list.h b/drivers/mstar/jpe2/drv/test/common/list.h +new file mode 100644 +index 00000000..ecf43d7a +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/list.h +@@ -0,0 +1,766 @@ ++#ifndef _LINUX_LIST_FOR_USERSPACE_H_ ++#define _LINUX_LIST_FOR_USERSPACE_H_ ++ ++struct list_head { ++ struct list_head *next, *prev; ++}; ++ ++struct hlist_head { ++ struct hlist_node *first; ++}; ++ ++struct hlist_node { ++ struct hlist_node *next, **pprev; ++}; ++ ++#ifndef offsetof ++#ifdef __compiler_offsetof ++#define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) ++#else ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++#endif ++#endif ++ ++/** ++ * container_of - cast a member of a structure out to the containing structure ++ * @ptr: the pointer to the member. ++ * @type: the type of the container struct this is embedded in. ++ * @member: the name of the member within the struct. ++ * ++ */ ++#define container_of(ptr, type, member) ({ \ ++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \ ++ (type *)( (char *)__mptr - offsetof(type,member) );}) ++ ++/* ++ * These are non-NULL pointers that will result in page faults ++ * under normal circumstances, used to verify that nobody uses ++ * non-initialized list entries. ++ */ ++#define LIST_POISON1 ((void *) 0x00100100) ++#define LIST_POISON2 ((void *) 0x00200200) ++ ++/* ++ * Simple doubly linked list implementation. ++ * ++ * Some of the internal functions ("__xxx") are useful when ++ * manipulating whole lists rather than single entries, as ++ * sometimes we already know the next/prev entries and we can ++ * generate better code by using them directly rather than ++ * using the generic single-entry routines. ++ */ ++ ++#define LIST_HEAD_INIT(name) { &(name), &(name) } ++ ++#define LIST_HEAD(name) \ ++ struct list_head name = LIST_HEAD_INIT(name) ++ ++static inline void INIT_LIST_HEAD(struct list_head *list) ++{ ++ list->next = list; ++ list->prev = list; ++} ++ ++/* ++ * Insert a new entry between two known consecutive entries. ++ * ++ * This is only for internal list manipulation where we know ++ * the prev/next entries already! ++ */ ++static inline void __list_add(struct list_head *new, ++ struct list_head *prev, ++ struct list_head *next) ++{ ++ next->prev = new; ++ new->next = next; ++ new->prev = prev; ++ prev->next = new; ++} ++ ++/** ++ * list_add - add a new entry ++ * @new: new entry to be added ++ * @head: list head to add it after ++ * ++ * Insert a new entry after the specified head. ++ * This is good for implementing stacks. ++ */ ++static inline void list_add(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head, head->next); ++} ++ ++ ++/** ++ * list_add_tail - add a new entry ++ * @new: new entry to be added ++ * @head: list head to add it before ++ * ++ * Insert a new entry before the specified head. ++ * This is useful for implementing queues. ++ */ ++static inline void list_add_tail(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head->prev, head); ++} ++ ++/* ++ * Delete a list entry by making the prev/next entries ++ * point to each other. ++ * ++ * This is only for internal list manipulation where we know ++ * the prev/next entries already! ++ */ ++static inline void __list_del(struct list_head * prev, struct list_head * next) ++{ ++ next->prev = prev; ++ prev->next = next; ++} ++ ++/** ++ * list_del - deletes entry from list. ++ * @entry: the element to delete from the list. ++ * Note: list_empty() on entry does not return true after this, the entry is ++ * in an undefined state. ++ */ ++static inline void __list_del_entry(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++} ++ ++static inline void list_del(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++ entry->next = LIST_POISON1; ++ entry->prev = LIST_POISON2; ++} ++ ++/** ++ * list_replace - replace old entry by new one ++ * @old : the element to be replaced ++ * @new : the new element to insert ++ * ++ * If @old was empty, it will be overwritten. ++ */ ++static inline void list_replace(struct list_head *old, ++ struct list_head *new) ++{ ++ new->next = old->next; ++ new->next->prev = new; ++ new->prev = old->prev; ++ new->prev->next = new; ++} ++ ++static inline void list_replace_init(struct list_head *old, ++ struct list_head *new) ++{ ++ list_replace(old, new); ++ INIT_LIST_HEAD(old); ++} ++ ++/** ++ * list_del_init - deletes entry from list and reinitialize it. ++ * @entry: the element to delete from the list. ++ */ ++static inline void list_del_init(struct list_head *entry) ++{ ++ __list_del_entry(entry); ++ INIT_LIST_HEAD(entry); ++} ++ ++/** ++ * list_move - delete from one list and add as another's head ++ * @list: the entry to move ++ * @head: the head that will precede our entry ++ */ ++static inline void list_move(struct list_head *list, struct list_head *head) ++{ ++ __list_del_entry(list); ++ list_add(list, head); ++} ++ ++/** ++ * list_move_tail - delete from one list and add as another's tail ++ * @list: the entry to move ++ * @head: the head that will follow our entry ++ */ ++static inline void list_move_tail(struct list_head *list, ++ struct list_head *head) ++{ ++ __list_del_entry(list); ++ list_add_tail(list, head); ++} ++ ++/** ++ * list_is_last - tests whether @list is the last entry in list @head ++ * @list: the entry to test ++ * @head: the head of the list ++ */ ++static inline int list_is_last(const struct list_head *list, ++ const struct list_head *head) ++{ ++ return list->next == head; ++} ++ ++/** ++ * list_empty - tests whether a list is empty ++ * @head: the list to test. ++ */ ++static inline int list_empty(const struct list_head *head) ++{ ++ return head->next == head; ++} ++ ++/** ++ * list_empty_careful - tests whether a list is empty and not being modified ++ * @head: the list to test ++ * ++ * Description: ++ * tests whether a list is empty _and_ checks that no other CPU might be ++ * in the process of modifying either member (next or prev) ++ * ++ * NOTE: using list_empty_careful() without synchronization ++ * can only be safe if the only activity that can happen ++ * to the list entry is list_del_init(). Eg. it cannot be used ++ * if another CPU could re-list_add() it. ++ */ ++static inline int list_empty_careful(const struct list_head *head) ++{ ++ struct list_head *next = head->next; ++ return (next == head) && (next == head->prev); ++} ++ ++/** ++ * list_rotate_left - rotate the list to the left ++ * @head: the head of the list ++ */ ++static inline void list_rotate_left(struct list_head *head) ++{ ++ struct list_head *first; ++ ++ if (!list_empty(head)) { ++ first = head->next; ++ list_move_tail(first, head); ++ } ++} ++ ++/** ++ * list_is_singular - tests whether a list has just one entry. ++ * @head: the list to test. ++ */ ++static inline int list_is_singular(const struct list_head *head) ++{ ++ return !list_empty(head) && (head->next == head->prev); ++} ++ ++static inline void __list_cut_position(struct list_head *list, ++ struct list_head *head, struct list_head *entry) ++{ ++ struct list_head *new_first = entry->next; ++ list->next = head->next; ++ list->next->prev = list; ++ list->prev = entry; ++ entry->next = list; ++ head->next = new_first; ++ new_first->prev = head; ++} ++ ++/** ++ * list_cut_position - cut a list into two ++ * @list: a new list to add all removed entries ++ * @head: a list with entries ++ * @entry: an entry within head, could be the head itself ++ * and if so we won't cut the list ++ * ++ * This helper moves the initial part of @head, up to and ++ * including @entry, from @head to @list. You should ++ * pass on @entry an element you know is on @head. @list ++ * should be an empty list or a list you do not care about ++ * losing its data. ++ * ++ */ ++static inline void list_cut_position(struct list_head *list, ++ struct list_head *head, struct list_head *entry) ++{ ++ if (list_empty(head)) ++ return; ++ if (list_is_singular(head) && ++ (head->next != entry && head != entry)) ++ return; ++ if (entry == head) ++ INIT_LIST_HEAD(list); ++ else ++ __list_cut_position(list, head, entry); ++} ++ ++static inline void __list_splice(const struct list_head *list, ++ struct list_head *prev, ++ struct list_head *next) ++{ ++ struct list_head *first = list->next; ++ struct list_head *last = list->prev; ++ ++ first->prev = prev; ++ prev->next = first; ++ ++ last->next = next; ++ next->prev = last; ++} ++ ++/** ++ * list_splice - join two lists, this is designed for stacks ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ */ ++static inline void list_splice(const struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) ++ __list_splice(list, head, head->next); ++} ++ ++/** ++ * list_splice_tail - join two lists, each list being a queue ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ */ ++static inline void list_splice_tail(struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) ++ __list_splice(list, head->prev, head); ++} ++ ++/** ++ * list_splice_init - join two lists and reinitialise the emptied list. ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ * ++ * The list at @list is reinitialised ++ */ ++static inline void list_splice_init(struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) { ++ __list_splice(list, head, head->next); ++ INIT_LIST_HEAD(list); ++ } ++} ++ ++/** ++ * list_splice_tail_init - join two lists and reinitialise the emptied list ++ * @list: the new list to add. ++ * @head: the place to add it in the first list. ++ * ++ * Each of the lists is a queue. ++ * The list at @list is reinitialised ++ */ ++static inline void list_splice_tail_init(struct list_head *list, ++ struct list_head *head) ++{ ++ if (!list_empty(list)) { ++ __list_splice(list, head->prev, head); ++ INIT_LIST_HEAD(list); ++ } ++} ++ ++/** ++ * list_entry - get the struct for this entry ++ * @ptr: the &struct list_head pointer. ++ * @type: the type of the struct this is embedded in. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_entry(ptr, type, member) \ ++ container_of(ptr, type, member) ++ ++/** ++ * list_first_entry - get the first element from a list ++ * @ptr: the list head to take the element from. ++ * @type: the type of the struct this is embedded in. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Note, that list is expected to be not empty. ++ */ ++#define list_first_entry(ptr, type, member) \ ++ list_entry((ptr)->next, type, member) ++ ++/** ++ * list_last_entry - get the last element from a list ++ * @ptr: the list head to take the element from. ++ * @type: the type of the struct this is embedded in. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Note, that list is expected to be not empty. ++ */ ++#define list_last_entry(ptr, type, member) \ ++ list_entry((ptr)->prev, type, member) ++ ++/** ++ * list_first_entry_or_null - get the first element from a list ++ * @ptr: the list head to take the element from. ++ * @type: the type of the struct this is embedded in. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Note that if the list is empty, it returns NULL. ++ */ ++#define list_first_entry_or_null(ptr, type, member) \ ++ (!list_empty(ptr) ? list_first_entry(ptr, type, member) : NULL) ++ ++/** ++ * list_next_entry - get the next element in list ++ * @pos: the type * to cursor ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_next_entry(pos, member) \ ++ list_entry((pos)->member.next, typeof(*(pos)), member) ++ ++/** ++ * list_prev_entry - get the prev element in list ++ * @pos: the type * to cursor ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_prev_entry(pos, member) \ ++ list_entry((pos)->member.prev, typeof(*(pos)), member) ++ ++/** ++ * list_for_each - iterate over a list ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @head: the head for your list. ++ */ ++#define list_for_each(pos, head) \ ++ for (pos = (head)->next; pos != (head); pos = pos->next) ++ ++/** ++ * list_for_each_prev - iterate over a list backwards ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @head: the head for your list. ++ */ ++#define list_for_each_prev(pos, head) \ ++ for (pos = (head)->prev; pos != (head); pos = pos->prev) ++ ++/** ++ * list_for_each_safe - iterate over a list safe against removal of list entry ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @n: another &struct list_head to use as temporary storage ++ * @head: the head for your list. ++ */ ++#define list_for_each_safe(pos, n, head) \ ++ for (pos = (head)->next, n = pos->next; pos != (head); \ ++ pos = n, n = pos->next) ++ ++/** ++ * list_for_each_prev_safe - iterate over a list backwards safe against removal of list entry ++ * @pos: the &struct list_head to use as a loop cursor. ++ * @n: another &struct list_head to use as temporary storage ++ * @head: the head for your list. ++ */ ++#define list_for_each_prev_safe(pos, n, head) \ ++ for (pos = (head)->prev, n = pos->prev; \ ++ pos != (head); \ ++ pos = n, n = pos->prev) ++ ++/** ++ * list_for_each_entry - iterate over list of given type ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_for_each_entry(pos, head, member) \ ++ for (pos = list_first_entry(head, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = list_next_entry(pos, member)) ++ ++/** ++ * list_for_each_entry_reverse - iterate backwards over list of given type. ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_for_each_entry_reverse(pos, head, member) \ ++ for (pos = list_last_entry(head, typeof(*pos), member); \ ++ &pos->member != (head); \ ++ pos = list_prev_entry(pos, member)) ++ ++/** ++ * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() ++ * @pos: the type * to use as a start point ++ * @head: the head of the list ++ * @member: the name of the list_struct within the struct. ++ * ++ * Prepares a pos entry for use as a start point in list_for_each_entry_continue(). ++ */ ++#define list_prepare_entry(pos, head, member) \ ++ ((pos) ? : list_entry(head, typeof(*pos), member)) ++ ++/** ++ * list_for_each_entry_continue - continue iteration over list of given type ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Continue to iterate over list of given type, continuing after ++ * the current position. ++ */ ++#define list_for_each_entry_continue(pos, head, member) \ ++ for (pos = list_next_entry(pos, member); \ ++ &pos->member != (head); \ ++ pos = list_next_entry(pos, member)) ++ ++/** ++ * list_for_each_entry_continue_reverse - iterate backwards from the given point ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Start to iterate over list of given type backwards, continuing after ++ * the current position. ++ */ ++#define list_for_each_entry_continue_reverse(pos, head, member) \ ++ for (pos = list_prev_entry(pos, member); \ ++ &pos->member != (head); \ ++ pos = list_prev_entry(pos, member)) ++ ++/** ++ * list_for_each_entry_from - iterate over list of given type from the current point ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate over list of given type, continuing from current position. ++ */ ++#define list_for_each_entry_from(pos, head, member) \ ++ for (; &pos->member != (head); \ ++ pos = list_next_entry(pos, member)) ++ ++/** ++ * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ */ ++#define list_for_each_entry_safe(pos, n, head, member) \ ++ for (pos = list_first_entry(head, typeof(*pos), member), \ ++ n = list_next_entry(pos, member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_next_entry(n, member)) ++ ++/** ++ * list_for_each_entry_safe_continue - continue list iteration safe against removal ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate over list of given type, continuing after current point, ++ * safe against removal of list entry. ++ */ ++#define list_for_each_entry_safe_continue(pos, n, head, member) \ ++ for (pos = list_next_entry(pos, member), \ ++ n = list_next_entry(pos, member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_next_entry(n, member)) ++ ++/** ++ * list_for_each_entry_safe_from - iterate over list from current point safe against removal ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate over list of given type from current point, safe against ++ * removal of list entry. ++ */ ++#define list_for_each_entry_safe_from(pos, n, head, member) \ ++ for (n = list_next_entry(pos, member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_next_entry(n, member)) ++ ++/** ++ * list_for_each_entry_safe_reverse - iterate backwards over list safe against removal ++ * @pos: the type * to use as a loop cursor. ++ * @n: another type * to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the list_struct within the struct. ++ * ++ * Iterate backwards over list of given type, safe against removal ++ * of list entry. ++ */ ++#define list_for_each_entry_safe_reverse(pos, n, head, member) \ ++ for (pos = list_last_entry(head, typeof(*pos), member), \ ++ n = list_prev_entry(pos, member); \ ++ &pos->member != (head); \ ++ pos = n, n = list_prev_entry(n, member)) ++ ++/** ++ * list_safe_reset_next - reset a stale list_for_each_entry_safe loop ++ * @pos: the loop cursor used in the list_for_each_entry_safe loop ++ * @n: temporary storage used in list_for_each_entry_safe ++ * @member: the name of the list_struct within the struct. ++ * ++ * list_safe_reset_next is not safe to use in general if the list may be ++ * modified concurrently (eg. the lock is dropped in the loop body). An ++ * exception to this is if the cursor element (pos) is pinned in the list, ++ * and list_safe_reset_next is called after re-taking the lock and before ++ * completing the current iteration of the loop body. ++ */ ++#define list_safe_reset_next(pos, n, member) \ ++ n = list_next_entry(pos, member) ++ ++/* ++ * Double linked lists with a single pointer list head. ++ * Mostly useful for hash tables where the two pointer list head is ++ * too wasteful. ++ * You lose the ability to access the tail in O(1). ++ */ ++ ++#define HLIST_HEAD_INIT { .first = NULL } ++#define HLIST_HEAD(name) struct hlist_head name = { .first = NULL } ++#define INIT_HLIST_HEAD(ptr) ((ptr)->first = NULL) ++static inline void INIT_HLIST_NODE(struct hlist_node *h) ++{ ++ h->next = NULL; ++ h->pprev = NULL; ++} ++ ++static inline int hlist_unhashed(const struct hlist_node *h) ++{ ++ return !h->pprev; ++} ++ ++static inline int hlist_empty(const struct hlist_head *h) ++{ ++ return !h->first; ++} ++ ++static inline void __hlist_del(struct hlist_node *n) ++{ ++ struct hlist_node *next = n->next; ++ struct hlist_node **pprev = n->pprev; ++ *pprev = next; ++ if (next) ++ next->pprev = pprev; ++} ++ ++static inline void hlist_del(struct hlist_node *n) ++{ ++ __hlist_del(n); ++ n->next = LIST_POISON1; ++ n->pprev = LIST_POISON2; ++} ++ ++static inline void hlist_del_init(struct hlist_node *n) ++{ ++ if (!hlist_unhashed(n)) { ++ __hlist_del(n); ++ INIT_HLIST_NODE(n); ++ } ++} ++ ++static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) ++{ ++ struct hlist_node *first = h->first; ++ n->next = first; ++ if (first) ++ first->pprev = &n->next; ++ h->first = n; ++ n->pprev = &h->first; ++} ++ ++/* next must be != NULL */ ++static inline void hlist_add_before(struct hlist_node *n, ++ struct hlist_node *next) ++{ ++ n->pprev = next->pprev; ++ n->next = next; ++ next->pprev = &n->next; ++ *(n->pprev) = n; ++} ++ ++static inline void hlist_add_behind(struct hlist_node *n, ++ struct hlist_node *prev) ++{ ++ n->next = prev->next; ++ prev->next = n; ++ n->pprev = &prev->next; ++ ++ if (n->next) ++ n->next->pprev = &n->next; ++} ++ ++/* after that we'll appear to be on some hlist and hlist_del will work */ ++static inline void hlist_add_fake(struct hlist_node *n) ++{ ++ n->pprev = &n->next; ++} ++ ++/* ++ * Move a list from one list head to another. Fixup the pprev ++ * reference of the first entry if it exists. ++ */ ++static inline void hlist_move_list(struct hlist_head *old, ++ struct hlist_head *new) ++{ ++ new->first = old->first; ++ if (new->first) ++ new->first->pprev = &new->first; ++ old->first = NULL; ++} ++ ++#define hlist_entry(ptr, type, member) container_of(ptr,type,member) ++ ++#define hlist_for_each(pos, head) \ ++ for (pos = (head)->first; pos ; pos = pos->next) ++ ++#define hlist_for_each_safe(pos, n, head) \ ++ for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ ++ pos = n) ++ ++#define hlist_entry_safe(ptr, type, member) \ ++ ({ typeof(ptr) ____ptr = (ptr); \ ++ ____ptr ? hlist_entry(____ptr, type, member) : NULL; \ ++ }) ++ ++/** ++ * hlist_for_each_entry - iterate over list of given type ++ * @pos: the type * to use as a loop cursor. ++ * @head: the head for your list. ++ * @member: the name of the hlist_node within the struct. ++ */ ++#define hlist_for_each_entry(pos, head, member) \ ++ for (pos = hlist_entry_safe((head)->first, typeof(*(pos)), member);\ ++ pos; \ ++ pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) ++ ++/** ++ * hlist_for_each_entry_continue - iterate over a hlist continuing after current point ++ * @pos: the type * to use as a loop cursor. ++ * @member: the name of the hlist_node within the struct. ++ */ ++#define hlist_for_each_entry_continue(pos, member) \ ++ for (pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member);\ ++ pos; \ ++ pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) ++ ++/** ++ * hlist_for_each_entry_from - iterate over a hlist continuing from current point ++ * @pos: the type * to use as a loop cursor. ++ * @member: the name of the hlist_node within the struct. ++ */ ++#define hlist_for_each_entry_from(pos, member) \ ++ for (; pos; \ ++ pos = hlist_entry_safe((pos)->member.next, typeof(*(pos)), member)) ++ ++/** ++ * hlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry ++ * @pos: the type * to use as a loop cursor. ++ * @n: another &struct hlist_node to use as temporary storage ++ * @head: the head for your list. ++ * @member: the name of the hlist_node within the struct. ++ */ ++#define hlist_for_each_entry_safe(pos, n, head, member) \ ++ for (pos = hlist_entry_safe((head)->first, typeof(*pos), member);\ ++ pos && ({ n = pos->member.next; 1; }); \ ++ pos = hlist_entry_safe(n, typeof(*pos), member)) ++ ++#endif // _LINUX_LIST_FOR_USERSPACE_H_ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/md5.c b/drivers/mstar/jpe2/drv/test/common/md5.c +new file mode 100644 +index 00000000..292cfcc0 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/md5.c +@@ -0,0 +1,416 @@ ++/* ++ Copyright (C) 1999, 2000, 2002 Aladdin Enterprises. All rights reserved. ++ ++ This software is provided 'as-is', without any express or implied ++ warranty. In no event will the authors be held liable for any damages ++ arising from the use of this software. ++ ++ Permission is granted to anyone to use this software for any purpose, ++ including commercial applications, and to alter it and redistribute it ++ freely, subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you must not ++ claim that you wrote the original software. If you use this software ++ in a product, an acknowledgment in the product documentation would be ++ appreciated but is not required. ++ 2. Altered source versions must be plainly marked as such, and must not be ++ misrepresented as being the original software. ++ 3. This notice may not be removed or altered from any source distribution. ++ ++ L. Peter Deutsch ++ ghost@aladdin.com ++ ++ */ ++/* $Id: md5.c,v 1.6 2002/04/13 19:20:28 lpd Exp $ */ ++/* ++ Independent implementation of MD5 (RFC 1321). ++ ++ This code implements the MD5 Algorithm defined in RFC 1321, whose ++ text is available at ++ http://www.ietf.org/rfc/rfc1321.txt ++ The code is derived from the text of the RFC, including the test suite ++ (section A.5) but excluding the rest of Appendix A. It does not include ++ any code or documentation that is identified in the RFC as being ++ copyrighted. ++ ++ The original and principal author of md5.c is L. Peter Deutsch ++ . Other authors are noted in the change history ++ that follows (in reverse chronological order): ++ ++ 2002-04-13 lpd Clarified derivation from RFC 1321; now handles byte order ++ either statically or dynamically; added missing #include ++ in library. ++ 2002-03-11 lpd Corrected argument list for main(), and added int return ++ type, in test program and T value program. ++ 2002-02-21 lpd Added missing #include in test program. ++ 2000-07-03 lpd Patched to eliminate warnings about "constant is ++ unsigned in ANSI C, signed in traditional"; made test program ++ self-checking. ++ 1999-11-04 lpd Edited comments slightly for automatic TOC extraction. ++ 1999-10-18 lpd Fixed typo in header comment (ansi2knr rather than md5). ++ 1999-05-03 lpd Original version. ++ */ ++#include ++#include ++#include "md5.h" ++ ++#undef BYTE_ORDER /* 1 = big-endian, -1 = little-endian, 0 = unknown */ ++#ifdef ARCH_IS_BIG_ENDIAN ++# define BYTE_ORDER (ARCH_IS_BIG_ENDIAN ? 1 : -1) ++#else ++# define BYTE_ORDER 0 ++#endif ++ ++#define T_MASK ((Md5Word_t)~0) ++#define T1 /* 0xd76aa478 */ (T_MASK ^ 0x28955b87) ++#define T2 /* 0xe8c7b756 */ (T_MASK ^ 0x173848a9) ++#define T3 0x242070db ++#define T4 /* 0xc1bdceee */ (T_MASK ^ 0x3e423111) ++#define T5 /* 0xf57c0faf */ (T_MASK ^ 0x0a83f050) ++#define T6 0x4787c62a ++#define T7 /* 0xa8304613 */ (T_MASK ^ 0x57cfb9ec) ++#define T8 /* 0xfd469501 */ (T_MASK ^ 0x02b96afe) ++#define T9 0x698098d8 ++#define T10 /* 0x8b44f7af */ (T_MASK ^ 0x74bb0850) ++#define T11 /* 0xffff5bb1 */ (T_MASK ^ 0x0000a44e) ++#define T12 /* 0x895cd7be */ (T_MASK ^ 0x76a32841) ++#define T13 0x6b901122 ++#define T14 /* 0xfd987193 */ (T_MASK ^ 0x02678e6c) ++#define T15 /* 0xa679438e */ (T_MASK ^ 0x5986bc71) ++#define T16 0x49b40821 ++#define T17 /* 0xf61e2562 */ (T_MASK ^ 0x09e1da9d) ++#define T18 /* 0xc040b340 */ (T_MASK ^ 0x3fbf4cbf) ++#define T19 0x265e5a51 ++#define T20 /* 0xe9b6c7aa */ (T_MASK ^ 0x16493855) ++#define T21 /* 0xd62f105d */ (T_MASK ^ 0x29d0efa2) ++#define T22 0x02441453 ++#define T23 /* 0xd8a1e681 */ (T_MASK ^ 0x275e197e) ++#define T24 /* 0xe7d3fbc8 */ (T_MASK ^ 0x182c0437) ++#define T25 0x21e1cde6 ++#define T26 /* 0xc33707d6 */ (T_MASK ^ 0x3cc8f829) ++#define T27 /* 0xf4d50d87 */ (T_MASK ^ 0x0b2af278) ++#define T28 0x455a14ed ++#define T29 /* 0xa9e3e905 */ (T_MASK ^ 0x561c16fa) ++#define T30 /* 0xfcefa3f8 */ (T_MASK ^ 0x03105c07) ++#define T31 0x676f02d9 ++#define T32 /* 0x8d2a4c8a */ (T_MASK ^ 0x72d5b375) ++#define T33 /* 0xfffa3942 */ (T_MASK ^ 0x0005c6bd) ++#define T34 /* 0x8771f681 */ (T_MASK ^ 0x788e097e) ++#define T35 0x6d9d6122 ++#define T36 /* 0xfde5380c */ (T_MASK ^ 0x021ac7f3) ++#define T37 /* 0xa4beea44 */ (T_MASK ^ 0x5b4115bb) ++#define T38 0x4bdecfa9 ++#define T39 /* 0xf6bb4b60 */ (T_MASK ^ 0x0944b49f) ++#define T40 /* 0xbebfbc70 */ (T_MASK ^ 0x4140438f) ++#define T41 0x289b7ec6 ++#define T42 /* 0xeaa127fa */ (T_MASK ^ 0x155ed805) ++#define T43 /* 0xd4ef3085 */ (T_MASK ^ 0x2b10cf7a) ++#define T44 0x04881d05 ++#define T45 /* 0xd9d4d039 */ (T_MASK ^ 0x262b2fc6) ++#define T46 /* 0xe6db99e5 */ (T_MASK ^ 0x1924661a) ++#define T47 0x1fa27cf8 ++#define T48 /* 0xc4ac5665 */ (T_MASK ^ 0x3b53a99a) ++#define T49 /* 0xf4292244 */ (T_MASK ^ 0x0bd6ddbb) ++#define T50 0x432aff97 ++#define T51 /* 0xab9423a7 */ (T_MASK ^ 0x546bdc58) ++#define T52 /* 0xfc93a039 */ (T_MASK ^ 0x036c5fc6) ++#define T53 0x655b59c3 ++#define T54 /* 0x8f0ccc92 */ (T_MASK ^ 0x70f3336d) ++#define T55 /* 0xffeff47d */ (T_MASK ^ 0x00100b82) ++#define T56 /* 0x85845dd1 */ (T_MASK ^ 0x7a7ba22e) ++#define T57 0x6fa87e4f ++#define T58 /* 0xfe2ce6e0 */ (T_MASK ^ 0x01d3191f) ++#define T59 /* 0xa3014314 */ (T_MASK ^ 0x5cfebceb) ++#define T60 0x4e0811a1 ++#define T61 /* 0xf7537e82 */ (T_MASK ^ 0x08ac817d) ++#define T62 /* 0xbd3af235 */ (T_MASK ^ 0x42c50dca) ++#define T63 0x2ad7d2bb ++#define T64 /* 0xeb86d391 */ (T_MASK ^ 0x14792c6e) ++ ++ ++static void ++_Md5_process(md5_state_t *pms, const Md5Byte_t *data /*[64]*/) ++{ ++ Md5Word_t ++ a = pms->abcd[0], b = pms->abcd[1], ++ c = pms->abcd[2], d = pms->abcd[3]; ++ Md5Word_t t; ++#if BYTE_ORDER > 0 ++ /* Define storage only for big-endian CPUs. */ ++ Md5Word_t X[16]; ++#else ++ /* Define storage for little-endian or both types of CPUs. */ ++ Md5Word_t xbuf[16]; ++ const Md5Word_t *X; ++#endif ++ ++ { ++#if BYTE_ORDER == 0 ++ /* ++ * Determine dynamically whether this is a big-endian or ++ * little-endian machine, since we can use a more efficient ++ * algorithm on the latter. ++ */ ++ static const int w = 1; ++ ++ if(*((const Md5Byte_t *)&w)) /* dynamic little-endian */ ++#endif ++#if BYTE_ORDER <= 0 /* little-endian */ ++ { ++ /* ++ * On little-endian machines, we can process properly aligned ++ * data without copying it. ++ */ ++ if(!((data - (const Md5Byte_t *)0) & 3)) ++ { ++ /* data are properly aligned */ ++ X = (const Md5Word_t *)data; ++ } ++ else ++ { ++ /* not aligned */ ++ memcpy((unsigned char*)xbuf, (unsigned char*)data, 64); ++ X = xbuf; ++ } ++ } ++#endif ++#if BYTE_ORDER == 0 ++ else /* dynamic big-endian */ ++#endif ++#if BYTE_ORDER >= 0 /* big-endian */ ++ { ++ /* ++ * On big-endian machines, we must arrange the bytes in the ++ * right order. ++ */ ++ const Md5Byte_t *xp = data; ++ int i; ++ ++# if BYTE_ORDER == 0 ++ X = xbuf; /* (dynamic only) */ ++# else ++# define xbuf X /* (static only) */ ++# endif ++ for(i = 0; i < 16; ++i, xp += 4) ++ xbuf[i] = xp[0] + (xp[1] << 8) + (xp[2] << 16) + (xp[3] << 24); ++ } ++#endif ++ } ++ ++#define ROTATE_LEFT(x, n) (((x) << (n)) | ((x) >> (32 - (n)))) ++ ++ /* Round 1. */ ++ /* Let [abcd k s i] denote the operation ++ a = b + ((a + F(b,c,d) + X[k] + T[i]) <<< s). */ ++#define F(x, y, z) (((x) & (y)) | (~(x) & (z))) ++#define SET(a, b, c, d, k, s, Ti)\ ++ t = a + F(b,c,d) + X[k] + Ti;\ ++ a = ROTATE_LEFT(t, s) + b ++ /* Do the following 16 operations. */ ++ SET(a, b, c, d, 0, 7, T1); ++ SET(d, a, b, c, 1, 12, T2); ++ SET(c, d, a, b, 2, 17, T3); ++ SET(b, c, d, a, 3, 22, T4); ++ SET(a, b, c, d, 4, 7, T5); ++ SET(d, a, b, c, 5, 12, T6); ++ SET(c, d, a, b, 6, 17, T7); ++ SET(b, c, d, a, 7, 22, T8); ++ SET(a, b, c, d, 8, 7, T9); ++ SET(d, a, b, c, 9, 12, T10); ++ SET(c, d, a, b, 10, 17, T11); ++ SET(b, c, d, a, 11, 22, T12); ++ SET(a, b, c, d, 12, 7, T13); ++ SET(d, a, b, c, 13, 12, T14); ++ SET(c, d, a, b, 14, 17, T15); ++ SET(b, c, d, a, 15, 22, T16); ++#undef SET ++ ++ /* Round 2. */ ++ /* Let [abcd k s i] denote the operation ++ a = b + ((a + G(b,c,d) + X[k] + T[i]) <<< s). */ ++#define G(x, y, z) (((x) & (z)) | ((y) & ~(z))) ++#define SET(a, b, c, d, k, s, Ti)\ ++ t = a + G(b,c,d) + X[k] + Ti;\ ++ a = ROTATE_LEFT(t, s) + b ++ /* Do the following 16 operations. */ ++ SET(a, b, c, d, 1, 5, T17); ++ SET(d, a, b, c, 6, 9, T18); ++ SET(c, d, a, b, 11, 14, T19); ++ SET(b, c, d, a, 0, 20, T20); ++ SET(a, b, c, d, 5, 5, T21); ++ SET(d, a, b, c, 10, 9, T22); ++ SET(c, d, a, b, 15, 14, T23); ++ SET(b, c, d, a, 4, 20, T24); ++ SET(a, b, c, d, 9, 5, T25); ++ SET(d, a, b, c, 14, 9, T26); ++ SET(c, d, a, b, 3, 14, T27); ++ SET(b, c, d, a, 8, 20, T28); ++ SET(a, b, c, d, 13, 5, T29); ++ SET(d, a, b, c, 2, 9, T30); ++ SET(c, d, a, b, 7, 14, T31); ++ SET(b, c, d, a, 12, 20, T32); ++#undef SET ++ ++ /* Round 3. */ ++ /* Let [abcd k s t] denote the operation ++ a = b + ((a + H(b,c,d) + X[k] + T[i]) <<< s). */ ++#define H(x, y, z) ((x) ^ (y) ^ (z)) ++#define SET(a, b, c, d, k, s, Ti)\ ++ t = a + H(b,c,d) + X[k] + Ti;\ ++ a = ROTATE_LEFT(t, s) + b ++ /* Do the following 16 operations. */ ++ SET(a, b, c, d, 5, 4, T33); ++ SET(d, a, b, c, 8, 11, T34); ++ SET(c, d, a, b, 11, 16, T35); ++ SET(b, c, d, a, 14, 23, T36); ++ SET(a, b, c, d, 1, 4, T37); ++ SET(d, a, b, c, 4, 11, T38); ++ SET(c, d, a, b, 7, 16, T39); ++ SET(b, c, d, a, 10, 23, T40); ++ SET(a, b, c, d, 13, 4, T41); ++ SET(d, a, b, c, 0, 11, T42); ++ SET(c, d, a, b, 3, 16, T43); ++ SET(b, c, d, a, 6, 23, T44); ++ SET(a, b, c, d, 9, 4, T45); ++ SET(d, a, b, c, 12, 11, T46); ++ SET(c, d, a, b, 15, 16, T47); ++ SET(b, c, d, a, 2, 23, T48); ++#undef SET ++ ++ /* Round 4. */ ++ /* Let [abcd k s t] denote the operation ++ a = b + ((a + I(b,c,d) + X[k] + T[i]) <<< s). */ ++#define I(x, y, z) ((y) ^ ((x) | ~(z))) ++#define SET(a, b, c, d, k, s, Ti)\ ++ t = a + I(b,c,d) + X[k] + Ti;\ ++ a = ROTATE_LEFT(t, s) + b ++ /* Do the following 16 operations. */ ++ SET(a, b, c, d, 0, 6, T49); ++ SET(d, a, b, c, 7, 10, T50); ++ SET(c, d, a, b, 14, 15, T51); ++ SET(b, c, d, a, 5, 21, T52); ++ SET(a, b, c, d, 12, 6, T53); ++ SET(d, a, b, c, 3, 10, T54); ++ SET(c, d, a, b, 10, 15, T55); ++ SET(b, c, d, a, 1, 21, T56); ++ SET(a, b, c, d, 8, 6, T57); ++ SET(d, a, b, c, 15, 10, T58); ++ SET(c, d, a, b, 6, 15, T59); ++ SET(b, c, d, a, 13, 21, T60); ++ SET(a, b, c, d, 4, 6, T61); ++ SET(d, a, b, c, 11, 10, T62); ++ SET(c, d, a, b, 2, 15, T63); ++ SET(b, c, d, a, 9, 21, T64); ++#undef SET ++ ++ /* Then perform the following additions. (That is increment each ++ of the four registers by the value it had before this block ++ was started.) */ ++ pms->abcd[0] += a; ++ pms->abcd[1] += b; ++ pms->abcd[2] += c; ++ pms->abcd[3] += d; ++} ++ ++void ++Md5Init(md5_state_t *pms) ++{ ++ pms->count[0] = pms->count[1] = 0; ++ pms->abcd[0] = 0x67452301; ++ pms->abcd[1] = /*0xefcdab89*/ T_MASK ^ 0x10325476; ++ pms->abcd[2] = /*0x98badcfe*/ T_MASK ^ 0x67452301; ++ pms->abcd[3] = 0x10325476; ++} ++ ++void ++Md5Append(md5_state_t *pms, const Md5Byte_t *data, int nbytes) ++{ ++ const Md5Byte_t *p = data; ++ int left = nbytes; ++ int offset = (pms->count[0] >> 3) & 63; ++ Md5Word_t nbits = (Md5Word_t)(nbytes << 3); ++ ++ if(nbytes <= 0) ++ return; ++ ++ /* Update the message length. */ ++ pms->count[1] += nbytes >> 29; ++ pms->count[0] += nbits; ++ if(pms->count[0] < nbits) ++ pms->count[1]++; ++ ++ /* Process an initial partial block. */ ++ if(offset) ++ { ++ int copy = (offset + nbytes > 64 ? 64 - offset : nbytes); ++ ++ memcpy((unsigned char*)pms->buf + offset, (unsigned char*)p, copy); ++ if(offset + copy < 64) ++ return; ++ p += copy; ++ left -= copy; ++ _Md5_process(pms, pms->buf); ++ } ++ ++ /* Process full blocks. */ ++ for(; left >= 64; p += 64, left -= 64) ++ _Md5_process(pms, p); ++ ++ /* Process a final partial block. */ ++ if(left) ++ memcpy((unsigned char*)pms->buf, (unsigned char*)p, left); ++} ++ ++void ++Md5Finish(md5_state_t *pms, Md5Byte_t digest[16]) ++{ ++ static const Md5Byte_t pad[64] = ++ { ++ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ++ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ++ }; ++ Md5Byte_t data[8]; ++ int i; ++ ++ /* Save the length before padding. */ ++ for(i = 0; i < 8; ++i) ++ data[i] = (Md5Byte_t)(pms->count[i >> 2] >> ((i & 3) << 3)); ++ /* Pad to 56 bytes mod 64. */ ++ Md5Append(pms, pad, ((55 - (pms->count[0] >> 3)) & 63) + 1); ++ /* Append the length. */ ++ Md5Append(pms, data, 8); ++ for(i = 0; i < 16; ++i) ++ digest[i] = (Md5Byte_t)(pms->abcd[i >> 2] >> ((i & 3) << 3)); ++} ++ ++/* ++ ********************************************************************** ++ ** md5driver.c -- sample routines to test ** ++ ** RSA Data Security, Inc. MD5 message digest algorithm. ** ++ ** Created: 2/16/90 RLR ** ++ ** Updated: 1/91 SRD ** ++ ********************************************************************** ++ */ ++ ++/* ++ ********************************************************************** ++ ** Copyright (C) 1990, RSA Data Security, Inc. All rights reserved. ** ++ ** ** ++ ** RSA Data Security, Inc. makes no representations concerning ** ++ ** either the merchantability of this software or the suitability ** ++ ** of this software for any particular purpose. It is provided "as ** ++ ** is" without express or implied warranty of any kind. ** ++ ** ** ++ ** These notices must be retained in any copies of any part of this ** ++ ** documentation and/or software. ** ++ ********************************************************************** ++ */ ++ ++ ++/* ++ ********************************************************************** ++ ** End of md5driver.c ** ++ ******************************* (cut) ******************************** ++ */ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/md5.h b/drivers/mstar/jpe2/drv/test/common/md5.h +new file mode 100644 +index 00000000..f0f54cc0 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/md5.h +@@ -0,0 +1,92 @@ ++/* ++ Copyright (C) 1999, 2002 Aladdin Enterprises. All rights reserved. ++ ++ This software is provided 'as-is', without any express or implied ++ warranty. In no event will the authors be held liable for any damages ++ arising from the use of this software. ++ ++ Permission is granted to anyone to use this software for any purpose, ++ including commercial applications, and to alter it and redistribute it ++ freely, subject to the following restrictions: ++ ++ 1. The origin of this software must not be misrepresented; you must not ++ claim that you wrote the original software. If you use this software ++ in a product, an acknowledgment in the product documentation would be ++ appreciated but is not required. ++ 2. Altered source versions must be plainly marked as such, and must not be ++ misrepresented as being the original software. ++ 3. This notice may not be removed or altered from any source distribution. ++ ++ L. Peter Deutsch ++ ghost@aladdin.com ++ ++ */ ++/* $Id: md5.h,v 1.4 2002/04/13 19:20:28 lpd Exp $ */ ++/* ++ Independent implementation of MD5 (RFC 1321). ++ ++ This code implements the MD5 Algorithm defined in RFC 1321, whose ++ text is available at ++ http://www.ietf.org/rfc/rfc1321.txt ++ The code is derived from the text of the RFC, including the test suite ++ (section A.5) but excluding the rest of Appendix A. It does not include ++ any code or documentation that is identified in the RFC as being ++ copyrighted. ++ ++ The original and principal author of md5.h is L. Peter Deutsch ++ . Other authors are noted in the change history ++ that follows (in reverse chronological order): ++ ++ 2002-04-13 lpd Removed support for non-ANSI compilers; removed ++ references to Ghostscript; clarified derivation from RFC 1321; ++ now handles byte order either statically or dynamically. ++ 1999-11-04 lpd Edited comments slightly for automatic TOC extraction. ++ 1999-10-18 lpd Fixed typo in header comment (ansi2knr rather than md5); ++ added conditionalization for C++ compilation from Martin ++ Purschke . ++ 1999-05-03 lpd Original version. ++ */ ++ ++#ifndef __MD5_H__ ++# define __MD5_H__ ++ ++/* ++ * This package supports both compile-time and run-time determination of CPU ++ * byte order. If ARCH_IS_BIG_ENDIAN is defined as 0, the code will be ++ * compiled to run only on little-endian CPUs; if ARCH_IS_BIG_ENDIAN is ++ * defined as non-zero, the code will be compiled to run only on big-endian ++ * CPUs; if ARCH_IS_BIG_ENDIAN is not defined, the code will be compiled to ++ * run on either big- or little-endian CPUs, but will run slightly less ++ * efficiently on either one than if ARCH_IS_BIG_ENDIAN is defined. ++ */ ++ ++typedef unsigned char Md5Byte_t; /* 8-bit byte */ ++typedef unsigned int Md5Word_t; /* 32-bit word */ ++ ++/* Define the state of the MD5 Algorithm. */ ++typedef struct md5_state_s ++{ ++ Md5Word_t count[2]; /* message length in bits, lsw first */ ++ Md5Word_t abcd[4]; /* digest buffer */ ++ Md5Byte_t buf[64]; /* accumulate block */ ++} md5_state_t; ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++/* Initialize the algorithm. */ ++void Md5Init(md5_state_t *pms); ++ ++/* Append a string to the message. */ ++void Md5Append(md5_state_t *pms, const Md5Byte_t *data, int nbytes); ++ ++/* Finish the message and return the digest. */ ++void Md5Finish(md5_state_t *pms, Md5Byte_t digest[16]); ++ ++#ifdef __cplusplus ++} /* end extern "C" */ ++#endif ++ ++#endif //` __MD5_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/util_pattern.c b/drivers/mstar/jpe2/drv/test/common/util_pattern.c +new file mode 100644 +index 00000000..12a81977 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/util_pattern.c +@@ -0,0 +1,498 @@ ++/* ++ * Copyright 2008 Tungsten Graphics ++ * Jakob Bornecrantz ++ * Copyright 2008 Intel Corporation ++ * Jesse Barnes ++ * ++ * Permission is hereby granted, free of charge, to any person obtaining a ++ * copy of this software and associated documentation files (the "Software"), ++ * to deal in the Software without restriction, including without limitation ++ * the rights to use, copy, modify, merge, publish, distribute, sublicense, ++ * and/or sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be included in ++ * all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR ++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, ++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE ++ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER ++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS ++ * IN THE SOFTWARE. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "util_pattern.h" ++ ++// From format.c ++#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) ++ ++#define MAKE_YUV_INFO(order, xsub, ysub, chroma_stride) \ ++ .yuv = { (order), (xsub), (ysub), (chroma_stride) } ++ ++static const UtilFormatInfo_t format_info[] = ++{ ++ /* YUV packed */ ++ { DRM_FORMAT_YUYV, "YUYV", MAKE_YUV_INFO(YUV_YCbCr | YUV_YC, 2, 2, 2) }, ++ { DRM_FORMAT_YVYU, "YVYU", MAKE_YUV_INFO(YUV_YCrCb | YUV_YC, 2, 2, 2) }, ++ /* YUV semi-planar */ ++ { DRM_FORMAT_NV12, "NV12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 2) }, ++ { DRM_FORMAT_NV21, "NV21", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 2) }, ++}; ++ ++uint32_t util_format_fourcc(const char *name) ++{ ++ unsigned int i; ++ ++ for(i = 0; i < ARRAY_SIZE(format_info); i++) ++ if(!strcmp(format_info[i].name, name)) ++ return format_info[i].format; ++ ++ return 0; ++} ++ ++const UtilFormatInfo_t *util_format_info_find(uint32_t format) ++{ ++ unsigned int i; ++ ++ for(i = 0; i < ARRAY_SIZE(format_info); i++) ++ if(format_info[i].format == format) ++ return &format_info[i]; ++ ++ return NULL; ++} ++ ++// From pattern.c ++struct color_yuv ++{ ++ unsigned char y; ++ unsigned char u; ++ unsigned char v; ++}; ++ ++#define MAKE_YUV_601_Y(r, g, b) \ ++ ((( 66 * (r) + 129 * (g) + 25 * (b) + 128) >> 8) + 16) ++#define MAKE_YUV_601_U(r, g, b) \ ++ (((-38 * (r) - 74 * (g) + 112 * (b) + 128) >> 8) + 128) ++#define MAKE_YUV_601_V(r, g, b) \ ++ (((112 * (r) - 94 * (g) - 18 * (b) + 128) >> 8) + 128) ++ ++#define MAKE_YUV_601(r, g, b) \ ++ { .y = MAKE_YUV_601_Y(r, g, b), \ ++ .u = MAKE_YUV_601_U(r, g, b), \ ++ .v = MAKE_YUV_601_V(r, g, b) } ++ ++#define MAKE_RGBA(rgb, r, g, b, a) \ ++ ((((r) >> (8 - (rgb)->red.length)) << (rgb)->red.offset) | \ ++ (((g) >> (8 - (rgb)->green.length)) << (rgb)->green.offset) | \ ++ (((b) >> (8 - (rgb)->blue.length)) << (rgb)->blue.offset) | \ ++ (((a) >> (8 - (rgb)->alpha.length)) << (rgb)->alpha.offset)) ++ ++#define MAKE_RGB24(rgb, r, g, b) \ ++ { .value = MAKE_RGBA(rgb, r, g, b, 0) } ++ ++static void fill_smpte_yuv_planar(const UtilYuvInfo_t *yuv, ++ unsigned char *y_mem, unsigned char *u_mem, ++ unsigned char *v_mem, unsigned int width, ++ unsigned int height, unsigned int stride) ++{ ++ const struct color_yuv colors_top[] = ++ { ++ MAKE_YUV_601(191, 192, 192), /* grey */ ++ MAKE_YUV_601(192, 192, 0), /* yellow */ ++ MAKE_YUV_601(0, 192, 192), /* cyan */ ++ MAKE_YUV_601(0, 192, 0), /* green */ ++ MAKE_YUV_601(192, 0, 192), /* magenta */ ++ MAKE_YUV_601(192, 0, 0), /* red */ ++ MAKE_YUV_601(0, 0, 192), /* blue */ ++ }; ++ ++ const struct color_yuv colors_middle[] = ++ { ++ MAKE_YUV_601(0, 0, 192), /* blue */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(192, 0, 192), /* magenta */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(0, 192, 192), /* cyan */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(192, 192, 192), /* grey */ ++ }; ++ ++ const struct color_yuv colors_bottom[] = ++ { ++ MAKE_YUV_601(0, 33, 76), /* in-phase */ ++ MAKE_YUV_601(255, 255, 255), /* super white */ ++ MAKE_YUV_601(50, 0, 106), /* quadrature */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(9, 9, 9), /* 3.5% */ ++ MAKE_YUV_601(19, 19, 19), /* 7.5% */ ++ MAKE_YUV_601(29, 29, 29), /* 11.5% */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ }; ++ ++ unsigned int cs = yuv->chroma_stride; ++ unsigned int xsub = yuv->xsub; ++ unsigned int ysub = yuv->ysub; ++ unsigned int x; ++ unsigned int y; ++ ++ /* Luma */ ++ for(y = 0; y < height * 6 / 9; ++y) ++ { ++ for(x = 0; x < width; ++x) ++ y_mem[x] = colors_top[x * 7 / width].y; ++ y_mem += stride; ++ } ++ ++ for(; y < height * 7 / 9; ++y) ++ { ++ for(x = 0; x < width; ++x) ++ y_mem[x] = colors_middle[x * 7 / width].y; ++ y_mem += stride; ++ } ++ ++ for(; y < height; ++y) ++ { ++ for(x = 0; x < width * 5 / 7; ++x) ++ y_mem[x] = colors_bottom[x * 4 / (width * 5 / 7)].y; ++ for(; x < width * 6 / 7; ++x) ++ y_mem[x] = colors_bottom[(x - width * 5 / 7) * 3 ++ / (width / 7) + 4].y; ++ for(; x < width; ++x) ++ y_mem[x] = colors_bottom[7].y; ++ y_mem += stride; ++ } ++ ++ /* Chroma */ ++ for(y = 0; y < height / ysub * 6 / 9; ++y) ++ { ++ for(x = 0; x < width; x += xsub) ++ { ++ u_mem[x * cs / xsub] = colors_top[x * 7 / width].u; ++ v_mem[x * cs / xsub] = colors_top[x * 7 / width].v; ++ } ++ u_mem += stride * cs / xsub; ++ v_mem += stride * cs / xsub; ++ } ++ ++ for(; y < height / ysub * 7 / 9; ++y) ++ { ++ for(x = 0; x < width; x += xsub) ++ { ++ u_mem[x * cs / xsub] = colors_middle[x * 7 / width].u; ++ v_mem[x * cs / xsub] = colors_middle[x * 7 / width].v; ++ } ++ u_mem += stride * cs / xsub; ++ v_mem += stride * cs / xsub; ++ } ++ ++ for(; y < height / ysub; ++y) ++ { ++ for(x = 0; x < width * 5 / 7; x += xsub) ++ { ++ u_mem[x * cs / xsub] = ++ colors_bottom[x * 4 / (width * 5 / 7)].u; ++ v_mem[x * cs / xsub] = ++ colors_bottom[x * 4 / (width * 5 / 7)].v; ++ } ++ for(; x < width * 6 / 7; x += xsub) ++ { ++ u_mem[x * cs / xsub] = colors_bottom[(x - width * 5 / 7) * ++ 3 / (width / 7) + 4].u; ++ v_mem[x * cs / xsub] = colors_bottom[(x - width * 5 / 7) * ++ 3 / (width / 7) + 4].v; ++ } ++ for(; x < width; x += xsub) ++ { ++ u_mem[x * cs / xsub] = colors_bottom[7].u; ++ v_mem[x * cs / xsub] = colors_bottom[7].v; ++ } ++ u_mem += stride * cs / xsub; ++ v_mem += stride * cs / xsub; ++ } ++} ++ ++static void fill_smpte_yuv_packed(const UtilYuvInfo_t *yuv, void *mem, ++ unsigned int width, unsigned int height, ++ unsigned int stride) ++{ ++ const struct color_yuv colors_top[] = ++ { ++ MAKE_YUV_601(191, 192, 192), /* grey */ ++ MAKE_YUV_601(192, 192, 0), /* yellow */ ++ MAKE_YUV_601(0, 192, 192), /* cyan */ ++ MAKE_YUV_601(0, 192, 0), /* green */ ++ MAKE_YUV_601(192, 0, 192), /* magenta */ ++ MAKE_YUV_601(192, 0, 0), /* red */ ++ MAKE_YUV_601(0, 0, 192), /* blue */ ++ }; ++ ++ const struct color_yuv colors_middle[] = ++ { ++ MAKE_YUV_601(0, 0, 192), /* blue */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(192, 0, 192), /* magenta */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(0, 192, 192), /* cyan */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(192, 192, 192), /* grey */ ++ }; ++ ++ const struct color_yuv colors_bottom[] = ++ { ++ MAKE_YUV_601(0, 33, 76), /* in-phase */ ++ MAKE_YUV_601(255, 255, 255), /* super white */ ++ MAKE_YUV_601(50, 0, 106), /* quadrature */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ MAKE_YUV_601(9, 9, 9), /* 3.5% */ ++ MAKE_YUV_601(19, 19, 19), /* 7.5% */ ++ MAKE_YUV_601(29, 29, 29), /* 11.5% */ ++ MAKE_YUV_601(19, 19, 19), /* black */ ++ }; ++ ++ unsigned char *y_mem = (yuv->order & YUV_YC) ? mem : mem + 1; ++ unsigned char *c_mem = (yuv->order & YUV_CY) ? mem : mem + 1; ++ unsigned int u = (yuv->order & YUV_YCrCb) ? 2 : 0; ++ unsigned int v = (yuv->order & YUV_YCbCr) ? 2 : 0; ++ unsigned int x; ++ unsigned int y; ++ ++ /* Luma */ ++ for(y = 0; y < height * 6 / 9; ++y) ++ { ++ for(x = 0; x < width; ++x) ++ y_mem[2 * x] = colors_top[x * 7 / width].y; ++ y_mem += stride; ++ } ++ ++ for(; y < height * 7 / 9; ++y) ++ { ++ for(x = 0; x < width; ++x) ++ y_mem[2 * x] = colors_middle[x * 7 / width].y; ++ y_mem += stride; ++ } ++ ++ for(; y < height; ++y) ++ { ++ for(x = 0; x < width * 5 / 7; ++x) ++ y_mem[2 * x] = colors_bottom[x * 4 / (width * 5 / 7)].y; ++ for(; x < width * 6 / 7; ++x) ++ y_mem[2 * x] = colors_bottom[(x - width * 5 / 7) * 3 ++ / (width / 7) + 4].y; ++ for(; x < width; ++x) ++ y_mem[2 * x] = colors_bottom[7].y; ++ y_mem += stride; ++ } ++ ++ /* Chroma */ ++ for(y = 0; y < height * 6 / 9; ++y) ++ { ++ for(x = 0; x < width; x += 2) ++ { ++ c_mem[2 * x + u] = colors_top[x * 7 / width].u; ++ c_mem[2 * x + v] = colors_top[x * 7 / width].v; ++ } ++ c_mem += stride; ++ } ++ ++ for(; y < height * 7 / 9; ++y) ++ { ++ for(x = 0; x < width; x += 2) ++ { ++ c_mem[2 * x + u] = colors_middle[x * 7 / width].u; ++ c_mem[2 * x + v] = colors_middle[x * 7 / width].v; ++ } ++ c_mem += stride; ++ } ++ ++ for(; y < height; ++y) ++ { ++ for(x = 0; x < width * 5 / 7; x += 2) ++ { ++ c_mem[2 * x + u] = colors_bottom[x * 4 / (width * 5 / 7)].u; ++ c_mem[2 * x + v] = colors_bottom[x * 4 / (width * 5 / 7)].v; ++ } ++ for(; x < width * 6 / 7; x += 2) ++ { ++ c_mem[2 * x + u] = colors_bottom[(x - width * 5 / 7) * ++ 3 / (width / 7) + 4].u; ++ c_mem[2 * x + v] = colors_bottom[(x - width * 5 / 7) * ++ 3 / (width / 7) + 4].v; ++ } ++ for(; x < width; x += 2) ++ { ++ c_mem[2 * x + u] = colors_bottom[7].u; ++ c_mem[2 * x + v] = colors_bottom[7].v; ++ } ++ c_mem += stride; ++ } ++} ++ ++ ++static void fill_smpte(const UtilFormatInfo_t *info, void *planes[3], ++ unsigned int width, unsigned int height, ++ unsigned int stride) ++{ ++ unsigned char *u, *v; ++ ++ switch(info->format) ++ { ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ return fill_smpte_yuv_packed(&info->yuv, planes[0], width, ++ height, stride); ++ ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ u = info->yuv.order & YUV_YCbCr ? planes[1] : planes[1] + 1; ++ v = info->yuv.order & YUV_YCrCb ? planes[1] : planes[1] + 1; ++ return fill_smpte_yuv_planar(&info->yuv, planes[0], u, v, ++ width, height, stride); ++ } ++} ++ ++static void fill_tiles_yuv_planar(const UtilFormatInfo_t *info, ++ unsigned char *y_mem, unsigned char *u_mem, ++ unsigned char *v_mem, unsigned int width, ++ unsigned int height, unsigned int stride) ++{ ++ const UtilYuvInfo_t *yuv = &info->yuv; ++ unsigned int cs = yuv->chroma_stride; ++ unsigned int xsub = yuv->xsub; ++ unsigned int ysub = yuv->ysub; ++ unsigned int x; ++ unsigned int y; ++ ++ for(y = 0; y < height; ++y) ++ { ++ for(x = 0; x < width; ++x) ++ { ++ div_t d = div(x + y, width); ++ uint32_t rgb32 = 0x00130502 * (d.quot >> 6) ++ + 0x000a1120 * (d.rem >> 6); ++ struct color_yuv color = ++ MAKE_YUV_601((rgb32 >> 16) & 0xff, ++ (rgb32 >> 8) & 0xff, rgb32 & 0xff); ++ ++ y_mem[x] = color.y; ++ u_mem[x / xsub * cs] = color.u; ++ v_mem[x / xsub * cs] = color.v; ++ } ++ ++ y_mem += stride; ++ if((y + 1) % ysub == 0) ++ { ++ u_mem += stride * cs / xsub; ++ v_mem += stride * cs / xsub; ++ } ++ } ++} ++ ++static void fill_tiles_yuv_packed(const UtilFormatInfo_t *info, ++ void *mem, unsigned int width, ++ unsigned int height, unsigned int stride) ++{ ++ const UtilYuvInfo_t *yuv = &info->yuv; ++ unsigned char *y_mem = (yuv->order & YUV_YC) ? mem : mem + 1; ++ unsigned char *c_mem = (yuv->order & YUV_CY) ? mem : mem + 1; ++ unsigned int u = (yuv->order & YUV_YCrCb) ? 2 : 0; ++ unsigned int v = (yuv->order & YUV_YCbCr) ? 2 : 0; ++ unsigned int x; ++ unsigned int y; ++ ++ for(y = 0; y < height; ++y) ++ { ++ for(x = 0; x < width; x += 2) ++ { ++ div_t d = div(x + y, width); ++ uint32_t rgb32 = 0x00130502 * (d.quot >> 6) ++ + 0x000a1120 * (d.rem >> 6); ++ struct color_yuv color = ++ MAKE_YUV_601((rgb32 >> 16) & 0xff, ++ (rgb32 >> 8) & 0xff, rgb32 & 0xff); ++ ++ y_mem[2 * x] = color.y; ++ c_mem[2 * x + u] = color.u; ++ y_mem[2 * x + 2] = color.y; ++ c_mem[2 * x + v] = color.v; ++ } ++ ++ y_mem += stride; ++ c_mem += stride; ++ } ++} ++ ++ ++static void fill_tiles(const UtilFormatInfo_t *info, void *planes[3], ++ unsigned int width, unsigned int height, ++ unsigned int stride) ++{ ++ unsigned char *u, *v; ++ ++ switch(info->format) ++ { ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ return fill_tiles_yuv_packed(info, planes[0], ++ width, height, stride); ++ ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ u = info->yuv.order & YUV_YCbCr ? planes[1] : planes[1] + 1; ++ v = info->yuv.order & YUV_YCrCb ? planes[1] : planes[1] + 1; ++ return fill_tiles_yuv_planar(info, planes[0], u, v, ++ width, height, stride); ++ } ++} ++ ++static void fill_plain(const UtilFormatInfo_t *info, void *planes[3], ++ unsigned int width, unsigned int height, ++ unsigned int stride) ++{ ++ memset(planes[0], 0x77, stride * height); ++} ++ ++/* ++ * UtilFillPattern - Fill a buffer with a test pattern ++ * @format: Pixel format ++ * @pattern: Test pattern ++ * @planes: Array of buffers ++ * @width: Width in pixels ++ * @height: Height in pixels ++ * @stride: Line stride (pitch) in bytes ++ * ++ * Fill the buffers with the test pattern specified by the pattern parameter. ++ * Supported formats vary depending on the selected pattern. ++ */ ++void UtilFillPattern(uint32_t format, UtilFillPattern_e pattern, ++ void *planes[3], unsigned int width, ++ unsigned int height, unsigned int stride) ++{ ++ const UtilFormatInfo_t *info; ++ ++ info = util_format_info_find(format); ++ if(info == NULL) ++ return; ++ ++ switch(pattern) ++ { ++ case UTIL_PATTERN_TILES: ++ return fill_tiles(info, planes, width, height, stride); ++ ++ case UTIL_PATTERN_SMPTE: ++ return fill_smpte(info, planes, width, height, stride); ++ ++ case UTIL_PATTERN_PLAIN: ++ return fill_plain(info, planes, width, height, stride); ++ ++ default: ++ printf("Error: unsupported test pattern %u.\n", pattern); ++ break; ++ } ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/common/util_pattern.h b/drivers/mstar/jpe2/drv/test/common/util_pattern.h +new file mode 100644 +index 00000000..d4c7b419 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/common/util_pattern.h +@@ -0,0 +1,63 @@ ++#ifndef __UTIL_PATTERN_H__ ++#define __UTIL_PATTERN_H__ ++ ++#ifndef uint32_t ++#define uint32_t unsigned int ++#endif ++ ++#define FOURCC_CODE(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ ++ ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) ++ ++#define DRM_FORMAT_YUYV FOURCC_CODE('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */ ++#define DRM_FORMAT_YVYU FOURCC_CODE('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */ ++#define DRM_FORMAT_NV12 FOURCC_CODE('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */ ++#define DRM_FORMAT_NV21 FOURCC_CODE('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */ ++ ++ ++typedef struct UtilColorComponent ++{ ++ unsigned int length; ++ unsigned int offset; ++} UtilColorComponent_t; ++ ++ ++typedef enum UtilYuvOrder ++{ ++ YUV_YCbCr = 1, ++ YUV_YCrCb = 2, ++ YUV_YC = 4, ++ YUV_CY = 8, ++} UtilYuvOrder_e; ++ ++ ++typedef struct UtilYuvInfo ++{ ++ UtilYuvOrder_e order; ++ unsigned int xsub; ++ unsigned int ysub; ++ unsigned int chroma_stride; ++} UtilYuvInfo_t; ++ ++ ++typedef struct UtilFormatInfo ++{ ++ uint32_t format; ++ const char *name; ++ const UtilYuvInfo_t yuv; ++} UtilFormatInfo_t; ++ ++typedef enum UtilFillPattern ++{ ++ UTIL_PATTERN_TILES, ++ UTIL_PATTERN_PLAIN, ++ UTIL_PATTERN_SMPTE, ++} UtilFillPattern_e; ++ ++ ++void UtilFillPattern(uint32_t format, ++ UtilFillPattern_e pattern, ++ void *planes[3], ++ unsigned int width, ++ unsigned int height, ++ unsigned int stride); ++#endif /* UTIL_PATTERN_H */ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/linux/cam_os_util_list.h b/drivers/mstar/jpe2/drv/test/linux/cam_os_util_list.h +new file mode 100644 +index 00000000..6110f320 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/linux/cam_os_util_list.h +@@ -0,0 +1,81 @@ ++#ifndef __CAM_OS_UTIL_LIST_H__ ++#define __CAM_OS_UTIL_LIST_H__ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif /* __cplusplus */ ++ ++ ++ ++struct CamOsListHead_t ++{ ++ struct CamOsListHead_t *pNext, *pPrev; ++}; ++ ++#ifndef offsetof ++#ifdef __compiler_offsetof ++#define offsetof(TYPE,MEMBER) __compiler_offsetof(TYPE,MEMBER) ++#else ++#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER) ++#endif ++#endif ++ ++ ++#define CAM_OS_POISON_POINTER_DELTA 0 ++#define CAM_OS_LIST_POISON1 ((void *) 0x00100100 + CAM_OS_POISON_POINTER_DELTA) ++#define CAM_OS_LIST_POISON2 ((void *) 0x00200200 + CAM_OS_POISON_POINTER_DELTA) ++ ++ ++#define CAM_OS_CONTAINER_OF(ptr, type, member) ({ \ ++ const typeof( ((type *)0)->member ) *__mptr = (ptr); \ ++ (type *)( (char *)__mptr - offsetof(type,member) );}) ++ ++#define CAM_OS_LIST_HEAD_INIT(name) { &(name), &(name) } ++ ++#define CAM_OS_LIST_ENTRY(ptr, type, member) \ ++ CAM_OS_CONTAINER_OF(ptr, type, member) ++ ++#define CAM_OS_LIST_FOR_EACH_SAFE(pos, n, head) \ ++ for (pos = (head)->pNext, n = pos->pNext; pos != (head); \ ++ pos = n, n = pos->pNext) ++ ++static inline void _ListDel(struct CamOsListHead_t * pPrev, struct CamOsListHead_t * pNext) ++{ ++ pNext->pPrev = pPrev; ++ pPrev->pNext = pNext; ++} ++ ++static inline void CAM_OS_LIST_DEL(struct CamOsListHead_t *pEntry) ++{ ++ _ListDel(pEntry->pPrev, pEntry->pNext); ++ pEntry->pNext = CAM_OS_LIST_POISON1; ++ pEntry->pPrev = CAM_OS_LIST_POISON2; ++} ++ ++static inline void CAM_OS_INIT_LIST_HEAD(struct CamOsListHead_t *pList) ++{ ++ pList->pNext = pList; ++ pList->pPrev = pList; ++} ++ ++static inline void _ListAdd(struct CamOsListHead_t *new, ++ struct CamOsListHead_t *pPrev, ++ struct CamOsListHead_t *pNext) ++{ ++ pNext->pPrev = new; ++ new->pNext = pNext; ++ new->pPrev = pPrev; ++ pPrev->pNext = new; ++} ++ ++static inline void CAM_OS_LIST_ADD_TAIL(struct CamOsListHead_t *new, struct CamOsListHead_t *head) ++{ ++ _ListAdd(new, head->pPrev, head); ++} ++ ++ ++#ifdef __cplusplus ++} ++#endif /* __cplusplus */ ++ ++#endif //__CAM_OS_UTIL_LIST_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/linux/cam_os_wrapper.c b/drivers/mstar/jpe2/drv/test/linux/cam_os_wrapper.c +new file mode 100644 +index 00000000..06b0fd37 +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/linux/cam_os_wrapper.c +@@ -0,0 +1,1811 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.c ++/// @brief Cam OS Wrapper Source File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#define CAM_OS_LINUX_USER ++ ++#if defined(__KERNEL__) ++#define CAM_OS_LINUX_KERNEL ++#endif ++ ++#ifdef CAM_OS_RTK ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "sys_sys.h" ++#include "sys_MsWrapper_cus_os_flag.h" ++#include "sys_MsWrapper_cus_os_sem.h" ++#include "sys_MsWrapper_cus_os_util.h" ++#include "sys_sys_isw_uart.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef void *CamOsThreadEntry_t(void *); ++ ++typedef struct ++{ ++ MsTaskId_e eHandleObj; ++ CamOsThreadEntry_t *ptEntry; ++ void *pArg; ++ Ms_Flag_t tExitFlag; ++ void *pStack; ++} CamOsThreadHandleRtk_t, *pCamOsThreadHandleRtk; ++ ++typedef struct ++{ ++ Ms_Flag_t tFlag; /* or semaphore if supported */ ++ Ms_Mutex_t tMutex; ++ u32 nSemval; ++} CamOsTsemRtk_t, *pCamOsTsemRtk; ++ ++static Ms_Mutex_t _gtMemLock; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(Ms_Flag_t), "CamOsMutex_t size define not enough!"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemRtk_t), "CamOsTsem_t size define not enough!"); ++ ++#elif defined(CAM_OS_LINUX_USER) ++#define _GNU_SOURCE ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "mdrv_verchk.h" ++#include ++#include ++#include ++#include ++#include ++#include "time.h" ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++typedef struct ++{ ++ pthread_cond_t tCondition; ++ pthread_mutex_t tMutex; ++ u32 nSemval; ++} CamOsTsemLU_t, *pCamOsTsemLU; ++ ++// TODO remove extern pthread_setname_np and pthread_getname_np ++extern int pthread_setname_np(pthread_t tTargetThread, const char *szTargetName); ++extern int pthread_getname_np(pthread_t tThread, char *szName, size_t nLen); ++ ++static pthread_mutex_t _gtMemLock = PTHREAD_MUTEX_INITIALIZER; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(pthread_mutex_t), "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLU_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "cam_os_wrapper.h" ++#include "cam_os_util_list.h" ++ ++#define CAM_OS_THREAD_STACKSIZE_DEFAULT 8192 ++ ++typedef struct ++{ ++ struct semaphore tSem; ++ struct mutex tMutex; ++ u32 nSemval; ++} CamOsTsemLK_t, *pCamOsTsemLK; ++ ++typedef s32 CamOsThreadEntry_t(void *); ++ ++struct mutex _gtMemLock; ++ ++_Static_assert(sizeof(CamOsMutex_t) >= sizeof(struct mutex), "CamOsMutex_t size define not enough! %d"); ++_Static_assert(sizeof(CamOsTsem_t) >= sizeof(CamOsTsemLK_t), "CamOsTsem_t size define not enough!"); ++_Static_assert(sizeof(CamOsTimespec_t) == sizeof(struct timespec), "CamOsTimespec_t size define error!"); ++ ++#endif ++ ++typedef struct MemoryList_t ++{ ++ struct CamOsListHead_t tList; ++ void *pPtr; ++ void *pMemifoPtr; ++ char *szName; ++} MemoryList_t; ++ ++static MemoryList_t _gtMemList; ++ ++static s32 _gnDmemDbgListInited = 0; ++ ++void CamOsDebug(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ va_list tArgs; ++ char nLineStr[256]; ++ ++ va_start(tArgs, szFmt); ++ vsprintf(nLineStr, szFmt, tArgs); ++ send_msg(nLineStr); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_USER) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vfprintf(stderr, szFmt, tArgs); ++ va_end(tArgs); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ va_list tArgs; ++ ++ va_start(tArgs, szFmt); ++ vprintk(szFmt, tArgs); ++ va_end(tArgs); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static char* _CamOsAdvance(char* pBuf) { ++ ++ char* pNewBuf = pBuf; ++ ++ /* Skip over nonwhite space */ ++ while ((*pNewBuf != ' ') && (*pNewBuf != '\t') && ++ (*pNewBuf != '\n') && (*pNewBuf != '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ /* Skip white space */ ++ while ((*pNewBuf == ' ') || (*pNewBuf == '\t') || ++ (*pNewBuf == '\n') || (*pNewBuf == '\0')) ++ { ++ pNewBuf++; ++ } ++ ++ return pNewBuf; ++} ++ ++static s32 _CamOsVsscanf(char* szBuf, char* szFmt, va_list tArgp) ++{ ++ char* pFmt; ++ char* pBuf; ++ char* pnSval; ++ int* pnIval; ++ double* pdbDval; ++ float* pfFval; ++ s32 nCount = 0; ++ ++ pBuf = szBuf; ++ ++ for (pFmt = szFmt; *pFmt; pFmt++) { ++ if (*pFmt == '%') ++ switch (*++pFmt) { ++ case 'd': ++ pnIval = va_arg(tArgp, int *); ++ sscanf(pBuf, "%d", pnIval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ case 'f': ++ pfFval = va_arg(tArgp, float *); ++ sscanf(pBuf, "%f", pfFval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ case 'l': ++ pdbDval = va_arg(tArgp, double *); ++ sscanf(pBuf, "%lf", pdbDval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ case 's': ++ pnSval = va_arg(tArgp, char *); ++ sscanf(pBuf, "%s", pnSval); ++ pBuf = _CamOsAdvance(pBuf); ++ nCount++; ++ break; ++ default: ++ break; ++ } ++ } ++ return nCount; ++} ++ ++static s32 _CamOsVfscanf(const char *szFmt, va_list tArgp) ++{ ++ s32 nCount; ++ ++ nCount = _CamOsVsscanf(wait_for_command(), (char *)szFmt, tArgp); ++ return nCount; ++} ++#endif ++ ++s32 CamOsScanf(const char *szFmt, ...) ++{ ++#ifdef CAM_OS_RTK ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start (tArgp, szFmt); ++ nCount = _CamOsVfscanf (szFmt, tArgp); ++ va_end (tArgp); ++ UartSendTrace("\n"); ++ return nCount; ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nCount = 0; ++ va_list tArgp; ++ ++ va_start (tArgp, szFmt); ++ nCount = vfscanf (stdin, szFmt, tArgp); ++ va_end (tArgp); ++ return nCount; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++ return 0; ++} ++ ++s32 CamOsGetChar(void) ++{ ++#ifdef CAM_OS_RTK ++ s32 Ret; ++ Ret = get_char(); ++ UartSendTrace("\n"); ++ return Ret; ++#elif defined(CAM_OS_LINUX_USER) ++ return getchar(); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return 0; ++#endif ++ return 0; ++} ++ ++void CamOsMsSleep(u32 nMsec) ++{ ++#ifdef CAM_OS_RTK ++ MsSleep(RTK_MS_TO_TICK(nMsec)); ++#elif defined(CAM_OS_LINUX_USER) ++ usleep((useconds_t)nMsec * 1000); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ msleep(nMsec); ++#endif ++} ++ ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes) ++{ ++#ifdef CAM_OS_RTK ++ u32 nTmp = VM_RTK_TICK_TO_MS(MsGetOsTick()); ++ ptRes->nSec = nTmp / 1000; ++ ptRes->nNanoSec = (nTmp % 1000) * 1000000; ++#elif defined(CAM_OS_LINUX_USER) ++ clock_gettime(CLOCK_MONOTONIC, (struct timespec *)ptRes); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ getrawmonotonic((struct timespec *)ptRes); ++#endif ++} ++ ++#ifdef CAM_OS_RTK ++static void _CamOSThreadEntry(void *pEntryData) ++{ ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)pEntryData; ++ ++ ptTaskHandle->ptEntry(ptTaskHandle->pArg); ++ ++ MsFlagSetbits(&ptTaskHandle->tExitFlag, 0x00000001); ++} ++ ++static void _CamOsThreadEmptyParser(vm_msg_t *ptMessage) ++{ ++ ++} ++#endif ++ ++CamOsRet_e CamOsThreadCreate(CamOsThread *pThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = NULL; ++ MsTaskCreateArgs_t tTaskArgs = {0}; ++ u32 nPrio = 100; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority >= 0) && (ptAttrb->nPriority < 100)) ++ { ++ nPrio = ptAttrb->nPriority * 2; ++ } ++ nStkSz = (ptAttrb->nStackSize)? ptAttrb->nStackSize : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ } ++ ++ *pThread = (void*) - 1; ++ do ++ { ++ if(!(ptTaskHandle = MsCallocateMem(sizeof(CamOsThreadHandleRtk_t)))) ++ { ++ CamOsDebug("%s : Allocate ptHandle fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ ptTaskHandle->ptEntry = pfnStartRoutine; ++ ptTaskHandle->pArg = pArg; ++ if(!(ptTaskHandle->pStack = MsAllocateMem((nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT))) ++ { ++ CamOsDebug("%s : Allocate stack fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_ALLOCMEM_FAIL; ++ break; ++ } ++ ++ memset(&ptTaskHandle->tExitFlag, 0, sizeof(Ms_Flag_t)); ++ MsFlagInit(&ptTaskHandle->tExitFlag); ++ //VEN_TEST_CHECK_RESULT((pTaskHandle->exit_flag.FlagId >> 0) && (pTaskHandle->exit_flag.FlagState == RTK_FLAG_INITIALIZED)); ++ ++ tTaskArgs.Priority = (nPrio >= 0 && nPrio <= 200) ? nPrio : 100; ++ tTaskArgs.StackSize = (nStkSz) ? nStkSz : CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ tTaskArgs.pStackTop = (u32*)ptTaskHandle->pStack; ++ tTaskArgs.AppliInit = &_CamOSThreadEntry; ++ tTaskArgs.AppliParser = _CamOsThreadEmptyParser; ++ tTaskArgs.pInitArgs = ptTaskHandle; ++ tTaskArgs.TaskId = &ptTaskHandle->eHandleObj; ++ tTaskArgs.ImmediatelyStart = TRUE; ++ tTaskArgs.TimeSliceMax = 10; ++ tTaskArgs.TimeSliceLeft = 10; ++ strcpy(tTaskArgs.TaskName, "CamOS"); ++ ++ if(MS_OK != MsCreateTask(&tTaskArgs)) ++ { ++ CamOsDebug("%s : Create task fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *pThread = ptTaskHandle; ++ } ++ while(0); ++ ++ if(!*pThread) ++ { ++ if(ptTaskHandle) ++ { ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsReleaseMemory(ptTaskHandle); ++ } ++ } ++ ++ //CamOsDebug("%s get taskid: %d priority: %d\n\r", __FUNCTION__, (u32)pTaskHandle->eHandleObj, TaskArgs.Priority); ++#elif defined(CAM_OS_LINUX_USER) ++ struct sched_param tSched; ++ pthread_t tThreadHandle = NULL; ++ pthread_attr_t tAttr; ++ if(ptAttrb != NULL) ++ { ++ pthread_attr_init(&tAttr); ++ pthread_attr_getschedparam(&tAttr, &tSched); ++ pthread_attr_setinheritsched(&tAttr, PTHREAD_EXPLICIT_SCHED); ++ pthread_attr_setschedpolicy(&tAttr, SCHED_RR); ++ ++ if((ptAttrb->nPriority >= 0) && (ptAttrb->nPriority < 100)) ++ { ++ tSched.sched_priority = ptAttrb->nPriority; ++ } ++ ++ pthread_attr_setschedparam(&tAttr, &tSched); ++ if(0 != ptAttrb->nStackSize) ++ { ++ pthread_attr_setstacksize(&tAttr, (size_t) ptAttrb->nStackSize); ++ eRet = CAM_OS_FAIL; ++ } ++ pthread_create(&tThreadHandle, &tAttr, pfnStartRoutine, pArg); ++ pthread_attr_destroy(&tAttr); ++ } ++ else ++ { ++ pthread_create(&tThreadHandle, NULL, pfnStartRoutine, pArg); ++ } ++ ++ *pThread = (CamOsThread *)tThreadHandle; ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle; ++ struct sched_param tSche = { .sched_priority = 0 }; ++ u32 nStkSz = CAM_OS_THREAD_STACKSIZE_DEFAULT; ++ ++ if(ptAttrb != NULL) ++ { ++ if((ptAttrb->nPriority >= 0) && (ptAttrb->nPriority < 100)) ++ { ++ tSche.sched_priority = ptAttrb->nPriority; ++ } ++ nStkSz = ptAttrb->nStackSize; ++ } ++ tpThreadHandle = kthread_run((CamOsThreadEntry_t *)pfnStartRoutine, pArg, "CAMOS"); ++ sched_setscheduler(tpThreadHandle, SCHED_RR, &tSche); ++ *pThread = (CamOsThread *)tpThreadHandle; ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadJoin(CamOsThread thread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsThreadHandleRtk_t *ptTaskHandle = (CamOsThreadHandleRtk_t *)thread; ++ if(ptTaskHandle) ++ { ++ MsFlagWait(&ptTaskHandle->tExitFlag, 0x00000001, RTK_FLAG_WAITMODE_AND | RTK_FLAG_WAITMODE_CLR); ++ MsFlagDestroy(&ptTaskHandle->tExitFlag); ++ MsDeleteTask(ptTaskHandle->eHandleObj); ++ ++ if(ptTaskHandle->pStack) ++ { ++ MsReleaseMemory(ptTaskHandle->pStack); ++ } ++ MsReleaseMemory(ptTaskHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_join(tThreadHandle, NULL); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadStop(CamOsThread thread) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct task_struct *tpThreadHandle = (struct task_struct *)thread; ++ if(tpThreadHandle) ++ { ++ if(0 != kthread_stop((struct task_struct *)thread)) ++ { ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadShouldStop(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(kthread_should_stop()) ++ { ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_FAIL; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadSetName(CamOsThread thread, const char *szName) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ // TODO RTK not support set task name dynamic. ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_setname_np(tThreadHandle, szName); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ ++ return eRet; ++} ++ ++CamOsRet_e CamOsThreadGetName(CamOsThread thread, const char *szName, u32 nLen) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_t tThreadHandle = (pthread_t)thread; ++ if(tThreadHandle) ++ { ++ pthread_getname_np(tThreadHandle, (char *)szName, nLen); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++u32 CamOsThreadGetID() ++{ ++#ifdef CAM_OS_RTK ++ return MsCurrTask(); ++#elif defined(CAM_OS_LINUX_USER) ++ return (u32)syscall(__NR_gettid); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return current->tgid; ++#endif ++ return 0; ++} ++ ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsInitMutex(ptHandle)) ++ { ++ CamOsDebug("%s : Init mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != pthread_mutex_init(ptHandle, NULL)) ++ { ++ fprintf(stderr, "%s : Init mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_init(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ // Do Nothing in RTK ++#elif defined(CAM_OS_LINUX_USER) ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ pthread_mutex_destroy(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsMutexLock(ptHandle)) ++ { ++ CamOsDebug("%s : Lock mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != (nErr = pthread_mutex_lock(ptHandle))) ++ { ++ fprintf(stderr, "%s : Lock mutex fail, err %d\n\r", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_lock(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ Ms_Mutex_t *ptHandle = (Ms_Mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(CUS_OS_OK != MsMutexUnlock(ptHandle)) ++ { ++ CamOsDebug("%s : Unlock mutex fail\n\r", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nErr = 0; ++ pthread_mutex_t *ptHandle = (pthread_mutex_t *)ptMutex; ++ if(ptHandle) ++ { ++ if(0 != (nErr = pthread_mutex_unlock(ptHandle))) ++ { ++ fprintf(stderr, "%s : Unlock mutex fail, err %d\n\r", __FUNCTION__, nErr); ++ eRet = CAM_OS_FAIL; ++ } ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ struct mutex *ptHandle = (struct mutex *)ptMutex; ++ if(ptHandle) ++ { ++ mutex_unlock(ptHandle); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagInit(&ptHandle->tFlag); ++ MsInitMutex(&ptHandle->tMutex); ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ if(0 != pthread_cond_init(&ptHandle->tCondition, NULL)) ++ { ++ return CAM_OS_FAIL; ++ } ++ if(0 != pthread_mutex_init(&ptHandle->tMutex, NULL)) ++ { ++ return CAM_OS_FAIL; ++ } ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ sema_init(&ptHandle->tSem, nVal); ++ mutex_init(&ptHandle->tMutex); ++ ptHandle->nSemval = nVal; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagDestroy(&ptHandle->tFlag); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_cond_destroy(&ptHandle->tCondition); ++ pthread_mutex_destroy(&ptHandle->tMutex); ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++void CamOsTsemUp(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ MsMutexUnlock(&ptHandle->tMutex); ++ MsFlagSetbits(&ptHandle->tFlag, 0x00000001); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval++; ++ mutex_unlock(&ptHandle->tMutex); ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemDown(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ MsMutexUnlock(&ptHandle->tMutex); ++ MsFlagWait(&ptHandle->tFlag, 0x00000001, MS_FLAG_WAITMODE_OR); ++ MsMutexLock(&ptHandle->tMutex); ++ } ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ MsMutexUnlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ } ++ ptHandle->nSemval--; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ down(&ptHandle->tSem); ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval--; ++ mutex_unlock(&ptHandle->tMutex); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ MsMutexUnlock(&ptHandle->tMutex); ++ nErr = MsFlagTimedWait(&ptHandle->tFlag, 1, (MS_FLAG_WAITMODE_OR), RTK_MS_TO_TICK(nMsec)); ++ /*time out*/ ++ MsMutexLock(&ptHandle->tMutex); ++ if(!nErr) ++ { ++ break; ++ } ++ } ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ MsMutexUnlock(&ptHandle->tMutex); ++ if(!nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ struct timeval tCurrTime; ++ u32 nMicDelay; ++ ++ if(ptHandle) ++ { ++ gettimeofday(&tCurrTime, NULL); ++ /** convert timeval to timespec and add delay in milliseconds for the timeout */ ++ nMicDelay = ((nMsec * 1000 + tCurrTime.tv_usec)); ++ tFinalTime.tv_sec = tCurrTime.tv_sec + (nMicDelay / 1000000); ++ tFinalTime.tv_nsec = (nMicDelay % 1000000) * 1000; ++ pthread_mutex_lock(&ptHandle->tMutex); ++ while(ptHandle->nSemval == 0) ++ { ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ if(nErr != 0) ++ { ++ ptHandle->nSemval--; ++ } ++ } ++ ptHandle->nSemval--; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ eRet = CAM_OS_OK; ++ else if(nErr == ETIMEDOUT) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec)); ++ mutex_lock(&ptHandle->tMutex); ++ if(ptHandle->nSemval > 0) ++ { ++ ptHandle->nSemval--; ++ } ++ mutex_unlock(&ptHandle->tMutex); ++ if(nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemSignal(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagSetbits(&ptHandle->tFlag, 0x00000001); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_signal(&ptHandle->tCondition); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ up(&ptHandle->tSem); ++ } ++#endif ++} ++ ++void CamOsTsemWait(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsFlagWait(&ptHandle->tFlag, 0x00000001, MS_FLAG_WAITMODE_OR); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ pthread_cond_wait(&ptHandle->tCondition, &ptHandle->tMutex); ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ down(&ptHandle->tSem); ++ } ++#endif ++} ++ ++CamOsRet_e CamOsTsemTimedWait(CamOsTsem_t *ptTsem, u32 nMsec) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = MsFlagTimedWait(&ptHandle->tFlag, 1, (MS_FLAG_WAITMODE_OR), RTK_MS_TO_TICK(nMsec)); ++ if(!nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ s32 nErr = 0; ++ struct timespec tFinalTime; ++ struct timeval tCurrTime; ++ u32 nMicDelay; ++ ++ if(ptHandle) ++ { ++ gettimeofday(&tCurrTime, NULL); ++ /** convert timeval to timespec and add delay in milliseconds for the timeout */ ++ nMicDelay = ((nMsec * 1000 + tCurrTime.tv_usec)); ++ tFinalTime.tv_sec = tCurrTime.tv_sec + (nMicDelay / 1000000); ++ tFinalTime.tv_nsec = (nMicDelay % 1000000) * 1000; ++ ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ++ nErr = pthread_cond_timedwait(&ptHandle->tCondition, &ptHandle->tMutex, ++ &tFinalTime); ++ ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ ++ if(!nErr) ++ eRet = CAM_OS_OK; ++ else if(nErr == ETIMEDOUT) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_FAIL; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ s32 nErr = 0; ++ if(ptHandle) ++ { ++ nErr = down_timeout(&ptHandle->tSem, msecs_to_jiffies(nMsec)); ++ if(nErr) ++ eRet = CAM_OS_TIMEOUT; ++ else ++ eRet = CAM_OS_OK; ++ } ++ else ++ { ++ eRet = CAM_OS_PARAM_ERR; ++ } ++#endif ++ return eRet; ++} ++ ++u32 CamOsTsemGetValue(CamOsTsem_t *ptTsem) ++{ ++ s32 eRet = 0; ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ eRet = ptHandle->nSemval; ++ } ++#endif ++ return eRet; ++} ++ ++void CamOsTsemReset(CamOsTsem_t *ptTsem) ++{ ++#ifdef CAM_OS_RTK ++ CamOsTsemRtk_t *ptHandle = (CamOsTsemRtk_t *)ptTsem; ++ if(ptHandle) ++ { ++ MsMutexLock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ MsMutexUnlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ CamOsTsemLU_t *ptHandle = (CamOsTsemLU_t *)ptTsem; ++ if(ptHandle) ++ { ++ pthread_mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ pthread_mutex_unlock(&ptHandle->tMutex); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ CamOsTsemLK_t *ptHandle = (CamOsTsemLK_t *)ptTsem; ++ if(ptHandle) ++ { ++ sema_init(&ptHandle->tSem, 0); ++ mutex_lock(&ptHandle->tMutex); ++ ptHandle->nSemval = 0; ++ mutex_unlock(&ptHandle->tMutex); ++ } ++#endif ++} ++ ++void* CamOsMemAlloc(u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsAllocateMem(nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return malloc(nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return kzalloc(nSize, GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemCalloc(u32 nNum, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsCallocateMem(nNum * nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return calloc(nNum, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ return kzalloc(nSize, GFP_KERNEL); ++#endif ++} ++ ++void* CamOsMemRealloc(void* pPtr, u32 nSize) ++{ ++#ifdef CAM_OS_RTK ++ return MsMemoryReAllocate(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_USER) ++ return realloc(pPtr, nSize); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ void *pAddr = kzalloc(nSize, GFP_KERNEL); ++ if(pPtr && pAddr) ++ { ++ memcpy(pAddr, pPtr, nSize); ++ kfree(pPtr); ++ } ++ return pAddr; ++#endif ++} ++ ++void CamOsMemRelease(void* pPtr) ++{ ++#ifdef CAM_OS_RTK ++ if(pPtr) ++ { ++ MsReleaseMemory(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(pPtr) ++ { ++ free(pPtr); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(pPtr) ++ { ++ kfree(pPtr); ++ } ++#endif ++} ++ ++static s32 _CheckDmemInfoListInited(void) ++{ ++#ifdef CAM_OS_RTK ++ if(!_gnDmemDbgListInited) ++ { ++ if(CUS_OS_OK != MsInitMutex(&_gtMemLock)) ++ { ++ CamOsDebug("%s : Init mutex fail\n\r", __FUNCTION__); ++ } ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#elif defined(CAM_OS_LINUX_USER) ++ if(!_gnDmemDbgListInited) ++ { ++ pthread_mutex_init(&_gtMemLock, NULL); ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ if(!_gnDmemDbgListInited) ++ { ++ mutex_init(&_gtMemLock); ++ ++ memset(&_gtMemList, 0, sizeof(MemoryList_t)); ++ CAM_OS_INIT_LIST_HEAD(&_gtMemList.tList); ++ ++ _gnDmemDbgListInited = 1; ++ } ++#endif ++ ++ return 0; ++} ++ ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppUserPtr, ++ u32 *pMiuAddr, ++ u64 *lpPhysAddr) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ u8 nAllocSucc = TRUE; ++ *ppUserPtr = MsAllocateNonCacheMemExt(nSize, 12); ++ nAllocSucc &= MsIsHeapMemory(*ppUserPtr); ++ ++ if((u32)*ppUserPtr & ((1 << 6) - 1)) ++ { ++ nAllocSucc &= FALSE; ++ MsReleaseMemory(*ppUserPtr); ++ } ++ ++ if(nAllocSucc == TRUE) ++ { ++ *lpPhysAddr = (u32)MsVA2PA(*ppUserPtr); ++ *pMiuAddr = (u32) * lpPhysAddr - (u32)&Image__RAM__Base; ++ } ++ else ++ { ++ *ppUserPtr = 0; ++ *lpPhysAddr = (u64)0; ++ *pMiuAddr = 0; ++ eRet = CAM_OS_FAIL; ++ } ++ ++ /*CamOsDebug("%s 0x%08X 0x%08X 0x%08X\r\n", ++ __FUNCTION__, ++ (u32)*ppUserPtr, ++ (u32)*phys_addr, ++ (u32)*miu_addr);*/ ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ MemoryList_t* ptNewEntry = (MemoryList_t*) MsAllocateMem(sizeof(MemoryList_t)); ++ ptNewEntry->pPtr = *ppUserPtr; ++ ptNewEntry->pMemifoPtr = NULL; ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysFd = -1; ++ s32 nMemFd = -1; ++ MSYS_DMEM_INFO * ptMsysMem = NULL; ++ unsigned char* pMmapPtr = NULL; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ fprintf(stderr, "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ break; ++ } ++ ++ if(0 > (nMsysFd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(0 > (nMemFd = open("/dev/mem", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/mem failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ ptMsysMem = (MSYS_DMEM_INFO *) malloc(sizeof(MSYS_DMEM_INFO)); ++ MSYS_ADDR_TRANSLATION_INFO tAddrInfo; ++ FILL_VERCHK_TYPE(tAddrInfo, tAddrInfo.VerChk_Version, tAddrInfo.VerChk_Size, ++ IOCTL_MSYS_VERSION); ++ FILL_VERCHK_TYPE(*ptMsysMem, ptMsysMem->VerChk_Version, ++ ptMsysMem->VerChk_Size, IOCTL_MSYS_VERSION); ++ ++ ptMsysMem->length = nSize; ++ snprintf(ptMsysMem->name, sizeof(ptMsysMem->name), "%s", szName); ++ ++ if(ioctl(nMsysFd, IOCTL_MSYS_REQUEST_DMEM, ptMsysMem)) ++ { ++ ptMsysMem->length = 0; ++ fprintf(stderr, "%s [%s][%d]Request Direct Memory Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ tAddrInfo.addr = ptMsysMem->phys; ++ *lpPhysAddr = ptMsysMem->phys; ++ if(ioctl(nMsysFd, IOCTL_MSYS_PHYS_TO_MIU, &tAddrInfo)) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s [%s][%d]IOCTL_MSYS_PHYS_TO_MIU Failed!!\n", __FUNCTION__, szName, (u32)nSize); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ *pMiuAddr = (u32)tAddrInfo.addr; ++ pMmapPtr = mmap(0, ptMsysMem->length, PROT_READ | PROT_WRITE, MAP_SHARED, ++ nMemFd, ptMsysMem->phys); ++ if(pMmapPtr == (void *) - 1) ++ { ++ ioctl(nMsysFd, IOCTL_MSYS_RELEASE_DMEM, ptMsysMem); ++ fprintf(stderr, "%s failed!! physAddr<0x%x> size<0x%x> errno<%d, %s> \r\n", ++ __FUNCTION__, ++ (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length, errno, strerror(errno)); ++ free(ptMsysMem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ *ppUserPtr = pMmapPtr; ++ ++ fprintf(stderr, "%s <%s> physAddr<0x%x> size<%d> \r\n", ++ __FUNCTION__, ++ szName, (u32)ptMsysMem->phys, ++ (u32)ptMsysMem->length); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ MemoryList_t* tpNewEntry = (MemoryList_t*) malloc(sizeof(MemoryList_t)); ++ tpNewEntry->pPtr = pMmapPtr; ++ tpNewEntry->pMemifoPtr = (void *) ptMsysMem; ++ tpNewEntry->szName = strdup(szName); ++ CAM_OS_LIST_ADD_TAIL(&(tpNewEntry->tList), &_gtMemList.tList); ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysFd >= 0) ++ { ++ close(nMsysFd); ++ } ++ if(nMemFd >= 0) ++ { ++ close(nMemFd); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *ptDmem = NULL; ++ MemoryList_t* ptNewEntry; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++ ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ ++ do ++ { ++ //Check request name to avoid allocate same dmem address. ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr && ptTmp->szName && 0 == strcmp(szName, ptTmp->szName)) ++ { ++ printk(KERN_WARNING "%s request same dmem name: %s\n", __FUNCTION__, szName); ++ eRet = CAM_OS_PARAM_ERR; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(eRet == CAM_OS_PARAM_ERR) ++ { ++ *ppUserPtr = 0; ++ *pMiuAddr = 0; ++ *lpPhysAddr = 0; ++ break; ++ } ++ ++ if(0 == (ptDmem = (MSYS_DMEM_INFO *)kzalloc(sizeof(MSYS_DMEM_INFO), GFP_KERNEL))) ++ { ++ printk(KERN_WARNING "%s kzalloc MSYS_DMEM_INFO fail\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ snprintf(ptDmem->name, 15, szName); ++ ptDmem->length = nSize; ++ ++ if(0 != msys_request_dmem(ptDmem)) ++ { ++ printk(KERN_WARNING "%s msys_request_dmem fail\n", __FUNCTION__); ++ kfree(ptDmem); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ *ppUserPtr = (void *)(u32)ptDmem->phys; ++ *pMiuAddr = Chip_Phys_to_MIU(ptDmem->phys); ++ *lpPhysAddr = ptDmem->phys; ++ ++ printk(KERN_INFO "%s <%s> physAddr<0x%08X> size<%d> \r\n", ++ __FUNCTION__, ++ szName, (u32)ptDmem->phys, ++ (u32)ptDmem->length); ++ ++ mutex_lock(&_gtMemLock); ++ ptNewEntry = (MemoryList_t*) kzalloc(sizeof(MemoryList_t), GFP_KERNEL); ++ ptNewEntry->pPtr = (void *)(u32)ptDmem->phys; ++ ptNewEntry->pMemifoPtr = (void *) ptDmem; ++ ptNewEntry->szName = (char *)kzalloc(strlen(szName), GFP_KERNEL); ++ strcpy(ptNewEntry->szName, szName); ++ CAM_OS_LIST_ADD_TAIL(&(ptNewEntry->tList), &_gtMemList.tList); ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemRelease(void* pUserPtr, u32 nSize) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++#ifdef CAM_OS_RTK ++ if(pUserPtr) ++ { ++ MsReleaseMemory(pUserPtr); ++ CamOsDebug("%s do release\n\r", __FUNCTION__); ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ free(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ free(ptTmp); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ s32 nMsysfd = -1; ++ s32 nErr = 0; ++ MSYS_DMEM_INFO *pMsysMem = NULL; ++ ++ do ++ { ++ if(0 > (nMsysfd = open("/dev/msys", O_RDWR | O_SYNC))) ++ { ++ fprintf(stderr, "%s open /dev/msys failed!!\n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ nErr = munmap(pUserPtr, nSize); ++ if(0 != nErr) ++ { ++ fprintf(stderr, "%s munmap failed!! <%p> size<%d> err<%d> errno<%d, %s> \r\n", ++ __FUNCTION__, ++ pUserPtr, (u32)nSize, nErr, errno, strerror(errno)); ++ } ++ ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ pMsysMem = (MSYS_DMEM_INFO *) ptTmp->pMemifoPtr; ++ break; ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ if(pMsysMem == NULL) ++ { ++ fprintf(stderr, "%s find Msys_DMEM_Info node failed!! <%p> \r\n", __FUNCTION__, pUserPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ if(ioctl(nMsysfd, IOCTL_MSYS_RELEASE_DMEM, pMsysMem)) ++ { ++ fprintf(stderr, "%s : IOCTL_MSYS_RELEASE_DMEM error physAddr<0x%x>\n", __FUNCTION__, (u32)pMsysMem->phys); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ if(pMsysMem) ++ { ++ free(pMsysMem); ++ pMsysMem = NULL; ++ } ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ free(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ free(ptTmp); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++ ++ if(nMsysfd >= 0) ++ { ++ close(nMsysfd); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ MSYS_DMEM_INFO *tpDmem = NULL; ++ ++ do ++ { ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ printk("search tmp->ptr: %08X %s\n", (u32)ptTmp->pPtr, ptTmp->szName); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ tpDmem = ptTmp->pMemifoPtr; ++ printk("search(2) pdmem->name: %s\n", tpDmem->name); ++ break; ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ if(tpDmem == NULL) ++ { ++ printk(KERN_WARNING "%s find Msys_DMEM_Info node failed!! <%p> \r\n", __FUNCTION__, pUserPtr); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ msys_release_dmem(tpDmem); ++ ++ if(tpDmem) ++ { ++ kfree(tpDmem); ++ tpDmem = NULL; ++ } ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr == pUserPtr) ++ { ++ if(ptTmp->szName) ++ kfree(ptTmp->szName); ++ CAM_OS_LIST_DEL(ptPos); ++ kfree(ptTmp); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++ } ++ while(0); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsDirectMemStat(void) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++ struct CamOsListHead_t *ptPos, *ptQ; ++ MemoryList_t* ptTmp; ++#ifdef CAM_OS_RTK ++ _CheckDmemInfoListInited(); ++ ++ MsMutexLock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ CamOsDebug("%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ MsMutexUnlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_USER) ++ _CheckDmemInfoListInited(); ++ ++ pthread_mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ fprintf(stderr, "%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ pthread_mutex_unlock(&_gtMemLock); ++#elif defined(CAM_OS_LINUX_KERNEL) ++ _CheckDmemInfoListInited(); ++ ++ mutex_lock(&_gtMemLock); ++ CAM_OS_LIST_FOR_EACH_SAFE(ptPos, ptQ, &_gtMemList.tList) ++ { ++ ptTmp = CAM_OS_LIST_ENTRY(ptPos, MemoryList_t, tList); ++ ++ if(ptTmp->pPtr) ++ { ++ printk(KERN_WARNING "%s memory allocated %p %s\n", __FUNCTION__, ptTmp->pPtr, ptTmp->szName); ++ } ++ } ++ mutex_unlock(&_gtMemLock); ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_set)(const char *szKey, const char *szValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error \n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set = dlsym(pLibHandle, "property_set"); ++ if(NULL == dlsym_property_set) ++ { ++ fprintf(stderr, "%s : dlsym property_set failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_set(szKey, szValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} ++ ++CamOsRet_e CamOsPropertyGet(const char *szKey, char *szValue, const char *szDefaultValue) ++{ ++ CamOsRet_e eRet = CAM_OS_OK; ++#ifdef CAM_OS_RTK ++ ++#elif defined(CAM_OS_LINUX_USER) ++ void *pLibHandle = NULL; ++ s32(*dlsym_property_get)(const char *szKey, char *szValue, const char *szDefaultValue) = NULL; ++ ++ do ++ { ++ pLibHandle = dlopen("libat.so", RTLD_NOW); ++ if(NULL == pLibHandle) ++ { ++ fprintf(stderr, "%s : load libat.so error \n", __FUNCTION__); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ dlsym_property_get = dlsym(pLibHandle, "property_get"); ++ if(NULL == dlsym_property_get) ++ { ++ fprintf(stderr, "%s : dlsym property_get failed, %s\n", __FUNCTION__, dlerror()); ++ eRet = CAM_OS_FAIL; ++ break; ++ } ++ ++ dlsym_property_get(szKey, szValue, szDefaultValue); ++ } ++ while(0); ++ ++ if(pLibHandle) ++ { ++ dlclose(pLibHandle); ++ } ++#elif defined(CAM_OS_LINUX_KERNEL) ++ ++#endif ++ return eRet; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/linux/cam_os_wrapper.h b/drivers/mstar/jpe2/drv/test/linux/cam_os_wrapper.h +new file mode 100644 +index 00000000..6ffbb84b +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/linux/cam_os_wrapper.h +@@ -0,0 +1,489 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////// ++/// @file cam_os_wrapper.h ++/// @brief Cam OS Wrapper Header File for ++/// 1. RTK OS ++/// 2. Linux User Space ++/// 3. Linux Kernel Space ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __CAM_OS_WRAPPER_H__ ++#define __CAM_OS_WRAPPER_H__ ++ ++#if !defined(__KERNEL__) ++typedef unsigned char bool; ++#endif ++typedef unsigned char u8; ++typedef signed char s8; ++typedef unsigned short u16; ++typedef signed short s16; ++typedef unsigned int u32; ++typedef signed int s32; ++typedef unsigned long long u64; ++typedef signed long long s64; ++ ++typedef enum ++{ ++ CAM_OS_OK = 0, ++ CAM_OS_FAIL = -1, ++ CAM_OS_PARAM_ERR = -2, ++ CAM_OS_ALLOCMEM_FAIL = -3, ++ CAM_OS_TIMEOUT = -4, ++} CamOsRet_e; ++ ++typedef struct ++{ ++ u8 nPriv[40]; ++} CamOsMutex_t; ++ ++typedef struct ++{ ++ u8 nPriv[80]; ++} CamOsTsem_t; ++ ++typedef struct ++{ ++ u32 nSec; ++ u32 nNanoSec; ++} CamOsTimespec_t; ++ ++typedef struct ++{ ++ u32 nPriority; /* From 1(lowest) to 99(highest) */ ++ u32 nStackSize; /* If nStackSize is zero, use OS default value */ ++} CamOsThreadAttrb_t, *pCamOsThreadAttrb; ++ ++typedef void * CamOsThread; ++ ++//============================================================================= ++// Description: ++// Writes the C string pointed by format to the standard output. ++// Parameters: ++// [in] szFmt: C string that contains the text to be written, it can ++// optionally contain embedded format specifiers. ++// Return: ++// N/A ++//============================================================================= ++void CamOsDebug(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Reads data from stdin and stores them according to the parameter format ++// into the locations pointed by the additional arguments. ++// Parameters: ++// [in] szFmt: C string that contains the text to be parsing, it can ++// optionally contain embedded format specifiers. ++// Return: ++// The number of items of the argument list successfully filled. ++//============================================================================= ++s32 CamOsScanf(const char *szFmt, ...); ++ ++//============================================================================= ++// Description: ++// Returns the next character from the standard input. ++// Parameters: ++// N/A ++// Return: ++// the character read is returned. ++//============================================================================= ++s32 CamOsGetChar(void); ++ ++//============================================================================= ++// Description: ++// Suspend execution for millisecond intervals. ++// Parameters: ++// [in] nMsec: Millisecond to suspend. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMsSleep(u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Gets the current time of the clock specified, and puts it into the ++// buffer pointed to by ptRes. ++// Parameters: ++// [out] nMsec: A pointer to a CamOsTimespec_t structure where ++// CamOsGetMonotonicTime() can store the time. ++// Return: ++// N/A ++//============================================================================= ++void CamOsGetMonotonicTime(CamOsTimespec_t *ptRes); ++ ++//============================================================================= ++// Description: ++// The CamOsThreadCreate() function is used to create a new thread/task, ++// with attributes specified by ptAttrb. If ptAttrb is NULL, the default ++// attributes are used. ++// Parameters: ++// [out] pThread: A successful call to CamOsThreadCreate() stores the handle ++// of the new thread in the buffer pointed to by pThread. ++// [in] ptAttrb: Argument points to a CamOsThreadAttrb_t structure whose ++// contents are used at thread creation time to determine ++// thread priority and stack size. Thread priority range from ++// 1(lowest) to 99(highest). ++// [in] pfnStartRoutine(): The new thread starts execution by invoking it. ++// [in] pArg: It is passed as the sole argument of pfnStartRoutine(). ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadCreate(CamOsThread *pThread, ++ CamOsThreadAttrb_t *ptAttrb, ++ void *(*pfnStartRoutine)(void *), ++ void *pArg); ++ ++//============================================================================= ++// Description: ++// Waits for the thread specified by pThread to terminate. If that thread ++// has already terminated, then CamOsThreadJoin() returns immediately. This ++// function is not applicable to Linux kernel space. ++// Parameters: ++// [in] thread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadJoin(CamOsThread thread); ++ ++//============================================================================= ++// Description: ++// Stop a thread created by CamOsThreadCreate in Linux kernel space. This ++// function is not applicable to RTK and Linux user space. ++// Parameters: ++// [in] thread: Handle of target thread. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadStop(CamOsThread thread); ++ ++//============================================================================= ++// Description: ++// When someone calls CamOsThreadStop, it will be woken and this will ++// return true. You should then return from the thread. This function is ++// not applicable to RTK and Linux user space. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadShouldStop(void); ++ ++//============================================================================= ++// Description: ++// Set the name of a thread. The thread name is a meaningful C language ++// string, whose length is restricted to 16 characters, including the ++// terminating null byte ('\0'). ++// Parameters: ++// [in] thread: Handle of target thread. ++// [in] szName: specifies the new name. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadSetName(CamOsThread thread, const char *szName); ++ ++//============================================================================= ++// Description: ++// Get the name of a thread. The buffer specified by name should be at ++// least 16 characters in length. ++// Parameters: ++// [in] thread: Handle of target thread. ++// [out] szName: Buffer used to return the thread name. ++// [in] nLen: Specifies the number of bytes available in szName ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsThreadGetName(CamOsThread thread, const char *szName, u32 nLen); ++ ++//============================================================================= ++// Description: ++// Get thread identification. ++// Parameters: ++// N/A ++// Return: ++// On success, returns the thread ID of the calling process. ++//============================================================================= ++u32 CamOsThreadGetID(void); ++ ++//============================================================================= ++// Description: ++// Initializes the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to initialize. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexInit(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Destroys the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexDestroy(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Lock the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to lock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexLock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Unlock the mutex. ++// Parameters: ++// [in] ptMutex: The mutex to unlock. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsMutexUnlock(CamOsMutex_t *ptMutex); ++ ++//============================================================================= ++// Description: ++// Initializes the semaphore at a given value. ++// Parameters: ++// [in] ptTsem: The semaphore to initialize. ++// [in] nVal: the initial value of the semaphore. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemInit(CamOsTsem_t *ptTsem, u32 nVal); ++ ++//============================================================================= ++// Description: ++// Destroy the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to destroy. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemDeinit(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Increases the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to increase. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemUp(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemDown(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Decreases the value of the semaphore. Blocks if the semaphore value is ++// zero. ++// Parameters: ++// [in] ptTsem: The semaphore to decrease ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if down successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTimedDown(CamOsTsem_t *ptTsem, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Signal the condition, if waiting. ++// Parameters: ++// [in] ptTsem: The semaphore to signal ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemSignal(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTsem: The semaphore to wait. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemWait(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Wait on the condition. ++// Parameters: ++// [in] ptTsem: The semaphore to wait. ++// Return: ++// If the timeout is reached the function exits with error CAM_OS_TIMEOUT. ++// CAM_OS_OK is returned if wait successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsTsemTimedWait(CamOsTsem_t *ptTsem, u32 nMsec); ++ ++//============================================================================= ++// Description: ++// Get the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to reset. ++// Return: ++// The value of the semaphore. ++//============================================================================= ++u32 CamOsTsemGetValue(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Reset the value of the semaphore. ++// Parameters: ++// [in] ptTsem: The semaphore to reset. ++// Return: ++// N/A ++//============================================================================= ++void CamOsTsemReset(CamOsTsem_t *ptTsem); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of memory, returning a pointer to the ++// beginning of the block. ++// Parameters: ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemAlloc(u32 nSize); ++ ++//============================================================================= ++// Description: ++// Allocates a block of memory for an array of nNum elements, each of them ++// nSize bytes long, and initializes all its bits to zero. ++// Parameters: ++// [in] nNum: Number of elements to allocate. ++// [in] nSize: Size of each element. ++// Return: ++// On success, a pointer to the memory block allocated by the function. If ++// failed to allocate, a null pointer is returned. ++//============================================================================= ++void* CamOsMemCalloc(u32 nNum, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Changes the size of the memory block pointed to by pPtr. The function ++// may move the memory block to a new location (whose address is returned ++// by the function). ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// [in] nSize: New size for the memory block, in bytes. ++// Return: ++// A pointer to the reallocated memory block, which may be either the same ++// as pPtr or a new location. ++//============================================================================= ++void* CamOsMemRealloc(void* pPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsMemAlloc, ++// CamOsMemCalloc or CamOsMemRealloc is deallocated, making it available ++// again for further allocations. If pPtr is a null pointer, the function ++// does nothing. ++// Parameters: ++// [in] pPtr: Pointer to a memory block previously allocated with ++// CamOsMemAlloc, CamOsMemCalloc or CamOsMemRealloc. ++// Return: ++// N/A ++//============================================================================= ++void CamOsMemRelease(void* pPtr); ++ ++//============================================================================= ++// Description: ++// Allocates a block of nSize bytes of direct memory (non-cached memory), ++// returning three pointer for different address domain to the beginning ++// of the block. ++// Parameters: ++// [in] szName: Name of the memory block, whose length is restricted to ++// 16 characters. ++// [in] nSize: Size of the memory block, in bytes. ++// [out] ppUserPtr: Virtual address pointer to the memory block. ++// [out] pMiuAddr: Memory Interface Unit address pointer to the memory block. ++// [out] lpPhysAddr: Physical address pointer to the memory block. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemAlloc(const char* szName, ++ u32 nSize, ++ void** ppUserPtr, ++ u32 *pMiuAddr, ++ u64 *lpPhysAddr); ++ ++//============================================================================= ++// Description: ++// A block of memory previously allocated by a call to CamOsDirectMemAlloc, ++// is deallocated, making it available again for further allocations. ++// Parameters: ++// [in] pUserPtr: Virtual address pointer to a memory block previously allocated with ++// CamOsDirectMemAlloc. ++// [in] nSize: Size of the memory block, in bytes. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemRelease(void* pUserPtr, u32 nSize); ++ ++//============================================================================= ++// Description: ++// Print all allocated direct memory information to the standard output. ++// Parameters: ++// N/A ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsDirectMemStat(void); ++ ++//============================================================================= ++// Description: ++// Set property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [in] szValue: Value if property. ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertySet(const char *szKey, const char *szValue); ++ ++//============================================================================= ++// Description: ++// Get property value by property name. ++// Parameters: ++// [in] szKey: Name of property. ++// [out] szValue: Value if property. ++// [in] szDefaultValue: If the property read fails or returns an empty ++// value, the default value is used ++// Return: ++// CAM_OS_OK is returned if successful; otherwise, returns CamOsRet_e. ++//============================================================================= ++CamOsRet_e CamOsPropertyGet(const char *szkey, char *szValue, const char *szDefaultValue); ++ ++#endif /* __CAM_OS_WRAPPER_H__ */ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/linux/jpe_test_i_sw.c b/drivers/mstar/jpe2/drv/test/linux/jpe_test_i_sw.c +new file mode 100644 +index 00000000..11743c8e +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/linux/jpe_test_i_sw.c +@@ -0,0 +1,732 @@ ++#ifndef __VER_JPE__ ++#define __VER_JPE__ ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "cam_os_wrapper.h" ++#include "drv_jpe_enc.h" ++ ++#include "md5.h" ++#include "util_pattern.h" ++ ++#define RED "\e[1;31m" ++#define BLUE "\e[1;34m" ++#define NORMAL "\e[0m" ++ ++#define JPEG_TEST_COUNT 10 ++#define JPEG_TEST_SUCCESS 0 ++#define JPEG_TEST_FAIL -1 ++#define JPEG_SCALE_FACTOR 100 // valid range is 1~100 ++ ++#define DEVICE_PATH "/dev/mstar_jpe0" ++ ++typedef struct KMA_t ++{ ++ void* user_ptr; ++ unsigned long miu_addr; ++ unsigned long phys_addr; ++ unsigned long mem_size; ++} KMA_t; ++ ++static KMA_t _gKmaFileIn_1; // used for YUV RAW data ++static KMA_t _gKmaFileOut_1; // used for JPEG encoded data ++static KMA_t _gKmaFileIn_2; // used for YUV RAW data ++static KMA_t _gKmaFileOut_2; // used for JPEG encoded data ++ ++static pthread_t _gTask1 = NULL; ++static pthread_t _gTask2 = NULL; ++ ++ ++ ++// YUV Test Data ++typedef struct HashResult_t ++{ ++ char pName[16]; ++ int size; ++ char pDigest[33]; ++} HashResult_t; ++ ++HashResult_t _gpYUVHash[] = ++{ ++ { "CIF.nv12", 152064, "2e32b62eeb3feea39d0046d15ada1db9" }, ++ { "CIF.nv21", 152064, "34cf41b049437fbb681717ccda4e2332" }, ++ { "CIF.yuyv", 202752, "d0b623f5f4f35f131fb2fae18d47f3a0" }, ++ { "CIF.yvyu", 202752, "949d22105ef7a93492467fa1dc18887b" }, ++ ++ { "VGA.nv12", 460800, "e5fb3e8491eb71de307fc7318a502753" }, ++ { "VGA.nv21", 460800, "0cf5b6a6e29f898b2e0f027e7b6a3d59" }, ++ { "VGA.yuyv", 614400, "ba04b608701c9ef4e34116e46cf2a983" }, ++ { "VGA.yvyu", 614400, "bafe471ea8445185d6b9050d75c5012a" }, ++ ++ { "1088P.nv12", 3133440, "929b9895da1ac761669b7fc5751ed8eb" }, ++ { "1088P.nv21", 3133440, "566276a1043b8440be166d9f417ad6eb" }, ++ { "1088P.yuyv", 4177920, "8f3b83841950a7b068ea81bca1b22ef8" }, ++ { "1088P.yvyu", 4177920, "71d63f2f73c1a55fbe5c5d4b25253f13" }, ++ ++ // TODO: make new sample for 2688x1536 ++ { "1536P.nv12", 3133440, "wrong hash value" }, ++ { "1536P.nv21", 3133440, "wrong hash value" }, ++ { "1536P.yuyv", 4177920, "wrong hash value" }, ++ { "1536P.yvyu", 4177920, "wrong hash value" }, ++}; ++ ++HashResult_t _gpJpegBinHash[] = ++{ ++ { "CIF.nv12", 3851, "b6ad3146d0863cf22f9edc9b15e1bbb7" }, ++ { "CIF.nv21", 3851, "b6ad3146d0863cf22f9edc9b15e1bbb7" }, ++ { "CIF.yuyv", 5376, "5dd1c1ed4f618e5e094f109acfcea61b" }, ++ { "CIF.yvyu", 5376, "5dd1c1ed4f618e5e094f109acfcea61b" }, ++ ++ { "VGA.nv12", 9380, "b07682d407fefa06867d0564db356f4b" }, ++ { "VGA.nv21", 9380, "b07682d407fefa06867d0564db356f4b" }, ++ { "VGA.yuyv", 12401, "e31c3c1bb5b01e2e23a09b38225ec742" }, ++ { "VGA.yvyu", 12401, "e31c3c1bb5b01e2e23a09b38225ec742" }, ++ ++ { "1088P.nv12", 46752, "050e81bdacbab019af6ffa07c9c44e53" }, ++ { "1088P.nv21", 46752, "050e81bdacbab019af6ffa07c9c44e53" }, ++ { "1088P.yuyv", 58892, "2868008e81f83f436aea57556652f8a4" }, ++ { "1088P.yvyu", 58892, "2868008e81f83f436aea57556652f8a4" }, ++ ++ { "1536P.nv12", 46752, "wrong hash value" }, ++ { "1536P.nv21", 46752, "wrong hash value" }, ++ { "1536P.yuyv", 58892, "wrong hash value" }, ++ { "1536P.yvyu", 58892, "wrong hash value" }, ++}; ++ ++ ++#define DCTSIZE2 64 ++u16 std_luminance_quant_tbl[DCTSIZE2] = ++{ ++ 16, 11, 10, 16, 24, 40, 51, 61, ++ 12, 12, 14, 19, 26, 58, 60, 55, ++ 14, 13, 16, 24, 40, 57, 69, 56, ++ 14, 17, 22, 29, 51, 87, 80, 62, ++ 18, 22, 37, 56, 68, 109, 103, 77, ++ 24, 35, 55, 64, 81, 104, 113, 92, ++ 49, 64, 78, 87, 103, 121, 120, 101, ++ 72, 92, 95, 98, 112, 100, 103, 99 ++}; ++ ++u16 std_chrominance_quant_tbl[DCTSIZE2] = ++{ ++ 17, 18, 24, 47, 99, 99, 99, 99, ++ 18, 21, 26, 66, 99, 99, 99, 99, ++ 24, 26, 56, 99, 99, 99, 99, 99, ++ 47, 66, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99 ++}; ++ ++ ++typedef enum JPEG_TEST_CLOCK_e ++{ ++ // clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ eCLK_288 = 0, ++ eCLK_216, ++ eCLK_54, ++ eCLK_27 ++} JPEG_TEST_CLOCK_e; ++ ++ ++typedef enum JPEG_TEST_RESOLUTION_e ++{ ++ eRESOLUTION_CIF = 0, ++ eRESOLUTION_VGA, ++ eRESOLUTION_1088P, // 1920x1088 ++ eRESOLUTION_1536P, // 2688x1536 ++} JPEG_TEST_RESOLUTION_e; ++ ++char *_gpResolutionName[] = ++{ ++ "CIF", ++ "VGA", ++ "1080P" ++}; ++ ++typedef enum JPEG_TEST_FORMAT_e ++{ ++ eNV12 = 0, ++ eNV21, ++ eYUYV, ++ eYVYU ++} JPEG_TEST_FORMAT_e; ++ ++struct bo ++{ ++ void *ptrHead; ++ void *ptr; ++ size_t size; ++ size_t offset; ++ size_t pitch; ++}; ++ ++ ++static unsigned char _gDbgMsgFlag = 0; ++ ++ ++ ++#if 0 ++unsigned int GetHash(char *pFileName, unsigned char digest[]) ++{ ++ unsigned int nSize = 0; ++ md5_state_t c; ++ ++ unsigned char *pBuffer = NULL; ++ FILE *pFile; ++ ++ if(!pFileName) ++ printf("pFileName is NULL\n"); ++ ++ pFile = fopen(pFileName, "r"); ++ if(pFile) ++ { ++ fseek(pFile, 0L, SEEK_END); ++ nSize = ftell(pFile); ++ fseek(pFile, 0L, SEEK_SET); ++ ++ pBuffer = malloc(nSize); ++ ++ fread(pBuffer, 1, nSize, pFile); ++ fclose(pFile); ++ ++ Md5Init(&c); ++ Md5Append(&c, pBuffer, nSize); ++ Md5Finish(&c, digest); ++ ++ free(pBuffer); ++ } ++ else ++ { ++ printf("fopen %s fail\n", pFileName); ++ } ++ return 1; ++} ++#endif ++ ++ ++static void _PatternRelease(struct bo *pBo) ++{ ++ CamOsMemRelease(pBo); ++} ++ ++static struct bo * ++_PatternCreate(unsigned int format, ++ unsigned int width, unsigned int height, ++ unsigned int handles[4], unsigned int pitches[4], ++ unsigned int offsets[4], UtilFillPattern_e pattern, void* pMemory) ++{ ++ unsigned int virtual_height; ++ struct bo *pBo; ++ unsigned int bpp; ++ void *planes[3] = { 0, }; ++ void *virtual; ++ ++ switch(format) ++ { ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ bpp = 8; ++ break; ++ ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ bpp = 16; ++ break; ++ ++ default: ++ CamOsDebug("unsupported format 0x%08x\n", format); ++ return NULL; ++ } ++ ++ switch(format) ++ { ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ virtual_height = height * 3 / 2; ++ break; ++ ++ default: ++ virtual_height = height; ++ break; ++ } ++ ++ pBo = CamOsMemCalloc(1, sizeof(struct bo)); ++ pBo->size = width * virtual_height * bpp / 8; ++ pBo->ptr = (void *)((int)(pMemory)); ++ ++ pBo->pitch = width * bpp / 8; ++ pBo->offset = 0; ++ ++ virtual = pBo->ptr; ++ ++ /* just testing a limited # of formats to test single ++ * and multi-planar path.. would be nice to add more.. ++ */ ++ switch(format) ++ { ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ offsets[0] = 0; ++ pitches[0] = pBo->pitch; ++ planes[0] = virtual; ++ break; ++ ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ offsets[0] = 0; ++ pitches[0] = pBo->pitch; ++ pitches[1] = pitches[0]; ++ offsets[1] = pitches[0] * height; ++ ++ planes[0] = virtual; ++ planes[1] = virtual + offsets[1]; ++ break; ++ } ++ ++ UtilFillPattern(format, pattern, planes, width, height, pitches[0]); ++ ++ return pBo; ++} ++ ++static void _DumpDigest(unsigned char *pDigest) ++{ ++ int j; ++ for(j = 0 ; j < 16; j++) ++ { ++ CamOsDebug("%02x", pDigest[j]); ++ } ++} ++ ++ ++static int _CompareDigest(char *pDigestStrIn, unsigned char *pDigestHex) ++{ ++ unsigned char j, tmp; ++ unsigned char pDigestStr[33]; ++ ++ for(j = 0 ; j < 16; j++) ++ { ++ //sprintf(pDigestStr + j*2, "%02x", pDigestHex[j]); ++ tmp = (pDigestHex[j] & 0xF0) >> 4; ++ pDigestStr[2 * j] = tmp >= 0x0a ? tmp - 10 + 'a' : tmp + '0'; ++ ++ tmp = (pDigestHex[j] & 0x0F); ++ pDigestStr[2 * j + 1] = tmp >= 0x0a ? tmp - 10 + 'a' : tmp + '0'; ++ } ++ ++ return memcmp(pDigestStrIn, pDigestStr, 32); ++} ++ ++static void _PrepareInputBuffer_1(void) ++{ ++ int nSize; ++ int eRet = CAM_OS_OK; ++ ++ u32* pInUserPtr; ++ u32 nInMiuAddr; ++ u64 nlInPhysAddr; ++ ++ u32* pOutUserPtr; ++ u32 nOutMiuAddr; ++ u64 nlOutPhysAddr; ++ ++ // NOTE: 4177920 is used for 1920x1088 resolution, enlarge size if you want to test large resolution ++ nSize = 4177920; ++ ++ eRet = CamOsDirectMemAlloc("JPE_IN1", ++ nSize, ++ (void**)&pInUserPtr, ++ &nInMiuAddr, ++ &nlInPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ eRet = CamOsDirectMemAlloc("JPE_OUT1", ++ nSize/2, ++ (void**)&pOutUserPtr, ++ &nOutMiuAddr, ++ &nlOutPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ _gKmaFileIn_1.user_ptr = pInUserPtr; ++ _gKmaFileIn_1.phys_addr = (unsigned long)nlInPhysAddr; ++ _gKmaFileIn_1.mem_size = (unsigned long)nSize; ++ _gKmaFileOut_1.user_ptr = pOutUserPtr; ++ _gKmaFileOut_1.phys_addr = (unsigned long)nlOutPhysAddr; ++ _gKmaFileOut_1.mem_size = (unsigned long)nSize / 2; ++} ++ ++ ++static void _PrepareInputBuffer_2(void) ++{ ++ int nSize; ++ int eRet = CAM_OS_OK; ++ ++ u32* pInUserPtr; ++ u32 nInMiuAddr; ++ u64 nlInPhysAddr; ++ ++ u32* pOutUserPtr; ++ u32 nOutMiuAddr; ++ u64 nlOutPhysAddr; ++ ++ // NOTE: 4177920 is used for 1920x1088 resolution, enlarge size if you want to test large resolution ++ nSize = 4177920; ++ ++ eRet = CamOsDirectMemAlloc("JPE_IN2", ++ nSize, ++ (void**)&pInUserPtr, ++ &nInMiuAddr, ++ &nlInPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ eRet = CamOsDirectMemAlloc("JPE_OUT2", ++ nSize/2, ++ (void**)&pOutUserPtr, ++ &nOutMiuAddr, ++ &nlOutPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ _gKmaFileIn_2.user_ptr = pInUserPtr; ++ _gKmaFileIn_2.phys_addr = (unsigned long)nlInPhysAddr; ++ _gKmaFileIn_2.mem_size = (unsigned long)nSize; ++ _gKmaFileOut_2.user_ptr = pOutUserPtr; ++ _gKmaFileOut_2.phys_addr = (unsigned long)nlOutPhysAddr; ++ _gKmaFileOut_2.mem_size = (unsigned long)nSize / 2; ++} ++ ++static void _ReleaseInputBuffer_1(void) ++{ ++ CamOsDirectMemRelease(_gKmaFileIn_1.user_ptr, _gKmaFileIn_1.mem_size); ++ CamOsDirectMemRelease(_gKmaFileOut_1.user_ptr, _gKmaFileOut_1.mem_size); ++} ++ ++static void _ReleaseInputBuffer_2(void) ++{ ++ CamOsDirectMemRelease(_gKmaFileIn_2.user_ptr, _gKmaFileIn_2.mem_size); ++ CamOsDirectMemRelease(_gKmaFileOut_2.user_ptr, _gKmaFileOut_2.mem_size); ++} ++ ++static int _DoEncode(JPEG_TEST_CLOCK_e eClkSelect, JPEG_TEST_RESOLUTION_e nRes, JPEG_TEST_FORMAT_e eRawFormat, int bDebugMsg, int nTaskId) ++{ ++ int nDev; ++ int pFormat[] = {DRM_FORMAT_NV12, DRM_FORMAT_NV21, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU}; ++ //char pSuffix[][5] = { "nv12", "nv21", "yuyv", "yvyu"}; ++ ++ unsigned char pDigest[16]; ++ int nSize; ++ int width = 320; ++ int height = 240; ++ ++ unsigned int handles[4] = {0}; ++ unsigned int pitches[4] = {0}; ++ unsigned int offsets[4] = {0}; ++ UtilFillPattern_e ePattern = UTIL_PATTERN_SMPTE; ++ ++ md5_state_t tMd5State; ++ struct bo *pBo; ++ ++ KMA_t *pKmaFileIn; // used for YUV RAW data ++ KMA_t *pKmaFileOut; // used for JPEG encoded data ++ ++ if(_gTask1 == nTaskId) ++ { ++ pKmaFileIn = &_gKmaFileIn_1; ++ pKmaFileOut = &_gKmaFileOut_1; ++ } ++ else ++ { ++ pKmaFileIn = &_gKmaFileIn_2; ++ pKmaFileOut = &_gKmaFileOut_2; ++ } ++ ++ switch(nRes) ++ { ++ case eRESOLUTION_CIF: ++ width = 352; ++ height = 288; ++ break; ++ ++ case eRESOLUTION_VGA: ++ width = 640; ++ height = 480; ++ break; ++ ++ case eRESOLUTION_1088P: ++ width = 1920; ++ height = 1088; ++ break; ++ ++ case eRESOLUTION_1536P: ++ width = 2688; ++ height = 1536; ++ break; ++ ++ default: ++ CamOsDebug("unknow resolution\n"); ++ return JPEG_TEST_FAIL; ++ break; ++ } ++ ++ // Step 1. generate pattern ++ pBo = _PatternCreate(pFormat[eRawFormat], width, height, handles, pitches, offsets, ePattern, pKmaFileIn->user_ptr); ++ if(bDebugMsg) ++ { ++ CamOsDebug("Expected Pattern : size = %d, Hash = %s\n", _gpYUVHash[eRawFormat + 4 * nRes].size, _gpYUVHash[eRawFormat + 4 * nRes].pDigest); ++ CamOsDebug("Actual Pattern : size = %d, ", pBo->size); ++ } ++ ++ if(_gpYUVHash[eRawFormat + 4 * nRes].size != pBo->size) ++ { ++ CamOsDebug("%sError!!!! Task(%d) Size(%d) mismatch with %d%s\n", RED, nTaskId, (int)(pBo->size), _gpYUVHash[eRawFormat + 4 * nRes].size, NORMAL); ++ } ++ ++#if 0 // raw data hash is slow, so we only enable it when needed. ++ memset(&tMd5State, sizeof(tMd5State), 0); ++ Md5Init(&tMd5State); ++ Md5Append(&tMd5State, pBo->ptr, pBo->size); ++ Md5Finish(&tMd5State, pDigest); ++ CamOsDebug("Hash = "); ++ _DumpDigest(pDigest); ++ CamOsDebug("\n\n"); ++#else ++ CamOsDebug("\n"); ++#endif ++ ++ // Step 2. RAW data to JPEG (without header) ++ JpeParam_t tParam; ++ JpeCfg_t *pJpeCfg = &tParam.tJpeCfg; ++ ++ memset(pJpeCfg, 0, sizeof(JpeCfg_t)); ++ ++ pJpeCfg->eInBufMode = JPE_IBUF_FRAME_MODE; ++ pJpeCfg->eCodecFormat = JPE_CODEC_JPEG; ++ ++ if(eNV12 == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_NV12; ++ else if(eNV21 == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_NV21; ++ else if(eYUYV == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_YUYV; ++ else if(eYVYU == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_YVYU; ++ ++ pJpeCfg->nWidth = width; ++ pJpeCfg->nHeight = height; ++ pJpeCfg->nQScale = JPEG_SCALE_FACTOR; ++ memcpy(pJpeCfg->YQTable, std_luminance_quant_tbl, DCTSIZE2 * sizeof(unsigned short)); ++ memcpy(pJpeCfg->CQTable, std_chrominance_quant_tbl, DCTSIZE2 * sizeof(unsigned short)); ++ ++ nSize = pBo->size; ++ ++ // Assign buffer for test ++ pJpeCfg->OutBuf.nAddr = (unsigned long)pKmaFileOut->phys_addr; ++ pJpeCfg->OutBuf.nSize = pKmaFileOut->mem_size; ++ ++ if(eYUYV == eRawFormat || eYVYU == eRawFormat) ++ { ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr = (unsigned int)pKmaFileIn->phys_addr; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize = nSize; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr = 0; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nSize = 0; ++ } ++ else if(eNV21 == eRawFormat || eNV12 == eRawFormat) ++ { ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr = (unsigned int)pKmaFileIn->phys_addr; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize = width * height; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr = (unsigned int)(pKmaFileIn->phys_addr + width * height); ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nSize = nSize - width * height; ++ } ++ ++ tParam.nClkSelect = (unsigned short)eClkSelect; ++ ++ nDev = open(DEVICE_PATH, O_RDWR); ++ if(nDev <= 0) ++ { ++ CamOsDebug("Can't open device %s return=%d errno=%d\n", DEVICE_PATH, nDev, errno); ++ return -1; ++ } ++ JpeEncode(&tParam, nDev); ++ ++ // Step 3. generate hash for JPEG encoded data ++ memset(&tMd5State, sizeof(tMd5State), 0); ++ Md5Init(&tMd5State); ++ // omit the end of JFIF (0xFFD9) ++ //Md5Append(&tMd5State, (const Md5Byte_t *)pJpeCfg->OutBuf.nAddr, (int)tParam.nEncodeSize - 2); ++ Md5Append(&tMd5State, (const Md5Byte_t *)pKmaFileOut->user_ptr, (int)tParam.nEncodeSize - 2); ++ Md5Finish(&tMd5State, pDigest); ++ ++ if(tParam.nEncodeSize > pJpeCfg->OutBuf.nSize) ++ { ++ CamOsDebug("%sTask(%d) Error!!!! nEncodeSize(%d) > OutBufSize(%d). This should never happen!! \n", RED, nTaskId, (int)(tParam.nEncodeSize), pJpeCfg->OutBuf.nSize, NORMAL); ++ } ++ ++ if(_gpJpegBinHash[eRawFormat + 4 * nRes].size != tParam.nEncodeSize - 2) ++ { ++ CamOsDebug("%sTask(%d) Error!!!! Size(%d) mismatch with %d%s\n", RED, nTaskId, (int)(tParam.nEncodeSize - 2), _gpJpegBinHash[eRawFormat + 4 * nRes].size, NORMAL); ++ } ++ ++ if(0 != _CompareDigest(_gpJpegBinHash[eRawFormat + 4 * nRes].pDigest, pDigest)) ++ { ++ CamOsDebug("%sTask(%d) Error!!!! Digest(", RED, nTaskId); ++ _DumpDigest(pDigest); ++ CamOsDebug(") mismatch with %s%s\n", _gpJpegBinHash[eRawFormat + 4 * nRes].pDigest, NORMAL); ++ } ++ else ++ { ++ if(bDebugMsg) ++ { ++ CamOsDebug("Expected result size is %d\n", _gpJpegBinHash[eRawFormat + 4 * nRes].size); ++ CamOsDebug("Expected Hash is %s\n", _gpJpegBinHash[eRawFormat + 4 * nRes].pDigest); ++ CamOsDebug("Actual Hash is "); ++ _DumpDigest(pDigest); ++ CamOsDebug("\n"); ++ } ++ CamOsDebug("Encode done. Hash value for %dx%d check pass.\n\n", width, height); ++ ++ } ++ ++ _PatternRelease(pBo); ++ ++ return JPEG_TEST_SUCCESS; ++} ++ ++static int _DoTest(JPEG_TEST_FORMAT_e eRawFormat, int bDebugMsg, int nTaskId) ++{ ++ int nRet; ++ JPEG_TEST_CLOCK_e eClkSelect = eCLK_288; ++ JPEG_TEST_RESOLUTION_e eRes = eRESOLUTION_1088P; ++ ++ CamOsDebug("===="); ++ switch(eRawFormat) ++ { ++ case eNV12: ++ CamOsDebug(" Raw format: eNV12 "); ++ break; ++ case eNV21: ++ CamOsDebug(" Raw format: eNV21 "); ++ break; ++ case eYUYV: ++ CamOsDebug(" Raw format: eYUYV "); ++ break; ++ case eYVYU: ++ CamOsDebug(" Raw format: eYVYU "); ++ break; ++ } ++ CamOsDebug(" ====\n"); ++ ++ ++#if JPE_DRIVER_VER == 2 ++ for(eClkSelect = eCLK_288; eClkSelect <= eCLK_27; eClkSelect++) ++#else ++ // do nothing, JPE Driver V1 don't support clock rate change. ++#endif ++ { ++ ++ switch(eClkSelect) ++ { ++ case eCLK_288: ++ CamOsDebug("%s Task:0x%x Clock: eCLK_288 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ case eCLK_216: ++ CamOsDebug("%s Task:0x%x Clock: eCLK_216 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ case eCLK_54: ++ CamOsDebug("%s Task:0x%x Clock: eCLK_54 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ case eCLK_27: ++ CamOsDebug("%s Task:0x%x Clock: eCLK_27 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ } ++ ++ for(eRes = eRESOLUTION_CIF; eRes <= eRESOLUTION_1088P; eRes++) ++ { ++ switch(eRes) ++ { ++ case eRESOLUTION_CIF: ++ CamOsDebug("%s Res: CIF %s \n", BLUE, NORMAL); ++ break; ++ case eRESOLUTION_VGA: ++ CamOsDebug("%s Res: VGA %s \n", BLUE, NORMAL); ++ break; ++ case eRESOLUTION_1088P: ++ CamOsDebug("%s Res: 1920x1088 %s \n", BLUE, NORMAL); ++ break; ++ case eRESOLUTION_1536P: ++ CamOsDebug("%s Res: 2688x1536 %s \n", BLUE, NORMAL); ++ break; ++ } ++ ++ nRet = _DoEncode(eClkSelect, eRes, eRawFormat, bDebugMsg, nTaskId); ++ if(JPEG_TEST_SUCCESS != nRet) ++ { ++ CamOsDebug("%s Error!!!! doEncode for resolution (%d) error!! %s\n", RED, eRes, NORMAL); ++ return -1; ++ } ++ } ++ } ++ return 0; ++ ++} ++ ++static void * _TestJpeTask1(void *pArg) ++{ ++ int i; ++ _PrepareInputBuffer_1(); ++ for(i = 0; i < JPEG_TEST_COUNT; i++) ++ { ++ _DoTest(eYUYV, _gDbgMsgFlag, _gTask1); ++ } ++ _ReleaseInputBuffer_1(); ++ return NULL; ++} ++ ++static void * _TestJpeTask2(void *pArg) ++{ ++ int i; ++ _PrepareInputBuffer_2(); ++ for(i = 0; i < JPEG_TEST_COUNT; i++) ++ { ++ _DoTest(eNV12, _gDbgMsgFlag, _gTask2); ++ } ++ _ReleaseInputBuffer_2(); ++ return NULL; ++} ++ ++int TestJpeDriverWith2Tasks() ++{ ++ // enable or disable debug message ++ _gDbgMsgFlag = 0; ++ ++ CamOsDebug("%s start of %s %s\n", BLUE, __func__, NORMAL); ++ ++ // Create Task here ++ pthread_create(&_gTask1, NULL, _TestJpeTask1, NULL); ++ pthread_create(&_gTask2, NULL, _TestJpeTask2, NULL); ++ ++ pthread_join(_gTask1, NULL); ++ CamOsDebug("Joined with thread1 0x%x\n",_gTask1); ++ ++ pthread_join(_gTask2, NULL); ++ CamOsDebug("Joined with thread2 0x%x\n",_gTask2); ++ ++ CamOsDebug("%s End of %s %s\n", BLUE, __func__, NORMAL); ++ ++ return 0; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/drv/test/rtk/jpe_test_i_sw.c b/drivers/mstar/jpe2/drv/test/rtk/jpe_test_i_sw.c +new file mode 100644 +index 00000000..5942b88e +--- /dev/null ++++ b/drivers/mstar/jpe2/drv/test/rtk/jpe_test_i_sw.c +@@ -0,0 +1,835 @@ ++#ifndef __VER_JPE__ ++#define __VER_JPE__ ++#endif ++ ++#include ++#include ++#include ++ ++#include "sys_MsWrapper_cus_os_msg.h" ++#include "sys_sys_isw_cli.h" ++#include "hal_drv_util.h" ++ ++#include "cam_os_wrapper.h" ++ ++#include "drv_jpe_io.h" ++#include "drv_jpe_io_st.h" ++#include "drv_jpe_module.h" ++#include "drv_jpe_enc.h" ++ ++#include "md5.h" ++#include "util_pattern.h" ++ ++#define RED "\e[1;31m" ++#define BLUE "\e[1;34m" ++#define NORMAL "\e[0m" ++ ++typedef struct KMA_t ++{ ++ void* user_ptr; ++ unsigned long miu_addr; ++ unsigned long phys_addr; ++ unsigned long mem_size; ++} KMA_t; ++ ++static KMA_t _gKmaFileIn_1; // used for YUV RAW data ++static KMA_t _gKmaFileOut_1; // used for JPEG encoded data ++static KMA_t _gKmaFileIn_2; // used for YUV RAW data ++static KMA_t _gKmaFileOut_2; // used for JPEG encoded data ++ ++static MsTaskId_e _gTask1; ++static MsTaskId_e _gTask2; ++ ++#define JPEG_TEST_COUNT 1 ++#define JPEG_TEST_SUCCESS 0 ++#define JPEG_TEST_FAIL -1 ++#define JPEG_SCALE_FACTOR 100 // valid range is 1~100 ++ ++// Definition for multi task ++typedef union ++{ ++ u32 userdata; ++} Body_test_t; ++ ++ ++#ifdef Body_t ++#undef Body_t ++#endif ++ ++#define Body_t Body_test_t ++ ++#include "stdmsg.ht" ++ ++#ifndef VM_MSG_DEF ++#define VM_MSG_DEF(_ENUM_, _UNION_) _ENUM_, ++#endif ++enum ++{ ++#include "sys_MsWrapper_cus_os_message_define__.hi" ++}; ++ ++ ++// YUV Test Data ++typedef struct HashResult_t ++{ ++ char pName[16]; ++ int size; ++ char pDigest[33]; ++} HashResult_t; ++ ++HashResult_t _gpYUVHash[] = ++{ ++ { "CIF.nv12", 152064, "2e32b62eeb3feea39d0046d15ada1db9" }, ++ { "CIF.nv21", 152064, "34cf41b049437fbb681717ccda4e2332" }, ++ { "CIF.yuyv", 202752, "d0b623f5f4f35f131fb2fae18d47f3a0" }, ++ { "CIF.yvyu", 202752, "949d22105ef7a93492467fa1dc18887b" }, ++ ++ { "VGA.nv12", 460800, "e5fb3e8491eb71de307fc7318a502753" }, ++ { "VGA.nv21", 460800, "0cf5b6a6e29f898b2e0f027e7b6a3d59" }, ++ { "VGA.yuyv", 614400, "ba04b608701c9ef4e34116e46cf2a983" }, ++ { "VGA.yvyu", 614400, "bafe471ea8445185d6b9050d75c5012a" }, ++ ++ { "1088P.nv12", 3133440, "929b9895da1ac761669b7fc5751ed8eb" }, ++ { "1088P.nv21", 3133440, "566276a1043b8440be166d9f417ad6eb" }, ++ { "1088P.yuyv", 4177920, "8f3b83841950a7b068ea81bca1b22ef8" }, ++ { "1088P.yvyu", 4177920, "71d63f2f73c1a55fbe5c5d4b25253f13" }, ++ ++ // TODO: make new sample for 2688x1536 ++ { "1536P.nv12", 3133440, "wrong hash value" }, ++ { "1536P.nv21", 3133440, "wrong hash value" }, ++ { "1536P.yuyv", 4177920, "wrong hash value" }, ++ { "1536P.yvyu", 4177920, "wrong hash value" }, ++}; ++ ++HashResult_t _gpJpegBinHash[] = ++{ ++ { "CIF.nv12", 3851, "b6ad3146d0863cf22f9edc9b15e1bbb7" }, ++ { "CIF.nv21", 3851, "b6ad3146d0863cf22f9edc9b15e1bbb7" }, ++ { "CIF.yuyv", 5376, "5dd1c1ed4f618e5e094f109acfcea61b" }, ++ { "CIF.yvyu", 5376, "5dd1c1ed4f618e5e094f109acfcea61b" }, ++ ++ { "VGA.nv12", 9380, "b07682d407fefa06867d0564db356f4b" }, ++ { "VGA.nv21", 9380, "b07682d407fefa06867d0564db356f4b" }, ++ { "VGA.yuyv", 12401, "e31c3c1bb5b01e2e23a09b38225ec742" }, ++ { "VGA.yvyu", 12401, "e31c3c1bb5b01e2e23a09b38225ec742" }, ++ ++ { "1088P.nv12", 46752, "050e81bdacbab019af6ffa07c9c44e53" }, ++ { "1088P.nv21", 46752, "050e81bdacbab019af6ffa07c9c44e53" }, ++ { "1088P.yuyv", 58892, "2868008e81f83f436aea57556652f8a4" }, ++ { "1088P.yvyu", 58892, "2868008e81f83f436aea57556652f8a4" }, ++ ++ { "1536P.nv12", 46752, "wrong hash value" }, ++ { "1536P.nv21", 46752, "wrong hash value" }, ++ { "1536P.yuyv", 58892, "wrong hash value" }, ++ { "1536P.yvyu", 58892, "wrong hash value" }, ++}; ++ ++ ++#define DCTSIZE2 64 ++u16 std_luminance_quant_tbl[DCTSIZE2] = ++{ ++ 16, 11, 10, 16, 24, 40, 51, 61, ++ 12, 12, 14, 19, 26, 58, 60, 55, ++ 14, 13, 16, 24, 40, 57, 69, 56, ++ 14, 17, 22, 29, 51, 87, 80, 62, ++ 18, 22, 37, 56, 68, 109, 103, 77, ++ 24, 35, 55, 64, 81, 104, 113, 92, ++ 49, 64, 78, 87, 103, 121, 120, 101, ++ 72, 92, 95, 98, 112, 100, 103, 99 ++}; ++ ++u16 std_chrominance_quant_tbl[DCTSIZE2] = ++{ ++ 17, 18, 24, 47, 99, 99, 99, 99, ++ 18, 21, 26, 66, 99, 99, 99, 99, ++ 24, 26, 56, 99, 99, 99, 99, 99, ++ 47, 66, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99, ++ 99, 99, 99, 99, 99, 99, 99, 99 ++}; ++ ++ ++typedef enum JPEG_TEST_CLOCK_e ++{ ++ // clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ eCLK_288 = 0, ++ eCLK_216, ++ eCLK_54, ++ eCLK_27 ++} JPEG_TEST_CLOCK_e; ++ ++ ++typedef enum JPEG_TEST_RESOLUTION_e ++{ ++ eRESOLUTION_CIF = 0, ++ eRESOLUTION_VGA, ++ eRESOLUTION_1088P, // 1920x1088 ++ eRESOLUTION_1536P, // 2688x1536 ++} JPEG_TEST_RESOLUTION_e; ++ ++char *_gpResolutionName[] = ++{ ++ "CIF", ++ "VGA", ++ "1080P" ++}; ++ ++typedef enum JPEG_TEST_FORMAT_e ++{ ++ eNV12 = 0, ++ eNV21, ++ eYUYV, ++ eYVYU ++} JPEG_TEST_FORMAT_e; ++ ++struct bo ++{ ++ void *ptrHead; ++ void *ptr; ++ size_t size; ++ size_t offset; ++ size_t pitch; ++}; ++ ++ ++static JpeDev_t* _gpTestDev; ++static unsigned char _gDbgMsgFlag = 0; ++ ++#if 0 ++unsigned int GetHash(char *pFileName, unsigned char digest[]) ++{ ++ unsigned int nSize = 0; ++ md5_state_t c; ++ ++ unsigned char *pBuffer = NULL; ++ FILE *pFile; ++ ++ if(!pFileName) ++ printf("pFileName is NULL\n"); ++ ++ pFile = fopen(pFileName, "r"); ++ if(pFile) ++ { ++ fseek(pFile, 0L, SEEK_END); ++ nSize = ftell(pFile); ++ fseek(pFile, 0L, SEEK_SET); ++ ++ pBuffer = malloc(nSize); ++ ++ fread(pBuffer, 1, nSize, pFile); ++ fclose(pFile); ++ ++ Md5Init(&c); ++ Md5Append(&c, pBuffer, nSize); ++ Md5Finish(&c, digest); ++ ++ free(pBuffer); ++ } ++ else ++ { ++ printf("fopen %s fail\n", pFileName); ++ } ++ return 1; ++} ++#endif ++ ++ ++static void _PatternRelease(struct bo *pBo) ++{ ++ MsReleaseMemory(pBo); ++} ++ ++static struct bo * ++_PatternCreate(unsigned int format, ++ unsigned int width, unsigned int height, ++ unsigned int handles[4], unsigned int pitches[4], ++ unsigned int offsets[4], UtilFillPattern_e pattern, void* pMemory) ++{ ++ unsigned int virtual_height; ++ struct bo *pBo; ++ unsigned int bpp; ++ void *planes[3] = { 0, }; ++ void *virtual; ++ ++ switch(format) ++ { ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ bpp = 8; ++ break; ++ ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ bpp = 16; ++ break; ++ ++ default: ++ CamOsDebug("unsupported format 0x%08x\n", format); ++ return NULL; ++ } ++ ++ switch(format) ++ { ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ virtual_height = height * 3 / 2; ++ break; ++ ++ default: ++ virtual_height = height; ++ break; ++ } ++ ++ pBo = CamOsMemCalloc(1, sizeof(struct bo)); ++ pBo->size = width * virtual_height * bpp / 8; ++ pBo->ptr = (void *)((int)(pMemory)); ++ ++ pBo->pitch = width * bpp / 8; ++ pBo->offset = 0; ++ ++ virtual = pBo->ptr; ++ ++ /* just testing a limited # of formats to test single ++ * and multi-planar path.. would be nice to add more.. ++ */ ++ switch(format) ++ { ++ case DRM_FORMAT_YUYV: ++ case DRM_FORMAT_YVYU: ++ offsets[0] = 0; ++ pitches[0] = pBo->pitch; ++ planes[0] = virtual; ++ break; ++ ++ case DRM_FORMAT_NV12: ++ case DRM_FORMAT_NV21: ++ offsets[0] = 0; ++ pitches[0] = pBo->pitch; ++ pitches[1] = pitches[0]; ++ offsets[1] = pitches[0] * height; ++ ++ planes[0] = virtual; ++ planes[1] = virtual + offsets[1]; ++ break; ++ } ++ ++ UtilFillPattern(format, pattern, planes, width, height, pitches[0]); ++ ++ return pBo; ++} ++ ++static void _DumpDigest(unsigned char *pDigest) ++{ ++ int j; ++ for(j = 0 ; j < 16; j++) ++ { ++ CamOsDebug("%02x", pDigest[j]); ++ } ++} ++ ++ ++static int _CompareDigest(char *pDigestStrIn, unsigned char *pDigestHex) ++{ ++ unsigned char j, tmp; ++ unsigned char pDigestStr[33]; ++ ++ for(j = 0 ; j < 16; j++) ++ { ++ //sprintf(pDigestStr + j*2, "%02x", pDigestHex[j]); ++ tmp = (pDigestHex[j] & 0xF0) >> 4; ++ pDigestStr[2 * j] = tmp >= 0x0a ? tmp - 10 + 'a' : tmp + '0'; ++ ++ tmp = (pDigestHex[j] & 0x0F); ++ pDigestStr[2 * j + 1] = tmp >= 0x0a ? tmp - 10 + 'a' : tmp + '0'; ++ } ++ ++ return memcmp(pDigestStrIn, pDigestStr, 32); ++} ++ ++static void _PrepareInputBuffer_1(void) ++{ ++ int nSize; ++ CamOsRet_e eRet = CAM_OS_OK; ++ ++ u32* pInUserPtr; ++ u32 nInMiuAddr; ++ u64 nlInPhysAddr; ++ ++ u32* pOutUserPtr; ++ u32 nOutMiuAddr; ++ u64 nlOutPhysAddr; ++ ++ nSize = 4177920; ++ ++ eRet = CamOsDirectMemAlloc("JPE_IN1", ++ nSize, ++ (void**)&pInUserPtr, ++ &nInMiuAddr, ++ &nlInPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ eRet = CamOsDirectMemAlloc("JPE_OUT1", ++ nSize/2, ++ (void**)&pOutUserPtr, ++ &nOutMiuAddr, ++ &nlOutPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ _gKmaFileIn_1.user_ptr = pInUserPtr; ++ _gKmaFileIn_1.phys_addr = (unsigned long)nlInPhysAddr; ++ _gKmaFileIn_1.mem_size = (unsigned long)nSize; ++ _gKmaFileOut_1.user_ptr = pOutUserPtr; ++ _gKmaFileOut_1.phys_addr = (unsigned long)nlOutPhysAddr; ++ _gKmaFileOut_1.mem_size = (unsigned long)nSize / 2; ++} ++ ++ ++static void _PrepareInputBuffer_2(void) ++{ ++ int nSize; ++ CamOsRet_e eRet = CAM_OS_OK; ++ ++ u32* pInUserPtr; ++ u32 nInMiuAddr; ++ u64 nlInPhysAddr; ++ ++ u32* pOutUserPtr; ++ u32 nOutMiuAddr; ++ u64 nlOutPhysAddr; ++ ++ nSize = 4177920; ++ ++ eRet = CamOsDirectMemAlloc("JPE_IN2", ++ nSize, ++ (void**)&pInUserPtr, ++ &nInMiuAddr, ++ &nlInPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ eRet = CamOsDirectMemAlloc("JPE_OUT2", ++ nSize/2, ++ (void**)&pOutUserPtr, ++ &nOutMiuAddr, ++ &nlOutPhysAddr); ++ if(CAM_OS_OK != eRet) ++ { ++ CamOsDebug("CamOsDirectMemAlloc fail\n"); ++ } ++ ++ _gKmaFileIn_2.user_ptr = pInUserPtr; ++ _gKmaFileIn_2.phys_addr = (unsigned long)nlInPhysAddr; ++ _gKmaFileIn_2.mem_size = (unsigned long)nSize; ++ _gKmaFileOut_2.user_ptr = pOutUserPtr; ++ _gKmaFileOut_2.phys_addr = (unsigned long)nlOutPhysAddr; ++ _gKmaFileOut_2.mem_size = (unsigned long)nSize / 2; ++} ++ ++static void _ReleaseInputBuffer_1(void) ++{ ++ MsReleaseMemory(_gKmaFileIn_1.user_ptr); ++ MsReleaseMemory(_gKmaFileOut_1.user_ptr); ++} ++ ++static void _ReleaseInputBuffer_2(void) ++{ ++ MsReleaseMemory(_gKmaFileIn_2.user_ptr); ++ MsReleaseMemory(_gKmaFileOut_2.user_ptr); ++} ++ ++static int _DoEncode(JPEG_TEST_CLOCK_e eClkSelect, JPEG_TEST_RESOLUTION_e nRes, JPEG_TEST_FORMAT_e eRawFormat, int bDebugMsg, int nTaskId) ++{ ++ int pFormat[] = {DRM_FORMAT_NV12, DRM_FORMAT_NV21, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU}; ++ //char pSuffix[][5] = { "nv12", "nv21", "yuyv", "yvyu"}; ++ ++ unsigned char pDigest[16]; ++ int nSize; ++ int width = 320; ++ int height = 240; ++ ++ unsigned int handles[4] = {0}; ++ unsigned int pitches[4] = {0}; ++ unsigned int offsets[4] = {0}; ++ UtilFillPattern_e ePattern = UTIL_PATTERN_SMPTE; ++ ++ md5_state_t tMd5State; ++ struct bo *pBo; ++ ++ KMA_t *pKmaFileIn; // used for YUV RAW data ++ KMA_t *pKmaFileOut; // used for JPEG encoded data ++ ++ if(_gTask1 == nTaskId) ++ { ++ _PrepareInputBuffer_1(); ++ pKmaFileIn = &_gKmaFileIn_1; ++ pKmaFileOut = &_gKmaFileOut_1; ++ } ++ else ++ { ++ _PrepareInputBuffer_2(); ++ pKmaFileIn = &_gKmaFileIn_2; ++ pKmaFileOut = &_gKmaFileOut_2; ++ } ++ ++ switch(nRes) ++ { ++ case eRESOLUTION_CIF: ++ width = 352; ++ height = 288; ++ break; ++ ++ case eRESOLUTION_VGA: ++ width = 640; ++ height = 480; ++ break; ++ ++ case eRESOLUTION_1088P: ++ width = 1920; ++ height = 1088; ++ break; ++ ++ case eRESOLUTION_1536P: ++ width = 2688; ++ height = 1536; ++ break; ++ ++ default: ++ CamOsDebug("unknow resolution\n"); ++ return JPEG_TEST_FAIL; ++ break; ++ } ++ ++ // Step 1. generate pattern ++ pBo = _PatternCreate(pFormat[eRawFormat], width, height, handles, pitches, offsets, ePattern, pKmaFileIn->user_ptr); ++ if(bDebugMsg) ++ { ++ CamOsDebug("Expected Pattern : size = %d, Hash = %s\n", _gpYUVHash[eRawFormat + 4 * nRes].size, _gpYUVHash[eRawFormat + 4 * nRes].pDigest); ++ CamOsDebug("Actual Pattern : size = %d, ", pBo->size); ++ } ++ ++ if(_gpYUVHash[eRawFormat + 4 * nRes].size != pBo->size) ++ { ++ CamOsDebug("%sError!!!! Task(%d) Size(%d) mismatch with %d%s\n", RED, nTaskId, (int)(pBo->size), _gpYUVHash[eRawFormat + 4 * nRes].size, NORMAL); ++ } ++ ++#if 0 // raw data hash is slow, so we only enable it when needed. ++ memset(&tMd5State, sizeof(tMd5State), 0); ++ Md5Init(&tMd5State); ++ Md5Append(&tMd5State, pBo->ptr, pBo->size); ++ Md5Finish(&tMd5State, pDigest); ++ CamOsDebug("Hash = "); ++ _DumpDigest(pDigest); ++ CamOsDebug("\n\n"); ++#else ++ CamOsDebug("\n"); ++#endif ++ ++ // Step 2. RAW data to JPEG (without header) ++ JpeParam_t tParam; ++ JpeCfg_t *pJpeCfg = &tParam.tJpeCfg; ++ ++ memset(pJpeCfg, 0, sizeof(JpeCfg_t)); ++ ++ pJpeCfg->eInBufMode = JPE_IBUF_FRAME_MODE; ++ pJpeCfg->eCodecFormat = JPE_CODEC_JPEG; ++ ++ if(eNV12 == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_NV12; ++ else if(eNV21 == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_NV21; ++ else if(eYUYV == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_YUYV; ++ else if(eYVYU == eRawFormat) pJpeCfg->eRawFormat = JPE_RAW_YVYU; ++ ++ pJpeCfg->nWidth = width; ++ pJpeCfg->nHeight = height; ++ pJpeCfg->nQScale = JPEG_SCALE_FACTOR; ++ memcpy(pJpeCfg->YQTable, std_luminance_quant_tbl, DCTSIZE2 * sizeof(unsigned short)); ++ memcpy(pJpeCfg->CQTable, std_chrominance_quant_tbl, DCTSIZE2 * sizeof(unsigned short)); ++ ++ nSize = pBo->size; ++ ++ // Assign buffer for test ++ pJpeCfg->OutBuf.nAddr = (unsigned long)pKmaFileOut->phys_addr; ++ pJpeCfg->OutBuf.nSize = pKmaFileOut->mem_size; ++ ++ if(eYUYV == eRawFormat || eYVYU == eRawFormat) ++ { ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr = (unsigned int)pKmaFileIn->phys_addr; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize = nSize; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr = 0; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nSize = 0; ++ } ++ else if(eNV21 == eRawFormat || eNV12 == eRawFormat) ++ { ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr = (unsigned int)pKmaFileIn->phys_addr; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize = width * height; ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr = (unsigned int)(pKmaFileIn->phys_addr + width * height); ++ pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nSize = nSize - width * height; ++ } ++ ++ tParam.nClkSelect = (unsigned short)eClkSelect; ++ JpeEncode(&tParam, _gpTestDev); ++ ++ // Step 3. generate hash for JPEG encoded data ++ memset(&tMd5State, sizeof(tMd5State), 0); ++ Md5Init(&tMd5State); ++ // omit the end of JFIF (0xFFD9) ++ Md5Append(&tMd5State, (const Md5Byte_t *)pJpeCfg->OutBuf.nAddr, (int)tParam.nEncodeSize - 2); ++ Md5Finish(&tMd5State, pDigest); ++ ++ if(tParam.nEncodeSize > pJpeCfg->OutBuf.nSize) ++ { ++ CamOsDebug("%sTask(%d) Error!!!! nEncodeSize(%d) > OutBufSize(%d). This should never happen!! \n", RED, nTaskId, (int)(tParam.nEncodeSize), pJpeCfg->OutBuf.nSize, NORMAL); ++ } ++ ++ if(_gpJpegBinHash[eRawFormat + 4 * nRes].size != tParam.nEncodeSize - 2) ++ { ++ CamOsDebug("%sTask(%d) Error!!!! Size(%d) mismatch with %d%s\n", RED, nTaskId, (int)(tParam.nEncodeSize - 2), _gpJpegBinHash[eRawFormat + 4 * nRes].size, NORMAL); ++ } ++ ++ if(0 != _CompareDigest(_gpJpegBinHash[eRawFormat + 4 * nRes].pDigest, pDigest)) ++ { ++ CamOsDebug("%sTask(%d) Error!!!! Digest(", RED, nTaskId); ++ _DumpDigest(pDigest); ++ CamOsDebug(") mismatch with %s%s\n", _gpJpegBinHash[eRawFormat + 4 * nRes].pDigest, NORMAL); ++ } ++ else ++ { ++ if(bDebugMsg) ++ { ++ CamOsDebug("Expected result size is %d\n", _gpJpegBinHash[eRawFormat + 4 * nRes].size); ++ CamOsDebug("Expected Hash is %s\n", _gpJpegBinHash[eRawFormat + 4 * nRes].pDigest); ++ CamOsDebug("Actual Hash is "); ++ _DumpDigest(pDigest); ++ CamOsDebug("\n"); ++ } ++ CamOsDebug("Encode done. Hash value for %dx%d check pass.\n\n", width, height); ++ ++ } ++ ++ _PatternRelease(pBo); ++ ++ if(_gTask1 == nTaskId) ++ { ++ _ReleaseInputBuffer_1(); ++ } ++ else ++ { ++ _ReleaseInputBuffer_2(); ++ } ++ return JPEG_TEST_SUCCESS; ++} ++ ++static int _DoTest(JPEG_TEST_FORMAT_e eRawFormat, int bDebugMsg, int nTaskId) ++{ ++ int nRet; ++ JPEG_TEST_CLOCK_e eClkSelect = eCLK_288; ++ JPEG_TEST_RESOLUTION_e eRes = eRESOLUTION_1088P; ++ ++ CamOsDebug("===="); ++ switch(eRawFormat) ++ { ++ case eNV12: ++ CamOsDebug(" Raw format: eNV12 "); ++ break; ++ case eNV21: ++ CamOsDebug(" Raw format: eNV21 "); ++ break; ++ case eYUYV: ++ CamOsDebug(" Raw format: eYUYV "); ++ break; ++ case eYVYU: ++ CamOsDebug(" Raw format: eYVYU "); ++ break; ++ } ++ CamOsDebug(" ====\n"); ++ ++ ++ for(eClkSelect = eCLK_288; eClkSelect <= eCLK_27; eClkSelect++) ++ { ++ switch(eClkSelect) ++ { ++ case eCLK_288: ++ CamOsDebug("%s Task:%d Clock: eCLK_288 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ case eCLK_216: ++ CamOsDebug("%s Task:%d Clock: eCLK_216 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ case eCLK_54: ++ CamOsDebug("%s Task:%d Clock: eCLK_54 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ case eCLK_27: ++ CamOsDebug("%s Task:%d Clock: eCLK_27 %s \n", BLUE, nTaskId, NORMAL); ++ break; ++ } ++ ++ for(eRes = eRESOLUTION_CIF; eRes <= eRESOLUTION_1088P; eRes++) ++ { ++ switch(eRes) ++ { ++ case eRESOLUTION_CIF: ++ CamOsDebug("%s Res: CIF %s \n", BLUE, NORMAL); ++ break; ++ case eRESOLUTION_VGA: ++ CamOsDebug("%s Res: VGA %s \n", BLUE, NORMAL); ++ break; ++ case eRESOLUTION_1088P: ++ CamOsDebug("%s Res: 1920x1088 %s \n", BLUE, NORMAL); ++ break; ++ case eRESOLUTION_1536P: ++ CamOsDebug("%s Res: 2688x1536 %s \n", BLUE, NORMAL); ++ break; ++ } ++ ++ nRet = _DoEncode(eClkSelect, eRes, eRawFormat, bDebugMsg, nTaskId); ++ if(JPEG_TEST_SUCCESS != nRet) ++ { ++ CamOsDebug("%s Error!!!! doEncode for resolution (%d) error!! %s\n", RED, eRes, NORMAL); ++ return eCLI_PARSE_INPUT_ERROR; ++ } ++ } ++ } ++ return eCLI_PARSE_OK; ++ ++} ++ ++ ++static int _TestJpeDbgMsg(CLI_t *pCli, char *p) ++{ ++ _gDbgMsgFlag = _gDbgMsgFlag ? 0 : 1; ++ return eCLI_PARSE_OK; ++} ++ ++static int _TestJpeYUYV(CLI_t *pCli, char *p) ++{ ++ _gpTestDev = JpeProbe(_gpTestDev); ++ _gTask1 = MsCurrTask(); ++ _DoTest(eYUYV, _gDbgMsgFlag, _gTask1); ++ JpeRemove(_gpTestDev); ++ return eCLI_PARSE_OK; ++} ++ ++static int _TestJpeYVYU(CLI_t *pCli, char *p) ++{ ++ _gpTestDev = JpeProbe(_gpTestDev); ++ _gTask1 = MsCurrTask(); ++ _DoTest(eYVYU, _gDbgMsgFlag, _gTask1); ++ JpeRemove(_gpTestDev); ++ return eCLI_PARSE_OK; ++} ++ ++static int _TestJpeNV12(CLI_t *pCli, char *p) ++{ ++ _gpTestDev = JpeProbe(_gpTestDev); ++ _gTask1 = MsCurrTask(); ++ _DoTest(eNV12, _gDbgMsgFlag, _gTask1); ++ JpeRemove(_gpTestDev); ++ return eCLI_PARSE_OK; ++} ++ ++static int _TestJpeNV21(CLI_t *pCli, char *p) ++{ ++ _gpTestDev = JpeProbe(_gpTestDev); ++ _gTask1 = MsCurrTask(); ++ _DoTest(eNV21, _gDbgMsgFlag, _gTask1); ++ JpeRemove(_gpTestDev); ++ return eCLI_PARSE_OK; ++} ++ ++static void _EmptyParser1(vm_msg_t *pMessage) ++{ ++ int i; ++ _gTask1 = MsCurrTask(); ++ for(i = 0; i < JPEG_TEST_COUNT; i++) ++ { ++ _DoTest(eYUYV, _gDbgMsgFlag, _gTask1); ++ } ++} ++ ++static void _EmptyParser2(vm_msg_t *pMessage) ++{ ++ int i; ++ _gTask2 = MsCurrTask(); ++ for(i = 0; i < JPEG_TEST_COUNT; i++) ++ { ++ _DoTest(eNV12, _gDbgMsgFlag, _gTask2); ++ } ++} ++ ++static void _EmptyInit(void *userdata) ++{ ++ CamOsDebug("%s %d\n", __FUNCTION__, __LINE__); ++} ++ ++static int _TestJpeMultiTask(CLI_t *pCli, char *p) ++{ ++ _gpTestDev = JpeProbe(_gpTestDev); ++ Msg_t *msg = NULL; ++ MsTaskId_e JpeTaskid[2]; ++ MsTaskCreateArgs_t JpeTaskArgs[2] = ++ { ++ {54, 0, NULL, _EmptyInit, _EmptyParser1, NULL, &JpeTaskid[0], NULL, FALSE, "task0", RTK_MS_TO_TICK(50), RTK_MS_TO_TICK(50)}, ++ {54, 0, NULL, _EmptyInit, _EmptyParser2, NULL, &JpeTaskid[1], NULL, FALSE, "task1", RTK_MS_TO_TICK(50), RTK_MS_TO_TICK(50)}, ++ }; ++ JpeTaskArgs[0].AppliInit = _EmptyInit; ++ JpeTaskArgs[0].pInitArgs = (void *)_gpTestDev; ++ JpeTaskArgs[0].AppliParser = _EmptyParser1; ++ JpeTaskArgs[0].StackSize = 4096; ++ JpeTaskArgs[0].pStackTop = (u32*)MsAllocateMem(JpeTaskArgs[0].StackSize); ++ strcpy(JpeTaskArgs[0].TaskName, "task0"); ++ ++ JpeTaskArgs[1].AppliInit = _EmptyInit; ++ JpeTaskArgs[1].pInitArgs = (void *)_gpTestDev; ++ JpeTaskArgs[1].AppliParser = _EmptyParser2; ++ JpeTaskArgs[1].StackSize = 4096; ++ JpeTaskArgs[1].pStackTop = (u32*)MsAllocateMem(JpeTaskArgs[0].StackSize); ++ strcpy(JpeTaskArgs[0].TaskName, "task1"); ++ ++ MsCreateTask(&JpeTaskArgs[0]); ++ MsStartTask(JpeTaskid[0]); ++ MsCreateTask(&JpeTaskArgs[1]); ++ MsStartTask(JpeTaskid[1]); ++ ++ CamOsDebug("%s JpeTaskid[0]=%d, JpeTaskid[1]=%d\n", BLUE, JpeTaskid[0], JpeTaskid[1], NORMAL); ++ ++ msg = (Msg_t*)MsAllocateMem(sizeof(Header_t)); ++ msg->Header.TypMsg = KERNEL_TEST_MSG0; ++ msg->Header.MbxSrc = CUS14_MBX; ++ msg->Header.MbxDst = JpeTaskid[0]; ++ msg->Header.Length = 0; ++ MsSend(JpeTaskid[0], msg); ++ ++ msg = (Msg_t*)MsAllocateMem(sizeof(Header_t)); ++ msg->Header.TypMsg = KERNEL_TEST_MSG1; ++ msg->Header.MbxSrc = CUS14_MBX; ++ msg->Header.MbxDst = JpeTaskid[1]; ++ msg->Header.Length = 0; ++ MsSend(JpeTaskid[1], msg); ++ ++ MsSleepExt(RTK_MS_TO_TICK(10 * JPEG_TEST_COUNT * 1000)); ++ ++ CamOsDebug("%s End of %s %s\n", BLUE, __func__, NORMAL); ++ JpeRemove(_gpTestDev); ++ ++ return eCLI_PARSE_OK; ++} ++ ++// g_atJPEMenuTbl will be used in isw_cli_main.c ++CliParseToken_t g_atJPEMenuTbl[] = ++{ ++ {"0", "trun on/off debug message", "", _TestJpeDbgMsg, NULL}, ++ {"1", "encode yuvu to jpeg (CIF, VGA, 1088P)", "", _TestJpeYUYV, NULL}, ++ {"2", "encode yvvu to jpeg (CIF, VGA, 1088P)", "", _TestJpeYVYU, NULL}, ++ {"3", "encode nv12 to jpeg (CIF, VGA, 1088P)", "", _TestJpeNV12, NULL}, ++ {"4", "encode nv21 to jpeg (CIF, VGA, 1088P)", "", _TestJpeNV21, NULL}, ++ {"5", "encode with 2 tasks", "", _TestJpeMultiTask, NULL}, ++ PARSE_TOKEN_DELIMITER ++}; +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/hal/jpe_hal.mak b/drivers/mstar/jpe2/hal/jpe_hal.mak +new file mode 100644 +index 00000000..7fc216a0 +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/jpe_hal.mak +@@ -0,0 +1,20 @@ ++#------------------------------------------------------------------------------- ++# Description of some variables owned by the library ++#------------------------------------------------------------------------------- ++# Library module (lib) or Binary module (bin) ++PROCESS = lib ++PATH_C +=\ ++ $(PATH_jpe_hal)/src ++ ++PATH_H +=\ ++ $(PATH_jpe_hal)/inc\ ++ $(PATH_jpe_hal)/pub\ ++ $(PATH_cam_os_wrapper)/pub\ ++ $(PATH_jpe)/pub ++ ++#------------------------------------------------------------------------------- ++# List of source files of the library or executable to generate ++#------------------------------------------------------------------------------- ++SRC_C_LIST =\ ++ hal_jpe_ios.c\ ++ hal_jpe_ops.c +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/hal/pub/hal_jpe_defs.h b/drivers/mstar/jpe2/hal/pub/hal_jpe_defs.h +new file mode 100644 +index 00000000..46327ae3 +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/pub/hal_jpe_defs.h +@@ -0,0 +1,142 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __HAL_JPE_DEF_H__ ++#define __HAL_JPE_DEF_H__ ++ ++ ++#if !defined(DEBUG_LEVEL) ++#define DEBUG_LEVEL 0 ++#endif ++ ++#define JPE_MSG_ERR 3 ++#define JPE_MSG_WARNING 4 ++#define JPE_MSG_DEBUG 5 ++#define JPE_MSG_LEVEL JPE_MSG_ERR //JPE_MSG_WARNING ++ ++#define JPE_MSG_ENABLE ++ ++#ifdef JPE_MSG_ENABLE ++#define JPE_MSG_FUNC_ENABLE ++#define JPE_STRINGIFY(x) #x ++#define JPE_TOSTRING(x) JPE_STRINGIFY(x) ++#ifdef JPE_MSG_FUNC_ENABLE ++#define JPE_MSG_TITLE "[JPE, %s] " ++#define JPE_MSG_FUNC __func__ ++#else ++#define JPE_MSG_TITLE "[JPE] %s" ++#define JPE_MSG_FUNC "" ++#endif ++ ++////////////////////////////////////// Define for Linux pletform /////////////////////////////// ++#if defined(__linux__) //#if defined(__linux__) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "cam_os_wrapper.h" ++//#include "mdrv_jpe.h" ++#define ms_dprintf JPE_MSG ++ ++//#define JPE_REGS_TRACE ++#define _REGW(base,idx) (*(((volatile u16*)(base))+2*(idx))) ++#if defined(JPE_REGS_TRACE) ++#define PRINT(s,idx,v,cmt) printk(#s":bank%d[%02x]=%04x %s\n",(idx&0x80)?1:0,idx&0x7F,v, cmt) ++#define REGW(base,idx,v,cmt) do{_REGW(base,idx)=(v);PRINT(w,idx,v,cmt);}while(0) ++#define REGR(base,idx,cmt) ({u16 v=_REGW(base,idx);PRINT(r,idx,v,cmt); v;}) ++#else ++#define REGW(base,idx,val,cmt) _REGW(base,idx)=(val) ++#define REGR(base,idx,cmt) _REGW(base,idx) ++#endif ++ ++ ++#define JPE_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= JPE_MSG_LEVEL) { \ ++ printk(KERN_SOH JPE_TOSTRING(dbglv) JPE_MSG_TITLE _fmt, JPE_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++////////////////////////////////////// Define for RTK platform /////////////////////////////// ++#elif defined(__I_SW__) ++#include ++#include ++#include // for memset ++#include "kernel.h" ++#include "vm_types.ht" ++#include "cam_os_wrapper.h" ++#include "sys_sys_isw_uart.h" ++#include "hal_drv_util.h" ++ ++#define _REGW(base,idx) (*(((volatile u16*)(base))+2*(idx))) ++#if defined(JPE_REGS_TRACE) ++#define PRINT(s,idx,v) UartSendTrace(#s":bank%d[%02x]=%04x\n",(idx&0x80)?1:0,idx&0x7F,v) ++#define REGW(base,idx,v,cmt) do{_REGW(base,idx)=(v);PRINT(w,idx,v,cmt);}while(0) ++#define REGR(base,idx,cmt) ({u16 v=_REGW(base,idx);PRINT(r,idx,v,cmt); v;}) ++#else ++#define REGW(base,idx,val,cmt) _REGW(base,idx)=(val) ++#define REGR(base,idx,cmt) _REGW(base,idx) ++#endif ++ ++#define Chip_Phys_to_MIU(addr) HalUtilPHY2MIUAddr((unsigned int)(addr)) ++ ++#define JPE_MSG(dbglv, _fmt, _args...) \ ++ do if(dbglv <= JPE_MSG_LEVEL) { \ ++ UartSendTrace(JPE_TOSTRING(dbglv) JPE_MSG_TITLE _fmt, JPE_MSG_FUNC, ## _args); \ ++ } while(0) ++ ++#else ++ ++#define JPE_MSG(dbglv, _fmt, _args...) ++ ++#endif ++#endif //#if defined(__linux__) ++ ++ ++typedef enum ++{ ++ JPE_DEV_INIT = 0, ++ JPE_DEV_BUSY, ++ JPE_DEV_ENC_DONE, ++ JPE_DEV_OUTBUF_FULL, ++ JPE_DEV_INBUF_FULL ++} JpeDevStatus_e; ++ ++typedef enum ++{ ++ JPE_IOC_RET_SUCCESS = 0, ++ JPE_IOC_RET_BAD_QTABLE = 1, ++ JPE_IOC_RET_BAD_QP = 2, ++ JPE_IOC_RET_BAD_BITSOFFSET = 3, ++ JPE_IOC_RET_BAD_BANKNUM = 4, ++ JPE_IOC_RET_BAD_INBUF = 5, ++ JPE_IOC_RET_BAD_OUTBUF = 6, ++ JPE_IOC_RET_BAD_NULLPTR = 7, ++ JPE_IOC_RET_BAD_BANKCNT = 8, ++ JPE_IOC_RET_BAD_LASTZZ = 9, ++ JPE_IOC_RET_UNKOWN_COMMAND = 10, ++ JPE_IOC_RET_BAD_VIRTUAL_MEM = 11, ++ JPE_IOC_RET_NEED_DRIVER_INIT = 12, ++ JPE_IOC_RET_FMT_NOT_SUPPORT = 13, ++ JPE_IOC_RET_HW_IS_RUNNING = 14, ++ JPE_IOC_RET_FAIL = 15 ++} JPE_IOC_RET_STATUS_e; ++ ++ ++#endif // __HAL_JPE_DEF_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/hal/pub/hal_jpe_ios.h b/drivers/mstar/jpe2/hal/pub/hal_jpe_ios.h +new file mode 100644 +index 00000000..a272f10e +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/pub/hal_jpe_ios.h +@@ -0,0 +1,1038 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __HAL_JPE_IOS_H__ ++#define __HAL_JPE_IOS_H__ ++ ++#include "hal_jpe_defs.h" ++ ++#define REG_CKG_BASE 0x1F207000 ++#define REG_CKG_JPE_BASE (REG_CKG_BASE+0x6A*4) ++ ++typedef struct JpeJob_t ++{ ++ u32 i_code; ++ u32 i_tick; ++ u32 i_bits; ++} JpeJob_t; ++ ++#define ADD_JPDE_0_1 //support HW multi-obuf mode ++#define ADD_JPDE_1_1 //support Jpeg YUV420 encode mode ++#define JPE_MIAW 27//25//24 ++#define ADDR_HI_BITS ((JPE_MIAW-6)-16) ++#define OUTBUF_HI_BITS (JPE_MIAW-16) ++#define ADDR_MASK (0xffffffff>>(32-(JPE_MIAW-6))) ++#define DMA_BOUND 27 ++#define DMA_HI_BITS (DMA_BOUND-16) ++#define LAST_FRAME_AVGQP_HI_BITS (24-16) ++#define BITCOUNT_HI_BITS (23-16) ++ ++typedef struct ++{ ++ JpeJob_t mjob; ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGFrameStartSw: 1; // frame start (1T clk_mfe) (write one clear) ++ u16 nRegJpeGSoftRstz: 1; // software reset; 0/1: reset/not reset ++ u16 nRegJpeGEncMode: 1; // 0/1: JPEG/H263 ++#if defined(ADD_JPDE_1_1) ++ u16 nRegJpeGEncFormat: 1; // 0/1: YUV420/YUV422 ++ u16 nRegJpeGFrameIdx: 2; ++ u16 nReg0000Dummy: 2; ++#else ++ u16 nReg0000Dummy: 5; ++#endif ++ u16 nRegJpeGQscale: 5; // frame level qscale: [H263]: 1 ~ 31 ++ u16 nRegJpeGMreq: 1; // mreq_jpe; miu clock gating enable ++ u16 nRegJpeGDctOnlyEn: 1; // 0: normal function, 1: DCT only to accelerate SW encoding ++ u16 nRegJpeGMode: 1; //0/1: JPE/JPD ++ } tReg00; ++ u16 nReg00; ++ } uReg00; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGPicWidth: 12; // picture width ++ } tReg01; ++ u16 nReg01; ++ } uReg01; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGPicHeight: 12; // picture height ++ } tReg02; ++ u16 nReg02; ++ } uReg02; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegMfeGErModeDummy: 2; ++ u16 nRegMfeGErMbyDummy: 2; ++ u16 nRegMfeGPackedModeDummy: 1; ++ u16 nRegMfeGQmodeDummy: 1; ++ u16 nRegJpeGTbcMode: 1; // table mode; 0: SW control, 1: HW control ++ u16 nRegMfeGFldpicEnDummy: 1; ++ } tReg03; ++ u16 nReg03; ++ } uReg03; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr0Low: 16; ++ } tReg06; ++ u16 nReg06; ++ } uReg06; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr0High: ADDR_HI_BITS; // Y buffer base address0 ++ } tReg07; ++ u16 nReg07; ++ } uReg07; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr1Low: 16; // Y buffer base address1 ++ } tReg08; ++ u16 nReg08; ++ } uReg08; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufYAdr1High: ADDR_HI_BITS; // Y buffer base address1 ++ }tReg09; ++ u16 nReg09; ++ } uReg09; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr0Low: 16; // C buffer base address0 ++ } tReg0a; ++ u16 nReg0a; ++ } uReg0a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr0High: ADDR_HI_BITS; // C buffer base address0 ++ } tReg0b; ++ u16 nReg0b; ++ } uReg0b; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr1Low: 16; // C buffer base address1 ++ } tReg0c; ++ u16 nReg0c; ++ } uReg0c; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBufCAdr1High: ADDR_HI_BITS; // C buffer base address1 ++ } tReg0d; ++ u16 nReg0d; ++ } uReg0d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGFsvsWptr: 8; //fsvs to jpe write pointer ++ } tReg0f; ++ u16 nReg0f; ++ } uReg0f; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGRowDownCnt: 8; //row_done counter in clk_jpe domain ++ } tReg10; ++ u16 nReg10; ++ } uReg10; ++ ++ union ++ { ++ struct ++ { ++ // clock gating ++ //[0]: clock gating: clk_jpe (used by JPE); 0: clk_jpe enable, 1: clk_jpe disable ++ //[1]: clock gating: clk_jpd (used by JPD); 0: clk_jpd enable, 1: clk_jpd disable ++ //[2]: clock gating: clk_miu0 (used by JPE); 0: clk_miu0 enable, 1: clk_miu0 disable ++ //[3]: clock gating: clk_miu1 (used by JPD); 0: clk_miu1 enable, 1: clk_miu1 disable ++ //[4]: clock gating: clk_viu (used by JPE); 0: clk_viu enable, 1: clk_viu disable" ++ u16 nRegJpeGClkGateEn: 5; //0x0a : gating jpd, 0x15 : gating jpe ++ } tReg16; ++ u16 nReg16; ++ } uReg16; ++ ++ // [JPEG] ++ union ++ { ++ struct ++ { ++ u16 nRegMfeGJpeEncModeDummy: 2; ++ u16 nRegJpeGJpeBuffermode: 1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode ++ u16 nRegJpeSAutoRstWaitCnt: 6; // the waiting count for regen_soft_rstz and regen_fs_sw generation ++ u16 nRegJpeGJpeFsvsMode: 2; // JPE fsvs generation mode; 0/1/2/3: pure sw/sw+hw/hw wo auto-restart/hw with auto-restart, but fsvs function is removed... ++ u16 nReg18Dummy: 4; ++ u16 nRegJpeGViuSoftRstz: 1; //viu software reset; 0/1: reset/not reset ++ } tReg18; ++ u16 nReg18; ++ } uReg18; ++ ++ ++ // [IRQ & important IP status checkings] ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqMask: 8; // 0/1: irq not-mask/mask ++ } tReg1c; ++ u16 nReg1c; ++ } uReg1c; ++ ++ union ++ { ++ struct ++ { ++#if 0 ++ u16 nRegJpeGIrqClr0: 1; // 0/1: not clear interrupt/clear interrupt 0 (write one clear) ++ u16 nRegJpeGIrqClr1: 1; // 0/1: not clear interrupt/clear interrupt 1 (write one clear) ++ u16 nRegJpeGIrqClr2: 1; // 0/1: not clear interrupt/clear interrupt 2 (write one clear) ++ u16 nRegJpeGIrqClr3: 1; // 0/1: not clear interrupt/clear interrupt 3 (write one clear) ++ u16 nRegJpeGIrqClr4: 1; // 0/1: not clear interrupt/clear interrupt 4 (write one clear) ++ u16 nRegJpeGIrqClr5: 1; // 0/1: not clear interrupt/clear interrupt 5 (write one clear) ++ u16 nRegJpeGIrqClr6: 1; // 0/1: not clear interrupt/clear interrupt 6 (write one clear) ++ u16 nRegJpeGIrqClr7: 1; // 0/1: not clear interrupt/clear interrupt 7 (write one clear) ++ u16 nRegJpeGIrqClr8: 1; // 0/1: not clear interrupt/clear interrupt 8 (write one clear) ++#else ++ u16 nRegJpeGIrqClr: 9; // bitwise 0/1: not clear interrupt/clear interrupt 8 (write one clear) ++#endif ++ u16 nRegJpeGSwrstSafe: 1; // to indicate there're no miu activities that need to pay attention to ++ u16 nRegJpeGLastDoneZ: 1; // to indicate all miu data has been written ++ } tReg1d; ++ u16 nReg1d; ++ } uReg1d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqCpu: 8; // status of interrupt on CPU side ({1'b0, netrigger, fs_fail_irq, txipime_out, bspobuf_full_irq, img_buf_full_irq, marb_bspobuf_ful, frame_done_irq}) ++ } tReg1e; ++ u16 nReg1e; ++ } uReg1e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqIp: 8; // status of interrupt on IP side ({1'b0, netrigger, fs_fail_irq, txipime_out, bspobuf_full_irq, img_buf_full_irq, marb_bspobuf_ful, frame_done_irq}) ++ } tReg1f; ++ u16 nReg1f; ++ } uReg1f; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGIrqForce: 8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt ++ } tReg20; ++ u16 nReg20; ++ } uReg20; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGSramSdEn: 3; //SRAM SD enable ++ } tReg21; ++ u16 nReg21; ++ } uReg21; ++ ++ // [TXIP PIPELINE ] ++ // QUAN ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSQuanIdxLast: 6; //the index of the last non-zero coefficient in the zig-zag order ++ u16 nRegJpeSQuanIdxSwlast: 1; //software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable ++ } tReg2c; ++ u16 nReg2c; ++ } uReg2c; ++ ++ // TXIP control & debug ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipMbx: 9; //txip mbx ++ u16 nRegJpeSTxipSngMb: 1; //0/1: disable/enable txip controller stop-and-go mechanism using (txip_mbx == reg_mfe_g_debugrig_mbx) & (txip_mby == reg_mfe_g_debugrig_mby) ++ u16 nRegJpeSTxipSngSet: 1; //txip controller stop-and-go mechanism using this register bit: 0/1: go/stop ++ u16 nRegJpeSTxipDbfFullHaltEn: 1; //txip controller stop-and-go mechanism using double buffer fullness as criterion; 0/1: disable/enable ++ } tReg2d; ++ u16 nReg2d; ++ } uReg2d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipMby: 9; // txip mby ++ } tReg2e; ++ u16 nReg2e; ++ } uReg2e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegMfeSTxipIrfshMbE1Dummy: 11; ++ u16 nRegJpeSTxipTimeoutEn: 1; // txip time out enable ++ u16 nRegJpeSTxipWaitMode: 1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count ++ } tReg32; ++ u16 nReg32; ++ } uReg32; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipIdlecnt: 16; //wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) ++ } tReg33; ++ u16 nReg33; ++ } uReg33; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTxipTimeout: 16; // txip timeout count (x 64T) ++ } tReg34; ++ u16 nReg34; ++ } uReg34; ++ ++ // [ECDB PIPELINE] ++ // ECDB control & debug ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSEcdbMbx: 9; // ecdb mbx ++ } tReg35; ++ u16 nReg35; ++ } uReg35; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSEcdbMby: 9; // ecdb mby ++ } tReg36; ++ u16 nReg36; ++ } uReg36; ++ ++ // BSP/BSPOBUF ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufSetAdr: 1; // set bsp obuf start address(write one clear) ++ u16 nRegJpeSBspFdcOffset: 5; // bsp's fdc offset ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeObuffullIrqAtFrameEnd: 1; // [JPDE_0_1] keep obuf full irq at frame end ++ u16 nRegJpeObufToggleObuf0Status: 1; // [JPDE_0_1] toggle buf0 status(write one clear) ++ u16 nRegJpeObufToggleObuf1Status: 1; // [JPDE_0_1] toggle buf1 status(write one clear) ++ u16 nRegJpeObufHwEn: 1; // [JPDE_0_1] enable HW obuf automatic mechanism ++ u16 nRegJpeObufUpdateAdr: 1; // [JPDE_0_1] update obuf address(write one clear) ++ u16 nRegJpeObufAdrRchkSe1: 2; // [JPDE_0_1] obuf adr read back check selection: 0/1/2/3: s0/e0/s1/e1 ++ u16 nRegJpeObufAdrRchkEn: 1; // [JPDE_0_1] enable bspobuf adr read back check through reg_jpe_s_bspobuf_wptr ++#endif ++ } tReg3b; ++ u16 nReg3b; ++ } uReg3b; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeSBspobufAdrLow: 16; // bsp obuf start address (4 byte unit) ++#else ++ u16 nRegJpeSBspobufSadrLow: 16; // bsp obuf start address (4 byte unit) ++#endif ++ } tReg3c; ++ u16 nReg3c; ++ } uReg3c; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeSBspobufAdrHigh: OUTBUF_HI_BITS; // bsp obuf start address (4 byte unit) ++ u16 nRegJpeSBspobufDummyBit: (16 - OUTBUF_HI_BITS - 2); ++ u16 nRegJpeSBspobufId:2; ++#else ++ u16 nRegJpeSBspobufSadrHigh: OUTBUF_HI_BITS; // bsp obuf start address (4 byte unit) ++#endif ++ } tReg3d; ++ u16 nReg3d; ++ } uReg3d; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nRegJpeSBspspobufWriteIdAdr: 1; // [JPDE_0_1] write to this address to enable writing of bspobuf address ++#else ++ u16 nRegJpeSBspobufEadrLow: 16; // bsp obuf end address (4 byte unit) ++#endif ++ } tReg3e; ++ u16 nReg3e; ++ } uReg3e; ++ ++ union ++ { ++ struct ++ { ++#ifdef ADD_JPDE_0_1 ++ u16 nReg3fReserved; ++#else ++ u16 nRegJpeSBspobufEadrHigh:OUTBUF_HI_BITS; // bsp obuf end address (4 byte unit) ++#endif ++ } tReg3f; ++ u16 nReg3f; ++ } uReg3f; ++ ++ union ++ { ++ struct ++ { ++ ++ u16 nRegJpeSBspByteIdx: 2; // last encoded byte index in 4-byte MIU ++#ifdef ADD_JPDE_0_1 ++#if 0 // Old one and not the same as spec ++ u16 nRegJpeObufIdx: 2; // HW obuf index(0->1->2->3->0->1¡K) ++ // SW obuf index(00->01->11->10->00...) ++ u16 nRegJpeObuf0Status: 1; ++ u16 nRegJpeObuf1Status: 1; ++ // reg_jpe_s_obuf_adr_status:6 {fifo_not_full, fifo_not_empty, enable_obufadr_update, obufadr_update_cnt[2:0]} ++ u16 nRegJpeObufAdrUpdateCnt: 3; ++ u16 nRegJpeEnableObufAdrUpdate: 1; ++ u16 nRegJpeFifoNotEmpty: 1; ++ u16 nRegJpeFifoNotFull: 1; ++#else ++ u16 nRegJpeSObufIdx: 2; // HW obuf index(0->1->2->3->0->1¡K) ++ u16 nRegJpeSObufSwIdx: 2; // SW obuf index(00->01->11->10->00...) ++ u16 RegJpeSObufAdrStatus: 6; // {fifo_not_full, fifo_not_empty, enable_obufadr_update, obufadr_update_cnt[2:0]} ++#endif ++#endif ++ } tReg42; ++ u16 nReg42; ++ } uReg42; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufWptrLow: 16; // bspobuf write pointer (4 byte unit) ++ } tReg44; ++ u16 nReg44; ++ } uReg44; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufWptrHigh:OUTBUF_HI_BITS; // bspobuf write pointer (4 byte unit) ++ } tReg45; ++ u16 nReg45; ++ } uReg45; ++ ++ // [Table Control] ++ union ++ { ++ struct ++ { ++ u16 nRegMfeSFdcAckDummy: 1; ++ u16 nRegMfeSFdcDoneClrDummy: 1; ++ u16 nRegMfeSFdcDoneDummy: 1; ++ u16 nReg48Dummy: 8; ++ u16 nRegMfeSFdcBsVldDummy: 1; ++ u16 nRegJpeSTbcEn: 1; // set for table read & write ; 1: enable, 0: disable (write one clear) ++ } tReg48; ++ u16 nReg48; ++ } uReg48; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTbcRw: 1; // table mode; 0: read, 1: write ++ u16 nRegJpeSTbcDoneClr: 1; // table done clear (write one clear) ++ u16 nRegJpeSTbcDone: 1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg_mfe_sbc_rdata ++ u16 nReg49Dummy: 5; ++ u16 nRegJpeSTbcAdr: 8; // table address ++ ++ } tReg49; ++ u16 nReg49; ++ } uReg49; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTbcWdata: 8; // table write data ++ } tReg4a; ++ u16 nReg4a; ++ } uReg4a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSTbcRdata: 8; // table read data ++ } tReg4b; ++ u16 nReg4b; ++ } uReg4b; ++ ++ // [Miu Arbiter] ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrBurstThd: 5; //miu read burst bunch up threshold ++ u16 nRegJpeSDmaMrTimeout: 3; //miu read burst timeout ++ u16 nRegJpeSDmaMwBurstThd: 5; //miu write burst bunch up threshold ++ u16 nRegJpeSDmaMwTimeout: 3; //miu write burst timeout ++ } tReg54; ++ u16 nReg54; ++ } uReg54; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrpriorityThd: 7; //hardware mfe2mi_rpriority threshold ++ u16 nRegJpeSDmaMrpriorityType: 1; //hardware mfe2mi_rpriority threshold ++ u16 nRegJpeSDmaMwpriorityThd: 7; //hardware mfe2mi_wpriority threshold ++ u16 nRegJpeSDmaMwpriorityType: 1; ++ } tReg55; ++ u16 nReg55; ++ } uReg55; ++ ++ union ++ { ++ struct ++ { ++ u16 reg_jpe_s_dma_mrpriority_sw: 2; //mfe2mi_rpriority software programmable ++ u16 reg5600_dummy: 1; ++ u16 reg_jpe_s_dma_mr_nwait_mw: 1; //miu read not wait mi2mfe_wrdy ++ u16 reg_jpe_s_dma_mwpriority_sw: 2; //mfe2mi_wpriority software programmable ++ u16 reg5601_dummy: 1; ++ u16 reg_jpe_s_dma_mw_nwait_mr: 1; //miu read not wait mi2mfe_wrdy ++ u16 reg_jpe_s_dma_mr_pending: 4; //miu read not wait mi2mfe_wrdy ++ u16 reg_jpe_s_dma_32b_ad_nswap: 1; //32bits miu address not swap. only for 32bits mode ++ u16 reg_jpe_s_dma_miu_wmode: 1; //0/1: original miu protocol/new miu protocol(wd_en) ++ } tReg56; ++ u16 nReg56; ++ } uReg56; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrlastThd: 5; //auto mfe2mi_rlast threshold ++ u16 nRegJpeSDmaMwlastThd: 5; //auto mfe2mi_wlast threshold ++ u16 nReg5700Dummy: 2; ++ u16 nRegJpeSDmaBurstSplit: 4; //0: disable; N: MIU Request IDLE ¡§N¡¨ cycles with every last signal ++ } tReg57; ++ u16 nReg57; ++ } uReg57; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaUbound0Low: 16; //miu write protection, miu upper bound 0 (BSP obuf) ++ } tReg58; ++ u16 nReg58; ++ } uReg58; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaUbound0High:DMA_HI_BITS; //miu write protection, miu upper bound 0 (BSP obuf) ++ } tReg59; ++ u16 nReg59; ++ } uReg59; ++ ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaLbound0Low: 16; // miu write protection, miu lower bound 0 ++ } tReg5a; ++ u16 nReg5a; ++ } uReg5a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaLbound0High: DMA_HI_BITS; // miu write protection, miu lower bound 0 ++ u16 nReg5bDummy:((16 - DMA_HI_BITS) - 2); // miu write protection, miu lower bound 0 ++ u16 nRegJpeSDmaMiuOff: 1; //miu write protection, miu off ++ u16 nRegJpeSDmaMiuBoundErr: 1; ++ } tReg5b; ++ u16 nReg5b; ++ } uReg5b; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMrRdffPriorThd: 4; // 4¡¦hx: high priority when rdff depth < {xxx,2¡¦b00} ++ u16 nRegJpeSDmaMrRdffPriorMask: 4; //Read data fifo depth priority initial mask, 0:disable, 1:release the mask after 8 requests ++ u16 nRegJpeSDmaMlastStallOld: 1; //jpde2mi Last in stall state 0:Guarantee jpde2mi Last, 1:No jpde2mi Last in Stall State ++ u16 nRegJpeSDmaRsv5c: 7; //reserved registers ++ } tReg5c; ++ u16 nReg5c; ++ } uReg5c; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSDmaMreqAlwaysActive: 1; //0:dynamic mreq, 1:always set mreq = 1 ++ u16 nRegJpeSDmaMreqModeSel: 1; //mreq mode selection 0:clk_miu enabled dynamically, 1:clk_miu enabled from Enstart -> Frame_done ++ u16 nRegJpeSDmaMiuBoundEn: 4; //miu write protection, miu bound enable for write port 0 ~ 3 ++ } tReg5d; ++ u16 nReg5d; ++ } uReg5d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegGJpeYPitch: 8; // Y frame buffer pitch ++ u16 nRegGJpeCPitch: 8; // C frame buffer pitch ++ } tReg5e; ++ u16 nReg5e; ++ } uReg5e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegSJpeYuvldrRlastThd: 4; // YUV loader MIU burst read interval ++ u16 nRegSJpeYuvldrMrprioritySw: 2; // YUV loader MIU read priority SW programmable ++ u16 nRegSJpeYuvldrMrpriorityThd: 7; // YUV loader MIU read priority setting threshold ++ u16 nRegSJpeYuvldrMrpriorityType: 1; // YUV loader MIU read priority type ++ u16 nRegSJpeYuvldrImiEn: 1; // YUV loader IMI enable ++ u16 nRegSJpeYuvldrCWwap: 1; // YUV loader Chroma swap ++ } tReg5f; ++ u16 nReg5f; ++ } uReg5f; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSBspobufWlastThd: 4; // BSP obuf MIU burst write interval ++ u16 nRegJpeSBspobufMwpriorityWw: 2; // BSP obuf MIU write priority SW programmable ++ u16 nRegJpeSBspobufMwpriorityThd: 7; // BSP obuf MIU write priority setting threshold ++ u16 nRegJpeSBspobufMwpriorityType: 1; // BSP obuf MIU write priority type ++ } tReg60; ++ u16 nReg60; ++ } uReg60; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeSYuvldrImiBound: 9; // YUV loader IMI bound (unit: Macro) ++ } tReg61; ++ u16 nReg61; ++ } uReg61; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeTlb: 1; // YUV loader IMI bound (unit: Macro) ++ } tReg64; ++ u16 nReg64; ++ } uReg64; ++ ++ // [Debug] ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGPatGenInit: 16; // pattern generation initial value ++ } tReg6f; ++ u16 nReg6f; ++ } uReg6f; ++ ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugMode: 5; // debug mode ++ u16 nRegJpeGPatGenEn: 1; //enable pattern generation ++ u16 nRegJpeGDebugTrigCycle: 10; // wait (8 * reg_mfe_g_debugrig_cycle) cycles ++ ++ } tReg70; ++ u16 nReg70; ++ } uReg70; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugTrigMbx: 9; // debug trigger mbx ++ } tReg71; ++ u16 nReg71; ++ } uReg71; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugTrigMby: 9; // debug trigger mby ++ } tReg72; ++ u16 nReg72; ++ } uReg72; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugTrig: 1; // reg trigger (write one clear) ++ u16 nRegJpeGDebugTrigMode: 2; // debug trigger mode; 0/1/2/3: regrigger/3rd stage (mbx, mby)/frame start ++ u16 nRegJpeGDebugEn: 1; // debug enable ++ u16 nRegJpeGCrcMode: 4; //'h0: Disable,¡¥hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf ++ u16 nRegJpeGDebugTcycleChkEn: 1; //enable total cycle check ++ u16 nRegJpeGDebugTcycleChkSel: 1; //select total cycle and report it on reg_mfe_g_crc_result[15:0] ++ u16 nRegJpeGRowDownIrqEn: 1; //row done irq enable; 0: disable, 1: enable ++ u16 nRegJpeGVsIrqEn: 1; //vs irq enable; 0: disable, 1: enable ++ } tReg73; ++ u16 nReg73; ++ } uReg73; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugState0: 16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, ++ } tReg74; ++ u16 nReg74; ++ } uReg74; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGSwBufferMode: 1; //0/1: hw/sw buffer mode, but not work anymore... ++ u16 nRegJpeGSwRowDone: 1; //sw row done (1T clk_jpe) (write one clear) ++ u16 nRegJpeGSwVsync: 1; //sw vsync (1T clk_jpe) (write one clear), but not work anymore... ++ } tReg75; ++ u16 nReg75; ++ } uReg75; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult0: 16; // CRC64[15..0] ++ } tReg76; ++ u16 nReg76; ++ } uReg76; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult1: 16; // CRC64[31..16] ++ } tReg77; ++ u16 nReg77; ++ } uReg77; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult2: 16; // CRC64[47..32] ++ } tReg78; ++ u16 nReg78; ++ } uReg78; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGCrcResult3: 16; // CRC64[63..48] ++ } tReg79; ++ u16 nReg79; ++ } uReg79; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGBistFail0: 16; ++ } tReg7a; ++ u16 nReg7a; ++ } uReg7a; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugOutLow: 16; ++ } tReg7b; ++ u16 nReg7b; ++ } uReg7b; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeGDebugOutHigh: ++ (21 - 16); ++ } tReg7c; ++ u16 nReg7c; ++ } uReg7c; ++ ++ //Reserved ++ union ++ { ++ struct ++ { ++ u16 nRegJpeRsv0: 16; //reserved registers ++ } tReg7d; ++ u16 nReg7d; ++ } uReg7d; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeRsv1: 16; //reserved registers ++ } tReg7e; ++ u16 nReg7e; ++ } uReg7e; ++ ++ union ++ { ++ struct ++ { ++ u16 nRegJpeRsv2: 16; //reserved registers ++ } tReg7f; ++ u16 nReg7f; ++ } uReg7f; ++ ++ union ++ { ++ struct ++ { ++ u16 regClk_jpe_clock_setting: 2; ++ u16 regClk_clock_source: 3; ++ }; ++ u16 regClk; ++ }; ++} JpeReg_t; ++ ++ ++typedef enum ++{ ++ JPE_HAL_QLEVEL_1 = 0, ++ JPE_HAL_QLEVEL_2, ++ JPE_HAL_QLEVEL_3, ++ JPE_HAL_QLEVEL_4, ++ JPE_HAL_QLEVEL_5, ++ JPE_HAL_QLEVEL_6, ++} JpeHalQLevel_e; ++ ++typedef enum ++{ ++ JPE_HAL_IRQ_FRAME_DONE = 0x00000001, // bit 0, jpe_framedone ++ JPE_HAL_IRQ_BSPOBUF0_FULL = 0x00000002, // bit 1, jpe_bspobuf0_full, SW mode: buf full; HW mode: buf0 full ++ JPE_HAL_IRQ_IMGBUF_FULL = 0x00000004, // bit 2, img_buf_full_irq ++ JPE_HAL_IRQ_BSPOBUF1_FULL = 0x00000008, // bit 3, jpe_bspobuf1_full, SW mode: not used; HW mode: buf1 full ++ JPE_HAL_IRQ_FS_FAIL = 0x00000020, // bit 5, fs_fail_irq ++ JPE_HAL_IRQ_LESS_ROW_DONE = 0x00000080, // bit 7, less_row_down_irq ++ JPE_HAL_IRQ_IMI_OVERFLOW = 0x00000100, // bit 8, jpe2scl_imi_overflow_int ++ JPE_HAL_IRQ_TXIP_TIMEOUT = 0x10000000, // bit 4 when reg_jpe_g_vs_irq_en = 0, txip_time_out_irq ++ JPE_HAL_IRQ_VS = 0x20000000, // bit 4 when reg_jpe_g_vs_irq_en = 1, vs ++ JPE_HAL_IRQ_NET_TRIGGER = 0x40000000, // bit 4 when reg_jpe_g_row_down_irq_en = 0, net_trigger ++ JPE_HAL_IRQ_VIU_ROW_DONE = 0x80000000, // bit 6 when reg_jpe_g_row_down_irq_en = 1, viu2jpe_row_done_jpe ++ JPE_HAL_IRQ_ALL = 0xF00001AF // ALL bits ++} JpeHalIrqEvent_e; ++ ++typedef enum ++{ ++ JPE_OBUF_0 = 0, ++ JPE_OBUF_1 = 1, ++} JpeHalOBufOdr_e; ++ ++typedef enum ++{ ++ JPE_FSVS_SW_MODE = 0, ++ JPE_FSVS_SW_HW_MODE, ++ JPE_FSVS_HW_MODE, ++ JPE_FSVS_HW_WO_RESTART_MODE, ++ JPE_FSVS_HW_WI_RESTART_MODE, ++ JPE_FSVS_INVALID, ++} JpeFsVsGenerationMode_e; ++ ++typedef enum ++{ ++ JPE_HAL_OBUF_SINGLE_MODE = 0x0, ++ JPE_HAL_OBUF_MULTI_MODE = 0x1 ++} JpeHalOutBufMode_e; ++ ++typedef enum ++{ ++ JPE_HAL_BUFFER_ROW_MODE = 0x0, ++ JPE_HAL_BUFFER_FRAME_MODE = 0x1 ++} JpeHalInBufMode_e; ++ ++typedef enum ++{ ++ JPE_HAL_CODEC_JPEG = 0x1, ++ JPE_HAL_CODEC_H263I = 0x2, ++ JPE_HAL_CODEC_ENCODE_DCT = 0x4, ++} JpeHalCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_HAL_SCL_HANDSHAKE_OFF = 0, ++ JPE_HAL_SCL_HANDSHAKE_ON ++} JpeHalSclHandShake_e; ++ ++typedef enum ++{ ++ JPE_HAL_RAW_YUYV = 0x0, ++ JPE_HAL_RAW_YVYU = 0x1, ++ JPE_HAL_RAW_NV12 = 0x3, ++ JPE_HAL_RAW_NV21 = 0x4, ++} JpeHalRawFormat_e; ++ ++typedef struct ++{ ++ u32 nInBufYAddr[2]; ++ u32 nInBufCAddr[2]; ++} JpeHalInBufCfg_t, *pJpeHalInBufCfg; ++ ++ ++typedef struct ++{ ++ u32 nOutBufAddr[2]; ++ u32 nOutBufSize[2]; ++ u32 nJpeOutBitOffset; ++} JpeHalOutBufCfg_t, *pJpeHalOutBufCfg; ++ ++typedef struct ++{ ++ u32 nBaseAddr; ++ u32 nSize; ++ JpeReg_t tJpeReg; ++ ++ // Jpeg configuration ++ int nInBufMode; ++ int nRawFormat; ++ int nCodecFormat; ++ ++ u32 nWidth; ++ u32 nHeight; ++ ++ u16 YQTable[64]; ++ u16 CQTable[64]; ++ u16 nQScale; ++ ++ JpeHalInBufCfg_t tJpeHalInBufCfg; ++ JpeHalOutBufCfg_t tJpeHalOutBufCfg; ++} JpeHalHandle_t; ++ ++ ++typedef struct JpeRegIndex_t ++{ ++ int i_id; ++ void* base; ++ int size; ++} JpeRegIndex_t; ++ ++typedef struct JpeIosCB_t ++{ ++ void (*release)(void*); //! release this object. ++ JPE_IOC_RET_STATUS_e(*setBank)(void*, JpeRegIndex_t*); //! assign register base pointer. ++ JPE_IOC_RET_STATUS_e(*encFire)(void*, void*, JpeJob_t*); //! process and trigger encoder job. ++ JPE_IOC_RET_STATUS_e(*isrFunc)(void*, int); //! interrupt service routine. ++ JPE_IOC_RET_STATUS_e(*irqMask)(void*, int); //! masking irq. ++} JpeIosCB_t; ++ ++typedef struct JpeIos_t ++{ ++ JpeIosCB_t mios; ++ ++ // Configuration used for encode ++ u32 nBaseAddr; ++ u16 YQTable[64]; ++ u16 CQTable[64]; ++ JpeReg_t tJpeReg; ++ JpeHalInBufCfg_t tJpeHalInBufCfg; ++ JpeHalOutBufCfg_t tJpeHalOutBufCfg; ++ ++ // Result after encode ++ JpeDevStatus_e eJpeDevStatus; ++ u32 nEncodeSize; ++} JpeIos_t; ++ ++extern JpeIosCB_t* JpeIosAcquire(char* pTags); ++#endif // __HAL_JPE_IOS_H__ +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/hal/pub/hal_jpe_ops.h b/drivers/mstar/jpe2/hal/pub/hal_jpe_ops.h +new file mode 100644 +index 00000000..98ef6067 +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/pub/hal_jpe_ops.h +@@ -0,0 +1,162 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __HAL_JPE_OPS_H__ ++#define __HAL_JPE_OPS_H__ ++ ++#include "hal_jpe_defs.h" ++ ++#if defined(__linux__) //#if defined(__linux__) ++#define JPE_DEV_STATE_NULL -1 ++#define JPE_DEV_STATE_IDLE 0 ++#define JPE_DEV_STATE_BUSY 1 ++#else ++#define JPE_DEV_STATE_NULL -1 ++#define JPE_DEV_STATE_IDLE 1 // 0 ++#define JPE_DEV_STATE_BUSY 0 // 1 ++#endif ++ ++#define JPE_CTX_STATE_NULL -1 ++#define JPE_CTX_STATE_IDLE 0 ++#define JPE_CTX_STATE_BUSY 1 ++ ++#define JPE_USER_DATA_SIZE (4*1024) ++ ++typedef enum ++{ ++ JPE_IBUF_ROW_MODE = 0x0, ++ JPE_IBUF_FRAME_MODE = 0x1 ++} JpeInBufMode_e; ++ ++typedef enum ++{ ++ JPE_COLOR_PLAN_LUMA = 0, ++ JPE_COLOR_PLAN_CHROMA = 1, ++ JPE_COLOR_PLAN_MAX = 2 ++} JPE_COLOR_PLAN_e; ++ ++typedef enum ++{ ++ JPE_RAW_YUYV = 0x0, ++ JPE_RAW_YVYU = 0x1, ++ JPE_RAW_NV12 = 0x3, ++ JPE_RAW_NV21 = 0x4, ++} JpeRawFormat_e; ++ ++typedef enum ++{ ++ JPE_CODEC_JPEG = 0x1, ++ JPE_CODEC_H263I = 0x2, //! obsolete ++ JPE_CODEC_ENCODE_DCT = 0x4, //! obsolete ++} JpeCodecFormat_e; ++ ++typedef enum ++{ ++ JPE_IDLE_STATE = 0, ++ JPE_BUSY_STATE = 1, ++ JPE_FRAME_DONE_STATE = 2, ++ JPE_OUTBUF_FULL_STATE = 3, ++ JPE_INBUF_FULL_STATE = 4 ++} JpeState_e; ++ ++typedef struct ++{ ++ u32 u32JpeId; ++ u32 nRefYLogAddrAlign[2]; ++ u32 nRefCLogAddrAlign[2]; ++ u32 nOutBufSLogAddrAlign; ++ u8 nSclHandShakeSupport; ++ u8 nCodecSupport; ++ u8 nBufferModeSupport; ++} JpeCaps_t; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; ++ unsigned long nOutputSize; ++ JpeState_e eState; ++} JpeBitstreamInfo_t; ++ ++typedef struct ++{ ++ unsigned long nAddr; ++ unsigned long nSize; ++} JpeBufInfo_t; ++ ++typedef struct ++{ ++ JpeInBufMode_e eInBufMode; ++ JpeRawFormat_e eRawFormat; ++ JpeCodecFormat_e eCodecFormat; ++ ++ u32 nWidth; ++ u32 nHeight; ++ u16 YQTable[64]; ++ u16 CQTable[64]; ++ u16 nQScale; ++ ++ JpeBufInfo_t InBuf[JPE_COLOR_PLAN_MAX]; ++ JpeBufInfo_t OutBuf; ++ ++ u32 nJpeOutBitOffset; ++ ++} JpeCfg_t; ++ ++ ++typedef struct ++{ ++ JpeHalHandle_t tJpeHalHandle; ++ JpeCfg_t tJpeCfg; ++ JpeDevStatus_e eJpeDevStatus; ++ u32 nEncodeSize; ++} JpeHandle_t; ++ ++ ++typedef struct JpeEncOutbuf_t ++{ ++ unsigned long nAddr; ++ unsigned long nOrigSize; // Original buffer Size ++ unsigned long nOutputSize; // Output Size ++ JpeState_e eState; ++} JpeEncOutbuf_t; ++ ++ ++typedef struct JpeOpsCB_t JpeOpsCB_t; ++struct JpeOpsCB_t ++{ ++ char jpename[16]; ++ void* (*jpeJob)(JpeOpsCB_t*); //! get mhve_job object. ++ JPE_IOC_RET_STATUS_e(*init)(JpeOpsCB_t*, JpeCfg_t*); //! initialize. ++ JPE_IOC_RET_STATUS_e(*getCaps)(JpeOpsCB_t*, JpeCaps_t*); //! get capabilities. ++ JPE_IOC_RET_STATUS_e(*setConf)(JpeOpsCB_t*, JpeCfg_t*); //! apply config from JpegCfg ++ JPE_IOC_RET_STATUS_e(*getConf)(JpeOpsCB_t*, JpeCfg_t*); //! query config. ++ void (*release)(JpeOpsCB_t*); //! release this object. ++}; ++ ++ ++typedef struct JpeOps_t ++{ ++ JpeOpsCB_t ops; ++ JpeEncOutbuf_t *pEncOutBuf; ++ JpeHalHandle_t tJpeHalHandle; ++ unsigned short nClkSelect; ++} JpeOps_t; ++ ++JpeOpsCB_t* JpeOpsAcquire(int id); ++ ++#endif //__HAL_JPE_OPS_H__ +diff --git a/drivers/mstar/jpe2/hal/src/hal_jpe.c b/drivers/mstar/jpe2/hal/src/hal_jpe.c +new file mode 100644 +index 00000000..67ad43f5 +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/src/hal_jpe.c +@@ -0,0 +1,1469 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#if defined(__linux__) ++//#include ++#include ++//#include ++#include "ms_platform.h" ++#elif defined(__I_SW__) ++#define Chip_Phys_to_MIU(addr) HalUtilPHY2MIUAddr((unsigned int)(addr)) ++#endif ++ ++#include "hal_jpe_defs.h" ++//#include "hal_drv_util.h" ++//#include "hal_miu_arb.h" ++//#include "sys_sys_arm.h" ++//#include "hal_int_ctrl.h" ++//#include "sys_MsWrapper_cus_os_int_ctrl.h" ++#define IMG_CAP_DBG_LEVEL (_CUS2 | LEVEL_5)/* Trace Filter of image capture */ ++ ++#define TRACE ++#define DEBUG_LEVEL 0 ++#include "hal_jpe_ms_dprintf.h" ++ ++//volatile JpeReg_t jpe_reg; ++#define TIME_OUT_CNT 10 ++ ++//#define IOBASE 0xFD000000 ++//#define JPEBASE 0x132000 ++//#define LPLLBASE 0x103300 ++ ++//static u16 ++//reg_ld(u32 addr) { ++// return *((volatile u16*)addr); ++//} ++ ++//static void ++//reg_st(u32 addr, u16 val) { ++// *((volatile u16*)addr) = val; ++//} ++ ++//#if 0 ++//#define REGR(idx,cmt) reg_ld(IOBASE+((JPEBASE)*2+(idx)*4)) ++//#define REGW(idx,val,cmt) reg_st(IOBASE+((JPEBASE)*2+(idx)*4),val) ++//#define REGR_LPLL(idx,cmt) reg_ld(IOBASE+((LPLLBASE)*2+(idx)*4)) ++//#define REGW_LPLL(idx,val,cmt) reg_st(IOBASE+((LPLLBASE)*2+(idx)*4),val) ++//#else ++//#define REGR(idx,cmt) reg_ld(IOBASE+((JPEBASE)*2+(idx)*4)) ++//#define REGW(idx,val,cmt) do {reg_st(IOBASE+((JPEBASE)*2+(idx)*4),val); JPE_MSG(1, "Write %04X to reg %02X (%0X), %s", val, idx, idx*2, cmt);} while(0) ++//#define REGR_LPLL(idx,cmt) reg_ld(IOBASE+((LPLLBASE)*2+(idx)*4)) ++//#define REGW_LPLL(idx,val,cmt) do {reg_st(IOBASE+((LPLLBASE)*2+(idx)*4),val); JPE_MSG(1, "Write "cmt, val, idx);} while(0) ++//#endif ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// IRQ API // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeIrqMaskConvertEnumerate2Real ++ * Convert enumerated mask to real mask. ++ * The converter simplifies the IF of IRQ and can handle the mux of bits in the IRQ mask ++ * ++ * Parameters: ++ * mask: enumerated mask ++ * ++ * Return: ++ * Real bitwise mask ++ */ ++static u16 _HalJpeIrqMaskConvertEnumerate2Real(JpeReg_t* pJpeReg,JpeHalIrqEvent_e mask) ++{ ++ u16 real_mask = (u16)(mask & 0xFFFF); ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 0 ++ if(mask & JPE_HAL_IRQ_TXIP_TIMEOUT && !pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ real_mask |= 0x0010; ++ } ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 1 ++ if(mask & JPE_HAL_IRQ_VS && pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ real_mask |= 0x0010; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 0 ++ if(mask & JPE_HAL_IRQ_NET_TRIGGER && !pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ real_mask |= 0x0040; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 1 ++ if(mask & JPE_HAL_IRQ_VIU_ROW_DONE && pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ real_mask |= 0x0040; ++ } ++ ++ return real_mask; ++} ++ ++/******************************************************************************************************************* ++ * _HalJpeIrqMaskConvertReal2Enumerate ++ * Convert real mask to enumated mask. ++ * The converter simplifies the IF of IRQ and can handle the mux of bits in the IRQ mask ++ * ++ * Parameters: ++ * mask: real bitwise mask ++ * ++ * Return: ++ * Enumerated IRQ ++ */ ++static JpeHalIrqEvent_e _HalJpeIrqMaskConvertReal2Enumerate( JpeReg_t* pJpeReg,u16 mask) ++{ ++ JpeHalIrqEvent_e enumerate = (u16)(mask & 0xFFAF); ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 0 ++ if(mask & 0x0010 && !pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_TXIP_TIMEOUT; ++ } ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 1 ++ if(mask & 0x0010 && pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_VS; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 0 ++ if(mask & 0x0040 && !pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_NET_TRIGGER; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 1 ++ if(mask & 0x0040 && pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_VIU_ROW_DONE; ++ } ++ ++ return enumerate; ++} ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetIrqMask ++ * Set interrupt trigger mask ++ * ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetIrqMask(JpeHalHandle_t* handle, JpeHalIrqEvent_e mask) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg1c.tReg1c.nRegJpeGIrqMask = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg,mask); ++ REGW(nBaseAddr,0x1c, pJpeReg->uReg1c.nReg1c, "[%x] reg[%x] : irq mask\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeClearIrq ++ * Clear triggered interrupt ++ * ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++void HalJpeClearIrq(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr,0x1d, "[%x] reg[%x] :IRQ register\n"); ++ ++ pJpeReg->uReg1d.tReg1d.nRegJpeGIrqClr = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg,mask); ++ REGW(nBaseAddr,0x1d, pJpeReg->uReg1d.nReg1d, "[%x] reg[%x] : Clear IRQ\n"); ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr,0x1d, "[%x] reg[%x] :IRQ register\n"); // HW is write-one-clear, so update again ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrqCheck ++ * Check current IRQ status ++ * ++ * Parameters: ++ * mask: Bitwise mask to be checked ++ * ++ * Return: ++ * Checked result, bitwise ++ */ ++JpeHalIrqEvent_e HalJpeGetIrqCheck(JpeHalHandle_t* handle,JpeHalIrqEvent_e mask) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ ++ u16 reg_value; ++ reg_value = REGR(nBaseAddr,0x1e, "[%x] reg[%x] :IRQ cpu and ip status\n"); ++ ++ return _HalJpeIrqMaskConvertReal2Enumerate(pJpeReg,reg_value) & mask; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrq ++ * Get current interrupt trigger status ++ * ++ * Return: ++ * Bitwise status ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++u16 HalJpeGetIrq(JpeHalHandle_t* handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ u16 u16Reg; ++ u16Reg = REGR(nBaseAddr, 0x1e, "[%x] reg[%x] :IRQ cpu and ip status\n"); ++ ++ return u16Reg; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrqEvent ++ * IRQ bit mask check ++ * ++ * Parameters: ++ * u16IrqReg: Bitwise IRQ status ++ * IrqEventMask: Bitwise mask ++ * ++ * Return: ++ * none ++ */ ++//JpeHalIrqEvent_e HalJpeGetIrqEvent(u16 u16IrqReg, JpeHalIrqEvent_e IrqEventMask) ++//{ ++// return _HalJpeIrqMaskConvertReal2Enumerate(u16IrqReg) & IrqEventMask; ++//} ++ ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Quntization Tables Setting // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeQTableEntryRead ++ * Read a entry of Q table ++ * ++ * Parameters: ++ * index: Q table index ++ * value: the pointer of value address ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++static int _HalJpeQTableEntryRead(JpeReg_t* pJpeReg,u32 nBaseAddr,u16 index, u16 *value) ++{ ++ int retry = TIME_OUT_CNT; ++ ++ ++ //read data ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcRw = 0; ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 1; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcAdr = index; ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table address\n"); ++ REGW(nBaseAddr,0x48, pJpeReg->uReg48.nReg48, "[%x] reg[%x] : table read enable\n"); ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 0; // write one clear ++ ++ while(retry-- > 0) { ++ pJpeReg->uReg49.nReg49 = REGR(nBaseAddr,0x49, "[%x] reg[%x] : table write enable\n"); ++ if(pJpeReg->uReg49.tReg49.nRegJpeSTbcDone) { ++ // Clear done ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 1; ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 0; ++ ++ // Get value ++ *value = REGR(nBaseAddr,0x4b, "[%x] reg[%x] : table read enable\n"); ++ break; ++ } ++ } ++ ++ return retry; ++} ++ ++/******************************************************************************************************************* ++ * _HalJpeQTableEntryWrite ++ * Write a entry of Q table ++ * ++ * Parameters: ++ * index: Q table index ++ * value: Quantization value ++ * ++ * Return: ++ * >=0: success ++ * <=0: failed ++ */ ++static int _HalJpeQTableEntryWrite(JpeReg_t* pJpeReg,u32 nBaseAddr,u16 index, u16 value) ++{ ++ int retry = TIME_OUT_CNT; ++ ++ // Set value ++ pJpeReg->uReg4a.tReg4a.nRegJpeSTbcWdata = value; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcRw = 1; ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 1; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcAdr = index; ++ REGW(nBaseAddr,0x4a, pJpeReg->uReg4a.nReg4a, "[%x] reg[%x] : table write data\n"); ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table address\n"); ++ REGW(nBaseAddr,0x48, pJpeReg->uReg48.nReg48, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 0; // write one clear ++ ++ // Wait for set done ++ while(retry-- > 0) { ++ pJpeReg->uReg49.nReg49 = REGR(nBaseAddr,0x49, "[%x] reg[%x] : table write enable\n"); ++ if(pJpeReg->uReg49.tReg49.nRegJpeSTbcDone) { ++ // Clear done ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 1; ++ REGW(nBaseAddr,0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 0; ++ break; ++ } ++ } ++ ++ return retry; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetQTable ++ * Update Q table ++ * ++ * Parameters: ++ * q_table_y: Q table for Y ++ * q_table_c: Q table for CbCr ++ * size: table size ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++int HalJpeSetQTable(JpeHalHandle_t* handle,const u16 *q_table_y, const u16 *q_table_c, u32 size) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ u16 value_w, value_r; ++ int i, retry, ret = 0; ++ ++ // Switch SW mode to update Q table ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 0; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=0\n"); ++ ++ // ? ++ // jpe_reg.uReg48.nReg48 = 0; ++ ++ // Udate Y table ++ for(i=0; i 0) { ++ value_w = q_table_y[((i&0x7)<<3)|(i>>3)]; ++ ++ // Write ++ if(_HalJpeQTableEntryWrite(pJpeReg,nBaseAddr,i, value_w) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i, &value_r) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Compare ++ if(value_r == value_w) ++ break; ++ } ++ } ++ ++ // Udate C table ++ for(i=0; i 0) { ++ value_w = q_table_c[((i&0x7)<<3)|(i>>3)]; ++ ++ // Write ++ if(_HalJpeQTableEntryWrite(pJpeReg,nBaseAddr,i+64, value_w) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i+64, &value_r) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Compare ++ if(value_r == value_w) ++ break; ++ } ++ } ++ ++ // update Index last identyfier ++ // The default size of Quantization table is 64, but JPE can accept that size smaller than 64 and ++ // treat others as 0 ( I guess...) ++ pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxLast = size; ++ pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxSwlast = (size < 63) ? 1 : 0; ++ REGW(nBaseAddr,0x2c, pJpeReg->uReg2c.nReg2c, "[%x] reg[%x] : Last zigzag\n"); ++ ++RETURN: ++ // Switch to hw mode ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 1; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=1\n"); ++ ++ return ret; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeReadQTable ++ * Read Q table set last time ++ * ++ * Parameters: ++ * q_table_y: Q table for Y ++ * q_table_c: Q table for CbCr ++ * size: table size ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++int HalJpeReadQTable(JpeHalHandle_t* handle,u16 *q_table_y, u16 *q_table_c, u32 *size) ++{ ++ int i, ret = 0; ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ // Switch SW mode to read Q table ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 0; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=0\n"); ++ ++ // Is the size of table smaller than 64? ++ if(pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxSwlast) { ++ *size = pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxLast; ++ } else { ++ *size = 64; ++ } ++ ++ // ? ++ // jpe_reg.uReg48.nReg48 = 0; ++ ++ // Udate Y table ++ for(i=0; i<*size; i++) { ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i, q_table_y+i) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ } ++ ++ // Udate C table ++ for(i=0; i<*size; i++) { ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg,nBaseAddr,i+64, q_table_c+i) <= 0) { ++ ret = -1; ++ goto RETURN; ++ } ++ } ++ ++RETURN: ++ // Switch to hw mode ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 1; ++ REGW(nBaseAddr,0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=1\n"); ++ ++ return ret; ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Configurations // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeSetJpeMode ++ * Config JPEG Mode ++ * ++ * Parameters: ++ * bUseJPE: 1 is JPEG encoder, 0 is JPEG decoder ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetJpeMode(JpeHalHandle_t* handle,u32 bUseJPE) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ if (bUseJPE) ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 0; ++ else ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 1; ++ ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : Set JPE mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetCodecFormat ++ * Config the encode froamt of HW codec ++ * ++ * Parameters: ++ * format: JPE_HAL_CODEC_JPEG: JPEG Mode ++ * JPE_HAL_CODEC_H263I: HW not support ++ * JPE_HAL_CODEC_ENCODE_DCT: SW not implemented yet ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetCodecFormat(JpeHalHandle_t* handle,JpeHalCodecFormat_e format) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ switch(format) { ++ case JPE_HAL_CODEC_JPEG: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 0; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 0; ++ break; ++ ++ case JPE_HAL_CODEC_H263I: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 1; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 0; ++ break; ++ ++ case JPE_HAL_CODEC_ENCODE_DCT: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 0; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 1; ++ break; ++ } ++ ++ REGW(nBaseAddr,0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : Codec mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetEncFormat ++ * Config the RAW format for HW codec ++ * ++ * Parameters: ++ * format: JPE_HAL_RAW_YUYV: 422 YUYV ++ * JPE_HAL_RAW_YVYU: 422 YVYU ++ * JPE_HAL_RAW_NV12: 420 NV12 ++ * JPE_HAL_RAW_NV21: 420 NV21 ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetRawFormat(JpeHalHandle_t* handle,JpeHalRawFormat_e format) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ switch(format) { ++ case JPE_HAL_RAW_YUYV: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 1; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 0; ++ break; ++ ++ case JPE_HAL_RAW_YVYU: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 1; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 1; ++ break; ++ ++ case JPE_HAL_RAW_NV12: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 0; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 0; ++ break; ++ ++ case JPE_HAL_RAW_NV21: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 0; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 1; ++ break; ++ } ++ ++ REGW(nBaseAddr,0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : YUV format\n"); ++ REGW(nBaseAddr,0x5F, pJpeReg->uReg5f.nReg5f, "[%x] reg[%x] : YUV format\n"); ++} ++ ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetPicDim ++ * Config the input dimension (for encoder only?) ++ * ++ * Parameters: ++ * width: Image width in pixel ++ * height: Image height in pixel ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetPicDim(JpeHalHandle_t* handle,u32 width, u32 height) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg01.tReg01.nRegJpeGPicWidth = width; // (width+15)&~15; ++ pJpeReg->uReg02.tReg02.nRegJpeGPicHeight = (height+7)&~7; ++ pJpeReg->uReg5e.tReg5e.nRegGJpeYPitch = (width+15) / 16; ++ pJpeReg->uReg5e.tReg5e.nRegGJpeCPitch = (width+15) / 16; ++ REGW(nBaseAddr,0x01, pJpeReg->uReg01.nReg01, "[%x] reg[%x] : picture width\n"); ++ REGW(nBaseAddr,0x02, pJpeReg->uReg02.nReg02, "[%x] reg[%x] : picture height\n"); ++ REGW(nBaseAddr,0x5E, pJpeReg->uReg5e.nReg5e, "[%x] reg[%x] : picture pitch\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeToggleOutBuf ++ * Toggle output buffer ++ * ++ * Parameters: ++ * nObufIdx: new output buffer index ++ * ++ * Return: ++ * none ++ */ ++void HalJpeToggleOutBuf(JpeHalHandle_t* handle,u32 nObufIdx) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ if (nObufIdx==0) ++ { ++ ms_dprintf(0,"nRegJpeObufToggleObuf_0\n"); ++ pJpeReg->uReg3b.nReg3b = REGR(nBaseAddr,0x3b, "[%x] reg[%x] : SW read buffer 0\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : SW read buffer 0\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ } ++ else ++ { ++ ms_dprintf(0,"nRegJpeObufToggleObuf_1\n"); ++ pJpeReg->uReg3b.nReg3b = REGR(nBaseAddr,0x3b, "[%x] reg[%x] : SW read buffer 1\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : SW read buffer 1\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ } ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetInputMode ++ * Config the operation mode of input buffer ++ * ++ * Parameters: ++ * mode: JPE_HAL_BUFFER_ROW_MODE: Double buffer mode (for ROW of IMI?) ++ * Others: Normal (single) frame mode (for MIU?) ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetInputMode(JpeHalHandle_t* handle,JpeHalInBufMode_e mode) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ if(mode == JPE_HAL_BUFFER_ROW_MODE) ++ pJpeReg->uReg18.tReg18.nRegJpeGJpeBuffermode = 0; ++ else ++ pJpeReg->uReg18.tReg18.nRegJpeGJpeBuffermode = 1; ++ REGW(nBaseAddr,0x18, pJpeReg->uReg18.nReg18, "[%x] reg[%x] : input buffer mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetOutputMode ++ * Config the operation mode of output buffer ++ * ++ * Parameters: ++ * mode: JPE_HAL_OBUF_SINGLE_MODE: All outputs are written to only one buffer ++ * JPE_HAL_OBUF_MULTI_MODE: Outputs are written to may buffers ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetOutputMode(JpeHalHandle_t *handle,JpeHalOutBufMode_e mode) ++{ ++ // End of config?? ++ uint nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufHwEn = mode; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : output buffer mode\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetInBuf ++ * Config input & output address ++ * ++ * Parameters: ++ * ptInBufCfg: Input buffer configuration ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetInBuf(JpeHalHandle_t* handle,pJpeHalInBufCfg ptInBufCfg) ++{ ++ u32 addr; ++ uint nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ //assert((ptBufInfo->nInBufYAddr[0]&0xFF)==0); ++ //assert((ptBufInfo->nInBufYAddr[1]&0xFF)==0); ++ //assert((ptBufInfo->nInBufCAddr[0]&0xFF)==0); ++ //assert((ptBufInfo->nInBufCAddr[1]&0xFF)==0); ++ ++ // Y0 ++ if(ptInBufCfg->nInBufYAddr[0]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufYAddr[0]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ ++ pJpeReg->uReg06.tReg06.nRegJpeGBufYAdr0Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg07.tReg07.nRegJpeGBufYAdr0High = addr>>(8+16); ++#if 0 ++ send_trace("ptInBufCfg->nInBufYAddr[0]=0x%x, addr=0x%x\n", ptInBufCfg->nInBufYAddr[0], addr); ++ send_trace("(0x%x,0x%x), nRegJpeGBufYAdr0Low:0x%x, nRegJpeGBufYAdr0High:0x%x \n", \ ++ (addr>>8)&0xFFFF,\ ++ addr>>(8+16),\ ++ pJpeReg->uReg06.tReg06.nRegJpeGBufYAdr0Low,\ ++ pJpeReg->uReg07.tReg07.nRegJpeGBufYAdr0High); ++#endif ++ // Y1 ++ if(ptInBufCfg->nInBufYAddr[1]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufYAddr[1]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ pJpeReg->uReg08.tReg08.nRegJpeGBufYAdr1Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg09.tReg09.nRegJpeGBufYAdr1High = addr>>(8+16); ++ ++ // C0 ++ if(ptInBufCfg->nInBufCAddr[0]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufCAddr[0]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ pJpeReg->uReg0a.tReg0a.nRegJpeGBufCAdr0Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg0b.tReg0b.nRegJpeGBufCAdr0High = addr>>(8+16); ++ ++ // C1 ++ if(ptInBufCfg->nInBufCAddr[1]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufCAddr[1]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ pJpeReg->uReg0c.tReg0c.nRegJpeGBufCAdr1Low = (addr>>8)&0xFFFF; ++ pJpeReg->uReg0d.tReg0d.nRegJpeGBufCAdr1High = addr>>(8+16); ++ ++ // Input buffers ++ // ++ REGW(nBaseAddr,0x06, pJpeReg->uReg06.nReg06, "[%x] reg[%x] : Y0_low\n"); ++ REGW(nBaseAddr,0x07, pJpeReg->uReg07.nReg07, "[%x] reg[%x] : Y0_high\n"); ++ REGW(nBaseAddr,0x08, pJpeReg->uReg08.nReg08, "[%x] reg[%x] : Y1_low\n"); ++ REGW(nBaseAddr,0x09, pJpeReg->uReg09.nReg09, "[%x] reg[%x] : Y1 high\n"); ++ REGW(nBaseAddr,0x0a, pJpeReg->uReg0a.nReg0a, "[%x] reg[%x] : C0_low\n"); ++ REGW(nBaseAddr,0x0b, pJpeReg->uReg0b.nReg0b, "[%x] reg[%x] : C0_high\n"); ++ REGW(nBaseAddr,0x0c, pJpeReg->uReg0c.nReg0c, "[%x] reg[%x] : C1_low\n"); ++ REGW(nBaseAddr,0x0d, pJpeReg->uReg0d.nReg0d, "[%x] reg[%x] : C1_high\n"); ++} ++ ++/******************************************************************************************************************* ++ * _HalJpeSetOutBuf ++ * Set output buffer ++ * ++ * Parameters: ++ * addr: physical address ++ * id: index of addres ++ * 0: start of 1st address ++ * 1: end of 1st address ++ * 2: start of 2nd address ++ * 3: end of 2nd address ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSetOutBuf(JpeReg_t* pJpeReg,u32 nBaseAddr,u32 addr, u32 id) ++{ ++ addr = Chip_Phys_to_MIU(addr); ++ ++ // Write address info ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (addr>>2)&0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = addr>>(2+16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = id; ++ REGW(nBaseAddr,0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr,0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ ++ // Enable write action? ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr,0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++ // jpe_reg.uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 0; ++ // REGW(0x3e, jpe_reg.uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write disable\n"); ++} ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetOutBuf ++ * Config input & output address ++ * ++ * Parameters: ++ * ptBufCfg: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetOutBuf(JpeHalHandle_t* handle,pJpeHalOutBufCfg ptOutBufCfg) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ // Start to config Output buffer ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspFdcOffset = ptOutBufCfg->nJpeOutBitOffset; ++#if defined(ADD_JPDE_0_1) ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ ++ // Start to config output buffer (write one clear) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; // HW is write-one-clear ++#endif ++ ++ ++ // Set 1st address ++ if(ptOutBufCfg->nOutBufAddr[0] != 0 && ptOutBufCfg->nOutBufSize[0] != 0) ++ { ++ //JPE_MSG(JPE_MSG_DEBUG, "Set[0] 0x%08X, size %d\n", ptOutBufCfg->nOutBufAddr[0], ptOutBufCfg->nOutBufSize[0]); ++ _HalJpeSetOutBuf(pJpeReg, nBaseAddr, ptOutBufCfg->nOutBufAddr[0], 0); ++ _HalJpeSetOutBuf(pJpeReg, nBaseAddr, ptOutBufCfg->nOutBufAddr[0] + ptOutBufCfg->nOutBufSize[0]-1, 1); ++ ++ } ++ ++ // Set 2nd address ++ if(ptOutBufCfg->nOutBufAddr[1] != 0 && ptOutBufCfg->nOutBufSize[1] != 0) ++ { ++ //JPE_MSG(JPE_MSG_DEBUG, "Set[1] 0x%08X, size %d\n", ptOutBufCfg->nOutBufAddr[1], ptOutBufCfg->nOutBufSize[1]); ++ _HalJpeSetOutBuf(pJpeReg,nBaseAddr,ptOutBufCfg->nOutBufAddr[1], 2); ++ _HalJpeSetOutBuf(pJpeReg,nBaseAddr,ptOutBufCfg->nOutBufAddr[1] + ptOutBufCfg->nOutBufSize[1]-1, 3); ++ } ++ ++ // Set configured address ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : buffer mode\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; // HW is write-one-clear ++ ++ ++#if defined(ADD_JPDE_0_1) ++ // Stop configuring output buffer (write one clear) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; // HW is write-one-clear ++#endif ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetDctMbAddr ++ * ??? ++ * ++ * Parameters: ++ * PhyAddr: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetDctMbAddr(JpeHalHandle_t* handle,u32 PhyAddr) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ u32 nMiuStartAddr, nMiuEndAddr, nY0MiuAddr; ++ ++ nMiuStartAddr = PhyAddr; ++ nMiuEndAddr = PhyAddr+768; ++ nY0MiuAddr = PhyAddr; ++ ++ REGW(nBaseAddr,0x06,(nY0MiuAddr>>8)&0xFFFF, "[%x] reg[%x] : Y0_low\n"); ++ REGW(nBaseAddr,0x07, nY0MiuAddr>>(8+16), "[%x] reg[%x] : Y0_high\n"); ++ // Output buffer ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspFdcOffset = 0; ++#if defined(ADD_JPDE_0_1) ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; ++#endif ++ ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (nMiuStartAddr>>2)&0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = nMiuStartAddr>>(2+16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = 0; ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr,0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr,0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ REGW(nBaseAddr,0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (nMiuEndAddr>>2)&0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = nMiuEndAddr>>(2+16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = 1; ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr,0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr,0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ REGW(nBaseAddr,0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 1; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : buffer mode\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; // HW is write-one-clear ++} ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Controls // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeSoftReset ++ * Reset JPEG engine ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSoftReset(JpeReg_t* pJpeReg,u32 nBaseAddr) ++{ ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 0; // Assure JPE is running. ++ pJpeReg->uReg00.tReg00.nRegJpeGSoftRstz =0; ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ ++ // delay for lower MCM frequence ++ // Repeated write to replace udelay(1) becase 1 us is too long ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ ++ pJpeReg->uReg00.tReg00.nRegJpeGSoftRstz = 1; ++ REGW(nBaseAddr,0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 1\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSoftReset ++ * SW reset JPEG engine & internal variables ++ * ++ * Parameters: ++ * handle: HAL handle ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSoftReset(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++#define _UPDATE_REG_VAR(nBaseAddr,reg_no) pJpeReg->uReg##reg_no.nReg##reg_no = REGR(nBaseAddr,0x##reg_no, "\n");//REGR(0x##reg_no, "\n"); ++ // SW reset at first ++ _HalJpeSoftReset(pJpeReg,nBaseAddr); ++ ++ // Sync all HW setting to jpe_reg ++ _UPDATE_REG_VAR(nBaseAddr,00); ++ _UPDATE_REG_VAR(nBaseAddr,01); ++ _UPDATE_REG_VAR(nBaseAddr,02); ++ _UPDATE_REG_VAR(nBaseAddr,03); ++ _UPDATE_REG_VAR(nBaseAddr,06); ++ _UPDATE_REG_VAR(nBaseAddr,07); ++ _UPDATE_REG_VAR(nBaseAddr,08); ++ _UPDATE_REG_VAR(nBaseAddr,09); ++ _UPDATE_REG_VAR(nBaseAddr,0a); ++ _UPDATE_REG_VAR(nBaseAddr,0b); ++ _UPDATE_REG_VAR(nBaseAddr,0c); ++ _UPDATE_REG_VAR(nBaseAddr,0d); ++ _UPDATE_REG_VAR(nBaseAddr,0f); ++ _UPDATE_REG_VAR(nBaseAddr,10); ++ _UPDATE_REG_VAR(nBaseAddr,16); ++ _UPDATE_REG_VAR(nBaseAddr,18); ++ _UPDATE_REG_VAR(nBaseAddr,1c); ++ _UPDATE_REG_VAR(nBaseAddr,1d); ++ _UPDATE_REG_VAR(nBaseAddr,1e); ++ _UPDATE_REG_VAR(nBaseAddr,1f); ++ _UPDATE_REG_VAR(nBaseAddr,20); ++ _UPDATE_REG_VAR(nBaseAddr,21); ++ _UPDATE_REG_VAR(nBaseAddr,2c); ++ _UPDATE_REG_VAR(nBaseAddr,2d); ++ _UPDATE_REG_VAR(nBaseAddr,2e); ++ _UPDATE_REG_VAR(nBaseAddr,32); ++ _UPDATE_REG_VAR(nBaseAddr,33); ++ _UPDATE_REG_VAR(nBaseAddr,34); ++ _UPDATE_REG_VAR(nBaseAddr,35); ++ _UPDATE_REG_VAR(nBaseAddr,36); ++ _UPDATE_REG_VAR(nBaseAddr,3b); ++ _UPDATE_REG_VAR(nBaseAddr,3c); ++ _UPDATE_REG_VAR(nBaseAddr,3d); ++ _UPDATE_REG_VAR(nBaseAddr,3e); ++ _UPDATE_REG_VAR(nBaseAddr,42); ++ _UPDATE_REG_VAR(nBaseAddr,44); ++ _UPDATE_REG_VAR(nBaseAddr,45); ++ _UPDATE_REG_VAR(nBaseAddr,48); ++ _UPDATE_REG_VAR(nBaseAddr,49); ++ _UPDATE_REG_VAR(nBaseAddr,4a); ++ _UPDATE_REG_VAR(nBaseAddr,4b); ++ _UPDATE_REG_VAR(nBaseAddr,54); ++ _UPDATE_REG_VAR(nBaseAddr,55); ++ _UPDATE_REG_VAR(nBaseAddr,56); ++ _UPDATE_REG_VAR(nBaseAddr,57); ++ _UPDATE_REG_VAR(nBaseAddr,58); ++ _UPDATE_REG_VAR(nBaseAddr,59); ++ _UPDATE_REG_VAR(nBaseAddr,5a); ++ _UPDATE_REG_VAR(nBaseAddr,5b); ++ _UPDATE_REG_VAR(nBaseAddr,5c); ++ _UPDATE_REG_VAR(nBaseAddr,5d); ++ _UPDATE_REG_VAR(nBaseAddr,5e); ++ _UPDATE_REG_VAR(nBaseAddr,5f); ++ _UPDATE_REG_VAR(nBaseAddr,60); ++ _UPDATE_REG_VAR(nBaseAddr,61); ++ _UPDATE_REG_VAR(nBaseAddr,64); ++ _UPDATE_REG_VAR(nBaseAddr,6f); ++ _UPDATE_REG_VAR(nBaseAddr,70); ++ _UPDATE_REG_VAR(nBaseAddr,71); ++ _UPDATE_REG_VAR(nBaseAddr,72); ++ _UPDATE_REG_VAR(nBaseAddr,73); ++ _UPDATE_REG_VAR(nBaseAddr,74); ++ _UPDATE_REG_VAR(nBaseAddr,75); ++ _UPDATE_REG_VAR(nBaseAddr,76); ++ _UPDATE_REG_VAR(nBaseAddr,77); ++ _UPDATE_REG_VAR(nBaseAddr,78); ++ _UPDATE_REG_VAR(nBaseAddr,79); ++ _UPDATE_REG_VAR(nBaseAddr,7a); ++ _UPDATE_REG_VAR(nBaseAddr,7b); ++ _UPDATE_REG_VAR(nBaseAddr,7c); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetEnable ++ * Enable JPEG enging ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetEnable(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 1; ++ REGW(nBaseAddr,0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : frame start\n"); ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 0; // write-one-clear ++} ++ ++/******************************************************************************************************************* ++ * HalJpeHwRowCounterReset ++ * SW reset JPEG VIU? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeHwRowCounterReset(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg18.tReg18.nRegJpeGViuSoftRstz=0; ++ REGW(nBaseAddr,0x18,pJpeReg->uReg18.nReg18, "[%x] reg[%x] : VIU reset 0\n"); ++ pJpeReg->uReg18.tReg18.nRegJpeGViuSoftRstz=1; ++ REGW(nBaseAddr,0x18, pJpeReg->uReg18.nReg18, "[%x] reg[%x] : VIU reset 1\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetSwVsnc ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetSWRowDown(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg75.tReg75.nRegJpeGSwRowDone = 1; ++ REGW(nBaseAddr,0x75, pJpeReg->uReg75.nReg75,"[%x] reg[%x] :SW Row Down\n"); ++ pJpeReg->uReg75.tReg75.nRegJpeGSwRowDone = 0; // write one clear ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Status // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeResetSafe ++ * to indicate there're no MIU activities that need to pay attention to ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * true: MIU accesse is active ++ * false: no MIU activity ++ */ ++bool HalJpeResetSafe(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr,0x1d, "[%x] reg[%x] :reset safe\n"); ++ ++ ms_dprintf(0, "uReg1d.tReg1d.nRegJpeGSwrstSafe is %d\n", pJpeReg->uReg1d.tReg1d.nRegJpeGSwrstSafe); ++ ++ return (pJpeReg->uReg1d.tReg1d.nRegJpeGSwrstSafe == 1) ? true : false; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetOutputByteSize ++ * Retrive the output size ++ * ++ * Parameters: ++ * nObufSel: buffer index ++ * ++ * Return: ++ * Output buffer size ++ */ ++u32 HalJpeGetOutputByteSize(JpeHalHandle_t *handle,u32 nObufSel) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ u16 u16Reg1, u16Reg2, u16Reg3; ++ u32 wptr, oBufSadr; ++ u16 u16Reg; ++ //u16 i; ++ ++ u16Reg = REGR(nBaseAddr,0x3b, "[%x] reg[%x] : obuf status\n"); ++ pJpeReg->uReg3b.nReg3b = u16Reg; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkEn = 1; ++/* ++ for (i=0; i<4; i++) { ++ jpe_reg.uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = i; ++ REGW(0x3b, jpe_reg.uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ _ReadRegJpe(0x44, &u16Reg1, "[%x] reg[%x] : wptr low\n"); ++ _ReadRegJpe(0x45, &u16Reg2, "[%x] reg[%x] : wptr high\n"); ++ oBufSadr = ((u16Reg2<<16) | u16Reg1)<<2; ++ ms_dprintf(1,"Obuf%d %d %d(s=0,e=1) = 0x%08x\n",i,i>>1, i&1, oBufSadr); ++ } ++*/ ++ //obuf adr read back check selection(0/1/2/3:s0/e0/s1/e1) ++ if (nObufSel == JPE_OBUF_0) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = 0; //s0 ++ else ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = 2; //s1 ++ ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ u16Reg1 = REGR(nBaseAddr,0x44, "[%x] reg[%x] : wptr low\n"); ++ u16Reg2 = REGR(nBaseAddr,0x45, "[%x] reg[%x] : wptr high\n"); ++ oBufSadr = ((u16Reg2<<16) | u16Reg1)<<2; ++ ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkEn = 0; ++ REGW(nBaseAddr,0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ u16Reg1 = REGR(nBaseAddr,0x44, "[%x] reg[%x] : wptr low\n"); ++ u16Reg2 = REGR(nBaseAddr,0x45, "[%x] reg[%x] : wptr high\n"); ++ wptr = ((u16Reg2<<16) | u16Reg1)<<2; ++ ++ u16Reg3 = REGR(nBaseAddr,0x42, "[%x] reg[%x] : last bytes in miu\n"); ++ ++ u16Reg3 &= 3; ++ u16Reg3 += 1; ++ ++ return wptr - oBufSadr + u16Reg3; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRowDownCnt ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++u16 HalJpeGetRowDownCnt(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ u16 u16Reg; ++ u16Reg = REGR(nBaseAddr,0x10, "[%x] reg[%x] :Row down count\n"); ++ return u16Reg&0x0F; ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// TXIP? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeStop ++ * ??? ++ * ++ * Parameters: ++ * opt: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeStop(JpeHalHandle_t *handle,bool opt) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg2d.tReg2d.nRegJpeSTxipSngSet = opt; ++ REGW(nBaseAddr,0x2d, pJpeReg->uReg2d.nReg2d, "[%x] reg[%x] : stop\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRowCount ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++u16 HalJpeGetRowCount(JpeHalHandle_t *handle) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg2e.nReg2e = REGR(nBaseAddr,0x2e, "[%x] reg[%x] :Row count\n"); ++ return pJpeReg->uReg2e.nReg2e; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeIdleCount ++ * ??? ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * none ++ */ ++void HalJpeIdleCount(JpeHalHandle_t *handle,u16 nIdleCount) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg32.tReg32.nRegJpeSTxipWaitMode = 0; ++ pJpeReg->uReg33.tReg33.nRegJpeSTxipIdlecnt = nIdleCount; ++ ++ REGW(nBaseAddr,0x32, pJpeReg->uReg32.nReg32, "[%x] reg[%x] : wait mode\n"); ++ REGW(nBaseAddr,0x33, pJpeReg->uReg33.nReg33, "[%x] reg[%x] : idle count\n"); ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Debugs? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeSetCycleReport ++ * ??? ++ * ++ * Parameters: ++ * mode: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetCycleReport(JpeHalHandle_t *handle,u16 mode) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++#ifdef CYCLE_REPORT ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkEn = 1; ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkSel = 1; ++#else ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkEn = 0; ++ pJpeReg->uReg73.tReg73.nRegJpeGDebugTcycleChkSel = 0; ++#endif ++ REGW(nBaseAddr,0x73, pJpeReg->uReg73.nReg73, "[%x] reg[%x] : cycle report\n"); ++} ++ ++/******************************************************************************************************************* ++ * HalJpeSetCrc ++ * ??? ++ * ++ * Parameters: ++ * mode: ??? ++ * ++ * Return: ++ * none ++ */ ++void HalJpeSetCrc(JpeHalHandle_t *handle,u16 mode) ++{ ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ pJpeReg->uReg73.tReg73.nRegJpeGCrcMode = 0x2; ++ REGW(nBaseAddr,0x73, pJpeReg->uReg73.nReg73, "[%x] reg[%x] : crc mode\n"); ++} ++ ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Capibilities? // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * HalJpeGetBufferModeSupportInfo ++ * Capability of supported mode of current JPEG HW ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The bitwise combination of supported mode ++ */ ++u8 HalJpeGetBufferModeSupportInfo(void) ++{ ++ return JPE_HAL_BUFFER_ROW_MODE|JPE_HAL_BUFFER_FRAME_MODE; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetSclHandShakeSupportInfo ++ * Capability of scaler data handshake ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * JpeHalSclHandShake_e ++ */ ++u8 HalJpeGetSclHandShakeSupportInfo(void) ++{ ++ return JPE_HAL_SCL_HANDSHAKE_ON; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetCodecSupportInfo ++ * Capability of supported codec format ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The bitwize combination of supported codec mode ++ */ ++u8 HalJpeGetCodecSupportInfo(void) ++{ ++ return JPE_HAL_CODEC_JPEG; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetOutBufSLogAddrAlignInfo ++ * Alignment of output buffer address (start) ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetOutBufSLogAddrAlignInfo(void) ++{ ++ return 4; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetOutBufELogAddrAlignInfo ++ * Alignment of output buffer address (end) ++ * ++ * Parameters: ++ * none ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetOutBufELogAddrAlignInfo(void) ++{ ++ return 4; ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRefCLogAddrAlignInfo ++ * Alignment of input buffer address (Y) ++ * ++ * Parameters: ++ * bufID: not use.... ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetRefYLogAddrAlignInfo(u8 bufID) ++{ ++ return 256; ++ ++} ++ ++/******************************************************************************************************************* ++ * HalJpeGetRefCLogAddrAlignInfo ++ * Alignment of input buffer address (C) ++ * ++ * Parameters: ++ * bufID: not use.... ++ * ++ * Return: ++ * The alignment ++ */ ++u32 HalJpeGetRefCLogAddrAlignInfo(u8 bufID) ++{ ++ return 256; ++} ++ ++ ++u32 HalJpeSetClock(JpeHalHandle_t* pJpeHalHandle) ++{ ++ JpeReg_t* pJpeReg = NULL; ++ ++ if(!pJpeHalHandle) ++ return -1; ++ ++ pJpeReg = &pJpeHalHandle->tJpeReg; ++ ++ /* Enable Clk */ ++ //REGW(REG_CKG_MFE_BASE,0x00,regs->regClk,"Set Clk"); ++ // REGWR(base,0x16,regs->reg16,"clock gating"); ++ REGW(REG_CKG_JPE_BASE, 0x00, pJpeReg->regClk, "Set Clk\n"); ++ ++ return 0; ++} +\ No newline at end of file +diff --git a/drivers/mstar/jpe2/hal/src/hal_jpe_ios.c b/drivers/mstar/jpe2/hal/src/hal_jpe_ios.c +new file mode 100644 +index 00000000..ad5e5ef2 +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/src/hal_jpe_ios.c +@@ -0,0 +1,925 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "hal_jpe_ios.h" ++ ++#define TIME_OUT_CNT 10 ++ ++/******************************************************************************************************************* ++ * _HalJpeIrqMaskConvertEnumerate2Real ++ * Convert enumerated mask to real mask. ++ * The converter simplifies the IF of IRQ and can handle the mux of bits in the IRQ mask ++ * ++ * Parameters: ++ * mask: enumerated mask ++ * ++ * Return: ++ * Real bitwise mask ++ */ ++static u16 _HalJpeIrqMaskConvertEnumerate2Real(JpeReg_t* pJpeReg, JpeHalIrqEvent_e mask) ++{ ++ u16 real_mask = (u16)(mask & 0xFFFF); ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 0 ++ if(mask & JPE_HAL_IRQ_TXIP_TIMEOUT && !pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ real_mask |= 0x0010; ++ } ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 1 ++ if(mask & JPE_HAL_IRQ_VS && pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ real_mask |= 0x0010; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 0 ++ if(mask & JPE_HAL_IRQ_NET_TRIGGER && !pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ real_mask |= 0x0040; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 1 ++ if(mask & JPE_HAL_IRQ_VIU_ROW_DONE && pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ real_mask |= 0x0040; ++ } ++ ++ return real_mask; ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeIrqMaskConvertReal2Enumerate ++ * Convert real mask to enumated mask. ++ * The converter simplifies the IF of IRQ and can handle the mux of bits in the IRQ mask ++ * ++ * Parameters: ++ * mask: real bitwise mask ++ * ++ * Return: ++ * Enumerated IRQ ++ */ ++static JpeHalIrqEvent_e _HalJpeIrqMaskConvertReal2Enumerate(JpeReg_t* pJpeReg, u16 mask) ++{ ++ JpeHalIrqEvent_e enumerate = (u16)(mask & 0xFFAF); ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 0 ++ if(mask & 0x0010 && !pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_TXIP_TIMEOUT; ++ } ++ ++ // Bit 4 when reg_jpe_g_vs_irq_en = 1 ++ if(mask & 0x0010 && pJpeReg->uReg73.tReg73.nRegJpeGVsIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_VS; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 0 ++ if(mask & 0x0040 && !pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_NET_TRIGGER; ++ } ++ ++ // Bit 6 when reg_jpe_g_row_down_irq_en = 1 ++ if(mask & 0x0040 && pJpeReg->uReg73.tReg73.nRegJpeGRowDownIrqEn) ++ { ++ enumerate |= JPE_HAL_IRQ_VIU_ROW_DONE; ++ } ++ ++ return enumerate; ++} ++ ++ ++/******************************************************************************************************************* ++ * HalJpeGetIrqCheck ++ * Check current IRQ status ++ * ++ * Parameters: ++ * mask: Bitwise mask to be checked ++ * ++ * Return: ++ * Checked result, bitwise ++ */ ++static JpeHalIrqEvent_e _HalJpeGetIrqCheck(u32 nBaseAddr, JpeReg_t* pJpeReg, JpeHalIrqEvent_e mask) ++{ ++ u16 reg_value; ++ reg_value = REGR(nBaseAddr, 0x1e, "[%x] reg[%x] :IRQ cpu and ip status\n"); ++ return _HalJpeIrqMaskConvertReal2Enumerate(pJpeReg, reg_value) & mask; ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeSetIrqMask ++ * Set interrupt trigger mask ++ * ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSetIrqMask(u32 nBaseAddr, JpeReg_t* pJpeReg, JpeHalIrqEvent_e nMask) ++{ ++ pJpeReg->uReg1c.tReg1c.nRegJpeGIrqMask = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg, nMask); ++ REGW(nBaseAddr, 0x1c, pJpeReg->uReg1c.nReg1c, "[%x] reg[%x] : irq mask\n"); ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeClearIrq ++ * Clear triggered interrupt ++ * ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeClearIrq(u32 nBaseAddr, JpeReg_t* pJpeReg, JpeHalIrqEvent_e nMask) ++{ ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr, 0x1d, "[%x] reg[%x] :IRQ register\n"); ++ ++ pJpeReg->uReg1d.tReg1d.nRegJpeGIrqClr = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg, nMask); ++ REGW(nBaseAddr, 0x1d, pJpeReg->uReg1d.nReg1d, "[%x] reg[%x] : Clear IRQ\n"); ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr, 0x1d, "[%x] reg[%x] :IRQ register\n"); // HW is write-one-clear, so update again ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeGetIrq ++ * Get current interrupt trigger status ++ * ++ * Return: ++ * Bitwise status ++ * Parameters: ++ * mask: Bitwise mask, defined in JpeHalIrqEvent_e ++ * ++ * Return: ++ * none ++ */ ++static u16 _HalJpeGetIrq(u32 nBaseAddr) ++{ ++ u16 u16Reg; ++ u16Reg = REGR(nBaseAddr, 0x1e, "[%x] reg[%x] :IRQ cpu and ip status\n"); ++ return u16Reg; ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeGetOutputByteSize ++ * Retrive the output size ++ * ++ * Parameters: ++ * nObufSel: buffer index ++ * ++ * Return: ++ * Output buffer size ++ */ ++static u32 _HalJpeGetOutputByteSize(u32 nBaseAddr, JpeReg_t* pJpeReg, u32 nObufSel) ++{ ++ u16 u16Reg1, u16Reg2, u16Reg3; ++ u32 wptr, oBufSadr; ++ u16 u16Reg; ++ ++ u16Reg = REGR(nBaseAddr, 0x3b, "[%x] reg[%x] : obuf status\n"); ++ pJpeReg->uReg3b.nReg3b = u16Reg; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkEn = 1; ++ ++ //obuf adr read back check selection(0/1/2/3:s0/e0/s1/e1) ++ if(nObufSel == JPE_OBUF_0) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = 0; //s0 ++ else ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkSe1 = 2; //s1 ++ ++ REGW(nBaseAddr, 0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ u16Reg1 = REGR(nBaseAddr, 0x44, "[%x] reg[%x] : wptr low\n"); ++ u16Reg2 = REGR(nBaseAddr, 0x45, "[%x] reg[%x] : wptr high\n"); ++ oBufSadr = ((u16Reg2 << 16) | u16Reg1) << 2; ++ ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufAdrRchkEn = 0; ++ REGW(nBaseAddr, 0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : write 3b\n"); ++ u16Reg1 = REGR(nBaseAddr, 0x44, "[%x] reg[%x] : wptr low\n"); ++ u16Reg2 = REGR(nBaseAddr, 0x45, "[%x] reg[%x] : wptr high\n"); ++ wptr = ((u16Reg2 << 16) | u16Reg1) << 2; ++ ++ u16Reg3 = REGR(nBaseAddr, 0x42, "[%x] reg[%x] : last bytes in miu\n"); ++ ++ u16Reg3 &= 3; ++ u16Reg3 += 1; ++ ++ return wptr - oBufSadr + u16Reg3; ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeSetOutBuf ++ * Set output buffer ++ * ++ * Parameters: ++ * addr: physical address ++ * id: index of addres ++ * 0: start of 1st address ++ * 1: end of 1st address ++ * 2: start of 2nd address ++ * 3: end of 2nd address ++ * ++ * Return: ++ * none ++ */ ++static void __HalJpeSetOutBuf(u32 nBaseAddr, JpeReg_t* pJpeReg, u32 addr, u32 id) ++{ ++ addr = Chip_Phys_to_MIU(addr); ++ ++ // Write address info ++ pJpeReg->uReg3c.tReg3c.nRegJpeSBspobufAdrLow = (addr >> 2) & 0xFFFF; ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufAdrHigh = addr >> (2 + 16); ++ pJpeReg->uReg3d.tReg3d.nRegJpeSBspobufId = id; ++ REGW(nBaseAddr, 0x3c, pJpeReg->uReg3c.nReg3c, "[%x] reg[%x] : bsp obuf address: \n"); ++ REGW(nBaseAddr, 0x3d, pJpeReg->uReg3d.nReg3d, "[%x] reg[%x] : bsp obuf address high\n"); ++ ++ // Enable write action? ++ pJpeReg->uReg3e.tReg3e.nRegJpeSBspspobufWriteIdAdr = 1; ++ REGW(nBaseAddr, 0x3e, pJpeReg->uReg3e.nReg3e, "[%x] reg[%x] : bsp obuf write id address: \n"); ++ ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeSetOutBuf ++ * Config input & output address ++ * ++ * Parameters: ++ * ptBufCfg: ??? ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSetOutBuf(u32 nBaseAddr, JpeReg_t* pJpeReg, JpeHalOutBufCfg_t *pOutBufCfg) ++{ ++ // Start to config Output buffer ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspFdcOffset = pOutBufCfg->nJpeOutBitOffset; ++#if defined(ADD_JPDE_0_1) ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf0Status = 0; ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufToggleObuf1Status = 0; ++ ++ // Start to config output buffer (write one clear) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr, 0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; // HW is write-one-clear ++#endif ++ ++ ++ // Set 1st address ++ if(pOutBufCfg->nOutBufAddr[0] != 0 && pOutBufCfg->nOutBufSize[0] != 0) ++ { ++ //JPE_MSG(JPE_MSG_DEBUG, "Set[0] 0x%08X, size %d\n", ptOutBufCfg->nOutBufAddr[0], ptOutBufCfg->nOutBufSize[0]); ++ __HalJpeSetOutBuf(nBaseAddr, pJpeReg, pOutBufCfg->nOutBufAddr[0], 0); ++ __HalJpeSetOutBuf(nBaseAddr, pJpeReg, pOutBufCfg->nOutBufAddr[0] + pOutBufCfg->nOutBufSize[0] - 1, 1); ++ ++ } ++ ++ // Set 2nd address ++ if(pOutBufCfg->nOutBufAddr[1] != 0 && pOutBufCfg->nOutBufSize[1] != 0) ++ { ++ //JPE_MSG(JPE_MSG_DEBUG, "Set[1] 0x%08X, size %d\n", ptOutBufCfg->nOutBufAddr[1], ptOutBufCfg->nOutBufSize[1]); ++ __HalJpeSetOutBuf(nBaseAddr, pJpeReg, pOutBufCfg->nOutBufAddr[1], 2); ++ __HalJpeSetOutBuf(nBaseAddr, pJpeReg, pOutBufCfg->nOutBufAddr[1] + pOutBufCfg->nOutBufSize[1] - 1, 3); ++ } ++ ++ // Set configured address ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 1; ++ REGW(nBaseAddr, 0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : buffer mode\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeSBspobufSetAdr = 0; // HW is write-one-clear ++ ++#if defined(ADD_JPDE_0_1) ++ // Stop configuring output buffer (write one clear) ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 1; ++ REGW(nBaseAddr, 0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : bsp obuf update adr\n"); ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufUpdateAdr = 0; // HW is write-one-clear ++#endif ++} ++ ++ ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++// // ++// Quntization Tables Setting // ++// // ++////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++/******************************************************************************************************************* ++ * _HalJpeQTableEntryRead ++ * Read a entry of Q table ++ * ++ * Parameters: ++ * index: Q table index ++ * value: the pointer of value address ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++static int _HalJpeQTableEntryRead(JpeReg_t* pJpeReg, u32 nBaseAddr, u16 index, u16 *value) ++{ ++ int retry = TIME_OUT_CNT; ++ ++ ++ //read data ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcRw = 0; ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 1; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcAdr = index; ++ REGW(nBaseAddr, 0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table address\n"); ++ REGW(nBaseAddr, 0x48, pJpeReg->uReg48.nReg48, "[%x] reg[%x] : table read enable\n"); ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 0; // write one clear ++ ++ while(retry-- > 0) ++ { ++ pJpeReg->uReg49.nReg49 = REGR(nBaseAddr, 0x49, "[%x] reg[%x] : table write enable\n"); ++ if(pJpeReg->uReg49.tReg49.nRegJpeSTbcDone) ++ { ++ // Clear done ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 1; ++ REGW(nBaseAddr, 0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 0; ++ ++ // Get value ++ *value = REGR(nBaseAddr, 0x4b, "[%x] reg[%x] : table read enable\n"); ++ break; ++ } ++ } ++ ++ return retry; ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeQTableEntryWrite ++ * Write a entry of Q table ++ * ++ * Parameters: ++ * index: Q table index ++ * value: Quantization value ++ * ++ * Return: ++ * >=0: success ++ * <=0: failed ++ */ ++static int _HalJpeQTableEntryWrite(JpeReg_t* pJpeReg, u32 nBaseAddr, u16 index, u16 value) ++{ ++ int retry = TIME_OUT_CNT; ++ ++ // Set value ++ pJpeReg->uReg4a.tReg4a.nRegJpeSTbcWdata = value; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcRw = 1; ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 1; ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcAdr = index; ++ REGW(nBaseAddr, 0x4a, pJpeReg->uReg4a.nReg4a, "[%x] reg[%x] : table write data\n"); ++ REGW(nBaseAddr, 0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table address\n"); ++ REGW(nBaseAddr, 0x48, pJpeReg->uReg48.nReg48, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg48.tReg48.nRegJpeSTbcEn = 0; // write one clear ++ ++ // Wait for set done ++ while(retry-- > 0) ++ { ++ pJpeReg->uReg49.nReg49 = REGR(nBaseAddr, 0x49, "[%x] reg[%x] : table write enable\n"); ++ if(pJpeReg->uReg49.tReg49.nRegJpeSTbcDone) ++ { ++ // Clear done ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 1; ++ REGW(nBaseAddr, 0x49, pJpeReg->uReg49.nReg49, "[%x] reg[%x] : table write enable\n"); ++ pJpeReg->uReg49.tReg49.nRegJpeSTbcDoneClr = 0; ++ break; ++ } ++ } ++ ++ return retry; ++} ++ ++ ++/******************************************************************************************************************* ++ * _HalJpeSetQTable ++ * Update Q table ++ * ++ * Parameters: ++ * q_table_y: Q table for Y ++ * q_table_c: Q table for CbCr ++ * size: table size ++ * ++ * Return: ++ * >=0: success ++ = <0: failed ++ */ ++int _HalJpeSetQTable(u32 nBaseAddr, JpeReg_t* pJpeReg, const u16 *q_table_y, const u16 *q_table_c, u32 size) ++{ ++ u16 value_w, value_r; ++ int i, retry, ret = 0; ++ ++ // Switch SW mode to update Q table ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 0; ++ REGW(nBaseAddr, 0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=0\n"); ++ ++ ++ // Udate Y table ++ for(i = 0; i < size; i++) ++ { ++ retry = TIME_OUT_CNT; ++ while(retry-- > 0) ++ { ++ value_w = q_table_y[((i & 0x7) << 3) | (i >> 3)]; ++ ++ // Write ++ if(_HalJpeQTableEntryWrite(pJpeReg, nBaseAddr, i, value_w) <= 0) ++ { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg, nBaseAddr, i, &value_r) <= 0) ++ { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Compare ++ if(value_r == value_w) ++ break; ++ } ++ } ++ ++ // Udate C table ++ for(i = 0; i < size; i++) ++ { ++ retry = TIME_OUT_CNT; ++ while(retry-- > 0) ++ { ++ value_w = q_table_c[((i & 0x7) << 3) | (i >> 3)]; ++ ++ // Write ++ if(_HalJpeQTableEntryWrite(pJpeReg, nBaseAddr, i + 64, value_w) <= 0) ++ { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Read ++ if(_HalJpeQTableEntryRead(pJpeReg, nBaseAddr, i + 64, &value_r) <= 0) ++ { ++ ret = -1; ++ goto RETURN; ++ } ++ ++ // Compare ++ if(value_r == value_w) ++ break; ++ } ++ } ++ ++ // update Index last identyfier ++ // The default size of Quantization table is 64, but JPE can accept that size smaller than 64 and ++ // treat others as 0 ( I guess...) ++ pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxLast = size; ++ pJpeReg->uReg2c.tReg2c.nRegJpeSQuanIdxSwlast = (size < 63) ? 1 : 0; ++ REGW(nBaseAddr, 0x2c, pJpeReg->uReg2c.nReg2c, "[%x] reg[%x] : Last zigzag\n"); ++ ++RETURN: ++ // Switch to hw mode ++ pJpeReg->uReg03.tReg03.nRegJpeGTbcMode = 1; ++ REGW(nBaseAddr, 0x3, pJpeReg->uReg03.nReg03, "[%x] reg[%x] : tbc_mode=1\n"); ++ ++ return ret; ++} ++ ++ ++/******************************************************************************************************************* ++ * HalJpeSetInBuf ++ * Config input & output address ++ * ++ * Parameters: ++ * ptInBufCfg: Input buffer configuration ++ * ++ * Return: ++ * none ++ */ ++static void _HalJpeSetInBuf(JpeHalHandle_t* handle, pJpeHalInBufCfg ptInBufCfg) ++{ ++ u32 addr; ++ u32 nBaseAddr = handle->nBaseAddr; ++ JpeReg_t* pJpeReg = &handle->tJpeReg; ++ ++ // Y0 ++ if(ptInBufCfg->nInBufYAddr[0]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufYAddr[0]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ ++ pJpeReg->uReg06.tReg06.nRegJpeGBufYAdr0Low = (addr >> 8) & 0xFFFF; ++ pJpeReg->uReg07.tReg07.nRegJpeGBufYAdr0High = addr >> (8 + 16); ++ ++ // Y1 ++ if(ptInBufCfg->nInBufYAddr[1]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufYAddr[1]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ pJpeReg->uReg08.tReg08.nRegJpeGBufYAdr1Low = (addr >> 8) & 0xFFFF; ++ pJpeReg->uReg09.tReg09.nRegJpeGBufYAdr1High = addr >> (8 + 16); ++ ++ // C0 ++ if(ptInBufCfg->nInBufCAddr[0]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufCAddr[0]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ pJpeReg->uReg0a.tReg0a.nRegJpeGBufCAdr0Low = (addr >> 8) & 0xFFFF; ++ pJpeReg->uReg0b.tReg0b.nRegJpeGBufCAdr0High = addr >> (8 + 16); ++ ++ // C1 ++ if(ptInBufCfg->nInBufCAddr[1]) ++ { ++ addr = Chip_Phys_to_MIU(ptInBufCfg->nInBufCAddr[1]); ++ } ++ else ++ { ++ addr = 0; ++ } ++ pJpeReg->uReg0c.tReg0c.nRegJpeGBufCAdr1Low = (addr >> 8) & 0xFFFF; ++ pJpeReg->uReg0d.tReg0d.nRegJpeGBufCAdr1High = addr >> (8 + 16); ++ ++ // Input buffers ++ // ++ REGW(nBaseAddr, 0x06, pJpeReg->uReg06.nReg06, "[%x] reg[%x] : Y0_low\n"); ++ REGW(nBaseAddr, 0x07, pJpeReg->uReg07.nReg07, "[%x] reg[%x] : Y0_high\n"); ++ REGW(nBaseAddr, 0x08, pJpeReg->uReg08.nReg08, "[%x] reg[%x] : Y1_low\n"); ++ REGW(nBaseAddr, 0x09, pJpeReg->uReg09.nReg09, "[%x] reg[%x] : Y1 high\n"); ++ REGW(nBaseAddr, 0x0a, pJpeReg->uReg0a.nReg0a, "[%x] reg[%x] : C0_low\n"); ++ REGW(nBaseAddr, 0x0b, pJpeReg->uReg0b.nReg0b, "[%x] reg[%x] : C0_high\n"); ++ REGW(nBaseAddr, 0x0c, pJpeReg->uReg0c.nReg0c, "[%x] reg[%x] : C1_low\n"); ++ REGW(nBaseAddr, 0x0d, pJpeReg->uReg0d.nReg0d, "[%x] reg[%x] : C1_high\n"); ++} ++ ++static void _Release(void* pIosIn) ++{ ++ JpeIos_t* pIos = pIosIn; ++ if(pIos) ++ { ++ CamOsMemRelease((void*)pIos); ++ } ++} ++ ++static JPE_IOC_RET_STATUS_e _SetBank(void* pIosIn, JpeRegIndex_t* pReg) ++{ ++ int err = JPE_IOC_RET_SUCCESS; ++ JpeIos_t* pIos = pIosIn; ++ ++ if((!pIos) || (!pReg)) ++ return JPE_IOC_RET_FAIL; ++ ++ switch(pReg->i_id) ++ { ++ case 0: ++ pIos->nBaseAddr = (u32)pReg->base; ++ //pIos->tJpeHalHandle.nBaseAddr = (u32)pReg->base; ++ //pIos->tJpeHalHandle.nSize = pReg->size; // should be 0x100 ++ break; ++ default: ++ err = JPE_IOC_RET_FAIL; ++ break; ++ } ++ return err; ++} ++ ++ ++static JPE_IOC_RET_STATUS_e _EncFire(void* pIosIn, void* pJpeHalHandleIn, JpeJob_t* pJob) ++{ ++ JpeIos_t* pIos = (JpeIos_t*)pIosIn; ++ JpeHalHandle_t *pJpeHalHandle = pJpeHalHandleIn; ++ ++ u32 nBaseAddr = pIos->nBaseAddr; ++ ++ JpeHalOutBufCfg_t *pJpeHalOutBufCfg = &pJpeHalHandle->tJpeHalOutBufCfg; ++ u16 *pYQTable = pJpeHalHandle->YQTable; ++ u16 *pCQTable = pJpeHalHandle->CQTable; ++ JpeReg_t* pJpeReg = (JpeReg_t*)pJob; ++ ++ pJpeHalHandle->nBaseAddr = nBaseAddr; ++ pJpeHalHandle->nSize = 0x100; ++ ++ pIos->eJpeDevStatus = JPE_DEV_BUSY; ++ ++ /* Set interrupt trigger mask, and only 3 bits are meaningful */ ++ pJpeReg->uReg1c.tReg1c.nRegJpeGIrqMask = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg, 0); ++ REGW(nBaseAddr, 0x1c, pJpeReg->uReg1c.nReg1c, "[%x] reg[%x] : irq mask\n"); ++ ++ ++ /* Enable JPEG engine */ ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 1; ++ REGW(nBaseAddr, 0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : frame start\n"); ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 0; // write-one-clear ++ ++ ++ /* Set Clock */ ++#if defined(__I_SW__) ++ REGW(REG_CKG_JPE_BASE, 0x00, pJpeReg->regClk, "Set Clk\n"); ++#endif ++ ++ /* Reset JPEG engine */ ++ // SW reset at first ++ pJpeReg->uReg00.tReg00.nRegJpeGMode = 0; // Assure JPE is running. ++ pJpeReg->uReg00.tReg00.nRegJpeGSoftRstz = 0; ++ REGW(nBaseAddr, 0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ // delay for lower MCM frequence ++ // Repeated write to replace udelay(1) becase 1 us is too long ++ REGW(nBaseAddr, 0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr, 0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr, 0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ REGW(nBaseAddr, 0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 0\n"); ++ pJpeReg->uReg00.tReg00.nRegJpeGSoftRstz = 1; ++ REGW(nBaseAddr, 0x0, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : SW reset 1\n"); ++ ++ ++ // Sync all HW setting to jpeg register ++#define _UPDATE_REG_VAR(nBaseAddr,reg_no) pJpeReg->uReg##reg_no.nReg##reg_no = REGR(nBaseAddr,0x##reg_no, "\n");//REGR(0x##reg_no, "\n"); ++ _UPDATE_REG_VAR(nBaseAddr, 00); ++ _UPDATE_REG_VAR(nBaseAddr, 01); ++ _UPDATE_REG_VAR(nBaseAddr, 02); ++ _UPDATE_REG_VAR(nBaseAddr, 03); ++ _UPDATE_REG_VAR(nBaseAddr, 06); ++ _UPDATE_REG_VAR(nBaseAddr, 07); ++ _UPDATE_REG_VAR(nBaseAddr, 08); ++ _UPDATE_REG_VAR(nBaseAddr, 09); ++ _UPDATE_REG_VAR(nBaseAddr, 0a); ++ _UPDATE_REG_VAR(nBaseAddr, 0b); ++ _UPDATE_REG_VAR(nBaseAddr, 0c); ++ _UPDATE_REG_VAR(nBaseAddr, 0d); ++ _UPDATE_REG_VAR(nBaseAddr, 0f); ++ _UPDATE_REG_VAR(nBaseAddr, 10); ++ _UPDATE_REG_VAR(nBaseAddr, 16); ++ _UPDATE_REG_VAR(nBaseAddr, 18); ++ _UPDATE_REG_VAR(nBaseAddr, 1c); ++ _UPDATE_REG_VAR(nBaseAddr, 1d); ++ _UPDATE_REG_VAR(nBaseAddr, 1e); ++ _UPDATE_REG_VAR(nBaseAddr, 1f); ++ _UPDATE_REG_VAR(nBaseAddr, 20); ++ _UPDATE_REG_VAR(nBaseAddr, 21); ++ _UPDATE_REG_VAR(nBaseAddr, 2c); ++ _UPDATE_REG_VAR(nBaseAddr, 2d); ++ _UPDATE_REG_VAR(nBaseAddr, 2e); ++ _UPDATE_REG_VAR(nBaseAddr, 32); ++ _UPDATE_REG_VAR(nBaseAddr, 33); ++ _UPDATE_REG_VAR(nBaseAddr, 34); ++ _UPDATE_REG_VAR(nBaseAddr, 35); ++ _UPDATE_REG_VAR(nBaseAddr, 36); ++ _UPDATE_REG_VAR(nBaseAddr, 3b); ++ _UPDATE_REG_VAR(nBaseAddr, 3c); ++ _UPDATE_REG_VAR(nBaseAddr, 3d); ++ _UPDATE_REG_VAR(nBaseAddr, 3e); ++ _UPDATE_REG_VAR(nBaseAddr, 42); ++ _UPDATE_REG_VAR(nBaseAddr, 44); ++ _UPDATE_REG_VAR(nBaseAddr, 45); ++ _UPDATE_REG_VAR(nBaseAddr, 48); ++ _UPDATE_REG_VAR(nBaseAddr, 49); ++ _UPDATE_REG_VAR(nBaseAddr, 4a); ++ _UPDATE_REG_VAR(nBaseAddr, 4b); ++ _UPDATE_REG_VAR(nBaseAddr, 54); ++ _UPDATE_REG_VAR(nBaseAddr, 55); ++ _UPDATE_REG_VAR(nBaseAddr, 56); ++ _UPDATE_REG_VAR(nBaseAddr, 57); ++ _UPDATE_REG_VAR(nBaseAddr, 58); ++ _UPDATE_REG_VAR(nBaseAddr, 59); ++ _UPDATE_REG_VAR(nBaseAddr, 5a); ++ _UPDATE_REG_VAR(nBaseAddr, 5b); ++ _UPDATE_REG_VAR(nBaseAddr, 5c); ++ _UPDATE_REG_VAR(nBaseAddr, 5d); ++ _UPDATE_REG_VAR(nBaseAddr, 5e); ++ _UPDATE_REG_VAR(nBaseAddr, 5f); ++ _UPDATE_REG_VAR(nBaseAddr, 60); ++ _UPDATE_REG_VAR(nBaseAddr, 61); ++ _UPDATE_REG_VAR(nBaseAddr, 64); ++ _UPDATE_REG_VAR(nBaseAddr, 6f); ++ _UPDATE_REG_VAR(nBaseAddr, 70); ++ _UPDATE_REG_VAR(nBaseAddr, 71); ++ _UPDATE_REG_VAR(nBaseAddr, 72); ++ _UPDATE_REG_VAR(nBaseAddr, 73); ++ _UPDATE_REG_VAR(nBaseAddr, 74); ++ _UPDATE_REG_VAR(nBaseAddr, 75); ++ _UPDATE_REG_VAR(nBaseAddr, 76); ++ _UPDATE_REG_VAR(nBaseAddr, 77); ++ _UPDATE_REG_VAR(nBaseAddr, 78); ++ _UPDATE_REG_VAR(nBaseAddr, 79); ++ _UPDATE_REG_VAR(nBaseAddr, 7a); ++ _UPDATE_REG_VAR(nBaseAddr, 7b); ++ _UPDATE_REG_VAR(nBaseAddr, 7c); ++ ++ ++ /* Config the operation mode of output buffer */ ++ pJpeReg->uReg3b.tReg3b.nRegJpeObufHwEn = JPE_HAL_OBUF_SINGLE_MODE; ++ REGW(nBaseAddr, 0x3b, pJpeReg->uReg3b.nReg3b, "[%x] reg[%x] : output buffer mode\n"); ++ ++ ++ /* Config output address */ ++ _HalJpeSetOutBuf(nBaseAddr, pJpeReg, pJpeHalOutBufCfg); ++ ++ ++ /* Clear IRQ */ ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr, 0x1d, "[%x] reg[%x] :IRQ register\n"); ++ pJpeReg->uReg1d.tReg1d.nRegJpeGIrqClr = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg, JPE_HAL_IRQ_ALL); ++ REGW(nBaseAddr, 0x1d, pJpeReg->uReg1d.nReg1d, "[%x] reg[%x] : Clear IRQ\n"); ++ pJpeReg->uReg1d.nReg1d = REGR(nBaseAddr, 0x1d, "[%x] reg[%x] :IRQ register\n"); // HW is write-one-clear, so update again ++ ++ ++ /* Set image dimension */ ++ //_HalJpeSetPicDim(pJpeHalHandle, pJpeHalHandle->nWidth, pJpeHalHandle->nHeight); ++ pJpeReg->uReg01.tReg01.nRegJpeGPicWidth = pJpeHalHandle->nWidth; // (width+15)&~15; ++ pJpeReg->uReg02.tReg02.nRegJpeGPicHeight = (u16)((pJpeHalHandle->nHeight + 7) & ~7); ++ pJpeReg->uReg5e.tReg5e.nRegGJpeYPitch = (u16)((pJpeHalHandle->nWidth + 15) >> 4); ++ pJpeReg->uReg5e.tReg5e.nRegGJpeCPitch = (u16)((pJpeHalHandle->nWidth + 15) >> 4); ++ REGW(nBaseAddr, 0x01, pJpeReg->uReg01.nReg01, "[%x] reg[%x] : picture width\n"); ++ REGW(nBaseAddr, 0x02, pJpeReg->uReg02.nReg02, "[%x] reg[%x] : picture height\n"); ++ REGW(nBaseAddr, 0x5E, pJpeReg->uReg5e.nReg5e, "[%x] reg[%x] : picture pitch\n"); ++ ++ /* Set codec mode */ ++ pJpeReg->uReg00.tReg00.nRegJpeGEncMode = 0; ++ pJpeReg->uReg00.tReg00.nRegJpeGDctOnlyEn = 0; ++ REGW(nBaseAddr, 0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : Codec mode\n"); ++ ++ ++ /* Config the RAW format for HW codec */ ++ switch(pJpeHalHandle->nRawFormat) ++ { ++ case JPE_HAL_RAW_YUYV: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 1; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 0; ++ break; ++ ++ case JPE_HAL_RAW_YVYU: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 1; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 1; ++ break; ++ ++ case JPE_HAL_RAW_NV12: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 0; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 0; ++ break; ++ ++ case JPE_HAL_RAW_NV21: ++ pJpeReg->uReg00.tReg00.nRegJpeGEncFormat = 0; ++ pJpeReg->uReg5f.tReg5f.nRegSJpeYuvldrCWwap = 1; ++ break; ++ } ++ REGW(nBaseAddr, 0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : YUV format\n"); ++ REGW(nBaseAddr, 0x5F, pJpeReg->uReg5f.nReg5f, "[%x] reg[%x] : YUV format\n"); ++ ++ ++ /* Config the operation mode of input buffer */ ++ //HalJpeSetInputMode(pJpeHalHandle, pJpeHalHandle->nInBufMode); ++ if(pJpeHalHandle->nInBufMode == JPE_HAL_BUFFER_ROW_MODE) ++ pJpeReg->uReg18.tReg18.nRegJpeGJpeBuffermode = 0; ++ else ++ pJpeReg->uReg18.tReg18.nRegJpeGJpeBuffermode = 1; ++ REGW(nBaseAddr, 0x18, pJpeReg->uReg18.nReg18, "[%x] reg[%x] : input buffer mode\n"); ++ ++ ++ /* Quantization table */ ++ if(_HalJpeSetQTable(nBaseAddr, pJpeReg, pYQTable, pCQTable, 64) != 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "HalJpeSetQTable fail, y_table=%p, c_table=%p\n", pYQTable, pCQTable); ++ JPE_MSG(JPE_MSG_ERR, "pJpeHalHandle->nBaseAddr=0x%x, tJpeReg=%p\n", nBaseAddr, pJpeReg); ++ return JPE_IOC_RET_BAD_QTABLE; ++ } ++ ++ /* Config input address*/ ++ _HalJpeSetInBuf(pJpeHalHandle, &pJpeHalHandle->tJpeHalInBufCfg); ++ ++ ++ /* Remvoe IRQ mask, and only 3 bits are meaningful */ ++ pJpeReg->uReg1c.tReg1c.nRegJpeGIrqMask = _HalJpeIrqMaskConvertEnumerate2Real(pJpeReg, 0); ++ REGW(nBaseAddr, 0x1c, pJpeReg->uReg1c.nReg1c, "[%x] reg[%x] : irq mask\n"); ++ ++ ++ /* Enable HW */ ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 1; ++ REGW(nBaseAddr, 0x00, pJpeReg->uReg00.nReg00, "[%x] reg[%x] : frame start\n"); ++ pJpeReg->uReg00.tReg00.nRegJpeGFrameStartSw = 0; // write-one-clear ++ ++ JPE_MSG(JPE_MSG_DEBUG, "[out] %s\n", __func__); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++ ++static JPE_IOC_RET_STATUS_e _IsrFunc(void* pIosIn, int msk) ++{ ++ JpeIos_t* pIos = (JpeIos_t*)pIosIn; ++ ++ u32 nBaseAddr = pIos->nBaseAddr; ++ JpeReg_t* pJpeReg = &pIos->tJpeReg; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "Interrupt: 0x%x\n", _HalJpeGetIrq(nBaseAddr)); ++ ++ /* JPE_IRQ_BSPOBUF_FULL */ ++ if(_HalJpeGetIrqCheck(nBaseAddr, pJpeReg, JPE_HAL_IRQ_BSPOBUF0_FULL)) ++ { ++ /* Status update */ ++ pIos->nEncodeSize = _HalJpeGetOutputByteSize(nBaseAddr, pJpeReg, 0); ++ pIos->eJpeDevStatus = JPE_DEV_OUTBUF_FULL; ++ ++ /* Clear IRQ */ ++ _HalJpeClearIrq(nBaseAddr, pJpeReg, JPE_HAL_IRQ_BSPOBUF0_FULL); ++ } ++ ++ /* JPE_IRQ_BSPOBUF1_FULL */ ++ else if(_HalJpeGetIrqCheck(nBaseAddr, pJpeReg, JPE_HAL_IRQ_BSPOBUF1_FULL)) ++ { ++ /* Status update */ ++ pIos->nEncodeSize = _HalJpeGetOutputByteSize(nBaseAddr, pJpeReg, 1); ++ pIos->eJpeDevStatus = JPE_DEV_OUTBUF_FULL; ++ ++ /* Clear IRQ */ ++ _HalJpeClearIrq(nBaseAddr, pJpeReg, JPE_HAL_IRQ_BSPOBUF1_FULL); ++ } ++ ++ /* JPE_IRQ_FRAME_DONE */ ++ else if(_HalJpeGetIrqCheck(nBaseAddr, pJpeReg, JPE_HAL_IRQ_FRAME_DONE)) ++ { ++ /* Status update */ ++ pIos->nEncodeSize = _HalJpeGetOutputByteSize(nBaseAddr, pJpeReg, 0); ++ pIos->eJpeDevStatus = JPE_DEV_ENC_DONE; ++ ++ /* Clear IRQ */ ++ _HalJpeClearIrq(nBaseAddr, pJpeReg, JPE_HAL_IRQ_FRAME_DONE); ++ } ++ else ++ { ++ u16 nIrq; ++ nIrq = _HalJpeGetIrq(nBaseAddr); ++ JPE_MSG(JPE_MSG_ERR, "Unexpect Interrupt: 0x%x size:%d ejpeDevStatus:%d\n", nIrq, pIos->nEncodeSize, pIos->eJpeDevStatus); ++ _HalJpeClearIrq(nBaseAddr, pJpeReg, JPE_HAL_IRQ_FRAME_DONE); ++ } ++ ++ JPE_MSG(JPE_MSG_DEBUG, "Interrupt: %X size:%d ejpeDevStatus:%d\n", _HalJpeGetIrq(nBaseAddr), pIos->nEncodeSize, pIos->eJpeDevStatus); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++ ++static JPE_IOC_RET_STATUS_e _IrqMask(void* pIosIn, int nMask) ++{ ++ JpeIos_t* pIos = (JpeIos_t*)pIosIn; ++ ++ u32 nBaseAddr = pIos->nBaseAddr; ++ JpeReg_t* pJpeReg = &pIos->tJpeReg; ++ ++ _HalJpeClearIrq(nBaseAddr, pJpeReg, nMask); ++ _HalJpeSetIrqMask(nBaseAddr, pJpeReg, nMask); ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++ ++JpeIosCB_t* JpeIosAcquire(char* tags) ++{ ++ JpeIos_t* pIos = NULL; ++ if(!tags) ++ return NULL; ++ ++ pIos = ((JpeIos_t *)CamOsMemCalloc(1, sizeof(JpeIos_t))); ++ if(pIos) ++ { ++ JpeIosCB_t* mios = &pIos->mios; ++ mios->release = _Release; ++ mios->setBank = _SetBank; ++ mios->encFire = _EncFire; ++ mios->isrFunc = _IsrFunc; ++ mios->irqMask = _IrqMask; ++ ++ // TODO: remove tJpeReg ++ memset(&pIos->tJpeReg, 0, sizeof(JpeReg_t)); ++ } ++ return (JpeIosCB_t*)pIos; ++} +diff --git a/drivers/mstar/jpe2/hal/src/hal_jpe_ops.c b/drivers/mstar/jpe2/hal/src/hal_jpe_ops.c +new file mode 100644 +index 00000000..6363142e +--- /dev/null ++++ b/drivers/mstar/jpe2/hal/src/hal_jpe_ops.c +@@ -0,0 +1,350 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2017 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include "hal_jpe_ios.h" ++#include "hal_jpe_ops.h" ++ ++#ifndef ARRAY_SIZE // include/linux/kernel.h already defined this macro ++#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0])) ++#endif ++ ++#define TIME_OUT_CNT 10 ++#define QTABLE_MAX 255 ++#define QTABLE_MIN 1 ++ ++#ifndef _MAX ++#define _MAX(a,b) ((a)>(b)?(a):(b)) ++#endif ++#ifndef _MIN ++#define _MIN(a,b) ((a)<(b)?(a):(b)) ++#endif ++ ++static JPE_IOC_RET_STATUS_e _JpeCheckCfg(JpeCfg_t *pCfg) ++{ ++ int align; ++ ++ // Support JPEG only ++ if(pCfg->eCodecFormat != JPE_CODEC_JPEG) ++ return JPE_IOC_RET_FMT_NOT_SUPPORT; ++ ++ // Alignment check ++ align = (pCfg->eRawFormat == JPE_RAW_NV12 || pCfg->eRawFormat == JPE_RAW_NV21) ? 16 : 8; ++ if(pCfg->nWidth % align) ++ { ++ JPE_MSG(JPE_MSG_ERR, "source width is not aligned to %d\n", align); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ if(pCfg->nHeight % align) ++ { ++ JPE_MSG(JPE_MSG_ERR, "source height is not aligned to %d\n", align); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ // Input buffer check ++ if(pCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr == 0 || pCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize == 0) ++ { ++ JPE_MSG(JPE_MSG_ERR, "Input buffer is not assigned\n"); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ // Output buffer check ++ if(pCfg->OutBuf.nAddr == 0 || pCfg->OutBuf.nSize == 0) ++ { ++ // When jpeg init, user can provide a empty output buffer. ++ //JPE_MSG(JPE_MSG_ERR, "Output buffer is not assigned\n"); ++ return JPE_IOC_RET_BAD_OUTBUF; ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++static JPE_IOC_RET_STATUS_e _JpeSetInBuf(JpeHalHandle_t* pJpeHalHandle, JpeCfg_t *pJpeCfg) ++{ ++ u32 size; ++ JpeHalInBufCfg_t *pInBufCfg = &pJpeHalHandle->tJpeHalInBufCfg; ++ ++ JPE_MSG(JPE_MSG_DEBUG, "set 0x%08lX, size %ld as input buffer\n", pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr, pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize); ++ ++ // Set input buffer ++ switch(pJpeCfg->eRawFormat) ++ { ++ case JPE_RAW_YUYV: ++ case JPE_RAW_YVYU: ++ if(pJpeCfg->eInBufMode == JPE_IBUF_FRAME_MODE) ++ { ++ pInBufCfg->nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ pInBufCfg->nInBufYAddr[1] = 0; ++ pInBufCfg->nInBufCAddr[0] = 0; ++ pInBufCfg->nInBufCAddr[1] = 0; ++ } ++ else if(pJpeCfg->eInBufMode == JPE_IBUF_ROW_MODE) ++ { ++ // Assume the user allocate big enough buffer and scaler also follow the same order ++ // If not, we may change the IF to follow the behavior of scaler ++ size = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize / 2; ++ pInBufCfg->nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ pInBufCfg->nInBufYAddr[1] = pInBufCfg->nInBufYAddr[0] + size; ++ pInBufCfg->nInBufCAddr[0] = 0; ++ pInBufCfg->nInBufCAddr[1] = 0; ++ } ++ else ++ { ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ break; ++ case JPE_RAW_NV12: ++ case JPE_RAW_NV21: ++ if(pJpeCfg->eInBufMode == JPE_IBUF_FRAME_MODE) ++ { ++ pInBufCfg->nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ pInBufCfg->nInBufYAddr[1] = 0; ++ pInBufCfg->nInBufCAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr; ++ pInBufCfg->nInBufCAddr[1] = 0; ++ } ++ else if(pJpeCfg->eInBufMode == JPE_IBUF_ROW_MODE) ++ { ++ // TODO: the luma size seems incorrect ++ // For YUV420P (NV12 or NV21) ++ // luma should be InBuf[JPE_COLOR_PLAN_LUMA].nSize ++ // chroma should be InBuf[JPE_COLOR_PLAN_CHROMA].nSize/2 (U+V) ++ ++ // Assume the user allocate big enough buffer and scaler also follow the same order ++ // If not, we may change the IF to follow the behavior of scaler ++ size = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nSize / 4; ++ pInBufCfg->nInBufYAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_LUMA].nAddr; ++ pInBufCfg->nInBufYAddr[1] = pInBufCfg->nInBufYAddr[0] + size; ++ pInBufCfg->nInBufCAddr[0] = pJpeCfg->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr; ++ pInBufCfg->nInBufCAddr[1] = pInBufCfg->nInBufCAddr[0] + size; ++ } ++ else ++ { ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ break; ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++static JPE_IOC_RET_STATUS_e _JpeSetQTable(JpeHalHandle_t* pJpeHalHandle, const u16 *q_table_y, const u16 *q_table_c, u32 size, const u16 q_scale) ++{ ++ u16 *pYTable, *pCTable; ++ JPE_IOC_RET_STATUS_e ret = JPE_IOC_RET_SUCCESS; ++ int i; ++ ++ if(!pJpeHalHandle) ++ return JPE_IOC_RET_FAIL; ++ ++ pYTable = pJpeHalHandle->YQTable; ++ pCTable = pJpeHalHandle->CQTable; ++ ++ for(i = 0; i < size; i++) ++ { ++ pYTable[i] = (u16)(((u32)q_table_y[i] * (u32)q_scale + 50) / 100); ++ //pYTable[i] = pYTable[i] ? pYTable[i] : 1; ++ pYTable[i] = _MAX(QTABLE_MIN, _MIN(pYTable[i], QTABLE_MAX)); ++ pCTable[i] = (u16)(((u32)q_table_c[i] * (u32)q_scale + 50) / 100); ++ //pCTable[i] = pCTable[i] ? pCTable[i] : 1; ++ pCTable[i] = _MAX(QTABLE_MIN, _MIN(pCTable[i], QTABLE_MAX)); ++ } ++ ++ return ret; ++} ++ ++static void* _JpeJob(JpeOpsCB_t* mops) ++{ ++ JpeOps_t* pJpeOps = (JpeOps_t*)mops; ++ ++ return &(pJpeOps->tJpeHalHandle.tJpeReg); ++} ++ ++static void _OpsFree(JpeOpsCB_t* mops) ++{ ++ CamOsMemRelease((void*)mops); ++} ++ ++static JPE_IOC_RET_STATUS_e _Init(JpeOpsCB_t* pJpeOpsCBIn, JpeCfg_t* pJpeCfgIn) ++{ ++ JPE_IOC_RET_STATUS_e eStatus = JPE_IOC_RET_SUCCESS; ++ ++ if(!pJpeCfgIn) ++ { ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ eStatus = _JpeCheckCfg(pJpeCfgIn); ++ // The output buffer information can be set latter, when encode frame ++ if((eStatus != JPE_IOC_RET_SUCCESS) && (eStatus != JPE_IOC_RET_BAD_OUTBUF)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "some parameter settings are wrong...\n"); ++ return eStatus; ++ } ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++static JPE_IOC_RET_STATUS_e _GetCaps(JpeOpsCB_t* pOpsCBIn, JpeCaps_t *pCaps) ++{ ++ if(pCaps == 0) ++ { ++ return JPE_IOC_RET_BAD_NULLPTR; ++ } ++ ++ pCaps->nBufferModeSupport = JPE_HAL_BUFFER_ROW_MODE | JPE_HAL_BUFFER_FRAME_MODE; ++ pCaps->nCodecSupport = JPE_HAL_CODEC_JPEG; ++ pCaps->nOutBufSLogAddrAlign = 4; ++ pCaps->nRefCLogAddrAlign[0] = 256; ++ pCaps->nRefCLogAddrAlign[1] = 256; ++ pCaps->nRefYLogAddrAlign[0] = 256; ++ pCaps->nRefYLogAddrAlign[1] = 256; ++ pCaps->nSclHandShakeSupport = JPE_HAL_SCL_HANDSHAKE_ON; ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++static JPE_IOC_RET_STATUS_e _SetConf(JpeOpsCB_t* pJpeOpsIn, JpeCfg_t* pJpeCfgIn) ++{ ++ JPE_IOC_RET_STATUS_e ret = JPE_IOC_RET_FAIL; ++ JpeOps_t* pJpeOps = (JpeOps_t*)pJpeOpsIn; ++ JpeHalHandle_t *pJpeHalHandle = &pJpeOps->tJpeHalHandle; ++ JpeHalOutBufCfg_t* pJpeHalOutBufCfg = &pJpeHalHandle->tJpeHalOutBufCfg; ++ ++ JpeReg_t* pJpeReg = &pJpeHalHandle->tJpeReg; ++ ++ if((!pJpeOpsIn) || (!pJpeCfgIn)) ++ { ++ JPE_MSG(JPE_MSG_ERR, "wrong parameters, pJpeOpsIn=%p, pJpeCfgIn=%p\n", pJpeOpsIn, pJpeCfgIn); ++ return JPE_IOC_RET_FAIL; ++ } ++ ++ ret = _JpeCheckCfg(pJpeCfgIn); ++ if(ret != JPE_IOC_RET_SUCCESS) ++ { ++ JPE_MSG(JPE_MSG_ERR, "jpeg encoder config fail\n"); ++ return ret; ++ } ++ ++ ++ /* HW-IP related regs setting */ ++ // set clk ++ ++ // 0: Enable, 1:Disable ++ pJpeReg->regClk_jpe_clock_setting = 0; ++ ++ // The default clock is set to 288MHZ ++ // clk-select = <0>; // 0: 288MHz 1: 216MHz 2: 54MHz 3: 27MHz ++ pJpeReg->regClk_clock_source = pJpeOps->nClkSelect; ++ ++ // Jpeg configuration ++ pJpeHalHandle->nInBufMode = (int)pJpeCfgIn->eInBufMode; ++ pJpeHalHandle->nRawFormat = (int)pJpeCfgIn->eRawFormat; ++ pJpeHalHandle->nCodecFormat = (int)pJpeCfgIn->eCodecFormat; ++ ++ pJpeHalHandle->nWidth = pJpeCfgIn->nWidth; ++ pJpeHalHandle->nHeight = pJpeCfgIn->nHeight; ++ ++ pJpeHalHandle->nQScale = pJpeCfgIn->nQScale; ++ ++ /* Quantization table */ ++ ret = _JpeSetQTable(pJpeHalHandle, pJpeCfgIn->YQTable, pJpeCfgIn->CQTable, ARRAY_SIZE(pJpeCfgIn->YQTable), pJpeCfgIn->nQScale); ++ if(ret != JPE_IOC_RET_SUCCESS) ++ { ++ JPE_MSG(JPE_MSG_ERR, "_JpeSetQTable() fail\n"); ++ return ret; ++ } ++ ++ ++ /* Set input buffer */ ++ if(pJpeCfgIn->InBuf[JPE_COLOR_PLAN_LUMA].nAddr != 0 && pJpeCfgIn->InBuf[JPE_COLOR_PLAN_LUMA].nSize != 0) ++ { ++ _JpeSetInBuf(pJpeHalHandle, pJpeCfgIn); ++ } ++ else ++ { ++ JPE_MSG(JPE_MSG_DEBUG, ++ "Illegal input buffer addr 0x%08lX, size %ld\n", pJpeCfgIn->InBuf[JPE_COLOR_PLAN_LUMA].nAddr, pJpeCfgIn->InBuf[JPE_COLOR_PLAN_LUMA].nSize); ++ return JPE_IOC_RET_BAD_INBUF; ++ } ++ ++ /* Set output buffer */ ++ pJpeHalOutBufCfg->nOutBufAddr[0] = pJpeCfgIn->OutBuf.nAddr; ++ pJpeHalOutBufCfg->nOutBufSize[0] = pJpeCfgIn->OutBuf.nSize; ++ pJpeHalOutBufCfg->nOutBufSize[1] = 0; ++ pJpeHalOutBufCfg->nOutBufAddr[1] = 0; ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++static JPE_IOC_RET_STATUS_e _GetConf(JpeOpsCB_t* pJpeOpsCB, JpeCfg_t* pJpeCfgOut) ++{ ++ JpeOps_t* pJpeOps = (JpeOps_t*)pJpeOpsCB; ++ JpeHalHandle_t* pJpeHalHandle = &pJpeOps->tJpeHalHandle; ++ ++ pJpeCfgOut->eInBufMode = pJpeHalHandle->nInBufMode; ++ pJpeCfgOut->eRawFormat = pJpeHalHandle->nRawFormat; ++ pJpeCfgOut->eCodecFormat = pJpeHalHandle->nCodecFormat; ++ ++ pJpeCfgOut->nWidth = pJpeHalHandle->nWidth; ++ pJpeCfgOut->nHeight = pJpeHalHandle->nHeight; ++ ++ memcpy(pJpeCfgOut->YQTable, pJpeHalHandle->YQTable, sizeof(u16) * 64); ++ memcpy(pJpeCfgOut->CQTable, pJpeHalHandle->CQTable, sizeof(u16) * 64); ++ pJpeCfgOut->nQScale = pJpeHalHandle->nQScale; ++ ++ pJpeCfgOut->InBuf[JPE_COLOR_PLAN_LUMA].nAddr = pJpeHalHandle->tJpeHalInBufCfg.nInBufYAddr[0]; ++ //pJpeCfgOut->InBuf[JPE_COLOR_PLAN_LUMA].nSize = pJpeHalHandle->tJpeHalInBufCfg.nInBufCAddr[0]; ++ pJpeCfgOut->InBuf[JPE_COLOR_PLAN_CHROMA].nAddr = pJpeHalHandle->tJpeHalInBufCfg.nInBufCAddr[0]; ++ //pJpeCfgOut->InBuf[JPE_COLOR_PLAN_CHROMA].nSize = pJpeHalHandle->tJpeHalInBufCfg.nInBufCAddr[1]; ++ ++ pJpeCfgOut->OutBuf.nAddr = pJpeHalHandle->tJpeHalOutBufCfg.nOutBufAddr[0]; ++ pJpeCfgOut->OutBuf.nSize = pJpeHalHandle->tJpeHalOutBufCfg.nOutBufSize[0]; ++ pJpeCfgOut->nJpeOutBitOffset = pJpeHalHandle->tJpeHalOutBufCfg.nJpeOutBitOffset; ++ ++ return JPE_IOC_RET_SUCCESS; ++} ++ ++/** ++ * Description: ++ * Check the parameter sanity. ++ * ++ * Author: ++ * Albert.Liao ++ * ++ * Input: ++ * pCfg: pointer to JPEG configurations ++ * ++ * Output: ++ * Success: JPE_IOC_RET_SUCCESS ++ * Failure: JPE_IOC_RET_BAD_INBUF, JPE_IOC_RET_FMT_NOT_SUPPORT ++ */ ++JpeOpsCB_t* JpeOpsAcquire(int id) ++{ ++ JpeOpsCB_t* pJpeOpsCB = NULL; ++ JpeOps_t* pJpeOps = NULL; ++ ++ if(NULL != (pJpeOps = CamOsMemCalloc(1, sizeof(JpeOps_t)))) ++ { ++ pJpeOpsCB = &pJpeOps->ops; ++ pJpeOpsCB->init = _Init; ++ pJpeOpsCB->release = _OpsFree; ++ pJpeOpsCB->setConf = _SetConf; ++ pJpeOpsCB->getConf = _GetConf; ++ pJpeOpsCB->getCaps = _GetCaps; ++ pJpeOpsCB->jpeJob = _JpeJob; ++ } ++ return (JpeOpsCB_t*)pJpeOps; ++} +diff --git a/drivers/mstar/mfe/Kconfig b/drivers/mstar/mfe/Kconfig +new file mode 100644 +index 00000000..9bd05935 +--- /dev/null ++++ b/drivers/mstar/mfe/Kconfig +@@ -0,0 +1,3 @@ ++config MS_MFE ++ tristate "MFE driver" ++ help +diff --git a/drivers/mstar/mfe/Makefile b/drivers/mstar/mfe/Makefile +new file mode 100644 +index 00000000..8d96bd80 +--- /dev/null ++++ b/drivers/mstar/mfe/Makefile +@@ -0,0 +1,18 @@ ++# ++# Makefile for MStar MFE (Multi-Format Encoder) device driver. ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/mfe/inc ++EXTRA_CFLAGS += -Idrivers/mstar/mfe ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++# files ++obj-$(CONFIG_MS_MFE) += kdrv_mmfe.o ++ ++kdrv_mmfe-y := \ ++ mmfe_module.o \ ++ mmfe_ops.o \ ++ src/mfe_asic.o \ ++ src/mfe_hdlr.o \ ++ src/mfe_avc.o \ ++ src/mfe_rc.o \ +diff --git a/drivers/mstar/mfe/inc/mfe_asic.h b/drivers/mstar/mfe/inc/mfe_asic.h +new file mode 100644 +index 00000000..87a69c31 +--- /dev/null ++++ b/drivers/mstar/mfe/inc/mfe_asic.h +@@ -0,0 +1,13 @@ ++ ++#ifndef _MFE_ASIC_H_ ++#define _MFE_ASIC_H_ ++ ++typedef struct mfe_asic { ++ struct mutex* lock; ++ int i_ctx_count; ++ void* p_iobase; ++ void* p_pmbase; ++} mfe_asic; ++ ++#endif//_MFE_ASIC_H_ ++ +diff --git a/drivers/mstar/mfe/inc/mfe_avc.h b/drivers/mstar/mfe/inc/mfe_avc.h +new file mode 100644 +index 00000000..f6797833 +--- /dev/null ++++ b/drivers/mstar/mfe/inc/mfe_avc.h +@@ -0,0 +1,102 @@ ++ ++#ifndef _MFE_AVC_H_ ++#define _MFE_AVC_H_ ++ ++typedef struct bitstream { ++ int bits_pos; ++ int length; ++ int left_count; ++ uint code_bits; ++ uchar* curr; ++ uchar* buffer; ++ int ebsp_zeros; ++} bs_t; ++ ++int avc_reset(bs_t*,uchar*, int); ++int avc_flush(bs_t*); ++int avc_count(bs_t*); ++ ++#define NAL_SLICE 1 ++#define NAL_IDR 5 ++#define NAL_SPS 7 ++#define NAL_PPS 8 ++#define NAL_FILLER 12 ++ ++#define NAL_PRIO_DISPOSED 0 ++#define NAL_PRIO_LOW 1 ++#define NAL_PRIO_HIGH 2 ++#define NAL_PRIO_HIGHEST 3 ++ ++typedef struct sps { ++ int i_sps_id; ++ int i_profile_idc; ++ int i_level_idc; ++ int b_constraint_set0; ++ int b_constraint_set1; ++ int b_constraint_set2; ++ int b_constraint_set3; ++ int i_log2_max_frame_num; ++ int i_poc_type; ++ int i_log2_max_poc_lsb; ++ int i_num_ref_frames; ++ int b_gaps_in_frame_num_value_allow; ++ int i_mb_w; ++ int i_mb_h; ++ int b_direct8x8_inference; ++ int b_crop; ++ struct { ++ int i_left, i_right; ++ int i_top, i_bottom; ++ } crop; ++ /* skip vui param */ ++} sps_t; ++ ++typedef struct pps { ++ sps_t* sps; ++ int i_pps_id; ++ int b_cabac; ++ /*only support slice_groups==1*/ ++ int i_num_ref_idx_l0_default_active; ++ int i_num_ref_idx_l1_default_active; ++ /*not support weighted pred*/ ++ int i_pic_init_qp; ++ int i_pic_init_qs; ++ /*only support chroma_qp_index_offset==0*/ ++ int b_deblocking_filter_control; ++ int b_constrained_intra_pred; ++ int b_redundant_pic_cnt; ++} pps_t; ++ ++#define SLICE_P 0 ++#define SLICE_B 1 ++#define SLICE_I 2 ++ ++typedef struct slice { ++ int b_idr_pic; ++ int i_ref_idc; ++ sps_t* sps; ++ pps_t* pps; ++ int i_type; ++ int i_first_mb; ++ int i_frame_num; ++ int i_idr_pic_id; ++ int i_poc; ++ int i_redundant_pic_cnt; ++ int b_direct_spatial_mv_pred; ++ int b_num_ref_idx_override; ++ int i_num_ref_idx_l0_active; ++ int i_num_ref_idx_l1_active; ++ int i_cabac_init_idc; ++ int i_qp; ++ int i_disable_deblocking_filter_idc; ++ int i_alpha_c0_offset; ++ int i_beta_offset; ++} slice_t; ++ ++int avc_write_nal(bs_t*, uchar); ++int avc_write_sps(bs_t*, sps_t*); ++int avc_write_pps(bs_t*, pps_t*); ++int avc_write_slice_header(bs_t*, slice_t*); ++ ++#endif//_MFE_AVC_H_ ++ +diff --git a/drivers/mstar/mfe/inc/mfe_hdlr.h b/drivers/mstar/mfe/inc/mfe_hdlr.h +new file mode 100644 +index 00000000..3f9cd05c +--- /dev/null ++++ b/drivers/mstar/mfe/inc/mfe_hdlr.h +@@ -0,0 +1,135 @@ ++ ++#ifndef _MFE_HDLR_H_ ++#define _MFE_HDLR_H_ ++ ++typedef struct { ++ int i_idx; ++ int b_busy; ++ uint base_y, base_c; ++} frame_t; ++ ++typedef struct { ++ int i_idx; ++ int i_poc; ++ int b_use; ++ uint32 planes[2]; ++} fs_t; ++ ++typedef struct { ++ int i_total; ++ fs_t frames[8]; ++} vbstore_t; ++ ++typedef struct { ++ void* mem_vptr; ++ int size; ++ dma_addr_t bus_addr; ++ unsigned int miu_addr; ++} kma_t; ++ ++typedef struct { ++ uint32 addr; ++ void* vptr; ++ int size; ++} mem_t; ++ ++typedef enum { ++ speed_invalid, ++ speed_lowest, ++ speed_low, ++ speed_high, ++ speed_highest, ++} clock_speed; ++ ++typedef enum { ++ pixel_tile_8x8, ++ pixel_tile_16x32, ++ pixel_semi_planer, ++} pixel_format; ++ ++typedef struct mfe_hdlr { ++ /* corresponding mfe-device */ ++ mfe_asic* asic; ++ /* rate control */ ++ cvbr_rc cvbr; ++ /* mfe-registers */ ++ mfe_regs* regs; ++ ++ struct mutex stream_lock; ++ struct mutex encode_lock; ++ ++ int b_stream; ++ int i_encode; ++ ++ int i_codec_type; ++ clock_speed clk_speed; ++ pixel_format pixel_fmt; ++ /* video input parameters */ ++ int i_picture_w, i_picture_h; ++ int i_display_w, i_display_h; ++ int i_mb_w, i_mb_h, i_mb_wxh; ++ /* picture type decision */ ++ int i_seq_numb; ++ int i_num_ppic, i_num_bpic; ++ int i_cnt_ppic, i_cnt_bpic; ++ /* motion search */ ++ int i_dmv_x; ++ int i_dmv_y; ++ int i_subpel; ++ unsigned int i_mv_block[2]; ++ /* bit-rate */ ++ int i_method; ++ int i_bps; ++ int i_qp; ++ /* frame-rate */ ++ frac_t fr_fps; ++ /* avc syntax element */ ++ sps_t sps; ++ pps_t pps; ++ slice_t sh; ++ /* freeback and statistic */ ++ int i_stat_size; ++ int i_last_bits; ++ int i_pic_avgqp; ++ ++ kma_t kma; ++ ++ uint32 i_base_gn; ++ uint32 i_size_gn; ++ uint32 i_base_bs; ++ uint32 i_size_bs; ++ void* p_vptr_bs; ++ ++ int i_num_ref_frames; ++ frame_t* dpb[4]; ++ frame_t frames[4]; ++ frame_t* recon; ++ frame_t input; ++ long long i_timecode; ++ ++ uchar code_sh[64]; ++ int bits_sh; ++ uchar code_sets[64]; ++ int bits_sets; ++ ++ void* p_outbuf; ++ int i_outlen; ++ int i_uselen; ++ int i_remlen; ++ ++} mfe_hdlr; ++ ++int mfe_hdlr_request(void**); ++int mfe_hdlr_release(void* ); ++ ++int mfe_hdlr_seq_init(mfe_hdlr* h); ++int mfe_hdlr_seq_exit(mfe_hdlr* h); ++void mfe_hdlr_pic_mode(mfe_hdlr* h); ++void mfe_hdlr_pic_init(mfe_hdlr* h); ++void mfe_hdlr_pic_done(mfe_hdlr* h); ++uint mfe_hdlr_pic_wait(void); ++void mfe_hdlr_pic_read_bits(mfe_hdlr* h); ++void mfe_hdlr_pic_prep_regs(mfe_hdlr* h); ++ ++#endif//_MFE_HDLR_H_ ++ +diff --git a/drivers/mstar/mfe/inc/mfe_rc.h b/drivers/mstar/mfe/inc/mfe_rc.h +new file mode 100644 +index 00000000..8a09a70c +--- /dev/null ++++ b/drivers/mstar/mfe/inc/mfe_rc.h +@@ -0,0 +1,221 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++////////////////////////////////////////////////////////////////////////// ++// MStar simple rate control ++////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MFE_RC_H_ ++#define _MFE_RC_H_ ++ ++#define MFE_VIDEO_MAX_W 1920 ++#define MFE_VIDEO_MAX_H 1088 ++ ++#define MFE_ER_MODE 0x11 //reg_mfe_g_er_mode 0/1/2/3: mby/bs/mby+bs/off ++#define MFE_ER_MBY 0 //reg_mfe_g_er_mby 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) ++#define MFE_ER_BS_TH 0 //reg_mfe_g_er_bs_th er_bs mode threshold ++ ++typedef int MFE_BOOL; ++typedef signed long long MFE_S64; ++ ++/************************************************************************/ ++/* Configuration */ ++/************************************************************************/ ++#define QS_SHIFT_FACTOR 5 ++// Define this to support MB-level rate control ++#define _SUPPORT_MBLEVEL_RC_ ++ ++// Define this to declare RC variables outside RC kernel ++// NOTE: MFE_MPEG4_CMODEL-- define this. ++//#define _USE_EXT_RCDATA_ ++ ++// The maximal allowable MB width ++#define MAX_MB_WIDTH (MFE_VIDEO_MAX_W>>4) ++ ++/* ~Configuration *******************************************************/ ++ ++#ifndef MSRC_MAX ++#define MSRC_MAX(a,b) (((a)>(b))?(a):(b)) ++#endif ++#ifndef MSRC_MIN ++#define MSRC_MIN(a,b) (((a)<(b))?(a):(b)) ++#endif ++ ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ #define TOP_QP_DIFF_LIMIT 3 // Must >= SPEC_QP_DIFF_LIMIT ++ #define LEFT_QP_DIFF_LIMIT 3 // Must >= SPEC_QP_DIFF_LIMIT ++#endif ++ ++typedef enum { ++ CONST_QUALITY = 1, //!< Constant qscale: Use specified QP. ++ CONST_BITRATE = 2, //!< Constant bitrate. ++ VARIABLE_BITRATE = 3, //!< Variable bitrate: instant bitrate is unrestricted. ++ CONSTRAINED_VARIABLE_BITRATE = 4, //!< Variable bitrate: instant maximal bitrate is restricted. ++ STRICT_CONST_BITRATE = 5, ++} RC_METHOD; ++ ++typedef enum { ++ FRAMELEVELRC = 1, //!< All MB's in one frame uses the same qscale. ++ MBLEVELRC = 2 //!< Allow qscale changing within frame, for better bitrate achievement. ++} RC_GRANULARITY; ++ ++#define CONST_QP 0 ++#define CBR 1 ++#define VBR 2 ++#define CONSTRAINED_VBR 3 ++#define STATIC_CBR 4 ++ ++// For CONSTRAINED_VARIABLE_BITRATE ++#define MAX_GAUGE_SIZE 60 ++ ++typedef struct fraction { ++ int num, den; ++} frac_t; ++ ++typedef struct { ++ /* Input parameters */ ++ int i_codec_type; ++ int i_pict_w, i_pict_h; ++ int i_method; ++ int b_mb_layer; ++ int i_num_ppic, i_num_bpic; ++ int i_bps, i_bps_max; ++ int b_fps_fixed; ++ int i_qp; ++ int i_fps; ++ frac_t fr_fps; ++ int m_nVPSize, m_nVPMbRow; ++ // Derived variables ++ int m_nAvgBitsPerFrame; ++ int m_nBitsPerFrame[3]; // I, P, B ++ /* rate control variables */ ++ int m_nFrameCount; // How many frame coded ++ int m_nBufFullness; // Rate control buffer ++ MFE_S64 m_nTotalBits; ++ // Last-frame status ++ MFE_BOOL m_bIsBotField; ++ int m_nLastFrameBits, m_nLastFrameAvgQStep[2]; ++ int m_nLastTargetBits; ++ /* Bitrate usage compensation */ ++ int m_nTargetFullness; ++ int m_nDeputyCount, m_nMinDeputyCount; ++ /* Variable bitrate */ ++ int m_nLongTermQP64; ++ // Model parameters ++ int m_nTargetBits; // target number of bits of current frame ++ int m_nTotalMB; // number of macroblocks in a frame ++ int m_nMBN; // Accumulated handled MB count (within one frame) ++ int m_nFrameQStep; ++ int m_nFrameType; ++ /* Only for CONSTRAINED_VARIABLE_BITRATE */ ++ int m_nMaxOffset; ++ int m_BitrateGauge[MAX_GAUGE_SIZE]; ++ int m_nGaugeCount, m_nGaugeIndex, m_nGaugeBitrate; ++ int m_nMaxFrozenFrame; ++ // QP, QStep: Min, Max ++ int m_nMinQP, m_nMaxQP; ++ int m_nMinQStep, m_nMaxQStep; ++ int m_nFrameSkipThrQP; ++ /* MB-level rate control */ ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ int m_nTargetMbBits; ++ int m_nTargetUsedBits; ++ int m_nUsedBits[3]; // For HW pipeline delay ++ int m_nSumAct; ++ int m_nMbWidth, m_nPrevQP, m_nLeftQP, m_nPrevTopQP[MAX_MB_WIDTH]; ++ int m_nLastTargetQP;// For sig_dump ++ // For coded frame slicing ++ int m_nNewPacket; // New GOB, video packet, slice... Simulating HW er_en ++ int m_nLastVPBits; ++#endif ++ int* m_pMBBitsArray;// Only for DEBUG usage. ++} cvbr_rc; ++ ++// Global ++void cvbr_InitRateControl(cvbr_rc* ct); ++void cvbr_CloseRateControl(cvbr_rc* ct); ++// Each frame ++int cvbr_InitFrame(cvbr_rc* ct, int nFrameType, char FieldType); // Return the initial frame qp ++int cvbr_UpdateFrame(cvbr_rc* ct, int totalUsedBits, char bDummyFrame, char FieldType); ++// Each macroblock ++int cvbr_InitMB(cvbr_rc* ct, int nVar, const int nPrevQP, const int nBits, int IsIntra, int IsP4MV, int BPredType, int nResetDQ); ++void output_MBR_reg(void* hd, cvbr_rc* ct); ++int rcQP2Qstep(cvbr_rc* ct, int QP); ++int rcQstep2QP(cvbr_rc* ct, int QstepX32); ++ ++#endif//_MFE_RC_H_ ++ +diff --git a/drivers/mstar/mfe/inc/mfe_regs.h b/drivers/mstar/mfe/inc/mfe_regs.h +new file mode 100644 +index 00000000..7dfe0b85 +--- /dev/null ++++ b/drivers/mstar/mfe/inc/mfe_regs.h +@@ -0,0 +1,1022 @@ ++ ++#ifndef _MFE_REGS_H_ ++#define _MFE_REGS_H_ ++ ++#define REG_ENC_MODE_MPG4 0 ++#define REG_ENC_MODE_H263 1 ++#define REG_ENC_MODE_H264 2 ++#define REG_ENC_MODE_JPEG 3 ++ ++#define MFE_MIAW 29//25//24 ++ ++#define ADDRESS_LO_BITS (16) ++#define ADDRESS_HI_BITS (MFE_MIAW-5-16) ++#define OUTBUFF_LO_BITS (16) ++#define OUTBUFF_HI_BITS (MFE_MIAW-16) ++#define IMIBUFF_LO_BITS (16) ++#define IMIBUFF_HI_BITS (MFE_MIAW-16) // low-bandwidth imi buffer is using 8-byte unit. ++ ++#define PIC_AVGQP_LO_BITS (16) ++#define PIC_AVGQP_HI_BITS (24-16) ++#define BIT_COUNT_LO_BITS (16) ++#define BIT_COUNT_HI_BITS (24-16) ++ ++// IRQ's ++#define IRQ_LESS_ROW_DONE 7 ++#define IRQ_NET_TRIGGER 6 ++#define IRQ_FS_FAIL 5 ++#define IRQ_TXIP_TIME_OUT 4 ++#define IRQ_BSPOBUF_FULL 3 ++#define IRQ_IMG_BUF_FULL 2 ++#define IRQ_MARB_BSPOBUF_FULL 1 ++#define IRQ_FRAME_DONE 0 ++ ++#define CHECK_IRQ_STATUS(r,irq) ((r>>irq)&1) ++ ++typedef struct _mfe_regs_ { ++ /* sw-coded data followed by mfe-output stream */ ++ void* coded_data; ++ int coded_bits; ++ /* miu address for mfe-hw */ ++ uint outbs_addr; ++ int outbs_size; ++ /* mfe-regs bank definition */ ++ union { ++ struct { ++ ushort reg00_g_frame_start_sw:1;// frame start (1T clk_mfe) ++ ushort reg00_g_soft_rstz:1; // software reset; 0/1: reset/not reset ++ ushort reg00_g_enc_mode:2; // 0/1/2/3: MPEG4/H263/H264/JPEG ++ ushort reg00_g_frame_type:2; // 0/1/2: I/P/B ++ ushort reg00_g_ref_no:1; // 0/1: 1 frame/2 frames ++ ushort reg00_g_mbr_en:1; // 0/1: disable/enable MB-level Rate control ++ ushort reg00_g_qscale:6; // frame level qscale: [H264]: 1 ~ 51; [MPEG4]: 1 ~ 31 ++ ushort reg00_g_rec_en:1; // reconstruct enable ++ ushort reg00_g_jpe_mst422_mode:1; // YUV422 input buffer format; 0: YUYV, 1: MST422 ++ }; ++ ushort reg00; ++ }; ++ union { ++ struct { ++ ushort reg01_g_pic_width:12; // picture width ++ ushort reg01_g_ver_minor_idx:4; ++ }; ++ ushort reg01; ++ }; ++ union { ++ struct { ++ ushort reg02_g_pic_height:12; // picture height ++ ushort reg02_g_ver_major_idx:4; ++ }; ++ ushort reg02; ++ }; ++ union { ++ struct { ++ ushort reg03_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off ++ ushort reg03_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) ++ ushort reg03_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV ++ ushort reg03_g_qmode:1; // quantization method; 0/1: h263/mp4 ++ ushort reg03_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control ++ ushort reg03_g_fldpic_en:1; // field picture coding ++ ushort reg03_g_dct_only_en:1; // regmfe_g_dct_only_en ++ }; ++ ushort reg03; ++ }; ++ union { ++ struct { ++ ushort reg04_g_er_bs_th:16; // er_bs mode threshold ++ }; ++ ushort reg04; ++ }; ++ union { ++ struct { ++ ushort reg05_g_inter_pref:16; // inter prediction preference ++ }; ++ ushort reg05; ++ }; ++ union { ++ struct { ++ ushort reg06_g_cur_y_addr_lo:ADDRESS_LO_BITS; // current luma base address ++ }; ++ ushort reg06; ++ }; ++ union { ++ struct { ++ ushort reg07_g_cur_y_addr_hi:ADDRESS_HI_BITS; // current luma base address ++ }; ++ ushort reg07; ++ }; ++ union { ++ struct { ++ ushort reg08_g_cur_c_addr_lo:ADDRESS_LO_BITS; // current chroma base address ++ }; ++ ushort reg08; ++ }; ++ union { ++ struct { ++ ushort reg09_g_cur_c_addr_hi:ADDRESS_HI_BITS; // current chroma base address ++ }; ++ ushort reg09; ++ }; ++ union { ++ struct { ++ ushort reg0a_g_ref_y_addr0_lo:ADDRESS_LO_BITS; // reference luma base address0 ++ }; ++ ushort reg0a; ++ }; ++ union { ++ struct { ++ ushort reg0b_g_ref_y_addr0_hi:ADDRESS_HI_BITS; // reference luma base address0 ++ }; ++ ushort reg0b; ++ }; ++ union { ++ struct { ++ ushort reg0c_g_ref_y_addr1_lo:ADDRESS_LO_BITS; // reference luma base address1 ++ }; ++ ushort reg0c; ++ }; ++ union { ++ struct { ++ ushort reg0d_g_ref_y_addr1_hi:ADDRESS_HI_BITS; // reference luma base address0 ++ }; ++ ushort reg0d; ++ }; ++ union { ++ struct { ++ ushort reg0e_g_ref_c_addr0_lo:ADDRESS_LO_BITS; // reference chroma base address0 ++ }; ++ ushort reg0e; ++ }; ++ union { ++ struct { ++ ushort reg0f_g_ref_c_addr0_hi:ADDRESS_HI_BITS; // reference chroma base address0 ++ }; ++ ushort reg0f; ++ }; ++ union { ++ struct { ++ ushort reg10_g_ref_c_addr1_lo:ADDRESS_LO_BITS; // reference chroma base address1 ++ }; ++ ushort reg10; ++ }; ++ union { ++ struct { ++ ushort reg11_g_ref_c_addr1_hi:ADDRESS_HI_BITS; // reference chroma base address1 ++ }; ++ ushort reg11; ++ }; ++ union { ++ struct { ++ ushort reg12_g_rec_y_addr_lo:ADDRESS_LO_BITS; // reconstructed luma base address ++ }; ++ ushort reg12; ++ }; ++ union { ++ struct { ++ ushort reg13_g_rec_y_addr_hi:ADDRESS_HI_BITS; // reconstructed luma base address ++ }; ++ ushort reg13; ++ }; ++ union { ++ struct { ++ ushort reg14_g_rec_c_addr_lo:ADDRESS_LO_BITS; // reconstructed chroma base address ++ }; ++ ushort reg14; ++ }; ++ union { ++ struct { ++ ushort reg15_g_rec_c_addr_hi:ADDRESS_HI_BITS; // reconstructed chroma base address ++ }; ++ ushort reg15; ++ }; ++ union { ++ struct { // clock gating ++ ushort gate_cry_crc_sram:1; ++ ushort gate_qtab_dbfdc_dbqtb_sram:1; ++ ushort gate_mcy_mcc_sram:1; ++ ushort gate_res0_res1_sram:1; ++ ushort gate_ieap:1; ++ ushort gate_dct_idct:1; ++ ushort gate_dbf:1; ++ }; ++ ushort reg16; ++ }; ++ union { ++ struct { ++ ushort reg17_s_auto_rst_wait_cnt:6; // the waiting count for regen_soft_rstz and regen_fs_sw generation ++ ushort reg17_g_sram1p_wp_type:1; // "MFE 1p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" ++ ushort reg17_g_sram2p_wp_type:1; // "MFE 2p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" ++ ushort reg17_g_clk_mfe_en:4; // NOT used now. ++ ushort reg17_g_mreq_sel:1; // "1" D1 MIU clk gating; "0" dynamic MIU clk gating ++ ushort reg17_g_mreq_always_active:1; // "1" mreq always active; "0" make mreq active according to FSM. (let this be default) ++ ushort reg17_g_clk_miu_d2_gate:1; // b1: turn off miu clock of power-domain "dma" and sleep into d2 mode ++ ushort reg17_g_clk_mfe_d2_gate:1; // b1: turn off mfe clock of power-domain "core" and sleep into d2 mode ++ }; ++ ushort reg17; ++ }; ++ // [JPEG] ++ union { ++ struct { ++ ushort reg18_g_jpe_enc_mode:2; // JPE encode mode; 2'b00/2'b01/2'b10/2'b11: 420/422/444/gray; current version supports 422 only ++ ushort reg18_g_jpe_buffer_mode:1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode ++ ushort reg18_g_jpe_multibuf_mode:2; // JPE multi-buffer mode; 0/1/2: 2/4/8 buffers ++ ushort reg18_g_jpe_qfactor:4; // JPE q factor; 0 ~ 15: (1 ~ 16)/4 ++ // (M1)JPE fsvs generation mode; ++ // 0: pure sw ++ // 1: sw+hw ++ // 2: hw w/o auto-restart ++ // 3: hw w/i auto-restart ++ ushort reg18_g_jpe_fsvs_mode:2; // (T8)JPE fsvs generation mode; 0/1/2: pure sw/sw+hw/hw ++ ushort reg18_reserved:3; ++ ushort reg18_g_jpe_turbo_en:1; // 0: turbo mode off, 1: turbo mode enabled ++ ushort reg18_g_viu_soft_rstz:1; // viu software reset; 0/1: reset/not reset ++ }; ++ ushort reg18; ++ }; ++ // [MPEG4/H263] ++ union { ++ struct { ++ ushort reg19_g_mp4_itlc:1; // 0/1: MPEG4 progressive/interlaced mode ++ ushort reg19_g_mp4_pskip_off:1; // 0/1: MPEG4 enable/disable p skip mode ++ ushort reg19_g_mp4_acp:2; // [0]: 0/1: sw/hw acp selection; [1]: sw default value: 0/1: disable/enable acp; current version off ++ ushort reg19_g_mp4_rounding_ctrl:1; // mp4 rounding control specified as in spec ++ ushort reg19_g_er_hec:1; // 0/1: header extension code off/on ++ ushort reg19_g_er_hec_t:3; // HEC counter reset values ++ ushort reg19_g_er_h263_unit:2; // 0/1/2: unit is 1/2/4, for calculating gob_num. ++ ushort reg19_g_mp4_direct_en:1; // MPEG4 direct enable ++ ushort reg19_g_mp4_direct_mvstore:1; // [M]: enable storing of mv & skip_mb information to DRAM in P(or sometimes I) frame ++ }; ++ ushort reg19; ++ }; ++ union { ++ struct { ++ ushort reg1a_g_mp4_direct_pref:8; // used in mp4 only, mp4 direct mode preference value ++ ushort reg1a_g_mp4_direct_trb:3; // used in mp4 only, mp4 direct mode trb (P0-B distance) ++ ushort reg1a_g_mp4_direct_trd:3; // used in mp4 only, mp4 direct mode trd (P0-P1 distance) ++ ushort reg1a_reserved:1; ++ ushort reg1a_g_mb_pitch_en:1; ++ }; ++ ushort reg1a; ++ }; ++ union { ++ struct { ++ ushort reg1b_g_mp4_flddct_diff_thr:8; // used in mp4 only, mp4 field dct difference threshold ++ ushort reg1b_g_mp4_flddct_en:1; // used in mp4 only, mp4 field dct enable ++ }; ++ ushort reg1b; ++ }; ++ // [IRQ & important IP status checkings] ++ union { ++ struct { ++ ushort reg1c_g_irq_mask:8; // 0/1: irq not-mask/mask ++ ushort reg1c_g_irq_force:8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt ++ }; ++ ushort reg1c; ++ }; ++ union { ++ struct { ++ ushort reg1d_g_irq_clr0:1; // 0/1: not clear interrupt/clear interrupt 0 ++ ushort reg1d_g_irq_clr1:1; // 0/1: not clear interrupt/clear interrupt 1 ++ ushort reg1d_g_irq_clr2:1; // 0/1: not clear interrupt/clear interrupt 2 ++ ushort reg1d_g_irq_clr3:1; // 0/1: not clear interrupt/clear interrupt 3 ++ ushort reg1d_g_irq_clr4:1; // 0/1: not clear interrupt/clear interrupt 4 ++ ushort reg1d_g_irq_clr5:1; // 0/1: not clear interrupt/clear interrupt 5 ++ ushort reg1d_g_irq_clr6:1; // 0/1: not clear interrupt/clear interrupt 6 ++ ushort reg1d_g_irq_clr7:1; // 0/1: not clear interrupt/clear interrupt 7 ++ ushort reg1d_g_swrst_safe:1; // to indicate there're no miu activities that need to pay attention to ++ }; ++ ushort reg1d; ++ }; ++ union { ++ struct { ++ // status of interrupt on CPU side ++ // ({1'b0,net_trigger,fs_fail_irq, txip_time_out,early_bspobuf_full_irq/buf1_full,img_buf_full_irq,marb_bspobuf_ful/buf0_full,frame_done_irq}) ++ // [3] SW mode: early obuf full; HW mode: buf1 full ++ // [1] SW mode: buf full; HW mode: buf0 full ++ ushort reg1e_g_irq_cpu:8; ++ // status of interrupt on IP side ++ // ({1'b0,net_trigger,fs_fail_irq, txip_time_out,early_bspobuf_full_irq/buf1_full,img_buf_full_irq,marb_bspobuf_ful/buf0_full,frame_done_irq}) ++ // [3] SW mode: early obuf full; HW mode: buf1 full ++ // [1] SW mode: buf full; HW mode: buf0 full ++ ushort reg1e_g_irq_ip:8; ++ }; ++ ushort reg1e; ++ }; ++ union { ++ struct { ++ ushort reserved_reg1f; ++ }; ++ ushort reg1f; ++ }; ++ // [ME setting] ++ union { ++ struct { ++ ushort reg20_s_me_4x4_disable:1; // 4x4_disable ++ ushort reg20_s_me_8x4_disable:1; // 8x4_disable ++ ushort reg20_s_me_4x8_disable:1; // 4x8_disable ++ ushort reg20_s_me_16x8_disable:1; // 16x8_disable ++ ushort reg20_s_me_8x16_disable:1; // 8x16_disable ++ ushort reg20_s_me_8x8_disable:1; // 8x8_disable ++ ushort reg20_s_me_16x16_disable:1; // 16x16_disable ++ ushort reg20_s_mesr_adapt:1; // me search range auto-adaptive; 0/1: off/on ++ ushort reg20_s_me_ref_en_mode:2; // ref enable mode: 2'b01/2'b10/2'b11: ref0 enable/ref1 enable/ref0&1 enable ++ }; ++ ushort reg20; ++ }; ++ // [IME PIPELINE] ++ union { ++ struct { ++ ushort reg21_s_ime_sr16:1; // search range limited to (h,v) = (+/-16, +/-16); 0/1: search range 32/16 ++ ushort reg21_s_ime_umv_disable:1; // 0/1: UMV enable/disable ++ ushort reg21_s_ime_ime_wait_fme:1; // 0/1: ime wait fme/fme wait ime ++ ushort reg21_s_ime_boundrect_en:1; // ime bounding rectangle enable (needed for level 3.0 and below) ++ ushort reg21_s_ime_h264_p8x8_ctrl_en:1; // ime h264 max p8x8 count control enable ++ ushort reg21_reserved:3; ++ ushort reg21_s_ime_h264_p8x8_max:8; // ime h264 max p8x8 count; value 0 is prohibited ++ // Max P8x8 MB count = 16 * reg21_s_ime_h264_p8x8_max ++ }; ++ ushort reg21; ++ }; ++ union { ++ struct { ++ ushort reg22_s_ime_mesr_max_addr:8; // me search range max depth ++ ushort reg22_s_ime_mesr_min_addr:8; // me search range min depth ++ }; ++ ushort reg22; ++ }; ++ union { ++ struct { ++ ushort reg23_s_ime_mvx_min:6; // me mvx min; 0/.../62 --> -32/.../30 ++ ushort reg23_reserved:2; ++ ushort reg23_s_ime_mvx_max:6; // me mvx max; 0/.../62 --> -32/.../30 ++ }; ++ ushort reg23; ++ }; ++ union { ++ struct { ++ ushort reg24_s_ime_mvy_min:6; // me mvy min; 0/.../62 --> -32/.../30 ++ ushort reg24_reserved:2; ++ ushort reg24_s_ime_mvy_max:6; // me mvy max; 0/.../62 --> -32/.../30 ++ }; ++ ushort reg24; ++ }; ++ // [FME pipeline] ++ union { ++ struct { ++ ushort reg25_s_fme_quarter_disable:1; // 0/1: Quarter fine-tune enable/disable ++ ushort reg25_s_fme_half_disable:1; // 0/1: Half fine-tune enable/disable ++ ushort reg25_reserved:1; ++ ushort reg25_s_fme_pmv_enable:1; // 0/1: disable/enable Previous Skip MV mode ++ ushort reg25_s_fme_mode_no:1; // 0: one mode. 1: two mode. ++ ushort reg25_s_fme_mode0_refno:1; // 0: one ref. for mode0 1: two ref. for mode0 ++ ushort reg25_s_fme_mode1_refno:1; // 0: one ref. for mode1 1: two ref. for mode1 ++ ushort reg25_s_fme_mode2_refno:1; // 0: one ref. for mode2 1: two ref. for mode2 ++ ushort reg25_s_fme_skip:1; // fme skip ++ ushort reg25_s_fme_pipeline_on:1; // 0/1: FME pipeline off/on ++ }; ++ ushort reg25; ++ }; ++ // MBR ++ union { ++ struct { ++ ushort reg26_s_mbr_pqp_dlimit:2; // previous qp diff limit ++ ushort reg26_s_mbr_uqp_dlimit:2; // upper qp diff limit ++ ushort reg26_s_mbr_tmb_bits:12; // target MB bits ++ }; ++ ushort reg26; ++ }; ++ union { ++ struct { ++ ushort reg27_s_mbr_frame_qstep:13; // frame level qp's qstep ++ }; ++ ushort reg27; ++ }; ++ union { ++ struct { ++ ushort reg28_s_mbr_last_frm_avg_qp_lo:PIC_AVGQP_LO_BITS; // last frame average qp (status register) ++ }; ++ ushort reg28; ++ }; ++ union { ++ struct { ++ ushort reg29_s_mbr_last_frm_avg_qp_hi:PIC_AVGQP_HI_BITS; // last frame average qp (status register) ++ ushort reg29_s_mbr_qp_cidx_offset:5;// [H264] chroma qp index offset (+12). Spec range is [-12,12] ++ }; ++ ushort reg29; ++ }; ++ union { ++ struct { ++ ushort reg2a_s_mbr_qp_min:6; // qp min ++ ushort reg2a_s_mbr_qp_max:6; // qp max ++ ushort reg2a_s_mvdctl_ref0_offset:2;// H264 mvy offset adjustment for MCC if ref is frame 0: 0/1/2: 0/+2/-2 ++ ushort reg2a_s_mvdctl_ref1_offset:2;// H264 mvy offset adjustment for MCC if ref is frame 1: 0/1/2: 0/+2/-2 ++ }; ++ ushort reg2a; ++ }; ++ // IEAP ++ union { ++ struct { ++ ushort reg2b_s_ieap_last_mode:4; // software control of the last mode of Intra4x4 mode 0 ~ 8 ++ ushort reg2b_s_ieap_constraint_intra:1; // software control constraint intra; 0/1: OFF/ON ++ ushort reg2b_s_ieap_ccest_en:1; // software control cost estimator; 0/1: OFF/ON ++ ushort reg2b_s_ieap_ccest_thr:2; // threshold of cost estimator set 0 ~ 3 for threshold 1 ~ 4 ++ ushort reg2b_s_ieap_drop_i16:1; // software control stop-Intra16x16-mode; 1:w/o I16M, 0:w/i I16MB ++ }; ++ ushort reg2b; ++ }; ++ // QUAN ++ union { ++ struct { ++ ushort reg2c_s_quan_idx_last:6; // the index of the last non-zero coefficient in the zig-zag order ++ ushort reg2c_s_quan_idx_swlast:1; // software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable ++ ushort reg2c_g_mb_pitch:8; // mb pitch (x-direction) ++ }; ++ ushort reg2c; ++ }; ++ // TXIP control & debug ++ union { ++ struct { ++ ushort reg2d_s_txip_mbx:9; // txip mbx ++ ushort reg2d_s_txip_sng_mb:1; // 0/1: disable/enable txip controller stop-and-go mechanism using ++ // (txip_mbx == reg71_g_debug_trig_mbx) & (txip_mby == reg72_g_debug_trig_mby) ++ ushort reg2d_s_txip_sng_set:1; // txip controller stop-and-go mechanism using this register bit: ++ // 0/1: go/stop ++ ushort reg2d_s_txip_dbf_full_halt_en:1; // txip controller stop-and-go mechanism using double buffer fullness as criterion: ++ // 0/1: disable/enable ++ }; ++ ushort reg2d; ++ }; ++ union { ++ struct { ++ ushort reg2e_s_txip_mby:9; // txip mby ++ }; ++ ushort reg2e; ++ }; ++ union { ++ struct { ++ ushort reg2f_s_txip_irfsh_mb_s0:13; // intra refresh mb start 0 ++ ushort reg2f_reserved:1; ++ ushort reg2f_s_txip_irfsh_en:2; // intra refresh enable bits: bit0: enable condition 0; bit 1: enable condition 1 ++ }; ++ ushort reg2f; ++ }; ++ union { ++ struct { ++ ushort reg30_s_txip_irfsh_mb_e0:13; // intra refresh mb end 0 ++ }; ++ ushort reg30; ++ }; ++ union { ++ struct { ++ ushort reg31_s_txip_irfsh_mb_s1:13; // intra refresh mb start 1 ++ }; ++ ushort reg31; ++ }; ++ union { ++ struct { ++ ushort reg32_s_txip_irfsh_mb_e1:13; // intra refresh mb end 1 ++ ushort reg32_reserved:1; ++ ushort reg32_s_txip_timeout_en:1; // txip time out enable ++ ushort reg32_s_txip_wait_mode:1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count ++ }; ++ ushort reg32; ++ }; ++ union { ++ struct { ++ ushort reg33_s_txip_idle_cnt:16; // wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) ++ }; ++ ushort reg33; ++ }; ++ union { ++ struct { ++ ushort reg34_s_txip_timeout:16; // txip timeout count (x 64T) ++ }; ++ ushort reg34; ++ }; ++ // [ECDB PIPELINE] ++ // ECDB control & debug ++ union { ++ struct { ++ ushort reg35_s_ecdb_mbx:9; // ecdb mbx ++ }; ++ ushort reg35; ++ }; ++ union { ++ struct { ++ ushort reg36_s_ecdb_mby:9; // ecdb mby ++ }; ++ ushort reg36; ++ }; ++ // MDC ++ union { ++ struct { ++ ushort reg37_s_mdc_total_mb_bw:4; // total mb bit width used in video_pkt ++ ushort reg37_s_mdc_m4vpktpzero:1; // MPEG4 video packet preceding zeros: 0/1: 16/17 zeros ++ ushort reg37_s_mdc_m4timev:2; // MPEG4 modulo time base: 0/1/2/3: 0/10/110/1110 ++ ushort reg37_s_mdc_m4iadcvlc_th:3; // MPEG4 intra dc vlc threshold ++ ushort reg37_s_mdc_m4vop_tinc_bw:4; // vop_time_increment bit width ++ }; ++ ushort reg37; ++ }; ++ union { ++ struct { ++ ushort reg38_s_mdc_m4vop_tinc:15; // vop_time_increment ++ }; ++ ushort reg38; ++ }; ++ union { ++ struct { ++ ushort reg39_s_mdc_gob_frame_id:2; // H263 gob frame id ++ ushort reg39_s_mdc_h264_nal_ref_idc:2; // nal_ref_idc ++ ushort reg39_s_mdc_h264_nal_unit_type:1; // 0/1: 1/5 ++ ushort reg39_s_mdc_h264_fnum_bits:2; // H264 frame num bits ++ ushort reg39_s_mdc_h264_dbf_control:1; // dbf control present flag ++ ushort reg39_s_mdc_h264_fnum_value:8; // H264 frame num value ++ }; ++ ushort reg39; ++ }; ++ union { ++ struct { ++ ushort reg3a_s_mdc_h264_idr_pic_id:3; ++ ushort reg3a_s_mdc_h264_disable_dbf_idc:2; ++ ushort reg3a_s_mdc_h264_alpha:4; // slice_alpha_c0_offset_div2 ++ ushort reg3a_s_mdc_h264_beta:4; // slice_beta_offset_div2 ++ ushort reg3a_s_mdc_h264_ridx_aor_flag:1; // reference index active override flag ++ }; ++ ushort reg3a; ++ }; ++ // BSPOBUF/MVOBUF ++ union { ++ struct { ++ ushort reg3b_s_bspobuf_set_adr:1; // set bsp obuf start address(write one clear) ++ ushort reg3b_s_mvobuf_set_adr:1; // set mv obuf start address (write one clear) ++ ushort reg3b_s_bspobuf_fifo_th:3; // bsp obuf threshold ++ ushort reg3b_s_mvobuf_fifo_th:3; // mv obuf threshold ++ ushort reg3b_s_bsp_fdc_skip:1; // fdc skip enable; 0: fdc skip disable, 1: fdc skip enable ++ ushort reg3b_reserved:5; ++ ushort reg3b_s_obuf_toggle_obuf0_status:1; // toggle buf0 status(write one clear) ++ ushort reg3b_s_obuf_toggle_obuf1_status:1; // toggle buf1 status(write one clear) ++ }; ++ ushort reg3b; ++ }; ++ union { ++ struct { ++ ushort reg3c_s_bspobuf_lo:OUTBUFF_LO_BITS; // bsp obuf start address ++ }; ++ ushort reg3c; ++ }; ++ union { ++ struct { ++ ushort reg3d_s_bspobuf_hi:OUTBUFF_HI_BITS; // bsp obuf address high ++ ushort reg3d_reserved:(16-OUTBUFF_HI_BITS-2); ++ ushort reg3d_s_obuf_id:2; // 00: s0, 01: e0, 10: s1, 11: e1 ++ }; ++ ushort reg3d; ++ }; ++ union { ++ struct { ++ ushort reg3e_s_obuf_write_id_adr:1; // write to this address to enable writing of bspobuf address ++ }; ++ ushort reg3e; ++ }; ++ union { ++ struct { ++ ushort reg3f_s_bspobuf_hw_en:1; // enable HW obuf automatic mechanism ++ ushort reg3f_s_bspobuf_update_adr:1; // update obuf address(write one clear) ++ ushort reg3f_s_bspobuf_adr_rchk_sel:2; // obuf adr read back check selection: 0/1/2/3: s0/e0/s1/e1 ++ ushort reg3f_s_bspobuf_adr_rchk_en:1; // enable bspobuf adr read back check through regmfe_s_bspobuf_wptr ++ ushort reg3f_reserved:3; ++ ushort reg3f_s_bsp_fdc_offset:7; // bsp's fdc offset ++ }; ++ ushort reg3f; ++ }; ++ union { ++ struct { ++ ushort reg40_s_mvobuf_saddr_lo:OUTBUFF_LO_BITS; // mv obuf start address ++ }; ++ ushort reg40; ++ }; ++ union { ++ struct { ++ ushort reg41_s_mvobuf_saddr_hi:OUTBUFF_HI_BITS; // mv obuf start address ++ }; ++ ushort reg41; ++ }; ++ union { ++ struct { ++ ushort reg42_s_bsp_bit_cnt_lo:BIT_COUNT_LO_BITS; // encoded bit count (one frame) ++ }; ++ ushort reg42; ++ }; ++ union { ++ struct { ++ ushort reg43_s_bsp_bit_cnt_hi:BIT_COUNT_HI_BITS; // encoded bit count (one frame) ++ }; ++ ushort reg43; ++ }; ++ union { ++ struct { ++ ushort reg44_s_bspobuf_wptr_lo:OUTBUFF_LO_BITS; // bspobuf write pointer (8 byte unit) ++ }; ++ ushort reg44; ++ }; ++ union { ++ struct { ++ ushort reg45_s_bspobuf_wptr_hi:OUTBUFF_HI_BITS; // bspobuf write pointer (8 byte unit) ++ }; ++ ushort reg45; ++ }; ++ // FDC ++ union { ++ struct { ++ ushort reg46_s_fdc_bs:16; // cpu to fdc bitstream data ++ }; ++ ushort reg46; ++ }; ++ union { ++ struct { ++ ushort reg47_s_fdc_bs_len:5; // cpu to fdc bitstream len; 0 ~ 16 ++ ushort reg47_s_fdc_bs_count:10; // cpu to fdc round count ++ }; ++ ushort reg47; ++ }; ++ // [Table Control] ++ union { ++ struct { ++ ushort reg48_s_fdc_ack:1; // fdc to cpu ack; 0/1: frame data pool not empty/frame data pool empty; 48x64 bits of space ++ ushort reg48_s_fdc_done_clr:1; // fdc done clear (write one clear) ++ ushort reg48_s_fdc_done:1; // fdc done; indicate to CPU that data has been written to internal buffer ++ ushort reg48_reserved:8; ++ ushort reg48_s_fdc_bs_vld:1; // set for bitstream write out (write one clear) ++ ushort reg48_s_tbc_en:1; // set for table read & write ; 1: enable, 0: disable (write one clear) ++ }; ++ ushort reg48; ++ }; ++ union { ++ struct { ++ ushort reg49_s_tbc_rw:1; // table mode; 0: read, 1: write ++ ushort reg49_s_tbc_done_clr:1; // table done clear (write one clear) ++ ushort reg49_s_tbc_done:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg4b_s_tbc_rdata ++ ushort reg49_reserved:5; ++ ushort reg49_s_tbc_adr:6; // table address ++ }; ++ ushort reg49; ++ }; ++ union { ++ struct { ++ ushort reg4a_s_tbc_wdata:16; // table write data ++ }; ++ ushort reg4a; ++ }; ++ union { ++ struct { ++ ushort reg4b_s_tbc_rdata:16; // table read data ++ }; ++ ushort reg4b; ++ }; ++ // [Get Neighbor] ++ union { ++ struct { ++ ushort reg4c_s_gn_saddr_lo:OUTBUFF_LO_BITS; // gn base adr low ++ }; ++ ushort reg4c; ++ }; ++ union { ++ struct { ++ ushort reg4d_s_gn_saddr_hi:OUTBUFF_HI_BITS; // gn base adr high ++#if (16-OUTBUFF_HI_BITS-1>0) ++ ushort reg4d_reserved:16-OUTBUFF_HI_BITS-1; ++#endif ++ ushort reg4d_s_gn_saddr_mode:1; // 1: gn save data in one frame 0: gn save data in one row ++ }; ++ ushort reg4d; ++ }; ++ union { ++ struct { ++ ushort reg4e_s_gn_mvibuf_saddr_lo:OUTBUFF_LO_BITS; // mv ibuf start address low ++ }; ++ ushort reg4e; ++ }; ++ union { ++ struct { ++ ushort reg4f_s_gn_mvibuf_saddr_hi:OUTBUFF_HI_BITS; // mv ibuf start address high ++ }; ++ ushort reg4f; ++ }; ++ union { ++ struct { ++ ushort reg56_s_marb_mrpriority_sw:2; // mfe2mi_rpriority software programmable ++ ushort reg56_s_marb_mr_timeout_ref:1; // miu read burst timeout count start point ++ ushort reg56_s_marb_mr_nwait_mw:1; // miu read not wait mi2mfe_wrdy ++ ushort reg56_s_marb_mwpriority_sw:2; // mfe2mi_wpriority software programmable ++ ushort reg56_s_marb_mw_timeout_ref:1; // miu write burst timeout count start point ++ ushort reg56_s_marb_mw_nwait_mr:1; // miu read not wait mi2mfe_wrdy ++ ushort reg56_s_marb_mr_pending:4; // max. pending read requests to miu ++ ushort reg56_s_marb_32b_ad_nswap:1; // 32bits miu address not swap. only for 32bits mode ++ ushort reg56_s_marb_miu_wmode:1; // 0/1: original miu protocol/new miu protocol(wd_en) ++ }; ++ ushort reg56; ++ }; ++ union { ++ struct { ++ ushort reg58_s_marb_ubound_0_lo:OUTBUFF_LO_BITS; // MIU protect for MPEG4 BSP obuf ++ }; ++ ushort reg58; ++ }; ++ union { ++ struct { ++ ushort reg59_s_marb_ubound_0_hi:OUTBUFF_HI_BITS; // MIU protect for MPEG4 BSP obuf ++ ushort reg59_reserved:(16-OUTBUFF_HI_BITS); ++ }; ++ ushort reg59; ++ }; ++ union { ++ struct { ++ ushort reg5a_s_marb_lbound_0_lo:OUTBUFF_LO_BITS; // MIU protect for MPEG4 BSP obuf ++ }; ++ ushort reg5a; ++ }; ++ union { ++ struct { ++ ushort reg5b_s_marb_lbound_0_hi:OUTBUFF_HI_BITS; // MIU protect for MPEG4 BSP obuf ++ ushort reg5b_s_marb_miu_bound_en_0:1; ++ }; ++ ushort reg5b; ++ }; ++ union { ++ struct { ++ ushort reg5c_s_marb_ubound_1_lo:OUTBUFF_LO_BITS; // MIU Upper bound protect for MPEG4 MC obuf rec ++ }; ++ ushort reg5c; ++ }; ++ union { ++ struct { ++ ushort reg5d_s_marb_ubound_1_hi:OUTBUFF_HI_BITS; // MIU Upper bound protect for MPEG4 MC obuf rec ++ }; ++ ushort reg5d; ++ }; ++ union { ++ struct { ++ ushort reg5e_s_marb_lbound_1_lo:OUTBUFF_LO_BITS; // MIU Lower bound protect for MPEG4 MC obuf ++ }; ++ ushort reg5e; ++ }; ++ union { ++ struct { ++ ushort reg5f_s_marb_lbound_1_hi:OUTBUFF_HI_BITS; // MIU Lower bound protect for MPEG4 MC obuf ++ ushort reg5f_s_marb_miu_bound_en_1:1; //miu write protection, miu bound enable for write port 1 ++ }; ++ ushort reg5f; ++ }; ++ union { ++ struct { ++ ushort reg60_s_marb_ubound_2_lo:OUTBUFF_LO_BITS; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg60; ++ }; ++ union { ++ struct { ++ ushort reg61_s_marb_ubound_2_hi:OUTBUFF_HI_BITS; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg61; ++ }; ++ union { ++ struct { ++ ushort reg62_s_marb_lbound_2_lo:OUTBUFF_LO_BITS; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg62; ++ }; ++ union { ++ struct { ++ ushort reg63_s_marb_lbound_2_hi:OUTBUFF_HI_BITS; // MIU protect for MPEG4 MV obuf ++ ushort reg63_s_marb_miu_bound_en_2:1; // miu write protection, miu bound enable for write port 2 ++ }; ++ ushort reg63; ++ }; ++ union { ++ struct { ++ ushort reg64_s_marb_ubound_3_lo:OUTBUFF_LO_BITS; // MIU protect for MPEG4 GN ++ }; ++ ushort reg64; ++ }; ++ union { ++ struct { ++ ushort reg65_s_marb_ubound_3_hi:OUTBUFF_HI_BITS; // MIU protect for MPEG4 GN ++ }; ++ ushort reg65; ++ }; ++ union { ++ struct { ++ ushort reg66_s_marb_lbound_3_lo:OUTBUFF_LO_BITS; // MIU protect for MPEG4 GN ++ }; ++ ushort reg66; ++ }; ++ union { ++ struct { ++ ushort reg67_s_marb_lbound_3_hi:OUTBUFF_HI_BITS; // MIU protect for MPEG4 GN ++ ushort reg67_s_marb_miu_bound_en_3:1; ++ ushort reg67_s_marb_miu_off:1; ++ ushort reg67_s_marb_miu_bound_err:1; ++ }; ++ ushort reg67; ++ }; ++ union { ++ struct { ++ ushort reg68_s_marb_eimi_block:1; // miu emi/imi block, 0: disable ++ ushort reg68_s_marb_lbwd_mode:1; // low bandwidth mode, 0: disable ++ ushort reg68_s_marb_imi_burst_thd:5;// imi write burst bunch up threshold ++ ushort reg68_s_marb_imi_timeout:3; // imi write burst timeout ++ ushort reg68_s_marb_imilast_thd:4; // auto mfe2imi_last threshold ++ ushort reg68_s_prfh_cryc_en:1; // 0: disable prfh_cryc circuit, 1: enable prfh_cryc circuit ++ ushort reg68_s_prfh_refy_en:1; // 0: disable prfh_refy circuit, 1: enable prfh_refy circuit ++ }; ++ ushort reg68; ++ }; ++ union { ++ struct { ++ ushort reg69_g_pat_gen_init:16; // pattern generation initial value ++ }; ++ ushort reg69; ++ }; ++ union { ++ struct { ++ ushort reg6a_s_bspobuf_idx:2; // HW obuf index(0->1->2->3->0->1¡K) ++ // SW obuf index(00->01->11->10->00...) ++ ushort reg6a_s_obuf0_status:1; ++ ushort reg6a_s_obuf1_status:1; ++ // regmfe_s_bspobuf_adr_status:6 ++ // {reg6a_fifo_not_full, reg6a_fifo_not_empty, reg6a_enable_obufadr_update, reg6a_obufadr_update_cnt[2:0]} ++ ushort reg6a_obufadr_update_cnt:3; ++ ushort reg6a_enable_obufadr_update:1; ++ ushort reg6a_fifo_not_empty:1; ++ ushort reg6a_fifo_not_full:1; ++ }; ++ ushort reg6a; ++ }; ++ union { ++ struct { ++ ushort reg6b_s_marb_imi_saddr_lo:IMIBUFF_LO_BITS; // imi base address for low bandwidth mode (in 8-byte unit) ++ }; ++ ushort reg6b; ++ }; ++ union { ++ struct { ++ ushort reg6c_s_marb_imi_saddr_hi:IMIBUFF_HI_BITS; ++#if ((16-IMIBUFF_HI_BITS-1-2)>0) ++ ushort reg6c_reserved:16-IMIBUFF_HI_BITS-1-2; ++#endif ++ ushort reg6c_s_marb_rimi_force:1; //b1:force all read path to IMI 'b0:Normal ++ ushort reg6c_s_marb_imi_cache_size:2; // imi cache size (0: 64kB, 1:32kB, 2:16kB, 3:8kB) ++ }; ++ ushort reg6c; ++ }; ++ union { ++ struct { ++ ushort reg6d_s_marb_imipriority_thd:4; //hardware mfe2imi_priority threshold ++ ushort reg6d_s_marb_imipriority_sw:2; //mfe2imi_priority software programmable ++ ushort reg6d_reserved:2; ++ ushort reg6d_s_prfh_cryc_idle_cnt:4; // prfh idle count (x 16T) for prfh_cryc ++ ushort reg6d_s_prfh_refy_idle_cnt:4; // prfh idle count (x 16T) for prfh_refy ++ }; ++ ushort reg6d; ++ }; ++ union { ++ struct { ++ ushort reg6e_s_mbr_qstep_min:7; // qstep min (note: max value of qstep_min is 128 because condition is qstep <= qstep_min) ++ }; ++ ushort reg6e; ++ }; ++ union { ++ struct { ++ ushort reg6f_s_mbr_qstep_max:13; // qstep max ++ }; ++ ushort reg6f; ++ }; ++ union { ++ struct { ++ ushort reg70_g_debug_mode:7; // debug mode ++ ushort reg70_g_debug_trig_cycle:9; // wait (8 * reg70_g_debug_trig_cycle) cycles ++ }; ++ ushort reg70; ++ }; ++ union { ++ struct { ++ ushort reg71_g_debug_trig_mbx:9; // debug trigger mbx ++ }; ++ ushort reg71; ++ }; ++ union { ++ struct { ++ ushort reg72_g_debug_trig_mby:9; // debug trigger mby ++ }; ++ ushort reg72; ++ }; ++ union { ++ struct { ++ ushort reg73_g_debug_trig:1; // reg trigger (write one clear) ++ ushort reg73_g_debug_trig_mode:2; // debug trigger mode; 0/1/2/3: reg_trigger/3rd stage (mbx, mby)/frame start ++ ushort reg73_g_debug_en:1; // debug enable ++ ushort reg73_g_crc_mode:4; //'h0: Disable,¡¥hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf ++ ushort reg73_g_debug_tcycle_chk_en:1; //enable total cycle check ++ ushort reg73_g_debug_tcycle_chk_sel:1; //select total cycle and report it on regmfe_g_crc_result[15:0] ++ ushort reg73_g_sw_buffer_mode:1; // 0/1: hw/sw buffer mode ++ ushort reg73_g_sw_row_done:1; // sw row done (1T clk_jpe) (write one clear) ++ ushort reg73_g_sw_vs:1; // sw vsync (1T clk_jpe) (write one clear) ++ ushort reg73_g_pat_gen_en:1; // enable pattern generation ++ ushort reg73_g_row_down_irq_en:1; // row done irq enable; 0: disable, 1: enable ++ ushort reg73_g_vs_irq_en:1; // vs irq enable; 0: disable, 1: enable ++ }; ++ ushort reg73; ++ }; ++ union { ++ struct { ++ ushort reg74_g_debug_state0:16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, ++ // txip2mve_en, txip2mcobuf_en, txip2mbldr_en, ecdb2mdc_en, ++ // ecdb2rlc_en, ecdb2vlc_en, 5'd0}" ++ }; ++ ushort reg74; ++ }; ++ union { ++ struct { ++ ushort reg75_g_debug_state1; // "debug state for ME submodule {3'd0, load_w4_ok, load_w3_ok, load_w2_ok, load_w1_ok, load_w0_ok, 2'd0, ++ // busy_ime, busy_fme, busy_mesr, busy_iacost, end_this_mb, init_this_mb" ++ }; ++ ushort reg75; ++ }; ++ union { ++ struct { ++ ushort reg76_g_crc_result0:16; // CRC64[15..0] ++ }; ++ ushort reg76; ++ }; ++ union { ++ struct { ++ ushort reg77_g_crc_result1:16; // CRC64[31..16] ++ }; ++ ushort reg77; ++ }; ++ union { ++ struct { ++ ushort reg78_g_crc_result2:16; // CRC64[47..32] ++ }; ++ ushort reg78; ++ }; ++ union { ++ struct { ++ ushort reg79_g_crc_result3:16; // CRC64[63..48] ++ }; ++ ushort reg79; ++ }; ++ union { ++ struct { ++ ushort reg7a_g_bist_fail0; ++ }; ++ ushort reg7a; ++ }; ++ union { ++ struct { ++ ushort reg7b_g_bist_fail1; ++ }; ++ ushort reg7b; ++ }; ++ union { ++ struct { ++ ushort reg7c_g_bist_fail2; ++ }; ++ ushort reg7c; ++ }; ++ union { ++ struct { ++ ushort reg7d_s_txip_eco0:1; //0: original, 1: fix mbldr_cry_done, mbldr_crc_done bug ++ ushort reg7d_s_txip_eco1:1; //reserved registers ++ ushort reg7d_eco_mreq_stallgo:1; //reg7d_eco_mreq_stallgo ++ ushort reg7d_eco_marb_stallgo:1; //reg7d_eco_marb_stallgo ++ ushort reg7d_reserved1:2; ++ ushort reg7d_eco_bsp_rdy_fix:1; ++ ushort reg7d_eco_bsp_multi_slice_fix:1; ++ ushort reg7d_reserved2:6; ++ ushort reg7d_g_secure_obufadr:1; ++ ushort reg7d_g_secure_miu_sel:1; ++ }; ++ ushort reg7d; ++ }; ++ union { ++ struct { ++ ushort reg7e_rsv1; ++ }; ++ ushort reg7e; ++ }; ++ union { ++ struct { ++ ushort reg7f_rsv2; ++ }; ++ ushort reg7f; ++ }; ++} mfe_regs; ++ ++void mfe_regs_power_on(void* iobase, int on, int power_level); ++void mfe_regs_enc_fire(void* iobase, mfe_regs* regs); ++void mfe_regs_enc_done(void* iobase, mfe_regs* regs); ++uint mfe_regs_enc_wait(void* iobase); ++ ++#endif//_MFE_REGS_H_ +diff --git a/drivers/mstar/mfe/inc/types.h b/drivers/mstar/mfe/inc/types.h +new file mode 100644 +index 00000000..47605b5c +--- /dev/null ++++ b/drivers/mstar/mfe/inc/types.h +@@ -0,0 +1,25 @@ ++ ++#ifndef _TYPES_H_ ++#define _TYPES_H_ ++ ++typedef unsigned char uchar; ++typedef unsigned short ushort; ++typedef unsigned int uint; ++ ++typedef unsigned char uint8; ++typedef unsigned short uint16; ++typedef unsigned int uint32; ++typedef unsigned long long uint64; ++typedef signed char int8; ++typedef signed short int16; ++typedef signed int int32; ++typedef signed long long int64; ++ ++#define MST_ASSERT(p) ++ ++#define I_VOP 0 ++#define P_VOP 1 ++#define B_VOP 2 ++ ++#endif ++ +diff --git a/drivers/mstar/mfe/mmfe_module.c b/drivers/mstar/mfe/mmfe_module.c +new file mode 100644 +index 00000000..5697b71d +--- /dev/null ++++ b/drivers/mstar/mfe/mmfe_module.c +@@ -0,0 +1,258 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++MODULE_LICENSE("GPL"); ++ ++static mst_dev* mstmfe; ++ ++static int ++mstmfe_open( ++ struct inode* inode, ++ struct file* file) ++{ ++ mst_ctx* ctx = kzalloc(sizeof(mst_ctx), GFP_KERNEL); ++ mfe_asic* d = mstmfe->dev_data; ++ ++ if (ctx) ++ { ++ mfe_hdlr* h = NULL; ++ ctx->mdev = mstmfe; ++ if (mfe_hdlr_request(&ctx->drv_data)) ++ { ++ kfree(ctx); ++ return -ENOMEM; ++ } ++ h = ctx->drv_data; ++ h->asic = d; ++ file->private_data = ctx; ++ return 0; ++ } ++ ++ return -ENOMEM; ++} ++ ++static int ++mstmfe_release( ++ struct inode* inode, ++ struct file* file) ++{ ++ mst_ctx* ctx = file->private_data; ++ mfe_hdlr* h = (mfe_hdlr*)ctx->drv_data; ++ ++ ctx->mdev = NULL; ++ if (h && h->regs) ++ { ++ kfree(h->regs); ++ } ++ mfe_hdlr_release(h); ++ kfree(ctx); ++ file->private_data = NULL; ++ ++ return 0; ++} ++ ++static long ++mstmfe_ioctl( ++ struct file* file, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ size_t n = _IOC_SIZE(cmd); ++ char buf[256]; ++ long err = 0; ++ void __user *uptr = (void __user *)arg; ++ void* mfh = file->private_data; ++ ++ if ((_IOC_DIR(cmd) & _IOC_WRITE) && copy_from_user(buf, uptr, n)) ++ { ++ return -EFAULT; ++ } ++ if (0 != (err = mstmfe_ops(mfh, cmd, buf))) ++ { ++ return err; ++ } ++ if ((_IOC_DIR(cmd) & _IOC_READ) && copy_to_user(uptr, buf, n)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static struct class mstar_class = { ++ .name = "mstar", ++ .owner = THIS_MODULE, ++}; ++ ++struct file_operations mst_fops = { ++ .owner = THIS_MODULE, ++ .open = mstmfe_open, ++ .release = mstmfe_release, ++ .unlocked_ioctl = mstmfe_ioctl, ++}; ++ ++static void mstmfe_dev_release(struct device* dev) {} ++ ++static int mstmfe_major = 0; ++static int mstmfe_minor = 0; ++ ++static int ++mstmfe_probe( ++ struct platform_device* pdev) ++{ ++ int err = 0; ++ dev_t dev; ++ mfe_asic* d = NULL; ++ struct resource* res; ++ ++ if (0 > (err = alloc_chrdev_region(&dev, mstmfe_minor, 1, "mstar"))) ++ { ++ return err; ++ } ++ ++ mstmfe_major = MAJOR(dev); ++ ++ if (!(mstmfe = kzalloc(sizeof(mst_dev), GFP_KERNEL))) ++ { ++ goto err_exit; ++ } ++ d = kzalloc(sizeof(mfe_asic), GFP_KERNEL); ++ mstmfe->dev_data = d; ++ ++ if (NULL == (mstmfe->cdev = cdev_alloc())) ++ { ++ goto err_exit; ++ } ++ mstmfe->cdev->ops = &mst_fops; ++ mstmfe->cdev->owner = THIS_MODULE; ++ ++ if (0 > (err = cdev_add(mstmfe->cdev,MKDEV(mstmfe_major,mstmfe_minor), 1))) ++ { ++ return err; ++ } ++ mstmfe->ldev.devt = MKDEV(mstmfe_major,mstmfe_minor); ++ mstmfe->ldev.class = &mstar_class; ++ mstmfe->ldev.parent = NULL; ++ mstmfe->ldev.release = mstmfe_dev_release; ++ dev_set_name(&mstmfe->ldev, "%s", "mmfe"); ++ ++ if (0 > (err = device_register(&mstmfe->ldev))) ++ { ++ cdev_del(mstmfe->cdev); ++ return err; ++ } ++ mstmfe->pdev = &pdev->dev; ++ ++ d->lock = &mstmfe->mutex; ++ mutex_init(d->lock); ++ d->i_ctx_count = 0; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ d->p_pmbase = (void*)res->start; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ d->p_iobase = (void*)res->start; ++ ++ printk("mmfe built at %s on %s\n",__TIME__,__DATE__); ++ ++ return err; ++ ++err_exit: ++ if (mstmfe && mstmfe->dev_data) ++ { ++ kfree(mstmfe->dev_data); ++ } ++ if (mstmfe) ++ { ++ kfree(mstmfe); ++ } ++ if (mstmfe->cdev) ++ { ++ cdev_del(mstmfe->cdev); ++ } ++ mstmfe = NULL; ++ ++ return err; ++} ++ ++static int ++mstmfe_remove( ++ struct platform_device* pdev) ++{ ++ int devno = MKDEV(mstmfe_major,mstmfe_minor); ++ ++ kfree(mstmfe->dev_data); ++ cdev_del(mstmfe->cdev); ++ ++ device_unregister(&mstmfe->ldev); ++ ++ kfree(mstmfe); ++ mstmfe = NULL; ++ ++ unregister_chrdev_region(devno, 1); ++ ++ return 0; ++} ++ ++static const struct of_device_id mmfe_of_match_tables[] = { ++ { .compatible = "mstar,mfe" }, ++ {}, ++}; ++static struct platform_driver mstmfe_pdrv = { ++ .probe = mstmfe_probe, ++ .remove = mstmfe_remove, ++ .driver = { ++ .name = "mmfe", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(mmfe_of_match_tables), ++ } ++}; ++ ++static int __init mstmfe_init(void) ++{ ++ int err = 0; ++ ++ if (0 > (err = class_register(&mstar_class))) ++ { ++ class_unregister(&mstar_class); ++ return err; ++ } ++ ++ return platform_driver_register(&mstmfe_pdrv); ++} ++ ++static void __exit mstmfe_exit(void) ++{ ++ platform_driver_unregister(&mstmfe_pdrv); ++ ++ class_unregister(&mstar_class); ++} ++ ++module_init(mstmfe_init); ++module_exit(mstmfe_exit); ++ +diff --git a/drivers/mstar/mfe/mmfe_ops.c b/drivers/mstar/mfe/mmfe_ops.c +new file mode 100644 +index 00000000..844b455b +--- /dev/null ++++ b/drivers/mstar/mfe/mmfe_ops.c +@@ -0,0 +1,467 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int mfe_ops_streamon(void*, int on); ++static int mfe_ops_enc_pict(void*, mmfe_buffer* b); ++static int mfe_ops_get_bits(void*, mmfe_buffer* b); ++static int mfe_ops_set_parm(void*, mmfe_params* p); ++static int mfe_ops_get_parm(void*, mmfe_params* p); ++ ++long ++mstmfe_ops( ++ void* mfh, ++ unsigned int cmd, ++ void* arg) ++{ ++ int err = 0; ++ ++ switch (cmd) ++ { ++ case IOCTL_MFE_S_PARM: ++ err = mfe_ops_set_parm(mfh, (mmfe_params*)arg); ++ break; ++ case IOCTL_MFE_G_PARM: ++ err = mfe_ops_get_parm(mfh, (mmfe_params*)arg); ++ break; ++ case IOCTL_MFE_STREAMON: ++ err = mfe_ops_streamon(mfh, 1); ++ break; ++ case IOCTL_MFE_STREAMOFF: ++ err = mfe_ops_streamon(mfh, 0); ++ break; ++ case IOCTL_MFE_S_PICT: ++ err = mfe_ops_enc_pict(mfh, (mmfe_buffer*)arg); ++ break; ++ case IOCTL_MFE_G_BITS: ++ err = mfe_ops_get_bits(mfh, (mmfe_buffer*)arg); ++ break; ++ default: ++ err = -EINVAL; ++ break; ++ } ++ ++ return (long)err; ++} ++ ++static const char* KEY_MFE_DMEM="MFE_DMEM"; ++ ++#define MIU_ALIGN(b,a) (((a)+(1<<(b))-1)&(~((1<<(b))-1))) ++#define CPB_SIZE (1024*1024) ++ ++static int ++request_kma( ++ struct device* dev, ++ kma_t* kma, ++ int reqsize) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name, KEY_MFE_DMEM, strlen(KEY_MFE_DMEM)+1); ++ dmem.length = reqsize; ++ if (0 != msys_request_dmem(&dmem)) ++ { ++ kma->mem_vptr = NULL; ++ kma->bus_addr = 0; ++ kma->miu_addr = 0; ++ kma->size = 0; ++ return -ENOMEM; ++ } ++ kma->mem_vptr = (void*)((uintptr_t)dmem.kvirt); ++ kma->bus_addr = dmem.phys; ++ kma->miu_addr = Chip_Phys_to_MIU(dmem.phys); ++ kma->size = dmem.length; ++ ++ return 0; ++} ++ ++static int ++release_kma( ++ struct device* dev, ++ kma_t* kma) ++{ ++ MSYS_DMEM_INFO dmem; ++ if (!kma || !kma->mem_vptr) ++ { ++ return -EINVAL; ++ } ++ memcpy(dmem.name, KEY_MFE_DMEM, strlen(KEY_MFE_DMEM)+1); ++ dmem.length = kma->size; ++ dmem.kvirt = (unsigned long long)((uintptr_t)kma->mem_vptr); ++ dmem.phys = (unsigned long long)((uintptr_t)kma->bus_addr); ++ msys_release_dmem(&dmem); ++ ++ return 0; ++} ++ ++static int ++mfe_ops_streamon( ++ void* mfh, ++ int on) ++{ ++ mst_ctx* ctx = (mst_ctx*)mfh; ++ mfe_hdlr* h = (mfe_hdlr*)ctx->drv_data; ++ mfe_asic* d = h->asic; ++ int err = 0; ++ ++ /* check valid parameters */ ++ if (on) ++ { ++ if (h->i_display_w <= 0 || h->i_display_h <= 0) ++ { ++ return -EINVAL; ++ } ++ if (h->i_bps <= 0) ++ { ++ return -EINVAL; ++ } ++ if (h->fr_fps.num < h->fr_fps.den || h->fr_fps.den <= 0) ++ { ++ return -EINVAL; ++ } ++ } ++ ++ mutex_lock(&h->stream_lock); ++ if (on) ++ { ++ int i, total_size, bs_size, gn_size, luma_size, cbcr_size; ++ uint32 rambase; ++ /* set external parameters */ ++ h->i_codec_type = REG_ENC_MODE_H264; ++ /* reset counters */ ++ h->i_seq_numb = h->i_cnt_ppic = 0; ++ h->i_num_bpic = h->i_cnt_bpic = 0; ++ h->i_last_bits = 0; ++ h->i_stat_size = 0; ++ h->i_pic_avgqp = 0; ++ /* intermediate parameters */ ++ h->i_mb_w = h->i_picture_w>>4; ++ h->i_mb_h = h->i_picture_h>>4; ++ h->i_mb_wxh = h->i_mb_w * h->i_mb_h; ++ h->i_num_ref_frames = 1; ++ /* .... */ ++ h->clk_speed = speed_high; ++ h->pixel_fmt = pixel_tile_8x8; ++ /* allocate output buffer */ ++ h->p_outbuf = kzalloc(CPB_SIZE, GFP_KERNEL); ++ h->i_outlen = CPB_SIZE; ++ h->i_uselen = 0; ++ h->i_remlen = 0; ++ /* bit rate control */ ++ h->cvbr.m_nVPMbRow = MFE_ER_MBY; ++ h->cvbr.m_nVPSize = MFE_ER_BS_TH; ++ /* calculate required buffer size */ ++ bs_size = CPB_SIZE; ++ gn_size = MIU_ALIGN(8,64*h->i_mb_w); ++ luma_size = MIU_ALIGN(8,256*h->i_mb_wxh); ++ cbcr_size = MIU_ALIGN(8,128*h->i_mb_wxh); ++ total_size = gn_size + bs_size + (luma_size + cbcr_size) * (h->i_num_ref_frames + 1); ++ /* requeset required dma-buff from system */ ++ if (!(err = request_kma(ctx->mdev->pdev, &h->kma, total_size))) ++ { /* layout allocated buffer to GN/frames/outbs */ ++ rambase = h->kma.miu_addr; ++ h->p_vptr_bs = h->kma.mem_vptr; ++ h->i_base_bs = rambase; ++ h->i_size_bs = bs_size; ++ rambase += h->i_size_bs; ++ h->i_base_gn = rambase; ++ h->i_size_gn = gn_size; ++ rambase += h->i_size_gn; ++ for (i = 0; i <= h->i_num_ref_frames; i++) ++ { ++ h->frames[i].i_idx = i; ++ h->frames[i].b_busy = 0; ++ h->frames[i].base_y = rambase; ++ rambase += luma_size; ++ h->frames[i].base_c = rambase; ++ rambase += cbcr_size; ++ } ++ if (!(err = mfe_hdlr_seq_init(h))) ++ { ++ mutex_lock(d->lock); ++ if (0 == d->i_ctx_count++) ++ { ++ mfe_regs_power_on(d->p_pmbase, 1, 4); ++ } ++ mutex_unlock(d->lock); ++ ++ h->b_stream = 1; ++ } ++ else ++ { ++ release_kma(ctx->mdev->pdev, &h->kma); ++ } ++ } ++ } ++ else ++ { ++ release_kma(ctx->mdev->pdev, &h->kma); ++ ++ printk("cpb<-end->-%8d-\n",h->i_stat_size); ++ ++ mfe_hdlr_seq_exit(h); ++ ++ mutex_lock(d->lock); ++ if (0 == --d->i_ctx_count) ++ { ++ mfe_regs_power_on(d->p_pmbase, 0, 0); ++ } ++ mutex_unlock(d->lock); ++ ++ h->b_stream = 0; ++ } ++ mutex_unlock(&h->stream_lock); ++ ++ return err; ++} ++ ++static int ++mfe_ops_enc_pict( ++ void* mfh, ++ mmfe_buffer* buf) ++{ ++ mst_ctx* ctx = (mst_ctx*)mfh; ++ mfe_hdlr* h = (mfe_hdlr*)ctx->drv_data; ++ mfe_asic* d = h->asic; ++ void* iobase = d->p_iobase; ++ uint irq = 0; ++ int err = -EBUSY; ++ ++ if (buf->i_memory != MEMORY_MMAP || buf->i_planes != 2) ++ { ++ return -EINVAL; ++ } ++ ++ mutex_lock(&h->encode_lock); ++ if (!h->i_encode) ++ { ++ h->i_encode = 1; ++ /* picture type decision */ ++ mfe_hdlr_pic_mode(h); ++ ++ h->input.base_y = buf->planes[0].addr; ++ h->input.base_c = buf->planes[1].addr; ++ h->i_timecode = buf->timecode; ++ ++ mfe_hdlr_pic_init(h); ++ mfe_hdlr_pic_prep_regs(h); ++ ++ mutex_lock(d->lock); ++ mfe_regs_enc_fire(iobase, h->regs); ++ irq = mfe_regs_enc_wait(iobase); ++ mfe_regs_enc_done(iobase, h->regs); ++ mutex_unlock(d->lock); ++ ++ mfe_hdlr_pic_done(h); ++ mfe_hdlr_pic_read_bits(h); ++ ++ h->i_encode = 2; ++ err = 0; ++ } ++ mutex_unlock(&h->encode_lock); ++ ++ return err; ++} ++ ++static int ++mfe_ops_get_bits( ++ void* mfh, ++ mmfe_buffer* buf) ++{ ++ mst_ctx* ctx = (mst_ctx*)mfh; ++ mfe_hdlr* h = (mfe_hdlr*)ctx->drv_data; ++ int err = -ENODATA; ++ ++ if (buf->i_memory != MEMORY_USER || buf->i_planes != 1) ++ { ++ return -EINVAL; ++ } ++ ++ mutex_lock(&h->encode_lock); ++ if (h->i_encode > 1) ++ { ++ int rem = h->i_remlen; ++ int use = h->i_uselen; ++ uchar* ptr = h->p_outbuf; ++ ptr = ptr + use - rem; ++ ++ err = -EFAULT; ++ if (buf->planes[0].size < rem) ++ { ++ rem = buf->planes[0].size; ++ } ++ if (!copy_to_user(buf->planes[0].uptr, ptr, rem)) ++ { ++ buf->planes[0].used = rem; ++ buf->timecode = h->i_timecode; ++ h->i_remlen -= rem; ++ if (!h->i_remlen) ++ { ++ h->i_encode = 0; ++ h->i_uselen = 0; ++ } ++ err = 0; ++ printk("cpb<%5d>-%8d-%2d\n",h->i_seq_numb,rem,h->sh.i_qp); ++ } ++ } ++ mutex_unlock(&h->encode_lock); ++ ++ return err; ++} ++ ++static int ++mfe_ops_set_parm( ++ void* mfh, ++ mmfe_params* par) ++{ ++ mst_ctx* ctx = (mst_ctx*)mfh; ++ mfe_hdlr* h = (mfe_hdlr*)ctx->drv_data; ++ int err = 0; ++ ++ mutex_lock(&h->stream_lock); ++ if (!h->b_stream) ++ { ++ switch (par->i_params) ++ { ++ case MVIDPARAMS_PIXELS: ++ h->i_codec_type = REG_ENC_MODE_H264; ++ h->i_picture_w = MIU_ALIGN(4,par->pixels.i_pict_w); ++ h->i_picture_h = MIU_ALIGN(4,par->pixels.i_pict_h); ++ h->i_display_w = par->pixels.i_pict_w; ++ h->i_display_h = par->pixels.i_pict_h; ++ break; ++ case MVIDPARAMS_FRAMERATE: ++ h->fr_fps.num = par->framerate.i_num; ++ h->fr_fps.den = par->framerate.i_den; ++ break; ++ case MVIDPARAMS_MOTION: ++ h->i_subpel = par->motion.i_subpel; ++ h->i_dmv_x = (par->motion.i_dmv_x); ++ h->i_dmv_x = h->i_dmv_x < 8 ? 8 : h->i_dmv_x; ++ h->i_dmv_x = h->i_dmv_x >16 ?16 : h->i_dmv_x; ++ h->i_dmv_y = (par->motion.i_dmv_y+7)&~7; ++ h->i_dmv_y = h->i_dmv_y ==8 ? 8 : 16; ++ h->i_mv_block[0] = par->motion.i_mv_block[0]; ++ h->i_mv_block[1] = 0; ++ break; ++ case MVIDPARAMS_BITRATE: ++ h->i_method = par->bitrate.i_method; ++ h->i_bps = par->bitrate.i_kbps * 1024; ++ h->i_qp = par->bitrate.i_qp; ++ break; ++ case MVIDPARAMS_GOP: ++ h->i_num_ppic = par->gop.i_pframes; ++ h->i_num_bpic = 0; ++ break; ++ case MVIDPARAMS_AVC: ++ { ++ sps_t* sps = &h->sps; ++ pps_t* pps = &h->pps; ++ slice_t* sh = &h->sh; ++ h->i_num_ref_frames = 1; ++ sps->i_profile_idc = 66; // baseline profile ++ sps->i_level_idc = 30; ++ pps->b_cabac = 0; ++ pps->b_deblocking_filter_control = par->avc.b_deblock_filter_control; ++ pps->b_constrained_intra_pred = par->avc.b_constrained_intra_pred; ++ sh->i_disable_deblocking_filter_idc = par->avc.i_disable_deblocking_idc; ++ sh->i_alpha_c0_offset = par->avc.i_alpha_c0_offset; ++ sh->i_beta_offset = par->avc.i_beta_offset; ++ } ++ break; ++ default: ++ printk("unsupported config\n"); ++ err = -EINVAL; ++ break; ++ } ++ } ++ else ++ { ++ err = -EINVAL; ++ } ++ mutex_unlock(&h->stream_lock); ++ ++ return err; ++} ++ ++static int ++mfe_ops_get_parm( ++ void* mfh, ++ mmfe_params* par) ++{ ++ mst_ctx* ctx = (mst_ctx*)mfh; ++ mfe_hdlr* h = (mfe_hdlr*)ctx->drv_data; ++ int err = 0; ++ ++ mutex_lock(&h->stream_lock); ++ switch (par->i_params) ++ { ++ case MVIDPARAMS_PIXELS: ++ par->pixels.i_pict_w = h->i_display_w; ++ par->pixels.i_pict_h = h->i_display_h; ++ par->pixels.i_pixfmt = 0; ++ break; ++ case MVIDPARAMS_FRAMERATE: ++ par->framerate.i_num = h->fr_fps.num; ++ par->framerate.i_den = h->fr_fps.den; ++ break; ++ case MVIDPARAMS_MOTION: ++ par->motion.i_dmv_x = h->i_dmv_x; ++ par->motion.i_dmv_y = h->i_dmv_y; ++ par->motion.i_subpel = h->i_subpel; ++ par->motion.i_mv_block[0] = h->i_mv_block[0]; ++ par->motion.i_mv_block[1] = 0; ++ break; ++ case MVIDPARAMS_BITRATE: ++ par->bitrate.i_method = h->i_method; ++ par->bitrate.i_kbps = h->i_bps>>10; ++ par->bitrate.i_qp = h->i_qp; ++ break; ++ case MVIDPARAMS_GOP: ++ par->gop.i_pframes = h->i_num_ppic; ++ par->gop.i_bframes = 0; ++ break; ++ case MVIDPARAMS_AVC: ++ { ++ sps_t* sps = &h->sps; ++ pps_t* pps = &h->pps; ++ slice_t* sh = &h->sh; ++ par->avc.i_profile = sps->i_profile_idc; ++ par->avc.i_level = sps->i_level_idc; ++ par->avc.i_num_ref_frames = 1; ++ par->avc.b_cabac = pps->b_cabac; ++ par->avc.b_deblock_filter_control = pps->b_deblocking_filter_control; ++ par->avc.b_constrained_intra_pred = pps->b_constrained_intra_pred; ++ par->avc.i_disable_deblocking_idc = sh->i_disable_deblocking_filter_idc; ++ par->avc.i_alpha_c0_offset = sh->i_alpha_c0_offset; ++ par->avc.i_beta_offset = sh->i_beta_offset; ++ par->avc.b_multiple_slices = 0; ++ } ++ break; ++ default: ++ printk("unsupported config\n"); ++ err = -EINVAL; ++ break; ++ } ++ mutex_unlock(&h->stream_lock); ++ ++ return err; ++} ++ +diff --git a/drivers/mstar/mfe/mmfe_ops.h b/drivers/mstar/mfe/mmfe_ops.h +new file mode 100644 +index 00000000..a6f28bbb +--- /dev/null ++++ b/drivers/mstar/mfe/mmfe_ops.h +@@ -0,0 +1,8 @@ ++ ++#ifndef _MMFE_OPS_H_ ++#define _MMFE_OPS_H_ ++ ++long mstmfe_ops(void*, unsigned int, void*); ++ ++#endif//_MMFE_OPS_H_ ++ +diff --git a/drivers/mstar/mfe/mst_def.h b/drivers/mstar/mfe/mst_def.h +new file mode 100644 +index 00000000..76f89766 +--- /dev/null ++++ b/drivers/mstar/mfe/mst_def.h +@@ -0,0 +1,19 @@ ++ ++#ifndef _MST_DEF_H_ ++#define _MST_DEF_H_ ++ ++typedef struct mst_dev { ++ struct cdev* cdev; // character device ++ struct device ldev; // device node ++ struct device* pdev;// platform device ++ struct mutex mutex; ++ void* dev_data; ++} mst_dev; ++ ++typedef struct mst_ctx { ++ mst_dev* mdev; ++ void* drv_data; ++} mst_ctx; ++ ++#endif//_MST_DEV_H_ ++ +diff --git a/drivers/mstar/mfe/src/mfe_asic.c b/drivers/mstar/mfe/src/mfe_asic.c +new file mode 100644 +index 00000000..9b30c4f1 +--- /dev/null ++++ b/drivers/mstar/mfe/src/mfe_asic.c +@@ -0,0 +1,261 @@ ++ ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define REGR(base,idx,cmt) ms_readw(((uint)base+(idx)*4)) ++#define REGW(base,idx,val,cmt) ms_writew(val,((uint)base+(idx)*4)) ++ ++static void clear_irq(void* iobase, uint bits) { ++ REGW(iobase,0x1d,bits,"clear irq"); ++} ++ ++static void set_outbs_addr(void* iobase, mfe_regs* reg, uint32 base, int len) { ++ uint32 value; ++ // Enable set-obuf ++ reg->reg3f_s_bspobuf_update_adr = 1; ++ REGW(iobase,0x3f,reg->reg3f,"ref_mfe_s_bspobuf_update_adr"); ++ reg->reg3f_s_bspobuf_update_adr = 0; // write-one-clear ++ // address value ++ value = base; ++ reg->reg3e = 0; ++ // For Safety ++ reg->reg3e_s_obuf_write_id_adr = 0; ++ REGW(iobase,0x3e,reg->reg3e,"write_id_addr"); ++ REGW(iobase,0x3e,reg->reg3e,"write_id_addr"); ++ reg->reg3c_s_bspobuf_lo = (uint16)(value>> 3); ++ reg->reg3d_s_bspobuf_hi = (uint16)(value>>19); ++ reg->reg3d_s_obuf_id = 0; // sta. addr ++ REGW(iobase,0x3c,reg->reg3c,"bspobuf addr_lo"); ++ REGW(iobase,0x3d,reg->reg3d,"bspobuf addr_hi"); ++ reg->reg3e_s_obuf_write_id_adr = 1; ++ REGW(iobase,0x3e,reg->reg3e,"write_id_addr"); ++ value += len; ++ // For Safety ++ reg->reg3e_s_obuf_write_id_adr = 0; ++ REGW(iobase,0x3e,reg->reg3e,"write_id_addr"); ++ REGW(iobase,0x3e,reg->reg3e,"write_id_addr"); ++ reg->reg3c_s_bspobuf_lo = (uint16)(value>> 3); ++ reg->reg3d_s_bspobuf_hi = (uint16)(value>>19); ++ reg->reg3d_s_obuf_id = 1; // end. addr ++ REGW(iobase,0x3c,reg->reg3c,"bspobuf addr_lo"); ++ REGW(iobase,0x3d,reg->reg3d,"bspobuf addr_hi"); ++ reg->reg3e_s_obuf_write_id_adr = 1; ++ REGW(iobase,0x3e,reg->reg3e,"write_id_addr"); ++ // address set ++ reg->reg3b_s_mvobuf_set_adr = 0; ++ reg->reg3b_s_mvobuf_fifo_th = 0; ++ reg->reg3b_s_bspobuf_fifo_th = 1; ++ reg->reg3b_s_bspobuf_set_adr = 1; ++ REGW(iobase,0x3b,reg->reg3b,"set bsp obuf"); ++ reg->reg3b_s_bspobuf_set_adr = 0; // HW is write-one-clear ++} ++ ++static void put_coded_bits(void* iobase, mfe_regs* reg, uchar* code, int len) { ++ int round = (len+15)>>4; ++ ushort word = 0; ++ ++ reg->reg46 = reg->reg47 = reg->reg48 = 0; ++ ++ if (len == 0) { ++ reg->reg47_s_fdc_bs_count = 0; ++ REGW(iobase,0x47,reg->reg47,"fdc round count"); ++ reg->reg46_s_fdc_bs = 0; ++ reg->reg47_s_fdc_bs_len = 0; ++ reg->reg48_s_fdc_bs_vld = 1; ++ REGW(iobase,0x46,reg->reg46,"fdc bs "); ++ REGW(iobase,0x47,reg->reg47,"fdc len"); ++ REGW(iobase,0x48,reg->reg48,"fdc vld"); ++ reg->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ return; ++ } ++ // Fill the total round reg ++ reg->reg47_s_fdc_bs_count = round - 1; // Count from 0 ++ REGW(iobase,0x47,reg->reg47,"fdc round count"); ++ ++ while (len > 16) { ++ word = (code[0]<<8) | code[1]; ++ code += 2; ++ len -= 16; ++ ++ reg->reg46_s_fdc_bs = word; ++ reg->reg47_s_fdc_bs_len = 15; ++ reg->reg48_s_fdc_bs_vld = 1; ++ REGW(iobase,0x46,reg->reg46,"fdc bs "); ++ REGW(iobase,0x47,reg->reg47,"fdc len"); ++ REGW(iobase,0x48,reg->reg48,"fdc vld"); ++ reg->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ } ++ ++ if (len > 0) { ++ word = code[0]<<8; ++ if (len > 8) { ++ word += code[1]; ++ } ++ reg->reg46_s_fdc_bs = word; ++ reg->reg47_s_fdc_bs_len = len; ++ reg->reg48_s_fdc_bs_vld = 1; ++ REGW(iobase,0x46,reg->reg46,"fdc bs "); ++ REGW(iobase,0x47,reg->reg47,"fdc len"); ++ REGW(iobase,0x48,reg->reg48,"fdc vld"); ++ reg->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ } ++} ++ ++void mfe_regs_power_on(void* iobase, int on, int power_level) { ++ if (!on) { ++ REGW(iobase,0x18,0x01,"power off mfe"); ++ } ++ else { ++ switch (power_level) { ++ case 0: ++ REGW(iobase,0x18,0x01,"power off mfe"); ++ break; ++ case 1: ++ REGW(iobase,0x18,0x00,"power on very slow"); ++ break; ++ case 2: ++ REGW(iobase,0x18,0x04,"power on slow"); ++ break; ++ case 3: ++ REGW(iobase,0x18,0x08,"power on medium"); ++ break; ++ case 4: ++ default: ++ REGW(iobase,0x18,0x12,"power on fast"); ++ break; ++ } ++ } ++} ++ ++void mfe_regs_enc_fire(void* iobase, mfe_regs* regs) { ++ /* flush regs to mfe-hw */ ++ clear_irq(iobase, 0x3F); ++ // switch to sw mode ++ regs->reg03_g_tbc_mode = 0; ++ REGW(iobase,0x03,regs->reg03,"tbc_mode=0"); ++ // switch to hw mode ++ regs->reg03_g_tbc_mode = 1; ++ REGW(iobase,0x03,regs->reg03,"tbc_mode=1"); ++ // sw reset ++ regs->reg00_g_soft_rstz = 0; ++ REGW(iobase,0x00,regs->reg00,"SW reset 0"); ++ regs->reg00_g_soft_rstz = 1; ++ REGW(iobase,0x00,regs->reg00,"SW reset 1"); ++ ++ REGW(iobase,0x01,regs->reg01,"pic width"); ++ REGW(iobase,0x02,regs->reg02,"pic height"); ++ REGW(iobase,0x03,regs->reg03,"value"); ++ REGW(iobase,0x04,regs->reg04,"er_bs mode threshold"); ++ REGW(iobase,0x05,regs->reg05,"inter prediction perference"); ++ /* set pict-buffer address */ ++ REGW(iobase,0x06,regs->reg06,"curr luma base addr_lo"); ++ REGW(iobase,0x07,regs->reg07,"curr luma base addr_hi"); ++ REGW(iobase,0x08,regs->reg08,"curr cbcr base addr_lo"); ++ REGW(iobase,0x09,regs->reg09,"curr cbcr base addr_hi"); ++ REGW(iobase,0x0a,regs->reg0a,"ref0 luma base addr_lo"); ++ REGW(iobase,0x0b,regs->reg0b,"ref0 luma base addr_hi"); ++ REGW(iobase,0x0c,regs->reg0c,"ref1 luma base addr_lo"); ++ REGW(iobase,0x0d,regs->reg0d,"ref1 luma base addr_hi"); ++ REGW(iobase,0x0e,regs->reg0e,"ref0 cbcr base addr_lo"); ++ REGW(iobase,0x0f,regs->reg0f,"ref0 cbcr base addr_hi"); ++ REGW(iobase,0x10,regs->reg10,"ref1 cbcr base addr_lo"); ++ REGW(iobase,0x11,regs->reg11,"ref1 cbcr base addr_hi"); ++ REGW(iobase,0x12,regs->reg12,"recn luma base addr_lo"); ++ REGW(iobase,0x13,regs->reg13,"recn luma base addr_hi"); ++ REGW(iobase,0x14,regs->reg14,"recn cbcr base addr_lo"); ++ REGW(iobase,0x15,regs->reg15,"recn cbcr base addr_hi"); ++ /*!set pict-buffer address */ ++ /* clock gating */ ++ REGW(iobase,0x16,regs->reg16,"clock gating"); ++ /* me setting */ ++ REGW(iobase,0x20,regs->reg20,"me partition setting"); ++ REGW(iobase,0x21,regs->reg21,"value"); ++ REGW(iobase,0x22,regs->reg22,"me search range max depth"); ++ REGW(iobase,0x23,regs->reg23,"me mvx"); ++ REGW(iobase,0x24,regs->reg24,"me mvy"); ++ REGW(iobase,0x25,regs->reg25,"FME"); ++ // GN ++ REGW(iobase,0x4c,regs->reg4c,"regmfe_s_gn_saddr_lo"); ++ REGW(iobase,0x4d,regs->reg4d,"regmfe_s_gn_saddr_hi"); ++ // MBR ++ REGW(iobase,0x26,regs->reg26,"MBR: mbbits"); ++ REGW(iobase,0x27,regs->reg27,"MBR: frame qstep"); ++ REGW(iobase,0x29,regs->reg29,"h264 qp offset"); ++ REGW(iobase,0x2a,regs->reg2a,"QP min/max"); ++ REGW(iobase,0x6e,regs->reg6e,"QStep min"); ++ REGW(iobase,0x6f,regs->reg6f,"QStep max"); ++ // INTRA UPDATE ++ REGW(iobase,0x2f,regs->reg2f,"value"); ++ REGW(iobase,0x30,regs->reg30,"value"); ++ REGW(iobase,0x31,regs->reg31,"value"); ++ REGW(iobase,0x32,regs->reg32,"value"); ++ // MDC ++ REGW(iobase,0x39,regs->reg39,"value"); ++ // DBF ++ REGW(iobase,0x3a,regs->reg3a,"value"); ++ ++ regs->reg73_g_crc_mode = 0xC; ++ regs->reg73_g_debug_tcycle_chk_en = 0x1; ++ regs->reg73_g_debug_tcycle_chk_sel = 0x0; ++ regs->reg73_g_debug_en = 0; // TEST ++ REGW(iobase,0x73,regs->reg73,"crc mode"); ++ REGW(iobase,0x2c,regs->reg2c,"last zigzag"); ++ // IEAP ++ REGW(iobase,0x2b,regs->reg2b,"ieap"); ++ // Cross-format wrong reg setting prevention ++ REGW(iobase,0x18,regs->reg18,"jpe encode mode"); ++ REGW(iobase,0x1b,regs->reg1b,"mpeg4 field dct"); ++ // regs->reg19 MUST be zero ++ REGW(iobase,0x19,0,"0/1:MPEG4 enable/disable p skip mode"); ++ // Prefetch & Low bandwidth mode ++ REGW(iobase,0x68,regs->reg68,"prefetch & low bandwidth mode"); ++ // Prefetch ++ REGW(iobase,0x6d,regs->reg6d,"prefetch mb idle count"); ++ // Low bandwidth ++ REGW(iobase,0x6b,regs->reg6b,"low bandwidth: IMI addr_lo"); ++ REGW(iobase,0x6c,regs->reg6c,"low bandwidth: IMI addr_hi"); ++ // Reset any StopAndGo or StopAndDrop setting. ++ regs->reg2d_s_txip_sng_mb = 0; ++ REGW(iobase,0x2d,regs->reg2d,"reg2d_s_txip_sng_mb=0"); ++ // enable eco item ++ REGW(iobase,0x7d,regs->reg7d,"reg7d_s_txip_eco0=1"); ++ /* set output address */ ++ set_outbs_addr(iobase, regs, regs->outbs_addr, regs->outbs_size); ++ /* Enable HW */ ++ regs->reg00_g_frame_start_sw = 1; ++ REGW(iobase,0x00,regs->reg00,"frame start"); ++ regs->reg00_g_frame_start_sw = 0; // HW is write-one-clear ++ /* write slice header */ ++ put_coded_bits(iobase, regs, regs->coded_data, regs->coded_bits); ++} ++ ++void mfe_regs_enc_done(void* iobase, mfe_regs* regs) { ++ regs->reg28 = REGR(iobase,0x28,"avg-qp:lo"); ++ regs->reg29 = REGR(iobase,0x29,"avg-qp:hi"); ++ regs->reg42 = REGR(iobase,0x42,"bits size:lo"); ++ regs->reg43 = REGR(iobase,0x43,"bits size:hi"); ++} ++ ++uint mfe_regs_enc_wait(void* iobase) { ++ ushort reg0x1e = 0; ++ ++ do { ++ reg0x1e = REGR(iobase,0x1e,"get irq"); ++ if (!reg0x1e) { ++ mdelay(8); ++ } ++ } while (!reg0x1e); ++ ++ return reg0x1e; ++} ++ +diff --git a/drivers/mstar/mfe/src/mfe_avc.c b/drivers/mstar/mfe/src/mfe_avc.c +new file mode 100644 +index 00000000..33a645f3 +--- /dev/null ++++ b/drivers/mstar/mfe/src/mfe_avc.c +@@ -0,0 +1,265 @@ ++ ++#include ++ ++#include ++ ++static void write_ebsp(bs_t* bs, uchar byte) { ++ if (bs->ebsp_zeros == 2 && byte < 4) { ++ *bs->curr++ = 0x03; ++ bs->ebsp_zeros = 0; ++ bs->bits_pos += 8; ++ } ++ if (byte == 0) { ++ bs->ebsp_zeros++; ++ } ++ *bs->curr++ = byte; ++} ++ ++int avc_reset(bs_t* bs, uchar* buff, int len) { ++ bs->bits_pos = 0; ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ bs->curr = bs->buffer = buff; ++ bs->length = len; ++ return 0; ++} ++ ++int avc_flush(bs_t* bs) { ++ ++ while (bs->left_count < 16) { ++ write_ebsp(bs, (uchar)(bs->code_bits>>8)); ++ bs->left_count += 8; ++ bs->code_bits <<= 8; ++ } ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ return bs->bits_pos; ++} ++ ++int avc_count(bs_t* bs) { ++ return bs->bits_pos; ++} ++ ++static int bs_write(bs_t* bs, int len, uint bit) { ++ if (bs->left_count > len) { ++ bs->left_count -= len; ++ bs->code_bits += bit << bs->left_count; ++ } else { ++ int left = (16 - len + bs->left_count); ++ uint pattern = (bs->code_bits << 16) + (bit << left); ++ bs->left_count = left; ++ bs->code_bits = pattern & 0xFFFF; ++ write_ebsp(bs, (uchar)(pattern>>24)); ++ write_ebsp(bs, (uchar)(pattern>>16)); ++ } ++ ++ bs->bits_pos += len; ++ ++ return len; ++} ++ ++static const uchar ue_code_lengths[256] = { ++ 1, 1, 3, 3, 5, 5, 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, ++ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, ++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, ++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++}; ++ ++static int bs_write_ue(bs_t* bs, int val) { ++ return bs_write(bs, (int)ue_code_lengths[val+1], (uint)val+1); ++} ++ ++static int bs_write_se(bs_t* bs, int val) { ++ int size = 0; ++ int tmp = 1 - 2*val; ++ if (tmp < 0) tmp = 2*val; ++ val = tmp; ++ if (tmp >= 256) { ++ size = 16; ++ tmp >>= 8; ++ } ++ size += ue_code_lengths[tmp]; ++ return bs_write(bs, size, (uint)val); ++} ++ ++static int bs_write_u1(bs_t* bs, int val) { ++ return bs_write(bs, 1, (uint)(val!=0)); ++} ++ ++static int bs_trail(bs_t* bs) { ++ int len; ++ ++ bs->left_count--; ++ bs->code_bits += 1 << bs->left_count; ++ ++ if (!bs->left_count) { ++ write_ebsp(bs, (uchar)(bs->code_bits>>8)); ++ write_ebsp(bs, (uchar)(bs->code_bits)); ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ } ++ ++ bs->bits_pos += 8; ++ bs->bits_pos &= ~0x7; ++ ++ len = 1 + (bs->left_count&0x7); ++ ++ bs->left_count &= ~7; ++ ++ return len; ++} ++ ++int avc_write_nal(bs_t* bs, uchar nal) { ++ *bs->curr++ = 0; ++ *bs->curr++ = 0; ++ *bs->curr++ = 0; ++ *bs->curr++ = 1; ++ *bs->curr++ = nal; ++ bs->bits_pos += 8*5; ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ ++ return 8*5; ++} ++ ++int avc_write_sps(bs_t* bs, sps_t* sps) { ++ int bit_pos = avc_count(bs); ++ bs_write(bs, 8, (uint)sps->i_profile_idc); ++ bs_write_u1(bs, sps->b_constraint_set0); ++ bs_write_u1(bs, sps->b_constraint_set1); ++ bs_write_u1(bs, sps->b_constraint_set2); ++ bs_write_u1(bs, sps->b_constraint_set3); ++ bs_write(bs, 4, 0); ++ ++ bs_write(bs, 8, (uint)sps->i_level_idc); ++ bs_write_ue(bs, sps->i_sps_id); ++ /* not support high profile ++ if (sps->i_profile_idc > PROFILE_HIGH) { ++ chroma_format_idc ++ .... ++ } ++ */ ++ bs_write_ue(bs, sps->i_log2_max_frame_num - 4); ++ bs_write_ue(bs, sps->i_poc_type); ++ if (sps->i_poc_type == 0) { ++ bs_write_ue(bs, sps->i_log2_max_poc_lsb - 4); ++ } ++ /* not support poc_type == 1 ++ else if (sps->i_poc_type == 1) { ++ .... ++ } ++ */ ++ bs_write_ue(bs, sps->i_num_ref_frames); ++ bs_write_u1(bs, sps->b_gaps_in_frame_num_value_allow); ++ bs_write_ue(bs, sps->i_mb_w - 1); ++ bs_write_ue(bs, sps->i_mb_h - 1); ++ bs_write_u1(bs, 1/*b_frame_mbs_only*/); ++ /* only support frame_mbs */ ++ bs_write_u1(bs, sps->b_direct8x8_inference); ++ bs_write_u1(bs, sps->b_crop); ++ if (sps->b_crop) { ++ bs_write_ue(bs, sps->crop.i_left); ++ bs_write_ue(bs, sps->crop.i_right); ++ bs_write_ue(bs, sps->crop.i_top); ++ bs_write_ue(bs, sps->crop.i_bottom); ++ } ++ bs_write_u1(bs, 0); /* skip vui params */ ++ bs_trail(bs); ++ ++ return bs->bits_pos - bit_pos; ++} ++ ++int avc_write_pps(bs_t* bs, pps_t* pps) { ++ int bit_pos = avc_count(bs); ++ bs_write_ue(bs, pps->i_pps_id); ++ bs_write_ue(bs, pps->sps->i_sps_id); ++ bs_write_u1(bs, pps->b_cabac); ++ bs_write_u1(bs, 0/*b_bottom_field_pic_order*/); ++ bs_write_ue(bs, 0/*i_num_slice_groups - 1*/); ++ bs_write_ue(bs, pps->i_num_ref_idx_l0_default_active - 1); ++ bs_write_ue(bs, pps->i_num_ref_idx_l1_default_active - 1); ++ /* not support weighted pred */ ++ bs_write_u1(bs, 0/*b_weighted_pred*/); ++ bs_write(bs, 2, 0/*b_weighted_bipred*/); ++ bs_write_se(bs, pps->i_pic_init_qp - 26); ++ bs_write_se(bs, pps->i_pic_init_qs - 26); ++ bs_write_se(bs, 0/*i_chroma_qp_index_offset*/); ++ bs_write_u1(bs, pps->b_deblocking_filter_control); ++ bs_write_u1(bs, pps->b_constrained_intra_pred); ++ bs_write_u1(bs, pps->b_redundant_pic_cnt); ++ /* not support transform8x8/q-matrix */ ++ bs_trail(bs); ++ ++ return bs->bits_pos - bit_pos; ++} ++ ++int avc_write_slice_header(bs_t* bs, slice_t* sh) { ++ bs_write_ue(bs, sh->i_first_mb); ++ bs_write_ue(bs, sh->i_type); ++ bs_write_ue(bs, sh->pps->i_pps_id); ++ bs_write(bs, sh->sps->i_log2_max_frame_num, (uint)sh->i_frame_num & ((1 << sh->sps->i_log2_max_frame_num) - 1)); ++ ++ if (sh->b_idr_pic) { ++ bs_write_ue(bs, sh->i_idr_pic_id); ++ } ++ if (sh->sps->i_poc_type == 0) { ++ bs_write(bs, sh->sps->i_log2_max_poc_lsb, (uint)sh->i_poc & ((1 << sh->sps->i_log2_max_poc_lsb) - 1)); ++ } ++ if (sh->pps->b_redundant_pic_cnt) { ++ bs_write_ue(bs, sh->i_redundant_pic_cnt); ++ } ++ if (sh->i_type == SLICE_B) { ++ bs_write_u1(bs, sh->b_direct_spatial_mv_pred); ++ } ++ if (sh->i_type == SLICE_P || sh->i_type == SLICE_B) { ++ bs_write_u1(bs, sh->b_num_ref_idx_override); ++ if (sh->b_num_ref_idx_override) { ++ bs_write_ue(bs, sh->i_num_ref_idx_l0_active - 1); ++ if (sh->i_type == SLICE_B) { ++ bs_write_ue(bs, sh->i_num_ref_idx_l1_active - 1); ++ } ++ } ++ } ++ /* not support ref_pic_list_reordering */ ++ if (sh->i_type != SLICE_I) { ++ bs_write_u1(bs, 0); ++ } ++ if (sh->i_type == SLICE_B) { ++ bs_write_u1(bs, 0); ++ } ++ /* not support weighted pred */ ++ /* not support dec_ref_pic_marking */ ++ if (sh->i_ref_idc) { ++ if (sh->b_idr_pic) { ++ bs_write_u1(bs, 0/*no_output_prior_pics_flag*/); ++ bs_write_u1(bs, 0/*long_term_reference_flag*/); ++ } else { ++ bs_write_u1(bs, 0/*adaptive_ref_pic_marking_mode_flag*/); ++ } ++ } ++ if (sh->pps->b_cabac && sh->i_type == SLICE_I) { ++ bs_write_ue(bs, sh->i_cabac_init_idc); ++ } ++ bs_write_se(bs, sh->i_qp - sh->pps->i_pic_init_qp); ++ if (sh->pps->b_deblocking_filter_control) { ++ bs_write_ue(bs, sh->i_disable_deblocking_filter_idc); ++ if (sh->i_disable_deblocking_filter_idc != 1) { ++ bs_write_se(bs, sh->i_alpha_c0_offset >> 1); ++ bs_write_se(bs, sh->i_beta_offset >> 1); ++ } ++ } ++ ++ return bs->bits_pos; ++} +diff --git a/drivers/mstar/mfe/src/mfe_hdlr.c b/drivers/mstar/mfe/src/mfe_hdlr.c +new file mode 100644 +index 00000000..fa2d7d38 +--- /dev/null ++++ b/drivers/mstar/mfe/src/mfe_hdlr.c +@@ -0,0 +1,512 @@ ++ ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BLOCK_TYPE_4x4 0 ++#define BLOCK_TYPE_4x8 0 ++#define BLOCK_TYPE_8x4 0 ++ ++#define _ALIGN_(b,x) (((x)+(1<<(b))-1)&(~((1<<(b))-1))) ++#define _BITS_(s) ((2<<(0?s))-(1<<(1?s))) ++#define _MAX_(a,b) ((a)>(b)?(a):(b)) ++#define _MIN_(a,b) ((a)<(b)?(a):(b)) ++ ++int ++mfe_hdlr_request( ++ void** pp) ++{ ++ mfe_hdlr* h; ++ int err = -ENOMEM; ++ ++ if (NULL != (h = kzalloc(sizeof(mfe_hdlr), GFP_KERNEL))) ++ { ++ sps_t* sps = &h->sps; ++ pps_t* pps = &h->pps; ++ slice_t* sh = &h->sh; ++ h->i_num_ref_frames = 1; ++ h->i_dmv_x = 16; ++ h->i_dmv_y = 16; ++ h->i_subpel = 2; ++ h->i_mv_block[0] = MV_BLOCK_SKIP|MV_BLOCK_16x16|MV_BLOCK_16x8|MV_BLOCK_8x16|MV_BLOCK_8x8; ++ h->i_mv_block[1] = 0; ++ sps->i_profile_idc = 66; ++ sps->i_level_idc = 30; ++ sps->b_constraint_set0 = 0; ++ sps->b_constraint_set1 = 1; ++ sps->b_constraint_set2 = 0; ++ sps->b_constraint_set3 = 0; ++ sps->i_log2_max_frame_num = 5; ++ sps->i_poc_type = 2; ++ sps->i_log2_max_poc_lsb = 4; // not used for poc_type=2 ++ sps->i_num_ref_frames = h->i_num_ref_frames; ++ sps->b_gaps_in_frame_num_value_allow = 0; ++ sps->b_direct8x8_inference = 1; ++ sps->b_crop = 0; ++ /* gen pps */ ++ pps->i_pps_id = 0; ++ pps->b_cabac = 0; ++ pps->i_num_ref_idx_l0_default_active = sps->i_num_ref_frames; ++ pps->i_num_ref_idx_l1_default_active = sps->i_num_ref_frames; ++ pps->i_pic_init_qp = 26; ++ pps->i_pic_init_qs = 26; ++ pps->b_redundant_pic_cnt = 0; ++ pps->b_deblocking_filter_control = 0; ++ pps->b_constrained_intra_pred = 0; ++ /* gen slice-header */ ++ sh->i_disable_deblocking_filter_idc = 0; ++ sh->i_alpha_c0_offset = 0; ++ sh->i_beta_offset = 0; ++ ++ mutex_init(&h->stream_lock); ++ mutex_init(&h->encode_lock); ++ h->b_stream = 0; ++ h->i_encode = 0; ++ err = 0; ++ } ++ *pp = h; ++ return err; ++} ++ ++int ++mfe_hdlr_release( ++ void* p) ++{ ++ if (p) ++ { ++ kfree(p); ++ } ++ return 0; ++} ++ ++int ++mfe_hdlr_seq_exit( ++ mfe_hdlr* h) ++{ ++ cvbr_rc* rc = &h->cvbr; ++ ++ cvbr_CloseRateControl(rc); ++ ++ kfree(h->regs); ++ h->regs = NULL; ++ return 0; ++} ++ ++#define HD_MB_SIZE ((1280*720)/256) ++ ++int ++mfe_hdlr_seq_init( ++ mfe_hdlr* h) ++{ ++ mfe_regs* regs = NULL; ++ cvbr_rc* rc = &h->cvbr; ++ sps_t* sps = &h->sps; ++ pps_t* pps = &h->pps; ++ slice_t* sh = &h->sh; ++ ++ if (!(regs = kzalloc(sizeof(mfe_regs), GFP_KERNEL))) ++ { ++ return -ENOMEM; ++ } ++ pps->sps = sps; ++ sh->sps = sps; ++ sh->pps = pps; ++ /* gen sps */ ++ sps->i_num_ref_frames = h->i_num_ref_frames; ++ sps->i_mb_w = h->i_mb_w; ++ sps->i_mb_h = h->i_mb_h; ++ sps->b_crop = 0; ++ if (sps->i_mb_h > 36) ++ { ++ sps->i_level_idc = 31; ++ } ++ /* gen pps */ ++ pps->i_pps_id = 0; ++ pps->i_num_ref_idx_l0_default_active = sps->i_num_ref_frames; ++ pps->i_num_ref_idx_l1_default_active = sps->i_num_ref_frames; ++ pps->i_pic_init_qp = 26; ++ pps->i_pic_init_qs = 26; ++ pps->b_redundant_pic_cnt = 0; ++ ++ regs->reg20_s_me_16x16_disable = !(h->i_mv_block[0]&MV_BLOCK_16x16); ++ regs->reg20_s_me_16x8_disable = !(h->i_mv_block[0]&MV_BLOCK_16x8); ++ regs->reg20_s_me_8x16_disable = !(h->i_mv_block[0]&MV_BLOCK_8x16); ++ regs->reg20_s_me_8x8_disable = !(h->i_mv_block[0]&MV_BLOCK_8x8); ++ regs->reg20_s_me_8x4_disable = !(h->i_mv_block[0]&MV_BLOCK_8x4); ++ regs->reg20_s_me_4x8_disable = !(h->i_mv_block[0]&MV_BLOCK_4x8); ++ regs->reg20_s_me_4x4_disable = !(h->i_mv_block[0]&MV_BLOCK_4x4); ++ regs->reg20_s_mesr_adapt = 1; ++ regs->reg21_s_ime_sr16 = (h->i_dmv_x<=16); ++ regs->reg21_s_ime_umv_disable = 0; ++ regs->reg22_s_ime_mesr_max_addr = (h->i_dmv_y==16 ? 95 : 85); ++ regs->reg22_s_ime_mesr_min_addr = (h->i_dmv_y==16 ? 0 : 10); ++ regs->reg23_s_ime_mvx_min = _MAX_(-h->i_dmv_x+32,-16+32); ++ regs->reg23_s_ime_mvx_max = _MIN_( h->i_dmv_x+32, 16+31); ++ regs->reg24_s_ime_mvy_min = _MAX_(-h->i_dmv_y+16,-16+16); ++ regs->reg24_s_ime_mvy_max = _MIN_( h->i_dmv_y+16, 16+15); ++ regs->reg25_s_fme_quarter_disable = (h->i_subpel!=2); ++ regs->reg25_s_fme_half_disable = (h->i_subpel==0); ++ regs->reg25_s_fme_pmv_enable = 0!=(h->i_mv_block[0]&MV_BLOCK_SKIP); ++ regs->reg25_s_fme_mode_no = (h->i_mb_wxh <= 396); ++ regs->reg2b_s_ieap_constraint_intra = pps->b_constrained_intra_pred; ++ regs->reg2b_s_ieap_last_mode = 8; ++ regs->reg2b_s_ieap_ccest_en = 1; ++ regs->reg2b_s_ieap_ccest_thr = 3; ++ regs->reg2b_s_ieap_drop_i16 = 0; ++ ++ h->regs = regs; ++ /* rate control */ ++ rc->fr_fps.num = h->fr_fps.num; ++ rc->fr_fps.den = h->fr_fps.den; ++ rc->i_fps = rc->fr_fps.num / rc->fr_fps.den; ++ rc->i_codec_type = h->i_codec_type; ++ rc->i_pict_w = h->i_picture_w; ++ rc->i_pict_h = h->i_picture_h; ++ rc->i_bps = h->i_bps; ++ rc->b_fps_fixed = 1; ++ rc->i_num_ppic = h->i_num_ppic; ++ rc->i_num_bpic = h->i_num_bpic; ++ rc->i_method = CBR; ++ rc->b_mb_layer = 1; ++ rc->i_bps_max = 0; ++#if 0 // Test const qp ++ rc->i_method = CONST_QP; ++ rc->b_mb_layer = 0; ++ rc->i_qp = 12; ++#endif ++ cvbr_InitRateControl(rc); ++ /*!rate control */ ++ ++ return 0; ++} ++ ++void ++mfe_hdlr_pic_mode( ++ mfe_hdlr* h) ++{ ++ slice_t* sh = &h->sh; ++ ++ if (0 == (h->i_cnt_bpic%(1+h->i_num_bpic))) ++ { ++ if (0 == (h->i_cnt_ppic%(1+h->i_num_ppic))) ++ { ++ sh->i_type = SLICE_I; ++ sh->b_idr_pic = 1; ++ sh->i_ref_idc = NAL_PRIO_HIGHEST; ++ h->i_cnt_ppic = 0; ++ } ++ else ++ { ++ sh->i_type = SLICE_P; ++ sh->b_idr_pic = 0; ++ sh->i_ref_idc = NAL_PRIO_HIGH; ++ } ++ ++h->i_cnt_ppic; ++ h->i_cnt_bpic = 0; ++ } ++ else ++ { ++ sh->i_type = SLICE_B; ++ sh->b_idr_pic = 0; ++ sh->i_ref_idc = NAL_PRIO_DISPOSED; ++ } ++ ++h->i_cnt_bpic; ++} ++ ++void ++mfe_hdlr_pic_init( ++ mfe_hdlr* h) ++{ ++ sps_t *sps = &h->sps; ++ pps_t *pps = &h->pps; ++ slice_t* sh = &h->sh; ++ bs_t outbs, *bs = &outbs; ++ uchar nal; ++ int i; ++ ++ if (sh->b_idr_pic) ++ { ++ for (i = 0; i < h->i_num_ref_frames; i++) ++ { ++ if (h->dpb[i]) ++ { ++ h->dpb[i]->b_busy = 0; ++ h->dpb[i] = NULL; ++ } ++ } ++ } ++ if (sh->i_ref_idc) ++ { ++ for (i = 0; i <= h->i_num_ref_frames; i++) ++ { ++ if (!h->frames[i].b_busy) ++ { ++ h->recon = &h->frames[i]; ++ h->recon->b_busy = 1; ++ break; ++ } ++ } ++ } ++ /* set slice header */ ++ nal = (sh->i_ref_idc<<5) | NAL_SLICE; ++ if (sh->b_idr_pic) ++ { ++ sh->i_idr_pic_id = (sh->i_idr_pic_id+1)%2; ++ sh->i_frame_num = 0; ++ sh->i_num_ref_idx_l0_active = 0; ++ nal = (NAL_PRIO_HIGHEST<<5) | NAL_IDR; ++ } ++ else if (sh->i_ref_idc) ++ { ++ sh->i_frame_num = (sh->i_frame_num+1)%(1<i_log2_max_frame_num); ++ ++ if (++sh->i_num_ref_idx_l0_active > sps->i_num_ref_frames) ++ { ++ sh->i_num_ref_idx_l0_active = sps->i_num_ref_frames; ++ } ++ } ++ sh->i_qp = cvbr_InitFrame(&h->cvbr, sh->i_type==SLICE_I?I_VOP:P_VOP, 0); ++ ++ avc_reset(bs, h->code_sh, 64); ++ /* first frame contains sps/pps */ ++ if (!h->i_seq_numb) ++ { ++ avc_write_nal(bs, (NAL_PRIO_HIGHEST<<5)|NAL_SPS); ++ avc_write_sps(bs, sps); ++ avc_flush(bs); ++ avc_write_nal(bs, (NAL_PRIO_HIGHEST<<5)|NAL_PPS); ++ avc_write_pps(bs, pps); ++ avc_flush(bs); ++ } ++ avc_write_nal(bs, nal); ++ avc_write_slice_header(bs, sh); ++ avc_flush(bs); ++ ++ h->bits_sh = avc_count(bs); ++} ++ ++void ++mfe_hdlr_pic_read_bits( ++ mfe_hdlr* h) ++{ ++ void* src = h->p_vptr_bs; ++ void* dst = h->p_outbuf; ++ int size; ++ ++ size = h->i_last_bits>>3; ++ ++ memcpy(dst, src, size); ++ ++ h->i_uselen = size; ++ h->i_remlen = size; ++ h->i_stat_size += size; ++} ++ ++void ++mfe_hdlr_pic_done( ++ mfe_hdlr* h) ++{ ++ slice_t* sh = &h->sh; ++ cvbr_rc* rc = &h->cvbr; ++ mfe_regs* regs = h->regs; ++ ++ h->i_pic_avgqp = ((int)regs->reg29_s_mbr_last_frm_avg_qp_hi<<16) + regs->reg28_s_mbr_last_frm_avg_qp_lo; ++ h->i_last_bits = ((int)regs->reg43_s_bsp_bit_cnt_hi<<16) + regs->reg42_s_bsp_bit_cnt_lo; ++ /* rate control */ ++ rc->m_nLastFrameAvgQStep[0] = h->i_pic_avgqp; ++ rc->m_nLastFrameAvgQStep[1] = 0; ++ cvbr_UpdateFrame(rc, h->i_last_bits, 0, 0); ++ /*!rate control */ ++ if (sh->i_ref_idc) ++ { ++ int i; ++ frame_t* dpb = h->recon; ++ h->recon = NULL; ++ for (i = 0; i < h->i_num_ref_frames; i++) ++ { ++ frame_t* out = h->dpb[i]; ++ h->dpb[i] = dpb; ++ dpb = out; ++ } ++ if (dpb) ++ { ++ dpb->b_busy = 0; ++ } ++ } ++ ++h->i_seq_numb; ++} ++ ++void ++mfe_hdlr_pic_prep_regs( ++ mfe_hdlr* h) ++{ ++ cvbr_rc* rc = &h->cvbr; ++ mfe_regs* regs = h->regs; ++ sps_t* sps = &h->sps; ++ pps_t* pps = &h->pps; ++ slice_t* sh = &h->sh; ++ ++ regs->reg68_s_marb_eimi_block = 0; ++ ++ regs->reg00_g_enc_mode = REG_ENC_MODE_H264; ++ regs->reg01_g_pic_width = h->i_picture_w; ++ regs->reg02_g_pic_height = h->i_picture_h; ++ // qtable ++ regs->reg03_g_qmode = 0; ++ // frame coding only ++ regs->reg03_g_fldpic_en = 0; ++ // mdc ++ regs->reg29_s_mbr_qp_cidx_offset = 0; ++ // pre-fetch ++ regs->reg68_s_prfh_cryc_en = 1; ++ regs->reg68_s_prfh_refy_en = 1; ++ regs->reg6d_s_prfh_cryc_idle_cnt = 0; ++ regs->reg6d_s_prfh_refy_idle_cnt = 0; ++ // NOT SW Buffer Mode ++ regs->reg73_g_sw_buffer_mode = 0; ++ regs->reg18_g_jpe_buffer_mode = 1; // frame-mode ++ regs->reg18_g_jpe_fsvs_mode = 0; ++ regs->reg18_g_viu_soft_rstz = 1; ++ // read default value when seq_num==0 ++ // regs->reg81 = REGR(MFEBASE,0x81,"value"); ++ // regs->reg68 = REGR(MFEBASE,0x68,"value"); ++ ++ // clock gating ++ regs->reg16 = 0xFFFF; ++ // per-frame: ref_frames/frame_type ++ regs->reg00_g_frame_type = sh->i_type==SLICE_I?0:sh->i_type==SLICE_P?1:2; ++ regs->reg00_g_ref_no = sh->i_num_ref_idx_l0_active==2?1:0; ++ // per-frame: slice parameters ++ regs->reg39_s_mdc_h264_nal_ref_idc = sh->i_ref_idc; ++ regs->reg39_s_mdc_h264_nal_unit_type = sh->b_idr_pic; ++ regs->reg39_s_mdc_h264_fnum_bits = sps->i_log2_max_frame_num-5; ++ regs->reg39_s_mdc_h264_dbf_control = pps->b_deblocking_filter_control; ++ regs->reg39_s_mdc_h264_fnum_value = sh->i_frame_num; ++ regs->reg3a_s_mdc_h264_idr_pic_id = sh->i_idr_pic_id; ++ regs->reg3a_s_mdc_h264_disable_dbf_idc = sh->i_disable_deblocking_filter_idc; ++ regs->reg3a_s_mdc_h264_alpha = sh->i_alpha_c0_offset; ++ regs->reg3a_s_mdc_h264_beta = sh->i_beta_offset; ++ regs->reg3a_s_mdc_h264_ridx_aor_flag = (sh->i_num_ref_idx_l0_active!=sh->pps->i_num_ref_idx_l0_default_active); ++ // per-frame: buffer setting: current/reference/reconstructing ++ regs->reg06_g_cur_y_addr_lo = (ushort)(h->input.base_y>> 8); ++ regs->reg07_g_cur_y_addr_hi = (ushort)(h->input.base_y>>24); ++ regs->reg08_g_cur_c_addr_lo = (ushort)(h->input.base_c>> 8); ++ regs->reg09_g_cur_c_addr_hi = (ushort)(h->input.base_c>>24); ++ if (sh->i_num_ref_idx_l0_active) ++ { ++ regs->reg0a_g_ref_y_addr0_lo = (ushort)(h->dpb[0]->base_y>> 8); ++ regs->reg0b_g_ref_y_addr0_hi = (ushort)(h->dpb[0]->base_y>>24); ++ regs->reg0e_g_ref_c_addr0_lo = (ushort)(h->dpb[0]->base_c>> 8); ++ regs->reg0f_g_ref_c_addr0_hi = (ushort)(h->dpb[0]->base_c>>24); ++ } ++ regs->reg12_g_rec_y_addr_lo = (ushort)(h->recon->base_y>> 8); ++ regs->reg13_g_rec_y_addr_hi = (ushort)(h->recon->base_y>>24); ++ regs->reg14_g_rec_c_addr_lo = (ushort)(h->recon->base_c>> 8); ++ regs->reg15_g_rec_c_addr_hi = (ushort)(h->recon->base_c>>24); ++ // Output buffers: Must be 8-byte aligned. ++ regs->reg3f_s_bspobuf_hw_en = 0; ++ // GN ++ regs->reg4c_s_gn_saddr_lo = (ushort)(h->i_base_gn>> 3); ++ regs->reg4d_s_gn_saddr_hi = (ushort)(h->i_base_gn>>19); ++ regs->reg4d_s_gn_saddr_mode = 0; ++ // IMI buffer ++ regs->reg68_s_marb_lbwd_mode = 0; ++ regs->reg6b_s_marb_imi_saddr_lo = 0; ++ regs->reg6c_s_marb_imi_saddr_hi = 0; ++ // Motion search ++ regs->reg20_s_me_ref_en_mode = (1<i_num_ref_idx_l0_active)-1; ++ // FME ++ regs->reg21_s_ime_ime_wait_fme = 1; ++ regs->reg25_s_fme_pipeline_on = regs->reg21_s_ime_ime_wait_fme ? 1 : 0; ++ // P8x8 BOUND RECT ++ regs->reg21_s_ime_boundrect_en = (sps->i_profile_idc==66 && sps->i_level_idc<=30); ++ regs->reg21_s_ime_h264_p8x8_ctrl_en = 0;//mfeinfo->i_p8x8_max_count < h->i_mb_wxh ? 1 : 0; ++ ++ regs->reg25_s_fme_mode0_refno = 1; ++ regs->reg25_s_fme_mode1_refno = 1; ++ regs->reg25_s_fme_mode2_refno = 1; ++ // Intra update (force disabled) ++ regs->reg2f_s_txip_irfsh_en = 0; ++ ++ regs->reg2c_s_quan_idx_last = 63; ++ if (regs->reg2c_s_quan_idx_last < 63) { ++ regs->reg2c_s_quan_idx_swlast = 1; ++ } ++ else { ++ regs->reg2c_s_quan_idx_swlast = 0; ++ } ++ ++ /* bitrate controller */ ++ // MBR ++ regs->reg00_g_mbr_en = rc->b_mb_layer ? 1 : 0; ++ regs->reg26_s_mbr_pqp_dlimit = LEFT_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = TOP_QP_DIFF_LIMIT; ++ // er_en ++ if (rc->m_nVPMbRow > 0 && rc->m_nVPSize <= 0) { ++ regs->reg03_g_er_mode = 0; ++ } ++ else if (rc->m_nVPMbRow <= 0 && rc->m_nVPSize > 0) { ++ regs->reg03_g_er_mode = 1; ++ } ++ else if (rc->m_nVPMbRow > 0 && rc->m_nVPSize > 0) { ++ regs->reg03_g_er_mode = 2; ++ } ++ else { ++ regs->reg03_g_er_mode = 3; ++ } ++ ++ if (rc->m_nVPMbRow == 0 || rc->m_nVPMbRow == 1) { ++ regs->reg03_g_er_mby = 0; ++ } ++ else if (rc->m_nVPMbRow == 2) { ++ regs->reg03_g_er_mby = 1; ++ } ++ else if (rc->m_nVPMbRow == 4) { ++ regs->reg03_g_er_mby = 2; ++ } ++ else if (rc->m_nVPMbRow == 8) { ++ regs->reg03_g_er_mby = 3; ++ } ++ else if (rc->m_nVPMbRow > 0) { ++ MST_ASSERT(0); ++ } ++ ++ if (regs->reg03_g_er_mode==1 || regs->reg03_g_er_mode==2) { ++ regs->reg04_g_er_bs_th = rc->m_nVPSize; ++ } ++ ++ regs->reg00_g_qscale = sh->i_qp; ++ regs->reg27_s_mbr_frame_qstep = rc->m_nFrameQStep; ++ regs->reg26_s_mbr_tmb_bits = rc->m_nTargetMbBits; ++ ++ MST_ASSERT(rc->m_nMinQStep<(2<<7)); ++ // QP/QStep: Min, max ++ regs->reg2a_s_mbr_qp_min = rc->m_nMinQP; ++ regs->reg2a_s_mbr_qp_max = rc->m_nMaxQP; ++ regs->reg6e_s_mbr_qstep_min = rc->m_nMinQStep; ++ regs->reg6f_s_mbr_qstep_max = rc->m_nMaxQStep; ++ /*!bitrate controller */ ++ regs->reg00_g_rec_en = 1; ++ ++ // Frame Coding Only ++ regs->reg2a_s_mvdctl_ref0_offset = 0; ++ regs->reg2a_s_mvdctl_ref1_offset = 0; ++ regs->reg7d_eco_bsp_rdy_fix = 1; ++ ++ regs->coded_data = h->code_sh; ++ regs->coded_bits = h->bits_sh; ++ regs->outbs_addr = h->i_base_bs; ++ regs->outbs_size = h->i_size_bs; ++} ++ +diff --git a/drivers/mstar/mfe/src/mfe_rc.c b/drivers/mstar/mfe/src/mfe_rc.c +new file mode 100644 +index 00000000..07d03428 +--- /dev/null ++++ b/drivers/mstar/mfe/src/mfe_rc.c +@@ -0,0 +1,864 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++////////////////////////////////////////////////////////////////////////// ++// MStar simple rate control ++////////////////////////////////////////////////////////////////////////// ++ ++#include ++ ++#include ++ ++#include ++ ++#define MFE_ASSERT(p) ++ ++#define MFE_DIV_S64 div_s64 ++ ++// H264 ++ // Spec limitation is [1, 51] ++ #define MSRC_MAX_QP_H264 48 ++ #define MSRC_MIN_QP_H264 5 ++ #define FRAMESKIP_THR_QP_H264 40 ++// MPEG-4, H263 ++ // Spec limitation is [1, 31] ++ #define MSRC_MAX_QP_MPEG4 28 ++ #define MSRC_MIN_QP_MPEG4 1 ++ #define FRAMESKIP_THR_QP_MPEG4 20 ++ ++//! How many seconds of frames are responsible for compensation of bitrate usage. ++#define CBR_DEPUTY_SECOND 1 ++#define CVBR_DEPUTY_SECOND 3 ++#define VBR_DEPUTY_SECOND 10 ++ ++#define MIN_DEPUTY_FACTOR 10 ++ ++//! Default I-frame weighting over inter-frame ++// #define IFRAME_WEIGHT 2 ++// #define PFRAME_WEIGHT 1 ++#define IFRAME_WEIGHT 8 ++#define PFRAME_WEIGHT 4 ++#define BFRAME_WEIGHT 3 ++ ++ ++ ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ #define MBACT_NORMALIZATION_FACTOR 2 ++ //#define FLAT_AREA_VAR_THR 5 ++ #define SPEC_QP_DIFF_LIMIT 2 // Spec limitation ++ #define USE_INT_PREC ++ // Below are used when USE_INT_PREC ++ #define SCALE_BITS 6 ++ #define SCALE_ACT 6 ++#endif ++ ++////////////////////////////////////////////////////////////////////////// ++// global variables ++////////////////////////////////////////////////////////////////////////// ++ ++//private: ++int cvbr_ComputeFrameQStep(cvbr_rc* ct, int nFrameType); // Return the target 'QStep' ++int cvbr_ComputeMbQP(cvbr_rc* ct, int mb_idx); // Return the target 'QP' ++ ++int rcQP2Qstep(cvbr_rc* ct, int QP); ++int rcQstep2QP(cvbr_rc* ct, int QstepX32); ++ ++/* ++void output_MBR_reg(void* hd, cvbr_rc* ct) ++{ ++ if (ct->m_nVPMbRow>0 && ct->m_nVPSize<=0) ++ sd_output(hd, 0, 2, "reg_mfe_g_er_mode"); ++ else if (ct->m_nVPMbRow<=0 && ct->m_nVPSize>0) ++ sd_output(hd, 1, 2, "reg_mfe_g_er_mode"); ++ else if (ct->m_nVPMbRow>0 && ct->m_nVPSize>0) ++ sd_output(hd, 2, 2, "reg_mfe_g_er_mode"); ++ else ++ sd_output(hd, 3, 2, "reg_mfe_g_er_mode"); ++ if (ct->m_nVPMbRow==1) ++ sd_output(hd, 0, 2, "reg_mfe_g_er_mby"); ++ else if (ct->m_nVPMbRow==2) ++ sd_output(hd, 1, 2, "reg_mfe_g_er_mby"); ++ else if (ct->m_nVPMbRow==4) ++ sd_output(hd, 2, 2, "reg_mfe_g_er_mby"); ++ else if (ct->m_nVPMbRow==8) ++ sd_output(hd, 3, 2, "reg_mfe_g_er_mby"); ++ else ++ sd_output(hd, 0, 2, "reg_mfe_g_er_mby"); ++} ++*/ ++ ++/* ++fps=14.985 = 15000/1001 ++fps=23.976 = 24000/1001 ++fps=29.970 = 30000/1001 ++*/ ++void cvbr_InitRateControl(cvbr_rc* ct) ++{ ++ int i, j; ++ ++ ct->m_nFrameCount = 0; ++ MFE_ASSERT(ct->CVBRRCInfo_nWidth<=MAX_MB_WIDTH*16); ++ ++ // More bitrate checking ++ if (ct->i_method == CONSTRAINED_VBR) { ++ if (ct->i_bps == 0) ++ ct->i_bps = (int)((ct->i_bps_max * 6) / 10); ++ if (ct->i_bps_max == 0) ++ ct->i_bps_max = (int)((ct->i_bps * 14) / 10); ++ ++ ct->m_nMaxOffset = (int)MFE_DIV_S64((MFE_S64)(ct->i_bps_max-ct->i_bps)*ct->fr_fps.den,ct->fr_fps.num) ; ++ ++ if (ct->b_mb_layer == 0) ++ ct->m_nMaxOffset = (ct->m_nMaxOffset) >> 2; ++ } ++ else { ++ ct->i_bps_max = 0; // Don't care ++ } ++ ++ // Derived ++ ct->m_nAvgBitsPerFrame = (int)MFE_DIV_S64((MFE_S64)ct->i_bps*ct->fr_fps.den, ct->fr_fps.num) ; ++ ++ i = 1 + ct->i_num_ppic * (1 + ct->i_num_bpic); ++ j = IFRAME_WEIGHT + PFRAME_WEIGHT*ct->i_num_ppic + BFRAME_WEIGHT*(ct->i_num_ppic*ct->i_num_bpic); ++ ct->m_nBitsPerFrame[0] = (int)MFE_DIV_S64((MFE_S64)ct->i_bps*ct->fr_fps.den*IFRAME_WEIGHT*i,j*ct->fr_fps.num); ++ ct->m_nBitsPerFrame[1] = (int)MFE_DIV_S64((MFE_S64)ct->i_bps*ct->fr_fps.den*PFRAME_WEIGHT*i,j*ct->fr_fps.num); ++ ct->m_nBitsPerFrame[2] = (int)MFE_DIV_S64((MFE_S64)ct->i_bps*ct->fr_fps.den*BFRAME_WEIGHT*i,j*ct->fr_fps.num); ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ ct->m_nMbWidth = (ct->i_pict_w + 15)>>4; ++#endif ++ // QP, QStep: min, max ++ ct->m_nMinQP = MSRC_MIN_QP_H264; ++ ct->m_nMaxQP = MSRC_MAX_QP_H264; ++ ct->m_nMinQStep = rcQP2Qstep(ct, MSRC_MIN_QP_H264)-1; ++ ct->m_nMaxQStep = rcQP2Qstep(ct, MSRC_MAX_QP_H264); ++ ct->m_nFrameSkipThrQP = FRAMESKIP_THR_QP_H264; ++ MFE_ASSERT(ct->m_nCodecType==REG_ENC_MODE_H264); ++ // Bitrate usage monitoring ++ ct->m_nMinDeputyCount = (ct->fr_fps.num*CBR_DEPUTY_SECOND)/ct->fr_fps.den; ++ ct->m_nTargetFullness = ct->i_bps >> 1; ++ ct->m_nBufFullness = ct->m_nTargetFullness; ++ switch (ct->i_method) { ++ case VBR: ++ ct->m_nDeputyCount = (ct->fr_fps.num*VBR_DEPUTY_SECOND)/ct->fr_fps.den; ++ break; ++ case CONSTRAINED_VBR: ++ ct->m_nDeputyCount = (ct->fr_fps.num*CVBR_DEPUTY_SECOND)/ct->fr_fps.den; ++ ct->m_BitrateGauge[0] = ct->m_nBitsPerFrame[0]; ++ for (i = 1; i < MAX_GAUGE_SIZE; i++) { ++ ct->m_BitrateGauge[i] = ct->m_nBitsPerFrame[1]; ++ for (j = 0; j < ct->i_num_bpic; j++, i++) { ++ if (i == MAX_GAUGE_SIZE) break; ++ ct->m_BitrateGauge[i] = ct->m_nBitsPerFrame[2]; ++ } ++ } ++ ct->m_nGaugeCount = ct->i_fps; ++ ct->m_nGaugeIndex = 0; ++ ct->m_nGaugeBitrate = (int)MFE_DIV_S64((MFE_S64)ct->i_bps*ct->fr_fps.den*ct->m_nGaugeCount,ct->fr_fps.num); ++ break; ++ case CBR: ++ default: ++ ct->m_nDeputyCount = (int)MFE_DIV_S64((MFE_S64)ct->fr_fps.num*CBR_DEPUTY_SECOND,ct->fr_fps.den) ; ++ break; ++ } ++ ++ ct->m_nFrameCount = 0; ++ ct->m_nTotalBits = 0; ++ ct->m_nLastFrameAvgQStep[0] = ct->m_nLastFrameAvgQStep[1] = ct->m_nLastFrameBits = 0; ++ ct->m_nLongTermQP64 = 0; ++ ++ ct->m_nTotalMB = (ct->i_pict_w>>4)*(ct->i_pict_h>>4); ++} ++ ++ ++void cvbr_CloseRateControl(cvbr_rc* ct) ++{ ++} ++ ++// FieldType: 0--Progressive, 1--First field, 2--second field. ++int cvbr_InitFrame(cvbr_rc* ct, int nFrameType, char FieldType) ++{ ++ int nDeputyCount = 0; ++ int delta = 0, nRtnQP; ++ ++ if (FieldType==0||FieldType==1) ++ ct->m_bIsBotField = 0; ++ else ++ ct->m_bIsBotField = 1; // FieldType is 2 ++ ++ ct->m_nFrameType = nFrameType; ++ ct->m_nLastVPBits = 0; ++ ct->m_nNewPacket = 0; ++ ++ // Target frame bitcount ++ if (FieldType!=2) ++ { ++ if (ct->m_nFrameCount>0) { ++ // 1. Determine the number of future frame to compensate for current bitrate mismatch. ++ if (ct->m_nFrameCount>ct->m_nDeputyCount*MIN_DEPUTY_FACTOR) ++ nDeputyCount = ct->m_nDeputyCount; ++ else if (ct->m_nFrameCountm_nMinDeputyCount) ++ nDeputyCount = ct->m_nMinDeputyCount; ++ else ++ nDeputyCount = ct->m_nMinDeputyCount + ++ (ct->m_nFrameCount-ct->m_nMinDeputyCount)*(ct->m_nDeputyCount-ct->m_nMinDeputyCount)/(ct->m_nDeputyCount*MIN_DEPUTY_FACTOR-ct->m_nMinDeputyCount); ++ // 2. Calculate the bitcount that this frame should be compensate for. ++ if (ct->i_method == CBR) { ++ delta = (int)MFE_DIV_S64((MFE_S64)(ct->m_nBufFullness-ct->m_nTargetFullness)*ct->fr_fps.den,ct->fr_fps.num); ++ } ++ else if (ct->i_method == CONSTRAINED_VBR) { ++ delta = (ct->m_nBufFullness-ct->m_nTargetFullness) / nDeputyCount; ++ if (delta<-ct->m_nMaxOffset) ++ delta = -ct->m_nMaxOffset; ++ } ++ else if (ct->i_method == VBR) { ++ delta = (ct->m_nBufFullness-ct->m_nTargetFullness) / nDeputyCount; ++ if (delta>0 && ((ct->m_nLastFrameAvgQStep[0]<<6)>ct->m_nLongTermQP64)) ++ delta = delta>>1; // Make it more variable bitrate to allow better quality ++ } ++ // 3. Finally, calculate the target bitcount. ++ if (ct->i_num_ppic==0) { ++ ct->m_nTargetBits = ct->m_nBitsPerFrame[0] - delta; ++ } ++ else { ++ switch (nFrameType) { ++ case I_VOP: ++ ct->m_nTargetBits = ct->m_nBitsPerFrame[0] - delta; ++ break; ++ case P_VOP: ++ ct->m_nTargetBits = ct->m_nBitsPerFrame[1] - delta; ++ break; ++ case B_VOP: ++ ct->m_nTargetBits = ct->m_nBitsPerFrame[2] - delta; ++ break; ++ } ++ } ++ if (ct->m_nTargetBits<=(ct->m_nAvgBitsPerFrame>>3)) ++ ct->m_nTargetBits = (ct->m_nAvgBitsPerFrame>>3); // Target bitcount must>0 for ComputeFrameQP() ++ } ++ else { ++ ct->m_nTargetBits = ct->m_nBitsPerFrame[0]; // Must be I-frame ++ } ++ ++ /* Return initial frame QP */ ++ ++ ct->m_nFrameQStep = cvbr_ComputeFrameQStep(ct, nFrameType); ++ ++ ct->m_nLastFrameAvgQStep[0] = ct->m_nLastFrameAvgQStep[1] = 0; ++ ct->m_nLastFrameBits = 0; ++ ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ ct->m_nTargetMbBits = ct->m_nTargetBits / ct->m_nTotalMB; ++#endif ++ } ++ else { // bottom field ++ int nTargetBits; ++ ct->m_nFrameQStep = ct->m_nLastFrameAvgQStep[0] / ((ct->m_nTotalMB>>1)-1); ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ nTargetBits = ct->m_nTargetBits - ct->m_nLastFrameBits; ++ if (nTargetBitsm_nTargetBits>>3) ++ nTargetBits = ct->m_nTargetBits>>3; ++ ct->m_nTargetMbBits = nTargetBits / (ct->m_nTotalMB>>1); ++#endif ++ } ++ ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ ct->m_nMBN = 0; ++ if (ct->m_nTargetMbBits<1) ++ ct->m_nTargetMbBits = 1; ++#endif ++ ++ nRtnQP = rcQstep2QP(ct, ct->m_nFrameQStep); ++ //ct->m_nFrameQStep = rcQP2Qstep(ct, nRtnQP); ++ ++// ms_dprintk(DRV_L3,"[CVBRRC] %5d%s[%s] InitFrame: TargetBits %7d InitQP %2d Buffer %7d Deputy=%d\n", ++// ct->m_nFrameCount, FieldType==0?"F":(FieldType==1?"T":"B"), nFrameType==I_VOP?"I":(nFrameType==P_VOP?"P":"B"), ++// (int)(ct->m_nTargetBits), nRtnQP, ct->m_nBufFullness, nDeputyCount); ++ ++ return nRtnQP; ++} ++ ++int cvbr_UpdateFrame(cvbr_rc* ct, int totalUsedBits, char bDummyFrame, char FieldType) ++{ ++ int frameskip = 0; ++ ++ // Update counter ++ ct->m_nTotalBits += totalUsedBits; ++ ct->m_nLastFrameBits += totalUsedBits; ++ ct->m_nBufFullness += totalUsedBits; ++ if (FieldType!=1) { ++ ct->m_nFrameCount++; ++ ct->m_nLastTargetBits = ct->m_nTargetBits; ++ ++ if (!bDummyFrame) { ++ ct->m_nLastFrameAvgQStep[0] = (ct->m_nLastFrameAvgQStep[0]+ct->m_nLastFrameAvgQStep[1]) / (FieldType==0 ? ct->m_nTotalMB-1 : ct->m_nTotalMB-2); ++ // Variable bitrate ++ if (ct->i_method == VBR) ++ ct->m_nLongTermQP64 += ((ct->m_nLastFrameAvgQStep[0]<<6)-ct->m_nLongTermQP64) / ct->m_nFrameCount; ++ else if (ct->i_method == CONSTRAINED_VBR) { ++ if (ct->m_nFrameCount == 1) ++ ct->m_nLongTermQP64 = ct->m_nLastFrameAvgQStep[0]<<6; ++ else ++ ct->m_nLongTermQP64 = (ct->m_nLongTermQP64*(ct->m_nDeputyCount-1) + (ct->m_nLastFrameAvgQStep[0]<<6)) / ct->m_nDeputyCount; ++ } ++ } ++ else { ++ ct->m_nLastFrameAvgQStep[0] = ct->m_nFrameQStep; ++ } ++ ++ if (ct->i_method == CONSTRAINED_VBR) { ++ ct->m_nGaugeBitrate -= ct->m_BitrateGauge[ct->m_nGaugeIndex]; ++ ct->m_nGaugeBitrate += totalUsedBits; ++ ct->m_BitrateGauge[ct->m_nGaugeIndex] = totalUsedBits; ++ ct->m_nGaugeIndex++; ++ if (ct->m_nGaugeIndex==ct->m_nGaugeCount) ++ ct->m_nGaugeIndex = 0; ++ } ++ ++ // Update buffer status ++ ct->m_nBufFullness -= ct->m_nAvgBitsPerFrame; ++ } ++ ++ ++ // Check if next skipped frame(s) needed ++ if (FieldType!=1 && !ct->b_fps_fixed && !bDummyFrame) { ++ if (ct->i_method == CONSTRAINED_VBR || ct->i_method == VBR) { ++ if (ct->m_nLongTermQP64 > (rcQP2Qstep(ct, ct->m_nFrameSkipThrQP)<<6) ++ && ct->m_nLastFrameBits >= (ct->m_nLastTargetBits<<1) ) { ++ //frameskip = (ct->m_nLastFrameBits / ct->m_nLastTargetBits)-1; ++ frameskip = (int)((ct->m_nLastFrameBits - ct->m_nLastTargetBits) / ct->m_nAvgBitsPerFrame - 1); ++ if (frameskip<0) ++ frameskip = 0; ++ else if (frameskip>ct->m_nMaxFrozenFrame) ++ frameskip = ct->m_nMaxFrozenFrame; ++ } ++ } ++ else if (ct->i_method == CBR) { ++ if (ct->m_nLastFrameAvgQStep[0]>rcQP2Qstep(ct, ct->m_nFrameSkipThrQP)) { ++ // Actual fullness is updated after encoding dummy-P frame ++ int nBufFullness = ct->m_nBufFullness; ++ while (nBufFullness > ct->m_nTargetFullness) { ++ nBufFullness = (int)(nBufFullness - ct->m_nAvgBitsPerFrame); ++ frameskip += 1; ++ } ++ } ++ } ++ } ++/* ++#ifdef DEBUG ++ if (frameskip > 255) ++ { ++ fprintf (stderr, "Warning: frameskip > 255\n"); ++ } ++ if (FieldType!=1){ ++ MFE_S64 tmp_bitrate ; ++ tmp_bitrate= (int)MFE_DIV_S64((MFE_S64)ct->m_nTotalBits*ct->fr_fps.num, ct->m_nFrameCount*ct->fr_fps.den) ; ++ ++// ms_dprintk(DRV_L3,"[CVBRRC] UpdateFrame(%7d bits, %3d%%) AvgQ=%2d LTQ=%2d Bitrate=%8d frameskip=%2d\n", ++// ct->m_nLastFrameBits, (ct->m_nLastFrameBits-ct->m_nTargetBits)*100/ct->m_nTargetBits, rcQstep2QP(ct, ct->m_nLastFrameAvgQStep[0]), ++// (int)(ct->m_nLongTermQP64+32)>>6,(int)tmp_bitrate, frameskip); ++ } ++ ++// DEBUG_RC(("[CVBRRC] UpdateFrame(%7d bits, %3d%%) AvgQ=%2d LTQ=%2d Bitrate=%8d frameskip=%2d\n", ++// totalUsedBits, (totalUsedBits-ct->m_nTargetBits)*100/ct->m_nTargetBits, ct->m_nLastFrameAvgQStep[0], ++// (int)ct->m_fLongTermQP, ct->m_nGaugeBitrate, frameskip)); ++#endif ++*/ ++ return frameskip; ++} ++ ++#define SMOOTH_PERIOD 1 ++#define INIT_QP_FACTOR 720 ++#define MIN_INIT_QP 1 ++#define MAX_INIT_QP 15 ++ ++/* Return target QPStep */ ++int cvbr_ComputeFrameQStep(cvbr_rc* ct, int nFrameType) ++{ ++ int newQPStep=0; ++ MFE_S64 buf_rest; ++ int buf_rest_pic; ++ int frames_left; ++ int nAdjust; ++ ++ int bitrate = ct->i_bps; ++ int targetFPS_DeNum = ct->fr_fps.den; ++ int targetFPS_Num = ct->fr_fps.num; ++ int TotalMB = ct->m_nTotalMB; ++ int frame_count = ct->m_nFrameCount; ++ ++ // For the very first frame, guess one qp! ++ if (ct->m_nFrameCount==0) { ++ ++ int nbpMb, newQP; ++ if (ct->i_method == CONST_QP) { ++ newQP = ct->i_qp; ++ newQPStep = rcQP2Qstep(ct, newQP); // So that frame qp will be exactly ct->i_qp ++ } ++ else { ++ nbpMb = (int)MFE_DIV_S64((MFE_S64)bitrate*targetFPS_DeNum, TotalMB*targetFPS_Num) +1 ; ++ //nbpMb = (int)((MFE_S64)ct->i_bps*ct->fr_fps.den)/(ct->m_nTotalMB*ct->fr_fps.num) + 1; ++ newQP = INIT_QP_FACTOR / nbpMb; ++ ++ if (newQPMAX_INIT_QP) ++ newQP = MAX_INIT_QP; ++ ++ newQPStep = newQP<m_nMaxFrozenFrame = newQP>>1; ++ ++ if (ct->m_nMaxFrozenFrame>15) ++ ct->m_nMaxFrozenFrame=15; ++ ++ return newQPStep; ++ } ++ ++ if (ct->i_method == CONST_QP) ++ return rcQP2Qstep(ct, ct->i_qp); ++ ++ if (ct->i_method == CBR) { ++ buf_rest= MFE_DIV_S64((MFE_S64)frame_count*targetFPS_DeNum*bitrate, targetFPS_Num) ; ++ //buf_rest = (((MFE_S64)ct->m_nFrameCount*ct->fr_fps.den*ct->i_bps)/ct->fr_fps.num); ++ buf_rest += (SMOOTH_PERIOD*ct->i_bps) - ct->m_nTotalBits; ++ ++ newQPStep = ct->m_nLastFrameAvgQStep[0]; ++ frames_left = (SMOOTH_PERIOD * ct->fr_fps.num) / ct->fr_fps.den; ++ //if (frames_left > 0) ++ { ++ int dQP; ++ buf_rest_pic = (int)MFE_DIV_S64(buf_rest , frames_left); ++ dQP = ct->m_nLastFrameAvgQStep[0]>>3; ++ if (ct->m_nLastFrameBits > (buf_rest_pic*9)>>3) { ++ newQPStep = ct->m_nLastFrameAvgQStep[0]+dQP; ++ } ++ else if (ct->m_nLastFrameBits < (buf_rest_pic*7)>>3) { ++ newQPStep = ct->m_nLastFrameAvgQStep[0]-dQP; ++ } ++ } ++ } ++ else if (ct->i_method == CONSTRAINED_VBR) { ++ int nLowBound, nHighBound; ++ nAdjust = ct->m_nLongTermQP64>>2; ++ nLowBound = (ct->m_nLongTermQP64 - nAdjust) >> 6; ++ nHighBound = (ct->m_nLongTermQP64 + nAdjust) >> 6; ++ if (ct->i_num_ppic>0 && nFrameType==I_VOP) { ++ newQPStep = ct->m_nLastFrameAvgQStep[0]; ++ if (ct->m_nGaugeBitratei_bps) ++ newQPStep = newQPStep-(1<m_nLongTermQP64 * MFE_DIV_S64(ct->m_nTotalBits,ct->m_nFrameCount), ct->m_nTargetBits) ; ++ //tmp = ct->m_nLongTermQP64 * (ct->m_nTotalBits/ct->m_nFrameCount) /ct->m_nTargetBits); ++ MFE_ASSERT((tmp >> 6) < (1<<31)); ++ newQPStep = (int)(MFE_DIV_S64((MFE_S64)ct->m_nLongTermQP64 * MFE_DIV_S64(ct->m_nTotalBits,ct->m_nFrameCount),ct->m_nTargetBits)>>6) ; ++ //newQPStep = (int)((ct->m_nLongTermQP64 * (ct->m_nTotalBits/ct->m_nFrameCount) / ct->m_nTargetBits) >> 6); ++ if (ct->m_nLastFrameBits>ct->m_nLastTargetBits) { ++ nAdjust = ((ct->m_nLastFrameBits-ct->m_nLastTargetBits)/ct->m_nMaxOffset) + (1<(3<m_nLastFrameAvgQStep[0]<<6) > ct->m_nLongTermQP64) { // Danger! Make it more aggressive ++ nHighBound = ct->m_nLastFrameAvgQStep[0]+nAdjust; ++ newQPStep = ct->m_nLastFrameAvgQStep[0]+nAdjust; ++ } ++ else { ++ nHighBound += nAdjust; ++ newQPStep += nAdjust; ++ } ++ } ++ else if (ct->m_nGaugeBitrate>ct->i_bps) { ++ if (newQPStep < ct->m_nLastFrameAvgQStep[0]) ++ newQPStep = ct->m_nLastFrameAvgQStep[0]; ++ if ((newQPStep<<6) < ct->m_nLongTermQP64) ++ newQPStep = ct->m_nLongTermQP64>>6; ++ } ++ else { ++ if ((newQPStep<<6) >= ct->m_nLongTermQP64) ++ newQPStep = (ct->m_nLongTermQP64>>6)-1; ++ if (ct->m_nTargetFullness>ct->m_nBufFullness) { ++ nAdjust = (ct->m_nTargetFullness-ct->m_nBufFullness) / (int)ct->i_bps; ++ newQPStep -= nAdjust; ++ } ++ } ++ } ++ newQPStep = MSRC_MIN(nHighBound, newQPStep); ++ newQPStep = MSRC_MAX(nLowBound, newQPStep); ++ } ++ else if (ct->i_method == VBR) { ++ int nLowBound, nHighBound; ++ if (ct->i_num_ppic>0 && nFrameType==I_VOP) { ++ newQPStep = ct->m_nLastFrameAvgQStep[0]; ++ if ((ct->m_nLastFrameAvgQStep[0]<<6) > ct->m_nLongTermQP64) ++ newQPStep = newQPStep-(1<m_nFrameCount >= ct->i_fps || ct->i_num_ppic==0) { ++ ++ tmp = MFE_DIV_S64((MFE_S64)ct->m_nLongTermQP64 * MFE_DIV_S64(ct->m_nTotalBits,ct->m_nFrameCount), ++ ct->m_nAvgBitsPerFrame); ++ MFE_ASSERT((tmp >> 6) < (1<<31)); ++ nAdjLTQ = (int)(MFE_DIV_S64((MFE_S64)ct->m_nLongTermQP64 * MFE_DIV_S64(ct->m_nTotalBits,ct->m_nFrameCount), ++ ct->m_nAvgBitsPerFrame)>>6); ++ } ++ else { ++ nAdjLTQ = ct->m_nLongTermQP64>>6; // Wait for stabilization ++ } ++ MFE_ASSERT(ct->m_nTargetBits>0); ++ newQPStep = (nAdjLTQ * ct->m_nAvgBitsPerFrame) / ct->m_nTargetBits; ++ ++ nAdjust = MSRC_MAX((2<>2); ++ nLowBound = (int)(nAdjLTQ) - nAdjust; ++ nHighBound = (int)(nAdjLTQ) + nAdjust; ++ ++ if (ct->m_nLastFrameBits>ct->m_nLastTargetBits) { ++ nAdjust = (int)(ct->m_nLastFrameBits/ct->m_nLastTargetBits); ++ if (nAdjust > 2) ++ nAdjust = 2; ++ nHighBound += nAdjust; ++ } ++ ++ if (ct->m_nAvgBitsPerFrame>ct->m_nTargetBits) { ++ newQPStep = MSRC_MIN(nHighBound, newQPStep); ++ } ++ else { ++ newQPStep = MSRC_MAX(nLowBound, newQPStep); ++ } ++ } ++ } ++ ++ return newQPStep; ++} ++ ++// int QP2QSTEP32[52] = { // QP2Qstep(QP) * 32 ++// 20, ++// 22, 26, 28, 32, 36, 40, 44, 52, 56, 64, ++// 72, 80, 88, 104, 112, 128, 144, 160, 176, 208, ++// 224, 256, 288, 320, 352, 416, 448, 512, 576, 640, ++// 704, 832, 896, 1024, 1152, 1280, 1408, 1664, 1792, 2048, ++// 2304, 2560, 2816, 3328, 3584, 4096, 4608, 5120, 5632, 6656, ++// 7168, ++// }; ++int rcQP2Qstep(cvbr_rc* ct, int QP) { ++ int i; ++ int Qstep; ++ static const int QP2QSTEP[6] = { 20, 22, 26, 28, 32, 36 }; ++ ++ Qstep = QP2QSTEP[QP%6]; ++ ++ for (i = 0; i < (QP/6); i++) { ++ Qstep *= 2; ++ } ++ ++ return Qstep; ++} ++ ++int rcQstep2QP(cvbr_rc* ct, int QstepX32) { ++ int q_per = 0, q_rem = 0; ++ ++ if (QstepX32 <= ct->m_nMinQStep) { ++ return ct->m_nMinQP; ++ } ++ else if (QstepX32 > ct->m_nMaxQStep) { ++ return ct->m_nMaxQP; ++ } ++ ++ while (QstepX32 > rcQP2Qstep(ct, 5)) { ++ QstepX32 >>= 1; ++ q_per += 1; ++ } ++ ++ if (QstepX32 <= 21) { ++ QstepX32 = 20; ++ q_rem = 0; ++ } ++ else if (QstepX32 <= 24) { ++ QstepX32 = 22; ++ q_rem = 1; ++ } ++ else if (QstepX32 <= 27) { ++ QstepX32 = 26; ++ q_rem = 2; ++ } ++ else if (QstepX32 <= 30) { ++ QstepX32 = 28; ++ q_rem = 3; ++ } ++ else if (QstepX32 <= 34) { ++ QstepX32 = 32; ++ q_rem = 4; ++ } ++ else { ++ QstepX32 = 36; ++ q_rem = 5; ++ } ++ ++ return (q_per * 6 + q_rem); ++} ++ ++#ifdef _SUPPORT_MBLEVEL_RC_ ++ ++//#define DUMP_FRAME_NO -1 //140 ++ ++// Each MB must call this routine once ++int cvbr_InitMB(cvbr_rc* ct, int nVar, const int nPrevQP, const int nBits, int IsIntra, int IsP4MV, int BPredType, int nResetDQ) ++{ ++#ifdef USE_INT_PREC ++ int nAvgAct, nActj, nNBits=0; ++#else ++ float fAvgAct, fActj, fNBits; ++#endif ++ int QStep, RtnQP, nVariance; ++// int TgtQP; ++ MFE_BOOL bChangeQP = 0; ++ int nMBX, nMBY; ++ ++#ifdef RAND_INPUT ++ nVariance = nVar = rand()%128; ++ //IsIntra = (rand()%4)==0 ? 1 : 0; ++ //Is4MV = (rand()%4)==0 ? 1 : 0; ++#else ++ nVariance = nVar; ++#endif ++ ++// if (ct->m_nFrameCount == DUMP_FRAME_NO) ++// printf("ct->m_nMBN = %d (MBX, MBY) = (%2d, %2d), nBits = %d\n", ct->m_nMBN, ct->m_nMBN%ct->m_nMbWidth, ct->m_nMBN/ct->m_nMbWidth, nBits); ++ ++// if (ct->m_rcGranularity==FRAMELEVELRC) { ++// return rcQstep2QP(ct->m_nFrameQStep); ++// } ++ ++ if (ct->m_nMBN==0) { // Initialization ++ ct->m_nSumAct = 0; ++ ct->m_nTargetUsedBits = 0; ++ } ++ ++ if (ct->m_nMBN>0) ++ { // Previous MB updating: Last MB is not counted! ++ // Update QP ++ ct->m_nPrevTopQP[(ct->m_nMBN-1)%ct->m_nMbWidth] = nPrevQP; ++ ct->m_nLastFrameAvgQStep[ct->m_bIsBotField] += rcQP2Qstep(ct, nPrevQP); ++ ++ // SW simulation hw pipeline: Update bit usage history ++ if (ct->m_nMBN<3) { ++ ct->m_nUsedBits[ct->m_nMBN-1] = nBits; ++ } ++ else { ++ ct->m_nUsedBits[0] = ct->m_nUsedBits[1]; ++ ct->m_nUsedBits[1] = nBits; ++ } ++ } ++ ++ if (ct->m_nMBN>1) // HW pipeline: See below nNBits (or fNBits) calculation ++ ct->m_nTargetUsedBits += ct->m_nTargetMbBits; ++ ++ // Update history ++ if (nVariance==0) { ++ nVariance = 1; ++ } ++ ++ ct->m_nSumAct += nVariance; ++ ++ // QP calculation ++ ct->m_nNewPacket = 0; // Default ++ if (ct->m_nMBN<2) { ++ RtnQP = rcQstep2QP(ct, ct->m_nFrameQStep); ++ } ++ else ++ { ++#ifdef USE_INT_PREC ++ nNBits = (ct->m_nUsedBits[0]<m_nTargetUsedBits; ++ //MFE_ASSERT(nNBits<(1<<(SCALE_BITS+6))); ++ if (nNBits>=(1<<(SCALE_BITS+6))) ++ nNBits = (1<<(SCALE_BITS+6)) - 1; ++ nAvgAct = ct->m_nSumAct / (ct->m_nMBN+1); ++ nActj = (((nVariance<<1) + nAvgAct) << SCALE_ACT) / (nVariance + (nAvgAct<<1)); ++ // Target QStep ++ if (ct->m_nFrameType==I_VOP) ++ QStep = (int)(((MFE_S64)ct->m_nFrameQStep * nActj) >> SCALE_ACT); ++ else ++ QStep = (int)(((MFE_S64)ct->m_nFrameQStep * nActj * nNBits) >> (SCALE_ACT+SCALE_BITS)); ++#else ++ fNBits = (float)ct->m_nUsedBits[0] / ct->m_nTargetUsedBits; ++ fAvgAct = (float)ct->m_nSumAct / (ct->m_nMBN+1); ++ fActj = ((nVariance*MBACT_NORMALIZATION_FACTOR) + fAvgAct) / (nVariance + (fAvgAct*MBACT_NORMALIZATION_FACTOR)); ++ // Target QStep ++ if (ct->m_nFrameType==I_VOP) ++ QStep = (int)(ct->m_nFrameQStep * fActj); ++ else ++ QStep = (int)(ct->m_nFrameQStep * fActj * fNBits); ++#endif ++ // if (QStep<(1<=0 && QStep<(1<<20)); ++ // Target QP ++ RtnQP = rcQstep2QP(ct, QStep); ++ // Refinement: Phase 1, top and left MB-QP limitation ++ if (ct->m_nMBN >= ct->m_nMbWidth) { ++ if (RtnQP > ct->m_nPrevTopQP[ct->m_nMBN%ct->m_nMbWidth] + TOP_QP_DIFF_LIMIT) { ++ RtnQP = ct->m_nPrevTopQP[ct->m_nMBN%ct->m_nMbWidth] + SPEC_QP_DIFF_LIMIT; ++ bChangeQP = 1; ++ } ++ else if (RtnQP < ct->m_nPrevTopQP[ct->m_nMBN%ct->m_nMbWidth] - TOP_QP_DIFF_LIMIT) { ++ RtnQP = ct->m_nPrevTopQP[ct->m_nMBN%ct->m_nMbWidth] - SPEC_QP_DIFF_LIMIT; ++ bChangeQP = 1; ++ } ++ } ++ ++ if (RtnQP > nPrevQP + LEFT_QP_DIFF_LIMIT) { ++ RtnQP = nPrevQP + SPEC_QP_DIFF_LIMIT; ++ bChangeQP = 1; ++ } ++ else if (RtnQP < nPrevQP - LEFT_QP_DIFF_LIMIT) { ++ RtnQP = nPrevQP - SPEC_QP_DIFF_LIMIT; ++ bChangeQP = 1; ++ } ++ // Refinement: Phase 2, spec QP range limitation ++ RtnQP = MSRC_MAX(ct->m_nMinQP, RtnQP); ++ RtnQP = MSRC_MIN(ct->m_nMaxQP, RtnQP); ++#if 0 // Don't need this because QP is bounded by rcQstep2QP(), ++ // and if TOP_QP_DIFF_LIMIT and BOTTOM_QP_DIFF_LIMIT >=2, there is no way to have +-1. ++ // Refinement: Phase 3, MPEG-4 B-frame limitation ++ if (ct->m_nCodecType==REG_ENC_MODE_MPG4 && ct->m_nFrameType==B_VOP /*&& RtnQP!=nPrevQP*/) { ++ if (RtnQP-nPrevQP==-1 || RtnQP-nPrevQP==1) ++ RtnQP = nPrevQP; ++ } ++#endif ++ // Avoid frequent QP changing ++ if (!bChangeQP) ++ RtnQP = nPrevQP; // Reset ++ ++ //DEBUG_RC((" [CVBRRC] %d : NBits=%d, AvgAct=%d\n", ct->m_nMBN, (int)fNBits, (int)fAvgAct )); ++ ++ ////////////////////////////////////////////////////////////////////////// ++ // er_en ++ if (ct->m_nVPSize) { ++ if (ct->m_nUsedBits[0]-ct->m_nLastVPBits>=ct->m_nVPSize) { ++ if (ct->m_nVPMbRow) { ++ nMBX = ct->m_nMBN%ct->m_nMbWidth; ++ nMBY = ct->m_nMBN/ct->m_nMbWidth; ++ if (nMBX==0 && nMBY>0 && (nMBY%ct->m_nVPMbRow)==0) { ++ ct->m_nNewPacket = 1; ++ ct->m_nLastVPBits = ct->m_nUsedBits[0]; ++ } ++ } ++ else { ++ ct->m_nNewPacket = 1; ++ ct->m_nLastVPBits = ct->m_nUsedBits[0]; ++ } ++ } ++ } ++ else if (ct->m_nVPMbRow) { ++ nMBX = ct->m_nMBN%ct->m_nMbWidth; ++ nMBY = ct->m_nMBN/ct->m_nMbWidth; ++ if (nMBX==0 && nMBY>0 && (nMBY%ct->m_nVPMbRow)==0) { ++ ct->m_nNewPacket = 1; ++ ct->m_nLastVPBits = ct->m_nUsedBits[0]; ++ } ++ } ++ } ++ ++ if (ct->b_mb_layer == 0) { ++ RtnQP = rcQstep2QP(ct, ct->m_nFrameQStep); ++ } ++ ++ ct->m_nMBN++; ++ ++ if (ct->i_method == CONST_QP) ++ return ct->i_qp; ++ ++ MFE_ASSERT(RtnQP<=ct->m_nMaxQP && RtnQP>=ct->m_nMinQP); ++ ++ return RtnQP; ++} ++ ++#else // _SUPPORT_MBLEVEL_RC_ not defined ++ ++int cvbr_InitMB(cvbr_rc* ct, int nVar, const int nPrevQP, const int nBits, int IsIntra, int IsP4MV, int BPredType, int nResetDQ) ++{ ++ if (ct->m_nMBN > 0) ++ ct->m_nLastFrameAvgQStep[ct->m_bIsBotField] += rcQP2Qstep(nPrevQP); ++ if (ct->i_method == CONST_QP) ++ return ct->i_qp; ++ return rcQstep2QP(ct->m_nFrameQStep); ++} ++ ++#endif // _SUPPORT_MBLEVEL_RC_ +diff --git a/drivers/mstar/mfev5/Kconfig b/drivers/mstar/mfev5/Kconfig +new file mode 100644 +index 00000000..3596a85d +--- /dev/null ++++ b/drivers/mstar/mfev5/Kconfig +@@ -0,0 +1,3 @@ ++config MS_MFEV5 ++ tristate "MFE-v5 driver" ++ help +diff --git a/drivers/mstar/mfev5/Makefile b/drivers/mstar/mfev5/Makefile +new file mode 100644 +index 00000000..a87bc16b +--- /dev/null ++++ b/drivers/mstar/mfev5/Makefile +@@ -0,0 +1,26 @@ ++# ++# Makefile for MStar MFE (Multi-Format Encoder) device driver. ++ ++ifdef CONFIG_ARCH_INFINITY ++ IP_NAME := mfe5 ++endif ++ ++ifdef CONFIG_ARCH_INFINITY3 ++ IP_NAME := mfe6 ++endif ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/mhve ++EXTRA_CFLAGS += -Idrivers/mstar/mfev5 ++EXTRA_CFLAGS += -Idrivers/mstar/mfev5/$(IP_NAME) ++ ++# files ++obj-$(CONFIG_MS_MFEV5) += mdrv_mmfe.o ++obj-$(CONFIG_MS_MFEV5) += $(IP_NAME)/ ++ ++mdrv_mmfe-y := \ ++ mmfe_module.o \ ++ mmfe_dev.o \ ++ mmfe_ctx.o \ ++ mmfe_rqc.o \ +diff --git a/drivers/mstar/mfev5/mfe5/Makefile b/drivers/mstar/mfev5/mfe5/Makefile +new file mode 100644 +index 00000000..ff480cce +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/Makefile +@@ -0,0 +1,22 @@ ++# ++# Makefile for MStar MFE driver on SOC INFINITY. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/mhve ++EXTRA_CFLAGS += -Idrivers/mstar/mfev5 ++EXTRA_CFLAGS += -Idrivers/mstar/mfev5/mfe5 ++ ++# files ++obj-$(CONFIG_MS_MFEV5) += mdrv_mfe5.o ++ ++mdrv_mfe5-y := \ ++ mfe.o \ ++ mfe_asic.o \ ++ mfe_h264.o \ ++ mfe_rctl.o \ ++ mfe_cvbr.o \ ++ mfe_msbr.o \ ++ mfe_msb2.o \ ++ mfe_msb3.o \ +diff --git a/drivers/mstar/mfev5/mfe5/mfe.c b/drivers/mstar/mfev5/mfe5/mfe.c +new file mode 100644 +index 00000000..15f92f1b +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe.c +@@ -0,0 +1,798 @@ ++ ++#include ++ ++#define _ALIGN(b,x) (((x)+(1<<(b))-1)&(~((1<<(b))-1))) ++#define _BITS_(s) ((2<<(1?s))-(1<<(0?s))) ++#define _MAX_(a,b) ((a)>(b)?(a):(b)) ++#define _MIN_(a,b) ((a)<(b)?(a):(b)) ++ ++#define MVBLK_DEFAULT \ ++ (MMFE_MVBLK_SKIP|MMFE_MVBLK_16x16|MMFE_MVBLK_16x8|MMFE_MVBLK_8x16|\ ++ MMFE_MVBLK_8x8|MMFE_MVBLK_8x4|MMFE_MVBLK_4x8|MMFE_MVBLK_4x4) ++ ++static int _seq_sync(mhve_ops*); ++static int _seq_conf(mhve_ops*); ++static int _seq_done(mhve_ops*); ++static int _enc_buff(mhve_ops*, mhve_vpb*); ++static int _deq_buff(mhve_ops*, mhve_vpb*); ++static int _put_data(mhve_ops*, void*,int); ++static int _enc_conf(mhve_ops*); ++static int _enc_done(mhve_ops*); ++static int _out_buff(mhve_ops*, mhve_cpb*); ++static int _set_conf(mhve_ops*, mhve_cfg*); ++static int _get_conf(mhve_ops*, mhve_cfg*); ++static void* _rqct_ops(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ return hndl->p_rqct; ++} ++static void* _mmfe_job(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ return hndl->p_regs; ++} ++static void __ops_free(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ rqct_ops* rqct = hndl->p_rqct; ++ mfe_regs* regs = hndl->p_regs; ++ if (regs) ++ MEM_FREE(regs); ++ if (rqct) ++ rqct->release(rqct); ++ MEM_FREE(hndl); ++} ++ ++void* mmfeops_acquire(int id) ++{ ++ mhve_ops* mops = NULL; ++ ++ while (NULL != (mops = MEM_ALLC(sizeof(mfe_hndl)))) ++ { ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ sps_t* sps = &hndl->m_sps; ++ pps_t* pps = &hndl->m_pps; ++ slice_t* sh = &hndl->m_sh; ++ ++ mops->release = __ops_free; ++ mops->rqct_ops = _rqct_ops; ++ mops->mhve_job = _mmfe_job; ++ mops->seq_sync = _seq_sync; ++ mops->seq_conf = _seq_conf; ++ mops->seq_done = _seq_done; ++ mops->enc_buff = _enc_buff; ++ mops->deq_buff = _deq_buff; ++ mops->put_data = _put_data; ++ mops->enc_conf = _enc_conf; ++ mops->enc_done = _enc_done; ++ mops->out_buff = _out_buff; ++ mops->set_conf = _set_conf; ++ mops->get_conf = _get_conf; ++ ++ hndl->p_rqct = rqctmfe_acquire(id); ++ hndl->p_regs = MEM_ALLC(sizeof(mfe_regs)); ++ if (!hndl->p_regs || !hndl->p_rqct) ++ break; ++ hndl->i_refn = 1; ++ hndl->i_dmvx = 32; ++ hndl->i_dmvy = 16; ++ hndl->i_subp = 2; ++ hndl->i_blkp[0] = MVBLK_DEFAULT; ++ hndl->i_blkp[1] = 0; ++ /* user data */ ++ sps->i_profile_idc = 66; ++ sps->i_level_idc = 30; ++ sps->b_constraint_set0 = 0; ++ sps->b_constraint_set1 = 1; ++ sps->b_constraint_set2 = 0; ++ sps->b_constraint_set3 = 0; ++ sps->i_log2_max_frame_num = 5; ++ sps->i_poc_type = 2; ++ sps->i_log2_max_poc_lsb = 4; // not used for poc_type=2 ++ sps->i_num_ref_frames = hndl->i_refn; ++ sps->b_gaps_in_frame_num_value_allow = 0; ++ sps->b_direct8x8_inference = 1; ++ sps->b_crop = 0; ++ /* gen pps */ ++ pps->i_pps_id = 0; ++ pps->b_cabac = 0; ++ pps->i_num_ref_idx_l0_default_active = sps->i_num_ref_frames; ++ pps->i_num_ref_idx_l1_default_active = sps->i_num_ref_frames; ++ pps->i_pic_init_qp = 26; ++ pps->i_pic_init_qs = 26; ++ pps->i_cqp_idx_offset = 0; ++ pps->b_redundant_pic_cnt = 0; ++ pps->b_deblocking_filter_control = 0; ++ pps->b_constrained_intra_pred = 0; ++ /* gen slice-header */ ++ sh->i_disable_deblocking_filter_idc = 0; ++ sh->i_alpha_c0_offset_div2 = 0; ++ sh->i_beta_offset_div2 = 0; ++ ++ return mops; ++ } ++ if (mops) ++ mops->release(mops); ++ return NULL; ++} ++ ++static int _seq_done(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ rqct_ops* rqct = hndl->p_rqct; ++ rqct->seq_done(rqct); ++ return 0; ++} ++ ++#define MB_SIZE 16 ++#define CROP_UNIT_X 2 ++#define CROP_UNIT_Y 2 ++ ++static int _seq_sync(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ rqct_ops* rqct = hndl->p_rqct; ++ sps_t* sps = &hndl->m_sps; ++ pps_t* pps = &hndl->m_pps; ++ slice_t* sh = &hndl->m_sh; ++ ++ pps->sps = sps; ++ sh->sps = sps; ++ sh->pps = pps; ++ /* gen sps */ ++ sps->i_num_ref_frames = hndl->i_refn; ++ sps->b_vui_param_pres = 1; ++ sps->vui.b_video_signal_pres = 1; ++ sps->vui.i_video_format = 5; ++ sps->vui.b_video_full_range = 1; ++ sps->vui.b_colour_desc_pres = 0; ++ sps->vui.i_colour_primaries = 1; ++ sps->vui.i_transf_character = 1; ++ sps->vui.i_matrix_coeffs = 1; ++ /* gen pps */ ++ pps->i_pps_id = 0; ++ pps->i_num_ref_idx_l0_default_active = sps->i_num_ref_frames; ++ pps->i_num_ref_idx_l1_default_active = sps->i_num_ref_frames; ++ pps->i_pic_init_qp = 26; ++ pps->i_pic_init_qs = 26; ++ pps->b_redundant_pic_cnt = 0; ++ /* rate control */ ++ rqct->seq_sync(rqct); ++ /*!rate control */ ++ hndl->b_seqh = 1; ++ hndl->i_seqn = 0; ++ hndl->i_obits = 0; ++ hndl->i_total = 0; ++ ++ return 0; ++} ++ ++static int _enc_buff(mhve_ops* mops, mhve_vpb* mvpb) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ sps_t *sps = &hndl->m_sps; ++ pps_t* pps = &hndl->m_pps; ++ slice_t* sh = &hndl->m_sh; ++ rqct_ops* rqct = hndl->p_rqct; ++ mfe_regs* regs = hndl->p_regs; ++ rpb_t* rpb; ++ bs_t outbs, *bs = &outbs; ++ rqct_buf vbuff; ++ uchar nal; ++ int i; ++ ++ hndl->m_encp = *mvpb; ++ mvpb = &hndl->m_encp; ++ ++ if (hndl->b_seqh) ++ { ++ static int mbs_level[5][2] = {{30, 40500},{31,108000},{32,216000},{40,245760},{50,589824}}; ++ int mbs; ++ sps->i_mb_w = hndl->i_mbsw; ++ sps->i_mb_h = hndl->i_mbsh; ++ sps->b_crop = 0; ++ if (hndl->i_pixw&(MB_SIZE-1) || hndl->i_pixh&(MB_SIZE-1)) ++ { ++ sps->b_crop = 1; ++ sps->crop.i_left = sps->crop.i_top = 0; ++ sps->crop.i_right = ((-hndl->i_pixw)&(MB_SIZE-1))/CROP_UNIT_X; ++ sps->crop.i_bottom= ((-hndl->i_pixh)&(MB_SIZE-1))/CROP_UNIT_Y; ++ } ++ mbs = sps->i_mb_w * sps->i_mb_h; ++ mbs = mbs * 30; ++ for (i = 0; i < 4 && mbs_level[i][1] < mbs; i++) ; ++ sps->i_level_idc = mbs_level[i][0]; ++ ++ avc_reset(bs, hndl->m_seqh, 32); ++ avc_write_nal(bs, (NAL_PRIO_HIGHEST<<5)|NAL_SPS); ++ avc_write_sps(bs, sps); ++ avc_flush(bs); ++ avc_write_nal(bs, (NAL_PRIO_HIGHEST<<5)|NAL_PPS); ++ avc_write_pps(bs, pps); ++ avc_flush(bs); ++ hndl->i_seqh = avc_count(bs); ++ rqct->seq_sync(rqct); ++ } ++ ++ vbuff.u_config = 0; ++ if (hndl->m_encp.u_flags&MMFE_FLAGS_IDR) ++ rqct->seq_sync(rqct); ++ if (hndl->m_encp.u_flags&MMFE_FLAGS_DISPOSABLE) ++ rqct->b_unrefp = 1; ++ if (hndl->m_encp.u_flags&MMFE_FLAGS_NIGHT_MODE) ++ vbuff.u_config |= RCTL_CFG_NIGHT; ++ hndl->m_encp.u_flags &=~MMFE_FLAGS_NIGHT_MODE; ++ ++ rqct->enc_buff(rqct, &vbuff); ++ ++ rqct->enc_conf(rqct, ®s->mjob); ++ ++ if (IS_IPIC(rqct->i_pictyp)) ++ { ++ sh->b_idr_pic = 1; ++ sh->i_ref_idc = NAL_PRIO_HIGHEST; ++ sh->i_type = SLICE_I; ++ hndl->m_encp.u_flags|= MMFE_FLAGS_IDR; ++ hndl->m_encp.u_flags&=~MMFE_FLAGS_DISPOSABLE; ++ hndl->b_seqh = 1; ++ } ++ else ++ { ++ sh->b_idr_pic = 0; ++ sh->i_ref_idc = (rqct->b_unrefp!=0)?NAL_PRIO_DISPOSED:NAL_PRIO_HIGH; ++ sh->i_type = IS_PPIC(rqct->i_pictyp)?SLICE_P:SLICE_I; ++ if (!rqct->b_unrefp) ++ hndl->m_encp.u_flags&=~MMFE_FLAGS_DISPOSABLE; ++ } ++ sh->i_qp = rqct->i_enc_qp; ++ ++ for (i = 0; i <= hndl->i_refn; i++) ++ { ++ rpb = &hndl->m_rpbs[i]; ++ if (IS_FREE(rpb->i_state)) ++ { ++ rpb->i_index = mvpb->i_index; ++ if (!rpb->b_valid) ++ { ++ rpb->u_phys[RPB_YPIX] = mvpb->planes[0].u_phys; ++ rpb->u_phys[RPB_CPIX] = mvpb->planes[1].u_phys; ++ mvpb->i_index = -1; ++ } ++ hndl->p_recn = rpb; ++ hndl->p_recn->i_state = RPB_STATE_BUSY; ++ break; ++ } ++ } ++ if (sh->b_idr_pic) ++ for (i = 0; i < hndl->i_refn; i++) ++ { ++ rpb = hndl->m_dpbs[i]; ++ if (rpb) ++ { ++ if (!rpb->b_valid) ++ mvpb->i_index = rpb->i_index; ++ rpb->i_state = RPB_STATE_FREE; ++ } ++ hndl->m_dpbs[i] = NULL; ++ } ++ /* set slice header */ ++ nal = (sh->i_ref_idc<<5) | NAL_SLICE; ++ if (sh->b_idr_pic) ++ { ++ sh->i_idr_pic_id = (sh->i_idr_pic_id+1)%2; ++ sh->i_frame_num = 0; ++ sh->i_num_ref_idx_l0_active = 0; ++ sh->i_poc = 0; ++ nal = (NAL_PRIO_HIGHEST<<5) | NAL_IDR; ++ } ++ else if (sh->i_ref_idc) ++ { ++ sh->i_frame_num = (sh->i_frame_num+1)%(1<i_log2_max_frame_num); ++ } ++ ++ avc_reset(bs, hndl->m_pich, 32); ++ avc_write_nal(bs, nal); ++ avc_write_slice_header(bs, sh); ++ avc_flush(bs); ++ hndl->i_pich = avc_count(bs); ++ ++ return 0; ++} ++ ++static int _deq_buff(mhve_ops* mops, mhve_vpb* mvpb) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ *mvpb = hndl->m_encp; ++ return 0; ++} ++ ++static int _enc_done(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ slice_t* sh = &hndl->m_sh; ++ rpb_t* dpb = NULL; ++ rqct_ops* rqct = hndl->p_rqct; ++ mfe_regs* regs = hndl->p_regs; ++ mhve_vpb* vpb = &hndl->m_encp; ++ ++ rqct->enc_done(rqct, ®s->mjob); ++ ++ hndl->i_obits = (rqct->i_bitcnt); ++ hndl->i_total+= (rqct->i_bitcnt)/8; ++ hndl->u_oused+= (rqct->i_bitcnt + regs->delta)/8; ++ /* update ref-list */ ++ dpb = hndl->p_recn; ++ if (sh->i_ref_idc) ++ { /* add recon. into reference list */ ++ int i; ++ for (i = 0; i < hndl->i_refn; i++) ++ { ++ rpb_t* out = hndl->m_dpbs[i]; ++ hndl->m_dpbs[i] = dpb; ++ dpb = out; ++ } ++ if (++sh->i_num_ref_idx_l0_active > sh->sps->i_num_ref_frames) ++ sh->i_num_ref_idx_l0_active = sh->sps->i_num_ref_frames; ++ } ++ if (dpb) ++ { ++ if (!dpb->b_valid) ++ vpb->i_index = dpb->i_index; ++ dpb->i_index = -1; ++ dpb->i_state = RPB_STATE_FREE; ++ } ++ hndl->p_recn = NULL; ++ ++sh->i_poc; ++ ++hndl->i_seqn; ++ hndl->b_seqh = 0; ++ return 0; ++} ++ ++#define MMFE_FLAGS_CTRL (MMFE_FLAGS_IDR|MMFE_FLAGS_DISPOSABLE) ++ ++static int _out_buff(mhve_ops* mops, mhve_cpb* mcpb) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ int err = 0; ++ if (mcpb->i_index >= 0) ++ { ++ hndl->u_oused = 0; ++ mcpb->planes[0].u_phys = 0; ++ mcpb->planes[0].i_size = 0; ++ return err; ++ } ++ err = hndl->u_oused; ++ mcpb->i_index = 0; ++ mcpb->planes[0].u_phys = hndl->u_obase; ++ mcpb->planes[0].i_size = err; ++ mcpb->i_stamp = hndl->m_encp.i_stamp; ++ mcpb->i_flags = (MMFE_FLAGS_SOP|MMFE_FLAGS_EOP)|(hndl->m_encp.u_flags&MMFE_FLAGS_CTRL); ++ return err; ++} ++ ++static int _seq_conf(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ mfe_regs* regs = hndl->p_regs; ++ pps_t* pps = &hndl->m_pps; ++ /* HW-IP related regs setting */ ++ // pre-fetch ++ regs->reg68_s_prfh_cryc_en = 1; // increase the tolerance of DRAM latency ++ regs->reg68_s_prfh_refy_en = 1; // increase the tolerance of DRAM latency ++ regs->reg6d_s_prfh_cryc_idle_cnt = 0; ++ regs->reg6d_s_prfh_refy_idle_cnt = 0; ++ // pixel format ++ regs->reg03_g_mstar_tile = 1; ++ regs->regd6_g_yuvldr_en = 0; ++ regs->regf4_s_plnrldr_en = 1; ++ // qtable ++ regs->reg03_g_qmode = 0; ++ // frame coding only ++ regs->reg03_g_fldpic_en = 0; ++ // NOT SW Buffer Mode ++ regs->reg73_g_sw_buffer_mode = 0; ++ regs->reg18_g_jpe_buffer_mode = 1; // frame-mode ++ regs->reg18_g_jpe_fsvs_mode = 0; ++ regs->reg18_g_viu_soft_rstz = 1; ++ // IMI buffer: low bandwidth ++ regs->reg68_s_marb_imi_burst_thd = 8; ++ regs->reg68_s_marb_imi_timeout = 7; ++ regs->reg68_s_marb_imilast_thd = 4; ++#if defined(MMFE_IMI_LBW_ADDR) ++ regs->reg68_s_marb_eimi_block = 1; ++ regs->reg68_s_marb_lbwd_mode = 1; ++ regs->reg6b_s_marb_imi_saddr_lo = (MMFE_IMI_LBW_ADDR>> 4)&0xFFFF; ++ regs->reg6c_s_marb_imi_saddr_hi = (MMFE_IMI_LBW_ADDR>>20)|0x1000; ++ regs->reg6c_s_marb_imi_cache_size = 0; // imi cache size (0: 64kB, 1:32kB, 2:16kB, 3:8kB) ++#else ++ regs->reg68_s_marb_eimi_block = 0; ++ regs->reg68_s_marb_lbwd_mode = 0; ++ regs->reg6b_s_marb_imi_saddr_lo = 0; ++ regs->reg6c_s_marb_imi_saddr_hi = 0; ++#endif ++ // IMI buffer: dbf last-line ++#if defined(MMFE_IMI_DBF_ADDR) ++ regs->reg4f_s_gn_bwr_mode = 3; ++ regs->reg4e_s_gn_mvibuf_saddr_lo = (MMFE_IMI_DBF_ADDR>> 3)&0xFFFF; ++ regs->reg4f_s_gn_mvibuf_saddr_hi = (MMFE_IMI_DBF_ADDR>>19)|0x0800; ++#else ++ regs->reg4f_s_gn_bwr_mode = 0; ++ regs->reg4e_s_gn_mvibuf_saddr_lo = 0; ++ regs->reg4f_s_gn_mvibuf_saddr_hi = 0; ++#endif ++ // Frame Coding Only ++ regs->reg2a_s_mvdctl_ref0_offset = 0; ++ regs->reg2a_s_mvdctl_ref1_offset = 0; ++ regs->reg7d_s_txip_eco0 = 0; ++ regs->reg7d_s_txip_eco1 = 0; ++ regs->reg7d_eco_mreq_stallgo = 1; ++ regs->reg7d_eco_marb_stallgo = 0; ++ regs->reg7d_reserved1 = 0; ++ regs->reg7d_eco_bsp_stuffing = 1; ++ regs->reg7d_eco_bsp_rdy_fix = 1; ++ regs->reg7d_eco_bsp_multi_slice_fix = 0; ++ /* global regs values (codec related) */ ++ regs->reg20_s_me_16x16_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_16x16); ++ regs->reg20_s_me_16x8_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_16x8); ++ regs->reg20_s_me_8x16_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_8x16); ++ regs->reg20_s_me_8x8_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_8x8); ++ regs->reg20_s_me_8x4_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_8x4); ++ regs->reg20_s_me_4x8_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_4x8); ++ regs->reg20_s_me_4x4_disable = !(hndl->i_blkp[0]&MMFE_MVBLK_4x4); ++ regs->reg20_s_mesr_adapt = 1; ++ regs->reg21_s_ime_sr16 = (hndl->i_dmvx<=16); ++ regs->reg21_s_ime_umv_disable = 0; ++ regs->reg22_s_ime_mesr_max_addr = (hndl->i_dmvy==16 ? 95 : 85); ++ regs->reg22_s_ime_mesr_min_addr = (hndl->i_dmvy==16 ? 0 : 10); ++ regs->reg23_s_ime_mvx_min = _MAX_(-hndl->i_dmvx+32,-32+32); ++ regs->reg23_s_ime_mvx_max = _MIN_( hndl->i_dmvx+32, 31+31); ++ regs->reg24_s_ime_mvy_min = _MAX_(-hndl->i_dmvy+16,-16+16); ++ regs->reg24_s_ime_mvy_max = _MIN_( hndl->i_dmvy+16, 16+15); ++ regs->reg25_s_fme_quarter_disable = (hndl->i_subp!=2); ++ regs->reg25_s_fme_half_disable = (hndl->i_subp==0); ++ regs->reg25_s_fme_pmv_enable = 0!=(hndl->i_blkp[0]&MMFE_MVBLK_SKIP); ++ regs->reg2b_s_ieap_constraint_intra = pps->b_constrained_intra_pred; ++ regs->reg2b_s_ieap_last_mode = 8; ++ regs->reg2b_s_ieap_ccest_en = 1; ++ regs->reg2b_s_ieap_ccest_thr = 3; ++ regs->reg2b_s_ieap_drop_i16 = 0; ++ regs->reg2b_s_ieap_early_termination = 1; ++ regs->reg2c_g_ieap_sram_4x2_swap = 1; ++ if (hndl->i_mbsw < 16) ++ regs->regfd_eco = 1; ++ return 0; ++} ++ ++static int _put_data(mhve_ops* mops, void* user, int size) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ mfe_regs* regs = hndl->p_regs; ++ int bcnt = 0; ++ int bits = 0; ++ char* src; ++ char* dst = hndl->p_okptr; ++ /* insert parm-sets */ ++ if (hndl->b_seqh) ++ { ++ MEM_COPY(dst, hndl->m_seqh, hndl->i_seqh/8); ++ bcnt+= hndl->i_seqh; ++ dst += hndl->i_seqh/8; ++ } ++ /* insert user-data */ ++ if (size > 0) ++ { ++ MEM_COPY(dst, user, size); ++ bcnt+= size*8; ++ dst += size; ++ } ++ /* insert slice-header */ ++ MEM_COPY(dst, hndl->m_pich, hndl->i_pich/8+1); ++ bits = hndl->i_pich; ++ bcnt+= bits; ++ hndl->u_oused = (bcnt>>6)*8; ++ src = hndl->p_okptr + hndl->u_oused; ++ dst = regs->coded; ++ MEM_COPY(dst, src, ((bcnt/8)%8)+1); ++ regs->count = bcnt&63; ++ regs->delta = regs->count - bits; ++ return 0; ++} ++ ++static int _enc_conf(mhve_ops* mops) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ mhve_vpb* encp = &hndl->m_encp; ++ mfe_regs* regs = hndl->p_regs; ++ sps_t* sps = &hndl->m_sps; ++ pps_t* pps = &hndl->m_pps; ++ slice_t* sh = &hndl->m_sh; ++ uint phys; ++ ushort v; ++ // codec type ( only support h.264 ) ++ regs->reg00_g_enc_mode = MFE_REG_ENC_H264; ++ regs->reg03_g_cabac_en = pps->b_cabac; ++ switch (hndl->e_pixf) ++ { ++ case MHVE_PIX_NV21: ++ regs->regf3_s_plnrldr_c_swap = MFE_REG_PLNRLDR_VU; ++ case MHVE_PIX_NV12: ++ regs->regf3_s_plnrldr_format = MFE_REG_PLNRLDR_420; ++ regs->reg90_g_capture_width_y= hndl->m_encp.i_pitch; ++ regs->reg91_g_capture_width_c= hndl->m_encp.i_pitch>>1; ++ break; ++ case MHVE_PIX_YVYU: ++ regs->regf3_s_plnrldr_c_swap = MFE_REG_PLNRLDR_VU; ++ case MHVE_PIX_YUYV: ++ regs->regf3_s_plnrldr_format = MFE_REG_PLNRLDR_422; ++ regs->reg90_g_capture_width_y= hndl->m_encp.i_pitch; ++ regs->reg91_g_capture_width_c= 0; ++ break; ++ default: ++ break; ++ } ++ // resolution ++ regs->reg01_g_pic_width = hndl->i_pctw; ++ regs->reg02_g_pic_height= hndl->i_pcth; ++ // mdc ++ regs->reg29_s_mbr_qp_cidx_offset = pps->i_cqp_idx_offset; ++ // clock gating ++ regs->reg16 = 0xFFFF; ++ // per-frame: ref_frames/frame_type ++ regs->reg00_g_frame_type = sh->i_type==SLICE_I?MFE_REG_ITYPE:sh->i_type==SLICE_P?MFE_REG_PTYPE:MFE_REG_BTYPE; ++ regs->reg00_g_ref_no = sh->i_num_ref_idx_l0_active==2?MFE_REG_REF_NUM_TWO:MFE_REG_REF_NUM_ONE; ++ // per-frame: slice parameters ++ regs->reg39_s_mdc_h264_nal_ref_idc = sh->i_ref_idc; ++ regs->reg39_s_mdc_h264_nal_unit_type = sh->b_idr_pic; ++ regs->reg39_s_mdc_h264_fnum_bits = sps->i_log2_max_frame_num-5; ++ regs->reg39_s_mdc_h264_dbf_control = pps->b_deblocking_filter_control; ++ regs->reg39_s_mdc_h264_fnum_value = sh->i_frame_num; ++ regs->reg3a_s_mdc_h264_idr_pic_id = sh->i_idr_pic_id; ++ regs->reg3a_s_mdc_h264_disable_dbf_idc = sh->i_disable_deblocking_filter_idc; ++ regs->reg3a_s_mdc_h264_alpha = sh->i_alpha_c0_offset_div2; ++ regs->reg3a_s_mdc_h264_beta = sh->i_beta_offset_div2; ++ regs->reg3a_s_mdc_h264_ridx_aor_flag = (sh->i_num_ref_idx_l0_active!=sh->pps->i_num_ref_idx_l0_default_active); ++ // per-frame: buffer setting: current/reference/reconstructing ++ phys = encp->planes[0].u_phys+encp->planes[0].i_bias; ++ regs->reg06_g_cur_y_addr_lo = (ushort)(phys>> 8); ++ regs->reg07_g_cur_y_addr_hi = (ushort)(phys>>24); ++ phys = encp->planes[1].u_phys+encp->planes[1].i_bias; ++ regs->reg08_g_cur_c_addr_lo = (ushort)(phys>> 8); ++ regs->reg09_g_cur_c_addr_hi = (ushort)(phys>>24); ++ if (sh->i_num_ref_idx_l0_active) ++ { ++ regs->reg0a_g_ref_y_addr0_lo = (ushort)(hndl->m_dpbs[0]->u_phys[RPB_YPIX]>> 8); ++ regs->reg0b_g_ref_y_addr0_hi = (ushort)(hndl->m_dpbs[0]->u_phys[RPB_YPIX]>>24); ++ regs->reg0e_g_ref_c_addr0_lo = (ushort)(hndl->m_dpbs[0]->u_phys[RPB_CPIX]>> 8); ++ regs->reg0f_g_ref_c_addr0_hi = (ushort)(hndl->m_dpbs[0]->u_phys[RPB_CPIX]>>24); ++ } ++ regs->reg12_g_rec_y_addr_lo = (ushort)(hndl->p_recn->u_phys[RPB_YPIX]>> 8); ++ regs->reg13_g_rec_y_addr_hi = (ushort)(hndl->p_recn->u_phys[RPB_YPIX]>>24); ++ regs->reg14_g_rec_c_addr_lo = (ushort)(hndl->p_recn->u_phys[RPB_CPIX]>> 8); ++ regs->reg15_g_rec_c_addr_hi = (ushort)(hndl->p_recn->u_phys[RPB_CPIX]>>24); ++ // Output buffers: Must be 8-byte aligned. ++ regs->reg3f_s_bspobuf_hw_en = 0; ++ // GN ++ regs->reg4c_s_gn_saddr_lo = (ushort)(hndl->u_mbp_base>> 3); ++ regs->reg4d_s_gn_saddr_hi = (ushort)(hndl->u_mbp_base>>19); ++ regs->reg4d_s_gn_saddr_mode = 0; // 0: gn data row, 1: gn data frame. ++ // Motion search ++ regs->reg20_s_me_ref_en_mode = (1<i_num_ref_idx_l0_active)-1; ++ // FME ++ regs->reg21_s_ime_ime_wait_fme = 1; ++ regs->reg25_s_fme_pipeline_on = regs->reg21_s_ime_ime_wait_fme ? 1 : 0; ++ // P8x8 BOUND RECT ++ regs->reg21_s_ime_boundrect_en = (sps->i_profile_idc==66 && sps->i_level_idc<=30); ++ regs->reg21_s_ime_h264_p8x8_ctrl_en = 0;//mfeinfo->i_p8x8_max_count < hndl->i_mb_wxh ? 1 : 0; ++ ++ regs->reg25_s_fme_mode0_refno = 1; ++ regs->reg25_s_fme_mode1_refno = 1; ++ regs->reg25_s_fme_mode2_refno = 1; ++ regs->reg25_s_fme_mode_no = (hndl->i_mbsn <= 396); ++ // Intra update (force disabled) ++ regs->reg2f_s_txip_irfsh_en = 0; ++ regs->reg2c_s_quan_idx_last = 63; ++ if (regs->reg2c_s_quan_idx_last < 63) ++ regs->reg2c_s_quan_idx_swlast = 1; ++ else ++ regs->reg2c_s_quan_idx_swlast = 0; ++ /* multi-slice mode */ ++ if (sps->i_poc_type != 2) ++ regs->reg03_g_er_mode = _BITS_(1:0); ++ else ++ { ++ v = hndl->i_rows > 0; ++ if (hndl->i_bits > 0) ++ v += 2; ++ regs->reg03_g_er_mode = _BITS_(1:0)&(v-1); ++ /* multi-slice by bits */ ++ regs->reg04_g_er_bs_th = hndl->i_bits; ++ /* multi-slice by row: 1/2/4/8 */ ++ for (v = 0; v < 3 && hndl->i_rows > (int)(1<reg03_g_er_mby = v; ++ } ++ ++ if (regs->regf2_g_roi_en != 0) ++ regs->reg00_g_mbr_en = 0; ++ regs->reg00_g_rec_en = 1; ++ ++ regs->obase[0] = hndl->u_obase + hndl->u_oused; ++ regs->osize[0] = hndl->u_osize - hndl->u_oused; ++ return 0; ++} ++ ++static int _set_conf(mhve_ops* mops, mhve_cfg* mcfg) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ int i, err = -1; ++ switch (mcfg->type) ++ { ++ case MHVE_CFG_RES: ++ if ((unsigned)mcfg->res.e_pixf <= MHVE_PIX_YVYU) ++ { ++ hndl->e_pixf = mcfg->res.e_pixf; ++ hndl->i_pixw = mcfg->res.i_pixw; ++ hndl->i_pixh = mcfg->res.i_pixh; ++ hndl->i_pctw = _ALIGN(4,mcfg->res.i_pixw); ++ hndl->i_pcth = _ALIGN(4,mcfg->res.i_pixh); ++ hndl->i_rpbn = mcfg->res.i_rpbn; ++ hndl->u_conf = mcfg->res.u_conf; ++ hndl->i_mbsw = hndl->i_pctw >>4; ++ hndl->i_mbsh = hndl->i_pcth >>4; ++ hndl->i_mbsn = hndl->i_mbsw*hndl->i_mbsh; ++ hndl->b_seqh = 1; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_DMA: ++ if ((unsigned)mcfg->dma.i_dmem < 2) ++ { ++ uint addr = mcfg->dma.u_phys; ++ int i = mcfg->dma.i_dmem; ++ rpb_t* ref = hndl->m_rpbs+i; ++ ref->i_index =-1; ++ ref->i_state = RPB_STATE_FREE; ++ ref->u_phys[RPB_YPIX] = !mcfg->dma.i_size[0]?0:addr; ++ addr += mcfg->dma.i_size[0]; ++ ref->u_phys[RPB_CPIX] = !mcfg->dma.i_size[1]?0:addr; ++ addr += mcfg->dma.i_size[1]; ++ ref->b_valid = ref->u_phys[RPB_YPIX]!=0; ++ err = 0; ++ } ++ else if (mcfg->dma.i_dmem == -1) ++ { ++ hndl->p_okptr = mcfg->dma.p_vptr; ++ hndl->u_obase = mcfg->dma.u_phys; ++ hndl->u_osize = mcfg->dma.i_size[0]; ++ hndl->u_oused = 0; ++ err = 0; ++ } ++ else if (mcfg->dma.i_dmem == -2) ++ { ++ hndl->u_mbp_base = mcfg->dma.u_phys; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_MOT: ++ hndl->i_subp = mcfg->mot.i_subp; ++ hndl->i_dmvx = mcfg->mot.i_dmvx; ++ hndl->i_dmvy = mcfg->mot.i_dmvy; ++ hndl->i_blkp[0] = mcfg->mot.i_blkp[0]; ++ hndl->i_blkp[1] = 0; ++ err = 0; ++ break; ++ case MHVE_CFG_AVC: ++ { ++ sps_t* sps = &hndl->m_sps; ++ pps_t* pps = &hndl->m_pps; ++ slice_t* sh = &hndl->m_sh; ++ hndl->i_refn = 1; ++ sps->i_profile_idc = MMFE_AVC_PROFILE_MP; ++ if (mcfg->avc.i_profile < MMFE_AVC_PROFILE_MP) ++ { ++ sps->i_profile_idc = MMFE_AVC_PROFILE_BP; ++ pps->b_cabac = 0; ++ } ++ if (mcfg->avc.i_level < MMFE_AVC_LEVEL_3) ++ sps->i_level_idc = MMFE_AVC_LEVEL_3; ++ if (mcfg->avc.i_level > MMFE_AVC_LEVEL_4) ++ sps->i_level_idc = MMFE_AVC_LEVEL_4; ++ sps->i_poc_type = mcfg->avc.i_poc_type==0?0:2; ++ pps->b_cabac = mcfg->avc.b_entropy_coding_type!=0; ++ pps->b_deblocking_filter_control = mcfg->avc.b_deblock_filter_control; ++ pps->b_constrained_intra_pred = mcfg->avc.b_constrained_intra_pred; ++ sh->i_disable_deblocking_filter_idc = mcfg->avc.i_disable_deblocking_idc; ++ sh->i_alpha_c0_offset_div2 = mcfg->avc.i_alpha_c0_offset; ++ sh->i_beta_offset_div2 = mcfg->avc.i_beta_offset; ++ hndl->b_seqh = 1; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_VUI: ++ { ++ sps_t* sps = &hndl->m_sps; ++ sps->b_vui_param_pres = 0; ++ sps->vui.b_video_full_range = mcfg->vui.b_video_full_range!=0; ++ if (sps->vui.b_video_full_range) ++ { ++ sps->vui.b_video_signal_pres = 1; ++ sps->vui.i_video_format = 5; ++ sps->vui.b_colour_desc_pres = 0; ++ sps->b_vui_param_pres = 1; ++ } ++ hndl->b_seqh = 1; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_SPL: ++ hndl->i_bits = mcfg->spl.i_bits; ++ hndl->i_rows = 0; ++ if (0 < mcfg->spl.i_rows) ++ { ++ for (i = 1; i < 8 && mcfg->spl.i_rows > i; i = i<<1) ; ++ hndl->i_rows = mcfg->spl.i_rows = i; ++ } ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ return err; ++} ++ ++static int _get_conf(mhve_ops* mops, mhve_cfg* mcfg) ++{ ++ mfe_hndl* hndl = (mfe_hndl*)mops; ++ int err = -1; ++ switch (mcfg->type) ++ { ++ case MHVE_CFG_RES: ++ mcfg->res.e_pixf = hndl->e_pixf; ++ mcfg->res.i_pixw = hndl->i_pixw; ++ mcfg->res.i_pixh = hndl->i_pixh; ++ mcfg->res.i_rpbn = hndl->i_rpbn; ++ mcfg->res.u_conf = hndl->u_conf; ++ err = 0; ++ break; ++ case MHVE_CFG_MOT: ++ mcfg->mot.i_subp = hndl->i_subp; ++ mcfg->mot.i_dmvx = hndl->i_dmvx; ++ mcfg->mot.i_dmvy = hndl->i_dmvy; ++ mcfg->mot.i_blkp[0] = hndl->i_blkp[0]; ++ mcfg->mot.i_blkp[1] = 0; ++ err = 0; ++ break; ++ case MHVE_CFG_AVC: ++ { ++ sps_t* sps = &hndl->m_sps; ++ pps_t* pps = &hndl->m_pps; ++ slice_t* sh = &hndl->m_sh; ++ mcfg->avc.i_profile = sps->i_profile_idc; ++ mcfg->avc.i_level = sps->i_level_idc; ++ mcfg->avc.i_num_ref_frames = hndl->i_refn; ++ mcfg->avc.i_poc_type = sps->i_poc_type; ++ mcfg->avc.b_entropy_coding_type = pps->b_cabac; ++ mcfg->avc.b_deblock_filter_control = pps->b_deblocking_filter_control; ++ mcfg->avc.b_constrained_intra_pred = pps->b_constrained_intra_pred; ++ mcfg->avc.i_disable_deblocking_idc = sh->i_disable_deblocking_filter_idc; ++ mcfg->avc.i_alpha_c0_offset = sh->i_alpha_c0_offset_div2; ++ mcfg->avc.i_beta_offset = sh->i_beta_offset_div2; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_VUI: ++ { ++ sps_t* sps = &hndl->m_sps; ++ mcfg->vui.b_video_full_range = sps->b_vui_param_pres!=0 && sps->vui.b_video_full_range!=0; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_SPL: ++ mcfg->spl.i_rows = hndl->i_rows; ++ mcfg->spl.i_bits = hndl->i_bits; ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ return err; ++} +diff --git a/drivers/mstar/mfev5/mfe5/mfe.h b/drivers/mstar/mfev5/mfe5/mfe.h +new file mode 100644 +index 00000000..8516d4b1 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe.h +@@ -0,0 +1,86 @@ ++ ++#ifndef _MFE_H_ ++#define _MFE_H_ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++typedef struct rpb_t { ++ char b_valid; /* 1: allocated direct memory. 0: use pic+'s memory */ ++ #define RPB_STATE_FREE 0 ++ #define RPB_STATE_BUSY 1 ++ #define RPB_STATE_INVL -1 ++ #define IS_FREE(s) ((s)==RPB_STATE_FREE) ++ #define IS_INVL(s) ((s)==RPB_STATE_INVL) ++ char i_state; ++ short i_index; ++ #define RPB_YPIX 0 ++ #define RPB_CPIX 1 ++ #define RPB_SIZE 2 ++ uint u_phys[RPB_SIZE]; ++} rpb_t; ++ ++typedef struct mfe_hndl { ++ mhve_ops ops; ++ /* mfe-registers */ ++ mfe_regs* p_regs; ++ /* rate control */ ++ rqct_ops* p_rqct; ++ /* seq counter */ ++ mhve_vpb m_encp; ++ int i_seqn; ++ int b_seqh; ++ /* current resource */ ++ mhve_pix_e e_pixf; ++ short i_pixw, i_pixh; ++ int i_rpbn; ++ uint u_conf; ++ short i_pctw, i_pcth; ++ short i_mbsw, i_mbsh; ++ int i_mbsn; ++ /* motion search */ ++ int i_dmvx; ++ int i_dmvy; ++ int i_subp; ++ uint i_blkp[2]; ++ /* h264_enc */ ++ sps_t m_sps; ++ pps_t m_pps; ++ slice_t m_sh; ++ /* multi-slices */ ++ int i_rows; ++ int i_bits; ++ /* freeback and statistic */ ++ int i_total; ++ int i_obits; ++ /* output bits */ ++ char* p_okptr; ++ uint u_obase; ++ uint u_osize; ++ uint u_obias; ++ uint u_oused; ++ uint u_vacan; ++ /*!output bits */ ++ uint u_mbp_base; ++ /* frame buffers */ ++ #define RPB_MAX_NR 4 ++ int i_refn; ++ rpb_t* p_recn; ++ rpb_t* m_dpbs[RPB_MAX_NR]; ++ rpb_t m_rpbs[RPB_MAX_NR]; ++ /* fragment of bits */ ++ /* sequence header */ ++ int i_seqh; ++ uchar m_seqh[32]; ++ /* picture header */ ++ int i_pich; ++ uchar m_pich[32]; ++} mfe_hndl; ++ ++#endif//_MFE_H_ +diff --git a/drivers/mstar/mfev5/mfe5/mfe_asic.c b/drivers/mstar/mfev5/mfe5/mfe_asic.c +new file mode 100644 +index 00000000..e768f1a7 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_asic.c +@@ -0,0 +1,396 @@ ++ ++#include ++ ++#include ++#include ++#include ++ ++static void _release(void* p) { if (p) kfree(p); } ++ ++static int _set_bank(mhve_ios*, mhve_reg*); ++static int _enc_fire(mhve_ios*, mhve_job*); ++static int _enc_poll(mhve_ios*); ++static int _isr_func(mhve_ios*, int); ++static int _irq_mask(mhve_ios*, int); ++ ++mhve_ios* mmfeios_acquire( ++ char* tags) ++{ ++ mfe_asic* asic = MEM_ALLC(sizeof(mfe_asic)); ++ if (asic) ++ { ++ mhve_ios* mios = &asic->mios; ++ mios->release = _release; ++ mios->set_bank = _set_bank; ++ mios->enc_fire = _enc_fire; ++ mios->enc_poll = _enc_poll; ++ mios->isr_func = _isr_func; ++ mios->irq_mask = _irq_mask; ++ } ++ return &asic->mios; ++} ++ ++static int _set_bank( ++ mhve_ios* ios, ++ mhve_reg* reg) ++{ ++ int err = 0; ++ mfe_asic* asic = (mfe_asic*)ios; ++ switch (reg->i_id) ++ { ++ case 0: ++ asic->p_base = reg->base; ++ break; ++ default: ++ err = -1; ++ break; ++ } ++ return err; ++} ++ ++#define REGW(base,idx) (*(((volatile unsigned short*)(base))+2*(idx))) ++ ++#if defined(MMFE_REGS_TRACE) ++#define PRINT(s,idx,v) printk(#s":bank%d[%02x]=%04x\n",(idx&0x80)?1:0,idx&0x7F,v) ++#define REGWR(base,idx,v,cmt) do{REGW(base,idx)=(v);PRINT(w,idx,v);}while(0) ++#define REGRD(base,idx,cmt) ({ushort v=REGW(base,idx);PRINT(r,idx,v); v;}) ++#else ++#define REGWR(base,idx,val,cmt) REGW(base,idx)=(val) ++#define REGRD(base,idx,cmt) REGW(base,idx) ++#endif ++ ++ ++static void ++clr_irq( ++ void* base, ++ uint bits) ++{ ++ REGWR(base,0x1d,bits,"clr irq"); ++} ++ ++static void ++msk_irq( ++ void* base, ++ uint bits) ++{ ++ REGWR(base,0x1c,bits,"msk irq"); ++} ++ ++static uint ++bit_irq( ++ void* base) ++{ ++ return 0xFF®RD(base,0x1e,"bit irq"); ++} ++ ++static void ++set_outbs_addr( ++ void* base, ++ mfe_regs* regs, ++ uint32 addr, ++ int size) ++{ ++#define UPDATE_ADDR (1<<1) // reg3b_s_bspobuf_set_adr ++#define SET_ADDRESS (1<<0) // reg3f_s_bspobuf_update_adr ++ uint32 value; ++ // address value ++ value = addr; ++ regs->reg3e = 0; ++ // For Safety ++ regs->reg3e_s_obuf_write_id_adr = 0; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ regs->reg3c_s_bspobuf_lo = (uint16)(value>> 3); ++ regs->reg3d_s_bspobuf_hi = (uint16)(value>>19); ++ regs->reg3d_s_obuf_id = 0; // sta. addr ++ REGWR(base,0x3c,regs->reg3c,"bspobuf addr_lo"); ++ REGWR(base,0x3d,regs->reg3d,"bspobuf addr_hi"); ++ regs->reg3e_s_obuf_write_id_adr = 1; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ // update-adr ++ REGWR(base,0x3f,regs->reg3f|UPDATE_ADDR,"ref_mfe_s_bspobuf_update_adr"); ++ value += (size-8); ++ // For Safety ++ regs->reg3e_s_obuf_write_id_adr = 0; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ regs->reg3c_s_bspobuf_lo = (uint16)(value>> 3); ++ regs->reg3d_s_bspobuf_hi = (uint16)(value>>19); ++ regs->reg3d_s_obuf_id = 1; // end. addr ++ REGWR(base,0x3c,regs->reg3c,"bspobuf addr_lo"); ++ REGWR(base,0x3d,regs->reg3d,"bspobuf addr_hi"); ++ regs->reg3e_s_obuf_write_id_adr = 1; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ // update-adr ++ REGWR(base,0x3f,regs->reg3f|UPDATE_ADDR,"ref_mfe_s_bspobuf_update_adr"); ++ // address set ++ regs->reg3b_s_mvobuf_set_adr = 0; ++ regs->reg3b_s_mvobuf_fifo_th = 0; ++ regs->reg3b_s_bspobuf_fifo_th = 1; ++ REGWR(base,0x3b,regs->reg3b|SET_ADDRESS,"set bsp obuf"); ++} ++ ++static void ++put_coded_bits( ++ void* base, ++ mfe_regs* regs, ++ uchar* code, ++ int size) ++{ ++ int round = (size+15)>>4; ++ ushort word = 0; ++ ++ regs->reg46 = regs->reg47 = regs->reg48 = 0; ++ ++ if (size == 0) ++ { ++ regs->reg47_s_fdc_bs_count = 0; ++ REGWR(base,0x47,regs->reg47,"fdc round count"); ++ regs->reg46_s_fdc_bs = 0; ++ regs->reg47_s_fdc_bs_len = 0; ++ regs->reg48_s_fdc_bs_vld = 1; ++ REGWR(base,0x46,regs->reg46,"fdc bs "); ++ REGWR(base,0x47,regs->reg47,"fdc len"); ++ REGWR(base,0x48,regs->reg48,"fdc vld"); ++ regs->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ return; ++ } ++ // Fill the total round regs ++ regs->reg47_s_fdc_bs_count = round - 1; // Count from 0 ++ REGWR(base,0x47,regs->reg47,"fdc round count"); ++ ++ while (size > 16) ++ { ++ word = (code[0]<<8) | code[1]; ++ code += 2; ++ size -= 16; ++ ++ regs->reg46_s_fdc_bs = word; ++ regs->reg47_s_fdc_bs_len = 15; ++ regs->reg48_s_fdc_bs_vld = 1; ++ REGWR(base,0x46,regs->reg46,"fdc bs "); ++ REGWR(base,0x47,regs->reg47,"fdc len"); ++ REGWR(base,0x48,regs->reg48,"fdc vld"); ++ regs->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ } ++ ++ if (size > 0) ++ { ++ word = code[0]<<8; ++ if (size > 8) ++ word += code[1]; ++ regs->reg46_s_fdc_bs = word; ++ regs->reg47_s_fdc_bs_len = size; ++ regs->reg48_s_fdc_bs_vld = 1; ++ REGWR(base,0x46,regs->reg46,"fdc bs "); ++ REGWR(base,0x47,regs->reg47,"fdc len"); ++ REGWR(base,0x48,regs->reg48,"fdc vld"); ++ regs->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ } ++} ++ ++static int _enc_fire( ++ mhve_ios* ios, ++ mhve_job* job) ++{ ++ mfe_asic* asic = (mfe_asic*)ios; ++ mfe_regs* regs = (mfe_regs*)job; ++ void* base = asic->p_base; ++ asic->p_regs = regs; ++ /* flush regs to mfe-hw */ ++ msk_irq(base, 0x00); ++ // switch to sw mode ++ regs->reg03_g_tbc_mode = 0; ++ REGWR(base,0x03,regs->reg03,"tbc_mode=0"); ++ // switch to hw mode ++ regs->reg03_g_tbc_mode = 1; ++ REGWR(base,0x03,regs->reg03,"tbc_mode=1"); ++ // sw reset ++ regs->reg00_g_soft_rstz = 0; ++ REGWR(base,0x00,regs->reg00,"SW reset 0"); ++ udelay(1); ++ regs->reg00_g_soft_rstz = 1; ++ REGWR(base,0x00,regs->reg00,"SW reset 1"); ++ REGWR(base,0x80,regs->reg80,"pp mode"); ++ REGWR(base,0x01,regs->reg01,"pic width"); ++ REGWR(base,0x02,regs->reg02,"pic height"); ++ REGWR(base,0x90,regs->reg90,"capture width y"); ++ REGWR(base,0x91,regs->reg91,"capture width c"); ++ REGWR(base,0xf2,regs->regf2,"roi settings"); ++ REGWR(base,0xf3,regs->regf3,"plnrldr setting"); ++ REGWR(base,0xf4,regs->regf4,"plnrldr enable"); ++ REGWR(base,0xfb,regs->regfb,"roi qmap addr lo"); ++ REGWR(base,0xfc,regs->regfc,"roi qmap addr hi"); ++ REGWR(base,0xfd,regs->regfd,"eco"); ++ REGWR(base,0x03,regs->reg03,"value"); ++ REGWR(base,0x04,regs->reg04,"er_bs mode threshold"); ++ REGWR(base,0x05,regs->reg05,"inter prediction perference"); ++ /* mb-pitch / packed422 / yuv-loader */ ++ REGWR(base,0x8b,regs->reg8b,"mb pitch"); ++ REGWR(base,0xd2,regs->regd2,"packed422 mode"); ++ REGWR(base,0xd6,regs->regd6,"yuv loader"); ++ /* sambc */ ++ REGWR(base,0xdb,regs->regdb,"sambc"); ++ REGWR(base,0xdc,regs->regdc,"sambc"); ++ REGWR(base,0xdd,regs->regdd,"sambc"); ++ REGWR(base,0xde,regs->regde,"sambc"); ++ REGWR(base,0xdf,regs->regdf,"sambc"); ++ REGWR(base,0xe0,regs->rege0,"sambc"); ++ REGWR(base,0xe1,regs->rege1,"sambc"); ++ /* set pict-buffer address */ ++ REGWR(base,0x06,regs->reg06,"curr luma base addr_lo"); ++ REGWR(base,0x07,regs->reg07,"curr luma base addr_hi"); ++ REGWR(base,0x08,regs->reg08,"curr cbcr base addr_lo"); ++ REGWR(base,0x09,regs->reg09,"curr cbcr base addr_hi"); ++ REGWR(base,0x0a,regs->reg0a,"ref0 luma base addr_lo"); ++ REGWR(base,0x0b,regs->reg0b,"ref0 luma base addr_hi"); ++ REGWR(base,0x0c,regs->reg0c,"ref1 luma base addr_lo"); ++ REGWR(base,0x0d,regs->reg0d,"ref1 luma base addr_hi"); ++ REGWR(base,0x0e,regs->reg0e,"ref0 cbcr base addr_lo"); ++ REGWR(base,0x0f,regs->reg0f,"ref0 cbcr base addr_hi"); ++ REGWR(base,0x10,regs->reg10,"ref1 cbcr base addr_lo"); ++ REGWR(base,0x11,regs->reg11,"ref1 cbcr base addr_hi"); ++ REGWR(base,0x12,regs->reg12,"recn luma base addr_lo"); ++ REGWR(base,0x13,regs->reg13,"recn luma base addr_hi"); ++ REGWR(base,0x14,regs->reg14,"recn cbcr base addr_lo"); ++ REGWR(base,0x15,regs->reg15,"recn cbcr base addr_hi"); ++ /*!set pict-buffer address */ ++ /* clock gating */ ++ REGWR(base,0x16,regs->reg16,"clock gating"); ++ /* me setting */ ++ REGWR(base,0x20,regs->reg20,"me partition setting"); ++ REGWR(base,0x21,regs->reg21,"value"); ++ REGWR(base,0x22,regs->reg22,"me search range max depth"); ++ REGWR(base,0x23,regs->reg23,"me mvx"); ++ REGWR(base,0x24,regs->reg24,"me mvy"); ++ REGWR(base,0x25,regs->reg25,"FME"); ++ // GN ++ REGWR(base,0x4c,regs->reg4c,"regmfe_s_gn_saddr_lo"); ++ REGWR(base,0x4d,regs->reg4d,"regmfe_s_gn_saddr_hi"); ++ // MBR ++ REGWR(base,0x26,regs->reg26,"MBR: mbbits"); ++ REGWR(base,0x27,regs->reg27,"MBR: frame qstep"); ++ REGWR(base,0x29,regs->reg29,"h264 qp offset"); ++ REGWR(base,0x2a,regs->reg2a,"QP min/max"); ++ REGWR(base,0x6e,regs->reg6e,"QStep min"); ++ REGWR(base,0x6f,regs->reg6f,"QStep max"); ++ // INTRA UPDATE ++ REGWR(base,0x2f,regs->reg2f,"value"); ++ REGWR(base,0x30,regs->reg30,"value"); ++ REGWR(base,0x31,regs->reg31,"value"); ++ REGWR(base,0x32,regs->reg32,"value"); ++ // MDC ++ REGWR(base,0x39,regs->reg39,"value"); ++ // DBF ++ REGWR(base,0x3a,regs->reg3a,"value"); ++ ++ regs->reg73_g_crc_mode = 0xC; ++ regs->reg73_g_debug_tcycle_chk_en = 0x1; ++ regs->reg73_g_debug_tcycle_chk_sel = 0x1; ++ regs->reg73_g_debug_en = 0; // TEST ++ REGWR(base,0x73,regs->reg73,"crc mode"); ++ REGWR(base,0x2c,regs->reg2c,"last zigzag"); ++ // IEAP ++ REGWR(base,0x2b,regs->reg2b,"ieap"); ++ // Cross-format wrong regs setting prevention ++ REGWR(base,0x18,regs->reg18,"jpe encode mode"); ++ REGWR(base,0x1b,regs->reg1b,"mpeg4 field dct"); ++ // regs->reg19 MUST be zero ++ REGWR(base,0x19,0,"0/1:MPEG4 enable/disable p skip mode"); ++ // Prefetch & Low bandwidth mode ++ REGWR(base,0x68,regs->reg68,"prefetch & low bandwidth mode"); ++ // Prefetch ++ REGWR(base,0x6d,regs->reg6d,"prefetch mb idle count"); ++ // Low bandwidth ++ REGWR(base,0x6b,regs->reg6b,"low bandwidth: IMI addr_lo"); ++ REGWR(base,0x6c,regs->reg6c,"low bandwidth: IMI addr_hi"); ++ // IMI DBF ++ REGWR(base,0x4e,regs->reg4e,"DBF: IMI addr_lo"); ++ REGWR(base,0x4f,regs->reg4f,"DBF: IMI addr_hi"); ++ // Reset any StopAndGo or StopAndDrop setting. ++ regs->reg2d_s_txip_sng_mb = 0; ++ REGWR(base,0x2d,regs->reg2d,"reg2d_s_txip_sng_mb=0"); ++ // enable eco item ++ REGWR(base,0x7d,regs->reg7d,"reg7d_s_txip_eco0=1"); ++ /* set output address */ ++ set_outbs_addr(base, regs, regs->obase[0], regs->osize[0]); ++ /* Enable HW */ ++ regs->reg00_g_frame_start_sw = 1; ++ REGWR(base,0x00,regs->reg00,"frame start"); ++ regs->reg00_g_frame_start_sw = 0; // HW is write-one-clear ++ /* write slice header */ ++ put_coded_bits(base, regs, regs->coded, regs->count); ++ return 0; ++} ++ ++static int _enc_poll( ++ mhve_ios* ios) ++{ ++ mfe_asic* asic = (mfe_asic*)ios; ++ mfe_regs* regs = asic->p_regs; ++ void* base = asic->p_base; ++ uint bit = 0; ++ do ++ { ++ while (!(bit = bit_irq(base))) ++ msleep(3); ++ // TODO: handle enc_done/buf_full ++ } ++ while (!(bit&BIT_ENC_DONE)); ++ // feedback ++ regs->reg28 = REGRD(base,0x28,"sum-qstep:lo"); ++ regs->reg29 = REGRD(base,0x29,"sum-qstep:hi"); ++ regs->reg42 = REGRD(base,0x42,"bits size:lo"); ++ regs->reg43 = REGRD(base,0x43,"bits size:hi"); ++ regs->reg76 = REGRD(base,0x76,"cycle count0"); ++ regs->reg77 = REGRD(base,0x77,"cycle count1"); ++ regs->cycles = ((uint)(regs->reg77&0xFF)<<16) + regs->reg76; ++ regs->bitcnt = ((uint)(regs->reg43_s_bsp_bit_cnt_hi)<<16) + regs->reg42_s_bsp_bit_cnt_lo; ++ regs->sumofq = ((uint)(regs->reg29_s_mbr_last_frm_avg_qp_hi)<<16) + regs->reg28_s_mbr_last_frm_avg_qp_lo; ++ regs->mjob.i_tick = (int)(regs->cycles); ++ regs->mjob.i_bits = (int)(regs->bitcnt - regs->delta); ++ clr_irq(base, 0xFF); ++ return bit; ++} ++ ++static int _isr_func( ++ mhve_ios* ios, ++ int irq) ++{ ++ mfe_asic* asic = (mfe_asic*)ios; ++ mfe_regs* regs = asic->p_regs; ++ void* base = asic->p_base; ++ uint bit = bit_irq(base); ++ if (bit&BIT_BUF_FULL) ++ { ++ clr_irq(base, 0xFF); ++ set_outbs_addr(base, regs, regs->obase[1], regs->osize[1]); ++ return 1; ++ } ++ msk_irq(base, 0xFF); ++ // TODO: handle enc_done/buf_full ++ regs->reg28 = REGRD(base,0x28,"avg-qp:lo"); ++ regs->reg29 = REGRD(base,0x29,"avg-qp:hi"); ++ regs->reg42 = REGRD(base,0x42,"bits size:lo"); ++ regs->reg43 = REGRD(base,0x43,"bits size:hi"); ++ regs->reg76 = REGRD(base,0x76,"cycle count0"); ++ regs->reg77 = REGRD(base,0x77,"cycle count1"); ++ regs->cycles = ((uint)(regs->reg77&0xFF)<<16) + regs->reg76; ++ regs->bitcnt = ((uint)(regs->reg43_s_bsp_bit_cnt_hi)<<16) + regs->reg42_s_bsp_bit_cnt_lo; ++ regs->sumofq = ((uint)(regs->reg29_s_mbr_last_frm_avg_qp_hi)<<16) + regs->reg28_s_mbr_last_frm_avg_qp_lo; ++ regs->mjob.i_tick = (int)(regs->cycles); ++ regs->mjob.i_bits = (int)(regs->bitcnt - regs->delta); ++ clr_irq(base, 0xFF); ++ return 0; ++} ++ ++static int _irq_mask( ++ mhve_ios* ios, ++ int msk) ++{ ++ mfe_asic* asic = (mfe_asic*)ios; ++ void* base = asic->p_base; ++ clr_irq(base, 0xFF); ++ msk_irq(base, 0xFF); ++ return 0; ++} +diff --git a/drivers/mstar/mfev5/mfe5/mfe_asic.h b/drivers/mstar/mfev5/mfe5/mfe_asic.h +new file mode 100644 +index 00000000..46ef7eaa +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_asic.h +@@ -0,0 +1,18 @@ ++ ++#ifndef _MFE_ASIC_H_ ++#define _MFE_ASIC_H_ ++ ++#include ++ ++typedef struct mfe_asic mfe_asic; ++ ++struct mfe_asic { ++ mhve_ios mios; ++ void* p_base; ++ mfe_regs* p_regs; ++}; ++ ++#define BIT_ENC_DONE (1<<0) ++#define BIT_BUF_FULL (1<<1) ++ ++#endif/*_MFE_ASIC_H_*/ +diff --git a/drivers/mstar/mfev5/mfe5/mfe_cvbr.c b/drivers/mstar/mfev5/mfe5/mfe_cvbr.c +new file mode 100644 +index 00000000..e0ec73d7 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_cvbr.c +@@ -0,0 +1,660 @@ ++ ++#include ++ ++#include ++ ++#define CVBR_NAME "CVBR" ++#define CVBR_VER_MJR 0 ++#define CVBR_VER_MNR 0 ++#define CVBR_VER_EXT 1 ++ ++#define MFE_VIDEO_MAX_W 1920 ++#define MFE_VIDEO_MAX_H 1088 ++ ++/************************************************************************/ ++/* Configuration */ ++/************************************************************************/ ++#define QS_SHIFT_FACTOR 5 ++ ++/************************************************************************/ ++/* Macros */ ++/************************************************************************/ ++#ifndef MSRC_MAX ++#define MSRC_MAX(a,b) (((a)>(b))?(a):(b)) ++#endif ++#ifndef MSRC_MIN ++#define MSRC_MIN(a,b) (((a)<(b))?(a):(b)) ++#endif ++ ++#define UP_QP_DIFF_LIMIT 3 ++#define LF_QP_DIFF_LIMIT 3 ++ ++#define CONST_QP 0 ++#define CBR 1 ++#define VBR 2 ++#define CONSTRAINED_VBR 3 ++#define STATIC_CBR 4 ++ ++// For Constrained VBR ++#define MAX_GAUGE_SIZE 64 ++ ++typedef struct mfe_cvbr { ++ mfe_rctl rqcx; ++ int i_method; ++ short i_leadqp, i_deltaq; ++ int i_btrate; ++ int i_pixels; ++ int i_tgt_mb; ++ int i_enc_qs; ++ int i_max_qs, i_min_qs; ++ int i_avg_qs; ++ // Derived variables ++ int i_avgbpf; ++ int m_bpf[3]; // I, P, B ++ /* coded frame counter */ ++ int i_frm_nr; ++ int64 i_totbit; ++ /* integral part of frame-rate */ ++ int n_fmrate, d_fmrate; ++ int i_fmrate; ++ int i_fps; ++ int i_maxbps; ++ int b_fixfps; ++ /* last-frame status */ ++ int i_last_avg_qs; ++ int i_last_frm_bs; ++ int i_last_tgt_bs; ++ /* bitrate usage compensation */ ++ int i_buf_fullness; // Rate control buffer ++ int i_tgt_fullness; ++ int i_deputy_cnt, i_deputy_min; ++ /* variable bitrate */ ++ int i_lt_qs64; ++ // model parameters ++ int i_tgt_bs; // target number of bits of current frame ++ /* only for Constrained VBR */ ++ int i_max_offset; ++ int i_gauge_bgt[MAX_GAUGE_SIZE]; ++ int i_gauge_cnt; ++ int i_gauge_idx; ++ int i_gauge_bps; ++ int i_frozen; ++ int i_thr_qp_frameskip; ++ int i_frameskip; // original MFE-RC: pic_done's output ++} mfe_cvbr; ++ ++#define MFE_ASSERT(p) ++ ++// Spec limitation is [1,51] ++#define MAX_QP (48) ++#define MIN_QP ( 5) ++#define THR_QP_FRAMESKIP (40) ++ ++//! How many seconds of frames are responsible for compensation of bitrate usage. ++#define DEPUTY_SECOND_CBR 1 ++#define DEPUTY_SECOND_CVBR 3 ++#define DEPUTY_SECOND_VBR 10 ++#define DEPUTY_FACTOR_MIN 10 ++ ++//! Default I-frame weighting over inter-frame ++#define IFRAME_WEIGHT 8 ++#define PFRAME_WEIGHT 4 ++#define BFRAME_WEIGHT 3 ++ ++static int cvbr_seq_sync(rqct_ops*); ++static int cvbr_seq_done(rqct_ops*); ++static int cvbr_seq_conf(rqct_ops*); ++static int cvbr_enc_conf(rqct_ops*, mhve_job*); ++static int cvbr_enc_done(rqct_ops*, mhve_job*); ++ ++static void _cvbrfree(rqct_ops* rqct) { MEM_FREE(rqct); } ++ ++void* cvbr_allocate(void) ++{ ++ rqct_ops* rqct; ++ ++ if (NULL != (rqct = MEM_ALLC(sizeof(mfe_cvbr)))) ++ { ++ mfe_rctl* rqcx = (mfe_rctl*)rqcx; ++ MEM_COPY(rqct->name, CVBR_NAME, 5); ++ rqct->seq_sync = cvbr_seq_sync; ++ rqct->seq_done = cvbr_seq_done; ++ rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->seq_conf = cvbr_seq_conf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = cvbr_enc_conf; ++ rqct->enc_done = cvbr_enc_done; ++ rqct->release = _cvbrfree; ++ ++ rqcx->attr.i_method = RQCT_METHOD_CQP; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = 3; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.i_btrate = 0; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->i_config = 0; ++ rqcx->i_pcount = 0; ++ rqcx->i_period = 0; ++ } ++ ++ return rqct; ++} ++ ++char* cvbr_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d-%02d:utopian version.",CVBR_NAME,CVBR_VER_MJR,CVBR_VER_MNR,CVBR_VER_EXT); ++ return line; ++} ++ ++static int compute_qs(mfe_cvbr* cvbr); ++static int qp2qs(mfe_cvbr* cvbr, int QP); ++static int qs2qp(mfe_cvbr* cvbr, int qsx32); ++ ++static int cvbr_seq_done(rqct_ops* rqct) ++{ ++ return 0; ++} ++ ++static int cvbr_seq_sync(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ rqcx->i_pcount = 0; ++ return 0; ++} ++ ++/** ++ * fps=14.985 = 15000/1001 ++ * fps=23.976 = 24000/1001 ++ * fps=29.970 = 30000/1001 ++ */ ++static int cvbr_seq_conf(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_cvbr* cvbr = (mfe_cvbr*)rqcx; ++ int i; ++ ++ printk("%s\n",cvbr_describe()); ++ ++ cvbr->i_method = (int)rqcx->attr.i_method; ++ cvbr->i_leadqp = rqcx->attr.i_leadqp; ++ cvbr->i_deltaq = rqcx->attr.i_deltaq; ++ cvbr->i_btrate = rqcx->attr.i_btrate; ++ cvbr->i_pixels = (int)rqcx->attr.i_pict_w * (int)rqcx->attr.i_pict_h; ++ cvbr->n_fmrate = rqcx->attr.n_fmrate; ++ cvbr->d_fmrate = rqcx->attr.d_fmrate; ++ cvbr->i_fmrate = (int)rqcx->attr.n_fmrate / (int)rqcx->attr.d_fmrate; ++ cvbr->i_maxbps = 0; ++ cvbr->b_fixfps = 1; ++ ++ rqcx->i_period = rqcx->attr.i_period; ++ ++ // more bitrate checking ++ if (cvbr->i_method == CONSTRAINED_VBR) ++ { ++ if (cvbr->i_maxbps == 0) ++ cvbr->i_maxbps = (int)((cvbr->i_btrate*14)/10); ++ ++ cvbr->i_max_offset = (int)div_s64((int64)(cvbr->i_maxbps-cvbr->i_btrate)*cvbr->d_fmrate,cvbr->n_fmrate); ++ ++ if (!(rqcx->i_config&RCTL_CFG_MB_DQP)) ++ cvbr->i_max_offset = (cvbr->i_max_offset) >> 2; ++ } ++ else ++ cvbr->i_maxbps = 0; // Don't care ++ ++ cvbr->i_avgbpf = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate,cvbr->n_fmrate); ++ ++ if (rqcx->i_period > 0) ++ { ++ int length = rqcx->i_period; ++ int weight = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_period-1); ++ cvbr->m_bpf[0] = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate*IFRAME_WEIGHT*length,weight*cvbr->n_fmrate); ++ cvbr->m_bpf[1] = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate*PFRAME_WEIGHT*length,weight*cvbr->n_fmrate); ++ cvbr->m_bpf[2] = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate*BFRAME_WEIGHT*length,weight*cvbr->n_fmrate); ++ } ++ else ++ { ++ cvbr->m_bpf[0] = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate*IFRAME_WEIGHT,PFRAME_WEIGHT*cvbr->n_fmrate); ++ cvbr->m_bpf[1] = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate,cvbr->n_fmrate); ++ } ++ ++ // QP, QStep: min, max ++ cvbr->i_min_qs = qp2qs(cvbr,MIN_QP)-1; ++ cvbr->i_max_qs = qp2qs(cvbr,MAX_QP); ++ cvbr->i_totbit = 0; ++ rqcx->i_pcount = rqcx->i_period; ++ // Bitrate usage monitoring ++ cvbr->i_deputy_min = (cvbr->n_fmrate*DEPUTY_SECOND_CBR)/cvbr->d_fmrate; ++ cvbr->i_tgt_fullness = cvbr->i_btrate >> 1; ++ cvbr->i_buf_fullness = cvbr->i_tgt_fullness; ++ switch (cvbr->i_method) ++ { ++ case RQCT_METHOD_VBR: ++ cvbr->i_deputy_cnt = (cvbr->n_fmrate*DEPUTY_SECOND_VBR)/cvbr->d_fmrate; ++ break; ++ case CONSTRAINED_VBR: ++ cvbr->i_deputy_cnt = (cvbr->n_fmrate*DEPUTY_SECOND_CVBR)/cvbr->d_fmrate; ++ cvbr->i_gauge_bgt[0] = cvbr->m_bpf[0]; ++ for (i = 1; i < MAX_GAUGE_SIZE; i++) ++ cvbr->i_gauge_bgt[i] = cvbr->m_bpf[1]; ++ cvbr->i_gauge_cnt = cvbr->i_fmrate; ++ cvbr->i_gauge_idx = 0; ++ cvbr->i_gauge_bps = (int)div_s64((int64)cvbr->i_btrate*cvbr->d_fmrate*cvbr->i_gauge_cnt,cvbr->n_fmrate); ++ break; ++ case RQCT_METHOD_CBR: ++ default: ++ cvbr->i_deputy_cnt = (int)div_s64((int64)cvbr->n_fmrate*DEPUTY_SECOND_CBR,cvbr->d_fmrate); ++ break; ++ } ++ cvbr->i_thr_qp_frameskip = THR_QP_FRAMESKIP; ++ cvbr->i_frm_nr = 0; ++ cvbr->i_last_avg_qs = cvbr->i_last_frm_bs = 0; ++ cvbr->i_lt_qs64 = 0; ++ ++ return 0; ++} ++ ++static int cvbr_enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ mfe_cvbr* cvbr = (mfe_cvbr*)rqcx; ++ int deputy_cnt = 0; ++ int delta = 0; ++ ++ // Target frame bitcount ++ if (cvbr->i_frm_nr > 0) ++ { ++ // 1. Determine the number of future frame to compensate for current bitrate mismatch. ++ if (cvbr->i_frm_nr > cvbr->i_deputy_cnt*DEPUTY_FACTOR_MIN) ++ deputy_cnt = cvbr->i_deputy_cnt; ++ else if (cvbr->i_frm_nr < cvbr->i_deputy_min) ++ deputy_cnt = cvbr->i_deputy_min; ++ else ++ { ++ int fact_n = cvbr->i_deputy_cnt - cvbr->i_deputy_min; ++ int fact_d = cvbr->i_deputy_cnt * DEPUTY_FACTOR_MIN - cvbr->i_deputy_min; ++ deputy_cnt = cvbr->i_deputy_min + (cvbr->i_frm_nr - cvbr->i_deputy_min) * fact_n / fact_d; ++ } ++ // 2. Calculate the bitcount that this frame should be compensate for. ++ if (cvbr->i_method == RQCT_METHOD_CBR) ++ { ++ delta = (int)div_s64((int64)(cvbr->i_buf_fullness-cvbr->i_tgt_fullness)*cvbr->d_fmrate,cvbr->n_fmrate); ++ } ++ else if (cvbr->i_method == CONSTRAINED_VBR) ++ { ++ delta = (cvbr->i_buf_fullness - cvbr->i_tgt_fullness) / deputy_cnt; ++ if (delta < -cvbr->i_max_offset) ++ delta = -cvbr->i_max_offset; ++ } ++ else if (cvbr->i_method == RQCT_METHOD_VBR) ++ { ++ delta = (cvbr->i_buf_fullness - cvbr->i_tgt_fullness) / deputy_cnt; ++ if (delta > 0 && (cvbr->i_last_avg_qs*64) > cvbr->i_lt_qs64) ++ delta = delta>>1; // Make it more variable bitrate to allow better quality ++ } ++ // 3. Finally, calculate the target bitcount. ++ cvbr->i_tgt_bs = cvbr->m_bpf[rqct->i_pictyp] - delta; ++ ++ if (cvbr->i_tgt_bs <=(cvbr->i_avgbpf >> 3)) ++ cvbr->i_tgt_bs = (cvbr->i_avgbpf >> 3); // Target bitcount must>0 for ComputeFrameQP() ++ } ++ else ++ { ++ cvbr->i_tgt_bs = cvbr->m_bpf[0]; // Must be I-frame ++ } ++ /* Return initial frame QP */ ++ cvbr->i_enc_qs = compute_qs(cvbr); ++ ++ cvbr->i_last_avg_qs = 0; ++ cvbr->i_last_frm_bs = 0; ++ ++ if (cvbr->i_method != RQCT_METHOD_CQP) ++ rqcx->i_config |= RCTL_CFG_MB_DQP; ++ ++ cvbr->i_tgt_mb = (int)div_s64((int64)cvbr->i_tgt_bs*256,cvbr->i_pixels); ++ ++ if (cvbr->i_tgt_mb < 1) ++ cvbr->i_tgt_mb = 1; ++ ++ rqct->i_enc_qp = qs2qp(cvbr, cvbr->i_enc_qs); ++ ++ mrqc_roi_draw(rqct, mjob); ++ ++ regs->reg00_g_mbr_en = !rqcx->attr.b_dqmstat && (cvbr->i_method!=RQCT_METHOD_CQP); ++ regs->reg26_s_mbr_pqp_dlimit = LF_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = UP_QP_DIFF_LIMIT; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = cvbr->i_enc_qs; ++ regs->reg26_s_mbr_tmb_bits = cvbr->i_tgt_mb; ++ regs->reg2a_s_mbr_qp_min = MIN_QP; ++ regs->reg2a_s_mbr_qp_max = MAX_QP; ++ regs->reg6e_s_mbr_qstep_min = cvbr->i_min_qs; ++ regs->reg6f_s_mbr_qstep_max = cvbr->i_max_qs; ++ ++ return 0; ++} ++ ++static int cvbr_enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_cvbr* cvbr = (mfe_cvbr*)rqcx; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ int frameskip = 0; ++ int mbs = (cvbr->i_pixels>>8); ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ cvbr->i_avg_qs = regs->sumofq / (mbs-1); ++ ++ rqct->i_enc_bs += rqct->i_bitcnt/8; ++ rqct->i_enc_nr++; ++ ++ // update counter ++ cvbr->i_totbit += rqct->i_bitcnt; ++ cvbr->i_frm_nr++; ++ cvbr->i_buf_fullness += rqct->i_bitcnt; ++ cvbr->i_last_frm_bs = rqct->i_bitcnt; ++ cvbr->i_last_tgt_bs = cvbr->i_tgt_bs; ++#if defined(MMFE_RCTL_PATCH) ++ if (cvbr->i_avg_qs <(cvbr->i_enc_qs/2)) ++ cvbr->i_avg_qs = cvbr->i_enc_qs; ++ if (cvbr->i_avg_qs > cvbr->i_max_qs) ++ cvbr->i_avg_qs = cvbr->i_max_qs; ++#endif ++ cvbr->i_last_avg_qs = cvbr->i_avg_qs; ++ // Variable bitrate ++ if (cvbr->i_method == RQCT_METHOD_VBR) ++ cvbr->i_lt_qs64 += ((cvbr->i_last_avg_qs*64)-cvbr->i_lt_qs64) / cvbr->i_frm_nr; ++ else if (cvbr->i_method == CONSTRAINED_VBR) ++ { ++ if (cvbr->i_frm_nr == 1) ++ cvbr->i_lt_qs64 = cvbr->i_last_avg_qs*64; ++ else ++ cvbr->i_lt_qs64 = (cvbr->i_lt_qs64*(cvbr->i_deputy_cnt-1) + (cvbr->i_last_avg_qs*64)) / cvbr->i_deputy_cnt; ++ } ++ ++ if (cvbr->i_method == CONSTRAINED_VBR) ++ { ++ cvbr->i_gauge_bps -= cvbr->i_gauge_bgt[cvbr->i_gauge_idx]; ++ cvbr->i_gauge_bps += rqct->i_bitcnt; ++ cvbr->i_gauge_bgt[cvbr->i_gauge_idx] = rqct->i_bitcnt; ++ cvbr->i_gauge_idx++; ++ if (cvbr->i_gauge_idx == cvbr->i_gauge_cnt) ++ cvbr->i_gauge_idx = 0; ++ } ++ // update buffer status ++ cvbr->i_buf_fullness -= cvbr->i_avgbpf; ++ // check if next skipped frame(s) needed ++ if (!cvbr->b_fixfps) ++ { ++ if (cvbr->i_method == CONSTRAINED_VBR || cvbr->i_method == RQCT_METHOD_VBR) ++ { ++ if (cvbr->i_lt_qs64 > (qp2qs(cvbr,cvbr->i_thr_qp_frameskip)*64) && ++ cvbr->i_last_frm_bs >= (cvbr->i_last_tgt_bs<<1)) ++ { ++ frameskip = (int)((cvbr->i_last_frm_bs - cvbr->i_last_tgt_bs) / cvbr->i_avgbpf - 1); ++ if (frameskip < 0) ++ frameskip = 0; ++ else if (frameskip > cvbr->i_frozen) ++ frameskip = cvbr->i_frozen; ++ } ++ } ++ else if (cvbr->i_method == RQCT_METHOD_CBR) ++ { ++ if (cvbr->i_last_avg_qs > qp2qs(cvbr, cvbr->i_thr_qp_frameskip)) ++ { // Actual fullness is updated after encoding dummy-P frame ++ int fullness = cvbr->i_buf_fullness; ++ while (fullness > cvbr->i_tgt_fullness) ++ { ++ fullness = (int)(fullness - cvbr->i_avgbpf); ++ frameskip++; ++ } ++ } ++ } ++ cvbr->i_frameskip = frameskip; ++ } ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d",\ ++ rqct->name,rqct->i_enc_nr%10000,rqct->i_pictyp==RQCT_PICTYP_I?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt); ++ return 0; ++} ++ ++#define SMOOTH_PERIOD 1 ++#define INIT_QP_FACTOR 720 ++#define MIN_INIT_QP 1 ++#define MAX_INIT_QP 96 ++ ++/* Return target QPStep */ ++static int compute_qs(mfe_cvbr* cvbr) ++{ ++ mfe_rctl* rqcx = &cvbr->rqcx; ++ rqct_ops* rqct = &rqcx->rqct; ++ int newqs = 0; ++ int64 buf_rest; ++ int buf_rest_pic; ++ int frames_left; ++ int adjust; ++ int bitrate = cvbr->i_btrate; ++ int fps_den = cvbr->d_fmrate; ++ int fps_num = cvbr->n_fmrate; ++ int mb_numb = cvbr->i_pixels>>8; ++ int frm_cnt = cvbr->i_frm_nr; ++ ++ // For the very first frame, guess one qp! ++ if (cvbr->i_frm_nr == 0) ++ { ++ int bpMBK, newqp; ++ if (cvbr->i_method == RQCT_METHOD_CQP) ++ { ++ newqp = cvbr->i_leadqp; ++ newqs = qp2qs(cvbr, newqp); // So that frame qp will be exactly cvbr->i_qp ++ } ++ else ++ { ++ bpMBK = (int)div_s64((int64)bitrate*fps_den,mb_numb*fps_num)+1; ++ newqp = INIT_QP_FACTOR / bpMBK; ++ ++ if (newqp < MIN_INIT_QP) ++ newqp = MIN_INIT_QP; ++ if (newqp > MAX_INIT_QP) ++ newqp = MAX_INIT_QP; ++ newqs = newqp << QS_SHIFT_FACTOR; ++ } ++ ++ cvbr->i_frozen = newqp >> 1; ++ ++ if (cvbr->i_frozen > 15) ++ cvbr->i_frozen = 15; ++ ++ return newqs; ++ } ++ ++ if (cvbr->i_method == RQCT_METHOD_CQP) ++ return qp2qs(cvbr, rqct->i_enc_qp); ++ ++ if (cvbr->i_method == RQCT_METHOD_CBR) ++ { ++ int dqp; ++ buf_rest = div_s64((int64)frm_cnt*fps_den*bitrate,fps_num); ++ buf_rest+= (SMOOTH_PERIOD*cvbr->i_btrate) - cvbr->i_totbit; ++ newqs = cvbr->i_last_avg_qs; ++ frames_left = (SMOOTH_PERIOD * cvbr->n_fmrate) / cvbr->d_fmrate; ++ buf_rest_pic = (int)div_s64(buf_rest,frames_left); ++ dqp = cvbr->i_last_avg_qs/8; ++ ++ if (cvbr->i_last_frm_bs > (buf_rest_pic*9)>>3) ++ newqs = cvbr->i_last_avg_qs + dqp; ++ else if (cvbr->i_last_frm_bs < (buf_rest_pic*7)>>3) ++ newqs = cvbr->i_last_avg_qs - dqp; ++ } ++ else if (cvbr->i_method == CONSTRAINED_VBR) ++ { ++ int lo_qs, hi_qs; ++ adjust = cvbr->i_lt_qs64>>2; ++ lo_qs = (cvbr->i_lt_qs64 - adjust) >> 6; ++ hi_qs = (cvbr->i_lt_qs64 + adjust) >> 6; ++ if (rqcx->i_period > 1 && IS_IPIC(rqct->i_pictyp)) ++ { ++ newqs = cvbr->i_last_avg_qs; ++ if (cvbr->i_gauge_bps < cvbr->i_btrate) ++ newqs = newqs-(1<i_lt_qs64 * div_s64(cvbr->i_totbit,cvbr->i_frm_nr), cvbr->i_tgt_bs) ; ++ //MFE_ASSERT((tmp >> 6) < (1<<31)); ++ newqs = (int)(div_s64((int64)cvbr->i_lt_qs64 * div_s64(cvbr->i_totbit,cvbr->i_frm_nr),cvbr->i_tgt_bs)>>6) ; ++ if (cvbr->i_last_frm_bs>cvbr->i_last_tgt_bs) ++ { ++ adjust = ((cvbr->i_last_frm_bs-cvbr->i_last_tgt_bs)/cvbr->i_max_offset) + (1< (3<i_last_avg_qs*64) > cvbr->i_lt_qs64) ++ { // Danger! Make it more aggressive ++ hi_qs = cvbr->i_last_avg_qs + adjust; ++ newqs = cvbr->i_last_avg_qs + adjust; ++ } ++ else ++ { ++ hi_qs += adjust; ++ newqs += adjust; ++ } ++ } ++ else if (cvbr->i_gauge_bps > cvbr->i_btrate) ++ { ++ if (cvbr->i_last_avg_qs > newqs) ++ newqs = cvbr->i_last_avg_qs; ++ if (cvbr->i_lt_qs64 > (newqs*64)) ++ newqs = cvbr->i_lt_qs64/64; ++ } ++ else ++ { ++ if ((newqs<<6) >= cvbr->i_lt_qs64) ++ newqs = (cvbr->i_lt_qs64/64)-1; ++ if (cvbr->i_tgt_fullness>cvbr->i_buf_fullness) ++ { ++ adjust = (cvbr->i_tgt_fullness - cvbr->i_buf_fullness) / (int)cvbr->i_btrate; ++ newqs -= adjust; ++ } ++ } ++ } ++ newqs = MSRC_MIN(hi_qs, newqs); ++ newqs = MSRC_MAX(lo_qs, newqs); ++ } ++ else if (cvbr->i_method == RQCT_METHOD_VBR) ++ { ++ int lo_qs, hi_qs; ++ if (rqcx->i_period > 1 && IS_IPIC(rqct->i_pictyp)) ++ { ++ newqs = cvbr->i_last_avg_qs; ++ if ((cvbr->i_last_avg_qs*64) > cvbr->i_lt_qs64) ++ newqs = newqs - (1<i_frm_nr >= cvbr->i_fmrate || rqcx->i_period == 1) ++ { ++ //int64 tmp = div_s64((int64)cvbr->i_lt_qs64*div_s64(cvbr->i_totbit,cvbr->i_frm_nr),cvbr->i_avgbpf); ++ //MFE_ASSERT((tmp >> 6) < (1<<31)); ++ adj_ltq = (int)(div_s64((int64)cvbr->i_lt_qs64*div_s64(cvbr->i_totbit,cvbr->i_frm_nr),cvbr->i_avgbpf)>>6); ++ } ++ else ++ { ++ adj_ltq = cvbr->i_lt_qs64/64; // Wait for stabilization ++ } ++ MFE_ASSERT(cvbr->i_tgt_bs>0); ++ newqs = (adj_ltq * cvbr->i_avgbpf) / cvbr->i_tgt_bs; ++ ++ adjust = MSRC_MAX((2<>2); ++ lo_qs = adj_ltq - adjust; ++ hi_qs = adj_ltq + adjust; ++ ++ if (cvbr->i_last_frm_bs > cvbr->i_last_tgt_bs) ++ { ++ adjust = (int)(cvbr->i_last_frm_bs/cvbr->i_last_tgt_bs); ++ if (adjust > 2) ++ adjust = 2; ++ hi_qs += adjust; ++ } ++ ++ if (cvbr->i_avgbpf > cvbr->i_tgt_bs) ++ newqs = MSRC_MIN(hi_qs,newqs); ++ else ++ newqs = MSRC_MAX(lo_qs,newqs); ++ } ++ } ++ return newqs; ++} ++ ++static int qp2qs(mfe_cvbr* cvbr, int qp) ++{ ++ int i; ++ int qs; ++ static const int QP2QSTEP[6] = { 20, 22, 26, 28, 32, 36 }; ++ ++ qs = QP2QSTEP[qp%6]; ++ ++ for (i = 0; i < (qp/6); i++) ++ qs *= 2; ++ ++ return qs; ++} ++ ++static int qs2qp(mfe_cvbr* cvbr, int qsx32) ++{ ++ int q_per = 0, q_rem = 0; ++ ++ if (qsx32 <= cvbr->i_min_qs) ++ return MIN_QP; ++ else if (qsx32 > cvbr->i_max_qs) ++ return MAX_QP; ++ ++ while (qsx32 > qp2qs(cvbr, 5)) ++ { ++ qsx32 >>= 1; ++ q_per += 1; ++ } ++ ++ if (qsx32 <= 21) ++ { ++ qsx32 = 20; ++ q_rem = 0; ++ } ++ else if (qsx32 <= 24) ++ { ++ qsx32 = 22; ++ q_rem = 1; ++ } ++ else if (qsx32 <= 27) ++ { ++ qsx32 = 26; ++ q_rem = 2; ++ } ++ else if (qsx32 <= 30) ++ { ++ qsx32 = 28; ++ q_rem = 3; ++ } ++ else if (qsx32 <= 34) ++ { ++ qsx32 = 32; ++ q_rem = 4; ++ } ++ else ++ { ++ qsx32 = 36; ++ q_rem = 5; ++ } ++ ++ return (q_per*6 + q_rem); ++} +diff --git a/drivers/mstar/mfev5/mfe5/mfe_defs.h b/drivers/mstar/mfev5/mfe5/mfe_defs.h +new file mode 100644 +index 00000000..15fd1768 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_defs.h +@@ -0,0 +1,39 @@ ++ ++#ifndef _MFE_DEFS_H_ ++#define _MFE_DEFS_H_ ++ ++#include ++#include ++ ++typedef unsigned char uchar; ++typedef unsigned short ushort; ++typedef unsigned int uint; ++ ++typedef unsigned char uint8; ++typedef unsigned short uint16; ++typedef unsigned int uint32; ++typedef unsigned long long uint64; ++typedef signed char int8; ++typedef signed short int16; ++typedef signed int int32; ++typedef signed long long int64; ++ ++#define MST_ASSERT(p) ++ ++/* mem operators (allc/free) */ ++#define MEM_ALLC(l) kzalloc(l,GFP_KERNEL) ++#define MEM_FREE(p) kfree(p) ++#define MEM_SETV(p,v,l) memset(p,v,l) ++#define MEM_COPY(p,q,l) memcpy(p,q,l) ++ ++//#define MMFE_PRINT(fmt,args...) printk("[MMFE]" fmt, ##args) ++#ifndef MMFE_PRINT ++#define MMFE_PRINT(fmt,args...) ++#endif ++ ++//#define MMFE_REGS_TRACE ++#define MMFE_RCTL_PATCH ++#define MMFE_IMI_LBW_ADDR 0x00000 /* From 0x00000 to 0x0FFFF */ ++#define MMFE_IMI_DBF_ADDR 0x10000 /* From 0x10000 to 0x13FFF */ ++ ++#endif/*_MFE_DEFS_H_*/ +diff --git a/drivers/mstar/mfev5/mfe5/mfe_h264.c b/drivers/mstar/mfev5/mfe5/mfe_h264.c +new file mode 100644 +index 00000000..b4386819 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_h264.c +@@ -0,0 +1,322 @@ ++ ++#include ++#include ++ ++static void write_ebsp(bs_t* bs, uchar byte) ++{ ++ if (bs->ebsp_zeros == 2 && byte < 4) ++ { ++ *bs->curr++ = 0x03; ++ bs->ebsp_zeros = 0; ++ bs->bits_pos += 8; ++ } ++ if (byte == 0) ++ bs->ebsp_zeros++; ++ *bs->curr++ = byte; ++} ++ ++int avc_reset(bs_t* bs, uchar* buff, int len) ++{ ++ bs->bits_pos = 0; ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ bs->curr = bs->buffer = buff; ++ bs->length = len; ++ return 0; ++} ++ ++int avc_flush(bs_t* bs) ++{ ++ while (bs->left_count < 16) ++ { ++ write_ebsp(bs, (uchar)(bs->code_bits>>8)); ++ bs->left_count += 8; ++ bs->code_bits <<= 8; ++ } ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ return bs->bits_pos; ++} ++ ++int avc_count(bs_t* bs) ++{ ++ return bs->bits_pos; ++} ++ ++static int bs_write(bs_t* bs, int len, uint bit) ++{ ++ if (bs->left_count > len) ++ { ++ bs->left_count -= len; ++ bs->code_bits += bit << bs->left_count; ++ } ++ else ++ { ++ int left = (16 - len + bs->left_count); ++ uint pattern = (bs->code_bits << 16) + (bit << left); ++ bs->left_count = left; ++ bs->code_bits = pattern & 0xFFFF; ++ write_ebsp(bs, (uchar)(pattern>>24)); ++ write_ebsp(bs, (uchar)(pattern>>16)); ++ } ++ bs->bits_pos += len; ++ return len; ++} ++ ++static int bs_align(bs_t* bs, int bit) ++{ ++ int size = bs->left_count&0x7; ++ uint code = bit?(1< 0) ++ bs_write(bs, size, code); ++ return size; ++} ++ ++static const uchar ue_code_lengths[256] = { ++ 1, 1, 3, 3, 5, 5, 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, ++ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, ++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, ++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++}; ++ ++static int bs_write_ue(bs_t* bs, int val) ++{ ++ return bs_write(bs, (int)ue_code_lengths[val+1], (uint)val+1); ++} ++ ++static int bs_write_se(bs_t* bs, int val) ++{ ++ int size = 0; ++ int tmp = 1 - 2*val; ++ if (tmp < 0) tmp = 2*val; ++ val = tmp; ++ if (tmp >= 256) ++ { ++ size = 16; ++ tmp >>= 8; ++ } ++ size += ue_code_lengths[tmp]; ++ return bs_write(bs, size, (uint)val); ++} ++ ++static int bs_write_u1(bs_t* bs, int val) ++{ ++ return bs_write(bs, 1, (uint)(val!=0)); ++} ++ ++static int bs_trail(bs_t* bs) ++{ ++ int len; ++ ++ bs->left_count--; ++ bs->code_bits += 1 << bs->left_count; ++ ++ if (!bs->left_count) ++ { ++ write_ebsp(bs, (uchar)(bs->code_bits>>8)); ++ write_ebsp(bs, (uchar)(bs->code_bits)); ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ } ++ bs->bits_pos += 8; ++ bs->bits_pos &= ~0x7; ++ ++ len = 1 + (bs->left_count&0x7); ++ ++ bs->left_count &= ~7; ++ ++ return len; ++} ++ ++int avc_write_nal(bs_t* bs, uchar nal) ++{ ++ *bs->curr++ = 0; ++ *bs->curr++ = 0; ++ *bs->curr++ = 0; ++ *bs->curr++ = 1; ++ *bs->curr++ = nal; ++ bs->bits_pos += 8*5; ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ ++ return 8*5; ++} ++ ++static int vui_write_param(bs_t* bs, vui_t* vui); ++ ++int avc_write_sps(bs_t* bs, sps_t* sps) ++{ ++ int bit_pos = avc_count(bs); ++ bs_write(bs, 8, (uint)sps->i_profile_idc); ++ bs_write_u1(bs, sps->b_constraint_set0); ++ bs_write_u1(bs, sps->b_constraint_set1); ++ bs_write_u1(bs, sps->b_constraint_set2); ++ bs_write_u1(bs, sps->b_constraint_set3); ++ bs_write(bs, 4, 0); ++ ++ bs_write(bs, 8, (uint)sps->i_level_idc); ++ bs_write_ue(bs, sps->i_sps_id); ++ /* not support high profile ++ if (sps->i_profile_idc > PROFILE_HIGH) ++ { ++ chroma_format_idc ++ .... ++ } ++ */ ++ bs_write_ue(bs, sps->i_log2_max_frame_num - 4); ++ bs_write_ue(bs, sps->i_poc_type); ++ if (sps->i_poc_type == 0) { ++ bs_write_ue(bs, sps->i_log2_max_poc_lsb - 4); ++ } ++ /* not support poc_type == 1 ++ else if (sps->i_poc_type == 1) ++ { ++ .... ++ } ++ */ ++ bs_write_ue(bs, sps->i_num_ref_frames); ++ bs_write_u1(bs, sps->b_gaps_in_frame_num_value_allow); ++ bs_write_ue(bs, sps->i_mb_w - 1); ++ bs_write_ue(bs, sps->i_mb_h - 1); ++ bs_write_u1(bs, 1/*b_frame_mbs_only*/); ++ /* only support frame_mbs */ ++ bs_write_u1(bs, sps->b_direct8x8_inference); ++ bs_write_u1(bs, sps->b_crop); ++ if (sps->b_crop) ++ { ++ bs_write_ue(bs, sps->crop.i_left); ++ bs_write_ue(bs, sps->crop.i_right); ++ bs_write_ue(bs, sps->crop.i_top); ++ bs_write_ue(bs, sps->crop.i_bottom); ++ } ++ bs_write_u1(bs, sps->b_vui_param_pres); ++ if (sps->b_vui_param_pres) ++ vui_write_param(bs, &sps->vui); ++ bs_trail(bs); ++ ++ return bs->bits_pos - bit_pos; ++} ++ ++static int vui_write_param(bs_t* bs, vui_t* vui) ++{ ++ int bit_pos = avc_count(bs); ++ bs_write_u1(bs, 0/* aspect_ratio_info_present_flag */); ++ bs_write_u1(bs, 0/* overscan_info_present_flag */); ++ bs_write_u1(bs, vui->b_video_signal_pres); ++ if (vui->b_video_signal_pres) ++ { ++ bs_write(bs, 3, vui->i_video_format); ++ bs_write_u1(bs, vui->b_video_full_range); ++ bs_write_u1(bs, vui->b_colour_desc_pres); ++ if (vui->b_colour_desc_pres) ++ { ++ bs_write(bs, 8, vui->i_colour_primaries); ++ bs_write(bs, 8, vui->i_transf_character); ++ bs_write(bs, 8, vui->i_matrix_coeffs); ++ } ++ } ++ bs_write_u1(bs, 0/* chroma_loc_info_present_flag */); ++ bs_write_u1(bs, 0/* timing_info_present_flag */); ++ bs_write_u1(bs, 0/* nal_hrd_parameters_present_flag */); ++ bs_write_u1(bs, 0/* vcl_hrd_parameters_present_flag */); ++ bs_write_u1(bs, 0/* pic_struct_present_flag */); ++ bs_write_u1(bs, 0/* bitstream_restriction_flag */); ++ return bs->bits_pos - bit_pos; ++} ++ ++int avc_write_pps(bs_t* bs, pps_t* pps) ++{ ++ int bit_pos = avc_count(bs); ++ bs_write_ue(bs, pps->i_pps_id); ++ bs_write_ue(bs, pps->sps->i_sps_id); ++ bs_write_u1(bs, pps->b_cabac); ++ bs_write_u1(bs, 0/*b_bottom_field_pic_order*/); ++ bs_write_ue(bs, 0/*i_num_slice_groups - 1*/); ++ bs_write_ue(bs, pps->i_num_ref_idx_l0_default_active - 1); ++ bs_write_ue(bs, pps->i_num_ref_idx_l1_default_active - 1); ++ /* not support weighted pred */ ++ bs_write_u1(bs, 0/*b_weighted_pred*/); ++ bs_write(bs, 2, 0/*b_weighted_bipred*/); ++ bs_write_se(bs, pps->i_pic_init_qp - 26); ++ bs_write_se(bs, pps->i_pic_init_qs - 26); ++ bs_write_se(bs, pps->i_cqp_idx_offset); ++ bs_write_u1(bs, pps->b_deblocking_filter_control); ++ bs_write_u1(bs, pps->b_constrained_intra_pred); ++ bs_write_u1(bs, pps->b_redundant_pic_cnt); ++ /* not support transform8x8/q-matrix */ ++ bs_trail(bs); ++ ++ return bs->bits_pos - bit_pos; ++} ++ ++int avc_write_slice_header(bs_t* bs, slice_t* sh) ++{ ++ bs_write_ue(bs, sh->i_first_mb); ++ bs_write_ue(bs, sh->i_type); ++ bs_write_ue(bs, sh->pps->i_pps_id); ++ bs_write(bs, sh->sps->i_log2_max_frame_num, (uint)sh->i_frame_num & ((1 << sh->sps->i_log2_max_frame_num) - 1)); ++ ++ if (sh->b_idr_pic) ++ bs_write_ue(bs, sh->i_idr_pic_id); ++ if (sh->sps->i_poc_type == 0) ++ bs_write(bs, sh->sps->i_log2_max_poc_lsb, (uint)sh->i_poc & ((1 << sh->sps->i_log2_max_poc_lsb) - 1)); ++ if (sh->pps->b_redundant_pic_cnt) ++ bs_write_ue(bs, sh->i_redundant_pic_cnt); ++ if (sh->i_type == SLICE_B) ++ bs_write_u1(bs, sh->b_direct_spatial_mv_pred); ++ if (sh->i_type == SLICE_P || sh->i_type == SLICE_B) ++ { ++ bs_write_u1(bs, sh->b_num_ref_idx_override); ++ if (sh->b_num_ref_idx_override) ++ { ++ bs_write_ue(bs, sh->i_num_ref_idx_l0_active - 1); ++ if (sh->i_type == SLICE_B) ++ bs_write_ue(bs, sh->i_num_ref_idx_l1_active - 1); ++ } ++ } ++ /* not support ref_pic_list_reordering */ ++ if (sh->i_type != SLICE_I) ++ bs_write_u1(bs, 0); ++ if (sh->i_type == SLICE_B) ++ bs_write_u1(bs, 0); ++ /* not support weighted pred */ ++ /* not support dec_ref_pic_marking */ ++ if (sh->i_ref_idc) ++ { ++ if (sh->b_idr_pic) ++ { ++ bs_write_u1(bs, 0/*no_output_prior_pics_flag*/); ++ bs_write_u1(bs, 0/*long_term_reference_flag*/); ++ } ++ else ++ bs_write_u1(bs, 0/*adaptive_ref_pic_marking_mode_flag*/); ++ } ++ if (sh->pps->b_cabac && sh->i_type != SLICE_I) ++ bs_write_ue(bs, sh->i_cabac_init_idc); ++ bs_write_se(bs, sh->i_qp - sh->pps->i_pic_init_qp); ++ if (sh->pps->b_deblocking_filter_control) ++ { ++ bs_write_ue(bs, sh->i_disable_deblocking_filter_idc); ++ if (sh->i_disable_deblocking_filter_idc != 1) ++ { ++ bs_write_se(bs, sh->i_alpha_c0_offset_div2); ++ bs_write_se(bs, sh->i_beta_offset_div2); ++ } ++ } ++ if (sh->pps->b_cabac) ++ bs_align(bs, 1); ++ ++ return bs->bits_pos; ++} +diff --git a/drivers/mstar/mfev5/mfe5/mfe_h264.h b/drivers/mstar/mfev5/mfe5/mfe_h264.h +new file mode 100644 +index 00000000..e2f3ee23 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_h264.h +@@ -0,0 +1,112 @@ ++ ++#ifndef _MFE_H264_H_ ++#define _MFE_H264_H_ ++ ++typedef struct bitstream { ++ int bits_pos; ++ int length; ++ int left_count; ++ uint code_bits; ++ uchar* curr; ++ uchar* buffer; ++ int ebsp_zeros; ++} bs_t; ++ ++int avc_reset(bs_t*,uchar*, int); ++int avc_flush(bs_t*); ++int avc_count(bs_t*); ++ ++#define NAL_SLICE 1 ++#define NAL_IDR 5 ++#define NAL_SPS 7 ++#define NAL_PPS 8 ++#define NAL_FILLER 12 ++ ++#define NAL_PRIO_DISPOSED 0 ++#define NAL_PRIO_LOW 1 ++#define NAL_PRIO_HIGH 2 ++#define NAL_PRIO_HIGHEST 3 ++ ++typedef struct sps { ++ int i_sps_id; ++ int i_profile_idc; ++ int i_level_idc; ++ int b_constraint_set0; ++ int b_constraint_set1; ++ int b_constraint_set2; ++ int b_constraint_set3; ++ int i_log2_max_frame_num; ++ int i_poc_type; ++ int i_log2_max_poc_lsb; ++ int i_num_ref_frames; ++ int b_gaps_in_frame_num_value_allow; ++ int i_mb_w; ++ int i_mb_h; ++ int b_direct8x8_inference; ++ int b_crop; ++ struct { ++ int i_left, i_right; ++ int i_top, i_bottom; ++ } crop; ++ int b_vui_param_pres; ++ struct vui { ++ int b_video_signal_pres; ++ int i_video_format; ++ int b_video_full_range; ++ int b_colour_desc_pres; ++ int i_colour_primaries; ++ int i_transf_character; ++ int i_matrix_coeffs; ++ } vui; ++} sps_t; ++ ++typedef struct vui vui_t; ++ ++typedef struct pps { ++ sps_t* sps; ++ int i_pps_id; ++ int b_cabac; ++ /*only support slice_groups==1*/ ++ int i_num_ref_idx_l0_default_active; ++ int i_num_ref_idx_l1_default_active; ++ /*not support weighted pred*/ ++ int i_pic_init_qp; ++ int i_pic_init_qs; ++ int i_cqp_idx_offset; ++ int b_deblocking_filter_control; ++ int b_constrained_intra_pred; ++ int b_redundant_pic_cnt; ++} pps_t; ++ ++#define SLICE_P 0 ++#define SLICE_B 1 ++#define SLICE_I 2 ++ ++typedef struct slice { ++ int b_idr_pic; ++ int i_ref_idc; ++ sps_t* sps; ++ pps_t* pps; ++ int i_type; ++ int i_first_mb; ++ int i_frame_num; ++ int i_idr_pic_id; ++ int i_poc; ++ int i_redundant_pic_cnt; ++ int b_direct_spatial_mv_pred; ++ int b_num_ref_idx_override; ++ int i_num_ref_idx_l0_active; ++ int i_num_ref_idx_l1_active; ++ int i_cabac_init_idc; ++ int i_qp; ++ int i_disable_deblocking_filter_idc; ++ int i_alpha_c0_offset_div2; ++ int i_beta_offset_div2; ++} slice_t; ++ ++int avc_write_nal(bs_t*, uchar ); ++int avc_write_sps(bs_t*, sps_t*); ++int avc_write_pps(bs_t*, pps_t*); ++int avc_write_slice_header(bs_t*, slice_t*); ++ ++#endif/*_MFE_H264_H_*/ +diff --git a/drivers/mstar/mfev5/mfe5/mfe_msb2.c b/drivers/mstar/mfev5/mfe5/mfe_msb2.c +new file mode 100644 +index 00000000..b2bd962b +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_msb2.c +@@ -0,0 +1,469 @@ ++ ++#include ++#include ++#include ++ ++/************************************************************************/ ++/* Version Declaration */ ++/************************************************************************/ ++ ++#define MSB2_NAME "MSB2" ++#define MSB2_VER_MJR 1 ++#define MSB2_VER_MNR 1 ++#define MSB2_VER_EXT 01 ++#define _EXP(expr) #expr ++#define _STR(expr) _EXP(expr) ++ ++/************************************************************************/ ++/* Macros */ ++/************************************************************************/ ++ ++#define UP_QP_DIFF_LIMIT 3 ++#define LF_QP_DIFF_LIMIT 3 ++ ++#define LOGOFF_DEFAULT 1 ++#define LOWERQ_DEFAULT 12 ++#define UPPERQ_DEFAULT 48 ++#define BOUNDQ_DEFAULT -1 ++ ++/************************************************************************/ ++/* Configuration */ ++/************************************************************************/ ++ ++/************************************************************************/ ++/* Constant */ ++/************************************************************************/ ++ ++/************************************************************************/ ++/* Local structures */ ++/************************************************************************/ ++ ++#define PICTYPES 2 ++ ++typedef struct mfe_msb2 ++{ ++ mfe_rctl rqcx; ++ int i_method; ++ int i_btrate; ++ int i_levelq; ++ int i_deltaq; ++ int n_fmrate; ++ int d_fmrate; ++ int i_fmrate; ++ int i_pixels; ++ int i_blocks; ++ short b_mbkadp, i_limitq; ++ short i_frmdqp, i_blkdqp; ++ short i_upperq, i_lowerq; ++ int i_gopbit; ++ int i_frmbit; ++ int i_pixbit; ++ int i_budget; ++ int i_ipbias; ++ int i_smooth; ++ int i_bucket; ++ int i_upperb, i_lowerb; ++ int i_margin; ++ int i_radius; ++ int i_degree; ++ int i_errpro; ++ int i_imbase; ++ int i_imbits; // bit-pos:imaginary ++ int i_rebits; // bit-pos:real ++ ++ iir_t iir_rqprod[PICTYPES]; ++ acc_t acc_rqprod; ++ acc_t acc_bitcnt; ++ int i_intrabit; ++ ++} mfe_msb2; ++ ++/************************************************************************/ ++/* Local prototypes */ ++/************************************************************************/ ++ ++#define COMPLEX_I (1<<24) ++#define COMPLEX_P (1<<20) ++#define QP_UPPER (48) ++#define QP_LOWER (12) ++#define QP_RANGE (QP_UPPER-QP_LOWER) ++#define QP_MAX (51) ++#define QP_MIN ( 0) ++ ++static int msb2_seq_sync(rqct_ops*); ++static int msb2_seq_done(rqct_ops*); ++static int msb2_seq_conf(rqct_ops*); ++static int msb2_enc_conf(rqct_ops*, mhve_job*); ++static int msb2_enc_done(rqct_ops*, mhve_job*); ++static void _msb2_ops_free(rqct_ops* rqct) { MEM_FREE(rqct); } ++ ++/************************************************************************/ ++/* Functions */ ++/************************************************************************/ ++ ++void* msb2_allocate(void) ++{ ++ rqct_ops* rqct = NULL; ++ mfe_rctl* rqcx; ++ mfe_msb2* msb2; ++ ++ if (!(rqct = MEM_ALLC(sizeof(mfe_msb2)))) ++ return NULL; ++ ++ MEM_COPY(rqct->name, MSB2_NAME, 5); ++ rqct->release = _msb2_ops_free; ++ rqct->seq_sync = msb2_seq_sync; ++ rqct->seq_done = msb2_seq_done; ++ rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->seq_conf = msb2_seq_conf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = msb2_enc_conf; ++ rqct->enc_done = msb2_enc_done; ++ rqct->i_enc_nr = 0; ++ rqct->i_enc_bs = 0; ++ rqcx = (mfe_rctl*)rqct; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.i_method = RQCT_METHOD_CQP; ++ rqcx->attr.i_btrate = 0; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = 1; ++ rqcx->attr.i_upperq = QP_UPPER; ++ rqcx->attr.i_lowerq = QP_LOWER; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->attr.i_period = 0; ++ rqcx->attr.b_logoff = LOGOFF_DEFAULT; ++ rqcx->i_config = 0; ++ rqcx->i_pcount = 0; ++ rqcx->i_period = 0; ++ msb2 = (mfe_msb2*)rqcx; ++ msb2->i_levelq =36; ++ ++ return rqct; ++} ++ ++char* msb2_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d-%02d:r&d analysis.",MSB2_NAME,MSB2_VER_MJR,MSB2_VER_MNR,MSB2_VER_EXT); ++ return line; ++} ++#define IPR_BIT (16) ++#define IPR_FAC (1<>(QSC_BIT)))>>(10-(QSC_BIT))) ++static int qscale[]={ ++ QSCALE( 645),QSCALE( 724),QSCALE( 813),QSCALE( 912),QSCALE( 1024), ++QSCALE( 1149),QSCALE( 1290),QSCALE( 1448),QSCALE( 1625),QSCALE( 1825),QSCALE( 2048), ++QSCALE( 2299),QSCALE( 2580),QSCALE( 2896),QSCALE( 3251),QSCALE( 3649),QSCALE( 4096), ++QSCALE( 4598),QSCALE( 5161),QSCALE( 5793),QSCALE( 6502),QSCALE( 7298),QSCALE( 8192), ++QSCALE( 9195),QSCALE( 10321),QSCALE( 11585),QSCALE( 13004),QSCALE( 14596),QSCALE( 16384), ++QSCALE( 18390),QSCALE( 20643),QSCALE( 23170),QSCALE( 26008),QSCALE( 29193),QSCALE( 32768), ++QSCALE( 36781),QSCALE( 41285),QSCALE( 46341),QSCALE( 52016),QSCALE( 58386),QSCALE( 65536), ++QSCALE( 73562),QSCALE( 82570),QSCALE( 92682),QSCALE(104032),QSCALE(116772),QSCALE(131072), ++QSCALE(147123),QSCALE(165140),QSCALE(185364),QSCALE(208064),QSCALE(233544),QSCALE(262144), ++}; ++static int qp2qs(int qp) ++{ ++ if (qp< 0) return qscale[ 0]; ++ if (qp>51) return 2147483647; ++ return qscale[qp]; ++} ++static int qindex[]={ ++ 4,10,16,16,22,22,22,22,28,28,28,28,28,28,28,28, ++34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34, ++40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, ++40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++}; ++static int qs2qp(int qs) ++{ ++ int idx, cost, best; ++ if (qsqscale[51]) return 51; ++ idx = qindex[qs>>QSC_BIT]; ++ best = (qscale[idx]-qs); ++ while (0<(cost=(qscale[--idx]-qs))) ++ best=cost; ++ if (best<-cost) ++ return ++idx; ++ return idx; ++} ++#define DQBIAS_BIT 15 ++#define DQBIAS_FAC (1<>(16-DQBIAS_BIT)) ++static const int dqplot[] = { ++DQBIAS( 0),//0.0000000000 ++DQBIAS(13889),//0.2119255505 ++DQBIAS(22749),//0.3471209568 ++DQBIAS(28655),//0.4372439481 ++DQBIAS(33009),//0.5036719007 ++DQBIAS(36440),//0.5560238879 ++DQBIAS(39266),//0.5991464061 ++DQBIAS(41666),//0.6357766516 ++DQBIAS(43752),//0.6676004651 ++DQBIAS(45595),//0.6957262149 ++DQBIAS(47246),//0.7209202303 ++DQBIAS(48741),//0.7437338663 ++DQBIAS(50107),//0.7645767803 ++DQBIAS(51365),//0.7837615271 ++DQBIAS(52529),//0.8015319306 ++DQBIAS(53614),//0.8180818208 ++DQBIAS(54629),//0.8335678038 ++DQBIAS(55582),//0.8481182052 ++DQBIAS(56482),//0.8618394843 ++DQBIAS(57332),//0.8748209289 ++DQBIAS(58139),//0.8871381559 ++DQBIAS(58907),//0.8988557638 ++DQBIAS(59640),//0.9100293726 ++DQBIAS(60339),//0.9207072127 ++DQBIAS(61010),//0.9309313772 ++DQBIAS(61652),//0.9407388203 ++DQBIAS(62270),//0.9501621606 ++DQBIAS(62864),//0.9592303332 ++DQBIAS(63437),//0.9679691242 ++DQBIAS(63989),//0.9764016112 ++DQBIAS(64523),//0.9845485296 ++DQBIAS(65040),//0.9924285792 ++}; ++static int qdelta(int r) ++{ ++ int d = 0, s = r<0; ++ r = s?-r:r; ++ while (r > dqplot[++d]) ; ++ --d; ++ return s?-d:d; ++} ++/* ++static int dqbias(int d) ++{ ++ int i=((unsigned)(d+32)>64)?32:(d<0?-d:d); ++ int p=dqplot[i]; ++ return d<0?-p:p; ++} ++*/ ++#define MAX_SUMQS ((1<< 24)- 1) ++#define ALIGN2MB(l) (((l)+15)>>4) ++static int calc_limitq(int mbs) ++{ ++ int qs = MAX_SUMQS/(mbs-1); ++ int qp = qs2qp(qs); ++ return qsi_pcount = 0; ++ return 0; ++} ++ ++#define SMOOTH_X (16) ++ ++static int msb2_seq_conf(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_msb2* msb2 = (mfe_msb2*)rqcx; ++ ++ printk("%s\n",msb2_describe()); ++ ++ msb2->i_method = (int)rqcx->attr.i_method; ++ msb2->i_btrate = (int)rqcx->attr.i_btrate; ++ if (rqcx->attr.i_leadqp > 8 && rqcx->attr.i_leadqp < 48) ++ msb2->i_levelq = (int)rqcx->attr.i_leadqp; ++ msb2->i_deltaq = (int)rqcx->attr.i_deltaq; ++ msb2->n_fmrate = (int)rqcx->attr.n_fmrate; ++ msb2->d_fmrate = (int)rqcx->attr.d_fmrate; ++ msb2->i_pixels = (int)rqcx->attr.i_pict_w*rqcx->attr.i_pict_h; ++ msb2->i_fmrate = (msb2->n_fmrate+msb2->n_fmrate-1)/msb2->d_fmrate; ++ msb2->i_blocks = ALIGN2MB(rqcx->attr.i_pict_w)*ALIGN2MB(rqcx->attr.i_pict_h); ++ msb2->i_limitq = calc_limitq(msb2->i_blocks); ++ msb2->i_upperq = (unsigned)rqcx->attr.i_upperq<52?rqcx->attr.i_upperq:QP_UPPER; ++ msb2->i_lowerq = (unsigned)rqcx->attr.i_lowerq<52?rqcx->attr.i_lowerq:QP_LOWER; ++ if (msb2->i_btrate == 0) ++ msb2->i_method = RQCT_METHOD_CQP; ++ rqcx->i_pcount = ++ rqcx->i_period = (int)rqcx->attr.i_period; ++ ++ msb2->i_smooth = rqcx->i_period*2; ++ msb2->i_frmbit = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate,msb2->n_fmrate); ++ msb2->i_pixbit = (int)div_s64((int64)msb2->i_frmbit*BPP_FAC,msb2->i_pixels); ++ msb2->i_gopbit = rqcx->i_period*msb2->i_frmbit; ++ msb2->b_mbkadp = 0; ++ msb2->i_blkdqp = 4; ++ msb2->i_frmdqp = 1; ++ ++ msb2->i_degree = msb2->i_btrate/(QP_RANGE*2); ++ msb2->i_margin = msb2->i_degree*(QP_RANGE); ++ msb2->i_bucket = msb2->i_margin<<1; ++ msb2->i_radius = msb2->i_margin>>1; ++ msb2->i_rebits = ++ msb2->i_imbits = ++ msb2->i_imbase = msb2->i_margin+(msb2->i_levelq-QP_LOWER)*msb2->i_degree; ++ msb2->i_lowerb = msb2->i_margin+(msb2->i_lowerq-QP_LOWER)*msb2->i_degree; ++ msb2->i_upperb = msb2->i_margin+(msb2->i_upperq-QP_LOWER)*msb2->i_degree; ++ ++ iir_init(&msb2->iir_rqprod[RQCT_PICTYP_I], COMPLEX_I, KAPA_ONE*3/4); ++ iir_init(&msb2->iir_rqprod[RQCT_PICTYP_P], COMPLEX_P, KAPA_ONE*2/4); ++ acc_init(&msb2->acc_rqprod, COMPLEX_P); ++ acc_init(&msb2->acc_bitcnt, msb2->i_frmbit*3/4); ++ ++ return 0; ++} ++ ++static int msb2_enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ mfe_msb2* msb2 = (mfe_msb2*)rqcx; ++ int qsc, bpp, pqp, dqp, lim, tgt=0; ++ int uqp = msb2->i_upperq; ++ int lqp = msb2->i_lowerq; ++ switch (msb2->i_method) ++ { ++ case RQCT_METHOD_CQP: ++ rqct->i_enc_qp = msb2->i_levelq; ++ if (IS_IPIC(rqct->i_pictyp)) ++ rqct->i_enc_qp -= msb2->i_deltaq; ++ break; ++ case RQCT_METHOD_CBR: ++ case RQCT_METHOD_VBR: ++ default: ++ lim = msb2->i_limitq; ++ if (IS_IPIC(rqct->i_pictyp)) ++ { ++ int xi = iir_data(&msb2->iir_rqprod[RQCT_PICTYP_I]); ++ int xp = acc_calc(&msb2->acc_rqprod,SMOOTH_X)/SMOOTH_X; ++ int ri = (int)div_s64((int64)qp2qs(40+msb2->i_deltaq)*IPR_FAC,qp2qs(40)); ++ int rp = (int)div_s64((int64)xp*IPR_FAC,xi); ++ msb2->i_budget = (int)div_s64((int64)msb2->i_gopbit*ri,(rqcx->i_period*rp+ri-rp)); ++ bpp = (int)div_s64((int64)msb2->i_budget*BPP_FAC,msb2->i_pixels); ++ qsc = xi/bpp; ++ pqp = _MAX(qs2qp(qsc),msb2->i_levelq-msb2->i_deltaq); ++ rqct->i_enc_qp = pqp = _MAX(lqp,_MIN(pqp,uqp)); ++ tgt = msb2->i_budget/msb2->i_blocks; ++ uqp = _MIN(pqp+msb2->i_blkdqp,_MIN(lim,uqp)); ++ lqp = _MAX(pqp-msb2->i_blkdqp,lqp); ++ msb2->b_mbkadp = msb2->i_blkdqp>0 && pqpi_ipbias = 0; ++ break; ++ } ++ pqp = QP_LOWER+(msb2->i_imbase-msb2->i_margin)/msb2->i_degree; ++ dqp = qdelta((int)div_s64((int64)(msb2->i_imbits-msb2->i_imbase)*DQBIAS_FAC,msb2->i_radius)); ++ msb2->i_levelq = pqp; ++ msb2->i_budget = msb2->i_frmbit-msb2->i_ipbias; ++ msb2->i_budget = _MAX(msb2->i_budget,msb2->i_frmbit/16); ++ rqct->i_enc_qp = pqp = _MAX(_MIN(uqp,pqp+dqp),lqp); ++ tgt = msb2->i_budget/msb2->i_blocks; ++ uqp = _MIN(pqp+msb2->i_blkdqp,_MIN(lim,uqp)); ++ lqp = _MAX(pqp-msb2->i_blkdqp,lqp); ++ msb2->b_mbkadp = msb2->i_blkdqp>0 && pqpb_mbkadp = msb2->b_mbkadp && !rqcx->attr.b_dqmstat; ++ regs->reg00_g_mbr_en = msb2->b_mbkadp; ++ regs->reg26_s_mbr_pqp_dlimit = LF_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = UP_QP_DIFF_LIMIT; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = qp2qs(rqct->i_enc_qp); ++ regs->reg26_s_mbr_tmb_bits = tgt>1 ? tgt : 1; ++ regs->reg2a_s_mbr_qp_min = lqp; ++ regs->reg2a_s_mbr_qp_max = uqp; ++ regs->reg6e_s_mbr_qstep_min = qp2qs(lqp); ++ regs->reg6f_s_mbr_qstep_max = qp2qs(uqp); ++ return 0; ++} ++ ++#define BSP_DUR (32) ++ ++static int msb2_enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_msb2* msb2 = (mfe_msb2*)rqcx; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ int bpp, cpx, bps, inc, dec, dur, avq = qp2qs(rqct->i_enc_qp), bcn = mjob->i_bits; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ rqct->i_enc_bs+= rqct->i_bitcnt/8; ++ rqct->i_enc_nr++; ++ ++ if (msb2->b_mbkadp) ++ avq = (avq + regs->sumofq)/msb2->i_blocks; ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ bpp = (int)div_s64((int64)rqct->i_bitcnt*BPP_FAC,msb2->i_pixels); ++ dur = rqcx->i_period; ++ cpx = bpp * avq; ++ ++ if (IS_PPIC(rqct->i_pictyp)) ++ { ++ acc_push(&msb2->acc_bitcnt, bcn); ++ acc_push(&msb2->acc_rqprod, cpx); ++ iir_push(&msb2->iir_rqprod[RQCT_PICTYP_P], acc_calc(&msb2->acc_rqprod,8)/8); ++ msb2->i_errpro = (msb2->i_ipbias-msb2->i_frmbit+bcn); ++ msb2->i_imbits += msb2->i_errpro; ++ msb2->i_imbits = _MIN(msb2->i_imbits,msb2->i_upperb+msb2->i_radius); ++ msb2->i_imbits = _MAX(msb2->i_imbits,msb2->i_lowerb); ++ msb2->i_rebits = _MAX(msb2->i_rebits,msb2->i_imbits); ++ } ++ else ++ { ++ msb2->i_intrabit = bcn; ++ iir_push(&msb2->iir_rqprod[RQCT_PICTYP_I], cpx); ++ if (msb2->i_imbits > msb2->i_upperb) ++ msb2->i_rebits = msb2->i_imbits; ++ msb2->i_errpro = (msb2->i_rebits-msb2->i_imbits); ++ msb2->i_imbits += msb2->i_errpro; ++ if (dur >= 2) ++ msb2->i_ipbias = (bcn - msb2->i_frmbit) / (dur-1); ++ if (dur == 0) ++ acc_push(&msb2->acc_bitcnt, bcn); ++ } ++ msb2->i_rebits += (bcn - msb2->i_frmbit); ++ ++ if (dur > 0) ++ bps = acc_calc(&msb2->acc_bitcnt, dur-1) + msb2->i_intrabit; ++ else ++ bps = acc_calc(&msb2->acc_bitcnt, dur=BSP_DUR); ++ bps = (int)div_s64((int64)bps*msb2->n_fmrate,msb2->d_fmrate*dur); ++ ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d bps:%8d",\ ++ rqct->name,rqct->i_enc_nr%10000,rqct->i_pictyp==RQCT_PICTYP_I?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt,bps); ++#if 0 ++// printk("%s\n",rqct->print_line); ++ printk("<%s#%04d@%c:%2d> bitcnt:%8d bps:%8d im:%8d df:%8d re:%8d\n",\ ++ rqct->name,rqct->i_enc_nr%10000,rqct->i_pictyp==RQCT_PICTYP_I?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt,bps,msb2->i_imbits,msb2->i_imbase,msb2->i_rebits); ++#endif ++ bcn = msb2->i_imbits-msb2->i_imbase; ++ inc = msb2->i_frmbit/64; ++ dec = -3*inc; ++ bcn = _MIN(inc,_MAX(bcn,dec)); ++ msb2->i_imbase += bcn; ++ msb2->i_imbase = _MIN(_MAX(msb2->i_imbase,msb2->i_lowerb),msb2->i_upperb); ++ ++ return 0; ++} +diff --git a/drivers/mstar/mfev5/mfe5/mfe_msb3.c b/drivers/mstar/mfev5/mfe5/mfe_msb3.c +new file mode 100644 +index 00000000..506b520f +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_msb3.c +@@ -0,0 +1,1386 @@ ++ ++#include ++ ++#include ++#include ++ ++/************************************************************************/ ++/* Macros */ ++/************************************************************************/ ++#define MSBR_VER_EXT 00 ++#define _EXP(expr) #expr ++#define _STR(expr) _EXP(expr) ++#define RC_MODULE_NAME "MSB3" ++#define RC_MODULE_VER_MAJOR 1 ++#define RC_MODULE_VER_MINOR 0 ++#define RC_MODULE_VER_TEST "T"_STR(MSBR_VER_EXT) ++#define MSBR_NAME RC_MODULE_NAME ++#define MSBR_VER_MJR RC_MODULE_VER_MAJOR ++#define MSBR_VER_MNR RC_MODULE_VER_MINOR ++ ++/* Debug related configuration */ ++#define DBG_PRINT_ENABLE 0 ++ ++/* General calculations */ ++#ifndef MSRC_MAX ++#define MSRC_MAX(a,b) (((a)>(b))?(a):(b)) ++#endif ++#ifndef MSRC_MIN ++#define MSRC_MIN(a,b) (((a)<(b))?(a):(b)) ++#endif ++#ifndef MSRC_FIT_IN_RANGE ++#define MSRC_FIT_IN_RANGE(a,low,high) MSRC_MIN(MSRC_MAX((a),(low)),(high)) ++#endif ++ ++#ifndef MSRC_PERCENT ++#define MSRC_PERCENT(percent,a) ( (percent) * (a) / 100 ) ++#endif ++ ++/* Debugging related macro */ ++#if DBG_PRINT_ENABLE ++#define MSBR_DBG printk ++#else ++#define MSBR_DBG(...) ++#endif ++ ++/* Static assert */ ++#define MSBR_SASSERT(EXP,STR) _Static_assert(EXP,STR) ++#define MSBR_ASSERT assert ++#define MFE_ASSERT(p) ++ ++/************************************************************************/ ++/* Configuration */ ++/************************************************************************/ ++ ++/* Skip the first N frames for VBV calculation */ ++#define CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES 50 ++ ++/* The feature to reset the fullness value if fullness overflow or underflow */ ++/* 1 - Enable */ ++/* 0 - Disable */ ++#define CFG_VBV_BUF_OVERFLOW_RESET 1 ++#define CFG_VBV_BUF_UNDERFLOW_RESET 1 ++ ++/* The selection of the rqcx of the new Qs */ ++#define LQS_USE_LAST_SET_QS 0 /* The last frame encode qs setting */ ++#define LQS_USE_LAST_AVG_ENC_QS 1 /* Feed back from HW */ ++#define LQS_USE_LAST_FRM_TYPE_SET_QS 2 /* The last same type frame encode qs setting */ ++#define CFG_LAST_QS_SELECTION LQS_USE_LAST_SET_QS ++ ++/* The choice of the VBV frame quota selection */ ++#define VFQ_USE_AVERAGE_SIZE 0 /* The average size of each frame */ ++#define VFQ_USE_WEIGHTED_SIZE 1 /* The weighted size rqcx on the setting of */ ++ /* IFRAME_WEIGHT, PFRAME_WEIGHT, BFRAME_WEIGHT */ ++ /* and Gop size */ ++#define CFG_VBV_FRAME_QUOTA_METHOD VFQ_USE_WEIGHTED_SIZE ++ ++#define CFG_CBR_IFRAME_CQP 0 /* 0 - Disable, 1 - Enable */ ++#define CFG_CBR_PFRAME_CQP 0 /* 0 - Disable, 1 - Enable */ ++ ++#define RDC_WEIGHTED_DIVIDED 0 ++#define RDC_AVERAGE_DIVIDED 1 ++#define CFG_RC_DELTA_CACULATE_METHOD RDC_WEIGHTED_DIVIDED ++ ++#define QS_SHIFT_FACTOR 5 ++ ++#define UP_QP_DIFF_LIMIT 3 ++#define LF_QP_DIFF_LIMIT 3 ++// Spec limitation is [1,51] ++#define I_FRAME_INIT_QP (30) ++#define I_FRAME_MAX_QP (44) ++#define I_FRAME_MIN_QP (15) ++ ++#define P_FRAME_INIT_QP (35) ++#define P_FRAME_MAX_QP (48) ++#define P_FRAME_MIN_QP (15) ++ ++#define B_FRAME_INIT_QP (P_FRAME_INIT_QP) ++#define B_FRAME_MAX_QP (P_FRAME_MAX_QP) ++#define B_FRAME_MIN_QP (P_FRAME_MIN_QP) ++ ++#define I_FRAME_MARGIN_QP (0) ++#define P_FRAME_MARGIN_QP (0) ++#define B_FRAME_MARGIN_QP (0) ++ ++// Compute qs ++#define SMOOTH_BASE 10 // 1 sec = 10* 100ms ++#define SMOOTH_PERIOD 10 // in second ++#define INIT_QP_OFFSET 18 ++#define INIT_QP_FACTOR 72 ++#define MIN_INIT_QP I_FRAME_MIN_QP ++#define MAX_INIT_QP I_FRAME_MAX_QP ++ ++#define THR_QP_FRAMESKIP (40) ++ ++//! How many seconds of frames are responsible for compensation of bitrate usage. ++#define SMOOTH_SECOND_CBR 10 // unit 100 ms ++#define SMOOTH_SECOND_CVBR 30 // unit 100 ms ++#define SMOOTH_SECOND_VBR 100 // unit 100 ms ++#define SMOOTH_FACTOR_MIN 100 // unit 100 ms ++ ++#define VBV_TGT_LVL_CBR 20 // unit 100 ms ++#define VBV_FUL_LOW_CBR 0 // unit 100 ms ++#define VBV_FUL_HIGH_CBR 40 // unit 100 ms ++#define VBV_BUF_SIZE_CBR 40 // unit 100 ms ++ ++#define VBV_TGT_LVL_VBR 40 // unit 100 ms ++#define VBV_FUL_LOW_VBR 0 // unit 100 ms ++#define VBV_FUL_HIGH_VBR 80 // unit 100 ms ++#define VBV_BUF_SIZE_VBR 80 // unit 100 ms ++ ++//! Default I-frame weighting over inter-frame ++#define IFRAME_WEIGHT (1024*7) ++#define PFRAME_WEIGHT 1024 ++#define BFRAME_WEIGHT 768 ++ ++ ++ ++MSBR_SASSERT( IFRAME_WEIGHT>0 && PFRAME_WEIGHT > 0, "The weighting of I frame or P frame should be bigger than zero" ); ++ ++/************************************************************************/ ++/* Constant */ ++/************************************************************************/ ++ ++// Operation Methods ++#define CONST_QP 0 ++#define CBR 1 ++#define VBR 2 ++#define CONSTRAINED_VBR 3 ++#define STATIC_CBR 4 ++ ++ ++// For Constrained VBR ++#define MAX_GAUGE_SIZE 64 ++ ++#define FRAME_TYPE_I 0 // I, P, B 3 types ++#define FRAME_TYPE_P 1 // I, P, B 3 types ++#define FRAME_TYPE_B 2 // I, P, B 3 types ++#define MAX_FRAME_TYPE 3 // I, P, B 3 types ++ ++/************************************************************************/ ++/* Local structures */ ++/************************************************************************/ ++ ++//#define LOG_MSG ++ ++typedef struct mfe_msb3 ++{ ++ mfe_rctl rqcx; ++ int i_method; ++ short i_leadqp, i_deltaq; ++ int i_btrate; ++ int i_pixels; ++ int n_fmrate; ++ int d_fmrate; ++ int i_fmrate; ++ int i_tgt_mb; ++ int i_avg_qs; ++ // Derived variables ++ int i_avgbpf; ++ int m_bpf[MAX_FRAME_TYPE]; // I, P, B ++ /* coded frame counter */ ++ int i_gbl_frm_nr; ++ int i_frm_nr; ++ int i_frm_count[MAX_FRAME_TYPE]; ++ int64 i_totbit; ++ int64 i_frm_totbits[MAX_FRAME_TYPE]; ++ /* integral part of frame-rate */ ++ int i_fps; ++ int i_maxbps; ++ /* this-frame params */ ++ int i_this_enc_qs; ++ int i_this_max_qp; ++ int i_this_min_qp; ++ int i_this_max_qs; ++ int i_this_min_qs; ++ /* last-frame status */ ++ int i_last_avg_qs; ++ int i_last_frm_bs; ++ int i_last_tgt_bs; ++ int i_last_enc_qp; ++ int i_last_enc_qs; ++ int i_last_qp[MAX_FRAME_TYPE]; ++ int i_last_qs[MAX_FRAME_TYPE]; ++ int i_last_tgt_size[MAX_FRAME_TYPE]; ++ int i_last_frm_size[MAX_FRAME_TYPE]; ++ ++ /* init qp values */ ++ int i_init_qp[MAX_FRAME_TYPE]; // Max qp value for each frame type ++ int i_max_qp[MAX_FRAME_TYPE]; // Max qp value for each frame type ++ int i_min_qp[MAX_FRAME_TYPE]; // Mini qp value for each frame type ++ int i_margin_qp[MAX_FRAME_TYPE]; // The margin of QP setting between the boundaries. ++ ++ /* bitrate usage compensation */ ++ int i_vbv_buf_size; // Rate control buffer size ++ int i_vbv_fullness_low; // Rate control buffer fullness low bound ++ int i_vbv_fullness_high; // Rate control buffer fullness high bound ++ int i_vbv_fullness; // Rate control buffer fullness ++ int i_vbv_real_fullness; // Rate control buffer fullness ++ int i_vbv_target; // Rate control buffer target fullness ++ int i_vbv_balance; ++ ++ int i_smooth_cnt; ++ int i_smooth_min; ++ /* variable bitrate */ ++ int i_lt_qs64; ++ // model parameters ++ int i_tgt_bs; // target number of bits of current frame ++ /* only for Constrained VBR */ ++ int i_max_offset; ++ int i_gauge_bgt[MAX_GAUGE_SIZE]; ++ int i_gauge_cnt; ++ int i_gauge_idx; ++ int i_gauge_bps; ++ int i_frozen; ++ int i_thr_qp_frameskip; ++ int i_frameskip; // original MFE-RC: pic_done's output ++ /*start new parameters */ ++ int i_levelq; ++ int i_smooth; ++ int i_pixbit; ++ int i_frmbit; ++ int i_budget; ++ int i_ipbias; ++ int i_btbias; ++ int i_gopbit; ++ int i_bucket; ++ int i_missed; ++ int i_bitpos; ++ int i_dqbias; ++#define PICTYPES (2) ++#define COMPLEXITY_I (1<<24) ++#define COMPLEXITY_P (1<<20) ++ iir_t iir_rqprod[PICTYPES]; ++ acc_t acc_rqprod; ++ acc_t acc_bitcnt; ++ /*endof new parameters */ ++} mfe_msb3; ++ ++typedef struct ++{ ++ int bps; ++ int fps_by_10; ++ int pixels; ++ int qp_bound; ++} qp_bound; ++ ++#define BOUND_NUMERIC_SHIFT 16 ++ ++// I frame QP upper bound ++static const qp_bound qp_i_upper[]= { ++ { 256000, 250, 1920*1080, 51 }, ++ { 512000, 250, 1920*1080, 44 }, ++ { 1000000, 250, 1920*1080, 43 }, ++ { 2000000, 250, 1920*1080, 39 }, ++ { 3000000, 250, 1920*1080, 39 } ++}; ++ ++// P frame QP upper bound ++static const qp_bound qp_p_upper[]= { ++ { 256000, 250, 1920*1080, 51 }, ++ { 512000, 250, 1920*1080, 44 }, ++ { 1000000, 250, 1920*1080, 43 }, ++ { 2000000, 250, 1920*1080, 40 }, ++ { 3000000, 250, 1920*1080, 40 } ++}; ++ ++#define SIZE_OF_I_QP_UPP_BOUND sizeof( qp_i_upper) / sizeof(qp_bound); ++#define SIZE_OF_P_QP_UPP_BOUND sizeof( qp_p_upper) / sizeof(qp_bound); ++ ++#define BOUND_FP_SHIFT 16 // just for calculation ++ ++#define IPR_BIT (16) ++#define IPR_FAC (1<>(QSC_BIT)))>>(10-(QSC_BIT))) ++static int qscale[]={ ++ QSCALE( 645),QSCALE( 724),QSCALE( 813),QSCALE( 912),QSCALE( 1024), ++QSCALE( 1149),QSCALE( 1290),QSCALE( 1448),QSCALE( 1625),QSCALE( 1825),QSCALE( 2048), ++QSCALE( 2299),QSCALE( 2580),QSCALE( 2896),QSCALE( 3251),QSCALE( 3649),QSCALE( 4096), ++QSCALE( 4598),QSCALE( 5161),QSCALE( 5793),QSCALE( 6502),QSCALE( 7298),QSCALE( 8192), ++QSCALE( 9195),QSCALE( 10321),QSCALE( 11585),QSCALE( 13004),QSCALE( 14596),QSCALE( 16384), ++QSCALE( 18390),QSCALE( 20643),QSCALE( 23170),QSCALE( 26008),QSCALE( 29193),QSCALE( 32768), ++QSCALE( 36781),QSCALE( 41285),QSCALE( 46341),QSCALE( 52016),QSCALE( 58386),QSCALE( 65536), ++QSCALE( 73562),QSCALE( 82570),QSCALE( 92682),QSCALE(104032),QSCALE(116772),QSCALE(131072), ++QSCALE(147123),QSCALE(165140),QSCALE(185364),QSCALE(208064),QSCALE(233544),QSCALE(262144), ++}; ++static int qp2qs(int qp) ++{ ++ if (qp< 0) return qscale[ 0]; ++ if (qp>51) return 2147483647; ++ return qscale[qp]; ++} ++static int qindex[]={ ++ 4,10,16,16,22,22,22,22,28,28,28,28,28,28,28,28, ++34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34, ++40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, ++40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++}; ++static int qs2qp(int qs) ++{ ++ int idx, cost, best; ++ if (qsqscale[51]) return 51; ++ idx = qindex[qs>>QSC_BIT]; ++ best = (qscale[idx]-qs); ++ while (0<(cost=(qscale[--idx]-qs))) ++ best=cost; ++ if (best<-cost) ++ return ++idx; ++ return idx; ++} ++ ++/************************************************************************/ ++/* Local prototypes */ ++/************************************************************************/ ++ ++static int msb3_seq_sync(rqct_ops*); ++static int msb3_seq_done(rqct_ops*); ++static int msb3_seq_conf(rqct_ops*); ++static int msb3_enc_conf(rqct_ops*, mhve_job*); ++static int msb3_enc_done(rqct_ops*, mhve_job*); ++static void msb3_release(rqct_ops*); ++ ++static int _msb3_compute_qs(mfe_msb3* msb3, int frm_type); ++static int _msb3_qp_init(mfe_msb3* msb3); ++static int _msb3_qp_update_max(mfe_msb3* msb3, int frm_type); ++static int _msb3_qp_fit_in_range(mfe_msb3* msb3, int frm_type); ++static int _msb3_get_qp_upper(int frm_type, int bps, int fps_by_10, int pixels ); ++ ++static int qp2qs(int QP); ++static int qs2qp(int qsx32); ++ ++/************************************************************************/ ++/* Functions */ ++/************************************************************************/ ++ ++ ++static void ++msb3_print_version(void) ++{ ++ printk("RATECTL_VER: [%s] %d.%d %s\n", RC_MODULE_NAME, RC_MODULE_VER_MAJOR, ++ RC_MODULE_VER_MINOR, RC_MODULE_VER_TEST ); ++} ++ ++char* msb3_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d-%02d:enhanced msbr.",MSBR_NAME,MSBR_VER_MJR,MSBR_VER_MNR,MSBR_VER_EXT); ++ return line; ++} ++ ++void* msb3_allocate(void) ++{ ++ rqct_ops* rqct; ++ ++ if (NULL != (rqct = MEM_ALLC(sizeof(mfe_msb3)))) ++ { ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ MEM_COPY(rqct->name, MSBR_NAME, 5); ++ rqct->seq_sync = msb3_seq_sync; ++ rqct->seq_done = msb3_seq_done; ++ rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->seq_conf = msb3_seq_conf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = msb3_enc_conf; ++ rqct->enc_done = msb3_enc_done; ++ rqct->release = msb3_release; ++ ++ rqcx->attr.i_method = RQCT_METHOD_CQP; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = 3; ++ rqcx->attr.i_upperq = 48; ++ rqcx->attr.i_lowerq = 12; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.i_btrate = 0; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->i_config = 0; ++ rqcx->i_pcount = 0; ++ rqcx->i_period = 0; ++ } ++ ++ return rqct; ++} ++ ++ ++static void msb3_release(rqct_ops* rqct) ++{ ++ MEM_FREE(rqct); ++} ++ ++static int msb3_seq_done(rqct_ops* rqct) ++{ ++ ++ /* Debug print */ ++ #if DBG_PRINT_ENABLE ++ { ++ mfe_msb3* msb3 = (mfe_msb3*)rqct; ++ ++ MSBR_DBG( "m_bpf %d %d %d \n", msb3->m_bpf[0], msb3->m_bpf[1], msb3->m_bpf[2] ); ++ } ++ #endif ++ ++ /* call seq_done() */ ++ return 0; ++} ++ ++static int msb3_seq_sync(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ rqcx->i_pcount = 0; ++ return 0; ++} ++ ++static int msb3_seq_conf(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_msb3* msb3 = (mfe_msb3*)rqcx; ++ int i; ++ ++ msb3_print_version(); ++ ++ msb3->i_method = (int)rqcx->attr.i_method; ++ msb3->i_leadqp = rqcx->attr.i_leadqp; ++ msb3->i_deltaq = rqcx->attr.i_deltaq; ++ msb3->i_btrate = rqcx->attr.i_btrate; ++ msb3->i_pixels = (int)rqcx->attr.i_pict_w * (int)rqcx->attr.i_pict_h; ++ msb3->n_fmrate = (int)rqcx->attr.n_fmrate; ++ msb3->d_fmrate = (int)rqcx->attr.d_fmrate; ++ msb3->i_fmrate = msb3->n_fmrate / msb3->d_fmrate; ++ msb3->i_maxbps = 0; ++ ++ rqcx->i_period = rqcx->attr.i_period; ++ ++ if (msb3->i_method == RQCT_METHOD_CBR) ++ { ++ msb3->i_levelq = rqcx->attr.i_leadqp; ++ msb3->i_smooth = rqcx->i_period; ++ msb3->i_frmbit = (int)div_s64((int64)msb3->i_btrate*msb3->d_fmrate,msb3->n_fmrate); ++ msb3->i_pixbit = (int)div_s64((int64)msb3->i_frmbit*BPP_FAC,msb3->i_pixels); ++ msb3->i_gopbit = rqcx->i_period*msb3->i_frmbit; ++ msb3->i_bucket = msb3->i_frmbit*msb3->i_smooth; ++ msb3->i_missed = msb3->i_bucket/4; ++ msb3->i_bitpos = msb3->i_bucket/4; ++ msb3->i_dqbias = msb3->i_levelq-42; ++ iir_init(&msb3->iir_rqprod[RQCT_PICTYP_I], COMPLEXITY_I, KAPA_ONE*3/4); ++ iir_init(&msb3->iir_rqprod[RQCT_PICTYP_P], COMPLEXITY_P, KAPA_ONE*2/4); ++ acc_init(&msb3->acc_rqprod, COMPLEXITY_P); ++ acc_init(&msb3->acc_bitcnt, msb3->i_frmbit*3/4); ++ if (msb3->i_levelq < 0) ++ msb3->i_levelq = 30; ++ rqcx->i_pcount = rqcx->i_period; ++ return 0; ++ } ++ ++ // more bitrate checking ++ if (msb3->i_method == CONSTRAINED_VBR) ++ { ++ if (msb3->i_maxbps == 0) ++ msb3->i_maxbps = (int)((msb3->i_btrate*14)/10); ++ ++ msb3->i_max_offset = (int)div_s64((int64)(msb3->i_maxbps-msb3->i_btrate)*msb3->d_fmrate,msb3->n_fmrate); ++ ++ if (!(rqcx->i_config&RCTL_CFG_MB_DQP)) ++ msb3->i_max_offset = (msb3->i_max_offset) >> 2; ++ } ++ else ++ msb3->i_maxbps = 0; // Don't care ++ ++ msb3->i_avgbpf = (int)div_s64((int64)msb3->i_btrate*msb3->d_fmrate,msb3->n_fmrate); ++ ++ if (rqcx->i_period > 0) ++ { ++ int length = rqcx->i_period; ++ int weight = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_period-1); ++ msb3->m_bpf[0] = (int)div64_s64((int64)msb3->i_btrate*msb3->d_fmrate*IFRAME_WEIGHT*length, (int64)weight*msb3->n_fmrate); ++ msb3->m_bpf[1] = (int)div64_s64((int64)msb3->i_btrate*msb3->d_fmrate*PFRAME_WEIGHT*length, (int64)weight*msb3->n_fmrate); ++ msb3->m_bpf[2] = (int)div64_s64((int64)msb3->i_btrate*msb3->d_fmrate*BFRAME_WEIGHT*length, (int64)weight*msb3->n_fmrate); ++ ++ } ++ else ++ { ++ msb3->m_bpf[0] = (int)div64_s64((int64)msb3->i_btrate*msb3->d_fmrate*IFRAME_WEIGHT, (int64)PFRAME_WEIGHT*msb3->n_fmrate); ++ msb3->m_bpf[1] = (int)div64_s64((int64)msb3->i_btrate*msb3->d_fmrate,msb3->n_fmrate); ++ msb3->m_bpf[2] = msb3->m_bpf[1]; ++ } ++ ++ _msb3_qp_init(msb3); ++ ++ // Init frame number in Gop ++ rqcx->i_pcount = rqcx->i_period; ++ msb3->i_totbit = 0; ++ ++ // Bitrate usage monitoring ++ msb3->i_smooth_min = (msb3->n_fmrate*SMOOTH_SECOND_CBR)/msb3->d_fmrate/SMOOTH_BASE; ++ ++ switch (msb3->i_method) ++ { ++ case RQCT_METHOD_VBR: ++ msb3->i_smooth_cnt = (msb3->n_fmrate*SMOOTH_SECOND_VBR)/msb3->d_fmrate/SMOOTH_BASE; ++ ++ msb3->i_vbv_target = msb3->i_btrate * VBV_TGT_LVL_VBR / SMOOTH_BASE; ++ msb3->i_vbv_fullness_low = msb3->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msb3->i_vbv_fullness_high = msb3->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msb3->i_vbv_buf_size = msb3->i_btrate * VBV_BUF_SIZE_VBR / SMOOTH_BASE; ++ ++ break; ++ case CONSTRAINED_VBR: ++ msb3->i_smooth_cnt = (msb3->n_fmrate*SMOOTH_SECOND_CVBR)/msb3->d_fmrate/SMOOTH_BASE; ++ msb3->i_gauge_bgt[0] = msb3->m_bpf[0]; ++ for (i = 1; i < MAX_GAUGE_SIZE; i++) ++ msb3->i_gauge_bgt[i] = msb3->m_bpf[1]; ++ msb3->i_gauge_cnt = msb3->i_fmrate; ++ msb3->i_gauge_idx = 0; ++ msb3->i_gauge_bps = (int)div_s64((int64)msb3->i_btrate*msb3->d_fmrate*msb3->i_gauge_cnt,msb3->n_fmrate); ++ ++ msb3->i_vbv_target = msb3->i_btrate * VBV_TGT_LVL_VBR / SMOOTH_BASE; ++ msb3->i_vbv_fullness_low = msb3->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msb3->i_vbv_fullness_high = msb3->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msb3->i_vbv_buf_size = msb3->i_btrate * VBV_BUF_SIZE_VBR / SMOOTH_BASE; ++ ++ break; ++ case RQCT_METHOD_CBR: ++ default: ++ ++ msb3->i_smooth_cnt = (int)div_s64((int64)msb3->n_fmrate*SMOOTH_SECOND_CBR,msb3->d_fmrate*SMOOTH_BASE); ++ msb3->i_vbv_target = msb3->i_btrate * VBV_TGT_LVL_CBR / SMOOTH_BASE; ++ msb3->i_vbv_fullness_low = msb3->i_btrate * VBV_FUL_LOW_CBR / SMOOTH_BASE; ++ msb3->i_vbv_fullness_high = msb3->i_btrate * VBV_FUL_LOW_CBR / SMOOTH_BASE; ++ msb3->i_vbv_buf_size = msb3->i_btrate * VBV_BUF_SIZE_CBR / SMOOTH_BASE; ++ ++ break; ++ } ++ ++ msb3->i_vbv_fullness = msb3->i_vbv_target; ++ msb3->i_vbv_real_fullness = msb3->i_vbv_target; ++ ++ MSBR_DBG( "conf i_vbv_fullness = %d\n", msb3->i_vbv_fullness); ++ ++ msb3->i_thr_qp_frameskip = THR_QP_FRAMESKIP; ++ msb3->i_frm_nr = 0; ++ msb3->i_last_avg_qs = msb3->i_last_frm_bs = 0; ++ msb3->i_lt_qs64 = 0; ++ ++ // Init var ++ for( i=0; ii_last_enc_qs = 0; ++ msb3->i_last_enc_qp = 0; ++ ++ msb3->i_last_qp[i] = 0; ++ msb3->i_last_qs[i] = 0; ++ msb3->i_last_tgt_size[i] = 0; ++ msb3->i_last_frm_size[i] = 0; ++ /* ++ msb3->i_last_qp[i] = msb3->i_init_qp[i]; ++ msb3->i_last_qs[i] = qp2qs( msb3->i_init_qp[i]); ++ msb3->i_last_tgt_size[i] = msb3->m_bpf[i]; ++ msb3->i_last_frm_size[i] = msb3->m_bpf[i]; ++ */ ++ } ++ ++ return 0; ++} ++ ++/* ++ Get smooth count ++*/ ++static int _msb3_get_smooth_count(mfe_msb3* msb3) ++{ ++ int smooth_cnt = 0; ++ if (msb3->i_frm_nr > msb3->i_smooth_cnt*SMOOTH_FACTOR_MIN/SMOOTH_BASE) ++ smooth_cnt = msb3->i_smooth_cnt; ++ else if (msb3->i_frm_nr < msb3->i_smooth_min) ++ smooth_cnt = msb3->i_smooth_min; ++ else ++ { ++ int fact_n = msb3->i_smooth_cnt - msb3->i_smooth_min; ++ int fact_d = msb3->i_smooth_cnt * SMOOTH_FACTOR_MIN/SMOOTH_BASE - msb3->i_smooth_min; ++ smooth_cnt = msb3->i_smooth_min + (msb3->i_frm_nr - msb3->i_smooth_min) * fact_n / fact_d; ++ } ++ ++ return smooth_cnt; ++} ++ ++static int _msb3_calculate_delta(mfe_msb3* msb3, int smooth_cnt, int frm_type) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)msb3; ++ ++ int delta = 0; ++ ++ ++ #if ( CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES != 0 ) ++ if(msb3->i_frm_nr < CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ) ++ { ++ msb3->i_vbv_fullness = msb3->i_vbv_target; ++ ++ return 0; ++ } ++ #endif //CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ++ ++ #if CFG_VBV_BUF_UNDERFLOW_RESET ++ ++ /* reset if under flow */ ++ if( msb3->i_vbv_fullness < 0 ) ++ { ++ MSBR_DBG( "reset i_vbv_fullness %d= 0\n", msb3->i_vbv_fullness ); ++ msb3->i_vbv_fullness = 0; ++ } ++ #endif //CFG_VBV_BUF_UNDERFLOW_RESET ++ ++ #if CFG_VBV_BUF_OVERFLOW_RESET ++ ++ if( msb3->i_vbv_fullness > msb3->i_vbv_buf_size ) ++ { ++ MSBR_DBG( "reset i_vbv_fullness %d= %d\n", msb3->i_vbv_fullness, msb3->i_vbv_buf_size ); ++ msb3->i_vbv_fullness = msb3->i_vbv_buf_size; ++ } ++ ++ #endif //CFG_VBV_BUF_OVERFLOW_RESET ++ ++ if (msb3->i_method == RQCT_METHOD_CBR) ++ { ++ delta = (int)div_s64((int64)(msb3->i_vbv_fullness-msb3->i_vbv_target)*msb3->d_fmrate,msb3->n_fmrate*SMOOTH_SECOND_CBR/SMOOTH_BASE); ++ MSBR_DBG( "i_vbv_fullness %d i_vbv_target %d delta = %d\n", msb3->i_vbv_fullness, msb3->i_vbv_target,delta ); ++ ++ #if( CFG_RC_DELTA_CACULATE_METHOD == RDC_WEIGHTED_DIVIDED ) ++ { ++ int wp[MAX_FRAME_TYPE] = {IFRAME_WEIGHT,PFRAME_WEIGHT,BFRAME_WEIGHT}; ++ int w = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_period-1); ++ int n = rqcx->i_period; ++ ++ // Multiply the ratio of the frame type ++ delta = delta* n * wp[frm_type] / w; ++ MSBR_DBG( "Adjust delta = %d\n", delta ); ++ } ++ #endif //CFG_RC_DELTA_CACULATE_METHOD ++ ++ } ++ else if (msb3->i_method == CONSTRAINED_VBR) ++ { ++ delta = (msb3->i_vbv_fullness - msb3->i_vbv_target) / smooth_cnt; ++ if (delta < -msb3->i_max_offset) ++ delta = -msb3->i_max_offset; ++ } ++ else if (msb3->i_method == RQCT_METHOD_VBR) ++ { ++ delta = (msb3->i_vbv_fullness - msb3->i_vbv_target) / smooth_cnt; ++ if (delta > 0 && (msb3->i_last_avg_qs*64) > msb3->i_lt_qs64) ++ delta = delta>>1; // Make it more variable bitrate to allow better quality ++ } ++ ++ return delta; ++} ++ ++ ++/* Return target QPStep */ ++static int _msb3_compute_qs(mfe_msb3* msb3, int frm_type) ++{ ++ mfe_rctl* rqcx = &msb3->rqcx; ++ int newqs = 0; ++ int adjust; ++ int bitrate = msb3->i_btrate; ++ int fps_den = msb3->d_fmrate; ++ int fps_num = msb3->n_fmrate; ++ int mb_numb = msb3->i_pixels>>8; ++ ++ // For the very first frame, guess one qp! ++ if (msb3->i_frm_nr == 0 || ++ msb3->i_last_qp[frm_type] == 0 ) ++ { ++ int bpMBK, newqp; ++ if (msb3->i_method == RQCT_METHOD_CQP) ++ { ++ newqp = msb3->i_leadqp; ++ newqs = qp2qs(newqp); // So that frame qp will be exactly msb3->i_qp ++ } ++ else ++ { ++ // bits per MB ++ bpMBK = (int)div_s64((int64)bitrate*fps_den*100,mb_numb*fps_num)+1; ++ newqp = INIT_QP_OFFSET + ( ( INIT_QP_FACTOR*100) / (bpMBK) ); ++ ++ if (newqp < MIN_INIT_QP) ++ newqp = MIN_INIT_QP; ++ if (newqp > MAX_INIT_QP) ++ newqp = MAX_INIT_QP; ++ newqs = newqp << QS_SHIFT_FACTOR; ++ } ++ ++ msb3->i_frozen = newqp >> 1; ++ ++ if (msb3->i_frozen > 15) ++ msb3->i_frozen = 15; ++ ++ return newqs; ++ } ++ ++ if (msb3->i_method == RQCT_METHOD_CQP) ++ return qp2qs(rqcx->rqct.i_enc_qp); ++ ++ if (msb3->i_method == RQCT_METHOD_CBR) ++ { ++ ++#if 1 ++ int dqs; ++ int last_size,tgt_size; ++ ++ last_size = msb3->i_last_frm_size[frm_type]; ++ ++ #if (CFG_LAST_QS_SELECTION == LQS_USE_LAST_SET_QS ) ++ newqs = msb3->i_last_enc_qs; ++ #elif (CFG_LAST_QS_SELECTION == LQS_USE_LAST_FRM_TYPE_SET_QS ) ++ newqs = msb3->i_last_qs[frm_type]; ++ #elif (CFG_LAST_QS_SELECTION == LQS_USE_LAST_AVG_ENC_QS ) ++ newqs = msb3->i_last_avg_qs; ++ #else ++ newqs = msb3->i_last_enc_qs; ++ #endif ++ ++ dqs = newqs / 8; ++ tgt_size = msb3->i_tgt_bs; ++ ++ MSBR_DBG( "newqs = %d dqs = %d last_size %d tgt_size %d\n", newqs, dqs, last_size, tgt_size); ++ ++ if( tgt_size > MSRC_PERCENT( 160, last_size) ) ++ { ++ newqs = newqs - dqs*2; ++ MSBR_DBG( "newqs-- = %d \n", newqs ); ++ } ++ else if( tgt_size > MSRC_PERCENT( 113, last_size) ) ++ { ++ newqs = newqs - dqs*1; ++ MSBR_DBG( "newqs- = %d \n", newqs ); ++ } ++ else if( tgt_size < MSRC_PERCENT( 60, last_size) ) ++ { ++ newqs = newqs + dqs*2; ++ MSBR_DBG( "newqs++ = %d \n", newqs ); ++ } ++ else if( tgt_size < MSRC_PERCENT( 87, last_size) ) ++ { ++ newqs = newqs + dqs*1; ++ MSBR_DBG( "newqs+ = %d \n", newqs ); ++ } ++ else ++ { ++ MSBR_DBG( "newqs~ = %d \n", newqs ); ++ } ++ ++#else ++ int frm_cnt = msb3->i_frm_nr; ++ int frames_left; ++ int buf_rest_pic; ++ int64 buf_rest; ++ ++ int dqp; ++ buf_rest = div_s64((int64)frm_cnt*fps_den*bitrate,fps_num); ++ buf_rest+= (SMOOTH_PERIOD*msb3->i_btrate) - msb3->i_totbit; ++ newqs = msb3->i_last_avg_qs; ++ frames_left = (SMOOTH_PERIOD * msb3->n_fmrate) / msb3->d_fmrate; ++ buf_rest_pic = (int)div_s64(buf_rest,frames_left); ++ dqp = msb3->i_last_avg_qs/8; ++ ++ if (msb3->i_last_frm_bs > (buf_rest_pic*9)>>3) ++ newqs = msb3->i_last_avg_qs + dqp; ++ else if (msb3->i_last_frm_bs < (buf_rest_pic*7)>>3) ++ newqs = msb3->i_last_avg_qs - dqp; ++#endif ++ ++ } ++ else if (msb3->i_method == CONSTRAINED_VBR) ++ { ++ int lo_qs, hi_qs; ++ adjust = msb3->i_lt_qs64>>2; ++ lo_qs = (msb3->i_lt_qs64 - adjust) >> 6; ++ hi_qs = (msb3->i_lt_qs64 + adjust) >> 6; ++ if (rqcx->i_period > 1 && IS_IPIC(rqcx->rqct.i_pictyp)) ++ { ++ newqs = msb3->i_last_avg_qs; ++ if (msb3->i_gauge_bps < msb3->i_btrate) ++ newqs = newqs-(1<i_lt_qs64 * div_s64(msb3->i_totbit,msb3->i_frm_nr), msb3->i_tgt_bs) ; ++ //MFE_ASSERT((tmp >> 6) < (1<<31)); ++ newqs = (int)(div_s64((int64)msb3->i_lt_qs64 * div_s64(msb3->i_totbit,msb3->i_frm_nr),msb3->i_tgt_bs)>>6) ; ++ if (msb3->i_last_frm_bs>msb3->i_last_tgt_bs) ++ { ++ adjust = ((msb3->i_last_frm_bs-msb3->i_last_tgt_bs)/msb3->i_max_offset) + (1< (3<i_last_avg_qs*64) > msb3->i_lt_qs64) ++ { ++ // Danger! Make it more aggressive ++ hi_qs = msb3->i_last_avg_qs + adjust; ++ newqs = msb3->i_last_avg_qs + adjust; ++ } ++ else ++ { ++ hi_qs += adjust; ++ newqs += adjust; ++ } ++ } ++ else if (msb3->i_gauge_bps > msb3->i_btrate) ++ { ++ if (msb3->i_last_avg_qs > newqs) ++ newqs = msb3->i_last_avg_qs; ++ if (msb3->i_lt_qs64 > (newqs*64)) ++ newqs = msb3->i_lt_qs64/64; ++ } ++ else ++ { ++ if ((newqs<<6) >= msb3->i_lt_qs64) ++ newqs = (msb3->i_lt_qs64/64)-1; ++ if (msb3->i_vbv_target>msb3->i_vbv_fullness) ++ { ++ adjust = (msb3->i_vbv_target - msb3->i_vbv_fullness) / (int)msb3->i_btrate; ++ newqs -= adjust; ++ } ++ } ++ } ++ newqs = MSRC_MIN(hi_qs, newqs); ++ newqs = MSRC_MAX(lo_qs, newqs); ++ } ++ else if (msb3->i_method == RQCT_METHOD_VBR) ++ { ++ int lo_qs, hi_qs; ++ if (rqcx->i_period > 1 && IS_IPIC(rqcx->rqct.i_pictyp)) ++ { ++ newqs = msb3->i_last_avg_qs; ++ if ((msb3->i_last_avg_qs*64) > msb3->i_lt_qs64) ++ newqs = newqs - (1<i_frm_nr >= msb3->i_fmrate || rqcx->i_period == 1) ++ { ++ //int64 tmp = div_s64((int64)msb3->i_lt_qs64*div_s64(msb3->i_totbit,msb3->i_frm_nr),msb3->i_avgbpf); ++ //MFE_ASSERT((tmp >> 6) < (1<<31)); ++ adj_ltq = (int)(div_s64((int64)msb3->i_lt_qs64*div_s64(msb3->i_totbit,msb3->i_frm_nr),msb3->i_avgbpf)>>6); ++ } ++ else ++ { ++ adj_ltq = msb3->i_lt_qs64/64; // Wait for stabilization ++ } ++ MFE_ASSERT(msb3->i_tgt_bs>0); ++ newqs = (adj_ltq * msb3->i_avgbpf) / msb3->i_tgt_bs; ++ ++ adjust = MSRC_MAX((2<>2); ++ lo_qs = adj_ltq - adjust; ++ hi_qs = adj_ltq + adjust; ++ ++ if (msb3->i_last_frm_bs > msb3->i_last_tgt_bs) ++ { ++ adjust = (int)(msb3->i_last_frm_bs/msb3->i_last_tgt_bs); ++ if (adjust > 2) ++ adjust = 2; ++ hi_qs += adjust; ++ } ++ ++ if (msb3->i_avgbpf > msb3->i_tgt_bs) ++ newqs = MSRC_MIN(hi_qs,newqs); ++ else ++ newqs = MSRC_MAX(lo_qs,newqs); ++ } ++ } ++ ++ return newqs; ++} ++ ++ ++static int msb3_enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ mfe_msb3* msb3 = (mfe_msb3*)rqcx; ++ int frm_type; ++ int delta = 0; ++ int init_frames = 0; ++ ++ if (msb3->i_method == RQCT_METHOD_CBR) ++ { ++ do ++ { ++ int qstep, bppix, btpos, dqoff; ++ if (IS_IPIC(rqct->i_pictyp)) ++ { ++ int Xi = iir_data(&msb3->iir_rqprod[RQCT_PICTYP_I]); ++ int Xp = acc_calc(&msb3->acc_rqprod, rqcx->i_period) / rqcx->i_period; ++ int Ri = (int)div_s64((int64)qp2qs(40+msb3->i_deltaq)*IPR_FAC,qp2qs(40)); ++ int Rp = (int)div_s64((int64)Xp*IPR_FAC,Xi); ++ msb3->i_budget = (int)div_s64((int64)msb3->i_gopbit*Ri,(rqcx->i_period*Rp+Ri-Rp)); ++ bppix = (int)div_s64((int64)msb3->i_budget*BPP_FAC,msb3->i_pixels); ++ qstep = Xi/bppix; ++ msb3->i_ipbias = 0; ++ msb3->i_btbias = 0; ++ if (rqcx->i_period > 1) ++ msb3->i_ipbias = (msb3->i_budget-msb3->i_frmbit)/(rqcx->i_period-1); ++ rqct->i_enc_qp = qs2qp(qstep); ++ break; ++ } ++ btpos = msb3->i_missed; ++ dqoff = qs2qp(((int)div_s64((int64)btpos*qp2qs(46),msb3->i_bucket)))-34; ++ btpos-= msb3->i_bucket/4; ++ msb3->i_budget = msb3->i_frmbit-msb3->i_ipbias-(btpos/msb3->i_smooth); ++ msb3->i_budget = _MAX(msb3->i_budget,msb3->i_frmbit/16); ++ msb3->i_levelq+= dqoff-msb3->i_dqbias; ++ msb3->i_dqbias = dqoff; ++ rqct->i_enc_qp = _MIN(51,msb3->i_levelq); ++ msb3->i_dqbias+= rqct->i_enc_qp-msb3->i_levelq; ++ msb3->i_levelq = rqct->i_enc_qp; ++ } ++ while (0); ++ mrqc_roi_draw(rqct, mjob); ++ regs->reg00_g_mbr_en = 0; ++ regs->reg26_s_mbr_pqp_dlimit = LF_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = UP_QP_DIFF_LIMIT; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = 0; ++ regs->reg26_s_mbr_tmb_bits = 0; ++ regs->reg2a_s_mbr_qp_min = 0; ++ regs->reg2a_s_mbr_qp_max = 0; ++ regs->reg6e_s_mbr_qstep_min = 0; ++ regs->reg6f_s_mbr_qstep_max = 0; ++ return 0; ++ } ++ ++ frm_type = rqct->i_pictyp; ++ ++ if( rqcx->i_period > 1 ) ++ { ++ // The number of P frames in GOP is not zero. ++ init_frames = 1; ++ } ++ ++ #if (CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES != 0 ) ++ init_frames = CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES; ++ #endif //CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ++ ++ // Target frame bitcount ++ if (msb3->i_frm_nr > init_frames) ++ { ++ int smooth_cnt = 0; ++ // 1. Determine the number of future frame to compensate for current bitrate mismatch. ++ smooth_cnt = _msb3_get_smooth_count(msb3); ++ ++ // 2. Calculate the bitcount that this frame should be compensate for. ++ delta = _msb3_calculate_delta( msb3, smooth_cnt, frm_type); ++ ++ // 3. Finally, calculate the target bitcount. ++ msb3->i_tgt_bs = msb3->m_bpf[frm_type] - delta; ++ ++ ++ // 4. Clip the target size to 70% ~ 130% ++ msb3->i_tgt_bs = MSRC_FIT_IN_RANGE( msb3->i_tgt_bs ++ ,MSRC_PERCENT ( 70, msb3->m_bpf[frm_type]) ++ ,MSRC_PERCENT (130, msb3->m_bpf[frm_type])); ++ ++ } ++ else ++ { ++ // The first I frame and the first P frame use the default value. ++ msb3->i_tgt_bs = msb3->m_bpf[frm_type]; ++ } ++ ++ /* Update max min qp value */ ++ _msb3_qp_update_max(msb3, frm_type); ++ /* Return initial frame QP */ ++ msb3->i_this_enc_qs = _msb3_compute_qs(msb3, frm_type); ++ rqct->i_enc_qp = qs2qp(msb3->i_this_enc_qs); ++ ++ MSBR_DBG( "Qp = %d qs = %d ls %d tg %d <%d:%d> dt %d\n", rqcx->rqct.i_enc_qp , msb3->i_this_enc_qs, msb3->i_last_frm_size[frm_type], msb3->i_tgt_bs ++ , msb3->i_frm_nr, frm_type,delta); ++ ++ /* Clip qs and qp value in range */ ++ _msb3_qp_fit_in_range(msb3, frm_type); ++ ++ msb3->i_last_avg_qs = 0; ++ msb3->i_last_frm_bs = 0; ++ ++ msb3->i_tgt_mb = (int)div_s64((int64)msb3->i_tgt_bs*256,msb3->i_pixels); ++ ++ if (msb3->i_tgt_mb < 1) ++ msb3->i_tgt_mb = 1; ++ ++ switch (msb3->i_method) ++ { ++ case RQCT_METHOD_CBR: ++ rqcx->i_config |= RCTL_CFG_MB_DQP; ++ ++ #if CFG_CBR_IFRAME_CQP ++ if( frm_type == 0 ) ++ rqcx->i_config&=~RCTL_CFG_MB_DQP; ++ #endif ++ ++ #if CFG_CBR_PFRAME_CQP ++ if( frm_type != 0 ) ++ rqcx->i_config&=~RCTL_CFG_MB_DQP; ++ #endif ++ ++ break; ++ case CONSTRAINED_VBR: ++ case RQCT_METHOD_VBR: ++ rqcx->i_config|= RCTL_CFG_MB_DQP; ++ break; ++ case RQCT_METHOD_CQP: ++ rqcx->i_config&=~RCTL_CFG_MB_DQP; ++ break; ++ default: ++ rqcx->i_config|= RCTL_CFG_MB_DQP; ++ break; ++ } ++ ++ mrqc_roi_draw(rqct, mjob); ++ ++ regs->reg00_g_mbr_en = !rqcx->attr.b_dqmstat && (msb3->i_method!=RQCT_METHOD_CQP); ++ regs->reg26_s_mbr_pqp_dlimit = LF_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = UP_QP_DIFF_LIMIT; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = msb3->i_this_enc_qs; ++ regs->reg26_s_mbr_tmb_bits = msb3->i_tgt_mb; ++ regs->reg2a_s_mbr_qp_min = msb3->i_this_min_qp; ++ regs->reg2a_s_mbr_qp_max = msb3->i_this_max_qp; ++ regs->reg6e_s_mbr_qstep_min = msb3->i_this_min_qs; ++ regs->reg6f_s_mbr_qstep_max = msb3->i_this_max_qs; ++ ++ return 0; ++} ++ ++static int msb3_enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_msb3* msb3 = (mfe_msb3*)rqcx; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ int frm_type; ++ int mbs = (msb3->i_pixels>>8), bps; ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ msb3->i_avg_qs = regs->sumofq / (mbs-1); ++ ++ rqct->i_enc_bs += rqct->i_bitcnt/8; ++ rqct->i_enc_nr++; ++ ++ acc_push(&msb3->acc_bitcnt, rqct->i_bitcnt); ++ bps = acc_calc(&msb3->acc_bitcnt, rqcx->i_period); ++ bps = (int)div_s64((int64)bps*msb3->n_fmrate,msb3->d_fmrate*rqcx->i_period); ++ ++ if (msb3->i_method == RQCT_METHOD_CBR) ++ { ++ int bpp = (int)div_s64((int64)rqct->i_bitcnt*BPP_FAC,msb3->i_pixels); ++ int cpx = bpp * qp2qs(rqct->i_enc_qp); ++ ++ if (IS_PPIC(rqct->i_pictyp)) ++ { ++ acc_push(&msb3->acc_rqprod, cpx); ++ iir_push(&msb3->iir_rqprod[RQCT_PICTYP_P], acc_calc(&msb3->acc_rqprod, 8) / 8); ++ msb3->i_missed += (rqct->i_bitcnt - msb3->i_frmbit + msb3->i_btbias); ++ } ++ else ++ { ++ iir_push(&msb3->iir_rqprod[RQCT_PICTYP_I], cpx); ++ msb3->i_missed = msb3->i_bitpos; ++ if (rqcx->i_period > 1) ++ msb3->i_btbias = (rqct->i_bitcnt - msb3->i_frmbit) / (rqcx->i_period - 1); ++ } ++ msb3->i_bitpos += (rqct->i_bitcnt - msb3->i_frmbit); ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d bps:%8d",\ ++ rqct->name,rqct->i_enc_nr,IS_IPIC(rqct->i_pictyp)?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt,bps); ++#if defined(LOG_MSG) ++ printk("%s\n",rqct->print_line); ++#endif ++ return 0; ++ } ++ ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d bps:%8d",\ ++ rqct->name,rqct->i_enc_nr,IS_IPIC(rqct->i_pictyp)?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt,bps); ++#if defined(LOG_MSG) ++ printk("%s\n",rqct->print_line); ++#endif ++ frm_type = rqct->i_pictyp; ++ ++ // update counter ++ msb3->i_totbit += rqct->i_bitcnt; ++ msb3->i_frm_nr++; ++ ++ MSBR_DBG( "conf i_vbv_fullness %d + bitcnt %d= ", msb3->i_vbv_fullness, rqct->i_bitcnt ); ++ ++ msb3->i_vbv_fullness += rqct->i_bitcnt; ++ msb3->i_vbv_real_fullness += rqct->i_bitcnt; ++ ++ MSBR_DBG( "%d\n", msb3->i_vbv_fullness ); ++ ++ ++ msb3->i_last_frm_bs = rqct->i_bitcnt; ++ msb3->i_last_tgt_bs = msb3->i_tgt_bs; ++ ++ msb3->i_last_enc_qs = msb3->i_this_enc_qs; ++ msb3->i_last_enc_qp = rqct->i_enc_qp; ++ ++ msb3->i_last_qs[frm_type] = msb3->i_this_enc_qs; ++ msb3->i_last_qp[frm_type] = rqct->i_enc_qp; ++ msb3->i_last_tgt_size[frm_type] = msb3->i_tgt_bs; ++ msb3->i_last_frm_size[frm_type] = rqct->i_bitcnt; ++ ++#if defined(MMFE_RCTL_PATCH) ++ if (msb3->i_avg_qs <(msb3->i_this_enc_qs/2)) ++ msb3->i_avg_qs = msb3->i_this_enc_qs; ++ if (msb3->i_avg_qs > msb3->i_this_max_qs) ++ msb3->i_avg_qs = msb3->i_this_max_qs; ++#endif ++ ++ msb3->i_last_avg_qs = msb3->i_avg_qs; ++ // Variable bitrate ++ if (msb3->i_method == RQCT_METHOD_VBR) ++ msb3->i_lt_qs64 += ((msb3->i_last_avg_qs*64)-msb3->i_lt_qs64) / msb3->i_frm_nr; ++ else if (msb3->i_method == CONSTRAINED_VBR) ++ { ++ if (msb3->i_frm_nr == 1) ++ msb3->i_lt_qs64 = msb3->i_last_avg_qs*64; ++ else ++ msb3->i_lt_qs64 = (msb3->i_lt_qs64*(msb3->i_smooth_cnt-1) + (msb3->i_last_avg_qs*64)) / msb3->i_smooth_cnt; ++ } ++ ++ if (msb3->i_method == CONSTRAINED_VBR) ++ { ++ msb3->i_gauge_bps -= msb3->i_gauge_bgt[msb3->i_gauge_idx]; ++ msb3->i_gauge_bps += rqct->i_bitcnt; ++ msb3->i_gauge_bgt[msb3->i_gauge_idx] = rqct->i_bitcnt; ++ msb3->i_gauge_idx++; ++ if (msb3->i_gauge_idx == msb3->i_gauge_cnt) ++ msb3->i_gauge_idx = 0; ++ } ++ ++ /* Update VBV buffer status */ ++ ++ #if ( CFG_VBV_FRAME_QUOTA_METHOD == VFQ_USE_AVERAGE_SIZE ) ++ ++ MSBR_DBG( "conf i_vbv_fullness %d - i_avgbpf %d= ", msb3->i_vbv_fullness, msb3->i_avgbpf ); ++ msb3->i_vbv_fullness -= msb3->i_avgbpf; ++ msb3->i_vbv_real_fullness -= msb3->i_avgbpf; ++ ++ #elif ( CFG_VBV_FRAME_QUOTA_METHOD == VFQ_USE_WEIGHTED_SIZE ) ++ ++ MSBR_DBG( "conf i_vbv_fullness %d - i_avgbpf %d= ", msb3->i_vbv_fullness, msb3->m_bpf[frm_type] ); ++ msb3->i_vbv_fullness -= msb3->m_bpf[frm_type]; ++ msb3->i_vbv_real_fullness -= msb3->m_bpf[frm_type]; ++ ++ #else // ++ ++ msb3->i_vbv_fullness -= msb3->i_avgbpf; ++ msb3->i_vbv_real_fullness -= msb3->i_avgbpf; ++ ++ #endif //VFQ_USE_WEIGHTED_SIZE ++ ++ MSBR_DBG( "%d\n", msb3->i_vbv_fullness); ++ ++ return 0; ++} ++/* ++static int qp2qs(int qp) ++{ ++ int i; ++ int qs; ++ static const int QP2QSTEP[6] = { 20, 22, 26, 28, 32, 36 }; ++ ++ qs = QP2QSTEP[qp%6]; ++ ++ for (i = 0; i < (qp/6); i++) ++ qs*=2; ++ ++ return qs; ++} ++ ++static int qs2qp(int qsx32) ++{ ++ int q_per = 0, q_rem = 0; ++ ++ while (qsx32 > qp2qs(5)) ++ { ++ qsx32 >>= 1; ++ q_per += 1; ++ } ++ ++ if (qsx32 <= 21) ++ { ++ qsx32 = 20; ++ q_rem = 0; ++ } ++ else if (qsx32 <= 24) ++ { ++ qsx32 = 22; ++ q_rem = 1; ++ } ++ else if (qsx32 <= 27) ++ { ++ qsx32 = 26; ++ q_rem = 2; ++ } ++ else if (qsx32 <= 30) ++ { ++ qsx32 = 28; ++ q_rem = 3; ++ } ++ else if (qsx32 <= 34) ++ { ++ qsx32 = 32; ++ q_rem = 4; ++ } ++ else ++ { ++ qsx32 = 36; ++ q_rem = 5; ++ } ++ ++ return (q_per*6 + q_rem); ++} ++*/ ++static int _msb3_qp_init(mfe_msb3* msb3) ++{ ++ int i; ++ // Init with a default value ++ for( i=0; i< MAX_FRAME_TYPE; i++ ) ++ { ++ msb3->i_init_qp[i] = P_FRAME_INIT_QP; ++ msb3->i_min_qp[i] = P_FRAME_MIN_QP; ++ msb3->i_max_qp[i] = P_FRAME_MAX_QP; ++ msb3->i_margin_qp[i] = P_FRAME_MARGIN_QP; ++ } ++ ++ msb3->i_init_qp[RQCT_PICTYP_I] = I_FRAME_INIT_QP; ++ msb3->i_min_qp[RQCT_PICTYP_I] = I_FRAME_MIN_QP; ++ msb3->i_max_qp[RQCT_PICTYP_I] = I_FRAME_MAX_QP; ++ msb3->i_margin_qp[RQCT_PICTYP_I] = I_FRAME_MARGIN_QP; ++ ++ msb3->i_init_qp[RQCT_PICTYP_P] = P_FRAME_INIT_QP; ++ msb3->i_min_qp[RQCT_PICTYP_P] = P_FRAME_MIN_QP; ++ msb3->i_max_qp[RQCT_PICTYP_P] = P_FRAME_MAX_QP; ++ msb3->i_margin_qp[RQCT_PICTYP_P] = P_FRAME_MARGIN_QP; ++ ++ msb3->i_init_qp[RQCT_PICTYP_B] = B_FRAME_INIT_QP; ++ msb3->i_min_qp[RQCT_PICTYP_B] = B_FRAME_MIN_QP; ++ msb3->i_max_qp[RQCT_PICTYP_B] = B_FRAME_MAX_QP; ++ msb3->i_margin_qp[RQCT_PICTYP_B] = B_FRAME_MARGIN_QP; ++ ++ if (msb3->i_method == RQCT_METHOD_VBR) ++ { ++ msb3->i_init_qp[RQCT_PICTYP_I] = msb3->i_leadqp - msb3->i_deltaq; ++ msb3->i_init_qp[RQCT_PICTYP_P] = msb3->i_leadqp; ++ msb3->i_min_qp[RQCT_PICTYP_I] = msb3->rqcx.attr.i_lowerq - msb3->i_deltaq; ++ msb3->i_max_qp[RQCT_PICTYP_I] = msb3->rqcx.attr.i_upperq - msb3->i_deltaq; ++ msb3->i_min_qp[RQCT_PICTYP_P] = msb3->rqcx.attr.i_lowerq; ++ msb3->i_max_qp[RQCT_PICTYP_P] = msb3->rqcx.attr.i_upperq; ++ } ++ ++ return 0; ++} ++ ++static int _msb3_qp_update_max(mfe_msb3* msb3, int frm_type) ++{ ++ int max_qp, min_qp; ++ ++ if( frm_type > MAX_FRAME_TYPE-1 ) frm_type = RQCT_PICTYP_P; ++ ++ min_qp = msb3->i_min_qp[frm_type]; ++ ++/* ++ // Fixed boundaries ++ max_qp = msb3->i_max_qp[frm_type]; ++*/ ++ max_qp = _msb3_get_qp_upper(frm_type, msb3->i_btrate, msb3->i_fmrate*10, msb3->i_pixels ); ++ ++ // Apply into max/min setting ++ msb3->i_this_min_qp = min_qp; ++ msb3->i_this_max_qp = max_qp; ++ msb3->i_this_min_qs = qp2qs(min_qp)-1; ++ msb3->i_this_max_qs = qp2qs(max_qp); ++ ++ return 0; ++} ++ ++static int _msb3_qp_fit_in_range(mfe_msb3* msb3, int frm_type) ++{ ++ mfe_rctl* rqcx = &msb3->rqcx; ++ rqct_ops* rqct = &rqcx->rqct; ++ int max_qp, min_qp; ++ int max_qs, min_qs; ++ ++ if( frm_type > MAX_FRAME_TYPE-1 ) frm_type = RQCT_PICTYP_P; ++ ++ max_qp = msb3->i_max_qp[frm_type] - msb3->i_margin_qp[frm_type]; ++ min_qp = msb3->i_min_qp[frm_type] - msb3->i_margin_qp[frm_type]; ++ ++ min_qs = qp2qs(min_qp )-1; ++ max_qs = qp2qs(max_qp ); ++ ++ msb3->i_this_enc_qs = MSRC_FIT_IN_RANGE(msb3->i_this_enc_qs, min_qs, max_qs ); ++ rqct->i_enc_qp = MSRC_FIT_IN_RANGE(rqct->i_enc_qp, min_qp, max_qp ); ++ ++ return 0; ++} ++ ++ ++static int _msb3_get_qp_upper(int frm_type, int bps, int fps_by_10, int pixels ) ++{ ++ int i; ++ int bpm; ++ int num = 0; ++ int qp; ++ const qp_bound* qp_table; ++ ++ bpm = (int)div64_s64( (int64)(bps*10)< ++ ++#include ++ ++/************************************************************************/ ++/* Macros */ ++/************************************************************************/ ++#define MSBR_VER_EXT 04 ++#define _EXP(expr) #expr ++#define _STR(expr) _EXP(expr) ++#define RC_MODULE_NAME "MSBR" ++#define RC_MODULE_VER_MAJOR 1 ++#define RC_MODULE_VER_MINOR 2 ++#define RC_MODULE_VER_TEST "T"_STR(MSBR_VER_EXT) ++#define MSBR_NAME RC_MODULE_NAME ++#define MSBR_VER_MJR RC_MODULE_VER_MAJOR ++#define MSBR_VER_MNR RC_MODULE_VER_MINOR ++ ++/* Debug related configuration */ ++#define DBG_PRINT_ENABLE 0 ++ ++/* General calculations */ ++#ifndef MSRC_MAX ++#define MSRC_MAX(a,b) (((a)>(b))?(a):(b)) ++#endif ++#ifndef MSRC_MIN ++#define MSRC_MIN(a,b) (((a)<(b))?(a):(b)) ++#endif ++#ifndef MSRC_FIT_IN_RANGE ++#define MSRC_FIT_IN_RANGE(a,low,high) MSRC_MIN(MSRC_MAX((a),(low)),(high)) ++#endif ++ ++#ifndef MSRC_PERCENT ++#define MSRC_PERCENT(percent,a) ( (percent) * (a) / 100 ) ++#endif ++ ++/* Debugging related macro */ ++#if DBG_PRINT_ENABLE ++#define MSBR_DBG printk ++#else ++#define MSBR_DBG(...) ++#endif ++ ++/* Static assert */ ++#define MSBR_SASSERT(EXP,STR) _Static_assert(EXP,STR) ++#define MSBR_ASSERT assert ++#define MFE_ASSERT(p) ++ ++/************************************************************************/ ++/* Configuration */ ++/************************************************************************/ ++ ++/* Skip the first N frames for VBV calculation */ ++#define CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES 50 ++ ++/* The feature to reset the fullness value if fullness overflow or underflow */ ++/* 1 - Enable */ ++/* 0 - Disable */ ++#define CFG_VBV_BUF_OVERFLOW_RESET 1 ++#define CFG_VBV_BUF_UNDERFLOW_RESET 1 ++ ++/* The selection of the rqcx of the new Qs */ ++#define LQS_USE_LAST_SET_QS 0 /* The last frame encode qs setting */ ++#define LQS_USE_LAST_AVG_ENC_QS 1 /* Feed back from HW */ ++#define LQS_USE_LAST_FRM_TYPE_SET_QS 2 /* The last same type frame encode qs setting */ ++#define CFG_LAST_QS_SELECTION LQS_USE_LAST_SET_QS ++ ++/* The choice of the VBV frame quota selection */ ++#define VFQ_USE_AVERAGE_SIZE 0 /* The average size of each frame */ ++#define VFQ_USE_WEIGHTED_SIZE 1 /* The weighted size rqcx on the setting of */ ++ /* IFRAME_WEIGHT, PFRAME_WEIGHT, BFRAME_WEIGHT */ ++ /* and Gop size */ ++#define CFG_VBV_FRAME_QUOTA_METHOD VFQ_USE_WEIGHTED_SIZE ++ ++#define CFG_CBR_IFRAME_CQP 0 /* 0 - Disable, 1 - Enable */ ++#define CFG_CBR_PFRAME_CQP 0 /* 0 - Disable, 1 - Enable */ ++ ++#define RDC_WEIGHTED_DIVIDED 0 ++#define RDC_AVERAGE_DIVIDED 1 ++#define CFG_RC_DELTA_CACULATE_METHOD RDC_WEIGHTED_DIVIDED ++ ++#define QS_SHIFT_FACTOR 5 ++ ++#define UP_QP_DIFF_LIMIT 3 ++#define LF_QP_DIFF_LIMIT 3 ++// Spec limitation is [1,51] ++#define I_FRAME_INIT_QP (30) ++#define I_FRAME_MAX_QP (44) ++#define I_FRAME_MIN_QP (15) ++ ++#define P_FRAME_INIT_QP (35) ++#define P_FRAME_MAX_QP (48) ++#define P_FRAME_MIN_QP (15) ++ ++#define B_FRAME_INIT_QP (P_FRAME_INIT_QP) ++#define B_FRAME_MAX_QP (P_FRAME_MAX_QP) ++#define B_FRAME_MIN_QP (P_FRAME_MIN_QP) ++ ++#define I_FRAME_MARGIN_QP (0) ++#define P_FRAME_MARGIN_QP (0) ++#define B_FRAME_MARGIN_QP (0) ++ ++// Compute qs ++#define SMOOTH_BASE 10 // 1 sec = 10* 100ms ++#define SMOOTH_PERIOD 10 // in second ++#define INIT_QP_OFFSET 18 ++#define INIT_QP_FACTOR 72 ++#define MIN_INIT_QP I_FRAME_MIN_QP ++#define MAX_INIT_QP I_FRAME_MAX_QP ++ ++#define THR_QP_FRAMESKIP (40) ++ ++//! How many seconds of frames are responsible for compensation of bitrate usage. ++#define SMOOTH_SECOND_CBR 10 // unit 100 ms ++#define SMOOTH_SECOND_CVBR 30 // unit 100 ms ++#define SMOOTH_SECOND_VBR 100 // unit 100 ms ++#define SMOOTH_FACTOR_MIN 100 // unit 100 ms ++ ++#define VBV_TGT_LVL_CBR 20 // unit 100 ms ++#define VBV_FUL_LOW_CBR 0 // unit 100 ms ++#define VBV_FUL_HIGH_CBR 40 // unit 100 ms ++#define VBV_BUF_SIZE_CBR 40 // unit 100 ms ++ ++#define VBV_TGT_LVL_VBR 40 // unit 100 ms ++#define VBV_FUL_LOW_VBR 0 // unit 100 ms ++#define VBV_FUL_HIGH_VBR 80 // unit 100 ms ++#define VBV_BUF_SIZE_VBR 80 // unit 100 ms ++ ++//! Default I-frame weighting over inter-frame ++#define IFRAME_WEIGHT (1024*7) ++#define PFRAME_WEIGHT 1024 ++#define BFRAME_WEIGHT 768 ++ ++ ++ ++MSBR_SASSERT( IFRAME_WEIGHT>0 && PFRAME_WEIGHT > 0, "The weighting of I frame or P frame should be bigger than zero" ); ++ ++/************************************************************************/ ++/* Constant */ ++/************************************************************************/ ++ ++// Operation Methods ++#define CONST_QP 0 ++#define CBR 1 ++#define VBR 2 ++#define CONSTRAINED_VBR 3 ++#define STATIC_CBR 4 ++ ++ ++// For Constrained VBR ++#define MAX_GAUGE_SIZE 64 ++ ++#define FRAME_TYPE_I 0 // I, P, B 3 types ++#define FRAME_TYPE_P 1 // I, P, B 3 types ++#define FRAME_TYPE_B 2 // I, P, B 3 types ++#define MAX_FRAME_TYPE 3 // I, P, B 3 types ++ ++/************************************************************************/ ++/* Local structures */ ++/************************************************************************/ ++ ++typedef struct mfe_msbr ++{ ++ mfe_rctl rqcx; ++ int i_method; ++ short i_leadqp, i_deltaq; ++ int i_btrate; ++ int i_pixels; ++ int i_tgt_mb; ++ int i_avg_qs; ++ // Derived variables ++ int i_avgbpf; ++ int m_bpf[MAX_FRAME_TYPE]; // I, P, B ++ /* coded frame counter */ ++ int i_gbl_frm_nr; ++ int i_frm_nr; ++ int i_frm_count[MAX_FRAME_TYPE]; ++ int64 i_totbit; ++ int64 i_frm_totbits[MAX_FRAME_TYPE]; ++ /* integral part of frame-rate */ ++ int n_fmrate; ++ int d_fmrate; ++ int i_fmrate; ++ int i_fps; ++ int i_maxbps; ++ int b_fixfps; ++ /* this-frame params */ ++ int i_this_enc_qs; ++ int i_this_max_qp; ++ int i_this_min_qp; ++ int i_this_max_qs; ++ int i_this_min_qs; ++ /* last-frame status */ ++ int i_last_avg_qs; ++ int i_last_frm_bs; ++ int i_last_tgt_bs; ++ int i_last_enc_qp; ++ int i_last_enc_qs; ++ int i_last_qp[MAX_FRAME_TYPE]; ++ int i_last_qs[MAX_FRAME_TYPE]; ++ int i_last_tgt_size[MAX_FRAME_TYPE]; ++ int i_last_frm_size[MAX_FRAME_TYPE]; ++ ++ /* init qp values */ ++ int i_init_qp[MAX_FRAME_TYPE]; // Max qp value for each frame type ++ int i_max_qp[MAX_FRAME_TYPE]; // Max qp value for each frame type ++ int i_min_qp[MAX_FRAME_TYPE]; // Mini qp value for each frame type ++ int i_margin_qp[MAX_FRAME_TYPE]; // The margin of QP setting between the boundaries. ++ ++ /* bitrate usage compensation */ ++ int i_vbv_buf_size; // Rate control buffer size ++ int i_vbv_fullness_low; // Rate control buffer fullness low bound ++ int i_vbv_fullness_high; // Rate control buffer fullness high bound ++ int i_vbv_fullness; // Rate control buffer fullness ++ int i_vbv_real_fullness; // Rate control buffer fullness ++ int i_vbv_target; // Rate control buffer target fullness ++ int i_vbv_balance; ++ ++ int i_smooth_cnt; ++ int i_smooth_min; ++ /* variable bitrate */ ++ int i_lt_qs64; ++ // model parameters ++ int i_tgt_bs; // target number of bits of current frame ++ /* only for Constrained VBR */ ++ int i_max_offset; ++ int i_gauge_bgt[MAX_GAUGE_SIZE]; ++ int i_gauge_cnt; ++ int i_gauge_idx; ++ int i_gauge_bps; ++ int i_frozen; ++ int i_thr_qp_frameskip; ++ int i_frameskip; // original MFE-RC: pic_done's output ++} mfe_msbr; ++ ++typedef struct ++{ ++ int bps; ++ int fps_by_10; ++ int pixels; ++ int qp_bound; ++} qp_bound; ++ ++#define BOUND_NUMERIC_SHIFT 16 ++ ++// I frame QP upper bound ++static const qp_bound qp_i_upper[]= { ++ { 256000, 250, 1920*1080, 51 }, ++ { 512000, 250, 1920*1080, 44 }, ++ { 1000000, 250, 1920*1080, 43 }, ++ { 2000000, 250, 1920*1080, 39 }, ++ { 3000000, 250, 1920*1080, 39 } ++}; ++ ++// P frame QP upper bound ++static const qp_bound qp_p_upper[]= { ++ { 256000, 250, 1920*1080, 51 }, ++ { 512000, 250, 1920*1080, 44 }, ++ { 1000000, 250, 1920*1080, 43 }, ++ { 2000000, 250, 1920*1080, 40 }, ++ { 3000000, 250, 1920*1080, 40 } ++}; ++ ++#define SIZE_OF_I_QP_UPP_BOUND sizeof( qp_i_upper) / sizeof(qp_bound); ++#define SIZE_OF_P_QP_UPP_BOUND sizeof( qp_p_upper) / sizeof(qp_bound); ++ ++#define BOUND_FP_SHIFT 16 // just for calculation ++ ++/************************************************************************/ ++/* Local prototypes */ ++/************************************************************************/ ++ ++static int msbr_seq_sync(rqct_ops*); ++static int msbr_seq_done(rqct_ops*); ++static int msbr_seq_conf(rqct_ops*); ++static int msbr_enc_conf(rqct_ops*, mhve_job*); ++static int msbr_enc_done(rqct_ops*, mhve_job*); ++static void msbr_release(rqct_ops*); ++ ++static int _msbr_compute_qs(mfe_msbr* msbr, int frm_type); ++static int _msbr_qp_init(mfe_msbr* msbr); ++static int _msbr_qp_update_max(mfe_msbr* msbr, int frm_type); ++static int _msbr_qp_fit_in_range(mfe_msbr* msbr, int frm_type); ++static int _msbr_get_qp_upper(int frm_type, int bps, int fps_by_10, int pixels ); ++ ++static int qp2qs(int QP); ++static int qs2qp(int qsx32); ++ ++/************************************************************************/ ++/* Functions */ ++/************************************************************************/ ++ ++ ++static void ++msbr_print_version(void) ++{ ++ printk("RATECTL_VER: [%s] %d.%d %s\n", RC_MODULE_NAME, RC_MODULE_VER_MAJOR, ++ RC_MODULE_VER_MINOR, RC_MODULE_VER_TEST ); ++} ++ ++char* msbr_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d-%02d:alternative rc.",MSBR_NAME,MSBR_VER_MJR,MSBR_VER_MNR,MSBR_VER_EXT); ++ return line; ++} ++ ++void* msbr_allocate(void) ++{ ++ rqct_ops* rqct; ++ ++ if (NULL != (rqct = MEM_ALLC(sizeof(mfe_msbr)))) ++ { ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ MEM_COPY(rqct->name, MSBR_NAME, 5); ++ rqct->seq_sync = msbr_seq_sync; ++ rqct->seq_done = msbr_seq_done; ++ rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->seq_conf = msbr_seq_conf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = msbr_enc_conf; ++ rqct->enc_done = msbr_enc_done; ++ rqct->release = msbr_release; ++ ++ rqcx->attr.i_method = RQCT_METHOD_CQP; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = 3; ++ rqcx->attr.i_upperq =48; ++ rqcx->attr.i_lowerq =12; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.i_btrate = 0; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->i_config = 0; ++ rqcx->i_pcount = 0; ++ rqcx->i_period = 0; ++ } ++ ++ return rqct; ++} ++ ++ ++static void msbr_release(rqct_ops* rqct) ++{ ++ MEM_FREE(rqct); ++} ++ ++static int msbr_seq_done(rqct_ops* rqct) ++{ ++ ++ /* Debug print */ ++ #if DBG_PRINT_ENABLE ++ { ++ mfe_msbr* msbr = (mfe_msbr*)rqct; ++ ++ MSBR_DBG( "m_bpf %d %d %d \n", msbr->m_bpf[0], msbr->m_bpf[1], msbr->m_bpf[2] ); ++ } ++ #endif ++ ++ /* call seq_done() */ ++ return 0; ++} ++ ++static int msbr_seq_sync(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ rqcx->i_pcount = 0; ++ return 0; ++} ++ ++static int msbr_seq_conf(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_msbr* msbr = (mfe_msbr*)rqcx; ++ int i; ++ ++ msbr_print_version(); ++ ++ msbr->i_method = (int)rqcx->attr.i_method; ++ msbr->i_leadqp = rqcx->attr.i_leadqp; ++ msbr->i_deltaq = rqcx->attr.i_deltaq; ++ msbr->i_btrate = rqcx->attr.i_btrate; ++ msbr->i_pixels = (int)rqcx->attr.i_pict_w * (int)rqcx->attr.i_pict_h; ++ msbr->n_fmrate = (int)rqcx->attr.n_fmrate; ++ msbr->d_fmrate = (int)rqcx->attr.d_fmrate; ++ msbr->i_fmrate = msbr->n_fmrate / msbr->d_fmrate; ++ msbr->i_maxbps = 0; ++ msbr->b_fixfps = 1; ++ ++ rqcx->i_period = rqcx->attr.i_period; ++ ++ // more bitrate checking ++ if (msbr->i_method == CONSTRAINED_VBR) ++ { ++ if (msbr->i_maxbps == 0) ++ msbr->i_maxbps = (int)((msbr->i_btrate*14)/10); ++ ++ msbr->i_max_offset = (int)div_s64((int64)(msbr->i_maxbps-msbr->i_btrate)*msbr->d_fmrate,msbr->n_fmrate); ++ ++ if (!(rqcx->i_config&RCTL_CFG_MB_DQP)) ++ msbr->i_max_offset = (msbr->i_max_offset) >> 2; ++ } ++ else ++ msbr->i_maxbps = 0; // Don't care ++ ++ msbr->i_avgbpf = (int)div_s64((int64)msbr->i_btrate*msbr->d_fmrate,msbr->n_fmrate); ++ ++ if (rqcx->i_period > 0) ++ { ++ int length = rqcx->i_period; ++ int weight = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_period-1); ++ msbr->m_bpf[0] = (int)div64_s64((int64)msbr->i_btrate*msbr->d_fmrate*IFRAME_WEIGHT*length, (int64)weight*msbr->n_fmrate); ++ msbr->m_bpf[1] = (int)div64_s64((int64)msbr->i_btrate*msbr->d_fmrate*PFRAME_WEIGHT*length, (int64)weight*msbr->n_fmrate); ++ msbr->m_bpf[2] = (int)div64_s64((int64)msbr->i_btrate*msbr->d_fmrate*BFRAME_WEIGHT*length, (int64)weight*msbr->n_fmrate); ++ ++ } ++ else ++ { ++ msbr->m_bpf[0] = (int)div64_s64((int64)msbr->i_btrate*msbr->d_fmrate*IFRAME_WEIGHT, (int64)PFRAME_WEIGHT*msbr->n_fmrate); ++ msbr->m_bpf[1] = (int)div64_s64((int64)msbr->i_btrate*msbr->d_fmrate,msbr->n_fmrate); ++ msbr->m_bpf[2] = msbr->m_bpf[1]; ++ } ++ ++ _msbr_qp_init(msbr); ++ ++ // Init frame number in Gop ++ rqcx->i_pcount = rqcx->i_period; ++ msbr->i_totbit = 0; ++ ++ // Bitrate usage monitoring ++ msbr->i_smooth_min = (msbr->n_fmrate*SMOOTH_SECOND_CBR)/msbr->d_fmrate/SMOOTH_BASE; ++ ++ switch (msbr->i_method) ++ { ++ case RQCT_METHOD_VBR: ++ msbr->i_smooth_cnt = (msbr->n_fmrate*SMOOTH_SECOND_VBR)/msbr->d_fmrate/SMOOTH_BASE; ++ ++ msbr->i_vbv_target = msbr->i_btrate * VBV_TGT_LVL_VBR / SMOOTH_BASE; ++ msbr->i_vbv_fullness_low = msbr->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msbr->i_vbv_fullness_high = msbr->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msbr->i_vbv_buf_size = msbr->i_btrate * VBV_BUF_SIZE_VBR / SMOOTH_BASE; ++ ++ break; ++ case CONSTRAINED_VBR: ++ msbr->i_smooth_cnt = (msbr->n_fmrate*SMOOTH_SECOND_CVBR)/msbr->d_fmrate/SMOOTH_BASE; ++ msbr->i_gauge_bgt[0] = msbr->m_bpf[0]; ++ for (i = 1; i < MAX_GAUGE_SIZE; i++) ++ msbr->i_gauge_bgt[i] = msbr->m_bpf[1]; ++ msbr->i_gauge_cnt = msbr->i_fmrate; ++ msbr->i_gauge_idx = 0; ++ msbr->i_gauge_bps = (int)div_s64((int64)msbr->i_btrate*msbr->d_fmrate*msbr->i_gauge_cnt,msbr->n_fmrate); ++ ++ msbr->i_vbv_target = msbr->i_btrate * VBV_TGT_LVL_VBR / SMOOTH_BASE; ++ msbr->i_vbv_fullness_low = msbr->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msbr->i_vbv_fullness_high = msbr->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msbr->i_vbv_buf_size = msbr->i_btrate * VBV_BUF_SIZE_VBR / SMOOTH_BASE; ++ ++ break; ++ case RQCT_METHOD_CBR: ++ default: ++ ++ msbr->i_smooth_cnt = (int)div_s64((int64)msbr->n_fmrate*SMOOTH_SECOND_CBR,msbr->d_fmrate*SMOOTH_BASE); ++ msbr->i_vbv_target = msbr->i_btrate * VBV_TGT_LVL_CBR / SMOOTH_BASE; ++ msbr->i_vbv_fullness_low = msbr->i_btrate * VBV_FUL_LOW_CBR / SMOOTH_BASE; ++ msbr->i_vbv_fullness_high = msbr->i_btrate * VBV_FUL_LOW_CBR / SMOOTH_BASE; ++ msbr->i_vbv_buf_size = msbr->i_btrate * VBV_BUF_SIZE_CBR / SMOOTH_BASE; ++ ++ break; ++ } ++ ++ msbr->i_vbv_fullness = msbr->i_vbv_target; ++ msbr->i_vbv_real_fullness = msbr->i_vbv_target; ++ ++ MSBR_DBG( "conf i_vbv_fullness = %d\n", msbr->i_vbv_fullness); ++ ++ msbr->i_thr_qp_frameskip = THR_QP_FRAMESKIP; ++ msbr->i_frm_nr = 0; ++ msbr->i_last_avg_qs = msbr->i_last_frm_bs = 0; ++ msbr->i_lt_qs64 = 0; ++ ++ // Init var ++ for( i=0; ii_last_enc_qs = 0; ++ msbr->i_last_enc_qp = 0; ++ ++ msbr->i_last_qp[i] = 0; ++ msbr->i_last_qs[i] = 0; ++ msbr->i_last_tgt_size[i] = 0; ++ msbr->i_last_frm_size[i] = 0; ++ /* ++ msbr->i_last_qp[i] = msbr->i_init_qp[i]; ++ msbr->i_last_qs[i] = qp2qs( msbr->i_init_qp[i]); ++ msbr->i_last_tgt_size[i] = msbr->m_bpf[i]; ++ msbr->i_last_frm_size[i] = msbr->m_bpf[i]; ++ */ ++ } ++ ++ return 0; ++} ++ ++/* ++ Get smooth count ++*/ ++static int _msbr_get_smooth_count(mfe_msbr* msbr) ++{ ++ int smooth_cnt = 0; ++ if (msbr->i_frm_nr > msbr->i_smooth_cnt*SMOOTH_FACTOR_MIN/SMOOTH_BASE) ++ smooth_cnt = msbr->i_smooth_cnt; ++ else if (msbr->i_frm_nr < msbr->i_smooth_min) ++ smooth_cnt = msbr->i_smooth_min; ++ else ++ { ++ int fact_n = msbr->i_smooth_cnt - msbr->i_smooth_min; ++ int fact_d = msbr->i_smooth_cnt * SMOOTH_FACTOR_MIN/SMOOTH_BASE - msbr->i_smooth_min; ++ smooth_cnt = msbr->i_smooth_min + (msbr->i_frm_nr - msbr->i_smooth_min) * fact_n / fact_d; ++ } ++ ++ return smooth_cnt; ++} ++ ++static int _msbr_calculate_delta(mfe_msbr* msbr, int smooth_cnt, int frm_type) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)msbr; ++ ++ int delta = 0; ++ ++ ++ #if ( CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES != 0 ) ++ if(msbr->i_frm_nr < CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ) ++ { ++ msbr->i_vbv_fullness = msbr->i_vbv_target; ++ ++ return 0; ++ } ++ #endif //CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ++ ++ #if CFG_VBV_BUF_UNDERFLOW_RESET ++ ++ /* reset if under flow */ ++ if( msbr->i_vbv_fullness < 0 ) ++ { ++ MSBR_DBG( "reset i_vbv_fullness %d= 0\n", msbr->i_vbv_fullness ); ++ msbr->i_vbv_fullness = 0; ++ } ++ #endif //CFG_VBV_BUF_UNDERFLOW_RESET ++ ++ #if CFG_VBV_BUF_OVERFLOW_RESET ++ ++ if( msbr->i_vbv_fullness > msbr->i_vbv_buf_size ) ++ { ++ MSBR_DBG( "reset i_vbv_fullness %d= %d\n", msbr->i_vbv_fullness, msbr->i_vbv_buf_size ); ++ msbr->i_vbv_fullness = msbr->i_vbv_buf_size; ++ } ++ ++ #endif //CFG_VBV_BUF_OVERFLOW_RESET ++ ++ if (msbr->i_method == RQCT_METHOD_CBR) ++ { ++ delta = (int)div_s64((int64)(msbr->i_vbv_fullness-msbr->i_vbv_target)*msbr->d_fmrate,msbr->n_fmrate*SMOOTH_SECOND_CBR/SMOOTH_BASE); ++ MSBR_DBG( "i_vbv_fullness %d i_vbv_target %d delta = %d\n", msbr->i_vbv_fullness, msbr->i_vbv_target,delta ); ++ ++ #if( CFG_RC_DELTA_CACULATE_METHOD == RDC_WEIGHTED_DIVIDED ) ++ { ++ int wp[MAX_FRAME_TYPE] = {IFRAME_WEIGHT,PFRAME_WEIGHT,BFRAME_WEIGHT}; ++ int w = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_period-1); ++ int n = rqcx->i_period; ++ ++ // Multiply the ratio of the frame type ++ delta = delta* n * wp[frm_type] / w; ++ MSBR_DBG( "Adjust delta = %d\n", delta ); ++ } ++ #endif //CFG_RC_DELTA_CACULATE_METHOD ++ ++ } ++ else if (msbr->i_method == CONSTRAINED_VBR) ++ { ++ delta = (msbr->i_vbv_fullness - msbr->i_vbv_target) / smooth_cnt; ++ if (delta < -msbr->i_max_offset) ++ delta = -msbr->i_max_offset; ++ } ++ else if (msbr->i_method == RQCT_METHOD_VBR) ++ { ++ delta = (msbr->i_vbv_fullness - msbr->i_vbv_target) / smooth_cnt; ++ if (delta > 0 && (msbr->i_last_avg_qs*64) > msbr->i_lt_qs64) ++ delta = delta>>1; // Make it more variable bitrate to allow better quality ++ } ++ ++ return delta; ++} ++ ++ ++/* Return target QPStep */ ++static int _msbr_compute_qs(mfe_msbr* msbr, int frm_type) ++{ ++ mfe_rctl* rqcx = &msbr->rqcx; ++ int newqs = 0; ++ int adjust; ++ int bitrate = msbr->i_btrate; ++ int fps_den = msbr->d_fmrate; ++ int fps_num = msbr->n_fmrate; ++ int mb_numb = msbr->i_pixels>>8; ++ ++ ++ // For the very first frame, guess one qp! ++ if (msbr->i_frm_nr == 0 || ++ msbr->i_last_qp[frm_type] == 0 ) ++ { ++ int bpMBK, newqp; ++ if (msbr->i_method == RQCT_METHOD_CQP) ++ { ++ newqp = msbr->i_leadqp; ++ newqs = qp2qs(newqp); // So that frame qp will be exactly msbr->i_qp ++ } ++ else ++ { ++ // bits per MB ++ bpMBK = (int)div_s64((int64)bitrate*fps_den*100,mb_numb*fps_num)+1; ++ newqp = INIT_QP_OFFSET + ( ( INIT_QP_FACTOR*100) / (bpMBK) ); ++ ++ if (newqp < MIN_INIT_QP) ++ newqp = MIN_INIT_QP; ++ if (newqp > MAX_INIT_QP) ++ newqp = MAX_INIT_QP; ++ newqs = newqp << QS_SHIFT_FACTOR; ++ } ++ ++ msbr->i_frozen = newqp >> 1; ++ ++ if (msbr->i_frozen > 15) ++ msbr->i_frozen = 15; ++ ++ return newqs; ++ } ++ ++ if (msbr->i_method == RQCT_METHOD_CQP) ++ return qp2qs(rqcx->rqct.i_enc_qp); ++ ++ if (msbr->i_method == RQCT_METHOD_CBR) ++ { ++ ++#if 1 ++ int dqs; ++ int last_size,tgt_size; ++ ++ last_size = msbr->i_last_frm_size[frm_type]; ++ ++ #if (CFG_LAST_QS_SELECTION == LQS_USE_LAST_SET_QS ) ++ newqs = msbr->i_last_enc_qs; ++ #elif (CFG_LAST_QS_SELECTION == LQS_USE_LAST_FRM_TYPE_SET_QS ) ++ newqs = msbr->i_last_qs[frm_type]; ++ #elif (CFG_LAST_QS_SELECTION == LQS_USE_LAST_AVG_ENC_QS ) ++ newqs = msbr->i_last_avg_qs; ++ #else ++ newqs = msbr->i_last_enc_qs; ++ #endif ++ ++ dqs = newqs / 8; ++ tgt_size = msbr->i_tgt_bs; ++ ++ MSBR_DBG( "newqs = %d dqs = %d last_size %d tgt_size %d\n", newqs, dqs, last_size, tgt_size); ++ ++ if( tgt_size > MSRC_PERCENT( 160, last_size) ) ++ { ++ newqs = newqs - dqs*2; ++ MSBR_DBG( "newqs-- = %d \n", newqs ); ++ } ++ else if( tgt_size > MSRC_PERCENT( 113, last_size) ) ++ { ++ newqs = newqs - dqs*1; ++ MSBR_DBG( "newqs- = %d \n", newqs ); ++ } ++ else if( tgt_size < MSRC_PERCENT( 60, last_size) ) ++ { ++ newqs = newqs + dqs*2; ++ MSBR_DBG( "newqs++ = %d \n", newqs ); ++ } ++ else if( tgt_size < MSRC_PERCENT( 87, last_size) ) ++ { ++ newqs = newqs + dqs*1; ++ MSBR_DBG( "newqs+ = %d \n", newqs ); ++ } ++ else ++ { ++ MSBR_DBG( "newqs~ = %d \n", newqs ); ++ } ++ ++#else ++ int frm_cnt = msbr->i_frm_nr; ++ int frames_left; ++ int buf_rest_pic; ++ int64 buf_rest; ++ ++ int dqp; ++ buf_rest = div_s64((int64)frm_cnt*fps_den*bitrate,fps_num); ++ buf_rest+= (SMOOTH_PERIOD*msbr->i_btrate) - msbr->i_totbit; ++ newqs = msbr->i_last_avg_qs; ++ frames_left = (SMOOTH_PERIOD * msbr->n_fmrate) / msbr->d_fmrate; ++ buf_rest_pic = (int)div_s64(buf_rest,frames_left); ++ dqp = msbr->i_last_avg_qs/8; ++ ++ if (msbr->i_last_frm_bs > (buf_rest_pic*9)>>3) ++ newqs = msbr->i_last_avg_qs + dqp; ++ else if (msbr->i_last_frm_bs < (buf_rest_pic*7)>>3) ++ newqs = msbr->i_last_avg_qs - dqp; ++#endif ++ ++ } ++ else if (msbr->i_method == CONSTRAINED_VBR) ++ { ++ int lo_qs, hi_qs; ++ adjust = msbr->i_lt_qs64>>2; ++ lo_qs = (msbr->i_lt_qs64 - adjust) >> 6; ++ hi_qs = (msbr->i_lt_qs64 + adjust) >> 6; ++ if (rqcx->i_period > 1 && IS_IPIC(rqcx->rqct.i_pictyp)) ++ { ++ newqs = msbr->i_last_avg_qs; ++ if (msbr->i_gauge_bps < msbr->i_btrate) ++ newqs = newqs-(1<i_lt_qs64 * div_s64(msbr->i_totbit,msbr->i_frm_nr), msbr->i_tgt_bs) ; ++ //MFE_ASSERT((tmp >> 6) < (1<<31)); ++ newqs = (int)(div_s64((int64)msbr->i_lt_qs64 * div_s64(msbr->i_totbit,msbr->i_frm_nr),msbr->i_tgt_bs)>>6) ; ++ if (msbr->i_last_frm_bs>msbr->i_last_tgt_bs) ++ { ++ adjust = ((msbr->i_last_frm_bs-msbr->i_last_tgt_bs)/msbr->i_max_offset) + (1< (3<i_last_avg_qs*64) > msbr->i_lt_qs64) ++ { ++ // Danger! Make it more aggressive ++ hi_qs = msbr->i_last_avg_qs + adjust; ++ newqs = msbr->i_last_avg_qs + adjust; ++ } ++ else ++ { ++ hi_qs += adjust; ++ newqs += adjust; ++ } ++ } ++ else if (msbr->i_gauge_bps > msbr->i_btrate) ++ { ++ if (msbr->i_last_avg_qs > newqs) ++ newqs = msbr->i_last_avg_qs; ++ if (msbr->i_lt_qs64 > (newqs*64)) ++ newqs = msbr->i_lt_qs64/64; ++ } ++ else ++ { ++ if ((newqs<<6) >= msbr->i_lt_qs64) ++ newqs = (msbr->i_lt_qs64/64)-1; ++ if (msbr->i_vbv_target>msbr->i_vbv_fullness) ++ { ++ adjust = (msbr->i_vbv_target - msbr->i_vbv_fullness) / (int)msbr->i_btrate; ++ newqs -= adjust; ++ } ++ } ++ } ++ newqs = MSRC_MIN(hi_qs, newqs); ++ newqs = MSRC_MAX(lo_qs, newqs); ++ } ++ else if (msbr->i_method == RQCT_METHOD_VBR) ++ { ++ int lo_qs, hi_qs; ++ if (rqcx->i_period > 1 && IS_IPIC(rqcx->rqct.i_pictyp)) ++ { ++ newqs = msbr->i_last_avg_qs; ++ if ((msbr->i_last_avg_qs*64) > msbr->i_lt_qs64) ++ newqs = newqs - (1<i_frm_nr >= msbr->i_fmrate || rqcx->i_period == 1) ++ { ++ //int64 tmp = div_s64((int64)msbr->i_lt_qs64*div_s64(msbr->i_totbit,msbr->i_frm_nr),msbr->i_avgbpf); ++ //MFE_ASSERT((tmp >> 6) < (1<<31)); ++ adj_ltq = (int)(div_s64((int64)msbr->i_lt_qs64*div_s64(msbr->i_totbit,msbr->i_frm_nr),msbr->i_avgbpf)>>6); ++ } ++ else ++ { ++ adj_ltq = msbr->i_lt_qs64/64; // Wait for stabilization ++ } ++ MFE_ASSERT(msbr->i_tgt_bs>0); ++ newqs = (adj_ltq * msbr->i_avgbpf) / msbr->i_tgt_bs; ++ ++ adjust = MSRC_MAX((2<>2); ++ lo_qs = adj_ltq - adjust; ++ hi_qs = adj_ltq + adjust; ++ ++ if (msbr->i_last_frm_bs > msbr->i_last_tgt_bs) ++ { ++ adjust = (int)(msbr->i_last_frm_bs/msbr->i_last_tgt_bs); ++ if (adjust > 2) ++ adjust = 2; ++ hi_qs += adjust; ++ } ++ ++ if (msbr->i_avgbpf > msbr->i_tgt_bs) ++ newqs = MSRC_MIN(hi_qs,newqs); ++ else ++ newqs = MSRC_MAX(lo_qs,newqs); ++ } ++ } ++ return newqs; ++} ++ ++ ++static int msbr_enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ mfe_msbr* msbr = (mfe_msbr*)rqcx; ++ int frm_type; ++ int delta = 0; ++ int init_frames = 0; ++ ++ frm_type = rqct->i_pictyp; ++ ++ if( rqcx->i_period > 1 ) ++ { ++ // The number of P frames in GOP is not zero. ++ init_frames = 1; ++ } ++ ++ #if (CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES != 0 ) ++ init_frames = CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES; ++ #endif //CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ++ ++ // Target frame bitcount ++ if (msbr->i_frm_nr > init_frames) ++ { ++ int smooth_cnt = 0; ++ // 1. Determine the number of future frame to compensate for current bitrate mismatch. ++ smooth_cnt = _msbr_get_smooth_count(msbr); ++ ++ // 2. Calculate the bitcount that this frame should be compensate for. ++ delta = _msbr_calculate_delta( msbr, smooth_cnt, frm_type); ++ ++ // 3. Finally, calculate the target bitcount. ++ msbr->i_tgt_bs = msbr->m_bpf[frm_type] - delta; ++ ++ ++ // 4. Clip the target size to 70% ~ 130% ++ msbr->i_tgt_bs = MSRC_FIT_IN_RANGE( msbr->i_tgt_bs ++ ,MSRC_PERCENT ( 70, msbr->m_bpf[frm_type]) ++ ,MSRC_PERCENT (130, msbr->m_bpf[frm_type])); ++ ++ } ++ else ++ { ++ // The first I frame and the first P frame use the default value. ++ msbr->i_tgt_bs = msbr->m_bpf[frm_type]; ++ } ++ ++ /* Update max min qp value */ ++ _msbr_qp_update_max(msbr, frm_type); ++ /* Return initial frame QP */ ++ msbr->i_this_enc_qs = _msbr_compute_qs(msbr, frm_type); ++ rqct->i_enc_qp = qs2qp(msbr->i_this_enc_qs); ++ ++ MSBR_DBG( "Qp = %d qs = %d ls %d tg %d <%d:%d> dt %d\n", rqcx->rqct.i_enc_qp , msbr->i_this_enc_qs, msbr->i_last_frm_size[frm_type], msbr->i_tgt_bs ++ , msbr->i_frm_nr, frm_type,delta); ++ ++ /* Clip qs and qp value in range */ ++ _msbr_qp_fit_in_range(msbr, frm_type); ++ ++ msbr->i_last_avg_qs = 0; ++ msbr->i_last_frm_bs = 0; ++ ++ msbr->i_tgt_mb = (int)div_s64((int64)msbr->i_tgt_bs*256,msbr->i_pixels); ++ ++ if (msbr->i_tgt_mb < 1) ++ msbr->i_tgt_mb = 1; ++ ++ switch (msbr->i_method) ++ { ++ case RQCT_METHOD_CBR: ++ rqcx->i_config |= RCTL_CFG_MB_DQP; ++ ++ #if CFG_CBR_IFRAME_CQP ++ if( frm_type == 0 ) ++ rqcx->i_config&=~RCTL_CFG_MB_DQP; ++ #endif ++ ++ #if CFG_CBR_PFRAME_CQP ++ if( frm_type != 0 ) ++ rqcx->i_config&=~RCTL_CFG_MB_DQP; ++ #endif ++ ++ break; ++ case CONSTRAINED_VBR: ++ case RQCT_METHOD_VBR: ++ rqcx->i_config|= RCTL_CFG_MB_DQP; ++ break; ++ case RQCT_METHOD_CQP: ++ rqcx->i_config&=~RCTL_CFG_MB_DQP; ++ break; ++ default: ++ rqcx->i_config|= RCTL_CFG_MB_DQP; ++ break; ++ } ++ ++ mrqc_roi_draw(rqct, mjob); ++ ++ regs->reg00_g_mbr_en = !rqcx->attr.b_dqmstat && (msbr->i_method!=RQCT_METHOD_CQP); ++ regs->reg26_s_mbr_pqp_dlimit = LF_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = UP_QP_DIFF_LIMIT; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = msbr->i_this_enc_qs; ++ regs->reg26_s_mbr_tmb_bits = msbr->i_tgt_mb; ++ regs->reg2a_s_mbr_qp_min = msbr->i_this_min_qp; ++ regs->reg2a_s_mbr_qp_max = msbr->i_this_max_qp; ++ regs->reg6e_s_mbr_qstep_min = msbr->i_this_min_qs; ++ regs->reg6f_s_mbr_qstep_max = msbr->i_this_max_qs; ++ ++ return 0; ++} ++ ++static int msbr_enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_msbr* msbr = (mfe_msbr*)rqcx; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ int frameskip = 0; ++ int frm_type; ++ int mbs = (msbr->i_pixels>>8); ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ msbr->i_avg_qs = regs->sumofq / (mbs-1); ++ ++ rqct->i_enc_bs += rqct->i_bitcnt/8; ++ rqct->i_enc_nr++; ++ ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d",\ ++ rqct->name,rqct->i_enc_nr,IS_IPIC(rqct->i_pictyp)?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt); ++ ++ frm_type = rqct->i_pictyp; ++ ++ // update counter ++ msbr->i_totbit += rqct->i_bitcnt; ++ msbr->i_frm_nr++; ++ ++ MSBR_DBG( "conf i_vbv_fullness %d + bitcnt %d= ", msbr->i_vbv_fullness, rqct->i_bitcnt ); ++ ++ msbr->i_vbv_fullness += rqct->i_bitcnt; ++ msbr->i_vbv_real_fullness += rqct->i_bitcnt; ++ ++ MSBR_DBG( "%d\n", msbr->i_vbv_fullness ); ++ ++ ++ msbr->i_last_frm_bs = rqct->i_bitcnt; ++ msbr->i_last_tgt_bs = msbr->i_tgt_bs; ++ ++ msbr->i_last_enc_qs = msbr->i_this_enc_qs; ++ msbr->i_last_enc_qp = rqct->i_enc_qp; ++ ++ msbr->i_last_qs[frm_type] = msbr->i_this_enc_qs; ++ msbr->i_last_qp[frm_type] = rqct->i_enc_qp; ++ msbr->i_last_tgt_size[frm_type] = msbr->i_tgt_bs; ++ msbr->i_last_frm_size[frm_type] = rqct->i_bitcnt; ++ ++#if defined(MMFE_RCTL_PATCH) ++ if (msbr->i_avg_qs <(msbr->i_this_enc_qs/2)) ++ msbr->i_avg_qs = msbr->i_this_enc_qs; ++ if (msbr->i_avg_qs > msbr->i_this_max_qs) ++ msbr->i_avg_qs = msbr->i_this_max_qs; ++#endif ++ ++ msbr->i_last_avg_qs = msbr->i_avg_qs; ++ // Variable bitrate ++ if (msbr->i_method == RQCT_METHOD_VBR) ++ msbr->i_lt_qs64 += ((msbr->i_last_avg_qs*64)-msbr->i_lt_qs64) / msbr->i_frm_nr; ++ else if (msbr->i_method == CONSTRAINED_VBR) ++ { ++ if (msbr->i_frm_nr == 1) ++ msbr->i_lt_qs64 = msbr->i_last_avg_qs*64; ++ else ++ msbr->i_lt_qs64 = (msbr->i_lt_qs64*(msbr->i_smooth_cnt-1) + (msbr->i_last_avg_qs*64)) / msbr->i_smooth_cnt; ++ } ++ ++ if (msbr->i_method == CONSTRAINED_VBR) ++ { ++ msbr->i_gauge_bps -= msbr->i_gauge_bgt[msbr->i_gauge_idx]; ++ msbr->i_gauge_bps += rqct->i_bitcnt; ++ msbr->i_gauge_bgt[msbr->i_gauge_idx] = rqct->i_bitcnt; ++ msbr->i_gauge_idx++; ++ if (msbr->i_gauge_idx == msbr->i_gauge_cnt) ++ msbr->i_gauge_idx = 0; ++ } ++ ++ /* Update VBV buffer status */ ++ ++ #if ( CFG_VBV_FRAME_QUOTA_METHOD == VFQ_USE_AVERAGE_SIZE ) ++ ++ MSBR_DBG( "conf i_vbv_fullness %d - i_avgbpf %d= ", msbr->i_vbv_fullness, msbr->i_avgbpf ); ++ msbr->i_vbv_fullness -= msbr->i_avgbpf; ++ msbr->i_vbv_real_fullness -= msbr->i_avgbpf; ++ ++ #elif ( CFG_VBV_FRAME_QUOTA_METHOD == VFQ_USE_WEIGHTED_SIZE ) ++ ++ MSBR_DBG( "conf i_vbv_fullness %d - i_avgbpf %d= ", msbr->i_vbv_fullness, msbr->m_bpf[frm_type] ); ++ msbr->i_vbv_fullness -= msbr->m_bpf[frm_type]; ++ msbr->i_vbv_real_fullness -= msbr->m_bpf[frm_type]; ++ ++ #else // ++ ++ msbr->i_vbv_fullness -= msbr->i_avgbpf; ++ msbr->i_vbv_real_fullness -= msbr->i_avgbpf; ++ ++ #endif //VFQ_USE_WEIGHTED_SIZE ++ ++ MSBR_DBG( "%d\n", msbr->i_vbv_fullness); ++ ++ // check if next skipped frame(s) needed ++ if (!msbr->b_fixfps) ++ { ++ if (msbr->i_method == CONSTRAINED_VBR || msbr->i_method == RQCT_METHOD_VBR) ++ { ++ if (msbr->i_lt_qs64 > (qp2qs(msbr->i_thr_qp_frameskip)*64) && ++ msbr->i_last_frm_bs >= (msbr->i_last_tgt_bs<<1)) ++ { ++ frameskip = (int)((msbr->i_last_frm_bs - msbr->i_last_tgt_bs) / msbr->i_avgbpf - 1); ++ if (frameskip < 0) ++ frameskip = 0; ++ else if (frameskip > msbr->i_frozen) ++ frameskip = msbr->i_frozen; ++ } ++ } ++ else if (msbr->i_method == RQCT_METHOD_CBR) ++ { ++ if (msbr->i_last_avg_qs > qp2qs(msbr->i_thr_qp_frameskip)) ++ { ++ // Actual fullness is updated after encoding dummy-P frame ++ int fullness = msbr->i_vbv_fullness; ++ while (fullness > msbr->i_vbv_target) ++ { ++ fullness = (int)(fullness - msbr->i_avgbpf); ++ frameskip++; ++ } ++ } ++ } ++ msbr->i_frameskip = frameskip; ++ } ++ return 0; ++} ++ ++static int qp2qs(int qp) ++{ ++ int i; ++ int qs; ++ static const int QP2QSTEP[6] = { 20, 22, 26, 28, 32, 36 }; ++ ++ qs = QP2QSTEP[qp%6]; ++ ++ for (i = 0; i < (qp/6); i++) ++ qs*=2; ++ ++ return qs; ++} ++ ++static int qs2qp(int qsx32) ++{ ++ int q_per = 0, q_rem = 0; ++ ++ while (qsx32 > qp2qs(5)) ++ { ++ qsx32 >>= 1; ++ q_per += 1; ++ } ++ ++ if (qsx32 <= 21) ++ { ++ qsx32 = 20; ++ q_rem = 0; ++ } ++ else if (qsx32 <= 24) ++ { ++ qsx32 = 22; ++ q_rem = 1; ++ } ++ else if (qsx32 <= 27) ++ { ++ qsx32 = 26; ++ q_rem = 2; ++ } ++ else if (qsx32 <= 30) ++ { ++ qsx32 = 28; ++ q_rem = 3; ++ } ++ else if (qsx32 <= 34) ++ { ++ qsx32 = 32; ++ q_rem = 4; ++ } ++ else ++ { ++ qsx32 = 36; ++ q_rem = 5; ++ } ++ ++ return (q_per*6 + q_rem); ++} ++ ++ ++static int _msbr_qp_init(mfe_msbr* msbr) ++{ ++ int i; ++ // Init with a default value ++ for( i=0; i< MAX_FRAME_TYPE; i++ ) ++ { ++ msbr->i_init_qp[i] = P_FRAME_INIT_QP; ++ msbr->i_min_qp[i] = P_FRAME_MIN_QP; ++ msbr->i_max_qp[i] = P_FRAME_MAX_QP; ++ msbr->i_margin_qp[i] = P_FRAME_MARGIN_QP; ++ } ++ ++ msbr->i_init_qp[RQCT_PICTYP_I] = I_FRAME_INIT_QP; ++ msbr->i_min_qp[RQCT_PICTYP_I] = I_FRAME_MIN_QP; ++ msbr->i_max_qp[RQCT_PICTYP_I] = I_FRAME_MAX_QP; ++ msbr->i_margin_qp[RQCT_PICTYP_I] = I_FRAME_MARGIN_QP; ++ ++ msbr->i_init_qp[RQCT_PICTYP_P] = P_FRAME_INIT_QP; ++ msbr->i_min_qp[RQCT_PICTYP_P] = P_FRAME_MIN_QP; ++ msbr->i_max_qp[RQCT_PICTYP_P] = P_FRAME_MAX_QP; ++ msbr->i_margin_qp[RQCT_PICTYP_P] = P_FRAME_MARGIN_QP; ++ ++ msbr->i_init_qp[RQCT_PICTYP_B] = B_FRAME_INIT_QP; ++ msbr->i_min_qp[RQCT_PICTYP_B] = B_FRAME_MIN_QP; ++ msbr->i_max_qp[RQCT_PICTYP_B] = B_FRAME_MAX_QP; ++ msbr->i_margin_qp[RQCT_PICTYP_B] = B_FRAME_MARGIN_QP; ++ ++ if (msbr->i_method == RQCT_METHOD_VBR) ++ { ++ msbr->i_init_qp[RQCT_PICTYP_I] = msbr->i_leadqp - msbr->i_deltaq; ++ msbr->i_init_qp[RQCT_PICTYP_P] = msbr->i_leadqp; ++ msbr->i_min_qp[RQCT_PICTYP_I] = msbr->rqcx.attr.i_lowerq - msbr->i_deltaq; ++ msbr->i_max_qp[RQCT_PICTYP_I] = msbr->rqcx.attr.i_upperq - msbr->i_deltaq; ++ msbr->i_min_qp[RQCT_PICTYP_P] = msbr->rqcx.attr.i_lowerq; ++ msbr->i_max_qp[RQCT_PICTYP_P] = msbr->rqcx.attr.i_upperq; ++ } ++ ++ return 0; ++} ++ ++static int _msbr_qp_update_max(mfe_msbr* msbr, int frm_type) ++{ ++ int max_qp, min_qp; ++ ++ if( frm_type > MAX_FRAME_TYPE-1 ) frm_type = RQCT_PICTYP_P; ++ ++ min_qp = msbr->i_min_qp[frm_type]; ++ ++/* ++ // Fixed boundaries ++ max_qp = msbr->i_max_qp[frm_type]; ++*/ ++ max_qp = _msbr_get_qp_upper(frm_type, msbr->i_btrate, msbr->i_fmrate*10, msbr->i_pixels ); ++ ++ // Apply into max/min setting ++ msbr->i_this_min_qp = min_qp; ++ msbr->i_this_max_qp = max_qp; ++ msbr->i_this_min_qs = qp2qs(min_qp)-1; ++ msbr->i_this_max_qs = qp2qs(max_qp); ++ ++ return 0; ++} ++ ++static int _msbr_qp_fit_in_range(mfe_msbr* msbr, int frm_type) ++{ ++ mfe_rctl* rqcx = &msbr->rqcx; ++ rqct_ops* rqct = &rqcx->rqct; ++ int max_qp, min_qp; ++ int max_qs, min_qs; ++ ++ if( frm_type > MAX_FRAME_TYPE-1 ) frm_type = RQCT_PICTYP_P; ++ ++ max_qp = msbr->i_max_qp[frm_type] - msbr->i_margin_qp[frm_type]; ++ min_qp = msbr->i_min_qp[frm_type] - msbr->i_margin_qp[frm_type]; ++ ++ min_qs = qp2qs(min_qp )-1; ++ max_qs = qp2qs(max_qp ); ++ ++ msbr->i_this_enc_qs = MSRC_FIT_IN_RANGE(msbr->i_this_enc_qs, min_qs, max_qs ); ++ rqct->i_enc_qp = MSRC_FIT_IN_RANGE(rqct->i_enc_qp, min_qp, max_qp ); ++ ++ return 0; ++} ++ ++ ++static int _msbr_get_qp_upper(int frm_type, int bps, int fps_by_10, int pixels ) ++{ ++ int i; ++ int bpm; ++ int num = 0; ++ int qp; ++ const qp_bound* qp_table; ++ ++ bpm = (int)div64_s64( (int64)(bps*10)< ++ ++#include ++ ++#define MRQC_NAME "MRQC" ++#define MRQC_VER_MJR 0 ++#define MRQC_VER_MNR 0 ++#define MRQC_VER_EXT 1 ++ ++void* msbr_allocate(void); ++char* msbr_describe(void); ++void* cvbr_allocate(void); ++char* cvbr_describe(void); ++void* msb2_allocate(void); ++char* msb2_describe(void); ++void* msb3_allocate(void); ++char* msb3_describe(void); ++ ++static void* mrqc_allocate(void); ++static char* mrqc_describe(void); ++ ++#define MRQC_FACTORIES_NR 8 ++ ++static struct mrqc_factory { ++ void* (*rqc_alloc)(void); ++ char* (*rqc_descr)(void); ++} factories[MRQC_FACTORIES_NR] = ++{ ++{mrqc_allocate,mrqc_describe}, ++{cvbr_allocate,cvbr_describe}, ++{msbr_allocate,msbr_describe}, ++{msb2_allocate,msb2_describe}, ++{msb3_allocate,msb3_describe}, ++{NULL,NULL}, ++}; ++ ++int rqctmfe_insert(void* (*allc)(void), char*(*desc)(void)) ++{ ++ if (factories[0].rqc_alloc != mrqc_allocate) ++ return -1; ++ factories[0].rqc_alloc = allc; ++ factories[0].rqc_descr = desc; ++ return 0; ++} ++EXPORT_SYMBOL(rqctmfe_insert); ++ ++int rqctmfe_remove(void) ++{ ++ if (factories[0].rqc_alloc == mrqc_allocate) ++ return -1; ++ factories[0].rqc_alloc = mrqc_allocate; ++ factories[0].rqc_descr = mrqc_describe; ++ return 0; ++} ++EXPORT_SYMBOL(rqctmfe_remove); ++ ++void* rqctmfe_acquire(int idx) ++{ ++ if ((unsigned)idx < MRQC_FACTORIES_NR && factories[idx].rqc_alloc) ++ return (factories[idx].rqc_alloc)(); ++ return (factories[0].rqc_alloc)(); ++} ++ ++char* rqctmfe_comment(int idx) ++{ ++ if ((unsigned)idx < MRQC_FACTORIES_NR && factories[idx].rqc_alloc) ++ return (factories[idx].rqc_descr)(); ++ return NULL; ++} ++ ++/* default rate controller */ ++ ++static void _mrqcfree(rqct_ops* rqct) {MEM_FREE(rqct);} ++static int _seq_sync(rqct_ops* rqct); ++static int _seq_done(rqct_ops* rqct); ++static int _seq_conf(rqct_ops* rqct); ++static int _enc_conf(rqct_ops* rqct, mhve_job* mjob); ++static int _enc_done(rqct_ops* rqct, mhve_job* mjob); ++ ++static void* mrqc_allocate(void) ++{ ++ rqct_ops* rqct = NULL; ++ mfe_rctl* rqcx; ++ ++ if (!(rqct = MEM_ALLC(sizeof(mfe_rctl)))) ++ return NULL; ++ ++ MEM_COPY(rqct->name, "mrct", 5); ++ rqct->release = _mrqcfree; ++ rqct->seq_sync = _seq_sync; ++ rqct->seq_done = _seq_done; ++ rqct->seq_conf = _seq_conf; ++ rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = _enc_conf; ++ rqct->enc_done = _enc_done; ++ rqcx = (mfe_rctl*)rqct; ++ rqcx->attr.i_method = RQCT_METHOD_CQP; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = 3; ++ rqcx->attr.i_btrate = 0; ++ rqcx->i_config = 0; ++ rqcx->i_pcount = 0; ++ rqcx->i_period = 0; ++ ++ return rqcx; ++} ++ ++static char* mrqc_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d.%02d:fixed qp only.",MRQC_NAME,MRQC_VER_MJR,MRQC_VER_MNR,MRQC_VER_EXT); ++ return line; ++} ++ ++static int _seq_conf(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ rqcx->i_period = rqcx->attr.i_period; ++ if (rqcx->attr.i_leadqp < 8 || rqcx->attr.i_leadqp > 48) ++ rqcx->attr.i_leadqp = 36; ++ rqcx->i_pcount = rqcx->i_period; ++ return 0; ++} ++ ++static int _seq_sync(rqct_ops* rqct) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ rqcx->i_pcount = 0; ++ return 0; ++} ++ ++static int _seq_done(rqct_ops* rqct) ++{ ++ return 0; ++} ++ ++static int _enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ rqct->i_enc_qp = rqcx->attr.i_leadqp; ++ if (rqct->i_pictyp == RQCT_PICTYP_I) ++ rqct->i_enc_qp = rqcx->attr.i_leadqp - rqcx->attr.i_deltaq; ++ mrqc_roi_draw(rqct, mjob); ++#define UP_DQP 3 ++#define LF_DQP 3 ++ regs->reg00_g_mbr_en = 0; ++ regs->reg26_s_mbr_pqp_dlimit = UP_DQP; ++ regs->reg26_s_mbr_uqp_dlimit = LF_DQP; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = 0; ++ regs->reg26_s_mbr_tmb_bits = 0; ++ regs->reg2a_s_mbr_qp_min = 0; ++ regs->reg2a_s_mbr_qp_max = 0; ++ regs->reg6e_s_mbr_qstep_min = 0; ++ regs->reg6f_s_mbr_qstep_max = 0; ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d",\ ++ rqct->name,rqct->i_enc_nr,IS_IPIC(rqct->i_pictyp)?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt); ++ return 0; ++} ++ ++int mrqc_enc_buff(rqct_ops* rqct, rqct_buf* buff) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ rqcx->i_config = buff->u_config; ++ if (rqcx->i_pcount == 0) ++ rqct->seq_conf(rqct); ++ /* picture-type decision */ ++ if (rqcx->i_pcount == rqcx->i_period) ++ { ++ rqcx->i_pcount = 1; ++ rqct->i_pictyp = RQCT_PICTYP_I; ++ rqct->b_unrefp = 0; ++ } ++ else ++ { ++ rqcx->i_pcount++; ++ rqct->i_pictyp = RQCT_PICTYP_P; ++ if (rqct->b_unrefp) ++ rqct->b_unrefp = !(rqcx->i_pcount%2); ++ } ++ return 0; ++} ++EXPORT_SYMBOL(mrqc_enc_buff); ++ ++static int _enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_regs* regs = (mfe_regs*)mjob; ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ rqct->i_enc_bs+= mjob->i_bits/8; ++ rqct->i_enc_nr++; ++ ++ return 0; ++} ++ ++int mrqc_set_rqcf(rqct_ops* rqct, rqct_cfg* rqcf) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ int err = -1; ++ switch (rqcf->type) ++ { ++ case RQCT_CFG_SEQ: ++ if ((unsigned)rqcf->seq.i_method > RQCT_METHOD_VBR) ++ break; ++ rqcx->attr.i_method = rqcf->seq.i_method; ++ rqcx->attr.i_period = rqcf->seq.i_period; ++ rqcx->attr.i_btrate = rqcf->seq.i_btrate; ++ rqcx->attr.i_leadqp = rqcf->seq.i_leadqp; ++ rqcx->i_pcount = 0; ++ err = 0; ++ break; ++ case RQCT_CFG_DQP: ++ if ((unsigned)rqcf->dqp.i_dqp > 15) ++ break; ++ rqcx->attr.i_deltaq = rqcf->dqp.i_dqp; ++ err = 0; ++ break; ++ case RQCT_CFG_QPR: ++ rqcx->attr.i_upperq = rqcf->qpr.i_upperq; ++ rqcx->attr.i_lowerq = rqcf->qpr.i_lowerq; ++ err = 0; ++ break; ++ case RQCT_CFG_LOG: ++ rqcx->attr.b_logoff = !rqcf->log.b_logm; ++ err = 0; ++ break; ++ /* private config */ ++ case RQCT_CFG_RES: ++ rqcx->attr.i_pict_w = rqcf->res.i_picw; ++ rqcx->attr.i_pict_h = rqcf->res.i_pich; ++ err = 0; ++ break; ++ case RQCT_CFG_FPS: ++ rqcx->attr.n_fmrate = rqcf->fps.n_fps; ++ rqcx->attr.d_fmrate = rqcf->fps.d_fps; ++ err = 0; ++ break; ++ case RQCT_CFG_ROI: ++ err = 0; ++ rqcx->attr.b_dqmstat = -1; ++ if (-1 == rqcf->roi.i_roiidx) ++ { ++ memset(rqcx->attr.i_roidqp, 0, sizeof(rqcx->attr.i_roidqp)); ++ break; ++ } ++ if (rqcf->roi.i_roidqp == 0 || ++ (unsigned)rqcf->roi.i_posx > (unsigned)rqcx->attr.i_dqmw || ++ (unsigned)rqcf->roi.i_posy > (unsigned)rqcx->attr.i_dqmh || ++ rqcf->roi.i_recw <= 0 || ++ rqcf->roi.i_rech <= 0) ++ { ++ rqcx->attr.i_roidqp[rqcf->roi.i_roiidx] = 0; ++ break; ++ } ++ if (rqcf->roi.i_recw > (rqcx->attr.i_dqmw - rqcf->roi.i_posx)) ++ rqcf->roi.i_recw = (rqcx->attr.i_dqmw - rqcf->roi.i_posx); ++ if (rqcf->roi.i_rech > (rqcx->attr.i_dqmh - rqcf->roi.i_posy)) ++ rqcf->roi.i_rech = (rqcx->attr.i_dqmh - rqcf->roi.i_posy); ++ rqcx->attr.i_roidqp[rqcf->roi.i_roiidx] = rqcf->roi.i_roidqp; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posx = rqcf->roi.i_posx; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posy = rqcf->roi.i_posy; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_recw = rqcf->roi.i_recw; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_rech = rqcf->roi.i_rech; ++ break; ++ case RQCT_CFG_DQM: ++ rqcx->attr.u_dqmphys = rqcf->dqm.u_phys; ++ rqcx->attr.p_dqmkptr = rqcf->dqm.p_kptr; ++ rqcx->attr.i_dqmsize = rqcf->dqm.i_size; ++ rqcx->attr.i_dqmw = rqcf->dqm.i_dqmw; ++ rqcx->attr.i_dqmh = rqcf->dqm.i_dqmh; ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ return err; ++} ++EXPORT_SYMBOL(mrqc_set_rqcf); ++ ++int mrqc_get_rqcf(rqct_ops* rqct, rqct_cfg* rqcf) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ int err = -1; ++ switch (rqcf->type) ++ { ++ case RQCT_CFG_SEQ: ++ rqcf->seq.i_method = rqcx->attr.i_method; ++ rqcf->seq.i_period = rqcx->attr.i_period; ++ rqcf->seq.i_btrate = rqcx->attr.i_btrate; ++ rqcf->seq.i_leadqp = rqcx->attr.i_leadqp; ++ err = 0; ++ break; ++ case RQCT_CFG_DQP: ++ rqcf->dqp.i_dqp = rqcx->attr.i_deltaq; ++ err = 0; ++ break; ++ case RQCT_CFG_QPR: ++ if ((unsigned)rqcf->qpr.i_upperq > 51 || ++ (unsigned)rqcf->qpr.i_lowerq > 51 || ++ rqcf->qpr.i_lowerq > rqcf->qpr.i_upperq) ++ break; ++ rqcf->qpr.i_upperq = rqcx->attr.i_upperq; ++ rqcf->qpr.i_lowerq = rqcx->attr.i_lowerq; ++ err = 0; ++ break; ++ case RQCT_CFG_LOG: ++ rqcf->log.b_logm = !rqcx->attr.b_logoff; ++ err = 0; ++ break; ++ /* private config */ ++ case RQCT_CFG_RES: ++ rqcf->res.i_picw = rqcx->attr.i_pict_w; ++ rqcf->res.i_pich = rqcx->attr.i_pict_h; ++ err = 0; ++ break; ++ case RQCT_CFG_FPS: ++ rqcf->fps.n_fps = rqcx->attr.n_fmrate; ++ rqcf->fps.d_fps = rqcx->attr.d_fmrate; ++ err = 0; ++ break; ++ case RQCT_CFG_ROI: ++ rqcf->roi.i_roidqp = rqcx->attr.i_roidqp[rqcf->roi.i_roiidx]; ++ rqcf->roi.i_posx = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posx; ++ rqcf->roi.i_posy = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posy; ++ rqcf->roi.i_recw = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_recw; ++ rqcf->roi.i_rech = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_rech; ++ err = 0; ++ break; ++ case RQCT_CFG_DQM: ++ rqcf->dqm.u_phys = rqcx->attr.u_dqmphys; ++ rqcf->dqm.p_kptr = rqcx->attr.p_dqmkptr; ++ rqcf->dqm.i_dqmw = rqcx->attr.i_dqmw; ++ rqcf->dqm.i_dqmh = rqcx->attr.i_dqmh; ++ rqcf->dqm.i_size = rqcx->attr.i_dqmsize; ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ return err; ++} ++EXPORT_SYMBOL(mrqc_get_rqcf); ++ ++static int _draw(rqct_att* attr) ++{ ++ int i = 0, enable = 0; ++ char* tbl = (char*)attr->p_dqmkptr + 1; ++ uchar* idc = (char*)attr->p_dqmkptr +16; ++ int mbw = attr->i_dqmw; ++ struct roirec* roi = attr->m_roirec; ++ while (i < RQCT_ROI_NR) ++ { ++ struct roirec* rec = roi++; ++ uchar h, l; ++ int w, j, k, m, n; ++ tbl[i] = attr->i_roidqp[i]; ++ if (tbl[i++] == 0) ++ continue; ++ enable++; ++ n = rec->i_rech; ++ j = rec->i_posy * mbw + rec->i_posx; ++ k = rec->i_recw + j; ++ l = (uchar)i; ++ h = l << 4; ++ for (m = 0; m < n; m++) ++ { ++ uchar* p = idc + (j>>1), q; ++ q = *p; ++ w = j; ++ do ++ switch (w&1) ++ { ++ case 0: ++ if (!(q&0x0F)) q += l; ++ break; ++ case 1: ++ if (!(q&0xF0)) q += h; ++ *p++ = q; ++ q = *p; ++ break; ++ } ++ while (++w < k); ++ *p++ = q; ++ j += mbw; ++ k += mbw; ++ } ++ } ++ idc[0] &=0xF0; ++ return enable; ++} ++ ++int mrqc_roi_draw(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe_rctl* rqcx = (mfe_rctl*)rqct; ++ mfe_regs* regs = (mfe_regs*)mjob; ++ if (0 > rqcx->attr.b_dqmstat) ++ { /* edit qmap and enable it */ ++ MEM_SETV((char*)rqcx->attr.p_dqmkptr +16, 0, rqcx->attr.i_dqmsize-16); ++ if (_draw(&rqcx->attr)) ++ { ++ regs->regf2_g_roi_en = 1; ++ regs->regfb_g_roi_qmap_adr_lo = (ushort)(rqcx->attr.u_dqmphys>> 8); ++ regs->regfc_g_roi_qmap_adr_hi = (ushort)(rqcx->attr.u_dqmphys>>24); ++ rqcx->attr.b_dqmstat = 1; ++ } ++ else ++ { ++ regs->regf2_g_roi_en = 0; ++ regs->regfb_g_roi_qmap_adr_lo = 0; ++ regs->regfc_g_roi_qmap_adr_hi = 0; ++ rqcx->attr.b_dqmstat = 0; ++ } ++#if 0 ++ /* draw qmap on console */ ++ int i, j, w = rqcx->attr.i_dqmw/2; ++ uchar* pl = (char*)rqcx->attr.p_dqmkptr +16; ++ for (i = -1; i < 15; i++) ++ printk("%3d",(int)(signed char)(rqcx->attr.p_dqmkptr+1)[i]); ++ printk("\n"); ++ for (i = 0; i < rqcx->attr.i_dqmh; i++) ++ { ++ for (j = 0; j < rqcx->attr.i_dqmw/2; j++) ++ { ++ uchar qm = pl[w*i+j]; ++ qm = (qm>>4) + (qm<<4); ++ printk("%02X",qm); ++ } ++ printk("\n"); ++ } ++#if 0 ++ printk("qmap-data:\n"); ++ pl = (char*)rqcx->attr.p_dqmkptr; ++ w = 16+(rqcx->attr.i_dqmw*rqcx->attr.i_dqmh+1)/2; ++ for (i = 0; i < w; i++) ++ { ++ printk(" %02X",(unsigned)pl[i]); ++ if ((i%16)==15) ++ printk("\n"); ++ } ++ printk("\n"); ++#endif ++#endif ++ } ++ return (rqcx->attr.b_dqmstat); ++} ++EXPORT_SYMBOL(mrqc_roi_draw); +diff --git a/drivers/mstar/mfev5/mfe5/mfe_rctl.h b/drivers/mstar/mfev5/mfe5/mfe_rctl.h +new file mode 100644 +index 00000000..5f86d59d +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_rctl.h +@@ -0,0 +1,31 @@ ++ ++#ifndef _MFE_RCTL_H_ ++#define _MFE_RCTL_H_ ++ ++#include ++ ++typedef struct mfe_rctl mfe_rctl; ++ ++struct mfe_rctl { ++ rqct_ops rqct; ++ rqct_att attr; ++ int i_period; ++ int i_pcount; ++ #define RCTL_CFG_MB_DQP (1<<0) ++ #define RCTL_CFG_NIGHT (1<<2) ++ int i_config; ++}; ++ ++void* rqctmfe_acquire(int); ++char* rqctmfe_comment(int); ++ ++/* basic functions of mfe rate-controller */ ++int mrqc_set_rqcf(rqct_ops* rqct, rqct_cfg* rqcf); ++int mrqc_get_rqcf(rqct_ops* rqct, rqct_cfg* rqcf); ++int mrqc_enc_buff(rqct_ops* rqct, rqct_buf* buff); ++int mrqc_roi_draw(rqct_ops* rqct, mhve_job* mjob); ++/* functions to insert/remove additional rate-controller */ ++int rqctmfe_insert(void*(*allc)(void), char*(*desc)(void)); ++int rqctmfe_remove(void); ++ ++#endif/*_MFE_RCTL_H_*/ +diff --git a/drivers/mstar/mfev5/mfe5/mfe_regs.h b/drivers/mstar/mfev5/mfe5/mfe_regs.h +new file mode 100644 +index 00000000..77bb7d35 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_regs.h +@@ -0,0 +1,1162 @@ ++ ++#ifndef _MFE_REGS_H_ ++#define _MFE_REGS_H_ ++ ++#include ++ ++// IRQ's ++#define IRQ_LESS_ROW_DONE 7 ++#define IRQ_NET_TRIGGER 6 ++#define IRQ_FS_FAIL 5 ++#define IRQ_TXIP_TIME_OUT 4 ++#define IRQ_BSPOBUF_FULL 3 ++#define IRQ_IMG_BUF_FULL 2 ++#define IRQ_MARB_BSPOBUF_FULL 1 ++#define IRQ_FRAME_DONE 0 ++ ++#define CHECK_IRQ_STATUS(r,irq) ((r>>irq)&1) ++ ++typedef struct mfe_regs { ++ mhve_job mjob; ++ /* sw-coded data followed by mfe-output stream */ ++ uchar coded[8]; ++ int count; ++ int delta; ++ /* miu address for mfe-hw */ ++ uint obase[2]; ++ int osize[2]; ++ /* ticks for profiling */ ++ uint cycles; ++ uint bitcnt; ++ uint sumofq; ++ /* mfe-regs bank definition */ ++ union { ++ struct { ++ ushort reg00_g_frame_start_sw:1; // frame start (1T clk_mfe) ++ ushort reg00_g_soft_rstz:1; // software reset; 0/1: reset/not reset ++ ushort reg00_g_enc_mode:2; // 0/1/2/3: MPEG4/H263/H264/JPEG ++ #define MFE_REG_ENC_MPG4 0 ++ #define MFE_REG_ENC_H263 1 ++ #define MFE_REG_ENC_H264 2 ++ #define MFE_REG_ENC_JPEG 3 ++ ushort reg00_g_frame_type:2; // 0/1/2: I/P/B ++ #define MFE_REG_ITYPE 0 ++ #define MFE_REG_PTYPE 1 ++ #define MFE_REG_BTYPE 2 ++ ushort reg00_g_ref_no:1; // 0/1: 1 frame/2 frames ++ #define MFE_REG_REF_NUM_ONE 0 ++ #define MFE_REG_REF_NUM_TWO 1 ++ ushort reg00_g_mbr_en:1; // 0/1: disable/enable MB-level Rate control ++ ushort reg00_g_qscale:6; // frame level qscale: [H264]: 1 ~ 51; [MPEG4]: 1 ~ 31 ++ ushort reg00_g_rec_en:1; // reconstruct enable ++ ushort reg00_g_jpe_mst422_mode:1; // YUV422 input buffer format; 0: YUYV, 1: MST422 ++ }; ++ ushort reg00; ++ }; ++ union { ++ struct { ++ ushort reg01_g_pic_width:16; // picture width ++ }; ++ ushort reg01; ++ }; ++ union { ++ struct { ++ ushort reg02_g_pic_height:16; // picture height ++ }; ++ ushort reg02; ++ }; ++ union { ++ struct { ++ ushort reg03_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off ++ ushort reg03_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) ++ ushort reg03_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV ++ ushort reg03_g_qmode:1; // quantization method; 0/1: h263/mp4 ++ ushort reg03_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control ++ ushort reg03_g_fldpic_en:1; // field picture coding ++ ushort reg03_g_dct_only_en:1; // regmfe_g_dct_only_en ++ ushort reg03_g_mstar_tile:1; ++ ushort reg03_g_mstar_tile_field_split:1; ++ ushort reg03_g_fldpic_idx:1; ++ ushort reg03_g_fldpic_multislice_en:1; ++ ushort reg03_g_cabac_en:1; ++ ushort reg03_non_secure:1; ++ }; ++ ushort reg03; ++ }; ++ union { ++ struct { ++ ushort reg04_g_er_bs_th:16; // er_bs mode threshold ++ }; ++ ushort reg04; ++ }; ++ union { ++ struct { ++ ushort reg05_g_inter_pref:16; // inter prediction preference ++ }; ++ ushort reg05; ++ }; ++ union { ++ struct { ++ ushort reg06_g_cur_y_addr_lo:16; // current luma base address ++ }; ++ ushort reg06; ++ }; ++ union { ++ struct { ++ ushort reg07_g_cur_y_addr_hi:8; // current luma base address ++ }; ++ ushort reg07; ++ }; ++ union { ++ struct { ++ ushort reg08_g_cur_c_addr_lo:16; // current chroma base address ++ }; ++ ushort reg08; ++ }; ++ union { ++ struct { ++ ushort reg09_g_cur_c_addr_hi:8; // current chroma base address ++ }; ++ ushort reg09; ++ }; ++ union { ++ struct { ++ ushort reg0a_g_ref_y_addr0_lo:16; // reference luma base address0 ++ }; ++ ushort reg0a; ++ }; ++ union { ++ struct { ++ ushort reg0b_g_ref_y_addr0_hi:8; // reference luma base address0 ++ }; ++ ushort reg0b; ++ }; ++ union { ++ struct { ++ ushort reg0c_g_ref_y_addr1_lo:16; // reference luma base address1 ++ }; ++ ushort reg0c; ++ }; ++ union { ++ struct { ++ ushort reg0d_g_ref_y_addr1_hi:8; // reference luma base address0 ++ }; ++ ushort reg0d; ++ }; ++ union { ++ struct { ++ ushort reg0e_g_ref_c_addr0_lo:16; // reference chroma base address0 ++ }; ++ ushort reg0e; ++ }; ++ union { ++ struct { ++ ushort reg0f_g_ref_c_addr0_hi:8; // reference chroma base address0 ++ }; ++ ushort reg0f; ++ }; ++ union { ++ struct { ++ ushort reg10_g_ref_c_addr1_lo:16; // reference chroma base address1 ++ }; ++ ushort reg10; ++ }; ++ union { ++ struct { ++ ushort reg11_g_ref_c_addr1_hi:8; // reference chroma base address1 ++ }; ++ ushort reg11; ++ }; ++ union { ++ struct { ++ ushort reg12_g_rec_y_addr_lo:16; // reconstructed luma base address ++ }; ++ ushort reg12; ++ }; ++ union { ++ struct { ++ ushort reg13_g_rec_y_addr_hi:8; // reconstructed luma base address ++ }; ++ ushort reg13; ++ }; ++ union { ++ struct { ++ ushort reg14_g_rec_c_addr_lo:16; // reconstructed chroma base address ++ }; ++ ushort reg14; ++ }; ++ union { ++ struct { ++ ushort reg15_g_rec_c_addr_hi:8; // reconstructed chroma base address ++ }; ++ ushort reg15; ++ }; ++ union { ++ struct { // clock gating ++ ushort gate_cry_crc_sram:1; ++ ushort gate_qtab_dbfdc_dbqtb_sram:1; ++ ushort gate_mcy_mcc_sram:1; ++ ushort gate_res0_res1_sram:1; ++ ushort gate_ieap:1; ++ ushort gate_dct_idct:1; ++ ushort gate_dbf:1; ++ }; ++ ushort reg16; ++ }; ++ union { ++ struct { ++ ushort reg17_s_auto_rst_wait_cnt:6; // the waiting count for regen_soft_rstz and regen_fs_sw generation ++ ushort reg17_g_sram1p_wp_type:1; // "MFE 1p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" ++ ushort reg17_g_sram2p_wp_type:1; // "MFE 2p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" ++ ushort reg17_g_clk_mfe_en:4; // NOT used now. ++ ushort reg17_g_mreq_sel:1; // "1" D1 MIU clk gating; "0" dynamic MIU clk gating ++ ushort reg17_g_mreq_always_active:1; // "1" mreq always active; "0" make mreq active according to FSM. (let this be default) ++ ushort reg17_g_clk_miu_d2_gate:1; // b1: turn off miu clock of power-domain "dma" and sleep into d2 mode ++ ushort reg17_g_clk_mfe_d2_gate:1; // b1: turn off mfe clock of power-domain "core" and sleep into d2 mode ++ }; ++ ushort reg17; ++ }; ++ // [JPEG] ++ union { ++ struct { ++ ushort reg18_g_jpe_enc_mode:2; // JPE encode mode; 2'b00/2'b01/2'b10/2'b11: 420/422/444/gray; current version supports 422 only ++ ushort reg18_g_jpe_buffer_mode:1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode ++ ushort reg18_g_jpe_multibuf_mode:2; // JPE multi-buffer mode; 0/1/2: 2/4/8 buffers ++ ushort reg18_g_jpe_qfactor:4; // JPE q factor; 0 ~ 15: (1 ~ 16)/4 ++ // (M1)JPE fsvs generation mode; ++ // 0: pure sw ++ // 1: sw+hw ++ // 2: hw w/o auto-restart ++ // 3: hw w/i auto-restart ++ ushort reg18_g_jpe_fsvs_mode:2; // (T8)JPE fsvs generation mode; 0/1/2: pure sw/sw+hw/hw ++ ushort reg18_reserved:3; ++ ushort reg18_g_jpe_turbo_en:1; // 0: turbo mode off, 1: turbo mode enabled ++ ushort reg18_g_viu_soft_rstz:1; // viu software reset; 0/1: reset/not reset ++ }; ++ ushort reg18; ++ }; ++ // [MPEG4/H263] ++ union { ++ struct { ++ ushort reg19_g_mp4_itlc:1; // 0/1: MPEG4 progressive/interlaced mode ++ ushort reg19_g_mp4_pskip_off:1; // 0/1: MPEG4 enable/disable p skip mode ++ ushort reg19_g_mp4_acp:2; // [0]: 0/1: sw/hw acp selection; [1]: sw default value: 0/1: disable/enable acp; current version off ++ ushort reg19_g_mp4_rounding_ctrl:1; // mp4 rounding control specified as in spec ++ ushort reg19_g_er_hec:1; // 0/1: header extension code off/on ++ ushort reg19_g_er_hec_t:3; // HEC counter reset values ++ ushort reg19_g_er_h263_unit:2; // 0/1/2: unit is 1/2/4, for calculating gob_num. ++ ushort reg19_g_mp4_direct_en:1; // MPEG4 direct enable ++ ushort reg19_g_mp4_direct_mvstore:1; // [M]: enable storing of mv & skip_mb information to DRAM in P(or sometimes I) frame ++ }; ++ ushort reg19; ++ }; ++ union { ++ struct { ++ ushort reg1a_g_mp4_direct_pref:8; // used in mp4 only, mp4 direct mode preference value ++ ushort reg1a_g_mp4_direct_trb:3; // used in mp4 only, mp4 direct mode trb (P0-B distance) ++ ushort reg1a_g_mp4_direct_trd:3; // used in mp4 only, mp4 direct mode trd (P0-P1 distance) ++ }; ++ ushort reg1a; ++ }; ++ union { ++ struct { ++ ushort reg1b_g_mp4_flddct_diff_thr:8; // used in mp4 only, mp4 field dct difference threshold ++ ushort reg1b_g_mp4_flddct_en:1; // used in mp4 only, mp4 field dct enable ++ }; ++ ushort reg1b; ++ }; ++ // [IRQ & important IP status checkings] ++ union { ++ struct { ++ ushort reg1c_g_irq_mask:8; // 0/1: irq not-mask/mask ++ ushort reg1c_g_irq_force:8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt ++ }; ++ ushort reg1c; ++ }; ++ union { ++ struct { ++ ushort reg1d_g_irq_clr0:1; // 0/1: not clear interrupt/clear interrupt 0 ++ ushort reg1d_g_irq_clr1:1; // 0/1: not clear interrupt/clear interrupt 1 ++ ushort reg1d_g_irq_clr2:1; // 0/1: not clear interrupt/clear interrupt 2 ++ ushort reg1d_g_irq_clr3:1; // 0/1: not clear interrupt/clear interrupt 3 ++ ushort reg1d_g_irq_clr4:1; // 0/1: not clear interrupt/clear interrupt 4 ++ ushort reg1d_g_irq_clr5:1; // 0/1: not clear interrupt/clear interrupt 5 ++ ushort reg1d_g_irq_clr6:1; // 0/1: not clear interrupt/clear interrupt 6 ++ ushort reg1d_g_irq_clr7:1; // 0/1: not clear interrupt/clear interrupt 7 ++ ushort reg1d_g_swrst_safe:1; // to indicate there're no miu activities that need to pay attention to ++ }; ++ ushort reg1d; ++ }; ++ union { ++ struct { ++ // status of interrupt on CPU side ++ // ({1'b0,net_trigger,fs_fail_irq, txip_time_out,early_bspobuf_full_irq/buf1_full,img_buf_full_irq,marb_bspobuf_ful/buf0_full,frame_done_irq}) ++ // [3] SW mode: early obuf full; HW mode: buf1 full ++ // [1] SW mode: buf full; HW mode: buf0 full ++ ushort reg1e_g_irq_cpu:8; ++ // status of interrupt on IP side ++ // ({1'b0,net_trigger,fs_fail_irq, txip_time_out,early_bspobuf_full_irq/buf1_full,img_buf_full_irq,marb_bspobuf_ful/buf0_full,frame_done_irq}) ++ // [3] SW mode: early obuf full; HW mode: buf1 full ++ // [1] SW mode: buf full; HW mode: buf0 full ++ ushort reg1e_g_irq_ip:8; ++ }; ++ ushort reg1e; ++ }; ++ union { ++ struct { ++ ushort reserved_reg1f; ++ }; ++ ushort reg1f; ++ }; ++ // [ME setting] ++ union { ++ struct { ++ ushort reg20_s_me_4x4_disable:1; // 4x4_disable ++ ushort reg20_s_me_8x4_disable:1; // 8x4_disable ++ ushort reg20_s_me_4x8_disable:1; // 4x8_disable ++ ushort reg20_s_me_16x8_disable:1; // 16x8_disable ++ ushort reg20_s_me_8x16_disable:1; // 8x16_disable ++ ushort reg20_s_me_8x8_disable:1; // 8x8_disable ++ ushort reg20_s_me_16x16_disable:1; // 16x16_disable ++ ushort reg20_s_mesr_adapt:1; // me search range auto-adaptive; 0/1: off/on ++ ushort reg20_s_me_ref_en_mode:2; // ref enable mode: 2'b01/2'b10/2'b11: ref0 enable/ref1 enable/ref0&1 enable ++ }; ++ ushort reg20; ++ }; ++ // [IME PIPELINE] ++ union { ++ struct { ++ ushort reg21_s_ime_sr16:1; // search range limited to (h,v) = (+/-16, +/-16); 0/1: search range 32/16 ++ ushort reg21_s_ime_umv_disable:1; // 0/1: UMV enable/disable ++ ushort reg21_s_ime_ime_wait_fme:1; // 0/1: ime wait fme/fme wait ime ++ ushort reg21_s_ime_boundrect_en:1; // ime bounding rectangle enable (needed for level 3.0 and below) ++ ushort reg21_s_ime_h264_p8x8_ctrl_en:1; // ime h264 max p8x8 count control enable ++ ushort reg21_reserved:3; ++ ushort reg21_s_ime_h264_p8x8_max:8; // ime h264 max p8x8 count; value 0 is prohibited ++ // Max P8x8 MB count = 16 * reg21_s_ime_h264_p8x8_max ++ }; ++ ushort reg21; ++ }; ++ union { ++ struct { ++ ushort reg22_s_ime_mesr_max_addr:8; // me search range max depth ++ ushort reg22_s_ime_mesr_min_addr:8; // me search range min depth ++ }; ++ ushort reg22; ++ }; ++ union { ++ struct { ++ ushort reg23_s_ime_mvx_min:6; // me mvx min; 0/.../62 --> -32/.../30 ++ ushort reg23_reserved:2; ++ ushort reg23_s_ime_mvx_max:6; // me mvx max; 0/.../62 --> -32/.../30 ++ }; ++ ushort reg23; ++ }; ++ union { ++ struct { ++ ushort reg24_s_ime_mvy_min:6; // me mvy min; 0/.../62 --> -32/.../30 ++ ushort reg24_reserved:2; ++ ushort reg24_s_ime_mvy_max:6; // me mvy max; 0/.../62 --> -32/.../30 ++ }; ++ ushort reg24; ++ }; ++ // [FME pipeline] ++ union { ++ struct { ++ ushort reg25_s_fme_quarter_disable:1; // 0/1: Quarter fine-tune enable/disable ++ ushort reg25_s_fme_half_disable:1; // 0/1: Half fine-tune enable/disable ++ ushort reg25_reserved:1; ++ ushort reg25_s_fme_pmv_enable:1; // 0/1: disable/enable Previous Skip MV mode ++ ushort reg25_s_fme_mode_no:1; // 0: one mode. 1: two mode. ++ ushort reg25_s_fme_mode0_refno:1; // 0: one ref. for mode0 1: two ref. for mode0 ++ ushort reg25_s_fme_mode1_refno:1; // 0: one ref. for mode1 1: two ref. for mode1 ++ ushort reg25_s_fme_mode2_refno:1; // 0: one ref. for mode2 1: two ref. for mode2 ++ ushort reg25_s_fme_skip:1; // fme skip ++ ushort reg25_s_fme_pipeline_on:1; // 0/1: FME pipeline off/on ++ }; ++ ushort reg25; ++ }; ++ // MBR ++ union { ++ struct { ++ ushort reg26_s_mbr_pqp_dlimit:2; // previous qp diff limit ++ ushort reg26_s_mbr_uqp_dlimit:2; // upper qp diff limit ++ ushort reg26_s_mbr_tmb_bits:12; // target MB bits ++ }; ++ ushort reg26; ++ }; ++ union { ++ struct { ++ ushort reg27_s_mbr_frame_qstep:13; // frame level qp's qstep ++ ushort reg27_s_mbr_new_lambda:1; ++ ushort reg27_s_mbr_tbl_woc_write:1; ++ ushort reg27_s_mbr_tbl_woc_done_clr:1; ++ }; ++ ushort reg27; ++ }; ++ union { ++ struct { ++ ushort reg28_s_mbr_last_frm_avg_qp_lo:16; // last frame average qp (status register) ++ }; ++ ushort reg28; ++ }; ++ union { ++ struct { ++ ushort reg29_s_mbr_last_frm_avg_qp_hi:8; // last frame average qp (status register) ++ ushort reg29_s_mbr_qp_cidx_offset:5; // [H264] chroma qp index offset (+12). Spec range is [-12,12] ++ }; ++ ushort reg29; ++ }; ++ union { ++ struct { ++ ushort reg2a_s_mbr_qp_min:6; // qp min ++ ushort reg2a_s_mbr_qp_max:6; // qp max ++ ushort reg2a_s_mvdctl_ref0_offset:2;// H264 mvy offset adjustment for MCC if ref is frame 0: 0/1/2: 0/+2/-2 ++ ushort reg2a_s_mvdctl_ref1_offset:2;// H264 mvy offset adjustment for MCC if ref is frame 1: 0/1/2: 0/+2/-2 ++ }; ++ ushort reg2a; ++ }; ++ // IEAP ++ union { ++ struct { ++ ushort reg2b_s_ieap_last_mode:4; // software control of the last mode of Intra4x4 mode 0 ~ 8 ++ ushort reg2b_s_ieap_constraint_intra:1; // software control constraint intra; 0/1: OFF/ON ++ ushort reg2b_s_ieap_ccest_en:1; // software control cost estimator; 0/1: OFF/ON ++ ushort reg2b_s_ieap_ccest_thr:2; // threshold of cost estimator set 0 ~ 3 for threshold 1 ~ 4 ++ ushort reg2b_s_ieap_drop_i16:1; // software control stop-Intra16x16-mode; 1:w/o I16M, 0:w/i I16MB ++ ushort reg2b_s_ieap_early_termination:1; ++ }; ++ ushort reg2b; ++ }; ++ // QUAN ++ union { ++ struct { ++ ushort reg2c_s_quan_idx_last:6; // the index of the last non-zero coefficient in the zig-zag order ++ ushort reg2c_s_quan_idx_swlast:1; // software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable ++ ushort reg2c_reserved:8; ++ ushort reg2c_g_ieap_sram_4x2_swap:1; ++ }; ++ ushort reg2c; ++ }; ++ // TXIP control & debug ++ union { ++ struct { ++ ushort reg2d_s_txip_mbx:9; // txip mbx ++ ushort reg2d_s_txip_sng_mb:1; // 0/1: disable/enable txip controller stop-and-go mechanism using ++ // (txip_mbx == reg71_g_debug_trig_mbx) & (txip_mby == reg72_g_debug_trig_mby) ++ ushort reg2d_s_txip_sng_set:1; // txip controller stop-and-go mechanism using this register bit: ++ // 0/1: go/stop ++ ushort reg2d_s_txip_dbf_full_halt_en:1; // txip controller stop-and-go mechanism using double buffer fullness as criterion: ++ // 0/1: disable/enable ++ ushort reg2d_s_txip_ack2fme_mode:1; ++ }; ++ ushort reg2d; ++ }; ++ union { ++ struct { ++ ushort reg2e_s_txip_mby:9; // txip mby ++ }; ++ ushort reg2e; ++ }; ++ union { ++ struct { ++ ushort reg2f_s_txip_irfsh_mb_s0:13; // intra refresh mb start 0 ++ ushort reg2f_reserved:1; ++ ushort reg2f_s_txip_irfsh_en:2; // intra refresh enable bits: bit0: enable condition 0; bit 1: enable condition 1 ++ }; ++ ushort reg2f; ++ }; ++ union { ++ struct { ++ ushort reg30_s_txip_irfsh_mb_e0:13; // intra refresh mb end 0 ++ }; ++ ushort reg30; ++ }; ++ union { ++ struct { ++ ushort reg31_s_txip_irfsh_mb_s1:13; // intra refresh mb start 1 ++ }; ++ ushort reg31; ++ }; ++ union { ++ struct { ++ ushort reg32_s_txip_irfsh_mb_e1:13; // intra refresh mb end 1 ++ ushort reg32_reserved:1; ++ ushort reg32_s_txip_timeout_en:1; // txip time out enable ++ ushort reg32_s_txip_wait_mode:1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count ++ }; ++ ushort reg32; ++ }; ++ union { ++ struct { ++ ushort reg33_s_txip_idle_cnt:16; // wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) ++ }; ++ ushort reg33; ++ }; ++ union { ++ struct { ++ ushort reg34_s_txip_timeout:16; // txip timeout count (x 64T) ++ }; ++ ushort reg34; ++ }; ++ // [ECDB PIPELINE] ++ // ECDB control & debug ++ union { ++ struct { ++ ushort reg35_s_ecdb_mbx:13; // ecdb mbx ++ }; ++ ushort reg35; ++ }; ++ union { ++ struct { ++ ushort reg36_s_ecdb_mby:13; // ecdb mby ++ }; ++ ushort reg36; ++ }; ++ // MDC ++ union { ++ struct { ++ ushort reg37_s_mdc_total_mb_bw:4; // total mb bit width used in video_pkt ++ ushort reg37_s_mdc_m4vpktpzero:1; // MPEG4 video packet preceding zeros: 0/1: 16/17 zeros ++ ushort reg37_s_mdc_m4timev:2; // MPEG4 modulo time base: 0/1/2/3: 0/10/110/1110 ++ ushort reg37_s_mdc_m4iadcvlc_th:3; // MPEG4 intra dc vlc threshold ++ ushort reg37_s_mdc_m4vop_tinc_bw:4; // vop_time_increment bit width ++ }; ++ ushort reg37; ++ }; ++ union { ++ struct { ++ ushort reg38_s_mdc_m4vop_tinc:15; // vop_time_increment ++ }; ++ ushort reg38; ++ }; ++ union { ++ struct { ++ ushort reg39_s_mdc_gob_frame_id:2; // H263 gob frame id ++ ushort reg39_s_mdc_h264_nal_ref_idc:2; // nal_ref_idc ++ ushort reg39_s_mdc_h264_nal_unit_type:1; // 0/1: 1/5 ++ ushort reg39_s_mdc_h264_fnum_bits:2; // H264 frame num bits ++ ushort reg39_s_mdc_h264_dbf_control:1; // dbf control present flag ++ ushort reg39_s_mdc_h264_fnum_value:8; // H264 frame num value ++ }; ++ ushort reg39; ++ }; ++ union { ++ struct { ++ ushort reg3a_s_mdc_h264_idr_pic_id:3; ++ ushort reg3a_s_mdc_h264_disable_dbf_idc:2; ++ ushort reg3a_s_mdc_h264_alpha:4; // slice_alpha_c0_offset_div2 ++ ushort reg3a_s_mdc_h264_beta:4; // slice_beta_offset_div2 ++ ushort reg3a_s_mdc_h264_ridx_aor_flag:1; // reference index active override flag ++ ushort reg3a_miu_sel:2; ++ }; ++ ushort reg3a; ++ }; ++ // BSPOBUF/MVOBUF ++ union { ++ struct { ++ ushort reg3b_s_bspobuf_set_adr:1; // set bsp obuf start address(write one clear) ++ ushort reg3b_s_mvobuf_set_adr:1; // set mv obuf start address (write one clear) ++ ushort reg3b_s_bspobuf_fifo_th:3; // bsp obuf threshold ++ ushort reg3b_s_mvobuf_fifo_th:3; // mv obuf threshold ++ ushort reg3b_s_bsp_fdc_skip:1; // fdc skip enable; 0: fdc skip disable, 1: fdc skip enable ++ ushort reg3b_reserved:5; ++ ushort reg3b_s_obuf_toggle_obuf0_status:1; // toggle buf0 status(write one clear) ++ ushort reg3b_s_obuf_toggle_obuf1_status:1; // toggle buf1 status(write one clear) ++ }; ++ ushort reg3b; ++ }; ++ union { ++ struct { ++ ushort reg3c_s_bspobuf_lo:16; // bsp obuf start address ++ }; ++ ushort reg3c; ++ }; ++ union { ++ struct { ++ ushort reg3d_s_bspobuf_hi:13; // bsp obuf address high ++ ushort reg3d_reserved:1; ++ ushort reg3d_s_obuf_id:2; // 00: s0, 01: e0, 10: s1, 11: e1 ++ }; ++ ushort reg3d; ++ }; ++ union { ++ struct { ++ ushort reg3e_s_obuf_write_id_adr:1; // write to this address to enable writing of bspobuf address ++ }; ++ ushort reg3e; ++ }; ++ union { ++ struct { ++ ushort reg3f_s_bspobuf_hw_en:1; // enable HW obuf automatic mechanism ++ ushort reg3f_s_bspobuf_update_adr:1; // update obuf address(write one clear) ++ ushort reg3f_s_bspobuf_adr_rchk_sel:2; // obuf adr read back check selection: 0/1/2/3: s0/e0/s1/e1 ++ ushort reg3f_s_bspobuf_adr_rchk_en:1; // enable bspobuf adr read back check through regmfe_s_bspobuf_wptr ++ ushort reg3f_reserved:3; ++ ushort reg3f_s_bsp_fdc_offset:7; // bsp's fdc offset ++ }; ++ ushort reg3f; ++ }; ++ union { ++ struct { ++ ushort reg40_s_mvobuf_saddr_lo:16; // mv obuf start address ++ }; ++ ushort reg40; ++ }; ++ union { ++ struct { ++ ushort reg41_s_mvobuf_saddr_hi:13; // mv obuf start address ++ }; ++ ushort reg41; ++ }; ++ union { ++ struct { ++ ushort reg42_s_bsp_bit_cnt_lo:16; // encoded bit count (one frame) ++ }; ++ ushort reg42; ++ }; ++ union { ++ struct { ++ ushort reg43_s_bsp_bit_cnt_hi:8; // encoded bit count (one frame) ++ }; ++ ushort reg43; ++ }; ++ union { ++ struct { ++ ushort reg44_s_bspobuf_wptr_lo:16; // bspobuf write pointer (8 byte unit) ++ }; ++ ushort reg44; ++ }; ++ union { ++ struct { ++ ushort reg45_s_bspobuf_wptr_hi:13; // bspobuf write pointer (8 byte unit) ++ }; ++ ushort reg45; ++ }; ++ // FDC ++ union { ++ struct { ++ ushort reg46_s_fdc_bs:16; // cpu to fdc bitstream data ++ }; ++ ushort reg46; ++ }; ++ union { ++ struct { ++ ushort reg47_s_fdc_bs_len:5; // cpu to fdc bitstream len; 0 ~ 16 ++ ushort reg47_s_fdc_bs_count:10; // cpu to fdc round count ++ }; ++ ushort reg47; ++ }; ++ // [Table Control] ++ union { ++ struct { ++ ushort reg48_s_fdc_ack:1; // fdc to cpu ack; 0/1: frame data pool not empty/frame data pool empty; 48x64 bits of space ++ ushort reg48_s_fdc_done_clr:1; // fdc done clear (write one clear) ++ ushort reg48_s_fdc_done:1; // fdc done; indicate to CPU that data has been written to internal buffer ++ ushort reg48_reserved:8; ++ ushort reg48_s_fdc_bs_vld:1; // set for bitstream write out (write one clear) ++ ushort reg48_s_tbc_en:1; // set for table read & write ; 1: enable, 0: disable (write one clear) ++ }; ++ ushort reg48; ++ }; ++ union { ++ struct { ++ ushort reg49_s_tbc_rw:1; // table mode; 0: read, 1: write ++ ushort reg49_s_tbc_done_clr:1; // table done clear (write one clear) ++ ushort reg49_s_tbc_done:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg4b_s_tbc_rdata ++ ushort reg49_reserved:5; ++ ushort reg49_s_tbc_adr:6; // table address ++ }; ++ ushort reg49; ++ }; ++ union { ++ struct { ++ ushort reg4a_s_tbc_wdata:16; // table write data ++ }; ++ ushort reg4a; ++ }; ++ union { ++ struct { ++ ushort reg4b_s_tbc_rdata:16; // table read data ++ }; ++ ushort reg4b; ++ }; ++ // [Get Neighbor] ++ union { ++ struct { ++ ushort reg4c_s_gn_saddr_lo:16; // gn base adr low ++ }; ++ ushort reg4c; ++ }; ++ union { ++ struct { ++ ushort reg4d_s_gn_saddr_hi:13; // gn base adr high ++ ushort reg4d_reserved:2; ++ ushort reg4d_s_gn_saddr_mode:1; // 1: gn save data in one frame 0: gn save data in one row ++ }; ++ ushort reg4d; ++ }; ++ union { ++ struct { ++ ushort reg4e_s_gn_mvibuf_saddr_lo:16; // mv ibuf start address low ++ }; ++ ushort reg4e; ++ }; ++ union { ++ struct { ++ ushort reg4f_s_gn_mvibuf_saddr_hi:13; // mv ibuf start address high ++ ushort reg4f_reserved:1; ++ ushort reg4f_s_gn_bwr_mode:2; ++ }; ++ ushort reg4f; ++ }; ++ union { ++ struct { ++ ushort reg56_s_marb_mrpriority_sw:2; // mfe2mi_rpriority software programmable ++ ushort reg56_s_marb_mr_timeout_ref:1; // miu read burst timeout count start point ++ ushort reg56_s_marb_mr_nwait_mw:1; // miu read not wait mi2mfe_wrdy ++ ushort reg56_s_marb_mwpriority_sw:2; // mfe2mi_wpriority software programmable ++ ushort reg56_s_marb_mw_timeout_ref:1; // miu write burst timeout count start point ++ ushort reg56_s_marb_mw_nwait_mr:1; // miu read not wait mi2mfe_wrdy ++ ushort reg56_s_marb_mr_pending:4; // max. pending read requests to miu ++ ushort reg56_s_marb_32b_ad_nswap:1; // 32bits miu address not swap. only for 32bits mode ++ ushort reg56_s_marb_miu_wmode:1; // 0/1: original miu protocol/new miu protocol(wd_en) ++ ushort reg56_s_marb_rp_ordering:1; ++ }; ++ ushort reg56; ++ }; ++ union { ++ struct { ++ ushort reg58_s_marb_ubound_0_lo:16; // MIU protect for MPEG4 BSP obuf ++ }; ++ ushort reg58; ++ }; ++ union { ++ struct { ++ ushort reg59_s_marb_ubound_0_hi:13; // MIU protect for MPEG4 BSP obuf ++ ushort reg59_reserved:3; ++ }; ++ ushort reg59; ++ }; ++ union { ++ struct { ++ ushort reg5a_s_marb_lbound_0_lo:16; // MIU protect for MPEG4 BSP obuf ++ }; ++ ushort reg5a; ++ }; ++ union { ++ struct { ++ ushort reg5b_s_marb_lbound_0_hi:13; // MIU protect for MPEG4 BSP obuf ++ ushort reg5b_s_marb_miu_bound_en_0:1; ++ }; ++ ushort reg5b; ++ }; ++ union { ++ struct { ++ ushort reg5c_s_marb_ubound_1_lo:16; // MIU Upper bound protect for MPEG4 MC obuf rec ++ }; ++ ushort reg5c; ++ }; ++ union { ++ struct { ++ ushort reg5d_s_marb_ubound_1_hi:13; // MIU Upper bound protect for MPEG4 MC obuf rec ++ }; ++ ushort reg5d; ++ }; ++ union { ++ struct { ++ ushort reg5e_s_marb_lbound_1_lo:16; // MIU Lower bound protect for MPEG4 MC obuf ++ }; ++ ushort reg5e; ++ }; ++ union { ++ struct { ++ ushort reg5f_s_marb_lbound_1_hi:13; // MIU Lower bound protect for MPEG4 MC obuf ++ ushort reg5f_s_marb_miu_bound_en_1:1; //miu write protection, miu bound enable for write port 1 ++ }; ++ ushort reg5f; ++ }; ++ union { ++ struct { ++ ushort reg60_s_marb_ubound_2_lo:16; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg60; ++ }; ++ union { ++ struct { ++ ushort reg61_s_marb_ubound_2_hi:13; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg61; ++ }; ++ union { ++ struct { ++ ushort reg62_s_marb_lbound_2_lo:16; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg62; ++ }; ++ union { ++ struct { ++ ushort reg63_s_marb_lbound_2_hi:13; // MIU protect for MPEG4 MV obuf ++ ushort reg63_s_marb_miu_bound_en_2:1; // miu write protection, miu bound enable for write port 2 ++ }; ++ ushort reg63; ++ }; ++ union { ++ struct { ++ ushort reg64_s_marb_ubound_3_lo:16; // MIU protect for MPEG4 GN ++ }; ++ ushort reg64; ++ }; ++ union { ++ struct { ++ ushort reg65_s_marb_ubound_3_hi:13; // MIU protect for MPEG4 GN ++ }; ++ ushort reg65; ++ }; ++ union { ++ struct { ++ ushort reg66_s_marb_lbound_3_lo:16; // MIU protect for MPEG4 GN ++ }; ++ ushort reg66; ++ }; ++ union { ++ struct { ++ ushort reg67_s_marb_lbound_3_hi:13; // MIU protect for MPEG4 GN ++ ushort reg67_s_marb_miu_bound_en_3:1; ++ ushort reg67_s_marb_miu_off:1; ++ ushort reg67_s_marb_miu_bound_err:1; ++ }; ++ ushort reg67; ++ }; ++ union { ++ struct { ++ ushort reg68_s_marb_eimi_block:1; // miu emi/imi block, 0: disable ++ ushort reg68_s_marb_lbwd_mode:1; // low bandwidth mode, 0: disable ++ ushort reg68_s_marb_imi_burst_thd:5;// imi write burst bunch up threshold ++ ushort reg68_s_marb_imi_timeout:3; // imi write burst timeout ++ ushort reg68_s_marb_imilast_thd:4; // auto mfe2imi_last threshold ++ ushort reg68_s_prfh_cryc_en:1; // 0: disable prfh_cryc circuit, 1: enable prfh_cryc circuit ++ ushort reg68_s_prfh_refy_en:1; // 0: disable prfh_refy circuit, 1: enable prfh_refy circuit ++ }; ++ ushort reg68; ++ }; ++ union { ++ struct { ++ ushort reg69_g_pat_gen_init:16; // pattern generation initial value ++ }; ++ ushort reg69; ++ }; ++ union { ++ struct { ++ ushort reg6a_s_bspobuf_idx:2; // HW obuf index(0->1->2->3->0->1¡K) ++ // SW obuf index(00->01->11->10->00...) ++ ushort reg6a_s_obuf0_status:1; ++ ushort reg6a_s_obuf1_status:1; ++ // regmfe_s_bspobuf_adr_status:6 ++ // {reg6a_fifo_not_full, reg6a_fifo_not_empty, reg6a_enable_obufadr_update, reg6a_obufadr_update_cnt[2:0]} ++ ushort reg6a_obufadr_update_cnt:3; ++ ushort reg6a_enable_obufadr_update:1; ++ ushort reg6a_fifo_not_empty:1; ++ ushort reg6a_fifo_not_full:1; ++ }; ++ ushort reg6a; ++ }; ++ union { ++ struct { ++ ushort reg6b_s_marb_imi_saddr_lo:16; // imi base address for low bandwidth mode (in 8-byte unit) ++ }; ++ ushort reg6b; ++ }; ++ union { ++ struct { ++ ushort reg6c_s_marb_imi_saddr_hi:13; ++ ushort reg6c_s_marb_rimi_force:1; // b1:force all read path to IMI 'b0:Normal ++ ushort reg6c_s_marb_imi_cache_size:2; // imi cache size (0: 64kB, 1:32kB, 2:16kB, 3:8kB) ++ }; ++ ushort reg6c; ++ }; ++ union { ++ struct { ++ ushort reg6d_s_marb_imipriority_thd:4; // hardware mfe2imi_priority threshold ++ ushort reg6d_s_marb_imipriority_sw:2; // mfe2imi_priority software programmable ++ ushort reg6d_reserved:2; ++ ushort reg6d_s_prfh_cryc_idle_cnt:4; // prfh idle count (x 16T) for prfh_cryc ++ ushort reg6d_s_prfh_refy_idle_cnt:4; // prfh idle count (x 16T) for prfh_refy ++ }; ++ ushort reg6d; ++ }; ++ union { ++ struct { ++ ushort reg6e_s_mbr_qstep_min:7; // qstep min (note: max value of qstep_min is 128 because condition is qstep <= qstep_min) ++ }; ++ ushort reg6e; ++ }; ++ union { ++ struct { ++ ushort reg6f_s_mbr_qstep_max:13; // qstep max ++ }; ++ ushort reg6f; ++ }; ++ union { ++ struct { ++ ushort reg70_g_debug_mode:7; // debug mode ++ ushort reg70_g_debug_trig_cycle:9; // wait (8 * reg70_g_debug_trig_cycle) cycles ++ }; ++ ushort reg70; ++ }; ++ union { ++ struct { ++ ushort reg71_g_debug_trig_mbx:13; // debug trigger mbx ++ }; ++ ushort reg71; ++ }; ++ union { ++ struct { ++ ushort reg72_g_debug_trig_mby:13; // debug trigger mby ++ }; ++ ushort reg72; ++ }; ++ union { ++ struct { ++ ushort reg73_g_debug_trig:1; // reg trigger (write one clear) ++ ushort reg73_g_debug_trig_mode:2; // debug trigger mode; 0/1/2/3: reg_trigger/3rd stage (mbx, mby)/frame start ++ ushort reg73_g_debug_en:1; // debug enable ++ ushort reg73_g_crc_mode:4; // 'h0: Disable,¡¥hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf ++ ushort reg73_g_debug_tcycle_chk_en:1; // enable total cycle check ++ ushort reg73_g_debug_tcycle_chk_sel:1; // select total cycle and report it on regmfe_g_crc_result[15:0] ++ ushort reg73_g_sw_buffer_mode:1; // 0/1: hw/sw buffer mode ++ ushort reg73_g_sw_row_done:1; // sw row done (1T clk_jpe) (write one clear) ++ ushort reg73_g_sw_vs:1; // sw vsync (1T clk_jpe) (write one clear) ++ ushort reg73_g_pat_gen_en:1; // enable pattern generation ++ ushort reg73_g_row_down_irq_en:1; // row done irq enable; 0: disable, 1: enable ++ ushort reg73_g_vs_irq_en:1; // vs irq enable; 0: disable, 1: enable ++ }; ++ ushort reg73; ++ }; ++ union { ++ struct { ++ ushort reg74_g_debug_state0:16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, ++ // txip2mve_en, txip2mcobuf_en, txip2mbldr_en, ecdb2mdc_en, ++ // ecdb2rlc_en, ecdb2vlc_en, 5'd0}" ++ }; ++ ushort reg74; ++ }; ++ union { ++ struct { ++ ushort reg75_g_debug_state1; // "debug state for ME submodule {3'd0, load_w4_ok, load_w3_ok, load_w2_ok, load_w1_ok, load_w0_ok, 2'd0, ++ // busy_ime, busy_fme, busy_mesr, busy_iacost, end_this_mb, init_this_mb" ++ }; ++ ushort reg75; ++ }; ++ union { ++ struct { ++ ushort reg76_g_crc_result0:16; // CRC64[15..0] ++ }; ++ ushort reg76; ++ }; ++ union { ++ struct { ++ ushort reg77_g_crc_result1:16; // CRC64[31..16] ++ }; ++ ushort reg77; ++ }; ++ union { ++ struct { ++ ushort reg78_g_crc_result2:16; // CRC64[47..32] ++ }; ++ ushort reg78; ++ }; ++ union { ++ struct { ++ ushort reg79_g_crc_result3:16; // CRC64[63..48] ++ }; ++ ushort reg79; ++ }; ++ union { ++ struct { ++ ushort reg7a_g_bist_fail0; ++ }; ++ ushort reg7a; ++ }; ++ union { ++ struct { ++ ushort reg7b_g_bist_fail1; ++ }; ++ ushort reg7b; ++ }; ++ union { ++ struct { ++ ushort reg7c_g_bist_fail2; ++ }; ++ ushort reg7c; ++ }; ++ union { ++ struct { ++ ushort reg7d_s_txip_eco0:1; // 0: original, 1: fix mbldr_cry_done, mbldr_crc_done bug ++ ushort reg7d_s_txip_eco1:1; // reserved registers ++ ushort reg7d_eco_mreq_stallgo:1; // reg7d_eco_mreq_stallgo ++ ushort reg7d_eco_marb_stallgo:1; // reg7d_eco_marb_stallgo ++ ushort reg7d_reserved1:1; ++ ushort reg7d_eco_bsp_stuffing:1; ++ ushort reg7d_eco_bsp_rdy_fix:1; ++ ushort reg7d_eco_bsp_multi_slice_fix:1; ++ ushort reg7d_reserved2:6; ++ ushort reg7d_g_secure_obufadr:1; ++ ushort reg7d_g_secure_miu_sel:1; ++ }; ++ ushort reg7d; ++ }; ++ union { ++ struct { ++ ushort reg80_s_pp_en:1; ++ ushort reg80_s_pp_mw_burst_thd:5; ++ ushort reg80_s_pp_mw_timeout:3; ++ ushort reg80_s_pp_mw_timeout_ref:1; ++ ushort reg80_s_pp_burst_split:2; ++ ushort reg80_s_pp_32b_ad_nswap:1; ++ }; ++ ushort reg80; ++ }; ++ union { ++ struct { ++ ushort reg8b_g_mb_pitch:12; ++ ushort reg8b_g_mb_pitch_en:1; ++ }; ++ ushort reg8b; ++ }; ++ union { ++ struct { ++ ushort reg90_g_capture_width_y:12; ++ }; ++ ushort reg90; ++ }; ++ union { ++ struct { ++ ushort reg91_g_capture_width_c:12; ++ }; ++ ushort reg91; ++ }; ++ union { ++ struct { ++ ushort regd2_g_jpd_hsk_en:1; ++ ushort regd2_s_packed422_en:1; ++ ushort regd2_s_packed422_endian:1; ++ ushort regd2_s_packed422_yc_swap:1; ++ ushort regd2_s_packed422_uv_swap:1; ++ ushort regd2_s_packed422_delta:8; ++ ushort regd2_g_jpd_hsk_shot:1; ++ ushort regd2_g_jpd_hsk_mfe:1; ++ ushort regd2_g_jpd_frame_done_mask:1; ++ }; ++ ushort regd2; ++ }; ++ union { ++ struct { ++ ushort regd6_g_yuvldr_en:1; ++ ushort regd6_g_hevd_tile:1; ++ ushort regd6_g_hevd_tile32:1; ++ ushort regd6_g_yuv420_semi:1; ++ ushort regd6_g_yuv420_semi_uv_swap:1; ++ }; ++ ushort regd6; ++ }; ++ union { ++ struct { ++ ushort regdb_s_sambc_td1k_rbw_max:8; ++ ushort regdb_s_sambc_td1k_rbw_min:8; ++ }; ++ ushort regdb; ++ }; ++ union { ++ struct { ++ ushort regdc_s_sambc_td8k_rbw_max:8; ++ ushort regdc_s_sambc_td8k_rbw_min:8; ++ }; ++ ushort regdc; ++ }; ++ union { ++ struct { ++ ushort regdd_s_sambc_td64k_rbw_max:8; ++ ushort regdd_s_sambc_td64k_rbw_min:8; ++ }; ++ ushort regdd; ++ }; ++ union { ++ struct { ++ ushort regde_s_sambc_td1k_wbw_max:8; ++ ushort regde_s_sambc_td1k_wbw_min:8; ++ }; ++ ushort regde; ++ }; ++ union { ++ struct { ++ ushort regdf_s_sambc_td8k_wbw_max:8; ++ ushort regdf_s_sambc_td8k_wbw_min:8; ++ }; ++ ushort regdf; ++ }; ++ union { ++ struct { ++ ushort rege0_s_sambc_td64k_wbw_max:8; ++ ushort rege0_s_sambc_td64k_wbw_min:8; ++ }; ++ ushort rege0; ++ }; ++ union { ++ struct { ++ ushort rege1_s_sambc_mask_en:4; ++ ushort rege1_s_sambc_slowdown_mode:4; ++ ushort rege1_s_sambc_bypass:8; ++ }; ++ ushort rege1; ++ }; ++ union { ++ struct { ++ ushort regf2_g_roi_en:1; ++ ushort regf2_g_roi_range_sw_limit:1; ++ }; ++ ushort regf2; ++ }; ++ union { ++ struct { ++ ushort regf3_s_plnrldr_format:1; ++ #define MFE_REG_PLNRLDR_420 0 ++ #define MFE_REG_PLNRLDR_422 1 ++ ushort regf3_s_plnrldr_rlast_thd:4; ++ ushort regf3_s_plnrldr_mrpriority_sw:2; ++ ushort regf3_s_plnrldr_mrpriority_thd:7; ++ ushort regf3_s_plnrldr_mrpriority_type:1; ++ ushort regf3_s_plnrldr_c_swap:1; ++ #define MFE_REG_PLNRLDR_UV 0 ++ #define MFE_REG_PLNRLDR_VU 1 ++ }; ++ ushort regf3; ++ }; ++ union { ++ struct { ++ ushort regf4_s_plnrldr_en:1; ++ }; ++ ushort regf4; ++ }; ++ union { ++ struct { ++ ushort regfb_g_roi_qmap_adr_lo:16; ++ }; ++ ushort regfb; ++ }; ++ union { ++ struct { ++ ushort regfc_g_roi_qmap_adr_hi:8; ++ }; ++ ushort regfc; ++ }; ++ union { ++ struct { ++ ushort regfd_reserved0:6; ++ ushort regfd_eco:1; ++ }; ++ ushort regfd; ++ }; ++} mfe_regs; ++ ++#endif//_MFE_REGS_H_ +diff --git a/drivers/mstar/mfev5/mfe5/mfe_util.h b/drivers/mstar/mfev5/mfe5/mfe_util.h +new file mode 100644 +index 00000000..4bda5a58 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe5/mfe_util.h +@@ -0,0 +1,64 @@ ++ ++#ifndef _MFE_UTIL_H_ ++#define _MFE_UTIL_H_ ++ ++#ifndef _MAX ++#define _MAX(a,b) ((a)>(b)?(a):(b)) ++#endif ++#ifndef _MIN ++#define _MIN(a,b) ((a)<(b)?(a):(b)) ++#endif ++ ++typedef struct iir_t { ++#define KAPA_ONE 1024 ++ int i_kapa; ++ int i_data; ++} iir_t; ++inline static int iir_init(iir_t* iir, int data, int kapa) ++{ ++ iir->i_kapa = kapa; ++ iir->i_data = data; ++ return iir->i_data; ++} ++inline static int iir_push(iir_t* iir, int data) ++{ ++ int64 calc = (int64)data * iir->i_kapa; ++ data = !iir->i_data ? data:iir->i_data; ++ calc += (int64)data * (KAPA_ONE-iir->i_kapa); ++ iir->i_data = (int)div_s64(calc,KAPA_ONE); ++ return iir->i_data; ++} ++inline static int iir_data(iir_t* iir) ++{ ++ return iir->i_data; ++} ++ ++typedef struct acc_t { ++#define ACC_SIZE (1<<8) ++#define ACC_MASK (ACC_SIZE-1) ++ int i_curr; ++ int i_data[ACC_SIZE]; ++} acc_t; ++inline static int acc_init(acc_t* acc, int data) ++{ ++ int i = ACC_SIZE; ++ while (i-- > 0) ++ acc->i_data[i] = -i*data; ++ acc->i_curr = 0; ++ return data; ++} ++inline static int acc_push(acc_t* acc, int data) ++{ ++ int v = data + acc->i_data[ACC_MASK&(acc->i_curr)]; ++ acc->i_curr--; ++ acc->i_data[ACC_MASK&(acc->i_curr)] = v; ++ return data; ++} ++inline static int acc_calc(acc_t* acc, int size) ++{ ++ int lead = acc->i_data[ACC_MASK&(acc->i_curr)]; ++ int tail = acc->i_data[ACC_MASK&(acc->i_curr+size)]; ++ return (lead-tail); ++} ++ ++#endif//_MFE_UTIL_H_ +diff --git a/drivers/mstar/mfev5/mfe6/Makefile b/drivers/mstar/mfev5/mfe6/Makefile +new file mode 100644 +index 00000000..99469c2e +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/Makefile +@@ -0,0 +1,22 @@ ++# ++# Makefile for MStar MFE driver on SOC INFINITY. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/mhve ++EXTRA_CFLAGS += -Idrivers/mstar/mfev5 ++EXTRA_CFLAGS += -Idrivers/mstar/mfev5/mfe6 ++ ++# make LINUX_KERNEL version of 'ops/ios'. ++EXTRA_CFLAGS += -DLINUX_KERNEL ++ ++# files ++obj-$(CONFIG_MS_MFEV5) += mdrv_mfe6.o ++ ++mdrv_mfe6-y := \ ++ mfe6_ops.o \ ++ mfe6_ios.o \ ++ h264_enc.o \ ++ mfe6_rqc.o \ ++ msb2_rqc.o \ +diff --git a/drivers/mstar/mfev5/mfe6/h264_enc.c b/drivers/mstar/mfev5/mfe6/h264_enc.c +new file mode 100644 +index 00000000..ffc13732 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/h264_enc.c +@@ -0,0 +1,504 @@ ++#include ++#include ++ ++static void write_ebsp(bs_t* bs, uchar byte) ++{ ++ if (bs->ebsp_zeros == 2 && byte < 4) ++ { ++ *bs->curr++ = 0x03; ++ bs->ebsp_zeros = 0; ++ bs->bits_pos += 8; ++ } ++ if (byte == 0) ++ bs->ebsp_zeros++; ++ else ++ bs->ebsp_zeros = 0; ++ *bs->curr++ = byte; ++} ++ ++int avc_reset(bs_t* bs, uchar* buff, int len) ++{ ++ bs->bits_pos = 0; ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ bs->curr = bs->buffer = buff; ++ bs->length = len; ++ return 0; ++} ++ ++int avc_flush(bs_t* bs) ++{ ++ while (bs->left_count < 16) ++ { ++ write_ebsp(bs, (uchar)(bs->code_bits>>8)); ++ bs->left_count += 8; ++ bs->code_bits <<= 8; ++ } ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ return bs->bits_pos; ++} ++ ++int avc_count(bs_t* bs) ++{ ++ return bs->bits_pos; ++} ++ ++static int bs_write(bs_t* bs, int len, uint bit) ++{ ++ if (bs->left_count > len) ++ { ++ bs->left_count -= len; ++ bs->code_bits += bit << bs->left_count; ++ } ++ else ++ { ++ int left = (16 - len + bs->left_count); ++ uint pattern = (bs->code_bits << 16) + (bit << left); ++ bs->left_count = left; ++ bs->code_bits = pattern & 0xFFFF; ++ write_ebsp(bs, (uchar)(pattern>>24)); ++ write_ebsp(bs, (uchar)(pattern>>16)); ++ } ++ bs->bits_pos += len; ++ return len; ++} ++ ++static int bs_align(bs_t* bs, int bit) ++{ ++ int size = bs->left_count&0x7; ++ uint code = bit?(1< 0) ++ bs_write(bs, size, code); ++ return size; ++} ++ ++static const uchar ue_code_lengths[256] = { ++ 1, 1, 3, 3, 5, 5, 5, 5, 7, 7, 7, 7, 7, 7, 7, 7, ++ 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, ++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, ++11,11,11,11,11,11,11,11,11,11,11,11,11,11,11,11, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++13,13,13,13,13,13,13,13,13,13,13,13,13,13,13,13, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15, ++}; ++ ++static int bs_write_ue(bs_t* bs, uint val) ++{ ++ return bs_write(bs, (int)ue_code_lengths[val+1], val+1); ++} ++ ++static int bs_write_se(bs_t* bs, int val) ++{ ++ int size = 0; ++ int tmp = 1 - 2*val; ++ if (tmp < 0) tmp = 2*val; ++ val = tmp; ++ if (tmp >= 256) ++ { ++ size = 16; ++ tmp >>= 8; ++ } ++ size += ue_code_lengths[tmp]; ++ return bs_write(bs, size, (uint)val); ++} ++ ++static int bs_write_u1(bs_t* bs, uint val) ++{ ++ return bs_write(bs, 1, val!=0); ++} ++ ++static int bs_write_32(bs_t* bs, uint val) ++{ ++ int len; ++ len = bs_write(bs, 16, (val>>16)&0xFFFF); ++ len += bs_write(bs, 16, val&0xFFFF); ++ return len; ++} ++ ++static int bs_trail(bs_t* bs) ++{ ++ int len; ++ ++ bs->left_count--; ++ bs->code_bits += 1 << bs->left_count; ++ ++ if (!bs->left_count) ++ { ++ write_ebsp(bs, (uchar)(bs->code_bits>>8)); ++ write_ebsp(bs, (uchar)(bs->code_bits)); ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ } ++ bs->bits_pos += 8; ++ bs->bits_pos &= ~0x7; ++ ++ len = 1 + (bs->left_count&0x7); ++ ++ bs->left_count &= ~7; ++ ++ return len; ++} ++ ++int avc_write_nal(bs_t* bs, uchar nal) ++{ ++ *bs->curr++ = 0; ++ *bs->curr++ = 0; ++ *bs->curr++ = 0; ++ *bs->curr++ = 1; ++ *bs->curr++ = nal; ++ bs->bits_pos += 8*5; ++ bs->left_count = 16; ++ bs->code_bits = 0; ++ ++ return 8*5; ++} ++ ++static int vui_write_param(bs_t* bs, vui_t* vui); ++ ++int avc_write_sps(bs_t* bs, sps_t* sps) ++{ ++ int bit_pos = avc_count(bs); ++ /* profile_idc */ ++ bs_write(bs, 8, (uint)sps->i_profile_idc); ++ /* constraint_set0_flag */ ++ bs_write_u1(bs, sps->b_constraint_set0); ++ /* constraint_set1_flag */ ++ bs_write_u1(bs, sps->b_constraint_set1); ++ /* constraint_set2_flag */ ++ bs_write_u1(bs, sps->b_constraint_set2); ++ /* constraint_set3_flag */ ++ bs_write_u1(bs, sps->b_constraint_set3); ++ /* constraint_set4_flag u(1) */ ++ /* constraint_set5_flag u(1) */ ++ /*reserved_zero_2bits (equal to 0) */ ++ bs_write(bs, 4, 0); ++ /* level_idc */ ++ bs_write(bs, 8, (uint)sps->i_level_idc); ++ /* seq_parameter_set_id */ ++ bs_write_ue(bs, sps->i_sps_id); ++#if 0 /* not support high profile */ ++ /* chroma_format_idc */ ++ if (sps->i_profile_idc > PROFILE_HIGH) ++ { ++ chroma_format_idc ++ .... ++ } ++#endif ++ /* log2_max_frame_num_minus4 */ ++ bs_write_ue(bs, sps->i_log2_max_frame_num - 4); ++ /* pic_order_cnt_type */ ++ bs_write_ue(bs, sps->i_poc_type); ++ if (sps->i_poc_type == 0) ++ { ++ /* log2_max_pic_order_cnt_lsb_minus4 */ ++ bs_write_ue(bs, sps->i_log2_max_poc_lsb - 4); ++ } ++ /* not support poc_type == 1 // B-slice used ++ else if (sps->i_poc_type == 1) ++ { ++ .... ++ } ++ */ ++ /* max_num_ref_frames */ ++ bs_write_ue(bs, sps->i_num_ref_frames); ++ /* gaps_in_frame_num_value_allowed_flag */ ++ bs_write_u1(bs, sps->b_gaps_in_frame_num_value_allow); ++ /* pic_width_in_mbs_minus1 */ ++ bs_write_ue(bs, sps->i_mb_w - 1); ++ /* pic_height_in_map_units_minus1 */ ++ bs_write_ue(bs, sps->i_mb_h - 1); ++ /* frame_mbs_only_flag */ ++ bs_write_u1(bs, 1/*b_frame_mbs_only*/); ++ /* only support frame_mbs */ ++ /* direct_8x8_inference_flag */ ++ bs_write_u1(bs, sps->b_direct8x8_inference); ++ /* frame_cropping_flag */ ++ bs_write_u1(bs, sps->b_crop); ++ if (sps->b_crop) ++ { ++ /* frame_crop_left_offset */ ++ bs_write_ue(bs, sps->crop.i_left); ++ /* frame_crop_right_offset */ ++ bs_write_ue(bs, sps->crop.i_right); ++ /* frame_crop_top_offset */ ++ bs_write_ue(bs, sps->crop.i_top); ++ /* frame_crop_bottom_offset */ ++ bs_write_ue(bs, sps->crop.i_bottom); ++ } ++ /* vui_parameters_present_flag */ ++ bs_write_u1(bs, sps->b_vui_param_pres); ++ if (sps->b_vui_param_pres) ++ vui_write_param(bs, &sps->vui); ++ bs_trail(bs); ++ ++ return bs->bits_pos - bit_pos; ++} ++ ++static int vui_write_param(bs_t* bs, vui_t* vui) ++{ ++ int bit_pos = avc_count(bs); ++ ++ /* aspect_ratio_info_present_flag */ ++ bs_write_u1(bs, 0); ++ /* overscan_info_present_flag */ ++ bs_write_u1(bs, 0); ++ /* video_signal_type_present_flag */ ++ bs_write_u1(bs, vui->b_video_signal_pres); ++ if (vui->b_video_signal_pres) ++ { ++ /* video_format */ ++ bs_write(bs, 3, vui->i_video_format); ++ /* video_full_range_flag */ ++ bs_write_u1(bs, vui->b_video_full_range); ++ /* colour_description_present_flag */ ++ bs_write_u1(bs, vui->b_colour_desc_pres); ++ if (vui->b_colour_desc_pres) ++ { ++ /* colour_primaries */ ++ bs_write(bs, 8, vui->i_colour_primaries); ++ /* transfer_characteristics */ ++ bs_write(bs, 8, vui->i_transf_character); ++ /* matrix_coefficients */ ++ bs_write(bs, 8, vui->i_matrix_coeffs); ++ } ++ } ++ /* chroma_loc_info_present_flag */ ++ bs_write_u1(bs, 0); ++ if (vui->b_timing_info_pres) ++ { ++ /* timing_info_present_flag */ ++ bs_write_u1(bs, 1); ++ /* num_units_in_tick */ ++ bs_write_32(bs, vui->i_num_units_in_tick); ++ /* time_scale */ ++ bs_write_32(bs, vui->i_time_scale); ++ /* fixed_frame_rate_flag */ ++ bs_write_u1(bs, vui->b_fixed_frame_rate); ++ } ++ else ++ { ++ /* timing_info_present_flag */ ++ bs_write_u1(bs, 0); ++ } ++ /* nal_hrd_parameters_present_flag */ ++ bs_write_u1(bs, 0); ++ /* vcl_hrd_parameters_present_flag */ ++ bs_write_u1(bs, 0); ++ /* pic_struct_present_flag */ ++ bs_write_u1(bs, 0); ++ /* bitstream_restriction_flag */ ++ bs_write_u1(bs, 0); ++ return bs->bits_pos - bit_pos; ++} ++ ++int avc_write_pps(bs_t* bs, pps_t* pps) ++{ ++ int bit_pos = avc_count(bs); ++ /* pic_parameter_set_id */ ++ bs_write_ue(bs, pps->i_pps_id); ++ /* seq_parameter_set_id */ ++ bs_write_ue(bs, pps->sps->i_sps_id); ++ /* entropy_coding_mode_flag */ ++ bs_write_u1(bs, pps->b_cabac); ++ /* bottom_field_pic_order_in_frame_present_flag */ ++ bs_write_u1(bs, 0/*b_bottom_field_pic_order*/); ++ /* num_slice_groups_minus1 */ ++ bs_write_ue(bs, 0/*i_num_slice_groups - 1*/); ++ /* num_ref_idx_l0_default_active_minus1 */ ++ bs_write_ue(bs, pps->i_num_ref_idx_l0_default_active - 1); ++ /* num_ref_idx_l1_default_active_minus1 */ ++ bs_write_ue(bs, pps->i_num_ref_idx_l1_default_active - 1); ++ /* not support weighted pred */ ++ /* weighted_pred_flag */ ++ bs_write_u1(bs, 0/*b_weighted_pred*/); ++ /* weighted_bipred_idc */ ++ bs_write(bs, 2, 0/*b_weighted_bipred*/); ++ /* pic_init_qp_minus26 */ ++ bs_write_se(bs, pps->i_pic_init_qp - 26); ++ /* pic_init_qs_minus26 */ ++ bs_write_se(bs, pps->i_pic_init_qs - 26); ++ /* chroma_qp_index_offset */ ++ bs_write_se(bs, pps->i_cqp_idx_offset); ++ /* deblocking_filter_control_present_flag */ ++ bs_write_u1(bs, pps->b_deblocking_filter_control); ++ /* constrained_intra_pred_flag */ ++ bs_write_u1(bs, pps->b_constrained_intra_pred); ++ /* redundant_pic_cnt_present_flag */ ++ bs_write_u1(bs, pps->b_redundant_pic_cnt); ++ /* not support transform8x8/q-matrix */ ++ bs_trail(bs); ++ ++ return bs->bits_pos - bit_pos; ++} ++ ++int avc_write_slice_header(bs_t* bs, slice_t* sh) ++{ ++ /* first_mb_in_slice */ ++ bs_write_ue(bs, sh->i_first_mb); ++ /* slice_type */ ++ bs_write_ue(bs, sh->i_type); ++ /* pic_parameter_set_id */ ++ bs_write_ue(bs, sh->pps->i_pps_id); ++ /* frame_num */ ++ bs_write(bs, sh->sps->i_log2_max_frame_num, (uint)sh->i_frm_num & ((1 << sh->sps->i_log2_max_frame_num) - 1)); ++ ++ /* idr_pic_id */ ++ if (sh->b_idr_pic) ++ bs_write_ue(bs, sh->i_idr_pid); ++ /* pic_order_cnt_type */ ++ if (sh->sps->i_poc_type == 0) ++ bs_write(bs, sh->sps->i_log2_max_poc_lsb, (uint)sh->i_poc & ((1 << sh->sps->i_log2_max_poc_lsb) - 1)); ++ /* redundant_pic_cnt */ ++ if (sh->pps->b_redundant_pic_cnt) ++ bs_write_ue(bs, sh->i_redundant_pic_cnt); ++ /* direct_spatial_mv_pred_flag */ ++ if (sh->i_type == SLICE_B) ++ bs_write_u1(bs, sh->b_direct_spatial_mv_pred); ++ if (sh->i_type == SLICE_P || sh->i_type == SLICE_B) ++ { ++ /* num_ref_idx_active_override_flag */ ++ bs_write_u1(bs, sh->b_num_ref_idx_override); ++ if (sh->b_num_ref_idx_override) ++ { ++ /* num_ref_idx_l0_active_minus1 */ ++ bs_write_ue(bs, sh->i_num_ref_idx_l0_active - 1); ++ /* num_ref_idx_l1_active_minus1 */ ++ if (sh->i_type == SLICE_B) ++ bs_write_ue(bs, sh->i_num_ref_idx_l1_active - 1); ++ } ++ } ++ /* ref_pic_list_modification() */ ++ if (sh->i_type != SLICE_I) ++ { ++ /* LTR is not enable */ ++ if (!sh->b_long_term_reference) ++ { ++ /* ref_pic_list_modification_flag_l0 */ ++ bs_write_u1(bs, 0); ++ } ++ else ++ { ++ int i; ++ /* ref_pic_list_modification_flag_l0 */ ++ bs_write_u1(bs, sh->b_ref_pic_list_modification_flag_l0); ++ /* fill ref pic list if LTR P-frame */ ++ if (sh->b_ref_pic_list_modification_flag_l0) ++ { ++ for (i = 0; i < MAX_MULTI_REF_FRAME_PLUS1; i++) ++ { ++ /* modification_of_pic_nums_idc */ ++ bs_write_ue(bs, sh->rpl0_t[i].modification_of_pic_nums_idc); ++ if (sh->rpl0_t[i].modification_of_pic_nums_idc == 0 || ++ sh->rpl0_t[i].modification_of_pic_nums_idc == 1) ++ { ++ /* abs_diff_pic_num_minus1 */ ++ bs_write_ue(bs, sh->rpl0_t[i].abs_diff_pic_num_minus1); ++ } ++ else if (sh->rpl0_t[i].modification_of_pic_nums_idc == 2) ++ { ++ /* long_term_pic_num */ ++ bs_write_ue(bs, sh->rpl0_t[i].long_term_pic_num); ++ } ++ else if (sh->rpl0_t[i].modification_of_pic_nums_idc == 4 || ++ sh->rpl0_t[i].modification_of_pic_nums_idc == 5) ++ { ++ /* abs_diff_view_idx_minus1 */ ++ bs_write_ue(bs, sh->rpl0_t[i].abs_diff_view_idx_minus1); ++ } ++ else if (sh->rpl0_t[i].modification_of_pic_nums_idc == 3) ++ { ++ break; ++ } ++ } ++ } ++ } ++ } ++ /* ref_pic_list_modification_flag_l1 */ ++ if (sh->i_type == SLICE_B) ++ bs_write_u1(bs, 0); ++ /* not support weighted pred */ ++ /* dec_ref_pic_marking() */ ++ if (sh->i_ref_idc) ++ { ++ /* I-frame */ ++ if (sh->b_idr_pic) ++ { ++ /* no_output_prior_pics_flag */ ++ bs_write_u1(bs, 0); ++ /* long_term_reference_flag */ ++ if (!sh->b_long_term_reference) ++ bs_write_u1(bs, 0); ++ else ++ bs_write_u1(bs, 1); ++ } ++ else ++ { ++ int i; ++ /* adaptive_ref_pic_marking_mode_flag */ ++ if(!sh->b_adaptive_ref_pic_marking_mode) ++ bs_write_u1(bs, 0); ++ else ++ { ++ bs_write_u1(bs, 1); ++ for (i = 0; i < MAX_MULTI_REF_FRAME_PLUS1; i++) ++ { ++ /* memory_management_control_operation */ ++ bs_write_ue(bs, sh->mmc_t[i].memory_management_control); ++ if(sh->mmc_t[i].memory_management_control == 1 || ++ sh->mmc_t[i].memory_management_control == 3) ++ { ++ /* difference_of_pic_nums_minus1 */ ++ bs_write_ue(bs, sh->mmc_t[i].difference_of_pic_nums_minus1); ++ } ++ if(sh->mmc_t[i].memory_management_control == 2) ++ { ++ /* ong_term_pic_num */ ++ bs_write_ue(bs, sh->mmc_t[i].long_term_pic_num); ++ } ++ if(sh->mmc_t[i].memory_management_control == 3 || ++ sh->mmc_t[i].memory_management_control == 6) ++ { ++ /* long_term_frame_idx */ ++ bs_write_ue(bs, sh->mmc_t[i].long_term_frame_idx); ++ } ++ if(sh->mmc_t[i].memory_management_control == 4) ++ { ++ /* max_long_term_frame_idx_plus1 */ ++ bs_write_ue(bs, sh->mmc_t[i].max_long_term_frame_idx_plus1); ++ } ++ } ++ } ++ } ++ } ++ /* cabac_init_idc */ ++ if (sh->pps->b_cabac && sh->i_type != SLICE_I) ++ bs_write_ue(bs, sh->i_cabac_init_idc); ++ /* slice_qp_delta */ ++ bs_write_se(bs, sh->i_qp - sh->pps->i_pic_init_qp); ++ if (sh->pps->b_deblocking_filter_control) ++ { ++ /* disable_deblocking_filter_idc */ ++ bs_write_ue(bs, sh->i_disable_deblocking_filter_idc); ++ if (sh->i_disable_deblocking_filter_idc != 1) ++ { ++ /* slice_alpha_c0_offset_div2 */ ++ bs_write_se(bs, sh->i_alpha_c0_offset_div2); ++ /* slice_beta_offset_div2 */ ++ bs_write_se(bs, sh->i_beta_offset_div2); ++ } ++ } ++ if (sh->pps->b_cabac) ++ bs_align(bs, 1); ++ ++ return bs->bits_pos; ++} +diff --git a/drivers/mstar/mfev5/mfe6/h264_enc.h b/drivers/mstar/mfev5/mfe6/h264_enc.h +new file mode 100644 +index 00000000..45da40cc +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/h264_enc.h +@@ -0,0 +1,148 @@ ++ ++#ifndef _H264_ENC_H_ ++#define _H264_ENC_H_ ++ ++typedef struct bitstream ++{ ++ int bits_pos; ++ int length; // ++ int left_count; // left count of 16bit unit ++ uint code_bits; // encode bits ++ uchar* curr; ++ uchar* buffer; ++ int ebsp_zeros; ++} bs_t; ++ ++int avc_reset(bs_t*,uchar*, int); ++int avc_flush(bs_t*); ++int avc_count(bs_t*); ++ ++#define NAL_SLICE 1 ++#define NAL_IDR 5 ++#define NAL_SPS 7 ++#define NAL_PPS 8 ++#define NAL_FILLER 12 ++ ++typedef struct sps ++{ ++ int i_sps_id; ++ int i_profile_idc; ++ int i_level_idc; ++ int b_constraint_set0; ++ int b_constraint_set1; ++ int b_constraint_set2; ++ int b_constraint_set3; ++ int i_log2_max_frame_num; ++ int i_poc_type; ++ int i_log2_max_poc_lsb; ++ int i_num_ref_frames; ++ int b_gaps_in_frame_num_value_allow; ++ int i_mb_w; ++ int i_mb_h; ++ int b_direct8x8_inference; ++ int b_crop; ++ struct ++ { ++ int i_left, i_right; ++ int i_top, i_bottom; ++ } crop; ++ int b_vui_param_pres; ++ struct vui ++ { ++ int b_video_signal_pres; ++ int i_video_format; ++ int b_video_full_range; ++ int b_timing_info_pres; ++ uint i_num_units_in_tick; ++ uint i_time_scale; ++ int b_fixed_frame_rate; ++ int b_colour_desc_pres; ++ int i_colour_primaries; ++ int i_transf_character; ++ int i_matrix_coeffs; ++ } vui; ++} sps_t; ++ ++typedef struct vui vui_t; ++ ++typedef struct pps ++{ ++ sps_t* sps; ++ int i_pps_id; ++ int b_cabac; ++ /*only support slice_groups==1*/ ++ int i_num_ref_idx_l0_default_active; ++ int i_num_ref_idx_l1_default_active; ++ /*not support weighted pred*/ ++ int i_pic_init_qp; ++ int i_pic_init_qs; ++ int i_cqp_idx_offset; ++ int b_deblocking_filter_control; ++ int b_constrained_intra_pred; ++ int b_redundant_pic_cnt; ++} pps_t; ++ ++typedef struct ref_pic_list_t ++{ ++ int modification_of_pic_nums_idc; ++ union ++ { ++ int abs_diff_pic_num_minus1; ++ int long_term_pic_num; ++ int abs_diff_view_idx_minus1; ++ }; ++} ref_pic_list_t; ++ ++typedef struct mem_mng_ctl_t ++{ ++ int memory_management_control; ++ int difference_of_pic_nums_minus1; ++ int long_term_pic_num; ++ int long_term_frame_idx; ++ int max_long_term_frame_idx_plus1; ++} mem_mng_ctl_t; ++ ++typedef struct slice ++{ ++ int b_idr_pic; ++#define NAL_PRIO_DISPOSED 0 ++#define NAL_PRIO_LOW 1 ++#define NAL_PRIO_HIGH 2 ++#define NAL_PRIO_HIGHEST 3 ++ int i_ref_idc; ++ sps_t* sps; ++ pps_t* pps; ++#define SLICE_P 0 ++#define SLICE_B 1 ++#define SLICE_I 2 ++ int i_type; ++ int i_first_mb; ++ int i_frm_num; ++ int i_idr_pid; ++ int b_long_term_reference; ++ int i_poc; ++ int i_redundant_pic_cnt; ++ int b_direct_spatial_mv_pred; ++ int b_num_ref_idx_override; ++ int i_num_ref_idx_l0_active; ++#define MAX_MULTI_REF_FRAME_PLUS1 3 ++ int b_ref_pic_list_modification_flag_l0; ++ ref_pic_list_t rpl0_t[MAX_MULTI_REF_FRAME_PLUS1]; ++ int i_num_ref_idx_l1_active; ++ int b_ref_pic_list_modification_flag_l1; ++ ref_pic_list_t rpl1_t[MAX_MULTI_REF_FRAME_PLUS1]; // used in B-frame ++ int i_cabac_init_idc; ++ int i_qp; ++ int i_disable_deblocking_filter_idc; ++ int i_alpha_c0_offset_div2; ++ int i_beta_offset_div2; ++ int b_adaptive_ref_pic_marking_mode; ++ mem_mng_ctl_t mmc_t[MAX_MULTI_REF_FRAME_PLUS1]; ++} slice_t; ++ ++int avc_write_nal(bs_t*, uchar ); ++int avc_write_sps(bs_t*, sps_t*); ++int avc_write_pps(bs_t*, pps_t*); ++int avc_write_slice_header(bs_t*, slice_t*); ++ ++#endif/*_H264_ENC_H_*/ +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_def.h b/drivers/mstar/mfev5/mfe6/mfe6_def.h +new file mode 100644 +index 00000000..ffe4ab04 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_def.h +@@ -0,0 +1,57 @@ ++ ++#ifndef _MFE6_DEF_H_ ++#define _MFE6_DEF_H_ ++ ++typedef unsigned char uchar; ++typedef unsigned short ushort; ++typedef unsigned int uint; ++ ++typedef unsigned char uint8; ++typedef unsigned short uint16; ++typedef unsigned int uint32; ++typedef unsigned long long uint64; ++typedef signed char int8; ++typedef signed short int16; ++typedef signed int int32; ++typedef signed long long int64; ++ ++/* macros */ ++#define MIN(a,b) ((a)>(b)?(b):(a)) ++#define MAX(a,b) ((a)<(b)?(b):(a)) ++ ++#define MST_ASSERT(p) ++ ++/* mem operators (allc/free) */ ++#if defined(LINUX_KERNEL) ++#include ++#include ++#define MEM_ALLC(l) kzalloc(l,GFP_KERNEL) ++#define MEM_FREE(p) kfree(p) ++#elif defined(REALTIME_OS) ++#error "REALTIME_OS not implement yet" ++#else /* Non-OS */ ++#include ++#include ++#include ++#define EXPORT_SYMBOL(sym) ++#define MEM_ALLC(l) malloc(l) ++#define MEM_FREE(p) free(p) ++#endif ++#define MEM_SETV(p,v,l) memset(p,v,l) ++#define MEM_COPY(p,q,l) memcpy(p,q,l) ++ ++/* Debug related configuration */ ++#define DBG_PRINT_ENABLE 0 ++/* Debugging related macro */ ++#if DBG_PRINT_ENABLE ++#define MFE_DBG printk ++#else ++#define MFE_DBG(...) ++#endif ++ ++//#define MMFE_REGS_TRACE ++#define MMFE_RCTL_PATCH ++#define MMFE_IMI_DBF_ADDR 0x00000 /* From 0x00000 to 0x03FFF */ ++#define MMFE_IMI_LBW_ADDR 0x04000 /* From 0x04000 to 0x13FFF */ ++ ++#endif/*_MFE6_DEF_H_*/ +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_ios.c b/drivers/mstar/mfev5/mfe6/mfe6_ios.c +new file mode 100644 +index 00000000..8e9cca79 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_ios.c +@@ -0,0 +1,420 @@ ++ ++#include ++#include ++#include ++ ++static void _release(void* p) { if (p) kfree(p); } ++ ++static int _set_bank(mhve_ios*, mhve_reg*); ++static int _enc_fire(mhve_ios*, mhve_job*); ++static int _enc_poll(mhve_ios*); ++static int _isr_func(mhve_ios*, int); ++static int _irq_mask(mhve_ios*, int); ++static int _busywait(int count) ++{ ++ volatile int i=count; ++ while (--i>0) ; ++ return 0; ++} ++ ++mhve_ios* mmfeios_acquire( ++ char* tags) ++{ ++ mfe6_ios* asic = MEM_ALLC(sizeof(mfe6_ios)); ++ if (asic) ++ { ++ mhve_ios* mios = &asic->mios; ++ mios->release = _release; ++ mios->set_bank = _set_bank; ++ mios->enc_fire = _enc_fire; ++ mios->enc_poll = _enc_poll; ++ mios->isr_func = _isr_func; ++ mios->irq_mask = _irq_mask; ++ } ++ return (mhve_ios*)asic; ++} ++ ++static int _set_bank( ++ mhve_ios* ios, ++ mhve_reg* reg) ++{ ++ int err = 0; ++ mfe6_ios* asic = (mfe6_ios*)ios; ++ switch (reg->i_id) ++ { ++ case 0: ++ asic->p_base = reg->base; ++ break; ++ default: ++ err = -1; ++ break; ++ } ++ return err; ++} ++ ++#define REGW(base,idx) (*(((volatile unsigned short*)(base))+2*(idx))) ++ ++#if defined(MMFE_REGS_TRACE) ++#define PRINT(s,idx,v) printk(#s":bank%d[%02x]=%04x\n",(idx&0x80)?1:0,idx&0x7F,v) ++#define REGWR(base,idx,v,cmt) do{REGW(base,idx)=(v);PRINT(w,idx,v);}while(0) ++#define REGRD(base,idx,cmt) ({ushort v=REGW(base,idx);PRINT(r,idx,v); v;}) ++#else ++#define REGWR(base,idx,val,cmt) REGW(base,idx)=(val) ++#define REGRD(base,idx,cmt) REGW(base,idx) ++#endif ++ ++ ++static void ++clr_irq( ++ void* base, ++ uint bits) ++{ ++ REGWR(base,0x1d,bits,"clr irq"); ++} ++ ++static void ++msk_irq( ++ void* base, ++ uint bits) ++{ ++ REGWR(base,0x1c,bits,"msk irq"); ++} ++ ++static uint ++bit_irq( ++ void* base) ++{ ++ return 0xFF®RD(base,0x1e,"bit irq"); ++} ++ ++static void ++set_outbs_addr( ++ void* base, ++ mfe6_reg* regs, ++ uint32 addr, ++ int size) ++{ ++ uint32 value; ++ // Enable set-obuf ++ regs->reg3f_s_bspobuf_update_adr = 1; ++ REGWR(base,0x3f,regs->reg3f,"ref_mfe_s_bspobuf_update_adr"); ++ regs->reg3f_s_bspobuf_update_adr = 0; // write-one-clear ++ // address value ++ value = addr; ++ regs->reg3e = 0; ++ // For Safety ++ regs->reg3e_s_obuf_write_id_adr = 0; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ regs->reg3c_s_bspobuf_lo = (uint16)(value>> 3); ++ regs->reg3d_s_bspobuf_hi = (uint16)(value>>19); ++ regs->reg3d_s_obuf_id = 0; // start. addr ++ REGWR(base,0x3c,regs->reg3c,"bspobuf addr_lo"); ++ REGWR(base,0x3d,regs->reg3d,"bspobuf addr_hi"); ++ regs->reg3e_s_obuf_write_id_adr = 1; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++// value += size; ++ value += size-1; ++ // For Safety ++ regs->reg3e_s_obuf_write_id_adr = 0; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ regs->reg3c_s_bspobuf_lo = (uint16)(value>> 3); ++ regs->reg3d_s_bspobuf_hi = (uint16)(value>>19); ++ regs->reg3d_s_obuf_id = 1; // end. addr ++ REGWR(base,0x3c,regs->reg3c,"bspobuf addr_lo"); ++ REGWR(base,0x3d,regs->reg3d,"bspobuf addr_hi"); ++ regs->reg3e_s_obuf_write_id_adr = 1; ++ REGWR(base,0x3e,regs->reg3e,"write_id_addr"); ++ // address set ++ regs->reg3b_s_mvobuf_set_adr = 0; ++ regs->reg3b_s_mvobuf_fifo_th = 0; ++ regs->reg3b_s_bspobuf_fifo_th = 1; ++ regs->reg3b_s_bspobuf_set_adr = 1; ++ REGWR(base,0x3b,regs->reg3b,"set bsp obuf"); ++ regs->reg3b_s_bspobuf_set_adr = 0; // HW is write-one-clear ++} ++ ++static void ++put_coded_bits( ++ void* base, ++ mfe6_reg* regs, ++ uchar* code, ++ int size) ++{ ++ int round = (size+15)>>4; ++ ushort word = 0; ++ ++ regs->reg46 = regs->reg47 = regs->reg48 = 0; ++ ++ if (size == 0) ++ { ++ regs->reg47_s_fdc_bs_count = 0; ++ REGWR(base,0x47,regs->reg47,"fdc round count"); ++ regs->reg46_s_fdc_bs = 0; ++ regs->reg47_s_fdc_bs_len = 0; ++ regs->reg48_s_fdc_bs_vld = 1; ++ REGWR(base,0x46,regs->reg46,"fdc bs "); ++ REGWR(base,0x47,regs->reg47,"fdc len"); ++ REGWR(base,0x48,regs->reg48,"fdc vld"); ++ regs->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ return; ++ } ++ // Fill the total round regs ++ regs->reg47_s_fdc_bs_count = round - 1; // Count from 0 ++ REGWR(base,0x47,regs->reg47,"fdc round count"); ++ ++ while (size > 16) ++ { ++ word = (code[0]<<8) | code[1]; ++ code += 2; ++ size -= 16; ++ ++ regs->reg46_s_fdc_bs = word; ++ regs->reg47_s_fdc_bs_len = 15; ++ regs->reg48_s_fdc_bs_vld = 1; ++ REGWR(base,0x46,regs->reg46,"fdc bs "); ++ REGWR(base,0x47,regs->reg47,"fdc len"); ++ REGWR(base,0x48,regs->reg48,"fdc vld"); ++ regs->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ } ++ ++ if (size > 0) ++ { ++ word = code[0]<<8; ++ if (size > 8) ++ word += code[1]; ++ regs->reg46_s_fdc_bs = word; ++ regs->reg47_s_fdc_bs_len = size; ++ regs->reg48_s_fdc_bs_vld = 1; ++ REGWR(base,0x46,regs->reg46,"fdc bs "); ++ REGWR(base,0x47,regs->reg47,"fdc len"); ++ REGWR(base,0x48,regs->reg48,"fdc vld"); ++ regs->reg48_s_fdc_bs_vld = 0; // write-one-clear ++ } ++} ++ ++static int _enc_fire( ++ mhve_ios* ios, ++ mhve_job* job) ++{ ++ mfe6_ios* asic = (mfe6_ios*)ios; ++ mfe6_reg* regs = (mfe6_reg*)job; ++ void* base = asic->p_base; ++ asic->p_regs = regs; ++ /* flush regs to mfe-hw */ ++ msk_irq(base, 0x00); ++ // switch to sw mode ++ regs->reg03_g_tbc_mode = 0; ++ REGWR(base,0x03,regs->reg03,"tbc_mode=0"); ++ // switch to hw mode ++ regs->reg03_g_tbc_mode = 1; ++ REGWR(base,0x03,regs->reg03,"tbc_mode=1"); ++ // sw reset ++ regs->reg00_g_soft_rstz = 0; ++ REGWR(base,0x00,regs->reg00,"SW reset 0"); ++ _busywait(800); ++ regs->reg00_g_soft_rstz = 1; ++ REGWR(base,0x00,regs->reg00,"SW reset 1"); ++ REGWR(base,0x80,regs->reg80,"pp mode"); ++ REGWR(base,0x01,regs->reg01,"pic width"); ++ REGWR(base,0x02,regs->reg02,"pic height"); ++ REGWR(base,0x90,regs->reg90,"capture width y"); ++ REGWR(base,0x91,regs->reg91,"capture width c"); ++ REGWR(base,0xf2,regs->regf2,"roi settings"); ++ REGWR(base,0xf3,regs->regf3,"plnrldr setting"); ++ REGWR(base,0xf4,regs->regf4,"plnrldr enable"); ++ REGWR(base,0xfb,regs->regfb,"roi qmap addr lo"); ++ REGWR(base,0xfc,regs->regfc,"roi qmap addr hi"); ++ REGWR(base,0xfd,regs->regfd,"eco"); ++ REGWR(base,0x03,regs->reg03,"value"); ++ REGWR(base,0x04,regs->reg04,"er_bs mode threshold"); ++ REGWR(base,0x05,regs->reg05,"inter prediction perference"); ++ /* mb-pitch / packed422 / yuv-loader */ ++ REGWR(base,0x8b,regs->reg8b,"mb pitch"); ++ REGWR(base,0xd2,regs->regd2,"packed422 mode"); ++ REGWR(base,0xd6,regs->regd6,"yuv loader"); ++ /* sambc */ ++ REGWR(base,0xdb,regs->regdb,"sambc"); ++ REGWR(base,0xdc,regs->regdc,"sambc"); ++ REGWR(base,0xdd,regs->regdd,"sambc"); ++ REGWR(base,0xde,regs->regde,"sambc"); ++ REGWR(base,0xdf,regs->regdf,"sambc"); ++ REGWR(base,0xe0,regs->rege0,"sambc"); ++ REGWR(base,0xe1,regs->rege1,"sambc"); ++ /* set pict-buffer address */ ++ REGWR(base,0x06,regs->reg06,"curr luma base addr_lo"); ++ REGWR(base,0x07,regs->reg07,"curr luma base addr_hi"); ++ REGWR(base,0x08,regs->reg08,"curr cbcr base addr_lo"); ++ REGWR(base,0x09,regs->reg09,"curr cbcr base addr_hi"); ++ REGWR(base,0x0a,regs->reg0a,"ref0 luma base addr_lo"); ++ REGWR(base,0x0b,regs->reg0b,"ref0 luma base addr_hi"); ++ REGWR(base,0x0c,regs->reg0c,"ref1 luma base addr_lo"); ++ REGWR(base,0x0d,regs->reg0d,"ref1 luma base addr_hi"); ++ REGWR(base,0x0e,regs->reg0e,"ref0 cbcr base addr_lo"); ++ REGWR(base,0x0f,regs->reg0f,"ref0 cbcr base addr_hi"); ++ REGWR(base,0x10,regs->reg10,"ref1 cbcr base addr_lo"); ++ REGWR(base,0x11,regs->reg11,"ref1 cbcr base addr_hi"); ++ REGWR(base,0x12,regs->reg12,"recn luma base addr_lo"); ++ REGWR(base,0x13,regs->reg13,"recn luma base addr_hi"); ++ REGWR(base,0x14,regs->reg14,"recn cbcr base addr_lo"); ++ REGWR(base,0x15,regs->reg15,"recn cbcr base addr_hi"); ++ /*!set pict-buffer address */ ++ /* clock gating */ ++ REGWR(base,0x16,regs->reg16,"clock gating"); ++ /* me setting */ ++ REGWR(base,0x20,regs->reg20,"me partition setting"); ++ REGWR(base,0x21,regs->reg21,"value"); ++ REGWR(base,0x22,regs->reg22,"me search range max depth"); ++ REGWR(base,0x23,regs->reg23,"me mvx"); ++ REGWR(base,0x24,regs->reg24,"me mvy"); ++ REGWR(base,0x25,regs->reg25,"FME"); ++ // GN ++ REGWR(base,0x4c,regs->reg4c,"regmfe_s_gn_saddr_lo"); ++ REGWR(base,0x4d,regs->reg4d,"regmfe_s_gn_saddr_hi"); ++ // MBR ++ REGWR(base,0x26,regs->reg26,"MBR: mbbits"); ++ REGWR(base,0x27,regs->reg27,"MBR: frame qstep"); ++ REGWR(base,0x29,regs->reg29,"h264 qp offset"); ++ REGWR(base,0x2a,regs->reg2a,"QP min/max"); ++ REGWR(base,0x6e,regs->reg6e,"QStep min"); ++ REGWR(base,0x6f,regs->reg6f,"QStep max"); ++ // INTRA UPDATE ++ REGWR(base,0x2f,regs->reg2f,"value"); ++ REGWR(base,0x30,regs->reg30,"value"); ++ REGWR(base,0x31,regs->reg31,"value"); ++ REGWR(base,0x32,regs->reg32,"value"); ++ // MDC ++ REGWR(base,0x39,regs->reg39,"value"); ++ // DBF ++ REGWR(base,0x3a,regs->reg3a,"value"); ++ ++ regs->reg73_g_crc_mode = 0xC; ++ regs->reg73_g_debug_tcycle_chk_en = 0x1; ++ regs->reg73_g_debug_tcycle_chk_sel = 0x1; ++ regs->reg73_g_debug_en = 0; // TEST ++ REGWR(base,0x73,regs->reg73,"crc mode"); ++ REGWR(base,0x2c,regs->reg2c,"last zigzag"); ++ // IEAP ++ REGWR(base,0x2b,regs->reg2b,"ieap"); ++ // Cross-format wrong regs setting prevention ++ REGWR(base,0x18,regs->reg18,"jpe encode mode"); ++ REGWR(base,0x1b,regs->reg1b,"mpeg4 field dct"); ++ // regs->reg19 MUST be zero ++ REGWR(base,0x19,0,"0/1:MPEG4 enable/disable p skip mode"); ++ // Prefetch & Low bandwidth mode ++ REGWR(base,0x68,regs->reg68,"prefetch & low bandwidth mode"); ++ // Prefetch ++ REGWR(base,0x6d,regs->reg6d,"prefetch mb idle count"); ++ // Low bandwidth ++ REGWR(base,0x6b,regs->reg6b,"low bandwidth: IMI addr_lo"); ++ REGWR(base,0x6c,regs->reg6c,"low bandwidth: IMI addr_hi"); ++ // IMI DBF ++ REGWR(base,0x4e,regs->reg4e,"DBF: IMI addr_lo"); ++ REGWR(base,0x4f,regs->reg4f,"DBF: IMI addr_hi"); ++ // Zmv ++ REGWR(base,0x86,regs->reg86,"ZMv base addr lo"); ++ // penalties ++ REGWR(base,0x87,regs->reg87,"ZMv base addr hi & i4x penalty"); ++ REGWR(base,0x88,regs->reg88,"penalties i16 & inter"); ++ REGWR(base,0x89,regs->reg89,"penalties i16 planar"); ++ // Reset any StopAndGo or StopAndDrop setting. ++ regs->reg2d_s_txip_sng_mb = 0; ++ REGWR(base,0x2d,regs->reg2d,"reg2d_s_txip_sng_mb=0"); ++ // enable eco item ++ REGWR(base,0x7d,regs->reg7d,"reg7d_s_txip_eco0=1"); ++ // poc ++ REGWR(base,0xf7,regs->regf7,"sh->i_poc"); ++ REGWR(base,0xf8,regs->regf8,"poc_enable & poc_width"); ++ /* set output address */ ++ set_outbs_addr(base, regs, regs->outbs_addr, regs->outbs_size); ++ /* Enable HW */ ++ regs->reg00_g_frame_start_sw = 1; ++ REGWR(base,0x00,regs->reg00,"frame start"); ++ regs->reg00_g_frame_start_sw = 0; // HW is write-one-clear ++ /* write slice header */ ++ put_coded_bits(base, regs, regs->coded_data, regs->coded_bits); ++ return 0; ++} ++ ++static int _enc_poll( ++ mhve_ios* ios) ++{ ++ mfe6_ios* asic = (mfe6_ios*)ios; ++ mfe6_reg* regs = asic->p_regs; ++ void* base = asic->p_base; ++ int err = -1; ++ int bit = bit_irq(base); ++ if (bit&BIT_ENC_DONE) ++ err = 0; ++ else if (bit&BIT_BUF_FULL) ++ err = 1; ++ if (err != 0) ++ return err; ++ // feedback ++ regs->reg28 = REGRD(base,0x28,"sum-qstep:lo"); ++ regs->reg29 = REGRD(base,0x29,"sum-qstep:hi"); ++ regs->regf5 = REGRD(base,0xf5,"sum-qstep:lo"); ++ regs->regf6 = REGRD(base,0xf6,"sum-qstep:hi"); ++ regs->reg42 = REGRD(base,0x42,"bits size:lo"); ++ regs->reg43 = REGRD(base,0x43,"bits size:hi"); ++ regs->reg76 = REGRD(base,0x76,"cycle count0"); ++ regs->reg77 = REGRD(base,0x77,"cycle count1"); ++ regs->enc_cycles = ((uint)(regs->reg77&0xFF)<<16) + regs->reg76; ++ regs->enc_bitcnt = ((uint)(regs->reg43_s_bsp_bit_cnt_hi)<<16) + regs->reg42_s_bsp_bit_cnt_lo; ++ regs->enc_sumpqs = ((uint)(regs->regf6_s_mbr_last_frm_avg_qp_hi)<<16) + regs->regf5_s_mbr_last_frm_avg_qp_lo; ++ regs->mjob.i_tick = (int)(regs->enc_cycles); ++ regs->mjob.i_bits = (int)(regs->enc_bitcnt - regs->bits_delta); ++ clr_irq(base, 0xFF); ++ return err; ++} ++ ++static int _isr_func( ++ mhve_ios* ios, ++ int irq) ++{ ++ mfe6_ios* asic = (mfe6_ios*)ios; ++ mfe6_reg* regs = asic->p_regs; ++ void* base = asic->p_base; ++ uint bit = 0; ++ bit = bit_irq(base); ++ msk_irq(base, 0xFF); ++ //if (bit & BIT_BUF_FULL) ++ //{ ++ // printk(KERN_ERR"mfe-enc buffer full(%d/%u)\n", regs->outbs_size, (((uint)(regs->reg43_s_bsp_bit_cnt_hi)<<16) + regs->reg42_s_bsp_bit_cnt_lo)/8); ++ // clr_irq(base, 0xFF); ++ // msk_irq(base, 0x00); ++ // return 1; ++ //} ++ // TODO: handle enc_done/buf_full ++ regs->reg28 = REGRD(base,0x28,"avg-qp:lo"); ++ regs->reg29 = REGRD(base,0x29,"avg-qp:hi"); ++ regs->regf5 = REGRD(base,0xf5,"avg-qp:lo"); ++ regs->regf6 = REGRD(base,0xf6,"avg-qp:hi"); ++ regs->reg42 = REGRD(base,0x42,"bits size:lo"); ++ regs->reg43 = REGRD(base,0x43,"bits size:hi"); ++ regs->reg76 = REGRD(base,0x76,"cycle count0"); ++ regs->reg77 = REGRD(base,0x77,"cycle count1"); ++ regs->enc_cycles = ((uint)(regs->reg77&0xFF)<<16) + regs->reg76; ++ regs->enc_bitcnt = ((uint)(regs->reg43_s_bsp_bit_cnt_hi)<<16) + regs->reg42_s_bsp_bit_cnt_lo; ++ regs->enc_sumpqs = ((uint)(regs->regf6_s_mbr_last_frm_avg_qp_hi)<<16) + regs->regf5_s_mbr_last_frm_avg_qp_lo; ++ regs->mjob.i_tick = (int)(regs->enc_cycles); ++ regs->mjob.i_bits = (int)(regs->enc_bitcnt - regs->bits_delta); ++ if (bit & BIT_BUF_FULL) ++ { ++ printk(KERN_ERR"mfe-enc buffer full(%d/%u)\n", regs->outbs_size, (((uint)(regs->reg43_s_bsp_bit_cnt_hi)<<16) + regs->reg42_s_bsp_bit_cnt_lo)/8); ++ } ++ clr_irq(base, 0xFF); ++ return 0; ++} ++ ++static int _irq_mask( ++ mhve_ios* ios, ++ int msk) ++{ ++ mfe6_ios* asic = (mfe6_ios*)ios; ++ void* base = asic->p_base; ++ clr_irq(base, 0xFF); ++ msk_irq(base, 0xFF); ++ return 0; ++} +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_ios.h b/drivers/mstar/mfev5/mfe6/mfe6_ios.h +new file mode 100644 +index 00000000..5fa6ffd2 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_ios.h +@@ -0,0 +1,16 @@ ++ ++#ifndef _MFE6_IOS_H_ ++#define _MFE6_IOS_H_ ++ ++#include ++ ++typedef struct mfe6_ios { ++ mhve_ios mios; ++ void* p_base; ++ mfe6_reg* p_regs; ++} mfe6_ios; ++ ++#define BIT_ENC_DONE (1<<0) ++#define BIT_BUF_FULL (1<<1) ++ ++#endif/*_MFE6_IOS_H_*/ +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_ops.c b/drivers/mstar/mfev5/mfe6/mfe6_ops.c +new file mode 100644 +index 00000000..607071f9 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_ops.c +@@ -0,0 +1,1036 @@ ++#include ++ ++#define _ALIGN(b,x) (((x)+(1<<(b))-1)&(~((1<<(b))-1))) ++#define _BITS_(s) ((2<<(1?s))-(1<<(0?s))) ++#define _MAX_(a,b) ((a)>(b)?(a):(b)) ++#define _MIN_(a,b) ((a)<(b)?(a):(b)) ++ ++#define LOG2_MAX_FRAME_NUM_DEFAULT 8 ++ ++#define MVBLK_DEFAULT \ ++ (MHVE_INTER_SKIP|MHVE_INTER_16x16|MHVE_INTER_16x8|MHVE_INTER_8x16|\ ++ MHVE_INTER_8x8|MHVE_INTER_8x4|MHVE_INTER_4x8|MHVE_INTER_4x4) ++ ++static int _seq_sync(mhve_ops*); ++static int _seq_conf(mhve_ops*); ++static int _seq_done(mhve_ops*); ++static int _enc_buff(mhve_ops*, mhve_vpb*); ++static int _deq_buff(mhve_ops*, mhve_vpb*); ++static int _put_data(mhve_ops*, void*,int); ++static int _enc_conf(mhve_ops*); ++static int _enc_done(mhve_ops*); ++static int _out_buff(mhve_ops*, mhve_cpb*); ++static int _set_conf(mhve_ops*, mhve_cfg*); ++static int _get_conf(mhve_ops*, mhve_cfg*); ++static void* _rqct_ops(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ return mfe6->p_rqct; ++} ++static void* _mmfe_job(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ return mfe6->p_regs; ++} ++static void __ops_free(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ rqct_ops* rqct = mfe6->p_rqct; ++ mfe6_reg* regs = mfe6->p_regs; ++ if (rqct) ++ rqct->release(rqct); ++ if (regs) ++ MEM_FREE(regs); ++// MEM_FREE(mops); ++} ++ ++void* mmfeops_acquire(int id) ++{ ++ mfe6_ops* mfe6 = MEM_ALLC(sizeof(mfe6_ops)); ++ ++ if (!mfe6) ++ { ++ printk(KERN_ERR"%s() alloc fail\n", __func__); ++ return mfe6; ++ } ++ ++ /* default setting */ ++ do ++ { ++ mhve_ops* mops = &mfe6->ops; ++ sps_t* sps = &mfe6->m_sps; ++ pps_t* pps = &mfe6->m_pps; ++ slice_t* sh = &mfe6->m_sh; ++ /* OPs prototype configuration */ ++ mops->release = __ops_free; ++ mops->rqct_ops = _rqct_ops; ++ mops->mhve_job = _mmfe_job; ++ mops->seq_sync = _seq_sync; ++ mops->seq_conf = _seq_conf; ++ mops->seq_done = _seq_done; ++ mops->enc_buff = _enc_buff; ++ mops->deq_buff = _deq_buff; ++ mops->put_data = _put_data; ++ mops->enc_conf = _enc_conf; ++ mops->enc_done = _enc_done; ++ mops->out_buff = _out_buff; ++ mops->set_conf = _set_conf; ++ mops->get_conf = _get_conf; ++ ++ mfe6->p_rqct = rqctmfe_acquire(id); ++ mfe6->p_regs = MEM_ALLC(sizeof(mfe6_reg)); ++ mfe6->i_refn = 1; ++ mfe6->i_dmvx = 32; ++ mfe6->i_dmvy = 16; ++ mfe6->i_subp = 2; ++ mfe6->i_blkp[0] = MVBLK_DEFAULT; ++ mfe6->i_blkp[1] = 0; ++ /* user data */ ++ sps->i_profile_idc = 66; ++ sps->i_level_idc = 30; ++ sps->b_constraint_set0 = 0; ++ sps->b_constraint_set1 = 1; ++ sps->b_constraint_set2 = 0; ++ sps->b_constraint_set3 = 0; ++ sps->i_log2_max_frame_num = LOG2_MAX_FRAME_NUM_DEFAULT; ++ sps->i_poc_type = 2; ++ sps->i_log2_max_poc_lsb = 4; // not used for poc_type=2 ++ sps->i_num_ref_frames = mfe6->i_refn; ++ sps->b_gaps_in_frame_num_value_allow = 0; ++ sps->b_direct8x8_inference = 1; ++ sps->b_crop = 0; ++ /* gen pps */ ++ pps->i_pps_id = 0; ++ pps->b_cabac = 0; ++ pps->i_num_ref_idx_l0_default_active = sps->i_num_ref_frames; ++ pps->i_num_ref_idx_l1_default_active = sps->i_num_ref_frames; ++ pps->i_pic_init_qp = 26; ++ pps->i_pic_init_qs = 26; ++ pps->i_cqp_idx_offset = 0; ++ pps->b_redundant_pic_cnt = 0; ++ pps->b_deblocking_filter_control = 0; ++ pps->b_constrained_intra_pred = 0; ++ /* gen slice-header */ ++ sh->i_disable_deblocking_filter_idc = 0; ++ sh->i_alpha_c0_offset_div2 = 0; ++ sh->i_beta_offset_div2 = 0; ++ ++ if (!mfe6->p_rqct || !mfe6->p_regs) ++ { ++ mops->release(mops); ++ kfree(mops); ++ } ++ mfe6->i_rpbn = 2; ++ return mfe6; ++ } ++ while(0); ++ ++ return mfe6; ++} ++ ++static int _seq_done(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ rqct_ops* rqct = mfe6->p_rqct; ++ int i; ++ ++ rqct->seq_done(rqct); ++ ++ for (i = 0; i < mfe6->i_refn; i++) ++ { ++ mfe6->m_dpbs[AVC_REF_L0][i] = mfe6->m_dpbs[AVC_REF_L1][i] = mfe6->m_dpbs[AVC_REF_LTR][i] = NULL; ++ } ++ ++ return 0; ++} ++ ++#define MB_SIZE 16 ++#define CROP_UNIT_X 2 ++#define CROP_UNIT_Y 2 ++ ++static int _seq_sync(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ rqct_ops* rqct = mfe6->p_rqct; ++ sps_t* sps = &mfe6->m_sps; ++ pps_t* pps = &mfe6->m_pps; ++ slice_t* sh = &mfe6->m_sh; ++ int i; ++ ++ pps->sps = sps; ++ sh->sps = sps; ++ sh->pps = pps; ++ /* gen sps */ ++ sps->i_num_ref_frames = sh->b_long_term_reference ? 2 : 1;//mfe6->i_refn; ++ sps->b_vui_param_pres = 1; ++ sps->vui.b_video_signal_pres = 1; ++ sps->vui.i_video_format = 5; ++ sps->vui.b_video_full_range = 1; ++ sps->vui.b_colour_desc_pres = 0; ++ sps->vui.i_colour_primaries = 1; ++ sps->vui.i_transf_character = 1; ++ sps->vui.i_matrix_coeffs = 1; ++ /* gen pps */ ++ pps->i_pps_id = 0; ++ pps->i_num_ref_idx_l0_default_active = sps->i_num_ref_frames; ++ pps->i_num_ref_idx_l1_default_active = sps->i_num_ref_frames; ++ pps->i_pic_init_qp = 26; ++ pps->i_pic_init_qs = 26; ++ pps->b_redundant_pic_cnt = 0; ++ /* rate control */ ++ rqct->seq_sync(rqct); ++ /*!rate control */ ++ mfe6->b_seqh = 1; ++ mfe6->i_seqn = 0; ++ mfe6->i_obits = 0; ++ mfe6->i_total = 0; ++ ++ /* initialize picture buffer */ ++ for (i = 0; i < mfe6->i_rpbn; i++) ++ { ++ mfe6->m_rpbs[i].i_state = RPB_STATE_FREE; ++ } ++ for (i = mfe6->i_rpbn; i < RPB_MAX_NR; i++) ++ { ++ mfe6->m_rpbs[i].i_state = RPB_STATE_INVL; ++ } ++ ++ return 0; ++} ++ ++static int _enc_buff(mhve_ops* mops, mhve_vpb* mvpb) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ sps_t *sps = &mfe6->m_sps; ++ pps_t* pps = &mfe6->m_pps; ++ slice_t* sh = &mfe6->m_sh; ++ rqct_ops* rqct = mfe6->p_rqct; ++ mhve_job* mjob = (mhve_job*)mfe6->p_regs; ++ rpb_t* rpb; ++ rqct_buf rqcb; ++ rqct_cfg rqcf; ++ bs_t outbs, *bs = &outbs; ++ uchar nal; ++ int i, err = 0; ++ ++ mfe6->m_encp = *mvpb; ++ mvpb = &mfe6->m_encp; ++ ++ /* RQCT sequence header */ ++ if (mfe6->b_seqh) ++ rqct->seq_sync(rqct); ++ if (mvpb->u_flags&MHVE_FLAGS_FORCEI) ++ rqct->seq_sync(rqct); ++ if (mvpb->u_flags&MHVE_FLAGS_DISREF) ++ rqct->b_unrefp = 1; ++ rqcb.u_config = 0; ++ /* RQCT decide picture type */ ++ if (0 != (err = rqct->enc_buff(rqct, &rqcb))) ++ return err; ++ /* Prepare SPS/PPS in sequence header */ ++ if (mfe6->b_seqh) ++ { ++ static int mbs_level[5][2] = {{30, 40500},{31,108000},{32,216000},{40,245760},{50,589824}}; ++ int mbs; ++ sps->i_mb_w = mfe6->i_mbsw; ++ sps->i_mb_h = mfe6->i_mbsh; ++ sps->b_crop = 0; ++ if (mfe6->i_pixw&(MB_SIZE-1) || mfe6->i_pixh&(MB_SIZE-1)) ++ { ++ sps->b_crop = 1; ++ sps->crop.i_left = sps->crop.i_top = 0; ++ sps->crop.i_right = ((-mfe6->i_pixw)&(MB_SIZE-1))/CROP_UNIT_X; ++ sps->crop.i_bottom= ((-mfe6->i_pixh)&(MB_SIZE-1))/CROP_UNIT_Y; ++ } ++ mbs = sps->i_mb_w * sps->i_mb_h; ++ mbs = mbs * 30; ++ for (i = 0; i < 4 && mbs_level[i][1] < mbs; i++) ; ++ sps->i_level_idc = mbs_level[i][0]; ++ ++ if (sps->vui.b_timing_info_pres) ++ { ++ rqcf.type = RQCT_CFG_FPS; ++ if (!(err = rqct->get_rqcf(rqct, &rqcf))) ++ { ++ sps->vui.i_num_units_in_tick = (uint)rqcf.fps.d_fps; ++ sps->vui.i_time_scale = (uint)rqcf.fps.n_fps*2; ++ } ++ sps->vui.b_fixed_frame_rate = 1; ++ } ++ ++ avc_reset(bs, mfe6->m_seqh, 32); ++ avc_write_nal(bs, (NAL_PRIO_HIGHEST<<5)|NAL_SPS); ++ avc_write_sps(bs, sps); ++ avc_flush(bs); ++ avc_write_nal(bs, (NAL_PRIO_HIGHEST<<5)|NAL_PPS); ++ avc_write_pps(bs, pps); ++ avc_flush(bs); ++ mfe6->i_seqh = avc_count(bs); ++#if 0 ++ { ++ int i; ++ printk("mfe6->i_seqh = %d\n, start dump m_seqh : ", mfe6->i_seqh); ++ for(i=0;ii_seqh/8;i++) ++ printk("%x ", mfe6->m_seqh[i]); ++ printk("\n end of dump\n"); ++ } ++#endif ++ } ++ /* RQCT register setting */ ++ rqct->enc_conf(rqct, mjob); ++ ++ /* Prepare slice header paremeter */ ++ if (IS_IPIC(rqct->i_pictyp)) ++ { ++ sh->b_idr_pic = 1; ++ sh->i_ref_idc = NAL_PRIO_HIGHEST; ++ sh->b_ref_pic_list_modification_flag_l0 = 0; ++ sh->i_type = SLICE_I; ++ sh->i_frm_num = 0; ++ /* LTR setting */ ++ if (sh->b_long_term_reference) ++ { ++ sh->i_idr_pid = (sh->i_idr_pid+1)%2; ++ sh->i_num_ref_idx_l0_active = 0; ++ sh->i_poc = 0; ++ } ++ mvpb->u_flags|= MHVE_FLAGS_FORCEI; ++ mvpb->u_flags&=~MHVE_FLAGS_DISREF; ++ mfe6->b_seqh = 1; ++ } ++ else ++ { ++ sh->b_idr_pic = 0; ++ sh->i_frm_num = (sh->i_frm_num+1)%(1<i_log2_max_frame_num); ++ if (sh->b_long_term_reference && IS_LTRPPIC(rqct->i_pictyp)) ++ { ++ sh->i_ref_idc = NAL_PRIO_HIGH; ++ sh->i_type = SLICE_P; ++ sh->b_ref_pic_list_modification_flag_l0 = 1; ++ sh->rpl0_t[0].modification_of_pic_nums_idc = 2; ++ sh->rpl0_t[0].long_term_pic_num = 0; ++ sh->rpl0_t[1].modification_of_pic_nums_idc = 3; ++ /* LTR P ref P */ ++ if (mfe6->b_enable_pred) ++ sh->b_adaptive_ref_pic_marking_mode = 1; ++ else ++ sh->b_adaptive_ref_pic_marking_mode = 0; ++ sh->mmc_t[0].memory_management_control = 5; ++ sh->mmc_t[1].memory_management_control = 6; ++ sh->mmc_t[1].long_term_frame_idx = 0; ++ sh->mmc_t[2].memory_management_control = 0; ++ } ++ else ++ { ++ sh->i_ref_idc = (rqct->b_unrefp!=0)?NAL_PRIO_DISPOSED:NAL_PRIO_HIGH; ++ sh->i_type = IS_PPIC(rqct->i_pictyp)? SLICE_P : SLICE_B; ++ sh->b_ref_pic_list_modification_flag_l0 = 0; ++ sh->b_adaptive_ref_pic_marking_mode = 0; ++ if (!rqct->b_unrefp) ++ mvpb->u_flags &= ~MHVE_FLAGS_DISREF; ++ } ++ } ++ sh->i_qp = rqct->i_enc_qp; ++ ++ /* pick picture buffer for reconstructing */ ++ rpb = mfe6->p_recn; ++ if (!rpb) ++ { ++ /* find free buffer */ ++ for (i = 0; i < mfe6->i_rpbn; i++) ++ if (IS_FREE(mfe6->m_rpbs[i].i_state)) ++ break; ++ if (i == mfe6->i_rpbn) ++ { ++ printk(KERN_ERR"%s-buf idx overflow(%d)\n", __func__, i); ++ return -1; ++ } ++ rpb = &mfe6->m_rpbs[i]; ++ /* setup buffer state */ ++ rpb->i_state = RPB_STATE_BUSY; ++ if (sh->b_long_term_reference) ++ { ++ /* Long term keep buffer */ ++ if (IS_IPIC(rqct->i_pictyp) || (mfe6->b_enable_pred && IS_LTRPPIC(rqct->i_pictyp))) ++ rpb->i_state = RPB_STATE_KEEP; ++ } ++ mfe6->p_recn = rpb; ++ } ++ /* not allocate direct memory */ ++ if (!rpb->b_valid) ++ { ++ rpb->i_index = mvpb->i_index; ++ rpb->u_phys[RPB_YPIX] = mvpb->planes[0].u_phys; ++ rpb->u_phys[RPB_CPIX] = mvpb->planes[1].u_phys; ++ mvpb->i_index = -1; ++ } ++ ++ /* prepare slice header */ ++ nal = (sh->i_ref_idc<<5) | NAL_SLICE; ++ if (sh->b_idr_pic) ++ nal = (NAL_PRIO_HIGHEST<<5) | NAL_IDR; ++ avc_reset(bs, mfe6->m_pich, 32); ++ avc_write_nal(bs, nal); ++ avc_write_slice_header(bs, sh); ++ avc_flush(bs); ++ mfe6->i_pich = avc_count(bs); ++ ++ return 0; ++} ++ ++static int _deq_buff(mhve_ops* mops, mhve_vpb* mvpb) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ *mvpb = mfe6->m_encp; ++ return 0; ++} ++ ++static int _enc_done(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ slice_t* sh = &mfe6->m_sh; ++ rqct_ops* rqct = mfe6->p_rqct; ++ mfe6_reg* regs = mfe6->p_regs; ++ mhve_vpb* vpb = &mfe6->m_encp; ++ rpb_t* dpb = mfe6->p_recn; ++ int err = 0; ++ int i; ++ ++ /* rqct control */ ++ /* feedback to rate-controller */ ++ /* actually always return err = 0 */ ++ if ((err = rqct->enc_done(rqct, ®s->mjob))) ++ { ++ /* not allocate direct memory */ ++ if (!dpb->b_valid) ++ { ++ vpb->i_index = dpb->i_index; ++ dpb->i_index = -1; ++ } ++ mfe6->i_obits = ++ mfe6->u_oused = 0; ++ return err; ++ } ++ /* output information */ ++ mfe6->i_obits = (rqct->i_bitcnt); ++ mfe6->i_total+= (rqct->i_bitcnt)/8; ++ mfe6->u_oused+= (rqct->i_bitcnt + regs->bits_delta)/8; ++ /* update ref-list */ ++ if (sh->i_ref_idc) ++ { /* add recon. into reference list */ ++ int b_ltr_keep = 0; ++ rpb_t* out = NULL; ++ ++ /* get LTR status */ ++ if (dpb) ++ b_ltr_keep = IS_KEEP(dpb->i_state); ++ ++// /* clear reference count and buffer ref. status */ ++// for (i = 0; i < mfe6->i_rpbn; i++) ++// { ++// rpb_t* rpb = mfe6->m_rpbs+i; ++// if (!IS_KEEP(rpb->i_state)) ++// rpb->i_state = RPB_STATE_FREE; ++// } ++ /* update LTR list */ ++ if (b_ltr_keep) ++ { ++ /* return previos LTR buffer if encoded picture is LTR frame */ ++ out = mfe6->m_dpbs[AVC_REF_LTR][0]; ++ mfe6->m_dpbs[AVC_REF_LTR][0] = dpb; ++ sh->i_frm_num = 0; ++ } ++ else ++ { ++ /* find the return buffer */ ++ for (i = 0; i < mfe6->i_rpbn; i++) ++ { ++ rpb_t* rpb = mfe6->m_rpbs+i; ++ if (IS_BUSY(rpb->i_state) && rpb != dpb) ++ { ++ out = rpb; ++ break; ++ } ++ } ++ } ++ /* update STR list */ ++ for (i = 0; i < mfe6->i_refn; i++) ++ { ++ mfe6->m_dpbs[AVC_REF_L0][i] = dpb; ++ } ++ dpb = out; ++ if (++sh->i_num_ref_idx_l0_active > mfe6->i_refn) ++ sh->i_num_ref_idx_l0_active = mfe6->i_refn; ++ } ++ /* return buffer information */ ++ if (dpb) ++ { ++ /* shrink mode: find the return buffer index */ ++ if (!dpb->b_valid) ++ vpb->i_index = dpb->i_index; ++ dpb->i_index = -1; ++ dpb->i_state = RPB_STATE_FREE; ++ } ++ mfe6->p_recn = NULL; ++ ++sh->i_poc; ++ ++mfe6->i_seqn; ++ mfe6->b_seqh=0; ++ return 0; ++} ++ ++#define MHVE_FLAGS_CTRL (MHVE_FLAGS_FORCEI|MHVE_FLAGS_DISREF) ++ ++static int _out_buff(mhve_ops* mops, mhve_cpb* mcpb) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ mhve_vpb* mvpb = &mfe6->m_encp; ++ rqct_ops* rqct = mfe6->p_rqct; ++ slice_t* sh = &mfe6->m_sh; ++ int err = 0; ++ if (mcpb->i_index >= 0) ++ { ++ mfe6->u_oused = 0; ++ mcpb->planes[0].u_phys = 0; ++ mcpb->planes[0].i_size = 0; ++ mcpb->i_stamp = 0; ++ mcpb->i_flags = (MHVE_FLAGS_SOP | MHVE_FLAGS_EOP); ++ return err; ++ } ++ err = mfe6->u_oused; ++ mcpb->i_index = 0; ++ mcpb->planes[0].u_phys = mfe6->u_obase; ++ mcpb->planes[0].i_size = err; ++ mcpb->planes[0].i_bias = 0; ++ mcpb->i_stamp = mvpb->i_stamp; ++ mcpb->i_flags = (MHVE_FLAGS_SOP | MHVE_FLAGS_EOP); ++ if (err > 0) ++ mcpb->i_flags |= (mvpb->u_flags & MHVE_FLAGS_CTRL); ++ /* Add flag for LTR P-frame */ ++ if (sh->b_long_term_reference && IS_LTRPPIC(rqct->i_pictyp)) ++ mcpb->i_flags |= MVHE_FLAGS_LTR_PFRAME; ++ return err; ++} ++ ++static int _seq_conf(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ mfe6_reg* regs = mfe6->p_regs; ++ pps_t* pps = &mfe6->m_pps; ++ /* HW-IP related regs setting */ ++ // pre-fetch ++ regs->reg68_s_prfh_cryc_en = 1; // increase the tolerance of DRAM latency ++ regs->reg68_s_prfh_refy_en = 1; // increase the tolerance of DRAM latency ++ regs->reg6d_s_prfh_cryc_idle_cnt = 0; ++ regs->reg6d_s_prfh_refy_idle_cnt = 0; ++ // pixel format ++ regs->reg03_g_mstar_tile = 1; ++ regs->regd6_g_yuvldr_en = 0; ++ regs->regf4_s_plnrldr_en = 1; ++ // qtable ++ regs->reg03_g_qmode = 0; ++ // frame coding only ++ regs->reg03_g_fldpic_en = 0; ++ // NOT SW Buffer Mode ++ regs->reg73_g_sw_buffer_mode = 0; ++ regs->reg18_g_jpe_buffer_mode = 1; // frame-mode ++ regs->reg18_g_jpe_fsvs_mode = 0; ++ regs->reg18_g_viu_soft_rstz = 1; ++ // IMI buffer: low bandwidth ++ regs->reg68_s_marb_imi_burst_thd = 8; ++ regs->reg68_s_marb_imi_timeout = 7; ++ regs->reg68_s_marb_imilast_thd = 4; ++ // IMI setting ++ regs->reg68_s_marb_eimi_block = 0; ++ regs->reg68_s_marb_lbwd_mode = 0; ++ regs->reg6b_s_marb_imi_saddr_lo = 0; ++ regs->reg6c_s_marb_imi_saddr_hi = 0; ++#if defined(MMFE_IMI_LBW_ADDR) ++ if (mfe6->i_pctw < 2048) ++ { ++ regs->reg68_s_marb_eimi_block = 1; ++ regs->reg68_s_marb_lbwd_mode = 1; ++ regs->reg6b_s_marb_imi_saddr_lo = (MMFE_IMI_LBW_ADDR>> 4)&0xFFFF; ++ regs->reg6c_s_marb_imi_saddr_hi = (MMFE_IMI_LBW_ADDR>>20)|0x1000; ++ regs->reg6c_s_marb_imi_cache_size = 0; // imi cache size (0: 64kB, 1:32kB, 2:16kB, 3:8kB) ++ } ++#endif ++ // IMI buffer: dbf last-line ++#if defined(MMFE_IMI_DBF_ADDR) ++ regs->reg4f_s_gn_bwr_mode = 3; ++ regs->reg4e_s_gn_mvibuf_saddr_lo = (MMFE_IMI_DBF_ADDR>> 3)&0xFFFF; ++ regs->reg4f_s_gn_mvibuf_saddr_hi = (MMFE_IMI_DBF_ADDR>>19)|0x0800; ++#else ++ regs->reg4f_s_gn_bwr_mode = 0; ++ regs->reg4e_s_gn_mvibuf_saddr_lo = 0; ++ regs->reg4f_s_gn_mvibuf_saddr_hi = 0; ++#endif ++ // Frame Coding Only ++ regs->reg2a_s_mvdctl_ref0_offset = 0; ++ regs->reg2a_s_mvdctl_ref1_offset = 0; ++ regs->reg7d_s_txip_eco0 = 0; ++ regs->reg7d_s_txip_eco1 = 0; ++ regs->reg7d_eco_mreq_stallgo = 1; ++ regs->reg7d_eco_marb_stallgo = 0; ++ regs->reg7d_reserved1 = 0; ++ regs->reg7d_eco_bsp_stuffing = 1; ++ regs->reg7d_eco_bsp_rdy_fix = 1; ++ regs->reg7d_eco_bsp_multi_slice_fix = 0; ++ /* global regs values (codec related) */ ++ regs->reg20_s_me_16x16_disable = !(mfe6->i_blkp[0]&MHVE_INTER_16x16); ++ regs->reg20_s_me_16x8_disable = !(mfe6->i_blkp[0]&MHVE_INTER_16x8); ++ regs->reg20_s_me_8x16_disable = !(mfe6->i_blkp[0]&MHVE_INTER_8x16); ++ regs->reg20_s_me_8x8_disable = !(mfe6->i_blkp[0]&MHVE_INTER_8x8); ++ regs->reg20_s_me_8x4_disable = !(mfe6->i_blkp[0]&MHVE_INTER_8x4); ++ regs->reg20_s_me_4x8_disable = !(mfe6->i_blkp[0]&MHVE_INTER_4x8); ++ regs->reg20_s_me_4x4_disable = !(mfe6->i_blkp[0]&MHVE_INTER_4x4); ++ regs->reg20_s_mesr_adapt = 1; ++ regs->reg21_s_ime_sr16 = (mfe6->i_dmvx<=16); ++ regs->reg21_s_ime_umv_disable = 0; ++ regs->reg22_s_ime_mesr_max_addr = (mfe6->i_dmvy==16 ? 95 : 85); ++ regs->reg22_s_ime_mesr_min_addr = (mfe6->i_dmvy==16 ? 0 : 10); ++ regs->reg23_s_ime_mvx_min = _MAX_(-mfe6->i_dmvx+32,-32+32); ++ regs->reg23_s_ime_mvx_max = _MIN_( mfe6->i_dmvx+32, 31+31); ++ regs->reg24_s_ime_mvy_min = _MAX_(-mfe6->i_dmvy+16,-16+16); ++ regs->reg24_s_ime_mvy_max = _MIN_( mfe6->i_dmvy+16, 16+15); ++ regs->reg25_s_fme_quarter_disable = (mfe6->i_subp!=2); ++ regs->reg25_s_fme_half_disable = (mfe6->i_subp==0); ++ regs->reg25_s_fme_pmv_enable = 0!=(mfe6->i_blkp[0]&MHVE_INTER_SKIP); ++ regs->reg2b_s_ieap_constraint_intra = pps->b_constrained_intra_pred; ++ regs->reg2b_s_ieap_last_mode = 8; ++ regs->reg2b_s_ieap_ccest_en = 0; ++ regs->reg2b_s_ieap_ccest_thr = 0; ++ regs->reg2b_s_ieap_drop_i16 = 0; ++ regs->reg2b_s_ieap_early_termination = 1; ++ regs->reg2c_g_ieap_sram_4x2_swap = 1; ++ if (mfe6->i_mbsw < 16) ++ regs->regfd_eco = 1; ++ return 0; ++} ++ ++static int _put_data(mhve_ops* mops, void* user, int size) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ mfe6_reg* regs = mfe6->p_regs; ++ char* src; ++ char* dst; ++ int bcnt = 0; ++ int bits = 0; ++ ++ if (size > 0) ++ { ++ dst = mfe6->p_okptr; ++ /* insert parm-sets */ ++ if (mfe6->b_seqh) ++ { ++ MEM_COPY(dst, mfe6->m_seqh, mfe6->i_seqh/8); ++ bcnt+= mfe6->i_seqh; ++ dst += mfe6->i_seqh/8; ++ } ++ /* insert user-data */ ++ MEM_COPY(dst, user, size); ++ bcnt+= size*8; ++ dst += size; ++ /* insert slice-header */ ++ MEM_COPY(dst, mfe6->m_pich, mfe6->i_pich/8+1); ++ bits = mfe6->i_pich; ++ bcnt+= bits; ++ mfe6->u_oused = (bcnt>>11)*256; ++ src = mfe6->p_okptr + mfe6->u_oused; ++ dst = regs->bits_coded; ++ MEM_COPY(dst, src, ((bcnt+7)/8)&255); ++ regs->bits_count = bcnt&2047; ++ regs->bits_delta = regs->bits_count - bits; ++ } ++ else ++ { ++ dst = regs->bits_coded; ++ /* insert parm-sets */ ++ if (mfe6->b_seqh) ++ { ++ MEM_COPY(dst, mfe6->m_seqh, mfe6->i_seqh/8); ++ bcnt+= mfe6->i_seqh; ++ dst += mfe6->i_seqh/8; ++ } ++ /* insert slice-header */ ++ MEM_COPY(dst, mfe6->m_pich, mfe6->i_pich/8+1); ++ bits = mfe6->i_pich; ++ bcnt+= bits; ++ regs->bits_count = bcnt; ++ regs->bits_delta = bcnt - bits; ++ mfe6->u_oused = 0; ++ } ++ return 0; ++} ++ ++static int _enc_conf(mhve_ops* mops) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ mhve_vpb* encp = &mfe6->m_encp; ++ mfe6_reg* regs = mfe6->p_regs; ++ sps_t* sps = &mfe6->m_sps; ++ pps_t* pps = &mfe6->m_pps; ++ slice_t* sh = &mfe6->m_sh; ++ rpb_t* rpb = NULL; ++ uint phys; ++ ushort v; ++ // codec type ( only support h.264 ) ++ regs->reg00_g_enc_mode = MFE_REG_ENC_H264; ++ regs->reg03_g_cabac_en = pps->b_cabac; ++ switch (mfe6->e_pixf) ++ { ++ case MHVE_PIX_NV21: ++ regs->regf3_s_plnrldr_c_swap = MFE_REG_PLNRLDR_VU; ++ case MHVE_PIX_NV12: ++ regs->regf3_s_plnrldr_format = MFE_REG_PLNRLDR_420; ++ regs->reg90_g_capture_width_y= mfe6->m_encp.i_pitch; ++ regs->reg91_g_capture_width_c= mfe6->m_encp.i_pitch>>1; ++ break; ++ case MHVE_PIX_YVYU: ++ regs->regf3_s_plnrldr_c_swap = MFE_REG_PLNRLDR_VU; ++ case MHVE_PIX_YUYV: ++ regs->regf3_s_plnrldr_format = MFE_REG_PLNRLDR_422; ++ regs->reg90_g_capture_width_y= mfe6->m_encp.i_pitch; ++ regs->reg91_g_capture_width_c = 0; ++ break; ++ default: ++ break; ++ } ++ // resolution ++ regs->reg01_g_pic_width = mfe6->i_pctw; ++ regs->reg02_g_pic_height= mfe6->i_pcth; ++ // mdc ++ regs->reg29_s_mbr_qp_cidx_offset = pps->i_cqp_idx_offset; ++ // clock gating ++ regs->reg16 = 0xFFFF; ++ // per-frame: ref_frames/frame_type ++ regs->reg00_g_frame_type = sh->i_type==SLICE_I?MFE_REG_ITYPE:sh->i_type==SLICE_P?MFE_REG_PTYPE:MFE_REG_BTYPE; ++ regs->reg00_g_ref_no = sh->i_num_ref_idx_l0_active==2?MFE_REG_REF_NUM_TWO:MFE_REG_REF_NUM_ONE; ++ // per-frame: slice parameters ++ regs->reg39_s_mdc_h264_nal_ref_idc = sh->i_ref_idc; ++ regs->reg39_s_mdc_h264_nal_unit_type = sh->b_idr_pic; ++ regs->reg39_s_mdc_h264_fnum_bits = sps->i_log2_max_frame_num-5; ++ regs->reg39_s_mdc_h264_dbf_control = pps->b_deblocking_filter_control; ++ regs->reg39_s_mdc_h264_fnum_value = sh->i_frm_num; ++ regs->reg3a_s_mdc_h264_idr_pic_id = sh->i_idr_pid; ++ regs->reg3a_s_mdc_h264_disable_dbf_idc = sh->i_disable_deblocking_filter_idc; ++ regs->reg3a_s_mdc_h264_alpha = sh->i_alpha_c0_offset_div2; ++ regs->reg3a_s_mdc_h264_beta = sh->i_beta_offset_div2; ++ regs->reg3a_s_mdc_h264_ridx_aor_flag = (sh->i_num_ref_idx_l0_active!=sh->pps->i_num_ref_idx_l0_default_active); ++ // per-frame: buffer setting: current/reference/reconstructing ++ phys = encp->planes[0].u_phys+encp->planes[0].i_bias; ++ regs->reg06_g_cur_y_addr_lo = (ushort)(phys>> 8); ++ regs->reg07_g_cur_y_addr_hi = (ushort)(phys>>24); ++ phys = encp->planes[1].u_phys+encp->planes[1].i_bias; ++ regs->reg08_g_cur_c_addr_lo = (ushort)(phys>> 8); ++ regs->reg09_g_cur_c_addr_hi = (ushort)(phys>>24); ++ ++ /* setup ref. picture */ ++ if (sh->b_long_term_reference && sh->b_ref_pic_list_modification_flag_l0) ++ { ++ rpb = mfe6->m_dpbs[AVC_REF_LTR][0]; ++ } ++ else if (sh->i_num_ref_idx_l0_active) ++ { ++ rpb = mfe6->m_dpbs[AVC_REF_L0][0]; ++ } ++ if (rpb) ++ { ++ regs->reg0a_g_ref_y_addr0_lo = (ushort)(rpb->u_phys[RPB_YPIX]>> 8); ++ regs->reg0b_g_ref_y_addr0_hi = (ushort)(rpb->u_phys[RPB_YPIX]>>24); ++ regs->reg0e_g_ref_c_addr0_lo = (ushort)(rpb->u_phys[RPB_CPIX]>> 8); ++ regs->reg0f_g_ref_c_addr0_hi = (ushort)(rpb->u_phys[RPB_CPIX]>>24); ++ } ++ else if (!rpb && sh->i_type != SLICE_I) ++ { ++ printk(KERN_ERR"%s() null ref buf err.\n", __func__); ++ return -1; ++ } ++ ++ /* setup recn buffer */ ++ regs->reg12_g_rec_y_addr_lo = (ushort)(mfe6->p_recn->u_phys[RPB_YPIX]>> 8); ++ regs->reg13_g_rec_y_addr_hi = (ushort)(mfe6->p_recn->u_phys[RPB_YPIX]>>24); ++ regs->reg14_g_rec_c_addr_lo = (ushort)(mfe6->p_recn->u_phys[RPB_CPIX]>> 8); ++ regs->reg15_g_rec_c_addr_hi = (ushort)(mfe6->p_recn->u_phys[RPB_CPIX]>>24); ++ // Output buffers: Must be 8-byte aligned. ++ regs->reg3f_s_bspobuf_hw_en = 0; ++ // GN ++ regs->reg4c_s_gn_saddr_lo = (ushort)(mfe6->u_mbp_base>> 3); ++ regs->reg4d_s_gn_saddr_hi = (ushort)(mfe6->u_mbp_base>>19); ++ regs->reg4d_s_gn_saddr_mode = 0; // 0: gn data row, 1: gn data frame. ++ // Motion search ++ regs->reg20_s_me_ref_en_mode = (1<i_num_ref_idx_l0_active)-1; ++ // FME ++ regs->reg21_s_ime_ime_wait_fme = 1; ++ regs->reg25_s_fme_pipeline_on = regs->reg21_s_ime_ime_wait_fme ? 1 : 0; ++ // P8x8 BOUND RECT ++ regs->reg21_s_ime_boundrect_en = (sps->i_profile_idc==66 && sps->i_level_idc<=30); ++ regs->reg21_s_ime_h264_p8x8_ctrl_en = 0;//mfeinfo->i_p8x8_max_count < mfe6->i_mb_wxh ? 1 : 0; ++ ++ regs->reg25_s_fme_mode0_refno = 1; ++ regs->reg25_s_fme_mode1_refno = 1; ++ regs->reg25_s_fme_mode2_refno = 1; ++ regs->reg25_s_fme_mode_no = (mfe6->i_mbsn <= 396); ++ // Intra update (force disabled) ++ regs->reg2f_s_txip_irfsh_en = 0; ++ regs->reg2c_s_quan_idx_last = 63; ++ if (regs->reg2c_s_quan_idx_last < 63) ++ regs->reg2c_s_quan_idx_swlast = 1; ++ else ++ regs->reg2c_s_quan_idx_swlast = 0; ++ /* multi-slice mode */ ++ v = mfe6->i_rows > 0; ++ if (mfe6->i_bits > 0) ++ v += 2; ++ regs->reg03_g_er_mode = _BITS_(1:0)&(v-1); ++ /* multi-slice by bits */ ++ regs->reg04_g_er_bs_th = mfe6->i_bits; ++ /* multi-slice by row: 1/2/4/8 */ ++ for (v = 0; v < 3 && mfe6->i_rows > (int)(1<reg03_g_er_mby = v; ++ /* set poc */ ++ regs->regf7_s_mdc_h264_poc = sh->i_poc; ++ regs->regf8_s_mdc_h264_poc_enable = (sps->i_poc_type == 0 ? 1 : 0); ++ regs->regf8_s_mdc_h264_poc_width = sps->i_log2_max_poc_lsb; ++ ++ if (regs->regf2_g_roi_en != 0) ++ regs->reg00_g_mbr_en = 0; ++ regs->reg00_g_rec_en = 1; ++ ++ regs->coded_data = regs->bits_coded; ++ regs->coded_bits = regs->bits_count; ++ regs->outbs_addr = mfe6->u_obase + mfe6->u_oused; ++ regs->outbs_size = mfe6->u_osize - mfe6->u_oused; ++ return 0; ++} ++ ++static int _set_conf(mhve_ops* mops, mhve_cfg* mcfg) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ rqct_cfg rqcf; ++ int i, err = -1; ++ switch (mcfg->type) ++ { ++ case MHVE_CFG_RES: ++ if ((unsigned)mcfg->res.e_pixf <= MHVE_PIX_YVYU) ++ { ++ mfe6->e_pixf = mcfg->res.e_pixf; ++ mfe6->i_pixw = mcfg->res.i_pixw; ++ mfe6->i_pixh = mcfg->res.i_pixh; ++ mfe6->i_pctw = _ALIGN(4,mcfg->res.i_pixw); ++ mfe6->i_pcth = _ALIGN(4,mcfg->res.i_pixh); ++ mfe6->i_rpbn = mcfg->res.i_rpbn; ++ mfe6->u_conf = mcfg->res.u_conf; ++ mfe6->i_mbsw = mfe6->i_pctw >>4; ++ mfe6->i_mbsh = mfe6->i_pcth >>4; ++ mfe6->i_mbsn = mfe6->i_mbsw*mfe6->i_mbsh; ++ mfe6->b_seqh = 1; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_DMA: ++ if (mcfg->dma.i_dmem >= 0) ++ { ++ uint addr = mcfg->dma.u_phys; ++ int i = mcfg->dma.i_dmem; ++ rpb_t* ref = mfe6->m_rpbs+i; ++ ref->i_index =-1; ++ ref->i_state = RPB_STATE_FREE; ++ ref->u_phys[RPB_YPIX] = !mcfg->dma.i_size[0]?0:addr; ++ addr += mcfg->dma.i_size[0]; ++ ref->u_phys[RPB_CPIX] = !mcfg->dma.i_size[1]?0:addr; ++ addr += mcfg->dma.i_size[1]; ++ ref->b_valid = ref->u_phys[RPB_YPIX]!=0; ++ err = 0; ++ } ++ else if (mcfg->dma.i_dmem == MHVE_CFG_DMA_OUTPUT_BUFFER) ++ { ++ mfe6->p_okptr = mcfg->dma.p_vptr; ++ mfe6->u_obase = mcfg->dma.u_phys; ++ mfe6->u_osize = mcfg->dma.i_size[0]; ++ mfe6->u_oused = 0; ++ err = 0; ++ } ++ else if (mcfg->dma.i_dmem == MHVE_CFG_DMA_NALU_BUFFER) ++ { ++ mfe6->u_mbp_base = mcfg->dma.u_phys; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_MOT: ++ mfe6->i_subp = mcfg->mot.i_subp; ++ mfe6->i_dmvx = mcfg->mot.i_dmvx; ++ mfe6->i_dmvy = mcfg->mot.i_dmvy; ++ mfe6->i_blkp[0] = mcfg->mot.i_blkp[0]; ++ mfe6->i_blkp[1] = 0; ++ err = 0; ++ break; ++ case MHVE_CFG_AVC: ++ { ++ sps_t* sps = &mfe6->m_sps; ++ pps_t* pps = &mfe6->m_pps; ++ slice_t* sh = &mfe6->m_sh; ++ mfe6->i_refn = 1; ++ sps->i_profile_idc = MHVE_AVC_PROFILE_MP; ++ if (mcfg->avc.i_profile < MHVE_AVC_PROFILE_MP) ++ { ++ sps->i_profile_idc = MHVE_AVC_PROFILE_BP; ++ pps->b_cabac = 0; ++ } ++ if (mcfg->avc.i_level < MHVE_AVC_LEVEL_3) ++ sps->i_level_idc = MHVE_AVC_LEVEL_3; ++ if (mcfg->avc.i_level > MHVE_AVC_LEVEL_4) ++ sps->i_level_idc = MHVE_AVC_LEVEL_4; ++ sps->i_poc_type = mcfg->avc.i_poc_type==0?0:2; ++ pps->b_cabac = mcfg->avc.b_entropy_coding_type!=0; ++ pps->b_deblocking_filter_control = mcfg->avc.b_deblock_filter_control; ++ pps->b_constrained_intra_pred = mcfg->avc.b_constrained_intra_pred; ++ sh->i_disable_deblocking_filter_idc = mcfg->avc.i_disable_deblocking_idc; ++ sh->i_alpha_c0_offset_div2 = mcfg->avc.i_alpha_c0_offset; ++ sh->i_beta_offset_div2 = mcfg->avc.i_beta_offset; ++ mfe6->b_seqh = 1; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_VUI: ++ { ++ sps_t* sps = &mfe6->m_sps; ++ sps->b_vui_param_pres = 0; ++ sps->vui.b_video_full_range = mcfg->vui.b_video_full_range != 0; ++ if (sps->vui.b_video_full_range) ++ { ++ sps->vui.b_video_signal_pres = 1; ++ sps->vui.i_video_format = 5; ++ sps->vui.b_colour_desc_pres = 0; ++ sps->b_vui_param_pres = 1; ++ } ++ sps->vui.b_timing_info_pres = mcfg->vui.b_timing_info_pres != 0; ++ if (sps->vui.b_timing_info_pres) ++ { ++ rqcf.type = RQCT_CFG_FPS; ++ if (!(err = rqct->get_rqcf(rqct, &rqcf))) ++ { ++ sps->vui.i_num_units_in_tick = (uint)rqcf.fps.d_fps; ++ sps->vui.i_time_scale = (uint)rqcf.fps.n_fps*2; ++ sps->vui.b_fixed_frame_rate = 1; ++ } ++ } ++ mfe6->b_seqh = 1; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_SPL: ++ mfe6->i_bits = mcfg->spl.i_bits; ++ mfe6->i_rows = 0; ++ if (0 < mcfg->spl.i_rows) ++ { ++ for (i = 1; i < 8 && mcfg->spl.i_rows > i; i = i<<1); ++ mfe6->i_rows = mcfg->spl.i_rows = i; ++ } ++ err = 0; ++ break; ++ case MHVE_CFG_LTR: ++ { ++ slice_t* sh = &mfe6->m_sh; ++ sps_t* sps = &mfe6->m_sps; ++ if (mcfg->ltr.b_long_term_reference) ++ { ++ /* NALU setting */ ++ sh->b_long_term_reference = 1; ++ sh->b_num_ref_idx_override = 1; ++ sps->i_log2_max_frame_num = LOG2_MAX_FRAME_NUM_DEFAULT+2; ++ sps->b_gaps_in_frame_num_value_allow = 1; ++ mfe6->b_enable_pred = mcfg->ltr.b_enable_pred; ++ } ++ else ++ { ++ /* NALU setting */ ++ sh->b_long_term_reference = 0; ++ sh->b_num_ref_idx_override = 0; ++ sps->i_log2_max_frame_num = LOG2_MAX_FRAME_NUM_DEFAULT; ++ sps->b_gaps_in_frame_num_value_allow = 0; ++ mfe6->b_enable_pred = 0; ++ } ++ err = 0; ++ } ++ break; ++ default: ++ break; ++ } ++ return err; ++} ++ ++static int _get_conf(mhve_ops* mops, mhve_cfg* mcfg) ++{ ++ mfe6_ops* mfe6 = (mfe6_ops*)mops; ++ int err = -1; ++ switch (mcfg->type) ++ { ++ case MHVE_CFG_RES: ++ mcfg->res.e_pixf = mfe6->e_pixf; ++ mcfg->res.i_pixw = mfe6->i_pixw; ++ mcfg->res.i_pixh = mfe6->i_pixh; ++ mcfg->res.i_rpbn = mfe6->i_rpbn; ++ mcfg->res.u_conf = mfe6->u_conf; ++ err = 0; ++ break; ++ case MHVE_CFG_MOT: ++ mcfg->mot.i_subp = mfe6->i_subp; ++ mcfg->mot.i_dmvx = mfe6->i_dmvx; ++ mcfg->mot.i_dmvy = mfe6->i_dmvy; ++ mcfg->mot.i_blkp[0] = mfe6->i_blkp[0]; ++ mcfg->mot.i_blkp[1] = 0; ++ err = 0; ++ break; ++ case MHVE_CFG_AVC: ++ { ++ sps_t* sps = &mfe6->m_sps; ++ pps_t* pps = &mfe6->m_pps; ++ slice_t* sh = &mfe6->m_sh; ++ mcfg->avc.i_profile = sps->i_profile_idc; ++ mcfg->avc.i_level = sps->i_level_idc; ++ mcfg->avc.i_num_ref_frames = mfe6->i_refn; ++ mcfg->avc.i_poc_type = sps->i_poc_type; ++ mcfg->avc.b_entropy_coding_type = pps->b_cabac; ++ mcfg->avc.b_deblock_filter_control = pps->b_deblocking_filter_control; ++ mcfg->avc.b_constrained_intra_pred = pps->b_constrained_intra_pred; ++ mcfg->avc.i_disable_deblocking_idc = sh->i_disable_deblocking_filter_idc; ++ mcfg->avc.i_alpha_c0_offset = sh->i_alpha_c0_offset_div2; ++ mcfg->avc.i_beta_offset = sh->i_beta_offset_div2; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_VUI: ++ { ++ sps_t* sps = &mfe6->m_sps; ++ mcfg->vui.b_video_full_range = sps->b_vui_param_pres!=0 && sps->vui.b_video_full_range!=0; ++ mcfg->vui.b_timing_info_pres = sps->b_vui_param_pres!=0 && sps->vui.b_timing_info_pres!=0; ++ err = 0; ++ } ++ break; ++ case MHVE_CFG_SPL: ++ mcfg->spl.i_rows = mfe6->i_rows; ++ mcfg->spl.i_bits = mfe6->i_bits; ++ err = 0; ++ break; ++ case MHVE_CFG_LTR: ++ { ++ slice_t* sh = &mfe6->m_sh; ++ if (sh->b_long_term_reference) ++ { ++ mcfg->ltr.b_long_term_reference = 1; ++ mcfg->ltr.b_enable_pred = mfe6->b_enable_pred; ++ } ++ else ++ { ++ mcfg->ltr.b_long_term_reference = 0; ++ mcfg->ltr.b_enable_pred = 0; ++ } ++ err = 0; ++ } ++ break; ++ default: ++ break; ++ } ++ return err; ++} +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_ops.h b/drivers/mstar/mfev5/mfe6/mfe6_ops.h +new file mode 100644 +index 00000000..5f6d6d7f +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_ops.h +@@ -0,0 +1,99 @@ ++#ifndef _MFE6_OPS_H_ ++#define _MFE6_OPS_H_ ++ ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++typedef struct rpb_t ++{ ++ char b_valid; /* 1: allocated direct memory. 0: use pic+'s memory */ ++#define RPB_STATE_FREE 0 ++#define RPB_STATE_BUSY 1 ++#define RPB_STATE_KEEP 2 // Identify this recn buffer is used to LTR reference picture ++#define RPB_STATE_INVL -1 ++#define IS_FREE(s) ((s)==RPB_STATE_FREE) ++#define IS_BUSY(s) ((s)==RPB_STATE_BUSY) ++#define IS_KEEP(s) ((s)==RPB_STATE_KEEP) ++#define IS_INVL(s) ((s)==RPB_STATE_INVL) ++ char i_state; ++ short i_index; /* only used in case b_valid is 0 that can keep cache buffer index */ ++#define RPB_YPIX 0 ++#define RPB_CPIX 1 ++#define RPB_SIZE 2 ++ uint u_phys[RPB_SIZE]; ++} rpb_t; ++ ++typedef enum AVC_REF_LIST ++{ ++ AVC_REF_L0 = 0, ++ AVC_REF_L1 = 1, ++ AVC_REF_LTR = 2, ++ AVC_REF_MAX = 3, ++} AVC_REF_LIST; ++ ++typedef struct mfe6_ops ++{ ++ mhve_ops ops; ++ /* mfe-registers */ ++ mfe6_reg* p_regs; ++ /* rate control */ ++ rqct_ops* p_rqct; ++ /* seq counter */ ++ mhve_vpb m_encp; // video picture buffer ++ int i_seqn; ++ int b_seqh; // sequence header ++ /* current resource */ ++ mhve_pix_e e_pixf; ++ short i_pixw, i_pixh; ++#define RPB_MAX_NR 4 ++ int i_rpbn; // reconstruct buffer numbers ++ rpb_t m_rpbs[RPB_MAX_NR]; ++ uint u_conf; ++ short i_pctw, i_pcth; // align 16 pixels width/height ++ short i_mbsw, i_mbsh; // MB level width/height ++ int i_mbsn; // marco block number ++ /* motion search */ ++ int i_dmvx; ++ int i_dmvy; ++ int i_subp; ++ uint i_blkp[2]; ++ /* h264_enc */ ++ sps_t m_sps; ++ pps_t m_pps; ++ slice_t m_sh; ++ /* multi-slices */ ++ int i_rows; ++ int i_bits; ++ /* feedback and statistic */ ++ int i_total; ++ int i_obits; ++ /* output bits */ ++ char* p_okptr; ++ uint u_obase; ++ uint u_osize; ++ uint u_obias; ++ uint u_oused; ++ uint u_vacan; ++ /*!output bits */ ++ uint u_mbp_base; ++ /* frame buffers */ ++ int i_refn; // reference frame numbers (1 or 2(multi-ref mode)) ++ rpb_t* p_recn; // reconstruct buffer header ++ rpb_t* m_dpbs[AVC_REF_MAX][RPB_MAX_NR]; ++ /* fragment of bits */ ++ /* sequence header */ ++ int i_seqh; ++ uchar m_seqh[64]; ++ /* picture header */ ++ int i_pich; ++ uchar m_pich[32]; ++ /* LTR */ ++ int b_enable_pred; // 0: P ref. I-frame, 1: P ref P-frame ++} mfe6_ops; ++ ++#endif//_MFE6_OPS_H_ +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_reg.h b/drivers/mstar/mfev5/mfe6/mfe6_reg.h +new file mode 100644 +index 00000000..c06e2d03 +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_reg.h +@@ -0,0 +1,1218 @@ ++ ++#ifndef _MFE6_REG_H_ ++#define _MFE6_REG_H_ ++ ++#include ++ ++// IRQ's ++#define IRQ_LESS_ROW_DONE 7 ++#define IRQ_NET_TRIGGER 6 ++#define IRQ_FS_FAIL 5 ++#define IRQ_TXIP_TIME_OUT 4 ++#define IRQ_BSPOBUF_FULL 3 ++#define IRQ_IMG_BUF_FULL 2 ++#define IRQ_MARB_BSPOBUF_FULL 1 ++#define IRQ_FRAME_DONE 0 ++ ++#define CHECK_IRQ_STATUS(r,irq) ((r>>irq)&1) ++ ++typedef struct mfe6_reg { ++ mhve_job mjob; ++ /* sw-coded data followed by mfe-output stream */ ++ void* coded_data; ++ int coded_bits; ++ uchar bits_coded[256]; ++ int bits_count; ++ int bits_delta; ++ /* miu address for mfe-hw */ ++ uint outbs_addr; ++ int outbs_size; ++ /* ticks for profiling */ ++ uint enc_cycles; ++ uint enc_bitcnt; ++ uint enc_sumpqs; ++ /* mfe-regs bank definition */ ++ union { ++ struct { ++ ushort reg00_g_frame_start_sw:1; // frame start (1T clk_mfe) ++ ushort reg00_g_soft_rstz:1; // software reset; 0/1: reset/not reset ++ ushort reg00_g_enc_mode:2; // 0/1/2/3: MPEG4/H263/H264/JPEG ++ #define MFE_REG_ENC_MPG4 0 ++ #define MFE_REG_ENC_H263 1 ++ #define MFE_REG_ENC_H264 2 ++ #define MFE_REG_ENC_JPEG 3 ++ ushort reg00_g_frame_type:2; // 0/1/2: I/P/B ++ #define MFE_REG_ITYPE 0 ++ #define MFE_REG_PTYPE 1 ++ #define MFE_REG_BTYPE 2 ++ ushort reg00_g_ref_no:1; // 0/1: 1 frame/2 frames ++ #define MFE_REG_REF_NUM_ONE 0 ++ #define MFE_REG_REF_NUM_TWO 1 ++ ushort reg00_g_mbr_en:1; // 0/1: disable/enable MB-level Rate control ++ ushort reg00_g_qscale:6; // frame level qscale: [H264]: 1 ~ 51; [MPEG4]: 1 ~ 31 ++ ushort reg00_g_rec_en:1; // reconstruct enable ++ ushort reg00_g_jpe_mst422_mode:1; // YUV422 input buffer format; 0: YUYV, 1: MST422 ++ }; ++ ushort reg00; ++ }; ++ union { ++ struct { ++ ushort reg01_g_pic_width:16; // picture width ++ }; ++ ushort reg01; ++ }; ++ union { ++ struct { ++ ushort reg02_g_pic_height:16; // picture height ++ }; ++ ushort reg02; ++ }; ++ union { ++ struct { ++ ushort reg03_g_er_mode:2; // 0/1/2/3: mby/bs/mby+bs/off ++ ushort reg03_g_er_mby:2; // 0/1/2/3: every 1/2/4/8 mb row(s) (error resilence) ++ ushort reg03_g_packed_mode:1; // frame buffer format for 422 packed mode; 0/1: YVYU/YUYV ++ ushort reg03_g_qmode:1; // quantization method; 0/1: h263/mp4 ++ ushort reg03_g_tbc_mode:1; // table mode; 0: SW control, 1: HW control ++ ushort reg03_g_fldpic_en:1; // field picture coding ++ ushort reg03_g_dct_only_en:1; // regmfe_g_dct_only_en ++ ushort reg03_g_mstar_tile:1; ++ ushort reg03_g_mstar_tile_field_split:1; ++ ushort reg03_g_fldpic_idx:1; ++ ushort reg03_g_fldpic_multislice_en:1; ++ ushort reg03_g_cabac_en:1; ++ ushort reg03_non_secure:1; ++ }; ++ ushort reg03; ++ }; ++ union { ++ struct { ++ ushort reg04_g_er_bs_th:16; // er_bs mode threshold ++ }; ++ ushort reg04; ++ }; ++ union { ++ struct { ++ ushort reg05_g_inter_pref:16; // inter prediction preference ++ }; ++ ushort reg05; ++ }; ++ union { ++ struct { ++ ushort reg06_g_cur_y_addr_lo:16; // current luma base address ++ }; ++ ushort reg06; ++ }; ++ union { ++ struct { ++ ushort reg07_g_cur_y_addr_hi:8; // current luma base address ++ }; ++ ushort reg07; ++ }; ++ union { ++ struct { ++ ushort reg08_g_cur_c_addr_lo:16; // current chroma base address ++ }; ++ ushort reg08; ++ }; ++ union { ++ struct { ++ ushort reg09_g_cur_c_addr_hi:8; // current chroma base address ++ }; ++ ushort reg09; ++ }; ++ union { ++ struct { ++ ushort reg0a_g_ref_y_addr0_lo:16; // reference luma base address0 ++ }; ++ ushort reg0a; ++ }; ++ union { ++ struct { ++ ushort reg0b_g_ref_y_addr0_hi:8; // reference luma base address0 ++ }; ++ ushort reg0b; ++ }; ++ union { ++ struct { ++ ushort reg0c_g_ref_y_addr1_lo:16; // reference luma base address1 ++ }; ++ ushort reg0c; ++ }; ++ union { ++ struct { ++ ushort reg0d_g_ref_y_addr1_hi:8; // reference luma base address0 ++ }; ++ ushort reg0d; ++ }; ++ union { ++ struct { ++ ushort reg0e_g_ref_c_addr0_lo:16; // reference chroma base address0 ++ }; ++ ushort reg0e; ++ }; ++ union { ++ struct { ++ ushort reg0f_g_ref_c_addr0_hi:8; // reference chroma base address0 ++ }; ++ ushort reg0f; ++ }; ++ union { ++ struct { ++ ushort reg10_g_ref_c_addr1_lo:16; // reference chroma base address1 ++ }; ++ ushort reg10; ++ }; ++ union { ++ struct { ++ ushort reg11_g_ref_c_addr1_hi:8; // reference chroma base address1 ++ }; ++ ushort reg11; ++ }; ++ union { ++ struct { ++ ushort reg12_g_rec_y_addr_lo:16; // reconstructed luma base address ++ }; ++ ushort reg12; ++ }; ++ union { ++ struct { ++ ushort reg13_g_rec_y_addr_hi:8; // reconstructed luma base address ++ }; ++ ushort reg13; ++ }; ++ union { ++ struct { ++ ushort reg14_g_rec_c_addr_lo:16; // reconstructed chroma base address ++ }; ++ ushort reg14; ++ }; ++ union { ++ struct { ++ ushort reg15_g_rec_c_addr_hi:8; // reconstructed chroma base address ++ }; ++ ushort reg15; ++ }; ++ union { ++ struct { // clock gating ++ ushort gate_cry_crc_sram:1; ++ ushort gate_qtab_dbfdc_dbqtb_sram:1; ++ ushort gate_mcy_mcc_sram:1; ++ ushort gate_res0_res1_sram:1; ++ ushort gate_ieap:1; ++ ushort gate_dct_idct:1; ++ ushort gate_dbf:1; ++ }; ++ ushort reg16; ++ }; ++ union { ++ struct { ++ ushort reg17_s_auto_rst_wait_cnt:6; // the waiting count for regen_soft_rstz and regen_fs_sw generation ++ ushort reg17_g_sram1p_wp_type:1; // "MFE 1p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" ++ ushort reg17_g_sram2p_wp_type:1; // "MFE 2p SRAM wrapper Type 'b1: Fix write-through problem 'b0: Original" ++ ushort reg17_g_clk_mfe_en:4; // NOT used now. ++ ushort reg17_g_mreq_sel:1; // "1" D1 MIU clk gating; "0" dynamic MIU clk gating ++ ushort reg17_g_mreq_always_active:1; // "1" mreq always active; "0" make mreq active according to FSM. (let this be default) ++ ushort reg17_g_clk_miu_d2_gate:1; // b1: turn off miu clock of power-domain "dma" and sleep into d2 mode ++ ushort reg17_g_clk_mfe_d2_gate:1; // b1: turn off mfe clock of power-domain "core" and sleep into d2 mode ++ }; ++ ushort reg17; ++ }; ++ // [JPEG] ++ union { ++ struct { ++ ushort reg18_g_jpe_enc_mode:2; // JPE encode mode; 2'b00/2'b01/2'b10/2'b11: 420/422/444/gray; current version supports 422 only ++ ushort reg18_g_jpe_buffer_mode:1; // JPE buffer mode; 0/1: double buffer mode/frame buffer mode ++ ushort reg18_g_jpe_multibuf_mode:2; // JPE multi-buffer mode; 0/1/2: 2/4/8 buffers ++ ushort reg18_g_jpe_qfactor:4; // JPE q factor; 0 ~ 15: (1 ~ 16)/4 ++ // (M1)JPE fsvs generation mode; ++ // 0: pure sw ++ // 1: sw+hw ++ // 2: hw w/o auto-restart ++ // 3: hw w/i auto-restart ++ ushort reg18_g_jpe_fsvs_mode:2; // (T8)JPE fsvs generation mode; 0/1/2: pure sw/sw+hw/hw ++ ushort reg18_reserved:3; ++ ushort reg18_g_jpe_turbo_en:1; // 0: turbo mode off, 1: turbo mode enabled ++ ushort reg18_g_viu_soft_rstz:1; // viu software reset; 0/1: reset/not reset ++ }; ++ ushort reg18; ++ }; ++ // [MPEG4/H263] ++ union { ++ struct { ++ ushort reg19_g_mp4_itlc:1; // 0/1: MPEG4 progressive/interlaced mode ++ ushort reg19_g_mp4_pskip_off:1; // 0/1: MPEG4 enable/disable p skip mode ++ ushort reg19_g_mp4_acp:2; // [0]: 0/1: sw/hw acp selection; [1]: sw default value: 0/1: disable/enable acp; current version off ++ ushort reg19_g_mp4_rounding_ctrl:1; // mp4 rounding control specified as in spec ++ ushort reg19_g_er_hec:1; // 0/1: header extension code off/on ++ ushort reg19_g_er_hec_t:3; // HEC counter reset values ++ ushort reg19_g_er_h263_unit:2; // 0/1/2: unit is 1/2/4, for calculating gob_num. ++ ushort reg19_g_mp4_direct_en:1; // MPEG4 direct enable ++ ushort reg19_g_mp4_direct_mvstore:1; // [M]: enable storing of mv & skip_mb information to DRAM in P(or sometimes I) frame ++ }; ++ ushort reg19; ++ }; ++ union { ++ struct { ++ ushort reg1a_g_mp4_direct_pref:8; // used in mp4 only, mp4 direct mode preference value ++ ushort reg1a_g_mp4_direct_trb:3; // used in mp4 only, mp4 direct mode trb (P0-B distance) ++ ushort reg1a_g_mp4_direct_trd:3; // used in mp4 only, mp4 direct mode trd (P0-P1 distance) ++ }; ++ ushort reg1a; ++ }; ++ union { ++ struct { ++ ushort reg1b_g_mp4_flddct_diff_thr:8; // used in mp4 only, mp4 field dct difference threshold ++ ushort reg1b_g_mp4_flddct_en:1; // used in mp4 only, mp4 field dct enable ++ }; ++ ushort reg1b; ++ }; ++ // [IRQ & important IP status checkings] ++ union { ++ struct { ++ ushort reg1c_g_irq_mask:8; // 0/1: irq not-mask/mask ++ ushort reg1c_g_irq_force:8; // 0/1: set corresponding interrupt as usual/force corresponding interrupt ++ }; ++ ushort reg1c; ++ }; ++ union { ++ struct { ++ ushort reg1d_g_irq_clr0:1; // 0/1: not clear interrupt/clear interrupt 0 ++ ushort reg1d_g_irq_clr1:1; // 0/1: not clear interrupt/clear interrupt 1 ++ ushort reg1d_g_irq_clr2:1; // 0/1: not clear interrupt/clear interrupt 2 ++ ushort reg1d_g_irq_clr3:1; // 0/1: not clear interrupt/clear interrupt 3 ++ ushort reg1d_g_irq_clr4:1; // 0/1: not clear interrupt/clear interrupt 4 ++ ushort reg1d_g_irq_clr5:1; // 0/1: not clear interrupt/clear interrupt 5 ++ ushort reg1d_g_irq_clr6:1; // 0/1: not clear interrupt/clear interrupt 6 ++ ushort reg1d_g_irq_clr7:1; // 0/1: not clear interrupt/clear interrupt 7 ++ ushort reg1d_g_swrst_safe:1; // to indicate there're no miu activities that need to pay attention to ++ }; ++ ushort reg1d; ++ }; ++ union { ++ struct { ++ // status of interrupt on CPU side ++ // ({1'b0,net_trigger,fs_fail_irq, txip_time_out,early_bspobuf_full_irq/buf1_full,img_buf_full_irq,marb_bspobuf_ful/buf0_full,frame_done_irq}) ++ // [3] SW mode: early obuf full; HW mode: buf1 full ++ // [1] SW mode: buf full; HW mode: buf0 full ++ ushort reg1e_g_irq_cpu:8; ++ // status of interrupt on IP side ++ // ({1'b0,net_trigger,fs_fail_irq, txip_time_out,early_bspobuf_full_irq/buf1_full,img_buf_full_irq,marb_bspobuf_ful/buf0_full,frame_done_irq}) ++ // [3] SW mode: early obuf full; HW mode: buf1 full ++ // [1] SW mode: buf full; HW mode: buf0 full ++ ushort reg1e_g_irq_ip:8; ++ }; ++ ushort reg1e; ++ }; ++ union { ++ struct { ++ ushort reserved_reg1f; ++ }; ++ ushort reg1f; ++ }; ++ // [ME setting] ++ union { ++ struct { ++ ushort reg20_s_me_4x4_disable:1; // 4x4_disable ++ ushort reg20_s_me_8x4_disable:1; // 8x4_disable ++ ushort reg20_s_me_4x8_disable:1; // 4x8_disable ++ ushort reg20_s_me_16x8_disable:1; // 16x8_disable ++ ushort reg20_s_me_8x16_disable:1; // 8x16_disable ++ ushort reg20_s_me_8x8_disable:1; // 8x8_disable ++ ushort reg20_s_me_16x16_disable:1; // 16x16_disable ++ ushort reg20_s_mesr_adapt:1; // me search range auto-adaptive; 0/1: off/on ++ ushort reg20_s_me_ref_en_mode:2; // ref enable mode: 2'b01/2'b10/2'b11: ref0 enable/ref1 enable/ref0&1 enable ++ }; ++ ushort reg20; ++ }; ++ // [IME PIPELINE] ++ union { ++ struct { ++ ushort reg21_s_ime_sr16:1; // search range limited to (h,v) = (+/-16, +/-16); 0/1: search range 32/16 ++ ushort reg21_s_ime_umv_disable:1; // 0/1: UMV enable/disable ++ ushort reg21_s_ime_ime_wait_fme:1; // 0/1: ime wait fme/fme wait ime ++ ushort reg21_s_ime_boundrect_en:1; // ime bounding rectangle enable (needed for level 3.0 and below) ++ ushort reg21_s_ime_h264_p8x8_ctrl_en:1; // ime h264 max p8x8 count control enable ++ ushort reg21_reserved:3; ++ ushort reg21_s_ime_h264_p8x8_max:8; // ime h264 max p8x8 count; value 0 is prohibited ++ // Max P8x8 MB count = 16 * reg21_s_ime_h264_p8x8_max ++ }; ++ ushort reg21; ++ }; ++ union { ++ struct { ++ ushort reg22_s_ime_mesr_max_addr:8; // me search range max depth ++ ushort reg22_s_ime_mesr_min_addr:8; // me search range min depth ++ }; ++ ushort reg22; ++ }; ++ union { ++ struct { ++ ushort reg23_s_ime_mvx_min:6; // me mvx min; 0/.../62 --> -32/.../30 ++ ushort reg23_reserved:2; ++ ushort reg23_s_ime_mvx_max:6; // me mvx max; 0/.../62 --> -32/.../30 ++ }; ++ ushort reg23; ++ }; ++ union { ++ struct { ++ ushort reg24_s_ime_mvy_min:6; // me mvy min; 0/.../62 --> -32/.../30 ++ ushort reg24_reserved:2; ++ ushort reg24_s_ime_mvy_max:6; // me mvy max; 0/.../62 --> -32/.../30 ++ }; ++ ushort reg24; ++ }; ++ // [FME pipeline] ++ union { ++ struct { ++ ushort reg25_s_fme_quarter_disable:1; // 0/1: Quarter fine-tune enable/disable ++ ushort reg25_s_fme_half_disable:1; // 0/1: Half fine-tune enable/disable ++ ushort reg25_reserved:1; ++ ushort reg25_s_fme_pmv_enable:1; // 0/1: disable/enable Previous Skip MV mode ++ ushort reg25_s_fme_mode_no:1; // 0: one mode. 1: two mode. ++ ushort reg25_s_fme_mode0_refno:1; // 0: one ref. for mode0 1: two ref. for mode0 ++ ushort reg25_s_fme_mode1_refno:1; // 0: one ref. for mode1 1: two ref. for mode1 ++ ushort reg25_s_fme_mode2_refno:1; // 0: one ref. for mode2 1: two ref. for mode2 ++ ushort reg25_s_fme_skip:1; // fme skip ++ ushort reg25_s_fme_pipeline_on:1; // 0/1: FME pipeline off/on ++ }; ++ ushort reg25; ++ }; ++ // MBR ++ union { ++ struct { ++ ushort reg26_s_mbr_pqp_dlimit:2; // previous qp diff limit ++ ushort reg26_s_mbr_uqp_dlimit:2; // upper qp diff limit ++ ushort reg26_s_mbr_tmb_bits:12; // target MB bits ++ }; ++ ushort reg26; ++ }; ++ union { ++ struct { ++ ushort reg27_s_mbr_frame_qstep:13; // frame level qp's qstep ++ ushort reg27_s_mbr_new_lambda:1; ++ ushort reg27_s_mbr_tbl_woc_write:1; ++ ushort reg27_s_mbr_tbl_woc_done_clr:1; ++ }; ++ ushort reg27; ++ }; ++ union { ++ struct { ++ ushort reg28_s_mbr_last_frm_avg_qp_lo:16; // last frame average qp (status register) ++ }; ++ ushort reg28; ++ }; ++ union { ++ struct { ++ ushort reg29_s_mbr_last_frm_avg_qp_hi:8; // last frame average qp (status register) ++ ushort reg29_s_mbr_qp_cidx_offset:5; // [H264] chroma qp index offset (+12). Spec range is [-12,12] ++ }; ++ ushort reg29; ++ }; ++ union { ++ struct { ++ ushort reg2a_s_mbr_qp_min:6; // qp min ++ ushort reg2a_s_mbr_qp_max:6; // qp max ++ ushort reg2a_s_mvdctl_ref0_offset:2;// H264 mvy offset adjustment for MCC if ref is frame 0: 0/1/2: 0/+2/-2 ++ ushort reg2a_s_mvdctl_ref1_offset:2;// H264 mvy offset adjustment for MCC if ref is frame 1: 0/1/2: 0/+2/-2 ++ }; ++ ushort reg2a; ++ }; ++ // IEAP ++ union { ++ struct { ++ ushort reg2b_s_ieap_last_mode:4; // software control of the last mode of Intra4x4 mode 0 ~ 8 ++ ushort reg2b_s_ieap_constraint_intra:1; // software control constraint intra; 0/1: OFF/ON ++ ushort reg2b_s_ieap_ccest_en:1; // software control cost estimator; 0/1: OFF/ON ++ ushort reg2b_s_ieap_ccest_thr:2; // threshold of cost estimator set 0 ~ 3 for threshold 1 ~ 4 ++ ushort reg2b_s_ieap_drop_i16:1; // software control stop-Intra16x16-mode; 1:w/o I16M, 0:w/i I16MB ++ ushort reg2b_s_ieap_early_termination:1; ++ }; ++ ushort reg2b; ++ }; ++ // QUAN ++ union { ++ struct { ++ ushort reg2c_s_quan_idx_last:6; // the index of the last non-zero coefficient in the zig-zag order ++ ushort reg2c_s_quan_idx_swlast:1; // software control of the index of the last non-zero coefficient in the zig-zag order; 0/1: disable/enable ++ ushort reg2c_reserved:8; ++ ushort reg2c_g_ieap_sram_4x2_swap:1; ++ }; ++ ushort reg2c; ++ }; ++ // TXIP control & debug ++ union { ++ struct { ++ ushort reg2d_s_txip_mbx:9; // txip mbx ++ ushort reg2d_s_txip_sng_mb:1; // 0/1: disable/enable txip controller stop-and-go mechanism using ++ // (txip_mbx == reg71_g_debug_trig_mbx) & (txip_mby == reg72_g_debug_trig_mby) ++ ushort reg2d_s_txip_sng_set:1; // txip controller stop-and-go mechanism using this register bit: ++ // 0/1: go/stop ++ ushort reg2d_s_txip_dbf_full_halt_en:1; // txip controller stop-and-go mechanism using double buffer fullness as criterion: ++ // 0/1: disable/enable ++ ushort reg2d_s_txip_ack2fme_mode:1; ++ }; ++ ushort reg2d; ++ }; ++ union { ++ struct { ++ ushort reg2e_s_txip_mby:9; // txip mby ++ }; ++ ushort reg2e; ++ }; ++ union { ++ struct { ++ ushort reg2f_s_txip_irfsh_mb_s0:13; // intra refresh mb start 0 ++ ushort reg2f_reserved:1; ++ ushort reg2f_s_txip_irfsh_en:2; // intra refresh enable bits: bit0: enable condition 0; bit 1: enable condition 1 ++ }; ++ ushort reg2f; ++ }; ++ union { ++ struct { ++ ushort reg30_s_txip_irfsh_mb_e0:13; // intra refresh mb end 0 ++ }; ++ ushort reg30; ++ }; ++ union { ++ struct { ++ ushort reg31_s_txip_irfsh_mb_s1:13; // intra refresh mb start 1 ++ }; ++ ushort reg31; ++ }; ++ union { ++ struct { ++ ushort reg32_s_txip_irfsh_mb_e1:13; // intra refresh mb end 1 ++ ushort reg32_reserved:1; ++ ushort reg32_s_txip_timeout_en:1; // txip time out enable ++ ushort reg32_s_txip_wait_mode:1; // txip waiting mode to move to next MB; 0/1: idle count/cycle count ++ }; ++ ushort reg32; ++ }; ++ union { ++ struct { ++ ushort reg33_s_txip_idle_cnt:16; // wait mode is 0: txip idle count (x 64T)/ wait mode is 1: txip total processing count (x 64T) ++ }; ++ ushort reg33; ++ }; ++ union { ++ struct { ++ ushort reg34_s_txip_timeout:16; // txip timeout count (x 64T) ++ }; ++ ushort reg34; ++ }; ++ // [ECDB PIPELINE] ++ // ECDB control & debug ++ union { ++ struct { ++ ushort reg35_s_ecdb_mbx:13; // ecdb mbx ++ }; ++ ushort reg35; ++ }; ++ union { ++ struct { ++ ushort reg36_s_ecdb_mby:13; // ecdb mby ++ }; ++ ushort reg36; ++ }; ++ // MDC ++ union { ++ struct { ++ ushort reg37_s_mdc_total_mb_bw:4; // total mb bit width used in video_pkt ++ ushort reg37_s_mdc_m4vpktpzero:1; // MPEG4 video packet preceding zeros: 0/1: 16/17 zeros ++ ushort reg37_s_mdc_m4timev:2; // MPEG4 modulo time base: 0/1/2/3: 0/10/110/1110 ++ ushort reg37_s_mdc_m4iadcvlc_th:3; // MPEG4 intra dc vlc threshold ++ ushort reg37_s_mdc_m4vop_tinc_bw:4; // vop_time_increment bit width ++ }; ++ ushort reg37; ++ }; ++ union { ++ struct { ++ ushort reg38_s_mdc_m4vop_tinc:15; // vop_time_increment ++ }; ++ ushort reg38; ++ }; ++ union { ++ struct { ++ ushort reg39_s_mdc_gob_frame_id:2; // H263 gob frame id ++ ushort reg39_s_mdc_h264_nal_ref_idc:2; // nal_ref_idc ++ ushort reg39_s_mdc_h264_nal_unit_type:1; // 0/1: 1/5 ++ ushort reg39_s_mdc_h264_fnum_bits:2; // H264 frame num bits ++ ushort reg39_s_mdc_h264_dbf_control:1; // dbf control present flag ++ ushort reg39_s_mdc_h264_fnum_value:8; // H264 frame num value ++ }; ++ ushort reg39; ++ }; ++ union { ++ struct { ++ ushort reg3a_s_mdc_h264_idr_pic_id:3; ++ ushort reg3a_s_mdc_h264_disable_dbf_idc:2; ++ ushort reg3a_s_mdc_h264_alpha:4; // slice_alpha_c0_offset_div2 ++ ushort reg3a_s_mdc_h264_beta:4; // slice_beta_offset_div2 ++ ushort reg3a_s_mdc_h264_ridx_aor_flag:1; // reference index active override flag ++ ushort reg3a_miu_sel:2; ++ }; ++ ushort reg3a; ++ }; ++ // BSPOBUF/MVOBUF ++ union { ++ struct { ++ ushort reg3b_s_bspobuf_set_adr:1; // set bsp obuf start address(write one clear) ++ ushort reg3b_s_mvobuf_set_adr:1; // set mv obuf start address (write one clear) ++ ushort reg3b_s_bspobuf_fifo_th:3; // bsp obuf threshold ++ ushort reg3b_s_mvobuf_fifo_th:3; // mv obuf threshold ++ ushort reg3b_s_bsp_fdc_skip:1; // fdc skip enable; 0: fdc skip disable, 1: fdc skip enable ++ ushort reg3b_reserved:5; ++ ushort reg3b_s_obuf_toggle_obuf0_status:1; // toggle buf0 status(write one clear) ++ ushort reg3b_s_obuf_toggle_obuf1_status:1; // toggle buf1 status(write one clear) ++ }; ++ ushort reg3b; ++ }; ++ union { ++ struct { ++ ushort reg3c_s_bspobuf_lo:16; // bsp obuf start address ++ }; ++ ushort reg3c; ++ }; ++ union { ++ struct { ++ ushort reg3d_s_bspobuf_hi:13; // bsp obuf address high ++ ushort reg3d_reserved:1; ++ ushort reg3d_s_obuf_id:2; // 00: s0, 01: e0, 10: s1, 11: e1 ++ }; ++ ushort reg3d; ++ }; ++ union { ++ struct { ++ ushort reg3e_s_obuf_write_id_adr:1; // write to this address to enable writing of bspobuf address ++ }; ++ ushort reg3e; ++ }; ++ union { ++ struct { ++ ushort reg3f_s_bspobuf_hw_en:1; // enable HW obuf automatic mechanism ++ ushort reg3f_s_bspobuf_update_adr:1; // update obuf address(write one clear) ++ ushort reg3f_s_bspobuf_adr_rchk_sel:2; // obuf adr read back check selection: 0/1/2/3: s0/e0/s1/e1 ++ ushort reg3f_s_bspobuf_adr_rchk_en:1; // enable bspobuf adr read back check through regmfe_s_bspobuf_wptr ++ ushort reg3f_reserved:3; ++ ushort reg3f_s_bsp_fdc_offset:7; // bsp's fdc offset ++ }; ++ ushort reg3f; ++ }; ++ union { ++ struct { ++ ushort reg40_s_mvobuf_saddr_lo:16; // mv obuf start address ++ }; ++ ushort reg40; ++ }; ++ union { ++ struct { ++ ushort reg41_s_mvobuf_saddr_hi:13; // mv obuf start address ++ }; ++ ushort reg41; ++ }; ++ union { ++ struct { ++ ushort reg42_s_bsp_bit_cnt_lo:16; // encoded bit count (one frame) ++ }; ++ ushort reg42; ++ }; ++ union { ++ struct { ++ ushort reg43_s_bsp_bit_cnt_hi:8; // encoded bit count (one frame) ++ }; ++ ushort reg43; ++ }; ++ union { ++ struct { ++ ushort reg44_s_bspobuf_wptr_lo:16; // bspobuf write pointer (8 byte unit) ++ }; ++ ushort reg44; ++ }; ++ union { ++ struct { ++ ushort reg45_s_bspobuf_wptr_hi:13; // bspobuf write pointer (8 byte unit) ++ }; ++ ushort reg45; ++ }; ++ // FDC ++ union { ++ struct { ++ ushort reg46_s_fdc_bs:16; // cpu to fdc bitstream data ++ }; ++ ushort reg46; ++ }; ++ union { ++ struct { ++ ushort reg47_s_fdc_bs_len:5; // cpu to fdc bitstream len; 0 ~ 16 ++ ushort reg47_s_fdc_bs_count:10; // cpu to fdc round count ++ }; ++ ushort reg47; ++ }; ++ // [Table Control] ++ union { ++ struct { ++ ushort reg48_s_fdc_ack:1; // fdc to cpu ack; 0/1: frame data pool not empty/frame data pool empty; 48x64 bits of space ++ ushort reg48_s_fdc_done_clr:1; // fdc done clear (write one clear) ++ ushort reg48_s_fdc_done:1; // fdc done; indicate to CPU that data has been written to internal buffer ++ ushort reg48_reserved:8; ++ ushort reg48_s_fdc_bs_vld:1; // set for bitstream write out (write one clear) ++ ushort reg48_s_tbc_en:1; // set for table read & write ; 1: enable, 0: disable (write one clear) ++ }; ++ ushort reg48; ++ }; ++ union { ++ struct { ++ ushort reg49_s_tbc_rw:1; // table mode; 0: read, 1: write ++ ushort reg49_s_tbc_done_clr:1; // table done clear (write one clear) ++ ushort reg49_s_tbc_done:1; // table done; indicate to CPU that (1) data has been written to table (2) table output is ready at reg4b_s_tbc_rdata ++ ushort reg49_reserved:5; ++ ushort reg49_s_tbc_adr:6; // table address ++ }; ++ ushort reg49; ++ }; ++ union { ++ struct { ++ ushort reg4a_s_tbc_wdata:16; // table write data ++ }; ++ ushort reg4a; ++ }; ++ union { ++ struct { ++ ushort reg4b_s_tbc_rdata:16; // table read data ++ }; ++ ushort reg4b; ++ }; ++ // [Get Neighbor] ++ union { ++ struct { ++ ushort reg4c_s_gn_saddr_lo:16; // gn base adr low ++ }; ++ ushort reg4c; ++ }; ++ union { ++ struct { ++ ushort reg4d_s_gn_saddr_hi:13; // gn base adr high ++ ushort reg4d_reserved:2; ++ ushort reg4d_s_gn_saddr_mode:1; // 1: gn save data in one frame 0: gn save data in one row ++ }; ++ ushort reg4d; ++ }; ++ union { ++ struct { ++ ushort reg4e_s_gn_mvibuf_saddr_lo:16; // mv ibuf start address low ++ }; ++ ushort reg4e; ++ }; ++ union { ++ struct { ++ ushort reg4f_s_gn_mvibuf_saddr_hi:13; // mv ibuf start address high ++ ushort reg4f_reserved:1; ++ ushort reg4f_s_gn_bwr_mode:2; ++ }; ++ ushort reg4f; ++ }; ++ union { ++ struct { ++ ushort reg56_s_marb_mrpriority_sw:2; // mfe2mi_rpriority software programmable ++ ushort reg56_s_marb_mr_timeout_ref:1; // miu read burst timeout count start point ++ ushort reg56_s_marb_mr_nwait_mw:1; // miu read not wait mi2mfe_wrdy ++ ushort reg56_s_marb_mwpriority_sw:2; // mfe2mi_wpriority software programmable ++ ushort reg56_s_marb_mw_timeout_ref:1; // miu write burst timeout count start point ++ ushort reg56_s_marb_mw_nwait_mr:1; // miu read not wait mi2mfe_wrdy ++ ushort reg56_s_marb_mr_pending:4; // max. pending read requests to miu ++ ushort reg56_s_marb_32b_ad_nswap:1; // 32bits miu address not swap. only for 32bits mode ++ ushort reg56_s_marb_miu_wmode:1; // 0/1: original miu protocol/new miu protocol(wd_en) ++ ushort reg56_s_marb_rp_ordering:1; ++ }; ++ ushort reg56; ++ }; ++ union { ++ struct { ++ ushort reg58_s_marb_ubound_0_lo:16; // MIU protect for MPEG4 BSP obuf ++ }; ++ ushort reg58; ++ }; ++ union { ++ struct { ++ ushort reg59_s_marb_ubound_0_hi:13; // MIU protect for MPEG4 BSP obuf ++ ushort reg59_reserved:3; ++ }; ++ ushort reg59; ++ }; ++ union { ++ struct { ++ ushort reg5a_s_marb_lbound_0_lo:16; // MIU protect for MPEG4 BSP obuf ++ }; ++ ushort reg5a; ++ }; ++ union { ++ struct { ++ ushort reg5b_s_marb_lbound_0_hi:13; // MIU protect for MPEG4 BSP obuf ++ ushort reg5b_s_marb_miu_bound_en_0:1; ++ }; ++ ushort reg5b; ++ }; ++ union { ++ struct { ++ ushort reg5c_s_marb_ubound_1_lo:16; // MIU Upper bound protect for MPEG4 MC obuf rec ++ }; ++ ushort reg5c; ++ }; ++ union { ++ struct { ++ ushort reg5d_s_marb_ubound_1_hi:13; // MIU Upper bound protect for MPEG4 MC obuf rec ++ }; ++ ushort reg5d; ++ }; ++ union { ++ struct { ++ ushort reg5e_s_marb_lbound_1_lo:16; // MIU Lower bound protect for MPEG4 MC obuf ++ }; ++ ushort reg5e; ++ }; ++ union { ++ struct { ++ ushort reg5f_s_marb_lbound_1_hi:13; // MIU Lower bound protect for MPEG4 MC obuf ++ ushort reg5f_s_marb_miu_bound_en_1:1; //miu write protection, miu bound enable for write port 1 ++ }; ++ ushort reg5f; ++ }; ++ union { ++ struct { ++ ushort reg60_s_marb_ubound_2_lo:16; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg60; ++ }; ++ union { ++ struct { ++ ushort reg61_s_marb_ubound_2_hi:13; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg61; ++ }; ++ union { ++ struct { ++ ushort reg62_s_marb_lbound_2_lo:16; // MIU protect for MPEG4 MV obuf ++ }; ++ ushort reg62; ++ }; ++ union { ++ struct { ++ ushort reg63_s_marb_lbound_2_hi:13; // MIU protect for MPEG4 MV obuf ++ ushort reg63_s_marb_miu_bound_en_2:1; // miu write protection, miu bound enable for write port 2 ++ }; ++ ushort reg63; ++ }; ++ union { ++ struct { ++ ushort reg64_s_marb_ubound_3_lo:16; // MIU protect for MPEG4 GN ++ }; ++ ushort reg64; ++ }; ++ union { ++ struct { ++ ushort reg65_s_marb_ubound_3_hi:13; // MIU protect for MPEG4 GN ++ }; ++ ushort reg65; ++ }; ++ union { ++ struct { ++ ushort reg66_s_marb_lbound_3_lo:16; // MIU protect for MPEG4 GN ++ }; ++ ushort reg66; ++ }; ++ union { ++ struct { ++ ushort reg67_s_marb_lbound_3_hi:13; // MIU protect for MPEG4 GN ++ ushort reg67_s_marb_miu_bound_en_3:1; ++ ushort reg67_s_marb_miu_off:1; ++ ushort reg67_s_marb_miu_bound_err:1; ++ }; ++ ushort reg67; ++ }; ++ union { ++ struct { ++ ushort reg68_s_marb_eimi_block:1; // miu emi/imi block, 0: disable ++ ushort reg68_s_marb_lbwd_mode:1; // low bandwidth mode, 0: disable ++ ushort reg68_s_marb_imi_burst_thd:5;// imi write burst bunch up threshold ++ ushort reg68_s_marb_imi_timeout:3; // imi write burst timeout ++ ushort reg68_s_marb_imilast_thd:4; // auto mfe2imi_last threshold ++ ushort reg68_s_prfh_cryc_en:1; // 0: disable prfh_cryc circuit, 1: enable prfh_cryc circuit ++ ushort reg68_s_prfh_refy_en:1; // 0: disable prfh_refy circuit, 1: enable prfh_refy circuit ++ }; ++ ushort reg68; ++ }; ++ union { ++ struct { ++ ushort reg69_g_pat_gen_init:16; // pattern generation initial value ++ }; ++ ushort reg69; ++ }; ++ union { ++ struct { ++ ushort reg6a_s_bspobuf_idx:2; // HW obuf index(0->1->2->3->0->1¡K) ++ // SW obuf index(00->01->11->10->00...) ++ ushort reg6a_s_obuf0_status:1; ++ ushort reg6a_s_obuf1_status:1; ++ // regmfe_s_bspobuf_adr_status:6 ++ // {reg6a_fifo_not_full, reg6a_fifo_not_empty, reg6a_enable_obufadr_update, reg6a_obufadr_update_cnt[2:0]} ++ ushort reg6a_obufadr_update_cnt:3; ++ ushort reg6a_enable_obufadr_update:1; ++ ushort reg6a_fifo_not_empty:1; ++ ushort reg6a_fifo_not_full:1; ++ }; ++ ushort reg6a; ++ }; ++ union { ++ struct { ++ ushort reg6b_s_marb_imi_saddr_lo:16; // imi base address for low bandwidth mode (in 8-byte unit) ++ }; ++ ushort reg6b; ++ }; ++ union { ++ struct { ++ ushort reg6c_s_marb_imi_saddr_hi:13; ++ ushort reg6c_s_marb_rimi_force:1; // b1:force all read path to IMI 'b0:Normal ++ ushort reg6c_s_marb_imi_cache_size:2; // imi cache size (0: 64kB, 1:32kB, 2:16kB, 3:8kB) ++ }; ++ ushort reg6c; ++ }; ++ union { ++ struct { ++ ushort reg6d_s_marb_imipriority_thd:4; // hardware mfe2imi_priority threshold ++ ushort reg6d_s_marb_imipriority_sw:2; // mfe2imi_priority software programmable ++ ushort reg6d_reserved:2; ++ ushort reg6d_s_prfh_cryc_idle_cnt:4; // prfh idle count (x 16T) for prfh_cryc ++ ushort reg6d_s_prfh_refy_idle_cnt:4; // prfh idle count (x 16T) for prfh_refy ++ }; ++ ushort reg6d; ++ }; ++ union { ++ struct { ++ ushort reg6e_s_mbr_qstep_min:7; // qstep min (note: max value of qstep_min is 128 because condition is qstep <= qstep_min) ++ }; ++ ushort reg6e; ++ }; ++ union { ++ struct { ++ ushort reg6f_s_mbr_qstep_max:13; // qstep max ++ }; ++ ushort reg6f; ++ }; ++ union { ++ struct { ++ ushort reg70_g_debug_mode:7; // debug mode ++ ushort reg70_g_debug_trig_cycle:9; // wait (8 * reg70_g_debug_trig_cycle) cycles ++ }; ++ ushort reg70; ++ }; ++ union { ++ struct { ++ ushort reg71_g_debug_trig_mbx:13; // debug trigger mbx ++ }; ++ ushort reg71; ++ }; ++ union { ++ struct { ++ ushort reg72_g_debug_trig_mby:13; // debug trigger mby ++ }; ++ ushort reg72; ++ }; ++ union { ++ struct { ++ ushort reg73_g_debug_trig:1; // reg trigger (write one clear) ++ ushort reg73_g_debug_trig_mode:2; // debug trigger mode; 0/1/2/3: reg_trigger/3rd stage (mbx, mby)/frame start ++ ushort reg73_g_debug_en:1; // debug enable ++ ushort reg73_g_crc_mode:4; // 'h0: Disable,¡¥hc: bsp obuf, 'hd: mc obuf, 'hd: mc obuf ++ ushort reg73_g_debug_tcycle_chk_en:1; // enable total cycle check ++ ushort reg73_g_debug_tcycle_chk_sel:1; // select total cycle and report it on regmfe_g_crc_result[15:0] ++ ushort reg73_g_sw_buffer_mode:1; // 0/1: hw/sw buffer mode ++ ushort reg73_g_sw_row_done:1; // sw row done (1T clk_jpe) (write one clear) ++ ushort reg73_g_sw_vs:1; // sw vsync (1T clk_jpe) (write one clear) ++ ushort reg73_g_pat_gen_en:1; // enable pattern generation ++ ushort reg73_g_row_down_irq_en:1; // row done irq enable; 0: disable, 1: enable ++ ushort reg73_g_vs_irq_en:1; // vs irq enable; 0: disable, 1: enable ++ }; ++ ushort reg73; ++ }; ++ union { ++ struct { ++ ushort reg74_g_debug_state0:16; // "debug state for TXIP/ECDB submodule {txip2q_en, txip2iq_en, txip2mbr_en, txip2zmem_en, txip2dpcm_en, ++ // txip2mve_en, txip2mcobuf_en, txip2mbldr_en, ecdb2mdc_en, ++ // ecdb2rlc_en, ecdb2vlc_en, 5'd0}" ++ }; ++ ushort reg74; ++ }; ++ union { ++ struct { ++ ushort reg75_g_debug_state1; // "debug state for ME submodule {3'd0, load_w4_ok, load_w3_ok, load_w2_ok, load_w1_ok, load_w0_ok, 2'd0, ++ // busy_ime, busy_fme, busy_mesr, busy_iacost, end_this_mb, init_this_mb" ++ }; ++ ushort reg75; ++ }; ++ union { ++ struct { ++ ushort reg76_g_crc_result0:16; // CRC64[15..0] ++ }; ++ ushort reg76; ++ }; ++ union { ++ struct { ++ ushort reg77_g_crc_result1:16; // CRC64[31..16] ++ }; ++ ushort reg77; ++ }; ++ union { ++ struct { ++ ushort reg78_g_crc_result2:16; // CRC64[47..32] ++ }; ++ ushort reg78; ++ }; ++ union { ++ struct { ++ ushort reg79_g_crc_result3:16; // CRC64[63..48] ++ }; ++ ushort reg79; ++ }; ++ union { ++ struct { ++ ushort reg7a_g_bist_fail0; ++ }; ++ ushort reg7a; ++ }; ++ union { ++ struct { ++ ushort reg7b_g_bist_fail1; ++ }; ++ ushort reg7b; ++ }; ++ union { ++ struct { ++ ushort reg7c_g_bist_fail2; ++ }; ++ ushort reg7c; ++ }; ++ union { ++ struct { ++ ushort reg7d_s_txip_eco0:1; // 0: original, 1: fix mbldr_cry_done, mbldr_crc_done bug ++ ushort reg7d_s_txip_eco1:1; // reserved registers ++ ushort reg7d_eco_mreq_stallgo:1; // reg7d_eco_mreq_stallgo ++ ushort reg7d_eco_marb_stallgo:1; // reg7d_eco_marb_stallgo ++ ushort reg7d_reserved1:1; ++ ushort reg7d_eco_bsp_stuffing:1; ++ ushort reg7d_eco_bsp_rdy_fix:1; ++ ushort reg7d_eco_bsp_multi_slice_fix:1; ++ ushort reg7d_reserved2:6; ++ ushort reg7d_g_secure_obufadr:1; ++ ushort reg7d_g_secure_miu_sel:1; ++ }; ++ ushort reg7d; ++ }; ++ union { ++ struct { ++ ushort reg80_s_pp_en:1; ++ ushort reg80_s_pp_mw_burst_thd:5; ++ ushort reg80_s_pp_mw_timeout:3; ++ ushort reg80_s_pp_mw_timeout_ref:1; ++ ushort reg80_s_pp_burst_split:2; ++ ushort reg80_s_pp_32b_ad_nswap:1; ++ }; ++ ushort reg80; ++ }; ++ union { ++ struct { ++ ushort reg86_g_zmvmap_base_lo:16; ++ }; ++ ushort reg86; ++ }; ++ union { ++ struct { ++ ushort reg87_g_zmvmap_base_hi:8; ++ ushort reg87_g_intra4_penalty:8; ++ }; ++ ushort reg87; ++ }; ++ union { ++ struct { ++ ushort reg88_g_intra16_penalty:8; ++ ushort reg88_g_inter_penalty:8; ++ }; ++ ushort reg88; ++ }; ++ union { ++ struct { ++ ushort reg89_g_planar_penalty_luma:8; ++ ushort reg89_g_planar_penalty_cbcr:8; ++ }; ++ ushort reg89; ++ }; ++ union { ++ struct { ++ ushort reg8b_g_mb_pitch:12; ++ ushort reg8b_g_mb_pitch_en:1; ++ }; ++ ushort reg8b; ++ }; ++ union { ++ struct { ++ ushort reg90_g_capture_width_y:13; ++ }; ++ ushort reg90; ++ }; ++ union { ++ struct { ++ ushort reg91_g_capture_width_c:13; ++ }; ++ ushort reg91; ++ }; ++ union { ++ struct { ++ ushort regd2_g_jpd_hsk_en:1; ++ ushort regd2_s_packed422_en:1; ++ ushort regd2_s_packed422_endian:1; ++ ushort regd2_s_packed422_yc_swap:1; ++ ushort regd2_s_packed422_uv_swap:1; ++ ushort regd2_s_packed422_delta:8; ++ ushort regd2_g_jpd_hsk_shot:1; ++ ushort regd2_g_jpd_hsk_mfe:1; ++ ushort regd2_g_jpd_frame_done_mask:1; ++ }; ++ ushort regd2; ++ }; ++ union { ++ struct { ++ ushort regd6_g_yuvldr_en:1; ++ ushort regd6_g_hevd_tile:1; ++ ushort regd6_g_hevd_tile32:1; ++ ushort regd6_g_yuv420_semi:1; ++ ushort regd6_g_yuv420_semi_uv_swap:1; ++ }; ++ ushort regd6; ++ }; ++ union { ++ struct { ++ ushort regdb_s_sambc_td1k_rbw_max:8; ++ ushort regdb_s_sambc_td1k_rbw_min:8; ++ }; ++ ushort regdb; ++ }; ++ union { ++ struct { ++ ushort regdc_s_sambc_td8k_rbw_max:8; ++ ushort regdc_s_sambc_td8k_rbw_min:8; ++ }; ++ ushort regdc; ++ }; ++ union { ++ struct { ++ ushort regdd_s_sambc_td64k_rbw_max:8; ++ ushort regdd_s_sambc_td64k_rbw_min:8; ++ }; ++ ushort regdd; ++ }; ++ union { ++ struct { ++ ushort regde_s_sambc_td1k_wbw_max:8; ++ ushort regde_s_sambc_td1k_wbw_min:8; ++ }; ++ ushort regde; ++ }; ++ union { ++ struct { ++ ushort regdf_s_sambc_td8k_wbw_max:8; ++ ushort regdf_s_sambc_td8k_wbw_min:8; ++ }; ++ ushort regdf; ++ }; ++ union { ++ struct { ++ ushort rege0_s_sambc_td64k_wbw_max:8; ++ ushort rege0_s_sambc_td64k_wbw_min:8; ++ }; ++ ushort rege0; ++ }; ++ union { ++ struct { ++ ushort rege1_s_sambc_mask_en:4; ++ ushort rege1_s_sambc_slowdown_mode:4; ++ ushort rege1_s_sambc_bypass:8; ++ }; ++ ushort rege1; ++ }; ++ union { ++ struct { ++ ushort regf2_g_roi_en:1; ++ ushort regf2_g_roi_range_sw_limit:1; ++ ushort regf2_g_zeromv_en:1; ++ ushort regf2_g_i16pln_en:1; ++ }; ++ ushort regf2; ++ }; ++ union { ++ struct { ++ ushort regf3_s_plnrldr_format:1; ++ #define MFE_REG_PLNRLDR_420 0 ++ #define MFE_REG_PLNRLDR_422 1 ++ ushort regf3_s_plnrldr_rlast_thd:4; ++ ushort regf3_s_plnrldr_mrpriority_sw:2; ++ ushort regf3_s_plnrldr_mrpriority_thd:7; ++ ushort regf3_s_plnrldr_mrpriority_type:1; ++ ushort regf3_s_plnrldr_c_swap:1; ++ #define MFE_REG_PLNRLDR_UV 0 ++ #define MFE_REG_PLNRLDR_VU 1 ++ }; ++ ushort regf3; ++ }; ++ union { ++ struct { ++ ushort regf4_s_plnrldr_en:1; ++ }; ++ ushort regf4; ++ }; ++ union { ++ struct { ++ ushort regf5_s_mbr_last_frm_avg_qp_lo:16; ++ }; ++ ushort regf5; ++ }; ++ union { ++ struct { ++ ushort regf6_s_mbr_last_frm_avg_qp_hi:16; ++ }; ++ ushort regf6; ++ }; ++ union { ++ struct { ++ ushort regf7_s_mdc_h264_poc:16; ++ }; ++ ushort regf7; ++ }; ++ union { ++ struct { ++ ushort regf8_s_mdc_h264_poc_enable:1; ++ ushort regf8_s_mdc_h264_poc_width:5; ++ }; ++ ushort regf8; ++ }; ++ union { ++ struct { ++ ushort regfb_g_roi_qmap_adr_lo:16; ++ }; ++ ushort regfb; ++ }; ++ union { ++ struct { ++ ushort regfc_g_roi_qmap_adr_hi:8; ++ }; ++ ushort regfc; ++ }; ++ union { ++ struct { ++ ushort regfd_reserved0:6; ++ ushort regfd_eco:1; ++ }; ++ ushort regfd; ++ }; ++} mfe6_reg; ++ ++#endif//_MFE6_REG_H_ +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_rqc.c b/drivers/mstar/mfev5/mfe6/mfe6_rqc.c +new file mode 100644 +index 00000000..364c1a6e +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_rqc.c +@@ -0,0 +1,529 @@ ++#include ++ ++#define MRQC_NAME "MRQC" ++#define MRQC_VER_MJR 0 ++#define MRQC_VER_MNR 0 ++#define MRQC_VER_EXT 1 ++ ++void* msb2_allocate(void); ++char* msb2_describe(void); ++ ++static void* mrqc_allocate(void); ++static char* mrqc_describe(void); ++ ++#define MRQC_FACTORIES_NR 8 ++ ++static struct mrqc_factory ++{ ++ void* (*rqc_alloc)(void); ++ char* (*rqc_descr)(void); ++} factories[MRQC_FACTORIES_NR] = ++{ ++ {mrqc_allocate,mrqc_describe}, ++ {msb2_allocate,msb2_describe}, ++ {NULL,NULL}, ++}; ++ ++int rqctmfe_insert(void* (*allc)(void), char*(*desc)(void)) ++{ ++ if (factories[0].rqc_alloc != mrqc_allocate) ++ return -1; ++ factories[0].rqc_alloc = allc; ++ factories[0].rqc_descr = desc; ++ return 0; ++} ++EXPORT_SYMBOL(rqctmfe_insert); ++ ++int rqctmfe_remove(void) ++{ ++ if (factories[0].rqc_alloc == mrqc_allocate) ++ return -1; ++ factories[0].rqc_alloc = mrqc_allocate; ++ factories[0].rqc_descr = mrqc_describe; ++ return 0; ++} ++EXPORT_SYMBOL(rqctmfe_remove); ++ ++void* rqctmfe_acquire(int idx) ++{ ++ if ((unsigned)idx < MRQC_FACTORIES_NR && factories[idx].rqc_alloc) ++ return (factories[idx].rqc_alloc)(); ++ return (factories[0].rqc_alloc)(); ++} ++ ++char* rqctmfe_comment(int idx) ++{ ++ if ((unsigned)idx < MRQC_FACTORIES_NR && factories[idx].rqc_alloc) ++ return (factories[idx].rqc_descr)(); ++ return NULL; ++} ++ ++/* default rate controller */ ++ ++static void _mrqcfree(rqct_ops* rqct) {MEM_FREE(rqct);} ++static int _seq_sync(rqct_ops* rqct); ++static int _seq_done(rqct_ops* rqct); ++static int _seq_conf(rqct_ops* rqct); ++static int _enc_conf(rqct_ops* rqct, mhve_job* mjob); ++static int _enc_done(rqct_ops* rqct, mhve_job* mjob); ++ ++static void* mrqc_allocate(void) ++{ ++ rqct_ops* rqct = NULL; ++ mfe6_rqc* rqcx; ++ ++ if (!(rqct = MEM_ALLC(sizeof(mfe6_rqc)))) ++ return NULL; ++ ++ MEM_COPY(rqct->name, "mrct", 5); ++ rqct->release = _mrqcfree; ++ rqct->seq_sync = _seq_sync; ++ rqct->seq_done = _seq_done; ++ rqct->seq_conf = _seq_conf; ++ rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = _enc_conf; ++ rqct->enc_done = _enc_done; ++ rqcx = (mfe6_rqc*)rqct; ++ rqcx->attr.i_method = RQCT_MODE_CQP; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->attr.i_iperiod= 0; ++ rqcx->attr.i_ltrperiod= 0; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = QP_IFRAME_DELTA; ++ rqcx->attr.i_btrate = 0; ++ rqcx->attr.i_iupperq = QP_MAX; ++ rqcx->attr.i_ilowerq = QP_MIN; ++ rqcx->attr.i_pupperq = QP_MAX; ++ rqcx->attr.i_plowerq = QP_MIN; ++ /* initiate penalties */ ++ rqcx->attr.b_i16pln = 1; ++ rqcx->attr.i_peni4x = 0; ++ rqcx->attr.i_peni16 = 0; ++ rqcx->attr.i_penint = 0; ++ rqcx->attr.i_penYpl = 0; ++ rqcx->attr.i_penCpl = 0; ++ rqcx->i_config = 0; ++ rqcx->i_ipcount = 0; ++ rqcx->i_iperiod = 0; ++ rqcx->i_ltrpcount = 0; ++ rqcx->i_ltrperiod = 0; ++ ++ return rqcx; ++} ++ ++static char* mrqc_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d.%02d:fixed qp only.",MRQC_NAME,MRQC_VER_MJR,MRQC_VER_MNR,MRQC_VER_EXT); ++ return line; ++} ++ ++static int _seq_conf(rqct_ops* rqct) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ rqcx->i_iperiod = rqcx->attr.i_iperiod; ++ rqcx->i_ltrperiod = rqcx->attr.i_ltrperiod; ++ ++ if (rqcx->attr.i_leadqp < 8 || rqcx->attr.i_leadqp > 48) ++ rqcx->attr.i_leadqp = 36; ++ rqcx->i_ipcount = rqcx->i_iperiod; ++ rqcx->i_ltrpcount = rqcx->i_ltrperiod; ++ return 0; ++} ++ ++static int _seq_sync(rqct_ops* rqct) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ /* recount frame */ ++ rqcx->i_ipcount = 0; ++ rqcx->i_ltrpcount = 0; ++ return 0; ++} ++ ++static int _seq_done(rqct_ops* rqct) ++{ ++ return 0; ++} ++ ++static int _enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ mfe6_reg* regs = (mfe6_reg*)mjob; ++ rqct->i_enc_qp = rqcx->attr.i_leadqp; ++ if (rqct->i_pictyp == RQCT_PICTYP_I) ++ rqct->i_enc_qp = rqcx->attr.i_leadqp - rqcx->attr.i_deltaq; ++ mrqc_roi_draw(rqct, mjob); ++#define UP_DQP 3 ++#define LF_DQP 3 ++ regs->reg00_g_mbr_en = 0; ++ regs->reg26_s_mbr_pqp_dlimit = UP_DQP; ++ regs->reg26_s_mbr_uqp_dlimit = LF_DQP; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = 0; ++ regs->reg26_s_mbr_tmb_bits = 0; ++ regs->reg2a_s_mbr_qp_min = 0; ++ regs->reg2a_s_mbr_qp_max = 0; ++ regs->reg6e_s_mbr_qstep_min = 0; ++ regs->reg6f_s_mbr_qstep_max = 0; ++ /* penalties of mbtypies */ ++ regs->regf2_g_i16pln_en = (0!=rqcx->attr.b_i16pln); ++ regs->reg87_g_intra4_penalty = rqcx->attr.i_peni4x; ++ regs->reg88_g_intra16_penalty = rqcx->attr.i_peni16; ++ regs->reg88_g_inter_penalty = rqcx->attr.i_penint; ++ regs->reg89_g_planar_penalty_luma = rqcx->attr.i_penYpl; ++ regs->reg89_g_planar_penalty_cbcr = rqcx->attr.i_penCpl; ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line, RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d", \ ++ rqct->name, rqct->i_enc_nr, IS_IPIC(rqct->i_pictyp)?'I':'P' , rqct->i_enc_qp, rqct->i_bitcnt); ++ return 0; ++} ++ ++int mrqc_enc_buff(rqct_ops* rqct, rqct_buf* buff) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ rqcx->i_config = buff->u_config; ++ if (rqcx->i_ipcount == 0) ++ rqct->seq_conf(rqct); ++ /* picture-type decision */ ++ if (rqcx->i_ipcount == rqcx->i_iperiod) ++ { ++ /* I-Frame */ ++ rqcx->i_ipcount = ++ rqcx->i_ltrpcount = ++ rqcx->i_refcnt = 1; ++ rqct->i_pictyp = RQCT_PICTYP_I; ++ rqct->b_unrefp = 0; ++ } ++ else ++ { ++ rqcx->i_ipcount++; ++ if (rqcx->i_ltrperiod != 0 && rqcx->i_ltrpcount >= rqcx->i_ltrperiod) ++ { ++// printk("%s-LTR period(%d), count(%d)\n", __func__, rqcx->i_ltrperiod, rqcx->i_ltrpcount); ++ /* LTR P-frame */ ++ rqct->i_pictyp = RQCT_PICTYP_LTRP; ++ rqcx->i_ltrpcount = 1; ++ } ++ else ++ { ++ /* P-frame */ ++ rqct->i_pictyp = RQCT_PICTYP_P; ++ if (rqcx->i_ltrperiod) ++ rqcx->i_ltrpcount++; ++ if (rqct->b_unrefp) ++ rqct->b_unrefp = !(1&rqcx->i_refcnt); ++ } ++ } ++ return 0; ++} ++EXPORT_SYMBOL(mrqc_enc_buff); ++ ++static int _enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ mfe6_reg* regs = (mfe6_reg*)mjob; ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->regf5 = regs->regf6 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ rqct->i_enc_bs+= mjob->i_bits/8; ++ rqct->i_enc_nr++; ++ rqcx->i_refcnt++; ++ return 0; ++} ++ ++int mrqc_set_rqcf(rqct_ops* rqct, rqct_cfg* rqcf) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ int err = -1; ++ switch (rqcf->type) ++ { ++ case RQCT_CFG_SEQ: ++ /* TODO: this is workaround for same gop when new seq */ ++#if 1 ++ if (rqcx->attr.i_method == rqcf->seq.i_method && ++ rqcx->attr.i_iperiod == rqcf->seq.i_period && ++ rqcx->attr.i_btrate == rqcf->seq.i_btrate && ++ rqcx->attr.i_leadqp == rqcf->seq.i_leadqp) ++ { ++ printk(KERN_ERR "%s - skip set RQCT_CFG_SEQ\n", __func__); ++ err = 0; ++ break; ++ } ++#endif ++ if ((unsigned)rqcf->seq.i_method > RQCT_MODE_VBR) ++ break; ++ rqcx->attr.i_method = rqcf->seq.i_method; ++ rqcx->attr.i_iperiod = rqcf->seq.i_period; ++ rqcx->attr.i_btrate = rqcf->seq.i_btrate; ++ rqcx->attr.i_leadqp = rqcf->seq.i_leadqp; ++ rqcx->i_ipcount = 0; ++ err = 0; ++ break; ++ case RQCT_CFG_LTR: ++ rqcx->attr.i_ltrperiod = rqcf->ltr.i_period; ++ rqcx->i_ltrperiod = rqcx->attr.i_ltrperiod; ++// rqcx->i_ltrpcount = 0; ++ err = 0; ++ break; ++ case RQCT_CFG_DQP: ++ rqcx->attr.i_deltaq = MAX(MIN(rqcf->dqp.i_dqp, DQP_MAX), DQP_MIN); ++ err = 0; ++ break; ++ case RQCT_CFG_QPR: ++ if (rqcf->qpr.i_iupperq < rqcf->qpr.i_ilowerq) ++ { ++ err = -1; ++ break; ++ } ++ if (rqcf->qpr.i_pupperq < rqcf->qpr.i_plowerq) ++ { ++ err = -1; ++ break; ++ } ++ rqcx->attr.i_iupperq = MAX(MIN(rqcf->qpr.i_iupperq, QP_MAX), QP_MIN); ++ rqcx->attr.i_ilowerq = MAX(MIN(rqcf->qpr.i_ilowerq, QP_MAX), QP_MIN); ++ rqcx->attr.i_pupperq = MAX(MIN(rqcf->qpr.i_pupperq, QP_MAX), QP_MIN); ++ rqcx->attr.i_plowerq = MAX(MIN(rqcf->qpr.i_plowerq, QP_MAX), QP_MIN); ++ err = 0; ++ break; ++ case RQCT_CFG_LOG: ++ rqcx->attr.b_logoff = !rqcf->log.b_logm; ++ err = 0; ++ break; ++ /* private config */ ++ case RQCT_CFG_RES: ++ rqcx->attr.i_pict_w = rqcf->res.i_picw; ++ rqcx->attr.i_pict_h = rqcf->res.i_pich; ++ err = 0; ++ break; ++ case RQCT_CFG_FPS: ++ rqcx->attr.n_fmrate = rqcf->fps.n_fps; ++ rqcx->attr.d_fmrate = rqcf->fps.d_fps; ++ err = 0; ++ break; ++ case RQCT_CFG_ROI: ++ err = 0; ++ rqcx->attr.b_dqmstat = -1; ++ if (-1 == rqcf->roi.i_roiidx) ++ { ++ memset(rqcx->attr.i_roidqp, 0, sizeof(rqcx->attr.i_roidqp)); ++ break; ++ } ++ if (rqcf->roi.i_roidqp == 0 || ++ (unsigned)rqcf->roi.i_posx > (unsigned)rqcx->attr.i_dqmw || ++ (unsigned)rqcf->roi.i_posy > (unsigned)rqcx->attr.i_dqmh || ++ rqcf->roi.i_recw <= 0 || ++ rqcf->roi.i_rech <= 0) ++ { ++ rqcx->attr.i_roidqp[rqcf->roi.i_roiidx] = 0; ++ break; ++ } ++ if (rqcf->roi.i_recw > (rqcx->attr.i_dqmw - rqcf->roi.i_posx)) ++ rqcf->roi.i_recw = (rqcx->attr.i_dqmw - rqcf->roi.i_posx); ++ if (rqcf->roi.i_rech > (rqcx->attr.i_dqmh - rqcf->roi.i_posy)) ++ rqcf->roi.i_rech = (rqcx->attr.i_dqmh - rqcf->roi.i_posy); ++ rqcx->attr.i_roidqp[rqcf->roi.i_roiidx] = rqcf->roi.i_roidqp; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posx = rqcf->roi.i_posx; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posy = rqcf->roi.i_posy; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_recw = rqcf->roi.i_recw; ++ rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_rech = rqcf->roi.i_rech; ++ break; ++ case RQCT_CFG_DQM: ++ rqcx->attr.u_dqmphys = rqcf->dqm.u_phys; ++ rqcx->attr.p_dqmkptr = rqcf->dqm.p_kptr; ++ rqcx->attr.i_dqmsize = rqcf->dqm.i_size; ++ rqcx->attr.i_dqmw = rqcf->dqm.i_dqmw; ++ rqcx->attr.i_dqmh = rqcf->dqm.i_dqmh; ++ err = 0; ++ break; ++ case RQCT_CFG_PEN: ++ rqcx->attr.b_i16pln = rqcf->pen.b_i16pln; ++ rqcx->attr.i_peni4x = rqcf->pen.i_peni4x; ++ rqcx->attr.i_peni16 = rqcf->pen.i_peni16; ++ rqcx->attr.i_penint = rqcf->pen.i_penint; ++ rqcx->attr.i_penYpl = rqcf->pen.i_penYpl; ++ rqcx->attr.i_penCpl = rqcf->pen.i_penCpl; ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ return err; ++} ++EXPORT_SYMBOL(mrqc_set_rqcf); ++ ++int mrqc_get_rqcf(rqct_ops* rqct, rqct_cfg* rqcf) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ int err = -1; ++ switch (rqcf->type) ++ { ++ case RQCT_CFG_SEQ: ++ rqcf->seq.i_method = rqcx->attr.i_method; ++ rqcf->seq.i_period = rqcx->attr.i_iperiod; ++ rqcf->seq.i_btrate = rqcx->attr.i_btrate; ++ rqcf->seq.i_leadqp = rqcx->attr.i_leadqp; ++ err = 0; ++ break; ++ case RQCT_CFG_LTR: ++ rqcf->ltr.i_period = rqcx->attr.i_ltrperiod; ++ err = 0; ++ break; ++ case RQCT_CFG_DQP: ++ rqcf->dqp.i_dqp = rqcx->attr.i_deltaq; ++ err = 0; ++ break; ++ case RQCT_CFG_QPR: ++ rqcf->qpr.i_iupperq = rqcx->attr.i_iupperq; ++ rqcf->qpr.i_ilowerq = rqcx->attr.i_ilowerq; ++ rqcf->qpr.i_pupperq = rqcx->attr.i_pupperq; ++ rqcf->qpr.i_plowerq = rqcx->attr.i_plowerq; ++ err = 0; ++ break; ++ case RQCT_CFG_LOG: ++ rqcf->log.b_logm = !rqcx->attr.b_logoff; ++ err = 0; ++ break; ++ /* private config */ ++ case RQCT_CFG_RES: ++ rqcf->res.i_picw = rqcx->attr.i_pict_w; ++ rqcf->res.i_pich = rqcx->attr.i_pict_h; ++ err = 0; ++ break; ++ case RQCT_CFG_FPS: ++ rqcf->fps.n_fps = rqcx->attr.n_fmrate; ++ rqcf->fps.d_fps = rqcx->attr.d_fmrate; ++ err = 0; ++ break; ++ case RQCT_CFG_ROI: ++ rqcf->roi.i_roidqp = rqcx->attr.i_roidqp[rqcf->roi.i_roiidx]; ++ rqcf->roi.i_posx = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posx; ++ rqcf->roi.i_posy = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_posy; ++ rqcf->roi.i_recw = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_recw; ++ rqcf->roi.i_rech = rqcx->attr.m_roirec[rqcf->roi.i_roiidx].i_rech; ++ err = 0; ++ break; ++ case RQCT_CFG_DQM: ++ rqcf->dqm.u_phys = rqcx->attr.u_dqmphys; ++ rqcf->dqm.p_kptr = rqcx->attr.p_dqmkptr; ++ rqcf->dqm.i_dqmw = rqcx->attr.i_dqmw; ++ rqcf->dqm.i_dqmh = rqcx->attr.i_dqmh; ++ rqcf->dqm.i_size = rqcx->attr.i_dqmsize; ++ err = 0; ++ break; ++ case RQCT_CFG_PEN: ++ rqcf->pen.b_i16pln = rqcx->attr.b_i16pln; ++ rqcf->pen.i_peni4x = rqcx->attr.i_peni4x; ++ rqcf->pen.i_peni16 = rqcx->attr.i_peni16; ++ rqcf->pen.i_penint = rqcx->attr.i_penint; ++ rqcf->pen.i_penYpl = rqcx->attr.i_penYpl; ++ rqcf->pen.i_penCpl = rqcx->attr.i_penCpl; ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ return err; ++} ++EXPORT_SYMBOL(mrqc_get_rqcf); ++ ++static int _draw(rqct_att* attr) ++{ ++ int i = 0, enable = 0; ++ char* tbl = (char*)attr->p_dqmkptr + 1; ++ uchar* idc = (char*)attr->p_dqmkptr +16; ++ int mbw = attr->i_dqmw; ++ struct roirec* roi = attr->m_roirec; ++ while (i < RQCT_ROI_NR) ++ { ++ struct roirec* rec = roi+i; ++ uchar h, l; ++ int w, j, k, m, n; ++ tbl[i] = attr->i_roidqp[i]; ++ if (tbl[i++] == 0) ++ continue; ++ enable++; ++ n = rec->i_rech; ++ j = rec->i_posy * mbw + rec->i_posx; ++ k = rec->i_recw + j; ++ l = (uchar)i; ++ h = l << 4; ++ for (m = 0; m < n; m++) ++ { ++ uchar* p = idc + (j>>1), q; ++ q = *p; ++ w = j; ++ do ++ switch (w&1) ++ { ++ case 0: ++ if (!(q&0x0F)) q += l; ++ break; ++ case 1: ++ if (!(q&0xF0)) q += h; ++ *p++ = q; ++ q = *p; ++ break; ++ } ++ while (++w < k); ++ *p++ = q; ++ j += mbw; ++ k += mbw; ++ } ++ } ++ idc[0] &=0xF0; ++ return enable; ++} ++ ++int mrqc_roi_draw(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ mfe6_reg* regs = (mfe6_reg*)mjob; ++ ++ if (0 > rqcx->attr.b_dqmstat) ++ { /* edit qmap and enable it */ ++ MEM_SETV((char*)rqcx->attr.p_dqmkptr +16, 0, rqcx->attr.i_dqmsize-16); ++ if (_draw(&rqcx->attr)) ++ { ++ regs->regf2_g_roi_en = 1; ++ regs->regfb_g_roi_qmap_adr_lo = (ushort)(rqcx->attr.u_dqmphys>> 8); ++ regs->regfc_g_roi_qmap_adr_hi = (ushort)(rqcx->attr.u_dqmphys>>24); ++ rqcx->attr.b_dqmstat = 1; ++ } ++ else ++ { ++ regs->regf2_g_roi_en = 0; ++ regs->regfb_g_roi_qmap_adr_lo = 0; ++ regs->regfc_g_roi_qmap_adr_hi = 0; ++ rqcx->attr.b_dqmstat = 0; ++ } ++#if 0 ++ /* draw qmap on console */ ++ int i, j, w = rqcx->attr.i_dqmw/2; ++ uchar* pl = (char*)rqcx->attr.p_dqmkptr +16; ++ for(i = 0; i < RQCT_ROI_NR; i++) ++ printk("%3d", rqcx->attr.i_roidqp[i]); ++ printk("\n"); ++ for (i = 0; i < rqcx->attr.i_dqmh; i++) ++ { ++ for (j = 0; j < rqcx->attr.i_dqmw/2; j++) ++ { ++ uchar qm = pl[w*i+j]; ++ qm = (qm>>4) + (qm<<4); ++ printk("%02X",qm); ++ } ++ printk("\n"); ++ } ++#endif ++ } ++ return (rqcx->attr.b_dqmstat); ++} ++EXPORT_SYMBOL(mrqc_roi_draw); +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_rqc.h b/drivers/mstar/mfev5/mfe6/mfe6_rqc.h +new file mode 100644 +index 00000000..a3c426ad +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_rqc.h +@@ -0,0 +1,42 @@ ++ ++#ifndef _MFE_RCTL_H_ ++#define _MFE_RCTL_H_ ++ ++#include ++ ++typedef struct mfe6_rqc ++{ ++ rqct_ops rqct; ++ rqct_att attr; ++ int i_iperiod; //I-frame/P-frame period ++ int i_ltrperiod; //LTR P-frame / P-frame period ++ int i_ipcount; //I-frame/P-frame count up to period ++ int i_ltrpcount; //LTR-frame/P-frame count up to period ++#define RCTL_CFG_MB_DQP (1<<0) ++#define RCTL_CFG_NIGHT (1<<2) ++ int i_refcnt; ++ int i_config; ++} mfe6_rqc; ++ ++#define QP_UPPER (48) ++#define QP_LOWER (12) ++#define QP_RANGE (QP_UPPER-QP_LOWER) ++#define QP_MAX (51) ++#define QP_MIN (10) ++#define QP_IFRAME_DELTA (-2) //I-frame QP delta from P-frame ++#define DQP_MAX 12 ++#define DQP_MIN -12 ++ ++void* rqctmfe_acquire(int); ++char* rqctmfe_comment(int); ++ ++/* basic functions of mfe rate-controller */ ++int mrqc_set_rqcf(rqct_ops* rqct, rqct_cfg* rqcf); ++int mrqc_get_rqcf(rqct_ops* rqct, rqct_cfg* rqcf); ++int mrqc_enc_buff(rqct_ops* rqct, rqct_buf* buff); ++int mrqc_roi_draw(rqct_ops* rqct, mhve_job* mjob); ++/* functions to insert/remove additional rate-controller */ ++int rqctmfe_insert(void*(*allc)(void), char*(*desc)(void)); ++int rqctmfe_remove(void); ++ ++#endif/*_MFE_RCTL_H_*/ +diff --git a/drivers/mstar/mfev5/mfe6/mfe6_utl.h b/drivers/mstar/mfev5/mfe6/mfe6_utl.h +new file mode 100644 +index 00000000..cb6c60df +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/mfe6_utl.h +@@ -0,0 +1,64 @@ ++ ++#ifndef _MFE6_UTL_H_ ++#define _MFE6_UTL_H_ ++ ++#ifndef _MAX ++#define _MAX(a,b) ((a)>(b)?(a):(b)) ++#endif ++#ifndef _MIN ++#define _MIN(a,b) ((a)<(b)?(a):(b)) ++#endif ++ ++typedef struct iir_t { ++#define KAPA_ONE 1024 ++ int i_kapa; ++ int i_data; ++} iir_t; ++inline static int iir_init(iir_t* iir, int data, int kapa) ++{ ++ iir->i_kapa = kapa; ++ iir->i_data = data; ++ return iir->i_data; ++} ++inline static int iir_push(iir_t* iir, int data) ++{ ++ int64 calc = (int64)data * iir->i_kapa; ++ data = !iir->i_data ? data:iir->i_data; ++ calc += (int64)data * (KAPA_ONE-iir->i_kapa); ++ iir->i_data = (int)div_s64(calc,KAPA_ONE); ++ return iir->i_data; ++} ++inline static int iir_data(iir_t* iir) ++{ ++ return iir->i_data; ++} ++ ++typedef struct acc_t { ++#define ACC_SIZE (1<<8) ++#define ACC_MASK (ACC_SIZE-1) ++ int i_curr; ++ int i_data[ACC_SIZE]; ++} acc_t; ++inline static int acc_init(acc_t* acc, int data) ++{ ++ int i = ACC_SIZE; ++ while (i-- > 0) ++ acc->i_data[i] = -i*data; ++ acc->i_curr = 0; ++ return data; ++} ++inline static int acc_push(acc_t* acc, int data) ++{ ++ int v = data + acc->i_data[ACC_MASK&(acc->i_curr)]; ++ acc->i_curr--; ++ acc->i_data[ACC_MASK&(acc->i_curr)] = v; ++ return data; ++} ++inline static int acc_calc(acc_t* acc, int size) ++{ ++ int lead = acc->i_data[ACC_MASK&(acc->i_curr)]; ++ int tail = acc->i_data[ACC_MASK&(acc->i_curr+size)]; ++ return (lead-tail); ++} ++ ++#endif//_MFE6_UTL_H_ +diff --git a/drivers/mstar/mfev5/mfe6/msb2_rqc.c b/drivers/mstar/mfev5/mfe6/msb2_rqc.c +new file mode 100644 +index 00000000..d8af728a +--- /dev/null ++++ b/drivers/mstar/mfev5/mfe6/msb2_rqc.c +@@ -0,0 +1,905 @@ ++ ++#include ++#include ++ ++/************************************************************************/ ++/* Version Declaration */ ++/************************************************************************/ ++ ++#define MSB2_NAME "MSB2" ++#define MSB2_VER_MJR 1 ++#define MSB2_VER_MNR 1 ++#define MSB2_VER_EXT 01 ++#define _EXP(expr) #expr ++#define _STR(expr) _EXP(expr) ++ ++/************************************************************************/ ++/* Macros */ ++/************************************************************************/ ++ ++#define UP_QP_DIFF_LIMIT 3 ++#define LF_QP_DIFF_LIMIT 3 ++ ++#define LOGOFF_DEFAULT 1 ++#define LOWERQ_DEFAULT 12 ++#define UPPERQ_DEFAULT 48 ++#define BOUNDQ_DEFAULT -1 ++#define QP_DEGREE 4 ++#define LQP_HW_LIMIT 16 ++#define QS_ACCURACY 39 //40 ++ ++/* 64-bits calculation */ ++#if defined(LINUX_KERNEL) ++#include ++#define DIV_S64(n,d) div_s64(n,d) ++#else ++#define DIV_S64(n,d) ((n)/(d)) ++#endif ++ ++#ifndef MSRC_FIT_IN_RANGE ++#define MSRC_FIT_IN_RANGE(a,low,high) MIN(MAX((a),(low)),(high)) ++#endif ++ ++#ifndef MSRC_PERCENT ++#define MSRC_PERCENT(percent,a) ( (percent) * (a) / 100 ) ++#endif ++ ++/* Skip the first N frames for VBV calculation */ ++#define CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES 50 ++ ++/* The feature to reset the fullness value if fullness overflow or underflow */ ++/* 1 - Enable */ ++/* 0 - Disable */ ++#define CFG_VBV_BUF_OVERFLOW_RESET 1 ++#define CFG_VBV_BUF_UNDERFLOW_RESET 1 ++ ++#define RDC_WEIGHTED_DIVIDED 0 ++#define RDC_AVERAGE_DIVIDED 1 ++#define CFG_RC_DELTA_CACULATE_METHOD RDC_WEIGHTED_DIVIDED ++ ++/* The choice of the VBV frame quota selection */ ++#define VFQ_USE_AVERAGE_SIZE 0 /* The average size of each frame */ ++#define VFQ_USE_WEIGHTED_SIZE 1 /* The weighted size rqcx on the setting of */ ++ /* IFRAME_WEIGHT, PFRAME_WEIGHT, BFRAME_WEIGHT */ ++ /* and Gop size */ ++#define CFG_VBV_FRAME_QUOTA_METHOD VFQ_USE_WEIGHTED_SIZE ++ ++#define SMOOTH_BASE 10 // 1 sec = 10* 100ms ++//! How many seconds of frames are responsible for compensation of bitrate usage. ++#define SMOOTH_SECOND_CBR 10 // unit 100 ms ++#define SMOOTH_SECOND_CVBR 30 // unit 100 ms ++#define SMOOTH_SECOND_VBR 100 // unit 100 ms ++#define SMOOTH_FACTOR_MIN 100 // unit 100 ms ++ ++#define VBV_TGT_LVL_CBR 20 // unit 100 ms ++#define VBV_FUL_LOW_CBR 0 // unit 100 ms ++#define VBV_FUL_HIGH_CBR 40 // unit 100 ms ++#define VBV_BUF_SIZE_CBR 40 // unit 100 ms ++ ++#define VBV_TGT_LVL_VBR 40 // unit 100 ms ++#define VBV_FUL_LOW_VBR 0 // unit 100 ms ++#define VBV_FUL_HIGH_VBR 80 // unit 100 ms ++#define VBV_BUF_SIZE_VBR 80 // unit 100 ms ++ ++//! Default I-frame weighting over inter-frame ++#define IFRAME_WEIGHT (1024*7) ++#define PFRAME_WEIGHT 1024 ++#define BFRAME_WEIGHT 768 ++ ++#define MAX_FRAME_TYPE 3 // I, P, B 3 types ++ ++//enable msbr rate control ++#define RC_MSBR 1 ++/************************************************************************/ ++/* Configuration */ ++/************************************************************************/ ++ ++/************************************************************************/ ++/* Constant */ ++/************************************************************************/ ++ ++/************************************************************************/ ++/* Local structures */ ++/************************************************************************/ ++ ++#define PICTYPES 2 ++ ++typedef struct msb2_rqc ++{ ++ mfe6_rqc rqcx; ++ int i_method; ++ int i_btrate; ++ int i_levelq; ++ int i_deltaq; ++ int n_fmrate; ++ int d_fmrate; ++ int i_fmrate; ++ int i_pixels; ++ int i_blocks; ++ short b_mbkadp, i_limitq; ++ short i_frmdqp, i_blkdqp; ++ short i_iupperq, i_ilowerq; ++ short i_pupperq, i_plowerq; ++ int i_gopbit; ++ int i_frmbit; ++ int i_pixbit; ++ int i_budget; ++ int i_ipbias; ++ int i_smooth; ++ int i_bucket; ++ int i_upperb, i_lowerb; ++ int i_margin; ++ int i_radius; ++ int i_degree; ++ int i_errpro; ++ int i_imbase; ++ int i_imbits; // bit-pos:imaginary ++ int i_rebits; // bit-pos:real ++ ++ iir_t iir_rqprod[PICTYPES]; ++ acc_t acc_rqprod; ++ acc_t acc_bitcnt; ++ int i_intrabit; ++ ++#if RC_MSBR ++ /* coded frame counter */ ++ int i_frm_nr; ++ /* bitrate usage compensation */ ++ int i_vbv_buf_size; // Rate control buffer size ++ int i_vbv_fullness_low; // Rate control buffer fullness low bound ++ int i_vbv_fullness_high; // Rate control buffer fullness high bound ++ int i_vbv_fullness; // Rate control buffer fullness ++ int i_vbv_real_fullness; // Rate control buffer fullness ++ int i_vbv_target; // Rate control buffer target fullness ++ ++ int i_smooth_cnt; ++ int i_smooth_min; ++ /* variable bitrate */ ++ int i_lt_qs64; ++ /* model parameters*/ ++ int i_tgt_bs; // target number of bits of current frame ++ /* Derived variables*/ ++ int m_bpf[MAX_FRAME_TYPE]; // I, P, B ++ int i_avgbpf; ++ /* last-frame status */ ++ int i_last_avg_qs; ++ int i_avg_qs; ++ /* bitcnt return */ ++ int vbr_bit_return_stage; ++#endif ++} msb2_rqc; ++ ++/************************************************************************/ ++/* Local prototypes */ ++/************************************************************************/ ++ ++#define COMPLEX_I (1<<24) ++#define COMPLEX_P (1<<20) ++ ++static int msb2_seq_sync(rqct_ops*); ++static int msb2_seq_done(rqct_ops*); ++static int msb2_seq_conf(rqct_ops*); ++static int msb2_enc_conf(rqct_ops*, mhve_job*); ++static int msb2_enc_done(rqct_ops*, mhve_job*); ++static void _msb2_ops_free(rqct_ops* rqct) { MEM_FREE(rqct); } ++ ++/************************************************************************/ ++/* Functions */ ++/************************************************************************/ ++ ++char* msb2_describe(void) ++{ ++ static char line[64]; ++ sprintf(line, "%s@v%d.%d-%02d:r&d analysis.",MSB2_NAME,MSB2_VER_MJR,MSB2_VER_MNR,MSB2_VER_EXT); ++ return line; ++} ++ ++static int msb2_set_rqcf(rqct_ops* rqct, rqct_cfg* rqcf) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ msb2_rqc* msb2 = (msb2_rqc*)rqcx; ++ int err = -1; ++ ++ switch (rqcf->type) ++ { ++ case RQCT_CFG_DQP: ++ rqcx->attr.i_deltaq = MAX(MIN(rqcf->dqp.i_dqp, DQP_MAX), DQP_MIN); ++ ++ msb2->i_deltaq = (int)rqcx->attr.i_deltaq; ++ err = 0; ++ break; ++ case RQCT_CFG_QPR: ++ if (rqcf->qpr.i_iupperq < rqcf->qpr.i_ilowerq) ++ { ++ err = -1; ++ break; ++ } ++ if (rqcf->qpr.i_pupperq < rqcf->qpr.i_plowerq) ++ { ++ err = -1; ++ break; ++ } ++ rqcx->attr.i_iupperq = MAX(MIN(rqcf->qpr.i_iupperq, QP_MAX), QP_MIN); ++ rqcx->attr.i_ilowerq = MAX(MIN(rqcf->qpr.i_ilowerq, QP_MAX), QP_MIN); ++ rqcx->attr.i_pupperq = MAX(MIN(rqcf->qpr.i_pupperq, QP_MAX), QP_MIN); ++ rqcx->attr.i_plowerq = MAX(MIN(rqcf->qpr.i_plowerq, QP_MAX), QP_MIN); ++ ++ msb2->i_iupperq = MAX(MIN(rqcx->attr.i_iupperq, QP_MAX), QP_MIN); ++ msb2->i_ilowerq = MAX(MIN(rqcx->attr.i_ilowerq, QP_MAX), QP_MIN); ++ msb2->i_pupperq = MAX(MIN(rqcx->attr.i_pupperq, QP_MAX), QP_MIN); ++ msb2->i_plowerq = MAX(MIN(rqcx->attr.i_plowerq, QP_MAX), QP_MIN); ++ err = 0; ++ break; ++ default: ++ err = mrqc_set_rqcf(rqct, rqcf); ++ break; ++ } ++ return err; ++} ++ ++void* msb2_allocate(void) ++{ ++ rqct_ops* rqct = NULL; ++ mfe6_rqc* rqcx; ++ msb2_rqc* msb2; ++ ++ if (!(rqct = MEM_ALLC(sizeof(msb2_rqc)))) ++ return NULL; ++ ++ MEM_COPY(rqct->name, MSB2_NAME, 5); ++ rqct->release = _msb2_ops_free; ++ rqct->seq_sync = msb2_seq_sync; ++ rqct->seq_done = msb2_seq_done; ++ //rqct->set_rqcf = mrqc_set_rqcf; ++ rqct->set_rqcf = msb2_set_rqcf; ++ rqct->get_rqcf = mrqc_get_rqcf; ++ rqct->seq_conf = msb2_seq_conf; ++ rqct->enc_buff = mrqc_enc_buff; ++ rqct->enc_conf = msb2_enc_conf; ++ rqct->enc_done = msb2_enc_done; ++ rqct->i_enc_nr = 0; ++ rqct->i_enc_bs = 0; ++ rqcx = (mfe6_rqc*)rqct; ++ rqcx->attr.i_pict_w = 0; ++ rqcx->attr.i_pict_h = 0; ++ rqcx->attr.i_method = RQCT_MODE_CQP; ++ rqcx->attr.i_btrate = 0; ++ rqcx->attr.i_leadqp =-1; ++ rqcx->attr.i_deltaq = QP_IFRAME_DELTA; ++ rqcx->attr.i_iupperq = QP_UPPER; ++ rqcx->attr.i_ilowerq = QP_LOWER; ++ rqcx->attr.i_pupperq = QP_UPPER; ++ rqcx->attr.i_plowerq = QP_LOWER; ++ rqcx->attr.n_fmrate =30; ++ rqcx->attr.d_fmrate = 1; ++ rqcx->attr.i_iperiod= 0; ++ rqcx->attr.i_ltrperiod= 0; ++ rqcx->attr.b_logoff = LOGOFF_DEFAULT; ++ /* initiate penalties */ ++ rqcx->attr.b_i16pln = 1; ++ rqcx->attr.i_peni4x = 0; ++ rqcx->attr.i_peni16 = 0; ++ rqcx->attr.i_penint = 0; ++ rqcx->attr.i_penYpl = 0; ++ rqcx->attr.i_penCpl = 0; ++ rqcx->i_config = 0; ++ rqcx->i_ipcount = 0; ++ rqcx->i_iperiod = 0; ++ rqcx->i_ltrpcount = 0; ++ rqcx->i_ltrperiod = 0; ++ msb2 = (msb2_rqc*)rqcx; ++ msb2->i_levelq =36; ++ ++ printk("%s\n",msb2_describe()); ++ ++ return rqct; ++} ++ ++#define IPR_BIT (16) ++#define IPR_FAC (1<>(QSC_BIT)))>>(10-(QSC_BIT))) ++static int qscale[]={ ++ QSCALE( 645),QSCALE( 724),QSCALE( 813),QSCALE( 912),QSCALE( 1024), ++QSCALE( 1149),QSCALE( 1290),QSCALE( 1448),QSCALE( 1625),QSCALE( 1825),QSCALE( 2048), ++QSCALE( 2299),QSCALE( 2580),QSCALE( 2896),QSCALE( 3251),QSCALE( 3649),QSCALE( 4096), ++QSCALE( 4598),QSCALE( 5161),QSCALE( 5793),QSCALE( 6502),QSCALE( 7298),QSCALE( 8192), ++QSCALE( 9195),QSCALE( 10321),QSCALE( 11585),QSCALE( 13004),QSCALE( 14596),QSCALE( 16384), ++QSCALE( 18390),QSCALE( 20643),QSCALE( 23170),QSCALE( 26008),QSCALE( 29193),QSCALE( 32768), ++QSCALE( 36781),QSCALE( 41285),QSCALE( 46341),QSCALE( 52016),QSCALE( 58386),QSCALE( 65536), ++QSCALE( 73562),QSCALE( 82570),QSCALE( 92682),QSCALE(104032),QSCALE(116772),QSCALE(131072), ++QSCALE(147123),QSCALE(165140),QSCALE(185364),QSCALE(208064),QSCALE(233544),QSCALE(262144), ++}; ++static int qp2qs(int qp) ++{ ++ if (qp< 0) return qscale[ 0]; ++ if (qp>51) return 2147483647; ++ return qscale[qp]; ++} ++static int qindex[]={ ++ 4,10,16,16,22,22,22,22,28,28,28,28,28,28,28,28, ++34,34,34,34,34,34,34,34,34,34,34,34,34,34,34,34, ++40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, ++40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++46,46,46,46,46,46,46,46,46,46,46,46,46,46,46,46, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++52,52,52,52,52,52,52,52,52,52,52,52,52,52,52,52, ++}; ++static int qs2qp(unsigned long qs) ++{ ++ int idx, cost, best; ++ if (qsqscale[51]) return 51; ++ idx = qindex[qs>>QSC_BIT]; ++ best = (qscale[idx]-qs); ++ while (0<(cost=(qscale[--idx]-qs))) ++ best=cost; ++ if (best<-cost) ++ return ++idx; ++ return idx; ++} ++#define DQBIAS_BIT 15 ++#define DQBIAS_FAC (1<>(16-DQBIAS_BIT)) ++static const int dqplot[] = { ++DQBIAS( 0),//0.0000000000 ++DQBIAS(13889),//0.2119255505 ++DQBIAS(22749),//0.3471209568 ++DQBIAS(28655),//0.4372439481 ++DQBIAS(33009),//0.5036719007 ++DQBIAS(36440),//0.5560238879 ++DQBIAS(39266),//0.5991464061 ++DQBIAS(41666),//0.6357766516 ++DQBIAS(43752),//0.6676004651 ++DQBIAS(45595),//0.6957262149 ++DQBIAS(47246),//0.7209202303 ++DQBIAS(48741),//0.7437338663 ++DQBIAS(50107),//0.7645767803 ++DQBIAS(51365),//0.7837615271 ++DQBIAS(52529),//0.8015319306 ++DQBIAS(53614),//0.8180818208 ++DQBIAS(54629),//0.8335678038 ++DQBIAS(55582),//0.8481182052 ++DQBIAS(56482),//0.8618394843 ++DQBIAS(57332),//0.8748209289 ++DQBIAS(58139),//0.8871381559 ++DQBIAS(58907),//0.8988557638 ++DQBIAS(59640),//0.9100293726 ++DQBIAS(60339),//0.9207072127 ++DQBIAS(61010),//0.9309313772 ++DQBIAS(61652),//0.9407388203 ++DQBIAS(62270),//0.9501621606 ++DQBIAS(62864),//0.9592303332 ++DQBIAS(63437),//0.9679691242 ++DQBIAS(63989),//0.9764016112 ++DQBIAS(64523),//0.9845485296 ++DQBIAS(65040),//0.9924285792 ++}; ++static int qdelta(int r) ++{ ++ int d = 0, s = r<0; ++ r = s?-r:r; ++ while (r > dqplot[++d]) ; ++ --d; ++ return s?-d:d; ++} ++/* ++static int dqbias(int d) ++{ ++ int i=((unsigned)(d+32)>64)?32:(d<0?-d:d); ++ int p=dqplot[i]; ++ return d<0?-p:p; ++} ++*/ ++#define MAX_SUMQS ((2UL<<31)-1) ++#define ALIGN2MB(l) (((l)+15)>>4) ++static int calc_limitq(int mbs) ++{ ++ unsigned long qs = MAX_SUMQS/(mbs-1); ++ int qp = qs2qp(qs); ++ return qsm_bpf[0], msb2->m_bpf[1], msb2->m_bpf[2] ); ++ } ++ #endif ++ ++ return 0; ++} ++ ++static int msb2_seq_sync(rqct_ops* rqct) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ rqcx->i_ipcount = 0; ++ rqcx->i_ltrpcount = 0; ++ return 0; ++} ++ ++#define SMOOTH_X (16) ++ ++static int msb2_seq_conf(rqct_ops* rqct) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ msb2_rqc* msb2 = (msb2_rqc*)rqcx; ++ short upperq = rqcx->attr.i_iupperq>rqcx->attr.i_pupperq?rqcx->attr.i_iupperq:rqcx->attr.i_pupperq; ++ short lowerq = rqcx->attr.i_ilowerqattr.i_plowerq?rqcx->attr.i_ilowerq:rqcx->attr.i_plowerq; ++ msb2->i_method = (int)rqcx->attr.i_method; ++ msb2->i_btrate = (int)rqcx->attr.i_btrate; ++ if (rqcx->attr.i_leadqp > 8 && rqcx->attr.i_leadqp < 48) ++ msb2->i_levelq = (int)rqcx->attr.i_leadqp; ++ msb2->i_deltaq = (int)rqcx->attr.i_deltaq; ++ msb2->n_fmrate = (int)rqcx->attr.n_fmrate; ++ msb2->d_fmrate = (int)rqcx->attr.d_fmrate; ++ msb2->i_pixels = (int)rqcx->attr.i_pict_w*rqcx->attr.i_pict_h; ++ msb2->i_fmrate = (msb2->n_fmrate+msb2->n_fmrate-1)/msb2->d_fmrate; ++ msb2->i_blocks = ALIGN2MB(rqcx->attr.i_pict_w)*ALIGN2MB(rqcx->attr.i_pict_h); ++ msb2->i_limitq = calc_limitq(msb2->i_blocks); ++ msb2->i_iupperq = MAX(MIN(rqcx->attr.i_iupperq, QP_MAX), QP_MIN); ++ msb2->i_ilowerq = MAX(MIN(rqcx->attr.i_ilowerq, QP_MAX), QP_MIN); ++ msb2->i_pupperq = MAX(MIN(rqcx->attr.i_pupperq, QP_MAX), QP_MIN); ++ msb2->i_plowerq = MAX(MIN(rqcx->attr.i_plowerq, QP_MAX), QP_MIN); ++ if (msb2->i_btrate == 0) ++ msb2->i_method = RQCT_MODE_CQP; ++ rqcx->i_ipcount = ++ rqcx->i_iperiod = (int)rqcx->attr.i_iperiod; ++ rqcx->i_ltrpcount = ++ rqcx->i_ltrperiod = (int)rqcx->attr.i_ltrperiod; ++ ++// msb2->i_smooth = rqcx->i_iperiod*2; ++ msb2->i_smooth = rqcx->i_iperiod; ++ msb2->i_frmbit = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate,msb2->n_fmrate); ++ msb2->i_pixbit = (int)div_s64((int64)msb2->i_frmbit*BPP_FAC,msb2->i_pixels); ++ msb2->i_gopbit = rqcx->i_iperiod*msb2->i_frmbit; ++ msb2->b_mbkadp = 0; ++ msb2->i_blkdqp = 4; ++ msb2->i_frmdqp = 1; ++ ++ msb2->i_degree = MAX(msb2->i_btrate/(QP_RANGE*2), 1); //avoid division by zero in kernel ++ msb2->i_margin = msb2->i_degree*(QP_RANGE); ++ msb2->i_bucket = msb2->i_margin<<1; ++ msb2->i_radius = msb2->i_margin>>1; ++ msb2->i_rebits = ++ msb2->i_imbits = ++ msb2->i_imbase = msb2->i_margin+(msb2->i_levelq-QP_LOWER)*msb2->i_degree; ++ msb2->i_lowerb = msb2->i_margin+(lowerq-QP_LOWER)*msb2->i_degree; ++ msb2->i_upperb = msb2->i_margin+(upperq-QP_LOWER)*msb2->i_degree; ++ ++ iir_init(&msb2->iir_rqprod[RQCT_PICTYP_I], COMPLEX_I, KAPA_ONE*3/4); ++ iir_init(&msb2->iir_rqprod[RQCT_PICTYP_P], COMPLEX_P, KAPA_ONE*2/4); ++ acc_init(&msb2->acc_rqprod, COMPLEX_P); ++ acc_init(&msb2->acc_bitcnt, msb2->i_frmbit*3/4); ++ ++#if RC_MSBR ++ msb2->i_avgbpf = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate,msb2->n_fmrate); ++ ++ if (rqcx->i_iperiod > 0) ++ { ++ int length = rqcx->i_iperiod; ++ int weight = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_iperiod-1); ++ msb2->m_bpf[0] = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate*IFRAME_WEIGHT*length, (int64)weight*msb2->n_fmrate); ++ msb2->m_bpf[1] = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate*PFRAME_WEIGHT*length, (int64)weight*msb2->n_fmrate); ++ msb2->m_bpf[2] = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate*BFRAME_WEIGHT*length, (int64)weight*msb2->n_fmrate); ++ } ++ else ++ { ++ msb2->m_bpf[0] = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate*IFRAME_WEIGHT, (int64)PFRAME_WEIGHT*msb2->n_fmrate); ++ msb2->m_bpf[1] = (int)div_s64((int64)msb2->i_btrate*msb2->d_fmrate,msb2->n_fmrate); ++ msb2->m_bpf[2] = msb2->m_bpf[1]; ++ } ++ ++ // Bitrate usage monitoring ++ msb2->i_smooth_min = (msb2->n_fmrate*SMOOTH_SECOND_CBR)/msb2->d_fmrate/SMOOTH_BASE; ++ ++ switch (msb2->i_method) ++ { ++ case RQCT_MODE_VBR: ++ msb2->i_smooth_cnt = (msb2->n_fmrate*SMOOTH_SECOND_VBR)/msb2->d_fmrate/SMOOTH_BASE; ++ msb2->i_vbv_target = msb2->i_btrate * VBV_TGT_LVL_VBR / SMOOTH_BASE; ++ msb2->i_vbv_fullness_low = msb2->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msb2->i_vbv_fullness_high = msb2->i_btrate * VBV_FUL_LOW_VBR / SMOOTH_BASE; ++ msb2->i_vbv_buf_size = msb2->i_btrate * VBV_BUF_SIZE_VBR / SMOOTH_BASE; ++ break; ++ case RQCT_MODE_CBR: ++ default: ++ msb2->i_smooth_cnt = (int)div_s64((int64)msb2->n_fmrate*SMOOTH_SECOND_CBR,msb2->d_fmrate*SMOOTH_BASE); ++ msb2->i_vbv_target = msb2->i_btrate * VBV_TGT_LVL_CBR / SMOOTH_BASE; ++ msb2->i_vbv_fullness_low = msb2->i_btrate * VBV_FUL_LOW_CBR / SMOOTH_BASE; ++ msb2->i_vbv_fullness_high = msb2->i_btrate * VBV_FUL_LOW_CBR / SMOOTH_BASE; ++ msb2->i_vbv_buf_size = msb2->i_btrate * VBV_BUF_SIZE_CBR / SMOOTH_BASE; ++ break; ++ } ++ ++ msb2->i_vbv_fullness = msb2->i_vbv_target; ++ msb2->i_vbv_real_fullness = msb2->i_vbv_target; ++ ++ MFE_DBG( "conf i_vbv_fullness = %d\n", msb2->i_vbv_fullness); ++ ++ msb2->i_last_avg_qs = 0; ++ msb2->i_frm_nr = 0; ++ msb2->i_lt_qs64 = 0; ++ msb2->vbr_bit_return_stage = 0; ++#endif ++ ++ return 0; ++} ++ ++#if RC_MSBR ++static int _msbr_get_smooth_count(msb2_rqc* msb2) ++{ ++ int smooth_cnt = 0; ++ if (msb2->i_frm_nr > msb2->i_smooth_cnt*SMOOTH_FACTOR_MIN/SMOOTH_BASE) ++ smooth_cnt = msb2->i_smooth_cnt; ++ else if (msb2->i_frm_nr < msb2->i_smooth_min) ++ smooth_cnt = msb2->i_smooth_min; ++ else ++ { ++ int fact_n = MAX((msb2->i_smooth_cnt - msb2->i_smooth_min), 1); ++ int fact_d = MAX((msb2->i_smooth_cnt * SMOOTH_FACTOR_MIN/SMOOTH_BASE - msb2->i_smooth_min), 1); ++ smooth_cnt = msb2->i_smooth_min + (msb2->i_frm_nr - msb2->i_smooth_min) * fact_n / fact_d; ++ } ++ ++ return smooth_cnt; ++} ++ ++static int _msbr_calculate_delta(msb2_rqc* msb2, int smooth_cnt, int frm_type) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)msb2; ++ rqct_ops* rqct = (rqct_ops*)rqcx; ++ int delta = 0; ++ ++ #if ( CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES != 0 ) ++ if(msb2->i_frm_nr < CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ) ++ { ++ msb2->i_vbv_fullness = msb2->i_vbv_target; ++ ++ return 0; ++ } ++ #endif //CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ++ ++ #if CFG_VBV_BUF_UNDERFLOW_RESET ++ ++ /* reset if under flow */ ++ if( msb2->i_vbv_fullness < 0 ) ++ { ++ MFE_DBG( "reset i_vbv_fullness %d= 0\n", msb2->i_vbv_fullness ); ++ msb2->i_vbv_fullness = 0; ++ } ++ #endif //CFG_VBV_BUF_UNDERFLOW_RESET ++ ++ #if CFG_VBV_BUF_OVERFLOW_RESET ++ ++ if( msb2->i_vbv_fullness > msb2->i_vbv_buf_size ) ++ { ++ MFE_DBG( "reset i_vbv_fullness %d= %d\n", msb2->i_vbv_fullness, msb2->i_vbv_buf_size ); ++ msb2->i_vbv_fullness = msb2->i_vbv_buf_size; ++ } ++ ++ #endif //CFG_VBV_BUF_OVERFLOW_RESET ++ ++ if (msb2->i_method == RQCT_MODE_CBR) ++ { ++ delta = (int)div_s64((int64)(msb2->i_vbv_fullness-msb2->i_vbv_target)*msb2->d_fmrate,msb2->n_fmrate*SMOOTH_SECOND_CBR/SMOOTH_BASE); ++ MFE_DBG( "i_vbv_fullness %d i_vbv_target %d delta = %d\n", msb2->i_vbv_fullness, msb2->i_vbv_target,delta ); ++ ++ #if( CFG_RC_DELTA_CACULATE_METHOD == RDC_WEIGHTED_DIVIDED ) ++ { ++ int wp[MAX_FRAME_TYPE] = {IFRAME_WEIGHT,PFRAME_WEIGHT,BFRAME_WEIGHT}; ++ int w = IFRAME_WEIGHT + PFRAME_WEIGHT*(rqcx->i_iperiod-1); ++ int n = rqcx->i_iperiod; ++ ++ // Multiply the ratio of the frame type ++ delta = delta* n * wp[frm_type] / w; ++ MFE_DBG( "Adjust delta = %d\n", delta ); ++ } ++ #endif //CFG_RC_DELTA_CACULATE_METHOD ++ ++ } ++ else if (msb2->i_method == RQCT_MODE_VBR) ++ { ++ delta = (msb2->i_vbv_fullness - msb2->i_vbv_target) / smooth_cnt; ++ if (delta > 0 && (msb2->i_last_avg_qs*64) > msb2->i_lt_qs64) ++ delta = delta>>1; // Make it more variable bitrate to allow better quality ++ ++//when previous frame's average QPi_pictyp)) ++ VbrMinQP = msb2->i_ilowerq; ++ else ++ VbrMinQP = msb2->i_plowerq; ++ ++ if (qs2qp(msb2->i_avg_qs) < VbrMinQP + QP_DEGREE) ++ { ++ int return_bits; ++ if (msb2->vbr_bit_return_stagevbr_bit_return_stage++; //when meet MAX_STAGE, return all the compensation bits. ++ } ++ return_bits = -delta * msb2->vbr_bit_return_stage / VBR_BIT_RETURN_MAX_STAGE; ++ delta = return_bits; ++ msb2->i_vbv_fullness += return_bits; ++ } ++ } ++ else ++ { ++ msb2->vbr_bit_return_stage = 0; ++ } ++ } ++ ++ return delta; ++} ++#endif ++ ++static int msb2_enc_conf(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ mfe6_reg* regs = (mfe6_reg*)mjob; ++ msb2_rqc* msb2 = (msb2_rqc*)rqcx; ++ int qsc, bpp, pqp, dqp, lim, tgt=0; ++ int uqp = 0; ++ int lqp = 0; ++ switch (msb2->i_method) ++ { ++ case RQCT_MODE_CQP: ++ rqct->i_enc_qp = msb2->i_levelq; ++ if (IS_IPIC(rqct->i_pictyp)) ++ rqct->i_enc_qp -= msb2->i_deltaq; ++ break; ++ case RQCT_MODE_CBR: ++ case RQCT_MODE_VBR: ++ default: ++ lim = msb2->i_limitq; ++ if (IS_IPIC(rqct->i_pictyp)) ++ { ++ int xi = iir_data(&msb2->iir_rqprod[RQCT_PICTYP_I]); ++ int xp = acc_calc(&msb2->acc_rqprod,SMOOTH_X)/SMOOTH_X; ++ int ri = (int)div_s64((int64)qp2qs(QS_ACCURACY+msb2->i_deltaq)*IPR_FAC,qp2qs(QS_ACCURACY)); ++ int rp = (int)div_s64((int64)xp*IPR_FAC,xi); ++ uqp = msb2->i_iupperq; ++ lqp = msb2->i_ilowerq; ++ msb2->i_budget = (int)div_s64((int64)msb2->i_gopbit*ri,(rqcx->i_iperiod*rp+ri-rp)); ++ bpp = _MAX((int)div_s64((int64)msb2->i_budget*BPP_FAC,msb2->i_pixels), 1); //avoid division by zero in kernel ++ qsc = xi/bpp; ++ pqp = _MAX(qs2qp(qsc),msb2->i_levelq-msb2->i_deltaq); ++ pqp = _MAX(lqp,_MIN(pqp,uqp)); ++ if( lqp>(pqp-QP_DEGREE) && lqp>LQP_HW_LIMIT) ++ pqp = lqp + QP_DEGREE; ++ rqct->i_enc_qp = pqp; ++ tgt = msb2->i_budget/msb2->i_blocks; ++ uqp = _MIN(pqp+msb2->i_blkdqp,_MIN(lim,uqp)); ++ lqp = _MIN(_MAX(pqp-msb2->i_blkdqp,lqp), LQP_HW_LIMIT); ++ msb2->b_mbkadp = msb2->i_blkdqp>0 && pqpi_ipbias = 0; ++ } ++ else ++ { ++ uqp = msb2->i_pupperq; ++ lqp = msb2->i_plowerq; ++ pqp = QP_LOWER+(msb2->i_imbase-msb2->i_margin)/msb2->i_degree; ++ dqp = qdelta((int)div_s64((int64)(msb2->i_imbits-msb2->i_imbase)*DQBIAS_FAC,msb2->i_radius)); ++ msb2->i_levelq = pqp; ++ msb2->i_budget = msb2->i_frmbit-msb2->i_ipbias; ++ msb2->i_budget = _MAX(msb2->i_budget,msb2->i_frmbit/16); ++ pqp = _MAX(_MIN(uqp,pqp+dqp),lqp); ++ if( lqp>(pqp-QP_DEGREE) && lqp>LQP_HW_LIMIT) ++ pqp = lqp + QP_DEGREE; ++ rqct->i_enc_qp = pqp; ++ tgt = msb2->i_budget/msb2->i_blocks; ++ uqp = _MIN(pqp+msb2->i_blkdqp,_MIN(lim,uqp)); ++ lqp = _MIN(_MAX(pqp-msb2->i_blkdqp,lqp), LQP_HW_LIMIT); ++ msb2->b_mbkadp = msb2->i_blkdqp>0 && pqpi_pictyp; ++ int delta = 0; ++ int init_frames = 0; ++ ++ if( rqcx->i_iperiod > 1 ) ++ { ++ // The number of P frames in GOP is not zero. ++ init_frames = 1; ++ } ++ ++ #if (CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES != 0 ) ++ init_frames = CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES; ++ #endif //CFG_VBV_SKIP_THE_FIRST_NUM_FRAMES ++ ++ // Target frame bitcount ++ if (msb2->i_frm_nr > init_frames) ++ { ++ int smooth_cnt = 0; ++ // 1. Determine the number of future frame to compensate for current bitrate mismatch. ++ smooth_cnt = _MAX(_msbr_get_smooth_count(msb2), 1); ++ ++ // 2. Calculate the bitcount that this frame should be compensate for. ++ delta = _msbr_calculate_delta( msb2, smooth_cnt, frm_type); ++ ++ // 3. Finally, calculate the target bitcount. ++ msb2->i_tgt_bs = msb2->m_bpf[frm_type] - delta; ++ ++ // 4. Clip the target size to 10% ~ 130% ++ msb2->i_tgt_bs = MSRC_FIT_IN_RANGE( msb2->i_tgt_bs ++ ,MSRC_PERCENT ( 10, msb2->m_bpf[frm_type]) ++ ,MSRC_PERCENT (130, msb2->m_bpf[frm_type])); ++ } ++ else ++ { ++ // The first I frame and the first P frame use the default value. ++ msb2->i_tgt_bs = msb2->m_bpf[frm_type]; ++ } ++ ++ MFE_DBG( "Qp = %d, tg %d <%d:%d> dt %d\n", rqcx->rqct.i_enc_qp , msb2->i_tgt_bs ++ , msb2->i_frm_nr, frm_type,delta); ++ msb2->i_last_avg_qs = 0; ++ tgt = (int)div_s64((int64)msb2->i_tgt_bs*256,msb2->i_pixels); ++ } ++ while(0); ++#endif ++ break; ++ } ++ mrqc_roi_draw(rqct, mjob); ++ msb2->b_mbkadp = msb2->b_mbkadp && !rqcx->attr.b_dqmstat; ++ regs->reg00_g_mbr_en = msb2->b_mbkadp; ++ regs->reg26_s_mbr_pqp_dlimit = LF_QP_DIFF_LIMIT; ++ regs->reg26_s_mbr_uqp_dlimit = UP_QP_DIFF_LIMIT; ++ regs->reg00_g_qscale = rqct->i_enc_qp; ++ regs->reg27_s_mbr_frame_qstep = qp2qs(rqct->i_enc_qp); ++ regs->reg26_s_mbr_tmb_bits = tgt>1 ? tgt : 1; ++ regs->reg2a_s_mbr_qp_min = lqp; ++ regs->reg2a_s_mbr_qp_max = uqp; ++ regs->reg6e_s_mbr_qstep_min = qp2qs(lqp); ++ regs->reg6f_s_mbr_qstep_max = qp2qs(uqp); ++ /* penalties of mbtypies */ ++ regs->regf2_g_i16pln_en = (0!=rqcx->attr.b_i16pln); ++ regs->reg87_g_intra4_penalty = rqcx->attr.i_peni4x; ++ regs->reg88_g_intra16_penalty = rqcx->attr.i_peni16; ++ regs->reg88_g_inter_penalty = rqcx->attr.i_penint; ++ regs->reg89_g_planar_penalty_luma = rqcx->attr.i_penYpl; ++ regs->reg89_g_planar_penalty_cbcr = rqcx->attr.i_penCpl; ++ return 0; ++} ++ ++#define BSP_DUR (32) ++ ++static int msb2_enc_done(rqct_ops* rqct, mhve_job* mjob) ++{ ++ mfe6_rqc* rqcx = (mfe6_rqc*)rqct; ++ msb2_rqc* msb2 = (msb2_rqc*)rqcx; ++ mfe6_reg* regs = (mfe6_reg*)mjob; ++ int bpp, cpx, bps, inc, dec, dur, avq = qp2qs(rqct->i_enc_qp), bcn = mjob->i_bits; ++ ++ rqct->i_bitcnt = mjob->i_bits; ++ rqct->i_enc_bs+= rqct->i_bitcnt/8; ++ rqct->i_enc_nr++; ++ ++ if (msb2->b_mbkadp) ++ avq = (avq + regs->enc_sumpqs)/msb2->i_blocks; ++ ++ regs->reg28 = regs->reg29 = 0; ++ regs->regf5 = regs->regf6 = 0; ++ regs->reg42 = regs->reg43 = 0; ++ ++ bpp = (int)div_s64((int64)rqct->i_bitcnt*BPP_FAC,msb2->i_pixels); ++ dur = rqcx->i_iperiod; ++ cpx = bpp * avq; ++ ++ if (IS_PPIC(rqct->i_pictyp)) ++ { ++ acc_push(&msb2->acc_bitcnt, bcn); ++ acc_push(&msb2->acc_rqprod, cpx); ++ iir_push(&msb2->iir_rqprod[RQCT_PICTYP_P], acc_calc(&msb2->acc_rqprod,8)/8); ++ msb2->i_errpro = (msb2->i_ipbias-msb2->i_frmbit+bcn); ++ msb2->i_imbits += msb2->i_errpro; ++ msb2->i_imbits = _MIN(msb2->i_imbits,msb2->i_upperb+msb2->i_radius); ++ msb2->i_imbits = _MAX(msb2->i_imbits,msb2->i_lowerb); ++ msb2->i_rebits = _MAX(msb2->i_rebits,msb2->i_imbits); ++ } ++ else ++ { ++ msb2->i_intrabit = bcn; ++ iir_push(&msb2->iir_rqprod[RQCT_PICTYP_I], cpx); ++ if (msb2->i_imbits > msb2->i_upperb) ++ msb2->i_rebits = msb2->i_imbits; ++ msb2->i_errpro = (msb2->i_rebits-msb2->i_imbits); ++ msb2->i_imbits += msb2->i_errpro; ++ if (dur >= 2) ++ msb2->i_ipbias = (bcn - msb2->i_frmbit) / (dur-1); ++ if (dur == 0) ++ acc_push(&msb2->acc_bitcnt, bcn); ++ } ++ msb2->i_rebits += (bcn - msb2->i_frmbit); ++ ++ if (dur > 0) ++ bps = acc_calc(&msb2->acc_bitcnt, dur-1) + msb2->i_intrabit; ++ else ++ bps = acc_calc(&msb2->acc_bitcnt, dur=BSP_DUR); ++ bps = (int)div_s64((int64)bps*msb2->n_fmrate,msb2->d_fmrate*dur); ++ ++ if (!rqcx->attr.b_logoff) ++ snprintf(rqct->print_line,RQCT_LINE_SIZE-1,"<%s#%04d@%c:%2d> bitcnt:%8d bps:%8d",\ ++ rqct->name,rqct->i_enc_nr%10000,rqct->i_pictyp==RQCT_PICTYP_I?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt,bps); ++#if 0 ++ // printk("%s\n",rqct->print_line); ++ printk("<%s#%04d@%c:%2d> bitcnt:%8d bps:%8d im:%8d df:%8d re:%8d\n",\ ++ rqct->name,rqct->i_enc_nr%10000,rqct->i_pictyp==RQCT_PICTYP_I?'I':'P',rqct->i_enc_qp,rqct->i_bitcnt,bps,msb2->i_imbits,msb2->i_imbase,msb2->i_rebits); ++#endif ++ bcn = msb2->i_imbits-msb2->i_imbase; ++ inc = msb2->i_frmbit/64; ++ dec = -3*inc; ++ bcn = _MIN(inc,_MAX(bcn,dec)); ++ msb2->i_imbase += bcn; ++ msb2->i_imbase = _MIN(_MAX(msb2->i_imbase,msb2->i_lowerb),msb2->i_upperb); ++ rqcx->i_refcnt++; ++ ++#if RC_MSBR ++ do ++ { ++ int frm_type; ++ frm_type = rqct->i_pictyp; ++ // update counter ++ msb2->i_frm_nr++; ++ ++ MFE_DBG( "conf i_vbv_fullness %d + bitcnt %d= ", msb2->i_vbv_fullness, rqct->i_bitcnt ); ++ ++ msb2->i_vbv_fullness += rqct->i_bitcnt; ++ msb2->i_vbv_real_fullness += rqct->i_bitcnt; ++ ++ MFE_DBG( "%d\n", msbr->i_vbv_fullness ); ++ ++ msb2->i_avg_qs = avq; ++ msb2->i_last_avg_qs = msb2->i_avg_qs; ++ // Variable bitrate ++ if (msb2->i_method == RQCT_MODE_VBR) ++ msb2->i_lt_qs64 += ((msb2->i_last_avg_qs*64)-msb2->i_lt_qs64) / msb2->i_frm_nr; ++ ++ /* Update VBV buffer status */ ++ ++ #if ( CFG_VBV_FRAME_QUOTA_METHOD == VFQ_USE_AVERAGE_SIZE ) ++ ++ MFE_DBG( "conf i_vbv_fullness %d - i_avgbpf %d= ", msb2->i_vbv_fullness, msb2->i_avgbpf ); ++ msb2->i_vbv_fullness -= msb2->i_avgbpf; ++ msb2->i_vbv_real_fullness -= msb2->i_avgbpf; ++ ++ #elif ( CFG_VBV_FRAME_QUOTA_METHOD == VFQ_USE_WEIGHTED_SIZE ) ++ ++ MFE_DBG( "conf i_vbv_fullness %d - i_avgbpf %d= ", msb2->i_vbv_fullness, msb2->m_bpf[frm_type] ); ++ msb2->i_vbv_fullness -= msb2->m_bpf[frm_type]; ++ msb2->i_vbv_real_fullness -= msb2->m_bpf[frm_type]; ++ ++ #else ++ ++ msb2->i_vbv_fullness -= msb2->i_avgbpf; ++ msb2->i_vbv_real_fullness -= msb2->i_avgbpf; ++ ++ #endif //VFQ_USE_WEIGHTED_SIZE ++ ++ MFE_DBG( "%d\n", msb2->i_vbv_fullness); ++ } ++ while(0); ++#endif ++ ++ return 0; ++} +diff --git a/drivers/mstar/mfev5/mmfe_ctx.c b/drivers/mstar/mfev5/mmfe_ctx.c +new file mode 100644 +index 00000000..ee998454 +--- /dev/null ++++ b/drivers/mstar/mfev5/mmfe_ctx.c +@@ -0,0 +1,1148 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++static int _mfectx_streamon(void* pctx, int on); ++static int _mfectx_enc_pict(void* pctx, mmfe_buff* buff); ++static int _mfectx_get_bits(void* pctx, mmfe_buff* buff); ++static int _mfectx_set_parm(void* pctx, mmfe_parm* parm); ++static int _mfectx_get_parm(void* pctx, mmfe_parm* parm); ++static int _mfectx_set_ctrl(void* pctx, mmfe_ctrl* ctrl); ++static int _mfectx_get_ctrl(void* pctx, mmfe_ctrl* ctrl); ++static int _mfectx_compress(void* pctx, mmfe_buff* buff); ++static int _mfectx_put_data(void* pctx, mmfe_buff* buff); ++static int _mfectx_set_rqcf(void* pctx, rqct_conf* rqcf); ++static int _mfectx_get_rqcf(void* pctx, rqct_conf* rqcf); ++static void _mfectx_release(void* pctx) ++{ ++ mmfe_ctx* mctx = pctx; ++ if (atomic_dec_and_test(&mctx->i_refcnt)) ++ { ++ mhve_ops* mops = mctx->p_handle; ++ while (mctx->i_dmems > 0) ++ msys_release_dmem(&mctx->m_dmems[--mctx->i_dmems]); ++ mutex_lock(&mctx->m_stream); ++ mctx->p_handle = NULL; ++ if (mops) ++ { ++ if (mops->release) ++ mops->release(mops); ++ kfree(mops); ++ mctx->p_handle = NULL; ++ } ++ mutex_unlock(&mctx->m_stream); ++#if MMFE_TIMER_SIZE>0 ++ if (mctx->p_timer) ++ { ++ kfree(mctx->p_timer); ++ mctx->p_timer = NULL; ++ } ++#endif ++ if (mctx->p_usrdt) ++ { ++ kfree(mctx->p_usrdt); ++ mctx->p_usrdt = NULL; ++ } ++ kfree(mctx); ++ } ++} ++static void _mfectx_adduser(void* pctx) ++{ ++ mmfe_ctx* mctx = pctx; ++ atomic_inc(&mctx->i_refcnt); ++} ++ ++void* mmfeops_acquire(int); ++ ++mmfe_ctx* ++mmfectx_acquire( ++ mmfe_dev* mdev) ++{ ++ mmfe_ctx* mctx = NULL; ++ mhve_ops* mops = NULL; ++ ++ if (!mdev || !(mctx = kzalloc(sizeof(mmfe_ctx), GFP_KERNEL))) ++ { ++ printk(KERN_ERR"%s() alloc fail\n", __func__); ++ return mctx; ++ } ++ ++ mctx->p_usrdt = NULL; ++ do ++ { ++ if (!(mops = mmfeops_acquire(mdev->i_rctidx))) ++ break; ++ if (!(mctx->p_usrdt = kzalloc(MMFE_USER_DATA_SIZE, GFP_KERNEL))) ++ break; ++#if MMFE_TIMER_SIZE>0 ++ mctx->p_timer = kzalloc(MMFE_TIMER_SIZE, GFP_KERNEL); ++ mctx->i_numbr = 0; ++#endif ++ mutex_init(&mctx->m_stream); ++ mutex_init(&mctx->m_encode); ++ mctx->i_state = MMFE_CTX_STATE_NULL; ++ mctx->release =_mfectx_release; ++ mctx->adduser =_mfectx_adduser; ++ atomic_set(&mctx->i_refcnt, 1); ++ mctx->p_handle = mops; ++ mctx->i_strid = STREAM_ID_DEFAULT; ++ return mctx; ++ } ++ while (0); ++ ++ if (mctx->p_usrdt) ++ { ++ kfree(mctx->p_usrdt); ++ mctx->p_usrdt = NULL; ++ } ++ if (mops) ++ { ++ if (mops->release) ++ mops->release(mops); ++ kfree(mops); ++ mctx->p_handle = NULL; ++ } ++ if (mctx) ++ { ++ kfree(mctx); ++ mctx = NULL; ++ } ++ return mctx; ++} ++ ++long ++mmfectx_actions( ++ mmfe_ctx* mctx, ++ unsigned int cmd, ++ void* arg) ++{ ++ int err = 0; ++ switch (cmd) ++ { ++ case IOCTL_MMFE_S_PARM: ++ err = _mfectx_set_parm(mctx, (mmfe_parm*)arg); ++ break; ++ case IOCTL_MMFE_G_PARM: ++ err = _mfectx_get_parm(mctx, (mmfe_parm*)arg); ++ break; ++ case IOCTL_MMFE_STREAMON: ++ err = _mfectx_streamon(mctx, 1); ++ break; ++ case IOCTL_MMFE_STREAMOFF: ++ err = _mfectx_streamon(mctx, 0); ++ break; ++ case IOCTL_MMFE_S_PICT: ++ err = _mfectx_enc_pict(mctx, (mmfe_buff*)arg); ++ break; ++ case IOCTL_MMFE_G_BITS: ++ err = _mfectx_get_bits(mctx, (mmfe_buff*)arg); ++ break; ++ case IOCTL_MMFE_S_CTRL: ++ err = _mfectx_set_ctrl(mctx, (mmfe_ctrl*)arg); ++ break; ++ case IOCTL_MMFE_G_CTRL: ++ err = _mfectx_get_ctrl(mctx, (mmfe_ctrl*)arg); ++ break; ++ case IOCTL_MMFE_ENCODE: ++ err = _mfectx_compress(mctx, (mmfe_buff*)arg); ++ break; ++ case IOCTL_MMFE_S_DATA: ++ err = _mfectx_put_data(mctx, (mmfe_buff*)arg); ++ break; ++ case IOCTL_RQCT_S_CONF: ++ err = _mfectx_set_rqcf(mctx, (rqct_conf*)arg); ++ break; ++ case IOCTL_RQCT_G_CONF: ++ err = _mfectx_get_rqcf(mctx, (rqct_conf*)arg); ++ break; ++ default: ++ err = -EINVAL; ++ break; ++ } ++ return (long)err; ++} ++ ++#define _ALIGN_(b,a) (((a)+(1<<(b))-1)&(~((1<<(b))-1))) ++ ++#define MBPIXELS_Y 256 ++#define MBPIXELS_C (MBPIXELS_Y/2) ++#define MBGNDATA 128 ++#define MBROWMAX 168 //(2688/16) ++ ++static int ++_mfectx_streamon( ++ void* pctx, ++ int on) ++{ ++ mmfe_ctx* mctx = pctx; ++ mmfe_dev* mdev = mctx->p_device; ++ mhve_ops* mops = mctx->p_handle; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ mhve_cfg mcfg; ++ rqct_cfg rqcf; ++ int i, err = 0; ++ ++ mutex_lock(&mctx->m_stream); ++ do ++ if (on) ++ { ++ int size_out, size_mbs, size_mbp, size_dqm; ++ int size_lum, size_chr, mbw, mbh, mbn; ++ int score, rpbn; ++ uint addr; ++ char*kptr; ++ msys_mem* pdmem; ++ if (MMFE_CTX_STATE_NULL != mctx->i_state) ++ break; ++ mctx->i_dmems = 0; ++ mcfg.type = MHVE_CFG_RES; ++ mops->get_conf(mops, &mcfg); ++ mbw = _ALIGN_(4,mcfg.res.i_pixw)/16; ++ mbh = _ALIGN_(4,mcfg.res.i_pixh)/16; ++ mbn = mbw*mbh; ++ /* calculate required buffer size */ ++ size_mbp = _ALIGN_( 8,MBROWMAX*MBGNDATA); ++ size_dqm = _ALIGN_( 8,(mbn+1)/2+16); ++ size_mbs = size_mbp + size_dqm; ++ size_lum = _ALIGN_( 8,mbn*MBPIXELS_Y); ++ size_chr = _ALIGN_( 8,mbn*MBPIXELS_C); ++ size_out = _ALIGN_(12,size_lum); ++ if (mctx->i_omode == MMFE_OMODE_MMAP) ++ size_out = 0; ++ /* intermediate parameters */ ++ rpbn = mcfg.res.i_rpbn; ++ do ++ { /* output-mode */ ++ mctx->p_ovptr = NULL; ++ mctx->u_ophys = 0; ++ mctx->i_osize = mctx->i_ormdr = 0; ++ if (size_out > 0) ++ { ++ pdmem = &mctx->m_dmems[mctx->i_dmems++]; ++ snprintf(pdmem->name, 15, "S%d:MFEDMBS", mctx->i_index); ++ pdmem->length = size_out; ++ if (0 != (err = msys_request_dmem(pdmem))) ++ break; ++ addr = Chip_Phys_to_MIU(pdmem->phys); ++ kptr = (char*)(uintptr_t)pdmem->kvirt; ++ mcfg.type = MHVE_CFG_DMA; ++ mcfg.dma.i_dmem = MHVE_CFG_DMA_OUTPUT_BUFFER; ++ mcfg.dma.p_vptr = kptr; ++ mcfg.dma.u_phys = addr; ++ mcfg.dma.i_size[0] = size_out; ++ mops->set_conf(mops, &mcfg); ++ mctx->p_ovptr = kptr; ++ mctx->u_ophys = addr; ++ mctx->i_osize = size_out; ++ } ++ pdmem = &mctx->m_dmems[mctx->i_dmems++]; ++ if (mctx->i_strid == STREAM_ID_DEFAULT) ++ { ++ snprintf(pdmem->name, 15, "S%d:MFEDMMB", mctx->i_index); ++ } ++ else ++ { ++ /* encoder buffer name alignment */ ++ snprintf(pdmem->name, 15, "S%d:VENCDMOUT", mctx->i_strid); ++ } ++ pdmem->length = size_mbs; ++ if (0 != (err = msys_request_dmem(pdmem))) ++ break; ++ addr = Chip_Phys_to_MIU(pdmem->phys); ++ kptr = (char*)(uintptr_t)pdmem->kvirt; ++ /* Q-Map allocate memory */ ++ rqcf.type = RQCT_CFG_DQM; ++ rqcf.dqm.u_phys = addr; addr += size_dqm; ++ rqcf.dqm.p_kptr = kptr; ++ rqcf.dqm.i_dqmw = mbw; ++ rqcf.dqm.i_dqmh = mbh; ++ rqcf.dqm.i_size = size_dqm; ++ rqct->set_rqcf(rqct, &rqcf); ++ /* mb-row: GN data */ ++ mcfg.type = MHVE_CFG_DMA; ++ mcfg.dma.i_dmem = MHVE_CFG_DMA_NALU_BUFFER; ++ mcfg.dma.u_phys = addr; ++ mcfg.dma.p_vptr = NULL; ++ mcfg.dma.i_size[0] = size_mbp; ++ mops->set_conf(mops, &mcfg); ++ /* ref/rec picture buffers */ ++ if (mctx->i_imode == MMFE_IMODE_PURE) ++ { ++ /* create internal buffer for reconstruct */ ++ for (i = 0; i < rpbn; i++) ++ { ++ pdmem = &mctx->m_dmems[mctx->i_dmems++]; ++ pdmem->length = size_lum + size_chr; ++ if (mctx->i_strid == STREAM_ID_DEFAULT) ++ { ++ snprintf(pdmem->name, 15, "S%d:MFEDMP%d", mctx->i_index, i); ++ } ++ else ++ { ++ /* encoder buffer name alignment */ ++ snprintf(pdmem->name, 15, "S%d:VENCDMP%d", mctx->i_strid, i); ++ } ++ if (0 != (err = msys_request_dmem(pdmem))) ++ break; ++ addr = Chip_Phys_to_MIU(pdmem->phys); ++ mcfg.type = MHVE_CFG_DMA; ++ mcfg.dma.i_dmem = i; ++ mcfg.dma.u_phys = addr; ++ mcfg.dma.p_vptr = NULL; ++ mcfg.dma.i_size[0] = size_lum; ++ mcfg.dma.i_size[1] = size_chr; ++ mops->set_conf(mops, &mcfg); ++ } ++ } ++ else if (mctx->i_imode == MMFE_IMODE_PLUS) ++ { ++ /* use input buffer as reconstruct buffer */ ++ for (i = 0; i < rpbn; i++) ++ { ++ mcfg.type = MHVE_CFG_DMA; ++ mcfg.dma.i_dmem = i; ++ mcfg.dma.u_phys = 0; ++ mcfg.dma.p_vptr = NULL; ++ mcfg.dma.i_size[0] = 0; ++ mcfg.dma.i_size[1] = 0; ++ mops->set_conf(mops, &mcfg); ++ } ++ } ++ rqcf.type = RQCT_CFG_FPS; ++ rqct->get_rqcf(rqct, &rqcf); ++ score = mbn; ++ score *= (int)rqcf.fps.n_fps; ++ score /= (int)rqcf.fps.d_fps; ++ mctx->i_score = score; ++ } ++ while (0); ++ ++ if (!err && !(err = mops->seq_sync(mops))) ++ { ++ mops->seq_conf(mops); ++ mmfedev_poweron(mdev, mctx->i_score); ++ mdev->i_counts[mctx->i_index][0] = mdev->i_counts[mctx->i_index][1] = 0; ++ mdev->i_counts[mctx->i_index][2] = mdev->i_counts[mctx->i_index][3] = 0; ++ mdev->i_counts[mctx->i_index][4] = 0; ++ mctx->i_state = MMFE_CTX_STATE_IDLE; ++ break; ++ } ++ } ++ else ++ { ++ if (MMFE_CTX_STATE_NULL == mctx->i_state) ++ break; ++ mmfedev_poweron(mdev,-mctx->i_score); ++ mctx->i_state = MMFE_CTX_STATE_NULL; ++ mctx->i_score = 0; ++ mops->seq_done(mops); ++#if 0 ++ printk("<%d>mfe performance:\n",mctx->i_index); ++ for (i = 0; i < MMFE_TIMER_SIZE/8; i++) ++ printk("<%d>%4d/%4d/%8d\n",mctx->i_index,mctx->p_timer[i].tm_dur[0],mctx->p_timer[i].tm_dur[1],mctx->p_timer[i].tm_cycles); ++#endif ++ } ++ while (0); ++ ++ if (!on || err) ++ { ++ while (mctx->i_dmems > 0) ++ msys_release_dmem(&mctx->m_dmems[--mctx->i_dmems]); ++ } ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++#define SEMI420(f) ((f)>=MHVE_PIX_NV12&&(f)<=MHVE_PIX_NV21) ++#define PACK422(f) ((f)>=MHVE_PIX_YUYV&&(f)<=MHVE_PIX_YVYU) ++#define MMFE_FLAGS_CONTROL (MMFE_FLAGS_IDR|MMFE_FLAGS_DISPOSABLE|MMFE_FLAGS_NIGHT_MODE) ++ ++static int ++_mfectx_enc_pict( ++ void* pctx, ++ mmfe_buff* buff) ++{ ++ int err = -EINVAL; ++ int pitch = 0; ++ mmfe_ctx* mctx = pctx; ++ mmfe_dev* mdev = mctx->p_device; ++ mhve_ops* mops = mctx->p_handle; ++ mhve_cpb* pcpb = mctx->m_mcpbs; ++ ++ if (buff->i_memory != MMFE_MEMORY_MMAP) ++ return -EINVAL; ++ pitch = buff->i_stride; ++ if (pitch < buff->i_width) ++ pitch = buff->i_width; ++ ++ mutex_lock(&mctx->m_stream); ++ do ++ if (MMFE_CTX_STATE_IDLE == mctx->i_state && MMFE_OMODE_USER == mctx->i_omode) ++ { ++ mhve_vpb mvpb; ++ mhve_cfg mcfg; ++ ++ mcfg.type = MHVE_CFG_RES; ++ mops->get_conf(mops, &mcfg); ++ if (buff->i_planes != 2 && (MHVE_PIX_NV21 >= mcfg.res.e_pixf)) ++ break; ++ if (buff->i_planes != 1 && (MHVE_PIX_YUYV <= mcfg.res.e_pixf)) ++ break; ++ if (mcfg.res.i_pixw != buff->i_width || mcfg.res.i_pixh != buff->i_height) ++ break; ++ ++ mvpb.i_index = buff->i_index; ++ mvpb.i_stamp = buff->i_timecode; ++ mvpb.u_flags = buff->i_flags&MMFE_FLAGS_CONTROL; ++ mvpb.i_pitch = pitch; ++ mvpb.planes[1].u_phys = 0; ++ mvpb.planes[1].i_bias = 0; ++ mvpb.planes[0].u_phys = buff->planes[0].mem.phys; ++ mvpb.planes[0].i_bias = buff->planes[0].i_bias; ++ if (mcfg.res.e_pixf <= MHVE_PIX_NV21) ++ { ++ mvpb.planes[1].u_phys = buff->planes[1].mem.phys; ++ mvpb.planes[1].i_bias = buff->planes[1].i_bias; ++ } ++ ++ mctx->i_state = MMFE_CTX_STATE_BUSY; ++ if (!(err = mops->enc_buff(mops, &mvpb))) ++ do ++ { ++ mops->put_data(mops, mctx->p_usrdt, mctx->i_usrsz); ++ mops->enc_conf(mops); ++ mmfedev_pushjob(mdev, mctx); ++ } ++ while (0 < (err = mops->enc_done(mops))); ++ ++ if (!err) ++ { ++ mctx->i_usrcn = mctx->i_usrsz = 0; ++ pcpb->i_index = -1; ++ } ++ ++ mctx->i_ormdr = ++ err = ++ mops->out_buff(mops, mctx->m_mcpbs); ++ } ++ while (0); ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_get_bits( ++ void* pctx, ++ mmfe_buff* buff) ++{ ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ int err = -ENODATA; ++ ++ if (buff->i_memory != MMFE_MEMORY_USER || buff->i_planes != 1) ++ return -EINVAL; ++ ++ mutex_lock(&mctx->m_stream); ++ if (MMFE_CTX_STATE_BUSY == mctx->i_state && MMFE_OMODE_USER == mctx->i_omode) ++ { ++ int flags = 0; ++ int rmdr = mctx->i_ormdr; ++ int size = mctx->m_mcpbs->planes[0].i_size; ++ char* ptr = mctx->p_ovptr + size - rmdr; ++ ++ if (rmdr == size) ++ flags = MMFE_FLAGS_SOP; ++ if (buff->planes[0].i_size < rmdr) ++ rmdr = buff->planes[0].i_size; ++ buff->i_flags = 0; ++ if (copy_to_user(buff->planes[0].mem.uptr, ptr, rmdr)) ++ err = -EFAULT; ++ else ++ { ++ buff->planes[0].i_used = rmdr; ++ buff->i_timecode = mctx->m_mcpbs->i_stamp; ++ mctx->i_ormdr -= rmdr; ++ err = 0; ++ } ++ if (0 == mctx->i_ormdr) ++ { ++ mctx->i_state = MMFE_CTX_STATE_IDLE; ++ flags |= MMFE_FLAGS_EOP; ++ mops->out_buff(mops, mctx->m_mcpbs); ++ } ++ if (!err) ++ buff->i_flags = flags|(mctx->m_mcpbs->i_flags&MMFE_FLAGS_CONTROL); ++ } ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_set_parm( ++ void* pctx, ++ mmfe_parm* parm) ++{ ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ int err = -EINVAL; ++ ++ mutex_lock(&mctx->m_stream); ++ if (mctx->i_state == MMFE_CTX_STATE_NULL) ++ { ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ mhve_cfg mcfg; ++ rqct_cfg rqcf; ++ unsigned char b_long_term_reference; ++ switch (parm->type) ++ { ++ case MMFE_PARM_RES: ++ /* check LTR mode */ ++ mcfg.type = MHVE_CFG_LTR; ++ err = mops->get_conf(mops, &mcfg); ++ b_long_term_reference = mcfg.ltr.b_long_term_reference; ++ if ((unsigned)parm->res.i_pixfmt > MMFE_PIXFMT_YUYV) ++ break; ++ if ((parm->res.i_pict_w%16) || (parm->res.i_pict_h%8)) ++ break; ++ mctx->i_max_w = _ALIGN_(4,parm->res.i_pict_w); ++ mctx->i_max_h = _ALIGN_(4,parm->res.i_pict_h); ++ //TODO: add stream id ++ mctx->i_strid = parm->res.i_strid; ++ mcfg.type = MHVE_CFG_RES; ++ mcfg.res.e_pixf = parm->res.i_pixfmt; ++ mcfg.res.i_pixw = parm->res.i_pict_w; ++ mcfg.res.i_pixh = parm->res.i_pict_h; ++ /* recn buffer number depend on LTR mode */ ++ if (b_long_term_reference) ++ mcfg.res.i_rpbn = 3; ++ else ++ mcfg.res.i_rpbn = 2; ++ mcfg.res.u_conf = 0; ++ mctx->i_omode = MMFE_OMODE_USER; ++ mctx->i_imode = MMFE_IMODE_PURE; ++ if (parm->res.i_outlen < 0) ++ mctx->i_omode = MMFE_OMODE_MMAP; ++ if (parm->res.i_outlen <-1) ++ mctx->i_imode = MMFE_IMODE_PLUS; ++ mops->set_conf(mops, &mcfg); ++ rqcf.type = RQCT_CFG_RES; ++ rqcf.res.i_picw = mctx->i_max_w; ++ rqcf.res.i_pich = mctx->i_max_h; ++ rqct->set_rqcf(rqct, &rqcf); ++ err = 0; ++ break; ++ case MMFE_PARM_FPS: ++ if (parm->fps.i_num > 0 && parm->fps.i_den > 0) ++ { ++ rqcf.type = RQCT_CFG_FPS; ++ rqcf.fps.n_fps = parm->fps.i_num; ++ rqcf.fps.d_fps = parm->fps.i_den; ++ rqct->set_rqcf(rqct, &rqcf); ++ err = 0; ++ } ++ break; ++ case MMFE_PARM_MOT: ++ mcfg.type = MHVE_CFG_MOT; ++ mcfg.mot.i_subp = parm->mot.i_subpel; ++ mcfg.mot.i_dmvx = _MIN(_MAX(8,parm->mot.i_dmv_x),32); ++ mcfg.mot.i_dmvy = parm->mot.i_dmv_y<=8?8:16; ++ mcfg.mot.i_blkp[0] = parm->mot.i_mvblks[0]; ++ mcfg.mot.i_blkp[1] = 0; ++ err = mops->set_conf(mops, &mcfg); ++ break; ++ case MMFE_PARM_BPS: ++ if ((unsigned)parm->bps.i_method > RQCT_METHOD_VBR) ++ break; ++ rqcf.type = RQCT_CONF_SEQ; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ rqcf.seq.i_method = parm->bps.i_method; ++ rqcf.seq.i_btrate = parm->bps.i_bps; ++ rqcf.seq.i_leadqp = parm->bps.i_ref_qp; ++ err = rqct->set_rqcf(rqct, &rqcf); ++ } ++ break; ++ case MMFE_PARM_GOP: ++ if (parm->gop.i_pframes < 0) ++ break; ++ rqcf.type = RQCT_CONF_SEQ; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ rqcf.seq.i_period = parm->gop.i_pframes+1; ++ if (!rqct->set_rqcf(rqct, &rqcf)) ++ err = 0; ++ } ++ break; ++ case MMFE_PARM_AVC: ++ mcfg.type = MHVE_CFG_AVC; ++ mcfg.avc.i_profile = parm->avc.i_profile; ++ mcfg.avc.i_level = parm->avc.i_level; ++ mcfg.avc.i_num_ref_frames = parm->avc.i_num_ref_frames; ++ mcfg.avc.i_poc_type = parm->avc.i_poc_type; ++ mcfg.avc.b_entropy_coding_type = parm->avc.b_cabac; ++ mcfg.avc.b_constrained_intra_pred = parm->avc.b_constrained_intra_pred; ++ mcfg.avc.b_deblock_filter_control = parm->avc.b_deblock_filter_control; ++ mcfg.avc.i_disable_deblocking_idc = parm->avc.i_disable_deblocking_idc; ++ mcfg.avc.i_alpha_c0_offset = parm->avc.i_alpha_c0_offset; ++ mcfg.avc.i_beta_offset = parm->avc.i_beta_offset; ++ err = mops->set_conf(mops, &mcfg); ++ break; ++ case MMFE_PARM_VUI: ++ mcfg.type = MHVE_CFG_VUI; ++ mcfg.vui.b_video_full_range = parm->vui.b_video_full_range != 0; ++ mcfg.vui.b_timing_info_pres = parm->vui.b_timing_info_pres != 0; ++ err = mops->set_conf(mops, &mcfg); ++ break; ++ case MMFE_PARM_LTR: ++ mcfg.type = MHVE_CFG_LTR; ++ mcfg.ltr.b_long_term_reference = parm->ltr.b_long_term_reference; ++ mcfg.ltr.b_enable_pred = parm->ltr.b_enable_pred; ++ err = mops->set_conf(mops, &mcfg); ++ b_long_term_reference = mcfg.ltr.b_long_term_reference; ++ /* Set recn buffer depend on LTR mode */ ++ mcfg.type = MHVE_CFG_RES; ++ if (!mops->get_conf(mops, &mcfg)) ++ { ++ mcfg.res.i_rpbn = b_long_term_reference ? 3 : 2; ++ err = mops->set_conf(mops, &mcfg); ++ } ++ /* RQCT control LTR P-frame period */ ++ rqcf.type = RQCT_CFG_LTR; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ rqcf.ltr.i_period = b_long_term_reference ? parm->ltr.i_ltr_period : 0; ++ err = rqct->set_rqcf(rqct, &rqcf); ++ } ++ break; ++ default: ++ printk("unsupported config\n"); ++ break; ++ } ++ } ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_get_parm( ++ void* pctx, ++ mmfe_parm* parm) ++{ ++ int err = 0; ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ mhve_cfg mcfg; ++ rqct_cfg rqcf; ++ ++ mutex_lock(&mctx->m_stream); ++ switch (parm->type) ++ { ++ case MMFE_PARM_IDX: ++ parm->idx.i_stream = mctx->i_index; ++ break; ++ case MMFE_PARM_RES: ++ mcfg.type = MHVE_CFG_RES; ++ mops->get_conf(mops, &mcfg); ++ parm->res.i_pict_w = mctx->i_max_w; ++ parm->res.i_pict_h = mctx->i_max_h; ++ parm->res.i_strid = mctx->i_strid; ++ parm->res.i_pixfmt = mcfg.res.e_pixf; ++ parm->res.i_outlen = 0; ++ parm->res.i_flags = 0; ++ break; ++ case MMFE_PARM_FPS: ++ rqcf.type = RQCT_CFG_FPS; ++ if (!(err = rqct->get_rqcf(rqct, &rqcf))) ++ { ++ parm->fps.i_num = (int)rqcf.fps.n_fps; ++ parm->fps.i_den = (int)rqcf.fps.d_fps; ++ } ++ break; ++ case MMFE_PARM_MOT: ++ mcfg.type = MHVE_CFG_MOT; ++ mops->get_conf(mops, &mcfg); ++ parm->mot.i_dmv_x = mcfg.mot.i_dmvx; ++ parm->mot.i_dmv_y = mcfg.mot.i_dmvy; ++ parm->mot.i_subpel= mcfg.mot.i_subp; ++ parm->mot.i_mvblks[0] = mcfg.mot.i_blkp[0]; ++ parm->mot.i_mvblks[1] = 0; ++ break; ++ case MMFE_PARM_BPS: ++ case MMFE_PARM_GOP: ++ rqcf.type = RQCT_CONF_SEQ; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ if (parm->type == MMFE_PARM_BPS) ++ { ++ parm->bps.i_method = rqcf.seq.i_method; ++ parm->bps.i_ref_qp = rqcf.seq.i_leadqp; ++ parm->bps.i_bps = rqcf.seq.i_btrate; ++ } ++ else ++ { ++ parm->gop.i_pframes = rqcf.seq.i_period-1; ++ parm->gop.i_bframes = 0; ++ } ++ } ++ break; ++ case MMFE_PARM_AVC: ++ mcfg.type = MHVE_CFG_AVC; ++ if (!(err = mops->get_conf(mops, &mcfg))) ++ { ++ parm->avc.i_profile = mcfg.avc.i_profile; ++ parm->avc.i_level = mcfg.avc.i_level; ++ parm->avc.i_num_ref_frames = mcfg.avc.i_num_ref_frames; ++ parm->avc.i_poc_type = mcfg.avc.i_poc_type; ++ parm->avc.b_cabac = mcfg.avc.b_entropy_coding_type; ++ parm->avc.b_deblock_filter_control = mcfg.avc.b_deblock_filter_control; ++ parm->avc.b_constrained_intra_pred = mcfg.avc.b_constrained_intra_pred; ++ parm->avc.i_disable_deblocking_idc = mcfg.avc.i_disable_deblocking_idc; ++ parm->avc.i_alpha_c0_offset = mcfg.avc.i_alpha_c0_offset; ++ parm->avc.i_beta_offset = mcfg.avc.i_beta_offset; ++ } ++ break; ++ case MMFE_PARM_VUI: ++ mcfg.type = MHVE_CFG_VUI; ++ if (!(err = mops->get_conf(mops, &mcfg))) ++ { ++ parm->vui.b_video_full_range = 0!=mcfg.vui.b_video_full_range; ++ parm->vui.b_timing_info_pres = 0!=mcfg.vui.b_timing_info_pres; ++ } ++ break; ++ case MMFE_PARM_LTR: ++ mcfg.type = MHVE_CFG_LTR; ++ if (!(err = mops->get_conf(mops, &mcfg))) ++ { ++ parm->ltr.b_long_term_reference = mcfg.ltr.b_long_term_reference; ++ if (mcfg.ltr.b_long_term_reference) ++ { ++ rqcf.type = RQCT_CFG_LTR; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ parm->ltr.i_ltr_period = rqcf.ltr.i_period; ++ } ++ parm->ltr.b_enable_pred = mcfg.ltr.b_enable_pred; ++ } ++ else ++ { ++ parm->ltr.i_ltr_period = 0; ++ parm->ltr.b_enable_pred = 0; ++ } ++ } ++ break; ++ default: ++ printk("unsupported config\n"); ++ break; ++ } ++ mutex_unlock(&mctx->m_stream); ++ return err; ++} ++ ++static int ++_mfectx_set_ctrl( ++ void* pctx, ++ mmfe_ctrl* ctrl) ++{ ++ int err = -EINVAL; ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ rqct_cfg rqcf; ++ mhve_cfg mcfg; ++ ++ mutex_lock(&mctx->m_stream); ++ if (mctx->i_state > MMFE_CTX_STATE_NULL) ++ switch (ctrl->type) ++ { ++ case MMFE_CTRL_ROI: ++ if (ctrl->roi.i_index >= RQCT_ROI_NR || ctrl->roi.i_index < -1) ++ break; ++ rqcf.type = RQCT_CFG_ROI; ++ rqcf.roi.i_roiidx = ctrl->roi.i_index; ++ err = 0; ++ if ((unsigned)(ctrl->roi.i_dqp + 15) > 30) ++ { ++ rqcf.roi.i_roidqp = 0; ++ rqct->set_rqcf(rqct, &rqcf); ++ break; ++ } ++ rqcf.roi.i_roidqp = ctrl->roi.i_dqp; ++ rqcf.roi.i_posx = ctrl->roi.i_mbx; ++ rqcf.roi.i_posy = ctrl->roi.i_mby; ++ rqcf.roi.i_recw = ctrl->roi.i_mbw; ++ rqcf.roi.i_rech = ctrl->roi.i_mbh; ++ rqct->set_rqcf(rqct, &rqcf); ++ break; ++ case MMFE_CTRL_SPL: ++ mcfg.type = MHVE_CFG_SPL; ++ mcfg.spl.i_rows = ctrl->spl.i_rows; ++ mcfg.spl.i_bits = ctrl->spl.i_bits; ++ mops->set_conf(mops, &mcfg); ++ err = 0; ++ break; ++ case MMFE_CTRL_SEQ: ++ if ((unsigned)ctrl->seq.i_pixfmt <= MMFE_PIXFMT_YVYU && ++ ctrl->seq.i_pixelw >= 128 && ++ ctrl->seq.i_pixelh >= 128 && ++ ctrl->seq.d_fps > 0 && ++ ctrl->seq.n_fps > 0) ++ { ++ int mbw, mbh, mbn; ++ mcfg.type = MHVE_CFG_RES; ++ mops->get_conf(mops, &mcfg); ++ mcfg.res.e_pixf = ctrl->seq.i_pixfmt; ++ mcfg.res.i_pixw = ctrl->seq.i_pixelw; ++ mcfg.res.i_pixh = ctrl->seq.i_pixelh; ++ if ((err = mops->set_conf(mops, &mcfg))) ++ break; ++ rqcf.type = RQCT_CFG_FPS; ++ rqcf.fps.n_fps = (short)ctrl->seq.n_fps; ++ rqcf.fps.d_fps = (short)ctrl->seq.d_fps; ++ if ((err = rqct->set_rqcf(rqct, &rqcf))) ++ break; ++ mbw = _ALIGN_(4,mcfg.res.i_pixw)>>4; ++ mbh = _ALIGN_(4,mcfg.res.i_pixh)>>4; ++ mbn = mbw*mbh; ++ rqcf.type = RQCT_CFG_RES; ++ rqcf.res.i_picw = (short)(mbw*16); ++ rqcf.res.i_pich = (short)(mbh*16); ++ if ((err = rqct->set_rqcf(rqct, &rqcf))) ++ break; ++ /* disable ROI */ ++ rqcf.type = RQCT_CFG_ROI; ++ rqcf.roi.i_roiidx = -1; ++ rqct->set_rqcf(rqct, &rqcf); ++ /* reset dqm */ ++ rqcf.type = RQCT_CFG_DQM; ++ rqct->get_rqcf(rqct, &rqcf); ++ rqcf.dqm.i_dqmw = mbw; ++ rqcf.dqm.i_dqmh = mbh; ++ rqcf.dqm.i_size = _ALIGN_(8,(mbn+1)/2+16); ++ rqct->set_rqcf(rqct, &rqcf); ++ err = 0; ++ } ++ break; ++ case MMFE_CTRL_LTR: ++ /* MUST set param first(can't open LTR mode after streamon) */ ++ mcfg.type = MHVE_CFG_LTR; ++ err = mops->get_conf(mops, &mcfg); ++ /* RQCT control LTR P-frame period */ ++ if (mcfg.ltr.b_long_term_reference) ++ { ++ mcfg.ltr.b_enable_pred = ctrl->ltr.b_enable_pred; ++ err = mops->set_conf(mops, &mcfg); ++ rqcf.type = RQCT_CFG_LTR; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ rqcf.ltr.i_period = ctrl->ltr.i_ltr_period; ++ if (!rqct->set_rqcf(rqct, &rqcf)) ++ err = 0; ++ } ++ } ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_get_ctrl( ++ void* pctx, ++ mmfe_ctrl* ctrl) ++{ ++ int err = -EINVAL; ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ rqct_cfg rqcf; ++ mhve_cfg mcfg; ++ ++ mutex_lock(&mctx->m_stream); ++ if (mctx->i_state > MMFE_CTX_STATE_NULL) ++ switch (ctrl->type) ++ { ++ case MMFE_CTRL_ROI: ++ rqcf.type = RQCT_CFG_ROI; ++ rqct->get_rqcf(rqct, &rqcf); ++ ctrl->roi.i_dqp = rqcf.roi.i_roidqp; ++ ctrl->roi.i_mbx = rqcf.roi.i_posx; ++ ctrl->roi.i_mby = rqcf.roi.i_posy; ++ ctrl->roi.i_mbw = rqcf.roi.i_recw; ++ ctrl->roi.i_mbh = rqcf.roi.i_rech; ++ err = 0; ++ break; ++ case MMFE_CTRL_SPL: ++ mcfg.type = MHVE_CFG_SPL; ++ mops->get_conf(mops, &mcfg); ++ ctrl->spl.i_rows = mcfg.spl.i_rows; ++ ctrl->spl.i_bits = mcfg.spl.i_bits; ++ err = 0; ++ break; ++ case MMFE_CTRL_SEQ: ++ mcfg.type = MHVE_CFG_RES; ++ mops->get_conf(mops, &mcfg); ++ ctrl->seq.i_pixelw = mcfg.res.i_pixw; ++ ctrl->seq.i_pixelh = mcfg.res.i_pixh; ++ ctrl->seq.i_pixfmt = mcfg.res.e_pixf; ++ rqcf.type = RQCT_CFG_FPS; ++ rqct->get_rqcf(rqct, &rqcf); ++ ctrl->seq.n_fps = (int)rqcf.fps.n_fps; ++ ctrl->seq.d_fps = (int)rqcf.fps.d_fps; ++ err = 0; ++ break; ++ case MMFE_CTRL_LTR: ++ mcfg.type = MHVE_CFG_LTR; ++ err = mops->get_conf(mops, &mcfg); ++ /* RQCT control LTR P-frame period */ ++ if (mcfg.ltr.b_long_term_reference) ++ { ++ ctrl->ltr.b_enable_pred = mcfg.ltr.b_enable_pred; ++ rqcf.type = RQCT_CFG_LTR; ++ if (!rqct->get_rqcf(rqct, &rqcf)) ++ { ++ ctrl->ltr.i_ltr_period = rqcf.ltr.i_period; ++ } ++ } ++ else ++ { ++ ctrl->ltr.b_enable_pred = 0; ++ ctrl->ltr.i_ltr_period = 0; ++ } ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++extern int msys_find_dmem_by_phys(unsigned long long phys, msys_mem* pdmem); ++ ++static void* ++phys2kptr( ++ unsigned long long phys) ++{ ++ msys_mem dmem; ++ char* kptr = NULL; ++ if (0 == msys_find_dmem_by_phys(phys, &dmem)) ++ { ++ kptr = (char*)(uintptr_t)dmem.kvirt; ++ kptr += (phys - dmem.phys); ++ } ++ return kptr; ++} ++ ++static int ++_mfectx_compress( ++ void* pctx, ++ mmfe_buff* buff) ++{ ++ mmfe_buff* buf = buff; ++ mmfe_buff* out = buff + 1; ++ mmfe_ctx* mctx = pctx; ++ mmfe_dev* mdev = mctx->p_device; ++ mhve_ops* mops = mctx->p_handle; ++ int pitch, err = -1; ++ ++ if (buff->i_memory != MMFE_MEMORY_MMAP) ++ return -EINVAL; ++ if (out->i_memory != MMFE_MEMORY_MMAP || out->i_planes != 1) ++ return -EINVAL; ++ pitch = buff->i_stride; ++ if (pitch < buff->i_width) ++ pitch = buff->i_width; ++ ++ mutex_lock(&mctx->m_stream); ++ do ++ if (MMFE_CTX_STATE_IDLE == mctx->i_state && MMFE_OMODE_MMAP == mctx->i_omode) ++ { ++ uint addr; ++ void* kptr; ++ mhve_cfg mcfg; ++ mhve_cpb mcpb; ++ mhve_vpb mvpb; ++ ++ /* align resolution to 32 */ ++ mcfg.type = MHVE_CFG_RES; ++ mops->get_conf(mops, &mcfg); ++ if (buff->i_planes != 2 && (MHVE_PIX_NV21 >= mcfg.res.e_pixf)) ++ break; ++ if (buff->i_planes != 1 && (MHVE_PIX_YUYV == mcfg.res.e_pixf)) ++ break; ++ if (mcfg.res.i_pixw != buf->i_width || ++ mcfg.res.i_pixh != buf->i_height) ++ break; ++ if (mcfg.res.e_pixf > MHVE_PIX_NV21) ++ pitch *= 2; ++ ++ /* setup input buffer */ ++ mcpb.i_index = 0; ++ mvpb.i_index = buf->i_index; ++ mvpb.i_stamp = buf->i_timecode; ++ mvpb.u_flags = buf->i_flags&MMFE_FLAGS_CONTROL; ++ mvpb.i_pitch = pitch; ++ mvpb.planes[1].u_phys = 0; ++ mvpb.planes[1].i_bias = 0; ++ addr = (uint)Chip_Phys_to_MIU(buf->planes[0].mem.phys); ++ mvpb.planes[0].u_phys = addr; ++ mvpb.planes[0].i_bias = buf->planes[0].i_bias; ++ if (mcfg.res.e_pixf <= MHVE_PIX_NV21) ++ { ++ addr = Chip_Phys_to_MIU(buf->planes[1].mem.phys); ++ mvpb.planes[1].u_phys = addr; ++ mvpb.planes[1].i_bias = buf->planes[1].i_bias; ++ } ++ ++ /* setup output buffer */ ++ addr = Chip_Phys_to_MIU(out->planes[0].mem.phys); ++ if (!(kptr = phys2kptr(out->planes[0].mem.phys))) ++ break; ++ mcfg.type = MHVE_CFG_DMA; ++ mcfg.dma.i_dmem = MHVE_CFG_DMA_OUTPUT_BUFFER; ++ mcfg.dma.p_vptr = kptr; ++ mcfg.dma.u_phys = addr; ++ mcfg.dma.i_size[0] = out->planes[0].i_size; ++ mops->set_conf(mops, &mcfg); ++ ++ mctx->i_state = MMFE_CTX_STATE_BUSY; ++ do ++ { ++ if (0 != (err = mops->enc_buff(mops, &mvpb))) ++ { ++ printk(KERN_ERR "%s() enc_buff err\n", __func__); ++ break; ++ } ++ mops->put_data(mops, mctx->p_usrdt, mctx->i_usrsz); ++ if (0 != (mops->enc_conf(mops))) ++ { ++ printk(KERN_ERR "%s() enc_conf err\n", __func__); ++ break; ++ } ++ if (0 != (mmfedev_pushjob(mdev, mctx))) ++ { ++ printk(KERN_ERR "%s() mvhedev_pushjob err\n", __func__); ++ break; ++ } ++ if (0 < (err = mops->enc_done(mops))) ++ { ++ printk(KERN_ERR "mfe-re-encode\n"); ++ } ++ } ++ while (err > 0); ++ ++ if (!err) ++ { ++ mctx->i_usrcn = mctx->i_usrsz = 0; ++ mcpb.i_index = -1; ++ } ++ ++ mops->deq_buff(mops, &mvpb); ++ buff->i_index = mvpb.i_index; ++ ++ err = mops->out_buff(mops, &mcpb); ++ out->planes[0].i_used = _MIN(mcpb.planes[0].i_size, mcfg.dma.i_size[0]); ++ out->planes[0].i_bias = mcpb.planes[0].i_bias; ++ out->i_timecode = mcpb.i_stamp; ++ out->i_flags = mcpb.i_flags; ++ ++ mctx->i_state = MMFE_CTX_STATE_IDLE; ++ } ++ while (0); ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_put_data( ++ void* pctx, ++ mmfe_buff* buff) ++{ ++ int err = -EINVAL; ++ mmfe_ctx* mctx = pctx; ++ void* dst; ++ ++ if (buff->i_memory != MMFE_MEMORY_USER || buff->i_planes != 1) ++ return err; ++ if (buff->planes[0].mem.uptr == NULL || ++ buff->planes[0].i_size < buff->planes[0].i_used || ++ buff->planes[0].i_used > 1024) ++ return err; ++ ++ mutex_lock(&mctx->m_stream); ++ do ++ if (MMFE_CTX_STATE_NULL != mctx->i_state && 4 > mctx->i_usrcn) ++ { ++ dst = (char*)mctx->p_usrdt + mctx->i_usrsz; ++ err = -EFAULT; ++ if (copy_from_user(dst, buff->planes[0].mem.uptr, buff->planes[0].i_used)) ++ break; ++ mctx->i_usrsz += buff->planes[0].i_used; ++ mctx->i_usrcn++; ++ err = 0; ++ } ++ while (0); ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_set_rqcf( ++ void* pctx, ++ rqct_conf* rqcf) ++{ ++ int err = -EINVAL; ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ ++ mutex_lock(&mctx->m_stream); ++ if ((unsigned)rqcf->type < RQCT_CONF_END && !rqct->set_rqcf(rqct, (rqct_cfg*)rqcf)) ++ err = 0; ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} ++ ++static int ++_mfectx_get_rqcf( ++ void* pctx, ++ rqct_conf* rqcf) ++{ ++ int err = -EINVAL; ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = mctx->p_handle; ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ ++ mutex_lock(&mctx->m_stream); ++ if ((unsigned)rqcf->type < RQCT_CONF_END && !rqct->get_rqcf(rqct, (rqct_cfg*)rqcf)) ++ err = 0; ++ mutex_unlock(&mctx->m_stream); ++ ++ return err; ++} +diff --git a/drivers/mstar/mfev5/mmfe_defs.h b/drivers/mstar/mfev5/mmfe_defs.h +new file mode 100644 +index 00000000..5a076557 +--- /dev/null ++++ b/drivers/mstar/mfev5/mmfe_defs.h +@@ -0,0 +1,128 @@ ++ ++#ifndef _MMFE_DEFS_H_ ++#define _MMFE_DEFS_H_ ++ ++#include ++#include ++#include ++ ++/* options */ ++#define MMFE_TIMER_SIZE 2048 ++ ++typedef MSYS_DMEM_INFO msys_mem; ++typedef struct mmfe_ctx mmfe_ctx; ++typedef struct mmfe_rqc mmfe_rqc; ++typedef struct mmfe_dev mmfe_dev; ++ ++struct mmfe_ctx ++{ ++ atomic_t i_refcnt; ++ void (*release) (void* ); ++ void (*adduser) (void* ); ++ struct mutex m_stream; ++ struct mutex m_encode; ++ mmfe_dev* p_device; ++ void* p_handle; ++ /* CTX status */ ++#define MMFE_CTX_STATE_NULL -1 ++#define MMFE_CTX_STATE_IDLE 0 ++#define MMFE_CTX_STATE_BUSY 1 ++ int i_state; ++ int i_score; ++ int i_index; ++ /* direct memory resource */ ++ int i_strid; // stream id set from user ++ short i_max_w; ++ short i_max_h; ++ /* user data buffer */ ++#define MMFE_USER_DATA_SIZE (4*1024) ++ unsigned char* p_usrdt; ++ short i_usrsz; ++ short i_usrcn; ++ /* user mode output */ ++ unsigned char* p_ovptr; ++ unsigned int u_ophys; ++ int i_osize; ++ int i_ormdr; ++ /* output cpbs(coded picture buffer) */ ++#define MMFE_CPBS_NR 1 ++ mhve_cpb m_mcpbs[MMFE_CPBS_NR]; ++ /* output buffer mode */ ++#define MMFE_OMODE_MMAP 0 ++#define MMFE_OMODE_USER 1 ++#define MMFE_OMODE_PIPE 2 ++ short i_omode; ++ /* input buffer mode */ ++#define MMFE_IMODE_PURE 0 ++#define MMFE_IMODE_PLUS 1 /* use input buffer as reconstruct buffer */ ++ short i_imode; ++ /* direct memory resource */ ++#define MMFE_DMEM_NR 4 ++ int i_dmems; ++ msys_mem m_dmems[MMFE_DMEM_NR]; ++#if MMFE_TIMER_SIZE ++ int i_numbr; ++ struct ++ { ++ unsigned char tm_dur[4]; ++ unsigned int tm_cycles; ++ } *p_timer; ++#endif ++}; ++ ++mmfe_ctx* mmfectx_acquire(mmfe_dev*); ++ long mmfectx_actions(mmfe_ctx*, unsigned int, void*); ++ ++struct mmfe_rqc ++{ ++ struct mutex* p_mutex; ++ struct cdev m_cdev; ++ struct mmfe_ctx* p_mctx; ++}; ++ ++long mmferqc_ioctls(void*, unsigned int, void*); ++size_t mmferqc_lprint(void*, char*, size_t); ++ ++struct mmfe_dev ++{ ++ int i_major; ++ int i_minor; ++ struct cdev m_cdev; // character device ++ struct device m_dev; // device node ++ struct device* p_dev; // platform device ++ struct mutex m_mutex; ++ struct semaphore m_sem; ++ int i_irq; ++ wait_queue_head_t m_wqh; ++#define MMFE_CLOCKS_NR 4 ++ struct clk* p_clocks[MMFE_CLOCKS_NR]; ++#define MMFE_STREAM_NR 4 ++ struct mmfe_rqc m_regrqc[MMFE_STREAM_NR]; ++ /* ... */ ++ void* p_asicip; ++#define MMFE_DEV_STATE_NULL -1 ++#define MMFE_DEV_STATE_IDLE 0 ++#define MMFE_DEV_STATE_BUSY 1 ++ int i_state; ++ int i_users; ++ int i_score; ++ /* statistic */ ++ int i_counts[MMFE_STREAM_NR][5]; ++ int i_thresh; ++ /* clock[0] */ ++ int i_clkidx; ++ int i_ratehz; ++ /* rate-controller */ ++ int i_rctidx; ++}; ++ ++int mmfedev_register(mmfe_dev*, mmfe_ctx*); ++int mmfedev_unregister(mmfe_dev*, mmfe_ctx*); ++int mmfedev_poweron(mmfe_dev*, int); ++int mmfedev_suspend(mmfe_dev*); ++int mmfedev_resume(mmfe_dev*); ++int mmfedev_pushjob(mmfe_dev*, mmfe_ctx*); ++int mmfedev_isr_fnx(mmfe_dev*); ++ ++#endif//_MMFE_DEFS_H_ ++ +diff --git a/drivers/mstar/mfev5/mmfe_dev.c b/drivers/mstar/mfev5/mmfe_dev.c +new file mode 100644 +index 00000000..080048b7 +--- /dev/null ++++ b/drivers/mstar/mfev5/mmfe_dev.c +@@ -0,0 +1,224 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++int ++mmfedev_register( ++ mmfe_dev* mdev, ++ mmfe_ctx* mctx) ++{ ++ int i = 0; ++ mutex_lock(&mdev->m_mutex); ++ mctx->i_index = -1; ++ while (i < MMFE_STREAM_NR) ++ { ++ if (mdev->m_regrqc[i++].p_mctx) ++ continue; ++ mdev->m_regrqc[--i].p_mctx = mctx; ++ mctx->p_device = mdev; ++ mctx->i_index = i; ++ break; ++ } ++ mutex_unlock(&mdev->m_mutex); ++ return mctx->i_index; ++} ++ ++int ++mmfedev_unregister( ++ mmfe_dev* mdev, ++ mmfe_ctx* mctx) ++{ ++ int id = mctx->i_index; ++ mutex_lock(&mdev->m_mutex); ++ mdev->m_regrqc[id].p_mctx = NULL; ++ mctx->p_device = NULL; ++ mctx->i_index = -1; ++ mutex_unlock(&mdev->m_mutex); ++ return 0; ++} ++ ++static int dev_clkrate(mmfe_dev*, int); ++static int dev_poweron(mmfe_dev*, int); ++ ++int ++mmfedev_poweron( ++ mmfe_dev* mdev, ++ int rate) ++{ ++ if (0 == rate) ++ return 0; ++ down(&mdev->m_sem); ++ do ++ { ++ mdev->i_score += rate; ++ if (mdev->i_users > 0) ++ dev_poweron(mdev, 0); ++ if (rate > 0) ++ mdev->i_users++; ++ else if (--mdev->i_users == 0) ++ break; ++ if (mdev->i_clkidx < 0) ++ mdev->i_ratehz = dev_clkrate(mdev, mdev->i_score*900); ++ dev_poweron(mdev, 1); ++ } ++ while (0); ++ up(&mdev->m_sem); ++ return 0; ++} ++ ++static int ++dev_clkrate( ++ mmfe_dev* mdev, ++ int rate) ++{ ++ struct clk* clock = mdev->p_clocks[0]; ++ struct clk* clk; ++ int i = 0, best = 0; ++ while (!(clk = clk_get_parent_by_index(clock, i++))) ++ { ++ int r = clk_get_rate(clk); ++ ++ if (rate > best && best < r) ++ best = r; ++ if (rate < best && rate < r && r < best) ++ best = r; ++ } ++ return best; ++} ++ ++static int ++dev_poweron( ++ mmfe_dev* mdev, ++ int on) ++{ ++ int i = on!=0; ++ struct clk* clk; ++ mhve_ios* mios = mdev->p_asicip; ++ mios->irq_mask(mios, 0xFF); ++ if (i == 0) ++ { ++ clk = mdev->p_clocks[0]; ++ clk_set_parent(clk, clk_get_parent_by_index(clk, 0)); ++ while (i < MMFE_CLOCKS_NR && (clk = mdev->p_clocks[i++])) ++ clk_disable_unprepare(clk); ++ return 0; ++ } ++ while (i < MMFE_CLOCKS_NR && (clk = mdev->p_clocks[i++])) ++ clk_prepare_enable(clk); ++ clk = mdev->p_clocks[0]; ++ clk_set_rate(clk, mdev->i_ratehz); ++ clk_prepare_enable(clk); ++ return 0; ++} ++ ++int ++mmfedev_suspend( ++ mmfe_dev* mdev) ++{ ++ down(&mdev->m_sem); ++ if (mdev->i_users > 0) ++ dev_poweron(mdev, 0); ++ return 0; ++} ++ ++int ++mmfedev_resume( ++ mmfe_dev* mdev) ++{ ++ if (mdev->i_users > 0) ++ dev_poweron(mdev, 1); ++ up(&mdev->m_sem); ++ return 0; ++} ++ ++static uint gettime(void) ++{ ++ struct timeval tv; ++ do_gettimeofday(&tv); ++ return (uint)((tv.tv_sec*1000000+tv.tv_usec+500)/1000); ++} ++ ++int ++mmfedev_pushjob( ++ mmfe_dev* mdev, ++ mmfe_ctx* mctx) ++{ ++ mhve_ops* mops = mctx->p_handle; ++ mhve_ios* mios = mdev->p_asicip; ++ mhve_job* mjob = mops->mhve_job(mops); ++ int otmr, itmr, id = mctx->i_index; ++ int err = 0; ++ long tick; ++ ++ otmr = gettime(); ++ down(&mdev->m_sem); ++ itmr = gettime(); ++ mdev->i_state = MMFE_DEV_STATE_BUSY; ++ mios->enc_fire(mios, mjob); ++ if (0 == (tick = wait_event_timeout(mdev->m_wqh, mdev->i_state==MMFE_DEV_STATE_IDLE, 60))) ++ { ++ mjob->i_code = MHVEJOB_TIME_OUT; ++ printk(KERN_ERR"mfe-wait event to(%ld)\n", tick); ++ err = -1; ++ } ++ itmr = gettime() - itmr; ++ up(&mdev->m_sem); ++ otmr = gettime() - otmr; ++ ++ if (otmr > mdev->i_thresh && mdev->i_thresh > 0) ++ mdev->i_counts[id][0]++; ++ if (otmr > mdev->i_counts[id][1]) ++ mdev->i_counts[id][1] = otmr; ++ if (itmr > mdev->i_counts[id][2]) ++ mdev->i_counts[id][2] = itmr; ++ if (mjob->i_tick > mdev->i_counts[id][3]) ++ mdev->i_counts[id][3] = mjob->i_tick; ++#if MMFE_TIMER_SIZE>0 ++ id = mctx->i_numbr&((MMFE_TIMER_SIZE/8)-1); ++ if(id==0){mctx->i_numbr = 0;} ++ mdev->i_counts[mctx->i_index][4] -= mctx->p_timer[id].tm_cycles/(MMFE_TIMER_SIZE/8); ++ mctx->p_timer[id].tm_dur[0] = (unsigned char)otmr; ++ mctx->p_timer[id].tm_dur[1] = (unsigned char)itmr; ++ mctx->p_timer[id].tm_cycles = (int)mjob->i_tick; ++ mctx->i_numbr++; ++ mdev->i_counts[mctx->i_index][4] += mctx->p_timer[id].tm_cycles/(MMFE_TIMER_SIZE/8); ++#endif ++ return err; ++} ++ ++int ++mmfedev_isr_fnx( ++ mmfe_dev* mdev) ++{ ++ mhve_ios* mios = mdev->p_asicip; ++ //if (!mios->isr_func(mios, 0)) ++ //{ ++ // mdev->i_state = MMFE_DEV_STATE_IDLE; ++ // wake_up(&mdev->m_wqh); ++ //} ++ mios->isr_func(mios, 0); ++ mdev->i_state = MMFE_DEV_STATE_IDLE; ++ wake_up(&mdev->m_wqh); ++ return 0; ++} +diff --git a/drivers/mstar/mfev5/mmfe_module.c b/drivers/mstar/mfev5/mmfe_module.c +new file mode 100644 +index 00000000..863b93c0 +--- /dev/null ++++ b/drivers/mstar/mfev5/mmfe_module.c +@@ -0,0 +1,492 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++MODULE_LICENSE("GPL"); ++ ++static int mmfe_open(struct inode*, struct file*); ++static int mmfe_release(struct inode*, struct file*); ++static long mmfe_ioctl(struct file*, unsigned int, unsigned long); ++ ++static struct file_operations mmfe_fops = { ++ .owner = THIS_MODULE, ++ .open = mmfe_open, ++ .release = mmfe_release, ++ .unlocked_ioctl = mmfe_ioctl, ++}; ++ ++static int ++mmfe_open( ++ struct inode* inode, ++ struct file* file) ++{ ++ mmfe_dev* mdev = container_of(inode->i_cdev,mmfe_dev,m_cdev); ++ mmfe_ctx* mctx; ++ if (!(mctx = mmfectx_acquire(mdev))) ++ return -ENOMEM; ++ if (0 <= mmfedev_register(mdev, mctx)) ++ { ++ file->private_data = mctx; ++ return 0; ++ } ++ mctx->release(mctx); ++ return -EINVAL; ++} ++ ++static int ++mmfe_release( ++ struct inode* inode, ++ struct file* file) ++{ ++ mmfe_dev* mdev = container_of(inode->i_cdev,mmfe_dev,m_cdev); ++ mmfe_ctx* mctx = file->private_data; ++ mmfedev_unregister(mdev, mctx); ++ file->private_data = NULL; ++ mctx->release(mctx); ++ return 0; ++} ++ ++static long ++mmfe_ioctl( ++ struct file* file, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ mmfe_ctx* mctx = file->private_data; ++ size_t n = _IOC_SIZE(cmd); ++ char buf[256]; ++ long err = -EFAULT; ++ void __user *uptr = (void __user *)arg; ++ unsigned int v = MMFEIF_VERSION_ID; ++ int type = _IOC_TYPE(cmd); ++ ++ if (type != MAGIC_RQCT && type != MAGIC_MMFE) ++ return -EINVAL; ++ switch (cmd) ++ { ++ case IOCTL_RQCT_VERSION: ++ v = RQCTIF_VERSION_ID; ++ if (access_ok(ACCESS_WRITE,uptr,sizeof(unsigned int))) ++ err = __put_user(v,(unsigned int*)uptr); ++ break; ++ case IOCTL_MMFE_VERSION: ++ v = MMFEIF_VERSION_ID; ++ if (access_ok(ACCESS_WRITE,uptr,sizeof(unsigned int))) ++ err = __put_user(v,(unsigned int*)uptr); ++ break; ++ default: ++ if ((_IOC_DIR(cmd) & _IOC_WRITE) && copy_from_user(buf, uptr, n)) ++ break; ++ if (0 > (err = mmfectx_actions(mctx, cmd, buf))) ++ break; ++ if ((_IOC_DIR(cmd) & _IOC_READ) && copy_to_user(uptr, buf, n)) ++ break; ++ err = 0; ++ break; ++ } ++ ++ return err; ++} ++ ++static int mrqc_open(struct inode*, struct file*); ++static int mrqc_release(struct inode*, struct file*); ++static long mrqc_ioctl(struct file*, unsigned int, unsigned long); ++static ssize_t mrqc_read(struct file*, char __user*, size_t, loff_t*); ++ ++static struct file_operations mrqc_fops = { ++ .owner = THIS_MODULE, ++ .open = mrqc_open, ++ .release = mrqc_release, ++ .unlocked_ioctl = mrqc_ioctl, ++ .read = mrqc_read, ++}; ++ ++static int ++mrqc_open( ++ struct inode* inode, ++ struct file* file) ++{ ++ int err = -EINVAL; ++ mmfe_rqc* mrqc = container_of(inode->i_cdev,mmfe_rqc,m_cdev); ++ mmfe_ctx* mctx = NULL; ++ mutex_lock(mrqc->p_mutex); ++ if (NULL != (mctx = mrqc->p_mctx)) ++ { ++ mctx->adduser(mctx); ++ file->private_data = mctx; ++ err = 0; ++ } ++ mutex_unlock(mrqc->p_mutex); ++ return err; ++} ++ ++static int ++mrqc_release( ++ struct inode* inode, ++ struct file* file) ++{ ++ mmfe_ctx* mctx = file->private_data; ++ mctx->release(mctx); ++ return 0; ++} ++ ++static long ++mrqc_ioctl( ++ struct file* file, ++ unsigned int cmd, ++ unsigned long arg) ++{ ++ size_t n = _IOC_SIZE(cmd); ++ char buf[256]; ++ long err = -EFAULT; ++ void __user *uptr = (void __user *)arg; ++ void* mctx = file->private_data; ++ unsigned int v = RQCTIF_VERSION_ID; ++ ++ if (_IOC_TYPE(cmd) != MAGIC_RQCT) ++ return -EINVAL; ++ switch (cmd) ++ { ++ case IOCTL_RQCT_VERSION: ++ if (access_ok(ACCESS_WRITE,uptr,sizeof(unsigned int))) ++ err = __put_user(v,(unsigned int*)uptr); ++ break; ++ default: ++ if ((_IOC_DIR(cmd) & _IOC_WRITE) && copy_from_user(buf, uptr, n)) ++ break; ++ if (0 > (err = mmferqc_ioctls(mctx, cmd, buf))) ++ break; ++ if ((_IOC_DIR(cmd) & _IOC_READ) && copy_to_user(uptr, buf, n)) ++ break; ++ err = 0; ++ break; ++ } ++ ++ return err; ++} ++ ++static ssize_t ++mrqc_read( ++ struct file* file, ++ char __user* buff, ++ size_t size, ++ loff_t* fpos) ++{ ++ char line[RQCT_LINE_SIZE]; ++ long err = -EFAULT; ++ void __user *uptr = (void __user*)buff; ++ void* mctx = file->private_data; ++ size_t lsize = mmferqc_lprint(mctx, line, RQCT_LINE_SIZE); ++ if (size > lsize) ++ size = lsize; ++ if (size > 0 && copy_to_user(uptr, line, size)) ++ return (ssize_t)err; ++ return (ssize_t)size; ++} ++ ++static void mmfe_dev_release(struct device* dev) {} ++ ++static ssize_t mmfe_tmr_store(struct device* dev, struct device_attribute* attr, const char* buff, size_t n) ++{ ++ mmfe_dev* mdev = container_of(dev,mmfe_dev,m_dev); ++ int i, thresh = 0; ++ if (0 != kstrtol(buff, 10, (long int*)&thresh)) ++ return -EINVAL; ++ mdev->i_thresh = thresh; ++ for (i = 0; i < MMFE_STREAM_NR; i++) ++ mdev->i_counts[i][0] = mdev->i_counts[i][1] = mdev->i_counts[i][2] = mdev->i_counts[i][3] = mdev->i_counts[i][4] = 0; ++ return n; ++} ++ ++static ssize_t mmfe_tmr_print(struct device* dev, struct device_attribute* attr, char* buff) ++{ ++ char* str = buff; ++ char* end = buff + PAGE_SIZE; ++ mmfe_dev* mdev = container_of(dev,mmfe_dev,m_dev); ++ int i; ++ for (i = 0; i < MMFE_STREAM_NR; i++) ++ str += scnprintf(str,end-str,"inst-%d:%8d/%5d/%5d/ %8d / %8d \n",i,mdev->i_counts[i][0],mdev->i_counts[i][1],mdev->i_counts[i][2],mdev->i_counts[i][3],mdev->i_counts[i][4]); ++ str += scnprintf(str,end-str,"thresh:%8d\n",mdev->i_thresh); ++ return (str - buff); ++} ++ ++static DEVICE_ATTR(tmr,0644,mmfe_tmr_print,mmfe_tmr_store); ++ ++static ssize_t mmfe_clk_store(struct device* dev, struct device_attribute* attr, const char* buff, size_t n) ++{ ++ mmfe_dev* mdev = container_of(dev,mmfe_dev,m_dev); ++ struct clk* clock = mdev->p_clocks[0]; ++ struct clk* ck = NULL; ++ int id = 0; ++ if (0 != kstrtol(buff, 10, (long int*)&id)) ++ return -EINVAL; ++ ck = clk_get_parent_by_index(clock, id); ++ if (ck == NULL) ++ mdev->i_ratehz = mdev->i_clkidx = -1; ++ else ++ { ++ mdev->i_clkidx = id; ++ mdev->i_ratehz = clk_get_rate(ck); ++ } ++ return n; ++} ++ ++static ssize_t mmfe_clk_print(struct device* dev, struct device_attribute* attr, char* buff) ++{ ++ char* str = buff; ++ char* end = buff + PAGE_SIZE; ++ mmfe_dev* mdev = container_of(dev,mmfe_dev,m_dev); ++ if (mdev->i_clkidx < 0) ++ str += scnprintf(str,end-str,"clkidx:%3d(dynamic)\n",mdev->i_clkidx); ++ else ++ str += scnprintf(str,end-str,"clkidx:%3d(%3d mhz)\n",mdev->i_clkidx,mdev->i_ratehz/1000000); ++ return (str - buff); ++} ++ ++static DEVICE_ATTR(clk,0644,mmfe_clk_print,mmfe_clk_store); ++ ++char* rqctmfe_comment(int); ++ ++static ssize_t mmfe_rct_store(struct device* dev, struct device_attribute* attr, const char* buff, size_t n) ++{ ++ mmfe_dev* mdev = container_of(dev,mmfe_dev,m_dev); ++ int id = 0; ++ char* brief; ++ if (0 != kstrtol(buff, 10, (long int*)&id)) ++ return -EINVAL; ++ if ((brief = rqctmfe_comment(id)) && *brief) ++ mdev->i_rctidx = id; ++ return n; ++} ++ ++static ssize_t mmfe_rct_print(struct device* dev, struct device_attribute* attr, char* buff) ++{ ++ char* str = buff; ++ char* end = buff + PAGE_SIZE; ++ mmfe_dev* mdev = container_of(dev,mmfe_dev,m_dev); ++ char* brief; ++ int j; ++ for (j = 0; (brief = rqctmfe_comment(j)); j++) ++ if (*brief) ++ str += scnprintf(str,end-str,"(%c)[%d]%s\n",j==mdev->i_rctidx?'*':' ',j,brief); ++ return (str - buff); ++} ++ ++static DEVICE_ATTR(rct,0644,mmfe_rct_print,mmfe_rct_store); ++ ++static irqreturn_t mmfe_isr(int irq, void* priv); ++ ++mhve_ios* mmfeios_acquire(char* tags); ++ ++static int ++mmfe_probe( ++ struct platform_device* pdev) ++{ ++ int i, err = 0; ++ dev_t dev; ++ mmfe_dev* mdev = NULL; ++ mhve_ios* mios = NULL; ++ mhve_reg mregs; ++ struct resource* res; ++ struct clk* clock; ++ int major, minor = 0; ++ ++ if (0 > (err = alloc_chrdev_region(&dev, minor, MMFE_STREAM_NR+1, "mstar_mmfe"))) ++ return err; ++ major = MAJOR(dev); ++ do ++ { ++ mmfe_rqc* mrqc; ++ err = -ENOMEM; ++ if (!(mdev = kzalloc(sizeof(mmfe_dev), GFP_KERNEL))) ++ break; ++ mutex_init(&mdev->m_mutex); ++ sema_init(&mdev->m_sem, 1); ++ mrqc = mdev->m_regrqc; ++ while (minor < MMFE_STREAM_NR) ++ { ++ cdev_init(&mrqc[minor].m_cdev, &mrqc_fops); ++ mrqc[minor].m_cdev.owner = THIS_MODULE; ++ if (0 > (err = cdev_add(&mrqc[minor].m_cdev, MKDEV(major,minor), 1))) ++ break; ++ mrqc[minor].p_mutex = &mdev->m_mutex; ++ minor++; ++ } ++ if (minor < MMFE_STREAM_NR) ++ break; ++ mdev->i_major = major; ++ mdev->i_minor = minor; ++ cdev_init(&mdev->m_cdev, &mmfe_fops); ++ mdev->m_cdev.owner = THIS_MODULE; ++ if (0 > (err = cdev_add(&mdev->m_cdev, MKDEV(major,minor), 1))) ++ break; ++ mdev->m_dev.devt = MKDEV(major,minor); ++ mdev->m_dev.class = msys_get_sysfs_class(); ++ mdev->m_dev.parent = NULL; ++ mdev->m_dev.release = mmfe_dev_release; ++ dev_set_name(&mdev->m_dev, "%s", "mmfe"); ++ if (0 > (err = device_register(&mdev->m_dev))) ++ break; ++ if (!(mdev->p_asicip = mmfeios_acquire("mfe5"))) ++ break; ++ mios = mdev->p_asicip; ++ mdev->p_dev = &pdev->dev; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ mregs.i_id = 0; ++ mregs.base = (void*)IO_ADDRESS(res->start); ++ mregs.size = (int)(res->end - res->start); ++ mios->set_bank(mios, &mregs); ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ mdev->i_irq = (int)res->start; ++ init_waitqueue_head(&mdev->m_wqh); ++ if (0 != (err = request_irq(mdev->i_irq, mmfe_isr, IRQF_SHARED, "mmfe_isr", mdev))) ++ break; ++ err = -EINVAL; ++ clock = clk_get(&pdev->dev, "CKG_mfe"); ++ if (IS_ERR(clock)) ++ break; ++ mdev->p_clocks[0] = clock; ++ mdev->i_clkidx = 0; ++ mdev->i_ratehz = clk_get_rate(clk_get_parent_by_index(clock,mdev->i_clkidx)); ++ for (i = 1; i < MMFE_CLOCKS_NR; i++) ++ { ++ clock = of_clk_get(pdev->dev.of_node, i); ++ if (IS_ERR(clock)) ++ break; ++ mdev->p_clocks[i] = clock; ++ } ++ mdev->i_rctidx = 1; ++ dev_set_drvdata(&pdev->dev, mdev); ++ ++ device_create_file(&mdev->m_dev, &dev_attr_tmr); ++ device_create_file(&mdev->m_dev, &dev_attr_clk); ++ device_create_file(&mdev->m_dev, &dev_attr_rct); ++// printk("mmfe built at %s on %s\n",__TIME__,__DATE__); ++ return 0; ++ } ++ while (0); ++ ++ if (mdev) ++ { ++ mhve_ios* mios = mdev->p_asicip; ++ cdev_del(&mdev->m_cdev); ++ if (mios) ++ mios->release(mios); ++ kfree(mdev); ++ } ++ ++ return err; ++} ++ ++static int ++mmfe_remove( ++ struct platform_device* pdev) ++{ ++ mmfe_dev* mdev = dev_get_drvdata(&pdev->dev); ++ mhve_ios* mios = mdev->p_asicip; ++ int devno = MKDEV(mdev->i_major,0); ++ int i = 0; ++ ++ free_irq(mdev->i_irq, mmfe_isr); ++ ++ clk_put(mdev->p_clocks[0]); ++ ++ while (i < MMFE_STREAM_NR) ++ cdev_del(&mdev->m_regrqc[i++].m_cdev); ++ cdev_del(&mdev->m_cdev); ++ ++ device_unregister(&mdev->m_dev); ++ ++ if (mios) ++ mios->release(mios); ++ kfree(mdev); ++ ++ dev_set_drvdata(&pdev->dev, NULL); ++ ++ unregister_chrdev_region(devno, MMFE_STREAM_NR+1); ++ ++ return 0; ++} ++ ++static int ++mmfe_suspend( ++ struct platform_device* pdev, ++ pm_message_t state) ++{ ++ mmfe_dev* mdev = dev_get_drvdata(&pdev->dev); ++ ++ return mmfedev_suspend(mdev); ++} ++ ++static int ++mmfe_resume( ++ struct platform_device* pdev) ++{ ++ mmfe_dev* mdev = dev_get_drvdata(&pdev->dev); ++ ++ return mmfedev_resume(mdev); ++} ++ ++static irqreturn_t mmfe_isr(int irq, void* priv) ++{ ++ mmfe_dev* mdev = (mmfe_dev*)priv; ++ ++ mmfedev_isr_fnx(mdev); ++ ++ return IRQ_HANDLED; ++} ++ ++static const struct of_device_id mmfe_of_match_tables[] = { ++ { .compatible = "mstar,mfe" }, ++ {}, ++}; ++ ++static struct platform_driver mmfe_pdrv = { ++ .probe = mmfe_probe, ++ .remove = mmfe_remove, ++ .suspend = mmfe_suspend, ++ .resume = mmfe_resume, ++ .driver = { ++ .name = "mmfe", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(mmfe_of_match_tables), ++ } ++}; ++ ++static int __init mmfe_init(void) ++{ ++ return platform_driver_register(&mmfe_pdrv); ++} ++ ++static void __exit mmfe_exit(void) ++{ ++ platform_driver_unregister(&mmfe_pdrv); ++} ++ ++module_init(mmfe_init); ++module_exit(mmfe_exit); ++ +diff --git a/drivers/mstar/mfev5/mmfe_rqc.c b/drivers/mstar/mfev5/mmfe_rqc.c +new file mode 100644 +index 00000000..64642ff7 +--- /dev/null ++++ b/drivers/mstar/mfev5/mmfe_rqc.c +@@ -0,0 +1,73 @@ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++long ++mmferqc_ioctls( ++ void* pctx, ++ unsigned int cmd, ++ void* arg) ++{ ++ int err = -EINVAL; ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = NULL; ++ mutex_lock(&mctx->m_stream); ++ if (NULL != (mops = mctx->p_handle)) ++ { ++ rqct_ops* rqct = mops->rqct_ops(mops); ++ switch (cmd) ++ { ++ case IOCTL_RQCT_S_CONF: ++ if (!rqct->set_rqcf(rqct, (rqct_cfg*)arg)) ++ err = 0; ++ break; ++ case IOCTL_RQCT_G_CONF: ++ if (!rqct->get_rqcf(rqct, (rqct_cfg*)arg)) ++ err = 0; ++ break; ++ default: ++ break; ++ } ++ } ++ mutex_unlock(&mctx->m_stream); ++ return err; ++} ++ ++size_t ++mmferqc_lprint( ++ void* pctx, ++ char* line, ++ size_t size) ++{ ++ mmfe_ctx* mctx = pctx; ++ mhve_ops* mops = NULL; ++ rqct_ops* rqct = NULL; ++ if (size > RQCT_LINE_SIZE) ++ size = RQCT_LINE_SIZE; ++ mutex_lock(&mctx->m_stream); ++ if (!(mops = mctx->p_handle)) ++ size = 0; ++ else ++ { ++ rqct = mops->rqct_ops(mops); ++ memset(line,0,size); ++ strncpy(line, rqct->print_line, size-1); ++ memset(rqct->print_line, 0, RQCT_LINE_SIZE); ++ } ++ mutex_unlock(&mctx->m_stream); ++ return size; ++} +diff --git a/drivers/mstar/mhve/mhve_ios.h b/drivers/mstar/mhve/mhve_ios.h +new file mode 100644 +index 00000000..971c8f4e +--- /dev/null ++++ b/drivers/mstar/mhve/mhve_ios.h +@@ -0,0 +1,38 @@ ++ ++// mstar hardware video encoder I/F (mhveif) ++ ++#ifndef _MHVE_IOS_H_ ++#define _MHVE_IOS_H_ ++ ++typedef struct mhve_ios mhve_ios; ++typedef struct mhve_reg mhve_reg; ++typedef struct mhve_job mhve_job; ++ ++struct mhve_ios { ++ void (*release)(void*); //! release this object. ++ int (*set_bank)(mhve_ios*, mhve_reg*); //! assign register base pointer. ++ int (*enc_fire)(mhve_ios*, mhve_job*); //! process and trigger encoder job. ++ int (*enc_poll)(mhve_ios*); //! polling encode-done. ++ int (*isr_func)(mhve_ios*, int); //! interrupt service routine. ++ int (*irq_mask)(mhve_ios*, int); //! masking irq. ++}; ++ ++struct mhve_reg { ++ int i_id; ++ void* base; ++ int size; ++}; ++ ++#define MHVEJOB_OKAY 0 ++#define MHVEJOB_ENC_DONE 0 ++#define MHVEJOB_BUF_FULL 1 ++#define MHVEJOB_ENC_FAIL -1 ++#define MHVEJOB_TIME_OUT -2 ++ ++struct mhve_job { ++ int i_code; // store encoder result as MHVEJOB_ENC_DONE/MHVEJOB_BUF_FULL/MHVEJOB_ENC_FAIL/MHVEJOB_TIME_OUT ++ int i_tick; // count hw tick ++ int i_bits; ++}; ++ ++#endif//_MHVE_IOS_H_ +diff --git a/drivers/mstar/mhve/mhve_ops.h b/drivers/mstar/mhve/mhve_ops.h +new file mode 100644 +index 00000000..6cab4ab4 +--- /dev/null ++++ b/drivers/mstar/mhve/mhve_ops.h +@@ -0,0 +1,209 @@ ++#ifndef _MHVE_OPS_H_ ++#define _MHVE_OPS_H_ ++ ++typedef struct mhve_ops mhve_ops; ++typedef struct mhve_vpb mhve_vpb; ++typedef struct mhve_cpb mhve_cpb; ++typedef union mhve_cfg mhve_cfg; ++ ++typedef signed long long int64; ++typedef unsigned int uint; ++ ++#define _MAX(a,b) ((a)>(b)?(a):(b)) ++#define _MIN(a,b) ((a)<(b)?(a):(b)) ++ ++#define MHVE_FLAGS_FORCEI (1<< 0) // Force I-Frame ++#define MHVE_FLAGS_DISREF (1<< 1) // Disable referenced any frame ++#define MVHE_FLAGS_LTR_PFRAME (1<< 4) // long term Reference P-frame ++ ++struct mhve_vpb // video picture buffer ++{ ++ int i_index; ++ uint u_flags; ++ int64 i_stamp; ++ int i_pitch; ++ struct ++ { ++ uint u_phys; ++ int i_bias; ++ int i_size; ++ } planes[2]; ++ /* ISP informations */ ++}; ++ ++#define MHVE_FLAGS_EOP (1<<31) ++#define MHVE_FLAGS_SOP (1<<30) ++ ++struct mhve_cpb // coded picture buffer ++{ ++ int i_index; ++ int i_flags; ++ int64 i_stamp; ++ int i_count; ++ struct ++ { ++ uint u_phys; ++ int i_bias; ++ int i_size; ++ } planes[2]; ++}; ++ ++typedef enum mhve_pix_e ++{ ++ MHVE_PIX_NV12 = 0, ++ MHVE_PIX_NV21, ++ MHVE_PIX_YUYV, ++ MHVE_PIX_YVYU, ++} mhve_pix_e; ++ ++#define MHVE_INTER_4x4 (1<<0) //!< bit-field of 4x4 block ++#define MHVE_INTER_8x4 (1<<1) //!< bit-field of 8x4 block ++#define MHVE_INTER_4x8 (1<<2) //!< bit-field of 4x8 block ++#define MHVE_INTER_8x8 (1<<3) //!< bit-field of 8x8 block ++#define MHVE_INTER_16x8 (1<<4) //!< bit-field of 16x8 block ++#define MHVE_INTER_8x16 (1<<5) //!< bit-field of 8x16 block ++#define MHVE_INTER_16x16 (1<<6) //!< bit-field of 16x16 block ++#define MHVE_INTER_SKIP (1<<7) //!< bit-field of skip ++ ++#define MHVE_AVC_PROFILE_BP 66 //!< H.264 Base Line Profile ++#define MHVE_AVC_PROFILE_MP 77 //!< H.264 Main Profile ++#define MHVE_AVC_LEVEL_3 30 //!< H.264 Level-3.0 ++#define MHVE_AVC_LEVEL_31 31 //!< H.264 Level-3.1 ++#define MHVE_AVC_LEVEL_32 32 //!< H.264 Level-3.2 ++#define MHVE_AVC_LEVEL_4 40 //!< H.264 Level-4.0 ++ ++union mhve_cfg ++{ ++ enum mhve_cfg_e ++ { ++ MHVE_CFG_RES=0, ++ MHVE_CFG_DMA, ++ MHVE_CFG_MOT, ++ MHVE_CFG_AVC, ++ MHVE_CFG_HEV, ++ MHVE_CFG_VUI, ++ MHVE_CFG_PEN, ++ MHVE_CFG_LFT, ++ MHVE_CFG_SPL, ++ MHVE_CFG_BAC, ++ MHVE_CFG_LTR ++ } type; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ mhve_pix_e e_pixf; ++ short i_pixw, i_pixh; ++ int i_rpbn; // reconstruct buffer numbers ++#define MHVE_CFG_COMPR (1<<0) ++#define MHVE_CFG_OMMAP (1<<1) ++ uint u_conf; ++ } res; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ /* identify number of reconstruct buffer or output/NALU buffer */ ++#define MHVE_CFG_DMA_OUTPUT_BUFFER -1 ++#define MHVE_CFG_DMA_NALU_BUFFER -2 ++#define MHVE_CFG_DMA_RESET_RECN_BUFFER -3 ++ int i_dmem; ++ void* p_vptr; ++ uint u_phys; ++ int i_size[6]; ++ } dma; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ int i_subp; ++ short i_dmvx; ++ short i_dmvy; ++ uint i_blkp[2]; ++ } mot; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_num_ref_frames; //!< ref.frames count. ++ unsigned char i_poc_type; //!< poc_type: support 0,2. ++ unsigned char b_entropy_coding_type; //!< entropy: cabac/cavlc. ++ unsigned char b_constrained_intra_pred; //!< contrained intra pred. ++ unsigned char b_deblock_filter_control; //!< deblock filter control. ++ unsigned char i_disable_deblocking_idc; //!< disable deblocking idc. ++ signed char i_alpha_c0_offset; //!< offset alpha div2. ++ signed char i_beta_offset; //!< offset beta div2. ++ } avc; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ unsigned short i_profile; //!< profile. ++ unsigned short i_level; //!< level. ++ unsigned char i_log2_max_cb_size; //!< max ctb size. ++ unsigned char i_log2_min_cb_size; //!< min ctb size. ++ unsigned char i_log2_max_tr_size; //!< max trb size. ++ unsigned char i_log2_min_tr_size; //!< min trb size. ++ unsigned char i_tr_depth_intra; //!< tr depth intra. ++ unsigned char i_tr_depth_inter; //!< tr depth inter. ++ unsigned char b_scaling_list_enable; //!< scaling list enable. ++ unsigned char b_sao_enable; //!< sao enable. ++ unsigned char b_strong_intra_smoothing; //!< strong intra smoothing. ++ unsigned char b_ctu_qp_delta_enable; //!< ctu qp delta enable. ++ unsigned char b_constrained_intra_pred; //!< constrained intra prediction. ++ unsigned char b_deblocking_override_enable; //!< deblocking override enable. ++ signed char i_cqp_offset; //!< cqp offset: -12 to 12 (inclusive) ++ unsigned char b_deblocking_disable; //!< deblocking disable. ++ signed char i_tc_offset_div2; //!< tc_offset_div2: -6 to 6 (inclusive) ++ signed char i_beta_offset_div2; //!< beta_offset_div2: -6 to 6 (inclusive) ++ } hev; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ unsigned char b_video_full_range; ++ unsigned char b_timing_info_pres; ++ } vui; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ signed char b_override; ++ signed char b_disable; ++ signed char i_offsetA; ++ signed char i_offsetB; ++ } lft; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ short i_rows; ++ short i_bits; ++ } spl; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ int b_init; ++ } bac; ++ struct ++ { ++ enum mhve_cfg_e i_type; ++ unsigned char b_long_term_reference; //!< toggle ltr ++ int b_enable_pred; //!< ltr mode ++ } ltr; ++}; ++ ++struct mhve_ops ++{ ++ char mhvename[16]; ++ void (*release) (mhve_ops*); //! release this object. ++ void*(*rqct_ops) (mhve_ops*); //! get rqct_ops handle. ++ void*(*mhve_job) (mhve_ops*); //! get mhve_job object. ++ int (*seq_sync) (mhve_ops*); //! start seq. encoding. ++ int (*seq_conf) (mhve_ops*); //! config seq. setting. ++ int (*seq_done) (mhve_ops*); //! finish seq. encoding. ++ int (*enc_buff) (mhve_ops*, mhve_vpb*); //! enqueue video buffer. ++ int (*deq_buff) (mhve_ops*, mhve_vpb*); //! dequeue video buffer. ++ int (*enc_conf) (mhve_ops*); //! config current enc. setting. ++ int (*put_data) (mhve_ops*, void*,int); //! put user data to output bit. ++ int (*enc_done) (mhve_ops*); //! finish encode frame. ++ int (*out_buff) (mhve_ops*, mhve_cpb*); //! output coded buffer. ++ int (*set_conf) (mhve_ops*, mhve_cfg*); //! apply config. ++ int (*get_conf) (mhve_ops*, mhve_cfg*); //! query config. ++}; ++ ++#endif/*_MHVE_OPS_H_*/ +diff --git a/drivers/mstar/mhve/rqct_cfg.h b/drivers/mstar/mhve/rqct_cfg.h +new file mode 100644 +index 00000000..4f5cae9f +--- /dev/null ++++ b/drivers/mstar/mhve/rqct_cfg.h +@@ -0,0 +1,142 @@ ++#ifndef _RQCT_CFG_H_ ++#define _RQCT_CFG_H_ ++ ++typedef union rqct_cfg rqct_cfg; ++typedef struct rqct_buf rqct_buf; ++ ++union rqct_cfg ++{ ++ enum rqct_cfg_e ++ { ++ RQCT_CFG_SEQ= 0, ++ RQCT_CFG_DQP, ++ RQCT_CFG_QPR, ++ RQCT_CFG_LOG, ++ RQCT_CFG_PEN, ++ RQCT_CFG_SPF, ++ RQCT_CFG_LTR, // Long term reference ++ /* below RQCT_CFG type MUST one by one match rqct_conf_e in mdrv_rqct_st.h */ ++ RQCT_CFG_RES=32, ++ RQCT_CFG_FPS, ++ RQCT_CFG_ROI, ++ RQCT_CFG_DQM, ++ RQCT_CFG_RCM, ++ } type; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_SEQ" ++ enum rqct_mode ++ { ++ RQCT_MODE_CQP=0, ++ RQCT_MODE_CBR, ++ RQCT_MODE_VBR, ++ } i_method; ++ int i_period; ++ int i_leadqp; ++ int i_btrate; ++ } seq; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_LTR" ++ int i_period; ++ } ltr; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_DQP" ++ int i_dqp; ++ } dqp; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_QPR" ++ int i_iupperq; ++ int i_ilowerq; ++ int i_pupperq; ++ int i_plowerq; ++ } qpr; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_LOG" ++ int b_logm; ++ } log; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_PEN" ++ short b_i16pln; ++ short i_peni4x; ++ short i_peni16; ++ short i_penint; ++ short i_penYpl; ++ short i_penCpl; ++ } pen; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_RCM" ++ enum rqct_spfrm_mode ++ { ++ RQCT_SPFRM_NONE=0, //!< super frame mode none. ++ RQCT_SPFRM_DISCARD, //!< super frame mode discard. ++ RQCT_SPFRM_REENCODE, //!< super frame mode reencode. ++ } e_spfrm; ++ int i_IfrmThr; ++ int i_PfrmThr; ++ int i_BfrmThr; ++ } spf; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_RES" ++ short i_picw; ++ short i_pich; ++ } res; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_FPS" ++ short n_fps; ++ short d_fps; ++ } fps; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_ROI" ++ short i_roiidx; ++ short i_roidqp; ++ short i_posx; ++ short i_posy; ++ short i_recw; ++ short i_rech; ++ } roi; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_DQM" ++ unsigned int u_phys; ++ void* p_kptr; ++ short i_dqmw; ++ short i_dqmh; ++ int i_size; ++ int i_unit; ++ } dqm; ++ ++ struct ++ { ++ enum rqct_cfg_e i_type; //!< MUST BE "RQCT_CFG_RCM" ++ unsigned int u_phys; ++ void* p_kptr; ++ int i_size; ++ } rcm; ++}; ++ ++struct rqct_buf ++{ ++ unsigned int u_config; ++}; ++ ++#endif//_RQCT_CFG_H_ +diff --git a/drivers/mstar/mhve/rqct_ops.h b/drivers/mstar/mhve/rqct_ops.h +new file mode 100644 +index 00000000..f18ca1fa +--- /dev/null ++++ b/drivers/mstar/mhve/rqct_ops.h +@@ -0,0 +1,72 @@ ++ ++// mstar hardware video encoder I/F (mhveif) ++ ++#ifndef _RQCT_OPS_H_ ++#define _RQCT_OPS_H_ ++ ++#include ++ ++typedef struct rqct_ops rqct_ops; ++ ++struct rqct_ops ++{ ++ char name[32]; ++ void (*release)(rqct_ops* rqct); ++ int (*seq_sync)(rqct_ops* rqct); ++ int (*seq_done)(rqct_ops* rqct); ++ int (*set_rqcf)(rqct_ops* rqct, rqct_cfg* rqcf); ++ int (*get_rqcf)(rqct_ops* rqct, rqct_cfg* rqcf); ++ int (*seq_conf)(rqct_ops* rqct); ++ int (*enc_buff)(rqct_ops* rqct, rqct_buf* buff); ++ int (*enc_conf)(rqct_ops* rqct, mhve_job* mjob); ++ int (*enc_done)(rqct_ops* rqct, mhve_job* mjob); ++#define RQCT_LINE_SIZE 128 ++ char print_line[RQCT_LINE_SIZE]; ++ enum ++ { ++ RQCT_PICTYP_I=0, ++ RQCT_PICTYP_P, ++ RQCT_PICTYP_B, ++ RQCT_PICTYP_LTRP, // This frame is LTR P-frame ++ } i_pictyp; ++#define IS_IPIC(t) (RQCT_PICTYP_I==(t)) ++#define IS_PPIC(t) (RQCT_PICTYP_P==(t)) ++#define IS_BPIC(t) (RQCT_PICTYP_B==(t)) ++#define IS_LTRPPIC(t) (RQCT_PICTYP_LTRP==(t)) ++ int i_enc_qp; ++ int b_unrefp; // used for disposable unreferenced frame ++ int i_bitcnt; ++ int i_enc_nr; ++ int i_enc_bs; ++}; ++ ++typedef struct rqct_att ++{ ++ short i_pict_w, i_pict_h; ++ short n_fmrate, d_fmrate; ++ short i_method, i_iperiod; // i_method:CBR/VBR; i_iperiod:GoP ++ short i_ltrperiod; // LTR P-frame period ++ short i_leadqp, i_deltaq; ++ short i_iupperq, i_ilowerq; ++ short i_pupperq, i_plowerq; ++ int i_btrate; ++ int b_logoff; ++ short b_i16pln, i_peni16; ++ short i_peni4x, i_penint; ++ short i_penYpl, i_penCpl; ++#define RQCT_ROI_NR 8 ++ signed char i_roidqp[RQCT_ROI_NR]; ++ struct roirec ++ { ++ short i_posx, i_posy; ++ short i_recw, i_rech; ++ } m_roirec[RQCT_ROI_NR]; ++ short i_dqmw, i_dqmh; ++ int b_dqmstat; ++ int i_dqmunit; ++ void* p_dqmkptr; ++ unsigned int u_dqmphys; ++ unsigned int i_dqmsize; ++} rqct_att; ++ ++#endif//_RQCT_OPS_H_ +diff --git a/drivers/mstar/msys/Kconfig b/drivers/mstar/msys/Kconfig +new file mode 100644 +index 00000000..5112f63e +--- /dev/null ++++ b/drivers/mstar/msys/Kconfig +@@ -0,0 +1,7 @@ ++config MS_MSYS ++ bool ++ default y ++ ++config MS_ZEN ++ bool ++ default y +diff --git a/drivers/mstar/msys/Makefile b/drivers/mstar/msys/Makefile +new file mode 100644 +index 00000000..6bf47502 +--- /dev/null ++++ b/drivers/mstar/msys/Makefile +@@ -0,0 +1,7 @@ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/mstar/crypto/infinity ++obj-$(CONFIG_MS_MSYS) = ms_msys.o +\ No newline at end of file +diff --git a/drivers/mstar/msys/ms_msys.c b/drivers/mstar/msys/ms_msys.c +new file mode 100644 +index 00000000..8784c74a +--- /dev/null ++++ b/drivers/mstar/msys/ms_msys.c +@@ -0,0 +1,2799 @@ ++/* ++ * mdrv_system.c ++ * ++ * Created on: 2012/9/21 ++ * Author: Administrator ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for dma_alloc_coherent */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_msys_io_st.h" ++#include "mdrv_msys_io.h" ++#include "mdrv_verchk.h" ++ ++ ++#define BENCH_MEMORY_FUNC 0 ++#define MSYS_DEBUG 0 ++#define MINOR_SYS_NUM 128 ++#define MAJOR_SYS_NUM 233 ++ ++#if MSYS_DEBUG ++#define MSYS_PRINT(fmt, args...) printk("[MSYS] " fmt, ## args) ++#else ++#define MSYS_PRINT(fmt, args...) ++#endif ++ ++#define MSYS_ERROR(fmt, args...) printk(KERN_ERR"MSYS: " fmt, ## args) ++#define MSYS_WARN(fmt, args...) printk(KERN_WARNING"MSYS: " fmt, ## args) ++ ++ ++extern void Chip_Flush_Memory(void); ++ ++static int msys_open(struct inode *inode, struct file *filp); ++static int msys_release(struct inode *inode, struct file *filp); ++static long msys_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++ ++typedef struct ++{ ++ MSYS_PROC_DEVICE proc_dev; ++ void *proc_addr; ++ struct proc_dir_entry* proc_entry; ++ struct list_head list; ++} PROC_INFO_LIST; ++ ++static int msys_request_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr); ++static int msys_release_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr); ++static int msys_request_proc_dev(MSYS_PROC_DEVICE* proc_dev); ++static int msys_release_proc_dev(MSYS_PROC_DEVICE* proc_dev); ++ ++#if BENCH_MEMORY_FUNC==1 ++static void msys_bench_memory(unsigned int); ++#endif ++ ++static struct file_operations msys_fops = { ++ .owner = THIS_MODULE, ++ .open = msys_open, ++ .release = msys_release, ++ .unlocked_ioctl=msys_ioctl, ++}; ++ ++ ++static struct miscdevice sys_dev = { ++ .minor = MINOR_SYS_NUM, ++ .name = "msys", ++ .fops = &msys_fops, ++}; ++ ++static unsigned char data_part_string[32]={0}; ++static unsigned char system_part_string[32]={0}; ++ ++static unsigned char mstar_property_path[32]="/data"; ++ ++static u64 sys_dma_mask = 0xffffffffUL; ++struct list_head kept_mem_head; ++struct list_head fixed_mem_head; ++static struct mutex dmem_mutex; ++static unsigned char fixed_dmem_enabled=0; ++static unsigned char dmem_realloc_enabled=0; ++//static unsigned long dmem_lock_flags; ++ ++static unsigned int dmem_retry_interval=100; //(ms) ++static unsigned int dmem_retry_count=16; ++ ++struct DMEM_INFO_LIST ++{ ++ struct list_head list; ++ MSYS_DMEM_INFO dmem_info; ++}; ++ ++ ++//port from fs/proc/meminfo.c ++unsigned int meminfo_free_in_K(void) ++{ ++ struct sysinfo i; ++#if 0 ++ unsigned long committed; ++ struct vmalloc_info vmi; ++ long cached; ++ long available; ++ unsigned long pagecache; ++ unsigned long wmark_low = 0; ++ unsigned long pages[NR_LRU_LISTS]; ++ struct zone *zone; ++ int lru; ++#endif ++ /* ++ * display in kilobytes. ++ */ ++ #define K(x) ((x) << (PAGE_SHIFT - 10)) ++ si_meminfo(&i); ++ si_swapinfo(&i); ++#if 0 ++ committed = percpu_counter_read_positive(&vm_committed_as); ++ cached = global_page_state(NR_FILE_PAGES) - ++ total_swapcache_pages() - i.bufferram; ++ if (cached < 0) ++ cached = 0; ++ ++ get_vmalloc_info(&vmi); ++ ++ for (lru = LRU_BASE; lru < NR_LRU_LISTS; lru++) ++ pages[lru] = global_page_state(NR_LRU_BASE + lru); ++ ++ for_each_zone(zone) ++ wmark_low += zone->watermark[WMARK_LOW]; ++ ++ /* ++ * Estimate the amount of memory available for userspace allocations, ++ * without causing swapping. ++ * ++ * Free memory cannot be taken below the low watermark, before the ++ * system starts swapping. ++ */ ++ available = i.freeram - wmark_low; ++ ++ /* ++ * Not all the page cache can be freed, otherwise the system will ++ * start swapping. Assume at least half of the page cache, or the ++ * low watermark worth of cache, needs to stay. ++ */ ++ pagecache = pages[LRU_ACTIVE_FILE] + pages[LRU_INACTIVE_FILE]; ++ pagecache -= min(pagecache / 2, wmark_low); ++ available += pagecache; ++ ++ /* ++ * Part of the reclaimable slab consists of items that are in use, ++ * and cannot be freed. Cap this estimate at the low watermark. ++ */ ++ available += global_page_state(NR_SLAB_RECLAIMABLE) - ++ min(global_page_state(NR_SLAB_RECLAIMABLE) / 2, wmark_low); ++ ++ if (available < 0) ++ available = 0; ++#endif ++ return K(i.freeram); ++ ++} ++EXPORT_SYMBOL(meminfo_free_in_K); ++ ++ ++ ++//static void *mm_mem_virt = NULL; /* virtual address of frame buffer 1 */ ++ ++ ++static int msys_open(struct inode *inode, struct file *filp) ++{ ++// printk(KERN_WARNING"%s():\n", __FUNCTION__); ++ return 0; ++} ++ ++static int msys_release(struct inode *inode, struct file *filp) ++{ ++// MSYS_PRINT(KERN_WARNING"%s():\n", __FUNCTION__); ++ return 0; ++} ++ ++ ++int msys_fix_dmem(char* name) ++{ ++ int err=0; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry,*match_entry; ++ match_entry=NULL; ++ ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(name!=NULL && name[0]!=0) ++ { ++ struct DMEM_INFO_LIST *new=NULL; ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (0==strncmp(entry->dmem_info.name, name,strnlen(name,15))) ++ { ++ match_entry=entry; ++ goto BEACH; ++ } ++ } ++ ++ ++ new=(struct DMEM_INFO_LIST *)kmalloc(sizeof(struct DMEM_INFO_LIST),GFP_KERNEL); ++ if(new==NULL) ++ { ++ MSYS_ERROR("allocate memory for fixed_mem_list entry error\n" ) ; ++ err = -ENOMEM; ++ goto BEACH; ++ } ++ memset(new->dmem_info.name,0,16); ++ memcpy(new->dmem_info.name,name,strnlen(name,15)); ++ //memcpy(&new->dmem_info,&mem_info,sizeof(MSYS_DMEM_INFO)); ++ ++ list_add(&new->list, &fixed_mem_head); ++ } ++ ++BEACH: ++ mutex_unlock(&dmem_mutex); ++ return err; ++} ++ ++ ++ ++int msys_unfix_dmem(char* name) ++{ ++ ++ //MSYS_DMEM_INFO mem_info; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry,*match_entry; ++ match_entry=NULL; ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(name!=NULL && name[0]!=0) ++ { ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (0==strncmp(entry->dmem_info.name, name,strnlen(name,15))) ++ { ++ match_entry=entry; ++ break; ++ } ++ } ++ } ++ ++ if(match_entry!=NULL) ++ { ++ list_del_init(&match_entry->list); ++ kfree(match_entry); ++ } ++ ++//BEACH: ++ mutex_unlock(&dmem_mutex); ++ return 0; ++ ++} ++ ++ ++int msys_find_dmem_by_phys(unsigned long long phys,MSYS_DMEM_INFO *mem_info) ++{ ++ ++ //MSYS_DMEM_INFO mem_info; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ ++ int res=-EINVAL; ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(0!=phys) ++ { ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if ((entry->dmem_info.phys<=phys) && phys<(entry->dmem_info.phys+entry->dmem_info.length)) ++ { ++ memcpy(mem_info,&entry->dmem_info,sizeof(MSYS_DMEM_INFO)); ++ res=0; ++ goto BEACH; ++ ; ++ } ++ } ++ } ++ ++ ++BEACH: ++ mutex_unlock(&dmem_mutex); ++ return res; ++} ++ ++int msys_find_dmem_by_name(const char *name, MSYS_DMEM_INFO *mem_info) ++{ ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry, *match_entry=NULL; ++ int res=-EINVAL; ++ ++ mutex_lock(&dmem_mutex); ++ ++ if(name!=NULL && name[0]!=0) ++ { ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ res=strncmp(entry->dmem_info.name, name, 16); ++ if (0==res) ++ { ++ //MSYS_ERROR("%s: Find name\n", __func__); ++ match_entry=entry; ++ break; ++ } ++ } ++ } ++ else ++ { ++ MSYS_ERROR("%s: Invalid name\n", __func__); ++ } ++ ++ if(match_entry!=NULL) ++ { ++ memcpy(mem_info, &match_entry->dmem_info, sizeof(MSYS_DMEM_INFO)); ++ } ++ else ++ { ++ memset(mem_info->name,0,16); ++ } ++ ++ mutex_unlock(&dmem_mutex); ++ ++ return res; ++} ++ ++ ++int msys_release_dmem(MSYS_DMEM_INFO *mem_info) ++{ ++ ++ //MSYS_DMEM_INFO mem_info; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry,*match_entry; ++ ++ int dmem_fixed=0; ++ ++ mutex_lock(&dmem_mutex); ++ match_entry=NULL; ++ ++// MSYS_PRINT("\nFREEING DMEM [%s]\n\n",mem_info->name); ++ if(mem_info->name[0]!=0) ++ { ++ list_for_each(ptr, &kept_mem_head) ++ { ++ int res=0; ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ res=strncmp(entry->dmem_info.name, mem_info->name,strnlen(mem_info->name,15)); ++// MSYS_PRINT("DMEM0 [%s],%s %d\n",entry->dmem_info.name,match_entry->dmem_info.name,res); ++ if (0==res) ++ { ++ match_entry=entry; ++ break; ++ } ++ } ++ } ++ ++ ++ if(match_entry==NULL && (0!=mem_info->phys)) ++ { ++ MSYS_ERROR("WARNING!! DMEM [%s]@0x%08X can not be found by name, try to find by phys address\n",mem_info->name, (unsigned int)mem_info->phys); ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (entry->dmem_info.phys==mem_info->phys) ++ { ++ match_entry=entry; ++ break; ++ } ++ } ++ ++ } ++ ++ ++ if(match_entry==NULL) ++ { ++ MSYS_ERROR("DMEM [%s]@0x%08X not found, skipping release...\n",mem_info->name, (unsigned int)mem_info->phys); ++ goto BEACH; ++ } ++ ++ if(fixed_dmem_enabled) ++ { ++ //check if entry is fixed ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ int res=0; ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ res=strcmp(entry->dmem_info.name, match_entry->dmem_info.name); ++ if (0==res) ++ { ++ dmem_fixed=1; ++ MSYS_PRINT("DMEM [%s]@0x%08X is fixed, skipping release...\n",match_entry->dmem_info.name,(unsigned int)match_entry->dmem_info.phys); ++ goto BEACH; ++ } ++ } ++ } ++ ++ ++ dma_free_coherent(sys_dev.this_device, PAGE_ALIGN(match_entry->dmem_info.length),(void *)(uintptr_t)match_entry->dmem_info.kvirt,match_entry->dmem_info.phys); ++ ++ MSYS_PRINT("DMEM [%s]@0x%08X successfully released\n",match_entry->dmem_info.name,(unsigned int)match_entry->dmem_info.phys); ++ ++ list_del_init(&match_entry->list); ++ kfree(match_entry); ++ ++ ++ ++ ++BEACH: ++ mutex_unlock(&dmem_mutex); ++ return 0; ++ ++} ++ ++int msys_request_dmem(MSYS_DMEM_INFO *mem_info) ++{ ++ dma_addr_t phys_addr; ++ int err=0; ++ int retry=0; ++ ++ if(mem_info->name[0]==0||strlen(mem_info->name)>15) ++ { ++ MSYS_ERROR( "Invalid DMEM name!! Either garbage or empty name!!\n"); ++ return -EINVAL; ++ } ++ ++ MSYS_ERROR("DMEM request: [%s]:0x%08X\n",mem_info->name,(unsigned int)mem_info->length); ++ ++ mutex_lock(&dmem_mutex); ++// if(mem_info->name[0]!=0) ++ { ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ ++ ++ ++ list_for_each(ptr, &kept_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ if (0==strncmp(entry->dmem_info.name, mem_info->name,strnlen(mem_info->name,15))) ++ { ++ if(dmem_realloc_enabled && (entry->dmem_info.length != mem_info->length)) ++ { ++ MSYS_ERROR("dmem realloc %s", entry->dmem_info.name); ++ dma_free_coherent(sys_dev.this_device, PAGE_ALIGN(entry->dmem_info.length),(void *)(uintptr_t)entry->dmem_info.kvirt,entry->dmem_info.phys); ++ MSYS_ERROR("DMEM [%s]@0x%08X successfully released\n",entry->dmem_info.name,(unsigned int)entry->dmem_info.phys); ++ list_del_init(&entry->list); ++ break; ++ } ++ else ++ { ++ memcpy(mem_info,&entry->dmem_info,sizeof(MSYS_DMEM_INFO)); ++ MSYS_ERROR("DMEM kept entry found: name=%s, phys=0x%08X, length=0x%08X\n",mem_info->name,(unsigned int)mem_info->phys,(unsigned int)mem_info->length); ++ goto BEACH_ENTRY_FOUND; ++ } ++ } ++ } ++ ++ //MSYS_PRINT(KERN_WARNING"can not found kept direct requested memory entry name=%s\n",mem_info.name); ++ ++ } ++// else ++// { ++// MSYS_PRINT(" !!ERROR!! Anonymous DMEM request is forbidden !!\n"); ++// return -EFAULT; ++// } ++ ++ while( !(mem_info->kvirt = (u64)(uintptr_t)dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(mem_info->length), &phys_addr, GFP_KERNEL)) ) ++ { ++ if(retry >= dmem_retry_count) ++ { ++ MSYS_ERROR( "unable to allocate direct memory\n"); ++ err = -ENOMEM; ++ goto BEACH_ALLOCATE_FAILED; ++ } ++ MSYS_ERROR( "retry ALLOC_DMEM %d\n",retry); ++ sysctl_compaction_handler(NULL, 1, NULL, NULL, NULL); ++ msleep(1000); ++ retry++; ++ } ++ ++ mem_info->phys=(u64)phys_addr; ++ ++ ++ { ++ struct DMEM_INFO_LIST *new=(struct DMEM_INFO_LIST *)kmalloc(sizeof(struct DMEM_INFO_LIST),GFP_KERNEL); ++ if(new==NULL) ++ { ++ MSYS_ERROR("allocate memory for mem_list entry error\n" ) ; ++ err = -ENOMEM; ++ goto BEACH; ++ ++ } ++ ++ memset(new->dmem_info.name,0,16); ++/* ++ new->dmem_info.kvirt=mem_info->kvirt; ++ new->dmem_info.phys=mem_info->phys; ++ new->dmem_info.length=mem_info->length; ++ if(mem_info->name!=NULL){ ++ memcpy(new->dmem_info.name,mem_info->name,strnlen(mem_info->name,15)); ++ } ++*/ ++ memcpy(&new->dmem_info,mem_info,sizeof(MSYS_DMEM_INFO)); ++ ++ list_add(&new->list, &kept_mem_head); ++ ++ } ++ ++ if(retry) ++ MSYS_ERROR("DMEM request: [%s]:0x%08X success, @0x%08X (retry=%d)\n",mem_info->name,(unsigned int)mem_info->length, (unsigned int)mem_info->phys, retry); ++ else ++ MSYS_PRINT("DMEM request: [%s]:0x%08X success, @0x%08X\n",mem_info->name,(unsigned int)mem_info->length, (unsigned int)mem_info->phys, retry); ++ ++ ++BEACH: ++ if(err==-ENOMEM) ++ { ++ msys_release_dmem(mem_info); ++ } ++ ++BEACH_ALLOCATE_FAILED: ++BEACH_ENTRY_FOUND: ++ if(err) ++ { ++ MSYS_ERROR("DMEM request: [%s]:0x%08X FAILED!! (retry=%d)\n",mem_info->name,(unsigned int)mem_info->length, retry); ++ } ++ ++#if 0 ++ if(0==err){ ++ memset((void *)((unsigned int)mem_info->kvirt),0,mem_info->length); ++ Chip_Flush_CacheAll(); ++ MSYS_PRINT("DMEM CLEAR!!\n"); ++ } ++ ++#endif ++ ++ mutex_unlock(&dmem_mutex); ++ return err; ++ ++} ++ ++unsigned int get_PIU_tick_count(void) ++{ ++ return ( INREG16(0x1F006050) | (INREG16(0x1F006054)<<16) ); ++} ++ ++EXPORT_SYMBOL(get_PIU_tick_count); ++ ++int msys_user_to_physical(unsigned long addr,unsigned long *phys) ++{ ++ ++ unsigned long paddr=0; ++ struct page *page; ++ down_read(¤t->mm->mmap_sem); ++ if (get_user_pages(current, current->mm, addr, 1, 1, 0, &page, NULL) <= 0) ++ { ++ up_read(¤t->mm->mmap_sem); ++ printk(KERN_WARNING"ERR!!\n"); ++ return -EINVAL; ++ } ++ up_read(¤t->mm->mmap_sem); ++ ++ paddr= page_to_phys(page); ++ ++ *phys=paddr; ++// if(paddr>0x21E00000) ++// { ++// printk(KERN_WARNING"\nKXX:0x%08X,0x%08X\n",(unsigned int)addr,(unsigned int)paddr); ++// } ++ ++ return 0; ++} ++ ++int msys_find_dmem_by_name_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMEM_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (((MSYS_DMEM_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if( (err=msys_find_dmem_by_name(mem_info.name, &mem_info)) ) ++ { ++ //return -ENOENT; ++ } ++ ++ if(copy_to_user((void __user *)arg, (void*)&mem_info, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_request_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMEM_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (((MSYS_DMEM_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if( (err=msys_request_dmem(&mem_info)) ) ++ { ++ MSYS_ERROR("request direct memory failed!!\n" ); ++ return err; ++ } ++ if(copy_to_user((void __user *)arg, (void*)&mem_info, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_release_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMEM_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (((MSYS_DMEM_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ return msys_release_dmem(&mem_info); ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int msys_flush_cache(unsigned long arg) ++{ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_DUMMY_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DUMMY_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DUMMY_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DUMMY_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DUMMY_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DUMMY_INFO), (((MSYS_DUMMY_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ Chip_Flush_CacheAll(); ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_addr_translation_verchk(unsigned long arg, bool direction) ++{ ++ MSYS_ADDR_TRANSLATION_INFO addr_info; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_ADDR_TRANSLATION_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_ADDR_TRANSLATION_INFO), (((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&addr_info, (void __user *)arg, sizeof(addr_info))) ++ { ++ return -EFAULT; ++ } ++ ++ if(direction) ++ addr_info.addr=Chip_MIU_to_Phys(addr_info.addr); ++ else ++ addr_info.addr=Chip_Phys_to_MIU(addr_info.addr); ++ ++ if(copy_to_user((void __user *)arg, (void*)&addr_info, sizeof(addr_info))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_get_riu_map_verchk(unsigned long arg) ++{ ++ MSYS_MMIO_INFO mmio_info; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_MMIO_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS((MSYS_MMIO_INFO __user *)arg, IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_MMIO_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_MMIO_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_MMIO_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_MMIO_INFO), (((MSYS_MMIO_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( copy_from_user((void*)&mmio_info, (void __user *)arg, sizeof(MSYS_MMIO_INFO)) ) ++ { ++ return -EFAULT; ++ } ++ ++ mmio_info.addr=Chip_Get_RIU_Phys(); ++ mmio_info.size=Chip_Get_RIU_Size(); ++ ++ if( copy_to_user((void __user *)arg, (void*)&mmio_info, sizeof(MSYS_MMIO_INFO)) ) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int msys_fix_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMEM_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (((MSYS_DMEM_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if( (err=msys_fix_dmem(mem_info.name)) ) ++ { ++ MSYS_ERROR("fix direct memory failed!! %s\n", mem_info.name); ++ return err; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_unfix_dmem_verchk(unsigned long arg) ++{ ++ MSYS_DMEM_INFO mem_info; ++ int err=0; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMEM_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMEM_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMEM_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMEM_INFO), (((MSYS_DMEM_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ if( (err=msys_unfix_dmem(mem_info.name)) ) ++ { ++ MSYS_ERROR("unfix direct memory failed!! %s\n", mem_info.name); ++ return err; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int msys_miu_protect_verchk(unsigned long arg) ++{ ++ MSYS_MIU_PROTECT_INFO protect_info; ++ u64 miu_addr_start; ++ u64 miu_addr_end; ++ u32 start_unit, end_unit; ++ u8 i=0; ++ ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_MIU_PROTECT_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_MIU_PROTECT_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_MIU_PROTECT_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_MIU_PROTECT_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_MIU_PROTECT_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_MIU_PROTECT_INFO), (((MSYS_MIU_PROTECT_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&protect_info, (void __user *)arg, sizeof(MSYS_MIU_PROTECT_INFO))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ miu_addr_start = Chip_Phys_to_MIU(protect_info.phys); ++ miu_addr_end = Chip_Phys_to_MIU(protect_info.phys + protect_info.length) - 1; ++ ++ if(miu_addr_start & (0x2000-1)) /*check 8KB align*/ ++ { ++ MSYS_WARN("MIU protect start=0x%08X is not 8KB aligned!\n", (u32)miu_addr_start); ++ } ++ ++ start_unit = (u32)((miu_addr_start & ~(0x2000-1)) >> 13); // 8KB unit ++ ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_60, (u16)(start_unit & 0xFFFF)); ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_68, (INREG16(BASE_REG_MIU_PA + REG_ID_68)) | ((start_unit>>16) & 0x3)); ++ ++ if( (miu_addr_end & (0x2000-1)) != (0x2000-1) ) /*check 8KB align*/ ++ { ++ MSYS_WARN("MIU protect end=0x%08X is not 8KB aligned!\n", (u32)miu_addr_end); ++ } ++ ++ end_unit = (u32)((miu_addr_end & ~(0x2000-1)) >> 13); // 8KB unit ++ ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_61, (u16)(end_unit & 0xFFFF)); ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_68, (INREG16(BASE_REG_MIU_PA + REG_ID_68)) | (((end_unit>>16) & 0x3) << 2)); ++ ++ printk("\n\tMIU protect start=0x%08X\n", start_unit << 13); ++ printk("\tMIU protect end=0x%08X\n", ((end_unit+1) << 13) -1); ++ printk("\tMIU protect id="); ++ ++ do ++ { ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_17 + (i*2), (protect_info.id[i] & 0x7F) | (protect_info.id[i+1]&0x7F)<<8 ); ++ printk(" 0x%02X 0x%02X", protect_info.id[i], protect_info.id[i+1]); ++ i+=2; ++ } while(protect_info.id[i]!=0x00 && i<16); ++ ++ printk("\n"); ++ ++ OUTREG16(BASE_REG_MIU_PA + REG_ID_10, 0xFFFF); // for test, we set all id enable ++ ++ if(protect_info.w_protect) ++ SETREG16(BASE_REG_MIU_PA + REG_ID_69, BIT0); ++ if(protect_info.r_protect) ++ SETREG16(BASE_REG_MIU_PA + REG_ID_69, BIT4); ++ if(protect_info.inv_protect) ++ SETREG16(BASE_REG_MIU_PA + REG_ID_69, BIT8); ++ ++ printk("\tMIU protect W_protect=%d\n", protect_info.w_protect); ++ printk("\tMIU protect R_protect=%d\n", protect_info.r_protect); ++ printk("\tMIU protect INV_protect=%d\n", protect_info.inv_protect); ++ ++ return 0; ++} ++ ++#if 0 // not test yet ++int msys_user_to_physical_verchk(unsigned long arg) ++{ ++ MSYS_ADDR_TRANSLATION_INFO addr_info; ++ int res=0; ++ struct page *page; ++ int addr; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_ADDR_TRANSLATION_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_ADDR_TRANSLATION_INFO), (((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&addr, (void __user *)arg, sizeof(addr))) ++ { ++ return -EFAULT; ++ } ++ down_read(¤t->mm->mmap_sem); ++ res = get_user_pages(current, current->mm, addr, 1, 1, 0, &page, NULL); ++ if (res <= 0) ++ return -EINVAL; ++ up_read(¤t->mm->mmap_sem); ++ printk("vaddr=0x%08X\n", addr); ++ addr = page_to_phys(page); ++ printk("paddr=0x%08X\n\n", addr); ++ if(copy_to_user((void __user *)arg, (void*)&addr, sizeof(addr))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ return 0; ++} ++#endif ++ ++ ++ ++int msys_string_verchk(unsigned long arg, unsigned int op) ++{ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_STRING_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_STRING_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_STRING_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_STRING_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_STRING_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_STRING_INFO), (((MSYS_STRING_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(op==0) ++ { ++ if(copy_to_user(&(((MSYS_STRING_INFO __user *)arg)->str[0]), (void*)system_part_string, sizeof(system_part_string))) ++ { ++ return -EFAULT; ++ } ++ } ++ else if(op==1) ++ { ++ ++ if(copy_to_user(&(((MSYS_STRING_INFO __user *)arg)->str[0]), (void*)data_part_string, sizeof(data_part_string))) ++ { ++ return -EFAULT; ++ } ++ } ++ else if(op==2) ++ { ++ if(copy_to_user(&(((MSYS_STRING_INFO __user *)arg)->str[0]), (void*)mstar_property_path, sizeof(mstar_property_path))) ++ { ++ return -EFAULT; ++ } ++ } ++ else if(op==3) ++ { ++ if(copy_from_user((void*)mstar_property_path, &(((MSYS_STRING_INFO __user *)arg)->str[0]), sizeof(mstar_property_path))) ++ { ++ return -EFAULT; ++ } ++ printk("set mstar_property_path=%s\n", mstar_property_path); ++ } ++ else ++ { ++ MSYS_ERROR("[%s] unsupport op=%d!!\n", __FUNCTION__, op); ++ return -EINVAL; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++ ++extern int g_sCurrentTemp; ++ ++int msys_get_temp_verchk(unsigned long arg) ++{ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_TEMP_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_TEMP_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_TEMP_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_TEMP_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_TEMP_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_TEMP_INFO), (((MSYS_TEMP_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ int temp = g_sCurrentTemp; ++ if(copy_to_user( &(((MSYS_TEMP_INFO __user *)arg)->temp), &temp, sizeof(temp) )) ++ return -EFAULT;; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int msys_get_udid_verchk(unsigned long arg) ++{ ++ MSYS_UDID_INFO udid_info; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_UDID_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_UDID_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_UDID_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_UDID_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_UDID_INFO), (((MSYS_UDID_INFO __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user((void*)&udid_info, (void __user *)arg, sizeof(udid_info))) ++ { ++ return -EFAULT; ++ } ++ #ifdef CONFIG_ARCH_INFINITY ++ CLRREG16(BASE_REG_EFUSE_PA + REG_ID_25, BIT8); //reg_sel_read_256[8]=0 to read a/b/c/d ++ udid_info.udid = (u64)INREG16(BASE_REG_EFUSE_PA + REG_ID_16) | ++ ((u64)(INREG16(BASE_REG_EFUSE_PA + REG_ID_17)) << 16) | ++ ((u64)INREG16(BASE_REG_EFUSE_PA + REG_ID_18) << 32); ++ #elif defined CONFIG_ARCH_INFINITY3 ++ CLRREG16(BASE_REG_EFUSE_PA + REG_ID_03, BIT8); //reg_sel_read_256[8]=0 to read a/b/c/d ++ udid_info.udid = (u64)INREG16(BASE_REG_EFUSE_PA + REG_ID_16) | ++ ((u64)(INREG16(BASE_REG_EFUSE_PA + REG_ID_17)) << 16) | ++ ((u64)INREG16(BASE_REG_EFUSE_PA + REG_ID_18) << 32); ++ #else ++ MSYS_ERROR("Not implement get udid for this platform\n"); ++ #endif ++ if(copy_to_user((void __user *)arg, (void*)&udid_info, sizeof(udid_info))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] No verchk header !!!\33[0m\n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++#if 0 ++#define CHK_NUM_WAITDONE 20000 ++ ++static int msys_dma_by_BDMA(unsigned long arg) ++{ ++ MSYS_DMA_INFO mem_info; ++ U16 u16data; ++ U32 u32Timer = 0; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMA_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMA_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMA_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMA_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMA_INFO), (((MSYS_DMA_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMEM_INFO))) ++ { ++ return -EFAULT; ++ } ++ //Set source and destination path ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_00, 0x0000); ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_02, 0x4040); ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_04, (Chip_Phys_to_MIU(mem_info.kphy_src) & 0x0000FFFF)); ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_05, (Chip_Phys_to_MIU(mem_info.kphy_src)>>16)); ++ // Set end address ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_06, (Chip_Phys_to_MIU(mem_info.kphy_des) & 0x0000FFFF)); ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_07, (Chip_Phys_to_MIU(mem_info.kphy_des) >> 16)); ++ //Set Size ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_08, (mem_info.length & 0x0000FFFF)); ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_09, (mem_info.length >> 16)); ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_00, 0x1); ++ ++ do ++ { ++ //check done ++ u16data = INREG16(BASE_REG_BDMA1_PA + REG_ID_01); ++ if(u16data & 0x8) ++ { ++ //clear done ++ OUTREG16(BASE_REG_BDMA1_PA + REG_ID_01, 0x8); ++ break; ++ } ++ ++ if (++u32Timer%1000 == 0) ++ cond_resched(); ++ }while(u32Timer < CHK_NUM_WAITDONE); ++ Chip_Flush_Memory(); ++ } ++ } ++ return 0; ++} ++ ++ ++#include "halAESDMA.c" ++ ++static int msys_dma_by_ADMA(unsigned long arg) ++{ ++ MSYS_DMA_INFO mem_info; ++ ++ if ( CHK_VERCHK_HEADER(&(((MSYS_ADDR_TRANSLATION_INFO __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS(&(((MSYS_DMA_INFO __user *)arg)->VerChk_Version), IOCTL_MSYS_VERSION) ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] verchk version (%04x) < ioctl verision (%04x) !!!\33[0m\n", __FUNCTION__, ++ ((MSYS_DMA_INFO __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, IOCTL_MSYS_VERSION); ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE(&(((MSYS_DMA_INFO __user *)arg)->VerChk_Size), sizeof(MSYS_DMA_INFO)) == 0 ) ++ { ++ VERCHK_ERR("\n\33[1;31m[%s] struct size(%04x) != verchk size(%04x) !!!\33[0m\n", __FUNCTION__, ++ sizeof(MSYS_DMA_INFO), (((MSYS_DMA_INFO __user *)arg)->VerChk_Size)); ++ return -EINVAL; ++ } ++ ++ ++ if(copy_from_user((void*)&mem_info, (void __user *)arg, sizeof(MSYS_DMA_INFO))) ++ { ++ return -EFAULT; ++ } ++ ++ OUTREG16(BASE_REG_CLKGEN_PA + REG_ID_61, 0x14); ++ HAL_AESDMA_Enable(0); ++ HAL_AESDMA_Reset(); ++ HAL_AESDMA_SetFileinAddr(Chip_Phys_to_MIU(mem_info.kphy_src)); ++ HAL_AESDMA_SetXIULength(mem_info.length); ++ HAL_AESDMA_SetFileoutAddr(Chip_Phys_to_MIU(mem_info.kphy_des),(mem_info.length)); ++ HAL_AESDMA_FileOutEnable(1); ++ HAL_AESDMA_Start(1); ++ ++ while((HAL_AESDMA_GetStatus() & AESDMA_CTRL_DMA_DONE) != AESDMA_CTRL_DMA_DONE) ++ { ++ } ++ ++ Chip_Flush_MIU_Pipe(); ++ HAL_AESDMA_Reset(); ++ } ++ } ++ return 0; ++} ++ ++#endif ++ ++static long msys_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ int err= 0; ++ ++ // wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ if (_IOC_TYPE(cmd) != MSYS_IOCTL_MAGIC) return -ENOTTY; ++ if (_IOC_NR(cmd) > IOCTL_SYS_MAXNR) return -ENOTTY; ++ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ ++ ++ switch(cmd) ++ { ++ case IOCTL_MSYS_REQUEST_DMEM: ++ { ++ if((err=msys_request_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_REQUEST_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_RELEASE_DMEM: ++ { ++ if((err=msys_release_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_RELEASE_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_FLUSH_CACHE: ++ { ++ if((err = msys_flush_cache(arg))) ++ MSYS_ERROR("IOCTL_MSYS_FLUSH_CACHE error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_PHYS_TO_MIU: ++ { ++ if((err=msys_addr_translation_verchk(arg, 0))) ++ MSYS_ERROR("IOCTL_MSYS_PHYS_TO_MIU error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_MIU_TO_PHYS: ++ { ++ if((err=msys_addr_translation_verchk(arg, 1))) ++ MSYS_ERROR("IOCTL_MSYS_MIU_TO_PHYS error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_RIU_MAP: ++ { ++ if((err=msys_get_riu_map_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_GET_RIU_MAP error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_FIX_DMEM: ++ { ++ if((err=msys_fix_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_FIX_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_UNFIX_DMEM: ++ { ++ if((err=msys_unfix_dmem_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_UNFIX_DMEM error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_FIND_DMEM_BY_NAME: ++ { ++// if((err=msys_find_dmem_by_name_verchk(arg))) ++// MSYS_ERROR("IOCTL_MSYS_FIND_DMEM_BY_NAME error!\n"); ++ msys_find_dmem_by_name_verchk(arg); ++ err=0; ++ } ++ break; ++ ++ case IOCTL_MSYS_MIU_PROTECT: ++ { ++ if((err=msys_miu_protect_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_MIU_PROTECT error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_USER_TO_PHYSICAL: ++ { ++ unsigned long addr,paddr; ++ ++ ++ if(copy_from_user((void*)&addr, (void __user *)arg, sizeof(addr))) ++ { ++ return -EFAULT; ++ } ++ ++ if((err=msys_user_to_physical(addr,&paddr))) ++ MSYS_ERROR("IOCTL_MSYS_GET_USER_PAGE error!\n"); ++ ++ if(copy_to_user((void __user *)arg, (void*)&paddr, sizeof(paddr))) ++ { ++ return -EFAULT; ++ } ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_SYSP_STRING: ++ { ++ if((err=msys_string_verchk(arg, 0))) ++ MSYS_ERROR("IOCTL_MSYS_GET_SYSP_STRING error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_DATAP_STRING: ++ { ++ if((err=msys_string_verchk(arg, 1))) ++ MSYS_ERROR("IOCTL_MSYS_GET_DATAP_STRING error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_PROPERTY_PATH: ++ { ++ if((err=msys_string_verchk(arg, 2))) ++ MSYS_ERROR("IOCTL_MSYS_GET_PROPERTY_PATH error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_SET_PROPERTY_PATH: ++ { ++ if((err=msys_string_verchk(arg, 3))) ++ MSYS_ERROR("IOCTL_MSYS_SET_PROPERTY_PATH error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_US_TICKS: ++ { ++ ++// u64 us_ticks=Chip_Get_US_Ticks(); ++// ++// if(copy_to_user((void __user *)arg, (void*)&us_ticks, sizeof(us_ticks))) ++// { ++// return -EFAULT; ++// } ++ return -EPERM; ++ } ++ break; ++ ++ case IOCTL_MSYS_GET_UDID: ++ { ++ if((err=msys_get_udid_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_GET_UDID error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_PRINT_PIU_TIMER_TICKS: ++ { ++ int id=arg; ++ printk(KERN_WARNING"PIU_T:%X#%d#\n",get_PIU_tick_count(),id); ++ } ++ break; ++ ++ case IOCTL_MSYS_BENCH_MEMORY: ++ { ++#if BENCH_MEMORY_FUNC==1 ++ int test_mem_size_in_MB=arg; ++ msys_bench_memory((unsigned int)test_mem_size_in_MB); ++#endif ++ } ++ break; ++ ++ case IOCTL_MSYS_RESET_TO_UBOOT: ++ { ++ do ++ { ++ SETREG16(REG_ADDR_STATUS, FORCE_UBOOT_BIT); ++ } while(!(INREG16(REG_ADDR_STATUS) & FORCE_UBOOT_BIT)); ++ OUTREG16(BASE_REG_PMSLEEP_PA + REG_ID_2E, 0x79); ++ } ++ break; ++ ++ case IOCTL_MSYS_READ_PM_TSENSOR: ++ { ++#if 0 ++ if((err=msys_get_temp_verchk(arg))) ++ MSYS_ERROR("IOCTL_MSYS_READ_PM_TSENSOR error!\n"); ++#else ++ int temp = g_sCurrentTemp; ++ if(copy_to_user( (void __user *)arg, &temp, sizeof(temp) )) ++ return -EFAULT; ++#endif ++ } ++ break; ++ ++ case IOCTL_MSYS_REQUEST_PROC_DEVICE: ++ { ++ MSYS_PROC_DEVICE proc_dev; ++ if(copy_from_user((void*)&proc_dev, (void __user *)arg, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ ++ if((err = msys_request_proc_dev(&proc_dev)) == -EEXIST) { ++ MSYS_PRINT("skip since device %s exist\n" , proc_attr->name); ++ } else if(err != 0) { ++ MSYS_ERROR("msys_request_proc_dev failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_dev, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_RELEASE_PROC_DEVICE: ++ { ++ MSYS_PROC_DEVICE proc_dev; ++ if(copy_from_user((void*)&proc_dev, (void __user *)arg, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ ++ if((err = msys_release_proc_dev(&proc_dev)) != 0) { ++ MSYS_ERROR("msys_release_proc_dev failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_dev, sizeof(MSYS_PROC_DEVICE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_REQUEST_PROC_ATTRIBUTE: ++ { ++ MSYS_PROC_ATTRIBUTE proc_attr; ++ ++ if(copy_from_user((void*)&proc_attr, (void __user *)arg, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ ++ if((err = msys_request_proc_attr(&proc_attr)) == -EEXIST) { ++ MSYS_PRINT("skip since attribute %s exist\n" , proc_attr->name); ++ } else if(err != 0) { ++ MSYS_ERROR("msys_request_proc_attribute failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_attr, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_RELEASE_PROC_ATTRIBUTE: ++ { ++ MSYS_PROC_ATTRIBUTE proc_attr; ++ ++ if(copy_from_user((void*)&proc_attr, (void __user *)arg, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ ++ if((err = msys_release_proc_attr(&proc_attr)) != 0) { ++ MSYS_ERROR("msys_release_proc_attr failed!!\n" ); ++ break; ++ } ++ ++ if(copy_to_user((void*)arg, (void*)&proc_attr, sizeof(MSYS_PROC_ATTRIBUTE))) ++ BUG(); ++ } ++ break; ++ ++ case IOCTL_MSYS_FLUSH_MEMORY: ++ { ++ __cpuc_flush_kern_all();//L1 ++ Chip_Flush_Memory();//L3 ++ } ++ break; ++#if 0 ++ case IOCTL_MSYS_BDMA: ++ { ++ if((err = msys_dma_by_BDMA(arg))) ++ MSYS_ERROR("IOCTL_MSYS_BDMA error!\n"); ++ } ++ break; ++ ++ case IOCTL_MSYS_ADMA: ++ { ++ if((err = msys_dma_by_ADMA(arg))) ++ MSYS_ERROR("IOCTL_MSYS_ADMA error!\n"); ++ } ++ break; ++#endif ++ ++ default: ++ MSYS_ERROR("Unknown IOCTL Command 0x%08X\n", cmd); ++ return -ENOTTY; ++ } ++ ++ ++ return err; ++} ++ ++ ++ ++#if BENCH_MEMORY_FUNC==1 ++typedef unsigned int volatile ulv; ++typedef unsigned long int volatile ullv; ++ ++/****************************************** ++ * Function prototypes and Global variables ++ ******************************************/ ++//int TEST_SolidBitsComparison(ulv *pSrc, ulv *pDest, unsigned int nCount); ++ ++ ++/****************************************** ++ * Extern ++ ******************************************/ ++ ++/****************************************** ++ * Functions ++ ******************************************/ ++ ++static int TEST_Memwrite(ulv * pDest, unsigned int nCount) ++{ ++ register unsigned int val = 0xA5A4B5B4; ++ ulv *p2 = NULL; ++ unsigned int nTest, i; ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p2 = (ulv *) pDest; ++ for (i = 0; i < nCount; i++) ++ *p2++ = val; ++ } ++ return nTest; ++} ++ ++static int TEST_Memread(ulv * pSrc, unsigned int nCount) ++{ ++ register unsigned int val; ++ ulv *p1 = NULL; ++ unsigned int nTest, i; ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ for (i = 0; i < nCount; i++) ++ val = *p1++; ++ } ++ return nTest; ++} ++ ++static int TEST_Memcpy_mips(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ int nTest = 0; ++// for (nTest = 0; nTest < 10; nTest++) ++// memcpy_MIPS((void*)pDest, (void*)pSrc, nCount*sizeof(unsigned int)); ++ return nTest; ++} ++ ++static int TEST_Memcpy(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ int nTest; ++ for (nTest = 0; nTest < 10; nTest++) ++ memcpy((void*)pDest, (void*)pSrc, nCount*sizeof(unsigned int)); ++ return nTest; ++} ++ ++static int TEST_MemBandWidth_long(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ ullv *p1 = NULL; ++ ullv *p2 = NULL; ++ unsigned int i; ++ unsigned int nTest; ++ ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p1 = (ullv *) pSrc; ++ p2 = (ullv *) pDest; ++ ++ for (i = 0; i < nCount; i++) ++ *p2++ = *p1++; ++ } ++ ++ return nTest; ++} ++ ++int TEST_MemBandWidth(ulv * pSrc, ulv * pDest, unsigned int nCount) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ unsigned int i; ++ unsigned int nTest; ++ ++ for (nTest = 0; nTest < 10; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ ++ for (i = 0; i < nCount; i++) ++ *p2++ = *p1++; ++ } ++ ++ return nTest; ++} ++ ++ ++int TEST_MemBandWidthRW(ulv * pSrc, ulv * pDest, unsigned int nCount, unsigned int step_size) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ //unsigned int i; ++ unsigned int nTest; ++ int Count; ++ ++ for (nTest = 0; nTest < 10 * step_size; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ Count = nCount / step_size; ++ //memcpy((void*)p2, (void*)p1, nCount*4); ++ while(Count--) ++ { ++ *p2 = *p1; ++ p2 += step_size; ++ p1 += step_size; ++ } ++ } ++ ++ return nTest; ++} ++ ++static int TEST_MemBandWidthR(ulv * pSrc, ulv * pDest, unsigned int nCount, unsigned int step_size) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ //unsigned int i; ++ unsigned int nTest; ++ int Count; ++ ++ for (nTest = 0; nTest < 10 * step_size; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ Count = nCount / step_size; ++ //memcpy((void*)p2, (void*)p1, nCount*4); ++ while(Count--) ++ { ++ *p2 = *p1; ++ p1 += step_size; ++ } ++ } ++ ++ return nTest; ++} ++ ++static int TEST_MemBandWidthW(ulv * pSrc, ulv * pDest, unsigned int nCount, unsigned int step_size) ++{ ++ ulv *p1 = NULL; ++ ulv *p2 = NULL; ++ //unsigned int i; ++ unsigned int nTest; ++ int Count; ++ ++ for (nTest = 0; nTest < 10 * step_size; nTest++) ++ { ++ p1 = (ulv *) pSrc; ++ p2 = (ulv *) pDest; ++ Count = nCount / step_size; ++ //memcpy((void*)p2, (void*)p1, nCount*4); ++ while(Count--) ++ { ++ *p2 = *p1; ++ p2 += step_size; ++ } ++ } ++ ++ return nTest; ++} ++ ++ ++ ++static void msys_bench_memory(unsigned int uMemSize) ++{ ++ unsigned int nLoop = 0; ++ unsigned int nAllocBytes; ++ unsigned int nBufSize; ++ unsigned int nCount; ++ unsigned int PAGE_MASK1 = 0x0FFF; ++ void *pBuf = NULL; ++ volatile void *pAlignedBuf = NULL; ++ volatile unsigned int *pSrc; ++ volatile unsigned int *pDest; ++ unsigned int bus_addr; ++ struct timespec tss, tse; ++ int nDelay; ++ int nTestCount = 0; ++ int nSize; ++ int i = 0; ++ ++ nBufSize = (unsigned int) (uMemSize << 20); ++ nAllocBytes = nBufSize + 4096; ++ ++ MSYS_WARNING("\n>>>> sys_memory_benchmark0\n"); ++ pBuf=dma_alloc_coherent(sys_dev.this_device, PAGE_ALIGN(nAllocBytes), &bus_addr, GFP_KERNEL); ++ ++ if(pBuf==NULL) ++ { ++ MSYS_ERROR("error while allocating DMA buffer for benchmark...\n"); ++ return; ++ } ++ ++ MSYS_WARNING(" Allocated %d bytes at 0x%08x\n", nAllocBytes, (unsigned int) pBuf); ++ ++ if ((unsigned int) pBuf % 4096) { ++ pAlignedBuf = (void volatile *) (((unsigned int) pBuf + 4096) ++ & PAGE_MASK1); ++ MSYS_WARNING(" Aligned at 0x%08x\n", (unsigned int) pAlignedBuf); ++ } else { ++ pAlignedBuf = pBuf; ++ } ++ ++ /* Show information */ ++ nCount = (nBufSize / 2) / sizeof(unsigned int); ++ ++ pSrc = (ulv *) pAlignedBuf; ++ pDest = (ulv *) ((unsigned int) pAlignedBuf + (nBufSize / 2)); ++ ++ MSYS_WARNING(" Read from : %p\n", pSrc); ++ MSYS_WARNING(" Write to : %p\n", pDest); ++ ++ nSize = nCount * sizeof(unsigned int); ++ ++ MSYS_WARNING(" Size : %x\n", nSize); ++ ++ MSYS_WARNING("\nMemory read/write test\n"); ++ nLoop = 0; ++ ++ MSYS_WARNING("\n(1) Memory read/write test through 32-bit pointer access\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_MemBandWidth(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8MSYS_WARNINGs, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(2) Memory read/write test through 32-bit pointer access\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_MemBandWidth_long(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(3) Memory read/write test through memcpy()\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memcpy(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(4) Memory read/write test through memcpy(prefetch version)\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memcpy_mips(pSrc, pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", ++ nLoop, nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(5) Memory read test\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memread(pSrc, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", nLoop, ++ nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ MSYS_WARNING("\n(6) Memory write test\n"); ++ ++ tss = CURRENT_TIME; ++ nTestCount = TEST_Memwrite(pDest, nCount); ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Write %3d: %d times, %8d bytes, %4d msec => %6d KB/sec\n", nLoop, ++ nTestCount, nSize, nDelay, ++ (((nSize * nTestCount) / 1024) * 1000) / nDelay); ++ ++ //============================= ++ ++ MSYS_WARNING("\n(7) Memory read/write test\n"); ++ ++ for (i = 1; i < 513; i = i << 1) ++ { ++ tss = CURRENT_TIME; ++ ++ nTestCount = TEST_MemBandWidthRW(pSrc, pDest, nCount, i); ++ ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read/Write %8d bytes, skip %4d bytes %4d msec => %6d KB/sec\n", ++ nSize, i * 4, nDelay, ++ ((((nSize / i) * nTestCount) / 1024) * 1000) / nDelay); ++ } ++ ++ MSYS_WARNING("\n(8) Memory read test\n"); ++ ++ for (i = 1; i < 513; i = i << 1) ++ { ++ tss = CURRENT_TIME; ++ ++ nTestCount = TEST_MemBandWidthR(pSrc, pDest, nCount, i); ++ ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Read %8d bytes, skip %4d bytes %4d msec => %6d KB/sec\n", ++ nSize, i * 4, nDelay, ++ ((((nSize / i) * nTestCount) / 1024) * 1000) / nDelay); ++ } ++ ++ MSYS_WARNING("\n(9) Memory write test\n"); ++ ++ for (i = 1; i < 513; i = i << 1) ++ { ++ tss = CURRENT_TIME; ++ ++ nTestCount = TEST_MemBandWidthW(pSrc, pDest, nCount, i); ++ ++ tse = CURRENT_TIME; ++ ++ nDelay = (tse.tv_sec - tss.tv_sec) * 1000 + tse.tv_nsec / 1000000 ++ - tss.tv_nsec / 1000000; ++ ++ MSYS_WARNING("Write %8d bytes, skip %4d bytes %4d msec => %6d KB/sec\n", ++ nSize, i * 4, nDelay, ++ ((((nSize / i) * nTestCount) / 1024) * 1000) / nDelay); ++ } ++ ++ ++ MSYS_WARNING("\n<<<< sys_memory_benchmark0\n"); ++ dma_free_coherent(sys_dev.this_device, nAllocBytes,pBuf,bus_addr); ++ // munlock((void *) pBuf, nAllocBytes); ++ // free((void *) pBuf); ++} ++ ++#endif ++ ++static int __init setup_system_part_string(char *arg) ++{ ++ memcpy(system_part_string,(arg+1),strlen(arg)dmem_info.length,(unsigned int)entry->dmem_info.phys,entry->dmem_info.name); ++ ++ total+=(unsigned int)entry->dmem_info.length; ++ i++; ++ } ++ ++ str += scnprintf(str, end - str, "\nTOTAL: 0x%08X\n\n",total); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(dmem, 0444, dmem_show, NULL); ++ ++ ++static ssize_t release_dmem_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ int error = 0; ++ const char *str = buf; ++ MSYS_DMEM_INFO mem_info; ++ memset(mem_info.name,0,16); ++ mem_info.phys=0; ++ ++ ++ ++ while (*str && !isspace(*str)) str++; ++ ++ len = str - buf; ++ if (!len) return -EINVAL; ++ ++ len=(len<15)?len:15; ++ memcpy(mem_info.name,buf,len); ++ ++ error = msys_release_dmem(&mem_info); ++ return n; ++ } ++ ++ return 0; ++} ++ ++DEVICE_ATTR(release_dmem, 0200, NULL, release_dmem_store); ++ ++static ssize_t dmem_realloc_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", dmem_realloc_enabled); ++ return (str - buf); ++} ++ ++static ssize_t dmem_realloc_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ ++ if(1==len) ++ { ++ if('0'==buf[0]) ++ { ++ dmem_realloc_enabled=0; ++ MSYS_PRINT("dmem realloc disabled\n"); ++ } ++ else if('1'==buf[0]) ++ { ++ dmem_realloc_enabled=1; ++ MSYS_PRINT("dmem realloc enabled\n"); ++ } ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++ ++ ++DEVICE_ATTR(dmem_realloc, 0644, dmem_realloc_show, dmem_realloc_store); ++ ++ ++static ssize_t unfix_dmem_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ int error = 0; ++ const char *str = buf; ++ char nbuf[16]={0}; ++ ++ ++ while (*str && !isspace(*str)) str++; ++ ++ len = str - buf; ++ if (!len) return -EINVAL; ++ ++ len=(len<15)?len:15; ++ memcpy(nbuf,buf,len); ++ ++ error = msys_unfix_dmem(nbuf); ++ return error ? error : n; ++ } ++ ++ return 0; ++} ++ ++DEVICE_ATTR(unfix_dmem, 0200, NULL, unfix_dmem_store); ++ ++static ssize_t fixed_dmem_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ int error = 0; ++ const char *str = buf; ++ char nbuf[16]={0}; ++ ++ ++ while (*str && !isspace(*str)) str++; ++ ++ len = str - buf; ++ if (!len) return -EINVAL; ++ ++ len=(len<15)?len:15; ++ memcpy(nbuf,buf,len); ++ ++ if(1==len){ ++ if('0'==nbuf[0]){ ++ fixed_dmem_enabled=0; ++ MSYS_ERROR("fix_dmem disabled\n" ) ; ++ }else if('1'==nbuf[0]){ ++ fixed_dmem_enabled=1; ++ MSYS_ERROR("fix_dmem enabled\n" ) ; ++ } ++ } ++ ++ error = msys_fix_dmem((char *)nbuf); ++ return error ? error : n; ++ } ++ ++ return 0; ++} ++ ++static ssize_t fixed_dmem_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ struct list_head *ptr; ++ struct DMEM_INFO_LIST *entry; ++ int i=0; ++ ++ list_for_each(ptr, &fixed_mem_head) ++ { ++ entry = list_entry(ptr, struct DMEM_INFO_LIST, list); ++ str += scnprintf(str, end - str, "%04d: %s\n",i,entry->dmem_info.name); ++ i++; ++ } ++ if (str > buf) str--; ++ ++ str += scnprintf(str, end - str, "\n"); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(fixed_dmem, 0644, fixed_dmem_show, fixed_dmem_store); ++ ++ ++static ssize_t PIU_T_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%X\n",get_PIU_tick_count()); ++ ++ return (str - buf); ++} ++ ++DEVICE_ATTR(PIU_T, 0444, PIU_T_show, NULL); ++ ++static ssize_t dmem_retry_interval_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ dmem_retry_interval = simple_strtoul(buf, NULL, 10); ++ MSYS_ERROR("dmem_retry_interval=%d\n", dmem_retry_interval); ++ return n; ++ ++ /* ++ if('0'==buf[0]) ++ { ++ cma_monitor_enabled=0; ++ return n; ++ } ++ else if('1'==buf[0]) ++ { ++ cma_monitor_enabled=1; ++ return n; ++ } ++ else ++ { ++ return -EINVAL; ++ }*/ ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t dmem_retry_interval_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", dmem_retry_interval); ++ return (str - buf); ++} ++DEVICE_ATTR(dmem_retry_interval, 0644, dmem_retry_interval_show, dmem_retry_interval_store); ++ ++static ssize_t dmem_retry_count_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ dmem_retry_count = simple_strtoul(buf, NULL, 10); ++ MSYS_ERROR("dmem_retry_count=%d\n", dmem_retry_count); ++ return n; ++ /* ++ if('0'==buf[0]) ++ { ++ cma_monitor_enabled=0; ++ return n; ++ } ++ else if('1'==buf[0]) ++ { ++ cma_monitor_enabled=1; ++ return n; ++ } ++ else ++ { ++ return -EINVAL; ++ }*/ ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t dmem_retry_count_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", dmem_retry_count); ++ return (str - buf); ++} ++DEVICE_ATTR(dmem_retry_count, 0644, dmem_retry_count_show, dmem_retry_count_store); ++ ++ ++struct list_head proc_info_head; ++static struct mutex proc_info_mutex; ++static struct proc_dir_entry* proc_class=NULL; ++static struct proc_dir_entry* proc_zen_kernel=NULL; ++ ++struct proc_dir_entry* msys_get_proc_class(void) ++{ ++ return proc_class; ++} ++ ++struct proc_dir_entry* msys_get_proc_zen_kernel(void) ++{ ++ return proc_zen_kernel; ++} ++ ++static int msys_seq_show(struct seq_file*m, void *p) ++{ ++ struct inode *inode = (struct inode *)m->private; ++ ++ PROC_INFO_LIST *proc_list = proc_get_parent_data(inode); ++ MSYS_PROC_ATTRIBUTE* proc_attr = PDE_DATA(inode); ++ ++ switch(proc_attr->type) ++ { ++ case MSYS_PROC_ATTR_CHAR: ++ seq_printf(m, "%c\n", *(unsigned int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_UINT: ++ seq_printf(m, "%u\n", *(unsigned int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_INT: ++ seq_printf(m, "%d\n", *(int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_XINT: ++ seq_printf(m, "0x%x\n", *(unsigned int *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_ULONG: ++ seq_printf(m, "%lu\n", *(unsigned long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_LONG: ++ seq_printf(m, "%ld\n", *(long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_XLONG: ++ seq_printf(m, "0x%lx\n", *(unsigned long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_ULLONG: ++ seq_printf(m, "%llu\n", *(unsigned long long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_LLONG: ++ seq_printf(m, "%lld\n", *(long long *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_XLLONG: ++ seq_printf(m, "0x%llx\n", *(unsigned long long*)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ case MSYS_PROC_ATTR_STRING: ++ seq_printf(m, "%s\n", (unsigned char *)(proc_list->proc_addr + proc_attr->offset)); ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static int msys_proc_open(struct inode *inode, struct file *file) ++{ ++ return single_open(file, msys_seq_show, inode); ++} ++ ++static int msys_proc_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ int ret = 0; ++ struct page *page = NULL; ++ ++ struct inode *inode = (struct inode *)(((struct seq_file *)file->private_data)->private); ++ ++ PROC_INFO_LIST *proc_list = proc_get_parent_data(inode); ++ ++ size_t size = vma->vm_end - vma->vm_start; ++ ++ if (size > proc_list->proc_dev.size) ++ { ++ MSYS_ERROR("msys_proc_mmap - invalid size = %d\n", size); ++ return -EINVAL; ++ } ++ ++ page = virt_to_page((unsigned long)proc_list->proc_addr + (vma->vm_pgoff << PAGE_SHIFT)); ++ ret = remap_pfn_range(vma, vma->vm_start, page_to_pfn(page), size, vma->vm_page_prot); ++ if (ret) ++ { ++ MSYS_ERROR("msys_proc_mmap - remap_pfn_range failed.\n"); ++ return ret; ++ } ++ //vma->vm_start = (unsigned long)info_addr; ++ //vma->vm_end = vma->vm_start + PAGE_ALIGN(MAX_LEN); ++ //vma->vm_flags |= VM_SHARED | VM_WRITE | VM_READ; ++ ++ //vma->vm_ops = &rpr_vm_ops; ++ ++ //if (remap_page_range(start, page, PAGE_SIZE, PAGE_SHARED)) ++ // return -EAGAIN; ++ return 0 ; ++} ++ ++static const struct file_operations msys_proc_fops = { ++ .owner = THIS_MODULE, ++ .open = msys_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++}; ++ ++static const struct file_operations msys_proc_mmap_fops = { ++ .owner = THIS_MODULE, ++ .open = msys_proc_open, ++ .mmap = msys_proc_mmap, ++ .release = single_release, ++}; ++ ++static PROC_INFO_LIST *msys_get_proc_info(MSYS_PROC_DEVICE* proc_dev) ++{ ++ struct list_head *tmp_proc_entry = NULL; ++ PROC_INFO_LIST *tmp_proc_info = NULL; ++ ++ list_for_each(tmp_proc_entry, &proc_info_head) { ++ tmp_proc_info = list_entry(tmp_proc_entry, PROC_INFO_LIST, list); ++ if (tmp_proc_info->proc_dev.parent == proc_dev->parent ++ && strcmp(tmp_proc_info->proc_dev.name, proc_dev->name) == 0) { ++ //MSYS_ERROR("%s: Find %s handle = %p\n", __func__, proc_dev->name, tmp_proc_info); ++ return tmp_proc_info; ++ } ++ } ++ return NULL; ++} ++ ++static PROC_INFO_LIST *msys_get_child_proc_info(PROC_INFO_LIST *parent_proc_info) ++{ ++ struct list_head *tmp_proc_entry = NULL; ++ PROC_INFO_LIST *tmp_proc_info = NULL; ++ ++ list_for_each(tmp_proc_entry, &proc_info_head) { ++ tmp_proc_info = list_entry(tmp_proc_entry, PROC_INFO_LIST, list); ++ if (tmp_proc_info->proc_dev.parent == parent_proc_info) { ++ //MSYS_ERROR("%s; Find %s has child %s = %p\n", __func__, parent_proc_info->proc_dev.name, tmp_proc_info->proc_dev.name, tmp_proc_info); ++ return tmp_proc_info; ++ } ++ } ++ return NULL; ++} ++ ++static int msys_request_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr) ++{ ++ int err = 0; ++ struct proc_dir_entry* tmp_proc_entry; ++ PROC_INFO_LIST *parent_proc_info; ++ MSYS_PROC_ATTRIBUTE *new_proc_attr; ++ ++ mutex_lock(&proc_info_mutex); ++ if(/*proc_attr->name != NULL &&*/ proc_attr->name[0] != 0) { ++ new_proc_attr = (MSYS_PROC_ATTRIBUTE *)kmalloc(sizeof(MSYS_PROC_ATTRIBUTE), GFP_KERNEL); ++ if (!new_proc_attr) { ++ MSYS_ERROR("kmalloc MSYS_PROC_ATTRIBUTE failed!!\n" ); ++ BUG(); ++ } ++ *new_proc_attr = *proc_attr; //It will be freed when release device/attributes. ++ ++ parent_proc_info = new_proc_attr->handle; ++ tmp_proc_entry = proc_create_data(new_proc_attr->name, 0, parent_proc_info->proc_entry, &msys_proc_fops, new_proc_attr); ++ if (!tmp_proc_entry) { ++ //MSYS_ERROR("Skip since attribute %s exists\n", proc_attr->name); ++ err = -EEXIST; ++ kfree(new_proc_attr); ++ } else { ++ //MSYS_ERROR("Set attribute %s handle = %p\n", proc_attr->name, proc_attr->handle); ++ } ++ } ++ mutex_unlock(&proc_info_mutex); ++ return err; ++} ++ ++static int msys_release_proc_attr(MSYS_PROC_ATTRIBUTE* proc_attr) ++{ ++ return 0; ++} ++ ++static int msys_request_proc_dev(MSYS_PROC_DEVICE* proc_dev) ++{ ++ int err = 0; ++ PROC_INFO_LIST *new_proc_info = NULL; ++ ++ mutex_lock(&proc_info_mutex); ++ ++ if(/*proc_dev->name != NULL && */proc_dev->name[0] != 0) { ++ if((proc_dev->handle = msys_get_proc_info(proc_dev)) != NULL) { ++ //MSYS_ERROR("Device proc_info %s exist, return original handle = %p\n" , proc_dev->name, proc_dev->handle); ++ err = -EEXIST; ++ goto GG; ++ } ++ ++ new_proc_info = (PROC_INFO_LIST *)kmalloc(sizeof(PROC_INFO_LIST), GFP_KERNEL); ++ if (!new_proc_info) { ++ MSYS_ERROR("kmalloc PROC_INFO_LIST failed!!\n" ); ++ err = -ENOMEM; ++ goto GG; ++ } ++ ++ new_proc_info->proc_entry = proc_mkdir_data(proc_dev->name, 0, ++ (proc_dev->parent)?((PROC_INFO_LIST *)proc_dev->parent)->proc_entry:proc_class, new_proc_info); ++ if (!new_proc_info->proc_entry) { ++ MSYS_ERROR("Skip since device proc_entry %s exists\n", proc_dev->name); ++ err = -EEXIST; ++ kfree(new_proc_info); ++ goto GG; ++ } ++ ++ if (proc_dev->parent && proc_dev->size == 0) { //subdevice case ++ new_proc_info->proc_addr = ((PROC_INFO_LIST *)proc_dev->parent)->proc_addr; ++ } ++ else { //device case ++ if (proc_dev->size & ~PAGE_MASK) { ++ proc_dev->size &= PAGE_MASK; ++ proc_dev->size += PAGE_SIZE; ++ //MSYS_ERROR("Size not align with %ld, resize to %ld\n", PAGE_SIZE, proc_dev->size); ++ } ++ if(proc_dev->size > KMALLOC_MAX_SIZE) ++ { ++ MSYS_ERROR("allocate %lu kernel memory for proc data error\n", proc_dev->size); ++ err = -ENOMEM; ++ kfree(new_proc_info); ++ goto GG; ++ } ++ new_proc_info->proc_addr = kmalloc(proc_dev->size, GFP_KERNEL); ++ if(!new_proc_info->proc_addr) { ++ MSYS_ERROR("allocate %lu kernel memory for proc data error\n", proc_dev->size); ++ err = -ENOMEM; ++ kfree(new_proc_info); ++ goto GG; ++ } ++ proc_create(".mmap", 0, new_proc_info->proc_entry, &msys_proc_mmap_fops); //It will be freed when relealse device. ++ } ++ ++ proc_dev->handle = new_proc_info; ++ new_proc_info->proc_dev = *proc_dev; ++ list_add(&new_proc_info->list, &proc_info_head); ++ //MSYS_ERROR("Set device %s handle = %p\n", new_proc_info->proc_dev.name, new_proc_info->proc_dev.handle); ++ } ++GG: ++ mutex_unlock(&proc_info_mutex); ++ return err; ++} ++ ++static int msys_release_proc_dev(MSYS_PROC_DEVICE* proc_dev) ++{ ++ int err = 0; ++ PROC_INFO_LIST *tmp_proc_info = NULL; ++ PROC_INFO_LIST *target_proc_info = NULL; ++ PROC_INFO_LIST *parent_proc_info = NULL; ++ PROC_INFO_LIST *child_proc_info = NULL; ++ ++ target_proc_info = msys_get_proc_info(proc_dev); ++ mutex_lock(&proc_info_mutex); ++ if(target_proc_info == NULL) { ++ MSYS_ERROR("%s: Cannot find handle of %s\n", __func__, proc_dev->name); ++ err = -ENODEV; ++ } else { ++ //Remove proc_entry ++ proc_remove(target_proc_info->proc_entry); ++ tmp_proc_info = target_proc_info; ++ //Find all proc_info's child from proc_info_list and remove proc_info from bottom which doesn't have child. ++ do { ++ child_proc_info = msys_get_child_proc_info(tmp_proc_info); ++ if(child_proc_info == NULL) { ++ parent_proc_info = tmp_proc_info->proc_dev.parent; ++ //MSYS_ERROR("%s: Free %s handle = %p\n", __func__, tmp_proc_info->proc_dev.name, tmp_proc_info->proc_dev.handle); ++ __list_del_entry(&tmp_proc_info->list); ++ kfree(tmp_proc_info); ++ if(tmp_proc_info != target_proc_info) { ++ tmp_proc_info = parent_proc_info; ++ } else { ++ break; ++ } ++ }else ++ tmp_proc_info = child_proc_info; ++ } while(1); ++ } ++ mutex_unlock(&proc_info_mutex); ++ return err; ++} ++ ++static struct class *msys_sysfs_class = NULL; ++ ++struct class *msys_get_sysfs_class(void) ++{ ++ if (!msys_sysfs_class) ++ { ++ msys_sysfs_class = class_create(THIS_MODULE, "mstar"); ++ if (!msys_sysfs_class) ++ MSYS_ERROR("cannot get class for sysfs\n"); ++ } ++ return msys_sysfs_class; ++} ++ ++static int __init msys_init(void) ++{ ++ int ret; ++ ++ //ret = misc_register(&sys_dev); ++ ret = register_chrdev(MAJOR_SYS_NUM, "msys", &msys_fops); ++ if (ret != 0) { ++ MSYS_ERROR("cannot register msys on minor=11 (err=%d)\n", ret); ++ } ++ ++ sys_dev.this_device = device_create(msys_get_sysfs_class(), NULL, ++ MKDEV(MAJOR_SYS_NUM, MINOR_SYS_NUM), NULL, "msys"); ++ ++ sys_dev.this_device->dma_mask=&sys_dma_mask; ++ sys_dev.this_device->coherent_dma_mask=sys_dma_mask; ++ mutex_init(&dmem_mutex); ++ ++ INIT_LIST_HEAD(&kept_mem_head); ++ INIT_LIST_HEAD(&fixed_mem_head); ++ ++ device_create_file(sys_dev.this_device, &dev_attr_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_fixed_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_unfix_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_release_dmem); ++ device_create_file(sys_dev.this_device, &dev_attr_PIU_T); ++ device_create_file(sys_dev.this_device, &dev_attr_dmem_retry_interval); ++ device_create_file(sys_dev.this_device, &dev_attr_dmem_retry_count); ++ device_create_file(sys_dev.this_device, &dev_attr_us_ticks); ++ device_create_file(sys_dev.this_device, &dev_attr_dmem_realloc); ++ ++ ++// ret = device_create_file(sys_dev.this_device, &dev_attr_dmem); ++ ++// if (ret != 0)printk("Failed to create sysfs files: %d\n", ret); ++ ++ ++#if defined(CONFIG_PROC_FS) ++ mutex_init(&proc_info_mutex); ++ INIT_LIST_HEAD(&proc_info_head); ++ proc_class=proc_mkdir("mstar",NULL); ++ proc_zen_kernel=proc_mkdir("kernel",proc_class); ++#endif ++ ++ ++ MSYS_WARN(" INIT DONE. TICK=0x%08X\n",get_PIU_tick_count()); ++ ++ return 0; ++} ++ ++//!!!! msys_kfile_* API has not been tested as they are not used. 2016/07/18 ++struct file* msys_kfile_open(const char* path, int flags, int rights) ++{ ++ struct file* filp = NULL; ++ mm_segment_t oldfs; ++ int err = 0; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ filp = filp_open(path, flags, rights); ++ set_fs(oldfs); ++ if(IS_ERR(filp)) { ++ err = PTR_ERR(filp); ++ return NULL; ++ } ++ return filp; ++} ++ ++void msys_kfile_close(struct file* fp) ++{ ++ ++ if(fp) ++ { ++ filp_close(fp,NULL); ++ } ++} ++ ++int msys_kfile_write(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size) ++{ ++ mm_segment_t oldfs; ++ int ret=-EINVAL; ++ ++ if(fp) ++ { ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ret = vfs_write(fp, data, size, &offset); ++ set_fs(oldfs); ++ } ++ return ret; ++} ++ ++int msys_kfile_read(struct file* fp, unsigned long long offset, unsigned char* data, unsigned int size) ++{ ++ mm_segment_t oldfs; ++ int ret; ++ ++ oldfs = get_fs(); ++ set_fs(get_ds()); ++ ++ ret = vfs_read(fp, data, size, &offset); ++ ++ set_fs(oldfs); ++ return ret; ++} ++ ++ ++subsys_initcall(msys_init); ++EXPORT_SYMBOL(msys_user_to_physical); ++EXPORT_SYMBOL(msys_request_dmem); ++EXPORT_SYMBOL(msys_release_dmem); ++EXPORT_SYMBOL(msys_fix_dmem); ++EXPORT_SYMBOL(msys_unfix_dmem); ++EXPORT_SYMBOL(msys_find_dmem_by_phys); ++EXPORT_SYMBOL(msys_get_proc_class); ++EXPORT_SYMBOL(msys_get_sysfs_class); ++EXPORT_SYMBOL(msys_kfile_open); ++EXPORT_SYMBOL(msys_kfile_write); ++EXPORT_SYMBOL(msys_kfile_read); ++EXPORT_SYMBOL(msys_kfile_close); ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("SYSTEM driver"); ++MODULE_LICENSE("MSTAR"); +diff --git a/drivers/mstar/notify/Kconfig b/drivers/mstar/notify/Kconfig +new file mode 100644 +index 00000000..bb3bf60e +--- /dev/null ++++ b/drivers/mstar/notify/Kconfig +@@ -0,0 +1,2 @@ ++config MS_NOTIFY ++ tristate "Mstar NOTIFY driver" +diff --git a/drivers/mstar/notify/Makefile b/drivers/mstar/notify/Makefile +new file mode 100644 +index 00000000..0c751b06 +--- /dev/null ++++ b/drivers/mstar/notify/Makefile +@@ -0,0 +1 @@ ++obj-$(CONFIG_MS_NOTIFY) += ms_notify.o +diff --git a/drivers/mstar/notify/ms_notify.c b/drivers/mstar/notify/ms_notify.c +new file mode 100644 +index 00000000..7d22b2ab +--- /dev/null ++++ b/drivers/mstar/notify/ms_notify.c +@@ -0,0 +1,97 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MAX_PAYLOAD 256 ++ ++static struct sock *_st_notify_sock; ++ ++static void _notify_reply(struct sk_buff * __skb) ++{ ++ struct nlmsghdr *nlh; ++ struct sk_buff *skb; ++ ++ unsigned char msg[MAX_PAYLOAD] = {0}; ++ ++ //int res; ++ ++ do ++ { ++ skb = skb_get(__skb); ++ ++ if (skb->len < NLMSG_SPACE(0)) ++ { ++ break; ++ } ++ ++ nlh = nlmsg_hdr(skb); ++ ++ #if 0 ++ printk("recv skb from user space uid: %d pid: %d seq: %d\n", NETLINK_CREDS(skb)->uid, NETLINK_CREDS(skb)->pid, nlh->nlmsg_seq); ++ #endif ++ ++ memcpy(msg, NLMSG_DATA(nlh), sizeof(msg)); ++ ++ kfree_skb(skb); ++ ++ if (NULL == (skb = alloc_skb(NLMSG_SPACE(MAX_PAYLOAD), GFP_ATOMIC))) ++ { ++ break; ++ } ++ ++ if (NULL == (nlh = nlmsg_put(skb, 0, 0, 0, MAX_PAYLOAD, 0))) ++ { ++ break; ++ } ++ ++ nlh->nlmsg_flags = 0; ++ memcpy(NLMSG_DATA(nlh), msg, MAX_PAYLOAD); ++ NETLINK_CB(skb).portid = 0; ++ NETLINK_CB(skb).dst_group = 1; ++ netlink_broadcast(_st_notify_sock, skb, 0, 1, GFP_ATOMIC); ++ //kfree_skb(skb); ++ return; ++ } while (0); ++ ++//nlmsg_failure: /* Used by NLMSG_PUT */ ++ if (skb) ++ { ++ kfree_skb(skb); ++ } ++ ++} ++ ++static int __init _notify_init(void) ++{ ++ struct netlink_kernel_cfg cfg = { ++ .groups = 0, ++ .input = _notify_reply, ++ }; ++ ++ if (NULL == (_st_notify_sock = netlink_kernel_create(&init_net, NETLINK_USERSOCK, &cfg))) ++ { ++ return -1; ++ } ++ ++ printk("mstar notify driver install successfully\n"); ++ return 0; ++} ++ ++static void __exit _notify_exit(void) ++{ ++ ++ netlink_kernel_release(_st_notify_sock); ++ ++ printk("mstar notify driver remove successfully\n"); ++} ++ ++module_init(_notify_init); ++module_exit(_notify_exit); ++ ++MODULE_DESCRIPTION("notify reply server module"); ++MODULE_AUTHOR("Raul Wang"); ++MODULE_LICENSE("GPL"); ++ +diff --git a/drivers/mstar/pm/Kconfig b/drivers/mstar/pm/Kconfig +new file mode 100644 +index 00000000..8cd7dce5 +--- /dev/null ++++ b/drivers/mstar/pm/Kconfig +@@ -0,0 +1,3 @@ ++config MS_PM ++ tristate "Mstar PM driver" ++ help +diff --git a/drivers/mstar/pm/Makefile b/drivers/mstar/pm/Makefile +new file mode 100644 +index 00000000..1f1e8e5a +--- /dev/null ++++ b/drivers/mstar/pm/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_MS_PM) += ms_pm.o +diff --git a/drivers/mstar/pm/ms_pm.c b/drivers/mstar/pm/ms_pm.c +new file mode 100644 +index 00000000..a361f7c0 +--- /dev/null ++++ b/drivers/mstar/pm/ms_pm.c +@@ -0,0 +1,181 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "infinity3/registers.h" ++#include "infinity3/irqs.h" ++#include ++ ++ ++extern U8 MDrv_GPIO_Pad_Read(U8 u8IndexGPIO); ++int detect_gpio=-1; ++int from_resend=0; ++ ++static irqreturn_t ms_pm_deepsleep_handler(int irq, void *dev_id) ++{ ++#if 0 ++ ++ struct platform_device *pdev = dev_id; ++ struct irq_data *data; ++ ++ ++ dev_info(&pdev->dev, "[%s] ++\n", __func__); ++ ++ if(detect_gpio == -1) ++ return IRQ_NONE; ++ ++ if(from_resend == 1) ++ { ++ from_resend = 0; ++ return IRQ_HANDLED; ++ } ++ ++ ++ data = irq_get_irq_data(irq); ++ ++ ++ data = irq_get_irq_data(irq); ++ //data->chip->irq_set_type(data, 0); //set polarity, get interrupt when L->H ++ data->chip->irq_set_type(data, 1); //set polarity, get interrupt when H->L ++ ++ //clear interrupt ++ SETREG16(BASE_REG_PMGPIO_PA + REG_ID_00, BIT6); ++ //unmask interrupt ++ CLRREG16(BASE_REG_PMGPIO_PA + REG_ID_00, BIT4); ++ ++#ifndef CONFIG_ARCH_INFINITY3 //no need in I3 ++ //power down eth ++ //wriu -w 0x0032fc 0x0102 // Power-down LDO ++ //wriu 0x0032b7 0x17 // Power-down ADC ++ //wriu 0x0032cb 0x13 // Power-down BGAP ++ //wriu 0x0032cc 0x30 // Power-down ADCPL ++ //wriu 0x0032cd 0xd8 // Power-down ADCPL ++ //wriu 0x0032d4 0x20 // Power-down LPF_OP ++ //wriu 0x0032b9 0x41 // Power-down LPF ++ //wriu 0x0032bb 0x84 // Power-down REF ++ //wriu -w 0x00333a 0x03f3 // PD_TX_IDAC, PD_TX_LD ++ //wriu 0x0033a1 0x20 // PD_SADC, EN_SAR_LOGIC** ++ //wriu 0x0033c5 0x40 // 100gat ++ //wriu 0x003330 0x53 // 200gat ++ OUTREG16(0x1F0065F8, 0x0102); ++ OUTREG8 (0x1F00656D, 0x17); ++ OUTREG8 (0x1F006595, 0x13); ++ OUTREG8 (0x1F006598, 0x30); ++ OUTREG8 (0x1F006599, 0xd8); ++ OUTREG8 (0x1F0065A8, 0x20); ++ OUTREG8 (0x1F006571, 0x41); ++ OUTREG8 (0x1F006575, 0x84); ++ OUTREG16(0x1F006674, 0x03f3); ++ OUTREG8 (0x1F006741, 0x20); ++ OUTREG8 (0x1F006789, 0x40); ++ OUTREG8 (0x1F006660, 0x53); ++ ++ //Set DVDD_NODIE to 0.95V ++ //OUTREG8(BASE_REG_PMSLEEP_PA + REG_ID_62, 0xA0); ++#endif ++ ++ //Switch reg_ckg_mcu/reg_ckg_spi to xtal, or it will hang when resume ++ OUTREG16(BASE_REG_PMSLEEP_PA + REG_ID_20, 0x0); ++ ++ OUTREG8(0x1F002E1C, 0x03); //reg_spi_arb_ctrl[1:0] ++ OUTREG16(0x1F002E20, 0x007F); //reg_non_pm_ack_timeout_len[15:0] ++ OUTREG8(0x1F007848, 0x30); //reg_pwoff_rst0_en, reg_pwoff_rst1_en ++ ++ //reg_ckg_pm_sleep ++ OUTREG16(0x1F001C88, ((INREG16(0x1F001C88)&(~0x7C00))|0x1000)); ++ ++ //Enter deepsleep ++ SETREG16(BASE_REG_PMSLEEP_PA + REG_ID_09, BIT15); ++ OUTREG16(BASE_REG_PMSLEEP_PA + REG_ID_32, 0x9f8e); ++ OUTREG16(BASE_REG_PMSLEEP_PA + REG_ID_33, 0x9f8e); ++ OUTREG8(BASE_REG_PMSLEEP_PA + REG_ID_37, 0xa5); ++ OUTREG8(BASE_REG_PMSLEEP_PA + REG_ID_1C, 0x0c); ++ OUTREG16(BASE_REG_PMSLEEP_PA + REG_ID_12, 0xbabe); ++ OUTREG8(BASE_REG_PMGPIO_PA + REG_ID_04, 0x10); ++ ++ /* we'll never reach here because power down */ ++#endif ++ return IRQ_HANDLED; ++} ++ ++#ifdef CONFIG_PM ++static int ms_pm_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ dev_info(&pdev->dev, "[%s] ++\n", __func__); ++ return 0; ++} ++ ++static int ms_pm_resume(struct platform_device *pdev) ++{ ++ dev_info(&pdev->dev, "[%s] ++\n", __func__); ++ return 0; ++} ++#endif ++ ++static int ms_pm_remove(struct platform_device *pdev) ++{ ++ dev_info(&pdev->dev, "[%s] ++\n", __func__); ++ ++ return 0; ++} ++ ++static int ms_pm_probe(struct platform_device *pdev) ++{ ++ struct irq_data *data; ++ int ret; ++ ++ data = irq_get_irq_data(platform_get_irq(pdev, 0)); ++ //data->chip->irq_set_type(data, 1); //get interrupt when H->L ++ data->chip->irq_set_type(data, 0); //get interrupt when L->H ++ data->chip->irq_ack(data); ++ ++ if((ret = of_property_read_u32(pdev->dev.of_node, "detect-gpio", &detect_gpio))) ++ { ++ detect_gpio=-1; ++ return ret; ++ } ++ ++ if(MDrv_GPIO_Pad_Read(detect_gpio)==0) ++ from_resend=1; ++ ++ pr_err("gpio_to_irq %d => %d\n", detect_gpio, gpio_to_irq(detect_gpio)); ++ ++ if((ret = devm_request_threaded_irq(&pdev->dev, data->irq, ms_pm_deepsleep_handler, NULL, 0, "ms_pm", pdev))) ++ return ret; ++ ++ dev_info(&pdev->dev, "[%s]: irq=%d, detect-gpio=%d\n", __func__, data->irq, detect_gpio); ++ ++ from_resend=0; ++ ++ return ret; ++} ++ ++ ++static const struct of_device_id ms_pm_of_match_table[] = { ++ { .compatible = "mstar,infinity-pm" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_pm_of_match_table); ++ ++static struct platform_driver ms_pm_driver = { ++ .remove = ms_pm_remove, ++ .probe = ms_pm_probe, ++#ifdef CONFIG_PM ++ .suspend = ms_pm_suspend, ++ .resume = ms_pm_resume, ++#endif ++ .driver = { ++ .name = "ms_pm_driver", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_pm_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_pm_driver); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/pwm/Kconfig b/drivers/mstar/pwm/Kconfig +new file mode 100644 +index 00000000..b0e7b492 +--- /dev/null ++++ b/drivers/mstar/pwm/Kconfig +@@ -0,0 +1,19 @@ ++config MS_PWM ++ ++tristate "MSTAR_PWM" ++ ++ help ++ Say Y here to enable the driver for the PWM. ++ ++ If unsure, say Y. ++ ++ To compile this driver as a module, choose M here: the ++ module will be called mdrv_ts. ++ ++select PWM ++ ++help ++ MStar PWM driver function ++ ++ ++ +diff --git a/drivers/mstar/pwm/Makefile b/drivers/mstar/pwm/Makefile +new file mode 100644 +index 00000000..2e7ef01c +--- /dev/null ++++ b/drivers/mstar/pwm/Makefile +@@ -0,0 +1,14 @@ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# specific options ++#EXTRA_CFLAGS += -DMSOS_TYPE_LINUX ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++EXTRA_CFLAGS += -Idrivers/mstar/pwm/$(CONFIG_MSTAR_CHIP_NAME) ++ ++# files ++obj-$(CONFIG_MS_PWM) += ms_pwm.o ++ms_pwm-y += mdrv_pwm.o $(CONFIG_MSTAR_CHIP_NAME)/mhal_pwm.o ++ +diff --git a/drivers/mstar/pwm/infinity/mhal_pwm.c b/drivers/mstar/pwm/infinity/mhal_pwm.c +new file mode 100644 +index 00000000..380743e0 +--- /dev/null ++++ b/drivers/mstar/pwm/infinity/mhal_pwm.c +@@ -0,0 +1,305 @@ ++// $Change: 626442 $ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// pwm.c ++// ++// DESCRIPTION ++// PWM HW control codes. ++// ++// HISTORY ++// 2008.05.15 Bryan Fan Initial Version ++// 2008.6.12 Bryan Fan Revised for Code Review ++// 2008.6.26 Bryan Fan Revised for new Code Review ++// ++//----------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------ ++// Include Files ++//------------------------------------------------------------------------------ ++ ++#include ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "infinity/registers.h" ++#include "mhal_pwm.h" ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDuty ++// ++// Description ++// Set Duty value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Duty value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetDuty( U8 u8Id, U16 u16Val ) ++{ ++ U32 u32Period; ++ U16 u16Duty; ++ ++ u16Val = u16Val & PWM_DUTY_MASK; ++ ++ if( PWM0 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM0_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM0_DUTY, u16Duty); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM1_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM1_DUTY, u16Duty); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM2_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM2_DUTY, u16Duty); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ u32Period = INREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM3_PERIOD); ++ u16Duty=u32Period*u16Val/100; ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM3_DUTY, u16Duty); ++ } ++ else ++ { ++ printk(KERN_INFO "DrvPWMSetDuty error!!!! (%x, %x)\r\n", u8Id, u16Val); ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetPeriod( U8 u8Id, U16 u16Val ) ++{ ++ U32 u32TempValue; ++ ++ u32TempValue=DEFAULT_PWM_CLK/u16Val; ++ u16Val = u32TempValue & PWM_PERIOD_MASK; ++ ++ printk(KERN_INFO "DrvPWMSetPeriod !!!! (%x, %x)\r\n", u32TempValue, u16Val); ++ ++ if( PWM0 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM0_PERIOD, u16Val); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM1_PERIOD, u16Val); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM2_PERIOD, u16Val); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREG16(BASE_REG_PMSLEEP_PA + u16REG_PWM3_PERIOD, u16Val); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetPeriod error!!!! (%x, %x)\r\n", u8Id, u16Val); ++ } ++ ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetPolarity( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM0_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM1_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM2_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM3_DIV, (u8Val<<8), PWM_CTRL_POLARITY ); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetPolarity error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++ ++} ++ ++void DrvPWMSetFreqDiv( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM0_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM1_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM2_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM3_DIV, u8Val, PWM_CTRL_DIV_MSAK ); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetDiv error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++ ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDben ++// ++// Description ++// Enable/Disable Dben function ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] On/Off value ++// ++// Return Value ++// None ++// ++ ++void DrvPWMSetDben( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM0_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM1_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM2_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ OUTREGMSK16( BASE_REG_PMSLEEP_PA + u16REG_PWM3_DIV, (u8Val<<12), PWM_CTRL_DBEN ); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMSetDben error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++ ++} ++ ++void DrvPWMEnable( U8 u8Id, U8 u8Val ) ++{ ++ if( PWM0 == u8Id ) ++ { ++ //reg_pwm0_mode = BIT[1:0] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, u8Val, 0x3); ++ } ++ else if( PWM1 == u8Id ) ++ { ++ //reg_pwm1_mode=BIT[3:2] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, (u8Val<<2), 0xC); ++ } ++ else if( PWM2 == u8Id ) ++ { ++ //reg_pwm2_mode=BIT[4] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, (u8Val<<4), 0x10); ++ } ++ else if( PWM3 == u8Id ) ++ { ++ //reg_pwm3_mode=BIT[6] ++ OUTREGMSK16(BASE_REG_CHIPTOP_PA + REG_ID_07, (u8Val<<6), 0x40); ++ } ++ else ++ { ++ printk(KERN_ERR "void DrvPWMEnable error!!!! (%x, %x)\r\n", u8Id, u8Val); ++ } ++} ++ ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMInit ++// ++// Description ++// PWM init function ++// ++// Parameters ++// u8CustLevel: [in] Cust Level ++// ++// Return Value ++// None ++//------------------------------------------------------------------------------ ++void DrvPWMInit( U8 u8Id ) ++{ ++ //printk(KERN_INFO "+DrvPWMInit\r\n"); ++ ++ DrvPWMSetFreqDiv( u8Id, DEFAULT_DIV_CNT ); ++ //DrvPWMSetPeriod( u8Id, DEFAULT_PERIOD ); ++ ++ DrvPWMSetPolarity( u8Id, DEFAULT_POLARITY ); ++ ++ DrvPWMSetDben( u8Id, DEFAULT_DBEN ); ++ ++ //printk(KERN_INFO "-DrvPWMInit\r\n"); ++} ++ +diff --git a/drivers/mstar/pwm/infinity/mhal_pwm.h b/drivers/mstar/pwm/infinity/mhal_pwm.h +new file mode 100644 +index 00000000..f1ef8a9f +--- /dev/null ++++ b/drivers/mstar/pwm/infinity/mhal_pwm.h +@@ -0,0 +1,120 @@ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// columbus_pwm.h ++// ++// DESCRIPTION ++// Define the PWM controller registers ++// ++// HISTORY ++// 2008.5.13 Bryan Fan Initial Version ++// 2008.6.12 Bryan Fan Revised for Code Review ++// 2008.6.27 Bryan Fan Revised for new Code Review ++// 2008.07.02 Bryan Fan Revised for new Code Review ++// ++//----------------------------------------------------------------------------- ++ ++#ifndef __PWM_H ++#define __PWM_H ++ ++#include "mdrv_types.h" ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++//PWM0 ++#define u16REG_PWM0_DIV BK_REG(0x68) ++#define u16REG_RESERVED_4 BK_REG(0x68) ++ ++#define u16REG_PWM0_DUTY BK_REG(0x69) ++#define u16REG_RESERVED_3 BK_REG(0x69) ++ ++#define u16REG_PWM0_PERIOD BK_REG(0x6A) ++#define u16REG_RESERVED_2 BK_REG(0x6A) ++ ++//PWM1 ++#define u16REG_PWM1_DIV BK_REG(0x6B) ++#define u16REG_RESERVED_7 BK_REG(0x6B) ++ ++#define u16REG_PWM1_DUTY BK_REG(0x6C) ++#define u16REG_RESERVED_6 BK_REG(0x6C) ++ ++#define u16REG_PWM1_PERIOD BK_REG(0x6D) ++#define u16REG_RESERVED_5 BK_REG(0x6D) ++ ++//PWM2 ++#define u16REG_PWM2_DIV BK_REG(0x78) ++#define u16REG_RESERVED_A BK_REG(0x78) ++ ++#define u16REG_PWM2_DUTY BK_REG(0x79) ++#define u16REG_RESERVED_9 BK_REG(0x79) ++ ++#define u16REG_PWM2_PERIOD BK_REG(0x7A) ++#define u16REG_RESERVED_8 BK_REG(0x7A) ++ ++//PWM3 ++#define u16REG_PWM3_PERIOD BK_REG(0x7B) ++#define u16REG_RESERVED_B BK_REG(0x7B) ++ ++#define u16REG_PWM3_DUTY BK_REG(0x7C) ++#define u16REG_RESERVED_C BK_REG(0x7C) ++ ++#define u16REG_PWM3_DIV BK_REG(0x7D) ++#define u16REG_RESERVED_D BK_REG(0x7D) ++ ++///////////////////////////////////////// ++ ++//#define DEFAULT_PWM_ID ++ ++// For future reference ++#define DEFAULT_PWM_CLK 12000000 ++#define DEFAULT_DIV_CNT 0// 0.000001 X 250 = 0.00025 sec = 0.25 ms ++#define DEFAULT_PERIOD 101//=0X2EE0 => 1ms{1000HZ=12000000/12000} ++ ++ ++#define DEFAULT_POLARITY 1 // 1 => 0 - L - duty - H - period, 0 => 0 - H - duty - L - period ++#define DEFAULT_DBEN 0 // double buffer for Period Reset ++ ++#define PWM0 0x00 ++#define PWM1 0x01 ++#define PWM2 0x02 ++#define PWM3 0x03 ++#define PWM4 0x04 ++#define PWM5 0x05 ++#define PMW_DEFAULT 0xFF ++ ++//PWMX_CTRL ++#define PWM_CTRL_DIV_MSAK 0x000000FF ++#define PWM_CTRL_POLARITY 0x00000100 ++#define PWM_CTRL_DBEN 0x00001000 ++ ++//Mask ++#define PWM_PERIOD_MASK 0x0000FFFF ++#define PWM_DUTY_MASK PWM_PERIOD_MASK ++#define PWM_CTRL_MASK 0x000015FF //0001 0101 1111 1111, BIT9,11,12 will not be tested ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriod( U8 u8Id, U16 u16Val ); ++void DrvPWMSetDuty( U8 u8Id, U16 u16Val ); ++void DrvPWMEnable( U8 u8Id, U8 u8Val); ++void DrvPWMSetPolarity( U8 u8Id, U8 u8Val ); ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/mstar/pwm/infinity3/mhal_pwm.c b/drivers/mstar/pwm/infinity3/mhal_pwm.c +new file mode 100644 +index 00000000..fba3b653 +--- /dev/null ++++ b/drivers/mstar/pwm/infinity3/mhal_pwm.c +@@ -0,0 +1,331 @@ ++// $Change: 626442 $ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// pwm.c ++// ++// DESCRIPTION ++// PWM HW control codes. ++// ++// HISTORY ++// 2008.05.15 Bryan Fan Initial Version ++// 2008.6.12 Bryan Fan Revised for Code Review ++// 2008.6.26 Bryan Fan Revised for new Code Review ++// ++//----------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------ ++// Include Files ++//------------------------------------------------------------------------------ ++ ++#include "mhal_pwm.h" ++#include "infinity3/gpio.h" ++ ++//------------------------------------------------------------------------------ ++// Variables ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Local Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// External Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// Global Functions ++//------------------------------------------------------------------------------ ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetDuty ++// ++// Description ++// Set Duty value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Duty value ++// ++// Return Value ++// None ++// ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period; ++ U32 u32Duty; ++ ++ u32Period = INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L) + ((INREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)<<16)); ++ ++// u32Period = INREG16((ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L)) + INREG16((ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H)) & 0xffff; ++ u32Duty = ((u32Period * u32Val) / 100); ++ ++ pr_err("reg=0x%08X clk=%d, u32Duty=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L), (U32)(clk_get_rate(ms_chip->clk)), u32Duty); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_L, (u32Duty&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_DUTY_H, ((u32Duty>>16)&0x3)); ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPeriod ++// ++// Description ++// Set Period value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u16Val: [in] Period value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val) ++{ ++ U32 u32Period; ++ ++ u32Period=(U32)(clk_get_rate(ms_chip->clk))/u32Val; ++ pr_err("reg=0x%08X clk=%d, period=0x%x\n", (U32)(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L), (U32)(clk_get_rate(ms_chip->clk)), u32Period); ++ ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_L, (u32Period&0xFFFF)); ++ OUTREG16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_PERIOD_H, ((u32Period>>16)&0x3)); ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: DrvPWMSetPolarity ++// ++// Description ++// Set Polarity value ++// ++// Parameters ++// u8Id: [in] PWM ID ++// u8Val: [in] Polarity value ++// ++// Return Value ++// None ++// ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val) ++{ ++ OUTREGMSK16(ms_chip->base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + (u8Id*0x80) + u16REG_PWM_CTRL, (u8Val<base + u16REG_SW_RESET, 1<base + u16REG_SW_RESET, 1< ++#include ++#include "ms_platform.h" ++#include "registers.h" ++#include "mdrv_types.h" ++ ++#define MS_PWM_INFO(x, args...) printk(x, ##args) ++#define MS_PWM_DBG(x, args...) printk(x, ##args) ++ ++struct mstar_pwm_chip { ++ struct pwm_chip chip; ++ struct clk *clk; ++ void __iomem *base; ++ u32 *pad_ctrl; ++}; ++ ++//------------------------------------------------------------------------------ ++// Constants ++//------------------------------------------------------------------------------ ++//Common PWM registers ++#define u16REG_PWM_SHIFT_L (0x0 << 2) ++#define u16REG_PWM_SHIFT_H (0x1 << 2) ++#define u16REG_PWM_DUTY_L (0x2 << 2) ++#define u16REG_PWM_DUTY_H (0x3 << 2) ++#define u16REG_PWM_PERIOD_L (0x4 << 2) //reg_pwm0_period ++#define u16REG_PWM_PERIOD_H (0x5 << 2) ++#define u16REG_PWM_DIV (0x6 << 2) ++#define u16REG_PWM_CTRL (0x7 << 2) ++ #define VDBEN_SW_BIT 0 ++ #define DBEN_BIT 1 ++ #define DIFF_P_EN_BIT 2 ++ #define SHIFT_GAT_BIT 3 ++ #define POLARITY_BIT 4 ++ ++#define u16REG_PWM_SHIFT2 (0x8 << 2) ++#define u16REG_PWM_DUTY2 (0x9 << 2) ++#define u16REG_PWM_SHIFT3 (0xA << 2) ++#define u16REG_PWM_DUTY3 (0xB << 2) ++#define u16REG_PWM_SHIFT4 (0xC << 2) ++#define u16REG_PWM_DUTY4 (0xD << 2) ++ ++#define u16REG_SW_RESET (0x7F << 2) ++ ++//------------------------------------------------------------------------------ ++// Export Functions ++//------------------------------------------------------------------------------ ++//void DrvBoostInit(void); ++//void DrvBoostReset(void); ++//void DrvPWMInit(U8 u8Id); ++//void DrvPWMReset(void); ++//void DrvBacklightSet(U8 u8Level, U8 u8IsSave); ++//U8 DrvBacklightGet(void); ++//void DrvBacklightOn(void); ++//void DrvBacklightOff(void); ++//void DrvPWMSetEn(U8 u8Id, U8 u8Val); ++void DrvPWMSetPeriod(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMSetDuty(struct mstar_pwm_chip *ms_chip, U8 u8Id, U32 u32Val); ++void DrvPWMEnable(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMSetPolarity(struct mstar_pwm_chip *ms_chip, U8 u8Id, U8 u8Val); ++void DrvPWMPadSet(U8 u8Id, U8 u8Val); ++ ++//----------------------------------------------------------------------------- ++ ++ ++ ++#endif //__PWM_H +diff --git a/drivers/mstar/pwm/mdrv_pwm.c b/drivers/mstar/pwm/mdrv_pwm.c +new file mode 100644 +index 00000000..0cad6069 +--- /dev/null ++++ b/drivers/mstar/pwm/mdrv_pwm.c +@@ -0,0 +1,169 @@ ++/* ++ * Copyright (C) ST-Ericsson SA 2010 ++ * ++ * Author: Arun R Murthy ++ * License terms: GNU General Public License (GPL) version 2 ++ */ ++#include ++#include ++#include ++#include ++ ++#include "mhal_pwm.h" ++ ++static inline struct mstar_pwm_chip *to_mstar_pwm_chip(struct pwm_chip *c) ++{ ++ return container_of(c, struct mstar_pwm_chip, chip); ++} ++ ++static int mstar_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ ++ MS_PWM_DBG("[PWN] %s duty_ns=%d, period_ns=%d\n", __func__, duty_ns, period_ns); ++ ++ DrvPWMSetPeriod(ms_pwm, pwm->hwpwm, period_ns); ++ DrvPWMSetDuty(ms_pwm, pwm->hwpwm, duty_ns); ++// DrvPWMPadSet(pwm->hwpwm, (U8)ms_pwm->pad_ctrl[pwm->hwpwm]); ++ return 0; ++} ++ ++static int mstar_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ MS_PWM_DBG("[PWM] %s\n", __func__); ++ DrvPWMEnable(ms_pwm, pwm->hwpwm, 1); ++ DrvPWMPadSet(pwm->hwpwm, (U8)ms_pwm->pad_ctrl[pwm->hwpwm]); ++ return 0; ++} ++ ++static void mstar_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ MS_PWM_DBG("[PWM] %s\n", __func__); ++ DrvPWMEnable(ms_pwm, pwm->hwpwm, 0); ++} ++ ++static int mstar_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity) ++{ ++ struct mstar_pwm_chip *ms_pwm = to_mstar_pwm_chip(chip); ++ MS_PWM_DBG("[PWM] %s %d\n", __func__, (U8)polarity); ++ DrvPWMSetPolarity(ms_pwm, pwm->hwpwm, (U8)polarity); ++ return 0; ++} ++ ++ ++static const struct pwm_ops mstar_pwm_ops = { ++ .config = mstar_pwm_config, ++ .enable = mstar_pwm_enable, ++ .disable = mstar_pwm_disable, ++ .set_polarity = mstar_pwm_set_polarity, ++ .owner = THIS_MODULE, ++}; ++ ++static int ms_pwm_probe(struct platform_device *pdev) ++{ ++ struct mstar_pwm_chip *ms_pwm; ++ struct resource *res; ++ int ret=0, i=0; ++ ++ ms_pwm = devm_kzalloc(&pdev->dev, sizeof(*ms_pwm), GFP_KERNEL); ++ if (ms_pwm == NULL) ++ { ++ dev_err(&pdev->dev, "failed to allocate memory\n"); ++ return -ENOMEM; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "Can't get I/O resource regs for pwm\n"); ++ return 0; ++ } ++ ++ //ms_pwm->base = devm_ioremap_resource(&pdev->dev, res); ++ ms_pwm->base = (void *)res->start; ++ ++ if (IS_ERR(ms_pwm->base)) ++ return PTR_ERR(ms_pwm->base); ++ ++ ms_pwm->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(ms_pwm->clk)) ++ return PTR_ERR(ms_pwm->clk); ++ ++ ret = clk_prepare_enable(ms_pwm->clk); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, ms_pwm); ++ ++ ms_pwm->chip.dev = &pdev->dev; ++ ms_pwm->chip.ops = &mstar_pwm_ops; ++ ms_pwm->chip.base = -1; ++ if(of_property_read_u32(pdev->dev.of_node, "npwm", &ms_pwm->chip.npwm)) ++ ms_pwm->chip.npwm = 4; ++ ++ ms_pwm->pad_ctrl = devm_kzalloc(&pdev->dev, sizeof(*ms_pwm->pad_ctrl), GFP_KERNEL); ++ if (ms_pwm->pad_ctrl == NULL) ++ { ++ dev_err(&pdev->dev, "failed to allocate memory\n"); ++ return -ENOMEM; ++ } ++ ++ if((ret=of_property_read_u32_array(pdev->dev.of_node, "pad-ctrl", ms_pwm->pad_ctrl, ms_pwm->chip.npwm))) ++ dev_err(&pdev->dev, "read pad-ctrl failed\n"); ++ ++ for(i=0; ichip.npwm; i++) ++ { ++ MS_PWM_DBG("ms_pwm->pad_ctrl[%d]=%d\n", i, ms_pwm->pad_ctrl[i]); ++ } ++ ++ ret = pwmchip_add(&ms_pwm->chip); ++ if (ret < 0) ++ { ++ clk_disable_unprepare(ms_pwm->clk); ++ dev_err(&pdev->dev, "pwmchip_add failed\n"); ++ return ret; ++ } ++ ++ dev_info(&pdev->dev, "probe successful\n"); ++ ++ return 0; ++} ++ ++static int ms_pwm_remove(struct platform_device *pdev) ++{ ++ struct mstar_pwm_chip *ms_pwm = dev_get_drvdata(&pdev->dev); ++ int err; ++ ++ clk_disable_unprepare(ms_pwm->clk); ++ ++ err = pwmchip_remove(&ms_pwm->chip); ++ if (err < 0) ++ return err; ++ ++ dev_info(&pdev->dev, "remove successful\n"); ++ return 0; ++} ++ ++static const struct of_device_id ms_pwm_of_match_table[] = { ++ { .compatible = "mstar,infinity3-pwm" }, ++ {} ++}; ++ ++MODULE_DEVICE_TABLE(of, ms_pwm_of_match_table); ++ ++static struct platform_driver ms_pwm_driver = { ++ .remove = ms_pwm_remove, ++ .probe = ms_pwm_probe, ++ .driver = { ++ .name = "mstar-i3pwm", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_pwm_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_pwm_driver); ++ ++MODULE_AUTHOR("MStar Semiconductor, Inc."); ++MODULE_DESCRIPTION("MStar PWM Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/mstar/rtc/Kconfig b/drivers/mstar/rtc/Kconfig +new file mode 100644 +index 00000000..d884fdcb +--- /dev/null ++++ b/drivers/mstar/rtc/Kconfig +@@ -0,0 +1,5 @@ ++config MS_RTC ++ select RTC_CLASS ++ tristate "RTC driver" ++ help ++ +diff --git a/drivers/mstar/rtc/Makefile b/drivers/mstar/rtc/Makefile +new file mode 100644 +index 00000000..67fb8b71 +--- /dev/null ++++ b/drivers/mstar/rtc/Makefile +@@ -0,0 +1,4 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++# files ++obj-$(CONFIG_MS_RTC) += ms_rtc.o +\ No newline at end of file +diff --git a/drivers/mstar/rtc/ms_rtc.c b/drivers/mstar/rtc/ms_rtc.c +new file mode 100644 +index 00000000..5ed5b4d1 +--- /dev/null ++++ b/drivers/mstar/rtc/ms_rtc.c +@@ -0,0 +1,365 @@ ++/* ++ * Real Time Clock driver for msb252x ++ * ++ * (C) 2011 Heyn lu, Mstar ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "ms_types.h" ++#include "ms_msys.h" ++ ++#define RTC_DEBUG 0 ++ ++#if RTC_DEBUG ++#define RTC_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define RTC_DBG(fmt, arg...) ++#endif ++#define RTC_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#define REG_RTC_CTRL 0x00 ++ #define SOFT_RSTZ_BIT BIT0 ++ #define CNT_EN_BIT BIT1 ++ #define WRAP_EN_BIT BIT2 ++ #define LOAD_EN_BIT BIT3 ++ #define READ_EN_BIT BIT4 ++ #define INT_MASK_BIT BIT5 ++ #define INT_FORCE_BIT BIT6 ++ #define INT_CLEAR_BIT BIT7 ++ ++#define REG_RTC_FREQ_CW_L 0x04 ++#define REG_RTC_FREQ_CW_H 0x08 ++ ++#define REG_RTC_LOAD_VAL_L 0x0C ++#define REG_RTC_LOAD_VAL_H 0x10 ++ ++#define REG_RTC_MATCH_VAL_L 0x14 ++#define REG_RTC_MATCH_VAL_H 0x18 ++ ++#define REG_RTC_CNT_VAL_L 0x20 ++#define REG_RTC_CNT_VAL_H 0x24 ++ ++struct ms_rtc_info { ++ struct platform_device *pdev; ++ struct rtc_device *rtc_dev; ++ struct device* rtc_devnode; ++ void __iomem *rtc_base; ++}; ++ ++int auto_wakeup_delay_seconds = 0; ++ ++static ssize_t auto_wakeup_timer_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ size_t len; ++ const char *str = buf; ++ while (*str && !isspace(*str)) str++; ++ len = str - buf; ++ if(len) ++ { ++ auto_wakeup_delay_seconds = simple_strtoul(buf, NULL, 10); ++ //printk("\nauto_wakeup_delay_seconds=%d\n", auto_wakeup_delay_seconds); ++ return n; ++ } ++ return -EINVAL; ++ } ++ return -EINVAL; ++} ++static ssize_t auto_wakeup_timer_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ++ str += scnprintf(str, end - str, "%d\n", auto_wakeup_delay_seconds); ++ return (str - buf); ++} ++DEVICE_ATTR(auto_wakeup_timer, 0644, auto_wakeup_timer_show, auto_wakeup_timer_store); ++ ++ ++static int ms_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ ++ seconds = readw(info->rtc_base + REG_RTC_MATCH_VAL_L) | (readw(info->rtc_base + REG_RTC_MATCH_VAL_H) << 16); ++ ++ rtc_time_to_tm(seconds, &alarm->time); ++ ++ if( !(readw(info->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT) ) ++ alarm->enabled = 1; ++ ++ RTC_DBG("ms_rtc_read_alarm[%d,%d,%d,%d,%d,%d], alarm_en=%d\n", ++ alarm->time.tm_year,alarm->time.tm_mon,alarm->time.tm_mday,alarm->time.tm_hour,alarm->time.tm_min,alarm->time.tm_sec, alarm->enabled); ++ ++ ++ return 0; ++} ++ ++static int ms_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ RTC_DBG("ms_rtc_set_alarm[%d,%d,%d,%d,%d,%d], alarm_en=%d\n", ++ alarm->time.tm_year,alarm->time.tm_mon,alarm->time.tm_mday,alarm->time.tm_hour,alarm->time.tm_min,alarm->time.tm_sec, alarm->enabled); ++ ++ rtc_tm_to_time(&alarm->time, &seconds); ++ ++ writew((seconds & 0xFFFF), info->rtc_base + REG_RTC_MATCH_VAL_L); ++ writew((seconds>>16) & 0xFFFF, info->rtc_base + REG_RTC_MATCH_VAL_H); ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ if(alarm->enabled) ++ { ++ writew(reg & ~(INT_MASK_BIT), info->rtc_base + REG_RTC_CTRL); ++ } ++ else ++ { ++ writew(reg | INT_MASK_BIT, info->rtc_base + REG_RTC_CTRL); ++ } ++ ++ return 0; ++} ++ ++static int ms_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ writew(reg | READ_EN_BIT, info->rtc_base + REG_RTC_CTRL); ++ while(readw(info->rtc_base + REG_RTC_CTRL) & READ_EN_BIT); //wait for HW latch done ++ ++ seconds = readw(info->rtc_base + REG_RTC_CNT_VAL_L) | (readw(info->rtc_base + REG_RTC_CNT_VAL_H) << 16); ++ ++ rtc_time_to_tm(seconds, tm); ++ ++ RTC_DBG("ms_rtc_read_time[%d,%d,%d,%d,%d,%d]\n", ++ tm->tm_year,tm->tm_mon,tm->tm_mday,tm->tm_hour,tm->tm_min,tm->tm_sec); ++ ++ return rtc_valid_tm(tm); ++} ++ ++static int ms_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev); ++ unsigned long seconds; ++ u16 reg; ++ ++ RTC_DBG("ms_rtc_set_time[%d,%d,%d,%d,%d,%d]\n", ++ tm->tm_year,tm->tm_mon,tm->tm_mday,tm->tm_hour,tm->tm_min,tm->tm_sec); ++ ++ rtc_tm_to_time(tm, &seconds); ++ writew(seconds & 0xFFFF, info->rtc_base + REG_RTC_LOAD_VAL_L); ++ writew((seconds >> 16) & 0xFFFF, info->rtc_base + REG_RTC_LOAD_VAL_H); ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ writew(reg | LOAD_EN_BIT, info->rtc_base + REG_RTC_CTRL); ++ /* need to check carefully if we want to clear REG_RTC_LOAD_VAL_H for customer*/ ++ while(readw(info->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT); ++ writew(0, info->rtc_base + REG_RTC_LOAD_VAL_H); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops ms_rtc_ops = { ++ .read_time = ms_rtc_read_time, ++ .set_time = ms_rtc_set_time, ++ .read_alarm = ms_rtc_read_alarm, ++ .set_alarm = ms_rtc_set_alarm, ++}; ++ ++static irqreturn_t ms_rtc_interrupt(s32 irq, void *dev_id) ++{ ++ struct ms_rtc_info *info = dev_get_drvdata(dev_id); ++ u16 reg; ++ ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ reg |= INT_CLEAR_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ RTC_DBG("RTC INTERRUPT\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++ ++#ifdef CONFIG_PM ++static s32 ms_rtc_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ if(auto_wakeup_delay_seconds) ++ { ++ struct rtc_time tm; ++ struct rtc_wkalrm alarm; ++ unsigned long seconds; ++ ms_rtc_read_time(&pdev->dev, &tm); ++ rtc_tm_to_time(&tm, &seconds); ++ RTC_DBG("[%s]: Ready to use RTC alarm, time=%ld\n", __func__, seconds); ++ seconds += auto_wakeup_delay_seconds; ++ rtc_time_to_tm(seconds, &alarm.time); ++ alarm.enabled=1; ++ ms_rtc_set_alarm(&pdev->dev, &alarm); ++ } ++ return 0; ++} ++ ++static s32 ms_rtc_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++#endif ++ ++static int ms_rtc_remove(struct platform_device *pdev) ++{ ++ struct clk *clk = of_clk_get(pdev->dev.of_node, 0); ++ int ret = 0; ++ ++ if(IS_ERR(clk)) ++ { ++ ret = PTR_ERR(clk); ++ RTC_ERR("[%s]: of_clk_get failed\n", __func__); ++ return ret; ++ } ++ clk_disable_unprepare(clk); ++ ++ return 0; ++} ++ ++static int ms_rtc_probe(struct platform_device *pdev) ++{ ++ struct ms_rtc_info *info; ++ struct resource *res; ++ struct clk *clk; ++ dev_t dev; ++ int ret = 0; ++ u16 reg; ++ u32 rate; ++ int rc; ++ ++ info = devm_kzalloc(&pdev->dev, sizeof(struct ms_rtc_info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ RTC_ERR("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ info->rtc_base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(info->rtc_base)) ++ return PTR_ERR(info->rtc_base); ++ info->pdev = pdev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) ++ { ++ RTC_ERR("[%s]: failed to get IORESOURCE_IRQ\n", __func__); ++ return -ENODEV; ++ } ++ rc = request_irq(res->start, ms_rtc_interrupt, IRQF_SHARED, "ms_rtc", &pdev->dev); ++ if (rc) ++ { ++ RTC_ERR("[%s]: request_irq()is failed. return code=%d\n", __func__, rc); ++ } ++ platform_set_drvdata(pdev, info); ++ ++ info->rtc_dev = devm_rtc_device_register(&pdev->dev, ++ dev_name(&pdev->dev), &ms_rtc_ops, ++ THIS_MODULE); ++ ++ if (IS_ERR(info->rtc_dev)) { ++ ret = PTR_ERR(info->rtc_dev); ++ RTC_ERR("[%s]: unable to register device (err=%d).\n", __func__, ret); ++ return ret; ++ } ++ ++ //Note: is it needed? ++ //device_set_wakeup_capable(&pdev->dev, 1); ++ //device_wakeup_enable(&pdev->dev); ++ ++ //init rtc ++ RTC_DBG("[%s]: hardware initialize\n", __func__); ++ //1. release reset ++ reg = readw(info->rtc_base + REG_RTC_CTRL); ++ if( !(reg & SOFT_RSTZ_BIT) ) ++ { ++ reg |= SOFT_RSTZ_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ } ++ //2. set frequency ++ clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(clk)) ++ { ++ ret = PTR_ERR(clk); ++ RTC_ERR("[%s]: of_clk_get failed\n", __func__); ++ return ret; ++ } ++ ++ /* Try to determine the frequency from the device tree */ ++ if (of_property_read_u32(pdev->dev.of_node, "clock-frequency", &rate)) ++ { ++ rate = clk_get_rate(clk); ++ } ++ else ++ { ++ clk_set_rate(clk, rate); ++ } ++ ++ clk_prepare_enable(clk); ++ RTC_ERR("[%s]: rtc setup, frequency=%lu\n", __func__, clk_get_rate(clk)); ++ writew(rate & 0xFFFF, info->rtc_base + REG_RTC_FREQ_CW_L); ++ writew((rate >>16) & 0xFFFF, info->rtc_base + REG_RTC_FREQ_CW_H); ++ ++ //3. enable counter ++ reg |= CNT_EN_BIT; ++ writew(reg, info->rtc_base + REG_RTC_CTRL); ++ ++ if (0 != (ret = alloc_chrdev_region(&dev, 0, 1, "ms_rtc"))) ++ return ret; ++ ++ info->rtc_devnode = device_create(msys_get_sysfs_class(), NULL, dev, NULL, "ms_rtc"); ++ device_create_file(info->rtc_devnode, &dev_attr_auto_wakeup_timer); ++ ++ return ret; ++} ++ ++static const struct of_device_id ms_rtc_of_match_table[] = { ++ { .compatible = "mstar,infinity-rtc" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_rtc_of_match_table); ++ ++static struct platform_driver ms_rtc_driver = { ++ .remove = ms_rtc_remove, ++ .probe = ms_rtc_probe, ++#ifdef CONFIG_PM ++ .suspend = ms_rtc_suspend, ++ .resume = ms_rtc_resume, ++#endif ++ .driver = { ++ .name = "ms_rtc", ++ .owner = THIS_MODULE, ++ .of_match_table = ms_rtc_of_match_table, ++ }, ++}; ++ ++module_platform_driver(ms_rtc_driver); ++ ++MODULE_AUTHOR("MStar Semiconductor, Inc."); ++MODULE_DESCRIPTION("MStar RTC Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/mstar/samples/.gitignore b/drivers/mstar/samples/.gitignore +new file mode 100644 +index 00000000..175edbb7 +--- /dev/null ++++ b/drivers/mstar/samples/.gitignore +@@ -0,0 +1,2 @@ ++*.bin ++*.exe +diff --git a/drivers/mstar/samples/README b/drivers/mstar/samples/README +new file mode 100644 +index 00000000..6d365be8 +--- /dev/null ++++ b/drivers/mstar/samples/README +@@ -0,0 +1,24 @@ ++Compile these small test program then execute them on target ++EX: arm-linux-gnueabihf-gcc -DPLATFORM_NAME=INFINITY -static -o regio.bin regio.c ++ ++Basically one C file should generate one test application ++ ++Use the "PLATFORM_NAME" define to check chip difference(CEDRIC, CHICAGO, INFINITY) ++Use "uname()" C API in code to check kernel version ++Application may need to be recompiled for different PLATFORM_NAME ++Application "SHOULD NOT" need to be recompiled for different kernel version ++ ++Check the unametest.c, the output is as following: ++ ++system name = Linux ++node name = (none) ++release = 3.18.14 ++version = #421 SMP PREEMPT Thu Jun 11 07:05:52 CST 2015 ++machine = armv7l ++ ++ ++ajtc.c network socket test client, packet generator ++ajts.c network socket test server, packet receiver ++us_ticks.c check the wrapping of IOCTL_MSYS_GET_US_TICKS ++regio.c userspace register w/r sample ++dmem.c userspace DMEM allocation & w/r sample +\ No newline at end of file +diff --git a/drivers/mstar/samples/ajtc.c b/drivers/mstar/samples/ajtc.c +new file mode 100644 +index 00000000..f5fdfbd2 +--- /dev/null ++++ b/drivers/mstar/samples/ajtc.c +@@ -0,0 +1,189 @@ ++#include ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++unsigned int checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++int d=0; ++int generate_aj_packet(char **buf,int dataLen, int packetid ) ++{ ++ char *pkt=malloc(dataLen+8); ++ int ckm=0; ++ int i=0; ++ if(pkt==NULL) ++ { ++ printf("malloc aj_packet failed!!\n"); ++ return -1; ++ } ++ pkt[0]=(char)0x51; ++ pkt[1]=(char)0x58; ++ pkt[2]=(char)0x91; ++ pkt[3]=(char)0x58; ++ pkt[4]=(char)(dataLen&0xFF); ++ pkt[5]=(char)((dataLen>>8)&0xFF); ++ pkt[6]=(char)((dataLen>>16)&0xFF); ++ pkt[7]=(char)((dataLen>>24)&0xFF); ++ d=0; ++// System.out.println("dataLen="+dataLen+", "+String.format("0x%02X,0x%02X,0x%02X,0x%02X",pkt[4],pkt[5],pkt[6],pkt[7])); ++ pkt[8]=(char)(packetid&0xFF); ++ pkt[9]=(char)((packetid>>8)&0xFF); ++ pkt[10]=(char)((packetid>>16)&0xFF); ++ pkt[11]=(char)((packetid>>24)&0xFF); ++ ++ pkt[12]=(char)('A'); ++ pkt[13]=(char)('J'); ++ pkt[14]=(char)('S'); ++ pkt[15]=(char)('X'); ++ ++ pkt[16]=(char)('X'); ++ pkt[17]=(char)('S'); ++ pkt[18]=(char)('J'); ++ pkt[19]=(char)('A'); ++ ++ pkt[20]=(char)(0); ++ pkt[21]=(char)(0); ++ pkt[22]=(char)(0); ++ pkt[23]=(char)(0); ++ ++ ++ for(i=16;i>8)&0xFF);; ++ pkt[dataLen+6]=(char)((ckm>>16)&0xFF);; ++ pkt[dataLen+7]=(char)((ckm>>24)&0xFF);; ++ //System.out.println("dataLen="+dataLen+", "+String.format("0x%02X,0x%02X,0x%02X,0x%02X, 0x%08X, 0x%02X,0x%02X,0x%02X,0x%02X",pkt[4],pkt[5],pkt[6],pkt[7],ckm,pkt[dataLen+4],pkt[dataLen+5],pkt[dataLen+6],pkt[dataLen+7])); ++ //System.out.println("pktid="+packetid+", checksum=0x"+Integer.toHexString(ckm).toUpperCase()); ++ *buf=pkt; ++ return (dataLen+8); ++} ++ ++int pktcount; ++int main(int argc , char **argv) ++{ ++ ++ int sock; ++ const char* default_ip="10.10.10.107"; ++ int port=3333; ++ int count=100000; ++ int loop=0; ++ int option=0; ++ int packet_size_fixed=0; ++ char server_ip[128]; ++ struct sockaddr_in server; ++ srand( (unsigned)time(NULL) ); ++ ++ ++ ++ ++ printf("[AJ Test Client(packet sender)]\n"); ++ ++ memset(server_ip,0,sizeof(server_ip)); ++ memcpy(server_ip,default_ip,strlen(default_ip)); ++ ++ ++ while ((option = getopt(argc, argv,"p:s:c:f")) != -1) { ++ switch (option) { ++ case 's' : //server ip ++ { ++ memset(server_ip,0,sizeof(server_ip)); ++ memcpy(server_ip,optarg,strlen(optarg)); ++ } ++ break; ++ case 'p' : port = atoi(optarg); //port ++ break; ++ case 'c' : count = atoi(optarg); // test packet count ++ break; ++ ++ case 'f' : packet_size_fixed=1; ++ break; ++ ++ ++ default: printf("invalide args\n"); ++ exit(EXIT_FAILURE); ++ } ++ } ++ ++ if(0==count)loop=1; ++ ++ //Create socket ++ sock = socket(AF_INET , SOCK_STREAM , 0); ++ if (sock == -1) ++ { ++ printf("Could not create socket"); ++ } ++ ++ bzero(&server,sizeof(server)); ++ server.sin_addr.s_addr = inet_addr(server_ip); ++ server.sin_family = AF_INET; ++ server.sin_port = htons( port ); ++ ++ //Connect to remote server ++ if (connect(sock , (struct sockaddr *)&server , sizeof(server)) < 0) ++ { ++ perror("connect failed. Error"); ++ return 1; ++ } ++ ++ printf("Connected\n"); ++ ++ //keep communicating with server ++ while((count>0) || loop) ++ { ++ char *abuf[1]={0}; ++ int packet_size=1024; ++ int alen=0; ++ if(!packet_size_fixed) ++ { ++ packet_size= 64+(int)(((double)(rand()) / (RAND_MAX + 1.0))*128*1024); ++ } ++ ++ if((alen=generate_aj_packet(abuf, packet_size, pktcount))<=0) ++ { ++ printf("generate_aj_packet error!!\n"); ++ goto DONE; ++ } ++ send(sock,*abuf,alen,0); ++ free(*abuf); ++ if(!loop)count--; ++ pktcount++; ++ if((pktcount%1000)==0)printf("%d ajtest packet sent...\n",pktcount); ++ ++ } ++DONE: ++ close(sock); ++ return 0; ++} +diff --git a/drivers/mstar/samples/ajts.c b/drivers/mstar/samples/ajts.c +new file mode 100644 +index 00000000..a0dfacd4 +--- /dev/null ++++ b/drivers/mstar/samples/ajts.c +@@ -0,0 +1,276 @@ ++#include ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++#include ++#include ++#include ++#define __ERR printf ++volatile sig_atomic_t flag = 0; ++int outfd; ++char* fName=NULL; ++void finish_function(int sig){ // can be called asynchronously ++ flag = 1; // set flag ++ if(NULL!=fName) ++ { ++ free(fName); ++ } ++ close(outfd); ++ exit(-3); ++} ++ ++//using namespace std; ++int recv_with_header(int fd, char **buf) ++{ ++ unsigned char flag[4]; ++ int ret=recv(fd,flag,4,0); ++ int len; ++ int offset=0; ++ if(ret<=0) ++ { ++ ++ if(errno==0) ++ { ++ return 0; ++ } ++ __ERR("recv flag error, err=%s, %d\n",strerror(errno),errno); ++ return -3; ++ } ++ ++ if(flag[0]!=0x51 || flag[1]!=0x58 || flag[2]!=0x91 || flag[3]!=0x58) ++ { ++ __ERR("recv bad flag: 0x%02x 0x%02x 0x%02x 0x%02x\n",flag[0],flag[1],flag[2],flag[3]); ++ return -4; ++ } ++ ++ ++ ret=recv(fd,flag,4,0); ++ if(ret<=0) ++ { ++ __ERR("recv len error, err=%s\n",strerror(errno)); ++ return -5; ++ } ++ ++ len=(flag[3]<<24) + (flag[2]<<16)+(flag[1]<<8) + (flag[0]); ++ if(len<=0) ++ { ++ __ERR("recv bad len: %d, 0x%02x 0x%02x 0x%02x 0x%02x\n",len, flag[0],flag[1],flag[2],flag[3]); ++ return -6; ++ } ++// printf(" len=0x%08X\n",len); ++ ++ if(len>=(15*1024*1024)) ++ { ++ __ERR("recv bad len: %d\n",len); ++ return -7; ++ } ++ ++ ++ *buf=(char *)malloc(len + 2); ++ if(*buf==NULL) ++ { ++ __ERR("new buf failed.\n"); ++ return -8; ++ } ++// printf(" malloc success, 0x%08X 0x%08X!!\n",*buf, tbuf); ++ memset( *buf, 0, len+2); ++// printf(" memset success!!\n"); ++ ++ while(len) ++ { ++ ret=recv(fd, *buf + offset,len,0); ++// printf(" ret=%d\n",ret); ++ if(ret<=0) ++ { ++ __ERR("recv data error, err=%s\n",strerror(errno)); ++ return -9; ++ } ++ else ++ { ++ offset+=ret; ++ len-=ret; ++ } ++ } ++// printf(" recv: %d bytes success\n",offset); ++ return offset; ++} ++ ++unsigned int checksum( unsigned char * buffer, long length ) ++{ ++ ++ long index; ++ unsigned int checksum; ++ ++ for( index = 0L, checksum = 0; index < length; index++) ++ { ++ checksum += (int)buffer[index]; ++ checksum &= 0x0FFFFFFF; ++// if(index<10)printf("%d %d\n",buffer[index],checksum); ++ ++ } ++ return checksum; ++ ++} ++ ++int main(int argc, char** argv) ++{ ++ int option = 0; ++ int port =3333; ++ ++ char *tbuf[1]={0}; ++ int sockfd; ++ struct sockaddr_in dest; ++ ++ printf("[AJ Test Server]\n"); ++ ++ ++ //The two options l and b expect numbers as argument ++ while ((option = getopt(argc, argv,"p:f:")) != -1) { ++ switch (option) { ++ case 'f' : ++ { ++ int len=strlen(optarg)+1; ++ fName=(char *)malloc(strlen(optarg)+1); ++ if(NULL==fName) ++ { ++ printf("failed to allocate memory, exit -1!!\n"); ++ exit(-1); ++ } ++ memset(fName,0,len); ++ memcpy(fName,optarg,(len-1)); ++ ++ } ++ break; ++ case 'p' : port = atoi(optarg); ++ break; ++ ++ default: printf("invalide args\n"); ++ exit(EXIT_FAILURE); ++ } ++ } ++#if 0 ++ outfd = open(fName,O_RDWR|O_CREAT|O_TRUNC,0777); ++ ++ if(outfd<0) ++ { ++ printf("open file:%s error!!\n",fName); ++ perror("error:"); ++ return -1; ++ } ++#endif ++ if(NULL!=fName) ++ { ++ printf("Server ready!! fName: %s, socket_port: %d\n",fName,port); ++ }else ++ { ++ printf("Server ready!! socket_port: %d\n",port); ++ } ++ sleep(1); ++ ++ sockfd=socket(AF_INET,SOCK_STREAM,0); ++ bzero(&dest,sizeof(dest)); ++ dest.sin_family=AF_INET; ++ dest.sin_port=htons(port); ++ dest.sin_addr.s_addr=INADDR_ANY; ++ signal(SIGINT, finish_function); ++ bind(sockfd,(struct sockaddr*)&dest,sizeof(dest)); ++ listen(sockfd,20); ++ ++ ++ while(1) ++ { ++ int clientfd; ++ struct sockaddr_in client_addr; ++ int addrlen=sizeof(client_addr); ++ int pktCount=0; ++ ++ clientfd=accept(sockfd,(struct sockaddr*)&client_addr,(socklen_t*)&addrlen); ++ if (clientfd < 0) ++ { ++ perror("accept failed"); ++ return -1; ++ } ++ printf("client connection accepted\n"); ++ while(1) ++ { ++ int ret=0; ++ ++ ret=recv_with_header(clientfd,tbuf); ++ ++ if(ret>0) ++ { ++#if 0 ++ write(outfd,*tbuf,ret); ++#endif ++ unsigned char *buf=(unsigned char*)tbuf[0];//(unsigned char *)(*tbuf); ++ int pktid=0; ++ int pktcs=0;//((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ int cs=0; ++// if(0==pktCount%100) ++// { ++// printf("pktCount: %08d\n",pktCount); ++// } ++ pktcs=((buf[ret-1])<<24) + (buf[ret-2]<<16)+(buf[ret-3]<<8) + (buf[ret-4]); ++ cs=checksum(buf,ret-4); ++ pktid=(buf[3]<<24) + (buf[2]<<16)+(buf[1]<<8) + (buf[0]); ++ if(pktcs!=cs || pktid!=pktCount) ++ { ++ int j=0; ++ unsigned int lc=0; ++ printf(" ERROR!! pktCount[%d, %d]: cs=0x%08X, pktcs=0x%08X\n\n",pktCount,pktid,cs,pktcs); ++ for(j=0;j 0 ) ++// { ++// //Send the message back to client ++// write(client_sock , client_message , strlen(client_message)); ++// } ++ ++ } ++ ++ if(NULL!=fName) ++ { ++ free(fName); ++ } ++ close(outfd); ++ return 0; ++} +diff --git a/drivers/mstar/samples/dmem.c b/drivers/mstar/samples/dmem.c +new file mode 100644 +index 00000000..ada844af +--- /dev/null ++++ b/drivers/mstar/samples/dmem.c +@@ -0,0 +1,157 @@ ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++ ++ ++ ++#include "../../drivers/mstar/include/mdrv_msys_io.h" ++#include "../../drivers/mstar/include/mdrv_msys_io_st.h" ++ ++//void sleep_ms(int milliseconds) // cross-platform sleep function ++//{ ++//#ifdef WIN32 ++// Sleep(milliseconds); ++//#elif _POSIX_C_SOURCE >= 199309L ++// struct timespec ts; ++// ts.tv_sec = 0; ++// ts.tv_nsec = milliseconds * 1000000; ++// nanosleep(&ts, NULL); ++//#else ++// usleep(milliseconds * 1000); ++//#endif ++//} ++ ++ ++ ++ ++int main ( int argc, char **argv ) ++{ ++ int msys_fd=open("/dev/msys",O_RDWR|O_SYNC); ++ int mem_fd=open("/dev/mem",O_RDWR|O_SYNC); ++// int kmem_fd=open("/dev/kmem",O_RDWR|O_SYNC); ++ unsigned char * map_base; ++ MSYS_DMEM_INFO info; ++ char **ptr=NULL; ++ unsigned long addr; ++ unsigned char content; ++ int i = 0; ++ ++ if(-1==msys_fd){ ++ printf("can't open /dev/msys\n"); ++ goto OPEN_FAILED; ++ } ++ ++ if(-1==mem_fd){ ++ printf("can't open /dev/mem\n"); ++ goto FAILED; ++ } ++// ++// if(-1==kmem_fd){ ++// printf("can't open /dev/kmem\n"); ++// goto OPEN_FAILED; ++// } ++ ++ if(0==strncmp("-req",argv[1],4)) ++ { ++ ++ if(0==strncmp("0x",argv[2],2)) ++ { ++ info.length=strtol(argv[2],ptr,16); ++ } ++ else ++ { ++ info.length=atoi(argv[2]); ++ } ++ ++ memset(info.name,16,0); ++ if(argc>3) ++ { ++ strncpy(info.name,argv[3],15); ++ } ++ ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_REQUEST_DMEM, &info)) ++ { ++ printf("DMEM request failed!!\n"); ++ goto FAILED; ++ } ++ printf("PHYS=0x%08X,KVIRT=0x%08X, LENGTH=0x%08X\n",(unsigned int)info.phys,(unsigned int)info.kvirt,(unsigned int)info.length); ++ ++ map_base = mmap(NULL, info.length , PROT_READ|PROT_WRITE, MAP_SHARED, mem_fd, info.phys); ++ ++ if (map_base == 0) ++ { ++ printf("NULL pointer!\n"); ++ goto FAILED; ++ ++ } ++ else ++ { ++ printf("Successfull!\n"); ++ } ++ ++ ++ for (;i < 0xff; ++i) ++ { ++ addr = (unsigned long)(map_base + i); ++ content = map_base[i]; ++ printf("address: 0x%lx content 0x%x\t\t", addr, (unsigned int)content); ++ ++ map_base[i] = (unsigned char)i; ++ content = map_base[i]; ++ printf("updated address: 0x%lx content 0x%x\n", addr, (unsigned int)content); ++ } ++ munmap(map_base, 0xff); ++ ++ }else if(0==strncmp("-rel",argv[1],4)){ ++ if(0==strncmp("0x",argv[2],2)) ++ { ++ info.phys=strtol(argv[2],ptr,16); ++ } ++ else ++ { ++ info.phys=atoi(argv[2]); ++ } ++ ++ memset(info.name,16,0); ++ if(argc>3) ++ { ++ strncpy(info.name,argv[3],15); ++ } ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_RELEASE_DMEM, &info)) ++ { ++ printf("DMEM release failed!!\n"); ++ goto FAILED; ++ } ++ } ++ else{ ++ printf("unsupported usage for dmem\n"); ++ printf("usage:\n"); ++ printf(" -req [name]\n"); ++ printf(" -rel [name]\n"); ++ ++ ++ } ++ ++ ++ close(msys_fd); ++ close(mem_fd); ++// close(kmem_fd); ++ return 0; // Indicates that everything vent well. ++ ++FAILED: ++ if(-1!=msys_fd)close(msys_fd); ++ if(-1!=mem_fd)close(mem_fd); ++// if(-1!=kmem_fd)close(kmem_fd); ++ ++OPEN_FAILED: ++ return -1; ++ ++} +diff --git a/drivers/mstar/samples/regio.c b/drivers/mstar/samples/regio.c +new file mode 100644 +index 00000000..2757fd60 +--- /dev/null ++++ b/drivers/mstar/samples/regio.c +@@ -0,0 +1,113 @@ ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++#include ++#include "../../drivers/mstar/include/mdrv_msys_io.h" ++#include "../../drivers/mstar/include/mdrv_msys_io_st.h" ++ ++int main(int argc, char *argv[]) ++{ ++ int msys_fd=-1; ++ int mem_fd=-1; ++ void *reg_map; ++ char **ptr=NULL; ++ int rlen=8; ++ int roffset; ++ MSYS_MMIO_INFO reg_map_info; ++ //printf("[mmio]START\n"); ++ ++ msys_fd = open("/dev/msys", O_RDWR|O_SYNC); ++ if (msys_fd == -1) ++ { ++ printf("Can't open /dev/msys\n"); ++ goto OUT; ++ } ++ mem_fd = open("/dev/mem", O_RDWR|O_SYNC); ++ if (mem_fd == -1) ++ { ++ printf("Can't open /dev/mem\n"); ++ goto OUT; ++ } ++ ++ //printf("devices open success!!\n"); ++ ++ if(0!=ioctl(msys_fd, IOCTL_MSYS_GET_RIU_MAP, ®_map_info)) ++ { ++ printf("IOCTL_MSYS_GET_RIU_MAP failed!!\n"); ++ goto OUT; ++ } ++// printf("reg_map_info: addr=0x%08X, size=0x%08X\n",(unsigned int)reg_map_info.addr,reg_map_info.size); ++ ++ if(((unsigned int)(reg_map=mmap (NULL, reg_map_info.size, PROT_READ|PROT_WRITE, MAP_SHARED , mem_fd, reg_map_info.addr))) == (unsigned int)MAP_FAILED) ++ { ++ printf("reg_map failed!!\n"); ++ goto OUT; ++ } ++ ++ sleep(1); ++// printf("The reg_map is ready, addr=0x%08X\n",(unsigned int)reg_map); ++ ++ if(0==strncmp("-r",argv[1],4)) ++ { ++ int i=0; ++ if(0==strncmp("0x",argv[2],2)) ++ { ++ roffset=strtol(argv[2],ptr,16); ++ } ++ else ++ { ++ roffset=atoi(argv[2]); ++ } ++ ++ ++ if(0==strncmp("0x",argv[3],2)) ++ { ++ rlen=strtol(argv[3],ptr,16); ++ } ++ else ++ { ++ rlen=atoi(argv[3]); ++ } ++ ++ rlen=(rlen<8)?8:rlen; ++ ++ ++ int *p=(int *)(reg_map+roffset); ++ for(i=0;i(32bit reg offset) (8 aligned)\n"); ++ printf(" -w
(32bit reg offset) \n"); ++ ++ } ++ ++ ++ ++ if(0!=munmap(reg_map,reg_map_info.size-1)) ++ { ++ printf("munmap failed!!\n"); ++ reg_map=NULL; ++ } ++ ++OUT: ++ if(msys_fd!=-1)close(msys_fd); ++ if(mem_fd!=-1)close(mem_fd); ++ ++// printf("[regio]END\n"); ++} +diff --git a/drivers/mstar/samples/unametest.c b/drivers/mstar/samples/unametest.c +new file mode 100644 +index 00000000..ad10842b +--- /dev/null ++++ b/drivers/mstar/samples/unametest.c +@@ -0,0 +1,34 @@ ++#include ++#include ++#include ++#include ++/* ++The output is as following: ++system name = Linux ++node name = (none) ++release = 3.18.14 ++version = #421 SMP PREEMPT Thu Jun 11 07:05:52 CST 2015 ++machine = armv7l ++*/ ++int main(void) { ++ ++ struct utsname buffer; ++ ++ errno = 0; ++ if (uname(&buffer) != 0) { ++ perror("uname"); ++ exit(EXIT_FAILURE); ++ } ++ ++ printf("system name = %s\n", buffer.sysname); ++ printf("node name = %s\n", buffer.nodename); ++ printf("release = %s\n", buffer.release); ++ printf("version = %s\n", buffer.version); ++ printf("machine = %s\n", buffer.machine); ++ ++ #ifdef _GNU_SOURCE ++ printf("domain name = %s\n", buffer.domainname); ++ #endif ++ ++ return EXIT_SUCCESS; ++} +diff --git a/drivers/mstar/samples/us_ticks.c b/drivers/mstar/samples/us_ticks.c +new file mode 100644 +index 00000000..57f58053 +--- /dev/null ++++ b/drivers/mstar/samples/us_ticks.c +@@ -0,0 +1,48 @@ ++#include ++#include ++#include ++#include // for usleep ++#include ++#include ++#include ++#include ++#include /* mmap() is defined in this header */ ++#include ++ ++#define MSYS_IOCTL_MAGIC 'S' ++ ++#define IOCTL_MSYS_GET_US_TICKS _IO(MSYS_IOCTL_MAGIC, 0x31) ++ ++int main(int argc, char** argv) ++{ ++ int msys_fd=open("/dev/msys",O_RDWR|O_SYNC); ++ unsigned long long t0=0,t1=0; ++ int count=0; ++ if(-1==msys_fd) ++ { ++ printf("can't open /dev/msys\n"); ++ goto OPEN_FAILED; ++ } ++ ++ while(1) ++ { ++ ioctl(msys_fd, IOCTL_MSYS_GET_US_TICKS, &t0); ++ if(t0 ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++#include "mdrv_sar.h" ++ ++ ++//#define OPEN_SAR_DEBUG ++#define INFINITY ++static U32 _gMIO_MapBase = 0; ++ ++#ifdef OPEN_SAR_DEBUG //switch printk ++#define sarDbg printk ++#else ++#define sarDbg(...) ++#endif ++ ++struct ms_sar ++{ ++ struct device *dev; ++ void __iomem *reg_base; ++}; ++ ++static int ms_sar_open(struct inode *inode, struct file *file); ++int ms_sar_get(int ch); ++static long ms_sar_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); ++void ms_sar_hw_init(void); ++ ++ ++static const struct file_operations sar_fops = ++{ ++ .open = ms_sar_open, ++ .unlocked_ioctl = ms_sar_ioctl, ++ ++}; ++static struct miscdevice sar_miscdev = {MISC_DYNAMIC_MINOR, DEVICE_NAME, &sar_fops}; ++ ++ ++BOOL HAL_SAR_Write2Byte(U32 u32RegAddr, U16 u16Val) ++{ ++ (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))) = u16Val; ++ return TRUE; ++} ++ ++U16 HAL_SAR_Read2Byte(U32 u32RegAddr) ++{ ++ return (*(volatile U32*)(_gMIO_MapBase+((u32RegAddr & 0xFFFFFF00ul) << 1) + (((u32RegAddr & 0xFF)/ 2) << 2))); ++} ++ ++BOOL HAL_SAR_Write2ByteMask(U32 u32RegAddr, U16 u16Val, U16 u16Mask) ++{ ++ u16Val = (HAL_SAR_Read2Byte(u32RegAddr) & ~u16Mask) | (u16Val & u16Mask); ++ //sarDbg("sar IOMap base:%16llx u16Val:%4x\n", _gMIO_MapBase, u16Val); ++ HAL_SAR_Write2Byte(u32RegAddr, u16Val); ++ return TRUE; ++} ++ ++static long ms_sar_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) ++{ ++ S32 s32Err= 0; ++ ADC_CONFIG_READ_ADC adcCfg; ++ ++ //printk("%s is invoked\n", __FUNCTION__); ++ ++ /* ++ * extract the type and number bitfields, and don't decode ++ * wrong cmds: return ENOTTY (inappropriate ioctl) before access_ok() ++ */ ++ if ((SARADC_IOC_MAGIC!= _IOC_TYPE(cmd)) || (_IOC_NR(cmd)> SARADC_IOC_MAXNR)) ++ { ++ return -ENOTTY; ++ } ++ ++ /* ++ * the direction is a bitmask, and VERIFY_WRITE catches R/W ++ * transfers. `Type' is user-oriented, while ++ * access_ok is kernel-oriented, so the concept of "read" and ++ * "write" is reversed ++ */ ++ if (_IOC_DIR(cmd) & _IOC_READ) ++ { ++ s32Err = !access_ok(VERIFY_WRITE, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ else if (_IOC_DIR(cmd) & _IOC_WRITE) ++ { ++ s32Err = !access_ok(VERIFY_READ, (void __user *)arg, _IOC_SIZE(cmd)); ++ } ++ if (s32Err) ++ { ++ return -EFAULT; ++ } ++ ++ ++ ++ switch(cmd) ++ { ++ case MS_SAR_INIT: ++ ms_sar_hw_init(); ++ break; ++ ++ case MS_SAR_SET_CHANNEL_READ_VALUE: ++ if(copy_from_user(&adcCfg, (ADC_CONFIG_READ_ADC __user *)arg, sizeof(ADC_CONFIG_READ_ADC))) ++ { ++ return EFAULT; ++ } ++ ++ channel = adcCfg.channel_value & 3; ++ ++ adcCfg.adc_value = ms_sar_get(channel); ++ sarDbg("channel = %d , adc =%d \n",channel, adcCfg.adc_value); ++ ++ if(copy_to_user((ADC_CONFIG_READ_ADC __user *)arg, &adcCfg, sizeof( ADC_CONFIG_READ_ADC))) ++ { ++ return EFAULT; ++ } ++ break; ++ ++ default: ++ printk("ioctl: unknown command\n"); ++ return -ENOTTY; ++ } ++ return 0; ++ ++} ++ ++static int ms_sar_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++void ms_sar_hw_init(void) ++{ ++ HAL_SAR_Write2Byte(REG_SAR_CTRL0,0x0a20); ++ //HAL_SAR_Write2Byte(REG_SAR_CKSAMP_PRD,0x0005); ++ //HAL_SAR_Write2ByteMask(REG_SAR_CTRL0,0x4000,0x4000); ++} ++EXPORT_SYMBOL(ms_sar_hw_init); ++ ++int ms_sar_get(int ch) ++{ ++ U16 value=0; ++ U32 count=0; ++ HAL_SAR_Write2ByteMask(REG_SAR_CTRL0,BIT14, 0x4000); ++ while(HAL_SAR_Read2Byte(REG_SAR_CTRL0)&BIT14 && count<100000) ++ { ++ udelay(1); ++ count++; ++ } ++ ++ switch(ch) ++ { ++ case 0: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT0, BIT0); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH1_DATA); ++ break; ++ case 1: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT1, BIT1); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH2_DATA); ++ break; ++ case 2: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT2, BIT2); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH3_DATA); ++ break; ++ case 3: ++ HAL_SAR_Write2ByteMask(REG_SAR_AISEL_CTRL, BIT3, BIT3); ++ value=HAL_SAR_Read2Byte(REG_SAR_CH4_DATA); ++ break; ++ default: ++ printk(KERN_ERR "error channel,support SAR0,SAR1,SAR2,SAR3\n"); ++ break; ++ } ++ return value; ++} ++EXPORT_SYMBOL(ms_sar_get); ++ ++ ++static int infinity_sar_probe(struct platform_device *pdev) ++{ ++ struct device *dev; ++ struct ms_sar *sar; ++ struct resource *res; ++ ++ //sarDbg("[SAR] infinity_sar_probe \n"); ++ printk("[SAR] infinity_sar_probe \n"); ++ dev = &pdev->dev; ++ sar = devm_kzalloc(dev, sizeof(*sar), GFP_KERNEL); ++ if (!sar) ++ return -ENOMEM; ++ ++ sar->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) ++ { ++ sarDbg("[%s]: failed to get IORESOURCE_MEM\n", __func__); ++ return -ENODEV; ++ } ++ sar->reg_base = devm_ioremap_resource(&pdev->dev, res); ++ _gMIO_MapBase=(U32)sar->reg_base; ++ ++ misc_register(&sar_miscdev); ++ return 0; ++} ++ ++static int infinity_sar_remove(struct platform_device *dev) ++{ ++ sarDbg("[SAR]infinity_sar_remove \n"); ++ misc_deregister(&sar_miscdev); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++ ++static int infinity_sar_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ sarDbg("[SAR]infinity_sar_suspend \n"); ++ return 0; ++} ++ ++static int infinity_sar_resume(struct platform_device *dev) ++{ ++ sarDbg("[SAR]infinity_sar_resume \n"); ++ return 0; ++} ++ ++#else ++#define infinity_sar_suspend NULL ++#define infinity_sar_resume NULL ++#endif /* CONFIG_PM */ ++ ++ ++ ++ ++static const struct of_device_id ms_sar_of_match_table[] = ++{ ++ { .compatible = "mstar,infinity-sar" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_sar_of_match_table); ++ ++static struct platform_driver infinity_sar_driver = ++{ ++ .probe = infinity_sar_probe, ++ .remove = infinity_sar_remove, ++#ifdef CONFIG_PM ++ .suspend = infinity_sar_suspend, ++ .resume = infinity_sar_resume, ++#endif ++ .driver = { ++ .owner = THIS_MODULE, ++ .name = "infinity-sar", ++ .of_match_table = ms_sar_of_match_table, ++ }, ++}; ++ ++module_platform_driver(infinity_sar_driver); ++ ++MODULE_AUTHOR("MStar Semiconductor, Inc."); ++MODULE_DESCRIPTION("infinity Sar Device Driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:infinity-sar"); +diff --git a/drivers/mstar/sar/mdrv_sar.h b/drivers/mstar/sar/mdrv_sar.h +new file mode 100644 +index 00000000..1f837f84 +--- /dev/null ++++ b/drivers/mstar/sar/mdrv_sar.h +@@ -0,0 +1,103 @@ ++//----------------------------------------------------------------------------- ++// ++// Copyright (c) 2008 MStar Semiconductor, Inc. All rights reserved. ++// ++//----------------------------------------------------------------------------- ++// FILE ++// mdrv_wdt.h ++// ++// DESCRIPTION ++// ++// ++// HISTORY ++// ++//----------------------------------------------------------------------------- ++ ++#ifndef __MDRV_SAR_H ++#define __MDRV_SAR_H ++ ++//#include ++//#include "mach/platform.h" ++#include "../include/ms_types.h" ++#include "../include/ms_platform.h" ++ ++#define DEVICE_NAME "sar" ++ ++#define INFINITY_BASE_REG_RIU_PA (0x1F000000) ++#define BASE_REG_WDT_PA GET_REG_ADDR(INFINITY_BASE_REG_RIU_PA, 0x001800) ++//#define BASE_REG_PM_PA GET_REG_ADDR(CHICAGO_BASE_REG_RIU_PA, 0x000700) ++#define BK_REG(reg) ((reg) << 2) ++ ++static int channel = 1; ++//static int mode = 0; ++ ++typedef struct ++{ ++ int channel_value; ++ int adc_value; ++}ADC_CONFIG_READ_ADC; ++ ++ ++#define SARADC_IOC_MAGIC 'a' ++#define MS_SAR_INIT _IO(SARADC_IOC_MAGIC, 0) ++#define MS_SAR_SET_CHANNEL_READ_VALUE _IO(SARADC_IOC_MAGIC, 1) ++ ++#define SARADC_IOC_MAXNR 2 ++ ++#define REG_SAR_CTRL0 0x00*2 ++#define REG_SAR_CKSAMP_PRD 0x01*2 ++#define REG_SAR_GCR_SAR_CH8 0x02*2 ++#define REG_SAR_AISEL_CTRL 0x11*2 ++#define REG_SAR_GPIO_CTRL 0x12*2 ++#define REG_SAR_INT_MASK 0x14*2 ++#define REG_SAR_INT_CLR 0x15*2 ++#define REG_SAR_INT_FORCE 0x16*2 ++#define REG_SAR_INT_STATUS 0x17*2 ++#define REG_SAR_CMP_OUT_RDY 0x18*2 ++#define REG_SAR_CH_REF_V_SEL 0x19*2 ++#define REG_SAR_CH1_UPB 0x20*2 ++#define REG_SAR_CH2_UPB 0x21*2 ++#define REG_SAR_CH3_UPB 0x22*2 ++#define REG_SAR_CH4_UPB 0x23*2 ++#define REG_SAR_CH5_UPB 0x24*2 ++#define REG_SAR_CH6_UPB 0x25*2 ++#define REG_SAR_CH7_UPB 0x26*2 ++#define REG_SAR_CH8_UPB 0x27*2 ++#define REG_SAR_CH1_LOB 0x30*2 ++#define REG_SAR_CH2_LOB 0x31*2 ++#define REG_SAR_CH3_LOB 0x32*2 ++#define REG_SAR_CH4_LOB 0x33*2 ++#define REG_SAR_CH5_LOB 0x34*2 ++#define REG_SAR_CH6_LOB 0x35*2 ++#define REG_SAR_CH7_LOB 0x36*2 ++#define REG_SAR_CH8_LOB 0x37*2 ++#define REG_SAR_CH1_DATA 0x40*2 ++#define REG_SAR_CH2_DATA 0x41*2 ++#define REG_SAR_CH3_DATA 0x42*2 ++#define REG_SAR_CH4_DATA 0x43*2 ++#define REG_SAR_CH5_DATA 0x44*2 ++#define REG_SAR_CH6_DATA 0x45*2 ++#define REG_SAR_CH7_DATA 0x46*2 ++#define REG_SAR_CH8_DATA 0x47*2 ++#define REG_SAR_SMCARD_CTRL 0x50*2 ++#define REG_SAR_FCIE_INT_CTRL 0x51*2 ++#define REG_SAR_INT_DIRECT2TOP_SEL 0x60*2 ++ ++#define BIT_0 0x1 ++#define BIT_1 0x2 ++#define BIT_2 0x4 ++#define BIT_3 0x8 ++#define BIT_4 0x10 ++#define BIT_5 0x20 ++#define BIT_6 0x40 ++#define BIT_7 0x80 ++#define BIT_8 0x100 ++#define BIT_9 0x200 ++#define BIT_10 0x400 ++#define BIT_11 0x800 ++#define BIT_12 0x1000 ++#define BIT_13 0x2000 ++#define BIT_14 0x4000 ++#define BIT_15 0x8000 ++ ++#endif +diff --git a/drivers/mstar/scl/Kconfig b/drivers/mstar/scl/Kconfig +new file mode 100644 +index 00000000..5805036a +--- /dev/null ++++ b/drivers/mstar/scl/Kconfig +@@ -0,0 +1,14 @@ ++config MS_SCL ++ bool "SCL driver" ++ help ++ To enable MSTAR SCL driver. ++ ++config MS_SCL_INFINITY ++ bool "support I1 driver" ++ depends on MS_SCL ++ depends on ARCH_INFINITY ++ ++config MS_SCL_INFINITY3 ++ bool "support I3 driver" ++ depends on MS_SCL ++ depends on ARCH_INFINITY3 +diff --git a/drivers/mstar/scl/Makefile b/drivers/mstar/scl/Makefile +new file mode 100644 +index 00000000..756ebdb3 +--- /dev/null ++++ b/drivers/mstar/scl/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_MS_SCL_INFINITY) += infinity/ ++obj-$(CONFIG_MS_SCL_INFINITY3) += infinity3/ +diff --git a/drivers/mstar/scl/infinity/Makefile b/drivers/mstar/scl/infinity/Makefile +new file mode 100644 +index 00000000..b2759f3c +--- /dev/null ++++ b/drivers/mstar/scl/infinity/Makefile +@@ -0,0 +1,101 @@ ++MS_ARCH_NAME=infinity ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/infinity ++ ++# ++# Makefile for MStar HVSP drivers. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/inc ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/inc ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/msos ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip ++ ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/cmdq ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/cmdq ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/pnl/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/pnl ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/pnl/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/pnl ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/sclirq/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/sclirq ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/sclirq/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/sclirq ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/vip/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/vip ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/hvsp/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/hvsp ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/hvsp/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/hvsp ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/scldma/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/scldma ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/scldma/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/scldma ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/hal/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/hal/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/hal/include/sc ++ ++EXTRA_CFLAGS += -Werror ++ ++# specific options ++# ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX_KERNEL ++ ++ccflags-$(CONFIG_ARCH_CEDRIC) += -DC3_SIM ++ ++ ++obj-$(CONFIG_MS_SCL_INFINITY) += mdrv_scl.o ++ ++mdrv_scl-y := src/mxlib/msos/MsOS.o\ ++ src/mdrv_multiinst.o \ ++ mdrv_hvsp1_io.o\ ++ mdrv_hvsp2_io.o\ ++ mdrv_hvsp3_io.o\ ++ src/mdrv_hvsp.o\ ++ src/mxlib/hal/hvsp/halhvsp.o\ ++ src/mxlib/drv/hvsp/drvhvsp.o\ ++ mdrv_scldma1_io.o\ ++ mdrv_scldma2_io.o\ ++ mdrv_scldma3_io.o\ ++ mdrv_scldma4_io.o\ ++ src/mdrv_scldma.o\ ++ src/mxlib/hal/sclirq/halsclirq.o\ ++ src/mxlib/drv/sclirq/drvsclirq.o\ ++ src/mxlib/hal/scldma/halscldma.o\ ++ src/mxlib/drv/scldma/drvscldma.o\ ++ mdrv_pnl_io.o\ ++ src/mdrv_pnl.o\ ++ src/mxlib/hal/pnl/halpnl.o\ ++ src/mxlib/drv/pnl/drvpnl.o\ ++ mdrv_vip_io.o\ ++ src/mdrv_vip.o\ ++ src/mxlib/hal/vip/halvip.o\ ++ src/mxlib/drv/vip/drvvip.o\ ++ src/mxlib/drv/cmdq/drvCMDQ.o\ ++ src/mxlib/hal/cmdq/halCMDQ.o\ ++ src/mxlib/pq/drvPQ.o\ ++ src/mxlib/pq/drvPQ_Bin.o\ ++ src/mxlib/pq/hal/mhal_pq.o\ ++ src/mxlib/pq/hal/QualityMap_Main.o\ ++ ++ ++ ++ +diff --git a/drivers/mstar/scl/infinity/inc/mdrv_hvsp.h b/drivers/mstar/scl/infinity/inc/mdrv_hvsp.h +new file mode 100644 +index 00000000..e2475b1f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/inc/mdrv_hvsp.h +@@ -0,0 +1,273 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_HVSP_H ++#define _MDRV_HVSP_H ++ ++ ++ ++#define MDRV_HVSP_CROP_NUM 2 ++#define SCL_DELAY2FRAMEINDOUBLEBUFFERMode 0 ++#define DNRBufferMode 1 // depend on DNR Buffer ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MDRV_HVSP_ID_1, ++ E_MDRV_HVSP_ID_2, ++ E_MDRV_HVSP_ID_3, ++ E_MDRV_HVSP_ID_MAX, //I1 has 3 HVSP ++}EN_MDRV_HVSP_ID_TYPE; ++typedef enum ++{ ++ E_MDRV_HVSP_SRC_ISP, ///< input source: ISP ++ E_MDRV_HVSP_SRC_BT656, ///< input source: BT656 ++ E_MDRV_HVSP_SRC_DRAM, ///< input source: DRAM ++ E_MDRV_HVSP_SRC_HVSP, ///< input source: HVSP1 ++ E_MDRV_HVSP_SRC_PAT_TGEN, ///< input source: PATGEN ++ E_MDRV_HVSP_SRC_NUM, ///< The max number of input source ++}EN_MDRV_HVSP_SRC_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_COLOR_RGB, ///< color format:RGB ++ E_MDRV_HVSP_COLOR_YUV444, ///< color format:YUV444 ++ E_MDRV_HVSP_COLOR_YUV422, ///< color format:YUV422 ++ E_MDRV_HVSP_COLOR_YUV420, ///< color format:YUV420 ++ E_MDRV_HVSP_COLOR_NUM, ///< The max number of color format ++}EN_MDRV_HVSP_COLOR_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_DNR_R = 1, // only read ++ E_MDRV_HVSP_DNR_W = 2, // only write ++ E_MDRV_HVSP_DNR_RW = 3, // RW open ++ E_MDRV_HVSP_DNR_NUM, // not open ++}EN_MDRV_HVSP_DNR_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30, // FHD PT GEN ++ E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60, // HD PT gEN ++ E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60, // SD PT GEN ++ E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED, // random size ++ E_MDRV_HVSP_PAT_TGEN_TIMING_MAX, // 4type ++}EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_MISC_CMD_SET_REG = 0, ++ ++ E_MDRV_HVSP_MISC_CMD_MAX, // MISC set 1 type ++}EN_MDRV_HVSP_MISC_CMD_TYPE; ++ ++typedef enum ++{ ++ EN_MDRV_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ EN_MDRV_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_MDRV_HVSP_OSD_LOC_TYPE; ++ ++typedef enum ++{ ++ EN_MDRV_HVSP_MONITOR_CROPCHECK = 1, ///< crop ++ EN_MDRV_HVSP_MONITOR_DMA1FRMCHECK = 2, ///< dma1frm ++ EN_MDRV_HVSP_MONITOR_DMA1SNPCHECK = 3, ///< dma1frm ++ EN_MDRV_HVSP_MONITOR_DMA2FRMCHECK = 4, ///< dma1frm ++ EN_MDRV_HVSP_MONITOR_DMA3FRMCHECK = 5, ///< dma1frm ++}EN_MDRV_HVSP_MONITOR_TYPE; ++ ++typedef enum ++{ ++ EN_MDRV_HVSP_CALLPATGEN_STATIC = 0, ///< crop ++ EN_MDRV_HVSP_CALLPATGEN_DYNAMIC = 1, ///< dma1frm ++}EN_MDRV_HVSP_CALLPATGEN_TYPE; ++typedef enum ++{ ++ EN_MDRV_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_MDRV_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_MDRV_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_MDRV_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_MDRV_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_MDRV_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_MDRV_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_MDRV_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++}EN_MDRV_HVSP_FBMG_SET_TYPE; ++typedef struct ++{ ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop width size ++ unsigned short u16Height; ///< crop height size ++}ST_MDRV_HVSP_WINDOW_CONFIG; ++typedef struct ++{ ++ unsigned char bInterlace; ///< is interlace or progressive ++ unsigned short u16Htotal; ///< Htt ++ unsigned short u16Vtotal; ///< Vtt ++ unsigned short u16Vfrequency; ///< Vfreq ++}ST_MDRV_HVSPTIMING_CONFIG; ++ ++typedef struct ++{ ++ unsigned long u32Riubase; ++ unsigned long u32IRQNUM;//scl ++ unsigned long u32CMDQIRQNUM;//cmdq ++}ST_MDRV_HVSP_INIT_CONFIG; ++ ++ ++typedef struct ++{ ++ unsigned long u32IRQNum; ++ unsigned long u32CMDQIRQNum;//cmdq ++}ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG; ++ ++typedef struct ++{ ++ EN_MDRV_HVSP_DNR_TYPE enRW; ++ unsigned long u32PhyAddr; ++ unsigned short u16Width; ++ unsigned short u16Height; ++ unsigned long u32MemSize; ++}ST_MDRV_HVSP_IPM_CONFIG; ++ ++typedef struct ++{ ++ unsigned char bEn; ++ unsigned short u16X; ++ unsigned short u16Y; ++ unsigned short u16Width; ++ unsigned short u16Height; ++}ST_MDRV_HVSP_CROP_WINDOW_CONFIG; ++typedef struct ++{ ++ void* idclk; ++ void* fclk1; ++ void* fclk2; ++ void* odclk; ++}ST_MDRV_HVSP_CLK_CONFIG; ++ ++typedef struct ++{ ++ unsigned short u16Src_Width; ++ unsigned short u16Src_Height; ++ unsigned short u16Dsp_Width; ++ unsigned short u16Dsp_Height; ++ ST_MDRV_HVSP_CROP_WINDOW_CONFIG stCropWin; ++ ST_MDRV_HVSP_CLK_CONFIG *stclk; ///< clk framework ++}ST_MDRV_HVSP_SCALING_CONFIG; ++ ++typedef struct ++{ ++ unsigned char bOSDEn; ///< OSD en ++ unsigned char bOSDBypass; ///< OSD en ++ unsigned char bWTMBypass; ///< OSD en ++}ST_MDRV_HVSP_OSD_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ EN_MDRV_HVSP_OSD_LOC_TYPE enOSD_loc; ///< OSD locate ++ ST_MDRV_HVSP_OSD_ONOFF_CONFIG stOsdOnOff; ++}ST_MDRV_HVSP_OSD_CONFIG; ++ ++typedef struct ++{ ++ EN_MDRV_HVSP_SRC_TYPE enSrcType; ++ EN_MDRV_HVSP_COLOR_TYPE enColor; ++ ST_MDRV_HVSP_WINDOW_CONFIG stCaptureWin; ++ ST_MDRV_HVSPTIMING_CONFIG stTimingCfg; ++ ST_MDRV_HVSP_CLK_CONFIG *stclk; ++}ST_MDRV_HVSP_INPUT_CONFIG; ++typedef struct ++{ ++ unsigned char bCropEn; ///< post crop En ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop frame width ++ unsigned short u16Height; ///< crop frame height ++ unsigned char bFmCntEn; ///< Is use CMDQ to set ++ unsigned char u8FmCnt; ///< when frame count ++ ST_MDRV_HVSP_CLK_CONFIG *stclk; /// ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "mdrv_hvsp_io_st.h" ++#include "mdrv_hvsp_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++#define MDRV_MS_HVSP_DEVICE_COUNT 1 ++#define MDRV_MS_HVSP_NAME "mhvsp1" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_HVSP "mhvsp1" ++#define MDRV_MAJOR_HVSP 0xea ++#define MDRV_MINOR_HVSP 0x01 ++ ++#define CMD_PARSING(x) (x==IOCTL_HVSP_SET_IN_CONFIG ? "IOCTL_HVSP_SET_IN_CONFIG" : \ ++ x==IOCTL_HVSP_SET_OUT_CONFIG ? "IOCTL_HVSP_SET_OUT_CONFIG" : \ ++ x==IOCTL_HVSP_SET_SCALING_CONFIG ? "IOCTL_HVSP_SET_SCALING_CONFIG" : \ ++ x==IOCTL_HVSP_REQ_MEM_CONFIG ? "IOCTL_HVSP_REQ_MEM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_MISC_CONFIG ? "IOCTL_HVSP_SET_MISC_CONFIG" : \ ++ x==IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ? "IOCTL_HVSP_GET_PRIVATE_ID_CONFIG" : \ ++ "UNKNOWN") ++ ++#define FHDWidth 1920 ++#define FHDHeight 1080 ++ ++//------------------------------------------------------------------------------------------------- ++ ++#define _ms_hvsp1_mem_bus_to_miu(x) (x-0x2000000) ++#define CMDQIRQ_ID ++#define SCLIRQ_ID ++//------------------------------------------------------------------------------------------------- ++ ++int mdrv_ms_hvsp1_open(struct inode *inode, struct file *filp); ++int mdrv_ms_hvsp1_release(struct inode *inode, struct file *filp); ++long mdrv_ms_hvsp1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_hvsp1_probe(struct platform_device *pdev); ++static int mdrv_ms_hvsp1_remove(struct platform_device *pdev); ++static int mdrv_ms_hvsp1_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_hvsp1_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_hvsp1_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//------------------------------------------------------------------------------------------------- ++ ++dma_addr_t sg_hvsp1_dnr_bus_addr = 0; ++static u_long sg_hvsp1_dnr_size = 1920*1080*2*2 ; ++static void *sg_hvsp1_dnr_vir_addr = NULL; ++const static char* KEY_DMEM_SCL_DNR="SCL_DNR"; ++unsigned int SCL_IRQ_ID = 0; //INT_IRQ_AU_SYSTEM; ++unsigned int CMDQ_IRQ_ID = 0; //INT_IRQ_AU_SYSTEM; ++unsigned int gu8DNRBufferReadyNum=0;//extern ++unsigned char gbdbgmessage[EN_DBGMG_NUM_CONFIG];//extern ++#if CONFIG_OF ++unsigned int gbProbeAlready = 0;//extern ++#endif ++static u_long sg_hvsp1_release_dnr_size; ++static void *sg_hvsp1_release_dnr_vir_addr = NULL; ++dma_addr_t sg_hvsp1_release_dnr_bus_addr; ++int gVSyncCount=0; ++int gMonitorErrCount = 0; ++ ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ unsigned char flag; ++ struct task_struct *pThread; ++}ST_IOCTL_HVSP_THREAD_CONFIG; ++ST_IOCTL_HVSP_THREAD_CONFIG gstThCfg={0,NULL}; ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_HVSP_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_HVSP; ++ ++static ST_DEV_HVSP _dev_ms_hvsp1 = ++{ ++ .s32Major = MDRV_MAJOR_HVSP, ++ .s32Minor = MDRV_MINOR_HVSP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_HVSP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_hvsp1_open, ++ .release = mdrv_ms_hvsp1_release, ++ .unlocked_ioctl = mdrv_ms_hvsp1_ioctl, ++ .poll = mdrv_ms_hvsp1_poll, ++ }, ++}; ++ ++static struct class * m_hvsp1_class = NULL; ++static char * hvsp1_classname = "m_hvsp1_class"; ++ ++ ++static const struct of_device_id ms_hvsp1_of_match_table[] = ++{ ++ { .compatible = "mstar,hvsp1" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_hvsp1_driver = ++{ ++ .probe = mdrv_ms_hvsp1_probe, ++ .remove = mdrv_ms_hvsp1_remove, ++ .suspend = mdrv_ms_hvsp1_suspend, ++ .resume = mdrv_ms_hvsp1_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_HVSP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_hvsp1_of_match_table), ++ }, ++}; ++ ++static u64 ms_hvsp1_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_hvsp1_device = ++{ ++ .name = "mhvsp1", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_hvsp1_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// internal function ++//------------------------------------------------------------------------------------------------- ++void _mdrv_hvsp1_SetInputTestPatternAndTgen(unsigned short Width,unsigned short Height) ++{ ++ ST_MDRV_HVSP_MISC_CONFIG stHvspMiscCfg; ++ unsigned char u8InputTgenSetBuf[] = ++ { ++ 0x18, 0x12, 0x80, 0x07, 0xFF,// 4 ++ 0x18, 0x12, 0x81, 0x80, 0xFF,// 9 ++ 0x18, 0x12, 0x82, 0x30, 0xFF, ++ 0x18, 0x12, 0x83, 0x30, 0xFF, ++ 0x18, 0x12, 0x84, 0x10, 0xFF, ++ 0x18, 0x12, 0x85, 0x10, 0xFF, ++ 0x18, 0x12, 0x86, 0x02, 0xFF, ++ 0x18, 0x12, 0x87, 0x00, 0xFF, ++ 0x18, 0x12, 0x88, 0x21, 0xFF, ++ 0x18, 0x12, 0x89, 0x0C, 0xFF, ++ 0x18, 0x12, 0xE0, 0x01, 0xFF, ++ 0x18, 0x12, 0xE1, 0x00, 0xFF, ++ 0x18, 0x12, 0xE2, 0x01, 0xFF, ++ 0x18, 0x12, 0xE3, 0x00, 0xFF, ++ 0x18, 0x12, 0xE4, 0x03, 0xFF, ++ 0x18, 0x12, 0xE5, 0x00, 0xFF, ++ 0x18, 0x12, 0xE6, 0x05, 0xFF, ++ 0x18, 0x12, 0xE7, 0x00, 0xFF, ++ 0x18, 0x12, 0xE8, 0xE4, 0xFF,//94 ++ 0x18, 0x12, 0xE9, 0x01, 0xFF,//99 ++ 0x18, 0x12, 0xEA, 0x05, 0xFF, ++ 0x18, 0x12, 0xEB, 0x00, 0xFF, ++ 0x18, 0x12, 0xEC, 0xE4, 0xFF,//114 ++ 0x18, 0x12, 0xED, 0x01, 0xFF,//119 ++ 0x18, 0x12, 0xEE, 0x72, 0xFF,//124 ++ 0x18, 0x12, 0xEF, 0x02, 0xFF,//129 ++ 0x18, 0x12, 0xF2, 0x04, 0xFF, ++ 0x18, 0x12, 0xF3, 0x00, 0xFF, ++ 0x18, 0x12, 0xF4, 0x7F, 0xFF, ++ 0x18, 0x12, 0xF5, 0x00, 0xFF, ++ 0x18, 0x12, 0xF6, 0xA8, 0xFF, ++ 0x18, 0x12, 0xF7, 0x00, 0xFF, ++ 0x18, 0x12, 0xF8, 0xA7, 0xFF,//164 ++ 0x18, 0x12, 0xF9, 0x01, 0xFF,//169 ++ 0x18, 0x12, 0xFA, 0xA8, 0xFF, ++ 0x18, 0x12, 0xFB, 0x00, 0xFF, ++ 0x18, 0x12, 0xFC, 0xA7, 0xFF,//184 ++ 0x18, 0x12, 0xFD, 0x01, 0xFF,//189 ++ 0x18, 0x12, 0xFE, 0x1F, 0xFF,//194 ++ 0x18, 0x12, 0xFF, 0x04, 0xFF,//199 ++ 0x21, 0x12, 0xE0, 0x01, 0x01,//vip ++ 0x1E, 0x12, 0x70, 0x00, 0xFF, ++ 0x1E, 0x12, 0x71, 0x04, 0x07, ++ 0x1E, 0x12, 0x72, 0x00, 0xFF, ++ 0x1E, 0x12, 0x73, 0x00, 0x01, ++ 0x1E, 0x12, 0x74, 0x00, 0xFF, ++ 0x1E, 0x12, 0x75, 0x04, 0x07, ++ 0x1E, 0x12, 0x76, 0x00, 0xFF, ++ 0x1E, 0x12, 0x77, 0x00, 0x01, ++ 0x1E, 0x12, 0x78, 0x00, 0xFF, ++ 0x1E, 0x12, 0x79, 0x04, 0x07, ++ 0x1E, 0x12, 0x7A, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7B, 0x00, 0x01, ++ 0x1E, 0x12, 0x7C, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7D, 0x04, 0x07, ++ 0x1E, 0x12, 0x7E, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7F, 0x00, 0x01, ++ }; ++ ++ // Input tgen setting ++ u8InputTgenSetBuf[93] = (unsigned char)((0x4+Height)&0x00FF); ++ u8InputTgenSetBuf[98] = (unsigned char)(((0x4+Height)&0xFF00)>>8); ++ u8InputTgenSetBuf[113] = (unsigned char)((0x4+Height)&0x00FF); ++ u8InputTgenSetBuf[118] = (unsigned char)(((0x4+Height)&0xFF00)>>8); ++ u8InputTgenSetBuf[123] = 0xFF; ++ u8InputTgenSetBuf[128] = 0x08; ++ u8InputTgenSetBuf[163] = (unsigned char)((0xA7+Width)&0x00FF); ++ u8InputTgenSetBuf[168] = (unsigned char)(((0xA7+Width)&0xFF00)>>8); ++ u8InputTgenSetBuf[183] = (unsigned char)((0xA7+Width)&0x00FF); ++ u8InputTgenSetBuf[188] = (unsigned char)(((0xA7+Width)&0xFF00)>>8); ++ u8InputTgenSetBuf[193] = 0xFF; ++ u8InputTgenSetBuf[198] = 0x08; ++ ++ stHvspMiscCfg.u8Cmd = 0; ++ stHvspMiscCfg.u32Size = sizeof(u8InputTgenSetBuf); ++ stHvspMiscCfg.u32Addr = (unsigned long)u8InputTgenSetBuf; ++ MDrv_HVSP_SetMiscConfigForKernel(&stHvspMiscCfg); ++} ++ ++void _mdrv_hvsp1_OpenInputTestPatternAndTgen(void) ++{ ++ ST_MDRV_HVSP_SCINFORM_CONFIG stCfg; ++ MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_1,&stCfg); ++ if(stCfg.u16crop2inWidth && stCfg.u16crop2inHeight) ++ { ++ MDrv_HVSP_SetPatTgenStatus(TRUE); ++ _mdrv_hvsp1_SetInputTestPatternAndTgen(stCfg.u16crop2inWidth,stCfg.u16crop2inHeight); ++ } ++ else ++ { ++ MDrv_HVSP_SetPatTgenStatus(TRUE); ++ _mdrv_hvsp1_SetInputTestPatternAndTgen(FHDWidth,FHDHeight); ++ SCL_ERR( "[HVSP1]Open Input Test Pattern And Tgen Default FHD\n"); ++ } ++} ++ ++void _mdrv_hvsp1_OpenTestPatternByISPTgen(unsigned char bDynamic) ++{ ++ ST_MDRV_HVSP_MISC_CONFIG stHvspMiscCfg; ++ unsigned char input_tgen_buf[] = ++ { ++ 0x18, 0x12, 0x80, 0x03, 0xFF,// 4 ++ 0x18, 0x12, 0x81, 0x80, 0xFF,// 9 ++ 0x18, 0x12, 0x82, 0x30, 0xFF, ++ 0x18, 0x12, 0x83, 0x30, 0xFF, ++ 0x18, 0x12, 0x84, 0x10, 0xFF, ++ 0x18, 0x12, 0x85, 0x10, 0xFF, ++ 0x18, 0x12, 0x86, 0x02, 0xFF, ++ 0x18, 0x12, 0x87, 0x00, 0xFF, ++ 0x18, 0x12, 0x88, 0x21, 0xFF, ++ 0x18, 0x12, 0x89, 0x0C, 0xFF, ++ 0x21, 0x12, 0xE0, 0x01, 0x01,//vip ++ 0x1E, 0x12, 0x70, 0x00, 0xFF, ++ 0x1E, 0x12, 0x71, 0x04, 0x07, ++ 0x1E, 0x12, 0x72, 0x00, 0xFF, ++ 0x1E, 0x12, 0x73, 0x00, 0x01, ++ 0x1E, 0x12, 0x74, 0x00, 0xFF, ++ 0x1E, 0x12, 0x75, 0x04, 0x07, ++ 0x1E, 0x12, 0x76, 0x00, 0xFF, ++ 0x1E, 0x12, 0x77, 0x00, 0x01, ++ 0x1E, 0x12, 0x78, 0x00, 0xFF, ++ 0x1E, 0x12, 0x79, 0x04, 0x07, ++ 0x1E, 0x12, 0x7A, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7B, 0x00, 0x01, ++ 0x1E, 0x12, 0x7C, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7D, 0x04, 0x07, ++ 0x1E, 0x12, 0x7E, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7F, 0x00, 0x01, ++ }; ++ if(bDynamic) ++ { ++ input_tgen_buf[3] = (unsigned char)0x7; ++ } ++ stHvspMiscCfg.u8Cmd = 0; ++ stHvspMiscCfg.u32Size = sizeof(input_tgen_buf); ++ stHvspMiscCfg.u32Addr = (unsigned long)input_tgen_buf; ++ MDrv_HVSP_SetMiscConfigForKernel(&stHvspMiscCfg); ++ ++} ++void _mdrv_hvsp1_CloseTestPatternByISPTgen(void) ++{ ++ ST_MDRV_HVSP_MISC_CONFIG stHvspMiscCfg; ++ unsigned char input_tgen_buf[] = ++ { ++ 0x18, 0x12, 0x80, 0x00, 0xFF,// 4 ++ 0x18, 0x12, 0x81, 0x00, 0xFF,// 9 ++ 0x18, 0x12, 0x86, 0x02, 0xFF, ++ 0x18, 0x12, 0x88, 0x20, 0xFF, ++ 0x18, 0x12, 0x89, 0x0C, 0xFF, ++ 0x18, 0x12, 0xE0, 0x00, 0xFF, ++ 0x18, 0x12, 0xE1, 0x00, 0xFF, ++ 0x21, 0x12, 0xE0, 0x00, 0x01, ++ }; ++ stHvspMiscCfg.u8Cmd = 0; ++ stHvspMiscCfg.u32Size = sizeof(input_tgen_buf); ++ stHvspMiscCfg.u32Addr = (unsigned long)input_tgen_buf; ++ MDrv_HVSP_SetPatTgenStatus(FALSE); ++ MDrv_HVSP_SetMiscConfigForKernel(&stHvspMiscCfg); ++ ++} ++ ++unsigned long _mdrv_hvsp1_HWMonitor(unsigned char u8flag) ++{ ++ return MDrv_HVSP_HWMonitor(u8flag); ++} ++unsigned char _mdrv_hvsp1_InputVSyncMonitor(void) ++{ ++ if(MDrv_HVSP_InputVSyncMonitor()) ++ { ++ return 1; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++static ssize_t ptgen_call_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]ptgen_call_store OK %d\n",(int)*str); ++ _mdrv_hvsp1_OpenTestPatternByISPTgen(EN_MDRV_HVSP_CALLPATGEN_STATIC); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]ptgen_call_close %d\n",(int)*str); ++ _mdrv_hvsp1_CloseTestPatternByISPTgen(); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[HVSP1]dynamic ptgen OK %d\n",(int)*str); ++ _mdrv_hvsp1_OpenTestPatternByISPTgen(EN_MDRV_HVSP_CALLPATGEN_DYNAMIC); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[HVSP1]ptgen_call SCL INPUT Tgen %d\n",(int)*str); ++ _mdrv_hvsp1_OpenInputTestPatternAndTgen(); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t ptgen_call_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf,"0:close\n1:open static ptgen\n2:open dynamic ptgen\n3:open scl time gen pattern"); ++} ++ ++static DEVICE_ATTR(ptgen,0644, ptgen_call_show, ptgen_call_store); ++ ++static int ms_hvsp1_MonitorThread(void *arg) ++{ ++ unsigned long u32Stime = 0,u32difftime = 0; ++ u32Stime = MsOS_GetSystemTime(); ++ _mdrv_hvsp1_HWMonitor(gstThCfg.flag); ++ while(gstThCfg.flag) ++ { ++ if(_mdrv_hvsp1_InputVSyncMonitor()) ++ { ++ gVSyncCount++; ++ gMonitorErrCount += _mdrv_hvsp1_HWMonitor(gstThCfg.flag); ++ u32difftime = MsOS_Timer_DiffTimeFromNow(u32Stime); ++ } ++ } ++ SCL_ERR( "[HVSP1]vsync count:%d MonitorErrCount:%d\n average:%hd (ms/frm)\n" ++ ,gVSyncCount,gMonitorErrCount,(short)(u32difftime/gVSyncCount)); ++ kthread_stop(gstThCfg.pThread); ++ gstThCfg.pThread = NULL; ++ return 0; ++} ++static ssize_t monitorHW_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_monitorHWShow(buf,gVSyncCount,gMonitorErrCount); ++} ++void _mdrv_hvsp1_CreateMonitorTask(unsigned char u8MonitorFlag) ++{ ++ const char *pName = {"HVSP_THREAD"}; ++ gstThCfg.flag = u8MonitorFlag; ++ gVSyncCount = 0; ++ gMonitorErrCount = 0; ++ gstThCfg.pThread = kthread_create(ms_hvsp1_MonitorThread,(void *)&gVSyncCount,pName); ++ if (IS_ERR(gstThCfg.pThread)) ++ { ++ gstThCfg.pThread = NULL; ++ SCL_ERR( "[HVSP1]Fail:creat thread\n"); ++ } ++ else ++ { ++ wake_up_process(gstThCfg.pThread ); ++ } ++} ++static ssize_t monitorHW_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >crop monitor ++ { ++ _mdrv_hvsp1_CreateMonitorTask(EN_MDRV_HVSP_MONITOR_CROPCHECK); ++ } ++ else if((int)*str == 50) //input 2 echo 2 >dma monitor ++ { ++ _mdrv_hvsp1_CreateMonitorTask(EN_MDRV_HVSP_MONITOR_DMA1FRMCHECK); ++ } ++ else if((int)*str == 51) //input 2 echo 3 >dma monitor ++ { ++ _mdrv_hvsp1_CreateMonitorTask(EN_MDRV_HVSP_MONITOR_DMA1SNPCHECK); ++ } ++ else if((int)*str == 52) //input 2 echo 4 >dma monitor ++ { ++ _mdrv_hvsp1_CreateMonitorTask(EN_MDRV_HVSP_MONITOR_DMA2FRMCHECK); ++ } ++ else if((int)*str == 53) //input 2 echo 5 >dma monitor ++ { ++ _mdrv_hvsp1_CreateMonitorTask(EN_MDRV_HVSP_MONITOR_DMA3FRMCHECK); ++ } ++ else if((int)*str == 48) ++ { ++ gstThCfg.flag =0 ; ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(monitorHW,0644, monitorHW_show, monitorHW_store); ++ ++static ssize_t check_clk_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_HVSP_CLK_CONFIG *stclk = NULL; ++ stclk = &(_dev_ms_hvsp1.stclk); ++ return MDrv_HVSP_ClkFrameworkShow(buf,stclk); ++} ++ ++static ssize_t check_clk_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 ++ { ++ SCL_ERR( "[CLK]open force mode %d\n",(int)*str); ++ MDrv_HVSP_SetCLKForcemode(1); ++ } ++ else if((int)*str == 48) //input 0 ++ { ++ SCL_ERR( "[CLK]close force mode %d\n",(int)*str); ++ MDrv_HVSP_SetCLKForcemode(0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[CLK]fclk1 max %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk1,0); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[CLK]fclk1 med %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk1,1); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ SCL_ERR( "[CLK]fclk1 open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk1,1); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ SCL_ERR( "[CLK]fclk1 close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk1,0); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ SCL_ERR( "[CLK]fclk2 max %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk2,0); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ SCL_ERR( "[CLK]fclk2 med %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk2,1); ++ } ++ else if((int)*str == 56) //input 8 ++ { ++ SCL_ERR( "[CLK]fclk2 open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk2,1); ++ } ++ else if((int)*str == 57) //input 9 ++ { ++ SCL_ERR( "[CLK]fclk2 close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk2,0); ++ } ++ else if((int)*str == 58) //input : ++ { ++ SCL_ERR( "[CLK]idclk ISP %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.idclk,0x10); ++ } ++ else if((int)*str == 68) //input D ++ { ++ SCL_ERR( "[CLK]idclk BT656 %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.idclk,0x21); ++ } ++ else if((int)*str == 66) //input B ++ { ++ SCL_ERR( "[CLK]idclk Open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.idclk,1); ++ } ++ else if((int)*str == 61) //input = ++ { ++ SCL_ERR( "[CLK]idclk Close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.idclk,0); ++ } ++ else if((int)*str == 67) //input C ++ { ++ SCL_ERR( "[CLK]odclk MAX %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.odclk,0); ++ } ++ else if((int)*str == 63) //input ? ++ { ++ SCL_ERR( "[CLK]odclk LPLL %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.odclk,3); ++ } ++ else if((int)*str == 64) //input @ ++ { ++ SCL_ERR( "[CLK]odclk open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.odclk,1); ++ } ++ else if((int)*str == 65) //input A ++ { ++ SCL_ERR( "[CLK]odclk close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.odclk,0); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++ ++static DEVICE_ATTR(clk,0644, check_clk_show, check_clk_store); ++static ssize_t check_osd_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ MDrv_HVSP_OsdStore(buf,E_MDRV_HVSP_ID_1); ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t check_osd_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_OsdShow(buf); ++} ++static DEVICE_ATTR(osd,0644, check_osd_show, check_osd_store); ++static ssize_t check_fbmg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG stFbMgCfg; ++ const char *str = buf; ++ if(NULL!=buf) ++ { ++ //if(!) ++ if((int)*str == 49) //input 1 ++ { ++ SCL_ERR( "[OSD]open OSD %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_LDCPATH_ON; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[OSD]Set OSD before %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_LDCPATH_OFF; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[OSD]Set OSD After %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_DNR_Read_ON; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ SCL_ERR( "[OSD]Set OSD Bypass %d\n",(int)*str); ++ stFbMgCfg.enSet= EN_IOCTL_HVSP_FBMG_SET_DNR_Read_OFF; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ SCL_ERR( "[OSD]Set OSD Bypass Off %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_DNR_Write_ON; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_DNR_Write_OFF; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass Off %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_1; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 56) //input 8 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass Off %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_DNR_BUFFER_2; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ else if((int)*str == 57) //input 9 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass Off %d\n",(int)*str); ++ stFbMgCfg.enSet = EN_IOCTL_HVSP_FBMG_SET_UNLOCK; ++ MDrv_HVSP_SetFbManageConfig(stFbMgCfg.enSet); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t check_fbmg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_FBMGShow(buf); ++} ++ ++static DEVICE_ATTR(fbmg,0644, check_fbmg_show, check_fbmg_store); ++ ++ ++static ssize_t check_proc_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_ProcShow(buf); ++} ++static DEVICE_ATTR(proc,0444, check_proc_show, NULL); ++ ++static ssize_t check_dbgmg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_DbgmgFlagShow(buf); ++} ++static unsigned char _mdrv_hvsp1_Changebuf2hex(int u32num) ++{ ++ unsigned char u8level; ++ if(u32num==10) ++ { ++ u8level = 1; ++ } ++ else if(u32num==48) ++ { ++ u8level = 0; ++ } ++ else if(u32num==49) ++ { ++ u8level = 0x1; ++ } ++ else if(u32num==50) ++ { ++ u8level = 0x2; ++ } ++ else if(u32num==51) ++ { ++ u8level = 0x3; ++ } ++ else if(u32num==52) ++ { ++ u8level = 0x4; ++ } ++ else if(u32num==53) ++ { ++ u8level = 0x5; ++ } ++ else if(u32num==54) ++ { ++ u8level = 0x6; ++ } ++ else if(u32num==55) ++ { ++ u8level = 0x7; ++ } ++ else if(u32num==56) ++ { ++ u8level = 0x8; ++ } ++ else if(u32num==57) ++ { ++ u8level = 0x9; ++ } ++ else if(u32num==65) ++ { ++ u8level = 0xa; ++ } ++ else if(u32num==66) ++ { ++ u8level = 0xb; ++ } ++ else if(u32num==67) ++ { ++ u8level = 0xc; ++ } ++ else if(u32num==68) ++ { ++ u8level = 0xd; ++ } ++ else if(u32num==69) ++ { ++ u8level = 0xe; ++ } ++ else if(u32num==70) ++ { ++ u8level = 0xf; ++ } ++ else if(u32num==97) ++ { ++ u8level = 0xa; ++ } ++ else if(u32num==98) ++ { ++ u8level = 0xb; ++ } ++ else if(u32num==99) ++ { ++ u8level = 0xc; ++ } ++ else if(u32num==100) ++ { ++ u8level = 0xd; ++ } ++ else if(u32num==101) ++ { ++ u8level = 0xe; ++ } ++ else if(u32num==102) ++ { ++ u8level = 0xf; ++ } ++ return u8level; ++} ++ ++static ssize_t check_dbgmg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ unsigned char u8level; ++ SCL_ERR( "[HVSP1]check_dbgmg_store OK %d\n",(int)*str); ++ SCL_ERR( "[HVSP1]check_dbgmg_store level %d\n",(int)*(str+1)); ++ SCL_ERR( "[HVSP1]check_dbgmg_store level2 %d\n",(int)*(str+2)); ++ if(((int)*(str+2))>=48)//LF :line feed ++ { ++ u8level = _mdrv_hvsp1_Changebuf2hex((int)*(str+2)); ++ u8level |= (_mdrv_hvsp1_Changebuf2hex((int)*(str+1))<<4); ++ } ++ else ++ { ++ u8level = _mdrv_hvsp1_Changebuf2hex((int)*(str+1)); ++ } ++ ++ if((int)*str == 48) //input 1 echo 0 > ++ { ++ Reset_DBGMG_FLAG(); ++ } ++ else if((int)*str == 49) //input 1 echo 1 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_MDRV_CONFIG,u8level); ++ } ++ else if((int)*str == 50) //input 1 echo 2 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_IOCTL_CONFIG,u8level); ++ } ++ else if((int)*str == 51) //input 1 echo 3 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_HVSP_CONFIG,u8level); ++ } ++ else if((int)*str == 52) //input 1 echo 4 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_SCLDMA_CONFIG,u8level); ++ } ++ else if((int)*str == 53) //input 1 echo 5 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_PNL_CONFIG,u8level); ++ } ++ else if((int)*str == 54) //input 1 echo 6 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_VIP_CONFIG,u8level); ++ } ++ else if((int)*str == 55) //input 1 echo 7 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVPQ_CONFIG,u8level); ++ } ++ else if((int)*str == 56) //input 1 echo 8 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_INST_ENTRY_CONFIG,u8level); ++ } ++ else if((int)*str == 57) //input 1 echo 9 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_INST_LOCK_CONFIG,u8level); ++ } ++ else if((int)*str == 65) //input 1 echo A > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_INST_FUNC_CONFIG,u8level); ++ } ++ else if((int)*str == 66) //input 1 echo B > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVHVSP_CONFIG,u8level); ++ } ++ else if((int)*str == 67) //input 1 echo C > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVSCLDMA_CONFIG,u8level); ++ } ++ else if((int)*str == 68) //input 1 echo D > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVSCLIRQ_CONFIG,u8level); ++ } ++ else if((int)*str == 69) //input 1 echo E > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVCMDQ_CONFIG,u8level); ++ } ++ else if((int)*str == 70) //input 1 echo F > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVVIP_CONFIG,u8level); ++ } ++ else if((int)*str == 71) //input 1 echo G > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_PRIORITY_CONFIG,1); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(dbgmg,0644, check_dbgmg_show, check_dbgmg_store); ++ ++static void* _ms_hvsp1_AllocDmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ if(0 != msys_request_dmem(&dmem)) ++ { ++ return NULL; ++ } ++ else ++ { ++ gu8DNRBufferReadyNum = 1 + (SCL_DELAY2FRAMEINDOUBLEBUFFERMode); ++ sg_hvsp1_release_dnr_size = sg_hvsp1_dnr_size; ++ sg_hvsp1_release_dnr_vir_addr = sg_hvsp1_dnr_vir_addr; ++ sg_hvsp1_release_dnr_bus_addr = sg_hvsp1_dnr_bus_addr; ++ } ++ *addr = dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void _ms_hvsp1_FreeDmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ dmem.kvirt = (unsigned long long)((uintptr_t)virt); ++ dmem.phys = (unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++ ++static int _ms_hvsp1_mem_allocate(void) ++{ ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, "[HVSP1] allocate memory\n"); ++ ++ if (!(sg_hvsp1_dnr_vir_addr = _ms_hvsp1_AllocDmem(KEY_DMEM_SCL_DNR, ++ PAGE_ALIGN(sg_hvsp1_dnr_size), ++ &sg_hvsp1_dnr_bus_addr))) ++ { ++ SCL_ERR( "%s: unable to allocate screen memory\n", __FUNCTION__); ++ return 0; ++ } ++ SCL_ERR( "[HVSP1]: DNR: Phy:%x Vir:%x\n", sg_hvsp1_dnr_bus_addr, (u32)sg_hvsp1_dnr_vir_addr); ++ ++ ++ return 1; ++} ++ ++static void _ms_hvsp1_mem_free(void) ++{ ++ if(sg_hvsp1_dnr_vir_addr != 0) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, "[HVSP1] mem free\n"); ++ _ms_hvsp1_FreeDmem(KEY_DMEM_SCL_DNR, ++ PAGE_ALIGN(sg_hvsp1_dnr_size), ++ sg_hvsp1_dnr_vir_addr, ++ sg_hvsp1_dnr_bus_addr); ++ ++ sg_hvsp1_dnr_vir_addr = 0; ++ sg_hvsp1_dnr_bus_addr = 0; ++ gu8DNRBufferReadyNum = 0; ++ } ++} ++static int _ms_hvsp1_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ST_MDRV_HVSP_VERSIONCHK_CONFIG _mdrv_ms_hvsp1_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_hvsp1_io_version_check(ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP1] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[HVSP1] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[HVSP1] Size(%d) \n",stVersion.u32StructSize ); ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP1] No Header !!! \n"); ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++MS_BOOL _mdrv_hvsp1_CheckModifyMemSize(ST_IOCTL_HVSP_REQ_MEM_CONFIG *stReqMemCfg) ++{ ++ if( (stReqMemCfg->u16Vsize & (15)) || (stReqMemCfg->u16Pitch & (15))) ++ { ++ SCL_ERR( ++ "[HVSP1] Size must be align 16, Vsize=%d, Pitch=%d\n",stReqMemCfg->u16Vsize, stReqMemCfg->u16Pitch); ++ if((stReqMemCfg->u16Pitch & (15))&&(stReqMemCfg->u16Vsize & (15))) ++ { ++ stReqMemCfg->u32MemSize = (((stReqMemCfg->u16Vsize/16)+1)*16) * ((stReqMemCfg->u16Pitch/16)+1)*16 * 4; ++ } ++ else if(stReqMemCfg->u16Pitch & (15)) ++ { ++ stReqMemCfg->u32MemSize = (stReqMemCfg->u16Vsize) * ((stReqMemCfg->u16Pitch/16)+1)*16 * 4; ++ } ++ else if(stReqMemCfg->u16Vsize & (15)) ++ { ++ stReqMemCfg->u32MemSize = (((stReqMemCfg->u16Vsize/16)+1)*16) * stReqMemCfg->u16Pitch * 4; ++ } ++ } ++ else ++ { ++ stReqMemCfg->u32MemSize = (stReqMemCfg->u16Vsize) *(stReqMemCfg->u16Pitch) *4; ++ } ++ if(Mdrv_HVSP_GetDNRBufferInformation()== 1) ++ { ++ SCL_ERR( ++ "[HVSP1] Buffer is single, Vsize=%d, Pitch=%d\n",stReqMemCfg->u16Vsize, stReqMemCfg->u16Pitch); ++ stReqMemCfg->u32MemSize = stReqMemCfg->u32MemSize /2 ; ++ } ++ sg_hvsp1_dnr_size = stReqMemCfg->u32MemSize; ++ if(Mdrv_HVSP_GetDNRBufferInformation()== 1) ++ { ++ if((unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 2) > stReqMemCfg->u32MemSize) ++ { ++ SCL_ERR( "[HVSP1] Memory size is too small, Vsize*Pitch*2=%lx, MemSize=%lx\n", ++ (unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 2), stReqMemCfg->u32MemSize); ++ return -EFAULT; ++ } ++ } ++ else if((unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 4) > stReqMemCfg->u32MemSize) ++ { ++ SCL_ERR( "[HVSP1] Memory size is too small, Vsize*Pitch*4=%lx, MemSize=%lx\n", ++ (unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 4), stReqMemCfg->u32MemSize); ++ return -EFAULT; ++ } ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, ++ "[HVSP1], Vsize=%d, Pitch=%d, Size=%lx\n", stReqMemCfg->u16Vsize, stReqMemCfg->u16Pitch,stReqMemCfg->u32MemSize); ++ return 0; ++} ++ ++void _mdrv_hvsp1_DNRBufferMemoryAllocate(void) ++{ ++ if(gu8DNRBufferReadyNum == 0) ++ { ++ _ms_hvsp1_mem_allocate(); ++ MDrv_HVSP_SetMemoryAllocateReady(gu8DNRBufferReadyNum); ++ } ++ else if(gu8DNRBufferReadyNum != 0 && sg_hvsp1_dnr_size > sg_hvsp1_release_dnr_size) ++ { ++ _ms_hvsp1_mem_free(); ++ gu8DNRBufferReadyNum = 0; ++ _ms_hvsp1_mem_allocate(); ++ MDrv_HVSP_SetMemoryAllocateReady((gu8DNRBufferReadyNum > 0) ? 1 :0); ++ } ++} ++ST_MDRV_HVSP_IPM_CONFIG _mdrv_hvsp1_FillIPMStructForDriver(ST_IOCTL_HVSP_REQ_MEM_CONFIG stReqMemCfg) ++{ ++ ST_MDRV_HVSP_IPM_CONFIG stIPMCfg; ++ stIPMCfg.u16Height = stReqMemCfg.u16Vsize; ++ stIPMCfg.u16Width = stReqMemCfg.u16Pitch; ++ stIPMCfg.u32MemSize = stReqMemCfg.u32MemSize; ++ if(gu8DNRBufferReadyNum) ++ { ++ stIPMCfg.enRW = E_IOCTL_HVSP_DNR_W; ++ sg_hvsp1_dnr_size = stReqMemCfg.u32MemSize; ++ } ++ else ++ { ++ stIPMCfg.enRW = E_IOCTL_HVSP_DNR_NUM; ++ sg_hvsp1_dnr_size = stReqMemCfg.u32MemSize; ++ } ++ stIPMCfg.u32PhyAddr = Chip_Phys_to_MIU(sg_hvsp1_dnr_bus_addr); ++ return stIPMCfg; ++} ++ ++ ++int _mdrv_ms_hvsp1_io_set_input_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_INPUT_CONFIG stInCfg; ++ ST_IOCTL_HVSP_INPUT_CONFIG stIOInCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_INPUT_CONFIG), ++ (((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOInCfg, (ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_INPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stInCfg.enColor = stIOInCfg.enColor; ++ stInCfg.enSrcType = stIOInCfg.enSrcType; ++ memcpy(&stInCfg.stCaptureWin , &stIOInCfg.stCaptureWin,sizeof(ST_MDRV_HVSP_WINDOW_CONFIG)); ++ memcpy(&stInCfg.stTimingCfg , &stIOInCfg.stTimingCfg,sizeof(ST_MDRV_HVSPTIMING_CONFIG)); ++ } ++ ++ } ++ stInCfg.stclk = &(_dev_ms_hvsp1.stclk); ++ ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG, (void *)&stInCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInputConfig(E_MDRV_HVSP_ID_1, &stInCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_hvsp1_io_set_output_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_OUTPUT_CONFIG stOutCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG), ++ (((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stOutCfg, (ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++int _mdrv_ms_hvsp1_io_set_scaling_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCALING_CONFIG stIOSclCfg; ++ ST_MDRV_HVSP_SCALING_CONFIG stSclCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SCALING_CONFIG), ++ (((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOSclCfg, (ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_SCALING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stSclCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp1.stclk); ++ stSclCfg.stCropWin.bEn = stIOSclCfg.bCropEn; ++ stSclCfg.stCropWin.u16Height = stIOSclCfg.stCropWin.u16Height; ++ stSclCfg.stCropWin.u16Width = stIOSclCfg.stCropWin.u16Width; ++ stSclCfg.stCropWin.u16X = stIOSclCfg.stCropWin.u16X; ++ stSclCfg.stCropWin.u16Y = stIOSclCfg.stCropWin.u16Y; ++ stSclCfg.u16Dsp_Height = stIOSclCfg.u16Dsp_Height; ++ stSclCfg.u16Dsp_Width = stIOSclCfg.u16Dsp_Width; ++ stSclCfg.u16Src_Height = stIOSclCfg.u16Src_Height; ++ stSclCfg.u16Src_Width = stIOSclCfg.u16Src_Width; ++ } ++ } ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG, (void *)&stSclCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetScalingConfig(E_MDRV_HVSP_ID_1, &stSclCfg )) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++int _mdrv_ms_hvsp1_io_req_mem_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_REQ_MEM_CONFIG stReqMemCfg; ++ ST_MDRV_HVSP_IPM_CONFIG stIPMCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_REQ_MEM_CONFIG), ++ (((ST_IOCTL_HVSP_REQ_MEM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_REQ_MEM_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stReqMemCfg, (ST_IOCTL_HVSP_REQ_MEM_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_REQ_MEM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ret = _mdrv_hvsp1_CheckModifyMemSize(&stReqMemCfg); ++ _mdrv_hvsp1_DNRBufferMemoryAllocate(); ++ stIPMCfg = _mdrv_hvsp1_FillIPMStructForDriver(stReqMemCfg); ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_MEM_REQ_CONFIG, (void *)&stIPMCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(MDrv_HVSP_SetInitIPMConfig(E_MDRV_HVSP_ID_1, &stIPMCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ } ++ if(gu8DNRBufferReadyNum == 0) ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_set_misc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_MISC_CONFIG stIOMiscCfg; ++ ST_MDRV_HVSP_MISC_CONFIG stMiscCfg; ++ if(copy_from_user(&stIOMiscCfg, (ST_IOCTL_HVSP_MISC_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_MISC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ memcpy(&stMiscCfg, &stIOMiscCfg,sizeof(ST_IOCTL_HVSP_MISC_CONFIG)); ++ } ++ ++ if(MDrv_HVSP_SetMiscConfig(&stMiscCfg)) ++ { ++ return 0; ++ } ++ else ++ { ++ return -EFAULT; ++ } ++} ++ ++int _mdrv_ms_hvsp1_io_set_post_crop_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_POSTCROP_CONFIG stIOPostCfg; ++ ST_MDRV_HVSP_POSTCROP_CONFIG stPostCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_POSTCROP_CONFIG), ++ (((ST_IOCTL_HVSP_POSTCROP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_POSTCROP_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOPostCfg, (ST_IOCTL_HVSP_POSTCROP_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_POSTCROP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stPostCfg.bCropEn = stIOPostCfg.bCropEn; ++ stPostCfg.bFmCntEn = stIOPostCfg.bFmCntEn; ++ stPostCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp1.stclk); ++ stPostCfg.u16Height = stIOPostCfg.u16Height; ++ stPostCfg.u16Width = stIOPostCfg.u16Width; ++ stPostCfg.u16X = stIOPostCfg.u16X; ++ stPostCfg.u16Y = stIOPostCfg.u16Y; ++ stPostCfg.u8FmCnt = stIOPostCfg.u8FmCnt; ++ } ++ } ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_POST_CROP_CONFIG, (void *)&stPostCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetPostCropConfig(E_MDRV_HVSP_ID_1, &stPostCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_HVSP_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_hvsp1_io_get_inform_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCINFORM_CONFIG stIOInfoCfg; ++ ST_MDRV_HVSP_SCINFORM_CONFIG stInfoCfg; ++ int Ret = 0; ++ if(!MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_1, &stInfoCfg)) ++ { ++ Ret = -EFAULT; ++ } ++ else ++ { ++ memcpy(&stIOInfoCfg, &stInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG)); ++ if(copy_to_user((ST_IOCTL_HVSP_SCINFORM_CONFIG __user *)arg, &stIOInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG))) ++ { ++ Ret = -EFAULT; ++ } ++ else ++ { ++ Ret = 0; ++ } ++ } ++ ++ return Ret; ++} ++ ++int _mdrv_ms_hvsp1_io_release_mem_config(struct file *filp, unsigned long arg) ++{ ++ _ms_hvsp1_mem_free(); ++ return 0; ++} ++ ++int _mdrv_ms_hvsp1_io_set_osd_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_OSD_CONFIG stOSDCfg; ++ ST_IOCTL_HVSP_OSD_CONFIG stIOOSDCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OSD_CONFIG), ++ (((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOOSDCfg, (ST_IOCTL_HVSP_OSD_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_OSD_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stOSDCfg.enOSD_loc = stIOOSDCfg.enOSD_loc; ++ stOSDCfg.stOsdOnOff.bOSDEn = stIOOSDCfg.bEn; ++ } ++ } ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG, (void *)&stOSDCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetOSDConfig(E_MDRV_HVSP_ID_1, &stOSDCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_set_fb_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG stFbMgCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG), ++ (((ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stFbMgCfg, (ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(!MDrv_HVSP_SetFbManageConfig((EN_MDRV_HVSP_FBMG_SET_TYPE)stFbMgCfg.enSet)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_HVSP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[HVSP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_HVSP_VERSION_CONFIG), ++ (((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_HVSP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_HVSP_VERSION); ++ stCfg.u32Version = IOCTL_HVSP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP] No Header !!! \n"); ++ SCL_ERR( "[HVSP]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_hvsp1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_hvsp1.refCnt <= 0) ++ { ++ SCL_ERR( "[HVSP1] HVSP1IO_IOCTL refCnt =%d!!! \n", _dev_ms_hvsp1.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_HVSP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_HVSP_MAX_NR) ++ { ++ SCL_ERR( "[HVSP1] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1, "[HVSP1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_input_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OUT_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_output_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_scaling_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_REQ_MEM_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_req_mem_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_MISC_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_misc_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_POST_CROP_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_post_crop_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_INFORM_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_get_inform_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_RELEASE_MEM_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_release_mem_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OSD_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_osd_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_FB_MANAGE_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_fb_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_get_version(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[HVSP1] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_hvsp1_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1, "[HVSP1]start %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = MDrv_HVSP_GetWaitQueueHead(); ++ MDrv_HVSP_SetPollWait(filp, pWaitQueueHead, wait); ++ if(MDrv_HVSP_GetCMDQDoneStatus()) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_hvsp1_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = SCL_IRQ_ID; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = CMDQ_IRQ_ID; ++ if(MDrv_HVSP_Suspend(E_MDRV_HVSP_ID_1, &stHvspSuspendResumeCfg)) ++ { ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++static int mdrv_ms_hvsp1_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = SCL_IRQ_ID; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = CMDQ_IRQ_ID; ++ if(MDrv_HVSP_Resume(E_MDRV_HVSP_ID_1, &stHvspSuspendResumeCfg)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp1_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_hvsp1.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ ++ _dev_ms_hvsp1.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp1_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data); ++ filp->private_data = NULL; ++ _dev_ms_hvsp1.refCnt--; ++ SCL_ASSERT(_dev_ms_hvsp1.refCnt>=0); ++ if(_dev_ms_hvsp1.refCnt == 0) ++ { ++ MDrv_HVSP_Release(E_MDRV_HVSP_ID_1); ++ } ++ return 0; ++} ++#if CONFIG_OF ++static int mdrv_ms_hvsp1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ unsigned char ret; ++ int s32Ret; ++ dev_t dev; ++ //struct resource *res_irq; ++ //struct device_node *np; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,__LINE__); ++//mod init ++ if(_dev_ms_hvsp1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp1.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP1] Unable to get major %d\n", _dev_ms_hvsp1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp1.cdev, &_dev_ms_hvsp1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp1.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ m_hvsp1_class = msys_get_sysfs_class(); ++ if(!m_hvsp1_class) ++ { ++ m_hvsp1_class = class_create(THIS_MODULE, hvsp1_classname); ++ } ++ if(IS_ERR(m_hvsp1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_hvsp1.devicenode = device_create(m_hvsp1_class, NULL, dev,NULL, "mhvsp1"); ++ _dev_ms_hvsp1.devicenode->dma_mask=&ms_hvsp1_dma_mask; ++ _dev_ms_hvsp1.devicenode->coherent_dma_mask=ms_hvsp1_dma_mask; ++ } ++ ++//probe ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ //res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);// return NULL ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ //if (res_irq) ++ //{ ++ //SCL_IRQ_ID = res_irq->start; ++ //SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] Get resource IORESOURCE_IRQ = 0x%x\n",SCL_IRQ_ID); ++ //} ++ //else ++ { ++ SCL_IRQ_ID = of_irq_to_resource(pdev->dev.of_node, 0, NULL); ++ CMDQ_IRQ_ID = of_irq_to_resource(pdev->dev.of_node, 1, NULL); ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] Get resource SCL_IRQ = 0x%x\n",SCL_IRQ_ID); ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] Get resource CMDQ_IRQ = 0x%x\n",CMDQ_IRQ_ID); ++ if (!SCL_IRQ_ID) ++ { ++ SCL_ERR( "[HVSP1] Can't Get SCL_IRQ\n"); ++ return -EINVAL; ++ } ++ if (!CMDQ_IRQ_ID) ++ { ++ SCL_ERR( "[HVSP1] Can't Get CMDQ_IRQ\n"); ++ return -EINVAL; ++ } ++ } ++ stHVSPInitCfg.u32IRQNUM = SCL_IRQ_ID; ++ stHVSPInitCfg.u32CMDQIRQNUM = CMDQ_IRQ_ID; ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_1, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_hvsp1_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_hvsp1.stclk.idclk = of_clk_get(st_ms_hvsp1_device.dev.of_node,0); ++ _dev_ms_hvsp1.stclk.fclk1 = of_clk_get(st_ms_hvsp1_device.dev.of_node,1); ++ _dev_ms_hvsp1.stclk.fclk2 = of_clk_get(st_ms_hvsp1_device.dev.of_node,2); ++ _dev_ms_hvsp1.stclk.odclk = of_clk_get(st_ms_hvsp1_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_hvsp1.stclk.idclk) || IS_ERR(_dev_ms_hvsp1.stclk.fclk1) || IS_ERR(_dev_ms_hvsp1.stclk.fclk2)|| IS_ERR(_dev_ms_hvsp1.stclk.odclk)) ++ { ++ SCL_ERR( "[HVSP1] Can't Get CLK\n"); ++ return 0 ; ++ } ++ //create device ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_ptgen); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_monitorHW); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_clk); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_proc); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_dbgmg); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_osd); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_fbmg); ++ ++ Reset_DBGMG_FLAG(); ++ if (ret != 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] attr ok\n"); ++ } ++ gbProbeAlready |= EN_DBG_HVSP1_CONFIG; ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1); ++ return 0; ++} ++static int mdrv_ms_hvsp1_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ _ms_hvsp1_mem_free(); ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ cdev_del(&_dev_ms_hvsp1.cdev); ++ device_destroy(m_hvsp1_class, MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor)); ++ class_destroy(m_hvsp1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_hvsp1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ unsigned char ret; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ SCL_IRQ_ID = SCLIRQ_ID; ++ CMDQ_IRQ_ID = CMDQIRQ_ID; ++ stHVSPInitCfg.u32IRQNUM = SCL_IRQ_ID; ++ stHVSPInitCfg.u32CMDQIRQNUM = CMDQ_IRQ_ID; ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_1, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ //no device tree use hardcode ++ //create device ++ ++ ret = device_create_file(&pdev->dev, &dev_attr_ptgen); ++ ret = device_create_file(&pdev->dev, &dev_attr_monitorHW); ++ ret = device_create_file(&pdev->dev, &dev_attr_clk); ++ ret = device_create_file(&pdev->dev, &dev_attr_proc); ++ ret = device_create_file(&pdev->dev, &dev_attr_dbgmg); ++ Reset_DBGMG_FLAG(); ++ if (ret != 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1); ++ return 0; ++} ++static int mdrv_ms_hvsp1_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ _ms_hvsp1_mem_free(); ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ ++ return 0; ++} ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_hvsp1_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_hvsp1_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_HVSP1_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++} ++#else ++ ++int _mdrv_ms_hvsp1_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ //struct device_node *np; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ //np = of_find_compatible_node(NULL, NULL, "mstar,hvsp1"); ++ //if (np) ++ //{ ++ // SCL_DBG(SCL_DBG_LV_MDRV_IO(), "Find scl dts node\n"); ++ // st_ms_hvsp1_device.dev.of_node = of_node_get(np); ++ // of_node_put(np); ++ //} ++ //else ++ //{ ++ // return -ENODEV; ++ //} ++ ++ if(_dev_ms_hvsp1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp1.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP1] Unable to get major %d\n", _dev_ms_hvsp1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp1.cdev, &_dev_ms_hvsp1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp1.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp1_class = class_create(THIS_MODULE, hvsp1_classname); ++ if(IS_ERR(m_hvsp1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_hvsp1_class, NULL, dev,NULL, "mhvsp1"); ++ } ++ ++ ret = platform_driver_register(&st_ms_hvsp1_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_hvsp1_device); ++ if (ret) // if register device fail, then unregister the driver. ++ { ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++ SCL_ERR( "[HVSP1] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_hvsp1.cdev); ++ device_destroy(m_hvsp1_class, MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor)); ++ class_destroy(m_hvsp1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++} ++ ++#endif ++ ++ ++module_init(_mdrv_ms_hvsp1_init); ++module_exit(_mdrv_ms_hvsp1_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms hvsp1 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_hvsp2_io.c b/drivers/mstar/scl/infinity/mdrv_hvsp2_io.c +new file mode 100644 +index 00000000..499c2070 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_hvsp2_io.c +@@ -0,0 +1,902 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "ms_msys.h" ++#include "mdrv_hvsp_io_st.h" ++#include "mdrv_hvsp_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_HVSP_DEVICE_COUNT 1 ++#define MDRV_MS_HVSP_NAME "mhvsp2" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_HVSP "mhvsp2" ++#define MDRV_MAJOR_HVSP 0xea ++#define MDRV_MINOR_HVSP 0x02 ++//------------------------------------------------------------------------------------------------- ++ ++#define CMD_PARSING(x) (x==IOCTL_HVSP_SET_IN_CONFIG ? "IOCTL_HVSP_SET_IN_CONFIG" : \ ++ x==IOCTL_HVSP_SET_OUT_CONFIG ? "IOCTL_HVSP_SET_OUT_CONFIG" : \ ++ x==IOCTL_HVSP_SET_SCALING_CONFIG ? "IOCTL_HVSP_SET_SCALING_CONFIG" : \ ++ x==IOCTL_HVSP_REQ_MEM_CONFIG ? "IOCTL_HVSP_REQ_MEM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_MISC_CONFIG ? "IOCTL_HVSP_SET_MISC_CONFIG" : \ ++ x==IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ? "IOCTL_HVSP_GET_PRIVATE_ID_CONFIG" : \ ++ "UNKNOWN") ++ ++//------------------------------------------------------------------------------------------------- ++ ++int mdrv_ms_hvsp2_open(struct inode *inode, struct file *filp); ++int mdrv_ms_hvsp2_release(struct inode *inode, struct file *filp); ++long mdrv_ms_hvsp2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_hvsp2_probe(struct platform_device *pdev); ++static int mdrv_ms_hvsp2_remove(struct platform_device *pdev); ++static int mdrv_ms_hvsp2_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_hvsp2_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_hvsp2_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_HVSP_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_HVSP; ++ ++static ST_DEV_HVSP _dev_ms_hvsp2 = ++{ ++ .s32Major = MDRV_MAJOR_HVSP, ++ .s32Minor = MDRV_MINOR_HVSP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_HVSP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_hvsp2_open, ++ .release = mdrv_ms_hvsp2_release, ++ .unlocked_ioctl = mdrv_ms_hvsp2_ioctl, ++ .poll = mdrv_ms_hvsp2_poll, ++ } ++}; ++ ++static struct class * m_hvsp2_class = NULL; ++static char * hvsp2_classname = "m_hvsp2_class"; ++ ++ ++static const struct of_device_id ms_hvsp2_of_match_table[] = ++{ ++ { .compatible = "mstar,hvsp2" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_hvsp2_driver = ++{ ++ .probe = mdrv_ms_hvsp2_probe, ++ .remove = mdrv_ms_hvsp2_remove, ++ .suspend = mdrv_ms_hvsp2_suspend, ++ .resume = mdrv_ms_hvsp2_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_HVSP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_hvsp2_of_match_table), ++ }, ++}; ++ ++static u64 ms_hvsp2_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_hvsp2_device = ++{ ++ .name = "mhvsp2", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_hvsp2_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ST_MDRV_HVSP_VERSIONCHK_CONFIG _mdrv_ms_hvsp2_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_hvsp2_io_version_check(ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP2] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[HVSP2] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP2] No Header !!! \n"); ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++ ++static int _ms_hvsp2_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp2_io_set_input_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_INPUT_CONFIG stInCfg; ++ ST_IOCTL_HVSP_INPUT_CONFIG stIOInCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_INPUT_CONFIG), ++ (((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOInCfg, (ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_INPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stInCfg.enColor = stIOInCfg.enColor; ++ stInCfg.enSrcType = stIOInCfg.enSrcType; ++ memcpy(&stInCfg.stCaptureWin , &stIOInCfg.stCaptureWin,sizeof(ST_MDRV_HVSP_WINDOW_CONFIG)); ++ memcpy(&stInCfg.stTimingCfg , &stIOInCfg.stTimingCfg,sizeof(ST_MDRV_HVSPTIMING_CONFIG)); ++ } ++ ++ } ++ ++ if(_ms_hvsp2_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG, (void *)&stInCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInputConfig(E_MDRV_HVSP_ID_2, &stInCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_hvsp2_io_set_output_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_OUTPUT_CONFIG stOutCfg; ++ int ret = 0; ++ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG), ++ (((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stOutCfg, (ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++int _mdrv_ms_hvsp2_io_set_scaling_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCALING_CONFIG stIOSclCfg; ++ ST_MDRV_HVSP_SCALING_CONFIG stSclCfg; ++ int ret = 0; ++ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SCALING_CONFIG), ++ (((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOSclCfg, (ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_SCALING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stSclCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp2.stclk); ++ stSclCfg.stCropWin.bEn = stIOSclCfg.bCropEn; ++ stSclCfg.stCropWin.u16Height = stIOSclCfg.stCropWin.u16Height; ++ stSclCfg.stCropWin.u16Width = stIOSclCfg.stCropWin.u16Width; ++ stSclCfg.stCropWin.u16X = stIOSclCfg.stCropWin.u16X; ++ stSclCfg.stCropWin.u16Y = stIOSclCfg.stCropWin.u16Y; ++ stSclCfg.u16Dsp_Height = stIOSclCfg.u16Dsp_Height; ++ stSclCfg.u16Dsp_Width = stIOSclCfg.u16Dsp_Width; ++ stSclCfg.u16Src_Height = stIOSclCfg.u16Src_Height; ++ stSclCfg.u16Src_Width = stIOSclCfg.u16Src_Width; ++ } ++ } ++ if(_ms_hvsp2_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG, (void *)&stSclCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetScalingConfig(E_MDRV_HVSP_ID_2, &stSclCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp2_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_HVSP_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_hvsp2_io_get_inform_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCINFORM_CONFIG stIOInfoCfg; ++ ST_MDRV_HVSP_SCINFORM_CONFIG stInfoCfg; ++ int ret = 0; ++ if(!MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_2, &stInfoCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ memcpy(&stIOInfoCfg, &stInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG)); ++ if(copy_to_user((ST_IOCTL_HVSP_SCINFORM_CONFIG __user *)arg, &stIOInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp2_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_HVSP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[HVSP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_HVSP_VERSION_CONFIG), ++ (((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_HVSP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_HVSP_VERSION); ++ stCfg.u32Version = IOCTL_HVSP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP] No Header !!! \n"); ++ SCL_ERR( "[HVSP]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_hvsp2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_hvsp2.refCnt <= 0) ++ { ++ SCL_ERR( "[HVSP2] HVSP2IO_IOCTL refCnt =%d!!! \n", _dev_ms_hvsp2.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_HVSP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_HVSP_MAX_NR) ++ { ++ SCL_ERR( "[HVSP2] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP2] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2, "[HVSP2] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_input_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OUT_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_output_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_scaling_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OSD_CONFIG: ++ case IOCTL_HVSP_SET_FB_MANAGE_CONFIG: ++ case IOCTL_HVSP_REQ_MEM_CONFIG: ++ case IOCTL_HVSP_SET_MISC_CONFIG: ++ case IOCTL_HVSP_SET_POST_CROP_CONFIG: ++ SCL_ERR( "[HVSP2] Not Support IOCTL %x\n ",u32Cmd); ++ retval = -EINVAL; ++ break; ++ case IOCTL_HVSP_GET_INFORM_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_get_inform_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_get_version(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[HVSP2] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_hvsp2_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2, "[SCLDMA1]start %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = MDrv_HVSP_GetWaitQueueHead(); ++ MDrv_HVSP_SetPollWait(filp, pWaitQueueHead, wait); ++ if(MDrv_HVSP_GetCMDQDoneStatus()) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_hvsp2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s:%d\n",__FUNCTION__,__LINE__); ++//mod init ++ if(_dev_ms_hvsp2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp2.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP2] Unable to get major %d\n", _dev_ms_hvsp2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp2.cdev, &_dev_ms_hvsp2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp2.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp2_class = msys_get_sysfs_class(); ++ if(!m_hvsp2_class) ++ { ++ m_hvsp2_class = class_create(THIS_MODULE, hvsp2_classname); ++ } ++ if(IS_ERR(m_hvsp2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_hvsp2.devicenode = device_create(m_hvsp2_class, NULL, dev,NULL, "mhvsp2"); ++ _dev_ms_hvsp2.devicenode->dma_mask=&ms_hvsp2_dma_mask; ++ _dev_ms_hvsp2.devicenode->coherent_dma_mask=ms_hvsp2_dma_mask; ++ } ++ ++//probe ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_2, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_hvsp2_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_hvsp2.stclk.idclk = of_clk_get(st_ms_hvsp2_device.dev.of_node,0); ++ _dev_ms_hvsp2.stclk.fclk1 = of_clk_get(st_ms_hvsp2_device.dev.of_node,1); ++ _dev_ms_hvsp2.stclk.fclk2 = of_clk_get(st_ms_hvsp2_device.dev.of_node,2); ++ _dev_ms_hvsp2.stclk.odclk = of_clk_get(st_ms_hvsp2_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_hvsp2.stclk.idclk) || IS_ERR(_dev_ms_hvsp2.stclk.fclk1) ++ || IS_ERR(_dev_ms_hvsp2.stclk.fclk2)|| IS_ERR(_dev_ms_hvsp2.stclk.odclk)) ++ { ++ SCL_ERR( "[HVSP2] Can't Get CLK\n"); ++ return 0 ; ++ } ++ //sysfs_create_link(&pdev->dev.parent->kobj, &pdev->dev.kobj, "mhvsp2"); ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2); ++ gbProbeAlready |= EN_DBG_HVSP2_CONFIG; ++ return 0; ++} ++static int mdrv_ms_hvsp2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ cdev_del(&_dev_ms_hvsp2.cdev); ++ device_destroy(m_hvsp2_class, MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor)); ++ class_destroy(m_hvsp2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ return 0; ++} ++ ++#else ++static int mdrv_ms_hvsp2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_2, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2); ++ ++ return 0; ++} ++ ++static int mdrv_ms_hvsp2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ return 0; ++} ++#endif ++static int mdrv_ms_hvsp2_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Suspend(E_MDRV_HVSP_ID_2, &stHvspSuspendResumeCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++static int mdrv_ms_hvsp2_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Resume(E_MDRV_HVSP_ID_2, &stHvspSuspendResumeCfg)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp2_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_hvsp2.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ ++ _dev_ms_hvsp2.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp2_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, filp->private_data); ++ ++ _dev_ms_hvsp2.refCnt--; ++ SCL_ASSERT(_dev_ms_hvsp2.refCnt >= 0); ++ if(_dev_ms_hvsp2.refCnt == 0) ++ { ++ MDrv_HVSP_Release(E_MDRV_HVSP_ID_2); ++ } ++ //free_irq(INT_IRQ_HVSP2W, MDrv_HVSP2W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_hvsp2_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_hvsp2_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_HVSP2_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[HVSP2] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP2] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++} ++#else ++int _mdrv_ms_hvsp2_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ struct device_node *np = NULL; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_hvsp2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp2.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP2] Unable to get major %d\n", _dev_ms_hvsp2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp2.cdev, &_dev_ms_hvsp2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp2.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp2_class = class_create(THIS_MODULE, hvsp2_classname); ++ if(IS_ERR(m_hvsp2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_hvsp2_class, NULL, dev,NULL, "mhvsp2"); ++ } ++ ++ /* initial the whole HVSP2 Driver */ ++ ret = platform_driver_register(&st_ms_hvsp2_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_hvsp2_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++ SCL_ERR( "[HVSP2] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_hvsp2.cdev); ++ device_destroy(m_hvsp2_class, MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor)); ++ class_destroy(m_hvsp2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_hvsp2_init); ++module_exit(_mdrv_ms_hvsp2_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms hvsp2 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_hvsp3_io.c b/drivers/mstar/scl/infinity/mdrv_hvsp3_io.c +new file mode 100644 +index 00000000..b3cba247 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_hvsp3_io.c +@@ -0,0 +1,930 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "ms_msys.h" ++#include "mdrv_hvsp_io_st.h" ++#include "mdrv_hvsp_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_HVSP_DEVICE_COUNT 1 ++#define MDRV_MS_HVSP_NAME "mhvsp3" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_HVSP "mhvsp3" ++#define MDRV_MAJOR_HVSP 0xea ++#define MDRV_MINOR_HVSP 0x03 ++//------------------------------------------------------------------------------------------------- ++ ++#define CMD_PARSING(x) (x==IOCTL_HVSP_SET_IN_CONFIG ? "IOCTL_HVSP_SET_IN_CONFIG" : \ ++ x==IOCTL_HVSP_SET_OUT_CONFIG ? "IOCTL_HVSP_SET_OUT_CONFIG" : \ ++ x==IOCTL_HVSP_SET_SCALING_CONFIG ? "IOCTL_HVSP_SET_SCALING_CONFIG" : \ ++ x==IOCTL_HVSP_REQ_MEM_CONFIG ? "IOCTL_HVSP_REQ_MEM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_MISC_CONFIG ? "IOCTL_HVSP_SET_MISC_CONFIG" : \ ++ x==IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ? "IOCTL_HVSP_GET_PRIVATE_ID_CONFIG" : \ ++ "UNKNOWN") ++ ++//------------------------------------------------------------------------------------------------- ++ ++int mdrv_ms_hvsp3_open(struct inode *inode, struct file *filp); ++int mdrv_ms_hvsp3_release(struct inode *inode, struct file *filp); ++long mdrv_ms_hvsp3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_hvsp3_probe(struct platform_device *pdev); ++static int mdrv_ms_hvsp3_remove(struct platform_device *pdev); ++static int mdrv_ms_hvsp3_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_hvsp3_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_hvsp3_poll(struct file *filp, struct poll_table_struct *wait); ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_HVSP_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_HVSP; ++ ++static ST_DEV_HVSP _dev_ms_hvsp3 = ++{ ++ .s32Major = MDRV_MAJOR_HVSP, ++ .s32Minor = MDRV_MINOR_HVSP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_HVSP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_hvsp3_open, ++ .release = mdrv_ms_hvsp3_release, ++ .unlocked_ioctl = mdrv_ms_hvsp3_ioctl, ++ .poll = mdrv_ms_hvsp3_poll, ++ } ++}; ++ ++static struct class * m_hvsp3_class = NULL; ++static char * hvsp3_classname = "m_hvsp3_class"; ++ ++ ++static const struct of_device_id ms_hvsp3_of_match_table[] = ++{ ++ { .compatible = "mstar,hvsp3" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_hvsp3_driver = ++{ ++ .probe = mdrv_ms_hvsp3_probe, ++ .remove = mdrv_ms_hvsp3_remove, ++ .suspend = mdrv_ms_hvsp3_suspend, ++ .resume = mdrv_ms_hvsp3_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_HVSP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_hvsp3_of_match_table), ++ }, ++}; ++ ++static u64 ms_hvsp3_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_hvsp3_device = ++{ ++ .name = "mhvsp3", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_hvsp3_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Instance function ++//------------------------------------------------------------------------------------------------- ++EN_MDRV_MULTI_INST_CMD_TYPE _mdrv_ms_hvsp3_translate_multiinst_cmd(unsigned int u32Cmd) ++{ ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd; ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ enCmd =E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG; ++ break; ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ enCmd =E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG; ++ break; ++ default: ++ enCmd =E_MDRV_MULTI_INST_CMD_MAX; ++ break; ++ } ++ ++ return enCmd; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ST_MDRV_HVSP_VERSIONCHK_CONFIG _mdrv_ms_hvsp3_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_hvsp3_io_version_check(ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP3] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[HVSP3] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP3] No Header !!! \n"); ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++ ++static int _ms_hvsp3_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp3_io_set_input_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_INPUT_CONFIG stInCfg; ++ ST_IOCTL_HVSP_INPUT_CONFIG stIOInCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_INPUT_CONFIG), ++ (((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOInCfg, (ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_INPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stInCfg.enColor = stIOInCfg.enColor; ++ stInCfg.enSrcType = stIOInCfg.enSrcType; ++ memcpy(&stInCfg.stCaptureWin , &stIOInCfg.stCaptureWin,sizeof(ST_MDRV_HVSP_WINDOW_CONFIG)); ++ memcpy(&stInCfg.stTimingCfg , &stIOInCfg.stTimingCfg,sizeof(ST_MDRV_HVSPTIMING_CONFIG)); ++ } ++ } ++ ++ if(_ms_hvsp3_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG, (void *)&stInCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInputConfig(E_MDRV_HVSP_ID_3, &stInCfg )) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_hvsp3_io_set_output_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_OUTPUT_CONFIG stOutCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG), ++ (((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stOutCfg, (ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++int _mdrv_ms_hvsp3_io_set_scaling_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCALING_CONFIG stIOSclCfg; ++ ST_MDRV_HVSP_SCALING_CONFIG stSclCfg; ++ int ret = 0; ++ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SCALING_CONFIG), ++ (((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_hvsp3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOSclCfg, (ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg, sizeof(ST_IOCTL_HVSP_SCALING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stSclCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp3.stclk); ++ stSclCfg.stCropWin.bEn = stIOSclCfg.bCropEn; ++ stSclCfg.stCropWin.u16Height = stIOSclCfg.stCropWin.u16Height; ++ stSclCfg.stCropWin.u16Width = stIOSclCfg.stCropWin.u16Width; ++ stSclCfg.stCropWin.u16X = stIOSclCfg.stCropWin.u16X; ++ stSclCfg.stCropWin.u16Y = stIOSclCfg.stCropWin.u16Y; ++ stSclCfg.u16Dsp_Height = stIOSclCfg.u16Dsp_Height; ++ stSclCfg.u16Dsp_Width = stIOSclCfg.u16Dsp_Width; ++ stSclCfg.u16Src_Height = stIOSclCfg.u16Src_Height; ++ stSclCfg.u16Src_Width = stIOSclCfg.u16Src_Width; ++ } ++ } ++ if(_ms_hvsp3_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG, (void *)&stSclCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetScalingConfig(E_MDRV_HVSP_ID_3, &stSclCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp3_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_HVSP_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_hvsp3_io_get_inform_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCINFORM_CONFIG stIOInfoCfg; ++ ST_MDRV_HVSP_SCINFORM_CONFIG stInfoCfg; ++ int ret = 0; ++ if(!MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_3, &stInfoCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ memcpy(&stIOInfoCfg, &stInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG)); ++ if(copy_to_user((ST_IOCTL_HVSP_SCINFORM_CONFIG __user *)arg, &stIOInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp3_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_HVSP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[HVSP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_HVSP_VERSION_CONFIG), ++ (((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_HVSP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_HVSP_VERSION); ++ stCfg.u32Version = IOCTL_HVSP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP] No Header !!! \n"); ++ SCL_ERR( "[HVSP]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_hvsp3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_hvsp3.refCnt <= 0) ++ { ++ SCL_ERR( "[HVSP3] HVSP3IO_IOCTL refCnt =%d!!! \n", _dev_ms_hvsp3.refCnt); ++ return -EFAULT; ++ } ++ ++ /* check u32Cmd valid */ ++ if(IOCTL_HVSP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_HVSP_MAX_NR) ++ { ++ SCL_ERR( "[HVSP3] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP3] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[HVSP3] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_input_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OUT_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_output_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_scaling_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OSD_CONFIG: ++ case IOCTL_HVSP_SET_FB_MANAGE_CONFIG: ++ case IOCTL_HVSP_REQ_MEM_CONFIG: ++ case IOCTL_HVSP_SET_MISC_CONFIG: ++ case IOCTL_HVSP_SET_POST_CROP_CONFIG: ++ SCL_ERR( "[HVSP2] Not Support IOCTL %x\n ",u32Cmd); ++ retval = -EINVAL; ++ break; ++ case IOCTL_HVSP_GET_INFORM_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_get_inform_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_get_version(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[HVSP3] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_hvsp3_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[SCLDMA1]start %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = MDrv_HVSP_GetWaitQueueHead(); ++ MDrv_HVSP_SetPollWait(filp, pWaitQueueHead, wait); ++ if(MDrv_HVSP_GetCMDQDoneStatus()) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_hvsp3_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s:%d\n",__FUNCTION__,__LINE__); ++//mod init ++ if(_dev_ms_hvsp3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp3.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP3] Unable to get major %d\n", _dev_ms_hvsp3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp3.cdev, &_dev_ms_hvsp3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp3.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp3_class = msys_get_sysfs_class(); ++ if(!m_hvsp3_class) ++ { ++ m_hvsp3_class = class_create(THIS_MODULE, hvsp3_classname); ++ } ++ if(IS_ERR(m_hvsp3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_hvsp3.devicenode = device_create(m_hvsp3_class, NULL, dev,NULL, "mhvsp3"); ++ _dev_ms_hvsp3.devicenode->dma_mask=&ms_hvsp3_dma_mask; ++ _dev_ms_hvsp3.devicenode->coherent_dma_mask=ms_hvsp3_dma_mask; ++ } ++ ++//probe ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_3, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_hvsp3_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_hvsp3.stclk.idclk = of_clk_get(st_ms_hvsp3_device.dev.of_node,0); ++ _dev_ms_hvsp3.stclk.fclk1 = of_clk_get(st_ms_hvsp3_device.dev.of_node,1); ++ _dev_ms_hvsp3.stclk.fclk2 = of_clk_get(st_ms_hvsp3_device.dev.of_node,2); ++ _dev_ms_hvsp3.stclk.odclk = of_clk_get(st_ms_hvsp3_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_hvsp3.stclk.idclk) || IS_ERR(_dev_ms_hvsp3.stclk.fclk1) ++ || IS_ERR(_dev_ms_hvsp3.stclk.fclk2)|| IS_ERR(_dev_ms_hvsp3.stclk.odclk)) ++ { ++ SCL_ERR( "[HVSP3] Can't Get CLK\n"); ++ return 0 ; ++ } ++ //sysfs_create_link(&pdev->dev.parent->kobj, &pdev->dev.kobj, "mhvsp3"); ++ gbProbeAlready |= EN_DBG_HVSP3_CONFIG; ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3); ++ return 0; ++} ++static int mdrv_ms_hvsp3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ cdev_del(&_dev_ms_hvsp3.cdev); ++ device_destroy(m_hvsp3_class, MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor)); ++ class_destroy(m_hvsp3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ return 0; ++} ++ ++#else ++ ++static int mdrv_ms_hvsp3_probe(struct platform_device *pdev) ++{ ++ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_3, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3); ++ ++ return 0; ++} ++ ++static int mdrv_ms_hvsp3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ return 0; ++} ++ ++#endif ++static int mdrv_ms_hvsp3_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Suspend(E_MDRV_HVSP_ID_3, &stHvspSuspendResumeCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++static int mdrv_ms_hvsp3_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Resume(E_MDRV_HVSP_ID_3, &stHvspSuspendResumeCfg)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int mdrv_ms_hvsp3_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_hvsp3.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ ++ } ++ _dev_ms_hvsp3.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp3_release(struct inode *inode, struct file *filp) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, filp->private_data); ++ ++ _dev_ms_hvsp3.refCnt--; ++ SCL_ASSERT(_dev_ms_hvsp3.refCnt>=0); ++ if(_dev_ms_hvsp3.refCnt == 0) ++ { ++ MDrv_HVSP_Release(E_MDRV_HVSP_ID_3); ++ } ++ //free_irq(INT_IRQ_HVSP3W, MDrv_HVSP3W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_hvsp3_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_hvsp3_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_HVSP3_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[HVSP3] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP3] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++} ++ ++#else ++int _mdrv_ms_hvsp3_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_hvsp3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp3.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP3] Unable to get major %d\n", _dev_ms_hvsp3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp3.cdev, &_dev_ms_hvsp3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp3.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp3_class = class_create(THIS_MODULE, hvsp3_classname); ++ if(IS_ERR(m_hvsp3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_hvsp3_class, NULL, dev,NULL, "mhvsp3"); ++ } ++ ++ /* initial the whole HVSP3 Driver */ ++ ret = platform_driver_register(&st_ms_hvsp3_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_hvsp3_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++ SCL_ERR( "[HVSP3] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++void _mdrv_ms_hvsp3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_hvsp3.cdev); ++ device_destroy(m_hvsp3_class, MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor)); ++ class_destroy(m_hvsp3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_hvsp3_init); ++module_exit(_mdrv_ms_hvsp3_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms hvsp3 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_pnl_io.c b/drivers/mstar/scl/infinity/mdrv_pnl_io.c +new file mode 100644 +index 00000000..c1390842 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_pnl_io.c +@@ -0,0 +1,591 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "ms_msys.h" ++ ++#include "mdrv_pnl_io_st.h" ++#include "mdrv_pnl_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_pnl.h" ++#include "mdrv_verchk.h" ++ ++#define MDRV_MS_PNL_DEVICE_COUNT 1 ++#define MDRV_MS_PNL_NAME "mpnl" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_PNL "mpnl" ++#define MDRV_MAJOR_PNL 0xea ++#define MDRV_MINOR_PNL 0x08 ++ ++#define CMD_PARSING(x) (x==IOCTL_PNL_SET_TIMING_CONFIG ? "IOCTL_PNL_SET_TIMING_CONFIG" : \ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_pnl_open(struct inode *inode, struct file *filp); ++int mdrv_ms_pnl_release(struct inode *inode, struct file *filp); ++long mdrv_ms_pnl_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_pnl_probe(struct platform_device *pdev); ++static int mdrv_ms_pnl_remove(struct platform_device *pdev); ++static int mdrv_ms_pnl_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_pnl_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_pnl_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ struct device *devicenode; ++}ST_DEV_PNL; ++ ++static ST_DEV_PNL _dev_ms_pnl = ++{ ++ .s32Major = MDRV_MAJOR_PNL, ++ .s32Minor = MDRV_MINOR_PNL, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_PNL, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_pnl_open, ++ .release = mdrv_ms_pnl_release, ++ .unlocked_ioctl = mdrv_ms_pnl_ioctl, ++ .poll = mdrv_ms_pnl_poll, ++ } ++}; ++ ++static struct class * m_pnl_class = NULL; ++static char * pnl_classname = "m_pnl_class"; ++ ++ ++static const struct of_device_id ms_pnl_of_match_table[] = ++{ ++ { .compatible = "mstar,pnl" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_pnl_driver = ++{ ++ .probe = mdrv_ms_pnl_probe, ++ .remove = mdrv_ms_pnl_remove, ++ .suspend = mdrv_ms_pnl_suspend, ++ .resume = mdrv_ms_pnl_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_PNL, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_pnl_of_match_table), ++ }, ++}; ++#if (!CONFIG_OF) ++static u64 ms_pnl_dma_mask = 0xffffffffUL; ++static struct platform_device st_ms_pnl_device = ++{ ++ .name = "mpnl", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_pnl_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ ++//---------------------------------------------------------------------------------------------- ++int _mdrv_ms_pnl_io_set_timing_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_PNL_TIMING_CONFIG stCfg; ++ ++ if ( CHK_VERCHK_HEADER( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version), IOCTL_PNL_VERSION) ) ++ { ++ ++ VERCHK_ERR("[PNL] Version(%04x) < %04x!!! \n", ++ ((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_PNL_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCLT_PNL_TIMING_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[PNL] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCLT_PNL_TIMING_CONFIG), ++ (((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->u16Vsync_St), sizeof(ST_MDRV_PNL_TIMING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[PNL] No Header !!! \n"); ++ ++ if(copy_from_user(&stCfg, (ST_MDRV_PNL_TIMING_CONFIG __user *)arg, sizeof(ST_MDRV_PNL_TIMING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[PNL] Size(%04d) \n",(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size) ); ++ ++ ++ if(!MDrv_PNL_Set_Timing_Config(&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_pnl_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_PNL_VERSION) ) ++ { ++ ++ VERCHK_ERR("[PNL] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_PNL_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_PNL_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[PNL] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_PNL_VERSION_CONFIG), ++ (((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_PNL_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_PNL_VERSION); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[PNL] Size(%04d) \n",(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Size) ); ++ stCfg.u32Version = IOCTL_PNL_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_PNL_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[PNL] No Header !!! \n"); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++ ++//============================================================================== ++long mdrv_ms_pnl_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_pnl.refCnt <= 0) ++ { ++ SCL_ERR( "[PNL] PNLIO_IOCTL refCnt =%d!!! \n", _dev_ms_pnl.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_PNL_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_PNL_MAX_NR) ++ { ++ SCL_ERR( "[PNL] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[PNL] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[PNL] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_PNL_SET_TIMING_CONFIG: ++ retval = _mdrv_ms_pnl_io_set_timing_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_PNL_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_pnl_io_get_version(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[PNL] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_pnl_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ++ return 0; ++} ++#if CONFIG_OF ++static int mdrv_ms_pnl_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_PNL_INIT_CONFIG stPnlInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ if(_dev_ms_pnl.s32Major) ++ { ++ dev = MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_pnl.s32Minor, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ _dev_ms_pnl.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[PNL] Unable to get major %d\n", _dev_ms_pnl.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_pnl.cdev, &_dev_ms_pnl.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_pnl.cdev, dev, MDRV_MS_PNL_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[PNL] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_pnl_class = msys_get_sysfs_class(); ++ if(!m_pnl_class) ++ { ++ m_pnl_class = class_create(THIS_MODULE, pnl_classname); ++ } ++ if(IS_ERR(m_pnl_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_pnl.devicenode =device_create(m_pnl_class, NULL, dev,NULL, "mpnl"); ++ } ++ stPnlInitCfg.u32RiuBase = 0x1F000000; ++ if(MDrv_PNL_Init(&stPnlInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ gbProbeAlready |= EN_DBG_PNL_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_pnl_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ cdev_del(&_dev_ms_pnl.cdev); ++ device_destroy(m_pnl_class, MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor)); ++ class_destroy(m_pnl_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor), MDRV_MS_PNL_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_pnl_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_PNL_INIT_CONFIG stPnlInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ stPnlInitCfg.u32RiuBase = 0x1F000000; ++ if(MDrv_PNL_Init(&stPnlInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int mdrv_ms_pnl_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_pnl_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mdrv_ms_pnl_resume(struct platform_device *dev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ MDrv_PNL_Resume(); ++ return 0; ++} ++ ++ ++int mdrv_ms_pnl_open(struct inode *inode, struct file *filp) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_pnl.refCnt>=0); ++ _dev_ms_pnl.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mdrv_ms_pnl_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ _dev_ms_pnl.refCnt--; ++ SCL_ASSERT(_dev_ms_pnl.refCnt>=0); ++ if(_dev_ms_pnl.refCnt==0) ++ { ++ MDrv_PNL_Release(); ++ } ++ //free_irq(INT_IRQ_PNLW, MDrv_PNLW_isr); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_pnl_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_pnl_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_PNL_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[PNL] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[PNL] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_pnl_driver); ++ } ++ ++ return ret; ++} ++void _mdrv_ms_pnl_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_pnl_driver); ++} ++#else ++int _mdrv_ms_pnl_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_pnl.s32Major) ++ { ++ dev = MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_pnl.s32Minor, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ _dev_ms_pnl.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[PNL] Unable to get major %d\n", _dev_ms_pnl.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_pnl.cdev, &_dev_ms_pnl.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_pnl.cdev, dev, MDRV_MS_PNL_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[PNL] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_pnl_class = class_create(THIS_MODULE, pnl_classname); ++ if(IS_ERR(m_pnl_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_pnl_class, NULL, dev,NULL, "mpnl"); ++ } ++ ++ /* initial the whole PNL Driver */ ++ ret = platform_driver_register(&st_ms_pnl_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_pnl_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_pnl_driver); ++ SCL_ERR( "[PNL] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_pnl_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_pnl.cdev); ++ device_destroy(m_pnl_class, MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor)); ++ class_destroy(m_pnl_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor), MDRV_MS_PNL_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_pnl_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_pnl_init); ++module_exit(_mdrv_ms_pnl_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms pnl ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_scldma1_io.c b/drivers/mstar/scl/infinity/mdrv_scldma1_io.c +new file mode 100644 +index 00000000..849f3391 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_scldma1_io.c +@@ -0,0 +1,1426 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_msys.h" ++ ++#include "ms_platform.h" ++#include "mdrv_scldma_io_st.h" ++#include "mdrv_scldma_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma1" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma1" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x04 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG ? "IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG" :\ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_scldma1_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma1_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma1_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma1_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma1_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma1_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma1_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma1 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma1_open, ++ .release = mdrv_ms_scldma1_release, ++ .unlocked_ioctl = mdrv_ms_scldma1_ioctl, ++ .poll = mdrv_ms_scldma1_poll, ++ } ++}; ++ ++static struct class * m_scldma1_class = NULL; ++static char * scldma1_classname = "m_scldma1_class"; ++ ++static const struct of_device_id ms_scldma1_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma1" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma1_driver = ++{ ++ .probe = mdrv_ms_scldma1_probe, ++ .remove = mdrv_ms_scldma1_remove, ++ .suspend = mdrv_ms_scldma1_suspend, ++ .resume = mdrv_ms_scldma1_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma1_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma1_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma1_device = ++{ ++ .name = "mscldma1", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma1_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ ++static ssize_t check_snp_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr; ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ int u32idx; ++ //out =0,in=1 ++ stScldmaAttr = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_SNP,0); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "========================SCL PROC FRAMEWORK======================\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "------------------------SCLDMA SNP CLIENT----------------------\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Enable: %hhd\n",stScldmaAttr.bDMAEn); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "output width: %hd, output height: %hd\n",stScldmaAttr.u16DMAH,stScldmaAttr.u16DMAV); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA color format: %s\n",PARSING_SCLDMA_IOCOLOR(stScldmaAttr.enColorType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA trigger mode: %s\n",PARSING_SCLDMA_IOBUFMD(stScldmaAttr.enBufMDType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer Num: %hd\n",stScldmaAttr.u16BufNum); ++ if(stScldmaAttr.enColorType ==E_MDRV_SCLDMA_COLOR_YUV422) ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*2)); ++ } ++ else ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*3/2)); ++ } ++ for(u32idx=0 ;u32idxptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_SNP,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_SNP,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_IOCTL_SCLDMA_MEM_SNP,0,0); ++ } ++ return n; ++ } ++ return 0; ++} ++static DEVICE_ATTR(cksnp,0600, check_snp_show, check_snp_store); ++ ++ ++static ssize_t check_frm_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr; ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ int u32idx; ++ //out =0,in=1 ++ stScldmaAttr = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_FRM,0); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "========================SCL PROC FRAMEWORK======================\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "------------------------SCLDMA FRM CLIENT----------------------\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Enable: %hhd\n",stScldmaAttr.bDMAEn); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "output width: %hd, output height: %hd\n",stScldmaAttr.u16DMAH,stScldmaAttr.u16DMAV); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA color format: %s\n",PARSING_SCLDMA_IOCOLOR(stScldmaAttr.enColorType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA trigger mode: %s\n",PARSING_SCLDMA_IOBUFMD(stScldmaAttr.enBufMDType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer Num: %hd\n",stScldmaAttr.u16BufNum); ++ if(stScldmaAttr.enColorType ==E_MDRV_SCLDMA_COLOR_YUV422) ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*2)); ++ } ++ else ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*3/2)); ++ } ++ for(u32idx=0 ;u32idxptgen_call ++ { ++ SCL_ERR( "All dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountAllClient(); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_FRM,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_FRM,0,0); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm,0600, check_frm_show, check_frm_store); ++static ssize_t check_db_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ //out =0,in=1 ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "Double buffer Status:%hhd\n",MDrv_SCLDMA_GetDoubleBufferStatus()); ++ return (p8StrBuf - buf); ++} ++static ssize_t check_db_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >ptgen_call ++ { ++ SCL_ERR( "DB default ON %d\n",(int)*str); ++ MDrv_SCLDMA_SetDoubleBufferConfig(1); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "DB default OFF %d\n",(int)*str); ++ MDrv_SCLDMA_SetDoubleBufferConfig(0); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(db,0600, check_db_show, check_db_store); ++ST_MDRV_SCLDMA_VERSIONCHK_CONFIG _mdrv_ms_scldma1_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_scldma1_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA1] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA1] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[SCLDMA1] Size(%d) \n",stVersion.u32StructSize ); ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA1] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++static int _ms_scldma1_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_set_in_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA1] not support IOCTL_SCLDMA_SET_IN_BUFFER_CONFIGn"); ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma1_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA1] not support IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG"); ++ ++ return -EFAULT; ++} ++ST_MDRV_SCLDMA_BUFFER_CONFIG _mdrv_ms_scldma1_io_fillbufferconfig(ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg) ++{ ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ stDMABufferCfg.u8Flag = stIODMABufferCfg.u8Flag; ++ stDMABufferCfg.enBufMDType = stIODMABufferCfg.enBufMDType; ++ stDMABufferCfg.enColorType = stIODMABufferCfg.enColorType; ++ stDMABufferCfg.enMemType = stIODMABufferCfg.enMemType; ++ stDMABufferCfg.u16BufNum = stIODMABufferCfg.u16BufNum; ++ stDMABufferCfg.u16Height = stIODMABufferCfg.u16Height; ++ stDMABufferCfg.u16Width = stIODMABufferCfg.u16Width; ++ memcpy(stDMABufferCfg.u32Base_Y,stIODMABufferCfg.u32Base_Y,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg.u32Base_C,stIODMABufferCfg.u32Base_C,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ return stDMABufferCfg; ++} ++ ++int _mdrv_ms_scldma1_io_set_out_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg; ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDMABufferCfg = _mdrv_ms_scldma1_io_fillbufferconfig(stIODMABufferCfg); ++ } ++ } ++ ++ if(_ms_scldma1_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientConfig(E_MDRV_SCLDMA_ID_1, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = stIOTrigCfg.enMemType; ++ } ++ } ++ ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma1.stclk); ++ if(_ms_scldma1_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientTrigger(E_MDRV_SCLDMA_ID_1, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_SNP) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_SNP,0); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_IMI) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_IMI,0); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32BufferidxVerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_1, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, ++ &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma1.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx(E_MDRV_SCLDMA_ID_1, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma1_io_set_lock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stCfg.ps32IdBuf == NULL || *(stCfg.ps32IdBuf) ==0) ++ { ++ SCL_ERR( "[SCLDMA1] not alloc multiinst buffer"); ++ return -EFAULT; ++ } ++ stMultiInstLockCfg.ps32PrivateID = stCfg.ps32IdBuf; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ if( !MDrv_MultiInst_Lock_Alloc(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2, stMultiInstLockCfg) ) ++ { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma1_io_set_unlock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma1_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stCfg.ps32IdBuf == NULL || *(stCfg.ps32IdBuf) ==0) ++ { ++ SCL_ERR( "[SCLDMA1] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ stMultiInstLockCfg.ps32PrivateID = stCfg.ps32IdBuf; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2, &stMultiInstLockCfg) ) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma1_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, ++ &stCfg, sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma1.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA1] SCLDMA1IO_IOCTL refCnt =%d!!! \n", _dev_ms_scldma1.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA1] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ if(u32Cmd == IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ++ || u32Cmd == IOCTL_SCLDMA_GET_VERSION_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1, "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1HLEVEL, ++ "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma1_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_information_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_lock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_unlock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_version(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA1] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma1_poll(struct file *filp, struct poll_table_struct *pstPollQueue) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMDone, bSNPDone, bIMIDone; ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = MDrv_SCLDMA_GetWaitQueueHead(E_MDRV_SCLDMA_ID_1); ++ MDrv_SCLDMA_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++ bIMIDone = 2; ++ bSNPDone = 2; ++ bFRMDone = 2; ++ if(MDrv_SCLDMA_GetOutBufferDoneEvent(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMDone = (stDoneCfg.bDone == 0x1 )? 0x1 : ++ (stDoneCfg.bDone == 0x2 )? 0x2 : ++ (stDoneCfg.bDone == 0x3 )? 0x3 : ++ (stDoneCfg.bDone == 0xF ) ? 0xF : 0; ++ } ++ else ++ { ++ bFRMDone = 0; ++ } ++ if(bFRMDone &&bFRMDone!=0xF) ++ { ++ if(bFRMDone& 0x1) ++ { ++ ret |= POLLIN; /* read */ ++ } ++ if(bFRMDone& 0x2) ++ { ++ ret |= POLLPRI; ++ } ++ } ++ else if(bFRMDone ==0) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = POLLERR; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1HLEVEL, "[SCLDMA1] %s ret=%x\n",__FUNCTION__,ret); ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma1.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA1] Unable to get major %d\n", _dev_ms_scldma1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma1.cdev, &_dev_ms_scldma1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma1.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma1_class = msys_get_sysfs_class(); ++ if(!m_scldma1_class) ++ { ++ m_scldma1_class = class_create(THIS_MODULE, scldma1_classname); ++ } ++ if(IS_ERR(m_scldma1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma1.devicenode =device_create(m_scldma1_class, NULL, dev,NULL, "mscldma1"); ++ _dev_ms_scldma1.devicenode->dma_mask=&ms_scldma1_dma_mask; ++ _dev_ms_scldma1.devicenode->coherent_dma_mask=ms_scldma1_dma_mask; ++ } ++ //probe ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_1, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_scldma1_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma1.stclk.idclk = of_clk_get(st_ms_scldma1_device.dev.of_node,0); ++ _dev_ms_scldma1.stclk.fclk1 = of_clk_get(st_ms_scldma1_device.dev.of_node,1); ++ _dev_ms_scldma1.stclk.fclk2 = of_clk_get(st_ms_scldma1_device.dev.of_node,2); ++ _dev_ms_scldma1.stclk.odclk = of_clk_get(st_ms_scldma1_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_scldma1.stclk.idclk) || IS_ERR(_dev_ms_scldma1.stclk.fclk1) || IS_ERR(_dev_ms_scldma1.stclk.fclk2)) ++ { ++ SCL_ERR( "[SCLDMA1] Can't Get CLK\n"); ++ return 0 ; ++ } ++ ++ //create device ++ if (device_create_file(_dev_ms_scldma1.devicenode, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(_dev_ms_scldma1.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma1.devicenode, &dev_attr_cksnp)!= 0) ++ { ++ dev_err(_dev_ms_scldma1.devicenode, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma1.devicenode, &dev_attr_db)!= 0) ++ { ++ dev_err(_dev_ms_scldma1.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ gbProbeAlready |= EN_DBG_SCLDMA1_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma1_remove(struct platform_device *pdev) ++{ ++ SCL_ERR( "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma1.stclk)); ++ cdev_del(&_dev_ms_scldma1.cdev); ++ device_destroy(m_scldma1_class, MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor)); ++ class_destroy(m_scldma1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_1, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ ++ //create device ++ ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_cksnp)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ return 0; ++} ++ ++static int mdrv_ms_scldma1_remove(struct platform_device *pdev) ++{ ++ SCL_ERR( "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma1.stclk)); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma1_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_1)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma1.stclk)); ++ MDrv_SCLDMA_Sys_Init(0); ++ ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++static int mdrv_ms_scldma1_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_1)) ++ { ++ MDrv_SCLDMA_Sys_Init(1); ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma1_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma1.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ MDrv_SCLDMA_Sys_Init(1); ++ _dev_ms_scldma1.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma1_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2, NULL); ++ filp->private_data = NULL; ++ ++ _dev_ms_scldma1.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma1.refCnt>=0); ++ if(_dev_ms_scldma1.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_1,&(_dev_ms_scldma1.stclk)); ++ } ++ //free_irq(INT_IRQ_SCLDMA1W, MDrv_SCLDMA1W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma1_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma1_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA1_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma1_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma1_driver); ++} ++ ++#else ++int _mdrv_ms_scldma1_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma1.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA1] Unable to get major %d\n", _dev_ms_scldma1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma1.cdev, &_dev_ms_scldma1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma1.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma1_class = class_create(THIS_MODULE, scldma1_classname); ++ if(IS_ERR(m_scldma1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma1_class, NULL, dev,NULL, "mscldma1"); ++ } ++ ++ /* initial the whole SCLDMA1 Driver */ ++ ret = platform_driver_register(&st_ms_scldma1_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma1_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma1_driver); ++ SCL_ERR( "[SCLDMA1] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma1.cdev); ++ device_destroy(m_scldma1_class, MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor)); ++ class_destroy(m_scldma1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma1_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_scldma1_init); ++module_exit(_mdrv_ms_scldma1_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma1 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_scldma2_io.c b/drivers/mstar/scl/infinity/mdrv_scldma2_io.c +new file mode 100644 +index 00000000..9462ba00 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_scldma2_io.c +@@ -0,0 +1,1199 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include "ms_msys.h" ++ ++#include "ms_platform.h" ++#include "mdrv_scldma_io_st.h" ++#include "mdrv_scldma_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma2" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma2" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x05 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ "UNKNOWN") ++ ++int mdrv_ms_scldma2_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma2_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma2_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma2_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma2_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma2_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma2_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma2 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma2_open, ++ .release = mdrv_ms_scldma2_release, ++ .unlocked_ioctl = mdrv_ms_scldma2_ioctl, ++ .poll = mdrv_ms_scldma2_poll, ++ } ++}; ++ ++static struct class * m_scldma2_class = NULL; ++static char * scldma2_classname = "m_scldma2_class"; ++ ++ ++static const struct of_device_id ms_scldma2_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma2" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma2_driver = ++{ ++ .probe = mdrv_ms_scldma2_probe, ++ .remove = mdrv_ms_scldma2_remove, ++ .suspend = mdrv_ms_scldma2_suspend, ++ .resume = mdrv_ms_scldma2_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma2_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma2_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma2_device = ++{ ++ .name = "mscldma2", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma2_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_frm_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr; ++ //out =0,in=1 ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ int u32idx; ++ //out =0,in=1 ++ stScldmaAttr = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM,0); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "========================SCL PROC FRAMEWORK======================\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "------------------------SCLDMA2 FRM CLIENT----------------------\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Enable: %hhd\n",stScldmaAttr.bDMAEn); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "output width: %hd, output height: %hd\n",stScldmaAttr.u16DMAH,stScldmaAttr.u16DMAV); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA color format: %s\n",PARSING_SCLDMA_IOCOLOR(stScldmaAttr.enColorType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA trigger mode: %s\n",PARSING_SCLDMA_IOBUFMD(stScldmaAttr.enBufMDType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer Num: %hd\n",stScldmaAttr.u16BufNum); ++ if(stScldmaAttr.enColorType ==E_MDRV_SCLDMA_COLOR_YUV422) ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*2)); ++ } ++ else ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*3/2)); ++ } ++ for(u32idx=0 ;u32idxptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM,0,0); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm,0600, check_frm_show, check_frm_store); ++ ++ST_MDRV_SCLDMA_VERSIONCHK_CONFIG _mdrv_ms_scldma2_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_scldma2_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA2] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA2] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA2] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++static int _ms_scldma2_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ST_MDRV_SCLDMA_BUFFER_CONFIG _mdrv_ms_scldma2_io_fillbufferconfig(ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg) ++{ ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ stDMABufferCfg.u8Flag = stIODMABufferCfg.u8Flag; ++ stDMABufferCfg.enBufMDType = stIODMABufferCfg.enBufMDType; ++ stDMABufferCfg.enColorType = stIODMABufferCfg.enColorType; ++ stDMABufferCfg.enMemType = stIODMABufferCfg.enMemType; ++ stDMABufferCfg.u16BufNum = stIODMABufferCfg.u16BufNum; ++ stDMABufferCfg.u16Height = stIODMABufferCfg.u16Height; ++ stDMABufferCfg.u16Width = stIODMABufferCfg.u16Width; ++ memcpy(stDMABufferCfg.u32Base_Y,stIODMABufferCfg.u32Base_Y,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg.u32Base_C,stIODMABufferCfg.u32Base_C,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ return stDMABufferCfg; ++} ++ ++int _mdrv_ms_scldma2_io_set_in_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA2] not support IOCTL_SCLDMA_SET_IN_BUFFER_CONFIGn"); ++ ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma2_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ++ SCL_ERR( "[SCLDMA2] not support IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG"); ++ return -EFAULT; ++} ++ ++int _mdrv_ms_scldma2_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ stVersion = _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_IMI) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_IMI,0); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32BufferidxVerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDMABufferCfg = _mdrv_ms_scldma2_io_fillbufferconfig(stIODMABufferCfg); ++ } ++ } ++ if(_ms_scldma2_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientConfig(E_MDRV_SCLDMA_ID_2, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma2_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = stIOTrigCfg.enMemType; ++ } ++ } ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma2.stclk); ++ if(_ms_scldma2_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientTrigger(E_MDRV_SCLDMA_ID_2, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma2_io_get_in_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA2] not support IOCTL_SCLDMA_GET_ACTIVE_BUFFER_CONFIG"); ++ ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma2_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma2.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx(E_MDRV_SCLDMA_ID_2, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++int _mdrv_ms_scldma2_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data, &stCfg.s32Id)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma2_io_buffer_queue_handle_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG stIOBufferQCfg; ++ ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG stBufferQCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ stVersion = _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma2_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_2, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, ++ &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma2_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, &stCfg, ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma2.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA2] SCLDMA2IO_IOCTL refCnt =%d!!! \n", _dev_ms_scldma2.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA2] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ if(u32Cmd == IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ++ || u32Cmd == IOCTL_SCLDMA_GET_VERSION_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2, "[SCLDMA2] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2HLEVEL, "[SCLDMA2] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma2_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_information_config(filp, u32Arg); ++ break; ++ ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ SCL_ERR( "[SCLDMA2] Not Support IOCTL %x\n ",u32Cmd); ++ retval = -EINVAL; ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_version(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA2] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma2_poll(struct file *filp, struct poll_table_struct *pstPollQueue) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMDone, bIMIDone; ++ unsigned int ret; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2HLEVEL, "[SCLDMA2] %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = MDrv_SCLDMA_GetWaitQueueHead(E_MDRV_SCLDMA_ID_2); ++ MDrv_SCLDMA_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++ bFRMDone = 2; ++ bIMIDone = 2; ++ if(MDrv_SCLDMA_GetOutBufferDoneEvent(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMDone = (stDoneCfg.bDone == 1 )? 1 : ++ (stDoneCfg.bDone == 0xF ) ? 0xF : 0; ++ } ++ else ++ { ++ bFRMDone = 0; ++ } ++ if(bFRMDone && bFRMDone!=0xF) ++ { ++ ret = POLLIN | POLLRDNORM; /* read */ ++ } ++ else if(bFRMDone ==0) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = POLLERR; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma2.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA2] Unable to get major %d\n", _dev_ms_scldma2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma2.cdev, &_dev_ms_scldma2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma2.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma2_class = msys_get_sysfs_class(); ++ if(!m_scldma2_class) ++ { ++ m_scldma2_class = class_create(THIS_MODULE, scldma2_classname); ++ } ++ if(IS_ERR(m_scldma2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma2.devicenode =device_create(m_scldma2_class, NULL, dev,NULL, "mscldma2"); ++ _dev_ms_scldma2.devicenode->dma_mask=&ms_scldma2_dma_mask; ++ _dev_ms_scldma2.devicenode->coherent_dma_mask=ms_scldma2_dma_mask; ++ } ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_2, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ st_ms_scldma2_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma2.stclk.idclk = of_clk_get(st_ms_scldma2_device.dev.of_node,0); ++ _dev_ms_scldma2.stclk.fclk1 = of_clk_get(st_ms_scldma2_device.dev.of_node,1); ++ _dev_ms_scldma2.stclk.fclk2 = of_clk_get(st_ms_scldma2_device.dev.of_node,2); ++ _dev_ms_scldma2.stclk.odclk = of_clk_get(st_ms_scldma2_device.dev.of_node,3); ++ if (device_create_file(_dev_ms_scldma2.devicenode, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(_dev_ms_scldma2.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2); ++ gbProbeAlready |= EN_DBG_SCLDMA2_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma2.stclk)); ++ cdev_del(&_dev_ms_scldma2.cdev); ++ device_destroy(m_scldma2_class, MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor)); ++ class_destroy(m_scldma2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_2, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2); ++ return 0; ++} ++ ++static int mdrv_ms_scldma2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma2.stclk)); ++ cdev_del(&_dev_ms_scldma2.cdev); ++ device_destroy(m_scldma2_class, MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor)); ++ class_destroy(m_scldma2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma2_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_2)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma2.stclk)); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_scldma2_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_2)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma2_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma2.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ ++ _dev_ms_scldma2.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma2_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data); ++ ++ _dev_ms_scldma2.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma2.refCnt>=0); ++ ++ //free_irq(INT_IRQ_SCLDMA2W, MDrv_SCLDMA2W_isr); ++ if(_dev_ms_scldma2.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_2,&(_dev_ms_scldma2.stclk)); ++ } ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma2_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma2_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA2_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma2_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma2_driver); ++} ++ ++#else ++int _mdrv_ms_scldma2_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma2.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA2] Unable to get major %d\n", _dev_ms_scldma2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma2.cdev, &_dev_ms_scldma2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma2.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma2_class = class_create(THIS_MODULE, scldma2_classname); ++ if(IS_ERR(m_scldma2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma2_class, NULL, dev,NULL, "mscldma2"); ++ } ++ ++ /* initial the whole SCLDMA2 Driver */ ++ ret = platform_driver_register(&st_ms_scldma2_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma2_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma2_driver); ++ SCL_ERR( "[SCLDMA2] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma2.cdev); ++ device_destroy(m_scldma2_class, MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor)); ++ class_destroy(m_scldma2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma2_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_scldma2_init); ++module_exit(_mdrv_ms_scldma2_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma2 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_scldma3_io.c b/drivers/mstar/scl/infinity/mdrv_scldma3_io.c +new file mode 100644 +index 00000000..643ae1c9 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_scldma3_io.c +@@ -0,0 +1,1498 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_msys.h" ++ ++#include "ms_platform.h" ++#include "mdrv_scldma_io_st.h" ++#include "mdrv_scldma_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma3" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma3" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x06 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_scldma3_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma3_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma3_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma3_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma3_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma3_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma3_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma3 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma3_open, ++ .release = mdrv_ms_scldma3_release, ++ .unlocked_ioctl = mdrv_ms_scldma3_ioctl, ++ .poll = mdrv_ms_scldma3_poll, ++ } ++}; ++ ++static struct class * m_scldma3_class = NULL; ++static char * scldma3_classname = "m_scldma3_class"; ++ ++ ++static const struct of_device_id ms_scldma3_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma3" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma3_driver = ++{ ++ .probe = mdrv_ms_scldma3_probe, ++ .remove = mdrv_ms_scldma3_remove, ++ .suspend = mdrv_ms_scldma3_suspend, ++ .resume = mdrv_ms_scldma3_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma3_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma3_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma3_device = ++{ ++ .name = "mscldma3", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma3_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_frmR_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr; ++ //out =0,in=1 ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ int i; ++ //out =0,in=1 ++ stScldmaAttr = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM,1); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "========================SCL PROC FRAMEWORK======================\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "------------------------SCLDMA FRMR CLIENT----------------------\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Enable: %hhd\n",stScldmaAttr.bDMAEn); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "output width: %hd, output height: %hd\n",stScldmaAttr.u16DMAH,stScldmaAttr.u16DMAV); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA color format: %s\n",PARSING_SCLDMA_IOCOLOR(stScldmaAttr.enColorType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA trigger mode: %s\n",PARSING_SCLDMA_IOBUFMD(stScldmaAttr.enBufMDType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer Num: %hd\n",stScldmaAttr.u16BufNum); ++ if(stScldmaAttr.enColorType ==E_MDRV_SCLDMA_COLOR_YUV422) ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*2)); ++ } ++ else ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*3/2)); ++ } ++ for(i=0 ;iptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,1); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,1,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,1,0); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrmR,0600, check_frmR_show, check_frmR_store); ++ ++ ++static ssize_t check_frmW_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr; ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ int i; ++ //out =0,in=1 ++ stScldmaAttr = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM,0); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "========================SCL PROC FRAMEWORK======================\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "------------------------SCLDMA FRMW CLIENT----------------------\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Enable: %hhd\n",stScldmaAttr.bDMAEn); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "output width: %hd, output height: %hd\n",stScldmaAttr.u16DMAH,stScldmaAttr.u16DMAV); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA color format: %s\n",PARSING_SCLDMA_IOCOLOR(stScldmaAttr.enColorType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA trigger mode: %s\n",PARSING_SCLDMA_IOBUFMD(stScldmaAttr.enBufMDType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer Num: %hd\n",stScldmaAttr.u16BufNum); ++ if(stScldmaAttr.enColorType ==E_MDRV_SCLDMA_COLOR_YUV422) ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*2)); ++ } ++ else ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*3/2)); ++ } ++ for(i=0 ;iptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,0,0); ++ } ++ return n; ++ } ++ return 0; ++} ++static DEVICE_ATTR(ckfrmW,0600, check_frmW_show, check_frmW_store); ++ST_MDRV_SCLDMA_VERSIONCHK_CONFIG _mdrv_ms_scldma3_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_scldma3_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA3] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA3] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA3] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++static int _ms_scldma3_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32BufferidxVerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDMABufferCfg = _mdrv_ms_scldma3_io_fillbufferconfig(stIODMABufferCfg); ++ } ++ } ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientConfig(E_MDRV_SCLDMA_ID_3, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_scldma3_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = stIOTrigCfg.enMemType; ++ } ++ } ++ ++ stDrvTrigCfg.stclk =& (_dev_ms_scldma3.stclk); ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientTrigger(E_MDRV_SCLDMA_ID_3, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_set_out_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg; ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDMABufferCfg = _mdrv_ms_scldma3_io_fillbufferconfig(stIODMABufferCfg); ++ } ++ } ++ ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientConfig(E_MDRV_SCLDMA_ID_3, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = stIOTrigCfg.enMemType; ++ } ++ } ++ ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma3.stclk); ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientTrigger(E_MDRV_SCLDMA_ID_3, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_in_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma3.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAReadBufferActiveIdx(E_MDRV_SCLDMA_ID_3, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma3.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx(E_MDRV_SCLDMA_ID_3, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_buffer_queue_handle_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG stIOBufferQCfg; ++ ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG stBufferQCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, (ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_3, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma3_io_set_lock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stCfg.ps32IdBuf == NULL || *(stCfg.ps32IdBuf) ==0) ++ { ++ SCL_ERR( "[SCLDMA3] not alloc multiinst buffer"); ++ return -EFAULT; ++ } ++ stMultiInstLockCfg.ps32PrivateID = stCfg.ps32IdBuf; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Alloc(E_MDRV_MULTI_INST_LOCK_ID_SC_3, stMultiInstLockCfg) ) ++ { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma3_io_set_unlock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma3_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stCfg.ps32IdBuf == NULL || *(stCfg.ps32IdBuf) ==0) ++ { ++ SCL_ERR( "[SCLDMA3] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ stMultiInstLockCfg.ps32PrivateID = stCfg.ps32IdBuf; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_3, &stMultiInstLockCfg) ) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma3_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, ++ &stCfg, sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma3.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA3] SCLDMA3IO_IOCTL refCnt =%d!!! \n", _dev_ms_scldma3.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA3] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_lock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_unlock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma3_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_version(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_information_config(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA3] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma3_poll(struct file *filp, struct poll_table_struct *pstPollQueue) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMR_Done = 0; ++ unsigned char bFRMW_Done = 0; ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[SCLDMA3] %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ bFRMR_Done = 0; ++ pWaitQueueHead = MDrv_SCLDMA_GetWaitQueueHead(E_MDRV_SCLDMA_ID_3); ++ MDrv_SCLDMA_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++ if(MDrv_SCLDMA_GetOutBufferDoneEvent(E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMW_Done = stDoneCfg.bDone ? 1: 0; ++ } ++ else ++ { ++ bFRMW_Done = 2; ++ } ++ ++ if(bFRMW_Done == 1) ++ { ++ ret |= (POLLIN | POLLOUT); ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma3_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma3.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA3] Unable to get major %d\n", _dev_ms_scldma3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma3.cdev, &_dev_ms_scldma3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma3.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma3_class = msys_get_sysfs_class(); ++ if(!m_scldma3_class) ++ { ++ m_scldma3_class = class_create(THIS_MODULE, scldma3_classname); ++ } ++ if(IS_ERR(m_scldma3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma3.devicenode =device_create(m_scldma3_class, NULL, dev,NULL, "mscldma3"); ++ _dev_ms_scldma3.devicenode->dma_mask=&ms_scldma3_dma_mask; ++ _dev_ms_scldma3.devicenode->coherent_dma_mask=ms_scldma3_dma_mask; ++ } ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_3, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ st_ms_scldma3_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma3.stclk.idclk = of_clk_get(st_ms_scldma3_device.dev.of_node,0); ++ _dev_ms_scldma3.stclk.fclk1 = of_clk_get(st_ms_scldma3_device.dev.of_node,1); ++ _dev_ms_scldma3.stclk.fclk2 = of_clk_get(st_ms_scldma3_device.dev.of_node,2); ++ _dev_ms_scldma3.stclk.odclk = of_clk_get(st_ms_scldma3_device.dev.of_node,3); ++ if (device_create_file(_dev_ms_scldma3.devicenode, &dev_attr_ckfrmW)!= 0) ++ { ++ dev_err(_dev_ms_scldma3.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma3.devicenode, &dev_attr_ckfrmR)!= 0) ++ { ++ dev_err(_dev_ms_scldma3.devicenode, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ gbProbeAlready |= EN_DBG_SCLDMA3_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma3.stclk)); ++ cdev_del(&_dev_ms_scldma3.cdev); ++ device_destroy(m_scldma3_class, MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor)); ++ class_destroy(m_scldma3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma3_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_3, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrmW)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrmR)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ return 0; ++} ++ ++static int mdrv_ms_scldma3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma3.stclk)); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma3_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_3)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma3.stclk)); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_scldma3_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_3)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma3_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma3.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ ++ } ++ ++ _dev_ms_scldma3.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma3_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ ++ MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_3, NULL); ++ ++ _dev_ms_scldma3.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma3.refCnt>=0); ++ if(_dev_ms_scldma3.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_3,&(_dev_ms_scldma3.stclk)); ++ } ++ //free_irq(INT_IRQ_SCLDMA3W, MDrv_SCLDMA3W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma3_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma3_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA3_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma3_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma3_driver); ++} ++ ++#else ++ ++int _mdrv_ms_scldma3_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma3.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA3] Unable to get major %d\n", _dev_ms_scldma3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma3.cdev, &_dev_ms_scldma3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma3.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma3_class = class_create(THIS_MODULE, scldma3_classname); ++ if(IS_ERR(m_scldma3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma3_class, NULL, dev,NULL, "mscldma3"); ++ } ++ ++ /* initial the whole SCLDMA3 Driver */ ++ ret = platform_driver_register(&st_ms_scldma3_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma3_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma3_driver); ++ SCL_ERR( "[SCLDMA3] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma3.cdev); ++ device_destroy(m_scldma3_class, MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor)); ++ class_destroy(m_scldma3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma3_driver); ++} ++ ++#endif ++module_init(_mdrv_ms_scldma3_init); ++module_exit(_mdrv_ms_scldma3_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma3 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_scldma4_io.c b/drivers/mstar/scl/infinity/mdrv_scldma4_io.c +new file mode 100644 +index 00000000..56c4ef74 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_scldma4_io.c +@@ -0,0 +1,1212 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include "ms_msys.h" ++ ++#include "ms_platform.h" ++#include "mdrv_scldma_io_st.h" ++#include "mdrv_scldma_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma4" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma4" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x09 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_scldma4_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma4_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma4_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma4_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma4_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma4_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma4_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma4_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma4 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma4_open, ++ .release = mdrv_ms_scldma4_release, ++ .unlocked_ioctl = mdrv_ms_scldma4_ioctl, ++ .poll = mdrv_ms_scldma4_poll, ++ } ++}; ++ ++static struct class * m_scldma4_class = NULL; ++static char * scldma4_classname = "m_scldma4_class"; ++ ++ ++static const struct of_device_id ms_scldma4_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma4" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma4_driver = ++{ ++ .probe = mdrv_ms_scldma4_probe, ++ .remove = mdrv_ms_scldma4_remove, ++ .suspend = mdrv_ms_scldma4_suspend, ++ .resume = mdrv_ms_scldma4_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma4_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma4_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma4_device = ++{ ++ .name = "mscldma4", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma4_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_frm_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE u16Y; ++ //out =0,in=1 ++ u16Y = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_PNL, E_MDRV_SCLDMA_MEM_FRM,1); ++ return sprintf(buf,"V count:%hd trig Count:%ld \n",u16Y.u16DMAcount,u16Y.u32Trigcount); ++} ++static ssize_t check_frm_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_PNL,E_MDRV_SCLDMA_MEM_FRM,1); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm,0600, check_frm_show, check_frm_store); ++ST_MDRV_SCLDMA_VERSIONCHK_CONFIG _mdrv_ms_scldma4_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_scldma4_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA3] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA3] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA3] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++ ++static int _ms_scldma4_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_DISP,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma4_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ stDmaInfo = MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_PNL, E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32BufferidxVerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDMABufferCfg = _mdrv_ms_scldma4_io_fillbufferconfig(stIODMABufferCfg); ++ } ++ } ++ ++ if(_ms_scldma4_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientConfig(E_MDRV_SCLDMA_ID_PNL, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_scldma4_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = stIOTrigCfg.enMemType; ++ } ++ } ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma4.stclk); ++ if(_ms_scldma4_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientTrigger(E_MDRV_SCLDMA_ID_PNL, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma4_io_set_out_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA4] not support IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG"); ++ ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma4_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA4] not support IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG"); ++ ++ return -EFAULT; ++} ++ ++int _mdrv_ms_scldma4_io_get_in_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma4.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAReadBufferActiveIdx(E_MDRV_SCLDMA_ID_PNL, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma4_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA4] not support IOCTL_SCLDMA_GET_ACTIVE_BUFFER_CONFIG"); ++ ++ return -EFAULT; ++} ++ ++int _mdrv_ms_scldma4_io_buffer_queue_handle_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG stIOBufferQCfg; ++ ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG stBufferQCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ stVersion = _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, (ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_PNL, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++ ++int _mdrv_ms_scldma4_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma4_io_set_lock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stCfg.ps32IdBuf == NULL || *(stCfg.ps32IdBuf) ==0) ++ { ++ SCL_ERR( "[SCLDMA4] not alloc multiinst buffer"); ++ return -EFAULT; ++ } ++ stMultiInstLockCfg.ps32PrivateID = stCfg.ps32IdBuf; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Alloc(E_MDRV_MULTI_INST_LOCK_ID_DISP, stMultiInstLockCfg) ) ++ { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma4_io_set_unlock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_scldma4_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stCfg.ps32IdBuf == NULL || *(stCfg.ps32IdBuf) ==0) ++ { ++ SCL_ERR( "[SCLDMA4] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ stMultiInstLockCfg.ps32PrivateID = stCfg.ps32IdBuf; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_DISP, &stMultiInstLockCfg) ) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_scldma4_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, ++ &stCfg, sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma4_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma4.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA4] SCLDMA_IOCTL refCnt =%d!!! \n", _dev_ms_scldma4.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA4] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_lock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_unlock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_version(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_information_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma4_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA4] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma4_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMR_Done; ++ unsigned int ret; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ if(MDrv_SCLDMA_GetInBufferDoneEvent(E_MDRV_SCLDMA_ID_PNL, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMR_Done = stDoneCfg.bDone ? 1: 0; ++ } ++ else ++ { ++ bFRMR_Done = 2; ++ } ++ ++ if(bFRMR_Done==1) ++ { ++ ret = (POLLOUT | POLLWRNORM); //writable ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma4_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma4.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma4.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma4.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA4] Unable to get major %d\n", _dev_ms_scldma4.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma4.cdev, &_dev_ms_scldma4.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma4.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA4] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma4_class = msys_get_sysfs_class(); ++ if(!m_scldma4_class) ++ { ++ m_scldma4_class = class_create(THIS_MODULE, scldma4_classname); ++ } ++ if(IS_ERR(m_scldma4_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma4.devicenode =device_create(m_scldma4_class, NULL, dev,NULL, "mscldma4"); ++ _dev_ms_scldma4.devicenode->dma_mask=&ms_scldma4_dma_mask; ++ _dev_ms_scldma4.devicenode->coherent_dma_mask=ms_scldma4_dma_mask; ++ } ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_PNL, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ st_ms_scldma4_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma4.stclk.idclk = of_clk_get(st_ms_scldma4_device.dev.of_node,0); ++ _dev_ms_scldma4.stclk.fclk1 = of_clk_get(st_ms_scldma4_device.dev.of_node,1); ++ _dev_ms_scldma4.stclk.fclk2 = of_clk_get(st_ms_scldma4_device.dev.of_node,2); ++ _dev_ms_scldma4.stclk.odclk = of_clk_get(st_ms_scldma4_device.dev.of_node,3); ++ if (device_create_file(_dev_ms_scldma4.devicenode, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(_dev_ms_scldma4.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_DISP); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ gbProbeAlready |= EN_DBG_SCLDMA4_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma4_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma4.stclk)); ++ cdev_del(&_dev_ms_scldma4.cdev); ++ device_destroy(m_scldma4_class, MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor)); ++ class_destroy(m_scldma4_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma4_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_PNL, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_DISP); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ ++ return 0; ++} ++ ++static int mdrv_ms_scldma4_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma4.stclk)); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma4_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_PNL)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma4.stclk)); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_scldma4_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_PNL)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_DISP, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma4_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma4.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_DISP, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ ++ _dev_ms_scldma4.refCnt++; ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma4_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data); ++ ++ MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_DISP, NULL); ++ ++ _dev_ms_scldma4.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma4.refCnt>=0); ++ if(_dev_ms_scldma4.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_PNL,&(_dev_ms_scldma4.stclk)); ++ } ++ //free_irq(INT_IRQ_SCLDMA4W, MDrv_SCLDMA4W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma4_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma4_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA4_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma4_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma4_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma4_driver); ++} ++ ++#else ++ ++int _mdrv_ms_scldma4_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma4.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma4.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma4.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA4] Unable to get major %d\n", _dev_ms_scldma4.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma4.cdev, &_dev_ms_scldma4.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma4.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA4] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma4_class = class_create(THIS_MODULE, scldma4_classname); ++ if(IS_ERR(m_scldma4_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma4_class, NULL, dev,NULL, "mscldma4"); ++ } ++ ++ /* initial the whole SCLDMA4 Driver */ ++ ret = platform_driver_register(&st_ms_scldma4_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma4_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma4_driver); ++ SCL_ERR( "[SCLDMA4] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma4_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma4.cdev); ++ device_destroy(m_scldma4_class, MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor)); ++ class_destroy(m_scldma4_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma4_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_scldma4_init); ++module_exit(_mdrv_ms_scldma4_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma4 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/mdrv_vip_io.c b/drivers/mstar/scl/infinity/mdrv_vip_io.c +new file mode 100644 +index 00000000..5f757c4c +--- /dev/null ++++ b/drivers/mstar/scl/infinity/mdrv_vip_io.c +@@ -0,0 +1,1692 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "ms_platform.h" ++ ++#include "ms_msys.h" ++ ++#include "mdrv_vip_io_st.h" ++#include "mdrv_vip_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_vip.h" ++#include "mdrv_verchk.h" ++ ++#define MDRV_MS_VIP_DEVICE_COUNT 1 ++#define MDRV_MS_VIP_NAME "mvip" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_VIP "mvip" ++#define MDRV_MAJOR_VIP 0xea ++#define MDRV_MINOR_VIP 0x07 ++#define _ms_vip_mem_bus_to_miu(x) (x-0x20000000) ++#define CMD_PARSING(x) ( x == IOCTL_VIP_SET_DNR_CONFIG ? "IOCTL_VIP_SET_DNR_CONFIG" : \ ++ x == IOCTL_VIP_SET_PEAKING_CONFIG ? "IOCTL_VIP_SET_PEAKING_CONFIG" : \ ++ x == IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG ? "IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG" : \ ++ x == IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ? "IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT" : \ ++ x == IOCTL_VIP_SET_DLC_CONFIG ? "IOCTL_VIP_SET_DLC_CONFIG" : \ ++ x == IOCTL_VIP_SET_LCE_CONFIG ? "IOCTL_VIP_SET_LCE_CONFIG" : \ ++ x == IOCTL_VIP_SET_UVC_CONFIG ? "IOCTL_VIP_SET_UVC_CONFIG" : \ ++ x == IOCTL_VIP_SET_IHC_CONFIG ? "IOCTL_VIP_SET_IHC_CONFIG" : \ ++ x == IOCTL_VIP_SET_ICE_CONFIG ? "IOCTL_VIP_SET_ICE_CONFIG" : \ ++ x == IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG ? "IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG" : \ ++ x == IOCTL_VIP_SET_IBC_CONFIG ? "IOCTL_VIP_SET_IBC_CONFIG" : \ ++ x == IOCTL_VIP_SET_FCC_CONFIG ? "IOCTL_VIP_SET_FCC_CONFIG" : \ ++ x == IOCTL_VIP_CMDQ_WRITE_CONFIG ? "IOCTL_VIP_CMDQ_WRITE_CONFIG" :\ ++ x == IOCTL_VIP_SET_LDC_CONFIG ? "IOCTL_VIP_SET_LDC_OnOff_CONFIG" : \ ++ x == IOCTL_VIP_SET_LDC_MD_CONFIG ? "IOCTL_VIP_SET_LDC_MD_CONFIG" : \ ++ x == IOCTL_VIP_SET_LDC_DMAP_CONFIG ? "IOCTL_VIP_SET_LDC_DMAP_CONFIG" : \ ++ x == IOCTL_VIP_SET_LDC_SRAM_CONFIG ? "IOCTL_VIP_SET_LDC_SRAM_CONFIG" : \ ++ x == IOCTL_VIP_SET_ACK_CONFIG ? "IOCTL_VIP_SET_ACK_CONFIG" : \ ++ x == IOCTL_VIP_SET_NLM_CONFIG ? "IOCTL_VIP_SET_NLM_CONFIG" : \ ++ x == IOCTL_VIP_SET_SNR_CONFIG ? "IOCTL_VIP_SET_SNR_CONFIG" : \ ++ x == IOCTL_VIP_SET_VIP_CONFIG ? "IOCTL_VIP_SET_VIP_CONFIG" : \ ++ x == IOCTL_VIP_SET_VTRACK_CONFIG ? "IOCTL_VIP_SET_VTRACK_CONFIG" : \ ++ x == IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ? "IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG" : \ ++ "UNKNOWN") ++ ++int mdrv_ms_vip_open(struct inode *inode, struct file *filp); ++int mdrv_ms_vip_release(struct inode *inode, struct file *filp); ++long mdrv_ms_vip_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_vip_probe(struct platform_device *pdev); ++static int mdrv_ms_vip_remove(struct platform_device *pdev); ++static int mdrv_ms_vip_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_vip_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_vip_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ struct device *devicenode; ++}ST_DEV_VIP; ++ ++static ST_DEV_VIP _dev_ms_vip = ++{ ++ .s32Major = MDRV_MAJOR_VIP, ++ .s32Minor = MDRV_MINOR_VIP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_VIP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_vip_open, ++ .release = mdrv_ms_vip_release, ++ .unlocked_ioctl = mdrv_ms_vip_ioctl, ++ .poll = mdrv_ms_vip_poll, ++ } ++}; ++ ++static struct class * m_vip_class = NULL; ++static char * vip_classname = "m_vip_class"; ++ ++ ++static const struct of_device_id ms_vip_of_match_table[] = ++{ ++ { .compatible = "mstar,vip" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_vip_driver = ++{ ++ .probe = mdrv_ms_vip_probe, ++ .remove = mdrv_ms_vip_remove, ++ .suspend = mdrv_ms_vip_suspend, ++ .resume = mdrv_ms_vip_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_VIP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_vip_of_match_table), ++ }, ++}; ++static u64 ms_vip_dma_mask = 0xffffffffUL; ++#if (!CONFIG_OF) ++ ++static struct platform_device st_ms_vip_device = ++{ ++ .name = "mvip", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_vip_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++static const char* KEY_DMEM_VIP_CMDQ="VIP_CMDQ"; ++static unsigned char g_bVIPSysInitReady = 0; ++dma_addr_t sg_vip_cmdq_bus_addr; ++static u_long sg_vip_cmdq_size = VIP_CMDQ_MEM_16K;//128kb 1F400 ++static void *sg_vip_cmdq_vir_addr = NULL; ++ST_VIP_CMDQ_INIT_CONFIG gstInitCMDQCfg; ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_bypass_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_ProcShow(buf); ++} ++static ssize_t check_bypass_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass OPEN %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(0x7FFFF); ++ } ++ else if((int)*str == 50) //input 2 echo 2 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_CONFIG); ++ } ++ else if((int)*str == 51) //input 3 echo 3 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_DNR_CONFIG); ++ } ++ else if((int)*str == 52) //input 4 echo 4 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_SNR_CONFIG); ++ } ++ else if((int)*str == 53) //input 5 echo 5 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_NLM_CONFIG); ++ } ++ else if((int)*str == 54) //input 6 echo 6 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_LDC_CONFIG); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(0); ++ } ++ ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(bypass,0600, check_bypass_show, check_bypass_store); ++ ++static ssize_t check_CMDQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "echo 1 > ckCMDQ :by already setting\n"); ++ str += scnprintf(str, end - str, "echo 2 > ckCMDQ :by auto testing\n"); ++ return (str - buf); ++} ++ ++static ssize_t check_CMDQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 > ++ { ++ SCL_ERR( "[CMDQ]CMDQ check by already setting %d\n",(int)*str); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_ALREADY_SETINNG); ++ MDrv_VIP_Resume(); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_RETURN_ORI); ++ MDrv_VIP_CheckRegister(); ++ } ++ else if((int)*str == 50) //input 2 echo 2 > ++ { ++ SCL_ERR( "[CMDQ]CMDQ check by auto testing %d\n",(int)*str); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_AUTOSETTING); ++ MDrv_VIP_Resume(); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_RETURN_ORI); ++ MDrv_VIP_CheckRegister(); ++ } ++ ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(ckCMDQ,0600, check_CMDQ_show, check_CMDQ_store); ++ ++static ssize_t check_PQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "echo 1 > ckPQ :by already setting\n"); ++ str += scnprintf(str, end - str, "echo 2 > ckPQ :by auto testing\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t check_PQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 > ++ { ++ SCL_ERR( "[HVSP1]PQ check by already setting %d\n",(int)*str); ++ MDrv_VIP_CheckConsist(); //consistency ++ MDrv_VIP_CheckRegister(); //basic check register ++ } ++ else if((int)*str == 50) //input 2 echo 2 > ++ { ++ SCL_ERR( "[HVSP1]PQ check by auto testing %d\n",(int)*str); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_PQ); ++ MDrv_VIP_Resume(); ++ MDrv_VIP_CheckRegister(); //basic check register ++ } ++ ++ return n; ++ } ++ ++ return 0; ++} ++static DEVICE_ATTR(ckPQ,0600, check_PQ_show, check_PQ_store); ++static ssize_t CMDQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_CMDQShow(buf); ++} ++ ++ ++static DEVICE_ATTR(CMDQ,0400, CMDQ_show, NULL); ++static ssize_t VIP_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_VIPShow(buf); ++} ++ ++static DEVICE_ATTR(VIPStatus,0400, VIP_show, NULL); ++ ++void _mdrv_ms_vip_LogConfigStruct(ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg) ++{ ++ unsigned char u8offset; ++ unsigned char *pu8value = NULL; ++ for(u8offset = 0;u8offset < stSetPQCfg.u32StructSize;u8offset++) ++ { ++ pu8value = stSetPQCfg.pPointToCfg + u8offset*1; ++ SCL_DBG(SCL_DBG_LV_VIP_LOG(), "[VIP] offset%hhd:%hhx \n",u8offset,*pu8value); ++ ++ } ++} ++void _mdrv_ms_vip_LogConfigByIP(EN_VIP_CONFIG_TYPE enVIPtype,unsigned char *pPointToCfg) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ stSetPQCfg = MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,pPointToCfg); ++ _mdrv_ms_vip_LogConfigStruct(stSetPQCfg); ++} ++ST_MDRV_VIP_VERSIONCHK_CONFIG _mdrv_ms_vip_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion) ++{ ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ stVersion.u32StructSize = (unsigned int)u32StructSize; ++ stVersion.u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion.pVersion = (unsigned int *)pVersion; ++ return stVersion; ++} ++int _mdrv_ms_vip_io_version_check(ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion.pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion.pVersion, IOCTL_VIP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[VIP] Version(%04x) < %04x!!! \n", ++ *(stVersion.pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_VIP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion.u32VersionSize, stVersion.u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[VIP] Size(%04x) != %04x!!! \n", ++ stVersion.u32StructSize, ++ stVersion.u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[VIP] Size(%d) \n",stVersion.u32StructSize ); ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[VIP] No Header !!! \n"); ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++int _mdrv_ms_vip_io_set_dnr_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DNR_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_DNR_CONFIG), ++ (((ST_IOCTL_VIP_DNR_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_DNR_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_DNR_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_DNR_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_DNR_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetDNRConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_peaking_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_PEAKING_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_PEAKING_CONFIG), ++ (((ST_IOCTL_VIP_PEAKING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_PEAKING_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_PEAKING_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_PEAKING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_PEAKING_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetPeakingConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_dlc_histogram_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG), ++ (((ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_DLC_HISTOGRAM_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetHistogramConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_get_dlc_histogram_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT stCfg; ++ ++ if(!MDrv_VIP_GetDLCHistogramReport((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ if (copy_to_user( (ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT __user *)arg, &stCfg, sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT) )) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_dlc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DLC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_DLC_CONFIG), ++ (((ST_IOCTL_VIP_DLC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_DLC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_DLC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_DLC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_DLC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetDLCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_lce_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LCE_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LCE_CONFIG), ++ (((ST_IOCTL_VIP_LCE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LCE_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_LCE_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_LCE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LCE_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLCEConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_uvc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_UVC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_UVC_CONFIG), ++ (((ST_IOCTL_VIP_UVC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_UVC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_UVC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_UVC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_UVC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetUVCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_ihc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_IHC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_IHC_CONFIG), ++ (((ST_IOCTL_VIP_IHC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_IHC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_IHC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_IHC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_IHC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetIHCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_icc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_ICC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_ICC_CONFIG), ++ (((ST_IOCTL_VIP_ICC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_ICC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_ICC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_ICC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_ICC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetICEConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ihc_ice_adp_y_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_IHCICC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_IHCICC_CONFIG), ++ (((ST_IOCTL_VIP_IHCICC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_IHCICC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_IHCICC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_IHCICC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_IHCICC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetIHCICCADPYConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ibc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_IBC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_IBC_CONFIG), ++ (((ST_IOCTL_VIP_IBC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_IBC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_IBC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_IBC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_IBC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetIBCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_fcc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_FCC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_FCC_CONFIG), ++ (((ST_IOCTL_VIP_FCC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_FCC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_FCC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_FCC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_FCC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetFCCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_nlm_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_NLM_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_NLM_CONFIG), ++ (((ST_IOCTL_VIP_NLM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_NLM_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_NLM_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_NLM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_NLM_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetNLMConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.stSRAM.bEn) ++ { ++ MDrv_VIP_SetNLMSRAMConfig(stCfg.stSRAM); ++ } ++ else if(!stCfg.stSRAM.bEn && stCfg.stSRAM.u32viradr) ++ { ++ MDrv_VIP_SetNLMSRAMConfig(stCfg.stSRAM); ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ack_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_ACK_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_ACK_CONFIG), ++ (((ST_IOCTL_VIP_ACK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_ACK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_ACK_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_ACK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_ACK_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetACKConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_snr_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_SNR_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_SNR_CONFIG), ++ (((ST_IOCTL_VIP_SNR_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_SNR_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_SNR_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_SNR_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_SNR_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetSNRConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_cmdq_write_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_CMDQ_CONFIG stCfg; ++ ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_CMDQ_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_CMDQ_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ if(!MDrv_VIP_CMDQWriteConfig(&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_CONFIG), ++ (((ST_IOCTL_VIP_LDC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_LDC_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_LDC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_vip_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_CONFIG), ++ (((ST_IOCTL_VIP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_SetVIPOtherConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_md_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_MD_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_MD_CONFIG), ++ (((ST_IOCTL_VIP_LDC_MD_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_MD_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_LDC_MD_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_LDC_MD_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_MD_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCmdConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_dmap_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_DMAP_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_DMAP_CONFIG), ++ (((ST_IOCTL_VIP_LDC_DMAP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_DMAP_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_LDC_DMAP_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_LDC_DMAP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_DMAP_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCDmapConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_sram_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_SRAM_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_SRAM_CONFIG), ++ (((ST_IOCTL_VIP_LDC_SRAM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_SRAM_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_LDC_SRAM_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_LDC_SRAM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_SRAM_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCSRAMConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_vtrack_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_VTRACK_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_VTRACK_CONFIG), ++ (((ST_IOCTL_VIP_VTRACK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_VTRACK_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_VTRACK_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_VTRACK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(stCfg.bSetKey) ++ { ++ MDrv_VIP_VtrackSetPayloadData(stCfg.u16Timecode,stCfg.u8OperatorID); ++ MDrv_VIP_VtrackSetKey(stCfg.bSetKey,stCfg.u8SetKey); ++ } ++ else ++ { ++ MDrv_VIP_VtrackSetPayloadData(stCfg.u16Timecode,stCfg.u8OperatorID); ++ MDrv_VIP_VtrackSetKey(0,NULL); ++ } ++ if(stCfg.bSetUserDef) ++ { ++ MDrv_VIP_VtrackSetUserDefindedSetting(stCfg.bSetUserDef,stCfg.u8SetUserDef); ++ } ++ else ++ { ++ MDrv_VIP_VtrackSetUserDefindedSetting(0,NULL); ++ } ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_vtrack_onoff_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG), ++ (((ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(!MDrv_VIP_VtrackEnable(stCfg.u8framerate,stCfg.EnType)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_VIP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[VIP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_VIP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_VIP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[VIP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_VIP_VERSION_CONFIG), ++ (((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_VIP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_VIP_VERSION); ++ stCfg.u32Version = IOCTL_VIP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_VIP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[VIP] No Header !!! \n"); ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_vip_io_set_allvip(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_AllSET_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ stVersion = _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_AllSET_CONFIG), ++ (((ST_IOCTL_VIP_AllSET_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_AllSET_CONFIG __user *)arg)->VerChk_Version)); ++ if(_mdrv_ms_vip_io_version_check(stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (ST_IOCTL_VIP_AllSET_CONFIG __user *)arg, sizeof(ST_IOCTL_VIP_AllSET_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ MDrv_VIP_SetAllVIPOneshot(&stCfg.stvipCfg); ++ return 0; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_vip_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_vip.refCnt <= 0) ++ { ++ SCL_ERR( "[VIP] VIPIO_IOCTL refCnt =%d!!! \n", _dev_ms_vip.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_VIP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_VIP_MAX_NR) ++ { ++ SCL_ERR( "[VIP] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[VIP] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_VIP, "[VIP] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_VIP_CMDQ_WRITE_CONFIG: ++ retval = _mdrv_ms_vip_io_cmdq_write_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_MD_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_md_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_DMAP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_dmap_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_SRAM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_sram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_DNR_CONFIG: ++ retval = _mdrv_ms_vip_io_set_dnr_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_PEAKING_CONFIG: ++ retval = _mdrv_ms_vip_io_set_peaking_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_dlc_histogram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT: ++ retval = _mdrv_ms_vip_io_get_dlc_histogram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_DLC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_dlc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LCE_CONFIG: ++ retval = _mdrv_ms_vip_io_set_lce_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_UVC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_uvc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_IHC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ihc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_ICE_CONFIG: ++ retval = _mdrv_ms_vip_io_set_icc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ihc_ice_adp_y_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_IBC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ibc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_FCC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_fcc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_ACK_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ack_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_NLM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_nlm_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_SNR_CONFIG: ++ retval = _mdrv_ms_vip_io_set_snr_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_VIP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_vip_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_VTRACK_CONFIG: ++ retval = _mdrv_ms_vip_io_set_vtrack_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG: ++ retval = _mdrv_ms_vip_io_set_vtrack_onoff_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_vip_io_get_version(filp, u32Arg); ++ break; ++ case IOCLT_VIP_SET_ALLVIP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_allvip(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[VIP] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_vip_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ wait_queue_head_t *event_wait_queue = NULL; ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_VIP, "[VIP]start %s ret=%x\n",__FUNCTION__,ret); ++ event_wait_queue = MDrv_VIP_GetWaitQueueHead(); ++ MDrv_VIP_SetPollWait(filp, event_wait_queue, wait); ++ if(MDrv_VIP_GetCMDQHWDone()) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ if(0 != msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr = dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ dmem.kvirt = (unsigned long long)((uintptr_t)virt); ++ dmem.phys = (unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++static int _ms_vip_mem_allocate(void) ++{ ++ if (!(sg_vip_cmdq_vir_addr = alloc_dmem(KEY_DMEM_VIP_CMDQ, ++ PAGE_ALIGN(sg_vip_cmdq_size), ++ &sg_vip_cmdq_bus_addr))) ++ { ++ SCL_ERR( "%s: unable to allocate screen memory\n", __FUNCTION__); ++ return 0; ++ } ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[CMDQ]: CMDQ: Phy:%x Vir:%x\n", sg_vip_cmdq_bus_addr, (u32)sg_vip_cmdq_vir_addr); ++ gstInitCMDQCfg.u32CMDQ_Phy = Chip_Phys_to_MIU(sg_vip_cmdq_bus_addr); ++ gstInitCMDQCfg.u32CMDQ_Size = sg_vip_cmdq_size; ++ gstInitCMDQCfg.u32CMDQ_Vir = (unsigned long)sg_vip_cmdq_vir_addr; ++ return 1; ++} ++ ++static void _ms_vip_mem_free(void) ++{ ++ free_dmem(KEY_DMEM_VIP_CMDQ, ++ PAGE_ALIGN(sg_vip_cmdq_size), ++ sg_vip_cmdq_vir_addr, ++ sg_vip_cmdq_bus_addr); ++ ++} ++#if CONFIG_OF ++static int mdrv_ms_vip_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ //mod ++ if(_dev_ms_vip.s32Major) ++ { ++ dev = MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_vip.s32Minor, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ _dev_ms_vip.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[VIP] Unable to get major %d\n", _dev_ms_vip.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_vip.cdev, &_dev_ms_vip.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_vip.cdev, dev, MDRV_MS_VIP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[VIP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_vip_class = msys_get_sysfs_class(); ++ if(!m_vip_class) ++ { ++ m_vip_class = class_create(THIS_MODULE, vip_classname); ++ } ++ if(IS_ERR(m_vip_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_vip.devicenode =device_create(m_vip_class, NULL, dev,NULL, "mvip"); ++ _dev_ms_vip.devicenode->dma_mask=&ms_vip_dma_mask; ++ _dev_ms_vip.devicenode->coherent_dma_mask=ms_vip_dma_mask; ++ } ++ //probe ++ if( _ms_vip_mem_allocate() == 0 ) ++ { ++ return -EFAULT; ++ } ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ stVipInitCfg.CMDQCfg.u32CMDQ_Phy = gstInitCMDQCfg.u32CMDQ_Phy; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Size = gstInitCMDQCfg.u32CMDQ_Size; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Vir = gstInitCMDQCfg.u32CMDQ_Vir; ++ if(MDrv_VIP_Init(&stVipInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_VIP_SuspendResetFlagInit(); ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_bypass)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_CMDQ)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_VIPStatus)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_ckCMDQ)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create dev_attr_ckCMDQ sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_ckPQ)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create dev_attr_ckPQ sysfs files\n"); ++ } ++ gbProbeAlready |= EN_DBG_VIP_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_vip_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ MDrv_VIP_Delete(); ++ _ms_vip_mem_free(); ++ g_bVIPSysInitReady = 0; ++ cdev_del(&_dev_ms_vip.cdev); ++ device_destroy(m_vip_class, MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor)); ++ class_destroy(m_vip_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor), MDRV_MS_VIP_DEVICE_COUNT); ++ return 0; ++} ++ ++#else ++static int mdrv_ms_vip_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ if( _ms_vip_mem_allocate() == 0 ) ++ { ++ return -EFAULT; ++ } ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ stVipInitCfg.CMDQCfg.u32CMDQ_Phy = gstInitCMDQCfg.u32CMDQ_Phy; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Size = gstInitCMDQCfg.u32CMDQ_Size; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Vir = gstInitCMDQCfg.u32CMDQ_Vir; ++ if(MDrv_VIP_Init(&stVipInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_VIP_SuspendResetFlagInit(); ++ if (device_create_file(&pdev->dev, &dev_attr_bypass)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckCMDQ)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create dev_attr_ckCMDQ sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckPQ)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create dev_attr_ckPQ sysfs files\n"); ++ } ++ ++ return 0; ++} ++ ++static int mdrv_ms_vip_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ MDrv_VIP_Delete(); ++ _ms_vip_mem_free(); ++ g_bVIPSysInitReady = 0; ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_vip_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ g_bVIPSysInitReady = 0; ++ MDrv_VIP_Delete(); ++ ++ return 0; ++} ++ ++ ++static int mdrv_ms_vip_resume(struct platform_device *dev) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ stVipInitCfg.CMDQCfg.u32CMDQ_Phy = gstInitCMDQCfg.u32CMDQ_Phy; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Size = gstInitCMDQCfg.u32CMDQ_Size; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Vir = gstInitCMDQCfg.u32CMDQ_Vir; ++ MDrv_VIP_Init(&stVipInitCfg); ++ MDrv_VIP_Resume(); ++ MDrv_VIP_Sys_Init(&stVipInitCfg); ++ MDrv_VIP_SuspendResetFlagInit(); ++ g_bVIPSysInitReady = 1; ++ return 0; ++} ++ ++ ++int mdrv_ms_vip_open(struct inode *inode, struct file *filp) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ if(g_bVIPSysInitReady == 0) ++ { ++ if(MDrv_VIP_Sys_Init(&stVipInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ g_bVIPSysInitReady = 1; ++ } ++ ++ SCL_ASSERT(_dev_ms_vip.refCnt >= 0); ++ _dev_ms_vip.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mdrv_ms_vip_release(struct inode *inode, struct file *filp) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ _dev_ms_vip.refCnt--; ++ if(_dev_ms_vip.refCnt==0) ++ { ++ MDrv_VIP_Release(); ++ } ++ SCL_ASSERT(_dev_ms_vip.refCnt >= 0); ++ //free_irq(INT_IRQ_VIPW, MDrv_VIPW_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_vip_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_vip_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_VIP_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[VIP] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[VIP] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_vip_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_vip_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_vip_driver); ++} ++#else ++int _mdrv_ms_vip_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_vip.s32Major) ++ { ++ dev = MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_vip.s32Minor, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ _dev_ms_vip.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[VIP] Unable to get major %d\n", _dev_ms_vip.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_vip.cdev, &_dev_ms_vip.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_vip.cdev, dev, MDRV_MS_VIP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[VIP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_vip_class = class_create(THIS_MODULE, vip_classname); ++ if(IS_ERR(m_vip_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_vip_class, NULL, dev,NULL, "mvip"); ++ } ++ ++ /* initial the whole VIP Driver */ ++ ret = platform_driver_register(&st_ms_vip_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_vip_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_vip_driver); ++ SCL_ERR( "[VIP] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_vip_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_vip.cdev); ++ device_destroy(m_vip_class, MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor)); ++ class_destroy(m_vip_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor), MDRV_MS_VIP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_vip_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_vip_init); ++module_exit(_mdrv_ms_vip_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms vip ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity/src/mdrv_hvsp.c b/drivers/mstar/scl/infinity/src/mdrv_hvsp.c +new file mode 100644 +index 00000000..44992fff +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mdrv_hvsp.c +@@ -0,0 +1,1002 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_HVSP_C ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++ ++#include "mdrv_hvsp_io_st.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "drvpnl.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define PARSING_PAT_TGEN_TIMING(x) (x == E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30 ? "E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30" : \ ++ x == E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60 ? "E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60" : \ ++ x == E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60 ? "E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60" : \ ++ x == E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED ? "E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED" : \ ++ "UNKNOWN") ++#define Is_Wrong_Type(enHVSP_ID,enSrcType)((enHVSP_ID == E_MDRV_HVSP_ID_1 && (enSrcType == E_MDRV_HVSP_SRC_DRAM)) ||\ ++ (enHVSP_ID == E_MDRV_HVSP_ID_2 && enSrcType != E_MDRV_HVSP_SRC_HVSP) ||\ ++ (enHVSP_ID == E_MDRV_HVSP_ID_3 && enSrcType != E_MDRV_HVSP_SRC_DRAM)) ++#define Is_PTGEN_FHD(u16Htotal,u16Vtotal,u16Vfrequency) ((u16Htotal) == 2200 && (u16Vtotal) == 1125 && (u16Vfrequency) == 30) ++#define Is_PTGEN_HD(u16Htotal,u16Vtotal,u16Vfrequency) ((u16Htotal) == 1344 && (u16Vtotal) == 806 && (u16Vfrequency) == 60) ++#define Is_PTGEN_SD(u16Htotal,u16Vtotal,u16Vfrequency) ((u16Htotal) == 800 && (u16Vtotal) == 525 && (u16Vfrequency) == 60) ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ST_MDRV_HVSP_SCALING_CONFIG gstHvspScalingCfg; ++ST_MDRV_HVSP_POSTCROP_CONFIG gstHvspPostCropCfg; ++///////////////// ++/// gbMemReadyForMdrv ++/// if True ,DNR buffer was allocated. ++//////////////// ++unsigned char gbMemReadyForMdrv; ++unsigned char gu8IPMBufferNum; ++ST_DRV_HVSP_PAT_TGEN_CONFIG gstPatTgenCfg[E_MDRV_HVSP_PAT_TGEN_TIMING_MAX] = ++{ ++ {1125, 4, 5, 36, 1080, 2200, 88, 44, 148, 1920}, // 1920_1080_30 ++ { 806, 3, 6, 29, 768, 1344, 24, 136, 160, 1024}, // 1024_768_60 ++ { 525, 33, 2, 10, 480, 800, 16, 96, 48, 640}, // 640_480_60 ++ { 0, 20, 10, 20, 0, 0, 30, 15, 30, 0}, // undefined ++}; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++unsigned char MDrv_HVSP_GetCMDQDoneStatus(void) ++{ ++ return Drv_HVSP_GetCMDQDoneStatus(); ++} ++ ++wait_queue_head_t * MDrv_HVSP_GetWaitQueueHead(void) ++{ ++ return Drv_HVSP_GetWaitQueueHead(); ++} ++void MDrv_HVSP_SetPollWait ++ (void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ MsOS_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++} ++unsigned char MDrv_HVSP_Suspend(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_HVSP_SUSPEND_RESUME_CONFIG stSuspendResumeCfg; ++ unsigned char bRet = TRUE;; ++ ++ stSuspendResumeCfg.u32IRQNUM = pCfg->u32IRQNum; ++ stSuspendResumeCfg.u32CMDQIRQNUM = pCfg->u32CMDQIRQNum; ++ if(Drv_HVSP_Suspend(&stSuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP]%s Suspend Fail\n", __FUNCTION__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++ ++unsigned char MDrv_HVSP_Resume(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_HVSP_SUSPEND_RESUME_CONFIG stSuspendResumeCfg; ++ unsigned char bRet = TRUE;; ++ ++ stSuspendResumeCfg.u32IRQNUM = pCfg->u32IRQNum; ++ stSuspendResumeCfg.u32CMDQIRQNUM = pCfg->u32CMDQIRQNum; ++ if(Drv_HVSP_Resume(&stSuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP]%s Resume Fail\n", __FUNCTION__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++void MDrv_HVSP_Release(EN_MDRV_HVSP_ID_TYPE enHVSP_ID) ++{ ++ EN_HVSP_ID_TYPE enID; ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ Drv_HVSP_Release(enID); ++} ++ ++unsigned char MDrv_HVSP_Init(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_INIT_CONFIG *pCfg) ++{ ++ ST_HVSP_INIT_CONFIG stInitCfg; ++ static unsigned char bInit = FALSE; ++ ++ stInitCfg.u32RIUBase = pCfg->u32Riubase; ++ stInitCfg.u32IRQNUM = pCfg ->u32IRQNUM; ++ stInitCfg.u32CMDQIRQNUM = pCfg ->u32CMDQIRQNUM; ++ gu8IPMBufferNum = DNRBufferMode; ++ Drv_HVSP_SetBufferNum(gu8IPMBufferNum); ++ if(Drv_HVSP_Init(&stInitCfg) == FALSE) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP]%s Init Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ else ++ { ++ if(bInit == FALSE) ++ { ++ MsOS_Memset(&gstHvspScalingCfg, 0, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ MsOS_Memset(&gstHvspPostCropCfg, 0, sizeof(ST_MDRV_HVSP_POSTCROP_CONFIG)); ++ } ++ bInit = TRUE; ++ ++ return TRUE; ++ } ++ ++} ++void MDrv_HVSP_SetMemoryAllocateReady(unsigned char bEn) ++{ ++ gbMemReadyForMdrv = bEn; ++ Drv_HVSP_SetMemoryAllocateReady(gbMemReadyForMdrv); ++} ++ST_HVSP_IPM_CONFIG _MDrv_HVSP_FillIPMStruct(ST_MDRV_HVSP_IPM_CONFIG *pCfg) ++{ ++ ST_HVSP_IPM_CONFIG stIPMCfg; ++ stIPMCfg.u16Fetch = pCfg->u16Width; ++ stIPMCfg.u16Vsize = pCfg->u16Height; ++ stIPMCfg.bRead = (pCfg->enRW)&0x01; ++ stIPMCfg.bWrite = ((pCfg->enRW)>>1)&0x01; ++ stIPMCfg.u32BaseAddr = pCfg->u32PhyAddr; ++ stIPMCfg.u32MemSize = pCfg->u32MemSize; ++ return stIPMCfg; ++} ++ ++ST_HVSP_LDC_FRAMEBUFFER_CONFIG _MDrv_HVSP_FillLDCStruct(ST_MDRV_HVSP_IPM_CONFIG *pCfg, MS_BOOL bWrite) ++{ ++ ST_HVSP_LDC_FRAMEBUFFER_CONFIG stLDCCfg; ++ stLDCCfg.bEnSWMode = 0x00; ++ stLDCCfg.u16Height = pCfg->u16Height; ++ stLDCCfg.u16Width = pCfg->u16Width; ++ stLDCCfg.u32FBaddr = pCfg->u32PhyAddr; ++ stLDCCfg.u8FBidx = 0x00; ++ stLDCCfg.u8FBrwdiff = SCL_DELAY2FRAMEINDOUBLEBUFFERMode ? 0x0 : 0x1; ++ // delay 1 frame, set 1 is true, because Frame_buffer_idx = hw_w_idx - reg_ldc_fb_hw_rw_diff ++ // So ,if want delay 2 frame, need to set '0' for 2 DNR buffer. ++ //if only 1 DNR buffer , set '0' also delay 1 frame. ++ stLDCCfg.bEnDNR = bWrite; ++ return stLDCCfg; ++} ++unsigned char MDrv_HVSP_SetInitIPMConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_IPM_CONFIG *pCfg) ++{ ++ ST_HVSP_IPM_CONFIG stIPMCfg; ++ ST_HVSP_LDC_FRAMEBUFFER_CONFIG stLDCCfg; ++ if(enHVSP_ID != E_MDRV_HVSP_ID_1) ++ { ++ SCL_ERR( "[HVSP]%s ID not correct: %d\n", __FUNCTION__, enHVSP_ID); ++ return FALSE; ++ } ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s:%d:PhyAddr=%lx, width=%x, height=%x \n", __FUNCTION__,enHVSP_ID, pCfg->u32PhyAddr, pCfg->u16Width, pCfg->u16Height); ++ stIPMCfg = _MDrv_HVSP_FillIPMStruct(pCfg); ++ stLDCCfg = _MDrv_HVSP_FillLDCStruct(pCfg, stIPMCfg.bWrite); ++ Drv_HVSP_SetLDCFrameBuffer_Config(stLDCCfg); ++ if(Drv_HVSP_Set_IPM_Config(stIPMCfg) == FALSE) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP] Set IPM Config Fail\n"); ++ return FALSE; ++ } ++ else ++ { ++ return TRUE;; ++ } ++} ++ ++ ++EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE _MDrv_HVSP_GetPatTGenTiming(ST_MDRV_HVSPTIMING_CONFIG *pTiming) ++{ ++ EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE enTiming; ++ ++ if(Is_PTGEN_FHD(pTiming->u16Htotal,pTiming->u16Vtotal,pTiming->u16Vfrequency)) ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30; ++ } ++ else if(Is_PTGEN_HD(pTiming->u16Htotal,pTiming->u16Vtotal,pTiming->u16Vfrequency)) ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60; ++ } ++ else if(Is_PTGEN_SD(pTiming->u16Htotal,pTiming->u16Vtotal,pTiming->u16Vfrequency)) ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60; ++ } ++ else ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED; ++ } ++ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "[HVSP]%s(%d) Timing:%s(%d)", __FUNCTION__, __LINE__, PARSING_PAT_TGEN_TIMING(enTiming), enTiming); ++ return enTiming; ++} ++ ++//--------------------------------------------------------------------------------------------------------- ++// IOCTL function ++//--------------------------------------------------------------------------------------------------------- ++MS_BOOL _MDrv_HVSP_IsInputSrcPatternGen(EN_HVSP_IP_MUX_TYPE enIPMux, ST_MDRV_HVSP_INPUT_CONFIG *pCfg) ++{ ++ if(enIPMux == E_HVSP_IP_MUX_PAT_TGEN) ++ { ++ EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE enPatTgenTiming; ++ ST_DRV_HVSP_PAT_TGEN_CONFIG stPatTgenCfg; ++ ++ enPatTgenTiming = _MDrv_HVSP_GetPatTGenTiming(&pCfg->stTimingCfg); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:%d type:%d\n", __FUNCTION__,E_MDRV_HVSP_ID_1,enPatTgenTiming); ++ MsOS_Memcpy(&stPatTgenCfg, &gstPatTgenCfg[enPatTgenTiming],sizeof(ST_DRV_HVSP_PAT_TGEN_CONFIG)); ++ if(enPatTgenTiming == E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED) ++ { ++ stPatTgenCfg.u16HActive = pCfg->stCaptureWin.u16Width; ++ stPatTgenCfg.u16VActive = pCfg->stCaptureWin.u16Height; ++ stPatTgenCfg.u16Htt = stPatTgenCfg.u16HActive + ++ stPatTgenCfg.u16HBackPorch + ++ stPatTgenCfg.u16HFrontPorch + ++ stPatTgenCfg.u16HSyncWidth; ++ ++ stPatTgenCfg.u16Vtt = stPatTgenCfg.u16VActive + ++ stPatTgenCfg.u16VBackPorch + ++ stPatTgenCfg.u16VFrontPorch + ++ stPatTgenCfg.u16VSyncWidth; ++ ++ } ++ return (unsigned char)Drv_HVSP_SetPatTgen(TRUE, &stPatTgenCfg); ++ } ++ else ++ { ++ return 0; ++ } ++} ++void MDrv_HVSP_SetPatTgenStatus(unsigned char bEn) ++{ ++ Drv_HVSP_SetPatTgen(bEn, NULL); ++} ++unsigned char MDrv_HVSP_SetInputConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_INPUT_CONFIG *pCfg) ++{ ++ unsigned char Ret = TRUE; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s:%d\n", __FUNCTION__,enHVSP_ID); ++ ++ //SCL_ERR("clk1:%d, clk2:%d\n",(int)pCfg->stclk->idclk,(int)pCfg->stclk->fclk1); ++ ++ if(Is_Wrong_Type(enHVSP_ID,pCfg->enSrcType)) ++ { ++ SCL_ERR( "[HVSP] Wrong Input Type: %d, %d\n", enHVSP_ID, pCfg->enSrcType); ++ return FALSE; ++ } ++ if(enHVSP_ID == E_MDRV_HVSP_ID_1) ++ { ++ EN_HVSP_IP_MUX_TYPE enIPMux; ++ enIPMux = pCfg->enSrcType == E_MDRV_HVSP_SRC_ISP ? E_HVSP_IP_MUX_ISP : ++ pCfg->enSrcType == E_MDRV_HVSP_SRC_BT656 ? E_HVSP_IP_MUX_BT656 : ++ pCfg->enSrcType == E_MDRV_HVSP_SRC_HVSP ? E_HVSP_IP_MUX_HVSP : ++ pCfg->enSrcType == E_MDRV_HVSP_SRC_PAT_TGEN ? E_HVSP_IP_MUX_PAT_TGEN : ++ E_HVSP_IP_MUX_MAX; ++ Ret &= (unsigned char)Drv_HVSP_SetInputMux(enIPMux,(ST_HVSP_CLK_CONFIG *)pCfg->stclk); ++ Drv_HVSP_SetInputSrcSize(pCfg->stCaptureWin.u16Height,pCfg->stCaptureWin.u16Width); ++ Drv_HVSP_SetCropWindowSize(); ++ if(_MDrv_HVSP_IsInputSrcPatternGen(enIPMux, pCfg)) ++ { ++ Ret &= TRUE; ++ } ++ else ++ { ++ Ret &= (unsigned char)Drv_HVSP_SetPatTgen(FALSE, NULL); ++ } ++ ++ } ++ return Ret; ++} ++ ++unsigned char MDrv_HVSP_SetPostCropConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_POSTCROP_CONFIG *pCfg) ++{ ++ EN_HVSP_ID_TYPE enID; ++ ST_HVSP_SCALING_CONFIG stScalingCfg; ++ unsigned char ret; ++ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s\n", __FUNCTION__); ++ ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ MsOS_Memcpy(&gstHvspPostCropCfg, pCfg, sizeof(ST_MDRV_HVSP_POSTCROP_CONFIG)); ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_1] = 0; ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_2] = pCfg->bCropEn; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_2] = pCfg->u16X; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_2] = pCfg->u16Y; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_2] = pCfg->u16Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_2] = pCfg->u16Height; ++ ++ stScalingCfg.u16Src_Width = gstHvspScalingCfg.u16Src_Width; ++ stScalingCfg.u16Src_Height = gstHvspScalingCfg.u16Src_Height; ++ stScalingCfg.u16Dsp_Width = gstHvspScalingCfg.u16Dsp_Width; ++ stScalingCfg.u16Dsp_Height = gstHvspScalingCfg.u16Dsp_Height; ++ ++ if(pCfg->bFmCntEn) ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_CMDQ_FRMCNT; ++ stScalingCfg.stCmdTrigCfg.u8Fmcnt = pCfg->u8FmCnt; ++ } ++ else ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_NONE; //ToDo ++ stScalingCfg.stCmdTrigCfg.u8Fmcnt = 0; ++ } ++ ++ ret = (unsigned char)Drv_HVSP_SetScaling(enID, stScalingCfg,(ST_HVSP_CLK_CONFIG *)pCfg->stclk); ++ return ret; ++ ++ ++} ++ ++unsigned char MDrv_HVSP_SetScalingConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SCALING_CONFIG *pCfg ) ++{ ++ EN_HVSP_ID_TYPE enID; ++ ST_HVSP_SCALING_CONFIG stScalingCfg; ++ unsigned char ret; ++ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s:%d\n", __FUNCTION__,enHVSP_ID); ++ ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ MsOS_Memcpy(&gstHvspScalingCfg, pCfg, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_1] = 0; ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_2] = pCfg->stCropWin.bEn; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16X; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Y; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Height; ++ ++ stScalingCfg.u16Src_Width = pCfg->u16Src_Width; ++ stScalingCfg.u16Src_Height = pCfg->u16Src_Height; ++ stScalingCfg.u16Dsp_Width = pCfg->u16Dsp_Width; ++ stScalingCfg.u16Dsp_Height = pCfg->u16Dsp_Height; ++ if(enHVSP_ID==E_MDRV_HVSP_ID_1 || enHVSP_ID==E_MDRV_HVSP_ID_2) ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_CMDQ_LDC_SYNC; //ToDo ++ } ++ else if(enHVSP_ID==E_MDRV_HVSP_ID_3) ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_NONE; //ToDo ++ } ++ else ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_POLL_LDC_SYNC; //ToDo ++ } ++ stScalingCfg.stCmdTrigCfg.u8Fmcnt = 0; ++ ++ ret = (unsigned char)Drv_HVSP_SetScaling(enID, stScalingCfg,(ST_HVSP_CLK_CONFIG *)pCfg->stclk); ++ return ret; ++} ++ ++ ++ ++static void _MDrv_HVSP_SetRegisterForce(MS_U32 u32Size, MS_U8 *pBuf) ++{ ++ MS_U32 i; ++ MS_U32 u32Reg; ++ MS_U16 u16Bank; ++ MS_U8 u8Addr, u8Val, u8Msk; ++ ++ // bank, addrr, val, msk ++ for(i=0; iu32Size, GFP_KERNEL); ++ ++ if(pBuf == NULL) ++ { ++ SCL_ERR( "[HVSP1] allocate buffer fail\n"); ++ return 0; ++ } ++ ++ ++ if(copy_from_user(pBuf, (ST_MDRV_HVSP_MISC_CONFIG __user *)pCfg->u32Addr, pCfg->u32Size)) ++ { ++ SCL_ERR( "[HVSP1] copy msic buffer error\n"); ++ MsOS_MemFree(pBuf); ++ return 0; ++ } ++ ++ switch(pCfg->u8Cmd) ++ { ++ case E_MDRV_HVSP_MISC_CMD_SET_REG: ++ _MDrv_HVSP_SetRegisterForce(pCfg->u32Size, pBuf); ++ break; ++ ++ default: ++ break; ++ } ++ ++ MsOS_MemFree(pBuf); ++ ++ return 1; ++} ++ ++unsigned char MDrv_HVSP_SetMiscConfigForKernel(ST_MDRV_HVSP_MISC_CONFIG *pCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "%s\n", __FUNCTION__); ++ switch(pCfg->u8Cmd) ++ { ++ case E_MDRV_HVSP_MISC_CMD_SET_REG: ++ _MDrv_HVSP_SetRegisterForce(pCfg->u32Size, (MS_U8 *)pCfg->u32Addr); ++ break; ++ ++ default: ++ break; ++ } ++ return 1; ++} ++ ++unsigned char MDrv_HVSP_GetSCLInform(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SCINFORM_CONFIG *pstCfg) ++{ ++ ST_DRV_HVSP_SCINFORM_CONFIG stInformCfg; ++ EN_HVSP_ID_TYPE enID; ++ unsigned char bRet = 1; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP1]%s\n", __FUNCTION__); ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ Drv_HVSP_GetSCLInform(enID, &stInformCfg); ++ MsOS_Memcpy(pstCfg, &stInformCfg, sizeof(ST_MDRV_HVSP_SCINFORM_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[HVSP1]u16Height:%hd u16Width:%hd\n",stInformCfg.u16Height, stInformCfg.u16Width); ++ return bRet; ++} ++ ++unsigned char MDrv_HVSP_SetOSDConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_OSD_CONFIG* pstCfg) ++{ ++ unsigned char Ret = TRUE; ++ ST_DRV_HVSP_OSD_CONFIG stOSdCfg; ++ EN_HVSP_ID_TYPE enID; ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ MsOS_Memcpy(pstCfg, &stOSdCfg, sizeof(ST_MDRV_HVSP_OSD_CONFIG)); ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enID)), ++ "%s::ID:%d, OnOff:%hhd ,Bypass:%hhd\n", ++ __FUNCTION__,enID,stOSdCfg.stOsdOnOff.bOSDEn,stOSdCfg.stOsdOnOff.bOSDBypass); ++ return Ret; ++} ++ ++unsigned char Mdrv_HVSP_GetDNRBufferInformation(void) ++{ ++ return gu8IPMBufferNum; ++} ++ ++unsigned char MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_TYPE enSet) ++{ ++ unsigned char Ret = TRUE; ++ ST_DRV_HVSP_SET_FB_MANAGE_CONFIG stCfg; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "%s\n", __FUNCTION__); ++ stCfg.enSet = enSet; ++ if (stCfg.enSet & EN_DRV_HVSP_FBMG_SET_DNR_COMDE_ON) ++ { ++ SCL_ERR( "COMDE_ON\n"); ++ MDrv_VIP_SetDNRConpressForDebug(1); ++ } ++ else if (stCfg.enSet & EN_DRV_HVSP_FBMG_SET_DNR_COMDE_OFF) ++ { ++ SCL_ERR( "COMDE_OFF\n"); ++ MDrv_VIP_SetDNRConpressForDebug(0); ++ } ++ else if (stCfg.enSet & EN_DRV_HVSP_FBMG_SET_DNR_COMDE_265OFF) ++ { ++ SCL_ERR( "COMDE_265OFF\n"); ++ MDrv_VIP_SetDNRConpressForDebug(0); ++ } ++ if(stCfg.enSet &EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_1) ++ { ++ gu8IPMBufferNum = 1; ++ Drv_HVSP_SetBufferNum(gu8IPMBufferNum); ++ } ++ else if (stCfg.enSet &EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_2) ++ { ++ gu8IPMBufferNum = 2; ++ Drv_HVSP_SetBufferNum(gu8IPMBufferNum); ++ } ++ Drv_HVSP_SetFbManageConfig(stCfg); ++ return Ret; ++} ++void MDrv_HVSP_IDCLKRelease(ST_MDRV_HVSP_CLK_CONFIG* stclk) ++{ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "%s\n", __FUNCTION__); ++ Drv_HVSP_IDCLKRelease((ST_HVSP_CLK_CONFIG *)stclk); ++} ++ ++unsigned long MDrv_HVSP_HWMonitor(unsigned char u8flag) ++{ ++ if(u8flag == EN_MDRV_HVSP_MONITOR_CROPCHECK) ++ { ++ return Drv_HVSP_CropCheck(); ++ } ++ else if(u8flag >= EN_MDRV_HVSP_MONITOR_DMA1FRMCHECK) ++ { ++ return Drv_HVSP_DMACheck(u8flag); ++ } ++ return 0; ++} ++ ++ ++unsigned char MDrv_HVSP_InputVSyncMonitor(void) ++{ ++ if(Drv_HVSP_CheckInputVSync()) ++ { ++ return 1; ++ } ++ else ++ { ++ return 0; ++ } ++} ++#if 1 ++void MDrv_HVSP_SetCLKForcemode(unsigned char bEn) ++{ ++ Drv_HVSP_SetCLKForcemode(bEn); ++} ++void MDrv_HVSP_SetCLKRate(void* adjclk,unsigned char u8Idx) ++{ ++ MSOS_ST_CLK* pstclock = NULL; ++ Drv_HVSP_SetCLKRate(u8Idx); ++ if (__clk_get_enable_count((MSOS_ST_CLK*)adjclk)==0) ++ { ++ } ++ else ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index((MSOS_ST_CLK*)adjclk, (u8Idx &0x0F)))) ++ { ++ clk_set_parent((MSOS_ST_CLK*)adjclk, pstclock); ++ } ++ } ++} ++void MDrv_HVSP_SetCLKOnOff(void* adjclk,unsigned char bEn) ++{ ++ MSOS_ST_CLK* pstclock = NULL; ++ if (__clk_get_enable_count((MSOS_ST_CLK*)adjclk)==0 &&bEn) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index((MSOS_ST_CLK*)adjclk, 0))) ++ { ++ clk_set_parent((MSOS_ST_CLK*)adjclk, pstclock); ++ clk_prepare_enable((MSOS_ST_CLK*)adjclk); ++ } ++ } ++ else if(__clk_get_enable_count((MSOS_ST_CLK*)adjclk)!=0 && !bEn) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index((MSOS_ST_CLK*)adjclk, 0))) ++ { ++ clk_set_parent((MSOS_ST_CLK*)adjclk, pstclock); ++ clk_disable_unprepare((MSOS_ST_CLK*)adjclk); ++ } ++ } ++} ++ssize_t MDrv_HVSP_monitorHWShow(char *buf,int VsyncCount ,int MonitorErrCount) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "========================SCL monitor HW BUTTON======================\n"); ++ str += scnprintf(str, end - str, "CROP Monitor :1\n"); ++ str += scnprintf(str, end - str, "DMA1FRM Monitor :2\n"); ++ str += scnprintf(str, end - str, "DMA1SNP Monitor :3\n"); ++ str += scnprintf(str, end - str, "DMA2FRM Monitor :4\n"); ++ str += scnprintf(str, end - str, "DMA3FRM Monitor :5\n"); ++ str += scnprintf(str, end - str, "========================SCL monitor HW ======================\n"); ++ str += scnprintf(str, end - str, "vysnc count:%d",VsyncCount); ++ str += scnprintf(str, end - str, "Monitor Err count:%d\n",MonitorErrCount); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_DbgmgFlagShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "========================SCL Debug Message BUTTON======================\n"); ++ str += scnprintf(str, end - str, "CONFIG ECHO STATUS\n"); ++ str += scnprintf(str, end - str, "MDRV_CONFIG (1) 0x%x\n",gbdbgmessage[EN_DBGMG_MDRV_CONFIG]); ++ str += scnprintf(str, end - str, "IOCTL_CONFIG (2) 0x%x\n",gbdbgmessage[EN_DBGMG_IOCTL_CONFIG]); ++ str += scnprintf(str, end - str, "HVSP_CONFIG (3) 0x%x\n",gbdbgmessage[EN_DBGMG_HVSP_CONFIG]); ++ str += scnprintf(str, end - str, "SCLDMA_CONFIG (4) 0x%x\n",gbdbgmessage[EN_DBGMG_SCLDMA_CONFIG]); ++ str += scnprintf(str, end - str, "PNL_CONFIG (5) 0x%x\n",gbdbgmessage[EN_DBGMG_PNL_CONFIG]); ++ str += scnprintf(str, end - str, "VIP_CONFIG (6) 0x%x\n",gbdbgmessage[EN_DBGMG_VIP_CONFIG]); ++ str += scnprintf(str, end - str, "DRVPQ_CONFIG (7) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVPQ_CONFIG]); ++ str += scnprintf(str, end - str, "INST_ENTRY_CONFIG (8) 0x%x\n",gbdbgmessage[EN_DBGMG_INST_ENTRY_CONFIG]); ++ str += scnprintf(str, end - str, "INST_LOCK_CONFIG (9) 0x%x\n",gbdbgmessage[EN_DBGMG_INST_LOCK_CONFIG]); ++ str += scnprintf(str, end - str, "INST_FUNC_CONFIG (A) 0x%x\n",gbdbgmessage[EN_DBGMG_INST_FUNC_CONFIG]); ++ str += scnprintf(str, end - str, "DRVHVSP_CONFIG (B) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVHVSP_CONFIG]); ++ str += scnprintf(str, end - str, "DRVSCLDMA_CONFIG (C) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVSCLDMA_CONFIG]); ++ str += scnprintf(str, end - str, "DRVSCLIRQ_CONFIG (D) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVSCLIRQ_CONFIG]); ++ str += scnprintf(str, end - str, "DRVCMDQ_CONFIG (E) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVCMDQ_CONFIG]); ++ str += scnprintf(str, end - str, "DRVVIP_CONFIG (F) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVVIP_CONFIG]); ++ str += scnprintf(str, end - str, "PRIORITY_CONFIG (G) 0x%x\n",gbdbgmessage[EN_DBGMG_PRIORITY_CONFIG]); ++ str += scnprintf(str, end - str, "ALL Reset (0)\n"); ++ str += scnprintf(str, end - str, "========================SCL Debug Message BUTTON======================\n"); ++ str += scnprintf(str, end - str, "========================SCL Debug Message LEVEL======================\n"); ++ str += scnprintf(str, end - str, "default is level 1\n"); ++ str += scnprintf(str, end - str, "-------------------------------IOCTL LEVEL---------------------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : SC1\n"); ++ str += scnprintf(str, end - str, "0x 2 : SC2\n"); ++ str += scnprintf(str, end - str, "0x 4 : SC3\n"); ++ str += scnprintf(str, end - str, "0x 8 : VIP\n"); ++ str += scnprintf(str, end - str, "0x10 : SC1HLEVEL\n"); ++ str += scnprintf(str, end - str, "0x20 : SC2HLEVEL\n"); ++ str += scnprintf(str, end - str, "0x40 : ELSE\n"); ++ str += scnprintf(str, end - str, "-------------------------------HVSP LEVEL---------------------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : HVSP1\n"); ++ str += scnprintf(str, end - str, "0x 2 : HVSP2\n"); ++ str += scnprintf(str, end - str, "0x 4 : HVSP3\n"); ++ str += scnprintf(str, end - str, "0x 8 : ELSE\n"); ++ str += scnprintf(str, end - str, "-------------------------------SCLDMA LEVEL-------------------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : SC1 FRM\n"); ++ str += scnprintf(str, end - str, "0x 2 : SC1 SNP \n"); ++ str += scnprintf(str, end - str, "0x 4 : SC2 FRM\n"); ++ str += scnprintf(str, end - str, "0x 8 : SC3 FRM\n"); ++ str += scnprintf(str, end - str, "0x10 : SC1 FRM HL\n"); ++ str += scnprintf(str, end - str, "0x20 : SC1 SNP HL\n"); ++ str += scnprintf(str, end - str, "0x40 : SC2 FRM HL\n"); ++ str += scnprintf(str, end - str, "0x80 : ELSE\n"); ++ str += scnprintf(str, end - str, "-------------------------------VIP LEVEL(IOlevel)-------------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : NORMAL\n"); ++ str += scnprintf(str, end - str, "0x 2 : VIP LOG \n"); ++ str += scnprintf(str, end - str, "0x 4 : VIP SUSPEND\n"); ++ str += scnprintf(str, end - str, "0x 8 : ELSE\n"); ++ str += scnprintf(str, end - str, "------------------------------MULTI LEVEL---------------------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : SC1\n"); ++ str += scnprintf(str, end - str, "0x 2 : SC3\n"); ++ str += scnprintf(str, end - str, "0x 4 : DISP\n"); ++ str += scnprintf(str, end - str, "0x 8 : ELSE\n"); ++ str += scnprintf(str, end - str, "-------------------------------SCLIRQ LEVEL(drvlevel)---------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : NORMAL\n"); ++ str += scnprintf(str, end - str, "0x 2 : SC1RINGA \n"); ++ str += scnprintf(str, end - str, "0x 4 : SC1RINGN\n"); ++ str += scnprintf(str, end - str, "0x 8 : SC1SINGLE\n"); ++ str += scnprintf(str, end - str, "0x10 : SC2RINGA\n"); ++ str += scnprintf(str, end - str, "0x20 : SC2RINGN \n"); ++ str += scnprintf(str, end - str, "0x40 : SC3SINGLE\n"); ++ str += scnprintf(str, end - str, "0x80 : ELSE\n"); ++ str += scnprintf(str, end - str, "-------------------------------CMDQ LEVEL(drvlevel)-----------------\n"); ++ str += scnprintf(str, end - str, "0x 1 : LOW\n"); ++ str += scnprintf(str, end - str, "0x 2 : NORMAL \n"); ++ str += scnprintf(str, end - str, "0x 4 : HIGH\n"); ++ str += scnprintf(str, end - str, "0x 8 : ISR\n"); ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "========================SCL Debug Message LEVEL======================\n"); ++ return (str - buf); ++} ++ ++ssize_t MDrv_HVSP_ProcShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvspformCfg; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvsp2formCfg; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvsp3formCfg; ++ ST_DRV_HVSP_SCINFORM_CONFIG stzoomformCfg; ++ ST_HVSP_IPM_CONFIG stIpmformCfg; ++ ST_DRV_HVSP_INPUTINFORM_CONFIG stInformCfg; ++ unsigned char bLDC; ++ ST_DRV_HVSP_OSD_CONFIG stOsdCfg; ++ Drv_HVSP_GetCrop12Inform(&stInformCfg); ++ Drv_HVSP_GetSCLInform(E_HVSP_ID_1,&stzoomformCfg); ++ Drv_HVSP_GetHVSPAttribute(E_HVSP_ID_1,&sthvspformCfg); ++ Drv_HVSP_GetHVSPAttribute(E_HVSP_ID_2,&sthvsp2formCfg); ++ Drv_HVSP_GetHVSPAttribute(E_HVSP_ID_3,&sthvsp3formCfg); ++ Drv_HVSP_GetOSDAttribute(E_HVSP_ID_1,&stOsdCfg); ++ bLDC = Drv_HVSP_GetFrameBufferAttribute(E_HVSP_ID_1,&stIpmformCfg); ++ str += scnprintf(str, end - str, "========================SCL PROC FRAMEWORK======================\n"); ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "------------------------SCL INPUT MUX----------------------\n"); ++ if(stInformCfg.enMux==0) ++ { ++ str += scnprintf(str, end - str, "Input SRC :BT656\n"); ++ } ++ else if(stInformCfg.enMux==1) ++ { ++ str += scnprintf(str, end - str, "Input SRC :ISP\n"); ++ } ++ else if(stInformCfg.enMux==3) ++ { ++ str += scnprintf(str, end - str, "Input SRC :PTGEN\n"); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "Input SRC :OTHER\n"); ++ } ++ str += scnprintf(str, end - str, "Input H :%hd\n",stInformCfg.u16inWidth); ++ str += scnprintf(str, end - str, "Input V :%hd\n",stInformCfg.u16inHeight); ++ str += scnprintf(str, end - str, "Receive H :%hd\n",stInformCfg.u16inWidthcount); ++ str += scnprintf(str, end - str, "Receive V :%hd\n",stInformCfg.u16inHeightcount); ++ str += scnprintf(str, end - str, "------------------------SCL FB-----------------------------\n"); ++ str += scnprintf(str, end - str, "FB H :%hd\n",stIpmformCfg.u16Fetch); ++ str += scnprintf(str, end - str, "FB V :%hd\n",stIpmformCfg.u16Vsize); ++ str += scnprintf(str, end - str, "FB Addr :%lx\n",stIpmformCfg.u32BaseAddr); ++ str += scnprintf(str, end - str, "FB memsize :%ld\n",stIpmformCfg.u32MemSize); ++ str += scnprintf(str, end - str, "FB Buffer :%hhd\n",gu8IPMBufferNum); ++ str += scnprintf(str, end - str, "FB Write :%hhd\n",stIpmformCfg.bWrite); ++ if(bLDC) ++ { ++ str += scnprintf(str, end - str, "READ PATH :LDC\n"); ++ } ++ else if(stIpmformCfg.bRead) ++ { ++ str += scnprintf(str, end - str, "READ PATH :DNR\n"); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "READ PATH :NONE\n"); ++ } ++ str += scnprintf(str, end - str, "------------------------SCL Zoom----------------------------\n"); ++ str += scnprintf(str, end - str, "Zoom :%hhd\n",stzoomformCfg.bEn); ++ str += scnprintf(str, end - str, "ZoomX :%hd\n",stzoomformCfg.u16X); ++ str += scnprintf(str, end - str, "ZoomY :%hd\n",stzoomformCfg.u16Y); ++ str += scnprintf(str, end - str, "ZoomOutW :%hd\n",stzoomformCfg.u16crop2OutWidth); ++ str += scnprintf(str, end - str, "ZoomOutH :%hd\n",stzoomformCfg.u16crop2OutHeight); ++ str += scnprintf(str, end - str, "SrcW :%hd\n",stzoomformCfg.u16crop2inWidth); ++ str += scnprintf(str, end - str, "SrcH :%hd\n",stzoomformCfg.u16crop2inHeight); ++ str += scnprintf(str, end - str, "------------------------SCL OSD----------------------------\n"); ++ str += scnprintf(str, end - str, "ONOFF :%hhd\n",stOsdCfg.stOsdOnOff.bOSDEn); ++ if(stOsdCfg.enOSD_loc) ++ { ++ str += scnprintf(str, end - str, "Locate: Before\n"); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "Locate: After\n"); ++ } ++ str += scnprintf(str, end - str, "------------------------SCL HVSP1----------------------------\n"); ++ str += scnprintf(str, end - str, "InputH :%hd\n",sthvspformCfg.u16inWidth); ++ str += scnprintf(str, end - str, "InputV :%hd\n",sthvspformCfg.u16inHeight); ++ str += scnprintf(str, end - str, "OutputH :%hd\n",sthvspformCfg.u16Width); ++ str += scnprintf(str, end - str, "OutputV :%hd\n",sthvspformCfg.u16Height); ++ str += scnprintf(str, end - str, "function :%hhd\n",sthvspformCfg.bEn); ++ str += scnprintf(str, end - str, "------------------------SCL HVSP2----------------------------\n"); ++ str += scnprintf(str, end - str, "InputH :%hd\n",sthvsp2formCfg.u16inWidth); ++ str += scnprintf(str, end - str, "InputV :%hd\n",sthvsp2formCfg.u16inHeight); ++ str += scnprintf(str, end - str, "OutputH :%hd\n",sthvsp2formCfg.u16Width); ++ str += scnprintf(str, end - str, "OutputV :%hd\n",sthvsp2formCfg.u16Height); ++ str += scnprintf(str, end - str, "function :%hhd\n",sthvsp2formCfg.bEn); ++ str += scnprintf(str, end - str, "------------------------SCL HVSP3----------------------------\n"); ++ str += scnprintf(str, end - str, "InputH :%hd\n",sthvsp3formCfg.u16inWidth); ++ str += scnprintf(str, end - str, "InputV :%hd\n",sthvsp3formCfg.u16inHeight); ++ str += scnprintf(str, end - str, "OutputH :%hd\n",sthvsp3formCfg.u16Width); ++ str += scnprintf(str, end - str, "OutputV :%hd\n",sthvsp3formCfg.u16Height); ++ str += scnprintf(str, end - str, "function :%hhd\n",sthvsp3formCfg.bEn); ++ str += scnprintf(str, end - str, "\n"); ++ str += scnprintf(str, end - str, "========================SCL PROC FRAMEWORK======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_ClkFrameworkShow(char *buf,ST_MDRV_HVSP_CLK_CONFIG* stclk) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "========================SCL CLK FRAMEWORK======================\n"); ++ str += scnprintf(str, end - str, "echo 1 > clk :open force mode\n"); ++ str += scnprintf(str, end - str, "echo 0 > clk :close force mode\n"); ++ str += scnprintf(str, end - str, "echo 2 > clk :fclk1 max\n"); ++ str += scnprintf(str, end - str, "echo 3 > clk :fclk1 med\n"); ++ str += scnprintf(str, end - str, "echo 4 > clk :fclk1 open\n"); ++ str += scnprintf(str, end - str, "echo 5 > clk :fclk1 close\n"); ++ str += scnprintf(str, end - str, "echo 6 > clk :fclk2 max\n"); ++ str += scnprintf(str, end - str, "echo 7 > clk :fclk2 med\n"); ++ str += scnprintf(str, end - str, "echo 8 > clk :fclk2 open\n"); ++ str += scnprintf(str, end - str, "echo 9 > clk :fclk2 close\n"); ++ str += scnprintf(str, end - str, "echo : > clk :idclk ISP\n"); ++ str += scnprintf(str, end - str, "echo D > clk :idclk BT656\n"); ++ str += scnprintf(str, end - str, "echo B > clk :idclk open\n"); ++ str += scnprintf(str, end - str, "echo = > clk :idclk close\n"); ++ str += scnprintf(str, end - str, "echo C > clk :odclk MAX\n"); ++ str += scnprintf(str, end - str, "echo ? > clk :odclk LPLL\n"); ++ str += scnprintf(str, end - str, "echo @ > clk :odclk open\n"); ++ str += scnprintf(str, end - str, "echo A > clk :odclk close\n"); ++ str += scnprintf(str, end - str, "========================SCL CLK STATUS======================\n"); ++ str += scnprintf(str, end - str, "force mode :%hhd\n",Drv_HVSP_GetCLKForcemode()); ++ if(__clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk1)) ++ { ++ str += scnprintf(str, end - str, "fclk1 open :%d ,%ld\n", ++ __clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk1),__clk_get_rate((MSOS_ST_CLK*)stclk->fclk1)); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "fclk1 close\n"); ++ } ++ if(__clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk2)) ++ { ++ str += scnprintf(str, end - str, "fclk2 open :%d,%ld\n", ++ __clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk2),__clk_get_rate((MSOS_ST_CLK*)stclk->fclk2)); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "fclk2 close\n"); ++ } ++ if(__clk_get_enable_count((MSOS_ST_CLK*)stclk->idclk)) ++ { ++ if(__clk_get_rate((MSOS_ST_CLK*)stclk->idclk) > 10) ++ { ++ str += scnprintf(str, end - str, "idclk open :ISP\n"); ++ } ++ else if(__clk_get_rate((MSOS_ST_CLK*)stclk->idclk) == 1) ++ { ++ str += scnprintf(str, end - str, "idclk open :BT656\n"); ++ } ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "idclk close\n"); ++ } ++ if(__clk_get_enable_count((MSOS_ST_CLK*)stclk->odclk)) ++ { ++ if(__clk_get_rate((MSOS_ST_CLK*)stclk->odclk) == 432000000) ++ { ++ str += scnprintf(str, end - str, "odclk open LPLL:%ld\n",(Drv_PNL_GetLPLLDclk()/10000)*10000); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "odclk open :%ld\n",__clk_get_rate(stclk->odclk)); ++ } ++ } ++ else if(Drv_PNL_GetPnlOpen()) ++ { ++ str += scnprintf(str, end - str, "odclk manual open LPLL:%ld\n",(Drv_PNL_GetLPLLDclk()/10000)*10000); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "odclk close\n"); ++ } ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_FBMGShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "------------------------SCL FBMG----------------------------\n"); ++ str += scnprintf(str, end - str, "LDCPATH_ON :1\n"); ++ str += scnprintf(str, end - str, "LDCPATH_OFF :2\n"); ++ str += scnprintf(str, end - str, "DNRRead_ON :3\n"); ++ str += scnprintf(str, end - str, "DNRRead_OFF :4\n"); ++ str += scnprintf(str, end - str, "DNRWrite_ON :5\n"); ++ str += scnprintf(str, end - str, "DNRWrite_OFF :6\n"); ++ str += scnprintf(str, end - str, "DNRBuf1 :7\n"); ++ str += scnprintf(str, end - str, "DNRBuf2 :8\n"); ++ str += scnprintf(str, end - str, "UNLOCK :9\n"); ++ str += scnprintf(str, end - str, "------------------------SCL FBMG----------------------------\n"); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_OsdShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ST_DRV_HVSP_OSD_CONFIG stOsdCfg; ++ Drv_HVSP_GetOSDAttribute(E_HVSP_ID_1,&stOsdCfg); ++ str += scnprintf(str, end - str, "------------------------SCL OSD----------------------------\n"); ++ str += scnprintf(str, end - str, "ONOFF :%hhd\n",stOsdCfg.stOsdOnOff.bOSDEn); ++ if(stOsdCfg.enOSD_loc) ++ { ++ str += scnprintf(str, end - str, "Locate: Before\n"); ++ } ++ else ++ { ++ str += scnprintf(str, end - str, "Locate: After\n"); ++ } ++ str += scnprintf(str, end - str, "Bypass :%hhd\n",stOsdCfg.stOsdOnOff.bOSDBypass); ++ str += scnprintf(str, end - str, "WTM Bypass:%hhd\n",stOsdCfg.stOsdOnOff.bWTMBypass); ++ str += scnprintf(str, end - str, "------------------------SCL OSD----------------------------\n"); ++ str += scnprintf(str, end - str, "echo 1 > OSD :open OSD\n"); ++ str += scnprintf(str, end - str, "echo 0 > OSD :close OSD\n"); ++ str += scnprintf(str, end - str, "echo 2 > OSD :Set OSD before\n"); ++ str += scnprintf(str, end - str, "echo 3 > OSD :Set OSD After\n"); ++ str += scnprintf(str, end - str, "echo 4 > OSD :Set OSD Bypass\n"); ++ str += scnprintf(str, end - str, "echo 5 > OSD :Set OSD Bypass Off\n"); ++ str += scnprintf(str, end - str, "echo 6 > OSD :Set OSD WTM Bypass\n"); ++ str += scnprintf(str, end - str, "echo 7 > OSD :Set OSD WTM Bypass Off\n"); ++ str += scnprintf(str, end - str, "------------------------SCL OSD----------------------------\n"); ++ return (str - buf); ++} ++void MDrv_HVSP_OsdStore(const char *buf,EN_MDRV_HVSP_ID_TYPE enHVSP_ID) ++{ ++ const char *str = buf; ++ ST_DRV_HVSP_OSD_CONFIG stOSdCfg; ++ EN_HVSP_ID_TYPE enID; ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ Drv_HVSP_GetOSDAttribute(enID,&stOSdCfg); ++ if((int)*str == 49) //input 1 ++ { ++ SCL_ERR( "[OSD]open OSD %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDEn = 1; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 48) //input 0 ++ { ++ SCL_ERR( "[OSD]close OSD %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDEn = 0; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[OSD]Set OSD before %d\n",(int)*str); ++ stOSdCfg.enOSD_loc = EN_DRV_HVSP_OSD_LOC_BEFORE; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[OSD]Set OSD After %d\n",(int)*str); ++ stOSdCfg.enOSD_loc = EN_DRV_HVSP_OSD_LOC_AFTER; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ SCL_ERR( "[OSD]Set OSD Bypass %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDBypass = 1; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ SCL_ERR( "[OSD]Set OSD Bypass Off %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDBypass = 0; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bWTMBypass = 1; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass Off %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bWTMBypass = 0; ++ Drv_HVSP_SetOSDConfig(enID, stOSdCfg); ++ } ++} ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mdrv_multiinst.c b/drivers/mstar/scl/infinity/src/mdrv_multiinst.c +new file mode 100644 +index 00000000..b1f5c36f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mdrv_multiinst.c +@@ -0,0 +1,1361 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_MULTI_INST_C ++#include ++#include ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvpnl.h" ++ ++ ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp_io_st.h" ++#include "mdrv_scldma_io_st.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst_st.h" ++#include "mdrv_multiinst.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define MULTIINST_SEM_DBG 0 ++#define _MULTIINST_SEM_TIMIE_OUT 5000 ++ ++#define MULTIINST_WAIT_SEM_FOREVER(_sem) down(&_sem) ++#define MULTIINST_RELEASE_SEM_FOREVER(_sem) up(&_sem) ++#define DRV_SC1_MUTEX_LOCK() MsOS_ObtainMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2],MSOS_WAIT_FOREVER) ++#define DRV_SC1_MUTEX_UNLOCK() MsOS_ReleaseMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2]) ++#define DRV_SC3_MUTEX_LOCK() MsOS_ObtainMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3],MSOS_WAIT_FOREVER) ++#define DRV_SC3_MUTEX_UNLOCK() MsOS_ReleaseMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3]) ++#define DRV_DSP_MUTEX_LOCK() MsOS_ObtainMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP],MSOS_WAIT_FOREVER) ++#define DRV_DSP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP]) ++#if MULTIINST_SEM_DBG ++ ++#define MULTIINST_WAIT_SEM(_sem) \ ++ printk(KERN_INFO "+++ [LOCK][%s]_1_[%d] \n", __FUNCTION__, __LINE__); \ ++ if(down_timeout(&_sem, msecs_to_jiffies(_MULTIINST_SEM_TIMIE_OUT)) < 0) \ ++ { \ ++ printk(KERN_INFO "[LOCK][%s] [%d], LOCK3 Mutex Time Out \n", __FUNCTION__, __LINE__); \ ++ } \ ++ printk(KERN_INFO "+++ [LOCK][%s]_2_[%d] \n", __FUNCTION__, __LINE__); ++ ++ ++#define MULTIINST_RELEASE_SEM(_sem) \ ++ printk(KERN_INFO "--- [LOCK][%s] [%d] \n", __FUNCTION__, __LINE__); \ ++ up(&_sem); ++ ++ ++#else ++#define MULTIINST_WAIT_SEM(_sem) \ ++ if(down_timeout(&_sem, msecs_to_jiffies(_MULTIINST_SEM_TIMIE_OUT)) < 0) \ ++ { \ ++ printk(KERN_INFO "[LOCK][%s] [%d], LOCK3 Mutex Time Out \n", __FUNCTION__, __LINE__); \ ++ } ++ ++#define MULTIINST_RELEASE_SEM(_sem) up(&_sem) ++ ++#endif //MULTIINST_SEM_DBG ++ ++ ++#define MDRV_MULTI_INST_HVSP_PRIVATE_ID_HEADER 0xA00000 ++#define MDRV_MULTI_INST_SCLDMA_PRIVATE_ID_HEADER 0xD00000 ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++struct semaphore gMultiInstLockSem[E_MDRV_MULTI_INST_LOCK_ID_MAX]; ++struct semaphore gMultiInstHvspEntrySem[E_MDRV_MULTI_INST_HVSP_DATA_ID_MAX]; ++struct semaphore gMultiInstScldmaEntrySem[E_MDRV_MULTI_INST_SCLDMA_DATA_ID_MAX]; ++ ++ST_MDRV_MULTI_INST_LOCK_CONFIG gstMultiInstLockCfg[E_MDRV_MULTI_INST_LOCK_ID_MAX]; ++ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG gstMultiInstScldmaEntryCfg[E_MDRV_MULTI_INST_SCLDMA_DATA_ID_MAX][MDRV_MULTI_INST_SCLDMA_NUM]; ++ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG gstMultiInstHvspEntryCfg[E_MDRV_MULTI_INST_HVSP_DATA_ID_MAX][MDRV_MULTI_INST_HVSP_NUM]; ++signed long gs32PreMultiInstScldmaPrivateId[E_MDRV_MULTI_INST_SCLDMA_DATA_ID_MAX]; ++signed long gs32PreMultiInstHvspPrivateId[E_MDRV_MULTI_INST_HVSP_DATA_ID_MAX]; ++ ++MS_S32 _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_MAX]={-1,-1,-1}; ++MS_BOOL _LOCK_Mutex_flag[E_MDRV_MULTI_INST_LOCK_ID_MAX]={0,0,0}; ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++ ++//---------------------------------------------------------------------------------------------------------------- ++// ++// Multi Instance Lock ++// ++//---------------------------------------------------------------------------------------------------------------- ++ ++unsigned char _MDrv_MultiInst_Lock_Get_PrivateID_Num(EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID) ++{ ++ unsigned char u8Num; ++ ++ switch(enLock_ID) ++ { ++ case E_MDRV_MULTI_INST_LOCK_ID_SC_1_2: ++ u8Num = 4; ++ break; ++ case E_MDRV_MULTI_INST_LOCK_ID_SC_3: ++ u8Num = 2; ++ break; ++ case E_MDRV_MULTI_INST_LOCK_ID_DISP: ++ u8Num = 1; ++ break; ++ default: ++ u8Num = 0; ++ break; ++ } ++ ++ return u8Num; ++} ++ ++ ++unsigned char MDrv_MultiInst_Lock_Init(EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID) ++{ ++ unsigned char bRet = 1; ++ unsigned char i; ++ unsigned char u8PrivateIDNum = 0; ++ char word[] = {"_SC1_Mutex"}; ++ char word2[] = {"_SC3_Mutex"}; ++ char word3[] = {"_DSP_Mutex"}; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enLock_ID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ u8PrivateIDNum = _MDrv_MultiInst_Lock_Get_PrivateID_Num(enLock_ID); ++ if(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2] == -1) ++ { ++ _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2] = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ } ++ if(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3] == -1) ++ { ++ _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3] = MsOS_CreateMutex(E_MSOS_FIFO, word2, MSOS_PROCESS_SHARED); ++ } ++ if(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP] == -1) ++ { ++ _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP] = MsOS_CreateMutex(E_MSOS_FIFO, word3, MSOS_PROCESS_SHARED); ++ } ++ if(gstMultiInstLockCfg[enLock_ID].ps32PrivateID == NULL) ++ { ++ gstMultiInstLockCfg[enLock_ID].u8IDNum = u8PrivateIDNum; ++ gstMultiInstLockCfg[enLock_ID].ps32PrivateID = MsOS_Memalloc(sizeof(signed long)*u8PrivateIDNum, GFP_KERNEL); ++ if(gstMultiInstLockCfg[enLock_ID].ps32PrivateID) ++ { ++ for(i=0; ips32PrivateID[i]) ++ { ++ bRet = 0; ++ break; ++ } ++ } ++ } ++ ++ if(bRet) ++ { ++ for(i=0;istData.stFlag.bInCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stInCfg, (ST_MDRV_HVSP_INPUT_CONFIG *)pData, sizeof(ST_MDRV_HVSP_INPUT_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG) ++ { ++ pEntry->stData.stFlag.bScaleCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stScaleCfg, (ST_MDRV_HVSP_SCALING_CONFIG *)pData, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_POST_CROP_CONFIG) ++ { ++ pEntry->stData.stFlag.bPostCropCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stPostCropCfg, (ST_MDRV_HVSP_POSTCROP_CONFIG *)pData, sizeof(ST_MDRV_HVSP_POSTCROP_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_MEM_REQ_CONFIG) ++ { ++ pEntry->stData.stFlag.bMemCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stMemCfg, (ST_MDRV_HVSP_IPM_CONFIG *)pData, sizeof(ST_MDRV_HVSP_IPM_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG) ++ { ++ pEntry->stData.stFlag.bOSDCfg= 1; ++ MsOS_Memcpy(&pEntry->stData.stOSDCfg, (ST_MDRV_HVSP_OSD_CONFIG*)pData, sizeof(ST_MDRV_HVSP_OSD_CONFIG)); ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): PrivateId:%lx, bMem:%d, bIn:%d, bScale:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, pEntry->stData.stFlag.bMemCfg, pEntry->stData.stFlag.bInCfg, ++ pEntry->stData.stFlag.bScaleCfg); ++ ++ MULTIINST_RELEASE_SEM(gMultiInstHvspEntrySem[enID]); ++ bRet = 1; ++ } ++ else ++ { ++ bRet = 0; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): HvspSaveData fail: PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ ++ return bRet; ++} ++ ++unsigned char _MDrv_MultiInst_Entry_SaveScldmaData( ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ unsigned char bRet = 1; ++ unsigned char index = 0; ++ if(pEntry) ++ { ++ ++ MULTIINST_WAIT_SEM(gMultiInstScldmaEntrySem[enID]); ++ if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG) ++ { ++ pEntry->stData.stFlag.bInBufCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stInBufCfg, (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG) ++ { ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stCfg; ++ MsOS_Memcpy(&stCfg, (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ index = stCfg.enMemType; ++ if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_FRM) ++ { ++ pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_FRM], (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_SNP) ++ { ++ pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_SNP], (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_IMI) ++ { ++ pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_IMI], (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG) ++ { ++ pEntry->stData.stFlag.bInTrigCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stInTrigCfg, (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG) ++ { ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stCfg; ++ MsOS_Memcpy(&stCfg, (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ index = stCfg.enMemType; ++ if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_FRM) ++ { ++ pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM], (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_SNP) ++ { ++ pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP], (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_IMI) ++ { ++ pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI], (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): PrivateId:%lx, bInBuf:%d, bOutBuf[%hhd]:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, pEntry->stData.stFlag.bInBufCfg, index,pEntry->stData.stFlag.bOutBufCfg[index]); ++ ++ MULTIINST_RELEASE_SEM(gMultiInstScldmaEntrySem[enID]); ++ bRet = 1; ++ } ++ else ++ { ++ bRet = 0; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): ScldmaSaveData fail: PrivateId:%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ ++ return bRet; ++} ++ ++unsigned char _MDrv_MultiInst_Entry_ReloadHvspData( ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd) ++{ ++ unsigned char bRet = 1; ++ ST_MDRV_MULTI_INST_HVSP_FLAG_TYPE stFlag; ++ EN_MDRV_HVSP_ID_TYPE enHvspId = enID == E_MDRV_MULTI_INST_HVSP_DATA_ID_1 ? E_MDRV_HVSP_ID_1 : ++ enID == E_MDRV_MULTI_INST_HVSP_DATA_ID_2 ? E_MDRV_HVSP_ID_2 : ++ enID == E_MDRV_MULTI_INST_HVSP_DATA_ID_3 ? E_MDRV_HVSP_ID_3 : ++ E_MDRV_HVSP_ID_MAX ; ++ MsOS_Memset(&stFlag, 0, sizeof(ST_MDRV_MULTI_INST_HVSP_FLAG_TYPE)); ++ ++ MULTIINST_WAIT_SEM(gMultiInstHvspEntrySem[enID]); ++ ++ if(pEntry) ++ { ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ++ { ++ //Reload ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(pEntry->s32PivateId != gs32PreMultiInstHvspPrivateId[enID] && ++ gs32PreMultiInstHvspPrivateId[enID] != -1) ++ { ++ //if not the same fd,reload others setting.(ioctl will set itself,so just set others configuration) ++ if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG) ++ { ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG) ++ { ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_POST_CROP_CONFIG) ++ { ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG) ++ { ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::The first time\n", __FUNCTION__, __LINE__); ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::PrivateId:%lx, bMem:%d, bIn:%d, bScale:%d,bPostCrop:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, stFlag.bMemCfg, stFlag.bInCfg, ++ stFlag.bScaleCfg, stFlag.bPostCropCfg); ++ ++ bRet = 1; ++ ++ if(stFlag.bMemCfg) ++ { ++ ST_HVSP_CMD_TRIG_CONFIG stHvspCmdTrigCfg; ++ stHvspCmdTrigCfg = Drv_HVSP_SetCMDQTrigTypeByRIU(); ++ ++ bRet &= MDrv_HVSP_SetInitIPMConfig(enHvspId, &pEntry->stData.stMemCfg); ++ ++ Drv_HVSP_SetCMDQTrigType(stHvspCmdTrigCfg); ++ } ++ ++ if(stFlag.bInCfg) ++ { ++ bRet &= MDrv_HVSP_SetInputConfig(enHvspId, &pEntry->stData.stInCfg); ++ } ++ ++ ++ if(stFlag.bScaleCfg) ++ { ++ bRet &= MDrv_HVSP_SetScalingConfig(enHvspId, &pEntry->stData.stScaleCfg); ++ } ++ ++ if(stFlag.bPostCropCfg) ++ { ++ bRet &= MDrv_HVSP_SetPostCropConfig(enHvspId, &pEntry->stData.stPostCropCfg); ++ } ++ ++ if(stFlag.bOSDCfg) ++ { ++ bRet &= MDrv_HVSP_SetOSDConfig(enHvspId, &pEntry->stData.stOSDCfg); ++ } ++ ++ gs32PreMultiInstHvspPrivateId[enID] = pEntry->s32PivateId; ++ } ++ else ++ { ++ bRet = 0; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d):: ReloadHvsp Fail, hvspId:%d\n", ++ __FUNCTION__, __LINE__, enID); ++ } ++ ++ MULTIINST_RELEASE_SEM(gMultiInstHvspEntrySem[enID]); ++ ++ return bRet; ++} ++ ++ ++unsigned char _MDrv_MultiInst_Entry_ReloadScldmaData( ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd) ++{ ++ unsigned char bRet; ++ ST_MDRV_MULTI_INST_SCLDMA_FLAG_TYPE stFlag; ++ EN_MDRV_SCLDMA_ID_TYPE enScldmaId = enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_1 ? E_MDRV_SCLDMA_ID_1 : ++ enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_2 ? E_MDRV_SCLDMA_ID_2 : ++ enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_3 ? E_MDRV_SCLDMA_ID_3 : ++ enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_4 ? E_MDRV_SCLDMA_ID_PNL : ++ E_MDRV_HVSP_ID_MAX ; ++ MsOS_Memset(&stFlag, 0, sizeof(ST_MDRV_MULTI_INST_SCLDMA_FLAG_TYPE)); ++ ++ MULTIINST_WAIT_SEM(gMultiInstScldmaEntrySem[enID]); ++ ++ if(pEntry) ++ { ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ++ { ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ stFlag.bInBufCfg = pEntry->stData.stFlag.bInBufCfg; ++ stFlag.bInTrigCfg = pEntry->stData.stFlag.bInTrigCfg; ++ if(pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_FRM].enBufMDType==E_MDRV_SCLDMA_BUFFER_MD_RING ++ &&(enScldmaId==E_MDRV_SCLDMA_ID_1 || enScldmaId==E_MDRV_SCLDMA_ID_2)) ++ { ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM] = 0; ++ } ++ else ++ { ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ } ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ } ++ else if(pEntry->s32PivateId != gs32PreMultiInstScldmaPrivateId[enID] && ++ gs32PreMultiInstScldmaPrivateId[enID] != -1) ++ { ++ if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG) ++ { ++ //for Sc3 , Sc1,Sc2 ignore ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG) ++ { ++ //for Sc3 , Sc1,Sc2 ignore ++ stFlag.bInBufCfg = pEntry->stData.stFlag.bInBufCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG || ++ enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG ++ ) ++ { ++ stFlag.bInBufCfg = pEntry->stData.stFlag.bInBufCfg; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::The first time\n", __FUNCTION__, __LINE__); ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::PrivateId:%lx, bInBuf:%d,bOutBuf_FRM:%d, bOutBuf_SNP:%d, bOutBuf_IMI:%d, bInTrig:%d, bOutTrig_FRM:%d, bOutTrig_SNP:%d, bOutTrig_IMI:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, stFlag.bInBufCfg, ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM],stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP],stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI], ++ stFlag.bInTrigCfg, ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM],stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP],stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]); ++ ++ bRet = 1; ++ if(stFlag.bInBufCfg) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAReadClientConfig(enScldmaId, &pEntry->stData.stInBufCfg); ++ } ++ ++ if(stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientConfig(enScldmaId, &pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]); ++ } ++ ++ ++ if(stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientConfig(enScldmaId, &pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]); ++ } ++ ++ ++ if(stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientConfig(enScldmaId, &pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]); ++ } ++ ++ if(stFlag.bInTrigCfg) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAReadClientTrigger(enScldmaId, &pEntry->stData.stInTrigCfg); ++ } ++ ++ if(stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientTrigger(enScldmaId, &pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]); ++ } ++ ++ if(stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientTrigger(enScldmaId, &pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]); ++ } ++ ++ if(stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientTrigger(enScldmaId, &pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]); ++ } ++ ++ gs32PreMultiInstScldmaPrivateId[enID] = pEntry->s32PivateId; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d):: ReloadScldmaFail, ScldmaId:%d\n", ++ __FUNCTION__, __LINE__, enID); ++ ++ bRet = 0; ++ } ++ ++ MULTIINST_RELEASE_SEM(gMultiInstScldmaEntrySem[enID]); ++ ++ return bRet; ++} ++ ++ ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE _MDrv_MultiInst_Entry_FlashHvspData( ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLockID; ++ unsigned char bSave, bReload ; ++ ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG && pEntry == NULL) ++ { ++ MS_U8 i; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): Force_Relaod, PrivateId=%lx\n", ++ __FUNCTION__, __LINE__, gs32PreMultiInstHvspPrivateId[enID]); ++ ++ for(i=0; is32PivateId) ) ++ { ++ // Reload Data ++ bReload = _MDrv_MultiInst_Entry_ReloadHvspData(enID, pEntry, enCmd); ++ // Save Data ++ bSave = (enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ? ++ 1 : ++ _MDrv_MultiInst_Entry_SaveHvspData(enID, pEntry, enCmd, pData); ++ ++ if(bReload & bSave) ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashHvspData fail, PrivateId=%lx, R:%d, S:%d\n", ++ __FUNCTION__, __LINE__, pEntry->s32PivateId, bReload, bSave); ++ } ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashHvspData LOCKED, PrivateId=%lx\n", ++ __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ } ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): FlashHvspData fail, PrivateId= NULL\n", __FUNCTION__, __LINE__); ++ } ++ return enRet; ++} ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE _MDrv_MultiInst_Entry_FlashScldmaData( ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLockID; ++ unsigned char bSave, bReload ; ++ ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG && pEntry == NULL) ++ { ++ MS_U8 i; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): Force_Relaod, PrivateId=%lx\n", ++ __FUNCTION__, __LINE__, gs32PreMultiInstScldmaPrivateId[enID]); ++ ++ for(i=0; is32PivateId) ) ++ { ++ // Reload Data ++ bReload = _MDrv_MultiInst_Entry_ReloadScldmaData(enID, pEntry, enCmd); ++ ++ // Save Data ++ bSave = (enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ? ++ 1 : ++ _MDrv_MultiInst_Entry_SaveScldmaData(enID, pEntry, enCmd, pData); ++ ++ if(bReload && bSave) ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashScldmaData fail, PrivateId=%lx, R:%d, S:%d\n", ++ __FUNCTION__, __LINE__, pEntry->s32PivateId, bReload, bSave); ++ } ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashScldmaData LOCKED, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ } ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): FlashScldmaData fail, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ ++ return enRet; ++} ++ ++ ++ ++unsigned char MDrv_MultiInst_Entry_Init_Variable(EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID) ++{ ++ unsigned char bRet = 1; ++ unsigned short i; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enHvspId; ++ ++ if( _MDrv_MultiInst_Trans_HvspID(enID, &enHvspId)) ++ { ++ for(i=0;ibUsed = 0; ++ MsOS_Memset(&pEntry->stData, 0, sizeof(ST_MDRV_MULTI_INST_HVSP_DATA_TYPE)); ++ MULTIINST_RELEASE_SEM(gMultiInstHvspEntrySem[enHvspId]); ++ ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): Free fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enSlcmdaId; ++ if( _MDrv_MultiInst_Trans_ScldmaID(enID, &enSlcmdaId) && pPrivate_Data) ++ { ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = NULL; ++ ++ MULTIINST_WAIT_SEM(gMultiInstScldmaEntrySem[enSlcmdaId]); ++ pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivate_Data; ++ pEntry->bUsed = 0; ++ MsOS_Memset(&pEntry->stData, 0, sizeof(ST_MDRV_MULTI_INST_SCLDMA_DATA_TYPE)); ++ MULTIINST_RELEASE_SEM(gMultiInstScldmaEntrySem[enSlcmdaId]); ++ ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): Free fail EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): Free fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ ++ return bRet; ++} ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE MDrv_MultiInst_Entry_FlashData( ++ EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID, ++ void *pPrivateData, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enHvspId; ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *)pPrivateData; ++ if(_MDrv_MultiInst_Trans_HvspID(enID, &enHvspId)) ++ { ++ enRet = _MDrv_MultiInst_Entry_FlashHvspData(enHvspId, pEntry, enCmd, pData); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashData fail, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enSclmdaId; ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivateData; ++ if(_MDrv_MultiInst_Trans_ScldmaID(enID, &enSclmdaId )) ++ { ++ enRet = _MDrv_MultiInst_Entry_FlashScldmaData(enSclmdaId, pEntry, enCmd, pData); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashData fail, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): FlashData fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ ++ return enRet; ++} ++ ++ ++unsigned char MDrv_MultiInst_Entry_GetPirvateId(EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID, void *pPrivateData, signed long *ps32PrivateId) ++{ ++ unsigned char bRet; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *)pPrivateData; ++ ++ if(pEntry) ++ { ++ *ps32PrivateId = pEntry->s32PivateId; ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): GetPrivateID fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ *ps32PrivateId = -1; ++ bRet = 0; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivateData; ++ if(pEntry) ++ { ++ *ps32PrivateId = pEntry->s32PivateId; ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): GetPrivateID fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ *ps32PrivateId = -1; ++ bRet = 0; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): GetPrivateID fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d) EntryId:%x PrivateID=%lx\n", ++ __FUNCTION__, __LINE__, enID, *ps32PrivateId); ++ return bRet; ++} ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE MDrv_MultiInst_Etnry_IsFree(EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID, void *pPrivateData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enIsFree; ++ EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *)pPrivateData; ++ ++ enLock_ID = (enID == E_MDRV_MULTI_INST_ENTRY_ID_HVSP1) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_HVSP2) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ? E_MDRV_MULTI_INST_LOCK_ID_SC_3 : ++ E_MDRV_MULTI_INST_LOCK_ID_MAX; ++ if(pEntry) ++ { ++ if( MDrv_MultiInst_Lock_IsFree(enLock_ID, pEntry->s32PivateId) ) ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): EntryIsFree fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ enIsFree = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivateData; ++ enLock_ID = (enID == E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3) ? E_MDRV_MULTI_INST_LOCK_ID_SC_3 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_DISP) ? E_MDRV_MULTI_INST_LOCK_ID_DISP : ++ E_MDRV_MULTI_INST_LOCK_ID_MAX; ++ if(pEntry) ++ { ++ if( MDrv_MultiInst_Lock_IsFree(enLock_ID, pEntry->s32PivateId) ) ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): EntryIsFree fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ enIsFree = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): EntryIsFree fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ enIsFree = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ ++ return enIsFree; ++} +diff --git a/drivers/mstar/scl/infinity/src/mdrv_pnl.c b/drivers/mstar/scl/infinity/src/mdrv_pnl.c +new file mode 100644 +index 00000000..52e8172b +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mdrv_pnl.c +@@ -0,0 +1,114 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_PNL_C ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvpnl.h" ++ ++#include "mdrv_pnl_io_st.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_pnl.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// gstCfg ++/// use in suspend/resume to save information ++//////////////// ++ST_MDRV_PNL_TIMING_CONFIG gstCfg; ++///////////////// ++/// gbResume ++/// use to determine whether need to set timing config as resume. ++//////////////// ++unsigned char gbResume=0; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void MDrv_PNL_Release(void) ++{ ++ if(gbResume) ++ { ++ Drv_PNL_Release(); ++ } ++} ++unsigned char MDrv_PNL_Init(ST_MDRV_PNL_INIT_CONFIG *pCfg) ++{ ++ ST_PNL_INIT_CONFIG stInitCfg; ++ stInitCfg.u32RiuBase = pCfg->u32RiuBase; ++ ++ if(Drv_PNL_Init(&stInitCfg) == 0) ++ { ++ SCL_ERR("[PNL]%s, Init Fail\n", __FUNCTION__); ++ return 0; ++ } ++ else ++ { ++ return 1; ++ } ++} ++void MDrv_PNL_Resume(void) ++{ ++ Drv_PNL_Resume(); ++ if(gbResume) ++ { ++ MDrv_PNL_Set_Timing_Config(&gstCfg); ++ } ++} ++unsigned char MDrv_PNL_Set_Timing_Config(ST_MDRV_PNL_TIMING_CONFIG *pCfg) ++{ ++ ST_PNL_TIMING_CONFIG stTimingCfg; ++ ++ stTimingCfg.u16Vsync_St = pCfg->u16Vsync_St; ++ stTimingCfg.u16Vsync_End = pCfg->u16Vsync_End; ++ stTimingCfg.u16Vde_St = pCfg->u16Vde_St; ++ stTimingCfg.u16Vde_End = pCfg->u16Vde_End; ++ stTimingCfg.u16Vfde_St = pCfg->u16Vfde_St; ++ stTimingCfg.u16Vfde_End = pCfg->u16Vfde_End; ++ stTimingCfg.u16Vtt = pCfg->u16Vtt; ++ ++ stTimingCfg.u16Hsync_St = pCfg->u16Hsync_St; ++ stTimingCfg.u16Hsync_End = pCfg->u16Hsync_End; ++ stTimingCfg.u16Hde_St = pCfg->u16Hde_St; ++ stTimingCfg.u16Hde_End = pCfg->u16Hde_End; ++ stTimingCfg.u16Hfde_St = pCfg->u16Hfde_St; ++ stTimingCfg.u16Hfde_End = pCfg->u16Hfde_End; ++ ++ stTimingCfg.u16Htt = pCfg->u16Htt; ++ ++ stTimingCfg.u16VFreqx10 = pCfg->u16VFreqx10; ++ MsOS_Memcpy(&gstCfg, pCfg,sizeof(ST_MDRV_PNL_TIMING_CONFIG)); ++ gbResume=1; ++ if( Drv_PNL_Set_Timing_Config(&stTimingCfg) == 0) ++ { ++ SCL_ERR("[PNL]%s, Set Timing Fail\n", __FUNCTION__); ++ return 0; ++ } ++ else ++ { ++ return 1; ++ } ++ ++} +diff --git a/drivers/mstar/scl/infinity/src/mdrv_scldma.c b/drivers/mstar/scl/infinity/src/mdrv_scldma.c +new file mode 100644 +index 00000000..c4c24f77 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mdrv_scldma.c +@@ -0,0 +1,546 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_SCLDMA_C ++ ++#include ++#include ++#include ++ ++#include "mdrv_types.h" ++#include "mdrv_scldma_io_st.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvscldma_st.h" ++#include "drvscldma.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define BUFFER_NUMBER_TO_HWIDX_OFFSET 1 ++#define _ISQueueNeedCopyToUser(enUsedType) (enUsedType==EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_PEEKQUEUE \ ++ || enUsedType==EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_DEQUEUE) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void _MDrv_SCLDMA_BufferQueueHandlerByUsedType ++(EN_MDRV_SCLDMA_USED_BUFFER_QUEUE_TYPE enUsedType,ST_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg) ++{ ++ switch(enUsedType) ++ { ++ case EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_PEEKQUEUE: ++ Drv_SCLDMA_PeekBufferQueue(pstCfg); ++ break; ++ case EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_DEQUEUE: ++ Drv_SCLDMA_BufferDeQueue(pstCfg); ++ break; ++ case EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_ENQUEUE: ++ Drv_SCLDMA_EnableBufferAccess(pstCfg); ++ break; ++ default : ++ SCL_ERR( "[SCLDMA]%s NO this Queue Handler Type\n", __FUNCTION__); ++ break; ++ } ++} ++ ++EN_MDRV_SCLDMA_MEM_TYPE _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer ++(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,EN_SCLDMA_ID_TYPE *enID) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ switch(enSCLDMA_ID) ++ { ++ case E_MDRV_SCLDMA_ID_3: ++ *enID = E_SCLDMA_ID_3_R; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_R : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ case E_MDRV_SCLDMA_ID_PNL: ++ *enID = E_SCLDMA_ID_PNL_R; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_DBG_R : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ default: ++ case E_MDRV_SCLDMA_ID_1: ++ case E_MDRV_SCLDMA_ID_2: ++ SCL_ERR( "[SCLDMA]%s %d::Not support In TRIGGER\n",__FUNCTION__, __LINE__); ++ break; ++ } ++ return enRWMode; ++} ++EN_MDRV_SCLDMA_MEM_TYPE _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer ++(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,EN_SCLDMA_ID_TYPE *enID) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ switch(enSCLDMA_ID) ++ { ++ case E_MDRV_SCLDMA_ID_1: ++ *enID = E_SCLDMA_ID_1_W; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_W : ++ enMemType == E_MDRV_SCLDMA_MEM_SNP ? E_SCLDMA_SNP_W : ++ enMemType == E_MDRV_SCLDMA_MEM_IMI ? E_SCLDMA_IMI_W : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ case E_MDRV_SCLDMA_ID_2: ++ *enID = E_SCLDMA_ID_2_W; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_W : ++ enMemType == E_MDRV_SCLDMA_MEM_IMI ? E_SCLDMA_IMI_W : ++ E_SCLDMA_RW_NUM; ++ ++ break; ++ ++ case E_MDRV_SCLDMA_ID_3: ++ *enID = E_SCLDMA_ID_3_W; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_W : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ case E_MDRV_SCLDMA_ID_PNL: ++ *enID = E_SCLDMA_ID_PNL_R; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_DBG_R: ++ E_SCLDMA_RW_NUM; ++ break; ++ default: ++ SCL_ERR( "[SCLDMA]%s %d::Not support In SCLDMA\n",__FUNCTION__, __LINE__); ++ enRWMode = E_SCLDMA_RW_NUM; ++ break; ++ } ++ return enRWMode; ++} ++EN_MDRV_SCLDMA_MEM_TYPE _MDrv_SCLDMA_SwitchIDForDriverlayer ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,EN_SCLDMA_ID_TYPE *enID,unsigned char bReadDMAMode) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ if(bReadDMAMode) ++ { ++ enRWMode = _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer(enSCLDMA_ID,enMemType,enID); ++ } ++ else ++ { ++ enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,enMemType,enID); ++ } ++ return enRWMode; ++} ++ST_MDRV_SCLDMA_ATTR_TYPE _MDrv_SCLDMA_FillDMAInfoStruct(ST_SCLDMA_ATTR_TYPE stDrvDMACfg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stSendToIOCfg; ++ int u32BufferIdx; ++ stSendToIOCfg.u16DMAcount = stDrvDMACfg.u16DMAcount; ++ stSendToIOCfg.u32Trigcount = stDrvDMACfg.u32Trigcount; ++ stSendToIOCfg.u16DMAH = stDrvDMACfg.u16DMAH; ++ stSendToIOCfg.u16DMAV = stDrvDMACfg.u16DMAV; ++ stSendToIOCfg.enBufMDType = stDrvDMACfg.enBuffMode; ++ stSendToIOCfg.enColorType = stDrvDMACfg.enColor; ++ stSendToIOCfg.u16BufNum = stDrvDMACfg.u8MaxIdx+1; ++ stSendToIOCfg.bDMAEn = stDrvDMACfg.bDMAEn; ++ for(u32BufferIdx=0;u32BufferIdxu8ActiveBuffer; ++ stActiveCfg.enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,pstCfg->enMemType,enID,bReadDMAMode); ++ stActiveCfg.stOnOff.bEn = pstCfg->stOnOff.bEn; ++ stActiveCfg.stOnOff.enRWMode =stActiveCfg.enRWMode; ++ stActiveCfg.stOnOff.stclk=(ST_SCLDMA_CLK_CONFIG *)(pstCfg->stOnOff.stclk); ++ return stActiveCfg; ++} ++ ++unsigned char _MDrv_SCLDMA_GetDMABufferActiveIdx ++ (EN_SCLDMA_ID_TYPE enID,ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg,ST_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg) ++{ ++ if(DoubleBufferStatus) ++ { ++ if(Drv_SCLDMA_GetDMABufferDoneIdx(enID, &stActiveCfg)) ++ { ++ pstCfg->u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ pstCfg->u8ISPcount = stActiveCfg.u8ISPcount; ++ pstCfg->u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ return TRUE; ++ } ++ else ++ { ++ pstCfg->u8ActiveBuffer = 0xFF; ++ pstCfg->u8ISPcount = 0; ++ pstCfg->u32FRMDoneTime = 0; ++ return FALSE; ++ } ++ } ++ else ++ { ++ if(Drv_SCLDMA_GetDMABufferDoneIdxWithoutDoublebuffer(enID, &stActiveCfg)) ++ { ++ pstCfg->u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ pstCfg->u8ISPcount = stActiveCfg.u8ISPcount; ++ pstCfg->u32FRMDoneTime = stActiveCfg.u32FRMDoneTime; ++ return TRUE; ++ } ++ else ++ { ++ pstCfg->u8ActiveBuffer = 0xFF; ++ pstCfg->u8ISPcount = 0; ++ pstCfg->u32FRMDoneTime = 0; ++ return FALSE; ++ } ++ } ++} ++ST_SCLDMA_RW_CONFIG _MDrv_SCLDMA_FillRWCfgStruct ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,ST_MDRV_SCLDMA_BUFFER_CONFIG *pCfg, ++ EN_SCLDMA_ID_TYPE *enID,unsigned char bReadDMAMode) ++{ ++ ST_SCLDMA_RW_CONFIG stSCLDMACfg; ++ unsigned short u16BufferIdx; ++ MsOS_Memset(&stSCLDMACfg, 0, sizeof(ST_SCLDMA_RW_CONFIG)); ++ stSCLDMACfg.enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,pCfg->enMemType,enID,bReadDMAMode); ++ stSCLDMACfg.u16Height = pCfg->u16Height; ++ stSCLDMACfg.u16Width = pCfg->u16Width; ++ stSCLDMACfg.u8MaxIdx = pCfg->u16BufNum -BUFFER_NUMBER_TO_HWIDX_OFFSET; ++ stSCLDMACfg.u8Flag = pCfg->u8Flag; ++ stSCLDMACfg.enBuffMode= (pCfg->enBufMDType == E_MDRV_SCLDMA_BUFFER_MD_RING) ? E_SCLDMA_BUF_MD_RING : ++ (pCfg->enBufMDType == E_MDRV_SCLDMA_BUFFER_MD_SWRING) ? E_SCLDMA_BUF_MD_SWRING : ++ E_SCLDMA_BUF_MD_SINGLE; ++ for(u16BufferIdx=0; u16BufferIdxu16BufNum; u16BufferIdx++) ++ { ++ stSCLDMACfg.u32Base_Y[u16BufferIdx] = pCfg->u32Base_Y[u16BufferIdx]; ++ stSCLDMACfg.u32Base_C[u16BufferIdx] = pCfg->u32Base_C[u16BufferIdx]; ++ } ++ ++ stSCLDMACfg.enColor = pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YUV422 ? E_SCLDMA_COLOR_YUV422 : ++ pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YUV420 ? E_SCLDMA_COLOR_YUV420 : ++ E_SCLDMA_COLOR_NUM; ++ return stSCLDMACfg; ++} ++void MDrv_SCLDMA_SetPollWait ++ (void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ MsOS_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++} ++unsigned char MDrv_SCLDMA_Suspend(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ ST_SCLDMA_SUSPEND_RESUME_CONFIG stSCLDMASuspendResumeCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet = TRUE; ++ ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_PNL ? E_SCLDMA_ID_PNL_R : ++ E_SCLDMA_ID_MAX; ++ MsOS_Memset(&stSCLDMASuspendResumeCfg, 0, sizeof(ST_SCLDMA_SUSPEND_RESUME_CONFIG)); ++ ++ ++ if(Drv_SCLDMA_Suspend(enID, &stSCLDMASuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA]%s %d::Suspend Fail\n",__FUNCTION__, __LINE__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_Resume(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ ST_SCLDMA_SUSPEND_RESUME_CONFIG stSCLDMASuspendResumeCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet = TRUE;; ++ ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_PNL ? E_SCLDMA_ID_PNL_R : ++ E_SCLDMA_ID_MAX; ++ ++ MsOS_Memset(&stSCLDMASuspendResumeCfg, 0, sizeof(ST_SCLDMA_SUSPEND_RESUME_CONFIG)); ++ ++ if(Drv_SCLDMA_Resume(enID, &stSCLDMASuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA]%s %d::Resume Fail\n",__FUNCTION__, __LINE__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_Init(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_INIT_CONFIG *pCfg) ++{ ++ unsigned char bRet = FALSE; ++ ST_SCLDMA_INIT_CONFIG stDMAInitCfg; ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,0,0)), "[SCLDMA]%s\n", __FUNCTION__); ++ ++ stDMAInitCfg.u32RIUBase = pCfg->u32Riubase; ++ if(Drv_SCLDMA_Init(&stDMAInitCfg) == FALSE) ++ { ++ SCL_ERR( "[SCLDMA]%s %d::Init Fail\n",__FUNCTION__, __LINE__); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ ++ return bRet; ++} ++void MDrv_SCLDMA_Sys_Init(unsigned char bEn) ++{ ++ Drv_SCLDMA_Sys_Init(bEn); ++} ++unsigned char MDrv_SCLDMA_GetDoubleBufferStatus(void) ++{ ++ return DoubleBufferStatus; ++} ++void MDrv_SCLDMA_SetDoubleBufferConfig(unsigned char bEn) ++{ ++ gbDBStatus = bEn; ++} ++void MDrv_SCLDMA_Release(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,ST_MDRV_SCLDMA_CLK_CONFIG *stclkcfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_CLK_CONFIG *stclk; ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_PNL ? E_SCLDMA_ID_PNL_R : ++ E_SCLDMA_ID_MAX; ++ ++ stclk = (ST_SCLDMA_CLK_CONFIG *)(stclkcfg); ++ Drv_SCLDMA_Release(enID,stclk); ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAReadClientConfig ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_RW_CONFIG stSCLDMACfg; ++ unsigned char bRet; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,0)), "[SCLDMA]%s\n", __FUNCTION__); ++ ++ stSCLDMACfg = _MDrv_SCLDMA_FillRWCfgStruct(enSCLDMA_ID,pCfg,&enID,1); ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientConfig(enID, stSCLDMACfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAReadClientTrigger ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_TRIGGER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_ONOFF_CONFIG stOnOffCfg; ++ unsigned char bRet; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ stOnOffCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer(enSCLDMA_ID,pCfg->enMemType,&enID); ++ stOnOffCfg.bEn = pCfg->bEn; ++ stOnOffCfg.stclk = (ST_SCLDMA_CLK_CONFIG *)(pCfg->stclk); ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientOnOff(enID ,stOnOffCfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAWriteClientConfig ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_RW_CONFIG stSCLDMACfg; ++ unsigned char bRet; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,0)), ++ "[SCLDMA]%s ID:%d\n", __FUNCTION__,enSCLDMA_ID); ++ ++ stSCLDMACfg = _MDrv_SCLDMA_FillRWCfgStruct(enSCLDMA_ID,pCfg,&enID,0); ++ ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientConfig(enID, stSCLDMACfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAWriteClientTrigger ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_TRIGGER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_ONOFF_CONFIG stOnOffCfg; ++ unsigned char bRet; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ ++ stOnOffCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,pCfg->enMemType,&enID); ++ stOnOffCfg.bEn = pCfg->bEn; ++ stOnOffCfg.stclk = (ST_SCLDMA_CLK_CONFIG *)(pCfg->stclk); ++ ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientOnOff(enID ,stOnOffCfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_GetInBufferDoneEvent ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, EN_MDRV_SCLDMA_MEM_TYPE enMemType, ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG *pCfg) ++{ ++ unsigned char bRet; ++ ST_SCLDMA_DONE_CONFIG stDonCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ ++ stDonCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer(enSCLDMA_ID,enMemType,&enID); ++ bRet = (unsigned char)Drv_SCLDMA_GetDMADoneEvent(enID, &stDonCfg); ++ pCfg->bDone = (unsigned char)stDonCfg.bDone; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,enMemType,1)), ++ "[SCLDMA]%s: ID:%d, bRet: %d, BufferDone:%d\n", __FUNCTION__, enID, bRet, stDonCfg.bDone); ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_GetOutBufferDoneEvent ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, EN_MDRV_SCLDMA_MEM_TYPE enMemType, ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG *pCfg) ++{ ++ unsigned char bRet; ++ ST_SCLDMA_DONE_CONFIG stDonCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ ++ stDonCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,enMemType,&enID); ++ bRet = (unsigned char)Drv_SCLDMA_GetDMADoneEvent(enID, &stDonCfg); ++ pCfg->bDone = (unsigned char)stDonCfg.bDone; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,enMemType,1)), "[SCLDMA]%s: ID:%d, bRet: %d, BufferDone:%d\n", __FUNCTION__, enID, bRet, stDonCfg.bDone); ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_GetDMAReadBufferActiveIdx ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg) ++{ ++ ST_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet; ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pstCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ stActiveCfg = _MDrv_SCLDMA_FillActiveBufferStruct(enSCLDMA_ID,pstCfg,&enID,1); ++ bRet = _MDrv_SCLDMA_GetDMABufferActiveIdx(enID, pstCfg, stActiveCfg); ++ return bRet; ++ ++} ++unsigned char MDrv_SCLDMA_BufferQueueHandle ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg) ++{ ++ unsigned char bRet =0; ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_BUFFER_QUEUE_CONFIG stCfg; ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pstCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ stCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,pstCfg->enMemType,&enID); ++ stCfg.enID = enID; ++ stCfg.u8AccessId = pstCfg->u8EnqueueIdx; ++ _MDrv_SCLDMA_BufferQueueHandlerByUsedType(pstCfg->enUsedType,&stCfg); ++ if(_ISQueueNeedCopyToUser(pstCfg->enUsedType)) ++ { ++ if(stCfg.pstRead != NULL) ++ { ++ MsOS_Memcpy(&pstCfg->stRead,stCfg.pstRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ pstCfg->u8InQueueCount = stCfg.u8InQueueCount; ++ pstCfg->u8EnqueueIdx = stCfg.u8AccessId; ++ bRet = 1; ++ } ++ } ++ return bRet; ++} ++unsigned char MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg) ++{ ++ ST_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet; ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID, pstCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ stActiveCfg = _MDrv_SCLDMA_FillActiveBufferStruct(enSCLDMA_ID, pstCfg, &enID,0); ++ bRet = _MDrv_SCLDMA_GetDMABufferActiveIdx(enID, pstCfg, stActiveCfg); ++ return bRet; ++} ++void MDrv_SCLDMA_SetForceCloseDMAClient ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType, ++ unsigned char bReadDMAMode,unsigned char bEnForceClose) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,enMemType,&enID,bReadDMAMode); ++ Drv_SCLDMA_SetForceCloseDMA(enID,enRWMode,bEnForceClose); ++} ++void MDrv_SCLDMA_ResetTrigCountByClient ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,unsigned char bReadDMAMode) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,enMemType,&enID,bReadDMAMode); ++ Drv_SCLDMA_ResetTrigCountByClient(enID,enRWMode); ++} ++ ++void MDrv_SCLDMA_ResetTrigCountAllClient(void) ++{ ++ Drv_SCLDMA_ResetTrigCountByClient(E_SCLDMA_ID_MAX,E_SCLDMA_RW_NUM); ++} ++ ++void MDrv_SCLDMA_ClkClose(ST_MDRV_SCLDMA_CLK_CONFIG* stclk) ++{ ++ Drv_SCLDMA_ClkClose((ST_SCLDMA_CLK_CONFIG *)stclk); ++} ++wait_queue_head_t * MDrv_SCLDMA_GetWaitQueueHead(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ E_SCLDMA_ID_MAX; ++ if(enID == E_SCLDMA_ID_MAX) ++ { ++ return 0; ++ } ++ else ++ { ++ return Drv_SCLDMA_GetWaitQueueHead(enID); ++ } ++} ++ ++ST_MDRV_SCLDMA_ATTR_TYPE MDrv_SCLDMA_GetDMAInformationByClient ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,unsigned char bReadDMAMode) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ ST_SCLDMA_ATTR_TYPE stDrvDMACfg; ++ ST_MDRV_SCLDMA_ATTR_TYPE stSendToIOCfg; ++ enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,enMemType,&enID,bReadDMAMode); ++ stDrvDMACfg = Drv_SCLDMA_GetDMAInformationByClient(enID, enRWMode); ++ stSendToIOCfg = _MDrv_SCLDMA_FillDMAInfoStruct(stDrvDMACfg); ++ return stSendToIOCfg; ++} +diff --git a/drivers/mstar/scl/infinity/src/mdrv_vip.c b/drivers/mstar/scl/infinity/src/mdrv_vip.c +new file mode 100644 +index 00000000..4dea26aa +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mdrv_vip.c +@@ -0,0 +1,1583 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_VIP_C ++ ++#include ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvvip.h" ++#include "drvCMDQ.h" ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++#include "mdrv_vip_io_st.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_vip.h" ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define MDRV_CMDQ_MUTEX_LOCK(enIP,bEn) (bEn ? Drv_CMDQ_GetModuleMutex(enIP,1) : 0) ++#define MDRV_CMDQ_MUTEX_UNLOCK(enIP,bEn) (bEn ? Drv_CMDQ_GetModuleMutex(enIP,0) : 0) ++#define _IsDNRBufferAllocatedReady() (gu8DNRBufferReadyNum) ++#define _IsCMDQNeedToReturnOrigin() (gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_RETURN_ORI) ++#define _IsCMDQAlreadySetting() (gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_ALREADY_SETINNG) ++#define _IsSetCMDQ() (gbVIPCheckCMDQorPQ >= EN_VIP_CMDQ_CHECK_ALREADY_SETINNG) ++#define _IsAutoSetting() (gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_AUTOSETTING\ ++ || gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_PQ) ++#define _Set_SuspendResetFlag(u32flag) (gstSupCfg.bresetflag |= u32flag) ++#define _IsSuspendResetFlag(enType) (gstSupCfg.bresetflag &enType) ++#define _IsCheckPQorCMDQmode() (gbVIPCheckCMDQorPQ) ++#define _IsNotToCheckPQorCMDQmode() (!gbVIPCheckCMDQorPQ) ++#define _IsOpenVIPBypass() (gu32OpenBypass) ++#define _IsNotOpenVIPBypass() (!gu32OpenBypass) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// gstSupCfg ++/// save data for suspend/resume and test Qmap. ++//////////////// ++ST_IOCTL_VIP_SUSPEND_CONFIG gstSupCfg; ++///////////////// ++/// gbVIPCheckCMDQorPQ ++/// if True ,is check PQ mode. ++//////////////// ++unsigned char gbVIPCheckCMDQorPQ = 0; ++unsigned long gu32OpenBypass = 0; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Function ++//------------------------------------------------------------------------------------------------- ++unsigned short _MDrv_VIP_ChioceStructSizeFromPQType(MS_U8 u8PQIPIdx) ++{ ++ MS_U16 u16DataSize; ++ switch(u8PQIPIdx) ++ { ++ case PQ_IP_PreSNR_Main: ++ u16DataSize = PQ_IP_PreSNR_Size; ++ break; ++ case PQ_IP_DNR_Main: ++ u16DataSize = PQ_IP_DNR_Size; ++ break; ++ case PQ_IP_DNR_Y_Main: ++ u16DataSize = PQ_IP_DNR_Y_Size; ++ break; ++ case PQ_IP_DNR_C_Main: ++ u16DataSize = PQ_IP_DNR_C_Size; ++ break; ++ case PQ_IP_LDC_Main: ++ u16DataSize = PQ_IP_LDC_Size; ++ break; ++ case PQ_IP_LDC_422_444_422_Main: ++ u16DataSize = PQ_IP_LDC_422_444_422_Size; ++ break; ++ case PQ_IP_NLM_Main: ++ u16DataSize = PQ_IP_NLM_Size; ++ break; ++ case PQ_IP_422to444_Main: ++ u16DataSize = PQ_IP_422to444_Size; ++ break; ++ case PQ_IP_VIP_Main: ++ u16DataSize = PQ_IP_VIP_Size; ++ break; ++ case PQ_IP_VIP_LineBuffer_Main: ++ u16DataSize = PQ_IP_VIP_LineBuffer_Size; ++ break; ++ case PQ_IP_VIP_HLPF_Main: ++ u16DataSize = PQ_IP_VIP_HLPF_Size; ++ break; ++ case PQ_IP_VIP_HLPF_dither_Main: ++ u16DataSize = PQ_IP_VIP_HLPF_dither_Size; ++ break; ++ case PQ_IP_VIP_VLPF_coef1_Main: ++ case PQ_IP_VIP_VLPF_coef2_Main: ++ u16DataSize = PQ_IP_VIP_VLPF_coef1_Size; ++ break; ++ case PQ_IP_VIP_VLPF_dither_Main: ++ u16DataSize = PQ_IP_VIP_VLPF_dither_Size; ++ break; ++ case PQ_IP_VIP_Peaking_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_Size; ++ break; ++ case PQ_IP_VIP_Peaking_band_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_band_Size; ++ break; ++ case PQ_IP_VIP_Peaking_adptive_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_adptive_Size; ++ break; ++ case PQ_IP_VIP_Peaking_Pcoring_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_Pcoring_Size; ++ break; ++ case PQ_IP_VIP_Peaking_Pcoring_ad_Y_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_Pcoring_ad_Y_Size; ++ break; ++ case PQ_IP_VIP_Peaking_gain_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_gain_Size; ++ break; ++ case PQ_IP_VIP_Peaking_gain_ad_Y_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_gain_ad_Y_Size; ++ break; ++ case PQ_IP_VIP_YC_gain_offset_Main: ++ u16DataSize = PQ_IP_VIP_YC_gain_offset_Size; ++ break; ++ case PQ_IP_VIP_LCE_Main: ++ u16DataSize = PQ_IP_VIP_LCE_Size; ++ break; ++ case PQ_IP_VIP_LCE_dither_Main: ++ u16DataSize = PQ_IP_VIP_LCE_dither_Size; ++ break; ++ case PQ_IP_VIP_LCE_setting_Main: ++ u16DataSize = PQ_IP_VIP_LCE_setting_Size; ++ break; ++ case PQ_IP_VIP_LCE_curve_Main: ++ u16DataSize = PQ_IP_VIP_LCE_curve_Size; ++ break; ++ case PQ_IP_VIP_DLC_Main: ++ u16DataSize = PQ_IP_VIP_DLC_Size; ++ break; ++ case PQ_IP_VIP_DLC_dither_Main: ++ u16DataSize = PQ_IP_VIP_DLC_dither_Size; ++ break; ++ case PQ_IP_VIP_DLC_His_range_Main: ++ u16DataSize = PQ_IP_VIP_DLC_His_range_Size; ++ break; ++ case PQ_IP_VIP_DLC_His_rangeH_Main: ++ u16DataSize = PQ_IP_VIP_DLC_His_rangeH_Size; ++ break; ++ case PQ_IP_VIP_DLC_His_rangeV_Main: ++ u16DataSize = PQ_IP_VIP_DLC_His_rangeV_Size; ++ break; ++ case PQ_IP_VIP_DLC_PC_Main: ++ u16DataSize = PQ_IP_VIP_DLC_PC_Size; ++ break; ++ case PQ_IP_VIP_UVC_Main: ++ u16DataSize = PQ_IP_VIP_UVC_Size; ++ break; ++ case PQ_IP_VIP_FCC_full_range_Main: ++ u16DataSize = PQ_IP_VIP_FCC_full_range_Size; ++ break; ++ case PQ_IP_VIP_FCC_T1_Main: ++ case PQ_IP_VIP_FCC_T2_Main: ++ case PQ_IP_VIP_FCC_T3_Main: ++ case PQ_IP_VIP_FCC_T4_Main: ++ case PQ_IP_VIP_FCC_T5_Main: ++ case PQ_IP_VIP_FCC_T6_Main: ++ case PQ_IP_VIP_FCC_T7_Main: ++ case PQ_IP_VIP_FCC_T8_Main: ++ u16DataSize = PQ_IP_VIP_FCC_T1_Size; ++ break; ++ case PQ_IP_VIP_FCC_T9_Main: ++ u16DataSize = PQ_IP_VIP_FCC_T9_Size; ++ break; ++ case PQ_IP_VIP_IHC_Main: ++ u16DataSize = PQ_IP_VIP_IHC_Size; ++ break; ++ case PQ_IP_VIP_IHC_Ymode_Main: ++ u16DataSize = PQ_IP_VIP_IHC_Ymode_Size; ++ break; ++ case PQ_IP_VIP_IHC_dither_Main: ++ u16DataSize = PQ_IP_VIP_IHC_dither_Size; ++ break; ++ case PQ_IP_VIP_IHC_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_IHC_SETTING_Size; ++ break; ++ case PQ_IP_VIP_ICC_Main: ++ u16DataSize = PQ_IP_VIP_ICC_Size; ++ break; ++ case PQ_IP_VIP_ICC_Ymode_Main: ++ u16DataSize = PQ_IP_VIP_ICC_Ymode_Size; ++ break; ++ case PQ_IP_VIP_ICC_dither_Main: ++ u16DataSize = PQ_IP_VIP_ICC_dither_Size; ++ break; ++ case PQ_IP_VIP_ICC_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_ICC_SETTING_Size; ++ break; ++ case PQ_IP_VIP_Ymode_Yvalue_ALL_Main: ++ u16DataSize = PQ_IP_VIP_Ymode_Yvalue_ALL_Size; ++ break; ++ case PQ_IP_VIP_Ymode_Yvalue_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_Ymode_Yvalue_SETTING_Size; ++ break; ++ case PQ_IP_VIP_IBC_Main: ++ u16DataSize = PQ_IP_VIP_IBC_Size; ++ break; ++ case PQ_IP_VIP_IBC_dither_Main: ++ u16DataSize = PQ_IP_VIP_IBC_dither_Size; ++ break; ++ case PQ_IP_VIP_IBC_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_IBC_SETTING_Size; ++ break; ++ case PQ_IP_VIP_ACK_Main: ++ u16DataSize = PQ_IP_VIP_ACK_Size; ++ break; ++ case PQ_IP_VIP_YCbCr_Clip_Main: ++ u16DataSize = PQ_IP_VIP_YCbCr_Clip_Size; ++ break; ++ default: ++ u16DataSize = 0; ++ ++ break; ++ } ++ return u16DataSize; ++} ++ST_MDRV_VIP_SETPQ_CONFIG _MDrv_VIP_FillPQCfgByType(MS_U8 u8PQIPIdx, MS_U8 *pData, MS_U16 u16DataSize) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ stSetPQCfg.enPQIPType = u8PQIPIdx; ++ stSetPQCfg.pPointToCfg = pData; ++ stSetPQCfg.u32StructSize = u16DataSize; ++ return stSetPQCfg; ++} ++ ++void _MDrv_VIP_FillstFCfgBelongGlobal(EN_VIP_CONFIG_TYPE enVIPtype,unsigned char bEn,unsigned char u8framecnt) ++{ ++ switch(enVIPtype) ++ { ++ case EN_VIP_DNR_CONFIG: ++ gstSupCfg.stdnr.stFCfg.bEn = bEn ; ++ gstSupCfg.stdnr.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_ACK_CONFIG: ++ gstSupCfg.stack.stFCfg.bEn = bEn ; ++ gstSupCfg.stack.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_IBC_CONFIG: ++ gstSupCfg.stibc.stFCfg.bEn = bEn ; ++ gstSupCfg.stibc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_IHCICC_CONFIG: ++ gstSupCfg.stihcicc.stFCfg.bEn = bEn ; ++ gstSupCfg.stihcicc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_ICC_CONFIG: ++ gstSupCfg.sticc.stFCfg.bEn = bEn ; ++ gstSupCfg.sticc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_IHC_CONFIG: ++ gstSupCfg.stihc.stFCfg.bEn = bEn ; ++ gstSupCfg.stihc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_FCC_CONFIG: ++ gstSupCfg.stfcc.stFCfg.bEn = bEn ; ++ gstSupCfg.stfcc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_UVC_CONFIG: ++ gstSupCfg.stuvc.stFCfg.bEn = bEn ; ++ gstSupCfg.stuvc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_DLC_CONFIG: ++ gstSupCfg.stdlc.stFCfg.bEn = bEn ; ++ gstSupCfg.stdlc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_DLC_HISTOGRAM_CONFIG: ++ gstSupCfg.sthist.stFCfg.bEn = bEn ; ++ gstSupCfg.sthist.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_LCE_CONFIG: ++ gstSupCfg.stlce.stFCfg.bEn = bEn ; ++ gstSupCfg.stlce.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_PEAKING_CONFIG: ++ gstSupCfg.stpk.stFCfg.bEn = bEn ; ++ gstSupCfg.stpk.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_LDC_MD_CONFIG: ++ gstSupCfg.stldcmd.stFCfg.bEn = bEn ; ++ gstSupCfg.stldcmd.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_LDC_DMAP_CONFIG: ++ gstSupCfg.stldcdmap.stFCfg.bEn = bEn ; ++ gstSupCfg.stldcdmap.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_LDC_SRAM_CONFIG: ++ gstSupCfg.stldcsram.stFCfg.bEn = bEn ; ++ gstSupCfg.stldcsram.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_NLM_CONFIG: ++ gstSupCfg.stnlm.stFCfg.bEn = bEn ; ++ gstSupCfg.stnlm.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_SNR_CONFIG: ++ gstSupCfg.stsnr.stFCfg.bEn = bEn ; ++ gstSupCfg.stsnr.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_LDC_CONFIG: ++ gstSupCfg.stldc.stFCfg.bEn = bEn ; ++ gstSupCfg.stldc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_CONFIG: ++ gstSupCfg.stack.stFCfg.bEn = bEn ; ++ gstSupCfg.stack.stFCfg.u8framecnt = u8framecnt; ++ break; ++ default: ++ gstSupCfg.stvip.stFCfg.bEn = 0 ; ++ gstSupCfg.stvip.stFCfg.u8framecnt = 0; ++ break; ++ ++ } ++} ++void _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_CONFIG_TYPE enVIPtype,void *pCfg) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ stSetPQCfg = MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,pCfg); ++ MsOS_Memcpy(stSetPQCfg.pGolbalStructAddr, stSetPQCfg.pPointToCfg,stSetPQCfg.u32StructSize); ++ _MDrv_VIP_FillstFCfgBelongGlobal(enVIPtype,0,0); ++ _Set_SuspendResetFlag(enVIPtype); ++ } ++} ++void _MDrv_VIP_ResetAlreadySetting(ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg) ++{ ++ void * pvPQSetParameter; ++ pvPQSetParameter = MsOS_Memalloc(stSetPQCfg.u32StructSize, GFP_KERNEL); ++ MsOS_Memset(pvPQSetParameter, 0, stSetPQCfg.u32StructSize); ++ stSetPQCfg.pfForSet(pvPQSetParameter); ++ MsOS_MemFree(pvPQSetParameter); ++} ++void _MDrv_VIP_FillAutoSetStruct(ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg) ++{ ++ void * pvPQSetParameter; ++ pvPQSetParameter = MsOS_Memalloc(stSetPQCfg.u32StructSize, GFP_KERNEL); ++ MsOS_Memset(pvPQSetParameter, 0xFF, stSetPQCfg.u32StructSize); ++ MsOS_Memcpy(stSetPQCfg.pGolbalStructAddr, pvPQSetParameter, stSetPQCfg.u32StructSize); ++ MsOS_MemFree(pvPQSetParameter); ++} ++void _MDrv_VIP_PrepareCheckSetting(EN_VIP_CONFIG_TYPE enVIPtype) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ unsigned char bEn,u8framecount; ++ bEn = (_IsSetCMDQ()) ? 1 : 0 ; ++ u8framecount = 0; ++ stSetPQCfg = MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,NULL); ++ if(_IsCMDQAlreadySetting()) ++ { ++ _MDrv_VIP_ResetAlreadySetting(stSetPQCfg); ++ } ++ else if(_IsAutoSetting()) ++ { ++ _MDrv_VIP_FillAutoSetStruct(stSetPQCfg); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, "[VIP]%x:addr:%lx\n",enVIPtype,(unsigned long)stSetPQCfg.pGolbalStructAddr); ++ } ++ _MDrv_VIP_FillstFCfgBelongGlobal(enVIPtype,bEn,u8framecount); ++} ++void _MDrv_VIP_For_PrepareCheckSetting(void) ++{ ++ EN_VIP_CONFIG_TYPE enVIPtype; ++ for(enVIPtype =EN_VIP_ACK_CONFIG;enVIPtype<=EN_VIP_CONFIG;(enVIPtype*=2)) ++ { ++ if(_IsSuspendResetFlag(enVIPtype)) ++ { ++ _MDrv_VIP_PrepareCheckSetting(enVIPtype); ++ } ++ } ++} ++void _MDrv_VIP_SetCMDQAfterPollTimeoutSkip(unsigned char bskip) ++{ ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_TYPE_IP0,bskip); ++} ++void _MDrv_VIP_WaitForCMDQDone(void) ++{ ++ int u32Time; ++ u32Time = MsOS_GetSystemTime(); ++ while(1) ++ { ++ if(Drv_CMDQ_CheckIPAlreadyDone(EN_CMDQ_TYPE_IP0)) ++ { ++ _MDrv_VIP_SetCMDQAfterPollTimeoutSkip(0);//close no wait ++ break; ++ } ++ else if(MsOS_Timer_DiffTimeFromNow(u32Time)>1000) ++ { ++ printf("[VIP]!!!!Timeout\n"); ++ break; ++ } ++ } ++} ++void _MDrv_VIP_For_SetEachIP(void) ++{ ++ EN_VIP_CONFIG_TYPE enVIPtype; ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ for(enVIPtype =EN_VIP_ACK_CONFIG;enVIPtype<=EN_VIP_CONFIG;(enVIPtype*=2)) ++ { ++ if(_IsSuspendResetFlag(enVIPtype)) ++ { ++ stSetPQCfg = MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,NULL); ++ stSetPQCfg.pfForSet((void *)stSetPQCfg.pGolbalStructAddr); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, "[MDRVVIP]%s %d \n", __FUNCTION__,enVIPtype); ++ } ++ } ++} ++void _MDrv_VIP_ResumeDumpSRAM(void) ++{ ++ if(_IsSuspendResetFlag(EN_VIP_NLM_CONFIG)) ++ { ++ if(gstSupCfg.stnlm.stSRAM.bEn) ++ { ++ MDrv_VIP_SetNLMSRAMConfig(gstSupCfg.stnlm.stSRAM); ++ } ++ else if(!gstSupCfg.stnlm.stSRAM.bEn && gstSupCfg.stnlm.stSRAM.u32viradr) ++ { ++ MDrv_VIP_SetNLMSRAMConfig(gstSupCfg.stnlm.stSRAM); ++ } ++ ++ } ++ Drv_VIP_SRAM_Dump(); ++} ++void _MDrv_VIP_PrepareBypassFunctionStruct(unsigned char bBypass,ST_MDRV_VIP_SETPQ_CONFIG stSetBypassCfg) ++{ ++ if(bBypass) ++ { ++ MsOS_Memset(stSetBypassCfg.pPointToCfg, 0,stSetBypassCfg.u32StructSize); ++ } ++ else ++ { ++ if(stSetBypassCfg.bSetConfigFlag) ++ { ++ MsOS_Memcpy(stSetBypassCfg.pPointToCfg,stSetBypassCfg.pGolbalStructAddr ,stSetBypassCfg.u32StructSize); ++ } ++ } ++} ++void _MDrv_VIP_SetCMDQStatus(unsigned char bFire,unsigned char bEn,unsigned char u8framecnt) ++{ ++ MDRv_PQ_Set_CmdqCfg(0,bEn,u8framecnt,bFire); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, "[MVIP]CMDQ:%hhd,framecnt:%hhd\n" ++ ,bEn,u8framecnt); ++} ++void _MDrv_VIP_SetPQParameter(ST_MDRV_VIP_SETPQ_CONFIG stSetBypassCfg) ++{ ++ MDrv_PQ_LoadSettingByData(0,stSetBypassCfg.enPQIPType,stSetBypassCfg.pPointToCfg,stSetBypassCfg.u32StructSize); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MVIP]enPQIPType:%ld,u32StructSize:%ld\n" ++ ,stSetBypassCfg.enPQIPType,stSetBypassCfg.u32StructSize); ++} ++void _MDrv_VIP_SetPQByType(MS_U8 u8PQIPIdx, MS_U8 *pData) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ stSetPQCfg = _MDrv_VIP_FillPQCfgByType(u8PQIPIdx,pData,_MDrv_VIP_ChioceStructSizeFromPQType(u8PQIPIdx)); ++ _MDrv_VIP_SetPQParameter(stSetPQCfg); ++} ++void _MDrv_VIP_For_SetEachPQTypeByIP ++ (unsigned char u8FirstType,unsigned char u8LastType,ST_IOCTL_VIP_FC_CONFIG stFCfg,MS_U8 ** pPointToData) ++{ ++ unsigned char u8PQType; ++ for(u8PQType = u8FirstType;u8PQType<=u8LastType;u8PQType++) ++ { ++ if(u8PQType == u8FirstType) ++ { ++ _MDrv_VIP_SetCMDQStatus(0,stFCfg.bEn,stFCfg.u8framecnt); ++ } ++ else if(u8PQType == u8LastType) ++ { ++ _MDrv_VIP_SetCMDQStatus(1,stFCfg.bEn,stFCfg.u8framecnt); ++ } ++ _MDrv_VIP_SetPQByType(u8PQType,pPointToData[u8PQType-u8FirstType]); ++ } ++} ++unsigned char _MDrv_VIP_SetBypassIP(unsigned long bBypass,EN_VIP_CONFIG_TYPE enVIPtype) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetBypassCfg; ++ stSetBypassCfg.bSetConfigFlag = _IsSuspendResetFlag(enVIPtype); ++ switch(enVIPtype) ++ { ++ case EN_VIP_DNR_CONFIG: ++ stSetBypassCfg.u32StructSize = sizeof(ST_IOCTL_VIP_DNR_ONOFF_CONFIG); ++ stSetBypassCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stdnr.stOnOff; ++ stSetBypassCfg.enPQIPType = PQ_IP_DNR_Main; ++ stSetBypassCfg.pPointToCfg = MsOS_Memalloc(stSetBypassCfg.u32StructSize, GFP_KERNEL); ++ _MDrv_VIP_PrepareBypassFunctionStruct(bBypass,stSetBypassCfg); ++ if(stSetBypassCfg.bSetConfigFlag) ++ { ++ _MDrv_VIP_SetPQParameter(stSetBypassCfg); ++ } ++ MsOS_MemFree(stSetBypassCfg.pPointToCfg); ++ break; ++ case EN_VIP_NLM_CONFIG: ++ stSetBypassCfg.u32StructSize = sizeof(ST_IOCTL_VIP_NLM_MAIN_CONFIG); ++ stSetBypassCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stnlm.stNLM; ++ stSetBypassCfg.enPQIPType = PQ_IP_NLM_Main; ++ stSetBypassCfg.pPointToCfg = MsOS_Memalloc(stSetBypassCfg.u32StructSize, GFP_KERNEL); ++ _MDrv_VIP_PrepareBypassFunctionStruct(bBypass,stSetBypassCfg); ++ if(stSetBypassCfg.bSetConfigFlag) ++ { ++ _MDrv_VIP_SetPQParameter(stSetBypassCfg); ++ } ++ MsOS_MemFree(stSetBypassCfg.pPointToCfg); ++ break; ++ case EN_VIP_SNR_CONFIG: ++ stSetBypassCfg.u32StructSize = sizeof(ST_IOCTL_VIP_SNR_MAIN_CONFIG); ++ stSetBypassCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stsnr.stSNR; ++ stSetBypassCfg.enPQIPType = PQ_IP_PreSNR_Main; ++ stSetBypassCfg.pPointToCfg = MsOS_Memalloc(stSetBypassCfg.u32StructSize, GFP_KERNEL); ++ _MDrv_VIP_PrepareBypassFunctionStruct(bBypass,stSetBypassCfg); ++ if(stSetBypassCfg.bSetConfigFlag) ++ { ++ _MDrv_VIP_SetPQParameter(stSetBypassCfg); ++ } ++ MsOS_MemFree(stSetBypassCfg.pPointToCfg); ++ break; ++ case EN_VIP_LDC_CONFIG: ++ Drv_VIP_SetLDCOnConfig(!bBypass); ++ break; ++ case EN_VIP_CONFIG: ++ MDRv_PQ_Set_CmdqCfg(0,0,0,0); ++ stSetBypassCfg.u32StructSize = sizeof(ST_IOCTL_VIP_BYPASS_CONFIG); ++ stSetBypassCfg.enPQIPType = PQ_IP_VIP_Main; ++ stSetBypassCfg.pPointToCfg = MsOS_Memalloc(stSetBypassCfg.u32StructSize, GFP_KERNEL); ++ MsOS_Memset(stSetBypassCfg.pPointToCfg, (bBypass) ? 0x1 :0,stSetBypassCfg.u32StructSize); ++ _MDrv_VIP_SetPQParameter(stSetBypassCfg); ++ MsOS_MemFree(stSetBypassCfg.pPointToCfg); ++ break; ++ default: ++ stSetBypassCfg.u32StructSize = 0; ++ stSetBypassCfg.pGolbalStructAddr = NULL; ++ stSetBypassCfg.bSetConfigFlag = 0; ++ stSetBypassCfg.pPointToCfg = NULL; ++ stSetBypassCfg.enPQIPType = PQ_IP_SC_End_Main; ++ return 0; ++ ++ } ++ return 1; ++} ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++ST_MDRV_VIP_SETPQ_CONFIG MDrv_VIP_FillBasicStructSetPQCfg(EN_VIP_CONFIG_TYPE enVIPtype,void *pPointToCfg) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ stSetPQCfg.bSetConfigFlag = _IsSuspendResetFlag(enVIPtype); ++ stSetPQCfg.pPointToCfg = pPointToCfg; ++ switch(enVIPtype) ++ { ++ case EN_VIP_DNR_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_DNR_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stdnr; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetDNRConfig; ++ break; ++ ++ case EN_VIP_ACK_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_ACK_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stack; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetACKConfig; ++ break; ++ ++ case EN_VIP_IBC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_IBC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stibc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetIBCConfig; ++ break; ++ ++ case EN_VIP_IHCICC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_IHCICC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stihcicc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetIHCICCADPYConfig; ++ break; ++ ++ case EN_VIP_ICC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_ICC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.sticc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetICEConfig; ++ break; ++ ++ case EN_VIP_IHC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_IHC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stihc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetIHCConfig; ++ break; ++ ++ case EN_VIP_FCC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_FCC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stfcc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetFCCConfig; ++ break; ++ case EN_VIP_UVC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_UVC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stuvc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetUVCConfig; ++ break; ++ ++ case EN_VIP_DLC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_DLC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stdlc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetDLCConfig; ++ break; ++ ++ case EN_VIP_DLC_HISTOGRAM_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.sthist; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetHistogramConfig; ++ break; ++ ++ case EN_VIP_LCE_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_LCE_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stlce; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetLCEConfig; ++ break; ++ ++ case EN_VIP_PEAKING_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_PEAKING_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stpk; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetPeakingConfig; ++ break; ++ ++ case EN_VIP_LDC_MD_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_LDC_MD_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldcmd; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetLDCmdConfig; ++ break; ++ ++ case EN_VIP_LDC_DMAP_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_LDC_DMAP_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldcdmap; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetLDCDmapConfig; ++ break; ++ ++ case EN_VIP_LDC_SRAM_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_LDC_SRAM_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldcsram; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetLDCSRAMConfig; ++ break; ++ ++ case EN_VIP_NLM_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_NLM_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stnlm; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetNLMConfig; ++ break; ++ case EN_VIP_SNR_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_SNR_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stsnr; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetSNRConfig; ++ break; ++ case EN_VIP_LDC_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_LDC_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldc; ++ stSetPQCfg.pfForSet = MDrv_VIP_SetLDCConfig; ++ break; ++ case EN_VIP_CONFIG: ++ stSetPQCfg.u32StructSize = sizeof(ST_IOCTL_VIP_CONFIG); ++ stSetPQCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stvip; ++ stSetPQCfg.pfForSet = MDrv_SetVIPOtherConfig; ++ break; ++ default: ++ stSetPQCfg.u32StructSize = 0; ++ stSetPQCfg.pGolbalStructAddr = NULL; ++ stSetPQCfg.bSetConfigFlag = 0; ++ stSetPQCfg.pfForSet = NULL; ++ break; ++ ++ } ++ return stSetPQCfg; ++} ++ ++ ++unsigned char MDrv_VIP_Init(ST_MDRV_VIP_INIT_CONFIG *pCfg) ++{ ++ ST_VIP_INIT_CONFIG stIniCfg; ++ ST_VIP_OPEN_CONFIG stCMDQIniCfg; ++ MS_PQ_Init_Info stPQInitInfo; ++ unsigned char ret = FALSE; ++ stIniCfg.u32RiuBase = pCfg->u32RiuBase; ++ stCMDQIniCfg.u32RiuBase = pCfg->u32RiuBase; ++ stCMDQIniCfg.u32CMDQ_Phy = pCfg->CMDQCfg.u32CMDQ_Phy; ++ stCMDQIniCfg.u32CMDQ_Size = pCfg->CMDQCfg.u32CMDQ_Size; ++ stCMDQIniCfg.u32CMDQ_Vir = pCfg->CMDQCfg.u32CMDQ_Vir; ++ if(Drv_VIP_Init(&stIniCfg) == 0) ++ { ++ SCL_ERR( "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ MDrv_PQ_init_RIU(pCfg->u32RiuBase); ++ Drv_CMDQ_Init(stCMDQIniCfg.u32CMDQ_Phy, stCMDQIniCfg.u32CMDQ_Vir, stCMDQIniCfg.u32CMDQ_Size, stCMDQIniCfg.u32RiuBase); ++ MsOS_Memset(&stPQInitInfo, 0, sizeof(MS_PQ_Init_Info)); ++ gu32OpenBypass = 0; ++ // Init PQ ++ stPQInitInfo.u16PnlWidth = 1920; ++ stPQInitInfo.u8PQBinCnt = 0; ++ stPQInitInfo.u8PQTextBinCnt = 0; ++ if(MDrv_PQ_Init(&stPQInitInfo)) ++ { ++ MDrv_PQ_DesideSrcType(PQ_MAIN_WINDOW, PQ_INPUT_SOURCE_ISP); ++ //MDrv_PQ_LoadSettings(PQ_MAIN_WINDOW); ++ ret = TRUE; ++ } ++ else ++ { ++ ret = FALSE; ++ } ++ Drv_VIP_SRAM_Dump(); ++ return ret; ++} ++void MDrv_VIP_Delete(void) ++{ ++ Drv_CMDQ_Delete(); ++} ++void MDrv_VIP_Release(void) ++{ ++ Drv_CMDQ_release(); ++} ++unsigned char MDrv_VIP_GetCMDQHWDone(void) ++{ ++ return Drv_VIP_GetCMDQHWDone(); ++} ++ ++wait_queue_head_t * MDrv_VIP_GetWaitQueueHead(void) ++{ ++ return Drv_VIP_GetWaitQueueHead(); ++} ++void MDrv_VIP_SetPollWait ++ (void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ MsOS_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++} ++ ++void MDrv_VIP_SuspendResetFlagInit(void) ++{ ++ gstSupCfg.bresetflag = 0; ++} ++void MDrv_VIP_SetAllVIPOneshot(ST_IOCTL_VIP_SUSPEND_CONFIG *stvipCfg) ++{ ++ EN_VIP_CONFIG_TYPE enVIPtype; ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ unsigned long u32StructSize = sizeof(unsigned long); ++ gstSupCfg.bresetflag = stvipCfg->bresetflag; ++ gstSupCfg.bresetflag &= 0x3FFFF; ++ for(enVIPtype =EN_VIP_ACK_CONFIG;enVIPtypestC); ++ p8PQType[1] = (MS_U8*)&(pCfg->stY); ++ p8PQType[0] = (MS_U8*)&(pCfg->stOnOff); ++ ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(_IsNotOpenVIPBypass()) ++ { ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_DNR_Main,PQ_IP_DNR_C_Main,pCfg->stFCfg,p8PQType); ++ Drv_VIP_SetDNRIPMRead(pCfg->stOnOff.bEn); ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_DNR_CONFIG,(void *)pCfg); ++ ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&(gstSupCfg.stdnr),gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,DNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++ ++unsigned char MDrv_VIP_SetPeakingConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_PEAKING_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_Peaking_gain_ad_Y_Main-PQ_IP_VIP_HLPF_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stHLPF); ++ p8PQType[1] = (MS_U8*)&(pCfg->stHLPFDith); ++ p8PQType[2] = (MS_U8*)&(pCfg->stVLPFcoef1); ++ p8PQType[3] = (MS_U8*)&(pCfg->stVLPFcoef2); ++ p8PQType[4] = (MS_U8*)&(pCfg->stVLPFDith); ++ p8PQType[5] = (MS_U8*)&(pCfg->stOnOff); ++ p8PQType[6] = (MS_U8*)&(pCfg->stBand); ++ p8PQType[7] = (MS_U8*)&(pCfg->stAdp); ++ p8PQType[8] = (MS_U8*)&(pCfg->stPcor); ++ p8PQType[9] = (MS_U8*)&(pCfg->stAdpY); ++ p8PQType[10] = (MS_U8*)&(pCfg->stGain); ++ p8PQType[11] = (MS_U8*)&(pCfg->stGainAdpY); ++ ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_HLPF_Main,PQ_IP_VIP_Peaking_gain_ad_Y_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_PEAKING_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stpk,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetHistogramConfig(void *pvCfg) ++{ ++ ST_VIP_DLC_HISTOGRAM_CONFIG stDLCCfg; ++ MS_U16 i; ++ ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG *pCfg = pvCfg; ++ stDLCCfg.bVariable_Section = pCfg->bVariable_Section; ++ stDLCCfg.bstat_MIU = pCfg->bstat_MIU; ++ stDLCCfg.bcurve_fit_en = pCfg->bcurve_fit_en; ++ stDLCCfg.bcurve_fit_rgb_en = pCfg->bcurve_fit_rgb_en; ++ stDLCCfg.bDLCdither_en = pCfg->bDLCdither_en; ++ stDLCCfg.bhis_y_rgb_mode_en = pCfg->bhis_y_rgb_mode_en; ++ stDLCCfg.bstatic = pCfg->bstatic; ++ stDLCCfg.bRange = pCfg->bRange; ++ stDLCCfg.u16Vst = pCfg->u16Vst; ++ stDLCCfg.u16Hst = pCfg->u16Hst; ++ stDLCCfg.u16Vnd = pCfg->u16Vnd; ++ stDLCCfg.u16Hnd = pCfg->u16Hnd; ++ stDLCCfg.u8HistSft = pCfg->u8HistSft; ++ stDLCCfg.u8trig_ref_mode = pCfg->u8trig_ref_mode; ++ stDLCCfg.u32StatBase[0] = pCfg->u32StatBase[0]; ++ stDLCCfg.u32StatBase[1] = pCfg->u32StatBase[1]; ++ stDLCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stDLCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ ++ for(i=0;iu8Histogram_Range[i]; ++ } ++ ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(Drv_VIP_SetDLCHistogramConfig(stDLCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ return FALSE; ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_DLC_HISTOGRAM_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.sthist,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_GetDLCHistogramReport(void *pvCfg) ++{ ++ ST_VIP_DLC_HISTOGRAM_REPORT stDLCCfg; ++ MS_U16 i; ++ ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT *pCfg = pvCfg; ++ stDLCCfg = Drv_VIP_GetDLCHistogramConfig(); ++ pCfg->u32PixelWeight = stDLCCfg.u32PixelWeight; ++ pCfg->u32PixelCount = stDLCCfg.u32PixelCount; ++ pCfg->u8MaxPixel = stDLCCfg.u8MaxPixel; ++ pCfg->u8MinPixel = stDLCCfg.u8MinPixel; ++ pCfg->u8Baseidx = stDLCCfg.u8Baseidx; ++ for(i=0;iu32Histogram[i] = stDLCCfg.u32Histogram[i]; ++ } ++ ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetDLCConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_DLC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_YC_gain_offset_Main-PQ_IP_VIP_DLC_His_range_Main+1)];//add PQ_IP_VIP_YC_gain_offset_Main ++ p8PQType[0] = (MS_U8*)&(pCfg->sthist); ++ p8PQType[1] = (MS_U8*)&(pCfg->stEn); ++ p8PQType[2] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[3] = (MS_U8*)&(pCfg->stHistH); ++ p8PQType[4] = (MS_U8*)&(pCfg->stHistV); ++ p8PQType[5] = (MS_U8*)&(pCfg->stPC); ++ p8PQType[6] = (MS_U8*)&(pCfg->stGainOffset); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_DLC_His_range_Main,PQ_IP_VIP_YC_gain_offset_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_DLC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stdlc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetLCEConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_LCE_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_LCE_curve_Main-PQ_IP_VIP_LCE_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stOnOff); ++ p8PQType[1] = (MS_U8*)&(pCfg->stDITHER); ++ p8PQType[2] = (MS_U8*)&(pCfg->stSet); ++ p8PQType[3] = (MS_U8*)&(pCfg->stCurve); ++ ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_LCE_Main,PQ_IP_VIP_LCE_curve_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_LCE_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stlce,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetUVCConfig(void *pvCfg) ++{ ++ MS_U8 *pUVC = NULL; ++ ST_IOCTL_VIP_UVC_CONFIG *pCfg = pvCfg; ++ pUVC = (MS_U8*)&(pCfg->stUVC); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ _MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_VIP_UVC_Main,pUVC); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_UVC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stuvc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++ ++unsigned char MDrv_VIP_SetIHCConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_IHC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_IHC_dither_Main-PQ_IP_VIP_IHC_Main+2)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stOnOff); ++ p8PQType[1] = (MS_U8*)&(pCfg->stYmd); ++ p8PQType[2] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[3] = (MS_U8*)&(pCfg->stset); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_VIP_IHC_SETTING_Main,p8PQType[3]); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_IHC_Main,PQ_IP_VIP_IHC_dither_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_IHC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stihc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetICEConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_ICC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_ICC_SETTING_Main-PQ_IP_VIP_ICC_dither_Main+2)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stEn); ++ p8PQType[1] = (MS_U8*)&(pCfg->stYmd); ++ p8PQType[2] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[3] = (MS_U8*)&(pCfg->stSet); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_VIP_ICC_SETTING_Main,p8PQType[3]); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_ICC_Main,PQ_IP_VIP_ICC_dither_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_ICC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.sticc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++ ++unsigned char MDrv_VIP_SetIHCICCADPYConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_IHCICC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_Ymode_Yvalue_SETTING_Main-PQ_IP_VIP_Ymode_Yvalue_ALL_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stYmdall); ++ p8PQType[1] = (MS_U8*)&(pCfg->stYmdset); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_Ymode_Yvalue_ALL_Main,PQ_IP_VIP_Ymode_Yvalue_SETTING_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_IHCICC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stihcicc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetIBCConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_IBC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_IBC_SETTING_Main-PQ_IP_VIP_IBC_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stEn); ++ p8PQType[1] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[2] = (MS_U8*)&(pCfg->stSet); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_IBC_Main,PQ_IP_VIP_IBC_SETTING_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_IBC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stibc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetFCCConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_FCC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_FCC_T9_Main-PQ_IP_VIP_FCC_T1_Main+2)]; ++ p8PQType[9] = (MS_U8*)&(pCfg->stfr); ++ p8PQType[0] = (MS_U8*)&(pCfg->stT[0]); ++ p8PQType[1] = (MS_U8*)&(pCfg->stT[1]); ++ p8PQType[2] = (MS_U8*)&(pCfg->stT[2]); ++ p8PQType[3] = (MS_U8*)&(pCfg->stT[3]); ++ p8PQType[4] = (MS_U8*)&(pCfg->stT[4]); ++ p8PQType[5] = (MS_U8*)&(pCfg->stT[5]); ++ p8PQType[6] = (MS_U8*)&(pCfg->stT[6]); ++ p8PQType[7] = (MS_U8*)&(pCfg->stT[7]); ++ p8PQType[8] = (MS_U8*)&(pCfg->stT9); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_VIP_FCC_full_range_Main,p8PQType[9]); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_FCC_T1_Main,PQ_IP_VIP_FCC_T9_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_FCC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stfcc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++ ++unsigned char MDrv_VIP_SetACKConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_ACK_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_YCbCr_Clip_Main-PQ_IP_VIP_ACK_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stACK); ++ p8PQType[1] = (MS_U8*)&(pCfg->stclip); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_VIP_ACK_Main,PQ_IP_VIP_YCbCr_Clip_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_ACK_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stack,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetNLMConfig(void *pvCfg) ++{ ++ MS_U8 *stNLM = NULL; ++ ST_IOCTL_VIP_NLM_CONFIG *pCfg = pvCfg; ++ stNLM = (MS_U8*)&(pCfg->stNLM); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(_IsNotOpenVIPBypass()) ++ { ++ _MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_NLM_Main,stNLM); ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_NLM_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stnlm,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetNLMSRAMConfig(ST_IOCTL_VIP_NLM_SRAM_CONFIG stSRAM) ++{ ++ ST_VIP_NLM_SRAM_CONFIG stCfg; ++ stCfg.u32baseadr = stSRAM.u32Baseadr; ++ stCfg.bCLientEn = stSRAM.bEn; ++ stCfg.u32viradr = stSRAM.u32viradr; ++ stCfg.btrigContinue = 0; //single ++ stCfg.u16depth = VIP_NLM_ENTRY_NUM; // entry ++ stCfg.u16reqlen = VIP_NLM_ENTRY_NUM; ++ stCfg.u16iniaddr = 0; ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s, flag:%hhx ,addr:%lx,addr:%lx \n", __FUNCTION__,stSRAM.bEn,stSRAM.u32viradr,stSRAM.u32Baseadr); ++ Drv_VIP_SetNLMSRAMConfig(stCfg); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetSNRConfig(void *pvCfg) ++{ ++ MS_U8 *stSNR = NULL; ++ ST_IOCTL_VIP_SNR_CONFIG *pCfg = pvCfg; ++ stSNR = (MS_U8*)&(pCfg->stSNR); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(_IsNotOpenVIPBypass()) ++ { ++ _MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_PreSNR_Main,stSNR); ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_SNR_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stsnr,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_SetVIPOtherConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_Main-PQ_IP_422to444_Main+2)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->st422_444); ++ p8PQType[1] = (MS_U8*)&(pCfg->stBypass); ++ p8PQType[2] = (MS_U8*)&(pCfg->stLB); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_VIP_LineBuffer_Main,p8PQType[2]); ++ _MDrv_VIP_For_SetEachPQTypeByIP(PQ_IP_422to444_Main,PQ_IP_VIP_Main,pCfg->stFCfg,p8PQType); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_CONFIG,(void *)pCfg); ++ return TRUE; ++} ++void MDrv_VIP_CheckRegister(void) ++{ ++ SCL_ERR( "[MDRVVIP]%s \n", __FUNCTION__); ++ MDRv_PQ_Check_Type(0,PQ_CHECK_REG); ++ MDrv_VIP_Resume(); ++ MDRv_PQ_Check_Type(0,PQ_CHECK_OFF); ++} ++ ++void MDrv_VIP_CheckConsist(void) ++{ ++ SCL_ERR( "[MDRVVIP]%s \n", __FUNCTION__); ++ MDRv_PQ_Check_Type(0,PQ_CHECK_SIZE); ++ MDrv_VIP_Resume(); ++ MDRv_PQ_Check_Type(0,PQ_CHECK_OFF); ++} ++void MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_TYPE enCheckType) ++{ ++ SCL_ERR( "[MDRVVIP]%s CHECK_TYPE:%hhd \n", __FUNCTION__,enCheckType); ++ gbVIPCheckCMDQorPQ = enCheckType; ++ if(_IsAutoSetting()) ++ { ++ _Set_SuspendResetFlag(0x3FFFF); ++ } ++ _MDrv_VIP_For_PrepareCheckSetting(); ++ ++ ++ if(_IsCMDQNeedToReturnOrigin()) ++ { ++ _MDrv_VIP_WaitForCMDQDone(); ++ } ++ else ++ { ++ _MDrv_VIP_SetCMDQAfterPollTimeoutSkip(1);//not wait ++ } ++} ++unsigned char MDrv_VIP_SetVIPBypassConfig(EN_VIP_CONFIG_TYPE enVIPtype) ++{ ++ if(enVIPtype) ++ { ++ gu32OpenBypass |= enVIPtype; ++ if(enVIPtype&EN_VIP_CONFIG) ++ { ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_CONFIG, EN_VIP_CONFIG); ++ } ++ if(enVIPtype&EN_VIP_DNR_CONFIG) ++ { ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_DNR_CONFIG, EN_VIP_DNR_CONFIG); ++ } ++ if(enVIPtype&EN_VIP_SNR_CONFIG) ++ { ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_SNR_CONFIG, EN_VIP_SNR_CONFIG); ++ } ++ if(enVIPtype&EN_VIP_NLM_CONFIG) ++ { ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_NLM_CONFIG, EN_VIP_NLM_CONFIG); ++ } ++ if(enVIPtype&EN_VIP_LDC_CONFIG) ++ { ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_LDC_CONFIG, EN_VIP_LDC_CONFIG); ++ } ++ } ++ else ++ { ++ gu32OpenBypass = enVIPtype; ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_CONFIG, EN_VIP_CONFIG); ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_DNR_CONFIG, EN_VIP_DNR_CONFIG); ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_SNR_CONFIG, EN_VIP_SNR_CONFIG); ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_NLM_CONFIG, EN_VIP_NLM_CONFIG); ++ _MDrv_VIP_SetBypassIP(enVIPtype&EN_VIP_LDC_CONFIG, EN_VIP_LDC_CONFIG); ++ } ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_CMDQWriteConfig(ST_IOCTL_VIP_CMDQ_CONFIG *pCfg) ++{ ++ MS_U32 u32Addr; ++ MS_U16 u16Data,u16Mask; ++ MS_U8 u8framecnt; ++ MS_U8 bfire,bUseFrameCntCMD; ++ ++ bfire = pCfg->bfire; ++ bUseFrameCntCMD = pCfg->bCnt; ++ u32Addr = pCfg->u32Addr; ++ u16Data = pCfg->u16Data; ++ u16Mask = pCfg->u16Mask; ++ u8framecnt = pCfg->u8framecnt; ++ if(bfire) ++ { ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,bfire); ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, fire\n", __FUNCTION__); ++ } ++ else if(bUseFrameCntCMD) ++ { ++ if(Drv_CMDQ_AssignFrameWriteCmd(u32Addr,u16Data,u16Mask,u8framecnt) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s,Write Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ } ++ else ++ { ++ if(Drv_CMDQ_WriteCmd(u32Addr,u16Data,u16Mask,0) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s,No frame cmd Write Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ } ++ return TRUE; ++ ++} ++unsigned char MDrv_VIP_SetLDCConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_LDC_CONFIG *pCfg = pvCfg; ++ if(_IsDNRBufferAllocatedReady()) ++ { ++ MS_U8 *stEn = NULL,*stmd = NULL; ++ stEn = (MS_U8*)&(pCfg->stEn); ++ stmd = (MS_U8*)&(pCfg->stmd); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ _MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ _MDrv_VIP_SetPQByType(PQ_IP_LDC_422_444_422_Main,stmd); ++ Drv_VIP_SetLDCOnConfig(pCfg->stEn.bEn_ldc); ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_LDC_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldc,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,DNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++unsigned char MDrv_VIP_SetLDCmdConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_LDC_MD_CONFIG *pCfg = pvCfg; ++ if(_IsDNRBufferAllocatedReady()) ++ { ++ ST_VIP_LDC_MD_CONFIG stLDCCfg; ++ stLDCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stLDCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ stLDCCfg.bEnSWMode = pCfg->bEnSWMode; ++ stLDCCfg.u8FBidx = pCfg->u8FBidx; ++ stLDCCfg.u8FBrwdiff = pCfg->u8FBrwdiff; ++ stLDCCfg.enbypass = pCfg->enbypass; ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(Drv_VIP_SetLDCMdConfig(stLDCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ return FALSE; ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_LDC_MD_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldcmd,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,DNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++unsigned char MDrv_VIP_SetLDCDmapConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_LDC_DMAP_CONFIG *pCfg = pvCfg; ++ if(_IsDNRBufferAllocatedReady()) ++ { ++ ST_VIP_LDC_DMAP_CONFIG stLDCCfg; ++ stLDCCfg.bEnPowerSave = pCfg->bEnPowerSave; ++ stLDCCfg.u32DMAPaddr = pCfg->u32DMAPaddr; ++ stLDCCfg.u16DMAPWidth = pCfg->u16DMAPWidth; ++ stLDCCfg.u8DMAPoffset = pCfg->u8DMAPoffset; ++ stLDCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stLDCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(Drv_VIP_SetLDCDmapConfig(stLDCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ return FALSE; ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_LDC_DMAP_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldcdmap,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,DNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++unsigned char MDrv_VIP_SetLDCSRAMConfig(void *pvCfg) ++{ ++ ST_IOCTL_VIP_LDC_SRAM_CONFIG *pCfg = pvCfg; ++ if(_IsDNRBufferAllocatedReady()) ++ { ++ ST_VIP_LDC_SRAM_CONFIG stLDCCfg; ++ stLDCCfg.u16SRAMhorstr = pCfg->u16SRAMhorstr; ++ stLDCCfg.u16SRAMverstr = pCfg->u16SRAMverstr; ++ stLDCCfg.u32loadhoraddr = pCfg->u32loadhoraddr; ++ stLDCCfg.u32loadveraddr = pCfg->u32loadveraddr; ++ stLDCCfg.u16SRAMhoramount = pCfg->u16SRAMhoramount; ++ stLDCCfg.u16SRAMveramount = pCfg->u16SRAMveramount; ++ stLDCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stLDCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ ++ if(Drv_VIP_SetLDCSRAMConfig(stLDCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ return FALSE; ++ } ++ ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_LDC_SRAM_CONFIG,(void *)pCfg); ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldcsram,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,DNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++MS_BOOL MDrv_VIP_VtrackEnable( unsigned char u8FrameRate, EN_VIP_IOCTL_VTRACK_ENABLE_TYPE bEnable) ++{ ++ Drv_VIP_VtrackEnable(u8FrameRate, bEnable); ++ return 1; ++} ++MS_BOOL MDrv_VIP_VtrackSetPayloadData(unsigned short u16Timecode, unsigned char u8OperatorID) ++{ ++ Drv_VIP_VtrackSetPayloadData(u16Timecode,u8OperatorID); ++ return 1; ++} ++MS_BOOL MDrv_VIP_VtrackSetKey(unsigned char bUserDefinded, unsigned char *pu8Setting) ++{ ++ Drv_VIP_VtrackSetKey(bUserDefinded,pu8Setting); ++ return 1; ++} ++ ++MS_BOOL MDrv_VIP_VtrackSetUserDefindedSetting(unsigned char bUserDefinded, unsigned char *pu8Setting) ++{ ++ Drv_VIP_VtrackSetUserDefindedSetting(bUserDefinded,pu8Setting); ++ return 1; ++} ++MS_BOOL MDrv_VIP_VtrackInit(void) ++{ ++ Drv_VIP_VtrackSetUserDefindedSetting(0,NULL); ++ Drv_VIP_VtrackSetPayloadData(0,0); ++ Drv_VIP_VtrackSetKey(0,NULL); ++ return 1; ++} ++ssize_t MDrv_VIP_ProcShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ str += scnprintf(str, end - str, "Command IP Status\n"); ++ str += scnprintf(str, end - str, "----------------------------------------------\n"); ++ str += scnprintf(str, end - str, " 0 Normal ALL %s\n",(gu32OpenBypass) ? "No" :"Yes"); ++ str += scnprintf(str, end - str, " 1 Bypass ALL %s\n",(gu32OpenBypass==0x7FFFF) ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " 2 VIP Bypass %s\n", Drv_VIP_GetBypassStatus(EN_VIP_CONFIG) ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " 3 DNR %s\n", Drv_VIP_GetBypassStatus(EN_VIP_DNR_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " 4 SNR %s\n", Drv_VIP_GetBypassStatus(EN_VIP_SNR_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " 5 NLM %s\n", Drv_VIP_GetBypassStatus(EN_VIP_NLM_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " 6 LDC %s\n", Drv_VIP_GetBypassStatus(EN_VIP_LDC_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, "----------------------------------------------\n"); ++ str += scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_VIP_CMDQShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned long long u64DramMsg; ++ unsigned short u16Count; ++ unsigned short idx,reserve = 0; ++ unsigned char bRotate; ++ MS_CMDQ_Info stCMDQinfo = Drv_CMDQ_GetCMDQInformation(EN_CMDQ_TYPE_IP0); ++ if(stCMDQinfo.u16WPoint >= stCMDQinfo.u16LPoint) ++ { ++ u16Count = stCMDQinfo.u16WPoint - stCMDQinfo.u16LPoint; ++ } ++ else ++ { ++ u16Count = stCMDQinfo.u16WPoint + stCMDQinfo.u16MaxCmdCnt-stCMDQinfo.u16LPoint; ++ bRotate = 1; ++ } ++ str += scnprintf(str, end - str, "========================CMDQ STATUS======================\n"); ++ str += scnprintf(str, end - str, "---------------------- SW INFORMATION -------------------\n"); ++ str += scnprintf(str, end - str, "CMDQ Current CMD End Pointer :%hd\n",stCMDQinfo.u16WPoint); ++ str += scnprintf(str, end - str, "CMDQ Last Time Trigger Pointer :%hd\n",stCMDQinfo.u16RPoint); ++ str += scnprintf(str, end - str, "CMDQ Last Time Trigger COUNT :%hd\n",u16Count); ++ str += scnprintf(str, end - str, "CMDQ Fire Pointer :%hd\n",stCMDQinfo.u16FPoint); ++ str += scnprintf(str, end - str, "CMDQ assign CMD Pointer :%hd\n",stCMDQinfo.u16assFrame_Point); ++ str += scnprintf(str, end - str, "---------------------- HW INFORMATION -------------------\n"); ++ str += scnprintf(str, end - str, "CMDQ Start :%lx\n",stCMDQinfo.PhyAddr); ++ str += scnprintf(str, end - str, "CMDQ End :%lx\n",stCMDQinfo.PhyAddrEnd); ++ str += scnprintf(str, end - str, "CMDQ Max CMD One shot :%hd\n",stCMDQinfo.u16MaxCmdCnt); ++ str += scnprintf(str, end - str, "CMDQ Non-FrameCnt CMD Buffer :%hd\n",stCMDQinfo.u16BufCmdCnt); ++ str += scnprintf(str, end - str, "---------------------- DRAM INFORMATION -----------------\n"); ++ for(idx=0;idx %lx\n",idx,u64DramMsg,Drv_CMDQ_GetCMDBankFromCMD(u64DramMsg)); ++ } ++ else ++ { ++ u64DramMsg = Drv_CMDQ_GetCMDFromPoint(stCMDQinfo.u16LPoint+idx); ++ str += scnprintf(str, end - str, "%hd:%llx => %lx\n",idx,u64DramMsg,Drv_CMDQ_GetCMDBankFromCMD(u64DramMsg)); ++ } ++ } ++ str += scnprintf(str, end - str, "========================CMDQ STATUS======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_VIP_VIPShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ str += scnprintf(str, end - str, " IP Status\n"); ++ str += scnprintf(str, end - str, "---------------------------------------\n"); ++ str += scnprintf(str, end - str, " Normal ALL %s\n",(gu32OpenBypass) ? "No" :"Yes"); ++ str += scnprintf(str, end - str, " Bypass ALL %s\n",(gu32OpenBypass==0x7FFFF) ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " VIP Bypass %s\n", Drv_VIP_GetBypassStatus(EN_VIP_CONFIG) ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " DNR %s\n", Drv_VIP_GetBypassStatus(EN_VIP_DNR_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " SNR %s\n", Drv_VIP_GetBypassStatus(EN_VIP_SNR_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " NLM %s\n", Drv_VIP_GetBypassStatus(EN_VIP_NLM_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " LDC %s\n", Drv_VIP_GetBypassStatus(EN_VIP_LDC_CONFIG) ? "Bypass" :"ON"); ++ str += scnprintf(str, end - str, " ACK %s\n", gstSupCfg.stack.stACK.backen ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " IBC %s\n", gstSupCfg.stibc.stEn.bIBC_en ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " ICC %s\n", gstSupCfg.sticc.stEn.bICC_en ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " IHC %s\n", gstSupCfg.stihc.stOnOff.bIHC_en? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC1 %s\n", gstSupCfg.stfcc.stT[0].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC2 %s\n", gstSupCfg.stfcc.stT[1].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC3 %s\n", gstSupCfg.stfcc.stT[2].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC4 %s\n", gstSupCfg.stfcc.stT[3].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC5 %s\n", gstSupCfg.stfcc.stT[4].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC6 %s\n", gstSupCfg.stfcc.stT[5].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC7 %s\n", gstSupCfg.stfcc.stT[6].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC8 %s\n", gstSupCfg.stfcc.stT[7].bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " FCC9 %s\n", gstSupCfg.stfcc.stT9.bEn ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " UVC %s\n", gstSupCfg.stuvc.stUVC.buvc_en? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " DLC CURVEFITPW %s\n", gstSupCfg.stdlc.stEn.bcurve_fit_var_pw_en? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " DLC CURVEFIT %s\n", gstSupCfg.stdlc.stEn.bcurve_fit_en? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " DLC STATISTIC %s\n", gstSupCfg.stdlc.stEn.bstatistic_en? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " LCE %s\n", gstSupCfg.stlce.stOnOff.bLCE_En ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, " PK %s\n", gstSupCfg.stpk.stOnOff.bpost_peaking_en ? "ON" :"OFF"); ++ str += scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ return (str - buf); ++} +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/cmdq/drvCMDQ.c b/drivers/mstar/scl/infinity/src/mxlib/drv/cmdq/drvCMDQ.c +new file mode 100644 +index 00000000..ef2f5463 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/cmdq/drvCMDQ.c +@@ -0,0 +1,1298 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// file drvCMDQ.c ++// @brief CMDQ Driver ++// @author MStar Semiconductor,Inc. ++// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++#define DRV_CMDQ_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsIRQ.h" ++#include "MsOS.h" ++#include "MsVersion.h" ++#include "MsDevice.h" ++ ++#include ++#include ++ ++#include "drvCMDQ.h" ++#include "halCMDQ.h" ++#include "regCMDQ.h" ++#include "halCHIP.h" ++#include "irqs.h" ++#include ++#include "mdrv_scl_dbg.h" ++ ++static MS_CMDQ_Info gstCMDQInfo[EN_CMDQ_TYPE_MAX] = {{0,0,0,0,0,0,0,FALSE,0,0,NULL}}; ++static MS_U8 gCMDQStatusFlag[EN_CMDQ_TYPE_MAX]; ++static CMDQ_Buffer_MIU gstMIUSel[EN_CMDQ_TYPE_MAX]; ++//-------------------------------------------------------------------------------------------------- ++// Global Variable ++//-------------------------------------------------------------------------------------------------- ++static MS_U32 gu32CMDQMode; ++static EN_CMDQ_IP_TYPE gstCurrworkIP; ++static MS_U32 gu32LasttimeFramecnt;//1.last time isp cnt ++MS_BOOL gbISRopen; ++MS_U16 gu16ISRflag; ++MS_S32 _gCMDQHVSPMUTEX = -1; ++static MS_S32 _gs32CMDQMutex = -1; ++#define CMDQ_MUTEX_CREATE() _gs32CMDQMutex = MsOS_CreateMutex(E_MSOS_FIFO, "CMDQMUTEX" , MSOS_PROCESS_SHARED) ++#define CMDQ_MUTEX_LOCK() MsOS_ObtainMutex(_gs32CMDQMutex,MSOS_WAIT_FOREVER) ++#define CMDQ_MUTEX_UNLOCK() MsOS_ReleaseMutex(_gs32CMDQMutex) ++#define CMDQ_MUTEX_DELETE() MsOS_DeleteMutex(_gs32CMDQMutex) ++#define _AlignTo(value, align) ( ((value) + ((align)-1)) & ~((align)-1) ) ++#define _NonFrameCountCMDCount() (gstCMDQInfo[gstCurrworkIP].u16WPoint-gstCMDQInfo[gstCurrworkIP].u16assFrame_Point) ++#define _NonFrameCountCMDCount_Ring() (gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt-\ ++ gstCMDQInfo[gstCurrworkIP].u16assFrame_Point+gstCMDQInfo[gstCurrworkIP].u16WPoint) ++#define _CMDQGetAddr(u16Point) (gstCMDQInfo[gstCurrworkIP].u32VirAddr + ((u16Point)* MS_CMDQ_CMD_LEN) ) ++#define _CMDQGetCMD(u8type,u32Addr,u16Data,u16Mask) ((MS_U64)(((MS_U64)(u8type)<<(14*4))|((MS_U64)(u32Addr)<<(8*4))|\ ++ ((MS_U64)(u16Data)<<(4*4))|((MS_U64)(u16Mask)))) ++#define _IsIspCountReset(u8isp_cnt,u8framecnt) (((gu32LasttimeFramecnt)>(u8isp_cnt))&&\ ++ ((gu32LasttimeFramecnt)>(u8framecnt))) ++#define _IsAssignCountReset(u8isp_cnt,u8framecnt) ((u8framecnt=(u8framecnt))) ++#define _IsFrameCountError(u8isp_cnt,u8framecnt,u8allowframeerror) (((MS_S16)u8isp_cnt)>(MS_S16)((u8framecnt)+(u8allowframeerror)))\ ++ &&((u8isp_cnt-u8framecnt)<10) ++#define _IsFrameCountWarn(u8isp_cnt,u8framecnt,u8allowframeerror) (((MS_S16)(u8isp_cnt)-(MS_S16)(u8framecnt))>=0&&\ ++ ((MS_S16)(u8isp_cnt)-(MS_S16)(u8framecnt))<=(u8allowframeerror)) ++#define _IsFirstNonFrameCountCMD() ((!((gCMDQStatusFlag[EN_CMDQ_TYPE_IP0])&CMDQ_FLAG_FRAMECNT_CMD))&& \ ++ ((gCMDQStatusFlag[EN_CMDQ_TYPE_IP0])&CMDQ_FLAG_FIRST_NONFRAMECNT)) ++#define _IsCMDQExecuteDone() (R2BYTEMSK(REG_CMDQ_44_L, 0x0003)==0x3 && R2BYTEMSK(REG_CMDQ_45_L, 0x0800)) ++#define _IsCMDQExecuteDoneISR() (((gu16ISRflag&0x4) == 0x4) && R2BYTEMSK(REG_CMDQ_45_L, 0x0800)) ++#define _IsCMDQIPIdle() (R2BYTEMSK(REG_CMDQ_45_L, 0x0800)) ++#define _IsCMDQDMADone() (R2BYTEMSK(REG_CMDQ_45_L, 0x0002)) ++#define _IsFlagType(IpNum,u8type) (gCMDQStatusFlag[IpNum] & (u8type)) ++#define _SetFlagType(IpNum,u8type) (gCMDQStatusFlag[IpNum] |= (u8type)) ++#define _ReSetFlagType(IpNum,u8type) (gCMDQStatusFlag[IpNum] &= ~(u8type)) ++#define _IsThisCmdAddrAlreadyExist(u32addr,u64cpcmd) (u32addr==((MS_U32)((u64cpcmd &0xFFFFFFFF00000000)>>32))) ++#define _IsIdxLargeThan(u32ShiftIdx,u16Num) (u32ShiftIdx>u16Num) ++//-------------------------------------------------------------------------------------------------- ++// Debug Function ++//-------------------------------------------------------------------------------------------------- ++#define CMDQDBG(x) ++#define CMDQERR(x) x ++#define CMDQCMD128 0 //one cmd 64bit but add one null cmd ++#define NotToCheckSameAddr 1 ++#define ToCheckSameAddr 0 ++#define RETURN_ERROR 2 ++#define CheckingTimes 35 ++//#define INT_IRQ_CMDQ 52 ++//-------------------------------------------------------------------------------------------------- ++// Global Function ++//-------------------------------------------------------------------------------------------------- ++ ++//--------------------------------------------------------------------------- ++///Get MMIO_Base and set struct _REG_CMDQCtrl * _CMDQCtrl ++//--------------------------------------------------------------------------- ++ ++ ++ ++//DRV----------------------------------------------------------------------------------------------- ++MS_U32 _Drv_CMDQ_SetRingTrigPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr) ++{ ++ Hal_CMDQ_SetOffsetPointer(enIPType,StartAddr); ++ return 1; ++} ++ ++MS_U32 _Drv_CMDQ_SetStartPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr) ++{ ++ Hal_CMDQ_SetStartPointer(enIPType,StartAddr); ++ return DRVCMDQ_OK; ++} ++ ++MS_U32 _Drv_CMDQ_SetEndPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 EndAddr) ++{ ++ Hal_CMDQ_SetEndPointer(enIPType,EndAddr); ++ return DRVCMDQ_OK; ++} ++ ++MS_U32 _Drv_CMDQ_SetTimerRatio(EN_CMDQ_IP_TYPE enIPType,MS_U32 u32time,MS_U32 u32ratio) ++{ ++ Hal_CMDQ_SetTimer(enIPType, u32time); ++ Hal_CMDQ_SetRatio(enIPType, u32ratio); ++ return DRVCMDQ_OK; ++} ++MS_U64 *_Drv_CMDQ_GetPointerFromPoint(MS_U16 u16Point,MS_U64 *pu32Addr) ++{ ++ MS_PHYADDR DstAddr; ++ DstAddr = _CMDQGetAddr(u16Point); ++ pu32Addr = (MS_U64 *)(DstAddr); ++ return pu32Addr; ++} ++void _Drv_CMDQ_SetCmdToPointer(MS_U64 u64Cmd ,MS_BOOL bSkipCheckSameAddr,MS_U64 *pu32Addr) ++{ ++ if(!bSkipCheckSameAddr) ++ { ++ *pu32Addr = ((u64Cmd &0xFFFFFFFFFFFF0000)|0x0000); ++ } ++ else ++ { ++ *pu32Addr =u64Cmd ; ++ } ++} ++void _Drv_CMDQ_AddCmd(MS_U64 u64Cmd ,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_U64 *pu32Addr = NULL; ++ pu32Addr = _Drv_CMDQ_GetPointerFromPoint(gstCMDQInfo[gstCurrworkIP].u16assFrame_Point,pu32Addr); ++ _Drv_CMDQ_SetCmdToPointer(u64Cmd,bSkipCheckSameAddr,pu32Addr); ++ gstCMDQInfo[gstCurrworkIP].u16WPoint++; ++ gstCMDQInfo[gstCurrworkIP].u16assFrame_Point++; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]add u16WPoint=%d u16assFrame_Point=%d\n" ++ ,gstCMDQInfo[gstCurrworkIP].u16WPoint,gstCMDQInfo[gstCurrworkIP].u16assFrame_Point); ++} ++MS_U32 _Drv_CMDQ_GetCmdDiffCnt(void) ++{ ++ MS_U32 cmddiffcnt; ++ if(gstCMDQInfo[gstCurrworkIP].u16WPoint>32) ; ++ if((u32BankAddr&0x0000FF)>=0x80) // odd bank ++ { ++ u16Addr = (MS_U16)((u32BankAddr&0x0000FF)-0x80); ++ } ++ else // even bank ++ { ++ u16Addr = (MS_U16)(u32BankAddr&0x0000FF); ++ } ++ u32Bank = (MS_U32)(((u32BankAddr - u16Addr))*2) ; ++ u32BankAddr = (MS_U32)(u32Bank + u16Addr); ++ ++ return u32BankAddr; ++} ++void _Drv_CMDQ_WaitForCPUWriteToDMem(void) ++{ ++ Chip_Flush_MIU_Pipe(); //wait for CPU write to mem ++} ++void Drv_CMDQ_SetRPoint(EN_CMDQ_IP_TYPE enIPType) ++{ ++ gstCMDQInfo[enIPType].u16LPoint = gstCMDQInfo[enIPType].u16RPoint; ++ gstCMDQInfo[enIPType].u16RPoint = ++ (gstCMDQInfo[enIPType].u16FPoint>0)? (gstCMDQInfo[enIPType].u16FPoint-1): gstCMDQInfo[enIPType].u16MaxCmdCnt; ++} ++MS_U32 _Drv_CMDQ_GetEndCmdAddr(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 u32EndAddr = 0; ++ gstCMDQInfo[enIPType].u16FPoint = gstCMDQInfo[enIPType].u16WPoint + 1; ++ gstCMDQInfo[enIPType].u16assFrame_Point = gstCMDQInfo[enIPType].u16WPoint; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]u16WPoint=%u u16RPoint=%u u16assFramePoint=%u\n", ++ gstCMDQInfo[enIPType].u16WPoint, ++ gstCMDQInfo[enIPType].u16RPoint, ++ gstCMDQInfo[enIPType].u16assFrame_Point); ++ ++ u32EndAddr = gstCMDQInfo[enIPType].PhyAddr+ ++ (((gstCMDQInfo[enIPType].u16FPoint)/MS_CMDQ_CMD_ALIGN)*MS_CMDQ_MEM_BASE_UNIT); ++ return u32EndAddr; ++} ++MS_BOOL _Drv_CMDQ_Fire(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart) ++{ ++ MS_U32 u32EndAddr = 0; ++ MS_U8 ret=0; ++ ++ u32EndAddr = _Drv_CMDQ_GetEndCmdAddr(enIPType); ++ ret =_Drv_CMDQ_SetRingTrigPointer(enIPType,u32EndAddr); //in function,addr already add 1 ++ _Drv_CMDQ_WaitForCPUWriteToDMem(); ++ if(ret) ++ { ++ _Drv_CMDQ_CheckMIUAddr(); ++ _Drv_CMDQ_BeTrigger(enIPType,bStart); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]go CMDQ u32EndAddr:%lx\n",u32EndAddr); ++ } ++ else ++ { ++ CMDQERR(printf("[CMDQ]Fire fail!!!\n")); ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++MS_U8 _Drv_CMDQ_SetBufferConfig(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr, MS_U32 EndAddr) ++{ ++ MS_U8 ret,ret2; ++ ret = _Drv_CMDQ_SetStartPointer(enIPType,StartAddr); ++ ret2 = _Drv_CMDQ_SetEndPointer(enIPType,EndAddr); ++ _Drv_CMDQ_SetRingTrigPointer(enIPType,StartAddr); ++ if((ret==DRVCMDQ_OK)&&(ret2==DRVCMDQ_OK)) ++ return 1; ++ else ++ return 0; ++} ++void _Drv_CMDQ_Init(MS_U32 phyAddr1) ++{ ++ if (phyAddr1 >= HAL_MIU1_BASE) ++ { ++ gstMIUSel[0].u8MIUSel_IP = EN_CMDQ_MIU_1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]%s: Init BF1 at MIU 1\n" ++ ,__FUNCTION__); ++ } ++ else ++ { ++ gstMIUSel[0].u8MIUSel_IP = EN_CMDQ_MIU_0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]%s: Init BF1 at MIU 0 \n" ++ ,__FUNCTION__); ++ } ++ gu32CMDQMode = RING_BUFFER_MODE; ++ gu32LasttimeFramecnt = 0; ++ gstCurrworkIP = EN_CMDQ_TYPE_IP0; ++} ++MS_U32 _Drv_CMDQ_InitByIP(EN_CMDQ_IP_TYPE enIPType) ++{ ++ char word[] = {"_CMDQ_Mutex"}; ++ ++ Hal_CMDQ_Setmiusel(enIPType, gstMIUSel[enIPType].u8MIUSel_IP); ++ _Drv_CMDQ_AddNull(enIPType);//add 2 null ++ gstCMDQInfo[enIPType].u16FPoint = gstCMDQInfo[enIPType].u16WPoint + 1; ++ gstCMDQInfo[enIPType].u16assFrame_Point= gstCMDQInfo[enIPType].u16WPoint; ++ Hal_CMDQ_SetBaseEn(enIPType, ENABLE); ++ Hal_CMDQ_SetTrigAlways(enIPType, ENABLE); ++ Hal_CMDQ_Reset(enIPType, ENABLE); ++ Hal_CMDQ_Reset(enIPType, DISABLE); ++ ++ if(FALSE == Hal_CMDQ_SetDMAMode(enIPType, gu32CMDQMode)) ++ { ++ CMDQERR(printf("[CMDQ]\033[35mCMDQ Set Mode FAIL!!\033[m\n")); ++ return DRVCMDQ_FAIL; ++ } ++ ++ /* the polling_timer is for re-checking polling value, ++ if the time_interval is too small, cmdq will polling RIU frequently, so that RIU will very busy */ ++ _Drv_CMDQ_SetTimerRatio(enIPType, CMDQ_poll_timer, CMDQ_timer_ratio); ++ // set time / ratio, total wait time is (wait_time * (ratio + 1)) => ( FF * (F + 1) / 216 MHz ) = sec ++ //4D*1=4D~=77 *(216/M) 1 ~=60(frame/s) ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(enIPType, 0); ++ ++ _Drv_CMDQ_SetBufferConfig(enIPType, gstCMDQInfo[enIPType].PhyAddr,gstCMDQInfo[enIPType].PhyAddrEnd); ++ Hal_CMDQ_WriteRegDirect(0x12183C,0xFFFF);//clear sctop irq ++ Hal_CMDQ_WriteRegDirect(0x121838,0xFFFD);//mask ++ Hal_CMDQ_ResetSoftInterrupt(enIPType); ++ Hal_CMDQ_SetISRMSK(enIPType,0xE0F8); ++ _gCMDQHVSPMUTEX = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ if (_gCMDQHVSPMUTEX == -1) ++ { ++ CMDQERR(printf("%s: Init MUTEX fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++//--------------------------- irq ++ return DRVCMDQ_OK; ++} ++//function----------------------------------------------------------------------------- ++void _Drv_CMDQ_AddNullToNonFrameCntBuffer(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U64 nullcmd=MS_CMDQ_NULL_CMD; ++ do ++ { ++ _Drv_CMDQ_AddCmdToNonFrameCntBuffer((MS_U64)nullcmd, ToCheckSameAddr); ++ _Drv_CMDQ_ResetCmdPointIfBottom(enIPType); ++ }while (gstCMDQInfo[enIPType].u16WPoint%MS_CMDQ_CMD_ALIGN != 0); ++} ++CMDQ_CheckCmdinfo _Drv_CMDQ_FillCheckCmdInfo(MS_BOOL bframecount,MS_U64 u64Cmd) ++{ ++ CMDQ_CheckCmdinfo stCMDQChkinfo; ++ stCMDQChkinfo.bframecount = bframecount; ++ stCMDQChkinfo.u32addr = (MS_U32)((u64Cmd &0xFFFFFFFF00000000)>>32); ++ stCMDQChkinfo.u16mask = (MS_U16)(u64Cmd &0xFFFF); ++ stCMDQChkinfo.u16data = (MS_U16)((u64Cmd>>16) &0xFFFF); ++ if(bframecount) //frame count ++ { ++ stCMDQChkinfo.u16StartPoint = gstCMDQInfo[gstCurrworkIP].u16RPoint; ++ if(gstCMDQInfo[gstCurrworkIP].u16assFrame_Point>0) ++ { ++ stCMDQChkinfo.u16EndPoint = gstCMDQInfo[gstCurrworkIP].u16assFrame_Point-1;//for read last time cmd ++ } ++ else ++ { ++ stCMDQChkinfo.u16EndPoint = gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt-1; ++ } ++ ++ if (stCMDQChkinfo.u16EndPoint+1==stCMDQChkinfo.u16StartPoint) ++ { ++ stCMDQChkinfo.Ret = 1; ++ return stCMDQChkinfo; ++ } ++ ++ if(stCMDQChkinfo.u16EndPoint+1>=stCMDQChkinfo.u16StartPoint) ++ { ++ stCMDQChkinfo.u32CmdDiffCnt = stCMDQChkinfo.u16EndPoint+1-stCMDQChkinfo.u16StartPoint; ++ } ++ else //ring ++ { ++ stCMDQChkinfo.u32CmdDiffCnt = ++ stCMDQChkinfo.u16EndPoint+1+(gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt-stCMDQChkinfo.u16StartPoint); ++ } ++ ++ } ++ else //nonframe count ++ { ++ stCMDQChkinfo.u16StartPoint = gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt; ++ if(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_ROTATION)) //full ++ { ++ stCMDQChkinfo.u32CmdDiffCnt = gstCMDQInfo[gstCurrworkIP].u16BufCmdCnt; ++ stCMDQChkinfo.u32ActualCmdDiffCnt = _NonFrameCountCMDCount(); ++ } ++ else ++ { ++ stCMDQChkinfo.u32CmdDiffCnt = _NonFrameCountCMDCount(); ++ } ++ stCMDQChkinfo.u16EndPoint = stCMDQChkinfo.u16StartPoint+stCMDQChkinfo.u32CmdDiffCnt; ++ } ++ return stCMDQChkinfo; ++} ++MS_U16 _Drv_CMDQ_GetCurrentCmdPoint(CMDQ_CheckCmdinfo stCMDQChkinfo, MS_U32 u32ShiftIdx) ++{ ++ MS_U16 u16CurrentPoint; ++ MS_U16 u16Temp; ++ if(((stCMDQChkinfo.u16EndPoint+1)>=stCMDQChkinfo.u16StartPoint) &&stCMDQChkinfo.bframecount) ++ { ++ u16CurrentPoint = (stCMDQChkinfo.u16EndPoint-u32ShiftIdx); ++ } ++ else if(((stCMDQChkinfo.u16EndPoint+1)=u32ShiftIdx)//top ++ { ++ u16CurrentPoint = (stCMDQChkinfo.u16EndPoint-u32ShiftIdx); ++ } ++ else//bottom ++ { ++ u16Temp = u32ShiftIdx-stCMDQChkinfo.u16EndPoint; ++ u16CurrentPoint = (gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt+gstCMDQInfo[gstCurrworkIP].u16BufCmdCnt-u16Temp); ++ } ++ } ++ else if(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_ROTATION) && !stCMDQChkinfo.bframecount) //nonframe count ++ { ++ u16CurrentPoint = (stCMDQChkinfo.u16StartPoint+stCMDQChkinfo.u32ActualCmdDiffCnt-u32ShiftIdx); ++ } ++ else ++ { ++ u16CurrentPoint = (stCMDQChkinfo.u16EndPoint-u32ShiftIdx); ++ } ++ return u16CurrentPoint; ++} ++MS_BOOL _Drv_CMDQ_CheckingAlreadyExist(CMDQ_CheckCmdinfo stCMDQChkinfo) ++{ ++ MS_U64 u64ExistedCmd; ++ MS_U16 u16ExistCmdData; ++ MS_U32 u32ShiftIdx; ++ MS_U16 u16CurrentPoint; ++ for(u32ShiftIdx = 0;u32ShiftIdx>16) &0xFFFF); ++ u16ExistCmdData = ((u16ExistCmdData&stCMDQChkinfo.u16mask) | (~stCMDQChkinfo.u16mask&stCMDQChkinfo.u16data)); ++ u64ExistedCmd = ((u64ExistedCmd &0xFFFFFFFF00000000)|((MS_U32)u16ExistCmdData<<16)|0x0000); ++ if(stCMDQChkinfo.bframecount && _IsIdxLargeThan(u32ShiftIdx,10)) // TO avoid this cmd too far away next cmd. ++ { ++ _Drv_CMDQ_AddCmd(u64ExistedCmd,0); ++#if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++#endif ++ *stCMDQChkinfo.pu32Addr = MS_CMDQ_NULL_CMD; ++ } ++ else if(stCMDQChkinfo.bframecount==0 && _IsIdxLargeThan(u32ShiftIdx,10)) ++ { ++ _Drv_CMDQ_AddCmdToNonFrameCntBuffer(u64ExistedCmd,0); ++#if CMDQCMD128 ++ _Drv_CMDQ_AddNullToNonFrameCntBuffer(gstCurrworkIP); ++#endif ++ *stCMDQChkinfo.pu32Addr = MS_CMDQ_NULL_CMD; ++ } ++ else ++ { ++ *stCMDQChkinfo.pu32Addr = u64ExistedCmd; ++ } ++ stCMDQChkinfo.Ret = 0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]find cmd same address %lx\n" ++ ,stCMDQChkinfo.u32addr); ++ break; ++ } ++#if CMDQCMD128 ++ else if(_IsIdxLargeThan(u32ShiftIdx,CheckingTimes*2)) ++ { ++ stCMDQChkinfo.Ret = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]check over 70\n"); ++ break; ++ } ++#else ++ else if(_IsIdxLargeThan(u32ShiftIdx,CheckingTimes)) ++ { ++ stCMDQChkinfo.Ret = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]check over 35\n"); ++ break; ++ } ++#endif ++ else ++ { ++ stCMDQChkinfo.Ret = 1; ++ } ++ ++ } ++ return stCMDQChkinfo.Ret; ++} ++MS_BOOL _Drv_CMDQ_CheckAddedCmdSameRegPos(MS_U64 u64Cmd,MS_BOOL bframecount,MS_BOOL bSkipCheckSameAddr) ++{ ++ CMDQ_CheckCmdinfo stCMDQChkinfo; ++ if (bSkipCheckSameAddr) ++ { ++ stCMDQChkinfo.Ret = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]bSkipCheckSameAddr check cmd repeat:%hhx\n" ++ ,bSkipCheckSameAddr); ++ return stCMDQChkinfo.Ret; ++ } ++ stCMDQChkinfo = _Drv_CMDQ_FillCheckCmdInfo(bframecount,u64Cmd); ++ if(stCMDQChkinfo.Ret) ++ { ++ return stCMDQChkinfo.Ret; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]u16EndPoint:%hd u16StartPoint:%hd u32CmdDiffCnt:%ld\n" ++ ,stCMDQChkinfo.u16EndPoint,stCMDQChkinfo.u16StartPoint,stCMDQChkinfo.u32CmdDiffCnt); ++ //checking ++ stCMDQChkinfo.Ret = _Drv_CMDQ_CheckingAlreadyExist(stCMDQChkinfo); ++ return stCMDQChkinfo.Ret; ++} ++void _Drv_CMDQ_SwapNonFrameCntBufCmd(MS_U64 *pu32Addr ,MS_U64 *pu32AddrEnd) ++{ ++ MS_U64 cmdend = 0; ++ cmdend = *pu32Addr; ++ *pu32AddrEnd = cmdend; ++ *pu32Addr = MS_CMDQ_NULL_CMD; ++} ++void _Drv_CMDQ_MoveBufCmd(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U64 *pu32Addr = NULL,*pu32AddrEnd = NULL; ++ MS_U32 i; ++ MS_U32 cmddiffcnt; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]%s\n" ++ ,__FUNCTION__); ++ cmddiffcnt = _Drv_CMDQ_GetCmdDiffCnt(); ++ if(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_ROTATION)) ++ { ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_ROTATION); ++ } ++ else if(gstCMDQInfo[enIPType].u16WPoint>gstCMDQInfo[enIPType].u16assFrame_Point) //move need rotation ++ { ++ for(i=0;iw ->ass not ring ,but total need ++ { ++ for(i=0;i=gstCMDQInfo[enIPType].u16MaxCmdCnt) ++ { ++ pu32AddrEnd = _Drv_CMDQ_GetPointerFromPoint ++ ((gstCMDQInfo[enIPType].u16assFrame_Point+i-gstCMDQInfo[enIPType].u16MaxCmdCnt),pu32AddrEnd); ++ } ++ else ++ { ++ pu32AddrEnd = _Drv_CMDQ_GetPointerFromPoint((gstCMDQInfo[enIPType].u16assFrame_Point+ i),pu32AddrEnd); ++ } ++ _Drv_CMDQ_SwapNonFrameCntBufCmd(pu32Addr,pu32AddrEnd); ++ } ++ } ++ ++} ++ ++MS_BOOL _Drv_CMDQ_BufferEmpty(EN_CMDQ_IP_TYPE eCMDQBuf) ++{ ++ if((gstCMDQInfo[eCMDQBuf].u16WPoint == gstCMDQInfo[eCMDQBuf].u16RPoint) && ++ (gstCMDQInfo[eCMDQBuf].u16WPoint == gstCMDQInfo[eCMDQBuf].u16FPoint)) ++ return TRUE; ++ else ++ return FALSE; ++} ++MS_U8 _Drv_CMDQ_GetISPHWCnt(void) ++{ ++ MS_U16 isp_cnt; ++ isp_cnt = Hal_CMDQ_Get_ISP_Cnt(); ++ isp_cnt = ((isp_cnt>>8)&0x7F); ++ return (MS_U8)isp_cnt; ++ ++} ++void _Drv_CMDQ_FillInitIPInfo ++ (EN_CMDQ_IP_TYPE enIPType,MS_PHYADDR IP0PhyAddr, MS_U32 u32IP0VirAddr, MS_U32 u32CMDQBufSize) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]PhyAddr:%lx u32VirAddr:%lx \n",IP0PhyAddr,u32IP0VirAddr); ++ gstCMDQInfo[enIPType].bEnable = FALSE; ++ gstCMDQInfo[enIPType].u16RPoint = 0; //last trig ++ gstCMDQInfo[enIPType].u16WPoint = 0; //current cmd end ++ gstCMDQInfo[enIPType].u16FPoint = 0; //fire point (128 bit/unit) ++ gstCMDQInfo[enIPType].u16assFrame_Point=0; // assign frame count ++ gstCMDQInfo[enIPType].u16MaxCmdCnt = (MS_U16)(u32CMDQBufSize / MS_CMDQ_CMD_LEN); ++ gstCMDQInfo[enIPType].u16BufCmdCnt = gstCMDQInfo[enIPType].u16MaxCmdCnt / ++ MS_CMDQ_NONFRAMECOUNT_PERCENT; // 10% ex. 100 -10=90->91...96.97.98.99.100 enable use ++ if(gstCMDQInfo[enIPType].u16BufCmdCnt%MS_CMDQ_CMD_ALIGN) ++ { ++ gstCMDQInfo[enIPType].u16BufCmdCnt++; ++ } ++ gstCMDQInfo[enIPType].u16MaxCmdCnt = gstCMDQInfo[enIPType].u16MaxCmdCnt - ++ gstCMDQInfo[enIPType].u16BufCmdCnt;//assframe count ++ gstCMDQInfo[enIPType].PhyAddr = IP0PhyAddr; ++ gstCMDQInfo[enIPType].u32VirAddr = u32IP0VirAddr; ++ gstCMDQInfo[enIPType].PhyAddrEnd = IP0PhyAddr+ ++ (gstCMDQInfo[enIPType].u16MaxCmdCnt/2)*MS_CMDQ_MEM_BASE_UNIT; ++ gCMDQStatusFlag[enIPType] = (CMDQ_FLAG_FIRE|CMDQ_FLAG_FIRST_NONFRAMECNT); ++} ++MS_U8 _Drv_CMDQ_GetUsePollFuctionFlag(MS_U8 u8AssignFramecnt ,MS_U8 bCntWarn) ++{ ++ MS_U8 bAddPollFunc = 0; ++ if(gu32LasttimeFramecnt == u8AssignFramecnt) ++ { ++ bAddPollFunc = 0; ++ } ++ else if(bCntWarn) ++ { ++ bAddPollFunc = 0; ++ } ++ else ++ { ++ bAddPollFunc = 1; ++ gu32LasttimeFramecnt = u8AssignFramecnt; ++ } ++ return bAddPollFunc; ++} ++MS_U8 _Drv_CMDQ_GetFrameCntWarningMsg(MS_U8 u8AssignFramecnt ,MS_U8 u8IspHWCnt) ++{ ++ MS_U8 bHWCntReset = 0; ++ MS_U8 u8AllowFrameErrRange = CMDQ_ADD_DELAYFRAME_SCLSELF+CMDQ_ALLOW_ERROR_COUNT; ++ // when=1 is delay 2 frame ,when =0 is delay 2frame but input isp count add already add 1 itself. ++ if (_IsIspCountReset(u8IspHWCnt,u8AssignFramecnt)) //0xff->0x00 ++ { ++ bHWCntReset = 1; ++ } ++ //ex. u8IspHWCnt=31 ,u8AssignFramecnt=28,Actually poll 29(add delay),not allow to write cmd (for save) ++ if (_IsFrameCountError(u8IspHWCnt,u8AssignFramecnt,u8AllowFrameErrRange) && bHWCntReset == 0 )// only allow one frame cnt error ++ { ++ CMDQERR(printf("[CMDQ]framecnt not true:%hhd isp_cnt:%hhd \n",u8AssignFramecnt,u8IspHWCnt)); ++ return RETURN_ERROR; ++ } ++ //ex. u8IspHWCnt=31 ,u8AssignFramecnt=29,Actually poll 30(add delay), 31-29=2<=2 reluctantly allow to write cmd ,do not poll ++ //ex. u8IspHWCnt=31 ,u8AssignFramecnt=30,Actually poll 31(add delay), 31-30=1<=2 allow to write cmd,do not poll ++ //ex. u8IspHWCnt=31 ,u8AssignFramecnt=31,Actually poll 32(add delay), 31-31=0<=2 to avoid hang up, do not poll ++ else if(_IsFrameCountWarn(u8IspHWCnt,u8AssignFramecnt,u8AllowFrameErrRange)&& bHWCntReset == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]framecnt not true:%hhd isp_cnt:%hhd but reluctantly allow to write\n" ++ ,u8AssignFramecnt,u8IspHWCnt); ++ return TRUE; ++ } ++ return FALSE; ++} ++MS_BOOL _Drv_CMDQ_WriteCmd(MS_U64 u64Cmd,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_BOOL bRet,flag_framecnt_cmd; ++ MS_U16 u16DummyCmdIdx,u16DummyCmdIdx_nonframe; ++ ++ EN_CMDQ_IP_TYPE enCMDQIP = gstCurrworkIP; ++ flag_framecnt_cmd=(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD)); ++ if(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD)) ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ] CMDQ framecnt type :%hhd\n",(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD))); ++ else ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ] CMDQ non_framecnt_cmd type :%hhd\n",(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD))); ++ CMDQDBG(printf("[CMDQ] u64Cmd:%llx\n",u64Cmd)); ++ if( _Drv_CMDQ_BufferEmpty(enCMDQIP) ) ++ { ++ CMDQERR(printf("[CMDQ] buffer empty init\n")); ++ gstCMDQInfo[enCMDQIP].u16RPoint = 0; ++ gstCMDQInfo[enCMDQIP].u16WPoint = 0; ++ gstCMDQInfo[enCMDQIP].u16FPoint = 0; ++ gstCMDQInfo[enCMDQIP].u16assFrame_Point= 0; ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ bRet = TRUE; ++ } ++ else ++ { ++ if(flag_framecnt_cmd)//write direct u16WPoint&u16assFrame_Point ++ ++ { ++ ++ u16DummyCmdIdx=(gstCMDQInfo[enCMDQIP].u16WPoint/2+1)*2; ++ if(u16DummyCmdIdx < gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//med ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,flag_framecnt_cmd,bSkipCheckSameAddr)) ++ { ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ] u16WPoint=%d u16assFrame_Point=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16WPoint,gstCMDQInfo[enCMDQIP].u16assFrame_Point); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ #endif ++ if(gstCMDQInfo[enCMDQIP].u16assFrame_Point == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt) ++ { ++ gstCMDQInfo[enCMDQIP].u16assFrame_Point=0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ] Reset assFrame_Point=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16assFrame_Point); ++ } ++ } ++ bRet = TRUE; ++ } ++ else if(u16DummyCmdIdx == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last ++ { ++ if(gstCMDQInfo[enCMDQIP].u16WPoint+1 < gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last+2 ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,flag_framecnt_cmd,bSkipCheckSameAddr)) ++ { ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ #endif ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]FC last+2 u16MaxCmdCnt=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16MaxCmdCnt,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ bRet = TRUE; ++ } ++ else if(gstCMDQInfo[enCMDQIP].u16WPoint+1 == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last+1 ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,flag_framecnt_cmd,bSkipCheckSameAddr)) ++ { ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ bRet = TRUE; ++ gstCMDQInfo[gstCurrworkIP].u16WPoint=0; ++ if(gstCMDQInfo[enCMDQIP].u16assFrame_Point == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt) ++ { ++ gstCMDQInfo[enCMDQIP].u16assFrame_Point=0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ] Reset assFrame_Point=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16assFrame_Point); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]FC last+1 u16MaxCmdCnt=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16MaxCmdCnt,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ } ++ ++ } ++ else if(u16DummyCmdIdx > gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,flag_framecnt_cmd,bSkipCheckSameAddr)) ++ { ++ gstCMDQInfo[gstCurrworkIP].u16WPoint=0; ++ if(gstCMDQInfo[enCMDQIP].u16assFrame_Point == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt) ++ { ++ gstCMDQInfo[enCMDQIP].u16assFrame_Point=0; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ] frame cnt buffer full -->reset\n"); ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ #endif ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]FC last u16MaxCmdCnt=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16MaxCmdCnt,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ bRet = TRUE; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ else if(flag_framecnt_cmd==0)//write to buf u16WPoint++ ++ { ++ u16DummyCmdIdx_nonframe = _Drv_CMDQ_GetCmdDiffCnt(); ++ u16DummyCmdIdx =(gstCMDQInfo[enCMDQIP].u16WPoint/2+1)*2;//+2 to avoid over ++ if(u16DummyCmdIdx_nonframe < gstCMDQInfo[enCMDQIP].u16BufCmdCnt) ++ { ++ if(u16DummyCmdIdx < gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//med ++ { ++ _Drv_CMDQ_AddCmdToNonFrameCntBuffer(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNullToNonFrameCntBuffer(gstCurrworkIP); ++ #endif ++ bRet = TRUE; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]nonFC u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ else if(u16DummyCmdIdx == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last ++ { ++ if(gstCMDQInfo[enCMDQIP].u16WPoint+1 < gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last+2 ++ { ++ _Drv_CMDQ_AddCmdToNonFrameCntBuffer(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNullToNonFrameCntBuffer(gstCurrworkIP); ++ #endif ++ bRet = TRUE; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]nonFC last +2 u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ else if(gstCMDQInfo[enCMDQIP].u16WPoint+1 == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last+1 ++ { ++ ++ _Drv_CMDQ_AddCmdToNonFrameCntBuffer(u64Cmd,bSkipCheckSameAddr); ++ bRet = TRUE; ++ gstCMDQInfo[gstCurrworkIP].u16WPoint=0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]nonFC last +1 u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ ++ } ++ else if(u16DummyCmdIdx > gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last ++ { ++ gstCMDQInfo[gstCurrworkIP].u16WPoint=0; ++ _Drv_CMDQ_AddCmdToNonFrameCntBuffer(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNullToNonFrameCntBuffer(gstCurrworkIP); ++ #endif ++ bRet = TRUE; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ] non-frame cnt to normal buffer full -->reset\n"); ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ _SetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_ROTATION); ++ bRet = TRUE; ++ CMDQERR(printf("[CMDQ] non-frame cnt buffer full\n")); ++ } ++ } ++ ++ } ++ return bRet; ++} ++MS_U64 _Drv_CMDQ_GetCmd(MS_U8 u8type,MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask) ++{ ++ MS_U16 u16Bank; ++ MS_U8 u8addr; ++ MS_CMDQ_CMD data; ++ u16Bank = (MS_U16)((u32Addr >> 8) & 0xFFFF); ++ u8addr = (MS_U8)((u32Addr & 0xFF) ); ++ if(u8addr%2) //Hbyte ++ { ++ data.u16Mask=~(u16Mask<<8); ++ data.u16Data = (R2BYTE(u32Addr-1) & ~(u16Mask<<8)) | ((u16Data & u16Mask)<<8); ++ } ++ else ++ { ++ data.u16Mask=~(u16Mask); ++ if( u16Mask == 0xFFFF ) ++ { ++ data.u16Data = u16Data; ++ } ++ else ++ { ++ data.u16Data = (R2BYTE(u32Addr) & ~u16Mask) | (u16Data & u16Mask); ++ } ++ } ++ ++ data.u8type = u8type; ++ data.u32Addr =((((MS_U32)u16Bank<<4)*8)|((MS_U32)u8addr/2)); ++ data.u64Cmd = _CMDQGetCMD(data.u8type,data.u32Addr,data.u16Data,data.u16Mask); ++ return data.u64Cmd; ++} ++void _Drv_CMDQ_PutCmd(MS_U8 u8type,MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_U64 u64CMD; ++ u64CMD = _Drv_CMDQ_GetCmd(u8type,u32Addr,u16Data,u16Mask); ++ _Drv_CMDQ_WriteCmd(u64CMD,bSkipCheckSameAddr);//cmd:real cmd ++} ++void _Drv_CMDQ_AddWaitLDCTrigCMD(void) ++{ ++ _Drv_CMDQ_AddNull(EN_CMDQ_TYPE_IP0); ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,0x12183C,0xFFFD,0xFFFF,1); ++ Drv_CMDQ_WaitCmd(sc2cmdq_lv_trig);//wait ++ _Drv_CMDQ_AddNull(EN_CMDQ_TYPE_IP0); ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,0x12183C,0xFFFF,0xFFFF,1); ++} ++void _Drv_CMDQ_AddFirstNonFrameCountCMD(void) ++{ ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRST_NONFRAMECNT); ++ _SetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD); ++ _Drv_CMDQ_AddWaitLDCTrigCMD(); ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD); ++} ++void _Drv_CMDQ_WriteFrameCntCMDHandler(MS_CMDQ_CMD stCMDQCMD) ++{ ++ static MS_U8 u8SclDelayMode = CMDQ_ADD_DELAYFRAME_SCLSELF; ++ _SetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD); ++ if(stCMDQCMD.bAddPollFunc)//put framecnt cmd last ++ { ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_SAMEFRAME); ++ Drv_CMDQ_PollingEqCmd(0x1302F4,(stCMDQCMD.u8AssignFramecnt+u8SclDelayMode),0x00FF);//poll_eq ++ _Drv_CMDQ_AddWaitLDCTrigCMD(); ++ } ++ else if(stCMDQCMD.bCntWarn) ++ { ++ if(_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_SAMEFRAME)) ++ { ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRE); ++ } ++ else if (_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRE)) ++ { ++ _Drv_CMDQ_AddWaitLDCTrigCMD(); ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRE); ++ _SetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_SAMEFRAME); ++ } ++ } ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,stCMDQCMD.u32Addr,stCMDQCMD.u16Data,stCMDQCMD.u16Mask,0); ++ _ReSetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FRAMECNT_CMD|CMDQ_FLAG_FIRE); ++} ++MS_CMDQ_CMD _Drv_CMDQ_FillCMDQCMD ++ (MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask,MS_U8 u8AssignFramecnt,MS_U8 bCntWarn,MS_U8 bAddPollFunc) ++{ ++ MS_CMDQ_CMD stCMDQCMD; ++ stCMDQCMD.u16Data = u16Data; ++ stCMDQCMD.u16Mask = u16Mask; ++ stCMDQCMD.u32Addr = u32Addr; ++ stCMDQCMD.u8AssignFramecnt = u8AssignFramecnt; ++ stCMDQCMD.bCntWarn = bCntWarn; ++ stCMDQCMD.bAddPollFunc = bAddPollFunc; ++ return stCMDQCMD; ++} ++void _Drv_CMDQ_MoveNonFrameCntBuf(void) ++{ ++ if(!_IsFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRST_NONFRAMECNT)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]API u16WPoint=%u u16RPoint=%u u16assFramePoint=%u\n", ++ gstCMDQInfo[gstCurrworkIP].u16WPoint, ++ gstCMDQInfo[gstCurrworkIP].u16RPoint, ++ gstCMDQInfo[gstCurrworkIP].u16assFrame_Point); ++ _Drv_CMDQ_MoveBufCmd(gstCurrworkIP); ++ _SetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRST_NONFRAMECNT); ++ } ++} ++//-------------------------------------------------------------------------------------------------- ++// In ring-buffer mode, this function will trig for update reg_sw_wr_mi_wadr ++// The CMDQ will keep on executing cmd until reg_rd_mi_radr reach reg_sw_wr_mi_wadr ++//-------------------------------------------------------------------------------------------------- ++ ++//API-------------------------------------------------------------------------------------------------- ++ ++void Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_IP_TYPE enIPType ,MS_U16 bEn) ++{ ++ Hal_CMDQ_SetSkipPollWhenWaitTimeout(enIPType,bEn); ++ Hal_CMDQ_SetTimeoutAmount(enIPType); ++} ++ ++void Drv_CMDQ_Enable(MS_BOOL bEnable,EN_CMDQ_IP_TYPE enIPType) ++{ ++ CMDQ_MUTEX_LOCK(); ++ gstCMDQInfo[enIPType].bEnable = bEnable; ++ CMDQ_MUTEX_UNLOCK(); ++} ++void Drv_CMDQ_InitRIUBase(MS_U32 u32RIUBase) ++{ ++ Hal_CMDQ_InitRIUBase(u32RIUBase); ++} ++ ++void Drv_CMDQ_Init(MS_PHYADDR PhyAddr1, MS_U32 u32VirAddr1, MS_U32 u32BufByteLen,MS_U32 u32RIUBase) ++{ ++ MS_PHYADDR IP0PhyAddr[CMDQ_NUMBER]; ++ MS_U32 u32CMDQBufSize; ++ MS_U32 u32IP0VirAddr[CMDQ_NUMBER]; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW, "[CMDQ]START init %s: 0x%lx,0x%lx, 0x%lx\n" ++ , __FUNCTION__, PhyAddr1,u32VirAddr1, u32BufByteLen); ++ Hal_CMDQ_InitRIUBase(u32RIUBase); ++ CMDQ_MUTEX_CREATE(); ++ u32CMDQBufSize = u32BufByteLen / CMDQ_NUMBER;// 0x4000/2 ++ IP0PhyAddr[EN_CMDQ_TYPE_IP0] = PhyAddr1; ++ u32IP0VirAddr[EN_CMDQ_TYPE_IP0] = u32VirAddr1; ++ MsOS_Memset((void *)u32VirAddr1, 0x00, u32BufByteLen); ++ ++ CMDQ_MUTEX_LOCK(); ++ _Drv_CMDQ_Init(PhyAddr1); ++ _Drv_CMDQ_FillInitIPInfo(EN_CMDQ_TYPE_IP0, IP0PhyAddr[EN_CMDQ_TYPE_IP0], ++ u32IP0VirAddr[EN_CMDQ_TYPE_IP0], u32CMDQBufSize); ++ _Drv_CMDQ_InitByIP(EN_CMDQ_TYPE_IP0); ++ CMDQ_MUTEX_UNLOCK(); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW, "[CMDQ]u16MaxCmdCnt:%hx,u16BufCmdCnt:%hx\r\n" ++ ,gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16MaxCmdCnt,gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16BufCmdCnt); ++ ++} ++void Drv_CMDQ_Delete(void) ++{ ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_CMDQ_48_L,0x0800,0x0800); //clear idle ++ while(1) ++ { ++ if(_IsCMDQIPIdle()) // wait idle ++ { ++ break; ++ } ++ } ++ Hal_CMDQ_SetISRMSK(EN_CMDQ_TYPE_IP0,0xFFFF); ++ Hal_CMDQ_ResetSoftInterrupt(EN_CMDQ_TYPE_IP0); ++ CMDQ_MUTEX_DELETE(); ++ ++} ++void Drv_CMDQ_release(void) ++{ ++ int u32Time; ++ MS_U32 u32CMDQBufSize = ++ (gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16MaxCmdCnt+gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16BufCmdCnt)*MS_CMDQ_CMD_LEN; ++ u32Time = MsOS_GetSystemTime(); ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_TYPE_IP0,1); ++ while(1) ++ { ++ if(Drv_CMDQ_CheckIPAlreadyDone(EN_CMDQ_TYPE_IP0)) ++ { ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_TYPE_IP0,0); ++ break; ++ } ++ else if(MsOS_Timer_DiffTimeFromNow(u32Time)>1000) ++ { ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_TYPE_IP0,0); ++ //printf("[CMDQ]!!!!Release Timeout\n"); ++ break; ++ } ++ } ++ _Drv_CMDQ_FillInitIPInfo(EN_CMDQ_TYPE_IP0, gstCMDQInfo[EN_CMDQ_TYPE_IP0].PhyAddr, ++ gstCMDQInfo[EN_CMDQ_TYPE_IP0].u32VirAddr,u32CMDQBufSize); ++ _Drv_CMDQ_Init(gstCMDQInfo[EN_CMDQ_TYPE_IP0].PhyAddr); ++ Hal_CMDQ_Reset(EN_CMDQ_TYPE_IP0, ENABLE); ++ Hal_CMDQ_Reset(EN_CMDQ_TYPE_IP0, DISABLE); ++ _Drv_CMDQ_AddNull(EN_CMDQ_TYPE_IP0);//add 2 null ++ gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16FPoint = gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16WPoint + 1; ++ gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16assFrame_Point= gstCMDQInfo[EN_CMDQ_TYPE_IP0].u16WPoint; ++} ++MS_BOOL Drv_CMDQ_AssignFrameWriteCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask,MS_U8 u8AssignFramecnt) ++{ ++ MS_U8 u8IspHWCnt; ++ MS_U8 bAddPollFunc = 0; ++ MS_U8 bCntWarn = 0; ++ MS_CMDQ_CMD stCMDQCMD; ++ ++ CMDQ_MUTEX_LOCK(); ++ u8IspHWCnt=_Drv_CMDQ_GetISPHWCnt(); ++ bCntWarn = _Drv_CMDQ_GetFrameCntWarningMsg(u8AssignFramecnt, u8IspHWCnt); ++ if(bCntWarn == RETURN_ERROR) ++ { ++ CMDQ_MUTEX_UNLOCK(); ++ return FALSE; ++ } ++ bAddPollFunc = _Drv_CMDQ_GetUsePollFuctionFlag(u8AssignFramecnt,bCntWarn); ++ stCMDQCMD = _Drv_CMDQ_FillCMDQCMD(u32Addr,u16Data,u16Mask,u8AssignFramecnt,bCntWarn,bAddPollFunc); ++ _Drv_CMDQ_WriteFrameCntCMDHandler(stCMDQCMD); ++ ++ CMDQ_MUTEX_UNLOCK(); ++ return 1; ++} ++ ++//u32Addr :8bit addr ++MS_BOOL Drv_CMDQ_WriteCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_BOOL bRet=1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]%s\n",__FUNCTION__); ++ CMDQ_MUTEX_LOCK(); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]Write: %04lx %04x %04x flag: %hhx\n" ++ ,u32Addr, u16Data, u16Mask,gCMDQStatusFlag[EN_CMDQ_TYPE_IP0]); ++ if(_IsFirstNonFrameCountCMD()) ++ { ++ _Drv_CMDQ_AddFirstNonFrameCountCMD(); ++ } ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,u32Addr,u16Data,u16Mask,bSkipCheckSameAddr); ++ CMDQ_MUTEX_UNLOCK(); ++ return bRet; ++} ++MS_CMDQ_Info Drv_CMDQ_GetCMDQInformation(EN_CMDQ_IP_TYPE enIPType) ++{ ++ return gstCMDQInfo[enIPType]; ++} ++void Drv_CMDQ_GetModuleMutex(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ if(bEn) ++ { ++ MsOS_ObtainMutex(_gCMDQHVSPMUTEX,MSOS_WAIT_FOREVER); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]IN Mutex\n"); ++ } ++ else ++ { ++ MsOS_ReleaseMutex(_gCMDQHVSPMUTEX); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]Out Mutex\n"); ++ } ++} ++MS_U16 Drv_CMDQ_GetFinalIrq(EN_CMDQ_IP_TYPE enIPType) ++{ ++ gu16ISRflag = R2BYTEMSK(REG_CMDQ_44_L, 0xFFFF); ++ return gu16ISRflag; ++} ++void Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Irq) ++{ ++ Hal_CMDQ_ClearIRQByFlag(enIPType,u16Irq); ++} ++void Drv_CMDQ_SetISRStatus(MS_BOOL bEn) ++{ ++ gbISRopen = bEn; ++} ++//------------------------------------------------------------------------------------------------- ++/// Fire the commands ++/// @return TRUE if succeed, FALSE if failed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_Fire(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart) ++{ ++ CMDQ_MUTEX_LOCK(); ++#if (CMDQCMD128==0) ++ if(gstCMDQInfo[gstCurrworkIP].u16WPoint%2) ++ { ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ } ++#endif ++ _Drv_CMDQ_MoveNonFrameCntBuf(); ++ _SetFlagType(EN_CMDQ_TYPE_IP0,CMDQ_FLAG_FIRE); ++ _Drv_CMDQ_Fire(enIPType,1); ++ CMDQ_MUTEX_UNLOCK(); ++ ++ return true; ++ ++} ++void Drv_CMDQ_WaitCmd(MS_U16 u16bus) ++{ ++ MS_U64 u64Cmd; ++ u64Cmd = MS_CMDQ_WAIT_CMD + u16bus; ++ _Drv_CMDQ_WriteCmd((MS_U64)u64Cmd, NotToCheckSameAddr); ++} ++ ++void Drv_CMDQ_PollingEqCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask) ++{ ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_POLLEQ,u32Addr,u16Data,u16Mask,NotToCheckSameAddr); ++} ++ ++void Drv_CMDQ_PollingNeqCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask) ++{ ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_POLLNEQ,u32Addr,u16Data,u16Mask,NotToCheckSameAddr); ++} ++MS_BOOL Drv_CMDQ_CheckIPAlreadyDone(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_BOOL bEn; ++ if(_IsCMDQDMADone()) //cmdq dma done ++ { ++ bEn = TRUE; ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_CMDQ_48_L,0x0003,0x0003); ++ } ++ else if(gbISRopen) ++ { ++ if(_IsCMDQExecuteDoneISR()) ++ { ++ bEn = TRUE; ++ } ++ else ++ { ++ bEn = FALSE; ++ } ++ } ++ else if(_IsCMDQExecuteDone()) ++ { ++ bEn = TRUE; ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_CMDQ_48_L,0x0003,0x0003); ++ } ++ else ++ { ++ bEn = FALSE; ++ } ++ return bEn; ++} +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/cmdq/drvCMDQ.h b/drivers/mstar/scl/infinity/src/mxlib/drv/cmdq/drvCMDQ.h +new file mode 100644 +index 00000000..3bb32330 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/cmdq/drvCMDQ.h +@@ -0,0 +1,365 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file drvCMDQ.h ++/// @brief CMDQ Driver Interface ++/// @author MStar Semiconductor,Inc. ++/// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRVCMDQ_H_ ++#define _DRVCMDQ_H_ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//#include "MsTypes.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++//#include ++ ++ ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Define ++//-------------------------------------------------------------------------------------------------- ++#define DIRECT_MODE 0x01 // direct mode :nonuse ++#define INCREMENT_MODE 0x00 // increment mode :nonuse ++#define RING_BUFFER_MODE 0x04 // ring mode ++#define CMDQ_DBUF 0 // whether double buffer ++#define CMDQ_irq 0 // isr open ++#define CMDQ_nonuse_Function 0 // mark no use function ++#define CMDQ_poll_timer 0x4D // poll timer ++#define CMDQ_timer_ratio 0x0 // time ratio ++#define CMDQ_base_amount 0x1FFFF // wait count amount ++#define CMDQ_timeout_amount 0x40 // wait timeout amount ++#define CMDQ_NUMBER 1 // number of CMDQ ip ++#define CMDQ_ADD_DELAYFRAME_SCLSELF 0 // when=1 is delay 2 frame ,when =0 is delay 2frame but input isp count add 1 itself. ++#define CMDQ_ALLOW_ERROR_COUNT 1 // allow overpass count ++#define CMDQ_IRQ_STATE_TRIG (1 << 0) ++#define CMDQ_IRQ_STATE_DONE (1 << 2) ++#define CMDQ_IRQ_WAIT_TIMEOUT (1 << 10) ++#define CMDQ_CMDTYPE_WRITE 0x10 ++#define CMDQ_CMDTYPE_WAIT 0x20 ++#define CMDQ_CMDTYPE_POLLEQ 0x30 ++#define CMDQ_CMDTYPE_POLLNEQ 0xb0 ++//-------------------------------------------------------------------------------------------------- ++// Driver Capability ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//----------------------------------------------------------------------------------------------- ++extern MS_U32 _CMDQ_RIU_BASE; ++ ++//-------------------------------------------------------------------------------------------------- ++// Type and Structure ++//-------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ EN_CMDQ_TYPE_IP0 , ++ EN_CMDQ_TYPE_IP1 , ++ EN_CMDQ_TYPE_IP2 , ++ EN_CMDQ_TYPE_MAX, ++}EN_CMDQ_IP_TYPE; ++ ++typedef enum ++{ ++ EN_CMDQ_MIU_0 , ++ EN_CMDQ_MIU_1 , ++}EN_CMDQ_MIU_TYPE; ++ ++typedef enum ++{ ++ CMDQ_FLAG_FIRE = 0x1, // whether already fire or need to fire ++ CMDQ_FLAG_FIRST_NONFRAMECNT = 0x2, // first non-frame cnt cmd need wait ++ CMDQ_FLAG_FRAMECNT_CMD = 0x4, // cmd whether framecnt ++ CMDQ_FLAG_ROTATION = 0x8, // using in nonframecnt , if full ++ CMDQ_FLAG_SAMEFRAME = 0x10, // using in framecnt , if trig but next cmd is same frame ,don't add poll ++ CMDQ_FLAG_NONFRAMEBUFFER = 0x20, ++}CMDQ_FLAG_TYPE; ++typedef struct ++{ ++ MS_U16 u16WPoint; // current cmd end ++ MS_U16 u16RPoint; // last trig ++ MS_U16 u16FPoint; // fire point (128 bit/unit) ++ MS_U16 u16assFrame_Point; // assign frame count ++ MS_PHYADDR PhyAddr; // by Chip_Phys_to_MIU ++ MS_U16 u16MaxCmdCnt; // assframe buf count ++ MS_U16 u16BufCmdCnt; // nonframecnt buf count ++ MS_BOOL bEnable; // CMDQ enable ((nonuse ++ MS_U32 u32VirAddr; // kernel virtul after allocate ++ MS_PHYADDR PhyAddrEnd; // by Chip_Phys_to_MIU+cnt ++ MS_U16 u16LPoint; // To get trig Count ++}MS_CMDQ_Info; ++ ++typedef struct ++{ ++ MS_U8 u8MIUSel_IP; ++}CMDQ_Buffer_MIU; ++typedef struct ++{ ++ MS_U16 u16StartPoint; ++ MS_U16 u16EndPoint; ++ MS_U32 u32CmdDiffCnt; ++ MS_U32 u32ActualCmdDiffCnt; ++ MS_BOOL bframecount; ++ MS_BOOL Ret; ++ MS_U32 u32addr; ++ MS_U16 u16mask; ++ MS_U16 u16data; ++ MS_U64 *pu32Addr; ++}CMDQ_CheckCmdinfo; ++ ++typedef struct ++{ ++ MS_U8 u8type; // CMD type(write,wait,poll) ++ MS_U16 u16Data; // 16bit data ++ MS_U32 u32Addr; // 16bit Bank addr + 8bit 16bit-regaddr ++ MS_U16 u16Mask; // inverse normal case ++ MS_U64 u64Cmd; // 64bit to consist CMDQ CMD ++ MS_U8 u8AssignFramecnt; ++ MS_U8 bCntWarn; ++ MS_U8 bAddPollFunc; ++}MS_CMDQ_CMD; ++ ++ ++typedef enum ++{ ++ E_CMDQ_EVENT_RUN = 0x00000001, ++ E_CMDQ_EVENT_IRQ = 0x00000002, ++} MDrvHDMITXEvent; ++ ++#define DRVCMDQ_OK 0x00000000 ++#define DRVCMDQ_FAIL 0x00000001 ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Function Prototype ++//-------------------------------------------------------------------------------------------------- ++//==============================Enable=============================================== ++ void Drv_CMDQ_Enable(MS_BOOL bEnable,EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_InitRIUBase(MS_U32 u32RIUBase); ++ ++//==============================Delete=============================================== ++void Drv_CMDQ_Delete(void); ++void Drv_CMDQ_SetRPoint(EN_CMDQ_IP_TYPE enIPType); ++MS_U64 Drv_CMDQ_GetCMDFromPoint(MS_U16 u16Point); ++MS_U32 Drv_CMDQ_GetCMDBankFromCMD(MS_U64 u64Cmd); ++//===============================init============================================== ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_Init ++/// is CMDQ IP init function, to set timer,address and size ++/// @param PhyAddr1 \b IN: from msys_request_dmem,and transform to MIU address ++/// @param u32VirAddr1 \b IN:like phyaddr,map to kernel virtual ++/// @param u32BufByteLen \b IN:already allocate memory size ++/// @param u32RIUBase \b IN:RIU's base shift ++//------------------------------------------------------------------------------------------------- ++ void Drv_CMDQ_Init(MS_PHYADDR PhyAddr1, MS_U32 u32VirAddr1, MS_U32 u32BufByteLen,MS_U32 u32RIUBase); ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_Set_timer_ratio ++/// set poll times in 1sec ++/// set time / ratio, total wait time is (wait_time * (ratio + 1)) =>ex. ( FF * (F + 1) / 216 MHz ) = sec ++/// 4D*1=4D~=77 *(216/M) 1 ~=60(frame/s) ++/// the polling_timer is for re-checking polling value, if the time_interval is too small, cmdq will polling RIU frequently, so that RIU will very busy ++/// @param time \b IN: poll wait time :#CMDQ_poll_timer ++/// @param ratio \b IN: time ratio :# CMDQ_timer_ratio ++/// retval : OK ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_SetSkipPollWhenWaitTimeOut ++/// set wait timeout count and whether jump timeout ++/// @param u16bjump \b IN:if true, timeout will jump wait, and carry out command ++//------------------------------------------------------------------------------------------------- ++void Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_IP_TYPE enIPType,MS_U16 bEn); ++//-------------------------------------------------------------------------------------------------- ++// Drv_CMDQ_Set_Buffer ++// set addr st and end pointer ,and set move range ++// In ring-buffer mode, this function will trig for update reg_sw_wr_mi_wadr ++// The CMDQ will keep on executing cmd until reg_rd_mi_radr reach reg_sw_wr_mi_wadr ++/// @param StartAddr \b IN:MIU addr(byte base) --> IP need 16byte addr,so function inside will /16 ++/// @param EndAddr \b IN:MIU addr ++//-------------------------------------------------------------------------------------------------- ++MS_U16 Drv_CMDQ_GetFinalIrq(EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Irq); ++void Drv_CMDQ_SetISRStatus(MS_BOOL bEn); ++void Drv_CMDQ_GetModuleMutex(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_CMDQ_Info Drv_CMDQ_GetCMDQInformation(EN_CMDQ_IP_TYPE enIPType); ++ ++//===============================write============================================== ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_WriteCmd ++/// write cmd API for any case ,to add cmd to MIU ++/// @param u32Addr \b IN: 8bit-addr ++/// @param u16Data \b IN: 16bit data ++/// @param u16Mask \b IN: 16bit ~mask, ++/// @param bSkipCheckSameAddr \b IN:if true,don't need to check .if false don't use mask(for RIU 32bit) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_WriteCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask,MS_BOOL bSkipCheckSameAddr); ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_AssignFrameWriteCmd ++/// write cmd API for frame count case ,to handle frame count case and add to MIU(use Drv_CMDQ_WriteCmd) ++/// @param u32Addr \b IN: 8bit-addr ++/// @param u16Data \b IN: 16bit data ++/// @param u16Mask \b IN: 16bit ~mask, ++/// @param u8framecnt \b IN: want to set cmd in this count ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_AssignFrameWriteCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask,MS_U8 u8framecnt); ++void Drv_CMDQ_release(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_AddCmd ++/// To add CMD to MIU, _Buf is use to nonframe count ++/// @param u64Cmd \b IN: the CMD want to write to MIU ++/// @param bSkipCheckSameAddr \b IN: if true,don't need to check .if false don't use mask(for RIU 32bit) ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_MoveBufCmd ++/// To move nonframe count CMD form nonframe count region to assframe count region ++/// @param enIPType \b IN: Buf number,nonuse ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_AddCmd_Check ++/// To check the CMD whether already exist. if yes ,to handle it. ++/// @param u64Cmd \b IN: the CMD want to write to MIU ++/// @param bframecount \b IN: if true, is frame count case. ++/// @param bSkipCheckSameAddr \b IN:if true,don't need to check .if false don't use mask(for RIU 32bit) ++//------------------------------------------------------------------------------------------------- ++ ++ //===============================wait============================================== ++ //------------------------------------------------------------------------------------------------- ++ /// Drv_CMDQ_WaitCmd ++ /// To add wait CMD ++ /// @param u16bus \b IN: wait trigger bus ++ //------------------------------------------------------------------------------------------------- ++ void Drv_CMDQ_WaitCmd(MS_U16 u16bus); ++ ++ //===============================poll============================================== ++ //------------------------------------------------------------------------------------------------- ++ /// Drv_CMDQ_PollingEqCmd ++ /// add Polling CMD ,or neq CMD ++ /// @param u32Addr \b IN: 8bit-addr ++ /// @param u16Data \b IN: 16bit data ++ /// @param u16Mask \b IN: 16bit ~mask, ++ //------------------------------------------------------------------------------------------------- ++ void Drv_CMDQ_PollingEqCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask); ++ void Drv_CMDQ_PollingNeqCmd(MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask); ++ ++ //===============================fire============================================== ++ //------------------------------------------------------------------------------------------------- ++ /// Drv_CMDQ_Fire ++ /// To trig CMDQ ++ /// @param bStart \b IN: trig ++ //------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_Fire(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart); ++ ++//===============================check============================================== ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_CheckIPAlreadyDone ++/// To check CMDQ status ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_CheckIPAlreadyDone(EN_CMDQ_IP_TYPE enIPType); ++ ++//===============================write Register============================================== ++#endif // _DRVCMDQ_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp.c b/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp.c +new file mode 100644 +index 00000000..e4c39e15 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp.c +@@ -0,0 +1,1066 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_HVSP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "MsDbg.h" ++#include ++#include ++#include ++#include ++ ++#include "drvhvsp_st.h" ++#include "halhvsp.h" ++#include "drvhvsp.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "irqs.h" ++#include "mdrv_scl_dbg.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_HVSP_DBG(x) ++#define DRV_HVSP_ERR(x) x ++#define DRV_HVSP_MUTEX_LOCK() MsOS_ObtainMutex(_HVSP_Mutex,MSOS_WAIT_FOREVER) ++#define DRV_HVSP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_HVSP_Mutex) ++#define FHD_Width 1920 ++#define FHD_Height 1080 ++#define HD_Width 1280 ++#define HD_Height 720 ++#define PNL_Width 800 ++#define PNL_Height 480 ++#define Is_DNRBufferReady() (gbMemReadyForDrv) ++#define Is_FrameBufferTooSmall(u32ReqMemSize,u32IPMMemSize) (u32ReqMemSize > u32IPMMemSize) ++#define Is_PreCropWidthNeedToOpen() (gstSrcSize.u16Width > gstIPMCfg.u16Fetch) ++#define Is_PreCropHeightNeedToOpen() (gstSrcSize.u16Height> gstIPMCfg.u16Vsize) ++#define Is_InputSrcRotate() (gstSrcSize.u16Height > gstSrcSize.u16Width) ++#define Is_IPM_NotSetReady() (gstIPMCfg.u16Fetch == 0 || gstIPMCfg.u16Vsize == 0) ++#define Is_INPUTMUX_SetReady() (gstSrcSize.bSet == 1) ++#define Is_PreCropNotNeedToOpen() ((gstIPMCfg.u16Fetch == gstSrcSize.u16Width) && \ ++ (gstIPMCfg.u16Vsize == gstSrcSize.u16Height)) ++#define VIP_HVSP_ID_SRAM_OFFSET 2 ++#define HVSP_RATIO(input, output) ((input * 1048576) / output) ++#define HVSP_CROP_RATIO(u16src, u16crop1, u16crop2) ((MS_U16)(((MS_U32)u16crop2 * (MS_U32)u16crop1) / (MS_U32)u16src )) ++#define HVSP_CROP_CHECK(u16croph,u16cropch,u16cropv,u16cropcv) (((u16croph) != (u16cropch))|| ((u16cropv) != (u16cropcv))) ++#define HVSP_DMA_CHECK(u16cropv,u16cropcv) (((u16cropv) != (u16cropcv))) ++#define _Change_SRAM_Qmap(enHVSP_ID,up) (((gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height\ ++ > gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height)&&up) || (((gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height\ ++ < gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height) && !up))) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ST_HVSP_SCALING_INFO gstScalinInfo[E_HVSP_ID_MAX]; ++ST_HVSP_IPM_CONFIG gstIPMCfg = {0}; ++ST_HVSP_SIZE_CONFIG gstSrcSize; ++///////////////// ++/// gbMemReadyForDrv ++/// if True ,DNR buffer was allocated. ++//////////////// ++MS_BOOL gbMemReadyForDrv; ++///////////////// ++/// bLDCEn ++/// if True ,LDC is open.(To sync VIP and HVSP driver) ++//////////////// ++MS_BOOL gbLDCEn=0; ++MS_U8 gu8FBBufferNum ; ++///////////////// ++/// gbHvspSuspend ++/// To Save suspend status. ++//////////////// ++MS_BOOL gbHvspSuspend = 0; ++///////////////// ++/// bclkforcemode ++/// use in Drvscldma and Drvhvsp ++/// if True ,can't dynamic set Clk ++//////////////// ++unsigned char gbclkforcemode = 0;//extern ++MS_S32 _HVSP_Mutex = -1; ++ ++//------------------------------------------------------------------------------------------------- ++// Private Functions ++//------------------------------------------------------------------------------------------------- ++void _Drv_HVSP_InitSWVarialbe(EN_HVSP_ID_TYPE HVSP_IP) ++{ ++ MsOS_Memset(&gstScalinInfo[HVSP_IP], 0, sizeof(ST_HVSP_SCALING_INFO)); ++ if(HVSP_IP == E_HVSP_ID_1) ++ { ++ MsOS_Memset(&gstIPMCfg, 0, sizeof(ST_HVSP_IPM_CONFIG)); ++ gbLDCEn = 0; ++ gstSrcSize.u16Height = FHD_Height; ++ gstSrcSize.u16Width = FHD_Width; ++ gstSrcSize.bSet = 0; ++ } ++} ++ ++ST_HVSP_CROP_INFO _Drv_HVSP_FillPreCropInfo(void) ++{ ++ ST_HVSP_CROP_INFO stCropInfo; ++ if(Is_IPM_NotSetReady() || Is_PreCropNotNeedToOpen()) ++ { ++ if(Is_IPM_NotSetReady()) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: IPM without setting\n", __FUNCTION__, __LINE__)); ++ } ++ stCropInfo.bEn = 0; ++ stCropInfo.u16Vst = 0; ++ stCropInfo.u16Hst = 0; ++ stCropInfo.u16Hsize = 0; ++ stCropInfo.u16Vsize = 0; ++ } ++ else ++ { ++ stCropInfo.bEn = 1; ++ if(Is_InputSrcRotate())//rotate ++ { ++ stCropInfo.u16Hst = 0; ++ stCropInfo.u16Vst = 0; ++ } ++ else if(Is_PreCropWidthNeedToOpen() || Is_PreCropHeightNeedToOpen()) ++ { ++ if(Is_PreCropWidthNeedToOpen()) ++ { ++ stCropInfo.u16Hst = (gstSrcSize.u16Width - gstIPMCfg.u16Fetch)/2; ++ } ++ if(Is_PreCropHeightNeedToOpen()) ++ { ++ stCropInfo.u16Vst = (gstSrcSize.u16Height - gstIPMCfg.u16Vsize)/2; ++ } ++ } ++ else ++ { ++ stCropInfo.u16Hst = 0; ++ stCropInfo.u16Vst = 0; ++ } ++ stCropInfo.u16Hsize = gstIPMCfg.u16Fetch; ++ stCropInfo.u16Vsize = gstIPMCfg.u16Vsize; ++ } ++ // crop1 ++ stCropInfo.u16In_hsize = gstSrcSize.u16Width; ++ stCropInfo.u16In_vsize = gstSrcSize.u16Height; ++ if(stCropInfo.u16In_hsize == 0) ++ { ++ stCropInfo.u16In_hsize = FHD_Width; ++ } ++ if(stCropInfo.u16In_vsize == 0) ++ { ++ stCropInfo.u16In_vsize = FHD_Height; ++ } ++ return stCropInfo; ++} ++void _Drv_HVSP_SetCoringThrdOn(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ Hal_HVSP_SetHspCoringThrdC(enHVSP_ID,0x1); ++ Hal_HVSP_SetHspCoringThrdY(enHVSP_ID,0x1); ++ Hal_HVSP_SetVspCoringThrdC(enHVSP_ID,0x1); ++ Hal_HVSP_SetVspCoringThrdY(enHVSP_ID,0x1); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Public Functions ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_HVSP_SetCMDQTrigType(ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg) ++{ ++ Hal_HVSP_SetCMDQTrigCfg(stCmdTrigCfg); ++ Hal_HVSP_SetCMDQTrigFrameCnt(0); ++ return TRUE; ++} ++ ++MS_BOOL Drv_HVSP_GetCMDQTrigType(ST_HVSP_CMD_TRIG_CONFIG *pCfg) ++{ ++ Hal_HVSP_GetCMDQTrigCfg(pCfg); ++ return TRUE; ++} ++ ++MS_BOOL Drv_HVSP_GetCMDQDoneStatus(void) ++{ ++ MS_U32 u32Events; ++ MS_U32 u32Time; ++ static MS_BOOL sbDone = 0; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ MsOS_ObtainMutex(_HVSP_Mutex, MSOS_WAIT_FOREVER); ++ u32Events = MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID()); // get status: FRM END ++ if(u32Events& E_SCLIRQ_EVENT_CMDQGOING) ++ { ++ sbDone = 0; ++ } ++ if(u32Events &E_SCLIRQ_EVENT_CMDQDONE) ++ { ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),u32Events); ++ sbDone = 1; ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, "[drvhvsp]CMDQ done @%lu\n", u32Time); ++ return 1; ++ } ++ else if (sbDone) ++ { ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, "[drvhvsp]CMDQ done(sb) @%lu\n", u32Time); ++ return 1; ++ } ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ return 0; ++} ++ ++wait_queue_head_t * Drv_HVSP_GetWaitQueueHead(void) ++{ ++ return Drv_SCLIRQ_GetSyncQueue(); ++} ++void Drv_HVSP_Release(EN_HVSP_ID_TYPE HVSP_IP) ++{ ++ Hal_HVSP_Set_Reset(); ++ _Drv_HVSP_InitSWVarialbe(HVSP_IP); ++} ++MS_BOOL Drv_HVSP_Suspend(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_SCLIRQ_SUSPEND_RESUME_CONFIG stSclirq; ++ MS_BOOL bRet = TRUE; ++ ++ MsOS_ObtainMutex(_HVSP_Mutex, MSOS_WAIT_FOREVER); ++ Hal_HVSP_Set_Reset(); ++ if(gbHvspSuspend == 0) ++ { ++ stSclirq.u32IRQNUM = pCfg->u32IRQNUM; ++ stSclirq.u32CMDQIRQNUM = pCfg->u32CMDQIRQNUM; ++ if(Drv_SCLIRQ_Suspend(&stSclirq)) ++ { ++ bRet = TRUE; ++ gbHvspSuspend = 1; ++ } ++ else ++ { ++ bRet = FALSE; ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) Suspend IRQ Fail\n", __FUNCTION__, __LINE__)); ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(3)), "[DRVHVSP]%s(%d) alrady suspned\n", __FUNCTION__, __LINE__); ++ bRet = TRUE; ++ } ++ ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ ++ return bRet; ++} ++ ++MS_BOOL Drv_HVSP_Resume(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_SCLIRQ_SUSPEND_RESUME_CONFIG stSclirq; ++ MS_BOOL bRet = TRUE; ++ ++ MsOS_ObtainMutex(_HVSP_Mutex, MSOS_WAIT_FOREVER); ++ ++ //printf("%s,(%d) %d\n", __FUNCTION__, __LINE__, gbHvspSuspend); ++ if(gbHvspSuspend == 1) ++ { ++ stSclirq.u32IRQNUM = pCfg->u32IRQNUM; ++ stSclirq.u32CMDQIRQNUM = pCfg->u32CMDQIRQNUM; ++ if(Drv_SCLIRQ_Resume(&stSclirq)) ++ { ++ Drv_SCLIRQ_InterruptEnable(SCLIRQ_VSYNC_FCLK_LDC); ++ Hal_HVSP_SetTestPatCfg(); ++ gbHvspSuspend = 0; ++ bRet = TRUE; ++ } ++ else ++ { ++ ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) Resume IRQ Fail\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(3)), "[DRVHVSP]%s(%d) alrady resume\n", __FUNCTION__, __LINE__); ++ bRet = TRUE; ++ } ++ ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ ++ return bRet; ++} ++void Drv_HVSP_SetBufferNum(MS_U8 u8Num) ++{ ++ gu8FBBufferNum = u8Num; ++} ++MS_BOOL Drv_HVSP_GetBufferNum(void) ++{ ++ return gu8FBBufferNum; ++} ++MS_BOOL Drv_HVSP_Init(ST_HVSP_INIT_CONFIG *pInitCfg) ++{ ++ char word[] = {"_HVSP_Mutex"}; ++ ST_SCLIRQ_INIT_CONFIG stIRQInitCfg; ++ MS_U8 u8IDidx; ++ ++ if(_HVSP_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(3)), "[DRVHVSP]%s(%d) alrady done\n", __FUNCTION__, __LINE__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) MsOS_Init Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ _HVSP_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ ++ if (_HVSP_Mutex == -1) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d): create mutex fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ stIRQInitCfg.u32RiuBase = pInitCfg->u32RIUBase; ++ stIRQInitCfg.u32IRQNUM = pInitCfg->u32IRQNUM; ++ stIRQInitCfg.u32CMDQIRQNUM = pInitCfg->u32CMDQIRQNUM; ++ if(Drv_SCLIRQ_Init(&stIRQInitCfg) == FALSE) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) Init IRQ Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ Hal_HVSP_SetRiuBase(pInitCfg->u32RIUBase); ++ DRV_HVSP_MUTEX_LOCK(); ++ Hal_HVSP_Set_Reset(); ++ for(u8IDidx = E_HVSP_ID_1; u8IDidx 50) ++ { ++ break; ++ } ++ } ++ } ++ Hal_HVSP_SetCMDQTrigFire(); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(HVSP_IP)), ++ "[DRVHVSP]%s id:%d @:%lu\n", __FUNCTION__,HVSP_IP,(MS_U32)MsOS_GetSystemTime()); ++ } ++} ++void Drv_HVSP_SetMemoryAllocateReady(MS_BOOL bEn) ++{ ++ gbMemReadyForDrv = bEn; ++} ++void _Drv_HVSP_SetHorizotnalScalingConfig(EN_HVSP_ID_TYPE enHVSP_ID,MS_BOOL bEn) ++{ ++ ++ Hal_HVSP_SetScalingHoEn(enHVSP_ID, bEn); ++ Hal_HVSP_SetScalingHoFacotr(enHVSP_ID, bEn ? gstScalinInfo[enHVSP_ID].u32ScalingRatio_H: 0); ++ Hal_HVSP_SetModeYHo(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_SRAM_0: E_HVSP_FILTER_MODE_BYPASS); ++ Hal_HVSP_SetModeCHo(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_BILINEAR: E_HVSP_FILTER_MODE_BYPASS,E_HVSP_SRAM_SEL_0); ++ Hal_HVSP_SetHspDithEn(enHVSP_ID,bEn); ++ Hal_HVSP_SetHspCoringEnC(enHVSP_ID,bEn); ++ Hal_HVSP_SetHspCoringEnY(enHVSP_ID,bEn); ++} ++void _Drv_HVSP_SetVerticalScalingConfig(EN_HVSP_ID_TYPE enHVSP_ID,MS_BOOL bEn) ++{ ++ Hal_HVSP_SetScalingVeEn(enHVSP_ID, bEn); ++ Hal_HVSP_SetScalingVeFactor(enHVSP_ID, bEn ? gstScalinInfo[enHVSP_ID].u32ScalingRatio_V: 0); ++ Hal_HVSP_SetModeYVe(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_SRAM_0: E_HVSP_FILTER_MODE_BYPASS); ++ Hal_HVSP_SetModeCVe(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_BILINEAR: E_HVSP_FILTER_MODE_BYPASS,E_HVSP_SRAM_SEL_0); ++ Hal_HVSP_SetVspDithEn(enHVSP_ID,bEn); ++ Hal_HVSP_SetVspCoringEnC(enHVSP_ID,bEn); ++ Hal_HVSP_SetVspCoringEnY(enHVSP_ID,bEn); ++} ++MS_BOOL Drv_HVSP_SetScaling(EN_HVSP_ID_TYPE enHVSP_ID, ST_HVSP_SCALING_CONFIG stCfg, ST_HVSP_CLK_CONFIG* stclk) ++{ ++ static MS_BOOL bScalingup[E_HVSP_ID_MAX] ={1,0,0}; ++ if(enHVSP_ID == E_HVSP_ID_1) ++ { ++ ST_HVSP_CROP_INFO stCropInfo_2; ++ MS_U32 u32FrameBufferMemSize = gstIPMCfg.u32MemSize; ++ MS_U32 u32ReqMemSize = stCfg.bCropEn[DRV_HVSP_CROP_1] ? ++ stCfg.u16Crop_Width[DRV_HVSP_CROP_1] * stCfg.u16Crop_Height[DRV_HVSP_CROP_1] * 4 : ++ stCfg.u16Src_Width * stCfg.u16Src_Height * 2 * Drv_HVSP_GetBufferNum(); ++ ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[DRVHVSP]%s id:%d @:%lu\n", ++ __FUNCTION__,enHVSP_ID,(MS_U32)MsOS_GetSystemTime()); ++ ++ if(Is_DNRBufferReady()) ++ { ++ if(Is_FrameBufferTooSmall(u32ReqMemSize, u32FrameBufferMemSize)) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: Out of memory\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ } ++ else ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: Can't Use DNR (FB Not Ready)\n", __FUNCTION__, __LINE__)); ++ if(Is_FrameBufferTooSmall(u32ReqMemSize, u32FrameBufferMemSize)) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: Out of memory\n", __FUNCTION__, __LINE__)); ++ } ++ } ++ if(stCfg.u16Src_Width != gstIPMCfg.u16Fetch) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: H Src Size Mismatch(%hd,%hd)\n", ++ __FUNCTION__, __LINE__,stCfg.u16Src_Width,gstIPMCfg.u16Fetch)); ++ } ++ if(stCfg.u16Src_Height != gstIPMCfg.u16Vsize) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: V Src Size Mismatch(%hd,%hd)\n", ++ __FUNCTION__, __LINE__,stCfg.u16Src_Height,gstIPMCfg.u16Vsize)); ++ } ++ ++ // setup cmd trig config ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_HVSP_SetCMDQTrigType(stCfg.stCmdTrigCfg); ++ ++ if(stCfg.bCropEn[DRV_HVSP_CROP_2]) ++ { ++ // crop2 ++ stCropInfo_2.bEn = stCfg.bCropEn[DRV_HVSP_CROP_2]; ++ if(gstIPMCfg.u16Fetch &&gstIPMCfg.u16Vsize) ++ { ++ stCropInfo_2.u16In_hsize = gstIPMCfg.u16Fetch; ++ stCropInfo_2.u16In_vsize = gstIPMCfg.u16Vsize; ++ } ++ else ++ { ++ stCropInfo_2.u16In_hsize = stCfg.u16Src_Width; ++ stCropInfo_2.u16In_vsize = stCfg.u16Src_Height; ++ } ++ stCropInfo_2.u16Hsize = stCfg.u16Crop_Width[DRV_HVSP_CROP_2]; ++ stCropInfo_2.u16Vsize = stCfg.u16Crop_Height[DRV_HVSP_CROP_2]; ++ stCropInfo_2.u16Hst = stCfg.u16Crop_X[DRV_HVSP_CROP_2]; ++ stCropInfo_2.u16Vst = stCfg.u16Crop_Y[DRV_HVSP_CROP_2]; ++ } ++ else ++ { ++ stCropInfo_2.bEn = 0; ++ if(gstIPMCfg.u16Fetch &&gstIPMCfg.u16Vsize) ++ { ++ stCropInfo_2.u16In_hsize = gstIPMCfg.u16Fetch; ++ stCropInfo_2.u16In_vsize = gstIPMCfg.u16Vsize; ++ stCropInfo_2.u16Hsize = gstIPMCfg.u16Fetch;//stCfg.u16Src_Width; ++ stCropInfo_2.u16Vsize = gstIPMCfg.u16Vsize;//stCfg.u16Src_Height; ++ } ++ else ++ { ++ stCropInfo_2.u16In_hsize = stCfg.u16Src_Width; ++ stCropInfo_2.u16In_vsize = stCfg.u16Src_Height; ++ stCropInfo_2.u16Hsize = stCfg.u16Src_Width;//stCfg.u16Src_Width; ++ stCropInfo_2.u16Vsize = stCfg.u16Src_Height;//stCfg.u16Src_Height; ++ } ++ stCropInfo_2.u16Hst = 0; ++ stCropInfo_2.u16Vst = 0; ++ } ++ ++ if(stCfg.bCropEn[DRV_HVSP_CROP_2]) ++ { ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width = stCfg.u16Crop_Width[DRV_HVSP_CROP_2]; ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height = stCfg.u16Crop_Height[DRV_HVSP_CROP_2]; ++ } ++ else ++ { ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width = stCropInfo_2.u16In_hsize;//stCfg.u16Src_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height = stCropInfo_2.u16In_vsize;//stCfg.u16Src_Height; ++ } ++ ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width = stCfg.u16Dsp_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height = stCfg.u16Dsp_Height; ++ ++ // Crop2 ++ Hal_HVSP_SetCropConfig(E_HVSP_CROP_ID_2, stCropInfo_2); ++ ++ // NLM size ++ Hal_HVSP_SetNLMSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_SetNLMLineBufferSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_SetNLMEn(1); ++ ++ } ++ else ++ { ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_HVSP_SetCMDQTrigType(stCfg.stCmdTrigCfg); ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width = stCfg.u16Src_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height = stCfg.u16Src_Height; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width = stCfg.u16Dsp_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height = stCfg.u16Dsp_Height; ++ } ++ ++ gstScalinInfo[enHVSP_ID].u32ScalingRatio_H = (MS_U32)HVSP_RATIO(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width); ++ ++ gstScalinInfo[enHVSP_ID].u32ScalingRatio_V = (MS_U32)HVSP_RATIO(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++ ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]%s(%d):: HVSP_%d, AfterCrop(%d, %d)\n", __FUNCTION__, __LINE__, ++ enHVSP_ID, gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]%s(%d):: HVSP_%d, AfterScaling(%d, %d)\n", __FUNCTION__, __LINE__, ++ enHVSP_ID, gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width, gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]%s(%d):: HVSP_%d, Ratio(%lx, %lx)\n", __FUNCTION__, __LINE__, ++ enHVSP_ID, gstScalinInfo[enHVSP_ID].u32ScalingRatio_H, gstScalinInfo[enHVSP_ID].u32ScalingRatio_V); ++ ++ // horizotnal HVSP Scaling ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width == gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width) ++ { ++ _Drv_HVSP_SetHorizotnalScalingConfig(enHVSP_ID, FALSE); ++ } ++ else ++ { ++ _Drv_HVSP_SetHorizotnalScalingConfig(enHVSP_ID, TRUE); ++ } ++ ++ // vertical HVSP Scaling ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height == gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height) ++ { ++ _Drv_HVSP_SetVerticalScalingConfig(enHVSP_ID, FALSE); ++ } ++ else ++ { ++ _Drv_HVSP_SetVerticalScalingConfig(enHVSP_ID, TRUE); ++ } ++ if(_Change_SRAM_Qmap(enHVSP_ID,bScalingup[enHVSP_ID])) ++ { ++ bScalingup[enHVSP_ID] = (bScalingup[enHVSP_ID]^1);//XOR 1 :reverse ++ Hal_VIP_SRAM_Dump(enHVSP_ID+VIP_HVSP_ID_SRAM_OFFSET,bScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[DRVHVSP]Change Qmap SRAM id:%d scaling UP:%hhu\n", ++ enHVSP_ID,bScalingup[enHVSP_ID]); ++ } ++ ++ // HVSP In size ++ Hal_HVSP_SetHVSPInputSize(enHVSP_ID, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ ++ // HVSP Out size ++ Hal_HVSP_SetHVSPOutputSize(enHVSP_ID, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++ if(enHVSP_ID == E_HVSP_ID_3) ++ { ++ if(!gbclkforcemode) ++ { ++ Hal_HVSP_FCLK2(stclk); ++ } ++ } ++ else ++ { ++ if(!gbclkforcemode) ++ { ++ Hal_HVSP_FCLK1(stclk); ++ } ++ } ++ _Drv_HVSP_SetCMDQTrigFire(stCfg.stCmdTrigCfg,enHVSP_ID); ++ DRV_HVSP_MUTEX_UNLOCK(); ++ return TRUE; ++} ++void Drv_HVSP_SetInputSrcSize(MS_U16 u16Height,MS_U16 u16Width) ++{ ++ if(u16Height > 0) ++ { ++ gstSrcSize.u16Height = u16Height; ++ } ++ if(u16Width > 0) ++ { ++ gstSrcSize.u16Width = u16Width; ++ } ++ gstSrcSize.bSet = 1; ++} ++void Drv_HVSP_SetCropWindowSize(void) ++{ ++ ST_HVSP_CROP_INFO stCropInfo_1; ++ ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg; ++ stCropInfo_1 = _Drv_HVSP_FillPreCropInfo(); ++ DRV_HVSP_MUTEX_LOCK(); ++ stCmdTrigCfg = Drv_HVSP_SetCMDQTrigTypeByRIU(); ++ Hal_HVSP_SetCropConfig(E_HVSP_CROP_ID_1, stCropInfo_1); ++ Drv_HVSP_SetCMDQTrigType(stCmdTrigCfg); ++ DRV_HVSP_MUTEX_UNLOCK(); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s Input:(%hd,%hd) Crop:(%hd,%hd)\n", __FUNCTION__, ++ stCropInfo_1.u16In_hsize,stCropInfo_1.u16In_vsize,stCropInfo_1.u16Hsize,stCropInfo_1.u16Vsize); ++} ++ ++MS_BOOL Drv_HVSP_SetInputMux(EN_HVSP_IP_MUX_TYPE enIP,ST_HVSP_CLK_CONFIG* stclk) ++{ ++ DRV_HVSP_DBG(printf("[DRVHVSP]%s(%d): IP=%x\n", __FUNCTION__, __LINE__,enIP)); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s(%d): IP=%x\n", __FUNCTION__, __LINE__,enIP); ++ Hal_HVSP_SetInputMuxType(enIP); ++ if(!gbclkforcemode && stclk != NULL) ++ { ++ Hal_HVSP_SetIdclkOnOff(1,stclk); ++ } ++ if(enIP >= E_HVSP_IP_MUX_MAX) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d):: Wrong IP Type\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ Hal_HVSP_SetHWInputMux(enIP); ++ return TRUE; ++} ++ ++MS_BOOL Drv_HVSP_SetRegisterForce(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Msk) ++{ ++ Hal_HVSP_Set_Reg(u32Reg, u8Val, u8Msk); ++ return TRUE; ++} ++void Drv_HVSP_SetOSDConfig(EN_HVSP_ID_TYPE enID, ST_DRV_HVSP_OSD_CONFIG stOSdCfg) ++{ ++ Hal_HVSP_SetOSDLocate(enID,stOSdCfg.enOSD_loc); ++ Hal_HVSP_SetOSDOnOff(enID,stOSdCfg.stOsdOnOff.bOSDEn); ++ Hal_HVSP_SetOSDbypass(enID,stOSdCfg.stOsdOnOff.bOSDBypass); ++ Hal_HVSP_SetOSDbypassWTM(enID,stOSdCfg.stOsdOnOff.bWTMBypass); ++} ++MS_BOOL Drv_HVSP_GetSCLInform(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_SCINFORM_CONFIG *stInformCfg) ++{ ++ stInformCfg->u16X = Hal_HVSP_GetCrop2Xinfo(); ++ stInformCfg->u16Y = Hal_HVSP_GetCrop2Yinfo(); ++ stInformCfg->u16Width = Hal_HVSP_GetHVSPOutputWidth(enID); ++ stInformCfg->u16Height = Hal_HVSP_GetHVSPOutputHeight(enID); ++ stInformCfg->u16crop2inWidth = Hal_HVSP_GetCrop2InputWidth(); ++ stInformCfg->u16crop2inHeight = Hal_HVSP_GetCrop2InputHeight(); ++ stInformCfg->u16crop2OutWidth = Hal_HVSP_GetCrop2OutputWidth(); ++ stInformCfg->u16crop2OutHeight = Hal_HVSP_GetCrop2OutputHeight(); ++ stInformCfg->bEn = Hal_HVSP_GetCrop2En(); ++ return TRUE; ++} ++MS_BOOL Drv_HVSP_GetHVSPAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_HVSPINFORM_CONFIG *stInformCfg) ++{ ++ stInformCfg->u16Width = Hal_HVSP_GetHVSPOutputWidth(enID); ++ stInformCfg->u16Height = Hal_HVSP_GetHVSPOutputHeight(enID); ++ stInformCfg->u16inWidth = Hal_HVSP_GetHVSPInputWidth(enID); ++ stInformCfg->u16inHeight = Hal_HVSP_GetHVSPInputHeight(enID); ++ stInformCfg->bEn = Hal_HVSP_GetScalingFunctionStatus(enID); ++ return TRUE; ++} ++void Drv_HVSP_GetOSDAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_OSD_CONFIG *stOsdCfg) ++{ ++ stOsdCfg->enOSD_loc = Hal_HVSP_GetOSDLocate(enID); ++ stOsdCfg->stOsdOnOff.bOSDEn = Hal_HVSP_GetOSDOnOff(enID); ++ stOsdCfg->stOsdOnOff.bOSDBypass = Hal_HVSP_GetOSDbypass(enID); ++ stOsdCfg->stOsdOnOff.bWTMBypass = Hal_HVSP_GetOSDbypassWTM(enID); ++} ++MS_BOOL Drv_HVSP_GetFrameBufferAttribute(EN_HVSP_ID_TYPE enID,ST_HVSP_IPM_CONFIG *stInformCfg) ++{ ++ stInformCfg->bWrite = gstIPMCfg.bWrite; ++ stInformCfg->u16Fetch = gstIPMCfg.u16Fetch; ++ stInformCfg->u16Vsize = gstIPMCfg.u16Vsize; ++ stInformCfg->u32BaseAddr = gstIPMCfg.u32BaseAddr+0x20000000; ++ stInformCfg->u32MemSize = gstIPMCfg.u32MemSize; ++ stInformCfg->bRead = gstIPMCfg.bRead; ++ return Hal_HVSP_GetLDCPathSel(); ++} ++MS_BOOL Drv_HVSP_SetLDCFrameBuffer_Config(ST_HVSP_LDC_FRAMEBUFFER_CONFIG stLDCCfg) ++{ ++ ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg; ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s(%d): Width=%hx,Height:%x\n", __FUNCTION__, ++ __LINE__, stLDCCfg.u16Width,stLDCCfg.u16Height); ++ DRV_HVSP_MUTEX_LOCK(); ++ stCmdTrigCfg = Drv_HVSP_SetCMDQTrigTypeByRIU(); ++ Hal_HVSP_SetLDCWidth(stLDCCfg.u16Width); ++ Hal_HVSP_SetLDCHeight(stLDCCfg.u16Height); ++ Hal_HVSP_SetLDCBase(stLDCCfg.u32FBaddr); ++ Hal_HVSP_SetLDCHWrwDiff((((MS_U16)stLDCCfg.u8FBrwdiff<<4)|((MS_U16)stLDCCfg.u8FBidx<<2)|((MS_U16)stLDCCfg.bEnSWMode<<8))); ++ Hal_HVSP_SetLDCPathSel(stLDCCfg.bEnDNR); ++ if(!gbLDCEn) ++ { ++ Hal_HVSP_SetLDCBypass(1); ++ } ++ Drv_HVSP_SetCMDQTrigType(stCmdTrigCfg); ++ DRV_HVSP_MUTEX_UNLOCK(); ++ return TRUE; ++} ++void Drv_HVSP_SetLDCONOFF(MS_BOOL bEn) ++{ ++ gbLDCEn = bEn; ++} ++MS_BOOL Drv_HVSP_SetPatTgen(MS_BOOL bEn, ST_DRV_HVSP_PAT_TGEN_CONFIG *pCfg) ++{ ++ MS_U16 u16VSync_St, u16HSync_St; ++ MS_BOOL bRet = TRUE; ++ Drv_SCLIRQ_SetPTGenStatus(bEn); ++ if(bEn) ++ { ++ u16VSync_St = 1; ++ u16HSync_St = 0; ++ if(pCfg) ++ { ++ if((u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch + pCfg->u16VActive - 1 )<1125) ++ { ++ Hal_HVSP_SetPatTgVtt(1125); //scaling up need bigger Vtt, , using vtt of 1920x1080 for all timing ++ } ++ else ++ { ++ Hal_HVSP_SetPatTgVtt(2200); //rotate ++ } ++ Hal_HVSP_SetPatTgVsyncSt(u16VSync_St); ++ Hal_HVSP_SetPatTgVsyncEnd(u16VSync_St + pCfg->u16VSyncWidth - 1); ++ Hal_HVSP_SetPatTgVdeSt(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch); ++ Hal_HVSP_SetPatTgVdeEnd(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch + pCfg->u16VActive - 1); ++ Hal_HVSP_SetPatTgVfdeSt(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch); ++ Hal_HVSP_SetPatTgVfdeEnd(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch + pCfg->u16VActive - 1); ++ ++ Hal_HVSP_SetPatTgHtt(2200); // scaling up need bigger Vtt, , using vtt of 1920x1080 for all timing ++ Hal_HVSP_SetPatTgHsyncSt(u16HSync_St); ++ Hal_HVSP_SetPatTgHsyncEnd(u16HSync_St + pCfg->u16HSyncWidth - 1); ++ Hal_HVSP_SetPatTgHdeSt(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch); ++ Hal_HVSP_SetPatTgHdeEnd(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch + pCfg->u16HActive - 1); ++ Hal_HVSP_SetPatTgHfdeSt(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch); ++ Hal_HVSP_SetPatTgHfdeEnd(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch + pCfg->u16HActive - 1); ++ ++ Hal_HVSP_SetPatTgEn(TRUE); ++ bRet = TRUE; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ Hal_HVSP_SetPatTgEn(FALSE); ++ bRet = TRUE; ++ } ++ return bRet; ++} ++void Drv_HVSP_IDCLKRelease(ST_HVSP_CLK_CONFIG* stclk) ++{ ++ if(!gbclkforcemode) ++ Hal_HVSP_SetIdclkOnOff(0,stclk); ++} ++unsigned long Drv_HVSP_CMDQStatusReport(void) ++{ ++ unsigned long u32Reg; ++ static MS_U32 u32savereg; ++ u32Reg = Hal_HVSP_GetCMDQStatus(); ++ if(u32savereg == u32Reg) ++ { ++ return 0; ++ } ++ else ++ { ++ u32savereg = u32Reg; ++ return u32Reg ; ++ } ++} ++unsigned long Drv_HVSP_CropCheck(void) ++{ ++ MS_U16 u16croph,u16cropv,u16cropch,u16cropcv; ++ static MS_BOOL sbPrint = 0; ++ if(!sbPrint) ++ { ++ Drv_SCLIRQ_Set_Checkcropflag(EN_HVSP_MONITOR_CROPCHECK); ++ printf("[DRVHVSP]check crop\n"); ++ } ++ u16croph = Hal_HVSP_GetCrop1Width(); ++ u16cropv = Hal_HVSP_GetCrop1Height(); ++ u16cropch = Hal_HVSP_GetCrop1WidthCount(); ++ u16cropcv = Hal_HVSP_GetCrop1HeightCount(); ++ if(HVSP_CROP_CHECK(u16croph,u16cropch,u16cropv,u16cropcv)) ++ { ++ (printf("[DRVHVSP]crop set :(H,V)=(%hd,%hd)\n crop receive:(H,V)=(%hd,%hd)\n", ++ u16croph,u16cropv,u16cropch+1,u16cropcv )); ++ return 1; ++ } ++ sbPrint = 1 ; ++ return 0; ++} ++unsigned long Drv_HVSP_DMACheck(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 u16dmav,u16dmacv,bEn,u16hvsp,u16hvsp2,u16hvsp3; ++ MS_U32 u32Time; ++ static MS_BOOL sbPrint = 0; ++ if(!sbPrint) ++ { ++ Drv_SCLIRQ_Set_Checkcropflag(enMonitorType); ++ printf("[DRVHVSP]check DMA:%d\n",enMonitorType); ++ } ++ u16dmav = Hal_HVSP_GetDMAHeight(enMonitorType); ++ u16dmacv = Hal_HVSP_GetDMAHeightCount(enMonitorType); ++ bEn = Hal_HVSP_GetDMAEn(enMonitorType); ++ if(HVSP_DMA_CHECK(u16dmav,u16dmacv)&& bEn) ++ { ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ u16hvsp = Hal_HVSP_GetHVSPOutputHeightCount(E_HVSP_ID_1); ++ u16hvsp2= Hal_HVSP_GetHVSPOutputHeightCount(E_HVSP_ID_2); ++ u16hvsp3= Hal_HVSP_GetHVSPOutputHeightCount(E_HVSP_ID_3); ++ (printf("[DRVHVSP]dma set :(V)=(%hd) @%lu\n dma receive:(V)=(%hd) hvsp(3,2,1):(%hd,%hd,%hd)\n", ++ u16dmav,u32Time,u16dmacv,u16hvsp3,u16hvsp2,u16hvsp )); ++ return 1; ++ } ++ sbPrint = 1 ; ++ return 0; ++} ++void Drv_HVSP_GetCrop12Inform(ST_DRV_HVSP_INPUTINFORM_CONFIG *stInformCfg) ++{ ++ stInformCfg->u16inWidth = Hal_HVSP_GetCrop1Width(); ++ stInformCfg->u16inHeight = Hal_HVSP_GetCrop1Height(); ++ stInformCfg->u16inWidthcount = Hal_HVSP_GetCrop1WidthCount(); ++ if(stInformCfg->u16inWidthcount) ++ { ++ stInformCfg->u16inWidthcount++; ++ } ++ stInformCfg->u16inHeightcount = Hal_HVSP_GetCrop1HeightCount(); ++ stInformCfg->enMux = Hal_HVSP_GetInputSrcMux(); ++ ++} ++void Drv_HVSP_SetCLKForcemode(unsigned char bEn) ++{ ++ gbclkforcemode = bEn; ++} ++MS_BOOL Drv_HVSP_GetCLKForcemode(void) ++{ ++ return gbclkforcemode; ++} ++void Drv_HVSP_SetCLKRate(unsigned char u8Idx) ++{ ++ if(gbclkforcemode) ++ { ++ u8Idx |= EN_HVSP_CLKATTR_FORCEMODE; ++ } ++ Hal_HVSP_SetCLKRate(u8Idx); ++} ++MS_U8 Drv_HVSP_CheckInputVSync(void) ++{ ++ MS_U32 u32Events = 0; ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_SYNC, &u32Events, E_OR, MSOS_WAIT_FOREVER); // get status: FRM END ++ if(u32Events) ++ { ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_SYNC)); ++ return 1; ++ } ++ return 0; ++} ++#undef DRV_HVSP_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp.h b/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp.h +new file mode 100644 +index 00000000..7ab3f593 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp.h +@@ -0,0 +1,152 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. 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If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_HVSP_H ++#define _DRV_HVSP_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_HVSP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++#define HVSP_irq 0 ++INTERFACE void Drv_HVSP_SetMemoryAllocateReady(MS_BOOL bEn); ++INTERFACE MS_BOOL Drv_HVSP_Init(ST_HVSP_INIT_CONFIG *pInitCfg); ++INTERFACE void Drv_HVSP_SetBufferNum(MS_U8 u8Num); ++INTERFACE MS_BOOL Drv_HVSP_GetBufferNum(void); ++INTERFACE MS_BOOL Drv_HVSP_Set_IPM_Config(ST_HVSP_IPM_CONFIG stCfg); ++INTERFACE void Drv_HVSP_SetFbManageConfig(ST_DRV_HVSP_SET_FB_MANAGE_CONFIG stCfg); ++INTERFACE MS_BOOL Drv_HVSP_SetScaling(EN_HVSP_ID_TYPE enHVSP_ID, ST_HVSP_SCALING_CONFIG stCfg, ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE MS_BOOL Drv_HVSP_SetInputMux(EN_HVSP_IP_MUX_TYPE enIP,ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE MS_BOOL Drv_HVSP_SetRegisterForce(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Msk); ++INTERFACE MS_BOOL Drv_HVSP_SetLDCFrameBuffer_Config(ST_HVSP_LDC_FRAMEBUFFER_CONFIG stLDCCfg); ++INTERFACE MS_BOOL Drv_HVSP_SetPatTgen(MS_BOOL bEn, ST_DRV_HVSP_PAT_TGEN_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_HVSP_GetSCLInform(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_SCINFORM_CONFIG *stInformCfg); ++INTERFACE void Drv_HVSP_SetOSDConfig(EN_HVSP_ID_TYPE enID, ST_DRV_HVSP_OSD_CONFIG stOSdCfg); ++INTERFACE void Drv_HVSP_IDCLKRelease(ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE unsigned long Drv_HVSP_CropCheck(void); ++INTERFACE unsigned long Drv_HVSP_DMACheck(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_U8 Drv_HVSP_CheckInputVSync(void); ++INTERFACE void Drv_HVSP_GetCrop12Inform(ST_DRV_HVSP_INPUTINFORM_CONFIG *stInformCfg); ++INTERFACE MS_BOOL Drv_HVSP_GetFrameBufferAttribute(EN_HVSP_ID_TYPE enID,ST_HVSP_IPM_CONFIG *stInformCfg); ++INTERFACE MS_BOOL Drv_HVSP_GetHVSPAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_HVSPINFORM_CONFIG *stInformCfg); ++INTERFACE void Drv_HVSP_GetOSDAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_OSD_CONFIG *stOsdCfg); ++INTERFACE MS_BOOL Drv_HVSP_Suspend(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_HVSP_Resume(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE void Drv_HVSP_Release(EN_HVSP_ID_TYPE HVSP_IP); ++INTERFACE MS_BOOL Drv_HVSP_SetCMDQTrigType(ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg); ++INTERFACE ST_HVSP_CMD_TRIG_CONFIG Drv_HVSP_SetCMDQTrigTypeByRIU(void); ++INTERFACE void Drv_HVSP_SetCLKForcemode(unsigned char bEn); ++INTERFACE MS_BOOL Drv_HVSP_GetCLKForcemode(void); ++INTERFACE void Drv_HVSP_SetCLKRate(unsigned char u8Idx); ++INTERFACE unsigned long Drv_HVSP_CMDQStatusReport(void); ++INTERFACE void Drv_HVSP_SetLDCONOFF(MS_BOOL bEn); ++INTERFACE wait_queue_head_t * Drv_HVSP_GetWaitQueueHead(void); ++INTERFACE MS_BOOL Drv_HVSP_GetCMDQDoneStatus(void); ++INTERFACE void Drv_HVSP_SetCropWindowSize(void); ++INTERFACE void Drv_HVSP_SetInputSrcSize(MS_U16 u16Height,MS_U16 u16Width); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp_st.h b/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp_st.h +new file mode 100644 +index 00000000..9372c220 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/hvsp/drvhvsp_st.h +@@ -0,0 +1,318 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_HVSP_ST_H ++#define _DRV_HVSP_ST_H ++ ++#define DRV_HVSP_CROP_1 0 ++#define DRV_HVSP_CROP_2 1 ++#define DRV_HVSP_CROP_NUM 2 ++//------------------------------------------------------------------------------------------------- ++// Defines & enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HVSP_CROP_ID_1, ++ E_HVSP_CROP_ID_2, ++ E_HVSP_CROP_ID_MAX, // I1 has 2 crop IP ++}EN_HVSP_CROP_ID_TYPE; ++ ++typedef enum ++{ ++ E_HVSP_IP_MUX_BT656 , //I1 HW only has BT656 and ISP input source ++ E_HVSP_IP_MUX_ISP , ++ E_HVSP_IP_MUX_HVSP , //SW used in HVSP 2 ++ E_HVSP_IP_MUX_PAT_TGEN, // SW used in debug pat ++ E_HVSP_IP_MUX_MAX, // 4 main type, 2 hw type, 2 sw type ++}EN_HVSP_IP_MUX_TYPE; ++ ++typedef enum ++{ ++ EN_HVSP_MONITOR_CROPCHECK = 1, ///< crop ++ EN_HVSP_MONITOR_DMA1FRMCHECK = 2, ///< dma1frm ++ EN_HVSP_MONITOR_DMA1SNPCHECK = 3, ///< dma1frm ++ EN_HVSP_MONITOR_DMA2FRMCHECK = 4, ///< dma1frm ++ EN_HVSP_MONITOR_DMA3FRMCHECK = 5, ///< dma1frm ++}EN_HVSP_MONITOR_TYPE; ++typedef enum ++{ ++ EN_DRV_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ EN_DRV_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_DRV_HVSP_OSD_LOC_TYPE; ++ ++ ++typedef enum ++{ ++ E_HVSP_ID_1, ++ E_HVSP_ID_2, ++ E_HVSP_ID_3, ++ E_HVSP_ID_MAX, //I1 has 3 HVSP ++}EN_HVSP_ID_TYPE; ++ ++typedef enum ++{ ++ E_HVSP_CMD_TRIG_NONE, //RIU ++ E_HVSP_CMD_TRIG_POLL_LDC_SYNC, //polling blanking region RIU ++ E_HVSP_CMD_TRIG_CMDQ_FRMCNT, //wait framecnt CMDQ ++ E_HVSP_CMD_TRIG_CMDQ_LDC_SYNC, //used CMDQ in blanking region ++ E_HVSP_CMD_TRIG_MAX, //HVSP has 4 type to set register,2 RIU,2 CMDQ ++}EN_HVSP_CMD_TRIG_TYPE; ++typedef enum ++{ ++ E_HVSP_EVENT_RUN = 0x00000001, ++ E_HVSP_EVENT_IRQ = 0x00000002, ++} MDrvHVSPTXEvent; ++typedef enum ++{ ++ EN_DRV_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_DRV_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_DRV_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_DRV_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_DRV_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_DRV_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_DRV_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_DRV_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_DRV_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_DRV_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++}EN_DRV_HVSP_FBMG_SET_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ MS_U32 u32RIUBase; // I1 :0x1F000000 ++ MS_U32 u32IRQNUM; // scl irq num by device tree ++ MS_U32 u32CMDQIRQNUM; // cmdq irq ++}ST_HVSP_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32IRQNUM; ++ MS_U32 u32CMDQIRQNUM; // cmdq irq ++}ST_HVSP_SUSPEND_RESUME_CONFIG; ++ ++typedef struct ++{ ++ MSOS_ST_CLK* idclk; // I1 scl clk 1.idclk(for before crop) ++ MSOS_ST_CLK* fclk1; // 2. fclk1(scl main clk) ++ MSOS_ST_CLK* fclk2; // 3.fclk2(scl hvsp3 only) ++ MSOS_ST_CLK* odclk; // 4.odclk(ttl only ) ++}ST_HVSP_CLK_CONFIG; ++typedef struct ++{ ++ MS_BOOL bRead; // DNR IP can Read from Buffer (if can read then DNR availability) ++ MS_BOOL bWrite; // DNR IP can Write to Buffer ++ MS_U32 u32BaseAddr;// DNR Buffer phycal address(unit:Byte) ++ MS_U16 u16Vsize; // DNR Frame Height size ++ MS_U16 u16Fetch; // DNR Frame Width size ++ MS_U32 u32MemSize; // DNR buffer size ++}ST_HVSP_IPM_CONFIG; ++ ++ ++typedef struct ++{ ++ EN_HVSP_CMD_TRIG_TYPE enType; ++ MS_U8 u8Fmcnt; ++}ST_HVSP_CMD_TRIG_CONFIG; ++ ++typedef struct ++{ ++ ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg; ++ MS_U16 u16Src_Width; // Input source width(post crop1) ++ MS_U16 u16Src_Height; // Input source height(post crop1) ++ MS_BOOL bCropEn[DRV_HVSP_CROP_NUM]; // crop enable ++ MS_U16 u16Crop_X[DRV_HVSP_CROP_NUM]; // crop x ++ MS_U16 u16Crop_Y[DRV_HVSP_CROP_NUM]; // crop y ++ MS_U16 u16Crop_Width[DRV_HVSP_CROP_NUM]; // post crop2 width ++ MS_U16 u16Crop_Height[DRV_HVSP_CROP_NUM]; // post crop2 height ++ MS_U16 u16Dsp_Width; // After scl display width ++ MS_U16 u16Dsp_Height; // After scl display height ++}ST_HVSP_SCALING_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bSet; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++}ST_HVSP_SIZE_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bCropEn; ++ ++ ST_HVSP_SIZE_CONFIG stSizeAfterCrop; ++ ST_HVSP_SIZE_CONFIG stSizeAfterScaling; ++ MS_U32 u32ScalingRatio_H; ++ MS_U32 u32ScalingRatio_V; ++}ST_HVSP_SCALING_INFO; ++ ++typedef struct ++{ ++ unsigned short u16Width; // LDC FB width ++ unsigned short u16Height; // LDC FB Heigh ++ unsigned long u32FBaddr; // DNR Buffer ++ unsigned char u8FBidx; // idx assign by sw ++ unsigned char u8FBrwdiff; // delay frame from DNR buffer ++ unsigned char bEnSWMode; // enable idx assign sw mode ++ unsigned char bEnDNR; // DNR enable? ++}ST_HVSP_LDC_FRAMEBUFFER_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Vtt; ++ MS_U16 u16VBackPorch; ++ MS_U16 u16VSyncWidth; ++ MS_U16 u16VFrontPorch; ++ MS_U16 u16VActive; ++ MS_U16 u16Htt; ++ MS_U16 u16HBackPorch; ++ MS_U16 u16HSyncWidth; ++ MS_U16 u16HFrontPorch; ++ MS_U16 u16HActive; ++}ST_DRV_HVSP_PAT_TGEN_CONFIG; ++ ++typedef struct ++{ ++ unsigned short u16X; //isp crop x ++ unsigned short u16Y; // isp crop y ++ unsigned short u16Width; // display width ++ unsigned short u16Height; // display height ++ unsigned short u16crop2inWidth; // after isp crop width ++ unsigned short u16crop2inHeight;// after isp crop height ++ unsigned short u16crop2OutWidth; // after isp crop width ++ unsigned short u16crop2OutHeight;// after isp crop height ++ unsigned char bEn; //crop En ++}ST_DRV_HVSP_SCINFORM_CONFIG; ++typedef struct ++{ ++ unsigned short u16Width; // display width ++ unsigned short u16Height; // display height ++ unsigned short u16inWidth; // after hvsp width ++ unsigned short u16inHeight;// after hvsp height ++ unsigned char bEn; //function En ++}ST_DRV_HVSP_HVSPINFORM_CONFIG; ++typedef struct ++{ ++ EN_HVSP_IP_MUX_TYPE enMux; // display width ++ unsigned short u16inWidth; // isp width ++ unsigned short u16inHeight;// isp height ++ unsigned short u16inWidthcount; // isp width ++ unsigned short u16inHeightcount;// isp height ++}ST_DRV_HVSP_INPUTINFORM_CONFIG; ++typedef struct ++{ ++ EN_DRV_HVSP_FBMG_SET_TYPE enSet; ++}ST_DRV_HVSP_SET_FB_MANAGE_CONFIG; ++typedef struct ++{ ++ unsigned char bOSDEn; ///< OSD en ++ unsigned char bOSDBypass; ///< OSD en ++ unsigned char bWTMBypass; ///< OSD en ++}ST_DRV_HVSP_OSD_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ EN_DRV_HVSP_OSD_LOC_TYPE enOSD_loc; ///< OSD locate ++ ST_DRV_HVSP_OSD_ONOFF_CONFIG stOsdOnOff; ++}ST_DRV_HVSP_OSD_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/pnl/drvpnl.c b/drivers/mstar/scl/infinity/src/mxlib/drv/pnl/drvpnl.c +new file mode 100644 +index 00000000..70f2572e +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/pnl/drvpnl.c +@@ -0,0 +1,260 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_PNL_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++ ++#include "halpnl.h" ++#include "drvpnl.h" ++#include "mdrv_scl_dbg.h" ++#include "drvsclirq_st.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_PNL_DBG(x) ++#define DRV_PNL_ERR(x) x ++#define ENLPLLCLK 1 //open lpll clk ++#define DISLPLLCLK 0 //close lpll clk ++#define FACTOR 10*1000000 ++#define LVDS_MPLL_CLOCK_MHZ 432 //ToDo ++#define PNL_CAL_LPLL_DCLK(Vtt,Htt,Freq) ((Vtt) * (Htt) * (Freq)) ++#define PNL_CAL_DCLK_FACKTOR(Lpll_Gain) ((MS_U64)LVDS_MPLL_CLOCK_MHZ * (MS_U64)524288 * (MS_U64)(Lpll_Gain)) ++#define PNL_CAL_LPLL_SET(DclkFacktor,Dclk_x10,Lpll_Div) (((DclkFacktor) * (FACTOR)) + (((MS_U64)(Dclk_x10) * (MS_U64)(Lpll_Div)) >> 1)) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_S32 _PNL_Mutex = -1; ++MS_BOOL gPnlOpen; ++MS_U32 gu32Dclk; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_PNL_Init(ST_PNL_INIT_CONFIG *pCfg) ++{ ++ char word[] = {"_PNL_Mutex"}; ++ ++ if(_PNL_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s already done\n", __FUNCTION__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s MsOs_Init Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _PNL_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ ++ if (_PNL_Mutex == -1) ++ { ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s create mutex fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ Hal_PNL_Set_Riu_Base(pCfg->u32RiuBase); ++ Hal_PNL_Set_Init_Y2R(); ++ gPnlOpen = 0; ++ ++ return TRUE; ++} ++MS_BOOL Drv_PNL_GetPnlOpen(void) ++{ ++ return gPnlOpen ; ++} ++void Drv_PNL_Release(void) ++{ ++ if(!gbclkforcemode && gPnlOpen) ++ { ++ Hal_PNL_Set_OpenLpll_CLK(DISLPLLCLK); ++ gPnlOpen = 0; ++ } ++} ++void Drv_PNL_Resume(void) ++{ ++ Hal_PNL_Set_Init_Y2R(); ++} ++MS_U32 Drv_PNL_GetLPLLDclk(void) ++{ ++ return gu32Dclk; ++} ++MS_BOOL Drv_PNL_Set_Timing_Config(ST_PNL_TIMING_CONFIG *pCfg) ++{ ++ MS_U16 u16LpllIdx = 0xFF; ++ MS_U32 u32Lpll_Gain, u32Lpll_Div, u32Dclk; ++ MS_U64 u64Dclk_x10, u64DclkFacktor, u64LpllSet; ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s, V:[%d %d %d %d], H:[%d %d %d %d]\n " ++ , __FUNCTION__, pCfg->u16Vsync_St, pCfg->u16Vsync_End, pCfg->u16Vde_St, pCfg->u16Vde_End, ++ pCfg->u16Hsync_St, pCfg->u16Hsync_End, pCfg->u16Hde_St, pCfg->u16Hde_End); ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s, Htt:%d, Vtt:%d, VFreqx10:%d\n " ++ ,__FUNCTION__, pCfg->u16Htt, pCfg->u16Vtt, pCfg->u16VFreqx10); ++ ++ ++ // LPLL setting ++ u64Dclk_x10 = PNL_CAL_LPLL_DCLK(pCfg->u16Vtt,pCfg->u16Htt,(pCfg->u16VFreqx10)); ++ u32Dclk = PNL_CAL_LPLL_DCLK(pCfg->u16Vtt,pCfg->u16Htt,(pCfg->u16VFreqx10/10)); ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%sDCLK:%ld\n ", __FUNCTION__, u32Dclk); ++ gu32Dclk = u32Dclk; ++ u16LpllIdx = Hal_PNL_Get_Lpll_Idx(u32Dclk); ++ if(u16LpllIdx == 0xFF) ++ { ++ DRV_PNL_ERR(printf("[DRVPNL]%s:: LPLL Clk is out of range\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ u32Lpll_Gain = Hal_PNL_Get_Lpll_Gain(u16LpllIdx); ++ u32Lpll_Div = Hal_PNL_Get_Lpll_Div(u16LpllIdx); ++ ++ u64DclkFacktor = PNL_CAL_DCLK_FACKTOR(u32Lpll_Gain); ++ u64LpllSet = PNL_CAL_LPLL_SET(u64DclkFacktor,u64Dclk_x10,u32Lpll_Div); ++ ++ do_div(u64LpllSet, u64Dclk_x10); ++ do_div(u64LpllSet, u32Lpll_Div); ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s::LpllIdx=%d, Gain:%d, Div:%d, LpllSet=%x\n " ++ ,__FUNCTION__, (int)u16LpllIdx, (int)u32Lpll_Gain, (int)u32Lpll_Div, (int)u64LpllSet); ++ ++ Hal_PNL_Dump_Lpll_Setting(u16LpllIdx); ++ Hal_PNL_Set_Lpll_Set((MS_U32)u64LpllSet); ++ if(!gbclkforcemode) ++ { ++ Hal_PNL_Set_OpenLpll_CLK(ENLPLLCLK); ++ gPnlOpen = 1; ++ } ++ //Tgen setting ++ Hal_PNL_Set_VSync_St(pCfg->u16Vsync_St); ++ Hal_PNL_Set_VSync_End(pCfg->u16Vsync_End); ++ Hal_PNL_Set_Vfde_St(pCfg->u16Vfde_St); ++ Hal_PNL_Set_Vfde_End(pCfg->u16Vfde_End); ++ Hal_PNL_Set_Vde_St(pCfg->u16Vde_St); ++ Hal_PNL_Set_Vde_End(pCfg->u16Vde_End); ++ Hal_PNL_Set_Vtt(pCfg->u16Vtt); ++ ++ Hal_PNL_Set_HSync_St(pCfg->u16Hsync_St); ++ Hal_PNL_Set_HSync_End(pCfg->u16Hsync_End); ++ Hal_PNL_Set_Hfde_St(pCfg->u16Hfde_St); ++ Hal_PNL_Set_Hfde_End(pCfg->u16Hfde_End); ++ Hal_PNL_Set_Hde_St(pCfg->u16Hde_St); ++ Hal_PNL_Set_Hde_End(pCfg->u16Hde_End); ++ Hal_PNL_Set_Htt(pCfg->u16Htt); ++ Hal_PNL_Set_FrameColr_En(0); ++ Hal_PNL_Set_Chiptop(); ++ ++ return TRUE; ++} ++ ++ ++MS_BOOL Drv_PNL_Set_CSC_Y2R_Config(ST_PNL_CSC_Y2R_CONFIG *pCfg) ++{ ++ Hal_PNL_Set_CSC_Y2R_En(pCfg->bEn); ++ Hal_PNL_Set_CSC_Y2R_Offset(pCfg->u8YOffset, pCfg->u8CbOffset, pCfg->u8CrOffset); ++ Hal_PNL_Set_CSC_Y2R_Coef(&pCfg->u16Coef[0]); ++ ++ return TRUE; ++} ++ ++#undef DRV_PNL_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/pnl/drvpnl.h b/drivers/mstar/scl/infinity/src/mxlib/drv/pnl/drvpnl.h +new file mode 100644 +index 00000000..9dafaa8a +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/pnl/drvpnl.h +@@ -0,0 +1,154 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_PNL_H ++#define _DRV_PNL_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++}ST_PNL_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Vsync_St; ++ MS_U16 u16Vsync_End; ++ MS_U16 u16Vde_St; ++ MS_U16 u16Vde_End; ++ MS_U16 u16Vfde_St; ++ MS_U16 u16Vfde_End; ++ MS_U16 u16Vtt; ++ MS_U16 u16Hsync_St; ++ MS_U16 u16Hsync_End; ++ MS_U16 u16Hde_St; ++ MS_U16 u16Hde_End; ++ MS_U16 u16Hfde_St; ++ MS_U16 u16Hfde_End; ++ MS_U16 u16Htt; ++ MS_U16 u16VFreqx10; ++}ST_PNL_TIMING_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U8 u8YOffset; ++ MS_U8 u8CbOffset; ++ MS_U8 u8CrOffset; ++ MS_U16 u16Coef[9]; ++}ST_PNL_CSC_Y2R_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_PNL_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++ ++INTERFACE MS_BOOL Drv_PNL_Init(ST_PNL_INIT_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_PNL_Set_Timing_Config(ST_PNL_TIMING_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_PNL_Set_CSC_Y2R_Config(ST_PNL_CSC_Y2R_CONFIG *pCfg); ++INTERFACE void Drv_PNL_Resume(void); ++INTERFACE MS_U32 Drv_PNL_GetLPLLDclk(void); ++INTERFACE void Drv_PNL_Release(void); ++INTERFACE MS_BOOL Drv_PNL_GetPnlOpen(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/scldma/drvscldma.c b/drivers/mstar/scl/infinity/src/mxlib/drv/scldma/drvscldma.c +new file mode 100644 +index 00000000..6f6fec6e +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/scldma/drvscldma.c +@@ -0,0 +1,3156 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_SCLDMA_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "drvscldma_st.h" ++#include "halscldma.h" ++#include "drvscldma.h" ++#include "mdrv_scl_dbg.h" ++#include "MsDbg.h" ++#include "ms_msys.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_SCLDMA_DBG(x) ++#define DRV_SCLDMA_DBG_H(x) ++#define DRV_SCLDMA_ERR(x) x ++#define FHD_Width 1920 ++#define FHD_Height 1080 ++#define HD_Width 1280 ++#define HD_Height 720 ++#define PNL_Width 800 ++#define PNL_Height 480 ++#define SINGLE_SKIP 0xF ++#define FRM_POLLIN 0x1 ++#define SNP_POLLIN 0x2 ++#define SCL_IMIinitAddr 0x14000 ++ ++#define SINGLE_BUFF_ACTIVE_TIMIEOUT 100 ++#define _Is_SC1EventNotBeFatch() (!(gu32FRMEvents & (E_SCLIRQ_EVENT_SC1POLL))) ++#define _Is_SC2EventNotBeFatch() (!(gu32SC2FRMEvents & (E_SCLIRQ_EVENT_SC2POLL))) ++#define _Is_SWRingModeBufferNotReady(enClientType) (gstScldmaBufferQueue[enClientType].bUsed ==0) ++#define _Is_SWRingModeBufferReady(enClientType) (gstScldmaBufferQueue[enClientType].bUsed) ++#define _Is_SWRingModeBufferNotFull(enClientType) (!gstScldmaBufferQueue[enClientType].bFull) ++#define _Is_SWRingModeBufferFull(enClientType) (gstScldmaBufferQueue[enClientType].bFull) ++#define _Is_RingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_RING) ++#define _Is_SingleMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SINGLE) ++#define _Is_SWRingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SWRING) ++#define _Is_DMACanReOpen(bReOpen,bRpchange) ((bReOpen)&&(bRpchange)) ++#define _Is_DMAClientOn(enClientType) (gstScldmaInfo.bDMAOnOff[enClientType]) ++#define _Is_DMAClientOff(enClientType) (!gstScldmaInfo.bDMAOnOff[enClientType]) ++#define _IsQueueWriteLargeRead(enClientType) \ ++ (gstScldmaBufferQueue[enClientType].pstWrite > gstScldmaBufferQueue[enClientType].pstRead) ++#define _IsQueueWriteSmallRead(enClientType) \ ++ (gstScldmaBufferQueue[enClientType].pstWrite < gstScldmaBufferQueue[enClientType].pstRead) ++#define _GetInQueueCountIfLarge(enClientType)\ ++ gstScldmaBufferQueue[enClientType].u8InQueueCount =\ ++ (gstScldmaBufferQueue[enClientType].pstWrite - gstScldmaBufferQueue[enClientType].pstRead)/SCLDMA_BUFFER_QUEUE_OFFSET; ++#define _GetInQueueCountIfSmall(enClientType)\ ++ gstScldmaBufferQueue[enClientType].u8InQueueCount =\ ++ ((gstScldmaBufferQueue[enClientType].pstWrite- gstScldmaBufferQueue[enClientType].pstHead)+\ ++ (gstScldmaBufferQueue[enClientType].pstTail- gstScldmaBufferQueue[enClientType].pstRead))\ ++ /SCLDMA_BUFFER_QUEUE_OFFSET; ++#define _Is_IdxRingCircuit(enClientType,idx) (idx == (gstScldmaInfo.bMaxid[enClientType]-1)) ++ ++#define _Is_SC3Singlemode(enClientType) (_Is_SingleMode(enClientType) && \ ++ (enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W)) ++#define _Is_SC3Ringmode(enClientType) (_Is_RingMode(enClientType) && \ ++ (enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W)) ++#define _Is_SC3SWRingmode(enClientType) (_Is_SWRingMode(enClientType) && \ ++ (enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W)) ++ ++#define _Is_OnlySC1SNPSingleDone(u32Event) (u32Event == E_SCLIRQ_EVENT_ISTSC1SNP &&_Is_SingleMode(E_SCLDMA_1_SNP_W)) ++#define _Is_OnlySC1FRMSingleDone(u32Event) (u32Event == E_SCLIRQ_EVENT_ISTSC1FRM &&_Is_SingleMode(E_SCLDMA_1_FRM_W)) ++#define _Is_OnlySC2FRMSingleDone(u32Event) (u32Event == E_SCLIRQ_EVENT_ISTSC2FRM &&_Is_SingleMode(E_SCLDMA_2_FRM_W)) ++#define _Is_VsrcId(enSCLDMA_ID) ((enSCLDMA_ID ==E_SCLDMA_ID_1_W)||(enSCLDMA_ID ==E_SCLDMA_ID_2_W)) ++#define _Is_VsrcDoubleBufferNotOpen() (gVsrcDBnotOpen) ++#define _Is_VsrcDoubleBufferOpen() (!gVsrcDBnotOpen) ++#define SCLDMA_SIZE_ALIGN(x, align) ((x+align) & ~(align-1)) ++#define SCLDMA_CHECK_ALIGN(x, align) (x & (align-1)) ++ ++#define DRV_SCLDMA_MUTEX_LOCK() MsOS_ObtainMutex(_SCLDMA_Mutex,MSOS_WAIT_FOREVER) ++#define DRV_SCLDMA_MUTEX_UNLOCK() MsOS_ReleaseMutex(_SCLDMA_Mutex) ++#define DRV_SCLDMA_MUTEX_LOCK_ISR() MsOS_ObtainMutex_IRQ(_SCLIRQ_SCLDMA_Mutex); ++#define DRV_SCLDMA_MUTEX_UNLOCK_ISR() MsOS_ReleaseMutex_IRQ(_SCLIRQ_SCLDMA_Mutex); ++ ++ ++#define PARSING_SCLDMA_ID(x) (x==E_SCLDMA_ID_1_W ? "SCLDMA_1_W" : \ ++ x==E_SCLDMA_ID_2_W ? "SCLDMA_2_W" : \ ++ x==E_SCLDMA_ID_3_W ? "SCLDMA_3_W" : \ ++ x==E_SCLDMA_ID_3_R ? "SCLDMA_3_R" : \ ++ x==E_SCLDMA_ID_PNL_R ? "SCLDMA_PNL_R" : \ ++ "UNKNOWN") ++ ++ ++ ++#define PARSING_SCLDMA_RWMD(x) (x==E_SCLDMA_FRM_W ? "FRM_W" : \ ++ x==E_SCLDMA_SNP_W ? "SNP_W" : \ ++ x==E_SCLDMA_IMI_W ? "IMI_W" : \ ++ x==E_SCLDMA_FRM_R ? "FRM_R" : \ ++ x==E_SCLDMA_DBG_R ? "DBG_R" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_BUFMD(x) (x==E_SCLDMA_BUF_MD_RING ? "RING" : \ ++ x==E_SCLDMA_BUF_MD_SINGLE ? "SINGLE" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_COLOR(x) (x==E_SCLDMA_COLOR_YUV422 ? "YUV422" : \ ++ x==E_SCLDMA_COLOR_YUV420 ? "YUV420" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_CLIENT(x) (x==E_SCLDMA_1_FRM_W ? "E_SCLDMA_1_FRM_W" : \ ++ x==E_SCLDMA_1_SNP_W ? "E_SCLDMA_1_SNP_W" : \ ++ x==E_SCLDMA_1_IMI_W ? "E_SCLDMA_1_IMI_W" : \ ++ x==E_SCLDMA_2_FRM_W ? "E_SCLDMA_2_FRM_W" : \ ++ x==E_SCLDMA_2_IMI_W ? "E_SCLDMA_2_IMI_W" : \ ++ x==E_SCLDMA_3_FRM_W ? "E_SCLDMA_3_FRM_W" : \ ++ x==E_SCLDMA_3_FRM_R ? "E_SCLDMA_3_FRM_R" : \ ++ x==E_SCLDMA_4_FRM_R ? "E_SCLDMA_4_FRM_R" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_ISR_LOG(x) (x==E_SCLDMA_ISR_LOG_ISPOFF ? "ISPOFF" : \ ++ x==E_SCLDMA_ISR_LOG_SNPONLY ? "SNPONLY" : \ ++ x==E_SCLDMA_ISR_LOG_SNPISR ? "SNPISR" : \ ++ x==E_SCLDMA_ISR_LOG_ISPON ? "ISPON" : \ ++ x==E_SCLDMA_ISR_LOG_SC1ON ? "SC1ON" : \ ++ x==E_SCLDMA_ISR_LOG_SC1OFF ? "SC1OFF" : \ ++ x==E_SCLDMA_ISR_LOG_SC2ON ? "SC2ON" : \ ++ x==E_SCLDMA_ISR_LOG_SC2OFF ? "SC2OFF" : \ ++ x==E_SCLDMA_ISR_LOG_SC1A ? "SC1A" : \ ++ x==E_SCLDMA_ISR_LOG_SC1N ? "SC1N" : \ ++ x==E_SCLDMA_ISR_LOG_SC2A ? "SC2A" : \ ++ x==E_SCLDMA_ISR_LOG_SC2N ? "SC2N" : \ ++ x==E_SCLDMA_ISR_LOG_FRMEND ? "FRMEND" : \ ++ "UNKNOWN") ++ ++ ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// _SCLDMA_Mutex ++/// use in scldma mutex,not include isr ++//////////////// ++MS_S32 _SCLDMA_Mutex = -1; ++ ++///////////////// ++/// _SCLIRQ_SCLDMA_Mutex ++/// scldma and sclirq mutex, include isr ++//////////////// ++MS_S32 _SCLIRQ_SCLDMA_Mutex = -1; ++ ++///////////////// ++/// gVsrcDBnotOpen ++/// if True ,DMA switch Double buffer not open ++//////////////// ++MS_BOOL gVsrcDBnotOpen; ++ ++///////////////// ++/// gu32FRMEvents ++/// used to save DMA event for diffenent client ++//////////////// ++MS_U32 gu32FRMEvents; ++MS_U32 gu32SC2FRMEvents; ++ ++///////////////// ++/// gu8ISPcount ++/// save frame count from ISP_hw - scl_delay ++//////////////// ++MS_U8 gu8ISPcount; ++ ++///////////////// ++/// gu32FRMDoneTime ++/// save frame done time. ++//////////////// ++MS_U32 gu32FRMDoneTime; ++ ++///////////////// ++/// gu32TrigCount ++/// save dma trig off times. ++//////////////// ++MS_U32 gu32TrigCount[E_SCLDMA_CLIENT_NUM]; ++MS_BOOL gbForceClose[E_SCLDMA_CLIENT_NUM]; ++ST_SCLDMA_INFO_TYPE gstScldmaInfo; ++ST_SCLDMA_BUFFER_QUEUE_CONFIG gstScldmaBufferQueue[E_SCLDMA_CLIENT_NUM]; ++ ++MS_BOOL gbScldmaSuspend; ++MS_BOOL gbDBStatus; ++#if SCLDMA_IRQ_EN ++EN_SCLDMA_IRQ_MODE_TYPE genIrqMode[E_SCLDMA_CLIENT_NUM]; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Functions/ ++//------------------------------------------------------------------------------------------------- ++#if SCLDMA_DBG_Thread ++MS_BOOL bcreat = 0; ++ST_SCLDMA_THREAD_CONFIG g_stthcfg = {0,NULL}; ++MS_BOOL _Delete_SCLDMA_Thread(void) ++{ ++ g_stthcfg.flag = 0; ++ if(g_stthcfg.sttask.pThread) ++ { ++ kthread_stop(g_stthcfg.sttask.pThread); ++ g_stthcfg.sttask.pThread = NULL; ++ printf("[HVSP]stop thread\n"); ++ } ++ bcreat = 0; ++ return 0; ++} ++ ++static int SCLDMA_hold_Thread(void *arg) ++{ ++ MS_U16 u16IrqNum; ++ MS_U64 u64Flag_E,u64Flag_S; ++ MS_U16 u32Scount = 0; ++ MS_U16 u16Stime; ++ printf("[DRVSCLDMA]%s:doing\n",__FUNCTION__); ++ u16IrqNum = SCLIRQ_TRIG_LDC; ++ ++ while(g_stthcfg.flag == 1) ++ { ++ Drv_SCLIRQ_Get_Flag(u16IrqNum, &u64Flag_E); ++ Drv_SCLIRQ_Get_Flag(4, &u64Flag_S); ++ if(u64Flag_S) ++ { ++ if(u64Flag_S) ++ { ++ u16Stime = (MS_U32)MsOS_GetSystemTime(); ++ u32Scount++; ++ Drv_SCLIRQ_Set_Clear(SCLIRQ_VSYNC_IDCLK); ++ printf("[DRVSCLDMA]IN_FRM_END time:%d, count:%d\n",u16Stime,u32Scount); ++ } ++ } ++ } ++ _Delete_SCLDMA_Thread(); ++ ++ return 0; ++ ++} ++ ++MS_BOOL _Create_SCLDMA_Thread(void) ++{ ++ MS_BOOL bCreate = FALSE; ++ const char *pName = {"HVSP_THREAD"};; ++ if(!bcreat) ++ g_stthcfg.sttask.pThread = kthread_create(SCLDMA_hold_Thread,(void *)&g_stthcfg,pName); ++ bCreate = TRUE; ++ bcreat = 1; ++ if(bCreate) ++ { ++ if (IS_ERR(g_stthcfg.sttask.pThread)) ++ { ++ g_stthcfg.sttask.pThread = NULL; ++ Drv_SCLDMA_SetThreadOnOffFlag(0,&g_stthcfg); ++ printf("[DRVSCLDMA]Fail:creat thread\n"); ++ return FALSE; ++ } ++ else ++ { ++ Drv_SCLDMA_SetThreadOnOffFlag(1,&g_stthcfg); ++ wake_up_process(g_stthcfg.sttask.pThread ); ++ } ++ } ++ ++ return 0; ++} ++#endif ++ ++void Drv_SCLDMA_SetThreadOnOffFlag(MS_BOOL bEn,ST_SCLDMA_THREAD_CONFIG *stthcfg) ++{ ++ stthcfg->flag = bEn; ++} ++void _Drv_SCLDMA_SC1OnOff(EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn) ++{ ++ Hal_SCLDMA_SetSC1HandshakeForce(enRW, bEn); ++ Hal_SCLDMA_SetSC1DMAEn(enRW, bEn); ++} ++void _Drv_SCLDMA_SC1OnOffWithoutDoubleBuffer ++ (EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn,EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ _Drv_SCLDMA_SC1OnOff(enRW, bEn); ++ } ++ else ++ { ++ if(bEn) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_ON); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else ++ { ++ _Drv_SCLDMA_SC1OnOff(enRW, bEn); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&(Get_DBGMG_SCLDMAclient(enClientType,1)), ++ "[DRMSCLDMA]%s %d wait for blanking\n", ++ __FUNCTION__,enClientType); ++ } ++} ++void _Drv_SCLDMA_SC2OnOff(EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn) ++{ ++ Hal_SCLDMA_SetSC2HandshakeForce(enRW, bEn); ++ Hal_SCLDMA_SetSC1ToSC2HandshakeForce(bEn); ++ Hal_SCLDMA_SetSC2DMAEn(enRW, bEn); ++} ++void _Drv_SCLDMA_SC2OnOffWithoutDoubleBuffer ++ (EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn,EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ _Drv_SCLDMA_SC2OnOff(enRW, bEn); ++ } ++ else ++ { ++ if(bEn) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_ON); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else ++ { ++ _Drv_SCLDMA_SC2OnOff(enRW, bEn); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&(Get_DBGMG_SCLDMAclient(enClientType,1)), ++ "[DRMSCLDMA]%s %d wait for blanking\n", ++ __FUNCTION__,enClientType); ++ } ++} ++void _Drv_SCLDMA_SWRegenVSyncTrigger(EN_SCLDMA_VS_ID_TYPE enIDType) ++{ ++ Hal_SCLDMA_TrigRegenVSync(enIDType,1); ++} ++void _Drv_SCLDMA_SetVsyncRegenMode(EN_SCLDMA_VS_ID_TYPE enIDType, EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigType) ++{ ++ Hal_SCLDMA_SetVSyncRegenMode(enIDType,enTrigType); ++} ++void _Drv_SCLDMA_SetVsyncTrigConfig(EN_SCLDMA_VS_ID_TYPE enIDType) ++{ ++ //hard code by hw setting ++ Hal_SCLDAM_SetRegenVSyncStartPoint(enIDType,10); ++ Hal_SCLDAM_SetRegenVSyncWidth(enIDType,40); ++} ++void _Drv_SCLDMA_ResetGlobalParameter(void) ++{ ++ MS_U8 u8ClientIdx; ++ for(u8ClientIdx=0; u8ClientIdxu32IRQNum; ++ if(Drv_SCLIRQ_Suspend(&stSclIrqCfg)) ++ { ++ bRet = TRUE; ++ gbScldmaSuspend = 1; ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s Suspend fail\n", __FUNCTION__)); ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s not all scldma suspend\n",__FUNCTION__); ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s already suspend\n",__FUNCTION__); ++ bRet = TRUE; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL Drv_SCLDMA_Resume(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_SCLIRQ_SUSPEND_RESUME_CONFIG stSclIrqCfg; ++ MS_BOOL bRet = TRUE; ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s(%d), ID:%s(%d), bSuspend=%d\n", ++ __FUNCTION__, __LINE__, PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID, gbScldmaSuspend); ++ ++ if(gbScldmaSuspend == 1) ++ { ++ stSclIrqCfg.u32IRQNUM = pCfg->u32IRQNum; ++ if(Drv_SCLIRQ_Resume(&stSclIrqCfg)) ++ { ++ gstScldmaInfo.u64mask = 0; ++ _Drv_SCLDMA_HWInitProcess(); ++ gbScldmaSuspend = 0; ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_EventID(), E_SCLIRQ_EVENT_RESUME); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SC3EventID(), E_SCLIRQ_SC3EVENT_RESUME); ++ bRet = TRUE; ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s Resume fail\n", __FUNCTION__)); ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s already Resume\n",__FUNCTION__); ++ bRet = TRUE; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL Drv_SCLDMA_Init(ST_SCLDMA_INIT_CONFIG *pInitCfg) ++{ ++ char word[] = {"_SCLDMA_Mutex"}; ++ char word2[] = {"_IRQDMA_Mutex"}; ++ //int i; ++ ST_SCLIRQ_INIT_CONFIG stIRQInitCfg; ++ ++ if(_SCLDMA_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s already done\n",__FUNCTION__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s MsOS_Init Fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ _SCLDMA_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ _SCLIRQ_SCLDMA_Mutex = MsOS_CreateSpinlock(E_MSOS_FIFO, word2, MSOS_PROCESS_SHARED); ++ if (_SCLDMA_Mutex == -1) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s create mutex fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ stIRQInitCfg.u32RiuBase = pInitCfg->u32RIUBase; ++ ++ ++ // init processing ++ ++ Hal_SCLDMA_SetRiuBase(pInitCfg->u32RIUBase); ++ if(Drv_SCLIRQ_Init(&stIRQInitCfg) == FALSE) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s Init IRQ Fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++ _Drv_SCLDMA_InitVariable(); ++ ++#if SCLDMA_IRQ_EN ++ ++ gstScldmaInfo.s32IrqEventId = MsOS_CreateEventGroup("SCLDMA_IRQ_EVENT"); ++ ++ if(gstScldmaInfo.s32IrqEventId < 0) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s(%d) Create Event Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ gstScldmaInfo.s32IrqTaskid = MsOS_CreateTask((TaskEntry)_Drv_SCLDMA_Irq_Event_Task, ++ (MS_U32)NULL, ++ TRUE, ++ (char*)"DrvScldma_Event_Task"); ++ ++ if(gstScldmaInfo.s32IrqTaskid < 0) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s(%d) Create Task Fail\n", __FUNCTION__, __LINE__)); ++ MsOS_DeleteEventGroup(gstScldmaInfo.s32IrqEventId); ++ return FALSE; ++ } ++ ++ gstScldmaInfo.s32IrqTimerId = MsOS_CreateTimer( _Drv_SCLDMA_CheckIrq_TimerCallback, ++ 5, ++ 5, ++ TRUE, ++ (char*)"SCLDMA_IRQ_TIMER"); ++ ++ if(gstScldmaInfo.s32IrqTimerId < 0) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s(%d) Create Timer Fail\n", __FUNCTION__, __LINE__)); ++ MsOS_DeleteEventGroup(gstScldmaInfo.s32IrqEventId); ++ MsOS_DeleteTask(gstScldmaInfo.s32IrqTaskid); ++ return FALSE; ++ } ++#endif ++ ++ _Drv_SCLDMA_HWInitProcess(); ++ ++ return TRUE; ++} ++ ++void Drv_SCLDMA_Sys_Init(MS_BOOL bEn) ++{ ++#if ENABLE_RING_DB ++ if(bEn) ++ { ++ ST_SCLDMA_RW_CONFIG stIMICfg; ++ stIMICfg.enRWMode = E_SCLDMA_IMI_W; ++ stIMICfg.u16Height = HD_Height; ++ stIMICfg.u16Width = HD_Width; ++ stIMICfg.u8MaxIdx = 0; ++ stIMICfg.u8Flag = 1; ++ stIMICfg.enBuffMode = E_SCLDMA_BUF_MD_RING; ++ stIMICfg.u32Base_Y[0] = SCL_IMIinitAddr; ++ stIMICfg.u32Base_C[0] = SCL_IMIinitAddr; ++ stIMICfg.enColor = E_SCLDMA_COLOR_YUV420 ; ++ Drv_SCLDMA_SetDMAClientConfig(E_SCLDMA_ID_1_W,stIMICfg); ++ } ++ else ++ { ++ Hal_SCLDMA_SetIMIClientReset(); ++ } ++#endif ++ ++ printf("[DRVSCLDMA] Double Buffer Status :%hhd\n",gbDBStatus); ++} ++void _Drv_SCLDMA_ResetGlobalSwitchByID(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U8 u8ClientIdx; ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ ++ for(u8ClientIdx=0; u8ClientIdx 1) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: More than 1 buffer to SINGLE mode\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ ++ if(stCfg.enRWMode == E_SCLDMA_RW_NUM) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: RW mode is not coreect\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ ++ for(u8BufferIdx=0; u8BufferIdx<=stCfg.u8MaxIdx; u8BufferIdx++) ++ { ++ if( SCLDMA_CHECK_ALIGN(stCfg.u32Base_Y[u8BufferIdx], 8)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: YBase must be 8 byte align\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ break; ++ } ++ ++ if(stCfg.enColor == E_SCLDMA_COLOR_YUV420 && ++ SCLDMA_CHECK_ALIGN(stCfg.u32Base_C[u8BufferIdx], 8)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: CBase must be 8 byte align DmaID:%s(%d)\n", __FUNCTION__, __LINE__,PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID)); ++ bRet = FALSE; ++ break; ++ } ++ } ++ ++ if(stCfg.enColor == E_SCLDMA_COLOR_YUV422) ++ { ++ for(u8BufferIdx=0; u8BufferIdx<=stCfg.u8MaxIdx; u8BufferIdx++) ++ { ++ if((stCfg.u32Base_C[u8BufferIdx] != (stCfg.u32Base_Y[u8BufferIdx] + 16) )) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]Error:%s %d: YUV422 CBase_%08lx, YBase_%08lx, \n", ++ __FUNCTION__, __LINE__, stCfg.u32Base_Y[u8BufferIdx], stCfg.u32Base_C[u8BufferIdx])); ++ bRet = FALSE; ++ } ++ } ++ } ++ ++ if(bRet == FALSE) ++ { ++ return FALSE; ++ } ++ ++ _Drv_SCLDMA_SetDMAInformationForGlobal(enClientType, stCfg); ++ _Drv_SCLDMA_SetVsyncTrigMode(enClientType); ++ ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetSC1DMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ case E_SCLDMA_ID_2_W: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetSC2DMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ case E_SCLDMA_ID_3_W: ++ case E_SCLDMA_ID_3_R: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetSC3DMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ case E_SCLDMA_ID_PNL_R: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetDisplayDMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ default: ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++MS_U16 _Drv_SCLDMA_GetActiveIRQNum(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16IrqNum; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16IrqNum = SCLIRQ_SC1_FRM_W_ACTIVE; ++ break; ++ case E_SCLDMA_1_SNP_W: ++ u16IrqNum = SCLIRQ_SC1_SNP_W_ACTIVE; ++ break; ++ case E_SCLDMA_1_IMI_W: ++ u16IrqNum = SCLIRQ_SC1_SNPI_W_ACTIVE; ++ break; ++ case E_SCLDMA_2_FRM_W: ++ u16IrqNum = SCLIRQ_SC2_FRM_W_ACTIVE; ++ break; ++ case E_SCLDMA_2_IMI_W: ++ u16IrqNum = SCLIRQ_SC2_FRMI_W_ACTIVE; ++ break; ++ case E_SCLDMA_3_FRM_W: ++ u16IrqNum = SCLIRQ_SC3_DMA_W_ACTIVE; ++ break; ++ case E_SCLDMA_3_FRM_R: ++ u16IrqNum = SCLIRQ_SC3_DMA_R_ACTIVE; ++ break; ++ case E_SCLDMA_4_FRM_R: ++ u16IrqNum = SCLIRQ_SC1_DBG_R_ACTIVE; ++ break; ++ default: ++ u16IrqNum = SCLIRQ_RESERVED; ++ break; ++ } ++ ++ return u16IrqNum; ++} ++void _Drv_SCLDMA_ResetTrigCount(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn) ++{ ++ if(!bEn) ++ { ++ gu32TrigCount[enClientType]++; ++ if(gu32TrigCount[enClientType]==0xEFFFFFFE) ++ { ++ gu32TrigCount[enClientType] = 1; ++ } ++ } ++ else ++ { ++ gu32TrigCount[enClientType]--; ++ } ++} ++MS_BOOL Drv_SCLDMA_SetISRHandlerDMAOff(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ MS_U64 u64ActN; ++ MS_BOOL bRet = 0; ++ if(gstScldmaInfo.bDMAOnOff[enClientType] == 0 &&_Is_RingMode(enClientType)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClientType,1), "[DRVSCLDMA] %s:: enClientType:%d still ON/OFF %hhd\n", ++ __FUNCTION__,enClientType,bEn); ++ } ++ else if(gstScldmaInfo.bDMAOnOff[enClientType] == bEn &&_Is_RingMode(enClientType)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClientType,1), "[DRVSCLDMA] %s:: enClientType:%d still ON/OFF %hhd\n", ++ __FUNCTION__,enClientType,bEn); ++ } ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ case E_SCLDMA_2_FRM_W: ++ case E_SCLDMA_3_FRM_W: ++ enRWMode = E_SCLDMA_FRM_W; ++ break; ++ case E_SCLDMA_1_SNP_W: ++ enRWMode = E_SCLDMA_SNP_W; ++ break; ++ case E_SCLDMA_1_IMI_W: ++ case E_SCLDMA_2_IMI_W: ++ enRWMode = E_SCLDMA_IMI_W; ++ break; ++ case E_SCLDMA_3_FRM_R: ++ enRWMode = E_SCLDMA_FRM_R; ++ break; ++ case E_SCLDMA_4_FRM_R: ++ enRWMode = E_SCLDMA_DBG_R; ++ break; ++ default: ++ enRWMode = E_SCLDMA_RW_NUM; ++ break; ++ ++ } ++ if(enClientType == E_SCLDMA_1_FRM_W || enClientType == E_SCLDMA_1_SNP_W || enClientType == E_SCLDMA_1_IMI_W) ++ { ++ if(bEn && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_Get_Flag((_Drv_SCLDMA_GetActiveIRQNum(enClientType)+1), &u64ActN); ++ if(!u64ActN) ++ { ++ _Drv_SCLDMA_SC1OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ } ++ else ++ { ++ _Drv_SCLDMA_SC1OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ else if(enClientType == E_SCLDMA_2_FRM_W || enClientType == E_SCLDMA_2_IMI_W) ++ { ++ if(bEn && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_Get_Flag((_Drv_SCLDMA_GetActiveIRQNum(enClientType)+1), &u64ActN); ++ if(!u64ActN) ++ { ++ _Drv_SCLDMA_SC2OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ } ++ else ++ { ++ _Drv_SCLDMA_SC2OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ else if(enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ if(bEn && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_Get_Flag((_Drv_SCLDMA_GetActiveIRQNum(enClientType)+1), &u64ActN); ++ if(!u64ActN) ++ { ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_R, bEn); ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_W, bEn); ++ bRet = bEn; ++ } ++ } ++ else ++ { ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_R, bEn); ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_W, bEn); ++ bRet = bEn; ++ } ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ else ++ { ++ Hal_SCLDMA_SetDisplayDMAEn(enRWMode, bEn); ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ ++ if(enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClientType,1), "[DRVSCLDMA]%s Client:%s trig off\n", ++ __FUNCTION__,PARSING_SCLDMA_CLIENT(enClientType)); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(8,1), "[DRVSCLDMA]%s Client:%s trig off\n", ++ __FUNCTION__,PARSING_SCLDMA_CLIENT(enClientType)); ++ } ++ return bRet; ++} ++void Drv_SCLDMA_DoubleBufferOnOffById(MS_BOOL bEn, EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ if(enSCLDMA_ID <= E_SCLDMA_ID_2_W) ++ { ++ Hal_SCLDMA_SetHandshakeDoubleBuffer(bEn); ++ gVsrcDBnotOpen = !bEn; ++ } ++ Hal_SCLDMA_SetDMAEnableDoubleBuffer(bEn,enSCLDMA_ID); ++} ++void Drv_SCLDMA_SetISPFrameCount(void) ++{ ++ gu8ISPcount = Hal_SCLDMA_GetISPFrameCountReg(); ++ if(SCL_DELAYFRAME_FROM_ISP == 1) ++ { ++ gu8ISPcount = (gu8ISPcount==0) ? 0x7F : (gu8ISPcount -1); ++ } ++ else if(SCL_DELAYFRAME_FROM_ISP == 2) ++ { ++ gu8ISPcount = (gu8ISPcount==0) ? 0x7E : ++ (gu8ISPcount==1) ? 0x7F :(gu8ISPcount -2); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()==EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLDMA]ISP Count:%hhx\n",gu8ISPcount); ++} ++void Drv_SCLDMA_SetSclFrameDoneTime(MS_U32 u32FRMDoneTime) ++{ ++ gu32FRMDoneTime = u32FRMDoneTime; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()==EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLDMA]FRMDoneTime:%lu\n",gu32FRMDoneTime); ++} ++EN_SCLDMA_DB_STATUS_TYPE Drv_SCLDMA_GetVsrcDoubleBufferStatus(MS_U32 u32Event) ++{ ++ MS_U32 enClientIdx; ++ MS_U8 bNeedOff = 0; ++ if(_Is_OnlySC1SNPSingleDone(u32Event))//only sc1 snp ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE,"[DRVSCLDMA] ONLY_SC1_SNP_SI_NEED_OFF \n"); ++ return EN_SCLDMA_DB_STATUS_NEED_OFF;//db off ++ } ++ else if(_Is_OnlySC1FRMSingleDone(u32Event))//only sc1 frm snp ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE,"[DRVSCLDMA] ONLY_SC1_FRM_SI_NEED_OFF \n"); ++ return EN_SCLDMA_DB_STATUS_NEED_OFF;//db off ++ } ++ else if(_Is_OnlySC2FRMSingleDone(u32Event))//only sc2 frm snp ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE,"[DRVSCLDMA] ONLY_SC2_FRM_SI_NEED_OFF \n"); ++ return EN_SCLDMA_DB_STATUS_NEED_OFF;//db off ++ } ++ else ++ { ++ for(enClientIdx= E_SCLDMA_1_FRM_W; enClientIdxenID ,pCfg->enRWMode); ++ if(_Is_SWRingModeBufferReady(enClientType)) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _Drv_SCLDMA_GetInQueueCount(enClientType); ++ pCfg->pstRead = gstScldmaBufferQueue[enClientType].pstRead; ++ pCfg->u8InQueueCount = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ pCfg->u8AccessId = gstScldmaBufferQueue[enClientType].u8AccessId; ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ //printf("[DRVSCLDMA]%d PEEK W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ //pCfg->pstWriteAlready->u8FrameAddrIdx, pCfg->pstRead->u8FrameAddrIdx,pCfg->u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ pCfg->pstWrite->u8FrameAddrIdx, pCfg->pstRead->u8FrameAddrIdx,pCfg->u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d non-used Buffer Queue\n",enClientType )); ++ } ++} ++void _Drv_SCLDMA_BufferClearQueue(EN_SCLDMA_CLIENT_TYPE enClientType,unsigned char u8idx) ++{ ++ ST_SCLDMA_FRAME_BUFFER_CONFIG *stCfg; ++ unsigned char u8BufferIdx; ++ if(_Is_SWRingModeBufferReady(enClientType)) ++ { ++ stCfg = gstScldmaBufferQueue[enClientType].pstHead; ++ for(u8BufferIdx = 0; u8BufferIdx<=gstScldmaInfo.bMaxid[enClientType]; u8BufferIdx++) ++ { ++ if(stCfg->u8FrameAddrIdx == u8idx && stCfg->u32FrameAddr != 0) ++ { ++ MsOS_Memset(stCfg,0,SCLDMA_BUFFER_QUEUE_OFFSET); ++ break; ++ } ++ else ++ { ++ stCfg += SCLDMA_BUFFER_QUEUE_OFFSET; ++ } ++ } ++ } ++} ++ST_SCLDMA_FRAME_BUFFER_CONFIG * _Drv_SCLDMA_MoveBufferQueueReadPoint(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstCfg; ++ pstCfg = gstScldmaBufferQueue[enClientType].pstRead; ++ gstScldmaBufferQueue[enClientType].pstRead = gstScldmaBufferQueue[enClientType].pstRead + SCLDMA_BUFFER_QUEUE_OFFSET; ++ if(gstScldmaBufferQueue[enClientType].pstRead >=gstScldmaBufferQueue[enClientType].pstTail) ++ { ++ gstScldmaBufferQueue[enClientType].pstRead = gstScldmaBufferQueue[enClientType].pstHead; ++ } ++ if(_Is_SWRingModeBufferFull(enClientType)) ++ { ++ gstScldmaBufferQueue[enClientType].bFull = 0; ++ } ++ _SetANDGetIdxType(enClientType,(pstCfg->u8FrameAddrIdx<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ return pstCfg; ++} ++void Drv_SCLDMA_BufferDeQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ unsigned char u8count; ++ enClientType = _Drv_SCLDMA_TransToClientType(pCfg->enID ,pCfg->enRWMode); ++ if(_Is_SWRingModeBufferReady(enClientType)) ++ { ++ u8count = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ if(u8count) ++ { ++ pCfg->pstRead = _Drv_SCLDMA_MoveBufferQueueReadPoint(enClientType); ++ } ++ _Drv_SCLDMA_GetInQueueCount(enClientType); ++ pCfg->pstHead = gstScldmaBufferQueue[enClientType].pstHead; ++ pCfg->pstTail = gstScldmaBufferQueue[enClientType].pstTail; ++ pCfg->pstWrite = gstScldmaBufferQueue[enClientType].pstWrite; ++ pCfg->pstWriteAlready = gstScldmaBufferQueue[enClientType].pstWriteAlready; ++ pCfg->u8InQueueCount = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ //printf("[DRVSCLDMA]%d DeQueue :R_P:%lx R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ // pCfg->pstRead->u32FrameAddr, pCfg->pstRead->u8FrameAddrIdx,gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d DeQueue :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ pCfg->pstWriteAlready->u8FrameAddrIdx,gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx,gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d non-used Buffer Queue\n",enClientType )); ++ } ++} ++void _Drv_SCLDMA_BufferFillQueue(ST_SCLDMA_FRAME_BUFFER_CONFIG *stCfg,const ST_SCLDMA_FRAME_BUFFER_CONFIG stTarget) ++{ ++ MsOS_Memcpy(stCfg,&stTarget,SCLDMA_BUFFER_QUEUE_OFFSET); ++} ++void _Drv_SCLDMA_MoveBufferQueueWritePoint(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ gstScldmaBufferQueue[enClientType].pstWriteAlready = gstScldmaBufferQueue[enClientType].pstWrite; ++ gstScldmaBufferQueue[enClientType].pstWrite += SCLDMA_BUFFER_QUEUE_OFFSET; ++ if(gstScldmaBufferQueue[enClientType].pstWrite >=gstScldmaBufferQueue[enClientType].pstTail) ++ { ++ gstScldmaBufferQueue[enClientType].pstWrite = gstScldmaBufferQueue[enClientType].pstHead; ++ } ++ ++ if(gstScldmaBufferQueue[enClientType].pstWrite == gstScldmaBufferQueue[enClientType].pstRead) ++ { ++ gstScldmaBufferQueue[enClientType].bFull = 1; ++ } ++} ++unsigned char Drv_SCLDMA_GetDoneBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ unsigned char u8BufIdx; ++ u8BufIdx = gstScldmaBufferQueue[enClientType].pstWriteAlready->u8FrameAddrIdx; ++ return u8BufIdx; ++} ++unsigned char Drv_SCLDMA_GetNextBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ unsigned char u8BufIdx; ++ u8BufIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ if(u8BufIdx == gstScldmaInfo.bMaxid[enClientType]) ++ { ++ u8BufIdx = 0; ++ } ++ else ++ { ++ u8BufIdx++; ++ } ++ return u8BufIdx; ++} ++unsigned char Drv_SCLDMA_GetActiveBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ unsigned char u8BufIdx; ++ u8BufIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ return u8BufIdx; ++} ++void _Drv_SCLDMA_DisableBufferAccess(EN_SCLDMA_CLIENT_TYPE enClientType,MS_U8 u8FrameAddrIdx) ++{ ++ gstScldmaBufferQueue[enClientType].u8Bufferflag &= ~(0x1<enID ,pCfg->enRWMode); ++ //printf("[DRVSCLDMA]EnableBufferAccess%d :%hhd\n",enClientType,pCfg->u8NextActiveId); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]EnableBufferAccess%d :%hhd\n",enClientType,pCfg->u8AccessId); ++ _Drv_SCLDMA_BufferClearQueue(enClientType,pCfg->u8AccessId); ++ _Drv_SCLDMA_EnableBufferAccess(enClientType,pCfg->u8AccessId); ++} ++MS_BOOL Drv_SCLDMA_MakeSureNextActiveId(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U8 u8BufferIdx; ++ MS_U8 u8FrameAddrIdx; ++ u8FrameAddrIdx = Drv_SCLDMA_GetNextBufferIdx(enClientType); ++ for(u8BufferIdx = 0; u8BufferIdxgstScldmaInfo.bMaxid[enClientType]) ++ { ++ u8FrameAddrIdx = 0; ++ } ++ ++ if(_Is_IdxRingCircuit(enClientType,u8BufferIdx)) ++ { ++ //DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d ChangeBufferIdx Fail\n",enClientType)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA] enClientType:%d ChangeBufferIdx Fail\n",enClientType); ++ } ++ } ++ } ++ return 0; ++} ++void _Drv_SCLDMA_ChangeSC3RBufferOnlyForSC3Mode(EN_SCLDMA_CLIENT_TYPE enClientType,MS_U8 u8FrameAddrIdx) ++{ ++ if(enClientType ==E_SCLDMA_3_FRM_W) ++ { ++ Hal_SCLDMA_SetDMAOutputBufferAddr(E_SCLDMA_3_FRM_R, ++ gstScldmaInfo.u32Base_Y[E_SCLDMA_3_FRM_R][u8FrameAddrIdx], ++ gstScldmaInfo.u32Base_C[E_SCLDMA_3_FRM_R][u8FrameAddrIdx]); ++ } ++} ++void Drv_SCLDMA_ChangeBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U8 u8FrameAddrIdx; ++ u8FrameAddrIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ Hal_SCLDMA_SetDMAOutputBufferAddr(enClientType, ++ gstScldmaInfo.u32Base_Y[enClientType][u8FrameAddrIdx], ++ gstScldmaInfo.u32Base_C[enClientType][u8FrameAddrIdx]); ++ _Drv_SCLDMA_ChangeSC3RBufferOnlyForSC3Mode(enClientType,u8FrameAddrIdx); ++ ++} ++unsigned char _Drv_SCLDMA_GetISPCount(void) ++{ ++ return ((gu8ISPcount==0x7F) ? 0 : (gu8ISPcount +1)); ++} ++void Drv_SCLDMA_SetFrameResolution(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ gstScldmaInfo.u16FrameHeight[enClientType] = Hal_SCLDMA_GetOutputVsize(enClientType); ++ gstScldmaInfo.u16FrameWidth[enClientType] = Hal_SCLDMA_GetOutputHsize(enClientType); ++} ++unsigned char Drv_SCLDMA_BufferEnQueue(EN_SCLDMA_CLIENT_TYPE enClientType,ST_SCLDMA_FRAME_BUFFER_CONFIG stTarget) ++{ ++ if(_Is_SWRingModeBufferReady(enClientType) && _Is_SWRingModeBufferNotFull(enClientType)) ++ { ++ stTarget.u8ISPcount = _Drv_SCLDMA_GetISPCount(); ++ _Drv_SCLDMA_BufferFillQueue(gstScldmaBufferQueue[enClientType].pstWrite,stTarget); ++ _Drv_SCLDMA_MoveBufferQueueWritePoint(enClientType); ++ _Drv_SCLDMA_DisableBufferAccess(enClientType,stTarget.u8FrameAddrIdx); ++ _Drv_SCLDMA_GetInQueueCount(enClientType); ++ ++ //printf("[DRVSCLDMA]%d EnQueue :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ //gstScldmaBufferQueue[enClientType].pstWriteAlready->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d EnQueue :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ gstScldmaBufferQueue[enClientType].pstWriteAlready->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ return 1; ++ } ++ else if(_Is_SWRingModeBufferFull(enClientType)) ++ { ++ //printf("[DRVSCLDMA]%d EnQueue Fail (FULL) :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ //gstScldmaBufferQueue[enClientType].pstWrite->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d EnQueue Fail (FULL) :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ gstScldmaBufferQueue[enClientType].pstWrite->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ return 0; ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d non-used Buffer Queue\n",enClientType )); ++ return 0; ++ } ++} ++MS_BOOL _Drv_SCLDMA_IsVsrcEventNotBeFatch(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_ID_1_W) ++ { ++ return _Is_SC1EventNotBeFatch(); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_ID_2_W) ++ { ++ return _Is_SC2EventNotBeFatch(); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] error ID:%d\n",enSCLDMA_ID )); ++ return 0; ++ } ++} ++MS_U32 _Drv_SCLDMA_GetEventById(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U32 u32Events; ++ MS_U32 *p32PointToStatic = (enSCLDMA_ID ==E_SCLDMA_ID_1_W) ? &gu32FRMEvents: &gu32SC2FRMEvents; ++ MS_U32 *p32PointToOtherStatic = (enSCLDMA_ID ==E_SCLDMA_ID_1_W) ? &gu32SC2FRMEvents: &gu32FRMEvents; ++ SCLIRQTXEvent enClearEventById = (enSCLDMA_ID ==E_SCLDMA_ID_1_W)? E_SCLIRQ_EVENT_SC1POLL : E_SCLIRQ_EVENT_SC2POLL; ++ SCLIRQTXEvent enRemainEventById = (enSCLDMA_ID ==E_SCLDMA_ID_1_W) ? E_SCLIRQ_EVENT_SC2POLL : E_SCLIRQ_EVENT_SC1POLL; ++ if(_Drv_SCLDMA_IsVsrcEventNotBeFatch(enSCLDMA_ID)) ++ { ++ u32Events = MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_EventID()); ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_EventID(),(u32Events & (E_SCLIRQ_EVENT_ALLPOLL))); ++ DRV_SCLDMA_MUTEX_LOCK(); ++ if(*p32PointToOtherStatic ==0) ++ { ++ *p32PointToOtherStatic = u32Events& (E_SCLIRQ_EVENT_ALLPOLL) ; ++ *p32PointToOtherStatic &= ~enClearEventById; ++ } ++ else ++ { ++ *p32PointToOtherStatic = *p32PointToOtherStatic | (u32Events & (enRemainEventById)); ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ } ++ else ++ { ++ DRV_SCLDMA_MUTEX_LOCK(); ++ u32Events = *p32PointToStatic; ++ *p32PointToStatic = 0; ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ } ++ return u32Events; ++} ++MS_BOOL _Drv_SCLDMA_GetSC3DoneFlagAndClearSC3Event(MS_U32 u32Events) ++{ ++ MS_BOOL bDone; ++ if((u32Events & E_SCLIRQ_SC3EVENT_DONE) == E_SCLIRQ_SC3EVENT_DONE) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_SC3EVENT_RESTART))) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if(u32Events & E_SCLIRQ_EVENT_RESUME) ++ { ++ bDone = FRM_POLLIN; ++ } ++ else //timeout ++ { ++ bDone = FALSE; ++ } ++ if(bDone) ++ { ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SC3EventID(),(u32Events & E_SCLIRQ_SC3EVENT_POLL)); ++ } ++ return bDone; ++} ++MS_BOOL _Drv_SCLDMA_GetSC2DoneFlag(MS_U32 u32Events) ++{ ++ MS_BOOL bSINGLE_SKIP = 0; ++ MS_BOOL bDone; ++ bSINGLE_SKIP = (u32Events&E_SCLIRQ_EVENT_SC2FRM)? !(_IsFlagType(E_SCLDMA_2_FRM_W,E_SCLDMA_FLAG_FRMIN)) ++ : 0; ++ if((u32Events & E_SCLIRQ_EVENT_SC2FRM) && bSINGLE_SKIP) //ISP FIFO FULL ++ { ++ bDone = SINGLE_SKIP; ++ if((u32Events & (E_SCLIRQ_EVENT_SC2RE))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ } ++ else if((u32Events & E_SCLIRQ_EVENT_SC2FRM)) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC2RESTART))) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if(u32Events & E_SCLIRQ_EVENT_RESUME) ++ { ++ bDone = FRM_POLLIN; ++ } ++ else //timeout ++ { ++ bDone = FALSE; ++ } ++ return bDone; ++} ++MS_BOOL _Drv_SCLDMA_GetSC1DoneFlag(MS_U32 u32Events) ++{ ++ MS_BOOL bSINGLE_SKIP = 0; ++ MS_BOOL bDone; ++ bSINGLE_SKIP = (u32Events&E_SCLIRQ_EVENT_SC1SNP)? !(_IsFlagType(E_SCLDMA_1_SNP_W,E_SCLDMA_FLAG_FRMIN)): ++ (u32Events&E_SCLIRQ_EVENT_SC1FRM)? !(_IsFlagType(E_SCLDMA_1_FRM_W,E_SCLDMA_FLAG_FRMIN)): 0; ++ if((u32Events & (E_SCLIRQ_EVENT_SC1)) && bSINGLE_SKIP) //ISP FIFO FULL ++ { ++ bDone = SINGLE_SKIP; ++ if((u32Events & (E_SCLIRQ_EVENT_SC1RE))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1))==(E_SCLIRQ_EVENT_SC1)) ++ { ++ bDone = FRM_POLLIN |SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1FRM))) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1SNP))) //frmend ++ { ++ bDone = SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1RESTART))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if(u32Events & E_SCLIRQ_EVENT_RESUME) ++ { ++ bDone = FRM_POLLIN; ++ } ++ else //timeout ++ { ++ bDone = FALSE; ++ } ++ return bDone; ++} ++MS_BOOL _Drv_SCLDMA_GetReadDoneEvent(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_BOOL bDone; ++ if( _Is_SingleMode(enClientType)) ++ { ++ MS_U16 u16IrqNum; ++ MS_U64 u64Flag, u64Flag_N; ++ ++ u16IrqNum = _Drv_SCLDMA_GetActiveIRQNum(enClientType); ++ ++ Drv_SCLIRQ_Get_Flag(u16IrqNum, &u64Flag); ++ Drv_SCLIRQ_Get_Flag(u16IrqNum+1, &u64Flag_N); ++ if(u64Flag && u64Flag_N ) ++ { ++ bDone = TRUE; ++ } ++ else ++ { ++ bDone = FALSE; ++ } ++ } ++ else if ( _Is_RingMode(enClientType)) ++ { ++ bDone = TRUE; ++ } ++ else if(_Is_SWRingMode(enClientType)) ++ { ++ bDone = TRUE; ++ } ++ else ++ { ++ bDone = FALSE; ++ } ++ return bDone; ++} ++MS_BOOL Drv_SCLDMA_GetDMADoneEvent(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_DONE_CONFIG *pCfg) ++{ ++ MS_BOOL bRet = 1; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ MS_U32 u32Time = 0; ++ MS_U32 u32Events = 0; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,pCfg->enRWMode); ++ if(enSCLDMA_ID ==E_SCLDMA_ID_PNL_R || enSCLDMA_ID ==E_SCLDMA_ID_3_R ) ++ { ++ _Drv_SCLDMA_GetReadDoneEvent(enClientType); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%s:: Client:%s bDone=%x @:%lu\n", ++ __FUNCTION__, PARSING_SCLDMA_ID(enSCLDMA_ID), pCfg->bDone,u32Time); ++ } ++ else if(enSCLDMA_ID ==E_SCLDMA_ID_3_W ) ++ { ++ u32Events = MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SC3EventID()); ++ pCfg->bDone = _Drv_SCLDMA_GetSC3DoneFlagAndClearSC3Event(u32Events); ++ ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,3), ++ "[DRVSCLDMA]%s:: Client:%s Event:%lx bDone=%x flag:%hhx@:%lu\n", ++ __FUNCTION__, PARSING_SCLDMA_CLIENT(enClientType),u32Events, pCfg->bDone, ++ gstScldmaInfo.bDmaflag[enClientType],u32Time); ++ } ++ else ++ { ++ if(enSCLDMA_ID ==E_SCLDMA_ID_1_W) ++ { ++ u32Events = _Drv_SCLDMA_GetEventById(E_SCLDMA_ID_1_W); ++ pCfg->bDone = _Drv_SCLDMA_GetSC1DoneFlag(u32Events); ++ } ++ else if(enSCLDMA_ID ==E_SCLDMA_ID_2_W) ++ { ++ u32Events = _Drv_SCLDMA_GetEventById(E_SCLDMA_ID_2_W); ++ pCfg->bDone = _Drv_SCLDMA_GetSC2DoneFlag(u32Events); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1),"[DRVSCLDMA]%s:: Client:%s Event:%lx bDone=%x\n", ++ __FUNCTION__, PARSING_SCLDMA_CLIENT(enClientType),u32Events, pCfg->bDone); ++ } ++ return bRet; ++} ++MS_BOOL _Drv_SCLDMA_GetLastTimePoint(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U8 u8LPoint = 0; ++ u8LPoint = _GetIdxType(enClientType,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ return u8LPoint; ++} ++MS_BOOL _Drv_SCLDMA_GetDMAWritePoint(EN_SCLDMA_CLIENT_TYPE enClientType, MS_U8 u8LPoint) ++{ ++ MS_U8 u8WPoint = 0; ++ if(_Is_DMAClientOn(enClientType) &&_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING)) ++ { ++ u8WPoint = 0x0F; ++ } ++ else if( _IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ u8WPoint =(u8LPoint==0) ? gstScldmaInfo.bMaxid[enClientType] : u8LPoint-1; ++ } ++ else ++ { ++ u8WPoint = u8LPoint; ++ } ++ return u8WPoint; ++} ++MS_BOOL _Drv_SCLDMA_GetAppReadPoint(EN_SCLDMA_CLIENT_TYPE enClientType ,MS_U8 u8AppInfo) ++{ ++ MS_U8 u8RPoint = 0; ++ if(_Is_DMAClientOn(enClientType) &&(_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING))) ++ { ++ u8RPoint = gstScldmaInfo.bMaxid[enClientType]; ++ } ++ else ++ { ++ u8RPoint = (u8AppInfo & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG) ? ++ (u8AppInfo &0x0F ) : (gstScldmaInfo.bDMAidx[enClientType]>>4)&E_SCLDMA_ACTIVE_BUFFER_SCL ; ++ } ++ return u8RPoint; ++} ++void _Drv_SCLDMA_DMAOffAtActiveTimeWhetherNeedReOpen(ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ if(stPointCfg->bRWequal&&(_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_DMAOFF))) ++ { ++ if(Drv_SCLDMA_SetISRHandlerDMAOff(stPointCfg->enClientType,1)) ++ { ++ _ReSetFlagType(stPointCfg->enClientType,(E_SCLDMA_FLAG_EVERDMAON|E_SCLDMA_FLAG_DMAOFF)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(stPointCfg->enClientType,1), ++ "[DRVSCLDMA] enClientType:%d ReOpen \n",stPointCfg->enClientType); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf( ++ "[DRVSCLDMA] enClientType:%d strong collisionR:%hhd\n",stPointCfg->enClientType,stPointCfg->u8RPoint )); ++ } ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++} ++void _Drv_SCLDMA_SetDMAOnWhenDMAOff ++ (EN_SCLDMA_ID_TYPE enSCLDMA_ID, EN_SCLDMA_CLIENT_TYPE enClientType, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ pCfg->stOnOff.bEn = 1; ++ Drv_SCLDMA_SetDMAClientOnOff(enSCLDMA_ID ,pCfg->stOnOff); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_EventID(), (enClientType==E_SCLDMA_1_FRM_W) ++ ? E_SCLIRQ_EVENT_SC1RESTART: E_SCLIRQ_EVENT_SC2RESTART); ++} ++MS_U8 _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOff(ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ MS_U8 u8ActiveBuffer; ++ if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && !stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL | E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ } ++ else if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint|E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ _ReSetFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON); ++ } ++ else ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ } ++ return u8ActiveBuffer; ++} ++MS_U8 _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOn(ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ MS_U8 u8ActiveBuffer; ++ if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && !stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL; ++ } ++ else if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint; ++ _ReSetFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON); ++ } ++ else ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint; ++ } ++ return u8ActiveBuffer; ++} ++ST_SCLDMA_POINT_CONFIG _Drv_SCLDMA_GetPointConfig(EN_SCLDMA_CLIENT_TYPE enClientType ,MS_U8 u8AppInfo) ++{ ++ ST_SCLDMA_POINT_CONFIG stPointCfg; ++ stPointCfg.u8LPoint = _Drv_SCLDMA_GetLastTimePoint(enClientType); ++ stPointCfg.u8WPoint = _Drv_SCLDMA_GetDMAWritePoint(enClientType, stPointCfg.u8LPoint); ++ stPointCfg.u8RPoint = _Drv_SCLDMA_GetAppReadPoint(enClientType,u8AppInfo); ++ stPointCfg.bRWequal = (stPointCfg.u8WPoint == stPointCfg.u8RPoint)? 1 : 0; ++ stPointCfg.bRPointChange = (u8AppInfo & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)? 1 : 0; ++ stPointCfg.enClientType = enClientType; ++ return stPointCfg; ++} ++void _Drv_SCLDMA_HandlerBufferWhenDMAOff ++ (EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_POINT_CONFIG *stPointCfg, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ if(_Is_DMACanReOpen(stPointCfg->bRWequal,stPointCfg->bRPointChange)) ++ { ++ _Drv_SCLDMA_SetDMAOnWhenDMAOff(enSCLDMA_ID,stPointCfg->enClientType,pCfg); ++ pCfg->u8ActiveBuffer = 0x0F ; ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOff(stPointCfg); ++ } ++} ++void _Drv_SCLDMA_HandlerBufferWhenDMAOn ++ (ST_SCLDMA_POINT_CONFIG *stPointCfg, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ _Drv_SCLDMA_DMAOffAtActiveTimeWhetherNeedReOpen(stPointCfg); ++ pCfg->u8ActiveBuffer = _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOn(stPointCfg); ++} ++MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdx(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ ST_SCLDMA_POINT_CONFIG stPointCfg; ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,pCfg->enRWMode); ++#if ENABLE_RING_DB ++ if(_Is_VsrcDoubleBufferNotOpen() && _Is_VsrcId(enSCLDMA_ID) && DoubleBufferStatus) ++ { ++ gVsrcDBnotOpen = 0; ++ _Drv_SCLDMA_SetDoubleBufferOn(E_SCLDMA_ID_1_W, SCLIRQ_SC1_SNPI_W_ACTIVE, E_SCLDMA_1_IMI_W); ++ } ++#endif ++ if(_Is_RingMode(enClientType)) ++ { ++ stPointCfg = _Drv_SCLDMA_GetPointConfig(enClientType,pCfg->u8ActiveBuffer); ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetIdxType(enClientType,(stPointCfg.u8RPoint<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if(_Is_DMAClientOn(enClientType)) ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOn(&stPointCfg,pCfg); ++ } ++ else ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOff(enSCLDMA_ID,&stPointCfg,pCfg); ++ } ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = 0xFF; ++ } ++ pCfg->u8ISPcount = gu8ISPcount; ++ pCfg->u32FRMDoneTime = gu32FRMDoneTime; ++ return 1; ++} ++void _Drv_SCLDMA_HandlerBufferWhenDMAOnWithoutDoublebuffer ++ (ST_SCLDMA_POINT_CONFIG *stPointCfg, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ pCfg->u8ActiveBuffer = _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOn(stPointCfg); ++} ++MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdxWithoutDoublebuffer ++ (EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ ST_SCLDMA_POINT_CONFIG stPointCfg; ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,pCfg->enRWMode); ++ if(_Is_RingMode(enClientType)) ++ { ++ stPointCfg = _Drv_SCLDMA_GetPointConfig(enClientType,pCfg->u8ActiveBuffer); ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetIdxType(enClientType,(stPointCfg.u8RPoint<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if(_Is_DMAClientOn(enClientType)) ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOnWithoutDoublebuffer(&stPointCfg,pCfg); ++ } ++ else ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOff(enSCLDMA_ID,&stPointCfg,pCfg); ++ } ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = 0xFF; ++ } ++ pCfg->u8ISPcount = gu8ISPcount; ++ pCfg->u32FRMDoneTime = gu32FRMDoneTime; ++ return 1; ++} ++void Drv_SCLDMA_SetForceCloseDMA(EN_SCLDMA_ID_TYPE enID,EN_SCLDMA_RW_MODE_TYPE enRWMode,MS_BOOL bEn) ++{ ++ EN_SCLDMA_CLIENT_TYPE client; ++ client = _Drv_SCLDMA_TransToClientType(enID ,enRWMode); ++ gbForceClose[client] = bEn; ++} ++ ++void Drv_SCLDMA_ResetTrigCountByClient(EN_SCLDMA_ID_TYPE enSCLDMA_ID,EN_SCLDMA_RW_MODE_TYPE enRWMode) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ MS_U8 u8ClientIdx; ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,enRWMode); ++ if(enClientType == E_SCLDMA_CLIENT_NUM) ++ { ++ for(u8ClientIdx=0; u8ClientIdxenRWMode); ++#if ENABLE_RING_DB ++ if(_Is_VsrcDoubleBufferNotOpen() && _Is_VsrcId(enSCLDMA_ID) && DoubleBufferStatus) ++ { ++ gVsrcDBnotOpen = 0; ++ _Drv_SCLDMA_SetDoubleBufferOn(E_SCLDMA_ID_1_W, SCLIRQ_SC1_SNPI_W_ACTIVE, E_SCLDMA_1_IMI_W); ++ } ++#endif ++ if(_Is_DMAClientOn(enClientType) &&_Is_RingMode(enClientType)) ++ { ++ //scl active id if E_SCLDMA_FLAG_EVERDMAON means OMX update R point not yet ++ u8LPoint = _GetIdxType(enClientType,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ if(_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING)) ++ { ++ u8WPoint = 0x0F; ++ } ++ else if( _IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ u8WPoint =(u8LPoint==0) ? gstScldmaInfo.bMaxid[enClientType] : u8LPoint-1; ++ } ++ else ++ { ++ u8WPoint = u8LPoint; ++ } ++ //OMX id ++ if((_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING))) ++ { ++ u8RPoint = gstScldmaInfo.bMaxid[enClientType]; ++ } ++ else ++ { ++ u8RPoint = (pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG) ? ++ (pCfg->u8ActiveBuffer &0x0F ) : (gstScldmaInfo.bDMAidx[enClientType]>>4)&E_SCLDMA_ACTIVE_BUFFER_SCL ; ++ } ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetIdxType(enClientType,(u8RPoint<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ if(u8WPoint == u8RPoint &&(_IsFlagType(enClientType,E_SCLDMA_FLAG_DMAOFF))) ++ { ++ if(Drv_SCLDMA_SetISRHandlerDMAOff(enClientType,1)) ++ { ++ _ReSetFlagType(enClientType,(E_SCLDMA_FLAG_EVERDMAON|E_SCLDMA_FLAG_DMAOFF)); ++ //DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d still ON/OFF R:%hhd\n",enClientType,u8RPoint )); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d strong collisionR:%hhd\n",enClientType,u8RPoint )); ++ } ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if((_IsFlagType(enClientType,E_SCLDMA_FLAG_EVERDMAON)) && !(pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ pCfg->u8ActiveBuffer = u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL; ++ } ++ else if((_IsFlagType(enClientType,E_SCLDMA_FLAG_EVERDMAON)) && (pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ pCfg->u8ActiveBuffer = u8WPoint; ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_EVERDMAON); ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = u8WPoint; ++ } ++ if(u8WPoint != 0xFF) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1),"[DRVSCLDMA]%d W_P:%hhd L_P:%hhd @:%lu\n", ++ enClientType,u8WPoint, u8LPoint,(MS_U32)MsOS_GetSystemTime()); ++ } ++ else if((_Is_DMAClientOff(enClientType) && _Is_RingMode(enClientType))) ++ { ++ //ring and trig off ++ //scl active id ++ u8LPoint = _GetIdxType(enClientType,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ if(_IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ u8WPoint = (u8LPoint == 0) ? gstScldmaInfo.bMaxid[enClientType] : u8LPoint-1; ++ } ++ else ++ { ++ u8WPoint = u8LPoint; ++ } ++ //OMX id ++ u8RPoint = (pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG) ? ++ (pCfg->u8ActiveBuffer &0x0F ) : (gstScldmaInfo.bDMAidx[enClientType]>>4)&E_SCLDMA_ACTIVE_BUFFER_SCL ; ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetIdxType(enClientType,(u8RPoint<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if((pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]OFF%d W_P:%hhd L_P:%hhd @:%lu\n", ++ enClientType,u8WPoint, u8LPoint,(MS_U32)MsOS_GetSystemTime()); ++ } ++ if((u8RPoint == u8WPoint)&&(pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ pCfg->stOnOff.bEn = 1; ++ Drv_SCLDMA_SetDMAClientOnOff(enSCLDMA_ID ,pCfg->stOnOff); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_EventID(), (enClientType==E_SCLDMA_1_FRM_W) ++ ? E_SCLIRQ_EVENT_SC1RESTART: E_SCLIRQ_EVENT_SC2RESTART); ++ pCfg->u8ActiveBuffer = 0x0F ; ++ } ++ else ++ { ++ if((_IsFlagType(enClientType,E_SCLDMA_FLAG_EVERDMAON)) && !(pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ pCfg->u8ActiveBuffer = u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL | E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ } ++ else if((_IsFlagType(enClientType,E_SCLDMA_FLAG_EVERDMAON)) && (pCfg->u8ActiveBuffer & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ pCfg->u8ActiveBuffer = u8WPoint|E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_EVERDMAON); ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ } ++ } ++ bRet = TRUE; ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = 0xFF; ++ bRet = FALSE; ++ } ++ pCfg->u8ISPcount = gu8ISPcount; ++ pCfg->u32FRMDoneTime = gu32FRMDoneTime; ++ return 1; ++} ++void _Drv_SCLDMA_SetDynamicClkOnOff(MS_BOOL bEn ,EN_SCLDMA_CLIENT_TYPE enClientType,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ MS_BOOL bOnOff = 0; ++ MS_BOOL bCheckClient = 0; ++ MS_U32 enCllientIdx; ++ EN_SCLDMA_CLIENT_TYPE enPreCondition; ++ EN_SCLDMA_CLIENT_TYPE enLasCondition; ++ enPreCondition = (enClientType < E_SCLDMA_3_FRM_R) ? 0 : E_SCLDMA_3_FRM_R; ++ enLasCondition = (enClientType < E_SCLDMA_3_FRM_R) ? E_SCLDMA_3_FRM_R : E_SCLDMA_4_FRM_R; ++ for(enCllientIdx = enPreCondition;enCllientIdx= E_SCLDMA_1_FRM_W && enClientType <= E_SCLDMA_2_IMI_W) || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ while(MsOS_Timer_DiffTimeFromNow(u32Time) < 20) ++ { ++ enIrqModeMd = _Drv_SCLDMA_Irq_Get_Mode(enClientType); ++ if( (enIrqModeMd & E_SCLDMA_IRQ_MODE_DONE) == E_SCLDMA_IRQ_MODE_DONE ) ++ { ++ bSignleDone = 1; ++ break; ++ } ++ } ++ } ++ else ++ { ++ while(MsOS_Timer_DiffTimeFromNow(u32Time) < 20) ++ { ++ if( (_Drv_SCLDMA_Irq_Get_Mode(enClientType) & E_SCLDMA_IRQ_MODE_DONE) == E_SCLDMA_IRQ_MODE_ACTIVE_N ) ++ { ++ bSignleDone = 1; ++ break; ++ } ++ } ++ } ++ ++ if(bSignleDone == FALSE) ++ { ++ DRV_SCLDMA_DBG(printf("[DRVSCLDMA]%s SINGLE mode, %s acitve\n", ++ __FUNCTION__, PARSING_SCLDMA_CLIENT(enClientType))); ++ bRWDone = bRWDone^(1< ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef DRV_SCLDMA_H ++#define DRV_SCLDMA_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_SCLDMA_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void isp_enable_input(u32 enable); ++INTERFACE MS_BOOL Drv_SCLDMA_Init(ST_SCLDMA_INIT_CONFIG *pInitCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_SetDMAClientConfig(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_RW_CONFIG stCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_SetDMAClientOnOff(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ONOFF_CONFIG stCfg ); ++INTERFACE EN_SCLDMA_DB_STATUS_TYPE Drv_SCLDMA_GetVsrcDoubleBufferStatus(MS_U32 u32Event); ++INTERFACE void Drv_SCLDMA_DoubleBufferOnOffById(MS_BOOL bEn, EN_SCLDMA_ID_TYPE enSCLDMA_ID); ++INTERFACE MS_BOOL Drv_SCLDMA_Set_VsConfig(EN_SCLDMA_VS_ID_TYPE enVsID, ST_SCLDMA_VS_CONFIG stCfg); ++INTERFACE void Drv_SCLDMA_Release(EN_SCLDMA_ID_TYPE enSCLDMA_ID,ST_SCLDMA_CLK_CONFIG *stclk); ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMADoneEvent(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_DONE_CONFIG *pCfg); ++INTERFACE void Drv_SCLDMA_PeekBufferQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg); ++INTERFACE void Drv_SCLDMA_BufferDeQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg); ++INTERFACE unsigned char Drv_SCLDMA_GetActiveBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE unsigned char Drv_SCLDMA_GetDoneBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE unsigned char Drv_SCLDMA_GetNextBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE void Drv_SCLDMA_SetFrameResolution(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE unsigned char Drv_SCLDMA_BufferEnQueue(EN_SCLDMA_CLIENT_TYPE enClientType,ST_SCLDMA_FRAME_BUFFER_CONFIG stTarget); ++INTERFACE void Drv_SCLDMA_ChangeBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE MS_BOOL Drv_SCLDMA_MakeSureNextActiveId(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE void Drv_SCLDMA_EnableBufferAccess(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pCfg); ++ ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMABufferActiveIdx(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdx(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdxWithoutDoublebuffer(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg); ++INTERFACE void Drv_SCLDMA_SetThreadOnOffFlag(MS_BOOL bEn,ST_SCLDMA_THREAD_CONFIG *stthcfg); ++INTERFACE ST_SCLDMA_ATTR_TYPE Drv_SCLDMA_GetDMAInformationByClient(EN_SCLDMA_ID_TYPE enSCLDMA_ID,EN_SCLDMA_RW_MODE_TYPE enRWMode); ++INTERFACE MS_BOOL Drv_SCLDMA_SetISRHandlerDMAOff(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_ResetTrigCountByClient(EN_SCLDMA_ID_TYPE enSCLDMA_ID,EN_SCLDMA_RW_MODE_TYPE enRWMode); ++INTERFACE void Drv_SCLDMA_SetForceCloseDMA(EN_SCLDMA_ID_TYPE enID,EN_SCLDMA_RW_MODE_TYPE enRWMode,MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_Sys_Init(MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_ClkClose(ST_SCLDMA_CLK_CONFIG* stclk); ++INTERFACE MS_BOOL Drv_SCLDMA_Resume(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_Suspend(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE wait_queue_head_t * Drv_SCLDMA_GetWaitQueueHead(EN_SCLDMA_ID_TYPE enID); ++INTERFACE MS_S32* Drv_SCLDMA_GetDMAandIRQCommonMutex(void); ++INTERFACE void Drv_SCLDMA_SetISPFrameCount(void); ++INTERFACE void Drv_SCLDMA_SetSclFrameDoneTime(MS_U32 u32FRMDoneTime); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/scldma/drvscldma_st.h b/drivers/mstar/scl/infinity/src/mxlib/drv/scldma/drvscldma_st.h +new file mode 100644 +index 00000000..600d2ff3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/scldma/drvscldma_st.h +@@ -0,0 +1,449 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef DRV_SCLDMA_ST_H ++#define DRV_SCLDMA_ST_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// DEFINE ++//------------------------------------------------------------------------------------------------- ++#define SCLDMA_DBG_Thread 0 ++#define DoubleBufferDefaultSet 0 // 0 close 1 open ++#define DoubleBufferStatus gbDBStatus ++#define ENABLE_RING_DB 1 ++#define SCLDMA_IRQ_EN 0 ++#define ENABLE_ACTIVEID_ISR 1 ++#define SCLDMA_BUFFER_QUEUE_OFFSET sizeof(ST_SCLDMA_FRAME_BUFFER_CONFIG) ++#define SCLDMA_IRQ_EVENT_ID_MSK 0xFF000000 ++#define SCLDMA_IRQ_EVENT_CLIENT_MSK 0x000000FF ++#define SCLDMA_IRQ_EVENT_CLEAR_IRQNUM_MSK 0x0000FF00 ++#define SCLDMA_IRQ_EVENT_CLEAR_MODE_MSK 0x00FF0000 ++ ++#define GET_SCLDMA_IRQ_EVENT_CLIENT(x) (x & SCLDMA_IRQ_EVENT_CLIENT_MSK) ++#define GET_SCLDMA_IRQ_EVENT_CLEAR_IRQNUM(x) ((x & SCLDMA_IRQ_EVENT_CLEAR_IRQNUM_MSK) >> 8) ++#define GET_SCLDMA_IRQ_EVENT_CLEAR_MODE(x) ((x & SCLDMA_IRQ_EVENT_CLEAR_MODE_MSK) >> 16) ++ ++#define SET_SCLDMA_IRQ_EVENT_PENDING(client) (E_SCLDMA_IRQ_EVENT_PENDING | \ ++ (client & 0x000000FF)) ++ ++#define SET_SCLDMA_IRQ_EVENT_CLEAR(client, mode, irqnum) (E_SCLDMA_IRQ_EVENT_CLEAR | \ ++ (client & 0xFF) | \ ++ ((irqnum & 0xFF) << 8) | \ ++ ((mode & 0xFF)<<16)) ++ ++//------------------------------------------------------------------------------------------------- ++// ENUM ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_SCLDMA_ID_1_W, ++ E_SCLDMA_ID_2_W, ++ E_SCLDMA_ID_3_W, ++ E_SCLDMA_ID_3_R, ++ E_SCLDMA_ID_PNL_R, ++ E_SCLDMA_ID_MAX, //scldma ID type,I1 has 1_W,2_W,3_R,3_R,PNL_R ++}EN_SCLDMA_ID_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_FRM_W, ++ E_SCLDMA_SNP_W, ++ E_SCLDMA_IMI_W, ++ E_SCLDMA_FRM_R, ++ E_SCLDMA_DBG_R, ++ E_SCLDMA_IMI_R, ++ E_SCLDMA_RW_NUM, //scldma rwmode, I1 has FRM,SNP,IMI RW ++}EN_SCLDMA_RW_MODE_TYPE; ++ ++typedef enum ++{ ++ EN_SCLDMA_DB_STATUS_NEED_OFF, ++ EN_SCLDMA_DB_STATUS_NEED_ON, ++ EN_SCLDMA_DB_STATUS_KEEP, ++ EN_SCLDMA_DB_STATUS_NUM, //double buffer switcher status, 3 choise ++}EN_SCLDMA_DB_STATUS_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_1_FRM_W = 0, ++ E_SCLDMA_1_SNP_W = 1, ++ E_SCLDMA_1_IMI_W = 2, ++ E_SCLDMA_2_FRM_W = 3, ++ E_SCLDMA_2_IMI_W = 4, ++ E_SCLDMA_3_FRM_R = 5, ++ E_SCLDMA_3_FRM_W = 6, ++ E_SCLDMA_4_FRM_R = 7, ++ E_SCLDMA_3_IMI_R = 8, ++ E_SCLDMA_CLIENT_NUM, //scldma client ,I1 has dma_1:3 cli dma_2 :2cli dma_3:In/Out debug:pnl &dma_3_IMIR ++}EN_SCLDMA_CLIENT_TYPE; ++ ++ ++typedef enum ++{ ++ E_SCLDMA_BUF_MD_RING, ++ E_SCLDMA_BUF_MD_SINGLE, ++ E_SCLDMA_BUF_MD_SWRING, ++ E_SCLDMA_BUF_MD_NUM, //scldma DMA write mode,I1 has 2 type: Ring(HW),Single(HW+SW) ++}EN_SCLDMA_BUFFER_MODE_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_COLOR_YUV422, ++ E_SCLDMA_COLOR_YUV420, ++ E_SCLDMA_COLOR_NUM, //I1 dma has 2 color type 422,420 ++}EN_SCLDMA_COLOR_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_VS_ID_SC = 0, ++ E_SCLDMA_VS_ID_AFF = 1, ++ E_SCLDMA_VS_ID_LDC = 2, ++ E_SCLDMA_VS_ID_SC3 = 3, ++ E_SCLDMA_VS_ID_DISP = 4, ++ E_SCLDMA_VS_ID_NUM = 5, //scl handle vsync type,I1 can handle in AFF,LDC,SC3,DISP, suggest sc1 use HW mode ,sc3 use regen mode ++}EN_SCLDMA_VS_ID_TYPE; ++ ++ ++ ++typedef enum ++{ ++ E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC = 0, ++ E_SCLDMA_VS_TRIG_MODE_HW_DELAY = 1, ++ E_SCLDMA_VS_TRIG_MODE_SWTRIGGER = 2, ++ E_SCLDMA_VS_TRIG_MODE_DISP_FM_END = 3, ++ E_SCLDMA_VS_TRIG_MODE_NUM = 4, ++}EN_SCLDMA_VS_TRIG_MODE_TYPE; ++ ++ ++typedef enum ++{ ++ E_SCLDMA_REF_VS_REF_MODE_FALLING = 0, ++ E_SCLDMA_REF_VS_REF_MODE_RASING = 1, ++ E_SCLDMA_REF_VS_REF_MODE_NUM = 2, ++}EN_SCLDMA_REGEN_VS_REF_MODE_TYPE; ++ ++ ++typedef enum ++{ ++ E_SCLDMA_IRQ_EVENT_TIMER = 0x01000000, ++ E_SCLDMA_IRQ_EVENT_PENDING = 0x02000000, ++ E_SCLDMA_IRQ_EVENT_CLEAR = 0x03000000, ++ E_SCLDMA_IRQ_EVENT_ALL = 0x0FFFFFFF, ++}EN_SCLDMA_IRQ_EVENT_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_IRQ_MODE_PENDING = 0x00, ++ E_SCLDMA_IRQ_MODE_ACTIVE = 0x01, ++ E_SCLDMA_IRQ_MODE_ACTIVE_N = 0x02, ++ E_SCLDMA_IRQ_MODE_SIDONE = 0x03, ++ E_SCLDMA_IRQ_MODE_END = 0x04, ++ E_SCLDMA_IRQ_MODE_DONE = 0x06, ++ E_SCLDMA_IRQ_MODE_ALL = 0x07, ++}EN_SCLDMA_IRQ_MODE_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_ACTIVE_BUFFER_OMX = 0xF0, // OMX buffer status ,driver reserve. ++ E_SCLDMA_ACTIVE_BUFFER_SCL = 0x03, // SCL buffer status, save active/done buffer idx ++ E_SCLDMA_ACTIVE_BUFFER_OFF = 0x04, // already not use ++ E_SCLDMA_ACTIVE_BUFFER_ACT = 0x08, // already not use ++ E_SCLDMA_ACTIVE_BUFFER_SCLANDFLAG = 0x0F, // like E_SCLDMA_ACTIVE_BUFFER_SCL ++ E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG = 0x10, // it's represent OMX is update empty buffer to buffer ++ E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG = 0x20, // it's represent dma turn off and driver update to OMX ++ E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL = 0x40, // it's represent dma already done one buffer, but OMX isn't to receive. ++}EN_SCLDMA_ACTIVE_BUFFER_TYPE; ++ ++//bit0 next time off , bit 1 blanking ,bit 2 DMAonoff, bit3 no DMA on ,bit4 ever DMA on ,but already off or open again ++typedef enum ++{ ++ E_SCLDMA_FLAG_NEXT_ON = 0x01, // for non double buffer mode, if active wait for blanking ++ E_SCLDMA_FLAG_BLANKING = 0x02, // if reset dma,active id is temporarily state, need to handle until first frame done. ++ E_SCLDMA_FLAG_DMATRIGON = 0x03, // already not use ++ E_SCLDMA_FLAG_DMAOFF = 0x04, // ref E_SCLDMA_ACTIVE_BUFFER_OFF,dma off ++ E_SCLDMA_FLAG_ACTIVE = 0x08, // ref E_SCLDMA_ACTIVE_BUFFER_ACT,dma act ++ E_SCLDMA_FLAG_EVERDMAON = 0x10, // like E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL ++ E_SCLDMA_FLAG_FRMIN = 0x20, // this frame is integrate. ++ E_SCLDMA_FLAG_FRMDONE = 0x40, // dma done.(idle) ++}EN_SCLDMA_FLAG_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_ISR_LOG_ISPOFF = 0x1, ++ E_SCLDMA_ISR_LOG_SNPONLY = 0x2, ++ E_SCLDMA_ISR_LOG_SNPISR = 0x3, ++ E_SCLDMA_ISR_LOG_ISPON = 0x4, ++ E_SCLDMA_ISR_LOG_SC1ON = 0x5, ++ E_SCLDMA_ISR_LOG_SC1OFF = 0x6, ++ E_SCLDMA_ISR_LOG_SC2ON = 0x7, ++ E_SCLDMA_ISR_LOG_SC2OFF = 0x8, ++ E_SCLDMA_ISR_LOG_SC1A = 0x9, ++ E_SCLDMA_ISR_LOG_SC1N = 0xA, ++ E_SCLDMA_ISR_LOG_SC2A = 0xB, ++ E_SCLDMA_ISR_LOG_SC2N = 0xC, ++ E_SCLDMA_ISR_LOG_FRMEND = 0xD,//isr log status ++}EN_SCLDMA_ISR_LOG_TYPE; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ MS_U8 u8RPoint;//R-OMX ++ MS_U8 u8WPoint;//W-SCL ++ MS_U8 u8LPoint;// L-last time scl ++ MS_BOOL bRWequal; ++ MS_BOOL bRPointChange; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++}ST_SCLDMA_POINT_CONFIG; ++typedef struct ++{ ++ MS_BOOL flag; ++ MS_S32 s32Taskid; ++ MSOS_ST_TASKSTRUCT sttask; ++}ST_SCLDMA_THREAD_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32RIUBase; ++}ST_SCLDMA_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32IRQNum; ++}ST_SCLDMA_SUSPEND_RESUME_CONFIG; ++ ++typedef struct ++{ ++ MS_U8 btsBase_0 : 1; ++ MS_U8 btsBase_1 : 1; ++ MS_U8 btsBase_2 : 1; ++ MS_U8 btsBase_3 : 1; ++ MS_U8 btsReserved : 4; ++}ST_SCLDMA_RW_FLGA_TYPE; ++ ++typedef struct ++{ ++ union ++ { ++ MS_U8 u8Flag; ++ ST_SCLDMA_RW_FLGA_TYPE bvFlag; ++ }; ++ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ EN_SCLDMA_COLOR_TYPE enColor; ++ EN_SCLDMA_BUFFER_MODE_TYPE enBuffMode; ++ MS_U32 u32Base_Y[4]; ++ MS_U32 u32Base_C[4]; ++ MS_U8 u8MaxIdx; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++}ST_SCLDMA_RW_CONFIG; ++ ++typedef struct ++{ ++ MSOS_ST_CLK* idclk; ++ MSOS_ST_CLK* fclk1; ++ MSOS_ST_CLK* fclk2; ++ MSOS_ST_CLK* odclk; ++}ST_SCLDMA_CLK_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ ST_SCLDMA_CLK_CONFIG *stclk; ++}ST_SCLDMA_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigMd; ++ EN_SCLDMA_REGEN_VS_REF_MODE_TYPE enVsRefMd; ++ MS_U16 u16Vs_Width; ++ MS_U16 u16Vs_St; ++}ST_SCLDMA_VS_CONFIG; ++ ++ ++typedef struct ++{ ++ MS_BOOL bDone; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++}ST_SCLDMA_DONE_CONFIG; ++ ++typedef struct ++{ ++ MS_U8 u8ActiveBuffer; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ ST_SCLDMA_ONOFF_CONFIG stOnOff; ++ MS_U8 u8ISPcount; ++ MS_U32 u32FRMDoneTime; ++}ST_SCLDMA_ACTIVE_BUFFER_CONFIG; ++typedef struct ++{ ++ unsigned char u8FrameAddrIdx; ///< ID of Frame address ++ unsigned long u32FrameAddr; ///< Frame Address ++ unsigned char u8ISPcount; ///< ISP counter ++ unsigned short u16FrameWidth; ///< Frame Width ++ unsigned short u16FrameHeight; ///< Frame Height ++ unsigned long long u64FRMDoneTime; ///< Time of FRMDone ++}__attribute__ ((__packed__))ST_SCLDMA_FRAME_BUFFER_CONFIG; ++ ++typedef struct ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bUsed; ++ unsigned char bFull; ++ unsigned char u8Bufferflag; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstHead; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstTail; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstWrite; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstWriteAlready; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstRead; ++ unsigned char u8InQueueCount; ++ unsigned char u8NextActiveId; ++ unsigned char u8AccessId; ++}ST_SCLDMA_BUFFER_QUEUE_CONFIG; ++ ++typedef struct ++{ ++ ST_SCLDMA_VS_CONFIG stVsCfg[E_SCLDMA_VS_ID_NUM]; ++ EN_SCLDMA_BUFFER_MODE_TYPE enBuffMode[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bDMAOnOff[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bDMAidx[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bMaxid[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bDmaflag[E_SCLDMA_CLIENT_NUM];//bit0 next time off , bit 1 blanking ,bit 2 DMAonoff, bit3 no DMA on ++ MS_U64 u64mask; ++ EN_SCLDMA_COLOR_TYPE enColor[E_SCLDMA_CLIENT_NUM]; ++ MS_U32 u32Base_Y[E_SCLDMA_CLIENT_NUM][4]; ++ MS_U32 u32Base_C[E_SCLDMA_CLIENT_NUM][4]; ++ MS_BOOL u16FrameWidth[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL u16FrameHeight[E_SCLDMA_CLIENT_NUM]; ++#if SCLDMA_IRQ_EN ++ MS_S32 s32IrqTaskid; ++ MS_S32 s32IrqEventId; ++ MS_S32 s32IrqTimerId; ++#endif ++}ST_SCLDMA_INFO_TYPE; ++typedef struct ++{ ++ MS_U16 u16DMAcount; ++ MS_U16 u16DMAH; ++ MS_U16 u16DMAV; ++ MS_U32 u32Trigcount; ++ EN_SCLDMA_COLOR_TYPE enColor; ++ EN_SCLDMA_BUFFER_MODE_TYPE enBuffMode; ++ MS_U32 u32Base_Y[4]; ++ MS_U32 u32Base_C[4]; ++ MS_U8 u8MaxIdx; ++ MS_U8 bDMAEn; ++}ST_SCLDMA_ATTR_TYPE; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// extern Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// ScldmaInfo ++/// use in Drvscldma and Drvsclirq ++/// record all DMA client status ++//////////////// ++extern ST_SCLDMA_INFO_TYPE gstScldmaInfo; ++extern MS_BOOL gbDBStatus; ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/sclirq/drvsclirq.c b/drivers/mstar/scl/infinity/src/mxlib/drv/sclirq/drvsclirq.c +new file mode 100644 +index 00000000..0affacd6 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/sclirq/drvsclirq.c +@@ -0,0 +1,1266 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_SCLIRQ_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "irqs.h" ++#include ++ ++#include "drvsclirq.h" ++#include "mdrv_scl_dbg.h" ++#include "drvsclirq_st.h" ++#include "drvscldma_st.h" ++#include "halscldma.h" ++#include "drvscldma.h" ++#include "regCMDQ.h" ++#include "drvCMDQ.h" ++#include "halsclirq.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_SCLIRQ_DBG(x) ++#define DRV_SCLIRQ_DBG_H(x) ++#define DRV_SCLIRQ_ERR(x) x ++#define freerunID 5 ++#define ENABLE_ISR 0 ++#define ENABLE_ACTIVEID_ISR 1 ++#define ENABLE_CMDQ_ISR 1 ++#define _Is_SCLDMA_RingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_RING) ++#define _Is_SCLDMA_SingleMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SINGLE) ++#define _Is_SCLDMA_SWRingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SWRING) ++#define _IsFrmIN() (gbFRMInFlag & (E_SCLIRQ_FRM_IN_COUNT_NOW << SCL_DELAYFRAME_FROM_ISP)) ++#define _IsFrmIN_Now() (gbFRMInFlag & (E_SCLIRQ_FRM_IN_COUNT_NOW )) ++#define DRV_SCLIRQ_MUTEX_LOCK_ISR() MsOS_ObtainMutex_IRQ(*_pSCLIRQ_SCLDMA_Mutex) ++#define DRV_SCLIRQ_MUTEX_UNLOCK_ISR() MsOS_ReleaseMutex_IRQ(*_pSCLIRQ_SCLDMA_Mutex) ++#define DRV_SCLIRQ_MUTEX_LOCK() MsOS_ObtainMutex(_SCLIRQ_Mutex , MSOS_WAIT_FOREVER) ++#define DRV_SCLIRQ_MUTEX_UNLOCK() MsOS_ReleaseMutex(_SCLIRQ_Mutex , MSOS_WAIT_FOREVER) ++//------------------------------------------------------------------------------------------------- ++// structure ++//------------------------------------------------------------------------------------------------- ++#if (ENABLE_ISR) ++typedef struct ++{ ++ MS_U64 u64IRQ; ++ MS_U64 u64Flag; ++ MS_U8 u8Count[E_SCLDMA_CLIENT_NUM]; ++}ST_SCLIRQ_IFNO_TYPE; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// _SCLIRQ_Mutex ++/// use in sclirq mutex,not include isr ++//////////////// ++MS_S32 _SCLIRQ_Mutex = -1; ++ ++///////////////// ++/// _pSCLIRQ_SCLDMA_Mutex ++/// scldma and sclirq mutex, include isr, send form scldma ++//////////////// ++MS_S32* _pSCLIRQ_SCLDMA_Mutex = NULL; ++ ++///////////////// ++/// gsclirqstate ++/// record irq state and set event as frame done ++//////////////// ++SCLIRQTXEvent gsclirqstate; ++ ++///////////////// ++/// gscl3irqstate ++/// record irq state and set event as frame done ++//////////////// ++SCLIRQSC3Event gscl3irqstate; ++ ++///////////////// ++/// _bSCLIRQ_Suspend ++/// record Suspend ++//////////////// ++MS_BOOL _bSCLIRQ_Suspend = 0; ++ ++///////////////// ++/// gu32IRQNUM ++/// record IRQ number to exit ++//////////////// ++MS_U32 gu32IRQNUM; ++MS_U32 gu32CMDQIRQNUM; ++///////////////// ++/// _s32FRMENDEventId ++/// the frame done wait queue ID ++//////////////// ++MS_S32 _s32FRMENDEventId; ++ ++///////////////// ++/// _s32SYNCEventId ++/// the fclk sync wait queue ID ++//////////////// ++MS_S32 _s32SYNCEventId; ++ ++///////////////// ++/// _s32SC3EventId ++/// the Sc3 wait queue ID ++//////////////// ++MS_S32 _s32SC3EventId; ++ ++///////////////// ++/// gbFRMInFlag ++/// use in Drvhvsp and Drvsclirq, and pass to Drvscldma ++/// if pre-crop (ISP) is receive full count ,ISR will set this TRUE; ++//////////////// ++MS_BOOL gbFRMInFlag; ++ ++///////////////// ++/// gbPtgenMode ++/// use in Drvscldma,Drvhvsp and Drvsclirq ++/// if True ,is debug ptgen mode. interrupt FRM_IN is inefficacy,so need to ignore. ++//////////////// ++unsigned char gbPtgenMode; ++ ++///////////////// ++/// gstThreadCfg ++/// IST thread ++//////////////// ++ST_SCLDMA_THREAD_CONFIG gstThreadCfg; ++ ++///////////////// ++/// gstSc3ThreadCfg ++/// SC3 IST thread ++//////////////// ++ST_SCLDMA_THREAD_CONFIG gstSc3ThreadCfg; ++ ++///////////////// ++/// gbMonitorCropMode ++/// it use by device attribute to judge checking type ++//////////////// ++unsigned char gbMonitorCropMode; ++///////////////// ++/// gbEachDMAEnable ++/// record frame status ++//////////////// ++static MS_BOOL gbEachDMAEnable; ++MS_BOOL gbInBlanking; ++ ++#if (ENABLE_ISR) ++ST_SCLIRQ_IFNO_TYPE gstSCLIrqInfo; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++#if (ENABLE_CMDQ_ISR) ++irqreturn_t _Drv_SCLIRQ_CMDQ_isr(int eIntNum, void* dev_id) ++{ ++ MS_U32 u32IrqFlag; ++ MS_U32 u32Time; ++ u32IrqFlag = Drv_CMDQ_GetFinalIrq(EN_CMDQ_TYPE_IP0); ++ Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_TYPE_IP0,0xFFFF); ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ if(u32IrqFlag & CMDQ_IRQ_STATE_TRIG) ++ { ++ MsOS_ClearEvent(_s32SYNCEventId,E_SCLIRQ_EVENT_CMDQ); ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CMDQGOING); ++ } ++ if(u32IrqFlag & CMDQ_IRQ_STATE_DONE) ++ { ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CMDQDONE); ++ Drv_CMDQ_SetRPoint(EN_CMDQ_TYPE_IP0); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISR, "[CMDQ]u32IrqFlag:%lx %lu\n",u32IrqFlag,u32Time); ++ return IRQ_HANDLED; ++} ++#endif ++void _Drv_SCLIRQ_SclFrameEndConnectToISP(void) ++{ ++ scl_ve_isr(); ++} ++#if ENABLE_ISR ++irqreturn_t _Drv_SCLIRQ_isr(int eIntNum, void* dev_id) ++{ ++ MS_U64 u64Flag = Hal_SCLIRQ_Get_Flag(0xFFFFFFFFFF); ++ ++ Hal_SCLIRQ_Set_Clear(u64Flag, 1); ++ ++ Hal_SCLIRQ_Set_Clear(u64Flag, 0); ++ ++ return IRQ_HANDLED; ++} ++ ++#elif ENABLE_ACTIVEID_ISR ++SCLIRQTXEvent _Drv_SCLIRQ_GetISTEventFlag(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ switch(enClient) ++ { ++ case E_SCLDMA_1_FRM_W: ++ return E_SCLIRQ_EVENT_ISTSC1FRM; ++ case E_SCLDMA_1_SNP_W: ++ return E_SCLIRQ_EVENT_ISTSC1SNP; ++ case E_SCLDMA_2_FRM_W: ++ return E_SCLIRQ_EVENT_ISTSC2FRM; ++ default : ++ return 0; ++ } ++} ++void _Drv_SCLIRQ_SetIsBlankingRegion(MS_BOOL bBk) ++{ ++ gbInBlanking = bBk; ++} ++MS_BOOL Drv_SCLIRQ_GetIsBlankingRegion(void) ++{ ++ return gbInBlanking; ++} ++static void Drv_SCLIRQ_RingMode_Active(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U8 u8RPoint = 0; ++ MS_U32 u32Time; ++ MS_U16 u16RealIdx; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ u8RPoint = (_GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_OMX))>>4; ++ if(!_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ u16RealIdx = Hal_SCLDMA_Get_RW_Idx(enClient); ++ } ++ else ++ { ++ u16RealIdx = _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ } ++ Drv_SCLDMA_SetFrameResolution(enClient); ++ if(u8RPoint==u16RealIdx && !_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING))//5 is debug freerun ++ { ++ //trig off ++ if(u8RPoint != freerunID ) ++ { ++ Drv_SCLDMA_SetISRHandlerDMAOff(enClient,0); ++ _SetFlagType(enClient,E_SCLDMA_FLAG_EVERDMAON); ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ _SetFlagType(enClient,(E_SCLDMA_FLAG_DMAOFF|E_SCLDMA_FLAG_ACTIVE)); ++ } ++ else ++ { ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_DMAOFF)); ++ } ++ } ++ else ++ { ++ _SetANDGetIdxType(enClient,u16RealIdx,E_SCLDMA_ACTIVE_BUFFER_OMX); ++ _SetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,0), ++ "[DRVSCLDMA]%d ISR R_P=%hhx RealIdx=%hx flag:%hhd @:%lu\n" ++ ,enClient,u8RPoint,u16RealIdx,gstScldmaInfo.bDmaflag[enClient],u32Time); ++} ++static void Drv_SCLIRQ_RingMode_Active_N(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_ACTIVE); ++ if(_IsFlagType(enclient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ gstScldmaInfo.bDMAOnOff[enclient] = 0; ++ } ++ if(_IsFlagType(enclient,E_SCLDMA_FLAG_BLANKING)) ++ { ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_BLANKING); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enclient,1), "[DRVSCLDMA]%d ISR actN flag:%hhd idx:%hhd @:%lu\n" ++ ,enclient,gstScldmaInfo.bDmaflag[enclient],gstScldmaInfo.bDMAidx[enclient],((MS_U32)MsOS_GetSystemTime())); ++ //printf("ACTIVE_N:%lu\n",u32Time); ++} ++static void Drv_SCLIRQ_RingMode_ActiveWithoutDoublebuffer(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U8 u8RPoint = 0; ++ MS_U32 u32Time; ++ MS_U16 u16RealIdx; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ u8RPoint = (_GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_OMX))>>4; ++ if(!_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ u16RealIdx = Hal_SCLDMA_Get_RW_Idx(enClient); ++ } ++ else ++ { ++ u16RealIdx = _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ } ++ Drv_SCLDMA_SetFrameResolution(enClient); ++ _SetANDGetIdxType(enClient,u16RealIdx,E_SCLDMA_ACTIVE_BUFFER_OMX); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,0), ++ "[DRVSCLDMA]%d wodb ISR R_P=%hhx RealIdx=%hx flag:%hhd @:%lu\n" ++ ,enClient,u8RPoint,u16RealIdx,gstScldmaInfo.bDmaflag[enClient],u32Time); ++} ++static void Drv_SCLIRQ_RingMode_Active_NWithoutDoublebuffer(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U8 u8RPoint = 0; ++ MS_U16 u16RealIdx; ++ u8RPoint = (_GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_OMX))>>4; ++ u16RealIdx = _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ if(u8RPoint==u16RealIdx && !_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING))//5 is debug freerun ++ { ++ //trig off ++ if(u8RPoint != freerunID ) ++ { ++ Drv_SCLDMA_SetISRHandlerDMAOff(enClient,0); ++ _SetANDGetFlagType ++ (enClient,E_SCLDMA_FLAG_FRMDONE|E_SCLDMA_FLAG_EVERDMAON|E_SCLDMA_FLAG_DMAOFF,(~E_SCLDMA_FLAG_ACTIVE)); ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ } ++ else ++ { ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_FRMDONE,(~(E_SCLDMA_FLAG_DMAOFF|E_SCLDMA_FLAG_ACTIVE))); ++ } ++ } ++ else ++ { ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ } ++ if(_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ gstScldmaInfo.bDMAOnOff[enClient] = 0; ++ } ++ if(_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING)) ++ { ++ _ReSetFlagType(enClient,E_SCLDMA_FLAG_BLANKING); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,1), "[DRVSCLDMA]%d ISR actN wodb flag:%hhd idx:%hhd @:%lu\n" ++ ,enClient,gstScldmaInfo.bDmaflag[enClient],gstScldmaInfo.bDMAidx[enClient],((MS_U32)MsOS_GetSystemTime())); ++ //printf("ACTIVE_N:%lu\n",u32Time); ++} ++static void Drv_SCLIRQ_SWRingMode_Active(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ MS_U32 u32Time; ++ MS_U16 u16RealIdx; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ if(_IsFlagType(enclient,E_SCLDMA_FLAG_BLANKING)) ++ { ++ u16RealIdx = 0; ++ } ++ else ++ { ++ u16RealIdx = Drv_SCLDMA_GetActiveBufferIdx(enclient); ++ } ++ _SetANDGetIdxType(enclient,u16RealIdx,E_SCLDMA_ACTIVE_BUFFER_OMX); ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enclient,0), "[DRVSCLDMA]%d ISR SWRING flag:%hhd ACT:%hhd@:%lu\n" ++ ,enclient,gstScldmaInfo.bDmaflag[enclient],u16RealIdx,u32Time); ++} ++static void Drv_SCLIRQ_SWRingMode_Active_N(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ ST_SCLDMA_FRAME_BUFFER_CONFIG stTarget; ++ MS_U64 u64Time; ++ u64Time = ((MS_U64)Chip_Get_US_Ticks()); ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_ACTIVE); ++ stTarget.u8FrameAddrIdx = _GetIdxType(enclient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ stTarget.u32FrameAddr = gstScldmaInfo.u32Base_Y[enclient][stTarget.u8FrameAddrIdx]; ++ stTarget.u64FRMDoneTime = u64Time; ++ stTarget.u16FrameWidth = gstScldmaInfo.u16FrameWidth[enclient]; ++ stTarget.u16FrameHeight = gstScldmaInfo.u16FrameHeight[enclient]; ++ if(Drv_SCLDMA_MakeSureNextActiveId(enclient)) ++ { ++ if(Drv_SCLDMA_BufferEnQueue(enclient,stTarget)) ++ { ++ Drv_SCLDMA_ChangeBufferIdx(enclient); ++ } ++ } ++ if(_IsFlagType(enclient,E_SCLDMA_FLAG_BLANKING)) ++ { ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_BLANKING); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enclient,1), "[DRVSCLDMA]%d ISR SWRING actN flag:%hhd idx:%hhd\n" ++ ,enclient,gstScldmaInfo.bDmaflag[enclient],gstScldmaInfo.bDMAidx[enclient]); ++} ++static void Drv_SCLIRQ_SC3SingleMode_Active(void) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_SC3SINGLE, "[DRVSCLIRQ]SC3 single act\n"); ++} ++static void Drv_SCLIRQ_SC3SingleMode_Active_N(void) ++{ ++ Drv_SCLDMA_SetISRHandlerDMAOff(E_SCLDMA_3_FRM_W,0); ++ _SetANDGetFlagType(E_SCLDMA_3_FRM_W,E_SCLDMA_FLAG_DMAOFF,~(E_SCLDMA_FLAG_EVERDMAON)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_SC3SINGLE, "[DRVSCLIRQ]SC3 single actN\n"); ++} ++static void Drv_SCLIRQ_SingleMode_Active(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ MS_U32 u32Time; ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ if(enclient< E_SCLDMA_3_FRM_R) ++ { ++ Drv_SCLDMA_SetISRHandlerDMAOff(enclient,0); ++ } ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_SC1SINGLE, "[DRVSCLIRQ]single act:%lu\n",u32Time); ++} ++static void Drv_SCLIRQ_SingleMode_Active_N(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ MS_U32 u32Time; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_SC1SINGLE, "[DRVSCLIRQ]single actN:%lu\n",u32Time); ++} ++static void Drv_SCLIRQ_SingleMode_ActiveWithoutDoublebuffer(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ MS_U32 u32Time; ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_SC1SINGLE, "[DRVSCLIRQ]singlewodb act:%lu\n",u32Time); ++} ++static void Drv_SCLIRQ_SingleMode_Active_NWithoutDoublebuffer(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ MS_U32 u32Time; ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ if(enclient< E_SCLDMA_3_FRM_R) ++ { ++ Drv_SCLDMA_SetISRHandlerDMAOff(enclient,0); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_SC1SINGLE, "[DRVSCLIRQ]singlewodb actN:%lu\n",u32Time); ++} ++static void _Drv_SCLIRQ_SetFrameInFlag(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ if(_IsFrmIN()) ++ { ++ _SetFlagType(enclient,E_SCLDMA_FLAG_FRMIN); ++ } ++ else ++ { ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_FRMIN); ++ } ++} ++void _Drv_SCLIRQ_MonitorSystemTimer(void) ++{ ++ MS_U64 u64Time; ++ static MS_U64 u64lasttime = 0; ++ u64Time = ((MS_U64)Chip_Get_US_Ticks()); ++ if(u64Time > u64lasttime) ++ { ++ u64lasttime = u64Time; ++ } ++ else ++ { ++ printf("[DRVSCLIRQ]!!!!!!!! system time reset last:%lld this:%lld\n",u64lasttime,u64Time); ++ u64lasttime = u64Time; ++ } ++} ++void _Drv_SCLIRQ_SetFrmEndEvent(void) ++{ ++ if(!gbEachDMAEnable) ++ { ++ gbEachDMAEnable = 1; ++ } ++ if(gsclirqstate) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_IRQ|E_SCLIRQ_EVENT_HVSPST); ++ MsOS_SetEvent(_s32FRMENDEventId, gsclirqstate); ++ if(gsclirqstate &E_SCLIRQ_EVENT_SC1FRM && (gbMonitorCropMode == 2)) ++ { ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_SYNC); ++ } ++ } ++} ++void _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBuffer(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ if ((_IsFlagType(enclient,E_SCLDMA_FLAG_NEXT_ON))) ++ { ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_NEXT_ON); ++ Drv_SCLDMA_SetISRHandlerDMAOff(enclient,1); ++ } ++} ++void _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBufferHandler(void) ++{ ++ _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBuffer(E_SCLDMA_1_FRM_W); ++ _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBuffer(E_SCLDMA_1_SNP_W); ++ _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBuffer(E_SCLDMA_2_FRM_W); ++} ++static void Drv_SCLIRQ_SetFrmEndInterruptStatus(MS_U32 u32Time) ++{ ++ _Drv_SCLIRQ_MonitorSystemTimer(); ++ Drv_SCLDMA_SetISPFrameCount(); ++ Drv_SCLDMA_SetSclFrameDoneTime(u32Time); ++ _Drv_SCLIRQ_SetFrmEndEvent(); ++ _Drv_SCLIRQ_SclFrameEndConnectToISP(); ++ _Drv_SCLIRQ_SetIsBlankingRegion(1); ++ _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBufferHandler(); ++} ++ ++void _Drv_SCLIRQ_HandlerFRMIN(MS_BOOL bEn) ++{ ++ if(!gbPtgenMode) ++ { ++ gbFRMInFlag = (MS_BOOL)((gbFRMInFlag << 1)|bEn); ++ } ++} ++ ++MS_BOOL _Delete_SCLIRQ_IST(void) ++{ ++ gstThreadCfg.flag = 0; ++ gstSc3ThreadCfg.flag = 0; ++ if(gstThreadCfg.sttask.pThread) ++ { ++ kthread_stop(gstThreadCfg.sttask.pThread); ++ gstThreadCfg.sttask.pThread = NULL; ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]stop thread\n")); ++ } ++ if(gstSc3ThreadCfg.sttask.pThread) ++ { ++ kthread_stop(gstSc3ThreadCfg.sttask.pThread); ++ gstSc3ThreadCfg.sttask.pThread = NULL; ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]stop SC3 thread\n")); ++ } ++ return 0; ++} ++//To Do:clear single mode irq ++void _Drv_SCLIRQ_SetSingleModeDMAInfo(EN_SCLDMA_CLIENT_TYPE enclient, MS_U32 u32Events) ++{ ++ if ((u32Events & (SCLIRQ_ISTEVENT_BASE << enclient)) && _Is_SCLDMA_SingleMode(enclient)) ++ { ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ gstScldmaInfo.bDMAOnOff[enclient] = 0; ++ Drv_SCLDMA_SetFrameResolution(enclient); ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++ } ++} ++static int SCLIRQ_IST(void *arg) ++{ ++ MS_U32 u32Events = 0; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLIRQ]%s:going\n",__FUNCTION__); ++ while(gstThreadCfg.flag == 1) ++ { ++ MsOS_WaitEvent(_s32FRMENDEventId, E_SCLIRQ_EVENT_IRQ, &u32Events, E_OR, MSOS_WAIT_FOREVER); // get status: FRM END ++ u32Events = MsOS_GetEvent(_s32FRMENDEventId);//get now ir ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLIRQ]%s:u32Events:%lx\n",__FUNCTION__,u32Events); ++ _Drv_SCLIRQ_SetSingleModeDMAInfo(E_SCLDMA_1_FRM_W,u32Events); ++ _Drv_SCLIRQ_SetSingleModeDMAInfo(E_SCLDMA_1_SNP_W,u32Events); ++ _Drv_SCLIRQ_SetSingleModeDMAInfo(E_SCLDMA_2_FRM_W,u32Events); ++ MsOS_ClearEventIRQ(_s32FRMENDEventId,(E_SCLIRQ_EVENT_IRQ|E_SCLIRQ_EVENT_ISTFRMEND)); ++ } ++ ++ return 0; ++ ++} ++ ++//To Do:do SC3 irq Bottom ++static int SCLIRQ_SC3IST(void *arg) ++{ ++ MS_U32 u32Events = 0; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLIRQ]%s:going\n",__FUNCTION__); ++ while(gstSc3ThreadCfg.flag == 1) ++ { ++ MsOS_WaitEvent(_s32SC3EventId, E_SCLIRQ_SC3EVENT_IRQ, &u32Events, E_OR, MSOS_WAIT_FOREVER); // get status: FRM END ++ u32Events = MsOS_GetEvent(_s32SC3EventId);//get now ir ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLIRQ]%s:u32Events:%lx\n",__FUNCTION__,u32Events); ++ if(u32Events & E_SCLIRQ_SC3EVENT_ISTACTIVE) ++ { ++ if(_Is_SCLDMA_RingMode(E_SCLDMA_3_FRM_W)) ++ { ++ } ++ else if(_Is_SCLDMA_SingleMode(E_SCLDMA_3_FRM_W)) ++ { ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ Drv_SCLIRQ_SingleMode_Active(E_SCLDMA_3_FRM_W); ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++ } ++ } ++ ++ if(u32Events & E_SCLIRQ_SC3EVENT_ISTACTIVEN) ++ { ++ if(_Is_SCLDMA_RingMode(E_SCLDMA_3_FRM_W)) ++ { ++ } ++ else if(_Is_SCLDMA_SingleMode(E_SCLDMA_3_FRM_W)) ++ { ++ Drv_SCLIRQ_SingleMode_Active_N(E_SCLDMA_3_FRM_W); ++ _Drv_SCLIRQ_SetSingleModeDMAInfo(E_SCLDMA_3_FRM_W,(SCLIRQ_ISTEVENT_BASE << E_SCLDMA_3_FRM_W)); ++ _Drv_SCLIRQ_SetSingleModeDMAInfo(E_SCLDMA_3_FRM_R,(SCLIRQ_ISTEVENT_BASE << E_SCLDMA_3_FRM_R)); ++ } ++ } ++ if(u32Events & E_SCLIRQ_SC3EVENT_ISTDONE) ++ { ++ MsOS_ClearEventIRQ(_s32SC3EventId,u32Events &(E_SCLIRQ_SC3EVENT_ISTCLEAR)); ++ MsOS_SetEvent_IRQ(_s32SC3EventId, (E_SCLIRQ_SC3EVENT_DONE |E_SCLIRQ_SC3EVENT_HVSPST)); ++ } ++ } ++ ++ return 0; ++ ++} ++MS_BOOL _Drv_SCLIRQ_ISTWork(ST_SCLDMA_THREAD_CONFIG *pstThread) ++{ ++ if (IS_ERR(pstThread->sttask.pThread)) ++ { ++ pstThread->sttask.pThread = NULL; ++ Drv_SCLDMA_SetThreadOnOffFlag(0,pstThread); ++ DRV_SCLIRQ_ERR(printf("[DRVSCLDMA]Fail:creat thread\n")); ++ return FALSE; ++ } ++ else ++ { ++ Drv_SCLDMA_SetThreadOnOffFlag(1,pstThread); ++ return TRUE; ++ } ++} ++MS_BOOL _Create_SCLIRQ_IST(void) ++{ ++ char *pName={"SCLIRQ_THREAD"}; ++ char *pSc3Name={"SCLIRQ_SC3THREAD"}; ++ unsigned char bRet = 0; ++ gstThreadCfg.s32Taskid = MsOS_CreateTask((TaskEntry)SCLIRQ_IST,(MS_U32)&gstThreadCfg,TRUE,pName); ++ gstSc3ThreadCfg.s32Taskid = MsOS_CreateTask((TaskEntry)SCLIRQ_SC3IST,(MS_U32)&gstSc3ThreadCfg,TRUE,pSc3Name); ++ gstThreadCfg.sttask = MsOS_GetTaskinfo(gstThreadCfg.s32Taskid); ++ gstSc3ThreadCfg.sttask = MsOS_GetTaskinfo(gstSc3ThreadCfg.s32Taskid); ++ MsOS_SetUserNice(gstSc3ThreadCfg.sttask,-9); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, ++ "[DRVSCLDMA]SC3 nice :%d Sc1:%d\n", ++ MsOS_GetUserNice(gstSc3ThreadCfg.sttask), ++ MsOS_GetUserNice(gstThreadCfg.sttask)); ++ bRet = _Drv_SCLIRQ_ISTWork(&gstThreadCfg); ++ bRet = _Drv_SCLIRQ_ISTWork(&gstSc3ThreadCfg); ++ return bRet; ++} ++void _Drv_SCLIRQ_AffFullHandler(MS_U32 u32Time ,MS_BOOL *bAffFull ,MS_BOOL *bAffcount) ++{ ++ if(!(*bAffFull)) ++ { ++ printf("SC AFF FULL @:%lu\n",u32Time); ++ *bAffFull = 1; ++ } ++ if((*bAffcount)>200) ++ { ++ *bAffFull = 0; ++ *bAffcount = 0; ++ } ++} ++void _Drv_SCLIRQ_IsAffFullContinue(MS_BOOL *bAffFull ,MS_BOOL *bAffcount) ++{ ++ if((*bAffFull)) ++ { ++ (*bAffcount)++; ++ } ++} ++void _Drv_SCLIRQ_FrameInEndHandler(MS_BOOL *bNonFRMEndCount,MS_BOOL *bISPFramePerfect) ++{ ++ Drv_SCLDMA_SetISPFrameCount(); ++ *bISPFramePerfect = 1; ++ if(gbEachDMAEnable) ++ { ++ (*bNonFRMEndCount)++; ++ if((*bNonFRMEndCount)>3) ++ { ++ gbEachDMAEnable = 0; ++ } ++ } ++} ++void _Drv_SCLIRQ_LDCVsyncInHandler(MS_BOOL *bISPFramePerfect) ++{ ++ if(!(*bISPFramePerfect)) ++ { ++ _Drv_SCLIRQ_HandlerFRMIN(0); ++ } ++ else ++ { ++ _Drv_SCLIRQ_HandlerFRMIN(1); ++ *bISPFramePerfect = 0; ++ } ++ gsclirqstate = E_SCLIRQ_EVENT_CLEAR; ++ if(gbEachDMAEnable) ++ { ++ _Drv_SCLIRQ_SetIsBlankingRegion(0); ++ } ++ if(gbMonitorCropMode == 1) ++ { ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_SYNC); ++ } ++} ++void _Drv_SCLIRQ_DMAActiveHandler(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ if(_Is_SCLDMA_RingMode(enclient) && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_RingMode_Active(enclient); ++ } ++ else if(_Is_SCLDMA_RingMode(enclient)) ++ { ++ Drv_SCLIRQ_RingMode_ActiveWithoutDoublebuffer(enclient); ++ } ++ else if(_Is_SCLDMA_SWRingMode(enclient)) ++ { ++ Drv_SCLIRQ_SWRingMode_Active(enclient); ++ } ++ else if(enclient ==E_SCLDMA_3_FRM_W &&_Is_SCLDMA_SingleMode(E_SCLDMA_3_FRM_W)) ++ { ++ Drv_SCLIRQ_SC3SingleMode_Active(); ++ } ++ else if(_Is_SCLDMA_SingleMode(enclient) && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_SingleMode_Active(enclient); ++ } ++ else if(_Is_SCLDMA_SingleMode(enclient)) ++ { ++ Drv_SCLIRQ_SingleMode_ActiveWithoutDoublebuffer(enclient); ++ } ++} ++void _Drv_SCLIRQ_DMAActive_NHandler(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ if(_Is_SCLDMA_RingMode(enclient) && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_RingMode_Active_N(enclient); ++ } ++ else if(_Is_SCLDMA_RingMode(enclient)) ++ { ++ Drv_SCLIRQ_RingMode_Active_NWithoutDoublebuffer(enclient); ++ } ++ else if(_Is_SCLDMA_SWRingMode(enclient)) ++ { ++ Drv_SCLIRQ_SWRingMode_Active_N(enclient); ++ } ++ else if(enclient ==E_SCLDMA_3_FRM_W && _Is_SCLDMA_SingleMode(E_SCLDMA_3_FRM_W)) ++ { ++ Drv_SCLIRQ_SC3SingleMode_Active_N(); ++ } ++ else if(_Is_SCLDMA_SingleMode(enclient) && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_SingleMode_Active_N(enclient); ++ } ++ else if(_Is_SCLDMA_SingleMode(enclient)) ++ { ++ Drv_SCLIRQ_SingleMode_Active_NWithoutDoublebuffer(enclient); ++ } ++ if(enclient < E_SCLDMA_3_FRM_R) ++ { ++ _Drv_SCLIRQ_SetFrameInFlag(enclient); ++ } ++} ++irqreturn_t _Drv_SCLIRQ_isr(int eIntNum, void* dev_id) ++{ ++ MS_U64 u64Flag,u64Mask=0x0; ++ MS_U32 u32Time; ++ static MS_BOOL bISPFramePerfect = 0; ++ static MS_BOOL bNonFRMEndCount = 0; ++ static MS_BOOL bAffFull = 1,bAffcount=0; ++ u64Mask = gstScldmaInfo.u64mask; ++ u64Flag = Hal_SCLIRQ_Get_Flag(0xFFFFFFFFFF); ++ if(_bSCLIRQ_Suspend) ++ { ++ Hal_SCLIRQ_Set_Clear(0xFFFFFFFFFF, 1); ++ } ++ ++ Hal_SCLIRQ_Set_Clear((~u64Mask)&u64Flag, 1); ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ if(u64Flag &SCLIRQ_MSK_AFF_FULL) ++ { ++ _Drv_SCLIRQ_AffFullHandler(u32Time, &bAffFull, &bAffcount); ++ } ++ // next frame IN . because of delay 1 frame. ++ // 1.frame coming ++ // 2.frame receive done.(irq get)keep in DNR ++ // 3.active from dnr ++ if(u64Flag &SCLIRQ_MSK_SC_IN_FRM_END) ++ { ++ _Drv_SCLIRQ_FrameInEndHandler(&bNonFRMEndCount,&bISPFramePerfect); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[FRMIN]@%lu\n",MsOS_GetSystemTime()); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_SC1_HVSP_FINISH) ++ { ++ //printf("HVSP:%lu,%ld\n",u32Time,count); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC) ++ { ++ _Drv_SCLIRQ_LDCVsyncInHandler(&bISPFramePerfect); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[FRMLDC]@%lu\n",MsOS_GetSystemTime()); ++ } ++ // SC1 FRM ++ if(u64Flag & SCLIRQ_MSK_SC1_FRM_W_ACTIVE) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_1_FRM_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC1FRM|E_SCLIRQ_EVENT_ISTSC1FRM); ++ _Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_1_FRM_W); ++ } ++ ++ ++ // SC2 FRM ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM_W_ACTIVE) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_2_FRM_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC2FRM|E_SCLIRQ_EVENT_ISTSC2FRM); ++ _Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_2_FRM_W); ++ } ++ // SC1 SNP ++ if(u64Flag & SCLIRQ_MSK_SC1_SNP_W_ACTIVE) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_1_SNP_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC1SNP|E_SCLIRQ_EVENT_ISTSC1SNP); ++ _Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_1_SNP_W); ++ } ++ // SC SRC FRMEND ++ if(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END) ++ { ++ Drv_SCLIRQ_SetFrmEndInterruptStatus(u32Time); ++ _Drv_SCLIRQ_IsAffFullContinue(&bAffFull, &bAffcount); ++ bNonFRMEndCount = 0; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "[FRMEND]%x flag:%llx,%lu\n",gsclirqstate,u64Flag,MsOS_GetSystemTime()); ++ } ++ ++ // SC3 FRM_W ++ if(u64Flag & SCLIRQ_MSK_SC3_DMA_W_ACTIVE) ++ { ++ gscl3irqstate = E_SCLIRQ_SC3EVENT_CLEAR; ++ gscl3irqstate |= (E_SCLIRQ_SC3EVENT_ACTIVE | E_SCLIRQ_SC3EVENT_ISTACTIVE); ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_3_FRM_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N) ++ { ++ gscl3irqstate |= (E_SCLIRQ_SC3EVENT_ACTIVEN | E_SCLIRQ_SC3EVENT_ISTACTIVEN | E_SCLIRQ_SC3EVENT_IRQ); ++ _Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_3_FRM_W); ++ MsOS_SetEvent(_s32SC3EventId, gscl3irqstate); ++ } ++ ++ Hal_SCLIRQ_Set_Clear((~u64Mask)&u64Flag, 0); ++ ++ return IRQ_HANDLED; ++} ++#endif ++MS_BOOL Drv_SCLIRQ_InitVariable(void) ++{ ++ MS_U64 u64Flag; ++#if (ENABLE_ISR) ++ MsOS_Memset(&gstSCLIrqInfo, 0, sizeof(ST_SCLIRQ_IFNO_TYPE)); ++#endif ++ gsclirqstate = 0; ++ gscl3irqstate = 0; ++ _bSCLIRQ_Suspend = 0; ++ gbFRMInFlag = 0; ++ gbPtgenMode = 0; ++ gbMonitorCropMode = 0; ++ gbEachDMAEnable = 0; ++ _Drv_SCLIRQ_SetIsBlankingRegion(1); ++ u64Flag = Hal_SCLIRQ_Get_Flag(0xFFFFFFFFFF); ++ Hal_SCLIRQ_Set_Clear(u64Flag, 1); ++ Hal_SCLIRQ_Set_Clear(u64Flag, 0); ++ return TRUE; ++} ++void Drv_SCLIRQ_SetPTGenStatus(MS_BOOL bPTGen) ++{ ++ gbPtgenMode = bPTGen; ++ if(bPTGen) ++ { ++ gbFRMInFlag = bPTGen | (bPTGen<< SCL_DELAYFRAME_FROM_ISP); ++ } ++} ++ ++void Drv_SCLIRQ_Set_Checkcropflag(MS_BOOL bcheck) ++{ ++ gbMonitorCropMode = bcheck; ++} ++MS_U8 Drv_SCLIRQ_Get_Checkcropflag(void) ++{ ++ return gbMonitorCropMode; ++} ++MS_U8 Drv_SCLIRQ_GetEachDMAEn(void) ++{ ++ return gbEachDMAEnable; ++} ++MS_BOOL Drv_SCLIRQ_Init(ST_SCLIRQ_INIT_CONFIG *pCfg) ++{ ++ char mutx_word[] = {"_SCLIRQ_Mutex"}; ++ ++ MS_U8 i; ++ ++ if(_SCLIRQ_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, "[DRVSCLIRQ]%s(%d)::Already Done\n", __FUNCTION__, __LINE__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d)::MsOS_Init Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ _SCLIRQ_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, mutx_word, MSOS_PROCESS_SHARED); ++ _pSCLIRQ_SCLDMA_Mutex = Drv_SCLDMA_GetDMAandIRQCommonMutex(); ++ if (_SCLIRQ_Mutex == -1) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d)::Create Mutex Flag Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ Hal_SCLIRQ_Set_Riu_Base(pCfg->u32RiuBase); ++ ++ // disable all interrupt first ++ for(i=0; iu32IRQNUM; ++ if(MsOS_AttachInterrupt(pCfg->u32IRQNUM, (InterruptCb)_Drv_SCLIRQ_isr ,IRQF_DISABLED, "SCLINTR")) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d):: Request IRQ Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ MsOS_DisableInterrupt(pCfg->u32IRQNUM); ++ MsOS_EnableInterrupt(pCfg->u32IRQNUM); ++ _Create_SCLIRQ_IST(); ++#endif ++#if (ENABLE_CMDQ_ISR) ++ Drv_CMDQ_InitRIUBase(pCfg->u32RiuBase); ++ if(MsOS_AttachInterrupt(pCfg->u32CMDQIRQNUM, (InterruptCb)_Drv_SCLIRQ_CMDQ_isr ,IRQF_DISABLED, "CMDQINTR")) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d):: Request IRQ Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ gu32CMDQIRQNUM = pCfg->u32CMDQIRQNUM; ++ MsOS_DisableInterrupt(pCfg->u32CMDQIRQNUM); ++ MsOS_EnableInterrupt(pCfg->u32CMDQIRQNUM); ++ Drv_CMDQ_SetISRStatus(1); ++#endif ++ ++ ++ return TRUE; ++} ++wait_queue_head_t * Drv_SCLIRQ_GetWaitQueueHead(MS_U32 enID) ++{ ++ if(enID == E_SCLDMA_ID_3_W) ++ { ++ return MsOS_GetEventQueue(_s32SC3EventId); ++ } ++ else ++ { ++ return MsOS_GetEventQueue(_s32FRMENDEventId); ++ } ++} ++ ++wait_queue_head_t * Drv_SCLIRQ_GetSyncQueue(void) ++{ ++ return MsOS_GetEventQueue(_s32SYNCEventId); ++} ++ ++MS_S32 Drv_SCLIRQ_Get_IRQ_EventID(void) ++{ ++ return _s32FRMENDEventId; ++} ++MS_S32 Drv_SCLIRQ_Get_IRQ_SYNCEventID(void) ++{ ++ return _s32SYNCEventId; ++} ++MS_S32 Drv_SCLIRQ_Get_IRQ_SC3EventID(void) ++{ ++ return _s32SC3EventId; ++} ++ ++MS_BOOL Drv_SCLIRQ_Suspend(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, "%s(%d), bSuspend=%d\n", __FUNCTION__, __LINE__, _bSCLIRQ_Suspend); ++ _bSCLIRQ_Suspend = 1; ++ return TRUE; ++} ++ ++MS_BOOL Drv_SCLIRQ_Resume(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ MS_U16 i; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, "%s(%d), bResume=%d\n", __FUNCTION__, __LINE__, _bSCLIRQ_Suspend); ++ ++ if(_bSCLIRQ_Suspend == 1) ++ { ++ // disable all interrupt first ++ for(i=0; i ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_SCLIRQ_H ++#define _DRV_SCLIRQ_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Enum ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++ MS_U32 u32IRQNUM; ++ MS_U32 u32CMDQIRQNUM; ++}ST_SCLIRQ_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32IRQNUM; ++ MS_U32 u32CMDQIRQNUM; ++}ST_SCLIRQ_SUSPEND_RESUME_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_SCLIRQ_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE wait_queue_head_t * Drv_SCLIRQ_GetWaitQueueHead(MS_U32 enID); ++INTERFACE void Drv_SCLIRQ_SetPTGenStatus(MS_BOOL bPTGen); ++INTERFACE void Drv_SCLIRQ_Set_Checkcropflag(MS_BOOL bcheck); ++INTERFACE MS_U8 Drv_SCLIRQ_Get_Checkcropflag(void); ++INTERFACE MS_U8 Drv_SCLIRQ_GetEachDMAEn(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_InitVariable(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_GetIsBlankingRegion(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_Init(ST_SCLIRQ_INIT_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLIRQ_Exit(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_InterruptEnable(MS_U16 u16IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Disable(MS_U16 u16IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Get_Flag(MS_U16 u16IRQ, MS_U64 *pFlag); ++INTERFACE MS_BOOL Drv_SCLIRQ_Set_Clear(MS_U16 u16IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Get_Flags_Msk(MS_U64 u64IrqMsk, MS_U64 *pFlags); ++INTERFACE MS_BOOL Drv_SCLIRQ_Set_Clear_Msk(MS_U64 u64IrqMsk); ++INTERFACE MS_BOOL Drv_SCLIRQ_Set_Mask(MS_U64 u64IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Suspend(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLIRQ_Resume(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_S32 Drv_SCLIRQ_Get_IRQ_EventID(void); ++INTERFACE MS_S32 Drv_SCLIRQ_Get_IRQ_SYNCEventID(void); ++INTERFACE MS_S32 Drv_SCLIRQ_Get_IRQ_SC3EventID(void); ++INTERFACE wait_queue_head_t * Drv_SCLIRQ_GetSyncQueue(void); ++INTERFACE void scl_ve_isr(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/sclirq/drvsclirq_st.h b/drivers/mstar/scl/infinity/src/mxlib/drv/sclirq/drvsclirq_st.h +new file mode 100644 +index 00000000..1d9811f9 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/sclirq/drvsclirq_st.h +@@ -0,0 +1,372 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef DRV_SCLIRQ_ST_H ++#define DRV_SCLIRQ_ST_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & enum ++//------------------------------------------------------------------------------------------------- ++#define SCL_DELAYFRAME_FROM_ISP (gu8DNRBufferReadyNum) //0 or 1 or 2 ++#define SCLIRQ_MSK_SC_IN_FRM_END (((MS_U64)1)<<0) ++#define SCLIRQ_MSK_SC3_ENG_FRM_END (((MS_U64)1)<<1) ++#define SCLIRQ_MSK_SC1_ENG_FRM_END (((MS_U64)1)<<2) ++#define SCLIRQ_MSK_DISP_DMA_END (((MS_U64)1)<<3) ++#define SCLIRQ_MSK_VSYNC_IDCLK (((MS_U64)1)<<4) ++#define SCLIRQ_MSK_VSYNC_SC1_HVSP_FINISH (((MS_U64)1)<<6) ++#define SCLIRQ_MSK_SC1_FRM_W_ACTIVE (((MS_U64)1)<<7) ++#define SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N (((MS_U64)1)<<8) ++#define SCLIRQ_MSK_SC1_SNP_W_ACTIVE (((MS_U64)1)<<9) ++#define SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N (((MS_U64)1)<<10) ++#define SCLIRQ_MSK_SC1_SNPI_W_ACTIVE (((MS_U64)1)<<11) ++#define SCLIRQ_MSK_SC1_SNPI_W_ACTIVE_N (((MS_U64)1)<<12) ++#define SCLIRQ_MSK_TRIG_LDC (((MS_U64)1)<<13) ++#define SCLIRQ_MSK_AFF_FULL (((MS_U64)1)<<14) ++#define SCLIRQ_MSK_VIP_HIST_DONE (((MS_U64)1)<<15) ++#define SCLIRQ_MSK_SC1_DBG_R_ACTIVE (((MS_U64)1)<<17) ++#define SCLIRQ_MSK_SC1_DBG_R_ACTIVE_N (((MS_U64)1)<<18) ++#define SCLIRQ_MSK_TTL_VS (((MS_U64)1)<<19) ++#define SCLIRQ_MSK_TTL_VDE (((MS_U64)1)<<20) ++#define SCLIRQ_MSK_TTL_VDE_N (((MS_U64)1)<<21) ++#define SCLIRQ_MSK_TRIG_DBG (((MS_U64)1)<<22) ++#define SCLIRQ_MSK_SC2_FRM_W_ACTIVE (((MS_U64)1)<<23) ++#define SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N (((MS_U64)1)<<24) ++#define SCLIRQ_MSK_SC2_FRMI_W_ACTIVE (((MS_U64)1)<<25) ++#define SCLIRQ_MSK_SC2_FRMI_W_ACTIVE_N (((MS_U64)1)<<26) ++#define SCLIRQ_MSK_SC2_HVSP_FINISH (((MS_U64)1)<<27) ++#define SCLIRQ_MSK_VSYNC_FCLK2 (((MS_U64)1)<<28) ++#define SCLIRQ_MSK_SC3_HVSP_FINISH (((MS_U64)1)<<29) ++#define SCLIRQ_MSK_TRIG_SC3_DMA_R (((MS_U64)1)<<30) ++#define SCLIRQ_MSK_SC3_DMA_R_ACTIVE (((MS_U64)1)<<31) ++#define SCLIRQ_MSK_SC3_DMA_R_ACTIVE_N (((MS_U64)1)<<32) ++#define SCLIRQ_MSK_SC3_DMA_W_ACTIVE (((MS_U64)1)<<33) ++#define SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N (((MS_U64)1)<<34) ++#define SCLIRQ_MSK_VSYNC_FCLK_LDC (((MS_U64)1)<<35) ++ ++#define SCLIRQ_SC_IN_FRM_END 0 ++#define SCLIRQ_SC3_ENG_FRM_END 1 ++#define SCLIRQ_SC1_ENG_FRM_END 2 ++#define SCLIRQ_DISP_DMA_END 3 ++#define SCLIRQ_VSYNC_IDCLK 4 ++#define SCLIRQ_VSYNC_FCLK 5 ++#define SCLIRQ_SC1_HVSP_FINISH 6 ++#define SCLIRQ_SC1_FRM_W_ACTIVE 7 ++#define SCLIRQ_SC1_FRM_W_ACTIVE_N 8 ++#define SCLIRQ_SC1_SNP_W_ACTIVE 9 ++#define SCLIRQ_SC1_SNP_W_ACTIVE_N 10 ++#define SCLIRQ_SC1_SNPI_W_ACTIVE 11 ++#define SCLIRQ_SC1_SNPI_W_ACTIVE_N 12 ++#define SCLIRQ_TRIG_LDC 13 ++#define SCLIRQ_AFF_FULL 14 ++#define SCLIRQ_VIP_HIST_DONE 15 ++#define SCLIRQ_RESERVED_00 16 ++#define SCLIRQ_SC1_DBG_R_ACTIVE 17 ++#define SCLIRQ_SC1_DBG_R_ACTIVE_N 18 ++#define SCLIRQ_TTL_VS 19 ++#define SCLIRQ_TTL_VDE 20 ++#define SCLIRQ_TTL_VDE_N 21 ++#define SCLIRQ_TRIG_DBG 22 ++#define SCLIRQ_SC2_FRM_W_ACTIVE 23 ++#define SCLIRQ_SC2_FRM_W_ACTIVE_N 24 ++#define SCLIRQ_SC2_FRMI_W_ACTIVE 25 ++#define SCLIRQ_SC2_FRMI_W_ACTIVE_N 26 ++#define SCLIRQ_SC2_HVSP_FINISH 27 ++#define SCLIRQ_VSYNC_FCLK2 28 ++#define SCLIRQ_SC3_HVSP_FINISH 29 ++#define SCLIRQ_TRIG_SC3_DMA_R 30 ++#define SCLIRQ_SC3_DMA_R_ACTIVE 31 ++#define SCLIRQ_SC3_DMA_R_ACTIVE_N 32 ++#define SCLIRQ_SC3_DMA_W_ACTIVE 33 ++#define SCLIRQ_SC3_DMA_W_ACTIVE_N 34 ++#define SCLIRQ_VSYNC_FCLK_LDC 35 ++#define SCLIRQ_RESERVED 48 ++#define SCLIRQ_NUM 48 //I1 interrupt ++ ++#define SCLIRQ_EVENT_MSK_SC_IN_FRM_END (((MS_U32)1)<<0) ++#define SCLIRQ_EVENT_MSK_SC3_ENG_FRM_END (((MS_U32)1)<<1) ++#define SCLIRQ_EVENT_MSK_SC1_ENG_FRM_END (((MS_U32)1)<<2) ++#define SCLIRQ_EVENT_MSK_DISP_DMA_END (((MS_U32)1)<<3) ++#define SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE (((MS_U32)1)<<4) ++#define SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE_N (((MS_U32)1)<<5) ++#define SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE (((MS_U32)1)<<6) ++#define SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE_N (((MS_U32)1)<<7) ++#define SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE (((MS_U32)1)<<8) ++#define SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE_N (((MS_U32)1)<<9) ++#define SCLIRQ_EVENT_MSK_TRIG_LDC (((MS_U32)1)<<10) ++#define SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE (((MS_U32)1)<<11) ++#define SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE_N (((MS_U32)1)<<12) ++#define SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE (((MS_U32)1)<<13) ++#define SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE_N (((MS_U32)1)<<14) ++#define SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE (((MS_U32)1)<<15) ++#define SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE_N (((MS_U32)1)<<16) ++#define SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE (((MS_U32)1)<<17) ++#define SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE_N (((MS_U32)1)<<18) ++#define SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE (((MS_U32)1)<<19) ++#define SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE_N (((MS_U32)1)<<20) ++#define SCLIRQ_EVENT_MSK_VSYNC_FCLK_LDC (((MS_U32)1)<<21) ++#define SCLIRQ_EVENT_MSK_ALL (0xFFFFFFFF) ++ ++ ++#define SCLIRQ_EVENT_SC_IN_FRM_END 0 ++#define SCLIRQ_EVENT_SC3_ENG_FRM_END 1 ++#define SCLIRQ_EVENT_SC1_ENG_FRM_END 2 ++#define SCLIRQ_EVENT_DISP_DMA_END 3 ++#define SCLIRQ_EVENT_SC1_FRM_W_ACTIVE 4 ++#define SCLIRQ_EVENT_SC1_FRM_W_ACTIVE_N 5 ++#define SCLIRQ_EVENT_SC1_SNP_W_ACTIVE 6 ++#define SCLIRQ_EVENT_SC1_SNP_W_ACTIVE_N 7 ++#define SCLIRQ_EVENT_SC1_SNPI_W_ACTIVE 8 ++#define SCLIRQ_EVENT_SC1_SNPI_W_ACTIVE_N 9 ++#define SCLIRQ_EVENT_TRIG_LDC 10 ++#define SCLIRQ_EVENT_SC1_DBG_R_ACTIVE 11 ++#define SCLIRQ_EVENT_SC1_DBG_R_ACTIVE_N 12 ++#define SCLIRQ_EVENT_SC2_FRM_W_ACTIVE 13 ++#define SCLIRQ_EVENT_SC2_FRM_W_ACTIVE_N 14 ++#define SCLIRQ_EVENT_SC2_FRMI_W_ACTIVE 15 ++#define SCLIRQ_EVENT_SC2_FRMI_W_ACTIVE_N 16 ++#define SCLIRQ_EVENT_SC3_DMA_R_ACTIVE 17 ++#define SCLIRQ_EVENT_SC3_DMA_R_ACTIVE_N 18 ++#define SCLIRQ_EVENT_SC3_DMA_W_ACTIVE 19 ++#define SCLIRQ_EVENT_SC3_DMA_W_ACTIVE_N 20 ++#define SCLIRQ_EVENT_VSYNC_FCLK_LDC 21 ++#define SCLIRQ_EVENT_NUM 22 ++#define SCLIRQ_ISTEVENT_BASE 0x10 ++ ++ ++ ++#define PARSING_EVENT_MSK(x) ( (x & SCLIRQ_EVENT_MSK_SC_IN_FRM_END) == SCLIRQ_EVENT_MSK_SC_IN_FRM_END ? "SCLIRQ_EVENT_MSK_SC_IN_FRM_END" : \ ++ (x & SCLIRQ_EVENT_MSK_SC3_ENG_FRM_END) == SCLIRQ_EVENT_MSK_SC3_ENG_FRM_END ? "SCLIRQ_EVENT_MSK_SC3_ENG_FRM_END" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_ENG_FRM_END) == SCLIRQ_EVENT_MSK_SC1_ENG_FRM_END ? "SCLIRQ_EVENT_MSK_SC1_ENG_FRM_END" : \ ++ (x & SCLIRQ_EVENT_MSK_DISP_DMA_END) == SCLIRQ_EVENT_MSK_DISP_DMA_END ? "SCLIRQ_EVENT_MSK_DISP_DMA_END" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE) == SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE ? "SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC1_FRM_W_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE) == SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE ? "SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC1_SNP_W_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE) == SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE ? "SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC1_SNPI_W_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_TRIG_LDC) == SCLIRQ_EVENT_MSK_TRIG_LDC ? "SCLIRQ_EVENT_MSK_TRIG_LDC" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE) == SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE ? "SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC1_DBG_R_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE) == SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE ? "SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC2_FRM_W_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE) == SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE ? "SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC2_FRMI_W_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE) == SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE ? "SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC3_DMA_R_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE) == SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE ? "SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE" : \ ++ (x & SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE_N) == SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE_N ? "SCLIRQ_EVENT_MSK_SC3_DMA_W_ACTIVE_N" : \ ++ (x & SCLIRQ_EVENT_MSK_VSYNC_FCLK_LDC) == SCLIRQ_EVENT_MSK_VSYNC_FCLK_LDC ? "SCLIRQ_EVENT_MSK_VSYNC_FCLK_LDC" : \ ++ "UNKNOWN") ++ ++ ++#define PARSING_IRQ_MSK(x) ( (x & SCLIRQ_MSK_SC_IN_FRM_END ) ? "SCLIRQ_MSK_SC_IN_FRM_END " : \ ++ (x & SCLIRQ_MSK_SC3_ENG_FRM_END ) ? "SCLIRQ_MSK_SC3_ENG_FRM_END " : \ ++ (x & SCLIRQ_MSK_SC1_ENG_FRM_END ) ? "SCLIRQ_MSK_SC1_ENG_FRM_END " : \ ++ (x & SCLIRQ_MSK_DISP_DMA_END ) ? "SCLIRQ_MSK_DISP_DMA_END " : \ ++ (x & SCLIRQ_MSK_SC1_FRM_W_ACTIVE ) ? "SCLIRQ_MSK_SC1_FRM_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC1_SNP_W_ACTIVE ) ? "SCLIRQ_MSK_SC1_SNP_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC1_SNPI_W_ACTIVE ) ? "SCLIRQ_MSK_SC1_SNPI_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_SNPI_W_ACTIVE_N) ? "SCLIRQ_MSK_SC1_SNPI_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_TRIG_LDC ) ? "SCLIRQ_MSK_TRIG_LDC " : \ ++ (x & SCLIRQ_MSK_AFF_FULL ) ? "SCLIRQ_MSK_AFF_FULL " : \ ++ (x & SCLIRQ_MSK_VIP_HIST_DONE ) ? "SCLIRQ_MSK_VIP_HIST_DONE " : \ ++ (x & SCLIRQ_MSK_SC1_DBG_R_ACTIVE ) ? "SCLIRQ_MSK_SC1_DBG_R_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_DBG_R_ACTIVE_N ) ? "SCLIRQ_MSK_SC1_DBG_R_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_TTL_VS ) ? "SCLIRQ_MSK_TTL_VS " : \ ++ (x & SCLIRQ_MSK_TTL_VDE ) ? "SCLIRQ_MSK_TTL_VDE " : \ ++ (x & SCLIRQ_MSK_TTL_VDE_N ) ? "SCLIRQ_MSK_TTL_VDE_N " : \ ++ (x & SCLIRQ_MSK_TRIG_DBG ) ? "SCLIRQ_MSK_TRIG_DBG " : \ ++ (x & SCLIRQ_MSK_SC2_FRM_W_ACTIVE ) ? "SCLIRQ_MSK_SC2_FRM_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC2_FRMI_W_ACTIVE ) ? "SCLIRQ_MSK_SC2_FRMI_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC2_FRMI_W_ACTIVE_N) ? "SCLIRQ_MSK_SC2_FRMI_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC2_HVSP_FINISH ) ? "SCLIRQ_MSK_SC2_HVSP_FINISH " : \ ++ (x & SCLIRQ_MSK_VSYNC_FCLK2 ) ? "SCLIRQ_MSK_VSYNC_FCLK2 " : \ ++ (x & SCLIRQ_MSK_SC3_HVSP_FINISH ) ? "SCLIRQ_MSK_SC3_HVSP_FINISH " : \ ++ (x & SCLIRQ_MSK_TRIG_SC3_DMA_R ) ? "SCLIRQ_MSK_TRIG_SC3_DMA_R " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_R_ACTIVE ) ? "SCLIRQ_MSK_SC3_DMA_R_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_R_ACTIVE_N ) ? "SCLIRQ_MSK_SC3_DMA_R_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_W_ACTIVE ) ? "SCLIRQ_MSK_SC3_DMA_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_VSYNC_FCLK_LDC ) ? "SCLIRQ_MSK_VSYNC_FCLK_LDC " : \ ++ "UNKNOWN") ++#define _IsFlagType(u8client,u8type) (gstScldmaInfo.bDmaflag[(u8client)] & (u8type)) ++#define _SetANDGetFlagType(u8client,u8Set,u8get) (gstScldmaInfo.bDmaflag[(u8client)]=((gstScldmaInfo.bDmaflag[(u8client)]&(u8get))|(u8Set))) ++#define _SetFlagType(u8client,u8type) (gstScldmaInfo.bDmaflag[(u8client)] |= (u8type)) ++#define _ReSetFlagType(u8client,u8type) (gstScldmaInfo.bDmaflag[(u8client)] &= ~(u8type)) ++#define _GetIdxType(u8client,u8type) (gstScldmaInfo.bDMAidx[(u8client)] & (u8type)) ++#define _SetANDGetIdxType(u8client,u8Set,u8get) (gstScldmaInfo.bDMAidx[(u8client)]=((gstScldmaInfo.bDMAidx[(u8client)]&(u8get))|(u8Set))) ++#define _SetIdxType(u8client,u8type) (gstScldmaInfo.bDMAidx[(u8client)] |= (u8type)) ++#define _ReSetIdxType(u8client,u8type) (gstScldmaInfo.bDMAidx[(u8client)] &= ~(u8type)) ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_SCLIRQ_EVENT_CLEAR = 0x00000000, // no event ++ E_SCLIRQ_EVENT_SC1FRM = 0x00000001, // SC1FRM done (for scldma done,avoid flag to update but not poll,keep it status) ++ E_SCLIRQ_EVENT_SC1SNP = 0x00000002, // SC1SNP done ++ E_SCLIRQ_EVENT_SC1 = (E_SCLIRQ_EVENT_SC1SNP|E_SCLIRQ_EVENT_SC1FRM), // SC1all done ++ E_SCLIRQ_EVENT_SC2FRM = 0x00000004, // SC2 FRM done ++ E_SCLIRQ_EVENT_FRMEND = (E_SCLIRQ_EVENT_SC2FRM|E_SCLIRQ_EVENT_SC1), // SC1 &SC2 done ++ E_SCLIRQ_EVENT_IRQ = 0x00000008, // any one FRM done ++ E_SCLIRQ_EVENT_ISTSC1FRM = 0x00000010, // SC1FRM done for IST ++ E_SCLIRQ_EVENT_ISTSC1SNP = 0x00000020, // SC1SNP done for IST ++ E_SCLIRQ_EVENT_ISTSC1 = (E_SCLIRQ_EVENT_ISTSC1FRM|E_SCLIRQ_EVENT_ISTSC1SNP), // SC1all done for IST ++ E_SCLIRQ_EVENT_ISTSC2FRM = 0x00000080, // SC2 FRM done for IST ++ E_SCLIRQ_EVENT_ISTFRMEND = (E_SCLIRQ_EVENT_ISTSC2FRM|E_SCLIRQ_EVENT_ISTSC1), // SC1 &SC2 done for IST ++ E_SCLIRQ_EVENT_SC1RESTART = 0x00000100, // SC1 FRM re-start ++ E_SCLIRQ_EVENT_SC2RESTART = 0x00000200, // SC2 FRM re-start ++ E_SCLIRQ_EVENT_ALLRESEART = (E_SCLIRQ_EVENT_SC2RESTART|E_SCLIRQ_EVENT_SC1RESTART), // SC1 SC2 restart ++ E_SCLIRQ_EVENT_RESUME = 0x00000400, // Suspend/Resume ++ E_SCLIRQ_EVENT_HVSPST = 0x00000800, ++ E_SCLIRQ_EVENT_SC1RE = (E_SCLIRQ_EVENT_SC1RESTART | E_SCLIRQ_EVENT_RESUME), ++ E_SCLIRQ_EVENT_SC2RE = (E_SCLIRQ_EVENT_SC2RESTART | E_SCLIRQ_EVENT_RESUME), ++ E_SCLIRQ_EVENT_SC1POLL = (E_SCLIRQ_EVENT_SC1|E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_RESUME), ++ E_SCLIRQ_EVENT_SC2POLL = (E_SCLIRQ_EVENT_SC2FRM|E_SCLIRQ_EVENT_SC2RESTART|E_SCLIRQ_EVENT_RESUME), ++ E_SCLIRQ_EVENT_ALLPOLL = (E_SCLIRQ_EVENT_FRMEND|E_SCLIRQ_EVENT_ALLRESEART|E_SCLIRQ_EVENT_RESUME), ++} SCLIRQTXEvent; ++ ++typedef enum ++{ ++ E_SCLIRQ_SC3EVENT_CLEAR = 0x00000000, // no event ++ E_SCLIRQ_SC3EVENT_ACTIVE = 0x00000001, // SC3FRM act ++ E_SCLIRQ_SC3EVENT_ACTIVEN = 0x00000002, // SC3FRM act_N ++ E_SCLIRQ_SC3EVENT_END = 0x00000003, ++ E_SCLIRQ_SC3EVENT_DONE = 0x00000004, // SC3FRM done ++ E_SCLIRQ_SC3EVENT_IRQ = 0x00000008, // any one ISR need to handle ++ E_SCLIRQ_SC3EVENT_ISTACTIVE = 0x00000010, // SC3 FRM act for IST ++ E_SCLIRQ_SC3EVENT_ISTACTIVEN = 0x00000020, // SC3 done for IST ++ E_SCLIRQ_SC3EVENT_ISTDONE = 0x00000030, // SC3 done for IST ++ E_SCLIRQ_SC3EVENT_RESTART = 0x00000100, // SC3 FRM re-start ++ E_SCLIRQ_SC3EVENT_RESUME = 0x00000400, // Suspend/Resume ++ E_SCLIRQ_SC3EVENT_HVSPST = 0x00000800, ++ E_SCLIRQ_SC3EVENT_ISTCLEAR = (E_SCLIRQ_SC3EVENT_IRQ | E_SCLIRQ_SC3EVENT_ISTDONE | E_SCLIRQ_SC3EVENT_END), ++ E_SCLIRQ_SC3EVENT_POLL = (E_SCLIRQ_SC3EVENT_HVSPST | E_SCLIRQ_SC3EVENT_DONE|E_SCLIRQ_SC3EVENT_RESTART|E_SCLIRQ_SC3EVENT_RESUME), ++} SCLIRQSC3Event; ++ ++typedef enum ++{ ++ E_SCLIRQ_EVENT_SYNC = 0x00000001, // Ldc trig ++ E_SCLIRQ_EVENT_FRMENDSYNC = 0x00000002, // frame end ++ E_SCLIRQ_EVENT_CMDQGOING = 0x00000010, // CMDQ going ++ E_SCLIRQ_EVENT_CMDQIDLE = 0x00000020, // CMDQ idle ++ E_SCLIRQ_EVENT_CMDQDONE = 0x00000040, // CMDQ done ++ E_SCLIRQ_EVENT_CMDQTIMEOUT = 0x00000080, // timeout ++ E_SCLIRQ_EVENT_CMDQ = (E_SCLIRQ_EVENT_CMDQGOING|E_SCLIRQ_EVENT_CMDQIDLE|E_SCLIRQ_EVENT_CMDQDONE|E_SCLIRQ_EVENT_CMDQTIMEOUT), ++}SCLIRQRXEvent; ++ ++typedef enum ++{ ++ E_SCLIRQ_FRM_IN_COUNT_NOW = 0x1, // FRAMEIN NOW ++ E_SCLIRQ_FRM_IN_COUNT_DELAYONE = 0x2, // delay one ++ E_SCLIRQ_FRM_IN_COUNT_DELAYTWO = 0x4, // delay two ++}E_SCLIRQ_FRM_IN_COUNT_TYPE; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// extern Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// bclkforcemode ++/// use in Drvscldma and Drvhvsp ++/// if True ,can't dynamic set Clk ++//////////////// ++extern unsigned char gbclkforcemode; ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/vip/drvvip.c b/drivers/mstar/scl/infinity/src/mxlib/drv/vip/drvvip.c +new file mode 100644 +index 00000000..bec9da85 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/vip/drvvip.c +@@ -0,0 +1,550 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. 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If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_VIP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "hwreg.h" ++#include "drvvip.h" ++#include "halvip.h" ++#include "mdrv_scl_dbg.h" ++#include "drvCMDQ.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_VIP_DBG 0 ++#define DRV_VIP_LDC_DMAP_align(x,align) ((x+align) & ~(align-1)) ++#define DMAPBLOCKUNIT 32 ++#define DMAPBLOCKUNITBYTE 4 ++#define DMAPBLOCKALIGN 4 ++#define DEFAULTLDCMD 0x1 ++#define SRAMNORMAL 0 ++#define SRAMFORSCALINGUP 1 ++ ++#define DLCVariableSection 8 ++#define DLCCurveFitEnable 7 ++#define DLCCurveFitRGBEnable 13 ++#define DLCDitherEnable 5 ++#define DLCHistYRGBEnable 10 ++#define DLCStaticEnable 1 ++#define LDCFBRWDiff 4 ++#define LDCSWModeEnable 10 ++#define LDCAppointFBidx 2 ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_S32 _VIP_Mutex = -1; ++//------------------------------------------------------------------------------------------------- ++// Loacl Functions ++//------------------------------------------------------------------------------------------------- ++MS_U16 _Drv_VIP_GetDLCEnableSetting(ST_VIP_DLC_HISTOGRAM_CONFIG stDLCCfg) ++{ ++ MS_U16 u16valueForReg1Eh04; ++ u16valueForReg1Eh04 = ((MS_U16)stDLCCfg.bVariable_Section<>4,0xFFFF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_19_L,(MS_U16)stDLCCfg.u32StatBase[0]>>20,0x07FF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_1A_L,(MS_U16)stDLCCfg.u32StatBase[1]>>4,0xFFFF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_1B_L,(MS_U16)stDLCCfg.u32StatBase[1]>>20,0x07FF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_DLC_08_L,stDLCCfg.bRange<<7,0x0080,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_01_L,stDLCCfg.u16Vst,0x03FF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_02_L,stDLCCfg.u16Vnd,0x03FF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_03_L,stDLCCfg.u16Hst,0x01FF,stDLCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_VIP_MWE_04_L,stDLCCfg.u16Vnd,0x01FF,stDLCCfg.stFCfg.u8framecnt); ++ ++ _Drv_VIP_For_SetDLCHistRangeEachSection(stDLCCfg); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++} ++void _Drv_VIP_SetDLCHistogramRIUConfig(ST_VIP_DLC_HISTOGRAM_CONFIG stDLCCfg,MS_U16 u16valueForReg1Eh04) ++{ ++ Hal_VIP_DLCHistVarOnOff(u16valueForReg1Eh04); ++ Hal_VIP_SetDLCstatMIU(stDLCCfg.bstat_MIU,stDLCCfg.u32StatBase[0],stDLCCfg.u32StatBase[1]); ++ Hal_VIP_SetDLCshift(stDLCCfg.u8HistSft); ++ HAl_VIP_SetDLCmode(stDLCCfg.u8trig_ref_mode); ++ Hal_VIP_SetDLCActWin(stDLCCfg.bRange,stDLCCfg.u16Vst,stDLCCfg.u16Hst,stDLCCfg.u16Vnd,stDLCCfg.u16Hnd); ++ _Drv_VIP_For_SetDLCHistRangeEachSection(stDLCCfg); ++} ++ST_VIP_DLC_HISTOGRAM_REPORT _Drv_VIP_GetDLCHistogramConfig(void) ++{ ++ ST_VIP_DLC_HISTOGRAM_REPORT stdlc; ++ stdlc.u32PixelCount = Hal_VIP_DLCGetPC(); ++ stdlc.u32PixelWeight = Hal_VIP_DLCGetPW(); ++ stdlc.u8Baseidx = Hal_VIP_DLCGetBaseidx(); ++ stdlc.u8MaxPixel = Hal_VIP_DLCGetMaxP(); ++ stdlc.u8MinPixel = Hal_VIP_DLCGetMinP(); ++ return stdlc; ++} ++MS_U8 _Drv_VIP_GetLDCFrameBufferSetting(ST_VIP_LDC_MD_CONFIG stLDCCfg) ++{ ++ return (MS_U8)((stLDCCfg.u8FBrwdiff<>16)),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_0C_L,((MS_U16)u32DMAP_pitch),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_0E_L,((MS_U16)stLDCCfg.bEnPowerSave)<<6| ++ ((MS_U16)stLDCCfg.u8DMAPoffset),0x007F,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++} ++void _Drv_VIP_SetLDCDmap(ST_VIP_LDC_DMAP_CONFIG stLDCCfg,MS_U32 u32DMAP_pitch) ++{ ++ Hal_VIP_SetLDCDmapBase(stLDCCfg.u32DMAPaddr); ++ Hal_VIP_SetLDCDmapPitch(u32DMAP_pitch); ++ Hal_VIP_SetLDCDmapOffset(stLDCCfg.u8DMAPoffset); ++ Hal_VIP_SetLDCDmapPS(stLDCCfg.bEnPowerSave); ++} ++void _Drv_VIP_SetLDCSRAMCfgByCMDQ(ST_VIP_LDC_SRAM_CONFIG stLDCCfg) ++{ ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_22_L,((MS_U16)stLDCCfg.u16SRAMhoramount),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_2A_L,((MS_U16)stLDCCfg.u16SRAMveramount),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_24_L,((MS_U16)(stLDCCfg.u32loadhoraddr>>4)),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_25_L,((MS_U16)(stLDCCfg.u32loadhoraddr>>20)),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_2C_L,((MS_U16)(stLDCCfg.u32loadveraddr>>4)),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_2D_L,((MS_U16)(stLDCCfg.u32loadveraddr>>20)),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_23_L,((MS_U16)stLDCCfg.u16SRAMhorstr),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_AssignFrameWriteCmd ++ (REG_SCL_LDC_2B_L,((MS_U16)stLDCCfg.u16SRAMverstr),0xFFFF,stLDCCfg.stFCfg.u8framecnt); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++} ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_VIP_Init(ST_VIP_INIT_CONFIG *pCfg) ++{ ++ char word[] = {"_VIP_Mutex"}; ++ ++ if(_VIP_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s already done\n", __FUNCTION__); ++ return TRUE; ++ } ++ ++ _VIP_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ ++ if (_VIP_Mutex == -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s create mutex fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ Hal_VIP_Set_Riu_Base(pCfg->u32RiuBase); ++ ++ ++ return TRUE; ++} ++void Drv_VIPLDCInit(void) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s: ", __FUNCTION__); ++ Hal_VIP_SetLDC422_444_allMd(DEFAULTLDCMD); ++} ++void Drv_VIP_SRAM_Dump(void) ++{ ++ Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_IHC,SRAMNORMAL); ++ Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_ICC,SRAMNORMAL); ++ Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_HVSP,SRAMFORSCALINGUP); ++ Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_HVSP_1,SRAMNORMAL); ++ Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_HVSP_2,SRAMNORMAL); ++} ++MS_BOOL Drv_VIP_GetCMDQHWDone(void) ++{ ++ return Drv_HVSP_GetCMDQDoneStatus(); ++} ++ ++wait_queue_head_t * Drv_VIP_GetWaitQueueHead(void) ++{ ++ return Drv_HVSP_GetWaitQueueHead(); ++} ++ ++void Drv_VIP_SetDNRIPMRead(MS_BOOL bEn) ++{ ++ Hal_VIP_SetDNRIPMRead(bEn); ++} ++unsigned char Drv_VIP_SetNLMSRAMConfig(ST_VIP_NLM_SRAM_CONFIG stCfg) ++{ ++ if(stCfg.bCLientEn) ++ { ++ _Drv_VIP_SetNLMSRAMbyAutodownload(stCfg); ++ } ++ else ++ { ++ _Drv_VIP_SetNLMSRAMbyCPU(stCfg); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_CONFIG stDLCCfg) ++{ ++ MS_U16 u16valueForReg1Eh04; ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s: ", __FUNCTION__); ++ u16valueForReg1Eh04 = _Drv_VIP_GetDLCEnableSetting(stDLCCfg); ++ if(stDLCCfg.stFCfg.bEn) ++ { ++ _Drv_VIP_SetDLCHistogramCMDQConfig(stDLCCfg,u16valueForReg1Eh04); ++ } ++ else ++ { ++ _Drv_VIP_SetDLCHistogramRIUConfig(stDLCCfg,u16valueForReg1Eh04); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), ++ "[DRVVIP]u16valueForReg1Eh04:%hx ,stDLCCfg.u32StatBase[0]:%lx,stDLCCfg.u32StatBase[1]%lx,stDLCCfg.bstat_MIU:%hhd\n" ++ ,u16valueForReg1Eh04,stDLCCfg.u32StatBase[0],stDLCCfg.u32StatBase[1],stDLCCfg.bstat_MIU); ++ } ++ ++ return TRUE; ++} ++ ++MS_U32 Drv_VIP_GetDLCHistogramReport(MS_U16 u16range) ++{ ++ MS_U32 u32value; ++ u32value = Hal_VIP_DLC_Hist_GetRange(u16range); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s Histogram_%hd:%lx \n", __FUNCTION__,u16range,u32value); ++ return u32value; ++} ++ST_VIP_DLC_HISTOGRAM_REPORT Drv_VIP_GetDLCHistogramConfig(void) ++{ ++ ST_VIP_DLC_HISTOGRAM_REPORT stdlc; ++ stdlc = _Drv_VIP_GetDLCHistogramConfig(); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s PixelCount:%lx,PixelWeight:%lx,Baseidx:%hhx \n" ++ ,__FUNCTION__, stdlc.u32PixelCount,stdlc.u32PixelWeight,stdlc.u8Baseidx); ++ return stdlc; ++} ++MS_BOOL Drv_VIP_SetLDCMdConfig(ST_VIP_LDC_MD_CONFIG stLDCCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ if(stLDCCfg.stFCfg.bEn) ++ { ++ _Drv_VIP_SetLDCFrameBufferConfigByCMDQ(stLDCCfg); ++ } ++ else ++ { ++ _Drv_VIP_SetLDCFrameBufferConfig(stLDCCfg); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetLDCOnConfig(MS_BOOL bEn) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s: bEn:%hhd\n", __FUNCTION__,bEn); ++ Hal_VIP_SetLDCBypass(!bEn); ++ Drv_HVSP_SetLDCONOFF(bEn); ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetLDCDmapConfig(ST_VIP_LDC_DMAP_CONFIG stLDCCfg) ++{ ++ MS_U32 u32DMAP_pitch =_Drv_VIP_GetLDCDmapPitch(stLDCCfg); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), ++ "[DRVVIP]%s DMAP_pitch:%lx,DMAPaddr:%lx \n",__FUNCTION__,u32DMAP_pitch,stLDCCfg.u32DMAPaddr); ++ if(stLDCCfg.stFCfg.bEn) ++ { ++ _Drv_VIP_Set_LDCDmapByCMDQ(stLDCCfg,u32DMAP_pitch); ++ } ++ else ++ { ++ _Drv_VIP_SetLDCDmap(stLDCCfg,u32DMAP_pitch); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetLDCSRAMConfig(ST_VIP_LDC_SRAM_CONFIG stLDCCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s loadhoraddr:%lx,loadveraddr:%lx \n" ++ ,__FUNCTION__,stLDCCfg.u32loadhoraddr,stLDCCfg.u32loadveraddr); ++ if(stLDCCfg.stFCfg.bEn) ++ { ++ _Drv_VIP_SetLDCSRAMCfgByCMDQ(stLDCCfg); ++ } ++ else ++ { ++ Hal_VIP_SetLDCSramAmount(stLDCCfg.u16SRAMhoramount,stLDCCfg.u16SRAMveramount); ++ Hal_VIP_SetLDCSramBase(stLDCCfg.u32loadhoraddr,stLDCCfg.u32loadveraddr); ++ Hal_VIP_SetLDCSramStr(stLDCCfg.u16SRAMhorstr,stLDCCfg.u16SRAMverstr); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackSetPayloadData(u16Timecode, u8OperatorID); ++ return 1; ++} ++MS_BOOL Drv_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackSetKey(bUserDefinded, pu8Setting); ++ return 1; ++} ++MS_BOOL Drv_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackSetUserDefindedSetting(bUserDefinded, pu8Setting); ++ return 1; ++} ++MS_BOOL Drv_VIP_VtrackEnable( MS_U8 u8FrameRate, EN_VIP_DRVVTRACK_ENABLE_TYPE bEnable) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackEnable(u8FrameRate, bEnable); ++ return 1; ++} ++MS_BOOL Drv_VIP_GetBypassStatus(EN_VIP_DRV_CONFIG_TYPE enIPType) ++{ ++ MS_BOOL bRet; ++ switch(enIPType) ++ { ++ case EN_VIP_DRV_CONFIG: ++ bRet = Hal_VIP_GetVIPBypass(); ++ break; ++ ++ case EN_VIP_DRV_DNR_CONFIG: ++ bRet = Hal_VIP_GetDNRBypass(); ++ break; ++ ++ case EN_VIP_DRV_SNR_CONFIG: ++ bRet = Hal_VIP_GetSNRBypass(); ++ break; ++ ++ case EN_VIP_DRV_LDC_CONFIG: ++ bRet = Hal_VIP_GetLDCBypass(); ++ break; ++ ++ case EN_VIP_DRV_NLM_CONFIG: ++ bRet = Hal_VIP_GetNLMBypass(); ++ break; ++ default: ++ bRet = 0; ++ break; ++ } ++ return bRet; ++} ++#undef DRV_VIP_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/drv/vip/drvvip.h b/drivers/mstar/scl/infinity/src/mxlib/drv/vip/drvvip.h +new file mode 100644 +index 00000000..92393abc +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/drv/vip/drvvip.h +@@ -0,0 +1,291 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_VIP_H ++#define _DRV_VIP_H ++//============================================================================= ++// Defines ++//============================================================================= ++// ++#define VIP_DLC_HISTOGRAM_SECTION_NUM 7 ++#define VIP_DLC_HISTOGRAM_REPORT_NUM 8 ++#define VIP_NLM_ENTRY_NUM 1104 ++#define VIP_NLM_AUTODOWNLOAD_BASE_UNIT 16 ++#define VIP_NLM_AUTODOWNLOAD_CLIENT 9 ++// ++typedef enum ++{ ++ E_VIP_LDC_Drv_MENULOAD, ++ E_VIP_LDC_Drv_BYPASS, ++ E_VIP_LDC_BYPASS_Drv_TYPE_NUM, ++}EN_VIP_LDC_BYPASS_Drv_TYPE; ++// ++typedef enum ++{ ++ EN_VIP_DRVVTRACK_ENABLE_ON, ++ EN_VIP_DRVVTRACK_ENABLE_OFF, ++ EN_VIP_DRVVTRACK_ENABLE_DEBUG, ++}EN_VIP_DRVVTRACK_ENABLE_TYPE; ++typedef enum ++{ ++ EN_VIP_DRV_ACK_CONFIG = 0x1, ///< ACK ++ EN_VIP_DRV_IBC_CONFIG = 0x2, ///< IBC ++ EN_VIP_DRV_IHCICC_CONFIG = 0x4, ///< ICCIHC ++ EN_VIP_DRV_ICC_CONFIG = 0x8, ///< ICE ++ EN_VIP_DRV_IHC_CONFIG = 0x10, ///< IHC ++ EN_VIP_DRV_FCC_CONFIG = 0x20, ///< FCC ++ EN_VIP_DRV_UVC_CONFIG = 0x40, ///< UVC ++ EN_VIP_DRV_DLC_CONFIG = 0x80, ///< DLC ++ EN_VIP_DRV_DLC_HISTOGRAM_CONFIG = 0x100, ///< HIST ++ EN_VIP_DRV_LCE_CONFIG = 0x200, ///< LCE ++ EN_VIP_DRV_PEAKING_CONFIG = 0x400, ///< PK ++ EN_VIP_DRV_NLM_CONFIG = 0x800, ///< NLM ++ EN_VIP_DRV_LDC_MD_CONFIG = 0x1000, ///< LDCMD ++ EN_VIP_DRV_LDC_DMAP_CONFIG = 0x2000, ///< LDCDMAP ++ EN_VIP_DRV_LDC_SRAM_CONFIG = 0x4000, ///< LDC SRAM ++ EN_VIP_DRV_LDC_CONFIG = 0x8000, ///< LDC ++ EN_VIP_DRV_DNR_CONFIG = 0x10000, ///< DNR ++ EN_VIP_DRV_SNR_CONFIG = 0x20000, ///< SNR ++ EN_VIP_DRV_CONFIG = 0x40000, ///< 19 bit to control 19 IOCTL ++}EN_VIP_DRV_CONFIG_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++// IOCTL_VIP_SET_DNR_CONFIG ++typedef struct ++{ ++ unsigned char bEn; ++ unsigned char u8framecnt; ++}ST_VIP_FC_CONFIG; ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++}ST_VIP_INIT_CONFIG; ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++ MS_U32 u32CMDQ_Phy; ++ MS_U32 u32CMDQ_Size; ++ MS_U32 u32CMDQ_Vir; ++}ST_VIP_OPEN_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32baseadr; ++ MS_U16 u16depth; ++ MS_U16 u16reqlen; ++ MS_BOOL bCLientEn; ++ MS_BOOL btrigContinue; ++ MS_U16 u16iniaddr; ++ MS_U32 u32viradr; ++}ST_VIP_NLM_SRAM_CONFIG; ++ ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned char u8FBidx; ++ unsigned char u8FBrwdiff; ++ unsigned char bEnSWMode; ++ EN_VIP_LDC_BYPASS_Drv_TYPE enbypass; ++}ST_VIP_LDC_MD_CONFIG; ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned long u32DMAPaddr; ++ unsigned short u16DMAPWidth; ++ unsigned char u8DMAPoffset; ++ unsigned char bEnPowerSave; ++}ST_VIP_LDC_DMAP_CONFIG; ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned long u32loadhoraddr; ++ unsigned short u16SRAMhorstr; ++ unsigned short u16SRAMhoramount; ++ unsigned long u32loadveraddr; ++ unsigned short u16SRAMverstr; ++ unsigned short u16SRAMveramount; ++}ST_VIP_LDC_SRAM_CONFIG; ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned char bVariable_Section;//1E04 ++ unsigned char bstatic; //1E04 ++ unsigned char bcurve_fit_en;//1E04 ++ unsigned char bhis_y_rgb_mode_en;//1E04 ++ unsigned char bcurve_fit_rgb_en;//1E04 ++ unsigned char bDLCdither_en;//1E04 ++ unsigned char u8Histogram_Range[VIP_DLC_HISTOGRAM_SECTION_NUM]; ++ unsigned char bstat_MIU; ++ unsigned char bRange; ++ unsigned short u16Vst; ++ unsigned short u16Vnd; ++ unsigned short u16Hst; ++ unsigned short u16Hnd; ++ unsigned char u8HistSft; ++ unsigned char u8trig_ref_mode; ++ unsigned long u32StatBase[2]; ++}ST_VIP_DLC_HISTOGRAM_CONFIG; ++ ++//IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ++typedef struct ++{ ++ unsigned int u32Histogram[VIP_DLC_HISTOGRAM_REPORT_NUM]; ++ unsigned long u32PixelWeight; ++ unsigned long u32PixelCount; ++ unsigned char u8MinPixel; ++ unsigned char u8MaxPixel; ++ unsigned char u8Baseidx; ++}ST_VIP_DLC_HISTOGRAM_REPORT; ++ ++//IOCTL_VIP_SET_FCC_ADP_YWIN_CONFIG ++ ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned long u32Addr; ++ unsigned short u16Data; ++ unsigned short u16Mask; ++ unsigned char u8framecnt; ++ unsigned char bfire; ++ unsigned char bCnt; ++}ST_VIP_CMDQ_CONFIG; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_VIP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE MS_BOOL Drv_VIP_SetLDCOnConfig(MS_BOOL bEn); ++INTERFACE ST_VIP_DLC_HISTOGRAM_REPORT Drv_VIP_GetDLCHistogramConfig(void); ++INTERFACE MS_BOOL Drv_VIP_Init(ST_VIP_INIT_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_VIP_SetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_CONFIG stDLCCfg); ++INTERFACE MS_U32 Drv_VIP_GetDLCHistogramReport(MS_U16 u16range); ++INTERFACE MS_BOOL Drv_VIP_SetLDCMdConfig(ST_VIP_LDC_MD_CONFIG stLDCCfg); ++INTERFACE MS_BOOL Drv_VIP_SetLDCDmapConfig(ST_VIP_LDC_DMAP_CONFIG stLDCCfg); ++INTERFACE MS_BOOL Drv_VIP_SetLDCSRAMConfig(ST_VIP_LDC_SRAM_CONFIG stLDCCfg); ++INTERFACE void Drv_VIPLDCInit(void); ++INTERFACE void Drv_VIP_DNR_Init(void); ++INTERFACE void Drv_VIP_PK_Init(void); ++INTERFACE void Drv_VIP_DLC_Init(void); ++INTERFACE void Drv_VIP_UVC_Init(void); ++INTERFACE void Drv_VIP_ICE_Init(void); ++INTERFACE void Drv_VIP_IHC_Init(void); ++INTERFACE void Drv_VIP_FCC_Init(void); ++INTERFACE void Drv_VIP_LCE_Init(void); ++INTERFACE unsigned char Drv_VIP_SetNLMSRAMConfig(ST_VIP_NLM_SRAM_CONFIG stCfg); ++INTERFACE void Drv_VIP_SRAM_Dump(void); ++INTERFACE void Drv_VIP_SetDNRIPMRead(MS_BOOL bEn); ++INTERFACE MS_BOOL Drv_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID); ++INTERFACE MS_BOOL Drv_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE MS_BOOL Drv_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE MS_BOOL Drv_VIP_VtrackEnable( MS_U8 u8FrameRate, EN_VIP_DRVVTRACK_ENABLE_TYPE bEnable); ++INTERFACE MS_BOOL Drv_VIP_GetBypassStatus(EN_VIP_DRV_CONFIG_TYPE enIPType); ++INTERFACE wait_queue_head_t * Drv_VIP_GetWaitQueueHead(void); ++INTERFACE MS_BOOL Drv_VIP_GetCMDQHWDone(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/halCMDQ.c b/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/halCMDQ.c +new file mode 100644 +index 00000000..885dedcc +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/halCMDQ.c +@@ -0,0 +1,379 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// file halCMDQ.c ++// @brief CMDQ HAL ++// @author MStar Semiconductor,Inc. ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++#include "MsCommon.h" ++#include "MsTypes.h" ++ ++ ++#include "regCMDQ.h" ++#include "drvCMDQ.h" ++#include "halCMDQ.h" ++ ++#define CMDQDBG(x) ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Driver Compiler Option ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Macro of bit operations ++//-------------------------------------------------------------------------------------------------- ++MS_U32 _CMDQ_RIU_BASE; ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Inline Function ++//-------------------------------------------------------------------------------------------------- ++ ++void Hal_CMDQ_InitRIUBase(MS_U32 u32PM_riu_base) ++{ ++ _CMDQ_RIU_BASE = u32PM_riu_base ; ++} ++ ++//--------------------------------------------------------------------------- ++///set the element of _CMDQCtrl ++/// .CMDQ_Enable ++/// .CMDQ_Length_ReadMode ++/// .CMDQ_Mask_Setting ++//--------------------------------------------------------------------------- ++void Hal_CMDQ_Enable(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ if(bEn) ++ { ++ W2BYTEMSK(REG_CMDQ_01_L, 0x01, 0x01); ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_CMDQ_01_L, 0x00, 0x01); ++ ++ } ++ ++} ++void Hal_CMDQ_SetBaseEn(EN_CMDQ_IP_TYPE enIPType, MS_BOOL bEn) ++{ ++ if(bEn) ++ { ++ W2BYTEMSK(REG_CMDQ_01_L, 0x01, 0x01); ++ W2BYTEMSK(REG_CMDQ_11_L, 0x190d, 0x1FFF); ++ W2BYTEMSK(REG_CMDQ_20_L, 0x0080, 0x0080); ++ } ++ else ++ { ++ ++ W2BYTEMSK(REG_CMDQ_11_L, 0x00, 0x10FF); ++ W2BYTEMSK(REG_CMDQ_20_L, 0x00, 0x0080); ++ } ++ ++} ++ ++ ++//--------------------------------------------------------------------------- ++///set the element of _CMDQCtrl ++/// .CMDQ_En_Clk_Miu ++//--------------------------------------------------------------------------- ++void Hal_CMDQ_Reset(EN_CMDQ_IP_TYPE enIPType, MS_BOOL bEn) ++{ ++ if(bEn) ++ { ++ W2BYTEMSK(REG_CMDQ_31_L, 0x00, 0x01); ++ } ++ else ++ { ++ W2BYTEMSK(REG_CMDQ_31_L, 0x01, 0x01); ++ } ++} ++void Hal_CMDQ_SetTrigAlways(EN_CMDQ_IP_TYPE enIPType, MS_BOOL bEn) ++{ ++ if(bEn) ++ W2BYTEMSK(REG_CMDQ_02_L, 0x00, 0x01); ++ else ++ W2BYTEMSK(REG_CMDQ_02_L, 0x01, 0x01); ++} ++MS_BOOL Hal_CMDQ_SetDMAMode(EN_CMDQ_IP_TYPE enIPType,int ModeSel) ++{ ++ if (ModeSel==1) ++ { ++ W2BYTEMSK(REG_CMDQ_02_L, 0x00, 0x02); ++ return TRUE; ++ } ++ else if(ModeSel==0) ++ { ++ W2BYTEMSK(REG_CMDQ_02_L, 0x01, 0x02); ++ return TRUE; ++ } ++ else ++ { ++ W2BYTEMSK(REG_CMDQ_02_L, 0x04, 0x04); ++ return TRUE; ++ } ++} ++ ++void Hal_CMDQ_SetStartPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr) ++{ ++ MS_U32 temp; ++ ++ temp=(MS_U32)(StartAddr); ++ temp=temp/16; ++ W4BYTE(REG_CMDQ_04_L,temp); ++} ++ ++void Hal_CMDQ_SetEndPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 EndAddr) ++{ ++ MS_U32 temp; ++ ++ temp=(MS_U32)(EndAddr); ++ temp=temp/16; ++ W4BYTE(REG_CMDQ_06_L,temp); ++} ++ ++void Hal_CMDQ_SetOffsetPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 OffsetAddr) ++{ ++ MS_U32 temp; ++ ++ temp=(MS_U32)(OffsetAddr); ++ temp=temp>>4; ++ CMDQDBG(printf("End_Pointer _bits:%lx\n", temp)); ++ W4BYTE(REG_CMDQ_08_L,temp); ++} ++ ++void Hal_CMDQ_SetTimer(EN_CMDQ_IP_TYPE enIPType,MS_U32 time) ++{ ++ W2BYTEMSK(REG_CMDQ_4A_L, time, 0xFFFF); ++} ++ ++void Hal_CMDQ_SetRatio(EN_CMDQ_IP_TYPE enIPType,MS_U32 Ratio) ++{ ++ W2BYTEMSK(REG_CMDQ_4B_L, Ratio, 0x00FF); ++} ++void Hal_CMDQ_Set_Waittrig(EN_CMDQ_IP_TYPE enIPType,MS_U16 trig) ++{ ++ W2BYTEMSK(REG_CMDQ_22_L, trig, 0x00FF); ++} ++void Hal_CMDQ_SetSkipPollWhenWaitTimeout(EN_CMDQ_IP_TYPE enIPType,MS_BOOL ben) ++{ ++ if(ben) ++ W2BYTEMSK(REG_CMDQ_29_L, 0x0080, 0x0080); ++ else ++ W2BYTEMSK(REG_CMDQ_29_L, 0x0000, 0x0080); ++} ++void Hal_CMDQ_SetTimeoutAmount(EN_CMDQ_IP_TYPE enIPType) ++{ ++ W2BYTEMSK(REG_CMDQ_28_L, (MS_U16)(CMDQ_base_amount&0xFFFF), 0xFFFF); ++ W2BYTEMSK(REG_CMDQ_29_L, (MS_U16)((CMDQ_base_amount>>16) &0xF), 0x000F); ++ W2BYTEMSK(REG_CMDQ_29_L, (MS_U16)(CMDQ_timeout_amount <<8), 0xFF00); ++ ++} ++void Hal_CMDQ_ClearIRQByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16IRQ) ++{ ++ W2BYTEMSK(REG_CMDQ_48_L, u16IRQ, 0xFFFF); ++} ++void Hal_CMDQ_ResetSoftInterrupt(EN_CMDQ_IP_TYPE enIPType) ++{ ++ W2BYTEMSK(REG_CMDQ_48_L, 0xFFFF, 0xFFFF); ++ W2BYTEMSK(REG_CMDQ_48_L, 0x0, 0xFFFF); ++} ++ ++void Hal_CMDQ_SetISRMSK(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Msk) ++{ ++ W2BYTEMSK(REG_CMDQ_47_L, u16Msk, 0xFFFF); ++} ++ ++void Hal_CMDQ_WriteRegDirect(MS_U32 u32Addr,MS_U16 u16Data) ++{ ++ W2BYTE(u32Addr, u16Data); ++} ++void Hal_CMDQ_WriteRegMaskDirect(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask) ++{ ++ W2BYTEMSK(u32Addr,u16Data,u16Mask); ++ ++} ++MS_U16 Hal_CMDQ_Get_ISP_Cnt(void) ++{ ++ MS_U16 isp_cnt; ++ MS_U32 reg; ++ reg=0x1302f4; ++ isp_cnt=R2BYTE(reg); ++ return isp_cnt; ++} ++//--------------------------------------------------------------------------- ++///Trigger for update start pointer and end pointer ++//--------------------------------------------------------------------------- ++void Hal_CMDQ_Start(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ if (bEn) ++ { ++ W2BYTEMSK(REG_CMDQ_03_L, 0x0002, 0x0002); ++ } ++ ++} ++MS_U32 Hal_CMDQ_GetMIUReadAddr(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 reg_value=0; ++ W2BYTEMSK(REG_CMDQ_03_L,0x0100 , 0x0100); ++ reg_value=R4BYTE(REG_CMDQ_0A_L); ++ return reg_value; ++} ++ ++//--------------------------------------------------------------------------- ++///Set Previous Dummy Register bit to be 1(which means this CAF is already write to DRAM) ++//--------------------------------------------------------------------------- ++MS_U32 Hal_CMDQ_ErrorCommand(EN_CMDQ_IP_TYPE enIPType,MS_U32 select_bit) ++{ ++ MS_U32 reg_value=0; ++ W2BYTEMSK(REG_CMDQ_43_L,select_bit , 0x0007); ++ reg_value= R2BYTE(REG_CMDQ_40_L); ++ return reg_value; ++ ++} ++ ++void Hal_CMDQ_Setmiusel(EN_CMDQ_IP_TYPE enIPType, MS_U8 u8MIUSel) ++{ ++ if (u8MIUSel == 0) ++ { ++ W2BYTEMSK(REG_CMDQ_10_L, 0x0000, 0x0002); ++ } ++ else ++ { ++ W2BYTEMSK(REG_CMDQ_10_L, 0x0002, 0x0002); ++ } ++} ++#if CMDQ_nonuse_Function ++/* ++MS_U32 Hal_CMDQ_Read_Start_Pointer(void) ++{ ++ MS_U32 reg_value=0; ++ reg_value=R4BYTE(REG_CMDQ_04_L); ++ return reg_value; ++} ++ ++MS_U32 Hal_CMDQ_Read_End_Pointer(void) ++{ ++ MS_U32 reg_value=0; ++ reg_value=R4BYTE(REG_CMDQ_06_L); ++ return reg_value; ++} ++*/ ++void Hal_CMDQ_Reset_Start_Pointer_bit(EN_CMDQ_IP_TYPE enIPType) ++{ ++ W2BYTEMSK(REG_CMDQ_03_L, 0x0004, 0x0004); ++} ++MS_U16 Hal_CMDQ_get_status(EN_CMDQ_IP_TYPE enIPType) ++{ ++ return ((R2BYTE(REG_CMDQ_01_L) & 0x0001)); ++} ++MS_BOOL Hal_CMDQ_Get_LDCtirg(void) ++{ ++ MS_U16 trig; ++ MS_BOOL ret; ++ trig=(R2BYTE(0x12183E)&0x0800)>>11; ++ ret= trig == 0x1 ? 0 :1; ++ return ret; ++} ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/halCMDQ.h b/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/halCMDQ.h +new file mode 100644 +index 00000000..3618ea1f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/halCMDQ.h +@@ -0,0 +1,164 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-20012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// file halCMDQ.h ++// @brief CMDQ HAL ++// @author MStar Semiconductor,Inc. ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef __HAL_CMDQ_H__ ++#define __HAL_CMDQ_H__ ++ ++ ++ ++// Trigger Bus inverse mask ++#define isp2cmdq_frame_done 0xFFFE // 0 ++#define isp2cmdq_vs_r 0xFFFD // 1 ++#define sc2cmdq_lv_trig 0xFFFB // 2 ++#define cmdq_dma_finished 0xFFF7 // 3 ++ ++ ++#define MS_CMDQ_NONFRAMECOUNT_PERCENT 8 // 1/8=12.5% ++#define MS_CMDQ_CMD_LEN 8 // 8byte =64bit ++#define MS_CMDQ_MEM_BASE_UNIT 16 // MIU 128bit ++#define MS_CMDQ_CMD_ALIGN 2 // (cmd/membase) ++#define MS_CMDQ_END_CMD 0x100802010000FFFE // nonuse ++#define MS_CMDQ_NULL_CMD 0x000000000000FFFF // null cmd ++#define MS_CMDQ_NULLTEST_CMD 0x00000000FFFFFFFF // null cmd ++#define MS_CMDQ_WRITE_CMD 0x1000000000000000 // write base head ++#define MS_CMDQ_ALLNULL_CMD 0x0000000000000000 // clean ++#define MS_CMDQ_WAIT_CMD 0x2000000000000000 // wait base head ++#define MS_CMDQ_POLL_EQ_CMD 0x3000000000000000 // polleq base head ++#define MS_CMDQ_POLL_NEQ_CMD 0xB000000000000000 // pollneq base head ++ ++//-------------------------------------------------------------------------------------------------- ++//-------------------------------------------------------------------------------------------------- ++// Macro of bit operations ++//-------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////// ++// HAL ++//////////////////////////////////////////////// ++ ++; ++void Hal_CMDQ_SetBaseEn(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++void Hal_CMDQ_Reset(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++void Hal_CMDQ_SetTrigAlways(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_BOOL Hal_CMDQ_SetDMAMode(EN_CMDQ_IP_TYPE enIPType,int ModeSel); ++void Hal_CMDQ_SetStartPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr); ++void Hal_CMDQ_SetEndPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 EndAddr); ++void Hal_CMDQ_SetOffsetPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 OffsetAddr); ++void Hal_CMDQ_SetTimer(EN_CMDQ_IP_TYPE enIPType,MS_U32 time); ++void Hal_CMDQ_SetRatio(EN_CMDQ_IP_TYPE enIPType,MS_U32 Ratio); ++void Hal_CMDQ_Start(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_U32 Hal_CMDQ_ErrorCommand(EN_CMDQ_IP_TYPE enIPType,MS_U32 select_bit); ++void Hal_CMDQ_Setmiusel(EN_CMDQ_IP_TYPE enIPType, MS_U8 u8MIUSel); ++void Hal_CMDQ_InitRIUBase(MS_U32 u32PM_riu_base); ++void Hal_CMDQ_Enable(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_U32 Hal_CMDQ_GetMIUReadAddr(EN_CMDQ_IP_TYPE enIPType); ++void Hal_CMDQ_Set_Waittrig(EN_CMDQ_IP_TYPE enIPType,MS_U16 trig); ++void Hal_CMDQ_SetSkipPollWhenWaitTimeout(EN_CMDQ_IP_TYPE enIPType,MS_BOOL ben); ++void Hal_CMDQ_SetTimeoutAmount(EN_CMDQ_IP_TYPE enIPType); ++void Hal_CMDQ_WriteRegDirect(MS_U32 u32Addr,MS_U16 u16Data); ++void Hal_CMDQ_WriteRegMaskDirect(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask); ++MS_U16 Hal_CMDQ_Get_ISP_Cnt(void); ++void Hal_CMDQ_ResetSoftInterrupt(EN_CMDQ_IP_TYPE enIPType); ++void Hal_CMDQ_ClearIRQByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16IRQ); ++void Hal_CMDQ_Reset_Start_Pointer_bit(EN_CMDQ_IP_TYPE enIPType); ++MS_U16 Hal_CMDQ_get_status(EN_CMDQ_IP_TYPE enIPType); ++MS_BOOL Hal_CMDQ_Get_LDCtirg(void); ++void Hal_CMDQ_SetISRMSK(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Msk); ++ ++ ++#endif // #ifndef _CMDQ_REG_MCU_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/regCMDQ.h b/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/regCMDQ.h +new file mode 100644 +index 00000000..f3523130 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/cmdq/regCMDQ.h +@@ -0,0 +1,438 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-20012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// file: regCMDQ.h ++// Description: CMDQ Register Definition ++// @author MStar Semiconductor,Inc. ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _CMDQ_REG_MCU_H_ ++#define _CMDQ_REG_MCU_H_ ++#include "MsTypes.h" ++ ++ ++//#include "MsCommon.h" ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Compliation Option ++//-------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Harware Capability ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 _CMDQ_RIU_BASE; ++//============================================================= ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++#define RIU_READ_BYTE(addr) ( READ_BYTE( _CMDQ_RIU_BASE + (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( _CMDQ_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( _CMDQ_RIU_BASE + (addr), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( _CMDQ_RIU_BASE + (addr), val) ++ ++//============================================================= ++// Standard Form ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++ ++//============================================================= ++//CMDQ ++#define REG_CMDQ_BASE 0x112000 ++#ifndef REG_TABLE_END ++#define REG_TABLE_END 0xFFFF ++#endif ++ ++#define REG_CMDQ_00_L (REG_CMDQ_BASE + 0x00) ++#define REG_CMDQ_00_H (REG_CMDQ_BASE + 0x01) ++#define REG_CMDQ_01_L (REG_CMDQ_BASE + 0x02) ++#define REG_CMDQ_01_H (REG_CMDQ_BASE + 0x03) ++#define REG_CMDQ_02_L (REG_CMDQ_BASE + 0x04) ++#define REG_CMDQ_02_H (REG_CMDQ_BASE + 0x05) ++#define REG_CMDQ_03_L (REG_CMDQ_BASE + 0x06) ++#define REG_CMDQ_03_H (REG_CMDQ_BASE + 0x07) ++#define REG_CMDQ_04_L (REG_CMDQ_BASE + 0x08) ++#define REG_CMDQ_04_H (REG_CMDQ_BASE + 0x09) ++#define REG_CMDQ_05_L (REG_CMDQ_BASE + 0x0A) ++#define REG_CMDQ_05_H (REG_CMDQ_BASE + 0x0B) ++#define REG_CMDQ_06_L (REG_CMDQ_BASE + 0x0C) ++#define REG_CMDQ_06_H (REG_CMDQ_BASE + 0x0D) ++#define REG_CMDQ_07_L (REG_CMDQ_BASE + 0x0E) ++#define REG_CMDQ_07_H (REG_CMDQ_BASE + 0x0F) ++#define REG_CMDQ_08_L (REG_CMDQ_BASE + 0x10) ++#define REG_CMDQ_08_H (REG_CMDQ_BASE + 0x11) ++#define REG_CMDQ_09_L (REG_CMDQ_BASE + 0x12) ++#define REG_CMDQ_09_H (REG_CMDQ_BASE + 0x13) ++#define REG_CMDQ_0A_L (REG_CMDQ_BASE + 0x14) ++#define REG_CMDQ_0A_H (REG_CMDQ_BASE + 0x15) ++#define REG_CMDQ_0B_L (REG_CMDQ_BASE + 0x16) ++#define REG_CMDQ_0B_H (REG_CMDQ_BASE + 0x17) ++#define REG_CMDQ_0C_L (REG_CMDQ_BASE + 0x18) ++#define REG_CMDQ_0C_H (REG_CMDQ_BASE + 0x19) ++#define REG_CMDQ_0D_L (REG_CMDQ_BASE + 0x1A) ++#define REG_CMDQ_0D_H (REG_CMDQ_BASE + 0x1B) ++#define REG_CMDQ_0E_L (REG_CMDQ_BASE + 0x1C) ++#define REG_CMDQ_0E_H (REG_CMDQ_BASE + 0x1D) ++#define REG_CMDQ_0F_L (REG_CMDQ_BASE + 0x1E) ++#define REG_CMDQ_0F_H (REG_CMDQ_BASE + 0x1F) ++#define REG_CMDQ_10_L (REG_CMDQ_BASE + 0x20) ++#define REG_CMDQ_10_H (REG_CMDQ_BASE + 0x21) ++#define REG_CMDQ_11_L (REG_CMDQ_BASE + 0x22) ++#define REG_CMDQ_11_H (REG_CMDQ_BASE + 0x23) ++#define REG_CMDQ_12_L (REG_CMDQ_BASE + 0x24) ++#define REG_CMDQ_12_H (REG_CMDQ_BASE + 0x25) ++#define REG_CMDQ_13_L (REG_CMDQ_BASE + 0x26) ++#define REG_CMDQ_13_H (REG_CMDQ_BASE + 0x27) ++#define REG_CMDQ_14_L (REG_CMDQ_BASE + 0x28) ++#define REG_CMDQ_14_H (REG_CMDQ_BASE + 0x29) ++#define REG_CMDQ_15_L (REG_CMDQ_BASE + 0x2A) ++#define REG_CMDQ_15_H (REG_CMDQ_BASE + 0x2B) ++#define REG_CMDQ_16_L (REG_CMDQ_BASE + 0x2C) ++#define REG_CMDQ_16_H (REG_CMDQ_BASE + 0x2D) ++#define REG_CMDQ_17_L (REG_CMDQ_BASE + 0x2E) ++#define REG_CMDQ_17_H (REG_CMDQ_BASE + 0x2F) ++#define REG_CMDQ_18_L (REG_CMDQ_BASE + 0x30) ++#define REG_CMDQ_18_H (REG_CMDQ_BASE + 0x31) ++#define REG_CMDQ_19_L (REG_CMDQ_BASE + 0x32) ++#define REG_CMDQ_19_H (REG_CMDQ_BASE + 0x33) ++#define REG_CMDQ_1A_L (REG_CMDQ_BASE + 0x34) ++#define REG_CMDQ_1A_H (REG_CMDQ_BASE + 0x35) ++#define REG_CMDQ_1B_L (REG_CMDQ_BASE + 0x36) ++#define REG_CMDQ_1B_H (REG_CMDQ_BASE + 0x37) ++#define REG_CMDQ_1C_L (REG_CMDQ_BASE + 0x38) ++#define REG_CMDQ_1C_H (REG_CMDQ_BASE + 0x39) ++#define REG_CMDQ_1D_L (REG_CMDQ_BASE + 0x3A) ++#define REG_CMDQ_1D_H (REG_CMDQ_BASE + 0x3B) ++#define REG_CMDQ_1E_L (REG_CMDQ_BASE + 0x3C) ++#define REG_CMDQ_1E_H (REG_CMDQ_BASE + 0x3D) ++#define REG_CMDQ_1F_L (REG_CMDQ_BASE + 0x3E) ++#define REG_CMDQ_1F_H (REG_CMDQ_BASE + 0x3F) ++#define REG_CMDQ_20_L (REG_CMDQ_BASE + 0x40) ++#define REG_CMDQ_20_H (REG_CMDQ_BASE + 0x41) ++#define REG_CMDQ_21_L (REG_CMDQ_BASE + 0x42) ++#define REG_CMDQ_21_H (REG_CMDQ_BASE + 0x43) ++#define REG_CMDQ_22_L (REG_CMDQ_BASE + 0x44) ++#define REG_CMDQ_22_H (REG_CMDQ_BASE + 0x45) ++#define REG_CMDQ_23_L (REG_CMDQ_BASE + 0x46) ++#define REG_CMDQ_23_H (REG_CMDQ_BASE + 0x47) ++#define REG_CMDQ_24_L (REG_CMDQ_BASE + 0x48) ++#define REG_CMDQ_24_H (REG_CMDQ_BASE + 0x49) ++#define REG_CMDQ_25_L (REG_CMDQ_BASE + 0x4A) ++#define REG_CMDQ_25_H (REG_CMDQ_BASE + 0x4B) ++#define REG_CMDQ_26_L (REG_CMDQ_BASE + 0x4C) ++#define REG_CMDQ_26_H (REG_CMDQ_BASE + 0x4D) ++#define REG_CMDQ_27_L (REG_CMDQ_BASE + 0x4E) ++#define REG_CMDQ_27_H (REG_CMDQ_BASE + 0x4F) ++#define REG_CMDQ_28_L (REG_CMDQ_BASE + 0x50) ++#define REG_CMDQ_28_H (REG_CMDQ_BASE + 0x51) ++#define REG_CMDQ_29_L (REG_CMDQ_BASE + 0x52) ++#define REG_CMDQ_29_H (REG_CMDQ_BASE + 0x53) ++#define REG_CMDQ_2A_L (REG_CMDQ_BASE + 0x54) ++#define REG_CMDQ_2A_H (REG_CMDQ_BASE + 0x55) ++#define REG_CMDQ_2B_L (REG_CMDQ_BASE + 0x56) ++#define REG_CMDQ_2B_H (REG_CMDQ_BASE + 0x57) ++#define REG_CMDQ_2C_L (REG_CMDQ_BASE + 0x58) ++#define REG_CMDQ_2C_H (REG_CMDQ_BASE + 0x59) ++#define REG_CMDQ_2D_L (REG_CMDQ_BASE + 0x5A) ++#define REG_CMDQ_2D_H (REG_CMDQ_BASE + 0x5B) ++#define REG_CMDQ_2E_L (REG_CMDQ_BASE + 0x5C) ++#define REG_CMDQ_2E_H (REG_CMDQ_BASE + 0x5D) ++#define REG_CMDQ_2F_L (REG_CMDQ_BASE + 0x5E) ++#define REG_CMDQ_2F_H (REG_CMDQ_BASE + 0x5F) ++#define REG_CMDQ_30_L (REG_CMDQ_BASE + 0x60) ++#define REG_CMDQ_30_H (REG_CMDQ_BASE + 0x61) ++#define REG_CMDQ_31_L (REG_CMDQ_BASE + 0x62) ++#define REG_CMDQ_31_H (REG_CMDQ_BASE + 0x63) ++#define REG_CMDQ_32_L (REG_CMDQ_BASE + 0x64) ++#define REG_CMDQ_32_H (REG_CMDQ_BASE + 0x65) ++#define REG_CMDQ_33_L (REG_CMDQ_BASE + 0x66) ++#define REG_CMDQ_33_H (REG_CMDQ_BASE + 0x67) ++#define REG_CMDQ_34_L (REG_CMDQ_BASE + 0x68) ++#define REG_CMDQ_34_H (REG_CMDQ_BASE + 0x69) ++#define REG_CMDQ_35_L (REG_CMDQ_BASE + 0x6A) ++#define REG_CMDQ_35_H (REG_CMDQ_BASE + 0x6B) ++#define REG_CMDQ_36_L (REG_CMDQ_BASE + 0x6C) ++#define REG_CMDQ_36_H (REG_CMDQ_BASE + 0x6D) ++#define REG_CMDQ_37_L (REG_CMDQ_BASE + 0x6E) ++#define REG_CMDQ_37_H (REG_CMDQ_BASE + 0x6F) ++#define REG_CMDQ_38_L (REG_CMDQ_BASE + 0x70) ++#define REG_CMDQ_38_H (REG_CMDQ_BASE + 0x71) ++#define REG_CMDQ_39_L (REG_CMDQ_BASE + 0x72) ++#define REG_CMDQ_39_H (REG_CMDQ_BASE + 0x73) ++#define REG_CMDQ_3A_L (REG_CMDQ_BASE + 0x74) ++#define REG_CMDQ_3A_H (REG_CMDQ_BASE + 0x75) ++#define REG_CMDQ_3B_L (REG_CMDQ_BASE + 0x76) ++#define REG_CMDQ_3B_H (REG_CMDQ_BASE + 0x77) ++#define REG_CMDQ_3C_L (REG_CMDQ_BASE + 0x78) ++#define REG_CMDQ_3C_H (REG_CMDQ_BASE + 0x79) ++#define REG_CMDQ_3D_L (REG_CMDQ_BASE + 0x7A) ++#define REG_CMDQ_3D_H (REG_CMDQ_BASE + 0x7B) ++#define REG_CMDQ_3E_L (REG_CMDQ_BASE + 0x7C) ++#define REG_CMDQ_3E_H (REG_CMDQ_BASE + 0x7D) ++#define REG_CMDQ_3F_L (REG_CMDQ_BASE + 0x7E) ++#define REG_CMDQ_3F_H (REG_CMDQ_BASE + 0x7F) ++#define REG_CMDQ_40_L (REG_CMDQ_BASE + 0x80) ++#define REG_CMDQ_40_H (REG_CMDQ_BASE + 0x81) ++#define REG_CMDQ_41_L (REG_CMDQ_BASE + 0x82) ++#define REG_CMDQ_41_H (REG_CMDQ_BASE + 0x83) ++#define REG_CMDQ_42_L (REG_CMDQ_BASE + 0x84) ++#define REG_CMDQ_42_H (REG_CMDQ_BASE + 0x85) ++#define REG_CMDQ_43_L (REG_CMDQ_BASE + 0x86) ++#define REG_CMDQ_43_H (REG_CMDQ_BASE + 0x87) ++#define REG_CMDQ_44_L (REG_CMDQ_BASE + 0x88) ++#define REG_CMDQ_44_H (REG_CMDQ_BASE + 0x89) ++#define REG_CMDQ_45_L (REG_CMDQ_BASE + 0x8A) ++#define REG_CMDQ_45_H (REG_CMDQ_BASE + 0x8B) ++#define REG_CMDQ_46_L (REG_CMDQ_BASE + 0x8C) ++#define REG_CMDQ_46_H (REG_CMDQ_BASE + 0x8D) ++#define REG_CMDQ_47_L (REG_CMDQ_BASE + 0x8E) ++#define REG_CMDQ_47_H (REG_CMDQ_BASE + 0x8F) ++#define REG_CMDQ_48_L (REG_CMDQ_BASE + 0x90) ++#define REG_CMDQ_48_H (REG_CMDQ_BASE + 0x91) ++#define REG_CMDQ_49_L (REG_CMDQ_BASE + 0x92) ++#define REG_CMDQ_49_H (REG_CMDQ_BASE + 0x93) ++#define REG_CMDQ_4A_L (REG_CMDQ_BASE + 0x94) ++#define REG_CMDQ_4A_H (REG_CMDQ_BASE + 0x95) ++#define REG_CMDQ_4B_L (REG_CMDQ_BASE + 0x96) ++#define REG_CMDQ_4B_H (REG_CMDQ_BASE + 0x97) ++#define REG_CMDQ_4C_L (REG_CMDQ_BASE + 0x98) ++#define REG_CMDQ_4C_H (REG_CMDQ_BASE + 0x99) ++#define REG_CMDQ_4D_L (REG_CMDQ_BASE + 0x9A) ++#define REG_CMDQ_4D_H (REG_CMDQ_BASE + 0x9B) ++#define REG_CMDQ_4E_L (REG_CMDQ_BASE + 0x9C) ++#define REG_CMDQ_4E_H (REG_CMDQ_BASE + 0x9D) ++#define REG_CMDQ_4F_L (REG_CMDQ_BASE + 0x9E) ++#define REG_CMDQ_4F_H (REG_CMDQ_BASE + 0x9F) ++#define REG_CMDQ_50_L (REG_CMDQ_BASE + 0xA0) ++#define REG_CMDQ_50_H (REG_CMDQ_BASE + 0xA1) ++#define REG_CMDQ_51_L (REG_CMDQ_BASE + 0xA2) ++#define REG_CMDQ_51_H (REG_CMDQ_BASE + 0xA3) ++#define REG_CMDQ_52_L (REG_CMDQ_BASE + 0xA4) ++#define REG_CMDQ_52_H (REG_CMDQ_BASE + 0xA5) ++#define REG_CMDQ_53_L (REG_CMDQ_BASE + 0xA6) ++#define REG_CMDQ_53_H (REG_CMDQ_BASE + 0xA7) ++#define REG_CMDQ_54_L (REG_CMDQ_BASE + 0xA8) ++#define REG_CMDQ_54_H (REG_CMDQ_BASE + 0xA9) ++#define REG_CMDQ_55_L (REG_CMDQ_BASE + 0xAA) ++#define REG_CMDQ_55_H (REG_CMDQ_BASE + 0xAB) ++#define REG_CMDQ_56_L (REG_CMDQ_BASE + 0xAC) ++#define REG_CMDQ_56_H (REG_CMDQ_BASE + 0xAD) ++#define REG_CMDQ_57_L (REG_CMDQ_BASE + 0xAE) ++#define REG_CMDQ_57_H (REG_CMDQ_BASE + 0xAF) ++#define REG_CMDQ_58_L (REG_CMDQ_BASE + 0xB0) ++#define REG_CMDQ_58_H (REG_CMDQ_BASE + 0xB1) ++#define REG_CMDQ_59_L (REG_CMDQ_BASE + 0xB2) ++#define REG_CMDQ_59_H (REG_CMDQ_BASE + 0xB3) ++#define REG_CMDQ_5A_L (REG_CMDQ_BASE + 0xB4) ++#define REG_CMDQ_5A_H (REG_CMDQ_BASE + 0xB5) ++#define REG_CMDQ_5B_L (REG_CMDQ_BASE + 0xB6) ++#define REG_CMDQ_5B_H (REG_CMDQ_BASE + 0xB7) ++#define REG_CMDQ_5C_L (REG_CMDQ_BASE + 0xB8) ++#define REG_CMDQ_5C_H (REG_CMDQ_BASE + 0xB9) ++#define REG_CMDQ_5D_L (REG_CMDQ_BASE + 0xBA) ++#define REG_CMDQ_5D_H (REG_CMDQ_BASE + 0xBB) ++#define REG_CMDQ_5E_L (REG_CMDQ_BASE + 0xBC) ++#define REG_CMDQ_5E_H (REG_CMDQ_BASE + 0xBD) ++#define REG_CMDQ_5F_L (REG_CMDQ_BASE + 0xBE) ++#define REG_CMDQ_5F_H (REG_CMDQ_BASE + 0xBF) ++#define REG_CMDQ_60_L (REG_CMDQ_BASE + 0xC0) ++#define REG_CMDQ_60_H (REG_CMDQ_BASE + 0xC1) ++#define REG_CMDQ_61_L (REG_CMDQ_BASE + 0xC2) ++#define REG_CMDQ_61_H (REG_CMDQ_BASE + 0xC3) ++#define REG_CMDQ_62_L (REG_CMDQ_BASE + 0xC4) ++#define REG_CMDQ_62_H (REG_CMDQ_BASE + 0xC5) ++#define REG_CMDQ_63_L (REG_CMDQ_BASE + 0xC6) ++#define REG_CMDQ_63_H (REG_CMDQ_BASE + 0xC7) ++#define REG_CMDQ_64_L (REG_CMDQ_BASE + 0xC8) ++#define REG_CMDQ_64_H (REG_CMDQ_BASE + 0xC9) ++#define REG_CMDQ_65_L (REG_CMDQ_BASE + 0xCA) ++#define REG_CMDQ_65_H (REG_CMDQ_BASE + 0xCB) ++#define REG_CMDQ_66_L (REG_CMDQ_BASE + 0xCC) ++#define REG_CMDQ_66_H (REG_CMDQ_BASE + 0xCD) ++#define REG_CMDQ_67_L (REG_CMDQ_BASE + 0xCE) ++#define REG_CMDQ_67_H (REG_CMDQ_BASE + 0xCF) ++#define REG_CMDQ_68_L (REG_CMDQ_BASE + 0xD0) ++#define REG_CMDQ_68_H (REG_CMDQ_BASE + 0xD1) ++#define REG_CMDQ_69_L (REG_CMDQ_BASE + 0xD2) ++#define REG_CMDQ_69_H (REG_CMDQ_BASE + 0xD3) ++#define REG_CMDQ_6A_L (REG_CMDQ_BASE + 0xD4) ++#define REG_CMDQ_6A_H (REG_CMDQ_BASE + 0xD5) ++#define REG_CMDQ_6B_L (REG_CMDQ_BASE + 0xD6) ++#define REG_CMDQ_6B_H (REG_CMDQ_BASE + 0xD7) ++#define REG_CMDQ_6C_L (REG_CMDQ_BASE + 0xD8) ++#define REG_CMDQ_6C_H (REG_CMDQ_BASE + 0xD9) ++#define REG_CMDQ_6D_L (REG_CMDQ_BASE + 0xDA) ++#define REG_CMDQ_6D_H (REG_CMDQ_BASE + 0xDB) ++#define REG_CMDQ_6E_L (REG_CMDQ_BASE + 0xDC) ++#define REG_CMDQ_6E_H (REG_CMDQ_BASE + 0xDD) ++#define REG_CMDQ_6F_L (REG_CMDQ_BASE + 0xDE) ++#define REG_CMDQ_6F_H (REG_CMDQ_BASE + 0xDF) ++#define REG_CMDQ_70_L (REG_CMDQ_BASE + 0xE0) ++#define REG_CMDQ_70_H (REG_CMDQ_BASE + 0xE1) ++#define REG_CMDQ_71_L (REG_CMDQ_BASE + 0xE2) ++#define REG_CMDQ_71_H (REG_CMDQ_BASE + 0xE3) ++#define REG_CMDQ_72_L (REG_CMDQ_BASE + 0xE4) ++#define REG_CMDQ_72_H (REG_CMDQ_BASE + 0xE5) ++#define REG_CMDQ_73_L (REG_CMDQ_BASE + 0xE6) ++#define REG_CMDQ_73_H (REG_CMDQ_BASE + 0xE7) ++#define REG_CMDQ_74_L (REG_CMDQ_BASE + 0xE8) ++#define REG_CMDQ_74_H (REG_CMDQ_BASE + 0xE9) ++#define REG_CMDQ_75_L (REG_CMDQ_BASE + 0xEA) ++#define REG_CMDQ_75_H (REG_CMDQ_BASE + 0xEB) ++#define REG_CMDQ_76_L (REG_CMDQ_BASE + 0xEC) ++#define REG_CMDQ_76_H (REG_CMDQ_BASE + 0xED) ++#define REG_CMDQ_77_L (REG_CMDQ_BASE + 0xEE) ++#define REG_CMDQ_77_H (REG_CMDQ_BASE + 0xEF) ++#define REG_CMDQ_78_L (REG_CMDQ_BASE + 0xF0) ++#define REG_CMDQ_78_H (REG_CMDQ_BASE + 0xF1) ++#define REG_CMDQ_79_L (REG_CMDQ_BASE + 0xF2) ++#define REG_CMDQ_79_H (REG_CMDQ_BASE + 0xF3) ++#define REG_CMDQ_7A_L (REG_CMDQ_BASE + 0xF4) ++#define REG_CMDQ_7A_H (REG_CMDQ_BASE + 0xF5) ++#define REG_CMDQ_7B_L (REG_CMDQ_BASE + 0xF6) ++#define REG_CMDQ_7B_H (REG_CMDQ_BASE + 0xF7) ++#define REG_CMDQ_7C_L (REG_CMDQ_BASE + 0xF8) ++#define REG_CMDQ_7C_H (REG_CMDQ_BASE + 0xF9) ++#define REG_CMDQ_7D_L (REG_CMDQ_BASE + 0xFA) ++#define REG_CMDQ_7D_H (REG_CMDQ_BASE + 0xFB) ++#define REG_CMDQ_7E_L (REG_CMDQ_BASE + 0xFC) ++#define REG_CMDQ_7E_H (REG_CMDQ_BASE + 0xFD) ++#define REG_CMDQ_7F_L (REG_CMDQ_BASE + 0xFE) ++#define REG_CMDQ_7F_H (REG_CMDQ_BASE + 0xFF) ++ ++#define CMDQ_CRASH_15_0_BIT 0x0000 //0x43 bit:3 command[15:0] ++#define CMDQ_CRASH_31_16_BIT 0x0001 //0x43 bit:3 command[31:16] ++#define CMDQ_CRASH_55_32_BIT 0x0002 //0x43 bit:3 command[55:32] ++#define CMDQ_CRASH_63_56_BIT 0x0003 //0x43 bit:3 command[63:56] ++ ++ ++ ++#endif // #ifndef _CMDQ_REG_MCU_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/halCHIP.h b/drivers/mstar/scl/infinity/src/mxlib/hal/halCHIP.h +new file mode 100644 +index 00000000..5023077f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/halCHIP.h +@@ -0,0 +1,60 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_CHIP_H_ ++#define _HAL_CHIP_H_ ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define ARM_CLOCK_FREQ 900000000 ++#define AEON_CLOCK_FREQ 240000000 ++#define XTAL_CLOCK_FREQ 12000000 ++ ++#define HAL_MIU1_BASE 0x60000000 // 1512MB ++#define HAL_MIU1_BUS_BASE 0xA0000000 // MIU1 Low 256MB ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//void CHIP_InitISR(void); ++//MS_BOOL CHIP_InISRContext(void); ++//MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb); ++//MS_BOOL CHIP_DetachISR(InterruptNum eIntNum); ++//MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum); ++//MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum); ++//MS_BOOL CHIP_EnableAllInterrupt(void); ++//MS_BOOL CHIP_DisableAllInterrupt(void); ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _HAL_CHIP_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/halhvsp.c b/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/halhvsp.c +new file mode 100644 +index 00000000..98d13097 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/halhvsp.c +@@ -0,0 +1,1959 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_HVSP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include ++#include ++// Internal Definition ++#include "hwreg.h" ++#include "halhvsp_utility.h" ++#include "drvhvsp_st.h" ++#include "drvsclirq.h" ++#include "halhvsp.h" ++#include "drvCMDQ.h" ++#include "MsDbg.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define HVSP_CMD_TRIG_BUFFER_SIZE 50 ++#define Is_InputSource(Src) (genIpType == (Src)) ++#define Is_CLK_Increase(height,rate) ((height) > 720 && (rate) < 172000000) ++#define Is_CLK_Decrease(height,rate) ((height) <= 720 && (rate) >= 172000000) ++#define Is_Reg_Type(type) (gstHvspCmdTrigCfg.enType == (type)) ++#define Is_IP_First_Set(ip) (gbhvspset[(ip)]==0) ++#define HAL_HVSP_RATIO(input, output) (((input) * 1048576) / (output)) ++#define DISABLE_CLK 0x1 ++#define LOW_CLK 0x4 ++#define LOCK_FB() (gblockfbmg) ++#define _SetHVSPType(ID,u8type) (gstSclFea[(ID)].u16ModeYCVH |= (u8type)) ++#define _ReSetHVSPType(ID,u8type) (gstSclFea[(ID)].u16ModeYCVH &= ~(u8type)) ++#define Is_CannotUseCMDQToSetReg() (gbUseCMDQ == 0) ++ ++typedef struct ++{ ++ MS_U32 u32Reg; ++ MS_U16 u16Msk; ++ MS_U16 u16Val; ++}ST_HVSP_CMD_TRIG_BUFFER_TYPE; ++ ++typedef struct ++{ ++ ST_HVSP_CMD_TRIG_BUFFER_TYPE stCmdTrigBuf[HVSP_CMD_TRIG_BUFFER_SIZE]; ++ MS_U16 u16Idx; ++}ST_HVSP_CMD_TRIG_BUFFER_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16ModeYCVH; ++ MS_U16 u16DithCoring; ++}ST_HVSP_SCALING_FEATURE_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_U32 HVSP_RIU_BASE; ++///////////////// ++/// gstHvspCmdTrigCfg ++/// To save set Register type and used in scaling function. ++//////////////// ++ST_HVSP_CMD_TRIG_CONFIG gstHvspCmdTrigCfg; ++///////////////// ++/// gstHvspCmdTrigBufCfg ++/// To save CMD and used in scaling function. ++//////////////// ++ST_HVSP_CMD_TRIG_BUFFER_CONFIG gstHvspCmdTrigBufCfg; ++///////////////// ++/// genIpType ++/// To save Input Source Type. ++//////////////// ++EN_HVSP_IP_MUX_TYPE genIpType; ++///////////////// ++/// gu16height ++/// To save resolution and used in dynamic change clk. ++//////////////// ++MS_U16 gu16height[2]={0,0}; ++///////////////// ++/// genFilterMode ++/// To save scaling type for handle CMDQ can't mask issue. ++//////////////// ++EN_HVSP_FILTER_MODE genFilterMode; ++///////////////// ++/// gbhvspset ++/// The first time set HVSP scaling config can't use CMDQ(no sync to trig),so need to save this information. ++//////////////// ++MS_BOOL gbhvspset[E_HVSP_ID_MAX]={0,0,0}; ++ST_HVSP_SCALING_FEATURE_CONFIG gstSclFea[E_HVSP_ID_MAX]; ++MS_BOOL gbUseCMDQ; ++MS_BOOL gblockfbmg = 0; ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++ ++//============CLK================================ ++#if CONFIG_OF ++void Hal_HVSP_SetIdclkOnOff(MS_BOOL bEn,ST_HVSP_CLK_CONFIG* stclk) ++{ ++ struct clk* pstclock = NULL; ++ if(bEn) ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ if (__clk_get_enable_count(stclk->idclk)==0) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->idclk, 1))) ++ { ++ clk_set_parent(stclk->idclk, pstclock); ++ clk_prepare_enable(stclk->idclk); ++ //printf("[idclk]enable count=%d\n", __clk_get_enable_count(stclk->idclk)); ++ } ++ else ++ { ++ printf("[idclk]BT656 NULL\n"); ++ ++ } ++ } ++ } ++ else ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ if (__clk_get_enable_count(stclk->idclk)==0) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->idclk, 0))) ++ { ++ clk_set_parent(stclk->idclk, pstclock); ++ clk_prepare_enable(stclk->idclk); ++ } ++ } ++ } ++ } ++ else ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0100,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0005,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->idclk, 0))) ++ { ++ clk_set_parent(stclk->idclk, pstclock); ++ } ++ while (__clk_get_enable_count(stclk->idclk)) ++ { ++ clk_disable_unprepare(stclk->idclk); ++ } ++ } ++ else ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0001,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->idclk, 0))) ++ { ++ clk_set_parent(stclk->idclk, pstclock); ++ } ++ while (__clk_get_enable_count(stclk->idclk)) ++ { ++ clk_disable_unprepare(stclk->idclk); ++ } ++ } ++ ++ } ++} ++void Hal_HVSP_SetCLKRate(unsigned char u8Idx) ++{ ++ if((u8Idx &EN_HVSP_CLKATTR_BT656))//BT656 ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ } ++ else if((u8Idx &EN_HVSP_CLKATTR_ISP))//ISP ++ { ++ printf("[hal]ISP xxxxxxxxx\n"); ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ } ++ if((u8Idx &EN_HVSP_CLKATTR_FORCEMODE)) ++ { ++ printf("[hal]FORCEMODE xxxxxxxxx\n"); ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++} ++ ++void Hal_HVSP_FCLK1(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ struct clk* pstclock = NULL; ++ if (__clk_get_enable_count(stclk->fclk1)==0) ++ { ++ } ++ else ++ { ++ if(Is_CLK_Increase(gu16height[0],__clk_get_rate(stclk->fclk1))) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ clk_set_parent(stclk->fclk1, pstclock); ++ } ++ } ++ else if(Is_CLK_Decrease(gu16height[0],__clk_get_rate(stclk->fclk1))) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->fclk1, 1))) ++ { ++ clk_set_parent(stclk->fclk1, pstclock); ++ } ++ } ++ } ++ ++} ++ ++void Hal_HVSP_FCLK2(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ struct clk* pstclock = NULL; ++ if (__clk_get_enable_count(stclk->fclk2)==0) ++ { ++ } ++ else ++ { ++ if(Is_CLK_Increase(gu16height[1],__clk_get_rate(stclk->fclk2))) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ clk_set_parent(stclk->fclk2, pstclock); ++ } ++ //printf("[HVSP]CLK UP\n"); ++ } ++ else if(Is_CLK_Decrease(gu16height[1],__clk_get_rate(stclk->fclk2))) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ clk_set_parent(stclk->fclk2, pstclock); ++ } ++ //printf("[HVSP]CLK down\n"); ++ } ++ } ++} ++ ++#else ++void Hal_HVSP_SetIdclkOnOff(MS_BOOL bEn,ST_HVSP_CLK_CONFIG* stclk) ++{ ++ printf("[hal]NO OF\n"); ++ if(bEn) ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ if ((R2BYTE(REG_SCL_CLK_63_L)&DISABLE_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0004,0x000F);//h63 ++ } ++ } ++ else ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ if ((R2BYTE(REG_SCL_CLK_63_L)&DISABLE_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0000,0x000F);//h63 ++ } ++ } ++ ++ } ++ else ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0100,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0005,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0005,0x000F);//h63 ++ } ++ else ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0001,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0001,0x000F);//h63 ++ } ++ ++ } ++} ++void Hal_HVSP_SetCLKRate(unsigned char u8Idx) ++{ ++ if((u8Idx &EN_HVSP_CLKATTR_BT656))//BT656 ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ } ++ else if((u8Idx &EN_HVSP_CLKATTR_ISP))//ISP ++ { ++ printf("[hal]ISP xxxxxxxxx\n"); ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ } ++ if((u8Idx &EN_HVSP_CLKATTR_FORCEMODE)) ++ { ++ printf("[hal]FORCEMODE xxxxxxxxx\n"); ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++} ++ ++void Hal_HVSP_FCLK1(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ if ((R2BYTE(REG_SCL_CLK_64_L)&DISABLE_CLK)) ++ { ++ } ++ else ++ { ++ if(gu16height[0]>720 && (R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//h61 ++ } ++ else if(gu16height[0]<=720 && !(R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,LOW_CLK,0x000F);//h61 ++ } ++ } ++ ++} ++ ++void Hal_HVSP_FCLK2(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ if ((R2BYTE(REG_SCL_CLK_65_L)&DISABLE_CLK)) ++ { ++ } ++ else ++ { ++ if(gu16height[1]>720 && (R2BYTE(REG_SCL_CLK_65_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0000,0x000F);//h61 ++ } ++ else if(gu16height[1]<=720 && !(R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,LOW_CLK,0x000F);//h61 ++ } ++ } ++} ++ ++ ++#endif ++ ++//=========================================================== ++void Hal_HVSP_SetFrameBufferManageLock(MS_BOOL bEn) ++{ ++ gblockfbmg = bEn; ++} ++void Hal_HVSP_SetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg) ++{ ++ gbUseCMDQ = Drv_SCLIRQ_GetEachDMAEn(); ++ gstHvspCmdTrigCfg.enType = stCmdTrigCfg.enType; ++ gstHvspCmdTrigCfg.u8Fmcnt = stCmdTrigCfg.u8Fmcnt; ++} ++ ++void Hal_HVSP_GetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG *pCfg) ++{ ++ MsOS_Memcpy(pCfg, &gstHvspCmdTrigCfg, sizeof(ST_HVSP_CMD_TRIG_CONFIG)); ++} ++ ++void Hal_HVSP_SetCMDQTrigFrameCnt(MS_U16 u16Idx) ++{ ++ gstHvspCmdTrigBufCfg.u16Idx = u16Idx; ++} ++ ++void Hal_HVSP_SetCMDQTrigFire(void) ++{ ++ MS_U16 i; ++ //printf("[HVSP]Hal_HVSP_SetCMDQTrigFire gstHvspCmdTrigCfg.enType:%d \n",gstHvspCmdTrigCfg.enType); ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_CMDQ_FRMCNT)) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ for(i=0; i< gstHvspCmdTrigBufCfg.u16Idx; i++) ++ { ++ Drv_CMDQ_AssignFrameWriteCmd(gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u32Reg, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Val, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Msk, ++ gstHvspCmdTrigCfg.u8Fmcnt); ++ } ++ ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ } ++ else if(Is_Reg_Type(E_HVSP_CMD_TRIG_CMDQ_LDC_SYNC)) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ for(i=0; i< gstHvspCmdTrigBufCfg.u16Idx; i++) ++ { ++ Drv_CMDQ_WriteCmd(gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u32Reg, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Val, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Msk,0); ++ } ++ ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ } ++ else if(Is_Reg_Type(E_HVSP_CMD_TRIG_POLL_LDC_SYNC)) ++ { ++ for(i=0; i< gstHvspCmdTrigBufCfg.u16Idx; i++) ++ { ++ W2BYTEMSK(gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u32Reg, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Val, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Msk); ++ } ++ } ++ ++} ++ ++ ++MS_BOOL _Hal_HVSP_Write_Cmd(MS_U32 u32Reg, MS_U16 u16Val, MS_U16 u16Msk) ++{ ++ MS_U16 u16idx = gstHvspCmdTrigBufCfg.u16Idx; ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[u16idx].u32Reg = u32Reg; ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[u16idx].u16Msk = u16Msk; ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[u16idx].u16Val = u16Val; ++ //printf("[HVSP]_Hal_HVSP_Write_Cmd u32Reg:%lx u16Msk:%hx u16Val:%hx \n",u32Reg,u16Msk,u16Val); ++ gstHvspCmdTrigBufCfg.u16Idx++; ++ if(gstHvspCmdTrigBufCfg.u16Idx >= HVSP_CMD_TRIG_BUFFER_SIZE) ++ { ++ gstHvspCmdTrigBufCfg.u16Idx = HVSP_CMD_TRIG_BUFFER_SIZE-1; ++ return FALSE; ++ } ++ else ++ { ++ return TRUE; ++ } ++} ++ ++void Hal_HVSP_SetRiuBase(MS_U32 u32RiuBase) ++{ ++ HVSP_RIU_BASE = u32RiuBase; ++} ++ ++void Hal_HVSP_Set_Reset(void) ++{ ++ gbhvspset[0]= 0; ++ gbhvspset[1]= 0; ++ gbhvspset[2]= 0; ++ gbUseCMDQ = 0; ++ gstSclFea[0].u16ModeYCVH= 0; ++ gstSclFea[1].u16ModeYCVH= 0; ++ gstSclFea[2].u16ModeYCVH= 0; ++ gstSclFea[0].u16DithCoring= 0; ++ gstSclFea[1].u16DithCoring= 0; ++ gstSclFea[2].u16DithCoring= 0; ++ Hal_HVSP_SetNLMEn(0); ++ W2BYTEMSK(REG_SCL2_50_L, 0, BIT0);//crop1 ++ W2BYTEMSK(REG_SCL2_58_L, 0, BIT0);//crop2 ++ Hal_HVSP_SetIPMReadEn(0); ++ Hal_HVSP_SetIPMWriteEn(0); ++ Hal_HVSP_SetLDCPathSel(0); ++ Hal_HVSP_SetLDCBypass(1); ++} ++ ++void Hal_HVSP_SetNLMSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_LCE_6E_L, u16Width, 0x0FFF); ++ W2BYTEMSK(REG_VIP_LCE_6F_L, u16Height, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_LCE_6E_L, u16Width, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_LCE_6F_L, u16Height, 0x1FFF); ++ } ++} ++ ++#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_Set_SW_Reset(MS_BOOL bEn) ++{ ++ ++ W2BYTEMSK(REG_SCL0_01_L, bEn ? BIT0 : 0, BIT0); ++ W2BYTEMSK(REG_SCL0_01_L, 0, BIT0); ++} ++#endif ++ ++void Hal_HVSP_SetNLMLineBufferSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ W2BYTEMSK(REG_SCL0_19_L, 0x8000, 0x8000); ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL0_1A_L, u16Width, 0x0FFF); ++ W2BYTEMSK(REG_SCL0_1B_L, u16Height, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL0_1A_L, u16Width, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL0_1B_L, u16Height, 0x1FFF); ++ } ++} ++ ++void Hal_HVSP_SetNLMEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_18_L, bEn ? BIT0 : 0, BIT0); ++} ++void Hal_HVSP_SetVpsSRAMEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_VIP_PK_10_L, bEn ? BIT7 : 0, BIT7); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Crop ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_SetBT656SrcConfig(MS_BOOL bEn,MS_U16 u16Lineoffset) ++{ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656) ) ++ { ++ W2BYTEMSK(REG_SCL0_61_L, bEn ? BIT7 : 0, BIT7); ++ W2BYTEMSK(REG_SCL0_63_L, u16Lineoffset, 0x07FF); ++ W2BYTEMSK(REG_SCL0_62_L, 8, 0x07FF); ++ } ++} ++ ++ ++void Hal_HVSP_SetCropConfig(EN_HVSP_CROP_ID_TYPE enID, ST_HVSP_CROP_INFO stCropInfo) ++{ ++ MS_U32 u32reg_idx = enID == E_HVSP_CROP_ID_1 ? 0x00 : 0x10; ++ ++ //Crop01: 0x50 ++ //Crop02: 0x58 ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ if((stCropInfo.u16In_hsize == stCropInfo.u16Hsize) && (stCropInfo.u16Vsize == stCropInfo.u16In_vsize)) ++ { ++ W2BYTEMSK(REG_SCL2_50_L + u32reg_idx, 0, BIT0); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL2_50_L + u32reg_idx, stCropInfo.bEn ? BIT0 : 0, BIT0); ++ } ++ W2BYTEMSK(REG_SCL2_51_L + u32reg_idx, stCropInfo.u16In_hsize, 0x07FF); ++ W2BYTEMSK(REG_SCL2_52_L + u32reg_idx, stCropInfo.u16In_vsize, 0x07FF); ++ W2BYTEMSK(REG_SCL2_53_L + u32reg_idx, stCropInfo.u16Hst, 0x07FF); ++ W2BYTEMSK(REG_SCL2_54_L + u32reg_idx, stCropInfo.u16Hsize, 0x07FF); ++ W2BYTEMSK(REG_SCL2_55_L + u32reg_idx, stCropInfo.u16Vst, 0x07FF); ++ W2BYTEMSK(REG_SCL2_56_L + u32reg_idx, stCropInfo.u16Vsize, 0x07FF); ++ } ++ else ++ { ++ if((stCropInfo.u16In_hsize == stCropInfo.u16Hsize) && (stCropInfo.u16Vsize == stCropInfo.u16In_vsize)) ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL2_50_L + u32reg_idx, 0, BIT0); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL2_50_L + u32reg_idx, stCropInfo.bEn ? BIT0 : 0, BIT0); ++ } ++ _Hal_HVSP_Write_Cmd(REG_SCL2_51_L + u32reg_idx, stCropInfo.u16In_hsize, 0x07FF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_52_L + u32reg_idx, stCropInfo.u16In_vsize, 0x07FF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_53_L + u32reg_idx, stCropInfo.u16Hst, 0x07FF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_54_L + u32reg_idx, stCropInfo.u16Hsize, 0x07FF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_55_L + u32reg_idx, stCropInfo.u16Vst, 0x07FF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_56_L + u32reg_idx, stCropInfo.u16Vsize, 0x07FF); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// IP Mux ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_SetInputMuxType(EN_HVSP_IP_MUX_TYPE enIpType) ++{ ++ genIpType = enIpType; ++} ++ ++MS_U32 Hal_HVSP_GetInputSrcMux(void) ++{ ++ return genIpType; ++} ++ ++void Hal_HVSP_SetHWInputMux(EN_HVSP_IP_MUX_TYPE enIpType) ++{ ++ W2BYTEMSK(REG_SCL0_60_L, enIpType == E_HVSP_IP_MUX_BT656 ? 0 : BIT0, BIT0); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IPM ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_SetIPMReadEn(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++void Hal_HVSP_SetIPMWriteEn(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT1 : 0, BIT1); ++} ++ ++void Hal_HVSP_SetIPMBase(MS_U32 u32Base) ++{ ++ MS_U16 u16Base_Lo, u16Base_Hi; ++ u32Base = u32Base>>4; ++ u16Base_Lo = u32Base & 0xFFFF; ++ u16Base_Hi = (u32Base & 0x07FF0000) >> 16; ++ W2BYTE(REG_SCL_DNR1_08_L, u16Base_Lo); ++ W2BYTE(REG_SCL_DNR1_09_L, u16Base_Hi); ++} ++ ++#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_Set_IPM_Read_Req(MS_U8 u8Thrd, MS_U8 u8Limit) ++{ ++ W2BYTE(REG_SCL_DNR1_0A_L, ((((MS_U16)u8Limit)<<8) | ((MS_U16)u8Thrd))); ++} ++ ++void Hal_HVSP_Set_IPM_Write_Req(MS_U8 u8Thrd, MS_U8 u8Limit) ++{ ++ W2BYTE(REG_SCL_DNR1_0B_L, ((((MS_U16)u8Limit)<<8) | ((MS_U16)u8Thrd))); ++} ++#endif ++ ++void Hal_HVSP_SetIPMvSize(MS_U16 u16Vsize) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_0D_L, u16Vsize, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_0D_L, u16Vsize, 0x1FFF); ++ } ++ gu16height[0] = u16Vsize; ++} ++ ++void Hal_HVSP_SetIPMLineOffset(MS_U16 u16Lineoffset) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_0E_L, u16Lineoffset, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_0E_L, u16Lineoffset, 0x1FFF); ++ } ++} ++ ++void Hal_HVSP_SetIPMFetchNum(MS_U16 u16FetchNum) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_0F_L, u16FetchNum, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_0F_L, u16FetchNum, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetIPMBufferNumber(MS_U8 u8Num) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_02_L, u8Num , 0x7); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Scaling ++//------------------------------------------------------------------------------------------------- ++ ++void Hal_HVSP_SetScalingVeEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0A_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0A_L : ++ REG_SCL_HVSP0_0A_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++} ++void Hal_HVSP_SetScalingVeFactor(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_09_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_09_L : ++ REG_SCL_HVSP0_09_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W3BYTE(u32reg, u32Ratio); ++ } ++ else ++ { ++ MS_U16 u16val_L = u32Ratio & 0xFFFF; ++ MS_U16 u16val_H = (u32Ratio >> 16) & 0x00FF; ++ if(u32Ratio) ++ { ++ u16val_H=(u16val_H|0x0100); ++ } ++ _Hal_HVSP_Write_Cmd(u32reg, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(u32reg+2, u16val_H, 0x01FF); ++ } ++} ++ ++void Hal_HVSP_SetScalingHoEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_08_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_08_L : ++ REG_SCL_HVSP0_08_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++} ++ ++void Hal_HVSP_SetScalingHoFacotr(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_07_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_07_L : ++ REG_SCL_HVSP0_07_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W3BYTE(u32reg, u32Ratio); ++ } ++ else ++ { ++ MS_U16 u16val_L = u32Ratio & 0xFFFF; ++ MS_U16 u16val_H = (u32Ratio >> 16) & 0x00FF; ++ if(u32Ratio) ++ { ++ u16val_H=(u16val_H|0x0100); ++ } ++ _Hal_HVSP_Write_Cmd(u32reg, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(u32reg+2, u16val_H, 0x01FF); ++ } ++} ++void Hal_HVSP_SetModeYHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ genFilterMode=enFilterMode; ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? 0 : BIT0, BIT0); ++ W2BYTEMSK(u32reg, (enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 || enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ? BIT6 : 0, BIT6); ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_1 ? BIT7 : 0, BIT7); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bBypass ? 0 : BIT0, BIT0); ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT0|BIT6|BIT7); ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT0); ++ _ReSetHVSPType(enID,BIT6|BIT7); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT0|BIT6); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT7); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT7); ++ } ++ } ++ } ++} ++ ++void Hal_HVSP_SetModeYVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? 0 : BIT8, BIT8); ++ W2BYTEMSK(u32reg, (enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 || enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ? BIT14 : 0, BIT14); ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_1 ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT15|BIT14|BIT8); ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT8); ++ _ReSetHVSPType(enID,BIT14|BIT15); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT8|BIT14); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT15); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT15); ++ } ++ } ++ //_Hal_HVSP_Write_Cmd(u32reg, bBypass ? 0 : BIT8, BIT8); ++ } ++} ++ ++void Hal_HVSP_SetModeCHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS || enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? (0<<1) : (1<<1), (BIT3|BIT2|BIT1)); ++ W2BYTEMSK(u32reg, 0x0000, BIT4); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<5) : (1<<5), BIT5); //ram_sel ++ } ++ else ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 ? (2<<1) : (3<<1), (BIT3|BIT2|BIT1)); ++ W2BYTEMSK(u32reg, BIT4, BIT4); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<5) : (1<<5), BIT5); //ram_sel ++ } ++ } ++ else ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT3|BIT2|BIT1|BIT4); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT5); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT5); ++ } ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT1); ++ _ReSetHVSPType(enID,BIT3|BIT2|BIT4); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT5); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT5); ++ } ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT4|BIT2); ++ _ReSetHVSPType(enID,BIT3); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT1); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT1); ++ } ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT5); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT5); ++ } ++ } ++ } ++} ++ ++void Hal_HVSP_SetModeCVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS || enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? (0<<9) : (1<<9), (BIT11|BIT10|BIT9)); ++ W2BYTEMSK(u32reg, 0x0000, BIT12); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<13) : (1<<13), BIT13); //ram_sel ++ } ++ else ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 ? (2<<9) : (3<<9), (BIT11|BIT10|BIT9)); ++ W2BYTEMSK(u32reg, BIT12, BIT12); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<13) : (1<<13), BIT13); //ram_sel ++ } ++ } ++ else ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT9|BIT10|BIT11|BIT12); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT13); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT13); ++ } ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT9); ++ _ReSetHVSPType(enID,BIT10|BIT11|BIT12); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT13); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT13); ++ } ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT10|BIT12); ++ _ReSetHVSPType(enID,BIT11); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT9); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT9); ++ } ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT13); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT13); ++ } ++ } ++ _Hal_HVSP_Write_Cmd(u32reg,gstSclFea[enID].u16ModeYCVH,0xFFFF); ++ } ++ ++} ++ ++void Hal_HVSP_SetHspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT0) : (0), BIT0); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT0) : (0), BIT0); ++ } ++} ++ ++ ++void Hal_HVSP_SetVspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT1) : (0), BIT1); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT1) : (0), BIT1); ++ } ++} ++ ++void Hal_HVSP_SetHspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT8) : (0), BIT8); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT8) : (0), BIT8); ++ } ++} ++ ++void Hal_HVSP_SetHspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT9) : (0), BIT9); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT11|BIT10|BIT9|BIT8|BIT1|BIT0) : (0), BIT11|BIT10|BIT9|BIT8|BIT1|BIT0); ++ } ++} ++ ++void Hal_HVSP_SetVspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT10) : (0), BIT10); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT10) : (0), BIT10); ++ } ++} ++ ++void Hal_HVSP_SetVspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT11) : (0), BIT11); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT11|BIT10|BIT9|BIT8|BIT1|BIT0) : (0), BIT11|BIT10|BIT9|BIT8|BIT1|BIT0); ++ } ++} ++ ++void Hal_HVSP_SetHspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0D_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0D_L : ++ REG_SCL_HVSP0_0D_L; ++ ++ W2BYTEMSK(u32reg, u16Thread, 0x00FF); ++} ++ ++void Hal_HVSP_SetHspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0D_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0D_L : ++ REG_SCL_HVSP0_0D_L; ++ ++ W2BYTEMSK(u32reg, u16Thread<<8, 0xFF00); ++} ++ ++void Hal_HVSP_SetVspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0E_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0E_L : ++ REG_SCL_HVSP0_0E_L; ++ ++ W2BYTEMSK(u32reg, u16Thread, 0x00FF); ++} ++ ++void Hal_HVSP_SetVspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0E_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0E_L : ++ REG_SCL_HVSP0_0E_L; ++ ++ W2BYTEMSK(u32reg, u16Thread<<8, 0xFF00); ++} ++#if ENABLE_HVSP_UNUSED_FUNCTION ++ ++void Hal_HVSP_Set_Hvsp_Sram_Coeff(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_SRAM_SEL_TYPE enSramSel, MS_BOOL bC_SRAM, MS_U8 *pData) ++{ ++ MS_U32 u32reg_41, u32reg_42, u32reg_43; ++ MS_U8 u8Ramcode[10]; ++ MS_U16 u16IdxBase = 0; ++ MS_U16 i, j, x; ++ ++ if(enID == E_HVSP_ID_2) ++ { ++ u32reg_41 = REG_SCL_HVSP1_41_L; ++ u32reg_42 = REG_SCL_HVSP1_42_L; ++ u32reg_43 = REG_SCL_HVSP1_43_L; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u32reg_41 = REG_SCL_HVSP2_41_L; ++ u32reg_42 = REG_SCL_HVSP2_42_L; ++ u32reg_43 = REG_SCL_HVSP2_43_L; ++ } ++ else ++ { ++ u32reg_41 = REG_SCL_HVSP0_41_L; ++ u32reg_42 = REG_SCL_HVSP0_42_L; ++ u32reg_43 = REG_SCL_HVSP0_43_L; ++ } ++ ++ u16IdxBase = enSramSel == E_HVSP_FILTER_SRAM_SEL_1 ? 0x00 : ++ enSramSel == E_HVSP_FILTER_SRAM_SEL_2 ? 0x40 : ++ enSramSel == E_HVSP_FILTER_SRAM_SEL_3 ? 0x80 : ++ 0xC0 ; ++ ++ W2BYTEMSK(u32reg_41, bC_SRAM ? BIT1 : BIT0, BIT1|BIT0); // reg_cram_rw_en ++ ++ for(i=0; i<64; i++) ++ { ++ while(R2BYTE(u32reg_41) & BIT8); ++ j=i*5; ++ ++ W2BYTEMSK(u32reg_42,(i|u16IdxBase), 0x00FF); ++ for ( x=0;x<5;x++ ) ++ { ++ u8Ramcode[x] = pData[j+x]; ++ } ++ ++ W2BYTEMSK(u32reg_43+0x00, (((MS_U16)u8Ramcode[1])<<8|(MS_U16)u8Ramcode[0]), 0xFFFF); ++ W2BYTEMSK(u32reg_43+0x02, (((MS_U16)u8Ramcode[3])<<8|(MS_U16)u8Ramcode[2]), 0xFFFF); ++ W2BYTEMSK(u32reg_43+0x04, ((MS_U16)u8Ramcode[4]), 0x00FF); ++ ++ ++ W2BYTEMSK(u32reg_41, BIT8, BIT8); ++ } ++} ++#endif ++ ++void Hal_HVSP_SetHVSPInputSize(EN_HVSP_ID_TYPE enID, MS_U16 u16Width, MS_U16 u16Height) ++{ ++ MS_U32 u32reg_20, u32reg_21; ++ ++ if(enID == E_HVSP_ID_2) ++ { ++ u32reg_20 = REG_SCL_HVSP1_20_L; ++ u32reg_21 = REG_SCL_HVSP1_21_L; ++ gu16height[0] = (gu16height[0]> 16) & 0x00FF; ++ u16val_H = (u16val_H|0x0100); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_07_L, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_07_L+2, u16val_H, 0x01FF); ++ } ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_20_L, u16Width,0xFFFF); ++ } ++ } ++ if((R2BYTE(REG_SCL_HVSP1_21_L) != u16Height)&&(gbhvspset[E_HVSP_ID_2])) ++ { ++ if(R2BYTE(REG_SCL_HVSP1_23_L)) ++ { ++ u32ratio = HAL_HVSP_RATIO(u16Height,R2BYTE(REG_SCL_HVSP1_23_L)); ++ if(u32ratio) ++ { ++ u16val_L = u32ratio & 0xFFFF; ++ u16val_H = (u32ratio >> 16) & 0x00FF; ++ u16val_H = (u16val_H|0x0100); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_09_L, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_09_L+2, u16val_H, 0x01FF); ++ } ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_21_L, u16Height,0xFFFF); ++ } ++ } ++ } ++ else if(enID ==E_HVSP_ID_2) ++ { ++ if(R2BYTE(REG_SCL_DMA0_62_L) != u16Width) ++ _Hal_HVSP_Write_Cmd(REG_SCL_DMA0_62_L, u16Width, 0xFFFF); ++ if(R2BYTE(REG_SCL_DMA0_63_L) != u16Height) ++ _Hal_HVSP_Write_Cmd(REG_SCL_DMA0_63_L, u16Height,0xFFFF); ++ } ++ } ++} ++ ++// input tgen ++void Hal_HVSP_SetPatTgEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_40_L, bEn ? (BIT0|BIT1|BIT2|BIT15) : 0, BIT0|BIT1|BIT2|BIT15); ++ W2BYTEMSK(REG_SCL0_70_L, bEn ? BIT0 : 0, BIT0); ++ W2BYTEMSK(REG_SCL0_44_L, bEn ? BIT0 : 0, BIT0); // h/v ++} ++ ++void Hal_HVSP_SetTestPatCfg(void) ++{ ++ W2BYTEMSK(REG_SCL0_42_L, 0x1010, 0xFFFF); // cb h/v width ++ W2BYTEMSK(REG_SCL0_43_L, 0x0008, 0xFFFF); // shfit time ++ W2BYTEMSK(REG_SCL0_44_L, 0x0C20, 0xFFFF); // h/v ++} ++ ++ ++void Hal_HVSP_SetPatTgVsyncSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_71_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVsyncEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_72_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVfdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_73_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVfdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_74_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_75_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_76_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVtt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_77_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHsyncSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_79_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHsyncEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7A_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHfdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7B_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHfdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7C_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7D_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7E_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHtt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7F_L, u16Val, 0x0FFF); ++} ++ ++ ++// LDC frame control ++//#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_SetLDCPathSel(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL0_03_L, bEn ? BIT12 : 0, BIT12); ++} ++MS_BOOL Hal_HVSP_GetLDCPathSel(void) ++{ ++ MS_U16 bEn; ++ bEn = R2BYTE(REG_SCL0_03_L); ++ return (MS_BOOL)((bEn&BIT12)>>12); ++} ++ ++void Hal_HVSP_SetLDCBypass(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0F_L, bEn ? BIT0 : 0, BIT0); ++} ++//#endif ++ ++void Hal_HVSP_SetLDCWidth(MS_U16 u16Width) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL_LDC_03_L, u16Width, 0x07FF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_LDC_03_L, u16Width, 0x07FF); ++ } ++} ++ ++void Hal_HVSP_SetLDCHeight(MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL_LDC_04_L, u16Height, 0x07FF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_LDC_04_L, u16Height, 0x07FF); ++ } ++} ++ ++void Hal_HVSP_SetLDCBase(MS_U32 u32Base) ++{ ++ W4BYTE(REG_SCL_LDC_05_L, u32Base); ++} ++ ++void Hal_HVSP_SetLDCHWrwDiff(MS_U16 u8Val) ++{ ++ W2BYTEMSK(REG_SCL_LDC_09_L, ((MS_U16)u8Val), BIT3|BIT2|BIT8|BIT5|BIT4); ++} ++ ++#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_SetLDCPitch(MS_U32 u32Pitch) ++{ ++ W4BYTE(REG_SCL_LDC_07_L, u32Pitch); ++} ++ ++void Hal_HVSP_SetLDCSW_Mode(MS_U8 bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_09_L, ((MS_U16)bEn)? BIT8 :0, BIT8); ++} ++ ++void Hal_HVSP_SetLDCDmap_Base(MS_U32 u32Base) ++{ ++ W4BYTE(REG_SCL_LDC_0A_L, u32Base); ++} ++ ++void Hal_HVSP_SetLDCDmap_Pitch(MS_U32 u32Pitch) ++{ ++ W4BYTE(REG_SCL_LDC_0C_L, u32Pitch); ++} ++#endif ++void Hal_HVSP_SetOSDLocate(EN_HVSP_ID_TYPE enID,EN_DRV_HVSP_OSD_LOC_TYPE enLoc) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ WBYTEMSK(REG_SCL2_60_L, (enLoc==EN_DRV_HVSP_OSD_LOC_BEFORE) ? BIT1: 0, BIT1); ++ } ++} ++void Hal_HVSP_SetOSDOnOff(EN_HVSP_ID_TYPE enID,MS_BOOL bEn) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ WBYTEMSK(REG_SCL2_60_L, bEn? BIT0: 0, BIT0); ++ } ++} ++void Hal_HVSP_SetOSDbypass(EN_HVSP_ID_TYPE enID,MS_BOOL bEn) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ } ++} ++void Hal_HVSP_SetOSDbypassWTM(EN_HVSP_ID_TYPE enID,MS_BOOL bEn) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ } ++} ++EN_DRV_HVSP_OSD_LOC_TYPE Hal_HVSP_GetOSDLocate(EN_HVSP_ID_TYPE enID) ++{ ++ EN_DRV_HVSP_OSD_LOC_TYPE bEn = 0; ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ bEn = (R2BYTE(REG_SCL2_60_L)& BIT1)>>1; ++ } ++ return bEn; ++} ++MS_BOOL Hal_HVSP_GetOSDOnOff(EN_HVSP_ID_TYPE enID) ++{ ++ MS_BOOL bEn = 0; ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ bEn = R2BYTE(REG_SCL2_60_L)& BIT0; ++ } ++ return bEn; ++} ++MS_BOOL Hal_HVSP_GetOSDbypass(EN_HVSP_ID_TYPE enID) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ } ++ return 0; ++} ++MS_BOOL Hal_HVSP_GetOSDbypassWTM(EN_HVSP_ID_TYPE enID) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ } ++ else ++ { ++ } ++ return 0; ++} ++ ++void Hal_HVSP_Set_Reg(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask) ++{ ++ WBYTEMSK(u32Reg, u8Val, u8Mask); ++} ++ ++void Hal_HVSP_SetLDCSW_Idx(MS_U8 idx) ++{ ++ W2BYTEMSK(REG_SCL_LDC_09_L, ((MS_U16)idx)<<2, BIT3|BIT2); ++} ++MS_U16 Hal_HVSP_Get_Crop_X(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_53_L); ++ return u16crop1; ++} ++ ++MS_U16 Hal_HVSP_Get_Crop_Y(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_55_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop2Xinfo(void) ++{ ++ MS_U16 u16crop2; ++ u16crop2 = R2BYTE(REG_SCL2_5B_L); ++ return u16crop2; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2Yinfo(void) ++{ ++ MS_U16 u16crop2; ++ u16crop2 = R2BYTE(REG_SCL2_5D_L); ++ return u16crop2; ++} ++ ++MS_U16 Hal_HVSP_GetCrop1WidthCount(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_70_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop1HeightCount(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_71_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_Get_Crop2_CountH(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_72_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_Get_Crop2_CountV(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_73_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop1Width(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_51_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop1Height(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_52_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetDMAHeight(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 u16def; ++ ++ switch(enMonitorType) ++ { ++ case EN_HVSP_MONITOR_DMA1FRMCHECK: ++ u16def = R2BYTE(REG_SCL_DMA0_1B_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA1SNPCHECK: ++ u16def = R2BYTE(REG_SCL_DMA0_4B_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA2FRMCHECK: ++ u16def = R2BYTE(REG_SCL_DMA0_63_L); ++ break; ++ case EN_HVSP_MONITOR_DMA3FRMCHECK: ++ u16def = R2BYTE(REG_SCL_DMA1_1B_L); ++ break; ++ default: ++ u16def = 0x0; ++ break; ++ } ++ return ((u16def )); ++} ++MS_U16 Hal_HVSP_GetDMAHeightCount(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 u16Idx; ++ ++ switch(enMonitorType) ++ { ++ case EN_HVSP_MONITOR_DMA1FRMCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_10_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA1SNPCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_12_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA2FRMCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_13_L); ++ break; ++ case EN_HVSP_MONITOR_DMA3FRMCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_15_L); ++ break; ++ default: ++ u16Idx = 0x0; ++ break; ++ } ++ return ((u16Idx)); ++} ++ ++MS_U16 Hal_HVSP_GetDMAEn(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 bEn; ++ switch(enMonitorType) ++ { ++ case EN_HVSP_MONITOR_DMA1FRMCHECK: ++ bEn = R2BYTE(REG_SCL_DMA0_01_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ ++ case EN_HVSP_MONITOR_DMA1SNPCHECK: ++ bEn = R2BYTE(REG_SCL_DMA0_03_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ ++ case EN_HVSP_MONITOR_DMA2FRMCHECK: ++ bEn = R2BYTE(REG_SCL_DMA0_04_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ case EN_HVSP_MONITOR_DMA3FRMCHECK: ++ bEn = R2BYTE(REG_SCL_DMA1_01_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ default: ++ bEn = 0x0; ++ break; ++ } ++ return bEn; ++} ++MS_U16 Hal_HVSP_GetHVSPInputWidth(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_20_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_20_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_20_L); ++ } ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetHVSPOutputWidth(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_22_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_22_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_22_L); ++ } ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2InputWidth(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_59_L); ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2InputHeight(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_5A_L); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetCrop2OutputWidth(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_5C_L); ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2OutputHeight(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_5E_L); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetCrop2En(void) ++{ ++ MS_U16 u16size; ++ u16size = (R2BYTE(REG_SCL2_58_L) & BIT0); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetHVSPOutputHeight(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_23_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_23_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_23_L); ++ } ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetHVSPInputHeight(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_21_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_21_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_21_L); ++ } ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetScalingFunctionStatus(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = (R2BYTE(REG_SCL_HVSP1_08_L) & BIT8)>>8; ++ u16size |= (R2BYTE(REG_SCL_HVSP1_0A_L)& BIT8)>>7; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = (R2BYTE(REG_SCL_HVSP2_08_L) & BIT8)>>8; ++ u16size |= (R2BYTE(REG_SCL_HVSP2_0A_L)& BIT8)>>7; ++ } ++ else ++ { ++ u16size = (R2BYTE(REG_SCL_HVSP0_08_L) & BIT8)>>8; ++ u16size |= (R2BYTE(REG_SCL_HVSP0_0A_L)& BIT8)>>7; ++ } ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetHVSPOutputHeightCount(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_25_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_26_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_26_L); ++ } ++ return u16size; ++} ++MS_U32 Hal_HVSP_GetCMDQStatus(void) ++{ ++ return R2BYTE(0x11208A); ++} ++#undef HAL_HVSP_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/include/halhvsp.h b/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/include/halhvsp.h +new file mode 100644 +index 00000000..b313ba9c +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/include/halhvsp.h +@@ -0,0 +1,290 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. 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If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_HVSP_H ++#define _HAL_HVSP_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_HVSP_FILTER_MODE_BYPASS, ++ E_HVSP_FILTER_MODE_BILINEAR, ++ E_HVSP_FILTER_MODE_SRAM_0, ++ E_HVSP_FILTER_MODE_SRAM_1, ++}EN_HVSP_FILTER_MODE; ++ ++typedef enum ++{ ++ E_HVSP_SRAM_SEL_0, ++ E_HVSP_SRAM_SEL_1, ++}EN_HVSP_SRAM_SEL_TYPE; ++ ++typedef enum ++{ ++ E_HVSP_FILTER_SRAM_SEL_1, ++ E_HVSP_FILTER_SRAM_SEL_2, ++ E_HVSP_FILTER_SRAM_SEL_3, ++ E_HVSP_FILTER_SRAM_SEL_4, ++}EN_HVSP_FILTER_SRAM_SEL_TYPE; ++ ++typedef enum ++{ ++ EN_HVSP_CLKATTR_ISP=0x10, ++ EN_HVSP_CLKATTR_BT656=0x20, ++ EN_HVSP_CLKATTR_FORCEMODE=0x40, ++}EN_HVSP_CLKATTR_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U16 u16In_hsize; ++ MS_U16 u16In_vsize; ++ MS_U16 u16Hst; ++ MS_U16 u16Hsize; ++ MS_U16 u16Vst; ++ MS_U16 u16Vsize; ++}ST_HVSP_CROP_INFO; ++typedef enum ++{ ++ EN_VIP_SRAM_DUMP_ICC, ++ EN_VIP_SRAM_DUMP_IHC, ++ EN_VIP_SRAM_DUMP_HVSP, ++ EN_VIP_SRAM_DUMP_HVSP_1, ++ EN_VIP_SRAM_DUMP_HVSP_2, ++}EN_VIP_SRAM_DUMP_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef MHAL_HVSP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_HVSP_SetRiuBase(MS_U32 u32RiuBase); ++INTERFACE void Hal_VIP_SetLDCSW_Idx(MS_U8 idx); ++INTERFACE void Hal_HVSP_SetCropConfig(EN_HVSP_CROP_ID_TYPE enID, ST_HVSP_CROP_INFO stCropInfo); ++INTERFACE void Hal_HVSP_SetHWInputMux(EN_HVSP_IP_MUX_TYPE enIpType); ++INTERFACE void Hal_HVSP_SetInputMuxType(EN_HVSP_IP_MUX_TYPE enIpType); ++INTERFACE MS_U32 Hal_HVSP_GetInputSrcMux(void); ++INTERFACE void Hal_HVSP_Set_Reset(void); ++ ++// NLM ++INTERFACE void Hal_HVSP_SetNLMSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetNLMEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetNLMLineBufferSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetVpsSRAMEn(MS_BOOL bEn); ++ ++// IPM ++INTERFACE void Hal_HVSP_SetIPMReadEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetIPMWriteEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetIPMBase(MS_U32 u32Base); ++INTERFACE void Hal_HVSP_SetIPMvSize(MS_U16 u16Vsize); ++INTERFACE void Hal_HVSP_SetIPMLineOffset(MS_U16 u16Lineoffset); ++INTERFACE void Hal_HVSP_SetIPMFetchNum(MS_U16 u16FetchNum); ++INTERFACE void Hal_HVSP_Set_IPM_Read_Req(MS_U8 u8Thrd, MS_U8 u8Limit); ++INTERFACE void Hal_HVSP_Set_IPM_Write_Req(MS_U8 u8Thrd, MS_U8 u8Limit); ++INTERFACE void Hal_HVSP_SetIPMBufferNumber(MS_U8 u8Num); ++ ++ ++// Scaling ++INTERFACE void Hal_HVSP_SetScalingVeEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben); ++INTERFACE void Hal_HVSP_SetScalingVeFactor(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio); ++INTERFACE void Hal_HVSP_SetScalingHoEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben); ++INTERFACE void Hal_HVSP_SetScalingHoFacotr(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio); ++INTERFACE void Hal_HVSP_SetModeYHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode); ++INTERFACE void Hal_HVSP_SetModeYVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode); ++INTERFACE void Hal_HVSP_SetModeCHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel); ++INTERFACE void Hal_HVSP_SetModeCVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel); ++INTERFACE void Hal_HVSP_SetHspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetVspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetHspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetHspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetVspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetVspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetHspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_SetHspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_SetVspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_SetVspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_Set_Sram_Coeff(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_SRAM_SEL_TYPE enSramSel, MS_BOOL bC_SRAM, MS_U8 *pData); ++INTERFACE void Hal_HVSP_SetHVSPInputSize(EN_HVSP_ID_TYPE enID, MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetHVSPOutputSize(EN_HVSP_ID_TYPE enID, MS_U16 u16Width, MS_U16 u16Height); ++ ++// PatTg ++INTERFACE void Hal_HVSP_SetPatTgEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetPatTgVsyncSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVsyncEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVfdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVfdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVtt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHsyncSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHsyncEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHfdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHfdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHtt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetTestPatCfg(void); ++// REG W ++INTERFACE void Hal_HVSP_Set_Reg(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask); ++ ++// CMD buffer ++INTERFACE void Hal_HVSP_SetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg); ++INTERFACE void Hal_HVSP_GetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG *pCfg); ++INTERFACE void Hal_HVSP_SetCMDQTrigFrameCnt(MS_U16 u16Idx); ++INTERFACE void Hal_HVSP_SetCMDQTrigFire(void); ++INTERFACE void Hal_HVSP_SetFrameBufferManageLock(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetLDCPathSel(MS_BOOL bEn); ++INTERFACE MS_BOOL Hal_HVSP_GetLDCPathSel(void); ++INTERFACE void Hal_HVSP_SetLDCBypass(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetLDCHeight(MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetLDCWidth(MS_U16 u16Width); ++INTERFACE void Hal_HVSP_SetLDCPitch(MS_U32 u32Pitch); ++INTERFACE void Hal_HVSP_SetLDCBase(MS_U32 u32Base); ++INTERFACE void Hal_HVSP_SetLDCHWrwDiff(MS_U16 u8Val); ++INTERFACE void Hal_HVSP_SetLDCSW_Mode(MS_U8 bEn); ++INTERFACE void Hal_HVSP_SetLDCSW_Idx(MS_U8 idx); ++INTERFACE void Hal_HVSP_SetOSDLocate(EN_HVSP_ID_TYPE enID,EN_DRV_HVSP_OSD_LOC_TYPE enLoc); ++INTERFACE void Hal_HVSP_SetOSDbypass(EN_HVSP_ID_TYPE enID,MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetOSDOnOff(EN_HVSP_ID_TYPE enID,MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetOSDbypassWTM(EN_HVSP_ID_TYPE enID,MS_BOOL bEn); ++INTERFACE EN_DRV_HVSP_OSD_LOC_TYPE Hal_HVSP_GetOSDLocate(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_BOOL Hal_HVSP_GetOSDbypass(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_BOOL Hal_HVSP_GetOSDOnOff(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_BOOL Hal_HVSP_GetOSDbypassWTM(EN_HVSP_ID_TYPE enID); ++INTERFACE void Hal_HVSP_SetIdclkOnOff(MS_BOOL bEn,ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE void Hal_HVSP_FCLK1(ST_HVSP_CLK_CONFIG *stclk); ++INTERFACE void Hal_HVSP_FCLK2(ST_HVSP_CLK_CONFIG *stclk); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPOutputHeight(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPOutputHeightCount(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetScalingFunctionStatus(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPInputHeight(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPInputWidth(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop_X(void); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPOutputWidth(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop_Y(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2Yinfo(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2Xinfo(void); ++INTERFACE void Hal_HVSP_SetBT656SrcConfig(MS_BOOL bEn,MS_U16 u16Lineoffset); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1WidthCount(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1HeightCount(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1Width(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1Height(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2InputWidth(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2InputHeight(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2OutputWidth(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2OutputHeight(void); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop2_CountH(void); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop2_CountV(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2En(void); ++INTERFACE void Hal_HVSP_SetCLKRate(unsigned char u8Idx); ++INTERFACE MS_U32 Hal_HVSP_GetCMDQStatus(void); ++INTERFACE MS_U16 Hal_HVSP_GetDMAHeight(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_U16 Hal_HVSP_GetDMAHeightCount(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_U16 Hal_HVSP_GetDMAEn(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE void Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_TYPE endump,MS_BOOL u8Sram); ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/include/halhvsp_utility.h b/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/include/halhvsp_utility.h +new file mode 100644 +index 00000000..9b525d94 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/hvsp/include/halhvsp_utility.h +@@ -0,0 +1,69 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCL_UTILITY_H_ ++#define _HALSCL_UTILITY_H_ ++ ++//!! Do not include this header in driver or api level ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 HVSP_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( HVSP_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( HVSP_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (HVSP_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( HVSP_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++ ++#define WBYTEMSK(u32Reg, u8Val, u8Mask) \ ++ RIU_WRITE_BYTE( (((u32Reg)<<1) - ((u32Reg) & 1)), ( RIU_READ_BYTE( (((u32Reg)<<1) - ((u32Reg) & 1)) ) & ~(u8Mask)) | ((u8Val) & (u8Mask)) ) ++ ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/hwreg.h b/drivers/mstar/scl/infinity/src/mxlib/hal/hwreg.h +new file mode 100644 +index 00000000..6e030097 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/hwreg.h +@@ -0,0 +1,6542 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HWREG_H_ ++#define _HWREG_H_ ++ ++//------------------------------------------------------------------------------------- ++#define REG_CHIPTOP_BASE 0x101E00 ++#define REG_ISP_BASE 0x130200 ++#define REG_SCL_LPLL_BASE 0x103300 ++#define REG_SCL_CLK_BASE 0x103800 ++#define REG_BLOCK_BASE 0x113300 ++#define REG_SCL_HVSP0_BASE 0x121000 ++#define REG_SCL_HVSP1_BASE 0x121100 ++#define REG_SCL_HVSP2_BASE 0x121200 ++#define REG_SCL_DMA0_BASE 0x121300 ++#define REG_SCL_DMA1_BASE 0x121400 ++#define REG_SCL_DMA2_BASE 0x121500 ++#define REG_SCL_DNR0_BASE 0x121600 ++#define REG_SCL_NLM0_BASE 0x121700 ++#define REG_SCL0_BASE 0x121800 ++#define REG_SCL1_BASE 0x121900 ++#define REG_SCL2_BASE 0x121A00 ++#define REG_VIP_ACE3_BASE 0x121B00 ++#define REG_VIP_ACE_BASE 0x121C00 ++#define REG_VIP_PK_BASE 0x121D00 ++#define REG_VIP_DLC_BASE 0x121E00 ++#define REG_VIP_MWE_BASE 0x121F00 ++#define REG_VIP_ACE2_BASE 0x122000 ++#define REG_VIP_LCE_BASE 0x122100 ++#define REG_SCL_DNR1_BASE 0x122200 ++#define REG_SCL_DNR2_BASE 0x122300 ++#define REG_SCL_LDC_BASE 0x122400 ++#define REG_SCL3_BASE 0x122500 ++#define REG_MCM_BASE 0x113200 ++ ++//------------------------------------------------------------------------------------- ++#define REG_ISP_7A_L (REG_ISP_BASE + 0xF4) ++#define REG_ISP_7A_H (REG_ISP_BASE + 0xF5) ++//------------------------------------------------------------------------------------- ++#define REG_MCM_00_L (REG_MCM_BASE + 0x00) ++#define REG_MCM_00_H (REG_MCM_BASE + 0x01) ++#define REG_MCM_01_L (REG_MCM_BASE + 0x02) ++#define REG_MCM_01_H (REG_MCM_BASE + 0x03) ++#define REG_MCM_02_L (REG_MCM_BASE + 0x04) ++#define REG_MCM_02_H (REG_MCM_BASE + 0x05) ++#define REG_MCM_03_L (REG_MCM_BASE + 0x06) ++#define REG_MCM_03_H (REG_MCM_BASE + 0x07) ++#define REG_MCM_04_L (REG_MCM_BASE + 0x08) ++#define REG_MCM_04_H (REG_MCM_BASE + 0x09) ++#define REG_MCM_05_L (REG_MCM_BASE + 0x0A) ++#define REG_MCM_05_H (REG_MCM_BASE + 0x0B) ++#define REG_MCM_06_L (REG_MCM_BASE + 0x0C) ++#define REG_MCM_06_H (REG_MCM_BASE + 0x0D) ++#define REG_MCM_07_L (REG_MCM_BASE + 0x0E) ++#define REG_MCM_07_H (REG_MCM_BASE + 0x0F) ++#define REG_MCM_08_L (REG_MCM_BASE + 0x10) ++#define REG_MCM_08_H (REG_MCM_BASE + 0x11) ++#define REG_MCM_09_L (REG_MCM_BASE + 0x12) ++#define REG_MCM_09_H (REG_MCM_BASE + 0x13) ++#define REG_MCM_0A_L (REG_MCM_BASE + 0x14) ++#define REG_MCM_0A_H (REG_MCM_BASE + 0x15) ++#define REG_MCM_0B_L (REG_MCM_BASE + 0x16) ++#define REG_MCM_0B_H (REG_MCM_BASE + 0x17) ++#define REG_MCM_0C_L (REG_MCM_BASE + 0x18) ++#define REG_MCM_0C_H (REG_MCM_BASE + 0x19) ++#define REG_MCM_0D_L (REG_MCM_BASE + 0x1A) ++#define REG_MCM_0D_H (REG_MCM_BASE + 0x1B) ++#define REG_MCM_0E_L (REG_MCM_BASE + 0x1C) ++#define REG_MCM_0E_H (REG_MCM_BASE + 0x1D) ++#define REG_MCM_0F_L (REG_MCM_BASE + 0x1E) ++#define REG_MCM_0F_H (REG_MCM_BASE + 0x1F) ++#define REG_MCM_10_L (REG_MCM_BASE + 0x20) ++#define REG_MCM_10_H (REG_MCM_BASE + 0x21) ++#define REG_MCM_11_L (REG_MCM_BASE + 0x22) ++#define REG_MCM_11_H (REG_MCM_BASE + 0x23) ++#define REG_MCM_12_L (REG_MCM_BASE + 0x24) ++#define REG_MCM_12_H (REG_MCM_BASE + 0x25) ++#define REG_MCM_13_L (REG_MCM_BASE + 0x26) ++#define REG_MCM_13_H (REG_MCM_BASE + 0x27) ++#define REG_MCM_14_L (REG_MCM_BASE + 0x28) ++#define REG_MCM_14_H (REG_MCM_BASE + 0x29) ++#define REG_MCM_15_L (REG_MCM_BASE + 0x2A) ++#define REG_MCM_15_H (REG_MCM_BASE + 0x2B) ++#define REG_MCM_16_L (REG_MCM_BASE + 0x2C) ++#define REG_MCM_16_H (REG_MCM_BASE + 0x2D) ++#define REG_MCM_17_L (REG_MCM_BASE + 0x2E) ++#define REG_MCM_17_H (REG_MCM_BASE + 0x2F) ++#define REG_MCM_18_L (REG_MCM_BASE + 0x30) ++#define REG_MCM_18_H (REG_MCM_BASE + 0x31) ++#define REG_MCM_19_L (REG_MCM_BASE + 0x32) ++#define REG_MCM_19_H (REG_MCM_BASE + 0x33) ++#define REG_MCM_1A_L (REG_MCM_BASE + 0x34) ++#define REG_MCM_1A_H (REG_MCM_BASE + 0x35) ++#define REG_MCM_1B_L (REG_MCM_BASE + 0x36) ++#define REG_MCM_1B_H (REG_MCM_BASE + 0x37) ++#define REG_MCM_1C_L (REG_MCM_BASE + 0x38) ++#define REG_MCM_1C_H (REG_MCM_BASE + 0x39) ++#define REG_MCM_1D_L (REG_MCM_BASE + 0x3A) ++#define REG_MCM_1D_H (REG_MCM_BASE + 0x3B) ++#define REG_MCM_1E_L (REG_MCM_BASE + 0x3C) ++#define REG_MCM_1E_H (REG_MCM_BASE + 0x3D) ++#define REG_MCM_1F_L (REG_MCM_BASE + 0x3E) ++#define REG_MCM_1F_H (REG_MCM_BASE + 0x3F) ++ ++//-------------- ++#define REG_CHIPTOP_00_L (REG_CHIPTOP_BASE + 0x00) ++#define REG_CHIPTOP_00_H (REG_CHIPTOP_BASE + 0x01) ++#define REG_CHIPTOP_01_L (REG_CHIPTOP_BASE + 0x02) ++#define REG_CHIPTOP_01_H (REG_CHIPTOP_BASE + 0x03) ++#define REG_CHIPTOP_02_L (REG_CHIPTOP_BASE + 0x04) ++#define REG_CHIPTOP_02_H (REG_CHIPTOP_BASE + 0x05) ++#define REG_CHIPTOP_03_L (REG_CHIPTOP_BASE + 0x06) ++#define REG_CHIPTOP_03_H (REG_CHIPTOP_BASE + 0x07) ++#define REG_CHIPTOP_04_L (REG_CHIPTOP_BASE + 0x08) ++#define REG_CHIPTOP_04_H (REG_CHIPTOP_BASE + 0x09) ++#define REG_CHIPTOP_05_L (REG_CHIPTOP_BASE + 0x0A) ++#define REG_CHIPTOP_05_H (REG_CHIPTOP_BASE + 0x0B) ++#define REG_CHIPTOP_06_L (REG_CHIPTOP_BASE + 0x0C) ++#define REG_CHIPTOP_06_H (REG_CHIPTOP_BASE + 0x0D) ++#define REG_CHIPTOP_07_L (REG_CHIPTOP_BASE + 0x0E) ++#define REG_CHIPTOP_07_H (REG_CHIPTOP_BASE + 0x0F) ++#define REG_CHIPTOP_08_L (REG_CHIPTOP_BASE + 0x10) ++#define REG_CHIPTOP_08_H (REG_CHIPTOP_BASE + 0x11) ++#define REG_CHIPTOP_09_L (REG_CHIPTOP_BASE + 0x12) ++#define REG_CHIPTOP_09_H (REG_CHIPTOP_BASE + 0x13) ++#define REG_CHIPTOP_0A_L (REG_CHIPTOP_BASE + 0x14) ++#define REG_CHIPTOP_0A_H (REG_CHIPTOP_BASE + 0x15) ++#define REG_CHIPTOP_0B_L (REG_CHIPTOP_BASE + 0x16) ++#define REG_CHIPTOP_0B_H (REG_CHIPTOP_BASE + 0x17) ++#define REG_CHIPTOP_0C_L (REG_CHIPTOP_BASE + 0x18) ++#define REG_CHIPTOP_0C_H (REG_CHIPTOP_BASE + 0x19) ++#define REG_CHIPTOP_0D_L (REG_CHIPTOP_BASE + 0x1A) ++#define REG_CHIPTOP_0D_H (REG_CHIPTOP_BASE + 0x1B) ++#define REG_CHIPTOP_0E_L (REG_CHIPTOP_BASE + 0x1C) ++#define REG_CHIPTOP_0E_H (REG_CHIPTOP_BASE + 0x1D) ++#define REG_CHIPTOP_0F_L (REG_CHIPTOP_BASE + 0x1E) ++#define REG_CHIPTOP_0F_H (REG_CHIPTOP_BASE + 0x1F) ++#define REG_CHIPTOP_10_L (REG_CHIPTOP_BASE + 0x20) ++#define REG_CHIPTOP_10_H (REG_CHIPTOP_BASE + 0x21) ++#define REG_CHIPTOP_11_L (REG_CHIPTOP_BASE + 0x22) ++#define REG_CHIPTOP_11_H (REG_CHIPTOP_BASE + 0x23) ++#define REG_CHIPTOP_12_L (REG_CHIPTOP_BASE + 0x24) ++#define REG_CHIPTOP_12_H (REG_CHIPTOP_BASE + 0x25) ++#define REG_CHIPTOP_13_L (REG_CHIPTOP_BASE + 0x26) ++#define REG_CHIPTOP_13_H (REG_CHIPTOP_BASE + 0x27) ++#define REG_CHIPTOP_14_L (REG_CHIPTOP_BASE + 0x28) ++#define REG_CHIPTOP_14_H (REG_CHIPTOP_BASE + 0x29) ++#define REG_CHIPTOP_15_L (REG_CHIPTOP_BASE + 0x2A) ++#define REG_CHIPTOP_15_H (REG_CHIPTOP_BASE + 0x2B) ++#define REG_CHIPTOP_16_L (REG_CHIPTOP_BASE + 0x2C) ++#define REG_CHIPTOP_16_H (REG_CHIPTOP_BASE + 0x2D) ++#define REG_CHIPTOP_17_L (REG_CHIPTOP_BASE + 0x2E) ++#define REG_CHIPTOP_17_H (REG_CHIPTOP_BASE + 0x2F) ++#define REG_CHIPTOP_18_L (REG_CHIPTOP_BASE + 0x30) ++#define REG_CHIPTOP_18_H (REG_CHIPTOP_BASE + 0x31) ++#define REG_CHIPTOP_19_L (REG_CHIPTOP_BASE + 0x32) ++#define REG_CHIPTOP_19_H (REG_CHIPTOP_BASE + 0x33) ++#define REG_CHIPTOP_1A_L (REG_CHIPTOP_BASE + 0x34) ++#define REG_CHIPTOP_1A_H (REG_CHIPTOP_BASE + 0x35) ++#define REG_CHIPTOP_1B_L (REG_CHIPTOP_BASE + 0x36) ++#define REG_CHIPTOP_1B_H (REG_CHIPTOP_BASE + 0x37) ++#define REG_CHIPTOP_1C_L (REG_CHIPTOP_BASE + 0x38) ++#define REG_CHIPTOP_1C_H (REG_CHIPTOP_BASE + 0x39) ++#define REG_CHIPTOP_1D_L (REG_CHIPTOP_BASE + 0x3A) ++#define REG_CHIPTOP_1D_H (REG_CHIPTOP_BASE + 0x3B) ++#define REG_CHIPTOP_1E_L (REG_CHIPTOP_BASE + 0x3C) ++#define REG_CHIPTOP_1E_H (REG_CHIPTOP_BASE + 0x3D) ++#define REG_CHIPTOP_1F_L (REG_CHIPTOP_BASE + 0x3E) ++#define REG_CHIPTOP_1F_H (REG_CHIPTOP_BASE + 0x3F) ++#define REG_CHIPTOP_20_L (REG_CHIPTOP_BASE + 0x40) ++#define REG_CHIPTOP_20_H (REG_CHIPTOP_BASE + 0x41) ++#define REG_CHIPTOP_21_L (REG_CHIPTOP_BASE + 0x42) ++#define REG_CHIPTOP_21_H (REG_CHIPTOP_BASE + 0x43) ++#define REG_CHIPTOP_22_L (REG_CHIPTOP_BASE + 0x44) ++#define REG_CHIPTOP_22_H (REG_CHIPTOP_BASE + 0x45) ++#define REG_CHIPTOP_23_L (REG_CHIPTOP_BASE + 0x46) ++#define REG_CHIPTOP_23_H (REG_CHIPTOP_BASE + 0x47) ++#define REG_CHIPTOP_24_L (REG_CHIPTOP_BASE + 0x48) ++#define REG_CHIPTOP_24_H (REG_CHIPTOP_BASE + 0x49) ++#define REG_CHIPTOP_25_L (REG_CHIPTOP_BASE + 0x4A) ++#define REG_CHIPTOP_25_H (REG_CHIPTOP_BASE + 0x4B) ++#define REG_CHIPTOP_26_L (REG_CHIPTOP_BASE + 0x4C) ++#define REG_CHIPTOP_26_H (REG_CHIPTOP_BASE + 0x4D) ++#define REG_CHIPTOP_27_L (REG_CHIPTOP_BASE + 0x4E) ++#define REG_CHIPTOP_27_H (REG_CHIPTOP_BASE + 0x4F) ++#define REG_CHIPTOP_28_L (REG_CHIPTOP_BASE + 0x50) ++#define REG_CHIPTOP_28_H (REG_CHIPTOP_BASE + 0x51) ++#define REG_CHIPTOP_29_L (REG_CHIPTOP_BASE + 0x52) ++#define REG_CHIPTOP_29_H (REG_CHIPTOP_BASE + 0x53) ++#define REG_CHIPTOP_2A_L (REG_CHIPTOP_BASE + 0x54) ++#define REG_CHIPTOP_2A_H (REG_CHIPTOP_BASE + 0x55) ++#define REG_CHIPTOP_2B_L (REG_CHIPTOP_BASE + 0x56) ++#define REG_CHIPTOP_2B_H (REG_CHIPTOP_BASE + 0x57) ++#define REG_CHIPTOP_2C_L (REG_CHIPTOP_BASE + 0x58) ++#define REG_CHIPTOP_2C_H (REG_CHIPTOP_BASE + 0x59) ++#define REG_CHIPTOP_2D_L (REG_CHIPTOP_BASE + 0x5A) ++#define REG_CHIPTOP_2D_H (REG_CHIPTOP_BASE + 0x5B) ++#define REG_CHIPTOP_2E_L (REG_CHIPTOP_BASE + 0x5C) ++#define REG_CHIPTOP_2E_H (REG_CHIPTOP_BASE + 0x5D) ++#define REG_CHIPTOP_2F_L (REG_CHIPTOP_BASE + 0x5E) ++#define REG_CHIPTOP_2F_H (REG_CHIPTOP_BASE + 0x5F) ++#define REG_CHIPTOP_30_L (REG_CHIPTOP_BASE + 0x60) ++#define REG_CHIPTOP_30_H (REG_CHIPTOP_BASE + 0x61) ++#define REG_CHIPTOP_31_L (REG_CHIPTOP_BASE + 0x62) ++#define REG_CHIPTOP_31_H (REG_CHIPTOP_BASE + 0x63) ++#define REG_CHIPTOP_32_L (REG_CHIPTOP_BASE + 0x64) ++#define REG_CHIPTOP_32_H (REG_CHIPTOP_BASE + 0x65) ++#define REG_CHIPTOP_33_L (REG_CHIPTOP_BASE + 0x66) ++#define REG_CHIPTOP_33_H (REG_CHIPTOP_BASE + 0x67) ++#define REG_CHIPTOP_34_L (REG_CHIPTOP_BASE + 0x68) ++#define REG_CHIPTOP_34_H (REG_CHIPTOP_BASE + 0x69) ++#define REG_CHIPTOP_35_L (REG_CHIPTOP_BASE + 0x6A) ++#define REG_CHIPTOP_35_H (REG_CHIPTOP_BASE + 0x6B) ++#define REG_CHIPTOP_36_L (REG_CHIPTOP_BASE + 0x6C) ++#define REG_CHIPTOP_36_H (REG_CHIPTOP_BASE + 0x6D) ++#define REG_CHIPTOP_37_L (REG_CHIPTOP_BASE + 0x6E) ++#define REG_CHIPTOP_37_H (REG_CHIPTOP_BASE + 0x6F) ++#define REG_CHIPTOP_38_L (REG_CHIPTOP_BASE + 0x70) ++#define REG_CHIPTOP_38_H (REG_CHIPTOP_BASE + 0x71) ++#define REG_CHIPTOP_39_L (REG_CHIPTOP_BASE + 0x72) ++#define REG_CHIPTOP_39_H (REG_CHIPTOP_BASE + 0x73) ++#define REG_CHIPTOP_3A_L (REG_CHIPTOP_BASE + 0x74) ++#define REG_CHIPTOP_3A_H (REG_CHIPTOP_BASE + 0x75) ++#define REG_CHIPTOP_3B_L (REG_CHIPTOP_BASE + 0x76) ++#define REG_CHIPTOP_3B_H (REG_CHIPTOP_BASE + 0x77) ++#define REG_CHIPTOP_3C_L (REG_CHIPTOP_BASE + 0x78) ++#define REG_CHIPTOP_3C_H (REG_CHIPTOP_BASE + 0x79) ++#define REG_CHIPTOP_3D_L (REG_CHIPTOP_BASE + 0x7A) ++#define REG_CHIPTOP_3D_H (REG_CHIPTOP_BASE + 0x7B) ++#define REG_CHIPTOP_3E_L (REG_CHIPTOP_BASE + 0x7C) ++#define REG_CHIPTOP_3E_H (REG_CHIPTOP_BASE + 0x7D) ++#define REG_CHIPTOP_3F_L (REG_CHIPTOP_BASE + 0x7E) ++#define REG_CHIPTOP_3F_H (REG_CHIPTOP_BASE + 0x7F) ++#define REG_CHIPTOP_40_L (REG_CHIPTOP_BASE + 0x80) ++#define REG_CHIPTOP_40_H (REG_CHIPTOP_BASE + 0x81) ++#define REG_CHIPTOP_41_L (REG_CHIPTOP_BASE + 0x82) ++#define REG_CHIPTOP_41_H (REG_CHIPTOP_BASE + 0x83) ++#define REG_CHIPTOP_42_L (REG_CHIPTOP_BASE + 0x84) ++#define REG_CHIPTOP_42_H (REG_CHIPTOP_BASE + 0x85) ++#define REG_CHIPTOP_43_L (REG_CHIPTOP_BASE + 0x86) ++#define REG_CHIPTOP_43_H (REG_CHIPTOP_BASE + 0x87) ++#define REG_CHIPTOP_44_L (REG_CHIPTOP_BASE + 0x88) ++#define REG_CHIPTOP_44_H (REG_CHIPTOP_BASE + 0x89) ++#define REG_CHIPTOP_45_L (REG_CHIPTOP_BASE + 0x8A) ++#define REG_CHIPTOP_45_H (REG_CHIPTOP_BASE + 0x8B) ++#define REG_CHIPTOP_46_L (REG_CHIPTOP_BASE + 0x8C) ++#define REG_CHIPTOP_46_H (REG_CHIPTOP_BASE + 0x8D) ++#define REG_CHIPTOP_47_L (REG_CHIPTOP_BASE + 0x8E) ++#define REG_CHIPTOP_47_H (REG_CHIPTOP_BASE + 0x8F) ++#define REG_CHIPTOP_48_L (REG_CHIPTOP_BASE + 0x90) ++#define REG_CHIPTOP_48_H (REG_CHIPTOP_BASE + 0x91) ++#define REG_CHIPTOP_49_L (REG_CHIPTOP_BASE + 0x92) ++#define REG_CHIPTOP_49_H (REG_CHIPTOP_BASE + 0x93) ++#define REG_CHIPTOP_4A_L (REG_CHIPTOP_BASE + 0x94) ++#define REG_CHIPTOP_4A_H (REG_CHIPTOP_BASE + 0x95) ++#define REG_CHIPTOP_4B_L (REG_CHIPTOP_BASE + 0x96) ++#define REG_CHIPTOP_4B_H (REG_CHIPTOP_BASE + 0x97) ++#define REG_CHIPTOP_4C_L (REG_CHIPTOP_BASE + 0x98) ++#define REG_CHIPTOP_4C_H (REG_CHIPTOP_BASE + 0x99) ++#define REG_CHIPTOP_4D_L (REG_CHIPTOP_BASE + 0x9A) ++#define REG_CHIPTOP_4D_H (REG_CHIPTOP_BASE + 0x9B) ++#define REG_CHIPTOP_4E_L (REG_CHIPTOP_BASE + 0x9C) ++#define REG_CHIPTOP_4E_H (REG_CHIPTOP_BASE + 0x9D) ++#define REG_CHIPTOP_4F_L (REG_CHIPTOP_BASE + 0x9E) ++#define REG_CHIPTOP_4F_H (REG_CHIPTOP_BASE + 0x9F) ++#define REG_CHIPTOP_50_L (REG_CHIPTOP_BASE + 0xA0) ++#define REG_CHIPTOP_50_H (REG_CHIPTOP_BASE + 0xA1) ++#define REG_CHIPTOP_51_L (REG_CHIPTOP_BASE + 0xA2) ++#define REG_CHIPTOP_51_H (REG_CHIPTOP_BASE + 0xA3) ++#define REG_CHIPTOP_52_L (REG_CHIPTOP_BASE + 0xA4) ++#define REG_CHIPTOP_52_H (REG_CHIPTOP_BASE + 0xA5) ++#define REG_CHIPTOP_53_L (REG_CHIPTOP_BASE + 0xA6) ++#define REG_CHIPTOP_53_H (REG_CHIPTOP_BASE + 0xA7) ++#define REG_CHIPTOP_54_L (REG_CHIPTOP_BASE + 0xA8) ++#define REG_CHIPTOP_54_H (REG_CHIPTOP_BASE + 0xA9) ++#define REG_CHIPTOP_55_L (REG_CHIPTOP_BASE + 0xAA) ++#define REG_CHIPTOP_55_H (REG_CHIPTOP_BASE + 0xAB) ++#define REG_CHIPTOP_56_L (REG_CHIPTOP_BASE + 0xAC) ++#define REG_CHIPTOP_56_H (REG_CHIPTOP_BASE + 0xAD) ++#define REG_CHIPTOP_57_L (REG_CHIPTOP_BASE + 0xAE) ++#define REG_CHIPTOP_57_H (REG_CHIPTOP_BASE + 0xAF) ++#define REG_CHIPTOP_58_L (REG_CHIPTOP_BASE + 0xB0) ++#define REG_CHIPTOP_58_H (REG_CHIPTOP_BASE + 0xB1) ++#define REG_CHIPTOP_59_L (REG_CHIPTOP_BASE + 0xB2) ++#define REG_CHIPTOP_59_H (REG_CHIPTOP_BASE + 0xB3) ++#define REG_CHIPTOP_5A_L (REG_CHIPTOP_BASE + 0xB4) ++#define REG_CHIPTOP_5A_H (REG_CHIPTOP_BASE + 0xB5) ++#define REG_CHIPTOP_5B_L (REG_CHIPTOP_BASE + 0xB6) ++#define REG_CHIPTOP_5B_H (REG_CHIPTOP_BASE + 0xB7) ++#define REG_CHIPTOP_5C_L (REG_CHIPTOP_BASE + 0xB8) ++#define REG_CHIPTOP_5C_H (REG_CHIPTOP_BASE + 0xB9) ++#define REG_CHIPTOP_5D_L (REG_CHIPTOP_BASE + 0xBA) ++#define REG_CHIPTOP_5D_H (REG_CHIPTOP_BASE + 0xBB) ++#define REG_CHIPTOP_5E_L (REG_CHIPTOP_BASE + 0xBC) ++#define REG_CHIPTOP_5E_H (REG_CHIPTOP_BASE + 0xBD) ++#define REG_CHIPTOP_5F_L (REG_CHIPTOP_BASE + 0xBE) ++#define REG_CHIPTOP_5F_H (REG_CHIPTOP_BASE + 0xBF) ++#define REG_CHIPTOP_60_L (REG_CHIPTOP_BASE + 0xC0) ++#define REG_CHIPTOP_60_H (REG_CHIPTOP_BASE + 0xC1) ++#define REG_CHIPTOP_61_L (REG_CHIPTOP_BASE + 0xC2) ++#define REG_CHIPTOP_61_H (REG_CHIPTOP_BASE + 0xC3) ++#define REG_CHIPTOP_62_L (REG_CHIPTOP_BASE + 0xC4) ++#define REG_CHIPTOP_62_H (REG_CHIPTOP_BASE + 0xC5) ++#define REG_CHIPTOP_63_L (REG_CHIPTOP_BASE + 0xC6) ++#define REG_CHIPTOP_63_H (REG_CHIPTOP_BASE + 0xC7) ++#define REG_CHIPTOP_64_L (REG_CHIPTOP_BASE + 0xC8) ++#define REG_CHIPTOP_64_H (REG_CHIPTOP_BASE + 0xC9) ++#define REG_CHIPTOP_65_L (REG_CHIPTOP_BASE + 0xCA) ++#define REG_CHIPTOP_65_H (REG_CHIPTOP_BASE + 0xCB) ++#define REG_CHIPTOP_66_L (REG_CHIPTOP_BASE + 0xCC) ++#define REG_CHIPTOP_66_H (REG_CHIPTOP_BASE + 0xCD) ++#define REG_CHIPTOP_67_L (REG_CHIPTOP_BASE + 0xCE) ++#define REG_CHIPTOP_67_H (REG_CHIPTOP_BASE + 0xCF) ++#define REG_CHIPTOP_68_L (REG_CHIPTOP_BASE + 0xD0) ++#define REG_CHIPTOP_68_H (REG_CHIPTOP_BASE + 0xD1) ++#define REG_CHIPTOP_69_L (REG_CHIPTOP_BASE + 0xD2) ++#define REG_CHIPTOP_69_H (REG_CHIPTOP_BASE + 0xD3) ++#define REG_CHIPTOP_6A_L (REG_CHIPTOP_BASE + 0xD4) ++#define REG_CHIPTOP_6A_H (REG_CHIPTOP_BASE + 0xD5) ++#define REG_CHIPTOP_6B_L (REG_CHIPTOP_BASE + 0xD6) ++#define REG_CHIPTOP_6B_H (REG_CHIPTOP_BASE + 0xD7) ++#define REG_CHIPTOP_6C_L (REG_CHIPTOP_BASE + 0xD8) ++#define REG_CHIPTOP_6C_H (REG_CHIPTOP_BASE + 0xD9) ++#define REG_CHIPTOP_6D_L (REG_CHIPTOP_BASE + 0xDA) ++#define REG_CHIPTOP_6D_H (REG_CHIPTOP_BASE + 0xDB) ++#define REG_CHIPTOP_6E_L (REG_CHIPTOP_BASE + 0xDC) ++#define REG_CHIPTOP_6E_H (REG_CHIPTOP_BASE + 0xDD) ++#define REG_CHIPTOP_6F_L (REG_CHIPTOP_BASE + 0xDE) ++#define REG_CHIPTOP_6F_H (REG_CHIPTOP_BASE + 0xDF) ++#define REG_CHIPTOP_70_L (REG_CHIPTOP_BASE + 0xE0) ++#define REG_CHIPTOP_70_H (REG_CHIPTOP_BASE + 0xE1) ++#define REG_CHIPTOP_71_L (REG_CHIPTOP_BASE + 0xE2) ++#define REG_CHIPTOP_71_H (REG_CHIPTOP_BASE + 0xE3) ++#define REG_CHIPTOP_72_L (REG_CHIPTOP_BASE + 0xE4) ++#define REG_CHIPTOP_72_H (REG_CHIPTOP_BASE + 0xE5) ++#define REG_CHIPTOP_73_L (REG_CHIPTOP_BASE + 0xE6) ++#define REG_CHIPTOP_73_H (REG_CHIPTOP_BASE + 0xE7) ++#define REG_CHIPTOP_74_L (REG_CHIPTOP_BASE + 0xE8) ++#define REG_CHIPTOP_74_H (REG_CHIPTOP_BASE + 0xE9) ++#define REG_CHIPTOP_75_L (REG_CHIPTOP_BASE + 0xEA) ++#define REG_CHIPTOP_75_H (REG_CHIPTOP_BASE + 0xEB) ++#define REG_CHIPTOP_76_L (REG_CHIPTOP_BASE + 0xEC) ++#define REG_CHIPTOP_76_H (REG_CHIPTOP_BASE + 0xED) ++#define REG_CHIPTOP_77_L (REG_CHIPTOP_BASE + 0xEE) ++#define REG_CHIPTOP_77_H (REG_CHIPTOP_BASE + 0xEF) ++#define REG_CHIPTOP_78_L (REG_CHIPTOP_BASE + 0xF0) ++#define REG_CHIPTOP_78_H (REG_CHIPTOP_BASE + 0xF1) ++#define REG_CHIPTOP_79_L (REG_CHIPTOP_BASE + 0xF2) ++#define REG_CHIPTOP_79_H (REG_CHIPTOP_BASE + 0xF3) ++#define REG_CHIPTOP_7A_L (REG_CHIPTOP_BASE + 0xF4) ++#define REG_CHIPTOP_7A_H (REG_CHIPTOP_BASE + 0xF5) ++#define REG_CHIPTOP_7B_L (REG_CHIPTOP_BASE + 0xF6) ++#define REG_CHIPTOP_7B_H (REG_CHIPTOP_BASE + 0xF7) ++#define REG_CHIPTOP_7C_L (REG_CHIPTOP_BASE + 0xF8) ++#define REG_CHIPTOP_7C_H (REG_CHIPTOP_BASE + 0xF9) ++#define REG_CHIPTOP_7D_L (REG_CHIPTOP_BASE + 0xFA) ++#define REG_CHIPTOP_7D_H (REG_CHIPTOP_BASE + 0xFB) ++#define REG_CHIPTOP_7E_L (REG_CHIPTOP_BASE + 0xFC) ++#define REG_CHIPTOP_7E_H (REG_CHIPTOP_BASE + 0xFD) ++#define REG_CHIPTOP_7F_L (REG_CHIPTOP_BASE + 0xFE) ++#define REG_CHIPTOP_7F_H (REG_CHIPTOP_BASE + 0xFF) ++ ++ ++#define REG_SCL_CLK_00_L (REG_SCL_CLK_BASE + 0x00) ++#define REG_SCL_CLK_00_H (REG_SCL_CLK_BASE + 0x01) ++#define REG_SCL_CLK_01_L (REG_SCL_CLK_BASE + 0x02) ++#define REG_SCL_CLK_01_H (REG_SCL_CLK_BASE + 0x03) ++#define REG_SCL_CLK_02_L (REG_SCL_CLK_BASE + 0x04) ++#define REG_SCL_CLK_02_H (REG_SCL_CLK_BASE + 0x05) ++#define REG_SCL_CLK_03_L (REG_SCL_CLK_BASE + 0x06) ++#define REG_SCL_CLK_03_H (REG_SCL_CLK_BASE + 0x07) ++#define REG_SCL_CLK_04_L (REG_SCL_CLK_BASE + 0x08) ++#define REG_SCL_CLK_04_H (REG_SCL_CLK_BASE + 0x09) ++#define REG_SCL_CLK_05_L (REG_SCL_CLK_BASE + 0x0A) ++#define REG_SCL_CLK_05_H (REG_SCL_CLK_BASE + 0x0B) ++#define REG_SCL_CLK_06_L (REG_SCL_CLK_BASE + 0x0C) ++#define REG_SCL_CLK_06_H (REG_SCL_CLK_BASE + 0x0D) ++#define REG_SCL_CLK_07_L (REG_SCL_CLK_BASE + 0x0E) ++#define REG_SCL_CLK_07_H (REG_SCL_CLK_BASE + 0x0F) ++#define REG_SCL_CLK_08_L (REG_SCL_CLK_BASE + 0x10) ++#define REG_SCL_CLK_08_H (REG_SCL_CLK_BASE + 0x11) ++#define REG_SCL_CLK_09_L (REG_SCL_CLK_BASE + 0x12) ++#define REG_SCL_CLK_09_H (REG_SCL_CLK_BASE + 0x13) ++#define REG_SCL_CLK_0A_L (REG_SCL_CLK_BASE + 0x14) ++#define REG_SCL_CLK_0A_H (REG_SCL_CLK_BASE + 0x15) ++#define REG_SCL_CLK_0B_L (REG_SCL_CLK_BASE + 0x16) ++#define REG_SCL_CLK_0B_H (REG_SCL_CLK_BASE + 0x17) ++#define REG_SCL_CLK_0C_L (REG_SCL_CLK_BASE + 0x18) ++#define REG_SCL_CLK_0C_H (REG_SCL_CLK_BASE + 0x19) ++#define REG_SCL_CLK_0D_L (REG_SCL_CLK_BASE + 0x1A) ++#define REG_SCL_CLK_0D_H (REG_SCL_CLK_BASE + 0x1B) ++#define REG_SCL_CLK_0E_L (REG_SCL_CLK_BASE + 0x1C) ++#define REG_SCL_CLK_0E_H (REG_SCL_CLK_BASE + 0x1D) ++#define REG_SCL_CLK_0F_L (REG_SCL_CLK_BASE + 0x1E) ++#define REG_SCL_CLK_0F_H (REG_SCL_CLK_BASE + 0x1F) ++#define REG_SCL_CLK_10_L (REG_SCL_CLK_BASE + 0x20) ++#define REG_SCL_CLK_10_H (REG_SCL_CLK_BASE + 0x21) ++#define REG_SCL_CLK_11_L (REG_SCL_CLK_BASE + 0x22) ++#define REG_SCL_CLK_11_H (REG_SCL_CLK_BASE + 0x23) ++#define REG_SCL_CLK_12_L (REG_SCL_CLK_BASE + 0x24) ++#define REG_SCL_CLK_12_H (REG_SCL_CLK_BASE + 0x25) ++#define REG_SCL_CLK_13_L (REG_SCL_CLK_BASE + 0x26) ++#define REG_SCL_CLK_13_H (REG_SCL_CLK_BASE + 0x27) ++#define REG_SCL_CLK_14_L (REG_SCL_CLK_BASE + 0x28) ++#define REG_SCL_CLK_14_H (REG_SCL_CLK_BASE + 0x29) ++#define REG_SCL_CLK_15_L (REG_SCL_CLK_BASE + 0x2A) ++#define REG_SCL_CLK_15_H (REG_SCL_CLK_BASE + 0x2B) ++#define REG_SCL_CLK_16_L (REG_SCL_CLK_BASE + 0x2C) ++#define REG_SCL_CLK_16_H (REG_SCL_CLK_BASE + 0x2D) ++#define REG_SCL_CLK_17_L (REG_SCL_CLK_BASE + 0x2E) ++#define REG_SCL_CLK_17_H (REG_SCL_CLK_BASE + 0x2F) ++#define REG_SCL_CLK_18_L (REG_SCL_CLK_BASE + 0x30) ++#define REG_SCL_CLK_18_H (REG_SCL_CLK_BASE + 0x31) ++#define REG_SCL_CLK_19_L (REG_SCL_CLK_BASE + 0x32) ++#define REG_SCL_CLK_19_H (REG_SCL_CLK_BASE + 0x33) ++#define REG_SCL_CLK_1A_L (REG_SCL_CLK_BASE + 0x34) ++#define REG_SCL_CLK_1A_H (REG_SCL_CLK_BASE + 0x35) ++#define REG_SCL_CLK_1B_L (REG_SCL_CLK_BASE + 0x36) ++#define REG_SCL_CLK_1B_H (REG_SCL_CLK_BASE + 0x37) ++#define REG_SCL_CLK_1C_L (REG_SCL_CLK_BASE + 0x38) ++#define REG_SCL_CLK_1C_H (REG_SCL_CLK_BASE + 0x39) ++#define REG_SCL_CLK_1D_L (REG_SCL_CLK_BASE + 0x3A) ++#define REG_SCL_CLK_1D_H (REG_SCL_CLK_BASE + 0x3B) ++#define REG_SCL_CLK_1E_L (REG_SCL_CLK_BASE + 0x3C) ++#define REG_SCL_CLK_1E_H (REG_SCL_CLK_BASE + 0x3D) ++#define REG_SCL_CLK_1F_L (REG_SCL_CLK_BASE + 0x3E) ++#define REG_SCL_CLK_1F_H (REG_SCL_CLK_BASE + 0x3F) ++#define REG_SCL_CLK_20_L (REG_SCL_CLK_BASE + 0x40) ++#define REG_SCL_CLK_20_H (REG_SCL_CLK_BASE + 0x41) ++#define REG_SCL_CLK_21_L (REG_SCL_CLK_BASE + 0x42) ++#define REG_SCL_CLK_21_H (REG_SCL_CLK_BASE + 0x43) ++#define REG_SCL_CLK_22_L (REG_SCL_CLK_BASE + 0x44) ++#define REG_SCL_CLK_22_H (REG_SCL_CLK_BASE + 0x45) ++#define REG_SCL_CLK_23_L (REG_SCL_CLK_BASE + 0x46) ++#define REG_SCL_CLK_23_H (REG_SCL_CLK_BASE + 0x47) ++#define REG_SCL_CLK_24_L (REG_SCL_CLK_BASE + 0x48) ++#define REG_SCL_CLK_24_H (REG_SCL_CLK_BASE + 0x49) ++#define REG_SCL_CLK_25_L (REG_SCL_CLK_BASE + 0x4A) ++#define REG_SCL_CLK_25_H (REG_SCL_CLK_BASE + 0x4B) ++#define REG_SCL_CLK_26_L (REG_SCL_CLK_BASE + 0x4C) ++#define REG_SCL_CLK_26_H (REG_SCL_CLK_BASE + 0x4D) ++#define REG_SCL_CLK_27_L (REG_SCL_CLK_BASE + 0x4E) ++#define REG_SCL_CLK_27_H (REG_SCL_CLK_BASE + 0x4F) ++#define REG_SCL_CLK_28_L (REG_SCL_CLK_BASE + 0x50) ++#define REG_SCL_CLK_28_H (REG_SCL_CLK_BASE + 0x51) ++#define REG_SCL_CLK_29_L (REG_SCL_CLK_BASE + 0x52) ++#define REG_SCL_CLK_29_H (REG_SCL_CLK_BASE + 0x53) ++#define REG_SCL_CLK_2A_L (REG_SCL_CLK_BASE + 0x54) ++#define REG_SCL_CLK_2A_H (REG_SCL_CLK_BASE + 0x55) ++#define REG_SCL_CLK_2B_L (REG_SCL_CLK_BASE + 0x56) ++#define REG_SCL_CLK_2B_H (REG_SCL_CLK_BASE + 0x57) ++#define REG_SCL_CLK_2C_L (REG_SCL_CLK_BASE + 0x58) ++#define REG_SCL_CLK_2C_H (REG_SCL_CLK_BASE + 0x59) ++#define REG_SCL_CLK_2D_L (REG_SCL_CLK_BASE + 0x5A) ++#define REG_SCL_CLK_2D_H (REG_SCL_CLK_BASE + 0x5B) ++#define REG_SCL_CLK_2E_L (REG_SCL_CLK_BASE + 0x5C) ++#define REG_SCL_CLK_2E_H (REG_SCL_CLK_BASE + 0x5D) ++#define REG_SCL_CLK_2F_L (REG_SCL_CLK_BASE + 0x5E) ++#define REG_SCL_CLK_2F_H (REG_SCL_CLK_BASE + 0x5F) ++#define REG_SCL_CLK_30_L (REG_SCL_CLK_BASE + 0x60) ++#define REG_SCL_CLK_30_H (REG_SCL_CLK_BASE + 0x61) ++#define REG_SCL_CLK_31_L (REG_SCL_CLK_BASE + 0x62) ++#define REG_SCL_CLK_31_H (REG_SCL_CLK_BASE + 0x63) ++#define REG_SCL_CLK_32_L (REG_SCL_CLK_BASE + 0x64) ++#define REG_SCL_CLK_32_H (REG_SCL_CLK_BASE + 0x65) ++#define REG_SCL_CLK_33_L (REG_SCL_CLK_BASE + 0x66) ++#define REG_SCL_CLK_33_H (REG_SCL_CLK_BASE + 0x67) ++#define REG_SCL_CLK_34_L (REG_SCL_CLK_BASE + 0x68) ++#define REG_SCL_CLK_34_H (REG_SCL_CLK_BASE + 0x69) ++#define REG_SCL_CLK_35_L (REG_SCL_CLK_BASE + 0x6A) ++#define REG_SCL_CLK_35_H (REG_SCL_CLK_BASE + 0x6B) ++#define REG_SCL_CLK_36_L (REG_SCL_CLK_BASE + 0x6C) ++#define REG_SCL_CLK_36_H (REG_SCL_CLK_BASE + 0x6D) ++#define REG_SCL_CLK_37_L (REG_SCL_CLK_BASE + 0x6E) ++#define REG_SCL_CLK_37_H (REG_SCL_CLK_BASE + 0x6F) ++#define REG_SCL_CLK_38_L (REG_SCL_CLK_BASE + 0x70) ++#define REG_SCL_CLK_38_H (REG_SCL_CLK_BASE + 0x71) ++#define REG_SCL_CLK_39_L (REG_SCL_CLK_BASE + 0x72) ++#define REG_SCL_CLK_39_H (REG_SCL_CLK_BASE + 0x73) ++#define REG_SCL_CLK_3A_L (REG_SCL_CLK_BASE + 0x74) ++#define REG_SCL_CLK_3A_H (REG_SCL_CLK_BASE + 0x75) ++#define REG_SCL_CLK_3B_L (REG_SCL_CLK_BASE + 0x76) ++#define REG_SCL_CLK_3B_H (REG_SCL_CLK_BASE + 0x77) ++#define REG_SCL_CLK_3C_L (REG_SCL_CLK_BASE + 0x78) ++#define REG_SCL_CLK_3C_H (REG_SCL_CLK_BASE + 0x79) ++#define REG_SCL_CLK_3D_L (REG_SCL_CLK_BASE + 0x7A) ++#define REG_SCL_CLK_3D_H (REG_SCL_CLK_BASE + 0x7B) ++#define REG_SCL_CLK_3E_L (REG_SCL_CLK_BASE + 0x7C) ++#define REG_SCL_CLK_3E_H (REG_SCL_CLK_BASE + 0x7D) ++#define REG_SCL_CLK_3F_L (REG_SCL_CLK_BASE + 0x7E) ++#define REG_SCL_CLK_3F_H (REG_SCL_CLK_BASE + 0x7F) ++#define REG_SCL_CLK_40_L (REG_SCL_CLK_BASE + 0x80) ++#define REG_SCL_CLK_40_H (REG_SCL_CLK_BASE + 0x81) ++#define REG_SCL_CLK_41_L (REG_SCL_CLK_BASE + 0x82) ++#define REG_SCL_CLK_41_H (REG_SCL_CLK_BASE + 0x83) ++#define REG_SCL_CLK_42_L (REG_SCL_CLK_BASE + 0x84) ++#define REG_SCL_CLK_42_H (REG_SCL_CLK_BASE + 0x85) ++#define REG_SCL_CLK_43_L (REG_SCL_CLK_BASE + 0x86) ++#define REG_SCL_CLK_43_H (REG_SCL_CLK_BASE + 0x87) ++#define REG_SCL_CLK_44_L (REG_SCL_CLK_BASE + 0x88) ++#define REG_SCL_CLK_44_H (REG_SCL_CLK_BASE + 0x89) ++#define REG_SCL_CLK_45_L (REG_SCL_CLK_BASE + 0x8A) ++#define REG_SCL_CLK_45_H (REG_SCL_CLK_BASE + 0x8B) ++#define REG_SCL_CLK_46_L (REG_SCL_CLK_BASE + 0x8C) ++#define REG_SCL_CLK_46_H (REG_SCL_CLK_BASE + 0x8D) ++#define REG_SCL_CLK_47_L (REG_SCL_CLK_BASE + 0x8E) ++#define REG_SCL_CLK_47_H (REG_SCL_CLK_BASE + 0x8F) ++#define REG_SCL_CLK_48_L (REG_SCL_CLK_BASE + 0x90) ++#define REG_SCL_CLK_48_H (REG_SCL_CLK_BASE + 0x91) ++#define REG_SCL_CLK_49_L (REG_SCL_CLK_BASE + 0x92) ++#define REG_SCL_CLK_49_H (REG_SCL_CLK_BASE + 0x93) ++#define REG_SCL_CLK_4A_L (REG_SCL_CLK_BASE + 0x94) ++#define REG_SCL_CLK_4A_H (REG_SCL_CLK_BASE + 0x95) ++#define REG_SCL_CLK_4B_L (REG_SCL_CLK_BASE + 0x96) ++#define REG_SCL_CLK_4B_H (REG_SCL_CLK_BASE + 0x97) ++#define REG_SCL_CLK_4C_L (REG_SCL_CLK_BASE + 0x98) ++#define REG_SCL_CLK_4C_H (REG_SCL_CLK_BASE + 0x99) ++#define REG_SCL_CLK_4D_L (REG_SCL_CLK_BASE + 0x9A) ++#define REG_SCL_CLK_4D_H (REG_SCL_CLK_BASE + 0x9B) ++#define REG_SCL_CLK_4E_L (REG_SCL_CLK_BASE + 0x9C) ++#define REG_SCL_CLK_4E_H (REG_SCL_CLK_BASE + 0x9D) ++#define REG_SCL_CLK_4F_L (REG_SCL_CLK_BASE + 0x9E) ++#define REG_SCL_CLK_4F_H (REG_SCL_CLK_BASE + 0x9F) ++#define REG_SCL_CLK_50_L (REG_SCL_CLK_BASE + 0xA0) ++#define REG_SCL_CLK_50_H (REG_SCL_CLK_BASE + 0xA1) ++#define REG_SCL_CLK_51_L (REG_SCL_CLK_BASE + 0xA2) ++#define REG_SCL_CLK_51_H (REG_SCL_CLK_BASE + 0xA3) ++#define REG_SCL_CLK_52_L (REG_SCL_CLK_BASE + 0xA4) ++#define REG_SCL_CLK_52_H (REG_SCL_CLK_BASE + 0xA5) ++#define REG_SCL_CLK_53_L (REG_SCL_CLK_BASE + 0xA6) ++#define REG_SCL_CLK_53_H (REG_SCL_CLK_BASE + 0xA7) ++#define REG_SCL_CLK_54_L (REG_SCL_CLK_BASE + 0xA8) ++#define REG_SCL_CLK_54_H (REG_SCL_CLK_BASE + 0xA9) ++#define REG_SCL_CLK_55_L (REG_SCL_CLK_BASE + 0xAA) ++#define REG_SCL_CLK_55_H (REG_SCL_CLK_BASE + 0xAB) ++#define REG_SCL_CLK_56_L (REG_SCL_CLK_BASE + 0xAC) ++#define REG_SCL_CLK_56_H (REG_SCL_CLK_BASE + 0xAD) ++#define REG_SCL_CLK_57_L (REG_SCL_CLK_BASE + 0xAE) ++#define REG_SCL_CLK_57_H (REG_SCL_CLK_BASE + 0xAF) ++#define REG_SCL_CLK_58_L (REG_SCL_CLK_BASE + 0xB0) ++#define REG_SCL_CLK_58_H (REG_SCL_CLK_BASE + 0xB1) ++#define REG_SCL_CLK_59_L (REG_SCL_CLK_BASE + 0xB2) ++#define REG_SCL_CLK_59_H (REG_SCL_CLK_BASE + 0xB3) ++#define REG_SCL_CLK_5A_L (REG_SCL_CLK_BASE + 0xB4) ++#define REG_SCL_CLK_5A_H (REG_SCL_CLK_BASE + 0xB5) ++#define REG_SCL_CLK_5B_L (REG_SCL_CLK_BASE + 0xB6) ++#define REG_SCL_CLK_5B_H (REG_SCL_CLK_BASE + 0xB7) ++#define REG_SCL_CLK_5C_L (REG_SCL_CLK_BASE + 0xB8) ++#define REG_SCL_CLK_5C_H (REG_SCL_CLK_BASE + 0xB9) ++#define REG_SCL_CLK_5D_L (REG_SCL_CLK_BASE + 0xBA) ++#define REG_SCL_CLK_5D_H (REG_SCL_CLK_BASE + 0xBB) ++#define REG_SCL_CLK_5E_L (REG_SCL_CLK_BASE + 0xBC) ++#define REG_SCL_CLK_5E_H (REG_SCL_CLK_BASE + 0xBD) ++#define REG_SCL_CLK_5F_L (REG_SCL_CLK_BASE + 0xBE) ++#define REG_SCL_CLK_5F_H (REG_SCL_CLK_BASE + 0xBF) ++#define REG_SCL_CLK_60_L (REG_SCL_CLK_BASE + 0xC0) ++#define REG_SCL_CLK_60_H (REG_SCL_CLK_BASE + 0xC1) ++#define REG_SCL_CLK_61_L (REG_SCL_CLK_BASE + 0xC2) ++#define REG_SCL_CLK_61_H (REG_SCL_CLK_BASE + 0xC3) ++#define REG_SCL_CLK_62_L (REG_SCL_CLK_BASE + 0xC4) ++#define REG_SCL_CLK_62_H (REG_SCL_CLK_BASE + 0xC5) ++#define REG_SCL_CLK_63_L (REG_SCL_CLK_BASE + 0xC6) ++#define REG_SCL_CLK_63_H (REG_SCL_CLK_BASE + 0xC7) ++#define REG_SCL_CLK_64_L (REG_SCL_CLK_BASE + 0xC8) ++#define REG_SCL_CLK_64_H (REG_SCL_CLK_BASE + 0xC9) ++#define REG_SCL_CLK_65_L (REG_SCL_CLK_BASE + 0xCA) ++#define REG_SCL_CLK_65_H (REG_SCL_CLK_BASE + 0xCB) ++#define REG_SCL_CLK_66_L (REG_SCL_CLK_BASE + 0xCC) ++#define REG_SCL_CLK_66_H (REG_SCL_CLK_BASE + 0xCD) ++#define REG_SCL_CLK_67_L (REG_SCL_CLK_BASE + 0xCE) ++#define REG_SCL_CLK_67_H (REG_SCL_CLK_BASE + 0xCF) ++#define REG_SCL_CLK_68_L (REG_SCL_CLK_BASE + 0xD0) ++#define REG_SCL_CLK_68_H (REG_SCL_CLK_BASE + 0xD1) ++#define REG_SCL_CLK_69_L (REG_SCL_CLK_BASE + 0xD2) ++#define REG_SCL_CLK_69_H (REG_SCL_CLK_BASE + 0xD3) ++#define REG_SCL_CLK_6A_L (REG_SCL_CLK_BASE + 0xD4) ++#define REG_SCL_CLK_6A_H (REG_SCL_CLK_BASE + 0xD5) ++#define REG_SCL_CLK_6B_L (REG_SCL_CLK_BASE + 0xD6) ++#define REG_SCL_CLK_6B_H (REG_SCL_CLK_BASE + 0xD7) ++#define REG_SCL_CLK_6C_L (REG_SCL_CLK_BASE + 0xD8) ++#define REG_SCL_CLK_6C_H (REG_SCL_CLK_BASE + 0xD9) ++#define REG_SCL_CLK_6D_L (REG_SCL_CLK_BASE + 0xDA) ++#define REG_SCL_CLK_6D_H (REG_SCL_CLK_BASE + 0xDB) ++#define REG_SCL_CLK_6E_L (REG_SCL_CLK_BASE + 0xDC) ++#define REG_SCL_CLK_6E_H (REG_SCL_CLK_BASE + 0xDD) ++#define REG_SCL_CLK_6F_L (REG_SCL_CLK_BASE + 0xDE) ++#define REG_SCL_CLK_6F_H (REG_SCL_CLK_BASE + 0xDF) ++#define REG_SCL_CLK_70_L (REG_SCL_CLK_BASE + 0xE0) ++#define REG_SCL_CLK_70_H (REG_SCL_CLK_BASE + 0xE1) ++#define REG_SCL_CLK_71_L (REG_SCL_CLK_BASE + 0xE2) ++#define REG_SCL_CLK_71_H (REG_SCL_CLK_BASE + 0xE3) ++#define REG_SCL_CLK_72_L (REG_SCL_CLK_BASE + 0xE4) ++#define REG_SCL_CLK_72_H (REG_SCL_CLK_BASE + 0xE5) ++#define REG_SCL_CLK_73_L (REG_SCL_CLK_BASE + 0xE6) ++#define REG_SCL_CLK_73_H (REG_SCL_CLK_BASE + 0xE7) ++#define REG_SCL_CLK_74_L (REG_SCL_CLK_BASE + 0xE8) ++#define REG_SCL_CLK_74_H (REG_SCL_CLK_BASE + 0xE9) ++#define REG_SCL_CLK_75_L (REG_SCL_CLK_BASE + 0xEA) ++#define REG_SCL_CLK_75_H (REG_SCL_CLK_BASE + 0xEB) ++#define REG_SCL_CLK_76_L (REG_SCL_CLK_BASE + 0xEC) ++#define REG_SCL_CLK_76_H (REG_SCL_CLK_BASE + 0xED) ++#define REG_SCL_CLK_77_L (REG_SCL_CLK_BASE + 0xEE) ++#define REG_SCL_CLK_77_H (REG_SCL_CLK_BASE + 0xEF) ++#define REG_SCL_CLK_78_L (REG_SCL_CLK_BASE + 0xF0) ++#define REG_SCL_CLK_78_H (REG_SCL_CLK_BASE + 0xF1) ++#define REG_SCL_CLK_79_L (REG_SCL_CLK_BASE + 0xF2) ++#define REG_SCL_CLK_79_H (REG_SCL_CLK_BASE + 0xF3) ++#define REG_SCL_CLK_7A_L (REG_SCL_CLK_BASE + 0xF4) ++#define REG_SCL_CLK_7A_H (REG_SCL_CLK_BASE + 0xF5) ++#define REG_SCL_CLK_7B_L (REG_SCL_CLK_BASE + 0xF6) ++#define REG_SCL_CLK_7B_H (REG_SCL_CLK_BASE + 0xF7) ++#define REG_SCL_CLK_7C_L (REG_SCL_CLK_BASE + 0xF8) ++#define REG_SCL_CLK_7C_H (REG_SCL_CLK_BASE + 0xF9) ++#define REG_SCL_CLK_7D_L (REG_SCL_CLK_BASE + 0xFA) ++#define REG_SCL_CLK_7D_H (REG_SCL_CLK_BASE + 0xFB) ++#define REG_SCL_CLK_7E_L (REG_SCL_CLK_BASE + 0xFC) ++#define REG_SCL_CLK_7E_H (REG_SCL_CLK_BASE + 0xFD) ++#define REG_SCL_CLK_7F_L (REG_SCL_CLK_BASE + 0xFE) ++#define REG_SCL_CLK_7F_H (REG_SCL_CLK_BASE + 0xFF) ++ ++#define REG_BLOCK_24_L (REG_BLOCK_BASE + 0x48) ++#define REG_BLOCK_24_H (REG_BLOCK_BASE + 0x49) ++ ++#define REG_SCL_LPLL_00_L (REG_SCL_LPLL_BASE + 0x00) ++#define REG_SCL_LPLL_00_H (REG_SCL_LPLL_BASE + 0x01) ++#define REG_SCL_LPLL_01_L (REG_SCL_LPLL_BASE + 0x02) ++#define REG_SCL_LPLL_01_H (REG_SCL_LPLL_BASE + 0x03) ++#define REG_SCL_LPLL_02_L (REG_SCL_LPLL_BASE + 0x04) ++#define REG_SCL_LPLL_02_H (REG_SCL_LPLL_BASE + 0x05) ++#define REG_SCL_LPLL_03_L (REG_SCL_LPLL_BASE + 0x06) ++#define REG_SCL_LPLL_03_H (REG_SCL_LPLL_BASE + 0x07) ++#define REG_SCL_LPLL_04_L (REG_SCL_LPLL_BASE + 0x08) ++#define REG_SCL_LPLL_04_H (REG_SCL_LPLL_BASE + 0x09) ++#define REG_SCL_LPLL_05_L (REG_SCL_LPLL_BASE + 0x0A) ++#define REG_SCL_LPLL_05_H (REG_SCL_LPLL_BASE + 0x0B) ++#define REG_SCL_LPLL_06_L (REG_SCL_LPLL_BASE + 0x0C) ++#define REG_SCL_LPLL_06_H (REG_SCL_LPLL_BASE + 0x0D) ++#define REG_SCL_LPLL_07_L (REG_SCL_LPLL_BASE + 0x0E) ++#define REG_SCL_LPLL_07_H (REG_SCL_LPLL_BASE + 0x0F) ++#define REG_SCL_LPLL_08_L (REG_SCL_LPLL_BASE + 0x10) ++#define REG_SCL_LPLL_08_H (REG_SCL_LPLL_BASE + 0x11) ++#define REG_SCL_LPLL_09_L (REG_SCL_LPLL_BASE + 0x12) ++#define REG_SCL_LPLL_09_H (REG_SCL_LPLL_BASE + 0x13) ++#define REG_SCL_LPLL_0A_L (REG_SCL_LPLL_BASE + 0x14) ++#define REG_SCL_LPLL_0A_H (REG_SCL_LPLL_BASE + 0x15) ++#define REG_SCL_LPLL_0B_L (REG_SCL_LPLL_BASE + 0x16) ++#define REG_SCL_LPLL_0B_H (REG_SCL_LPLL_BASE + 0x17) ++#define REG_SCL_LPLL_0C_L (REG_SCL_LPLL_BASE + 0x18) ++#define REG_SCL_LPLL_0C_H (REG_SCL_LPLL_BASE + 0x19) ++#define REG_SCL_LPLL_0D_L (REG_SCL_LPLL_BASE + 0x1A) ++#define REG_SCL_LPLL_0D_H (REG_SCL_LPLL_BASE + 0x1B) ++#define REG_SCL_LPLL_0E_L (REG_SCL_LPLL_BASE + 0x1C) ++#define REG_SCL_LPLL_0E_H (REG_SCL_LPLL_BASE + 0x1D) ++#define REG_SCL_LPLL_0F_L (REG_SCL_LPLL_BASE + 0x1E) ++#define REG_SCL_LPLL_0F_H (REG_SCL_LPLL_BASE + 0x1F) ++#define REG_SCL_LPLL_10_L (REG_SCL_LPLL_BASE + 0x20) ++#define REG_SCL_LPLL_10_H (REG_SCL_LPLL_BASE + 0x21) ++#define REG_SCL_LPLL_11_L (REG_SCL_LPLL_BASE + 0x22) ++#define REG_SCL_LPLL_11_H (REG_SCL_LPLL_BASE + 0x23) ++#define REG_SCL_LPLL_12_L (REG_SCL_LPLL_BASE + 0x24) ++#define REG_SCL_LPLL_12_H (REG_SCL_LPLL_BASE + 0x25) ++#define REG_SCL_LPLL_13_L (REG_SCL_LPLL_BASE + 0x26) ++#define REG_SCL_LPLL_13_H (REG_SCL_LPLL_BASE + 0x27) ++#define REG_SCL_LPLL_14_L (REG_SCL_LPLL_BASE + 0x28) ++#define REG_SCL_LPLL_14_H (REG_SCL_LPLL_BASE + 0x29) ++#define REG_SCL_LPLL_15_L (REG_SCL_LPLL_BASE + 0x2A) ++#define REG_SCL_LPLL_15_H (REG_SCL_LPLL_BASE + 0x2B) ++#define REG_SCL_LPLL_16_L (REG_SCL_LPLL_BASE + 0x2C) ++#define REG_SCL_LPLL_16_H (REG_SCL_LPLL_BASE + 0x2D) ++#define REG_SCL_LPLL_17_L (REG_SCL_LPLL_BASE + 0x2E) ++#define REG_SCL_LPLL_17_H (REG_SCL_LPLL_BASE + 0x2F) ++#define REG_SCL_LPLL_18_L (REG_SCL_LPLL_BASE + 0x30) ++#define REG_SCL_LPLL_18_H (REG_SCL_LPLL_BASE + 0x31) ++#define REG_SCL_LPLL_19_L (REG_SCL_LPLL_BASE + 0x32) ++#define REG_SCL_LPLL_19_H (REG_SCL_LPLL_BASE + 0x33) ++#define REG_SCL_LPLL_1A_L (REG_SCL_LPLL_BASE + 0x34) ++#define REG_SCL_LPLL_1A_H (REG_SCL_LPLL_BASE + 0x35) ++#define REG_SCL_LPLL_1B_L (REG_SCL_LPLL_BASE + 0x36) ++#define REG_SCL_LPLL_1B_H (REG_SCL_LPLL_BASE + 0x37) ++#define REG_SCL_LPLL_1C_L (REG_SCL_LPLL_BASE + 0x38) ++#define REG_SCL_LPLL_1C_H (REG_SCL_LPLL_BASE + 0x39) ++#define REG_SCL_LPLL_1D_L (REG_SCL_LPLL_BASE + 0x3A) ++#define REG_SCL_LPLL_1D_H (REG_SCL_LPLL_BASE + 0x3B) ++#define REG_SCL_LPLL_1E_L (REG_SCL_LPLL_BASE + 0x3C) ++#define REG_SCL_LPLL_1E_H (REG_SCL_LPLL_BASE + 0x3D) ++#define REG_SCL_LPLL_1F_L (REG_SCL_LPLL_BASE + 0x3E) ++#define REG_SCL_LPLL_1F_H (REG_SCL_LPLL_BASE + 0x3F) ++#define REG_SCL_LPLL_20_L (REG_SCL_LPLL_BASE + 0x40) ++#define REG_SCL_LPLL_20_H (REG_SCL_LPLL_BASE + 0x41) ++#define REG_SCL_LPLL_21_L (REG_SCL_LPLL_BASE + 0x42) ++#define REG_SCL_LPLL_21_H (REG_SCL_LPLL_BASE + 0x43) ++#define REG_SCL_LPLL_22_L (REG_SCL_LPLL_BASE + 0x44) ++#define REG_SCL_LPLL_22_H (REG_SCL_LPLL_BASE + 0x45) ++#define REG_SCL_LPLL_23_L (REG_SCL_LPLL_BASE + 0x46) ++#define REG_SCL_LPLL_23_H (REG_SCL_LPLL_BASE + 0x47) ++#define REG_SCL_LPLL_24_L (REG_SCL_LPLL_BASE + 0x48) ++#define REG_SCL_LPLL_24_H (REG_SCL_LPLL_BASE + 0x49) ++#define REG_SCL_LPLL_25_L (REG_SCL_LPLL_BASE + 0x4A) ++#define REG_SCL_LPLL_25_H (REG_SCL_LPLL_BASE + 0x4B) ++#define REG_SCL_LPLL_26_L (REG_SCL_LPLL_BASE + 0x4C) ++#define REG_SCL_LPLL_26_H (REG_SCL_LPLL_BASE + 0x4D) ++#define REG_SCL_LPLL_27_L (REG_SCL_LPLL_BASE + 0x4E) ++#define REG_SCL_LPLL_27_H (REG_SCL_LPLL_BASE + 0x4F) ++#define REG_SCL_LPLL_28_L (REG_SCL_LPLL_BASE + 0x50) ++#define REG_SCL_LPLL_28_H (REG_SCL_LPLL_BASE + 0x51) ++#define REG_SCL_LPLL_29_L (REG_SCL_LPLL_BASE + 0x52) ++#define REG_SCL_LPLL_29_H (REG_SCL_LPLL_BASE + 0x53) ++#define REG_SCL_LPLL_2A_L (REG_SCL_LPLL_BASE + 0x54) ++#define REG_SCL_LPLL_2A_H (REG_SCL_LPLL_BASE + 0x55) ++#define REG_SCL_LPLL_2B_L (REG_SCL_LPLL_BASE + 0x56) ++#define REG_SCL_LPLL_2B_H (REG_SCL_LPLL_BASE + 0x57) ++#define REG_SCL_LPLL_2C_L (REG_SCL_LPLL_BASE + 0x58) ++#define REG_SCL_LPLL_2C_H (REG_SCL_LPLL_BASE + 0x59) ++#define REG_SCL_LPLL_2D_L (REG_SCL_LPLL_BASE + 0x5A) ++#define REG_SCL_LPLL_2D_H (REG_SCL_LPLL_BASE + 0x5B) ++#define REG_SCL_LPLL_2E_L (REG_SCL_LPLL_BASE + 0x5C) ++#define REG_SCL_LPLL_2E_H (REG_SCL_LPLL_BASE + 0x5D) ++#define REG_SCL_LPLL_2F_L (REG_SCL_LPLL_BASE + 0x5E) ++#define REG_SCL_LPLL_2F_H (REG_SCL_LPLL_BASE + 0x5F) ++#define REG_SCL_LPLL_30_L (REG_SCL_LPLL_BASE + 0x60) ++#define REG_SCL_LPLL_30_H (REG_SCL_LPLL_BASE + 0x61) ++#define REG_SCL_LPLL_31_L (REG_SCL_LPLL_BASE + 0x62) ++#define REG_SCL_LPLL_31_H (REG_SCL_LPLL_BASE + 0x63) ++#define REG_SCL_LPLL_32_L (REG_SCL_LPLL_BASE + 0x64) ++#define REG_SCL_LPLL_32_H (REG_SCL_LPLL_BASE + 0x65) ++#define REG_SCL_LPLL_33_L (REG_SCL_LPLL_BASE + 0x66) ++#define REG_SCL_LPLL_33_H (REG_SCL_LPLL_BASE + 0x67) ++#define REG_SCL_LPLL_34_L (REG_SCL_LPLL_BASE + 0x68) ++#define REG_SCL_LPLL_34_H (REG_SCL_LPLL_BASE + 0x69) ++#define REG_SCL_LPLL_35_L (REG_SCL_LPLL_BASE + 0x6A) ++#define REG_SCL_LPLL_35_H (REG_SCL_LPLL_BASE + 0x6B) ++#define REG_SCL_LPLL_36_L (REG_SCL_LPLL_BASE + 0x6C) ++#define REG_SCL_LPLL_36_H (REG_SCL_LPLL_BASE + 0x6D) ++#define REG_SCL_LPLL_37_L (REG_SCL_LPLL_BASE + 0x6E) ++#define REG_SCL_LPLL_37_H (REG_SCL_LPLL_BASE + 0x6F) ++#define REG_SCL_LPLL_38_L (REG_SCL_LPLL_BASE + 0x70) ++#define REG_SCL_LPLL_38_H (REG_SCL_LPLL_BASE + 0x71) ++#define REG_SCL_LPLL_39_L (REG_SCL_LPLL_BASE + 0x72) ++#define REG_SCL_LPLL_39_H (REG_SCL_LPLL_BASE + 0x73) ++#define REG_SCL_LPLL_3A_L (REG_SCL_LPLL_BASE + 0x74) ++#define REG_SCL_LPLL_3A_H (REG_SCL_LPLL_BASE + 0x75) ++#define REG_SCL_LPLL_3B_L (REG_SCL_LPLL_BASE + 0x76) ++#define REG_SCL_LPLL_3B_H (REG_SCL_LPLL_BASE + 0x77) ++#define REG_SCL_LPLL_3C_L (REG_SCL_LPLL_BASE + 0x78) ++#define REG_SCL_LPLL_3C_H (REG_SCL_LPLL_BASE + 0x79) ++#define REG_SCL_LPLL_3D_L (REG_SCL_LPLL_BASE + 0x7A) ++#define REG_SCL_LPLL_3D_H (REG_SCL_LPLL_BASE + 0x7B) ++#define REG_SCL_LPLL_3E_L (REG_SCL_LPLL_BASE + 0x7C) ++#define REG_SCL_LPLL_3E_H (REG_SCL_LPLL_BASE + 0x7D) ++#define REG_SCL_LPLL_3F_L (REG_SCL_LPLL_BASE + 0x7E) ++#define REG_SCL_LPLL_3F_H (REG_SCL_LPLL_BASE + 0x7F) ++#define REG_SCL_LPLL_40_L (REG_SCL_LPLL_BASE + 0x80) ++#define REG_SCL_LPLL_40_H (REG_SCL_LPLL_BASE + 0x81) ++#define REG_SCL_LPLL_41_L (REG_SCL_LPLL_BASE + 0x82) ++#define REG_SCL_LPLL_41_H (REG_SCL_LPLL_BASE + 0x83) ++#define REG_SCL_LPLL_42_L (REG_SCL_LPLL_BASE + 0x84) ++#define REG_SCL_LPLL_42_H (REG_SCL_LPLL_BASE + 0x85) ++#define REG_SCL_LPLL_43_L (REG_SCL_LPLL_BASE + 0x86) ++#define REG_SCL_LPLL_43_H (REG_SCL_LPLL_BASE + 0x87) ++#define REG_SCL_LPLL_44_L (REG_SCL_LPLL_BASE + 0x88) ++#define REG_SCL_LPLL_44_H (REG_SCL_LPLL_BASE + 0x89) ++#define REG_SCL_LPLL_45_L (REG_SCL_LPLL_BASE + 0x8A) ++#define REG_SCL_LPLL_45_H (REG_SCL_LPLL_BASE + 0x8B) ++#define REG_SCL_LPLL_46_L (REG_SCL_LPLL_BASE + 0x8C) ++#define REG_SCL_LPLL_46_H (REG_SCL_LPLL_BASE + 0x8D) ++#define REG_SCL_LPLL_47_L (REG_SCL_LPLL_BASE + 0x8E) ++#define REG_SCL_LPLL_47_H (REG_SCL_LPLL_BASE + 0x8F) ++#define REG_SCL_LPLL_48_L (REG_SCL_LPLL_BASE + 0x90) ++#define REG_SCL_LPLL_48_H (REG_SCL_LPLL_BASE + 0x91) ++#define REG_SCL_LPLL_49_L (REG_SCL_LPLL_BASE + 0x92) ++#define REG_SCL_LPLL_49_H (REG_SCL_LPLL_BASE + 0x93) ++#define REG_SCL_LPLL_4A_L (REG_SCL_LPLL_BASE + 0x94) ++#define REG_SCL_LPLL_4A_H (REG_SCL_LPLL_BASE + 0x95) ++#define REG_SCL_LPLL_4B_L (REG_SCL_LPLL_BASE + 0x96) ++#define REG_SCL_LPLL_4B_H (REG_SCL_LPLL_BASE + 0x97) ++#define REG_SCL_LPLL_4C_L (REG_SCL_LPLL_BASE + 0x98) ++#define REG_SCL_LPLL_4C_H (REG_SCL_LPLL_BASE + 0x99) ++#define REG_SCL_LPLL_4D_L (REG_SCL_LPLL_BASE + 0x9A) ++#define REG_SCL_LPLL_4D_H (REG_SCL_LPLL_BASE + 0x9B) ++#define REG_SCL_LPLL_4E_L (REG_SCL_LPLL_BASE + 0x9C) ++#define REG_SCL_LPLL_4E_H (REG_SCL_LPLL_BASE + 0x9D) ++#define REG_SCL_LPLL_4F_L (REG_SCL_LPLL_BASE + 0x9E) ++#define REG_SCL_LPLL_4F_H (REG_SCL_LPLL_BASE + 0x9F) ++#define REG_SCL_LPLL_50_L (REG_SCL_LPLL_BASE + 0xA0) ++#define REG_SCL_LPLL_50_H (REG_SCL_LPLL_BASE + 0xA1) ++#define REG_SCL_LPLL_51_L (REG_SCL_LPLL_BASE + 0xA2) ++#define REG_SCL_LPLL_51_H (REG_SCL_LPLL_BASE + 0xA3) ++#define REG_SCL_LPLL_52_L (REG_SCL_LPLL_BASE + 0xA4) ++#define REG_SCL_LPLL_52_H (REG_SCL_LPLL_BASE + 0xA5) ++#define REG_SCL_LPLL_53_L (REG_SCL_LPLL_BASE + 0xA6) ++#define REG_SCL_LPLL_53_H (REG_SCL_LPLL_BASE + 0xA7) ++#define REG_SCL_LPLL_54_L (REG_SCL_LPLL_BASE + 0xA8) ++#define REG_SCL_LPLL_54_H (REG_SCL_LPLL_BASE + 0xA9) ++#define REG_SCL_LPLL_55_L (REG_SCL_LPLL_BASE + 0xAA) ++#define REG_SCL_LPLL_55_H (REG_SCL_LPLL_BASE + 0xAB) ++#define REG_SCL_LPLL_56_L (REG_SCL_LPLL_BASE + 0xAC) ++#define REG_SCL_LPLL_56_H (REG_SCL_LPLL_BASE + 0xAD) ++#define REG_SCL_LPLL_57_L (REG_SCL_LPLL_BASE + 0xAE) ++#define REG_SCL_LPLL_57_H (REG_SCL_LPLL_BASE + 0xAF) ++#define REG_SCL_LPLL_58_L (REG_SCL_LPLL_BASE + 0xB0) ++#define REG_SCL_LPLL_58_H (REG_SCL_LPLL_BASE + 0xB1) ++#define REG_SCL_LPLL_59_L (REG_SCL_LPLL_BASE + 0xB2) ++#define REG_SCL_LPLL_59_H (REG_SCL_LPLL_BASE + 0xB3) ++#define REG_SCL_LPLL_5A_L (REG_SCL_LPLL_BASE + 0xB4) ++#define REG_SCL_LPLL_5A_H (REG_SCL_LPLL_BASE + 0xB5) ++#define REG_SCL_LPLL_5B_L (REG_SCL_LPLL_BASE + 0xB6) ++#define REG_SCL_LPLL_5B_H (REG_SCL_LPLL_BASE + 0xB7) ++#define REG_SCL_LPLL_5C_L (REG_SCL_LPLL_BASE + 0xB8) ++#define REG_SCL_LPLL_5C_H (REG_SCL_LPLL_BASE + 0xB9) ++#define REG_SCL_LPLL_5D_L (REG_SCL_LPLL_BASE + 0xBA) ++#define REG_SCL_LPLL_5D_H (REG_SCL_LPLL_BASE + 0xBB) ++#define REG_SCL_LPLL_5E_L (REG_SCL_LPLL_BASE + 0xBC) ++#define REG_SCL_LPLL_5E_H (REG_SCL_LPLL_BASE + 0xBD) ++#define REG_SCL_LPLL_5F_L (REG_SCL_LPLL_BASE + 0xBE) ++#define REG_SCL_LPLL_5F_H (REG_SCL_LPLL_BASE + 0xBF) ++#define REG_SCL_LPLL_60_L (REG_SCL_LPLL_BASE + 0xC0) ++#define REG_SCL_LPLL_60_H (REG_SCL_LPLL_BASE + 0xC1) ++#define REG_SCL_LPLL_61_L (REG_SCL_LPLL_BASE + 0xC2) ++#define REG_SCL_LPLL_61_H (REG_SCL_LPLL_BASE + 0xC3) ++#define REG_SCL_LPLL_62_L (REG_SCL_LPLL_BASE + 0xC4) ++#define REG_SCL_LPLL_62_H (REG_SCL_LPLL_BASE + 0xC5) ++#define REG_SCL_LPLL_63_L (REG_SCL_LPLL_BASE + 0xC6) ++#define REG_SCL_LPLL_63_H (REG_SCL_LPLL_BASE + 0xC7) ++#define REG_SCL_LPLL_64_L (REG_SCL_LPLL_BASE + 0xC8) ++#define REG_SCL_LPLL_64_H (REG_SCL_LPLL_BASE + 0xC9) ++#define REG_SCL_LPLL_65_L (REG_SCL_LPLL_BASE + 0xCA) ++#define REG_SCL_LPLL_65_H (REG_SCL_LPLL_BASE + 0xCB) ++#define REG_SCL_LPLL_66_L (REG_SCL_LPLL_BASE + 0xCC) ++#define REG_SCL_LPLL_66_H (REG_SCL_LPLL_BASE + 0xCD) ++#define REG_SCL_LPLL_67_L (REG_SCL_LPLL_BASE + 0xCE) ++#define REG_SCL_LPLL_67_H (REG_SCL_LPLL_BASE + 0xCF) ++#define REG_SCL_LPLL_68_L (REG_SCL_LPLL_BASE + 0xD0) ++#define REG_SCL_LPLL_68_H (REG_SCL_LPLL_BASE + 0xD1) ++#define REG_SCL_LPLL_69_L (REG_SCL_LPLL_BASE + 0xD2) ++#define REG_SCL_LPLL_69_H (REG_SCL_LPLL_BASE + 0xD3) ++#define REG_SCL_LPLL_6A_L (REG_SCL_LPLL_BASE + 0xD4) ++#define REG_SCL_LPLL_6A_H (REG_SCL_LPLL_BASE + 0xD5) ++#define REG_SCL_LPLL_6B_L (REG_SCL_LPLL_BASE + 0xD6) ++#define REG_SCL_LPLL_6B_H (REG_SCL_LPLL_BASE + 0xD7) ++#define REG_SCL_LPLL_6C_L (REG_SCL_LPLL_BASE + 0xD8) ++#define REG_SCL_LPLL_6C_H (REG_SCL_LPLL_BASE + 0xD9) ++#define REG_SCL_LPLL_6D_L (REG_SCL_LPLL_BASE + 0xDA) ++#define REG_SCL_LPLL_6D_H (REG_SCL_LPLL_BASE + 0xDB) ++#define REG_SCL_LPLL_6E_L (REG_SCL_LPLL_BASE + 0xDC) ++#define REG_SCL_LPLL_6E_H (REG_SCL_LPLL_BASE + 0xDD) ++#define REG_SCL_LPLL_6F_L (REG_SCL_LPLL_BASE + 0xDE) ++#define REG_SCL_LPLL_6F_H (REG_SCL_LPLL_BASE + 0xDF) ++#define REG_SCL_LPLL_70_L (REG_SCL_LPLL_BASE + 0xE0) ++#define REG_SCL_LPLL_70_H (REG_SCL_LPLL_BASE + 0xE1) ++#define REG_SCL_LPLL_71_L (REG_SCL_LPLL_BASE + 0xE2) ++#define REG_SCL_LPLL_71_H (REG_SCL_LPLL_BASE + 0xE3) ++#define REG_SCL_LPLL_72_L (REG_SCL_LPLL_BASE + 0xE4) ++#define REG_SCL_LPLL_72_H (REG_SCL_LPLL_BASE + 0xE5) ++#define REG_SCL_LPLL_73_L (REG_SCL_LPLL_BASE + 0xE6) ++#define REG_SCL_LPLL_73_H (REG_SCL_LPLL_BASE + 0xE7) ++#define REG_SCL_LPLL_74_L (REG_SCL_LPLL_BASE + 0xE8) ++#define REG_SCL_LPLL_74_H (REG_SCL_LPLL_BASE + 0xE9) ++#define REG_SCL_LPLL_75_L (REG_SCL_LPLL_BASE + 0xEA) ++#define REG_SCL_LPLL_75_H (REG_SCL_LPLL_BASE + 0xEB) ++#define REG_SCL_LPLL_76_L (REG_SCL_LPLL_BASE + 0xEC) ++#define REG_SCL_LPLL_76_H (REG_SCL_LPLL_BASE + 0xED) ++#define REG_SCL_LPLL_77_L (REG_SCL_LPLL_BASE + 0xEE) ++#define REG_SCL_LPLL_77_H (REG_SCL_LPLL_BASE + 0xEF) ++#define REG_SCL_LPLL_78_L (REG_SCL_LPLL_BASE + 0xF0) ++#define REG_SCL_LPLL_78_H (REG_SCL_LPLL_BASE + 0xF1) ++#define REG_SCL_LPLL_79_L (REG_SCL_LPLL_BASE + 0xF2) ++#define REG_SCL_LPLL_79_H (REG_SCL_LPLL_BASE + 0xF3) ++#define REG_SCL_LPLL_7A_L (REG_SCL_LPLL_BASE + 0xF4) ++#define REG_SCL_LPLL_7A_H (REG_SCL_LPLL_BASE + 0xF5) ++#define REG_SCL_LPLL_7B_L (REG_SCL_LPLL_BASE + 0xF6) ++#define REG_SCL_LPLL_7B_H (REG_SCL_LPLL_BASE + 0xF7) ++#define REG_SCL_LPLL_7C_L (REG_SCL_LPLL_BASE + 0xF8) ++#define REG_SCL_LPLL_7C_H (REG_SCL_LPLL_BASE + 0xF9) ++#define REG_SCL_LPLL_7D_L (REG_SCL_LPLL_BASE + 0xFA) ++#define REG_SCL_LPLL_7D_H (REG_SCL_LPLL_BASE + 0xFB) ++#define REG_SCL_LPLL_7E_L (REG_SCL_LPLL_BASE + 0xFC) ++#define REG_SCL_LPLL_7E_H (REG_SCL_LPLL_BASE + 0xFD) ++#define REG_SCL_LPLL_7F_L (REG_SCL_LPLL_BASE + 0xFE) ++#define REG_SCL_LPLL_7F_H (REG_SCL_LPLL_BASE + 0xFF) ++ ++#define REG_SCL_HVSP0_00_L (REG_SCL_HVSP0_BASE + 0x00) ++#define REG_SCL_HVSP0_00_H (REG_SCL_HVSP0_BASE + 0x01) ++#define REG_SCL_HVSP0_01_L (REG_SCL_HVSP0_BASE + 0x02) ++#define REG_SCL_HVSP0_01_H (REG_SCL_HVSP0_BASE + 0x03) ++#define REG_SCL_HVSP0_02_L (REG_SCL_HVSP0_BASE + 0x04) ++#define REG_SCL_HVSP0_02_H (REG_SCL_HVSP0_BASE + 0x05) ++#define REG_SCL_HVSP0_03_L (REG_SCL_HVSP0_BASE + 0x06) ++#define REG_SCL_HVSP0_03_H (REG_SCL_HVSP0_BASE + 0x07) ++#define REG_SCL_HVSP0_04_L (REG_SCL_HVSP0_BASE + 0x08) ++#define REG_SCL_HVSP0_04_H (REG_SCL_HVSP0_BASE + 0x09) ++#define REG_SCL_HVSP0_05_L (REG_SCL_HVSP0_BASE + 0x0A) ++#define REG_SCL_HVSP0_05_H (REG_SCL_HVSP0_BASE + 0x0B) ++#define REG_SCL_HVSP0_06_L (REG_SCL_HVSP0_BASE + 0x0C) ++#define REG_SCL_HVSP0_06_H (REG_SCL_HVSP0_BASE + 0x0D) ++#define REG_SCL_HVSP0_07_L (REG_SCL_HVSP0_BASE + 0x0E) ++#define REG_SCL_HVSP0_07_H (REG_SCL_HVSP0_BASE + 0x0F) ++#define REG_SCL_HVSP0_08_L (REG_SCL_HVSP0_BASE + 0x10) ++#define REG_SCL_HVSP0_08_H (REG_SCL_HVSP0_BASE + 0x11) ++#define REG_SCL_HVSP0_09_L (REG_SCL_HVSP0_BASE + 0x12) ++#define REG_SCL_HVSP0_09_H (REG_SCL_HVSP0_BASE + 0x13) ++#define REG_SCL_HVSP0_0A_L (REG_SCL_HVSP0_BASE + 0x14) ++#define REG_SCL_HVSP0_0A_H (REG_SCL_HVSP0_BASE + 0x15) ++#define REG_SCL_HVSP0_0B_L (REG_SCL_HVSP0_BASE + 0x16) ++#define REG_SCL_HVSP0_0B_H (REG_SCL_HVSP0_BASE + 0x17) ++#define REG_SCL_HVSP0_0C_L (REG_SCL_HVSP0_BASE + 0x18) ++#define REG_SCL_HVSP0_0C_H (REG_SCL_HVSP0_BASE + 0x19) ++#define REG_SCL_HVSP0_0D_L (REG_SCL_HVSP0_BASE + 0x1A) ++#define REG_SCL_HVSP0_0D_H (REG_SCL_HVSP0_BASE + 0x1B) ++#define REG_SCL_HVSP0_0E_L (REG_SCL_HVSP0_BASE + 0x1C) ++#define REG_SCL_HVSP0_0E_H (REG_SCL_HVSP0_BASE + 0x1D) ++#define REG_SCL_HVSP0_0F_L (REG_SCL_HVSP0_BASE + 0x1E) ++#define REG_SCL_HVSP0_0F_H (REG_SCL_HVSP0_BASE + 0x1F) ++#define REG_SCL_HVSP0_10_L (REG_SCL_HVSP0_BASE + 0x20) ++#define REG_SCL_HVSP0_10_H (REG_SCL_HVSP0_BASE + 0x21) ++#define REG_SCL_HVSP0_11_L (REG_SCL_HVSP0_BASE + 0x22) ++#define REG_SCL_HVSP0_11_H (REG_SCL_HVSP0_BASE + 0x23) ++#define REG_SCL_HVSP0_12_L (REG_SCL_HVSP0_BASE + 0x24) ++#define REG_SCL_HVSP0_12_H (REG_SCL_HVSP0_BASE + 0x25) ++#define REG_SCL_HVSP0_13_L (REG_SCL_HVSP0_BASE + 0x26) ++#define REG_SCL_HVSP0_13_H (REG_SCL_HVSP0_BASE + 0x27) ++#define REG_SCL_HVSP0_14_L (REG_SCL_HVSP0_BASE + 0x28) ++#define REG_SCL_HVSP0_14_H (REG_SCL_HVSP0_BASE + 0x29) ++#define REG_SCL_HVSP0_15_L (REG_SCL_HVSP0_BASE + 0x2A) ++#define REG_SCL_HVSP0_15_H (REG_SCL_HVSP0_BASE + 0x2B) ++#define REG_SCL_HVSP0_16_L (REG_SCL_HVSP0_BASE + 0x2C) ++#define REG_SCL_HVSP0_16_H (REG_SCL_HVSP0_BASE + 0x2D) ++#define REG_SCL_HVSP0_17_L (REG_SCL_HVSP0_BASE + 0x2E) ++#define REG_SCL_HVSP0_17_H (REG_SCL_HVSP0_BASE + 0x2F) ++#define REG_SCL_HVSP0_18_L (REG_SCL_HVSP0_BASE + 0x30) ++#define REG_SCL_HVSP0_18_H (REG_SCL_HVSP0_BASE + 0x31) ++#define REG_SCL_HVSP0_19_L (REG_SCL_HVSP0_BASE + 0x32) ++#define REG_SCL_HVSP0_19_H (REG_SCL_HVSP0_BASE + 0x33) ++#define REG_SCL_HVSP0_1A_L (REG_SCL_HVSP0_BASE + 0x34) ++#define REG_SCL_HVSP0_1A_H (REG_SCL_HVSP0_BASE + 0x35) ++#define REG_SCL_HVSP0_1B_L (REG_SCL_HVSP0_BASE + 0x36) ++#define REG_SCL_HVSP0_1B_H (REG_SCL_HVSP0_BASE + 0x37) ++#define REG_SCL_HVSP0_1C_L (REG_SCL_HVSP0_BASE + 0x38) ++#define REG_SCL_HVSP0_1C_H (REG_SCL_HVSP0_BASE + 0x39) ++#define REG_SCL_HVSP0_1D_L (REG_SCL_HVSP0_BASE + 0x3A) ++#define REG_SCL_HVSP0_1D_H (REG_SCL_HVSP0_BASE + 0x3B) ++#define REG_SCL_HVSP0_1E_L (REG_SCL_HVSP0_BASE + 0x3C) ++#define REG_SCL_HVSP0_1E_H (REG_SCL_HVSP0_BASE + 0x3D) ++#define REG_SCL_HVSP0_1F_L (REG_SCL_HVSP0_BASE + 0x3E) ++#define REG_SCL_HVSP0_1F_H (REG_SCL_HVSP0_BASE + 0x3F) ++#define REG_SCL_HVSP0_20_L (REG_SCL_HVSP0_BASE + 0x40) ++#define REG_SCL_HVSP0_20_H (REG_SCL_HVSP0_BASE + 0x41) ++#define REG_SCL_HVSP0_21_L (REG_SCL_HVSP0_BASE + 0x42) ++#define REG_SCL_HVSP0_21_H (REG_SCL_HVSP0_BASE + 0x43) ++#define REG_SCL_HVSP0_22_L (REG_SCL_HVSP0_BASE + 0x44) ++#define REG_SCL_HVSP0_22_H (REG_SCL_HVSP0_BASE + 0x45) ++#define REG_SCL_HVSP0_23_L (REG_SCL_HVSP0_BASE + 0x46) ++#define REG_SCL_HVSP0_23_H (REG_SCL_HVSP0_BASE + 0x47) ++#define REG_SCL_HVSP0_24_L (REG_SCL_HVSP0_BASE + 0x48) ++#define REG_SCL_HVSP0_24_H (REG_SCL_HVSP0_BASE + 0x49) ++#define REG_SCL_HVSP0_25_L (REG_SCL_HVSP0_BASE + 0x4A) ++#define REG_SCL_HVSP0_25_H (REG_SCL_HVSP0_BASE + 0x4B) ++#define REG_SCL_HVSP0_26_L (REG_SCL_HVSP0_BASE + 0x4C) ++#define REG_SCL_HVSP0_26_H (REG_SCL_HVSP0_BASE + 0x4D) ++#define REG_SCL_HVSP0_27_L (REG_SCL_HVSP0_BASE + 0x4E) ++#define REG_SCL_HVSP0_27_H (REG_SCL_HVSP0_BASE + 0x4F) ++#define REG_SCL_HVSP0_28_L (REG_SCL_HVSP0_BASE + 0x50) ++#define REG_SCL_HVSP0_28_H (REG_SCL_HVSP0_BASE + 0x51) ++#define REG_SCL_HVSP0_29_L (REG_SCL_HVSP0_BASE + 0x52) ++#define REG_SCL_HVSP0_29_H (REG_SCL_HVSP0_BASE + 0x53) ++#define REG_SCL_HVSP0_2A_L (REG_SCL_HVSP0_BASE + 0x54) ++#define REG_SCL_HVSP0_2A_H (REG_SCL_HVSP0_BASE + 0x55) ++#define REG_SCL_HVSP0_2B_L (REG_SCL_HVSP0_BASE + 0x56) ++#define REG_SCL_HVSP0_2B_H (REG_SCL_HVSP0_BASE + 0x57) ++#define REG_SCL_HVSP0_2C_L (REG_SCL_HVSP0_BASE + 0x58) ++#define REG_SCL_HVSP0_2C_H (REG_SCL_HVSP0_BASE + 0x59) ++#define REG_SCL_HVSP0_2D_L (REG_SCL_HVSP0_BASE + 0x5A) ++#define REG_SCL_HVSP0_2D_H (REG_SCL_HVSP0_BASE + 0x5B) ++#define REG_SCL_HVSP0_2E_L (REG_SCL_HVSP0_BASE + 0x5C) ++#define REG_SCL_HVSP0_2E_H (REG_SCL_HVSP0_BASE + 0x5D) ++#define REG_SCL_HVSP0_2F_L (REG_SCL_HVSP0_BASE + 0x5E) ++#define REG_SCL_HVSP0_2F_H (REG_SCL_HVSP0_BASE + 0x5F) ++#define REG_SCL_HVSP0_30_L (REG_SCL_HVSP0_BASE + 0x60) ++#define REG_SCL_HVSP0_30_H (REG_SCL_HVSP0_BASE + 0x61) ++#define REG_SCL_HVSP0_31_L (REG_SCL_HVSP0_BASE + 0x62) ++#define REG_SCL_HVSP0_31_H (REG_SCL_HVSP0_BASE + 0x63) ++#define REG_SCL_HVSP0_32_L (REG_SCL_HVSP0_BASE + 0x64) ++#define REG_SCL_HVSP0_32_H (REG_SCL_HVSP0_BASE + 0x65) ++#define REG_SCL_HVSP0_33_L (REG_SCL_HVSP0_BASE + 0x66) ++#define REG_SCL_HVSP0_33_H (REG_SCL_HVSP0_BASE + 0x67) ++#define REG_SCL_HVSP0_34_L (REG_SCL_HVSP0_BASE + 0x68) ++#define REG_SCL_HVSP0_34_H (REG_SCL_HVSP0_BASE + 0x69) ++#define REG_SCL_HVSP0_35_L (REG_SCL_HVSP0_BASE + 0x6A) ++#define REG_SCL_HVSP0_35_H (REG_SCL_HVSP0_BASE + 0x6B) ++#define REG_SCL_HVSP0_36_L (REG_SCL_HVSP0_BASE + 0x6C) ++#define REG_SCL_HVSP0_36_H (REG_SCL_HVSP0_BASE + 0x6D) ++#define REG_SCL_HVSP0_37_L (REG_SCL_HVSP0_BASE + 0x6E) ++#define REG_SCL_HVSP0_37_H (REG_SCL_HVSP0_BASE + 0x6F) ++#define REG_SCL_HVSP0_38_L (REG_SCL_HVSP0_BASE + 0x70) ++#define REG_SCL_HVSP0_38_H (REG_SCL_HVSP0_BASE + 0x71) ++#define REG_SCL_HVSP0_39_L (REG_SCL_HVSP0_BASE + 0x72) ++#define REG_SCL_HVSP0_39_H (REG_SCL_HVSP0_BASE + 0x73) ++#define REG_SCL_HVSP0_3A_L (REG_SCL_HVSP0_BASE + 0x74) ++#define REG_SCL_HVSP0_3A_H (REG_SCL_HVSP0_BASE + 0x75) ++#define REG_SCL_HVSP0_3B_L (REG_SCL_HVSP0_BASE + 0x76) ++#define REG_SCL_HVSP0_3B_H (REG_SCL_HVSP0_BASE + 0x77) ++#define REG_SCL_HVSP0_3C_L (REG_SCL_HVSP0_BASE + 0x78) ++#define REG_SCL_HVSP0_3C_H (REG_SCL_HVSP0_BASE + 0x79) ++#define REG_SCL_HVSP0_3D_L (REG_SCL_HVSP0_BASE + 0x7A) ++#define REG_SCL_HVSP0_3D_H (REG_SCL_HVSP0_BASE + 0x7B) ++#define REG_SCL_HVSP0_3E_L (REG_SCL_HVSP0_BASE + 0x7C) ++#define REG_SCL_HVSP0_3E_H (REG_SCL_HVSP0_BASE + 0x7D) ++#define REG_SCL_HVSP0_3F_L (REG_SCL_HVSP0_BASE + 0x7E) ++#define REG_SCL_HVSP0_3F_H (REG_SCL_HVSP0_BASE + 0x7F) ++#define REG_SCL_HVSP0_40_L (REG_SCL_HVSP0_BASE + 0x80) ++#define REG_SCL_HVSP0_40_H (REG_SCL_HVSP0_BASE + 0x81) ++#define REG_SCL_HVSP0_41_L (REG_SCL_HVSP0_BASE + 0x82) ++#define REG_SCL_HVSP0_41_H (REG_SCL_HVSP0_BASE + 0x83) ++#define REG_SCL_HVSP0_42_L (REG_SCL_HVSP0_BASE + 0x84) ++#define REG_SCL_HVSP0_42_H (REG_SCL_HVSP0_BASE + 0x85) ++#define REG_SCL_HVSP0_43_L (REG_SCL_HVSP0_BASE + 0x86) ++#define REG_SCL_HVSP0_43_H (REG_SCL_HVSP0_BASE + 0x87) ++#define REG_SCL_HVSP0_44_L (REG_SCL_HVSP0_BASE + 0x88) ++#define REG_SCL_HVSP0_44_H (REG_SCL_HVSP0_BASE + 0x89) ++#define REG_SCL_HVSP0_45_L (REG_SCL_HVSP0_BASE + 0x8A) ++#define REG_SCL_HVSP0_45_H (REG_SCL_HVSP0_BASE + 0x8B) ++#define REG_SCL_HVSP0_46_L (REG_SCL_HVSP0_BASE + 0x8C) ++#define REG_SCL_HVSP0_46_H (REG_SCL_HVSP0_BASE + 0x8D) ++#define REG_SCL_HVSP0_47_L (REG_SCL_HVSP0_BASE + 0x8E) ++#define REG_SCL_HVSP0_47_H (REG_SCL_HVSP0_BASE + 0x8F) ++#define REG_SCL_HVSP0_48_L (REG_SCL_HVSP0_BASE + 0x90) ++#define REG_SCL_HVSP0_48_H (REG_SCL_HVSP0_BASE + 0x91) ++#define REG_SCL_HVSP0_49_L (REG_SCL_HVSP0_BASE + 0x92) ++#define REG_SCL_HVSP0_49_H (REG_SCL_HVSP0_BASE + 0x93) ++#define REG_SCL_HVSP0_4A_L (REG_SCL_HVSP0_BASE + 0x94) ++#define REG_SCL_HVSP0_4A_H (REG_SCL_HVSP0_BASE + 0x95) ++#define REG_SCL_HVSP0_4B_L (REG_SCL_HVSP0_BASE + 0x96) ++#define REG_SCL_HVSP0_4B_H (REG_SCL_HVSP0_BASE + 0x97) ++#define REG_SCL_HVSP0_4C_L (REG_SCL_HVSP0_BASE + 0x98) ++#define REG_SCL_HVSP0_4C_H (REG_SCL_HVSP0_BASE + 0x99) ++#define REG_SCL_HVSP0_4D_L (REG_SCL_HVSP0_BASE + 0x9A) ++#define REG_SCL_HVSP0_4D_H (REG_SCL_HVSP0_BASE + 0x9B) ++#define REG_SCL_HVSP0_4E_L (REG_SCL_HVSP0_BASE + 0x9C) ++#define REG_SCL_HVSP0_4E_H (REG_SCL_HVSP0_BASE + 0x9D) ++#define REG_SCL_HVSP0_4F_L (REG_SCL_HVSP0_BASE + 0x9E) ++#define REG_SCL_HVSP0_4F_H (REG_SCL_HVSP0_BASE + 0x9F) ++#define REG_SCL_HVSP0_50_L (REG_SCL_HVSP0_BASE + 0xA0) ++#define REG_SCL_HVSP0_50_H (REG_SCL_HVSP0_BASE + 0xA1) ++#define REG_SCL_HVSP0_51_L (REG_SCL_HVSP0_BASE + 0xA2) ++#define REG_SCL_HVSP0_51_H (REG_SCL_HVSP0_BASE + 0xA3) ++#define REG_SCL_HVSP0_52_L (REG_SCL_HVSP0_BASE + 0xA4) ++#define REG_SCL_HVSP0_52_H (REG_SCL_HVSP0_BASE + 0xA5) ++#define REG_SCL_HVSP0_53_L (REG_SCL_HVSP0_BASE + 0xA6) ++#define REG_SCL_HVSP0_53_H (REG_SCL_HVSP0_BASE + 0xA7) ++#define REG_SCL_HVSP0_54_L (REG_SCL_HVSP0_BASE + 0xA8) ++#define REG_SCL_HVSP0_54_H (REG_SCL_HVSP0_BASE + 0xA9) ++#define REG_SCL_HVSP0_55_L (REG_SCL_HVSP0_BASE + 0xAA) ++#define REG_SCL_HVSP0_55_H (REG_SCL_HVSP0_BASE + 0xAB) ++#define REG_SCL_HVSP0_56_L (REG_SCL_HVSP0_BASE + 0xAC) ++#define REG_SCL_HVSP0_56_H (REG_SCL_HVSP0_BASE + 0xAD) ++#define REG_SCL_HVSP0_57_L (REG_SCL_HVSP0_BASE + 0xAE) ++#define REG_SCL_HVSP0_57_H (REG_SCL_HVSP0_BASE + 0xAF) ++#define REG_SCL_HVSP0_58_L (REG_SCL_HVSP0_BASE + 0xB0) ++#define REG_SCL_HVSP0_58_H (REG_SCL_HVSP0_BASE + 0xB1) ++#define REG_SCL_HVSP0_59_L (REG_SCL_HVSP0_BASE + 0xB2) ++#define REG_SCL_HVSP0_59_H (REG_SCL_HVSP0_BASE + 0xB3) ++#define REG_SCL_HVSP0_5A_L (REG_SCL_HVSP0_BASE + 0xB4) ++#define REG_SCL_HVSP0_5A_H (REG_SCL_HVSP0_BASE + 0xB5) ++#define REG_SCL_HVSP0_5B_L (REG_SCL_HVSP0_BASE + 0xB6) ++#define REG_SCL_HVSP0_5B_H (REG_SCL_HVSP0_BASE + 0xB7) ++#define REG_SCL_HVSP0_5C_L (REG_SCL_HVSP0_BASE + 0xB8) ++#define REG_SCL_HVSP0_5C_H (REG_SCL_HVSP0_BASE + 0xB9) ++#define REG_SCL_HVSP0_5D_L (REG_SCL_HVSP0_BASE + 0xBA) ++#define REG_SCL_HVSP0_5D_H (REG_SCL_HVSP0_BASE + 0xBB) ++#define REG_SCL_HVSP0_5E_L (REG_SCL_HVSP0_BASE + 0xBC) ++#define REG_SCL_HVSP0_5E_H (REG_SCL_HVSP0_BASE + 0xBD) ++#define REG_SCL_HVSP0_5F_L (REG_SCL_HVSP0_BASE + 0xBE) ++#define REG_SCL_HVSP0_5F_H (REG_SCL_HVSP0_BASE + 0xBF) ++#define REG_SCL_HVSP0_60_L (REG_SCL_HVSP0_BASE + 0xC0) ++#define REG_SCL_HVSP0_60_H (REG_SCL_HVSP0_BASE + 0xC1) ++#define REG_SCL_HVSP0_61_L (REG_SCL_HVSP0_BASE + 0xC2) ++#define REG_SCL_HVSP0_61_H (REG_SCL_HVSP0_BASE + 0xC3) ++#define REG_SCL_HVSP0_62_L (REG_SCL_HVSP0_BASE + 0xC4) ++#define REG_SCL_HVSP0_62_H (REG_SCL_HVSP0_BASE + 0xC5) ++#define REG_SCL_HVSP0_63_L (REG_SCL_HVSP0_BASE + 0xC6) ++#define REG_SCL_HVSP0_63_H (REG_SCL_HVSP0_BASE + 0xC7) ++#define REG_SCL_HVSP0_64_L (REG_SCL_HVSP0_BASE + 0xC8) ++#define REG_SCL_HVSP0_64_H (REG_SCL_HVSP0_BASE + 0xC9) ++#define REG_SCL_HVSP0_65_L (REG_SCL_HVSP0_BASE + 0xCA) ++#define REG_SCL_HVSP0_65_H (REG_SCL_HVSP0_BASE + 0xCB) ++#define REG_SCL_HVSP0_66_L (REG_SCL_HVSP0_BASE + 0xCC) ++#define REG_SCL_HVSP0_66_H (REG_SCL_HVSP0_BASE + 0xCD) ++#define REG_SCL_HVSP0_67_L (REG_SCL_HVSP0_BASE + 0xCE) ++#define REG_SCL_HVSP0_67_H (REG_SCL_HVSP0_BASE + 0xCF) ++#define REG_SCL_HVSP0_68_L (REG_SCL_HVSP0_BASE + 0xD0) ++#define REG_SCL_HVSP0_68_H (REG_SCL_HVSP0_BASE + 0xD1) ++#define REG_SCL_HVSP0_69_L (REG_SCL_HVSP0_BASE + 0xD2) ++#define REG_SCL_HVSP0_69_H (REG_SCL_HVSP0_BASE + 0xD3) ++#define REG_SCL_HVSP0_6A_L (REG_SCL_HVSP0_BASE + 0xD4) ++#define REG_SCL_HVSP0_6A_H (REG_SCL_HVSP0_BASE + 0xD5) ++#define REG_SCL_HVSP0_6B_L (REG_SCL_HVSP0_BASE + 0xD6) ++#define REG_SCL_HVSP0_6B_H (REG_SCL_HVSP0_BASE + 0xD7) ++#define REG_SCL_HVSP0_6C_L (REG_SCL_HVSP0_BASE + 0xD8) ++#define REG_SCL_HVSP0_6C_H (REG_SCL_HVSP0_BASE + 0xD9) ++#define REG_SCL_HVSP0_6D_L (REG_SCL_HVSP0_BASE + 0xDA) ++#define REG_SCL_HVSP0_6D_H (REG_SCL_HVSP0_BASE + 0xDB) ++#define REG_SCL_HVSP0_6E_L (REG_SCL_HVSP0_BASE + 0xDC) ++#define REG_SCL_HVSP0_6E_H (REG_SCL_HVSP0_BASE + 0xDD) ++#define REG_SCL_HVSP0_6F_L (REG_SCL_HVSP0_BASE + 0xDE) ++#define REG_SCL_HVSP0_6F_H (REG_SCL_HVSP0_BASE + 0xDF) ++#define REG_SCL_HVSP0_70_L (REG_SCL_HVSP0_BASE + 0xE0) ++#define REG_SCL_HVSP0_70_H (REG_SCL_HVSP0_BASE + 0xE1) ++#define REG_SCL_HVSP0_71_L (REG_SCL_HVSP0_BASE + 0xE2) ++#define REG_SCL_HVSP0_71_H (REG_SCL_HVSP0_BASE + 0xE3) ++#define REG_SCL_HVSP0_72_L (REG_SCL_HVSP0_BASE + 0xE4) ++#define REG_SCL_HVSP0_72_H (REG_SCL_HVSP0_BASE + 0xE5) ++#define REG_SCL_HVSP0_73_L (REG_SCL_HVSP0_BASE + 0xE6) ++#define REG_SCL_HVSP0_73_H (REG_SCL_HVSP0_BASE + 0xE7) ++#define REG_SCL_HVSP0_74_L (REG_SCL_HVSP0_BASE + 0xE8) ++#define REG_SCL_HVSP0_74_H (REG_SCL_HVSP0_BASE + 0xE9) ++#define REG_SCL_HVSP0_75_L (REG_SCL_HVSP0_BASE + 0xEA) ++#define REG_SCL_HVSP0_75_H (REG_SCL_HVSP0_BASE + 0xEB) ++#define REG_SCL_HVSP0_76_L (REG_SCL_HVSP0_BASE + 0xEC) ++#define REG_SCL_HVSP0_76_H (REG_SCL_HVSP0_BASE + 0xED) ++#define REG_SCL_HVSP0_77_L (REG_SCL_HVSP0_BASE + 0xEE) ++#define REG_SCL_HVSP0_77_H (REG_SCL_HVSP0_BASE + 0xEF) ++#define REG_SCL_HVSP0_78_L (REG_SCL_HVSP0_BASE + 0xF0) ++#define REG_SCL_HVSP0_78_H (REG_SCL_HVSP0_BASE + 0xF1) ++#define REG_SCL_HVSP0_79_L (REG_SCL_HVSP0_BASE + 0xF2) ++#define REG_SCL_HVSP0_79_H (REG_SCL_HVSP0_BASE + 0xF3) ++#define REG_SCL_HVSP0_7A_L (REG_SCL_HVSP0_BASE + 0xF4) ++#define REG_SCL_HVSP0_7A_H (REG_SCL_HVSP0_BASE + 0xF5) ++#define REG_SCL_HVSP0_7B_L (REG_SCL_HVSP0_BASE + 0xF6) ++#define REG_SCL_HVSP0_7B_H (REG_SCL_HVSP0_BASE + 0xF7) ++#define REG_SCL_HVSP0_7C_L (REG_SCL_HVSP0_BASE + 0xF8) ++#define REG_SCL_HVSP0_7C_H (REG_SCL_HVSP0_BASE + 0xF9) ++#define REG_SCL_HVSP0_7D_L (REG_SCL_HVSP0_BASE + 0xFA) ++#define REG_SCL_HVSP0_7D_H (REG_SCL_HVSP0_BASE + 0xFB) ++#define REG_SCL_HVSP0_7E_L (REG_SCL_HVSP0_BASE + 0xFC) ++#define REG_SCL_HVSP0_7E_H (REG_SCL_HVSP0_BASE + 0xFD) ++#define REG_SCL_HVSP0_7F_L (REG_SCL_HVSP0_BASE + 0xFE) ++#define REG_SCL_HVSP0_7F_H (REG_SCL_HVSP0_BASE + 0xFF) ++ ++#define REG_SCL_HVSP1_00_L (REG_SCL_HVSP1_BASE + 0x00) ++#define REG_SCL_HVSP1_00_H (REG_SCL_HVSP1_BASE + 0x01) ++#define REG_SCL_HVSP1_01_L (REG_SCL_HVSP1_BASE + 0x02) ++#define REG_SCL_HVSP1_01_H (REG_SCL_HVSP1_BASE + 0x03) ++#define REG_SCL_HVSP1_02_L (REG_SCL_HVSP1_BASE + 0x04) ++#define REG_SCL_HVSP1_02_H (REG_SCL_HVSP1_BASE + 0x05) ++#define REG_SCL_HVSP1_03_L (REG_SCL_HVSP1_BASE + 0x06) ++#define REG_SCL_HVSP1_03_H (REG_SCL_HVSP1_BASE + 0x07) ++#define REG_SCL_HVSP1_04_L (REG_SCL_HVSP1_BASE + 0x08) ++#define REG_SCL_HVSP1_04_H (REG_SCL_HVSP1_BASE + 0x09) ++#define REG_SCL_HVSP1_05_L (REG_SCL_HVSP1_BASE + 0x0A) ++#define REG_SCL_HVSP1_05_H (REG_SCL_HVSP1_BASE + 0x0B) ++#define REG_SCL_HVSP1_06_L (REG_SCL_HVSP1_BASE + 0x0C) ++#define REG_SCL_HVSP1_06_H (REG_SCL_HVSP1_BASE + 0x0D) ++#define REG_SCL_HVSP1_07_L (REG_SCL_HVSP1_BASE + 0x0E) ++#define REG_SCL_HVSP1_07_H (REG_SCL_HVSP1_BASE + 0x0F) ++#define REG_SCL_HVSP1_08_L (REG_SCL_HVSP1_BASE + 0x10) ++#define REG_SCL_HVSP1_08_H (REG_SCL_HVSP1_BASE + 0x11) ++#define REG_SCL_HVSP1_09_L (REG_SCL_HVSP1_BASE + 0x12) ++#define REG_SCL_HVSP1_09_H (REG_SCL_HVSP1_BASE + 0x13) ++#define REG_SCL_HVSP1_0A_L (REG_SCL_HVSP1_BASE + 0x14) ++#define REG_SCL_HVSP1_0A_H (REG_SCL_HVSP1_BASE + 0x15) ++#define REG_SCL_HVSP1_0B_L (REG_SCL_HVSP1_BASE + 0x16) ++#define REG_SCL_HVSP1_0B_H (REG_SCL_HVSP1_BASE + 0x17) ++#define REG_SCL_HVSP1_0C_L (REG_SCL_HVSP1_BASE + 0x18) ++#define REG_SCL_HVSP1_0C_H (REG_SCL_HVSP1_BASE + 0x19) ++#define REG_SCL_HVSP1_0D_L (REG_SCL_HVSP1_BASE + 0x1A) ++#define REG_SCL_HVSP1_0D_H (REG_SCL_HVSP1_BASE + 0x1B) ++#define REG_SCL_HVSP1_0E_L (REG_SCL_HVSP1_BASE + 0x1C) ++#define REG_SCL_HVSP1_0E_H (REG_SCL_HVSP1_BASE + 0x1D) ++#define REG_SCL_HVSP1_0F_L (REG_SCL_HVSP1_BASE + 0x1E) ++#define REG_SCL_HVSP1_0F_H (REG_SCL_HVSP1_BASE + 0x1F) ++#define REG_SCL_HVSP1_10_L (REG_SCL_HVSP1_BASE + 0x20) ++#define REG_SCL_HVSP1_10_H (REG_SCL_HVSP1_BASE + 0x21) ++#define REG_SCL_HVSP1_11_L (REG_SCL_HVSP1_BASE + 0x22) ++#define REG_SCL_HVSP1_11_H (REG_SCL_HVSP1_BASE + 0x23) ++#define REG_SCL_HVSP1_12_L (REG_SCL_HVSP1_BASE + 0x24) ++#define REG_SCL_HVSP1_12_H (REG_SCL_HVSP1_BASE + 0x25) ++#define REG_SCL_HVSP1_13_L (REG_SCL_HVSP1_BASE + 0x26) ++#define REG_SCL_HVSP1_13_H (REG_SCL_HVSP1_BASE + 0x27) ++#define REG_SCL_HVSP1_14_L (REG_SCL_HVSP1_BASE + 0x28) ++#define REG_SCL_HVSP1_14_H (REG_SCL_HVSP1_BASE + 0x29) ++#define REG_SCL_HVSP1_15_L (REG_SCL_HVSP1_BASE + 0x2A) ++#define REG_SCL_HVSP1_15_H (REG_SCL_HVSP1_BASE + 0x2B) ++#define REG_SCL_HVSP1_16_L (REG_SCL_HVSP1_BASE + 0x2C) ++#define REG_SCL_HVSP1_16_H (REG_SCL_HVSP1_BASE + 0x2D) ++#define REG_SCL_HVSP1_17_L (REG_SCL_HVSP1_BASE + 0x2E) ++#define REG_SCL_HVSP1_17_H (REG_SCL_HVSP1_BASE + 0x2F) ++#define REG_SCL_HVSP1_18_L (REG_SCL_HVSP1_BASE + 0x30) ++#define REG_SCL_HVSP1_18_H (REG_SCL_HVSP1_BASE + 0x31) ++#define REG_SCL_HVSP1_19_L (REG_SCL_HVSP1_BASE + 0x32) ++#define REG_SCL_HVSP1_19_H (REG_SCL_HVSP1_BASE + 0x33) ++#define REG_SCL_HVSP1_1A_L (REG_SCL_HVSP1_BASE + 0x34) ++#define REG_SCL_HVSP1_1A_H (REG_SCL_HVSP1_BASE + 0x35) ++#define REG_SCL_HVSP1_1B_L (REG_SCL_HVSP1_BASE + 0x36) ++#define REG_SCL_HVSP1_1B_H (REG_SCL_HVSP1_BASE + 0x37) ++#define REG_SCL_HVSP1_1C_L (REG_SCL_HVSP1_BASE + 0x38) ++#define REG_SCL_HVSP1_1C_H (REG_SCL_HVSP1_BASE + 0x39) ++#define REG_SCL_HVSP1_1D_L (REG_SCL_HVSP1_BASE + 0x3A) ++#define REG_SCL_HVSP1_1D_H (REG_SCL_HVSP1_BASE + 0x3B) ++#define REG_SCL_HVSP1_1E_L (REG_SCL_HVSP1_BASE + 0x3C) ++#define REG_SCL_HVSP1_1E_H (REG_SCL_HVSP1_BASE + 0x3D) ++#define REG_SCL_HVSP1_1F_L (REG_SCL_HVSP1_BASE + 0x3E) ++#define REG_SCL_HVSP1_1F_H (REG_SCL_HVSP1_BASE + 0x3F) ++#define REG_SCL_HVSP1_20_L (REG_SCL_HVSP1_BASE + 0x40) ++#define REG_SCL_HVSP1_20_H (REG_SCL_HVSP1_BASE + 0x41) ++#define REG_SCL_HVSP1_21_L (REG_SCL_HVSP1_BASE + 0x42) ++#define REG_SCL_HVSP1_21_H (REG_SCL_HVSP1_BASE + 0x43) ++#define REG_SCL_HVSP1_22_L (REG_SCL_HVSP1_BASE + 0x44) ++#define REG_SCL_HVSP1_22_H (REG_SCL_HVSP1_BASE + 0x45) ++#define REG_SCL_HVSP1_23_L (REG_SCL_HVSP1_BASE + 0x46) ++#define REG_SCL_HVSP1_23_H (REG_SCL_HVSP1_BASE + 0x47) ++#define REG_SCL_HVSP1_24_L (REG_SCL_HVSP1_BASE + 0x48) ++#define REG_SCL_HVSP1_24_H (REG_SCL_HVSP1_BASE + 0x49) ++#define REG_SCL_HVSP1_25_L (REG_SCL_HVSP1_BASE + 0x4A) ++#define REG_SCL_HVSP1_25_H (REG_SCL_HVSP1_BASE + 0x4B) ++#define REG_SCL_HVSP1_26_L (REG_SCL_HVSP1_BASE + 0x4C) ++#define REG_SCL_HVSP1_26_H (REG_SCL_HVSP1_BASE + 0x4D) ++#define REG_SCL_HVSP1_27_L (REG_SCL_HVSP1_BASE + 0x4E) ++#define REG_SCL_HVSP1_27_H (REG_SCL_HVSP1_BASE + 0x4F) ++#define REG_SCL_HVSP1_28_L (REG_SCL_HVSP1_BASE + 0x50) ++#define REG_SCL_HVSP1_28_H (REG_SCL_HVSP1_BASE + 0x51) ++#define REG_SCL_HVSP1_29_L (REG_SCL_HVSP1_BASE + 0x52) ++#define REG_SCL_HVSP1_29_H (REG_SCL_HVSP1_BASE + 0x53) ++#define REG_SCL_HVSP1_2A_L (REG_SCL_HVSP1_BASE + 0x54) ++#define REG_SCL_HVSP1_2A_H (REG_SCL_HVSP1_BASE + 0x55) ++#define REG_SCL_HVSP1_2B_L (REG_SCL_HVSP1_BASE + 0x56) ++#define REG_SCL_HVSP1_2B_H (REG_SCL_HVSP1_BASE + 0x57) ++#define REG_SCL_HVSP1_2C_L (REG_SCL_HVSP1_BASE + 0x58) ++#define REG_SCL_HVSP1_2C_H (REG_SCL_HVSP1_BASE + 0x59) ++#define REG_SCL_HVSP1_2D_L (REG_SCL_HVSP1_BASE + 0x5A) ++#define REG_SCL_HVSP1_2D_H (REG_SCL_HVSP1_BASE + 0x5B) ++#define REG_SCL_HVSP1_2E_L (REG_SCL_HVSP1_BASE + 0x5C) ++#define REG_SCL_HVSP1_2E_H (REG_SCL_HVSP1_BASE + 0x5D) ++#define REG_SCL_HVSP1_2F_L (REG_SCL_HVSP1_BASE + 0x5E) ++#define REG_SCL_HVSP1_2F_H (REG_SCL_HVSP1_BASE + 0x5F) ++#define REG_SCL_HVSP1_30_L (REG_SCL_HVSP1_BASE + 0x60) ++#define REG_SCL_HVSP1_30_H (REG_SCL_HVSP1_BASE + 0x61) ++#define REG_SCL_HVSP1_31_L (REG_SCL_HVSP1_BASE + 0x62) ++#define REG_SCL_HVSP1_31_H (REG_SCL_HVSP1_BASE + 0x63) ++#define REG_SCL_HVSP1_32_L (REG_SCL_HVSP1_BASE + 0x64) ++#define REG_SCL_HVSP1_32_H (REG_SCL_HVSP1_BASE + 0x65) ++#define REG_SCL_HVSP1_33_L (REG_SCL_HVSP1_BASE + 0x66) ++#define REG_SCL_HVSP1_33_H (REG_SCL_HVSP1_BASE + 0x67) ++#define REG_SCL_HVSP1_34_L (REG_SCL_HVSP1_BASE + 0x68) ++#define REG_SCL_HVSP1_34_H (REG_SCL_HVSP1_BASE + 0x69) ++#define REG_SCL_HVSP1_35_L (REG_SCL_HVSP1_BASE + 0x6A) ++#define REG_SCL_HVSP1_35_H (REG_SCL_HVSP1_BASE + 0x6B) ++#define REG_SCL_HVSP1_36_L (REG_SCL_HVSP1_BASE + 0x6C) ++#define REG_SCL_HVSP1_36_H (REG_SCL_HVSP1_BASE + 0x6D) ++#define REG_SCL_HVSP1_37_L (REG_SCL_HVSP1_BASE + 0x6E) ++#define REG_SCL_HVSP1_37_H (REG_SCL_HVSP1_BASE + 0x6F) ++#define REG_SCL_HVSP1_38_L (REG_SCL_HVSP1_BASE + 0x70) ++#define REG_SCL_HVSP1_38_H (REG_SCL_HVSP1_BASE + 0x71) ++#define REG_SCL_HVSP1_39_L (REG_SCL_HVSP1_BASE + 0x72) ++#define REG_SCL_HVSP1_39_H (REG_SCL_HVSP1_BASE + 0x73) ++#define REG_SCL_HVSP1_3A_L (REG_SCL_HVSP1_BASE + 0x74) ++#define REG_SCL_HVSP1_3A_H (REG_SCL_HVSP1_BASE + 0x75) ++#define REG_SCL_HVSP1_3B_L (REG_SCL_HVSP1_BASE + 0x76) ++#define REG_SCL_HVSP1_3B_H (REG_SCL_HVSP1_BASE + 0x77) ++#define REG_SCL_HVSP1_3C_L (REG_SCL_HVSP1_BASE + 0x78) ++#define REG_SCL_HVSP1_3C_H (REG_SCL_HVSP1_BASE + 0x79) ++#define REG_SCL_HVSP1_3D_L (REG_SCL_HVSP1_BASE + 0x7A) ++#define REG_SCL_HVSP1_3D_H (REG_SCL_HVSP1_BASE + 0x7B) ++#define REG_SCL_HVSP1_3E_L (REG_SCL_HVSP1_BASE + 0x7C) ++#define REG_SCL_HVSP1_3E_H (REG_SCL_HVSP1_BASE + 0x7D) ++#define REG_SCL_HVSP1_3F_L (REG_SCL_HVSP1_BASE + 0x7E) ++#define REG_SCL_HVSP1_3F_H (REG_SCL_HVSP1_BASE + 0x7F) ++#define REG_SCL_HVSP1_40_L (REG_SCL_HVSP1_BASE + 0x80) ++#define REG_SCL_HVSP1_40_H (REG_SCL_HVSP1_BASE + 0x81) ++#define REG_SCL_HVSP1_41_L (REG_SCL_HVSP1_BASE + 0x82) ++#define REG_SCL_HVSP1_41_H (REG_SCL_HVSP1_BASE + 0x83) ++#define REG_SCL_HVSP1_42_L (REG_SCL_HVSP1_BASE + 0x84) ++#define REG_SCL_HVSP1_42_H (REG_SCL_HVSP1_BASE + 0x85) ++#define REG_SCL_HVSP1_43_L (REG_SCL_HVSP1_BASE + 0x86) ++#define REG_SCL_HVSP1_43_H (REG_SCL_HVSP1_BASE + 0x87) ++#define REG_SCL_HVSP1_44_L (REG_SCL_HVSP1_BASE + 0x88) ++#define REG_SCL_HVSP1_44_H (REG_SCL_HVSP1_BASE + 0x89) ++#define REG_SCL_HVSP1_45_L (REG_SCL_HVSP1_BASE + 0x8A) ++#define REG_SCL_HVSP1_45_H (REG_SCL_HVSP1_BASE + 0x8B) ++#define REG_SCL_HVSP1_46_L (REG_SCL_HVSP1_BASE + 0x8C) ++#define REG_SCL_HVSP1_46_H (REG_SCL_HVSP1_BASE + 0x8D) ++#define REG_SCL_HVSP1_47_L (REG_SCL_HVSP1_BASE + 0x8E) ++#define REG_SCL_HVSP1_47_H (REG_SCL_HVSP1_BASE + 0x8F) ++#define REG_SCL_HVSP1_48_L (REG_SCL_HVSP1_BASE + 0x90) ++#define REG_SCL_HVSP1_48_H (REG_SCL_HVSP1_BASE + 0x91) ++#define REG_SCL_HVSP1_49_L (REG_SCL_HVSP1_BASE + 0x92) ++#define REG_SCL_HVSP1_49_H (REG_SCL_HVSP1_BASE + 0x93) ++#define REG_SCL_HVSP1_4A_L (REG_SCL_HVSP1_BASE + 0x94) ++#define REG_SCL_HVSP1_4A_H (REG_SCL_HVSP1_BASE + 0x95) ++#define REG_SCL_HVSP1_4B_L (REG_SCL_HVSP1_BASE + 0x96) ++#define REG_SCL_HVSP1_4B_H (REG_SCL_HVSP1_BASE + 0x97) ++#define REG_SCL_HVSP1_4C_L (REG_SCL_HVSP1_BASE + 0x98) ++#define REG_SCL_HVSP1_4C_H (REG_SCL_HVSP1_BASE + 0x99) ++#define REG_SCL_HVSP1_4D_L (REG_SCL_HVSP1_BASE + 0x9A) ++#define REG_SCL_HVSP1_4D_H (REG_SCL_HVSP1_BASE + 0x9B) ++#define REG_SCL_HVSP1_4E_L (REG_SCL_HVSP1_BASE + 0x9C) ++#define REG_SCL_HVSP1_4E_H (REG_SCL_HVSP1_BASE + 0x9D) ++#define REG_SCL_HVSP1_4F_L (REG_SCL_HVSP1_BASE + 0x9E) ++#define REG_SCL_HVSP1_4F_H (REG_SCL_HVSP1_BASE + 0x9F) ++#define REG_SCL_HVSP1_50_L (REG_SCL_HVSP1_BASE + 0xA0) ++#define REG_SCL_HVSP1_50_H (REG_SCL_HVSP1_BASE + 0xA1) ++#define REG_SCL_HVSP1_51_L (REG_SCL_HVSP1_BASE + 0xA2) ++#define REG_SCL_HVSP1_51_H (REG_SCL_HVSP1_BASE + 0xA3) ++#define REG_SCL_HVSP1_52_L (REG_SCL_HVSP1_BASE + 0xA4) ++#define REG_SCL_HVSP1_52_H (REG_SCL_HVSP1_BASE + 0xA5) ++#define REG_SCL_HVSP1_53_L (REG_SCL_HVSP1_BASE + 0xA6) ++#define REG_SCL_HVSP1_53_H (REG_SCL_HVSP1_BASE + 0xA7) ++#define REG_SCL_HVSP1_54_L (REG_SCL_HVSP1_BASE + 0xA8) ++#define REG_SCL_HVSP1_54_H (REG_SCL_HVSP1_BASE + 0xA9) ++#define REG_SCL_HVSP1_55_L (REG_SCL_HVSP1_BASE + 0xAA) ++#define REG_SCL_HVSP1_55_H (REG_SCL_HVSP1_BASE + 0xAB) ++#define REG_SCL_HVSP1_56_L (REG_SCL_HVSP1_BASE + 0xAC) ++#define REG_SCL_HVSP1_56_H (REG_SCL_HVSP1_BASE + 0xAD) ++#define REG_SCL_HVSP1_57_L (REG_SCL_HVSP1_BASE + 0xAE) ++#define REG_SCL_HVSP1_57_H (REG_SCL_HVSP1_BASE + 0xAF) ++#define REG_SCL_HVSP1_58_L (REG_SCL_HVSP1_BASE + 0xB0) ++#define REG_SCL_HVSP1_58_H (REG_SCL_HVSP1_BASE + 0xB1) ++#define REG_SCL_HVSP1_59_L (REG_SCL_HVSP1_BASE + 0xB2) ++#define REG_SCL_HVSP1_59_H (REG_SCL_HVSP1_BASE + 0xB3) ++#define REG_SCL_HVSP1_5A_L (REG_SCL_HVSP1_BASE + 0xB4) ++#define REG_SCL_HVSP1_5A_H (REG_SCL_HVSP1_BASE + 0xB5) ++#define REG_SCL_HVSP1_5B_L (REG_SCL_HVSP1_BASE + 0xB6) ++#define REG_SCL_HVSP1_5B_H (REG_SCL_HVSP1_BASE + 0xB7) ++#define REG_SCL_HVSP1_5C_L (REG_SCL_HVSP1_BASE + 0xB8) ++#define REG_SCL_HVSP1_5C_H (REG_SCL_HVSP1_BASE + 0xB9) ++#define REG_SCL_HVSP1_5D_L (REG_SCL_HVSP1_BASE + 0xBA) ++#define REG_SCL_HVSP1_5D_H (REG_SCL_HVSP1_BASE + 0xBB) ++#define REG_SCL_HVSP1_5E_L (REG_SCL_HVSP1_BASE + 0xBC) ++#define REG_SCL_HVSP1_5E_H (REG_SCL_HVSP1_BASE + 0xBD) ++#define REG_SCL_HVSP1_5F_L (REG_SCL_HVSP1_BASE + 0xBE) ++#define REG_SCL_HVSP1_5F_H (REG_SCL_HVSP1_BASE + 0xBF) ++#define REG_SCL_HVSP1_60_L (REG_SCL_HVSP1_BASE + 0xC0) ++#define REG_SCL_HVSP1_60_H (REG_SCL_HVSP1_BASE + 0xC1) ++#define REG_SCL_HVSP1_61_L (REG_SCL_HVSP1_BASE + 0xC2) ++#define REG_SCL_HVSP1_61_H (REG_SCL_HVSP1_BASE + 0xC3) ++#define REG_SCL_HVSP1_62_L (REG_SCL_HVSP1_BASE + 0xC4) ++#define REG_SCL_HVSP1_62_H (REG_SCL_HVSP1_BASE + 0xC5) ++#define REG_SCL_HVSP1_63_L (REG_SCL_HVSP1_BASE + 0xC6) ++#define REG_SCL_HVSP1_63_H (REG_SCL_HVSP1_BASE + 0xC7) ++#define REG_SCL_HVSP1_64_L (REG_SCL_HVSP1_BASE + 0xC8) ++#define REG_SCL_HVSP1_64_H (REG_SCL_HVSP1_BASE + 0xC9) ++#define REG_SCL_HVSP1_65_L (REG_SCL_HVSP1_BASE + 0xCA) ++#define REG_SCL_HVSP1_65_H (REG_SCL_HVSP1_BASE + 0xCB) ++#define REG_SCL_HVSP1_66_L (REG_SCL_HVSP1_BASE + 0xCC) ++#define REG_SCL_HVSP1_66_H (REG_SCL_HVSP1_BASE + 0xCD) ++#define REG_SCL_HVSP1_67_L (REG_SCL_HVSP1_BASE + 0xCE) ++#define REG_SCL_HVSP1_67_H (REG_SCL_HVSP1_BASE + 0xCF) ++#define REG_SCL_HVSP1_68_L (REG_SCL_HVSP1_BASE + 0xD0) ++#define REG_SCL_HVSP1_68_H (REG_SCL_HVSP1_BASE + 0xD1) ++#define REG_SCL_HVSP1_69_L (REG_SCL_HVSP1_BASE + 0xD2) ++#define REG_SCL_HVSP1_69_H (REG_SCL_HVSP1_BASE + 0xD3) ++#define REG_SCL_HVSP1_6A_L (REG_SCL_HVSP1_BASE + 0xD4) ++#define REG_SCL_HVSP1_6A_H (REG_SCL_HVSP1_BASE + 0xD5) ++#define REG_SCL_HVSP1_6B_L (REG_SCL_HVSP1_BASE + 0xD6) ++#define REG_SCL_HVSP1_6B_H (REG_SCL_HVSP1_BASE + 0xD7) ++#define REG_SCL_HVSP1_6C_L (REG_SCL_HVSP1_BASE + 0xD8) ++#define REG_SCL_HVSP1_6C_H (REG_SCL_HVSP1_BASE + 0xD9) ++#define REG_SCL_HVSP1_6D_L (REG_SCL_HVSP1_BASE + 0xDA) ++#define REG_SCL_HVSP1_6D_H (REG_SCL_HVSP1_BASE + 0xDB) ++#define REG_SCL_HVSP1_6E_L (REG_SCL_HVSP1_BASE + 0xDC) ++#define REG_SCL_HVSP1_6E_H (REG_SCL_HVSP1_BASE + 0xDD) ++#define REG_SCL_HVSP1_6F_L (REG_SCL_HVSP1_BASE + 0xDE) ++#define REG_SCL_HVSP1_6F_H (REG_SCL_HVSP1_BASE + 0xDF) ++#define REG_SCL_HVSP1_70_L (REG_SCL_HVSP1_BASE + 0xE0) ++#define REG_SCL_HVSP1_70_H (REG_SCL_HVSP1_BASE + 0xE1) ++#define REG_SCL_HVSP1_71_L (REG_SCL_HVSP1_BASE + 0xE2) ++#define REG_SCL_HVSP1_71_H (REG_SCL_HVSP1_BASE + 0xE3) ++#define REG_SCL_HVSP1_72_L (REG_SCL_HVSP1_BASE + 0xE4) ++#define REG_SCL_HVSP1_72_H (REG_SCL_HVSP1_BASE + 0xE5) ++#define REG_SCL_HVSP1_73_L (REG_SCL_HVSP1_BASE + 0xE6) ++#define REG_SCL_HVSP1_73_H (REG_SCL_HVSP1_BASE + 0xE7) ++#define REG_SCL_HVSP1_74_L (REG_SCL_HVSP1_BASE + 0xE8) ++#define REG_SCL_HVSP1_74_H (REG_SCL_HVSP1_BASE + 0xE9) ++#define REG_SCL_HVSP1_75_L (REG_SCL_HVSP1_BASE + 0xEA) ++#define REG_SCL_HVSP1_75_H (REG_SCL_HVSP1_BASE + 0xEB) ++#define REG_SCL_HVSP1_76_L (REG_SCL_HVSP1_BASE + 0xEC) ++#define REG_SCL_HVSP1_76_H (REG_SCL_HVSP1_BASE + 0xED) ++#define REG_SCL_HVSP1_77_L (REG_SCL_HVSP1_BASE + 0xEE) ++#define REG_SCL_HVSP1_77_H (REG_SCL_HVSP1_BASE + 0xEF) ++#define REG_SCL_HVSP1_78_L (REG_SCL_HVSP1_BASE + 0xF0) ++#define REG_SCL_HVSP1_78_H (REG_SCL_HVSP1_BASE + 0xF1) ++#define REG_SCL_HVSP1_79_L (REG_SCL_HVSP1_BASE + 0xF2) ++#define REG_SCL_HVSP1_79_H (REG_SCL_HVSP1_BASE + 0xF3) ++#define REG_SCL_HVSP1_7A_L (REG_SCL_HVSP1_BASE + 0xF4) ++#define REG_SCL_HVSP1_7A_H (REG_SCL_HVSP1_BASE + 0xF5) ++#define REG_SCL_HVSP1_7B_L (REG_SCL_HVSP1_BASE + 0xF6) ++#define REG_SCL_HVSP1_7B_H (REG_SCL_HVSP1_BASE + 0xF7) ++#define REG_SCL_HVSP1_7C_L (REG_SCL_HVSP1_BASE + 0xF8) ++#define REG_SCL_HVSP1_7C_H (REG_SCL_HVSP1_BASE + 0xF9) ++#define REG_SCL_HVSP1_7D_L (REG_SCL_HVSP1_BASE + 0xFA) ++#define REG_SCL_HVSP1_7D_H (REG_SCL_HVSP1_BASE + 0xFB) ++#define REG_SCL_HVSP1_7E_L (REG_SCL_HVSP1_BASE + 0xFC) ++#define REG_SCL_HVSP1_7E_H (REG_SCL_HVSP1_BASE + 0xFD) ++#define REG_SCL_HVSP1_7F_L (REG_SCL_HVSP1_BASE + 0xFE) ++#define REG_SCL_HVSP1_7F_H (REG_SCL_HVSP1_BASE + 0xFF) ++ ++#define REG_SCL_HVSP2_00_L (REG_SCL_HVSP2_BASE + 0x00) ++#define REG_SCL_HVSP2_00_H (REG_SCL_HVSP2_BASE + 0x01) ++#define REG_SCL_HVSP2_01_L (REG_SCL_HVSP2_BASE + 0x02) ++#define REG_SCL_HVSP2_01_H (REG_SCL_HVSP2_BASE + 0x03) ++#define REG_SCL_HVSP2_02_L (REG_SCL_HVSP2_BASE + 0x04) ++#define REG_SCL_HVSP2_02_H (REG_SCL_HVSP2_BASE + 0x05) ++#define REG_SCL_HVSP2_03_L (REG_SCL_HVSP2_BASE + 0x06) ++#define REG_SCL_HVSP2_03_H (REG_SCL_HVSP2_BASE + 0x07) ++#define REG_SCL_HVSP2_04_L (REG_SCL_HVSP2_BASE + 0x08) ++#define REG_SCL_HVSP2_04_H (REG_SCL_HVSP2_BASE + 0x09) ++#define REG_SCL_HVSP2_05_L (REG_SCL_HVSP2_BASE + 0x0A) ++#define REG_SCL_HVSP2_05_H (REG_SCL_HVSP2_BASE + 0x0B) ++#define REG_SCL_HVSP2_06_L (REG_SCL_HVSP2_BASE + 0x0C) ++#define REG_SCL_HVSP2_06_H (REG_SCL_HVSP2_BASE + 0x0D) ++#define REG_SCL_HVSP2_07_L (REG_SCL_HVSP2_BASE + 0x0E) ++#define REG_SCL_HVSP2_07_H (REG_SCL_HVSP2_BASE + 0x0F) ++#define REG_SCL_HVSP2_08_L (REG_SCL_HVSP2_BASE + 0x10) ++#define REG_SCL_HVSP2_08_H (REG_SCL_HVSP2_BASE + 0x11) ++#define REG_SCL_HVSP2_09_L (REG_SCL_HVSP2_BASE + 0x12) ++#define REG_SCL_HVSP2_09_H (REG_SCL_HVSP2_BASE + 0x13) ++#define REG_SCL_HVSP2_0A_L (REG_SCL_HVSP2_BASE + 0x14) ++#define REG_SCL_HVSP2_0A_H (REG_SCL_HVSP2_BASE + 0x15) ++#define REG_SCL_HVSP2_0B_L (REG_SCL_HVSP2_BASE + 0x16) ++#define REG_SCL_HVSP2_0B_H (REG_SCL_HVSP2_BASE + 0x17) ++#define REG_SCL_HVSP2_0C_L (REG_SCL_HVSP2_BASE + 0x18) ++#define REG_SCL_HVSP2_0C_H (REG_SCL_HVSP2_BASE + 0x19) ++#define REG_SCL_HVSP2_0D_L (REG_SCL_HVSP2_BASE + 0x1A) ++#define REG_SCL_HVSP2_0D_H (REG_SCL_HVSP2_BASE + 0x1B) ++#define REG_SCL_HVSP2_0E_L (REG_SCL_HVSP2_BASE + 0x1C) ++#define REG_SCL_HVSP2_0E_H (REG_SCL_HVSP2_BASE + 0x1D) ++#define REG_SCL_HVSP2_0F_L (REG_SCL_HVSP2_BASE + 0x1E) ++#define REG_SCL_HVSP2_0F_H (REG_SCL_HVSP2_BASE + 0x1F) ++#define REG_SCL_HVSP2_10_L (REG_SCL_HVSP2_BASE + 0x20) ++#define REG_SCL_HVSP2_10_H (REG_SCL_HVSP2_BASE + 0x21) ++#define REG_SCL_HVSP2_11_L (REG_SCL_HVSP2_BASE + 0x22) ++#define REG_SCL_HVSP2_11_H (REG_SCL_HVSP2_BASE + 0x23) ++#define REG_SCL_HVSP2_12_L (REG_SCL_HVSP2_BASE + 0x24) ++#define REG_SCL_HVSP2_12_H (REG_SCL_HVSP2_BASE + 0x25) ++#define REG_SCL_HVSP2_13_L (REG_SCL_HVSP2_BASE + 0x26) ++#define REG_SCL_HVSP2_13_H (REG_SCL_HVSP2_BASE + 0x27) ++#define REG_SCL_HVSP2_14_L (REG_SCL_HVSP2_BASE + 0x28) ++#define REG_SCL_HVSP2_14_H (REG_SCL_HVSP2_BASE + 0x29) ++#define REG_SCL_HVSP2_15_L (REG_SCL_HVSP2_BASE + 0x2A) ++#define REG_SCL_HVSP2_15_H (REG_SCL_HVSP2_BASE + 0x2B) ++#define REG_SCL_HVSP2_16_L (REG_SCL_HVSP2_BASE + 0x2C) ++#define REG_SCL_HVSP2_16_H (REG_SCL_HVSP2_BASE + 0x2D) ++#define REG_SCL_HVSP2_17_L (REG_SCL_HVSP2_BASE + 0x2E) ++#define REG_SCL_HVSP2_17_H (REG_SCL_HVSP2_BASE + 0x2F) ++#define REG_SCL_HVSP2_18_L (REG_SCL_HVSP2_BASE + 0x30) ++#define REG_SCL_HVSP2_18_H (REG_SCL_HVSP2_BASE + 0x31) ++#define REG_SCL_HVSP2_19_L (REG_SCL_HVSP2_BASE + 0x32) ++#define REG_SCL_HVSP2_19_H (REG_SCL_HVSP2_BASE + 0x33) ++#define REG_SCL_HVSP2_1A_L (REG_SCL_HVSP2_BASE + 0x34) ++#define REG_SCL_HVSP2_1A_H (REG_SCL_HVSP2_BASE + 0x35) ++#define REG_SCL_HVSP2_1B_L (REG_SCL_HVSP2_BASE + 0x36) ++#define REG_SCL_HVSP2_1B_H (REG_SCL_HVSP2_BASE + 0x37) ++#define REG_SCL_HVSP2_1C_L (REG_SCL_HVSP2_BASE + 0x38) ++#define REG_SCL_HVSP2_1C_H (REG_SCL_HVSP2_BASE + 0x39) ++#define REG_SCL_HVSP2_1D_L (REG_SCL_HVSP2_BASE + 0x3A) ++#define REG_SCL_HVSP2_1D_H (REG_SCL_HVSP2_BASE + 0x3B) ++#define REG_SCL_HVSP2_1E_L (REG_SCL_HVSP2_BASE + 0x3C) ++#define REG_SCL_HVSP2_1E_H (REG_SCL_HVSP2_BASE + 0x3D) ++#define REG_SCL_HVSP2_1F_L (REG_SCL_HVSP2_BASE + 0x3E) ++#define REG_SCL_HVSP2_1F_H (REG_SCL_HVSP2_BASE + 0x3F) ++#define REG_SCL_HVSP2_20_L (REG_SCL_HVSP2_BASE + 0x40) ++#define REG_SCL_HVSP2_20_H (REG_SCL_HVSP2_BASE + 0x41) ++#define REG_SCL_HVSP2_21_L (REG_SCL_HVSP2_BASE + 0x42) ++#define REG_SCL_HVSP2_21_H (REG_SCL_HVSP2_BASE + 0x43) ++#define REG_SCL_HVSP2_22_L (REG_SCL_HVSP2_BASE + 0x44) ++#define REG_SCL_HVSP2_22_H (REG_SCL_HVSP2_BASE + 0x45) ++#define REG_SCL_HVSP2_23_L (REG_SCL_HVSP2_BASE + 0x46) ++#define REG_SCL_HVSP2_23_H (REG_SCL_HVSP2_BASE + 0x47) ++#define REG_SCL_HVSP2_24_L (REG_SCL_HVSP2_BASE + 0x48) ++#define REG_SCL_HVSP2_24_H (REG_SCL_HVSP2_BASE + 0x49) ++#define REG_SCL_HVSP2_25_L (REG_SCL_HVSP2_BASE + 0x4A) ++#define REG_SCL_HVSP2_25_H (REG_SCL_HVSP2_BASE + 0x4B) ++#define REG_SCL_HVSP2_26_L (REG_SCL_HVSP2_BASE + 0x4C) ++#define REG_SCL_HVSP2_26_H (REG_SCL_HVSP2_BASE + 0x4D) ++#define REG_SCL_HVSP2_27_L (REG_SCL_HVSP2_BASE + 0x4E) ++#define REG_SCL_HVSP2_27_H (REG_SCL_HVSP2_BASE + 0x4F) ++#define REG_SCL_HVSP2_28_L (REG_SCL_HVSP2_BASE + 0x50) ++#define REG_SCL_HVSP2_28_H (REG_SCL_HVSP2_BASE + 0x51) ++#define REG_SCL_HVSP2_29_L (REG_SCL_HVSP2_BASE + 0x52) ++#define REG_SCL_HVSP2_29_H (REG_SCL_HVSP2_BASE + 0x53) ++#define REG_SCL_HVSP2_2A_L (REG_SCL_HVSP2_BASE + 0x54) ++#define REG_SCL_HVSP2_2A_H (REG_SCL_HVSP2_BASE + 0x55) ++#define REG_SCL_HVSP2_2B_L (REG_SCL_HVSP2_BASE + 0x56) ++#define REG_SCL_HVSP2_2B_H (REG_SCL_HVSP2_BASE + 0x57) ++#define REG_SCL_HVSP2_2C_L (REG_SCL_HVSP2_BASE + 0x58) ++#define REG_SCL_HVSP2_2C_H (REG_SCL_HVSP2_BASE + 0x59) ++#define REG_SCL_HVSP2_2D_L (REG_SCL_HVSP2_BASE + 0x5A) ++#define REG_SCL_HVSP2_2D_H (REG_SCL_HVSP2_BASE + 0x5B) ++#define REG_SCL_HVSP2_2E_L (REG_SCL_HVSP2_BASE + 0x5C) ++#define REG_SCL_HVSP2_2E_H (REG_SCL_HVSP2_BASE + 0x5D) ++#define REG_SCL_HVSP2_2F_L (REG_SCL_HVSP2_BASE + 0x5E) ++#define REG_SCL_HVSP2_2F_H (REG_SCL_HVSP2_BASE + 0x5F) ++#define REG_SCL_HVSP2_30_L (REG_SCL_HVSP2_BASE + 0x60) ++#define REG_SCL_HVSP2_30_H (REG_SCL_HVSP2_BASE + 0x61) ++#define REG_SCL_HVSP2_31_L (REG_SCL_HVSP2_BASE + 0x62) ++#define REG_SCL_HVSP2_31_H (REG_SCL_HVSP2_BASE + 0x63) ++#define REG_SCL_HVSP2_32_L (REG_SCL_HVSP2_BASE + 0x64) ++#define REG_SCL_HVSP2_32_H (REG_SCL_HVSP2_BASE + 0x65) ++#define REG_SCL_HVSP2_33_L (REG_SCL_HVSP2_BASE + 0x66) ++#define REG_SCL_HVSP2_33_H (REG_SCL_HVSP2_BASE + 0x67) ++#define REG_SCL_HVSP2_34_L (REG_SCL_HVSP2_BASE + 0x68) ++#define REG_SCL_HVSP2_34_H (REG_SCL_HVSP2_BASE + 0x69) ++#define REG_SCL_HVSP2_35_L (REG_SCL_HVSP2_BASE + 0x6A) ++#define REG_SCL_HVSP2_35_H (REG_SCL_HVSP2_BASE + 0x6B) ++#define REG_SCL_HVSP2_36_L (REG_SCL_HVSP2_BASE + 0x6C) ++#define REG_SCL_HVSP2_36_H (REG_SCL_HVSP2_BASE + 0x6D) ++#define REG_SCL_HVSP2_37_L (REG_SCL_HVSP2_BASE + 0x6E) ++#define REG_SCL_HVSP2_37_H (REG_SCL_HVSP2_BASE + 0x6F) ++#define REG_SCL_HVSP2_38_L (REG_SCL_HVSP2_BASE + 0x70) ++#define REG_SCL_HVSP2_38_H (REG_SCL_HVSP2_BASE + 0x71) ++#define REG_SCL_HVSP2_39_L (REG_SCL_HVSP2_BASE + 0x72) ++#define REG_SCL_HVSP2_39_H (REG_SCL_HVSP2_BASE + 0x73) ++#define REG_SCL_HVSP2_3A_L (REG_SCL_HVSP2_BASE + 0x74) ++#define REG_SCL_HVSP2_3A_H (REG_SCL_HVSP2_BASE + 0x75) ++#define REG_SCL_HVSP2_3B_L (REG_SCL_HVSP2_BASE + 0x76) ++#define REG_SCL_HVSP2_3B_H (REG_SCL_HVSP2_BASE + 0x77) ++#define REG_SCL_HVSP2_3C_L (REG_SCL_HVSP2_BASE + 0x78) ++#define REG_SCL_HVSP2_3C_H (REG_SCL_HVSP2_BASE + 0x79) ++#define REG_SCL_HVSP2_3D_L (REG_SCL_HVSP2_BASE + 0x7A) ++#define REG_SCL_HVSP2_3D_H (REG_SCL_HVSP2_BASE + 0x7B) ++#define REG_SCL_HVSP2_3E_L (REG_SCL_HVSP2_BASE + 0x7C) ++#define REG_SCL_HVSP2_3E_H (REG_SCL_HVSP2_BASE + 0x7D) ++#define REG_SCL_HVSP2_3F_L (REG_SCL_HVSP2_BASE + 0x7E) ++#define REG_SCL_HVSP2_3F_H (REG_SCL_HVSP2_BASE + 0x7F) ++#define REG_SCL_HVSP2_40_L (REG_SCL_HVSP2_BASE + 0x80) ++#define REG_SCL_HVSP2_40_H (REG_SCL_HVSP2_BASE + 0x81) ++#define REG_SCL_HVSP2_41_L (REG_SCL_HVSP2_BASE + 0x82) ++#define REG_SCL_HVSP2_41_H (REG_SCL_HVSP2_BASE + 0x83) ++#define REG_SCL_HVSP2_42_L (REG_SCL_HVSP2_BASE + 0x84) ++#define REG_SCL_HVSP2_42_H (REG_SCL_HVSP2_BASE + 0x85) ++#define REG_SCL_HVSP2_43_L (REG_SCL_HVSP2_BASE + 0x86) ++#define REG_SCL_HVSP2_43_H (REG_SCL_HVSP2_BASE + 0x87) ++#define REG_SCL_HVSP2_44_L (REG_SCL_HVSP2_BASE + 0x88) ++#define REG_SCL_HVSP2_44_H (REG_SCL_HVSP2_BASE + 0x89) ++#define REG_SCL_HVSP2_45_L (REG_SCL_HVSP2_BASE + 0x8A) ++#define REG_SCL_HVSP2_45_H (REG_SCL_HVSP2_BASE + 0x8B) ++#define REG_SCL_HVSP2_46_L (REG_SCL_HVSP2_BASE + 0x8C) ++#define REG_SCL_HVSP2_46_H (REG_SCL_HVSP2_BASE + 0x8D) ++#define REG_SCL_HVSP2_47_L (REG_SCL_HVSP2_BASE + 0x8E) ++#define REG_SCL_HVSP2_47_H (REG_SCL_HVSP2_BASE + 0x8F) ++#define REG_SCL_HVSP2_48_L (REG_SCL_HVSP2_BASE + 0x90) ++#define REG_SCL_HVSP2_48_H (REG_SCL_HVSP2_BASE + 0x91) ++#define REG_SCL_HVSP2_49_L (REG_SCL_HVSP2_BASE + 0x92) ++#define REG_SCL_HVSP2_49_H (REG_SCL_HVSP2_BASE + 0x93) ++#define REG_SCL_HVSP2_4A_L (REG_SCL_HVSP2_BASE + 0x94) ++#define REG_SCL_HVSP2_4A_H (REG_SCL_HVSP2_BASE + 0x95) ++#define REG_SCL_HVSP2_4B_L (REG_SCL_HVSP2_BASE + 0x96) ++#define REG_SCL_HVSP2_4B_H (REG_SCL_HVSP2_BASE + 0x97) ++#define REG_SCL_HVSP2_4C_L (REG_SCL_HVSP2_BASE + 0x98) ++#define REG_SCL_HVSP2_4C_H (REG_SCL_HVSP2_BASE + 0x99) ++#define REG_SCL_HVSP2_4D_L (REG_SCL_HVSP2_BASE + 0x9A) ++#define REG_SCL_HVSP2_4D_H (REG_SCL_HVSP2_BASE + 0x9B) ++#define REG_SCL_HVSP2_4E_L (REG_SCL_HVSP2_BASE + 0x9C) ++#define REG_SCL_HVSP2_4E_H (REG_SCL_HVSP2_BASE + 0x9D) ++#define REG_SCL_HVSP2_4F_L (REG_SCL_HVSP2_BASE + 0x9E) ++#define REG_SCL_HVSP2_4F_H (REG_SCL_HVSP2_BASE + 0x9F) ++#define REG_SCL_HVSP2_50_L (REG_SCL_HVSP2_BASE + 0xA0) ++#define REG_SCL_HVSP2_50_H (REG_SCL_HVSP2_BASE + 0xA1) ++#define REG_SCL_HVSP2_51_L (REG_SCL_HVSP2_BASE + 0xA2) ++#define REG_SCL_HVSP2_51_H (REG_SCL_HVSP2_BASE + 0xA3) ++#define REG_SCL_HVSP2_52_L (REG_SCL_HVSP2_BASE + 0xA4) ++#define REG_SCL_HVSP2_52_H (REG_SCL_HVSP2_BASE + 0xA5) ++#define REG_SCL_HVSP2_53_L (REG_SCL_HVSP2_BASE + 0xA6) ++#define REG_SCL_HVSP2_53_H (REG_SCL_HVSP2_BASE + 0xA7) ++#define REG_SCL_HVSP2_54_L (REG_SCL_HVSP2_BASE + 0xA8) ++#define REG_SCL_HVSP2_54_H (REG_SCL_HVSP2_BASE + 0xA9) ++#define REG_SCL_HVSP2_55_L (REG_SCL_HVSP2_BASE + 0xAA) ++#define REG_SCL_HVSP2_55_H (REG_SCL_HVSP2_BASE + 0xAB) ++#define REG_SCL_HVSP2_56_L (REG_SCL_HVSP2_BASE + 0xAC) ++#define REG_SCL_HVSP2_56_H (REG_SCL_HVSP2_BASE + 0xAD) ++#define REG_SCL_HVSP2_57_L (REG_SCL_HVSP2_BASE + 0xAE) ++#define REG_SCL_HVSP2_57_H (REG_SCL_HVSP2_BASE + 0xAF) ++#define REG_SCL_HVSP2_58_L (REG_SCL_HVSP2_BASE + 0xB0) ++#define REG_SCL_HVSP2_58_H (REG_SCL_HVSP2_BASE + 0xB1) ++#define REG_SCL_HVSP2_59_L (REG_SCL_HVSP2_BASE + 0xB2) ++#define REG_SCL_HVSP2_59_H (REG_SCL_HVSP2_BASE + 0xB3) ++#define REG_SCL_HVSP2_5A_L (REG_SCL_HVSP2_BASE + 0xB4) ++#define REG_SCL_HVSP2_5A_H (REG_SCL_HVSP2_BASE + 0xB5) ++#define REG_SCL_HVSP2_5B_L (REG_SCL_HVSP2_BASE + 0xB6) ++#define REG_SCL_HVSP2_5B_H (REG_SCL_HVSP2_BASE + 0xB7) ++#define REG_SCL_HVSP2_5C_L (REG_SCL_HVSP2_BASE + 0xB8) ++#define REG_SCL_HVSP2_5C_H (REG_SCL_HVSP2_BASE + 0xB9) ++#define REG_SCL_HVSP2_5D_L (REG_SCL_HVSP2_BASE + 0xBA) ++#define REG_SCL_HVSP2_5D_H (REG_SCL_HVSP2_BASE + 0xBB) ++#define REG_SCL_HVSP2_5E_L (REG_SCL_HVSP2_BASE + 0xBC) ++#define REG_SCL_HVSP2_5E_H (REG_SCL_HVSP2_BASE + 0xBD) ++#define REG_SCL_HVSP2_5F_L (REG_SCL_HVSP2_BASE + 0xBE) ++#define REG_SCL_HVSP2_5F_H (REG_SCL_HVSP2_BASE + 0xBF) ++#define REG_SCL_HVSP2_60_L (REG_SCL_HVSP2_BASE + 0xC0) ++#define REG_SCL_HVSP2_60_H (REG_SCL_HVSP2_BASE + 0xC1) ++#define REG_SCL_HVSP2_61_L (REG_SCL_HVSP2_BASE + 0xC2) ++#define REG_SCL_HVSP2_61_H (REG_SCL_HVSP2_BASE + 0xC3) ++#define REG_SCL_HVSP2_62_L (REG_SCL_HVSP2_BASE + 0xC4) ++#define REG_SCL_HVSP2_62_H (REG_SCL_HVSP2_BASE + 0xC5) ++#define REG_SCL_HVSP2_63_L (REG_SCL_HVSP2_BASE + 0xC6) ++#define REG_SCL_HVSP2_63_H (REG_SCL_HVSP2_BASE + 0xC7) ++#define REG_SCL_HVSP2_64_L (REG_SCL_HVSP2_BASE + 0xC8) ++#define REG_SCL_HVSP2_64_H (REG_SCL_HVSP2_BASE + 0xC9) ++#define REG_SCL_HVSP2_65_L (REG_SCL_HVSP2_BASE + 0xCA) ++#define REG_SCL_HVSP2_65_H (REG_SCL_HVSP2_BASE + 0xCB) ++#define REG_SCL_HVSP2_66_L (REG_SCL_HVSP2_BASE + 0xCC) ++#define REG_SCL_HVSP2_66_H (REG_SCL_HVSP2_BASE + 0xCD) ++#define REG_SCL_HVSP2_67_L (REG_SCL_HVSP2_BASE + 0xCE) ++#define REG_SCL_HVSP2_67_H (REG_SCL_HVSP2_BASE + 0xCF) ++#define REG_SCL_HVSP2_68_L (REG_SCL_HVSP2_BASE + 0xD0) ++#define REG_SCL_HVSP2_68_H (REG_SCL_HVSP2_BASE + 0xD1) ++#define REG_SCL_HVSP2_69_L (REG_SCL_HVSP2_BASE + 0xD2) ++#define REG_SCL_HVSP2_69_H (REG_SCL_HVSP2_BASE + 0xD3) ++#define REG_SCL_HVSP2_6A_L (REG_SCL_HVSP2_BASE + 0xD4) ++#define REG_SCL_HVSP2_6A_H (REG_SCL_HVSP2_BASE + 0xD5) ++#define REG_SCL_HVSP2_6B_L (REG_SCL_HVSP2_BASE + 0xD6) ++#define REG_SCL_HVSP2_6B_H (REG_SCL_HVSP2_BASE + 0xD7) ++#define REG_SCL_HVSP2_6C_L (REG_SCL_HVSP2_BASE + 0xD8) ++#define REG_SCL_HVSP2_6C_H (REG_SCL_HVSP2_BASE + 0xD9) ++#define REG_SCL_HVSP2_6D_L (REG_SCL_HVSP2_BASE + 0xDA) ++#define REG_SCL_HVSP2_6D_H (REG_SCL_HVSP2_BASE + 0xDB) ++#define REG_SCL_HVSP2_6E_L (REG_SCL_HVSP2_BASE + 0xDC) ++#define REG_SCL_HVSP2_6E_H (REG_SCL_HVSP2_BASE + 0xDD) ++#define REG_SCL_HVSP2_6F_L (REG_SCL_HVSP2_BASE + 0xDE) ++#define REG_SCL_HVSP2_6F_H (REG_SCL_HVSP2_BASE + 0xDF) ++#define REG_SCL_HVSP2_70_L (REG_SCL_HVSP2_BASE + 0xE0) ++#define REG_SCL_HVSP2_70_H (REG_SCL_HVSP2_BASE + 0xE1) ++#define REG_SCL_HVSP2_71_L (REG_SCL_HVSP2_BASE + 0xE2) ++#define REG_SCL_HVSP2_71_H (REG_SCL_HVSP2_BASE + 0xE3) ++#define REG_SCL_HVSP2_72_L (REG_SCL_HVSP2_BASE + 0xE4) ++#define REG_SCL_HVSP2_72_H (REG_SCL_HVSP2_BASE + 0xE5) ++#define REG_SCL_HVSP2_73_L (REG_SCL_HVSP2_BASE + 0xE6) ++#define REG_SCL_HVSP2_73_H (REG_SCL_HVSP2_BASE + 0xE7) ++#define REG_SCL_HVSP2_74_L (REG_SCL_HVSP2_BASE + 0xE8) ++#define REG_SCL_HVSP2_74_H (REG_SCL_HVSP2_BASE + 0xE9) ++#define REG_SCL_HVSP2_75_L (REG_SCL_HVSP2_BASE + 0xEA) ++#define REG_SCL_HVSP2_75_H (REG_SCL_HVSP2_BASE + 0xEB) ++#define REG_SCL_HVSP2_76_L (REG_SCL_HVSP2_BASE + 0xEC) ++#define REG_SCL_HVSP2_76_H (REG_SCL_HVSP2_BASE + 0xED) ++#define REG_SCL_HVSP2_77_L (REG_SCL_HVSP2_BASE + 0xEE) ++#define REG_SCL_HVSP2_77_H (REG_SCL_HVSP2_BASE + 0xEF) ++#define REG_SCL_HVSP2_78_L (REG_SCL_HVSP2_BASE + 0xF0) ++#define REG_SCL_HVSP2_78_H (REG_SCL_HVSP2_BASE + 0xF1) ++#define REG_SCL_HVSP2_79_L (REG_SCL_HVSP2_BASE + 0xF2) ++#define REG_SCL_HVSP2_79_H (REG_SCL_HVSP2_BASE + 0xF3) ++#define REG_SCL_HVSP2_7A_L (REG_SCL_HVSP2_BASE + 0xF4) ++#define REG_SCL_HVSP2_7A_H (REG_SCL_HVSP2_BASE + 0xF5) ++#define REG_SCL_HVSP2_7B_L (REG_SCL_HVSP2_BASE + 0xF6) ++#define REG_SCL_HVSP2_7B_H (REG_SCL_HVSP2_BASE + 0xF7) ++#define REG_SCL_HVSP2_7C_L (REG_SCL_HVSP2_BASE + 0xF8) ++#define REG_SCL_HVSP2_7C_H (REG_SCL_HVSP2_BASE + 0xF9) ++#define REG_SCL_HVSP2_7D_L (REG_SCL_HVSP2_BASE + 0xFA) ++#define REG_SCL_HVSP2_7D_H (REG_SCL_HVSP2_BASE + 0xFB) ++#define REG_SCL_HVSP2_7E_L (REG_SCL_HVSP2_BASE + 0xFC) ++#define REG_SCL_HVSP2_7E_H (REG_SCL_HVSP2_BASE + 0xFD) ++#define REG_SCL_HVSP2_7F_L (REG_SCL_HVSP2_BASE + 0xFE) ++#define REG_SCL_HVSP2_7F_H (REG_SCL_HVSP2_BASE + 0xFF) ++ ++#define REG_SCL_LDC_00_L (REG_SCL_LDC_BASE + 0x00) ++#define REG_SCL_LDC_00_H (REG_SCL_LDC_BASE + 0x01) ++#define REG_SCL_LDC_01_L (REG_SCL_LDC_BASE + 0x02) ++#define REG_SCL_LDC_01_H (REG_SCL_LDC_BASE + 0x03) ++#define REG_SCL_LDC_02_L (REG_SCL_LDC_BASE + 0x04) ++#define REG_SCL_LDC_02_H (REG_SCL_LDC_BASE + 0x05) ++#define REG_SCL_LDC_03_L (REG_SCL_LDC_BASE + 0x06) ++#define REG_SCL_LDC_03_H (REG_SCL_LDC_BASE + 0x07) ++#define REG_SCL_LDC_04_L (REG_SCL_LDC_BASE + 0x08) ++#define REG_SCL_LDC_04_H (REG_SCL_LDC_BASE + 0x09) ++#define REG_SCL_LDC_05_L (REG_SCL_LDC_BASE + 0x0A) ++#define REG_SCL_LDC_05_H (REG_SCL_LDC_BASE + 0x0B) ++#define REG_SCL_LDC_06_L (REG_SCL_LDC_BASE + 0x0C) ++#define REG_SCL_LDC_06_H (REG_SCL_LDC_BASE + 0x0D) ++#define REG_SCL_LDC_07_L (REG_SCL_LDC_BASE + 0x0E) ++#define REG_SCL_LDC_07_H (REG_SCL_LDC_BASE + 0x0F) ++#define REG_SCL_LDC_08_L (REG_SCL_LDC_BASE + 0x10) ++#define REG_SCL_LDC_08_H (REG_SCL_LDC_BASE + 0x11) ++#define REG_SCL_LDC_09_L (REG_SCL_LDC_BASE + 0x12) ++#define REG_SCL_LDC_09_H (REG_SCL_LDC_BASE + 0x13) ++#define REG_SCL_LDC_0A_L (REG_SCL_LDC_BASE + 0x14) ++#define REG_SCL_LDC_0A_H (REG_SCL_LDC_BASE + 0x15) ++#define REG_SCL_LDC_0B_L (REG_SCL_LDC_BASE + 0x16) ++#define REG_SCL_LDC_0B_H (REG_SCL_LDC_BASE + 0x17) ++#define REG_SCL_LDC_0C_L (REG_SCL_LDC_BASE + 0x18) ++#define REG_SCL_LDC_0C_H (REG_SCL_LDC_BASE + 0x19) ++#define REG_SCL_LDC_0D_L (REG_SCL_LDC_BASE + 0x1A) ++#define REG_SCL_LDC_0D_H (REG_SCL_LDC_BASE + 0x1B) ++#define REG_SCL_LDC_0E_L (REG_SCL_LDC_BASE + 0x1C) ++#define REG_SCL_LDC_0E_H (REG_SCL_LDC_BASE + 0x1D) ++#define REG_SCL_LDC_0F_L (REG_SCL_LDC_BASE + 0x1E) ++#define REG_SCL_LDC_0F_H (REG_SCL_LDC_BASE + 0x1F) ++#define REG_SCL_LDC_10_L (REG_SCL_LDC_BASE + 0x20) ++#define REG_SCL_LDC_10_H (REG_SCL_LDC_BASE + 0x21) ++#define REG_SCL_LDC_11_L (REG_SCL_LDC_BASE + 0x22) ++#define REG_SCL_LDC_11_H (REG_SCL_LDC_BASE + 0x23) ++#define REG_SCL_LDC_12_L (REG_SCL_LDC_BASE + 0x24) ++#define REG_SCL_LDC_12_H (REG_SCL_LDC_BASE + 0x25) ++#define REG_SCL_LDC_13_L (REG_SCL_LDC_BASE + 0x26) ++#define REG_SCL_LDC_13_H (REG_SCL_LDC_BASE + 0x27) ++#define REG_SCL_LDC_14_L (REG_SCL_LDC_BASE + 0x28) ++#define REG_SCL_LDC_14_H (REG_SCL_LDC_BASE + 0x29) ++#define REG_SCL_LDC_15_L (REG_SCL_LDC_BASE + 0x2A) ++#define REG_SCL_LDC_15_H (REG_SCL_LDC_BASE + 0x2B) ++#define REG_SCL_LDC_16_L (REG_SCL_LDC_BASE + 0x2C) ++#define REG_SCL_LDC_16_H (REG_SCL_LDC_BASE + 0x2D) ++#define REG_SCL_LDC_17_L (REG_SCL_LDC_BASE + 0x2E) ++#define REG_SCL_LDC_17_H (REG_SCL_LDC_BASE + 0x2F) ++#define REG_SCL_LDC_18_L (REG_SCL_LDC_BASE + 0x30) ++#define REG_SCL_LDC_18_H (REG_SCL_LDC_BASE + 0x31) ++#define REG_SCL_LDC_19_L (REG_SCL_LDC_BASE + 0x32) ++#define REG_SCL_LDC_19_H (REG_SCL_LDC_BASE + 0x33) ++#define REG_SCL_LDC_1A_L (REG_SCL_LDC_BASE + 0x34) ++#define REG_SCL_LDC_1A_H (REG_SCL_LDC_BASE + 0x35) ++#define REG_SCL_LDC_1B_L (REG_SCL_LDC_BASE + 0x36) ++#define REG_SCL_LDC_1B_H (REG_SCL_LDC_BASE + 0x37) ++#define REG_SCL_LDC_1C_L (REG_SCL_LDC_BASE + 0x38) ++#define REG_SCL_LDC_1C_H (REG_SCL_LDC_BASE + 0x39) ++#define REG_SCL_LDC_1D_L (REG_SCL_LDC_BASE + 0x3A) ++#define REG_SCL_LDC_1D_H (REG_SCL_LDC_BASE + 0x3B) ++#define REG_SCL_LDC_1E_L (REG_SCL_LDC_BASE + 0x3C) ++#define REG_SCL_LDC_1E_H (REG_SCL_LDC_BASE + 0x3D) ++#define REG_SCL_LDC_1F_L (REG_SCL_LDC_BASE + 0x3E) ++#define REG_SCL_LDC_1F_H (REG_SCL_LDC_BASE + 0x3F) ++#define REG_SCL_LDC_20_L (REG_SCL_LDC_BASE + 0x40) ++#define REG_SCL_LDC_20_H (REG_SCL_LDC_BASE + 0x41) ++#define REG_SCL_LDC_21_L (REG_SCL_LDC_BASE + 0x42) ++#define REG_SCL_LDC_21_H (REG_SCL_LDC_BASE + 0x43) ++#define REG_SCL_LDC_22_L (REG_SCL_LDC_BASE + 0x44) ++#define REG_SCL_LDC_22_H (REG_SCL_LDC_BASE + 0x45) ++#define REG_SCL_LDC_23_L (REG_SCL_LDC_BASE + 0x46) ++#define REG_SCL_LDC_23_H (REG_SCL_LDC_BASE + 0x47) ++#define REG_SCL_LDC_24_L (REG_SCL_LDC_BASE + 0x48) ++#define REG_SCL_LDC_24_H (REG_SCL_LDC_BASE + 0x49) ++#define REG_SCL_LDC_25_L (REG_SCL_LDC_BASE + 0x4A) ++#define REG_SCL_LDC_25_H (REG_SCL_LDC_BASE + 0x4B) ++#define REG_SCL_LDC_26_L (REG_SCL_LDC_BASE + 0x4C) ++#define REG_SCL_LDC_26_H (REG_SCL_LDC_BASE + 0x4D) ++#define REG_SCL_LDC_27_L (REG_SCL_LDC_BASE + 0x4E) ++#define REG_SCL_LDC_27_H (REG_SCL_LDC_BASE + 0x4F) ++#define REG_SCL_LDC_28_L (REG_SCL_LDC_BASE + 0x50) ++#define REG_SCL_LDC_28_H (REG_SCL_LDC_BASE + 0x51) ++#define REG_SCL_LDC_29_L (REG_SCL_LDC_BASE + 0x52) ++#define REG_SCL_LDC_29_H (REG_SCL_LDC_BASE + 0x53) ++#define REG_SCL_LDC_2A_L (REG_SCL_LDC_BASE + 0x54) ++#define REG_SCL_LDC_2A_H (REG_SCL_LDC_BASE + 0x55) ++#define REG_SCL_LDC_2B_L (REG_SCL_LDC_BASE + 0x56) ++#define REG_SCL_LDC_2B_H (REG_SCL_LDC_BASE + 0x57) ++#define REG_SCL_LDC_2C_L (REG_SCL_LDC_BASE + 0x58) ++#define REG_SCL_LDC_2C_H (REG_SCL_LDC_BASE + 0x59) ++#define REG_SCL_LDC_2D_L (REG_SCL_LDC_BASE + 0x5A) ++#define REG_SCL_LDC_2D_H (REG_SCL_LDC_BASE + 0x5B) ++#define REG_SCL_LDC_2E_L (REG_SCL_LDC_BASE + 0x5C) ++#define REG_SCL_LDC_2E_H (REG_SCL_LDC_BASE + 0x5D) ++#define REG_SCL_LDC_2F_L (REG_SCL_LDC_BASE + 0x5E) ++#define REG_SCL_LDC_2F_H (REG_SCL_LDC_BASE + 0x5F) ++#define REG_SCL_LDC_30_L (REG_SCL_LDC_BASE + 0x60) ++#define REG_SCL_LDC_30_H (REG_SCL_LDC_BASE + 0x61) ++#define REG_SCL_LDC_31_L (REG_SCL_LDC_BASE + 0x62) ++#define REG_SCL_LDC_31_H (REG_SCL_LDC_BASE + 0x63) ++#define REG_SCL_LDC_32_L (REG_SCL_LDC_BASE + 0x64) ++#define REG_SCL_LDC_32_H (REG_SCL_LDC_BASE + 0x65) ++#define REG_SCL_LDC_33_L (REG_SCL_LDC_BASE + 0x66) ++#define REG_SCL_LDC_33_H (REG_SCL_LDC_BASE + 0x67) ++#define REG_SCL_LDC_34_L (REG_SCL_LDC_BASE + 0x68) ++#define REG_SCL_LDC_34_H (REG_SCL_LDC_BASE + 0x69) ++#define REG_SCL_LDC_35_L (REG_SCL_LDC_BASE + 0x6A) ++#define REG_SCL_LDC_35_H (REG_SCL_LDC_BASE + 0x6B) ++#define REG_SCL_LDC_36_L (REG_SCL_LDC_BASE + 0x6C) ++#define REG_SCL_LDC_36_H (REG_SCL_LDC_BASE + 0x6D) ++#define REG_SCL_LDC_37_L (REG_SCL_LDC_BASE + 0x6E) ++#define REG_SCL_LDC_37_H (REG_SCL_LDC_BASE + 0x6F) ++#define REG_SCL_LDC_38_L (REG_SCL_LDC_BASE + 0x70) ++#define REG_SCL_LDC_38_H (REG_SCL_LDC_BASE + 0x71) ++#define REG_SCL_LDC_39_L (REG_SCL_LDC_BASE + 0x72) ++#define REG_SCL_LDC_39_H (REG_SCL_LDC_BASE + 0x73) ++#define REG_SCL_LDC_3A_L (REG_SCL_LDC_BASE + 0x74) ++#define REG_SCL_LDC_3A_H (REG_SCL_LDC_BASE + 0x75) ++#define REG_SCL_LDC_3B_L (REG_SCL_LDC_BASE + 0x76) ++#define REG_SCL_LDC_3B_H (REG_SCL_LDC_BASE + 0x77) ++#define REG_SCL_LDC_3C_L (REG_SCL_LDC_BASE + 0x78) ++#define REG_SCL_LDC_3C_H (REG_SCL_LDC_BASE + 0x79) ++#define REG_SCL_LDC_3D_L (REG_SCL_LDC_BASE + 0x7A) ++#define REG_SCL_LDC_3D_H (REG_SCL_LDC_BASE + 0x7B) ++#define REG_SCL_LDC_3E_L (REG_SCL_LDC_BASE + 0x7C) ++#define REG_SCL_LDC_3E_H (REG_SCL_LDC_BASE + 0x7D) ++#define REG_SCL_LDC_3F_L (REG_SCL_LDC_BASE + 0x7E) ++#define REG_SCL_LDC_3F_H (REG_SCL_LDC_BASE + 0x7F) ++#define REG_SCL_LDC_40_L (REG_SCL_LDC_BASE + 0x80) ++#define REG_SCL_LDC_40_H (REG_SCL_LDC_BASE + 0x81) ++#define REG_SCL_LDC_41_L (REG_SCL_LDC_BASE + 0x82) ++#define REG_SCL_LDC_41_H (REG_SCL_LDC_BASE + 0x83) ++#define REG_SCL_LDC_42_L (REG_SCL_LDC_BASE + 0x84) ++#define REG_SCL_LDC_42_H (REG_SCL_LDC_BASE + 0x85) ++#define REG_SCL_LDC_43_L (REG_SCL_LDC_BASE + 0x86) ++#define REG_SCL_LDC_43_H (REG_SCL_LDC_BASE + 0x87) ++#define REG_SCL_LDC_44_L (REG_SCL_LDC_BASE + 0x88) ++#define REG_SCL_LDC_44_H (REG_SCL_LDC_BASE + 0x89) ++#define REG_SCL_LDC_45_L (REG_SCL_LDC_BASE + 0x8A) ++#define REG_SCL_LDC_45_H (REG_SCL_LDC_BASE + 0x8B) ++#define REG_SCL_LDC_46_L (REG_SCL_LDC_BASE + 0x8C) ++#define REG_SCL_LDC_46_H (REG_SCL_LDC_BASE + 0x8D) ++#define REG_SCL_LDC_47_L (REG_SCL_LDC_BASE + 0x8E) ++#define REG_SCL_LDC_47_H (REG_SCL_LDC_BASE + 0x8F) ++#define REG_SCL_LDC_48_L (REG_SCL_LDC_BASE + 0x90) ++#define REG_SCL_LDC_48_H (REG_SCL_LDC_BASE + 0x91) ++#define REG_SCL_LDC_49_L (REG_SCL_LDC_BASE + 0x92) ++#define REG_SCL_LDC_49_H (REG_SCL_LDC_BASE + 0x93) ++#define REG_SCL_LDC_4A_L (REG_SCL_LDC_BASE + 0x94) ++#define REG_SCL_LDC_4A_H (REG_SCL_LDC_BASE + 0x95) ++#define REG_SCL_LDC_4B_L (REG_SCL_LDC_BASE + 0x96) ++#define REG_SCL_LDC_4B_H (REG_SCL_LDC_BASE + 0x97) ++#define REG_SCL_LDC_4C_L (REG_SCL_LDC_BASE + 0x98) ++#define REG_SCL_LDC_4C_H (REG_SCL_LDC_BASE + 0x99) ++#define REG_SCL_LDC_4D_L (REG_SCL_LDC_BASE + 0x9A) ++#define REG_SCL_LDC_4D_H (REG_SCL_LDC_BASE + 0x9B) ++#define REG_SCL_LDC_4E_L (REG_SCL_LDC_BASE + 0x9C) ++#define REG_SCL_LDC_4E_H (REG_SCL_LDC_BASE + 0x9D) ++#define REG_SCL_LDC_4F_L (REG_SCL_LDC_BASE + 0x9E) ++#define REG_SCL_LDC_4F_H (REG_SCL_LDC_BASE + 0x9F) ++#define REG_SCL_LDC_50_L (REG_SCL_LDC_BASE + 0xA0) ++#define REG_SCL_LDC_50_H (REG_SCL_LDC_BASE + 0xA1) ++#define REG_SCL_LDC_51_L (REG_SCL_LDC_BASE + 0xA2) ++#define REG_SCL_LDC_51_H (REG_SCL_LDC_BASE + 0xA3) ++#define REG_SCL_LDC_52_L (REG_SCL_LDC_BASE + 0xA4) ++#define REG_SCL_LDC_52_H (REG_SCL_LDC_BASE + 0xA5) ++#define REG_SCL_LDC_53_L (REG_SCL_LDC_BASE + 0xA6) ++#define REG_SCL_LDC_53_H (REG_SCL_LDC_BASE + 0xA7) ++#define REG_SCL_LDC_54_L (REG_SCL_LDC_BASE + 0xA8) ++#define REG_SCL_LDC_54_H (REG_SCL_LDC_BASE + 0xA9) ++#define REG_SCL_LDC_55_L (REG_SCL_LDC_BASE + 0xAA) ++#define REG_SCL_LDC_55_H (REG_SCL_LDC_BASE + 0xAB) ++#define REG_SCL_LDC_56_L (REG_SCL_LDC_BASE + 0xAC) ++#define REG_SCL_LDC_56_H (REG_SCL_LDC_BASE + 0xAD) ++#define REG_SCL_LDC_57_L (REG_SCL_LDC_BASE + 0xAE) ++#define REG_SCL_LDC_57_H (REG_SCL_LDC_BASE + 0xAF) ++#define REG_SCL_LDC_58_L (REG_SCL_LDC_BASE + 0xB0) ++#define REG_SCL_LDC_58_H (REG_SCL_LDC_BASE + 0xB1) ++#define REG_SCL_LDC_59_L (REG_SCL_LDC_BASE + 0xB2) ++#define REG_SCL_LDC_59_H (REG_SCL_LDC_BASE + 0xB3) ++#define REG_SCL_LDC_5A_L (REG_SCL_LDC_BASE + 0xB4) ++#define REG_SCL_LDC_5A_H (REG_SCL_LDC_BASE + 0xB5) ++#define REG_SCL_LDC_5B_L (REG_SCL_LDC_BASE + 0xB6) ++#define REG_SCL_LDC_5B_H (REG_SCL_LDC_BASE + 0xB7) ++#define REG_SCL_LDC_5C_L (REG_SCL_LDC_BASE + 0xB8) ++#define REG_SCL_LDC_5C_H (REG_SCL_LDC_BASE + 0xB9) ++#define REG_SCL_LDC_5D_L (REG_SCL_LDC_BASE + 0xBA) ++#define REG_SCL_LDC_5D_H (REG_SCL_LDC_BASE + 0xBB) ++#define REG_SCL_LDC_5E_L (REG_SCL_LDC_BASE + 0xBC) ++#define REG_SCL_LDC_5E_H (REG_SCL_LDC_BASE + 0xBD) ++#define REG_SCL_LDC_5F_L (REG_SCL_LDC_BASE + 0xBE) ++#define REG_SCL_LDC_5F_H (REG_SCL_LDC_BASE + 0xBF) ++#define REG_SCL_LDC_60_L (REG_SCL_LDC_BASE + 0xC0) ++#define REG_SCL_LDC_60_H (REG_SCL_LDC_BASE + 0xC1) ++#define REG_SCL_LDC_61_L (REG_SCL_LDC_BASE + 0xC2) ++#define REG_SCL_LDC_61_H (REG_SCL_LDC_BASE + 0xC3) ++#define REG_SCL_LDC_62_L (REG_SCL_LDC_BASE + 0xC4) ++#define REG_SCL_LDC_62_H (REG_SCL_LDC_BASE + 0xC5) ++#define REG_SCL_LDC_63_L (REG_SCL_LDC_BASE + 0xC6) ++#define REG_SCL_LDC_63_H (REG_SCL_LDC_BASE + 0xC7) ++#define REG_SCL_LDC_64_L (REG_SCL_LDC_BASE + 0xC8) ++#define REG_SCL_LDC_64_H (REG_SCL_LDC_BASE + 0xC9) ++#define REG_SCL_LDC_65_L (REG_SCL_LDC_BASE + 0xCA) ++#define REG_SCL_LDC_65_H (REG_SCL_LDC_BASE + 0xCB) ++#define REG_SCL_LDC_66_L (REG_SCL_LDC_BASE + 0xCC) ++#define REG_SCL_LDC_66_H (REG_SCL_LDC_BASE + 0xCD) ++#define REG_SCL_LDC_67_L (REG_SCL_LDC_BASE + 0xCE) ++#define REG_SCL_LDC_67_H (REG_SCL_LDC_BASE + 0xCF) ++#define REG_SCL_LDC_68_L (REG_SCL_LDC_BASE + 0xD0) ++#define REG_SCL_LDC_68_H (REG_SCL_LDC_BASE + 0xD1) ++#define REG_SCL_LDC_69_L (REG_SCL_LDC_BASE + 0xD2) ++#define REG_SCL_LDC_69_H (REG_SCL_LDC_BASE + 0xD3) ++#define REG_SCL_LDC_6A_L (REG_SCL_LDC_BASE + 0xD4) ++#define REG_SCL_LDC_6A_H (REG_SCL_LDC_BASE + 0xD5) ++#define REG_SCL_LDC_6B_L (REG_SCL_LDC_BASE + 0xD6) ++#define REG_SCL_LDC_6B_H (REG_SCL_LDC_BASE + 0xD7) ++#define REG_SCL_LDC_6C_L (REG_SCL_LDC_BASE + 0xD8) ++#define REG_SCL_LDC_6C_H (REG_SCL_LDC_BASE + 0xD9) ++#define REG_SCL_LDC_6D_L (REG_SCL_LDC_BASE + 0xDA) ++#define REG_SCL_LDC_6D_H (REG_SCL_LDC_BASE + 0xDB) ++#define REG_SCL_LDC_6E_L (REG_SCL_LDC_BASE + 0xDC) ++#define REG_SCL_LDC_6E_H (REG_SCL_LDC_BASE + 0xDD) ++#define REG_SCL_LDC_6F_L (REG_SCL_LDC_BASE + 0xDE) ++#define REG_SCL_LDC_6F_H (REG_SCL_LDC_BASE + 0xDF) ++#define REG_SCL_LDC_70_L (REG_SCL_LDC_BASE + 0xE0) ++#define REG_SCL_LDC_70_H (REG_SCL_LDC_BASE + 0xE1) ++#define REG_SCL_LDC_71_L (REG_SCL_LDC_BASE + 0xE2) ++#define REG_SCL_LDC_71_H (REG_SCL_LDC_BASE + 0xE3) ++#define REG_SCL_LDC_72_L (REG_SCL_LDC_BASE + 0xE4) ++#define REG_SCL_LDC_72_H (REG_SCL_LDC_BASE + 0xE5) ++#define REG_SCL_LDC_73_L (REG_SCL_LDC_BASE + 0xE6) ++#define REG_SCL_LDC_73_H (REG_SCL_LDC_BASE + 0xE7) ++#define REG_SCL_LDC_74_L (REG_SCL_LDC_BASE + 0xE8) ++#define REG_SCL_LDC_74_H (REG_SCL_LDC_BASE + 0xE9) ++#define REG_SCL_LDC_75_L (REG_SCL_LDC_BASE + 0xEA) ++#define REG_SCL_LDC_75_H (REG_SCL_LDC_BASE + 0xEB) ++#define REG_SCL_LDC_76_L (REG_SCL_LDC_BASE + 0xEC) ++#define REG_SCL_LDC_76_H (REG_SCL_LDC_BASE + 0xED) ++#define REG_SCL_LDC_77_L (REG_SCL_LDC_BASE + 0xEE) ++#define REG_SCL_LDC_77_H (REG_SCL_LDC_BASE + 0xEF) ++#define REG_SCL_LDC_78_L (REG_SCL_LDC_BASE + 0xF0) ++#define REG_SCL_LDC_78_H (REG_SCL_LDC_BASE + 0xF1) ++#define REG_SCL_LDC_79_L (REG_SCL_LDC_BASE + 0xF2) ++#define REG_SCL_LDC_79_H (REG_SCL_LDC_BASE + 0xF3) ++#define REG_SCL_LDC_7A_L (REG_SCL_LDC_BASE + 0xF4) ++#define REG_SCL_LDC_7A_H (REG_SCL_LDC_BASE + 0xF5) ++#define REG_SCL_LDC_7B_L (REG_SCL_LDC_BASE + 0xF6) ++#define REG_SCL_LDC_7B_H (REG_SCL_LDC_BASE + 0xF7) ++#define REG_SCL_LDC_7C_L (REG_SCL_LDC_BASE + 0xF8) ++#define REG_SCL_LDC_7C_H (REG_SCL_LDC_BASE + 0xF9) ++#define REG_SCL_LDC_7D_L (REG_SCL_LDC_BASE + 0xFA) ++#define REG_SCL_LDC_7D_H (REG_SCL_LDC_BASE + 0xFB) ++#define REG_SCL_LDC_7E_L (REG_SCL_LDC_BASE + 0xFC) ++#define REG_SCL_LDC_7E_H (REG_SCL_LDC_BASE + 0xFD) ++#define REG_SCL_LDC_7F_L (REG_SCL_LDC_BASE + 0xFE) ++#define REG_SCL_LDC_7F_H (REG_SCL_LDC_BASE + 0xFF) ++ ++#define REG_SCL_DMA0_00_L (REG_SCL_DMA0_BASE + 0x00) ++#define REG_SCL_DMA0_00_H (REG_SCL_DMA0_BASE + 0x01) ++#define REG_SCL_DMA0_01_L (REG_SCL_DMA0_BASE + 0x02) ++#define REG_SCL_DMA0_01_H (REG_SCL_DMA0_BASE + 0x03) ++#define REG_SCL_DMA0_02_L (REG_SCL_DMA0_BASE + 0x04) ++#define REG_SCL_DMA0_02_H (REG_SCL_DMA0_BASE + 0x05) ++#define REG_SCL_DMA0_03_L (REG_SCL_DMA0_BASE + 0x06) ++#define REG_SCL_DMA0_03_H (REG_SCL_DMA0_BASE + 0x07) ++#define REG_SCL_DMA0_04_L (REG_SCL_DMA0_BASE + 0x08) ++#define REG_SCL_DMA0_04_H (REG_SCL_DMA0_BASE + 0x09) ++#define REG_SCL_DMA0_05_L (REG_SCL_DMA0_BASE + 0x0A) ++#define REG_SCL_DMA0_05_H (REG_SCL_DMA0_BASE + 0x0B) ++#define REG_SCL_DMA0_06_L (REG_SCL_DMA0_BASE + 0x0C) ++#define REG_SCL_DMA0_06_H (REG_SCL_DMA0_BASE + 0x0D) ++#define REG_SCL_DMA0_07_L (REG_SCL_DMA0_BASE + 0x0E) ++#define REG_SCL_DMA0_07_H (REG_SCL_DMA0_BASE + 0x0F) ++#define REG_SCL_DMA0_08_L (REG_SCL_DMA0_BASE + 0x10) ++#define REG_SCL_DMA0_08_H (REG_SCL_DMA0_BASE + 0x11) ++#define REG_SCL_DMA0_09_L (REG_SCL_DMA0_BASE + 0x12) ++#define REG_SCL_DMA0_09_H (REG_SCL_DMA0_BASE + 0x13) ++#define REG_SCL_DMA0_0A_L (REG_SCL_DMA0_BASE + 0x14) ++#define REG_SCL_DMA0_0A_H (REG_SCL_DMA0_BASE + 0x15) ++#define REG_SCL_DMA0_0B_L (REG_SCL_DMA0_BASE + 0x16) ++#define REG_SCL_DMA0_0B_H (REG_SCL_DMA0_BASE + 0x17) ++#define REG_SCL_DMA0_0C_L (REG_SCL_DMA0_BASE + 0x18) ++#define REG_SCL_DMA0_0C_H (REG_SCL_DMA0_BASE + 0x19) ++#define REG_SCL_DMA0_0D_L (REG_SCL_DMA0_BASE + 0x1A) ++#define REG_SCL_DMA0_0D_H (REG_SCL_DMA0_BASE + 0x1B) ++#define REG_SCL_DMA0_0E_L (REG_SCL_DMA0_BASE + 0x1C) ++#define REG_SCL_DMA0_0E_H (REG_SCL_DMA0_BASE + 0x1D) ++#define REG_SCL_DMA0_0F_L (REG_SCL_DMA0_BASE + 0x1E) ++#define REG_SCL_DMA0_0F_H (REG_SCL_DMA0_BASE + 0x1F) ++#define REG_SCL_DMA0_10_L (REG_SCL_DMA0_BASE + 0x20) ++#define REG_SCL_DMA0_10_H (REG_SCL_DMA0_BASE + 0x21) ++#define REG_SCL_DMA0_11_L (REG_SCL_DMA0_BASE + 0x22) ++#define REG_SCL_DMA0_11_H (REG_SCL_DMA0_BASE + 0x23) ++#define REG_SCL_DMA0_12_L (REG_SCL_DMA0_BASE + 0x24) ++#define REG_SCL_DMA0_12_H (REG_SCL_DMA0_BASE + 0x25) ++#define REG_SCL_DMA0_13_L (REG_SCL_DMA0_BASE + 0x26) ++#define REG_SCL_DMA0_13_H (REG_SCL_DMA0_BASE + 0x27) ++#define REG_SCL_DMA0_14_L (REG_SCL_DMA0_BASE + 0x28) ++#define REG_SCL_DMA0_14_H (REG_SCL_DMA0_BASE + 0x29) ++#define REG_SCL_DMA0_15_L (REG_SCL_DMA0_BASE + 0x2A) ++#define REG_SCL_DMA0_15_H (REG_SCL_DMA0_BASE + 0x2B) ++#define REG_SCL_DMA0_16_L (REG_SCL_DMA0_BASE + 0x2C) ++#define REG_SCL_DMA0_16_H (REG_SCL_DMA0_BASE + 0x2D) ++#define REG_SCL_DMA0_17_L (REG_SCL_DMA0_BASE + 0x2E) ++#define REG_SCL_DMA0_17_H (REG_SCL_DMA0_BASE + 0x2F) ++#define REG_SCL_DMA0_18_L (REG_SCL_DMA0_BASE + 0x30) ++#define REG_SCL_DMA0_18_H (REG_SCL_DMA0_BASE + 0x31) ++#define REG_SCL_DMA0_19_L (REG_SCL_DMA0_BASE + 0x32) ++#define REG_SCL_DMA0_19_H (REG_SCL_DMA0_BASE + 0x33) ++#define REG_SCL_DMA0_1A_L (REG_SCL_DMA0_BASE + 0x34) ++#define REG_SCL_DMA0_1A_H (REG_SCL_DMA0_BASE + 0x35) ++#define REG_SCL_DMA0_1B_L (REG_SCL_DMA0_BASE + 0x36) ++#define REG_SCL_DMA0_1B_H (REG_SCL_DMA0_BASE + 0x37) ++#define REG_SCL_DMA0_1C_L (REG_SCL_DMA0_BASE + 0x38) ++#define REG_SCL_DMA0_1C_H (REG_SCL_DMA0_BASE + 0x39) ++#define REG_SCL_DMA0_1D_L (REG_SCL_DMA0_BASE + 0x3A) ++#define REG_SCL_DMA0_1D_H (REG_SCL_DMA0_BASE + 0x3B) ++#define REG_SCL_DMA0_1E_L (REG_SCL_DMA0_BASE + 0x3C) ++#define REG_SCL_DMA0_1E_H (REG_SCL_DMA0_BASE + 0x3D) ++#define REG_SCL_DMA0_1F_L (REG_SCL_DMA0_BASE + 0x3E) ++#define REG_SCL_DMA0_1F_H (REG_SCL_DMA0_BASE + 0x3F) ++#define REG_SCL_DMA0_20_L (REG_SCL_DMA0_BASE + 0x40) ++#define REG_SCL_DMA0_20_H (REG_SCL_DMA0_BASE + 0x41) ++#define REG_SCL_DMA0_21_L (REG_SCL_DMA0_BASE + 0x42) ++#define REG_SCL_DMA0_21_H (REG_SCL_DMA0_BASE + 0x43) ++#define REG_SCL_DMA0_22_L (REG_SCL_DMA0_BASE + 0x44) ++#define REG_SCL_DMA0_22_H (REG_SCL_DMA0_BASE + 0x45) ++#define REG_SCL_DMA0_23_L (REG_SCL_DMA0_BASE + 0x46) ++#define REG_SCL_DMA0_23_H (REG_SCL_DMA0_BASE + 0x47) ++#define REG_SCL_DMA0_24_L (REG_SCL_DMA0_BASE + 0x48) ++#define REG_SCL_DMA0_24_H (REG_SCL_DMA0_BASE + 0x49) ++#define REG_SCL_DMA0_25_L (REG_SCL_DMA0_BASE + 0x4A) ++#define REG_SCL_DMA0_25_H (REG_SCL_DMA0_BASE + 0x4B) ++#define REG_SCL_DMA0_26_L (REG_SCL_DMA0_BASE + 0x4C) ++#define REG_SCL_DMA0_26_H (REG_SCL_DMA0_BASE + 0x4D) ++#define REG_SCL_DMA0_27_L (REG_SCL_DMA0_BASE + 0x4E) ++#define REG_SCL_DMA0_27_H (REG_SCL_DMA0_BASE + 0x4F) ++#define REG_SCL_DMA0_28_L (REG_SCL_DMA0_BASE + 0x50) ++#define REG_SCL_DMA0_28_H (REG_SCL_DMA0_BASE + 0x51) ++#define REG_SCL_DMA0_29_L (REG_SCL_DMA0_BASE + 0x52) ++#define REG_SCL_DMA0_29_H (REG_SCL_DMA0_BASE + 0x53) ++#define REG_SCL_DMA0_2A_L (REG_SCL_DMA0_BASE + 0x54) ++#define REG_SCL_DMA0_2A_H (REG_SCL_DMA0_BASE + 0x55) ++#define REG_SCL_DMA0_2B_L (REG_SCL_DMA0_BASE + 0x56) ++#define REG_SCL_DMA0_2B_H (REG_SCL_DMA0_BASE + 0x57) ++#define REG_SCL_DMA0_2C_L (REG_SCL_DMA0_BASE + 0x58) ++#define REG_SCL_DMA0_2C_H (REG_SCL_DMA0_BASE + 0x59) ++#define REG_SCL_DMA0_2D_L (REG_SCL_DMA0_BASE + 0x5A) ++#define REG_SCL_DMA0_2D_H (REG_SCL_DMA0_BASE + 0x5B) ++#define REG_SCL_DMA0_2E_L (REG_SCL_DMA0_BASE + 0x5C) ++#define REG_SCL_DMA0_2E_H (REG_SCL_DMA0_BASE + 0x5D) ++#define REG_SCL_DMA0_2F_L (REG_SCL_DMA0_BASE + 0x5E) ++#define REG_SCL_DMA0_2F_H (REG_SCL_DMA0_BASE + 0x5F) ++#define REG_SCL_DMA0_30_L (REG_SCL_DMA0_BASE + 0x60) ++#define REG_SCL_DMA0_30_H (REG_SCL_DMA0_BASE + 0x61) ++#define REG_SCL_DMA0_31_L (REG_SCL_DMA0_BASE + 0x62) ++#define REG_SCL_DMA0_31_H (REG_SCL_DMA0_BASE + 0x63) ++#define REG_SCL_DMA0_32_L (REG_SCL_DMA0_BASE + 0x64) ++#define REG_SCL_DMA0_32_H (REG_SCL_DMA0_BASE + 0x65) ++#define REG_SCL_DMA0_33_L (REG_SCL_DMA0_BASE + 0x66) ++#define REG_SCL_DMA0_33_H (REG_SCL_DMA0_BASE + 0x67) ++#define REG_SCL_DMA0_34_L (REG_SCL_DMA0_BASE + 0x68) ++#define REG_SCL_DMA0_34_H (REG_SCL_DMA0_BASE + 0x69) ++#define REG_SCL_DMA0_35_L (REG_SCL_DMA0_BASE + 0x6A) ++#define REG_SCL_DMA0_35_H (REG_SCL_DMA0_BASE + 0x6B) ++#define REG_SCL_DMA0_36_L (REG_SCL_DMA0_BASE + 0x6C) ++#define REG_SCL_DMA0_36_H (REG_SCL_DMA0_BASE + 0x6D) ++#define REG_SCL_DMA0_37_L (REG_SCL_DMA0_BASE + 0x6E) ++#define REG_SCL_DMA0_37_H (REG_SCL_DMA0_BASE + 0x6F) ++#define REG_SCL_DMA0_38_L (REG_SCL_DMA0_BASE + 0x70) ++#define REG_SCL_DMA0_38_H (REG_SCL_DMA0_BASE + 0x71) ++#define REG_SCL_DMA0_39_L (REG_SCL_DMA0_BASE + 0x72) ++#define REG_SCL_DMA0_39_H (REG_SCL_DMA0_BASE + 0x73) ++#define REG_SCL_DMA0_3A_L (REG_SCL_DMA0_BASE + 0x74) ++#define REG_SCL_DMA0_3A_H (REG_SCL_DMA0_BASE + 0x75) ++#define REG_SCL_DMA0_3B_L (REG_SCL_DMA0_BASE + 0x76) ++#define REG_SCL_DMA0_3B_H (REG_SCL_DMA0_BASE + 0x77) ++#define REG_SCL_DMA0_3C_L (REG_SCL_DMA0_BASE + 0x78) ++#define REG_SCL_DMA0_3C_H (REG_SCL_DMA0_BASE + 0x79) ++#define REG_SCL_DMA0_3D_L (REG_SCL_DMA0_BASE + 0x7A) ++#define REG_SCL_DMA0_3D_H (REG_SCL_DMA0_BASE + 0x7B) ++#define REG_SCL_DMA0_3E_L (REG_SCL_DMA0_BASE + 0x7C) ++#define REG_SCL_DMA0_3E_H (REG_SCL_DMA0_BASE + 0x7D) ++#define REG_SCL_DMA0_3F_L (REG_SCL_DMA0_BASE + 0x7E) ++#define REG_SCL_DMA0_3F_H (REG_SCL_DMA0_BASE + 0x7F) ++#define REG_SCL_DMA0_40_L (REG_SCL_DMA0_BASE + 0x80) ++#define REG_SCL_DMA0_40_H (REG_SCL_DMA0_BASE + 0x81) ++#define REG_SCL_DMA0_41_L (REG_SCL_DMA0_BASE + 0x82) ++#define REG_SCL_DMA0_41_H (REG_SCL_DMA0_BASE + 0x83) ++#define REG_SCL_DMA0_42_L (REG_SCL_DMA0_BASE + 0x84) ++#define REG_SCL_DMA0_42_H (REG_SCL_DMA0_BASE + 0x85) ++#define REG_SCL_DMA0_43_L (REG_SCL_DMA0_BASE + 0x86) ++#define REG_SCL_DMA0_43_H (REG_SCL_DMA0_BASE + 0x87) ++#define REG_SCL_DMA0_44_L (REG_SCL_DMA0_BASE + 0x88) ++#define REG_SCL_DMA0_44_H (REG_SCL_DMA0_BASE + 0x89) ++#define REG_SCL_DMA0_45_L (REG_SCL_DMA0_BASE + 0x8A) ++#define REG_SCL_DMA0_45_H (REG_SCL_DMA0_BASE + 0x8B) ++#define REG_SCL_DMA0_46_L (REG_SCL_DMA0_BASE + 0x8C) ++#define REG_SCL_DMA0_46_H (REG_SCL_DMA0_BASE + 0x8D) ++#define REG_SCL_DMA0_47_L (REG_SCL_DMA0_BASE + 0x8E) ++#define REG_SCL_DMA0_47_H (REG_SCL_DMA0_BASE + 0x8F) ++#define REG_SCL_DMA0_48_L (REG_SCL_DMA0_BASE + 0x90) ++#define REG_SCL_DMA0_48_H (REG_SCL_DMA0_BASE + 0x91) ++#define REG_SCL_DMA0_49_L (REG_SCL_DMA0_BASE + 0x92) ++#define REG_SCL_DMA0_49_H (REG_SCL_DMA0_BASE + 0x93) ++#define REG_SCL_DMA0_4A_L (REG_SCL_DMA0_BASE + 0x94) ++#define REG_SCL_DMA0_4A_H (REG_SCL_DMA0_BASE + 0x95) ++#define REG_SCL_DMA0_4B_L (REG_SCL_DMA0_BASE + 0x96) ++#define REG_SCL_DMA0_4B_H (REG_SCL_DMA0_BASE + 0x97) ++#define REG_SCL_DMA0_4C_L (REG_SCL_DMA0_BASE + 0x98) ++#define REG_SCL_DMA0_4C_H (REG_SCL_DMA0_BASE + 0x99) ++#define REG_SCL_DMA0_4D_L (REG_SCL_DMA0_BASE + 0x9A) ++#define REG_SCL_DMA0_4D_H (REG_SCL_DMA0_BASE + 0x9B) ++#define REG_SCL_DMA0_4E_L (REG_SCL_DMA0_BASE + 0x9C) ++#define REG_SCL_DMA0_4E_H (REG_SCL_DMA0_BASE + 0x9D) ++#define REG_SCL_DMA0_4F_L (REG_SCL_DMA0_BASE + 0x9E) ++#define REG_SCL_DMA0_4F_H (REG_SCL_DMA0_BASE + 0x9F) ++#define REG_SCL_DMA0_50_L (REG_SCL_DMA0_BASE + 0xA0) ++#define REG_SCL_DMA0_50_H (REG_SCL_DMA0_BASE + 0xA1) ++#define REG_SCL_DMA0_51_L (REG_SCL_DMA0_BASE + 0xA2) ++#define REG_SCL_DMA0_51_H (REG_SCL_DMA0_BASE + 0xA3) ++#define REG_SCL_DMA0_52_L (REG_SCL_DMA0_BASE + 0xA4) ++#define REG_SCL_DMA0_52_H (REG_SCL_DMA0_BASE + 0xA5) ++#define REG_SCL_DMA0_53_L (REG_SCL_DMA0_BASE + 0xA6) ++#define REG_SCL_DMA0_53_H (REG_SCL_DMA0_BASE + 0xA7) ++#define REG_SCL_DMA0_54_L (REG_SCL_DMA0_BASE + 0xA8) ++#define REG_SCL_DMA0_54_H (REG_SCL_DMA0_BASE + 0xA9) ++#define REG_SCL_DMA0_55_L (REG_SCL_DMA0_BASE + 0xAA) ++#define REG_SCL_DMA0_55_H (REG_SCL_DMA0_BASE + 0xAB) ++#define REG_SCL_DMA0_56_L (REG_SCL_DMA0_BASE + 0xAC) ++#define REG_SCL_DMA0_56_H (REG_SCL_DMA0_BASE + 0xAD) ++#define REG_SCL_DMA0_57_L (REG_SCL_DMA0_BASE + 0xAE) ++#define REG_SCL_DMA0_57_H (REG_SCL_DMA0_BASE + 0xAF) ++#define REG_SCL_DMA0_58_L (REG_SCL_DMA0_BASE + 0xB0) ++#define REG_SCL_DMA0_58_H (REG_SCL_DMA0_BASE + 0xB1) ++#define REG_SCL_DMA0_59_L (REG_SCL_DMA0_BASE + 0xB2) ++#define REG_SCL_DMA0_59_H (REG_SCL_DMA0_BASE + 0xB3) ++#define REG_SCL_DMA0_5A_L (REG_SCL_DMA0_BASE + 0xB4) ++#define REG_SCL_DMA0_5A_H (REG_SCL_DMA0_BASE + 0xB5) ++#define REG_SCL_DMA0_5B_L (REG_SCL_DMA0_BASE + 0xB6) ++#define REG_SCL_DMA0_5B_H (REG_SCL_DMA0_BASE + 0xB7) ++#define REG_SCL_DMA0_5C_L (REG_SCL_DMA0_BASE + 0xB8) ++#define REG_SCL_DMA0_5C_H (REG_SCL_DMA0_BASE + 0xB9) ++#define REG_SCL_DMA0_5D_L (REG_SCL_DMA0_BASE + 0xBA) ++#define REG_SCL_DMA0_5D_H (REG_SCL_DMA0_BASE + 0xBB) ++#define REG_SCL_DMA0_5E_L (REG_SCL_DMA0_BASE + 0xBC) ++#define REG_SCL_DMA0_5E_H (REG_SCL_DMA0_BASE + 0xBD) ++#define REG_SCL_DMA0_5F_L (REG_SCL_DMA0_BASE + 0xBE) ++#define REG_SCL_DMA0_5F_H (REG_SCL_DMA0_BASE + 0xBF) ++#define REG_SCL_DMA0_60_L (REG_SCL_DMA0_BASE + 0xC0) ++#define REG_SCL_DMA0_60_H (REG_SCL_DMA0_BASE + 0xC1) ++#define REG_SCL_DMA0_61_L (REG_SCL_DMA0_BASE + 0xC2) ++#define REG_SCL_DMA0_61_H (REG_SCL_DMA0_BASE + 0xC3) ++#define REG_SCL_DMA0_62_L (REG_SCL_DMA0_BASE + 0xC4) ++#define REG_SCL_DMA0_62_H (REG_SCL_DMA0_BASE + 0xC5) ++#define REG_SCL_DMA0_63_L (REG_SCL_DMA0_BASE + 0xC6) ++#define REG_SCL_DMA0_63_H (REG_SCL_DMA0_BASE + 0xC7) ++#define REG_SCL_DMA0_64_L (REG_SCL_DMA0_BASE + 0xC8) ++#define REG_SCL_DMA0_64_H (REG_SCL_DMA0_BASE + 0xC9) ++#define REG_SCL_DMA0_65_L (REG_SCL_DMA0_BASE + 0xCA) ++#define REG_SCL_DMA0_65_H (REG_SCL_DMA0_BASE + 0xCB) ++#define REG_SCL_DMA0_66_L (REG_SCL_DMA0_BASE + 0xCC) ++#define REG_SCL_DMA0_66_H (REG_SCL_DMA0_BASE + 0xCD) ++#define REG_SCL_DMA0_67_L (REG_SCL_DMA0_BASE + 0xCE) ++#define REG_SCL_DMA0_67_H (REG_SCL_DMA0_BASE + 0xCF) ++#define REG_SCL_DMA0_68_L (REG_SCL_DMA0_BASE + 0xD0) ++#define REG_SCL_DMA0_68_H (REG_SCL_DMA0_BASE + 0xD1) ++#define REG_SCL_DMA0_69_L (REG_SCL_DMA0_BASE + 0xD2) ++#define REG_SCL_DMA0_69_H (REG_SCL_DMA0_BASE + 0xD3) ++#define REG_SCL_DMA0_6A_L (REG_SCL_DMA0_BASE + 0xD4) ++#define REG_SCL_DMA0_6A_H (REG_SCL_DMA0_BASE + 0xD5) ++#define REG_SCL_DMA0_6B_L (REG_SCL_DMA0_BASE + 0xD6) ++#define REG_SCL_DMA0_6B_H (REG_SCL_DMA0_BASE + 0xD7) ++#define REG_SCL_DMA0_6C_L (REG_SCL_DMA0_BASE + 0xD8) ++#define REG_SCL_DMA0_6C_H (REG_SCL_DMA0_BASE + 0xD9) ++#define REG_SCL_DMA0_6D_L (REG_SCL_DMA0_BASE + 0xDA) ++#define REG_SCL_DMA0_6D_H (REG_SCL_DMA0_BASE + 0xDB) ++#define REG_SCL_DMA0_6E_L (REG_SCL_DMA0_BASE + 0xDC) ++#define REG_SCL_DMA0_6E_H (REG_SCL_DMA0_BASE + 0xDD) ++#define REG_SCL_DMA0_6F_L (REG_SCL_DMA0_BASE + 0xDE) ++#define REG_SCL_DMA0_6F_H (REG_SCL_DMA0_BASE + 0xDF) ++#define REG_SCL_DMA0_70_L (REG_SCL_DMA0_BASE + 0xE0) ++#define REG_SCL_DMA0_70_H (REG_SCL_DMA0_BASE + 0xE1) ++#define REG_SCL_DMA0_71_L (REG_SCL_DMA0_BASE + 0xE2) ++#define REG_SCL_DMA0_71_H (REG_SCL_DMA0_BASE + 0xE3) ++#define REG_SCL_DMA0_72_L (REG_SCL_DMA0_BASE + 0xE4) ++#define REG_SCL_DMA0_72_H (REG_SCL_DMA0_BASE + 0xE5) ++#define REG_SCL_DMA0_73_L (REG_SCL_DMA0_BASE + 0xE6) ++#define REG_SCL_DMA0_73_H (REG_SCL_DMA0_BASE + 0xE7) ++#define REG_SCL_DMA0_74_L (REG_SCL_DMA0_BASE + 0xE8) ++#define REG_SCL_DMA0_74_H (REG_SCL_DMA0_BASE + 0xE9) ++#define REG_SCL_DMA0_75_L (REG_SCL_DMA0_BASE + 0xEA) ++#define REG_SCL_DMA0_75_H (REG_SCL_DMA0_BASE + 0xEB) ++#define REG_SCL_DMA0_76_L (REG_SCL_DMA0_BASE + 0xEC) ++#define REG_SCL_DMA0_76_H (REG_SCL_DMA0_BASE + 0xED) ++#define REG_SCL_DMA0_77_L (REG_SCL_DMA0_BASE + 0xEE) ++#define REG_SCL_DMA0_77_H (REG_SCL_DMA0_BASE + 0xEF) ++#define REG_SCL_DMA0_78_L (REG_SCL_DMA0_BASE + 0xF0) ++#define REG_SCL_DMA0_78_H (REG_SCL_DMA0_BASE + 0xF1) ++#define REG_SCL_DMA0_79_L (REG_SCL_DMA0_BASE + 0xF2) ++#define REG_SCL_DMA0_79_H (REG_SCL_DMA0_BASE + 0xF3) ++#define REG_SCL_DMA0_7A_L (REG_SCL_DMA0_BASE + 0xF4) ++#define REG_SCL_DMA0_7A_H (REG_SCL_DMA0_BASE + 0xF5) ++#define REG_SCL_DMA0_7B_L (REG_SCL_DMA0_BASE + 0xF6) ++#define REG_SCL_DMA0_7B_H (REG_SCL_DMA0_BASE + 0xF7) ++#define REG_SCL_DMA0_7C_L (REG_SCL_DMA0_BASE + 0xF8) ++#define REG_SCL_DMA0_7C_H (REG_SCL_DMA0_BASE + 0xF9) ++#define REG_SCL_DMA0_7D_L (REG_SCL_DMA0_BASE + 0xFA) ++#define REG_SCL_DMA0_7D_H (REG_SCL_DMA0_BASE + 0xFB) ++#define REG_SCL_DMA0_7E_L (REG_SCL_DMA0_BASE + 0xFC) ++#define REG_SCL_DMA0_7E_H (REG_SCL_DMA0_BASE + 0xFD) ++#define REG_SCL_DMA0_7F_L (REG_SCL_DMA0_BASE + 0xFE) ++#define REG_SCL_DMA0_7F_H (REG_SCL_DMA0_BASE + 0xFF) ++ ++#define REG_SCL_DMA1_00_L (REG_SCL_DMA1_BASE + 0x00) ++#define REG_SCL_DMA1_00_H (REG_SCL_DMA1_BASE + 0x01) ++#define REG_SCL_DMA1_01_L (REG_SCL_DMA1_BASE + 0x02) ++#define REG_SCL_DMA1_01_H (REG_SCL_DMA1_BASE + 0x03) ++#define REG_SCL_DMA1_02_L (REG_SCL_DMA1_BASE + 0x04) ++#define REG_SCL_DMA1_02_H (REG_SCL_DMA1_BASE + 0x05) ++#define REG_SCL_DMA1_03_L (REG_SCL_DMA1_BASE + 0x06) ++#define REG_SCL_DMA1_03_H (REG_SCL_DMA1_BASE + 0x07) ++#define REG_SCL_DMA1_04_L (REG_SCL_DMA1_BASE + 0x08) ++#define REG_SCL_DMA1_04_H (REG_SCL_DMA1_BASE + 0x09) ++#define REG_SCL_DMA1_05_L (REG_SCL_DMA1_BASE + 0x0A) ++#define REG_SCL_DMA1_05_H (REG_SCL_DMA1_BASE + 0x0B) ++#define REG_SCL_DMA1_06_L (REG_SCL_DMA1_BASE + 0x0C) ++#define REG_SCL_DMA1_06_H (REG_SCL_DMA1_BASE + 0x0D) ++#define REG_SCL_DMA1_07_L (REG_SCL_DMA1_BASE + 0x0E) ++#define REG_SCL_DMA1_07_H (REG_SCL_DMA1_BASE + 0x0F) ++#define REG_SCL_DMA1_08_L (REG_SCL_DMA1_BASE + 0x10) ++#define REG_SCL_DMA1_08_H (REG_SCL_DMA1_BASE + 0x11) ++#define REG_SCL_DMA1_09_L (REG_SCL_DMA1_BASE + 0x12) ++#define REG_SCL_DMA1_09_H (REG_SCL_DMA1_BASE + 0x13) ++#define REG_SCL_DMA1_0A_L (REG_SCL_DMA1_BASE + 0x14) ++#define REG_SCL_DMA1_0A_H (REG_SCL_DMA1_BASE + 0x15) ++#define REG_SCL_DMA1_0B_L (REG_SCL_DMA1_BASE + 0x16) ++#define REG_SCL_DMA1_0B_H (REG_SCL_DMA1_BASE + 0x17) ++#define REG_SCL_DMA1_0C_L (REG_SCL_DMA1_BASE + 0x18) ++#define REG_SCL_DMA1_0C_H (REG_SCL_DMA1_BASE + 0x19) ++#define REG_SCL_DMA1_0D_L (REG_SCL_DMA1_BASE + 0x1A) ++#define REG_SCL_DMA1_0D_H (REG_SCL_DMA1_BASE + 0x1B) ++#define REG_SCL_DMA1_0E_L (REG_SCL_DMA1_BASE + 0x1C) ++#define REG_SCL_DMA1_0E_H (REG_SCL_DMA1_BASE + 0x1D) ++#define REG_SCL_DMA1_0F_L (REG_SCL_DMA1_BASE + 0x1E) ++#define REG_SCL_DMA1_0F_H (REG_SCL_DMA1_BASE + 0x1F) ++#define REG_SCL_DMA1_10_L (REG_SCL_DMA1_BASE + 0x20) ++#define REG_SCL_DMA1_10_H (REG_SCL_DMA1_BASE + 0x21) ++#define REG_SCL_DMA1_11_L (REG_SCL_DMA1_BASE + 0x22) ++#define REG_SCL_DMA1_11_H (REG_SCL_DMA1_BASE + 0x23) ++#define REG_SCL_DMA1_12_L (REG_SCL_DMA1_BASE + 0x24) ++#define REG_SCL_DMA1_12_H (REG_SCL_DMA1_BASE + 0x25) ++#define REG_SCL_DMA1_13_L (REG_SCL_DMA1_BASE + 0x26) ++#define REG_SCL_DMA1_13_H (REG_SCL_DMA1_BASE + 0x27) ++#define REG_SCL_DMA1_14_L (REG_SCL_DMA1_BASE + 0x28) ++#define REG_SCL_DMA1_14_H (REG_SCL_DMA1_BASE + 0x29) ++#define REG_SCL_DMA1_15_L (REG_SCL_DMA1_BASE + 0x2A) ++#define REG_SCL_DMA1_15_H (REG_SCL_DMA1_BASE + 0x2B) ++#define REG_SCL_DMA1_16_L (REG_SCL_DMA1_BASE + 0x2C) ++#define REG_SCL_DMA1_16_H (REG_SCL_DMA1_BASE + 0x2D) ++#define REG_SCL_DMA1_17_L (REG_SCL_DMA1_BASE + 0x2E) ++#define REG_SCL_DMA1_17_H (REG_SCL_DMA1_BASE + 0x2F) ++#define REG_SCL_DMA1_18_L (REG_SCL_DMA1_BASE + 0x30) ++#define REG_SCL_DMA1_18_H (REG_SCL_DMA1_BASE + 0x31) ++#define REG_SCL_DMA1_19_L (REG_SCL_DMA1_BASE + 0x32) ++#define REG_SCL_DMA1_19_H (REG_SCL_DMA1_BASE + 0x33) ++#define REG_SCL_DMA1_1A_L (REG_SCL_DMA1_BASE + 0x34) ++#define REG_SCL_DMA1_1A_H (REG_SCL_DMA1_BASE + 0x35) ++#define REG_SCL_DMA1_1B_L (REG_SCL_DMA1_BASE + 0x36) ++#define REG_SCL_DMA1_1B_H (REG_SCL_DMA1_BASE + 0x37) ++#define REG_SCL_DMA1_1C_L (REG_SCL_DMA1_BASE + 0x38) ++#define REG_SCL_DMA1_1C_H (REG_SCL_DMA1_BASE + 0x39) ++#define REG_SCL_DMA1_1D_L (REG_SCL_DMA1_BASE + 0x3A) ++#define REG_SCL_DMA1_1D_H (REG_SCL_DMA1_BASE + 0x3B) ++#define REG_SCL_DMA1_1E_L (REG_SCL_DMA1_BASE + 0x3C) ++#define REG_SCL_DMA1_1E_H (REG_SCL_DMA1_BASE + 0x3D) ++#define REG_SCL_DMA1_1F_L (REG_SCL_DMA1_BASE + 0x3E) ++#define REG_SCL_DMA1_1F_H (REG_SCL_DMA1_BASE + 0x3F) ++#define REG_SCL_DMA1_20_L (REG_SCL_DMA1_BASE + 0x40) ++#define REG_SCL_DMA1_20_H (REG_SCL_DMA1_BASE + 0x41) ++#define REG_SCL_DMA1_21_L (REG_SCL_DMA1_BASE + 0x42) ++#define REG_SCL_DMA1_21_H (REG_SCL_DMA1_BASE + 0x43) ++#define REG_SCL_DMA1_22_L (REG_SCL_DMA1_BASE + 0x44) ++#define REG_SCL_DMA1_22_H (REG_SCL_DMA1_BASE + 0x45) ++#define REG_SCL_DMA1_23_L (REG_SCL_DMA1_BASE + 0x46) ++#define REG_SCL_DMA1_23_H (REG_SCL_DMA1_BASE + 0x47) ++#define REG_SCL_DMA1_24_L (REG_SCL_DMA1_BASE + 0x48) ++#define REG_SCL_DMA1_24_H (REG_SCL_DMA1_BASE + 0x49) ++#define REG_SCL_DMA1_25_L (REG_SCL_DMA1_BASE + 0x4A) ++#define REG_SCL_DMA1_25_H (REG_SCL_DMA1_BASE + 0x4B) ++#define REG_SCL_DMA1_26_L (REG_SCL_DMA1_BASE + 0x4C) ++#define REG_SCL_DMA1_26_H (REG_SCL_DMA1_BASE + 0x4D) ++#define REG_SCL_DMA1_27_L (REG_SCL_DMA1_BASE + 0x4E) ++#define REG_SCL_DMA1_27_H (REG_SCL_DMA1_BASE + 0x4F) ++#define REG_SCL_DMA1_28_L (REG_SCL_DMA1_BASE + 0x50) ++#define REG_SCL_DMA1_28_H (REG_SCL_DMA1_BASE + 0x51) ++#define REG_SCL_DMA1_29_L (REG_SCL_DMA1_BASE + 0x52) ++#define REG_SCL_DMA1_29_H (REG_SCL_DMA1_BASE + 0x53) ++#define REG_SCL_DMA1_2A_L (REG_SCL_DMA1_BASE + 0x54) ++#define REG_SCL_DMA1_2A_H (REG_SCL_DMA1_BASE + 0x55) ++#define REG_SCL_DMA1_2B_L (REG_SCL_DMA1_BASE + 0x56) ++#define REG_SCL_DMA1_2B_H (REG_SCL_DMA1_BASE + 0x57) ++#define REG_SCL_DMA1_2C_L (REG_SCL_DMA1_BASE + 0x58) ++#define REG_SCL_DMA1_2C_H (REG_SCL_DMA1_BASE + 0x59) ++#define REG_SCL_DMA1_2D_L (REG_SCL_DMA1_BASE + 0x5A) ++#define REG_SCL_DMA1_2D_H (REG_SCL_DMA1_BASE + 0x5B) ++#define REG_SCL_DMA1_2E_L (REG_SCL_DMA1_BASE + 0x5C) ++#define REG_SCL_DMA1_2E_H (REG_SCL_DMA1_BASE + 0x5D) ++#define REG_SCL_DMA1_2F_L (REG_SCL_DMA1_BASE + 0x5E) ++#define REG_SCL_DMA1_2F_H (REG_SCL_DMA1_BASE + 0x5F) ++#define REG_SCL_DMA1_30_L (REG_SCL_DMA1_BASE + 0x60) ++#define REG_SCL_DMA1_30_H (REG_SCL_DMA1_BASE + 0x61) ++#define REG_SCL_DMA1_31_L (REG_SCL_DMA1_BASE + 0x62) ++#define REG_SCL_DMA1_31_H (REG_SCL_DMA1_BASE + 0x63) ++#define REG_SCL_DMA1_32_L (REG_SCL_DMA1_BASE + 0x64) ++#define REG_SCL_DMA1_32_H (REG_SCL_DMA1_BASE + 0x65) ++#define REG_SCL_DMA1_33_L (REG_SCL_DMA1_BASE + 0x66) ++#define REG_SCL_DMA1_33_H (REG_SCL_DMA1_BASE + 0x67) ++#define REG_SCL_DMA1_34_L (REG_SCL_DMA1_BASE + 0x68) ++#define REG_SCL_DMA1_34_H (REG_SCL_DMA1_BASE + 0x69) ++#define REG_SCL_DMA1_35_L (REG_SCL_DMA1_BASE + 0x6A) ++#define REG_SCL_DMA1_35_H (REG_SCL_DMA1_BASE + 0x6B) ++#define REG_SCL_DMA1_36_L (REG_SCL_DMA1_BASE + 0x6C) ++#define REG_SCL_DMA1_36_H (REG_SCL_DMA1_BASE + 0x6D) ++#define REG_SCL_DMA1_37_L (REG_SCL_DMA1_BASE + 0x6E) ++#define REG_SCL_DMA1_37_H (REG_SCL_DMA1_BASE + 0x6F) ++#define REG_SCL_DMA1_38_L (REG_SCL_DMA1_BASE + 0x70) ++#define REG_SCL_DMA1_38_H (REG_SCL_DMA1_BASE + 0x71) ++#define REG_SCL_DMA1_39_L (REG_SCL_DMA1_BASE + 0x72) ++#define REG_SCL_DMA1_39_H (REG_SCL_DMA1_BASE + 0x73) ++#define REG_SCL_DMA1_3A_L (REG_SCL_DMA1_BASE + 0x74) ++#define REG_SCL_DMA1_3A_H (REG_SCL_DMA1_BASE + 0x75) ++#define REG_SCL_DMA1_3B_L (REG_SCL_DMA1_BASE + 0x76) ++#define REG_SCL_DMA1_3B_H (REG_SCL_DMA1_BASE + 0x77) ++#define REG_SCL_DMA1_3C_L (REG_SCL_DMA1_BASE + 0x78) ++#define REG_SCL_DMA1_3C_H (REG_SCL_DMA1_BASE + 0x79) ++#define REG_SCL_DMA1_3D_L (REG_SCL_DMA1_BASE + 0x7A) ++#define REG_SCL_DMA1_3D_H (REG_SCL_DMA1_BASE + 0x7B) ++#define REG_SCL_DMA1_3E_L (REG_SCL_DMA1_BASE + 0x7C) ++#define REG_SCL_DMA1_3E_H (REG_SCL_DMA1_BASE + 0x7D) ++#define REG_SCL_DMA1_3F_L (REG_SCL_DMA1_BASE + 0x7E) ++#define REG_SCL_DMA1_3F_H (REG_SCL_DMA1_BASE + 0x7F) ++#define REG_SCL_DMA1_40_L (REG_SCL_DMA1_BASE + 0x80) ++#define REG_SCL_DMA1_40_H (REG_SCL_DMA1_BASE + 0x81) ++#define REG_SCL_DMA1_41_L (REG_SCL_DMA1_BASE + 0x82) ++#define REG_SCL_DMA1_41_H (REG_SCL_DMA1_BASE + 0x83) ++#define REG_SCL_DMA1_42_L (REG_SCL_DMA1_BASE + 0x84) ++#define REG_SCL_DMA1_42_H (REG_SCL_DMA1_BASE + 0x85) ++#define REG_SCL_DMA1_43_L (REG_SCL_DMA1_BASE + 0x86) ++#define REG_SCL_DMA1_43_H (REG_SCL_DMA1_BASE + 0x87) ++#define REG_SCL_DMA1_44_L (REG_SCL_DMA1_BASE + 0x88) ++#define REG_SCL_DMA1_44_H (REG_SCL_DMA1_BASE + 0x89) ++#define REG_SCL_DMA1_45_L (REG_SCL_DMA1_BASE + 0x8A) ++#define REG_SCL_DMA1_45_H (REG_SCL_DMA1_BASE + 0x8B) ++#define REG_SCL_DMA1_46_L (REG_SCL_DMA1_BASE + 0x8C) ++#define REG_SCL_DMA1_46_H (REG_SCL_DMA1_BASE + 0x8D) ++#define REG_SCL_DMA1_47_L (REG_SCL_DMA1_BASE + 0x8E) ++#define REG_SCL_DMA1_47_H (REG_SCL_DMA1_BASE + 0x8F) ++#define REG_SCL_DMA1_48_L (REG_SCL_DMA1_BASE + 0x90) ++#define REG_SCL_DMA1_48_H (REG_SCL_DMA1_BASE + 0x91) ++#define REG_SCL_DMA1_49_L (REG_SCL_DMA1_BASE + 0x92) ++#define REG_SCL_DMA1_49_H (REG_SCL_DMA1_BASE + 0x93) ++#define REG_SCL_DMA1_4A_L (REG_SCL_DMA1_BASE + 0x94) ++#define REG_SCL_DMA1_4A_H (REG_SCL_DMA1_BASE + 0x95) ++#define REG_SCL_DMA1_4B_L (REG_SCL_DMA1_BASE + 0x96) ++#define REG_SCL_DMA1_4B_H (REG_SCL_DMA1_BASE + 0x97) ++#define REG_SCL_DMA1_4C_L (REG_SCL_DMA1_BASE + 0x98) ++#define REG_SCL_DMA1_4C_H (REG_SCL_DMA1_BASE + 0x99) ++#define REG_SCL_DMA1_4D_L (REG_SCL_DMA1_BASE + 0x9A) ++#define REG_SCL_DMA1_4D_H (REG_SCL_DMA1_BASE + 0x9B) ++#define REG_SCL_DMA1_4E_L (REG_SCL_DMA1_BASE + 0x9C) ++#define REG_SCL_DMA1_4E_H (REG_SCL_DMA1_BASE + 0x9D) ++#define REG_SCL_DMA1_4F_L (REG_SCL_DMA1_BASE + 0x9E) ++#define REG_SCL_DMA1_4F_H (REG_SCL_DMA1_BASE + 0x9F) ++#define REG_SCL_DMA1_50_L (REG_SCL_DMA1_BASE + 0xA0) ++#define REG_SCL_DMA1_50_H (REG_SCL_DMA1_BASE + 0xA1) ++#define REG_SCL_DMA1_51_L (REG_SCL_DMA1_BASE + 0xA2) ++#define REG_SCL_DMA1_51_H (REG_SCL_DMA1_BASE + 0xA3) ++#define REG_SCL_DMA1_52_L (REG_SCL_DMA1_BASE + 0xA4) ++#define REG_SCL_DMA1_52_H (REG_SCL_DMA1_BASE + 0xA5) ++#define REG_SCL_DMA1_53_L (REG_SCL_DMA1_BASE + 0xA6) ++#define REG_SCL_DMA1_53_H (REG_SCL_DMA1_BASE + 0xA7) ++#define REG_SCL_DMA1_54_L (REG_SCL_DMA1_BASE + 0xA8) ++#define REG_SCL_DMA1_54_H (REG_SCL_DMA1_BASE + 0xA9) ++#define REG_SCL_DMA1_55_L (REG_SCL_DMA1_BASE + 0xAA) ++#define REG_SCL_DMA1_55_H (REG_SCL_DMA1_BASE + 0xAB) ++#define REG_SCL_DMA1_56_L (REG_SCL_DMA1_BASE + 0xAC) ++#define REG_SCL_DMA1_56_H (REG_SCL_DMA1_BASE + 0xAD) ++#define REG_SCL_DMA1_57_L (REG_SCL_DMA1_BASE + 0xAE) ++#define REG_SCL_DMA1_57_H (REG_SCL_DMA1_BASE + 0xAF) ++#define REG_SCL_DMA1_58_L (REG_SCL_DMA1_BASE + 0xB0) ++#define REG_SCL_DMA1_58_H (REG_SCL_DMA1_BASE + 0xB1) ++#define REG_SCL_DMA1_59_L (REG_SCL_DMA1_BASE + 0xB2) ++#define REG_SCL_DMA1_59_H (REG_SCL_DMA1_BASE + 0xB3) ++#define REG_SCL_DMA1_5A_L (REG_SCL_DMA1_BASE + 0xB4) ++#define REG_SCL_DMA1_5A_H (REG_SCL_DMA1_BASE + 0xB5) ++#define REG_SCL_DMA1_5B_L (REG_SCL_DMA1_BASE + 0xB6) ++#define REG_SCL_DMA1_5B_H (REG_SCL_DMA1_BASE + 0xB7) ++#define REG_SCL_DMA1_5C_L (REG_SCL_DMA1_BASE + 0xB8) ++#define REG_SCL_DMA1_5C_H (REG_SCL_DMA1_BASE + 0xB9) ++#define REG_SCL_DMA1_5D_L (REG_SCL_DMA1_BASE + 0xBA) ++#define REG_SCL_DMA1_5D_H (REG_SCL_DMA1_BASE + 0xBB) ++#define REG_SCL_DMA1_5E_L (REG_SCL_DMA1_BASE + 0xBC) ++#define REG_SCL_DMA1_5E_H (REG_SCL_DMA1_BASE + 0xBD) ++#define REG_SCL_DMA1_5F_L (REG_SCL_DMA1_BASE + 0xBE) ++#define REG_SCL_DMA1_5F_H (REG_SCL_DMA1_BASE + 0xBF) ++#define REG_SCL_DMA1_60_L (REG_SCL_DMA1_BASE + 0xC0) ++#define REG_SCL_DMA1_60_H (REG_SCL_DMA1_BASE + 0xC1) ++#define REG_SCL_DMA1_61_L (REG_SCL_DMA1_BASE + 0xC2) ++#define REG_SCL_DMA1_61_H (REG_SCL_DMA1_BASE + 0xC3) ++#define REG_SCL_DMA1_62_L (REG_SCL_DMA1_BASE + 0xC4) ++#define REG_SCL_DMA1_62_H (REG_SCL_DMA1_BASE + 0xC5) ++#define REG_SCL_DMA1_63_L (REG_SCL_DMA1_BASE + 0xC6) ++#define REG_SCL_DMA1_63_H (REG_SCL_DMA1_BASE + 0xC7) ++#define REG_SCL_DMA1_64_L (REG_SCL_DMA1_BASE + 0xC8) ++#define REG_SCL_DMA1_64_H (REG_SCL_DMA1_BASE + 0xC9) ++#define REG_SCL_DMA1_65_L (REG_SCL_DMA1_BASE + 0xCA) ++#define REG_SCL_DMA1_65_H (REG_SCL_DMA1_BASE + 0xCB) ++#define REG_SCL_DMA1_66_L (REG_SCL_DMA1_BASE + 0xCC) ++#define REG_SCL_DMA1_66_H (REG_SCL_DMA1_BASE + 0xCD) ++#define REG_SCL_DMA1_67_L (REG_SCL_DMA1_BASE + 0xCE) ++#define REG_SCL_DMA1_67_H (REG_SCL_DMA1_BASE + 0xCF) ++#define REG_SCL_DMA1_68_L (REG_SCL_DMA1_BASE + 0xD0) ++#define REG_SCL_DMA1_68_H (REG_SCL_DMA1_BASE + 0xD1) ++#define REG_SCL_DMA1_69_L (REG_SCL_DMA1_BASE + 0xD2) ++#define REG_SCL_DMA1_69_H (REG_SCL_DMA1_BASE + 0xD3) ++#define REG_SCL_DMA1_6A_L (REG_SCL_DMA1_BASE + 0xD4) ++#define REG_SCL_DMA1_6A_H (REG_SCL_DMA1_BASE + 0xD5) ++#define REG_SCL_DMA1_6B_L (REG_SCL_DMA1_BASE + 0xD6) ++#define REG_SCL_DMA1_6B_H (REG_SCL_DMA1_BASE + 0xD7) ++#define REG_SCL_DMA1_6C_L (REG_SCL_DMA1_BASE + 0xD8) ++#define REG_SCL_DMA1_6C_H (REG_SCL_DMA1_BASE + 0xD9) ++#define REG_SCL_DMA1_6D_L (REG_SCL_DMA1_BASE + 0xDA) ++#define REG_SCL_DMA1_6D_H (REG_SCL_DMA1_BASE + 0xDB) ++#define REG_SCL_DMA1_6E_L (REG_SCL_DMA1_BASE + 0xDC) ++#define REG_SCL_DMA1_6E_H (REG_SCL_DMA1_BASE + 0xDD) ++#define REG_SCL_DMA1_6F_L (REG_SCL_DMA1_BASE + 0xDE) ++#define REG_SCL_DMA1_6F_H (REG_SCL_DMA1_BASE + 0xDF) ++#define REG_SCL_DMA1_70_L (REG_SCL_DMA1_BASE + 0xE0) ++#define REG_SCL_DMA1_70_H (REG_SCL_DMA1_BASE + 0xE1) ++#define REG_SCL_DMA1_71_L (REG_SCL_DMA1_BASE + 0xE2) ++#define REG_SCL_DMA1_71_H (REG_SCL_DMA1_BASE + 0xE3) ++#define REG_SCL_DMA1_72_L (REG_SCL_DMA1_BASE + 0xE4) ++#define REG_SCL_DMA1_72_H (REG_SCL_DMA1_BASE + 0xE5) ++#define REG_SCL_DMA1_73_L (REG_SCL_DMA1_BASE + 0xE6) ++#define REG_SCL_DMA1_73_H (REG_SCL_DMA1_BASE + 0xE7) ++#define REG_SCL_DMA1_74_L (REG_SCL_DMA1_BASE + 0xE8) ++#define REG_SCL_DMA1_74_H (REG_SCL_DMA1_BASE + 0xE9) ++#define REG_SCL_DMA1_75_L (REG_SCL_DMA1_BASE + 0xEA) ++#define REG_SCL_DMA1_75_H (REG_SCL_DMA1_BASE + 0xEB) ++#define REG_SCL_DMA1_76_L (REG_SCL_DMA1_BASE + 0xEC) ++#define REG_SCL_DMA1_76_H (REG_SCL_DMA1_BASE + 0xED) ++#define REG_SCL_DMA1_77_L (REG_SCL_DMA1_BASE + 0xEE) ++#define REG_SCL_DMA1_77_H (REG_SCL_DMA1_BASE + 0xEF) ++#define REG_SCL_DMA1_78_L (REG_SCL_DMA1_BASE + 0xF0) ++#define REG_SCL_DMA1_78_H (REG_SCL_DMA1_BASE + 0xF1) ++#define REG_SCL_DMA1_79_L (REG_SCL_DMA1_BASE + 0xF2) ++#define REG_SCL_DMA1_79_H (REG_SCL_DMA1_BASE + 0xF3) ++#define REG_SCL_DMA1_7A_L (REG_SCL_DMA1_BASE + 0xF4) ++#define REG_SCL_DMA1_7A_H (REG_SCL_DMA1_BASE + 0xF5) ++#define REG_SCL_DMA1_7B_L (REG_SCL_DMA1_BASE + 0xF6) ++#define REG_SCL_DMA1_7B_H (REG_SCL_DMA1_BASE + 0xF7) ++#define REG_SCL_DMA1_7C_L (REG_SCL_DMA1_BASE + 0xF8) ++#define REG_SCL_DMA1_7C_H (REG_SCL_DMA1_BASE + 0xF9) ++#define REG_SCL_DMA1_7D_L (REG_SCL_DMA1_BASE + 0xFA) ++#define REG_SCL_DMA1_7D_H (REG_SCL_DMA1_BASE + 0xFB) ++#define REG_SCL_DMA1_7E_L (REG_SCL_DMA1_BASE + 0xFC) ++#define REG_SCL_DMA1_7E_H (REG_SCL_DMA1_BASE + 0xFD) ++#define REG_SCL_DMA1_7F_L (REG_SCL_DMA1_BASE + 0xFE) ++#define REG_SCL_DMA1_7F_H (REG_SCL_DMA1_BASE + 0xFF) ++ ++#define REG_SCL_DMA2_00_L (REG_SCL_DMA2_BASE + 0x00) ++#define REG_SCL_DMA2_00_H (REG_SCL_DMA2_BASE + 0x01) ++#define REG_SCL_DMA2_01_L (REG_SCL_DMA2_BASE + 0x02) ++#define REG_SCL_DMA2_01_H (REG_SCL_DMA2_BASE + 0x03) ++#define REG_SCL_DMA2_02_L (REG_SCL_DMA2_BASE + 0x04) ++#define REG_SCL_DMA2_02_H (REG_SCL_DMA2_BASE + 0x05) ++#define REG_SCL_DMA2_03_L (REG_SCL_DMA2_BASE + 0x06) ++#define REG_SCL_DMA2_03_H (REG_SCL_DMA2_BASE + 0x07) ++#define REG_SCL_DMA2_04_L (REG_SCL_DMA2_BASE + 0x08) ++#define REG_SCL_DMA2_04_H (REG_SCL_DMA2_BASE + 0x09) ++#define REG_SCL_DMA2_05_L (REG_SCL_DMA2_BASE + 0x0A) ++#define REG_SCL_DMA2_05_H (REG_SCL_DMA2_BASE + 0x0B) ++#define REG_SCL_DMA2_06_L (REG_SCL_DMA2_BASE + 0x0C) ++#define REG_SCL_DMA2_06_H (REG_SCL_DMA2_BASE + 0x0D) ++#define REG_SCL_DMA2_07_L (REG_SCL_DMA2_BASE + 0x0E) ++#define REG_SCL_DMA2_07_H (REG_SCL_DMA2_BASE + 0x0F) ++#define REG_SCL_DMA2_08_L (REG_SCL_DMA2_BASE + 0x10) ++#define REG_SCL_DMA2_08_H (REG_SCL_DMA2_BASE + 0x11) ++#define REG_SCL_DMA2_09_L (REG_SCL_DMA2_BASE + 0x12) ++#define REG_SCL_DMA2_09_H (REG_SCL_DMA2_BASE + 0x13) ++#define REG_SCL_DMA2_0A_L (REG_SCL_DMA2_BASE + 0x14) ++#define REG_SCL_DMA2_0A_H (REG_SCL_DMA2_BASE + 0x15) ++#define REG_SCL_DMA2_0B_L (REG_SCL_DMA2_BASE + 0x16) ++#define REG_SCL_DMA2_0B_H (REG_SCL_DMA2_BASE + 0x17) ++#define REG_SCL_DMA2_0C_L (REG_SCL_DMA2_BASE + 0x18) ++#define REG_SCL_DMA2_0C_H (REG_SCL_DMA2_BASE + 0x19) ++#define REG_SCL_DMA2_0D_L (REG_SCL_DMA2_BASE + 0x1A) ++#define REG_SCL_DMA2_0D_H (REG_SCL_DMA2_BASE + 0x1B) ++#define REG_SCL_DMA2_0E_L (REG_SCL_DMA2_BASE + 0x1C) ++#define REG_SCL_DMA2_0E_H (REG_SCL_DMA2_BASE + 0x1D) ++#define REG_SCL_DMA2_0F_L (REG_SCL_DMA2_BASE + 0x1E) ++#define REG_SCL_DMA2_0F_H (REG_SCL_DMA2_BASE + 0x1F) ++#define REG_SCL_DMA2_10_L (REG_SCL_DMA2_BASE + 0x20) ++#define REG_SCL_DMA2_10_H (REG_SCL_DMA2_BASE + 0x21) ++#define REG_SCL_DMA2_11_L (REG_SCL_DMA2_BASE + 0x22) ++#define REG_SCL_DMA2_11_H (REG_SCL_DMA2_BASE + 0x23) ++#define REG_SCL_DMA2_12_L (REG_SCL_DMA2_BASE + 0x24) ++#define REG_SCL_DMA2_12_H (REG_SCL_DMA2_BASE + 0x25) ++#define REG_SCL_DMA2_13_L (REG_SCL_DMA2_BASE + 0x26) ++#define REG_SCL_DMA2_13_H (REG_SCL_DMA2_BASE + 0x27) ++#define REG_SCL_DMA2_14_L (REG_SCL_DMA2_BASE + 0x28) ++#define REG_SCL_DMA2_14_H (REG_SCL_DMA2_BASE + 0x29) ++#define REG_SCL_DMA2_15_L (REG_SCL_DMA2_BASE + 0x2A) ++#define REG_SCL_DMA2_15_H (REG_SCL_DMA2_BASE + 0x2B) ++#define REG_SCL_DMA2_16_L (REG_SCL_DMA2_BASE + 0x2C) ++#define REG_SCL_DMA2_16_H (REG_SCL_DMA2_BASE + 0x2D) ++#define REG_SCL_DMA2_17_L (REG_SCL_DMA2_BASE + 0x2E) ++#define REG_SCL_DMA2_17_H (REG_SCL_DMA2_BASE + 0x2F) ++#define REG_SCL_DMA2_18_L (REG_SCL_DMA2_BASE + 0x30) ++#define REG_SCL_DMA2_18_H (REG_SCL_DMA2_BASE + 0x31) ++#define REG_SCL_DMA2_19_L (REG_SCL_DMA2_BASE + 0x32) ++#define REG_SCL_DMA2_19_H (REG_SCL_DMA2_BASE + 0x33) ++#define REG_SCL_DMA2_1A_L (REG_SCL_DMA2_BASE + 0x34) ++#define REG_SCL_DMA2_1A_H (REG_SCL_DMA2_BASE + 0x35) ++#define REG_SCL_DMA2_1B_L (REG_SCL_DMA2_BASE + 0x36) ++#define REG_SCL_DMA2_1B_H (REG_SCL_DMA2_BASE + 0x37) ++#define REG_SCL_DMA2_1C_L (REG_SCL_DMA2_BASE + 0x38) ++#define REG_SCL_DMA2_1C_H (REG_SCL_DMA2_BASE + 0x39) ++#define REG_SCL_DMA2_1D_L (REG_SCL_DMA2_BASE + 0x3A) ++#define REG_SCL_DMA2_1D_H (REG_SCL_DMA2_BASE + 0x3B) ++#define REG_SCL_DMA2_1E_L (REG_SCL_DMA2_BASE + 0x3C) ++#define REG_SCL_DMA2_1E_H (REG_SCL_DMA2_BASE + 0x3D) ++#define REG_SCL_DMA2_1F_L (REG_SCL_DMA2_BASE + 0x3E) ++#define REG_SCL_DMA2_1F_H (REG_SCL_DMA2_BASE + 0x3F) ++#define REG_SCL_DMA2_20_L (REG_SCL_DMA2_BASE + 0x40) ++#define REG_SCL_DMA2_20_H (REG_SCL_DMA2_BASE + 0x41) ++#define REG_SCL_DMA2_21_L (REG_SCL_DMA2_BASE + 0x42) ++#define REG_SCL_DMA2_21_H (REG_SCL_DMA2_BASE + 0x43) ++#define REG_SCL_DMA2_22_L (REG_SCL_DMA2_BASE + 0x44) ++#define REG_SCL_DMA2_22_H (REG_SCL_DMA2_BASE + 0x45) ++#define REG_SCL_DMA2_23_L (REG_SCL_DMA2_BASE + 0x46) ++#define REG_SCL_DMA2_23_H (REG_SCL_DMA2_BASE + 0x47) ++#define REG_SCL_DMA2_24_L (REG_SCL_DMA2_BASE + 0x48) ++#define REG_SCL_DMA2_24_H (REG_SCL_DMA2_BASE + 0x49) ++#define REG_SCL_DMA2_25_L (REG_SCL_DMA2_BASE + 0x4A) ++#define REG_SCL_DMA2_25_H (REG_SCL_DMA2_BASE + 0x4B) ++#define REG_SCL_DMA2_26_L (REG_SCL_DMA2_BASE + 0x4C) ++#define REG_SCL_DMA2_26_H (REG_SCL_DMA2_BASE + 0x4D) ++#define REG_SCL_DMA2_27_L (REG_SCL_DMA2_BASE + 0x4E) ++#define REG_SCL_DMA2_27_H (REG_SCL_DMA2_BASE + 0x4F) ++#define REG_SCL_DMA2_28_L (REG_SCL_DMA2_BASE + 0x50) ++#define REG_SCL_DMA2_28_H (REG_SCL_DMA2_BASE + 0x51) ++#define REG_SCL_DMA2_29_L (REG_SCL_DMA2_BASE + 0x52) ++#define REG_SCL_DMA2_29_H (REG_SCL_DMA2_BASE + 0x53) ++#define REG_SCL_DMA2_2A_L (REG_SCL_DMA2_BASE + 0x54) ++#define REG_SCL_DMA2_2A_H (REG_SCL_DMA2_BASE + 0x55) ++#define REG_SCL_DMA2_2B_L (REG_SCL_DMA2_BASE + 0x56) ++#define REG_SCL_DMA2_2B_H (REG_SCL_DMA2_BASE + 0x57) ++#define REG_SCL_DMA2_2C_L (REG_SCL_DMA2_BASE + 0x58) ++#define REG_SCL_DMA2_2C_H (REG_SCL_DMA2_BASE + 0x59) ++#define REG_SCL_DMA2_2D_L (REG_SCL_DMA2_BASE + 0x5A) ++#define REG_SCL_DMA2_2D_H (REG_SCL_DMA2_BASE + 0x5B) ++#define REG_SCL_DMA2_2E_L (REG_SCL_DMA2_BASE + 0x5C) ++#define REG_SCL_DMA2_2E_H (REG_SCL_DMA2_BASE + 0x5D) ++#define REG_SCL_DMA2_2F_L (REG_SCL_DMA2_BASE + 0x5E) ++#define REG_SCL_DMA2_2F_H (REG_SCL_DMA2_BASE + 0x5F) ++#define REG_SCL_DMA2_30_L (REG_SCL_DMA2_BASE + 0x60) ++#define REG_SCL_DMA2_30_H (REG_SCL_DMA2_BASE + 0x61) ++#define REG_SCL_DMA2_31_L (REG_SCL_DMA2_BASE + 0x62) ++#define REG_SCL_DMA2_31_H (REG_SCL_DMA2_BASE + 0x63) ++#define REG_SCL_DMA2_32_L (REG_SCL_DMA2_BASE + 0x64) ++#define REG_SCL_DMA2_32_H (REG_SCL_DMA2_BASE + 0x65) ++#define REG_SCL_DMA2_33_L (REG_SCL_DMA2_BASE + 0x66) ++#define REG_SCL_DMA2_33_H (REG_SCL_DMA2_BASE + 0x67) ++#define REG_SCL_DMA2_34_L (REG_SCL_DMA2_BASE + 0x68) ++#define REG_SCL_DMA2_34_H (REG_SCL_DMA2_BASE + 0x69) ++#define REG_SCL_DMA2_35_L (REG_SCL_DMA2_BASE + 0x6A) ++#define REG_SCL_DMA2_35_H (REG_SCL_DMA2_BASE + 0x6B) ++#define REG_SCL_DMA2_36_L (REG_SCL_DMA2_BASE + 0x6C) ++#define REG_SCL_DMA2_36_H (REG_SCL_DMA2_BASE + 0x6D) ++#define REG_SCL_DMA2_37_L (REG_SCL_DMA2_BASE + 0x6E) ++#define REG_SCL_DMA2_37_H (REG_SCL_DMA2_BASE + 0x6F) ++#define REG_SCL_DMA2_38_L (REG_SCL_DMA2_BASE + 0x70) ++#define REG_SCL_DMA2_38_H (REG_SCL_DMA2_BASE + 0x71) ++#define REG_SCL_DMA2_39_L (REG_SCL_DMA2_BASE + 0x72) ++#define REG_SCL_DMA2_39_H (REG_SCL_DMA2_BASE + 0x73) ++#define REG_SCL_DMA2_3A_L (REG_SCL_DMA2_BASE + 0x74) ++#define REG_SCL_DMA2_3A_H (REG_SCL_DMA2_BASE + 0x75) ++#define REG_SCL_DMA2_3B_L (REG_SCL_DMA2_BASE + 0x76) ++#define REG_SCL_DMA2_3B_H (REG_SCL_DMA2_BASE + 0x77) ++#define REG_SCL_DMA2_3C_L (REG_SCL_DMA2_BASE + 0x78) ++#define REG_SCL_DMA2_3C_H (REG_SCL_DMA2_BASE + 0x79) ++#define REG_SCL_DMA2_3D_L (REG_SCL_DMA2_BASE + 0x7A) ++#define REG_SCL_DMA2_3D_H (REG_SCL_DMA2_BASE + 0x7B) ++#define REG_SCL_DMA2_3E_L (REG_SCL_DMA2_BASE + 0x7C) ++#define REG_SCL_DMA2_3E_H (REG_SCL_DMA2_BASE + 0x7D) ++#define REG_SCL_DMA2_3F_L (REG_SCL_DMA2_BASE + 0x7E) ++#define REG_SCL_DMA2_3F_H (REG_SCL_DMA2_BASE + 0x7F) ++#define REG_SCL_DMA2_40_L (REG_SCL_DMA2_BASE + 0x80) ++#define REG_SCL_DMA2_40_H (REG_SCL_DMA2_BASE + 0x81) ++#define REG_SCL_DMA2_41_L (REG_SCL_DMA2_BASE + 0x82) ++#define REG_SCL_DMA2_41_H (REG_SCL_DMA2_BASE + 0x83) ++#define REG_SCL_DMA2_42_L (REG_SCL_DMA2_BASE + 0x84) ++#define REG_SCL_DMA2_42_H (REG_SCL_DMA2_BASE + 0x85) ++#define REG_SCL_DMA2_43_L (REG_SCL_DMA2_BASE + 0x86) ++#define REG_SCL_DMA2_43_H (REG_SCL_DMA2_BASE + 0x87) ++#define REG_SCL_DMA2_44_L (REG_SCL_DMA2_BASE + 0x88) ++#define REG_SCL_DMA2_44_H (REG_SCL_DMA2_BASE + 0x89) ++#define REG_SCL_DMA2_45_L (REG_SCL_DMA2_BASE + 0x8A) ++#define REG_SCL_DMA2_45_H (REG_SCL_DMA2_BASE + 0x8B) ++#define REG_SCL_DMA2_46_L (REG_SCL_DMA2_BASE + 0x8C) ++#define REG_SCL_DMA2_46_H (REG_SCL_DMA2_BASE + 0x8D) ++#define REG_SCL_DMA2_47_L (REG_SCL_DMA2_BASE + 0x8E) ++#define REG_SCL_DMA2_47_H (REG_SCL_DMA2_BASE + 0x8F) ++#define REG_SCL_DMA2_48_L (REG_SCL_DMA2_BASE + 0x90) ++#define REG_SCL_DMA2_48_H (REG_SCL_DMA2_BASE + 0x91) ++#define REG_SCL_DMA2_49_L (REG_SCL_DMA2_BASE + 0x92) ++#define REG_SCL_DMA2_49_H (REG_SCL_DMA2_BASE + 0x93) ++#define REG_SCL_DMA2_4A_L (REG_SCL_DMA2_BASE + 0x94) ++#define REG_SCL_DMA2_4A_H (REG_SCL_DMA2_BASE + 0x95) ++#define REG_SCL_DMA2_4B_L (REG_SCL_DMA2_BASE + 0x96) ++#define REG_SCL_DMA2_4B_H (REG_SCL_DMA2_BASE + 0x97) ++#define REG_SCL_DMA2_4C_L (REG_SCL_DMA2_BASE + 0x98) ++#define REG_SCL_DMA2_4C_H (REG_SCL_DMA2_BASE + 0x99) ++#define REG_SCL_DMA2_4D_L (REG_SCL_DMA2_BASE + 0x9A) ++#define REG_SCL_DMA2_4D_H (REG_SCL_DMA2_BASE + 0x9B) ++#define REG_SCL_DMA2_4E_L (REG_SCL_DMA2_BASE + 0x9C) ++#define REG_SCL_DMA2_4E_H (REG_SCL_DMA2_BASE + 0x9D) ++#define REG_SCL_DMA2_4F_L (REG_SCL_DMA2_BASE + 0x9E) ++#define REG_SCL_DMA2_4F_H (REG_SCL_DMA2_BASE + 0x9F) ++#define REG_SCL_DMA2_50_L (REG_SCL_DMA2_BASE + 0xA0) ++#define REG_SCL_DMA2_50_H (REG_SCL_DMA2_BASE + 0xA1) ++#define REG_SCL_DMA2_51_L (REG_SCL_DMA2_BASE + 0xA2) ++#define REG_SCL_DMA2_51_H (REG_SCL_DMA2_BASE + 0xA3) ++#define REG_SCL_DMA2_52_L (REG_SCL_DMA2_BASE + 0xA4) ++#define REG_SCL_DMA2_52_H (REG_SCL_DMA2_BASE + 0xA5) ++#define REG_SCL_DMA2_53_L (REG_SCL_DMA2_BASE + 0xA6) ++#define REG_SCL_DMA2_53_H (REG_SCL_DMA2_BASE + 0xA7) ++#define REG_SCL_DMA2_54_L (REG_SCL_DMA2_BASE + 0xA8) ++#define REG_SCL_DMA2_54_H (REG_SCL_DMA2_BASE + 0xA9) ++#define REG_SCL_DMA2_55_L (REG_SCL_DMA2_BASE + 0xAA) ++#define REG_SCL_DMA2_55_H (REG_SCL_DMA2_BASE + 0xAB) ++#define REG_SCL_DMA2_56_L (REG_SCL_DMA2_BASE + 0xAC) ++#define REG_SCL_DMA2_56_H (REG_SCL_DMA2_BASE + 0xAD) ++#define REG_SCL_DMA2_57_L (REG_SCL_DMA2_BASE + 0xAE) ++#define REG_SCL_DMA2_57_H (REG_SCL_DMA2_BASE + 0xAF) ++#define REG_SCL_DMA2_58_L (REG_SCL_DMA2_BASE + 0xB0) ++#define REG_SCL_DMA2_58_H (REG_SCL_DMA2_BASE + 0xB1) ++#define REG_SCL_DMA2_59_L (REG_SCL_DMA2_BASE + 0xB2) ++#define REG_SCL_DMA2_59_H (REG_SCL_DMA2_BASE + 0xB3) ++#define REG_SCL_DMA2_5A_L (REG_SCL_DMA2_BASE + 0xB4) ++#define REG_SCL_DMA2_5A_H (REG_SCL_DMA2_BASE + 0xB5) ++#define REG_SCL_DMA2_5B_L (REG_SCL_DMA2_BASE + 0xB6) ++#define REG_SCL_DMA2_5B_H (REG_SCL_DMA2_BASE + 0xB7) ++#define REG_SCL_DMA2_5C_L (REG_SCL_DMA2_BASE + 0xB8) ++#define REG_SCL_DMA2_5C_H (REG_SCL_DMA2_BASE + 0xB9) ++#define REG_SCL_DMA2_5D_L (REG_SCL_DMA2_BASE + 0xBA) ++#define REG_SCL_DMA2_5D_H (REG_SCL_DMA2_BASE + 0xBB) ++#define REG_SCL_DMA2_5E_L (REG_SCL_DMA2_BASE + 0xBC) ++#define REG_SCL_DMA2_5E_H (REG_SCL_DMA2_BASE + 0xBD) ++#define REG_SCL_DMA2_5F_L (REG_SCL_DMA2_BASE + 0xBE) ++#define REG_SCL_DMA2_5F_H (REG_SCL_DMA2_BASE + 0xBF) ++#define REG_SCL_DMA2_60_L (REG_SCL_DMA2_BASE + 0xC0) ++#define REG_SCL_DMA2_60_H (REG_SCL_DMA2_BASE + 0xC1) ++#define REG_SCL_DMA2_61_L (REG_SCL_DMA2_BASE + 0xC2) ++#define REG_SCL_DMA2_61_H (REG_SCL_DMA2_BASE + 0xC3) ++#define REG_SCL_DMA2_62_L (REG_SCL_DMA2_BASE + 0xC4) ++#define REG_SCL_DMA2_62_H (REG_SCL_DMA2_BASE + 0xC5) ++#define REG_SCL_DMA2_63_L (REG_SCL_DMA2_BASE + 0xC6) ++#define REG_SCL_DMA2_63_H (REG_SCL_DMA2_BASE + 0xC7) ++#define REG_SCL_DMA2_64_L (REG_SCL_DMA2_BASE + 0xC8) ++#define REG_SCL_DMA2_64_H (REG_SCL_DMA2_BASE + 0xC9) ++#define REG_SCL_DMA2_65_L (REG_SCL_DMA2_BASE + 0xCA) ++#define REG_SCL_DMA2_65_H (REG_SCL_DMA2_BASE + 0xCB) ++#define REG_SCL_DMA2_66_L (REG_SCL_DMA2_BASE + 0xCC) ++#define REG_SCL_DMA2_66_H (REG_SCL_DMA2_BASE + 0xCD) ++#define REG_SCL_DMA2_67_L (REG_SCL_DMA2_BASE + 0xCE) ++#define REG_SCL_DMA2_67_H (REG_SCL_DMA2_BASE + 0xCF) ++#define REG_SCL_DMA2_68_L (REG_SCL_DMA2_BASE + 0xD0) ++#define REG_SCL_DMA2_68_H (REG_SCL_DMA2_BASE + 0xD1) ++#define REG_SCL_DMA2_69_L (REG_SCL_DMA2_BASE + 0xD2) ++#define REG_SCL_DMA2_69_H (REG_SCL_DMA2_BASE + 0xD3) ++#define REG_SCL_DMA2_6A_L (REG_SCL_DMA2_BASE + 0xD4) ++#define REG_SCL_DMA2_6A_H (REG_SCL_DMA2_BASE + 0xD5) ++#define REG_SCL_DMA2_6B_L (REG_SCL_DMA2_BASE + 0xD6) ++#define REG_SCL_DMA2_6B_H (REG_SCL_DMA2_BASE + 0xD7) ++#define REG_SCL_DMA2_6C_L (REG_SCL_DMA2_BASE + 0xD8) ++#define REG_SCL_DMA2_6C_H (REG_SCL_DMA2_BASE + 0xD9) ++#define REG_SCL_DMA2_6D_L (REG_SCL_DMA2_BASE + 0xDA) ++#define REG_SCL_DMA2_6D_H (REG_SCL_DMA2_BASE + 0xDB) ++#define REG_SCL_DMA2_6E_L (REG_SCL_DMA2_BASE + 0xDC) ++#define REG_SCL_DMA2_6E_H (REG_SCL_DMA2_BASE + 0xDD) ++#define REG_SCL_DMA2_6F_L (REG_SCL_DMA2_BASE + 0xDE) ++#define REG_SCL_DMA2_6F_H (REG_SCL_DMA2_BASE + 0xDF) ++#define REG_SCL_DMA2_70_L (REG_SCL_DMA2_BASE + 0xE0) ++#define REG_SCL_DMA2_70_H (REG_SCL_DMA2_BASE + 0xE1) ++#define REG_SCL_DMA2_71_L (REG_SCL_DMA2_BASE + 0xE2) ++#define REG_SCL_DMA2_71_H (REG_SCL_DMA2_BASE + 0xE3) ++#define REG_SCL_DMA2_72_L (REG_SCL_DMA2_BASE + 0xE4) ++#define REG_SCL_DMA2_72_H (REG_SCL_DMA2_BASE + 0xE5) ++#define REG_SCL_DMA2_73_L (REG_SCL_DMA2_BASE + 0xE6) ++#define REG_SCL_DMA2_73_H (REG_SCL_DMA2_BASE + 0xE7) ++#define REG_SCL_DMA2_74_L (REG_SCL_DMA2_BASE + 0xE8) ++#define REG_SCL_DMA2_74_H (REG_SCL_DMA2_BASE + 0xE9) ++#define REG_SCL_DMA2_75_L (REG_SCL_DMA2_BASE + 0xEA) ++#define REG_SCL_DMA2_75_H (REG_SCL_DMA2_BASE + 0xEB) ++#define REG_SCL_DMA2_76_L (REG_SCL_DMA2_BASE + 0xEC) ++#define REG_SCL_DMA2_76_H (REG_SCL_DMA2_BASE + 0xED) ++#define REG_SCL_DMA2_77_L (REG_SCL_DMA2_BASE + 0xEE) ++#define REG_SCL_DMA2_77_H (REG_SCL_DMA2_BASE + 0xEF) ++#define REG_SCL_DMA2_78_L (REG_SCL_DMA2_BASE + 0xF0) ++#define REG_SCL_DMA2_78_H (REG_SCL_DMA2_BASE + 0xF1) ++#define REG_SCL_DMA2_79_L (REG_SCL_DMA2_BASE + 0xF2) ++#define REG_SCL_DMA2_79_H (REG_SCL_DMA2_BASE + 0xF3) ++#define REG_SCL_DMA2_7A_L (REG_SCL_DMA2_BASE + 0xF4) ++#define REG_SCL_DMA2_7A_H (REG_SCL_DMA2_BASE + 0xF5) ++#define REG_SCL_DMA2_7B_L (REG_SCL_DMA2_BASE + 0xF6) ++#define REG_SCL_DMA2_7B_H (REG_SCL_DMA2_BASE + 0xF7) ++#define REG_SCL_DMA2_7C_L (REG_SCL_DMA2_BASE + 0xF8) ++#define REG_SCL_DMA2_7C_H (REG_SCL_DMA2_BASE + 0xF9) ++#define REG_SCL_DMA2_7D_L (REG_SCL_DMA2_BASE + 0xFA) ++#define REG_SCL_DMA2_7D_H (REG_SCL_DMA2_BASE + 0xFB) ++#define REG_SCL_DMA2_7E_L (REG_SCL_DMA2_BASE + 0xFC) ++#define REG_SCL_DMA2_7E_H (REG_SCL_DMA2_BASE + 0xFD) ++#define REG_SCL_DMA2_7F_L (REG_SCL_DMA2_BASE + 0xFE) ++#define REG_SCL_DMA2_7F_H (REG_SCL_DMA2_BASE + 0xFF) ++ ++#define REG_SCL_DNR0_00_L (REG_SCL_DNR0_BASE + 0x00) ++#define REG_SCL_DNR0_00_H (REG_SCL_DNR0_BASE + 0x01) ++#define REG_SCL_DNR0_01_L (REG_SCL_DNR0_BASE + 0x02) ++#define REG_SCL_DNR0_01_H (REG_SCL_DNR0_BASE + 0x03) ++#define REG_SCL_DNR0_02_L (REG_SCL_DNR0_BASE + 0x04) ++#define REG_SCL_DNR0_02_H (REG_SCL_DNR0_BASE + 0x05) ++#define REG_SCL_DNR0_03_L (REG_SCL_DNR0_BASE + 0x06) ++#define REG_SCL_DNR0_03_H (REG_SCL_DNR0_BASE + 0x07) ++#define REG_SCL_DNR0_04_L (REG_SCL_DNR0_BASE + 0x08) ++#define REG_SCL_DNR0_04_H (REG_SCL_DNR0_BASE + 0x09) ++#define REG_SCL_DNR0_05_L (REG_SCL_DNR0_BASE + 0x0A) ++#define REG_SCL_DNR0_05_H (REG_SCL_DNR0_BASE + 0x0B) ++#define REG_SCL_DNR0_06_L (REG_SCL_DNR0_BASE + 0x0C) ++#define REG_SCL_DNR0_06_H (REG_SCL_DNR0_BASE + 0x0D) ++#define REG_SCL_DNR0_07_L (REG_SCL_DNR0_BASE + 0x0E) ++#define REG_SCL_DNR0_07_H (REG_SCL_DNR0_BASE + 0x0F) ++#define REG_SCL_DNR0_08_L (REG_SCL_DNR0_BASE + 0x10) ++#define REG_SCL_DNR0_08_H (REG_SCL_DNR0_BASE + 0x11) ++#define REG_SCL_DNR0_09_L (REG_SCL_DNR0_BASE + 0x12) ++#define REG_SCL_DNR0_09_H (REG_SCL_DNR0_BASE + 0x13) ++#define REG_SCL_DNR0_0A_L (REG_SCL_DNR0_BASE + 0x14) ++#define REG_SCL_DNR0_0A_H (REG_SCL_DNR0_BASE + 0x15) ++#define REG_SCL_DNR0_0B_L (REG_SCL_DNR0_BASE + 0x16) ++#define REG_SCL_DNR0_0B_H (REG_SCL_DNR0_BASE + 0x17) ++#define REG_SCL_DNR0_0C_L (REG_SCL_DNR0_BASE + 0x18) ++#define REG_SCL_DNR0_0C_H (REG_SCL_DNR0_BASE + 0x19) ++#define REG_SCL_DNR0_0D_L (REG_SCL_DNR0_BASE + 0x1A) ++#define REG_SCL_DNR0_0D_H (REG_SCL_DNR0_BASE + 0x1B) ++#define REG_SCL_DNR0_0E_L (REG_SCL_DNR0_BASE + 0x1C) ++#define REG_SCL_DNR0_0E_H (REG_SCL_DNR0_BASE + 0x1D) ++#define REG_SCL_DNR0_0F_L (REG_SCL_DNR0_BASE + 0x1E) ++#define REG_SCL_DNR0_0F_H (REG_SCL_DNR0_BASE + 0x1F) ++#define REG_SCL_DNR0_10_L (REG_SCL_DNR0_BASE + 0x20) ++#define REG_SCL_DNR0_10_H (REG_SCL_DNR0_BASE + 0x21) ++#define REG_SCL_DNR0_11_L (REG_SCL_DNR0_BASE + 0x22) ++#define REG_SCL_DNR0_11_H (REG_SCL_DNR0_BASE + 0x23) ++#define REG_SCL_DNR0_12_L (REG_SCL_DNR0_BASE + 0x24) ++#define REG_SCL_DNR0_12_H (REG_SCL_DNR0_BASE + 0x25) ++#define REG_SCL_DNR0_13_L (REG_SCL_DNR0_BASE + 0x26) ++#define REG_SCL_DNR0_13_H (REG_SCL_DNR0_BASE + 0x27) ++#define REG_SCL_DNR0_14_L (REG_SCL_DNR0_BASE + 0x28) ++#define REG_SCL_DNR0_14_H (REG_SCL_DNR0_BASE + 0x29) ++#define REG_SCL_DNR0_15_L (REG_SCL_DNR0_BASE + 0x2A) ++#define REG_SCL_DNR0_15_H (REG_SCL_DNR0_BASE + 0x2B) ++#define REG_SCL_DNR0_16_L (REG_SCL_DNR0_BASE + 0x2C) ++#define REG_SCL_DNR0_16_H (REG_SCL_DNR0_BASE + 0x2D) ++#define REG_SCL_DNR0_17_L (REG_SCL_DNR0_BASE + 0x2E) ++#define REG_SCL_DNR0_17_H (REG_SCL_DNR0_BASE + 0x2F) ++#define REG_SCL_DNR0_18_L (REG_SCL_DNR0_BASE + 0x30) ++#define REG_SCL_DNR0_18_H (REG_SCL_DNR0_BASE + 0x31) ++#define REG_SCL_DNR0_19_L (REG_SCL_DNR0_BASE + 0x32) ++#define REG_SCL_DNR0_19_H (REG_SCL_DNR0_BASE + 0x33) ++#define REG_SCL_DNR0_1A_L (REG_SCL_DNR0_BASE + 0x34) ++#define REG_SCL_DNR0_1A_H (REG_SCL_DNR0_BASE + 0x35) ++#define REG_SCL_DNR0_1B_L (REG_SCL_DNR0_BASE + 0x36) ++#define REG_SCL_DNR0_1B_H (REG_SCL_DNR0_BASE + 0x37) ++#define REG_SCL_DNR0_1C_L (REG_SCL_DNR0_BASE + 0x38) ++#define REG_SCL_DNR0_1C_H (REG_SCL_DNR0_BASE + 0x39) ++#define REG_SCL_DNR0_1D_L (REG_SCL_DNR0_BASE + 0x3A) ++#define REG_SCL_DNR0_1D_H (REG_SCL_DNR0_BASE + 0x3B) ++#define REG_SCL_DNR0_1E_L (REG_SCL_DNR0_BASE + 0x3C) ++#define REG_SCL_DNR0_1E_H (REG_SCL_DNR0_BASE + 0x3D) ++#define REG_SCL_DNR0_1F_L (REG_SCL_DNR0_BASE + 0x3E) ++#define REG_SCL_DNR0_1F_H (REG_SCL_DNR0_BASE + 0x3F) ++#define REG_SCL_DNR0_20_L (REG_SCL_DNR0_BASE + 0x40) ++#define REG_SCL_DNR0_20_H (REG_SCL_DNR0_BASE + 0x41) ++#define REG_SCL_DNR0_21_L (REG_SCL_DNR0_BASE + 0x42) ++#define REG_SCL_DNR0_21_H (REG_SCL_DNR0_BASE + 0x43) ++#define REG_SCL_DNR0_22_L (REG_SCL_DNR0_BASE + 0x44) ++#define REG_SCL_DNR0_22_H (REG_SCL_DNR0_BASE + 0x45) ++#define REG_SCL_DNR0_23_L (REG_SCL_DNR0_BASE + 0x46) ++#define REG_SCL_DNR0_23_H (REG_SCL_DNR0_BASE + 0x47) ++#define REG_SCL_DNR0_24_L (REG_SCL_DNR0_BASE + 0x48) ++#define REG_SCL_DNR0_24_H (REG_SCL_DNR0_BASE + 0x49) ++#define REG_SCL_DNR0_25_L (REG_SCL_DNR0_BASE + 0x4A) ++#define REG_SCL_DNR0_25_H (REG_SCL_DNR0_BASE + 0x4B) ++#define REG_SCL_DNR0_26_L (REG_SCL_DNR0_BASE + 0x4C) ++#define REG_SCL_DNR0_26_H (REG_SCL_DNR0_BASE + 0x4D) ++#define REG_SCL_DNR0_27_L (REG_SCL_DNR0_BASE + 0x4E) ++#define REG_SCL_DNR0_27_H (REG_SCL_DNR0_BASE + 0x4F) ++#define REG_SCL_DNR0_28_L (REG_SCL_DNR0_BASE + 0x50) ++#define REG_SCL_DNR0_28_H (REG_SCL_DNR0_BASE + 0x51) ++#define REG_SCL_DNR0_29_L (REG_SCL_DNR0_BASE + 0x52) ++#define REG_SCL_DNR0_29_H (REG_SCL_DNR0_BASE + 0x53) ++#define REG_SCL_DNR0_2A_L (REG_SCL_DNR0_BASE + 0x54) ++#define REG_SCL_DNR0_2A_H (REG_SCL_DNR0_BASE + 0x55) ++#define REG_SCL_DNR0_2B_L (REG_SCL_DNR0_BASE + 0x56) ++#define REG_SCL_DNR0_2B_H (REG_SCL_DNR0_BASE + 0x57) ++#define REG_SCL_DNR0_2C_L (REG_SCL_DNR0_BASE + 0x58) ++#define REG_SCL_DNR0_2C_H (REG_SCL_DNR0_BASE + 0x59) ++#define REG_SCL_DNR0_2D_L (REG_SCL_DNR0_BASE + 0x5A) ++#define REG_SCL_DNR0_2D_H (REG_SCL_DNR0_BASE + 0x5B) ++#define REG_SCL_DNR0_2E_L (REG_SCL_DNR0_BASE + 0x5C) ++#define REG_SCL_DNR0_2E_H (REG_SCL_DNR0_BASE + 0x5D) ++#define REG_SCL_DNR0_2F_L (REG_SCL_DNR0_BASE + 0x5E) ++#define REG_SCL_DNR0_2F_H (REG_SCL_DNR0_BASE + 0x5F) ++#define REG_SCL_DNR0_30_L (REG_SCL_DNR0_BASE + 0x60) ++#define REG_SCL_DNR0_30_H (REG_SCL_DNR0_BASE + 0x61) ++#define REG_SCL_DNR0_31_L (REG_SCL_DNR0_BASE + 0x62) ++#define REG_SCL_DNR0_31_H (REG_SCL_DNR0_BASE + 0x63) ++#define REG_SCL_DNR0_32_L (REG_SCL_DNR0_BASE + 0x64) ++#define REG_SCL_DNR0_32_H (REG_SCL_DNR0_BASE + 0x65) ++#define REG_SCL_DNR0_33_L (REG_SCL_DNR0_BASE + 0x66) ++#define REG_SCL_DNR0_33_H (REG_SCL_DNR0_BASE + 0x67) ++#define REG_SCL_DNR0_34_L (REG_SCL_DNR0_BASE + 0x68) ++#define REG_SCL_DNR0_34_H (REG_SCL_DNR0_BASE + 0x69) ++#define REG_SCL_DNR0_35_L (REG_SCL_DNR0_BASE + 0x6A) ++#define REG_SCL_DNR0_35_H (REG_SCL_DNR0_BASE + 0x6B) ++#define REG_SCL_DNR0_36_L (REG_SCL_DNR0_BASE + 0x6C) ++#define REG_SCL_DNR0_36_H (REG_SCL_DNR0_BASE + 0x6D) ++#define REG_SCL_DNR0_37_L (REG_SCL_DNR0_BASE + 0x6E) ++#define REG_SCL_DNR0_37_H (REG_SCL_DNR0_BASE + 0x6F) ++#define REG_SCL_DNR0_38_L (REG_SCL_DNR0_BASE + 0x70) ++#define REG_SCL_DNR0_38_H (REG_SCL_DNR0_BASE + 0x71) ++#define REG_SCL_DNR0_39_L (REG_SCL_DNR0_BASE + 0x72) ++#define REG_SCL_DNR0_39_H (REG_SCL_DNR0_BASE + 0x73) ++#define REG_SCL_DNR0_3A_L (REG_SCL_DNR0_BASE + 0x74) ++#define REG_SCL_DNR0_3A_H (REG_SCL_DNR0_BASE + 0x75) ++#define REG_SCL_DNR0_3B_L (REG_SCL_DNR0_BASE + 0x76) ++#define REG_SCL_DNR0_3B_H (REG_SCL_DNR0_BASE + 0x77) ++#define REG_SCL_DNR0_3C_L (REG_SCL_DNR0_BASE + 0x78) ++#define REG_SCL_DNR0_3C_H (REG_SCL_DNR0_BASE + 0x79) ++#define REG_SCL_DNR0_3D_L (REG_SCL_DNR0_BASE + 0x7A) ++#define REG_SCL_DNR0_3D_H (REG_SCL_DNR0_BASE + 0x7B) ++#define REG_SCL_DNR0_3E_L (REG_SCL_DNR0_BASE + 0x7C) ++#define REG_SCL_DNR0_3E_H (REG_SCL_DNR0_BASE + 0x7D) ++#define REG_SCL_DNR0_3F_L (REG_SCL_DNR0_BASE + 0x7E) ++#define REG_SCL_DNR0_3F_H (REG_SCL_DNR0_BASE + 0x7F) ++#define REG_SCL_DNR0_40_L (REG_SCL_DNR0_BASE + 0x80) ++#define REG_SCL_DNR0_40_H (REG_SCL_DNR0_BASE + 0x81) ++#define REG_SCL_DNR0_41_L (REG_SCL_DNR0_BASE + 0x82) ++#define REG_SCL_DNR0_41_H (REG_SCL_DNR0_BASE + 0x83) ++#define REG_SCL_DNR0_42_L (REG_SCL_DNR0_BASE + 0x84) ++#define REG_SCL_DNR0_42_H (REG_SCL_DNR0_BASE + 0x85) ++#define REG_SCL_DNR0_43_L (REG_SCL_DNR0_BASE + 0x86) ++#define REG_SCL_DNR0_43_H (REG_SCL_DNR0_BASE + 0x87) ++#define REG_SCL_DNR0_44_L (REG_SCL_DNR0_BASE + 0x88) ++#define REG_SCL_DNR0_44_H (REG_SCL_DNR0_BASE + 0x89) ++#define REG_SCL_DNR0_45_L (REG_SCL_DNR0_BASE + 0x8A) ++#define REG_SCL_DNR0_45_H (REG_SCL_DNR0_BASE + 0x8B) ++#define REG_SCL_DNR0_46_L (REG_SCL_DNR0_BASE + 0x8C) ++#define REG_SCL_DNR0_46_H (REG_SCL_DNR0_BASE + 0x8D) ++#define REG_SCL_DNR0_47_L (REG_SCL_DNR0_BASE + 0x8E) ++#define REG_SCL_DNR0_47_H (REG_SCL_DNR0_BASE + 0x8F) ++#define REG_SCL_DNR0_48_L (REG_SCL_DNR0_BASE + 0x90) ++#define REG_SCL_DNR0_48_H (REG_SCL_DNR0_BASE + 0x91) ++#define REG_SCL_DNR0_49_L (REG_SCL_DNR0_BASE + 0x92) ++#define REG_SCL_DNR0_49_H (REG_SCL_DNR0_BASE + 0x93) ++#define REG_SCL_DNR0_4A_L (REG_SCL_DNR0_BASE + 0x94) ++#define REG_SCL_DNR0_4A_H (REG_SCL_DNR0_BASE + 0x95) ++#define REG_SCL_DNR0_4B_L (REG_SCL_DNR0_BASE + 0x96) ++#define REG_SCL_DNR0_4B_H (REG_SCL_DNR0_BASE + 0x97) ++#define REG_SCL_DNR0_4C_L (REG_SCL_DNR0_BASE + 0x98) ++#define REG_SCL_DNR0_4C_H (REG_SCL_DNR0_BASE + 0x99) ++#define REG_SCL_DNR0_4D_L (REG_SCL_DNR0_BASE + 0x9A) ++#define REG_SCL_DNR0_4D_H (REG_SCL_DNR0_BASE + 0x9B) ++#define REG_SCL_DNR0_4E_L (REG_SCL_DNR0_BASE + 0x9C) ++#define REG_SCL_DNR0_4E_H (REG_SCL_DNR0_BASE + 0x9D) ++#define REG_SCL_DNR0_4F_L (REG_SCL_DNR0_BASE + 0x9E) ++#define REG_SCL_DNR0_4F_H (REG_SCL_DNR0_BASE + 0x9F) ++#define REG_SCL_DNR0_50_L (REG_SCL_DNR0_BASE + 0xA0) ++#define REG_SCL_DNR0_50_H (REG_SCL_DNR0_BASE + 0xA1) ++#define REG_SCL_DNR0_51_L (REG_SCL_DNR0_BASE + 0xA2) ++#define REG_SCL_DNR0_51_H (REG_SCL_DNR0_BASE + 0xA3) ++#define REG_SCL_DNR0_52_L (REG_SCL_DNR0_BASE + 0xA4) ++#define REG_SCL_DNR0_52_H (REG_SCL_DNR0_BASE + 0xA5) ++#define REG_SCL_DNR0_53_L (REG_SCL_DNR0_BASE + 0xA6) ++#define REG_SCL_DNR0_53_H (REG_SCL_DNR0_BASE + 0xA7) ++#define REG_SCL_DNR0_54_L (REG_SCL_DNR0_BASE + 0xA8) ++#define REG_SCL_DNR0_54_H (REG_SCL_DNR0_BASE + 0xA9) ++#define REG_SCL_DNR0_55_L (REG_SCL_DNR0_BASE + 0xAA) ++#define REG_SCL_DNR0_55_H (REG_SCL_DNR0_BASE + 0xAB) ++#define REG_SCL_DNR0_56_L (REG_SCL_DNR0_BASE + 0xAC) ++#define REG_SCL_DNR0_56_H (REG_SCL_DNR0_BASE + 0xAD) ++#define REG_SCL_DNR0_57_L (REG_SCL_DNR0_BASE + 0xAE) ++#define REG_SCL_DNR0_57_H (REG_SCL_DNR0_BASE + 0xAF) ++#define REG_SCL_DNR0_58_L (REG_SCL_DNR0_BASE + 0xB0) ++#define REG_SCL_DNR0_58_H (REG_SCL_DNR0_BASE + 0xB1) ++#define REG_SCL_DNR0_59_L (REG_SCL_DNR0_BASE + 0xB2) ++#define REG_SCL_DNR0_59_H (REG_SCL_DNR0_BASE + 0xB3) ++#define REG_SCL_DNR0_5A_L (REG_SCL_DNR0_BASE + 0xB4) ++#define REG_SCL_DNR0_5A_H (REG_SCL_DNR0_BASE + 0xB5) ++#define REG_SCL_DNR0_5B_L (REG_SCL_DNR0_BASE + 0xB6) ++#define REG_SCL_DNR0_5B_H (REG_SCL_DNR0_BASE + 0xB7) ++#define REG_SCL_DNR0_5C_L (REG_SCL_DNR0_BASE + 0xB8) ++#define REG_SCL_DNR0_5C_H (REG_SCL_DNR0_BASE + 0xB9) ++#define REG_SCL_DNR0_5D_L (REG_SCL_DNR0_BASE + 0xBA) ++#define REG_SCL_DNR0_5D_H (REG_SCL_DNR0_BASE + 0xBB) ++#define REG_SCL_DNR0_5E_L (REG_SCL_DNR0_BASE + 0xBC) ++#define REG_SCL_DNR0_5E_H (REG_SCL_DNR0_BASE + 0xBD) ++#define REG_SCL_DNR0_5F_L (REG_SCL_DNR0_BASE + 0xBE) ++#define REG_SCL_DNR0_5F_H (REG_SCL_DNR0_BASE + 0xBF) ++#define REG_SCL_DNR0_60_L (REG_SCL_DNR0_BASE + 0xC0) ++#define REG_SCL_DNR0_60_H (REG_SCL_DNR0_BASE + 0xC1) ++#define REG_SCL_DNR0_61_L (REG_SCL_DNR0_BASE + 0xC2) ++#define REG_SCL_DNR0_61_H (REG_SCL_DNR0_BASE + 0xC3) ++#define REG_SCL_DNR0_62_L (REG_SCL_DNR0_BASE + 0xC4) ++#define REG_SCL_DNR0_62_H (REG_SCL_DNR0_BASE + 0xC5) ++#define REG_SCL_DNR0_63_L (REG_SCL_DNR0_BASE + 0xC6) ++#define REG_SCL_DNR0_63_H (REG_SCL_DNR0_BASE + 0xC7) ++#define REG_SCL_DNR0_64_L (REG_SCL_DNR0_BASE + 0xC8) ++#define REG_SCL_DNR0_64_H (REG_SCL_DNR0_BASE + 0xC9) ++#define REG_SCL_DNR0_65_L (REG_SCL_DNR0_BASE + 0xCA) ++#define REG_SCL_DNR0_65_H (REG_SCL_DNR0_BASE + 0xCB) ++#define REG_SCL_DNR0_66_L (REG_SCL_DNR0_BASE + 0xCC) ++#define REG_SCL_DNR0_66_H (REG_SCL_DNR0_BASE + 0xCD) ++#define REG_SCL_DNR0_67_L (REG_SCL_DNR0_BASE + 0xCE) ++#define REG_SCL_DNR0_67_H (REG_SCL_DNR0_BASE + 0xCF) ++#define REG_SCL_DNR0_68_L (REG_SCL_DNR0_BASE + 0xD0) ++#define REG_SCL_DNR0_68_H (REG_SCL_DNR0_BASE + 0xD1) ++#define REG_SCL_DNR0_69_L (REG_SCL_DNR0_BASE + 0xD2) ++#define REG_SCL_DNR0_69_H (REG_SCL_DNR0_BASE + 0xD3) ++#define REG_SCL_DNR0_6A_L (REG_SCL_DNR0_BASE + 0xD4) ++#define REG_SCL_DNR0_6A_H (REG_SCL_DNR0_BASE + 0xD5) ++#define REG_SCL_DNR0_6B_L (REG_SCL_DNR0_BASE + 0xD6) ++#define REG_SCL_DNR0_6B_H (REG_SCL_DNR0_BASE + 0xD7) ++#define REG_SCL_DNR0_6C_L (REG_SCL_DNR0_BASE + 0xD8) ++#define REG_SCL_DNR0_6C_H (REG_SCL_DNR0_BASE + 0xD9) ++#define REG_SCL_DNR0_6D_L (REG_SCL_DNR0_BASE + 0xDA) ++#define REG_SCL_DNR0_6D_H (REG_SCL_DNR0_BASE + 0xDB) ++#define REG_SCL_DNR0_6E_L (REG_SCL_DNR0_BASE + 0xDC) ++#define REG_SCL_DNR0_6E_H (REG_SCL_DNR0_BASE + 0xDD) ++#define REG_SCL_DNR0_6F_L (REG_SCL_DNR0_BASE + 0xDE) ++#define REG_SCL_DNR0_6F_H (REG_SCL_DNR0_BASE + 0xDF) ++#define REG_SCL_DNR0_70_L (REG_SCL_DNR0_BASE + 0xE0) ++#define REG_SCL_DNR0_70_H (REG_SCL_DNR0_BASE + 0xE1) ++#define REG_SCL_DNR0_71_L (REG_SCL_DNR0_BASE + 0xE2) ++#define REG_SCL_DNR0_71_H (REG_SCL_DNR0_BASE + 0xE3) ++#define REG_SCL_DNR0_72_L (REG_SCL_DNR0_BASE + 0xE4) ++#define REG_SCL_DNR0_72_H (REG_SCL_DNR0_BASE + 0xE5) ++#define REG_SCL_DNR0_73_L (REG_SCL_DNR0_BASE + 0xE6) ++#define REG_SCL_DNR0_73_H (REG_SCL_DNR0_BASE + 0xE7) ++#define REG_SCL_DNR0_74_L (REG_SCL_DNR0_BASE + 0xE8) ++#define REG_SCL_DNR0_74_H (REG_SCL_DNR0_BASE + 0xE9) ++#define REG_SCL_DNR0_75_L (REG_SCL_DNR0_BASE + 0xEA) ++#define REG_SCL_DNR0_75_H (REG_SCL_DNR0_BASE + 0xEB) ++#define REG_SCL_DNR0_76_L (REG_SCL_DNR0_BASE + 0xEC) ++#define REG_SCL_DNR0_76_H (REG_SCL_DNR0_BASE + 0xED) ++#define REG_SCL_DNR0_77_L (REG_SCL_DNR0_BASE + 0xEE) ++#define REG_SCL_DNR0_77_H (REG_SCL_DNR0_BASE + 0xEF) ++#define REG_SCL_DNR0_78_L (REG_SCL_DNR0_BASE + 0xF0) ++#define REG_SCL_DNR0_78_H (REG_SCL_DNR0_BASE + 0xF1) ++#define REG_SCL_DNR0_79_L (REG_SCL_DNR0_BASE + 0xF2) ++#define REG_SCL_DNR0_79_H (REG_SCL_DNR0_BASE + 0xF3) ++#define REG_SCL_DNR0_7A_L (REG_SCL_DNR0_BASE + 0xF4) ++#define REG_SCL_DNR0_7A_H (REG_SCL_DNR0_BASE + 0xF5) ++#define REG_SCL_DNR0_7B_L (REG_SCL_DNR0_BASE + 0xF6) ++#define REG_SCL_DNR0_7B_H (REG_SCL_DNR0_BASE + 0xF7) ++#define REG_SCL_DNR0_7C_L (REG_SCL_DNR0_BASE + 0xF8) ++#define REG_SCL_DNR0_7C_H (REG_SCL_DNR0_BASE + 0xF9) ++#define REG_SCL_DNR0_7D_L (REG_SCL_DNR0_BASE + 0xFA) ++#define REG_SCL_DNR0_7D_H (REG_SCL_DNR0_BASE + 0xFB) ++#define REG_SCL_DNR0_7E_L (REG_SCL_DNR0_BASE + 0xFC) ++#define REG_SCL_DNR0_7E_H (REG_SCL_DNR0_BASE + 0xFD) ++#define REG_SCL_DNR0_7F_L (REG_SCL_DNR0_BASE + 0xFE) ++#define REG_SCL_DNR0_7F_H (REG_SCL_DNR0_BASE + 0xFF) ++ ++#define REG_SCL_DNR1_00_L (REG_SCL_DNR1_BASE + 0x00) ++#define REG_SCL_DNR1_00_H (REG_SCL_DNR1_BASE + 0x01) ++#define REG_SCL_DNR1_01_L (REG_SCL_DNR1_BASE + 0x02) ++#define REG_SCL_DNR1_01_H (REG_SCL_DNR1_BASE + 0x03) ++#define REG_SCL_DNR1_02_L (REG_SCL_DNR1_BASE + 0x04) ++#define REG_SCL_DNR1_02_H (REG_SCL_DNR1_BASE + 0x05) ++#define REG_SCL_DNR1_03_L (REG_SCL_DNR1_BASE + 0x06) ++#define REG_SCL_DNR1_03_H (REG_SCL_DNR1_BASE + 0x07) ++#define REG_SCL_DNR1_04_L (REG_SCL_DNR1_BASE + 0x08) ++#define REG_SCL_DNR1_04_H (REG_SCL_DNR1_BASE + 0x09) ++#define REG_SCL_DNR1_05_L (REG_SCL_DNR1_BASE + 0x0A) ++#define REG_SCL_DNR1_05_H (REG_SCL_DNR1_BASE + 0x0B) ++#define REG_SCL_DNR1_06_L (REG_SCL_DNR1_BASE + 0x0C) ++#define REG_SCL_DNR1_06_H (REG_SCL_DNR1_BASE + 0x0D) ++#define REG_SCL_DNR1_07_L (REG_SCL_DNR1_BASE + 0x0E) ++#define REG_SCL_DNR1_07_H (REG_SCL_DNR1_BASE + 0x0F) ++#define REG_SCL_DNR1_08_L (REG_SCL_DNR1_BASE + 0x10) ++#define REG_SCL_DNR1_08_H (REG_SCL_DNR1_BASE + 0x11) ++#define REG_SCL_DNR1_09_L (REG_SCL_DNR1_BASE + 0x12) ++#define REG_SCL_DNR1_09_H (REG_SCL_DNR1_BASE + 0x13) ++#define REG_SCL_DNR1_0A_L (REG_SCL_DNR1_BASE + 0x14) ++#define REG_SCL_DNR1_0A_H (REG_SCL_DNR1_BASE + 0x15) ++#define REG_SCL_DNR1_0B_L (REG_SCL_DNR1_BASE + 0x16) ++#define REG_SCL_DNR1_0B_H (REG_SCL_DNR1_BASE + 0x17) ++#define REG_SCL_DNR1_0C_L (REG_SCL_DNR1_BASE + 0x18) ++#define REG_SCL_DNR1_0C_H (REG_SCL_DNR1_BASE + 0x19) ++#define REG_SCL_DNR1_0D_L (REG_SCL_DNR1_BASE + 0x1A) ++#define REG_SCL_DNR1_0D_H (REG_SCL_DNR1_BASE + 0x1B) ++#define REG_SCL_DNR1_0E_L (REG_SCL_DNR1_BASE + 0x1C) ++#define REG_SCL_DNR1_0E_H (REG_SCL_DNR1_BASE + 0x1D) ++#define REG_SCL_DNR1_0F_L (REG_SCL_DNR1_BASE + 0x1E) ++#define REG_SCL_DNR1_0F_H (REG_SCL_DNR1_BASE + 0x1F) ++#define REG_SCL_DNR1_10_L (REG_SCL_DNR1_BASE + 0x20) ++#define REG_SCL_DNR1_10_H (REG_SCL_DNR1_BASE + 0x21) ++#define REG_SCL_DNR1_11_L (REG_SCL_DNR1_BASE + 0x22) ++#define REG_SCL_DNR1_11_H (REG_SCL_DNR1_BASE + 0x23) ++#define REG_SCL_DNR1_12_L (REG_SCL_DNR1_BASE + 0x24) ++#define REG_SCL_DNR1_12_H (REG_SCL_DNR1_BASE + 0x25) ++#define REG_SCL_DNR1_13_L (REG_SCL_DNR1_BASE + 0x26) ++#define REG_SCL_DNR1_13_H (REG_SCL_DNR1_BASE + 0x27) ++#define REG_SCL_DNR1_14_L (REG_SCL_DNR1_BASE + 0x28) ++#define REG_SCL_DNR1_14_H (REG_SCL_DNR1_BASE + 0x29) ++#define REG_SCL_DNR1_15_L (REG_SCL_DNR1_BASE + 0x2A) ++#define REG_SCL_DNR1_15_H (REG_SCL_DNR1_BASE + 0x2B) ++#define REG_SCL_DNR1_16_L (REG_SCL_DNR1_BASE + 0x2C) ++#define REG_SCL_DNR1_16_H (REG_SCL_DNR1_BASE + 0x2D) ++#define REG_SCL_DNR1_17_L (REG_SCL_DNR1_BASE + 0x2E) ++#define REG_SCL_DNR1_17_H (REG_SCL_DNR1_BASE + 0x2F) ++#define REG_SCL_DNR1_18_L (REG_SCL_DNR1_BASE + 0x30) ++#define REG_SCL_DNR1_18_H (REG_SCL_DNR1_BASE + 0x31) ++#define REG_SCL_DNR1_19_L (REG_SCL_DNR1_BASE + 0x32) ++#define REG_SCL_DNR1_19_H (REG_SCL_DNR1_BASE + 0x33) ++#define REG_SCL_DNR1_1A_L (REG_SCL_DNR1_BASE + 0x34) ++#define REG_SCL_DNR1_1A_H (REG_SCL_DNR1_BASE + 0x35) ++#define REG_SCL_DNR1_1B_L (REG_SCL_DNR1_BASE + 0x36) ++#define REG_SCL_DNR1_1B_H (REG_SCL_DNR1_BASE + 0x37) ++#define REG_SCL_DNR1_1C_L (REG_SCL_DNR1_BASE + 0x38) ++#define REG_SCL_DNR1_1C_H (REG_SCL_DNR1_BASE + 0x39) ++#define REG_SCL_DNR1_1D_L (REG_SCL_DNR1_BASE + 0x3A) ++#define REG_SCL_DNR1_1D_H (REG_SCL_DNR1_BASE + 0x3B) ++#define REG_SCL_DNR1_1E_L (REG_SCL_DNR1_BASE + 0x3C) ++#define REG_SCL_DNR1_1E_H (REG_SCL_DNR1_BASE + 0x3D) ++#define REG_SCL_DNR1_1F_L (REG_SCL_DNR1_BASE + 0x3E) ++#define REG_SCL_DNR1_1F_H (REG_SCL_DNR1_BASE + 0x3F) ++#define REG_SCL_DNR1_20_L (REG_SCL_DNR1_BASE + 0x40) ++#define REG_SCL_DNR1_20_H (REG_SCL_DNR1_BASE + 0x41) ++#define REG_SCL_DNR1_21_L (REG_SCL_DNR1_BASE + 0x42) ++#define REG_SCL_DNR1_21_H (REG_SCL_DNR1_BASE + 0x43) ++#define REG_SCL_DNR1_22_L (REG_SCL_DNR1_BASE + 0x44) ++#define REG_SCL_DNR1_22_H (REG_SCL_DNR1_BASE + 0x45) ++#define REG_SCL_DNR1_23_L (REG_SCL_DNR1_BASE + 0x46) ++#define REG_SCL_DNR1_23_H (REG_SCL_DNR1_BASE + 0x47) ++#define REG_SCL_DNR1_24_L (REG_SCL_DNR1_BASE + 0x48) ++#define REG_SCL_DNR1_24_H (REG_SCL_DNR1_BASE + 0x49) ++#define REG_SCL_DNR1_25_L (REG_SCL_DNR1_BASE + 0x4A) ++#define REG_SCL_DNR1_25_H (REG_SCL_DNR1_BASE + 0x4B) ++#define REG_SCL_DNR1_26_L (REG_SCL_DNR1_BASE + 0x4C) ++#define REG_SCL_DNR1_26_H (REG_SCL_DNR1_BASE + 0x4D) ++#define REG_SCL_DNR1_27_L (REG_SCL_DNR1_BASE + 0x4E) ++#define REG_SCL_DNR1_27_H (REG_SCL_DNR1_BASE + 0x4F) ++#define REG_SCL_DNR1_28_L (REG_SCL_DNR1_BASE + 0x50) ++#define REG_SCL_DNR1_28_H (REG_SCL_DNR1_BASE + 0x51) ++#define REG_SCL_DNR1_29_L (REG_SCL_DNR1_BASE + 0x52) ++#define REG_SCL_DNR1_29_H (REG_SCL_DNR1_BASE + 0x53) ++#define REG_SCL_DNR1_2A_L (REG_SCL_DNR1_BASE + 0x54) ++#define REG_SCL_DNR1_2A_H (REG_SCL_DNR1_BASE + 0x55) ++#define REG_SCL_DNR1_2B_L (REG_SCL_DNR1_BASE + 0x56) ++#define REG_SCL_DNR1_2B_H (REG_SCL_DNR1_BASE + 0x57) ++#define REG_SCL_DNR1_2C_L (REG_SCL_DNR1_BASE + 0x58) ++#define REG_SCL_DNR1_2C_H (REG_SCL_DNR1_BASE + 0x59) ++#define REG_SCL_DNR1_2D_L (REG_SCL_DNR1_BASE + 0x5A) ++#define REG_SCL_DNR1_2D_H (REG_SCL_DNR1_BASE + 0x5B) ++#define REG_SCL_DNR1_2E_L (REG_SCL_DNR1_BASE + 0x5C) ++#define REG_SCL_DNR1_2E_H (REG_SCL_DNR1_BASE + 0x5D) ++#define REG_SCL_DNR1_2F_L (REG_SCL_DNR1_BASE + 0x5E) ++#define REG_SCL_DNR1_2F_H (REG_SCL_DNR1_BASE + 0x5F) ++#define REG_SCL_DNR1_30_L (REG_SCL_DNR1_BASE + 0x60) ++#define REG_SCL_DNR1_30_H (REG_SCL_DNR1_BASE + 0x61) ++#define REG_SCL_DNR1_31_L (REG_SCL_DNR1_BASE + 0x62) ++#define REG_SCL_DNR1_31_H (REG_SCL_DNR1_BASE + 0x63) ++#define REG_SCL_DNR1_32_L (REG_SCL_DNR1_BASE + 0x64) ++#define REG_SCL_DNR1_32_H (REG_SCL_DNR1_BASE + 0x65) ++#define REG_SCL_DNR1_33_L (REG_SCL_DNR1_BASE + 0x66) ++#define REG_SCL_DNR1_33_H (REG_SCL_DNR1_BASE + 0x67) ++#define REG_SCL_DNR1_34_L (REG_SCL_DNR1_BASE + 0x68) ++#define REG_SCL_DNR1_34_H (REG_SCL_DNR1_BASE + 0x69) ++#define REG_SCL_DNR1_35_L (REG_SCL_DNR1_BASE + 0x6A) ++#define REG_SCL_DNR1_35_H (REG_SCL_DNR1_BASE + 0x6B) ++#define REG_SCL_DNR1_36_L (REG_SCL_DNR1_BASE + 0x6C) ++#define REG_SCL_DNR1_36_H (REG_SCL_DNR1_BASE + 0x6D) ++#define REG_SCL_DNR1_37_L (REG_SCL_DNR1_BASE + 0x6E) ++#define REG_SCL_DNR1_37_H (REG_SCL_DNR1_BASE + 0x6F) ++#define REG_SCL_DNR1_38_L (REG_SCL_DNR1_BASE + 0x70) ++#define REG_SCL_DNR1_38_H (REG_SCL_DNR1_BASE + 0x71) ++#define REG_SCL_DNR1_39_L (REG_SCL_DNR1_BASE + 0x72) ++#define REG_SCL_DNR1_39_H (REG_SCL_DNR1_BASE + 0x73) ++#define REG_SCL_DNR1_3A_L (REG_SCL_DNR1_BASE + 0x74) ++#define REG_SCL_DNR1_3A_H (REG_SCL_DNR1_BASE + 0x75) ++#define REG_SCL_DNR1_3B_L (REG_SCL_DNR1_BASE + 0x76) ++#define REG_SCL_DNR1_3B_H (REG_SCL_DNR1_BASE + 0x77) ++#define REG_SCL_DNR1_3C_L (REG_SCL_DNR1_BASE + 0x78) ++#define REG_SCL_DNR1_3C_H (REG_SCL_DNR1_BASE + 0x79) ++#define REG_SCL_DNR1_3D_L (REG_SCL_DNR1_BASE + 0x7A) ++#define REG_SCL_DNR1_3D_H (REG_SCL_DNR1_BASE + 0x7B) ++#define REG_SCL_DNR1_3E_L (REG_SCL_DNR1_BASE + 0x7C) ++#define REG_SCL_DNR1_3E_H (REG_SCL_DNR1_BASE + 0x7D) ++#define REG_SCL_DNR1_3F_L (REG_SCL_DNR1_BASE + 0x7E) ++#define REG_SCL_DNR1_3F_H (REG_SCL_DNR1_BASE + 0x7F) ++#define REG_SCL_DNR1_40_L (REG_SCL_DNR1_BASE + 0x80) ++#define REG_SCL_DNR1_40_H (REG_SCL_DNR1_BASE + 0x81) ++#define REG_SCL_DNR1_41_L (REG_SCL_DNR1_BASE + 0x82) ++#define REG_SCL_DNR1_41_H (REG_SCL_DNR1_BASE + 0x83) ++#define REG_SCL_DNR1_42_L (REG_SCL_DNR1_BASE + 0x84) ++#define REG_SCL_DNR1_42_H (REG_SCL_DNR1_BASE + 0x85) ++#define REG_SCL_DNR1_43_L (REG_SCL_DNR1_BASE + 0x86) ++#define REG_SCL_DNR1_43_H (REG_SCL_DNR1_BASE + 0x87) ++#define REG_SCL_DNR1_44_L (REG_SCL_DNR1_BASE + 0x88) ++#define REG_SCL_DNR1_44_H (REG_SCL_DNR1_BASE + 0x89) ++#define REG_SCL_DNR1_45_L (REG_SCL_DNR1_BASE + 0x8A) ++#define REG_SCL_DNR1_45_H (REG_SCL_DNR1_BASE + 0x8B) ++#define REG_SCL_DNR1_46_L (REG_SCL_DNR1_BASE + 0x8C) ++#define REG_SCL_DNR1_46_H (REG_SCL_DNR1_BASE + 0x8D) ++#define REG_SCL_DNR1_47_L (REG_SCL_DNR1_BASE + 0x8E) ++#define REG_SCL_DNR1_47_H (REG_SCL_DNR1_BASE + 0x8F) ++#define REG_SCL_DNR1_48_L (REG_SCL_DNR1_BASE + 0x90) ++#define REG_SCL_DNR1_48_H (REG_SCL_DNR1_BASE + 0x91) ++#define REG_SCL_DNR1_49_L (REG_SCL_DNR1_BASE + 0x92) ++#define REG_SCL_DNR1_49_H (REG_SCL_DNR1_BASE + 0x93) ++#define REG_SCL_DNR1_4A_L (REG_SCL_DNR1_BASE + 0x94) ++#define REG_SCL_DNR1_4A_H (REG_SCL_DNR1_BASE + 0x95) ++#define REG_SCL_DNR1_4B_L (REG_SCL_DNR1_BASE + 0x96) ++#define REG_SCL_DNR1_4B_H (REG_SCL_DNR1_BASE + 0x97) ++#define REG_SCL_DNR1_4C_L (REG_SCL_DNR1_BASE + 0x98) ++#define REG_SCL_DNR1_4C_H (REG_SCL_DNR1_BASE + 0x99) ++#define REG_SCL_DNR1_4D_L (REG_SCL_DNR1_BASE + 0x9A) ++#define REG_SCL_DNR1_4D_H (REG_SCL_DNR1_BASE + 0x9B) ++#define REG_SCL_DNR1_4E_L (REG_SCL_DNR1_BASE + 0x9C) ++#define REG_SCL_DNR1_4E_H (REG_SCL_DNR1_BASE + 0x9D) ++#define REG_SCL_DNR1_4F_L (REG_SCL_DNR1_BASE + 0x9E) ++#define REG_SCL_DNR1_4F_H (REG_SCL_DNR1_BASE + 0x9F) ++#define REG_SCL_DNR1_50_L (REG_SCL_DNR1_BASE + 0xA0) ++#define REG_SCL_DNR1_50_H (REG_SCL_DNR1_BASE + 0xA1) ++#define REG_SCL_DNR1_51_L (REG_SCL_DNR1_BASE + 0xA2) ++#define REG_SCL_DNR1_51_H (REG_SCL_DNR1_BASE + 0xA3) ++#define REG_SCL_DNR1_52_L (REG_SCL_DNR1_BASE + 0xA4) ++#define REG_SCL_DNR1_52_H (REG_SCL_DNR1_BASE + 0xA5) ++#define REG_SCL_DNR1_53_L (REG_SCL_DNR1_BASE + 0xA6) ++#define REG_SCL_DNR1_53_H (REG_SCL_DNR1_BASE + 0xA7) ++#define REG_SCL_DNR1_54_L (REG_SCL_DNR1_BASE + 0xA8) ++#define REG_SCL_DNR1_54_H (REG_SCL_DNR1_BASE + 0xA9) ++#define REG_SCL_DNR1_55_L (REG_SCL_DNR1_BASE + 0xAA) ++#define REG_SCL_DNR1_55_H (REG_SCL_DNR1_BASE + 0xAB) ++#define REG_SCL_DNR1_56_L (REG_SCL_DNR1_BASE + 0xAC) ++#define REG_SCL_DNR1_56_H (REG_SCL_DNR1_BASE + 0xAD) ++#define REG_SCL_DNR1_57_L (REG_SCL_DNR1_BASE + 0xAE) ++#define REG_SCL_DNR1_57_H (REG_SCL_DNR1_BASE + 0xAF) ++#define REG_SCL_DNR1_58_L (REG_SCL_DNR1_BASE + 0xB0) ++#define REG_SCL_DNR1_58_H (REG_SCL_DNR1_BASE + 0xB1) ++#define REG_SCL_DNR1_59_L (REG_SCL_DNR1_BASE + 0xB2) ++#define REG_SCL_DNR1_59_H (REG_SCL_DNR1_BASE + 0xB3) ++#define REG_SCL_DNR1_5A_L (REG_SCL_DNR1_BASE + 0xB4) ++#define REG_SCL_DNR1_5A_H (REG_SCL_DNR1_BASE + 0xB5) ++#define REG_SCL_DNR1_5B_L (REG_SCL_DNR1_BASE + 0xB6) ++#define REG_SCL_DNR1_5B_H (REG_SCL_DNR1_BASE + 0xB7) ++#define REG_SCL_DNR1_5C_L (REG_SCL_DNR1_BASE + 0xB8) ++#define REG_SCL_DNR1_5C_H (REG_SCL_DNR1_BASE + 0xB9) ++#define REG_SCL_DNR1_5D_L (REG_SCL_DNR1_BASE + 0xBA) ++#define REG_SCL_DNR1_5D_H (REG_SCL_DNR1_BASE + 0xBB) ++#define REG_SCL_DNR1_5E_L (REG_SCL_DNR1_BASE + 0xBC) ++#define REG_SCL_DNR1_5E_H (REG_SCL_DNR1_BASE + 0xBD) ++#define REG_SCL_DNR1_5F_L (REG_SCL_DNR1_BASE + 0xBE) ++#define REG_SCL_DNR1_5F_H (REG_SCL_DNR1_BASE + 0xBF) ++#define REG_SCL_DNR1_60_L (REG_SCL_DNR1_BASE + 0xC0) ++#define REG_SCL_DNR1_60_H (REG_SCL_DNR1_BASE + 0xC1) ++#define REG_SCL_DNR1_61_L (REG_SCL_DNR1_BASE + 0xC2) ++#define REG_SCL_DNR1_61_H (REG_SCL_DNR1_BASE + 0xC3) ++#define REG_SCL_DNR1_62_L (REG_SCL_DNR1_BASE + 0xC4) ++#define REG_SCL_DNR1_62_H (REG_SCL_DNR1_BASE + 0xC5) ++#define REG_SCL_DNR1_63_L (REG_SCL_DNR1_BASE + 0xC6) ++#define REG_SCL_DNR1_63_H (REG_SCL_DNR1_BASE + 0xC7) ++#define REG_SCL_DNR1_64_L (REG_SCL_DNR1_BASE + 0xC8) ++#define REG_SCL_DNR1_64_H (REG_SCL_DNR1_BASE + 0xC9) ++#define REG_SCL_DNR1_65_L (REG_SCL_DNR1_BASE + 0xCA) ++#define REG_SCL_DNR1_65_H (REG_SCL_DNR1_BASE + 0xCB) ++#define REG_SCL_DNR1_66_L (REG_SCL_DNR1_BASE + 0xCC) ++#define REG_SCL_DNR1_66_H (REG_SCL_DNR1_BASE + 0xCD) ++#define REG_SCL_DNR1_67_L (REG_SCL_DNR1_BASE + 0xCE) ++#define REG_SCL_DNR1_67_H (REG_SCL_DNR1_BASE + 0xCF) ++#define REG_SCL_DNR1_68_L (REG_SCL_DNR1_BASE + 0xD0) ++#define REG_SCL_DNR1_68_H (REG_SCL_DNR1_BASE + 0xD1) ++#define REG_SCL_DNR1_69_L (REG_SCL_DNR1_BASE + 0xD2) ++#define REG_SCL_DNR1_69_H (REG_SCL_DNR1_BASE + 0xD3) ++#define REG_SCL_DNR1_6A_L (REG_SCL_DNR1_BASE + 0xD4) ++#define REG_SCL_DNR1_6A_H (REG_SCL_DNR1_BASE + 0xD5) ++#define REG_SCL_DNR1_6B_L (REG_SCL_DNR1_BASE + 0xD6) ++#define REG_SCL_DNR1_6B_H (REG_SCL_DNR1_BASE + 0xD7) ++#define REG_SCL_DNR1_6C_L (REG_SCL_DNR1_BASE + 0xD8) ++#define REG_SCL_DNR1_6C_H (REG_SCL_DNR1_BASE + 0xD9) ++#define REG_SCL_DNR1_6D_L (REG_SCL_DNR1_BASE + 0xDA) ++#define REG_SCL_DNR1_6D_H (REG_SCL_DNR1_BASE + 0xDB) ++#define REG_SCL_DNR1_6E_L (REG_SCL_DNR1_BASE + 0xDC) ++#define REG_SCL_DNR1_6E_H (REG_SCL_DNR1_BASE + 0xDD) ++#define REG_SCL_DNR1_6F_L (REG_SCL_DNR1_BASE + 0xDE) ++#define REG_SCL_DNR1_6F_H (REG_SCL_DNR1_BASE + 0xDF) ++#define REG_SCL_DNR1_70_L (REG_SCL_DNR1_BASE + 0xE0) ++#define REG_SCL_DNR1_70_H (REG_SCL_DNR1_BASE + 0xE1) ++#define REG_SCL_DNR1_71_L (REG_SCL_DNR1_BASE + 0xE2) ++#define REG_SCL_DNR1_71_H (REG_SCL_DNR1_BASE + 0xE3) ++#define REG_SCL_DNR1_72_L (REG_SCL_DNR1_BASE + 0xE4) ++#define REG_SCL_DNR1_72_H (REG_SCL_DNR1_BASE + 0xE5) ++#define REG_SCL_DNR1_73_L (REG_SCL_DNR1_BASE + 0xE6) ++#define REG_SCL_DNR1_73_H (REG_SCL_DNR1_BASE + 0xE7) ++#define REG_SCL_DNR1_74_L (REG_SCL_DNR1_BASE + 0xE8) ++#define REG_SCL_DNR1_74_H (REG_SCL_DNR1_BASE + 0xE9) ++#define REG_SCL_DNR1_75_L (REG_SCL_DNR1_BASE + 0xEA) ++#define REG_SCL_DNR1_75_H (REG_SCL_DNR1_BASE + 0xEB) ++#define REG_SCL_DNR1_76_L (REG_SCL_DNR1_BASE + 0xEC) ++#define REG_SCL_DNR1_76_H (REG_SCL_DNR1_BASE + 0xED) ++#define REG_SCL_DNR1_77_L (REG_SCL_DNR1_BASE + 0xEE) ++#define REG_SCL_DNR1_77_H (REG_SCL_DNR1_BASE + 0xEF) ++#define REG_SCL_DNR1_78_L (REG_SCL_DNR1_BASE + 0xF0) ++#define REG_SCL_DNR1_78_H (REG_SCL_DNR1_BASE + 0xF1) ++#define REG_SCL_DNR1_79_L (REG_SCL_DNR1_BASE + 0xF2) ++#define REG_SCL_DNR1_79_H (REG_SCL_DNR1_BASE + 0xF3) ++#define REG_SCL_DNR1_7A_L (REG_SCL_DNR1_BASE + 0xF4) ++#define REG_SCL_DNR1_7A_H (REG_SCL_DNR1_BASE + 0xF5) ++#define REG_SCL_DNR1_7B_L (REG_SCL_DNR1_BASE + 0xF6) ++#define REG_SCL_DNR1_7B_H (REG_SCL_DNR1_BASE + 0xF7) ++#define REG_SCL_DNR1_7C_L (REG_SCL_DNR1_BASE + 0xF8) ++#define REG_SCL_DNR1_7C_H (REG_SCL_DNR1_BASE + 0xF9) ++#define REG_SCL_DNR1_7D_L (REG_SCL_DNR1_BASE + 0xFA) ++#define REG_SCL_DNR1_7D_H (REG_SCL_DNR1_BASE + 0xFB) ++#define REG_SCL_DNR1_7E_L (REG_SCL_DNR1_BASE + 0xFC) ++#define REG_SCL_DNR1_7E_H (REG_SCL_DNR1_BASE + 0xFD) ++#define REG_SCL_DNR1_7F_L (REG_SCL_DNR1_BASE + 0xFE) ++#define REG_SCL_DNR1_7F_H (REG_SCL_DNR1_BASE + 0xFF) ++ ++#define REG_SCL_DNR2_00_L (REG_SCL_DNR2_BASE + 0x00) ++#define REG_SCL_DNR2_00_H (REG_SCL_DNR2_BASE + 0x01) ++#define REG_SCL_DNR2_01_L (REG_SCL_DNR2_BASE + 0x02) ++#define REG_SCL_DNR2_01_H (REG_SCL_DNR2_BASE + 0x03) ++#define REG_SCL_DNR2_02_L (REG_SCL_DNR2_BASE + 0x04) ++#define REG_SCL_DNR2_02_H (REG_SCL_DNR2_BASE + 0x05) ++#define REG_SCL_DNR2_03_L (REG_SCL_DNR2_BASE + 0x06) ++#define REG_SCL_DNR2_03_H (REG_SCL_DNR2_BASE + 0x07) ++#define REG_SCL_DNR2_04_L (REG_SCL_DNR2_BASE + 0x08) ++#define REG_SCL_DNR2_04_H (REG_SCL_DNR2_BASE + 0x09) ++#define REG_SCL_DNR2_05_L (REG_SCL_DNR2_BASE + 0x0A) ++#define REG_SCL_DNR2_05_H (REG_SCL_DNR2_BASE + 0x0B) ++#define REG_SCL_DNR2_06_L (REG_SCL_DNR2_BASE + 0x0C) ++#define REG_SCL_DNR2_06_H (REG_SCL_DNR2_BASE + 0x0D) ++#define REG_SCL_DNR2_07_L (REG_SCL_DNR2_BASE + 0x0E) ++#define REG_SCL_DNR2_07_H (REG_SCL_DNR2_BASE + 0x0F) ++#define REG_SCL_DNR2_08_L (REG_SCL_DNR2_BASE + 0x10) ++#define REG_SCL_DNR2_08_H (REG_SCL_DNR2_BASE + 0x11) ++#define REG_SCL_DNR2_09_L (REG_SCL_DNR2_BASE + 0x12) ++#define REG_SCL_DNR2_09_H (REG_SCL_DNR2_BASE + 0x13) ++#define REG_SCL_DNR2_0A_L (REG_SCL_DNR2_BASE + 0x14) ++#define REG_SCL_DNR2_0A_H (REG_SCL_DNR2_BASE + 0x15) ++#define REG_SCL_DNR2_0B_L (REG_SCL_DNR2_BASE + 0x16) ++#define REG_SCL_DNR2_0B_H (REG_SCL_DNR2_BASE + 0x17) ++#define REG_SCL_DNR2_0C_L (REG_SCL_DNR2_BASE + 0x18) ++#define REG_SCL_DNR2_0C_H (REG_SCL_DNR2_BASE + 0x19) ++#define REG_SCL_DNR2_0D_L (REG_SCL_DNR2_BASE + 0x1A) ++#define REG_SCL_DNR2_0D_H (REG_SCL_DNR2_BASE + 0x1B) ++#define REG_SCL_DNR2_0E_L (REG_SCL_DNR2_BASE + 0x1C) ++#define REG_SCL_DNR2_0E_H (REG_SCL_DNR2_BASE + 0x1D) ++#define REG_SCL_DNR2_0F_L (REG_SCL_DNR2_BASE + 0x1E) ++#define REG_SCL_DNR2_0F_H (REG_SCL_DNR2_BASE + 0x1F) ++#define REG_SCL_DNR2_10_L (REG_SCL_DNR2_BASE + 0x20) ++#define REG_SCL_DNR2_10_H (REG_SCL_DNR2_BASE + 0x21) ++#define REG_SCL_DNR2_11_L (REG_SCL_DNR2_BASE + 0x22) ++#define REG_SCL_DNR2_11_H (REG_SCL_DNR2_BASE + 0x23) ++#define REG_SCL_DNR2_12_L (REG_SCL_DNR2_BASE + 0x24) ++#define REG_SCL_DNR2_12_H (REG_SCL_DNR2_BASE + 0x25) ++#define REG_SCL_DNR2_13_L (REG_SCL_DNR2_BASE + 0x26) ++#define REG_SCL_DNR2_13_H (REG_SCL_DNR2_BASE + 0x27) ++#define REG_SCL_DNR2_14_L (REG_SCL_DNR2_BASE + 0x28) ++#define REG_SCL_DNR2_14_H (REG_SCL_DNR2_BASE + 0x29) ++#define REG_SCL_DNR2_15_L (REG_SCL_DNR2_BASE + 0x2A) ++#define REG_SCL_DNR2_15_H (REG_SCL_DNR2_BASE + 0x2B) ++#define REG_SCL_DNR2_16_L (REG_SCL_DNR2_BASE + 0x2C) ++#define REG_SCL_DNR2_16_H (REG_SCL_DNR2_BASE + 0x2D) ++#define REG_SCL_DNR2_17_L (REG_SCL_DNR2_BASE + 0x2E) ++#define REG_SCL_DNR2_17_H (REG_SCL_DNR2_BASE + 0x2F) ++#define REG_SCL_DNR2_18_L (REG_SCL_DNR2_BASE + 0x30) ++#define REG_SCL_DNR2_18_H (REG_SCL_DNR2_BASE + 0x31) ++#define REG_SCL_DNR2_19_L (REG_SCL_DNR2_BASE + 0x32) ++#define REG_SCL_DNR2_19_H (REG_SCL_DNR2_BASE + 0x33) ++#define REG_SCL_DNR2_1A_L (REG_SCL_DNR2_BASE + 0x34) ++#define REG_SCL_DNR2_1A_H (REG_SCL_DNR2_BASE + 0x35) ++#define REG_SCL_DNR2_1B_L (REG_SCL_DNR2_BASE + 0x36) ++#define REG_SCL_DNR2_1B_H (REG_SCL_DNR2_BASE + 0x37) ++#define REG_SCL_DNR2_1C_L (REG_SCL_DNR2_BASE + 0x38) ++#define REG_SCL_DNR2_1C_H (REG_SCL_DNR2_BASE + 0x39) ++#define REG_SCL_DNR2_1D_L (REG_SCL_DNR2_BASE + 0x3A) ++#define REG_SCL_DNR2_1D_H (REG_SCL_DNR2_BASE + 0x3B) ++#define REG_SCL_DNR2_1E_L (REG_SCL_DNR2_BASE + 0x3C) ++#define REG_SCL_DNR2_1E_H (REG_SCL_DNR2_BASE + 0x3D) ++#define REG_SCL_DNR2_1F_L (REG_SCL_DNR2_BASE + 0x3E) ++#define REG_SCL_DNR2_1F_H (REG_SCL_DNR2_BASE + 0x3F) ++#define REG_SCL_DNR2_20_L (REG_SCL_DNR2_BASE + 0x40) ++#define REG_SCL_DNR2_20_H (REG_SCL_DNR2_BASE + 0x41) ++#define REG_SCL_DNR2_21_L (REG_SCL_DNR2_BASE + 0x42) ++#define REG_SCL_DNR2_21_H (REG_SCL_DNR2_BASE + 0x43) ++#define REG_SCL_DNR2_22_L (REG_SCL_DNR2_BASE + 0x44) ++#define REG_SCL_DNR2_22_H (REG_SCL_DNR2_BASE + 0x45) ++#define REG_SCL_DNR2_23_L (REG_SCL_DNR2_BASE + 0x46) ++#define REG_SCL_DNR2_23_H (REG_SCL_DNR2_BASE + 0x47) ++#define REG_SCL_DNR2_24_L (REG_SCL_DNR2_BASE + 0x48) ++#define REG_SCL_DNR2_24_H (REG_SCL_DNR2_BASE + 0x49) ++#define REG_SCL_DNR2_25_L (REG_SCL_DNR2_BASE + 0x4A) ++#define REG_SCL_DNR2_25_H (REG_SCL_DNR2_BASE + 0x4B) ++#define REG_SCL_DNR2_26_L (REG_SCL_DNR2_BASE + 0x4C) ++#define REG_SCL_DNR2_26_H (REG_SCL_DNR2_BASE + 0x4D) ++#define REG_SCL_DNR2_27_L (REG_SCL_DNR2_BASE + 0x4E) ++#define REG_SCL_DNR2_27_H (REG_SCL_DNR2_BASE + 0x4F) ++#define REG_SCL_DNR2_28_L (REG_SCL_DNR2_BASE + 0x50) ++#define REG_SCL_DNR2_28_H (REG_SCL_DNR2_BASE + 0x51) ++#define REG_SCL_DNR2_29_L (REG_SCL_DNR2_BASE + 0x52) ++#define REG_SCL_DNR2_29_H (REG_SCL_DNR2_BASE + 0x53) ++#define REG_SCL_DNR2_2A_L (REG_SCL_DNR2_BASE + 0x54) ++#define REG_SCL_DNR2_2A_H (REG_SCL_DNR2_BASE + 0x55) ++#define REG_SCL_DNR2_2B_L (REG_SCL_DNR2_BASE + 0x56) ++#define REG_SCL_DNR2_2B_H (REG_SCL_DNR2_BASE + 0x57) ++#define REG_SCL_DNR2_2C_L (REG_SCL_DNR2_BASE + 0x58) ++#define REG_SCL_DNR2_2C_H (REG_SCL_DNR2_BASE + 0x59) ++#define REG_SCL_DNR2_2D_L (REG_SCL_DNR2_BASE + 0x5A) ++#define REG_SCL_DNR2_2D_H (REG_SCL_DNR2_BASE + 0x5B) ++#define REG_SCL_DNR2_2E_L (REG_SCL_DNR2_BASE + 0x5C) ++#define REG_SCL_DNR2_2E_H (REG_SCL_DNR2_BASE + 0x5D) ++#define REG_SCL_DNR2_2F_L (REG_SCL_DNR2_BASE + 0x5E) ++#define REG_SCL_DNR2_2F_H (REG_SCL_DNR2_BASE + 0x5F) ++#define REG_SCL_DNR2_30_L (REG_SCL_DNR2_BASE + 0x60) ++#define REG_SCL_DNR2_30_H (REG_SCL_DNR2_BASE + 0x61) ++#define REG_SCL_DNR2_31_L (REG_SCL_DNR2_BASE + 0x62) ++#define REG_SCL_DNR2_31_H (REG_SCL_DNR2_BASE + 0x63) ++#define REG_SCL_DNR2_32_L (REG_SCL_DNR2_BASE + 0x64) ++#define REG_SCL_DNR2_32_H (REG_SCL_DNR2_BASE + 0x65) ++#define REG_SCL_DNR2_33_L (REG_SCL_DNR2_BASE + 0x66) ++#define REG_SCL_DNR2_33_H (REG_SCL_DNR2_BASE + 0x67) ++#define REG_SCL_DNR2_34_L (REG_SCL_DNR2_BASE + 0x68) ++#define REG_SCL_DNR2_34_H (REG_SCL_DNR2_BASE + 0x69) ++#define REG_SCL_DNR2_35_L (REG_SCL_DNR2_BASE + 0x6A) ++#define REG_SCL_DNR2_35_H (REG_SCL_DNR2_BASE + 0x6B) ++#define REG_SCL_DNR2_36_L (REG_SCL_DNR2_BASE + 0x6C) ++#define REG_SCL_DNR2_36_H (REG_SCL_DNR2_BASE + 0x6D) ++#define REG_SCL_DNR2_37_L (REG_SCL_DNR2_BASE + 0x6E) ++#define REG_SCL_DNR2_37_H (REG_SCL_DNR2_BASE + 0x6F) ++#define REG_SCL_DNR2_38_L (REG_SCL_DNR2_BASE + 0x70) ++#define REG_SCL_DNR2_38_H (REG_SCL_DNR2_BASE + 0x71) ++#define REG_SCL_DNR2_39_L (REG_SCL_DNR2_BASE + 0x72) ++#define REG_SCL_DNR2_39_H (REG_SCL_DNR2_BASE + 0x73) ++#define REG_SCL_DNR2_3A_L (REG_SCL_DNR2_BASE + 0x74) ++#define REG_SCL_DNR2_3A_H (REG_SCL_DNR2_BASE + 0x75) ++#define REG_SCL_DNR2_3B_L (REG_SCL_DNR2_BASE + 0x76) ++#define REG_SCL_DNR2_3B_H (REG_SCL_DNR2_BASE + 0x77) ++#define REG_SCL_DNR2_3C_L (REG_SCL_DNR2_BASE + 0x78) ++#define REG_SCL_DNR2_3C_H (REG_SCL_DNR2_BASE + 0x79) ++#define REG_SCL_DNR2_3D_L (REG_SCL_DNR2_BASE + 0x7A) ++#define REG_SCL_DNR2_3D_H (REG_SCL_DNR2_BASE + 0x7B) ++#define REG_SCL_DNR2_3E_L (REG_SCL_DNR2_BASE + 0x7C) ++#define REG_SCL_DNR2_3E_H (REG_SCL_DNR2_BASE + 0x7D) ++#define REG_SCL_DNR2_3F_L (REG_SCL_DNR2_BASE + 0x7E) ++#define REG_SCL_DNR2_3F_H (REG_SCL_DNR2_BASE + 0x7F) ++#define REG_SCL_DNR2_40_L (REG_SCL_DNR2_BASE + 0x80) ++#define REG_SCL_DNR2_40_H (REG_SCL_DNR2_BASE + 0x81) ++#define REG_SCL_DNR2_41_L (REG_SCL_DNR2_BASE + 0x82) ++#define REG_SCL_DNR2_41_H (REG_SCL_DNR2_BASE + 0x83) ++#define REG_SCL_DNR2_42_L (REG_SCL_DNR2_BASE + 0x84) ++#define REG_SCL_DNR2_42_H (REG_SCL_DNR2_BASE + 0x85) ++#define REG_SCL_DNR2_43_L (REG_SCL_DNR2_BASE + 0x86) ++#define REG_SCL_DNR2_43_H (REG_SCL_DNR2_BASE + 0x87) ++#define REG_SCL_DNR2_44_L (REG_SCL_DNR2_BASE + 0x88) ++#define REG_SCL_DNR2_44_H (REG_SCL_DNR2_BASE + 0x89) ++#define REG_SCL_DNR2_45_L (REG_SCL_DNR2_BASE + 0x8A) ++#define REG_SCL_DNR2_45_H (REG_SCL_DNR2_BASE + 0x8B) ++#define REG_SCL_DNR2_46_L (REG_SCL_DNR2_BASE + 0x8C) ++#define REG_SCL_DNR2_46_H (REG_SCL_DNR2_BASE + 0x8D) ++#define REG_SCL_DNR2_47_L (REG_SCL_DNR2_BASE + 0x8E) ++#define REG_SCL_DNR2_47_H (REG_SCL_DNR2_BASE + 0x8F) ++#define REG_SCL_DNR2_48_L (REG_SCL_DNR2_BASE + 0x90) ++#define REG_SCL_DNR2_48_H (REG_SCL_DNR2_BASE + 0x91) ++#define REG_SCL_DNR2_49_L (REG_SCL_DNR2_BASE + 0x92) ++#define REG_SCL_DNR2_49_H (REG_SCL_DNR2_BASE + 0x93) ++#define REG_SCL_DNR2_4A_L (REG_SCL_DNR2_BASE + 0x94) ++#define REG_SCL_DNR2_4A_H (REG_SCL_DNR2_BASE + 0x95) ++#define REG_SCL_DNR2_4B_L (REG_SCL_DNR2_BASE + 0x96) ++#define REG_SCL_DNR2_4B_H (REG_SCL_DNR2_BASE + 0x97) ++#define REG_SCL_DNR2_4C_L (REG_SCL_DNR2_BASE + 0x98) ++#define REG_SCL_DNR2_4C_H (REG_SCL_DNR2_BASE + 0x99) ++#define REG_SCL_DNR2_4D_L (REG_SCL_DNR2_BASE + 0x9A) ++#define REG_SCL_DNR2_4D_H (REG_SCL_DNR2_BASE + 0x9B) ++#define REG_SCL_DNR2_4E_L (REG_SCL_DNR2_BASE + 0x9C) ++#define REG_SCL_DNR2_4E_H (REG_SCL_DNR2_BASE + 0x9D) ++#define REG_SCL_DNR2_4F_L (REG_SCL_DNR2_BASE + 0x9E) ++#define REG_SCL_DNR2_4F_H (REG_SCL_DNR2_BASE + 0x9F) ++#define REG_SCL_DNR2_50_L (REG_SCL_DNR2_BASE + 0xA0) ++#define REG_SCL_DNR2_50_H (REG_SCL_DNR2_BASE + 0xA1) ++#define REG_SCL_DNR2_51_L (REG_SCL_DNR2_BASE + 0xA2) ++#define REG_SCL_DNR2_51_H (REG_SCL_DNR2_BASE + 0xA3) ++#define REG_SCL_DNR2_52_L (REG_SCL_DNR2_BASE + 0xA4) ++#define REG_SCL_DNR2_52_H (REG_SCL_DNR2_BASE + 0xA5) ++#define REG_SCL_DNR2_53_L (REG_SCL_DNR2_BASE + 0xA6) ++#define REG_SCL_DNR2_53_H (REG_SCL_DNR2_BASE + 0xA7) ++#define REG_SCL_DNR2_54_L (REG_SCL_DNR2_BASE + 0xA8) ++#define REG_SCL_DNR2_54_H (REG_SCL_DNR2_BASE + 0xA9) ++#define REG_SCL_DNR2_55_L (REG_SCL_DNR2_BASE + 0xAA) ++#define REG_SCL_DNR2_55_H (REG_SCL_DNR2_BASE + 0xAB) ++#define REG_SCL_DNR2_56_L (REG_SCL_DNR2_BASE + 0xAC) ++#define REG_SCL_DNR2_56_H (REG_SCL_DNR2_BASE + 0xAD) ++#define REG_SCL_DNR2_57_L (REG_SCL_DNR2_BASE + 0xAE) ++#define REG_SCL_DNR2_57_H (REG_SCL_DNR2_BASE + 0xAF) ++#define REG_SCL_DNR2_58_L (REG_SCL_DNR2_BASE + 0xB0) ++#define REG_SCL_DNR2_58_H (REG_SCL_DNR2_BASE + 0xB1) ++#define REG_SCL_DNR2_59_L (REG_SCL_DNR2_BASE + 0xB2) ++#define REG_SCL_DNR2_59_H (REG_SCL_DNR2_BASE + 0xB3) ++#define REG_SCL_DNR2_5A_L (REG_SCL_DNR2_BASE + 0xB4) ++#define REG_SCL_DNR2_5A_H (REG_SCL_DNR2_BASE + 0xB5) ++#define REG_SCL_DNR2_5B_L (REG_SCL_DNR2_BASE + 0xB6) ++#define REG_SCL_DNR2_5B_H (REG_SCL_DNR2_BASE + 0xB7) ++#define REG_SCL_DNR2_5C_L (REG_SCL_DNR2_BASE + 0xB8) ++#define REG_SCL_DNR2_5C_H (REG_SCL_DNR2_BASE + 0xB9) ++#define REG_SCL_DNR2_5D_L (REG_SCL_DNR2_BASE + 0xBA) ++#define REG_SCL_DNR2_5D_H (REG_SCL_DNR2_BASE + 0xBB) ++#define REG_SCL_DNR2_5E_L (REG_SCL_DNR2_BASE + 0xBC) ++#define REG_SCL_DNR2_5E_H (REG_SCL_DNR2_BASE + 0xBD) ++#define REG_SCL_DNR2_5F_L (REG_SCL_DNR2_BASE + 0xBE) ++#define REG_SCL_DNR2_5F_H (REG_SCL_DNR2_BASE + 0xBF) ++#define REG_SCL_DNR2_60_L (REG_SCL_DNR2_BASE + 0xC0) ++#define REG_SCL_DNR2_60_H (REG_SCL_DNR2_BASE + 0xC1) ++#define REG_SCL_DNR2_61_L (REG_SCL_DNR2_BASE + 0xC2) ++#define REG_SCL_DNR2_61_H (REG_SCL_DNR2_BASE + 0xC3) ++#define REG_SCL_DNR2_62_L (REG_SCL_DNR2_BASE + 0xC4) ++#define REG_SCL_DNR2_62_H (REG_SCL_DNR2_BASE + 0xC5) ++#define REG_SCL_DNR2_63_L (REG_SCL_DNR2_BASE + 0xC6) ++#define REG_SCL_DNR2_63_H (REG_SCL_DNR2_BASE + 0xC7) ++#define REG_SCL_DNR2_64_L (REG_SCL_DNR2_BASE + 0xC8) ++#define REG_SCL_DNR2_64_H (REG_SCL_DNR2_BASE + 0xC9) ++#define REG_SCL_DNR2_65_L (REG_SCL_DNR2_BASE + 0xCA) ++#define REG_SCL_DNR2_65_H (REG_SCL_DNR2_BASE + 0xCB) ++#define REG_SCL_DNR2_66_L (REG_SCL_DNR2_BASE + 0xCC) ++#define REG_SCL_DNR2_66_H (REG_SCL_DNR2_BASE + 0xCD) ++#define REG_SCL_DNR2_67_L (REG_SCL_DNR2_BASE + 0xCE) ++#define REG_SCL_DNR2_67_H (REG_SCL_DNR2_BASE + 0xCF) ++#define REG_SCL_DNR2_68_L (REG_SCL_DNR2_BASE + 0xD0) ++#define REG_SCL_DNR2_68_H (REG_SCL_DNR2_BASE + 0xD1) ++#define REG_SCL_DNR2_69_L (REG_SCL_DNR2_BASE + 0xD2) ++#define REG_SCL_DNR2_69_H (REG_SCL_DNR2_BASE + 0xD3) ++#define REG_SCL_DNR2_6A_L (REG_SCL_DNR2_BASE + 0xD4) ++#define REG_SCL_DNR2_6A_H (REG_SCL_DNR2_BASE + 0xD5) ++#define REG_SCL_DNR2_6B_L (REG_SCL_DNR2_BASE + 0xD6) ++#define REG_SCL_DNR2_6B_H (REG_SCL_DNR2_BASE + 0xD7) ++#define REG_SCL_DNR2_6C_L (REG_SCL_DNR2_BASE + 0xD8) ++#define REG_SCL_DNR2_6C_H (REG_SCL_DNR2_BASE + 0xD9) ++#define REG_SCL_DNR2_6D_L (REG_SCL_DNR2_BASE + 0xDA) ++#define REG_SCL_DNR2_6D_H (REG_SCL_DNR2_BASE + 0xDB) ++#define REG_SCL_DNR2_6E_L (REG_SCL_DNR2_BASE + 0xDC) ++#define REG_SCL_DNR2_6E_H (REG_SCL_DNR2_BASE + 0xDD) ++#define REG_SCL_DNR2_6F_L (REG_SCL_DNR2_BASE + 0xDE) ++#define REG_SCL_DNR2_6F_H (REG_SCL_DNR2_BASE + 0xDF) ++#define REG_SCL_DNR2_70_L (REG_SCL_DNR2_BASE + 0xE0) ++#define REG_SCL_DNR2_70_H (REG_SCL_DNR2_BASE + 0xE1) ++#define REG_SCL_DNR2_71_L (REG_SCL_DNR2_BASE + 0xE2) ++#define REG_SCL_DNR2_71_H (REG_SCL_DNR2_BASE + 0xE3) ++#define REG_SCL_DNR2_72_L (REG_SCL_DNR2_BASE + 0xE4) ++#define REG_SCL_DNR2_72_H (REG_SCL_DNR2_BASE + 0xE5) ++#define REG_SCL_DNR2_73_L (REG_SCL_DNR2_BASE + 0xE6) ++#define REG_SCL_DNR2_73_H (REG_SCL_DNR2_BASE + 0xE7) ++#define REG_SCL_DNR2_74_L (REG_SCL_DNR2_BASE + 0xE8) ++#define REG_SCL_DNR2_74_H (REG_SCL_DNR2_BASE + 0xE9) ++#define REG_SCL_DNR2_75_L (REG_SCL_DNR2_BASE + 0xEA) ++#define REG_SCL_DNR2_75_H (REG_SCL_DNR2_BASE + 0xEB) ++#define REG_SCL_DNR2_76_L (REG_SCL_DNR2_BASE + 0xEC) ++#define REG_SCL_DNR2_76_H (REG_SCL_DNR2_BASE + 0xED) ++#define REG_SCL_DNR2_77_L (REG_SCL_DNR2_BASE + 0xEE) ++#define REG_SCL_DNR2_77_H (REG_SCL_DNR2_BASE + 0xEF) ++#define REG_SCL_DNR2_78_L (REG_SCL_DNR2_BASE + 0xF0) ++#define REG_SCL_DNR2_78_H (REG_SCL_DNR2_BASE + 0xF1) ++#define REG_SCL_DNR2_79_L (REG_SCL_DNR2_BASE + 0xF2) ++#define REG_SCL_DNR2_79_H (REG_SCL_DNR2_BASE + 0xF3) ++#define REG_SCL_DNR2_7A_L (REG_SCL_DNR2_BASE + 0xF4) ++#define REG_SCL_DNR2_7A_H (REG_SCL_DNR2_BASE + 0xF5) ++#define REG_SCL_DNR2_7B_L (REG_SCL_DNR2_BASE + 0xF6) ++#define REG_SCL_DNR2_7B_H (REG_SCL_DNR2_BASE + 0xF7) ++#define REG_SCL_DNR2_7C_L (REG_SCL_DNR2_BASE + 0xF8) ++#define REG_SCL_DNR2_7C_H (REG_SCL_DNR2_BASE + 0xF9) ++#define REG_SCL_DNR2_7D_L (REG_SCL_DNR2_BASE + 0xFA) ++#define REG_SCL_DNR2_7D_H (REG_SCL_DNR2_BASE + 0xFB) ++#define REG_SCL_DNR2_7E_L (REG_SCL_DNR2_BASE + 0xFC) ++#define REG_SCL_DNR2_7E_H (REG_SCL_DNR2_BASE + 0xFD) ++#define REG_SCL_DNR2_7F_L (REG_SCL_DNR2_BASE + 0xFE) ++#define REG_SCL_DNR2_7F_H (REG_SCL_DNR2_BASE + 0xFF) ++ ++#define REG_SCL_NLM0_00_L (REG_SCL_NLM0_BASE + 0x00) ++#define REG_SCL_NLM0_00_H (REG_SCL_NLM0_BASE + 0x01) ++#define REG_SCL_NLM0_01_L (REG_SCL_NLM0_BASE + 0x02) ++#define REG_SCL_NLM0_01_H (REG_SCL_NLM0_BASE + 0x03) ++#define REG_SCL_NLM0_02_L (REG_SCL_NLM0_BASE + 0x04) ++#define REG_SCL_NLM0_02_H (REG_SCL_NLM0_BASE + 0x05) ++#define REG_SCL_NLM0_03_L (REG_SCL_NLM0_BASE + 0x06) ++#define REG_SCL_NLM0_03_H (REG_SCL_NLM0_BASE + 0x07) ++#define REG_SCL_NLM0_04_L (REG_SCL_NLM0_BASE + 0x08) ++#define REG_SCL_NLM0_04_H (REG_SCL_NLM0_BASE + 0x09) ++#define REG_SCL_NLM0_05_L (REG_SCL_NLM0_BASE + 0x0A) ++#define REG_SCL_NLM0_05_H (REG_SCL_NLM0_BASE + 0x0B) ++#define REG_SCL_NLM0_06_L (REG_SCL_NLM0_BASE + 0x0C) ++#define REG_SCL_NLM0_06_H (REG_SCL_NLM0_BASE + 0x0D) ++#define REG_SCL_NLM0_07_L (REG_SCL_NLM0_BASE + 0x0E) ++#define REG_SCL_NLM0_07_H (REG_SCL_NLM0_BASE + 0x0F) ++#define REG_SCL_NLM0_08_L (REG_SCL_NLM0_BASE + 0x10) ++#define REG_SCL_NLM0_08_H (REG_SCL_NLM0_BASE + 0x11) ++#define REG_SCL_NLM0_09_L (REG_SCL_NLM0_BASE + 0x12) ++#define REG_SCL_NLM0_09_H (REG_SCL_NLM0_BASE + 0x13) ++#define REG_SCL_NLM0_0A_L (REG_SCL_NLM0_BASE + 0x14) ++#define REG_SCL_NLM0_0A_H (REG_SCL_NLM0_BASE + 0x15) ++#define REG_SCL_NLM0_0B_L (REG_SCL_NLM0_BASE + 0x16) ++#define REG_SCL_NLM0_0B_H (REG_SCL_NLM0_BASE + 0x17) ++#define REG_SCL_NLM0_0C_L (REG_SCL_NLM0_BASE + 0x18) ++#define REG_SCL_NLM0_0C_H (REG_SCL_NLM0_BASE + 0x19) ++#define REG_SCL_NLM0_0D_L (REG_SCL_NLM0_BASE + 0x1A) ++#define REG_SCL_NLM0_0D_H (REG_SCL_NLM0_BASE + 0x1B) ++#define REG_SCL_NLM0_0E_L (REG_SCL_NLM0_BASE + 0x1C) ++#define REG_SCL_NLM0_0E_H (REG_SCL_NLM0_BASE + 0x1D) ++#define REG_SCL_NLM0_0F_L (REG_SCL_NLM0_BASE + 0x1E) ++#define REG_SCL_NLM0_0F_H (REG_SCL_NLM0_BASE + 0x1F) ++#define REG_SCL_NLM0_10_L (REG_SCL_NLM0_BASE + 0x20) ++#define REG_SCL_NLM0_10_H (REG_SCL_NLM0_BASE + 0x21) ++#define REG_SCL_NLM0_11_L (REG_SCL_NLM0_BASE + 0x22) ++#define REG_SCL_NLM0_11_H (REG_SCL_NLM0_BASE + 0x23) ++#define REG_SCL_NLM0_12_L (REG_SCL_NLM0_BASE + 0x24) ++#define REG_SCL_NLM0_12_H (REG_SCL_NLM0_BASE + 0x25) ++#define REG_SCL_NLM0_13_L (REG_SCL_NLM0_BASE + 0x26) ++#define REG_SCL_NLM0_13_H (REG_SCL_NLM0_BASE + 0x27) ++#define REG_SCL_NLM0_14_L (REG_SCL_NLM0_BASE + 0x28) ++#define REG_SCL_NLM0_14_H (REG_SCL_NLM0_BASE + 0x29) ++#define REG_SCL_NLM0_15_L (REG_SCL_NLM0_BASE + 0x2A) ++#define REG_SCL_NLM0_15_H (REG_SCL_NLM0_BASE + 0x2B) ++#define REG_SCL_NLM0_16_L (REG_SCL_NLM0_BASE + 0x2C) ++#define REG_SCL_NLM0_16_H (REG_SCL_NLM0_BASE + 0x2D) ++#define REG_SCL_NLM0_17_L (REG_SCL_NLM0_BASE + 0x2E) ++#define REG_SCL_NLM0_17_H (REG_SCL_NLM0_BASE + 0x2F) ++#define REG_SCL_NLM0_18_L (REG_SCL_NLM0_BASE + 0x30) ++#define REG_SCL_NLM0_18_H (REG_SCL_NLM0_BASE + 0x31) ++#define REG_SCL_NLM0_19_L (REG_SCL_NLM0_BASE + 0x32) ++#define REG_SCL_NLM0_19_H (REG_SCL_NLM0_BASE + 0x33) ++#define REG_SCL_NLM0_1A_L (REG_SCL_NLM0_BASE + 0x34) ++#define REG_SCL_NLM0_1A_H (REG_SCL_NLM0_BASE + 0x35) ++#define REG_SCL_NLM0_1B_L (REG_SCL_NLM0_BASE + 0x36) ++#define REG_SCL_NLM0_1B_H (REG_SCL_NLM0_BASE + 0x37) ++#define REG_SCL_NLM0_1C_L (REG_SCL_NLM0_BASE + 0x38) ++#define REG_SCL_NLM0_1C_H (REG_SCL_NLM0_BASE + 0x39) ++#define REG_SCL_NLM0_1D_L (REG_SCL_NLM0_BASE + 0x3A) ++#define REG_SCL_NLM0_1D_H (REG_SCL_NLM0_BASE + 0x3B) ++#define REG_SCL_NLM0_1E_L (REG_SCL_NLM0_BASE + 0x3C) ++#define REG_SCL_NLM0_1E_H (REG_SCL_NLM0_BASE + 0x3D) ++#define REG_SCL_NLM0_1F_L (REG_SCL_NLM0_BASE + 0x3E) ++#define REG_SCL_NLM0_1F_H (REG_SCL_NLM0_BASE + 0x3F) ++#define REG_SCL_NLM0_20_L (REG_SCL_NLM0_BASE + 0x40) ++#define REG_SCL_NLM0_20_H (REG_SCL_NLM0_BASE + 0x41) ++#define REG_SCL_NLM0_21_L (REG_SCL_NLM0_BASE + 0x42) ++#define REG_SCL_NLM0_21_H (REG_SCL_NLM0_BASE + 0x43) ++#define REG_SCL_NLM0_22_L (REG_SCL_NLM0_BASE + 0x44) ++#define REG_SCL_NLM0_22_H (REG_SCL_NLM0_BASE + 0x45) ++#define REG_SCL_NLM0_23_L (REG_SCL_NLM0_BASE + 0x46) ++#define REG_SCL_NLM0_23_H (REG_SCL_NLM0_BASE + 0x47) ++#define REG_SCL_NLM0_24_L (REG_SCL_NLM0_BASE + 0x48) ++#define REG_SCL_NLM0_24_H (REG_SCL_NLM0_BASE + 0x49) ++#define REG_SCL_NLM0_25_L (REG_SCL_NLM0_BASE + 0x4A) ++#define REG_SCL_NLM0_25_H (REG_SCL_NLM0_BASE + 0x4B) ++#define REG_SCL_NLM0_26_L (REG_SCL_NLM0_BASE + 0x4C) ++#define REG_SCL_NLM0_26_H (REG_SCL_NLM0_BASE + 0x4D) ++#define REG_SCL_NLM0_27_L (REG_SCL_NLM0_BASE + 0x4E) ++#define REG_SCL_NLM0_27_H (REG_SCL_NLM0_BASE + 0x4F) ++#define REG_SCL_NLM0_28_L (REG_SCL_NLM0_BASE + 0x50) ++#define REG_SCL_NLM0_28_H (REG_SCL_NLM0_BASE + 0x51) ++#define REG_SCL_NLM0_29_L (REG_SCL_NLM0_BASE + 0x52) ++#define REG_SCL_NLM0_29_H (REG_SCL_NLM0_BASE + 0x53) ++#define REG_SCL_NLM0_2A_L (REG_SCL_NLM0_BASE + 0x54) ++#define REG_SCL_NLM0_2A_H (REG_SCL_NLM0_BASE + 0x55) ++#define REG_SCL_NLM0_2B_L (REG_SCL_NLM0_BASE + 0x56) ++#define REG_SCL_NLM0_2B_H (REG_SCL_NLM0_BASE + 0x57) ++#define REG_SCL_NLM0_2C_L (REG_SCL_NLM0_BASE + 0x58) ++#define REG_SCL_NLM0_2C_H (REG_SCL_NLM0_BASE + 0x59) ++#define REG_SCL_NLM0_2D_L (REG_SCL_NLM0_BASE + 0x5A) ++#define REG_SCL_NLM0_2D_H (REG_SCL_NLM0_BASE + 0x5B) ++#define REG_SCL_NLM0_2E_L (REG_SCL_NLM0_BASE + 0x5C) ++#define REG_SCL_NLM0_2E_H (REG_SCL_NLM0_BASE + 0x5D) ++#define REG_SCL_NLM0_2F_L (REG_SCL_NLM0_BASE + 0x5E) ++#define REG_SCL_NLM0_2F_H (REG_SCL_NLM0_BASE + 0x5F) ++#define REG_SCL_NLM0_30_L (REG_SCL_NLM0_BASE + 0x60) ++#define REG_SCL_NLM0_30_H (REG_SCL_NLM0_BASE + 0x61) ++#define REG_SCL_NLM0_31_L (REG_SCL_NLM0_BASE + 0x62) ++#define REG_SCL_NLM0_31_H (REG_SCL_NLM0_BASE + 0x63) ++#define REG_SCL_NLM0_32_L (REG_SCL_NLM0_BASE + 0x64) ++#define REG_SCL_NLM0_32_H (REG_SCL_NLM0_BASE + 0x65) ++#define REG_SCL_NLM0_33_L (REG_SCL_NLM0_BASE + 0x66) ++#define REG_SCL_NLM0_33_H (REG_SCL_NLM0_BASE + 0x67) ++#define REG_SCL_NLM0_34_L (REG_SCL_NLM0_BASE + 0x68) ++#define REG_SCL_NLM0_34_H (REG_SCL_NLM0_BASE + 0x69) ++#define REG_SCL_NLM0_35_L (REG_SCL_NLM0_BASE + 0x6A) ++#define REG_SCL_NLM0_35_H (REG_SCL_NLM0_BASE + 0x6B) ++#define REG_SCL_NLM0_36_L (REG_SCL_NLM0_BASE + 0x6C) ++#define REG_SCL_NLM0_36_H (REG_SCL_NLM0_BASE + 0x6D) ++#define REG_SCL_NLM0_37_L (REG_SCL_NLM0_BASE + 0x6E) ++#define REG_SCL_NLM0_37_H (REG_SCL_NLM0_BASE + 0x6F) ++#define REG_SCL_NLM0_38_L (REG_SCL_NLM0_BASE + 0x70) ++#define REG_SCL_NLM0_38_H (REG_SCL_NLM0_BASE + 0x71) ++#define REG_SCL_NLM0_39_L (REG_SCL_NLM0_BASE + 0x72) ++#define REG_SCL_NLM0_39_H (REG_SCL_NLM0_BASE + 0x73) ++#define REG_SCL_NLM0_3A_L (REG_SCL_NLM0_BASE + 0x74) ++#define REG_SCL_NLM0_3A_H (REG_SCL_NLM0_BASE + 0x75) ++#define REG_SCL_NLM0_3B_L (REG_SCL_NLM0_BASE + 0x76) ++#define REG_SCL_NLM0_3B_H (REG_SCL_NLM0_BASE + 0x77) ++#define REG_SCL_NLM0_3C_L (REG_SCL_NLM0_BASE + 0x78) ++#define REG_SCL_NLM0_3C_H (REG_SCL_NLM0_BASE + 0x79) ++#define REG_SCL_NLM0_3D_L (REG_SCL_NLM0_BASE + 0x7A) ++#define REG_SCL_NLM0_3D_H (REG_SCL_NLM0_BASE + 0x7B) ++#define REG_SCL_NLM0_3E_L (REG_SCL_NLM0_BASE + 0x7C) ++#define REG_SCL_NLM0_3E_H (REG_SCL_NLM0_BASE + 0x7D) ++#define REG_SCL_NLM0_3F_L (REG_SCL_NLM0_BASE + 0x7E) ++#define REG_SCL_NLM0_3F_H (REG_SCL_NLM0_BASE + 0x7F) ++#define REG_SCL_NLM0_40_L (REG_SCL_NLM0_BASE + 0x80) ++#define REG_SCL_NLM0_40_H (REG_SCL_NLM0_BASE + 0x81) ++#define REG_SCL_NLM0_41_L (REG_SCL_NLM0_BASE + 0x82) ++#define REG_SCL_NLM0_41_H (REG_SCL_NLM0_BASE + 0x83) ++#define REG_SCL_NLM0_42_L (REG_SCL_NLM0_BASE + 0x84) ++#define REG_SCL_NLM0_42_H (REG_SCL_NLM0_BASE + 0x85) ++#define REG_SCL_NLM0_43_L (REG_SCL_NLM0_BASE + 0x86) ++#define REG_SCL_NLM0_43_H (REG_SCL_NLM0_BASE + 0x87) ++#define REG_SCL_NLM0_44_L (REG_SCL_NLM0_BASE + 0x88) ++#define REG_SCL_NLM0_44_H (REG_SCL_NLM0_BASE + 0x89) ++#define REG_SCL_NLM0_45_L (REG_SCL_NLM0_BASE + 0x8A) ++#define REG_SCL_NLM0_45_H (REG_SCL_NLM0_BASE + 0x8B) ++#define REG_SCL_NLM0_46_L (REG_SCL_NLM0_BASE + 0x8C) ++#define REG_SCL_NLM0_46_H (REG_SCL_NLM0_BASE + 0x8D) ++#define REG_SCL_NLM0_47_L (REG_SCL_NLM0_BASE + 0x8E) ++#define REG_SCL_NLM0_47_H (REG_SCL_NLM0_BASE + 0x8F) ++#define REG_SCL_NLM0_48_L (REG_SCL_NLM0_BASE + 0x90) ++#define REG_SCL_NLM0_48_H (REG_SCL_NLM0_BASE + 0x91) ++#define REG_SCL_NLM0_49_L (REG_SCL_NLM0_BASE + 0x92) ++#define REG_SCL_NLM0_49_H (REG_SCL_NLM0_BASE + 0x93) ++#define REG_SCL_NLM0_4A_L (REG_SCL_NLM0_BASE + 0x94) ++#define REG_SCL_NLM0_4A_H (REG_SCL_NLM0_BASE + 0x95) ++#define REG_SCL_NLM0_4B_L (REG_SCL_NLM0_BASE + 0x96) ++#define REG_SCL_NLM0_4B_H (REG_SCL_NLM0_BASE + 0x97) ++#define REG_SCL_NLM0_4C_L (REG_SCL_NLM0_BASE + 0x98) ++#define REG_SCL_NLM0_4C_H (REG_SCL_NLM0_BASE + 0x99) ++#define REG_SCL_NLM0_4D_L (REG_SCL_NLM0_BASE + 0x9A) ++#define REG_SCL_NLM0_4D_H (REG_SCL_NLM0_BASE + 0x9B) ++#define REG_SCL_NLM0_4E_L (REG_SCL_NLM0_BASE + 0x9C) ++#define REG_SCL_NLM0_4E_H (REG_SCL_NLM0_BASE + 0x9D) ++#define REG_SCL_NLM0_4F_L (REG_SCL_NLM0_BASE + 0x9E) ++#define REG_SCL_NLM0_4F_H (REG_SCL_NLM0_BASE + 0x9F) ++#define REG_SCL_NLM0_50_L (REG_SCL_NLM0_BASE + 0xA0) ++#define REG_SCL_NLM0_50_H (REG_SCL_NLM0_BASE + 0xA1) ++#define REG_SCL_NLM0_51_L (REG_SCL_NLM0_BASE + 0xA2) ++#define REG_SCL_NLM0_51_H (REG_SCL_NLM0_BASE + 0xA3) ++#define REG_SCL_NLM0_52_L (REG_SCL_NLM0_BASE + 0xA4) ++#define REG_SCL_NLM0_52_H (REG_SCL_NLM0_BASE + 0xA5) ++#define REG_SCL_NLM0_53_L (REG_SCL_NLM0_BASE + 0xA6) ++#define REG_SCL_NLM0_53_H (REG_SCL_NLM0_BASE + 0xA7) ++#define REG_SCL_NLM0_54_L (REG_SCL_NLM0_BASE + 0xA8) ++#define REG_SCL_NLM0_54_H (REG_SCL_NLM0_BASE + 0xA9) ++#define REG_SCL_NLM0_55_L (REG_SCL_NLM0_BASE + 0xAA) ++#define REG_SCL_NLM0_55_H (REG_SCL_NLM0_BASE + 0xAB) ++#define REG_SCL_NLM0_56_L (REG_SCL_NLM0_BASE + 0xAC) ++#define REG_SCL_NLM0_56_H (REG_SCL_NLM0_BASE + 0xAD) ++#define REG_SCL_NLM0_57_L (REG_SCL_NLM0_BASE + 0xAE) ++#define REG_SCL_NLM0_57_H (REG_SCL_NLM0_BASE + 0xAF) ++#define REG_SCL_NLM0_58_L (REG_SCL_NLM0_BASE + 0xB0) ++#define REG_SCL_NLM0_58_H (REG_SCL_NLM0_BASE + 0xB1) ++#define REG_SCL_NLM0_59_L (REG_SCL_NLM0_BASE + 0xB2) ++#define REG_SCL_NLM0_59_H (REG_SCL_NLM0_BASE + 0xB3) ++#define REG_SCL_NLM0_5A_L (REG_SCL_NLM0_BASE + 0xB4) ++#define REG_SCL_NLM0_5A_H (REG_SCL_NLM0_BASE + 0xB5) ++#define REG_SCL_NLM0_5B_L (REG_SCL_NLM0_BASE + 0xB6) ++#define REG_SCL_NLM0_5B_H (REG_SCL_NLM0_BASE + 0xB7) ++#define REG_SCL_NLM0_5C_L (REG_SCL_NLM0_BASE + 0xB8) ++#define REG_SCL_NLM0_5C_H (REG_SCL_NLM0_BASE + 0xB9) ++#define REG_SCL_NLM0_5D_L (REG_SCL_NLM0_BASE + 0xBA) ++#define REG_SCL_NLM0_5D_H (REG_SCL_NLM0_BASE + 0xBB) ++#define REG_SCL_NLM0_5E_L (REG_SCL_NLM0_BASE + 0xBC) ++#define REG_SCL_NLM0_5E_H (REG_SCL_NLM0_BASE + 0xBD) ++#define REG_SCL_NLM0_5F_L (REG_SCL_NLM0_BASE + 0xBE) ++#define REG_SCL_NLM0_5F_H (REG_SCL_NLM0_BASE + 0xBF) ++#define REG_SCL_NLM0_60_L (REG_SCL_NLM0_BASE + 0xC0) ++#define REG_SCL_NLM0_60_H (REG_SCL_NLM0_BASE + 0xC1) ++#define REG_SCL_NLM0_61_L (REG_SCL_NLM0_BASE + 0xC2) ++#define REG_SCL_NLM0_61_H (REG_SCL_NLM0_BASE + 0xC3) ++#define REG_SCL_NLM0_62_L (REG_SCL_NLM0_BASE + 0xC4) ++#define REG_SCL_NLM0_62_H (REG_SCL_NLM0_BASE + 0xC5) ++#define REG_SCL_NLM0_63_L (REG_SCL_NLM0_BASE + 0xC6) ++#define REG_SCL_NLM0_63_H (REG_SCL_NLM0_BASE + 0xC7) ++#define REG_SCL_NLM0_64_L (REG_SCL_NLM0_BASE + 0xC8) ++#define REG_SCL_NLM0_64_H (REG_SCL_NLM0_BASE + 0xC9) ++#define REG_SCL_NLM0_65_L (REG_SCL_NLM0_BASE + 0xCA) ++#define REG_SCL_NLM0_65_H (REG_SCL_NLM0_BASE + 0xCB) ++#define REG_SCL_NLM0_66_L (REG_SCL_NLM0_BASE + 0xCC) ++#define REG_SCL_NLM0_66_H (REG_SCL_NLM0_BASE + 0xCD) ++#define REG_SCL_NLM0_67_L (REG_SCL_NLM0_BASE + 0xCE) ++#define REG_SCL_NLM0_67_H (REG_SCL_NLM0_BASE + 0xCF) ++#define REG_SCL_NLM0_68_L (REG_SCL_NLM0_BASE + 0xD0) ++#define REG_SCL_NLM0_68_H (REG_SCL_NLM0_BASE + 0xD1) ++#define REG_SCL_NLM0_69_L (REG_SCL_NLM0_BASE + 0xD2) ++#define REG_SCL_NLM0_69_H (REG_SCL_NLM0_BASE + 0xD3) ++#define REG_SCL_NLM0_6A_L (REG_SCL_NLM0_BASE + 0xD4) ++#define REG_SCL_NLM0_6A_H (REG_SCL_NLM0_BASE + 0xD5) ++#define REG_SCL_NLM0_6B_L (REG_SCL_NLM0_BASE + 0xD6) ++#define REG_SCL_NLM0_6B_H (REG_SCL_NLM0_BASE + 0xD7) ++#define REG_SCL_NLM0_6C_L (REG_SCL_NLM0_BASE + 0xD8) ++#define REG_SCL_NLM0_6C_H (REG_SCL_NLM0_BASE + 0xD9) ++#define REG_SCL_NLM0_6D_L (REG_SCL_NLM0_BASE + 0xDA) ++#define REG_SCL_NLM0_6D_H (REG_SCL_NLM0_BASE + 0xDB) ++#define REG_SCL_NLM0_6E_L (REG_SCL_NLM0_BASE + 0xDC) ++#define REG_SCL_NLM0_6E_H (REG_SCL_NLM0_BASE + 0xDD) ++#define REG_SCL_NLM0_6F_L (REG_SCL_NLM0_BASE + 0xDE) ++#define REG_SCL_NLM0_6F_H (REG_SCL_NLM0_BASE + 0xDF) ++#define REG_SCL_NLM0_70_L (REG_SCL_NLM0_BASE + 0xE0) ++#define REG_SCL_NLM0_70_H (REG_SCL_NLM0_BASE + 0xE1) ++#define REG_SCL_NLM0_71_L (REG_SCL_NLM0_BASE + 0xE2) ++#define REG_SCL_NLM0_71_H (REG_SCL_NLM0_BASE + 0xE3) ++#define REG_SCL_NLM0_72_L (REG_SCL_NLM0_BASE + 0xE4) ++#define REG_SCL_NLM0_72_H (REG_SCL_NLM0_BASE + 0xE5) ++#define REG_SCL_NLM0_73_L (REG_SCL_NLM0_BASE + 0xE6) ++#define REG_SCL_NLM0_73_H (REG_SCL_NLM0_BASE + 0xE7) ++#define REG_SCL_NLM0_74_L (REG_SCL_NLM0_BASE + 0xE8) ++#define REG_SCL_NLM0_74_H (REG_SCL_NLM0_BASE + 0xE9) ++#define REG_SCL_NLM0_75_L (REG_SCL_NLM0_BASE + 0xEA) ++#define REG_SCL_NLM0_75_H (REG_SCL_NLM0_BASE + 0xEB) ++#define REG_SCL_NLM0_76_L (REG_SCL_NLM0_BASE + 0xEC) ++#define REG_SCL_NLM0_76_H (REG_SCL_NLM0_BASE + 0xED) ++#define REG_SCL_NLM0_77_L (REG_SCL_NLM0_BASE + 0xEE) ++#define REG_SCL_NLM0_77_H (REG_SCL_NLM0_BASE + 0xEF) ++#define REG_SCL_NLM0_78_L (REG_SCL_NLM0_BASE + 0xF0) ++#define REG_SCL_NLM0_78_H (REG_SCL_NLM0_BASE + 0xF1) ++#define REG_SCL_NLM0_79_L (REG_SCL_NLM0_BASE + 0xF2) ++#define REG_SCL_NLM0_79_H (REG_SCL_NLM0_BASE + 0xF3) ++#define REG_SCL_NLM0_7A_L (REG_SCL_NLM0_BASE + 0xF4) ++#define REG_SCL_NLM0_7A_H (REG_SCL_NLM0_BASE + 0xF5) ++#define REG_SCL_NLM0_7B_L (REG_SCL_NLM0_BASE + 0xF6) ++#define REG_SCL_NLM0_7B_H (REG_SCL_NLM0_BASE + 0xF7) ++#define REG_SCL_NLM0_7C_L (REG_SCL_NLM0_BASE + 0xF8) ++#define REG_SCL_NLM0_7C_H (REG_SCL_NLM0_BASE + 0xF9) ++#define REG_SCL_NLM0_7D_L (REG_SCL_NLM0_BASE + 0xFA) ++#define REG_SCL_NLM0_7D_H (REG_SCL_NLM0_BASE + 0xFB) ++#define REG_SCL_NLM0_7E_L (REG_SCL_NLM0_BASE + 0xFC) ++#define REG_SCL_NLM0_7E_H (REG_SCL_NLM0_BASE + 0xFD) ++#define REG_SCL_NLM0_7F_L (REG_SCL_NLM0_BASE + 0xFE) ++#define REG_SCL_NLM0_7F_H (REG_SCL_NLM0_BASE + 0xFF) ++ ++#define REG_SCL0_00_L (REG_SCL0_BASE + 0x00) ++#define REG_SCL0_00_H (REG_SCL0_BASE + 0x01) ++#define REG_SCL0_01_L (REG_SCL0_BASE + 0x02) ++#define REG_SCL0_01_H (REG_SCL0_BASE + 0x03) ++#define REG_SCL0_02_L (REG_SCL0_BASE + 0x04) ++#define REG_SCL0_02_H (REG_SCL0_BASE + 0x05) ++#define REG_SCL0_03_L (REG_SCL0_BASE + 0x06) ++#define REG_SCL0_03_H (REG_SCL0_BASE + 0x07) ++#define REG_SCL0_04_L (REG_SCL0_BASE + 0x08) ++#define REG_SCL0_04_H (REG_SCL0_BASE + 0x09) ++#define REG_SCL0_05_L (REG_SCL0_BASE + 0x0A) ++#define REG_SCL0_05_H (REG_SCL0_BASE + 0x0B) ++#define REG_SCL0_06_L (REG_SCL0_BASE + 0x0C) ++#define REG_SCL0_06_H (REG_SCL0_BASE + 0x0D) ++#define REG_SCL0_07_L (REG_SCL0_BASE + 0x0E) ++#define REG_SCL0_07_H (REG_SCL0_BASE + 0x0F) ++#define REG_SCL0_08_L (REG_SCL0_BASE + 0x10) ++#define REG_SCL0_08_H (REG_SCL0_BASE + 0x11) ++#define REG_SCL0_09_L (REG_SCL0_BASE + 0x12) ++#define REG_SCL0_09_H (REG_SCL0_BASE + 0x13) ++#define REG_SCL0_0A_L (REG_SCL0_BASE + 0x14) ++#define REG_SCL0_0A_H (REG_SCL0_BASE + 0x15) ++#define REG_SCL0_0B_L (REG_SCL0_BASE + 0x16) ++#define REG_SCL0_0B_H (REG_SCL0_BASE + 0x17) ++#define REG_SCL0_0C_L (REG_SCL0_BASE + 0x18) ++#define REG_SCL0_0C_H (REG_SCL0_BASE + 0x19) ++#define REG_SCL0_0D_L (REG_SCL0_BASE + 0x1A) ++#define REG_SCL0_0D_H (REG_SCL0_BASE + 0x1B) ++#define REG_SCL0_0E_L (REG_SCL0_BASE + 0x1C) ++#define REG_SCL0_0E_H (REG_SCL0_BASE + 0x1D) ++#define REG_SCL0_0F_L (REG_SCL0_BASE + 0x1E) ++#define REG_SCL0_0F_H (REG_SCL0_BASE + 0x1F) ++#define REG_SCL0_10_L (REG_SCL0_BASE + 0x20) ++#define REG_SCL0_10_H (REG_SCL0_BASE + 0x21) ++#define REG_SCL0_11_L (REG_SCL0_BASE + 0x22) ++#define REG_SCL0_11_H (REG_SCL0_BASE + 0x23) ++#define REG_SCL0_12_L (REG_SCL0_BASE + 0x24) ++#define REG_SCL0_12_H (REG_SCL0_BASE + 0x25) ++#define REG_SCL0_13_L (REG_SCL0_BASE + 0x26) ++#define REG_SCL0_13_H (REG_SCL0_BASE + 0x27) ++#define REG_SCL0_14_L (REG_SCL0_BASE + 0x28) ++#define REG_SCL0_14_H (REG_SCL0_BASE + 0x29) ++#define REG_SCL0_15_L (REG_SCL0_BASE + 0x2A) ++#define REG_SCL0_15_H (REG_SCL0_BASE + 0x2B) ++#define REG_SCL0_16_L (REG_SCL0_BASE + 0x2C) ++#define REG_SCL0_16_H (REG_SCL0_BASE + 0x2D) ++#define REG_SCL0_17_L (REG_SCL0_BASE + 0x2E) ++#define REG_SCL0_17_H (REG_SCL0_BASE + 0x2F) ++#define REG_SCL0_18_L (REG_SCL0_BASE + 0x30) ++#define REG_SCL0_18_H (REG_SCL0_BASE + 0x31) ++#define REG_SCL0_19_L (REG_SCL0_BASE + 0x32) ++#define REG_SCL0_19_H (REG_SCL0_BASE + 0x33) ++#define REG_SCL0_1A_L (REG_SCL0_BASE + 0x34) ++#define REG_SCL0_1A_H (REG_SCL0_BASE + 0x35) ++#define REG_SCL0_1B_L (REG_SCL0_BASE + 0x36) ++#define REG_SCL0_1B_H (REG_SCL0_BASE + 0x37) ++#define REG_SCL0_1C_L (REG_SCL0_BASE + 0x38) ++#define REG_SCL0_1C_H (REG_SCL0_BASE + 0x39) ++#define REG_SCL0_1D_L (REG_SCL0_BASE + 0x3A) ++#define REG_SCL0_1D_H (REG_SCL0_BASE + 0x3B) ++#define REG_SCL0_1E_L (REG_SCL0_BASE + 0x3C) ++#define REG_SCL0_1E_H (REG_SCL0_BASE + 0x3D) ++#define REG_SCL0_1F_L (REG_SCL0_BASE + 0x3E) ++#define REG_SCL0_1F_H (REG_SCL0_BASE + 0x3F) ++#define REG_SCL0_20_L (REG_SCL0_BASE + 0x40) ++#define REG_SCL0_20_H (REG_SCL0_BASE + 0x41) ++#define REG_SCL0_21_L (REG_SCL0_BASE + 0x42) ++#define REG_SCL0_21_H (REG_SCL0_BASE + 0x43) ++#define REG_SCL0_22_L (REG_SCL0_BASE + 0x44) ++#define REG_SCL0_22_H (REG_SCL0_BASE + 0x45) ++#define REG_SCL0_23_L (REG_SCL0_BASE + 0x46) ++#define REG_SCL0_23_H (REG_SCL0_BASE + 0x47) ++#define REG_SCL0_24_L (REG_SCL0_BASE + 0x48) ++#define REG_SCL0_24_H (REG_SCL0_BASE + 0x49) ++#define REG_SCL0_25_L (REG_SCL0_BASE + 0x4A) ++#define REG_SCL0_25_H (REG_SCL0_BASE + 0x4B) ++#define REG_SCL0_26_L (REG_SCL0_BASE + 0x4C) ++#define REG_SCL0_26_H (REG_SCL0_BASE + 0x4D) ++#define REG_SCL0_27_L (REG_SCL0_BASE + 0x4E) ++#define REG_SCL0_27_H (REG_SCL0_BASE + 0x4F) ++#define REG_SCL0_28_L (REG_SCL0_BASE + 0x50) ++#define REG_SCL0_28_H (REG_SCL0_BASE + 0x51) ++#define REG_SCL0_29_L (REG_SCL0_BASE + 0x52) ++#define REG_SCL0_29_H (REG_SCL0_BASE + 0x53) ++#define REG_SCL0_2A_L (REG_SCL0_BASE + 0x54) ++#define REG_SCL0_2A_H (REG_SCL0_BASE + 0x55) ++#define REG_SCL0_2B_L (REG_SCL0_BASE + 0x56) ++#define REG_SCL0_2B_H (REG_SCL0_BASE + 0x57) ++#define REG_SCL0_2C_L (REG_SCL0_BASE + 0x58) ++#define REG_SCL0_2C_H (REG_SCL0_BASE + 0x59) ++#define REG_SCL0_2D_L (REG_SCL0_BASE + 0x5A) ++#define REG_SCL0_2D_H (REG_SCL0_BASE + 0x5B) ++#define REG_SCL0_2E_L (REG_SCL0_BASE + 0x5C) ++#define REG_SCL0_2E_H (REG_SCL0_BASE + 0x5D) ++#define REG_SCL0_2F_L (REG_SCL0_BASE + 0x5E) ++#define REG_SCL0_2F_H (REG_SCL0_BASE + 0x5F) ++#define REG_SCL0_30_L (REG_SCL0_BASE + 0x60) ++#define REG_SCL0_30_H (REG_SCL0_BASE + 0x61) ++#define REG_SCL0_31_L (REG_SCL0_BASE + 0x62) ++#define REG_SCL0_31_H (REG_SCL0_BASE + 0x63) ++#define REG_SCL0_32_L (REG_SCL0_BASE + 0x64) ++#define REG_SCL0_32_H (REG_SCL0_BASE + 0x65) ++#define REG_SCL0_33_L (REG_SCL0_BASE + 0x66) ++#define REG_SCL0_33_H (REG_SCL0_BASE + 0x67) ++#define REG_SCL0_34_L (REG_SCL0_BASE + 0x68) ++#define REG_SCL0_34_H (REG_SCL0_BASE + 0x69) ++#define REG_SCL0_35_L (REG_SCL0_BASE + 0x6A) ++#define REG_SCL0_35_H (REG_SCL0_BASE + 0x6B) ++#define REG_SCL0_36_L (REG_SCL0_BASE + 0x6C) ++#define REG_SCL0_36_H (REG_SCL0_BASE + 0x6D) ++#define REG_SCL0_37_L (REG_SCL0_BASE + 0x6E) ++#define REG_SCL0_37_H (REG_SCL0_BASE + 0x6F) ++#define REG_SCL0_38_L (REG_SCL0_BASE + 0x70) ++#define REG_SCL0_38_H (REG_SCL0_BASE + 0x71) ++#define REG_SCL0_39_L (REG_SCL0_BASE + 0x72) ++#define REG_SCL0_39_H (REG_SCL0_BASE + 0x73) ++#define REG_SCL0_3A_L (REG_SCL0_BASE + 0x74) ++#define REG_SCL0_3A_H (REG_SCL0_BASE + 0x75) ++#define REG_SCL0_3B_L (REG_SCL0_BASE + 0x76) ++#define REG_SCL0_3B_H (REG_SCL0_BASE + 0x77) ++#define REG_SCL0_3C_L (REG_SCL0_BASE + 0x78) ++#define REG_SCL0_3C_H (REG_SCL0_BASE + 0x79) ++#define REG_SCL0_3D_L (REG_SCL0_BASE + 0x7A) ++#define REG_SCL0_3D_H (REG_SCL0_BASE + 0x7B) ++#define REG_SCL0_3E_L (REG_SCL0_BASE + 0x7C) ++#define REG_SCL0_3E_H (REG_SCL0_BASE + 0x7D) ++#define REG_SCL0_3F_L (REG_SCL0_BASE + 0x7E) ++#define REG_SCL0_3F_H (REG_SCL0_BASE + 0x7F) ++#define REG_SCL0_40_L (REG_SCL0_BASE + 0x80) ++#define REG_SCL0_40_H (REG_SCL0_BASE + 0x81) ++#define REG_SCL0_41_L (REG_SCL0_BASE + 0x82) ++#define REG_SCL0_41_H (REG_SCL0_BASE + 0x83) ++#define REG_SCL0_42_L (REG_SCL0_BASE + 0x84) ++#define REG_SCL0_42_H (REG_SCL0_BASE + 0x85) ++#define REG_SCL0_43_L (REG_SCL0_BASE + 0x86) ++#define REG_SCL0_43_H (REG_SCL0_BASE + 0x87) ++#define REG_SCL0_44_L (REG_SCL0_BASE + 0x88) ++#define REG_SCL0_44_H (REG_SCL0_BASE + 0x89) ++#define REG_SCL0_45_L (REG_SCL0_BASE + 0x8A) ++#define REG_SCL0_45_H (REG_SCL0_BASE + 0x8B) ++#define REG_SCL0_46_L (REG_SCL0_BASE + 0x8C) ++#define REG_SCL0_46_H (REG_SCL0_BASE + 0x8D) ++#define REG_SCL0_47_L (REG_SCL0_BASE + 0x8E) ++#define REG_SCL0_47_H (REG_SCL0_BASE + 0x8F) ++#define REG_SCL0_48_L (REG_SCL0_BASE + 0x90) ++#define REG_SCL0_48_H (REG_SCL0_BASE + 0x91) ++#define REG_SCL0_49_L (REG_SCL0_BASE + 0x92) ++#define REG_SCL0_49_H (REG_SCL0_BASE + 0x93) ++#define REG_SCL0_4A_L (REG_SCL0_BASE + 0x94) ++#define REG_SCL0_4A_H (REG_SCL0_BASE + 0x95) ++#define REG_SCL0_4B_L (REG_SCL0_BASE + 0x96) ++#define REG_SCL0_4B_H (REG_SCL0_BASE + 0x97) ++#define REG_SCL0_4C_L (REG_SCL0_BASE + 0x98) ++#define REG_SCL0_4C_H (REG_SCL0_BASE + 0x99) ++#define REG_SCL0_4D_L (REG_SCL0_BASE + 0x9A) ++#define REG_SCL0_4D_H (REG_SCL0_BASE + 0x9B) ++#define REG_SCL0_4E_L (REG_SCL0_BASE + 0x9C) ++#define REG_SCL0_4E_H (REG_SCL0_BASE + 0x9D) ++#define REG_SCL0_4F_L (REG_SCL0_BASE + 0x9E) ++#define REG_SCL0_4F_H (REG_SCL0_BASE + 0x9F) ++#define REG_SCL0_50_L (REG_SCL0_BASE + 0xA0) ++#define REG_SCL0_50_H (REG_SCL0_BASE + 0xA1) ++#define REG_SCL0_51_L (REG_SCL0_BASE + 0xA2) ++#define REG_SCL0_51_H (REG_SCL0_BASE + 0xA3) ++#define REG_SCL0_52_L (REG_SCL0_BASE + 0xA4) ++#define REG_SCL0_52_H (REG_SCL0_BASE + 0xA5) ++#define REG_SCL0_53_L (REG_SCL0_BASE + 0xA6) ++#define REG_SCL0_53_H (REG_SCL0_BASE + 0xA7) ++#define REG_SCL0_54_L (REG_SCL0_BASE + 0xA8) ++#define REG_SCL0_54_H (REG_SCL0_BASE + 0xA9) ++#define REG_SCL0_55_L (REG_SCL0_BASE + 0xAA) ++#define REG_SCL0_55_H (REG_SCL0_BASE + 0xAB) ++#define REG_SCL0_56_L (REG_SCL0_BASE + 0xAC) ++#define REG_SCL0_56_H (REG_SCL0_BASE + 0xAD) ++#define REG_SCL0_57_L (REG_SCL0_BASE + 0xAE) ++#define REG_SCL0_57_H (REG_SCL0_BASE + 0xAF) ++#define REG_SCL0_58_L (REG_SCL0_BASE + 0xB0) ++#define REG_SCL0_58_H (REG_SCL0_BASE + 0xB1) ++#define REG_SCL0_59_L (REG_SCL0_BASE + 0xB2) ++#define REG_SCL0_59_H (REG_SCL0_BASE + 0xB3) ++#define REG_SCL0_5A_L (REG_SCL0_BASE + 0xB4) ++#define REG_SCL0_5A_H (REG_SCL0_BASE + 0xB5) ++#define REG_SCL0_5B_L (REG_SCL0_BASE + 0xB6) ++#define REG_SCL0_5B_H (REG_SCL0_BASE + 0xB7) ++#define REG_SCL0_5C_L (REG_SCL0_BASE + 0xB8) ++#define REG_SCL0_5C_H (REG_SCL0_BASE + 0xB9) ++#define REG_SCL0_5D_L (REG_SCL0_BASE + 0xBA) ++#define REG_SCL0_5D_H (REG_SCL0_BASE + 0xBB) ++#define REG_SCL0_5E_L (REG_SCL0_BASE + 0xBC) ++#define REG_SCL0_5E_H (REG_SCL0_BASE + 0xBD) ++#define REG_SCL0_5F_L (REG_SCL0_BASE + 0xBE) ++#define REG_SCL0_5F_H (REG_SCL0_BASE + 0xBF) ++#define REG_SCL0_60_L (REG_SCL0_BASE + 0xC0) ++#define REG_SCL0_60_H (REG_SCL0_BASE + 0xC1) ++#define REG_SCL0_61_L (REG_SCL0_BASE + 0xC2) ++#define REG_SCL0_61_H (REG_SCL0_BASE + 0xC3) ++#define REG_SCL0_62_L (REG_SCL0_BASE + 0xC4) ++#define REG_SCL0_62_H (REG_SCL0_BASE + 0xC5) ++#define REG_SCL0_63_L (REG_SCL0_BASE + 0xC6) ++#define REG_SCL0_63_H (REG_SCL0_BASE + 0xC7) ++#define REG_SCL0_64_L (REG_SCL0_BASE + 0xC8) ++#define REG_SCL0_64_H (REG_SCL0_BASE + 0xC9) ++#define REG_SCL0_65_L (REG_SCL0_BASE + 0xCA) ++#define REG_SCL0_65_H (REG_SCL0_BASE + 0xCB) ++#define REG_SCL0_66_L (REG_SCL0_BASE + 0xCC) ++#define REG_SCL0_66_H (REG_SCL0_BASE + 0xCD) ++#define REG_SCL0_67_L (REG_SCL0_BASE + 0xCE) ++#define REG_SCL0_67_H (REG_SCL0_BASE + 0xCF) ++#define REG_SCL0_68_L (REG_SCL0_BASE + 0xD0) ++#define REG_SCL0_68_H (REG_SCL0_BASE + 0xD1) ++#define REG_SCL0_69_L (REG_SCL0_BASE + 0xD2) ++#define REG_SCL0_69_H (REG_SCL0_BASE + 0xD3) ++#define REG_SCL0_6A_L (REG_SCL0_BASE + 0xD4) ++#define REG_SCL0_6A_H (REG_SCL0_BASE + 0xD5) ++#define REG_SCL0_6B_L (REG_SCL0_BASE + 0xD6) ++#define REG_SCL0_6B_H (REG_SCL0_BASE + 0xD7) ++#define REG_SCL0_6C_L (REG_SCL0_BASE + 0xD8) ++#define REG_SCL0_6C_H (REG_SCL0_BASE + 0xD9) ++#define REG_SCL0_6D_L (REG_SCL0_BASE + 0xDA) ++#define REG_SCL0_6D_H (REG_SCL0_BASE + 0xDB) ++#define REG_SCL0_6E_L (REG_SCL0_BASE + 0xDC) ++#define REG_SCL0_6E_H (REG_SCL0_BASE + 0xDD) ++#define REG_SCL0_6F_L (REG_SCL0_BASE + 0xDE) ++#define REG_SCL0_6F_H (REG_SCL0_BASE + 0xDF) ++#define REG_SCL0_70_L (REG_SCL0_BASE + 0xE0) ++#define REG_SCL0_70_H (REG_SCL0_BASE + 0xE1) ++#define REG_SCL0_71_L (REG_SCL0_BASE + 0xE2) ++#define REG_SCL0_71_H (REG_SCL0_BASE + 0xE3) ++#define REG_SCL0_72_L (REG_SCL0_BASE + 0xE4) ++#define REG_SCL0_72_H (REG_SCL0_BASE + 0xE5) ++#define REG_SCL0_73_L (REG_SCL0_BASE + 0xE6) ++#define REG_SCL0_73_H (REG_SCL0_BASE + 0xE7) ++#define REG_SCL0_74_L (REG_SCL0_BASE + 0xE8) ++#define REG_SCL0_74_H (REG_SCL0_BASE + 0xE9) ++#define REG_SCL0_75_L (REG_SCL0_BASE + 0xEA) ++#define REG_SCL0_75_H (REG_SCL0_BASE + 0xEB) ++#define REG_SCL0_76_L (REG_SCL0_BASE + 0xEC) ++#define REG_SCL0_76_H (REG_SCL0_BASE + 0xED) ++#define REG_SCL0_77_L (REG_SCL0_BASE + 0xEE) ++#define REG_SCL0_77_H (REG_SCL0_BASE + 0xEF) ++#define REG_SCL0_78_L (REG_SCL0_BASE + 0xF0) ++#define REG_SCL0_78_H (REG_SCL0_BASE + 0xF1) ++#define REG_SCL0_79_L (REG_SCL0_BASE + 0xF2) ++#define REG_SCL0_79_H (REG_SCL0_BASE + 0xF3) ++#define REG_SCL0_7A_L (REG_SCL0_BASE + 0xF4) ++#define REG_SCL0_7A_H (REG_SCL0_BASE + 0xF5) ++#define REG_SCL0_7B_L (REG_SCL0_BASE + 0xF6) ++#define REG_SCL0_7B_H (REG_SCL0_BASE + 0xF7) ++#define REG_SCL0_7C_L (REG_SCL0_BASE + 0xF8) ++#define REG_SCL0_7C_H (REG_SCL0_BASE + 0xF9) ++#define REG_SCL0_7D_L (REG_SCL0_BASE + 0xFA) ++#define REG_SCL0_7D_H (REG_SCL0_BASE + 0xFB) ++#define REG_SCL0_7E_L (REG_SCL0_BASE + 0xFC) ++#define REG_SCL0_7E_H (REG_SCL0_BASE + 0xFD) ++#define REG_SCL0_7F_L (REG_SCL0_BASE + 0xFE) ++#define REG_SCL0_7F_H (REG_SCL0_BASE + 0xFF) ++ ++#define REG_SCL1_00_L (REG_SCL1_BASE + 0x00) ++#define REG_SCL1_00_H (REG_SCL1_BASE + 0x01) ++#define REG_SCL1_01_L (REG_SCL1_BASE + 0x02) ++#define REG_SCL1_01_H (REG_SCL1_BASE + 0x03) ++#define REG_SCL1_02_L (REG_SCL1_BASE + 0x04) ++#define REG_SCL1_02_H (REG_SCL1_BASE + 0x05) ++#define REG_SCL1_03_L (REG_SCL1_BASE + 0x06) ++#define REG_SCL1_03_H (REG_SCL1_BASE + 0x07) ++#define REG_SCL1_04_L (REG_SCL1_BASE + 0x08) ++#define REG_SCL1_04_H (REG_SCL1_BASE + 0x09) ++#define REG_SCL1_05_L (REG_SCL1_BASE + 0x0A) ++#define REG_SCL1_05_H (REG_SCL1_BASE + 0x0B) ++#define REG_SCL1_06_L (REG_SCL1_BASE + 0x0C) ++#define REG_SCL1_06_H (REG_SCL1_BASE + 0x0D) ++#define REG_SCL1_07_L (REG_SCL1_BASE + 0x0E) ++#define REG_SCL1_07_H (REG_SCL1_BASE + 0x0F) ++#define REG_SCL1_08_L (REG_SCL1_BASE + 0x10) ++#define REG_SCL1_08_H (REG_SCL1_BASE + 0x11) ++#define REG_SCL1_09_L (REG_SCL1_BASE + 0x12) ++#define REG_SCL1_09_H (REG_SCL1_BASE + 0x13) ++#define REG_SCL1_0A_L (REG_SCL1_BASE + 0x14) ++#define REG_SCL1_0A_H (REG_SCL1_BASE + 0x15) ++#define REG_SCL1_0B_L (REG_SCL1_BASE + 0x16) ++#define REG_SCL1_0B_H (REG_SCL1_BASE + 0x17) ++#define REG_SCL1_0C_L (REG_SCL1_BASE + 0x18) ++#define REG_SCL1_0C_H (REG_SCL1_BASE + 0x19) ++#define REG_SCL1_0D_L (REG_SCL1_BASE + 0x1A) ++#define REG_SCL1_0D_H (REG_SCL1_BASE + 0x1B) ++#define REG_SCL1_0E_L (REG_SCL1_BASE + 0x1C) ++#define REG_SCL1_0E_H (REG_SCL1_BASE + 0x1D) ++#define REG_SCL1_0F_L (REG_SCL1_BASE + 0x1E) ++#define REG_SCL1_0F_H (REG_SCL1_BASE + 0x1F) ++#define REG_SCL1_10_L (REG_SCL1_BASE + 0x20) ++#define REG_SCL1_10_H (REG_SCL1_BASE + 0x21) ++#define REG_SCL1_11_L (REG_SCL1_BASE + 0x22) ++#define REG_SCL1_11_H (REG_SCL1_BASE + 0x23) ++#define REG_SCL1_12_L (REG_SCL1_BASE + 0x24) ++#define REG_SCL1_12_H (REG_SCL1_BASE + 0x25) ++#define REG_SCL1_13_L (REG_SCL1_BASE + 0x26) ++#define REG_SCL1_13_H (REG_SCL1_BASE + 0x27) ++#define REG_SCL1_14_L (REG_SCL1_BASE + 0x28) ++#define REG_SCL1_14_H (REG_SCL1_BASE + 0x29) ++#define REG_SCL1_15_L (REG_SCL1_BASE + 0x2A) ++#define REG_SCL1_15_H (REG_SCL1_BASE + 0x2B) ++#define REG_SCL1_16_L (REG_SCL1_BASE + 0x2C) ++#define REG_SCL1_16_H (REG_SCL1_BASE + 0x2D) ++#define REG_SCL1_17_L (REG_SCL1_BASE + 0x2E) ++#define REG_SCL1_17_H (REG_SCL1_BASE + 0x2F) ++#define REG_SCL1_18_L (REG_SCL1_BASE + 0x30) ++#define REG_SCL1_18_H (REG_SCL1_BASE + 0x31) ++#define REG_SCL1_19_L (REG_SCL1_BASE + 0x32) ++#define REG_SCL1_19_H (REG_SCL1_BASE + 0x33) ++#define REG_SCL1_1A_L (REG_SCL1_BASE + 0x34) ++#define REG_SCL1_1A_H (REG_SCL1_BASE + 0x35) ++#define REG_SCL1_1B_L (REG_SCL1_BASE + 0x36) ++#define REG_SCL1_1B_H (REG_SCL1_BASE + 0x37) ++#define REG_SCL1_1C_L (REG_SCL1_BASE + 0x38) ++#define REG_SCL1_1C_H (REG_SCL1_BASE + 0x39) ++#define REG_SCL1_1D_L (REG_SCL1_BASE + 0x3A) ++#define REG_SCL1_1D_H (REG_SCL1_BASE + 0x3B) ++#define REG_SCL1_1E_L (REG_SCL1_BASE + 0x3C) ++#define REG_SCL1_1E_H (REG_SCL1_BASE + 0x3D) ++#define REG_SCL1_1F_L (REG_SCL1_BASE + 0x3E) ++#define REG_SCL1_1F_H (REG_SCL1_BASE + 0x3F) ++#define REG_SCL1_20_L (REG_SCL1_BASE + 0x40) ++#define REG_SCL1_20_H (REG_SCL1_BASE + 0x41) ++#define REG_SCL1_21_L (REG_SCL1_BASE + 0x42) ++#define REG_SCL1_21_H (REG_SCL1_BASE + 0x43) ++#define REG_SCL1_22_L (REG_SCL1_BASE + 0x44) ++#define REG_SCL1_22_H (REG_SCL1_BASE + 0x45) ++#define REG_SCL1_23_L (REG_SCL1_BASE + 0x46) ++#define REG_SCL1_23_H (REG_SCL1_BASE + 0x47) ++#define REG_SCL1_24_L (REG_SCL1_BASE + 0x48) ++#define REG_SCL1_24_H (REG_SCL1_BASE + 0x49) ++#define REG_SCL1_25_L (REG_SCL1_BASE + 0x4A) ++#define REG_SCL1_25_H (REG_SCL1_BASE + 0x4B) ++#define REG_SCL1_26_L (REG_SCL1_BASE + 0x4C) ++#define REG_SCL1_26_H (REG_SCL1_BASE + 0x4D) ++#define REG_SCL1_27_L (REG_SCL1_BASE + 0x4E) ++#define REG_SCL1_27_H (REG_SCL1_BASE + 0x4F) ++#define REG_SCL1_28_L (REG_SCL1_BASE + 0x50) ++#define REG_SCL1_28_H (REG_SCL1_BASE + 0x51) ++#define REG_SCL1_29_L (REG_SCL1_BASE + 0x52) ++#define REG_SCL1_29_H (REG_SCL1_BASE + 0x53) ++#define REG_SCL1_2A_L (REG_SCL1_BASE + 0x54) ++#define REG_SCL1_2A_H (REG_SCL1_BASE + 0x55) ++#define REG_SCL1_2B_L (REG_SCL1_BASE + 0x56) ++#define REG_SCL1_2B_H (REG_SCL1_BASE + 0x57) ++#define REG_SCL1_2C_L (REG_SCL1_BASE + 0x58) ++#define REG_SCL1_2C_H (REG_SCL1_BASE + 0x59) ++#define REG_SCL1_2D_L (REG_SCL1_BASE + 0x5A) ++#define REG_SCL1_2D_H (REG_SCL1_BASE + 0x5B) ++#define REG_SCL1_2E_L (REG_SCL1_BASE + 0x5C) ++#define REG_SCL1_2E_H (REG_SCL1_BASE + 0x5D) ++#define REG_SCL1_2F_L (REG_SCL1_BASE + 0x5E) ++#define REG_SCL1_2F_H (REG_SCL1_BASE + 0x5F) ++#define REG_SCL1_30_L (REG_SCL1_BASE + 0x60) ++#define REG_SCL1_30_H (REG_SCL1_BASE + 0x61) ++#define REG_SCL1_31_L (REG_SCL1_BASE + 0x62) ++#define REG_SCL1_31_H (REG_SCL1_BASE + 0x63) ++#define REG_SCL1_32_L (REG_SCL1_BASE + 0x64) ++#define REG_SCL1_32_H (REG_SCL1_BASE + 0x65) ++#define REG_SCL1_33_L (REG_SCL1_BASE + 0x66) ++#define REG_SCL1_33_H (REG_SCL1_BASE + 0x67) ++#define REG_SCL1_34_L (REG_SCL1_BASE + 0x68) ++#define REG_SCL1_34_H (REG_SCL1_BASE + 0x69) ++#define REG_SCL1_35_L (REG_SCL1_BASE + 0x6A) ++#define REG_SCL1_35_H (REG_SCL1_BASE + 0x6B) ++#define REG_SCL1_36_L (REG_SCL1_BASE + 0x6C) ++#define REG_SCL1_36_H (REG_SCL1_BASE + 0x6D) ++#define REG_SCL1_37_L (REG_SCL1_BASE + 0x6E) ++#define REG_SCL1_37_H (REG_SCL1_BASE + 0x6F) ++#define REG_SCL1_38_L (REG_SCL1_BASE + 0x70) ++#define REG_SCL1_38_H (REG_SCL1_BASE + 0x71) ++#define REG_SCL1_39_L (REG_SCL1_BASE + 0x72) ++#define REG_SCL1_39_H (REG_SCL1_BASE + 0x73) ++#define REG_SCL1_3A_L (REG_SCL1_BASE + 0x74) ++#define REG_SCL1_3A_H (REG_SCL1_BASE + 0x75) ++#define REG_SCL1_3B_L (REG_SCL1_BASE + 0x76) ++#define REG_SCL1_3B_H (REG_SCL1_BASE + 0x77) ++#define REG_SCL1_3C_L (REG_SCL1_BASE + 0x78) ++#define REG_SCL1_3C_H (REG_SCL1_BASE + 0x79) ++#define REG_SCL1_3D_L (REG_SCL1_BASE + 0x7A) ++#define REG_SCL1_3D_H (REG_SCL1_BASE + 0x7B) ++#define REG_SCL1_3E_L (REG_SCL1_BASE + 0x7C) ++#define REG_SCL1_3E_H (REG_SCL1_BASE + 0x7D) ++#define REG_SCL1_3F_L (REG_SCL1_BASE + 0x7E) ++#define REG_SCL1_3F_H (REG_SCL1_BASE + 0x7F) ++#define REG_SCL1_40_L (REG_SCL1_BASE + 0x80) ++#define REG_SCL1_40_H (REG_SCL1_BASE + 0x81) ++#define REG_SCL1_41_L (REG_SCL1_BASE + 0x82) ++#define REG_SCL1_41_H (REG_SCL1_BASE + 0x83) ++#define REG_SCL1_42_L (REG_SCL1_BASE + 0x84) ++#define REG_SCL1_42_H (REG_SCL1_BASE + 0x85) ++#define REG_SCL1_43_L (REG_SCL1_BASE + 0x86) ++#define REG_SCL1_43_H (REG_SCL1_BASE + 0x87) ++#define REG_SCL1_44_L (REG_SCL1_BASE + 0x88) ++#define REG_SCL1_44_H (REG_SCL1_BASE + 0x89) ++#define REG_SCL1_45_L (REG_SCL1_BASE + 0x8A) ++#define REG_SCL1_45_H (REG_SCL1_BASE + 0x8B) ++#define REG_SCL1_46_L (REG_SCL1_BASE + 0x8C) ++#define REG_SCL1_46_H (REG_SCL1_BASE + 0x8D) ++#define REG_SCL1_47_L (REG_SCL1_BASE + 0x8E) ++#define REG_SCL1_47_H (REG_SCL1_BASE + 0x8F) ++#define REG_SCL1_48_L (REG_SCL1_BASE + 0x90) ++#define REG_SCL1_48_H (REG_SCL1_BASE + 0x91) ++#define REG_SCL1_49_L (REG_SCL1_BASE + 0x92) ++#define REG_SCL1_49_H (REG_SCL1_BASE + 0x93) ++#define REG_SCL1_4A_L (REG_SCL1_BASE + 0x94) ++#define REG_SCL1_4A_H (REG_SCL1_BASE + 0x95) ++#define REG_SCL1_4B_L (REG_SCL1_BASE + 0x96) ++#define REG_SCL1_4B_H (REG_SCL1_BASE + 0x97) ++#define REG_SCL1_4C_L (REG_SCL1_BASE + 0x98) ++#define REG_SCL1_4C_H (REG_SCL1_BASE + 0x99) ++#define REG_SCL1_4D_L (REG_SCL1_BASE + 0x9A) ++#define REG_SCL1_4D_H (REG_SCL1_BASE + 0x9B) ++#define REG_SCL1_4E_L (REG_SCL1_BASE + 0x9C) ++#define REG_SCL1_4E_H (REG_SCL1_BASE + 0x9D) ++#define REG_SCL1_4F_L (REG_SCL1_BASE + 0x9E) ++#define REG_SCL1_4F_H (REG_SCL1_BASE + 0x9F) ++#define REG_SCL1_50_L (REG_SCL1_BASE + 0xA0) ++#define REG_SCL1_50_H (REG_SCL1_BASE + 0xA1) ++#define REG_SCL1_51_L (REG_SCL1_BASE + 0xA2) ++#define REG_SCL1_51_H (REG_SCL1_BASE + 0xA3) ++#define REG_SCL1_52_L (REG_SCL1_BASE + 0xA4) ++#define REG_SCL1_52_H (REG_SCL1_BASE + 0xA5) ++#define REG_SCL1_53_L (REG_SCL1_BASE + 0xA6) ++#define REG_SCL1_53_H (REG_SCL1_BASE + 0xA7) ++#define REG_SCL1_54_L (REG_SCL1_BASE + 0xA8) ++#define REG_SCL1_54_H (REG_SCL1_BASE + 0xA9) ++#define REG_SCL1_55_L (REG_SCL1_BASE + 0xAA) ++#define REG_SCL1_55_H (REG_SCL1_BASE + 0xAB) ++#define REG_SCL1_56_L (REG_SCL1_BASE + 0xAC) ++#define REG_SCL1_56_H (REG_SCL1_BASE + 0xAD) ++#define REG_SCL1_57_L (REG_SCL1_BASE + 0xAE) ++#define REG_SCL1_57_H (REG_SCL1_BASE + 0xAF) ++#define REG_SCL1_58_L (REG_SCL1_BASE + 0xB0) ++#define REG_SCL1_58_H (REG_SCL1_BASE + 0xB1) ++#define REG_SCL1_59_L (REG_SCL1_BASE + 0xB2) ++#define REG_SCL1_59_H (REG_SCL1_BASE + 0xB3) ++#define REG_SCL1_5A_L (REG_SCL1_BASE + 0xB4) ++#define REG_SCL1_5A_H (REG_SCL1_BASE + 0xB5) ++#define REG_SCL1_5B_L (REG_SCL1_BASE + 0xB6) ++#define REG_SCL1_5B_H (REG_SCL1_BASE + 0xB7) ++#define REG_SCL1_5C_L (REG_SCL1_BASE + 0xB8) ++#define REG_SCL1_5C_H (REG_SCL1_BASE + 0xB9) ++#define REG_SCL1_5D_L (REG_SCL1_BASE + 0xBA) ++#define REG_SCL1_5D_H (REG_SCL1_BASE + 0xBB) ++#define REG_SCL1_5E_L (REG_SCL1_BASE + 0xBC) ++#define REG_SCL1_5E_H (REG_SCL1_BASE + 0xBD) ++#define REG_SCL1_5F_L (REG_SCL1_BASE + 0xBE) ++#define REG_SCL1_5F_H (REG_SCL1_BASE + 0xBF) ++#define REG_SCL1_60_L (REG_SCL1_BASE + 0xC0) ++#define REG_SCL1_60_H (REG_SCL1_BASE + 0xC1) ++#define REG_SCL1_61_L (REG_SCL1_BASE + 0xC2) ++#define REG_SCL1_61_H (REG_SCL1_BASE + 0xC3) ++#define REG_SCL1_62_L (REG_SCL1_BASE + 0xC4) ++#define REG_SCL1_62_H (REG_SCL1_BASE + 0xC5) ++#define REG_SCL1_63_L (REG_SCL1_BASE + 0xC6) ++#define REG_SCL1_63_H (REG_SCL1_BASE + 0xC7) ++#define REG_SCL1_64_L (REG_SCL1_BASE + 0xC8) ++#define REG_SCL1_64_H (REG_SCL1_BASE + 0xC9) ++#define REG_SCL1_65_L (REG_SCL1_BASE + 0xCA) ++#define REG_SCL1_65_H (REG_SCL1_BASE + 0xCB) ++#define REG_SCL1_66_L (REG_SCL1_BASE + 0xCC) ++#define REG_SCL1_66_H (REG_SCL1_BASE + 0xCD) ++#define REG_SCL1_67_L (REG_SCL1_BASE + 0xCE) ++#define REG_SCL1_67_H (REG_SCL1_BASE + 0xCF) ++#define REG_SCL1_68_L (REG_SCL1_BASE + 0xD0) ++#define REG_SCL1_68_H (REG_SCL1_BASE + 0xD1) ++#define REG_SCL1_69_L (REG_SCL1_BASE + 0xD2) ++#define REG_SCL1_69_H (REG_SCL1_BASE + 0xD3) ++#define REG_SCL1_6A_L (REG_SCL1_BASE + 0xD4) ++#define REG_SCL1_6A_H (REG_SCL1_BASE + 0xD5) ++#define REG_SCL1_6B_L (REG_SCL1_BASE + 0xD6) ++#define REG_SCL1_6B_H (REG_SCL1_BASE + 0xD7) ++#define REG_SCL1_6C_L (REG_SCL1_BASE + 0xD8) ++#define REG_SCL1_6C_H (REG_SCL1_BASE + 0xD9) ++#define REG_SCL1_6D_L (REG_SCL1_BASE + 0xDA) ++#define REG_SCL1_6D_H (REG_SCL1_BASE + 0xDB) ++#define REG_SCL1_6E_L (REG_SCL1_BASE + 0xDC) ++#define REG_SCL1_6E_H (REG_SCL1_BASE + 0xDD) ++#define REG_SCL1_6F_L (REG_SCL1_BASE + 0xDE) ++#define REG_SCL1_6F_H (REG_SCL1_BASE + 0xDF) ++#define REG_SCL1_70_L (REG_SCL1_BASE + 0xE0) ++#define REG_SCL1_70_H (REG_SCL1_BASE + 0xE1) ++#define REG_SCL1_71_L (REG_SCL1_BASE + 0xE2) ++#define REG_SCL1_71_H (REG_SCL1_BASE + 0xE3) ++#define REG_SCL1_72_L (REG_SCL1_BASE + 0xE4) ++#define REG_SCL1_72_H (REG_SCL1_BASE + 0xE5) ++#define REG_SCL1_73_L (REG_SCL1_BASE + 0xE6) ++#define REG_SCL1_73_H (REG_SCL1_BASE + 0xE7) ++#define REG_SCL1_74_L (REG_SCL1_BASE + 0xE8) ++#define REG_SCL1_74_H (REG_SCL1_BASE + 0xE9) ++#define REG_SCL1_75_L (REG_SCL1_BASE + 0xEA) ++#define REG_SCL1_75_H (REG_SCL1_BASE + 0xEB) ++#define REG_SCL1_76_L (REG_SCL1_BASE + 0xEC) ++#define REG_SCL1_76_H (REG_SCL1_BASE + 0xED) ++#define REG_SCL1_77_L (REG_SCL1_BASE + 0xEE) ++#define REG_SCL1_77_H (REG_SCL1_BASE + 0xEF) ++#define REG_SCL1_78_L (REG_SCL1_BASE + 0xF0) ++#define REG_SCL1_78_H (REG_SCL1_BASE + 0xF1) ++#define REG_SCL1_79_L (REG_SCL1_BASE + 0xF2) ++#define REG_SCL1_79_H (REG_SCL1_BASE + 0xF3) ++#define REG_SCL1_7A_L (REG_SCL1_BASE + 0xF4) ++#define REG_SCL1_7A_H (REG_SCL1_BASE + 0xF5) ++#define REG_SCL1_7B_L (REG_SCL1_BASE + 0xF6) ++#define REG_SCL1_7B_H (REG_SCL1_BASE + 0xF7) ++#define REG_SCL1_7C_L (REG_SCL1_BASE + 0xF8) ++#define REG_SCL1_7C_H (REG_SCL1_BASE + 0xF9) ++#define REG_SCL1_7D_L (REG_SCL1_BASE + 0xFA) ++#define REG_SCL1_7D_H (REG_SCL1_BASE + 0xFB) ++#define REG_SCL1_7E_L (REG_SCL1_BASE + 0xFC) ++#define REG_SCL1_7E_H (REG_SCL1_BASE + 0xFD) ++#define REG_SCL1_7F_L (REG_SCL1_BASE + 0xFE) ++#define REG_SCL1_7F_H (REG_SCL1_BASE + 0xFF) ++ ++#define REG_SCL2_00_L (REG_SCL2_BASE + 0x00) ++#define REG_SCL2_00_H (REG_SCL2_BASE + 0x01) ++#define REG_SCL2_01_L (REG_SCL2_BASE + 0x02) ++#define REG_SCL2_01_H (REG_SCL2_BASE + 0x03) ++#define REG_SCL2_02_L (REG_SCL2_BASE + 0x04) ++#define REG_SCL2_02_H (REG_SCL2_BASE + 0x05) ++#define REG_SCL2_03_L (REG_SCL2_BASE + 0x06) ++#define REG_SCL2_03_H (REG_SCL2_BASE + 0x07) ++#define REG_SCL2_04_L (REG_SCL2_BASE + 0x08) ++#define REG_SCL2_04_H (REG_SCL2_BASE + 0x09) ++#define REG_SCL2_05_L (REG_SCL2_BASE + 0x0A) ++#define REG_SCL2_05_H (REG_SCL2_BASE + 0x0B) ++#define REG_SCL2_06_L (REG_SCL2_BASE + 0x0C) ++#define REG_SCL2_06_H (REG_SCL2_BASE + 0x0D) ++#define REG_SCL2_07_L (REG_SCL2_BASE + 0x0E) ++#define REG_SCL2_07_H (REG_SCL2_BASE + 0x0F) ++#define REG_SCL2_08_L (REG_SCL2_BASE + 0x10) ++#define REG_SCL2_08_H (REG_SCL2_BASE + 0x11) ++#define REG_SCL2_09_L (REG_SCL2_BASE + 0x12) ++#define REG_SCL2_09_H (REG_SCL2_BASE + 0x13) ++#define REG_SCL2_0A_L (REG_SCL2_BASE + 0x14) ++#define REG_SCL2_0A_H (REG_SCL2_BASE + 0x15) ++#define REG_SCL2_0B_L (REG_SCL2_BASE + 0x16) ++#define REG_SCL2_0B_H (REG_SCL2_BASE + 0x17) ++#define REG_SCL2_0C_L (REG_SCL2_BASE + 0x18) ++#define REG_SCL2_0C_H (REG_SCL2_BASE + 0x19) ++#define REG_SCL2_0D_L (REG_SCL2_BASE + 0x1A) ++#define REG_SCL2_0D_H (REG_SCL2_BASE + 0x1B) ++#define REG_SCL2_0E_L (REG_SCL2_BASE + 0x1C) ++#define REG_SCL2_0E_H (REG_SCL2_BASE + 0x1D) ++#define REG_SCL2_0F_L (REG_SCL2_BASE + 0x1E) ++#define REG_SCL2_0F_H (REG_SCL2_BASE + 0x1F) ++#define REG_SCL2_10_L (REG_SCL2_BASE + 0x20) ++#define REG_SCL2_10_H (REG_SCL2_BASE + 0x21) ++#define REG_SCL2_11_L (REG_SCL2_BASE + 0x22) ++#define REG_SCL2_11_H (REG_SCL2_BASE + 0x23) ++#define REG_SCL2_12_L (REG_SCL2_BASE + 0x24) ++#define REG_SCL2_12_H (REG_SCL2_BASE + 0x25) ++#define REG_SCL2_13_L (REG_SCL2_BASE + 0x26) ++#define REG_SCL2_13_H (REG_SCL2_BASE + 0x27) ++#define REG_SCL2_14_L (REG_SCL2_BASE + 0x28) ++#define REG_SCL2_14_H (REG_SCL2_BASE + 0x29) ++#define REG_SCL2_15_L (REG_SCL2_BASE + 0x2A) ++#define REG_SCL2_15_H (REG_SCL2_BASE + 0x2B) ++#define REG_SCL2_16_L (REG_SCL2_BASE + 0x2C) ++#define REG_SCL2_16_H (REG_SCL2_BASE + 0x2D) ++#define REG_SCL2_17_L (REG_SCL2_BASE + 0x2E) ++#define REG_SCL2_17_H (REG_SCL2_BASE + 0x2F) ++#define REG_SCL2_18_L (REG_SCL2_BASE + 0x30) ++#define REG_SCL2_18_H (REG_SCL2_BASE + 0x31) ++#define REG_SCL2_19_L (REG_SCL2_BASE + 0x32) ++#define REG_SCL2_19_H (REG_SCL2_BASE + 0x33) ++#define REG_SCL2_1A_L (REG_SCL2_BASE + 0x34) ++#define REG_SCL2_1A_H (REG_SCL2_BASE + 0x35) ++#define REG_SCL2_1B_L (REG_SCL2_BASE + 0x36) ++#define REG_SCL2_1B_H (REG_SCL2_BASE + 0x37) ++#define REG_SCL2_1C_L (REG_SCL2_BASE + 0x38) ++#define REG_SCL2_1C_H (REG_SCL2_BASE + 0x39) ++#define REG_SCL2_1D_L (REG_SCL2_BASE + 0x3A) ++#define REG_SCL2_1D_H (REG_SCL2_BASE + 0x3B) ++#define REG_SCL2_1E_L (REG_SCL2_BASE + 0x3C) ++#define REG_SCL2_1E_H (REG_SCL2_BASE + 0x3D) ++#define REG_SCL2_1F_L (REG_SCL2_BASE + 0x3E) ++#define REG_SCL2_1F_H (REG_SCL2_BASE + 0x3F) ++#define REG_SCL2_20_L (REG_SCL2_BASE + 0x40) ++#define REG_SCL2_20_H (REG_SCL2_BASE + 0x41) ++#define REG_SCL2_21_L (REG_SCL2_BASE + 0x42) ++#define REG_SCL2_21_H (REG_SCL2_BASE + 0x43) ++#define REG_SCL2_22_L (REG_SCL2_BASE + 0x44) ++#define REG_SCL2_22_H (REG_SCL2_BASE + 0x45) ++#define REG_SCL2_23_L (REG_SCL2_BASE + 0x46) ++#define REG_SCL2_23_H (REG_SCL2_BASE + 0x47) ++#define REG_SCL2_24_L (REG_SCL2_BASE + 0x48) ++#define REG_SCL2_24_H (REG_SCL2_BASE + 0x49) ++#define REG_SCL2_25_L (REG_SCL2_BASE + 0x4A) ++#define REG_SCL2_25_H (REG_SCL2_BASE + 0x4B) ++#define REG_SCL2_26_L (REG_SCL2_BASE + 0x4C) ++#define REG_SCL2_26_H (REG_SCL2_BASE + 0x4D) ++#define REG_SCL2_27_L (REG_SCL2_BASE + 0x4E) ++#define REG_SCL2_27_H (REG_SCL2_BASE + 0x4F) ++#define REG_SCL2_28_L (REG_SCL2_BASE + 0x50) ++#define REG_SCL2_28_H (REG_SCL2_BASE + 0x51) ++#define REG_SCL2_29_L (REG_SCL2_BASE + 0x52) ++#define REG_SCL2_29_H (REG_SCL2_BASE + 0x53) ++#define REG_SCL2_2A_L (REG_SCL2_BASE + 0x54) ++#define REG_SCL2_2A_H (REG_SCL2_BASE + 0x55) ++#define REG_SCL2_2B_L (REG_SCL2_BASE + 0x56) ++#define REG_SCL2_2B_H (REG_SCL2_BASE + 0x57) ++#define REG_SCL2_2C_L (REG_SCL2_BASE + 0x58) ++#define REG_SCL2_2C_H (REG_SCL2_BASE + 0x59) ++#define REG_SCL2_2D_L (REG_SCL2_BASE + 0x5A) ++#define REG_SCL2_2D_H (REG_SCL2_BASE + 0x5B) ++#define REG_SCL2_2E_L (REG_SCL2_BASE + 0x5C) ++#define REG_SCL2_2E_H (REG_SCL2_BASE + 0x5D) ++#define REG_SCL2_2F_L (REG_SCL2_BASE + 0x5E) ++#define REG_SCL2_2F_H (REG_SCL2_BASE + 0x5F) ++#define REG_SCL2_30_L (REG_SCL2_BASE + 0x60) ++#define REG_SCL2_30_H (REG_SCL2_BASE + 0x61) ++#define REG_SCL2_31_L (REG_SCL2_BASE + 0x62) ++#define REG_SCL2_31_H (REG_SCL2_BASE + 0x63) ++#define REG_SCL2_32_L (REG_SCL2_BASE + 0x64) ++#define REG_SCL2_32_H (REG_SCL2_BASE + 0x65) ++#define REG_SCL2_33_L (REG_SCL2_BASE + 0x66) ++#define REG_SCL2_33_H (REG_SCL2_BASE + 0x67) ++#define REG_SCL2_34_L (REG_SCL2_BASE + 0x68) ++#define REG_SCL2_34_H (REG_SCL2_BASE + 0x69) ++#define REG_SCL2_35_L (REG_SCL2_BASE + 0x6A) ++#define REG_SCL2_35_H (REG_SCL2_BASE + 0x6B) ++#define REG_SCL2_36_L (REG_SCL2_BASE + 0x6C) ++#define REG_SCL2_36_H (REG_SCL2_BASE + 0x6D) ++#define REG_SCL2_37_L (REG_SCL2_BASE + 0x6E) ++#define REG_SCL2_37_H (REG_SCL2_BASE + 0x6F) ++#define REG_SCL2_38_L (REG_SCL2_BASE + 0x70) ++#define REG_SCL2_38_H (REG_SCL2_BASE + 0x71) ++#define REG_SCL2_39_L (REG_SCL2_BASE + 0x72) ++#define REG_SCL2_39_H (REG_SCL2_BASE + 0x73) ++#define REG_SCL2_3A_L (REG_SCL2_BASE + 0x74) ++#define REG_SCL2_3A_H (REG_SCL2_BASE + 0x75) ++#define REG_SCL2_3B_L (REG_SCL2_BASE + 0x76) ++#define REG_SCL2_3B_H (REG_SCL2_BASE + 0x77) ++#define REG_SCL2_3C_L (REG_SCL2_BASE + 0x78) ++#define REG_SCL2_3C_H (REG_SCL2_BASE + 0x79) ++#define REG_SCL2_3D_L (REG_SCL2_BASE + 0x7A) ++#define REG_SCL2_3D_H (REG_SCL2_BASE + 0x7B) ++#define REG_SCL2_3E_L (REG_SCL2_BASE + 0x7C) ++#define REG_SCL2_3E_H (REG_SCL2_BASE + 0x7D) ++#define REG_SCL2_3F_L (REG_SCL2_BASE + 0x7E) ++#define REG_SCL2_3F_H (REG_SCL2_BASE + 0x7F) ++#define REG_SCL2_40_L (REG_SCL2_BASE + 0x80) ++#define REG_SCL2_40_H (REG_SCL2_BASE + 0x81) ++#define REG_SCL2_41_L (REG_SCL2_BASE + 0x82) ++#define REG_SCL2_41_H (REG_SCL2_BASE + 0x83) ++#define REG_SCL2_42_L (REG_SCL2_BASE + 0x84) ++#define REG_SCL2_42_H (REG_SCL2_BASE + 0x85) ++#define REG_SCL2_43_L (REG_SCL2_BASE + 0x86) ++#define REG_SCL2_43_H (REG_SCL2_BASE + 0x87) ++#define REG_SCL2_44_L (REG_SCL2_BASE + 0x88) ++#define REG_SCL2_44_H (REG_SCL2_BASE + 0x89) ++#define REG_SCL2_45_L (REG_SCL2_BASE + 0x8A) ++#define REG_SCL2_45_H (REG_SCL2_BASE + 0x8B) ++#define REG_SCL2_46_L (REG_SCL2_BASE + 0x8C) ++#define REG_SCL2_46_H (REG_SCL2_BASE + 0x8D) ++#define REG_SCL2_47_L (REG_SCL2_BASE + 0x8E) ++#define REG_SCL2_47_H (REG_SCL2_BASE + 0x8F) ++#define REG_SCL2_48_L (REG_SCL2_BASE + 0x90) ++#define REG_SCL2_48_H (REG_SCL2_BASE + 0x91) ++#define REG_SCL2_49_L (REG_SCL2_BASE + 0x92) ++#define REG_SCL2_49_H (REG_SCL2_BASE + 0x93) ++#define REG_SCL2_4A_L (REG_SCL2_BASE + 0x94) ++#define REG_SCL2_4A_H (REG_SCL2_BASE + 0x95) ++#define REG_SCL2_4B_L (REG_SCL2_BASE + 0x96) ++#define REG_SCL2_4B_H (REG_SCL2_BASE + 0x97) ++#define REG_SCL2_4C_L (REG_SCL2_BASE + 0x98) ++#define REG_SCL2_4C_H (REG_SCL2_BASE + 0x99) ++#define REG_SCL2_4D_L (REG_SCL2_BASE + 0x9A) ++#define REG_SCL2_4D_H (REG_SCL2_BASE + 0x9B) ++#define REG_SCL2_4E_L (REG_SCL2_BASE + 0x9C) ++#define REG_SCL2_4E_H (REG_SCL2_BASE + 0x9D) ++#define REG_SCL2_4F_L (REG_SCL2_BASE + 0x9E) ++#define REG_SCL2_4F_H (REG_SCL2_BASE + 0x9F) ++#define REG_SCL2_50_L (REG_SCL2_BASE + 0xA0) ++#define REG_SCL2_50_H (REG_SCL2_BASE + 0xA1) ++#define REG_SCL2_51_L (REG_SCL2_BASE + 0xA2) ++#define REG_SCL2_51_H (REG_SCL2_BASE + 0xA3) ++#define REG_SCL2_52_L (REG_SCL2_BASE + 0xA4) ++#define REG_SCL2_52_H (REG_SCL2_BASE + 0xA5) ++#define REG_SCL2_53_L (REG_SCL2_BASE + 0xA6) ++#define REG_SCL2_53_H (REG_SCL2_BASE + 0xA7) ++#define REG_SCL2_54_L (REG_SCL2_BASE + 0xA8) ++#define REG_SCL2_54_H (REG_SCL2_BASE + 0xA9) ++#define REG_SCL2_55_L (REG_SCL2_BASE + 0xAA) ++#define REG_SCL2_55_H (REG_SCL2_BASE + 0xAB) ++#define REG_SCL2_56_L (REG_SCL2_BASE + 0xAC) ++#define REG_SCL2_56_H (REG_SCL2_BASE + 0xAD) ++#define REG_SCL2_57_L (REG_SCL2_BASE + 0xAE) ++#define REG_SCL2_57_H (REG_SCL2_BASE + 0xAF) ++#define REG_SCL2_58_L (REG_SCL2_BASE + 0xB0) ++#define REG_SCL2_58_H (REG_SCL2_BASE + 0xB1) ++#define REG_SCL2_59_L (REG_SCL2_BASE + 0xB2) ++#define REG_SCL2_59_H (REG_SCL2_BASE + 0xB3) ++#define REG_SCL2_5A_L (REG_SCL2_BASE + 0xB4) ++#define REG_SCL2_5A_H (REG_SCL2_BASE + 0xB5) ++#define REG_SCL2_5B_L (REG_SCL2_BASE + 0xB6) ++#define REG_SCL2_5B_H (REG_SCL2_BASE + 0xB7) ++#define REG_SCL2_5C_L (REG_SCL2_BASE + 0xB8) ++#define REG_SCL2_5C_H (REG_SCL2_BASE + 0xB9) ++#define REG_SCL2_5D_L (REG_SCL2_BASE + 0xBA) ++#define REG_SCL2_5D_H (REG_SCL2_BASE + 0xBB) ++#define REG_SCL2_5E_L (REG_SCL2_BASE + 0xBC) ++#define REG_SCL2_5E_H (REG_SCL2_BASE + 0xBD) ++#define REG_SCL2_5F_L (REG_SCL2_BASE + 0xBE) ++#define REG_SCL2_5F_H (REG_SCL2_BASE + 0xBF) ++#define REG_SCL2_60_L (REG_SCL2_BASE + 0xC0) ++#define REG_SCL2_60_H (REG_SCL2_BASE + 0xC1) ++#define REG_SCL2_61_L (REG_SCL2_BASE + 0xC2) ++#define REG_SCL2_61_H (REG_SCL2_BASE + 0xC3) ++#define REG_SCL2_62_L (REG_SCL2_BASE + 0xC4) ++#define REG_SCL2_62_H (REG_SCL2_BASE + 0xC5) ++#define REG_SCL2_63_L (REG_SCL2_BASE + 0xC6) ++#define REG_SCL2_63_H (REG_SCL2_BASE + 0xC7) ++#define REG_SCL2_64_L (REG_SCL2_BASE + 0xC8) ++#define REG_SCL2_64_H (REG_SCL2_BASE + 0xC9) ++#define REG_SCL2_65_L (REG_SCL2_BASE + 0xCA) ++#define REG_SCL2_65_H (REG_SCL2_BASE + 0xCB) ++#define REG_SCL2_66_L (REG_SCL2_BASE + 0xCC) ++#define REG_SCL2_66_H (REG_SCL2_BASE + 0xCD) ++#define REG_SCL2_67_L (REG_SCL2_BASE + 0xCE) ++#define REG_SCL2_67_H (REG_SCL2_BASE + 0xCF) ++#define REG_SCL2_68_L (REG_SCL2_BASE + 0xD0) ++#define REG_SCL2_68_H (REG_SCL2_BASE + 0xD1) ++#define REG_SCL2_69_L (REG_SCL2_BASE + 0xD2) ++#define REG_SCL2_69_H (REG_SCL2_BASE + 0xD3) ++#define REG_SCL2_6A_L (REG_SCL2_BASE + 0xD4) ++#define REG_SCL2_6A_H (REG_SCL2_BASE + 0xD5) ++#define REG_SCL2_6B_L (REG_SCL2_BASE + 0xD6) ++#define REG_SCL2_6B_H (REG_SCL2_BASE + 0xD7) ++#define REG_SCL2_6C_L (REG_SCL2_BASE + 0xD8) ++#define REG_SCL2_6C_H (REG_SCL2_BASE + 0xD9) ++#define REG_SCL2_6D_L (REG_SCL2_BASE + 0xDA) ++#define REG_SCL2_6D_H (REG_SCL2_BASE + 0xDB) ++#define REG_SCL2_6E_L (REG_SCL2_BASE + 0xDC) ++#define REG_SCL2_6E_H (REG_SCL2_BASE + 0xDD) ++#define REG_SCL2_6F_L (REG_SCL2_BASE + 0xDE) ++#define REG_SCL2_6F_H (REG_SCL2_BASE + 0xDF) ++#define REG_SCL2_70_L (REG_SCL2_BASE + 0xE0) ++#define REG_SCL2_70_H (REG_SCL2_BASE + 0xE1) ++#define REG_SCL2_71_L (REG_SCL2_BASE + 0xE2) ++#define REG_SCL2_71_H (REG_SCL2_BASE + 0xE3) ++#define REG_SCL2_72_L (REG_SCL2_BASE + 0xE4) ++#define REG_SCL2_72_H (REG_SCL2_BASE + 0xE5) ++#define REG_SCL2_73_L (REG_SCL2_BASE + 0xE6) ++#define REG_SCL2_73_H (REG_SCL2_BASE + 0xE7) ++#define REG_SCL2_74_L (REG_SCL2_BASE + 0xE8) ++#define REG_SCL2_74_H (REG_SCL2_BASE + 0xE9) ++#define REG_SCL2_75_L (REG_SCL2_BASE + 0xEA) ++#define REG_SCL2_75_H (REG_SCL2_BASE + 0xEB) ++#define REG_SCL2_76_L (REG_SCL2_BASE + 0xEC) ++#define REG_SCL2_76_H (REG_SCL2_BASE + 0xED) ++#define REG_SCL2_77_L (REG_SCL2_BASE + 0xEE) ++#define REG_SCL2_77_H (REG_SCL2_BASE + 0xEF) ++#define REG_SCL2_78_L (REG_SCL2_BASE + 0xF0) ++#define REG_SCL2_78_H (REG_SCL2_BASE + 0xF1) ++#define REG_SCL2_79_L (REG_SCL2_BASE + 0xF2) ++#define REG_SCL2_79_H (REG_SCL2_BASE + 0xF3) ++#define REG_SCL2_7A_L (REG_SCL2_BASE + 0xF4) ++#define REG_SCL2_7A_H (REG_SCL2_BASE + 0xF5) ++#define REG_SCL2_7B_L (REG_SCL2_BASE + 0xF6) ++#define REG_SCL2_7B_H (REG_SCL2_BASE + 0xF7) ++#define REG_SCL2_7C_L (REG_SCL2_BASE + 0xF8) ++#define REG_SCL2_7C_H (REG_SCL2_BASE + 0xF9) ++#define REG_SCL2_7D_L (REG_SCL2_BASE + 0xFA) ++#define REG_SCL2_7D_H (REG_SCL2_BASE + 0xFB) ++#define REG_SCL2_7E_L (REG_SCL2_BASE + 0xFC) ++#define REG_SCL2_7E_H (REG_SCL2_BASE + 0xFD) ++#define REG_SCL2_7F_L (REG_SCL2_BASE + 0xFE) ++#define REG_SCL2_7F_H (REG_SCL2_BASE + 0xFF) ++ ++#define REG_SCL3_00_L (REG_SCL3_BASE + 0x00) ++#define REG_SCL3_00_H (REG_SCL3_BASE + 0x01) ++#define REG_SCL3_01_L (REG_SCL3_BASE + 0x02) ++#define REG_SCL3_01_H (REG_SCL3_BASE + 0x03) ++#define REG_SCL3_02_L (REG_SCL3_BASE + 0x04) ++#define REG_SCL3_02_H (REG_SCL3_BASE + 0x05) ++#define REG_SCL3_03_L (REG_SCL3_BASE + 0x06) ++#define REG_SCL3_03_H (REG_SCL3_BASE + 0x07) ++#define REG_SCL3_04_L (REG_SCL3_BASE + 0x08) ++#define REG_SCL3_04_H (REG_SCL3_BASE + 0x09) ++#define REG_SCL3_05_L (REG_SCL3_BASE + 0x0A) ++#define REG_SCL3_05_H (REG_SCL3_BASE + 0x0B) ++#define REG_SCL3_06_L (REG_SCL3_BASE + 0x0C) ++#define REG_SCL3_06_H (REG_SCL3_BASE + 0x0D) ++#define REG_SCL3_07_L (REG_SCL3_BASE + 0x0E) ++#define REG_SCL3_07_H (REG_SCL3_BASE + 0x0F) ++#define REG_SCL3_08_L (REG_SCL3_BASE + 0x10) ++#define REG_SCL3_08_H (REG_SCL3_BASE + 0x11) ++#define REG_SCL3_09_L (REG_SCL3_BASE + 0x12) ++#define REG_SCL3_09_H (REG_SCL3_BASE + 0x13) ++#define REG_SCL3_0A_L (REG_SCL3_BASE + 0x14) ++#define REG_SCL3_0A_H (REG_SCL3_BASE + 0x15) ++#define REG_SCL3_0B_L (REG_SCL3_BASE + 0x16) ++#define REG_SCL3_0B_H (REG_SCL3_BASE + 0x17) ++#define REG_SCL3_0C_L (REG_SCL3_BASE + 0x18) ++#define REG_SCL3_0C_H (REG_SCL3_BASE + 0x19) ++#define REG_SCL3_0D_L (REG_SCL3_BASE + 0x1A) ++#define REG_SCL3_0D_H (REG_SCL3_BASE + 0x1B) ++#define REG_SCL3_0E_L (REG_SCL3_BASE + 0x1C) ++#define REG_SCL3_0E_H (REG_SCL3_BASE + 0x1D) ++#define REG_SCL3_0F_L (REG_SCL3_BASE + 0x1E) ++#define REG_SCL3_0F_H (REG_SCL3_BASE + 0x1F) ++#define REG_SCL3_10_L (REG_SCL3_BASE + 0x20) ++#define REG_SCL3_10_H (REG_SCL3_BASE + 0x21) ++#define REG_SCL3_11_L (REG_SCL3_BASE + 0x22) ++#define REG_SCL3_11_H (REG_SCL3_BASE + 0x23) ++#define REG_SCL3_12_L (REG_SCL3_BASE + 0x24) ++#define REG_SCL3_12_H (REG_SCL3_BASE + 0x25) ++#define REG_SCL3_13_L (REG_SCL3_BASE + 0x26) ++#define REG_SCL3_13_H (REG_SCL3_BASE + 0x27) ++#define REG_SCL3_14_L (REG_SCL3_BASE + 0x28) ++#define REG_SCL3_14_H (REG_SCL3_BASE + 0x29) ++#define REG_SCL3_15_L (REG_SCL3_BASE + 0x2A) ++#define REG_SCL3_15_H (REG_SCL3_BASE + 0x2B) ++#define REG_SCL3_16_L (REG_SCL3_BASE + 0x2C) ++#define REG_SCL3_16_H (REG_SCL3_BASE + 0x2D) ++#define REG_SCL3_17_L (REG_SCL3_BASE + 0x2E) ++#define REG_SCL3_17_H (REG_SCL3_BASE + 0x2F) ++#define REG_SCL3_18_L (REG_SCL3_BASE + 0x30) ++#define REG_SCL3_18_H (REG_SCL3_BASE + 0x31) ++#define REG_SCL3_19_L (REG_SCL3_BASE + 0x32) ++#define REG_SCL3_19_H (REG_SCL3_BASE + 0x33) ++#define REG_SCL3_1A_L (REG_SCL3_BASE + 0x34) ++#define REG_SCL3_1A_H (REG_SCL3_BASE + 0x35) ++#define REG_SCL3_1B_L (REG_SCL3_BASE + 0x36) ++#define REG_SCL3_1B_H (REG_SCL3_BASE + 0x37) ++#define REG_SCL3_1C_L (REG_SCL3_BASE + 0x38) ++#define REG_SCL3_1C_H (REG_SCL3_BASE + 0x39) ++#define REG_SCL3_1D_L (REG_SCL3_BASE + 0x3A) ++#define REG_SCL3_1D_H (REG_SCL3_BASE + 0x3B) ++#define REG_SCL3_1E_L (REG_SCL3_BASE + 0x3C) ++#define REG_SCL3_1E_H (REG_SCL3_BASE + 0x3D) ++#define REG_SCL3_1F_L (REG_SCL3_BASE + 0x3E) ++#define REG_SCL3_1F_H (REG_SCL3_BASE + 0x3F) ++#define REG_SCL3_20_L (REG_SCL3_BASE + 0x40) ++#define REG_SCL3_20_H (REG_SCL3_BASE + 0x41) ++#define REG_SCL3_21_L (REG_SCL3_BASE + 0x42) ++#define REG_SCL3_21_H (REG_SCL3_BASE + 0x43) ++#define REG_SCL3_22_L (REG_SCL3_BASE + 0x44) ++#define REG_SCL3_22_H (REG_SCL3_BASE + 0x45) ++#define REG_SCL3_23_L (REG_SCL3_BASE + 0x46) ++#define REG_SCL3_23_H (REG_SCL3_BASE + 0x47) ++#define REG_SCL3_24_L (REG_SCL3_BASE + 0x48) ++#define REG_SCL3_24_H (REG_SCL3_BASE + 0x49) ++#define REG_SCL3_25_L (REG_SCL3_BASE + 0x4A) ++#define REG_SCL3_25_H (REG_SCL3_BASE + 0x4B) ++#define REG_SCL3_26_L (REG_SCL3_BASE + 0x4C) ++#define REG_SCL3_26_H (REG_SCL3_BASE + 0x4D) ++#define REG_SCL3_27_L (REG_SCL3_BASE + 0x4E) ++#define REG_SCL3_27_H (REG_SCL3_BASE + 0x4F) ++#define REG_SCL3_28_L (REG_SCL3_BASE + 0x50) ++#define REG_SCL3_28_H (REG_SCL3_BASE + 0x51) ++#define REG_SCL3_29_L (REG_SCL3_BASE + 0x52) ++#define REG_SCL3_29_H (REG_SCL3_BASE + 0x53) ++#define REG_SCL3_2A_L (REG_SCL3_BASE + 0x54) ++#define REG_SCL3_2A_H (REG_SCL3_BASE + 0x55) ++#define REG_SCL3_2B_L (REG_SCL3_BASE + 0x56) ++#define REG_SCL3_2B_H (REG_SCL3_BASE + 0x57) ++#define REG_SCL3_2C_L (REG_SCL3_BASE + 0x58) ++#define REG_SCL3_2C_H (REG_SCL3_BASE + 0x59) ++#define REG_SCL3_2D_L (REG_SCL3_BASE + 0x5A) ++#define REG_SCL3_2D_H (REG_SCL3_BASE + 0x5B) ++#define REG_SCL3_2E_L (REG_SCL3_BASE + 0x5C) ++#define REG_SCL3_2E_H (REG_SCL3_BASE + 0x5D) ++#define REG_SCL3_2F_L (REG_SCL3_BASE + 0x5E) ++#define REG_SCL3_2F_H (REG_SCL3_BASE + 0x5F) ++#define REG_SCL3_30_L (REG_SCL3_BASE + 0x60) ++#define REG_SCL3_30_H (REG_SCL3_BASE + 0x61) ++#define REG_SCL3_31_L (REG_SCL3_BASE + 0x62) ++#define REG_SCL3_31_H (REG_SCL3_BASE + 0x63) ++#define REG_SCL3_32_L (REG_SCL3_BASE + 0x64) ++#define REG_SCL3_32_H (REG_SCL3_BASE + 0x65) ++#define REG_SCL3_33_L (REG_SCL3_BASE + 0x66) ++#define REG_SCL3_33_H (REG_SCL3_BASE + 0x67) ++#define REG_SCL3_34_L (REG_SCL3_BASE + 0x68) ++#define REG_SCL3_34_H (REG_SCL3_BASE + 0x69) ++#define REG_SCL3_35_L (REG_SCL3_BASE + 0x6A) ++#define REG_SCL3_35_H (REG_SCL3_BASE + 0x6B) ++#define REG_SCL3_36_L (REG_SCL3_BASE + 0x6C) ++#define REG_SCL3_36_H (REG_SCL3_BASE + 0x6D) ++#define REG_SCL3_37_L (REG_SCL3_BASE + 0x6E) ++#define REG_SCL3_37_H (REG_SCL3_BASE + 0x6F) ++#define REG_SCL3_38_L (REG_SCL3_BASE + 0x70) ++#define REG_SCL3_38_H (REG_SCL3_BASE + 0x71) ++#define REG_SCL3_39_L (REG_SCL3_BASE + 0x72) ++#define REG_SCL3_39_H (REG_SCL3_BASE + 0x73) ++#define REG_SCL3_3A_L (REG_SCL3_BASE + 0x74) ++#define REG_SCL3_3A_H (REG_SCL3_BASE + 0x75) ++#define REG_SCL3_3B_L (REG_SCL3_BASE + 0x76) ++#define REG_SCL3_3B_H (REG_SCL3_BASE + 0x77) ++#define REG_SCL3_3C_L (REG_SCL3_BASE + 0x78) ++#define REG_SCL3_3C_H (REG_SCL3_BASE + 0x79) ++#define REG_SCL3_3D_L (REG_SCL3_BASE + 0x7A) ++#define REG_SCL3_3D_H (REG_SCL3_BASE + 0x7B) ++#define REG_SCL3_3E_L (REG_SCL3_BASE + 0x7C) ++#define REG_SCL3_3E_H (REG_SCL3_BASE + 0x7D) ++#define REG_SCL3_3F_L (REG_SCL3_BASE + 0x7E) ++#define REG_SCL3_3F_H (REG_SCL3_BASE + 0x7F) ++#define REG_SCL3_40_L (REG_SCL3_BASE + 0x80) ++#define REG_SCL3_40_H (REG_SCL3_BASE + 0x81) ++#define REG_SCL3_41_L (REG_SCL3_BASE + 0x82) ++#define REG_SCL3_41_H (REG_SCL3_BASE + 0x83) ++#define REG_SCL3_42_L (REG_SCL3_BASE + 0x84) ++#define REG_SCL3_42_H (REG_SCL3_BASE + 0x85) ++#define REG_SCL3_43_L (REG_SCL3_BASE + 0x86) ++#define REG_SCL3_43_H (REG_SCL3_BASE + 0x87) ++#define REG_SCL3_44_L (REG_SCL3_BASE + 0x88) ++#define REG_SCL3_44_H (REG_SCL3_BASE + 0x89) ++#define REG_SCL3_45_L (REG_SCL3_BASE + 0x8A) ++#define REG_SCL3_45_H (REG_SCL3_BASE + 0x8B) ++#define REG_SCL3_46_L (REG_SCL3_BASE + 0x8C) ++#define REG_SCL3_46_H (REG_SCL3_BASE + 0x8D) ++#define REG_SCL3_47_L (REG_SCL3_BASE + 0x8E) ++#define REG_SCL3_47_H (REG_SCL3_BASE + 0x8F) ++#define REG_SCL3_48_L (REG_SCL3_BASE + 0x90) ++#define REG_SCL3_48_H (REG_SCL3_BASE + 0x91) ++#define REG_SCL3_49_L (REG_SCL3_BASE + 0x92) ++#define REG_SCL3_49_H (REG_SCL3_BASE + 0x93) ++#define REG_SCL3_4A_L (REG_SCL3_BASE + 0x94) ++#define REG_SCL3_4A_H (REG_SCL3_BASE + 0x95) ++#define REG_SCL3_4B_L (REG_SCL3_BASE + 0x96) ++#define REG_SCL3_4B_H (REG_SCL3_BASE + 0x97) ++#define REG_SCL3_4C_L (REG_SCL3_BASE + 0x98) ++#define REG_SCL3_4C_H (REG_SCL3_BASE + 0x99) ++#define REG_SCL3_4D_L (REG_SCL3_BASE + 0x9A) ++#define REG_SCL3_4D_H (REG_SCL3_BASE + 0x9B) ++#define REG_SCL3_4E_L (REG_SCL3_BASE + 0x9C) ++#define REG_SCL3_4E_H (REG_SCL3_BASE + 0x9D) ++#define REG_SCL3_4F_L (REG_SCL3_BASE + 0x9E) ++#define REG_SCL3_4F_H (REG_SCL3_BASE + 0x9F) ++#define REG_SCL3_50_L (REG_SCL3_BASE + 0xA0) ++#define REG_SCL3_50_H (REG_SCL3_BASE + 0xA1) ++#define REG_SCL3_51_L (REG_SCL3_BASE + 0xA2) ++#define REG_SCL3_51_H (REG_SCL3_BASE + 0xA3) ++#define REG_SCL3_52_L (REG_SCL3_BASE + 0xA4) ++#define REG_SCL3_52_H (REG_SCL3_BASE + 0xA5) ++#define REG_SCL3_53_L (REG_SCL3_BASE + 0xA6) ++#define REG_SCL3_53_H (REG_SCL3_BASE + 0xA7) ++#define REG_SCL3_54_L (REG_SCL3_BASE + 0xA8) ++#define REG_SCL3_54_H (REG_SCL3_BASE + 0xA9) ++#define REG_SCL3_55_L (REG_SCL3_BASE + 0xAA) ++#define REG_SCL3_55_H (REG_SCL3_BASE + 0xAB) ++#define REG_SCL3_56_L (REG_SCL3_BASE + 0xAC) ++#define REG_SCL3_56_H (REG_SCL3_BASE + 0xAD) ++#define REG_SCL3_57_L (REG_SCL3_BASE + 0xAE) ++#define REG_SCL3_57_H (REG_SCL3_BASE + 0xAF) ++#define REG_SCL3_58_L (REG_SCL3_BASE + 0xB0) ++#define REG_SCL3_58_H (REG_SCL3_BASE + 0xB1) ++#define REG_SCL3_59_L (REG_SCL3_BASE + 0xB2) ++#define REG_SCL3_59_H (REG_SCL3_BASE + 0xB3) ++#define REG_SCL3_5A_L (REG_SCL3_BASE + 0xB4) ++#define REG_SCL3_5A_H (REG_SCL3_BASE + 0xB5) ++#define REG_SCL3_5B_L (REG_SCL3_BASE + 0xB6) ++#define REG_SCL3_5B_H (REG_SCL3_BASE + 0xB7) ++#define REG_SCL3_5C_L (REG_SCL3_BASE + 0xB8) ++#define REG_SCL3_5C_H (REG_SCL3_BASE + 0xB9) ++#define REG_SCL3_5D_L (REG_SCL3_BASE + 0xBA) ++#define REG_SCL3_5D_H (REG_SCL3_BASE + 0xBB) ++#define REG_SCL3_5E_L (REG_SCL3_BASE + 0xBC) ++#define REG_SCL3_5E_H (REG_SCL3_BASE + 0xBD) ++#define REG_SCL3_5F_L (REG_SCL3_BASE + 0xBE) ++#define REG_SCL3_5F_H (REG_SCL3_BASE + 0xBF) ++#define REG_SCL3_60_L (REG_SCL3_BASE + 0xC0) ++#define REG_SCL3_60_H (REG_SCL3_BASE + 0xC1) ++#define REG_SCL3_61_L (REG_SCL3_BASE + 0xC2) ++#define REG_SCL3_61_H (REG_SCL3_BASE + 0xC3) ++#define REG_SCL3_62_L (REG_SCL3_BASE + 0xC4) ++#define REG_SCL3_62_H (REG_SCL3_BASE + 0xC5) ++#define REG_SCL3_63_L (REG_SCL3_BASE + 0xC6) ++#define REG_SCL3_63_H (REG_SCL3_BASE + 0xC7) ++#define REG_SCL3_64_L (REG_SCL3_BASE + 0xC8) ++#define REG_SCL3_64_H (REG_SCL3_BASE + 0xC9) ++#define REG_SCL3_65_L (REG_SCL3_BASE + 0xCA) ++#define REG_SCL3_65_H (REG_SCL3_BASE + 0xCB) ++#define REG_SCL3_66_L (REG_SCL3_BASE + 0xCC) ++#define REG_SCL3_66_H (REG_SCL3_BASE + 0xCD) ++#define REG_SCL3_67_L (REG_SCL3_BASE + 0xCE) ++#define REG_SCL3_67_H (REG_SCL3_BASE + 0xCF) ++#define REG_SCL3_68_L (REG_SCL3_BASE + 0xD0) ++#define REG_SCL3_68_H (REG_SCL3_BASE + 0xD1) ++#define REG_SCL3_69_L (REG_SCL3_BASE + 0xD2) ++#define REG_SCL3_69_H (REG_SCL3_BASE + 0xD3) ++#define REG_SCL3_6A_L (REG_SCL3_BASE + 0xD4) ++#define REG_SCL3_6A_H (REG_SCL3_BASE + 0xD5) ++#define REG_SCL3_6B_L (REG_SCL3_BASE + 0xD6) ++#define REG_SCL3_6B_H (REG_SCL3_BASE + 0xD7) ++#define REG_SCL3_6C_L (REG_SCL3_BASE + 0xD8) ++#define REG_SCL3_6C_H (REG_SCL3_BASE + 0xD9) ++#define REG_SCL3_6D_L (REG_SCL3_BASE + 0xDA) ++#define REG_SCL3_6D_H (REG_SCL3_BASE + 0xDB) ++#define REG_SCL3_6E_L (REG_SCL3_BASE + 0xDC) ++#define REG_SCL3_6E_H (REG_SCL3_BASE + 0xDD) ++#define REG_SCL3_6F_L (REG_SCL3_BASE + 0xDE) ++#define REG_SCL3_6F_H (REG_SCL3_BASE + 0xDF) ++#define REG_SCL3_70_L (REG_SCL3_BASE + 0xE0) ++#define REG_SCL3_70_H (REG_SCL3_BASE + 0xE1) ++#define REG_SCL3_71_L (REG_SCL3_BASE + 0xE2) ++#define REG_SCL3_71_H (REG_SCL3_BASE + 0xE3) ++#define REG_SCL3_72_L (REG_SCL3_BASE + 0xE4) ++#define REG_SCL3_72_H (REG_SCL3_BASE + 0xE5) ++#define REG_SCL3_73_L (REG_SCL3_BASE + 0xE6) ++#define REG_SCL3_73_H (REG_SCL3_BASE + 0xE7) ++#define REG_SCL3_74_L (REG_SCL3_BASE + 0xE8) ++#define REG_SCL3_74_H (REG_SCL3_BASE + 0xE9) ++#define REG_SCL3_75_L (REG_SCL3_BASE + 0xEA) ++#define REG_SCL3_75_H (REG_SCL3_BASE + 0xEB) ++#define REG_SCL3_76_L (REG_SCL3_BASE + 0xEC) ++#define REG_SCL3_76_H (REG_SCL3_BASE + 0xED) ++#define REG_SCL3_77_L (REG_SCL3_BASE + 0xEE) ++#define REG_SCL3_77_H (REG_SCL3_BASE + 0xEF) ++#define REG_SCL3_78_L (REG_SCL3_BASE + 0xF0) ++#define REG_SCL3_78_H (REG_SCL3_BASE + 0xF1) ++#define REG_SCL3_79_L (REG_SCL3_BASE + 0xF2) ++#define REG_SCL3_79_H (REG_SCL3_BASE + 0xF3) ++#define REG_SCL3_7A_L (REG_SCL3_BASE + 0xF4) ++#define REG_SCL3_7A_H (REG_SCL3_BASE + 0xF5) ++#define REG_SCL3_7B_L (REG_SCL3_BASE + 0xF6) ++#define REG_SCL3_7B_H (REG_SCL3_BASE + 0xF7) ++#define REG_SCL3_7C_L (REG_SCL3_BASE + 0xF8) ++#define REG_SCL3_7C_H (REG_SCL3_BASE + 0xF9) ++#define REG_SCL3_7D_L (REG_SCL3_BASE + 0xFA) ++#define REG_SCL3_7D_H (REG_SCL3_BASE + 0xFB) ++#define REG_SCL3_7E_L (REG_SCL3_BASE + 0xFC) ++#define REG_SCL3_7E_H (REG_SCL3_BASE + 0xFD) ++#define REG_SCL3_7F_L (REG_SCL3_BASE + 0xFE) ++#define REG_SCL3_7F_H (REG_SCL3_BASE + 0xFF) ++ ++#define REG_VIP_ACE3_00_L (REG_VIP_ACE3_BASE + 0x00) ++#define REG_VIP_ACE3_00_H (REG_VIP_ACE3_BASE + 0x01) ++#define REG_VIP_ACE3_01_L (REG_VIP_ACE3_BASE + 0x02) ++#define REG_VIP_ACE3_01_H (REG_VIP_ACE3_BASE + 0x03) ++#define REG_VIP_ACE3_02_L (REG_VIP_ACE3_BASE + 0x04) ++#define REG_VIP_ACE3_02_H (REG_VIP_ACE3_BASE + 0x05) ++#define REG_VIP_ACE3_03_L (REG_VIP_ACE3_BASE + 0x06) ++#define REG_VIP_ACE3_03_H (REG_VIP_ACE3_BASE + 0x07) ++#define REG_VIP_ACE3_04_L (REG_VIP_ACE3_BASE + 0x08) ++#define REG_VIP_ACE3_04_H (REG_VIP_ACE3_BASE + 0x09) ++#define REG_VIP_ACE3_05_L (REG_VIP_ACE3_BASE + 0x0A) ++#define REG_VIP_ACE3_05_H (REG_VIP_ACE3_BASE + 0x0B) ++#define REG_VIP_ACE3_06_L (REG_VIP_ACE3_BASE + 0x0C) ++#define REG_VIP_ACE3_06_H (REG_VIP_ACE3_BASE + 0x0D) ++#define REG_VIP_ACE3_07_L (REG_VIP_ACE3_BASE + 0x0E) ++#define REG_VIP_ACE3_07_H (REG_VIP_ACE3_BASE + 0x0F) ++#define REG_VIP_ACE3_08_L (REG_VIP_ACE3_BASE + 0x10) ++#define REG_VIP_ACE3_08_H (REG_VIP_ACE3_BASE + 0x11) ++#define REG_VIP_ACE3_09_L (REG_VIP_ACE3_BASE + 0x12) ++#define REG_VIP_ACE3_09_H (REG_VIP_ACE3_BASE + 0x13) ++#define REG_VIP_ACE3_0A_L (REG_VIP_ACE3_BASE + 0x14) ++#define REG_VIP_ACE3_0A_H (REG_VIP_ACE3_BASE + 0x15) ++#define REG_VIP_ACE3_0B_L (REG_VIP_ACE3_BASE + 0x16) ++#define REG_VIP_ACE3_0B_H (REG_VIP_ACE3_BASE + 0x17) ++#define REG_VIP_ACE3_0C_L (REG_VIP_ACE3_BASE + 0x18) ++#define REG_VIP_ACE3_0C_H (REG_VIP_ACE3_BASE + 0x19) ++#define REG_VIP_ACE3_0D_L (REG_VIP_ACE3_BASE + 0x1A) ++#define REG_VIP_ACE3_0D_H (REG_VIP_ACE3_BASE + 0x1B) ++#define REG_VIP_ACE3_0E_L (REG_VIP_ACE3_BASE + 0x1C) ++#define REG_VIP_ACE3_0E_H (REG_VIP_ACE3_BASE + 0x1D) ++#define REG_VIP_ACE3_0F_L (REG_VIP_ACE3_BASE + 0x1E) ++#define REG_VIP_ACE3_0F_H (REG_VIP_ACE3_BASE + 0x1F) ++#define REG_VIP_ACE3_10_L (REG_VIP_ACE3_BASE + 0x20) ++#define REG_VIP_ACE3_10_H (REG_VIP_ACE3_BASE + 0x21) ++#define REG_VIP_ACE3_11_L (REG_VIP_ACE3_BASE + 0x22) ++#define REG_VIP_ACE3_11_H (REG_VIP_ACE3_BASE + 0x23) ++#define REG_VIP_ACE3_12_L (REG_VIP_ACE3_BASE + 0x24) ++#define REG_VIP_ACE3_12_H (REG_VIP_ACE3_BASE + 0x25) ++#define REG_VIP_ACE3_13_L (REG_VIP_ACE3_BASE + 0x26) ++#define REG_VIP_ACE3_13_H (REG_VIP_ACE3_BASE + 0x27) ++#define REG_VIP_ACE3_14_L (REG_VIP_ACE3_BASE + 0x28) ++#define REG_VIP_ACE3_14_H (REG_VIP_ACE3_BASE + 0x29) ++#define REG_VIP_ACE3_15_L (REG_VIP_ACE3_BASE + 0x2A) ++#define REG_VIP_ACE3_15_H (REG_VIP_ACE3_BASE + 0x2B) ++#define REG_VIP_ACE3_16_L (REG_VIP_ACE3_BASE + 0x2C) ++#define REG_VIP_ACE3_16_H (REG_VIP_ACE3_BASE + 0x2D) ++#define REG_VIP_ACE3_17_L (REG_VIP_ACE3_BASE + 0x2E) ++#define REG_VIP_ACE3_17_H (REG_VIP_ACE3_BASE + 0x2F) ++#define REG_VIP_ACE3_18_L (REG_VIP_ACE3_BASE + 0x30) ++#define REG_VIP_ACE3_18_H (REG_VIP_ACE3_BASE + 0x31) ++#define REG_VIP_ACE3_19_L (REG_VIP_ACE3_BASE + 0x32) ++#define REG_VIP_ACE3_19_H (REG_VIP_ACE3_BASE + 0x33) ++#define REG_VIP_ACE3_1A_L (REG_VIP_ACE3_BASE + 0x34) ++#define REG_VIP_ACE3_1A_H (REG_VIP_ACE3_BASE + 0x35) ++#define REG_VIP_ACE3_1B_L (REG_VIP_ACE3_BASE + 0x36) ++#define REG_VIP_ACE3_1B_H (REG_VIP_ACE3_BASE + 0x37) ++#define REG_VIP_ACE3_1C_L (REG_VIP_ACE3_BASE + 0x38) ++#define REG_VIP_ACE3_1C_H (REG_VIP_ACE3_BASE + 0x39) ++#define REG_VIP_ACE3_1D_L (REG_VIP_ACE3_BASE + 0x3A) ++#define REG_VIP_ACE3_1D_H (REG_VIP_ACE3_BASE + 0x3B) ++#define REG_VIP_ACE3_1E_L (REG_VIP_ACE3_BASE + 0x3C) ++#define REG_VIP_ACE3_1E_H (REG_VIP_ACE3_BASE + 0x3D) ++#define REG_VIP_ACE3_1F_L (REG_VIP_ACE3_BASE + 0x3E) ++#define REG_VIP_ACE3_1F_H (REG_VIP_ACE3_BASE + 0x3F) ++#define REG_VIP_ACE3_20_L (REG_VIP_ACE3_BASE + 0x40) ++#define REG_VIP_ACE3_20_H (REG_VIP_ACE3_BASE + 0x41) ++#define REG_VIP_ACE3_21_L (REG_VIP_ACE3_BASE + 0x42) ++#define REG_VIP_ACE3_21_H (REG_VIP_ACE3_BASE + 0x43) ++#define REG_VIP_ACE3_22_L (REG_VIP_ACE3_BASE + 0x44) ++#define REG_VIP_ACE3_22_H (REG_VIP_ACE3_BASE + 0x45) ++#define REG_VIP_ACE3_23_L (REG_VIP_ACE3_BASE + 0x46) ++#define REG_VIP_ACE3_23_H (REG_VIP_ACE3_BASE + 0x47) ++#define REG_VIP_ACE3_24_L (REG_VIP_ACE3_BASE + 0x48) ++#define REG_VIP_ACE3_24_H (REG_VIP_ACE3_BASE + 0x49) ++#define REG_VIP_ACE3_25_L (REG_VIP_ACE3_BASE + 0x4A) ++#define REG_VIP_ACE3_25_H (REG_VIP_ACE3_BASE + 0x4B) ++#define REG_VIP_ACE3_26_L (REG_VIP_ACE3_BASE + 0x4C) ++#define REG_VIP_ACE3_26_H (REG_VIP_ACE3_BASE + 0x4D) ++#define REG_VIP_ACE3_27_L (REG_VIP_ACE3_BASE + 0x4E) ++#define REG_VIP_ACE3_27_H (REG_VIP_ACE3_BASE + 0x4F) ++#define REG_VIP_ACE3_28_L (REG_VIP_ACE3_BASE + 0x50) ++#define REG_VIP_ACE3_28_H (REG_VIP_ACE3_BASE + 0x51) ++#define REG_VIP_ACE3_29_L (REG_VIP_ACE3_BASE + 0x52) ++#define REG_VIP_ACE3_29_H (REG_VIP_ACE3_BASE + 0x53) ++#define REG_VIP_ACE3_2A_L (REG_VIP_ACE3_BASE + 0x54) ++#define REG_VIP_ACE3_2A_H (REG_VIP_ACE3_BASE + 0x55) ++#define REG_VIP_ACE3_2B_L (REG_VIP_ACE3_BASE + 0x56) ++#define REG_VIP_ACE3_2B_H (REG_VIP_ACE3_BASE + 0x57) ++#define REG_VIP_ACE3_2C_L (REG_VIP_ACE3_BASE + 0x58) ++#define REG_VIP_ACE3_2C_H (REG_VIP_ACE3_BASE + 0x59) ++#define REG_VIP_ACE3_2D_L (REG_VIP_ACE3_BASE + 0x5A) ++#define REG_VIP_ACE3_2D_H (REG_VIP_ACE3_BASE + 0x5B) ++#define REG_VIP_ACE3_2E_L (REG_VIP_ACE3_BASE + 0x5C) ++#define REG_VIP_ACE3_2E_H (REG_VIP_ACE3_BASE + 0x5D) ++#define REG_VIP_ACE3_2F_L (REG_VIP_ACE3_BASE + 0x5E) ++#define REG_VIP_ACE3_2F_H (REG_VIP_ACE3_BASE + 0x5F) ++#define REG_VIP_ACE3_30_L (REG_VIP_ACE3_BASE + 0x60) ++#define REG_VIP_ACE3_30_H (REG_VIP_ACE3_BASE + 0x61) ++#define REG_VIP_ACE3_31_L (REG_VIP_ACE3_BASE + 0x62) ++#define REG_VIP_ACE3_31_H (REG_VIP_ACE3_BASE + 0x63) ++#define REG_VIP_ACE3_32_L (REG_VIP_ACE3_BASE + 0x64) ++#define REG_VIP_ACE3_32_H (REG_VIP_ACE3_BASE + 0x65) ++#define REG_VIP_ACE3_33_L (REG_VIP_ACE3_BASE + 0x66) ++#define REG_VIP_ACE3_33_H (REG_VIP_ACE3_BASE + 0x67) ++#define REG_VIP_ACE3_34_L (REG_VIP_ACE3_BASE + 0x68) ++#define REG_VIP_ACE3_34_H (REG_VIP_ACE3_BASE + 0x69) ++#define REG_VIP_ACE3_35_L (REG_VIP_ACE3_BASE + 0x6A) ++#define REG_VIP_ACE3_35_H (REG_VIP_ACE3_BASE + 0x6B) ++#define REG_VIP_ACE3_36_L (REG_VIP_ACE3_BASE + 0x6C) ++#define REG_VIP_ACE3_36_H (REG_VIP_ACE3_BASE + 0x6D) ++#define REG_VIP_ACE3_37_L (REG_VIP_ACE3_BASE + 0x6E) ++#define REG_VIP_ACE3_37_H (REG_VIP_ACE3_BASE + 0x6F) ++#define REG_VIP_ACE3_38_L (REG_VIP_ACE3_BASE + 0x70) ++#define REG_VIP_ACE3_38_H (REG_VIP_ACE3_BASE + 0x71) ++#define REG_VIP_ACE3_39_L (REG_VIP_ACE3_BASE + 0x72) ++#define REG_VIP_ACE3_39_H (REG_VIP_ACE3_BASE + 0x73) ++#define REG_VIP_ACE3_3A_L (REG_VIP_ACE3_BASE + 0x74) ++#define REG_VIP_ACE3_3A_H (REG_VIP_ACE3_BASE + 0x75) ++#define REG_VIP_ACE3_3B_L (REG_VIP_ACE3_BASE + 0x76) ++#define REG_VIP_ACE3_3B_H (REG_VIP_ACE3_BASE + 0x77) ++#define REG_VIP_ACE3_3C_L (REG_VIP_ACE3_BASE + 0x78) ++#define REG_VIP_ACE3_3C_H (REG_VIP_ACE3_BASE + 0x79) ++#define REG_VIP_ACE3_3D_L (REG_VIP_ACE3_BASE + 0x7A) ++#define REG_VIP_ACE3_3D_H (REG_VIP_ACE3_BASE + 0x7B) ++#define REG_VIP_ACE3_3E_L (REG_VIP_ACE3_BASE + 0x7C) ++#define REG_VIP_ACE3_3E_H (REG_VIP_ACE3_BASE + 0x7D) ++#define REG_VIP_ACE3_3F_L (REG_VIP_ACE3_BASE + 0x7E) ++#define REG_VIP_ACE3_3F_H (REG_VIP_ACE3_BASE + 0x7F) ++#define REG_VIP_ACE3_40_L (REG_VIP_ACE3_BASE + 0x80) ++#define REG_VIP_ACE3_40_H (REG_VIP_ACE3_BASE + 0x81) ++#define REG_VIP_ACE3_41_L (REG_VIP_ACE3_BASE + 0x82) ++#define REG_VIP_ACE3_41_H (REG_VIP_ACE3_BASE + 0x83) ++#define REG_VIP_ACE3_42_L (REG_VIP_ACE3_BASE + 0x84) ++#define REG_VIP_ACE3_42_H (REG_VIP_ACE3_BASE + 0x85) ++#define REG_VIP_ACE3_43_L (REG_VIP_ACE3_BASE + 0x86) ++#define REG_VIP_ACE3_43_H (REG_VIP_ACE3_BASE + 0x87) ++#define REG_VIP_ACE3_44_L (REG_VIP_ACE3_BASE + 0x88) ++#define REG_VIP_ACE3_44_H (REG_VIP_ACE3_BASE + 0x89) ++#define REG_VIP_ACE3_45_L (REG_VIP_ACE3_BASE + 0x8A) ++#define REG_VIP_ACE3_45_H (REG_VIP_ACE3_BASE + 0x8B) ++#define REG_VIP_ACE3_46_L (REG_VIP_ACE3_BASE + 0x8C) ++#define REG_VIP_ACE3_46_H (REG_VIP_ACE3_BASE + 0x8D) ++#define REG_VIP_ACE3_47_L (REG_VIP_ACE3_BASE + 0x8E) ++#define REG_VIP_ACE3_47_H (REG_VIP_ACE3_BASE + 0x8F) ++#define REG_VIP_ACE3_48_L (REG_VIP_ACE3_BASE + 0x90) ++#define REG_VIP_ACE3_48_H (REG_VIP_ACE3_BASE + 0x91) ++#define REG_VIP_ACE3_49_L (REG_VIP_ACE3_BASE + 0x92) ++#define REG_VIP_ACE3_49_H (REG_VIP_ACE3_BASE + 0x93) ++#define REG_VIP_ACE3_4A_L (REG_VIP_ACE3_BASE + 0x94) ++#define REG_VIP_ACE3_4A_H (REG_VIP_ACE3_BASE + 0x95) ++#define REG_VIP_ACE3_4B_L (REG_VIP_ACE3_BASE + 0x96) ++#define REG_VIP_ACE3_4B_H (REG_VIP_ACE3_BASE + 0x97) ++#define REG_VIP_ACE3_4C_L (REG_VIP_ACE3_BASE + 0x98) ++#define REG_VIP_ACE3_4C_H (REG_VIP_ACE3_BASE + 0x99) ++#define REG_VIP_ACE3_4D_L (REG_VIP_ACE3_BASE + 0x9A) ++#define REG_VIP_ACE3_4D_H (REG_VIP_ACE3_BASE + 0x9B) ++#define REG_VIP_ACE3_4E_L (REG_VIP_ACE3_BASE + 0x9C) ++#define REG_VIP_ACE3_4E_H (REG_VIP_ACE3_BASE + 0x9D) ++#define REG_VIP_ACE3_4F_L (REG_VIP_ACE3_BASE + 0x9E) ++#define REG_VIP_ACE3_4F_H (REG_VIP_ACE3_BASE + 0x9F) ++#define REG_VIP_ACE3_50_L (REG_VIP_ACE3_BASE + 0xA0) ++#define REG_VIP_ACE3_50_H (REG_VIP_ACE3_BASE + 0xA1) ++#define REG_VIP_ACE3_51_L (REG_VIP_ACE3_BASE + 0xA2) ++#define REG_VIP_ACE3_51_H (REG_VIP_ACE3_BASE + 0xA3) ++#define REG_VIP_ACE3_52_L (REG_VIP_ACE3_BASE + 0xA4) ++#define REG_VIP_ACE3_52_H (REG_VIP_ACE3_BASE + 0xA5) ++#define REG_VIP_ACE3_53_L (REG_VIP_ACE3_BASE + 0xA6) ++#define REG_VIP_ACE3_53_H (REG_VIP_ACE3_BASE + 0xA7) ++#define REG_VIP_ACE3_54_L (REG_VIP_ACE3_BASE + 0xA8) ++#define REG_VIP_ACE3_54_H (REG_VIP_ACE3_BASE + 0xA9) ++#define REG_VIP_ACE3_55_L (REG_VIP_ACE3_BASE + 0xAA) ++#define REG_VIP_ACE3_55_H (REG_VIP_ACE3_BASE + 0xAB) ++#define REG_VIP_ACE3_56_L (REG_VIP_ACE3_BASE + 0xAC) ++#define REG_VIP_ACE3_56_H (REG_VIP_ACE3_BASE + 0xAD) ++#define REG_VIP_ACE3_57_L (REG_VIP_ACE3_BASE + 0xAE) ++#define REG_VIP_ACE3_57_H (REG_VIP_ACE3_BASE + 0xAF) ++#define REG_VIP_ACE3_58_L (REG_VIP_ACE3_BASE + 0xB0) ++#define REG_VIP_ACE3_58_H (REG_VIP_ACE3_BASE + 0xB1) ++#define REG_VIP_ACE3_59_L (REG_VIP_ACE3_BASE + 0xB2) ++#define REG_VIP_ACE3_59_H (REG_VIP_ACE3_BASE + 0xB3) ++#define REG_VIP_ACE3_5A_L (REG_VIP_ACE3_BASE + 0xB4) ++#define REG_VIP_ACE3_5A_H (REG_VIP_ACE3_BASE + 0xB5) ++#define REG_VIP_ACE3_5B_L (REG_VIP_ACE3_BASE + 0xB6) ++#define REG_VIP_ACE3_5B_H (REG_VIP_ACE3_BASE + 0xB7) ++#define REG_VIP_ACE3_5C_L (REG_VIP_ACE3_BASE + 0xB8) ++#define REG_VIP_ACE3_5C_H (REG_VIP_ACE3_BASE + 0xB9) ++#define REG_VIP_ACE3_5D_L (REG_VIP_ACE3_BASE + 0xBA) ++#define REG_VIP_ACE3_5D_H (REG_VIP_ACE3_BASE + 0xBB) ++#define REG_VIP_ACE3_5E_L (REG_VIP_ACE3_BASE + 0xBC) ++#define REG_VIP_ACE3_5E_H (REG_VIP_ACE3_BASE + 0xBD) ++#define REG_VIP_ACE3_5F_L (REG_VIP_ACE3_BASE + 0xBE) ++#define REG_VIP_ACE3_5F_H (REG_VIP_ACE3_BASE + 0xBF) ++#define REG_VIP_ACE3_60_L (REG_VIP_ACE3_BASE + 0xC0) ++#define REG_VIP_ACE3_60_H (REG_VIP_ACE3_BASE + 0xC1) ++#define REG_VIP_ACE3_61_L (REG_VIP_ACE3_BASE + 0xC2) ++#define REG_VIP_ACE3_61_H (REG_VIP_ACE3_BASE + 0xC3) ++#define REG_VIP_ACE3_62_L (REG_VIP_ACE3_BASE + 0xC4) ++#define REG_VIP_ACE3_62_H (REG_VIP_ACE3_BASE + 0xC5) ++#define REG_VIP_ACE3_63_L (REG_VIP_ACE3_BASE + 0xC6) ++#define REG_VIP_ACE3_63_H (REG_VIP_ACE3_BASE + 0xC7) ++#define REG_VIP_ACE3_64_L (REG_VIP_ACE3_BASE + 0xC8) ++#define REG_VIP_ACE3_64_H (REG_VIP_ACE3_BASE + 0xC9) ++#define REG_VIP_ACE3_65_L (REG_VIP_ACE3_BASE + 0xCA) ++#define REG_VIP_ACE3_65_H (REG_VIP_ACE3_BASE + 0xCB) ++#define REG_VIP_ACE3_66_L (REG_VIP_ACE3_BASE + 0xCC) ++#define REG_VIP_ACE3_66_H (REG_VIP_ACE3_BASE + 0xCD) ++#define REG_VIP_ACE3_67_L (REG_VIP_ACE3_BASE + 0xCE) ++#define REG_VIP_ACE3_67_H (REG_VIP_ACE3_BASE + 0xCF) ++#define REG_VIP_ACE3_68_L (REG_VIP_ACE3_BASE + 0xD0) ++#define REG_VIP_ACE3_68_H (REG_VIP_ACE3_BASE + 0xD1) ++#define REG_VIP_ACE3_69_L (REG_VIP_ACE3_BASE + 0xD2) ++#define REG_VIP_ACE3_69_H (REG_VIP_ACE3_BASE + 0xD3) ++#define REG_VIP_ACE3_6A_L (REG_VIP_ACE3_BASE + 0xD4) ++#define REG_VIP_ACE3_6A_H (REG_VIP_ACE3_BASE + 0xD5) ++#define REG_VIP_ACE3_6B_L (REG_VIP_ACE3_BASE + 0xD6) ++#define REG_VIP_ACE3_6B_H (REG_VIP_ACE3_BASE + 0xD7) ++#define REG_VIP_ACE3_6C_L (REG_VIP_ACE3_BASE + 0xD8) ++#define REG_VIP_ACE3_6C_H (REG_VIP_ACE3_BASE + 0xD9) ++#define REG_VIP_ACE3_6D_L (REG_VIP_ACE3_BASE + 0xDA) ++#define REG_VIP_ACE3_6D_H (REG_VIP_ACE3_BASE + 0xDB) ++#define REG_VIP_ACE3_6E_L (REG_VIP_ACE3_BASE + 0xDC) ++#define REG_VIP_ACE3_6E_H (REG_VIP_ACE3_BASE + 0xDD) ++#define REG_VIP_ACE3_6F_L (REG_VIP_ACE3_BASE + 0xDE) ++#define REG_VIP_ACE3_6F_H (REG_VIP_ACE3_BASE + 0xDF) ++#define REG_VIP_ACE3_70_L (REG_VIP_ACE3_BASE + 0xE0) ++#define REG_VIP_ACE3_70_H (REG_VIP_ACE3_BASE + 0xE1) ++#define REG_VIP_ACE3_71_L (REG_VIP_ACE3_BASE + 0xE2) ++#define REG_VIP_ACE3_71_H (REG_VIP_ACE3_BASE + 0xE3) ++#define REG_VIP_ACE3_72_L (REG_VIP_ACE3_BASE + 0xE4) ++#define REG_VIP_ACE3_72_H (REG_VIP_ACE3_BASE + 0xE5) ++#define REG_VIP_ACE3_73_L (REG_VIP_ACE3_BASE + 0xE6) ++#define REG_VIP_ACE3_73_H (REG_VIP_ACE3_BASE + 0xE7) ++#define REG_VIP_ACE3_74_L (REG_VIP_ACE3_BASE + 0xE8) ++#define REG_VIP_ACE3_74_H (REG_VIP_ACE3_BASE + 0xE9) ++#define REG_VIP_ACE3_75_L (REG_VIP_ACE3_BASE + 0xEA) ++#define REG_VIP_ACE3_75_H (REG_VIP_ACE3_BASE + 0xEB) ++#define REG_VIP_ACE3_76_L (REG_VIP_ACE3_BASE + 0xEC) ++#define REG_VIP_ACE3_76_H (REG_VIP_ACE3_BASE + 0xED) ++#define REG_VIP_ACE3_77_L (REG_VIP_ACE3_BASE + 0xEE) ++#define REG_VIP_ACE3_77_H (REG_VIP_ACE3_BASE + 0xEF) ++#define REG_VIP_ACE3_78_L (REG_VIP_ACE3_BASE + 0xF0) ++#define REG_VIP_ACE3_78_H (REG_VIP_ACE3_BASE + 0xF1) ++#define REG_VIP_ACE3_79_L (REG_VIP_ACE3_BASE + 0xF2) ++#define REG_VIP_ACE3_79_H (REG_VIP_ACE3_BASE + 0xF3) ++#define REG_VIP_ACE3_7A_L (REG_VIP_ACE3_BASE + 0xF4) ++#define REG_VIP_ACE3_7A_H (REG_VIP_ACE3_BASE + 0xF5) ++#define REG_VIP_ACE3_7B_L (REG_VIP_ACE3_BASE + 0xF6) ++#define REG_VIP_ACE3_7B_H (REG_VIP_ACE3_BASE + 0xF7) ++#define REG_VIP_ACE3_7C_L (REG_VIP_ACE3_BASE + 0xF8) ++#define REG_VIP_ACE3_7C_H (REG_VIP_ACE3_BASE + 0xF9) ++#define REG_VIP_ACE3_7D_L (REG_VIP_ACE3_BASE + 0xFA) ++#define REG_VIP_ACE3_7D_H (REG_VIP_ACE3_BASE + 0xFB) ++#define REG_VIP_ACE3_7E_L (REG_VIP_ACE3_BASE + 0xFC) ++#define REG_VIP_ACE3_7E_H (REG_VIP_ACE3_BASE + 0xFD) ++#define REG_VIP_ACE3_7F_L (REG_VIP_ACE3_BASE + 0xFE) ++#define REG_VIP_ACE3_7F_H (REG_VIP_ACE3_BASE + 0xFF) ++ ++#define REG_VIP_ACE2_00_L (REG_VIP_ACE2_BASE + 0x00) ++#define REG_VIP_ACE2_00_H (REG_VIP_ACE2_BASE + 0x01) ++#define REG_VIP_ACE2_01_L (REG_VIP_ACE2_BASE + 0x02) ++#define REG_VIP_ACE2_01_H (REG_VIP_ACE2_BASE + 0x03) ++#define REG_VIP_ACE2_02_L (REG_VIP_ACE2_BASE + 0x04) ++#define REG_VIP_ACE2_02_H (REG_VIP_ACE2_BASE + 0x05) ++#define REG_VIP_ACE2_03_L (REG_VIP_ACE2_BASE + 0x06) ++#define REG_VIP_ACE2_03_H (REG_VIP_ACE2_BASE + 0x07) ++#define REG_VIP_ACE2_04_L (REG_VIP_ACE2_BASE + 0x08) ++#define REG_VIP_ACE2_04_H (REG_VIP_ACE2_BASE + 0x09) ++#define REG_VIP_ACE2_05_L (REG_VIP_ACE2_BASE + 0x0A) ++#define REG_VIP_ACE2_05_H (REG_VIP_ACE2_BASE + 0x0B) ++#define REG_VIP_ACE2_06_L (REG_VIP_ACE2_BASE + 0x0C) ++#define REG_VIP_ACE2_06_H (REG_VIP_ACE2_BASE + 0x0D) ++#define REG_VIP_ACE2_07_L (REG_VIP_ACE2_BASE + 0x0E) ++#define REG_VIP_ACE2_07_H (REG_VIP_ACE2_BASE + 0x0F) ++#define REG_VIP_ACE2_08_L (REG_VIP_ACE2_BASE + 0x10) ++#define REG_VIP_ACE2_08_H (REG_VIP_ACE2_BASE + 0x11) ++#define REG_VIP_ACE2_09_L (REG_VIP_ACE2_BASE + 0x12) ++#define REG_VIP_ACE2_09_H (REG_VIP_ACE2_BASE + 0x13) ++#define REG_VIP_ACE2_0A_L (REG_VIP_ACE2_BASE + 0x14) ++#define REG_VIP_ACE2_0A_H (REG_VIP_ACE2_BASE + 0x15) ++#define REG_VIP_ACE2_0B_L (REG_VIP_ACE2_BASE + 0x16) ++#define REG_VIP_ACE2_0B_H (REG_VIP_ACE2_BASE + 0x17) ++#define REG_VIP_ACE2_0C_L (REG_VIP_ACE2_BASE + 0x18) ++#define REG_VIP_ACE2_0C_H (REG_VIP_ACE2_BASE + 0x19) ++#define REG_VIP_ACE2_0D_L (REG_VIP_ACE2_BASE + 0x1A) ++#define REG_VIP_ACE2_0D_H (REG_VIP_ACE2_BASE + 0x1B) ++#define REG_VIP_ACE2_0E_L (REG_VIP_ACE2_BASE + 0x1C) ++#define REG_VIP_ACE2_0E_H (REG_VIP_ACE2_BASE + 0x1D) ++#define REG_VIP_ACE2_0F_L (REG_VIP_ACE2_BASE + 0x1E) ++#define REG_VIP_ACE2_0F_H (REG_VIP_ACE2_BASE + 0x1F) ++#define REG_VIP_ACE2_10_L (REG_VIP_ACE2_BASE + 0x20) ++#define REG_VIP_ACE2_10_H (REG_VIP_ACE2_BASE + 0x21) ++#define REG_VIP_ACE2_11_L (REG_VIP_ACE2_BASE + 0x22) ++#define REG_VIP_ACE2_11_H (REG_VIP_ACE2_BASE + 0x23) ++#define REG_VIP_ACE2_12_L (REG_VIP_ACE2_BASE + 0x24) ++#define REG_VIP_ACE2_12_H (REG_VIP_ACE2_BASE + 0x25) ++#define REG_VIP_ACE2_13_L (REG_VIP_ACE2_BASE + 0x26) ++#define REG_VIP_ACE2_13_H (REG_VIP_ACE2_BASE + 0x27) ++#define REG_VIP_ACE2_14_L (REG_VIP_ACE2_BASE + 0x28) ++#define REG_VIP_ACE2_14_H (REG_VIP_ACE2_BASE + 0x29) ++#define REG_VIP_ACE2_15_L (REG_VIP_ACE2_BASE + 0x2A) ++#define REG_VIP_ACE2_15_H (REG_VIP_ACE2_BASE + 0x2B) ++#define REG_VIP_ACE2_16_L (REG_VIP_ACE2_BASE + 0x2C) ++#define REG_VIP_ACE2_16_H (REG_VIP_ACE2_BASE + 0x2D) ++#define REG_VIP_ACE2_17_L (REG_VIP_ACE2_BASE + 0x2E) ++#define REG_VIP_ACE2_17_H (REG_VIP_ACE2_BASE + 0x2F) ++#define REG_VIP_ACE2_18_L (REG_VIP_ACE2_BASE + 0x30) ++#define REG_VIP_ACE2_18_H (REG_VIP_ACE2_BASE + 0x31) ++#define REG_VIP_ACE2_19_L (REG_VIP_ACE2_BASE + 0x32) ++#define REG_VIP_ACE2_19_H (REG_VIP_ACE2_BASE + 0x33) ++#define REG_VIP_ACE2_1A_L (REG_VIP_ACE2_BASE + 0x34) ++#define REG_VIP_ACE2_1A_H (REG_VIP_ACE2_BASE + 0x35) ++#define REG_VIP_ACE2_1B_L (REG_VIP_ACE2_BASE + 0x36) ++#define REG_VIP_ACE2_1B_H (REG_VIP_ACE2_BASE + 0x37) ++#define REG_VIP_ACE2_1C_L (REG_VIP_ACE2_BASE + 0x38) ++#define REG_VIP_ACE2_1C_H (REG_VIP_ACE2_BASE + 0x39) ++#define REG_VIP_ACE2_1D_L (REG_VIP_ACE2_BASE + 0x3A) ++#define REG_VIP_ACE2_1D_H (REG_VIP_ACE2_BASE + 0x3B) ++#define REG_VIP_ACE2_1E_L (REG_VIP_ACE2_BASE + 0x3C) ++#define REG_VIP_ACE2_1E_H (REG_VIP_ACE2_BASE + 0x3D) ++#define REG_VIP_ACE2_1F_L (REG_VIP_ACE2_BASE + 0x3E) ++#define REG_VIP_ACE2_1F_H (REG_VIP_ACE2_BASE + 0x3F) ++#define REG_VIP_ACE2_20_L (REG_VIP_ACE2_BASE + 0x40) ++#define REG_VIP_ACE2_20_H (REG_VIP_ACE2_BASE + 0x41) ++#define REG_VIP_ACE2_21_L (REG_VIP_ACE2_BASE + 0x42) ++#define REG_VIP_ACE2_21_H (REG_VIP_ACE2_BASE + 0x43) ++#define REG_VIP_ACE2_22_L (REG_VIP_ACE2_BASE + 0x44) ++#define REG_VIP_ACE2_22_H (REG_VIP_ACE2_BASE + 0x45) ++#define REG_VIP_ACE2_23_L (REG_VIP_ACE2_BASE + 0x46) ++#define REG_VIP_ACE2_23_H (REG_VIP_ACE2_BASE + 0x47) ++#define REG_VIP_ACE2_24_L (REG_VIP_ACE2_BASE + 0x48) ++#define REG_VIP_ACE2_24_H (REG_VIP_ACE2_BASE + 0x49) ++#define REG_VIP_ACE2_25_L (REG_VIP_ACE2_BASE + 0x4A) ++#define REG_VIP_ACE2_25_H (REG_VIP_ACE2_BASE + 0x4B) ++#define REG_VIP_ACE2_26_L (REG_VIP_ACE2_BASE + 0x4C) ++#define REG_VIP_ACE2_26_H (REG_VIP_ACE2_BASE + 0x4D) ++#define REG_VIP_ACE2_27_L (REG_VIP_ACE2_BASE + 0x4E) ++#define REG_VIP_ACE2_27_H (REG_VIP_ACE2_BASE + 0x4F) ++#define REG_VIP_ACE2_28_L (REG_VIP_ACE2_BASE + 0x50) ++#define REG_VIP_ACE2_28_H (REG_VIP_ACE2_BASE + 0x51) ++#define REG_VIP_ACE2_29_L (REG_VIP_ACE2_BASE + 0x52) ++#define REG_VIP_ACE2_29_H (REG_VIP_ACE2_BASE + 0x53) ++#define REG_VIP_ACE2_2A_L (REG_VIP_ACE2_BASE + 0x54) ++#define REG_VIP_ACE2_2A_H (REG_VIP_ACE2_BASE + 0x55) ++#define REG_VIP_ACE2_2B_L (REG_VIP_ACE2_BASE + 0x56) ++#define REG_VIP_ACE2_2B_H (REG_VIP_ACE2_BASE + 0x57) ++#define REG_VIP_ACE2_2C_L (REG_VIP_ACE2_BASE + 0x58) ++#define REG_VIP_ACE2_2C_H (REG_VIP_ACE2_BASE + 0x59) ++#define REG_VIP_ACE2_2D_L (REG_VIP_ACE2_BASE + 0x5A) ++#define REG_VIP_ACE2_2D_H (REG_VIP_ACE2_BASE + 0x5B) ++#define REG_VIP_ACE2_2E_L (REG_VIP_ACE2_BASE + 0x5C) ++#define REG_VIP_ACE2_2E_H (REG_VIP_ACE2_BASE + 0x5D) ++#define REG_VIP_ACE2_2F_L (REG_VIP_ACE2_BASE + 0x5E) ++#define REG_VIP_ACE2_2F_H (REG_VIP_ACE2_BASE + 0x5F) ++#define REG_VIP_ACE2_30_L (REG_VIP_ACE2_BASE + 0x60) ++#define REG_VIP_ACE2_30_H (REG_VIP_ACE2_BASE + 0x61) ++#define REG_VIP_ACE2_31_L (REG_VIP_ACE2_BASE + 0x62) ++#define REG_VIP_ACE2_31_H (REG_VIP_ACE2_BASE + 0x63) ++#define REG_VIP_ACE2_32_L (REG_VIP_ACE2_BASE + 0x64) ++#define REG_VIP_ACE2_32_H (REG_VIP_ACE2_BASE + 0x65) ++#define REG_VIP_ACE2_33_L (REG_VIP_ACE2_BASE + 0x66) ++#define REG_VIP_ACE2_33_H (REG_VIP_ACE2_BASE + 0x67) ++#define REG_VIP_ACE2_34_L (REG_VIP_ACE2_BASE + 0x68) ++#define REG_VIP_ACE2_34_H (REG_VIP_ACE2_BASE + 0x69) ++#define REG_VIP_ACE2_35_L (REG_VIP_ACE2_BASE + 0x6A) ++#define REG_VIP_ACE2_35_H (REG_VIP_ACE2_BASE + 0x6B) ++#define REG_VIP_ACE2_36_L (REG_VIP_ACE2_BASE + 0x6C) ++#define REG_VIP_ACE2_36_H (REG_VIP_ACE2_BASE + 0x6D) ++#define REG_VIP_ACE2_37_L (REG_VIP_ACE2_BASE + 0x6E) ++#define REG_VIP_ACE2_37_H (REG_VIP_ACE2_BASE + 0x6F) ++#define REG_VIP_ACE2_38_L (REG_VIP_ACE2_BASE + 0x70) ++#define REG_VIP_ACE2_38_H (REG_VIP_ACE2_BASE + 0x71) ++#define REG_VIP_ACE2_39_L (REG_VIP_ACE2_BASE + 0x72) ++#define REG_VIP_ACE2_39_H (REG_VIP_ACE2_BASE + 0x73) ++#define REG_VIP_ACE2_3A_L (REG_VIP_ACE2_BASE + 0x74) ++#define REG_VIP_ACE2_3A_H (REG_VIP_ACE2_BASE + 0x75) ++#define REG_VIP_ACE2_3B_L (REG_VIP_ACE2_BASE + 0x76) ++#define REG_VIP_ACE2_3B_H (REG_VIP_ACE2_BASE + 0x77) ++#define REG_VIP_ACE2_3C_L (REG_VIP_ACE2_BASE + 0x78) ++#define REG_VIP_ACE2_3C_H (REG_VIP_ACE2_BASE + 0x79) ++#define REG_VIP_ACE2_3D_L (REG_VIP_ACE2_BASE + 0x7A) ++#define REG_VIP_ACE2_3D_H (REG_VIP_ACE2_BASE + 0x7B) ++#define REG_VIP_ACE2_3E_L (REG_VIP_ACE2_BASE + 0x7C) ++#define REG_VIP_ACE2_3E_H (REG_VIP_ACE2_BASE + 0x7D) ++#define REG_VIP_ACE2_3F_L (REG_VIP_ACE2_BASE + 0x7E) ++#define REG_VIP_ACE2_3F_H (REG_VIP_ACE2_BASE + 0x7F) ++#define REG_VIP_ACE2_40_L (REG_VIP_ACE2_BASE + 0x80) ++#define REG_VIP_ACE2_40_H (REG_VIP_ACE2_BASE + 0x81) ++#define REG_VIP_ACE2_41_L (REG_VIP_ACE2_BASE + 0x82) ++#define REG_VIP_ACE2_41_H (REG_VIP_ACE2_BASE + 0x83) ++#define REG_VIP_ACE2_42_L (REG_VIP_ACE2_BASE + 0x84) ++#define REG_VIP_ACE2_42_H (REG_VIP_ACE2_BASE + 0x85) ++#define REG_VIP_ACE2_43_L (REG_VIP_ACE2_BASE + 0x86) ++#define REG_VIP_ACE2_43_H (REG_VIP_ACE2_BASE + 0x87) ++#define REG_VIP_ACE2_44_L (REG_VIP_ACE2_BASE + 0x88) ++#define REG_VIP_ACE2_44_H (REG_VIP_ACE2_BASE + 0x89) ++#define REG_VIP_ACE2_45_L (REG_VIP_ACE2_BASE + 0x8A) ++#define REG_VIP_ACE2_45_H (REG_VIP_ACE2_BASE + 0x8B) ++#define REG_VIP_ACE2_46_L (REG_VIP_ACE2_BASE + 0x8C) ++#define REG_VIP_ACE2_46_H (REG_VIP_ACE2_BASE + 0x8D) ++#define REG_VIP_ACE2_47_L (REG_VIP_ACE2_BASE + 0x8E) ++#define REG_VIP_ACE2_47_H (REG_VIP_ACE2_BASE + 0x8F) ++#define REG_VIP_ACE2_48_L (REG_VIP_ACE2_BASE + 0x90) ++#define REG_VIP_ACE2_48_H (REG_VIP_ACE2_BASE + 0x91) ++#define REG_VIP_ACE2_49_L (REG_VIP_ACE2_BASE + 0x92) ++#define REG_VIP_ACE2_49_H (REG_VIP_ACE2_BASE + 0x93) ++#define REG_VIP_ACE2_4A_L (REG_VIP_ACE2_BASE + 0x94) ++#define REG_VIP_ACE2_4A_H (REG_VIP_ACE2_BASE + 0x95) ++#define REG_VIP_ACE2_4B_L (REG_VIP_ACE2_BASE + 0x96) ++#define REG_VIP_ACE2_4B_H (REG_VIP_ACE2_BASE + 0x97) ++#define REG_VIP_ACE2_4C_L (REG_VIP_ACE2_BASE + 0x98) ++#define REG_VIP_ACE2_4C_H (REG_VIP_ACE2_BASE + 0x99) ++#define REG_VIP_ACE2_4D_L (REG_VIP_ACE2_BASE + 0x9A) ++#define REG_VIP_ACE2_4D_H (REG_VIP_ACE2_BASE + 0x9B) ++#define REG_VIP_ACE2_4E_L (REG_VIP_ACE2_BASE + 0x9C) ++#define REG_VIP_ACE2_4E_H (REG_VIP_ACE2_BASE + 0x9D) ++#define REG_VIP_ACE2_4F_L (REG_VIP_ACE2_BASE + 0x9E) ++#define REG_VIP_ACE2_4F_H (REG_VIP_ACE2_BASE + 0x9F) ++#define REG_VIP_ACE2_50_L (REG_VIP_ACE2_BASE + 0xA0) ++#define REG_VIP_ACE2_50_H (REG_VIP_ACE2_BASE + 0xA1) ++#define REG_VIP_ACE2_51_L (REG_VIP_ACE2_BASE + 0xA2) ++#define REG_VIP_ACE2_51_H (REG_VIP_ACE2_BASE + 0xA3) ++#define REG_VIP_ACE2_52_L (REG_VIP_ACE2_BASE + 0xA4) ++#define REG_VIP_ACE2_52_H (REG_VIP_ACE2_BASE + 0xA5) ++#define REG_VIP_ACE2_53_L (REG_VIP_ACE2_BASE + 0xA6) ++#define REG_VIP_ACE2_53_H (REG_VIP_ACE2_BASE + 0xA7) ++#define REG_VIP_ACE2_54_L (REG_VIP_ACE2_BASE + 0xA8) ++#define REG_VIP_ACE2_54_H (REG_VIP_ACE2_BASE + 0xA9) ++#define REG_VIP_ACE2_55_L (REG_VIP_ACE2_BASE + 0xAA) ++#define REG_VIP_ACE2_55_H (REG_VIP_ACE2_BASE + 0xAB) ++#define REG_VIP_ACE2_56_L (REG_VIP_ACE2_BASE + 0xAC) ++#define REG_VIP_ACE2_56_H (REG_VIP_ACE2_BASE + 0xAD) ++#define REG_VIP_ACE2_57_L (REG_VIP_ACE2_BASE + 0xAE) ++#define REG_VIP_ACE2_57_H (REG_VIP_ACE2_BASE + 0xAF) ++#define REG_VIP_ACE2_58_L (REG_VIP_ACE2_BASE + 0xB0) ++#define REG_VIP_ACE2_58_H (REG_VIP_ACE2_BASE + 0xB1) ++#define REG_VIP_ACE2_59_L (REG_VIP_ACE2_BASE + 0xB2) ++#define REG_VIP_ACE2_59_H (REG_VIP_ACE2_BASE + 0xB3) ++#define REG_VIP_ACE2_5A_L (REG_VIP_ACE2_BASE + 0xB4) ++#define REG_VIP_ACE2_5A_H (REG_VIP_ACE2_BASE + 0xB5) ++#define REG_VIP_ACE2_5B_L (REG_VIP_ACE2_BASE + 0xB6) ++#define REG_VIP_ACE2_5B_H (REG_VIP_ACE2_BASE + 0xB7) ++#define REG_VIP_ACE2_5C_L (REG_VIP_ACE2_BASE + 0xB8) ++#define REG_VIP_ACE2_5C_H (REG_VIP_ACE2_BASE + 0xB9) ++#define REG_VIP_ACE2_5D_L (REG_VIP_ACE2_BASE + 0xBA) ++#define REG_VIP_ACE2_5D_H (REG_VIP_ACE2_BASE + 0xBB) ++#define REG_VIP_ACE2_5E_L (REG_VIP_ACE2_BASE + 0xBC) ++#define REG_VIP_ACE2_5E_H (REG_VIP_ACE2_BASE + 0xBD) ++#define REG_VIP_ACE2_5F_L (REG_VIP_ACE2_BASE + 0xBE) ++#define REG_VIP_ACE2_5F_H (REG_VIP_ACE2_BASE + 0xBF) ++#define REG_VIP_ACE2_60_L (REG_VIP_ACE2_BASE + 0xC0) ++#define REG_VIP_ACE2_60_H (REG_VIP_ACE2_BASE + 0xC1) ++#define REG_VIP_ACE2_61_L (REG_VIP_ACE2_BASE + 0xC2) ++#define REG_VIP_ACE2_61_H (REG_VIP_ACE2_BASE + 0xC3) ++#define REG_VIP_ACE2_62_L (REG_VIP_ACE2_BASE + 0xC4) ++#define REG_VIP_ACE2_62_H (REG_VIP_ACE2_BASE + 0xC5) ++#define REG_VIP_ACE2_63_L (REG_VIP_ACE2_BASE + 0xC6) ++#define REG_VIP_ACE2_63_H (REG_VIP_ACE2_BASE + 0xC7) ++#define REG_VIP_ACE2_64_L (REG_VIP_ACE2_BASE + 0xC8) ++#define REG_VIP_ACE2_64_H (REG_VIP_ACE2_BASE + 0xC9) ++#define REG_VIP_ACE2_65_L (REG_VIP_ACE2_BASE + 0xCA) ++#define REG_VIP_ACE2_65_H (REG_VIP_ACE2_BASE + 0xCB) ++#define REG_VIP_ACE2_66_L (REG_VIP_ACE2_BASE + 0xCC) ++#define REG_VIP_ACE2_66_H (REG_VIP_ACE2_BASE + 0xCD) ++#define REG_VIP_ACE2_67_L (REG_VIP_ACE2_BASE + 0xCE) ++#define REG_VIP_ACE2_67_H (REG_VIP_ACE2_BASE + 0xCF) ++#define REG_VIP_ACE2_68_L (REG_VIP_ACE2_BASE + 0xD0) ++#define REG_VIP_ACE2_68_H (REG_VIP_ACE2_BASE + 0xD1) ++#define REG_VIP_ACE2_69_L (REG_VIP_ACE2_BASE + 0xD2) ++#define REG_VIP_ACE2_69_H (REG_VIP_ACE2_BASE + 0xD3) ++#define REG_VIP_ACE2_6A_L (REG_VIP_ACE2_BASE + 0xD4) ++#define REG_VIP_ACE2_6A_H (REG_VIP_ACE2_BASE + 0xD5) ++#define REG_VIP_ACE2_6B_L (REG_VIP_ACE2_BASE + 0xD6) ++#define REG_VIP_ACE2_6B_H (REG_VIP_ACE2_BASE + 0xD7) ++#define REG_VIP_ACE2_6C_L (REG_VIP_ACE2_BASE + 0xD8) ++#define REG_VIP_ACE2_6C_H (REG_VIP_ACE2_BASE + 0xD9) ++#define REG_VIP_ACE2_6D_L (REG_VIP_ACE2_BASE + 0xDA) ++#define REG_VIP_ACE2_6D_H (REG_VIP_ACE2_BASE + 0xDB) ++#define REG_VIP_ACE2_6E_L (REG_VIP_ACE2_BASE + 0xDC) ++#define REG_VIP_ACE2_6E_H (REG_VIP_ACE2_BASE + 0xDD) ++#define REG_VIP_ACE2_6F_L (REG_VIP_ACE2_BASE + 0xDE) ++#define REG_VIP_ACE2_6F_H (REG_VIP_ACE2_BASE + 0xDF) ++#define REG_VIP_ACE2_70_L (REG_VIP_ACE2_BASE + 0xE0) ++#define REG_VIP_ACE2_70_H (REG_VIP_ACE2_BASE + 0xE1) ++#define REG_VIP_ACE2_71_L (REG_VIP_ACE2_BASE + 0xE2) ++#define REG_VIP_ACE2_71_H (REG_VIP_ACE2_BASE + 0xE3) ++#define REG_VIP_ACE2_72_L (REG_VIP_ACE2_BASE + 0xE4) ++#define REG_VIP_ACE2_72_H (REG_VIP_ACE2_BASE + 0xE5) ++#define REG_VIP_ACE2_73_L (REG_VIP_ACE2_BASE + 0xE6) ++#define REG_VIP_ACE2_73_H (REG_VIP_ACE2_BASE + 0xE7) ++#define REG_VIP_ACE2_74_L (REG_VIP_ACE2_BASE + 0xE8) ++#define REG_VIP_ACE2_74_H (REG_VIP_ACE2_BASE + 0xE9) ++#define REG_VIP_ACE2_75_L (REG_VIP_ACE2_BASE + 0xEA) ++#define REG_VIP_ACE2_75_H (REG_VIP_ACE2_BASE + 0xEB) ++#define REG_VIP_ACE2_76_L (REG_VIP_ACE2_BASE + 0xEC) ++#define REG_VIP_ACE2_76_H (REG_VIP_ACE2_BASE + 0xED) ++#define REG_VIP_ACE2_77_L (REG_VIP_ACE2_BASE + 0xEE) ++#define REG_VIP_ACE2_77_H (REG_VIP_ACE2_BASE + 0xEF) ++#define REG_VIP_ACE2_78_L (REG_VIP_ACE2_BASE + 0xF0) ++#define REG_VIP_ACE2_78_H (REG_VIP_ACE2_BASE + 0xF1) ++#define REG_VIP_ACE2_79_L (REG_VIP_ACE2_BASE + 0xF2) ++#define REG_VIP_ACE2_79_H (REG_VIP_ACE2_BASE + 0xF3) ++#define REG_VIP_ACE2_7A_L (REG_VIP_ACE2_BASE + 0xF4) ++#define REG_VIP_ACE2_7A_H (REG_VIP_ACE2_BASE + 0xF5) ++#define REG_VIP_ACE2_7B_L (REG_VIP_ACE2_BASE + 0xF6) ++#define REG_VIP_ACE2_7B_H (REG_VIP_ACE2_BASE + 0xF7) ++#define REG_VIP_ACE2_7C_L (REG_VIP_ACE2_BASE + 0xF8) ++#define REG_VIP_ACE2_7C_H (REG_VIP_ACE2_BASE + 0xF9) ++#define REG_VIP_ACE2_7D_L (REG_VIP_ACE2_BASE + 0xFA) ++#define REG_VIP_ACE2_7D_H (REG_VIP_ACE2_BASE + 0xFB) ++#define REG_VIP_ACE2_7E_L (REG_VIP_ACE2_BASE + 0xFC) ++#define REG_VIP_ACE2_7E_H (REG_VIP_ACE2_BASE + 0xFD) ++#define REG_VIP_ACE2_7F_L (REG_VIP_ACE2_BASE + 0xFE) ++#define REG_VIP_ACE2_7F_H (REG_VIP_ACE2_BASE + 0xFF) ++ ++#define REG_VIP_ACE_00_L (REG_VIP_ACE_BASE + 0x00) ++#define REG_VIP_ACE_00_H (REG_VIP_ACE_BASE + 0x01) ++#define REG_VIP_ACE_01_L (REG_VIP_ACE_BASE + 0x02) ++#define REG_VIP_ACE_01_H (REG_VIP_ACE_BASE + 0x03) ++#define REG_VIP_ACE_02_L (REG_VIP_ACE_BASE + 0x04) ++#define REG_VIP_ACE_02_H (REG_VIP_ACE_BASE + 0x05) ++#define REG_VIP_ACE_03_L (REG_VIP_ACE_BASE + 0x06) ++#define REG_VIP_ACE_03_H (REG_VIP_ACE_BASE + 0x07) ++#define REG_VIP_ACE_04_L (REG_VIP_ACE_BASE + 0x08) ++#define REG_VIP_ACE_04_H (REG_VIP_ACE_BASE + 0x09) ++#define REG_VIP_ACE_05_L (REG_VIP_ACE_BASE + 0x0A) ++#define REG_VIP_ACE_05_H (REG_VIP_ACE_BASE + 0x0B) ++#define REG_VIP_ACE_06_L (REG_VIP_ACE_BASE + 0x0C) ++#define REG_VIP_ACE_06_H (REG_VIP_ACE_BASE + 0x0D) ++#define REG_VIP_ACE_07_L (REG_VIP_ACE_BASE + 0x0E) ++#define REG_VIP_ACE_07_H (REG_VIP_ACE_BASE + 0x0F) ++#define REG_VIP_ACE_08_L (REG_VIP_ACE_BASE + 0x10) ++#define REG_VIP_ACE_08_H (REG_VIP_ACE_BASE + 0x11) ++#define REG_VIP_ACE_09_L (REG_VIP_ACE_BASE + 0x12) ++#define REG_VIP_ACE_09_H (REG_VIP_ACE_BASE + 0x13) ++#define REG_VIP_ACE_0A_L (REG_VIP_ACE_BASE + 0x14) ++#define REG_VIP_ACE_0A_H (REG_VIP_ACE_BASE + 0x15) ++#define REG_VIP_ACE_0B_L (REG_VIP_ACE_BASE + 0x16) ++#define REG_VIP_ACE_0B_H (REG_VIP_ACE_BASE + 0x17) ++#define REG_VIP_ACE_0C_L (REG_VIP_ACE_BASE + 0x18) ++#define REG_VIP_ACE_0C_H (REG_VIP_ACE_BASE + 0x19) ++#define REG_VIP_ACE_0D_L (REG_VIP_ACE_BASE + 0x1A) ++#define REG_VIP_ACE_0D_H (REG_VIP_ACE_BASE + 0x1B) ++#define REG_VIP_ACE_0E_L (REG_VIP_ACE_BASE + 0x1C) ++#define REG_VIP_ACE_0E_H (REG_VIP_ACE_BASE + 0x1D) ++#define REG_VIP_ACE_0F_L (REG_VIP_ACE_BASE + 0x1E) ++#define REG_VIP_ACE_0F_H (REG_VIP_ACE_BASE + 0x1F) ++#define REG_VIP_ACE_10_L (REG_VIP_ACE_BASE + 0x20) ++#define REG_VIP_ACE_10_H (REG_VIP_ACE_BASE + 0x21) ++#define REG_VIP_ACE_11_L (REG_VIP_ACE_BASE + 0x22) ++#define REG_VIP_ACE_11_H (REG_VIP_ACE_BASE + 0x23) ++#define REG_VIP_ACE_12_L (REG_VIP_ACE_BASE + 0x24) ++#define REG_VIP_ACE_12_H (REG_VIP_ACE_BASE + 0x25) ++#define REG_VIP_ACE_13_L (REG_VIP_ACE_BASE + 0x26) ++#define REG_VIP_ACE_13_H (REG_VIP_ACE_BASE + 0x27) ++#define REG_VIP_ACE_14_L (REG_VIP_ACE_BASE + 0x28) ++#define REG_VIP_ACE_14_H (REG_VIP_ACE_BASE + 0x29) ++#define REG_VIP_ACE_15_L (REG_VIP_ACE_BASE + 0x2A) ++#define REG_VIP_ACE_15_H (REG_VIP_ACE_BASE + 0x2B) ++#define REG_VIP_ACE_16_L (REG_VIP_ACE_BASE + 0x2C) ++#define REG_VIP_ACE_16_H (REG_VIP_ACE_BASE + 0x2D) ++#define REG_VIP_ACE_17_L (REG_VIP_ACE_BASE + 0x2E) ++#define REG_VIP_ACE_17_H (REG_VIP_ACE_BASE + 0x2F) ++#define REG_VIP_ACE_18_L (REG_VIP_ACE_BASE + 0x30) ++#define REG_VIP_ACE_18_H (REG_VIP_ACE_BASE + 0x31) ++#define REG_VIP_ACE_19_L (REG_VIP_ACE_BASE + 0x32) ++#define REG_VIP_ACE_19_H (REG_VIP_ACE_BASE + 0x33) ++#define REG_VIP_ACE_1A_L (REG_VIP_ACE_BASE + 0x34) ++#define REG_VIP_ACE_1A_H (REG_VIP_ACE_BASE + 0x35) ++#define REG_VIP_ACE_1B_L (REG_VIP_ACE_BASE + 0x36) ++#define REG_VIP_ACE_1B_H (REG_VIP_ACE_BASE + 0x37) ++#define REG_VIP_ACE_1C_L (REG_VIP_ACE_BASE + 0x38) ++#define REG_VIP_ACE_1C_H (REG_VIP_ACE_BASE + 0x39) ++#define REG_VIP_ACE_1D_L (REG_VIP_ACE_BASE + 0x3A) ++#define REG_VIP_ACE_1D_H (REG_VIP_ACE_BASE + 0x3B) ++#define REG_VIP_ACE_1E_L (REG_VIP_ACE_BASE + 0x3C) ++#define REG_VIP_ACE_1E_H (REG_VIP_ACE_BASE + 0x3D) ++#define REG_VIP_ACE_1F_L (REG_VIP_ACE_BASE + 0x3E) ++#define REG_VIP_ACE_1F_H (REG_VIP_ACE_BASE + 0x3F) ++#define REG_VIP_ACE_20_L (REG_VIP_ACE_BASE + 0x40) ++#define REG_VIP_ACE_20_H (REG_VIP_ACE_BASE + 0x41) ++#define REG_VIP_ACE_21_L (REG_VIP_ACE_BASE + 0x42) ++#define REG_VIP_ACE_21_H (REG_VIP_ACE_BASE + 0x43) ++#define REG_VIP_ACE_22_L (REG_VIP_ACE_BASE + 0x44) ++#define REG_VIP_ACE_22_H (REG_VIP_ACE_BASE + 0x45) ++#define REG_VIP_ACE_23_L (REG_VIP_ACE_BASE + 0x46) ++#define REG_VIP_ACE_23_H (REG_VIP_ACE_BASE + 0x47) ++#define REG_VIP_ACE_24_L (REG_VIP_ACE_BASE + 0x48) ++#define REG_VIP_ACE_24_H (REG_VIP_ACE_BASE + 0x49) ++#define REG_VIP_ACE_25_L (REG_VIP_ACE_BASE + 0x4A) ++#define REG_VIP_ACE_25_H (REG_VIP_ACE_BASE + 0x4B) ++#define REG_VIP_ACE_26_L (REG_VIP_ACE_BASE + 0x4C) ++#define REG_VIP_ACE_26_H (REG_VIP_ACE_BASE + 0x4D) ++#define REG_VIP_ACE_27_L (REG_VIP_ACE_BASE + 0x4E) ++#define REG_VIP_ACE_27_H (REG_VIP_ACE_BASE + 0x4F) ++#define REG_VIP_ACE_28_L (REG_VIP_ACE_BASE + 0x50) ++#define REG_VIP_ACE_28_H (REG_VIP_ACE_BASE + 0x51) ++#define REG_VIP_ACE_29_L (REG_VIP_ACE_BASE + 0x52) ++#define REG_VIP_ACE_29_H (REG_VIP_ACE_BASE + 0x53) ++#define REG_VIP_ACE_2A_L (REG_VIP_ACE_BASE + 0x54) ++#define REG_VIP_ACE_2A_H (REG_VIP_ACE_BASE + 0x55) ++#define REG_VIP_ACE_2B_L (REG_VIP_ACE_BASE + 0x56) ++#define REG_VIP_ACE_2B_H (REG_VIP_ACE_BASE + 0x57) ++#define REG_VIP_ACE_2C_L (REG_VIP_ACE_BASE + 0x58) ++#define REG_VIP_ACE_2C_H (REG_VIP_ACE_BASE + 0x59) ++#define REG_VIP_ACE_2D_L (REG_VIP_ACE_BASE + 0x5A) ++#define REG_VIP_ACE_2D_H (REG_VIP_ACE_BASE + 0x5B) ++#define REG_VIP_ACE_2E_L (REG_VIP_ACE_BASE + 0x5C) ++#define REG_VIP_ACE_2E_H (REG_VIP_ACE_BASE + 0x5D) ++#define REG_VIP_ACE_2F_L (REG_VIP_ACE_BASE + 0x5E) ++#define REG_VIP_ACE_2F_H (REG_VIP_ACE_BASE + 0x5F) ++#define REG_VIP_ACE_30_L (REG_VIP_ACE_BASE + 0x60) ++#define REG_VIP_ACE_30_H (REG_VIP_ACE_BASE + 0x61) ++#define REG_VIP_ACE_31_L (REG_VIP_ACE_BASE + 0x62) ++#define REG_VIP_ACE_31_H (REG_VIP_ACE_BASE + 0x63) ++#define REG_VIP_ACE_32_L (REG_VIP_ACE_BASE + 0x64) ++#define REG_VIP_ACE_32_H (REG_VIP_ACE_BASE + 0x65) ++#define REG_VIP_ACE_33_L (REG_VIP_ACE_BASE + 0x66) ++#define REG_VIP_ACE_33_H (REG_VIP_ACE_BASE + 0x67) ++#define REG_VIP_ACE_34_L (REG_VIP_ACE_BASE + 0x68) ++#define REG_VIP_ACE_34_H (REG_VIP_ACE_BASE + 0x69) ++#define REG_VIP_ACE_35_L (REG_VIP_ACE_BASE + 0x6A) ++#define REG_VIP_ACE_35_H (REG_VIP_ACE_BASE + 0x6B) ++#define REG_VIP_ACE_36_L (REG_VIP_ACE_BASE + 0x6C) ++#define REG_VIP_ACE_36_H (REG_VIP_ACE_BASE + 0x6D) ++#define REG_VIP_ACE_37_L (REG_VIP_ACE_BASE + 0x6E) ++#define REG_VIP_ACE_37_H (REG_VIP_ACE_BASE + 0x6F) ++#define REG_VIP_ACE_38_L (REG_VIP_ACE_BASE + 0x70) ++#define REG_VIP_ACE_38_H (REG_VIP_ACE_BASE + 0x71) ++#define REG_VIP_ACE_39_L (REG_VIP_ACE_BASE + 0x72) ++#define REG_VIP_ACE_39_H (REG_VIP_ACE_BASE + 0x73) ++#define REG_VIP_ACE_3A_L (REG_VIP_ACE_BASE + 0x74) ++#define REG_VIP_ACE_3A_H (REG_VIP_ACE_BASE + 0x75) ++#define REG_VIP_ACE_3B_L (REG_VIP_ACE_BASE + 0x76) ++#define REG_VIP_ACE_3B_H (REG_VIP_ACE_BASE + 0x77) ++#define REG_VIP_ACE_3C_L (REG_VIP_ACE_BASE + 0x78) ++#define REG_VIP_ACE_3C_H (REG_VIP_ACE_BASE + 0x79) ++#define REG_VIP_ACE_3D_L (REG_VIP_ACE_BASE + 0x7A) ++#define REG_VIP_ACE_3D_H (REG_VIP_ACE_BASE + 0x7B) ++#define REG_VIP_ACE_3E_L (REG_VIP_ACE_BASE + 0x7C) ++#define REG_VIP_ACE_3E_H (REG_VIP_ACE_BASE + 0x7D) ++#define REG_VIP_ACE_3F_L (REG_VIP_ACE_BASE + 0x7E) ++#define REG_VIP_ACE_3F_H (REG_VIP_ACE_BASE + 0x7F) ++#define REG_VIP_ACE_40_L (REG_VIP_ACE_BASE + 0x80) ++#define REG_VIP_ACE_40_H (REG_VIP_ACE_BASE + 0x81) ++#define REG_VIP_ACE_41_L (REG_VIP_ACE_BASE + 0x82) ++#define REG_VIP_ACE_41_H (REG_VIP_ACE_BASE + 0x83) ++#define REG_VIP_ACE_42_L (REG_VIP_ACE_BASE + 0x84) ++#define REG_VIP_ACE_42_H (REG_VIP_ACE_BASE + 0x85) ++#define REG_VIP_ACE_43_L (REG_VIP_ACE_BASE + 0x86) ++#define REG_VIP_ACE_43_H (REG_VIP_ACE_BASE + 0x87) ++#define REG_VIP_ACE_44_L (REG_VIP_ACE_BASE + 0x88) ++#define REG_VIP_ACE_44_H (REG_VIP_ACE_BASE + 0x89) ++#define REG_VIP_ACE_45_L (REG_VIP_ACE_BASE + 0x8A) ++#define REG_VIP_ACE_45_H (REG_VIP_ACE_BASE + 0x8B) ++#define REG_VIP_ACE_46_L (REG_VIP_ACE_BASE + 0x8C) ++#define REG_VIP_ACE_46_H (REG_VIP_ACE_BASE + 0x8D) ++#define REG_VIP_ACE_47_L (REG_VIP_ACE_BASE + 0x8E) ++#define REG_VIP_ACE_47_H (REG_VIP_ACE_BASE + 0x8F) ++#define REG_VIP_ACE_48_L (REG_VIP_ACE_BASE + 0x90) ++#define REG_VIP_ACE_48_H (REG_VIP_ACE_BASE + 0x91) ++#define REG_VIP_ACE_49_L (REG_VIP_ACE_BASE + 0x92) ++#define REG_VIP_ACE_49_H (REG_VIP_ACE_BASE + 0x93) ++#define REG_VIP_ACE_4A_L (REG_VIP_ACE_BASE + 0x94) ++#define REG_VIP_ACE_4A_H (REG_VIP_ACE_BASE + 0x95) ++#define REG_VIP_ACE_4B_L (REG_VIP_ACE_BASE + 0x96) ++#define REG_VIP_ACE_4B_H (REG_VIP_ACE_BASE + 0x97) ++#define REG_VIP_ACE_4C_L (REG_VIP_ACE_BASE + 0x98) ++#define REG_VIP_ACE_4C_H (REG_VIP_ACE_BASE + 0x99) ++#define REG_VIP_ACE_4D_L (REG_VIP_ACE_BASE + 0x9A) ++#define REG_VIP_ACE_4D_H (REG_VIP_ACE_BASE + 0x9B) ++#define REG_VIP_ACE_4E_L (REG_VIP_ACE_BASE + 0x9C) ++#define REG_VIP_ACE_4E_H (REG_VIP_ACE_BASE + 0x9D) ++#define REG_VIP_ACE_4F_L (REG_VIP_ACE_BASE + 0x9E) ++#define REG_VIP_ACE_4F_H (REG_VIP_ACE_BASE + 0x9F) ++#define REG_VIP_ACE_50_L (REG_VIP_ACE_BASE + 0xA0) ++#define REG_VIP_ACE_50_H (REG_VIP_ACE_BASE + 0xA1) ++#define REG_VIP_ACE_51_L (REG_VIP_ACE_BASE + 0xA2) ++#define REG_VIP_ACE_51_H (REG_VIP_ACE_BASE + 0xA3) ++#define REG_VIP_ACE_52_L (REG_VIP_ACE_BASE + 0xA4) ++#define REG_VIP_ACE_52_H (REG_VIP_ACE_BASE + 0xA5) ++#define REG_VIP_ACE_53_L (REG_VIP_ACE_BASE + 0xA6) ++#define REG_VIP_ACE_53_H (REG_VIP_ACE_BASE + 0xA7) ++#define REG_VIP_ACE_54_L (REG_VIP_ACE_BASE + 0xA8) ++#define REG_VIP_ACE_54_H (REG_VIP_ACE_BASE + 0xA9) ++#define REG_VIP_ACE_55_L (REG_VIP_ACE_BASE + 0xAA) ++#define REG_VIP_ACE_55_H (REG_VIP_ACE_BASE + 0xAB) ++#define REG_VIP_ACE_56_L (REG_VIP_ACE_BASE + 0xAC) ++#define REG_VIP_ACE_56_H (REG_VIP_ACE_BASE + 0xAD) ++#define REG_VIP_ACE_57_L (REG_VIP_ACE_BASE + 0xAE) ++#define REG_VIP_ACE_57_H (REG_VIP_ACE_BASE + 0xAF) ++#define REG_VIP_ACE_58_L (REG_VIP_ACE_BASE + 0xB0) ++#define REG_VIP_ACE_58_H (REG_VIP_ACE_BASE + 0xB1) ++#define REG_VIP_ACE_59_L (REG_VIP_ACE_BASE + 0xB2) ++#define REG_VIP_ACE_59_H (REG_VIP_ACE_BASE + 0xB3) ++#define REG_VIP_ACE_5A_L (REG_VIP_ACE_BASE + 0xB4) ++#define REG_VIP_ACE_5A_H (REG_VIP_ACE_BASE + 0xB5) ++#define REG_VIP_ACE_5B_L (REG_VIP_ACE_BASE + 0xB6) ++#define REG_VIP_ACE_5B_H (REG_VIP_ACE_BASE + 0xB7) ++#define REG_VIP_ACE_5C_L (REG_VIP_ACE_BASE + 0xB8) ++#define REG_VIP_ACE_5C_H (REG_VIP_ACE_BASE + 0xB9) ++#define REG_VIP_ACE_5D_L (REG_VIP_ACE_BASE + 0xBA) ++#define REG_VIP_ACE_5D_H (REG_VIP_ACE_BASE + 0xBB) ++#define REG_VIP_ACE_5E_L (REG_VIP_ACE_BASE + 0xBC) ++#define REG_VIP_ACE_5E_H (REG_VIP_ACE_BASE + 0xBD) ++#define REG_VIP_ACE_5F_L (REG_VIP_ACE_BASE + 0xBE) ++#define REG_VIP_ACE_5F_H (REG_VIP_ACE_BASE + 0xBF) ++#define REG_VIP_ACE_60_L (REG_VIP_ACE_BASE + 0xC0) ++#define REG_VIP_ACE_60_H (REG_VIP_ACE_BASE + 0xC1) ++#define REG_VIP_ACE_61_L (REG_VIP_ACE_BASE + 0xC2) ++#define REG_VIP_ACE_61_H (REG_VIP_ACE_BASE + 0xC3) ++#define REG_VIP_ACE_62_L (REG_VIP_ACE_BASE + 0xC4) ++#define REG_VIP_ACE_62_H (REG_VIP_ACE_BASE + 0xC5) ++#define REG_VIP_ACE_63_L (REG_VIP_ACE_BASE + 0xC6) ++#define REG_VIP_ACE_63_H (REG_VIP_ACE_BASE + 0xC7) ++#define REG_VIP_ACE_64_L (REG_VIP_ACE_BASE + 0xC8) ++#define REG_VIP_ACE_64_H (REG_VIP_ACE_BASE + 0xC9) ++#define REG_VIP_ACE_65_L (REG_VIP_ACE_BASE + 0xCA) ++#define REG_VIP_ACE_65_H (REG_VIP_ACE_BASE + 0xCB) ++#define REG_VIP_ACE_66_L (REG_VIP_ACE_BASE + 0xCC) ++#define REG_VIP_ACE_66_H (REG_VIP_ACE_BASE + 0xCD) ++#define REG_VIP_ACE_67_L (REG_VIP_ACE_BASE + 0xCE) ++#define REG_VIP_ACE_67_H (REG_VIP_ACE_BASE + 0xCF) ++#define REG_VIP_ACE_68_L (REG_VIP_ACE_BASE + 0xD0) ++#define REG_VIP_ACE_68_H (REG_VIP_ACE_BASE + 0xD1) ++#define REG_VIP_ACE_69_L (REG_VIP_ACE_BASE + 0xD2) ++#define REG_VIP_ACE_69_H (REG_VIP_ACE_BASE + 0xD3) ++#define REG_VIP_ACE_6A_L (REG_VIP_ACE_BASE + 0xD4) ++#define REG_VIP_ACE_6A_H (REG_VIP_ACE_BASE + 0xD5) ++#define REG_VIP_ACE_6B_L (REG_VIP_ACE_BASE + 0xD6) ++#define REG_VIP_ACE_6B_H (REG_VIP_ACE_BASE + 0xD7) ++#define REG_VIP_ACE_6C_L (REG_VIP_ACE_BASE + 0xD8) ++#define REG_VIP_ACE_6C_H (REG_VIP_ACE_BASE + 0xD9) ++#define REG_VIP_ACE_6D_L (REG_VIP_ACE_BASE + 0xDA) ++#define REG_VIP_ACE_6D_H (REG_VIP_ACE_BASE + 0xDB) ++#define REG_VIP_ACE_6E_L (REG_VIP_ACE_BASE + 0xDC) ++#define REG_VIP_ACE_6E_H (REG_VIP_ACE_BASE + 0xDD) ++#define REG_VIP_ACE_6F_L (REG_VIP_ACE_BASE + 0xDE) ++#define REG_VIP_ACE_6F_H (REG_VIP_ACE_BASE + 0xDF) ++#define REG_VIP_ACE_70_L (REG_VIP_ACE_BASE + 0xE0) ++#define REG_VIP_ACE_70_H (REG_VIP_ACE_BASE + 0xE1) ++#define REG_VIP_ACE_71_L (REG_VIP_ACE_BASE + 0xE2) ++#define REG_VIP_ACE_71_H (REG_VIP_ACE_BASE + 0xE3) ++#define REG_VIP_ACE_72_L (REG_VIP_ACE_BASE + 0xE4) ++#define REG_VIP_ACE_72_H (REG_VIP_ACE_BASE + 0xE5) ++#define REG_VIP_ACE_73_L (REG_VIP_ACE_BASE + 0xE6) ++#define REG_VIP_ACE_73_H (REG_VIP_ACE_BASE + 0xE7) ++#define REG_VIP_ACE_74_L (REG_VIP_ACE_BASE + 0xE8) ++#define REG_VIP_ACE_74_H (REG_VIP_ACE_BASE + 0xE9) ++#define REG_VIP_ACE_75_L (REG_VIP_ACE_BASE + 0xEA) ++#define REG_VIP_ACE_75_H (REG_VIP_ACE_BASE + 0xEB) ++#define REG_VIP_ACE_76_L (REG_VIP_ACE_BASE + 0xEC) ++#define REG_VIP_ACE_76_H (REG_VIP_ACE_BASE + 0xED) ++#define REG_VIP_ACE_77_L (REG_VIP_ACE_BASE + 0xEE) ++#define REG_VIP_ACE_77_H (REG_VIP_ACE_BASE + 0xEF) ++#define REG_VIP_ACE_78_L (REG_VIP_ACE_BASE + 0xF0) ++#define REG_VIP_ACE_78_H (REG_VIP_ACE_BASE + 0xF1) ++#define REG_VIP_ACE_79_L (REG_VIP_ACE_BASE + 0xF2) ++#define REG_VIP_ACE_79_H (REG_VIP_ACE_BASE + 0xF3) ++#define REG_VIP_ACE_7A_L (REG_VIP_ACE_BASE + 0xF4) ++#define REG_VIP_ACE_7A_H (REG_VIP_ACE_BASE + 0xF5) ++#define REG_VIP_ACE_7B_L (REG_VIP_ACE_BASE + 0xF6) ++#define REG_VIP_ACE_7B_H (REG_VIP_ACE_BASE + 0xF7) ++#define REG_VIP_ACE_7C_L (REG_VIP_ACE_BASE + 0xF8) ++#define REG_VIP_ACE_7C_H (REG_VIP_ACE_BASE + 0xF9) ++#define REG_VIP_ACE_7D_L (REG_VIP_ACE_BASE + 0xFA) ++#define REG_VIP_ACE_7D_H (REG_VIP_ACE_BASE + 0xFB) ++#define REG_VIP_ACE_7E_L (REG_VIP_ACE_BASE + 0xFC) ++#define REG_VIP_ACE_7E_H (REG_VIP_ACE_BASE + 0xFD) ++#define REG_VIP_ACE_7F_L (REG_VIP_ACE_BASE + 0xFE) ++#define REG_VIP_ACE_7F_H (REG_VIP_ACE_BASE + 0xFF) ++ ++ ++#define REG_VIP_PK_00_L (REG_VIP_PK_BASE + 0x00) ++#define REG_VIP_PK_00_H (REG_VIP_PK_BASE + 0x01) ++#define REG_VIP_PK_01_L (REG_VIP_PK_BASE + 0x02) ++#define REG_VIP_PK_01_H (REG_VIP_PK_BASE + 0x03) ++#define REG_VIP_PK_02_L (REG_VIP_PK_BASE + 0x04) ++#define REG_VIP_PK_02_H (REG_VIP_PK_BASE + 0x05) ++#define REG_VIP_PK_03_L (REG_VIP_PK_BASE + 0x06) ++#define REG_VIP_PK_03_H (REG_VIP_PK_BASE + 0x07) ++#define REG_VIP_PK_04_L (REG_VIP_PK_BASE + 0x08) ++#define REG_VIP_PK_04_H (REG_VIP_PK_BASE + 0x09) ++#define REG_VIP_PK_05_L (REG_VIP_PK_BASE + 0x0A) ++#define REG_VIP_PK_05_H (REG_VIP_PK_BASE + 0x0B) ++#define REG_VIP_PK_06_L (REG_VIP_PK_BASE + 0x0C) ++#define REG_VIP_PK_06_H (REG_VIP_PK_BASE + 0x0D) ++#define REG_VIP_PK_07_L (REG_VIP_PK_BASE + 0x0E) ++#define REG_VIP_PK_07_H (REG_VIP_PK_BASE + 0x0F) ++#define REG_VIP_PK_08_L (REG_VIP_PK_BASE + 0x10) ++#define REG_VIP_PK_08_H (REG_VIP_PK_BASE + 0x11) ++#define REG_VIP_PK_09_L (REG_VIP_PK_BASE + 0x12) ++#define REG_VIP_PK_09_H (REG_VIP_PK_BASE + 0x13) ++#define REG_VIP_PK_0A_L (REG_VIP_PK_BASE + 0x14) ++#define REG_VIP_PK_0A_H (REG_VIP_PK_BASE + 0x15) ++#define REG_VIP_PK_0B_L (REG_VIP_PK_BASE + 0x16) ++#define REG_VIP_PK_0B_H (REG_VIP_PK_BASE + 0x17) ++#define REG_VIP_PK_0C_L (REG_VIP_PK_BASE + 0x18) ++#define REG_VIP_PK_0C_H (REG_VIP_PK_BASE + 0x19) ++#define REG_VIP_PK_0D_L (REG_VIP_PK_BASE + 0x1A) ++#define REG_VIP_PK_0D_H (REG_VIP_PK_BASE + 0x1B) ++#define REG_VIP_PK_0E_L (REG_VIP_PK_BASE + 0x1C) ++#define REG_VIP_PK_0E_H (REG_VIP_PK_BASE + 0x1D) ++#define REG_VIP_PK_0F_L (REG_VIP_PK_BASE + 0x1E) ++#define REG_VIP_PK_0F_H (REG_VIP_PK_BASE + 0x1F) ++#define REG_VIP_PK_10_L (REG_VIP_PK_BASE + 0x20) ++#define REG_VIP_PK_10_H (REG_VIP_PK_BASE + 0x21) ++#define REG_VIP_PK_11_L (REG_VIP_PK_BASE + 0x22) ++#define REG_VIP_PK_11_H (REG_VIP_PK_BASE + 0x23) ++#define REG_VIP_PK_12_L (REG_VIP_PK_BASE + 0x24) ++#define REG_VIP_PK_12_H (REG_VIP_PK_BASE + 0x25) ++#define REG_VIP_PK_13_L (REG_VIP_PK_BASE + 0x26) ++#define REG_VIP_PK_13_H (REG_VIP_PK_BASE + 0x27) ++#define REG_VIP_PK_14_L (REG_VIP_PK_BASE + 0x28) ++#define REG_VIP_PK_14_H (REG_VIP_PK_BASE + 0x29) ++#define REG_VIP_PK_15_L (REG_VIP_PK_BASE + 0x2A) ++#define REG_VIP_PK_15_H (REG_VIP_PK_BASE + 0x2B) ++#define REG_VIP_PK_16_L (REG_VIP_PK_BASE + 0x2C) ++#define REG_VIP_PK_16_H (REG_VIP_PK_BASE + 0x2D) ++#define REG_VIP_PK_17_L (REG_VIP_PK_BASE + 0x2E) ++#define REG_VIP_PK_17_H (REG_VIP_PK_BASE + 0x2F) ++#define REG_VIP_PK_18_L (REG_VIP_PK_BASE + 0x30) ++#define REG_VIP_PK_18_H (REG_VIP_PK_BASE + 0x31) ++#define REG_VIP_PK_19_L (REG_VIP_PK_BASE + 0x32) ++#define REG_VIP_PK_19_H (REG_VIP_PK_BASE + 0x33) ++#define REG_VIP_PK_1A_L (REG_VIP_PK_BASE + 0x34) ++#define REG_VIP_PK_1A_H (REG_VIP_PK_BASE + 0x35) ++#define REG_VIP_PK_1B_L (REG_VIP_PK_BASE + 0x36) ++#define REG_VIP_PK_1B_H (REG_VIP_PK_BASE + 0x37) ++#define REG_VIP_PK_1C_L (REG_VIP_PK_BASE + 0x38) ++#define REG_VIP_PK_1C_H (REG_VIP_PK_BASE + 0x39) ++#define REG_VIP_PK_1D_L (REG_VIP_PK_BASE + 0x3A) ++#define REG_VIP_PK_1D_H (REG_VIP_PK_BASE + 0x3B) ++#define REG_VIP_PK_1E_L (REG_VIP_PK_BASE + 0x3C) ++#define REG_VIP_PK_1E_H (REG_VIP_PK_BASE + 0x3D) ++#define REG_VIP_PK_1F_L (REG_VIP_PK_BASE + 0x3E) ++#define REG_VIP_PK_1F_H (REG_VIP_PK_BASE + 0x3F) ++#define REG_VIP_PK_20_L (REG_VIP_PK_BASE + 0x40) ++#define REG_VIP_PK_20_H (REG_VIP_PK_BASE + 0x41) ++#define REG_VIP_PK_21_L (REG_VIP_PK_BASE + 0x42) ++#define REG_VIP_PK_21_H (REG_VIP_PK_BASE + 0x43) ++#define REG_VIP_PK_22_L (REG_VIP_PK_BASE + 0x44) ++#define REG_VIP_PK_22_H (REG_VIP_PK_BASE + 0x45) ++#define REG_VIP_PK_23_L (REG_VIP_PK_BASE + 0x46) ++#define REG_VIP_PK_23_H (REG_VIP_PK_BASE + 0x47) ++#define REG_VIP_PK_24_L (REG_VIP_PK_BASE + 0x48) ++#define REG_VIP_PK_24_H (REG_VIP_PK_BASE + 0x49) ++#define REG_VIP_PK_25_L (REG_VIP_PK_BASE + 0x4A) ++#define REG_VIP_PK_25_H (REG_VIP_PK_BASE + 0x4B) ++#define REG_VIP_PK_26_L (REG_VIP_PK_BASE + 0x4C) ++#define REG_VIP_PK_26_H (REG_VIP_PK_BASE + 0x4D) ++#define REG_VIP_PK_27_L (REG_VIP_PK_BASE + 0x4E) ++#define REG_VIP_PK_27_H (REG_VIP_PK_BASE + 0x4F) ++#define REG_VIP_PK_28_L (REG_VIP_PK_BASE + 0x50) ++#define REG_VIP_PK_28_H (REG_VIP_PK_BASE + 0x51) ++#define REG_VIP_PK_29_L (REG_VIP_PK_BASE + 0x52) ++#define REG_VIP_PK_29_H (REG_VIP_PK_BASE + 0x53) ++#define REG_VIP_PK_2A_L (REG_VIP_PK_BASE + 0x54) ++#define REG_VIP_PK_2A_H (REG_VIP_PK_BASE + 0x55) ++#define REG_VIP_PK_2B_L (REG_VIP_PK_BASE + 0x56) ++#define REG_VIP_PK_2B_H (REG_VIP_PK_BASE + 0x57) ++#define REG_VIP_PK_2C_L (REG_VIP_PK_BASE + 0x58) ++#define REG_VIP_PK_2C_H (REG_VIP_PK_BASE + 0x59) ++#define REG_VIP_PK_2D_L (REG_VIP_PK_BASE + 0x5A) ++#define REG_VIP_PK_2D_H (REG_VIP_PK_BASE + 0x5B) ++#define REG_VIP_PK_2E_L (REG_VIP_PK_BASE + 0x5C) ++#define REG_VIP_PK_2E_H (REG_VIP_PK_BASE + 0x5D) ++#define REG_VIP_PK_2F_L (REG_VIP_PK_BASE + 0x5E) ++#define REG_VIP_PK_2F_H (REG_VIP_PK_BASE + 0x5F) ++#define REG_VIP_PK_30_L (REG_VIP_PK_BASE + 0x60) ++#define REG_VIP_PK_30_H (REG_VIP_PK_BASE + 0x61) ++#define REG_VIP_PK_31_L (REG_VIP_PK_BASE + 0x62) ++#define REG_VIP_PK_31_H (REG_VIP_PK_BASE + 0x63) ++#define REG_VIP_PK_32_L (REG_VIP_PK_BASE + 0x64) ++#define REG_VIP_PK_32_H (REG_VIP_PK_BASE + 0x65) ++#define REG_VIP_PK_33_L (REG_VIP_PK_BASE + 0x66) ++#define REG_VIP_PK_33_H (REG_VIP_PK_BASE + 0x67) ++#define REG_VIP_PK_34_L (REG_VIP_PK_BASE + 0x68) ++#define REG_VIP_PK_34_H (REG_VIP_PK_BASE + 0x69) ++#define REG_VIP_PK_35_L (REG_VIP_PK_BASE + 0x6A) ++#define REG_VIP_PK_35_H (REG_VIP_PK_BASE + 0x6B) ++#define REG_VIP_PK_36_L (REG_VIP_PK_BASE + 0x6C) ++#define REG_VIP_PK_36_H (REG_VIP_PK_BASE + 0x6D) ++#define REG_VIP_PK_37_L (REG_VIP_PK_BASE + 0x6E) ++#define REG_VIP_PK_37_H (REG_VIP_PK_BASE + 0x6F) ++#define REG_VIP_PK_38_L (REG_VIP_PK_BASE + 0x70) ++#define REG_VIP_PK_38_H (REG_VIP_PK_BASE + 0x71) ++#define REG_VIP_PK_39_L (REG_VIP_PK_BASE + 0x72) ++#define REG_VIP_PK_39_H (REG_VIP_PK_BASE + 0x73) ++#define REG_VIP_PK_3A_L (REG_VIP_PK_BASE + 0x74) ++#define REG_VIP_PK_3A_H (REG_VIP_PK_BASE + 0x75) ++#define REG_VIP_PK_3B_L (REG_VIP_PK_BASE + 0x76) ++#define REG_VIP_PK_3B_H (REG_VIP_PK_BASE + 0x77) ++#define REG_VIP_PK_3C_L (REG_VIP_PK_BASE + 0x78) ++#define REG_VIP_PK_3C_H (REG_VIP_PK_BASE + 0x79) ++#define REG_VIP_PK_3D_L (REG_VIP_PK_BASE + 0x7A) ++#define REG_VIP_PK_3D_H (REG_VIP_PK_BASE + 0x7B) ++#define REG_VIP_PK_3E_L (REG_VIP_PK_BASE + 0x7C) ++#define REG_VIP_PK_3E_H (REG_VIP_PK_BASE + 0x7D) ++#define REG_VIP_PK_3F_L (REG_VIP_PK_BASE + 0x7E) ++#define REG_VIP_PK_3F_H (REG_VIP_PK_BASE + 0x7F) ++#define REG_VIP_PK_40_L (REG_VIP_PK_BASE + 0x80) ++#define REG_VIP_PK_40_H (REG_VIP_PK_BASE + 0x81) ++#define REG_VIP_PK_41_L (REG_VIP_PK_BASE + 0x82) ++#define REG_VIP_PK_41_H (REG_VIP_PK_BASE + 0x83) ++#define REG_VIP_PK_42_L (REG_VIP_PK_BASE + 0x84) ++#define REG_VIP_PK_42_H (REG_VIP_PK_BASE + 0x85) ++#define REG_VIP_PK_43_L (REG_VIP_PK_BASE + 0x86) ++#define REG_VIP_PK_43_H (REG_VIP_PK_BASE + 0x87) ++#define REG_VIP_PK_44_L (REG_VIP_PK_BASE + 0x88) ++#define REG_VIP_PK_44_H (REG_VIP_PK_BASE + 0x89) ++#define REG_VIP_PK_45_L (REG_VIP_PK_BASE + 0x8A) ++#define REG_VIP_PK_45_H (REG_VIP_PK_BASE + 0x8B) ++#define REG_VIP_PK_46_L (REG_VIP_PK_BASE + 0x8C) ++#define REG_VIP_PK_46_H (REG_VIP_PK_BASE + 0x8D) ++#define REG_VIP_PK_47_L (REG_VIP_PK_BASE + 0x8E) ++#define REG_VIP_PK_47_H (REG_VIP_PK_BASE + 0x8F) ++#define REG_VIP_PK_48_L (REG_VIP_PK_BASE + 0x90) ++#define REG_VIP_PK_48_H (REG_VIP_PK_BASE + 0x91) ++#define REG_VIP_PK_49_L (REG_VIP_PK_BASE + 0x92) ++#define REG_VIP_PK_49_H (REG_VIP_PK_BASE + 0x93) ++#define REG_VIP_PK_4A_L (REG_VIP_PK_BASE + 0x94) ++#define REG_VIP_PK_4A_H (REG_VIP_PK_BASE + 0x95) ++#define REG_VIP_PK_4B_L (REG_VIP_PK_BASE + 0x96) ++#define REG_VIP_PK_4B_H (REG_VIP_PK_BASE + 0x97) ++#define REG_VIP_PK_4C_L (REG_VIP_PK_BASE + 0x98) ++#define REG_VIP_PK_4C_H (REG_VIP_PK_BASE + 0x99) ++#define REG_VIP_PK_4D_L (REG_VIP_PK_BASE + 0x9A) ++#define REG_VIP_PK_4D_H (REG_VIP_PK_BASE + 0x9B) ++#define REG_VIP_PK_4E_L (REG_VIP_PK_BASE + 0x9C) ++#define REG_VIP_PK_4E_H (REG_VIP_PK_BASE + 0x9D) ++#define REG_VIP_PK_4F_L (REG_VIP_PK_BASE + 0x9E) ++#define REG_VIP_PK_4F_H (REG_VIP_PK_BASE + 0x9F) ++#define REG_VIP_PK_50_L (REG_VIP_PK_BASE + 0xA0) ++#define REG_VIP_PK_50_H (REG_VIP_PK_BASE + 0xA1) ++#define REG_VIP_PK_51_L (REG_VIP_PK_BASE + 0xA2) ++#define REG_VIP_PK_51_H (REG_VIP_PK_BASE + 0xA3) ++#define REG_VIP_PK_52_L (REG_VIP_PK_BASE + 0xA4) ++#define REG_VIP_PK_52_H (REG_VIP_PK_BASE + 0xA5) ++#define REG_VIP_PK_53_L (REG_VIP_PK_BASE + 0xA6) ++#define REG_VIP_PK_53_H (REG_VIP_PK_BASE + 0xA7) ++#define REG_VIP_PK_54_L (REG_VIP_PK_BASE + 0xA8) ++#define REG_VIP_PK_54_H (REG_VIP_PK_BASE + 0xA9) ++#define REG_VIP_PK_55_L (REG_VIP_PK_BASE + 0xAA) ++#define REG_VIP_PK_55_H (REG_VIP_PK_BASE + 0xAB) ++#define REG_VIP_PK_56_L (REG_VIP_PK_BASE + 0xAC) ++#define REG_VIP_PK_56_H (REG_VIP_PK_BASE + 0xAD) ++#define REG_VIP_PK_57_L (REG_VIP_PK_BASE + 0xAE) ++#define REG_VIP_PK_57_H (REG_VIP_PK_BASE + 0xAF) ++#define REG_VIP_PK_58_L (REG_VIP_PK_BASE + 0xB0) ++#define REG_VIP_PK_58_H (REG_VIP_PK_BASE + 0xB1) ++#define REG_VIP_PK_59_L (REG_VIP_PK_BASE + 0xB2) ++#define REG_VIP_PK_59_H (REG_VIP_PK_BASE + 0xB3) ++#define REG_VIP_PK_5A_L (REG_VIP_PK_BASE + 0xB4) ++#define REG_VIP_PK_5A_H (REG_VIP_PK_BASE + 0xB5) ++#define REG_VIP_PK_5B_L (REG_VIP_PK_BASE + 0xB6) ++#define REG_VIP_PK_5B_H (REG_VIP_PK_BASE + 0xB7) ++#define REG_VIP_PK_5C_L (REG_VIP_PK_BASE + 0xB8) ++#define REG_VIP_PK_5C_H (REG_VIP_PK_BASE + 0xB9) ++#define REG_VIP_PK_5D_L (REG_VIP_PK_BASE + 0xBA) ++#define REG_VIP_PK_5D_H (REG_VIP_PK_BASE + 0xBB) ++#define REG_VIP_PK_5E_L (REG_VIP_PK_BASE + 0xBC) ++#define REG_VIP_PK_5E_H (REG_VIP_PK_BASE + 0xBD) ++#define REG_VIP_PK_5F_L (REG_VIP_PK_BASE + 0xBE) ++#define REG_VIP_PK_5F_H (REG_VIP_PK_BASE + 0xBF) ++#define REG_VIP_PK_60_L (REG_VIP_PK_BASE + 0xC0) ++#define REG_VIP_PK_60_H (REG_VIP_PK_BASE + 0xC1) ++#define REG_VIP_PK_61_L (REG_VIP_PK_BASE + 0xC2) ++#define REG_VIP_PK_61_H (REG_VIP_PK_BASE + 0xC3) ++#define REG_VIP_PK_62_L (REG_VIP_PK_BASE + 0xC4) ++#define REG_VIP_PK_62_H (REG_VIP_PK_BASE + 0xC5) ++#define REG_VIP_PK_63_L (REG_VIP_PK_BASE + 0xC6) ++#define REG_VIP_PK_63_H (REG_VIP_PK_BASE + 0xC7) ++#define REG_VIP_PK_64_L (REG_VIP_PK_BASE + 0xC8) ++#define REG_VIP_PK_64_H (REG_VIP_PK_BASE + 0xC9) ++#define REG_VIP_PK_65_L (REG_VIP_PK_BASE + 0xCA) ++#define REG_VIP_PK_65_H (REG_VIP_PK_BASE + 0xCB) ++#define REG_VIP_PK_66_L (REG_VIP_PK_BASE + 0xCC) ++#define REG_VIP_PK_66_H (REG_VIP_PK_BASE + 0xCD) ++#define REG_VIP_PK_67_L (REG_VIP_PK_BASE + 0xCE) ++#define REG_VIP_PK_67_H (REG_VIP_PK_BASE + 0xCF) ++#define REG_VIP_PK_68_L (REG_VIP_PK_BASE + 0xD0) ++#define REG_VIP_PK_68_H (REG_VIP_PK_BASE + 0xD1) ++#define REG_VIP_PK_69_L (REG_VIP_PK_BASE + 0xD2) ++#define REG_VIP_PK_69_H (REG_VIP_PK_BASE + 0xD3) ++#define REG_VIP_PK_6A_L (REG_VIP_PK_BASE + 0xD4) ++#define REG_VIP_PK_6A_H (REG_VIP_PK_BASE + 0xD5) ++#define REG_VIP_PK_6B_L (REG_VIP_PK_BASE + 0xD6) ++#define REG_VIP_PK_6B_H (REG_VIP_PK_BASE + 0xD7) ++#define REG_VIP_PK_6C_L (REG_VIP_PK_BASE + 0xD8) ++#define REG_VIP_PK_6C_H (REG_VIP_PK_BASE + 0xD9) ++#define REG_VIP_PK_6D_L (REG_VIP_PK_BASE + 0xDA) ++#define REG_VIP_PK_6D_H (REG_VIP_PK_BASE + 0xDB) ++#define REG_VIP_PK_6E_L (REG_VIP_PK_BASE + 0xDC) ++#define REG_VIP_PK_6E_H (REG_VIP_PK_BASE + 0xDD) ++#define REG_VIP_PK_6F_L (REG_VIP_PK_BASE + 0xDE) ++#define REG_VIP_PK_6F_H (REG_VIP_PK_BASE + 0xDF) ++#define REG_VIP_PK_70_L (REG_VIP_PK_BASE + 0xE0) ++#define REG_VIP_PK_70_H (REG_VIP_PK_BASE + 0xE1) ++#define REG_VIP_PK_71_L (REG_VIP_PK_BASE + 0xE2) ++#define REG_VIP_PK_71_H (REG_VIP_PK_BASE + 0xE3) ++#define REG_VIP_PK_72_L (REG_VIP_PK_BASE + 0xE4) ++#define REG_VIP_PK_72_H (REG_VIP_PK_BASE + 0xE5) ++#define REG_VIP_PK_73_L (REG_VIP_PK_BASE + 0xE6) ++#define REG_VIP_PK_73_H (REG_VIP_PK_BASE + 0xE7) ++#define REG_VIP_PK_74_L (REG_VIP_PK_BASE + 0xE8) ++#define REG_VIP_PK_74_H (REG_VIP_PK_BASE + 0xE9) ++#define REG_VIP_PK_75_L (REG_VIP_PK_BASE + 0xEA) ++#define REG_VIP_PK_75_H (REG_VIP_PK_BASE + 0xEB) ++#define REG_VIP_PK_76_L (REG_VIP_PK_BASE + 0xEC) ++#define REG_VIP_PK_76_H (REG_VIP_PK_BASE + 0xED) ++#define REG_VIP_PK_77_L (REG_VIP_PK_BASE + 0xEE) ++#define REG_VIP_PK_77_H (REG_VIP_PK_BASE + 0xEF) ++#define REG_VIP_PK_78_L (REG_VIP_PK_BASE + 0xF0) ++#define REG_VIP_PK_78_H (REG_VIP_PK_BASE + 0xF1) ++#define REG_VIP_PK_79_L (REG_VIP_PK_BASE + 0xF2) ++#define REG_VIP_PK_79_H (REG_VIP_PK_BASE + 0xF3) ++#define REG_VIP_PK_7A_L (REG_VIP_PK_BASE + 0xF4) ++#define REG_VIP_PK_7A_H (REG_VIP_PK_BASE + 0xF5) ++#define REG_VIP_PK_7B_L (REG_VIP_PK_BASE + 0xF6) ++#define REG_VIP_PK_7B_H (REG_VIP_PK_BASE + 0xF7) ++#define REG_VIP_PK_7C_L (REG_VIP_PK_BASE + 0xF8) ++#define REG_VIP_PK_7C_H (REG_VIP_PK_BASE + 0xF9) ++#define REG_VIP_PK_7D_L (REG_VIP_PK_BASE + 0xFA) ++#define REG_VIP_PK_7D_H (REG_VIP_PK_BASE + 0xFB) ++#define REG_VIP_PK_7E_L (REG_VIP_PK_BASE + 0xFC) ++#define REG_VIP_PK_7E_H (REG_VIP_PK_BASE + 0xFD) ++#define REG_VIP_PK_7F_L (REG_VIP_PK_BASE + 0xFE) ++#define REG_VIP_PK_7F_H (REG_VIP_PK_BASE + 0xFF) ++ ++#define REG_VIP_DLC_00_L (REG_VIP_DLC_BASE + 0x00) ++#define REG_VIP_DLC_00_H (REG_VIP_DLC_BASE + 0x01) ++#define REG_VIP_DLC_01_L (REG_VIP_DLC_BASE + 0x02) ++#define REG_VIP_DLC_01_H (REG_VIP_DLC_BASE + 0x03) ++#define REG_VIP_DLC_02_L (REG_VIP_DLC_BASE + 0x04) ++#define REG_VIP_DLC_02_H (REG_VIP_DLC_BASE + 0x05) ++#define REG_VIP_DLC_03_L (REG_VIP_DLC_BASE + 0x06) ++#define REG_VIP_DLC_03_H (REG_VIP_DLC_BASE + 0x07) ++#define REG_VIP_DLC_04_L (REG_VIP_DLC_BASE + 0x08) ++#define REG_VIP_DLC_04_H (REG_VIP_DLC_BASE + 0x09) ++#define REG_VIP_DLC_05_L (REG_VIP_DLC_BASE + 0x0A) ++#define REG_VIP_DLC_05_H (REG_VIP_DLC_BASE + 0x0B) ++#define REG_VIP_DLC_06_L (REG_VIP_DLC_BASE + 0x0C) ++#define REG_VIP_DLC_06_H (REG_VIP_DLC_BASE + 0x0D) ++#define REG_VIP_DLC_07_L (REG_VIP_DLC_BASE + 0x0E) ++#define REG_VIP_DLC_07_H (REG_VIP_DLC_BASE + 0x0F) ++#define REG_VIP_DLC_08_L (REG_VIP_DLC_BASE + 0x10) ++#define REG_VIP_DLC_08_H (REG_VIP_DLC_BASE + 0x11) ++#define REG_VIP_DLC_09_L (REG_VIP_DLC_BASE + 0x12) ++#define REG_VIP_DLC_09_H (REG_VIP_DLC_BASE + 0x13) ++#define REG_VIP_DLC_0A_L (REG_VIP_DLC_BASE + 0x14) ++#define REG_VIP_DLC_0A_H (REG_VIP_DLC_BASE + 0x15) ++#define REG_VIP_DLC_0B_L (REG_VIP_DLC_BASE + 0x16) ++#define REG_VIP_DLC_0B_H (REG_VIP_DLC_BASE + 0x17) ++#define REG_VIP_DLC_0C_L (REG_VIP_DLC_BASE + 0x18) ++#define REG_VIP_DLC_0C_H (REG_VIP_DLC_BASE + 0x19) ++#define REG_VIP_DLC_0D_L (REG_VIP_DLC_BASE + 0x1A) ++#define REG_VIP_DLC_0D_H (REG_VIP_DLC_BASE + 0x1B) ++#define REG_VIP_DLC_0E_L (REG_VIP_DLC_BASE + 0x1C) ++#define REG_VIP_DLC_0E_H (REG_VIP_DLC_BASE + 0x1D) ++#define REG_VIP_DLC_0F_L (REG_VIP_DLC_BASE + 0x1E) ++#define REG_VIP_DLC_0F_H (REG_VIP_DLC_BASE + 0x1F) ++#define REG_VIP_DLC_10_L (REG_VIP_DLC_BASE + 0x20) ++#define REG_VIP_DLC_10_H (REG_VIP_DLC_BASE + 0x21) ++#define REG_VIP_DLC_11_L (REG_VIP_DLC_BASE + 0x22) ++#define REG_VIP_DLC_11_H (REG_VIP_DLC_BASE + 0x23) ++#define REG_VIP_DLC_12_L (REG_VIP_DLC_BASE + 0x24) ++#define REG_VIP_DLC_12_H (REG_VIP_DLC_BASE + 0x25) ++#define REG_VIP_DLC_13_L (REG_VIP_DLC_BASE + 0x26) ++#define REG_VIP_DLC_13_H (REG_VIP_DLC_BASE + 0x27) ++#define REG_VIP_DLC_14_L (REG_VIP_DLC_BASE + 0x28) ++#define REG_VIP_DLC_14_H (REG_VIP_DLC_BASE + 0x29) ++#define REG_VIP_DLC_15_L (REG_VIP_DLC_BASE + 0x2A) ++#define REG_VIP_DLC_15_H (REG_VIP_DLC_BASE + 0x2B) ++#define REG_VIP_DLC_16_L (REG_VIP_DLC_BASE + 0x2C) ++#define REG_VIP_DLC_16_H (REG_VIP_DLC_BASE + 0x2D) ++#define REG_VIP_DLC_17_L (REG_VIP_DLC_BASE + 0x2E) ++#define REG_VIP_DLC_17_H (REG_VIP_DLC_BASE + 0x2F) ++#define REG_VIP_DLC_18_L (REG_VIP_DLC_BASE + 0x30) ++#define REG_VIP_DLC_18_H (REG_VIP_DLC_BASE + 0x31) ++#define REG_VIP_DLC_19_L (REG_VIP_DLC_BASE + 0x32) ++#define REG_VIP_DLC_19_H (REG_VIP_DLC_BASE + 0x33) ++#define REG_VIP_DLC_1A_L (REG_VIP_DLC_BASE + 0x34) ++#define REG_VIP_DLC_1A_H (REG_VIP_DLC_BASE + 0x35) ++#define REG_VIP_DLC_1B_L (REG_VIP_DLC_BASE + 0x36) ++#define REG_VIP_DLC_1B_H (REG_VIP_DLC_BASE + 0x37) ++#define REG_VIP_DLC_1C_L (REG_VIP_DLC_BASE + 0x38) ++#define REG_VIP_DLC_1C_H (REG_VIP_DLC_BASE + 0x39) ++#define REG_VIP_DLC_1D_L (REG_VIP_DLC_BASE + 0x3A) ++#define REG_VIP_DLC_1D_H (REG_VIP_DLC_BASE + 0x3B) ++#define REG_VIP_DLC_1E_L (REG_VIP_DLC_BASE + 0x3C) ++#define REG_VIP_DLC_1E_H (REG_VIP_DLC_BASE + 0x3D) ++#define REG_VIP_DLC_1F_L (REG_VIP_DLC_BASE + 0x3E) ++#define REG_VIP_DLC_1F_H (REG_VIP_DLC_BASE + 0x3F) ++#define REG_VIP_DLC_20_L (REG_VIP_DLC_BASE + 0x40) ++#define REG_VIP_DLC_20_H (REG_VIP_DLC_BASE + 0x41) ++#define REG_VIP_DLC_21_L (REG_VIP_DLC_BASE + 0x42) ++#define REG_VIP_DLC_21_H (REG_VIP_DLC_BASE + 0x43) ++#define REG_VIP_DLC_22_L (REG_VIP_DLC_BASE + 0x44) ++#define REG_VIP_DLC_22_H (REG_VIP_DLC_BASE + 0x45) ++#define REG_VIP_DLC_23_L (REG_VIP_DLC_BASE + 0x46) ++#define REG_VIP_DLC_23_H (REG_VIP_DLC_BASE + 0x47) ++#define REG_VIP_DLC_24_L (REG_VIP_DLC_BASE + 0x48) ++#define REG_VIP_DLC_24_H (REG_VIP_DLC_BASE + 0x49) ++#define REG_VIP_DLC_25_L (REG_VIP_DLC_BASE + 0x4A) ++#define REG_VIP_DLC_25_H (REG_VIP_DLC_BASE + 0x4B) ++#define REG_VIP_DLC_26_L (REG_VIP_DLC_BASE + 0x4C) ++#define REG_VIP_DLC_26_H (REG_VIP_DLC_BASE + 0x4D) ++#define REG_VIP_DLC_27_L (REG_VIP_DLC_BASE + 0x4E) ++#define REG_VIP_DLC_27_H (REG_VIP_DLC_BASE + 0x4F) ++#define REG_VIP_DLC_28_L (REG_VIP_DLC_BASE + 0x50) ++#define REG_VIP_DLC_28_H (REG_VIP_DLC_BASE + 0x51) ++#define REG_VIP_DLC_29_L (REG_VIP_DLC_BASE + 0x52) ++#define REG_VIP_DLC_29_H (REG_VIP_DLC_BASE + 0x53) ++#define REG_VIP_DLC_2A_L (REG_VIP_DLC_BASE + 0x54) ++#define REG_VIP_DLC_2A_H (REG_VIP_DLC_BASE + 0x55) ++#define REG_VIP_DLC_2B_L (REG_VIP_DLC_BASE + 0x56) ++#define REG_VIP_DLC_2B_H (REG_VIP_DLC_BASE + 0x57) ++#define REG_VIP_DLC_2C_L (REG_VIP_DLC_BASE + 0x58) ++#define REG_VIP_DLC_2C_H (REG_VIP_DLC_BASE + 0x59) ++#define REG_VIP_DLC_2D_L (REG_VIP_DLC_BASE + 0x5A) ++#define REG_VIP_DLC_2D_H (REG_VIP_DLC_BASE + 0x5B) ++#define REG_VIP_DLC_2E_L (REG_VIP_DLC_BASE + 0x5C) ++#define REG_VIP_DLC_2E_H (REG_VIP_DLC_BASE + 0x5D) ++#define REG_VIP_DLC_2F_L (REG_VIP_DLC_BASE + 0x5E) ++#define REG_VIP_DLC_2F_H (REG_VIP_DLC_BASE + 0x5F) ++#define REG_VIP_DLC_30_L (REG_VIP_DLC_BASE + 0x60) ++#define REG_VIP_DLC_30_H (REG_VIP_DLC_BASE + 0x61) ++#define REG_VIP_DLC_31_L (REG_VIP_DLC_BASE + 0x62) ++#define REG_VIP_DLC_31_H (REG_VIP_DLC_BASE + 0x63) ++#define REG_VIP_DLC_32_L (REG_VIP_DLC_BASE + 0x64) ++#define REG_VIP_DLC_32_H (REG_VIP_DLC_BASE + 0x65) ++#define REG_VIP_DLC_33_L (REG_VIP_DLC_BASE + 0x66) ++#define REG_VIP_DLC_33_H (REG_VIP_DLC_BASE + 0x67) ++#define REG_VIP_DLC_34_L (REG_VIP_DLC_BASE + 0x68) ++#define REG_VIP_DLC_34_H (REG_VIP_DLC_BASE + 0x69) ++#define REG_VIP_DLC_35_L (REG_VIP_DLC_BASE + 0x6A) ++#define REG_VIP_DLC_35_H (REG_VIP_DLC_BASE + 0x6B) ++#define REG_VIP_DLC_36_L (REG_VIP_DLC_BASE + 0x6C) ++#define REG_VIP_DLC_36_H (REG_VIP_DLC_BASE + 0x6D) ++#define REG_VIP_DLC_37_L (REG_VIP_DLC_BASE + 0x6E) ++#define REG_VIP_DLC_37_H (REG_VIP_DLC_BASE + 0x6F) ++#define REG_VIP_DLC_38_L (REG_VIP_DLC_BASE + 0x70) ++#define REG_VIP_DLC_38_H (REG_VIP_DLC_BASE + 0x71) ++#define REG_VIP_DLC_39_L (REG_VIP_DLC_BASE + 0x72) ++#define REG_VIP_DLC_39_H (REG_VIP_DLC_BASE + 0x73) ++#define REG_VIP_DLC_3A_L (REG_VIP_DLC_BASE + 0x74) ++#define REG_VIP_DLC_3A_H (REG_VIP_DLC_BASE + 0x75) ++#define REG_VIP_DLC_3B_L (REG_VIP_DLC_BASE + 0x76) ++#define REG_VIP_DLC_3B_H (REG_VIP_DLC_BASE + 0x77) ++#define REG_VIP_DLC_3C_L (REG_VIP_DLC_BASE + 0x78) ++#define REG_VIP_DLC_3C_H (REG_VIP_DLC_BASE + 0x79) ++#define REG_VIP_DLC_3D_L (REG_VIP_DLC_BASE + 0x7A) ++#define REG_VIP_DLC_3D_H (REG_VIP_DLC_BASE + 0x7B) ++#define REG_VIP_DLC_3E_L (REG_VIP_DLC_BASE + 0x7C) ++#define REG_VIP_DLC_3E_H (REG_VIP_DLC_BASE + 0x7D) ++#define REG_VIP_DLC_3F_L (REG_VIP_DLC_BASE + 0x7E) ++#define REG_VIP_DLC_3F_H (REG_VIP_DLC_BASE + 0x7F) ++#define REG_VIP_DLC_40_L (REG_VIP_DLC_BASE + 0x80) ++#define REG_VIP_DLC_40_H (REG_VIP_DLC_BASE + 0x81) ++#define REG_VIP_DLC_41_L (REG_VIP_DLC_BASE + 0x82) ++#define REG_VIP_DLC_41_H (REG_VIP_DLC_BASE + 0x83) ++#define REG_VIP_DLC_42_L (REG_VIP_DLC_BASE + 0x84) ++#define REG_VIP_DLC_42_H (REG_VIP_DLC_BASE + 0x85) ++#define REG_VIP_DLC_43_L (REG_VIP_DLC_BASE + 0x86) ++#define REG_VIP_DLC_43_H (REG_VIP_DLC_BASE + 0x87) ++#define REG_VIP_DLC_44_L (REG_VIP_DLC_BASE + 0x88) ++#define REG_VIP_DLC_44_H (REG_VIP_DLC_BASE + 0x89) ++#define REG_VIP_DLC_45_L (REG_VIP_DLC_BASE + 0x8A) ++#define REG_VIP_DLC_45_H (REG_VIP_DLC_BASE + 0x8B) ++#define REG_VIP_DLC_46_L (REG_VIP_DLC_BASE + 0x8C) ++#define REG_VIP_DLC_46_H (REG_VIP_DLC_BASE + 0x8D) ++#define REG_VIP_DLC_47_L (REG_VIP_DLC_BASE + 0x8E) ++#define REG_VIP_DLC_47_H (REG_VIP_DLC_BASE + 0x8F) ++#define REG_VIP_DLC_48_L (REG_VIP_DLC_BASE + 0x90) ++#define REG_VIP_DLC_48_H (REG_VIP_DLC_BASE + 0x91) ++#define REG_VIP_DLC_49_L (REG_VIP_DLC_BASE + 0x92) ++#define REG_VIP_DLC_49_H (REG_VIP_DLC_BASE + 0x93) ++#define REG_VIP_DLC_4A_L (REG_VIP_DLC_BASE + 0x94) ++#define REG_VIP_DLC_4A_H (REG_VIP_DLC_BASE + 0x95) ++#define REG_VIP_DLC_4B_L (REG_VIP_DLC_BASE + 0x96) ++#define REG_VIP_DLC_4B_H (REG_VIP_DLC_BASE + 0x97) ++#define REG_VIP_DLC_4C_L (REG_VIP_DLC_BASE + 0x98) ++#define REG_VIP_DLC_4C_H (REG_VIP_DLC_BASE + 0x99) ++#define REG_VIP_DLC_4D_L (REG_VIP_DLC_BASE + 0x9A) ++#define REG_VIP_DLC_4D_H (REG_VIP_DLC_BASE + 0x9B) ++#define REG_VIP_DLC_4E_L (REG_VIP_DLC_BASE + 0x9C) ++#define REG_VIP_DLC_4E_H (REG_VIP_DLC_BASE + 0x9D) ++#define REG_VIP_DLC_4F_L (REG_VIP_DLC_BASE + 0x9E) ++#define REG_VIP_DLC_4F_H (REG_VIP_DLC_BASE + 0x9F) ++#define REG_VIP_DLC_50_L (REG_VIP_DLC_BASE + 0xA0) ++#define REG_VIP_DLC_50_H (REG_VIP_DLC_BASE + 0xA1) ++#define REG_VIP_DLC_51_L (REG_VIP_DLC_BASE + 0xA2) ++#define REG_VIP_DLC_51_H (REG_VIP_DLC_BASE + 0xA3) ++#define REG_VIP_DLC_52_L (REG_VIP_DLC_BASE + 0xA4) ++#define REG_VIP_DLC_52_H (REG_VIP_DLC_BASE + 0xA5) ++#define REG_VIP_DLC_53_L (REG_VIP_DLC_BASE + 0xA6) ++#define REG_VIP_DLC_53_H (REG_VIP_DLC_BASE + 0xA7) ++#define REG_VIP_DLC_54_L (REG_VIP_DLC_BASE + 0xA8) ++#define REG_VIP_DLC_54_H (REG_VIP_DLC_BASE + 0xA9) ++#define REG_VIP_DLC_55_L (REG_VIP_DLC_BASE + 0xAA) ++#define REG_VIP_DLC_55_H (REG_VIP_DLC_BASE + 0xAB) ++#define REG_VIP_DLC_56_L (REG_VIP_DLC_BASE + 0xAC) ++#define REG_VIP_DLC_56_H (REG_VIP_DLC_BASE + 0xAD) ++#define REG_VIP_DLC_57_L (REG_VIP_DLC_BASE + 0xAE) ++#define REG_VIP_DLC_57_H (REG_VIP_DLC_BASE + 0xAF) ++#define REG_VIP_DLC_58_L (REG_VIP_DLC_BASE + 0xB0) ++#define REG_VIP_DLC_58_H (REG_VIP_DLC_BASE + 0xB1) ++#define REG_VIP_DLC_59_L (REG_VIP_DLC_BASE + 0xB2) ++#define REG_VIP_DLC_59_H (REG_VIP_DLC_BASE + 0xB3) ++#define REG_VIP_DLC_5A_L (REG_VIP_DLC_BASE + 0xB4) ++#define REG_VIP_DLC_5A_H (REG_VIP_DLC_BASE + 0xB5) ++#define REG_VIP_DLC_5B_L (REG_VIP_DLC_BASE + 0xB6) ++#define REG_VIP_DLC_5B_H (REG_VIP_DLC_BASE + 0xB7) ++#define REG_VIP_DLC_5C_L (REG_VIP_DLC_BASE + 0xB8) ++#define REG_VIP_DLC_5C_H (REG_VIP_DLC_BASE + 0xB9) ++#define REG_VIP_DLC_5D_L (REG_VIP_DLC_BASE + 0xBA) ++#define REG_VIP_DLC_5D_H (REG_VIP_DLC_BASE + 0xBB) ++#define REG_VIP_DLC_5E_L (REG_VIP_DLC_BASE + 0xBC) ++#define REG_VIP_DLC_5E_H (REG_VIP_DLC_BASE + 0xBD) ++#define REG_VIP_DLC_5F_L (REG_VIP_DLC_BASE + 0xBE) ++#define REG_VIP_DLC_5F_H (REG_VIP_DLC_BASE + 0xBF) ++#define REG_VIP_DLC_60_L (REG_VIP_DLC_BASE + 0xC0) ++#define REG_VIP_DLC_60_H (REG_VIP_DLC_BASE + 0xC1) ++#define REG_VIP_DLC_61_L (REG_VIP_DLC_BASE + 0xC2) ++#define REG_VIP_DLC_61_H (REG_VIP_DLC_BASE + 0xC3) ++#define REG_VIP_DLC_62_L (REG_VIP_DLC_BASE + 0xC4) ++#define REG_VIP_DLC_62_H (REG_VIP_DLC_BASE + 0xC5) ++#define REG_VIP_DLC_63_L (REG_VIP_DLC_BASE + 0xC6) ++#define REG_VIP_DLC_63_H (REG_VIP_DLC_BASE + 0xC7) ++#define REG_VIP_DLC_64_L (REG_VIP_DLC_BASE + 0xC8) ++#define REG_VIP_DLC_64_H (REG_VIP_DLC_BASE + 0xC9) ++#define REG_VIP_DLC_65_L (REG_VIP_DLC_BASE + 0xCA) ++#define REG_VIP_DLC_65_H (REG_VIP_DLC_BASE + 0xCB) ++#define REG_VIP_DLC_66_L (REG_VIP_DLC_BASE + 0xCC) ++#define REG_VIP_DLC_66_H (REG_VIP_DLC_BASE + 0xCD) ++#define REG_VIP_DLC_67_L (REG_VIP_DLC_BASE + 0xCE) ++#define REG_VIP_DLC_67_H (REG_VIP_DLC_BASE + 0xCF) ++#define REG_VIP_DLC_68_L (REG_VIP_DLC_BASE + 0xD0) ++#define REG_VIP_DLC_68_H (REG_VIP_DLC_BASE + 0xD1) ++#define REG_VIP_DLC_69_L (REG_VIP_DLC_BASE + 0xD2) ++#define REG_VIP_DLC_69_H (REG_VIP_DLC_BASE + 0xD3) ++#define REG_VIP_DLC_6A_L (REG_VIP_DLC_BASE + 0xD4) ++#define REG_VIP_DLC_6A_H (REG_VIP_DLC_BASE + 0xD5) ++#define REG_VIP_DLC_6B_L (REG_VIP_DLC_BASE + 0xD6) ++#define REG_VIP_DLC_6B_H (REG_VIP_DLC_BASE + 0xD7) ++#define REG_VIP_DLC_6C_L (REG_VIP_DLC_BASE + 0xD8) ++#define REG_VIP_DLC_6C_H (REG_VIP_DLC_BASE + 0xD9) ++#define REG_VIP_DLC_6D_L (REG_VIP_DLC_BASE + 0xDA) ++#define REG_VIP_DLC_6D_H (REG_VIP_DLC_BASE + 0xDB) ++#define REG_VIP_DLC_6E_L (REG_VIP_DLC_BASE + 0xDC) ++#define REG_VIP_DLC_6E_H (REG_VIP_DLC_BASE + 0xDD) ++#define REG_VIP_DLC_6F_L (REG_VIP_DLC_BASE + 0xDE) ++#define REG_VIP_DLC_6F_H (REG_VIP_DLC_BASE + 0xDF) ++#define REG_VIP_DLC_70_L (REG_VIP_DLC_BASE + 0xE0) ++#define REG_VIP_DLC_70_H (REG_VIP_DLC_BASE + 0xE1) ++#define REG_VIP_DLC_71_L (REG_VIP_DLC_BASE + 0xE2) ++#define REG_VIP_DLC_71_H (REG_VIP_DLC_BASE + 0xE3) ++#define REG_VIP_DLC_72_L (REG_VIP_DLC_BASE + 0xE4) ++#define REG_VIP_DLC_72_H (REG_VIP_DLC_BASE + 0xE5) ++#define REG_VIP_DLC_73_L (REG_VIP_DLC_BASE + 0xE6) ++#define REG_VIP_DLC_73_H (REG_VIP_DLC_BASE + 0xE7) ++#define REG_VIP_DLC_74_L (REG_VIP_DLC_BASE + 0xE8) ++#define REG_VIP_DLC_74_H (REG_VIP_DLC_BASE + 0xE9) ++#define REG_VIP_DLC_75_L (REG_VIP_DLC_BASE + 0xEA) ++#define REG_VIP_DLC_75_H (REG_VIP_DLC_BASE + 0xEB) ++#define REG_VIP_DLC_76_L (REG_VIP_DLC_BASE + 0xEC) ++#define REG_VIP_DLC_76_H (REG_VIP_DLC_BASE + 0xED) ++#define REG_VIP_DLC_77_L (REG_VIP_DLC_BASE + 0xEE) ++#define REG_VIP_DLC_77_H (REG_VIP_DLC_BASE + 0xEF) ++#define REG_VIP_DLC_78_L (REG_VIP_DLC_BASE + 0xF0) ++#define REG_VIP_DLC_78_H (REG_VIP_DLC_BASE + 0xF1) ++#define REG_VIP_DLC_79_L (REG_VIP_DLC_BASE + 0xF2) ++#define REG_VIP_DLC_79_H (REG_VIP_DLC_BASE + 0xF3) ++#define REG_VIP_DLC_7A_L (REG_VIP_DLC_BASE + 0xF4) ++#define REG_VIP_DLC_7A_H (REG_VIP_DLC_BASE + 0xF5) ++#define REG_VIP_DLC_7B_L (REG_VIP_DLC_BASE + 0xF6) ++#define REG_VIP_DLC_7B_H (REG_VIP_DLC_BASE + 0xF7) ++#define REG_VIP_DLC_7C_L (REG_VIP_DLC_BASE + 0xF8) ++#define REG_VIP_DLC_7C_H (REG_VIP_DLC_BASE + 0xF9) ++#define REG_VIP_DLC_7D_L (REG_VIP_DLC_BASE + 0xFA) ++#define REG_VIP_DLC_7D_H (REG_VIP_DLC_BASE + 0xFB) ++#define REG_VIP_DLC_7E_L (REG_VIP_DLC_BASE + 0xFC) ++#define REG_VIP_DLC_7E_H (REG_VIP_DLC_BASE + 0xFD) ++#define REG_VIP_DLC_7F_L (REG_VIP_DLC_BASE + 0xFE) ++#define REG_VIP_DLC_7F_H (REG_VIP_DLC_BASE + 0xFF) ++ ++#define REG_VIP_MWE_00_L (REG_VIP_MWE_BASE + 0x00) ++#define REG_VIP_MWE_00_H (REG_VIP_MWE_BASE + 0x01) ++#define REG_VIP_MWE_01_L (REG_VIP_MWE_BASE + 0x02) ++#define REG_VIP_MWE_01_H (REG_VIP_MWE_BASE + 0x03) ++#define REG_VIP_MWE_02_L (REG_VIP_MWE_BASE + 0x04) ++#define REG_VIP_MWE_02_H (REG_VIP_MWE_BASE + 0x05) ++#define REG_VIP_MWE_03_L (REG_VIP_MWE_BASE + 0x06) ++#define REG_VIP_MWE_03_H (REG_VIP_MWE_BASE + 0x07) ++#define REG_VIP_MWE_04_L (REG_VIP_MWE_BASE + 0x08) ++#define REG_VIP_MWE_04_H (REG_VIP_MWE_BASE + 0x09) ++#define REG_VIP_MWE_05_L (REG_VIP_MWE_BASE + 0x0A) ++#define REG_VIP_MWE_05_H (REG_VIP_MWE_BASE + 0x0B) ++#define REG_VIP_MWE_06_L (REG_VIP_MWE_BASE + 0x0C) ++#define REG_VIP_MWE_06_H (REG_VIP_MWE_BASE + 0x0D) ++#define REG_VIP_MWE_07_L (REG_VIP_MWE_BASE + 0x0E) ++#define REG_VIP_MWE_07_H (REG_VIP_MWE_BASE + 0x0F) ++#define REG_VIP_MWE_08_L (REG_VIP_MWE_BASE + 0x10) ++#define REG_VIP_MWE_08_H (REG_VIP_MWE_BASE + 0x11) ++#define REG_VIP_MWE_09_L (REG_VIP_MWE_BASE + 0x12) ++#define REG_VIP_MWE_09_H (REG_VIP_MWE_BASE + 0x13) ++#define REG_VIP_MWE_0A_L (REG_VIP_MWE_BASE + 0x14) ++#define REG_VIP_MWE_0A_H (REG_VIP_MWE_BASE + 0x15) ++#define REG_VIP_MWE_0B_L (REG_VIP_MWE_BASE + 0x16) ++#define REG_VIP_MWE_0B_H (REG_VIP_MWE_BASE + 0x17) ++#define REG_VIP_MWE_0C_L (REG_VIP_MWE_BASE + 0x18) ++#define REG_VIP_MWE_0C_H (REG_VIP_MWE_BASE + 0x19) ++#define REG_VIP_MWE_0D_L (REG_VIP_MWE_BASE + 0x1A) ++#define REG_VIP_MWE_0D_H (REG_VIP_MWE_BASE + 0x1B) ++#define REG_VIP_MWE_0E_L (REG_VIP_MWE_BASE + 0x1C) ++#define REG_VIP_MWE_0E_H (REG_VIP_MWE_BASE + 0x1D) ++#define REG_VIP_MWE_0F_L (REG_VIP_MWE_BASE + 0x1E) ++#define REG_VIP_MWE_0F_H (REG_VIP_MWE_BASE + 0x1F) ++#define REG_VIP_MWE_10_L (REG_VIP_MWE_BASE + 0x20) ++#define REG_VIP_MWE_10_H (REG_VIP_MWE_BASE + 0x21) ++#define REG_VIP_MWE_11_L (REG_VIP_MWE_BASE + 0x22) ++#define REG_VIP_MWE_11_H (REG_VIP_MWE_BASE + 0x23) ++#define REG_VIP_MWE_12_L (REG_VIP_MWE_BASE + 0x24) ++#define REG_VIP_MWE_12_H (REG_VIP_MWE_BASE + 0x25) ++#define REG_VIP_MWE_13_L (REG_VIP_MWE_BASE + 0x26) ++#define REG_VIP_MWE_13_H (REG_VIP_MWE_BASE + 0x27) ++#define REG_VIP_MWE_14_L (REG_VIP_MWE_BASE + 0x28) ++#define REG_VIP_MWE_14_H (REG_VIP_MWE_BASE + 0x29) ++#define REG_VIP_MWE_15_L (REG_VIP_MWE_BASE + 0x2A) ++#define REG_VIP_MWE_15_H (REG_VIP_MWE_BASE + 0x2B) ++#define REG_VIP_MWE_16_L (REG_VIP_MWE_BASE + 0x2C) ++#define REG_VIP_MWE_16_H (REG_VIP_MWE_BASE + 0x2D) ++#define REG_VIP_MWE_17_L (REG_VIP_MWE_BASE + 0x2E) ++#define REG_VIP_MWE_17_H (REG_VIP_MWE_BASE + 0x2F) ++#define REG_VIP_MWE_18_L (REG_VIP_MWE_BASE + 0x30) ++#define REG_VIP_MWE_18_H (REG_VIP_MWE_BASE + 0x31) ++#define REG_VIP_MWE_19_L (REG_VIP_MWE_BASE + 0x32) ++#define REG_VIP_MWE_19_H (REG_VIP_MWE_BASE + 0x33) ++#define REG_VIP_MWE_1A_L (REG_VIP_MWE_BASE + 0x34) ++#define REG_VIP_MWE_1A_H (REG_VIP_MWE_BASE + 0x35) ++#define REG_VIP_MWE_1B_L (REG_VIP_MWE_BASE + 0x36) ++#define REG_VIP_MWE_1B_H (REG_VIP_MWE_BASE + 0x37) ++#define REG_VIP_MWE_1C_L (REG_VIP_MWE_BASE + 0x38) ++#define REG_VIP_MWE_1C_H (REG_VIP_MWE_BASE + 0x39) ++#define REG_VIP_MWE_1D_L (REG_VIP_MWE_BASE + 0x3A) ++#define REG_VIP_MWE_1D_H (REG_VIP_MWE_BASE + 0x3B) ++#define REG_VIP_MWE_1E_L (REG_VIP_MWE_BASE + 0x3C) ++#define REG_VIP_MWE_1E_H (REG_VIP_MWE_BASE + 0x3D) ++#define REG_VIP_MWE_1F_L (REG_VIP_MWE_BASE + 0x3E) ++#define REG_VIP_MWE_1F_H (REG_VIP_MWE_BASE + 0x3F) ++#define REG_VIP_MWE_20_L (REG_VIP_MWE_BASE + 0x40) ++#define REG_VIP_MWE_20_H (REG_VIP_MWE_BASE + 0x41) ++#define REG_VIP_MWE_21_L (REG_VIP_MWE_BASE + 0x42) ++#define REG_VIP_MWE_21_H (REG_VIP_MWE_BASE + 0x43) ++#define REG_VIP_MWE_22_L (REG_VIP_MWE_BASE + 0x44) ++#define REG_VIP_MWE_22_H (REG_VIP_MWE_BASE + 0x45) ++#define REG_VIP_MWE_23_L (REG_VIP_MWE_BASE + 0x46) ++#define REG_VIP_MWE_23_H (REG_VIP_MWE_BASE + 0x47) ++#define REG_VIP_MWE_24_L (REG_VIP_MWE_BASE + 0x48) ++#define REG_VIP_MWE_24_H (REG_VIP_MWE_BASE + 0x49) ++#define REG_VIP_MWE_25_L (REG_VIP_MWE_BASE + 0x4A) ++#define REG_VIP_MWE_25_H (REG_VIP_MWE_BASE + 0x4B) ++#define REG_VIP_MWE_26_L (REG_VIP_MWE_BASE + 0x4C) ++#define REG_VIP_MWE_26_H (REG_VIP_MWE_BASE + 0x4D) ++#define REG_VIP_MWE_27_L (REG_VIP_MWE_BASE + 0x4E) ++#define REG_VIP_MWE_27_H (REG_VIP_MWE_BASE + 0x4F) ++#define REG_VIP_MWE_28_L (REG_VIP_MWE_BASE + 0x50) ++#define REG_VIP_MWE_28_H (REG_VIP_MWE_BASE + 0x51) ++#define REG_VIP_MWE_29_L (REG_VIP_MWE_BASE + 0x52) ++#define REG_VIP_MWE_29_H (REG_VIP_MWE_BASE + 0x53) ++#define REG_VIP_MWE_2A_L (REG_VIP_MWE_BASE + 0x54) ++#define REG_VIP_MWE_2A_H (REG_VIP_MWE_BASE + 0x55) ++#define REG_VIP_MWE_2B_L (REG_VIP_MWE_BASE + 0x56) ++#define REG_VIP_MWE_2B_H (REG_VIP_MWE_BASE + 0x57) ++#define REG_VIP_MWE_2C_L (REG_VIP_MWE_BASE + 0x58) ++#define REG_VIP_MWE_2C_H (REG_VIP_MWE_BASE + 0x59) ++#define REG_VIP_MWE_2D_L (REG_VIP_MWE_BASE + 0x5A) ++#define REG_VIP_MWE_2D_H (REG_VIP_MWE_BASE + 0x5B) ++#define REG_VIP_MWE_2E_L (REG_VIP_MWE_BASE + 0x5C) ++#define REG_VIP_MWE_2E_H (REG_VIP_MWE_BASE + 0x5D) ++#define REG_VIP_MWE_2F_L (REG_VIP_MWE_BASE + 0x5E) ++#define REG_VIP_MWE_2F_H (REG_VIP_MWE_BASE + 0x5F) ++#define REG_VIP_MWE_30_L (REG_VIP_MWE_BASE + 0x60) ++#define REG_VIP_MWE_30_H (REG_VIP_MWE_BASE + 0x61) ++#define REG_VIP_MWE_31_L (REG_VIP_MWE_BASE + 0x62) ++#define REG_VIP_MWE_31_H (REG_VIP_MWE_BASE + 0x63) ++#define REG_VIP_MWE_32_L (REG_VIP_MWE_BASE + 0x64) ++#define REG_VIP_MWE_32_H (REG_VIP_MWE_BASE + 0x65) ++#define REG_VIP_MWE_33_L (REG_VIP_MWE_BASE + 0x66) ++#define REG_VIP_MWE_33_H (REG_VIP_MWE_BASE + 0x67) ++#define REG_VIP_MWE_34_L (REG_VIP_MWE_BASE + 0x68) ++#define REG_VIP_MWE_34_H (REG_VIP_MWE_BASE + 0x69) ++#define REG_VIP_MWE_35_L (REG_VIP_MWE_BASE + 0x6A) ++#define REG_VIP_MWE_35_H (REG_VIP_MWE_BASE + 0x6B) ++#define REG_VIP_MWE_36_L (REG_VIP_MWE_BASE + 0x6C) ++#define REG_VIP_MWE_36_H (REG_VIP_MWE_BASE + 0x6D) ++#define REG_VIP_MWE_37_L (REG_VIP_MWE_BASE + 0x6E) ++#define REG_VIP_MWE_37_H (REG_VIP_MWE_BASE + 0x6F) ++#define REG_VIP_MWE_38_L (REG_VIP_MWE_BASE + 0x70) ++#define REG_VIP_MWE_38_H (REG_VIP_MWE_BASE + 0x71) ++#define REG_VIP_MWE_39_L (REG_VIP_MWE_BASE + 0x72) ++#define REG_VIP_MWE_39_H (REG_VIP_MWE_BASE + 0x73) ++#define REG_VIP_MWE_3A_L (REG_VIP_MWE_BASE + 0x74) ++#define REG_VIP_MWE_3A_H (REG_VIP_MWE_BASE + 0x75) ++#define REG_VIP_MWE_3B_L (REG_VIP_MWE_BASE + 0x76) ++#define REG_VIP_MWE_3B_H (REG_VIP_MWE_BASE + 0x77) ++#define REG_VIP_MWE_3C_L (REG_VIP_MWE_BASE + 0x78) ++#define REG_VIP_MWE_3C_H (REG_VIP_MWE_BASE + 0x79) ++#define REG_VIP_MWE_3D_L (REG_VIP_MWE_BASE + 0x7A) ++#define REG_VIP_MWE_3D_H (REG_VIP_MWE_BASE + 0x7B) ++#define REG_VIP_MWE_3E_L (REG_VIP_MWE_BASE + 0x7C) ++#define REG_VIP_MWE_3E_H (REG_VIP_MWE_BASE + 0x7D) ++#define REG_VIP_MWE_3F_L (REG_VIP_MWE_BASE + 0x7E) ++#define REG_VIP_MWE_3F_H (REG_VIP_MWE_BASE + 0x7F) ++#define REG_VIP_MWE_40_L (REG_VIP_MWE_BASE + 0x80) ++#define REG_VIP_MWE_40_H (REG_VIP_MWE_BASE + 0x81) ++#define REG_VIP_MWE_41_L (REG_VIP_MWE_BASE + 0x82) ++#define REG_VIP_MWE_41_H (REG_VIP_MWE_BASE + 0x83) ++#define REG_VIP_MWE_42_L (REG_VIP_MWE_BASE + 0x84) ++#define REG_VIP_MWE_42_H (REG_VIP_MWE_BASE + 0x85) ++#define REG_VIP_MWE_43_L (REG_VIP_MWE_BASE + 0x86) ++#define REG_VIP_MWE_43_H (REG_VIP_MWE_BASE + 0x87) ++#define REG_VIP_MWE_44_L (REG_VIP_MWE_BASE + 0x88) ++#define REG_VIP_MWE_44_H (REG_VIP_MWE_BASE + 0x89) ++#define REG_VIP_MWE_45_L (REG_VIP_MWE_BASE + 0x8A) ++#define REG_VIP_MWE_45_H (REG_VIP_MWE_BASE + 0x8B) ++#define REG_VIP_MWE_46_L (REG_VIP_MWE_BASE + 0x8C) ++#define REG_VIP_MWE_46_H (REG_VIP_MWE_BASE + 0x8D) ++#define REG_VIP_MWE_47_L (REG_VIP_MWE_BASE + 0x8E) ++#define REG_VIP_MWE_47_H (REG_VIP_MWE_BASE + 0x8F) ++#define REG_VIP_MWE_48_L (REG_VIP_MWE_BASE + 0x90) ++#define REG_VIP_MWE_48_H (REG_VIP_MWE_BASE + 0x91) ++#define REG_VIP_MWE_49_L (REG_VIP_MWE_BASE + 0x92) ++#define REG_VIP_MWE_49_H (REG_VIP_MWE_BASE + 0x93) ++#define REG_VIP_MWE_4A_L (REG_VIP_MWE_BASE + 0x94) ++#define REG_VIP_MWE_4A_H (REG_VIP_MWE_BASE + 0x95) ++#define REG_VIP_MWE_4B_L (REG_VIP_MWE_BASE + 0x96) ++#define REG_VIP_MWE_4B_H (REG_VIP_MWE_BASE + 0x97) ++#define REG_VIP_MWE_4C_L (REG_VIP_MWE_BASE + 0x98) ++#define REG_VIP_MWE_4C_H (REG_VIP_MWE_BASE + 0x99) ++#define REG_VIP_MWE_4D_L (REG_VIP_MWE_BASE + 0x9A) ++#define REG_VIP_MWE_4D_H (REG_VIP_MWE_BASE + 0x9B) ++#define REG_VIP_MWE_4E_L (REG_VIP_MWE_BASE + 0x9C) ++#define REG_VIP_MWE_4E_H (REG_VIP_MWE_BASE + 0x9D) ++#define REG_VIP_MWE_4F_L (REG_VIP_MWE_BASE + 0x9E) ++#define REG_VIP_MWE_4F_H (REG_VIP_MWE_BASE + 0x9F) ++#define REG_VIP_MWE_50_L (REG_VIP_MWE_BASE + 0xA0) ++#define REG_VIP_MWE_50_H (REG_VIP_MWE_BASE + 0xA1) ++#define REG_VIP_MWE_51_L (REG_VIP_MWE_BASE + 0xA2) ++#define REG_VIP_MWE_51_H (REG_VIP_MWE_BASE + 0xA3) ++#define REG_VIP_MWE_52_L (REG_VIP_MWE_BASE + 0xA4) ++#define REG_VIP_MWE_52_H (REG_VIP_MWE_BASE + 0xA5) ++#define REG_VIP_MWE_53_L (REG_VIP_MWE_BASE + 0xA6) ++#define REG_VIP_MWE_53_H (REG_VIP_MWE_BASE + 0xA7) ++#define REG_VIP_MWE_54_L (REG_VIP_MWE_BASE + 0xA8) ++#define REG_VIP_MWE_54_H (REG_VIP_MWE_BASE + 0xA9) ++#define REG_VIP_MWE_55_L (REG_VIP_MWE_BASE + 0xAA) ++#define REG_VIP_MWE_55_H (REG_VIP_MWE_BASE + 0xAB) ++#define REG_VIP_MWE_56_L (REG_VIP_MWE_BASE + 0xAC) ++#define REG_VIP_MWE_56_H (REG_VIP_MWE_BASE + 0xAD) ++#define REG_VIP_MWE_57_L (REG_VIP_MWE_BASE + 0xAE) ++#define REG_VIP_MWE_57_H (REG_VIP_MWE_BASE + 0xAF) ++#define REG_VIP_MWE_58_L (REG_VIP_MWE_BASE + 0xB0) ++#define REG_VIP_MWE_58_H (REG_VIP_MWE_BASE + 0xB1) ++#define REG_VIP_MWE_59_L (REG_VIP_MWE_BASE + 0xB2) ++#define REG_VIP_MWE_59_H (REG_VIP_MWE_BASE + 0xB3) ++#define REG_VIP_MWE_5A_L (REG_VIP_MWE_BASE + 0xB4) ++#define REG_VIP_MWE_5A_H (REG_VIP_MWE_BASE + 0xB5) ++#define REG_VIP_MWE_5B_L (REG_VIP_MWE_BASE + 0xB6) ++#define REG_VIP_MWE_5B_H (REG_VIP_MWE_BASE + 0xB7) ++#define REG_VIP_MWE_5C_L (REG_VIP_MWE_BASE + 0xB8) ++#define REG_VIP_MWE_5C_H (REG_VIP_MWE_BASE + 0xB9) ++#define REG_VIP_MWE_5D_L (REG_VIP_MWE_BASE + 0xBA) ++#define REG_VIP_MWE_5D_H (REG_VIP_MWE_BASE + 0xBB) ++#define REG_VIP_MWE_5E_L (REG_VIP_MWE_BASE + 0xBC) ++#define REG_VIP_MWE_5E_H (REG_VIP_MWE_BASE + 0xBD) ++#define REG_VIP_MWE_5F_L (REG_VIP_MWE_BASE + 0xBE) ++#define REG_VIP_MWE_5F_H (REG_VIP_MWE_BASE + 0xBF) ++#define REG_VIP_MWE_60_L (REG_VIP_MWE_BASE + 0xC0) ++#define REG_VIP_MWE_60_H (REG_VIP_MWE_BASE + 0xC1) ++#define REG_VIP_MWE_61_L (REG_VIP_MWE_BASE + 0xC2) ++#define REG_VIP_MWE_61_H (REG_VIP_MWE_BASE + 0xC3) ++#define REG_VIP_MWE_62_L (REG_VIP_MWE_BASE + 0xC4) ++#define REG_VIP_MWE_62_H (REG_VIP_MWE_BASE + 0xC5) ++#define REG_VIP_MWE_63_L (REG_VIP_MWE_BASE + 0xC6) ++#define REG_VIP_MWE_63_H (REG_VIP_MWE_BASE + 0xC7) ++#define REG_VIP_MWE_64_L (REG_VIP_MWE_BASE + 0xC8) ++#define REG_VIP_MWE_64_H (REG_VIP_MWE_BASE + 0xC9) ++#define REG_VIP_MWE_65_L (REG_VIP_MWE_BASE + 0xCA) ++#define REG_VIP_MWE_65_H (REG_VIP_MWE_BASE + 0xCB) ++#define REG_VIP_MWE_66_L (REG_VIP_MWE_BASE + 0xCC) ++#define REG_VIP_MWE_66_H (REG_VIP_MWE_BASE + 0xCD) ++#define REG_VIP_MWE_67_L (REG_VIP_MWE_BASE + 0xCE) ++#define REG_VIP_MWE_67_H (REG_VIP_MWE_BASE + 0xCF) ++#define REG_VIP_MWE_68_L (REG_VIP_MWE_BASE + 0xD0) ++#define REG_VIP_MWE_68_H (REG_VIP_MWE_BASE + 0xD1) ++#define REG_VIP_MWE_69_L (REG_VIP_MWE_BASE + 0xD2) ++#define REG_VIP_MWE_69_H (REG_VIP_MWE_BASE + 0xD3) ++#define REG_VIP_MWE_6A_L (REG_VIP_MWE_BASE + 0xD4) ++#define REG_VIP_MWE_6A_H (REG_VIP_MWE_BASE + 0xD5) ++#define REG_VIP_MWE_6B_L (REG_VIP_MWE_BASE + 0xD6) ++#define REG_VIP_MWE_6B_H (REG_VIP_MWE_BASE + 0xD7) ++#define REG_VIP_MWE_6C_L (REG_VIP_MWE_BASE + 0xD8) ++#define REG_VIP_MWE_6C_H (REG_VIP_MWE_BASE + 0xD9) ++#define REG_VIP_MWE_6D_L (REG_VIP_MWE_BASE + 0xDA) ++#define REG_VIP_MWE_6D_H (REG_VIP_MWE_BASE + 0xDB) ++#define REG_VIP_MWE_6E_L (REG_VIP_MWE_BASE + 0xDC) ++#define REG_VIP_MWE_6E_H (REG_VIP_MWE_BASE + 0xDD) ++#define REG_VIP_MWE_6F_L (REG_VIP_MWE_BASE + 0xDE) ++#define REG_VIP_MWE_6F_H (REG_VIP_MWE_BASE + 0xDF) ++#define REG_VIP_MWE_70_L (REG_VIP_MWE_BASE + 0xE0) ++#define REG_VIP_MWE_70_H (REG_VIP_MWE_BASE + 0xE1) ++#define REG_VIP_MWE_71_L (REG_VIP_MWE_BASE + 0xE2) ++#define REG_VIP_MWE_71_H (REG_VIP_MWE_BASE + 0xE3) ++#define REG_VIP_MWE_72_L (REG_VIP_MWE_BASE + 0xE4) ++#define REG_VIP_MWE_72_H (REG_VIP_MWE_BASE + 0xE5) ++#define REG_VIP_MWE_73_L (REG_VIP_MWE_BASE + 0xE6) ++#define REG_VIP_MWE_73_H (REG_VIP_MWE_BASE + 0xE7) ++#define REG_VIP_MWE_74_L (REG_VIP_MWE_BASE + 0xE8) ++#define REG_VIP_MWE_74_H (REG_VIP_MWE_BASE + 0xE9) ++#define REG_VIP_MWE_75_L (REG_VIP_MWE_BASE + 0xEA) ++#define REG_VIP_MWE_75_H (REG_VIP_MWE_BASE + 0xEB) ++#define REG_VIP_MWE_76_L (REG_VIP_MWE_BASE + 0xEC) ++#define REG_VIP_MWE_76_H (REG_VIP_MWE_BASE + 0xED) ++#define REG_VIP_MWE_77_L (REG_VIP_MWE_BASE + 0xEE) ++#define REG_VIP_MWE_77_H (REG_VIP_MWE_BASE + 0xEF) ++#define REG_VIP_MWE_78_L (REG_VIP_MWE_BASE + 0xF0) ++#define REG_VIP_MWE_78_H (REG_VIP_MWE_BASE + 0xF1) ++#define REG_VIP_MWE_79_L (REG_VIP_MWE_BASE + 0xF2) ++#define REG_VIP_MWE_79_H (REG_VIP_MWE_BASE + 0xF3) ++#define REG_VIP_MWE_7A_L (REG_VIP_MWE_BASE + 0xF4) ++#define REG_VIP_MWE_7A_H (REG_VIP_MWE_BASE + 0xF5) ++#define REG_VIP_MWE_7B_L (REG_VIP_MWE_BASE + 0xF6) ++#define REG_VIP_MWE_7B_H (REG_VIP_MWE_BASE + 0xF7) ++#define REG_VIP_MWE_7C_L (REG_VIP_MWE_BASE + 0xF8) ++#define REG_VIP_MWE_7C_H (REG_VIP_MWE_BASE + 0xF9) ++#define REG_VIP_MWE_7D_L (REG_VIP_MWE_BASE + 0xFA) ++#define REG_VIP_MWE_7D_H (REG_VIP_MWE_BASE + 0xFB) ++#define REG_VIP_MWE_7E_L (REG_VIP_MWE_BASE + 0xFC) ++#define REG_VIP_MWE_7E_H (REG_VIP_MWE_BASE + 0xFD) ++#define REG_VIP_MWE_7F_L (REG_VIP_MWE_BASE + 0xFE) ++#define REG_VIP_MWE_7F_H (REG_VIP_MWE_BASE + 0xFF) ++ ++#define REG_VIP_LCE_00_L (REG_VIP_LCE_BASE + 0x00) ++#define REG_VIP_LCE_00_H (REG_VIP_LCE_BASE + 0x01) ++#define REG_VIP_LCE_01_L (REG_VIP_LCE_BASE + 0x02) ++#define REG_VIP_LCE_01_H (REG_VIP_LCE_BASE + 0x03) ++#define REG_VIP_LCE_02_L (REG_VIP_LCE_BASE + 0x04) ++#define REG_VIP_LCE_02_H (REG_VIP_LCE_BASE + 0x05) ++#define REG_VIP_LCE_03_L (REG_VIP_LCE_BASE + 0x06) ++#define REG_VIP_LCE_03_H (REG_VIP_LCE_BASE + 0x07) ++#define REG_VIP_LCE_04_L (REG_VIP_LCE_BASE + 0x08) ++#define REG_VIP_LCE_04_H (REG_VIP_LCE_BASE + 0x09) ++#define REG_VIP_LCE_05_L (REG_VIP_LCE_BASE + 0x0A) ++#define REG_VIP_LCE_05_H (REG_VIP_LCE_BASE + 0x0B) ++#define REG_VIP_LCE_06_L (REG_VIP_LCE_BASE + 0x0C) ++#define REG_VIP_LCE_06_H (REG_VIP_LCE_BASE + 0x0D) ++#define REG_VIP_LCE_07_L (REG_VIP_LCE_BASE + 0x0E) ++#define REG_VIP_LCE_07_H (REG_VIP_LCE_BASE + 0x0F) ++#define REG_VIP_LCE_08_L (REG_VIP_LCE_BASE + 0x10) ++#define REG_VIP_LCE_08_H (REG_VIP_LCE_BASE + 0x11) ++#define REG_VIP_LCE_09_L (REG_VIP_LCE_BASE + 0x12) ++#define REG_VIP_LCE_09_H (REG_VIP_LCE_BASE + 0x13) ++#define REG_VIP_LCE_0A_L (REG_VIP_LCE_BASE + 0x14) ++#define REG_VIP_LCE_0A_H (REG_VIP_LCE_BASE + 0x15) ++#define REG_VIP_LCE_0B_L (REG_VIP_LCE_BASE + 0x16) ++#define REG_VIP_LCE_0B_H (REG_VIP_LCE_BASE + 0x17) ++#define REG_VIP_LCE_0C_L (REG_VIP_LCE_BASE + 0x18) ++#define REG_VIP_LCE_0C_H (REG_VIP_LCE_BASE + 0x19) ++#define REG_VIP_LCE_0D_L (REG_VIP_LCE_BASE + 0x1A) ++#define REG_VIP_LCE_0D_H (REG_VIP_LCE_BASE + 0x1B) ++#define REG_VIP_LCE_0E_L (REG_VIP_LCE_BASE + 0x1C) ++#define REG_VIP_LCE_0E_H (REG_VIP_LCE_BASE + 0x1D) ++#define REG_VIP_LCE_0F_L (REG_VIP_LCE_BASE + 0x1E) ++#define REG_VIP_LCE_0F_H (REG_VIP_LCE_BASE + 0x1F) ++#define REG_VIP_LCE_10_L (REG_VIP_LCE_BASE + 0x20) ++#define REG_VIP_LCE_10_H (REG_VIP_LCE_BASE + 0x21) ++#define REG_VIP_LCE_11_L (REG_VIP_LCE_BASE + 0x22) ++#define REG_VIP_LCE_11_H (REG_VIP_LCE_BASE + 0x23) ++#define REG_VIP_LCE_12_L (REG_VIP_LCE_BASE + 0x24) ++#define REG_VIP_LCE_12_H (REG_VIP_LCE_BASE + 0x25) ++#define REG_VIP_LCE_13_L (REG_VIP_LCE_BASE + 0x26) ++#define REG_VIP_LCE_13_H (REG_VIP_LCE_BASE + 0x27) ++#define REG_VIP_LCE_14_L (REG_VIP_LCE_BASE + 0x28) ++#define REG_VIP_LCE_14_H (REG_VIP_LCE_BASE + 0x29) ++#define REG_VIP_LCE_15_L (REG_VIP_LCE_BASE + 0x2A) ++#define REG_VIP_LCE_15_H (REG_VIP_LCE_BASE + 0x2B) ++#define REG_VIP_LCE_16_L (REG_VIP_LCE_BASE + 0x2C) ++#define REG_VIP_LCE_16_H (REG_VIP_LCE_BASE + 0x2D) ++#define REG_VIP_LCE_17_L (REG_VIP_LCE_BASE + 0x2E) ++#define REG_VIP_LCE_17_H (REG_VIP_LCE_BASE + 0x2F) ++#define REG_VIP_LCE_18_L (REG_VIP_LCE_BASE + 0x30) ++#define REG_VIP_LCE_18_H (REG_VIP_LCE_BASE + 0x31) ++#define REG_VIP_LCE_19_L (REG_VIP_LCE_BASE + 0x32) ++#define REG_VIP_LCE_19_H (REG_VIP_LCE_BASE + 0x33) ++#define REG_VIP_LCE_1A_L (REG_VIP_LCE_BASE + 0x34) ++#define REG_VIP_LCE_1A_H (REG_VIP_LCE_BASE + 0x35) ++#define REG_VIP_LCE_1B_L (REG_VIP_LCE_BASE + 0x36) ++#define REG_VIP_LCE_1B_H (REG_VIP_LCE_BASE + 0x37) ++#define REG_VIP_LCE_1C_L (REG_VIP_LCE_BASE + 0x38) ++#define REG_VIP_LCE_1C_H (REG_VIP_LCE_BASE + 0x39) ++#define REG_VIP_LCE_1D_L (REG_VIP_LCE_BASE + 0x3A) ++#define REG_VIP_LCE_1D_H (REG_VIP_LCE_BASE + 0x3B) ++#define REG_VIP_LCE_1E_L (REG_VIP_LCE_BASE + 0x3C) ++#define REG_VIP_LCE_1E_H (REG_VIP_LCE_BASE + 0x3D) ++#define REG_VIP_LCE_1F_L (REG_VIP_LCE_BASE + 0x3E) ++#define REG_VIP_LCE_1F_H (REG_VIP_LCE_BASE + 0x3F) ++#define REG_VIP_LCE_20_L (REG_VIP_LCE_BASE + 0x40) ++#define REG_VIP_LCE_20_H (REG_VIP_LCE_BASE + 0x41) ++#define REG_VIP_LCE_21_L (REG_VIP_LCE_BASE + 0x42) ++#define REG_VIP_LCE_21_H (REG_VIP_LCE_BASE + 0x43) ++#define REG_VIP_LCE_22_L (REG_VIP_LCE_BASE + 0x44) ++#define REG_VIP_LCE_22_H (REG_VIP_LCE_BASE + 0x45) ++#define REG_VIP_LCE_23_L (REG_VIP_LCE_BASE + 0x46) ++#define REG_VIP_LCE_23_H (REG_VIP_LCE_BASE + 0x47) ++#define REG_VIP_LCE_24_L (REG_VIP_LCE_BASE + 0x48) ++#define REG_VIP_LCE_24_H (REG_VIP_LCE_BASE + 0x49) ++#define REG_VIP_LCE_25_L (REG_VIP_LCE_BASE + 0x4A) ++#define REG_VIP_LCE_25_H (REG_VIP_LCE_BASE + 0x4B) ++#define REG_VIP_LCE_26_L (REG_VIP_LCE_BASE + 0x4C) ++#define REG_VIP_LCE_26_H (REG_VIP_LCE_BASE + 0x4D) ++#define REG_VIP_LCE_27_L (REG_VIP_LCE_BASE + 0x4E) ++#define REG_VIP_LCE_27_H (REG_VIP_LCE_BASE + 0x4F) ++#define REG_VIP_LCE_28_L (REG_VIP_LCE_BASE + 0x50) ++#define REG_VIP_LCE_28_H (REG_VIP_LCE_BASE + 0x51) ++#define REG_VIP_LCE_29_L (REG_VIP_LCE_BASE + 0x52) ++#define REG_VIP_LCE_29_H (REG_VIP_LCE_BASE + 0x53) ++#define REG_VIP_LCE_2A_L (REG_VIP_LCE_BASE + 0x54) ++#define REG_VIP_LCE_2A_H (REG_VIP_LCE_BASE + 0x55) ++#define REG_VIP_LCE_2B_L (REG_VIP_LCE_BASE + 0x56) ++#define REG_VIP_LCE_2B_H (REG_VIP_LCE_BASE + 0x57) ++#define REG_VIP_LCE_2C_L (REG_VIP_LCE_BASE + 0x58) ++#define REG_VIP_LCE_2C_H (REG_VIP_LCE_BASE + 0x59) ++#define REG_VIP_LCE_2D_L (REG_VIP_LCE_BASE + 0x5A) ++#define REG_VIP_LCE_2D_H (REG_VIP_LCE_BASE + 0x5B) ++#define REG_VIP_LCE_2E_L (REG_VIP_LCE_BASE + 0x5C) ++#define REG_VIP_LCE_2E_H (REG_VIP_LCE_BASE + 0x5D) ++#define REG_VIP_LCE_2F_L (REG_VIP_LCE_BASE + 0x5E) ++#define REG_VIP_LCE_2F_H (REG_VIP_LCE_BASE + 0x5F) ++#define REG_VIP_LCE_30_L (REG_VIP_LCE_BASE + 0x60) ++#define REG_VIP_LCE_30_H (REG_VIP_LCE_BASE + 0x61) ++#define REG_VIP_LCE_31_L (REG_VIP_LCE_BASE + 0x62) ++#define REG_VIP_LCE_31_H (REG_VIP_LCE_BASE + 0x63) ++#define REG_VIP_LCE_32_L (REG_VIP_LCE_BASE + 0x64) ++#define REG_VIP_LCE_32_H (REG_VIP_LCE_BASE + 0x65) ++#define REG_VIP_LCE_33_L (REG_VIP_LCE_BASE + 0x66) ++#define REG_VIP_LCE_33_H (REG_VIP_LCE_BASE + 0x67) ++#define REG_VIP_LCE_34_L (REG_VIP_LCE_BASE + 0x68) ++#define REG_VIP_LCE_34_H (REG_VIP_LCE_BASE + 0x69) ++#define REG_VIP_LCE_35_L (REG_VIP_LCE_BASE + 0x6A) ++#define REG_VIP_LCE_35_H (REG_VIP_LCE_BASE + 0x6B) ++#define REG_VIP_LCE_36_L (REG_VIP_LCE_BASE + 0x6C) ++#define REG_VIP_LCE_36_H (REG_VIP_LCE_BASE + 0x6D) ++#define REG_VIP_LCE_37_L (REG_VIP_LCE_BASE + 0x6E) ++#define REG_VIP_LCE_37_H (REG_VIP_LCE_BASE + 0x6F) ++#define REG_VIP_LCE_38_L (REG_VIP_LCE_BASE + 0x70) ++#define REG_VIP_LCE_38_H (REG_VIP_LCE_BASE + 0x71) ++#define REG_VIP_LCE_39_L (REG_VIP_LCE_BASE + 0x72) ++#define REG_VIP_LCE_39_H (REG_VIP_LCE_BASE + 0x73) ++#define REG_VIP_LCE_3A_L (REG_VIP_LCE_BASE + 0x74) ++#define REG_VIP_LCE_3A_H (REG_VIP_LCE_BASE + 0x75) ++#define REG_VIP_LCE_3B_L (REG_VIP_LCE_BASE + 0x76) ++#define REG_VIP_LCE_3B_H (REG_VIP_LCE_BASE + 0x77) ++#define REG_VIP_LCE_3C_L (REG_VIP_LCE_BASE + 0x78) ++#define REG_VIP_LCE_3C_H (REG_VIP_LCE_BASE + 0x79) ++#define REG_VIP_LCE_3D_L (REG_VIP_LCE_BASE + 0x7A) ++#define REG_VIP_LCE_3D_H (REG_VIP_LCE_BASE + 0x7B) ++#define REG_VIP_LCE_3E_L (REG_VIP_LCE_BASE + 0x7C) ++#define REG_VIP_LCE_3E_H (REG_VIP_LCE_BASE + 0x7D) ++#define REG_VIP_LCE_3F_L (REG_VIP_LCE_BASE + 0x7E) ++#define REG_VIP_LCE_3F_H (REG_VIP_LCE_BASE + 0x7F) ++#define REG_VIP_LCE_40_L (REG_VIP_LCE_BASE + 0x80) ++#define REG_VIP_LCE_40_H (REG_VIP_LCE_BASE + 0x81) ++#define REG_VIP_LCE_41_L (REG_VIP_LCE_BASE + 0x82) ++#define REG_VIP_LCE_41_H (REG_VIP_LCE_BASE + 0x83) ++#define REG_VIP_LCE_42_L (REG_VIP_LCE_BASE + 0x84) ++#define REG_VIP_LCE_42_H (REG_VIP_LCE_BASE + 0x85) ++#define REG_VIP_LCE_43_L (REG_VIP_LCE_BASE + 0x86) ++#define REG_VIP_LCE_43_H (REG_VIP_LCE_BASE + 0x87) ++#define REG_VIP_LCE_44_L (REG_VIP_LCE_BASE + 0x88) ++#define REG_VIP_LCE_44_H (REG_VIP_LCE_BASE + 0x89) ++#define REG_VIP_LCE_45_L (REG_VIP_LCE_BASE + 0x8A) ++#define REG_VIP_LCE_45_H (REG_VIP_LCE_BASE + 0x8B) ++#define REG_VIP_LCE_46_L (REG_VIP_LCE_BASE + 0x8C) ++#define REG_VIP_LCE_46_H (REG_VIP_LCE_BASE + 0x8D) ++#define REG_VIP_LCE_47_L (REG_VIP_LCE_BASE + 0x8E) ++#define REG_VIP_LCE_47_H (REG_VIP_LCE_BASE + 0x8F) ++#define REG_VIP_LCE_48_L (REG_VIP_LCE_BASE + 0x90) ++#define REG_VIP_LCE_48_H (REG_VIP_LCE_BASE + 0x91) ++#define REG_VIP_LCE_49_L (REG_VIP_LCE_BASE + 0x92) ++#define REG_VIP_LCE_49_H (REG_VIP_LCE_BASE + 0x93) ++#define REG_VIP_LCE_4A_L (REG_VIP_LCE_BASE + 0x94) ++#define REG_VIP_LCE_4A_H (REG_VIP_LCE_BASE + 0x95) ++#define REG_VIP_LCE_4B_L (REG_VIP_LCE_BASE + 0x96) ++#define REG_VIP_LCE_4B_H (REG_VIP_LCE_BASE + 0x97) ++#define REG_VIP_LCE_4C_L (REG_VIP_LCE_BASE + 0x98) ++#define REG_VIP_LCE_4C_H (REG_VIP_LCE_BASE + 0x99) ++#define REG_VIP_LCE_4D_L (REG_VIP_LCE_BASE + 0x9A) ++#define REG_VIP_LCE_4D_H (REG_VIP_LCE_BASE + 0x9B) ++#define REG_VIP_LCE_4E_L (REG_VIP_LCE_BASE + 0x9C) ++#define REG_VIP_LCE_4E_H (REG_VIP_LCE_BASE + 0x9D) ++#define REG_VIP_LCE_4F_L (REG_VIP_LCE_BASE + 0x9E) ++#define REG_VIP_LCE_4F_H (REG_VIP_LCE_BASE + 0x9F) ++#define REG_VIP_LCE_50_L (REG_VIP_LCE_BASE + 0xA0) ++#define REG_VIP_LCE_50_H (REG_VIP_LCE_BASE + 0xA1) ++#define REG_VIP_LCE_51_L (REG_VIP_LCE_BASE + 0xA2) ++#define REG_VIP_LCE_51_H (REG_VIP_LCE_BASE + 0xA3) ++#define REG_VIP_LCE_52_L (REG_VIP_LCE_BASE + 0xA4) ++#define REG_VIP_LCE_52_H (REG_VIP_LCE_BASE + 0xA5) ++#define REG_VIP_LCE_53_L (REG_VIP_LCE_BASE + 0xA6) ++#define REG_VIP_LCE_53_H (REG_VIP_LCE_BASE + 0xA7) ++#define REG_VIP_LCE_54_L (REG_VIP_LCE_BASE + 0xA8) ++#define REG_VIP_LCE_54_H (REG_VIP_LCE_BASE + 0xA9) ++#define REG_VIP_LCE_55_L (REG_VIP_LCE_BASE + 0xAA) ++#define REG_VIP_LCE_55_H (REG_VIP_LCE_BASE + 0xAB) ++#define REG_VIP_LCE_56_L (REG_VIP_LCE_BASE + 0xAC) ++#define REG_VIP_LCE_56_H (REG_VIP_LCE_BASE + 0xAD) ++#define REG_VIP_LCE_57_L (REG_VIP_LCE_BASE + 0xAE) ++#define REG_VIP_LCE_57_H (REG_VIP_LCE_BASE + 0xAF) ++#define REG_VIP_LCE_58_L (REG_VIP_LCE_BASE + 0xB0) ++#define REG_VIP_LCE_58_H (REG_VIP_LCE_BASE + 0xB1) ++#define REG_VIP_LCE_59_L (REG_VIP_LCE_BASE + 0xB2) ++#define REG_VIP_LCE_59_H (REG_VIP_LCE_BASE + 0xB3) ++#define REG_VIP_LCE_5A_L (REG_VIP_LCE_BASE + 0xB4) ++#define REG_VIP_LCE_5A_H (REG_VIP_LCE_BASE + 0xB5) ++#define REG_VIP_LCE_5B_L (REG_VIP_LCE_BASE + 0xB6) ++#define REG_VIP_LCE_5B_H (REG_VIP_LCE_BASE + 0xB7) ++#define REG_VIP_LCE_5C_L (REG_VIP_LCE_BASE + 0xB8) ++#define REG_VIP_LCE_5C_H (REG_VIP_LCE_BASE + 0xB9) ++#define REG_VIP_LCE_5D_L (REG_VIP_LCE_BASE + 0xBA) ++#define REG_VIP_LCE_5D_H (REG_VIP_LCE_BASE + 0xBB) ++#define REG_VIP_LCE_5E_L (REG_VIP_LCE_BASE + 0xBC) ++#define REG_VIP_LCE_5E_H (REG_VIP_LCE_BASE + 0xBD) ++#define REG_VIP_LCE_5F_L (REG_VIP_LCE_BASE + 0xBE) ++#define REG_VIP_LCE_5F_H (REG_VIP_LCE_BASE + 0xBF) ++#define REG_VIP_LCE_60_L (REG_VIP_LCE_BASE + 0xC0) ++#define REG_VIP_LCE_60_H (REG_VIP_LCE_BASE + 0xC1) ++#define REG_VIP_LCE_61_L (REG_VIP_LCE_BASE + 0xC2) ++#define REG_VIP_LCE_61_H (REG_VIP_LCE_BASE + 0xC3) ++#define REG_VIP_LCE_62_L (REG_VIP_LCE_BASE + 0xC4) ++#define REG_VIP_LCE_62_H (REG_VIP_LCE_BASE + 0xC5) ++#define REG_VIP_LCE_63_L (REG_VIP_LCE_BASE + 0xC6) ++#define REG_VIP_LCE_63_H (REG_VIP_LCE_BASE + 0xC7) ++#define REG_VIP_LCE_64_L (REG_VIP_LCE_BASE + 0xC8) ++#define REG_VIP_LCE_64_H (REG_VIP_LCE_BASE + 0xC9) ++#define REG_VIP_LCE_65_L (REG_VIP_LCE_BASE + 0xCA) ++#define REG_VIP_LCE_65_H (REG_VIP_LCE_BASE + 0xCB) ++#define REG_VIP_LCE_66_L (REG_VIP_LCE_BASE + 0xCC) ++#define REG_VIP_LCE_66_H (REG_VIP_LCE_BASE + 0xCD) ++#define REG_VIP_LCE_67_L (REG_VIP_LCE_BASE + 0xCE) ++#define REG_VIP_LCE_67_H (REG_VIP_LCE_BASE + 0xCF) ++#define REG_VIP_LCE_68_L (REG_VIP_LCE_BASE + 0xD0) ++#define REG_VIP_LCE_68_H (REG_VIP_LCE_BASE + 0xD1) ++#define REG_VIP_LCE_69_L (REG_VIP_LCE_BASE + 0xD2) ++#define REG_VIP_LCE_69_H (REG_VIP_LCE_BASE + 0xD3) ++#define REG_VIP_LCE_6A_L (REG_VIP_LCE_BASE + 0xD4) ++#define REG_VIP_LCE_6A_H (REG_VIP_LCE_BASE + 0xD5) ++#define REG_VIP_LCE_6B_L (REG_VIP_LCE_BASE + 0xD6) ++#define REG_VIP_LCE_6B_H (REG_VIP_LCE_BASE + 0xD7) ++#define REG_VIP_LCE_6C_L (REG_VIP_LCE_BASE + 0xD8) ++#define REG_VIP_LCE_6C_H (REG_VIP_LCE_BASE + 0xD9) ++#define REG_VIP_LCE_6D_L (REG_VIP_LCE_BASE + 0xDA) ++#define REG_VIP_LCE_6D_H (REG_VIP_LCE_BASE + 0xDB) ++#define REG_VIP_LCE_6E_L (REG_VIP_LCE_BASE + 0xDC) ++#define REG_VIP_LCE_6E_H (REG_VIP_LCE_BASE + 0xDD) ++#define REG_VIP_LCE_6F_L (REG_VIP_LCE_BASE + 0xDE) ++#define REG_VIP_LCE_6F_H (REG_VIP_LCE_BASE + 0xDF) ++#define REG_VIP_LCE_70_L (REG_VIP_LCE_BASE + 0xE0) ++#define REG_VIP_LCE_70_H (REG_VIP_LCE_BASE + 0xE1) ++#define REG_VIP_LCE_71_L (REG_VIP_LCE_BASE + 0xE2) ++#define REG_VIP_LCE_71_H (REG_VIP_LCE_BASE + 0xE3) ++#define REG_VIP_LCE_72_L (REG_VIP_LCE_BASE + 0xE4) ++#define REG_VIP_LCE_72_H (REG_VIP_LCE_BASE + 0xE5) ++#define REG_VIP_LCE_73_L (REG_VIP_LCE_BASE + 0xE6) ++#define REG_VIP_LCE_73_H (REG_VIP_LCE_BASE + 0xE7) ++#define REG_VIP_LCE_74_L (REG_VIP_LCE_BASE + 0xE8) ++#define REG_VIP_LCE_74_H (REG_VIP_LCE_BASE + 0xE9) ++#define REG_VIP_LCE_75_L (REG_VIP_LCE_BASE + 0xEA) ++#define REG_VIP_LCE_75_H (REG_VIP_LCE_BASE + 0xEB) ++#define REG_VIP_LCE_76_L (REG_VIP_LCE_BASE + 0xEC) ++#define REG_VIP_LCE_76_H (REG_VIP_LCE_BASE + 0xED) ++#define REG_VIP_LCE_77_L (REG_VIP_LCE_BASE + 0xEE) ++#define REG_VIP_LCE_77_H (REG_VIP_LCE_BASE + 0xEF) ++#define REG_VIP_LCE_78_L (REG_VIP_LCE_BASE + 0xF0) ++#define REG_VIP_LCE_78_H (REG_VIP_LCE_BASE + 0xF1) ++#define REG_VIP_LCE_79_L (REG_VIP_LCE_BASE + 0xF2) ++#define REG_VIP_LCE_79_H (REG_VIP_LCE_BASE + 0xF3) ++#define REG_VIP_LCE_7A_L (REG_VIP_LCE_BASE + 0xF4) ++#define REG_VIP_LCE_7A_H (REG_VIP_LCE_BASE + 0xF5) ++#define REG_VIP_LCE_7B_L (REG_VIP_LCE_BASE + 0xF6) ++#define REG_VIP_LCE_7B_H (REG_VIP_LCE_BASE + 0xF7) ++#define REG_VIP_LCE_7C_L (REG_VIP_LCE_BASE + 0xF8) ++#define REG_VIP_LCE_7C_H (REG_VIP_LCE_BASE + 0xF9) ++#define REG_VIP_LCE_7D_L (REG_VIP_LCE_BASE + 0xFA) ++#define REG_VIP_LCE_7D_H (REG_VIP_LCE_BASE + 0xFB) ++#define REG_VIP_LCE_7E_L (REG_VIP_LCE_BASE + 0xFC) ++#define REG_VIP_LCE_7E_H (REG_VIP_LCE_BASE + 0xFD) ++#define REG_VIP_LCE_7F_L (REG_VIP_LCE_BASE + 0xFE) ++#define REG_VIP_LCE_7F_H (REG_VIP_LCE_BASE + 0xFF) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/halpnl.c b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/halpnl.c +new file mode 100644 +index 00000000..4e7659f3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/halpnl.c +@@ -0,0 +1,355 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_PNL_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++// Internal Definition ++#include "hwreg.h" ++#include "halpnl_utility.h" ++#include "halpnl.h" ++#include "Infinity_pnl_lpll_tbl.h" ++#include "MsDbg.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DCLK_5MHZ 5000000 ++#define DCLK_10MHZ 10000000 ++#define DCLK_20MHZ 20000000 ++#define DCLK_40MHZ 40000000 ++#define DCLK_80MHZ 80000000 ++#define Is_Package_BGA() (Chip_Get_Package_Type()==MS_PACKAGE_BGA) ++#define Is_Package_QFP() (Chip_Get_Package_Type()==MS_PACKAGE_QFP) ++#define Is_Dclk_Less5M(Dclk) ((Dclk) <= DCLK_5MHZ) ++#define Is_Dclk_5MTo10M(Dclk) ((Dclk > DCLK_5MHZ) && (Dclk <= DCLK_10MHZ)) ++#define Is_Dclk_10MTo20M(Dclk) ((Dclk > DCLK_10MHZ) && (Dclk <= DCLK_20MHZ)) ++#define Is_Dclk_20MTo40M(Dclk) ((Dclk > DCLK_20MHZ) && (Dclk <= DCLK_40MHZ)) ++#define Is_Dclk_40MTo80M(Dclk) ((Dclk > DCLK_40MHZ) && (Dclk <= DCLK_80MHZ)) ++//------------------------------------------------------------------------------------------------- ++// Variable ++ ++MS_U32 PNL_RIU_BASE = 0; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_PNL_Set_Riu_Base(MS_U32 u32Riubase) ++{ ++ PNL_RIU_BASE = u32Riubase; ++} ++ ++void Hal_PNL_Set_Chiptop(void) ++{ ++ MS_U16 u16chip_top; ++ u16chip_top=R2BYTE(REG_CHIPTOP_0F_L); ++ if(Is_Package_BGA()) ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,(u16chip_top|0x0040),0x0040); ++ //W2BYTE(0x101eA0,0x0000); ++ } ++ else if(Is_Package_QFP()) ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,(u16chip_top|0x0000),0x0040); ++ printf("[PNL]QFP!!! OPEN PNL ERROR "); ++ } ++} ++ ++void Hal_PNL_Set_Init_Y2R(void) ++{ ++ MS_U16 u16Coef[9]={0xcc4,0x950,0x3ffc,0x397e,0x0950,0x3cde,0x3ffe,0x950,0x1024};//hw setting ++ Hal_PNL_Set_CSC_Y2R_En(1); ++ Hal_PNL_Set_CSC_Y2R_Offset(0x10,0x80,0x80); ++ Hal_PNL_Set_CSC_Y2R_Coef(u16Coef); ++} ++void Hal_PNL_Set_VSync_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_01_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_VSync_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_02_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vfde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_03_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vfde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_04_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_05_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_06_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vtt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_07_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_HSync_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_09_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_HSync_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0A_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hfde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0B_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hfde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0C_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0D_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0E_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Htt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0F_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_FrameColr_En(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL2_10_L, bEn ? BIT8 : 0, BIT8); ++} ++ ++#if ENABLE_PNL_UNUSED_FUNCTION ++void Hal_PNL_Set_FrameColor(MS_U32 u32Color) ++{ ++ W4BYTE(REG_SCL2_11_L, u32Color); ++} ++#endif ++ ++MS_U16 Hal_PNL_Get_Lpll_Idx(MS_U64 u64Dclk) ++{ ++ MS_U16 u16Idx = 0; ++ ++ if(Is_Dclk_Less5M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ; ++ } ++ else if(Is_Dclk_5MTo10M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ; ++ } ++ else if(Is_Dclk_10MTo20M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ; ++ } ++ else if(Is_Dclk_20MTo40M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ; ++ } ++ else if(Is_Dclk_40MTo80M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ; ++ } ++ else ++ { ++ u16Idx = 0xFF; ++ } ++ return u16Idx; ++} ++ ++MS_U16 Hal_PNL_Get_Lpll_Gain(MS_U16 u16Idx) ++{ ++ return u16LoopGain[u16Idx]; ++} ++ ++MS_U16 Hal_PNL_Get_Lpll_Div(MS_U16 u16Idx) ++{ ++ return u16LoopDiv[u16Idx]; ++} ++ ++void Hal_PNL_Dump_Lpll_Setting(MS_U16 u16Idx) ++{ ++ MS_U16 u16RegIdx; ++ ++ for(u16RegIdx=0; u16RegIdx < LPLL_REG_NUM; u16RegIdx++) ++ { ++ ++ if(LPLLSettingTBL[u16Idx][u16RegIdx].address == 0xFF) ++ { ++ MsOS_DelayTask(LPLLSettingTBL[u16Idx][u16RegIdx].value); ++ continue; ++ } ++ ++ W2BYTEMSK((REG_SCL_LPLL_BASE | ((MS_U32)LPLLSettingTBL[u16Idx][u16RegIdx].address *2)), ++ LPLLSettingTBL[u16Idx][u16RegIdx].value, ++ LPLLSettingTBL[u16Idx][u16RegIdx].mask); ++ } ++ ++} ++ ++void Hal_PNL_Set_Lpll_Set(MS_U32 u32LpllSet) ++{ ++ MS_U16 u16LpllSet_Lo, u16LpllSet_Hi; ++ u16LpllSet_Lo = (MS_U16)(u32LpllSet & 0x0000FFFF); ++ u16LpllSet_Hi = (MS_U16)((u32LpllSet & 0x00FF0000) >> 16); ++ W2BYTE(REG_SCL_LPLL_48_L, u16LpllSet_Lo); ++ W2BYTE(REG_SCL_LPLL_49_L, u16LpllSet_Hi); ++} ++ ++void Hal_PNL_Set_OpenLpll_CLK(MS_U8 bLpllClk) ++{ ++ MS_U16 u16byte; ++ W2BYTEMSK(REG_SCL_CLK_66_L, bLpllClk ? 0x000C : 0x1, 0x000F); ++ u16byte=R2BYTE(REG_CHIPTOP_0F_L); ++ W2BYTEMSK(REG_CHIPTOP_0F_L, bLpllClk ? (0x0041|u16byte) : u16byte, 0x0041); ++} ++// CSC Y2R ++void Hal_PNL_Set_CSC_Y2R_En(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL2_19_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++void Hal_PNL_Set_CSC_Y2R_Offset(MS_U8 u8Y, MS_U8 u8Cb, MS_U8 u8Cr) ++{ ++ W2BYTEMSK(REG_SCL2_19_L, ((MS_U16)u8Y << 8), 0xFF00); ++ W2BYTEMSK(REG_SCL2_1A_L, (((MS_U16)u8Cb << 8)|((MS_U16)u8Cr)), 0xFFFF); ++} ++ ++void Hal_PNL_Set_CSC_Y2R_Coef(MS_U16 *pu16Coef) ++{ ++ ++ MS_U8 u8idx; ++ ++ for(u8idx=0; u8idx<9; u8idx++) ++ { ++ W2BYTEMSK(REG_SCL2_1B_L + (u8idx<<1), pu16Coef[u8idx], 0x3FFF); ++ } ++} ++ ++ ++#undef HAL_PNL_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/Infinity_pnl_lpll_tbl.h b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/Infinity_pnl_lpll_tbl.h +new file mode 100644 +index 00000000..4ccefde2 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/Infinity_pnl_lpll_tbl.h +@@ -0,0 +1,227 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef _LPLL_TBL_H_ ++#define _LPLL_TBL_H_ ++ ++#define LPLL_REG_NUM 17 ++ ++typedef enum ++{ ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ, //0 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ, //1 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ, //2 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ, //3 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ, //4 ++ ++ E_PNL_SUPPORTED_LPLL_MAX, //5 ++} E_PNL_SUPPORTED_LPLL_TYPE; ++ ++typedef struct ++{ ++ MS_U8 address; ++ MS_U16 value; ++ MS_U16 mask; ++}TBLStruct,*pTBLStruct; ++ ++TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= ++{ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ NO.0 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0050,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ NO.1 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0050,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ NO.2 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x00A0,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ NO.3 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0080,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ NO.4 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0080,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++}; ++MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= ++{ ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ NO.0 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ NO.1 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ NO.2 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ NO.3 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ NO.4 ++}; ++MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= ++{ ++ 20, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ NO.0 ++ 40, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ NO.1 ++ 80, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ NO.2 ++ 160, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ NO.3 ++ 160, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ NO.4 ++}; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/halpnl.h b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/halpnl.h +new file mode 100644 +index 00000000..4187dc1a +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/halpnl.h +@@ -0,0 +1,148 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_PNL_H ++#define _HAL_PNL_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_PNL_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_PNL_Set_Riu_Base(MS_U32 u32Riubase); ++INTERFACE void Hal_PNL_Set_Chiptop(void); ++INTERFACE void Hal_PNL_Set_Init_Y2R(void); ++INTERFACE void Hal_PNL_Set_VSync_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_VSync_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vfde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vfde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vtt(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_HSync_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_HSync_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hfde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hfde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Htt(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_FrameColr_En(MS_BOOL bEn); ++INTERFACE void Hal_PNL_Set_FrameColor(MS_U32 u32Color); ++INTERFACE void Hal_PNL_Dump_Lpll_Setting(MS_U16 u16Idx); ++INTERFACE void Hal_PNL_Set_Lpll_Set(MS_U32 u32LpllSet); ++INTERFACE MS_U16 Hal_PNL_Get_Lpll_Idx(MS_U64 u64Dclk); ++INTERFACE MS_U16 Hal_PNL_Get_Lpll_Gain(MS_U16 u16Idx); ++INTERFACE MS_U16 Hal_PNL_Get_Lpll_Div(MS_U16 u16Idx); ++INTERFACE void Hal_PNL_Set_CSC_Y2R_En(MS_BOOL bEn); ++INTERFACE void Hal_PNL_Set_CSC_Y2R_Offset(MS_U8 u8Y, MS_U8 u8Cb, MS_U8 u8Cr); ++INTERFACE void Hal_PNL_Set_CSC_Y2R_Coef(MS_U16 *pu16Coef); ++INTERFACE void Hal_PNL_Set_OpenLpll_CLK(MS_U8 bLpllClk); ++ ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/halpnl_utility.h b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/halpnl_utility.h +new file mode 100644 +index 00000000..294b8cd4 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/halpnl_utility.h +@@ -0,0 +1,53 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALPNL_UTILITY_H_ ++#define _HALPNL_UTILITY_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 PNL_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( PNL_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( PNL_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (PNL_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( PNL_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/infinity_lpll_setting.xlsm b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/infinity_lpll_setting.xlsm +new file mode 100644 +index 00000000..d1835f45 +Binary files /dev/null and b/drivers/mstar/scl/infinity/src/mxlib/hal/pnl/include/infinity_lpll_setting.xlsm differ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/halscldma.c b/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/halscldma.c +new file mode 100644 +index 00000000..8a299576 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/halscldma.c +@@ -0,0 +1,1615 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_SCLDMA_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#endif ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg.h" ++#include "halscldma_utility.h" ++#include "drvscldma_st.h" ++#include "halscldma.h" ++#include ++#include ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define HAL_SCLDMA_ERR(x) x ++#define DISABLE_CLK 0x1 ++#define LOW_CLK 0x4 ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_U32 SCLDMA_RIU_BASE = 0; ++MS_U16 u16gheight[2] = {1080,720}; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_SCLDMA_SetRiuBase(MS_U32 u32riubase) ++{ ++ SCLDMA_RIU_BASE = u32riubase; ++} ++void Hal_SCLDMA_Set_SW_Reset(void) ++{ ++ W2BYTEMSK(REG_SCL0_01_L,BIT0,BIT0); ++ W2BYTEMSK(REG_SCL0_01_L,0,BIT0); ++} ++void Hal_SCLDMA_SetReqLen(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_19_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_49_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_49_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_61_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_79_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_31_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_19_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_31_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_SetReqTh(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_19_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_49_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_49_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_61_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_79_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_31_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_19_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_31_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_SetPriThd(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_18_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_48_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_48_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_60_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_78_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_30_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_18_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_30_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_HKForceAuto(void) ++{ ++ // sc22sc2_hk_force_auto, sc2out_hk_force_auto ++ W2BYTEMSK(REG_SCL0_03_L, BIT11|BIT10|BIT9|BIT8|BIT1|BIT0, BIT11|BIT10|BIT9|BIT8|BIT1|BIT0); ++} ++void Hal_SCLDMA_HWInit(void) ++{ ++ Hal_SCLDMA_HKForceAuto(); ++ Hal_SCLDMA_SetMCMByDMAClient(E_SCLDMA_1_SNP_W,0); ++ Hal_SCLDMA_SetPriThd(E_SCLDMA_3_FRM_R,0x08); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_3_FRM_R,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_3_FRM_R,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_3_FRM_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_3_FRM_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_1_FRM_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_1_FRM_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_1_SNP_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_1_SNP_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_2_FRM_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_2_FRM_W,0x12); ++ Hal_SCLDMA_Set_SW_Reset(); ++ ++} ++#if CONFIG_OF ++void Hal_SCLDMA_CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* stclock = NULL; ++ MS_U16 regclk; ++ if(bEn) ++ { ++ if (__clk_get_enable_count(stclk->fclk1) == 0) ++ { ++ if(u16gheight[0] > 720) ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ clk_set_parent(stclk->fclk1, stclock); ++ clk_prepare_enable(stclk->fclk1); ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ //printf("[SCLDMA]flag:%ld index:%hx\n",__clk_get_rate(stclk->fclk1),regclk); ++ } ++ } ++ else ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk1, 1))) ++ { ++ clk_set_parent(stclk->fclk1, stclock); ++ clk_prepare_enable(stclk->fclk1); ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ //printf("[SCLDMA]flag:%ld index:%hx\n",__clk_get_rate(stclk->fclk1),regclk); ++ } ++ } ++ } ++ else ++ { ++ if(u16gheight[0] > 720 && __clk_get_rate(stclk->fclk1) < 172000000) ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ clk_set_parent(stclk->fclk1, stclock); ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ //printf("[SCLDMA]flag:%ld index:%hx\n",__clk_get_rate(stclk->fclk1),regclk); ++ } ++ } ++ else if(u16gheight[0] <= 720 && __clk_get_rate(stclk->fclk1) >= 172000000) ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk1, 1))) ++ { ++ clk_set_parent(stclk->fclk1, stclock); ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ //printf("[SCLDMA]flag:%ld index:%hx\n",__clk_get_rate(stclk->fclk1),regclk); ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ clk_set_parent(stclk->fclk1, stclock); ++ } ++ while (__clk_get_enable_count(stclk->fclk1)) ++ { ++ clk_disable_unprepare(stclk->fclk1); ++ } ++ } ++} ++ ++void Hal_SCLDMA_SC3CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* stclock = NULL; ++ if(bEn) ++ { ++ if (__clk_get_enable_count(stclk->fclk2) == 0) ++ { ++ if(u16gheight[1] > 720) ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ clk_set_parent(stclk->fclk2, stclock); ++ clk_prepare_enable(stclk->fclk2); ++ } ++ } ++ else ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ clk_set_parent(stclk->fclk2, stclock); ++ clk_prepare_enable(stclk->fclk2); ++ } ++ ++ } ++ } ++ else ++ { ++ if(u16gheight[1] > 720 && __clk_get_rate(stclk->fclk2) < 172000000) ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ clk_set_parent(stclk->fclk2, stclock); ++ } ++ } ++ else if(u16gheight[1] <= 720 && __clk_get_rate(stclk->fclk2) >= 172000000) ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ clk_set_parent(stclk->fclk2, stclock); ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ if (NULL != (stclock = clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ clk_set_parent(stclk->fclk2, stclock); ++ } ++ while (__clk_get_enable_count(stclk->fclk2)) ++ { ++ clk_disable_unprepare(stclk->fclk2); ++ } ++ } ++} ++void Hal_SCLDMA_ODCLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* pstclock = NULL; ++ if(bEn) ++ { ++ if(__clk_get_enable_count(stclk->odclk)==0) ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->odclk, 3))) ++ { ++ clk_set_parent(stclk->odclk, pstclock); ++ clk_prepare_enable(stclk->odclk); ++ } ++ else ++ { ++ printf("[odclk]NULL\n"); ++ ++ } ++ } ++ else ++ { ++ printf("[odclk]CAN'T/Already OPEN\n"); ++ } ++ ++ } ++ else ++ { ++ if (NULL != (pstclock = clk_get_parent_by_index(stclk->odclk, 0))) ++ { ++ clk_set_parent(stclk->odclk, pstclock); ++ } ++ while (__clk_get_enable_count(stclk->odclk)) ++ { ++ clk_disable_unprepare(stclk->odclk); ++ } ++ } ++} ++ ++#else ++void Hal_SCLDMA_CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ MS_U16 regclk; ++ printf("[hal]NO OF\n"); ++ if(bEn) ++ { ++ if ((R2BYTE(REG_SCL_CLK_64_L)&DISABLE_CLK)) ++ { ++ if(u16gheight[0] > 720) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ } ++ else ++ { ++ if(u16gheight[0] > 720 && (R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ else if(u16gheight[0] <= 720 && !(R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ } ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0,0x000F);//h61 ++ } ++} ++ ++void Hal_SCLDMA_SC3CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ MS_U16 regclk; ++ if(bEn) ++ { ++ if ((R2BYTE(REG_SCL_CLK_65_L)&DISABLE_CLK)) ++ { ++ if(u16gheight[1] > 720) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ } ++ else ++ { ++ if(u16gheight[1] > 720 && (R2BYTE(REG_SCL_CLK_65_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ else if(u16gheight[1] <= 720 && !(R2BYTE(REG_SCL_CLK_65_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ } ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0,0x000F);//h61 ++ } ++} ++void Hal_SCLDMA_ODCLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* pstclock = NULL; ++ if(bEn) ++ { ++ if((R2BYTE(REG_SCL_CLK_66_L)&DISABLE_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_66_L,0x000C,0x000F);//h66 ++ } ++ else ++ { ++ printf("[odclk]CAN'T/Already OPEN\n"); ++ } ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_66_L,0x000D,0x000F);//h66 ++ } ++} ++ ++#endif ++ ++void Hal_SCLDMA_SetSC2HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT0, BIT0); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT1, BIT1); ++ } ++} ++ ++void Hal_SCLDMA_SetSC1HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT9, BIT9); ++ } ++ else if(enRWMode == E_SCLDMA_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT10, BIT10); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT11, BIT11); ++ } ++ ++ //HAL_SCLDMA_ERR(printf("[HalSCLDMA]HK_Force:%hx\n", R2BYTE(REG_SCL0_02_L))); ++} ++ ++void Hal_SCLDMA_SetSC1ToSC2HandshakeForce(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT8, BIT8); ++} ++void Hal_SCLDMA_SetMCMByDMAClient(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_MCM_06_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_MCM_07_L, u8value, 0xFF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_MCM_10_L, u8value, 0xFF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_MCM_08_L, u8value, 0xFF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_MCM_10_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_MCM_08_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_MCM_07_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_SetCheckFrmEndSignal(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_BOOL bEn) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT11 : 0, BIT11); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT12 : 0, BIT12); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT13 : 0, BIT13); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT10 : 0, BIT10); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT9 : 0, BIT9); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT8 : 0, BIT8); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++ ++void Hal_SCLDMA_SetSC1DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_01_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_03_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_03_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ //HAL_SCLDMA_ERR(printf("[HalSCLDMA]DMA1_En:%hx\n", R2BYTE(REG_SCL_DMA0_01_L))); ++ ++} ++void Hal_SCLDMA_GetHVSPResolutionForEnsure(MS_U16 u16height) ++{ ++ MS_U16 u16Srcheight,u16Dspheight,u16FBheight; ++ u16Srcheight = R2BYTE(REG_SCL_HVSP0_21_L); ++ u16Dspheight = R2BYTE(REG_SCL_HVSP0_23_L); ++ u16FBheight = R2BYTE(REG_SCL_DNR1_0D_L); ++ if(u16Srcheight>0) ++ { ++ u16gheight[0] = (u16Srcheight>u16Dspheight) ? u16Srcheight : u16Dspheight ; ++ u16gheight[0] = (u16FBheight>u16gheight[0])? u16FBheight:u16gheight[0]; ++ } ++ u16Srcheight = R2BYTE(REG_SCL_HVSP2_21_L); ++ u16Dspheight = R2BYTE(REG_SCL_HVSP2_23_L); ++ if(u16Srcheight>0) ++ { ++ u16gheight[1] = (u16Srcheight>u16Dspheight) ? u16Srcheight : u16Dspheight ; ++ } ++ ++} ++MS_U16 Hal_GetHVSPOutputHSize(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U16 u16Width; ++ u16Width = (enSCLDMA_ID == E_SCLDMA_ID_1_W) ?R2BYTE(REG_SCL_HVSP0_22_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_2_W) ?R2BYTE(REG_SCL_HVSP1_22_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_W) ?R2BYTE(REG_SCL_HVSP2_22_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_R) ?R2BYTE(REG_SCL_HVSP2_20_L) : ++ 0; ++ return u16Width; ++} ++MS_U16 Hal_GetHVSPOutputVSize(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U16 u16Height; ++ u16Height = (enSCLDMA_ID == E_SCLDMA_ID_1_W) ? R2BYTE(REG_SCL_HVSP0_23_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_2_W) ? R2BYTE(REG_SCL_HVSP1_23_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_W) ? R2BYTE(REG_SCL_HVSP2_23_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_R) ? R2BYTE(REG_SCL_HVSP2_21_L) : ++ 0; ++ return u16Height; ++} ++void Hal_SCLDMA_SetSC1DMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ if(stSCLDMACfg.enRWMode == E_SCLDMA_FRM_W) ++ { ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_08_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_10_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_0A_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_12_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_0C_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_14_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_0E_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_16_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA0_18_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ Hal_SCLDMA_GetHVSPResolutionForEnsure(stSCLDMACfg.u16Height); ++ W2BYTEMSK(REG_SCL_DMA0_1E_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : 0, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA0_1E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA0_01_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg.enRWMode == E_SCLDMA_SNP_W) ++ { ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_38_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_40_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_3A_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_42_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_3C_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_44_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_3E_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_46_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA0_48_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA0_4E_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : 0, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA0_4E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA0_03_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg.enRWMode == E_SCLDMA_IMI_W) ++ { ++#if ENABLE_RING_DB ++ u32yoffset = 0x20; ++ u32coffset = 0x20; ++#else ++ if(stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420) ++ { ++ u32yoffset=(stSCLDMACfg.u16Width*16)/8-1; ++ u32coffset=(stSCLDMACfg.u16Width*8)/8-1; ++ } ++ else if(stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422) ++ { ++ u32yoffset=(stSCLDMACfg.u16Width*16)/8-2; ++ u32coffset=(stSCLDMACfg.u16Width*16)/8-2; ++ } ++#endif ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_38_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_3A_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_42_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_3C_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_44_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_3E_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_46_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA1_48_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : 0, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_03_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ W4BYTE(REG_SCL_DMA2_40_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_42_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL0_64_L,0, BIT15); // sc1 open ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg.enRWMode)); ++ } ++ if(Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W)==stSCLDMACfg.u16Width ||(Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W) == 0)) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_1A_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4A_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_4A_L, stSCLDMACfg.u16Width, 0xFFFF); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_1A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W), 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W), 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_4A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W), 0xFFFF); ++ } ++ if(Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W) == stSCLDMACfg.u16Height ||(Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W) == 0)) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_1B_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4B_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_4B_L, stSCLDMACfg.u16Height,0xFFFF); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_1A_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W), 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4A_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W), 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_4A_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W), 0xFFFF); ++ } ++ ++} ++void Hal_SCLDMA_SetIMIClientReset(void) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ u32yoffset = 0x0; ++ u32coffset = 0x0; ++ W4BYTE(REG_SCL_DMA1_38_L, 0); ++ W4BYTE(REG_SCL_DMA1_40_L, 0); ++ W4BYTE(REG_SCL_DMA1_3A_L, 0); ++ W4BYTE(REG_SCL_DMA1_42_L, 0); ++ W4BYTE(REG_SCL_DMA1_3C_L, 0); ++ W4BYTE(REG_SCL_DMA1_44_L, 0); ++ W4BYTE(REG_SCL_DMA1_3E_L, 0); ++ W4BYTE(REG_SCL_DMA1_46_L, 0); ++ ++ W2BYTEMSK(REG_SCL_DMA1_48_L, 0, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_4A_L, 0, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4B_L, 0, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, 0, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, 0, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_03_L, 0, BIT14); // w_422_pack[14] ++ W4BYTE(REG_SCL_DMA2_40_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_42_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL0_64_L,0, BIT15); // sc1 open ++ ++} ++void Hal_SCLDMA_SetDMAOutputBufferAddr ++ (EN_SCLDMA_CLIENT_TYPE enClientType,unsigned long u32YBufferAddr,unsigned long u32CBufferAddr) ++{ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ W4BYTE(REG_SCL_DMA0_08_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_10_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ W4BYTE(REG_SCL_DMA1_38_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ W4BYTE(REG_SCL_DMA0_38_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_40_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ W4BYTE(REG_SCL_DMA0_50_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_58_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ W4BYTE(REG_SCL_DMA1_38_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ W4BYTE(REG_SCL_DMA1_20_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_28_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ W4BYTE(REG_SCL_DMA1_08_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_10_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ W4BYTE(REG_SCL_DMA0_20_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_28_L, u32CBufferAddr>>3); ++ break; ++ default: ++ break; ++ } ++ ++} ++ ++void Hal_SCLDMA_SetSC2DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_04_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_03_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ ++} ++ ++void Hal_SCLDMA_SetSC2DMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ if(stSCLDMACfg.enRWMode == E_SCLDMA_FRM_W) ++ { ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_50_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_58_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_52_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_5A_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_54_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_5C_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_56_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_5E_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA0_60_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA0_62_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_63_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_66_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA0_66_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : 0, BIT3); ++ W2BYTEMSK(REG_SCL_DMA0_04_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ } ++ else if(stSCLDMACfg.enRWMode == E_SCLDMA_IMI_W) ++ { ++ ++ if(stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420) ++ { ++ u32yoffset=(stSCLDMACfg.u16Width*16)/8-1; ++ u32coffset=(stSCLDMACfg.u16Width*8)/8-1; ++ } ++ else if(stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422) ++ { ++ u32yoffset=(stSCLDMACfg.u16Width*16)/8-2; ++ u32coffset=(stSCLDMACfg.u16Width*16)/8-2; ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_38_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_3A_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_42_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_3C_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_44_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_3E_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_46_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA1_48_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_4A_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4B_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : 0, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_03_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ W4BYTE(REG_SCL_DMA2_40_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_42_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL0_64_L,BIT15, BIT15); //sc2 open ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg.enRWMode)); ++ } ++ ++} ++ ++ ++void Hal_SCLDMA_SetSC3DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_02_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_01_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ ++} ++ ++void Hal_SCLDMA_SetSC3DMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ if(stSCLDMACfg.enRWMode == E_SCLDMA_FRM_R) ++ { ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_20_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_28_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_22_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_2A_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_24_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_2C_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_26_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_2E_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA1_30_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_32_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_33_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_36_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT7 : 0, BIT7); ++ W2BYTEMSK(REG_SCL_DMA1_36_L, 0x06, 0x0F); //422to444_md[1:0], 420to422_md[2], 420to422_md_avg[3] ++ W2BYTEMSK(REG_SCL_DMA1_02_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ } ++ else if(stSCLDMACfg.enRWMode == E_SCLDMA_FRM_W) ++ { ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_08_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_10_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_0A_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_12_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_0C_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_14_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_0E_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_16_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA1_18_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_1A_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_1B_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_1E_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : 0, BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_1E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_01_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ Hal_SCLDMA_GetHVSPResolutionForEnsure(stSCLDMACfg.u16Height); ++ ++ } ++ else if(stSCLDMACfg.enRWMode == E_SCLDMA_IMI_R) ++ { ++ if(stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV420) ++ { ++ u32yoffset=(stSCLDMACfg.u16Width*16)/8-1; ++ u32coffset=(stSCLDMACfg.u16Width*8)/8-1; ++ } ++ else if(stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422) ++ { ++ u32yoffset=(stSCLDMACfg.u16Width*16)/8-2; ++ u32coffset=(stSCLDMACfg.u16Width*16)/8-2; ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_20_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_28_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_22_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_2A_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_24_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_2C_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_26_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_2E_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA1_30_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_32_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA1_33_L, stSCLDMACfg.u16Height,0xFFFF); ++ ++ W2BYTEMSK(REG_SCL_DMA1_36_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT7 : 0, BIT7); ++ W2BYTEMSK(REG_SCL_DMA1_36_L, 0x06, 0x0F); //422to444_md[1:0], 420to422_md[2], 420to422_md_avg[3] ++ W4BYTE(REG_SCL_DMA2_48_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_4A_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL_DMA2_02_L, 0x01,0x01); // SC3 mode ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg.enRWMode)); ++ } ++ ++} ++ ++void Hal_SCLDMA_SetDisplayDMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_DBG_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_02_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ ++} ++ ++ ++void Hal_SCLDMA_SetDisplayDMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg) ++{ ++ ++ if(stSCLDMACfg.enRWMode == E_SCLDMA_DBG_R) ++ { ++ if(stSCLDMACfg.bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_20_L, stSCLDMACfg.u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_28_L, stSCLDMACfg.u32Base_C[0]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_22_L, stSCLDMACfg.u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_2A_L, stSCLDMACfg.u32Base_C[1]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_24_L, stSCLDMACfg.u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_2C_L, stSCLDMACfg.u32Base_C[2]>>3); ++ } ++ if(stSCLDMACfg.bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_26_L, stSCLDMACfg.u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_2E_L, stSCLDMACfg.u32Base_C[3]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA0_30_L, stSCLDMACfg.u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTEMSK(REG_SCL_DMA0_32_L, stSCLDMACfg.u16Width, 0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_33_L, stSCLDMACfg.u16Height,0xFFFF); ++ W2BYTEMSK(REG_SCL_DMA0_36_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT7 : 0, BIT7); ++ W2BYTEMSK(REG_SCL_DMA0_36_L, 0x06, 0x0F); //422to444_md[1:0], 420to422_md[2], 420to422_md_avg[3] ++ W2BYTEMSK(REG_SCL_DMA0_02_L, stSCLDMACfg.enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg.enRWMode)); ++ } ++} ++ ++ ++//SCLDMA Trig ++void Hal_SCLDMA_SetVSyncRegenMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigMd) ++{ ++ MS_U16 u16val, u16Mask; ++ MS_U32 u32Reg; ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0001 : ++ 0x0002; ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_26_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0100 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0200 : ++ 0x0300; ++ ++ u16Mask = BIT9|BIT8; ++ u32Reg = REG_SCL0_26_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0001 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0002 : ++ 0x0003 ; ++ ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_20_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0001 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0002 : ++ 0x0003 ; ++ ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_22_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0001 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0002 : ++ 0x0003 ; ++ ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_24_L; ++ } ++ else ++ { ++ return; ++ } ++ ++ ++ W2BYTEMSK(u32Reg, u16val, u16Mask); ++} ++ ++void Hal_SCLDMA_SetRegenVSyncVariableWidthEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_2D_L, bEn ? BIT7 : 0, BIT7); ++ ++} ++ ++void Hal_SCLDMA_SetRegenVSyncRefEdgeMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_REGEN_VS_REF_MODE_TYPE enRefMd) ++{ ++ MS_U8 u16val = enRefMd == E_SCLDMA_REF_VS_REF_MODE_RASING ? 1 : 0; ++ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val, BIT0); ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<1, BIT1); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<2, BIT2); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<3, BIT3); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<4, BIT4); ++ } ++ else ++ { ++ } ++} ++ ++void Hal_SCLDAM_SetRegenVSyncWidth(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_Width) ++{ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ W2BYTE(REG_SCL0_28_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTE(REG_SCL0_29_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTE(REG_SCL0_2A_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTE(REG_SCL0_2B_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTE(REG_SCL0_2C_L, u16Vs_Width); ++ } ++ else ++ { ++ } ++} ++ ++ ++void Hal_SCLDAM_SetRegenVSyncStartPoint(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_St) ++{ ++ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTE(REG_SCL0_27_L, u16Vs_St); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTE(REG_SCL0_21_L, u16Vs_St); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTE(REG_SCL0_23_L, u16Vs_St); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTE(REG_SCL0_25_L, u16Vs_St); ++ } ++ else ++ { ++ } ++} ++ ++void Hal_SCLDMA_TrigRegenVSync(EN_SCLDMA_VS_ID_TYPE enID, MS_BOOL bEn) ++{ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTEMSK(REG_SCL0_26_L, bEn ? BIT10: 0, BIT10); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTEMSK(REG_SCL0_20_L, bEn ? BIT2: 0, BIT2); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTEMSK(REG_SCL0_22_L, bEn ? BIT2: 0, BIT2); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTEMSK(REG_SCL0_24_L, bEn ? BIT2: 0, BIT2); ++ } ++ else ++ { ++ } ++} ++ ++void Hal_SCLDMA_SetDMAEnableDoubleBuffer(MS_BOOL bEn,EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ case E_SCLDMA_ID_2_W: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT4 : 0, BIT4); ++ break; ++ ++ case E_SCLDMA_ID_3_W: ++ case E_SCLDMA_ID_3_R: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT5 : 0, BIT5); ++ break; ++ ++ case E_SCLDMA_ID_PNL_R: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT6 : 0, BIT6); ++ break; ++ ++ default: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT7 : 0, BIT7); ++ break; ++ ++ } ++} ++void Hal_SCLDMA_SetHandshakeDoubleBuffer(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT0 : 0, BIT0); ++ ++} ++MS_U8 Hal_SCLDMA_GetISPFrameCountReg(void) ++{ ++ MS_U8 u8Value = (MS_U8)((R2BYTE(REG_ISP_7A_L)>>8)&0x7F); ++ //u8Value = (u8Value==0) ? 0x7F : (u8Value - 1); ++ return u8Value; ++} ++MS_U16 Hal_SCLDMA_GetDMAOutputCount(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16Idx,u16def; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_10_L); ++ u16def = R2BYTE(REG_SCL_DMA0_1B_L); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_11_L); ++ u16def = R2BYTE(REG_SCL_DMA1_4B_L); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_12_L); ++ u16def = R2BYTE(REG_SCL_DMA0_4B_L); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_13_L); ++ u16def = R2BYTE(REG_SCL_DMA0_63_L); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_14_L); ++ u16def = R2BYTE(REG_SCL_DMA0_7B_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16Idx = R2BYTE(REG_SCL_DMA2_16_L); ++ u16def = R2BYTE(REG_SCL_DMA1_33_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_15_L); ++ u16def = R2BYTE(REG_SCL_DMA1_1B_L); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16Idx = R2BYTE(REG_SCL_DMA2_17_L); ++ u16def = R2BYTE(REG_SCL_DMA0_33_L); ++ break; ++ default: ++ u16Idx = 0x0; ++ u16def = 0x0; ++ break; ++ } ++ return ((u16Idx)); ++ ++} ++MS_U16 Hal_SCLDMA_GetOutputHsize(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16Idx,u16def; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_1A_L); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA1_4A_L); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16def = R2BYTE(REG_SCL_DMA0_4A_L); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_62_L); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA0_7A_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA1_32_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA1_1A_L); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA0_32_L); ++ break; ++ default: ++ u16Idx = 0x0; ++ u16def = 0x0; ++ break; ++ } ++ return ((u16def)); ++ ++} ++MS_U16 Hal_SCLDMA_GetOutputVsize(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16Idx,u16def; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_1B_L); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA1_4B_L); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16def = R2BYTE(REG_SCL_DMA0_4B_L); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_63_L); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA0_7B_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA1_33_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA1_1B_L); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA0_33_L); ++ break; ++ default: ++ u16Idx = 0x0; ++ u16def = 0x0; ++ break; ++ } ++ return ((u16def)); ++ ++} ++MS_U16 Hal_SCLDMA_Get_RW_Idx(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U16 u16Idx; ++ switch(enClient) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16Idx = R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT1|BIT0)); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT3|BIT2)))>>2; ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT5|BIT4)))>>4; ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT7|BIT6)))>>6; ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT9|BIT8)))>>8; ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT11|BIT10)))>>10; ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT13|BIT12)))>>12; ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT15|BIT14)))>>14; ++ break; ++ default: ++ u16Idx = 0xFF; ++ break; ++ } ++ return u16Idx; ++} ++ ++#undef HAL_SCLDMA_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/include/halscldma.h b/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/include/halscldma.h +new file mode 100644 +index 00000000..b04200b3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/include/halscldma.h +@@ -0,0 +1,154 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. 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If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_SCLDMA_H ++#define _HAL_SCLDMA_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_SCLDMA_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_SCLDMA_HWInit(void); ++INTERFACE void Hal_SCLDMA_CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk); ++INTERFACE void Hal_SCLDMA_SC3CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk); ++void Hal_SCLDMA_ODCLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk); ++INTERFACE void Hal_SCLDMA_SetSC2HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC1HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC1ToSC2HandshakeForce(MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetCheckFrmEndSignal(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetMCMByDMAClient(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value); ++INTERFACE void Hal_SCLDMA_SetIMIClientReset(void); ++INTERFACE void Hal_SCLDMA_SetDMAOutputBufferAddr ++ (EN_SCLDMA_CLIENT_TYPE enClientType,unsigned long u32YBufferAddr,unsigned long u32CBufferAddr); ++INTERFACE void Hal_SCLDMA_SetRiuBase(MS_U32 u32riubase); ++INTERFACE void Hal_SCLDMA_SetSC1DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC1DMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetSC2DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC2DMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetSC3DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC3DMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetDisplayDMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetDisplayDMAConfig(ST_SCLDMA_RW_CONFIG stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetVSyncRegenMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigMd); ++INTERFACE void Hal_SCLDMA_SetRegenVSyncRefEdgeMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_REGEN_VS_REF_MODE_TYPE enRefMd); ++INTERFACE void Hal_SCLDAM_SetRegenVSyncWidth(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_Width); ++INTERFACE void Hal_SCLDAM_SetRegenVSyncStartPoint(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_St); ++INTERFACE void Hal_SCLDMA_TrigRegenVSync(EN_SCLDMA_VS_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetRegenVSyncVariableWidthEn(MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetDMAEnableDoubleBuffer(MS_BOOL bEn,EN_SCLDMA_ID_TYPE enSCLDMA_ID); ++INTERFACE MS_U16 Hal_SCLDMA_Get_RW_Idx(EN_SCLDMA_CLIENT_TYPE enClient); ++INTERFACE MS_U16 Hal_SCLDMA_GetDMAOutputCount(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE MS_U16 Hal_SCLDMA_GetOutputHsize(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE MS_U16 Hal_SCLDMA_GetOutputVsize(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE void Hal_SCLDMA_SetHandshakeDoubleBuffer(MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_Set_SW_Reset(void); ++INTERFACE MS_U8 Hal_SCLDMA_GetISPFrameCountReg(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/include/halscldma_utility.h b/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/include/halscldma_utility.h +new file mode 100644 +index 00000000..510c8966 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/scldma/include/halscldma_utility.h +@@ -0,0 +1,64 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCL_UTILITY_H_ ++#define _HALSCL_UTILITY_H_ ++ ++//!! Do not include this header in driver or api level ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 SCLDMA_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( SCLDMA_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( SCLDMA_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (SCLDMA_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( SCLDMA_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/halsclirq.c b/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/halsclirq.c +new file mode 100644 +index 00000000..e6312c03 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/halsclirq.c +@@ -0,0 +1,216 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_SCLIRQ_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg.h" ++#include "halsclirq_utility.h" ++#include "drvsclirq_st.h" ++#include "halsclirq.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++ ++MS_U32 SCLIRQ_RIU_BASE = 0; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_SCLIRQ_Set_Riu_Base(MS_U32 u32Riubase) ++{ ++ SCLIRQ_RIU_BASE = u32Riubase; ++} ++ ++ ++MS_U64 Hal_SCLIRQ_Get_Flag(MS_U64 u64IRQ) ++{ ++ MS_U32 u32Mask; ++ MS_U16 u16Mask; ++ MS_U64 u64Flag = 0; ++ ++ if(u64IRQ & 0x00000000FFFFFFFF) ++ { ++ u32Mask = (MS_U32)(u64IRQ & 0xFFFFFFFF); ++ u64Flag |= (MS_U64)(R4BYTE(REG_SCL0_13_L) & u32Mask); ++ } ++ ++ if(u64IRQ & 0x000000FF00000000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0x000000FF00000000)>>32); ++ u64Flag |= (((MS_U64)(R2BYTE(REG_SCL0_15_L) & u16Mask))<<32); ++ ++ } ++ ++ return u64Flag; ++} ++MS_U16 Hal_SCLIRQ_CMDQ_get_clear_irq(void) ++{ ++ return R2BYTEMSK(REG_SCL0_1E_L, 0xFFFF); ++} ++ ++ ++void Hal_SCLIRQ_Set_Clear(MS_U64 u64IRQ, MS_BOOL bEn) ++{ ++ MS_U16 u16Mask; ++ ++ if(u64IRQ & 0x0000FFFF) ++ { ++ u16Mask = (MS_U16)(u64IRQ & 0x0000FFFF); ++ W2BYTEMSK(REG_SCL0_10_L, bEn ? u16Mask : 0, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFFFF0000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFFFF0000)>>16); ++ W2BYTEMSK(REG_SCL0_11_L, bEn ? u16Mask : 0, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFF00000000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFF00000000)>>32); ++ W2BYTEMSK(REG_SCL0_12_L, bEn ? u16Mask : 0, u16Mask); ++ } ++} ++ ++void Hal_SCLIRQ_Set_Mask(MS_U64 u64IRQ, MS_BOOL bEn) ++{ ++ MS_U16 u16val; ++ MS_U16 u16Mask; ++ ++ if(u64IRQ & 0x0000FFFF) ++ { ++ u16Mask = (MS_U16)(u64IRQ & 0x0000FFFF); ++ u16val = bEn ? ~u16Mask : u16Mask; ++ W2BYTEMSK(REG_SCL0_08_L, u16val, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFFFF0000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFFFF0000)>>16); ++ u16val = bEn ? ~u16Mask : u16Mask; ++ W2BYTEMSK(REG_SCL0_09_L, u16val, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFF00000000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFF00000000)>>32); ++ u16val = bEn ? ~u16Mask : u16Mask; ++ W2BYTEMSK(REG_SCL0_0A_L, u16val, u16Mask); ++ } ++} ++ ++#undef HAL_SCLIRQ_C +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/include/halsclirq.h b/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/include/halsclirq.h +new file mode 100644 +index 00000000..f5cdae8a +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/include/halsclirq.h +@@ -0,0 +1,124 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_SCLIRQ_H ++#define _HAL_SCLIRQ_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_SCLIRQ_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_SCLIRQ_Set_Riu_Base(MS_U32 u32Riubase); ++INTERFACE void Hal_SCLIRQ_Set_Mask(MS_U64 u64IRQ, MS_BOOL bEn); ++INTERFACE void Hal_SCLIRQ_Set_Clear(MS_U64 u64IRQ, MS_BOOL bEn); ++INTERFACE MS_U64 Hal_SCLIRQ_Get_Flag(MS_U64 u64IRQ); ++INTERFACE MS_U16 Hal_SCLIRQ_CMDQ_get_clear_irq(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/include/halsclirq_utility.h b/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/include/halsclirq_utility.h +new file mode 100644 +index 00000000..3cb8af12 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/sclirq/include/halsclirq_utility.h +@@ -0,0 +1,53 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCLIRQ_UTILITY_H_ ++#define _HALSCLIRQ_UTILITY_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 SCLIRQ_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( SCLIRQ_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( SCLIRQ_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (SCLIRQ_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( SCLIRQ_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/vip/halvip.c b/drivers/mstar/scl/infinity/src/mxlib/hal/vip/halvip.c +new file mode 100644 +index 00000000..79a37266 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/vip/halvip.c +@@ -0,0 +1,735 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_VIP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg.h" ++#include "halvip_utility.h" ++#include "halvip.h" ++#include "drvPQ_Define.h" ++ ++#include "Infinity_Main.h" // table config parameter ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define HAL_VIP_DBG(x) ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_U32 VIP_RIU_BASE = 0; ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_VIP_Set_Riu_Base(MS_U32 u32riubase) ++{ ++ VIP_RIU_BASE = u32riubase; ++} ++void Hal_VIP_SetDNRIPMRead(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT0 : 0, BIT0);//IOenable ++} ++void Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_TYPE endump,MS_BOOL u8Sram) ++{ ++ MS_U16 u16addr = 0,u16tvalue = 0,u16tcount = 0,u16clkreg,u16readdata; ++ MS_U8 u8sec = 0; ++ EN_VIP_SRAM_SEC_NUM enSecNum; ++ MS_U32 u32reg = endump == EN_VIP_SRAM_DUMP_IHC ? REG_VIP_ACE2_7C_L : ++ endump == EN_VIP_SRAM_DUMP_ICC ? REG_VIP_ACE2_78_L : ++ endump == EN_VIP_SRAM_DUMP_HVSP ? REG_SCL_HVSP0_41_L: ++ endump == EN_VIP_SRAM_DUMP_HVSP_1 ? REG_SCL_HVSP1_41_L: ++ endump == EN_VIP_SRAM_DUMP_HVSP_2 ? REG_SCL_HVSP2_41_L: ++ 0; ++ u16clkreg = R2BYTE(REG_SCL_CLK_64_L); ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0,0xFFFF); ++ if(endump == EN_VIP_SRAM_DUMP_HVSP_2) ++ { ++ u16clkreg = R2BYTE(REG_SCL_CLK_65_L); ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0,0xFFFF); ++ } ++ if(endump == EN_VIP_SRAM_DUMP_IHC || endump == EN_VIP_SRAM_DUMP_ICC) ++ { ++ W2BYTEMSK(u32reg, BIT0, BIT0);//IOenable ++ for(u8sec=0;u8sec<4;u8sec++) ++ { ++ switch(u8sec) ++ { ++ case 0: ++ enSecNum = EN_VIP_SRAM_SEC_0; ++ break; ++ case 1: ++ enSecNum = EN_VIP_SRAM_SEC_1; ++ break; ++ case 2: ++ enSecNum = EN_VIP_SRAM_SEC_2; ++ break; ++ case 3: ++ enSecNum = EN_VIP_SRAM_SEC_3; ++ break; ++ default: ++ break; ++ ++ } ++ W2BYTEMSK(u32reg, u8sec<<1, BIT1|BIT2);//sec ++ for(u16addr=0;u16addr>4); ++ W4BYTE(REG_VIP_MWE_1A_L,u32addr2>>4); ++} ++void Hal_VIP_SetDLCshift(MS_U8 u8value) ++{ ++ W2BYTEMSK(REG_VIP_DLC_03_L,u8value,0x0007); ++} ++void HAl_VIP_SetDLCmode(MS_U8 u8value) ++{ ++ W2BYTEMSK(REG_VIP_MWE_1C_L,u8value<<2,0x0004); ++} ++void Hal_VIP_SetDLCActWin(MS_BOOL bEn,MS_U16 u16Vst,MS_U16 u16Hst,MS_U16 u16Vnd,MS_U16 u16Hnd) ++{ ++ W2BYTEMSK(REG_VIP_DLC_08_L,bEn<<7,0x0080); ++ W2BYTEMSK(REG_VIP_MWE_01_L,u16Vst,0x03FF); ++ W2BYTEMSK(REG_VIP_MWE_02_L,u16Vnd,0x03FF); ++ W2BYTEMSK(REG_VIP_MWE_03_L,u16Hst,0x01FF); ++ W2BYTEMSK(REG_VIP_MWE_04_L,u16Hnd,0x01FF); ++} ++void Hal_VIP_DLCHistSetRange(MS_U8 u8value,MS_U8 u8range) ++{ ++ MS_U16 u16tvalue; ++ MS_U16 u16Mask; ++ MS_U32 u32Reg; ++ u8range = u8range-1; ++ u32Reg = REG_VIP_DLC_0C_L+(((u8range)/2)*2); ++ if((u8range%2) == 0) ++ { ++ u16Mask = 0x00FF; ++ u16tvalue = ((MS_U16)u8value); ++ ++ } ++ else ++ { ++ u16Mask = 0xFF00; ++ u16tvalue = ((MS_U16)u8value)<<8; ++ } ++ ++ W2BYTEMSK(u32Reg,(u16tvalue),u16Mask); ++ ++} ++MS_U32 Hal_VIP_DLC_Hist_GetRange(MS_U8 u8range) ++{ ++ MS_U32 u32tvalue; ++ MS_U32 u32Reg; ++ u32Reg = REG_VIP_MWE_20_L+(((u8range)*2)*2); ++ u32tvalue = R4BYTE(u32Reg); ++ return u32tvalue; ++ ++} ++ ++MS_U8 Hal_VIP_DLCGetBaseidx(void) ++{ ++ MS_U8 u8tvalue; ++ u8tvalue = R2BYTE(REG_VIP_MWE_15_L); ++ u8tvalue = (MS_U8)(u8tvalue&0x80)>>7; ++ return u8tvalue; ++} ++ ++MS_U32 Hal_VIP_DLCGetPC(void) ++{ ++ MS_U32 u32tvalue; ++ u32tvalue = R4BYTE(REG_VIP_MWE_08_L); ++ return u32tvalue; ++} ++ ++MS_U32 Hal_VIP_DLCGetPW(void) ++{ ++ MS_U32 u32tvalue; ++ u32tvalue = R4BYTE(REG_VIP_MWE_0A_L); ++ return u32tvalue; ++} ++ ++MS_U8 Hal_VIP_DLCGetMinP(void) ++{ ++ MS_U16 u16tvalue; ++ u16tvalue = R2BYTE(REG_VIP_DLC_62_L); ++ u16tvalue = (u16tvalue>>8); ++ return (MS_U8)u16tvalue; ++} ++ ++MS_U8 Hal_VIP_DLCGetMaxP(void) ++{ ++ MS_U16 u16tvalue; ++ u16tvalue = R2BYTE(REG_VIP_DLC_62_L); ++ return (MS_U8)u16tvalue; ++} ++// LDC frame control ++void Hal_VIP_SetLDCBypass(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0F_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++ ++void Hal_VIP_SetLDCFrameBufferSetting(MS_U8 u8Val) ++{ ++ W2BYTEMSK(REG_SCL_LDC_09_L, (u8Val), BIT8|BIT5|BIT4|BIT3|BIT2); ++} ++ ++ ++void Hal_VIP_SetLDCDmapBase(MS_U32 u32Base) ++{ ++ W4BYTE(REG_SCL_LDC_0A_L, u32Base); ++} ++ ++void Hal_VIP_SetLDCDmapPitch(MS_U32 u32Pitch) ++{ ++ W4BYTE(REG_SCL_LDC_0C_L, u32Pitch); ++} ++void Hal_VIP_SetLDC422_444_allMd(MS_U8 u8md) ++{ ++ W2BYTEMSK(REG_SCL_LDC_1F_L, (MS_U16)u8md, BIT4|BIT3|BIT2|BIT1|BIT0); ++} ++void Hal_VIP_SetLDCDmapOffset(MS_U8 u8offset) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0E_L, (u8offset), 0x003F); ++} ++ ++void Hal_VIP_SetLDCDmapPS(MS_U8 bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0E_L, (bEn<<6), BIT6); ++} ++void Hal_VIP_SetLDCSramAmount(MS_U16 u16hor,MS_U16 u16ver) ++{ ++ W2BYTEMSK(REG_SCL_LDC_22_L, ((MS_U16)u16hor), 0xFFFF); ++ W2BYTEMSK(REG_SCL_LDC_2A_L, ((MS_U16)u16ver), 0xFFFF); ++} ++void Hal_VIP_SetLDCSramBase(MS_U32 u32hor,MS_U32 u32ver) ++{ ++ W4BYTE(REG_SCL_LDC_24_L, (u32hor>>4)); ++ W4BYTE(REG_SCL_LDC_2C_L, (u32ver>>4)); ++} ++void Hal_VIP_SetLDCSramStr(MS_U16 u16hor,MS_U16 u16ver) ++{ ++ ++ W2BYTEMSK(REG_SCL_LDC_23_L, ((MS_U16)u16hor), 0xFFFF); ++ W2BYTEMSK(REG_SCL_LDC_2B_L, ((MS_U16)u16ver), 0xFFFF); ++} ++ ++void Hal_VIP_SetAutodownloadAddr(MS_U32 u32baseadr,MS_U16 u16iniaddr,MS_U8 u8cli) ++{ ++ switch(u8cli) ++ { ++ case 9: ++ W2BYTEMSK(REG_SCL1_73_L, (MS_U16)(u32baseadr>>4), 0xFFFF); ++ W2BYTEMSK(REG_SCL1_74_L, (MS_U16)(u32baseadr>>20), 0x01FF); ++ W2BYTEMSK(REG_SCL1_77_L, ((MS_U16)u16iniaddr), 0xFFFF); ++ break; ++ default: ++ break; ++ } ++} ++ ++void Hal_VIP_SetAutodownloadReq(MS_U16 u16depth,MS_U16 u16reqlen,MS_U8 u8cli) ++{ ++ switch(u8cli) ++ { ++ case 9: ++ W2BYTEMSK(REG_SCL1_76_L, ((MS_U16)u16reqlen), 0xFFFF); ++ W2BYTEMSK(REG_SCL1_75_L, ((MS_U16)u16depth), 0xFFFF); ++ break; ++ default: ++ break; ++ } ++} ++ ++void Hal_VIP_SetAutodownload(MS_U8 bCLientEn,MS_U8 btrigContinue,MS_U8 u8cli) ++{ ++ switch(u8cli) ++ { ++ case 9: ++ W2BYTEMSK(REG_SCL1_72_L, bCLientEn|(btrigContinue<<1), 0x0003); ++ break; ++ default: ++ break; ++ } ++} ++ ++void Hal_VIP_SetAutodownloadTimer(MS_U8 bCLientEn) ++{ ++ W2BYTEMSK(REG_SCL1_78_L, bCLientEn<<15, 0x8000); ++} ++void Hal_VIP_GetNLMSRAM(MS_U16 u16entry) ++{ ++ MS_U32 u32tvalue1,u32tvalue2; ++ W2BYTEMSK(REG_SCL_NLM0_62_L, u16entry, 0x07FF); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x8000, 0x8000); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x2000, 0x2000); ++ u32tvalue1 = R2BYTE(REG_SCL_NLM0_64_L); ++ u32tvalue2 = R2BYTE(REG_SCL_NLM0_65_L); ++ u32tvalue1 |= ((u32tvalue2&0x00F0)<<12); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x0000, 0x8000); ++ HAL_VIP_DBG(printf("[Get_SRAM]entry%hx :%lx\n",u16entry,u32tvalue1)); ++} ++ ++void Hal_VIP_SetNLMSRAMbyCPU(MS_U16 u16entry,MS_U32 u32tvalue) ++{ ++ W2BYTEMSK(REG_SCL_NLM0_62_L, u16entry, 0x07FF); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x8000, 0x8000); ++ W2BYTEMSK(REG_SCL_NLM0_63_L, (MS_U16)u32tvalue, 0xFFFF); ++ W2BYTEMSK(REG_SCL_NLM0_65_L, (MS_U16)(u32tvalue>>16), 0x000F); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x4000, 0x4000); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x0000, 0x8000); ++ HAL_VIP_DBG(printf("[Set_SRAM]entry%hx :%lx\n",u16entry,u32tvalue)); ++} ++ ++#define VTRACK_KEY_SETTING_LENGTH 8 ++ ++static MS_U8 u8VtrackKey[VTRACK_KEY_SETTING_LENGTH]= ++{ ++ 0xaa,0x13,0x46,0x90,0x28,0x35,0x29,0xFE, ++}; ++ ++void Hal_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ /* ++ * Default Setting: ++ * setting1 [0e] => 8'h00 ++ * setting2 [0f] => 8'h00 ++ * setting3 [1a:10] => 165'h04 21 08 418c6318c4 21084210842108421086318c53 ++ */ ++ ++ MS_U8 *pu8Data = NULL; ++ MS_U16 u16Index = 0; ++ MS_U16 u16Data = 0; ++ ++ if (bUserDefinded == TRUE) ++ { ++ pu8Data = pu8Setting; ++ } ++ else ++ { ++ pu8Data = &u8VtrackKey[0]; ++ } ++ for (u16Index = 0; u16Index < VTRACK_KEY_SETTING_LENGTH; u16Index = u16Index+2) ++ { ++ MS_U8 u8Offset = (( (u16Index) / 2) *2 ); ++ MS_U32 u32Addr = REG_SCL1_24_L + u8Offset; ++ ++ if ( (VTRACK_KEY_SETTING_LENGTH - u16Index) >= 2) ++ { ++ u16Data = (MS_U16)pu8Data[u16Index +1]; ++ u16Data = (u16Data << 8) + (MS_U16) pu8Data[u16Index]; ++ W2BYTEMSK(u32Addr, u16Data, 0xffff); ++ } ++ } ++ ++} ++ ++void Hal_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID) ++{ ++ /* ++ * reg_payload_use from 0x28 to 0x2C (1B - 1F) ++ * {14'h0, TimeCode[55:40], Unique ID (OTP)[39:8], Operator ID[7:0]} ++ */ ++ ++ W2BYTEMSK(REG_SCL1_28_L, (MS_U16)u8OperatorID, 0x00ff); ++ W2BYTEMSK(REG_SCL1_2A_L, (u16Timecode << 8) , 0xff00); ++ W2BYTEMSK(REG_SCL1_2B_L, (u16Timecode >> 8) , 0x00ff); ++ ++} ++ ++#define VTRACK_SETTING_LENGTH 23 ++ ++static MS_U8 u8VtrackSetting[VTRACK_SETTING_LENGTH]= ++{ ++ 0x00, 0x00, 0xe8, 0x18, 0x32, ++ 0x86, 0x10, 0x42, 0x08, 0x21, ++ 0x84, 0x10, 0x42, 0x08, 0x21, ++ 0xc4, 0x18, 0x63, 0x8c, 0x41, ++ 0x08, 0x21, 0x04, ++}; ++ ++void Hal_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ /* ++ * Default Setting: ++ * setting1 [0e] => 8'h00 ++ * setting2 [0f] => 8'h00 ++ * setting3 [1a:10] => 165'h04 21 08 418c6318c4 21084210842108421086318c53 ++ */ ++ ++ MS_U8 *pu8Data = NULL; ++ MS_U16 u16Index = 0; ++ MS_U16 u16Data = 0; ++ ++ if (bUserDefinded == TRUE) ++ { ++ pu8Data = pu8Setting; ++ } ++ else ++ { ++ pu8Data = &u8VtrackSetting[0]; ++ } ++ //MenuLoad enable ++ W2BYTEMSK(REG_SCL1_2E_L, pu8Data[0], 0xff); ++ W2BYTEMSK(REG_SCL1_2F_L, pu8Data[1], 0xff); ++ for (u16Index = 2; u16Index < VTRACK_SETTING_LENGTH; u16Index = u16Index+2) ++ { ++ MS_U8 u8Offset = (( (u16Index - 2) / 2) *2 ); ++ MS_U32 u32Addr = REG_SCL1_30_L + u8Offset; ++ ++ if ( (VTRACK_SETTING_LENGTH - u16Index) >= 2) ++ { ++ u16Data = (MS_U16)pu8Data[u16Index +1]; ++ u16Data = (u16Data << 8) + (MS_U16) pu8Data[u16Index]; ++ W2BYTEMSK(u32Addr, u16Data, 0xffff); ++ } ++ else ++ { ++ u16Data = (MS_U16) pu8Data[u16Index]; ++ W2BYTEMSK(u32Addr, u16Data, 0x00ff); ++ } ++ } ++ ++} ++ ++#define VIP_VTRACK_MODE 0x1c //[3]:v_sync_inv_en ;[2]:h_sync_inv_en [4]mux ++void Hal_VIP_VtrackEnable(MS_U8 u8FrameRate, EN_VIP_VTRACK_ENABLE_TYPE bEnable) ++{ ++ //FrameRateIn => 8'h1E ++ W2BYTEMSK(REG_SCL1_21_L , u8FrameRate, 0xFF); ++ ++ //EnableIn => 1 ++ //DebugEn => 0 ++ if (bEnable == EN_VIP_VTRACK_ENABLE_ON) ++ { ++ W2BYTEMSK(REG_SCL1_20_L , BIT(0), BIT(1)|BIT(0) ); ++ W2BYTEMSK(REG_SCL1_22_L , VIP_VTRACK_MODE, 0x3F ); ++ } ++ else if(bEnable == EN_VIP_VTRACK_ENABLE_DEBUG) ++ { ++ W2BYTEMSK(REG_SCL1_20_L , BIT(1)|BIT(0), BIT(1)|BIT(0) ); ++ W2BYTEMSK(REG_SCL1_22_L , VIP_VTRACK_MODE, 0x3F ); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL1_20_L , 0x00, BIT(1)|BIT(0) ); ++ W2BYTEMSK(REG_SCL1_22_L , VIP_VTRACK_MODE, 0x3F ); ++ } ++} ++MS_BOOL Hal_VIP_GetVIPBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = R2BYTE(REG_VIP_LCE_70_L)&BIT0; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetDNRBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = R2BYTE(REG_SCL_DNR0_21_L)&(BIT0|BIT1); ++ bRet = (((bRet&BIT1)>>1)|(bRet&BIT0))? 0: 1; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetSNRBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = R2BYTE(REG_SCL_DNR0_22_L)&(BIT0|BIT1); ++ bRet = (((bRet&BIT1)>>1)|(bRet&BIT0))? 0: 1; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetLDCBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = (R2BYTE(REG_SCL_LDC_0F_L)&BIT0)? 1: 0; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetNLMBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = (R2BYTE(REG_SCL_NLM0_01_L)&BIT0)? 0: 1; ++ return bRet; ++} +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/vip/include/halvip.h b/drivers/mstar/scl/infinity/src/mxlib/hal/vip/include/halvip.h +new file mode 100644 +index 00000000..f0a8bb7f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/vip/include/halvip.h +@@ -0,0 +1,179 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_VIP_H ++#define _HAL_VIP_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ EN_VIP_SRAM_SEC_0 =289, ++ EN_VIP_SRAM_SEC_1 =272, ++ EN_VIP_SRAM_SEC_2 =272, ++ EN_VIP_SRAM_SEC_3 =256, ++}EN_VIP_SRAM_SEC_NUM; ++ ++typedef enum ++{ ++ EN_VIP_SRAM_DUMP_ICC, ++ EN_VIP_SRAM_DUMP_IHC, ++ EN_VIP_SRAM_DUMP_HVSP, ++ EN_VIP_SRAM_DUMP_HVSP_1, ++ EN_VIP_SRAM_DUMP_HVSP_2, ++}EN_VIP_SRAM_DUMP_TYPE; ++typedef enum ++{ ++ EN_VIP_VTRACK_ENABLE_ON, ++ EN_VIP_VTRACK_ENABLE_OFF, ++ EN_VIP_VTRACK_ENABLE_DEBUG, ++}EN_VIP_VTRACK_ENABLE_TYPE; ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_VIP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++INTERFACE void Hal_VIP_SetLDCFrameBufferSetting(MS_U8 u8Val); ++INTERFACE void Hal_VIP_SetLDC422_444_allMd(MS_U8 u8md); ++INTERFACE void Hal_VIP_Set_Riu_Base(MS_U32 u32riubase); ++INTERFACE void Hal_VIP_DLCHistVarOnOff(MS_U16 u16var); ++INTERFACE void Hal_VIP_SetDLCstatMIU(MS_U8 u8value,MS_U32 u32addr1,MS_U32 u32addr2); ++INTERFACE void Hal_VIP_SetDLCshift(MS_U8 u8value); ++INTERFACE void HAl_VIP_SetDLCmode(MS_U8 u8value); ++INTERFACE void Hal_VIP_DLCHistSetRange(MS_U8 u8value,MS_U8 u8range); ++INTERFACE MS_U32 Hal_VIP_DLC_Hist_GetRange(MS_U8 u8range); ++INTERFACE void Hal_VIP_SetLDCBypass(MS_BOOL bEn); ++INTERFACE void Hal_VIP_SetLDCDmapPitch(MS_U32 u32Pitch); ++INTERFACE void Hal_VIP_SetLDCDmapBase(MS_U32 u32Base); ++INTERFACE void Hal_VIP_SetLDCDmapPS(MS_U8 bEn); ++INTERFACE void Hal_VIP_SetLDCDmapOffset(MS_U8 u8offset); ++INTERFACE void Hal_VIP_SetLDCSramAmount(MS_U16 u16hor,MS_U16 u16ver); ++INTERFACE void Hal_VIP_SetLDCSramBase(MS_U32 u32hor,MS_U32 u32ver); ++INTERFACE void Hal_VIP_SetLDCSramStr(MS_U16 u16hor,MS_U16 u16ver); ++INTERFACE MS_U8 Hal_VIP_DLCGetBaseidx(void); ++INTERFACE MS_U32 Hal_VIP_DLCGetPC(void); ++INTERFACE MS_U32 Hal_VIP_DLCGetPW(void); ++INTERFACE MS_U8 Hal_VIP_DLCGetMinP(void); ++INTERFACE MS_U8 Hal_VIP_DLCGetMaxP(void); ++INTERFACE void Hal_VIP_SetDLCActWin(MS_BOOL bEn,MS_U16 u16Vst,MS_U16 u16Hst,MS_U16 u16Vnd,MS_U16 u16Hnd); ++INTERFACE void Hal_VIP_SetDNRIPMRead(MS_BOOL bEn); ++ ++INTERFACE void Hal_VIP_SetAutodownloadAddr(MS_U32 u32baseadr,MS_U16 u16iniaddr,MS_U8 u8cli); ++INTERFACE void Hal_VIP_SetAutodownloadReq(MS_U16 u16depth,MS_U16 u16reqlen,MS_U8 u8cli); ++INTERFACE void Hal_VIP_SetAutodownload(MS_U8 bCLientEn,MS_U8 btrigContinue,MS_U8 u8cli); ++INTERFACE void Hal_VIP_SetAutodownloadTimer(MS_U8 bCLientEn); ++INTERFACE void Hal_VIP_GetNLMSRAM(MS_U16 u16entry); ++INTERFACE void Hal_VIP_SetNLMSRAMbyCPU(MS_U16 u16entry,MS_U32 u32tvalue); ++INTERFACE void Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_TYPE endump,MS_BOOL u8Sram); ++INTERFACE void Hal_VIP_VtrackEnable(MS_U8 u8FrameRate, EN_VIP_VTRACK_ENABLE_TYPE bEnable); ++INTERFACE void Hal_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE void Hal_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE void Hal_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID); ++INTERFACE MS_BOOL Hal_VIP_GetVIPBypass(void); ++INTERFACE MS_BOOL Hal_VIP_GetDNRBypass(void); ++INTERFACE MS_BOOL Hal_VIP_GetSNRBypass(void); ++INTERFACE MS_BOOL Hal_VIP_GetLDCBypass(void); ++INTERFACE MS_BOOL Hal_VIP_GetNLMBypass(void); ++ #undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/hal/vip/include/halvip_utility.h b/drivers/mstar/scl/infinity/src/mxlib/hal/vip/include/halvip_utility.h +new file mode 100644 +index 00000000..5ddf71f7 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/hal/vip/include/halvip_utility.h +@@ -0,0 +1,64 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCL_UTILITY_H_ ++#define _HALSCL_UTILITY_H_ ++ ++//!! Do not include this header in driver or api level ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 SCL_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( VIP_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( VIP_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (VIP_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( VIP_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/include/MsCommon.h b/drivers/mstar/scl/infinity/src/mxlib/include/MsCommon.h +new file mode 100644 +index 00000000..f200f639 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/include/MsCommon.h +@@ -0,0 +1,208 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsCommon.h ++/// @brief MStar Common Interface Header File ++/// @author MStar Semiconductor Inc. ++/// @note MsCommon.h includes most command header files including basic data type, macro(MsTypes.h),\n ++/// board configuration(MsBoard.h), and OS related API(MsOS.h).\n ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_COMMON_H_ ++#define _MS_COMMON_H_ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include "ms_platform.h" ++#include ++#include ++ ++#endif ++ ++#ifndef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#else ++#endif ++ ++#include ++//#include ++ ++#include "MsTypes.h" ++#include "MsIRQ.h" ++//#include "MsVersion.h" ++#include "MsOS.h" // Plan to be obsoleted in next generation. ++#include "MsDevice.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macros ++//------------------------------------------------------------------------------------------------- ++#define GEN_EXCEP { while(1); } ++ ++//#define REG(addr) (*(volatile U32 *)(addr)) ++#if 0 ++#ifdef __aeon__ ++ ++//------------------------------------------------------------------------------------------------- ++// In order to keep the compatiblity of the source code from Venus, ++// keep these memory address translation for a while. ++// They will be removed in the future. ++//------------------------------------------------------------------------------------------------- ++#define CACHED_BASE ((void *)0x00000000) ++#define UNCACHED_BASE ((void *)0x80000000) ++ ++#define CACHED_SIZE ((void *)0x20000000) ++#define UNCACHED_SIZE ((void *)0x20000000) ++// 0xA0000000~0xA000FFFF belongs to RIU ++// 0xA1000000~ belongs to SPI ++ ++//cached/unchched segment ++#define KSEG0_BASE CACHED_BASE ++#define KSEG1_BASE UNCACHED_BASE ++#define KSEG0_SIZE CACHED_SIZE ++#define KSEG1_SIZE UNCACHED_SIZE ++ ++//cached <-> uncached ++#define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x80000000)) ++#define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x80000000)) ++ ++//virtual <-> physical ++#define VA2PA(addr) ((void *)(((U32)addr) & 0x1fffffff)) ++#define PA2KSEG0(addr) ((void *)(((U32)addr) | 0x00000000)) ++#define PA2KSEG1(addr) ((void *)(((U32)addr) | 0x80000000)) ++#endif ++ ++#if defined(__mips__) ++ ++//cached/unchched segment ++#define KSEG0_BASE ((void *)0x80000000) ++#define KSEG1_BASE ((void *)0xa0000000) ++#define KSEG0_SIZE 0x20000000 ++#define KSEG1_SIZE 0x20000000 ++ ++//cached addr <-> unchched addr ++#define KSEG02KSEG1(addr) ((void *)((MS_U32)(addr)|0x20000000)) //cached -> unchched ++#define KSEG12KSEG0(addr) ((void *)((MS_U32)(addr)&~0x20000000)) //unchched -> cached ++ ++//virtual addr <-> physical addr ++#define VA2PA(addr) ((void *)(((MS_U32)addr) & 0x1fffffff)) //virtual -> physical ++#define PA2KSEG0(addr) ((void *)(((MS_U32)addr) | 0x80000000)) //physical -> cached ++#define PA2KSEG1(addr) ((void *)(((MS_U32)addr) | 0xa0000000)) //physical -> unchched ++#endif ++#endif ++ ++#if 0 ++//cached/unchched segment ++#define KSEG0_BASE ((void *)0x80000000) ++#define KSEG1_BASE ((void *)0xa0000000) ++#define KSEG0_SIZE 0x20000000 ++#define KSEG1_SIZE 0x20000000 ++ ++//cached <-> unchched ++#define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x20000000)) ++#define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x20000000)) ++ ++//virtual <-> physical ++#define VA2PA(addr) ((void *)(((U32)addr) & 0x1fffffff)) ++#define PA2KSEG0(addr) ((void *)(((U32)addr) | 0x80000000)) ++#define PA2KSEG1(addr) ((void *)(((U32)addr) | 0xa0000000)) ++#endif ++ ++//user-defined assert ++#ifdef MS_DEBUG ++#define MS_ASSERT(_bool_) \ ++ { \ ++ if ( ! ( _bool_ ) ) \ ++ { \ ++/* UTL_printf("ASSERT FAIL: %s, %s %s %d\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__); */ \ ++/* MAsm_CPU_SwDbgBp(); */ \ ++ } \ ++ } ++#else ++#define MS_ASSERT(_bool_) \ ++ { \ ++ if ( ! ( _bool_ ) ) \ ++ { \ ++/* UTL_printf("ASSERT FAIL: %s %s %s %d\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__); */ \ ++ } \ ++ } ++#endif ++ ++ ++#ifndef MIN ++#define MIN(_a_, _b_) ((_a_) < (_b_) ? (_a_) : (_b_)) ++#endif ++#ifndef MAX ++#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_)) ++#endif ++ ++ ++#define ALIGN_4(_x_) (((_x_) + 3) & ~3) ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define ALIGN_16(_x_) (((_x_) + 15) & ~15) // No data type specified, optimized by complier ++#define ALIGN_32(_x_) (((_x_) + 31) & ~31) // No data type specified, optimized by complier ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++ ++ ++//!!! avoid warning of out-of-range integer !!!// ++#if defined(MSOS_TYPE_NOS) // for chip back verificatoin ++#define BIT(_bit_) (1UL << (_bit_)) ++#else ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#endif ++ ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++ ++#define READ_BYTE(x) ms_readb(x) ++#define READ_WORD(x) ms_readw(x) ++#define READ_LONG(x) ms_readl(x) ++#define WRITE_BYTE(x, y) ms_writeb((MS_U8)(y), x) ++#define WRITE_WORD(x, y) ms_writew((MS_U16)(y), x) ++#define WRITE_LONG(x, y) ms_writel((MS_U32)(y), x) ++ ++#else ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++ ++#if ( defined(MSOS_TYPE_CE) || defined(MSOS_TYPE_NOS) ) ++ #define WRITE_BYTE(_reg, _val) (*((volatile MS_U8*)(_reg))) = (MS_U8)(_val) ++ #define WRITE_WORD(_reg, _val) (*((volatile MS_U16*)(_reg))) = (MS_U16)(_val) ++#else ++ #define WRITE_BYTE(_reg, _val) { (*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++ #define WRITE_WORD(_reg, _val) { (*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#endif ++#define WRITE_LONG(_reg, _val) { (*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#endif ++ ++#endif // _MS_COMMON_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/include/MsDbg.h b/drivers/mstar/scl/infinity/src/mxlib/include/MsDbg.h +new file mode 100644 +index 00000000..76b831d5 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/include/MsDbg.h +@@ -0,0 +1,28 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MS_DBG_H_ ++#define _MS_DBG_H_ ++ ++#define ENABLE_HVSP_UNUSED_FUNCTION 0 ++#define ENABLE_PNL_UNUSED_FUNCTION 0 ++#define ENABLE_SCLDMA_UNUSED_FUNCTION 0 ++#define ENABLE_VIP_UNUSED_FUNCTION 0 ++#define ENABLE_PQ_UNUSED_FUNCTION 0 ++ ++#endif // _MS_DBG_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/include/MsDevice.h b/drivers/mstar/scl/infinity/src/mxlib/include/MsDevice.h +new file mode 100644 +index 00000000..784a480e +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/include/MsDevice.h +@@ -0,0 +1,158 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __PRANA_DEVICE_H__ ++#define __PRANA_DEVICE_H__ ++ ++#include "MsTypes.h" ++ ++#define DEVICE_NULL ((device_t)0) ++ ++typedef unsigned long device_t; ++ ++// ++// device PM event ++// ++typedef enum ++{ ++ E_EVT_SUSPEND = 1, ++ E_EVT_SHUTDOWN = 2, ++} eDEVEVT; ++ ++// ++// poll types ++// ++ ++#ifndef POLLIN ++#define POLLIN 0x01 ++#endif ++ ++#ifndef POLLOUT ++#define POLLOUT 0x02 ++#endif ++ ++#ifndef POLLHUP ++#define POLLHUP 0x04 ++#endif ++ ++// ++// device I/O operations ++// ++struct devio ++{ ++ int (*open) (device_t dev, int mode); ++ int (*close)(device_t dev); ++// int (*read) (device_t dev, char *buf, size_t len, int off); ++ int (*read) (device_t dev, char *buf, MS_U32 len, int off); ++// int (*write)(device_t dev, const char *buf, size_t len, int off); ++ int (*write)(device_t dev, const char *buf, MS_U32 len, int off); ++ int (*poll) (device_t dev, int types); ++ int (*ioctl)(device_t dev, int request, unsigned long arg); ++ int (*event)(eDEVEVT evt); ++}; ++ ++ ++#define DEVICE_MAGIC (('D' << 24) | ('E' << 16) | ('V' << 8) | 'I') ++ ++// ++// device structure ++// ++#if 0 ++struct device ++{ ++ int magic; // magic number ++ int refcnt; // reference count ++ int flags; // device characteristics ++ struct devio *devio; // device i/o table ++}; ++#endif ++ ++#define device_valid(dev) ((dev)->magic == DEVICE_MAGIC) ++#endif /* __PRANA_DEVICE_H__ */ ++ ++//MSTAR Module ID ++/******************************************************************************* ++!!!! WARNING NOT ALLOW MODIFY EXISTED VALUE !!!! ++!!!! ONLY ALLOW ADD NEW VALUE AFTER END OF THIS LIST !!!! ++*******************************************************************************/ ++#define MS_MODULE_HW 0x0000 ++ ++#define MS_MODULE_CHIPTOP 0x0011 ++#define MS_MODULE_MIU 0x0012 ++#define MS_MODULE_WDT 0x003C ++#define MS_MODULE_CFG 0x00F0 // Chip hard configuration info ++#define MS_MODULE_OTP 0x00F4 ++#define MS_MODULE_SPRAM 0x00F5 ++ ++#define MS_MODULE_ACE 0x0101 ++#define MS_MODULE_AUDIO 0x0102 ++#define MS_MODULE_AVD 0x0103 ++#define MS_MODULE_BDMA 0x0104 ++#define MS_MODULE_DLC 0x0105 ++#define MS_MODULE_FLASH 0x0106 ++#define MS_MODULE_GE 0x0107 ++#define MS_MODULE_GOP 0x0108 ++#define MS_MODULE_HVD 0x0109 ++#define MS_MODULE_HWI2C 0x010a ++#define MS_MODULE_IR 0x010b ++#define MS_MODULE_IRQ 0x010c ++#define MS_MODULE_JPD 0x010d ++#define MS_MODULE_MBX 0x010e ++#define MS_MODULE_MVD 0x010f ++#define MS_MODULE_MVOP 0x0120 ++#define MS_MODULE_RVD 0x0122 ++#define MS_MODULE_SC 0x0123 ++#define MS_MODULE_TSP 0x0124 ++#define MS_MODULE_UART 0x0125 ++#define MS_MODULE_VPU 0x0126 ++#define MS_MODULE_XC 0x0127 ++#define MS_MODULE_PNL 0x0128 ++#define MS_MODULE_ISP 0x0129 ++#define MS_MODULE_PFSH 0x012a ++#define MS_MODULE_GPIO 0x012b ++#define MS_MODULE_PM 0x012c ++#define MS_MODULE_VBI 0x012d ++#define MS_MODULE_PCMCIA 0x012e ++#define MS_MODULE_PIU 0x012f ++#define MS_MODULE_MHEG5 0x0130 ++#define MS_MODULE_RTC_0 0x0131 ++#define MS_MODULE_RTC_2 0x0132 ++#define MS_MODULE_VIF 0x0133 ++#define MS_MODULE_MFE 0x0134 ++#define MS_MODULE_DIP 0x0135 ++#define MS_MODULE_RASP 0x0136 ++#define MS_MODULE_MMFILEIN 0x0137 ++#define MS_MODULE_MPIF 0x0138 ++#define MS_MODULE_GPD 0x0139 ++#define MS_MODULE_TSO 0x013a ++#define MS_MODULE_IMI 0x013b // for C3 ++ ++ ++#define MS_MODULE_SEM 0x02f0 ++ ++#define MS_MODULE_CA 0x0300 // CA reserved ++#define MS_MODULE_NDS 0x0310 // NDS ++#define MS_MODULE_NSK 0x0311 ++#define MS_MODULE_CAM 0x0312 ++#define MS_MODULE_NGA 0x0313 ++ ++#define MS_MODULE_PWM 0x1032 ++#define MS_MODULE_DMD 0x1033 ++#define MS_MODULE_PWS 0x1034 ++#define MS_MODULE_EFUSE 0x1035 ++ ++#define MS_MODULE_FRC 0x2000 // A5 only +diff --git a/drivers/mstar/scl/infinity/src/mxlib/include/MsIRQ.h b/drivers/mstar/scl/infinity/src/mxlib/include/MsIRQ.h +new file mode 100644 +index 00000000..832417cf +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/include/MsIRQ.h +@@ -0,0 +1,420 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file MsIRQ.h ++/// @brief MStar IRQ ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MS_IRQ_H_ ++#define _MS_IRQ_H_ ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure Declaration ++//------------------------------------------------------------------------------------------------- ++#define MS_IRQ_MAX (128) //64 IRQs + 64 FIQs ++#define ENABLE_USB_PORT0 ++#define E_IRQ_FIQ_INVALID 0xFFFF ++ ++// Interrupt related ++typedef enum ++{ ++ // IRQ ++ E_INT_IRQ_0x00_START = 0x00, ++ E_INT_IRQ_UART0 = E_INT_IRQ_0x00_START+0, ++ E_INT_IRQ_BDMA_CH0 = E_INT_IRQ_0x00_START+1, ++ E_INT_IRQ_BDMA_CH1 = E_INT_IRQ_0x00_START+2, ++ E_INT_IRQ_MVD = E_INT_IRQ_0x00_START+3, ++ E_INT_IRQ_PS = E_INT_IRQ_0x00_START+4, ++ E_INT_IRQ_NFIE = E_INT_IRQ_0x00_START+5, ++ E_INT_IRQ_USB = E_INT_IRQ_0x00_START+6, ++ E_INT_IRQ_UHC = E_INT_IRQ_0x00_START+7, ++ E_INT_IRQ_EC_BRIDGE = E_INT_IRQ_0x00_START+8, ++ E_INT_IRQ_EMAC = E_INT_IRQ_0x00_START+9, ++ E_INT_IRQ_DISP = E_INT_IRQ_0x00_START+10, ++ E_INT_IRQ_DHC = E_INT_IRQ_0x00_START+11, ++ E_INT_IRQ_PMSLEEP = E_INT_IRQ_0x00_START+12, ++ E_INT_IRQ_SBM = E_INT_IRQ_0x00_START+13, ++ E_INT_IRQ_COMB = E_INT_IRQ_0x00_START+14, ++ E_INT_IRQ_ECC_DERR = E_INT_IRQ_0x00_START+15, ++ E_INT_IRQ_0x00_END = 0x0F, ++ ++ E_INT_IRQ_0x10_START = 0x10, ++ E_INT_IRQ_TSP2HK = E_INT_IRQ_0x10_START+0, ++ E_INT_IRQ_VE = E_INT_IRQ_0x10_START+1, ++ E_INT_IRQ_CIMAX2MCU = E_INT_IRQ_0x10_START+2, ++ E_INT_IRQ_DC = E_INT_IRQ_0x10_START+3, ++ E_INT_IRQ_GOP = E_INT_IRQ_0x10_START+4, ++ E_INT_IRQ_PCM = E_INT_IRQ_0x10_START+5, ++ E_INT_IRQ_IIC0 = E_INT_IRQ_0x10_START+6, ++ E_INT_IRQ_RTC = E_INT_IRQ_0x10_START+7, ++ E_INT_IRQ_KEYPAD = E_INT_IRQ_0x10_START+8, ++ E_INT_IRQ_PM = E_INT_IRQ_0x10_START+9, ++ E_INT_IRQ_DDC2BI = E_INT_IRQ_0x10_START+10, ++ E_INT_IRQ_SCM = E_INT_IRQ_0x10_START+11, ++ E_INT_IRQ_VBI = E_INT_IRQ_0x10_START+12, ++ E_INT_IRQ_M4VD = E_INT_IRQ_0x10_START+13, ++ E_INT_IRQ_FCIE2RIU = E_INT_IRQ_0x10_START+14, ++ E_INT_IRQ_ADCDVI2RIU = E_INT_IRQ_0x10_START+15, ++ E_INT_IRQ_0x10_END = 0x1F, ++ ++ // FIQ ++ E_INT_FIQ_0x20_START = 0x20, ++ E_INT_FIQ_EXTIMER0 = E_INT_FIQ_0x20_START+0, ++ E_INT_FIQ_EXTIMER1 = E_INT_FIQ_0x20_START+1, ++ E_INT_FIQ_WDT = E_INT_FIQ_0x20_START+2, ++ E_INT_FIQ_AEON_TO_8051 = E_INT_FIQ_0x20_START+3, ++ E_INT_FIQ_8051_TO_AEON = E_INT_FIQ_0x20_START+4, ++ E_INT_FIQ_8051_TO_BEON = E_INT_FIQ_0x20_START+5, ++ E_INT_FIQ_BEON_TO_8051 = E_INT_FIQ_0x20_START+6, ++ E_INT_FIQ_BEON_TO_AEON = E_INT_FIQ_0x20_START+7, ++ E_INT_FIQ_AEON_TO_BEON = E_INT_FIQ_0x20_START+8, ++ E_INT_FIQ_JPD = E_INT_FIQ_0x20_START+9, ++ E_INT_FIQ_MENULOAD = E_INT_FIQ_0x20_START+10, ++ E_INT_FIQ_HDMI_NON_PCM = E_INT_FIQ_0x20_START+11, ++ E_INT_FIQ_SPDIF_IN_NON_PCM = E_INT_FIQ_0x20_START+12, ++ E_INT_FIQ_EMAC = E_INT_FIQ_0x20_START+13, ++ E_INT_FIQ_SE_DSP2UP = E_INT_FIQ_0x20_START+14, ++ E_INT_FIQ_TSP2AEON = E_INT_FIQ_0x20_START+15, ++ E_INT_FIQ_0x20_END = 0x2F, ++ ++ E_INT_FIQ_0x30_START = 0x30, ++ E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0, ++ E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1, ++ E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2, ++ E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3, ++ E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4, ++ E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5, ++ E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6, ++ E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7, ++ E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8, ++ E_INT_FIQ_INT_CCFL = E_INT_FIQ_0x30_START+9, ++ E_INT_FIQ_INT = E_INT_FIQ_0x30_START+10, ++ E_INT_FIQ_IR = E_INT_FIQ_0x30_START+11, ++ E_INT_FIQ_AFEC_VSYNC = E_INT_FIQ_0x30_START+12, ++ E_INT_FIQ_DEC_DSP2UP = E_INT_FIQ_0x30_START+13, ++ E_INT_FIQ_MIPS_WDT = E_INT_FIQ_0x30_START+14, //U3 ++ E_INT_FIQ_DEC_DSP2MIPS = E_INT_FIQ_0x30_START+15, ++ E_INT_FIQ_0x30_END = 0x3F, ++ ++ E_INT_IRQ_0x40_START = 0x40, ++ E_INT_IRQ_SVD_HVD = E_INT_IRQ_0x40_START+0, ++ E_INT_IRQ_USB2 = E_INT_IRQ_0x40_START+1, ++ E_INT_IRQ_UHC2 = E_INT_IRQ_0x40_START+2, ++ E_INT_IRQ_MIU = E_INT_IRQ_0x40_START+3, ++ E_INT_IRQ_GDMA = E_INT_IRQ_0x40_START+4, //U3 ++ E_INT_IRQ_UART2 = E_INT_IRQ_0x40_START+5, //U3 ++ E_INT_IRQ_UART1 = E_INT_IRQ_0x40_START+6, //U3 ++ E_INT_IRQ_DEMOD = E_INT_IRQ_0x40_START+7, //U3 ++ E_INT_IRQ_MPIF = E_INT_IRQ_0x40_START+8, //U3 ++ E_INT_IRQ_JPD = E_INT_IRQ_0x40_START+9, //U3 ++ E_INT_IRQ_AEON2HI = E_INT_IRQ_0x40_START+10, //U3 ++ E_INT_IRQ_BDMA0 = E_INT_IRQ_0x40_START+11, //U3 ++ E_INT_IRQ_BDMA1 = E_INT_IRQ_0x40_START+12, //U3 ++ E_INT_IRQ_OTG = E_INT_IRQ_0x40_START+13, //U3 ++ E_INT_IRQ_MVD_CHECKSUM_FAIL = E_INT_IRQ_0x40_START+14, //U3 ++ E_INT_IRQ_TSP_CHECKSUM_FAIL = E_INT_IRQ_0x40_START+15, //U3 ++ E_INT_IRQ_0x40_END = 0x4F, ++ ++ E_INT_IRQ_0x50_START = 0x50, ++ E_INT_IRQ_CA_I3 = E_INT_IRQ_0x50_START+0, //U3 ++ E_INT_IRQ_HDMI_LEVEL = E_INT_IRQ_0x50_START+1, //U3 ++ E_INT_IRQ_MIPS_WADR_ERR = E_INT_IRQ_0x50_START+2, //U3 ++ E_INT_IRQ_RASP = E_INT_IRQ_0x50_START+3, //U3 ++ E_INT_IRQ_CA_SVP = E_INT_IRQ_0x50_START+4, //U3 ++ E_INT_IRQ_UART2MCU = E_INT_IRQ_0x50_START+5, //U3 ++ E_INT_IRQ_URDMA2MCU = E_INT_IRQ_0x50_START+6, //U3 ++ E_INT_IRQ_IIC1 = E_INT_IRQ_0x50_START+7, //U3 ++ E_INT_IRQ_HDCP = E_INT_IRQ_0x50_START+8, //U3 ++ E_INT_IRQ_DMA_WADR_ERR = E_INT_IRQ_0x50_START+9, //U3 ++ E_INT_IRQ_UP_IRQ_UART_CA = E_INT_IRQ_0x50_START+10, //U3 ++ E_INT_IRQ_UP_IRQ_EMM_ECM = E_INT_IRQ_0x50_START+11, //U3 ++ E_INT_IRQ_ONIF = E_INT_IRQ_0x50_START+12, //T8 ++ E_INT_IRQ_USB1 = E_INT_IRQ_0x50_START+13, //T8 ++ E_INT_IRQ_UHC1 = E_INT_IRQ_0x50_START+14, //T8 ++ E_INT_IRQ_MFE = E_INT_IRQ_0x50_START+15, //T8 ++ E_INT_IRQ_0x50_END = 0x5F, ++ ++ E_INT_FIQ_0x60_START = 0x60, ++ E_INT_FIQ_IR_INT_RC = E_INT_FIQ_0x60_START+0, //U3 ++ E_INT_FIQ_HDMITX_IRQ_EDGE = E_INT_FIQ_0x60_START+1, //U3 ++ E_INT_FIQ_UP_IRQ_UART_CA = E_INT_FIQ_0x60_START+2, //U3 ++ E_INT_FIQ_UP_IRQ_EMM_ECM = E_INT_FIQ_0x60_START+3, //U3 ++ E_INT_FIQ_PVR2MI_INT0 = E_INT_FIQ_0x60_START+4, //U3 ++ E_INT_FIQ_PVR2MI_INT1 = E_INT_FIQ_0x60_START+5, //U3 ++ //E_INT_FIQ_8051_TO_AEON = E_INT_FIQ_0x60_START+6, //T3, E_INT_FIQ_8051_TO_AEON ++ //Not Used = E_INT_FIQ_0x60_START+7, ++ E_INT_FIQ_AEON_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+8, //T3, ++ E_INT_FIQ_AEON_TO_MIPS_VPE1 = E_INT_FIQ_0x60_START+9, //T3, E_INT_FIQ_AEON_TO_BEON ++ //E_INT_FIQ_AEON_TO_8051 = E_INT_FIQ_0x60_START+10, //T3, E_INT_FIQ_AEON_TO_8051 ++ //Not Used = E_INT_FIQ_0x60_START+11, ++ E_INT_FIQ_MIPS_VPE1_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+12, //T3 ++ E_INT_FIQ_MIPS_VPE1_TO_AEON = E_INT_FIQ_0x60_START+13, //T3 ++ E_INT_FIQ_MIPS_VPE1_TO_8051 = E_INT_FIQ_0x60_START+14, //T3 ++ //Not Used = E_INT_FIQ_0x60_START+15, ++ E_INT_FIQ_0x60_END = 0x6F, ++ ++ E_INT_FIQ_0x70_START = 0x70, ++ E_INT_FIQ_MIPS_VPE0_TO_MIPS_VPE1 = E_INT_FIQ_0x70_START+0, //T3 ++ E_INT_FIQ_MIPS_VPE0_TO_AEON = E_INT_FIQ_0x70_START+1, //T3, E_INT_FIQ_AEON_TO_BEON ++ E_INT_FIQ_MIPS_VPE0_TO_8051 = E_INT_FIQ_0x70_START+2, //T3, E_INT_FIQ_BEON_TO_8051 ++ E_INT_FIQ_IR_IN = E_INT_FIQ_0x70_START+3, //T8 ++ E_INT_FIQ_DMDMCU2HK = E_INT_FIQ_0x70_START+4, ++ E_INT_FIQ_R2TOMCU_INT0 = E_INT_FIQ_0x70_START+5, //T8 ++ E_INT_FIQ_R2TOMCU_INT1 = E_INT_FIQ_0x70_START+6, //T8 ++ E_INT_FIQ_DSPTOMCU_INT0 = E_INT_FIQ_0x70_START+7, //T8 ++ E_INT_FIQ_DSPTOMCU_INT1 = E_INT_FIQ_0x70_START+8, //T8 ++ E_INT_FIQ_USB = E_INT_FIQ_0x70_START+9, //T8 ++ E_INT_FIQ_UHC = E_INT_FIQ_0x70_START+10, //T8 ++ E_INT_FIQ_USB1 = E_INT_FIQ_0x70_START+11, //T8 ++ E_INT_FIQ_UHC1 = E_INT_FIQ_0x70_START+12, //T8 ++ E_INT_FIQ_USB2 = E_INT_FIQ_0x70_START+13, //T8 ++ E_INT_FIQ_UHC2 = E_INT_FIQ_0x70_START+14, //T8 ++ //Not Used = E_INT_FIQ_0x70_START+15, ++ E_INT_FIQ_0x70_END = 0x7F, ++ ++ ++ // Add IRQ from 0x80 ~ 0xBF, ++ // if IRQ enum from 0x00 ~ 0x1F, and 0x40 ~ 0x5F is occupied ++ E_INT_IRQ_0x80_START = 0x80, ++ E_INT_IRQ_MLINK = E_INT_IRQ_0x80_START+0, //U3 ++ E_INT_IRQ_AFEC = E_INT_IRQ_0x80_START+1, //T3 ++ E_INT_IRQ_DPTX = E_INT_IRQ_0x80_START+2, //T3 ++ E_INT_IRQ_TMDDRLINK = E_INT_IRQ_0x80_START+3, //T3 ++ E_INT_IRQ_DISPI = E_INT_IRQ_0x80_START+4, //T3 ++ E_INT_IRQ_EXP_MLINK = E_INT_IRQ_0x80_START+5, //T3 ++ E_INT_IRQ_M4VE = E_INT_IRQ_0x80_START+6, //T3 ++ E_INT_IRQ_DVI_HDMI_HDCP = E_INT_IRQ_0x80_START+7, //T3 ++ E_INT_IRQ_G3D2MCU = E_INT_IRQ_0x80_START+8, //T3 ++ E_INT_IRQ_VP6 = E_INT_IRQ_0x80_START+9, //A3 ++ //Not Used = E_INT_IRQ_0x80_START+10, ++ E_INT_IRQ_CEC = E_INT_IRQ_0x80_START+11, //T8 ++ E_INT_IRQ_HDCP_IIC = E_INT_IRQ_0x80_START+12, //T8 ++ E_INT_IRQ_HDCP_X74 = E_INT_IRQ_0x80_START+13, //T8 ++ E_INT_IRQ_WADR_ERR = E_INT_IRQ_0x80_START+14, //T8 ++ E_INT_IRQ_DCSUB = E_INT_IRQ_0x80_START+15, //T8 ++ E_INT_IRQ_0x80_END = 0x8F, ++ ++ E_INT_IRQ_0x90_START = 0x90, ++ E_INT_IRQ_GE = E_INT_IRQ_0x90_START+0, //T8 ++ E_INT_IRQ_SYNC_DET = E_INT_IRQ_0x90_START+1, //M10 ++ E_INT_IRQ_FSP = E_INT_IRQ_0x90_START+2, //M10 ++ E_INT_IRQ_PWM_RP_L = E_INT_IRQ_0x90_START+3, //M10 ++ E_INT_IRQ_PWM_FP_L = E_INT_IRQ_0x90_START+4, //M10 ++ E_INT_IRQ_PWM_RP_R = E_INT_IRQ_0x90_START+5, //M10 ++ E_INT_IRQ_PWM_FP_R = E_INT_IRQ_0x90_START+6, //M10 ++ E_INT_IRQ_FRC_SC = E_INT_IRQ_0x90_START+7, //A5 ++ E_INT_IRQ_FRC_INT_FIQ2HST0 = E_INT_IRQ_0x90_START+8, //A5 ++ E_INT_IRQ_SMART = E_INT_IRQ_0x90_START+9, //A5 ++ E_INT_IRQ_MVD2MIPS = E_INT_IRQ_0x90_START+10, //A5 ++ E_INT_IRQ_GPD = E_INT_IRQ_0x90_START+11, //A5 ++ //Not Used = E_INT_IRQ_0x90_START+12, //A5 ++ E_INT_IRQ_FRC_INT_IRQ2HST0 = E_INT_IRQ_0x90_START+13, //A5 ++ E_INT_IRQ_MIIC_DMA_INT3 = E_INT_IRQ_0x90_START+14, //A5 ++ E_INT_IRQ_MIIC_INT3 = E_INT_IRQ_0x90_START+15, //A5 ++ E_INT_IRQ_0x90_END = 0x9F, ++ ++ E_INT_IRQ_0xA0_START = 0xA0, ++ E_INT_IRQ_IIC2 = E_INT_IRQ_0xA0_START+0, //A1 ++ E_INT_IRQ_MIIC_DMA0 = E_INT_IRQ_0xA0_START+1, //A1 ++ E_INT_IRQ_MIIC_DMA1 = E_INT_IRQ_0xA0_START+2, //A1 ++ E_INT_IRQ_MIIC_DMA2 = E_INT_IRQ_0xA0_START+3, //A1 ++ E_INT_IRQ_MSPI0 = E_INT_IRQ_0xA0_START+4, //A1 ++ E_INT_IRQ_MSPI1 = E_INT_IRQ_0xA0_START+5, //A1 ++ E_INT_IRQ_EXT_GPIO0 = E_INT_IRQ_0xA0_START+6, //A1 ++ E_INT_IRQ_EXT_GPIO1 = E_INT_IRQ_0xA0_START+7, //A1 ++ E_INT_IRQ_EXT_GPIO2 = E_INT_IRQ_0xA0_START+8, //A1 ++ E_INT_IRQ_EXT_GPIO3 = E_INT_IRQ_0xA0_START+9, //A1 ++ E_INT_IRQ_EXT_GPIO4 = E_INT_IRQ_0xA0_START+10, //A1 ++ E_INT_IRQ_EXT_GPIO5 = E_INT_IRQ_0xA0_START+11, //A1 ++ E_INT_IRQ_EXT_GPIO6 = E_INT_IRQ_0xA0_START+12, //A1 ++ E_INT_IRQ_EXT_GPIO7 = E_INT_IRQ_0xA0_START+13, //A1 ++ E_INT_IRQ_MIIC_DMA_INT2 = E_INT_IRQ_0xA0_START+14, //A5 ++ E_INT_IRQ_MIIC_INT2 = E_INT_IRQ_0xA0_START+15, //A5 ++ E_INT_IRQ_0xA0_END = 0xAF, ++ ++ E_INT_IRQ_0xB0_START = 0xB0, ++ E_INT_IRQ_MIIC_DMA_INT1 = E_INT_IRQ_0xB0_START+0, //A5 ++ E_INT_IRQ_MIIC_INT1 = E_INT_IRQ_0xB0_START+1, //A5 ++ E_INT_IRQ_MIIC_DMA_INT0 = E_INT_IRQ_0xB0_START+2, //A5 ++ E_INT_IRQ_MIIC_INT0 = E_INT_IRQ_0xB0_START+3, //A5 ++ //Not Used = E_INT_IRQ_0xB0_START+4, ++ //Not Used = E_INT_IRQ_0xB0_START+5, ++ //Not Used = E_INT_IRQ_0xB0_START+6, ++ //Not Used = E_INT_IRQ_0xB0_START+7, ++ //Not Used = E_INT_IRQ_0xB0_START+8, ++ //Not Used = E_INT_IRQ_0xB0_START+9, ++ //Not Used = E_INT_IRQ_0xB0_START+10, ++ //Not Used = E_INT_IRQ_0xB0_START+11, ++ //Not Used = E_INT_IRQ_0xB0_START+12, ++ //Not Used = E_INT_IRQ_0xB0_START+13, ++ //Not Used = E_INT_IRQ_0xB0_START+14, ++ //Not Used = E_INT_IRQ_0xB0_START+15, ++ E_INT_IRQ_0xB0_END = 0xBF, ++ ++ ++ // Add FIQ from 0xC0 ~ 0xFD, ++ // if FIQ enum from 0x20 ~ 0x4F, and 0x60 ~ 0x7F is occupied ++ E_INT_FIQ_0xC0_START = 0xC0, ++ E_INT_FIQ_DMARD = E_INT_FIQ_0xC0_START+0, //U3 ++ E_INT_FIQ_AU_DMA_BUF_INT = E_INT_FIQ_0xC0_START+1, //T3 ++ E_INT_FIQ_8051_TO_MIPS_VPE1 = E_INT_FIQ_0xC0_START+2, //T3 ++ E_INT_FIQ_DVI_DET = E_INT_FIQ_0xC0_START+3, //M10 ++ E_INT_FIQ_PM_GPIO0 = E_INT_FIQ_0xC0_START+4, //M10 ++ E_INT_FIQ_PM_GPIO1 = E_INT_FIQ_0xC0_START+5, //M10 ++ E_INT_FIQ_PM_GPIO2 = E_INT_FIQ_0xC0_START+6, //M10 ++ E_INT_FIQ_PM_GPIO3 = E_INT_FIQ_0xC0_START+7, //M10 ++ E_INT_FIQ_PM_XIU_TIMEOUT = E_INT_FIQ_0xC0_START+8, //M10 ++ E_INT_FIQ_PWM_RP_RP_L = E_INT_FIQ_0xC0_START+9, //M10 ++ E_INT_FIQ_PWM_RP_FP_L = E_INT_FIQ_0xC0_START+10, //M10 ++ E_INT_FIQ_PWM_RP_RP_R = E_INT_FIQ_0xC0_START+11, //M10 ++ E_INT_FIQ_PWM_RP_FP_R = E_INT_FIQ_0xC0_START+12, //M10 ++ E_INT_FIQ_8051_TO_MIPS_VPE0 = E_INT_FIQ_0xC0_START+13, //A5 ++ E_INT_FIQ_FRC_R2_TO_MIPS = E_INT_FIQ_0xC0_START+14, ++ E_INT_FIQ_VP6 = E_INT_FIQ_0xC0_START+15, //A3 ++ E_INT_FIQ_0xC0_END = 0xCF, ++ ++ E_INT_FIQ_0xD0_START = 0xD0, ++ E_INT_FIQ_STRETCH = E_INT_FIQ_0xD0_START+0, ++ E_INT_FIQ_GPIO0 = E_INT_FIQ_0xD0_START+1, //T12 ++ E_INT_FIQ_GPIO1 = E_INT_FIQ_0xD0_START+2, //T12 ++ E_INT_FIQ_GPIO2 = E_INT_FIQ_0xD0_START+3, //T12 ++ E_INT_FIQ_GPIO3 = E_INT_FIQ_0xD0_START+4, //T12 ++ E_INT_FIQ_GPIO4 = E_INT_FIQ_0xD0_START+5, //T12 ++ E_INT_FIQ_GPIO5 = E_INT_FIQ_0xD0_START+6, //T12 ++ E_INT_FIQ_GPIO6 = E_INT_FIQ_0xD0_START+7, //T12 ++ E_INT_FIQ_GPIO7 = E_INT_FIQ_0xD0_START+8, //T12 ++ //Not Used = E_INT_FIQ_0xD0_START+9, ++ //Not Used = E_INT_FIQ_0xD0_START+10, ++ //Not Used = E_INT_FIQ_0xD0_START+11, ++ //Not Used = E_INT_FIQ_0xD0_START+12, ++ //Not Used = E_INT_FIQ_0xD0_START+13, ++ //Not Used = E_INT_FIQ_0xD0_START+14, ++ //Not Used = E_INT_FIQ_0xD0_START+15, ++ E_INT_FIQ_0xD0_END = 0xDF, ++ ++ E_INT_FIQ_0xE0_START = 0xE0, ++ E_INT_FIQ_LDM_DMA0 = E_INT_FIQ_0xE0_START+0, //A1 ++ E_INT_FIQ_LDM_DMA1 = E_INT_FIQ_0xE0_START+1, //A1 ++ E_INT_IRQ_SDIO = E_INT_FIQ_0xE0_START+2, //K2 ++ E_INT_IRQ_UHC3 = E_INT_FIQ_0xE0_START+3, //K2 ++ E_INT_IRQ_USB3 = E_INT_FIQ_0xE0_START+4, //K2 ++ //Not Used = E_INT_FIQ_0xE0_START+2, ++ //Not Used = E_INT_FIQ_0xE0_START+3, ++ //Not Used = E_INT_FIQ_0xE0_START+4, ++ //Not Used = E_INT_FIQ_0xE0_START+5, ++ //Not Used = E_INT_FIQ_0xE0_START+6, ++ //Not Used = E_INT_FIQ_0xE0_START+7, ++ //Not Used = E_INT_FIQ_0xE0_START+8, ++ //Not Used = E_INT_FIQ_0xE0_START+9, ++ //Not Used = E_INT_FIQ_0xE0_START+10, ++ //Not Used = E_INT_FIQ_0xE0_START+11, ++ //Not Used = E_INT_FIQ_0xE0_START+12, ++ //Not Used = E_INT_FIQ_0xE0_START+13, ++ //Not Used = E_INT_FIQ_0xE0_START+14, ++ //Not Used = E_INT_FIQ_0xE0_START+15, ++ E_INT_FIQ_0xE0_END = 0xEF, ++ ++ E_INT_FIQ_0xF0_START = 0xF0, ++ E_INT_FIQ_DEC_DSP2R2M = E_INT_FIQ_0xF0_START + 0, ++ E_INT_FIQ_AEON_TO_R2M = E_INT_FIQ_0xF0_START + 1, ++ E_INT_FIQ_R2M_TO_AEON = E_INT_FIQ_0xF0_START + 2, ++ E_INT_FIQ_R2M_TO_8051 = E_INT_FIQ_0xF0_START + 3, ++ E_INT_IRQ_VIVALDI_DMA_INTR2 = E_INT_FIQ_0xF0_START + 4, ++ E_INT_IRQ_VIVALDI_DMA_INTR1 = E_INT_FIQ_0xF0_START + 5, ++ E_INT_IRQ_AFEC_INT = E_INT_FIQ_0xF0_START + 6, ++ E_INT_IRQ_FRM_PM = E_INT_FIQ_0xF0_START + 11, ++ E_INT_FIQ_FRM_PM = E_INT_FIQ_0xF0_START + 12, ++ //Not Used = E_INT_FIQ_0xF0_START+0, ++ //Not Used = E_INT_FIQ_0xF0_START+1, ++ //Not Used = E_INT_FIQ_0xF0_START+2, ++ //Not Used = E_INT_FIQ_0xF0_START+3, ++ //Not Used = E_INT_FIQ_0xF0_START+4, ++ //Not Used = E_INT_FIQ_0xF0_START+5, ++ //Not Used = E_INT_FIQ_0xF0_START+6, ++ //Not Used = E_INT_FIQ_0xF0_START+7, ++ //Not Used = E_INT_FIQ_0xF0_START+8, ++ //Not Used = E_INT_FIQ_0xF0_START+9, ++ //Not Used = E_INT_FIQ_0xF0_START+10, ++ //Not Used = E_INT_FIQ_0xF0_START+11, ++ //Not Used = E_INT_FIQ_0xF0_START+12, ++ //Not Used = E_INT_FIQ_0xF0_START+13, ++ E_INT_IRQ_FIQ_NONE = E_INT_FIQ_0xF0_START+14, ++ E_INT_IRQ_FIQ_ALL = E_INT_FIQ_0xF0_START+15, ++ E_INT_FIQ_0xF0_END = 0xFF, ++ ++} InterruptNum; ++ ++ ++typedef enum ++{ ++ // IRQ ++ E_FRCINT_IRQ_0x00_START = 0x00, ++ E_FRCINT_IRQ_0x00_END = 0x0F, ++ ++ E_FRCINT_IRQ_0x10_START = 0x10, ++ E_FRCINT_IRQ_FRC_XIU_TIMEOUT = E_FRCINT_IRQ_0x10_START+5, ++ E_FRCINT_IRQ_PWM_RP_L = E_FRCINT_IRQ_0x10_START+6, ++ E_FRCINT_IRQ_PWM_FP_L = E_FRCINT_IRQ_0x10_START+7, ++ E_FRCINT_IRQ_PWM_RP_R = E_FRCINT_IRQ_0x10_START+8, ++ E_FRCINT_IRQ_PWM_FP_R = E_FRCINT_IRQ_0x10_START+9, ++ E_FRCINT_IRQ_SC = E_FRCINT_IRQ_0x10_START+10, ++ E_FRCINT_IRQ_D2B = E_FRCINT_IRQ_0x10_START+11, ++ E_FRCINT_IRQ_MSPI1 = E_FRCINT_IRQ_0x10_START+14, ++ E_FRCINT_IRQ_MSPI0 = E_FRCINT_IRQ_0x10_START+15, ++ E_FRCINT_IRQ_0x10_END = 0x1F, ++ ++ // FIQ ++ E_FRCINT_FIQ_0x20_START = 0x20, ++ E_FRCINT_FIQ_MIPS_TO_FRCR2 = E_FRCINT_FIQ_0x20_START+0, ++ E_FRCINT_FIQ_FRCR2_TO_MIPS = E_FRCINT_FIQ_0x20_START+4, ++ E_FRCINT_FIQ_0x20_END = 0x2F, ++ ++ E_FRCINT_FIQ_0x30_START = 0x30, ++ E_FRCINT_FIQ_PWM_RP_L = E_FRCINT_FIQ_0x30_START+6, ++ E_FRCINT_FIQ_PWM_FP_L = E_FRCINT_FIQ_0x30_START+7, ++ E_FRCINT_FIQ_PWM_RP_R = E_FRCINT_FIQ_0x30_START+8, ++ E_FRCINT_FIQ_PWM_FP_R = E_FRCINT_FIQ_0x30_START+9, ++ E_FRCINT_FIQ_LDM_DMA_DONE1 = E_FRCINT_FIQ_0x30_START+12, ++ E_FRCINT_FIQ_LDM_DMA_DONE0 = E_FRCINT_FIQ_0x30_START+13, ++ E_FRCINT_FIQ_SC = E_FRCINT_FIQ_0x30_START+14, ++ E_FRCINT_FIQ_OP2_VS = E_FRCINT_FIQ_0x30_START+15, ++ E_FRCINT_FIQ_0x30_END = 0x3F, ++ ++ // END ++ E_FRCINT_FIQ_0xF0_START = 0xF0, ++ E_FRCINT_IRQ_FIQ_NONE = E_FRCINT_FIQ_0xF0_START+14, ++ E_FRCINT_IRQ_FIQ_ALL = E_FRCINT_FIQ_0xF0_START+15, ++ E_FRCINT_FIQ_0xF0_END = 0xFF, ++ ++} InterruptNum_Frc; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _MS_IRQ_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/include/MsTypes.h b/drivers/mstar/scl/infinity/src/mxlib/include/MsTypes.h +new file mode 100644 +index 00000000..1dd8dbf9 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/include/MsTypes.h +@@ -0,0 +1,232 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsTypes.h ++/// @brief MStar General Data Types ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_TYPES_H_ ++#define _MS_TYPES_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#if !defined(BIT0) && !defined(BIT1) ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++//[TODO] use MS_U8, ... instead ++// data type for 8051 code ++//typedef MS_U16 WORD; ++//typedef MS_U8 BYTE; ++ ++ ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++ ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++///Define MS FB Format, to share with GE,GOP ++/// FIXME THE NAME NEED TO BE REFINED, AND MUST REMOVE UNNESSARY FMT ++typedef enum ++{ ++ /// color format I1 ++ E_MS_FMT_I1 = 0x0, ++ /// color format I2 ++ E_MS_FMT_I2 = 0x1, ++ /// color format I4 ++ E_MS_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ E_MS_FMT_I8 = 0x4, ++ /// color format blinking display ++ E_MS_FMT_FaBaFgBg2266 = 0x6, ++ /// color format for blinking display format ++ E_MS_FMT_1ABFgBg12355 = 0x7, ++ /// color format RGB565 ++ E_MS_FMT_RGB565 = 0x8, ++ /// color format ARGB1555 ++ /// @note [URANUS] ARGB1555 is only RGB555 ++ E_MS_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ E_MS_FMT_ARGB4444 = 0xa, ++ /// color format ARGB1555 DST ++ E_MS_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ E_MS_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ E_MS_FMT_ARGB8888 = 0xf, ++ /// color format RGBA5551 ++ E_MS_FMT_RGBA5551 = 0x10, ++ /// color format RGBA4444 ++ E_MS_FMT_RGBA4444 = 0x11, ++ /// color format ABGR8888 ++ E_MS_FMT_ABGR8888 = 0x1f, ++ ++ E_MS_FMT_GENERIC = 0xFFFF, ++ ++} MS_ColorFormat; ++ ++ ++typedef union _MSIF_Version ++{ ++ struct _DDI ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 model; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 change[8]; ++ MS_U8 os; ++ } MS_DDI; ++ struct _MW ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 mod; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 changelist[8]; ++ MS_U8 os; ++ } MW; ++ struct _APP ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U8 id[4]; ++ MS_U8 quality; ++ MS_U8 version[4]; ++ MS_U8 time[6]; ++ MS_U8 changelist[8]; ++ MS_U8 reserve[3]; ++ } APP; ++} MSIF_Version; ++ ++typedef struct _MS_SW_VERSION_INFO ++{ ++ char UtopiaBspVersion[8]; //Utopia BSP Version ++ char MajorVersion[4]; //Major Version Number ++ char MinorVersion[4]; //Minor Version Number ++ char ChangeList_API[16]; //Sync Perforce Change List Number in API Folder ++ char ChangeList_DRV[16]; //Sync Perforce Change List Number in DRV Folder ++ char ChangeList_HAL[16]; //Sync Perforce Change List Number in HAL Folder ++ ++} MS_SW_VERSION_INFO; ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/include/MsVersion.h b/drivers/mstar/scl/infinity/src/mxlib/include/MsVersion.h +new file mode 100644 +index 00000000..1d2a7651 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/include/MsVersion.h +@@ -0,0 +1,118 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file MsVersion.h ++/// @brief MStar DDI Version Def ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_VERSION_H_ ++#define _MS_VERSION_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Version String Definition ++//------------------------------------------------------------------------------------------------- ++#define MSIF_TAG {'M','S','I','F'} // MSIF ++#define MSIF_CLASS {'0','0'} // DRV/API (DDI) ++#define MSIF_CUS 0x0000 // MStar Common library ++#define MSIF_MOD 0x0000 // MStar Common library ++#define MSIF_CHIP 0x000F ++#define MSIF_CPU '1' ++#define MSIF_OS '2' ++ ++ ++#endif // _MS_VERSION_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/msos/MsOS.c b/drivers/mstar/scl/infinity/src/mxlib/msos/MsOS.c +new file mode 100644 +index 00000000..3e1ab51a +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/msos/MsOS.c +@@ -0,0 +1,1350 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (?œMStar Confidential Information?? by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/// ++ ++#define MS_OS_C ++ ++/******************************************************************************/ ++/* Header Files */ ++/* ****************************************************************************/ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsIRQ.h" ++#include "MsOS.h" ++#include "halCHIP.h" ++ ++ ++/********************************************************************************/ ++/* Macro */ ++/********************************************************************************/ ++#define MSOS_MUTEX_USE_SEM ++ ++#define MSOS_ID_PREFIX 0x76540000 ++#define MSOS_ID_PREFIX_MASK 0xFFFF0000 ++#define MSOS_ID_MASK 0x0000FFFF //~MSOS_ID_PREFIX_MASK ++ ++#define HAS_FLAG(flag, bit) ((flag) & (bit)) ++#define SET_FLAG(flag, bit) ((flag)|= (bit)) ++#define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) ++ ++ ++#ifndef MIN ++#define MIN(a, b) (((a) < (b)) ? (a) : (b)) ++#endif // #ifndef MIN ++ ++#ifndef MAX ++#define MAX(a, b) (((a) > (b)) ? (a) : (b)) ++#endif ++ ++#ifdef MSOS_MEMPOOL_MAX ++#undef MSOS_MEMPOOL_MAX ++#define MSOS_MEMPOOL_MAX 2 ++#endif // #ifdef MSOS_MEMPOOL_MAX ++ ++ ++ ++/********************************************************************************/ ++/* Constant */ ++/********************************************************************************/ ++ ++ ++/******************************************************************************/ ++/* Enum */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************/ ++/* Global Variables */ ++/******************************************************************************/ ++// ++// Mutex ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++#ifdef MSOS_MUTEX_USE_SEM ++ struct semaphore stMutex; ++#else ++ spinlock_t stMutex; ++#endif ++ MS_U8 u8Name[MAX_MUTEX_NAME_LENGTH]; ++} MsOS_Mutex_Info; ++typedef struct ++{ ++ MS_BOOL bUsed; ++ spinlock_t stMutex; ++ MS_U8 u8Name[MAX_MUTEX_NAME_LENGTH]; ++} MsOS_Spinlock_Info; ++ ++static MsOS_Mutex_Info _MsOS_Mutex_Info[MSOS_MUTEX_MAX]; ++static MsOS_Spinlock_Info _MsOS_Spinlock_Info[MSOS_SPINLOCK_MAX]; ++ ++static DEFINE_SPINLOCK(_MsOS_Mutex_Mutex); ++#define MUTEX_MUTEX_LOCK() spin_lock(&_MsOS_Mutex_Mutex) ++#define MUTEX_MUTEX_UNLOCK() spin_unlock(&_MsOS_Mutex_Mutex) ++ ++// ++// Task Management ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++ struct task_struct* pstThreadInfo; ++} MsOS_Task_Info; ++ ++static MsOS_Task_Info _MsOS_Task_Info[MSOS_TASK_MAX]; ++ ++#ifdef MSOS_MUTEX_USE_SEM ++struct semaphore _MsOS_Task_Mutex; ++#define MUTEX_TASK_LOCK() down(&_MsOS_Task_Mutex) ++#define MUTEX_TASK_UNLOCK() up(&_MsOS_Task_Mutex) ++#else ++static DEFINE_SPINLOCK(_MsOS_Task_Mutex); ++#define MUTEX_TASK_LOCK() spin_lock(&_MsOS_Task_Mutex) ++#define MUTEX_TASK_UNLOCK() spin_unlock(&_MsOS_Task_Mutex) ++#endif ++ ++// ++// Event Group ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++ MS_U32 u32EventGroup; ++ spinlock_t stMutexEvent; ++ wait_queue_head_t stSemaphore; ++ // pthread_cond_t stSemaphore; // ????????????? ++} MsOS_EventGroup_Info; ++ ++static MsOS_EventGroup_Info _MsOS_EventGroup_Info[MSOS_EVENTGROUP_MAX]; ++static DEFINE_SPINLOCK(_MsOS_EventGroup_Mutex); ++#define EVENT_MUTEX_LOCK() spin_lock(&_MsOS_EventGroup_Mutex) ++#define EVENT_MUTEX_UNLOCK() spin_unlock(&_MsOS_EventGroup_Mutex) ++ ++ ++// Timer ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++ TimerCb pTimerCb; ++ struct timer_list timer; ++ int period; ++ int first; ++} MsOS_Timer_Info; ++static MsOS_Timer_Info _MsOS_Timer_Info[MSOS_TIMER_MAX]; ++static DEFINE_SPINLOCK(_MsOS_Timer_Mutex); ++#define TIMER_MUTEX_LOCK() spin_lock(&_MsOS_Timer_Mutex) ++#define TIMER_MUTEX_UNLOCK() spin_unlock(&_MsOS_Timer_Mutex) ++ ++/******************************************************************************/ ++/* Local Variables */ ++/******************************************************************************/ ++ ++/******************************************************************************/ ++/* P r i v a t e F u n c t i o n s */ ++/******************************************************************************/ ++void MsOS_SetPollWait(void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ poll_wait((struct file *)filp, (wait_queue_head_t *)pWaitQueueHead, (struct poll_table_struct *)pstPollQueue); ++} ++MS_U32 MsOS_GetSystemTime (void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++} ++MS_U64 MsOS_GetSystemTimeStamp (void) ++{ ++ struct timeval tv; ++ MS_U64 u64TimeStamp; ++ do_gettimeofday(&tv); ++ u64TimeStamp =(MS_U64)tv.tv_sec* 1000000ULL+ (MS_U64)tv.tv_usec; ++ return u64TimeStamp; ++} ++ ++MS_U32 MsOS_Timer_DiffTimeFromNow(MS_U32 u32TaskTimer) //unit = ms ++{ ++ return (MsOS_GetSystemTime() - u32TaskTimer); ++} ++ ++void MsOS_DelayTask (MS_U32 u32Ms) ++{ ++ //sleep in spinlock will cause deadlock ++#ifdef MSOS_MUTEX_USE_SEM ++ msleep_interruptible((unsigned int)u32Ms); ++#else ++ mdelay(u32Ms); ++#endif ++} ++ ++ ++void MsOS_DelayTaskUs (MS_U32 u32Us) ++{ ++ struct timespec TS1, TS2; ++ getnstimeofday(&TS1); ++ getnstimeofday(&TS2); ++ ++ while((TS2.tv_nsec - TS1.tv_nsec)< (u32Us * 1000UL)) ++ { ++ getnstimeofday(&TS2); ++ } ++#if 0 ++ struct timespec req, rem; ++ ++ req.tv_sec = 0; ++ req.tv_nsec = (long) (u32Us*1000UL); ++ ++ while(1) ++ { ++ int err; ++ ++ err = nanosleep(&req, &rem); ++ if(err==-1) ++ { ++ #if 0 ++ switch(errno) ++ { ++ case EINTR: ++ req.tv_sec = rem.tv_sec; ++ req.tv_nsec = rem.tv_nsec; ++ continue; ++ default: ++ printk("nanosleep is interrupted: %d\n", errno); ++ } ++ #endif ++ } ++ ++ break; ++ } ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// ++// Interrupt management ++// ++//------------------------------------------------------------------------------------------------- ++/// Attach the interrupt callback function to interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @param pIntCb \b IN: Interrupt callback function ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_AttachInterrupt (InterruptNum eIntNum, InterruptCb pIntCb,unsigned long flags,const char *name) ++{ ++ int i; ++ i = request_irq(eIntNum, (irq_handler_t)pIntCb, flags, name, NULL); ++ ++ return i; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Detach the interrupt callback function from interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DetachInterrupt (InterruptNum eIntNum) ++{ ++ // PTH_RET_CHK(pthread_mutex_lock(&_ISR_Mutex)); ++ //HAL_IRQ_Detech((int)eIntNum); TODo!! ++ // PTH_RET_CHK(pthread_mutex_unlock(&_ISR_Mutex)); ++ free_irq(eIntNum, NULL); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable (unmask) the interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_EnableInterrupt (InterruptNum eIntNum) ++{ ++ enable_irq((int)eIntNum); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Disable (mask) the interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @return TRUE : succeed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DisableInterrupt (InterruptNum eIntNum) ++{ ++ disable_irq((int)eIntNum); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Disable all interrupts (including timer interrupt), the scheduler is disabled. ++/// @return Interrupt register value before all interrupts disable ++//------------------------------------------------------------------------------------------------- ++MS_U32 MsOS_DisableAllInterrupts(void) ++{ ++#if 0 ++ return CHIP_DisableAllInterrupt() ; ++#else ++ return 0; ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Restore the interrupts from last MsOS_DisableAllInterrupts. ++/// @param u32OldInterrupts \b IN: Interrupt register value from @ref MsOS_DisableAllInterrupts ++/// @return TRUE : succeed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_RestoreAllInterrupts(MS_U32 u32OldInterrupts) ++{ ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Enable all CPU interrupts. ++/// @return TRUE : succeed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_EnableAllInterrupts(void) ++{ ++#if 0 ++ return CHIP_EnableAllInterrupt() ; ++#else ++ return TRUE; ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// In Interuupt Context or not ++/// @return TRUE : Yes ++/// @return FALSE : No ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_In_Interrupt (void) ++{ ++#if 0 ++ return CHIP_InISRContext(); ++#else ++ return FALSE; ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++ ++// ++// Mutex ++// ++//------------------------------------------------------------------------------------------------- ++/// Create a mutex in the unlocked state ++/// @param eAttribute \b IN: E_MSOS_FIFO: suspended in FIFO order ++/// @param pMutexName \b IN: mutex name ++/// @param u32Flag \b IN: process data shared flag ++/// @return >=0 : assigned mutex Id ++/// @return <0 : fail ++/// @note A mutex has the concept of an owner, whereas a semaphore does not. ++/// A mutex provides priority inheritance protocol against proiorty inversion, whereas a binary semaphore does not. ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_CreateMutex ( MsOSAttribute eAttribute, char *pMutexName1, MS_U32 u32Flag) ++{ ++ MS_S32 s32Id, s32LstUnused = MSOS_MUTEX_MAX; ++ MS_U8 pMutexName[MAX_MUTEX_NAME_LENGTH]; ++ MS_U32 u32MaxLen; ++ ++ if (NULL == pMutexName1) ++ { ++ return -1; ++ } ++ if (strlen(pMutexName1) >= (MAX_MUTEX_NAME_LENGTH-1)) ++ { ++ printk("%s: Warning strlen(%s) is longer than MAX_MUTEX_NAME_LENGTH(%d). Oversize char will be discard.\n", ++ __FUNCTION__,pMutexName1,MAX_MUTEX_NAME_LENGTH); ++ } ++ if (0 == (u32MaxLen = MIN(strlen(pMutexName1), (MAX_MUTEX_NAME_LENGTH-1)))) ++ { ++ return -1; ++ } ++ strncpy((char*)pMutexName, (const char*)pMutexName1, u32MaxLen); ++ pMutexName[u32MaxLen] = '\0'; ++ ++ MUTEX_MUTEX_LOCK(); ++ for(s32Id=0;s32Ids32LstUnused)) ++ { ++ _MsOS_Mutex_Info[s32LstUnused].bUsed = TRUE; ++ strcpy((char*)_MsOS_Mutex_Info[s32LstUnused].u8Name, (const char*)pMutexName); ++#ifdef MSOS_MUTEX_USE_SEM ++ sema_init(&_MsOS_Mutex_Info[s32LstUnused].stMutex, 1); ++#else ++ spin_lock_init(&_MsOS_Mutex_Info[s32LstUnused].stMutex); ++#endif ++ s32Id = s32LstUnused; ++ } ++ MUTEX_MUTEX_UNLOCK(); ++ ++ if(MSOS_MUTEX_MAX <= s32Id) ++ { ++ return -1; ++ } ++ ++ s32Id |= MSOS_ID_PREFIX; ++ ++ return s32Id; ++} ++MS_S32 MsOS_CreateSpinlock ( MsOSAttribute eAttribute, char *pMutexName1, MS_U32 u32Flag) ++{ ++ MS_S32 s32Id, s32LstUnused = MSOS_SPINLOCK_MAX; ++ MS_U8 pMutexName[MAX_MUTEX_NAME_LENGTH]; ++ MS_U32 u32MaxLen; ++ ++ if (NULL == pMutexName1) ++ { ++ return -1; ++ } ++ if (strlen(pMutexName1) >= (MAX_MUTEX_NAME_LENGTH-1)) ++ { ++ printk("%s: Warning strlen(%s) is longer than MAX_MUTEX_NAME_LENGTH(%d). Oversize char will be discard.\n", ++ __FUNCTION__,pMutexName1,MAX_MUTEX_NAME_LENGTH); ++ } ++ if (0 == (u32MaxLen = MIN(strlen(pMutexName1), (MAX_MUTEX_NAME_LENGTH-1)))) ++ { ++ return -1; ++ } ++ strncpy((char*)pMutexName, (const char*)pMutexName1, u32MaxLen); ++ pMutexName[u32MaxLen] = '\0'; ++ ++ MUTEX_MUTEX_LOCK(); ++ for(s32Id=0;s32Ids32LstUnused)) ++ { ++ _MsOS_Spinlock_Info[s32LstUnused].bUsed = TRUE; ++ strcpy((char*)_MsOS_Spinlock_Info[s32LstUnused].u8Name, (const char*)pMutexName); ++ spin_lock_init(&_MsOS_Spinlock_Info[s32LstUnused].stMutex); ++ s32Id = s32LstUnused; ++ } ++ MUTEX_MUTEX_UNLOCK(); ++ ++ if(MSOS_SPINLOCK_MAX <= s32Id) ++ { ++ return -1; ++ } ++ ++ s32Id |= MSOS_ID_PREFIX; ++ ++ return s32Id; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete the specified mutex ++/// @param s32MutexId \b IN: mutex ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++/// @note It is important that the mutex be in the unlocked state when it is ++/// destroyed, or else the behavior is undefined. ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteMutex (MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ MUTEX_MUTEX_LOCK(); ++ ++ MS_ASSERT(_MsOS_Mutex_Info[s32MutexId].bUsed); ++ _MsOS_Mutex_Info[s32MutexId].bUsed = FALSE; ++ _MsOS_Mutex_Info[s32MutexId].u8Name[0] = '\0'; ++ ++ MUTEX_MUTEX_UNLOCK(); ++ return TRUE; ++} ++MS_BOOL MsOS_DeleteSpinlock (MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ MUTEX_MUTEX_LOCK(); ++ ++ MS_ASSERT(_MsOS_Spinlock_Info[s32MutexId].bUsed); ++ _MsOS_Spinlock_Info[s32MutexId].bUsed = FALSE; ++ _MsOS_Spinlock_Info[s32MutexId].u8Name[0] = '\0'; ++ ++ MUTEX_MUTEX_UNLOCK(); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Attempt to lock a mutex ++/// @param s32MutexId \b IN: mutex ID ++/// @param u32WaitMs \b IN: 0 ~ MSOS_WAIT_FOREVER: suspend time (ms) if the mutex is locked ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++// @FIXME: don't support time-out at this stage ++MS_BOOL MsOS_ObtainMutex_IRQ(MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ spin_lock_irq(&(_MsOS_Spinlock_Info[s32MutexId].stMutex)); ++ return TRUE; ++} ++MS_BOOL MsOS_ObtainMutex (MS_S32 s32MutexId, MS_U32 u32WaitMs) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ ++ if (u32WaitMs==MSOS_WAIT_FOREVER) //blocking wait ++ { ++#ifdef MSOS_MUTEX_USE_SEM ++ down(&(_MsOS_Mutex_Info[s32MutexId].stMutex)); ++#else ++ spin_lock(&(_MsOS_Mutex_Info[s32MutexId].stMutex)); ++#endif ++ bRet = TRUE; ++ } ++ else if (u32WaitMs==0) //non-blocking ++ { ++#ifdef MSOS_MUTEX_USE_SEM ++ if (!down_trylock(&_MsOS_Mutex_Info[s32MutexId].stMutex)) ++#else ++ if (spin_trylock(&_MsOS_Mutex_Info[s32MutexId].stMutex)) ++#endif ++ { ++ bRet = TRUE; ++ } ++ } ++ else //blocking wait with timeout ++ { ++#ifndef MSOS_MUTEX_USE_SEM ++ MS_U32 u32CurTime = MsOS_GetSystemTime(); ++#endif ++ ++ while(1) ++ { ++#ifdef MSOS_MUTEX_USE_SEM ++ if (0 == down_timeout(&_MsOS_Mutex_Info[s32MutexId].stMutex, msecs_to_jiffies(u32WaitMs))) ++#else ++ if (spin_trylock(&_MsOS_Mutex_Info[s32MutexId].stMutex)) ++#endif ++ { ++ bRet = TRUE; ++ break; ++ } ++#ifdef MSOS_MUTEX_USE_SEM ++ else ++#else ++ else if((MsOS_GetSystemTime() - u32CurTime) > u32WaitMs) ++#endif ++ { ++ printf("Mutext TimeOut: ID:%x \n", (int)s32MutexId); ++ bRet = FALSE; ++ break; ++ } ++ ++ // msleep(5); ++ } ++ ++ } ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Attempt to unlock a mutex ++/// @param s32MutexId \b IN: mutex ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++/// @note Only the owner thread of the mutex can unlock it. ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_ReleaseMutex_IRQ (MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ if(spin_is_locked(&(_MsOS_Spinlock_Info[s32MutexId].stMutex))) ++ { ++ spin_unlock_irq(&(_MsOS_Spinlock_Info[s32MutexId].stMutex)); ++ } ++ return TRUE; ++ ++} ++MS_BOOL MsOS_ReleaseMutex (MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++#ifdef MSOS_MUTEX_USE_SEM ++ up(&(_MsOS_Mutex_Info[s32MutexId].stMutex)); ++#else ++ spin_unlock(&(_MsOS_Mutex_Info[s32MutexId].stMutex)); ++#endif ++ ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Get a mutex informaton ++// @param s32MutexId \b IN: mutex ID ++// @param peAttribute \b OUT: ptr to suspended mode: E_MSOS_FIFO / E_MSOS_PRIORITY ++// @param pMutexName \b OUT: ptr to mutex name ++// @return TRUE : succeed ++// @return FALSE : the mutex has not been created. ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_InfoMutex (MS_S32 s32MutexId, MsOSAttribute *peAttribute, char *pMutexName) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ ++ if(_MsOS_Mutex_Info[s32MutexId].bUsed == TRUE) ++ { ++ //ToDo: extend _MsOS_Mutex_Info structure ? ++ *peAttribute = E_MSOS_FIFO; //only FIFO for eCos ++ // @FIXME: linux porting ++ // UTL_strcpy(pMutexName, "ABC"); ++ strcpy(pMutexName, (const char*)_MsOS_Mutex_Info[s32MutexId].u8Name); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++ ++ ++MS_U32 MsOS_PA2KSEG1_1(MS_U32 addr) ++{ ++ ++ // miu0 ++ if ((0x00000000 <= addr) && (HAL_MIU1_BASE > addr)) ++ { ++ return ((MS_U32)(addr) | (0x40000000)); ++ } ++ // miu1 ++ if ((HAL_MIU1_BASE <= addr) && (((MS_U64)HAL_MIU1_BASE * 2) > (MS_U64)addr)) ++ { ++ return ((addr & ~(HAL_MIU1_BASE)) | 0xD0000000); ++ } ++ return 0; ++} ++ ++ ++void MsOS_FlushMemory(void) ++{ ++ ++} ++ ++ ++void MsOS_ReadMemory(void) ++{ ++ ++} ++ ++// ++// Task ++// ++//------------------------------------------------------------------------------------------------- ++/// Create a task ++/// @param pTaskEntry \b IN: task entry point ++/// @param u32TaskEntryData \b IN: task entry data: a pointer to some static data, or a ++/// small integer, or NULL if the task does not require any additional data. ++/// @param eTaskPriority \b IN: task priority ++/// @param bAutoStart \b IN: start immediately or later ++/// @param pStackBase \b IN: task stack ++/// @param u32StackSize \b IN: stack size ++/// @param pTaskName \b IN: task name ++/// @return >=0 : assigned Task ID ++/// @return < 0 : fail ++//------------------------------------------------------------------------------------------------- ++MSOS_ST_TASKSTRUCT MsOS_GetTaskinfo(MS_S32 s32Id) ++{ ++ MSOS_ST_TASKSTRUCT stTask; ++ stTask.pThread = _MsOS_Task_Info[(s32Id&0xFFFF)].pstThreadInfo; ++ return stTask; ++} ++void MsOS_SetUserNice(MSOS_ST_TASKSTRUCT stTask, long nice) ++{ ++ set_user_nice(stTask.pThread,nice); ++} ++int MsOS_GetUserNice(MSOS_ST_TASKSTRUCT stTask) ++{ ++ return (int)task_nice(stTask.pThread); ++} ++ ++MS_S32 MsOS_CreateTask (TaskEntry pTaskEntry, ++ MS_U32 u32TaskEntryData, ++ MS_BOOL bAutoStart, ++ char *pTaskName) ++{ ++ // @FIXME: ++ // (1) eTaskPriority: Task priority is ignored here ++ // (2) pTaskName: is ignored here ++ // (3) Need mutex to protect critical section ++ ++ MS_S32 s32Id; ++ ++ MUTEX_TASK_LOCK(); ++ ++ for( s32Id=0; s32Id= MSOS_TASK_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_Task_Info[s32Id].bUsed = TRUE; ++ //_MsOS_Task_Info[s32Id].pstThreadInfo = kthread_create(((int)(void *)pTaskEntry), (void*)u32TaskEntryData, pTaskName); ++ _MsOS_Task_Info[s32Id].pstThreadInfo = kthread_create(pTaskEntry, (void*)u32TaskEntryData, pTaskName); ++ ++ MUTEX_TASK_UNLOCK(); ++ ++ if (bAutoStart) ++ { ++ wake_up_process(_MsOS_Task_Info[s32Id].pstThreadInfo); ++ } ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete a previously created task ++/// @param s32TaskId \b IN: task ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteTask (MS_S32 s32TaskId) ++{ ++#if 1 ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ ++ kthread_stop(_MsOS_Task_Info[s32TaskId].pstThreadInfo); ++ _MsOS_Task_Info[s32TaskId].bUsed = FALSE; ++#else ++ printk("[%s][%d] %s is not supported\n", __FUNCTION__, __LINE__, __FUNCTION__); ++#endif ++ return TRUE; ++} ++ ++ ++ ++MS_BOOL MsOS_Init (void) ++{ ++ MS_U32 u32I; ++ static MS_BOOL bInit = FALSE; ++ ++ if(bInit) ++ { ++ return TRUE; ++ } ++ // ++ // Task Management ++ // ++#ifdef MSOS_MUTEX_USE_SEM ++ sema_init(&_MsOS_Task_Mutex, 1); ++#else ++ spin_lock_init(&_MsOS_Task_Mutex); ++#endif ++ for( u32I=0; u32I=0 : assigned Event Id ++/// @return <0 : fail ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_CreateEventGroup (char *pEventName) ++{ ++ MS_S32 s32Id; ++ ++ EVENT_MUTEX_LOCK(); ++ for(s32Id=0; s32Id= MSOS_EVENTGROUP_MAX) ++ { ++ return -1; ++ } ++ spin_lock_init(&_MsOS_EventGroup_Info[s32Id].stMutexEvent); ++ init_waitqueue_head(&_MsOS_EventGroup_Info[s32Id].stSemaphore); ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete the event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @return TRUE : succeed ++/// @return FALSE : fail, sb is waiting for the event flag ++/// @note event group that are being waited on must not be deleted ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteEventGroup (MS_S32 s32EventGroupId) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ init_waitqueue_head(&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++ // PTH_RET_CHK(pthread_mutex_destroy(&_MsOS_EventGroup_Info[s32EventGroupId].stMutex)); ++ EVENT_MUTEX_LOCK(); ++ _MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup= 0; ++ _MsOS_EventGroup_Info[s32EventGroupId].bUsed = FALSE; ++ EVENT_MUTEX_UNLOCK(); ++ return TRUE; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Set the event flag (bitwise OR w/ current value) in the specified event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @param u32EventFlag \b IN: event flag value ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL MsOS_SetEvent_IRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ SET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ wake_up(&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++ return TRUE; ++} ++MS_BOOL MsOS_SetEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ spin_lock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ SET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ wake_up(&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++ return TRUE; ++} ++ ++MS_U32 MsOS_GetEvent(MS_S32 s32EventGroupId) ++{ ++ MS_U32 u32Event; ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ u32Event = HAS_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, 0xFFFF); ++ return u32Event; ++} ++//------------------------------------------------------------------------------------------------- ++/// Clear the specified event flag (bitwise XOR operation) in the specified event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @param u32EventFlag \b IN: event flag value ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_ClearEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ spin_lock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ RESET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ return TRUE; ++} ++MS_BOOL MsOS_ClearEventIRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ RESET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Wait for the specified event flag combination from the event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @param u32WaitEventFlag \b IN: wait event flag value ++/// @param pu32RetrievedEventFlag \b OUT: retrieved event flag value ++/// @param eWaitMode \b IN: E_AND/E_OR/E_AND_CLEAR/E_OR_CLEAR ++/// @param u32WaitMs \b IN: 0 ~ MSOS_WAIT_FOREVER: suspend time (ms) if the event is not ready ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_WaitEvent (MS_S32 s32EventGroupId, ++ MS_U32 u32WaitEventFlag, ++ MS_U32 *pu32RetrievedEventFlag, ++ EventWaitMode eWaitMode, ++ MS_U32 u32WaitMs) ++{ ++ MS_BOOL bRet= FALSE; ++ MS_BOOL bAnd; ++ MS_BOOL bClear; ++ MS_BOOL bTimeout=0; ++ ++ *pu32RetrievedEventFlag = 0; ++ ++ if (!u32WaitEventFlag) ++ { ++ return FALSE; ++ } ++ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ bClear= ((E_AND_CLEAR== eWaitMode) || (E_OR_CLEAR== eWaitMode))? TRUE: FALSE; ++ bAnd= ((E_AND== eWaitMode)|| (E_AND_CLEAR== eWaitMode))? TRUE: FALSE; ++ ++ do{ ++/* ++ *pu32RetrievedEventFlag= HAS_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32WaitEventFlag); ++ if ((bAnd)? (*pu32RetrievedEventFlag== u32WaitEventFlag): (0!= *pu32RetrievedEventFlag)) ++ { ++ break; ++ } ++*/ ++ if (u32WaitMs== MSOS_WAIT_FOREVER) //blocking wait ++ { ++ if (bAnd) ++ { ++ wait_event(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) == u32WaitEventFlag)); ++ } ++ else ++ { ++ //(printf("[DRVSCLDMA]%ld before Wait event:%lx @:%ld \n",u32WaitEventFlag,_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag,MsOS_GetSystemTime())); ++ wait_event(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) != 0)); ++ //(printf("[DRVSCLDMA]%ld After Wait event:%lx @:%ld \n",u32WaitEventFlag,MsOS_GetEvent(s32EventGroupId),MsOS_GetSystemTime())); ++ } ++ } ++ else ++ { ++ u32WaitMs = msecs_to_jiffies(u32WaitMs); ++ if (bAnd) ++ { ++ bTimeout = wait_event_timeout(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) == u32WaitEventFlag), ++ u32WaitMs); ++ } ++ else ++ { ++ bTimeout = wait_event_timeout(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) != 0), ++ u32WaitMs); ++ } ++ } ++ if(!bTimeout) ++ *pu32RetrievedEventFlag= HAS_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32WaitEventFlag); ++ else ++ printf("[SCL_MSOS]wait timeout\n"); ++ } while (0); ++ ++ bRet= (bAnd)? (*pu32RetrievedEventFlag== u32WaitEventFlag): (0!= *pu32RetrievedEventFlag); ++ if (bRet && bClear) ++ { ++ spin_lock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ RESET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, *pu32RetrievedEventFlag); ++ spin_unlock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ } ++ return bRet; ++} ++ ++wait_queue_head_t* MsOS_GetEventQueue (MS_S32 s32EventGroupId) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ return (&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++} ++ ++ ++// ++// Timer management ++// ++static void _MsOS_TimerNotify(unsigned long data) ++{ ++ MS_S32 s32Id = (MS_S32) data; ++ ++ if (_MsOS_Timer_Info[s32Id].pTimerCb) ++ { ++ _MsOS_Timer_Info[s32Id].pTimerCb(0, s32Id| MSOS_ID_PREFIX); ++ } ++ _MsOS_Timer_Info[s32Id].timer.expires = jiffies + HZ*_MsOS_Timer_Info[s32Id].period/1000; ++ add_timer(&(_MsOS_Timer_Info[s32Id].timer)); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Create a Timer ++/// @param pTimerCb \b IN: timer callback function ++/// @param u32FirstTimeMs \b IN: first ms for timer expiration ++/// @param u32PeriodTimeMs \b IN: periodic ms for timer expiration after first expiration ++/// 0: one shot timer ++/// @param bStartTimer \b IN: TRUE: activates the timer after it is created ++/// FALSE: leaves the timer disabled after it is created ++/// @param pTimerName \b IN: Timer name (not used by eCos) ++/// @return >=0 : assigned Timer ID ++/// <0 : fail ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_CreateTimer (TimerCb pTimerCb, ++ MS_U32 u32FirstTimeMs, ++ MS_U32 u32PeriodTimeMs, ++ MS_BOOL bStartTimer, ++ char *pTimerName) ++{ ++ MS_S32 s32Id; ++ ++ TIMER_MUTEX_LOCK(); ++ for(s32Id=0;s32Id= MSOS_TIMER_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_Timer_Info[s32Id].pTimerCb= pTimerCb; ++ _MsOS_Timer_Info[s32Id].first = u32FirstTimeMs; ++ _MsOS_Timer_Info[s32Id].period = u32PeriodTimeMs; ++ _MsOS_Timer_Info[s32Id].timer.data = (unsigned long)s32Id; ++ _MsOS_Timer_Info[s32Id].timer.expires = jiffies + HZ*u32FirstTimeMs/1000; ++ _MsOS_Timer_Info[s32Id].timer.function = _MsOS_TimerNotify; ++ if (bStartTimer) ++ { ++ add_timer(&(_MsOS_Timer_Info[s32Id].timer)); ++ } ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete the Timer ++/// @param s32TimerId \b IN: Timer ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteTimer (MS_S32 s32TimerId) ++{ ++ //return FALSE; ++ ++ if ( (s32TimerId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TimerId &= MSOS_ID_MASK; ++ } ++ ++ if( _MsOS_Timer_Info[s32TimerId].bUsed ) ++ { ++ TIMER_MUTEX_LOCK(); ++ del_timer(&(_MsOS_Timer_Info[s32TimerId].timer)); ++ _MsOS_Timer_Info[s32TimerId].bUsed = FALSE; ++ ++ _MsOS_Timer_Info[s32TimerId].pTimerCb = NULL; ++ _MsOS_Timer_Info[s32TimerId].period = 0; ++ _MsOS_Timer_Info[s32TimerId].first = 0; ++ TIMER_MUTEX_UNLOCK(); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Start the Timer ++/// @param s32TimerId \b IN: Timer ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_StartTimer (MS_S32 s32TimerId) ++{ ++ //return FALSE; ++ ++ if ( (s32TimerId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TimerId &= MSOS_ID_MASK; ++ } ++ ++ if( _MsOS_Timer_Info[s32TimerId].bUsed ) ++ { ++ _MsOS_Timer_Info[s32TimerId].timer.expires = jiffies + _MsOS_Timer_Info[s32TimerId].period/1000; ++ add_timer(&(_MsOS_Timer_Info[s32TimerId].timer)); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Stop the Timer ++/// @param s32TimerId \b IN: Timer ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++/// @note MsOS_StopTimer then MsOS_StartTimer => The timer will trigger at the same relative ++/// intervals that it would have if it had not been disabled. ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_StopTimer (MS_S32 s32TimerId) ++{ ++ //return FALSE; ++ ++ if ( (s32TimerId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TimerId &= MSOS_ID_MASK; ++ } ++ ++ if( _MsOS_Timer_Info[s32TimerId].bUsed ) ++ { ++ del_timer(&(_MsOS_Timer_Info[s32TimerId].timer)); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++void* MsOS_Memalloc(size_t size, gfp_t flags) ++{ ++ return kmalloc(size, flags); ++} ++void MsOS_MemFree(void *pVirAddr) ++{ ++ kfree(pVirAddr); ++} ++void* MsOS_VirMemalloc(size_t size) ++{ ++ return vmalloc(size); ++} ++void MsOS_VirMemFree(void *pVirAddr) ++{ ++ vfree(pVirAddr); ++} ++void* MsOS_Memcpy(void *pstCfg,const void *pstInformCfg,__kernel_size_t size) ++{ ++ return memcpy(pstCfg, pstInformCfg, size); ++} ++void* MsOS_Memset(void *pstCfg,int val,__kernel_size_t size) ++{ ++ return memset(pstCfg, val, size); ++} +diff --git a/drivers/mstar/scl/infinity/src/mxlib/msos/MsOS.h b/drivers/mstar/scl/infinity/src/mxlib/msos/MsOS.h +new file mode 100644 +index 00000000..291922bc +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/msos/MsOS.h +@@ -0,0 +1,857 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsOS.h ++/// @brief MStar OS Wrapper ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MS_OS_H_ ++#define _MS_OS_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Defines ++//------------------------------------------------------------------------------------------------- ++#define MSIF_MSOS_LIB_CODE {'M','S','O','S'} //Lib code ++#define MSIF_MSOS_LIBVER {'0','1'} //LIB version ++#define MSIF_MSOS_BUILDNUM {'0','1'} //Build Number ++#define MSIF_MSOS_CHANGELIST {'0','0','0','0','0','0','0','0'} //P4 ChangeList Number ++ ++#define MSOS_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_TAG, /* 'MSIF' */ \ ++ MSIF_CLASS, /* '00' */ \ ++ MSIF_CUS, /* 0x0000 */ \ ++ MSIF_MOD, /* 0x0000 */ \ ++ MSIF_CHIP, \ ++ MSIF_CPU, \ ++ MSIF_MSOS_LIB_CODE, /* IP__ */ \ ++ MSIF_MSOS_LIBVER, /* 0.0 ~ Z.Z */ \ ++ MSIF_MSOS_BUILDNUM, /* 00 ~ 99 */ \ ++ MSIF_MSOS_CHANGELIST, /* CL# */ \ ++ MSIF_OS ++ ++#define MSOS_TASK_MAX 32//(32+120) ++#define MSOS_MEMPOOL_MAX (8+64) ++#define MSOS_FIXSIZE_MEMPOOL_MAX (8) ++#define MSOS_SEMAPHORE_MAX (32+150) ++#define MSOS_MUTEX_MAX 32//(64+240) ++#define MSOS_SPINLOCK_MAX 8 ++#define MSOS_EVENTGROUP_MAX 32//(64) ++#define MSOS_TIMER_MAX (32) ++#define MSOS_QUEUE_MAX (16+60) ++ ++#define MSOS_OS_MALLOC (0x7654FFFF) ++#define MSOS_MALLOC_ID (0x0000FFFF) ++ ++//------------------------------------------------------------------------------------------------- ++// Macros ++//------------------------------------------------------------------------------------------------- ++//time and clock macros ++#define TICK_PER_ONE_MS (1) //Note: confirm Kernel fisrt ++#define MSOS_WAIT_FOREVER (0xffffff00/TICK_PER_ONE_MS) ++ ++#ifdef MSOS_PERF_DEBUG ++#define MSOS_PERF_PROFILE_DECL() MS_U32 u32time1=0, u32time2=0 ++#define MSOS_PERF_PROFILE_ON() u32time1 = MsOS_GetSystemTime() ++#define MSOS_PERF_PROFILE_OFF() u32time2 = MsOS_GetSystemTime(); \ ++ printf("[MSOS_DBG]%s:%d takes %6dms\n",__FILE__, __LINE__, u32time2-u32time1) ++#else ++#define MSOS_PERF_PROFILE_DECL() ++#define MSOS_PERF_PROFILE_ON() ++#define MSOS_PERF_PROFILE_OFF() ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure Declaration ++//------------------------------------------------------------------------------------------------- ++#if defined (MSOS_TYPE_ECOS) || defined (MSOS_TYPE_LINUX) || defined (MSOS_TYPE_NOS) || defined (MSOS_TYPE_UCOS) || defined (MSOS_TYPE_CE) ++ ++//compatible with Nucleus's task_entry ++typedef void ( *TaskEntry ) (MS_U32 argc, void *argv); ///< Task entry function argc: pass additional data to task entry; argv: not used by eCos ++typedef void ( *InterruptCb ) (InterruptNum eIntNum); ///< Interrupt callback function ++typedef void ( *SignalCb ) (MS_U32 u32Signals); ///< Signal callback function ++typedef void ( *TimerCb ) (MS_U32 u32StTimer, MS_U32 u32TimerID); ///< Timer callback function u32StTimer: not used; u32TimerID: Timer ID ++ ++typedef struct { ++ volatile MS_S32 s32Value; ++} MsOS_Atomic; ++ ++ ++#ifdef MSOS_TYPE_UCOS ++/// Task priority ++typedef enum ++{ ++ E_TASK_PRI_SYS = 0, ///< System priority task ( interrupt level driver, e.g. TSP, SMART ) ++ E_TASK_PRI_HIGHEST = 16, ///< Highest priority task ( background monitor driver, e.g. DVBC, HDMI ) ++ E_TASK_PRI_HIGH = 32, ///< High priority task ( service task ) ++ E_TASK_PRI_MEDIUM = 48, ///< Medium priority task ( application task ) ++ E_TASK_PRI_LOW = 64, ///< Low priority task ( nonbusy application task ) ++ E_TASK_PRI_LOWEST = 96, ///< Lowest priority task ( idle application task ) ++} TaskPriority; ++#else ++/// Task priority ++typedef enum ++{ ++ E_TASK_PRI_SYS = 0, ///< System priority task ( interrupt level driver, e.g. TSP, SMART ) ++ E_TASK_PRI_HIGHEST = 4, ///< Highest priority task ( background monitor driver, e.g. DVBC, HDMI ) ++ E_TASK_PRI_HIGH = 8, ///< High priority task ( service task ) ++ E_TASK_PRI_MEDIUM = 12, ///< Medium priority task ( application task ) ++ E_TASK_PRI_LOW = 16, ///< Low priority task ( nonbusy application task ) ++ E_TASK_PRI_LOWEST = 24, ///< Lowest priority task ( idle application task ) ++} TaskPriority; ++#endif ++ ++ ++/// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++/// Message size type ++typedef enum ++{ ++ E_MSG_FIXED_SIZE, ///< Fixed size message ++ E_MSG_VAR_SIZE, ///< Variable size message ++} MessageType; ++ ++/// Event mode ++typedef enum ++{ ++ E_AND, ///< Specify all of the requested events are require. ++ E_OR, ///< Specify any of the requested events are require. ++ E_AND_CLEAR, ///< Specify all of the requested events are require. If the request are successful, clear the event. ++ E_OR_CLEAR, ///< Specify any of the requested events are require. If the request are successful, clear the event. ++} EventWaitMode; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ MS_U32 uPoolSize; ++ MS_U32 u32MinAllocation; ++ MS_U32 u32Addr; ++ MsOSAttribute eAttribute; ++ char szName[16]; ++} MemoryPool_Info, *PMemoryPool_Info; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ TaskPriority ePriority; ++ void *pStack; ++ MS_U32 u32StackSize; ++ char szName[16]; ++} Task_Info, *PTask_Info; ++ ++typedef struct ++{ ++ unsigned int LX_MEM_ADDR; ++ unsigned int LX_MEM_LENGTH; ++ unsigned int LX_MEM2_ADDR; ++ unsigned int LX_MEM2_LENGTH; ++ unsigned int EMAC_ADDR; ++ unsigned int EMAC_LENGTH; ++ unsigned int DRAM_ADDR; ++ unsigned int DRAM_LENGTH; ++ unsigned int BB_ADDR; ++ unsigned int BB_LENGTH; ++ unsigned int MPOOL_MEM_ADDR; ++ unsigned int MPOOL_MEM_LENGTH; ++ unsigned int G3D_MEM0_ADDR; ++ unsigned int G3D_MEM0_LENGTH; ++ unsigned int G3D_MEM1_ADDR; ++ unsigned int G3D_MEM1_LENGTH; ++ unsigned int G3D_CMDQ_ADDR; ++ unsigned int G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t; ++ ++#elif defined (MSOS_TYPE_LINUX_KERNEL) ++ ++//#include ++//#include ++ ++//typedef void ( *TaskEntry ) (MS_U32 argc, void *argv); ///< Task entry function argc: pass additional data to task entry; argv: not used by eCos ++typedef int (*TaskEntry)(void *argv); ++//typedef void ( *InterruptCb ) (InterruptNum eIntNum); ///< Interrupt callback function ++typedef irqreturn_t ( *InterruptCb ) (InterruptNum eIntNum, void* dev_id); ++typedef void ( *SignalCb ) (MS_U32 u32Signals); ///< Signal callback function ++typedef void ( *TimerCb ) (MS_U32 u32StTimer, MS_U32 u32TimerID); ///< Timer callback function u32StTimer: not used; u32TimerID: Timer ID ++ ++typedef struct { ++ volatile MS_S32 s32Value; ++} MsOS_Atomic; ++ ++/// Task priority ++typedef enum ++{ ++ E_TASK_PRI_SYS = 0, ///< System priority task ( interrupt level driver, e.g. TSP, SMART ) ++ E_TASK_PRI_HIGHEST = 4, ///< Highest priority task ( background monitor driver, e.g. DVBC, HDMI ) ++ E_TASK_PRI_HIGH = 8, ///< High priority task ( service task ) ++ E_TASK_PRI_MEDIUM = 12, ///< Medium priority task ( application task ) ++ E_TASK_PRI_LOW = 16, ///< Low priority task ( nonbusy application task ) ++ E_TASK_PRI_LOWEST = 24, ///< Lowest priority task ( idle application task ) ++} TaskPriority; ++ ++/// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++/// Message size type ++typedef enum ++{ ++ E_MSG_FIXED_SIZE, ///< Fixed size message ++ E_MSG_VAR_SIZE, ///< Variable size message ++} MessageType; ++ ++/// Event mode ++typedef enum ++{ ++ E_AND, ///< Specify all of the requested events are require. ++ E_OR, ///< Specify any of the requested events are require. ++ E_AND_CLEAR, ///< Specify all of the requested events are require. If the request are successful, clear the event. ++ E_OR_CLEAR, ///< Specify any of the requested events are require. If the request are successful, clear the event. ++} EventWaitMode; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ MS_U32 uPoolSize; ++ MS_U32 u32MinAllocation; ++ MS_U32 u32Addr; ++ MsOSAttribute eAttribute; ++ char szName[16]; ++} MemoryPool_Info, *PMemoryPool_Info; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ TaskPriority ePriority; ++ void *pStack; ++ MS_U32 u32StackSize; ++ char szName[16]; ++} Task_Info, *PTask_Info; ++ ++typedef struct ++{ ++ unsigned int LX_MEM_ADDR; ++ unsigned int LX_MEM_LENGTH; ++ unsigned int LX_MEM2_ADDR; ++ unsigned int LX_MEM2_LENGTH; ++ unsigned int EMAC_ADDR; ++ unsigned int EMAC_LENGTH; ++ unsigned int DRAM_ADDR; ++ unsigned int DRAM_LENGTH; ++ unsigned int BB_ADDR; ++ unsigned int BB_LENGTH; ++ unsigned int MPOOL_MEM_ADDR; ++ unsigned int MPOOL_MEM_LENGTH; ++ unsigned int G3D_MEM0_ADDR; ++ unsigned int G3D_MEM0_LENGTH; ++ unsigned int G3D_MEM1_ADDR; ++ unsigned int G3D_MEM1_LENGTH; ++ unsigned int G3D_CMDQ_ADDR; ++ unsigned int G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t; ++ ++#elif defined (MSOS_TYPE_XXX) ++ ++#error "The OS is not supported now ..." ++ ++#endif ++ ++ ++///////////paul include for RTOS and LINUX ++typedef struct ++{ ++ struct task_struct *pThread; ++}MSOS_ST_TASKSTRUCT; ++typedef struct clk MSOS_ST_CLK; ++ ++//------------------------------------------------------------------------------------------------- ++// Extern Functions ++//------------------------------------------------------------------------------------------------- ++// ++// Init ++// ++MS_BOOL MsOS_Init (void); ++ ++ ++// ++// Memory management ++// ++MS_S32 MsOS_CreateMemoryPool (MS_U32 u32PoolSize, ++ MS_U32 u32MinAllocation, ++ void * pPoolAddr, ++ MsOSAttribute eAttribute, ++ char *pPoolName); ++ ++MS_BOOL MsOS_DeleteMemoryPool (MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_InfoMemoryPool (MS_S32 s32PoolId, ++ void **pPoolAddr, ++ MS_U32 *pu32PoolSize, ++ MS_U32 *pu32FreeSize, ++ MS_U32 *pu32LargestFreeBlockSize); ++ ++void * MsOS_AllocateMemory (MS_U32 u32Size, MS_S32 s32PoolId); ++ ++//void * MsOS_AllocateAlignedMemory (MS_U32 u32Size, MS_U32 u32AlignedByte, MS_S32 s32PoolId); ++ ++void * MsOS_ReallocateMemory (void *pOrgAddress, MS_U32 u32NewSize, MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_FreeMemory (void *pAddress, MS_S32 s32PoolId); ++ ++MS_S32 MsOS_CreateFixSizeMemoryPool (MS_U32 u32PoolSize, ++ MS_U32 u32BlockSize, ++ void * pPoolAddr, ++ MsOSAttribute eAttribute, ++ char *pPoolName); ++ ++MS_BOOL MsOS_DeleteFixSizeMemoryPool (MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_InfoFixSizeMemoryPool (MS_S32 s32PoolId, ++ void **pPoolAddr, ++ MS_U32 *pu32PoolSize, ++ MS_U32 *pu32FreeSize, ++ MS_U32 *pu32LargestFreeBlockSize); ++ ++void * MsOS_AllocateFixSizeMemory (MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_FreeFixSizeMemory (void *pAddress, MS_S32 s32PoolId); ++ ++ ++// ++// Task ++// ++MS_S32 MsOS_CreateTask (TaskEntry pTaskEntry, ++ MS_U32 u32TaskEntryData, ++ MS_BOOL bAutoStart, ++ char *pTaskName); ++MSOS_ST_TASKSTRUCT MsOS_GetTaskinfo(MS_S32 s32Id); ++int MsOS_GetUserNice(MSOS_ST_TASKSTRUCT stTask); ++void MsOS_SetUserNice(MSOS_ST_TASKSTRUCT stTask, long nice); ++MS_BOOL MsOS_DeleteTask (MS_S32 s32TaskId); ++ ++void MsOS_YieldTask (void); ++ ++void MsOS_DelayTask (MS_U32 u32Ms); ++ ++void MsOS_DelayTaskUs (MS_U32 u32Us); ++ ++MS_BOOL MsOS_ResumeTask (MS_S32 s32TaskId); ++ ++MS_BOOL MsOS_SuspendTask (MS_S32 s32TaskId); ++ ++MS_S32 MsOS_InfoTaskID (void); ++//------------------------------------------------------------------------------------------------- ++/// Get thread ID of current thread/process in OS ++/// @return : current thread ID ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_GetOSThreadID (void); ++ ++// ++// Mutex ++// ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++#define MAX_MUTEX_NAME_LENGTH 16 ++MS_S32 MsOS_CreateMutex ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++MS_S32 MsOS_CreateSpinlock ( MsOSAttribute eAttribute, char *pMutexName1, MS_U32 u32Flag); ++ ++MS_BOOL MsOS_DeleteMutex (MS_S32 s32MutexId); ++MS_BOOL MsOS_DeleteSpinlock (MS_S32 s32MutexId); ++MS_BOOL MsOS_ObtainMutex_IRQ(MS_S32 s32MutexId); ++MS_BOOL MsOS_ObtainMutex (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++MS_BOOL MsOS_ReleaseMutex_IRQ (MS_S32 s32MutexId); ++MS_BOOL MsOS_ReleaseMutex (MS_S32 s32MutexId); ++ ++MS_BOOL MsOS_InfoMutex (MS_S32 s32MutexId, MsOSAttribute *peAttribute, char *pMutexName); ++ ++ ++// ++// Semaphore ++// ++MS_S32 MsOS_CreateSemaphore (MS_U32 u32InitCnt, ++ MsOSAttribute eAttribute, ++ char *pName); ++ ++MS_BOOL MsOS_DeleteSemaphore (MS_S32 s32SemaphoreId); ++ ++MS_BOOL MsOS_ObtainSemaphore (MS_S32 s32SemaphoreId, MS_U32 u32WaitMs); ++ ++MS_BOOL MsOS_ReleaseSemaphore (MS_S32 s32SemaphoreId); ++ ++MS_BOOL MsOS_InfoSemaphore (MS_S32 s32SemaphoreId, MS_U32 *pu32Cnt, MsOSAttribute *peAttribute, char *pSemaphoreName); ++ ++ ++// ++// Event management ++// ++MS_S32 MsOS_CreateEventGroup (char *pName); ++ ++MS_BOOL MsOS_DeleteEventGroup (MS_S32 s32EventGroupId); ++MS_BOOL MsOS_SetEvent_IRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++ ++MS_BOOL MsOS_SetEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++MS_U32 MsOS_GetEvent(MS_S32 s32EventGroupId); ++MS_BOOL MsOS_ClearEventIRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++MS_BOOL MsOS_ClearEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++MS_BOOL MsOS_WaitEvent (MS_S32 s32EventGroupId, ++ MS_U32 u32WaitEventFlag, ++ MS_U32 *pu32RetrievedEventFlag, ++ EventWaitMode eWaitMode, ++ MS_U32 u32WaitMs); ++wait_queue_head_t* MsOS_GetEventQueue (MS_S32 s32EventGroupId); ++ ++/* ++// ++// Signal management ++// ++MS_BOOL MsOS_CreateSignal (SignalCb pSignalCb); ++ ++MS_BOOL MsOS_ControlSignals (MS_U32 u32SignalMask); ++ ++MS_BOOL MsOS_SendSignals (MS_S32 s32TaskId, MS_U32 u32Signal); ++ ++MS_U32 MsOS_ReceiveSignals (void); ++*/ ++ ++// ++// Timer management ++// ++MS_S32 MsOS_CreateTimer (TimerCb pTimerCb, ++ MS_U32 u32FirstTimeMs, ++ MS_U32 u32PeriodTimeMs, ++ MS_BOOL bStartTimer, ++ char *pName); ++ ++MS_BOOL MsOS_DeleteTimer (MS_S32 s32TimerId); ++ ++MS_BOOL MsOS_StartTimer (MS_S32 s32TimerId); ++ ++MS_BOOL MsOS_StopTimer (MS_S32 s32TimerId); ++ ++MS_BOOL MsOS_ResetTimer (MS_S32 s32TimerId, ++ MS_U32 u32FirstTimeMs, ++ MS_U32 u32PeriodTimeMs, ++ MS_BOOL bStartTimer); ++void* MsOS_Memalloc(size_t size, gfp_t flags); ++void MsOS_MemFree(void *pVirAddr); ++void* MsOS_VirMemalloc(size_t size); ++void MsOS_VirMemFree(void *pVirAddr); ++void* MsOS_Memcpy(void *pstCfg,const void *pstInformCfg,__kernel_size_t size); ++void* MsOS_Memset(void *pstCfg,int val,__kernel_size_t size); ++// ++// System time ++// ++//MS_U32 MsOS_GetSystemTick (void); ++ ++MS_U32 MsOS_GetSystemTime (void); ++void MsOS_SetPollWait(void *filp,void *pWaitQueueHead,void *pstPollQueue); ++MS_U64 MsOS_GetSystemTimeStamp (void); ++ ++ ++MS_U32 MsOS_Timer_DiffTimeFromNow(MS_U32 u32TaskTimer); ///[OBSOLETE] ++ ++MS_U32 MsOS_Timer_DiffTime(MS_U32 u32Timer, MS_U32 u32TaskTimer); ///[OBSOLETE] ++//MS_BOOL MsOS_SetSystemTime (MS_U32 u32SystemTime); ++ ++ ++// ++// Queue ++// ++MS_S32 MsOS_CreateQueue (void *pStartAddr, ++ MS_U32 u32QueueSize, ++ MessageType eMessageType, ++ MS_U32 u32MessageSize, ++ MsOSAttribute eAttribute, ++ char *pQueueName); ++ ++MS_BOOL MsOS_DeleteQueue (MS_S32 s32QueueId); ++ ++MS_BOOL MsOS_SendToQueue (MS_S32 s32QueueId, MS_U8 *pu8Message, MS_U32 u32Size, MS_U32 u32WaitMs); ++ ++MS_BOOL MsOS_RecvFromQueue (MS_S32 s32QueueId, MS_U8 *pu8Message, MS_U32 u32IntendedSize, MS_U32 *pu32ActualSize, MS_U32 u32WaitMs); ++ ++MS_BOOL MsOS_PeekFromQueue (MS_S32 s32QueueId, MS_U8 *pu8Message, MS_U32 u32IntendedSize, MS_U32 *pu32ActualSize); ++ ++// ++// Atomic operation ++// ++void MsOS_AtomicSet(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++MS_S32 MsOS_AtomicRead(const MsOS_Atomic *pAtomic); ++ ++void MsOS_AtomicAdd(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++void MsOS_AtomicSub(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++ ++MS_S32 MsOS_AtomicAddReturn(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++MS_S32 MsOS_AtomicSubReturn(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++ ++// ++// Per-thread data ++// ++MS_BOOL MsOS_CreateThreadDataIndex(MS_U32 *pu32Index); ++MS_BOOL MsOS_DeleteThreadDataIndex(MS_U32 u32Index); ++MS_BOOL MsOS_SetThreadData(MS_U32 u32Index, MS_U32 u32Data); ++MS_BOOL MsOS_GetThreadData(MS_U32 u32Index, MS_U32 *pu32Data); ++ ++ ++// ++// Interrupt management ++// ++MS_BOOL MsOS_AttachInterrupt (InterruptNum eIntNum, InterruptCb pIntCb,unsigned long flags,const char *name); ++ ++MS_BOOL MsOS_DetachInterrupt (InterruptNum eIntNum); ++ ++MS_BOOL MsOS_EnableInterrupt (InterruptNum eIntNum); ++ ++MS_BOOL MsOS_DisableInterrupt (InterruptNum eIntNum); ++ ++MS_BOOL MsOS_In_Interrupt (void); ++ ++MS_U32 MsOS_DisableAllInterrupts(void); ++ ++MS_BOOL MsOS_RestoreAllInterrupts(MS_U32 u32OldInterrupts); ++ ++MS_BOOL MsOS_EnableAllInterrupts(void); ++ ++ ++ ++#if defined(__aeon__) ++typedef enum { ++ E_EXCEPTION_BUS_ERROR = 2, ++ E_EXCEPTION_DATA_PAGE_FAULT, ++ E_EXCEPTION_INSTRUCTION_PAGE_FAULT, ++ E_EXCEPTION_TICK_TIMER, ///< tick timer, do not use directly ++ E_EXCEPTION_UNALIGNED_ACCESS, ++ E_EXCEPTION_ILLEGAL_INSTRUCTION, ++ E_EXCEPTION_EXTERNAL_INTERRUPT, ///< external interrupt, do not use directly ++ E_EXCEPTION_DTLB_MISS, ++ E_EXCEPTION_ITLB_MISS, ++ E_EXCEPTION_RANGE, ++ E_EXCEPTION_SYSCALL, ///< caused by l.sys ++ E_EXCEPTION_RESERVED, ++ E_EXCEPTION_TRAP, ///< caused by l.trap ++ E_EXCEPTION_MAX = E_EXCEPTION_TRAP, ++} MHAL_EXCEPTION_TYPE; ++ ++typedef enum { ++ E_INTERRUPT_TICK_TIMER, //< risc32 builtin tick timer ++ E_INTERRUPT_00 = 1, //< PIC interrupt start from 1 for handler performance ++ E_INTERRUPT_01, ++ E_INTERRUPT_02, ++ E_INTERRUPT_03, ++ E_INTERRUPT_04, ++ E_INTERRUPT_05, ++ E_INTERRUPT_06, ++ E_INTERRUPT_07, ++ E_INTERRUPT_08, ++ E_INTERRUPT_09, ++ E_INTERRUPT_10, ++ E_INTERRUPT_11, ++ E_INTERRUPT_12, ++ E_INTERRUPT_13, ++ E_INTERRUPT_14, ++ E_INTERRUPT_15, ++ E_INTERRUPT_16, ++ E_INTERRUPT_17, ++ E_INTERRUPT_18, ++ E_INTERRUPT_19, ++ E_INTERRUPT_20, ++ E_INTERRUPT_21, ++ E_INTERRUPT_22, ++ E_INTERRUPT_23, ++ E_INTERRUPT_24, ++ E_INTERRUPT_25, ++ E_INTERRUPT_26, ++ E_INTERRUPT_27, ++ E_INTERRUPT_28, ++ E_INTERRUPT_29, ++ E_INTERRUPT_30, ++ E_INTERRUPT_31, ++} MHAL_INTERRUPT_TYPE; ++ ++// Aliases for interrupt number ++#define E_INTERRUPT_FIQ E_INTERRUPT_02 ++#define E_INTERRUPT_IRQ E_INTERRUPT_03 ++#define E_INTERRUPT_UART E_INTERRUPT_19 ++#define E_INTERRUPT_MAX E_INTERRUPT_31 ++ ++typedef struct ++{ ++ unsigned long r[32]; ///< GPR registers ++#ifdef __AEONR2__ ++ unsigned long machi2; // Highest 32-bits of new 32x32=64 multiplier ++#endif ++ unsigned long machi; // High and low words of ++ unsigned long maclo; // multiply/accumulate reg ++ ++ // These are only saved for exceptions and interrupts ++ int vector; ///< vector number ++ int sr; ///< status register ++ unsigned long pc; ///< program counter ++ ++ // Saved only for exceptions, and not restored when continued: ++ // Effective address of instruction/data access that caused exception ++ unsigned long eear; ///< exception effective address ++} MHAL_SavedRegisters; ++#else ++typedef enum { ++ E_EXCEPTION_DATA_TLBERROR_ACCESS = 1, // TLB modification exception ++ E_EXCEPTION_DATA_TLBMISS_ACCESS, // TLB miss (Load or IFetch) ++ E_EXCEPTION_DATA_TLBMISS_WRITE, // TLB miss (Store) ++ E_EXCEPTION_DATA_UNALIGNED_ACCESS, // Address error (Load or Ifetch) ++ E_EXCEPTION_DATA_UNALIGNED_WRITE, // Address error (store) ++ E_EXCEPTION_CODE_ACCESS, // Bus error (Ifetch) ++ E_EXCEPTION_DATA_ACCESS, // Bus error (data load or store) ++ E_EXCEPTION_SYSTEM_CALL, // System call ++ E_EXCEPTION_INSTRUCTION_BP, // Break point ++ E_EXCEPTION_ILLEGAL_INSTRUCTION, // Reserved instruction ++ E_EXCEPTION_COPROCESSOR, // Coprocessor unusable ++ E_EXCEPTION_OVERFLOW, // Arithmetic overflow ++ E_EXCEPTION_RESERVED_13, // Reserved ++ E_EXCEPTION_DIV_BY_ZERO, // Division-by-zero [reserved vector] ++ E_EXCEPTION_FPU, // Floating point exception ++ E_EXCEPTION_MAX = E_EXCEPTION_FPU, ++} MHAL_EXCEPTION_TYPE; ++ ++typedef enum { ++ E_INTERRUPT_02 = 0, ++ E_INTERRUPT_03, ++ E_INTERRUPT_04, ++ E_INTERRUPT_05, ++ E_INTERRUPT_06, ++ E_INTERRUPT_07, ++} MHAL_INTERRUPT_TYPE; ++ ++// Aliases for interrupt number ++#define E_INTERRUPT_FIQ E_INTERRUPT_03 ++#define E_INTERRUPT_IRQ E_INTERRUPT_02 ++#define E_INTERRUPT_TICK_TIMER E_INTERRUPT_07 ++#define E_INTERRUPT_MAX E_INTERRUPT_07 ++#define E_EXCEPTION_TRAP E_EXCEPTION_RESERVED_13 ++ ++typedef struct ++{ ++ // These are common to all saved states ++ unsigned long d[32]; /* Data regs */ ++ unsigned long hi; /* hi word of mpy/div reg */ ++ unsigned long lo; /* lo word of mpy/div reg */ ++ ++ // The status register contains the interrupt-enable bit which needs ++ // to be preserved across context switches. ++ unsigned long sr; /* Status Reg */ ++ ++ // These are only saved for exceptions and interrupts ++ unsigned long vector; /* Vector number */ ++ unsigned long pc; /* Program Counter */ ++ ++ // These are only saved for exceptions, and are not restored ++ // when continued. ++ unsigned long cause; /* Exception cause register */ ++ unsigned long badvr; /* Bad virtual address reg */ ++ ++} MHAL_SavedRegisters; ++#endif ++ ++#if defined (__arm__) ++typedef void (*mhal_isr_t)(void); ++#else ++typedef void (*mhal_isr_t)(MHAL_SavedRegisters *regs, MS_U32 vector); ++#endif ++ ++MS_U32 MsOS_CPU_DisableInterrupt (void); ++ ++MS_BOOL MsOS_CPU_EnableInterrupt (void); ++ ++MS_BOOL MsOS_CPU_RestoreInterrupt (MS_U32 u32OldInterrupts); ++ ++MS_BOOL MsOS_CPU_MaskAllInterrupt (void); ++ ++MS_BOOL MsOS_CPU_MaskInterrupt (MHAL_INTERRUPT_TYPE intr_num); ++ ++MS_BOOL MsOS_CPU_UnMaskInterrupt (MHAL_INTERRUPT_TYPE intr_num); ++ ++MS_BOOL MsOS_CPU_LockInterrupt (void); ++ ++MS_BOOL MsOS_CPU_UnLockInterrupt (void); ++ ++MS_BOOL MsOS_CPU_AttachInterrupt (MHAL_INTERRUPT_TYPE intr_num, mhal_isr_t isr, MS_U32 dat); ++ ++MS_BOOL MsOS_CPU_DetachInterrupt (MHAL_INTERRUPT_TYPE intr_num); ++ ++MS_BOOL MsOS_CPU_AttachException (MHAL_EXCEPTION_TYPE expt_num, mhal_isr_t isr, MS_U32 dat); ++ ++MS_BOOL MsOS_CPU_DetachExceptiont (MHAL_EXCEPTION_TYPE expt_num); ++ ++MS_BOOL MsOS_CPU_SetEBASE (MS_U32 u32Addr); ++ ++ ++ ++ ++// ++// Cache Opertation ++// ++MS_BOOL MsOS_Dcache_Flush( MS_U32 u32Start , MS_U32 u32Size ); ++ ++MS_BOOL MsOS_Dcache_Invalidate( MS_U32 u32Start , MS_U32 u32Size ); ++ ++MS_BOOL MsOS_Dcache_Writeback( MS_U32 u32Start , MS_U32 u32Size ); ++ ++#if defined(CHIP_T12) || defined(CHIP_T8) || defined(CHIP_J2) || defined(CHIP_A2) || defined(CHIP_A5) || defined(CHIP_A3) ++MS_BOOL MsOS_L2Cache_Flush(void); ++MS_BOOL MsOS_L2Cache_Read(void); ++#endif ++ ++// ++// CPU relative Operation ++// ++void MsOS_Sync(void); ++ ++typedef enum //_MsOSMPool_DbgLevel ++{ ++ E_MsOSMPool_DBG_Release = 0, ++ E_MsOSMPool_DBG_L1, // display error msg ++} MsOSMPool_DbgLevel; ++ ++// Kernel related information ++MS_BOOL MDrv_SYS_Info(IO_Sys_Info_t* SysInfo); ++// MPool Operation ++void MsOS_MPool_SetDbgLevel(MsOSMPool_DbgLevel DbgLevel); ++MS_BOOL MsOS_MPool_Init(void); ++MS_BOOL MsOS_MPool_Get(void** pAddrVirt, MS_U32* pu32AddrPhys, MS_U32* pu32Size, MS_BOOL bNonCache); ++MS_BOOL MsOS_MPool_Close(void); ++MS_U32 MsOS_MPool_VA2PA(MS_U32 pAddrVirt); ++MS_U32 MsOS_MPool_PA2KSEG1(MS_U32 pAddrPhys); ++MS_U32 MsOS_MPool_PA2KSEG0(MS_U32 pAddrPhys); ++MS_BOOL MsOS_MPool_Dcache_Flush(MS_U32 pAddrVirt, MS_U32 u32Size); // the input address should be user mode cacheable address ++MS_BOOL MsOS_MPool_Mapping(MS_U8 u8MiuSel, MS_U32 u32Offset, MS_U32 u32MapSize, MS_BOOL bNonCache); ++MS_BOOL MsOS_MPool_Kernel_Detect(MS_U32 *lx_addr, MS_U32 *lx_size, MS_U32 *lx2_addr, MS_U32 *lx2_size); ++ ++#define MsOS_MPool_PA2VA MsOS_MPool_PA2KSEG1 ++ ++// Share memory operation ++#define MAX_CLIENT_NAME_LENGTH 50 ++#define MSOS_SHM_QUERY 0x00000000 ++#define MSOS_SHM_CREATE 0x00000001 ++ ++MS_BOOL MsOS_SHM_Init(void); ++MS_BOOL MsOS_SHM_GetId(MS_U8* pu8ClientName, MS_U32 u32BufSize, MS_U32* pu32ShmId, MS_U32* pu32Addr, MS_U32* pu32BufSize, MS_U32 u32Flag); ++MS_BOOL MsOS_SHM_FreeId(MS_U8* pu8ClientName, MS_U32 u32ShmId); ++ ++// ++// OS Dependent Macro ++// ++ ++// Worldwide thread safe macro ++// Usage: ++// MS_S32 os_X_MutexID; ++// os_X_MutexID = OS_CREATE_MUTEX(_M_); ++// if (os_X_MutexID < 0) { return FALSE; } ++// if (OS_OBTAIN_MUTEX(os_X_MutexID, 1000) == FALSE) { return FALSE; } ++// ... ++// OS_RELEASE_MUTEX(os_X_MutexID); ++// return X; ++// ++ ++#define OS_CREATE_MUTEX(_M_) MsOS_CreateMutex(E_MSOS_FIFO, "OS_"#_M_"_Mutex", MSOS_PROCESS_SHARED) ++#define OS_OBTAIN_MUTEX(_mx, _tm) MsOS_ObtainMutex(_mx, _tm) ++#define OS_RELEASE_MUTEX(_mx) MsOS_ReleaseMutex(_mx) ++#define OS_DELETE_MUTEX(_mx) MsOS_DeleteMutex(_mx) ++#define OS_DELAY_TASK(_msec) MsOS_DelayTask(_msec) ++#define OS_SYSTEM_TIME() MsOS_GetSystemTime() ++#define OS_ENTER_CRITICAL() MsOS_DisableAllInterrupts(); ++#define OS_EXIT_CRITICAL() MsOS_EnableAllInterrupts(); ++ ++//------------------------------------------------------------------------------------------------- ++// Virutal/Physial address operation ++//------------------------------------------------------------------------------------------------- ++MS_U32 MsOS_VA2PA(MS_U32 addr); ++MS_U32 MsOS_PA2KSEG0(MS_U32 addr); ++MS_U32 MsOS_PA2KSEG1_1(MS_U32 addr); ++void MsOS_FlushMemory(void); ++void MsOS_ReadMemory(void); ++ ++#define MS_VA2PA(_addr_) (MS_U32)MsOS_VA2PA((_addr_)) ++#define MS_PA2KSEG0(_addr_) (MS_U32)MsOS_PA2KSEG0((_addr_)) ++#define MS_PA2KSEG1(_addr_) (MS_U32)MsOS_PA2KSEG1_1((_addr_)) ++ ++//------------------------------------------------------------------------------------------------- ++// Debug message ++//------------------------------------------------------------------------------------------------- ++#define MS_CRITICAL_MSG(x) x // for dump critical message ++#define MS_FATAL_MSG(fmt,...) printf( "[MS_FATAL]: %s: %d \n" fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__) ++ ++ ++#if defined (MSOS_TYPE_LINUX_KERNEL) ++#define printf(_fmt, _args...) printk(KERN_WARNING _fmt, ## _args) ++//#define printf printk ++#elif defined (MSOS_TYPE_CE) ++ ++typedef const wchar_t* LPCWSTR; ++extern void NKDbgPrintfW(LPCWSTR lpszFmt, ...); ++#define TXT(quote) L##quote ++#define printf(fmt, ...) NKDbgPrintfW(TXT(fmt), __VA_ARGS__) ++ ++#endif ++#if defined (MS_DEBUG) ++ #define MS_DEBUG_MSG(x) x ++#elif defined (MS_OPTIMIZE) ++ #define MS_DEBUG_MSG(x) // retail version remove debug message ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// debug ++//------------------------------------------------------------------------------------------------- ++extern void MsOS_RegMyDbg(void); ///< MsOS debug register itself debug ++ ++typedef MS_BOOL (*UartDbg_IP_CallBack) (int argc, char *argv[]); ///< MsOS debug call back function prototype ++ ++///< define your own name, help, callback mapping here ++typedef struct ++{ ++ const char *Func_Name; ++ const char *Func_Help; ++ UartDbg_IP_CallBack pCallBack; ++} MS_DBG_LINK; ++ ++///< for application to pass debug command into MsOS debug module ++extern MS_BOOL MsOS_Dbg_ParseCmd(char *Cmd, MS_U32 u32CmdLen); ++ ++///< register your main menu here ++extern MS_BOOL MsOS_Dbg_Regist(const char *Func_Name, const char *Func_Help, MS_DBG_LINK *pAryDbgLink); ++ ++///< for user to handle their own sub menu ++extern MS_BOOL MsOS_Dbg_ExecuteSubCB(const char *Func_Name, int argc, char *argv[], MS_DBG_LINK *pAryDbgLink); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _MS_OS_H_ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ.c b/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ.c +new file mode 100644 +index 00000000..99eff221 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ.c +@@ -0,0 +1,9188 @@ ++// $Change: 628136 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#define _MDRV_PQ_C_ ++ ++ ++#ifdef MSOS_TYPE_LINUX ++#include ++#endif ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++#include "MsCommon.h" ++//#include "MsVersion.h" ++#include "MsOS.h" ++#include "hwreg_utility2.h" ++#include "color_reg.h" ++ ++ ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++#include "drvPQ_Datatypes.h" ++#include "mhal_pq.h" ++#include "drvPQ_Bin.h" ++ ++#include "QualityMode.c" ++ ++ ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++ ++#define PQTAB_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_PQTAB) x; } while(0); ++#define SRULE_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_SRULE) x; } while(0); ++#define CSCRULE_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_CSCRULE) x; } while(0); ++#define PQGRULE_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_GRULE) x; } while(0); ++#define PQBW_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_BW) x; } while(0); ++#define PQMADi_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_MADI) x; } while(0); ++#define PQINFO_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_INFO) x; } while(0); ++#define PQIOCTL_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_IOCTL) x; } while(0); ++#define PQP2P_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_P2P) x; } while(0); ++#define PQCOLOR_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_COLOR) x; } while(0); ++ ++#if PQ_ENABLE_UNUSED_FUNC ++static MSIF_Version _drv_pq_version = { ++ ++ #if (defined( MSOS_TYPE_CE) || defined(MSOS_TYPE_LINUX_KERNEL)) ++ { PQ_DRV_VERSION }, ++ #else ++ .DDI = { PQ_DRV_VERSION }, ++ #endif ++}; ++ ++static MS_BOOL _bColorRange0_255[PQ_MAX_WINDOW]; ++static MS_BOOL _bPointToPointMode = FALSE; ++static MS_BOOL _bDS_En = FALSE; ++static MS_U16 _u16RW_Method = 0; ++ ++#endif ++ ++#if PQ_ENABLE_DEBUG ++MS_BOOL _u16DbgSwitch = 1; ++#endif ++ ++static MS_U16 _u16PQSrcType[PQ_MAX_WINDOW]; ++MS_U16 _u16PQSrcType_DBK_Detect[PQ_MAX_WINDOW]; //For Auto_DBK SW driver used ++ ++static PQ_INPUT_SOURCE_TYPE _enInputSourceType[PQ_MAX_WINDOW]; ++ ++ ++//whether current status is Point-to-point mode ++ ++static MS_U16 _u16PQDbgSwitch = 0; ++ ++ ++ ++typedef struct ++{ ++ // input timing ++ MS_U16 u16input_hsize; ++ MS_U16 u16input_vtotal; ++ MS_U16 u16input_vfreq; ++ ++ // output timing ++ MS_U16 u16output_hsize; ++ MS_U16 u16output_vtotal; ++ MS_U16 u16output_vfreq; ++ ++ // memory format ++ MS_BOOL bFBL; ++ MS_BOOL bMemFmt422; ++ MS_BOOL bInterlace; ++ MS_BOOL b4RMode; ++ MS_U8 u8BitsPerPixel; ++ ++ // osd ++ MS_BOOL bOSD_On; ++ MS_U16 u16OSD_hsize; ++ MS_U8 u8OSD_BitsPerPixel; ++ ++ // dram ++ MS_U32 u32MemBW; ++ MS_BOOL bSC_MIUSel; ++ MS_BOOL bGOP_MIUSel; ++ MS_BOOL bDDR2; ++ MS_U32 u32DDRFreq; ++ MS_U8 u8BusWidth; ++ MS_U32 u32Miu0MemSize; ++ MS_U32 u32Miu1MemSize; ++ ++ // PVR ++ MS_U32 u32PVR_BW; ++ ++ //AEON ++ MS_U32 u32MISC_BW; ++} BW_INFO_t; ++ ++#if (PQ_ENABLE_PIP) ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++static PQ_DISPLAY_TYPE genDisplayType = PQ_DISPLAY_ONE; ++#endif ++#endif ++ ++#if (defined( MSOS_TYPE_CE) || defined(MSOS_TYPE_LINUX_KERNEL)) ++#if PQ_ENABLE_UNUSED_FUNC ++static MS_PQ_INFO _info = {128, 217}; ++static MS_PQ_RFBL_INFO _stRFBL_Info = {FALSE, FALSE, 0 }; ++#endif ++static MS_PQ_Status _status = {FALSE, FALSE, }; ++ ++#else ++static MS_PQ_INFO _info = {.u16Input_Src_Num = 128, .u8IP_Num = 217,}; ++static MS_PQ_Status _status = {.bIsInitialized = FALSE, .bIsRunning = FALSE, }; ++static MS_PQ_RFBL_INFO _stRFBL_Info = {.bEnable = FALSE, .bFilm = FALSE , .u8MADiType = 0, }; ++#endif ++ ++//static BW_INFO_t bw_info; ++ ++ ++#if(ENABLE_PQ_BIN) ++static MS_BOOL gbPQBinEnable = 0; ++MS_PQBin_Header_Info stPQBinHeaderInfo[MAX_PQ_BIN_NUM]; ++extern MS_PQTextBin_Header_Info stPQTextBinHeaderInfo[MAX_PQ_TEXT_BIN_NUM]; ++//extern MS_BOOL gbEnablePQTextBin; ++#endif ++ ++MS_S32 _PQ_Mutex = -1; ++ ++#ifdef MSOS_TYPE_LINUX ++pthread_mutex_t _PQ_MLoad_Mutex; ++#endif ++ ++////////////////////////////////////////////////////////////////// ++// PQ Patch ++MS_BOOL _bOSD_On = FALSE; ++ ++#if PQ_ENABLE_UNUSED_FUNC ++static MS_BOOL bSetFrameCount = TRUE; ++#endif ++ ++#if 0 //def _PDEBUG ++#define PTH_PQ_RET_CHK(_pf_) \ ++ ({ \ ++ int r = _pf_; \ ++ if (r != 0 && r != ETIMEDOUT) \ ++ fprintf(stderr, "[PTHREAD] %s: %d: %s: %s\r\n", __FILE__, __LINE__, #_pf_, strerror(r)); \ ++ r; \ ++ }) ++#else ++#define PTH_PQ_RET_CHK(_pf_) //_pf_ ++#endif ++ ++ ++#ifdef MSOS_TYPE_LINUX ++#define PQ_MLOAD_ENTRY() PTH_PQ_RET_CHK(pthread_mutex_lock(&_PQ_MLoad_Mutex)) ++#define PQ_MLOAD_RETURN() PTH_PQ_RET_CHK(pthread_mutex_unlock(&_PQ_MLoad_Mutex)) ++#else ++#define PQ_MLOAD_ENTRY() ++#define PQ_MLOAD_RETURN() ++#endif ++ ++////////////////////////////////////////////////////////////////// ++// OS related ++// ++// ++#define XC_PQ_WAIT_MUTEX (TICK_PER_ONE_MS * 50) // 50 ms ++ ++/* ++// Mutex & Lock ++static MS_S32 _s32XC_PQMutex = -1; ++ ++ ++#define XC_PQ_ENTRY() { if (_s32XC_PQMutex < 0) { return E_XC_ACE_FAIL; } \ ++ if(OS_OBTAIN_MUTEX(_s32XC_PQMutex, XC_PQ_WAIT_MUTEX) == FALSE) return E_XC_ACE_OBTAIN_MUTEX_FAIL; } ++ ++#define XC_PQ_RETURN(_ret) { OS_RELEASE_MUTEX(_s32XC_PQMutex); return _ret; } ++*/ ++ ++////////////////////////////////////////////////////////////////// ++void _MDrv_PQ_Clear_SRAM_Table_Index(void) ++{ ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Clear_SRAM_Table_Index(); ++ } ++ else ++#endif ++ { ++ MDrv_PQ_ClearTableIndex(MAIN); ++ #if ENABLE_PQ_EX ++ MDrv_PQ_ClearTableIndex(MAINEX); ++ #endif ++ ++ #if PQ_ENABLE_PIP ++ MDrv_PQ_ClearTableIndex(SUB); ++ MDrv_PQ_ClearTableIndex(SUBEX); ++ #endif ++ ++ #if ENABLE_MULTI_SCALER ++ ++ MDrv_PQ_ClearTableIndex(SC1_MAIN); ++ MDrv_PQ_ClearTableIndex(SC1_MAINEX); ++ ++ MDrv_PQ_ClearTableIndex(SC2_MAIN); ++ MDrv_PQ_ClearTableIndex(SC2_MAINEX); ++ MDrv_PQ_ClearTableIndex(SC2_SUB); ++ MDrv_PQ_ClearTableIndex(SC2_SUBEX); ++ #endif ++ } ++} ++ ++MS_BOOL MDrv_PQ_Init(MS_PQ_Init_Info *pstPQInitInfo) ++{ ++ PQTABLE_INFO PQTableInfo; ++#if(ENABLE_PQ_BIN) ++ MS_U8 i; ++ MS_U8 u8ID; ++#endif ++ if(_PQ_Mutex != -1) ++ { ++ printf("%s, already init\n", __FUNCTION__); ++ return TRUE; ++ } ++ ++ _PQ_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "_PQ_Mutex", MSOS_PROCESS_SHARED); ++ ++ if(_PQ_Mutex == -1) ++ { ++ (printf("[MAPI PQ][%06d] create mutex fail\r\n", __LINE__)); ++ return FALSE; ++ } ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTableInfo)); ++ ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ PTH_PQ_RET_CHK(pthread_mutexattr_t attr); ++ PTH_PQ_RET_CHK(pthread_mutexattr_init(&attr)); ++ PTH_PQ_RET_CHK(pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE)); ++ PTH_PQ_RET_CHK(pthread_mutex_init(&_PQ_MLoad_Mutex, &attr)); ++ #endif ++#endif ++ ++ _status.bIsInitialized = TRUE; ++ _status.bIsRunning = TRUE; ++ ++ _MDrv_PQ_Clear_SRAM_Table_Index(); ++ ++#if(ENABLE_PQ_BIN) ++ if(pstPQInitInfo->u8PQTextBinCnt) ++ { ++ //gbEnablePQTextBin = 1; ++ for(i = 0; i < pstPQInitInfo->u8PQTextBinCnt; i++) ++ { ++ #if PQ_ENABLE_UNUSED_FUNC ++ u8ID = pstPQInitInfo->stPQTextBinInfo[i].u8PQID; ++ stPQTextBinHeaderInfo[u8ID].u8BinID = pstPQInitInfo->stPQTextBinInfo[i].u8PQID; ++ #if !defined(MSOS_TYPE_LINUX) && !defined(MSOS_TYPE_LINUX_KERNEL) ++ stPQTextBinHeaderInfo[u8ID].u32BinStartAddress = MS_PA2KSEG0(pstPQInitInfo->stPQTextBinInfo[i].PQBin_PhyAddr); ++ #else ++ stPQTextBinHeaderInfo[u8ID].u32BinStartAddress = /*MS_PA2KSEG0*/(pstPQInitInfo->stPQTextBinInfo[i].PQBin_PhyAddr); ++ #endif ++ if(MDrv_PQTextBin_Parsing(&stPQTextBinHeaderInfo[u8ID]) == FALSE) ++ { ++ printf("MDrv_PQTextBin_Parsing: Parsing Fail, ID=%d \n", i); ++ return FALSE; ++ } ++ #endif ++ } ++ ++ } ++ else ++ { ++ //printf("NonPQBin_Text !!\r\n"); ++ //gbEnablePQTextBin = 0; ++ } ++ ++ if(pstPQInitInfo->u8PQBinCnt) ++ { ++ printf("Start PQ Bin Init \n"); ++ gbPQBinEnable = 1; ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, MAIN_WINDOW); ++ #if PQ_ENABLE_PIP ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SUB_WINDOW); ++ #endif ++ ++ #if ENABLE_MULTI_SCALER ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SC1_MAIN_WINDOW); ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SC2_MAIN_WINDOW); ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SC2_SUB_WINDOW); ++ #endif ++ ++ switch(pstPQInitInfo->u16PnlWidth) ++ { ++ default: ++ case 1366: ++ MDrv_PQBin_SetPanelID(1, MAIN_WINDOW); ++ #if PQ_ENABLE_PIP ++ MDrv_PQBin_SetPanelID(1, SUB_WINDOW); ++ #endif ++ #if ENABLE_MULTI_SCALER ++ MDrv_PQBin_SetPanelID(1, SC2_MAIN_WINDOW); ++ MDrv_PQBin_SetPanelID(1, SC2_SUB_WINDOW); ++ MDrv_PQBin_SetPanelID(0, SC1_SUB_WINDOW); ++ #endif ++ break; ++ ++ case 1920: ++ MDrv_PQBin_SetPanelID(1, MAIN_WINDOW); ++ #if PQ_ENABLE_PIP ++ MDrv_PQBin_SetPanelID(1, SUB_WINDOW); ++ #endif ++ #if ENABLE_MULTI_SCALER ++ MDrv_PQBin_SetPanelID(1, SC2_MAIN_WINDOW); ++ MDrv_PQBin_SetPanelID(1, SC2_SUB_WINDOW); ++ MDrv_PQBin_SetPanelID(0, SC1_SUB_WINDOW); ++ #endif ++ break; ++ } ++ ++ //because main and sub's common table may be different, ++ //so we will take main's common table as correct one. ++ //so here load sub first and then use main's overwrite sub's ++ //Sub first ++ for(i = 0; i < MAX_PQ_BIN_NUM; i++) ++ { ++ if(pstPQInitInfo->stPQBinInfo[i].PQ_Bin_BufSize > 0) ++ { ++ PQ_WIN ePQWin; ++ u8ID = pstPQInitInfo->stPQBinInfo[i].u8PQID; ++ ePQWin = MDrv_PQBin_TransToPQWin(u8ID); ++ stPQBinHeaderInfo[u8ID].u8BinID = (MS_U8)pstPQInitInfo->stPQBinInfo[i].u8PQID; ++ stPQBinHeaderInfo[u8ID].u32BinStartAddress = (MS_U32)(pstPQInitInfo->stPQBinInfo[i].PQBin_PhyAddr); ++ MDrv_PQBin_Parsing(&stPQBinHeaderInfo[u8ID]); ++ MDrv_PQBin_LoadCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(ePQWin), &stPQBinHeaderInfo[u8ID]); ++ } ++ else ++ { ++ printf("MDrv_PQ_Init() Error: PQ_Bin_BufSize < 0 !! \r\n"); ++ } ++ } ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ //PQTableInfo = PQTableInfo; ++ #if(ENABLE_PQ_BIN) ++ gbPQBinEnable = 1; ++ #endif ++ ++ #else ++ MS_BOOL bSkipCommTable = TRUE; ++ ++ //printf("NonPQBin !! \r\n"); ++ #if(ENABLE_PQ_BIN) ++ gbPQBinEnable = 0; ++ #endif ++ ++ ++ MDrv_PQ_Set_DisplayType_Main(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ #if (PQ_ENABLE_PIP) ++ MDrv_PQ_Set_DisplayType_Sub(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Sub(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Main(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ ++ MDrv_PQ_Set_DisplayType_SC1_Main(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ #endif ++ ++ #if(ENABLE_PQ_LOAD_TABLE_INFO) ++ MDrv_PQ_PreInitLoadTableInfo(MAIN); ++ ++ #if ENABLE_PQ_EX ++ MDrv_PQ_PreInitLoadTableInfo(MAINEX); ++ #endif ++ ++ #if PQ_ENABLE_PIP ++ MDrv_PQ_PreInitLoadTableInfo(SUB); ++ MDrv_PQ_PreInitLoadTableInfo(SUBEX); ++ #endif ++ #endif ++ ++ #endif // end of #if(PQ_ONLY_SUPPORT_BIN == 0) ++ ++ } ++ ++#if 0 ++ // Set BK12 [40] [1:0] = b'11 to enable hw double buffer write ++ // at blanking area for changing memory format by L_BK_SCMI(0x02) ++ // this register is added after T2 U04 ++ Hal_PQ_set_memfmt_doublebuffer(PQ_MAIN_WINDOW, ENABLE); ++#if ENABLE_MULTI_SCALER ++ Hal_PQ_set_memfmt_doublebuffer(PQ_SC1_MAIN_WINDOW, ENABLE); ++ Hal_PQ_set_memfmt_doublebuffer(PQ_SC2_MAIN_WINDOW, ENABLE); ++#endif ++ ++ MsOS_Memcpy(&_stPQ_Info, pstPQInitInfo, sizeof(MS_PQ_Init_Info)); ++ ++ MsOS_Memset(&bw_info, 0x00, sizeof(bw_info)); ++ bw_info.bDDR2 = pstPQInitInfo->bDDR2; ++ bw_info.u32DDRFreq = pstPQInitInfo->u32DDRFreq; ++ bw_info.u8BusWidth = pstPQInitInfo->u8BusWidth; ++ bw_info.u16output_vtotal = pstPQInitInfo->u16Pnl_vtotal; ++ bw_info.u16output_hsize = pstPQInitInfo->u16PnlWidth; ++ bw_info.u16OSD_hsize = pstPQInitInfo->u16OSD_hsize; ++ bw_info.u32Miu0MemSize = pstPQInitInfo->u32miu0em_size; ++ bw_info.u32Miu1MemSize = pstPQInitInfo->u32miu1em_size; ++ ++ for(i = 0; i < PQ_MAX_WINDOW; i++) ++ _bColorRange0_255[i] = TRUE; ++#endif ++ ++#if (PQ_ENABLE_PIP) ++ #if (PQ_ONLY_SUPPORT_BIN == 0) ++ genDisplayType = PQ_DISPLAY_ONE; ++ #endif ++#endif ++ ++ return TRUE; ++} ++ ++void MDrv_PQ_DesideSrcType(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType) ++{ ++ _enInputSourceType[eWindow] = enInputSourceType; ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ _u16PQSrcType_DBK_Detect[eWindow] = _u16PQSrcType[eWindow]; //For Auto_DBK SW driver used ++ PQTAB_DBG(printf("[PQ_DesideSrcType] window=%u, enInputSrcType=%u, SrcType=%u\r\n", ++ eWindow, enInputSourceType, _u16PQSrcType[eWindow])); ++ ++ Hal_PQ_set_sourceidx(eWindow, _u16PQSrcType[eWindow]); ++ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(MAIN, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(MAINEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SUB, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SUBEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC1_MAIN, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC1_MAINEX, _u16PQSrcType[eWindow]); ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_MAIN, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_MAINEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_SUB, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_SUBEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#endif ++ ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ ++ } ++ ++#endif //#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_Main(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_Main: QMAP_1920_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_NR_Main: MST_GRule_1920_NR_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_MPEG_NR_Main:MST_GRule_1920_MPEG_NR_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_FILM_MODE_Main:MST_GRule_1920_FILM_MODE_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DYNAMIC_CONTRAST_Main:MST_GRule_1920_DYNAMIC_CONTRAST_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_ULTRAT_CLEAR_Main:MST_GRule_1920_ULTRAT_CLEAR_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DDR_SELECT_Main:MST_GRule_1920_DDR_SELECT_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_OSD_BW_Main:MST_GRule_1920_OSD_BW_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PTP_Main:MST_GRule_1920_PTP_Main); ++#endif ++ break; ++#if PQ_ENABLE_PIP ++ case PQ_DISPLAY_PIP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_PIP_Main: QMAP_1920_PIP_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_NR_Main: MST_GRule_1920_PIP_NR_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_MPEG_NR_Main:MST_GRule_1920_PIP_MPEG_NR_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_FILM_MODE_Main:MST_GRule_1920_PIP_FILM_MODE_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DYNAMIC_CONTRAST_Main:MST_GRule_1920_PIP_DYNAMIC_CONTRAST_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_ULTRAT_CLEAR_Main:MST_GRule_1920_PIP_ULTRAT_CLEAR_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DDR_SELECT_Main:MST_GRule_1920_PIP_DDR_SELECT_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_OSD_BW_Main:MST_GRule_1920_PIP_OSD_BW_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_PTP_Main:MST_GRule_1920_PIP_PTP_Main); ++#endif ++ ++ break; ++ ++ case PQ_DISPLAY_POP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_POP_Main: QMAP_1920_POP_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_NR_Main: MST_GRule_1920_POP_NR_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_MPEG_NR_Main:MST_GRule_1920_POP_MPEG_NR_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_FILM_MODE_Main:MST_GRule_1920_POP_FILM_MODE_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DYNAMIC_CONTRAST_Main:MST_GRule_1920_POP_DYNAMIC_CONTRAST_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_ULTRAT_CLEAR_Main:MST_GRule_1920_POP_ULTRAT_CLEAR_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DDR_SELECT_Main:MST_GRule_1920_POP_DDR_SELECT_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_OSD_BW_Main:MST_GRule_1920_POP_OSD_BW_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_PTP_Main:MST_GRule_1920_POP_PTP_Main); ++#endif ++ break; ++#endif ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_MAIN_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Main; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_Main; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Main; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_Main; ++ ++#if PQ_ENABLE_HSDRULE ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_Main; ++#endif ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_Main; ++#if PQ_ENABLE_CSCRULE ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_Main; ++#endif ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_Main; ++#endif ++ ++#if (PQ_ENABLE_HSDRULE) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_Main; ++#endif ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_Main; ++#if (PQ_ENABLE_CSCRULE) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_Main; ++#endif ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_Main; ++#endif ++ ++#if (PQ_ENABLE_HSDRULE) ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_Main; ++#endif ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_Main; ++ ++#if (PQ_ENABLE_CSCRULE) ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_Main; ++#endif ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_Main; ++#endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_Main; ++#endif ++ ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_Main; ++#endif ++ ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_Main; ++#endif ++ ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_Main; ++#endif ++ ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_Main; ++#endif ++ ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_Main; ++#endif ++ ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_Main; ++#endif ++ ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_PTP] = PQ_GRULE_PTP_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_PTP] = PQ_GRULE_PTP_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_PTP] = (void*)MST_GRule_PTP_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_PTP] = (void*)MST_GRule_PTP_Main; ++#endif ++ ++ MDrv_PQ_AddTable_(MAIN, &PQTableInfo); ++ ++ if(!bSkipCommTable) ++ { ++#if (PQ_ENABLE_UNUSED_FUNC) ++ MDrv_PQ_LoadCommTable_(MAIN); ++#endif ++ } ++ ++#if (ENABLE_PQ_EX) ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Main_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_Main_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Main_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_Main_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Main_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++#if PQ_ENABLE_PIP ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Main_Ex; ++ } ++#endif ++ break; ++ ++ case PQ_DISPLAY_POP: ++#if PQ_ENABLE_PIP ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Main_Ex; ++ } ++#endif ++ break; ++ } ++ ++ MDrv_PQ_AddTable_(MAINEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(MAINEX); ++ } ++ if((MS_U16)QM_INPUTTYPE_NUM_Main != (MS_U16)QM_INPUTTYPE_NUM_Main_Ex) ++ { ++ printf("PQ INPUTTYPE NUM MISMATCH: MAIN != EX"); ++ MS_ASSERT(0); ++ } ++#endif ++ return TRUE; ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++#endif ++} ++ ++void MDRv_PQ_Check_Type(PQ_WIN eWindow, PQ_CHECK_TYPE EnCheck) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Check_Type_(MAIN, EnCheck); ++ ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MDRv_PQ_Set_CmdqCfg(PQ_WIN eWindow, MS_BOOL bEnCMDQ, MS_U8 u8FmCnt,MS_BOOL bFire) ++{ ++ PQ_DBG(printf("%s %d, Win:%d, CMDQEn:%d, FmCnt:%d", __FUNCTION__, __LINE__, eWindow, bEnCMDQ, u8FmCnt)); ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ PQ_CMDQ_CONFIG CmdqCfg; ++ ++ CmdqCfg.bEnFmCnt = bEnCMDQ; ++ CmdqCfg.u8FmCnt = u8FmCnt; ++ CmdqCfg.bfire = bFire; ++ MDrv_PQ_Set_CmdqCfg_(MAIN, CmdqCfg); ++ ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++} ++void MDrv_PQ_init_RIU(MS_U32 riu_addr) ++{ ++ Hal_PQ_init_riu_base(riu_addr); ++} ++ ++void MDrv_PQ_LoadSettingByData(PQ_WIN eWindow, MS_U8 u8PQIPIdx, MS_U8 *pData, MS_U16 u16DataSize) ++{ ++ PQ_DBG(printf("%s %d, Win:%d, IPIdx:%d, Size%d \n", __FUNCTION__, __LINE__, eWindow, u8PQIPIdx, u16DataSize)); ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ PQ_DATA_INFO DataInfo; ++ ++ DataInfo.pBuf = pData; ++ DataInfo.u16BufSize = u16DataSize; ++ MDrv_PQ_LoadTableByData_(MAIN, _u16PQSrcType[eWindow], u8PQIPIdx, &DataInfo); ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++} ++ ++ ++void MDrv_PQ_LoadSettings(PQ_WIN eWindow) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_MAIN]); ++ ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("MAIN table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#if(ENABLE_PQ_EX == 1) ++ PQTAB_DBG(printf("MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, MDrv_PQ_GetTableIndex(eWindow, PQ_IP_UC_CTL_Main), PQ_IP_UC_CTL_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SUB table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ ++ PQTAB_DBG(printf("SUB MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SC1_MAIN]); ++ ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SC1_MAIN table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC1_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#if(ENABLE_PQ_EX == 1) ++ PQTAB_DBG(printf("SC2_MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC1_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, MDrv_PQ_GetTableIndex(eWindow, PQ_IP_UC_CTL_SC1_Main), PQ_IP_UC_CTL_SC1_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SC2_MAIN]); ++ ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SC2_MAIN table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#if(ENABLE_PQ_EX == 1) ++ PQTAB_DBG(printf("SC2_MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, MDrv_PQ_GetTableIndex(eWindow, PQ_IP_UC_CTL_SC2_Main), PQ_IP_UC_CTL_SC2_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SC2_SUB table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ ++ PQTAB_DBG(printf("SC2_SUB MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ } ++#endif ++ ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_MAIN); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_MAIN_EX); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SUB); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SUB_EX); ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC1_MAIN); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC1_MAIN_EX); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_MAIN); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_MAIN_EX); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_SUB); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_SUB_EX); ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++#endif ++} ++ ++#if (PQ_ENABLE_UNUSED_FUNC) ++ ++MS_BOOL MDrv_PQ_Exit(void) ++{ ++ _MDrv_PQ_Clear_SRAM_Table_Index(); ++ return true; ++} ++ ++MS_U16 MDrv_PQ_GetIPNum(PQ_WIN eWindow) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(MAIN); ++#endif ++ } ++ } ++ ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SUB); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ // SC1_MAIN ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SC1_MAIN); ++#endif ++ } ++ } ++ // SC2_MAIN ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SC2_MAIN); ++#endif ++ } ++ } ++ // SC2_SUB ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SC2_SUB); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ ++ else ++ { ++ MS_ASSERT(0); ++ return 0xFFFF; ++ } ++} ++ ++MS_U16 MDrv_PQ_GetTableNum(PQ_WIN eWindow, MS_U16 u16PQIPIdx) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ UNUSED(u16PQIPIdx); ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ UNUSED(u16PQIPIdx); ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SC1_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ UNUSED(u16PQIPIdx); ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SC2_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SC2_SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++#endif //ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ return 0xFFFF; ++ } ++} ++ ++MS_U16 MDrv_PQ_GetCurrentTableIndex(PQ_WIN eWindow, MS_U16 u16PQIPIdx) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), u16PQIPIdx, PQ_BIN_STD_MAIN); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), u16PQIPIdx, PQ_BIN_STD_SUB); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), u16PQIPIdx, PQ_BIN_STD_SC1_MAIN); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SC1_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), u16PQIPIdx, PQ_BIN_STD_SC2_MAIN); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SC2_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), u16PQIPIdx, PQ_BIN_STD_SC2_SUB); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SC2_SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ return 0xFFFF; ++ } ++} ++ ++//Get main page setting from u16IPIdx(column), according to current input source type(row) ++MS_U16 MDrv_PQ_GetTableIndex(PQ_WIN eWindow, MS_U16 u16IPIdx) ++{ ++ MS_U8 u16TabIdx = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(MAIN, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SUB, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SC1_MAIN, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SC2_MAIN, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SC2_SUB, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16TabIdx; ++} ++ ++static MS_U16 MDrv_PQ_GetXRuleIPIndex(PQ_WIN eWindow, MS_U16 u16XRuleType, MS_U16 u16XRuleIP) ++{ ++ MS_U8 u16IPIdx = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SC1_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SC2_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SC2_SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16IPIdx; ++} ++ ++static MS_U16 MDrv_PQ_GetXRuleTableIndex(PQ_WIN eWindow, MS_U16 u16XRuleType, MS_U16 u16XRuleIdx, MS_U16 u16XRuleIP) ++{ ++ MS_U16 u16TabIdx = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SC1_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SC2_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SC2_SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++ ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16TabIdx; ++} ++ ++static MS_U16 MDrv_PQ_GetXRuleIPNum(PQ_WIN eWindow, MS_U16 u16XRuleType) ++{ ++ MS_U16 u16IPNum = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(MAIN, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SUB, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SC1_MAIN, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SC2_MAIN, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SC2_SUB, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16IPNum; ++} ++ ++#if (PQ_GRULE_NR_ENABLE || PQ_GRULE_OSD_BW_ENABLE) ++static MS_U16 MDrv_PQ_GetGRule_LevelIndex(PQ_WIN eWindow, MS_U16 u16GRuleType, MS_U16 u16GRuleLevelIndex) ++{ ++ MS_U16 u16Ret = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SC1_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SC2_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SC2_SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16Ret; ++} ++ ++static MS_U16 MDrv_PQ_GetGRule_IPIndex(PQ_WIN eWindow, MS_U16 u16GRuleType, MS_U16 u16GRuleIPIndex) ++{ ++ MS_U16 u16Ret = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SC1_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SC2_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SC2_SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++ return u16Ret; ++} ++ ++static MS_U16 MDrv_PQ_GetGRule_TableIndex(PQ_WIN eWindow, MS_U16 u16GRuleType, MS_U16 u16PQ_NRIdx, MS_U16 u16GRuleIPIndex) ++{ ++ MS_U16 u16Ret = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)MDrv_PQ_GetGRule_TableIndex_(MAIN, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)(MDrv_PQ_GetGRule_TableIndex_(SUB, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex)); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)MDrv_PQ_GetGRule_TableIndex_(SC1_MAIN, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)MDrv_PQ_GetGRule_TableIndex_(SC2_MAIN, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)(MDrv_PQ_GetGRule_TableIndex_(SC2_SUB, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex)); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++ return u16Ret; ++} ++#endif ++ ++ ++void MDrv_PQ_LoadTableData(PQ_WIN eWindow, MS_U16 u16TabIdx, MS_U16 u16PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SC1_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SC2_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SC2_SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MDrv_PQ_LoadTable(PQ_WIN eWindow, MS_U16 u16TabIdx, MS_U16 u16PQIPIdx) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SC1_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SC2_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SC2_SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MDrv_PQ_CheckSettings(PQ_WIN eWindow) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo MAINEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if(ENABLE_PQ_EX) ++ MDrv_PQ_CheckCommTable_(MAINEX); ++ MDrv_PQ_CheckTableBySrcType_(MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ MDrv_PQ_CheckCommTable_(MAIN); ++ MDrv_PQ_CheckTableBySrcType_(MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo SUBEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_CheckCommTable_(SUBEX); ++ MDrv_PQ_CheckTableBySrcType_(SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ MDrv_PQ_CheckCommTable_(SUB); ++ MDrv_PQ_CheckTableBySrcType_(SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo MAINEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if(ENABLE_PQ_EX) ++ MDrv_PQ_CheckCommTable_(SC1_MAINEX); ++ MDrv_PQ_CheckTableBySrcType_(SC1_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ MDrv_PQ_CheckCommTable_(SC1_MAIN); ++ MDrv_PQ_CheckTableBySrcType_(SC1_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo MAINEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if(ENABLE_PQ_EX) ++ MDrv_PQ_CheckCommTable_(SC2_MAINEX); ++ MDrv_PQ_CheckTableBySrcType_(SC2_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ MDrv_PQ_CheckCommTable_(SC2_MAIN); ++ MDrv_PQ_CheckTableBySrcType_(SC2_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo SUBEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_CheckCommTable_(SC2_SUBEX); ++ MDrv_PQ_CheckTableBySrcType_(SC2_SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ MDrv_PQ_CheckCommTable_(SC2_SUB); ++ MDrv_PQ_CheckTableBySrcType_(SC2_SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++ ++#if(ENABLE_PQ_MLOAD) ++void MDrv_PQ_Set_MLoadEn(PQ_WIN eWindow, MS_BOOL bEn) ++{ ++ if(MApi_XC_MLoad_GetStatus(eWindow) != E_MLOAD_ENABLED) ++ { ++ bEn = FALSE; ++ } ++ ++ if(bEn) ++ { ++ PQ_MLOAD_ENTRY(); ++ } ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(MAIN, bEn); ++#endif ++ } ++ ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SUB, bEn); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SC1_MAIN, bEn); ++#endif ++ } ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SC2_MAIN, bEn); ++#endif ++ } ++ ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SC2_SUB, bEn); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++ ++ if(bEn == FALSE) ++ { ++ PQ_MLOAD_RETURN(); ++ } ++} ++#endif ++ ++ ++ ++void MDrv_PQ_Set_DTVInfo(PQ_WIN eWindow, MS_PQ_Dtv_Info *pstPQDTVInfo) ++{ ++ MsOS_Memcpy(&_stDTV_Info[eWindow], pstPQDTVInfo, sizeof(MS_PQ_Dtv_Info)); ++ ++ PQINFO_DBG(printf("PQ DTV Info:Win=%u, type=%u\r\n", eWindow, _stDTV_Info[eWindow].eType)); ++} ++ ++void MDrv_PQ_Set_MultiMediaInfo(PQ_WIN eWindow, MS_PQ_MuliMedia_Info *pstPQMMInfo) ++{ ++ MsOS_Memcpy(&_stMultiMedia_Info[eWindow], pstPQMMInfo, sizeof(MS_PQ_MuliMedia_Info)); ++ PQINFO_DBG(printf("PQ MM Info:Win=%u, type=%u\r\n", eWindow, _stMultiMedia_Info[eWindow].eType)); ++} ++ ++void MDrv_PQ_Set_VDInfo(PQ_WIN eWindow, MS_PQ_Vd_Info *pstPQVDInfo) ++{ ++ MsOS_Memcpy(&_stVD_Info[eWindow], pstPQVDInfo, sizeof(MS_PQ_Vd_Info)); ++ ++ PQINFO_DBG(printf("PQ VD Info:Win=%u, SigType=%u, bSCARTRGB=%u, VIFIn=%u\r\n", ++ eWindow, ++ _stVD_Info[eWindow].enVideoStandard, ++ _stVD_Info[eWindow].bIsSCART_RGB, ++ _stVD_Info[eWindow].bIsVIFIN)); ++ ++} ++ ++void MDrv_PQ_Set_ModeInfo(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info *pstPQModeInfo) ++{ ++ ++ MsOS_Memcpy(&_stMode_Info[eWindow], pstPQModeInfo, sizeof(MS_PQ_Mode_Info)); ++ ++ //printf("PQ Set Mode Info: %s, Src=%x\r\n", (eWindow)?("SubWin"):("MainWin"), enInputSourceType); ++ ++ if(QM_IsSourceYPbPr(enInputSourceType)) ++ { ++ if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 720))) && ++ (pstPQModeInfo->u16input_vsize < 500) && ++ (pstPQModeInfo->u16input_vfreq < 650)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x480_60I : ++ PQ_MD_720x480_60P; ++ ++ } ++ else if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 720))) && ++ (pstPQModeInfo->u16input_vsize < 600) && ++ (pstPQModeInfo->u16input_vfreq < 550)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x576_50I : ++ PQ_MD_720x576_50P; ++ } ++ else if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 1280)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 1280)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 1280)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 1280))) && ++ (pstPQModeInfo->u16input_vsize < 800) && ++ (pstPQModeInfo->bInterlace == FALSE)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1280x720_50P : ++ PQ_MD_1280x720_60P; ++ ++ } ++ else if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 1920)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 1920)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 1920)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 1920))) && ++ (pstPQModeInfo->u16input_vsize < 1100)) ++ { ++ if(pstPQModeInfo->bInterlace) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1920x1080_50I : ++ PQ_MD_1920x1080_60I; ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 245) ? PQ_MD_1920x1080_24P : ++ (pstPQModeInfo->u16input_vfreq < 270) ? PQ_MD_1920x1080_25P : ++ (pstPQModeInfo->u16input_vfreq < 350) ? PQ_MD_1920x1080_30P : ++ (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1920x1080_50P : ++ PQ_MD_1920x1080_60P; ++ ++ } ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = PQ_MD_720x576_50I; ++ } ++ } ++ else if(QM_IsSourceHDMI(enInputSourceType)) ++ { ++ if((pstPQModeInfo->u16input_hsize < 1500) && ++ (pstPQModeInfo->u16input_vsize < 500) && ++ (pstPQModeInfo->u16input_vfreq < 650)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x480_60I : ++ PQ_MD_720x480_60P; ++ ++ } ++ else if((pstPQModeInfo->u16input_hsize < 1500) && ++ (pstPQModeInfo->u16input_vsize < 600) && ++ (pstPQModeInfo->u16input_vfreq < 550)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x576_50I : ++ PQ_MD_720x576_50P; ++ } ++ else if((pstPQModeInfo->u16input_hsize < 1300) && ++ (pstPQModeInfo->u16input_vsize < 800) && ++ (pstPQModeInfo->bInterlace == FALSE)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1280x720_50P : ++ PQ_MD_1280x720_60P; ++ ++ } ++ else if((pstPQModeInfo->u16input_hsize < 1930) && ++ (pstPQModeInfo->u16input_vsize < 1100)) ++ { ++ if(pstPQModeInfo->bInterlace) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1920x1080_50I : ++ PQ_MD_1920x1080_60I; ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 245) ? PQ_MD_1920x1080_24P : ++ (pstPQModeInfo->u16input_vfreq < 270) ? PQ_MD_1920x1080_25P : ++ (pstPQModeInfo->u16input_vfreq < 350) ? PQ_MD_1920x1080_30P : ++ (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1920x1080_50P : ++ PQ_MD_1920x1080_60P; ++ ++ } ++ } ++ else if(pstPQModeInfo->u16input_hsize < 1350 && ++ pstPQModeInfo->u16input_vsize < 1550) ++ { ++ //special handle 1280X1470p ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1280x720_50P : ++ PQ_MD_1280x720_60P; ++ } ++ } ++ else if(pstPQModeInfo->u16input_hsize < 1930 && ++ pstPQModeInfo->u16input_vsize < 2300) ++ { ++ //special handle 1920X2205p ++ if(pstPQModeInfo->bInterlace) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1920x1080_50I : ++ PQ_MD_1920x1080_60I; ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 250) ? PQ_MD_1920x1080_24P : ++ (pstPQModeInfo->u16input_vfreq < 350) ? PQ_MD_1920x1080_30P : ++ (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1920x1080_50P : ++ PQ_MD_1920x1080_60P; ++ ++ } ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = PQ_MD_720x576_50I; ++ } ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = PQ_MD_Num; ++ } ++ ++ if(QM_IsSourceYPbPr(enInputSourceType) || QM_IsSourceHDMI(enInputSourceType)) ++ { ++ if(_u8ModeIndex[eWindow] <= (MS_U8)PQ_MD_720x576_50P) ++ _gIsSrcHDMode[eWindow] = 0; ++ else ++ _gIsSrcHDMode[eWindow] = 1; ++ ++ } ++ else ++ { ++ if(pstPQModeInfo->u16input_hsize >= 1200) ++ _gIsSrcHDMode[eWindow] = 1; ++ else ++ _gIsSrcHDMode[eWindow] = 0; ++ } ++ ++ PQINFO_DBG( ++ printf("PQ ModeInfo:%d input(%d, %d), disp(%d, %d), ModeIdx=%d, FBL=%u, Interlace=%u, InV=%u, OutV=%u, inVtt=%u\r\n", ++ eWindow, ++ _stMode_Info[eWindow].u16input_hsize, ++ _stMode_Info[eWindow].u16input_vsize, ++ _stMode_Info[eWindow].u16display_hsize, ++ _stMode_Info[eWindow].u16display_vsize, ++ _u8ModeIndex[eWindow], ++ _stMode_Info[eWindow].bFBL, ++ _stMode_Info[eWindow].bInterlace, ++ _stMode_Info[eWindow].u16input_vfreq, ++ _stMode_Info[eWindow].u16ouput_vfreq, ++ _stMode_Info[eWindow].u16input_vtotal); ++ ); ++ ++} ++ ++void MDrv_PQ_SetHDMIInfo(PQ_WIN eWindow, const MS_PQ_Hdmi_Info* const pstPQHDMIInfo) ++{ ++ _stHDMI_Info[eWindow].bIsHDMI = pstPQHDMIInfo->bIsHDMI; ++ _stHDMI_Info[eWindow].enColorFmt = pstPQHDMIInfo->enColorFmt; ++ ++ PQINFO_DBG(printf("PQ HDMI, bHDMI=%u, colorfmt=%u\r\n", ++ _stHDMI_Info[eWindow].bIsHDMI, ++ _stHDMI_Info[eWindow].enColorFmt)); ++} ++ ++void MDrv_PQ_SetHDMI_PC(PQ_WIN eWindow, MS_BOOL bIsTrue) ++{ ++ _stHDMI_Info[eWindow].bIsHDMIPC = bIsTrue; ++} ++ ++MS_BOOL MDrv_PQ_GetHDMI_PC_Status(PQ_WIN eWindow) ++{ ++ return _stHDMI_Info[eWindow].bIsHDMIPC; ++} ++ ++ ++ ++PQ_INPUT_SOURCE_TYPE MDrv_PQ_GetInputSourceType(PQ_WIN eWindow) ++{ ++ return _enInputSourceType[eWindow]; ++} ++ ++MS_U16 MDrv_PQ_GetSrcType(PQ_WIN eWindow) ++{ ++ return _u16PQSrcType[eWindow]; ++} ++ ++// if not HSD case, ignore return value ++static MS_BOOL _MDrv_PQ_LoadScalingTable(PQ_WIN eWindow, ++ MS_U8 eXRuleType, ++ MS_U8 u8XRuleIP, ++ MS_BOOL bPreV_ScalingDown, ++ MS_BOOL bInterlace, ++ MS_BOOL bColorSpaceYUV, ++ MS_U16 u16InputSize, ++ MS_U16 u16SizeAfterScaling) ++{ ++ MS_U32 u32Ratio; ++ MS_U16 u16IPIdx; ++#if(ENABLE_PQ_BIN) ++ MS_U16 u16TabIdx = gbPQBinEnable == 0 ? PQ_IP_NULL : PQ_BIN_IP_NULL; ++#else ++ MS_U16 u16TabIdx = PQ_IP_NULL; ++#endif ++ MS_U8 u8XRuleIdx = 0xFF; ++ ++ if(u16InputSize == 0) ++ u32Ratio = 2000; ++ else ++ u32Ratio = ((MS_U32) u16SizeAfterScaling * 1000) / u16InputSize; ++ ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex(eWindow, eXRuleType, u8XRuleIP); ++ ++ SRULE_DBG(printf("XRuleIP=%d, IPIdx=%d, input=%d, output=%d, ratio=%ld, \r\n", ++ (MS_U16)u8XRuleIP, (MS_U16)u16IPIdx, ++ u16InputSize, u16SizeAfterScaling, u32Ratio)); ++ ++#if PQ_ENABLE_HSDRULE ++ if(bPreV_ScalingDown && bInterlace) ++ { ++ u8XRuleIdx = PQ_HSDRule_PreV_ScalingDown_Interlace_Main; ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, (MS_U16)eXRuleType, (MS_U16)u8XRuleIdx, (MS_U16)u8XRuleIP); ++ } ++ else if(bPreV_ScalingDown && (!bInterlace)) ++ { ++ u8XRuleIdx = PQ_HSDRule_PreV_ScalingDown_Progressive_Main; ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, (MS_U16)eXRuleType, (MS_U16)u8XRuleIdx, (MS_U16)u8XRuleIP); ++ } ++#endif ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 0) && (u16TabIdx != PQ_IP_NULL)) || ++ ((gbPQBinEnable == 1) && (u16TabIdx != PQ_BIN_IP_NULL))) ++#else ++ if(u16TabIdx != PQ_IP_NULL) ++#endif ++ { ++ ++ SRULE_DBG(printf("u8XRuleIdx: PreV down, interlace:%u", bInterlace)); ++ SRULE_DBG(printf("(a)tabidx=%u\r\n", (MS_U16)u16TabIdx)); ++ } ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TabIdx == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TabIdx == PQ_IP_NULL))) ++#else ++ if(u16TabIdx == PQ_IP_NULL) ++#endif ++ { ++ if(u32Ratio > 1000) ++ { ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ SRULE_DBG(printf("u8XRuleIdx: >x1, ")); ++ SRULE_DBG(printf("(c)tabidx=%u\r\n", (MS_U16)u16TabIdx)); ++ } ++ else ++ { ++ ++ #if PQ_ENABLE_HSDRULE ++ if(bColorSpaceYUV) ++ { ++ if(u32Ratio == 1000) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_10x_YUV_Main; ++ else if(u32Ratio >= 900) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_09x_YUV_Main; ++ else if(u32Ratio >= 800) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_08x_YUV_Main; ++ else if(u32Ratio >= 700) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_07x_YUV_Main; ++ else if(u32Ratio >= 600) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_06x_YUV_Main; ++ else if(u32Ratio >= 500) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_05x_YUV_Main; ++ else if(u32Ratio >= 400) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_04x_YUV_Main; ++ else if(u32Ratio >= 300) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_03x_YUV_Main; ++ else if(u32Ratio >= 200) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_02x_YUV_Main; ++ else if(u32Ratio >= 100) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_01x_YUV_Main; ++ else ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_00x_YUV_Main; ++ } ++ else ++ { ++ if(u32Ratio == 1000) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_10x_RGB_Main; ++ else if(u32Ratio >= 900) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_09x_RGB_Main; ++ else if(u32Ratio >= 800) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_08x_RGB_Main; ++ else if(u32Ratio >= 700) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_07x_RGB_Main; ++ else if(u32Ratio >= 600) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_06x_RGB_Main; ++ else if(u32Ratio >= 500) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_05x_RGB_Main; ++ else if(u32Ratio >= 400) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_04x_RGB_Main; ++ else if(u32Ratio >= 300) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_03x_RGB_Main; ++ else if(u32Ratio >= 200) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_02x_RGB_Main; ++ else if(u32Ratio >= 100) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_01x_RGB_Main; ++ else ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_00x_RGB_Main; ++ } ++ #endif ++ SRULE_DBG(printf("u8XRuleIdx=%u, ", (MS_U16)u8XRuleIdx)); ++ if(u8XRuleIdx == 0xFF) ++ { ++ MS_ASSERT(0); ++ return 1; ++ } ++ ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, (MS_U16)eXRuleType, (MS_U16)u8XRuleIdx, (MS_U16)u8XRuleIP); ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TabIdx == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TabIdx == PQ_IP_NULL))) ++#else ++ if(u16TabIdx == PQ_IP_NULL) ++#endif ++ { ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ SRULE_DBG(printf("(d)tabidx=%u\r\n", u16TabIdx)); ++ } ++ else ++ { ++ SRULE_DBG(printf("(e)tabidx=%u\r\n", u16TabIdx)); ++ } ++ } ++ } ++ ++#if PQ_EN_DMS_SW_CTRL ++ // App will call halt_subwin to disconnet sub window. ++ // It will casue PQ display type to be PQ_DISPLAY_ONE. ++ // But, sub window is still on and DMS_LV_12 will be set ++ // to On in HSD rulee for main window. ++ // For fix this issue, we need to check sub window wheter ++ // on or off to descide DMS_LV_12 off or on. ++ ++ //Disable DMS_V12_L ++ // 1.VSD : V prescaling, 2. PIP, 3. FBL ++ if((((eXRuleType == E_XRULE_VSD)&&(bPreV_ScalingDown)) ++ ||_stMode_Info[eWindow].bFBL ++ || (E_XC_3D_INPUT_MODE_NONE != MApi_XC_Get_3D_Input_Mode(MAIN_WINDOW)) ++ ) && (PQ_IP_DMS_V_12L_Main == MDrv_PQ_GetXRuleIPIndex(eWindow, eXRuleType, u8XRuleIP)) ++ ) ++ { ++ //Disable De-Mosquito ++ u16TabIdx = PQ_IP_DMS_V_12L_OFF_Main; ++ } ++ #endif ++ ++ SRULE_DBG(printf("LoadScalingTable: TabIdx:%d IPIdx:%d \r\n", u16TabIdx, u16IPIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ ++#if PQ_ENABLE_HSDRULE ++ ++ if(eXRuleType == E_XRULE_VSD) ++ return (u16TabIdx == PQ_IP_VSD_Bilinear_Main) ; // PreVSDMode: 0:Cb, 1:Bilinear ++ else ++ return (u16TabIdx != PQ_IP_HSD_Y_CB_Main); // PreHSDMode - 0:Cb, 1:Adv ++#else ++ ++ return 1; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_LoadScalingTable(PQ_WIN eWindow, ++ MS_U8 eXRuleType, ++ MS_BOOL bPreV_ScalingDown, ++ MS_BOOL bInterlace, ++ MS_BOOL bColorSpaceYUV, ++ MS_U16 u16InputSize, ++ MS_U16 u16SizeAfterScaling) ++{ ++ MS_BOOL bRet = 0; // default is CB mode ++ MS_U16 i; ++ ++ if(eXRuleType > 3) ++ MS_ASSERT(0); ++ ++ SRULE_DBG(printf("[PQ_LoadScalingTable] HSD/VSD/HSP/VSP:%u\r\n", (MS_U16)eXRuleType)); ++ SRULE_DBG(printf("Pre_ScalingDown:%d, bInter:%d, bYUV:%d \r\n", bPreV_ScalingDown, bInterlace, bColorSpaceYUV)); ++ ++ for(i = 0; i < MDrv_PQ_GetXRuleIPNum(eWindow, (MS_U16)eXRuleType); i++) ++ { ++ MS_BOOL bSDMode; ++ bSDMode = _MDrv_PQ_LoadScalingTable(eWindow, ++ eXRuleType, ++ (MS_U8)i, ++ bPreV_ScalingDown, ++ bInterlace, ++ bColorSpaceYUV, ++ u16InputSize, ++ u16SizeAfterScaling); ++ bRet |= (bSDMode << (1 * i)); ++ } ++ ++ if(eXRuleType == E_XRULE_VSD) ++ { ++ bRet &= 0x01; ++ } ++#if 0 ++ //121 filter ++ if(((MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_LINE_ALTERNATIVE) || ++ (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_TOP_BOTTOM)) && ++ (MApi_XC_Get_3D_HW_Version() > 0)) ++ { ++ if((u16InputSize >= u16SizeAfterScaling) && (eXRuleType == E_XRULE_VSP)) ++ { ++ //if post V down, we will load 121 filter, and when it's post scaling case ++ //reload 121 filter's VSP_Y=SRAM_1_4Tap, VSP_C=C_SRAM_1, ++ // SRAM1=InvSinc4Tc4p4Fc50Apass01Astop55, C_SRAM1=C121 for main-win ++ //reload 121 filter's VSP_Y=SRAM_3_4Tap, VSP_C=C_SRAM_3, ++ // SRAM3=InvSinc4Tc4p4Fc50Apass01Astop55, C_SRAM3=C121 for sub-win ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VSP_Y_SRAM_1_4Tap_Main, PQ_IP_VSP_Y_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VSP_C_C_SRAM_1_Main, PQ_IP_VSP_C_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_SRAM1_InvSinc4Tc4p4Fc50Apass01Astop55_Main, PQ_IP_SRAM1_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_C_SRAM1_C121_Main, PQ_IP_C_SRAM1_Main); ++ ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_VSP_Y_SRAM_3_4Tap_Sub, PQ_IP_VSP_Y_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_VSP_C_C_SRAM_3_Sub, PQ_IP_VSP_C_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_SRAM3_InvSinc4Tc4p4Fc50Apass01Astop55_Sub, PQ_IP_SRAM3_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_C_SRAM3_C121_Sub, PQ_IP_C_SRAM3_Sub); ++ } ++ } ++#endif ++ ++ return bRet; ++} ++ ++ ++////////////////////////////////////////////////////////////////// ++// set color range of input source and take effect immediately ++// ++void MDrv_PQ_SetColorRange(PQ_WIN eWindow, MS_BOOL bColorRange0_255) ++{ ++ _bColorRange0_255[eWindow] = bColorRange0_255; ++ MDrv_PQ_SetCSC(eWindow, _gFourceColorFmt[eWindow]); ++} ++ ++MS_BOOL MDrv_PQ_Get_CSC_XRuleIdx(MS_BOOL *pbInputColorSpaceRGB, ++ MS_U16 * pu16DoCSC, ++ PQ_WIN eWindow, ++ PQ_FOURCE_COLOR_FMT enFourceColor, ++ MS_BOOL bLoadPQTable) ++{ ++#if PQ_ENABLE_CSCRULE ++ ++ MS_U16 u16XRuleIdx, u16XRuleIP; ++ MS_U16 u16IPIdx, u16TabIdx; ++ MS_U16 eXRuleType = E_XRULE_CSC; ++ MS_BOOL bInputTypeVideo; ++ MS_BOOL bInputResolutionHD = _gIsSrcHDMode[eWindow]; ++ MS_U16 u16YUV_CSC, u16RGB_CSC; ++ ++ _gFourceColorFmt[eWindow] = enFourceColor; ++ ++#if ENABLE_VGA_EIA_TIMING ++ if ((QM_IsSourceVGA(_enInputSourceType[eWindow]) || ++ QM_IsSourceDVI_HDMIPC(_enInputSourceType[eWindow], eWindow)) && !QM_IsInterlaced(eWindow)) ++#else ++ if(QM_IsSourceVGA(_enInputSourceType[eWindow]) || ++ (QM_IsSourceDVI_HDMIPC(_enInputSourceType[eWindow], eWindow) && !QM_IsInterlaced(eWindow))) ++#endif ++ { ++ CSCRULE_DBG(printf("PC mode\r\n")); ++ bInputTypeVideo = FALSE; ++ ++#if (PQ_ENABLE_PIP == 1) ++ if(eWindow == PQ_SUB_WINDOW) ++ { ++ printf("[%s][%d] VGA in sub video case, force PC mode to video mode \r\n", __FUNCTION__, __LINE__); ++ bInputTypeVideo = TRUE; ++ } ++#endif ++ } ++ else ++ { ++ CSCRULE_DBG(printf("VIDEO mode\r\n")); ++ bInputTypeVideo = TRUE; ++ } ++ ++ if(MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) ++ { ++ CSCRULE_DBG(printf("PointToPoint mode\r\n")); ++ bInputTypeVideo = FALSE; ++ } ++ ++ if( QM_IsSourceVGA(_enInputSourceType[eWindow]) || ++ (QM_IsSourceDVI_HDMIPC(_enInputSourceType[eWindow],eWindow)) || ++ (QM_IsSourceHDMI_Video(_enInputSourceType[eWindow],eWindow) && (QM_HDMIPC_COLORRGB(eWindow))) ) ++ { ++ CSCRULE_DBG(printf("Input RGB\r\n")); ++ (*pbInputColorSpaceRGB) = TRUE; ++ } ++ else ++ { ++ CSCRULE_DBG(printf("Input YUV\r\n")); ++ (*pbInputColorSpaceRGB) = FALSE; ++ } ++ ++ if (bInputTypeVideo) ++ { ++ if (*pbInputColorSpaceRGB) ++ { ++ if (eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : // fource to RGB and input is RGB, hence no need change ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : // fource to RGB and input is RGB, hence no need change ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#endif ++ } ++ else // InputColorSpaceYUV ++ { ++ if(enFourceColor == PQ_FOURCE_COLOR_RGB ) ++ { ++ MS_ASSERT(0); ++ PQTAB_DBG(printf("InputColorSpace is YUV, Fource Color Space is RGB!!!\r\n")); ++ } ++ ++ if(eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ ++ if(enFourceColor == PQ_FOURCE_COLOR_RGB) ++ { ++ if(bInputResolutionHD) ++ { ++ if(_bColorRange0_255[eWindow]) ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ else ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ } ++ else ++ { ++ if(_bColorRange0_255[eWindow]) ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ else ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ } ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ } ++#endif ++ } ++ } ++ else // InputTypePC ++ { ++ if (*pbInputColorSpaceRGB) ++ { ++ if (eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#endif ++ } ++ else // InputColorSpaceYUV ++ { ++ if(enFourceColor == PQ_FOURCE_COLOR_RGB ) ++ { ++ MS_ASSERT(0); ++ PQTAB_DBG(printf("InputColorSpace is YUV, Fource Color Space is RGB!!!\r\n")); ++ } ++ ++ if(eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ } ++#endif ++ } ++ } ++ ++ for(u16XRuleIP=0; u16XRuleIP u16GRule_NR_Num) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < u16GRule_NR_IP_Num; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, u16GRule_Type, i); ++ ++ if(u16PQ_NRIdx == u16GRule_NR_Num) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, u16GRule_Type, u16PQ_NRIdx, i); ++ ++ PQGRULE_DBG(printf("[NR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_NRIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if (eWindow == PQ_SUB_WINDOW) ++ { ++ MS_U16 u16GRule_NR_Num = eWindow == PQ_SUB_WINDOW ? PQ_GRULE_NR_NUM_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRULE_NR_NUM_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ MS_U16 u16GRule_NR_IP_Num = eWindow == PQ_SUB_WINDOW ? PQ_GRULE_NR_IP_NUM_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRULE_NR_IP_NUM_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ ++ MS_U16 u16GRule_Type = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ if(u16PQ_NRIdx > u16GRule_NR_Num) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < u16GRule_NR_IP_Num; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, u16GRule_Type, i); ++ ++ if(u16PQ_NRIdx == u16GRule_NR_Num) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, u16GRule_Type, u16PQ_NRIdx, i); ++ ++ PQGRULE_DBG(printf("[NR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_NRIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++ } ++#endif ++ else ++ { ++ PQGRULE_DBG(printf("[NR] Not support case \r\n")); ++ } ++} ++#endif ++ ++ ++void MDrv_PQ_LoadNRTable(PQ_WIN eWindow, PQ_3D_NR_FUNCTION_TYPE en3DNRType) ++{ ++#if (PQ_GRULE_NR_ENABLE) ++ ++ MS_U16 u16PQ_NRIdx; ++ MS_U16 u16GRule_Type, u16GRule_Level; ++ ++ PQGRULE_DBG( printf("[PQ_LoadNRTable] ") ); ++ ++ if (eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ u16GRule_Type = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ if(en3DNRType == PQ_3D_NR_OFF) ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Off_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Off_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Off_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_AUTO) ++ { ++ // Auto NR will be process in msAPI_DynamicNR_Handler(), hence we only need to pre-setup the PQ table. ++ PQGRULE_DBG(printf("Auto\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Low_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Low_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Low_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_LOW) ++ { ++ PQGRULE_DBG(printf("Low\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Low_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Low_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Low_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_MID) ++ { ++ PQGRULE_DBG(printf("Mid\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Middle_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Middle_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Middle_SC1_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_HIGH) ++ { ++ PQGRULE_DBG(printf("High\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_High_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_High_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_High_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_DEFAULT) ++ { ++ MS_U16 u16NR_Idx = eWindow == PQ_MAIN_WINDOW ? PQ_GRULE_NR_NUM_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRULE_NR_NUM_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRULE_NR_NUM_SC2_Main : ++ #endif ++ 0xFFFF; ++ PQGRULE_DBG(printf("Default\r\n")); ++ _MDrv_PQ_LoadNRTable(eWindow, u16NR_Idx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if (eWindow == PQ_SUB_WINDOW) ++ { ++ u16GRule_Type = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ if(en3DNRType == PQ_3D_NR_OFF) ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Off_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Off_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_AUTO) ++ { ++ // Auto NR will be process in msAPI_DynamicNR_Handler(), hence we only need to pre-setup the PQ table. ++ PQGRULE_DBG(printf("Auto\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Low_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Low_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_LOW) ++ { ++ PQGRULE_DBG(printf("Low\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Low_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Low_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_MID) ++ { ++ PQGRULE_DBG(printf("Mid\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Middle_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Middle_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_HIGH) ++ { ++ PQGRULE_DBG(printf("High\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_High_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_High_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_DEFAULT) ++ { ++ MS_U16 u16NR_Idx = eWindow == PQ_SUB_WINDOW ? PQ_GRULE_NR_NUM_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRULE_NR_NUM_SC2_Sub : ++ #endif ++ 0xFFFF; ++ PQGRULE_DBG(printf("Default\r\n")); ++ _MDrv_PQ_LoadNRTable(eWindow, u16NR_Idx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++ } ++#endif ++ else ++ { ++ PQGRULE_DBG(printf("Not support case \r\n")); ++ } ++ ++#if 0 //trunk don't have janus code, it's obsolete ++#ifdef __AEONR2__ //patch for DDR2-800 on Janus ++ if(QM_IsInterlaced(eWindow) && QM_IsSourceMultiMedia(MDrv_PQ_GetInputSourceType(eWindow)) && (MApi_XC_ReadByte(0x110D30)==0x66)) ++ { ++ MS_U16 u16Input_HSize; ++ MS_U16 u16Input_VSize; ++ u16Input_HSize = _stMode_Info[eWindow].u16input_hsize; ++ u16Input_VSize = _stMode_Info[eWindow].u16input_vsize; ++ ++ if(u16Input_HSize>1280 && u16Input_VSize>=900) ++ { ++ MApi_XC_WriteByte(0x102F00, 0x12); ++ MApi_XC_WriteByte(0x102F03, 0x27); ++ MApi_XC_WriteByte(0x102F00, 0x06); ++ MApi_XC_WriteByte(0x102F42, MApi_XC_ReadByte(0x102F42)&0xFE); ++ } ++ } ++#endif ++#endif ++#endif // PQ_GRULE_NR_ENABLE ++} ++ ++#if PQ_GRULE_OSD_BW_ENABLE ++static void _MDrv_PQ_LoadOSD_BWTable(PQ_WIN eWindow, MS_U16 u16PQ_OSD_BW_Idx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ ++ if(u16PQ_OSD_BW_Idx > PQ_GRULE_OSD_BW_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_OSD_BW_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_OSD_BW_Main, i); ++ ++ if(u16PQ_OSD_BW_Idx == PQ_GRULE_OSD_BW_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSD_BW_Idx, i); ++ ++ PQGRULE_DBG(printf("[NR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u8TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_OSD_BW_Idx, i, u16IPIdx, u16IPIdx)); ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++ ++ ++void MDrv_PQ_LoadOSD_BWTable(PQ_WIN eWindow, PQ_OSD_BW_FUNCTION_TYPE enOSD_BW_Type) ++{ ++ MS_U16 u16PQ_NRIdx; ++ ++ PQGRULE_DBG(printf("[PQ_Load_OSD_BW_Table] ")); ++ ++ if(enOSD_BW_Type == PQ_OSD_BW_ON) ++ { ++ PQGRULE_DBG(printf("On\r\n")); ++ ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ if(bw_info.u32Miu1MemSize == 0) ++ { ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_Main); ++ _MDrv_PQ_LoadOSD_BWTable(eWindow, u16PQ_NRIdx); ++ } ++ else ++ { ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_Main); ++ _MDrv_PQ_LoadOSD_BWTable(eWindow, u16PQ_NRIdx); ++ } ++ #else ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_On_Main); ++ _MDrv_PQ_LoadOSD_BWTable(eWindow, u16PQ_NRIdx); ++ #endif ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++#endif ++ ++#if PQ_GRULE_FILM_MODE_ENABLE ++static void _MDrv_PQ_LoadFilmModeTable(PQ_WIN eWindow, MS_U16 u16PQ_FilmModeIdx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ if(u16PQ_FilmModeIdx > PQ_GRULE_FILM_MODE_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_FILM_MODE_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_FILM_MODE_Main, i); ++ ++ if(u16PQ_FilmModeIdx == PQ_GRULE_FILM_MODE_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16TabIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_FILM_MODE_Main, u16PQ_FilmModeIdx, i); ++ ++ PQGRULE_DBG(printf("[FM]SRC: %u, FM: %u, FMIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_FilmModeIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++ ++void MDrv_PQ_LoadFilmModeTable(PQ_WIN eWindow, PQ_FILM_MODE_FUNCTION_TYPE enFilmModeType) ++{ ++#if PQ_GRULE_FILM_MODE_ENABLE ++ MS_U16 u16PQ_FilmModeIdx; ++ ++ if(enFilmModeType == PQ_FilmMode_OFF) ++ { ++ u16PQ_FilmModeIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_FILM_MODE_Main, PQ_GRule_FILM_MODE_Off_Main); ++ _MDrv_PQ_LoadFilmModeTable(eWindow, u16PQ_FilmModeIdx); ++ ++ } ++ else if(enFilmModeType == PQ_FilmMode_ON) ++ { ++ u16PQ_FilmModeIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_FILM_MODE_Main, PQ_GRule_FILM_MODE_On_Main); ++ _MDrv_PQ_LoadFilmModeTable(eWindow, u16PQ_FilmModeIdx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(enFilmModeType); ++#endif ++} ++ ++#if PQ_GRULE_DYNAMIC_CONTRAST_ENABLE ++static void _MDrv_PQ_DynamicContrastTable(PQ_WIN eWindow, MS_U16 u16PQ_DynContrIdx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ if(u16PQ_DynContrIdx > PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, i); ++ ++ if(u16PQ_DynContrIdx == PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16TabIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, u16PQ_DynContrIdx, i); ++ ++ PQGRULE_DBG(printf("[DC]SRC: %u, DC: %u, DCIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_DynContrIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_LoadDynamicContrastTable(PQ_WIN eWindow, PQ_DYNAMIC_CONTRAST_FUNCTION_TYPE enDynamicContrastType) ++{ ++#if PQ_GRULE_DYNAMIC_CONTRAST_ENABLE ++ MS_U16 u16PQ_DynContrIdx; ++ ++ if(enDynamicContrastType == PQ_DynContr_OFF) ++ { ++ u16PQ_DynContrIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, PQ_GRule_DYNAMIC_CONTRAST_Off_Main); ++ _MDrv_PQ_DynamicContrastTable(eWindow, u16PQ_DynContrIdx); ++ } ++ else if(enDynamicContrastType == PQ_DynContr_ON) ++ { ++ u16PQ_DynContrIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, PQ_GRule_DYNAMIC_CONTRAST_On_Main); ++ _MDrv_PQ_DynamicContrastTable(eWindow, u16PQ_DynContrIdx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(enDynamicContrastType); ++#endif ++} ++ ++ ++#if PQ_GRULE_MPEG_NR_ENABLE ++static void _MDrv_PQ_LoadMPEGNRTable(PQ_WIN eWindow, MS_U16 u16PQ_NRIdx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ if(u16PQ_NRIdx > PQ_GRULE_MPEG_NR_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_MPEG_NR_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_MPEG_NR_Main, i); ++ ++ if(u16PQ_NRIdx == PQ_GRULE_MPEG_NR_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_MPEG_NR_Main, u16PQ_NRIdx, i); ++ ++ PQGRULE_DBG(printf("[MPEGNR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_NRIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_LoadMPEGNRTable(PQ_WIN eWindow, PQ_MPEG_NR_FUNCTION_TYPE enMPEGNRType) ++{ ++#if(PQ_GRULE_MPEG_NR_ENABLE) ++ MS_U16 u16PQ_NRIdx; ++ ++ PQGRULE_DBG(printf("[PQ_LoadMPEGNRTable] ")); ++ ++ if(enMPEGNRType == PQ_MPEG_NR_OFF) ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Off_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if( enMPEGNRType == PQ_MPEG_NR_AUTO ) ++ { ++ // Auto NR will be process in msAPI_DynamicNR_Handler(), hence we only need to pre-setup the PQ table. ++ PQGRULE_DBG(printf("Auto\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Low_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_LOW) ++ { ++ PQGRULE_DBG(printf("Low\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Low_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_MID) ++ { ++ PQGRULE_DBG(printf("Mid\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Middle_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_HIGH) ++ { ++ PQGRULE_DBG(printf("High\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_High_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_DEFAULT) ++ { ++ PQGRULE_DBG(printf("Default\r\n")); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, PQ_GRULE_MPEG_NR_NUM_Main); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(enMPEGNRType); ++#endif ++} ++#if PQ_GRULE_ULTRAT_CLEAR_ENABLE ++static void _MDrv_PQ_Load_ULTRACLEAR_Table(PQ_WIN eWindow, MS_U16 u16PQ_ULTRACLEAR_Idx) ++{ ++ MS_U16 i = 0, u16IPIdx = 0, u16TabIdx = 0; ++ ++ if(u16PQ_ULTRACLEAR_Idx > PQ_GRULE_ULTRAT_CLEAR_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, i); ++ ++ if(u16PQ_ULTRACLEAR_Idx == PQ_GRULE_ULTRAT_CLEAR_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, u16PQ_ULTRACLEAR_Idx, i); ++ ++ PQGRULE_DBG(printf("[UC]SRC: %u, UC: %u, UCIPIdx:%u, IPIdx:%u, u8TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_ULTRACLEAR_Idx, i, u16IPIdx, u16IPIdx)); ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_Load_ULTRACLEAR_Table(PQ_WIN eWindow, PQ_FEATURE_SWITCH_TYPE enCtrlType) ++{ ++ MS_U16 u16PQ_TableIdx = 0; ++#if PQ_GRULE_ULTRAT_CLEAR_ENABLE ++ PQGRULE_DBG(printf("[PQ_Load_ULTRACLEAR_Table] ")); ++ if(enCtrlType == PQ_FEATURE_SWITCH_ON) ++ { ++ PQGRULE_DBG(printf("On\r\n")); ++ u16PQ_TableIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, PQ_GRule_ULTRAT_CLEAR_On_Main); ++ _MDrv_PQ_Load_ULTRACLEAR_Table(eWindow, u16PQ_TableIdx); ++ } ++ else ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16PQ_TableIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, PQ_GRule_ULTRAT_CLEAR_Off_Main); ++ _MDrv_PQ_Load_ULTRACLEAR_Table(eWindow, u16PQ_TableIdx); ++ } ++#else ++ UNUSED(u16PQ_TableIdx); ++ UNUSED(eWindow); ++ UNUSED(enCtrlType); ++ ++#endif ++ ++} ++ ++MS_BOOL MDrv_PQ_GRULE_Get_Support_Status(PQ_SUPPORTED_TYPE enType) ++{ ++ MS_BOOL bStatus = FALSE; ++ switch(enType) ++ { ++ case E_PQ_SUPPORTED_FILM: ++ if(PQ_GRULE_FILM_MODE_ENABLE) ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_NR: ++ if(PQ_GRULE_NR_ENABLE) ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_MPEG_NR: ++ if(PQ_GRULE_MPEG_NR_ENABLE) ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_BLACK_LEVEL: ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_ULTRA_CLEAR: ++ if(PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ bStatus = TRUE; ++ break; ++ default: ++ break; ++ } ++ ++ return bStatus; ++ ++} ++ ++MS_U8 _MDrv_PQ_wait_output_vsync(PQ_WIN ePQWin, MS_U8 u8NumVSyncs, MS_U16 u16Timeout) ++{ ++ MS_U32 u32Time; ++ MS_U8 bVSync; ++ //MS_BOOL bMainWin = (ePQWin == PQ_MAIN_WINDOW) ? TRUE : FALSE; ++ ++ bVSync = 0; ++ u32Time = MsOS_GetSystemTime(); ++ ++ while(1) ++ { ++ if(Hal_PQ_get_output_vsync_value(ePQWin) == bVSync) ++ { ++ u8NumVSyncs--; ++ if(bVSync && (u8NumVSyncs == 0)) ++ break; ++ bVSync = !bVSync; ++ } ++ ++ if((MsOS_GetSystemTime() - u32Time) >= u16Timeout) ++ break; ++ } ++ ++ return u8NumVSyncs; ++} ++ ++MS_U8 _MDrv_PQ_wait_input_vsync(PQ_WIN ePQWin, MS_U8 u8NumVSyncs, MS_U16 u16Timeout) ++{ ++ MS_U32 u32Time; ++ //MS_BOOL bMainWin = (ePQWin == PQ_MAIN_WINDOW) ? TRUE : FALSE; ++ MS_U8 u8VsyncPolarity = Hal_PQ_get_input_vsync_polarity(ePQWin); ++ MS_U8 bVSync = !u8VsyncPolarity; ++ ++ u32Time = MsOS_GetSystemTime(); ++ ++ while(1) ++ { ++ if(Hal_PQ_get_input_vsync_value(ePQWin) == bVSync) ++ { ++ u8NumVSyncs--; ++ if((bVSync == u8VsyncPolarity) && (u8NumVSyncs == 0)) ++ break; ++ bVSync = !bVSync; ++ } ++ ++ if((MsOS_GetSystemTime() - u32Time) >= u16Timeout) ++ { ++ //printf("!!input vsync timeout\r\n"); ++ break; ++ } ++ } ++ ++ return u8NumVSyncs; ++} ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++void MDrv_PQ_Set_DBRule(PQ_WIN eWindow, MS_U16 u16MADi_Idx) ++{ ++ MS_U16 eXRuleType = E_XRULE_CSC; ++ MS_U16 u16XRuleIdx, u16XRuleIP; ++ MS_U16 u16IPIdx, u16TabIdx; ++ ++ eXRuleType = (_stMode_Info[eWindow].u16input_vfreq > 550) ? E_XRULE_DB_NTSC : E_XRULE_DB_PAL; ++ ++ if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_4R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_4R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_2R_Main; ++ } ++ else if(yHal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_MC) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_MC_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_2R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_4R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_27_4R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_2R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_27_2R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE8_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE10) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE10_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT8) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE_MOT8_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE_MOT10_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_4R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_4R_880_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_2R_880_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_6R_MC_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_14F_6R_MC) == u16MADi_Idx) //Add New MADi mode ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_14F_6R_MC_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_MC_NW) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_MC_NW_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC_NW) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_6R_MC_NW_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_884) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_884_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R_884) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_2R_884_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_4R_880_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_2R_880_Main; ++ } ++ else ++ { ++ u16XRuleIdx = 0xFF; ++ } ++ ++ for(u16XRuleIP = 0; u16XRuleIP < MDrv_PQ_GetXRuleIPNum(eWindow, eXRuleType); u16XRuleIP++) ++ { ++ if(u16XRuleIdx == 0xFF) ++ continue; ++ ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex(eWindow, eXRuleType, u16XRuleIP); ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, eXRuleType, u16XRuleIdx, u16XRuleIP); ++ //(printf("u16XRuleIdx:%u, u16XRuleIP=%u, IPIdx=%u, TabIdx=%u\r\n", u16XRuleIdx, u16XRuleIP, u16IPIdx, u16TabIdx)); ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_EnableMADIForce(PQ_WIN eWindow, MS_BOOL bFullMotion) ++{ ++#if PQ_ENABLE_FORCE_MADI ++ MS_U16 u16TabIdx, u16IPIdx; ++ if(bFullMotion) ++ { ++ ++ u16TabIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++ else ++ { ++ u16TabIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ ++ } ++#else ++UNUSED(eWindow); ++UNUSED(bFullMotion); ++#endif ++} ++ ++////////////////////////////////////////////////////////////////// ++// Load MADi/444To422/422To444 table ++// ++// parameter: ++// [IN] u8PQTabType ++// bMemFmt422: TRUE - 422 ++// FALSE - 444 ++// bFBL: TRUE - framebuffer-less mode ++// FALSE - framebuffer mode ++// [OUT] u8BitsPerPixel ++// bits per pixel for decided memory format ++// ++// return: deinterlace (MADi) mode ++// ++PQ_DEINTERLACE_MODE MDrv_PQ_SetMemFormat(PQ_WIN eWindow, MS_BOOL bMemFmt422, MS_BOOL bFBL, MS_U8 *pu8BitsPerPixel) ++{ ++ ++#if(PQ_ENABLE_MEMFMT) ++ ++ MS_U16 u16TabIdx_MemFormat = 0; ++ MS_U16 u16TabIdx_MADi = 0; ++ MS_U16 u16TabIdx_MADi_Motion=0xFFFF; ++ MS_U16 u16TabIdx_444To422 = 0; ++ MS_U16 u16TabIdx_422To444 = 0; ++ PQ_DEINTERLACE_MODE eDeInterlaceMode = PQ_DEINT_OFF; ++ MS_U8 u8FrameCount = 4; ++ ++ if(eWindow == PQ_MAIN_WINDOW ++#if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++#endif ++ ) ++ { ++#if 0 //Ryan ++ SCALER_WIN eSCWin = ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? SC2_MAIN_WINDOW : ++ eWindow == PQ_SC1_MAIN_WINDOW ? SC1_MAIN_WINDOW : ++ #endif ++ MAIN_WINDOW; ++ MApi_XC_Set_OPWriteOffEnable(ENABLE, eSCWin); //default ++#endif ++ } ++ else ++ { ++ PQINFO_DBG(printf("No need to enable OP write with sub window, it would change main window setting \r\n")); ++ } ++ ++ PQTAB_DBG(printf("==>In PQ : eWindow =%d\r\n", eWindow)); ++ ++ if(!bFBL) ++ { ++ // if MADi mode change from 25 <=> 27, cropping base address need to be recalculated. ++#if PQ_GRULE_OSD_BW_ENABLE ++ if(((_stMode_Info[eWindow].u16input_hsize >= 1280) && (_stMode_Info[eWindow].u16input_vsize >= 720)) && ++ (_bOSD_On)) ++ { ++ MDrv_PQ_GetMADiFromGrule(eWindow, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++ } ++ else ++#endif ++ { ++ MDrv_PQ_GetMADiInGeneral(eWindow, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++#if PQ_GRULE_OSD_BW_ENABLE ++ MDrv_PQ_Patch2Rto4RForFieldPackingMode(eWindow, u16TabIdx_MADi); ++#endif ++ } ++ ++ MDrv_PQ_GetMADiForRFBL(eWindow, bFBL, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++ } ++ else // FBL ++ { ++ MS_U8 u8FblMode = Hal_PQ_get_madi_fbl_mode(bMemFmt422, _stMode_Info[eWindow].bInterlace); ++ u16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, (MS_MADI_TYPE)u8FblMode); ++ } ++ ++ ++ PQMADi_DBG(printf("Memory is %s mode \r\n", (bFBL)?("1.FBL"):("2.FB"))); ++ PQMADi_DBG(printf("get MADi idx = %u\r\n", u16TabIdx_MADi)); ++ ++ MDrv_PQ_GetMemFmtInGeneral(eWindow, bMemFmt422, &u16TabIdx_MemFormat, &u16TabIdx_444To422, &u16TabIdx_422To444); ++ ++ PQTAB_DBG(printf("%s :u16TabIdx_444To422=%u\r\n", eWindow?"SubWin":"MainWin",u16TabIdx_444To422)); ++ PQTAB_DBG(printf("%s :u16TabIdx_422To444=%u\r\n", eWindow?"SubWin":"MainWin",u16TabIdx_422To444)); ++ PQMADi_DBG(printf("MemFmt is 422 : %s\r\n",(bMemFmt422)?("Yes"):("No"))); ++ ++ MDrv_PQ_GetBPPInfoFromMADi(eWindow, bMemFmt422, u16TabIdx_MADi, u16TabIdx_MemFormat, pu8BitsPerPixel, &eDeInterlaceMode, &u8FrameCount); ++ ++ PQMADi_DBG(printf("BitPerPixel =%d, DIMode =%x\r\n", *pu8BitsPerPixel, eDeInterlaceMode)); ++ ++ _gbMemfmt422[eWindow] = bMemFmt422; ++ ++ MDrv_PQ_ChangeMemConfigFor3D(eWindow, bMemFmt422, &u16TabIdx_MemFormat, &u16TabIdx_444To422, &u16TabIdx_422To444, ++ pu8BitsPerPixel, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++ ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ MS_U16 u16IPIdx; ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MemFormat_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MemFormat_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MemFormat_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MemFormat, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MADi, u16IPIdx); ++#if PQ_GRULE_OSD_BW_ENABLE ++ if(0xFFFF != u16TabIdx_MADi_Motion) ++ { ++ PQTAB_DBG(printf("u16TabIdx_MADi_Motion=%u\r\n", u16TabIdx_MADi_Motion)); ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Motion_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Motion_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Motion_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MADi_Motion, u16IPIdx); ++ } ++#endif ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_444To422_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_444To422_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_444To422_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_444To422, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_422To444_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_422To444_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_422To444_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_422To444, u16IPIdx); ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ MS_U16 u16IPIdx; ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_MemFormat_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MemFormat_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MemFormat, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MADi, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_444To422_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_444To422_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_444To422, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_422To444_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_422To444_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_422To444, u16IPIdx); ++ } ++#endif ++ ++ PQTAB_DBG(printf("u16TabIdx_MemFormat=%u\r\n", u16TabIdx_MemFormat)); ++ PQTAB_DBG(printf("%s, u16TabIdx_MADi=%u\r\n", eWindow?"SUB_WIN":"MAIN_WIN",u16TabIdx_MADi)); ++ PQTAB_DBG(printf("%s, u16TabIdx_MADi=%u\r\n", eWindow?"SUB_WIN":"MAIN_WIN",u16TabIdx_MADi)); ++ PQTAB_DBG(printf("main :u16TabIdx_444To422=%u\r\n", u16TabIdx_444To422)); ++ PQTAB_DBG(printf("main :u16TabIdx_422To444=%u\r\n", u16TabIdx_422To444)); ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ MDrv_PQ_Set_DBRule(eWindow, u16TabIdx_MADi); ++#endif ++ ++ MDrv_PQ_ForceBPPForDynamicMemFmt(eWindow, bMemFmt422, pu8BitsPerPixel); ++ MDrv_PQ_SetFrameNumber(eWindow, u16TabIdx_MADi, u8FrameCount); ++ ++ if(_bDS_En) ++ { ++ _u16RW_Method = Hal_PQ_get_rw_method(eWindow); ++ Hal_PQ_set_rw_method(eWindow, 0x4000); ++ } ++ return eDeInterlaceMode; ++#else ++ return PQ_DEINT_OFF; ++#endif ++} ++ ++void MDrv_PQ_ReduceBW_ForOSD(PQ_WIN eWindow, MS_BOOL bOSD_On) ++{ ++#if PQ_GRULE_OSD_BW_ENABLE ++ MS_U8 u8BitPerPixel = 0; ++{ ++ if((_stMode_Info[eWindow].u16input_hsize >= 1280) && (_stMode_Info[eWindow].u16input_vsize >= 720)) ++ { ++ PQBW_DBG(printf("[PQ_ReduceBW_ForOSD]:%u\r\n", bOSD_On)); ++ ++ _bOSD_On = bOSD_On; ++ bSetFrameCount = FALSE; ++ ++ MDrv_PQ_SetMemFormat( ++ eWindow, ++ _gbMemfmt422[eWindow], ++ _stMode_Info[eWindow].bFBL, ++ &u8BitPerPixel); ++ bSetFrameCount = TRUE; ++ ++ } ++} ++#else ++ UNUSED(eWindow); ++ UNUSED(bOSD_On); ++#endif ++ ++ return; ++} ++ ++void MDrv_PQ_ReduceBW_ForPVR(PQ_WIN eWindow, MS_BOOL bPVR_On) ++{ ++ UNUSED(eWindow); ++ UNUSED(bPVR_On); ++} ++ ++void _MDrv_PQ_Set_MVOP_UVShift(MS_BOOL bEnable) ++{ ++ MS_U8 regval; ++ ++ regval = MApi_XC_ReadByte(VOP_MPG_JPG_SWITCH); ++ ++ if(((regval & 0x10) == 0x10) && ((regval & 0x3) == 0x2)) ++ { ++ // 422 with MCU control mode ++ if(bEnable) ++ { ++ MS_ASSERT(0); ++ } ++ } ++ ++ // output 420 and interlace ++ //[IP - Sheet] : Main Page --- 420CUP ++ //[Project] : Titania2 ++ //[Description]: Chroma artifacts when 420to422 is applied duplicate method. ++ //[Root cause]: Apply 420to422 average algorithm to all DTV input cases. ++ //The average algorithm must cooperate with MVOP. ++ MApi_XC_WriteByteMask(VOP_UV_SHIFT, (bEnable) ? 1 : 0, 0x3); ++} ++ ++void MDrv_PQ_Set420upsampling(PQ_WIN eWindow, ++ MS_BOOL bFBL, ++ MS_BOOL bPreV_ScalingDown, ++ MS_U16 u16V_CropStart) ++{ ++#if PQ_ENABLE_420UPSAMPLING ++ ++ MS_U16 u16TabIdx; ++ ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_420CUP_Main); ++ ++ PQTAB_DBG(printf("[PQ_Set420upsampling]: SrcType:%u, FBL:%u, PreV down:%u, V_CropStart:%u, u8TabIdx=%u, ", ++ _u16PQSrcType[eWindow], bFBL, bPreV_ScalingDown, u16V_CropStart, u16TabIdx)); ++ ++ if((u16TabIdx == Hal_PQ_get_420_cup_idx(MS_420_CUP_ON)) && (!bPreV_ScalingDown) && (!bFBL)) ++ { ++ PQTAB_DBG(printf("UVShift: on\r\n")); ++ _MDrv_PQ_Set_MVOP_UVShift(ENABLE); ++ MDrv_PQ_LoadTable(eWindow, Hal_PQ_get_420_cup_idx(MS_420_CUP_ON), PQ_IP_420CUP_Main); ++ } ++ else // P mode should not do UV shift ++ { ++ PQTAB_DBG(printf("UVShift: off\r\n")); ++ _MDrv_PQ_Set_MVOP_UVShift(DISABLE); ++ MDrv_PQ_LoadTable(eWindow, Hal_PQ_get_420_cup_idx(MS_420_CUP_OFF), PQ_IP_420CUP_Main); ++ } ++ ++ if((u16V_CropStart & 0x3) == 0) // crop lines are multiple of 4 ++ Hal_PQ_set_420upSample(eWindow, 0x6666); ++ else if((u16V_CropStart & 0x1) == 0) // crop lines are multiple of 2 ++ Hal_PQ_set_420upSample(eWindow, 0x9999); ++ else ++ MS_ASSERT(0); ++#endif ++} ++ ++void MDrv_PQ_SetFilmMode(PQ_WIN eWindow, MS_BOOL bEnable) ++{ ++#if PQ_ENABLE_SETFILM_MODE ++ MS_U16 u16TabIdx; ++ ++ PQTAB_DBG(printf("[PQ_SetFilmMode]: PQTabType=%u, enable=%u\r\n", eWindow, bEnable)); ++ ++ if(bEnable) ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_Film32_Main); ++ else ++ u16TabIdx = PQ_IP_Film32_OFF_Main; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, PQ_IP_Film32_Main); ++ ++ if(bEnable) ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_Film22_Main); ++ else ++ u16TabIdx = PQ_IP_Film22_OFF_Main; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, PQ_IP_Film22_Main); ++#endif ++} ++ ++ ++void MDrv_PQ_SetNonLinearScaling(PQ_WIN eWindow, MS_U8 u8Level, MS_BOOL bEnable) ++{ ++#if PQ_ENABLE_NONLINEAR_SCALING ++ MS_U16 u16TabIdx; ++ PQTAB_DBG(printf("[PQ_SetNonLinearScaling]: Level=%u, enable=%u\r\n", u8Level, bEnable)); ++ ++ if(bEnable) ++ { ++ switch(_stPQ_Info.u16PnlWidth) ++ { ++ case 1920: ++ switch(u8Level) ++ { ++ case 2: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1920_2); ++ break; ++ case 1: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1920_1); ++ break; ++ case 0: ++ default: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1920_0); ++ break; ++ } ++ break; ++ case 1680: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1680); ++ break; ++ case 1440: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1440); ++ break; ++ case 1366: ++ switch(u8Level) ++ { ++ case 2: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1366_2); ++ break; ++ case 1: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1366_1); ++ break; ++ case 0: ++ default: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1366_0); ++ break; ++ ++ } ++ break; ++ default: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_OFF); ++ break; ++ ++ break; ++ } ++ } ++ else ++ { ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_OFF); ++ } ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, PQ_IP_HnonLinear_Main); ++#endif ++} ++ ++void MDrv_PQ_3DCloneforPIP(MS_BOOL bIpSync) ++{ ++#if 0 //Ryan ++ //MVOP_Handle stHdl = { E_MVOP_MODULE_MAIN }; ++ MS_BOOL bEnAltOutputState = FALSE; ++ ++//![for temporary A3-WinCE6 porting, 20120109] ++#if 0 //ndef MSOS_TYPE_CE ++ ++ if (E_MVOP_OK == MDrv_MVOP_GetCommand(&stHdl, E_MVOP_CMD_GET_3DLR_ALT_OUT, &bEnAltOutputState, sizeof(bEnAltOutputState))) ++ { ++ //printf("%s Get3DLRAltOutput=0x%x\r\n", __FUNCTION__, bEnAltOutputState); ++ } ++ else ++ { ++ //printf("Fail to query E_MVOP_CMD_GET_3DLR_ALT_OUT!!\r\n"); ++ } ++ ++#endif ++ ++ if((E_XC_3D_OUTPUT_LINE_ALTERNATIVE == MApi_XC_Get_3D_Output_Mode()) ++ || (E_XC_3D_OUTPUT_TOP_BOTTOM == MApi_XC_Get_3D_Output_Mode()) ++ || (E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF == MApi_XC_Get_3D_Output_Mode())) ++ { ++ #if 0 ++ MApi_XC_ACE_3DClonePQMap(E_ACE_WEAVETYPE_NONE); ++ //printf("3D:confirm to clone main/sub win\r\n"); ++ #endif ++ ++ if((MApi_XC_Get_3D_HW_Version() < 2) && bIpSync) ++ { ++ MApi_XC_3DMainSub_IPSync(); ++ //printf("3D:confirm to do main/sub win sync\r\n"); ++ } ++ } ++ else if(MApi_XC_IsCurrentFrameBufferLessMode() && bEnAltOutputState) ++ { ++ #if 0 ++ MApi_XC_ACE_3DClonePQMap(E_ACE_WEAVETYPE_H); ++ #endif ++ } ++ MApi_XC_3D_PostPQSetting(MAIN_WINDOW); ++#endif ++} ++ ++void MDrv_PQ_DisableFilmMode(PQ_WIN eWindow, MS_BOOL bOn) ++{ ++ if(bOn) ++ { ++ MDrv_PQ_SetFilmMode(eWindow, DISABLE); ++ } ++ else ++ { ++ MDrv_PQ_SetFilmMode(eWindow, ENABLE); ++ } ++} ++ ++MS_BOOL MDrv_PQ_DisableUCFeature(PQ_WIN eWindow) ++{ ++ MS_BOOL bRet = TRUE; ++ ++#if PQ_EN_UCNR_OFF ++ if(PQ_MAIN_WINDOW == eWindow) ++ { ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_UCNR_OFF_Main, PQ_IP_UCNR_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_UC_CTL_OFF_Main, PQ_IP_UC_CTL_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_UCDi_OFF_Main, PQ_IP_UCDi_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(PQ_SUB_WINDOW == eWindow) ++ { ++ #if defined(AMBER3) ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_UCNR_OFF_Sub, PQ_IP_UCNR_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_UC_CTL_OFF_Sub, PQ_IP_UC_CTL_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_UCDi_OFF_Sub, PQ_IP_UCDi_Sub); ++ #endif ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(PQ_SC1_MAIN_WINDOW == eWindow) ++ { ++ MDrv_PQ_LoadTable(PQ_SC1_MAIN_WINDOW, PQ_IP_UCNR_OFF_SC1_Main, PQ_IP_UCNR_SC1_Main); ++ MDrv_PQ_LoadTable(PQ_SC1_MAIN_WINDOW, PQ_IP_UC_CTL_OFF_SC1_Main, PQ_IP_UC_CTL_SC1_Main); ++ MDrv_PQ_LoadTable(PQ_SC1_MAIN_WINDOW, PQ_IP_UCDi_OFF_SC1_Main, PQ_IP_UCDi_SC1_Main); ++ } ++ else if(PQ_SC2_MAIN_WINDOW == eWindow) ++ { ++ MDrv_PQ_LoadTable(PQ_SC2_MAIN_WINDOW, PQ_IP_UCNR_OFF_SC2_Main, PQ_IP_UCNR_SC2_Main); ++ MDrv_PQ_LoadTable(PQ_SC2_MAIN_WINDOW, PQ_IP_UC_CTL_OFF_SC2_Main, PQ_IP_UC_CTL_SC2_Main); ++ MDrv_PQ_LoadTable(PQ_SC2_MAIN_WINDOW, PQ_IP_UCDi_OFF_SC2_Main, PQ_IP_UCDi_SC2_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(PQ_SUB_WINDOW == eWindow) ++ { ++ #if defined(AMBER3) ++ MDrv_PQ_LoadTable(PQ_SC2_SUB_WINDOW, PQ_IP_UCNR_OFF_SC2_Sub, PQ_IP_UCNR_SC2_Sub); ++ MDrv_PQ_LoadTable(PQ_SC2_SUB_WINDOW, PQ_IP_UC_CTL_OFF_SC2_Sub, PQ_IP_UC_CTL_SC2_Sub); ++ MDrv_PQ_LoadTable(PQ_SC2_SUB_WINDOW, PQ_IP_UCDi_OFF_SC2_Sub, PQ_IP_UCDi_SC2_Sub); ++ #endif ++ } ++#endif ++#endif ++ ++ bRet = TRUE; ++#else ++ UNUSED(eWindow); ++ bRet = FALSE; ++#endif ++ return bRet; ++} ++ ++E_DRVPQ_ReturnValue MDrv_PQ_GetLibVer(const MSIF_Version **ppVersion) ++{ ++ if(ppVersion == NULL) ++ { ++ return E_DRVPQ_RET_FAIL; ++ } ++ ++ *ppVersion = &_drv_pq_version; ++ return E_DRVPQ_RET_OK; ++} ++ ++ ++PQ_ReturnValue MDrv_PQ_GetInfo(MS_PQ_INFO *pInfo) ++{ ++ MsOS_Memcpy((void*)pInfo, (void*)&_info, sizeof(MS_PQ_INFO)); ++ return E_PQ_RET_OK; ++} ++ ++MS_BOOL MDrv_PQ_GetStatus(MS_PQ_Status *pStatus) ++{ ++ MsOS_Memcpy((void*)pStatus, (void*)&_status, sizeof(MS_PQ_Status)); ++ return FALSE; ++} ++ ++MS_BOOL MDrv_PQ_SetDbgLevel(MS_U16 u16DbgSwitch) ++{ ++ _u16PQDbgSwitch = u16DbgSwitch; ++ return TRUE; ++} ++ ++void MDrv_PQ_Set_DisplayType(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, PQ_WIN ePQWin) ++{ ++ printf("!!!!!SetDisplayType %d %d \r\n", u16DisplayWidth, enDisplaType); ++#if (PQ_ENABLE_PIP) ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ if(ePQWin == PQ_SC1_MAIN_WINDOW) ++ { ++ MDrv_PQBin_SetPanelID(0, PQ_SC1_MAIN_WINDOW); ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, ePQWin); ++ } ++ else ++ { ++ PQ_BIN_DISPLAY_TYPE enBinDispType; ++ ++ MDrv_PQBin_SetPanelID(u16DisplayWidth == 1366 ? 1 : 1, ePQWin); ++ ++ enBinDispType = enDisplaType == PQ_DISPLAY_ONE ? PQ_BIN_DISPLAY_ONE : ++ enDisplaType == PQ_DISPLAY_PIP ? PQ_BIN_DISPLAY_PIP : ++ PQ_BIN_DISPLAY_POP; ++ MDrv_PQBin_SetDisplayType(enBinDispType, ePQWin); ++ } ++ ++ } ++ else ++#endif ++ { ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ MS_BOOL bSkipCommTable = TRUE; ++ ++ if(genDisplayType != enDisplaType) ++ { ++ MDrv_PQ_Set_DisplayType_Sub(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_Main(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Sub(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Main(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC1_Main(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ ++ genDisplayType = enDisplaType; ++ } ++ ++#endif // #if PQ_ONLY_SUPPORT_BIN ++ ++ } ++ ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++#endif ++} ++ ++PQ_DISPLAY_TYPE MDrv_PQ_Get_DisplayType(void) ++{ ++#if (PQ_ENABLE_PIP) ++ ++ return genDisplayType; ++#else ++ return PQ_DISPLAY_ONE; ++#endif ++} ++ ++void MDrv_PQ_MADiForceMotionC(PQ_WIN eWindow, MS_BOOL bEnable) ++{ ++ MS_U16 u16DataC = 0; ++ u16DataC = Hal_PQ_get_force_c_motion(eWindow); ++ ++#if (PQ_ENABLE_PIP) ++ if(eWindow == PQ_SUB_WINDOW || eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ u16DataC <<= 8; ++ } ++#endif ++ ++ if(bEnable) ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ u16DataC |= 0x0080; ++ } ++ else ++ { ++ u16DataC |= 0x8000; ++ } ++ } ++ else ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ u16DataC &= 0x000F; ++ } ++ else ++ { ++ u16DataC &= 0x0F00; ++ } ++ } ++ Hal_PQ_set_force_c_motion(eWindow, u16DataC); ++ ++} ++ ++void MDrv_PQ_MADiForceMotionY(PQ_WIN eWindow, MS_BOOL bEnable) ++{ ++ MS_U16 u16Data = 0; ++ ++ u16Data = Hal_PQ_get_force_y_motion(eWindow); ++ ++#if (PQ_ENABLE_PIP) ++ if(eWindow == PQ_SUB_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC2_SUB_WINDOW ++ #endif ++ ) ++ { ++ u16Data <<= 8; ++ } ++#endif ++ ++ if(bEnable) ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ u16Data |= 0x0080; ++ else ++ u16Data |= 0x8000; ++ } ++ else ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ u16Data &= 0x003F; ++ else ++ u16Data &= 0x3F00; ++ } ++ ++ Hal_PQ_set_force_y_motion(eWindow, u16Data); ++} ++ ++void MDrv_PQ_SetRFblMode(MS_BOOL bEnable, MS_BOOL bFilm) ++{ ++ _stRFBL_Info.bEnable = bEnable; ++ _stRFBL_Info.bFilm = bFilm; ++ ++ if(!bEnable) //default mode ++ { ++ MDrv_PQ_MADiForceMotionY(PQ_MAIN_WINDOW, FALSE); ++ MDrv_PQ_MADiForceMotionC(PQ_MAIN_WINDOW, FALSE); ++ ++ _stRFBL_Info.u8MADiType = MS_MADI_24_2R; ++ //printf("[%s]-[%d] : Y/C motion : ( 0 , 0 ) \r\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ _stRFBL_Info.u8MADiType = (bFilm) ? (MS_U8)MS_MADI_24_RFBL_FILM : (MS_U8)MS_MADI_24_RFBL_NFILM; ++ MDrv_PQ_MADiForceMotionY(PQ_MAIN_WINDOW, FALSE); ++ MDrv_PQ_MADiForceMotionC(PQ_MAIN_WINDOW, (!bFilm)); ++ ++ //printf("[%s]-[%d] : Y/C motion : ( 0 , %d) \r\n", __FUNCTION__, __LINE__,(!bFilm)); ++ } ++} ++ ++void MDrv_PQ_GetRFblMode(MS_PQ_RFBL_INFO * pstInfo) ++{ ++ MsOS_Memcpy(pstInfo, &_stRFBL_Info, sizeof(MS_PQ_RFBL_INFO)); ++ return; ++} ++ ++#if (PQ_ENABLE_VD_SAMPLING) ++ ++MS_BOOL MDrv_PQ_Get_VDSampling_Info(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, PQ_VIDEOSTANDARD_TYPE eStandard, MS_PQ_VD_Sampling_Info *pInfo) ++{ ++ PQ_VIDEOSTANDARD_TYPE eCurStandard = _stVD_Info[eWindow].enVideoStandard; ++ MS_U16 u16CurSrc = _u16PQSrcType[eWindow]; ++ MS_U16 u16TableIdx; ++ MS_U16 u16IPIdx = Hal_PQ_get_ip_idx(MS_PQ_IP_VD_SAMPLING); ++ MS_U8 u8SampleTable[10]; ++ ++ MsOS_Memset(u8SampleTable, 0, sizeof(u8SampleTable)); ++ ++ PQINFO_DBG(printf("[PQ] GetVDSampling: win:%d, src:%d, standard:%d, PQIP=%x\r\n", eWindow, enInputSourceType, eStandard, u16IPIdx)); ++ if((((enInputSourceType >= PQ_INPUT_SOURCE_TV) && (enInputSourceType <= PQ_INPUT_SOURCE_SVIDEO))||(enInputSourceType == PQ_INPUT_SOURCE_SCART)) && ++ (eStandard < E_PQ_VIDEOSTANDARD_NOTSTANDARD) && ++ (u16IPIdx != 0xFFFF)) ++ { ++ _stVD_Info[eWindow].enVideoStandard = eStandard; ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ ++ ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ PQINFO_DBG(printf("[PQ] VDSampling: TableIdx=%d\r\n", u16TableIdx)); ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TableIdx == PQ_BIN_IP_NULL)) ++ || ((gbPQBinEnable == 0) && (u16TableIdx == PQ_IP_NULL))) ++#else ++ if(u16TableIdx == PQ_IP_NULL) ++#endif ++ { ++ pInfo->eType = PQ_VD_SAMPLING_OFF; ++ } ++ else ++ { ++ MDrv_PQ_LoadTableData(eWindow, u16TableIdx, u16IPIdx, u8SampleTable, 10); ++ pInfo->u16Vstart = ((MS_U16)u8SampleTable[0]) | (((MS_U16)u8SampleTable[1])<<8); ++ pInfo->u16Hstart = ((MS_U16)u8SampleTable[2]) | (((MS_U16)u8SampleTable[3])<<8); ++ pInfo->u16Hsize = ((MS_U16)u8SampleTable[4]) | (((MS_U16)u8SampleTable[5]) << 8); ++ pInfo->u16Vsize = ((MS_U16)u8SampleTable[6]) | (((MS_U16)u8SampleTable[7]) << 8); ++ pInfo->u16Htt = ((MS_U16)u8SampleTable[8]) | (((MS_U16)u8SampleTable[9]) << 8); ++ pInfo->eType = PQ_VD_SAMPLING_ON; ++ ++ PQINFO_DBG(printf("VD x:%x, y:%x, w:%x, h:%x, Htt=%x \r\n", ++ pInfo->u16Hstart, pInfo->u16Vstart, pInfo->u16Hsize, pInfo->u16Vsize, pInfo->u16Htt)); ++ } ++ ++ _stVD_Info[eWindow].enVideoStandard = eCurStandard; ++ _u16PQSrcType[eWindow] = u16CurSrc; ++ } ++ else ++ { ++ pInfo->eType = PQ_VD_SAMPLING_OFF; ++ } ++ return TRUE; ++} ++ ++#endif ++ ++ ++MS_BOOL _MDrv_PQ_Get_HSDSampling(PQ_WIN eWindow, MS_U32 *pu32ratio, MS_BOOL *bADVMode) ++{ ++#if PQ_ENABLE_HSDRULE ++ ++ MS_U16 u16IPIdx = Hal_PQ_get_ip_idx(MS_PQ_IP_HSD_SAMPLING); ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ if(u16IPIdx != 0xFFFF) ++ { ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ } ++ else ++ { ++#if(ENABLE_PQ_BIN) ++ u16TableIdx = (gbPQBinEnable) ? PQ_BIN_IP_NULL : PQ_IP_NULL; ++#else ++ u16TableIdx = PQ_IP_NULL; ++#endif ++ } ++ ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TableIdx == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TableIdx == PQ_IP_NULL))) ++#else ++ if(u16TableIdx == PQ_IP_NULL) ++#endif ++ { ++ *pu32ratio = 0; ++ bret = FALSE; ++ } ++ ++#if(PQ_ONLY_SUPPORT_BIN) ++ else if((( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_Y_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])) || ++ ( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_C_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])))) ++#elif(ENABLE_PQ_BIN) ++ else if(((gbPQBinEnable == 1) && ++ (( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_Y_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])) || ++ ( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_C_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])))) ++ || ++ ((MST_SkipRule_IP_Main[PQ_IP_HSD_Y_Main] == 1) || (MST_SkipRule_IP_Main[PQ_IP_HSD_C_Main] == 1)) ++ ) ++#else ++ else if((MST_SkipRule_IP_Main[PQ_IP_HSD_Y_Main] == 1) || (MST_SkipRule_IP_Main[PQ_IP_HSD_C_Main] == 1)) ++#endif ++ { ++ SRULE_DBG(printf("HSD_Y, HSD_C is True in SKipRule, driver consider HSDSampling is not defined in QMap.\r\n")); ++ *pu32ratio = 0; ++ bret = FALSE; ++ } ++ else ++ { ++#if PQ_NEW_HSD_SAMPLING_TYPE ++ if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_000)) ++ { ++ *pu32ratio = 1000; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_125)) ++ { ++ *pu32ratio = 875; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_250)) ++ { ++ *pu32ratio = 750; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_375)) ++ { ++ *pu32ratio = 625; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_500)) ++ { ++ *pu32ratio = 500; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_625)) ++ { ++ *pu32ratio = 375; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_750)) ++ { ++ *pu32ratio = 250; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_875)) ++ { ++ *pu32ratio = 125; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_2_000)) ++ { ++ *pu32ratio = 1; ++ } ++ else ++#endif ++ { ++ *pu32ratio = 0; ++ } ++ ++ bret = TRUE; ++ } ++ ++ // Load HSD_Y & HSD_C ++ if(bret) ++ { ++ MS_U16 u16HSD_Y_idx, u16HSD_C_idx; ++ ++ u16HSD_Y_idx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_HSD_Y_Main); ++ MDrv_PQ_LoadTable(eWindow, u16HSD_Y_idx, PQ_IP_HSD_Y_Main); ++ ++ u16HSD_C_idx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_HSD_C_Main); ++ MDrv_PQ_LoadTable(eWindow, u16HSD_C_idx, PQ_IP_HSD_C_Main); ++ ++ SRULE_DBG(printf("HSD_Y:%d, HSD_C:%d\r\n", u16HSD_Y_idx, u16HSD_C_idx)); ++ ++ *bADVMode = ((u16HSD_Y_idx == PQ_IP_HSD_Y_CB_Main) && ++ (u16HSD_C_idx == PQ_IP_HSD_C_CB_Main)) ? FALSE : TRUE; ++ } ++ else ++ { ++ *bADVMode = FALSE; ++ } ++ ++ ++ SRULE_DBG(printf("[PQ] GetHSDSampling, IPIdx=%d, Table=%d, ratio=%ld ret=%d\r\n", u16IPIdx, u16TableIdx, *pu32ratio, bret)); ++ ++ return bret; ++#else ++ return TRUE; ++#endif ++ ++} ++ ++ ++MS_BOOL MDrv_PQ_IOCTL(PQ_WIN eWindow, MS_U32 u32Flag, void *pBuf, MS_U32 u32BufSize) ++{ ++ MS_BOOL bret = TRUE; ++ ++ switch(u32Flag) ++ { ++ case E_PQ_IOCTL_HSD_SAMPLING: ++ { ++ if(u32BufSize == sizeof(PQ_HSD_SAMPLING_INFO)) ++ { ++ MS_U32 u32ratio; ++ MS_BOOL bADVMode; ++ ++ bret = _MDrv_PQ_Get_HSDSampling(eWindow, &u32ratio, &bADVMode); ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->u32ratio = u32ratio; ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->bADVMode = bADVMode; ++ bret = TRUE; ++ ++ //printf("ratio %lx, bADVmode=%d\r\n\r\n",((PQ_HSD_SAMPLING_INFO *)pBuf)->u32ratio, ((PQ_HSD_SAMPLING_INFO *)pBuf)->bADVMode); ++ ++ } ++ else ++ { ++ //printf("Size is not correct, in=%ld, %d\r\n", u32BufSize, sizeof(PQ_HSD_SAMPLING_INFO)); ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->u32ratio = 0; ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->bADVMode = 0; ++ bret = FALSE; ++ } ++ break; ++ } ++ ++ case E_PQ_IOCTL_PREVSD_BILINEAR: ++ bret = TRUE; ++ *((MS_BOOL *)pBuf) = TRUE; ++ break; ++ ++ case E_PQ_IOCTL_ADC_SAMPLING: ++ if(u32BufSize == sizeof(PQ_ADC_SAMPLING_INFO)) ++ { ++ ++ PQ_INPUT_SOURCE_TYPE enInputSrc = ((PQ_ADC_SAMPLING_INFO *)pBuf)->enPQSourceType; ++ MS_PQ_Mode_Info *pModeInfo = &(((PQ_ADC_SAMPLING_INFO *)pBuf)->stPQModeInfo); ++ MS_PQ_ADC_SAMPLING_TYPE enADCSamplingType = MDrv_PQ_Get_ADCSampling_Info(eWindow, enInputSrc, pModeInfo); ++ ++ if((enADCSamplingType == E_PQ_ADC_SAMPLING_NOT_SUPPORT) || (enADCSamplingType == E_PQ_ADC_SAMPLING_NONE)) ++ { ++ ((PQ_ADC_SAMPLING_INFO *)pBuf)->u16ratio = 1; ++ bret = FALSE; ++ } ++ else ++ { ++ ((PQ_ADC_SAMPLING_INFO *)pBuf)->u16ratio = (MS_U16)enADCSamplingType; ++ bret = TRUE; ++ } ++ } ++ else ++ { ++ bret = FALSE; ++ ((PQ_ADC_SAMPLING_INFO *)pBuf)->u16ratio = 1; ++ } ++ break; ++ case E_PQ_IOCTL_RFBL_CTRL: ++ //printf("IOCTL %lx\r\n", u32Flag); ++#if PQ_ENABLE_RFBL ++ bret = MDrv_PQ_Get_RFBL_Info(eWindow); ++#else ++ bret = FALSE; ++#endif ++ UNUSED(pBuf); ++ UNUSED(u32BufSize); ++ break; ++ ++ default: ++ printf("unknown IOCTL %lx\r\n", u32Flag); ++ UNUSED(pBuf); ++ UNUSED(u32BufSize); ++ bret = FALSE; ++ break; ++ } ++ ++ //printf("[PQ] IOCTL : win:%x, Flag=%08lx, size=%ld, ret:%x\r\n", eWindow, u32Flag, u32BufSize, bret); ++ ++ return bret; ++} ++ ++ ++MS_PQ_ADC_SAMPLING_TYPE MDrv_PQ_Get_ADCSampling_Info(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info *pstPQModeInfo) ++{ ++ MS_PQ_ADC_SAMPLING_TYPE enRetType; ++ MS_U16 u16PQSrcType; ++ MS_U16 u16TableIdx; ++ MS_PQ_Mode_Info stModeInfo; ++ ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ MsOS_Memcpy(&stModeInfo, &_stMode_Info[eWindow], sizeof(MS_PQ_Mode_Info)); ++ ++ MDrv_PQ_Set_ModeInfo(eWindow, enInputSourceType, pstPQModeInfo); ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ ++ if(Hal_PQ_get_ip_idx(MS_PQ_IP_ADC_SAMPLING) == 0xFFFF) ++ { ++ return E_PQ_ADC_SAMPLING_NOT_SUPPORT; ++ } ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, Hal_PQ_get_ip_idx(MS_PQ_IP_ADC_SAMPLING)); ++ ++ if(u16TableIdx == Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_X_1)) ++ { ++ enRetType = E_PQ_ADC_SAMPLING_X_1; ++ } ++ else if(u16TableIdx == Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_X_2)) ++ { ++ enRetType = E_PQ_ADC_SAMPLING_X_2; ++ } ++ else if(u16TableIdx == Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_X_4)) ++ { ++ enRetType = E_PQ_ADC_SAMPLING_X_4; ++ } ++ else ++ { ++ enRetType = E_PQ_ADC_SAMPLING_NONE; ++ } ++ ++ MsOS_Memcpy(&_stMode_Info[eWindow], &stModeInfo, sizeof(MS_PQ_Mode_Info)); ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ ++ return enRetType; ++} ++ ++MS_BOOL MDrv_PQ_Set3D_OnOff(MS_BOOL bEn) ++{ ++ _gIs3D_En = bEn; ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_SetH264_OnOff(MS_BOOL bEn) ++{ ++ _gIsH264 = bEn; ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_SetMM_OnOff(MS_BOOL bEn) ++{ ++ _gIsMMplayer = bEn; ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetCaps(MS_PQ_CAP_INFO *pInfo) ++{ ++ MS_BOOL bRet = TRUE; ++#if(PQ_ENABLE_PIP) ++ const XC_ApiInfo* pXC_ApiInfo = MApi_XC_GetInfo(); ++ if (pXC_ApiInfo != NULL) ++ { ++ pInfo->bPIP_Supported = ((pXC_ApiInfo->u8MaxWindowNum) >= 2) ? TRUE : FALSE; ++ } ++ else ++ { ++ pInfo->bPIP_Supported = FALSE; ++ bRet = FALSE; ++ } ++#else ++ pInfo->bPIP_Supported = FALSE; ++#endif ++ ++#if(PQ_ENABLE_3D_VIDEO) ++ pInfo->b3DVideo_Supported = TRUE; ++#else ++ pInfo->b3DVideo_Supported = FALSE; ++#endif ++ ++ return bRet; ++} ++ ++void MDRV_PQ_PrintLoadTableInfo(MS_PQ_PQLOADTABLE_WIN enPQWin) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++ MS_U16 u16IPIdx; ++ MS_U8 u8TabIdx; ++ MS_U16 u16IPNum; ++ ++ if(enPQWin == PQ_LOAD_TABLE_MAIN) ++ printf("[TableInfo::Main] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_MAIN_EX) ++ printf("[TableInfo::Main Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SUB) ++ printf("[TableInfo::SUB] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SUB_EX) ++ printf("[TableInfo::SUB Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN) ++ printf("[TableInfo::SC1_Main] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN_EX) ++ printf("[TableInfo::SC1_Main Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN) ++ printf("[TableInfo::SC2_Main] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN_EX) ++ printf("[TableInfo::SC2_Main Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB) ++ printf("[TableInfo::SC2_SUB] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB_EX) ++ printf("[TableInfo::SC2_SUB Ex] \r\n"); ++ else ++ return; ++ ++ u16IPNum = enPQWin == PQ_LOAD_TABLE_MAIN ? PQ_IP_NUM_Main : ++ enPQWin == PQ_LOAD_TABLE_MAIN_EX ? PQ_IP_NUM_Main_Ex : ++ enPQWin == PQ_LOAD_TABLE_SUB ? PQ_IP_NUM_Sub : ++ enPQWin == PQ_LOAD_TABLE_SUB_EX ? PQ_IP_NUM_Sub_Ex : ++ enPQWin == PQ_LOAD_TABLE_SC1_MAIN ? PQ_IP_NUM_SC1_Main : ++ enPQWin == PQ_LOAD_TABLE_SC1_MAIN_EX ? PQ_IP_NUM_SC1_Main_Ex : ++ enPQWin == PQ_LOAD_TABLE_SC2_MAIN ? PQ_IP_NUM_SC2_Main : ++ enPQWin == PQ_LOAD_TABLE_SC2_MAIN_EX ? PQ_IP_NUM_SC2_Main_Ex : ++ enPQWin == PQ_LOAD_TABLE_SC2_SUB ? PQ_IP_NUM_SC2_Sub : ++ enPQWin == PQ_LOAD_TABLE_SC2_SUB_EX ? PQ_IP_NUM_SC2_Sub_Ex : ++ 0; ++ ++ for(u16IPIdx = 0; u16IPIdx < u16IPNum; ++ u16IPIdx) ++ { ++ printf(" %u(%s)=", u16IPIdx, MDrv_PQ_GetIPName(u16IPIdx)); // IP Name ++ ++ if(enPQWin == PQ_LOAD_TABLE_MAIN) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(MAIN, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_MAIN_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(MAINEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ } ++ ++#if PQ_ENABLE_PIP ++ else if(enPQWin == PQ_LOAD_TABLE_SUB) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SUB, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SUB_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SUBEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ ++ } ++#endif ++ ++#if defined(CEDRIC) ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC1_MAIN, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC1_MAINEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ } ++ ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_MAIN, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_MAINEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ } ++ ++#if PQ_ENABLE_PIP ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_SUB, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_SUBEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ ++ } ++#endif ++ ++#endif // CEDRIC ++ else ++ { ++ } ++ } ++#else ++ UNUSED(enPQWin); ++#endif ++} ++ ++MS_BOOL MDrv_PQ_SetDS_OnOFF(PQ_WIN eWindow, MS_BOOL bEn) ++{ ++ //store the original value ++ _u16RW_Method = Hal_PQ_get_rw_method(eWindow); ++ if(bEn) ++ { ++ _bDS_En = TRUE; ++ } ++ else ++ { ++ _bDS_En = FALSE; ++ Hal_PQ_set_rw_method(eWindow, _u16RW_Method); ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_Get_RFBL_Info(PQ_WIN eWindow) ++{ ++#if 0//Ryan ++ ++ MS_BOOL bret = TRUE; ++ ++ MS_U16 u16TabIdx_MADi = 0; ++// PQ_WIN eWindow = (bIsMainWindow == TRUE) ? (PQ_MAIN_WINDOW):(PQ_SUB_WINDOW); ++ ++ u16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Main); ++ (printf("[PQ] MADI: u16TabIdx_MADi=%d\r\n", u16TabIdx_MADi)); ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TabIdx_MADi == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TabIdx_MADi == PQ_IP_NULL))) ++#else ++ if(u16TabIdx_MADi == PQ_IP_NULL) ++#endif ++ { ++ MApi_XC_EnableRequest_FrameBufferLess(DISABLE); ++ ++ bret = FALSE; ++ printf("[PQ] MADI: Get Null\r\n"); ++ printf("[PQ] MADI: DISABLE RFBL\r\n"); ++ ++ } ++ else ++ { ++ if((u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_2D)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_25D)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_YC)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_FILM)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE10_MOT)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE8_MOT)) ++ ++ ) ++ { ++ MApi_XC_EnableRequest_FrameBufferLess(ENABLE); ++ printf("[PQ] MADI: ENABLE RFBL\r\n"); ++ ++ } ++ else ++ { ++ MApi_XC_EnableRequest_FrameBufferLess(DISABLE); ++ printf("[PQ] MADI: DISABLE RFBL\r\n"); ++ ++ } ++ bret = TRUE; ++ } ++ ++ return bret; ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_CheckHDMode(PQ_WIN eWindow) ++{ ++ return _gIsSrcHDMode[eWindow]; ++} ++ ++//for Super Resolution interlace and SD mode detected use ++MS_BOOL MDrv_PQ_Get_Interlace_SD_mode(PQ_WIN ePQWin) ++{ ++ if(QM_IsInterlaced(ePQWin) && (QM_GetInputHSize(ePQWin) < 1500)) ++ { ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++#if PQ_GRULE_PTP_ENABLE ++static void _MDrv_PQ_LoadPTPTable(PQ_WIN eWindow, MS_U16 u16PQ_PTP_Idx) ++{ ++ MS_U16 i, u16IPIdx=0, u16TabIdx=0; ++ ++ if (u16PQ_PTP_Idx > PQ_GRULE_PTP_LVL_NUM_Main){ ++ MS_ASSERT(0); return; ++ } ++ ++ for(i=0; istDispWin.x = (_stPQ_Info.u16PnlWidth - pstXC_SetWin_Info->stCropWin.width)/2; ++ pstXC_SetWin_Info->stDispWin.width = pstXC_SetWin_Info->stCropWin.width; ++ pstXC_SetWin_Info->stDispWin.y = (_stPQ_Info.u16PnlHeight- pstXC_SetWin_Info->stCropWin.height)/2; ++ pstXC_SetWin_Info->stDispWin.height = pstXC_SetWin_Info->stCropWin.height; ++ ++ //RGB HDMI, DVI, VGA ++ if((((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == TRUE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == FALSE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ (IsSrcTypeVga(pstXC_SetWin_Info->enInputSourceType))) && ++ (!pstXC_SetWin_Info->bInterlace)) ++ { ++ MApi_XC_EnableForceRGBin(TRUE, MAIN_WINDOW); ++ } ++ MApi_XC_Set_MemFmt(E_MS_XC_MEM_FMT_444); ++ } ++ else ++ { ++ MApi_XC_EnableForceRGBin(FALSE, MAIN_WINDOW); ++ MApi_XC_Set_MemFmt(E_MS_XC_MEM_FMT_AUTO); ++ } ++ ++ PQP2P_DBG(printf("[MDrv_PQ_Set_PointToPoint] True or False: %u\r\n",bEnable);) ++ _bPointToPointMode = bEnable; ++ ++ return TRUE; ++#endif ++} ++#endif ++ ++MS_BOOL MDrv_PQ_Get_PointToPoint(PQ_WIN eWindow) ++{ ++ UNUSED(eWindow); ++ return _bPointToPointMode; ++} ++ ++#if 0//Ryan ++MS_BOOL MDrv_PQ_Check_PointToPoint_Condition(XC_SETWIN_INFO *pstXC_SetWin_Info,PQ_WIN eWindow) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ UNUSED(eWindow); ++ ++#if PQ_GRULE_PTP_ENABLE ++ // HDMI RGB, HDMI YUV444, DVI, YPbPr, VGA. ++ // all in progressive mode ++ PQP2P_DBG(printf("----HDMI source=%u, HDMIPacket=%u, RGB=%u, YUV444=%u, Ypbpr=%u, VGA=%u, interlace=%u\r\n", ++ (IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)), ++ (_stHDMI_Info[eWindow].bIsHDMI == TRUE), ++ (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW)), ++ (QM_HDMIPC_COLORYUV444(PQ_MAIN_WINDOW)), ++ (IsSrcTypeYPbPr(pstXC_SetWin_Info->enInputSourceType)), ++ (IsSrcTypeVga(pstXC_SetWin_Info->enInputSourceType)), ++ (pstXC_SetWin_Info->bInterlace) ++ );) ++ //at this time, the PQ input source has not been inited. so we use XC_SETWIN_INFO to check ++ //we cannot do the PTP when timing size is bigger than panel size ++ if((((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == TRUE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == TRUE) && (QM_HDMIPC_COLORYUV444(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == FALSE) && (QM_HDMIPC_COLORYUV444(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == FALSE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ (IsSrcTypeVga(pstXC_SetWin_Info->enInputSourceType)) || ++ (IsSrcTypeYPbPr(pstXC_SetWin_Info->enInputSourceType))) && ++ (!pstXC_SetWin_Info->bInterlace) && ++ ((_stPQ_Info.u16PnlWidth >= pstXC_SetWin_Info->stCropWin.width) && (_stPQ_Info.u16PnlHeight >= pstXC_SetWin_Info->stCropWin.height))) ++ { ++ bRet = TRUE; ++ } ++#else ++ UNUSED(pstXC_SetWin_Info); ++#endif ++ ++ PQP2P_DBG(printf("[MDrv_PQ_Check_PointToPoint_Condition] %u\r\n",bRet);) ++ ++ return bRet; ++} ++#endif ++ ++MS_BOOL MDrv_PQ_Update_MemFormat(void) ++{ ++ MS_U8 u8BitPerPixel = 0; ++ MDrv_PQ_SetMemFormat( ++ PQ_MAIN_WINDOW, ++ _gbMemfmt422[PQ_MAIN_WINDOW], ++ _stMode_Info[PQ_MAIN_WINDOW].bFBL, ++ &u8BitPerPixel); ++ ++ return TRUE; ++} ++ ++MS_U16 MDrv_PQ_GetVsize(void) ++{ ++ return _stMode_Info[PQ_MAIN_WINDOW].u16input_vsize; ++} ++ ++MS_BOOL MDrv_PQ_LOW_3dQuality(MS_BOOL bEnable) ++{ ++ if(bEnable) ++ { ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_Peaking_band_AV_NTSC_Main, PQ_IP_VIP_Peaking_band_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_VNMR_S2_Main, PQ_IP_VIP_VNMR_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_VLPF_coef1_0x6_Main, PQ_IP_VIP_VLPF_coef1_Main); ++#endif ++ } ++ else ++ { ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_Peaking_band_Main), PQ_IP_VIP_Peaking_band_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_VNMR_Main), PQ_IP_VIP_VNMR_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_VLPF_coef1_Main), PQ_IP_VIP_VLPF_coef1_Main); ++#endif ++ } ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_SetEnhanceQuality(void) ++{ ++#if PQ_VIP_RGBCMY_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_R_INC_3_Main, PQ_IP_VIP_ICC_R_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_G_INC_8_Main, PQ_IP_VIP_ICC_G_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_B_INC_6_Main, PQ_IP_VIP_ICC_B_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_C_INC_6_Main, PQ_IP_VIP_ICC_C_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_M_INC_6_Main, PQ_IP_VIP_ICC_M_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_Y_INC_7_Main, PQ_IP_VIP_ICC_Y_Main); ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_RestoreEnhanceQuality(void) ++{ ++#if PQ_VIP_RGBCMY_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_R_Main), PQ_IP_VIP_ICC_R_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_G_Main), PQ_IP_VIP_ICC_G_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_B_Main), PQ_IP_VIP_ICC_B_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_C_Main), PQ_IP_VIP_ICC_C_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_M_Main), PQ_IP_VIP_ICC_M_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_Y_Main), PQ_IP_VIP_ICC_Y_Main); ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_RestoreOffQuality(void) ++{ ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_ON_Main, PQ_IP_VIP_ICC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IBC_ON_Main, PQ_IP_VIP_IBC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IHC_ON_Main, PQ_IP_VIP_IHC_Main); ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_SetOffQuality(void) ++{ ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_OFF_Main, PQ_IP_VIP_ICC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IBC_OFF_Main, PQ_IP_VIP_IBC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IHC_OFF_Main, PQ_IP_VIP_IHC_Main); ++#endif ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// selection to VIP CSC ++// Both equation selection rules are ++// 0: SDTV(601) R G B : 16-235 ++// 1: SDTV(601) R G B : 0-255 ++/// @param bMainWin \b IN: Enable ++//------------------------------------------------------------------------------------------------- ++void MDrv_PQ_SetSelectCSC(MS_U16 u16selection, PQ_WIN ePQWin) ++{ ++ HAL_PQ_set_SelectCSC(u16selection, ePQWin); ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_Sub(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++ ++#if PQ_ENABLE_PIP && (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ PQTableInfo.eWin = PQ_SUB_WINDOW; ++ // Load Sub PQ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_Sub; ++ #endif ++ } ++ break; ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SUB_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Sub; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_Sub; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Sub; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_Sub; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_Sub; ++ #endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_Sub; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_Sub; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_Sub; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_Sub; ++#endif ++ ++ ++ MDrv_PQ_AddTable_(SUB, &PQTableInfo); ++ ++ ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SUB); ++ } ++ ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Sub_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_Sub_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Sub_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_Sub_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub_Ex; ++ } ++ break; ++ } ++ MDrv_PQ_AddTable_(SUBEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SUBEX); ++ } ++ ++ return TRUE; ++ ++ ++#else ++ ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++ ++#endif ++} ++ ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_SC1_Main(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if 0//Ryan ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ printf("++++MDrv_PQ_Set_DisplayType_SC1_Main++++ \r\n"); ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfo.pQuality_Map_Aray = (void*)(QMAP_720_SC1_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)(MST_GRule_720_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)(MST_GRule_720_MPEG_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)(MST_GRule_720_FILM_MODE_SC1_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)(MST_GRule_720_DYNAMIC_CONTRAST_SC1_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)(MST_GRule_720_ULTRAT_CLEAR_SC1_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)(MST_GRule_720_DDR_SELECT_SC1_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)(MST_GRule_720_OSD_BW_SC1_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)(MST_GRule_PTP_SC1_Main); ++#endif ++ break; ++#if PQ_ENABLE_PIP_SC1 //// JoshChiang++, 20120730 //// ++ case PQ_DISPLAY_PIP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_PIP_SC1_Main: QMAP_1920_PIP_SC1_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_NR_SC1_Main: MST_GRule_1920_PIP_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_MPEG_NR_SC1_Main:MST_GRule_1920_PIP_MPEG_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_FILM_MODE_SC1_Main:MST_GRule_1920_PIP_FILM_MODE_SC1_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC1_Main:MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC1_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_ULTRAT_CLEAR_SC1_Main:MST_GRule_1920_PIP_ULTRAT_CLEAR_SC1_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DDR_SELECT_SC1_Main:MST_GRule_1920_PIP_DDR_SELECT_SC1_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_OSD_BW_SC1_Main:MST_GRule_1920_PIP_OSD_BW_SC1_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_PTP_SC1_Main:MST_GRule_1920_PIP_PTP_SC1_Main); ++#endif ++ ++ break; ++ ++ case PQ_DISPLAY_POP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_POP_SC1_Main: QMAP_1920_POP_SC1_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_NR_SC1_Main: MST_GRule_1920_POP_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_MPEG_NR_SC1_Main:MST_GRule_1920_POP_MPEG_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_FILM_MODE_SC1_Main:MST_GRule_1920_POP_FILM_MODE_SC1_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC1_Main:MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC1_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_ULTRAT_CLEAR_SC1_Main:MST_GRule_1920_POP_ULTRAT_CLEAR_SC1_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DDR_SELECT_SC1_Main:MST_GRule_1920_POP_DDR_SELECT_SC1_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_OSD_BW_SC1_Main:MST_GRule_1920_POP_OSD_BW_SC1_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_PTP_SC1_Main:MST_GRule_1920_POP_PTP_SC1_Main); ++#endif ++ break; ++#endif ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SC1_MAIN_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC1_Main; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_SC1_Main; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC1_Main; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_SC1_Main; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_SC1_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_SC1_Main; ++#endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_SC1_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_SC1_Main; ++#endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_SC1_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_PTP] = PQ_GRULE_PTP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_PTP] = PQ_GRULE_PTP_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_PTP] = (void*)MST_GRule_PTP_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_PTP] = (void*)MST_GRule_PTP_SC1_Main; ++#endif ++ ++ MDrv_PQ_AddTable_(SC1_MAIN, &PQTableInfo); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC1_MAIN); ++ } ++ ++#if (ENABLE_PQ_EX) ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC1_Main_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_SC1_Main_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC1_Main_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_SC1_Main_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_720_SC1_Main_Ex; ++ break; ++ ++ case PQ_DISPLAY_PIP: ++#if PQ_ENABLE_PIP_SC1 //// JoshChiang++, 20120730 //// ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC1_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC1_Main_Ex; ++ } ++#endif ++ break; ++ ++ case PQ_DISPLAY_POP: ++#if PQ_ENABLE_PIP_SC1 //// JoshChiang++, 20120730 //// ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC1_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC1_Main_Ex; ++ } ++#endif ++ break; ++ } ++ ++ MDrv_PQ_AddTable_(SC1_MAINEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC1_MAINEX); ++ } ++ if((MS_U16)QM_INPUTTYPE_NUM_SC1_Main != (MS_U16)QM_INPUTTYPE_NUM_SC1_Main_Ex) ++ { ++ printf("PQ INPUTTYPE NUM MISMATCH: MAIN != EX"); ++ MS_ASSERT(0); ++ } ++#endif ++ return TRUE; ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++#endif ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_SC2_Main(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if 0//Ryan ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ printf("++++MDrv_PQ_Set_DisplayType_SC2_Main++++ \r\n"); ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_SC2_Main: QMAP_1920_SC2_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_NR_SC2_Main: MST_GRule_1920_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_MPEG_NR_SC2_Main:MST_GRule_1920_MPEG_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_FILM_MODE_SC2_Main:MST_GRule_1920_FILM_MODE_SC2_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DYNAMIC_CONTRAST_SC2_Main:MST_GRule_1920_DYNAMIC_CONTRAST_SC2_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_ULTRAT_CLEAR_SC2_Main:MST_GRule_1920_ULTRAT_CLEAR_SC2_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DDR_SELECT_SC2_Main:MST_GRule_1920_DDR_SELECT_SC2_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_OSD_BW_SC2_Main:MST_GRule_1920_OSD_BW_SC2_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PTP_SC2_Main:MST_GRule_1920_PTP_SC2_Main); ++#endif ++ break; ++#if PQ_ENABLE_PIP ++ case PQ_DISPLAY_PIP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_PIP_SC2_Main: QMAP_1920_PIP_SC2_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_NR_SC2_Main: MST_GRule_1920_PIP_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_MPEG_NR_SC2_Main:MST_GRule_1920_PIP_MPEG_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_FILM_MODE_SC2_Main:MST_GRule_1920_PIP_FILM_MODE_SC2_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC2_Main:MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC2_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_ULTRAT_CLEAR_SC2_Main:MST_GRule_1920_PIP_ULTRAT_CLEAR_SC2_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DDR_SELECT_SC2_Main:MST_GRule_1920_PIP_DDR_SELECT_SC2_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_OSD_BW_SC2_Main:MST_GRule_1920_PIP_OSD_BW_SC2_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_PTP_SC2_Main:MST_GRule_1920_PIP_PTP_SC2_Main); ++#endif ++ ++ break; ++ ++ case PQ_DISPLAY_POP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_POP_SC2_Main: QMAP_1920_POP_SC2_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_NR_SC2_Main: MST_GRule_1920_POP_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_MPEG_NR_SC2_Main:MST_GRule_1920_POP_MPEG_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_FILM_MODE_SC2_Main:MST_GRule_1920_POP_FILM_MODE_SC2_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC2_Main:MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC2_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_ULTRAT_CLEAR_SC2_Main:MST_GRule_1920_POP_ULTRAT_CLEAR_SC2_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DDR_SELECT_SC2_Main:MST_GRule_1920_POP_DDR_SELECT_SC2_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_OSD_BW_SC2_Main:MST_GRule_1920_POP_OSD_BW_SC2_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_PTP_SC2_Main:MST_GRule_1920_POP_PTP_SC2_Main); ++#endif ++ break; ++#endif ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SC2_MAIN_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Main; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_SC2_Main; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Main; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Main; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_SC2_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_SC2_Main; ++#endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_SC2_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_SC2_Main; ++#endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_SC2_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_PTP] = PQ_GRULE_PTP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_PTP] = PQ_GRULE_PTP_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_PTP] = (void*)MST_GRule_PTP_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_PTP] = (void*)MST_GRule_PTP_SC2_Main; ++#endif ++ ++ MDrv_PQ_AddTable_(SC2_MAIN, &PQTableInfo); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_MAIN); ++ } ++ ++#if (ENABLE_PQ_EX) ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Main_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_SC2_Main_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Main_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Main_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Main_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++#if PQ_ENABLE_PIP ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Main_Ex; ++ } ++#endif ++ break; ++ ++ case PQ_DISPLAY_POP: ++#if PQ_ENABLE_PIP ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Main_Ex; ++ } ++#endif ++ break; ++ } ++ ++ MDrv_PQ_AddTable_(SC2_MAINEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_MAINEX); ++ } ++ if((MS_U16)QM_INPUTTYPE_NUM_SC2_Main != (MS_U16)QM_INPUTTYPE_NUM_SC2_Main_Ex) ++ { ++ printf("PQ INPUTTYPE NUM MISMATCH: MAIN != EX"); ++ MS_ASSERT(0); ++ } ++#endif ++ return TRUE; ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++#endif ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_SC2_Sub(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if 0//Ryan ++#if PQ_ENABLE_PIP && (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ printf("++++MDrv_PQ_Set_DisplayType_SC2_Sub++++ \r\n"); ++ // Load SC2_Sub PQ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_SC2_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_SC2_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_SC2_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_SC2_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_SC2_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_SC2_Sub; ++ #endif ++ } ++ break; ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SC2_SUB_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_SC2_Sub; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Sub; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Sub; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_SC2_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_SC2_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_SC2_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_SC2_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_SC2_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_SC2_Sub; ++ #endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_SC2_Sub; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_SC2_Sub; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_SC2_Sub; ++#endif ++ ++ ++ MDrv_PQ_AddTable_(SC2_SUB, &PQTableInfo); ++ ++ ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_SUB); ++ } ++ ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Sub_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_SC2_Sub_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Sub_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Sub_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub_Ex; ++ } ++ break; ++ } ++ MDrv_PQ_AddTable_(SC2_SUBEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_SUBEX); ++ } ++ ++ return TRUE; ++ ++ ++#else ++ ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++ ++#endif ++#else ++ return TRUE; ++#endif ++} ++ ++ ++MS_BOOL MDrv_PQ_GetMADiFromGrule(PQ_WIN eWindow, MS_U16 *pu16TabIdx_MADi_Motion, MS_U16 *pu16TabIdx_MADi) ++{ ++#if PQ_GRULE_OSD_BW_ENABLE ++ MS_U16 u16PQ_OSDBWIdx = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ { ++ if(bw_info.u32Miu1MemSize ==0) // 1 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ } ++ #else //DDR select disable ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_On_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ #endif ++ ++ #if (PQ_GRULE_OSD_BW_IP_NUM_Main > 1) ++ *pu16TabIdx_MADi_Motion = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 1); // Add MADi_Motion ip ++ #else ++ UNUSED(pu16TabIdx_MADi_Motion); ++ #endif ++ } ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ { ++ if(bw_info.u32Miu1MemSize ==0) // 1 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ } ++ #else //DDR select disable ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, PQ_GRule_Lvl_OSD_BW_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ #endif ++ ++ #if (PQ_GRULE_OSD_BW_IP_NUM_SC1_Main > 1) ++ *pu16TabIdx_MADi_Motion = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 1); // Add MADi_Motion ip ++ #else ++ UNUSED(pu16TabIdx_MADi_Motion); ++ #endif ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ { ++ if(bw_info.u32Miu1MemSize ==0) // 1 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ } ++ #else //DDR select disable ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, PQ_GRule_Lvl_OSD_BW_On_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ #endif ++ ++ #if (PQ_GRULE_OSD_BW_IP_NUM_SC2_Main > 1) ++ *pu16TabIdx_MADi_Motion = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 1); // Add MADi_Motion ip ++ #else ++ UNUSED(pu16TabIdx_MADi_Motion); ++ #endif ++ } ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ // TODO: Should sub window need to consider the OSD BW ?? ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(pu16TabIdx_MADi_Motion); ++ UNUSED(pu16TabIdx_MADi); ++#endif ++ ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetMemFmtInGeneral(PQ_WIN eWindow, ++ MS_BOOL bMemFmt422, ++ MS_U16 *pu16TabIdx_MemFormat, ++ MS_U16 *pu16TabIdx_444To422, ++ MS_U16 *pu16TabIdx_422To444 ++ ) ++{ ++#if (PQ_ENABLE_MEMFMT) ++ if(bMemFmt422) ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC1_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_SC1_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_SC2_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ } ++ else ++ { ++ // use 444_10BIT mode only if < 1440x1080 ++ // frame buffer 1920x1080x3x2 == 1440x1080x4x2 ++ // also bandwidth not enough for 1920x1080 444_10BIT ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC1_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_SC1_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_SC2_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_SC2_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ } ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetMADiInGeneral(PQ_WIN eWindow, MS_U16 *pu16TabIdx_MADi_Motion, MS_U16 *pu16TabIdx_MADi) ++{ ++#if (PQ_ENABLE_MEMFMT) ++ UNUSED(pu16TabIdx_MADi_Motion); ++ UNUSED(pu16TabIdx_MADi); ++#if PQ_GRULE_DDR_SELECT_ENABLE ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ MS_U16 u16PQ_DDRSELIdx = 0; ++ if(bw_info.u32Miu1MemSize==0) // 1 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_Main, PQ_GRule_Lvl_DDR_SELECT_1DDR_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_Main, PQ_GRule_Lvl_DDR_SELECT_2DDR_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ } ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Sub); ++ } ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ MS_U16 u16PQ_DDRSELIdx = 0; ++ if(bw_info.u32Miu1MemSize==0) // 1 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, PQ_GRule_Lvl_DDR_SELECT_1DDR_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, PQ_GRule_Lvl_DDR_SELECT_2DDR_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ MS_U16 u16PQ_DDRSELIdx = 0; ++ if(bw_info.u32Miu1MemSize==0) // 1 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, PQ_GRule_Lvl_DDR_SELECT_1DDR_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, PQ_GRule_Lvl_DDR_SELECT_2DDR_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC2_Sub); ++ } ++#endif // ENABLE_MULTI_SCALER ++#else //DDR select disable ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Sub); ++ ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC2_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC2_Sub); ++ ++ } ++#endif ++#endif ++ //printf("$$[%s]:%d, %s, u16TabIdx_MADi=%u\r\n", __FUNCTION__, __LINE__, eWindow?"SUB":"MAIN", u16TabIdx_MADi); ++ } ++#endif ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetMADiForRFBL(PQ_WIN eWindow, MS_BOOL bFBL, MS_U16 *pu16TabIdx_MADi_Motion, MS_U16 *pu16TabIdx_MADi) ++{ ++ UNUSED(pu16TabIdx_MADi_Motion); ++ if((_stRFBL_Info.bEnable)&&(!bFBL)) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, (MS_MADI_TYPE)_stRFBL_Info.u8MADiType); ++ if(!_stMode_Info[eWindow].bInterlace) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_NO_MIU); ++ ++ MDrv_PQ_MADiForceMotionY(eWindow, FALSE); ++ MDrv_PQ_MADiForceMotionC(eWindow, FALSE); ++ //printf("[%s]-[%d] : disable Y/C motion\r\n", __FUNCTION__, __LINE__); ++ } ++ //printf("[%s]-[%d] : u16TabIdx_MADi = %d\r\n",__FUNCTION__,__LINE__,u16TabIdx_MADi); ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_Patch2Rto4RForFieldPackingMode(PQ_WIN eWindow, MS_U16 u16TabIdx_MADi) ++{ ++#if 0//Ryan ++#if PQ_GRULE_OSD_BW_ENABLE ++ // Patch: in OSD turn off case, when 2R-->4R, J2, M10 with new OPM system will flash(4R-->2R is OK) ++ // we need to set 4R first, and wait some time, and do other MAdi setting, the flash will be ok. ++ // which is only for non-OS platform patch, since OS platform won't turn off OSD for DFB system. ++ // Only FieldPackingMode need this solution ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ if((MApi_XC_IsFieldPackingModeSupported() && ++ (_stMode_Info[eWindow].u16input_hsize>=1280)&& ++ (_stMode_Info[eWindow].u16input_vsize>=720) && ++ (!_bOSD_On)) && ++ ((u16TabIdx_MADi == PQ_IP_MADi_24_4R_Main) || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_Main) || ++ (u16TabIdx_MADi == PQ_IP_MADi_26_4R_Main) || (u16TabIdx_MADi == PQ_IP_MADi_27_4R_Main) ++#if PQ_MADI_88X_MODE ++ || (u16TabIdx_MADi == PQ_IP_MADi_24_4R_880_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_880_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_884_Main) ++#endif ++ )) ++ { ++ //set to 4R first, ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_03_L, 0 , 0x0002 ); ++ //delay ++ _MDrv_PQ_wait_output_vsync(eWindow, 1, 90); ++ } ++ } ++ ++#if ENABLE_MULTI_SCALER ++ if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ if((MApi_XC_IsFieldPackingModeSupported() && ++ (_stMode_Info[eWindow].u16input_hsize>=1280)&& ++ (_stMode_Info[eWindow].u16input_vsize>=720) && ++ (!_bOSD_On)) && ++ ((u16TabIdx_MADi == PQ_IP_MADi_24_4R_SC1_Main) || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_SC1_Main) || ++ (u16TabIdx_MADi == PQ_IP_MADi_26_4R_SC1_Main) || (u16TabIdx_MADi == PQ_IP_MADi_27_4R_SC1_Main) ++#if PQ_MADI_88X_MODE ++ || (u16TabIdx_MADi == PQ_IP_MADi_24_4R_880_SC1_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_880_SC1_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_884_SC1_Main) ++#endif ++ )) ++ { ++ //set to 4R first, ++ MApi_XC_W2BYTEMSK(REG_SC1_BK12_03_L, 0 , 0x0002 ); ++ //delay ++ _MDrv_PQ_wait_output_vsync(eWindow, 1, 90); ++ } ++ } ++ ++ if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if((MApi_XC_IsFieldPackingModeSupported() && ++ (_stMode_Info[eWindow].u16input_hsize>=1280)&& ++ (_stMode_Info[eWindow].u16input_vsize>=720) && ++ (!_bOSD_On)) && ++ ((u16TabIdx_MADi == PQ_IP_MADi_24_4R_SC2_Main) || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_SC2_Main) || ++ (u16TabIdx_MADi == PQ_IP_MADi_26_4R_SC2_Main) || (u16TabIdx_MADi == PQ_IP_MADi_27_4R_SC2_Main) ++#if PQ_MADI_88X_MODE ++ || (u16TabIdx_MADi == PQ_IP_MADi_24_4R_880_SC2_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_880_SC2_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_884_SC2_Main) ++#endif ++ )) ++ { ++ //set to 4R first, ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_03_L, 0 , 0x0002 ); ++ //delay ++ _MDrv_PQ_wait_output_vsync(eWindow, 1, 90); ++ } ++ } ++#endif // ENABLE_MULTI_SCALER ++ ++#else ++ UNUSED(eWindow); ++ UNUSED(u16TabIdx_MADi); ++#endif ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetBPPInfoFromMADi(PQ_WIN eWindow, ++ MS_BOOL bMemFmt422, ++ MS_U16 u16TabIdx_MADi, ++ MS_U16 u16TabIdx_MemFormat, ++ MS_U8 *pu8BitsPerPixel, ++ PQ_DEINTERLACE_MODE *peDeInterlaceMode, ++ MS_U8 *pu8FrameCount ++ ) ++{ ++#if 0//Ryan ++ if(bMemFmt422) ++ { ++ // decide bits/pixel and deinterlace mode flag ++ if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_4R)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ ++ PQMADi_DBG(printf("24_4R PQ_DEINT_3DDI_HISTORY \r\n")); ++ } ++ else if( (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R)) || ++ (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R_880))) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("24_2R PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("25 4R PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ PQMADi_DBG(printf("25 4R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_14F_6R_MC)) //Add New MADi mode ++ { ++ *pu8BitsPerPixel = 24; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 14; ++ PQMADi_DBG(printf("25 14F 6R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_14F_8R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 14; ++ PQMADi_DBG(printf("25 14F 8R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_12F_8R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 12; ++ PQMADi_DBG(printf("25 12F 8R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_16F_8R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 16; ++ PQMADi_DBG(printf("25 16F 8R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC_NW)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_FilmPreDet)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R FilmPreDet_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_FilmPreDet_PAL)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R FilmPreDet PAL_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_6R_FilmPreDet)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("24 6R FilmPreDet_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_6R_FilmPreDet_PAL)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("24 6R FilmPreDet PAL_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_8F_4R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 8F 4R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++#if PQ_ENABLE_RFBL ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_2D)) // Need to ReDefine ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_25D)) // Need to ReDefine ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D)) // Need to ReDefine ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_YC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_FILM)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++#endif ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("25 2 PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_26_4R)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("26 4 PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_26_2R)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("26 2 PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_4R)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_3DDI; ++ PQMADi_DBG(printf("27 4 PQ_DEINT_3DDI\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_2R)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_3DDI; ++ PQMADi_DBG(printf("27 2 PQ_DEINT_3DDI\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 8 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE10)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 10 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT8)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P M 8 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P M 10 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_RFBL_FILM)) ++ { ++ *pu8BitsPerPixel = 12; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ //printf("==================================== MS_MADI_24_RFBL_FILM\r\n"); ++ //printf("24 PQ_DEINT_3DDI_HISTORY\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_RFBL_NFILM)) ++ { ++ *pu8BitsPerPixel = 12; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ //printf("==================================== MS_MADI_24_RFBL_NFILM\r\n"); ++ //printf("24 PQ_DEINT_3DDI_HISTORY\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_FBL_DNR)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_AVG; ++ //printf("==================================== MS_MADI_FBL_DNR\r\n"); ++ //printf("24 PQ_DEINT_2DDI_AVG\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_FBL_MIU)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_AVG; ++ //printf("==================================== MS_MADI_FBL_MIU\r\n"); ++ //printf("24 PQ_DEINT_2DDI_AVG\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_NO_MIU)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_AVG; ++ //printf("==================================== MS_MADI_P_MODE8_NO_MIU\r\n"); ++ //printf("24 PQ_DEINT_2DDI_AVG\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10_8Frame)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ PQMADi_DBG(printf("P M 10 8Frame PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 8; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10_4Frame)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ PQMADi_DBG(printf("P M 10 4Frame PQ_DEINT_2DDI_BOB\r\n")); ++ } ++ else if (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_3Frame)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE,MAIN_WINDOW); ++ PQMADi_DBG(printf("P M 10 3Frame PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 3; ++ } ++ else if (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_6Frame_6R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE,MAIN_WINDOW); ++ *pu8FrameCount = 6; ++ } ++ else if (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_12Frame_8R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE,MAIN_WINDOW); ++ *pu8FrameCount = 12; ++ } ++#if PQ_ENABLE_RFBL ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE10_MOT)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("RFBL P M 10 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE8_MOT)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("RFBL P M 8 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ PQMADi_DBG(printf("None\r\n")); ++ } ++ ++ } ++ else ++ { ++ //in order to disable user mode, ++ if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_444)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 8 444 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE10_444)) ++ { ++ *pu8BitsPerPixel = 30; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 10 444 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ ++ if((u16TabIdx_MemFormat == PQ_IP_MemFormat_444_10BIT_Main) ++#if PQ_ENABLE_PIP ++ ||(u16TabIdx_MemFormat == PQ_IP_MemFormat_444_10BIT_Sub) ++#endif ++ ) ++ { ++ *pu8BitsPerPixel = 32; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("PQ_IP_MemFormat_444_10BIT\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if((u16TabIdx_MemFormat == PQ_IP_MemFormat_444_8BIT_Main) ++#if PQ_ENABLE_PIP ++ ||(u16TabIdx_MemFormat == PQ_IP_MemFormat_444_8BIT_Sub) ++#endif ++ ) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("PQ_IP_MemFormat_444_8BIT\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else ++ { ++ *pu8BitsPerPixel = 24; ++ PQMADi_DBG(printf("PQ_IP_MemFormat_422MF_Main\r\n")); ++ *pu8FrameCount = 2; ++ } ++ ++ if ( MApi_XC_R2BYTE(REG_SC_BK2A_02_L) & BIT(15) ) //if on need disable. ++ { ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, PQ_IP_UC_CTL_OFF_Main, PQ_IP_UC_CTL_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++ } ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_ChangeMemConfigFor3D(PQ_WIN eWindow, ++ MS_BOOL bMemFmt422, ++ MS_U16 *pu16TabIdx_MemFormat, ++ MS_U16 *pu16TabIdx_444To422, ++ MS_U16 *pu16TabIdx_422To444, ++ MS_U8 *pu8BitsPerPixel, ++ MS_U16 *pu16TabIdx_MADi_Motion, ++ MS_U16 *pu16TabIdx_MADi ++ ) ++{ ++#if 0 //Ryan ++ UNUSED(pu16TabIdx_MADi_Motion); ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ //reduce mem size, put it into 16M, 2 frame mode. ++ if((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) ++ && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE) ++ && (_stMode_Info[eWindow].u16input_hsize == 1920) ++ && (_stMode_Info[eWindow].u16input_vsize == 2205)) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_444); ++ *pu8BitsPerPixel = 16; ++ ++ // DVI is 444 input, we need to conver it to 422, otherwise DVI will use 32 bpp instead, not 16 ++ // because 444 format combine to the setting of pu16TabIdx_MemFormat ++ if(!bMemFmt422) ++ { ++ //PQ_IP_MemFormat_Main 422 ++ *pu16TabIdx_MemFormat = PQ_IP_MemFormat_422MF_Main; ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ //PQ_IP_422To444_Main on ++ *pu16TabIdx_422To444 = PQ_IP_422To444_ON_Main; ++ PQBW_DBG(printf("3D: force 422, 444to422 and 422to444 ON\r\n");) ++ } ++ ++ printf("3D: modify progressive memory fmt for 1080p framepacking\r\n"); ++ } ++ ++ if(MApi_XC_Get_3D_HW_Version() < 2) ++ { ++ //PQ main page maybe MADi mode to 8 field mode, but it cannot do madi for line by line output. ++ //so we force it back to normal 25_2R like mode. ++ if((MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_TOP_BOTTOM) && (TRUE == _stMode_Info[eWindow].bInterlace)) ++ { ++ // we must use MS_MADI_25_4R or 2R to avoid MC madi mode for dnr offset calcuation problem. ++ if(TRUE == _stMode_Info[eWindow].bInterlace) ++ { ++ if((_stMode_Info[eWindow].u16input_vsize >= 900) && ++ (_stMode_Info[eWindow].u16input_hsize >= 1440) && ++ (bw_info.u32Miu1MemSize==0))// 1ddr case, should save bw ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R); ++ PQBW_DBG(printf("3D: force to 25_2R\r\n");) ++ } ++ else ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R); ++ PQBW_DBG(printf("3D: force to 25_4R\r\n");) ++ } ++ } ++ ++ //Madi do line by line must use 422 format ++ if(!bMemFmt422) ++ { ++ //PQ_IP_MemFormat_Main 422 ++ *pu16TabIdx_MemFormat = PQ_IP_MemFormat_422MF_Main; ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ //PQ_IP_422To444_Main on ++ *pu16TabIdx_422To444 = PQ_IP_422To444_ON_Main; ++ PQBW_DBG(printf("3D: force 422, 444to422 and 422to444 ON\r\n");) ++ } ++ ++ // we can only process 422 format for E_XC_3D_INPUT_TOP_BOTTOM. ++ // so, if it's 444 format, we have to force it to be 422 and the u8BitsPerPixel is also changed to 24. ++ *pu8BitsPerPixel = 24; ++ PQBW_DBG(printf("3D:force u8BitsPerPixel to 24\r\n");) ++ } ++ ++ //frame alterntive must use bob mode ++ if((E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_NOFRC == MApi_XC_Get_3D_Output_Mode()) || ++ (E_XC_3D_OUTPUT_FRAME_ALTERNATIVE == MApi_XC_Get_3D_Output_Mode())) ++ { ++ MDrv_PQ_EnableMADIForce(PQ_MAIN_WINDOW, TRUE); ++#if PQ_MADI_DFK ++ MDrv_PQ_LoadTable(eWindow, PQ_IP_MADi_DFK_OFF_Main, PQ_IP_MADi_DFK_Main); ++#endif ++ MDrv_PQ_LoadTable(eWindow, PQ_IP_EODi_OFF_Main, PQ_IP_EODi_Main); ++ } ++ //line by line must use weave mode ++ else if(E_XC_3D_OUTPUT_LINE_ALTERNATIVE == MApi_XC_Get_3D_Output_Mode()) ++ { ++ MDrv_PQ_EnableMADIForce(eWindow, FALSE); ++ } ++ ++ //None 3D case: by Ethan.Lee, saveing memory size for 1920x1200 ++ if ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_MODE_NONE) && ++ (MApi_XC_Get_3D_Output_Mode()== E_XC_3D_OUTPUT_MODE_NONE) ) ++ { ++ // Saving memory size for 1920x1200P HDMI 20110421EL ++ if ( (_stMode_Info[eWindow].u16input_vsize > 1100) && (QM_IsSourceHDMI_Video(_enInputSourceType[eWindow], eWindow))) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_444); ++ *pu8BitsPerPixel = 16; ++ if(!bMemFmt422) ++ { ++ //PQ_IP_MemFormat_Main 422 ++ *pu16TabIdx_MemFormat = PQ_IP_MemFormat_422MF_Main; ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ //PQ_IP_422To444_Main on ++ *pu16TabIdx_422To444 = PQ_IP_422To444_ON_Main; ++ PQBW_DBG(printf("3D: force 422, 444to422 and 422to444 ON\r\n");) ++ } ++ } ++ } ++ } ++ ++ //Frame packing interlace must use 25_2R for ++ // A. Madi for line by line output for old 3D engine. Or, ++ // B. better quality. (P mode will shaking a little) ++ if(((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_L) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_R) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_TOP_BOTTOM) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_LINE_ALTERNATIVE) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ ) ++ { ++ //framepacking interlace 1080i ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R); ++ _stMode_Info[eWindow].bInterlace = TRUE; ++ *pu8BitsPerPixel = 24; ++ ++ PQBW_DBG(printf("3D: force to 25_2R\r\n");) ++ } ++ } ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_ForceBPPForDynamicMemFmt(PQ_WIN eWindow, MS_BOOL bMemFmt422, MS_U8 *pu8BitsPerPixel) ++{ ++ //force Memory FMT and use the same pixel number to avoid the garbage when memory mode is changed. ++ if(bMemFmt422) ++ { ++ MS_U16 u16MemFMT= 0; ++ ++ if(!_stMode_Info[eWindow].bInterlace) ++ { ++ // for dynamically memory format changing, we need to keep it as 24 bits ++ if(SUPPORT_DYNAMIC_MEM_FMT)//STB could be false ++ { ++ *pu8BitsPerPixel = 24; ++ } ++ } ++ ++ if (eWindow == PQ_MAIN_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC_BK12_02_L, 0xFF); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC_BK12_42_L, 0xFF); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if (eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC1_BK12_02_L, 0xFF); ++ } ++ else if (eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC2_BK12_02_L, 0xFF); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC2_BK12_42_L, 0xFF); ++ } ++ #endif // ENABLE_MULTI_SCALER ++ ++ if((u16MemFMT == 0xBB) || (u16MemFMT == 0xAA) || (u16MemFMT == 0x99) || (u16MemFMT == 0x88)) ++ { ++ *pu8BitsPerPixel = 24; ++ } ++ else if((u16MemFMT == 0x55) || (u16MemFMT == 0x66) || (u16MemFMT == 0x44)) ++ { ++ *pu8BitsPerPixel = 20; ++ } ++ else ++ { ++ //decide by original setting ++ } ++ } ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_SetFrameNumber(PQ_WIN eWindow, MS_U16 u16TabIdx_MADi, MS_U8 u8FrameCount) ++{ ++ if(SUPPORT_SCMI_V2) ++ { ++ //Set Frame number ++ if((bSetFrameCount )&& ((_stMode_Info[eWindow].bInterlace) ++ ||(u16TabIdx_MADi == (Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_6Frame_6R))) ++ ||(u16TabIdx_MADi == (Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_12Frame_8R))))) ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_19_L, u8FrameCount , 0x001F); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_59_L, u8FrameCount , 0x001F); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC1_BK12_19_L, u8FrameCount , 0x001F); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_19_L, u8FrameCount , 0x001F); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_59_L, u8FrameCount , 0x001F); ++ } ++ #endif // ENABLE_MULTI_SCALER ++ ++ } ++ else ++ { ++ //When the frame mode from P_MODE_MC_6Frame_6R or P_MODE_MC_12Frame_8R transform to other P_MODE , set the frame config to 3 frame. ++ ++ if(eWindow == PQ_MAIN_WINDOW ++ #if PQ_ENABLE_PIP ++ || eWindow == PQ_SUB_WINDOW ++ #endif ++ ) ++ { ++ if ((MApi_XC_R2BYTEMSK(REG_SC_BK12_19_L , 0x001F ) == 0x0C)||(MApi_XC_R2BYTEMSK(REG_SC_BK12_19_L , 0x001F ) == 0x06)) ++ { ++ if (eWindow == PQ_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_19_L, 0x03 , 0x001F ); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_59_L, 0x03 , 0x001F ); ++ } ++ } ++ } ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC2_MAIN_WINDOW || eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ if ((MApi_XC_R2BYTEMSK(REG_SC2_BK12_19_L , 0x001F ) == 0x0C)||(MApi_XC_R2BYTEMSK(REG_SC2_BK12_19_L , 0x001F ) == 0x06)) ++ { ++ if (eWindow == PQ_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_19_L, 0x03 , 0x001F ); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_59_L, 0x03 , 0x001F ); ++ } ++ } ++ } ++ else ++ { ++ if ((MApi_XC_R2BYTEMSK(REG_SC1_BK12_19_L , 0x001F ) == 0x0C)||(MApi_XC_R2BYTEMSK(REG_SC1_BK12_19_L , 0x001F ) == 0x06)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC1_BK12_19_L, 0x03 , 0x001F ); ++ } ++ } ++ #endif ++ } ++ } ++ return TRUE; ++} ++ ++#if (PQ_ENABLE_PICTURE) ++static MS_BOOL _MDrv_PQ_Get_Picture_3x3_Matrix(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret; ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_3x3matrix_PIC2_Main); ++ ++ PQCOLOR_DBG(printf("3x3matrix:win%d TabIdx:%d \n",eWindow, u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Sub : ++ PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SC2_Sub : ++ PQ_IP_SRAM_3x3matrix_PIC2_SC1_Main : ++ #endif ++ PQ_IP_SRAM_3x3matrix_PIC2_Main; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_Main, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_Sub, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_SC1_Main, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_SC2_Main, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ return bret; ++} ++ ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_DLC(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_DLC_PIC1_Main); ++ ++ PQCOLOR_DBG(printf("DLC Curve:win:%d TabIdx:%d \n",eWindow, u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Sub : ++ PQ_IP_SRAM_DLC_PIC1_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_DLC_PIC1_SIZE_Main; ++ ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SC2_Sub : ++ PQ_IP_SRAM_DLC_PIC1_SC1_Main : ++ #endif ++ PQ_IP_SRAM_DLC_PIC1_Main; ++ ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_Main, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_Sub, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_SC1_Main, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_SC2_Main, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ } ++ ++ return bret; ++} ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_ColorSetting(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Main); ++ PQCOLOR_DBG(printf("ColorSetting: win:%d, TabIdx:%d \n",eWindow, u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Sub : ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Sub : ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Main; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Main, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Sub, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC1_Main, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Main, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ ++ return bret; ++} ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_Gamma_TBL(PQ_WIN eWindow, MS_U16 *pBuf, PQ_PICTURE_TYPE enPictureType) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ MS_U16 u16PQIdx, u16Tabsize; ++ ++ u16TableIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_GammaTbl_R_PIC1_Main) : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_GammaTbl_G_PIC1_Main) : ++ MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_GammaTbl_B_PIC1_Main); ++ ++ PQCOLOR_DBG(printf("Gamma: TabIdx:%d \n", u16TableIdx)); ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_Main; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_Main; ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_Sub; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_Sub; ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SC1_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SC1_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SC1_Main; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_SC1_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_SC1_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_SC1_Main; ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SC2_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SC2_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SC2_Main; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_SC2_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_SC2_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_SC2_Main; ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SC2_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SC2_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SC2_Sub; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_SC2_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_SC2_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_SC2_Sub; ++ } ++#endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ if(!bret) ++ { ++ return FALSE; ++ } ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16Tabsize); ++ ++ ++ } ++ else ++#endif ++ { ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ } ++ ++ return bret; ++} ++ ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_AutoColor(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_Auto_Color_PIC2_Main); ++ PQCOLOR_DBG(printf("AutoColor: TabIdx:%d \n", u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_BIN_STD_SC1_MAIN : ++ #endif ++ PQ_BIN_STD_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Auto_Color_PIC2_Main; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_Main, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_Sub, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_SC1_Main, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_SC2_Main, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ } ++ ++ return bret; ++} ++ ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_ColorTemp(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_Color_Temp_PIC1_Main); ++ PQCOLOR_DBG(printf("ColorTemp: TabIdx:%d \n", u16TableIdx)); ++ ++#if(ENABLE_PQ_BIN) ++ ++ ++ if(gbPQBinEnable) ++ { ++ ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_BIN_STD_SC1_MAIN : ++ #endif ++ PQ_BIN_STD_MAIN; ++ ++ MS_U16 u16TabeSize = eWindow == PQ_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Main : ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_Main : ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Color_Temp_PIC1_Main; ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_Main, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_Sub, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Sub); ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_SC1_Main, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_SC2_Main, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Sub); ++ } ++#endif ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ ++ return bret; ++} ++ ++MS_BOOL MDrv_PQ_Get_Sharpness(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info * pstPQModeInfo, MS_U8 *pu8Sharpness) ++{ ++ MS_BOOL bret = TRUE; ++ MS_U16 u16PQSrcType = 0; ++ MS_PQ_Mode_Info stModeInfo; ++ MS_U16 u16TableIdx; ++ MS_U16 u16IPIdx; ++ MS_U8 u8Peaking_Gain[1]; ++ ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ _u16PQSrcType[eWindow] = QM_AV_PAL_M_Main; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ MsOS_Memcpy(&stModeInfo, &_stMode_Info[eWindow], sizeof(MS_PQ_Mode_Info)); ++ MDrv_PQ_Set_ModeInfo(eWindow, enInputSourceType, pstPQModeInfo); ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ } ++ ++ PQCOLOR_DBG(printf("PQ_Get_Sharpness: win:%d SRC:%d \n", eWindow, _u16PQSrcType[eWindow])); ++ ++ u16IPIdx = PQ_IP_VIP_Peaking_gain_Main; ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TableIdx == PQ_BIN_IP_NULL)) ++ || ((gbPQBinEnable == 0) && (u16TableIdx == PQ_IP_NULL))) ++#else ++ if(u16TableIdx == PQ_IP_NULL) ++#endif ++ { ++ *pu8Sharpness = 0xFF; ++ bret = FALSE; ++ } ++ else ++ { ++ MDrv_PQ_LoadTableData(eWindow, u16TableIdx, u16IPIdx, u8Peaking_Gain, 1); ++ *pu8Sharpness = u8Peaking_Gain[0]; ++ ++ } ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ MsOS_Memcpy(&_stMode_Info[eWindow], &stModeInfo, sizeof(MS_PQ_Mode_Info)); ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ ++ return bret; ++} ++ ++ ++MS_BOOL MDrv_PQ_Get_Picture(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info * pstPQModeInfo, PQ_PICTURE_TYPE enType, void *pBuf) ++{ ++ MS_BOOL bret = FALSE; ++ MS_U16 u16PQSrcType = PQ_INPUT_SOURCE_NONE; ++ MS_PQ_Mode_Info stModeInfo; ++ ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ _u16PQSrcType[eWindow] = QM_AV_PAL_M_Main; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ MsOS_Memcpy(&stModeInfo, &_stMode_Info[eWindow], sizeof(MS_PQ_Mode_Info)); ++ MDrv_PQ_Set_ModeInfo(eWindow, enInputSourceType, pstPQModeInfo); ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ } ++ ++ ++ PQCOLOR_DBG(printf("PQ_Get_Picture: Type:%d SRC:%d \n", enType, _u16PQSrcType[eWindow])); ++ ++ switch(enType) ++ { ++ case E_PQ_PICTURE_3x3_MATRIX: ++ bret = _MDrv_PQ_Get_Picture_3x3_Matrix(eWindow, pBuf); ++ break; ++ ++ case E_PQ_PICTURE_DLC_CURVE: ++ bret = _MDrv_PQ_Get_Picture_DLC(eWindow, pBuf); ++ break; ++ ++ case E_PQ_PICTURE_COLOR_SETTING: ++ bret = _MDrv_PQ_Get_Picture_ColorSetting(eWindow, pBuf); ++ break; ++ ++ case E_PQ_PICTURE_GAMMA_TBL_R: ++ case E_PQ_PICTURE_GAMMA_TBL_G: ++ case E_PQ_PICTURE_GAMMA_TBL_B: ++ bret = _MDrv_PQ_Get_Picture_Gamma_TBL(eWindow, pBuf, enType); ++ break; ++ ++ case E_PQ_PICTURE_AUTO_COLOR: ++ bret = _MDrv_PQ_Get_Picture_AutoColor(eWindow, pBuf); ++ break; ++ ++ ++ case E_PQ_PICTURE_COLOR_TEMP: ++ bret = _MDrv_PQ_Get_Picture_ColorTemp(eWindow, pBuf); ++ break; ++ } ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ MsOS_Memcpy(&_stMode_Info[eWindow], &stModeInfo, sizeof(MS_PQ_Mode_Info)); ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ ++ return bret; ++} ++#endif ++ ++#endif // PQ_ENABLE_UNUSED_FUNC +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ_Bin.c b/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ_Bin.c +new file mode 100644 +index 00000000..8e9182a3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ_Bin.c +@@ -0,0 +1,1764 @@ ++// $Change: 661747 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#define _DRV_PQ_BIN_C ++ ++ ++#ifdef MSOS_TYPE_LINUX ++#include ++#endif ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++ ++#include "MsCommon.h" ++#include "MsOS.h" ++#include "MsTypes.h" ++#include "hwreg_utility2.h" ++#include "color_reg.h" ++ ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ_Bin.h" ++#include "drvPQ_Datatypes.h" ++#include "drvPQ.h" ++ ++#include "mhal_pq.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#if(ENABLE_PQ_BIN) ++ ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++#define PQ_BIN_DBG_HEADER_DATA 0 ++#define PQ_BIN_DBG(x) //(x) ++#define PQ_BIN_DBG_HEADER(x) //(x) ++#define PQ_BIN_DUMP_DBG(x) //(x) ++#define PQ_BIN_DUMP_FILTER_DBG(x) //(x) ++#define PQ_BIN_XRULE_DBG(x) //(x) ++#define PQ_BIN_GRULE_DBG(x) //(x) ++#define PQ_TEXT_BIN_DBG_HEADER(x) //(x) ++#define PQ_TEXT_BIN_DBG(x) //(x) ++#define PQ_BIN_DBG_SRAMERROR(x) //(x) ++#define PQ_BIN_PICTURE(x) //(x) ++ ++#if (PQ_BIN_ENABLE_CHECK == 0) ++#define PQ_REG_FUNC( u32Reg, u8Value, u8Mask ) MApi_XC_WriteByteMask( u32Reg, u8Value, u8Mask ) ++#define PQ_REG_MLOAD_FUNC(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg-1, ((MS_U16)u8Value)<<8, ((MS_U16)u8Mask)<<8); \ ++ } \ ++ else \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg, u8Value, u8Mask); \ ++ } \ ++ }while(0) ++ ++#define PQ_REG_MLOAD_WRITE_CMD(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg-1; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask)<<8; \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value)<<8; \ ++ } \ ++ else \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask); \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value); \ ++ } \ ++ _u16MLoadCmdCnt++; \ ++ }while(0) ++ ++#else // #if(PQ_ENABLE_CHECK == 1) ++static MS_U8 _u8PQBinfunction = PQ_FUNC_DUMP_REG; ++static void _MDrv_PQBin_SetFunction(MS_U8 u8Func) ++{ ++ _u8PQBinfunction = u8Func; ++} ++ ++#define PQ_REG_FUNC( u16Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if (_u8PQBinfunction == PQ_FUNC_DUMP_REG) \ ++ { \ ++ MApi_XC_WriteByteMask( (MS_U32)u16Reg, u8Value, u8Mask ); \ ++ } \ ++ else \ ++ { \ ++ if ((MApi_XC_ReadByte((MS_U32)u16Reg) & u8Mask) != (u8Value & u8Mask)) \ ++ { \ ++ printf("[PQRegErr] "); \ ++ if ((u16Reg >> 8) == 0x2F) \ ++ { \ ++ printf("bk=%02x, ", (MS_U16)SC_BK_CURRENT); \ } \ ++ else if ((u16Reg >> 8) == 0x36) \ ++ { \ ++ printf("bk=%02x, ", (MS_U16)COMB_BK_CURRENT); \ } \ ++ printf("addr=%04x, mask=%02x, val=%02x[%02x]\n", \ u16Reg, (MS_U16)u8Mask, (MS_U16)MApi_XC_ReadByte((MS_U32)u16Reg), (MS_U16)u8Value); \ ++ } \ } \ ++ }while(0) ++#endif //#if (PQ_ENABLE_CHECK) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++static MS_U16 _u16PQTabIdx[PQ_MAX_WINDOW][PQ_BIN_MAX_PNL][PQ_BIN_MAX_IP]; // store all TabIdx of all IPs ++static MS_U8 _gPQBinDisplayType[PQ_MAX_WINDOW]; ++static MS_U8 _gPQBinPnlIdx[PQ_MAX_WINDOW]; ++static MS_BOOL _bMLoadEn = FALSE; ++#define MLOAD_MAX_CMD 30 ++static MS_U32 _u32MLoadCmd[MLOAD_MAX_CMD]; ++static MS_U16 _u16MLoadMsk[MLOAD_MAX_CMD]; ++static MS_U16 _u16MLoadVal[MLOAD_MAX_CMD]; ++static MS_U16 _u16MLoadCmdCnt = 0; ++ ++static MS_U16 u16ICC_CRD_Table[PQ_MAX_WINDOW]; ++static MS_U16 u16IHC_CRD_Table[PQ_MAX_WINDOW]; ++ ++static MS_U16 u16SRAM1Table[PQ_MAX_WINDOW]; ++static MS_U16 u16SRAM2Table[PQ_MAX_WINDOW]; ++static MS_U16 u16SRAM3Table[PQ_MAX_WINDOW]; ++static MS_U16 u16SRAM4Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM1Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM2Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM3Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM4Table[PQ_MAX_WINDOW]; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void MDrv_PQBin_Clear_SRAM_Table_Index(void) ++{ ++ MS_U8 i; ++ ++ for(i=0;iu16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DUMP_DBG(printf("[PQBin]IP_Info error: General Reg Table\n")); ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset; ++ for(i=0; i< pTabInfo->u16RegNum; i++) ++ { ++ u32Offset = ( PQ_BIN_BANK_SIZE + PQ_BIN_ADDR_SIZE + PQ_BIN_MASK_SIZE + (MS_U32)pTabInfo->u16GroupNum) * (MS_U32)i; ++ u8Bank = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Addr = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Mask = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset += pTabInfo->u16GroupIdx; ++ u8Value = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ PQ_BIN_DBG_SRAMERROR(printf("4 [read addr=%lx], GroupIdx=%x,RegNum=%x,reg=%04x, msk=%02x, val=%02x, u8CurBank=%x\n", ++ (u32Addr+u32Offset-(MS_U32)pTabInfo->u16GroupIdx),pTabInfo->u16GroupIdx,pTabInfo->u16RegNum,NON_PM_BASE | (((MS_U16)u8Bank) << 8) | (MS_U16)u8Addr, u8Mask, u8Value, u8Bank);) ++ ++ u32RegAddr = NON_PM_BASE | (((MS_U16)u8Bank) << 8) | (MS_U16)u8Addr; ++ ++ PQ_BIN_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\n", u32RegAddr, u8Mask, u8Value)); ++ ++ PQ_REG_FUNC(u32RegAddr, u8Value, u8Mask); ++ } ++} ++ ++void MDrv_PQBin_DumpCombRegTable(const MS_PQBin_IP_Table_Info* const pTabInfo) ++{ ++ MS_U16 i; ++ MS_U8 u8Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ MS_U32 u32Addr, u32Offset, u32RegAddr; ++ ++ COMB_BK_STORE; ++ ++ PQ_BIN_DUMP_DBG(printf("tab: comb\n")); ++ ++ if(pTabInfo->u16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DUMP_DBG(printf("[PQBin]IP_Info error: Comb Reg Table\n")); ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset; ++ for(i=0; i< pTabInfo->u16RegNum; i++) ++ { ++ u32Offset = ( PQ_BIN_BANK_SIZE + PQ_BIN_ADDR_SIZE + PQ_BIN_MASK_SIZE + (MS_U32)pTabInfo->u16GroupNum) * (MS_U32)i; ++ u8CurBank = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Addr = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Mask = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset += pTabInfo->u16GroupIdx; ++ u8Value = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ PQ_BIN_DBG_SRAMERROR(printf("2 [read addr=%lx], GroupIdx=%x,RegNum=%x,reg=%04lx, msk=%02x, val=%02x, u8CurBank=%x\n", ++ (u32Addr+u32Offset-(MS_U32)pTabInfo->u16GroupIdx),pTabInfo->u16GroupIdx,pTabInfo->u16RegNum,COMB_REG_BASE | (MS_U32)u8Addr, u8Mask, u8Value, u8CurBank);) ++ ++ if (u8CurBank != COMB_BK_CURRENT) ++ { ++ PQ_BIN_DUMP_DBG(printf("<>\n", u8CurBank)); ++ COMB_BK_SWITCH(u8CurBank); ++ } ++ ++ u32RegAddr = COMB_REG_BASE | (MS_U16)u8Addr; ++ ++ PQ_BIN_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\n", u32RegAddr, u8Mask, u8Value)); ++ PQ_REG_FUNC(u32RegAddr, u8Value, u8Mask); ++ ++ } ++ COMB_BK_RESTORE; ++} ++ ++ ++void MDrv_PQBin_DumpScalerRegTable(const MS_PQBin_IP_Table_Info* const pTabInfo) ++{ ++ MS_U32 u32RegAddr; ++ MS_U8 u8Mask; ++ MS_U8 u8Addr; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ MS_U32 u32Addr, u32Offset; ++ MS_U16 i; ++ ++#ifdef MSOS_TYPE_LINUX ++#if(ENABLE_PQ_MLOAD) ++ pthread_mutex_lock(&_PQ_MLoad_Mutex); ++#endif ++#endif ++ //consider dump reg amount is very large, so we shouldn't use MApi_XC_W2BYTE(), ++ // because mutex cost much time. ++ SC_BK_STORE_MUTEX; ++ ++ PQ_BIN_DUMP_DBG(printf("tab: sc\n")); ++ if(pTabInfo->u16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: Scaler Reg Table\n")); ++ ++ SC_BK_RESTORE_MUTEX; ++ ++#ifdef MSOS_TYPE_LINUX ++#if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++#endif ++#endif ++ ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset; ++ for(i=0; iu16RegNum; i++) ++ { ++ u32Offset = ( PQ_BIN_BANK_SIZE + PQ_BIN_ADDR_SIZE + PQ_BIN_MASK_SIZE + (MS_U32)pTabInfo->u16GroupNum) * (MS_U32)i; ++ u8CurBank = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Addr = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Mask = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset += (MS_U32)pTabInfo->u16GroupIdx; ++ u8Value = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ PQ_BIN_DBG_SRAMERROR(printf("1 [read addr=%lx], GroupIdx=%x,RegNum=%x,reg=%04lx, msk=%02x, val=%02x, u8CurBank=%x\n", ++ (u32Addr+u32Offset-(MS_U32)pTabInfo->u16GroupIdx),pTabInfo->u16GroupIdx,pTabInfo->u16RegNum,BK_SCALER_BASE | (MS_U32)u8Addr, u8Mask, u8Value, u8CurBank);) ++ ++ if(_bMLoadEn) ++ { ++ u32RegAddr = (((MS_U32)u8CurBank) << 8) | (MS_U32)u8Addr; ++ //PQ_REG_MLOAD_FUNC(u32RegAddr, u8Value, u8Mask); ++ PQ_REG_MLOAD_WRITE_CMD(u32RegAddr, u8Value, u8Mask); ++ } ++ else ++ { ++#if (SCALER_REGISTER_SPREAD) ++ u32RegAddr = BK_SCALER_BASE | (((MS_U32)u8CurBank) << 8) | (MS_U32)u8Addr; ++#else ++ if (u8CurBank != SC_BK_CURRENT) ++ { ++ PQ_BIN_DUMP_DBG(printf("<>\n", u8CurBank)); ++ SC_BK_SWITCH(u8CurBank); ++ } ++ ++ u32RegAddr = BK_SCALER_BASE | (MS_U32)u8Addr; ++#endif ++ PQ_REG_FUNC(u32RegAddr, u8Value, u8Mask); ++ } ++ PQ_BIN_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\n", u32RegAddr, u8Mask, u8Value)); ++ ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++ ++#ifdef MSOS_TYPE_LINUX ++#if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++#endif ++#endif ++} ++ ++void MDrv_PQBin_DumpFilterTable(MS_PQBin_IP_Table_Info *pTabInfo) ++{ ++ MS_U32 u32Addr; ++ PQ_BIN_DBG(printf("tab: sram\n")); ++ ++ if(pTabInfo->u16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]IP_Info error: SRAM Table\n")); ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset + pTabInfo->u16GroupIdx * pTabInfo->u16RegNum; ++ ++ PQ_BIN_DUMP_FILTER_DBG(printf("PQ Filter Table: Win:%d, Type:%d \n", pTabInfo->ePQWin, pTabInfo->u16TableType)); ++ switch(pTabInfo->u16TableType) ++ { ++ case PQ_TABTYPE_SRAM1: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM1, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM2: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM2, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM3: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM3, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM4: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM4, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM1: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM1, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM2: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM2, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM3: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM3, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM4: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM4, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM_COLOR_INDEX: ++ Hal_PQ_set_sram_color_index_table(pTabInfo->ePQWin, SC_FILTER_SRAM_COLOR_INDEX, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_SNR: ++ Hal_PQ_set_sram_color_gain_snr_table(pTabInfo->ePQWin, SC_FILTER_SRAM_COLOR_GAIN_SNR, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_DNR: ++ Hal_PQ_set_sram_color_gain_dnr_table(pTabInfo->ePQWin, SC_FILTER_SRAM_COLOR_GAIN_DNR, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_VIP_ICC_CRD_SRAM: ++ Hal_PQ_set_sram_icc_crd_table(pTabInfo->ePQWin, SC_FILTER_SRAM_ICC_CRD, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ Hal_PQ_set_sram_ihc_crd_table(pTabInfo->ePQWin, SC_FILTER_SRAM_IHC_CRD, (void *)u32Addr); ++ break; ++ ++ default: ++ printf("[PQBin] Unknown sram type %u\n", pTabInfo->u16TableType); ++ MS_ASSERT(0); ++ break; ++ } ++} ++ ++void MDrv_PQBin_DumpTable(MS_PQBin_IP_Table_Info* pTabInfo) ++{ ++ // to save loading SRAM table time, SRAM are only downloaded ++ // when current SRAM table is different to previous SRAM table ++ ++ if ((pTabInfo->u16RegNum == 0) || (pTabInfo->u32TabOffset == PQ_BIN_ADDR_NULL)) ++ { ++ PQ_BIN_DUMP_DBG(printf("NULL Table\n")); ++ return; ++ } ++ ++ switch(pTabInfo->u16TableType) ++ { ++ case PQ_TABTYPE_SCALER: ++ MDrv_PQBin_DumpScalerRegTable(pTabInfo); ++ break; ++ case PQ_TABTYPE_COMB: ++ MDrv_PQBin_DumpCombRegTable(pTabInfo); ++ break; ++ case PQ_TABTYPE_GENERAL: ++ MDrv_PQBin_DumpGeneralRegTable(pTabInfo); ++ break; ++ case PQ_TABTYPE_SRAM1: ++ if (u16SRAM1Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram1: %u, new sram1: %u\n", ++ u16SRAM1Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM1Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram1: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM2: ++ if (u16SRAM2Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram2: %u, new sram2: %u\n", ++ u16SRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM2Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram2: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM3: ++ if (u16SRAM3Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram3: %u, new sram3: %u\n", ++ u16SRAM3Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM3Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram3: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM4: ++ if (u16SRAM4Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram4: %u, new sram4: %u\n", ++ u16SRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM4Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram4: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_C_SRAM1: ++ if (u16CSRAM1Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram1: %u, new Csram1: %u\n", ++ u16CSRAM1Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM1Table [pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram1: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM2: ++ if (u16CSRAM2Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old Csram2: %u, new Csram2: %u\n", ++ u16CSRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM2Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram2: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM3: ++ if (u16SRAM3Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old Csram3: %u, new Csram3: %u\n", ++ u16CSRAM3Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM3Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram3: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM4: ++ if (u16CSRAM4Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram4: %u, new Csram4: %u\n", ++ u16CSRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM4Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram4: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ if(u16IHC_CRD_Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old IHC_CRD_SRAM: %u, new IHC_CRD_SRAM: %u\n", ++ u16IHC_CRD_Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16IHC_CRD_Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ break; ++ ++ default: ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]DumpTable:unknown type: %u\n", pTabInfo->u16TableType)); ++ break; ++ } ++} ++ ++ ++// return total IP count ++MS_U16 MDrv_PQBin_GetIPNum(MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ PQ_BIN_DBG(printf("[PQBin]:IPNum=%u\n", pPQBinHeader->u16IP_Comm_Num)); ++ return pPQBinHeader->u16IP_Comm_Num; ++} ++ ++// return total table count of given IP ++MS_U16 MDrv_PQBin_GetTableNum(MS_U16 u16PQIPIdx, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U16 u16TabNum; ++ ++ u32Addr = pPQBinHeader->u32BinStartAddress + pPQBinHeader->u32IP_Comm_Offset; ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IP_GROUP_NUM_OFFSET; ++ u16TabNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ PQ_BIN_DBG(printf("[PQBin]TabNum=%u\n", u16TabNum)); ++ return u16TabNum; ++} ++ ++// return current used table index of given IP ++MS_U16 MDrv_PQBin_GetCurrentTableIndex(MS_U16 u16PnlIdx, MS_U16 u16PQIPIdx, MS_U8 u8BinID) ++{ ++ PQ_WIN ePQWin = MDrv_PQBin_TransToPQWin(u8BinID); ++ //printf("[PQBin]CurrTableIdx=%d\n", _u16PQTabIdx[u16PnlIdx][u16PQIPIdx]); ++ ++ return _u16PQTabIdx[ePQWin][u16PnlIdx][u16PQIPIdx]; ++} ++ ++ ++MS_U16 MDrv_PQBin_GetTableIndex(MS_U16 u16PQSrcType, MS_U16 u16PQIPIdx, MS_U16 u16PQPnlIdx, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U32 u32SourceLUT_Addr; ++ MS_U32 u32SourceLUT_Offset; ++ MS_U16 u16SourceLUT_SourceNum; ++ MS_U16 u16SourceLUT_IPNum; ++ MS_U32 u32SourceLUT_Data_Pitch; ++ MS_U16 u16TableIdx; ++ ++ if(u16PQPnlIdx >= pPQBinHeader->u16SourceLUT_PnlNum) ++ { ++ (printf("[PQBin]invalid panel type\n")); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ ++ u32Addr = pPQBinHeader->u32BinStartAddress + pPQBinHeader->u32SourceLUT_Offset; ++ u32Offset = pPQBinHeader->u32SourceLUT_Pitch * u16PQPnlIdx + PQ_BIN_SOURCELUT_SOURCE_NUM_OFFSET; ++ u16SourceLUT_SourceNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ if (u16PQSrcType >= u16SourceLUT_SourceNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]invalid input type\n")); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Offset = pPQBinHeader->u32SourceLUT_Pitch * u16PQPnlIdx + PQ_BIN_SOURCELUT_IP_NUM_OFFSET; ++ u16SourceLUT_IPNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ if (u16PQIPIdx >= u16SourceLUT_IPNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]invalid ip type\n")); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ ++ u32Offset = pPQBinHeader->u32SourceLUT_Pitch * u16PQPnlIdx + PQ_BIN_SOURCELUT_OFFSET_OFFSET; ++ u32SourceLUT_Addr = MDrv_PQBin_Get4ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32SourceLUT_Addr += pPQBinHeader->u32BinStartAddress + PQ_BIN_HEADER_LEN; ++ u32SourceLUT_Data_Pitch = (MS_U32)u16SourceLUT_IPNum * 2; ++ u32SourceLUT_Offset = u32SourceLUT_Data_Pitch * (MS_U32)u16PQSrcType + ++ (MS_U32)u16PQIPIdx * 2; ++ ++ u16TableIdx = MDrv_PQBin_Get2ByteData((void *)(u32SourceLUT_Addr+u32SourceLUT_Offset), ++ &u32SourceLUT_Offset); ++ PQ_BIN_DBG(printf("[PQBin]TableId=%u\n",u16TableIdx)); ++ return u16TableIdx; ++} ++ ++void MDrv_PQBin_GetTable(MS_U16 u16PnlIdx, MS_U16 u16TabIdx, MS_U16 u16PQIPIdx, MS_PQBin_IP_Table_Info *pTableInfo, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ PQ_WIN ePQWin = MDrv_PQBin_TransToPQWin(pPQBinHeader->u8BinID); ++ if((u16PnlIdx >= PQ_BIN_MAX_PNL) || (u16PQIPIdx >= PQ_BIN_MAX_IP)) ++ { ++ printf("[PQBin]:Out Of Range!! PnlIdx=%u, IPIdx=%u\n", u16PnlIdx, u16PQIPIdx); ++ MS_ASSERT(0); ++ return; ++ } ++ _u16PQTabIdx[ePQWin][u16PnlIdx][u16PQIPIdx] = u16TabIdx; ++ ++ if (u16TabIdx != PQ_BIN_IP_NULL) ++ { ++ u32Addr = pPQBinHeader->u32IP_Comm_Offset + ++ pPQBinHeader->u32BinStartAddress; ++ ++ if(u16TabIdx == PQ_BIN_IP_COMM) ++ { ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_TABLE_TYPE_OFFSET; ++ pTableInfo->u16TableType = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_COMM_REG_NUM_OFFSET; ++ pTableInfo->u16RegNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_COMMOFFSET_OFFSET; ++ pTableInfo->u32TabOffset = MDrv_PQBin_Get4ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ pTableInfo->u32TabOffset += (pPQBinHeader->u32BinStartAddress + PQ_BIN_HEADER_LEN); ++ ++ pTableInfo->u16GroupNum = 1; ++ pTableInfo->u16GroupIdx = 0; ++ } ++ else ++ { ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_TABLE_TYPE_OFFSET; ++ pTableInfo->u16TableType = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IP_REG_NUM_OFFSET; ++ pTableInfo->u16RegNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IP_GROUP_NUM_OFFSET; ++ pTableInfo->u16GroupNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IPOFFSET_OFFSET; ++ pTableInfo->u32TabOffset = MDrv_PQBin_Get4ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ pTableInfo->u32TabOffset += (pPQBinHeader->u32BinStartAddress + PQ_BIN_HEADER_LEN); ++ ++ pTableInfo->u16GroupIdx = u16TabIdx; ++ } ++ } ++ else ++ { ++ pTableInfo->u16GroupIdx = 0; ++ pTableInfo->u32TabOffset = PQ_BIN_ADDR_NULL; ++ pTableInfo->u16RegNum = 0; ++ pTableInfo->u16TableType = 0; ++ pTableInfo->u16GroupNum = 0; ++ } ++ ++ pTableInfo->ePQWin = MDrv_PQBin_TransToPQWin(pPQBinHeader->u8BinID); ++ ++ PQ_BIN_DBG(printf("[PQBin]: GetTable: Offset=%lx, RegNum=%u, GroupIdx=%u, GroupNum=%u, Type=%u eWin=%d\n", ++ pTableInfo->u32TabOffset, ++ pTableInfo->u16RegNum, ++ pTableInfo->u16GroupIdx, ++ pTableInfo->u16GroupNum, ++ pTableInfo->u16TableType, ++ pTableInfo->ePQWin)); ++} ++ ++MS_BOOL MDrv_PQBin_LoadPictureSetting( ++ MS_U16 u16PnlIdx, ++ MS_U16 u16TabIdx, ++ MS_U16 u16PQIPIdx, ++ MS_PQBin_Header_Info *pPQBinHeader, ++ void *pTable, ++ MS_U16 u16TableSize) ++{ ++ MS_PQBin_IP_Table_Info stTableInfo; ++ MS_U32 u32Addr = 0; ++ ++ MsOS_Memset(&stTableInfo, 0, sizeof(MS_PQBin_IP_Table_Info)); ++ ++ MDrv_PQBin_GetTable(u16PnlIdx, ++ u16TabIdx, ++ u16PQIPIdx, ++ &stTableInfo, ++ pPQBinHeader); ++ ++ PQ_BIN_PICTURE(printf("PQ_Bin: Picture: pnlidx:%d, TabIdx:%d, ipidx:%d \r\n", u16PnlIdx, u16TabIdx, u16PQIPIdx)); ++ PQ_BIN_PICTURE(printf("PQ_Bin: Picture: RegNum:%d, TabType:%d, GroupIdx:%d \r\n", stTableInfo.u16RegNum, stTableInfo.u16TableType, stTableInfo.u16GroupIdx)); ++ if(stTableInfo.u16GroupIdx >= stTableInfo.u16GroupNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data\n")); ++ return FALSE; ++ } ++ ++ if(u16TableSize > stTableInfo.u16RegNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data is too big\n")); ++ return FALSE; ++ } ++ ++ if(stTableInfo.u16TableType == PQ_TABTYPE_PICTURE_1) ++ { ++ u32Addr = stTableInfo.u32TabOffset + stTableInfo.u16RegNum * stTableInfo.u16GroupIdx * sizeof(MS_U8); ++ MsOS_Memcpy((MS_U8 *)pTable, (MS_U8 *)u32Addr, sizeof(MS_U8)*stTableInfo.u16RegNum); ++ } ++ else if(stTableInfo.u16TableType == PQ_TABTYPE_PICTURE_2) ++ { ++ u32Addr = stTableInfo.u32TabOffset + stTableInfo.u16RegNum * stTableInfo.u16GroupIdx * sizeof(MS_U16); ++ MsOS_Memcpy((MS_U16 *)pTable, (MS_U16 *)u32Addr, sizeof(MS_U16)*stTableInfo.u16RegNum); ++ } ++ else ++ { ++ return FALSE; ++ } ++ ++ ++#if 0 ++{ ++ MS_U32 u32Offset = 0; ++ for(u32Offset=0; u32Offset= stTableInfo.u16GroupNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data\n")); ++ return; ++ } ++ ++ if(u16TableSize > stTableInfo.u16RegNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data is too big\n")); ++ return; ++ } ++ u32Addr = stTableInfo.u32TabOffset; ++ for(i=0; iu16IP_Comm_Num; i++) ++ { ++ PQ_BIN_DBG_SRAMERROR(printf("--------MDrv_PQBin_LoadCommTable: u16TabIdx=%u, u16PQIPIdx=%u\n", PQ_BIN_IP_COMM, i);) ++ MDrv_PQBin_GetTable(u16PnlIdx, ++ PQ_BIN_IP_COMM, ++ i, ++ &stTableInfo, ++ pPQBinHeader); ++ ++ if(((stTableInfo.u16TableType >= PQ_TABTYPE_SRAM1) && (stTableInfo.u16TableType <= PQ_TABTYPE_C_SRAM1)) || ++ (stTableInfo.u16TableType == PQ_TABTYPE_VIP_IHC_CRD_SRAM) || ++ (stTableInfo.u16TableType == PQ_TABTYPE_VIP_ICC_CRD_SRAM) ++ ) ++ { ++ continue; ++ } ++ ++ MDrv_PQBin_DumpTable(&stTableInfo); ++ } ++} ++ ++ ++ ++void MDrv_PQBin_Parsing(MS_PQBin_Header_Info *pPQBinHeader) ++{ ++ MS_U32 u32PQBin_Addr; ++ MS_U32 u32Offset; ++#if PQ_BIN_DBG_HEADER_DATA ++ MS_U32 u32tmpoffset; ++#endif ++ MS_U8 i; ++ ++ { // for printf ++ pPQBinHeader->u8Header[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8Version[PQ_BIN_VERSION_LEN] = '\0'; ++ pPQBinHeader->u8Dummy[PQ_BIN_DUMMY] = '\0'; ++ pPQBinHeader->u8GRuleHader[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8XRuleHader[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8SkipRuleHader[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8IP_Comm_Header[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8SourceLUT_Header[PQ_BIN_HEADER_LEN] = '\0'; ++ } ++ ++ ++ u32Offset = 0; ++ u32PQBin_Addr = pPQBinHeader->u32BinStartAddress; ++ //printf("\n BinStartaDDR ID%u=%lx \n", pPQBinHeader->u8BinID, u32PQBin_Addr); ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8Version[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQBinHeader->u32StartOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQBinHeader->u32EndOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ for(i=0; i< PQ_BIN_DUMMY; i++) ++ { ++ pPQBinHeader->u8Dummy[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u8PQID = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("Header :%s \n", pPQBinHeader->u8Header)); ++ PQ_BIN_DBG_HEADER(printf("Version:%s \n", pPQBinHeader->u8Version)); ++ PQ_BIN_DBG_HEADER(printf("startADDR=%lx, EndAddr=%lx \n", pPQBinHeader->u32StartOffset, pPQBinHeader->u32EndOffset)); ++ PQ_BIN_DBG_HEADER(printf("Dummy :%s \n", pPQBinHeader->u8Dummy)); ++ PQ_BIN_DBG_HEADER(printf("PQID :%d \n", pPQBinHeader->u8PQID)); ++ //------------------------------------------------------------------------------------------- ++ // GRule ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8GRuleHader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16GRule_RuleNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQBinHeader->u16GRule_PnlNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ ++ PQ_BIN_DBG_HEADER(printf("GRuleHeader:%s\n", pPQBinHeader->u8GRuleHader)); ++ PQ_BIN_DBG_HEADER(printf("GRule: RuleNum=%u, PnlNum=%u \n", pPQBinHeader->u16GRule_RuleNum, pPQBinHeader->u16GRule_PnlNum)); ++ ++ pPQBinHeader->u32GRule_Offset = u32Offset; ++ pPQBinHeader->u32GRule_Pitch = PQ_BIN_GRULE_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32GRule_Pitch * (MS_U32)pPQBinHeader->u16GRule_RuleNum; ++ ++ ++ pPQBinHeader->u32GRule_Lvl_Offset = u32Offset; ++ pPQBinHeader->u32GRule_Lvl_Pitch = PQ_BIN_GRULE_LEVEL_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32GRule_Lvl_Pitch * (MS_U32)pPQBinHeader->u16GRule_RuleNum * (MS_U32)pPQBinHeader->u16GRule_PnlNum; ++ ++ PQ_BIN_DBG_HEADER(printf("GRule Rule : offset=%lx, pitch=%lu \n", pPQBinHeader->u32GRule_Offset, pPQBinHeader->u32GRule_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("GRule Level: offset=%lx, pitch=%lu \n", pPQBinHeader->u32GRule_Lvl_Offset, pPQBinHeader->u32GRule_Lvl_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("XRule Start:%lx\n", u32Offset)); ++ ++ //------------------------------------------------------------------------------------------- ++ // XRule ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8XRuleHader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQBinHeader->u16XRuleNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("XRuleHeader:%s\n", pPQBinHeader->u8XRuleHader)); ++ PQ_BIN_DBG_HEADER(printf("XRule: RuleNum=%u\n", pPQBinHeader->u16XRuleNum)); ++ ++ pPQBinHeader->u32XRule_Offset = u32Offset; ++ pPQBinHeader->u32XRUle_Pitch = PQ_BIN_XRULE_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32XRUle_Pitch * (MS_U32)pPQBinHeader->u16XRuleNum; ++ ++ PQ_BIN_DBG_HEADER(printf("XRule: offset=%lx, pitch=%lu\n",pPQBinHeader->u32XRule_Offset, pPQBinHeader->u32XRUle_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("SkipRule Start:%lx\n", u32Offset)); ++ ++ //------------------------------------------------------------------------------------------- ++ // SkipRule ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8SkipRuleHader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16SkipRule_IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQBinHeader->u32SkipRule_Offset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("SkipRuleHeader:%s IpNum=%u, Offset=%lx\n", pPQBinHeader->u8SkipRuleHader, pPQBinHeader->u16SkipRule_IPNum, pPQBinHeader->u32SkipRule_Offset)); ++ PQ_BIN_DBG_HEADER(printf("IP_Comm Start:%lx\n", u32Offset)); ++ ++ //------------------------------------------------------------------------------------------- ++ // IP & Common ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8IP_Comm_Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16IP_Comm_Num = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("IP_CommHeader:%s\n", pPQBinHeader->u8IP_Comm_Header)); ++ PQ_BIN_DBG_HEADER(printf("IP_Comm, Num=%u\n", pPQBinHeader->u16IP_Comm_Num)); ++ ++ pPQBinHeader->u32IP_Comm_Offset = u32Offset; ++ pPQBinHeader->u32IP_Comm_Pitch = PQ_BIN_IP_COMM_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)pPQBinHeader->u16IP_Comm_Num; ++ ++ PQ_BIN_DBG_HEADER(printf("IP_Comm, Offset=%lx, pitch=%lu\n", pPQBinHeader->u32IP_Comm_Offset, pPQBinHeader->u32IP_Comm_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("SourceLUT Start:%lx\n", u32Offset)); ++ //------------------------------------------------------------------------------------------- ++ // SourceLUT ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8SourceLUT_Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16SourceLUT_PnlNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("SourceLUTHeader:%s\n", pPQBinHeader->u8SourceLUT_Header)); ++ PQ_BIN_DBG_HEADER(printf("SourceLUT, PnlNum=%u\n", pPQBinHeader->u16SourceLUT_PnlNum)); ++ ++ pPQBinHeader->u32SourceLUT_Offset = u32Offset; ++ pPQBinHeader->u32SourceLUT_Pitch = PQ_BIN_SOURCELUT_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32SourceLUT_Pitch * (MS_U32)pPQBinHeader->u16SourceLUT_PnlNum; ++ ++ PQ_BIN_DBG_HEADER(printf("SourceLUT: offset=%lx, pitch=%lu\n", pPQBinHeader->u32SourceLUT_Offset, pPQBinHeader->u32SourceLUT_Pitch)); ++ ++ ++#if PQ_BIN_DBG_HEADER_DATA ++ // GRule ++ u32tmpoffset = pPQBinHeader->u32GRule_Offset; ++ for(i=0; iu16GRule_RuleNum; i++) ++ { ++ ++ MS_PQBin_GRule_Info stGRuleInfo; ++ ++ stGRuleInfo.u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u16SourceNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u32IPOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u32RuleOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("GRule %u, IPNum=%u, SourceNum=%u, GroupNum=%u, IPOffset=%lx, RuleOffset=%lx\n", ++ i, ++ stGRuleInfo.u16IPNum, ++ stGRuleInfo.u16SourceNum, ++ stGRuleInfo.u16GroupNum, ++ stGRuleInfo.u32IPOffset, ++ stGRuleInfo.u32RuleOffset); ++ } ++ ++ // GRule Level ++ for(i=0; iu16GRule_RuleNum*pPQBinHeader->u16GRule_PnlNum; i++) ++ { ++ MS_PQBin_GRule_Level_Info stGRuleLvlInfo; ++ ++ stGRuleLvlInfo.u16LvlNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleLvlInfo.u32Offset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("GRule_Lvl %u, u16LvlNum=%u, u32Offset=%lx \n", ++ i, stGRuleLvlInfo.u16LvlNum, stGRuleLvlInfo.u32Offset); ++ } ++ ++ // XRule ++ u32tmpoffset = pPQBinHeader->u32XRule_Offset; ++ for(i=0; iu16XRuleNum; i++) ++ { ++ MS_PQBin_XRule_Info stXRuleInfo; ++ ++ stXRuleInfo.u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stXRuleInfo.u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stXRuleInfo.u32IPOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stXRuleInfo.u32GroupOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("XRule %u, IPNum=%u, GroupNum=%u, IPOffset=%lx, GroupOffset=%lx\n", ++ i, stXRuleInfo.u16IPNum, stXRuleInfo.u16GroupNum, stXRuleInfo.u32IPOffset, stXRuleInfo.u32GroupOffset); ++ } ++ ++ // IP & Common ++ u32tmpoffset = pPQBinHeader->u32IP_Comm_Offset; ++ for(i=0; iu16IP_Comm_Num; i++) ++ { ++ MS_PQBin_IP_Common_Info stIPCommInfo; ++ ++ stIPCommInfo.u16CommRegNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u16IPRegNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u16IPGroupNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u32CommOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u32IPOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("IP_Comm %u, CommRegNum=%u, IPRegNum=%u, IPGroupNum=%u, CommOffset=%lx, IPOffset=%lx\n", ++ i, ++ stIPCommInfo.u16CommRegNum, ++ stIPCommInfo.u16IPRegNum, ++ stIPCommInfo.u16IPGroupNum, ++ stIPCommInfo.u32CommOffset, ++ stIPCommInfo.u32IPOffset); ++ } ++ ++ // SourceLUT ++ u32tmpoffset = pPQBinHeader->u32SourceLUT_Offset; ++ for(i=0; iu16SourceLUT_PnlNum; i++) ++ { ++ MS_PQBin_SourceLUT_Info stSourceLUTInfo; ++ ++ stSourceLUTInfo.u16SourceNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stSourceLUTInfo.u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stSourceLUTInfo.u32Offset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("SourceLUT %u, SourceNum=%u, IPNum=%u, Offset=%lx\n", ++ i, ++ stSourceLUTInfo.u16SourceNum, ++ stSourceLUTInfo.u16IPNum, ++ stSourceLUTInfo.u32Offset); ++ ++ } ++#endif ++ ++} ++ ++ ++MS_U16 MDrv_PQBin_GetSkipRule(MS_U16 u16PQIPIdx, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U16 u16SkipRet; ++ ++ u32Addr = pPQBinHeader->u32SkipRule_Offset + ++ pPQBinHeader->u32BinStartAddress + ++ PQ_BIN_SKIPRULE_HEADER_LEN; ++ ++ u32Offset = u16PQIPIdx * 2; ++ u16SkipRet = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)) , &u32Offset); ++ return u16SkipRet; ++} ++ ++void MDrv_PQBin_LoadTableBySrcType( ++ MS_U16 u16PQSrcType, ++ MS_U16 u16PQIPIdx, ++ MS_U16 u16PQPnlIdx, ++ MS_PQBin_Header_Info *pPQBinHeader) ++{ ++ MS_U16 QMIPtype_size,i; ++ MS_U16 u16TabIdx; ++ MS_PQBin_IP_Table_Info stTableInfo; ++ //XC_ApiStatusEx stXCStatusEx; Ryan ++ ++ if (u16PQIPIdx==PQ_BIN_IP_ALL) ++ { ++ QMIPtype_size= MDrv_PQBin_GetIPNum(pPQBinHeader); ++ u16PQIPIdx=0; ++ } ++ else ++ { ++ QMIPtype_size=1; ++ } ++ ++ ++ for(i=0; iu32XRule_Offset + pPQBinHeader->u32BinStartAddress; ++ ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_IP_NUM_OFFSET; ++ u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_GROUPOFFSET_OFFSET; ++ u32Rule_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress; ++ ++ ++ u32Rule_Offset = (u16IPNum * u16XRuleIdx + u16XRuleIP ) * 2; ++ u16TableIdx = MDrv_PQBin_Get2ByteData((void *)(u32Rule_Addr+u32Rule_Offset), &u32Rule_Offset); ++ ++ PQ_BIN_XRULE_DBG(printf("[PQBin_XRule]: TableIdx=%u\n", u16TableIdx)); ++ return u16TableIdx; ++ ++} ++ ++MS_U16 MDrv_PQBin_GetXRuleIPIndex(MS_U16 u16XRuleType, MS_U16 u16XRuleIP, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U32 u32IP_Addr; ++ MS_U32 u32IP_Offset; ++ MS_U16 u16IPIdx; ++ ++ u32Addr = pPQBinHeader->u32XRule_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_IPOFFSET_OFFSET; ++ ++ u32IP_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress + PQ_BIN_XRULE_HEADER_LEN; ++ ++ u32IP_Offset = u16XRuleIP * 2; ++ ++ u16IPIdx = MDrv_PQBin_Get2ByteData((void *)(u32IP_Addr+u32IP_Offset), &u32IP_Offset); ++ ++ PQ_BIN_XRULE_DBG(printf("[PQBin_XRule]: IPIdx=%u\n", u16IPIdx)); ++ return u16IPIdx; ++ ++} ++ ++MS_U16 MDrv_PQBin_GetXRuleIPNum(MS_U16 u16XRuleType, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U16 u16IPNum; ++ ++ u32Addr = pPQBinHeader->u32XRule_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_IP_NUM_OFFSET; ++ u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_XRULE_DBG(printf("[PQBin_XRule]: IPNum=%u\n", u16IPNum)); ++ return u16IPNum; ++} ++ ++ ++ ++MS_U16 MDrv_PQBin_GetGRule_LevelIndex( ++ MS_U16 u16PnlIdx, ++ MS_U16 u16GRuleType, ++ MS_U16 u16GRuleLvlIndex, ++ MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset, u32Lvl_Addr; ++ MS_U16 u16LvlNum; ++ MS_U16 u16LvlIdx; ++ ++ if(u16PnlIdx >= pPQBinHeader->u16GRule_PnlNum) ++ { ++ MS_ASSERT(0); ++ printf("GRue: Pnl idx out of rage =%u\n", u16PnlIdx); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Addr = pPQBinHeader->u32GRule_Lvl_Offset + pPQBinHeader->u32BinStartAddress; ++ ++ u32Offset = pPQBinHeader->u32GRule_Lvl_Pitch * (MS_U32) (u16PnlIdx + pPQBinHeader->u16GRule_PnlNum * u16GRuleType) + ++ PQ_BIN_GRULE_LEVEL_LVL_NUM_OFFSET; ++ u16LvlNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ if(u16GRuleLvlIndex >= u16LvlNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: lvl idx out of rage =%u\n", u16GRuleLvlIndex); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Addr = pPQBinHeader->u32GRule_Lvl_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32GRule_Lvl_Pitch * (MS_U32) (u16PnlIdx + pPQBinHeader->u16GRule_PnlNum * u16GRuleType) + ++ PQ_BIN_GRULE_LEVEL_OFFSET_OFFSET; ++ ++ u32Lvl_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Addr = u32Lvl_Addr + pPQBinHeader->u32BinStartAddress; ++ u32Offset = PQ_BIN_GRULE_HEADER_LEN + u16GRuleLvlIndex * 2; ++ ++ u16LvlIdx = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_GRULE_DBG(printf("[PQBin_GRule: LvlIdx=%u\n", u16LvlIdx)); ++ return u16LvlIdx; ++} ++ ++ ++MS_U16 MDrv_PQBin_GetGRule_IPIndex( ++ MS_U16 u16GRuleType, ++ MS_U16 u16GRuleIPIndex, ++ MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32IP_Addr, u32IP_Offset; ++ MS_U16 u16IPIdx; ++ ++ u32Addr = pPQBinHeader->u32GRule_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + ++ PQ_BIN_GRULE_IPOFFSET_OFFSET; ++ ++ u32IP_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress + PQ_BIN_GRULE_HEADER_LEN; ++ u32IP_Offset = u16GRuleIPIndex * 2; ++ u16IPIdx = MDrv_PQBin_Get2ByteData((void *)(u32IP_Addr+u32IP_Offset), &u32IP_Offset); ++ ++ PQ_BIN_GRULE_DBG(printf("[PQBin_GRule: IPIdx=%u\n", u16IPIdx)); ++ return u16IPIdx; ++} ++ ++MS_U16 MDrv_PQBin_GetGRule_TableIndex( ++ MS_U16 u16GRuleType, ++ MS_U16 u16PQSrcType, ++ MS_U16 u16PQ_NRIdx, ++ MS_U16 u16GRuleIPIndex, ++ MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32Rule_Addr, u32Rule_Offset; ++ MS_U16 u16GroupNum, u16IPNum, u16SrcNum; ++ MS_U16 u16TableIdx; ++ ++ if(u16GRuleType >= pPQBinHeader->u16GRule_RuleNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: ruleid out of range=%u\n", u16GRuleType); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Addr = pPQBinHeader->u32GRule_Offset + pPQBinHeader->u32BinStartAddress; ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_GROUP_NUM_OFFSET; ++ u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_IP_NUM_OFFSET; ++ u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_SOURCE_NUM_OFFSET; ++ u16SrcNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ ++ ++ if(u16PQSrcType >= u16SrcNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: SrcIdx out of range =%u\n", u16PQSrcType); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ if(u16PQ_NRIdx >= u16GroupNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: GroupIdx out of range =%u\n", u16PQ_NRIdx); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ if(u16GRuleIPIndex >= u16IPNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: IPIdx out of range =%u\n", u16GRuleIPIndex); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_RULEOFFSET_OFFSET; ++ u32Rule_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress + PQ_BIN_GRULE_HEADER_LEN; ++ ++ ++ u32Rule_Offset = (u16IPNum * u16GroupNum * u16PQSrcType + ++ u16IPNum * u16PQ_NRIdx + ++ u16GRuleIPIndex) * 2; ++ u16TableIdx = MDrv_PQBin_Get2ByteData((void *)(u32Rule_Addr+u32Rule_Offset), &u32Rule_Offset); ++ PQ_BIN_GRULE_DBG(printf("[PQBin_GRule: TabIdx=%u\n", u16TableIdx)); ++ return u16TableIdx; ++} ++ ++ ++void MDrv_PQBin_CheckCommTable(MS_U16 u16PnlIdx, MS_PQBin_Header_Info * pPQBinHeader) ++{ ++#if (PQ_ENABLE_CHECK == 1) ++ _u8PQBinfunction = PQ_FUNC_CHK_REG; ++ MDrv_PQBin_LoadCommTable(u16PnlIdx, pPQBinHeader); ++ _u8PQBinfunction = PQ_FUNC_DUMP_REG; ++#else ++ UNUSED(u16PnlIdx); ++ UNUSED(pPQBinHeader); ++#endif ++} ++ ++void MDrv_PQBin_CheckTableBySrcType( ++ MS_U16 u16PQSrcType, ++ MS_U16 u16PQIPIdx, ++ MS_U16 u16PQPnlIdx, ++ MS_PQBin_Header_Info * pPQBinHeader) ++{ ++#if (PQ_ENABLE_CHECK == 1) ++ _u8PQBinfunction = PQ_FUNC_CHK_REG; ++ MDrv_PQBin_LoadTableBySrcType(u16PQSrcType, ++ u16PQIPIdx, ++ u16PQPnlIdx, ++ pPQBinHeader); ++ _u8PQBinfunction = PQ_FUNC_DUMP_REG; ++#else ++ UNUSED(u16PQSrcType); ++ UNUSED(u16PQIPIdx); ++ UNUSED(u16PQPnlIdx); ++ UNUSED(pPQBinHeader); ++#endif ++} ++ ++void MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_TYPE enDisplayType, PQ_WIN ePQWin) ++{ ++ _gPQBinDisplayType[ePQWin] = enDisplayType; ++} ++ ++PQ_BIN_DISPLAY_TYPE MDrv_PQBin_GetDisplayType(PQ_WIN ePQWin) ++{ ++ return (PQ_BIN_DISPLAY_TYPE)_gPQBinDisplayType[ePQWin]; ++} ++ ++void MDrv_PQBin_SetPanelID(MS_U8 u8PnlIDx, PQ_WIN ePQWin) ++{ ++ _gPQBinPnlIdx[ePQWin] = u8PnlIDx; ++} ++ ++MS_U8 MDrv_PQBin_GetPanelIdx(PQ_WIN ePQWin) ++{ ++#if (PQ_ENABLE_PIP) ++ if(ePQWin == PQ_SC1_MAIN_WINDOW) ++ return _gPQBinPnlIdx[ePQWin] * 1 + _gPQBinDisplayType[ePQWin]; // SC1 only has 720 panel ++ else ++ return _gPQBinPnlIdx[ePQWin] * PQ_BIN_DISPLAY_NUM + _gPQBinDisplayType[ePQWin]; ++#else ++ return _gPQBinPnlIdx[ePQWin] * 1 + _gPQBinDisplayType[ePQWin]; ++#endif ++} ++ ++void MDrv_PQBin_Set_MLoadEn(MS_BOOL bEn) ++{ ++ MS_U16 i; ++ ++ if(bEn == DISABLE) ++ { ++ //if spread reg, no need to use mutex, but it's ok to use mutex ++ // (because it's not MApi_XC_W2BYTE(), which has mutex already) ++ //if not spread reg, must use mutex to protect MLoad_trigger func. ++ SC_BK_STORE_MUTEX; ++ ++ if(_u16MLoadCmdCnt) ++ { ++ for(i=1; i<_u16MLoadCmdCnt; i++) ++ { ++ if(_u32MLoadCmd[i-1] == _u32MLoadCmd[i]) ++ { ++ _u16MLoadMsk[i] |= _u16MLoadMsk[i-1]; ++ _u16MLoadVal[i] |= _u16MLoadVal[i-1]; ++ } ++ } ++ #if(ENABLE_PQ_MLOAD) ++ MApi_XC_MLoad_WriteCmds_And_Fire( ++ &_u32MLoadCmd[0], &_u16MLoadVal[0], &_u16MLoadMsk[0], _u16MLoadCmdCnt); ++ #endif ++ ++ _u16MLoadCmdCnt = 0; ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++ } ++ ++ _bMLoadEn = bEn; ++} ++ ++//------------------------------------------------------------------------------ ++// Text Bin function ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_PQTextBin_Parsing(MS_PQTextBin_Header_Info *pPQTextBinHeader) ++{ ++ MS_U32 u32PQBin_Addr; ++ MS_U32 u32Offset; ++#if PQ_BIN_DBG_HEADER_DATA ++ MS_U32 u32tmpoffset; ++#endif ++ MS_U8 i; ++ ++ u32Offset = 0; ++ u32PQBin_Addr = pPQTextBinHeader->u32BinStartAddress; ++ printf("TextBinStartaDDR ID%u=%lx\n", pPQTextBinHeader->u8BinID, u32PQBin_Addr); ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8Version[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ ++ pPQTextBinHeader->u32StartOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQTextBinHeader->u32EndOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ for(i=0; i< PQ_TEXT_BIN_DUMMY; i++) ++ { ++ pPQTextBinHeader->u8Dummy[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("Header :%s\n", pPQTextBinHeader->u8Header)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("Version:%s\n", pPQTextBinHeader->u8Version)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("startADDR=%lx, pPQTextBinHeader=%lx\n", pPQTextBinHeader->u32StartOffset, pPQTextBinHeader->u32EndOffset)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("Dummy :%s \n", pPQTextBinHeader->u8Dummy)); ++ ++ ++ if(pPQTextBinHeader->u8Header[0] != 0x43 || pPQTextBinHeader->u8Header[0] != 0x33 || ++ pPQTextBinHeader->u8Dummy[0] != 0xA5 || pPQTextBinHeader->u8Dummy[0] != 0x59) ++ { ++ printf("PQ Parsing Fail \n"); ++ return FALSE; ++ } ++ ++ ++ // SrcType ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8SrcTypeHeader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQTextBinHeader->u16SrcNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ PQ_TEXT_BIN_DBG_HEADER(printf("SrcTypeHeader:%s\n", pPQTextBinHeader->u8SrcTypeHeader)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("SrcType: RuleNum=%u\n", pPQTextBinHeader->u16SrcNum)); ++ ++ pPQTextBinHeader->u32SrcType_Offset = u32Offset; ++ pPQTextBinHeader->u32SrcType_Pitch = PQ_TEXT_BIN_SRCTYPE_INFO_SIZE; ++ u32Offset += pPQTextBinHeader->u32SrcType_Pitch * (MS_U32)pPQTextBinHeader->u16SrcNum; ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("SrcType: offset=%lx, pitch=%lu\n",pPQTextBinHeader->u32SrcType_Offset, pPQTextBinHeader->u32SrcType_Pitch)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName Start:%lx\n", u32Offset)); ++ ++ // IP Name ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8IPNameHeader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQTextBinHeader->u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPNameHeader:%s\n", pPQTextBinHeader->u8IPNameHeader)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName: IPNum=%u\n", pPQTextBinHeader->u16IPNum)); ++ ++ pPQTextBinHeader->u32IPName_Offset = u32Offset; ++ pPQTextBinHeader->u32IPName_Pitch = PQ_TEXT_BIN_IPNAME_INFO_SIZE; ++ u32Offset += pPQTextBinHeader->u32IPName_Pitch * (MS_U32)pPQTextBinHeader->u16IPNum; ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName: offset=%lx, pitch=%lu\n",pPQTextBinHeader->u32IPName_Offset, pPQTextBinHeader->u32IPName_Pitch)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("GroupName Start:%lx\n", u32Offset)); ++ ++ // Group Name ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8GroupNameHeader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQTextBinHeader->u16GroupIPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("GroupName:%s\n", pPQTextBinHeader->u8GroupNameHeader)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("GroupName: IPNum=%u\n", pPQTextBinHeader->u16GroupIPNum)); ++ ++ pPQTextBinHeader->u32IP_Group_Offset = u32Offset; ++ pPQTextBinHeader->u32IP_Group_pitch = PQ_TEXT_BIN_GROUPNAME_INFO_SIZE; ++ u32Offset += pPQTextBinHeader->u32IP_Group_pitch * (MS_U32)pPQTextBinHeader->u16GroupIPNum; ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName: offset=%lx, pitch=%lu\n",pPQTextBinHeader->u32IP_Group_Offset, pPQTextBinHeader->u32IP_Group_pitch)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("Group Start:%lx\n", u32Offset)); ++ ++ return TRUE; ++ ++} ++ ++MS_U32 MDrv_PQTextBin_GetSrcType(MS_U16 u16SrcIdx, MS_PQTextBin_Header_Info* pPQTextBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32DstAddr; ++ ++ if(u16SrcIdx >= pPQTextBinHeader->u16SrcNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetSrcType:: SrcIdx Out of range %u\n", u16SrcIdx); ++ u16SrcIdx = 0; ++ } ++ u32Addr = pPQTextBinHeader->u32SrcType_Offset + pPQTextBinHeader->u32BinStartAddress; ++ u32Offset = pPQTextBinHeader->u32SrcType_Pitch * u16SrcIdx + ++ PQ_TEXT_BIN_SRCTYPE_OFFSET_OFFSET; ++ ++ u32DstAddr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ PQ_TEXT_BIN_DBG(printf("PQTextBin SrcType: Addr%lx, SrcIdx%u\n", u32DstAddr, u16SrcIdx)); ++ return u32DstAddr; ++} ++ ++MS_U32 MDrv_PQTextBin_GetIPName(MS_U16 u16PQIPIdx, MS_PQTextBin_Header_Info* pPQTextBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32DstAddr; ++ ++ if(u16PQIPIdx >= pPQTextBinHeader->u16IPNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetIPName:: IPIdx Out of range %u\n", u16PQIPIdx); ++ u16PQIPIdx = 0; ++ } ++ u32Addr = pPQTextBinHeader->u32IPName_Offset + pPQTextBinHeader->u32BinStartAddress; ++ u32Offset = pPQTextBinHeader->u32IPName_Pitch * u16PQIPIdx + ++ PQ_TEXT_BIN_IPNAME_OFFSET_OFFSET; ++ ++ u32DstAddr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ PQ_TEXT_BIN_DBG(printf("PQTextBin IPName: %lx\n", u32DstAddr)); ++ return u32DstAddr; ++} ++ ++MS_U32 MDrv_PQTextBin_GetTableName(MS_U16 u16PQIPIdx, MS_U16 u16TabIdx, MS_PQTextBin_Header_Info* pPQTextBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32DstAddr; ++ MS_U16 u16GroupNum; ++ MS_U32 u32Total_Len; ++ MS_U32 i; ++ ++ if(u16PQIPIdx >= pPQTextBinHeader->u16GroupIPNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetGroupName:: IPIdx Out of range %u\n", u16PQIPIdx); ++ u16PQIPIdx = 0; ++ } ++ ++ u32Addr = pPQTextBinHeader->u32IP_Group_Offset + pPQTextBinHeader->u32BinStartAddress; ++ u32Offset = pPQTextBinHeader->u32IP_Group_pitch * u16PQIPIdx + ++ PQ_TEXT_BIN_GROUPNAME_IPGROUP_GROUPNUM_OFFSET; ++ u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ if(u16TabIdx >= u16GroupNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetGroupName :: TableIdx Out of range %u\n", u16TabIdx); ++ u16TabIdx = 0; ++ } ++ u32Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ u32Offset = PQ_TEXT_BIN_GROUPNAME_GROUPOFFSET_OFFSET; ++ u32DstAddr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ u32Total_Len = 0; ++ for(i=0; i< u16TabIdx; i++) ++ { ++ u32Offset = PQ_TEXT_BIN_GROUPNAME_GROUPOFFSET_LEN + ++ PQ_TEXT_BIN_GROUPNAME_GROUPLENGTH_LEN * i; ++ ++ u32Total_Len += MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ } ++ ++ PQ_TEXT_BIN_DBG(printf("PQTextBin GroupName: %lx\n", (u32DstAddr+u32Total_Len))); ++ return (u32DstAddr+u32Total_Len); ++} ++ ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ_Text.c b/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ_Text.c +new file mode 100644 +index 00000000..72ca383c +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/drvPQ_Text.c +@@ -0,0 +1,135 @@ ++// $Change: 600891 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++ ++#include "MsCommon.h" ++#include "MsTypes.h" ++ ++#include "drvPQ_Define.h" ++#include "drvPQ.h" ++ ++//#include "QualityMap_Text.c" ++#include "drvPQ_Bin.h" ++ ++ ++#if(ENABLE_PQ_BIN) ++MS_PQTextBin_Header_Info stPQTextBinHeaderInfo[MAX_PQ_TEXT_BIN_NUM]; ++MS_BOOL gbEnablePQTextBin = 0; ++#endif ++ ++#if 0 ++char* MDrv_PQ_GetSrcTypeName(PQ_WIN eWindow) ++{ ++#if(ENABLE_PQ_BIN) ++ if(gbEnablePQTextBin) ++ { ++ MS_U32 u32Addr; ++ MS_U16 u16SrcIDx = MDrv_PQ_GetSrcType(eWindow); ++ ++ u32Addr = MDrv_PQTextBin_GetSrcType(u16SrcIDx, &stPQTextBinHeaderInfo[eWindow]); ++ return ((char *)u32Addr); ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ return NULL; ++ #else ++ return PQ_INPUTTYPE_TEXT_Main[MDrv_PQ_GetSrcType(eWindow)]; ++ #endif ++ } ++} ++ ++char* MDrv_PQ_GetIPName(MS_U8 u8PQIPIdx) ++{ ++#if(ENABLE_PQ_BIN) ++ ++ if(gbEnablePQTextBin) ++ { ++ MS_U32 u32Addr;; ++ u32Addr = MDrv_PQTextBin_GetIPName((MS_U16)u8PQIPIdx, &stPQTextBinHeaderInfo[PQ_MAIN_WINDOW]); ++ return ((char *)u32Addr); ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ return NULL; ++ #else ++ return PQ_IP_Text_Main[u8PQIPIdx]; ++ #endif ++ } ++} ++ ++char* MDrv_PQ_GetTableName(MS_U8 u8PQIPIdx, MS_U8 u8TabIdx ) ++{ ++#if(ENABLE_PQ_BIN) ++ if(gbEnablePQTextBin) ++ { ++ MS_U32 u32Addr;; ++ u32Addr = MDrv_PQTextBin_GetTableName((MS_U16)u8PQIPIdx, ++ (MS_U16)u8TabIdx, ++ &stPQTextBinHeaderInfo[PQ_MAIN_WINDOW]); ++ return ((char *)u32Addr); ++ ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ return NULL; ++ #else ++ char** PQ_Stream; ++ ++ PQ_Stream = PQ_IPTAB_TEXT_Main[u8PQIPIdx]; ++ return PQ_Stream[u8TabIdx]; ++ #endif ++ } ++} ++ ++#if 0 ++void MDrv_PQ_Text_Demo(SCALER_WIN eWindow) ++{ ++ MS_U8 u8IPIdx, u8TabIdx, u8IPNum, u8TabNum; ++ U16 u16PQSrcType; ++ ++ u16PQSrcType = MDrv_PQ_GetSrcType(eWindow); ++ printf("u16PQSrcType=%u\n", u16PQSrcType); ++ ++ u8IPNum = MDrv_PQ_GetIPNum(eWindow); ++ ++ for( u8IPIdx = 0; u8IPIdx < u8IPNum; u8IPIdx++) ++ { ++ u8TabNum = MDrv_PQ_GetTableNum(eWindow, u8IPIdx); ++ printf("IP:%u [%s], tabnum=%u\n", u8IPIdx, MDrv_PQ_GetIPName(u8IPIdx), u8TabNum); ++ ++ u8TabIdx = MDrv_PQ_GetCurrentTableIndex(eWindow, u8IPIdx); ++ printf("TAB:%u [%s]\n", u8TabIdx, ++ (u8TabIdx == PQ_IP_NULL) ? "null" : MDrv_PQ_GetTableName(u8IPIdx, u8TabIdx)); ++ } ++} ++#endif ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/drvbw.c b/drivers/mstar/scl/infinity/src/mxlib/pq/drvbw.c +new file mode 100644 +index 00000000..7d7ed40c +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/drvbw.c +@@ -0,0 +1,265 @@ ++// $Change: 617839 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "hwreg_utility2.h" ++#include "drvXC_IOPort.h" ++#include "apiXC.h" ++#include "color_reg.h" ++#include "drvPQ_Define.h" ++#include "drvPQ.h" ++#include "QualityMode.h" ++ ++ ++extern MS_PQ_Mode_Info _stMode_Info[PQ_MAX_WINDOW]; ++ ++#define BW_DBG(x) //x ++ ++ ++ ++typedef struct ++{ ++ MS_U8 *pIPTable; ++ MS_U8 u8TabNums; ++ MS_U8 u8TabIdx; ++} TAB_Info; ++ ++#include "Cedric_QualityMap_BW.c" ++ ++static MS_U8 *pBwTable=(void*)BWTABLE; ++ ++static void _MDrv_BW_LoadTable(MS_U8 u8TabIdx) ++{ ++ TAB_Info tab_Info; ++ tab_Info.pIPTable = pBwTable; ++ tab_Info.u8TabNums = BWTABLE_NUMS; ++ tab_Info.u8TabIdx = u8TabIdx; ++ ++ BW_DBG(printf("[BW]LoadTable\n")); ++ ++ _MDrv_BW_DumpTable(&tab_Info); ++} ++ ++void MDrv_BW_LoadInitTable(void) ++{ ++ TAB_Info tab_Info; ++ tab_Info.pIPTable = (void*)BWTABLE_COM; ++ tab_Info.u8TabNums = 1; ++ tab_Info.u8TabIdx = 0; ++ ++ BW_DBG(printf("[BW]LoadCommTable\n")); ++ _MDrv_BW_DumpTable(&tab_Info); ++} ++ ++#ifdef __AEONR2__ //janus ++void MDrv_BW_LoadTableByContext(PQ_WIN eWindow) ++{ ++ MS_U16 u16Input_HSize; ++ MS_U16 u16Input_VSize; ++ MS_U16 u16Input_VFreq; ++ MS_BOOL bIsInterlaced; ++ MS_U8 u8TabIdx; ++ PQ_INPUT_SOURCE_TYPE pqInputSourceType; ++ ++ u16Input_HSize = _stMode_Info[eWindow].u16input_hsize; ++ u16Input_VSize = _stMode_Info[eWindow].u16input_vsize; ++ u16Input_VFreq = _stMode_Info[eWindow].u16input_vfreq; ++ bIsInterlaced = _stMode_Info[eWindow].bInterlace; ++ pqInputSourceType = MDrv_PQ_GetInputSourceType(eWindow); ++ ++ if ( QM_IsSourceMultiMedia(pqInputSourceType) ) ++ { ++ if(u16Input_HSize>1280 && u16Input_VSize>=900) ++ u8TabIdx = BWTABLE_MM; ++ else ++ u8TabIdx = BWTABLE_MM_720p; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced && (u16Input_VFreq >= 490)) ++ { ++ // 1920x1080@50/60p ++ if( QM_IsSourceVGA(pqInputSourceType) ) ++ { ++ u8TabIdx = BWTABLE_PC_mode; ++ } ++ else ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ } ++ else ++ { ++ if ( QM_IsSourceATV(pqInputSourceType) || QM_IsSourceAV(pqInputSourceType) || QM_IsSourceSV(pqInputSourceType) ) ++ u8TabIdx = BWTABLE_Normal_mode; ++ else ++ u8TabIdx = BWTABLE_case6; ++ } ++ ++ pBwTable=_MDrv_BW_DDR_Speed(); ++ ++ _MDrv_BW_LoadTable(u8TabIdx); ++} ++ ++#else ++ ++void MDrv_BW_LoadTableByContext(PQ_WIN eWindow) ++{ ++ ++ MS_U16 u16Input_HSize; ++ MS_U16 u16Input_VSize; ++ MS_BOOL bIsInterlaced; ++ MS_U8 u8TabIdx; ++ MS_U16 u16Input_VFreq; ++ MS_U16 u16input_vtotal; ++ ++ u16Input_HSize = _stMode_Info[eWindow].u16input_hsize; ++ u16Input_VSize = _stMode_Info[eWindow].u16input_vsize; ++ bIsInterlaced = _stMode_Info[eWindow].bInterlace; ++ u16Input_VFreq = _stMode_Info[eWindow].u16input_vfreq; ++ u16input_vtotal = _stMode_Info[eWindow].u16input_vtotal; ++ ++//![for temporary A3-WinCE6 porting, 20120109] ++#if (defined(MSOS_TYPE_CE) || defined(MSOS_TYPE_LINUX_KERNEL)) ++ ++ if (u16Input_HSize>=1440 && u16Input_VSize >= 900) ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ ++#else ++ ++ #if ((CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD) && !ENABLE_MIU_1) ++ ++ if(QM_IsSourceMultiMedia(MDrv_PQ_GetInputSourceType(eWindow))) ++ { ++ u8TabIdx = BWTABLE_MM; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced && (u16Input_VFreq >= 490)) ++ { ++ // 1920x1080@50/60p ++ if(QM_IsSourceVGA(MDrv_PQ_GetInputSourceType(eWindow))) ++ { ++ u8TabIdx = BWTABLE_PC_mode; ++ } ++ else ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ } ++ else ++ { ++ if(QM_IsSourceDTV(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize >= 720) //DTV 720P and 1080i case ++ { ++ //printf(">>>111 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_720p_1080i_mode; ++ } ++ else ++ { ++ //printf(">>>222 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ } ++ ++ #elif (CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD) ++ ++ if(u16Input_HSize>=1024 && u16Input_VSize >= 768 && !bIsInterlaced && (u16Input_VFreq >= 490) && QM_IsSourceVGA(MDrv_PQ_GetInputSourceType(eWindow))) ++ { ++ u8TabIdx = BWTABLE_PC_mode; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced) ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ else if(QM_IsSourceDTV(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize >= 720) //DTV 720P and 1080i case ++ { ++ //printf(">>>333 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_720p_1080i_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ ++ #elif (CHIP_FAMILY_TYPE == CHIP_FAMILY_A6) ++ ++ if(QM_IsSourceMultiMedia(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize > 2000) //MPO case ++ { ++ //printf(">>>333 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_mpo_mode; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced) ++ { ++ if(QM_IsSourceVGA(MDrv_PQ_GetInputSourceType(eWindow)) && (u16input_vtotal ==1120)) ++ { ++ //printf("print u16input_vtotal = %d\n",u16input_vtotal); ++ //patch for special vga 1080p timing with vtotal 1120, htt 2576 ++ u8TabIdx = BWTABLE_S1080p_mode; ++ } ++ else ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ } ++ else ++ { ++ if(QM_IsSourceDTV(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize > 720) //DTV 1080i case ++ { ++ //printf(">>>333 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_1080i_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ } ++ ++ #else ++ ++ if (u16Input_HSize>=1440 && u16Input_VSize >= 900) ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ ++ #endif ++ ++#endif ++ ++ ++ _MDrv_BW_LoadTable(u8TabIdx); ++ ++} ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/QualityMap_Main.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/QualityMap_Main.c +new file mode 100644 +index 00000000..6a9e637e +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/QualityMap_Main.c +@@ -0,0 +1,50 @@ ++// $Change: 616729 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#define PQTABLE_NAME MAIN // table config parameter ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++#include "MsTypes.h" ++#include "color_reg.h" ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++#include "hwreg_utility2.h" ++ ++#define PQTBL_REGTYPE PQTBL_NORMAL // table config parameter ++ ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ ++#include "Infinity_Main.c" // table config parameter ++#include "Infinity_Main_1920.c" // table config parameter ++#include "Infinity_Main_HSPRule.c" // table config parameter ++#include "Infinity_Main_VSPRule.c" // table config parameter ++#include "Infinity_Main_GRule.c" // table config parameter ++#include "Infinity_Main_1920_GRule.c" // table config parameter ++#endif ++ ++#include "QualityMode.h" ++#include "drvPQ_Datatypes.h" ++#include "mhal_pq.h" ++#include "drvPQ_Template.h" +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/color_reg.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/color_reg.h +new file mode 100644 +index 00000000..1d68001e +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/color_reg.h +@@ -0,0 +1,13694 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _COLOR_REG_H_ ++#define _COLOR_REG_H_ ++/////////////////////////////////////////////////////// ++// Scaler Bank ++/////////////////////////////////////////////////////// ++#define REG_BANK_RESET 0x00 ++#define REG_BANK_GOPINT 0x00 ++#define REG_BANK_IP1F2 0x01 ++#define REG_BANK_IP2F2 0x02 ++#define REG_BANK_IP1F1 0x03 ++#define REG_BANK_IP2F1 0x04 ++#define REG_BANK_OPM 0x05 ++#define REG_BANK_DNR 0x06 ++#define REG_BANK_OP1 0x07 ++#define REG_BANK_OP1PIP 0x08 ++#define REG_BANK_OP1HVSP 0x09 ++#define REG_BANK_FILM 0x0A //T2 ++#define REG_BANK_ELA 0x0B ++#define REG_BANK_ACE 0x0C ++#define REG_BANK_HD 0x0E ++#define REG_BANK_S_VOP 0x0F ++#define REG_BANK_VOP 0x10 ++#define REG_BANK_TCON 0x11 ++#define REG_BANK_SCMI 0x12 //T2 ++#define REG_BANK_OD 0x16 ++#define REG_BANK_SRAM 0x17 ++#define REG_BANK_VIP 0x18 ++#define REG_BANK_VPS 0x19 ++#define REG_BANK_DLC 0x1A ++#define REG_BANK_OP1PIPEXT 0x1B ++#define REG_BANK_SmoothFilter 0x1C ++#define REG_BANK_MFC 0x1D ++#define REG_BANK_PIP 0x20 ++#define REG_BANK_EODI 0x21 ++#define REG_BANK_MADI 0x22 ++#define REG_BANK_HVSP 0x23 ++#define REG_BANK_DMS 0x26 ++#define REG_BANK_PRED 0x28 ++// Scaler Base ++#define BK_IPMUX_BASE 0x2E00 ++//#define BK_SCALER_BASE 0x102F00 ++#define BK_MOD_BASE 0x3200 ++#define BK_TCON_BASE 0x3000 ++#define BK_LPLL_BASE 0x3100 ++#define REG_GOP_BANK 0x101FFE ++#define MAKE_ADDR(_x_) (0x100000 | _x_) ++// MVOP Base ++#define VOP_MPG_JPG_SWITCH 0x1440 ++#define VOP_UV_SHIFT 0x1460 ++#define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) ++#define _PK_H_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2+1)) ++#define REG_SC_DUMMY _PK_L_(0xFF, 0x01) ++#define REG_TABLE_END 0xFFFF ++//---------------------------------------------- ++#define REG_SC_BK00_00_L _PK_L_(0x00, 0x00) ++#define REG_SC_BK00_00_H _PK_H_(0x00, 0x00) ++#define REG_SC_BK00_01_L _PK_L_(0x00, 0x01) ++#define REG_SC_BK00_01_H _PK_H_(0x00, 0x01) ++#define REG_SC_BK00_02_L _PK_L_(0x00, 0x02) ++#define REG_SC_BK00_02_H _PK_H_(0x00, 0x02) ++#define REG_SC_BK00_03_L _PK_L_(0x00, 0x03) ++#define REG_SC_BK00_03_H _PK_H_(0x00, 0x03) ++#define REG_SC_BK00_04_L _PK_L_(0x00, 0x04) ++#define REG_SC_BK00_04_H _PK_H_(0x00, 0x04) ++#define REG_SC_BK00_05_L _PK_L_(0x00, 0x05) ++#define REG_SC_BK00_05_H _PK_H_(0x00, 0x05) ++#define REG_SC_BK00_06_L _PK_L_(0x00, 0x06) ++#define REG_SC_BK00_06_H _PK_H_(0x00, 0x06) ++#define REG_SC_BK00_07_L _PK_L_(0x00, 0x07) ++#define REG_SC_BK00_07_H _PK_H_(0x00, 0x07) ++#define REG_SC_BK00_08_L _PK_L_(0x00, 0x08) ++#define REG_SC_BK00_08_H _PK_H_(0x00, 0x08) ++#define REG_SC_BK00_09_L _PK_L_(0x00, 0x09) ++#define REG_SC_BK00_09_H _PK_H_(0x00, 0x09) ++#define REG_SC_BK00_0A_L _PK_L_(0x00, 0x0A) ++#define REG_SC_BK00_0A_H _PK_H_(0x00, 0x0A) ++#define REG_SC_BK00_0B_L _PK_L_(0x00, 0x0B) ++#define REG_SC_BK00_0B_H _PK_H_(0x00, 0x0B) ++#define REG_SC_BK00_0C_L _PK_L_(0x00, 0x0C) ++#define REG_SC_BK00_0C_H _PK_H_(0x00, 0x0C) ++#define REG_SC_BK00_0D_L _PK_L_(0x00, 0x0D) ++#define REG_SC_BK00_0D_H _PK_H_(0x00, 0x0D) ++#define REG_SC_BK00_0E_L _PK_L_(0x00, 0x0E) ++#define REG_SC_BK00_0E_H _PK_H_(0x00, 0x0E) ++#define REG_SC_BK00_0F_L _PK_L_(0x00, 0x0F) ++#define REG_SC_BK00_0F_H _PK_H_(0x00, 0x0F) ++#define REG_SC_BK00_10_L _PK_L_(0x00, 0x10) ++#define REG_SC_BK00_10_H _PK_H_(0x00, 0x10) ++#define REG_SC_BK00_11_L _PK_L_(0x00, 0x11) ++#define REG_SC_BK00_11_H _PK_H_(0x00, 0x11) ++#define REG_SC_BK00_12_L _PK_L_(0x00, 0x12) ++#define REG_SC_BK00_12_H _PK_H_(0x00, 0x12) ++#define REG_SC_BK00_13_L _PK_L_(0x00, 0x13) ++#define REG_SC_BK00_13_H _PK_H_(0x00, 0x13) ++#define REG_SC_BK00_14_L _PK_L_(0x00, 0x14) ++#define REG_SC_BK00_14_H _PK_H_(0x00, 0x14) ++#define REG_SC_BK00_15_L _PK_L_(0x00, 0x15) ++#define REG_SC_BK00_15_H _PK_H_(0x00, 0x15) ++#define REG_SC_BK00_16_L _PK_L_(0x00, 0x16) ++#define REG_SC_BK00_16_H _PK_H_(0x00, 0x16) ++#define REG_SC_BK00_17_L _PK_L_(0x00, 0x17) ++#define REG_SC_BK00_17_H _PK_H_(0x00, 0x17) ++#define REG_SC_BK00_18_L _PK_L_(0x00, 0x18) ++#define REG_SC_BK00_18_H _PK_H_(0x00, 0x18) ++#define REG_SC_BK00_19_L _PK_L_(0x00, 0x19) ++#define REG_SC_BK00_19_H _PK_H_(0x00, 0x19) ++#define REG_SC_BK00_1A_L _PK_L_(0x00, 0x1A) ++#define REG_SC_BK00_1A_H _PK_H_(0x00, 0x1A) ++#define REG_SC_BK00_1B_L _PK_L_(0x00, 0x1B) ++#define REG_SC_BK00_1B_H _PK_H_(0x00, 0x1B) ++#define REG_SC_BK00_1C_L _PK_L_(0x00, 0x1C) ++#define REG_SC_BK00_1C_H _PK_H_(0x00, 0x1C) ++#define REG_SC_BK00_1D_L _PK_L_(0x00, 0x1D) ++#define REG_SC_BK00_1D_H _PK_H_(0x00, 0x1D) ++#define REG_SC_BK00_1E_L _PK_L_(0x00, 0x1E) ++#define REG_SC_BK00_1E_H _PK_H_(0x00, 0x1E) ++#define REG_SC_BK00_1F_L _PK_L_(0x00, 0x1F) ++#define REG_SC_BK00_1F_H _PK_H_(0x00, 0x1F) ++#define REG_SC_BK00_20_L _PK_L_(0x00, 0x20) ++#define REG_SC_BK00_20_H _PK_H_(0x00, 0x20) ++#define REG_SC_BK00_21_L _PK_L_(0x00, 0x21) ++#define REG_SC_BK00_21_H _PK_H_(0x00, 0x21) ++#define REG_SC_BK00_22_L _PK_L_(0x00, 0x22) ++#define REG_SC_BK00_22_H _PK_H_(0x00, 0x22) ++#define REG_SC_BK00_23_L _PK_L_(0x00, 0x23) ++#define REG_SC_BK00_23_H _PK_H_(0x00, 0x23) ++#define REG_SC_BK00_24_L _PK_L_(0x00, 0x24) ++#define REG_SC_BK00_24_H _PK_H_(0x00, 0x24) ++#define REG_SC_BK00_25_L _PK_L_(0x00, 0x25) ++#define REG_SC_BK00_25_H _PK_H_(0x00, 0x25) ++#define REG_SC_BK00_26_L _PK_L_(0x00, 0x26) ++#define REG_SC_BK00_26_H _PK_H_(0x00, 0x26) ++#define REG_SC_BK00_27_L _PK_L_(0x00, 0x27) ++#define REG_SC_BK00_27_H _PK_H_(0x00, 0x27) ++#define REG_SC_BK00_28_L _PK_L_(0x00, 0x28) ++#define REG_SC_BK00_28_H _PK_H_(0x00, 0x28) ++#define REG_SC_BK00_29_L _PK_L_(0x00, 0x29) ++#define REG_SC_BK00_29_H _PK_H_(0x00, 0x29) ++#define REG_SC_BK00_2A_L _PK_L_(0x00, 0x2A) ++#define REG_SC_BK00_2A_H _PK_H_(0x00, 0x2A) ++#define REG_SC_BK00_2B_L _PK_L_(0x00, 0x2B) ++#define REG_SC_BK00_2B_H _PK_H_(0x00, 0x2B) ++#define REG_SC_BK00_2C_L _PK_L_(0x00, 0x2C) ++#define REG_SC_BK00_2C_H _PK_H_(0x00, 0x2C) ++#define REG_SC_BK00_2D_L _PK_L_(0x00, 0x2D) ++#define REG_SC_BK00_2D_H _PK_H_(0x00, 0x2D) ++#define REG_SC_BK00_2E_L _PK_L_(0x00, 0x2E) ++#define REG_SC_BK00_2E_H _PK_H_(0x00, 0x2E) ++#define REG_SC_BK00_2F_L _PK_L_(0x00, 0x2F) ++#define REG_SC_BK00_2F_H _PK_H_(0x00, 0x2F) ++#define REG_SC_BK00_30_L _PK_L_(0x00, 0x30) ++#define REG_SC_BK00_30_H _PK_H_(0x00, 0x30) ++#define REG_SC_BK00_31_L _PK_L_(0x00, 0x31) ++#define REG_SC_BK00_31_H _PK_H_(0x00, 0x31) ++#define REG_SC_BK00_32_L _PK_L_(0x00, 0x32) ++#define REG_SC_BK00_32_H _PK_H_(0x00, 0x32) ++#define REG_SC_BK00_33_L _PK_L_(0x00, 0x33) ++#define REG_SC_BK00_33_H _PK_H_(0x00, 0x33) ++#define REG_SC_BK00_34_L _PK_L_(0x00, 0x34) ++#define REG_SC_BK00_34_H _PK_H_(0x00, 0x34) ++#define REG_SC_BK00_35_L _PK_L_(0x00, 0x35) ++#define REG_SC_BK00_35_H _PK_H_(0x00, 0x35) ++#define REG_SC_BK00_36_L _PK_L_(0x00, 0x36) ++#define REG_SC_BK00_36_H _PK_H_(0x00, 0x36) ++#define REG_SC_BK00_37_L _PK_L_(0x00, 0x37) ++#define REG_SC_BK00_37_H _PK_H_(0x00, 0x37) ++#define REG_SC_BK00_38_L _PK_L_(0x00, 0x38) ++#define REG_SC_BK00_38_H _PK_H_(0x00, 0x38) ++#define REG_SC_BK00_39_L _PK_L_(0x00, 0x39) ++#define REG_SC_BK00_39_H _PK_H_(0x00, 0x39) ++#define REG_SC_BK00_3A_L _PK_L_(0x00, 0x3A) ++#define REG_SC_BK00_3A_H _PK_H_(0x00, 0x3A) ++#define REG_SC_BK00_3B_L _PK_L_(0x00, 0x3B) ++#define REG_SC_BK00_3B_H _PK_H_(0x00, 0x3B) ++#define REG_SC_BK00_3C_L _PK_L_(0x00, 0x3C) ++#define REG_SC_BK00_3C_H _PK_H_(0x00, 0x3C) ++#define REG_SC_BK00_3D_L _PK_L_(0x00, 0x3D) ++#define REG_SC_BK00_3D_H _PK_H_(0x00, 0x3D) ++#define REG_SC_BK00_3E_L _PK_L_(0x00, 0x3E) ++#define REG_SC_BK00_3E_H _PK_H_(0x00, 0x3E) ++#define REG_SC_BK00_3F_L _PK_L_(0x00, 0x3F) ++#define REG_SC_BK00_3F_H _PK_H_(0x00, 0x3F) ++#define REG_SC_BK00_40_L _PK_L_(0x00, 0x40) ++#define REG_SC_BK00_40_H _PK_H_(0x00, 0x40) ++#define REG_SC_BK00_41_L _PK_L_(0x00, 0x41) ++#define REG_SC_BK00_41_H _PK_H_(0x00, 0x41) ++#define REG_SC_BK00_42_L _PK_L_(0x00, 0x42) ++#define REG_SC_BK00_42_H _PK_H_(0x00, 0x42) ++#define REG_SC_BK00_43_L _PK_L_(0x00, 0x43) ++#define REG_SC_BK00_43_H _PK_H_(0x00, 0x43) ++#define REG_SC_BK00_44_L _PK_L_(0x00, 0x44) ++#define REG_SC_BK00_44_H _PK_H_(0x00, 0x44) ++#define REG_SC_BK00_45_L _PK_L_(0x00, 0x45) ++#define REG_SC_BK00_45_H _PK_H_(0x00, 0x45) ++#define REG_SC_BK00_46_L _PK_L_(0x00, 0x46) ++#define REG_SC_BK00_46_H _PK_H_(0x00, 0x46) ++#define REG_SC_BK00_47_L _PK_L_(0x00, 0x47) ++#define REG_SC_BK00_47_H _PK_H_(0x00, 0x47) ++#define REG_SC_BK00_48_L _PK_L_(0x00, 0x48) ++#define REG_SC_BK00_48_H _PK_H_(0x00, 0x48) ++#define REG_SC_BK00_49_L _PK_L_(0x00, 0x49) ++#define REG_SC_BK00_49_H _PK_H_(0x00, 0x49) ++#define REG_SC_BK00_4A_L _PK_L_(0x00, 0x4A) ++#define REG_SC_BK00_4A_H _PK_H_(0x00, 0x4A) ++#define REG_SC_BK00_4B_L _PK_L_(0x00, 0x4B) ++#define REG_SC_BK00_4B_H _PK_H_(0x00, 0x4B) ++#define REG_SC_BK00_4C_L _PK_L_(0x00, 0x4C) ++#define REG_SC_BK00_4C_H _PK_H_(0x00, 0x4C) ++#define REG_SC_BK00_4D_L _PK_L_(0x00, 0x4D) ++#define REG_SC_BK00_4D_H _PK_H_(0x00, 0x4D) ++#define REG_SC_BK00_4E_L _PK_L_(0x00, 0x4E) ++#define REG_SC_BK00_4E_H _PK_H_(0x00, 0x4E) ++#define REG_SC_BK00_4F_L _PK_L_(0x00, 0x4F) ++#define REG_SC_BK00_4F_H _PK_H_(0x00, 0x4F) ++#define REG_SC_BK00_50_L _PK_L_(0x00, 0x50) ++#define REG_SC_BK00_50_H _PK_H_(0x00, 0x50) ++#define REG_SC_BK00_51_L _PK_L_(0x00, 0x51) ++#define REG_SC_BK00_51_H _PK_H_(0x00, 0x51) ++#define REG_SC_BK00_52_L _PK_L_(0x00, 0x52) ++#define REG_SC_BK00_52_H _PK_H_(0x00, 0x52) ++#define REG_SC_BK00_53_L _PK_L_(0x00, 0x53) ++#define REG_SC_BK00_53_H _PK_H_(0x00, 0x53) ++#define REG_SC_BK00_54_L _PK_L_(0x00, 0x54) ++#define REG_SC_BK00_54_H _PK_H_(0x00, 0x54) ++#define REG_SC_BK00_55_L _PK_L_(0x00, 0x55) ++#define REG_SC_BK00_55_H _PK_H_(0x00, 0x55) ++#define REG_SC_BK00_56_L _PK_L_(0x00, 0x56) ++#define REG_SC_BK00_56_H _PK_H_(0x00, 0x56) ++#define REG_SC_BK00_57_L _PK_L_(0x00, 0x57) ++#define REG_SC_BK00_57_H _PK_H_(0x00, 0x57) ++#define REG_SC_BK00_58_L _PK_L_(0x00, 0x58) ++#define REG_SC_BK00_58_H _PK_H_(0x00, 0x58) ++#define REG_SC_BK00_59_L _PK_L_(0x00, 0x59) ++#define REG_SC_BK00_59_H _PK_H_(0x00, 0x59) ++#define REG_SC_BK00_5A_L _PK_L_(0x00, 0x5A) ++#define REG_SC_BK00_5A_H _PK_H_(0x00, 0x5A) ++#define REG_SC_BK00_5B_L _PK_L_(0x00, 0x5B) ++#define REG_SC_BK00_5B_H _PK_H_(0x00, 0x5B) ++#define REG_SC_BK00_5C_L _PK_L_(0x00, 0x5C) ++#define REG_SC_BK00_5C_H _PK_H_(0x00, 0x5C) ++#define REG_SC_BK00_5D_L _PK_L_(0x00, 0x5D) ++#define REG_SC_BK00_5D_H _PK_H_(0x00, 0x5D) ++#define REG_SC_BK00_5E_L _PK_L_(0x00, 0x5E) ++#define REG_SC_BK00_5E_H _PK_H_(0x00, 0x5E) ++#define REG_SC_BK00_5F_L _PK_L_(0x00, 0x5F) ++#define REG_SC_BK00_5F_H _PK_H_(0x00, 0x5F) ++#define REG_SC_BK00_60_L _PK_L_(0x00, 0x60) ++#define REG_SC_BK00_60_H _PK_H_(0x00, 0x60) ++#define REG_SC_BK00_61_L _PK_L_(0x00, 0x61) ++#define REG_SC_BK00_61_H _PK_H_(0x00, 0x61) ++#define REG_SC_BK00_62_L _PK_L_(0x00, 0x62) ++#define REG_SC_BK00_62_H _PK_H_(0x00, 0x62) ++#define REG_SC_BK00_63_L _PK_L_(0x00, 0x63) ++#define REG_SC_BK00_63_H _PK_H_(0x00, 0x63) ++#define REG_SC_BK00_64_L _PK_L_(0x00, 0x64) ++#define REG_SC_BK00_64_H _PK_H_(0x00, 0x64) ++#define REG_SC_BK00_65_L _PK_L_(0x00, 0x65) ++#define REG_SC_BK00_65_H _PK_H_(0x00, 0x65) ++#define REG_SC_BK00_66_L _PK_L_(0x00, 0x66) ++#define REG_SC_BK00_66_H _PK_H_(0x00, 0x66) ++#define REG_SC_BK00_67_L _PK_L_(0x00, 0x67) ++#define REG_SC_BK00_67_H _PK_H_(0x00, 0x67) ++#define REG_SC_BK00_68_L _PK_L_(0x00, 0x68) ++#define REG_SC_BK00_68_H _PK_H_(0x00, 0x68) ++#define REG_SC_BK00_69_L _PK_L_(0x00, 0x69) ++#define REG_SC_BK00_69_H _PK_H_(0x00, 0x69) ++#define REG_SC_BK00_6A_L _PK_L_(0x00, 0x6A) ++#define REG_SC_BK00_6A_H _PK_H_(0x00, 0x6A) ++#define REG_SC_BK00_6B_L _PK_L_(0x00, 0x6B) ++#define REG_SC_BK00_6B_H _PK_H_(0x00, 0x6B) ++#define REG_SC_BK00_6C_L _PK_L_(0x00, 0x6C) ++#define REG_SC_BK00_6C_H _PK_H_(0x00, 0x6C) ++#define REG_SC_BK00_6D_L _PK_L_(0x00, 0x6D) ++#define REG_SC_BK00_6D_H _PK_H_(0x00, 0x6D) ++#define REG_SC_BK00_6E_L _PK_L_(0x00, 0x6E) ++#define REG_SC_BK00_6E_H _PK_H_(0x00, 0x6E) ++#define REG_SC_BK00_6F_L _PK_L_(0x00, 0x6F) ++#define REG_SC_BK00_6F_H _PK_H_(0x00, 0x6F) ++#define REG_SC_BK00_70_L _PK_L_(0x00, 0x70) ++#define REG_SC_BK00_70_H _PK_H_(0x00, 0x70) ++#define REG_SC_BK00_71_L _PK_L_(0x00, 0x71) ++#define REG_SC_BK00_71_H _PK_H_(0x00, 0x71) ++#define REG_SC_BK00_72_L _PK_L_(0x00, 0x72) ++#define REG_SC_BK00_72_H _PK_H_(0x00, 0x72) ++#define REG_SC_BK00_73_L _PK_L_(0x00, 0x73) ++#define REG_SC_BK00_73_H _PK_H_(0x00, 0x73) ++#define REG_SC_BK00_74_L _PK_L_(0x00, 0x74) ++#define REG_SC_BK00_74_H _PK_H_(0x00, 0x74) ++#define REG_SC_BK00_75_L _PK_L_(0x00, 0x75) ++#define REG_SC_BK00_75_H _PK_H_(0x00, 0x75) ++#define REG_SC_BK00_76_L _PK_L_(0x00, 0x76) ++#define REG_SC_BK00_76_H _PK_H_(0x00, 0x76) ++#define REG_SC_BK00_77_L _PK_L_(0x00, 0x77) ++#define REG_SC_BK00_77_H _PK_H_(0x00, 0x77) ++#define REG_SC_BK00_78_L _PK_L_(0x00, 0x78) ++#define REG_SC_BK00_78_H _PK_H_(0x00, 0x78) ++#define REG_SC_BK00_79_L _PK_L_(0x00, 0x79) ++#define REG_SC_BK00_79_H _PK_H_(0x00, 0x79) ++#define REG_SC_BK00_7A_L _PK_L_(0x00, 0x7A) ++#define REG_SC_BK00_7A_H _PK_H_(0x00, 0x7A) ++#define REG_SC_BK00_7B_L _PK_L_(0x00, 0x7B) ++#define REG_SC_BK00_7B_H _PK_H_(0x00, 0x7B) ++#define REG_SC_BK00_7C_L _PK_L_(0x00, 0x7C) ++#define REG_SC_BK00_7C_H _PK_H_(0x00, 0x7C) ++#define REG_SC_BK00_7D_L _PK_L_(0x00, 0x7D) ++#define REG_SC_BK00_7D_H _PK_H_(0x00, 0x7D) ++#define REG_SC_BK00_7E_L _PK_L_(0x00, 0x7E) ++#define REG_SC_BK00_7E_H _PK_H_(0x00, 0x7E) ++#define REG_SC_BK00_7F_L _PK_L_(0x00, 0x7F) ++#define REG_SC_BK00_7F_H _PK_H_(0x00, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK01_00_L _PK_L_(0x01, 0x00) ++#define REG_SC_BK01_00_H _PK_H_(0x01, 0x00) ++#define REG_SC_BK01_01_L _PK_L_(0x01, 0x01) ++#define REG_SC_BK01_01_H _PK_H_(0x01, 0x01) ++#define REG_SC_BK01_02_L _PK_L_(0x01, 0x02) ++#define REG_SC_BK01_02_H _PK_H_(0x01, 0x02) ++#define REG_SC_BK01_03_L _PK_L_(0x01, 0x03) ++#define REG_SC_BK01_03_H _PK_H_(0x01, 0x03) ++#define REG_SC_BK01_04_L _PK_L_(0x01, 0x04) ++#define REG_SC_BK01_04_H _PK_H_(0x01, 0x04) ++#define REG_SC_BK01_05_L _PK_L_(0x01, 0x05) ++#define REG_SC_BK01_05_H _PK_H_(0x01, 0x05) ++#define REG_SC_BK01_06_L _PK_L_(0x01, 0x06) ++#define REG_SC_BK01_06_H _PK_H_(0x01, 0x06) ++#define REG_SC_BK01_07_L _PK_L_(0x01, 0x07) ++#define REG_SC_BK01_07_H _PK_H_(0x01, 0x07) ++#define REG_SC_BK01_08_L _PK_L_(0x01, 0x08) ++#define REG_SC_BK01_08_H _PK_H_(0x01, 0x08) ++#define REG_SC_BK01_09_L _PK_L_(0x01, 0x09) ++#define REG_SC_BK01_09_H _PK_H_(0x01, 0x09) ++#define REG_SC_BK01_0A_L _PK_L_(0x01, 0x0A) ++#define REG_SC_BK01_0A_H _PK_H_(0x01, 0x0A) ++#define REG_SC_BK01_0B_L _PK_L_(0x01, 0x0B) ++#define REG_SC_BK01_0B_H _PK_H_(0x01, 0x0B) ++#define REG_SC_BK01_0C_L _PK_L_(0x01, 0x0C) ++#define REG_SC_BK01_0C_H _PK_H_(0x01, 0x0C) ++#define REG_SC_BK01_0D_L _PK_L_(0x01, 0x0D) ++#define REG_SC_BK01_0D_H _PK_H_(0x01, 0x0D) ++#define REG_SC_BK01_0E_L _PK_L_(0x01, 0x0E) ++#define REG_SC_BK01_0E_H _PK_H_(0x01, 0x0E) ++#define REG_SC_BK01_0F_L _PK_L_(0x01, 0x0F) ++#define REG_SC_BK01_0F_H _PK_H_(0x01, 0x0F) ++#define REG_SC_BK01_10_L _PK_L_(0x01, 0x10) ++#define REG_SC_BK01_10_H _PK_H_(0x01, 0x10) ++#define REG_SC_BK01_11_L _PK_L_(0x01, 0x11) ++#define REG_SC_BK01_11_H _PK_H_(0x01, 0x11) ++#define REG_SC_BK01_12_L _PK_L_(0x01, 0x12) ++#define REG_SC_BK01_12_H _PK_H_(0x01, 0x12) ++#define REG_SC_BK01_13_L _PK_L_(0x01, 0x13) ++#define REG_SC_BK01_13_H _PK_H_(0x01, 0x13) ++#define REG_SC_BK01_14_L _PK_L_(0x01, 0x14) ++#define REG_SC_BK01_14_H _PK_H_(0x01, 0x14) ++#define REG_SC_BK01_15_L _PK_L_(0x01, 0x15) ++#define REG_SC_BK01_15_H _PK_H_(0x01, 0x15) ++#define REG_SC_BK01_16_L _PK_L_(0x01, 0x16) ++#define REG_SC_BK01_16_H _PK_H_(0x01, 0x16) ++#define REG_SC_BK01_17_L _PK_L_(0x01, 0x17) ++#define REG_SC_BK01_17_H _PK_H_(0x01, 0x17) ++#define REG_SC_BK01_18_L _PK_L_(0x01, 0x18) ++#define REG_SC_BK01_18_H _PK_H_(0x01, 0x18) ++#define REG_SC_BK01_19_L _PK_L_(0x01, 0x19) ++#define REG_SC_BK01_19_H _PK_H_(0x01, 0x19) ++#define REG_SC_BK01_1A_L _PK_L_(0x01, 0x1A) ++#define REG_SC_BK01_1A_H _PK_H_(0x01, 0x1A) ++#define REG_SC_BK01_1B_L _PK_L_(0x01, 0x1B) ++#define REG_SC_BK01_1B_H _PK_H_(0x01, 0x1B) ++#define REG_SC_BK01_1C_L _PK_L_(0x01, 0x1C) ++#define REG_SC_BK01_1C_H _PK_H_(0x01, 0x1C) ++#define REG_SC_BK01_1D_L _PK_L_(0x01, 0x1D) ++#define REG_SC_BK01_1D_H _PK_H_(0x01, 0x1D) ++#define REG_SC_BK01_1E_L _PK_L_(0x01, 0x1E) ++#define REG_SC_BK01_1E_H _PK_H_(0x01, 0x1E) ++#define REG_SC_BK01_1F_L _PK_L_(0x01, 0x1F) ++#define REG_SC_BK01_1F_H _PK_H_(0x01, 0x1F) ++#define REG_SC_BK01_20_L _PK_L_(0x01, 0x20) ++#define REG_SC_BK01_20_H _PK_H_(0x01, 0x20) ++#define REG_SC_BK01_21_L _PK_L_(0x01, 0x21) ++#define REG_SC_BK01_21_H _PK_H_(0x01, 0x21) ++#define REG_SC_BK01_22_L _PK_L_(0x01, 0x22) ++#define REG_SC_BK01_22_H _PK_H_(0x01, 0x22) ++#define REG_SC_BK01_23_L _PK_L_(0x01, 0x23) ++#define REG_SC_BK01_23_H _PK_H_(0x01, 0x23) ++#define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) ++#define REG_SC_BK01_24_H _PK_H_(0x01, 0x24) ++#define REG_SC_BK01_25_L _PK_L_(0x01, 0x25) ++#define REG_SC_BK01_25_H _PK_H_(0x01, 0x25) ++#define REG_SC_BK01_26_L _PK_L_(0x01, 0x26) ++#define REG_SC_BK01_26_H _PK_H_(0x01, 0x26) ++#define REG_SC_BK01_27_L _PK_L_(0x01, 0x27) ++#define REG_SC_BK01_27_H _PK_H_(0x01, 0x27) ++#define REG_SC_BK01_28_L _PK_L_(0x01, 0x28) ++#define REG_SC_BK01_28_H _PK_H_(0x01, 0x28) ++#define REG_SC_BK01_29_L _PK_L_(0x01, 0x29) ++#define REG_SC_BK01_29_H _PK_H_(0x01, 0x29) ++#define REG_SC_BK01_2A_L _PK_L_(0x01, 0x2A) ++#define REG_SC_BK01_2A_H _PK_H_(0x01, 0x2A) ++#define REG_SC_BK01_2B_L _PK_L_(0x01, 0x2B) ++#define REG_SC_BK01_2B_H _PK_H_(0x01, 0x2B) ++#define REG_SC_BK01_2C_L _PK_L_(0x01, 0x2C) ++#define REG_SC_BK01_2C_H _PK_H_(0x01, 0x2C) ++#define REG_SC_BK01_2D_L _PK_L_(0x01, 0x2D) ++#define REG_SC_BK01_2D_H _PK_H_(0x01, 0x2D) ++#define REG_SC_BK01_2E_L _PK_L_(0x01, 0x2E) ++#define REG_SC_BK01_2E_H _PK_H_(0x01, 0x2E) ++#define REG_SC_BK01_2F_L _PK_L_(0x01, 0x2F) ++#define REG_SC_BK01_2F_H _PK_H_(0x01, 0x2F) ++#define REG_SC_BK01_30_L _PK_L_(0x01, 0x30) ++#define REG_SC_BK01_30_H _PK_H_(0x01, 0x30) ++#define REG_SC_BK01_31_L _PK_L_(0x01, 0x31) ++#define REG_SC_BK01_31_H _PK_H_(0x01, 0x31) ++#define REG_SC_BK01_32_L _PK_L_(0x01, 0x32) ++#define REG_SC_BK01_32_H _PK_H_(0x01, 0x32) ++#define REG_SC_BK01_33_L _PK_L_(0x01, 0x33) ++#define REG_SC_BK01_33_H _PK_H_(0x01, 0x33) ++#define REG_SC_BK01_34_L _PK_L_(0x01, 0x34) ++#define REG_SC_BK01_34_H _PK_H_(0x01, 0x34) ++#define REG_SC_BK01_35_L _PK_L_(0x01, 0x35) ++#define REG_SC_BK01_35_H _PK_H_(0x01, 0x35) ++#define REG_SC_BK01_36_L _PK_L_(0x01, 0x36) ++#define REG_SC_BK01_36_H _PK_H_(0x01, 0x36) ++#define REG_SC_BK01_37_L _PK_L_(0x01, 0x37) ++#define REG_SC_BK01_37_H _PK_H_(0x01, 0x37) ++#define REG_SC_BK01_38_L _PK_L_(0x01, 0x38) ++#define REG_SC_BK01_38_H _PK_H_(0x01, 0x38) ++#define REG_SC_BK01_39_L _PK_L_(0x01, 0x39) ++#define REG_SC_BK01_39_H _PK_H_(0x01, 0x39) ++#define REG_SC_BK01_3A_L _PK_L_(0x01, 0x3A) ++#define REG_SC_BK01_3A_H _PK_H_(0x01, 0x3A) ++#define REG_SC_BK01_3B_L _PK_L_(0x01, 0x3B) ++#define REG_SC_BK01_3B_H _PK_H_(0x01, 0x3B) ++#define REG_SC_BK01_3C_L _PK_L_(0x01, 0x3C) ++#define REG_SC_BK01_3C_H _PK_H_(0x01, 0x3C) ++#define REG_SC_BK01_3D_L _PK_L_(0x01, 0x3D) ++#define REG_SC_BK01_3D_H _PK_H_(0x01, 0x3D) ++#define REG_SC_BK01_3E_L _PK_L_(0x01, 0x3E) ++#define REG_SC_BK01_3E_H _PK_H_(0x01, 0x3E) ++#define REG_SC_BK01_3F_L _PK_L_(0x01, 0x3F) ++#define REG_SC_BK01_3F_H _PK_H_(0x01, 0x3F) ++#define REG_SC_BK01_40_L _PK_L_(0x01, 0x40) ++#define REG_SC_BK01_40_H _PK_H_(0x01, 0x40) ++#define REG_SC_BK01_41_L _PK_L_(0x01, 0x41) ++#define REG_SC_BK01_41_H _PK_H_(0x01, 0x41) ++#define REG_SC_BK01_42_L _PK_L_(0x01, 0x42) ++#define REG_SC_BK01_42_H _PK_H_(0x01, 0x42) ++#define REG_SC_BK01_43_L _PK_L_(0x01, 0x43) ++#define REG_SC_BK01_43_H _PK_H_(0x01, 0x43) ++#define REG_SC_BK01_44_L _PK_L_(0x01, 0x44) ++#define REG_SC_BK01_44_H _PK_H_(0x01, 0x44) ++#define REG_SC_BK01_45_L _PK_L_(0x01, 0x45) ++#define REG_SC_BK01_45_H _PK_H_(0x01, 0x45) ++#define REG_SC_BK01_46_L _PK_L_(0x01, 0x46) ++#define REG_SC_BK01_46_H _PK_H_(0x01, 0x46) ++#define REG_SC_BK01_47_L _PK_L_(0x01, 0x47) ++#define REG_SC_BK01_47_H _PK_H_(0x01, 0x47) ++#define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) ++#define REG_SC_BK01_48_H _PK_H_(0x01, 0x48) ++#define REG_SC_BK01_49_L _PK_L_(0x01, 0x49) ++#define REG_SC_BK01_49_H _PK_H_(0x01, 0x49) ++#define REG_SC_BK01_4A_L _PK_L_(0x01, 0x4A) ++#define REG_SC_BK01_4A_H _PK_H_(0x01, 0x4A) ++#define REG_SC_BK01_4B_L _PK_L_(0x01, 0x4B) ++#define REG_SC_BK01_4B_H _PK_H_(0x01, 0x4B) ++#define REG_SC_BK01_4C_L _PK_L_(0x01, 0x4C) ++#define REG_SC_BK01_4C_H _PK_H_(0x01, 0x4C) ++#define REG_SC_BK01_4D_L _PK_L_(0x01, 0x4D) ++#define REG_SC_BK01_4D_H _PK_H_(0x01, 0x4D) ++#define REG_SC_BK01_4E_L _PK_L_(0x01, 0x4E) ++#define REG_SC_BK01_4E_H _PK_H_(0x01, 0x4E) ++#define REG_SC_BK01_4F_L _PK_L_(0x01, 0x4F) ++#define REG_SC_BK01_4F_H _PK_H_(0x01, 0x4F) ++#define REG_SC_BK01_50_L _PK_L_(0x01, 0x50) ++#define REG_SC_BK01_50_H _PK_H_(0x01, 0x50) ++#define REG_SC_BK01_51_L _PK_L_(0x01, 0x51) ++#define REG_SC_BK01_51_H _PK_H_(0x01, 0x51) ++#define REG_SC_BK01_52_L _PK_L_(0x01, 0x52) ++#define REG_SC_BK01_52_H _PK_H_(0x01, 0x52) ++#define REG_SC_BK01_53_L _PK_L_(0x01, 0x53) ++#define REG_SC_BK01_53_H _PK_H_(0x01, 0x53) ++#define REG_SC_BK01_54_L _PK_L_(0x01, 0x54) ++#define REG_SC_BK01_54_H _PK_H_(0x01, 0x54) ++#define REG_SC_BK01_55_L _PK_L_(0x01, 0x55) ++#define REG_SC_BK01_55_H _PK_H_(0x01, 0x55) ++#define REG_SC_BK01_56_L _PK_L_(0x01, 0x56) ++#define REG_SC_BK01_56_H _PK_H_(0x01, 0x56) ++#define REG_SC_BK01_57_L _PK_L_(0x01, 0x57) ++#define REG_SC_BK01_57_H _PK_H_(0x01, 0x57) ++#define REG_SC_BK01_58_L _PK_L_(0x01, 0x58) ++#define REG_SC_BK01_58_H _PK_H_(0x01, 0x58) ++#define REG_SC_BK01_59_L _PK_L_(0x01, 0x59) ++#define REG_SC_BK01_59_H _PK_H_(0x01, 0x59) ++#define REG_SC_BK01_5A_L _PK_L_(0x01, 0x5A) ++#define REG_SC_BK01_5A_H _PK_H_(0x01, 0x5A) ++#define REG_SC_BK01_5B_L _PK_L_(0x01, 0x5B) ++#define REG_SC_BK01_5B_H _PK_H_(0x01, 0x5B) ++#define REG_SC_BK01_5C_L _PK_L_(0x01, 0x5C) ++#define REG_SC_BK01_5C_H _PK_H_(0x01, 0x5C) ++#define REG_SC_BK01_5D_L _PK_L_(0x01, 0x5D) ++#define REG_SC_BK01_5D_H _PK_H_(0x01, 0x5D) ++#define REG_SC_BK01_5E_L _PK_L_(0x01, 0x5E) ++#define REG_SC_BK01_5E_H _PK_H_(0x01, 0x5E) ++#define REG_SC_BK01_5F_L _PK_L_(0x01, 0x5F) ++#define REG_SC_BK01_5F_H _PK_H_(0x01, 0x5F) ++#define REG_SC_BK01_60_L _PK_L_(0x01, 0x60) ++#define REG_SC_BK01_60_H _PK_H_(0x01, 0x60) ++#define REG_SC_BK01_61_L _PK_L_(0x01, 0x61) ++#define REG_SC_BK01_61_H _PK_H_(0x01, 0x61) ++#define REG_SC_BK01_62_L _PK_L_(0x01, 0x62) ++#define REG_SC_BK01_62_H _PK_H_(0x01, 0x62) ++#define REG_SC_BK01_63_L _PK_L_(0x01, 0x63) ++#define REG_SC_BK01_63_H _PK_H_(0x01, 0x63) ++#define REG_SC_BK01_64_L _PK_L_(0x01, 0x64) ++#define REG_SC_BK01_64_H _PK_H_(0x01, 0x64) ++#define REG_SC_BK01_65_L _PK_L_(0x01, 0x65) ++#define REG_SC_BK01_65_H _PK_H_(0x01, 0x65) ++#define REG_SC_BK01_66_L _PK_L_(0x01, 0x66) ++#define REG_SC_BK01_66_H _PK_H_(0x01, 0x66) ++#define REG_SC_BK01_67_L _PK_L_(0x01, 0x67) ++#define REG_SC_BK01_67_H _PK_H_(0x01, 0x67) ++#define REG_SC_BK01_68_L _PK_L_(0x01, 0x68) ++#define REG_SC_BK01_68_H _PK_H_(0x01, 0x68) ++#define REG_SC_BK01_69_L _PK_L_(0x01, 0x69) ++#define REG_SC_BK01_69_H _PK_H_(0x01, 0x69) ++#define REG_SC_BK01_6A_L _PK_L_(0x01, 0x6A) ++#define REG_SC_BK01_6A_H _PK_H_(0x01, 0x6A) ++#define REG_SC_BK01_6B_L _PK_L_(0x01, 0x6B) ++#define REG_SC_BK01_6B_H _PK_H_(0x01, 0x6B) ++#define REG_SC_BK01_6C_L _PK_L_(0x01, 0x6C) ++#define REG_SC_BK01_6C_H _PK_H_(0x01, 0x6C) ++#define REG_SC_BK01_6D_L _PK_L_(0x01, 0x6D) ++#define REG_SC_BK01_6D_H _PK_H_(0x01, 0x6D) ++#define REG_SC_BK01_6E_L _PK_L_(0x01, 0x6E) ++#define REG_SC_BK01_6E_H _PK_H_(0x01, 0x6E) ++#define REG_SC_BK01_6F_L _PK_L_(0x01, 0x6F) ++#define REG_SC_BK01_6F_H _PK_H_(0x01, 0x6F) ++#define REG_SC_BK01_70_L _PK_L_(0x01, 0x70) ++#define REG_SC_BK01_70_H _PK_H_(0x01, 0x70) ++#define REG_SC_BK01_71_L _PK_L_(0x01, 0x71) ++#define REG_SC_BK01_71_H _PK_H_(0x01, 0x71) ++#define REG_SC_BK01_72_L _PK_L_(0x01, 0x72) ++#define REG_SC_BK01_72_H _PK_H_(0x01, 0x72) ++#define REG_SC_BK01_73_L _PK_L_(0x01, 0x73) ++#define REG_SC_BK01_73_H _PK_H_(0x01, 0x73) ++#define REG_SC_BK01_74_L _PK_L_(0x01, 0x74) ++#define REG_SC_BK01_74_H _PK_H_(0x01, 0x74) ++#define REG_SC_BK01_75_L _PK_L_(0x01, 0x75) ++#define REG_SC_BK01_75_H _PK_H_(0x01, 0x75) ++#define REG_SC_BK01_76_L _PK_L_(0x01, 0x76) ++#define REG_SC_BK01_76_H _PK_H_(0x01, 0x76) ++#define REG_SC_BK01_77_L _PK_L_(0x01, 0x77) ++#define REG_SC_BK01_77_H _PK_H_(0x01, 0x77) ++#define REG_SC_BK01_78_L _PK_L_(0x01, 0x78) ++#define REG_SC_BK01_78_H _PK_H_(0x01, 0x78) ++#define REG_SC_BK01_79_L _PK_L_(0x01, 0x79) ++#define REG_SC_BK01_79_H _PK_H_(0x01, 0x79) ++#define REG_SC_BK01_7A_L _PK_L_(0x01, 0x7A) ++#define REG_SC_BK01_7A_H _PK_H_(0x01, 0x7A) ++#define REG_SC_BK01_7B_L _PK_L_(0x01, 0x7B) ++#define REG_SC_BK01_7B_H _PK_H_(0x01, 0x7B) ++#define REG_SC_BK01_7C_L _PK_L_(0x01, 0x7C) ++#define REG_SC_BK01_7C_H _PK_H_(0x01, 0x7C) ++#define REG_SC_BK01_7D_L _PK_L_(0x01, 0x7D) ++#define REG_SC_BK01_7D_H _PK_H_(0x01, 0x7D) ++#define REG_SC_BK01_7E_L _PK_L_(0x01, 0x7E) ++#define REG_SC_BK01_7E_H _PK_H_(0x01, 0x7E) ++#define REG_SC_BK01_7F_L _PK_L_(0x01, 0x7F) ++#define REG_SC_BK01_7F_H _PK_H_(0x01, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK02_00_L _PK_L_(0x02, 0x00) ++#define REG_SC_BK02_00_H _PK_H_(0x02, 0x00) ++#define REG_SC_BK02_01_L _PK_L_(0x02, 0x01) ++#define REG_SC_BK02_01_H _PK_H_(0x02, 0x01) ++#define REG_SC_BK02_02_L _PK_L_(0x02, 0x02) ++#define REG_SC_BK02_02_H _PK_H_(0x02, 0x02) ++#define REG_SC_BK02_03_L _PK_L_(0x02, 0x03) ++#define REG_SC_BK02_03_H _PK_H_(0x02, 0x03) ++#define REG_SC_BK02_04_L _PK_L_(0x02, 0x04) ++#define REG_SC_BK02_04_H _PK_H_(0x02, 0x04) ++#define REG_SC_BK02_05_L _PK_L_(0x02, 0x05) ++#define REG_SC_BK02_05_H _PK_H_(0x02, 0x05) ++#define REG_SC_BK02_06_L _PK_L_(0x02, 0x06) ++#define REG_SC_BK02_06_H _PK_H_(0x02, 0x06) ++#define REG_SC_BK02_07_L _PK_L_(0x02, 0x07) ++#define REG_SC_BK02_07_H _PK_H_(0x02, 0x07) ++#define REG_SC_BK02_08_L _PK_L_(0x02, 0x08) ++#define REG_SC_BK02_08_H _PK_H_(0x02, 0x08) ++#define REG_SC_BK02_09_L _PK_L_(0x02, 0x09) ++#define REG_SC_BK02_09_H _PK_H_(0x02, 0x09) ++#define REG_SC_BK02_0A_L _PK_L_(0x02, 0x0A) ++#define REG_SC_BK02_0A_H _PK_H_(0x02, 0x0A) ++#define REG_SC_BK02_0B_L _PK_L_(0x02, 0x0B) ++#define REG_SC_BK02_0B_H _PK_H_(0x02, 0x0B) ++#define REG_SC_BK02_0C_L _PK_L_(0x02, 0x0C) ++#define REG_SC_BK02_0C_H _PK_H_(0x02, 0x0C) ++#define REG_SC_BK02_0D_L _PK_L_(0x02, 0x0D) ++#define REG_SC_BK02_0D_H _PK_H_(0x02, 0x0D) ++#define REG_SC_BK02_0E_L _PK_L_(0x02, 0x0E) ++#define REG_SC_BK02_0E_H _PK_H_(0x02, 0x0E) ++#define REG_SC_BK02_0F_L _PK_L_(0x02, 0x0F) ++#define REG_SC_BK02_0F_H _PK_H_(0x02, 0x0F) ++#define REG_SC_BK02_10_L _PK_L_(0x02, 0x10) ++#define REG_SC_BK02_10_H _PK_H_(0x02, 0x10) ++#define REG_SC_BK02_11_L _PK_L_(0x02, 0x11) ++#define REG_SC_BK02_11_H _PK_H_(0x02, 0x11) ++#define REG_SC_BK02_12_L _PK_L_(0x02, 0x12) ++#define REG_SC_BK02_12_H _PK_H_(0x02, 0x12) ++#define REG_SC_BK02_13_L _PK_L_(0x02, 0x13) ++#define REG_SC_BK02_13_H _PK_H_(0x02, 0x13) ++#define REG_SC_BK02_14_L _PK_L_(0x02, 0x14) ++#define REG_SC_BK02_14_H _PK_H_(0x02, 0x14) ++#define REG_SC_BK02_15_L _PK_L_(0x02, 0x15) ++#define REG_SC_BK02_15_H _PK_H_(0x02, 0x15) ++#define REG_SC_BK02_16_L _PK_L_(0x02, 0x16) ++#define REG_SC_BK02_16_H _PK_H_(0x02, 0x16) ++#define REG_SC_BK02_17_L _PK_L_(0x02, 0x17) ++#define REG_SC_BK02_17_H _PK_H_(0x02, 0x17) ++#define REG_SC_BK02_18_L _PK_L_(0x02, 0x18) ++#define REG_SC_BK02_18_H _PK_H_(0x02, 0x18) ++#define REG_SC_BK02_19_L _PK_L_(0x02, 0x19) ++#define REG_SC_BK02_19_H _PK_H_(0x02, 0x19) ++#define REG_SC_BK02_1A_L _PK_L_(0x02, 0x1A) ++#define REG_SC_BK02_1A_H _PK_H_(0x02, 0x1A) ++#define REG_SC_BK02_1B_L _PK_L_(0x02, 0x1B) ++#define REG_SC_BK02_1B_H _PK_H_(0x02, 0x1B) ++#define REG_SC_BK02_1C_L _PK_L_(0x02, 0x1C) ++#define REG_SC_BK02_1C_H _PK_H_(0x02, 0x1C) ++#define REG_SC_BK02_1D_L _PK_L_(0x02, 0x1D) ++#define REG_SC_BK02_1D_H _PK_H_(0x02, 0x1D) ++#define REG_SC_BK02_1E_L _PK_L_(0x02, 0x1E) ++#define REG_SC_BK02_1E_H _PK_H_(0x02, 0x1E) ++#define REG_SC_BK02_1F_L _PK_L_(0x02, 0x1F) ++#define REG_SC_BK02_1F_H _PK_H_(0x02, 0x1F) ++#define REG_SC_BK02_20_L _PK_L_(0x02, 0x20) ++#define REG_SC_BK02_20_H _PK_H_(0x02, 0x20) ++#define REG_SC_BK02_21_L _PK_L_(0x02, 0x21) ++#define REG_SC_BK02_21_H _PK_H_(0x02, 0x21) ++#define REG_SC_BK02_22_L _PK_L_(0x02, 0x22) ++#define REG_SC_BK02_22_H _PK_H_(0x02, 0x22) ++#define REG_SC_BK02_23_L _PK_L_(0x02, 0x23) ++#define REG_SC_BK02_23_H _PK_H_(0x02, 0x23) ++#define REG_SC_BK02_24_L _PK_L_(0x02, 0x24) ++#define REG_SC_BK02_24_H _PK_H_(0x02, 0x24) ++#define REG_SC_BK02_25_L _PK_L_(0x02, 0x25) ++#define REG_SC_BK02_25_H _PK_H_(0x02, 0x25) ++#define REG_SC_BK02_26_L _PK_L_(0x02, 0x26) ++#define REG_SC_BK02_26_H _PK_H_(0x02, 0x26) ++#define REG_SC_BK02_27_L _PK_L_(0x02, 0x27) ++#define REG_SC_BK02_27_H _PK_H_(0x02, 0x27) ++#define REG_SC_BK02_28_L _PK_L_(0x02, 0x28) ++#define REG_SC_BK02_28_H _PK_H_(0x02, 0x28) ++#define REG_SC_BK02_29_L _PK_L_(0x02, 0x29) ++#define REG_SC_BK02_29_H _PK_H_(0x02, 0x29) ++#define REG_SC_BK02_2A_L _PK_L_(0x02, 0x2A) ++#define REG_SC_BK02_2A_H _PK_H_(0x02, 0x2A) ++#define REG_SC_BK02_2B_L _PK_L_(0x02, 0x2B) ++#define REG_SC_BK02_2B_H _PK_H_(0x02, 0x2B) ++#define REG_SC_BK02_2C_L _PK_L_(0x02, 0x2C) ++#define REG_SC_BK02_2C_H _PK_H_(0x02, 0x2C) ++#define REG_SC_BK02_2D_L _PK_L_(0x02, 0x2D) ++#define REG_SC_BK02_2D_H _PK_H_(0x02, 0x2D) ++#define REG_SC_BK02_2E_L _PK_L_(0x02, 0x2E) ++#define REG_SC_BK02_2E_H _PK_H_(0x02, 0x2E) ++#define REG_SC_BK02_2F_L _PK_L_(0x02, 0x2F) ++#define REG_SC_BK02_2F_H _PK_H_(0x02, 0x2F) ++#define REG_SC_BK02_30_L _PK_L_(0x02, 0x30) ++#define REG_SC_BK02_30_H _PK_H_(0x02, 0x30) ++#define REG_SC_BK02_31_L _PK_L_(0x02, 0x31) ++#define REG_SC_BK02_31_H _PK_H_(0x02, 0x31) ++#define REG_SC_BK02_32_L _PK_L_(0x02, 0x32) ++#define REG_SC_BK02_32_H _PK_H_(0x02, 0x32) ++#define REG_SC_BK02_33_L _PK_L_(0x02, 0x33) ++#define REG_SC_BK02_33_H _PK_H_(0x02, 0x33) ++#define REG_SC_BK02_34_L _PK_L_(0x02, 0x34) ++#define REG_SC_BK02_34_H _PK_H_(0x02, 0x34) ++#define REG_SC_BK02_35_L _PK_L_(0x02, 0x35) ++#define REG_SC_BK02_35_H _PK_H_(0x02, 0x35) ++#define REG_SC_BK02_36_L _PK_L_(0x02, 0x36) ++#define REG_SC_BK02_36_H _PK_H_(0x02, 0x36) ++#define REG_SC_BK02_37_L _PK_L_(0x02, 0x37) ++#define REG_SC_BK02_37_H _PK_H_(0x02, 0x37) ++#define REG_SC_BK02_38_L _PK_L_(0x02, 0x38) ++#define REG_SC_BK02_38_H _PK_H_(0x02, 0x38) ++#define REG_SC_BK02_39_L _PK_L_(0x02, 0x39) ++#define REG_SC_BK02_39_H _PK_H_(0x02, 0x39) ++#define REG_SC_BK02_3A_L _PK_L_(0x02, 0x3A) ++#define REG_SC_BK02_3A_H _PK_H_(0x02, 0x3A) ++#define REG_SC_BK02_3B_L _PK_L_(0x02, 0x3B) ++#define REG_SC_BK02_3B_H _PK_H_(0x02, 0x3B) ++#define REG_SC_BK02_3C_L _PK_L_(0x02, 0x3C) ++#define REG_SC_BK02_3C_H _PK_H_(0x02, 0x3C) ++#define REG_SC_BK02_3D_L _PK_L_(0x02, 0x3D) ++#define REG_SC_BK02_3D_H _PK_H_(0x02, 0x3D) ++#define REG_SC_BK02_3E_L _PK_L_(0x02, 0x3E) ++#define REG_SC_BK02_3E_H _PK_H_(0x02, 0x3E) ++#define REG_SC_BK02_3F_L _PK_L_(0x02, 0x3F) ++#define REG_SC_BK02_3F_H _PK_H_(0x02, 0x3F) ++#define REG_SC_BK02_40_L _PK_L_(0x02, 0x40) ++#define REG_SC_BK02_40_H _PK_H_(0x02, 0x40) ++#define REG_SC_BK02_41_L _PK_L_(0x02, 0x41) ++#define REG_SC_BK02_41_H _PK_H_(0x02, 0x41) ++#define REG_SC_BK02_42_L _PK_L_(0x02, 0x42) ++#define REG_SC_BK02_42_H _PK_H_(0x02, 0x42) ++#define REG_SC_BK02_43_L _PK_L_(0x02, 0x43) ++#define REG_SC_BK02_43_H _PK_H_(0x02, 0x43) ++#define REG_SC_BK02_44_L _PK_L_(0x02, 0x44) ++#define REG_SC_BK02_44_H _PK_H_(0x02, 0x44) ++#define REG_SC_BK02_45_L _PK_L_(0x02, 0x45) ++#define REG_SC_BK02_45_H _PK_H_(0x02, 0x45) ++#define REG_SC_BK02_46_L _PK_L_(0x02, 0x46) ++#define REG_SC_BK02_46_H _PK_H_(0x02, 0x46) ++#define REG_SC_BK02_47_L _PK_L_(0x02, 0x47) ++#define REG_SC_BK02_47_H _PK_H_(0x02, 0x47) ++#define REG_SC_BK02_48_L _PK_L_(0x02, 0x48) ++#define REG_SC_BK02_48_H _PK_H_(0x02, 0x48) ++#define REG_SC_BK02_49_L _PK_L_(0x02, 0x49) ++#define REG_SC_BK02_49_H _PK_H_(0x02, 0x49) ++#define REG_SC_BK02_4A_L _PK_L_(0x02, 0x4A) ++#define REG_SC_BK02_4A_H _PK_H_(0x02, 0x4A) ++#define REG_SC_BK02_4B_L _PK_L_(0x02, 0x4B) ++#define REG_SC_BK02_4B_H _PK_H_(0x02, 0x4B) ++#define REG_SC_BK02_4C_L _PK_L_(0x02, 0x4C) ++#define REG_SC_BK02_4C_H _PK_H_(0x02, 0x4C) ++#define REG_SC_BK02_4D_L _PK_L_(0x02, 0x4D) ++#define REG_SC_BK02_4D_H _PK_H_(0x02, 0x4D) ++#define REG_SC_BK02_4E_L _PK_L_(0x02, 0x4E) ++#define REG_SC_BK02_4E_H _PK_H_(0x02, 0x4E) ++#define REG_SC_BK02_4F_L _PK_L_(0x02, 0x4F) ++#define REG_SC_BK02_4F_H _PK_H_(0x02, 0x4F) ++#define REG_SC_BK02_50_L _PK_L_(0x02, 0x50) ++#define REG_SC_BK02_50_H _PK_H_(0x02, 0x50) ++#define REG_SC_BK02_51_L _PK_L_(0x02, 0x51) ++#define REG_SC_BK02_51_H _PK_H_(0x02, 0x51) ++#define REG_SC_BK02_52_L _PK_L_(0x02, 0x52) ++#define REG_SC_BK02_52_H _PK_H_(0x02, 0x52) ++#define REG_SC_BK02_53_L _PK_L_(0x02, 0x53) ++#define REG_SC_BK02_53_H _PK_H_(0x02, 0x53) ++#define REG_SC_BK02_54_L _PK_L_(0x02, 0x54) ++#define REG_SC_BK02_54_H _PK_H_(0x02, 0x54) ++#define REG_SC_BK02_55_L _PK_L_(0x02, 0x55) ++#define REG_SC_BK02_55_H _PK_H_(0x02, 0x55) ++#define REG_SC_BK02_56_L _PK_L_(0x02, 0x56) ++#define REG_SC_BK02_56_H _PK_H_(0x02, 0x56) ++#define REG_SC_BK02_57_L _PK_L_(0x02, 0x57) ++#define REG_SC_BK02_57_H _PK_H_(0x02, 0x57) ++#define REG_SC_BK02_58_L _PK_L_(0x02, 0x58) ++#define REG_SC_BK02_58_H _PK_H_(0x02, 0x58) ++#define REG_SC_BK02_59_L _PK_L_(0x02, 0x59) ++#define REG_SC_BK02_59_H _PK_H_(0x02, 0x59) ++#define REG_SC_BK02_5A_L _PK_L_(0x02, 0x5A) ++#define REG_SC_BK02_5A_H _PK_H_(0x02, 0x5A) ++#define REG_SC_BK02_5B_L _PK_L_(0x02, 0x5B) ++#define REG_SC_BK02_5B_H _PK_H_(0x02, 0x5B) ++#define REG_SC_BK02_5C_L _PK_L_(0x02, 0x5C) ++#define REG_SC_BK02_5C_H _PK_H_(0x02, 0x5C) ++#define REG_SC_BK02_5D_L _PK_L_(0x02, 0x5D) ++#define REG_SC_BK02_5D_H _PK_H_(0x02, 0x5D) ++#define REG_SC_BK02_5E_L _PK_L_(0x02, 0x5E) ++#define REG_SC_BK02_5E_H _PK_H_(0x02, 0x5E) ++#define REG_SC_BK02_5F_L _PK_L_(0x02, 0x5F) ++#define REG_SC_BK02_5F_H _PK_H_(0x02, 0x5F) ++#define REG_SC_BK02_60_L _PK_L_(0x02, 0x60) ++#define REG_SC_BK02_60_H _PK_H_(0x02, 0x60) ++#define REG_SC_BK02_61_L _PK_L_(0x02, 0x61) ++#define REG_SC_BK02_61_H _PK_H_(0x02, 0x61) ++#define REG_SC_BK02_62_L _PK_L_(0x02, 0x62) ++#define REG_SC_BK02_62_H _PK_H_(0x02, 0x62) ++#define REG_SC_BK02_63_L _PK_L_(0x02, 0x63) ++#define REG_SC_BK02_63_H _PK_H_(0x02, 0x63) ++#define REG_SC_BK02_64_L _PK_L_(0x02, 0x64) ++#define REG_SC_BK02_64_H _PK_H_(0x02, 0x64) ++#define REG_SC_BK02_65_L _PK_L_(0x02, 0x65) ++#define REG_SC_BK02_65_H _PK_H_(0x02, 0x65) ++#define REG_SC_BK02_66_L _PK_L_(0x02, 0x66) ++#define REG_SC_BK02_66_H _PK_H_(0x02, 0x66) ++#define REG_SC_BK02_67_L _PK_L_(0x02, 0x67) ++#define REG_SC_BK02_67_H _PK_H_(0x02, 0x67) ++#define REG_SC_BK02_68_L _PK_L_(0x02, 0x68) ++#define REG_SC_BK02_68_H _PK_H_(0x02, 0x68) ++#define REG_SC_BK02_69_L _PK_L_(0x02, 0x69) ++#define REG_SC_BK02_69_H _PK_H_(0x02, 0x69) ++#define REG_SC_BK02_6A_L _PK_L_(0x02, 0x6A) ++#define REG_SC_BK02_6A_H _PK_H_(0x02, 0x6A) ++#define REG_SC_BK02_6B_L _PK_L_(0x02, 0x6B) ++#define REG_SC_BK02_6B_H _PK_H_(0x02, 0x6B) ++#define REG_SC_BK02_6C_L _PK_L_(0x02, 0x6C) ++#define REG_SC_BK02_6C_H _PK_H_(0x02, 0x6C) ++#define REG_SC_BK02_6D_L _PK_L_(0x02, 0x6D) ++#define REG_SC_BK02_6D_H _PK_H_(0x02, 0x6D) ++#define REG_SC_BK02_6E_L _PK_L_(0x02, 0x6E) ++#define REG_SC_BK02_6E_H _PK_H_(0x02, 0x6E) ++#define REG_SC_BK02_6F_L _PK_L_(0x02, 0x6F) ++#define REG_SC_BK02_6F_H _PK_H_(0x02, 0x6F) ++#define REG_SC_BK02_70_L _PK_L_(0x02, 0x70) ++#define REG_SC_BK02_70_H _PK_H_(0x02, 0x70) ++#define REG_SC_BK02_71_L _PK_L_(0x02, 0x71) ++#define REG_SC_BK02_71_H _PK_H_(0x02, 0x71) ++#define REG_SC_BK02_72_L _PK_L_(0x02, 0x72) ++#define REG_SC_BK02_72_H _PK_H_(0x02, 0x72) ++#define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) ++#define REG_SC_BK02_73_H _PK_H_(0x02, 0x73) ++#define REG_SC_BK02_74_L _PK_L_(0x02, 0x74) ++#define REG_SC_BK02_74_H _PK_H_(0x02, 0x74) ++#define REG_SC_BK02_75_L _PK_L_(0x02, 0x75) ++#define REG_SC_BK02_75_H _PK_H_(0x02, 0x75) ++#define REG_SC_BK02_76_L _PK_L_(0x02, 0x76) ++#define REG_SC_BK02_76_H _PK_H_(0x02, 0x76) ++#define REG_SC_BK02_77_L _PK_L_(0x02, 0x77) ++#define REG_SC_BK02_77_H _PK_H_(0x02, 0x77) ++#define REG_SC_BK02_78_L _PK_L_(0x02, 0x78) ++#define REG_SC_BK02_78_H _PK_H_(0x02, 0x78) ++#define REG_SC_BK02_79_L _PK_L_(0x02, 0x79) ++#define REG_SC_BK02_79_H _PK_H_(0x02, 0x79) ++#define REG_SC_BK02_7A_L _PK_L_(0x02, 0x7A) ++#define REG_SC_BK02_7A_H _PK_H_(0x02, 0x7A) ++#define REG_SC_BK02_7B_L _PK_L_(0x02, 0x7B) ++#define REG_SC_BK02_7B_H _PK_H_(0x02, 0x7B) ++#define REG_SC_BK02_7C_L _PK_L_(0x02, 0x7C) ++#define REG_SC_BK02_7C_H _PK_H_(0x02, 0x7C) ++#define REG_SC_BK02_7D_L _PK_L_(0x02, 0x7D) ++#define REG_SC_BK02_7D_H _PK_H_(0x02, 0x7D) ++#define REG_SC_BK02_7E_L _PK_L_(0x02, 0x7E) ++#define REG_SC_BK02_7E_H _PK_H_(0x02, 0x7E) ++#define REG_SC_BK02_7F_L _PK_L_(0x02, 0x7F) ++#define REG_SC_BK02_7F_H _PK_H_(0x02, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK03_00_L _PK_L_(0x03, 0x00) ++#define REG_SC_BK03_00_H _PK_H_(0x03, 0x00) ++#define REG_SC_BK03_01_L _PK_L_(0x03, 0x01) ++#define REG_SC_BK03_01_H _PK_H_(0x03, 0x01) ++#define REG_SC_BK03_02_L _PK_L_(0x03, 0x02) ++#define REG_SC_BK03_02_H _PK_H_(0x03, 0x02) ++#define REG_SC_BK03_03_L _PK_L_(0x03, 0x03) ++#define REG_SC_BK03_03_H _PK_H_(0x03, 0x03) ++#define REG_SC_BK03_04_L _PK_L_(0x03, 0x04) ++#define REG_SC_BK03_04_H _PK_H_(0x03, 0x04) ++#define REG_SC_BK03_05_L _PK_L_(0x03, 0x05) ++#define REG_SC_BK03_05_H _PK_H_(0x03, 0x05) ++#define REG_SC_BK03_06_L _PK_L_(0x03, 0x06) ++#define REG_SC_BK03_06_H _PK_H_(0x03, 0x06) ++#define REG_SC_BK03_07_L _PK_L_(0x03, 0x07) ++#define REG_SC_BK03_07_H _PK_H_(0x03, 0x07) ++#define REG_SC_BK03_08_L _PK_L_(0x03, 0x08) ++#define REG_SC_BK03_08_H _PK_H_(0x03, 0x08) ++#define REG_SC_BK03_09_L _PK_L_(0x03, 0x09) ++#define REG_SC_BK03_09_H _PK_H_(0x03, 0x09) ++#define REG_SC_BK03_0A_L _PK_L_(0x03, 0x0A) ++#define REG_SC_BK03_0A_H _PK_H_(0x03, 0x0A) ++#define REG_SC_BK03_0B_L _PK_L_(0x03, 0x0B) ++#define REG_SC_BK03_0B_H _PK_H_(0x03, 0x0B) ++#define REG_SC_BK03_0C_L _PK_L_(0x03, 0x0C) ++#define REG_SC_BK03_0C_H _PK_H_(0x03, 0x0C) ++#define REG_SC_BK03_0D_L _PK_L_(0x03, 0x0D) ++#define REG_SC_BK03_0D_H _PK_H_(0x03, 0x0D) ++#define REG_SC_BK03_0E_L _PK_L_(0x03, 0x0E) ++#define REG_SC_BK03_0E_H _PK_H_(0x03, 0x0E) ++#define REG_SC_BK03_0F_L _PK_L_(0x03, 0x0F) ++#define REG_SC_BK03_0F_H _PK_H_(0x03, 0x0F) ++#define REG_SC_BK03_10_L _PK_L_(0x03, 0x10) ++#define REG_SC_BK03_10_H _PK_H_(0x03, 0x10) ++#define REG_SC_BK03_11_L _PK_L_(0x03, 0x11) ++#define REG_SC_BK03_11_H _PK_H_(0x03, 0x11) ++#define REG_SC_BK03_12_L _PK_L_(0x03, 0x12) ++#define REG_SC_BK03_12_H _PK_H_(0x03, 0x12) ++#define REG_SC_BK03_13_L _PK_L_(0x03, 0x13) ++#define REG_SC_BK03_13_H _PK_H_(0x03, 0x13) ++#define REG_SC_BK03_14_L _PK_L_(0x03, 0x14) ++#define REG_SC_BK03_14_H _PK_H_(0x03, 0x14) ++#define REG_SC_BK03_15_L _PK_L_(0x03, 0x15) ++#define REG_SC_BK03_15_H _PK_H_(0x03, 0x15) ++#define REG_SC_BK03_16_L _PK_L_(0x03, 0x16) ++#define REG_SC_BK03_16_H _PK_H_(0x03, 0x16) ++#define REG_SC_BK03_17_L _PK_L_(0x03, 0x17) ++#define REG_SC_BK03_17_H _PK_H_(0x03, 0x17) ++#define REG_SC_BK03_18_L _PK_L_(0x03, 0x18) ++#define REG_SC_BK03_18_H _PK_H_(0x03, 0x18) ++#define REG_SC_BK03_19_L _PK_L_(0x03, 0x19) ++#define REG_SC_BK03_19_H _PK_H_(0x03, 0x19) ++#define REG_SC_BK03_1A_L _PK_L_(0x03, 0x1A) ++#define REG_SC_BK03_1A_H _PK_H_(0x03, 0x1A) ++#define REG_SC_BK03_1B_L _PK_L_(0x03, 0x1B) ++#define REG_SC_BK03_1B_H _PK_H_(0x03, 0x1B) ++#define REG_SC_BK03_1C_L _PK_L_(0x03, 0x1C) ++#define REG_SC_BK03_1C_H _PK_H_(0x03, 0x1C) ++#define REG_SC_BK03_1D_L _PK_L_(0x03, 0x1D) ++#define REG_SC_BK03_1D_H _PK_H_(0x03, 0x1D) ++#define REG_SC_BK03_1E_L _PK_L_(0x03, 0x1E) ++#define REG_SC_BK03_1E_H _PK_H_(0x03, 0x1E) ++#define REG_SC_BK03_1F_L _PK_L_(0x03, 0x1F) ++#define REG_SC_BK03_1F_H _PK_H_(0x03, 0x1F) ++#define REG_SC_BK03_20_L _PK_L_(0x03, 0x20) ++#define REG_SC_BK03_20_H _PK_H_(0x03, 0x20) ++#define REG_SC_BK03_21_L _PK_L_(0x03, 0x21) ++#define REG_SC_BK03_21_H _PK_H_(0x03, 0x21) ++#define REG_SC_BK03_22_L _PK_L_(0x03, 0x22) ++#define REG_SC_BK03_22_H _PK_H_(0x03, 0x22) ++#define REG_SC_BK03_23_L _PK_L_(0x03, 0x23) ++#define REG_SC_BK03_23_H _PK_H_(0x03, 0x23) ++#define REG_SC_BK03_24_L _PK_L_(0x03, 0x24) ++#define REG_SC_BK03_24_H _PK_H_(0x03, 0x24) ++#define REG_SC_BK03_25_L _PK_L_(0x03, 0x25) ++#define REG_SC_BK03_25_H _PK_H_(0x03, 0x25) ++#define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) ++#define REG_SC_BK03_26_H _PK_H_(0x03, 0x26) ++#define REG_SC_BK03_27_L _PK_L_(0x03, 0x27) ++#define REG_SC_BK03_27_H _PK_H_(0x03, 0x27) ++#define REG_SC_BK03_28_L _PK_L_(0x03, 0x28) ++#define REG_SC_BK03_28_H _PK_H_(0x03, 0x28) ++#define REG_SC_BK03_29_L _PK_L_(0x03, 0x29) ++#define REG_SC_BK03_29_H _PK_H_(0x03, 0x29) ++#define REG_SC_BK03_2A_L _PK_L_(0x03, 0x2A) ++#define REG_SC_BK03_2A_H _PK_H_(0x03, 0x2A) ++#define REG_SC_BK03_2B_L _PK_L_(0x03, 0x2B) ++#define REG_SC_BK03_2B_H _PK_H_(0x03, 0x2B) ++#define REG_SC_BK03_2C_L _PK_L_(0x03, 0x2C) ++#define REG_SC_BK03_2C_H _PK_H_(0x03, 0x2C) ++#define REG_SC_BK03_2D_L _PK_L_(0x03, 0x2D) ++#define REG_SC_BK03_2D_H _PK_H_(0x03, 0x2D) ++#define REG_SC_BK03_2E_L _PK_L_(0x03, 0x2E) ++#define REG_SC_BK03_2E_H _PK_H_(0x03, 0x2E) ++#define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) ++#define REG_SC_BK03_2F_H _PK_H_(0x03, 0x2F) ++#define REG_SC_BK03_30_L _PK_L_(0x03, 0x30) ++#define REG_SC_BK03_30_H _PK_H_(0x03, 0x30) ++#define REG_SC_BK03_31_L _PK_L_(0x03, 0x31) ++#define REG_SC_BK03_31_H _PK_H_(0x03, 0x31) ++#define REG_SC_BK03_32_L _PK_L_(0x03, 0x32) ++#define REG_SC_BK03_32_H _PK_H_(0x03, 0x32) ++#define REG_SC_BK03_33_L _PK_L_(0x03, 0x33) ++#define REG_SC_BK03_33_H _PK_H_(0x03, 0x33) ++#define REG_SC_BK03_34_L _PK_L_(0x03, 0x34) ++#define REG_SC_BK03_34_H _PK_H_(0x03, 0x34) ++#define REG_SC_BK03_35_L _PK_L_(0x03, 0x35) ++#define REG_SC_BK03_35_H _PK_H_(0x03, 0x35) ++#define REG_SC_BK03_36_L _PK_L_(0x03, 0x36) ++#define REG_SC_BK03_36_H _PK_H_(0x03, 0x36) ++#define REG_SC_BK03_37_L _PK_L_(0x03, 0x37) ++#define REG_SC_BK03_37_H _PK_H_(0x03, 0x37) ++#define REG_SC_BK03_38_L _PK_L_(0x03, 0x38) ++#define REG_SC_BK03_38_H _PK_H_(0x03, 0x38) ++#define REG_SC_BK03_39_L _PK_L_(0x03, 0x39) ++#define REG_SC_BK03_39_H _PK_H_(0x03, 0x39) ++#define REG_SC_BK03_3A_L _PK_L_(0x03, 0x3A) ++#define REG_SC_BK03_3A_H _PK_H_(0x03, 0x3A) ++#define REG_SC_BK03_3B_L _PK_L_(0x03, 0x3B) ++#define REG_SC_BK03_3B_H _PK_H_(0x03, 0x3B) ++#define REG_SC_BK03_3C_L _PK_L_(0x03, 0x3C) ++#define REG_SC_BK03_3C_H _PK_H_(0x03, 0x3C) ++#define REG_SC_BK03_3D_L _PK_L_(0x03, 0x3D) ++#define REG_SC_BK03_3D_H _PK_H_(0x03, 0x3D) ++#define REG_SC_BK03_3E_L _PK_L_(0x03, 0x3E) ++#define REG_SC_BK03_3E_H _PK_H_(0x03, 0x3E) ++#define REG_SC_BK03_3F_L _PK_L_(0x03, 0x3F) ++#define REG_SC_BK03_3F_H _PK_H_(0x03, 0x3F) ++#define REG_SC_BK03_40_L _PK_L_(0x03, 0x40) ++#define REG_SC_BK03_40_H _PK_H_(0x03, 0x40) ++#define REG_SC_BK03_41_L _PK_L_(0x03, 0x41) ++#define REG_SC_BK03_41_H _PK_H_(0x03, 0x41) ++#define REG_SC_BK03_42_L _PK_L_(0x03, 0x42) ++#define REG_SC_BK03_42_H _PK_H_(0x03, 0x42) ++#define REG_SC_BK03_43_L _PK_L_(0x03, 0x43) ++#define REG_SC_BK03_43_H _PK_H_(0x03, 0x43) ++#define REG_SC_BK03_44_L _PK_L_(0x03, 0x44) ++#define REG_SC_BK03_44_H _PK_H_(0x03, 0x44) ++#define REG_SC_BK03_45_L _PK_L_(0x03, 0x45) ++#define REG_SC_BK03_45_H _PK_H_(0x03, 0x45) ++#define REG_SC_BK03_46_L _PK_L_(0x03, 0x46) ++#define REG_SC_BK03_46_H _PK_H_(0x03, 0x46) ++#define REG_SC_BK03_47_L _PK_L_(0x03, 0x47) ++#define REG_SC_BK03_47_H _PK_H_(0x03, 0x47) ++#define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) ++#define REG_SC_BK03_48_H _PK_H_(0x03, 0x48) ++#define REG_SC_BK03_49_L _PK_L_(0x03, 0x49) ++#define REG_SC_BK03_49_H _PK_H_(0x03, 0x49) ++#define REG_SC_BK03_4A_L _PK_L_(0x03, 0x4A) ++#define REG_SC_BK03_4A_H _PK_H_(0x03, 0x4A) ++#define REG_SC_BK03_4B_L _PK_L_(0x03, 0x4B) ++#define REG_SC_BK03_4B_H _PK_H_(0x03, 0x4B) ++#define REG_SC_BK03_4C_L _PK_L_(0x03, 0x4C) ++#define REG_SC_BK03_4C_H _PK_H_(0x03, 0x4C) ++#define REG_SC_BK03_4D_L _PK_L_(0x03, 0x4D) ++#define REG_SC_BK03_4D_H _PK_H_(0x03, 0x4D) ++#define REG_SC_BK03_4E_L _PK_L_(0x03, 0x4E) ++#define REG_SC_BK03_4E_H _PK_H_(0x03, 0x4E) ++#define REG_SC_BK03_4F_L _PK_L_(0x03, 0x4F) ++#define REG_SC_BK03_4F_H _PK_H_(0x03, 0x4F) ++#define REG_SC_BK03_50_L _PK_L_(0x03, 0x50) ++#define REG_SC_BK03_50_H _PK_H_(0x03, 0x50) ++#define REG_SC_BK03_51_L _PK_L_(0x03, 0x51) ++#define REG_SC_BK03_51_H _PK_H_(0x03, 0x51) ++#define REG_SC_BK03_52_L _PK_L_(0x03, 0x52) ++#define REG_SC_BK03_52_H _PK_H_(0x03, 0x52) ++#define REG_SC_BK03_53_L _PK_L_(0x03, 0x53) ++#define REG_SC_BK03_53_H _PK_H_(0x03, 0x53) ++#define REG_SC_BK03_54_L _PK_L_(0x03, 0x54) ++#define REG_SC_BK03_54_H _PK_H_(0x03, 0x54) ++#define REG_SC_BK03_55_L _PK_L_(0x03, 0x55) ++#define REG_SC_BK03_55_H _PK_H_(0x03, 0x55) ++#define REG_SC_BK03_56_L _PK_L_(0x03, 0x56) ++#define REG_SC_BK03_56_H _PK_H_(0x03, 0x56) ++#define REG_SC_BK03_57_L _PK_L_(0x03, 0x57) ++#define REG_SC_BK03_57_H _PK_H_(0x03, 0x57) ++#define REG_SC_BK03_58_L _PK_L_(0x03, 0x58) ++#define REG_SC_BK03_58_H _PK_H_(0x03, 0x58) ++#define REG_SC_BK03_59_L _PK_L_(0x03, 0x59) ++#define REG_SC_BK03_59_H _PK_H_(0x03, 0x59) ++#define REG_SC_BK03_5A_L _PK_L_(0x03, 0x5A) ++#define REG_SC_BK03_5A_H _PK_H_(0x03, 0x5A) ++#define REG_SC_BK03_5B_L _PK_L_(0x03, 0x5B) ++#define REG_SC_BK03_5B_H _PK_H_(0x03, 0x5B) ++#define REG_SC_BK03_5C_L _PK_L_(0x03, 0x5C) ++#define REG_SC_BK03_5C_H _PK_H_(0x03, 0x5C) ++#define REG_SC_BK03_5D_L _PK_L_(0x03, 0x5D) ++#define REG_SC_BK03_5D_H _PK_H_(0x03, 0x5D) ++#define REG_SC_BK03_5E_L _PK_L_(0x03, 0x5E) ++#define REG_SC_BK03_5E_H _PK_H_(0x03, 0x5E) ++#define REG_SC_BK03_5F_L _PK_L_(0x03, 0x5F) ++#define REG_SC_BK03_5F_H _PK_H_(0x03, 0x5F) ++#define REG_SC_BK03_60_L _PK_L_(0x03, 0x60) ++#define REG_SC_BK03_60_H _PK_H_(0x03, 0x60) ++#define REG_SC_BK03_61_L _PK_L_(0x03, 0x61) ++#define REG_SC_BK03_61_H _PK_H_(0x03, 0x61) ++#define REG_SC_BK03_62_L _PK_L_(0x03, 0x62) ++#define REG_SC_BK03_62_H _PK_H_(0x03, 0x62) ++#define REG_SC_BK03_63_L _PK_L_(0x03, 0x63) ++#define REG_SC_BK03_63_H _PK_H_(0x03, 0x63) ++#define REG_SC_BK03_64_L _PK_L_(0x03, 0x64) ++#define REG_SC_BK03_64_H _PK_H_(0x03, 0x64) ++#define REG_SC_BK03_65_L _PK_L_(0x03, 0x65) ++#define REG_SC_BK03_65_H _PK_H_(0x03, 0x65) ++#define REG_SC_BK03_66_L _PK_L_(0x03, 0x66) ++#define REG_SC_BK03_66_H _PK_H_(0x03, 0x66) ++#define REG_SC_BK03_67_L _PK_L_(0x03, 0x67) ++#define REG_SC_BK03_67_H _PK_H_(0x03, 0x67) ++#define REG_SC_BK03_68_L _PK_L_(0x03, 0x68) ++#define REG_SC_BK03_68_H _PK_H_(0x03, 0x68) ++#define REG_SC_BK03_69_L _PK_L_(0x03, 0x69) ++#define REG_SC_BK03_69_H _PK_H_(0x03, 0x69) ++#define REG_SC_BK03_6A_L _PK_L_(0x03, 0x6A) ++#define REG_SC_BK03_6A_H _PK_H_(0x03, 0x6A) ++#define REG_SC_BK03_6B_L _PK_L_(0x03, 0x6B) ++#define REG_SC_BK03_6B_H _PK_H_(0x03, 0x6B) ++#define REG_SC_BK03_6C_L _PK_L_(0x03, 0x6C) ++#define REG_SC_BK03_6C_H _PK_H_(0x03, 0x6C) ++#define REG_SC_BK03_6D_L _PK_L_(0x03, 0x6D) ++#define REG_SC_BK03_6D_H _PK_H_(0x03, 0x6D) ++#define REG_SC_BK03_6E_L _PK_L_(0x03, 0x6E) ++#define REG_SC_BK03_6E_H _PK_H_(0x03, 0x6E) ++#define REG_SC_BK03_6F_L _PK_L_(0x03, 0x6F) ++#define REG_SC_BK03_6F_H _PK_H_(0x03, 0x6F) ++#define REG_SC_BK03_70_L _PK_L_(0x03, 0x70) ++#define REG_SC_BK03_70_H _PK_H_(0x03, 0x70) ++#define REG_SC_BK03_71_L _PK_L_(0x03, 0x71) ++#define REG_SC_BK03_71_H _PK_H_(0x03, 0x71) ++#define REG_SC_BK03_72_L _PK_L_(0x03, 0x72) ++#define REG_SC_BK03_72_H _PK_H_(0x03, 0x72) ++#define REG_SC_BK03_73_L _PK_L_(0x03, 0x73) ++#define REG_SC_BK03_73_H _PK_H_(0x03, 0x73) ++#define REG_SC_BK03_74_L _PK_L_(0x03, 0x74) ++#define REG_SC_BK03_74_H _PK_H_(0x03, 0x74) ++#define REG_SC_BK03_75_L _PK_L_(0x03, 0x75) ++#define REG_SC_BK03_75_H _PK_H_(0x03, 0x75) ++#define REG_SC_BK03_76_L _PK_L_(0x03, 0x76) ++#define REG_SC_BK03_76_H _PK_H_(0x03, 0x76) ++#define REG_SC_BK03_77_L _PK_L_(0x03, 0x77) ++#define REG_SC_BK03_77_H _PK_H_(0x03, 0x77) ++#define REG_SC_BK03_78_L _PK_L_(0x03, 0x78) ++#define REG_SC_BK03_78_H _PK_H_(0x03, 0x78) ++#define REG_SC_BK03_79_L _PK_L_(0x03, 0x79) ++#define REG_SC_BK03_79_H _PK_H_(0x03, 0x79) ++#define REG_SC_BK03_7A_L _PK_L_(0x03, 0x7A) ++#define REG_SC_BK03_7A_H _PK_H_(0x03, 0x7A) ++#define REG_SC_BK03_7B_L _PK_L_(0x03, 0x7B) ++#define REG_SC_BK03_7B_H _PK_H_(0x03, 0x7B) ++#define REG_SC_BK03_7C_L _PK_L_(0x03, 0x7C) ++#define REG_SC_BK03_7C_H _PK_H_(0x03, 0x7C) ++#define REG_SC_BK03_7D_L _PK_L_(0x03, 0x7D) ++#define REG_SC_BK03_7D_H _PK_H_(0x03, 0x7D) ++#define REG_SC_BK03_7E_L _PK_L_(0x03, 0x7E) ++#define REG_SC_BK03_7E_H _PK_H_(0x03, 0x7E) ++#define REG_SC_BK03_7F_L _PK_L_(0x03, 0x7F) ++#define REG_SC_BK03_7F_H _PK_H_(0x03, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK04_00_L _PK_L_(0x04, 0x00) ++#define REG_SC_BK04_00_H _PK_H_(0x04, 0x00) ++#define REG_SC_BK04_01_L _PK_L_(0x04, 0x01) ++#define REG_SC_BK04_01_H _PK_H_(0x04, 0x01) ++#define REG_SC_BK04_02_L _PK_L_(0x04, 0x02) ++#define REG_SC_BK04_02_H _PK_H_(0x04, 0x02) ++#define REG_SC_BK04_03_L _PK_L_(0x04, 0x03) ++#define REG_SC_BK04_03_H _PK_H_(0x04, 0x03) ++#define REG_SC_BK04_04_L _PK_L_(0x04, 0x04) ++#define REG_SC_BK04_04_H _PK_H_(0x04, 0x04) ++#define REG_SC_BK04_05_L _PK_L_(0x04, 0x05) ++#define REG_SC_BK04_05_H _PK_H_(0x04, 0x05) ++#define REG_SC_BK04_06_L _PK_L_(0x04, 0x06) ++#define REG_SC_BK04_06_H _PK_H_(0x04, 0x06) ++#define REG_SC_BK04_07_L _PK_L_(0x04, 0x07) ++#define REG_SC_BK04_07_H _PK_H_(0x04, 0x07) ++#define REG_SC_BK04_08_L _PK_L_(0x04, 0x08) ++#define REG_SC_BK04_08_H _PK_H_(0x04, 0x08) ++#define REG_SC_BK04_09_L _PK_L_(0x04, 0x09) ++#define REG_SC_BK04_09_H _PK_H_(0x04, 0x09) ++#define REG_SC_BK04_0A_L _PK_L_(0x04, 0x0A) ++#define REG_SC_BK04_0A_H _PK_H_(0x04, 0x0A) ++#define REG_SC_BK04_0B_L _PK_L_(0x04, 0x0B) ++#define REG_SC_BK04_0B_H _PK_H_(0x04, 0x0B) ++#define REG_SC_BK04_0C_L _PK_L_(0x04, 0x0C) ++#define REG_SC_BK04_0C_H _PK_H_(0x04, 0x0C) ++#define REG_SC_BK04_0D_L _PK_L_(0x04, 0x0D) ++#define REG_SC_BK04_0D_H _PK_H_(0x04, 0x0D) ++#define REG_SC_BK04_0E_L _PK_L_(0x04, 0x0E) ++#define REG_SC_BK04_0E_H _PK_H_(0x04, 0x0E) ++#define REG_SC_BK04_0F_L _PK_L_(0x04, 0x0F) ++#define REG_SC_BK04_0F_H _PK_H_(0x04, 0x0F) ++#define REG_SC_BK04_10_L _PK_L_(0x04, 0x10) ++#define REG_SC_BK04_10_H _PK_H_(0x04, 0x10) ++#define REG_SC_BK04_11_L _PK_L_(0x04, 0x11) ++#define REG_SC_BK04_11_H _PK_H_(0x04, 0x11) ++#define REG_SC_BK04_12_L _PK_L_(0x04, 0x12) ++#define REG_SC_BK04_12_H _PK_H_(0x04, 0x12) ++#define REG_SC_BK04_13_L _PK_L_(0x04, 0x13) ++#define REG_SC_BK04_13_H _PK_H_(0x04, 0x13) ++#define REG_SC_BK04_14_L _PK_L_(0x04, 0x14) ++#define REG_SC_BK04_14_H _PK_H_(0x04, 0x14) ++#define REG_SC_BK04_15_L _PK_L_(0x04, 0x15) ++#define REG_SC_BK04_15_H _PK_H_(0x04, 0x15) ++#define REG_SC_BK04_16_L _PK_L_(0x04, 0x16) ++#define REG_SC_BK04_16_H _PK_H_(0x04, 0x16) ++#define REG_SC_BK04_17_L _PK_L_(0x04, 0x17) ++#define REG_SC_BK04_17_H _PK_H_(0x04, 0x17) ++#define REG_SC_BK04_18_L _PK_L_(0x04, 0x18) ++#define REG_SC_BK04_18_H _PK_H_(0x04, 0x18) ++#define REG_SC_BK04_19_L _PK_L_(0x04, 0x19) ++#define REG_SC_BK04_19_H _PK_H_(0x04, 0x19) ++#define REG_SC_BK04_1A_L _PK_L_(0x04, 0x1A) ++#define REG_SC_BK04_1A_H _PK_H_(0x04, 0x1A) ++#define REG_SC_BK04_1B_L _PK_L_(0x04, 0x1B) ++#define REG_SC_BK04_1B_H _PK_H_(0x04, 0x1B) ++#define REG_SC_BK04_1C_L _PK_L_(0x04, 0x1C) ++#define REG_SC_BK04_1C_H _PK_H_(0x04, 0x1C) ++#define REG_SC_BK04_1D_L _PK_L_(0x04, 0x1D) ++#define REG_SC_BK04_1D_H _PK_H_(0x04, 0x1D) ++#define REG_SC_BK04_1E_L _PK_L_(0x04, 0x1E) ++#define REG_SC_BK04_1E_H _PK_H_(0x04, 0x1E) ++#define REG_SC_BK04_1F_L _PK_L_(0x04, 0x1F) ++#define REG_SC_BK04_1F_H _PK_H_(0x04, 0x1F) ++#define REG_SC_BK04_20_L _PK_L_(0x04, 0x20) ++#define REG_SC_BK04_20_H _PK_H_(0x04, 0x20) ++#define REG_SC_BK04_21_L _PK_L_(0x04, 0x21) ++#define REG_SC_BK04_21_H _PK_H_(0x04, 0x21) ++#define REG_SC_BK04_22_L _PK_L_(0x04, 0x22) ++#define REG_SC_BK04_22_H _PK_H_(0x04, 0x22) ++#define REG_SC_BK04_23_L _PK_L_(0x04, 0x23) ++#define REG_SC_BK04_23_H _PK_H_(0x04, 0x23) ++#define REG_SC_BK04_24_L _PK_L_(0x04, 0x24) ++#define REG_SC_BK04_24_H _PK_H_(0x04, 0x24) ++#define REG_SC_BK04_25_L _PK_L_(0x04, 0x25) ++#define REG_SC_BK04_25_H _PK_H_(0x04, 0x25) ++#define REG_SC_BK04_26_L _PK_L_(0x04, 0x26) ++#define REG_SC_BK04_26_H _PK_H_(0x04, 0x26) ++#define REG_SC_BK04_27_L _PK_L_(0x04, 0x27) ++#define REG_SC_BK04_27_H _PK_H_(0x04, 0x27) ++#define REG_SC_BK04_28_L _PK_L_(0x04, 0x28) ++#define REG_SC_BK04_28_H _PK_H_(0x04, 0x28) ++#define REG_SC_BK04_29_L _PK_L_(0x04, 0x29) ++#define REG_SC_BK04_29_H _PK_H_(0x04, 0x29) ++#define REG_SC_BK04_2A_L _PK_L_(0x04, 0x2A) ++#define REG_SC_BK04_2A_H _PK_H_(0x04, 0x2A) ++#define REG_SC_BK04_2B_L _PK_L_(0x04, 0x2B) ++#define REG_SC_BK04_2B_H _PK_H_(0x04, 0x2B) ++#define REG_SC_BK04_2C_L _PK_L_(0x04, 0x2C) ++#define REG_SC_BK04_2C_H _PK_H_(0x04, 0x2C) ++#define REG_SC_BK04_2D_L _PK_L_(0x04, 0x2D) ++#define REG_SC_BK04_2D_H _PK_H_(0x04, 0x2D) ++#define REG_SC_BK04_2E_L _PK_L_(0x04, 0x2E) ++#define REG_SC_BK04_2E_H _PK_H_(0x04, 0x2E) ++#define REG_SC_BK04_2F_L _PK_L_(0x04, 0x2F) ++#define REG_SC_BK04_2F_H _PK_H_(0x04, 0x2F) ++#define REG_SC_BK04_30_L _PK_L_(0x04, 0x30) ++#define REG_SC_BK04_30_H _PK_H_(0x04, 0x30) ++#define REG_SC_BK04_31_L _PK_L_(0x04, 0x31) ++#define REG_SC_BK04_31_H _PK_H_(0x04, 0x31) ++#define REG_SC_BK04_32_L _PK_L_(0x04, 0x32) ++#define REG_SC_BK04_32_H _PK_H_(0x04, 0x32) ++#define REG_SC_BK04_33_L _PK_L_(0x04, 0x33) ++#define REG_SC_BK04_33_H _PK_H_(0x04, 0x33) ++#define REG_SC_BK04_34_L _PK_L_(0x04, 0x34) ++#define REG_SC_BK04_34_H _PK_H_(0x04, 0x34) ++#define REG_SC_BK04_35_L _PK_L_(0x04, 0x35) ++#define REG_SC_BK04_35_H _PK_H_(0x04, 0x35) ++#define REG_SC_BK04_36_L _PK_L_(0x04, 0x36) ++#define REG_SC_BK04_36_H _PK_H_(0x04, 0x36) ++#define REG_SC_BK04_37_L _PK_L_(0x04, 0x37) ++#define REG_SC_BK04_37_H _PK_H_(0x04, 0x37) ++#define REG_SC_BK04_38_L _PK_L_(0x04, 0x38) ++#define REG_SC_BK04_38_H _PK_H_(0x04, 0x38) ++#define REG_SC_BK04_39_L _PK_L_(0x04, 0x39) ++#define REG_SC_BK04_39_H _PK_H_(0x04, 0x39) ++#define REG_SC_BK04_3A_L _PK_L_(0x04, 0x3A) ++#define REG_SC_BK04_3A_H _PK_H_(0x04, 0x3A) ++#define REG_SC_BK04_3B_L _PK_L_(0x04, 0x3B) ++#define REG_SC_BK04_3B_H _PK_H_(0x04, 0x3B) ++#define REG_SC_BK04_3C_L _PK_L_(0x04, 0x3C) ++#define REG_SC_BK04_3C_H _PK_H_(0x04, 0x3C) ++#define REG_SC_BK04_3D_L _PK_L_(0x04, 0x3D) ++#define REG_SC_BK04_3D_H _PK_H_(0x04, 0x3D) ++#define REG_SC_BK04_3E_L _PK_L_(0x04, 0x3E) ++#define REG_SC_BK04_3E_H _PK_H_(0x04, 0x3E) ++#define REG_SC_BK04_3F_L _PK_L_(0x04, 0x3F) ++#define REG_SC_BK04_3F_H _PK_H_(0x04, 0x3F) ++#define REG_SC_BK04_40_L _PK_L_(0x04, 0x40) ++#define REG_SC_BK04_40_H _PK_H_(0x04, 0x40) ++#define REG_SC_BK04_41_L _PK_L_(0x04, 0x41) ++#define REG_SC_BK04_41_H _PK_H_(0x04, 0x41) ++#define REG_SC_BK04_42_L _PK_L_(0x04, 0x42) ++#define REG_SC_BK04_42_H _PK_H_(0x04, 0x42) ++#define REG_SC_BK04_43_L _PK_L_(0x04, 0x43) ++#define REG_SC_BK04_43_H _PK_H_(0x04, 0x43) ++#define REG_SC_BK04_44_L _PK_L_(0x04, 0x44) ++#define REG_SC_BK04_44_H _PK_H_(0x04, 0x44) ++#define REG_SC_BK04_45_L _PK_L_(0x04, 0x45) ++#define REG_SC_BK04_45_H _PK_H_(0x04, 0x45) ++#define REG_SC_BK04_46_L _PK_L_(0x04, 0x46) ++#define REG_SC_BK04_46_H _PK_H_(0x04, 0x46) ++#define REG_SC_BK04_47_L _PK_L_(0x04, 0x47) ++#define REG_SC_BK04_47_H _PK_H_(0x04, 0x47) ++#define REG_SC_BK04_48_L _PK_L_(0x04, 0x48) ++#define REG_SC_BK04_48_H _PK_H_(0x04, 0x48) ++#define REG_SC_BK04_49_L _PK_L_(0x04, 0x49) ++#define REG_SC_BK04_49_H _PK_H_(0x04, 0x49) ++#define REG_SC_BK04_4A_L _PK_L_(0x04, 0x4A) ++#define REG_SC_BK04_4A_H _PK_H_(0x04, 0x4A) ++#define REG_SC_BK04_4B_L _PK_L_(0x04, 0x4B) ++#define REG_SC_BK04_4B_H _PK_H_(0x04, 0x4B) ++#define REG_SC_BK04_4C_L _PK_L_(0x04, 0x4C) ++#define REG_SC_BK04_4C_H _PK_H_(0x04, 0x4C) ++#define REG_SC_BK04_4D_L _PK_L_(0x04, 0x4D) ++#define REG_SC_BK04_4D_H _PK_H_(0x04, 0x4D) ++#define REG_SC_BK04_4E_L _PK_L_(0x04, 0x4E) ++#define REG_SC_BK04_4E_H _PK_H_(0x04, 0x4E) ++#define REG_SC_BK04_4F_L _PK_L_(0x04, 0x4F) ++#define REG_SC_BK04_4F_H _PK_H_(0x04, 0x4F) ++#define REG_SC_BK04_50_L _PK_L_(0x04, 0x50) ++#define REG_SC_BK04_50_H _PK_H_(0x04, 0x50) ++#define REG_SC_BK04_51_L _PK_L_(0x04, 0x51) ++#define REG_SC_BK04_51_H _PK_H_(0x04, 0x51) ++#define REG_SC_BK04_52_L _PK_L_(0x04, 0x52) ++#define REG_SC_BK04_52_H _PK_H_(0x04, 0x52) ++#define REG_SC_BK04_53_L _PK_L_(0x04, 0x53) ++#define REG_SC_BK04_53_H _PK_H_(0x04, 0x53) ++#define REG_SC_BK04_54_L _PK_L_(0x04, 0x54) ++#define REG_SC_BK04_54_H _PK_H_(0x04, 0x54) ++#define REG_SC_BK04_55_L _PK_L_(0x04, 0x55) ++#define REG_SC_BK04_55_H _PK_H_(0x04, 0x55) ++#define REG_SC_BK04_56_L _PK_L_(0x04, 0x56) ++#define REG_SC_BK04_56_H _PK_H_(0x04, 0x56) ++#define REG_SC_BK04_57_L _PK_L_(0x04, 0x57) ++#define REG_SC_BK04_57_H _PK_H_(0x04, 0x57) ++#define REG_SC_BK04_58_L _PK_L_(0x04, 0x58) ++#define REG_SC_BK04_58_H _PK_H_(0x04, 0x58) ++#define REG_SC_BK04_59_L _PK_L_(0x04, 0x59) ++#define REG_SC_BK04_59_H _PK_H_(0x04, 0x59) ++#define REG_SC_BK04_5A_L _PK_L_(0x04, 0x5A) ++#define REG_SC_BK04_5A_H _PK_H_(0x04, 0x5A) ++#define REG_SC_BK04_5B_L _PK_L_(0x04, 0x5B) ++#define REG_SC_BK04_5B_H _PK_H_(0x04, 0x5B) ++#define REG_SC_BK04_5C_L _PK_L_(0x04, 0x5C) ++#define REG_SC_BK04_5C_H _PK_H_(0x04, 0x5C) ++#define REG_SC_BK04_5D_L _PK_L_(0x04, 0x5D) ++#define REG_SC_BK04_5D_H _PK_H_(0x04, 0x5D) ++#define REG_SC_BK04_5E_L _PK_L_(0x04, 0x5E) ++#define REG_SC_BK04_5E_H _PK_H_(0x04, 0x5E) ++#define REG_SC_BK04_5F_L _PK_L_(0x04, 0x5F) ++#define REG_SC_BK04_5F_H _PK_H_(0x04, 0x5F) ++#define REG_SC_BK04_60_L _PK_L_(0x04, 0x60) ++#define REG_SC_BK04_60_H _PK_H_(0x04, 0x60) ++#define REG_SC_BK04_61_L _PK_L_(0x04, 0x61) ++#define REG_SC_BK04_61_H _PK_H_(0x04, 0x61) ++#define REG_SC_BK04_62_L _PK_L_(0x04, 0x62) ++#define REG_SC_BK04_62_H _PK_H_(0x04, 0x62) ++#define REG_SC_BK04_63_L _PK_L_(0x04, 0x63) ++#define REG_SC_BK04_63_H _PK_H_(0x04, 0x63) ++#define REG_SC_BK04_64_L _PK_L_(0x04, 0x64) ++#define REG_SC_BK04_64_H _PK_H_(0x04, 0x64) ++#define REG_SC_BK04_65_L _PK_L_(0x04, 0x65) ++#define REG_SC_BK04_65_H _PK_H_(0x04, 0x65) ++#define REG_SC_BK04_66_L _PK_L_(0x04, 0x66) ++#define REG_SC_BK04_66_H _PK_H_(0x04, 0x66) ++#define REG_SC_BK04_67_L _PK_L_(0x04, 0x67) ++#define REG_SC_BK04_67_H _PK_H_(0x04, 0x67) ++#define REG_SC_BK04_68_L _PK_L_(0x04, 0x68) ++#define REG_SC_BK04_68_H _PK_H_(0x04, 0x68) ++#define REG_SC_BK04_69_L _PK_L_(0x04, 0x69) ++#define REG_SC_BK04_69_H _PK_H_(0x04, 0x69) ++#define REG_SC_BK04_6A_L _PK_L_(0x04, 0x6A) ++#define REG_SC_BK04_6A_H _PK_H_(0x04, 0x6A) ++#define REG_SC_BK04_6B_L _PK_L_(0x04, 0x6B) ++#define REG_SC_BK04_6B_H _PK_H_(0x04, 0x6B) ++#define REG_SC_BK04_6C_L _PK_L_(0x04, 0x6C) ++#define REG_SC_BK04_6C_H _PK_H_(0x04, 0x6C) ++#define REG_SC_BK04_6D_L _PK_L_(0x04, 0x6D) ++#define REG_SC_BK04_6D_H _PK_H_(0x04, 0x6D) ++#define REG_SC_BK04_6E_L _PK_L_(0x04, 0x6E) ++#define REG_SC_BK04_6E_H _PK_H_(0x04, 0x6E) ++#define REG_SC_BK04_6F_L _PK_L_(0x04, 0x6F) ++#define REG_SC_BK04_6F_H _PK_H_(0x04, 0x6F) ++#define REG_SC_BK04_70_L _PK_L_(0x04, 0x70) ++#define REG_SC_BK04_70_H _PK_H_(0x04, 0x70) ++#define REG_SC_BK04_71_L _PK_L_(0x04, 0x71) ++#define REG_SC_BK04_71_H _PK_H_(0x04, 0x71) ++#define REG_SC_BK04_72_L _PK_L_(0x04, 0x72) ++#define REG_SC_BK04_72_H _PK_H_(0x04, 0x72) ++#define REG_SC_BK04_73_L _PK_L_(0x04, 0x73) ++#define REG_SC_BK04_73_H _PK_H_(0x04, 0x73) ++#define REG_SC_BK04_74_L _PK_L_(0x04, 0x74) ++#define REG_SC_BK04_74_H _PK_H_(0x04, 0x74) ++#define REG_SC_BK04_75_L _PK_L_(0x04, 0x75) ++#define REG_SC_BK04_75_H _PK_H_(0x04, 0x75) ++#define REG_SC_BK04_76_L _PK_L_(0x04, 0x76) ++#define REG_SC_BK04_76_H _PK_H_(0x04, 0x76) ++#define REG_SC_BK04_77_L _PK_L_(0x04, 0x77) ++#define REG_SC_BK04_77_H _PK_H_(0x04, 0x77) ++#define REG_SC_BK04_78_L _PK_L_(0x04, 0x78) ++#define REG_SC_BK04_78_H _PK_H_(0x04, 0x78) ++#define REG_SC_BK04_79_L _PK_L_(0x04, 0x79) ++#define REG_SC_BK04_79_H _PK_H_(0x04, 0x79) ++#define REG_SC_BK04_7A_L _PK_L_(0x04, 0x7A) ++#define REG_SC_BK04_7A_H _PK_H_(0x04, 0x7A) ++#define REG_SC_BK04_7B_L _PK_L_(0x04, 0x7B) ++#define REG_SC_BK04_7B_H _PK_H_(0x04, 0x7B) ++#define REG_SC_BK04_7C_L _PK_L_(0x04, 0x7C) ++#define REG_SC_BK04_7C_H _PK_H_(0x04, 0x7C) ++#define REG_SC_BK04_7D_L _PK_L_(0x04, 0x7D) ++#define REG_SC_BK04_7D_H _PK_H_(0x04, 0x7D) ++#define REG_SC_BK04_7E_L _PK_L_(0x04, 0x7E) ++#define REG_SC_BK04_7E_H _PK_H_(0x04, 0x7E) ++#define REG_SC_BK04_7F_L _PK_L_(0x04, 0x7F) ++#define REG_SC_BK04_7F_H _PK_H_(0x04, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK05_00_L _PK_L_(0x05, 0x00) ++#define REG_SC_BK05_00_H _PK_H_(0x05, 0x00) ++#define REG_SC_BK05_01_L _PK_L_(0x05, 0x01) ++#define REG_SC_BK05_01_H _PK_H_(0x05, 0x01) ++#define REG_SC_BK05_02_L _PK_L_(0x05, 0x02) ++#define REG_SC_BK05_02_H _PK_H_(0x05, 0x02) ++#define REG_SC_BK05_03_L _PK_L_(0x05, 0x03) ++#define REG_SC_BK05_03_H _PK_H_(0x05, 0x03) ++#define REG_SC_BK05_04_L _PK_L_(0x05, 0x04) ++#define REG_SC_BK05_04_H _PK_H_(0x05, 0x04) ++#define REG_SC_BK05_05_L _PK_L_(0x05, 0x05) ++#define REG_SC_BK05_05_H _PK_H_(0x05, 0x05) ++#define REG_SC_BK05_06_L _PK_L_(0x05, 0x06) ++#define REG_SC_BK05_06_H _PK_H_(0x05, 0x06) ++#define REG_SC_BK05_07_L _PK_L_(0x05, 0x07) ++#define REG_SC_BK05_07_H _PK_H_(0x05, 0x07) ++#define REG_SC_BK05_08_L _PK_L_(0x05, 0x08) ++#define REG_SC_BK05_08_H _PK_H_(0x05, 0x08) ++#define REG_SC_BK05_09_L _PK_L_(0x05, 0x09) ++#define REG_SC_BK05_09_H _PK_H_(0x05, 0x09) ++#define REG_SC_BK05_0A_L _PK_L_(0x05, 0x0A) ++#define REG_SC_BK05_0A_H _PK_H_(0x05, 0x0A) ++#define REG_SC_BK05_0B_L _PK_L_(0x05, 0x0B) ++#define REG_SC_BK05_0B_H _PK_H_(0x05, 0x0B) ++#define REG_SC_BK05_0C_L _PK_L_(0x05, 0x0C) ++#define REG_SC_BK05_0C_H _PK_H_(0x05, 0x0C) ++#define REG_SC_BK05_0D_L _PK_L_(0x05, 0x0D) ++#define REG_SC_BK05_0D_H _PK_H_(0x05, 0x0D) ++#define REG_SC_BK05_0E_L _PK_L_(0x05, 0x0E) ++#define REG_SC_BK05_0E_H _PK_H_(0x05, 0x0E) ++#define REG_SC_BK05_0F_L _PK_L_(0x05, 0x0F) ++#define REG_SC_BK05_0F_H _PK_H_(0x05, 0x0F) ++#define REG_SC_BK05_10_L _PK_L_(0x05, 0x10) ++#define REG_SC_BK05_10_H _PK_H_(0x05, 0x10) ++#define REG_SC_BK05_11_L _PK_L_(0x05, 0x11) ++#define REG_SC_BK05_11_H _PK_H_(0x05, 0x11) ++#define REG_SC_BK05_12_L _PK_L_(0x05, 0x12) ++#define REG_SC_BK05_12_H _PK_H_(0x05, 0x12) ++#define REG_SC_BK05_13_L _PK_L_(0x05, 0x13) ++#define REG_SC_BK05_13_H _PK_H_(0x05, 0x13) ++#define REG_SC_BK05_14_L _PK_L_(0x05, 0x14) ++#define REG_SC_BK05_14_H _PK_H_(0x05, 0x14) ++#define REG_SC_BK05_15_L _PK_L_(0x05, 0x15) ++#define REG_SC_BK05_15_H _PK_H_(0x05, 0x15) ++#define REG_SC_BK05_16_L _PK_L_(0x05, 0x16) ++#define REG_SC_BK05_16_H _PK_H_(0x05, 0x16) ++#define REG_SC_BK05_17_L _PK_L_(0x05, 0x17) ++#define REG_SC_BK05_17_H _PK_H_(0x05, 0x17) ++#define REG_SC_BK05_18_L _PK_L_(0x05, 0x18) ++#define REG_SC_BK05_18_H _PK_H_(0x05, 0x18) ++#define REG_SC_BK05_19_L _PK_L_(0x05, 0x19) ++#define REG_SC_BK05_19_H _PK_H_(0x05, 0x19) ++#define REG_SC_BK05_1A_L _PK_L_(0x05, 0x1A) ++#define REG_SC_BK05_1A_H _PK_H_(0x05, 0x1A) ++#define REG_SC_BK05_1B_L _PK_L_(0x05, 0x1B) ++#define REG_SC_BK05_1B_H _PK_H_(0x05, 0x1B) ++#define REG_SC_BK05_1C_L _PK_L_(0x05, 0x1C) ++#define REG_SC_BK05_1C_H _PK_H_(0x05, 0x1C) ++#define REG_SC_BK05_1D_L _PK_L_(0x05, 0x1D) ++#define REG_SC_BK05_1D_H _PK_H_(0x05, 0x1D) ++#define REG_SC_BK05_1E_L _PK_L_(0x05, 0x1E) ++#define REG_SC_BK05_1E_H _PK_H_(0x05, 0x1E) ++#define REG_SC_BK05_1F_L _PK_L_(0x05, 0x1F) ++#define REG_SC_BK05_1F_H _PK_H_(0x05, 0x1F) ++#define REG_SC_BK05_20_L _PK_L_(0x05, 0x20) ++#define REG_SC_BK05_20_H _PK_H_(0x05, 0x20) ++#define REG_SC_BK05_21_L _PK_L_(0x05, 0x21) ++#define REG_SC_BK05_21_H _PK_H_(0x05, 0x21) ++#define REG_SC_BK05_22_L _PK_L_(0x05, 0x22) ++#define REG_SC_BK05_22_H _PK_H_(0x05, 0x22) ++#define REG_SC_BK05_23_L _PK_L_(0x05, 0x23) ++#define REG_SC_BK05_23_H _PK_H_(0x05, 0x23) ++#define REG_SC_BK05_24_L _PK_L_(0x05, 0x24) ++#define REG_SC_BK05_24_H _PK_H_(0x05, 0x24) ++#define REG_SC_BK05_25_L _PK_L_(0x05, 0x25) ++#define REG_SC_BK05_25_H _PK_H_(0x05, 0x25) ++#define REG_SC_BK05_26_L _PK_L_(0x05, 0x26) ++#define REG_SC_BK05_26_H _PK_H_(0x05, 0x26) ++#define REG_SC_BK05_27_L _PK_L_(0x05, 0x27) ++#define REG_SC_BK05_27_H _PK_H_(0x05, 0x27) ++#define REG_SC_BK05_28_L _PK_L_(0x05, 0x28) ++#define REG_SC_BK05_28_H _PK_H_(0x05, 0x28) ++#define REG_SC_BK05_29_L _PK_L_(0x05, 0x29) ++#define REG_SC_BK05_29_H _PK_H_(0x05, 0x29) ++#define REG_SC_BK05_2A_L _PK_L_(0x05, 0x2A) ++#define REG_SC_BK05_2A_H _PK_H_(0x05, 0x2A) ++#define REG_SC_BK05_2B_L _PK_L_(0x05, 0x2B) ++#define REG_SC_BK05_2B_H _PK_H_(0x05, 0x2B) ++#define REG_SC_BK05_2C_L _PK_L_(0x05, 0x2C) ++#define REG_SC_BK05_2C_H _PK_H_(0x05, 0x2C) ++#define REG_SC_BK05_2D_L _PK_L_(0x05, 0x2D) ++#define REG_SC_BK05_2D_H _PK_H_(0x05, 0x2D) ++#define REG_SC_BK05_2E_L _PK_L_(0x05, 0x2E) ++#define REG_SC_BK05_2E_H _PK_H_(0x05, 0x2E) ++#define REG_SC_BK05_2F_L _PK_L_(0x05, 0x2F) ++#define REG_SC_BK05_2F_H _PK_H_(0x05, 0x2F) ++#define REG_SC_BK05_30_L _PK_L_(0x05, 0x30) ++#define REG_SC_BK05_30_H _PK_H_(0x05, 0x30) ++#define REG_SC_BK05_31_L _PK_L_(0x05, 0x31) ++#define REG_SC_BK05_31_H _PK_H_(0x05, 0x31) ++#define REG_SC_BK05_32_L _PK_L_(0x05, 0x32) ++#define REG_SC_BK05_32_H _PK_H_(0x05, 0x32) ++#define REG_SC_BK05_33_L _PK_L_(0x05, 0x33) ++#define REG_SC_BK05_33_H _PK_H_(0x05, 0x33) ++#define REG_SC_BK05_34_L _PK_L_(0x05, 0x34) ++#define REG_SC_BK05_34_H _PK_H_(0x05, 0x34) ++#define REG_SC_BK05_35_L _PK_L_(0x05, 0x35) ++#define REG_SC_BK05_35_H _PK_H_(0x05, 0x35) ++#define REG_SC_BK05_36_L _PK_L_(0x05, 0x36) ++#define REG_SC_BK05_36_H _PK_H_(0x05, 0x36) ++#define REG_SC_BK05_37_L _PK_L_(0x05, 0x37) ++#define REG_SC_BK05_37_H _PK_H_(0x05, 0x37) ++#define REG_SC_BK05_38_L _PK_L_(0x05, 0x38) ++#define REG_SC_BK05_38_H _PK_H_(0x05, 0x38) ++#define REG_SC_BK05_39_L _PK_L_(0x05, 0x39) ++#define REG_SC_BK05_39_H _PK_H_(0x05, 0x39) ++#define REG_SC_BK05_3A_L _PK_L_(0x05, 0x3A) ++#define REG_SC_BK05_3A_H _PK_H_(0x05, 0x3A) ++#define REG_SC_BK05_3B_L _PK_L_(0x05, 0x3B) ++#define REG_SC_BK05_3B_H _PK_H_(0x05, 0x3B) ++#define REG_SC_BK05_3C_L _PK_L_(0x05, 0x3C) ++#define REG_SC_BK05_3C_H _PK_H_(0x05, 0x3C) ++#define REG_SC_BK05_3D_L _PK_L_(0x05, 0x3D) ++#define REG_SC_BK05_3D_H _PK_H_(0x05, 0x3D) ++#define REG_SC_BK05_3E_L _PK_L_(0x05, 0x3E) ++#define REG_SC_BK05_3E_H _PK_H_(0x05, 0x3E) ++#define REG_SC_BK05_3F_L _PK_L_(0x05, 0x3F) ++#define REG_SC_BK05_3F_H _PK_H_(0x05, 0x3F) ++#define REG_SC_BK05_40_L _PK_L_(0x05, 0x40) ++#define REG_SC_BK05_40_H _PK_H_(0x05, 0x40) ++#define REG_SC_BK05_41_L _PK_L_(0x05, 0x41) ++#define REG_SC_BK05_41_H _PK_H_(0x05, 0x41) ++#define REG_SC_BK05_42_L _PK_L_(0x05, 0x42) ++#define REG_SC_BK05_42_H _PK_H_(0x05, 0x42) ++#define REG_SC_BK05_43_L _PK_L_(0x05, 0x43) ++#define REG_SC_BK05_43_H _PK_H_(0x05, 0x43) ++#define REG_SC_BK05_44_L _PK_L_(0x05, 0x44) ++#define REG_SC_BK05_44_H _PK_H_(0x05, 0x44) ++#define REG_SC_BK05_45_L _PK_L_(0x05, 0x45) ++#define REG_SC_BK05_45_H _PK_H_(0x05, 0x45) ++#define REG_SC_BK05_46_L _PK_L_(0x05, 0x46) ++#define REG_SC_BK05_46_H _PK_H_(0x05, 0x46) ++#define REG_SC_BK05_47_L _PK_L_(0x05, 0x47) ++#define REG_SC_BK05_47_H _PK_H_(0x05, 0x47) ++#define REG_SC_BK05_48_L _PK_L_(0x05, 0x48) ++#define REG_SC_BK05_48_H _PK_H_(0x05, 0x48) ++#define REG_SC_BK05_49_L _PK_L_(0x05, 0x49) ++#define REG_SC_BK05_49_H _PK_H_(0x05, 0x49) ++#define REG_SC_BK05_4A_L _PK_L_(0x05, 0x4A) ++#define REG_SC_BK05_4A_H _PK_H_(0x05, 0x4A) ++#define REG_SC_BK05_4B_L _PK_L_(0x05, 0x4B) ++#define REG_SC_BK05_4B_H _PK_H_(0x05, 0x4B) ++#define REG_SC_BK05_4C_L _PK_L_(0x05, 0x4C) ++#define REG_SC_BK05_4C_H _PK_H_(0x05, 0x4C) ++#define REG_SC_BK05_4D_L _PK_L_(0x05, 0x4D) ++#define REG_SC_BK05_4D_H _PK_H_(0x05, 0x4D) ++#define REG_SC_BK05_4E_L _PK_L_(0x05, 0x4E) ++#define REG_SC_BK05_4E_H _PK_H_(0x05, 0x4E) ++#define REG_SC_BK05_4F_L _PK_L_(0x05, 0x4F) ++#define REG_SC_BK05_4F_H _PK_H_(0x05, 0x4F) ++#define REG_SC_BK05_50_L _PK_L_(0x05, 0x50) ++#define REG_SC_BK05_50_H _PK_H_(0x05, 0x50) ++#define REG_SC_BK05_51_L _PK_L_(0x05, 0x51) ++#define REG_SC_BK05_51_H _PK_H_(0x05, 0x51) ++#define REG_SC_BK05_52_L _PK_L_(0x05, 0x52) ++#define REG_SC_BK05_52_H _PK_H_(0x05, 0x52) ++#define REG_SC_BK05_53_L _PK_L_(0x05, 0x53) ++#define REG_SC_BK05_53_H _PK_H_(0x05, 0x53) ++#define REG_SC_BK05_54_L _PK_L_(0x05, 0x54) ++#define REG_SC_BK05_54_H _PK_H_(0x05, 0x54) ++#define REG_SC_BK05_55_L _PK_L_(0x05, 0x55) ++#define REG_SC_BK05_55_H _PK_H_(0x05, 0x55) ++#define REG_SC_BK05_56_L _PK_L_(0x05, 0x56) ++#define REG_SC_BK05_56_H _PK_H_(0x05, 0x56) ++#define REG_SC_BK05_57_L _PK_L_(0x05, 0x57) ++#define REG_SC_BK05_57_H _PK_H_(0x05, 0x57) ++#define REG_SC_BK05_58_L _PK_L_(0x05, 0x58) ++#define REG_SC_BK05_58_H _PK_H_(0x05, 0x58) ++#define REG_SC_BK05_59_L _PK_L_(0x05, 0x59) ++#define REG_SC_BK05_59_H _PK_H_(0x05, 0x59) ++#define REG_SC_BK05_5A_L _PK_L_(0x05, 0x5A) ++#define REG_SC_BK05_5A_H _PK_H_(0x05, 0x5A) ++#define REG_SC_BK05_5B_L _PK_L_(0x05, 0x5B) ++#define REG_SC_BK05_5B_H _PK_H_(0x05, 0x5B) ++#define REG_SC_BK05_5C_L _PK_L_(0x05, 0x5C) ++#define REG_SC_BK05_5C_H _PK_H_(0x05, 0x5C) ++#define REG_SC_BK05_5D_L _PK_L_(0x05, 0x5D) ++#define REG_SC_BK05_5D_H _PK_H_(0x05, 0x5D) ++#define REG_SC_BK05_5E_L _PK_L_(0x05, 0x5E) ++#define REG_SC_BK05_5E_H _PK_H_(0x05, 0x5E) ++#define REG_SC_BK05_5F_L _PK_L_(0x05, 0x5F) ++#define REG_SC_BK05_5F_H _PK_H_(0x05, 0x5F) ++#define REG_SC_BK05_60_L _PK_L_(0x05, 0x60) ++#define REG_SC_BK05_60_H _PK_H_(0x05, 0x60) ++#define REG_SC_BK05_61_L _PK_L_(0x05, 0x61) ++#define REG_SC_BK05_61_H _PK_H_(0x05, 0x61) ++#define REG_SC_BK05_62_L _PK_L_(0x05, 0x62) ++#define REG_SC_BK05_62_H _PK_H_(0x05, 0x62) ++#define REG_SC_BK05_63_L _PK_L_(0x05, 0x63) ++#define REG_SC_BK05_63_H _PK_H_(0x05, 0x63) ++#define REG_SC_BK05_64_L _PK_L_(0x05, 0x64) ++#define REG_SC_BK05_64_H _PK_H_(0x05, 0x64) ++#define REG_SC_BK05_65_L _PK_L_(0x05, 0x65) ++#define REG_SC_BK05_65_H _PK_H_(0x05, 0x65) ++#define REG_SC_BK05_66_L _PK_L_(0x05, 0x66) ++#define REG_SC_BK05_66_H _PK_H_(0x05, 0x66) ++#define REG_SC_BK05_67_L _PK_L_(0x05, 0x67) ++#define REG_SC_BK05_67_H _PK_H_(0x05, 0x67) ++#define REG_SC_BK05_68_L _PK_L_(0x05, 0x68) ++#define REG_SC_BK05_68_H _PK_H_(0x05, 0x68) ++#define REG_SC_BK05_69_L _PK_L_(0x05, 0x69) ++#define REG_SC_BK05_69_H _PK_H_(0x05, 0x69) ++#define REG_SC_BK05_6A_L _PK_L_(0x05, 0x6A) ++#define REG_SC_BK05_6A_H _PK_H_(0x05, 0x6A) ++#define REG_SC_BK05_6B_L _PK_L_(0x05, 0x6B) ++#define REG_SC_BK05_6B_H _PK_H_(0x05, 0x6B) ++#define REG_SC_BK05_6C_L _PK_L_(0x05, 0x6C) ++#define REG_SC_BK05_6C_H _PK_H_(0x05, 0x6C) ++#define REG_SC_BK05_6D_L _PK_L_(0x05, 0x6D) ++#define REG_SC_BK05_6D_H _PK_H_(0x05, 0x6D) ++#define REG_SC_BK05_6E_L _PK_L_(0x05, 0x6E) ++#define REG_SC_BK05_6E_H _PK_H_(0x05, 0x6E) ++#define REG_SC_BK05_6F_L _PK_L_(0x05, 0x6F) ++#define REG_SC_BK05_6F_H _PK_H_(0x05, 0x6F) ++#define REG_SC_BK05_70_L _PK_L_(0x05, 0x70) ++#define REG_SC_BK05_70_H _PK_H_(0x05, 0x70) ++#define REG_SC_BK05_71_L _PK_L_(0x05, 0x71) ++#define REG_SC_BK05_71_H _PK_H_(0x05, 0x71) ++#define REG_SC_BK05_72_L _PK_L_(0x05, 0x72) ++#define REG_SC_BK05_72_H _PK_H_(0x05, 0x72) ++#define REG_SC_BK05_73_L _PK_L_(0x05, 0x73) ++#define REG_SC_BK05_73_H _PK_H_(0x05, 0x73) ++#define REG_SC_BK05_74_L _PK_L_(0x05, 0x74) ++#define REG_SC_BK05_74_H _PK_H_(0x05, 0x74) ++#define REG_SC_BK05_75_L _PK_L_(0x05, 0x75) ++#define REG_SC_BK05_75_H _PK_H_(0x05, 0x75) ++#define REG_SC_BK05_76_L _PK_L_(0x05, 0x76) ++#define REG_SC_BK05_76_H _PK_H_(0x05, 0x76) ++#define REG_SC_BK05_77_L _PK_L_(0x05, 0x77) ++#define REG_SC_BK05_77_H _PK_H_(0x05, 0x77) ++#define REG_SC_BK05_78_L _PK_L_(0x05, 0x78) ++#define REG_SC_BK05_78_H _PK_H_(0x05, 0x78) ++#define REG_SC_BK05_79_L _PK_L_(0x05, 0x79) ++#define REG_SC_BK05_79_H _PK_H_(0x05, 0x79) ++#define REG_SC_BK05_7A_L _PK_L_(0x05, 0x7A) ++#define REG_SC_BK05_7A_H _PK_H_(0x05, 0x7A) ++#define REG_SC_BK05_7B_L _PK_L_(0x05, 0x7B) ++#define REG_SC_BK05_7B_H _PK_H_(0x05, 0x7B) ++#define REG_SC_BK05_7C_L _PK_L_(0x05, 0x7C) ++#define REG_SC_BK05_7C_H _PK_H_(0x05, 0x7C) ++#define REG_SC_BK05_7D_L _PK_L_(0x05, 0x7D) ++#define REG_SC_BK05_7D_H _PK_H_(0x05, 0x7D) ++#define REG_SC_BK05_7E_L _PK_L_(0x05, 0x7E) ++#define REG_SC_BK05_7E_H _PK_H_(0x05, 0x7E) ++#define REG_SC_BK05_7F_L _PK_L_(0x05, 0x7F) ++#define REG_SC_BK05_7F_H _PK_H_(0x05, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK06_00_L _PK_L_(0x06, 0x00) ++#define REG_SC_BK06_00_H _PK_H_(0x06, 0x00) ++#define REG_SC_BK06_01_L _PK_L_(0x06, 0x01) ++#define REG_SC_BK06_01_H _PK_H_(0x06, 0x01) ++#define REG_SC_BK06_02_L _PK_L_(0x06, 0x02) ++#define REG_SC_BK06_02_H _PK_H_(0x06, 0x02) ++#define REG_SC_BK06_03_L _PK_L_(0x06, 0x03) ++#define REG_SC_BK06_03_H _PK_H_(0x06, 0x03) ++#define REG_SC_BK06_04_L _PK_L_(0x06, 0x04) ++#define REG_SC_BK06_04_H _PK_H_(0x06, 0x04) ++#define REG_SC_BK06_05_L _PK_L_(0x06, 0x05) ++#define REG_SC_BK06_05_H _PK_H_(0x06, 0x05) ++#define REG_SC_BK06_06_L _PK_L_(0x06, 0x06) ++#define REG_SC_BK06_06_H _PK_H_(0x06, 0x06) ++#define REG_SC_BK06_07_L _PK_L_(0x06, 0x07) ++#define REG_SC_BK06_07_H _PK_H_(0x06, 0x07) ++#define REG_SC_BK06_08_L _PK_L_(0x06, 0x08) ++#define REG_SC_BK06_08_H _PK_H_(0x06, 0x08) ++#define REG_SC_BK06_09_L _PK_L_(0x06, 0x09) ++#define REG_SC_BK06_09_H _PK_H_(0x06, 0x09) ++#define REG_SC_BK06_0A_L _PK_L_(0x06, 0x0A) ++#define REG_SC_BK06_0A_H _PK_H_(0x06, 0x0A) ++#define REG_SC_BK06_0B_L _PK_L_(0x06, 0x0B) ++#define REG_SC_BK06_0B_H _PK_H_(0x06, 0x0B) ++#define REG_SC_BK06_0C_L _PK_L_(0x06, 0x0C) ++#define REG_SC_BK06_0C_H _PK_H_(0x06, 0x0C) ++#define REG_SC_BK06_0D_L _PK_L_(0x06, 0x0D) ++#define REG_SC_BK06_0D_H _PK_H_(0x06, 0x0D) ++#define REG_SC_BK06_0E_L _PK_L_(0x06, 0x0E) ++#define REG_SC_BK06_0E_H _PK_H_(0x06, 0x0E) ++#define REG_SC_BK06_0F_L _PK_L_(0x06, 0x0F) ++#define REG_SC_BK06_0F_H _PK_H_(0x06, 0x0F) ++#define REG_SC_BK06_10_L _PK_L_(0x06, 0x10) ++#define REG_SC_BK06_10_H _PK_H_(0x06, 0x10) ++#define REG_SC_BK06_11_L _PK_L_(0x06, 0x11) ++#define REG_SC_BK06_11_H _PK_H_(0x06, 0x11) ++#define REG_SC_BK06_12_L _PK_L_(0x06, 0x12) ++#define REG_SC_BK06_12_H _PK_H_(0x06, 0x12) ++#define REG_SC_BK06_13_L _PK_L_(0x06, 0x13) ++#define REG_SC_BK06_13_H _PK_H_(0x06, 0x13) ++#define REG_SC_BK06_14_L _PK_L_(0x06, 0x14) ++#define REG_SC_BK06_14_H _PK_H_(0x06, 0x14) ++#define REG_SC_BK06_15_L _PK_L_(0x06, 0x15) ++#define REG_SC_BK06_15_H _PK_H_(0x06, 0x15) ++#define REG_SC_BK06_16_L _PK_L_(0x06, 0x16) ++#define REG_SC_BK06_16_H _PK_H_(0x06, 0x16) ++#define REG_SC_BK06_17_L _PK_L_(0x06, 0x17) ++#define REG_SC_BK06_17_H _PK_H_(0x06, 0x17) ++#define REG_SC_BK06_18_L _PK_L_(0x06, 0x18) ++#define REG_SC_BK06_18_H _PK_H_(0x06, 0x18) ++#define REG_SC_BK06_19_L _PK_L_(0x06, 0x19) ++#define REG_SC_BK06_19_H _PK_H_(0x06, 0x19) ++#define REG_SC_BK06_1A_L _PK_L_(0x06, 0x1A) ++#define REG_SC_BK06_1A_H _PK_H_(0x06, 0x1A) ++#define REG_SC_BK06_1B_L _PK_L_(0x06, 0x1B) ++#define REG_SC_BK06_1B_H _PK_H_(0x06, 0x1B) ++#define REG_SC_BK06_1C_L _PK_L_(0x06, 0x1C) ++#define REG_SC_BK06_1C_H _PK_H_(0x06, 0x1C) ++#define REG_SC_BK06_1D_L _PK_L_(0x06, 0x1D) ++#define REG_SC_BK06_1D_H _PK_H_(0x06, 0x1D) ++#define REG_SC_BK06_1E_L _PK_L_(0x06, 0x1E) ++#define REG_SC_BK06_1E_H _PK_H_(0x06, 0x1E) ++#define REG_SC_BK06_1F_L _PK_L_(0x06, 0x1F) ++#define REG_SC_BK06_1F_H _PK_H_(0x06, 0x1F) ++#define REG_SC_BK06_20_L _PK_L_(0x06, 0x20) ++#define REG_SC_BK06_20_H _PK_H_(0x06, 0x20) ++#define REG_SC_BK06_21_L _PK_L_(0x06, 0x21) ++#define REG_SC_BK06_21_H _PK_H_(0x06, 0x21) ++#define REG_SC_BK06_22_L _PK_L_(0x06, 0x22) ++#define REG_SC_BK06_22_H _PK_H_(0x06, 0x22) ++#define REG_SC_BK06_23_L _PK_L_(0x06, 0x23) ++#define REG_SC_BK06_23_H _PK_H_(0x06, 0x23) ++#define REG_SC_BK06_24_L _PK_L_(0x06, 0x24) ++#define REG_SC_BK06_24_H _PK_H_(0x06, 0x24) ++#define REG_SC_BK06_25_L _PK_L_(0x06, 0x25) ++#define REG_SC_BK06_25_H _PK_H_(0x06, 0x25) ++#define REG_SC_BK06_26_L _PK_L_(0x06, 0x26) ++#define REG_SC_BK06_26_H _PK_H_(0x06, 0x26) ++#define REG_SC_BK06_27_L _PK_L_(0x06, 0x27) ++#define REG_SC_BK06_27_H _PK_H_(0x06, 0x27) ++#define REG_SC_BK06_28_L _PK_L_(0x06, 0x28) ++#define REG_SC_BK06_28_H _PK_H_(0x06, 0x28) ++#define REG_SC_BK06_29_L _PK_L_(0x06, 0x29) ++#define REG_SC_BK06_29_H _PK_H_(0x06, 0x29) ++#define REG_SC_BK06_2A_L _PK_L_(0x06, 0x2A) ++#define REG_SC_BK06_2A_H _PK_H_(0x06, 0x2A) ++#define REG_SC_BK06_2B_L _PK_L_(0x06, 0x2B) ++#define REG_SC_BK06_2B_H _PK_H_(0x06, 0x2B) ++#define REG_SC_BK06_2C_L _PK_L_(0x06, 0x2C) ++#define REG_SC_BK06_2C_H _PK_H_(0x06, 0x2C) ++#define REG_SC_BK06_2D_L _PK_L_(0x06, 0x2D) ++#define REG_SC_BK06_2D_H _PK_H_(0x06, 0x2D) ++#define REG_SC_BK06_2E_L _PK_L_(0x06, 0x2E) ++#define REG_SC_BK06_2E_H _PK_H_(0x06, 0x2E) ++#define REG_SC_BK06_2F_L _PK_L_(0x06, 0x2F) ++#define REG_SC_BK06_2F_H _PK_H_(0x06, 0x2F) ++#define REG_SC_BK06_30_L _PK_L_(0x06, 0x30) ++#define REG_SC_BK06_30_H _PK_H_(0x06, 0x30) ++#define REG_SC_BK06_31_L _PK_L_(0x06, 0x31) ++#define REG_SC_BK06_31_H _PK_H_(0x06, 0x31) ++#define REG_SC_BK06_32_L _PK_L_(0x06, 0x32) ++#define REG_SC_BK06_32_H _PK_H_(0x06, 0x32) ++#define REG_SC_BK06_33_L _PK_L_(0x06, 0x33) ++#define REG_SC_BK06_33_H _PK_H_(0x06, 0x33) ++#define REG_SC_BK06_34_L _PK_L_(0x06, 0x34) ++#define REG_SC_BK06_34_H _PK_H_(0x06, 0x34) ++#define REG_SC_BK06_35_L _PK_L_(0x06, 0x35) ++#define REG_SC_BK06_35_H _PK_H_(0x06, 0x35) ++#define REG_SC_BK06_36_L _PK_L_(0x06, 0x36) ++#define REG_SC_BK06_36_H _PK_H_(0x06, 0x36) ++#define REG_SC_BK06_37_L _PK_L_(0x06, 0x37) ++#define REG_SC_BK06_37_H _PK_H_(0x06, 0x37) ++#define REG_SC_BK06_38_L _PK_L_(0x06, 0x38) ++#define REG_SC_BK06_38_H _PK_H_(0x06, 0x38) ++#define REG_SC_BK06_39_L _PK_L_(0x06, 0x39) ++#define REG_SC_BK06_39_H _PK_H_(0x06, 0x39) ++#define REG_SC_BK06_3A_L _PK_L_(0x06, 0x3A) ++#define REG_SC_BK06_3A_H _PK_H_(0x06, 0x3A) ++#define REG_SC_BK06_3B_L _PK_L_(0x06, 0x3B) ++#define REG_SC_BK06_3B_H _PK_H_(0x06, 0x3B) ++#define REG_SC_BK06_3C_L _PK_L_(0x06, 0x3C) ++#define REG_SC_BK06_3C_H _PK_H_(0x06, 0x3C) ++#define REG_SC_BK06_3D_L _PK_L_(0x06, 0x3D) ++#define REG_SC_BK06_3D_H _PK_H_(0x06, 0x3D) ++#define REG_SC_BK06_3E_L _PK_L_(0x06, 0x3E) ++#define REG_SC_BK06_3E_H _PK_H_(0x06, 0x3E) ++#define REG_SC_BK06_3F_L _PK_L_(0x06, 0x3F) ++#define REG_SC_BK06_3F_H _PK_H_(0x06, 0x3F) ++#define REG_SC_BK06_40_L _PK_L_(0x06, 0x40) ++#define REG_SC_BK06_40_H _PK_H_(0x06, 0x40) ++#define REG_SC_BK06_41_L _PK_L_(0x06, 0x41) ++#define REG_SC_BK06_41_H _PK_H_(0x06, 0x41) ++#define REG_SC_BK06_42_L _PK_L_(0x06, 0x42) ++#define REG_SC_BK06_42_H _PK_H_(0x06, 0x42) ++#define REG_SC_BK06_43_L _PK_L_(0x06, 0x43) ++#define REG_SC_BK06_43_H _PK_H_(0x06, 0x43) ++#define REG_SC_BK06_44_L _PK_L_(0x06, 0x44) ++#define REG_SC_BK06_44_H _PK_H_(0x06, 0x44) ++#define REG_SC_BK06_45_L _PK_L_(0x06, 0x45) ++#define REG_SC_BK06_45_H _PK_H_(0x06, 0x45) ++#define REG_SC_BK06_46_L _PK_L_(0x06, 0x46) ++#define REG_SC_BK06_46_H _PK_H_(0x06, 0x46) ++#define REG_SC_BK06_47_L _PK_L_(0x06, 0x47) ++#define REG_SC_BK06_47_H _PK_H_(0x06, 0x47) ++#define REG_SC_BK06_48_L _PK_L_(0x06, 0x48) ++#define REG_SC_BK06_48_H _PK_H_(0x06, 0x48) ++#define REG_SC_BK06_49_L _PK_L_(0x06, 0x49) ++#define REG_SC_BK06_49_H _PK_H_(0x06, 0x49) ++#define REG_SC_BK06_4A_L _PK_L_(0x06, 0x4A) ++#define REG_SC_BK06_4A_H _PK_H_(0x06, 0x4A) ++#define REG_SC_BK06_4B_L _PK_L_(0x06, 0x4B) ++#define REG_SC_BK06_4B_H _PK_H_(0x06, 0x4B) ++#define REG_SC_BK06_4C_L _PK_L_(0x06, 0x4C) ++#define REG_SC_BK06_4C_H _PK_H_(0x06, 0x4C) ++#define REG_SC_BK06_4D_L _PK_L_(0x06, 0x4D) ++#define REG_SC_BK06_4D_H _PK_H_(0x06, 0x4D) ++#define REG_SC_BK06_4E_L _PK_L_(0x06, 0x4E) ++#define REG_SC_BK06_4E_H _PK_H_(0x06, 0x4E) ++#define REG_SC_BK06_4F_L _PK_L_(0x06, 0x4F) ++#define REG_SC_BK06_4F_H _PK_H_(0x06, 0x4F) ++#define REG_SC_BK06_50_L _PK_L_(0x06, 0x50) ++#define REG_SC_BK06_50_H _PK_H_(0x06, 0x50) ++#define REG_SC_BK06_51_L _PK_L_(0x06, 0x51) ++#define REG_SC_BK06_51_H _PK_H_(0x06, 0x51) ++#define REG_SC_BK06_52_L _PK_L_(0x06, 0x52) ++#define REG_SC_BK06_52_H _PK_H_(0x06, 0x52) ++#define REG_SC_BK06_53_L _PK_L_(0x06, 0x53) ++#define REG_SC_BK06_53_H _PK_H_(0x06, 0x53) ++#define REG_SC_BK06_54_L _PK_L_(0x06, 0x54) ++#define REG_SC_BK06_54_H _PK_H_(0x06, 0x54) ++#define REG_SC_BK06_55_L _PK_L_(0x06, 0x55) ++#define REG_SC_BK06_55_H _PK_H_(0x06, 0x55) ++#define REG_SC_BK06_56_L _PK_L_(0x06, 0x56) ++#define REG_SC_BK06_56_H _PK_H_(0x06, 0x56) ++#define REG_SC_BK06_57_L _PK_L_(0x06, 0x57) ++#define REG_SC_BK06_57_H _PK_H_(0x06, 0x57) ++#define REG_SC_BK06_58_L _PK_L_(0x06, 0x58) ++#define REG_SC_BK06_58_H _PK_H_(0x06, 0x58) ++#define REG_SC_BK06_59_L _PK_L_(0x06, 0x59) ++#define REG_SC_BK06_59_H _PK_H_(0x06, 0x59) ++#define REG_SC_BK06_5A_L _PK_L_(0x06, 0x5A) ++#define REG_SC_BK06_5A_H _PK_H_(0x06, 0x5A) ++#define REG_SC_BK06_5B_L _PK_L_(0x06, 0x5B) ++#define REG_SC_BK06_5B_H _PK_H_(0x06, 0x5B) ++#define REG_SC_BK06_5C_L _PK_L_(0x06, 0x5C) ++#define REG_SC_BK06_5C_H _PK_H_(0x06, 0x5C) ++#define REG_SC_BK06_5D_L _PK_L_(0x06, 0x5D) ++#define REG_SC_BK06_5D_H _PK_H_(0x06, 0x5D) ++#define REG_SC_BK06_5E_L _PK_L_(0x06, 0x5E) ++#define REG_SC_BK06_5E_H _PK_H_(0x06, 0x5E) ++#define REG_SC_BK06_5F_L _PK_L_(0x06, 0x5F) ++#define REG_SC_BK06_5F_H _PK_H_(0x06, 0x5F) ++#define REG_SC_BK06_60_L _PK_L_(0x06, 0x60) ++#define REG_SC_BK06_60_H _PK_H_(0x06, 0x60) ++#define REG_SC_BK06_61_L _PK_L_(0x06, 0x61) ++#define REG_SC_BK06_61_H _PK_H_(0x06, 0x61) ++#define REG_SC_BK06_62_L _PK_L_(0x06, 0x62) ++#define REG_SC_BK06_62_H _PK_H_(0x06, 0x62) ++#define REG_SC_BK06_63_L _PK_L_(0x06, 0x63) ++#define REG_SC_BK06_63_H _PK_H_(0x06, 0x63) ++#define REG_SC_BK06_64_L _PK_L_(0x06, 0x64) ++#define REG_SC_BK06_64_H _PK_H_(0x06, 0x64) ++#define REG_SC_BK06_65_L _PK_L_(0x06, 0x65) ++#define REG_SC_BK06_65_H _PK_H_(0x06, 0x65) ++#define REG_SC_BK06_66_L _PK_L_(0x06, 0x66) ++#define REG_SC_BK06_66_H _PK_H_(0x06, 0x66) ++#define REG_SC_BK06_67_L _PK_L_(0x06, 0x67) ++#define REG_SC_BK06_67_H _PK_H_(0x06, 0x67) ++#define REG_SC_BK06_68_L _PK_L_(0x06, 0x68) ++#define REG_SC_BK06_68_H _PK_H_(0x06, 0x68) ++#define REG_SC_BK06_69_L _PK_L_(0x06, 0x69) ++#define REG_SC_BK06_69_H _PK_H_(0x06, 0x69) ++#define REG_SC_BK06_6A_L _PK_L_(0x06, 0x6A) ++#define REG_SC_BK06_6A_H _PK_H_(0x06, 0x6A) ++#define REG_SC_BK06_6B_L _PK_L_(0x06, 0x6B) ++#define REG_SC_BK06_6B_H _PK_H_(0x06, 0x6B) ++#define REG_SC_BK06_6C_L _PK_L_(0x06, 0x6C) ++#define REG_SC_BK06_6C_H _PK_H_(0x06, 0x6C) ++#define REG_SC_BK06_6D_L _PK_L_(0x06, 0x6D) ++#define REG_SC_BK06_6D_H _PK_H_(0x06, 0x6D) ++#define REG_SC_BK06_6E_L _PK_L_(0x06, 0x6E) ++#define REG_SC_BK06_6E_H _PK_H_(0x06, 0x6E) ++#define REG_SC_BK06_6F_L _PK_L_(0x06, 0x6F) ++#define REG_SC_BK06_6F_H _PK_H_(0x06, 0x6F) ++#define REG_SC_BK06_70_L _PK_L_(0x06, 0x70) ++#define REG_SC_BK06_70_H _PK_H_(0x06, 0x70) ++#define REG_SC_BK06_71_L _PK_L_(0x06, 0x71) ++#define REG_SC_BK06_71_H _PK_H_(0x06, 0x71) ++#define REG_SC_BK06_72_L _PK_L_(0x06, 0x72) ++#define REG_SC_BK06_72_H _PK_H_(0x06, 0x72) ++#define REG_SC_BK06_73_L _PK_L_(0x06, 0x73) ++#define REG_SC_BK06_73_H _PK_H_(0x06, 0x73) ++#define REG_SC_BK06_74_L _PK_L_(0x06, 0x74) ++#define REG_SC_BK06_74_H _PK_H_(0x06, 0x74) ++#define REG_SC_BK06_75_L _PK_L_(0x06, 0x75) ++#define REG_SC_BK06_75_H _PK_H_(0x06, 0x75) ++#define REG_SC_BK06_76_L _PK_L_(0x06, 0x76) ++#define REG_SC_BK06_76_H _PK_H_(0x06, 0x76) ++#define REG_SC_BK06_77_L _PK_L_(0x06, 0x77) ++#define REG_SC_BK06_77_H _PK_H_(0x06, 0x77) ++#define REG_SC_BK06_78_L _PK_L_(0x06, 0x78) ++#define REG_SC_BK06_78_H _PK_H_(0x06, 0x78) ++#define REG_SC_BK06_79_L _PK_L_(0x06, 0x79) ++#define REG_SC_BK06_79_H _PK_H_(0x06, 0x79) ++#define REG_SC_BK06_7A_L _PK_L_(0x06, 0x7A) ++#define REG_SC_BK06_7A_H _PK_H_(0x06, 0x7A) ++#define REG_SC_BK06_7B_L _PK_L_(0x06, 0x7B) ++#define REG_SC_BK06_7B_H _PK_H_(0x06, 0x7B) ++#define REG_SC_BK06_7C_L _PK_L_(0x06, 0x7C) ++#define REG_SC_BK06_7C_H _PK_H_(0x06, 0x7C) ++#define REG_SC_BK06_7D_L _PK_L_(0x06, 0x7D) ++#define REG_SC_BK06_7D_H _PK_H_(0x06, 0x7D) ++#define REG_SC_BK06_7E_L _PK_L_(0x06, 0x7E) ++#define REG_SC_BK06_7E_H _PK_H_(0x06, 0x7E) ++#define REG_SC_BK06_7F_L _PK_L_(0x06, 0x7F) ++#define REG_SC_BK06_7F_H _PK_H_(0x06, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK07_00_L _PK_L_(0x07, 0x00) ++#define REG_SC_BK07_00_H _PK_H_(0x07, 0x00) ++#define REG_SC_BK07_01_L _PK_L_(0x07, 0x01) ++#define REG_SC_BK07_01_H _PK_H_(0x07, 0x01) ++#define REG_SC_BK07_02_L _PK_L_(0x07, 0x02) ++#define REG_SC_BK07_02_H _PK_H_(0x07, 0x02) ++#define REG_SC_BK07_03_L _PK_L_(0x07, 0x03) ++#define REG_SC_BK07_03_H _PK_H_(0x07, 0x03) ++#define REG_SC_BK07_04_L _PK_L_(0x07, 0x04) ++#define REG_SC_BK07_04_H _PK_H_(0x07, 0x04) ++#define REG_SC_BK07_05_L _PK_L_(0x07, 0x05) ++#define REG_SC_BK07_05_H _PK_H_(0x07, 0x05) ++#define REG_SC_BK07_06_L _PK_L_(0x07, 0x06) ++#define REG_SC_BK07_06_H _PK_H_(0x07, 0x06) ++#define REG_SC_BK07_07_L _PK_L_(0x07, 0x07) ++#define REG_SC_BK07_07_H _PK_H_(0x07, 0x07) ++#define REG_SC_BK07_08_L _PK_L_(0x07, 0x08) ++#define REG_SC_BK07_08_H _PK_H_(0x07, 0x08) ++#define REG_SC_BK07_09_L _PK_L_(0x07, 0x09) ++#define REG_SC_BK07_09_H _PK_H_(0x07, 0x09) ++#define REG_SC_BK07_0A_L _PK_L_(0x07, 0x0A) ++#define REG_SC_BK07_0A_H _PK_H_(0x07, 0x0A) ++#define REG_SC_BK07_0B_L _PK_L_(0x07, 0x0B) ++#define REG_SC_BK07_0B_H _PK_H_(0x07, 0x0B) ++#define REG_SC_BK07_0C_L _PK_L_(0x07, 0x0C) ++#define REG_SC_BK07_0C_H _PK_H_(0x07, 0x0C) ++#define REG_SC_BK07_0D_L _PK_L_(0x07, 0x0D) ++#define REG_SC_BK07_0D_H _PK_H_(0x07, 0x0D) ++#define REG_SC_BK07_0E_L _PK_L_(0x07, 0x0E) ++#define REG_SC_BK07_0E_H _PK_H_(0x07, 0x0E) ++#define REG_SC_BK07_0F_L _PK_L_(0x07, 0x0F) ++#define REG_SC_BK07_0F_H _PK_H_(0x07, 0x0F) ++#define REG_SC_BK07_10_L _PK_L_(0x07, 0x10) ++#define REG_SC_BK07_10_H _PK_H_(0x07, 0x10) ++#define REG_SC_BK07_11_L _PK_L_(0x07, 0x11) ++#define REG_SC_BK07_11_H _PK_H_(0x07, 0x11) ++#define REG_SC_BK07_12_L _PK_L_(0x07, 0x12) ++#define REG_SC_BK07_12_H _PK_H_(0x07, 0x12) ++#define REG_SC_BK07_13_L _PK_L_(0x07, 0x13) ++#define REG_SC_BK07_13_H _PK_H_(0x07, 0x13) ++#define REG_SC_BK07_14_L _PK_L_(0x07, 0x14) ++#define REG_SC_BK07_14_H _PK_H_(0x07, 0x14) ++#define REG_SC_BK07_15_L _PK_L_(0x07, 0x15) ++#define REG_SC_BK07_15_H _PK_H_(0x07, 0x15) ++#define REG_SC_BK07_16_L _PK_L_(0x07, 0x16) ++#define REG_SC_BK07_16_H _PK_H_(0x07, 0x16) ++#define REG_SC_BK07_17_L _PK_L_(0x07, 0x17) ++#define REG_SC_BK07_17_H _PK_H_(0x07, 0x17) ++#define REG_SC_BK07_18_L _PK_L_(0x07, 0x18) ++#define REG_SC_BK07_18_H _PK_H_(0x07, 0x18) ++#define REG_SC_BK07_19_L _PK_L_(0x07, 0x19) ++#define REG_SC_BK07_19_H _PK_H_(0x07, 0x19) ++#define REG_SC_BK07_1A_L _PK_L_(0x07, 0x1A) ++#define REG_SC_BK07_1A_H _PK_H_(0x07, 0x1A) ++#define REG_SC_BK07_1B_L _PK_L_(0x07, 0x1B) ++#define REG_SC_BK07_1B_H _PK_H_(0x07, 0x1B) ++#define REG_SC_BK07_1C_L _PK_L_(0x07, 0x1C) ++#define REG_SC_BK07_1C_H _PK_H_(0x07, 0x1C) ++#define REG_SC_BK07_1D_L _PK_L_(0x07, 0x1D) ++#define REG_SC_BK07_1D_H _PK_H_(0x07, 0x1D) ++#define REG_SC_BK07_1E_L _PK_L_(0x07, 0x1E) ++#define REG_SC_BK07_1E_H _PK_H_(0x07, 0x1E) ++#define REG_SC_BK07_1F_L _PK_L_(0x07, 0x1F) ++#define REG_SC_BK07_1F_H _PK_H_(0x07, 0x1F) ++#define REG_SC_BK07_20_L _PK_L_(0x07, 0x20) ++#define REG_SC_BK07_20_H _PK_H_(0x07, 0x20) ++#define REG_SC_BK07_21_L _PK_L_(0x07, 0x21) ++#define REG_SC_BK07_21_H _PK_H_(0x07, 0x21) ++#define REG_SC_BK07_22_L _PK_L_(0x07, 0x22) ++#define REG_SC_BK07_22_H _PK_H_(0x07, 0x22) ++#define REG_SC_BK07_23_L _PK_L_(0x07, 0x23) ++#define REG_SC_BK07_23_H _PK_H_(0x07, 0x23) ++#define REG_SC_BK07_24_L _PK_L_(0x07, 0x24) ++#define REG_SC_BK07_24_H _PK_H_(0x07, 0x24) ++#define REG_SC_BK07_25_L _PK_L_(0x07, 0x25) ++#define REG_SC_BK07_25_H _PK_H_(0x07, 0x25) ++#define REG_SC_BK07_26_L _PK_L_(0x07, 0x26) ++#define REG_SC_BK07_26_H _PK_H_(0x07, 0x26) ++#define REG_SC_BK07_27_L _PK_L_(0x07, 0x27) ++#define REG_SC_BK07_27_H _PK_H_(0x07, 0x27) ++#define REG_SC_BK07_28_L _PK_L_(0x07, 0x28) ++#define REG_SC_BK07_28_H _PK_H_(0x07, 0x28) ++#define REG_SC_BK07_29_L _PK_L_(0x07, 0x29) ++#define REG_SC_BK07_29_H _PK_H_(0x07, 0x29) ++#define REG_SC_BK07_2A_L _PK_L_(0x07, 0x2A) ++#define REG_SC_BK07_2A_H _PK_H_(0x07, 0x2A) ++#define REG_SC_BK07_2B_L _PK_L_(0x07, 0x2B) ++#define REG_SC_BK07_2B_H _PK_H_(0x07, 0x2B) ++#define REG_SC_BK07_2C_L _PK_L_(0x07, 0x2C) ++#define REG_SC_BK07_2C_H _PK_H_(0x07, 0x2C) ++#define REG_SC_BK07_2D_L _PK_L_(0x07, 0x2D) ++#define REG_SC_BK07_2D_H _PK_H_(0x07, 0x2D) ++#define REG_SC_BK07_2E_L _PK_L_(0x07, 0x2E) ++#define REG_SC_BK07_2E_H _PK_H_(0x07, 0x2E) ++#define REG_SC_BK07_2F_L _PK_L_(0x07, 0x2F) ++#define REG_SC_BK07_2F_H _PK_H_(0x07, 0x2F) ++#define REG_SC_BK07_30_L _PK_L_(0x07, 0x30) ++#define REG_SC_BK07_30_H _PK_H_(0x07, 0x30) ++#define REG_SC_BK07_31_L _PK_L_(0x07, 0x31) ++#define REG_SC_BK07_31_H _PK_H_(0x07, 0x31) ++#define REG_SC_BK07_32_L _PK_L_(0x07, 0x32) ++#define REG_SC_BK07_32_H _PK_H_(0x07, 0x32) ++#define REG_SC_BK07_33_L _PK_L_(0x07, 0x33) ++#define REG_SC_BK07_33_H _PK_H_(0x07, 0x33) ++#define REG_SC_BK07_34_L _PK_L_(0x07, 0x34) ++#define REG_SC_BK07_34_H _PK_H_(0x07, 0x34) ++#define REG_SC_BK07_35_L _PK_L_(0x07, 0x35) ++#define REG_SC_BK07_35_H _PK_H_(0x07, 0x35) ++#define REG_SC_BK07_36_L _PK_L_(0x07, 0x36) ++#define REG_SC_BK07_36_H _PK_H_(0x07, 0x36) ++#define REG_SC_BK07_37_L _PK_L_(0x07, 0x37) ++#define REG_SC_BK07_37_H _PK_H_(0x07, 0x37) ++#define REG_SC_BK07_38_L _PK_L_(0x07, 0x38) ++#define REG_SC_BK07_38_H _PK_H_(0x07, 0x38) ++#define REG_SC_BK07_39_L _PK_L_(0x07, 0x39) ++#define REG_SC_BK07_39_H _PK_H_(0x07, 0x39) ++#define REG_SC_BK07_3A_L _PK_L_(0x07, 0x3A) ++#define REG_SC_BK07_3A_H _PK_H_(0x07, 0x3A) ++#define REG_SC_BK07_3B_L _PK_L_(0x07, 0x3B) ++#define REG_SC_BK07_3B_H _PK_H_(0x07, 0x3B) ++#define REG_SC_BK07_3C_L _PK_L_(0x07, 0x3C) ++#define REG_SC_BK07_3C_H _PK_H_(0x07, 0x3C) ++#define REG_SC_BK07_3D_L _PK_L_(0x07, 0x3D) ++#define REG_SC_BK07_3D_H _PK_H_(0x07, 0x3D) ++#define REG_SC_BK07_3E_L _PK_L_(0x07, 0x3E) ++#define REG_SC_BK07_3E_H _PK_H_(0x07, 0x3E) ++#define REG_SC_BK07_3F_L _PK_L_(0x07, 0x3F) ++#define REG_SC_BK07_3F_H _PK_H_(0x07, 0x3F) ++#define REG_SC_BK07_40_L _PK_L_(0x07, 0x40) ++#define REG_SC_BK07_40_H _PK_H_(0x07, 0x40) ++#define REG_SC_BK07_41_L _PK_L_(0x07, 0x41) ++#define REG_SC_BK07_41_H _PK_H_(0x07, 0x41) ++#define REG_SC_BK07_42_L _PK_L_(0x07, 0x42) ++#define REG_SC_BK07_42_H _PK_H_(0x07, 0x42) ++#define REG_SC_BK07_43_L _PK_L_(0x07, 0x43) ++#define REG_SC_BK07_43_H _PK_H_(0x07, 0x43) ++#define REG_SC_BK07_44_L _PK_L_(0x07, 0x44) ++#define REG_SC_BK07_44_H _PK_H_(0x07, 0x44) ++#define REG_SC_BK07_45_L _PK_L_(0x07, 0x45) ++#define REG_SC_BK07_45_H _PK_H_(0x07, 0x45) ++#define REG_SC_BK07_46_L _PK_L_(0x07, 0x46) ++#define REG_SC_BK07_46_H _PK_H_(0x07, 0x46) ++#define REG_SC_BK07_47_L _PK_L_(0x07, 0x47) ++#define REG_SC_BK07_47_H _PK_H_(0x07, 0x47) ++#define REG_SC_BK07_48_L _PK_L_(0x07, 0x48) ++#define REG_SC_BK07_48_H _PK_H_(0x07, 0x48) ++#define REG_SC_BK07_49_L _PK_L_(0x07, 0x49) ++#define REG_SC_BK07_49_H _PK_H_(0x07, 0x49) ++#define REG_SC_BK07_4A_L _PK_L_(0x07, 0x4A) ++#define REG_SC_BK07_4A_H _PK_H_(0x07, 0x4A) ++#define REG_SC_BK07_4B_L _PK_L_(0x07, 0x4B) ++#define REG_SC_BK07_4B_H _PK_H_(0x07, 0x4B) ++#define REG_SC_BK07_4C_L _PK_L_(0x07, 0x4C) ++#define REG_SC_BK07_4C_H _PK_H_(0x07, 0x4C) ++#define REG_SC_BK07_4D_L _PK_L_(0x07, 0x4D) ++#define REG_SC_BK07_4D_H _PK_H_(0x07, 0x4D) ++#define REG_SC_BK07_4E_L _PK_L_(0x07, 0x4E) ++#define REG_SC_BK07_4E_H _PK_H_(0x07, 0x4E) ++#define REG_SC_BK07_4F_L _PK_L_(0x07, 0x4F) ++#define REG_SC_BK07_4F_H _PK_H_(0x07, 0x4F) ++#define REG_SC_BK07_50_L _PK_L_(0x07, 0x50) ++#define REG_SC_BK07_50_H _PK_H_(0x07, 0x50) ++#define REG_SC_BK07_51_L _PK_L_(0x07, 0x51) ++#define REG_SC_BK07_51_H _PK_H_(0x07, 0x51) ++#define REG_SC_BK07_52_L _PK_L_(0x07, 0x52) ++#define REG_SC_BK07_52_H _PK_H_(0x07, 0x52) ++#define REG_SC_BK07_53_L _PK_L_(0x07, 0x53) ++#define REG_SC_BK07_53_H _PK_H_(0x07, 0x53) ++#define REG_SC_BK07_54_L _PK_L_(0x07, 0x54) ++#define REG_SC_BK07_54_H _PK_H_(0x07, 0x54) ++#define REG_SC_BK07_55_L _PK_L_(0x07, 0x55) ++#define REG_SC_BK07_55_H _PK_H_(0x07, 0x55) ++#define REG_SC_BK07_56_L _PK_L_(0x07, 0x56) ++#define REG_SC_BK07_56_H _PK_H_(0x07, 0x56) ++#define REG_SC_BK07_57_L _PK_L_(0x07, 0x57) ++#define REG_SC_BK07_57_H _PK_H_(0x07, 0x57) ++#define REG_SC_BK07_58_L _PK_L_(0x07, 0x58) ++#define REG_SC_BK07_58_H _PK_H_(0x07, 0x58) ++#define REG_SC_BK07_59_L _PK_L_(0x07, 0x59) ++#define REG_SC_BK07_59_H _PK_H_(0x07, 0x59) ++#define REG_SC_BK07_5A_L _PK_L_(0x07, 0x5A) ++#define REG_SC_BK07_5A_H _PK_H_(0x07, 0x5A) ++#define REG_SC_BK07_5B_L _PK_L_(0x07, 0x5B) ++#define REG_SC_BK07_5B_H _PK_H_(0x07, 0x5B) ++#define REG_SC_BK07_5C_L _PK_L_(0x07, 0x5C) ++#define REG_SC_BK07_5C_H _PK_H_(0x07, 0x5C) ++#define REG_SC_BK07_5D_L _PK_L_(0x07, 0x5D) ++#define REG_SC_BK07_5D_H _PK_H_(0x07, 0x5D) ++#define REG_SC_BK07_5E_L _PK_L_(0x07, 0x5E) ++#define REG_SC_BK07_5E_H _PK_H_(0x07, 0x5E) ++#define REG_SC_BK07_5F_L _PK_L_(0x07, 0x5F) ++#define REG_SC_BK07_5F_H _PK_H_(0x07, 0x5F) ++#define REG_SC_BK07_60_L _PK_L_(0x07, 0x60) ++#define REG_SC_BK07_60_H _PK_H_(0x07, 0x60) ++#define REG_SC_BK07_61_L _PK_L_(0x07, 0x61) ++#define REG_SC_BK07_61_H _PK_H_(0x07, 0x61) ++#define REG_SC_BK07_62_L _PK_L_(0x07, 0x62) ++#define REG_SC_BK07_62_H _PK_H_(0x07, 0x62) ++#define REG_SC_BK07_63_L _PK_L_(0x07, 0x63) ++#define REG_SC_BK07_63_H _PK_H_(0x07, 0x63) ++#define REG_SC_BK07_64_L _PK_L_(0x07, 0x64) ++#define REG_SC_BK07_64_H _PK_H_(0x07, 0x64) ++#define REG_SC_BK07_65_L _PK_L_(0x07, 0x65) ++#define REG_SC_BK07_65_H _PK_H_(0x07, 0x65) ++#define REG_SC_BK07_66_L _PK_L_(0x07, 0x66) ++#define REG_SC_BK07_66_H _PK_H_(0x07, 0x66) ++#define REG_SC_BK07_67_L _PK_L_(0x07, 0x67) ++#define REG_SC_BK07_67_H _PK_H_(0x07, 0x67) ++#define REG_SC_BK07_68_L _PK_L_(0x07, 0x68) ++#define REG_SC_BK07_68_H _PK_H_(0x07, 0x68) ++#define REG_SC_BK07_69_L _PK_L_(0x07, 0x69) ++#define REG_SC_BK07_69_H _PK_H_(0x07, 0x69) ++#define REG_SC_BK07_6A_L _PK_L_(0x07, 0x6A) ++#define REG_SC_BK07_6A_H _PK_H_(0x07, 0x6A) ++#define REG_SC_BK07_6B_L _PK_L_(0x07, 0x6B) ++#define REG_SC_BK07_6B_H _PK_H_(0x07, 0x6B) ++#define REG_SC_BK07_6C_L _PK_L_(0x07, 0x6C) ++#define REG_SC_BK07_6C_H _PK_H_(0x07, 0x6C) ++#define REG_SC_BK07_6D_L _PK_L_(0x07, 0x6D) ++#define REG_SC_BK07_6D_H _PK_H_(0x07, 0x6D) ++#define REG_SC_BK07_6E_L _PK_L_(0x07, 0x6E) ++#define REG_SC_BK07_6E_H _PK_H_(0x07, 0x6E) ++#define REG_SC_BK07_6F_L _PK_L_(0x07, 0x6F) ++#define REG_SC_BK07_6F_H _PK_H_(0x07, 0x6F) ++#define REG_SC_BK07_70_L _PK_L_(0x07, 0x70) ++#define REG_SC_BK07_70_H _PK_H_(0x07, 0x70) ++#define REG_SC_BK07_71_L _PK_L_(0x07, 0x71) ++#define REG_SC_BK07_71_H _PK_H_(0x07, 0x71) ++#define REG_SC_BK07_72_L _PK_L_(0x07, 0x72) ++#define REG_SC_BK07_72_H _PK_H_(0x07, 0x72) ++#define REG_SC_BK07_73_L _PK_L_(0x07, 0x73) ++#define REG_SC_BK07_73_H _PK_H_(0x07, 0x73) ++#define REG_SC_BK07_74_L _PK_L_(0x07, 0x74) ++#define REG_SC_BK07_74_H _PK_H_(0x07, 0x74) ++#define REG_SC_BK07_75_L _PK_L_(0x07, 0x75) ++#define REG_SC_BK07_75_H _PK_H_(0x07, 0x75) ++#define REG_SC_BK07_76_L _PK_L_(0x07, 0x76) ++#define REG_SC_BK07_76_H _PK_H_(0x07, 0x76) ++#define REG_SC_BK07_77_L _PK_L_(0x07, 0x77) ++#define REG_SC_BK07_77_H _PK_H_(0x07, 0x77) ++#define REG_SC_BK07_78_L _PK_L_(0x07, 0x78) ++#define REG_SC_BK07_78_H _PK_H_(0x07, 0x78) ++#define REG_SC_BK07_79_L _PK_L_(0x07, 0x79) ++#define REG_SC_BK07_79_H _PK_H_(0x07, 0x79) ++#define REG_SC_BK07_7A_L _PK_L_(0x07, 0x7A) ++#define REG_SC_BK07_7A_H _PK_H_(0x07, 0x7A) ++#define REG_SC_BK07_7B_L _PK_L_(0x07, 0x7B) ++#define REG_SC_BK07_7B_H _PK_H_(0x07, 0x7B) ++#define REG_SC_BK07_7C_L _PK_L_(0x07, 0x7C) ++#define REG_SC_BK07_7C_H _PK_H_(0x07, 0x7C) ++#define REG_SC_BK07_7D_L _PK_L_(0x07, 0x7D) ++#define REG_SC_BK07_7D_H _PK_H_(0x07, 0x7D) ++#define REG_SC_BK07_7E_L _PK_L_(0x07, 0x7E) ++#define REG_SC_BK07_7E_H _PK_H_(0x07, 0x7E) ++#define REG_SC_BK07_7F_L _PK_L_(0x07, 0x7F) ++#define REG_SC_BK07_7F_H _PK_H_(0x07, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK08_00_L _PK_L_(0x08, 0x00) ++#define REG_SC_BK08_00_H _PK_H_(0x08, 0x00) ++#define REG_SC_BK08_01_L _PK_L_(0x08, 0x01) ++#define REG_SC_BK08_01_H _PK_H_(0x08, 0x01) ++#define REG_SC_BK08_02_L _PK_L_(0x08, 0x02) ++#define REG_SC_BK08_02_H _PK_H_(0x08, 0x02) ++#define REG_SC_BK08_03_L _PK_L_(0x08, 0x03) ++#define REG_SC_BK08_03_H _PK_H_(0x08, 0x03) ++#define REG_SC_BK08_04_L _PK_L_(0x08, 0x04) ++#define REG_SC_BK08_04_H _PK_H_(0x08, 0x04) ++#define REG_SC_BK08_05_L _PK_L_(0x08, 0x05) ++#define REG_SC_BK08_05_H _PK_H_(0x08, 0x05) ++#define REG_SC_BK08_06_L _PK_L_(0x08, 0x06) ++#define REG_SC_BK08_06_H _PK_H_(0x08, 0x06) ++#define REG_SC_BK08_07_L _PK_L_(0x08, 0x07) ++#define REG_SC_BK08_07_H _PK_H_(0x08, 0x07) ++#define REG_SC_BK08_08_L _PK_L_(0x08, 0x08) ++#define REG_SC_BK08_08_H _PK_H_(0x08, 0x08) ++#define REG_SC_BK08_09_L _PK_L_(0x08, 0x09) ++#define REG_SC_BK08_09_H _PK_H_(0x08, 0x09) ++#define REG_SC_BK08_0A_L _PK_L_(0x08, 0x0A) ++#define REG_SC_BK08_0A_H _PK_H_(0x08, 0x0A) ++#define REG_SC_BK08_0B_L _PK_L_(0x08, 0x0B) ++#define REG_SC_BK08_0B_H _PK_H_(0x08, 0x0B) ++#define REG_SC_BK08_0C_L _PK_L_(0x08, 0x0C) ++#define REG_SC_BK08_0C_H _PK_H_(0x08, 0x0C) ++#define REG_SC_BK08_0D_L _PK_L_(0x08, 0x0D) ++#define REG_SC_BK08_0D_H _PK_H_(0x08, 0x0D) ++#define REG_SC_BK08_0E_L _PK_L_(0x08, 0x0E) ++#define REG_SC_BK08_0E_H _PK_H_(0x08, 0x0E) ++#define REG_SC_BK08_0F_L _PK_L_(0x08, 0x0F) ++#define REG_SC_BK08_0F_H _PK_H_(0x08, 0x0F) ++#define REG_SC_BK08_10_L _PK_L_(0x08, 0x10) ++#define REG_SC_BK08_10_H _PK_H_(0x08, 0x10) ++#define REG_SC_BK08_11_L _PK_L_(0x08, 0x11) ++#define REG_SC_BK08_11_H _PK_H_(0x08, 0x11) ++#define REG_SC_BK08_12_L _PK_L_(0x08, 0x12) ++#define REG_SC_BK08_12_H _PK_H_(0x08, 0x12) ++#define REG_SC_BK08_13_L _PK_L_(0x08, 0x13) ++#define REG_SC_BK08_13_H _PK_H_(0x08, 0x13) ++#define REG_SC_BK08_14_L _PK_L_(0x08, 0x14) ++#define REG_SC_BK08_14_H _PK_H_(0x08, 0x14) ++#define REG_SC_BK08_15_L _PK_L_(0x08, 0x15) ++#define REG_SC_BK08_15_H _PK_H_(0x08, 0x15) ++#define REG_SC_BK08_16_L _PK_L_(0x08, 0x16) ++#define REG_SC_BK08_16_H _PK_H_(0x08, 0x16) ++#define REG_SC_BK08_17_L _PK_L_(0x08, 0x17) ++#define REG_SC_BK08_17_H _PK_H_(0x08, 0x17) ++#define REG_SC_BK08_18_L _PK_L_(0x08, 0x18) ++#define REG_SC_BK08_18_H _PK_H_(0x08, 0x18) ++#define REG_SC_BK08_19_L _PK_L_(0x08, 0x19) ++#define REG_SC_BK08_19_H _PK_H_(0x08, 0x19) ++#define REG_SC_BK08_1A_L _PK_L_(0x08, 0x1A) ++#define REG_SC_BK08_1A_H _PK_H_(0x08, 0x1A) ++#define REG_SC_BK08_1B_L _PK_L_(0x08, 0x1B) ++#define REG_SC_BK08_1B_H _PK_H_(0x08, 0x1B) ++#define REG_SC_BK08_1C_L _PK_L_(0x08, 0x1C) ++#define REG_SC_BK08_1C_H _PK_H_(0x08, 0x1C) ++#define REG_SC_BK08_1D_L _PK_L_(0x08, 0x1D) ++#define REG_SC_BK08_1D_H _PK_H_(0x08, 0x1D) ++#define REG_SC_BK08_1E_L _PK_L_(0x08, 0x1E) ++#define REG_SC_BK08_1E_H _PK_H_(0x08, 0x1E) ++#define REG_SC_BK08_1F_L _PK_L_(0x08, 0x1F) ++#define REG_SC_BK08_1F_H _PK_H_(0x08, 0x1F) ++#define REG_SC_BK08_20_L _PK_L_(0x08, 0x20) ++#define REG_SC_BK08_20_H _PK_H_(0x08, 0x20) ++#define REG_SC_BK08_21_L _PK_L_(0x08, 0x21) ++#define REG_SC_BK08_21_H _PK_H_(0x08, 0x21) ++#define REG_SC_BK08_22_L _PK_L_(0x08, 0x22) ++#define REG_SC_BK08_22_H _PK_H_(0x08, 0x22) ++#define REG_SC_BK08_23_L _PK_L_(0x08, 0x23) ++#define REG_SC_BK08_23_H _PK_H_(0x08, 0x23) ++#define REG_SC_BK08_24_L _PK_L_(0x08, 0x24) ++#define REG_SC_BK08_24_H _PK_H_(0x08, 0x24) ++#define REG_SC_BK08_25_L _PK_L_(0x08, 0x25) ++#define REG_SC_BK08_25_H _PK_H_(0x08, 0x25) ++#define REG_SC_BK08_26_L _PK_L_(0x08, 0x26) ++#define REG_SC_BK08_26_H _PK_H_(0x08, 0x26) ++#define REG_SC_BK08_27_L _PK_L_(0x08, 0x27) ++#define REG_SC_BK08_27_H _PK_H_(0x08, 0x27) ++#define REG_SC_BK08_28_L _PK_L_(0x08, 0x28) ++#define REG_SC_BK08_28_H _PK_H_(0x08, 0x28) ++#define REG_SC_BK08_29_L _PK_L_(0x08, 0x29) ++#define REG_SC_BK08_29_H _PK_H_(0x08, 0x29) ++#define REG_SC_BK08_2A_L _PK_L_(0x08, 0x2A) ++#define REG_SC_BK08_2A_H _PK_H_(0x08, 0x2A) ++#define REG_SC_BK08_2B_L _PK_L_(0x08, 0x2B) ++#define REG_SC_BK08_2B_H _PK_H_(0x08, 0x2B) ++#define REG_SC_BK08_2C_L _PK_L_(0x08, 0x2C) ++#define REG_SC_BK08_2C_H _PK_H_(0x08, 0x2C) ++#define REG_SC_BK08_2D_L _PK_L_(0x08, 0x2D) ++#define REG_SC_BK08_2D_H _PK_H_(0x08, 0x2D) ++#define REG_SC_BK08_2E_L _PK_L_(0x08, 0x2E) ++#define REG_SC_BK08_2E_H _PK_H_(0x08, 0x2E) ++#define REG_SC_BK08_2F_L _PK_L_(0x08, 0x2F) ++#define REG_SC_BK08_2F_H _PK_H_(0x08, 0x2F) ++#define REG_SC_BK08_30_L _PK_L_(0x08, 0x30) ++#define REG_SC_BK08_30_H _PK_H_(0x08, 0x30) ++#define REG_SC_BK08_31_L _PK_L_(0x08, 0x31) ++#define REG_SC_BK08_31_H _PK_H_(0x08, 0x31) ++#define REG_SC_BK08_32_L _PK_L_(0x08, 0x32) ++#define REG_SC_BK08_32_H _PK_H_(0x08, 0x32) ++#define REG_SC_BK08_33_L _PK_L_(0x08, 0x33) ++#define REG_SC_BK08_33_H _PK_H_(0x08, 0x33) ++#define REG_SC_BK08_34_L _PK_L_(0x08, 0x34) ++#define REG_SC_BK08_34_H _PK_H_(0x08, 0x34) ++#define REG_SC_BK08_35_L _PK_L_(0x08, 0x35) ++#define REG_SC_BK08_35_H _PK_H_(0x08, 0x35) ++#define REG_SC_BK08_36_L _PK_L_(0x08, 0x36) ++#define REG_SC_BK08_36_H _PK_H_(0x08, 0x36) ++#define REG_SC_BK08_37_L _PK_L_(0x08, 0x37) ++#define REG_SC_BK08_37_H _PK_H_(0x08, 0x37) ++#define REG_SC_BK08_38_L _PK_L_(0x08, 0x38) ++#define REG_SC_BK08_38_H _PK_H_(0x08, 0x38) ++#define REG_SC_BK08_39_L _PK_L_(0x08, 0x39) ++#define REG_SC_BK08_39_H _PK_H_(0x08, 0x39) ++#define REG_SC_BK08_3A_L _PK_L_(0x08, 0x3A) ++#define REG_SC_BK08_3A_H _PK_H_(0x08, 0x3A) ++#define REG_SC_BK08_3B_L _PK_L_(0x08, 0x3B) ++#define REG_SC_BK08_3B_H _PK_H_(0x08, 0x3B) ++#define REG_SC_BK08_3C_L _PK_L_(0x08, 0x3C) ++#define REG_SC_BK08_3C_H _PK_H_(0x08, 0x3C) ++#define REG_SC_BK08_3D_L _PK_L_(0x08, 0x3D) ++#define REG_SC_BK08_3D_H _PK_H_(0x08, 0x3D) ++#define REG_SC_BK08_3E_L _PK_L_(0x08, 0x3E) ++#define REG_SC_BK08_3E_H _PK_H_(0x08, 0x3E) ++#define REG_SC_BK08_3F_L _PK_L_(0x08, 0x3F) ++#define REG_SC_BK08_3F_H _PK_H_(0x08, 0x3F) ++#define REG_SC_BK08_40_L _PK_L_(0x08, 0x40) ++#define REG_SC_BK08_40_H _PK_H_(0x08, 0x40) ++#define REG_SC_BK08_41_L _PK_L_(0x08, 0x41) ++#define REG_SC_BK08_41_H _PK_H_(0x08, 0x41) ++#define REG_SC_BK08_42_L _PK_L_(0x08, 0x42) ++#define REG_SC_BK08_42_H _PK_H_(0x08, 0x42) ++#define REG_SC_BK08_43_L _PK_L_(0x08, 0x43) ++#define REG_SC_BK08_43_H _PK_H_(0x08, 0x43) ++#define REG_SC_BK08_44_L _PK_L_(0x08, 0x44) ++#define REG_SC_BK08_44_H _PK_H_(0x08, 0x44) ++#define REG_SC_BK08_45_L _PK_L_(0x08, 0x45) ++#define REG_SC_BK08_45_H _PK_H_(0x08, 0x45) ++#define REG_SC_BK08_46_L _PK_L_(0x08, 0x46) ++#define REG_SC_BK08_46_H _PK_H_(0x08, 0x46) ++#define REG_SC_BK08_47_L _PK_L_(0x08, 0x47) ++#define REG_SC_BK08_47_H _PK_H_(0x08, 0x47) ++#define REG_SC_BK08_48_L _PK_L_(0x08, 0x48) ++#define REG_SC_BK08_48_H _PK_H_(0x08, 0x48) ++#define REG_SC_BK08_49_L _PK_L_(0x08, 0x49) ++#define REG_SC_BK08_49_H _PK_H_(0x08, 0x49) ++#define REG_SC_BK08_4A_L _PK_L_(0x08, 0x4A) ++#define REG_SC_BK08_4A_H _PK_H_(0x08, 0x4A) ++#define REG_SC_BK08_4B_L _PK_L_(0x08, 0x4B) ++#define REG_SC_BK08_4B_H _PK_H_(0x08, 0x4B) ++#define REG_SC_BK08_4C_L _PK_L_(0x08, 0x4C) ++#define REG_SC_BK08_4C_H _PK_H_(0x08, 0x4C) ++#define REG_SC_BK08_4D_L _PK_L_(0x08, 0x4D) ++#define REG_SC_BK08_4D_H _PK_H_(0x08, 0x4D) ++#define REG_SC_BK08_4E_L _PK_L_(0x08, 0x4E) ++#define REG_SC_BK08_4E_H _PK_H_(0x08, 0x4E) ++#define REG_SC_BK08_4F_L _PK_L_(0x08, 0x4F) ++#define REG_SC_BK08_4F_H _PK_H_(0x08, 0x4F) ++#define REG_SC_BK08_50_L _PK_L_(0x08, 0x50) ++#define REG_SC_BK08_50_H _PK_H_(0x08, 0x50) ++#define REG_SC_BK08_51_L _PK_L_(0x08, 0x51) ++#define REG_SC_BK08_51_H _PK_H_(0x08, 0x51) ++#define REG_SC_BK08_52_L _PK_L_(0x08, 0x52) ++#define REG_SC_BK08_52_H _PK_H_(0x08, 0x52) ++#define REG_SC_BK08_53_L _PK_L_(0x08, 0x53) ++#define REG_SC_BK08_53_H _PK_H_(0x08, 0x53) ++#define REG_SC_BK08_54_L _PK_L_(0x08, 0x54) ++#define REG_SC_BK08_54_H _PK_H_(0x08, 0x54) ++#define REG_SC_BK08_55_L _PK_L_(0x08, 0x55) ++#define REG_SC_BK08_55_H _PK_H_(0x08, 0x55) ++#define REG_SC_BK08_56_L _PK_L_(0x08, 0x56) ++#define REG_SC_BK08_56_H _PK_H_(0x08, 0x56) ++#define REG_SC_BK08_57_L _PK_L_(0x08, 0x57) ++#define REG_SC_BK08_57_H _PK_H_(0x08, 0x57) ++#define REG_SC_BK08_58_L _PK_L_(0x08, 0x58) ++#define REG_SC_BK08_58_H _PK_H_(0x08, 0x58) ++#define REG_SC_BK08_59_L _PK_L_(0x08, 0x59) ++#define REG_SC_BK08_59_H _PK_H_(0x08, 0x59) ++#define REG_SC_BK08_5A_L _PK_L_(0x08, 0x5A) ++#define REG_SC_BK08_5A_H _PK_H_(0x08, 0x5A) ++#define REG_SC_BK08_5B_L _PK_L_(0x08, 0x5B) ++#define REG_SC_BK08_5B_H _PK_H_(0x08, 0x5B) ++#define REG_SC_BK08_5C_L _PK_L_(0x08, 0x5C) ++#define REG_SC_BK08_5C_H _PK_H_(0x08, 0x5C) ++#define REG_SC_BK08_5D_L _PK_L_(0x08, 0x5D) ++#define REG_SC_BK08_5D_H _PK_H_(0x08, 0x5D) ++#define REG_SC_BK08_5E_L _PK_L_(0x08, 0x5E) ++#define REG_SC_BK08_5E_H _PK_H_(0x08, 0x5E) ++#define REG_SC_BK08_5F_L _PK_L_(0x08, 0x5F) ++#define REG_SC_BK08_5F_H _PK_H_(0x08, 0x5F) ++#define REG_SC_BK08_60_L _PK_L_(0x08, 0x60) ++#define REG_SC_BK08_60_H _PK_H_(0x08, 0x60) ++#define REG_SC_BK08_61_L _PK_L_(0x08, 0x61) ++#define REG_SC_BK08_61_H _PK_H_(0x08, 0x61) ++#define REG_SC_BK08_62_L _PK_L_(0x08, 0x62) ++#define REG_SC_BK08_62_H _PK_H_(0x08, 0x62) ++#define REG_SC_BK08_63_L _PK_L_(0x08, 0x63) ++#define REG_SC_BK08_63_H _PK_H_(0x08, 0x63) ++#define REG_SC_BK08_64_L _PK_L_(0x08, 0x64) ++#define REG_SC_BK08_64_H _PK_H_(0x08, 0x64) ++#define REG_SC_BK08_65_L _PK_L_(0x08, 0x65) ++#define REG_SC_BK08_65_H _PK_H_(0x08, 0x65) ++#define REG_SC_BK08_66_L _PK_L_(0x08, 0x66) ++#define REG_SC_BK08_66_H _PK_H_(0x08, 0x66) ++#define REG_SC_BK08_67_L _PK_L_(0x08, 0x67) ++#define REG_SC_BK08_67_H _PK_H_(0x08, 0x67) ++#define REG_SC_BK08_68_L _PK_L_(0x08, 0x68) ++#define REG_SC_BK08_68_H _PK_H_(0x08, 0x68) ++#define REG_SC_BK08_69_L _PK_L_(0x08, 0x69) ++#define REG_SC_BK08_69_H _PK_H_(0x08, 0x69) ++#define REG_SC_BK08_6A_L _PK_L_(0x08, 0x6A) ++#define REG_SC_BK08_6A_H _PK_H_(0x08, 0x6A) ++#define REG_SC_BK08_6B_L _PK_L_(0x08, 0x6B) ++#define REG_SC_BK08_6B_H _PK_H_(0x08, 0x6B) ++#define REG_SC_BK08_6C_L _PK_L_(0x08, 0x6C) ++#define REG_SC_BK08_6C_H _PK_H_(0x08, 0x6C) ++#define REG_SC_BK08_6D_L _PK_L_(0x08, 0x6D) ++#define REG_SC_BK08_6D_H _PK_H_(0x08, 0x6D) ++#define REG_SC_BK08_6E_L _PK_L_(0x08, 0x6E) ++#define REG_SC_BK08_6E_H _PK_H_(0x08, 0x6E) ++#define REG_SC_BK08_6F_L _PK_L_(0x08, 0x6F) ++#define REG_SC_BK08_6F_H _PK_H_(0x08, 0x6F) ++#define REG_SC_BK08_70_L _PK_L_(0x08, 0x70) ++#define REG_SC_BK08_70_H _PK_H_(0x08, 0x70) ++#define REG_SC_BK08_71_L _PK_L_(0x08, 0x71) ++#define REG_SC_BK08_71_H _PK_H_(0x08, 0x71) ++#define REG_SC_BK08_72_L _PK_L_(0x08, 0x72) ++#define REG_SC_BK08_72_H _PK_H_(0x08, 0x72) ++#define REG_SC_BK08_73_L _PK_L_(0x08, 0x73) ++#define REG_SC_BK08_73_H _PK_H_(0x08, 0x73) ++#define REG_SC_BK08_74_L _PK_L_(0x08, 0x74) ++#define REG_SC_BK08_74_H _PK_H_(0x08, 0x74) ++#define REG_SC_BK08_75_L _PK_L_(0x08, 0x75) ++#define REG_SC_BK08_75_H _PK_H_(0x08, 0x75) ++#define REG_SC_BK08_76_L _PK_L_(0x08, 0x76) ++#define REG_SC_BK08_76_H _PK_H_(0x08, 0x76) ++#define REG_SC_BK08_77_L _PK_L_(0x08, 0x77) ++#define REG_SC_BK08_77_H _PK_H_(0x08, 0x77) ++#define REG_SC_BK08_78_L _PK_L_(0x08, 0x78) ++#define REG_SC_BK08_78_H _PK_H_(0x08, 0x78) ++#define REG_SC_BK08_79_L _PK_L_(0x08, 0x79) ++#define REG_SC_BK08_79_H _PK_H_(0x08, 0x79) ++#define REG_SC_BK08_7A_L _PK_L_(0x08, 0x7A) ++#define REG_SC_BK08_7A_H _PK_H_(0x08, 0x7A) ++#define REG_SC_BK08_7B_L _PK_L_(0x08, 0x7B) ++#define REG_SC_BK08_7B_H _PK_H_(0x08, 0x7B) ++#define REG_SC_BK08_7C_L _PK_L_(0x08, 0x7C) ++#define REG_SC_BK08_7C_H _PK_H_(0x08, 0x7C) ++#define REG_SC_BK08_7D_L _PK_L_(0x08, 0x7D) ++#define REG_SC_BK08_7D_H _PK_H_(0x08, 0x7D) ++#define REG_SC_BK08_7E_L _PK_L_(0x08, 0x7E) ++#define REG_SC_BK08_7E_H _PK_H_(0x08, 0x7E) ++#define REG_SC_BK08_7F_L _PK_L_(0x08, 0x7F) ++#define REG_SC_BK08_7F_H _PK_H_(0x08, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK09_00_L _PK_L_(0x09, 0x00) ++#define REG_SC_BK09_00_H _PK_H_(0x09, 0x00) ++#define REG_SC_BK09_01_L _PK_L_(0x09, 0x01) ++#define REG_SC_BK09_01_H _PK_H_(0x09, 0x01) ++#define REG_SC_BK09_02_L _PK_L_(0x09, 0x02) ++#define REG_SC_BK09_02_H _PK_H_(0x09, 0x02) ++#define REG_SC_BK09_03_L _PK_L_(0x09, 0x03) ++#define REG_SC_BK09_03_H _PK_H_(0x09, 0x03) ++#define REG_SC_BK09_04_L _PK_L_(0x09, 0x04) ++#define REG_SC_BK09_04_H _PK_H_(0x09, 0x04) ++#define REG_SC_BK09_05_L _PK_L_(0x09, 0x05) ++#define REG_SC_BK09_05_H _PK_H_(0x09, 0x05) ++#define REG_SC_BK09_06_L _PK_L_(0x09, 0x06) ++#define REG_SC_BK09_06_H _PK_H_(0x09, 0x06) ++#define REG_SC_BK09_07_L _PK_L_(0x09, 0x07) ++#define REG_SC_BK09_07_H _PK_H_(0x09, 0x07) ++#define REG_SC_BK09_08_L _PK_L_(0x09, 0x08) ++#define REG_SC_BK09_08_H _PK_H_(0x09, 0x08) ++#define REG_SC_BK09_09_L _PK_L_(0x09, 0x09) ++#define REG_SC_BK09_09_H _PK_H_(0x09, 0x09) ++#define REG_SC_BK09_0A_L _PK_L_(0x09, 0x0A) ++#define REG_SC_BK09_0A_H _PK_H_(0x09, 0x0A) ++#define REG_SC_BK09_0B_L _PK_L_(0x09, 0x0B) ++#define REG_SC_BK09_0B_H _PK_H_(0x09, 0x0B) ++#define REG_SC_BK09_0C_L _PK_L_(0x09, 0x0C) ++#define REG_SC_BK09_0C_H _PK_H_(0x09, 0x0C) ++#define REG_SC_BK09_0D_L _PK_L_(0x09, 0x0D) ++#define REG_SC_BK09_0D_H _PK_H_(0x09, 0x0D) ++#define REG_SC_BK09_0E_L _PK_L_(0x09, 0x0E) ++#define REG_SC_BK09_0E_H _PK_H_(0x09, 0x0E) ++#define REG_SC_BK09_0F_L _PK_L_(0x09, 0x0F) ++#define REG_SC_BK09_0F_H _PK_H_(0x09, 0x0F) ++#define REG_SC_BK09_10_L _PK_L_(0x09, 0x10) ++#define REG_SC_BK09_10_H _PK_H_(0x09, 0x10) ++#define REG_SC_BK09_11_L _PK_L_(0x09, 0x11) ++#define REG_SC_BK09_11_H _PK_H_(0x09, 0x11) ++#define REG_SC_BK09_12_L _PK_L_(0x09, 0x12) ++#define REG_SC_BK09_12_H _PK_H_(0x09, 0x12) ++#define REG_SC_BK09_13_L _PK_L_(0x09, 0x13) ++#define REG_SC_BK09_13_H _PK_H_(0x09, 0x13) ++#define REG_SC_BK09_14_L _PK_L_(0x09, 0x14) ++#define REG_SC_BK09_14_H _PK_H_(0x09, 0x14) ++#define REG_SC_BK09_15_L _PK_L_(0x09, 0x15) ++#define REG_SC_BK09_15_H _PK_H_(0x09, 0x15) ++#define REG_SC_BK09_16_L _PK_L_(0x09, 0x16) ++#define REG_SC_BK09_16_H _PK_H_(0x09, 0x16) ++#define REG_SC_BK09_17_L _PK_L_(0x09, 0x17) ++#define REG_SC_BK09_17_H _PK_H_(0x09, 0x17) ++#define REG_SC_BK09_18_L _PK_L_(0x09, 0x18) ++#define REG_SC_BK09_18_H _PK_H_(0x09, 0x18) ++#define REG_SC_BK09_19_L _PK_L_(0x09, 0x19) ++#define REG_SC_BK09_19_H _PK_H_(0x09, 0x19) ++#define REG_SC_BK09_1A_L _PK_L_(0x09, 0x1A) ++#define REG_SC_BK09_1A_H _PK_H_(0x09, 0x1A) ++#define REG_SC_BK09_1B_L _PK_L_(0x09, 0x1B) ++#define REG_SC_BK09_1B_H _PK_H_(0x09, 0x1B) ++#define REG_SC_BK09_1C_L _PK_L_(0x09, 0x1C) ++#define REG_SC_BK09_1C_H _PK_H_(0x09, 0x1C) ++#define REG_SC_BK09_1D_L _PK_L_(0x09, 0x1D) ++#define REG_SC_BK09_1D_H _PK_H_(0x09, 0x1D) ++#define REG_SC_BK09_1E_L _PK_L_(0x09, 0x1E) ++#define REG_SC_BK09_1E_H _PK_H_(0x09, 0x1E) ++#define REG_SC_BK09_1F_L _PK_L_(0x09, 0x1F) ++#define REG_SC_BK09_1F_H _PK_H_(0x09, 0x1F) ++#define REG_SC_BK09_20_L _PK_L_(0x09, 0x20) ++#define REG_SC_BK09_20_H _PK_H_(0x09, 0x20) ++#define REG_SC_BK09_21_L _PK_L_(0x09, 0x21) ++#define REG_SC_BK09_21_H _PK_H_(0x09, 0x21) ++#define REG_SC_BK09_22_L _PK_L_(0x09, 0x22) ++#define REG_SC_BK09_22_H _PK_H_(0x09, 0x22) ++#define REG_SC_BK09_23_L _PK_L_(0x09, 0x23) ++#define REG_SC_BK09_23_H _PK_H_(0x09, 0x23) ++#define REG_SC_BK09_24_L _PK_L_(0x09, 0x24) ++#define REG_SC_BK09_24_H _PK_H_(0x09, 0x24) ++#define REG_SC_BK09_25_L _PK_L_(0x09, 0x25) ++#define REG_SC_BK09_25_H _PK_H_(0x09, 0x25) ++#define REG_SC_BK09_26_L _PK_L_(0x09, 0x26) ++#define REG_SC_BK09_26_H _PK_H_(0x09, 0x26) ++#define REG_SC_BK09_27_L _PK_L_(0x09, 0x27) ++#define REG_SC_BK09_27_H _PK_H_(0x09, 0x27) ++#define REG_SC_BK09_28_L _PK_L_(0x09, 0x28) ++#define REG_SC_BK09_28_H _PK_H_(0x09, 0x28) ++#define REG_SC_BK09_29_L _PK_L_(0x09, 0x29) ++#define REG_SC_BK09_29_H _PK_H_(0x09, 0x29) ++#define REG_SC_BK09_2A_L _PK_L_(0x09, 0x2A) ++#define REG_SC_BK09_2A_H _PK_H_(0x09, 0x2A) ++#define REG_SC_BK09_2B_L _PK_L_(0x09, 0x2B) ++#define REG_SC_BK09_2B_H _PK_H_(0x09, 0x2B) ++#define REG_SC_BK09_2C_L _PK_L_(0x09, 0x2C) ++#define REG_SC_BK09_2C_H _PK_H_(0x09, 0x2C) ++#define REG_SC_BK09_2D_L _PK_L_(0x09, 0x2D) ++#define REG_SC_BK09_2D_H _PK_H_(0x09, 0x2D) ++#define REG_SC_BK09_2E_L _PK_L_(0x09, 0x2E) ++#define REG_SC_BK09_2E_H _PK_H_(0x09, 0x2E) ++#define REG_SC_BK09_2F_L _PK_L_(0x09, 0x2F) ++#define REG_SC_BK09_2F_H _PK_H_(0x09, 0x2F) ++#define REG_SC_BK09_30_L _PK_L_(0x09, 0x30) ++#define REG_SC_BK09_30_H _PK_H_(0x09, 0x30) ++#define REG_SC_BK09_31_L _PK_L_(0x09, 0x31) ++#define REG_SC_BK09_31_H _PK_H_(0x09, 0x31) ++#define REG_SC_BK09_32_L _PK_L_(0x09, 0x32) ++#define REG_SC_BK09_32_H _PK_H_(0x09, 0x32) ++#define REG_SC_BK09_33_L _PK_L_(0x09, 0x33) ++#define REG_SC_BK09_33_H _PK_H_(0x09, 0x33) ++#define REG_SC_BK09_34_L _PK_L_(0x09, 0x34) ++#define REG_SC_BK09_34_H _PK_H_(0x09, 0x34) ++#define REG_SC_BK09_35_L _PK_L_(0x09, 0x35) ++#define REG_SC_BK09_35_H _PK_H_(0x09, 0x35) ++#define REG_SC_BK09_36_L _PK_L_(0x09, 0x36) ++#define REG_SC_BK09_36_H _PK_H_(0x09, 0x36) ++#define REG_SC_BK09_37_L _PK_L_(0x09, 0x37) ++#define REG_SC_BK09_37_H _PK_H_(0x09, 0x37) ++#define REG_SC_BK09_38_L _PK_L_(0x09, 0x38) ++#define REG_SC_BK09_38_H _PK_H_(0x09, 0x38) ++#define REG_SC_BK09_39_L _PK_L_(0x09, 0x39) ++#define REG_SC_BK09_39_H _PK_H_(0x09, 0x39) ++#define REG_SC_BK09_3A_L _PK_L_(0x09, 0x3A) ++#define REG_SC_BK09_3A_H _PK_H_(0x09, 0x3A) ++#define REG_SC_BK09_3B_L _PK_L_(0x09, 0x3B) ++#define REG_SC_BK09_3B_H _PK_H_(0x09, 0x3B) ++#define REG_SC_BK09_3C_L _PK_L_(0x09, 0x3C) ++#define REG_SC_BK09_3C_H _PK_H_(0x09, 0x3C) ++#define REG_SC_BK09_3D_L _PK_L_(0x09, 0x3D) ++#define REG_SC_BK09_3D_H _PK_H_(0x09, 0x3D) ++#define REG_SC_BK09_3E_L _PK_L_(0x09, 0x3E) ++#define REG_SC_BK09_3E_H _PK_H_(0x09, 0x3E) ++#define REG_SC_BK09_3F_L _PK_L_(0x09, 0x3F) ++#define REG_SC_BK09_3F_H _PK_H_(0x09, 0x3F) ++#define REG_SC_BK09_40_L _PK_L_(0x09, 0x40) ++#define REG_SC_BK09_40_H _PK_H_(0x09, 0x40) ++#define REG_SC_BK09_41_L _PK_L_(0x09, 0x41) ++#define REG_SC_BK09_41_H _PK_H_(0x09, 0x41) ++#define REG_SC_BK09_42_L _PK_L_(0x09, 0x42) ++#define REG_SC_BK09_42_H _PK_H_(0x09, 0x42) ++#define REG_SC_BK09_43_L _PK_L_(0x09, 0x43) ++#define REG_SC_BK09_43_H _PK_H_(0x09, 0x43) ++#define REG_SC_BK09_44_L _PK_L_(0x09, 0x44) ++#define REG_SC_BK09_44_H _PK_H_(0x09, 0x44) ++#define REG_SC_BK09_45_L _PK_L_(0x09, 0x45) ++#define REG_SC_BK09_45_H _PK_H_(0x09, 0x45) ++#define REG_SC_BK09_46_L _PK_L_(0x09, 0x46) ++#define REG_SC_BK09_46_H _PK_H_(0x09, 0x46) ++#define REG_SC_BK09_47_L _PK_L_(0x09, 0x47) ++#define REG_SC_BK09_47_H _PK_H_(0x09, 0x47) ++#define REG_SC_BK09_48_L _PK_L_(0x09, 0x48) ++#define REG_SC_BK09_48_H _PK_H_(0x09, 0x48) ++#define REG_SC_BK09_49_L _PK_L_(0x09, 0x49) ++#define REG_SC_BK09_49_H _PK_H_(0x09, 0x49) ++#define REG_SC_BK09_4A_L _PK_L_(0x09, 0x4A) ++#define REG_SC_BK09_4A_H _PK_H_(0x09, 0x4A) ++#define REG_SC_BK09_4B_L _PK_L_(0x09, 0x4B) ++#define REG_SC_BK09_4B_H _PK_H_(0x09, 0x4B) ++#define REG_SC_BK09_4C_L _PK_L_(0x09, 0x4C) ++#define REG_SC_BK09_4C_H _PK_H_(0x09, 0x4C) ++#define REG_SC_BK09_4D_L _PK_L_(0x09, 0x4D) ++#define REG_SC_BK09_4D_H _PK_H_(0x09, 0x4D) ++#define REG_SC_BK09_4E_L _PK_L_(0x09, 0x4E) ++#define REG_SC_BK09_4E_H _PK_H_(0x09, 0x4E) ++#define REG_SC_BK09_4F_L _PK_L_(0x09, 0x4F) ++#define REG_SC_BK09_4F_H _PK_H_(0x09, 0x4F) ++#define REG_SC_BK09_50_L _PK_L_(0x09, 0x50) ++#define REG_SC_BK09_50_H _PK_H_(0x09, 0x50) ++#define REG_SC_BK09_51_L _PK_L_(0x09, 0x51) ++#define REG_SC_BK09_51_H _PK_H_(0x09, 0x51) ++#define REG_SC_BK09_52_L _PK_L_(0x09, 0x52) ++#define REG_SC_BK09_52_H _PK_H_(0x09, 0x52) ++#define REG_SC_BK09_53_L _PK_L_(0x09, 0x53) ++#define REG_SC_BK09_53_H _PK_H_(0x09, 0x53) ++#define REG_SC_BK09_54_L _PK_L_(0x09, 0x54) ++#define REG_SC_BK09_54_H _PK_H_(0x09, 0x54) ++#define REG_SC_BK09_55_L _PK_L_(0x09, 0x55) ++#define REG_SC_BK09_55_H _PK_H_(0x09, 0x55) ++#define REG_SC_BK09_56_L _PK_L_(0x09, 0x56) ++#define REG_SC_BK09_56_H _PK_H_(0x09, 0x56) ++#define REG_SC_BK09_57_L _PK_L_(0x09, 0x57) ++#define REG_SC_BK09_57_H _PK_H_(0x09, 0x57) ++#define REG_SC_BK09_58_L _PK_L_(0x09, 0x58) ++#define REG_SC_BK09_58_H _PK_H_(0x09, 0x58) ++#define REG_SC_BK09_59_L _PK_L_(0x09, 0x59) ++#define REG_SC_BK09_59_H _PK_H_(0x09, 0x59) ++#define REG_SC_BK09_5A_L _PK_L_(0x09, 0x5A) ++#define REG_SC_BK09_5A_H _PK_H_(0x09, 0x5A) ++#define REG_SC_BK09_5B_L _PK_L_(0x09, 0x5B) ++#define REG_SC_BK09_5B_H _PK_H_(0x09, 0x5B) ++#define REG_SC_BK09_5C_L _PK_L_(0x09, 0x5C) ++#define REG_SC_BK09_5C_H _PK_H_(0x09, 0x5C) ++#define REG_SC_BK09_5D_L _PK_L_(0x09, 0x5D) ++#define REG_SC_BK09_5D_H _PK_H_(0x09, 0x5D) ++#define REG_SC_BK09_5E_L _PK_L_(0x09, 0x5E) ++#define REG_SC_BK09_5E_H _PK_H_(0x09, 0x5E) ++#define REG_SC_BK09_5F_L _PK_L_(0x09, 0x5F) ++#define REG_SC_BK09_5F_H _PK_H_(0x09, 0x5F) ++#define REG_SC_BK09_60_L _PK_L_(0x09, 0x60) ++#define REG_SC_BK09_60_H _PK_H_(0x09, 0x60) ++#define REG_SC_BK09_61_L _PK_L_(0x09, 0x61) ++#define REG_SC_BK09_61_H _PK_H_(0x09, 0x61) ++#define REG_SC_BK09_62_L _PK_L_(0x09, 0x62) ++#define REG_SC_BK09_62_H _PK_H_(0x09, 0x62) ++#define REG_SC_BK09_63_L _PK_L_(0x09, 0x63) ++#define REG_SC_BK09_63_H _PK_H_(0x09, 0x63) ++#define REG_SC_BK09_64_L _PK_L_(0x09, 0x64) ++#define REG_SC_BK09_64_H _PK_H_(0x09, 0x64) ++#define REG_SC_BK09_65_L _PK_L_(0x09, 0x65) ++#define REG_SC_BK09_65_H _PK_H_(0x09, 0x65) ++#define REG_SC_BK09_66_L _PK_L_(0x09, 0x66) ++#define REG_SC_BK09_66_H _PK_H_(0x09, 0x66) ++#define REG_SC_BK09_67_L _PK_L_(0x09, 0x67) ++#define REG_SC_BK09_67_H _PK_H_(0x09, 0x67) ++#define REG_SC_BK09_68_L _PK_L_(0x09, 0x68) ++#define REG_SC_BK09_68_H _PK_H_(0x09, 0x68) ++#define REG_SC_BK09_69_L _PK_L_(0x09, 0x69) ++#define REG_SC_BK09_69_H _PK_H_(0x09, 0x69) ++#define REG_SC_BK09_6A_L _PK_L_(0x09, 0x6A) ++#define REG_SC_BK09_6A_H _PK_H_(0x09, 0x6A) ++#define REG_SC_BK09_6B_L _PK_L_(0x09, 0x6B) ++#define REG_SC_BK09_6B_H _PK_H_(0x09, 0x6B) ++#define REG_SC_BK09_6C_L _PK_L_(0x09, 0x6C) ++#define REG_SC_BK09_6C_H _PK_H_(0x09, 0x6C) ++#define REG_SC_BK09_6D_L _PK_L_(0x09, 0x6D) ++#define REG_SC_BK09_6D_H _PK_H_(0x09, 0x6D) ++#define REG_SC_BK09_6E_L _PK_L_(0x09, 0x6E) ++#define REG_SC_BK09_6E_H _PK_H_(0x09, 0x6E) ++#define REG_SC_BK09_6F_L _PK_L_(0x09, 0x6F) ++#define REG_SC_BK09_6F_H _PK_H_(0x09, 0x6F) ++#define REG_SC_BK09_70_L _PK_L_(0x09, 0x70) ++#define REG_SC_BK09_70_H _PK_H_(0x09, 0x70) ++#define REG_SC_BK09_71_L _PK_L_(0x09, 0x71) ++#define REG_SC_BK09_71_H _PK_H_(0x09, 0x71) ++#define REG_SC_BK09_72_L _PK_L_(0x09, 0x72) ++#define REG_SC_BK09_72_H _PK_H_(0x09, 0x72) ++#define REG_SC_BK09_73_L _PK_L_(0x09, 0x73) ++#define REG_SC_BK09_73_H _PK_H_(0x09, 0x73) ++#define REG_SC_BK09_74_L _PK_L_(0x09, 0x74) ++#define REG_SC_BK09_74_H _PK_H_(0x09, 0x74) ++#define REG_SC_BK09_75_L _PK_L_(0x09, 0x75) ++#define REG_SC_BK09_75_H _PK_H_(0x09, 0x75) ++#define REG_SC_BK09_76_L _PK_L_(0x09, 0x76) ++#define REG_SC_BK09_76_H _PK_H_(0x09, 0x76) ++#define REG_SC_BK09_77_L _PK_L_(0x09, 0x77) ++#define REG_SC_BK09_77_H _PK_H_(0x09, 0x77) ++#define REG_SC_BK09_78_L _PK_L_(0x09, 0x78) ++#define REG_SC_BK09_78_H _PK_H_(0x09, 0x78) ++#define REG_SC_BK09_79_L _PK_L_(0x09, 0x79) ++#define REG_SC_BK09_79_H _PK_H_(0x09, 0x79) ++#define REG_SC_BK09_7A_L _PK_L_(0x09, 0x7A) ++#define REG_SC_BK09_7A_H _PK_H_(0x09, 0x7A) ++#define REG_SC_BK09_7B_L _PK_L_(0x09, 0x7B) ++#define REG_SC_BK09_7B_H _PK_H_(0x09, 0x7B) ++#define REG_SC_BK09_7C_L _PK_L_(0x09, 0x7C) ++#define REG_SC_BK09_7C_H _PK_H_(0x09, 0x7C) ++#define REG_SC_BK09_7D_L _PK_L_(0x09, 0x7D) ++#define REG_SC_BK09_7D_H _PK_H_(0x09, 0x7D) ++#define REG_SC_BK09_7E_L _PK_L_(0x09, 0x7E) ++#define REG_SC_BK09_7E_H _PK_H_(0x09, 0x7E) ++#define REG_SC_BK09_7F_L _PK_L_(0x09, 0x7F) ++#define REG_SC_BK09_7F_H _PK_H_(0x09, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0A_00_L _PK_L_(0x0A, 0x00) ++#define REG_SC_BK0A_00_H _PK_H_(0x0A, 0x00) ++#define REG_SC_BK0A_01_L _PK_L_(0x0A, 0x01) ++#define REG_SC_BK0A_01_H _PK_H_(0x0A, 0x01) ++#define REG_SC_BK0A_02_L _PK_L_(0x0A, 0x02) ++#define REG_SC_BK0A_02_H _PK_H_(0x0A, 0x02) ++#define REG_SC_BK0A_03_L _PK_L_(0x0A, 0x03) ++#define REG_SC_BK0A_03_H _PK_H_(0x0A, 0x03) ++#define REG_SC_BK0A_04_L _PK_L_(0x0A, 0x04) ++#define REG_SC_BK0A_04_H _PK_H_(0x0A, 0x04) ++#define REG_SC_BK0A_05_L _PK_L_(0x0A, 0x05) ++#define REG_SC_BK0A_05_H _PK_H_(0x0A, 0x05) ++#define REG_SC_BK0A_06_L _PK_L_(0x0A, 0x06) ++#define REG_SC_BK0A_06_H _PK_H_(0x0A, 0x06) ++#define REG_SC_BK0A_07_L _PK_L_(0x0A, 0x07) ++#define REG_SC_BK0A_07_H _PK_H_(0x0A, 0x07) ++#define REG_SC_BK0A_08_L _PK_L_(0x0A, 0x08) ++#define REG_SC_BK0A_08_H _PK_H_(0x0A, 0x08) ++#define REG_SC_BK0A_09_L _PK_L_(0x0A, 0x09) ++#define REG_SC_BK0A_09_H _PK_H_(0x0A, 0x09) ++#define REG_SC_BK0A_0A_L _PK_L_(0x0A, 0x0A) ++#define REG_SC_BK0A_0A_H _PK_H_(0x0A, 0x0A) ++#define REG_SC_BK0A_0B_L _PK_L_(0x0A, 0x0B) ++#define REG_SC_BK0A_0B_H _PK_H_(0x0A, 0x0B) ++#define REG_SC_BK0A_0C_L _PK_L_(0x0A, 0x0C) ++#define REG_SC_BK0A_0C_H _PK_H_(0x0A, 0x0C) ++#define REG_SC_BK0A_0D_L _PK_L_(0x0A, 0x0D) ++#define REG_SC_BK0A_0D_H _PK_H_(0x0A, 0x0D) ++#define REG_SC_BK0A_0E_L _PK_L_(0x0A, 0x0E) ++#define REG_SC_BK0A_0E_H _PK_H_(0x0A, 0x0E) ++#define REG_SC_BK0A_0F_L _PK_L_(0x0A, 0x0F) ++#define REG_SC_BK0A_0F_H _PK_H_(0x0A, 0x0F) ++#define REG_SC_BK0A_10_L _PK_L_(0x0A, 0x10) ++#define REG_SC_BK0A_10_H _PK_H_(0x0A, 0x10) ++#define REG_SC_BK0A_11_L _PK_L_(0x0A, 0x11) ++#define REG_SC_BK0A_11_H _PK_H_(0x0A, 0x11) ++#define REG_SC_BK0A_12_L _PK_L_(0x0A, 0x12) ++#define REG_SC_BK0A_12_H _PK_H_(0x0A, 0x12) ++#define REG_SC_BK0A_13_L _PK_L_(0x0A, 0x13) ++#define REG_SC_BK0A_13_H _PK_H_(0x0A, 0x13) ++#define REG_SC_BK0A_14_L _PK_L_(0x0A, 0x14) ++#define REG_SC_BK0A_14_H _PK_H_(0x0A, 0x14) ++#define REG_SC_BK0A_15_L _PK_L_(0x0A, 0x15) ++#define REG_SC_BK0A_15_H _PK_H_(0x0A, 0x15) ++#define REG_SC_BK0A_16_L _PK_L_(0x0A, 0x16) ++#define REG_SC_BK0A_16_H _PK_H_(0x0A, 0x16) ++#define REG_SC_BK0A_17_L _PK_L_(0x0A, 0x17) ++#define REG_SC_BK0A_17_H _PK_H_(0x0A, 0x17) ++#define REG_SC_BK0A_18_L _PK_L_(0x0A, 0x18) ++#define REG_SC_BK0A_18_H _PK_H_(0x0A, 0x18) ++#define REG_SC_BK0A_19_L _PK_L_(0x0A, 0x19) ++#define REG_SC_BK0A_19_H _PK_H_(0x0A, 0x19) ++#define REG_SC_BK0A_1A_L _PK_L_(0x0A, 0x1A) ++#define REG_SC_BK0A_1A_H _PK_H_(0x0A, 0x1A) ++#define REG_SC_BK0A_1B_L _PK_L_(0x0A, 0x1B) ++#define REG_SC_BK0A_1B_H _PK_H_(0x0A, 0x1B) ++#define REG_SC_BK0A_1C_L _PK_L_(0x0A, 0x1C) ++#define REG_SC_BK0A_1C_H _PK_H_(0x0A, 0x1C) ++#define REG_SC_BK0A_1D_L _PK_L_(0x0A, 0x1D) ++#define REG_SC_BK0A_1D_H _PK_H_(0x0A, 0x1D) ++#define REG_SC_BK0A_1E_L _PK_L_(0x0A, 0x1E) ++#define REG_SC_BK0A_1E_H _PK_H_(0x0A, 0x1E) ++#define REG_SC_BK0A_1F_L _PK_L_(0x0A, 0x1F) ++#define REG_SC_BK0A_1F_H _PK_H_(0x0A, 0x1F) ++#define REG_SC_BK0A_20_L _PK_L_(0x0A, 0x20) ++#define REG_SC_BK0A_20_H _PK_H_(0x0A, 0x20) ++#define REG_SC_BK0A_21_L _PK_L_(0x0A, 0x21) ++#define REG_SC_BK0A_21_H _PK_H_(0x0A, 0x21) ++#define REG_SC_BK0A_22_L _PK_L_(0x0A, 0x22) ++#define REG_SC_BK0A_22_H _PK_H_(0x0A, 0x22) ++#define REG_SC_BK0A_23_L _PK_L_(0x0A, 0x23) ++#define REG_SC_BK0A_23_H _PK_H_(0x0A, 0x23) ++#define REG_SC_BK0A_24_L _PK_L_(0x0A, 0x24) ++#define REG_SC_BK0A_24_H _PK_H_(0x0A, 0x24) ++#define REG_SC_BK0A_25_L _PK_L_(0x0A, 0x25) ++#define REG_SC_BK0A_25_H _PK_H_(0x0A, 0x25) ++#define REG_SC_BK0A_26_L _PK_L_(0x0A, 0x26) ++#define REG_SC_BK0A_26_H _PK_H_(0x0A, 0x26) ++#define REG_SC_BK0A_27_L _PK_L_(0x0A, 0x27) ++#define REG_SC_BK0A_27_H _PK_H_(0x0A, 0x27) ++#define REG_SC_BK0A_28_L _PK_L_(0x0A, 0x28) ++#define REG_SC_BK0A_28_H _PK_H_(0x0A, 0x28) ++#define REG_SC_BK0A_29_L _PK_L_(0x0A, 0x29) ++#define REG_SC_BK0A_29_H _PK_H_(0x0A, 0x29) ++#define REG_SC_BK0A_2A_L _PK_L_(0x0A, 0x2A) ++#define REG_SC_BK0A_2A_H _PK_H_(0x0A, 0x2A) ++#define REG_SC_BK0A_2B_L _PK_L_(0x0A, 0x2B) ++#define REG_SC_BK0A_2B_H _PK_H_(0x0A, 0x2B) ++#define REG_SC_BK0A_2C_L _PK_L_(0x0A, 0x2C) ++#define REG_SC_BK0A_2C_H _PK_H_(0x0A, 0x2C) ++#define REG_SC_BK0A_2D_L _PK_L_(0x0A, 0x2D) ++#define REG_SC_BK0A_2D_H _PK_H_(0x0A, 0x2D) ++#define REG_SC_BK0A_2E_L _PK_L_(0x0A, 0x2E) ++#define REG_SC_BK0A_2E_H _PK_H_(0x0A, 0x2E) ++#define REG_SC_BK0A_2F_L _PK_L_(0x0A, 0x2F) ++#define REG_SC_BK0A_2F_H _PK_H_(0x0A, 0x2F) ++#define REG_SC_BK0A_30_L _PK_L_(0x0A, 0x30) ++#define REG_SC_BK0A_30_H _PK_H_(0x0A, 0x30) ++#define REG_SC_BK0A_31_L _PK_L_(0x0A, 0x31) ++#define REG_SC_BK0A_31_H _PK_H_(0x0A, 0x31) ++#define REG_SC_BK0A_32_L _PK_L_(0x0A, 0x32) ++#define REG_SC_BK0A_32_H _PK_H_(0x0A, 0x32) ++#define REG_SC_BK0A_33_L _PK_L_(0x0A, 0x33) ++#define REG_SC_BK0A_33_H _PK_H_(0x0A, 0x33) ++#define REG_SC_BK0A_34_L _PK_L_(0x0A, 0x34) ++#define REG_SC_BK0A_34_H _PK_H_(0x0A, 0x34) ++#define REG_SC_BK0A_35_L _PK_L_(0x0A, 0x35) ++#define REG_SC_BK0A_35_H _PK_H_(0x0A, 0x35) ++#define REG_SC_BK0A_36_L _PK_L_(0x0A, 0x36) ++#define REG_SC_BK0A_36_H _PK_H_(0x0A, 0x36) ++#define REG_SC_BK0A_37_L _PK_L_(0x0A, 0x37) ++#define REG_SC_BK0A_37_H _PK_H_(0x0A, 0x37) ++#define REG_SC_BK0A_38_L _PK_L_(0x0A, 0x38) ++#define REG_SC_BK0A_38_H _PK_H_(0x0A, 0x38) ++#define REG_SC_BK0A_39_L _PK_L_(0x0A, 0x39) ++#define REG_SC_BK0A_39_H _PK_H_(0x0A, 0x39) ++#define REG_SC_BK0A_3A_L _PK_L_(0x0A, 0x3A) ++#define REG_SC_BK0A_3A_H _PK_H_(0x0A, 0x3A) ++#define REG_SC_BK0A_3B_L _PK_L_(0x0A, 0x3B) ++#define REG_SC_BK0A_3B_H _PK_H_(0x0A, 0x3B) ++#define REG_SC_BK0A_3C_L _PK_L_(0x0A, 0x3C) ++#define REG_SC_BK0A_3C_H _PK_H_(0x0A, 0x3C) ++#define REG_SC_BK0A_3D_L _PK_L_(0x0A, 0x3D) ++#define REG_SC_BK0A_3D_H _PK_H_(0x0A, 0x3D) ++#define REG_SC_BK0A_3E_L _PK_L_(0x0A, 0x3E) ++#define REG_SC_BK0A_3E_H _PK_H_(0x0A, 0x3E) ++#define REG_SC_BK0A_3F_L _PK_L_(0x0A, 0x3F) ++#define REG_SC_BK0A_3F_H _PK_H_(0x0A, 0x3F) ++#define REG_SC_BK0A_40_L _PK_L_(0x0A, 0x40) ++#define REG_SC_BK0A_40_H _PK_H_(0x0A, 0x40) ++#define REG_SC_BK0A_41_L _PK_L_(0x0A, 0x41) ++#define REG_SC_BK0A_41_H _PK_H_(0x0A, 0x41) ++#define REG_SC_BK0A_42_L _PK_L_(0x0A, 0x42) ++#define REG_SC_BK0A_42_H _PK_H_(0x0A, 0x42) ++#define REG_SC_BK0A_43_L _PK_L_(0x0A, 0x43) ++#define REG_SC_BK0A_43_H _PK_H_(0x0A, 0x43) ++#define REG_SC_BK0A_44_L _PK_L_(0x0A, 0x44) ++#define REG_SC_BK0A_44_H _PK_H_(0x0A, 0x44) ++#define REG_SC_BK0A_45_L _PK_L_(0x0A, 0x45) ++#define REG_SC_BK0A_45_H _PK_H_(0x0A, 0x45) ++#define REG_SC_BK0A_46_L _PK_L_(0x0A, 0x46) ++#define REG_SC_BK0A_46_H _PK_H_(0x0A, 0x46) ++#define REG_SC_BK0A_47_L _PK_L_(0x0A, 0x47) ++#define REG_SC_BK0A_47_H _PK_H_(0x0A, 0x47) ++#define REG_SC_BK0A_48_L _PK_L_(0x0A, 0x48) ++#define REG_SC_BK0A_48_H _PK_H_(0x0A, 0x48) ++#define REG_SC_BK0A_49_L _PK_L_(0x0A, 0x49) ++#define REG_SC_BK0A_49_H _PK_H_(0x0A, 0x49) ++#define REG_SC_BK0A_4A_L _PK_L_(0x0A, 0x4A) ++#define REG_SC_BK0A_4A_H _PK_H_(0x0A, 0x4A) ++#define REG_SC_BK0A_4B_L _PK_L_(0x0A, 0x4B) ++#define REG_SC_BK0A_4B_H _PK_H_(0x0A, 0x4B) ++#define REG_SC_BK0A_4C_L _PK_L_(0x0A, 0x4C) ++#define REG_SC_BK0A_4C_H _PK_H_(0x0A, 0x4C) ++#define REG_SC_BK0A_4D_L _PK_L_(0x0A, 0x4D) ++#define REG_SC_BK0A_4D_H _PK_H_(0x0A, 0x4D) ++#define REG_SC_BK0A_4E_L _PK_L_(0x0A, 0x4E) ++#define REG_SC_BK0A_4E_H _PK_H_(0x0A, 0x4E) ++#define REG_SC_BK0A_4F_L _PK_L_(0x0A, 0x4F) ++#define REG_SC_BK0A_4F_H _PK_H_(0x0A, 0x4F) ++#define REG_SC_BK0A_50_L _PK_L_(0x0A, 0x50) ++#define REG_SC_BK0A_50_H _PK_H_(0x0A, 0x50) ++#define REG_SC_BK0A_51_L _PK_L_(0x0A, 0x51) ++#define REG_SC_BK0A_51_H _PK_H_(0x0A, 0x51) ++#define REG_SC_BK0A_52_L _PK_L_(0x0A, 0x52) ++#define REG_SC_BK0A_52_H _PK_H_(0x0A, 0x52) ++#define REG_SC_BK0A_53_L _PK_L_(0x0A, 0x53) ++#define REG_SC_BK0A_53_H _PK_H_(0x0A, 0x53) ++#define REG_SC_BK0A_54_L _PK_L_(0x0A, 0x54) ++#define REG_SC_BK0A_54_H _PK_H_(0x0A, 0x54) ++#define REG_SC_BK0A_55_L _PK_L_(0x0A, 0x55) ++#define REG_SC_BK0A_55_H _PK_H_(0x0A, 0x55) ++#define REG_SC_BK0A_56_L _PK_L_(0x0A, 0x56) ++#define REG_SC_BK0A_56_H _PK_H_(0x0A, 0x56) ++#define REG_SC_BK0A_57_L _PK_L_(0x0A, 0x57) ++#define REG_SC_BK0A_57_H _PK_H_(0x0A, 0x57) ++#define REG_SC_BK0A_58_L _PK_L_(0x0A, 0x58) ++#define REG_SC_BK0A_58_H _PK_H_(0x0A, 0x58) ++#define REG_SC_BK0A_59_L _PK_L_(0x0A, 0x59) ++#define REG_SC_BK0A_59_H _PK_H_(0x0A, 0x59) ++#define REG_SC_BK0A_5A_L _PK_L_(0x0A, 0x5A) ++#define REG_SC_BK0A_5A_H _PK_H_(0x0A, 0x5A) ++#define REG_SC_BK0A_5B_L _PK_L_(0x0A, 0x5B) ++#define REG_SC_BK0A_5B_H _PK_H_(0x0A, 0x5B) ++#define REG_SC_BK0A_5C_L _PK_L_(0x0A, 0x5C) ++#define REG_SC_BK0A_5C_H _PK_H_(0x0A, 0x5C) ++#define REG_SC_BK0A_5D_L _PK_L_(0x0A, 0x5D) ++#define REG_SC_BK0A_5D_H _PK_H_(0x0A, 0x5D) ++#define REG_SC_BK0A_5E_L _PK_L_(0x0A, 0x5E) ++#define REG_SC_BK0A_5E_H _PK_H_(0x0A, 0x5E) ++#define REG_SC_BK0A_5F_L _PK_L_(0x0A, 0x5F) ++#define REG_SC_BK0A_5F_H _PK_H_(0x0A, 0x5F) ++#define REG_SC_BK0A_60_L _PK_L_(0x0A, 0x60) ++#define REG_SC_BK0A_60_H _PK_H_(0x0A, 0x60) ++#define REG_SC_BK0A_61_L _PK_L_(0x0A, 0x61) ++#define REG_SC_BK0A_61_H _PK_H_(0x0A, 0x61) ++#define REG_SC_BK0A_62_L _PK_L_(0x0A, 0x62) ++#define REG_SC_BK0A_62_H _PK_H_(0x0A, 0x62) ++#define REG_SC_BK0A_63_L _PK_L_(0x0A, 0x63) ++#define REG_SC_BK0A_63_H _PK_H_(0x0A, 0x63) ++#define REG_SC_BK0A_64_L _PK_L_(0x0A, 0x64) ++#define REG_SC_BK0A_64_H _PK_H_(0x0A, 0x64) ++#define REG_SC_BK0A_65_L _PK_L_(0x0A, 0x65) ++#define REG_SC_BK0A_65_H _PK_H_(0x0A, 0x65) ++#define REG_SC_BK0A_66_L _PK_L_(0x0A, 0x66) ++#define REG_SC_BK0A_66_H _PK_H_(0x0A, 0x66) ++#define REG_SC_BK0A_67_L _PK_L_(0x0A, 0x67) ++#define REG_SC_BK0A_67_H _PK_H_(0x0A, 0x67) ++#define REG_SC_BK0A_68_L _PK_L_(0x0A, 0x68) ++#define REG_SC_BK0A_68_H _PK_H_(0x0A, 0x68) ++#define REG_SC_BK0A_69_L _PK_L_(0x0A, 0x69) ++#define REG_SC_BK0A_69_H _PK_H_(0x0A, 0x69) ++#define REG_SC_BK0A_6A_L _PK_L_(0x0A, 0x6A) ++#define REG_SC_BK0A_6A_H _PK_H_(0x0A, 0x6A) ++#define REG_SC_BK0A_6B_L _PK_L_(0x0A, 0x6B) ++#define REG_SC_BK0A_6B_H _PK_H_(0x0A, 0x6B) ++#define REG_SC_BK0A_6C_L _PK_L_(0x0A, 0x6C) ++#define REG_SC_BK0A_6C_H _PK_H_(0x0A, 0x6C) ++#define REG_SC_BK0A_6D_L _PK_L_(0x0A, 0x6D) ++#define REG_SC_BK0A_6D_H _PK_H_(0x0A, 0x6D) ++#define REG_SC_BK0A_6E_L _PK_L_(0x0A, 0x6E) ++#define REG_SC_BK0A_6E_H _PK_H_(0x0A, 0x6E) ++#define REG_SC_BK0A_6F_L _PK_L_(0x0A, 0x6F) ++#define REG_SC_BK0A_6F_H _PK_H_(0x0A, 0x6F) ++#define REG_SC_BK0A_70_L _PK_L_(0x0A, 0x70) ++#define REG_SC_BK0A_70_H _PK_H_(0x0A, 0x70) ++#define REG_SC_BK0A_71_L _PK_L_(0x0A, 0x71) ++#define REG_SC_BK0A_71_H _PK_H_(0x0A, 0x71) ++#define REG_SC_BK0A_72_L _PK_L_(0x0A, 0x72) ++#define REG_SC_BK0A_72_H _PK_H_(0x0A, 0x72) ++#define REG_SC_BK0A_73_L _PK_L_(0x0A, 0x73) ++#define REG_SC_BK0A_73_H _PK_H_(0x0A, 0x73) ++#define REG_SC_BK0A_74_L _PK_L_(0x0A, 0x74) ++#define REG_SC_BK0A_74_H _PK_H_(0x0A, 0x74) ++#define REG_SC_BK0A_75_L _PK_L_(0x0A, 0x75) ++#define REG_SC_BK0A_75_H _PK_H_(0x0A, 0x75) ++#define REG_SC_BK0A_76_L _PK_L_(0x0A, 0x76) ++#define REG_SC_BK0A_76_H _PK_H_(0x0A, 0x76) ++#define REG_SC_BK0A_77_L _PK_L_(0x0A, 0x77) ++#define REG_SC_BK0A_77_H _PK_H_(0x0A, 0x77) ++#define REG_SC_BK0A_78_L _PK_L_(0x0A, 0x78) ++#define REG_SC_BK0A_78_H _PK_H_(0x0A, 0x78) ++#define REG_SC_BK0A_79_L _PK_L_(0x0A, 0x79) ++#define REG_SC_BK0A_79_H _PK_H_(0x0A, 0x79) ++#define REG_SC_BK0A_7A_L _PK_L_(0x0A, 0x7A) ++#define REG_SC_BK0A_7A_H _PK_H_(0x0A, 0x7A) ++#define REG_SC_BK0A_7B_L _PK_L_(0x0A, 0x7B) ++#define REG_SC_BK0A_7B_H _PK_H_(0x0A, 0x7B) ++#define REG_SC_BK0A_7C_L _PK_L_(0x0A, 0x7C) ++#define REG_SC_BK0A_7C_H _PK_H_(0x0A, 0x7C) ++#define REG_SC_BK0A_7D_L _PK_L_(0x0A, 0x7D) ++#define REG_SC_BK0A_7D_H _PK_H_(0x0A, 0x7D) ++#define REG_SC_BK0A_7E_L _PK_L_(0x0A, 0x7E) ++#define REG_SC_BK0A_7E_H _PK_H_(0x0A, 0x7E) ++#define REG_SC_BK0A_7F_L _PK_L_(0x0A, 0x7F) ++#define REG_SC_BK0A_7F_H _PK_H_(0x0A, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0B_00_L _PK_L_(0x0B, 0x00) ++#define REG_SC_BK0B_00_H _PK_H_(0x0B, 0x00) ++#define REG_SC_BK0B_01_L _PK_L_(0x0B, 0x01) ++#define REG_SC_BK0B_01_H _PK_H_(0x0B, 0x01) ++#define REG_SC_BK0B_02_L _PK_L_(0x0B, 0x02) ++#define REG_SC_BK0B_02_H _PK_H_(0x0B, 0x02) ++#define REG_SC_BK0B_03_L _PK_L_(0x0B, 0x03) ++#define REG_SC_BK0B_03_H _PK_H_(0x0B, 0x03) ++#define REG_SC_BK0B_04_L _PK_L_(0x0B, 0x04) ++#define REG_SC_BK0B_04_H _PK_H_(0x0B, 0x04) ++#define REG_SC_BK0B_05_L _PK_L_(0x0B, 0x05) ++#define REG_SC_BK0B_05_H _PK_H_(0x0B, 0x05) ++#define REG_SC_BK0B_06_L _PK_L_(0x0B, 0x06) ++#define REG_SC_BK0B_06_H _PK_H_(0x0B, 0x06) ++#define REG_SC_BK0B_07_L _PK_L_(0x0B, 0x07) ++#define REG_SC_BK0B_07_H _PK_H_(0x0B, 0x07) ++#define REG_SC_BK0B_08_L _PK_L_(0x0B, 0x08) ++#define REG_SC_BK0B_08_H _PK_H_(0x0B, 0x08) ++#define REG_SC_BK0B_09_L _PK_L_(0x0B, 0x09) ++#define REG_SC_BK0B_09_H _PK_H_(0x0B, 0x09) ++#define REG_SC_BK0B_0A_L _PK_L_(0x0B, 0x0A) ++#define REG_SC_BK0B_0A_H _PK_H_(0x0B, 0x0A) ++#define REG_SC_BK0B_0B_L _PK_L_(0x0B, 0x0B) ++#define REG_SC_BK0B_0B_H _PK_H_(0x0B, 0x0B) ++#define REG_SC_BK0B_0C_L _PK_L_(0x0B, 0x0C) ++#define REG_SC_BK0B_0C_H _PK_H_(0x0B, 0x0C) ++#define REG_SC_BK0B_0D_L _PK_L_(0x0B, 0x0D) ++#define REG_SC_BK0B_0D_H _PK_H_(0x0B, 0x0D) ++#define REG_SC_BK0B_0E_L _PK_L_(0x0B, 0x0E) ++#define REG_SC_BK0B_0E_H _PK_H_(0x0B, 0x0E) ++#define REG_SC_BK0B_0F_L _PK_L_(0x0B, 0x0F) ++#define REG_SC_BK0B_0F_H _PK_H_(0x0B, 0x0F) ++#define REG_SC_BK0B_10_L _PK_L_(0x0B, 0x10) ++#define REG_SC_BK0B_10_H _PK_H_(0x0B, 0x10) ++#define REG_SC_BK0B_11_L _PK_L_(0x0B, 0x11) ++#define REG_SC_BK0B_11_H _PK_H_(0x0B, 0x11) ++#define REG_SC_BK0B_12_L _PK_L_(0x0B, 0x12) ++#define REG_SC_BK0B_12_H _PK_H_(0x0B, 0x12) ++#define REG_SC_BK0B_13_L _PK_L_(0x0B, 0x13) ++#define REG_SC_BK0B_13_H _PK_H_(0x0B, 0x13) ++#define REG_SC_BK0B_14_L _PK_L_(0x0B, 0x14) ++#define REG_SC_BK0B_14_H _PK_H_(0x0B, 0x14) ++#define REG_SC_BK0B_15_L _PK_L_(0x0B, 0x15) ++#define REG_SC_BK0B_15_H _PK_H_(0x0B, 0x15) ++#define REG_SC_BK0B_16_L _PK_L_(0x0B, 0x16) ++#define REG_SC_BK0B_16_H _PK_H_(0x0B, 0x16) ++#define REG_SC_BK0B_17_L _PK_L_(0x0B, 0x17) ++#define REG_SC_BK0B_17_H _PK_H_(0x0B, 0x17) ++#define REG_SC_BK0B_18_L _PK_L_(0x0B, 0x18) ++#define REG_SC_BK0B_18_H _PK_H_(0x0B, 0x18) ++#define REG_SC_BK0B_19_L _PK_L_(0x0B, 0x19) ++#define REG_SC_BK0B_19_H _PK_H_(0x0B, 0x19) ++#define REG_SC_BK0B_1A_L _PK_L_(0x0B, 0x1A) ++#define REG_SC_BK0B_1A_H _PK_H_(0x0B, 0x1A) ++#define REG_SC_BK0B_1B_L _PK_L_(0x0B, 0x1B) ++#define REG_SC_BK0B_1B_H _PK_H_(0x0B, 0x1B) ++#define REG_SC_BK0B_1C_L _PK_L_(0x0B, 0x1C) ++#define REG_SC_BK0B_1C_H _PK_H_(0x0B, 0x1C) ++#define REG_SC_BK0B_1D_L _PK_L_(0x0B, 0x1D) ++#define REG_SC_BK0B_1D_H _PK_H_(0x0B, 0x1D) ++#define REG_SC_BK0B_1E_L _PK_L_(0x0B, 0x1E) ++#define REG_SC_BK0B_1E_H _PK_H_(0x0B, 0x1E) ++#define REG_SC_BK0B_1F_L _PK_L_(0x0B, 0x1F) ++#define REG_SC_BK0B_1F_H _PK_H_(0x0B, 0x1F) ++#define REG_SC_BK0B_20_L _PK_L_(0x0B, 0x20) ++#define REG_SC_BK0B_20_H _PK_H_(0x0B, 0x20) ++#define REG_SC_BK0B_21_L _PK_L_(0x0B, 0x21) ++#define REG_SC_BK0B_21_H _PK_H_(0x0B, 0x21) ++#define REG_SC_BK0B_22_L _PK_L_(0x0B, 0x22) ++#define REG_SC_BK0B_22_H _PK_H_(0x0B, 0x22) ++#define REG_SC_BK0B_23_L _PK_L_(0x0B, 0x23) ++#define REG_SC_BK0B_23_H _PK_H_(0x0B, 0x23) ++#define REG_SC_BK0B_24_L _PK_L_(0x0B, 0x24) ++#define REG_SC_BK0B_24_H _PK_H_(0x0B, 0x24) ++#define REG_SC_BK0B_25_L _PK_L_(0x0B, 0x25) ++#define REG_SC_BK0B_25_H _PK_H_(0x0B, 0x25) ++#define REG_SC_BK0B_26_L _PK_L_(0x0B, 0x26) ++#define REG_SC_BK0B_26_H _PK_H_(0x0B, 0x26) ++#define REG_SC_BK0B_27_L _PK_L_(0x0B, 0x27) ++#define REG_SC_BK0B_27_H _PK_H_(0x0B, 0x27) ++#define REG_SC_BK0B_28_L _PK_L_(0x0B, 0x28) ++#define REG_SC_BK0B_28_H _PK_H_(0x0B, 0x28) ++#define REG_SC_BK0B_29_L _PK_L_(0x0B, 0x29) ++#define REG_SC_BK0B_29_H _PK_H_(0x0B, 0x29) ++#define REG_SC_BK0B_2A_L _PK_L_(0x0B, 0x2A) ++#define REG_SC_BK0B_2A_H _PK_H_(0x0B, 0x2A) ++#define REG_SC_BK0B_2B_L _PK_L_(0x0B, 0x2B) ++#define REG_SC_BK0B_2B_H _PK_H_(0x0B, 0x2B) ++#define REG_SC_BK0B_2C_L _PK_L_(0x0B, 0x2C) ++#define REG_SC_BK0B_2C_H _PK_H_(0x0B, 0x2C) ++#define REG_SC_BK0B_2D_L _PK_L_(0x0B, 0x2D) ++#define REG_SC_BK0B_2D_H _PK_H_(0x0B, 0x2D) ++#define REG_SC_BK0B_2E_L _PK_L_(0x0B, 0x2E) ++#define REG_SC_BK0B_2E_H _PK_H_(0x0B, 0x2E) ++#define REG_SC_BK0B_2F_L _PK_L_(0x0B, 0x2F) ++#define REG_SC_BK0B_2F_H _PK_H_(0x0B, 0x2F) ++#define REG_SC_BK0B_30_L _PK_L_(0x0B, 0x30) ++#define REG_SC_BK0B_30_H _PK_H_(0x0B, 0x30) ++#define REG_SC_BK0B_31_L _PK_L_(0x0B, 0x31) ++#define REG_SC_BK0B_31_H _PK_H_(0x0B, 0x31) ++#define REG_SC_BK0B_32_L _PK_L_(0x0B, 0x32) ++#define REG_SC_BK0B_32_H _PK_H_(0x0B, 0x32) ++#define REG_SC_BK0B_33_L _PK_L_(0x0B, 0x33) ++#define REG_SC_BK0B_33_H _PK_H_(0x0B, 0x33) ++#define REG_SC_BK0B_34_L _PK_L_(0x0B, 0x34) ++#define REG_SC_BK0B_34_H _PK_H_(0x0B, 0x34) ++#define REG_SC_BK0B_35_L _PK_L_(0x0B, 0x35) ++#define REG_SC_BK0B_35_H _PK_H_(0x0B, 0x35) ++#define REG_SC_BK0B_36_L _PK_L_(0x0B, 0x36) ++#define REG_SC_BK0B_36_H _PK_H_(0x0B, 0x36) ++#define REG_SC_BK0B_37_L _PK_L_(0x0B, 0x37) ++#define REG_SC_BK0B_37_H _PK_H_(0x0B, 0x37) ++#define REG_SC_BK0B_38_L _PK_L_(0x0B, 0x38) ++#define REG_SC_BK0B_38_H _PK_H_(0x0B, 0x38) ++#define REG_SC_BK0B_39_L _PK_L_(0x0B, 0x39) ++#define REG_SC_BK0B_39_H _PK_H_(0x0B, 0x39) ++#define REG_SC_BK0B_3A_L _PK_L_(0x0B, 0x3A) ++#define REG_SC_BK0B_3A_H _PK_H_(0x0B, 0x3A) ++#define REG_SC_BK0B_3B_L _PK_L_(0x0B, 0x3B) ++#define REG_SC_BK0B_3B_H _PK_H_(0x0B, 0x3B) ++#define REG_SC_BK0B_3C_L _PK_L_(0x0B, 0x3C) ++#define REG_SC_BK0B_3C_H _PK_H_(0x0B, 0x3C) ++#define REG_SC_BK0B_3D_L _PK_L_(0x0B, 0x3D) ++#define REG_SC_BK0B_3D_H _PK_H_(0x0B, 0x3D) ++#define REG_SC_BK0B_3E_L _PK_L_(0x0B, 0x3E) ++#define REG_SC_BK0B_3E_H _PK_H_(0x0B, 0x3E) ++#define REG_SC_BK0B_3F_L _PK_L_(0x0B, 0x3F) ++#define REG_SC_BK0B_3F_H _PK_H_(0x0B, 0x3F) ++#define REG_SC_BK0B_40_L _PK_L_(0x0B, 0x40) ++#define REG_SC_BK0B_40_H _PK_H_(0x0B, 0x40) ++#define REG_SC_BK0B_41_L _PK_L_(0x0B, 0x41) ++#define REG_SC_BK0B_41_H _PK_H_(0x0B, 0x41) ++#define REG_SC_BK0B_42_L _PK_L_(0x0B, 0x42) ++#define REG_SC_BK0B_42_H _PK_H_(0x0B, 0x42) ++#define REG_SC_BK0B_43_L _PK_L_(0x0B, 0x43) ++#define REG_SC_BK0B_43_H _PK_H_(0x0B, 0x43) ++#define REG_SC_BK0B_44_L _PK_L_(0x0B, 0x44) ++#define REG_SC_BK0B_44_H _PK_H_(0x0B, 0x44) ++#define REG_SC_BK0B_45_L _PK_L_(0x0B, 0x45) ++#define REG_SC_BK0B_45_H _PK_H_(0x0B, 0x45) ++#define REG_SC_BK0B_46_L _PK_L_(0x0B, 0x46) ++#define REG_SC_BK0B_46_H _PK_H_(0x0B, 0x46) ++#define REG_SC_BK0B_47_L _PK_L_(0x0B, 0x47) ++#define REG_SC_BK0B_47_H _PK_H_(0x0B, 0x47) ++#define REG_SC_BK0B_48_L _PK_L_(0x0B, 0x48) ++#define REG_SC_BK0B_48_H _PK_H_(0x0B, 0x48) ++#define REG_SC_BK0B_49_L _PK_L_(0x0B, 0x49) ++#define REG_SC_BK0B_49_H _PK_H_(0x0B, 0x49) ++#define REG_SC_BK0B_4A_L _PK_L_(0x0B, 0x4A) ++#define REG_SC_BK0B_4A_H _PK_H_(0x0B, 0x4A) ++#define REG_SC_BK0B_4B_L _PK_L_(0x0B, 0x4B) ++#define REG_SC_BK0B_4B_H _PK_H_(0x0B, 0x4B) ++#define REG_SC_BK0B_4C_L _PK_L_(0x0B, 0x4C) ++#define REG_SC_BK0B_4C_H _PK_H_(0x0B, 0x4C) ++#define REG_SC_BK0B_4D_L _PK_L_(0x0B, 0x4D) ++#define REG_SC_BK0B_4D_H _PK_H_(0x0B, 0x4D) ++#define REG_SC_BK0B_4E_L _PK_L_(0x0B, 0x4E) ++#define REG_SC_BK0B_4E_H _PK_H_(0x0B, 0x4E) ++#define REG_SC_BK0B_4F_L _PK_L_(0x0B, 0x4F) ++#define REG_SC_BK0B_4F_H _PK_H_(0x0B, 0x4F) ++#define REG_SC_BK0B_50_L _PK_L_(0x0B, 0x50) ++#define REG_SC_BK0B_50_H _PK_H_(0x0B, 0x50) ++#define REG_SC_BK0B_51_L _PK_L_(0x0B, 0x51) ++#define REG_SC_BK0B_51_H _PK_H_(0x0B, 0x51) ++#define REG_SC_BK0B_52_L _PK_L_(0x0B, 0x52) ++#define REG_SC_BK0B_52_H _PK_H_(0x0B, 0x52) ++#define REG_SC_BK0B_53_L _PK_L_(0x0B, 0x53) ++#define REG_SC_BK0B_53_H _PK_H_(0x0B, 0x53) ++#define REG_SC_BK0B_54_L _PK_L_(0x0B, 0x54) ++#define REG_SC_BK0B_54_H _PK_H_(0x0B, 0x54) ++#define REG_SC_BK0B_55_L _PK_L_(0x0B, 0x55) ++#define REG_SC_BK0B_55_H _PK_H_(0x0B, 0x55) ++#define REG_SC_BK0B_56_L _PK_L_(0x0B, 0x56) ++#define REG_SC_BK0B_56_H _PK_H_(0x0B, 0x56) ++#define REG_SC_BK0B_57_L _PK_L_(0x0B, 0x57) ++#define REG_SC_BK0B_57_H _PK_H_(0x0B, 0x57) ++#define REG_SC_BK0B_58_L _PK_L_(0x0B, 0x58) ++#define REG_SC_BK0B_58_H _PK_H_(0x0B, 0x58) ++#define REG_SC_BK0B_59_L _PK_L_(0x0B, 0x59) ++#define REG_SC_BK0B_59_H _PK_H_(0x0B, 0x59) ++#define REG_SC_BK0B_5A_L _PK_L_(0x0B, 0x5A) ++#define REG_SC_BK0B_5A_H _PK_H_(0x0B, 0x5A) ++#define REG_SC_BK0B_5B_L _PK_L_(0x0B, 0x5B) ++#define REG_SC_BK0B_5B_H _PK_H_(0x0B, 0x5B) ++#define REG_SC_BK0B_5C_L _PK_L_(0x0B, 0x5C) ++#define REG_SC_BK0B_5C_H _PK_H_(0x0B, 0x5C) ++#define REG_SC_BK0B_5D_L _PK_L_(0x0B, 0x5D) ++#define REG_SC_BK0B_5D_H _PK_H_(0x0B, 0x5D) ++#define REG_SC_BK0B_5E_L _PK_L_(0x0B, 0x5E) ++#define REG_SC_BK0B_5E_H _PK_H_(0x0B, 0x5E) ++#define REG_SC_BK0B_5F_L _PK_L_(0x0B, 0x5F) ++#define REG_SC_BK0B_5F_H _PK_H_(0x0B, 0x5F) ++#define REG_SC_BK0B_60_L _PK_L_(0x0B, 0x60) ++#define REG_SC_BK0B_60_H _PK_H_(0x0B, 0x60) ++#define REG_SC_BK0B_61_L _PK_L_(0x0B, 0x61) ++#define REG_SC_BK0B_61_H _PK_H_(0x0B, 0x61) ++#define REG_SC_BK0B_62_L _PK_L_(0x0B, 0x62) ++#define REG_SC_BK0B_62_H _PK_H_(0x0B, 0x62) ++#define REG_SC_BK0B_63_L _PK_L_(0x0B, 0x63) ++#define REG_SC_BK0B_63_H _PK_H_(0x0B, 0x63) ++#define REG_SC_BK0B_64_L _PK_L_(0x0B, 0x64) ++#define REG_SC_BK0B_64_H _PK_H_(0x0B, 0x64) ++#define REG_SC_BK0B_65_L _PK_L_(0x0B, 0x65) ++#define REG_SC_BK0B_65_H _PK_H_(0x0B, 0x65) ++#define REG_SC_BK0B_66_L _PK_L_(0x0B, 0x66) ++#define REG_SC_BK0B_66_H _PK_H_(0x0B, 0x66) ++#define REG_SC_BK0B_67_L _PK_L_(0x0B, 0x67) ++#define REG_SC_BK0B_67_H _PK_H_(0x0B, 0x67) ++#define REG_SC_BK0B_68_L _PK_L_(0x0B, 0x68) ++#define REG_SC_BK0B_68_H _PK_H_(0x0B, 0x68) ++#define REG_SC_BK0B_69_L _PK_L_(0x0B, 0x69) ++#define REG_SC_BK0B_69_H _PK_H_(0x0B, 0x69) ++#define REG_SC_BK0B_6A_L _PK_L_(0x0B, 0x6A) ++#define REG_SC_BK0B_6A_H _PK_H_(0x0B, 0x6A) ++#define REG_SC_BK0B_6B_L _PK_L_(0x0B, 0x6B) ++#define REG_SC_BK0B_6B_H _PK_H_(0x0B, 0x6B) ++#define REG_SC_BK0B_6C_L _PK_L_(0x0B, 0x6C) ++#define REG_SC_BK0B_6C_H _PK_H_(0x0B, 0x6C) ++#define REG_SC_BK0B_6D_L _PK_L_(0x0B, 0x6D) ++#define REG_SC_BK0B_6D_H _PK_H_(0x0B, 0x6D) ++#define REG_SC_BK0B_6E_L _PK_L_(0x0B, 0x6E) ++#define REG_SC_BK0B_6E_H _PK_H_(0x0B, 0x6E) ++#define REG_SC_BK0B_6F_L _PK_L_(0x0B, 0x6F) ++#define REG_SC_BK0B_6F_H _PK_H_(0x0B, 0x6F) ++#define REG_SC_BK0B_70_L _PK_L_(0x0B, 0x70) ++#define REG_SC_BK0B_70_H _PK_H_(0x0B, 0x70) ++#define REG_SC_BK0B_71_L _PK_L_(0x0B, 0x71) ++#define REG_SC_BK0B_71_H _PK_H_(0x0B, 0x71) ++#define REG_SC_BK0B_72_L _PK_L_(0x0B, 0x72) ++#define REG_SC_BK0B_72_H _PK_H_(0x0B, 0x72) ++#define REG_SC_BK0B_73_L _PK_L_(0x0B, 0x73) ++#define REG_SC_BK0B_73_H _PK_H_(0x0B, 0x73) ++#define REG_SC_BK0B_74_L _PK_L_(0x0B, 0x74) ++#define REG_SC_BK0B_74_H _PK_H_(0x0B, 0x74) ++#define REG_SC_BK0B_75_L _PK_L_(0x0B, 0x75) ++#define REG_SC_BK0B_75_H _PK_H_(0x0B, 0x75) ++#define REG_SC_BK0B_76_L _PK_L_(0x0B, 0x76) ++#define REG_SC_BK0B_76_H _PK_H_(0x0B, 0x76) ++#define REG_SC_BK0B_77_L _PK_L_(0x0B, 0x77) ++#define REG_SC_BK0B_77_H _PK_H_(0x0B, 0x77) ++#define REG_SC_BK0B_78_L _PK_L_(0x0B, 0x78) ++#define REG_SC_BK0B_78_H _PK_H_(0x0B, 0x78) ++#define REG_SC_BK0B_79_L _PK_L_(0x0B, 0x79) ++#define REG_SC_BK0B_79_H _PK_H_(0x0B, 0x79) ++#define REG_SC_BK0B_7A_L _PK_L_(0x0B, 0x7A) ++#define REG_SC_BK0B_7A_H _PK_H_(0x0B, 0x7A) ++#define REG_SC_BK0B_7B_L _PK_L_(0x0B, 0x7B) ++#define REG_SC_BK0B_7B_H _PK_H_(0x0B, 0x7B) ++#define REG_SC_BK0B_7C_L _PK_L_(0x0B, 0x7C) ++#define REG_SC_BK0B_7C_H _PK_H_(0x0B, 0x7C) ++#define REG_SC_BK0B_7D_L _PK_L_(0x0B, 0x7D) ++#define REG_SC_BK0B_7D_H _PK_H_(0x0B, 0x7D) ++#define REG_SC_BK0B_7E_L _PK_L_(0x0B, 0x7E) ++#define REG_SC_BK0B_7E_H _PK_H_(0x0B, 0x7E) ++#define REG_SC_BK0B_7F_L _PK_L_(0x0B, 0x7F) ++#define REG_SC_BK0B_7F_H _PK_H_(0x0B, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0C_00_L _PK_L_(0x0C, 0x00) ++#define REG_SC_BK0C_00_H _PK_H_(0x0C, 0x00) ++#define REG_SC_BK0C_01_L _PK_L_(0x0C, 0x01) ++#define REG_SC_BK0C_01_H _PK_H_(0x0C, 0x01) ++#define REG_SC_BK0C_02_L _PK_L_(0x0C, 0x02) ++#define REG_SC_BK0C_02_H _PK_H_(0x0C, 0x02) ++#define REG_SC_BK0C_03_L _PK_L_(0x0C, 0x03) ++#define REG_SC_BK0C_03_H _PK_H_(0x0C, 0x03) ++#define REG_SC_BK0C_04_L _PK_L_(0x0C, 0x04) ++#define REG_SC_BK0C_04_H _PK_H_(0x0C, 0x04) ++#define REG_SC_BK0C_05_L _PK_L_(0x0C, 0x05) ++#define REG_SC_BK0C_05_H _PK_H_(0x0C, 0x05) ++#define REG_SC_BK0C_06_L _PK_L_(0x0C, 0x06) ++#define REG_SC_BK0C_06_H _PK_H_(0x0C, 0x06) ++#define REG_SC_BK0C_07_L _PK_L_(0x0C, 0x07) ++#define REG_SC_BK0C_07_H _PK_H_(0x0C, 0x07) ++#define REG_SC_BK0C_08_L _PK_L_(0x0C, 0x08) ++#define REG_SC_BK0C_08_H _PK_H_(0x0C, 0x08) ++#define REG_SC_BK0C_09_L _PK_L_(0x0C, 0x09) ++#define REG_SC_BK0C_09_H _PK_H_(0x0C, 0x09) ++#define REG_SC_BK0C_0A_L _PK_L_(0x0C, 0x0A) ++#define REG_SC_BK0C_0A_H _PK_H_(0x0C, 0x0A) ++#define REG_SC_BK0C_0B_L _PK_L_(0x0C, 0x0B) ++#define REG_SC_BK0C_0B_H _PK_H_(0x0C, 0x0B) ++#define REG_SC_BK0C_0C_L _PK_L_(0x0C, 0x0C) ++#define REG_SC_BK0C_0C_H _PK_H_(0x0C, 0x0C) ++#define REG_SC_BK0C_0D_L _PK_L_(0x0C, 0x0D) ++#define REG_SC_BK0C_0D_H _PK_H_(0x0C, 0x0D) ++#define REG_SC_BK0C_0E_L _PK_L_(0x0C, 0x0E) ++#define REG_SC_BK0C_0E_H _PK_H_(0x0C, 0x0E) ++#define REG_SC_BK0C_0F_L _PK_L_(0x0C, 0x0F) ++#define REG_SC_BK0C_0F_H _PK_H_(0x0C, 0x0F) ++#define REG_SC_BK0C_10_L _PK_L_(0x0C, 0x10) ++#define REG_SC_BK0C_10_H _PK_H_(0x0C, 0x10) ++#define REG_SC_BK0C_11_L _PK_L_(0x0C, 0x11) ++#define REG_SC_BK0C_11_H _PK_H_(0x0C, 0x11) ++#define REG_SC_BK0C_12_L _PK_L_(0x0C, 0x12) ++#define REG_SC_BK0C_12_H _PK_H_(0x0C, 0x12) ++#define REG_SC_BK0C_13_L _PK_L_(0x0C, 0x13) ++#define REG_SC_BK0C_13_H _PK_H_(0x0C, 0x13) ++#define REG_SC_BK0C_14_L _PK_L_(0x0C, 0x14) ++#define REG_SC_BK0C_14_H _PK_H_(0x0C, 0x14) ++#define REG_SC_BK0C_15_L _PK_L_(0x0C, 0x15) ++#define REG_SC_BK0C_15_H _PK_H_(0x0C, 0x15) ++#define REG_SC_BK0C_16_L _PK_L_(0x0C, 0x16) ++#define REG_SC_BK0C_16_H _PK_H_(0x0C, 0x16) ++#define REG_SC_BK0C_17_L _PK_L_(0x0C, 0x17) ++#define REG_SC_BK0C_17_H _PK_H_(0x0C, 0x17) ++#define REG_SC_BK0C_18_L _PK_L_(0x0C, 0x18) ++#define REG_SC_BK0C_18_H _PK_H_(0x0C, 0x18) ++#define REG_SC_BK0C_19_L _PK_L_(0x0C, 0x19) ++#define REG_SC_BK0C_19_H _PK_H_(0x0C, 0x19) ++#define REG_SC_BK0C_1A_L _PK_L_(0x0C, 0x1A) ++#define REG_SC_BK0C_1A_H _PK_H_(0x0C, 0x1A) ++#define REG_SC_BK0C_1B_L _PK_L_(0x0C, 0x1B) ++#define REG_SC_BK0C_1B_H _PK_H_(0x0C, 0x1B) ++#define REG_SC_BK0C_1C_L _PK_L_(0x0C, 0x1C) ++#define REG_SC_BK0C_1C_H _PK_H_(0x0C, 0x1C) ++#define REG_SC_BK0C_1D_L _PK_L_(0x0C, 0x1D) ++#define REG_SC_BK0C_1D_H _PK_H_(0x0C, 0x1D) ++#define REG_SC_BK0C_1E_L _PK_L_(0x0C, 0x1E) ++#define REG_SC_BK0C_1E_H _PK_H_(0x0C, 0x1E) ++#define REG_SC_BK0C_1F_L _PK_L_(0x0C, 0x1F) ++#define REG_SC_BK0C_1F_H _PK_H_(0x0C, 0x1F) ++#define REG_SC_BK0C_20_L _PK_L_(0x0C, 0x20) ++#define REG_SC_BK0C_20_H _PK_H_(0x0C, 0x20) ++#define REG_SC_BK0C_21_L _PK_L_(0x0C, 0x21) ++#define REG_SC_BK0C_21_H _PK_H_(0x0C, 0x21) ++#define REG_SC_BK0C_22_L _PK_L_(0x0C, 0x22) ++#define REG_SC_BK0C_22_H _PK_H_(0x0C, 0x22) ++#define REG_SC_BK0C_23_L _PK_L_(0x0C, 0x23) ++#define REG_SC_BK0C_23_H _PK_H_(0x0C, 0x23) ++#define REG_SC_BK0C_24_L _PK_L_(0x0C, 0x24) ++#define REG_SC_BK0C_24_H _PK_H_(0x0C, 0x24) ++#define REG_SC_BK0C_25_L _PK_L_(0x0C, 0x25) ++#define REG_SC_BK0C_25_H _PK_H_(0x0C, 0x25) ++#define REG_SC_BK0C_26_L _PK_L_(0x0C, 0x26) ++#define REG_SC_BK0C_26_H _PK_H_(0x0C, 0x26) ++#define REG_SC_BK0C_27_L _PK_L_(0x0C, 0x27) ++#define REG_SC_BK0C_27_H _PK_H_(0x0C, 0x27) ++#define REG_SC_BK0C_28_L _PK_L_(0x0C, 0x28) ++#define REG_SC_BK0C_28_H _PK_H_(0x0C, 0x28) ++#define REG_SC_BK0C_29_L _PK_L_(0x0C, 0x29) ++#define REG_SC_BK0C_29_H _PK_H_(0x0C, 0x29) ++#define REG_SC_BK0C_2A_L _PK_L_(0x0C, 0x2A) ++#define REG_SC_BK0C_2A_H _PK_H_(0x0C, 0x2A) ++#define REG_SC_BK0C_2B_L _PK_L_(0x0C, 0x2B) ++#define REG_SC_BK0C_2B_H _PK_H_(0x0C, 0x2B) ++#define REG_SC_BK0C_2C_L _PK_L_(0x0C, 0x2C) ++#define REG_SC_BK0C_2C_H _PK_H_(0x0C, 0x2C) ++#define REG_SC_BK0C_2D_L _PK_L_(0x0C, 0x2D) ++#define REG_SC_BK0C_2D_H _PK_H_(0x0C, 0x2D) ++#define REG_SC_BK0C_2E_L _PK_L_(0x0C, 0x2E) ++#define REG_SC_BK0C_2E_H _PK_H_(0x0C, 0x2E) ++#define REG_SC_BK0C_2F_L _PK_L_(0x0C, 0x2F) ++#define REG_SC_BK0C_2F_H _PK_H_(0x0C, 0x2F) ++#define REG_SC_BK0C_30_L _PK_L_(0x0C, 0x30) ++#define REG_SC_BK0C_30_H _PK_H_(0x0C, 0x30) ++#define REG_SC_BK0C_31_L _PK_L_(0x0C, 0x31) ++#define REG_SC_BK0C_31_H _PK_H_(0x0C, 0x31) ++#define REG_SC_BK0C_32_L _PK_L_(0x0C, 0x32) ++#define REG_SC_BK0C_32_H _PK_H_(0x0C, 0x32) ++#define REG_SC_BK0C_33_L _PK_L_(0x0C, 0x33) ++#define REG_SC_BK0C_33_H _PK_H_(0x0C, 0x33) ++#define REG_SC_BK0C_34_L _PK_L_(0x0C, 0x34) ++#define REG_SC_BK0C_34_H _PK_H_(0x0C, 0x34) ++#define REG_SC_BK0C_35_L _PK_L_(0x0C, 0x35) ++#define REG_SC_BK0C_35_H _PK_H_(0x0C, 0x35) ++#define REG_SC_BK0C_36_L _PK_L_(0x0C, 0x36) ++#define REG_SC_BK0C_36_H _PK_H_(0x0C, 0x36) ++#define REG_SC_BK0C_37_L _PK_L_(0x0C, 0x37) ++#define REG_SC_BK0C_37_H _PK_H_(0x0C, 0x37) ++#define REG_SC_BK0C_38_L _PK_L_(0x0C, 0x38) ++#define REG_SC_BK0C_38_H _PK_H_(0x0C, 0x38) ++#define REG_SC_BK0C_39_L _PK_L_(0x0C, 0x39) ++#define REG_SC_BK0C_39_H _PK_H_(0x0C, 0x39) ++#define REG_SC_BK0C_3A_L _PK_L_(0x0C, 0x3A) ++#define REG_SC_BK0C_3A_H _PK_H_(0x0C, 0x3A) ++#define REG_SC_BK0C_3B_L _PK_L_(0x0C, 0x3B) ++#define REG_SC_BK0C_3B_H _PK_H_(0x0C, 0x3B) ++#define REG_SC_BK0C_3C_L _PK_L_(0x0C, 0x3C) ++#define REG_SC_BK0C_3C_H _PK_H_(0x0C, 0x3C) ++#define REG_SC_BK0C_3D_L _PK_L_(0x0C, 0x3D) ++#define REG_SC_BK0C_3D_H _PK_H_(0x0C, 0x3D) ++#define REG_SC_BK0C_3E_L _PK_L_(0x0C, 0x3E) ++#define REG_SC_BK0C_3E_H _PK_H_(0x0C, 0x3E) ++#define REG_SC_BK0C_3F_L _PK_L_(0x0C, 0x3F) ++#define REG_SC_BK0C_3F_H _PK_H_(0x0C, 0x3F) ++#define REG_SC_BK0C_40_L _PK_L_(0x0C, 0x40) ++#define REG_SC_BK0C_40_H _PK_H_(0x0C, 0x40) ++#define REG_SC_BK0C_41_L _PK_L_(0x0C, 0x41) ++#define REG_SC_BK0C_41_H _PK_H_(0x0C, 0x41) ++#define REG_SC_BK0C_42_L _PK_L_(0x0C, 0x42) ++#define REG_SC_BK0C_42_H _PK_H_(0x0C, 0x42) ++#define REG_SC_BK0C_43_L _PK_L_(0x0C, 0x43) ++#define REG_SC_BK0C_43_H _PK_H_(0x0C, 0x43) ++#define REG_SC_BK0C_44_L _PK_L_(0x0C, 0x44) ++#define REG_SC_BK0C_44_H _PK_H_(0x0C, 0x44) ++#define REG_SC_BK0C_45_L _PK_L_(0x0C, 0x45) ++#define REG_SC_BK0C_45_H _PK_H_(0x0C, 0x45) ++#define REG_SC_BK0C_46_L _PK_L_(0x0C, 0x46) ++#define REG_SC_BK0C_46_H _PK_H_(0x0C, 0x46) ++#define REG_SC_BK0C_47_L _PK_L_(0x0C, 0x47) ++#define REG_SC_BK0C_47_H _PK_H_(0x0C, 0x47) ++#define REG_SC_BK0C_48_L _PK_L_(0x0C, 0x48) ++#define REG_SC_BK0C_48_H _PK_H_(0x0C, 0x48) ++#define REG_SC_BK0C_49_L _PK_L_(0x0C, 0x49) ++#define REG_SC_BK0C_49_H _PK_H_(0x0C, 0x49) ++#define REG_SC_BK0C_4A_L _PK_L_(0x0C, 0x4A) ++#define REG_SC_BK0C_4A_H _PK_H_(0x0C, 0x4A) ++#define REG_SC_BK0C_4B_L _PK_L_(0x0C, 0x4B) ++#define REG_SC_BK0C_4B_H _PK_H_(0x0C, 0x4B) ++#define REG_SC_BK0C_4C_L _PK_L_(0x0C, 0x4C) ++#define REG_SC_BK0C_4C_H _PK_H_(0x0C, 0x4C) ++#define REG_SC_BK0C_4D_L _PK_L_(0x0C, 0x4D) ++#define REG_SC_BK0C_4D_H _PK_H_(0x0C, 0x4D) ++#define REG_SC_BK0C_4E_L _PK_L_(0x0C, 0x4E) ++#define REG_SC_BK0C_4E_H _PK_H_(0x0C, 0x4E) ++#define REG_SC_BK0C_4F_L _PK_L_(0x0C, 0x4F) ++#define REG_SC_BK0C_4F_H _PK_H_(0x0C, 0x4F) ++#define REG_SC_BK0C_50_L _PK_L_(0x0C, 0x50) ++#define REG_SC_BK0C_50_H _PK_H_(0x0C, 0x50) ++#define REG_SC_BK0C_51_L _PK_L_(0x0C, 0x51) ++#define REG_SC_BK0C_51_H _PK_H_(0x0C, 0x51) ++#define REG_SC_BK0C_52_L _PK_L_(0x0C, 0x52) ++#define REG_SC_BK0C_52_H _PK_H_(0x0C, 0x52) ++#define REG_SC_BK0C_53_L _PK_L_(0x0C, 0x53) ++#define REG_SC_BK0C_53_H _PK_H_(0x0C, 0x53) ++#define REG_SC_BK0C_54_L _PK_L_(0x0C, 0x54) ++#define REG_SC_BK0C_54_H _PK_H_(0x0C, 0x54) ++#define REG_SC_BK0C_55_L _PK_L_(0x0C, 0x55) ++#define REG_SC_BK0C_55_H _PK_H_(0x0C, 0x55) ++#define REG_SC_BK0C_56_L _PK_L_(0x0C, 0x56) ++#define REG_SC_BK0C_56_H _PK_H_(0x0C, 0x56) ++#define REG_SC_BK0C_57_L _PK_L_(0x0C, 0x57) ++#define REG_SC_BK0C_57_H _PK_H_(0x0C, 0x57) ++#define REG_SC_BK0C_58_L _PK_L_(0x0C, 0x58) ++#define REG_SC_BK0C_58_H _PK_H_(0x0C, 0x58) ++#define REG_SC_BK0C_59_L _PK_L_(0x0C, 0x59) ++#define REG_SC_BK0C_59_H _PK_H_(0x0C, 0x59) ++#define REG_SC_BK0C_5A_L _PK_L_(0x0C, 0x5A) ++#define REG_SC_BK0C_5A_H _PK_H_(0x0C, 0x5A) ++#define REG_SC_BK0C_5B_L _PK_L_(0x0C, 0x5B) ++#define REG_SC_BK0C_5B_H _PK_H_(0x0C, 0x5B) ++#define REG_SC_BK0C_5C_L _PK_L_(0x0C, 0x5C) ++#define REG_SC_BK0C_5C_H _PK_H_(0x0C, 0x5C) ++#define REG_SC_BK0C_5D_L _PK_L_(0x0C, 0x5D) ++#define REG_SC_BK0C_5D_H _PK_H_(0x0C, 0x5D) ++#define REG_SC_BK0C_5E_L _PK_L_(0x0C, 0x5E) ++#define REG_SC_BK0C_5E_H _PK_H_(0x0C, 0x5E) ++#define REG_SC_BK0C_5F_L _PK_L_(0x0C, 0x5F) ++#define REG_SC_BK0C_5F_H _PK_H_(0x0C, 0x5F) ++#define REG_SC_BK0C_60_L _PK_L_(0x0C, 0x60) ++#define REG_SC_BK0C_60_H _PK_H_(0x0C, 0x60) ++#define REG_SC_BK0C_61_L _PK_L_(0x0C, 0x61) ++#define REG_SC_BK0C_61_H _PK_H_(0x0C, 0x61) ++#define REG_SC_BK0C_62_L _PK_L_(0x0C, 0x62) ++#define REG_SC_BK0C_62_H _PK_H_(0x0C, 0x62) ++#define REG_SC_BK0C_63_L _PK_L_(0x0C, 0x63) ++#define REG_SC_BK0C_63_H _PK_H_(0x0C, 0x63) ++#define REG_SC_BK0C_64_L _PK_L_(0x0C, 0x64) ++#define REG_SC_BK0C_64_H _PK_H_(0x0C, 0x64) ++#define REG_SC_BK0C_65_L _PK_L_(0x0C, 0x65) ++#define REG_SC_BK0C_65_H _PK_H_(0x0C, 0x65) ++#define REG_SC_BK0C_66_L _PK_L_(0x0C, 0x66) ++#define REG_SC_BK0C_66_H _PK_H_(0x0C, 0x66) ++#define REG_SC_BK0C_67_L _PK_L_(0x0C, 0x67) ++#define REG_SC_BK0C_67_H _PK_H_(0x0C, 0x67) ++#define REG_SC_BK0C_68_L _PK_L_(0x0C, 0x68) ++#define REG_SC_BK0C_68_H _PK_H_(0x0C, 0x68) ++#define REG_SC_BK0C_69_L _PK_L_(0x0C, 0x69) ++#define REG_SC_BK0C_69_H _PK_H_(0x0C, 0x69) ++#define REG_SC_BK0C_6A_L _PK_L_(0x0C, 0x6A) ++#define REG_SC_BK0C_6A_H _PK_H_(0x0C, 0x6A) ++#define REG_SC_BK0C_6B_L _PK_L_(0x0C, 0x6B) ++#define REG_SC_BK0C_6B_H _PK_H_(0x0C, 0x6B) ++#define REG_SC_BK0C_6C_L _PK_L_(0x0C, 0x6C) ++#define REG_SC_BK0C_6C_H _PK_H_(0x0C, 0x6C) ++#define REG_SC_BK0C_6D_L _PK_L_(0x0C, 0x6D) ++#define REG_SC_BK0C_6D_H _PK_H_(0x0C, 0x6D) ++#define REG_SC_BK0C_6E_L _PK_L_(0x0C, 0x6E) ++#define REG_SC_BK0C_6E_H _PK_H_(0x0C, 0x6E) ++#define REG_SC_BK0C_6F_L _PK_L_(0x0C, 0x6F) ++#define REG_SC_BK0C_6F_H _PK_H_(0x0C, 0x6F) ++#define REG_SC_BK0C_70_L _PK_L_(0x0C, 0x70) ++#define REG_SC_BK0C_70_H _PK_H_(0x0C, 0x70) ++#define REG_SC_BK0C_71_L _PK_L_(0x0C, 0x71) ++#define REG_SC_BK0C_71_H _PK_H_(0x0C, 0x71) ++#define REG_SC_BK0C_72_L _PK_L_(0x0C, 0x72) ++#define REG_SC_BK0C_72_H _PK_H_(0x0C, 0x72) ++#define REG_SC_BK0C_73_L _PK_L_(0x0C, 0x73) ++#define REG_SC_BK0C_73_H _PK_H_(0x0C, 0x73) ++#define REG_SC_BK0C_74_L _PK_L_(0x0C, 0x74) ++#define REG_SC_BK0C_74_H _PK_H_(0x0C, 0x74) ++#define REG_SC_BK0C_75_L _PK_L_(0x0C, 0x75) ++#define REG_SC_BK0C_75_H _PK_H_(0x0C, 0x75) ++#define REG_SC_BK0C_76_L _PK_L_(0x0C, 0x76) ++#define REG_SC_BK0C_76_H _PK_H_(0x0C, 0x76) ++#define REG_SC_BK0C_77_L _PK_L_(0x0C, 0x77) ++#define REG_SC_BK0C_77_H _PK_H_(0x0C, 0x77) ++#define REG_SC_BK0C_78_L _PK_L_(0x0C, 0x78) ++#define REG_SC_BK0C_78_H _PK_H_(0x0C, 0x78) ++#define REG_SC_BK0C_79_L _PK_L_(0x0C, 0x79) ++#define REG_SC_BK0C_79_H _PK_H_(0x0C, 0x79) ++#define REG_SC_BK0C_7A_L _PK_L_(0x0C, 0x7A) ++#define REG_SC_BK0C_7A_H _PK_H_(0x0C, 0x7A) ++#define REG_SC_BK0C_7B_L _PK_L_(0x0C, 0x7B) ++#define REG_SC_BK0C_7B_H _PK_H_(0x0C, 0x7B) ++#define REG_SC_BK0C_7C_L _PK_L_(0x0C, 0x7C) ++#define REG_SC_BK0C_7C_H _PK_H_(0x0C, 0x7C) ++#define REG_SC_BK0C_7D_L _PK_L_(0x0C, 0x7D) ++#define REG_SC_BK0C_7D_H _PK_H_(0x0C, 0x7D) ++#define REG_SC_BK0C_7E_L _PK_L_(0x0C, 0x7E) ++#define REG_SC_BK0C_7E_H _PK_H_(0x0C, 0x7E) ++#define REG_SC_BK0C_7F_L _PK_L_(0x0C, 0x7F) ++#define REG_SC_BK0C_7F_H _PK_H_(0x0C, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0D_00_L _PK_L_(0x0D, 0x00) ++#define REG_SC_BK0D_00_H _PK_H_(0x0D, 0x00) ++#define REG_SC_BK0D_01_L _PK_L_(0x0D, 0x01) ++#define REG_SC_BK0D_01_H _PK_H_(0x0D, 0x01) ++#define REG_SC_BK0D_02_L _PK_L_(0x0D, 0x02) ++#define REG_SC_BK0D_02_H _PK_H_(0x0D, 0x02) ++#define REG_SC_BK0D_03_L _PK_L_(0x0D, 0x03) ++#define REG_SC_BK0D_03_H _PK_H_(0x0D, 0x03) ++#define REG_SC_BK0D_04_L _PK_L_(0x0D, 0x04) ++#define REG_SC_BK0D_04_H _PK_H_(0x0D, 0x04) ++#define REG_SC_BK0D_05_L _PK_L_(0x0D, 0x05) ++#define REG_SC_BK0D_05_H _PK_H_(0x0D, 0x05) ++#define REG_SC_BK0D_06_L _PK_L_(0x0D, 0x06) ++#define REG_SC_BK0D_06_H _PK_H_(0x0D, 0x06) ++#define REG_SC_BK0D_07_L _PK_L_(0x0D, 0x07) ++#define REG_SC_BK0D_07_H _PK_H_(0x0D, 0x07) ++#define REG_SC_BK0D_08_L _PK_L_(0x0D, 0x08) ++#define REG_SC_BK0D_08_H _PK_H_(0x0D, 0x08) ++#define REG_SC_BK0D_09_L _PK_L_(0x0D, 0x09) ++#define REG_SC_BK0D_09_H _PK_H_(0x0D, 0x09) ++#define REG_SC_BK0D_0A_L _PK_L_(0x0D, 0x0A) ++#define REG_SC_BK0D_0A_H _PK_H_(0x0D, 0x0A) ++#define REG_SC_BK0D_0B_L _PK_L_(0x0D, 0x0B) ++#define REG_SC_BK0D_0B_H _PK_H_(0x0D, 0x0B) ++#define REG_SC_BK0D_0C_L _PK_L_(0x0D, 0x0C) ++#define REG_SC_BK0D_0C_H _PK_H_(0x0D, 0x0C) ++#define REG_SC_BK0D_0D_L _PK_L_(0x0D, 0x0D) ++#define REG_SC_BK0D_0D_H _PK_H_(0x0D, 0x0D) ++#define REG_SC_BK0D_0E_L _PK_L_(0x0D, 0x0E) ++#define REG_SC_BK0D_0E_H _PK_H_(0x0D, 0x0E) ++#define REG_SC_BK0D_0F_L _PK_L_(0x0D, 0x0F) ++#define REG_SC_BK0D_0F_H _PK_H_(0x0D, 0x0F) ++#define REG_SC_BK0D_10_L _PK_L_(0x0D, 0x10) ++#define REG_SC_BK0D_10_H _PK_H_(0x0D, 0x10) ++#define REG_SC_BK0D_11_L _PK_L_(0x0D, 0x11) ++#define REG_SC_BK0D_11_H _PK_H_(0x0D, 0x11) ++#define REG_SC_BK0D_12_L _PK_L_(0x0D, 0x12) ++#define REG_SC_BK0D_12_H _PK_H_(0x0D, 0x12) ++#define REG_SC_BK0D_13_L _PK_L_(0x0D, 0x13) ++#define REG_SC_BK0D_13_H _PK_H_(0x0D, 0x13) ++#define REG_SC_BK0D_14_L _PK_L_(0x0D, 0x14) ++#define REG_SC_BK0D_14_H _PK_H_(0x0D, 0x14) ++#define REG_SC_BK0D_15_L _PK_L_(0x0D, 0x15) ++#define REG_SC_BK0D_15_H _PK_H_(0x0D, 0x15) ++#define REG_SC_BK0D_16_L _PK_L_(0x0D, 0x16) ++#define REG_SC_BK0D_16_H _PK_H_(0x0D, 0x16) ++#define REG_SC_BK0D_17_L _PK_L_(0x0D, 0x17) ++#define REG_SC_BK0D_17_H _PK_H_(0x0D, 0x17) ++#define REG_SC_BK0D_18_L _PK_L_(0x0D, 0x18) ++#define REG_SC_BK0D_18_H _PK_H_(0x0D, 0x18) ++#define REG_SC_BK0D_19_L _PK_L_(0x0D, 0x19) ++#define REG_SC_BK0D_19_H _PK_H_(0x0D, 0x19) ++#define REG_SC_BK0D_1A_L _PK_L_(0x0D, 0x1A) ++#define REG_SC_BK0D_1A_H _PK_H_(0x0D, 0x1A) ++#define REG_SC_BK0D_1B_L _PK_L_(0x0D, 0x1B) ++#define REG_SC_BK0D_1B_H _PK_H_(0x0D, 0x1B) ++#define REG_SC_BK0D_1C_L _PK_L_(0x0D, 0x1C) ++#define REG_SC_BK0D_1C_H _PK_H_(0x0D, 0x1C) ++#define REG_SC_BK0D_1D_L _PK_L_(0x0D, 0x1D) ++#define REG_SC_BK0D_1D_H _PK_H_(0x0D, 0x1D) ++#define REG_SC_BK0D_1E_L _PK_L_(0x0D, 0x1E) ++#define REG_SC_BK0D_1E_H _PK_H_(0x0D, 0x1E) ++#define REG_SC_BK0D_1F_L _PK_L_(0x0D, 0x1F) ++#define REG_SC_BK0D_1F_H _PK_H_(0x0D, 0x1F) ++#define REG_SC_BK0D_20_L _PK_L_(0x0D, 0x20) ++#define REG_SC_BK0D_20_H _PK_H_(0x0D, 0x20) ++#define REG_SC_BK0D_21_L _PK_L_(0x0D, 0x21) ++#define REG_SC_BK0D_21_H _PK_H_(0x0D, 0x21) ++#define REG_SC_BK0D_22_L _PK_L_(0x0D, 0x22) ++#define REG_SC_BK0D_22_H _PK_H_(0x0D, 0x22) ++#define REG_SC_BK0D_23_L _PK_L_(0x0D, 0x23) ++#define REG_SC_BK0D_23_H _PK_H_(0x0D, 0x23) ++#define REG_SC_BK0D_24_L _PK_L_(0x0D, 0x24) ++#define REG_SC_BK0D_24_H _PK_H_(0x0D, 0x24) ++#define REG_SC_BK0D_25_L _PK_L_(0x0D, 0x25) ++#define REG_SC_BK0D_25_H _PK_H_(0x0D, 0x25) ++#define REG_SC_BK0D_26_L _PK_L_(0x0D, 0x26) ++#define REG_SC_BK0D_26_H _PK_H_(0x0D, 0x26) ++#define REG_SC_BK0D_27_L _PK_L_(0x0D, 0x27) ++#define REG_SC_BK0D_27_H _PK_H_(0x0D, 0x27) ++#define REG_SC_BK0D_28_L _PK_L_(0x0D, 0x28) ++#define REG_SC_BK0D_28_H _PK_H_(0x0D, 0x28) ++#define REG_SC_BK0D_29_L _PK_L_(0x0D, 0x29) ++#define REG_SC_BK0D_29_H _PK_H_(0x0D, 0x29) ++#define REG_SC_BK0D_2A_L _PK_L_(0x0D, 0x2A) ++#define REG_SC_BK0D_2A_H _PK_H_(0x0D, 0x2A) ++#define REG_SC_BK0D_2B_L _PK_L_(0x0D, 0x2B) ++#define REG_SC_BK0D_2B_H _PK_H_(0x0D, 0x2B) ++#define REG_SC_BK0D_2C_L _PK_L_(0x0D, 0x2C) ++#define REG_SC_BK0D_2C_H _PK_H_(0x0D, 0x2C) ++#define REG_SC_BK0D_2D_L _PK_L_(0x0D, 0x2D) ++#define REG_SC_BK0D_2D_H _PK_H_(0x0D, 0x2D) ++#define REG_SC_BK0D_2E_L _PK_L_(0x0D, 0x2E) ++#define REG_SC_BK0D_2E_H _PK_H_(0x0D, 0x2E) ++#define REG_SC_BK0D_2F_L _PK_L_(0x0D, 0x2F) ++#define REG_SC_BK0D_2F_H _PK_H_(0x0D, 0x2F) ++#define REG_SC_BK0D_30_L _PK_L_(0x0D, 0x30) ++#define REG_SC_BK0D_30_H _PK_H_(0x0D, 0x30) ++#define REG_SC_BK0D_31_L _PK_L_(0x0D, 0x31) ++#define REG_SC_BK0D_31_H _PK_H_(0x0D, 0x31) ++#define REG_SC_BK0D_32_L _PK_L_(0x0D, 0x32) ++#define REG_SC_BK0D_32_H _PK_H_(0x0D, 0x32) ++#define REG_SC_BK0D_33_L _PK_L_(0x0D, 0x33) ++#define REG_SC_BK0D_33_H _PK_H_(0x0D, 0x33) ++#define REG_SC_BK0D_34_L _PK_L_(0x0D, 0x34) ++#define REG_SC_BK0D_34_H _PK_H_(0x0D, 0x34) ++#define REG_SC_BK0D_35_L _PK_L_(0x0D, 0x35) ++#define REG_SC_BK0D_35_H _PK_H_(0x0D, 0x35) ++#define REG_SC_BK0D_36_L _PK_L_(0x0D, 0x36) ++#define REG_SC_BK0D_36_H _PK_H_(0x0D, 0x36) ++#define REG_SC_BK0D_37_L _PK_L_(0x0D, 0x37) ++#define REG_SC_BK0D_37_H _PK_H_(0x0D, 0x37) ++#define REG_SC_BK0D_38_L _PK_L_(0x0D, 0x38) ++#define REG_SC_BK0D_38_H _PK_H_(0x0D, 0x38) ++#define REG_SC_BK0D_39_L _PK_L_(0x0D, 0x39) ++#define REG_SC_BK0D_39_H _PK_H_(0x0D, 0x39) ++#define REG_SC_BK0D_3A_L _PK_L_(0x0D, 0x3A) ++#define REG_SC_BK0D_3A_H _PK_H_(0x0D, 0x3A) ++#define REG_SC_BK0D_3B_L _PK_L_(0x0D, 0x3B) ++#define REG_SC_BK0D_3B_H _PK_H_(0x0D, 0x3B) ++#define REG_SC_BK0D_3C_L _PK_L_(0x0D, 0x3C) ++#define REG_SC_BK0D_3C_H _PK_H_(0x0D, 0x3C) ++#define REG_SC_BK0D_3D_L _PK_L_(0x0D, 0x3D) ++#define REG_SC_BK0D_3D_H _PK_H_(0x0D, 0x3D) ++#define REG_SC_BK0D_3E_L _PK_L_(0x0D, 0x3E) ++#define REG_SC_BK0D_3E_H _PK_H_(0x0D, 0x3E) ++#define REG_SC_BK0D_3F_L _PK_L_(0x0D, 0x3F) ++#define REG_SC_BK0D_3F_H _PK_H_(0x0D, 0x3F) ++#define REG_SC_BK0D_40_L _PK_L_(0x0D, 0x40) ++#define REG_SC_BK0D_40_H _PK_H_(0x0D, 0x40) ++#define REG_SC_BK0D_41_L _PK_L_(0x0D, 0x41) ++#define REG_SC_BK0D_41_H _PK_H_(0x0D, 0x41) ++#define REG_SC_BK0D_42_L _PK_L_(0x0D, 0x42) ++#define REG_SC_BK0D_42_H _PK_H_(0x0D, 0x42) ++#define REG_SC_BK0D_43_L _PK_L_(0x0D, 0x43) ++#define REG_SC_BK0D_43_H _PK_H_(0x0D, 0x43) ++#define REG_SC_BK0D_44_L _PK_L_(0x0D, 0x44) ++#define REG_SC_BK0D_44_H _PK_H_(0x0D, 0x44) ++#define REG_SC_BK0D_45_L _PK_L_(0x0D, 0x45) ++#define REG_SC_BK0D_45_H _PK_H_(0x0D, 0x45) ++#define REG_SC_BK0D_46_L _PK_L_(0x0D, 0x46) ++#define REG_SC_BK0D_46_H _PK_H_(0x0D, 0x46) ++#define REG_SC_BK0D_47_L _PK_L_(0x0D, 0x47) ++#define REG_SC_BK0D_47_H _PK_H_(0x0D, 0x47) ++#define REG_SC_BK0D_48_L _PK_L_(0x0D, 0x48) ++#define REG_SC_BK0D_48_H _PK_H_(0x0D, 0x48) ++#define REG_SC_BK0D_49_L _PK_L_(0x0D, 0x49) ++#define REG_SC_BK0D_49_H _PK_H_(0x0D, 0x49) ++#define REG_SC_BK0D_4A_L _PK_L_(0x0D, 0x4A) ++#define REG_SC_BK0D_4A_H _PK_H_(0x0D, 0x4A) ++#define REG_SC_BK0D_4B_L _PK_L_(0x0D, 0x4B) ++#define REG_SC_BK0D_4B_H _PK_H_(0x0D, 0x4B) ++#define REG_SC_BK0D_4C_L _PK_L_(0x0D, 0x4C) ++#define REG_SC_BK0D_4C_H _PK_H_(0x0D, 0x4C) ++#define REG_SC_BK0D_4D_L _PK_L_(0x0D, 0x4D) ++#define REG_SC_BK0D_4D_H _PK_H_(0x0D, 0x4D) ++#define REG_SC_BK0D_4E_L _PK_L_(0x0D, 0x4E) ++#define REG_SC_BK0D_4E_H _PK_H_(0x0D, 0x4E) ++#define REG_SC_BK0D_4F_L _PK_L_(0x0D, 0x4F) ++#define REG_SC_BK0D_4F_H _PK_H_(0x0D, 0x4F) ++#define REG_SC_BK0D_50_L _PK_L_(0x0D, 0x50) ++#define REG_SC_BK0D_50_H _PK_H_(0x0D, 0x50) ++#define REG_SC_BK0D_51_L _PK_L_(0x0D, 0x51) ++#define REG_SC_BK0D_51_H _PK_H_(0x0D, 0x51) ++#define REG_SC_BK0D_52_L _PK_L_(0x0D, 0x52) ++#define REG_SC_BK0D_52_H _PK_H_(0x0D, 0x52) ++#define REG_SC_BK0D_53_L _PK_L_(0x0D, 0x53) ++#define REG_SC_BK0D_53_H _PK_H_(0x0D, 0x53) ++#define REG_SC_BK0D_54_L _PK_L_(0x0D, 0x54) ++#define REG_SC_BK0D_54_H _PK_H_(0x0D, 0x54) ++#define REG_SC_BK0D_55_L _PK_L_(0x0D, 0x55) ++#define REG_SC_BK0D_55_H _PK_H_(0x0D, 0x55) ++#define REG_SC_BK0D_56_L _PK_L_(0x0D, 0x56) ++#define REG_SC_BK0D_56_H _PK_H_(0x0D, 0x56) ++#define REG_SC_BK0D_57_L _PK_L_(0x0D, 0x57) ++#define REG_SC_BK0D_57_H _PK_H_(0x0D, 0x57) ++#define REG_SC_BK0D_58_L _PK_L_(0x0D, 0x58) ++#define REG_SC_BK0D_58_H _PK_H_(0x0D, 0x58) ++#define REG_SC_BK0D_59_L _PK_L_(0x0D, 0x59) ++#define REG_SC_BK0D_59_H _PK_H_(0x0D, 0x59) ++#define REG_SC_BK0D_5A_L _PK_L_(0x0D, 0x5A) ++#define REG_SC_BK0D_5A_H _PK_H_(0x0D, 0x5A) ++#define REG_SC_BK0D_5B_L _PK_L_(0x0D, 0x5B) ++#define REG_SC_BK0D_5B_H _PK_H_(0x0D, 0x5B) ++#define REG_SC_BK0D_5C_L _PK_L_(0x0D, 0x5C) ++#define REG_SC_BK0D_5C_H _PK_H_(0x0D, 0x5C) ++#define REG_SC_BK0D_5D_L _PK_L_(0x0D, 0x5D) ++#define REG_SC_BK0D_5D_H _PK_H_(0x0D, 0x5D) ++#define REG_SC_BK0D_5E_L _PK_L_(0x0D, 0x5E) ++#define REG_SC_BK0D_5E_H _PK_H_(0x0D, 0x5E) ++#define REG_SC_BK0D_5F_L _PK_L_(0x0D, 0x5F) ++#define REG_SC_BK0D_5F_H _PK_H_(0x0D, 0x5F) ++#define REG_SC_BK0D_60_L _PK_L_(0x0D, 0x60) ++#define REG_SC_BK0D_60_H _PK_H_(0x0D, 0x60) ++#define REG_SC_BK0D_61_L _PK_L_(0x0D, 0x61) ++#define REG_SC_BK0D_61_H _PK_H_(0x0D, 0x61) ++#define REG_SC_BK0D_62_L _PK_L_(0x0D, 0x62) ++#define REG_SC_BK0D_62_H _PK_H_(0x0D, 0x62) ++#define REG_SC_BK0D_63_L _PK_L_(0x0D, 0x63) ++#define REG_SC_BK0D_63_H _PK_H_(0x0D, 0x63) ++#define REG_SC_BK0D_64_L _PK_L_(0x0D, 0x64) ++#define REG_SC_BK0D_64_H _PK_H_(0x0D, 0x64) ++#define REG_SC_BK0D_65_L _PK_L_(0x0D, 0x65) ++#define REG_SC_BK0D_65_H _PK_H_(0x0D, 0x65) ++#define REG_SC_BK0D_66_L _PK_L_(0x0D, 0x66) ++#define REG_SC_BK0D_66_H _PK_H_(0x0D, 0x66) ++#define REG_SC_BK0D_67_L _PK_L_(0x0D, 0x67) ++#define REG_SC_BK0D_67_H _PK_H_(0x0D, 0x67) ++#define REG_SC_BK0D_68_L _PK_L_(0x0D, 0x68) ++#define REG_SC_BK0D_68_H _PK_H_(0x0D, 0x68) ++#define REG_SC_BK0D_69_L _PK_L_(0x0D, 0x69) ++#define REG_SC_BK0D_69_H _PK_H_(0x0D, 0x69) ++#define REG_SC_BK0D_6A_L _PK_L_(0x0D, 0x6A) ++#define REG_SC_BK0D_6A_H _PK_H_(0x0D, 0x6A) ++#define REG_SC_BK0D_6B_L _PK_L_(0x0D, 0x6B) ++#define REG_SC_BK0D_6B_H _PK_H_(0x0D, 0x6B) ++#define REG_SC_BK0D_6C_L _PK_L_(0x0D, 0x6C) ++#define REG_SC_BK0D_6C_H _PK_H_(0x0D, 0x6C) ++#define REG_SC_BK0D_6D_L _PK_L_(0x0D, 0x6D) ++#define REG_SC_BK0D_6D_H _PK_H_(0x0D, 0x6D) ++#define REG_SC_BK0D_6E_L _PK_L_(0x0D, 0x6E) ++#define REG_SC_BK0D_6E_H _PK_H_(0x0D, 0x6E) ++#define REG_SC_BK0D_6F_L _PK_L_(0x0D, 0x6F) ++#define REG_SC_BK0D_6F_H _PK_H_(0x0D, 0x6F) ++#define REG_SC_BK0D_70_L _PK_L_(0x0D, 0x70) ++#define REG_SC_BK0D_70_H _PK_H_(0x0D, 0x70) ++#define REG_SC_BK0D_71_L _PK_L_(0x0D, 0x71) ++#define REG_SC_BK0D_71_H _PK_H_(0x0D, 0x71) ++#define REG_SC_BK0D_72_L _PK_L_(0x0D, 0x72) ++#define REG_SC_BK0D_72_H _PK_H_(0x0D, 0x72) ++#define REG_SC_BK0D_73_L _PK_L_(0x0D, 0x73) ++#define REG_SC_BK0D_73_H _PK_H_(0x0D, 0x73) ++#define REG_SC_BK0D_74_L _PK_L_(0x0D, 0x74) ++#define REG_SC_BK0D_74_H _PK_H_(0x0D, 0x74) ++#define REG_SC_BK0D_75_L _PK_L_(0x0D, 0x75) ++#define REG_SC_BK0D_75_H _PK_H_(0x0D, 0x75) ++#define REG_SC_BK0D_76_L _PK_L_(0x0D, 0x76) ++#define REG_SC_BK0D_76_H _PK_H_(0x0D, 0x76) ++#define REG_SC_BK0D_77_L _PK_L_(0x0D, 0x77) ++#define REG_SC_BK0D_77_H _PK_H_(0x0D, 0x77) ++#define REG_SC_BK0D_78_L _PK_L_(0x0D, 0x78) ++#define REG_SC_BK0D_78_H _PK_H_(0x0D, 0x78) ++#define REG_SC_BK0D_79_L _PK_L_(0x0D, 0x79) ++#define REG_SC_BK0D_79_H _PK_H_(0x0D, 0x79) ++#define REG_SC_BK0D_7A_L _PK_L_(0x0D, 0x7A) ++#define REG_SC_BK0D_7A_H _PK_H_(0x0D, 0x7A) ++#define REG_SC_BK0D_7B_L _PK_L_(0x0D, 0x7B) ++#define REG_SC_BK0D_7B_H _PK_H_(0x0D, 0x7B) ++#define REG_SC_BK0D_7C_L _PK_L_(0x0D, 0x7C) ++#define REG_SC_BK0D_7C_H _PK_H_(0x0D, 0x7C) ++#define REG_SC_BK0D_7D_L _PK_L_(0x0D, 0x7D) ++#define REG_SC_BK0D_7D_H _PK_H_(0x0D, 0x7D) ++#define REG_SC_BK0D_7E_L _PK_L_(0x0D, 0x7E) ++#define REG_SC_BK0D_7E_H _PK_H_(0x0D, 0x7E) ++#define REG_SC_BK0D_7F_L _PK_L_(0x0D, 0x7F) ++#define REG_SC_BK0D_7F_H _PK_H_(0x0D, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0E_00_L _PK_L_(0x0E, 0x00) ++#define REG_SC_BK0E_00_H _PK_H_(0x0E, 0x00) ++#define REG_SC_BK0E_01_L _PK_L_(0x0E, 0x01) ++#define REG_SC_BK0E_01_H _PK_H_(0x0E, 0x01) ++#define REG_SC_BK0E_02_L _PK_L_(0x0E, 0x02) ++#define REG_SC_BK0E_02_H _PK_H_(0x0E, 0x02) ++#define REG_SC_BK0E_03_L _PK_L_(0x0E, 0x03) ++#define REG_SC_BK0E_03_H _PK_H_(0x0E, 0x03) ++#define REG_SC_BK0E_04_L _PK_L_(0x0E, 0x04) ++#define REG_SC_BK0E_04_H _PK_H_(0x0E, 0x04) ++#define REG_SC_BK0E_05_L _PK_L_(0x0E, 0x05) ++#define REG_SC_BK0E_05_H _PK_H_(0x0E, 0x05) ++#define REG_SC_BK0E_06_L _PK_L_(0x0E, 0x06) ++#define REG_SC_BK0E_06_H _PK_H_(0x0E, 0x06) ++#define REG_SC_BK0E_07_L _PK_L_(0x0E, 0x07) ++#define REG_SC_BK0E_07_H _PK_H_(0x0E, 0x07) ++#define REG_SC_BK0E_08_L _PK_L_(0x0E, 0x08) ++#define REG_SC_BK0E_08_H _PK_H_(0x0E, 0x08) ++#define REG_SC_BK0E_09_L _PK_L_(0x0E, 0x09) ++#define REG_SC_BK0E_09_H _PK_H_(0x0E, 0x09) ++#define REG_SC_BK0E_0A_L _PK_L_(0x0E, 0x0A) ++#define REG_SC_BK0E_0A_H _PK_H_(0x0E, 0x0A) ++#define REG_SC_BK0E_0B_L _PK_L_(0x0E, 0x0B) ++#define REG_SC_BK0E_0B_H _PK_H_(0x0E, 0x0B) ++#define REG_SC_BK0E_0C_L _PK_L_(0x0E, 0x0C) ++#define REG_SC_BK0E_0C_H _PK_H_(0x0E, 0x0C) ++#define REG_SC_BK0E_0D_L _PK_L_(0x0E, 0x0D) ++#define REG_SC_BK0E_0D_H _PK_H_(0x0E, 0x0D) ++#define REG_SC_BK0E_0E_L _PK_L_(0x0E, 0x0E) ++#define REG_SC_BK0E_0E_H _PK_H_(0x0E, 0x0E) ++#define REG_SC_BK0E_0F_L _PK_L_(0x0E, 0x0F) ++#define REG_SC_BK0E_0F_H _PK_H_(0x0E, 0x0F) ++#define REG_SC_BK0E_10_L _PK_L_(0x0E, 0x10) ++#define REG_SC_BK0E_10_H _PK_H_(0x0E, 0x10) ++#define REG_SC_BK0E_11_L _PK_L_(0x0E, 0x11) ++#define REG_SC_BK0E_11_H _PK_H_(0x0E, 0x11) ++#define REG_SC_BK0E_12_L _PK_L_(0x0E, 0x12) ++#define REG_SC_BK0E_12_H _PK_H_(0x0E, 0x12) ++#define REG_SC_BK0E_13_L _PK_L_(0x0E, 0x13) ++#define REG_SC_BK0E_13_H _PK_H_(0x0E, 0x13) ++#define REG_SC_BK0E_14_L _PK_L_(0x0E, 0x14) ++#define REG_SC_BK0E_14_H _PK_H_(0x0E, 0x14) ++#define REG_SC_BK0E_15_L _PK_L_(0x0E, 0x15) ++#define REG_SC_BK0E_15_H _PK_H_(0x0E, 0x15) ++#define REG_SC_BK0E_16_L _PK_L_(0x0E, 0x16) ++#define REG_SC_BK0E_16_H _PK_H_(0x0E, 0x16) ++#define REG_SC_BK0E_17_L _PK_L_(0x0E, 0x17) ++#define REG_SC_BK0E_17_H _PK_H_(0x0E, 0x17) ++#define REG_SC_BK0E_18_L _PK_L_(0x0E, 0x18) ++#define REG_SC_BK0E_18_H _PK_H_(0x0E, 0x18) ++#define REG_SC_BK0E_19_L _PK_L_(0x0E, 0x19) ++#define REG_SC_BK0E_19_H _PK_H_(0x0E, 0x19) ++#define REG_SC_BK0E_1A_L _PK_L_(0x0E, 0x1A) ++#define REG_SC_BK0E_1A_H _PK_H_(0x0E, 0x1A) ++#define REG_SC_BK0E_1B_L _PK_L_(0x0E, 0x1B) ++#define REG_SC_BK0E_1B_H _PK_H_(0x0E, 0x1B) ++#define REG_SC_BK0E_1C_L _PK_L_(0x0E, 0x1C) ++#define REG_SC_BK0E_1C_H _PK_H_(0x0E, 0x1C) ++#define REG_SC_BK0E_1D_L _PK_L_(0x0E, 0x1D) ++#define REG_SC_BK0E_1D_H _PK_H_(0x0E, 0x1D) ++#define REG_SC_BK0E_1E_L _PK_L_(0x0E, 0x1E) ++#define REG_SC_BK0E_1E_H _PK_H_(0x0E, 0x1E) ++#define REG_SC_BK0E_1F_L _PK_L_(0x0E, 0x1F) ++#define REG_SC_BK0E_1F_H _PK_H_(0x0E, 0x1F) ++#define REG_SC_BK0E_20_L _PK_L_(0x0E, 0x20) ++#define REG_SC_BK0E_20_H _PK_H_(0x0E, 0x20) ++#define REG_SC_BK0E_21_L _PK_L_(0x0E, 0x21) ++#define REG_SC_BK0E_21_H _PK_H_(0x0E, 0x21) ++#define REG_SC_BK0E_22_L _PK_L_(0x0E, 0x22) ++#define REG_SC_BK0E_22_H _PK_H_(0x0E, 0x22) ++#define REG_SC_BK0E_23_L _PK_L_(0x0E, 0x23) ++#define REG_SC_BK0E_23_H _PK_H_(0x0E, 0x23) ++#define REG_SC_BK0E_24_L _PK_L_(0x0E, 0x24) ++#define REG_SC_BK0E_24_H _PK_H_(0x0E, 0x24) ++#define REG_SC_BK0E_25_L _PK_L_(0x0E, 0x25) ++#define REG_SC_BK0E_25_H _PK_H_(0x0E, 0x25) ++#define REG_SC_BK0E_26_L _PK_L_(0x0E, 0x26) ++#define REG_SC_BK0E_26_H _PK_H_(0x0E, 0x26) ++#define REG_SC_BK0E_27_L _PK_L_(0x0E, 0x27) ++#define REG_SC_BK0E_27_H _PK_H_(0x0E, 0x27) ++#define REG_SC_BK0E_28_L _PK_L_(0x0E, 0x28) ++#define REG_SC_BK0E_28_H _PK_H_(0x0E, 0x28) ++#define REG_SC_BK0E_29_L _PK_L_(0x0E, 0x29) ++#define REG_SC_BK0E_29_H _PK_H_(0x0E, 0x29) ++#define REG_SC_BK0E_2A_L _PK_L_(0x0E, 0x2A) ++#define REG_SC_BK0E_2A_H _PK_H_(0x0E, 0x2A) ++#define REG_SC_BK0E_2B_L _PK_L_(0x0E, 0x2B) ++#define REG_SC_BK0E_2B_H _PK_H_(0x0E, 0x2B) ++#define REG_SC_BK0E_2C_L _PK_L_(0x0E, 0x2C) ++#define REG_SC_BK0E_2C_H _PK_H_(0x0E, 0x2C) ++#define REG_SC_BK0E_2D_L _PK_L_(0x0E, 0x2D) ++#define REG_SC_BK0E_2D_H _PK_H_(0x0E, 0x2D) ++#define REG_SC_BK0E_2E_L _PK_L_(0x0E, 0x2E) ++#define REG_SC_BK0E_2E_H _PK_H_(0x0E, 0x2E) ++#define REG_SC_BK0E_2F_L _PK_L_(0x0E, 0x2F) ++#define REG_SC_BK0E_2F_H _PK_H_(0x0E, 0x2F) ++#define REG_SC_BK0E_30_L _PK_L_(0x0E, 0x30) ++#define REG_SC_BK0E_30_H _PK_H_(0x0E, 0x30) ++#define REG_SC_BK0E_31_L _PK_L_(0x0E, 0x31) ++#define REG_SC_BK0E_31_H _PK_H_(0x0E, 0x31) ++#define REG_SC_BK0E_32_L _PK_L_(0x0E, 0x32) ++#define REG_SC_BK0E_32_H _PK_H_(0x0E, 0x32) ++#define REG_SC_BK0E_33_L _PK_L_(0x0E, 0x33) ++#define REG_SC_BK0E_33_H _PK_H_(0x0E, 0x33) ++#define REG_SC_BK0E_34_L _PK_L_(0x0E, 0x34) ++#define REG_SC_BK0E_34_H _PK_H_(0x0E, 0x34) ++#define REG_SC_BK0E_35_L _PK_L_(0x0E, 0x35) ++#define REG_SC_BK0E_35_H _PK_H_(0x0E, 0x35) ++#define REG_SC_BK0E_36_L _PK_L_(0x0E, 0x36) ++#define REG_SC_BK0E_36_H _PK_H_(0x0E, 0x36) ++#define REG_SC_BK0E_37_L _PK_L_(0x0E, 0x37) ++#define REG_SC_BK0E_37_H _PK_H_(0x0E, 0x37) ++#define REG_SC_BK0E_38_L _PK_L_(0x0E, 0x38) ++#define REG_SC_BK0E_38_H _PK_H_(0x0E, 0x38) ++#define REG_SC_BK0E_39_L _PK_L_(0x0E, 0x39) ++#define REG_SC_BK0E_39_H _PK_H_(0x0E, 0x39) ++#define REG_SC_BK0E_3A_L _PK_L_(0x0E, 0x3A) ++#define REG_SC_BK0E_3A_H _PK_H_(0x0E, 0x3A) ++#define REG_SC_BK0E_3B_L _PK_L_(0x0E, 0x3B) ++#define REG_SC_BK0E_3B_H _PK_H_(0x0E, 0x3B) ++#define REG_SC_BK0E_3C_L _PK_L_(0x0E, 0x3C) ++#define REG_SC_BK0E_3C_H _PK_H_(0x0E, 0x3C) ++#define REG_SC_BK0E_3D_L _PK_L_(0x0E, 0x3D) ++#define REG_SC_BK0E_3D_H _PK_H_(0x0E, 0x3D) ++#define REG_SC_BK0E_3E_L _PK_L_(0x0E, 0x3E) ++#define REG_SC_BK0E_3E_H _PK_H_(0x0E, 0x3E) ++#define REG_SC_BK0E_3F_L _PK_L_(0x0E, 0x3F) ++#define REG_SC_BK0E_3F_H _PK_H_(0x0E, 0x3F) ++#define REG_SC_BK0E_40_L _PK_L_(0x0E, 0x40) ++#define REG_SC_BK0E_40_H _PK_H_(0x0E, 0x40) ++#define REG_SC_BK0E_41_L _PK_L_(0x0E, 0x41) ++#define REG_SC_BK0E_41_H _PK_H_(0x0E, 0x41) ++#define REG_SC_BK0E_42_L _PK_L_(0x0E, 0x42) ++#define REG_SC_BK0E_42_H _PK_H_(0x0E, 0x42) ++#define REG_SC_BK0E_43_L _PK_L_(0x0E, 0x43) ++#define REG_SC_BK0E_43_H _PK_H_(0x0E, 0x43) ++#define REG_SC_BK0E_44_L _PK_L_(0x0E, 0x44) ++#define REG_SC_BK0E_44_H _PK_H_(0x0E, 0x44) ++#define REG_SC_BK0E_45_L _PK_L_(0x0E, 0x45) ++#define REG_SC_BK0E_45_H _PK_H_(0x0E, 0x45) ++#define REG_SC_BK0E_46_L _PK_L_(0x0E, 0x46) ++#define REG_SC_BK0E_46_H _PK_H_(0x0E, 0x46) ++#define REG_SC_BK0E_47_L _PK_L_(0x0E, 0x47) ++#define REG_SC_BK0E_47_H _PK_H_(0x0E, 0x47) ++#define REG_SC_BK0E_48_L _PK_L_(0x0E, 0x48) ++#define REG_SC_BK0E_48_H _PK_H_(0x0E, 0x48) ++#define REG_SC_BK0E_49_L _PK_L_(0x0E, 0x49) ++#define REG_SC_BK0E_49_H _PK_H_(0x0E, 0x49) ++#define REG_SC_BK0E_4A_L _PK_L_(0x0E, 0x4A) ++#define REG_SC_BK0E_4A_H _PK_H_(0x0E, 0x4A) ++#define REG_SC_BK0E_4B_L _PK_L_(0x0E, 0x4B) ++#define REG_SC_BK0E_4B_H _PK_H_(0x0E, 0x4B) ++#define REG_SC_BK0E_4C_L _PK_L_(0x0E, 0x4C) ++#define REG_SC_BK0E_4C_H _PK_H_(0x0E, 0x4C) ++#define REG_SC_BK0E_4D_L _PK_L_(0x0E, 0x4D) ++#define REG_SC_BK0E_4D_H _PK_H_(0x0E, 0x4D) ++#define REG_SC_BK0E_4E_L _PK_L_(0x0E, 0x4E) ++#define REG_SC_BK0E_4E_H _PK_H_(0x0E, 0x4E) ++#define REG_SC_BK0E_4F_L _PK_L_(0x0E, 0x4F) ++#define REG_SC_BK0E_4F_H _PK_H_(0x0E, 0x4F) ++#define REG_SC_BK0E_50_L _PK_L_(0x0E, 0x50) ++#define REG_SC_BK0E_50_H _PK_H_(0x0E, 0x50) ++#define REG_SC_BK0E_51_L _PK_L_(0x0E, 0x51) ++#define REG_SC_BK0E_51_H _PK_H_(0x0E, 0x51) ++#define REG_SC_BK0E_52_L _PK_L_(0x0E, 0x52) ++#define REG_SC_BK0E_52_H _PK_H_(0x0E, 0x52) ++#define REG_SC_BK0E_53_L _PK_L_(0x0E, 0x53) ++#define REG_SC_BK0E_53_H _PK_H_(0x0E, 0x53) ++#define REG_SC_BK0E_54_L _PK_L_(0x0E, 0x54) ++#define REG_SC_BK0E_54_H _PK_H_(0x0E, 0x54) ++#define REG_SC_BK0E_55_L _PK_L_(0x0E, 0x55) ++#define REG_SC_BK0E_55_H _PK_H_(0x0E, 0x55) ++#define REG_SC_BK0E_56_L _PK_L_(0x0E, 0x56) ++#define REG_SC_BK0E_56_H _PK_H_(0x0E, 0x56) ++#define REG_SC_BK0E_57_L _PK_L_(0x0E, 0x57) ++#define REG_SC_BK0E_57_H _PK_H_(0x0E, 0x57) ++#define REG_SC_BK0E_58_L _PK_L_(0x0E, 0x58) ++#define REG_SC_BK0E_58_H _PK_H_(0x0E, 0x58) ++#define REG_SC_BK0E_59_L _PK_L_(0x0E, 0x59) ++#define REG_SC_BK0E_59_H _PK_H_(0x0E, 0x59) ++#define REG_SC_BK0E_5A_L _PK_L_(0x0E, 0x5A) ++#define REG_SC_BK0E_5A_H _PK_H_(0x0E, 0x5A) ++#define REG_SC_BK0E_5B_L _PK_L_(0x0E, 0x5B) ++#define REG_SC_BK0E_5B_H _PK_H_(0x0E, 0x5B) ++#define REG_SC_BK0E_5C_L _PK_L_(0x0E, 0x5C) ++#define REG_SC_BK0E_5C_H _PK_H_(0x0E, 0x5C) ++#define REG_SC_BK0E_5D_L _PK_L_(0x0E, 0x5D) ++#define REG_SC_BK0E_5D_H _PK_H_(0x0E, 0x5D) ++#define REG_SC_BK0E_5E_L _PK_L_(0x0E, 0x5E) ++#define REG_SC_BK0E_5E_H _PK_H_(0x0E, 0x5E) ++#define REG_SC_BK0E_5F_L _PK_L_(0x0E, 0x5F) ++#define REG_SC_BK0E_5F_H _PK_H_(0x0E, 0x5F) ++#define REG_SC_BK0E_60_L _PK_L_(0x0E, 0x60) ++#define REG_SC_BK0E_60_H _PK_H_(0x0E, 0x60) ++#define REG_SC_BK0E_61_L _PK_L_(0x0E, 0x61) ++#define REG_SC_BK0E_61_H _PK_H_(0x0E, 0x61) ++#define REG_SC_BK0E_62_L _PK_L_(0x0E, 0x62) ++#define REG_SC_BK0E_62_H _PK_H_(0x0E, 0x62) ++#define REG_SC_BK0E_63_L _PK_L_(0x0E, 0x63) ++#define REG_SC_BK0E_63_H _PK_H_(0x0E, 0x63) ++#define REG_SC_BK0E_64_L _PK_L_(0x0E, 0x64) ++#define REG_SC_BK0E_64_H _PK_H_(0x0E, 0x64) ++#define REG_SC_BK0E_65_L _PK_L_(0x0E, 0x65) ++#define REG_SC_BK0E_65_H _PK_H_(0x0E, 0x65) ++#define REG_SC_BK0E_66_L _PK_L_(0x0E, 0x66) ++#define REG_SC_BK0E_66_H _PK_H_(0x0E, 0x66) ++#define REG_SC_BK0E_67_L _PK_L_(0x0E, 0x67) ++#define REG_SC_BK0E_67_H _PK_H_(0x0E, 0x67) ++#define REG_SC_BK0E_68_L _PK_L_(0x0E, 0x68) ++#define REG_SC_BK0E_68_H _PK_H_(0x0E, 0x68) ++#define REG_SC_BK0E_69_L _PK_L_(0x0E, 0x69) ++#define REG_SC_BK0E_69_H _PK_H_(0x0E, 0x69) ++#define REG_SC_BK0E_6A_L _PK_L_(0x0E, 0x6A) ++#define REG_SC_BK0E_6A_H _PK_H_(0x0E, 0x6A) ++#define REG_SC_BK0E_6B_L _PK_L_(0x0E, 0x6B) ++#define REG_SC_BK0E_6B_H _PK_H_(0x0E, 0x6B) ++#define REG_SC_BK0E_6C_L _PK_L_(0x0E, 0x6C) ++#define REG_SC_BK0E_6C_H _PK_H_(0x0E, 0x6C) ++#define REG_SC_BK0E_6D_L _PK_L_(0x0E, 0x6D) ++#define REG_SC_BK0E_6D_H _PK_H_(0x0E, 0x6D) ++#define REG_SC_BK0E_6E_L _PK_L_(0x0E, 0x6E) ++#define REG_SC_BK0E_6E_H _PK_H_(0x0E, 0x6E) ++#define REG_SC_BK0E_6F_L _PK_L_(0x0E, 0x6F) ++#define REG_SC_BK0E_6F_H _PK_H_(0x0E, 0x6F) ++#define REG_SC_BK0E_70_L _PK_L_(0x0E, 0x70) ++#define REG_SC_BK0E_70_H _PK_H_(0x0E, 0x70) ++#define REG_SC_BK0E_71_L _PK_L_(0x0E, 0x71) ++#define REG_SC_BK0E_71_H _PK_H_(0x0E, 0x71) ++#define REG_SC_BK0E_72_L _PK_L_(0x0E, 0x72) ++#define REG_SC_BK0E_72_H _PK_H_(0x0E, 0x72) ++#define REG_SC_BK0E_73_L _PK_L_(0x0E, 0x73) ++#define REG_SC_BK0E_73_H _PK_H_(0x0E, 0x73) ++#define REG_SC_BK0E_74_L _PK_L_(0x0E, 0x74) ++#define REG_SC_BK0E_74_H _PK_H_(0x0E, 0x74) ++#define REG_SC_BK0E_75_L _PK_L_(0x0E, 0x75) ++#define REG_SC_BK0E_75_H _PK_H_(0x0E, 0x75) ++#define REG_SC_BK0E_76_L _PK_L_(0x0E, 0x76) ++#define REG_SC_BK0E_76_H _PK_H_(0x0E, 0x76) ++#define REG_SC_BK0E_77_L _PK_L_(0x0E, 0x77) ++#define REG_SC_BK0E_77_H _PK_H_(0x0E, 0x77) ++#define REG_SC_BK0E_78_L _PK_L_(0x0E, 0x78) ++#define REG_SC_BK0E_78_H _PK_H_(0x0E, 0x78) ++#define REG_SC_BK0E_79_L _PK_L_(0x0E, 0x79) ++#define REG_SC_BK0E_79_H _PK_H_(0x0E, 0x79) ++#define REG_SC_BK0E_7A_L _PK_L_(0x0E, 0x7A) ++#define REG_SC_BK0E_7A_H _PK_H_(0x0E, 0x7A) ++#define REG_SC_BK0E_7B_L _PK_L_(0x0E, 0x7B) ++#define REG_SC_BK0E_7B_H _PK_H_(0x0E, 0x7B) ++#define REG_SC_BK0E_7C_L _PK_L_(0x0E, 0x7C) ++#define REG_SC_BK0E_7C_H _PK_H_(0x0E, 0x7C) ++#define REG_SC_BK0E_7D_L _PK_L_(0x0E, 0x7D) ++#define REG_SC_BK0E_7D_H _PK_H_(0x0E, 0x7D) ++#define REG_SC_BK0E_7E_L _PK_L_(0x0E, 0x7E) ++#define REG_SC_BK0E_7E_H _PK_H_(0x0E, 0x7E) ++#define REG_SC_BK0E_7F_L _PK_L_(0x0E, 0x7F) ++#define REG_SC_BK0E_7F_H _PK_H_(0x0E, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0F_00_L _PK_L_(0x0F, 0x00) ++#define REG_SC_BK0F_00_H _PK_H_(0x0F, 0x00) ++#define REG_SC_BK0F_01_L _PK_L_(0x0F, 0x01) ++#define REG_SC_BK0F_01_H _PK_H_(0x0F, 0x01) ++#define REG_SC_BK0F_02_L _PK_L_(0x0F, 0x02) ++#define REG_SC_BK0F_02_H _PK_H_(0x0F, 0x02) ++#define REG_SC_BK0F_03_L _PK_L_(0x0F, 0x03) ++#define REG_SC_BK0F_03_H _PK_H_(0x0F, 0x03) ++#define REG_SC_BK0F_04_L _PK_L_(0x0F, 0x04) ++#define REG_SC_BK0F_04_H _PK_H_(0x0F, 0x04) ++#define REG_SC_BK0F_05_L _PK_L_(0x0F, 0x05) ++#define REG_SC_BK0F_05_H _PK_H_(0x0F, 0x05) ++#define REG_SC_BK0F_06_L _PK_L_(0x0F, 0x06) ++#define REG_SC_BK0F_06_H _PK_H_(0x0F, 0x06) ++#define REG_SC_BK0F_07_L _PK_L_(0x0F, 0x07) ++#define REG_SC_BK0F_07_H _PK_H_(0x0F, 0x07) ++#define REG_SC_BK0F_08_L _PK_L_(0x0F, 0x08) ++#define REG_SC_BK0F_08_H _PK_H_(0x0F, 0x08) ++#define REG_SC_BK0F_09_L _PK_L_(0x0F, 0x09) ++#define REG_SC_BK0F_09_H _PK_H_(0x0F, 0x09) ++#define REG_SC_BK0F_0A_L _PK_L_(0x0F, 0x0A) ++#define REG_SC_BK0F_0A_H _PK_H_(0x0F, 0x0A) ++#define REG_SC_BK0F_0B_L _PK_L_(0x0F, 0x0B) ++#define REG_SC_BK0F_0B_H _PK_H_(0x0F, 0x0B) ++#define REG_SC_BK0F_0C_L _PK_L_(0x0F, 0x0C) ++#define REG_SC_BK0F_0C_H _PK_H_(0x0F, 0x0C) ++#define REG_SC_BK0F_0D_L _PK_L_(0x0F, 0x0D) ++#define REG_SC_BK0F_0D_H _PK_H_(0x0F, 0x0D) ++#define REG_SC_BK0F_0E_L _PK_L_(0x0F, 0x0E) ++#define REG_SC_BK0F_0E_H _PK_H_(0x0F, 0x0E) ++#define REG_SC_BK0F_0F_L _PK_L_(0x0F, 0x0F) ++#define REG_SC_BK0F_0F_H _PK_H_(0x0F, 0x0F) ++#define REG_SC_BK0F_10_L _PK_L_(0x0F, 0x10) ++#define REG_SC_BK0F_10_H _PK_H_(0x0F, 0x10) ++#define REG_SC_BK0F_11_L _PK_L_(0x0F, 0x11) ++#define REG_SC_BK0F_11_H _PK_H_(0x0F, 0x11) ++#define REG_SC_BK0F_12_L _PK_L_(0x0F, 0x12) ++#define REG_SC_BK0F_12_H _PK_H_(0x0F, 0x12) ++#define REG_SC_BK0F_13_L _PK_L_(0x0F, 0x13) ++#define REG_SC_BK0F_13_H _PK_H_(0x0F, 0x13) ++#define REG_SC_BK0F_14_L _PK_L_(0x0F, 0x14) ++#define REG_SC_BK0F_14_H _PK_H_(0x0F, 0x14) ++#define REG_SC_BK0F_15_L _PK_L_(0x0F, 0x15) ++#define REG_SC_BK0F_15_H _PK_H_(0x0F, 0x15) ++#define REG_SC_BK0F_16_L _PK_L_(0x0F, 0x16) ++#define REG_SC_BK0F_16_H _PK_H_(0x0F, 0x16) ++#define REG_SC_BK0F_17_L _PK_L_(0x0F, 0x17) ++#define REG_SC_BK0F_17_H _PK_H_(0x0F, 0x17) ++#define REG_SC_BK0F_18_L _PK_L_(0x0F, 0x18) ++#define REG_SC_BK0F_18_H _PK_H_(0x0F, 0x18) ++#define REG_SC_BK0F_19_L _PK_L_(0x0F, 0x19) ++#define REG_SC_BK0F_19_H _PK_H_(0x0F, 0x19) ++#define REG_SC_BK0F_1A_L _PK_L_(0x0F, 0x1A) ++#define REG_SC_BK0F_1A_H _PK_H_(0x0F, 0x1A) ++#define REG_SC_BK0F_1B_L _PK_L_(0x0F, 0x1B) ++#define REG_SC_BK0F_1B_H _PK_H_(0x0F, 0x1B) ++#define REG_SC_BK0F_1C_L _PK_L_(0x0F, 0x1C) ++#define REG_SC_BK0F_1C_H _PK_H_(0x0F, 0x1C) ++#define REG_SC_BK0F_1D_L _PK_L_(0x0F, 0x1D) ++#define REG_SC_BK0F_1D_H _PK_H_(0x0F, 0x1D) ++#define REG_SC_BK0F_1E_L _PK_L_(0x0F, 0x1E) ++#define REG_SC_BK0F_1E_H _PK_H_(0x0F, 0x1E) ++#define REG_SC_BK0F_1F_L _PK_L_(0x0F, 0x1F) ++#define REG_SC_BK0F_1F_H _PK_H_(0x0F, 0x1F) ++#define REG_SC_BK0F_20_L _PK_L_(0x0F, 0x20) ++#define REG_SC_BK0F_20_H _PK_H_(0x0F, 0x20) ++#define REG_SC_BK0F_21_L _PK_L_(0x0F, 0x21) ++#define REG_SC_BK0F_21_H _PK_H_(0x0F, 0x21) ++#define REG_SC_BK0F_22_L _PK_L_(0x0F, 0x22) ++#define REG_SC_BK0F_22_H _PK_H_(0x0F, 0x22) ++#define REG_SC_BK0F_23_L _PK_L_(0x0F, 0x23) ++#define REG_SC_BK0F_23_H _PK_H_(0x0F, 0x23) ++#define REG_SC_BK0F_24_L _PK_L_(0x0F, 0x24) ++#define REG_SC_BK0F_24_H _PK_H_(0x0F, 0x24) ++#define REG_SC_BK0F_25_L _PK_L_(0x0F, 0x25) ++#define REG_SC_BK0F_25_H _PK_H_(0x0F, 0x25) ++#define REG_SC_BK0F_26_L _PK_L_(0x0F, 0x26) ++#define REG_SC_BK0F_26_H _PK_H_(0x0F, 0x26) ++#define REG_SC_BK0F_27_L _PK_L_(0x0F, 0x27) ++#define REG_SC_BK0F_27_H _PK_H_(0x0F, 0x27) ++#define REG_SC_BK0F_28_L _PK_L_(0x0F, 0x28) ++#define REG_SC_BK0F_28_H _PK_H_(0x0F, 0x28) ++#define REG_SC_BK0F_29_L _PK_L_(0x0F, 0x29) ++#define REG_SC_BK0F_29_H _PK_H_(0x0F, 0x29) ++#define REG_SC_BK0F_2A_L _PK_L_(0x0F, 0x2A) ++#define REG_SC_BK0F_2A_H _PK_H_(0x0F, 0x2A) ++#define REG_SC_BK0F_2B_L _PK_L_(0x0F, 0x2B) ++#define REG_SC_BK0F_2B_H _PK_H_(0x0F, 0x2B) ++#define REG_SC_BK0F_2C_L _PK_L_(0x0F, 0x2C) ++#define REG_SC_BK0F_2C_H _PK_H_(0x0F, 0x2C) ++#define REG_SC_BK0F_2D_L _PK_L_(0x0F, 0x2D) ++#define REG_SC_BK0F_2D_H _PK_H_(0x0F, 0x2D) ++#define REG_SC_BK0F_2E_L _PK_L_(0x0F, 0x2E) ++#define REG_SC_BK0F_2E_H _PK_H_(0x0F, 0x2E) ++#define REG_SC_BK0F_2F_L _PK_L_(0x0F, 0x2F) ++#define REG_SC_BK0F_2F_H _PK_H_(0x0F, 0x2F) ++#define REG_SC_BK0F_30_L _PK_L_(0x0F, 0x30) ++#define REG_SC_BK0F_30_H _PK_H_(0x0F, 0x30) ++#define REG_SC_BK0F_31_L _PK_L_(0x0F, 0x31) ++#define REG_SC_BK0F_31_H _PK_H_(0x0F, 0x31) ++#define REG_SC_BK0F_32_L _PK_L_(0x0F, 0x32) ++#define REG_SC_BK0F_32_H _PK_H_(0x0F, 0x32) ++#define REG_SC_BK0F_33_L _PK_L_(0x0F, 0x33) ++#define REG_SC_BK0F_33_H _PK_H_(0x0F, 0x33) ++#define REG_SC_BK0F_34_L _PK_L_(0x0F, 0x34) ++#define REG_SC_BK0F_34_H _PK_H_(0x0F, 0x34) ++#define REG_SC_BK0F_35_L _PK_L_(0x0F, 0x35) ++#define REG_SC_BK0F_35_H _PK_H_(0x0F, 0x35) ++#define REG_SC_BK0F_36_L _PK_L_(0x0F, 0x36) ++#define REG_SC_BK0F_36_H _PK_H_(0x0F, 0x36) ++#define REG_SC_BK0F_37_L _PK_L_(0x0F, 0x37) ++#define REG_SC_BK0F_37_H _PK_H_(0x0F, 0x37) ++#define REG_SC_BK0F_38_L _PK_L_(0x0F, 0x38) ++#define REG_SC_BK0F_38_H _PK_H_(0x0F, 0x38) ++#define REG_SC_BK0F_39_L _PK_L_(0x0F, 0x39) ++#define REG_SC_BK0F_39_H _PK_H_(0x0F, 0x39) ++#define REG_SC_BK0F_3A_L _PK_L_(0x0F, 0x3A) ++#define REG_SC_BK0F_3A_H _PK_H_(0x0F, 0x3A) ++#define REG_SC_BK0F_3B_L _PK_L_(0x0F, 0x3B) ++#define REG_SC_BK0F_3B_H _PK_H_(0x0F, 0x3B) ++#define REG_SC_BK0F_3C_L _PK_L_(0x0F, 0x3C) ++#define REG_SC_BK0F_3C_H _PK_H_(0x0F, 0x3C) ++#define REG_SC_BK0F_3D_L _PK_L_(0x0F, 0x3D) ++#define REG_SC_BK0F_3D_H _PK_H_(0x0F, 0x3D) ++#define REG_SC_BK0F_3E_L _PK_L_(0x0F, 0x3E) ++#define REG_SC_BK0F_3E_H _PK_H_(0x0F, 0x3E) ++#define REG_SC_BK0F_3F_L _PK_L_(0x0F, 0x3F) ++#define REG_SC_BK0F_3F_H _PK_H_(0x0F, 0x3F) ++#define REG_SC_BK0F_40_L _PK_L_(0x0F, 0x40) ++#define REG_SC_BK0F_40_H _PK_H_(0x0F, 0x40) ++#define REG_SC_BK0F_41_L _PK_L_(0x0F, 0x41) ++#define REG_SC_BK0F_41_H _PK_H_(0x0F, 0x41) ++#define REG_SC_BK0F_42_L _PK_L_(0x0F, 0x42) ++#define REG_SC_BK0F_42_H _PK_H_(0x0F, 0x42) ++#define REG_SC_BK0F_43_L _PK_L_(0x0F, 0x43) ++#define REG_SC_BK0F_43_H _PK_H_(0x0F, 0x43) ++#define REG_SC_BK0F_44_L _PK_L_(0x0F, 0x44) ++#define REG_SC_BK0F_44_H _PK_H_(0x0F, 0x44) ++#define REG_SC_BK0F_45_L _PK_L_(0x0F, 0x45) ++#define REG_SC_BK0F_45_H _PK_H_(0x0F, 0x45) ++#define REG_SC_BK0F_46_L _PK_L_(0x0F, 0x46) ++#define REG_SC_BK0F_46_H _PK_H_(0x0F, 0x46) ++#define REG_SC_BK0F_47_L _PK_L_(0x0F, 0x47) ++#define REG_SC_BK0F_47_H _PK_H_(0x0F, 0x47) ++#define REG_SC_BK0F_48_L _PK_L_(0x0F, 0x48) ++#define REG_SC_BK0F_48_H _PK_H_(0x0F, 0x48) ++#define REG_SC_BK0F_49_L _PK_L_(0x0F, 0x49) ++#define REG_SC_BK0F_49_H _PK_H_(0x0F, 0x49) ++#define REG_SC_BK0F_4A_L _PK_L_(0x0F, 0x4A) ++#define REG_SC_BK0F_4A_H _PK_H_(0x0F, 0x4A) ++#define REG_SC_BK0F_4B_L _PK_L_(0x0F, 0x4B) ++#define REG_SC_BK0F_4B_H _PK_H_(0x0F, 0x4B) ++#define REG_SC_BK0F_4C_L _PK_L_(0x0F, 0x4C) ++#define REG_SC_BK0F_4C_H _PK_H_(0x0F, 0x4C) ++#define REG_SC_BK0F_4D_L _PK_L_(0x0F, 0x4D) ++#define REG_SC_BK0F_4D_H _PK_H_(0x0F, 0x4D) ++#define REG_SC_BK0F_4E_L _PK_L_(0x0F, 0x4E) ++#define REG_SC_BK0F_4E_H _PK_H_(0x0F, 0x4E) ++#define REG_SC_BK0F_4F_L _PK_L_(0x0F, 0x4F) ++#define REG_SC_BK0F_4F_H _PK_H_(0x0F, 0x4F) ++#define REG_SC_BK0F_50_L _PK_L_(0x0F, 0x50) ++#define REG_SC_BK0F_50_H _PK_H_(0x0F, 0x50) ++#define REG_SC_BK0F_51_L _PK_L_(0x0F, 0x51) ++#define REG_SC_BK0F_51_H _PK_H_(0x0F, 0x51) ++#define REG_SC_BK0F_52_L _PK_L_(0x0F, 0x52) ++#define REG_SC_BK0F_52_H _PK_H_(0x0F, 0x52) ++#define REG_SC_BK0F_53_L _PK_L_(0x0F, 0x53) ++#define REG_SC_BK0F_53_H _PK_H_(0x0F, 0x53) ++#define REG_SC_BK0F_54_L _PK_L_(0x0F, 0x54) ++#define REG_SC_BK0F_54_H _PK_H_(0x0F, 0x54) ++#define REG_SC_BK0F_55_L _PK_L_(0x0F, 0x55) ++#define REG_SC_BK0F_55_H _PK_H_(0x0F, 0x55) ++#define REG_SC_BK0F_56_L _PK_L_(0x0F, 0x56) ++#define REG_SC_BK0F_56_H _PK_H_(0x0F, 0x56) ++#define REG_SC_BK0F_57_L _PK_L_(0x0F, 0x57) ++#define REG_SC_BK0F_57_H _PK_H_(0x0F, 0x57) ++#define REG_SC_BK0F_58_L _PK_L_(0x0F, 0x58) ++#define REG_SC_BK0F_58_H _PK_H_(0x0F, 0x58) ++#define REG_SC_BK0F_59_L _PK_L_(0x0F, 0x59) ++#define REG_SC_BK0F_59_H _PK_H_(0x0F, 0x59) ++#define REG_SC_BK0F_5A_L _PK_L_(0x0F, 0x5A) ++#define REG_SC_BK0F_5A_H _PK_H_(0x0F, 0x5A) ++#define REG_SC_BK0F_5B_L _PK_L_(0x0F, 0x5B) ++#define REG_SC_BK0F_5B_H _PK_H_(0x0F, 0x5B) ++#define REG_SC_BK0F_5C_L _PK_L_(0x0F, 0x5C) ++#define REG_SC_BK0F_5C_H _PK_H_(0x0F, 0x5C) ++#define REG_SC_BK0F_5D_L _PK_L_(0x0F, 0x5D) ++#define REG_SC_BK0F_5D_H _PK_H_(0x0F, 0x5D) ++#define REG_SC_BK0F_5E_L _PK_L_(0x0F, 0x5E) ++#define REG_SC_BK0F_5E_H _PK_H_(0x0F, 0x5E) ++#define REG_SC_BK0F_5F_L _PK_L_(0x0F, 0x5F) ++#define REG_SC_BK0F_5F_H _PK_H_(0x0F, 0x5F) ++#define REG_SC_BK0F_60_L _PK_L_(0x0F, 0x60) ++#define REG_SC_BK0F_60_H _PK_H_(0x0F, 0x60) ++#define REG_SC_BK0F_61_L _PK_L_(0x0F, 0x61) ++#define REG_SC_BK0F_61_H _PK_H_(0x0F, 0x61) ++#define REG_SC_BK0F_62_L _PK_L_(0x0F, 0x62) ++#define REG_SC_BK0F_62_H _PK_H_(0x0F, 0x62) ++#define REG_SC_BK0F_63_L _PK_L_(0x0F, 0x63) ++#define REG_SC_BK0F_63_H _PK_H_(0x0F, 0x63) ++#define REG_SC_BK0F_64_L _PK_L_(0x0F, 0x64) ++#define REG_SC_BK0F_64_H _PK_H_(0x0F, 0x64) ++#define REG_SC_BK0F_65_L _PK_L_(0x0F, 0x65) ++#define REG_SC_BK0F_65_H _PK_H_(0x0F, 0x65) ++#define REG_SC_BK0F_66_L _PK_L_(0x0F, 0x66) ++#define REG_SC_BK0F_66_H _PK_H_(0x0F, 0x66) ++#define REG_SC_BK0F_67_L _PK_L_(0x0F, 0x67) ++#define REG_SC_BK0F_67_H _PK_H_(0x0F, 0x67) ++#define REG_SC_BK0F_68_L _PK_L_(0x0F, 0x68) ++#define REG_SC_BK0F_68_H _PK_H_(0x0F, 0x68) ++#define REG_SC_BK0F_69_L _PK_L_(0x0F, 0x69) ++#define REG_SC_BK0F_69_H _PK_H_(0x0F, 0x69) ++#define REG_SC_BK0F_6A_L _PK_L_(0x0F, 0x6A) ++#define REG_SC_BK0F_6A_H _PK_H_(0x0F, 0x6A) ++#define REG_SC_BK0F_6B_L _PK_L_(0x0F, 0x6B) ++#define REG_SC_BK0F_6B_H _PK_H_(0x0F, 0x6B) ++#define REG_SC_BK0F_6C_L _PK_L_(0x0F, 0x6C) ++#define REG_SC_BK0F_6C_H _PK_H_(0x0F, 0x6C) ++#define REG_SC_BK0F_6D_L _PK_L_(0x0F, 0x6D) ++#define REG_SC_BK0F_6D_H _PK_H_(0x0F, 0x6D) ++#define REG_SC_BK0F_6E_L _PK_L_(0x0F, 0x6E) ++#define REG_SC_BK0F_6E_H _PK_H_(0x0F, 0x6E) ++#define REG_SC_BK0F_6F_L _PK_L_(0x0F, 0x6F) ++#define REG_SC_BK0F_6F_H _PK_H_(0x0F, 0x6F) ++#define REG_SC_BK0F_70_L _PK_L_(0x0F, 0x70) ++#define REG_SC_BK0F_70_H _PK_H_(0x0F, 0x70) ++#define REG_SC_BK0F_71_L _PK_L_(0x0F, 0x71) ++#define REG_SC_BK0F_71_H _PK_H_(0x0F, 0x71) ++#define REG_SC_BK0F_72_L _PK_L_(0x0F, 0x72) ++#define REG_SC_BK0F_72_H _PK_H_(0x0F, 0x72) ++#define REG_SC_BK0F_73_L _PK_L_(0x0F, 0x73) ++#define REG_SC_BK0F_73_H _PK_H_(0x0F, 0x73) ++#define REG_SC_BK0F_74_L _PK_L_(0x0F, 0x74) ++#define REG_SC_BK0F_74_H _PK_H_(0x0F, 0x74) ++#define REG_SC_BK0F_75_L _PK_L_(0x0F, 0x75) ++#define REG_SC_BK0F_75_H _PK_H_(0x0F, 0x75) ++#define REG_SC_BK0F_76_L _PK_L_(0x0F, 0x76) ++#define REG_SC_BK0F_76_H _PK_H_(0x0F, 0x76) ++#define REG_SC_BK0F_77_L _PK_L_(0x0F, 0x77) ++#define REG_SC_BK0F_77_H _PK_H_(0x0F, 0x77) ++#define REG_SC_BK0F_78_L _PK_L_(0x0F, 0x78) ++#define REG_SC_BK0F_78_H _PK_H_(0x0F, 0x78) ++#define REG_SC_BK0F_79_L _PK_L_(0x0F, 0x79) ++#define REG_SC_BK0F_79_H _PK_H_(0x0F, 0x79) ++#define REG_SC_BK0F_7A_L _PK_L_(0x0F, 0x7A) ++#define REG_SC_BK0F_7A_H _PK_H_(0x0F, 0x7A) ++#define REG_SC_BK0F_7B_L _PK_L_(0x0F, 0x7B) ++#define REG_SC_BK0F_7B_H _PK_H_(0x0F, 0x7B) ++#define REG_SC_BK0F_7C_L _PK_L_(0x0F, 0x7C) ++#define REG_SC_BK0F_7C_H _PK_H_(0x0F, 0x7C) ++#define REG_SC_BK0F_7D_L _PK_L_(0x0F, 0x7D) ++#define REG_SC_BK0F_7D_H _PK_H_(0x0F, 0x7D) ++#define REG_SC_BK0F_7E_L _PK_L_(0x0F, 0x7E) ++#define REG_SC_BK0F_7E_H _PK_H_(0x0F, 0x7E) ++#define REG_SC_BK0F_7F_L _PK_L_(0x0F, 0x7F) ++#define REG_SC_BK0F_7F_H _PK_H_(0x0F, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK10_00_L _PK_L_(0x10, 0x00) ++#define REG_SC_BK10_00_H _PK_H_(0x10, 0x00) ++#define REG_SC_BK10_01_L _PK_L_(0x10, 0x01) ++#define REG_SC_BK10_01_H _PK_H_(0x10, 0x01) ++#define REG_SC_BK10_02_L _PK_L_(0x10, 0x02) ++#define REG_SC_BK10_02_H _PK_H_(0x10, 0x02) ++#define REG_SC_BK10_03_L _PK_L_(0x10, 0x03) ++#define REG_SC_BK10_03_H _PK_H_(0x10, 0x03) ++#define REG_SC_BK10_04_L _PK_L_(0x10, 0x04) ++#define REG_SC_BK10_04_H _PK_H_(0x10, 0x04) ++#define REG_SC_BK10_05_L _PK_L_(0x10, 0x05) ++#define REG_SC_BK10_05_H _PK_H_(0x10, 0x05) ++#define REG_SC_BK10_06_L _PK_L_(0x10, 0x06) ++#define REG_SC_BK10_06_H _PK_H_(0x10, 0x06) ++#define REG_SC_BK10_07_L _PK_L_(0x10, 0x07) ++#define REG_SC_BK10_07_H _PK_H_(0x10, 0x07) ++#define REG_SC_BK10_08_L _PK_L_(0x10, 0x08) ++#define REG_SC_BK10_08_H _PK_H_(0x10, 0x08) ++#define REG_SC_BK10_09_L _PK_L_(0x10, 0x09) ++#define REG_SC_BK10_09_H _PK_H_(0x10, 0x09) ++#define REG_SC_BK10_0A_L _PK_L_(0x10, 0x0A) ++#define REG_SC_BK10_0A_H _PK_H_(0x10, 0x0A) ++#define REG_SC_BK10_0B_L _PK_L_(0x10, 0x0B) ++#define REG_SC_BK10_0B_H _PK_H_(0x10, 0x0B) ++#define REG_SC_BK10_0C_L _PK_L_(0x10, 0x0C) ++#define REG_SC_BK10_0C_H _PK_H_(0x10, 0x0C) ++#define REG_SC_BK10_0D_L _PK_L_(0x10, 0x0D) ++#define REG_SC_BK10_0D_H _PK_H_(0x10, 0x0D) ++#define REG_SC_BK10_0E_L _PK_L_(0x10, 0x0E) ++#define REG_SC_BK10_0E_H _PK_H_(0x10, 0x0E) ++#define REG_SC_BK10_0F_L _PK_L_(0x10, 0x0F) ++#define REG_SC_BK10_0F_H _PK_H_(0x10, 0x0F) ++#define REG_SC_BK10_10_L _PK_L_(0x10, 0x10) ++#define REG_SC_BK10_10_H _PK_H_(0x10, 0x10) ++#define REG_SC_BK10_11_L _PK_L_(0x10, 0x11) ++#define REG_SC_BK10_11_H _PK_H_(0x10, 0x11) ++#define REG_SC_BK10_12_L _PK_L_(0x10, 0x12) ++#define REG_SC_BK10_12_H _PK_H_(0x10, 0x12) ++#define REG_SC_BK10_13_L _PK_L_(0x10, 0x13) ++#define REG_SC_BK10_13_H _PK_H_(0x10, 0x13) ++#define REG_SC_BK10_14_L _PK_L_(0x10, 0x14) ++#define REG_SC_BK10_14_H _PK_H_(0x10, 0x14) ++#define REG_SC_BK10_15_L _PK_L_(0x10, 0x15) ++#define REG_SC_BK10_15_H _PK_H_(0x10, 0x15) ++#define REG_SC_BK10_16_L _PK_L_(0x10, 0x16) ++#define REG_SC_BK10_16_H _PK_H_(0x10, 0x16) ++#define REG_SC_BK10_17_L _PK_L_(0x10, 0x17) ++#define REG_SC_BK10_17_H _PK_H_(0x10, 0x17) ++#define REG_SC_BK10_18_L _PK_L_(0x10, 0x18) ++#define REG_SC_BK10_18_H _PK_H_(0x10, 0x18) ++#define REG_SC_BK10_19_L _PK_L_(0x10, 0x19) ++#define REG_SC_BK10_19_H _PK_H_(0x10, 0x19) ++#define REG_SC_BK10_1A_L _PK_L_(0x10, 0x1A) ++#define REG_SC_BK10_1A_H _PK_H_(0x10, 0x1A) ++#define REG_SC_BK10_1B_L _PK_L_(0x10, 0x1B) ++#define REG_SC_BK10_1B_H _PK_H_(0x10, 0x1B) ++#define REG_SC_BK10_1C_L _PK_L_(0x10, 0x1C) ++#define REG_SC_BK10_1C_H _PK_H_(0x10, 0x1C) ++#define REG_SC_BK10_1D_L _PK_L_(0x10, 0x1D) ++#define REG_SC_BK10_1D_H _PK_H_(0x10, 0x1D) ++#define REG_SC_BK10_1E_L _PK_L_(0x10, 0x1E) ++#define REG_SC_BK10_1E_H _PK_H_(0x10, 0x1E) ++#define REG_SC_BK10_1F_L _PK_L_(0x10, 0x1F) ++#define REG_SC_BK10_1F_H _PK_H_(0x10, 0x1F) ++#define REG_SC_BK10_20_L _PK_L_(0x10, 0x20) ++#define REG_SC_BK10_20_H _PK_H_(0x10, 0x20) ++#define REG_SC_BK10_21_L _PK_L_(0x10, 0x21) ++#define REG_SC_BK10_21_H _PK_H_(0x10, 0x21) ++#define REG_SC_BK10_22_L _PK_L_(0x10, 0x22) ++#define REG_SC_BK10_22_H _PK_H_(0x10, 0x22) ++#define REG_SC_BK10_23_L _PK_L_(0x10, 0x23) ++#define REG_SC_BK10_23_H _PK_H_(0x10, 0x23) ++#define REG_SC_BK10_24_L _PK_L_(0x10, 0x24) ++#define REG_SC_BK10_24_H _PK_H_(0x10, 0x24) ++#define REG_SC_BK10_25_L _PK_L_(0x10, 0x25) ++#define REG_SC_BK10_25_H _PK_H_(0x10, 0x25) ++#define REG_SC_BK10_26_L _PK_L_(0x10, 0x26) ++#define REG_SC_BK10_26_H _PK_H_(0x10, 0x26) ++#define REG_SC_BK10_27_L _PK_L_(0x10, 0x27) ++#define REG_SC_BK10_27_H _PK_H_(0x10, 0x27) ++#define REG_SC_BK10_28_L _PK_L_(0x10, 0x28) ++#define REG_SC_BK10_28_H _PK_H_(0x10, 0x28) ++#define REG_SC_BK10_29_L _PK_L_(0x10, 0x29) ++#define REG_SC_BK10_29_H _PK_H_(0x10, 0x29) ++#define REG_SC_BK10_2A_L _PK_L_(0x10, 0x2A) ++#define REG_SC_BK10_2A_H _PK_H_(0x10, 0x2A) ++#define REG_SC_BK10_2B_L _PK_L_(0x10, 0x2B) ++#define REG_SC_BK10_2B_H _PK_H_(0x10, 0x2B) ++#define REG_SC_BK10_2C_L _PK_L_(0x10, 0x2C) ++#define REG_SC_BK10_2C_H _PK_H_(0x10, 0x2C) ++#define REG_SC_BK10_2D_L _PK_L_(0x10, 0x2D) ++#define REG_SC_BK10_2D_H _PK_H_(0x10, 0x2D) ++#define REG_SC_BK10_2E_L _PK_L_(0x10, 0x2E) ++#define REG_SC_BK10_2E_H _PK_H_(0x10, 0x2E) ++#define REG_SC_BK10_2F_L _PK_L_(0x10, 0x2F) ++#define REG_SC_BK10_2F_H _PK_H_(0x10, 0x2F) ++#define REG_SC_BK10_30_L _PK_L_(0x10, 0x30) ++#define REG_SC_BK10_30_H _PK_H_(0x10, 0x30) ++#define REG_SC_BK10_31_L _PK_L_(0x10, 0x31) ++#define REG_SC_BK10_31_H _PK_H_(0x10, 0x31) ++#define REG_SC_BK10_32_L _PK_L_(0x10, 0x32) ++#define REG_SC_BK10_32_H _PK_H_(0x10, 0x32) ++#define REG_SC_BK10_33_L _PK_L_(0x10, 0x33) ++#define REG_SC_BK10_33_H _PK_H_(0x10, 0x33) ++#define REG_SC_BK10_34_L _PK_L_(0x10, 0x34) ++#define REG_SC_BK10_34_H _PK_H_(0x10, 0x34) ++#define REG_SC_BK10_35_L _PK_L_(0x10, 0x35) ++#define REG_SC_BK10_35_H _PK_H_(0x10, 0x35) ++#define REG_SC_BK10_36_L _PK_L_(0x10, 0x36) ++#define REG_SC_BK10_36_H _PK_H_(0x10, 0x36) ++#define REG_SC_BK10_37_L _PK_L_(0x10, 0x37) ++#define REG_SC_BK10_37_H _PK_H_(0x10, 0x37) ++#define REG_SC_BK10_38_L _PK_L_(0x10, 0x38) ++#define REG_SC_BK10_38_H _PK_H_(0x10, 0x38) ++#define REG_SC_BK10_39_L _PK_L_(0x10, 0x39) ++#define REG_SC_BK10_39_H _PK_H_(0x10, 0x39) ++#define REG_SC_BK10_3A_L _PK_L_(0x10, 0x3A) ++#define REG_SC_BK10_3A_H _PK_H_(0x10, 0x3A) ++#define REG_SC_BK10_3B_L _PK_L_(0x10, 0x3B) ++#define REG_SC_BK10_3B_H _PK_H_(0x10, 0x3B) ++#define REG_SC_BK10_3C_L _PK_L_(0x10, 0x3C) ++#define REG_SC_BK10_3C_H _PK_H_(0x10, 0x3C) ++#define REG_SC_BK10_3D_L _PK_L_(0x10, 0x3D) ++#define REG_SC_BK10_3D_H _PK_H_(0x10, 0x3D) ++#define REG_SC_BK10_3E_L _PK_L_(0x10, 0x3E) ++#define REG_SC_BK10_3E_H _PK_H_(0x10, 0x3E) ++#define REG_SC_BK10_3F_L _PK_L_(0x10, 0x3F) ++#define REG_SC_BK10_3F_H _PK_H_(0x10, 0x3F) ++#define REG_SC_BK10_40_L _PK_L_(0x10, 0x40) ++#define REG_SC_BK10_40_H _PK_H_(0x10, 0x40) ++#define REG_SC_BK10_41_L _PK_L_(0x10, 0x41) ++#define REG_SC_BK10_41_H _PK_H_(0x10, 0x41) ++#define REG_SC_BK10_42_L _PK_L_(0x10, 0x42) ++#define REG_SC_BK10_42_H _PK_H_(0x10, 0x42) ++#define REG_SC_BK10_43_L _PK_L_(0x10, 0x43) ++#define REG_SC_BK10_43_H _PK_H_(0x10, 0x43) ++#define REG_SC_BK10_44_L _PK_L_(0x10, 0x44) ++#define REG_SC_BK10_44_H _PK_H_(0x10, 0x44) ++#define REG_SC_BK10_45_L _PK_L_(0x10, 0x45) ++#define REG_SC_BK10_45_H _PK_H_(0x10, 0x45) ++#define REG_SC_BK10_46_L _PK_L_(0x10, 0x46) ++#define REG_SC_BK10_46_H _PK_H_(0x10, 0x46) ++#define REG_SC_BK10_47_L _PK_L_(0x10, 0x47) ++#define REG_SC_BK10_47_H _PK_H_(0x10, 0x47) ++#define REG_SC_BK10_48_L _PK_L_(0x10, 0x48) ++#define REG_SC_BK10_48_H _PK_H_(0x10, 0x48) ++#define REG_SC_BK10_49_L _PK_L_(0x10, 0x49) ++#define REG_SC_BK10_49_H _PK_H_(0x10, 0x49) ++#define REG_SC_BK10_4A_L _PK_L_(0x10, 0x4A) ++#define REG_SC_BK10_4A_H _PK_H_(0x10, 0x4A) ++#define REG_SC_BK10_4B_L _PK_L_(0x10, 0x4B) ++#define REG_SC_BK10_4B_H _PK_H_(0x10, 0x4B) ++#define REG_SC_BK10_4C_L _PK_L_(0x10, 0x4C) ++#define REG_SC_BK10_4C_H _PK_H_(0x10, 0x4C) ++#define REG_SC_BK10_4D_L _PK_L_(0x10, 0x4D) ++#define REG_SC_BK10_4D_H _PK_H_(0x10, 0x4D) ++#define REG_SC_BK10_4E_L _PK_L_(0x10, 0x4E) ++#define REG_SC_BK10_4E_H _PK_H_(0x10, 0x4E) ++#define REG_SC_BK10_4F_L _PK_L_(0x10, 0x4F) ++#define REG_SC_BK10_4F_H _PK_H_(0x10, 0x4F) ++#define REG_SC_BK10_50_L _PK_L_(0x10, 0x50) ++#define REG_SC_BK10_50_H _PK_H_(0x10, 0x50) ++#define REG_SC_BK10_51_L _PK_L_(0x10, 0x51) ++#define REG_SC_BK10_51_H _PK_H_(0x10, 0x51) ++#define REG_SC_BK10_52_L _PK_L_(0x10, 0x52) ++#define REG_SC_BK10_52_H _PK_H_(0x10, 0x52) ++#define REG_SC_BK10_53_L _PK_L_(0x10, 0x53) ++#define REG_SC_BK10_53_H _PK_H_(0x10, 0x53) ++#define REG_SC_BK10_54_L _PK_L_(0x10, 0x54) ++#define REG_SC_BK10_54_H _PK_H_(0x10, 0x54) ++#define REG_SC_BK10_55_L _PK_L_(0x10, 0x55) ++#define REG_SC_BK10_55_H _PK_H_(0x10, 0x55) ++#define REG_SC_BK10_56_L _PK_L_(0x10, 0x56) ++#define REG_SC_BK10_56_H _PK_H_(0x10, 0x56) ++#define REG_SC_BK10_57_L _PK_L_(0x10, 0x57) ++#define REG_SC_BK10_57_H _PK_H_(0x10, 0x57) ++#define REG_SC_BK10_58_L _PK_L_(0x10, 0x58) ++#define REG_SC_BK10_58_H _PK_H_(0x10, 0x58) ++#define REG_SC_BK10_59_L _PK_L_(0x10, 0x59) ++#define REG_SC_BK10_59_H _PK_H_(0x10, 0x59) ++#define REG_SC_BK10_5A_L _PK_L_(0x10, 0x5A) ++#define REG_SC_BK10_5A_H _PK_H_(0x10, 0x5A) ++#define REG_SC_BK10_5B_L _PK_L_(0x10, 0x5B) ++#define REG_SC_BK10_5B_H _PK_H_(0x10, 0x5B) ++#define REG_SC_BK10_5C_L _PK_L_(0x10, 0x5C) ++#define REG_SC_BK10_5C_H _PK_H_(0x10, 0x5C) ++#define REG_SC_BK10_5D_L _PK_L_(0x10, 0x5D) ++#define REG_SC_BK10_5D_H _PK_H_(0x10, 0x5D) ++#define REG_SC_BK10_5E_L _PK_L_(0x10, 0x5E) ++#define REG_SC_BK10_5E_H _PK_H_(0x10, 0x5E) ++#define REG_SC_BK10_5F_L _PK_L_(0x10, 0x5F) ++#define REG_SC_BK10_5F_H _PK_H_(0x10, 0x5F) ++#define REG_SC_BK10_60_L _PK_L_(0x10, 0x60) ++#define REG_SC_BK10_60_H _PK_H_(0x10, 0x60) ++#define REG_SC_BK10_61_L _PK_L_(0x10, 0x61) ++#define REG_SC_BK10_61_H _PK_H_(0x10, 0x61) ++#define REG_SC_BK10_62_L _PK_L_(0x10, 0x62) ++#define REG_SC_BK10_62_H _PK_H_(0x10, 0x62) ++#define REG_SC_BK10_63_L _PK_L_(0x10, 0x63) ++#define REG_SC_BK10_63_H _PK_H_(0x10, 0x63) ++#define REG_SC_BK10_64_L _PK_L_(0x10, 0x64) ++#define REG_SC_BK10_64_H _PK_H_(0x10, 0x64) ++#define REG_SC_BK10_65_L _PK_L_(0x10, 0x65) ++#define REG_SC_BK10_65_H _PK_H_(0x10, 0x65) ++#define REG_SC_BK10_66_L _PK_L_(0x10, 0x66) ++#define REG_SC_BK10_66_H _PK_H_(0x10, 0x66) ++#define REG_SC_BK10_67_L _PK_L_(0x10, 0x67) ++#define REG_SC_BK10_67_H _PK_H_(0x10, 0x67) ++#define REG_SC_BK10_68_L _PK_L_(0x10, 0x68) ++#define REG_SC_BK10_68_H _PK_H_(0x10, 0x68) ++#define REG_SC_BK10_69_L _PK_L_(0x10, 0x69) ++#define REG_SC_BK10_69_H _PK_H_(0x10, 0x69) ++#define REG_SC_BK10_6A_L _PK_L_(0x10, 0x6A) ++#define REG_SC_BK10_6A_H _PK_H_(0x10, 0x6A) ++#define REG_SC_BK10_6B_L _PK_L_(0x10, 0x6B) ++#define REG_SC_BK10_6B_H _PK_H_(0x10, 0x6B) ++#define REG_SC_BK10_6C_L _PK_L_(0x10, 0x6C) ++#define REG_SC_BK10_6C_H _PK_H_(0x10, 0x6C) ++#define REG_SC_BK10_6D_L _PK_L_(0x10, 0x6D) ++#define REG_SC_BK10_6D_H _PK_H_(0x10, 0x6D) ++#define REG_SC_BK10_6E_L _PK_L_(0x10, 0x6E) ++#define REG_SC_BK10_6E_H _PK_H_(0x10, 0x6E) ++#define REG_SC_BK10_6F_L _PK_L_(0x10, 0x6F) ++#define REG_SC_BK10_6F_H _PK_H_(0x10, 0x6F) ++#define REG_SC_BK10_70_L _PK_L_(0x10, 0x70) ++#define REG_SC_BK10_70_H _PK_H_(0x10, 0x70) ++#define REG_SC_BK10_71_L _PK_L_(0x10, 0x71) ++#define REG_SC_BK10_71_H _PK_H_(0x10, 0x71) ++#define REG_SC_BK10_72_L _PK_L_(0x10, 0x72) ++#define REG_SC_BK10_72_H _PK_H_(0x10, 0x72) ++#define REG_SC_BK10_73_L _PK_L_(0x10, 0x73) ++#define REG_SC_BK10_73_H _PK_H_(0x10, 0x73) ++#define REG_SC_BK10_74_L _PK_L_(0x10, 0x74) ++#define REG_SC_BK10_74_H _PK_H_(0x10, 0x74) ++#define REG_SC_BK10_75_L _PK_L_(0x10, 0x75) ++#define REG_SC_BK10_75_H _PK_H_(0x10, 0x75) ++#define REG_SC_BK10_76_L _PK_L_(0x10, 0x76) ++#define REG_SC_BK10_76_H _PK_H_(0x10, 0x76) ++#define REG_SC_BK10_77_L _PK_L_(0x10, 0x77) ++#define REG_SC_BK10_77_H _PK_H_(0x10, 0x77) ++#define REG_SC_BK10_78_L _PK_L_(0x10, 0x78) ++#define REG_SC_BK10_78_H _PK_H_(0x10, 0x78) ++#define REG_SC_BK10_79_L _PK_L_(0x10, 0x79) ++#define REG_SC_BK10_79_H _PK_H_(0x10, 0x79) ++#define REG_SC_BK10_7A_L _PK_L_(0x10, 0x7A) ++#define REG_SC_BK10_7A_H _PK_H_(0x10, 0x7A) ++#define REG_SC_BK10_7B_L _PK_L_(0x10, 0x7B) ++#define REG_SC_BK10_7B_H _PK_H_(0x10, 0x7B) ++#define REG_SC_BK10_7C_L _PK_L_(0x10, 0x7C) ++#define REG_SC_BK10_7C_H _PK_H_(0x10, 0x7C) ++#define REG_SC_BK10_7D_L _PK_L_(0x10, 0x7D) ++#define REG_SC_BK10_7D_H _PK_H_(0x10, 0x7D) ++#define REG_SC_BK10_7E_L _PK_L_(0x10, 0x7E) ++#define REG_SC_BK10_7E_H _PK_H_(0x10, 0x7E) ++#define REG_SC_BK10_7F_L _PK_L_(0x10, 0x7F) ++#define REG_SC_BK10_7F_H _PK_H_(0x10, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK11_00_L _PK_L_(0x11, 0x00) ++#define REG_SC_BK11_00_H _PK_H_(0x11, 0x00) ++#define REG_SC_BK11_01_L _PK_L_(0x11, 0x01) ++#define REG_SC_BK11_01_H _PK_H_(0x11, 0x01) ++#define REG_SC_BK11_02_L _PK_L_(0x11, 0x02) ++#define REG_SC_BK11_02_H _PK_H_(0x11, 0x02) ++#define REG_SC_BK11_03_L _PK_L_(0x11, 0x03) ++#define REG_SC_BK11_03_H _PK_H_(0x11, 0x03) ++#define REG_SC_BK11_04_L _PK_L_(0x11, 0x04) ++#define REG_SC_BK11_04_H _PK_H_(0x11, 0x04) ++#define REG_SC_BK11_05_L _PK_L_(0x11, 0x05) ++#define REG_SC_BK11_05_H _PK_H_(0x11, 0x05) ++#define REG_SC_BK11_06_L _PK_L_(0x11, 0x06) ++#define REG_SC_BK11_06_H _PK_H_(0x11, 0x06) ++#define REG_SC_BK11_07_L _PK_L_(0x11, 0x07) ++#define REG_SC_BK11_07_H _PK_H_(0x11, 0x07) ++#define REG_SC_BK11_08_L _PK_L_(0x11, 0x08) ++#define REG_SC_BK11_08_H _PK_H_(0x11, 0x08) ++#define REG_SC_BK11_09_L _PK_L_(0x11, 0x09) ++#define REG_SC_BK11_09_H _PK_H_(0x11, 0x09) ++#define REG_SC_BK11_0A_L _PK_L_(0x11, 0x0A) ++#define REG_SC_BK11_0A_H _PK_H_(0x11, 0x0A) ++#define REG_SC_BK11_0B_L _PK_L_(0x11, 0x0B) ++#define REG_SC_BK11_0B_H _PK_H_(0x11, 0x0B) ++#define REG_SC_BK11_0C_L _PK_L_(0x11, 0x0C) ++#define REG_SC_BK11_0C_H _PK_H_(0x11, 0x0C) ++#define REG_SC_BK11_0D_L _PK_L_(0x11, 0x0D) ++#define REG_SC_BK11_0D_H _PK_H_(0x11, 0x0D) ++#define REG_SC_BK11_0E_L _PK_L_(0x11, 0x0E) ++#define REG_SC_BK11_0E_H _PK_H_(0x11, 0x0E) ++#define REG_SC_BK11_0F_L _PK_L_(0x11, 0x0F) ++#define REG_SC_BK11_0F_H _PK_H_(0x11, 0x0F) ++#define REG_SC_BK11_10_L _PK_L_(0x11, 0x10) ++#define REG_SC_BK11_10_H _PK_H_(0x11, 0x10) ++#define REG_SC_BK11_11_L _PK_L_(0x11, 0x11) ++#define REG_SC_BK11_11_H _PK_H_(0x11, 0x11) ++#define REG_SC_BK11_12_L _PK_L_(0x11, 0x12) ++#define REG_SC_BK11_12_H _PK_H_(0x11, 0x12) ++#define REG_SC_BK11_13_L _PK_L_(0x11, 0x13) ++#define REG_SC_BK11_13_H _PK_H_(0x11, 0x13) ++#define REG_SC_BK11_14_L _PK_L_(0x11, 0x14) ++#define REG_SC_BK11_14_H _PK_H_(0x11, 0x14) ++#define REG_SC_BK11_15_L _PK_L_(0x11, 0x15) ++#define REG_SC_BK11_15_H _PK_H_(0x11, 0x15) ++#define REG_SC_BK11_16_L _PK_L_(0x11, 0x16) ++#define REG_SC_BK11_16_H _PK_H_(0x11, 0x16) ++#define REG_SC_BK11_17_L _PK_L_(0x11, 0x17) ++#define REG_SC_BK11_17_H _PK_H_(0x11, 0x17) ++#define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) ++#define REG_SC_BK11_18_H _PK_H_(0x11, 0x18) ++#define REG_SC_BK11_19_L _PK_L_(0x11, 0x19) ++#define REG_SC_BK11_19_H _PK_H_(0x11, 0x19) ++#define REG_SC_BK11_1A_L _PK_L_(0x11, 0x1A) ++#define REG_SC_BK11_1A_H _PK_H_(0x11, 0x1A) ++#define REG_SC_BK11_1B_L _PK_L_(0x11, 0x1B) ++#define REG_SC_BK11_1B_H _PK_H_(0x11, 0x1B) ++#define REG_SC_BK11_1C_L _PK_L_(0x11, 0x1C) ++#define REG_SC_BK11_1C_H _PK_H_(0x11, 0x1C) ++#define REG_SC_BK11_1D_L _PK_L_(0x11, 0x1D) ++#define REG_SC_BK11_1D_H _PK_H_(0x11, 0x1D) ++#define REG_SC_BK11_1E_L _PK_L_(0x11, 0x1E) ++#define REG_SC_BK11_1E_H _PK_H_(0x11, 0x1E) ++#define REG_SC_BK11_1F_L _PK_L_(0x11, 0x1F) ++#define REG_SC_BK11_1F_H _PK_H_(0x11, 0x1F) ++#define REG_SC_BK11_20_L _PK_L_(0x11, 0x20) ++#define REG_SC_BK11_20_H _PK_H_(0x11, 0x20) ++#define REG_SC_BK11_21_L _PK_L_(0x11, 0x21) ++#define REG_SC_BK11_21_H _PK_H_(0x11, 0x21) ++#define REG_SC_BK11_22_L _PK_L_(0x11, 0x22) ++#define REG_SC_BK11_22_H _PK_H_(0x11, 0x22) ++#define REG_SC_BK11_23_L _PK_L_(0x11, 0x23) ++#define REG_SC_BK11_23_H _PK_H_(0x11, 0x23) ++#define REG_SC_BK11_24_L _PK_L_(0x11, 0x24) ++#define REG_SC_BK11_24_H _PK_H_(0x11, 0x24) ++#define REG_SC_BK11_25_L _PK_L_(0x11, 0x25) ++#define REG_SC_BK11_25_H _PK_H_(0x11, 0x25) ++#define REG_SC_BK11_26_L _PK_L_(0x11, 0x26) ++#define REG_SC_BK11_26_H _PK_H_(0x11, 0x26) ++#define REG_SC_BK11_27_L _PK_L_(0x11, 0x27) ++#define REG_SC_BK11_27_H _PK_H_(0x11, 0x27) ++#define REG_SC_BK11_28_L _PK_L_(0x11, 0x28) ++#define REG_SC_BK11_28_H _PK_H_(0x11, 0x28) ++#define REG_SC_BK11_29_L _PK_L_(0x11, 0x29) ++#define REG_SC_BK11_29_H _PK_H_(0x11, 0x29) ++#define REG_SC_BK11_2A_L _PK_L_(0x11, 0x2A) ++#define REG_SC_BK11_2A_H _PK_H_(0x11, 0x2A) ++#define REG_SC_BK11_2B_L _PK_L_(0x11, 0x2B) ++#define REG_SC_BK11_2B_H _PK_H_(0x11, 0x2B) ++#define REG_SC_BK11_2C_L _PK_L_(0x11, 0x2C) ++#define REG_SC_BK11_2C_H _PK_H_(0x11, 0x2C) ++#define REG_SC_BK11_2D_L _PK_L_(0x11, 0x2D) ++#define REG_SC_BK11_2D_H _PK_H_(0x11, 0x2D) ++#define REG_SC_BK11_2E_L _PK_L_(0x11, 0x2E) ++#define REG_SC_BK11_2E_H _PK_H_(0x11, 0x2E) ++#define REG_SC_BK11_2F_L _PK_L_(0x11, 0x2F) ++#define REG_SC_BK11_2F_H _PK_H_(0x11, 0x2F) ++#define REG_SC_BK11_30_L _PK_L_(0x11, 0x30) ++#define REG_SC_BK11_30_H _PK_H_(0x11, 0x30) ++#define REG_SC_BK11_31_L _PK_L_(0x11, 0x31) ++#define REG_SC_BK11_31_H _PK_H_(0x11, 0x31) ++#define REG_SC_BK11_32_L _PK_L_(0x11, 0x32) ++#define REG_SC_BK11_32_H _PK_H_(0x11, 0x32) ++#define REG_SC_BK11_33_L _PK_L_(0x11, 0x33) ++#define REG_SC_BK11_33_H _PK_H_(0x11, 0x33) ++#define REG_SC_BK11_34_L _PK_L_(0x11, 0x34) ++#define REG_SC_BK11_34_H _PK_H_(0x11, 0x34) ++#define REG_SC_BK11_35_L _PK_L_(0x11, 0x35) ++#define REG_SC_BK11_35_H _PK_H_(0x11, 0x35) ++#define REG_SC_BK11_36_L _PK_L_(0x11, 0x36) ++#define REG_SC_BK11_36_H _PK_H_(0x11, 0x36) ++#define REG_SC_BK11_37_L _PK_L_(0x11, 0x37) ++#define REG_SC_BK11_37_H _PK_H_(0x11, 0x37) ++#define REG_SC_BK11_38_L _PK_L_(0x11, 0x38) ++#define REG_SC_BK11_38_H _PK_H_(0x11, 0x38) ++#define REG_SC_BK11_39_L _PK_L_(0x11, 0x39) ++#define REG_SC_BK11_39_H _PK_H_(0x11, 0x39) ++#define REG_SC_BK11_3A_L _PK_L_(0x11, 0x3A) ++#define REG_SC_BK11_3A_H _PK_H_(0x11, 0x3A) ++#define REG_SC_BK11_3B_L _PK_L_(0x11, 0x3B) ++#define REG_SC_BK11_3B_H _PK_H_(0x11, 0x3B) ++#define REG_SC_BK11_3C_L _PK_L_(0x11, 0x3C) ++#define REG_SC_BK11_3C_H _PK_H_(0x11, 0x3C) ++#define REG_SC_BK11_3D_L _PK_L_(0x11, 0x3D) ++#define REG_SC_BK11_3D_H _PK_H_(0x11, 0x3D) ++#define REG_SC_BK11_3E_L _PK_L_(0x11, 0x3E) ++#define REG_SC_BK11_3E_H _PK_H_(0x11, 0x3E) ++#define REG_SC_BK11_3F_L _PK_L_(0x11, 0x3F) ++#define REG_SC_BK11_3F_H _PK_H_(0x11, 0x3F) ++#define REG_SC_BK11_40_L _PK_L_(0x11, 0x40) ++#define REG_SC_BK11_40_H _PK_H_(0x11, 0x40) ++#define REG_SC_BK11_41_L _PK_L_(0x11, 0x41) ++#define REG_SC_BK11_41_H _PK_H_(0x11, 0x41) ++#define REG_SC_BK11_42_L _PK_L_(0x11, 0x42) ++#define REG_SC_BK11_42_H _PK_H_(0x11, 0x42) ++#define REG_SC_BK11_43_L _PK_L_(0x11, 0x43) ++#define REG_SC_BK11_43_H _PK_H_(0x11, 0x43) ++#define REG_SC_BK11_44_L _PK_L_(0x11, 0x44) ++#define REG_SC_BK11_44_H _PK_H_(0x11, 0x44) ++#define REG_SC_BK11_45_L _PK_L_(0x11, 0x45) ++#define REG_SC_BK11_45_H _PK_H_(0x11, 0x45) ++#define REG_SC_BK11_46_L _PK_L_(0x11, 0x46) ++#define REG_SC_BK11_46_H _PK_H_(0x11, 0x46) ++#define REG_SC_BK11_47_L _PK_L_(0x11, 0x47) ++#define REG_SC_BK11_47_H _PK_H_(0x11, 0x47) ++#define REG_SC_BK11_48_L _PK_L_(0x11, 0x48) ++#define REG_SC_BK11_48_H _PK_H_(0x11, 0x48) ++#define REG_SC_BK11_49_L _PK_L_(0x11, 0x49) ++#define REG_SC_BK11_49_H _PK_H_(0x11, 0x49) ++#define REG_SC_BK11_4A_L _PK_L_(0x11, 0x4A) ++#define REG_SC_BK11_4A_H _PK_H_(0x11, 0x4A) ++#define REG_SC_BK11_4B_L _PK_L_(0x11, 0x4B) ++#define REG_SC_BK11_4B_H _PK_H_(0x11, 0x4B) ++#define REG_SC_BK11_4C_L _PK_L_(0x11, 0x4C) ++#define REG_SC_BK11_4C_H _PK_H_(0x11, 0x4C) ++#define REG_SC_BK11_4D_L _PK_L_(0x11, 0x4D) ++#define REG_SC_BK11_4D_H _PK_H_(0x11, 0x4D) ++#define REG_SC_BK11_4E_L _PK_L_(0x11, 0x4E) ++#define REG_SC_BK11_4E_H _PK_H_(0x11, 0x4E) ++#define REG_SC_BK11_4F_L _PK_L_(0x11, 0x4F) ++#define REG_SC_BK11_4F_H _PK_H_(0x11, 0x4F) ++#define REG_SC_BK11_50_L _PK_L_(0x11, 0x50) ++#define REG_SC_BK11_50_H _PK_H_(0x11, 0x50) ++#define REG_SC_BK11_51_L _PK_L_(0x11, 0x51) ++#define REG_SC_BK11_51_H _PK_H_(0x11, 0x51) ++#define REG_SC_BK11_52_L _PK_L_(0x11, 0x52) ++#define REG_SC_BK11_52_H _PK_H_(0x11, 0x52) ++#define REG_SC_BK11_53_L _PK_L_(0x11, 0x53) ++#define REG_SC_BK11_53_H _PK_H_(0x11, 0x53) ++#define REG_SC_BK11_54_L _PK_L_(0x11, 0x54) ++#define REG_SC_BK11_54_H _PK_H_(0x11, 0x54) ++#define REG_SC_BK11_55_L _PK_L_(0x11, 0x55) ++#define REG_SC_BK11_55_H _PK_H_(0x11, 0x55) ++#define REG_SC_BK11_56_L _PK_L_(0x11, 0x56) ++#define REG_SC_BK11_56_H _PK_H_(0x11, 0x56) ++#define REG_SC_BK11_57_L _PK_L_(0x11, 0x57) ++#define REG_SC_BK11_57_H _PK_H_(0x11, 0x57) ++#define REG_SC_BK11_58_L _PK_L_(0x11, 0x58) ++#define REG_SC_BK11_58_H _PK_H_(0x11, 0x58) ++#define REG_SC_BK11_59_L _PK_L_(0x11, 0x59) ++#define REG_SC_BK11_59_H _PK_H_(0x11, 0x59) ++#define REG_SC_BK11_5A_L _PK_L_(0x11, 0x5A) ++#define REG_SC_BK11_5A_H _PK_H_(0x11, 0x5A) ++#define REG_SC_BK11_5B_L _PK_L_(0x11, 0x5B) ++#define REG_SC_BK11_5B_H _PK_H_(0x11, 0x5B) ++#define REG_SC_BK11_5C_L _PK_L_(0x11, 0x5C) ++#define REG_SC_BK11_5C_H _PK_H_(0x11, 0x5C) ++#define REG_SC_BK11_5D_L _PK_L_(0x11, 0x5D) ++#define REG_SC_BK11_5D_H _PK_H_(0x11, 0x5D) ++#define REG_SC_BK11_5E_L _PK_L_(0x11, 0x5E) ++#define REG_SC_BK11_5E_H _PK_H_(0x11, 0x5E) ++#define REG_SC_BK11_5F_L _PK_L_(0x11, 0x5F) ++#define REG_SC_BK11_5F_H _PK_H_(0x11, 0x5F) ++#define REG_SC_BK11_60_L _PK_L_(0x11, 0x60) ++#define REG_SC_BK11_60_H _PK_H_(0x11, 0x60) ++#define REG_SC_BK11_61_L _PK_L_(0x11, 0x61) ++#define REG_SC_BK11_61_H _PK_H_(0x11, 0x61) ++#define REG_SC_BK11_62_L _PK_L_(0x11, 0x62) ++#define REG_SC_BK11_62_H _PK_H_(0x11, 0x62) ++#define REG_SC_BK11_63_L _PK_L_(0x11, 0x63) ++#define REG_SC_BK11_63_H _PK_H_(0x11, 0x63) ++#define REG_SC_BK11_64_L _PK_L_(0x11, 0x64) ++#define REG_SC_BK11_64_H _PK_H_(0x11, 0x64) ++#define REG_SC_BK11_65_L _PK_L_(0x11, 0x65) ++#define REG_SC_BK11_65_H _PK_H_(0x11, 0x65) ++#define REG_SC_BK11_66_L _PK_L_(0x11, 0x66) ++#define REG_SC_BK11_66_H _PK_H_(0x11, 0x66) ++#define REG_SC_BK11_67_L _PK_L_(0x11, 0x67) ++#define REG_SC_BK11_67_H _PK_H_(0x11, 0x67) ++#define REG_SC_BK11_68_L _PK_L_(0x11, 0x68) ++#define REG_SC_BK11_68_H _PK_H_(0x11, 0x68) ++#define REG_SC_BK11_69_L _PK_L_(0x11, 0x69) ++#define REG_SC_BK11_69_H _PK_H_(0x11, 0x69) ++#define REG_SC_BK11_6A_L _PK_L_(0x11, 0x6A) ++#define REG_SC_BK11_6A_H _PK_H_(0x11, 0x6A) ++#define REG_SC_BK11_6B_L _PK_L_(0x11, 0x6B) ++#define REG_SC_BK11_6B_H _PK_H_(0x11, 0x6B) ++#define REG_SC_BK11_6C_L _PK_L_(0x11, 0x6C) ++#define REG_SC_BK11_6C_H _PK_H_(0x11, 0x6C) ++#define REG_SC_BK11_6D_L _PK_L_(0x11, 0x6D) ++#define REG_SC_BK11_6D_H _PK_H_(0x11, 0x6D) ++#define REG_SC_BK11_6E_L _PK_L_(0x11, 0x6E) ++#define REG_SC_BK11_6E_H _PK_H_(0x11, 0x6E) ++#define REG_SC_BK11_6F_L _PK_L_(0x11, 0x6F) ++#define REG_SC_BK11_6F_H _PK_H_(0x11, 0x6F) ++#define REG_SC_BK11_70_L _PK_L_(0x11, 0x70) ++#define REG_SC_BK11_70_H _PK_H_(0x11, 0x70) ++#define REG_SC_BK11_71_L _PK_L_(0x11, 0x71) ++#define REG_SC_BK11_71_H _PK_H_(0x11, 0x71) ++#define REG_SC_BK11_72_L _PK_L_(0x11, 0x72) ++#define REG_SC_BK11_72_H _PK_H_(0x11, 0x72) ++#define REG_SC_BK11_73_L _PK_L_(0x11, 0x73) ++#define REG_SC_BK11_73_H _PK_H_(0x11, 0x73) ++#define REG_SC_BK11_74_L _PK_L_(0x11, 0x74) ++#define REG_SC_BK11_74_H _PK_H_(0x11, 0x74) ++#define REG_SC_BK11_75_L _PK_L_(0x11, 0x75) ++#define REG_SC_BK11_75_H _PK_H_(0x11, 0x75) ++#define REG_SC_BK11_76_L _PK_L_(0x11, 0x76) ++#define REG_SC_BK11_76_H _PK_H_(0x11, 0x76) ++#define REG_SC_BK11_77_L _PK_L_(0x11, 0x77) ++#define REG_SC_BK11_77_H _PK_H_(0x11, 0x77) ++#define REG_SC_BK11_78_L _PK_L_(0x11, 0x78) ++#define REG_SC_BK11_78_H _PK_H_(0x11, 0x78) ++#define REG_SC_BK11_79_L _PK_L_(0x11, 0x79) ++#define REG_SC_BK11_79_H _PK_H_(0x11, 0x79) ++#define REG_SC_BK11_7A_L _PK_L_(0x11, 0x7A) ++#define REG_SC_BK11_7A_H _PK_H_(0x11, 0x7A) ++#define REG_SC_BK11_7B_L _PK_L_(0x11, 0x7B) ++#define REG_SC_BK11_7B_H _PK_H_(0x11, 0x7B) ++#define REG_SC_BK11_7C_L _PK_L_(0x11, 0x7C) ++#define REG_SC_BK11_7C_H _PK_H_(0x11, 0x7C) ++#define REG_SC_BK11_7D_L _PK_L_(0x11, 0x7D) ++#define REG_SC_BK11_7D_H _PK_H_(0x11, 0x7D) ++#define REG_SC_BK11_7E_L _PK_L_(0x11, 0x7E) ++#define REG_SC_BK11_7E_H _PK_H_(0x11, 0x7E) ++#define REG_SC_BK11_7F_L _PK_L_(0x11, 0x7F) ++#define REG_SC_BK11_7F_H _PK_H_(0x11, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK12_00_L _PK_L_(0x12, 0x00) ++#define REG_SC_BK12_00_H _PK_H_(0x12, 0x00) ++#define REG_SC_BK12_01_L _PK_L_(0x12, 0x01) ++#define REG_SC_BK12_01_H _PK_H_(0x12, 0x01) ++#define REG_SC_BK12_02_L _PK_L_(0x12, 0x02) ++#define REG_SC_BK12_02_H _PK_H_(0x12, 0x02) ++#define REG_SC_BK12_03_L _PK_L_(0x12, 0x03) ++#define REG_SC_BK12_03_H _PK_H_(0x12, 0x03) ++#define REG_SC_BK12_04_L _PK_L_(0x12, 0x04) ++#define REG_SC_BK12_04_H _PK_H_(0x12, 0x04) ++#define REG_SC_BK12_05_L _PK_L_(0x12, 0x05) ++#define REG_SC_BK12_05_H _PK_H_(0x12, 0x05) ++#define REG_SC_BK12_06_L _PK_L_(0x12, 0x06) ++#define REG_SC_BK12_06_H _PK_H_(0x12, 0x06) ++#define REG_SC_BK12_07_L _PK_L_(0x12, 0x07) ++#define REG_SC_BK12_07_H _PK_H_(0x12, 0x07) ++#define REG_SC_BK12_08_L _PK_L_(0x12, 0x08) ++#define REG_SC_BK12_08_H _PK_H_(0x12, 0x08) ++#define REG_SC_BK12_09_L _PK_L_(0x12, 0x09) ++#define REG_SC_BK12_09_H _PK_H_(0x12, 0x09) ++#define REG_SC_BK12_0A_L _PK_L_(0x12, 0x0A) ++#define REG_SC_BK12_0A_H _PK_H_(0x12, 0x0A) ++#define REG_SC_BK12_0B_L _PK_L_(0x12, 0x0B) ++#define REG_SC_BK12_0B_H _PK_H_(0x12, 0x0B) ++#define REG_SC_BK12_0C_L _PK_L_(0x12, 0x0C) ++#define REG_SC_BK12_0C_H _PK_H_(0x12, 0x0C) ++#define REG_SC_BK12_0D_L _PK_L_(0x12, 0x0D) ++#define REG_SC_BK12_0D_H _PK_H_(0x12, 0x0D) ++#define REG_SC_BK12_0E_L _PK_L_(0x12, 0x0E) ++#define REG_SC_BK12_0E_H _PK_H_(0x12, 0x0E) ++#define REG_SC_BK12_0F_L _PK_L_(0x12, 0x0F) ++#define REG_SC_BK12_0F_H _PK_H_(0x12, 0x0F) ++#define REG_SC_BK12_10_L _PK_L_(0x12, 0x10) ++#define REG_SC_BK12_10_H _PK_H_(0x12, 0x10) ++#define REG_SC_BK12_11_L _PK_L_(0x12, 0x11) ++#define REG_SC_BK12_11_H _PK_H_(0x12, 0x11) ++#define REG_SC_BK12_12_L _PK_L_(0x12, 0x12) ++#define REG_SC_BK12_12_H _PK_H_(0x12, 0x12) ++#define REG_SC_BK12_13_L _PK_L_(0x12, 0x13) ++#define REG_SC_BK12_13_H _PK_H_(0x12, 0x13) ++#define REG_SC_BK12_14_L _PK_L_(0x12, 0x14) ++#define REG_SC_BK12_14_H _PK_H_(0x12, 0x14) ++#define REG_SC_BK12_15_L _PK_L_(0x12, 0x15) ++#define REG_SC_BK12_15_H _PK_H_(0x12, 0x15) ++#define REG_SC_BK12_16_L _PK_L_(0x12, 0x16) ++#define REG_SC_BK12_16_H _PK_H_(0x12, 0x16) ++#define REG_SC_BK12_17_L _PK_L_(0x12, 0x17) ++#define REG_SC_BK12_17_H _PK_H_(0x12, 0x17) ++#define REG_SC_BK12_18_L _PK_L_(0x12, 0x18) ++#define REG_SC_BK12_18_H _PK_H_(0x12, 0x18) ++#define REG_SC_BK12_19_L _PK_L_(0x12, 0x19) ++#define REG_SC_BK12_19_H _PK_H_(0x12, 0x19) ++#define REG_SC_BK12_1A_L _PK_L_(0x12, 0x1A) ++#define REG_SC_BK12_1A_H _PK_H_(0x12, 0x1A) ++#define REG_SC_BK12_1B_L _PK_L_(0x12, 0x1B) ++#define REG_SC_BK12_1B_H _PK_H_(0x12, 0x1B) ++#define REG_SC_BK12_1C_L _PK_L_(0x12, 0x1C) ++#define REG_SC_BK12_1C_H _PK_H_(0x12, 0x1C) ++#define REG_SC_BK12_1D_L _PK_L_(0x12, 0x1D) ++#define REG_SC_BK12_1D_H _PK_H_(0x12, 0x1D) ++#define REG_SC_BK12_1E_L _PK_L_(0x12, 0x1E) ++#define REG_SC_BK12_1E_H _PK_H_(0x12, 0x1E) ++#define REG_SC_BK12_1F_L _PK_L_(0x12, 0x1F) ++#define REG_SC_BK12_1F_H _PK_H_(0x12, 0x1F) ++#define REG_SC_BK12_20_L _PK_L_(0x12, 0x20) ++#define REG_SC_BK12_20_H _PK_H_(0x12, 0x20) ++#define REG_SC_BK12_21_L _PK_L_(0x12, 0x21) ++#define REG_SC_BK12_21_H _PK_H_(0x12, 0x21) ++#define REG_SC_BK12_22_L _PK_L_(0x12, 0x22) ++#define REG_SC_BK12_22_H _PK_H_(0x12, 0x22) ++#define REG_SC_BK12_23_L _PK_L_(0x12, 0x23) ++#define REG_SC_BK12_23_H _PK_H_(0x12, 0x23) ++#define REG_SC_BK12_24_L _PK_L_(0x12, 0x24) ++#define REG_SC_BK12_24_H _PK_H_(0x12, 0x24) ++#define REG_SC_BK12_25_L _PK_L_(0x12, 0x25) ++#define REG_SC_BK12_25_H _PK_H_(0x12, 0x25) ++#define REG_SC_BK12_26_L _PK_L_(0x12, 0x26) ++#define REG_SC_BK12_26_H _PK_H_(0x12, 0x26) ++#define REG_SC_BK12_27_L _PK_L_(0x12, 0x27) ++#define REG_SC_BK12_27_H _PK_H_(0x12, 0x27) ++#define REG_SC_BK12_28_L _PK_L_(0x12, 0x28) ++#define REG_SC_BK12_28_H _PK_H_(0x12, 0x28) ++#define REG_SC_BK12_29_L _PK_L_(0x12, 0x29) ++#define REG_SC_BK12_29_H _PK_H_(0x12, 0x29) ++#define REG_SC_BK12_2A_L _PK_L_(0x12, 0x2A) ++#define REG_SC_BK12_2A_H _PK_H_(0x12, 0x2A) ++#define REG_SC_BK12_2B_L _PK_L_(0x12, 0x2B) ++#define REG_SC_BK12_2B_H _PK_H_(0x12, 0x2B) ++#define REG_SC_BK12_2C_L _PK_L_(0x12, 0x2C) ++#define REG_SC_BK12_2C_H _PK_H_(0x12, 0x2C) ++#define REG_SC_BK12_2D_L _PK_L_(0x12, 0x2D) ++#define REG_SC_BK12_2D_H _PK_H_(0x12, 0x2D) ++#define REG_SC_BK12_2E_L _PK_L_(0x12, 0x2E) ++#define REG_SC_BK12_2E_H _PK_H_(0x12, 0x2E) ++#define REG_SC_BK12_2F_L _PK_L_(0x12, 0x2F) ++#define REG_SC_BK12_2F_H _PK_H_(0x12, 0x2F) ++#define REG_SC_BK12_30_L _PK_L_(0x12, 0x30) ++#define REG_SC_BK12_30_H _PK_H_(0x12, 0x30) ++#define REG_SC_BK12_31_L _PK_L_(0x12, 0x31) ++#define REG_SC_BK12_31_H _PK_H_(0x12, 0x31) ++#define REG_SC_BK12_32_L _PK_L_(0x12, 0x32) ++#define REG_SC_BK12_32_H _PK_H_(0x12, 0x32) ++#define REG_SC_BK12_33_L _PK_L_(0x12, 0x33) ++#define REG_SC_BK12_33_H _PK_H_(0x12, 0x33) ++#define REG_SC_BK12_34_L _PK_L_(0x12, 0x34) ++#define REG_SC_BK12_34_H _PK_H_(0x12, 0x34) ++#define REG_SC_BK12_35_L _PK_L_(0x12, 0x35) ++#define REG_SC_BK12_35_H _PK_H_(0x12, 0x35) ++#define REG_SC_BK12_36_L _PK_L_(0x12, 0x36) ++#define REG_SC_BK12_36_H _PK_H_(0x12, 0x36) ++#define REG_SC_BK12_37_L _PK_L_(0x12, 0x37) ++#define REG_SC_BK12_37_H _PK_H_(0x12, 0x37) ++#define REG_SC_BK12_38_L _PK_L_(0x12, 0x38) ++#define REG_SC_BK12_38_H _PK_H_(0x12, 0x38) ++#define REG_SC_BK12_39_L _PK_L_(0x12, 0x39) ++#define REG_SC_BK12_39_H _PK_H_(0x12, 0x39) ++#define REG_SC_BK12_3A_L _PK_L_(0x12, 0x3A) ++#define REG_SC_BK12_3A_H _PK_H_(0x12, 0x3A) ++#define REG_SC_BK12_3B_L _PK_L_(0x12, 0x3B) ++#define REG_SC_BK12_3B_H _PK_H_(0x12, 0x3B) ++#define REG_SC_BK12_3C_L _PK_L_(0x12, 0x3C) ++#define REG_SC_BK12_3C_H _PK_H_(0x12, 0x3C) ++#define REG_SC_BK12_3D_L _PK_L_(0x12, 0x3D) ++#define REG_SC_BK12_3D_H _PK_H_(0x12, 0x3D) ++#define REG_SC_BK12_3E_L _PK_L_(0x12, 0x3E) ++#define REG_SC_BK12_3E_H _PK_H_(0x12, 0x3E) ++#define REG_SC_BK12_3F_L _PK_L_(0x12, 0x3F) ++#define REG_SC_BK12_3F_H _PK_H_(0x12, 0x3F) ++#define REG_SC_BK12_40_L _PK_L_(0x12, 0x40) ++#define REG_SC_BK12_40_H _PK_H_(0x12, 0x40) ++#define REG_SC_BK12_41_L _PK_L_(0x12, 0x41) ++#define REG_SC_BK12_41_H _PK_H_(0x12, 0x41) ++#define REG_SC_BK12_42_L _PK_L_(0x12, 0x42) ++#define REG_SC_BK12_42_H _PK_H_(0x12, 0x42) ++#define REG_SC_BK12_43_L _PK_L_(0x12, 0x43) ++#define REG_SC_BK12_43_H _PK_H_(0x12, 0x43) ++#define REG_SC_BK12_44_L _PK_L_(0x12, 0x44) ++#define REG_SC_BK12_44_H _PK_H_(0x12, 0x44) ++#define REG_SC_BK12_45_L _PK_L_(0x12, 0x45) ++#define REG_SC_BK12_45_H _PK_H_(0x12, 0x45) ++#define REG_SC_BK12_46_L _PK_L_(0x12, 0x46) ++#define REG_SC_BK12_46_H _PK_H_(0x12, 0x46) ++#define REG_SC_BK12_47_L _PK_L_(0x12, 0x47) ++#define REG_SC_BK12_47_H _PK_H_(0x12, 0x47) ++#define REG_SC_BK12_48_L _PK_L_(0x12, 0x48) ++#define REG_SC_BK12_48_H _PK_H_(0x12, 0x48) ++#define REG_SC_BK12_49_L _PK_L_(0x12, 0x49) ++#define REG_SC_BK12_49_H _PK_H_(0x12, 0x49) ++#define REG_SC_BK12_4A_L _PK_L_(0x12, 0x4A) ++#define REG_SC_BK12_4A_H _PK_H_(0x12, 0x4A) ++#define REG_SC_BK12_4B_L _PK_L_(0x12, 0x4B) ++#define REG_SC_BK12_4B_H _PK_H_(0x12, 0x4B) ++#define REG_SC_BK12_4C_L _PK_L_(0x12, 0x4C) ++#define REG_SC_BK12_4C_H _PK_H_(0x12, 0x4C) ++#define REG_SC_BK12_4D_L _PK_L_(0x12, 0x4D) ++#define REG_SC_BK12_4D_H _PK_H_(0x12, 0x4D) ++#define REG_SC_BK12_4E_L _PK_L_(0x12, 0x4E) ++#define REG_SC_BK12_4E_H _PK_H_(0x12, 0x4E) ++#define REG_SC_BK12_4F_L _PK_L_(0x12, 0x4F) ++#define REG_SC_BK12_4F_H _PK_H_(0x12, 0x4F) ++#define REG_SC_BK12_50_L _PK_L_(0x12, 0x50) ++#define REG_SC_BK12_50_H _PK_H_(0x12, 0x50) ++#define REG_SC_BK12_51_L _PK_L_(0x12, 0x51) ++#define REG_SC_BK12_51_H _PK_H_(0x12, 0x51) ++#define REG_SC_BK12_52_L _PK_L_(0x12, 0x52) ++#define REG_SC_BK12_52_H _PK_H_(0x12, 0x52) ++#define REG_SC_BK12_53_L _PK_L_(0x12, 0x53) ++#define REG_SC_BK12_53_H _PK_H_(0x12, 0x53) ++#define REG_SC_BK12_54_L _PK_L_(0x12, 0x54) ++#define REG_SC_BK12_54_H _PK_H_(0x12, 0x54) ++#define REG_SC_BK12_55_L _PK_L_(0x12, 0x55) ++#define REG_SC_BK12_55_H _PK_H_(0x12, 0x55) ++#define REG_SC_BK12_56_L _PK_L_(0x12, 0x56) ++#define REG_SC_BK12_56_H _PK_H_(0x12, 0x56) ++#define REG_SC_BK12_57_L _PK_L_(0x12, 0x57) ++#define REG_SC_BK12_57_H _PK_H_(0x12, 0x57) ++#define REG_SC_BK12_58_L _PK_L_(0x12, 0x58) ++#define REG_SC_BK12_58_H _PK_H_(0x12, 0x58) ++#define REG_SC_BK12_59_L _PK_L_(0x12, 0x59) ++#define REG_SC_BK12_59_H _PK_H_(0x12, 0x59) ++#define REG_SC_BK12_5A_L _PK_L_(0x12, 0x5A) ++#define REG_SC_BK12_5A_H _PK_H_(0x12, 0x5A) ++#define REG_SC_BK12_5B_L _PK_L_(0x12, 0x5B) ++#define REG_SC_BK12_5B_H _PK_H_(0x12, 0x5B) ++#define REG_SC_BK12_5C_L _PK_L_(0x12, 0x5C) ++#define REG_SC_BK12_5C_H _PK_H_(0x12, 0x5C) ++#define REG_SC_BK12_5D_L _PK_L_(0x12, 0x5D) ++#define REG_SC_BK12_5D_H _PK_H_(0x12, 0x5D) ++#define REG_SC_BK12_5E_L _PK_L_(0x12, 0x5E) ++#define REG_SC_BK12_5E_H _PK_H_(0x12, 0x5E) ++#define REG_SC_BK12_5F_L _PK_L_(0x12, 0x5F) ++#define REG_SC_BK12_5F_H _PK_H_(0x12, 0x5F) ++#define REG_SC_BK12_60_L _PK_L_(0x12, 0x60) ++#define REG_SC_BK12_60_H _PK_H_(0x12, 0x60) ++#define REG_SC_BK12_61_L _PK_L_(0x12, 0x61) ++#define REG_SC_BK12_61_H _PK_H_(0x12, 0x61) ++#define REG_SC_BK12_62_L _PK_L_(0x12, 0x62) ++#define REG_SC_BK12_62_H _PK_H_(0x12, 0x62) ++#define REG_SC_BK12_63_L _PK_L_(0x12, 0x63) ++#define REG_SC_BK12_63_H _PK_H_(0x12, 0x63) ++#define REG_SC_BK12_64_L _PK_L_(0x12, 0x64) ++#define REG_SC_BK12_64_H _PK_H_(0x12, 0x64) ++#define REG_SC_BK12_65_L _PK_L_(0x12, 0x65) ++#define REG_SC_BK12_65_H _PK_H_(0x12, 0x65) ++#define REG_SC_BK12_66_L _PK_L_(0x12, 0x66) ++#define REG_SC_BK12_66_H _PK_H_(0x12, 0x66) ++#define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) ++#define REG_SC_BK12_67_H _PK_H_(0x12, 0x67) ++#define REG_SC_BK12_68_L _PK_L_(0x12, 0x68) ++#define REG_SC_BK12_68_H _PK_H_(0x12, 0x68) ++#define REG_SC_BK12_69_L _PK_L_(0x12, 0x69) ++#define REG_SC_BK12_69_H _PK_H_(0x12, 0x69) ++#define REG_SC_BK12_6A_L _PK_L_(0x12, 0x6A) ++#define REG_SC_BK12_6A_H _PK_H_(0x12, 0x6A) ++#define REG_SC_BK12_6B_L _PK_L_(0x12, 0x6B) ++#define REG_SC_BK12_6B_H _PK_H_(0x12, 0x6B) ++#define REG_SC_BK12_6C_L _PK_L_(0x12, 0x6C) ++#define REG_SC_BK12_6C_H _PK_H_(0x12, 0x6C) ++#define REG_SC_BK12_6D_L _PK_L_(0x12, 0x6D) ++#define REG_SC_BK12_6D_H _PK_H_(0x12, 0x6D) ++#define REG_SC_BK12_6E_L _PK_L_(0x12, 0x6E) ++#define REG_SC_BK12_6E_H _PK_H_(0x12, 0x6E) ++#define REG_SC_BK12_6F_L _PK_L_(0x12, 0x6F) ++#define REG_SC_BK12_6F_H _PK_H_(0x12, 0x6F) ++#define REG_SC_BK12_70_L _PK_L_(0x12, 0x70) ++#define REG_SC_BK12_70_H _PK_H_(0x12, 0x70) ++#define REG_SC_BK12_71_L _PK_L_(0x12, 0x71) ++#define REG_SC_BK12_71_H _PK_H_(0x12, 0x71) ++#define REG_SC_BK12_72_L _PK_L_(0x12, 0x72) ++#define REG_SC_BK12_72_H _PK_H_(0x12, 0x72) ++#define REG_SC_BK12_73_L _PK_L_(0x12, 0x73) ++#define REG_SC_BK12_73_H _PK_H_(0x12, 0x73) ++#define REG_SC_BK12_74_L _PK_L_(0x12, 0x74) ++#define REG_SC_BK12_74_H _PK_H_(0x12, 0x74) ++#define REG_SC_BK12_75_L _PK_L_(0x12, 0x75) ++#define REG_SC_BK12_75_H _PK_H_(0x12, 0x75) ++#define REG_SC_BK12_76_L _PK_L_(0x12, 0x76) ++#define REG_SC_BK12_76_H _PK_H_(0x12, 0x76) ++#define REG_SC_BK12_77_L _PK_L_(0x12, 0x77) ++#define REG_SC_BK12_77_H _PK_H_(0x12, 0x77) ++#define REG_SC_BK12_78_L _PK_L_(0x12, 0x78) ++#define REG_SC_BK12_78_H _PK_H_(0x12, 0x78) ++#define REG_SC_BK12_79_L _PK_L_(0x12, 0x79) ++#define REG_SC_BK12_79_H _PK_H_(0x12, 0x79) ++#define REG_SC_BK12_7A_L _PK_L_(0x12, 0x7A) ++#define REG_SC_BK12_7A_H _PK_H_(0x12, 0x7A) ++#define REG_SC_BK12_7B_L _PK_L_(0x12, 0x7B) ++#define REG_SC_BK12_7B_H _PK_H_(0x12, 0x7B) ++#define REG_SC_BK12_7C_L _PK_L_(0x12, 0x7C) ++#define REG_SC_BK12_7C_H _PK_H_(0x12, 0x7C) ++#define REG_SC_BK12_7D_L _PK_L_(0x12, 0x7D) ++#define REG_SC_BK12_7D_H _PK_H_(0x12, 0x7D) ++#define REG_SC_BK12_7E_L _PK_L_(0x12, 0x7E) ++#define REG_SC_BK12_7E_H _PK_H_(0x12, 0x7E) ++#define REG_SC_BK12_7F_L _PK_L_(0x12, 0x7F) ++#define REG_SC_BK12_7F_H _PK_H_(0x12, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK13_00_L _PK_L_(0x13, 0x00) ++#define REG_SC_BK13_00_H _PK_H_(0x13, 0x00) ++#define REG_SC_BK13_01_L _PK_L_(0x13, 0x01) ++#define REG_SC_BK13_01_H _PK_H_(0x13, 0x01) ++#define REG_SC_BK13_02_L _PK_L_(0x13, 0x02) ++#define REG_SC_BK13_02_H _PK_H_(0x13, 0x02) ++#define REG_SC_BK13_03_L _PK_L_(0x13, 0x03) ++#define REG_SC_BK13_03_H _PK_H_(0x13, 0x03) ++#define REG_SC_BK13_04_L _PK_L_(0x13, 0x04) ++#define REG_SC_BK13_04_H _PK_H_(0x13, 0x04) ++#define REG_SC_BK13_05_L _PK_L_(0x13, 0x05) ++#define REG_SC_BK13_05_H _PK_H_(0x13, 0x05) ++#define REG_SC_BK13_06_L _PK_L_(0x13, 0x06) ++#define REG_SC_BK13_06_H _PK_H_(0x13, 0x06) ++#define REG_SC_BK13_07_L _PK_L_(0x13, 0x07) ++#define REG_SC_BK13_07_H _PK_H_(0x13, 0x07) ++#define REG_SC_BK13_08_L _PK_L_(0x13, 0x08) ++#define REG_SC_BK13_08_H _PK_H_(0x13, 0x08) ++#define REG_SC_BK13_09_L _PK_L_(0x13, 0x09) ++#define REG_SC_BK13_09_H _PK_H_(0x13, 0x09) ++#define REG_SC_BK13_0A_L _PK_L_(0x13, 0x0A) ++#define REG_SC_BK13_0A_H _PK_H_(0x13, 0x0A) ++#define REG_SC_BK13_0B_L _PK_L_(0x13, 0x0B) ++#define REG_SC_BK13_0B_H _PK_H_(0x13, 0x0B) ++#define REG_SC_BK13_0C_L _PK_L_(0x13, 0x0C) ++#define REG_SC_BK13_0C_H _PK_H_(0x13, 0x0C) ++#define REG_SC_BK13_0D_L _PK_L_(0x13, 0x0D) ++#define REG_SC_BK13_0D_H _PK_H_(0x13, 0x0D) ++#define REG_SC_BK13_0E_L _PK_L_(0x13, 0x0E) ++#define REG_SC_BK13_0E_H _PK_H_(0x13, 0x0E) ++#define REG_SC_BK13_0F_L _PK_L_(0x13, 0x0F) ++#define REG_SC_BK13_0F_H _PK_H_(0x13, 0x0F) ++#define REG_SC_BK13_10_L _PK_L_(0x13, 0x10) ++#define REG_SC_BK13_10_H _PK_H_(0x13, 0x10) ++#define REG_SC_BK13_11_L _PK_L_(0x13, 0x11) ++#define REG_SC_BK13_11_H _PK_H_(0x13, 0x11) ++#define REG_SC_BK13_12_L _PK_L_(0x13, 0x12) ++#define REG_SC_BK13_12_H _PK_H_(0x13, 0x12) ++#define REG_SC_BK13_13_L _PK_L_(0x13, 0x13) ++#define REG_SC_BK13_13_H _PK_H_(0x13, 0x13) ++#define REG_SC_BK13_14_L _PK_L_(0x13, 0x14) ++#define REG_SC_BK13_14_H _PK_H_(0x13, 0x14) ++#define REG_SC_BK13_15_L _PK_L_(0x13, 0x15) ++#define REG_SC_BK13_15_H _PK_H_(0x13, 0x15) ++#define REG_SC_BK13_16_L _PK_L_(0x13, 0x16) ++#define REG_SC_BK13_16_H _PK_H_(0x13, 0x16) ++#define REG_SC_BK13_17_L _PK_L_(0x13, 0x17) ++#define REG_SC_BK13_17_H _PK_H_(0x13, 0x17) ++#define REG_SC_BK13_18_L _PK_L_(0x13, 0x18) ++#define REG_SC_BK13_18_H _PK_H_(0x13, 0x18) ++#define REG_SC_BK13_19_L _PK_L_(0x13, 0x19) ++#define REG_SC_BK13_19_H _PK_H_(0x13, 0x19) ++#define REG_SC_BK13_1A_L _PK_L_(0x13, 0x1A) ++#define REG_SC_BK13_1A_H _PK_H_(0x13, 0x1A) ++#define REG_SC_BK13_1B_L _PK_L_(0x13, 0x1B) ++#define REG_SC_BK13_1B_H _PK_H_(0x13, 0x1B) ++#define REG_SC_BK13_1C_L _PK_L_(0x13, 0x1C) ++#define REG_SC_BK13_1C_H _PK_H_(0x13, 0x1C) ++#define REG_SC_BK13_1D_L _PK_L_(0x13, 0x1D) ++#define REG_SC_BK13_1D_H _PK_H_(0x13, 0x1D) ++#define REG_SC_BK13_1E_L _PK_L_(0x13, 0x1E) ++#define REG_SC_BK13_1E_H _PK_H_(0x13, 0x1E) ++#define REG_SC_BK13_1F_L _PK_L_(0x13, 0x1F) ++#define REG_SC_BK13_1F_H _PK_H_(0x13, 0x1F) ++#define REG_SC_BK13_20_L _PK_L_(0x13, 0x20) ++#define REG_SC_BK13_20_H _PK_H_(0x13, 0x20) ++#define REG_SC_BK13_21_L _PK_L_(0x13, 0x21) ++#define REG_SC_BK13_21_H _PK_H_(0x13, 0x21) ++#define REG_SC_BK13_22_L _PK_L_(0x13, 0x22) ++#define REG_SC_BK13_22_H _PK_H_(0x13, 0x22) ++#define REG_SC_BK13_23_L _PK_L_(0x13, 0x23) ++#define REG_SC_BK13_23_H _PK_H_(0x13, 0x23) ++#define REG_SC_BK13_24_L _PK_L_(0x13, 0x24) ++#define REG_SC_BK13_24_H _PK_H_(0x13, 0x24) ++#define REG_SC_BK13_25_L _PK_L_(0x13, 0x25) ++#define REG_SC_BK13_25_H _PK_H_(0x13, 0x25) ++#define REG_SC_BK13_26_L _PK_L_(0x13, 0x26) ++#define REG_SC_BK13_26_H _PK_H_(0x13, 0x26) ++#define REG_SC_BK13_27_L _PK_L_(0x13, 0x27) ++#define REG_SC_BK13_27_H _PK_H_(0x13, 0x27) ++#define REG_SC_BK13_28_L _PK_L_(0x13, 0x28) ++#define REG_SC_BK13_28_H _PK_H_(0x13, 0x28) ++#define REG_SC_BK13_29_L _PK_L_(0x13, 0x29) ++#define REG_SC_BK13_29_H _PK_H_(0x13, 0x29) ++#define REG_SC_BK13_2A_L _PK_L_(0x13, 0x2A) ++#define REG_SC_BK13_2A_H _PK_H_(0x13, 0x2A) ++#define REG_SC_BK13_2B_L _PK_L_(0x13, 0x2B) ++#define REG_SC_BK13_2B_H _PK_H_(0x13, 0x2B) ++#define REG_SC_BK13_2C_L _PK_L_(0x13, 0x2C) ++#define REG_SC_BK13_2C_H _PK_H_(0x13, 0x2C) ++#define REG_SC_BK13_2D_L _PK_L_(0x13, 0x2D) ++#define REG_SC_BK13_2D_H _PK_H_(0x13, 0x2D) ++#define REG_SC_BK13_2E_L _PK_L_(0x13, 0x2E) ++#define REG_SC_BK13_2E_H _PK_H_(0x13, 0x2E) ++#define REG_SC_BK13_2F_L _PK_L_(0x13, 0x2F) ++#define REG_SC_BK13_2F_H _PK_H_(0x13, 0x2F) ++#define REG_SC_BK13_30_L _PK_L_(0x13, 0x30) ++#define REG_SC_BK13_30_H _PK_H_(0x13, 0x30) ++#define REG_SC_BK13_31_L _PK_L_(0x13, 0x31) ++#define REG_SC_BK13_31_H _PK_H_(0x13, 0x31) ++#define REG_SC_BK13_32_L _PK_L_(0x13, 0x32) ++#define REG_SC_BK13_32_H _PK_H_(0x13, 0x32) ++#define REG_SC_BK13_33_L _PK_L_(0x13, 0x33) ++#define REG_SC_BK13_33_H _PK_H_(0x13, 0x33) ++#define REG_SC_BK13_34_L _PK_L_(0x13, 0x34) ++#define REG_SC_BK13_34_H _PK_H_(0x13, 0x34) ++#define REG_SC_BK13_35_L _PK_L_(0x13, 0x35) ++#define REG_SC_BK13_35_H _PK_H_(0x13, 0x35) ++#define REG_SC_BK13_36_L _PK_L_(0x13, 0x36) ++#define REG_SC_BK13_36_H _PK_H_(0x13, 0x36) ++#define REG_SC_BK13_37_L _PK_L_(0x13, 0x37) ++#define REG_SC_BK13_37_H _PK_H_(0x13, 0x37) ++#define REG_SC_BK13_38_L _PK_L_(0x13, 0x38) ++#define REG_SC_BK13_38_H _PK_H_(0x13, 0x38) ++#define REG_SC_BK13_39_L _PK_L_(0x13, 0x39) ++#define REG_SC_BK13_39_H _PK_H_(0x13, 0x39) ++#define REG_SC_BK13_3A_L _PK_L_(0x13, 0x3A) ++#define REG_SC_BK13_3A_H _PK_H_(0x13, 0x3A) ++#define REG_SC_BK13_3B_L _PK_L_(0x13, 0x3B) ++#define REG_SC_BK13_3B_H _PK_H_(0x13, 0x3B) ++#define REG_SC_BK13_3C_L _PK_L_(0x13, 0x3C) ++#define REG_SC_BK13_3C_H _PK_H_(0x13, 0x3C) ++#define REG_SC_BK13_3D_L _PK_L_(0x13, 0x3D) ++#define REG_SC_BK13_3D_H _PK_H_(0x13, 0x3D) ++#define REG_SC_BK13_3E_L _PK_L_(0x13, 0x3E) ++#define REG_SC_BK13_3E_H _PK_H_(0x13, 0x3E) ++#define REG_SC_BK13_3F_L _PK_L_(0x13, 0x3F) ++#define REG_SC_BK13_3F_H _PK_H_(0x13, 0x3F) ++#define REG_SC_BK13_40_L _PK_L_(0x13, 0x40) ++#define REG_SC_BK13_40_H _PK_H_(0x13, 0x40) ++#define REG_SC_BK13_41_L _PK_L_(0x13, 0x41) ++#define REG_SC_BK13_41_H _PK_H_(0x13, 0x41) ++#define REG_SC_BK13_42_L _PK_L_(0x13, 0x42) ++#define REG_SC_BK13_42_H _PK_H_(0x13, 0x42) ++#define REG_SC_BK13_43_L _PK_L_(0x13, 0x43) ++#define REG_SC_BK13_43_H _PK_H_(0x13, 0x43) ++#define REG_SC_BK13_44_L _PK_L_(0x13, 0x44) ++#define REG_SC_BK13_44_H _PK_H_(0x13, 0x44) ++#define REG_SC_BK13_45_L _PK_L_(0x13, 0x45) ++#define REG_SC_BK13_45_H _PK_H_(0x13, 0x45) ++#define REG_SC_BK13_46_L _PK_L_(0x13, 0x46) ++#define REG_SC_BK13_46_H _PK_H_(0x13, 0x46) ++#define REG_SC_BK13_47_L _PK_L_(0x13, 0x47) ++#define REG_SC_BK13_47_H _PK_H_(0x13, 0x47) ++#define REG_SC_BK13_48_L _PK_L_(0x13, 0x48) ++#define REG_SC_BK13_48_H _PK_H_(0x13, 0x48) ++#define REG_SC_BK13_49_L _PK_L_(0x13, 0x49) ++#define REG_SC_BK13_49_H _PK_H_(0x13, 0x49) ++#define REG_SC_BK13_4A_L _PK_L_(0x13, 0x4A) ++#define REG_SC_BK13_4A_H _PK_H_(0x13, 0x4A) ++#define REG_SC_BK13_4B_L _PK_L_(0x13, 0x4B) ++#define REG_SC_BK13_4B_H _PK_H_(0x13, 0x4B) ++#define REG_SC_BK13_4C_L _PK_L_(0x13, 0x4C) ++#define REG_SC_BK13_4C_H _PK_H_(0x13, 0x4C) ++#define REG_SC_BK13_4D_L _PK_L_(0x13, 0x4D) ++#define REG_SC_BK13_4D_H _PK_H_(0x13, 0x4D) ++#define REG_SC_BK13_4E_L _PK_L_(0x13, 0x4E) ++#define REG_SC_BK13_4E_H _PK_H_(0x13, 0x4E) ++#define REG_SC_BK13_4F_L _PK_L_(0x13, 0x4F) ++#define REG_SC_BK13_4F_H _PK_H_(0x13, 0x4F) ++#define REG_SC_BK13_50_L _PK_L_(0x13, 0x50) ++#define REG_SC_BK13_50_H _PK_H_(0x13, 0x50) ++#define REG_SC_BK13_51_L _PK_L_(0x13, 0x51) ++#define REG_SC_BK13_51_H _PK_H_(0x13, 0x51) ++#define REG_SC_BK13_52_L _PK_L_(0x13, 0x52) ++#define REG_SC_BK13_52_H _PK_H_(0x13, 0x52) ++#define REG_SC_BK13_53_L _PK_L_(0x13, 0x53) ++#define REG_SC_BK13_53_H _PK_H_(0x13, 0x53) ++#define REG_SC_BK13_54_L _PK_L_(0x13, 0x54) ++#define REG_SC_BK13_54_H _PK_H_(0x13, 0x54) ++#define REG_SC_BK13_55_L _PK_L_(0x13, 0x55) ++#define REG_SC_BK13_55_H _PK_H_(0x13, 0x55) ++#define REG_SC_BK13_56_L _PK_L_(0x13, 0x56) ++#define REG_SC_BK13_56_H _PK_H_(0x13, 0x56) ++#define REG_SC_BK13_57_L _PK_L_(0x13, 0x57) ++#define REG_SC_BK13_57_H _PK_H_(0x13, 0x57) ++#define REG_SC_BK13_58_L _PK_L_(0x13, 0x58) ++#define REG_SC_BK13_58_H _PK_H_(0x13, 0x58) ++#define REG_SC_BK13_59_L _PK_L_(0x13, 0x59) ++#define REG_SC_BK13_59_H _PK_H_(0x13, 0x59) ++#define REG_SC_BK13_5A_L _PK_L_(0x13, 0x5A) ++#define REG_SC_BK13_5A_H _PK_H_(0x13, 0x5A) ++#define REG_SC_BK13_5B_L _PK_L_(0x13, 0x5B) ++#define REG_SC_BK13_5B_H _PK_H_(0x13, 0x5B) ++#define REG_SC_BK13_5C_L _PK_L_(0x13, 0x5C) ++#define REG_SC_BK13_5C_H _PK_H_(0x13, 0x5C) ++#define REG_SC_BK13_5D_L _PK_L_(0x13, 0x5D) ++#define REG_SC_BK13_5D_H _PK_H_(0x13, 0x5D) ++#define REG_SC_BK13_5E_L _PK_L_(0x13, 0x5E) ++#define REG_SC_BK13_5E_H _PK_H_(0x13, 0x5E) ++#define REG_SC_BK13_5F_L _PK_L_(0x13, 0x5F) ++#define REG_SC_BK13_5F_H _PK_H_(0x13, 0x5F) ++#define REG_SC_BK13_60_L _PK_L_(0x13, 0x60) ++#define REG_SC_BK13_60_H _PK_H_(0x13, 0x60) ++#define REG_SC_BK13_61_L _PK_L_(0x13, 0x61) ++#define REG_SC_BK13_61_H _PK_H_(0x13, 0x61) ++#define REG_SC_BK13_62_L _PK_L_(0x13, 0x62) ++#define REG_SC_BK13_62_H _PK_H_(0x13, 0x62) ++#define REG_SC_BK13_63_L _PK_L_(0x13, 0x63) ++#define REG_SC_BK13_63_H _PK_H_(0x13, 0x63) ++#define REG_SC_BK13_64_L _PK_L_(0x13, 0x64) ++#define REG_SC_BK13_64_H _PK_H_(0x13, 0x64) ++#define REG_SC_BK13_65_L _PK_L_(0x13, 0x65) ++#define REG_SC_BK13_65_H _PK_H_(0x13, 0x65) ++#define REG_SC_BK13_66_L _PK_L_(0x13, 0x66) ++#define REG_SC_BK13_66_H _PK_H_(0x13, 0x66) ++#define REG_SC_BK13_67_L _PK_L_(0x13, 0x67) ++#define REG_SC_BK13_67_H _PK_H_(0x13, 0x67) ++#define REG_SC_BK13_68_L _PK_L_(0x13, 0x68) ++#define REG_SC_BK13_68_H _PK_H_(0x13, 0x68) ++#define REG_SC_BK13_69_L _PK_L_(0x13, 0x69) ++#define REG_SC_BK13_69_H _PK_H_(0x13, 0x69) ++#define REG_SC_BK13_6A_L _PK_L_(0x13, 0x6A) ++#define REG_SC_BK13_6A_H _PK_H_(0x13, 0x6A) ++#define REG_SC_BK13_6B_L _PK_L_(0x13, 0x6B) ++#define REG_SC_BK13_6B_H _PK_H_(0x13, 0x6B) ++#define REG_SC_BK13_6C_L _PK_L_(0x13, 0x6C) ++#define REG_SC_BK13_6C_H _PK_H_(0x13, 0x6C) ++#define REG_SC_BK13_6D_L _PK_L_(0x13, 0x6D) ++#define REG_SC_BK13_6D_H _PK_H_(0x13, 0x6D) ++#define REG_SC_BK13_6E_L _PK_L_(0x13, 0x6E) ++#define REG_SC_BK13_6E_H _PK_H_(0x13, 0x6E) ++#define REG_SC_BK13_6F_L _PK_L_(0x13, 0x6F) ++#define REG_SC_BK13_6F_H _PK_H_(0x13, 0x6F) ++#define REG_SC_BK13_70_L _PK_L_(0x13, 0x70) ++#define REG_SC_BK13_70_H _PK_H_(0x13, 0x70) ++#define REG_SC_BK13_71_L _PK_L_(0x13, 0x71) ++#define REG_SC_BK13_71_H _PK_H_(0x13, 0x71) ++#define REG_SC_BK13_72_L _PK_L_(0x13, 0x72) ++#define REG_SC_BK13_72_H _PK_H_(0x13, 0x72) ++#define REG_SC_BK13_73_L _PK_L_(0x13, 0x73) ++#define REG_SC_BK13_73_H _PK_H_(0x13, 0x73) ++#define REG_SC_BK13_74_L _PK_L_(0x13, 0x74) ++#define REG_SC_BK13_74_H _PK_H_(0x13, 0x74) ++#define REG_SC_BK13_75_L _PK_L_(0x13, 0x75) ++#define REG_SC_BK13_75_H _PK_H_(0x13, 0x75) ++#define REG_SC_BK13_76_L _PK_L_(0x13, 0x76) ++#define REG_SC_BK13_76_H _PK_H_(0x13, 0x76) ++#define REG_SC_BK13_77_L _PK_L_(0x13, 0x77) ++#define REG_SC_BK13_77_H _PK_H_(0x13, 0x77) ++#define REG_SC_BK13_78_L _PK_L_(0x13, 0x78) ++#define REG_SC_BK13_78_H _PK_H_(0x13, 0x78) ++#define REG_SC_BK13_79_L _PK_L_(0x13, 0x79) ++#define REG_SC_BK13_79_H _PK_H_(0x13, 0x79) ++#define REG_SC_BK13_7A_L _PK_L_(0x13, 0x7A) ++#define REG_SC_BK13_7A_H _PK_H_(0x13, 0x7A) ++#define REG_SC_BK13_7B_L _PK_L_(0x13, 0x7B) ++#define REG_SC_BK13_7B_H _PK_H_(0x13, 0x7B) ++#define REG_SC_BK13_7C_L _PK_L_(0x13, 0x7C) ++#define REG_SC_BK13_7C_H _PK_H_(0x13, 0x7C) ++#define REG_SC_BK13_7D_L _PK_L_(0x13, 0x7D) ++#define REG_SC_BK13_7D_H _PK_H_(0x13, 0x7D) ++#define REG_SC_BK13_7E_L _PK_L_(0x13, 0x7E) ++#define REG_SC_BK13_7E_H _PK_H_(0x13, 0x7E) ++#define REG_SC_BK13_7F_L _PK_L_(0x13, 0x7F) ++#define REG_SC_BK13_7F_H _PK_H_(0x13, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK14_00_L _PK_L_(0x14, 0x00) ++#define REG_SC_BK14_00_H _PK_H_(0x14, 0x00) ++#define REG_SC_BK14_01_L _PK_L_(0x14, 0x01) ++#define REG_SC_BK14_01_H _PK_H_(0x14, 0x01) ++#define REG_SC_BK14_02_L _PK_L_(0x14, 0x02) ++#define REG_SC_BK14_02_H _PK_H_(0x14, 0x02) ++#define REG_SC_BK14_03_L _PK_L_(0x14, 0x03) ++#define REG_SC_BK14_03_H _PK_H_(0x14, 0x03) ++#define REG_SC_BK14_04_L _PK_L_(0x14, 0x04) ++#define REG_SC_BK14_04_H _PK_H_(0x14, 0x04) ++#define REG_SC_BK14_05_L _PK_L_(0x14, 0x05) ++#define REG_SC_BK14_05_H _PK_H_(0x14, 0x05) ++#define REG_SC_BK14_06_L _PK_L_(0x14, 0x06) ++#define REG_SC_BK14_06_H _PK_H_(0x14, 0x06) ++#define REG_SC_BK14_07_L _PK_L_(0x14, 0x07) ++#define REG_SC_BK14_07_H _PK_H_(0x14, 0x07) ++#define REG_SC_BK14_08_L _PK_L_(0x14, 0x08) ++#define REG_SC_BK14_08_H _PK_H_(0x14, 0x08) ++#define REG_SC_BK14_09_L _PK_L_(0x14, 0x09) ++#define REG_SC_BK14_09_H _PK_H_(0x14, 0x09) ++#define REG_SC_BK14_0A_L _PK_L_(0x14, 0x0A) ++#define REG_SC_BK14_0A_H _PK_H_(0x14, 0x0A) ++#define REG_SC_BK14_0B_L _PK_L_(0x14, 0x0B) ++#define REG_SC_BK14_0B_H _PK_H_(0x14, 0x0B) ++#define REG_SC_BK14_0C_L _PK_L_(0x14, 0x0C) ++#define REG_SC_BK14_0C_H _PK_H_(0x14, 0x0C) ++#define REG_SC_BK14_0D_L _PK_L_(0x14, 0x0D) ++#define REG_SC_BK14_0D_H _PK_H_(0x14, 0x0D) ++#define REG_SC_BK14_0E_L _PK_L_(0x14, 0x0E) ++#define REG_SC_BK14_0E_H _PK_H_(0x14, 0x0E) ++#define REG_SC_BK14_0F_L _PK_L_(0x14, 0x0F) ++#define REG_SC_BK14_0F_H _PK_H_(0x14, 0x0F) ++#define REG_SC_BK14_10_L _PK_L_(0x14, 0x10) ++#define REG_SC_BK14_10_H _PK_H_(0x14, 0x10) ++#define REG_SC_BK14_11_L _PK_L_(0x14, 0x11) ++#define REG_SC_BK14_11_H _PK_H_(0x14, 0x11) ++#define REG_SC_BK14_12_L _PK_L_(0x14, 0x12) ++#define REG_SC_BK14_12_H _PK_H_(0x14, 0x12) ++#define REG_SC_BK14_13_L _PK_L_(0x14, 0x13) ++#define REG_SC_BK14_13_H _PK_H_(0x14, 0x13) ++#define REG_SC_BK14_14_L _PK_L_(0x14, 0x14) ++#define REG_SC_BK14_14_H _PK_H_(0x14, 0x14) ++#define REG_SC_BK14_15_L _PK_L_(0x14, 0x15) ++#define REG_SC_BK14_15_H _PK_H_(0x14, 0x15) ++#define REG_SC_BK14_16_L _PK_L_(0x14, 0x16) ++#define REG_SC_BK14_16_H _PK_H_(0x14, 0x16) ++#define REG_SC_BK14_17_L _PK_L_(0x14, 0x17) ++#define REG_SC_BK14_17_H _PK_H_(0x14, 0x17) ++#define REG_SC_BK14_18_L _PK_L_(0x14, 0x18) ++#define REG_SC_BK14_18_H _PK_H_(0x14, 0x18) ++#define REG_SC_BK14_19_L _PK_L_(0x14, 0x19) ++#define REG_SC_BK14_19_H _PK_H_(0x14, 0x19) ++#define REG_SC_BK14_1A_L _PK_L_(0x14, 0x1A) ++#define REG_SC_BK14_1A_H _PK_H_(0x14, 0x1A) ++#define REG_SC_BK14_1B_L _PK_L_(0x14, 0x1B) ++#define REG_SC_BK14_1B_H _PK_H_(0x14, 0x1B) ++#define REG_SC_BK14_1C_L _PK_L_(0x14, 0x1C) ++#define REG_SC_BK14_1C_H _PK_H_(0x14, 0x1C) ++#define REG_SC_BK14_1D_L _PK_L_(0x14, 0x1D) ++#define REG_SC_BK14_1D_H _PK_H_(0x14, 0x1D) ++#define REG_SC_BK14_1E_L _PK_L_(0x14, 0x1E) ++#define REG_SC_BK14_1E_H _PK_H_(0x14, 0x1E) ++#define REG_SC_BK14_1F_L _PK_L_(0x14, 0x1F) ++#define REG_SC_BK14_1F_H _PK_H_(0x14, 0x1F) ++#define REG_SC_BK14_20_L _PK_L_(0x14, 0x20) ++#define REG_SC_BK14_20_H _PK_H_(0x14, 0x20) ++#define REG_SC_BK14_21_L _PK_L_(0x14, 0x21) ++#define REG_SC_BK14_21_H _PK_H_(0x14, 0x21) ++#define REG_SC_BK14_22_L _PK_L_(0x14, 0x22) ++#define REG_SC_BK14_22_H _PK_H_(0x14, 0x22) ++#define REG_SC_BK14_23_L _PK_L_(0x14, 0x23) ++#define REG_SC_BK14_23_H _PK_H_(0x14, 0x23) ++#define REG_SC_BK14_24_L _PK_L_(0x14, 0x24) ++#define REG_SC_BK14_24_H _PK_H_(0x14, 0x24) ++#define REG_SC_BK14_25_L _PK_L_(0x14, 0x25) ++#define REG_SC_BK14_25_H _PK_H_(0x14, 0x25) ++#define REG_SC_BK14_26_L _PK_L_(0x14, 0x26) ++#define REG_SC_BK14_26_H _PK_H_(0x14, 0x26) ++#define REG_SC_BK14_27_L _PK_L_(0x14, 0x27) ++#define REG_SC_BK14_27_H _PK_H_(0x14, 0x27) ++#define REG_SC_BK14_28_L _PK_L_(0x14, 0x28) ++#define REG_SC_BK14_28_H _PK_H_(0x14, 0x28) ++#define REG_SC_BK14_29_L _PK_L_(0x14, 0x29) ++#define REG_SC_BK14_29_H _PK_H_(0x14, 0x29) ++#define REG_SC_BK14_2A_L _PK_L_(0x14, 0x2A) ++#define REG_SC_BK14_2A_H _PK_H_(0x14, 0x2A) ++#define REG_SC_BK14_2B_L _PK_L_(0x14, 0x2B) ++#define REG_SC_BK14_2B_H _PK_H_(0x14, 0x2B) ++#define REG_SC_BK14_2C_L _PK_L_(0x14, 0x2C) ++#define REG_SC_BK14_2C_H _PK_H_(0x14, 0x2C) ++#define REG_SC_BK14_2D_L _PK_L_(0x14, 0x2D) ++#define REG_SC_BK14_2D_H _PK_H_(0x14, 0x2D) ++#define REG_SC_BK14_2E_L _PK_L_(0x14, 0x2E) ++#define REG_SC_BK14_2E_H _PK_H_(0x14, 0x2E) ++#define REG_SC_BK14_2F_L _PK_L_(0x14, 0x2F) ++#define REG_SC_BK14_2F_H _PK_H_(0x14, 0x2F) ++#define REG_SC_BK14_30_L _PK_L_(0x14, 0x30) ++#define REG_SC_BK14_30_H _PK_H_(0x14, 0x30) ++#define REG_SC_BK14_31_L _PK_L_(0x14, 0x31) ++#define REG_SC_BK14_31_H _PK_H_(0x14, 0x31) ++#define REG_SC_BK14_32_L _PK_L_(0x14, 0x32) ++#define REG_SC_BK14_32_H _PK_H_(0x14, 0x32) ++#define REG_SC_BK14_33_L _PK_L_(0x14, 0x33) ++#define REG_SC_BK14_33_H _PK_H_(0x14, 0x33) ++#define REG_SC_BK14_34_L _PK_L_(0x14, 0x34) ++#define REG_SC_BK14_34_H _PK_H_(0x14, 0x34) ++#define REG_SC_BK14_35_L _PK_L_(0x14, 0x35) ++#define REG_SC_BK14_35_H _PK_H_(0x14, 0x35) ++#define REG_SC_BK14_36_L _PK_L_(0x14, 0x36) ++#define REG_SC_BK14_36_H _PK_H_(0x14, 0x36) ++#define REG_SC_BK14_37_L _PK_L_(0x14, 0x37) ++#define REG_SC_BK14_37_H _PK_H_(0x14, 0x37) ++#define REG_SC_BK14_38_L _PK_L_(0x14, 0x38) ++#define REG_SC_BK14_38_H _PK_H_(0x14, 0x38) ++#define REG_SC_BK14_39_L _PK_L_(0x14, 0x39) ++#define REG_SC_BK14_39_H _PK_H_(0x14, 0x39) ++#define REG_SC_BK14_3A_L _PK_L_(0x14, 0x3A) ++#define REG_SC_BK14_3A_H _PK_H_(0x14, 0x3A) ++#define REG_SC_BK14_3B_L _PK_L_(0x14, 0x3B) ++#define REG_SC_BK14_3B_H _PK_H_(0x14, 0x3B) ++#define REG_SC_BK14_3C_L _PK_L_(0x14, 0x3C) ++#define REG_SC_BK14_3C_H _PK_H_(0x14, 0x3C) ++#define REG_SC_BK14_3D_L _PK_L_(0x14, 0x3D) ++#define REG_SC_BK14_3D_H _PK_H_(0x14, 0x3D) ++#define REG_SC_BK14_3E_L _PK_L_(0x14, 0x3E) ++#define REG_SC_BK14_3E_H _PK_H_(0x14, 0x3E) ++#define REG_SC_BK14_3F_L _PK_L_(0x14, 0x3F) ++#define REG_SC_BK14_3F_H _PK_H_(0x14, 0x3F) ++#define REG_SC_BK14_40_L _PK_L_(0x14, 0x40) ++#define REG_SC_BK14_40_H _PK_H_(0x14, 0x40) ++#define REG_SC_BK14_41_L _PK_L_(0x14, 0x41) ++#define REG_SC_BK14_41_H _PK_H_(0x14, 0x41) ++#define REG_SC_BK14_42_L _PK_L_(0x14, 0x42) ++#define REG_SC_BK14_42_H _PK_H_(0x14, 0x42) ++#define REG_SC_BK14_43_L _PK_L_(0x14, 0x43) ++#define REG_SC_BK14_43_H _PK_H_(0x14, 0x43) ++#define REG_SC_BK14_44_L _PK_L_(0x14, 0x44) ++#define REG_SC_BK14_44_H _PK_H_(0x14, 0x44) ++#define REG_SC_BK14_45_L _PK_L_(0x14, 0x45) ++#define REG_SC_BK14_45_H _PK_H_(0x14, 0x45) ++#define REG_SC_BK14_46_L _PK_L_(0x14, 0x46) ++#define REG_SC_BK14_46_H _PK_H_(0x14, 0x46) ++#define REG_SC_BK14_47_L _PK_L_(0x14, 0x47) ++#define REG_SC_BK14_47_H _PK_H_(0x14, 0x47) ++#define REG_SC_BK14_48_L _PK_L_(0x14, 0x48) ++#define REG_SC_BK14_48_H _PK_H_(0x14, 0x48) ++#define REG_SC_BK14_49_L _PK_L_(0x14, 0x49) ++#define REG_SC_BK14_49_H _PK_H_(0x14, 0x49) ++#define REG_SC_BK14_4A_L _PK_L_(0x14, 0x4A) ++#define REG_SC_BK14_4A_H _PK_H_(0x14, 0x4A) ++#define REG_SC_BK14_4B_L _PK_L_(0x14, 0x4B) ++#define REG_SC_BK14_4B_H _PK_H_(0x14, 0x4B) ++#define REG_SC_BK14_4C_L _PK_L_(0x14, 0x4C) ++#define REG_SC_BK14_4C_H _PK_H_(0x14, 0x4C) ++#define REG_SC_BK14_4D_L _PK_L_(0x14, 0x4D) ++#define REG_SC_BK14_4D_H _PK_H_(0x14, 0x4D) ++#define REG_SC_BK14_4E_L _PK_L_(0x14, 0x4E) ++#define REG_SC_BK14_4E_H _PK_H_(0x14, 0x4E) ++#define REG_SC_BK14_4F_L _PK_L_(0x14, 0x4F) ++#define REG_SC_BK14_4F_H _PK_H_(0x14, 0x4F) ++#define REG_SC_BK14_50_L _PK_L_(0x14, 0x50) ++#define REG_SC_BK14_50_H _PK_H_(0x14, 0x50) ++#define REG_SC_BK14_51_L _PK_L_(0x14, 0x51) ++#define REG_SC_BK14_51_H _PK_H_(0x14, 0x51) ++#define REG_SC_BK14_52_L _PK_L_(0x14, 0x52) ++#define REG_SC_BK14_52_H _PK_H_(0x14, 0x52) ++#define REG_SC_BK14_53_L _PK_L_(0x14, 0x53) ++#define REG_SC_BK14_53_H _PK_H_(0x14, 0x53) ++#define REG_SC_BK14_54_L _PK_L_(0x14, 0x54) ++#define REG_SC_BK14_54_H _PK_H_(0x14, 0x54) ++#define REG_SC_BK14_55_L _PK_L_(0x14, 0x55) ++#define REG_SC_BK14_55_H _PK_H_(0x14, 0x55) ++#define REG_SC_BK14_56_L _PK_L_(0x14, 0x56) ++#define REG_SC_BK14_56_H _PK_H_(0x14, 0x56) ++#define REG_SC_BK14_57_L _PK_L_(0x14, 0x57) ++#define REG_SC_BK14_57_H _PK_H_(0x14, 0x57) ++#define REG_SC_BK14_58_L _PK_L_(0x14, 0x58) ++#define REG_SC_BK14_58_H _PK_H_(0x14, 0x58) ++#define REG_SC_BK14_59_L _PK_L_(0x14, 0x59) ++#define REG_SC_BK14_59_H _PK_H_(0x14, 0x59) ++#define REG_SC_BK14_5A_L _PK_L_(0x14, 0x5A) ++#define REG_SC_BK14_5A_H _PK_H_(0x14, 0x5A) ++#define REG_SC_BK14_5B_L _PK_L_(0x14, 0x5B) ++#define REG_SC_BK14_5B_H _PK_H_(0x14, 0x5B) ++#define REG_SC_BK14_5C_L _PK_L_(0x14, 0x5C) ++#define REG_SC_BK14_5C_H _PK_H_(0x14, 0x5C) ++#define REG_SC_BK14_5D_L _PK_L_(0x14, 0x5D) ++#define REG_SC_BK14_5D_H _PK_H_(0x14, 0x5D) ++#define REG_SC_BK14_5E_L _PK_L_(0x14, 0x5E) ++#define REG_SC_BK14_5E_H _PK_H_(0x14, 0x5E) ++#define REG_SC_BK14_5F_L _PK_L_(0x14, 0x5F) ++#define REG_SC_BK14_5F_H _PK_H_(0x14, 0x5F) ++#define REG_SC_BK14_60_L _PK_L_(0x14, 0x60) ++#define REG_SC_BK14_60_H _PK_H_(0x14, 0x60) ++#define REG_SC_BK14_61_L _PK_L_(0x14, 0x61) ++#define REG_SC_BK14_61_H _PK_H_(0x14, 0x61) ++#define REG_SC_BK14_62_L _PK_L_(0x14, 0x62) ++#define REG_SC_BK14_62_H _PK_H_(0x14, 0x62) ++#define REG_SC_BK14_63_L _PK_L_(0x14, 0x63) ++#define REG_SC_BK14_63_H _PK_H_(0x14, 0x63) ++#define REG_SC_BK14_64_L _PK_L_(0x14, 0x64) ++#define REG_SC_BK14_64_H _PK_H_(0x14, 0x64) ++#define REG_SC_BK14_65_L _PK_L_(0x14, 0x65) ++#define REG_SC_BK14_65_H _PK_H_(0x14, 0x65) ++#define REG_SC_BK14_66_L _PK_L_(0x14, 0x66) ++#define REG_SC_BK14_66_H _PK_H_(0x14, 0x66) ++#define REG_SC_BK14_67_L _PK_L_(0x14, 0x67) ++#define REG_SC_BK14_67_H _PK_H_(0x14, 0x67) ++#define REG_SC_BK14_68_L _PK_L_(0x14, 0x68) ++#define REG_SC_BK14_68_H _PK_H_(0x14, 0x68) ++#define REG_SC_BK14_69_L _PK_L_(0x14, 0x69) ++#define REG_SC_BK14_69_H _PK_H_(0x14, 0x69) ++#define REG_SC_BK14_6A_L _PK_L_(0x14, 0x6A) ++#define REG_SC_BK14_6A_H _PK_H_(0x14, 0x6A) ++#define REG_SC_BK14_6B_L _PK_L_(0x14, 0x6B) ++#define REG_SC_BK14_6B_H _PK_H_(0x14, 0x6B) ++#define REG_SC_BK14_6C_L _PK_L_(0x14, 0x6C) ++#define REG_SC_BK14_6C_H _PK_H_(0x14, 0x6C) ++#define REG_SC_BK14_6D_L _PK_L_(0x14, 0x6D) ++#define REG_SC_BK14_6D_H _PK_H_(0x14, 0x6D) ++#define REG_SC_BK14_6E_L _PK_L_(0x14, 0x6E) ++#define REG_SC_BK14_6E_H _PK_H_(0x14, 0x6E) ++#define REG_SC_BK14_6F_L _PK_L_(0x14, 0x6F) ++#define REG_SC_BK14_6F_H _PK_H_(0x14, 0x6F) ++#define REG_SC_BK14_70_L _PK_L_(0x14, 0x70) ++#define REG_SC_BK14_70_H _PK_H_(0x14, 0x70) ++#define REG_SC_BK14_71_L _PK_L_(0x14, 0x71) ++#define REG_SC_BK14_71_H _PK_H_(0x14, 0x71) ++#define REG_SC_BK14_72_L _PK_L_(0x14, 0x72) ++#define REG_SC_BK14_72_H _PK_H_(0x14, 0x72) ++#define REG_SC_BK14_73_L _PK_L_(0x14, 0x73) ++#define REG_SC_BK14_73_H _PK_H_(0x14, 0x73) ++#define REG_SC_BK14_74_L _PK_L_(0x14, 0x74) ++#define REG_SC_BK14_74_H _PK_H_(0x14, 0x74) ++#define REG_SC_BK14_75_L _PK_L_(0x14, 0x75) ++#define REG_SC_BK14_75_H _PK_H_(0x14, 0x75) ++#define REG_SC_BK14_76_L _PK_L_(0x14, 0x76) ++#define REG_SC_BK14_76_H _PK_H_(0x14, 0x76) ++#define REG_SC_BK14_77_L _PK_L_(0x14, 0x77) ++#define REG_SC_BK14_77_H _PK_H_(0x14, 0x77) ++#define REG_SC_BK14_78_L _PK_L_(0x14, 0x78) ++#define REG_SC_BK14_78_H _PK_H_(0x14, 0x78) ++#define REG_SC_BK14_79_L _PK_L_(0x14, 0x79) ++#define REG_SC_BK14_79_H _PK_H_(0x14, 0x79) ++#define REG_SC_BK14_7A_L _PK_L_(0x14, 0x7A) ++#define REG_SC_BK14_7A_H _PK_H_(0x14, 0x7A) ++#define REG_SC_BK14_7B_L _PK_L_(0x14, 0x7B) ++#define REG_SC_BK14_7B_H _PK_H_(0x14, 0x7B) ++#define REG_SC_BK14_7C_L _PK_L_(0x14, 0x7C) ++#define REG_SC_BK14_7C_H _PK_H_(0x14, 0x7C) ++#define REG_SC_BK14_7D_L _PK_L_(0x14, 0x7D) ++#define REG_SC_BK14_7D_H _PK_H_(0x14, 0x7D) ++#define REG_SC_BK14_7E_L _PK_L_(0x14, 0x7E) ++#define REG_SC_BK14_7E_H _PK_H_(0x14, 0x7E) ++#define REG_SC_BK14_7F_L _PK_L_(0x14, 0x7F) ++#define REG_SC_BK14_7F_H _PK_H_(0x14, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK15_00_L _PK_L_(0x15, 0x00) ++#define REG_SC_BK15_00_H _PK_H_(0x15, 0x00) ++#define REG_SC_BK15_01_L _PK_L_(0x15, 0x01) ++#define REG_SC_BK15_01_H _PK_H_(0x15, 0x01) ++#define REG_SC_BK15_02_L _PK_L_(0x15, 0x02) ++#define REG_SC_BK15_02_H _PK_H_(0x15, 0x02) ++#define REG_SC_BK15_03_L _PK_L_(0x15, 0x03) ++#define REG_SC_BK15_03_H _PK_H_(0x15, 0x03) ++#define REG_SC_BK15_04_L _PK_L_(0x15, 0x04) ++#define REG_SC_BK15_04_H _PK_H_(0x15, 0x04) ++#define REG_SC_BK15_05_L _PK_L_(0x15, 0x05) ++#define REG_SC_BK15_05_H _PK_H_(0x15, 0x05) ++#define REG_SC_BK15_06_L _PK_L_(0x15, 0x06) ++#define REG_SC_BK15_06_H _PK_H_(0x15, 0x06) ++#define REG_SC_BK15_07_L _PK_L_(0x15, 0x07) ++#define REG_SC_BK15_07_H _PK_H_(0x15, 0x07) ++#define REG_SC_BK15_08_L _PK_L_(0x15, 0x08) ++#define REG_SC_BK15_08_H _PK_H_(0x15, 0x08) ++#define REG_SC_BK15_09_L _PK_L_(0x15, 0x09) ++#define REG_SC_BK15_09_H _PK_H_(0x15, 0x09) ++#define REG_SC_BK15_0A_L _PK_L_(0x15, 0x0A) ++#define REG_SC_BK15_0A_H _PK_H_(0x15, 0x0A) ++#define REG_SC_BK15_0B_L _PK_L_(0x15, 0x0B) ++#define REG_SC_BK15_0B_H _PK_H_(0x15, 0x0B) ++#define REG_SC_BK15_0C_L _PK_L_(0x15, 0x0C) ++#define REG_SC_BK15_0C_H _PK_H_(0x15, 0x0C) ++#define REG_SC_BK15_0D_L _PK_L_(0x15, 0x0D) ++#define REG_SC_BK15_0D_H _PK_H_(0x15, 0x0D) ++#define REG_SC_BK15_0E_L _PK_L_(0x15, 0x0E) ++#define REG_SC_BK15_0E_H _PK_H_(0x15, 0x0E) ++#define REG_SC_BK15_0F_L _PK_L_(0x15, 0x0F) ++#define REG_SC_BK15_0F_H _PK_H_(0x15, 0x0F) ++#define REG_SC_BK15_10_L _PK_L_(0x15, 0x10) ++#define REG_SC_BK15_10_H _PK_H_(0x15, 0x10) ++#define REG_SC_BK15_11_L _PK_L_(0x15, 0x11) ++#define REG_SC_BK15_11_H _PK_H_(0x15, 0x11) ++#define REG_SC_BK15_12_L _PK_L_(0x15, 0x12) ++#define REG_SC_BK15_12_H _PK_H_(0x15, 0x12) ++#define REG_SC_BK15_13_L _PK_L_(0x15, 0x13) ++#define REG_SC_BK15_13_H _PK_H_(0x15, 0x13) ++#define REG_SC_BK15_14_L _PK_L_(0x15, 0x14) ++#define REG_SC_BK15_14_H _PK_H_(0x15, 0x14) ++#define REG_SC_BK15_15_L _PK_L_(0x15, 0x15) ++#define REG_SC_BK15_15_H _PK_H_(0x15, 0x15) ++#define REG_SC_BK15_16_L _PK_L_(0x15, 0x16) ++#define REG_SC_BK15_16_H _PK_H_(0x15, 0x16) ++#define REG_SC_BK15_17_L _PK_L_(0x15, 0x17) ++#define REG_SC_BK15_17_H _PK_H_(0x15, 0x17) ++#define REG_SC_BK15_18_L _PK_L_(0x15, 0x18) ++#define REG_SC_BK15_18_H _PK_H_(0x15, 0x18) ++#define REG_SC_BK15_19_L _PK_L_(0x15, 0x19) ++#define REG_SC_BK15_19_H _PK_H_(0x15, 0x19) ++#define REG_SC_BK15_1A_L _PK_L_(0x15, 0x1A) ++#define REG_SC_BK15_1A_H _PK_H_(0x15, 0x1A) ++#define REG_SC_BK15_1B_L _PK_L_(0x15, 0x1B) ++#define REG_SC_BK15_1B_H _PK_H_(0x15, 0x1B) ++#define REG_SC_BK15_1C_L _PK_L_(0x15, 0x1C) ++#define REG_SC_BK15_1C_H _PK_H_(0x15, 0x1C) ++#define REG_SC_BK15_1D_L _PK_L_(0x15, 0x1D) ++#define REG_SC_BK15_1D_H _PK_H_(0x15, 0x1D) ++#define REG_SC_BK15_1E_L _PK_L_(0x15, 0x1E) ++#define REG_SC_BK15_1E_H _PK_H_(0x15, 0x1E) ++#define REG_SC_BK15_1F_L _PK_L_(0x15, 0x1F) ++#define REG_SC_BK15_1F_H _PK_H_(0x15, 0x1F) ++#define REG_SC_BK15_20_L _PK_L_(0x15, 0x20) ++#define REG_SC_BK15_20_H _PK_H_(0x15, 0x20) ++#define REG_SC_BK15_21_L _PK_L_(0x15, 0x21) ++#define REG_SC_BK15_21_H _PK_H_(0x15, 0x21) ++#define REG_SC_BK15_22_L _PK_L_(0x15, 0x22) ++#define REG_SC_BK15_22_H _PK_H_(0x15, 0x22) ++#define REG_SC_BK15_23_L _PK_L_(0x15, 0x23) ++#define REG_SC_BK15_23_H _PK_H_(0x15, 0x23) ++#define REG_SC_BK15_24_L _PK_L_(0x15, 0x24) ++#define REG_SC_BK15_24_H _PK_H_(0x15, 0x24) ++#define REG_SC_BK15_25_L _PK_L_(0x15, 0x25) ++#define REG_SC_BK15_25_H _PK_H_(0x15, 0x25) ++#define REG_SC_BK15_26_L _PK_L_(0x15, 0x26) ++#define REG_SC_BK15_26_H _PK_H_(0x15, 0x26) ++#define REG_SC_BK15_27_L _PK_L_(0x15, 0x27) ++#define REG_SC_BK15_27_H _PK_H_(0x15, 0x27) ++#define REG_SC_BK15_28_L _PK_L_(0x15, 0x28) ++#define REG_SC_BK15_28_H _PK_H_(0x15, 0x28) ++#define REG_SC_BK15_29_L _PK_L_(0x15, 0x29) ++#define REG_SC_BK15_29_H _PK_H_(0x15, 0x29) ++#define REG_SC_BK15_2A_L _PK_L_(0x15, 0x2A) ++#define REG_SC_BK15_2A_H _PK_H_(0x15, 0x2A) ++#define REG_SC_BK15_2B_L _PK_L_(0x15, 0x2B) ++#define REG_SC_BK15_2B_H _PK_H_(0x15, 0x2B) ++#define REG_SC_BK15_2C_L _PK_L_(0x15, 0x2C) ++#define REG_SC_BK15_2C_H _PK_H_(0x15, 0x2C) ++#define REG_SC_BK15_2D_L _PK_L_(0x15, 0x2D) ++#define REG_SC_BK15_2D_H _PK_H_(0x15, 0x2D) ++#define REG_SC_BK15_2E_L _PK_L_(0x15, 0x2E) ++#define REG_SC_BK15_2E_H _PK_H_(0x15, 0x2E) ++#define REG_SC_BK15_2F_L _PK_L_(0x15, 0x2F) ++#define REG_SC_BK15_2F_H _PK_H_(0x15, 0x2F) ++#define REG_SC_BK15_30_L _PK_L_(0x15, 0x30) ++#define REG_SC_BK15_30_H _PK_H_(0x15, 0x30) ++#define REG_SC_BK15_31_L _PK_L_(0x15, 0x31) ++#define REG_SC_BK15_31_H _PK_H_(0x15, 0x31) ++#define REG_SC_BK15_32_L _PK_L_(0x15, 0x32) ++#define REG_SC_BK15_32_H _PK_H_(0x15, 0x32) ++#define REG_SC_BK15_33_L _PK_L_(0x15, 0x33) ++#define REG_SC_BK15_33_H _PK_H_(0x15, 0x33) ++#define REG_SC_BK15_34_L _PK_L_(0x15, 0x34) ++#define REG_SC_BK15_34_H _PK_H_(0x15, 0x34) ++#define REG_SC_BK15_35_L _PK_L_(0x15, 0x35) ++#define REG_SC_BK15_35_H _PK_H_(0x15, 0x35) ++#define REG_SC_BK15_36_L _PK_L_(0x15, 0x36) ++#define REG_SC_BK15_36_H _PK_H_(0x15, 0x36) ++#define REG_SC_BK15_37_L _PK_L_(0x15, 0x37) ++#define REG_SC_BK15_37_H _PK_H_(0x15, 0x37) ++#define REG_SC_BK15_38_L _PK_L_(0x15, 0x38) ++#define REG_SC_BK15_38_H _PK_H_(0x15, 0x38) ++#define REG_SC_BK15_39_L _PK_L_(0x15, 0x39) ++#define REG_SC_BK15_39_H _PK_H_(0x15, 0x39) ++#define REG_SC_BK15_3A_L _PK_L_(0x15, 0x3A) ++#define REG_SC_BK15_3A_H _PK_H_(0x15, 0x3A) ++#define REG_SC_BK15_3B_L _PK_L_(0x15, 0x3B) ++#define REG_SC_BK15_3B_H _PK_H_(0x15, 0x3B) ++#define REG_SC_BK15_3C_L _PK_L_(0x15, 0x3C) ++#define REG_SC_BK15_3C_H _PK_H_(0x15, 0x3C) ++#define REG_SC_BK15_3D_L _PK_L_(0x15, 0x3D) ++#define REG_SC_BK15_3D_H _PK_H_(0x15, 0x3D) ++#define REG_SC_BK15_3E_L _PK_L_(0x15, 0x3E) ++#define REG_SC_BK15_3E_H _PK_H_(0x15, 0x3E) ++#define REG_SC_BK15_3F_L _PK_L_(0x15, 0x3F) ++#define REG_SC_BK15_3F_H _PK_H_(0x15, 0x3F) ++#define REG_SC_BK15_40_L _PK_L_(0x15, 0x40) ++#define REG_SC_BK15_40_H _PK_H_(0x15, 0x40) ++#define REG_SC_BK15_41_L _PK_L_(0x15, 0x41) ++#define REG_SC_BK15_41_H _PK_H_(0x15, 0x41) ++#define REG_SC_BK15_42_L _PK_L_(0x15, 0x42) ++#define REG_SC_BK15_42_H _PK_H_(0x15, 0x42) ++#define REG_SC_BK15_43_L _PK_L_(0x15, 0x43) ++#define REG_SC_BK15_43_H _PK_H_(0x15, 0x43) ++#define REG_SC_BK15_44_L _PK_L_(0x15, 0x44) ++#define REG_SC_BK15_44_H _PK_H_(0x15, 0x44) ++#define REG_SC_BK15_45_L _PK_L_(0x15, 0x45) ++#define REG_SC_BK15_45_H _PK_H_(0x15, 0x45) ++#define REG_SC_BK15_46_L _PK_L_(0x15, 0x46) ++#define REG_SC_BK15_46_H _PK_H_(0x15, 0x46) ++#define REG_SC_BK15_47_L _PK_L_(0x15, 0x47) ++#define REG_SC_BK15_47_H _PK_H_(0x15, 0x47) ++#define REG_SC_BK15_48_L _PK_L_(0x15, 0x48) ++#define REG_SC_BK15_48_H _PK_H_(0x15, 0x48) ++#define REG_SC_BK15_49_L _PK_L_(0x15, 0x49) ++#define REG_SC_BK15_49_H _PK_H_(0x15, 0x49) ++#define REG_SC_BK15_4A_L _PK_L_(0x15, 0x4A) ++#define REG_SC_BK15_4A_H _PK_H_(0x15, 0x4A) ++#define REG_SC_BK15_4B_L _PK_L_(0x15, 0x4B) ++#define REG_SC_BK15_4B_H _PK_H_(0x15, 0x4B) ++#define REG_SC_BK15_4C_L _PK_L_(0x15, 0x4C) ++#define REG_SC_BK15_4C_H _PK_H_(0x15, 0x4C) ++#define REG_SC_BK15_4D_L _PK_L_(0x15, 0x4D) ++#define REG_SC_BK15_4D_H _PK_H_(0x15, 0x4D) ++#define REG_SC_BK15_4E_L _PK_L_(0x15, 0x4E) ++#define REG_SC_BK15_4E_H _PK_H_(0x15, 0x4E) ++#define REG_SC_BK15_4F_L _PK_L_(0x15, 0x4F) ++#define REG_SC_BK15_4F_H _PK_H_(0x15, 0x4F) ++#define REG_SC_BK15_50_L _PK_L_(0x15, 0x50) ++#define REG_SC_BK15_50_H _PK_H_(0x15, 0x50) ++#define REG_SC_BK15_51_L _PK_L_(0x15, 0x51) ++#define REG_SC_BK15_51_H _PK_H_(0x15, 0x51) ++#define REG_SC_BK15_52_L _PK_L_(0x15, 0x52) ++#define REG_SC_BK15_52_H _PK_H_(0x15, 0x52) ++#define REG_SC_BK15_53_L _PK_L_(0x15, 0x53) ++#define REG_SC_BK15_53_H _PK_H_(0x15, 0x53) ++#define REG_SC_BK15_54_L _PK_L_(0x15, 0x54) ++#define REG_SC_BK15_54_H _PK_H_(0x15, 0x54) ++#define REG_SC_BK15_55_L _PK_L_(0x15, 0x55) ++#define REG_SC_BK15_55_H _PK_H_(0x15, 0x55) ++#define REG_SC_BK15_56_L _PK_L_(0x15, 0x56) ++#define REG_SC_BK15_56_H _PK_H_(0x15, 0x56) ++#define REG_SC_BK15_57_L _PK_L_(0x15, 0x57) ++#define REG_SC_BK15_57_H _PK_H_(0x15, 0x57) ++#define REG_SC_BK15_58_L _PK_L_(0x15, 0x58) ++#define REG_SC_BK15_58_H _PK_H_(0x15, 0x58) ++#define REG_SC_BK15_59_L _PK_L_(0x15, 0x59) ++#define REG_SC_BK15_59_H _PK_H_(0x15, 0x59) ++#define REG_SC_BK15_5A_L _PK_L_(0x15, 0x5A) ++#define REG_SC_BK15_5A_H _PK_H_(0x15, 0x5A) ++#define REG_SC_BK15_5B_L _PK_L_(0x15, 0x5B) ++#define REG_SC_BK15_5B_H _PK_H_(0x15, 0x5B) ++#define REG_SC_BK15_5C_L _PK_L_(0x15, 0x5C) ++#define REG_SC_BK15_5C_H _PK_H_(0x15, 0x5C) ++#define REG_SC_BK15_5D_L _PK_L_(0x15, 0x5D) ++#define REG_SC_BK15_5D_H _PK_H_(0x15, 0x5D) ++#define REG_SC_BK15_5E_L _PK_L_(0x15, 0x5E) ++#define REG_SC_BK15_5E_H _PK_H_(0x15, 0x5E) ++#define REG_SC_BK15_5F_L _PK_L_(0x15, 0x5F) ++#define REG_SC_BK15_5F_H _PK_H_(0x15, 0x5F) ++#define REG_SC_BK15_60_L _PK_L_(0x15, 0x60) ++#define REG_SC_BK15_60_H _PK_H_(0x15, 0x60) ++#define REG_SC_BK15_61_L _PK_L_(0x15, 0x61) ++#define REG_SC_BK15_61_H _PK_H_(0x15, 0x61) ++#define REG_SC_BK15_62_L _PK_L_(0x15, 0x62) ++#define REG_SC_BK15_62_H _PK_H_(0x15, 0x62) ++#define REG_SC_BK15_63_L _PK_L_(0x15, 0x63) ++#define REG_SC_BK15_63_H _PK_H_(0x15, 0x63) ++#define REG_SC_BK15_64_L _PK_L_(0x15, 0x64) ++#define REG_SC_BK15_64_H _PK_H_(0x15, 0x64) ++#define REG_SC_BK15_65_L _PK_L_(0x15, 0x65) ++#define REG_SC_BK15_65_H _PK_H_(0x15, 0x65) ++#define REG_SC_BK15_66_L _PK_L_(0x15, 0x66) ++#define REG_SC_BK15_66_H _PK_H_(0x15, 0x66) ++#define REG_SC_BK15_67_L _PK_L_(0x15, 0x67) ++#define REG_SC_BK15_67_H _PK_H_(0x15, 0x67) ++#define REG_SC_BK15_68_L _PK_L_(0x15, 0x68) ++#define REG_SC_BK15_68_H _PK_H_(0x15, 0x68) ++#define REG_SC_BK15_69_L _PK_L_(0x15, 0x69) ++#define REG_SC_BK15_69_H _PK_H_(0x15, 0x69) ++#define REG_SC_BK15_6A_L _PK_L_(0x15, 0x6A) ++#define REG_SC_BK15_6A_H _PK_H_(0x15, 0x6A) ++#define REG_SC_BK15_6B_L _PK_L_(0x15, 0x6B) ++#define REG_SC_BK15_6B_H _PK_H_(0x15, 0x6B) ++#define REG_SC_BK15_6C_L _PK_L_(0x15, 0x6C) ++#define REG_SC_BK15_6C_H _PK_H_(0x15, 0x6C) ++#define REG_SC_BK15_6D_L _PK_L_(0x15, 0x6D) ++#define REG_SC_BK15_6D_H _PK_H_(0x15, 0x6D) ++#define REG_SC_BK15_6E_L _PK_L_(0x15, 0x6E) ++#define REG_SC_BK15_6E_H _PK_H_(0x15, 0x6E) ++#define REG_SC_BK15_6F_L _PK_L_(0x15, 0x6F) ++#define REG_SC_BK15_6F_H _PK_H_(0x15, 0x6F) ++#define REG_SC_BK15_70_L _PK_L_(0x15, 0x70) ++#define REG_SC_BK15_70_H _PK_H_(0x15, 0x70) ++#define REG_SC_BK15_71_L _PK_L_(0x15, 0x71) ++#define REG_SC_BK15_71_H _PK_H_(0x15, 0x71) ++#define REG_SC_BK15_72_L _PK_L_(0x15, 0x72) ++#define REG_SC_BK15_72_H _PK_H_(0x15, 0x72) ++#define REG_SC_BK15_73_L _PK_L_(0x15, 0x73) ++#define REG_SC_BK15_73_H _PK_H_(0x15, 0x73) ++#define REG_SC_BK15_74_L _PK_L_(0x15, 0x74) ++#define REG_SC_BK15_74_H _PK_H_(0x15, 0x74) ++#define REG_SC_BK15_75_L _PK_L_(0x15, 0x75) ++#define REG_SC_BK15_75_H _PK_H_(0x15, 0x75) ++#define REG_SC_BK15_76_L _PK_L_(0x15, 0x76) ++#define REG_SC_BK15_76_H _PK_H_(0x15, 0x76) ++#define REG_SC_BK15_77_L _PK_L_(0x15, 0x77) ++#define REG_SC_BK15_77_H _PK_H_(0x15, 0x77) ++#define REG_SC_BK15_78_L _PK_L_(0x15, 0x78) ++#define REG_SC_BK15_78_H _PK_H_(0x15, 0x78) ++#define REG_SC_BK15_79_L _PK_L_(0x15, 0x79) ++#define REG_SC_BK15_79_H _PK_H_(0x15, 0x79) ++#define REG_SC_BK15_7A_L _PK_L_(0x15, 0x7A) ++#define REG_SC_BK15_7A_H _PK_H_(0x15, 0x7A) ++#define REG_SC_BK15_7B_L _PK_L_(0x15, 0x7B) ++#define REG_SC_BK15_7B_H _PK_H_(0x15, 0x7B) ++#define REG_SC_BK15_7C_L _PK_L_(0x15, 0x7C) ++#define REG_SC_BK15_7C_H _PK_H_(0x15, 0x7C) ++#define REG_SC_BK15_7D_L _PK_L_(0x15, 0x7D) ++#define REG_SC_BK15_7D_H _PK_H_(0x15, 0x7D) ++#define REG_SC_BK15_7E_L _PK_L_(0x15, 0x7E) ++#define REG_SC_BK15_7E_H _PK_H_(0x15, 0x7E) ++#define REG_SC_BK15_7F_L _PK_L_(0x15, 0x7F) ++#define REG_SC_BK15_7F_H _PK_H_(0x15, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK16_00_L _PK_L_(0x16, 0x00) ++#define REG_SC_BK16_00_H _PK_H_(0x16, 0x00) ++#define REG_SC_BK16_01_L _PK_L_(0x16, 0x01) ++#define REG_SC_BK16_01_H _PK_H_(0x16, 0x01) ++#define REG_SC_BK16_02_L _PK_L_(0x16, 0x02) ++#define REG_SC_BK16_02_H _PK_H_(0x16, 0x02) ++#define REG_SC_BK16_03_L _PK_L_(0x16, 0x03) ++#define REG_SC_BK16_03_H _PK_H_(0x16, 0x03) ++#define REG_SC_BK16_04_L _PK_L_(0x16, 0x04) ++#define REG_SC_BK16_04_H _PK_H_(0x16, 0x04) ++#define REG_SC_BK16_05_L _PK_L_(0x16, 0x05) ++#define REG_SC_BK16_05_H _PK_H_(0x16, 0x05) ++#define REG_SC_BK16_06_L _PK_L_(0x16, 0x06) ++#define REG_SC_BK16_06_H _PK_H_(0x16, 0x06) ++#define REG_SC_BK16_07_L _PK_L_(0x16, 0x07) ++#define REG_SC_BK16_07_H _PK_H_(0x16, 0x07) ++#define REG_SC_BK16_08_L _PK_L_(0x16, 0x08) ++#define REG_SC_BK16_08_H _PK_H_(0x16, 0x08) ++#define REG_SC_BK16_09_L _PK_L_(0x16, 0x09) ++#define REG_SC_BK16_09_H _PK_H_(0x16, 0x09) ++#define REG_SC_BK16_0A_L _PK_L_(0x16, 0x0A) ++#define REG_SC_BK16_0A_H _PK_H_(0x16, 0x0A) ++#define REG_SC_BK16_0B_L _PK_L_(0x16, 0x0B) ++#define REG_SC_BK16_0B_H _PK_H_(0x16, 0x0B) ++#define REG_SC_BK16_0C_L _PK_L_(0x16, 0x0C) ++#define REG_SC_BK16_0C_H _PK_H_(0x16, 0x0C) ++#define REG_SC_BK16_0D_L _PK_L_(0x16, 0x0D) ++#define REG_SC_BK16_0D_H _PK_H_(0x16, 0x0D) ++#define REG_SC_BK16_0E_L _PK_L_(0x16, 0x0E) ++#define REG_SC_BK16_0E_H _PK_H_(0x16, 0x0E) ++#define REG_SC_BK16_0F_L _PK_L_(0x16, 0x0F) ++#define REG_SC_BK16_0F_H _PK_H_(0x16, 0x0F) ++#define REG_SC_BK16_10_L _PK_L_(0x16, 0x10) ++#define REG_SC_BK16_10_H _PK_H_(0x16, 0x10) ++#define REG_SC_BK16_11_L _PK_L_(0x16, 0x11) ++#define REG_SC_BK16_11_H _PK_H_(0x16, 0x11) ++#define REG_SC_BK16_12_L _PK_L_(0x16, 0x12) ++#define REG_SC_BK16_12_H _PK_H_(0x16, 0x12) ++#define REG_SC_BK16_13_L _PK_L_(0x16, 0x13) ++#define REG_SC_BK16_13_H _PK_H_(0x16, 0x13) ++#define REG_SC_BK16_14_L _PK_L_(0x16, 0x14) ++#define REG_SC_BK16_14_H _PK_H_(0x16, 0x14) ++#define REG_SC_BK16_15_L _PK_L_(0x16, 0x15) ++#define REG_SC_BK16_15_H _PK_H_(0x16, 0x15) ++#define REG_SC_BK16_16_L _PK_L_(0x16, 0x16) ++#define REG_SC_BK16_16_H _PK_H_(0x16, 0x16) ++#define REG_SC_BK16_17_L _PK_L_(0x16, 0x17) ++#define REG_SC_BK16_17_H _PK_H_(0x16, 0x17) ++#define REG_SC_BK16_18_L _PK_L_(0x16, 0x18) ++#define REG_SC_BK16_18_H _PK_H_(0x16, 0x18) ++#define REG_SC_BK16_19_L _PK_L_(0x16, 0x19) ++#define REG_SC_BK16_19_H _PK_H_(0x16, 0x19) ++#define REG_SC_BK16_1A_L _PK_L_(0x16, 0x1A) ++#define REG_SC_BK16_1A_H _PK_H_(0x16, 0x1A) ++#define REG_SC_BK16_1B_L _PK_L_(0x16, 0x1B) ++#define REG_SC_BK16_1B_H _PK_H_(0x16, 0x1B) ++#define REG_SC_BK16_1C_L _PK_L_(0x16, 0x1C) ++#define REG_SC_BK16_1C_H _PK_H_(0x16, 0x1C) ++#define REG_SC_BK16_1D_L _PK_L_(0x16, 0x1D) ++#define REG_SC_BK16_1D_H _PK_H_(0x16, 0x1D) ++#define REG_SC_BK16_1E_L _PK_L_(0x16, 0x1E) ++#define REG_SC_BK16_1E_H _PK_H_(0x16, 0x1E) ++#define REG_SC_BK16_1F_L _PK_L_(0x16, 0x1F) ++#define REG_SC_BK16_1F_H _PK_H_(0x16, 0x1F) ++#define REG_SC_BK16_20_L _PK_L_(0x16, 0x20) ++#define REG_SC_BK16_20_H _PK_H_(0x16, 0x20) ++#define REG_SC_BK16_21_L _PK_L_(0x16, 0x21) ++#define REG_SC_BK16_21_H _PK_H_(0x16, 0x21) ++#define REG_SC_BK16_22_L _PK_L_(0x16, 0x22) ++#define REG_SC_BK16_22_H _PK_H_(0x16, 0x22) ++#define REG_SC_BK16_23_L _PK_L_(0x16, 0x23) ++#define REG_SC_BK16_23_H _PK_H_(0x16, 0x23) ++#define REG_SC_BK16_24_L _PK_L_(0x16, 0x24) ++#define REG_SC_BK16_24_H _PK_H_(0x16, 0x24) ++#define REG_SC_BK16_25_L _PK_L_(0x16, 0x25) ++#define REG_SC_BK16_25_H _PK_H_(0x16, 0x25) ++#define REG_SC_BK16_26_L _PK_L_(0x16, 0x26) ++#define REG_SC_BK16_26_H _PK_H_(0x16, 0x26) ++#define REG_SC_BK16_27_L _PK_L_(0x16, 0x27) ++#define REG_SC_BK16_27_H _PK_H_(0x16, 0x27) ++#define REG_SC_BK16_28_L _PK_L_(0x16, 0x28) ++#define REG_SC_BK16_28_H _PK_H_(0x16, 0x28) ++#define REG_SC_BK16_29_L _PK_L_(0x16, 0x29) ++#define REG_SC_BK16_29_H _PK_H_(0x16, 0x29) ++#define REG_SC_BK16_2A_L _PK_L_(0x16, 0x2A) ++#define REG_SC_BK16_2A_H _PK_H_(0x16, 0x2A) ++#define REG_SC_BK16_2B_L _PK_L_(0x16, 0x2B) ++#define REG_SC_BK16_2B_H _PK_H_(0x16, 0x2B) ++#define REG_SC_BK16_2C_L _PK_L_(0x16, 0x2C) ++#define REG_SC_BK16_2C_H _PK_H_(0x16, 0x2C) ++#define REG_SC_BK16_2D_L _PK_L_(0x16, 0x2D) ++#define REG_SC_BK16_2D_H _PK_H_(0x16, 0x2D) ++#define REG_SC_BK16_2E_L _PK_L_(0x16, 0x2E) ++#define REG_SC_BK16_2E_H _PK_H_(0x16, 0x2E) ++#define REG_SC_BK16_2F_L _PK_L_(0x16, 0x2F) ++#define REG_SC_BK16_2F_H _PK_H_(0x16, 0x2F) ++#define REG_SC_BK16_30_L _PK_L_(0x16, 0x30) ++#define REG_SC_BK16_30_H _PK_H_(0x16, 0x30) ++#define REG_SC_BK16_31_L _PK_L_(0x16, 0x31) ++#define REG_SC_BK16_31_H _PK_H_(0x16, 0x31) ++#define REG_SC_BK16_32_L _PK_L_(0x16, 0x32) ++#define REG_SC_BK16_32_H _PK_H_(0x16, 0x32) ++#define REG_SC_BK16_33_L _PK_L_(0x16, 0x33) ++#define REG_SC_BK16_33_H _PK_H_(0x16, 0x33) ++#define REG_SC_BK16_34_L _PK_L_(0x16, 0x34) ++#define REG_SC_BK16_34_H _PK_H_(0x16, 0x34) ++#define REG_SC_BK16_35_L _PK_L_(0x16, 0x35) ++#define REG_SC_BK16_35_H _PK_H_(0x16, 0x35) ++#define REG_SC_BK16_36_L _PK_L_(0x16, 0x36) ++#define REG_SC_BK16_36_H _PK_H_(0x16, 0x36) ++#define REG_SC_BK16_37_L _PK_L_(0x16, 0x37) ++#define REG_SC_BK16_37_H _PK_H_(0x16, 0x37) ++#define REG_SC_BK16_38_L _PK_L_(0x16, 0x38) ++#define REG_SC_BK16_38_H _PK_H_(0x16, 0x38) ++#define REG_SC_BK16_39_L _PK_L_(0x16, 0x39) ++#define REG_SC_BK16_39_H _PK_H_(0x16, 0x39) ++#define REG_SC_BK16_3A_L _PK_L_(0x16, 0x3A) ++#define REG_SC_BK16_3A_H _PK_H_(0x16, 0x3A) ++#define REG_SC_BK16_3B_L _PK_L_(0x16, 0x3B) ++#define REG_SC_BK16_3B_H _PK_H_(0x16, 0x3B) ++#define REG_SC_BK16_3C_L _PK_L_(0x16, 0x3C) ++#define REG_SC_BK16_3C_H _PK_H_(0x16, 0x3C) ++#define REG_SC_BK16_3D_L _PK_L_(0x16, 0x3D) ++#define REG_SC_BK16_3D_H _PK_H_(0x16, 0x3D) ++#define REG_SC_BK16_3E_L _PK_L_(0x16, 0x3E) ++#define REG_SC_BK16_3E_H _PK_H_(0x16, 0x3E) ++#define REG_SC_BK16_3F_L _PK_L_(0x16, 0x3F) ++#define REG_SC_BK16_3F_H _PK_H_(0x16, 0x3F) ++#define REG_SC_BK16_40_L _PK_L_(0x16, 0x40) ++#define REG_SC_BK16_40_H _PK_H_(0x16, 0x40) ++#define REG_SC_BK16_41_L _PK_L_(0x16, 0x41) ++#define REG_SC_BK16_41_H _PK_H_(0x16, 0x41) ++#define REG_SC_BK16_42_L _PK_L_(0x16, 0x42) ++#define REG_SC_BK16_42_H _PK_H_(0x16, 0x42) ++#define REG_SC_BK16_43_L _PK_L_(0x16, 0x43) ++#define REG_SC_BK16_43_H _PK_H_(0x16, 0x43) ++#define REG_SC_BK16_44_L _PK_L_(0x16, 0x44) ++#define REG_SC_BK16_44_H _PK_H_(0x16, 0x44) ++#define REG_SC_BK16_45_L _PK_L_(0x16, 0x45) ++#define REG_SC_BK16_45_H _PK_H_(0x16, 0x45) ++#define REG_SC_BK16_46_L _PK_L_(0x16, 0x46) ++#define REG_SC_BK16_46_H _PK_H_(0x16, 0x46) ++#define REG_SC_BK16_47_L _PK_L_(0x16, 0x47) ++#define REG_SC_BK16_47_H _PK_H_(0x16, 0x47) ++#define REG_SC_BK16_48_L _PK_L_(0x16, 0x48) ++#define REG_SC_BK16_48_H _PK_H_(0x16, 0x48) ++#define REG_SC_BK16_49_L _PK_L_(0x16, 0x49) ++#define REG_SC_BK16_49_H _PK_H_(0x16, 0x49) ++#define REG_SC_BK16_4A_L _PK_L_(0x16, 0x4A) ++#define REG_SC_BK16_4A_H _PK_H_(0x16, 0x4A) ++#define REG_SC_BK16_4B_L _PK_L_(0x16, 0x4B) ++#define REG_SC_BK16_4B_H _PK_H_(0x16, 0x4B) ++#define REG_SC_BK16_4C_L _PK_L_(0x16, 0x4C) ++#define REG_SC_BK16_4C_H _PK_H_(0x16, 0x4C) ++#define REG_SC_BK16_4D_L _PK_L_(0x16, 0x4D) ++#define REG_SC_BK16_4D_H _PK_H_(0x16, 0x4D) ++#define REG_SC_BK16_4E_L _PK_L_(0x16, 0x4E) ++#define REG_SC_BK16_4E_H _PK_H_(0x16, 0x4E) ++#define REG_SC_BK16_4F_L _PK_L_(0x16, 0x4F) ++#define REG_SC_BK16_4F_H _PK_H_(0x16, 0x4F) ++#define REG_SC_BK16_50_L _PK_L_(0x16, 0x50) ++#define REG_SC_BK16_50_H _PK_H_(0x16, 0x50) ++#define REG_SC_BK16_51_L _PK_L_(0x16, 0x51) ++#define REG_SC_BK16_51_H _PK_H_(0x16, 0x51) ++#define REG_SC_BK16_52_L _PK_L_(0x16, 0x52) ++#define REG_SC_BK16_52_H _PK_H_(0x16, 0x52) ++#define REG_SC_BK16_53_L _PK_L_(0x16, 0x53) ++#define REG_SC_BK16_53_H _PK_H_(0x16, 0x53) ++#define REG_SC_BK16_54_L _PK_L_(0x16, 0x54) ++#define REG_SC_BK16_54_H _PK_H_(0x16, 0x54) ++#define REG_SC_BK16_55_L _PK_L_(0x16, 0x55) ++#define REG_SC_BK16_55_H _PK_H_(0x16, 0x55) ++#define REG_SC_BK16_56_L _PK_L_(0x16, 0x56) ++#define REG_SC_BK16_56_H _PK_H_(0x16, 0x56) ++#define REG_SC_BK16_57_L _PK_L_(0x16, 0x57) ++#define REG_SC_BK16_57_H _PK_H_(0x16, 0x57) ++#define REG_SC_BK16_58_L _PK_L_(0x16, 0x58) ++#define REG_SC_BK16_58_H _PK_H_(0x16, 0x58) ++#define REG_SC_BK16_59_L _PK_L_(0x16, 0x59) ++#define REG_SC_BK16_59_H _PK_H_(0x16, 0x59) ++#define REG_SC_BK16_5A_L _PK_L_(0x16, 0x5A) ++#define REG_SC_BK16_5A_H _PK_H_(0x16, 0x5A) ++#define REG_SC_BK16_5B_L _PK_L_(0x16, 0x5B) ++#define REG_SC_BK16_5B_H _PK_H_(0x16, 0x5B) ++#define REG_SC_BK16_5C_L _PK_L_(0x16, 0x5C) ++#define REG_SC_BK16_5C_H _PK_H_(0x16, 0x5C) ++#define REG_SC_BK16_5D_L _PK_L_(0x16, 0x5D) ++#define REG_SC_BK16_5D_H _PK_H_(0x16, 0x5D) ++#define REG_SC_BK16_5E_L _PK_L_(0x16, 0x5E) ++#define REG_SC_BK16_5E_H _PK_H_(0x16, 0x5E) ++#define REG_SC_BK16_5F_L _PK_L_(0x16, 0x5F) ++#define REG_SC_BK16_5F_H _PK_H_(0x16, 0x5F) ++#define REG_SC_BK16_60_L _PK_L_(0x16, 0x60) ++#define REG_SC_BK16_60_H _PK_H_(0x16, 0x60) ++#define REG_SC_BK16_61_L _PK_L_(0x16, 0x61) ++#define REG_SC_BK16_61_H _PK_H_(0x16, 0x61) ++#define REG_SC_BK16_62_L _PK_L_(0x16, 0x62) ++#define REG_SC_BK16_62_H _PK_H_(0x16, 0x62) ++#define REG_SC_BK16_63_L _PK_L_(0x16, 0x63) ++#define REG_SC_BK16_63_H _PK_H_(0x16, 0x63) ++#define REG_SC_BK16_64_L _PK_L_(0x16, 0x64) ++#define REG_SC_BK16_64_H _PK_H_(0x16, 0x64) ++#define REG_SC_BK16_65_L _PK_L_(0x16, 0x65) ++#define REG_SC_BK16_65_H _PK_H_(0x16, 0x65) ++#define REG_SC_BK16_66_L _PK_L_(0x16, 0x66) ++#define REG_SC_BK16_66_H _PK_H_(0x16, 0x66) ++#define REG_SC_BK16_67_L _PK_L_(0x16, 0x67) ++#define REG_SC_BK16_67_H _PK_H_(0x16, 0x67) ++#define REG_SC_BK16_68_L _PK_L_(0x16, 0x68) ++#define REG_SC_BK16_68_H _PK_H_(0x16, 0x68) ++#define REG_SC_BK16_69_L _PK_L_(0x16, 0x69) ++#define REG_SC_BK16_69_H _PK_H_(0x16, 0x69) ++#define REG_SC_BK16_6A_L _PK_L_(0x16, 0x6A) ++#define REG_SC_BK16_6A_H _PK_H_(0x16, 0x6A) ++#define REG_SC_BK16_6B_L _PK_L_(0x16, 0x6B) ++#define REG_SC_BK16_6B_H _PK_H_(0x16, 0x6B) ++#define REG_SC_BK16_6C_L _PK_L_(0x16, 0x6C) ++#define REG_SC_BK16_6C_H _PK_H_(0x16, 0x6C) ++#define REG_SC_BK16_6D_L _PK_L_(0x16, 0x6D) ++#define REG_SC_BK16_6D_H _PK_H_(0x16, 0x6D) ++#define REG_SC_BK16_6E_L _PK_L_(0x16, 0x6E) ++#define REG_SC_BK16_6E_H _PK_H_(0x16, 0x6E) ++#define REG_SC_BK16_6F_L _PK_L_(0x16, 0x6F) ++#define REG_SC_BK16_6F_H _PK_H_(0x16, 0x6F) ++#define REG_SC_BK16_70_L _PK_L_(0x16, 0x70) ++#define REG_SC_BK16_70_H _PK_H_(0x16, 0x70) ++#define REG_SC_BK16_71_L _PK_L_(0x16, 0x71) ++#define REG_SC_BK16_71_H _PK_H_(0x16, 0x71) ++#define REG_SC_BK16_72_L _PK_L_(0x16, 0x72) ++#define REG_SC_BK16_72_H _PK_H_(0x16, 0x72) ++#define REG_SC_BK16_73_L _PK_L_(0x16, 0x73) ++#define REG_SC_BK16_73_H _PK_H_(0x16, 0x73) ++#define REG_SC_BK16_74_L _PK_L_(0x16, 0x74) ++#define REG_SC_BK16_74_H _PK_H_(0x16, 0x74) ++#define REG_SC_BK16_75_L _PK_L_(0x16, 0x75) ++#define REG_SC_BK16_75_H _PK_H_(0x16, 0x75) ++#define REG_SC_BK16_76_L _PK_L_(0x16, 0x76) ++#define REG_SC_BK16_76_H _PK_H_(0x16, 0x76) ++#define REG_SC_BK16_77_L _PK_L_(0x16, 0x77) ++#define REG_SC_BK16_77_H _PK_H_(0x16, 0x77) ++#define REG_SC_BK16_78_L _PK_L_(0x16, 0x78) ++#define REG_SC_BK16_78_H _PK_H_(0x16, 0x78) ++#define REG_SC_BK16_79_L _PK_L_(0x16, 0x79) ++#define REG_SC_BK16_79_H _PK_H_(0x16, 0x79) ++#define REG_SC_BK16_7A_L _PK_L_(0x16, 0x7A) ++#define REG_SC_BK16_7A_H _PK_H_(0x16, 0x7A) ++#define REG_SC_BK16_7B_L _PK_L_(0x16, 0x7B) ++#define REG_SC_BK16_7B_H _PK_H_(0x16, 0x7B) ++#define REG_SC_BK16_7C_L _PK_L_(0x16, 0x7C) ++#define REG_SC_BK16_7C_H _PK_H_(0x16, 0x7C) ++#define REG_SC_BK16_7D_L _PK_L_(0x16, 0x7D) ++#define REG_SC_BK16_7D_H _PK_H_(0x16, 0x7D) ++#define REG_SC_BK16_7E_L _PK_L_(0x16, 0x7E) ++#define REG_SC_BK16_7E_H _PK_H_(0x16, 0x7E) ++#define REG_SC_BK16_7F_L _PK_L_(0x16, 0x7F) ++#define REG_SC_BK16_7F_H _PK_H_(0x16, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK17_00_L _PK_L_(0x17, 0x00) ++#define REG_SC_BK17_00_H _PK_H_(0x17, 0x00) ++#define REG_SC_BK17_01_L _PK_L_(0x17, 0x01) ++#define REG_SC_BK17_01_H _PK_H_(0x17, 0x01) ++#define REG_SC_BK17_02_L _PK_L_(0x17, 0x02) ++#define REG_SC_BK17_02_H _PK_H_(0x17, 0x02) ++#define REG_SC_BK17_03_L _PK_L_(0x17, 0x03) ++#define REG_SC_BK17_03_H _PK_H_(0x17, 0x03) ++#define REG_SC_BK17_04_L _PK_L_(0x17, 0x04) ++#define REG_SC_BK17_04_H _PK_H_(0x17, 0x04) ++#define REG_SC_BK17_05_L _PK_L_(0x17, 0x05) ++#define REG_SC_BK17_05_H _PK_H_(0x17, 0x05) ++#define REG_SC_BK17_06_L _PK_L_(0x17, 0x06) ++#define REG_SC_BK17_06_H _PK_H_(0x17, 0x06) ++#define REG_SC_BK17_07_L _PK_L_(0x17, 0x07) ++#define REG_SC_BK17_07_H _PK_H_(0x17, 0x07) ++#define REG_SC_BK17_08_L _PK_L_(0x17, 0x08) ++#define REG_SC_BK17_08_H _PK_H_(0x17, 0x08) ++#define REG_SC_BK17_09_L _PK_L_(0x17, 0x09) ++#define REG_SC_BK17_09_H _PK_H_(0x17, 0x09) ++#define REG_SC_BK17_0A_L _PK_L_(0x17, 0x0A) ++#define REG_SC_BK17_0A_H _PK_H_(0x17, 0x0A) ++#define REG_SC_BK17_0B_L _PK_L_(0x17, 0x0B) ++#define REG_SC_BK17_0B_H _PK_H_(0x17, 0x0B) ++#define REG_SC_BK17_0C_L _PK_L_(0x17, 0x0C) ++#define REG_SC_BK17_0C_H _PK_H_(0x17, 0x0C) ++#define REG_SC_BK17_0D_L _PK_L_(0x17, 0x0D) ++#define REG_SC_BK17_0D_H _PK_H_(0x17, 0x0D) ++#define REG_SC_BK17_0E_L _PK_L_(0x17, 0x0E) ++#define REG_SC_BK17_0E_H _PK_H_(0x17, 0x0E) ++#define REG_SC_BK17_0F_L _PK_L_(0x17, 0x0F) ++#define REG_SC_BK17_0F_H _PK_H_(0x17, 0x0F) ++#define REG_SC_BK17_10_L _PK_L_(0x17, 0x10) ++#define REG_SC_BK17_10_H _PK_H_(0x17, 0x10) ++#define REG_SC_BK17_11_L _PK_L_(0x17, 0x11) ++#define REG_SC_BK17_11_H _PK_H_(0x17, 0x11) ++#define REG_SC_BK17_12_L _PK_L_(0x17, 0x12) ++#define REG_SC_BK17_12_H _PK_H_(0x17, 0x12) ++#define REG_SC_BK17_13_L _PK_L_(0x17, 0x13) ++#define REG_SC_BK17_13_H _PK_H_(0x17, 0x13) ++#define REG_SC_BK17_14_L _PK_L_(0x17, 0x14) ++#define REG_SC_BK17_14_H _PK_H_(0x17, 0x14) ++#define REG_SC_BK17_15_L _PK_L_(0x17, 0x15) ++#define REG_SC_BK17_15_H _PK_H_(0x17, 0x15) ++#define REG_SC_BK17_16_L _PK_L_(0x17, 0x16) ++#define REG_SC_BK17_16_H _PK_H_(0x17, 0x16) ++#define REG_SC_BK17_17_L _PK_L_(0x17, 0x17) ++#define REG_SC_BK17_17_H _PK_H_(0x17, 0x17) ++#define REG_SC_BK17_18_L _PK_L_(0x17, 0x18) ++#define REG_SC_BK17_18_H _PK_H_(0x17, 0x18) ++#define REG_SC_BK17_19_L _PK_L_(0x17, 0x19) ++#define REG_SC_BK17_19_H _PK_H_(0x17, 0x19) ++#define REG_SC_BK17_1A_L _PK_L_(0x17, 0x1A) ++#define REG_SC_BK17_1A_H _PK_H_(0x17, 0x1A) ++#define REG_SC_BK17_1B_L _PK_L_(0x17, 0x1B) ++#define REG_SC_BK17_1B_H _PK_H_(0x17, 0x1B) ++#define REG_SC_BK17_1C_L _PK_L_(0x17, 0x1C) ++#define REG_SC_BK17_1C_H _PK_H_(0x17, 0x1C) ++#define REG_SC_BK17_1D_L _PK_L_(0x17, 0x1D) ++#define REG_SC_BK17_1D_H _PK_H_(0x17, 0x1D) ++#define REG_SC_BK17_1E_L _PK_L_(0x17, 0x1E) ++#define REG_SC_BK17_1E_H _PK_H_(0x17, 0x1E) ++#define REG_SC_BK17_1F_L _PK_L_(0x17, 0x1F) ++#define REG_SC_BK17_1F_H _PK_H_(0x17, 0x1F) ++#define REG_SC_BK17_20_L _PK_L_(0x17, 0x20) ++#define REG_SC_BK17_20_H _PK_H_(0x17, 0x20) ++#define REG_SC_BK17_21_L _PK_L_(0x17, 0x21) ++#define REG_SC_BK17_21_H _PK_H_(0x17, 0x21) ++#define REG_SC_BK17_22_L _PK_L_(0x17, 0x22) ++#define REG_SC_BK17_22_H _PK_H_(0x17, 0x22) ++#define REG_SC_BK17_23_L _PK_L_(0x17, 0x23) ++#define REG_SC_BK17_23_H _PK_H_(0x17, 0x23) ++#define REG_SC_BK17_24_L _PK_L_(0x17, 0x24) ++#define REG_SC_BK17_24_H _PK_H_(0x17, 0x24) ++#define REG_SC_BK17_25_L _PK_L_(0x17, 0x25) ++#define REG_SC_BK17_25_H _PK_H_(0x17, 0x25) ++#define REG_SC_BK17_26_L _PK_L_(0x17, 0x26) ++#define REG_SC_BK17_26_H _PK_H_(0x17, 0x26) ++#define REG_SC_BK17_27_L _PK_L_(0x17, 0x27) ++#define REG_SC_BK17_27_H _PK_H_(0x17, 0x27) ++#define REG_SC_BK17_28_L _PK_L_(0x17, 0x28) ++#define REG_SC_BK17_28_H _PK_H_(0x17, 0x28) ++#define REG_SC_BK17_29_L _PK_L_(0x17, 0x29) ++#define REG_SC_BK17_29_H _PK_H_(0x17, 0x29) ++#define REG_SC_BK17_2A_L _PK_L_(0x17, 0x2A) ++#define REG_SC_BK17_2A_H _PK_H_(0x17, 0x2A) ++#define REG_SC_BK17_2B_L _PK_L_(0x17, 0x2B) ++#define REG_SC_BK17_2B_H _PK_H_(0x17, 0x2B) ++#define REG_SC_BK17_2C_L _PK_L_(0x17, 0x2C) ++#define REG_SC_BK17_2C_H _PK_H_(0x17, 0x2C) ++#define REG_SC_BK17_2D_L _PK_L_(0x17, 0x2D) ++#define REG_SC_BK17_2D_H _PK_H_(0x17, 0x2D) ++#define REG_SC_BK17_2E_L _PK_L_(0x17, 0x2E) ++#define REG_SC_BK17_2E_H _PK_H_(0x17, 0x2E) ++#define REG_SC_BK17_2F_L _PK_L_(0x17, 0x2F) ++#define REG_SC_BK17_2F_H _PK_H_(0x17, 0x2F) ++#define REG_SC_BK17_30_L _PK_L_(0x17, 0x30) ++#define REG_SC_BK17_30_H _PK_H_(0x17, 0x30) ++#define REG_SC_BK17_31_L _PK_L_(0x17, 0x31) ++#define REG_SC_BK17_31_H _PK_H_(0x17, 0x31) ++#define REG_SC_BK17_32_L _PK_L_(0x17, 0x32) ++#define REG_SC_BK17_32_H _PK_H_(0x17, 0x32) ++#define REG_SC_BK17_33_L _PK_L_(0x17, 0x33) ++#define REG_SC_BK17_33_H _PK_H_(0x17, 0x33) ++#define REG_SC_BK17_34_L _PK_L_(0x17, 0x34) ++#define REG_SC_BK17_34_H _PK_H_(0x17, 0x34) ++#define REG_SC_BK17_35_L _PK_L_(0x17, 0x35) ++#define REG_SC_BK17_35_H _PK_H_(0x17, 0x35) ++#define REG_SC_BK17_36_L _PK_L_(0x17, 0x36) ++#define REG_SC_BK17_36_H _PK_H_(0x17, 0x36) ++#define REG_SC_BK17_37_L _PK_L_(0x17, 0x37) ++#define REG_SC_BK17_37_H _PK_H_(0x17, 0x37) ++#define REG_SC_BK17_38_L _PK_L_(0x17, 0x38) ++#define REG_SC_BK17_38_H _PK_H_(0x17, 0x38) ++#define REG_SC_BK17_39_L _PK_L_(0x17, 0x39) ++#define REG_SC_BK17_39_H _PK_H_(0x17, 0x39) ++#define REG_SC_BK17_3A_L _PK_L_(0x17, 0x3A) ++#define REG_SC_BK17_3A_H _PK_H_(0x17, 0x3A) ++#define REG_SC_BK17_3B_L _PK_L_(0x17, 0x3B) ++#define REG_SC_BK17_3B_H _PK_H_(0x17, 0x3B) ++#define REG_SC_BK17_3C_L _PK_L_(0x17, 0x3C) ++#define REG_SC_BK17_3C_H _PK_H_(0x17, 0x3C) ++#define REG_SC_BK17_3D_L _PK_L_(0x17, 0x3D) ++#define REG_SC_BK17_3D_H _PK_H_(0x17, 0x3D) ++#define REG_SC_BK17_3E_L _PK_L_(0x17, 0x3E) ++#define REG_SC_BK17_3E_H _PK_H_(0x17, 0x3E) ++#define REG_SC_BK17_3F_L _PK_L_(0x17, 0x3F) ++#define REG_SC_BK17_3F_H _PK_H_(0x17, 0x3F) ++#define REG_SC_BK17_40_L _PK_L_(0x17, 0x40) ++#define REG_SC_BK17_40_H _PK_H_(0x17, 0x40) ++#define REG_SC_BK17_41_L _PK_L_(0x17, 0x41) ++#define REG_SC_BK17_41_H _PK_H_(0x17, 0x41) ++#define REG_SC_BK17_42_L _PK_L_(0x17, 0x42) ++#define REG_SC_BK17_42_H _PK_H_(0x17, 0x42) ++#define REG_SC_BK17_43_L _PK_L_(0x17, 0x43) ++#define REG_SC_BK17_43_H _PK_H_(0x17, 0x43) ++#define REG_SC_BK17_44_L _PK_L_(0x17, 0x44) ++#define REG_SC_BK17_44_H _PK_H_(0x17, 0x44) ++#define REG_SC_BK17_45_L _PK_L_(0x17, 0x45) ++#define REG_SC_BK17_45_H _PK_H_(0x17, 0x45) ++#define REG_SC_BK17_46_L _PK_L_(0x17, 0x46) ++#define REG_SC_BK17_46_H _PK_H_(0x17, 0x46) ++#define REG_SC_BK17_47_L _PK_L_(0x17, 0x47) ++#define REG_SC_BK17_47_H _PK_H_(0x17, 0x47) ++#define REG_SC_BK17_48_L _PK_L_(0x17, 0x48) ++#define REG_SC_BK17_48_H _PK_H_(0x17, 0x48) ++#define REG_SC_BK17_49_L _PK_L_(0x17, 0x49) ++#define REG_SC_BK17_49_H _PK_H_(0x17, 0x49) ++#define REG_SC_BK17_4A_L _PK_L_(0x17, 0x4A) ++#define REG_SC_BK17_4A_H _PK_H_(0x17, 0x4A) ++#define REG_SC_BK17_4B_L _PK_L_(0x17, 0x4B) ++#define REG_SC_BK17_4B_H _PK_H_(0x17, 0x4B) ++#define REG_SC_BK17_4C_L _PK_L_(0x17, 0x4C) ++#define REG_SC_BK17_4C_H _PK_H_(0x17, 0x4C) ++#define REG_SC_BK17_4D_L _PK_L_(0x17, 0x4D) ++#define REG_SC_BK17_4D_H _PK_H_(0x17, 0x4D) ++#define REG_SC_BK17_4E_L _PK_L_(0x17, 0x4E) ++#define REG_SC_BK17_4E_H _PK_H_(0x17, 0x4E) ++#define REG_SC_BK17_4F_L _PK_L_(0x17, 0x4F) ++#define REG_SC_BK17_4F_H _PK_H_(0x17, 0x4F) ++#define REG_SC_BK17_50_L _PK_L_(0x17, 0x50) ++#define REG_SC_BK17_50_H _PK_H_(0x17, 0x50) ++#define REG_SC_BK17_51_L _PK_L_(0x17, 0x51) ++#define REG_SC_BK17_51_H _PK_H_(0x17, 0x51) ++#define REG_SC_BK17_52_L _PK_L_(0x17, 0x52) ++#define REG_SC_BK17_52_H _PK_H_(0x17, 0x52) ++#define REG_SC_BK17_53_L _PK_L_(0x17, 0x53) ++#define REG_SC_BK17_53_H _PK_H_(0x17, 0x53) ++#define REG_SC_BK17_54_L _PK_L_(0x17, 0x54) ++#define REG_SC_BK17_54_H _PK_H_(0x17, 0x54) ++#define REG_SC_BK17_55_L _PK_L_(0x17, 0x55) ++#define REG_SC_BK17_55_H _PK_H_(0x17, 0x55) ++#define REG_SC_BK17_56_L _PK_L_(0x17, 0x56) ++#define REG_SC_BK17_56_H _PK_H_(0x17, 0x56) ++#define REG_SC_BK17_57_L _PK_L_(0x17, 0x57) ++#define REG_SC_BK17_57_H _PK_H_(0x17, 0x57) ++#define REG_SC_BK17_58_L _PK_L_(0x17, 0x58) ++#define REG_SC_BK17_58_H _PK_H_(0x17, 0x58) ++#define REG_SC_BK17_59_L _PK_L_(0x17, 0x59) ++#define REG_SC_BK17_59_H _PK_H_(0x17, 0x59) ++#define REG_SC_BK17_5A_L _PK_L_(0x17, 0x5A) ++#define REG_SC_BK17_5A_H _PK_H_(0x17, 0x5A) ++#define REG_SC_BK17_5B_L _PK_L_(0x17, 0x5B) ++#define REG_SC_BK17_5B_H _PK_H_(0x17, 0x5B) ++#define REG_SC_BK17_5C_L _PK_L_(0x17, 0x5C) ++#define REG_SC_BK17_5C_H _PK_H_(0x17, 0x5C) ++#define REG_SC_BK17_5D_L _PK_L_(0x17, 0x5D) ++#define REG_SC_BK17_5D_H _PK_H_(0x17, 0x5D) ++#define REG_SC_BK17_5E_L _PK_L_(0x17, 0x5E) ++#define REG_SC_BK17_5E_H _PK_H_(0x17, 0x5E) ++#define REG_SC_BK17_5F_L _PK_L_(0x17, 0x5F) ++#define REG_SC_BK17_5F_H _PK_H_(0x17, 0x5F) ++#define REG_SC_BK17_60_L _PK_L_(0x17, 0x60) ++#define REG_SC_BK17_60_H _PK_H_(0x17, 0x60) ++#define REG_SC_BK17_61_L _PK_L_(0x17, 0x61) ++#define REG_SC_BK17_61_H _PK_H_(0x17, 0x61) ++#define REG_SC_BK17_62_L _PK_L_(0x17, 0x62) ++#define REG_SC_BK17_62_H _PK_H_(0x17, 0x62) ++#define REG_SC_BK17_63_L _PK_L_(0x17, 0x63) ++#define REG_SC_BK17_63_H _PK_H_(0x17, 0x63) ++#define REG_SC_BK17_64_L _PK_L_(0x17, 0x64) ++#define REG_SC_BK17_64_H _PK_H_(0x17, 0x64) ++#define REG_SC_BK17_65_L _PK_L_(0x17, 0x65) ++#define REG_SC_BK17_65_H _PK_H_(0x17, 0x65) ++#define REG_SC_BK17_66_L _PK_L_(0x17, 0x66) ++#define REG_SC_BK17_66_H _PK_H_(0x17, 0x66) ++#define REG_SC_BK17_67_L _PK_L_(0x17, 0x67) ++#define REG_SC_BK17_67_H _PK_H_(0x17, 0x67) ++#define REG_SC_BK17_68_L _PK_L_(0x17, 0x68) ++#define REG_SC_BK17_68_H _PK_H_(0x17, 0x68) ++#define REG_SC_BK17_69_L _PK_L_(0x17, 0x69) ++#define REG_SC_BK17_69_H _PK_H_(0x17, 0x69) ++#define REG_SC_BK17_6A_L _PK_L_(0x17, 0x6A) ++#define REG_SC_BK17_6A_H _PK_H_(0x17, 0x6A) ++#define REG_SC_BK17_6B_L _PK_L_(0x17, 0x6B) ++#define REG_SC_BK17_6B_H _PK_H_(0x17, 0x6B) ++#define REG_SC_BK17_6C_L _PK_L_(0x17, 0x6C) ++#define REG_SC_BK17_6C_H _PK_H_(0x17, 0x6C) ++#define REG_SC_BK17_6D_L _PK_L_(0x17, 0x6D) ++#define REG_SC_BK17_6D_H _PK_H_(0x17, 0x6D) ++#define REG_SC_BK17_6E_L _PK_L_(0x17, 0x6E) ++#define REG_SC_BK17_6E_H _PK_H_(0x17, 0x6E) ++#define REG_SC_BK17_6F_L _PK_L_(0x17, 0x6F) ++#define REG_SC_BK17_6F_H _PK_H_(0x17, 0x6F) ++#define REG_SC_BK17_70_L _PK_L_(0x17, 0x70) ++#define REG_SC_BK17_70_H _PK_H_(0x17, 0x70) ++#define REG_SC_BK17_71_L _PK_L_(0x17, 0x71) ++#define REG_SC_BK17_71_H _PK_H_(0x17, 0x71) ++#define REG_SC_BK17_72_L _PK_L_(0x17, 0x72) ++#define REG_SC_BK17_72_H _PK_H_(0x17, 0x72) ++#define REG_SC_BK17_73_L _PK_L_(0x17, 0x73) ++#define REG_SC_BK17_73_H _PK_H_(0x17, 0x73) ++#define REG_SC_BK17_74_L _PK_L_(0x17, 0x74) ++#define REG_SC_BK17_74_H _PK_H_(0x17, 0x74) ++#define REG_SC_BK17_75_L _PK_L_(0x17, 0x75) ++#define REG_SC_BK17_75_H _PK_H_(0x17, 0x75) ++#define REG_SC_BK17_76_L _PK_L_(0x17, 0x76) ++#define REG_SC_BK17_76_H _PK_H_(0x17, 0x76) ++#define REG_SC_BK17_77_L _PK_L_(0x17, 0x77) ++#define REG_SC_BK17_77_H _PK_H_(0x17, 0x77) ++#define REG_SC_BK17_78_L _PK_L_(0x17, 0x78) ++#define REG_SC_BK17_78_H _PK_H_(0x17, 0x78) ++#define REG_SC_BK17_79_L _PK_L_(0x17, 0x79) ++#define REG_SC_BK17_79_H _PK_H_(0x17, 0x79) ++#define REG_SC_BK17_7A_L _PK_L_(0x17, 0x7A) ++#define REG_SC_BK17_7A_H _PK_H_(0x17, 0x7A) ++#define REG_SC_BK17_7B_L _PK_L_(0x17, 0x7B) ++#define REG_SC_BK17_7B_H _PK_H_(0x17, 0x7B) ++#define REG_SC_BK17_7C_L _PK_L_(0x17, 0x7C) ++#define REG_SC_BK17_7C_H _PK_H_(0x17, 0x7C) ++#define REG_SC_BK17_7D_L _PK_L_(0x17, 0x7D) ++#define REG_SC_BK17_7D_H _PK_H_(0x17, 0x7D) ++#define REG_SC_BK17_7E_L _PK_L_(0x17, 0x7E) ++#define REG_SC_BK17_7E_H _PK_H_(0x17, 0x7E) ++#define REG_SC_BK17_7F_L _PK_L_(0x17, 0x7F) ++#define REG_SC_BK17_7F_H _PK_H_(0x17, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK18_00_L _PK_L_(0x18, 0x00) ++#define REG_SC_BK18_00_H _PK_H_(0x18, 0x00) ++#define REG_SC_BK18_01_L _PK_L_(0x18, 0x01) ++#define REG_SC_BK18_01_H _PK_H_(0x18, 0x01) ++#define REG_SC_BK18_02_L _PK_L_(0x18, 0x02) ++#define REG_SC_BK18_02_H _PK_H_(0x18, 0x02) ++#define REG_SC_BK18_03_L _PK_L_(0x18, 0x03) ++#define REG_SC_BK18_03_H _PK_H_(0x18, 0x03) ++#define REG_SC_BK18_04_L _PK_L_(0x18, 0x04) ++#define REG_SC_BK18_04_H _PK_H_(0x18, 0x04) ++#define REG_SC_BK18_05_L _PK_L_(0x18, 0x05) ++#define REG_SC_BK18_05_H _PK_H_(0x18, 0x05) ++#define REG_SC_BK18_06_L _PK_L_(0x18, 0x06) ++#define REG_SC_BK18_06_H _PK_H_(0x18, 0x06) ++#define REG_SC_BK18_07_L _PK_L_(0x18, 0x07) ++#define REG_SC_BK18_07_H _PK_H_(0x18, 0x07) ++#define REG_SC_BK18_08_L _PK_L_(0x18, 0x08) ++#define REG_SC_BK18_08_H _PK_H_(0x18, 0x08) ++#define REG_SC_BK18_09_L _PK_L_(0x18, 0x09) ++#define REG_SC_BK18_09_H _PK_H_(0x18, 0x09) ++#define REG_SC_BK18_0A_L _PK_L_(0x18, 0x0A) ++#define REG_SC_BK18_0A_H _PK_H_(0x18, 0x0A) ++#define REG_SC_BK18_0B_L _PK_L_(0x18, 0x0B) ++#define REG_SC_BK18_0B_H _PK_H_(0x18, 0x0B) ++#define REG_SC_BK18_0C_L _PK_L_(0x18, 0x0C) ++#define REG_SC_BK18_0C_H _PK_H_(0x18, 0x0C) ++#define REG_SC_BK18_0D_L _PK_L_(0x18, 0x0D) ++#define REG_SC_BK18_0D_H _PK_H_(0x18, 0x0D) ++#define REG_SC_BK18_0E_L _PK_L_(0x18, 0x0E) ++#define REG_SC_BK18_0E_H _PK_H_(0x18, 0x0E) ++#define REG_SC_BK18_0F_L _PK_L_(0x18, 0x0F) ++#define REG_SC_BK18_0F_H _PK_H_(0x18, 0x0F) ++#define REG_SC_BK18_10_L _PK_L_(0x18, 0x10) ++#define REG_SC_BK18_10_H _PK_H_(0x18, 0x10) ++#define REG_SC_BK18_11_L _PK_L_(0x18, 0x11) ++#define REG_SC_BK18_11_H _PK_H_(0x18, 0x11) ++#define REG_SC_BK18_12_L _PK_L_(0x18, 0x12) ++#define REG_SC_BK18_12_H _PK_H_(0x18, 0x12) ++#define REG_SC_BK18_13_L _PK_L_(0x18, 0x13) ++#define REG_SC_BK18_13_H _PK_H_(0x18, 0x13) ++#define REG_SC_BK18_14_L _PK_L_(0x18, 0x14) ++#define REG_SC_BK18_14_H _PK_H_(0x18, 0x14) ++#define REG_SC_BK18_15_L _PK_L_(0x18, 0x15) ++#define REG_SC_BK18_15_H _PK_H_(0x18, 0x15) ++#define REG_SC_BK18_16_L _PK_L_(0x18, 0x16) ++#define REG_SC_BK18_16_H _PK_H_(0x18, 0x16) ++#define REG_SC_BK18_17_L _PK_L_(0x18, 0x17) ++#define REG_SC_BK18_17_H _PK_H_(0x18, 0x17) ++#define REG_SC_BK18_18_L _PK_L_(0x18, 0x18) ++#define REG_SC_BK18_18_H _PK_H_(0x18, 0x18) ++#define REG_SC_BK18_19_L _PK_L_(0x18, 0x19) ++#define REG_SC_BK18_19_H _PK_H_(0x18, 0x19) ++#define REG_SC_BK18_1A_L _PK_L_(0x18, 0x1A) ++#define REG_SC_BK18_1A_H _PK_H_(0x18, 0x1A) ++#define REG_SC_BK18_1B_L _PK_L_(0x18, 0x1B) ++#define REG_SC_BK18_1B_H _PK_H_(0x18, 0x1B) ++#define REG_SC_BK18_1C_L _PK_L_(0x18, 0x1C) ++#define REG_SC_BK18_1C_H _PK_H_(0x18, 0x1C) ++#define REG_SC_BK18_1D_L _PK_L_(0x18, 0x1D) ++#define REG_SC_BK18_1D_H _PK_H_(0x18, 0x1D) ++#define REG_SC_BK18_1E_L _PK_L_(0x18, 0x1E) ++#define REG_SC_BK18_1E_H _PK_H_(0x18, 0x1E) ++#define REG_SC_BK18_1F_L _PK_L_(0x18, 0x1F) ++#define REG_SC_BK18_1F_H _PK_H_(0x18, 0x1F) ++#define REG_SC_BK18_20_L _PK_L_(0x18, 0x20) ++#define REG_SC_BK18_20_H _PK_H_(0x18, 0x20) ++#define REG_SC_BK18_21_L _PK_L_(0x18, 0x21) ++#define REG_SC_BK18_21_H _PK_H_(0x18, 0x21) ++#define REG_SC_BK18_22_L _PK_L_(0x18, 0x22) ++#define REG_SC_BK18_22_H _PK_H_(0x18, 0x22) ++#define REG_SC_BK18_23_L _PK_L_(0x18, 0x23) ++#define REG_SC_BK18_23_H _PK_H_(0x18, 0x23) ++#define REG_SC_BK18_24_L _PK_L_(0x18, 0x24) ++#define REG_SC_BK18_24_H _PK_H_(0x18, 0x24) ++#define REG_SC_BK18_25_L _PK_L_(0x18, 0x25) ++#define REG_SC_BK18_25_H _PK_H_(0x18, 0x25) ++#define REG_SC_BK18_26_L _PK_L_(0x18, 0x26) ++#define REG_SC_BK18_26_H _PK_H_(0x18, 0x26) ++#define REG_SC_BK18_27_L _PK_L_(0x18, 0x27) ++#define REG_SC_BK18_27_H _PK_H_(0x18, 0x27) ++#define REG_SC_BK18_28_L _PK_L_(0x18, 0x28) ++#define REG_SC_BK18_28_H _PK_H_(0x18, 0x28) ++#define REG_SC_BK18_29_L _PK_L_(0x18, 0x29) ++#define REG_SC_BK18_29_H _PK_H_(0x18, 0x29) ++#define REG_SC_BK18_2A_L _PK_L_(0x18, 0x2A) ++#define REG_SC_BK18_2A_H _PK_H_(0x18, 0x2A) ++#define REG_SC_BK18_2B_L _PK_L_(0x18, 0x2B) ++#define REG_SC_BK18_2B_H _PK_H_(0x18, 0x2B) ++#define REG_SC_BK18_2C_L _PK_L_(0x18, 0x2C) ++#define REG_SC_BK18_2C_H _PK_H_(0x18, 0x2C) ++#define REG_SC_BK18_2D_L _PK_L_(0x18, 0x2D) ++#define REG_SC_BK18_2D_H _PK_H_(0x18, 0x2D) ++#define REG_SC_BK18_2E_L _PK_L_(0x18, 0x2E) ++#define REG_SC_BK18_2E_H _PK_H_(0x18, 0x2E) ++#define REG_SC_BK18_2F_L _PK_L_(0x18, 0x2F) ++#define REG_SC_BK18_2F_H _PK_H_(0x18, 0x2F) ++#define REG_SC_BK18_30_L _PK_L_(0x18, 0x30) ++#define REG_SC_BK18_30_H _PK_H_(0x18, 0x30) ++#define REG_SC_BK18_31_L _PK_L_(0x18, 0x31) ++#define REG_SC_BK18_31_H _PK_H_(0x18, 0x31) ++#define REG_SC_BK18_32_L _PK_L_(0x18, 0x32) ++#define REG_SC_BK18_32_H _PK_H_(0x18, 0x32) ++#define REG_SC_BK18_33_L _PK_L_(0x18, 0x33) ++#define REG_SC_BK18_33_H _PK_H_(0x18, 0x33) ++#define REG_SC_BK18_34_L _PK_L_(0x18, 0x34) ++#define REG_SC_BK18_34_H _PK_H_(0x18, 0x34) ++#define REG_SC_BK18_35_L _PK_L_(0x18, 0x35) ++#define REG_SC_BK18_35_H _PK_H_(0x18, 0x35) ++#define REG_SC_BK18_36_L _PK_L_(0x18, 0x36) ++#define REG_SC_BK18_36_H _PK_H_(0x18, 0x36) ++#define REG_SC_BK18_37_L _PK_L_(0x18, 0x37) ++#define REG_SC_BK18_37_H _PK_H_(0x18, 0x37) ++#define REG_SC_BK18_38_L _PK_L_(0x18, 0x38) ++#define REG_SC_BK18_38_H _PK_H_(0x18, 0x38) ++#define REG_SC_BK18_39_L _PK_L_(0x18, 0x39) ++#define REG_SC_BK18_39_H _PK_H_(0x18, 0x39) ++#define REG_SC_BK18_3A_L _PK_L_(0x18, 0x3A) ++#define REG_SC_BK18_3A_H _PK_H_(0x18, 0x3A) ++#define REG_SC_BK18_3B_L _PK_L_(0x18, 0x3B) ++#define REG_SC_BK18_3B_H _PK_H_(0x18, 0x3B) ++#define REG_SC_BK18_3C_L _PK_L_(0x18, 0x3C) ++#define REG_SC_BK18_3C_H _PK_H_(0x18, 0x3C) ++#define REG_SC_BK18_3D_L _PK_L_(0x18, 0x3D) ++#define REG_SC_BK18_3D_H _PK_H_(0x18, 0x3D) ++#define REG_SC_BK18_3E_L _PK_L_(0x18, 0x3E) ++#define REG_SC_BK18_3E_H _PK_H_(0x18, 0x3E) ++#define REG_SC_BK18_3F_L _PK_L_(0x18, 0x3F) ++#define REG_SC_BK18_3F_H _PK_H_(0x18, 0x3F) ++#define REG_SC_BK18_40_L _PK_L_(0x18, 0x40) ++#define REG_SC_BK18_40_H _PK_H_(0x18, 0x40) ++#define REG_SC_BK18_41_L _PK_L_(0x18, 0x41) ++#define REG_SC_BK18_41_H _PK_H_(0x18, 0x41) ++#define REG_SC_BK18_42_L _PK_L_(0x18, 0x42) ++#define REG_SC_BK18_42_H _PK_H_(0x18, 0x42) ++#define REG_SC_BK18_43_L _PK_L_(0x18, 0x43) ++#define REG_SC_BK18_43_H _PK_H_(0x18, 0x43) ++#define REG_SC_BK18_44_L _PK_L_(0x18, 0x44) ++#define REG_SC_BK18_44_H _PK_H_(0x18, 0x44) ++#define REG_SC_BK18_45_L _PK_L_(0x18, 0x45) ++#define REG_SC_BK18_45_H _PK_H_(0x18, 0x45) ++#define REG_SC_BK18_46_L _PK_L_(0x18, 0x46) ++#define REG_SC_BK18_46_H _PK_H_(0x18, 0x46) ++#define REG_SC_BK18_47_L _PK_L_(0x18, 0x47) ++#define REG_SC_BK18_47_H _PK_H_(0x18, 0x47) ++#define REG_SC_BK18_48_L _PK_L_(0x18, 0x48) ++#define REG_SC_BK18_48_H _PK_H_(0x18, 0x48) ++#define REG_SC_BK18_49_L _PK_L_(0x18, 0x49) ++#define REG_SC_BK18_49_H _PK_H_(0x18, 0x49) ++#define REG_SC_BK18_4A_L _PK_L_(0x18, 0x4A) ++#define REG_SC_BK18_4A_H _PK_H_(0x18, 0x4A) ++#define REG_SC_BK18_4B_L _PK_L_(0x18, 0x4B) ++#define REG_SC_BK18_4B_H _PK_H_(0x18, 0x4B) ++#define REG_SC_BK18_4C_L _PK_L_(0x18, 0x4C) ++#define REG_SC_BK18_4C_H _PK_H_(0x18, 0x4C) ++#define REG_SC_BK18_4D_L _PK_L_(0x18, 0x4D) ++#define REG_SC_BK18_4D_H _PK_H_(0x18, 0x4D) ++#define REG_SC_BK18_4E_L _PK_L_(0x18, 0x4E) ++#define REG_SC_BK18_4E_H _PK_H_(0x18, 0x4E) ++#define REG_SC_BK18_4F_L _PK_L_(0x18, 0x4F) ++#define REG_SC_BK18_4F_H _PK_H_(0x18, 0x4F) ++#define REG_SC_BK18_50_L _PK_L_(0x18, 0x50) ++#define REG_SC_BK18_50_H _PK_H_(0x18, 0x50) ++#define REG_SC_BK18_51_L _PK_L_(0x18, 0x51) ++#define REG_SC_BK18_51_H _PK_H_(0x18, 0x51) ++#define REG_SC_BK18_52_L _PK_L_(0x18, 0x52) ++#define REG_SC_BK18_52_H _PK_H_(0x18, 0x52) ++#define REG_SC_BK18_53_L _PK_L_(0x18, 0x53) ++#define REG_SC_BK18_53_H _PK_H_(0x18, 0x53) ++#define REG_SC_BK18_54_L _PK_L_(0x18, 0x54) ++#define REG_SC_BK18_54_H _PK_H_(0x18, 0x54) ++#define REG_SC_BK18_55_L _PK_L_(0x18, 0x55) ++#define REG_SC_BK18_55_H _PK_H_(0x18, 0x55) ++#define REG_SC_BK18_56_L _PK_L_(0x18, 0x56) ++#define REG_SC_BK18_56_H _PK_H_(0x18, 0x56) ++#define REG_SC_BK18_57_L _PK_L_(0x18, 0x57) ++#define REG_SC_BK18_57_H _PK_H_(0x18, 0x57) ++#define REG_SC_BK18_58_L _PK_L_(0x18, 0x58) ++#define REG_SC_BK18_58_H _PK_H_(0x18, 0x58) ++#define REG_SC_BK18_59_L _PK_L_(0x18, 0x59) ++#define REG_SC_BK18_59_H _PK_H_(0x18, 0x59) ++#define REG_SC_BK18_5A_L _PK_L_(0x18, 0x5A) ++#define REG_SC_BK18_5A_H _PK_H_(0x18, 0x5A) ++#define REG_SC_BK18_5B_L _PK_L_(0x18, 0x5B) ++#define REG_SC_BK18_5B_H _PK_H_(0x18, 0x5B) ++#define REG_SC_BK18_5C_L _PK_L_(0x18, 0x5C) ++#define REG_SC_BK18_5C_H _PK_H_(0x18, 0x5C) ++#define REG_SC_BK18_5D_L _PK_L_(0x18, 0x5D) ++#define REG_SC_BK18_5D_H _PK_H_(0x18, 0x5D) ++#define REG_SC_BK18_5E_L _PK_L_(0x18, 0x5E) ++#define REG_SC_BK18_5E_H _PK_H_(0x18, 0x5E) ++#define REG_SC_BK18_5F_L _PK_L_(0x18, 0x5F) ++#define REG_SC_BK18_5F_H _PK_H_(0x18, 0x5F) ++#define REG_SC_BK18_60_L _PK_L_(0x18, 0x60) ++#define REG_SC_BK18_60_H _PK_H_(0x18, 0x60) ++#define REG_SC_BK18_61_L _PK_L_(0x18, 0x61) ++#define REG_SC_BK18_61_H _PK_H_(0x18, 0x61) ++#define REG_SC_BK18_62_L _PK_L_(0x18, 0x62) ++#define REG_SC_BK18_62_H _PK_H_(0x18, 0x62) ++#define REG_SC_BK18_63_L _PK_L_(0x18, 0x63) ++#define REG_SC_BK18_63_H _PK_H_(0x18, 0x63) ++#define REG_SC_BK18_64_L _PK_L_(0x18, 0x64) ++#define REG_SC_BK18_64_H _PK_H_(0x18, 0x64) ++#define REG_SC_BK18_65_L _PK_L_(0x18, 0x65) ++#define REG_SC_BK18_65_H _PK_H_(0x18, 0x65) ++#define REG_SC_BK18_66_L _PK_L_(0x18, 0x66) ++#define REG_SC_BK18_66_H _PK_H_(0x18, 0x66) ++#define REG_SC_BK18_67_L _PK_L_(0x18, 0x67) ++#define REG_SC_BK18_67_H _PK_H_(0x18, 0x67) ++#define REG_SC_BK18_68_L _PK_L_(0x18, 0x68) ++#define REG_SC_BK18_68_H _PK_H_(0x18, 0x68) ++#define REG_SC_BK18_69_L _PK_L_(0x18, 0x69) ++#define REG_SC_BK18_69_H _PK_H_(0x18, 0x69) ++#define REG_SC_BK18_6A_L _PK_L_(0x18, 0x6A) ++#define REG_SC_BK18_6A_H _PK_H_(0x18, 0x6A) ++#define REG_SC_BK18_6B_L _PK_L_(0x18, 0x6B) ++#define REG_SC_BK18_6B_H _PK_H_(0x18, 0x6B) ++#define REG_SC_BK18_6C_L _PK_L_(0x18, 0x6C) ++#define REG_SC_BK18_6C_H _PK_H_(0x18, 0x6C) ++#define REG_SC_BK18_6D_L _PK_L_(0x18, 0x6D) ++#define REG_SC_BK18_6D_H _PK_H_(0x18, 0x6D) ++#define REG_SC_BK18_6E_L _PK_L_(0x18, 0x6E) ++#define REG_SC_BK18_6E_H _PK_H_(0x18, 0x6E) ++#define REG_SC_BK18_6F_L _PK_L_(0x18, 0x6F) ++#define REG_SC_BK18_6F_H _PK_H_(0x18, 0x6F) ++#define REG_SC_BK18_70_L _PK_L_(0x18, 0x70) ++#define REG_SC_BK18_70_H _PK_H_(0x18, 0x70) ++#define REG_SC_BK18_71_L _PK_L_(0x18, 0x71) ++#define REG_SC_BK18_71_H _PK_H_(0x18, 0x71) ++#define REG_SC_BK18_72_L _PK_L_(0x18, 0x72) ++#define REG_SC_BK18_72_H _PK_H_(0x18, 0x72) ++#define REG_SC_BK18_73_L _PK_L_(0x18, 0x73) ++#define REG_SC_BK18_73_H _PK_H_(0x18, 0x73) ++#define REG_SC_BK18_74_L _PK_L_(0x18, 0x74) ++#define REG_SC_BK18_74_H _PK_H_(0x18, 0x74) ++#define REG_SC_BK18_75_L _PK_L_(0x18, 0x75) ++#define REG_SC_BK18_75_H _PK_H_(0x18, 0x75) ++#define REG_SC_BK18_76_L _PK_L_(0x18, 0x76) ++#define REG_SC_BK18_76_H _PK_H_(0x18, 0x76) ++#define REG_SC_BK18_77_L _PK_L_(0x18, 0x77) ++#define REG_SC_BK18_77_H _PK_H_(0x18, 0x77) ++#define REG_SC_BK18_78_L _PK_L_(0x18, 0x78) ++#define REG_SC_BK18_78_H _PK_H_(0x18, 0x78) ++#define REG_SC_BK18_79_L _PK_L_(0x18, 0x79) ++#define REG_SC_BK18_79_H _PK_H_(0x18, 0x79) ++#define REG_SC_BK18_7A_L _PK_L_(0x18, 0x7A) ++#define REG_SC_BK18_7A_H _PK_H_(0x18, 0x7A) ++#define REG_SC_BK18_7B_L _PK_L_(0x18, 0x7B) ++#define REG_SC_BK18_7B_H _PK_H_(0x18, 0x7B) ++#define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) ++#define REG_SC_BK18_7C_H _PK_H_(0x18, 0x7C) ++#define REG_SC_BK18_7D_L _PK_L_(0x18, 0x7D) ++#define REG_SC_BK18_7D_H _PK_H_(0x18, 0x7D) ++#define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) ++#define REG_SC_BK18_7E_H _PK_H_(0x18, 0x7E) ++#define REG_SC_BK18_7F_L _PK_L_(0x18, 0x7F) ++#define REG_SC_BK18_7F_H _PK_H_(0x18, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK19_00_L _PK_L_(0x19, 0x00) ++#define REG_SC_BK19_00_H _PK_H_(0x19, 0x00) ++#define REG_SC_BK19_01_L _PK_L_(0x19, 0x01) ++#define REG_SC_BK19_01_H _PK_H_(0x19, 0x01) ++#define REG_SC_BK19_02_L _PK_L_(0x19, 0x02) ++#define REG_SC_BK19_02_H _PK_H_(0x19, 0x02) ++#define REG_SC_BK19_03_L _PK_L_(0x19, 0x03) ++#define REG_SC_BK19_03_H _PK_H_(0x19, 0x03) ++#define REG_SC_BK19_04_L _PK_L_(0x19, 0x04) ++#define REG_SC_BK19_04_H _PK_H_(0x19, 0x04) ++#define REG_SC_BK19_05_L _PK_L_(0x19, 0x05) ++#define REG_SC_BK19_05_H _PK_H_(0x19, 0x05) ++#define REG_SC_BK19_06_L _PK_L_(0x19, 0x06) ++#define REG_SC_BK19_06_H _PK_H_(0x19, 0x06) ++#define REG_SC_BK19_07_L _PK_L_(0x19, 0x07) ++#define REG_SC_BK19_07_H _PK_H_(0x19, 0x07) ++#define REG_SC_BK19_08_L _PK_L_(0x19, 0x08) ++#define REG_SC_BK19_08_H _PK_H_(0x19, 0x08) ++#define REG_SC_BK19_09_L _PK_L_(0x19, 0x09) ++#define REG_SC_BK19_09_H _PK_H_(0x19, 0x09) ++#define REG_SC_BK19_0A_L _PK_L_(0x19, 0x0A) ++#define REG_SC_BK19_0A_H _PK_H_(0x19, 0x0A) ++#define REG_SC_BK19_0B_L _PK_L_(0x19, 0x0B) ++#define REG_SC_BK19_0B_H _PK_H_(0x19, 0x0B) ++#define REG_SC_BK19_0C_L _PK_L_(0x19, 0x0C) ++#define REG_SC_BK19_0C_H _PK_H_(0x19, 0x0C) ++#define REG_SC_BK19_0D_L _PK_L_(0x19, 0x0D) ++#define REG_SC_BK19_0D_H _PK_H_(0x19, 0x0D) ++#define REG_SC_BK19_0E_L _PK_L_(0x19, 0x0E) ++#define REG_SC_BK19_0E_H _PK_H_(0x19, 0x0E) ++#define REG_SC_BK19_0F_L _PK_L_(0x19, 0x0F) ++#define REG_SC_BK19_0F_H _PK_H_(0x19, 0x0F) ++#define REG_SC_BK19_10_L _PK_L_(0x19, 0x10) ++#define REG_SC_BK19_10_H _PK_H_(0x19, 0x10) ++#define REG_SC_BK19_11_L _PK_L_(0x19, 0x11) ++#define REG_SC_BK19_11_H _PK_H_(0x19, 0x11) ++#define REG_SC_BK19_12_L _PK_L_(0x19, 0x12) ++#define REG_SC_BK19_12_H _PK_H_(0x19, 0x12) ++#define REG_SC_BK19_13_L _PK_L_(0x19, 0x13) ++#define REG_SC_BK19_13_H _PK_H_(0x19, 0x13) ++#define REG_SC_BK19_14_L _PK_L_(0x19, 0x14) ++#define REG_SC_BK19_14_H _PK_H_(0x19, 0x14) ++#define REG_SC_BK19_15_L _PK_L_(0x19, 0x15) ++#define REG_SC_BK19_15_H _PK_H_(0x19, 0x15) ++#define REG_SC_BK19_16_L _PK_L_(0x19, 0x16) ++#define REG_SC_BK19_16_H _PK_H_(0x19, 0x16) ++#define REG_SC_BK19_17_L _PK_L_(0x19, 0x17) ++#define REG_SC_BK19_17_H _PK_H_(0x19, 0x17) ++#define REG_SC_BK19_18_L _PK_L_(0x19, 0x18) ++#define REG_SC_BK19_18_H _PK_H_(0x19, 0x18) ++#define REG_SC_BK19_19_L _PK_L_(0x19, 0x19) ++#define REG_SC_BK19_19_H _PK_H_(0x19, 0x19) ++#define REG_SC_BK19_1A_L _PK_L_(0x19, 0x1A) ++#define REG_SC_BK19_1A_H _PK_H_(0x19, 0x1A) ++#define REG_SC_BK19_1B_L _PK_L_(0x19, 0x1B) ++#define REG_SC_BK19_1B_H _PK_H_(0x19, 0x1B) ++#define REG_SC_BK19_1C_L _PK_L_(0x19, 0x1C) ++#define REG_SC_BK19_1C_H _PK_H_(0x19, 0x1C) ++#define REG_SC_BK19_1D_L _PK_L_(0x19, 0x1D) ++#define REG_SC_BK19_1D_H _PK_H_(0x19, 0x1D) ++#define REG_SC_BK19_1E_L _PK_L_(0x19, 0x1E) ++#define REG_SC_BK19_1E_H _PK_H_(0x19, 0x1E) ++#define REG_SC_BK19_1F_L _PK_L_(0x19, 0x1F) ++#define REG_SC_BK19_1F_H _PK_H_(0x19, 0x1F) ++#define REG_SC_BK19_20_L _PK_L_(0x19, 0x20) ++#define REG_SC_BK19_20_H _PK_H_(0x19, 0x20) ++#define REG_SC_BK19_21_L _PK_L_(0x19, 0x21) ++#define REG_SC_BK19_21_H _PK_H_(0x19, 0x21) ++#define REG_SC_BK19_22_L _PK_L_(0x19, 0x22) ++#define REG_SC_BK19_22_H _PK_H_(0x19, 0x22) ++#define REG_SC_BK19_23_L _PK_L_(0x19, 0x23) ++#define REG_SC_BK19_23_H _PK_H_(0x19, 0x23) ++#define REG_SC_BK19_24_L _PK_L_(0x19, 0x24) ++#define REG_SC_BK19_24_H _PK_H_(0x19, 0x24) ++#define REG_SC_BK19_25_L _PK_L_(0x19, 0x25) ++#define REG_SC_BK19_25_H _PK_H_(0x19, 0x25) ++#define REG_SC_BK19_26_L _PK_L_(0x19, 0x26) ++#define REG_SC_BK19_26_H _PK_H_(0x19, 0x26) ++#define REG_SC_BK19_27_L _PK_L_(0x19, 0x27) ++#define REG_SC_BK19_27_H _PK_H_(0x19, 0x27) ++#define REG_SC_BK19_28_L _PK_L_(0x19, 0x28) ++#define REG_SC_BK19_28_H _PK_H_(0x19, 0x28) ++#define REG_SC_BK19_29_L _PK_L_(0x19, 0x29) ++#define REG_SC_BK19_29_H _PK_H_(0x19, 0x29) ++#define REG_SC_BK19_2A_L _PK_L_(0x19, 0x2A) ++#define REG_SC_BK19_2A_H _PK_H_(0x19, 0x2A) ++#define REG_SC_BK19_2B_L _PK_L_(0x19, 0x2B) ++#define REG_SC_BK19_2B_H _PK_H_(0x19, 0x2B) ++#define REG_SC_BK19_2C_L _PK_L_(0x19, 0x2C) ++#define REG_SC_BK19_2C_H _PK_H_(0x19, 0x2C) ++#define REG_SC_BK19_2D_L _PK_L_(0x19, 0x2D) ++#define REG_SC_BK19_2D_H _PK_H_(0x19, 0x2D) ++#define REG_SC_BK19_2E_L _PK_L_(0x19, 0x2E) ++#define REG_SC_BK19_2E_H _PK_H_(0x19, 0x2E) ++#define REG_SC_BK19_2F_L _PK_L_(0x19, 0x2F) ++#define REG_SC_BK19_2F_H _PK_H_(0x19, 0x2F) ++#define REG_SC_BK19_30_L _PK_L_(0x19, 0x30) ++#define REG_SC_BK19_30_H _PK_H_(0x19, 0x30) ++#define REG_SC_BK19_31_L _PK_L_(0x19, 0x31) ++#define REG_SC_BK19_31_H _PK_H_(0x19, 0x31) ++#define REG_SC_BK19_32_L _PK_L_(0x19, 0x32) ++#define REG_SC_BK19_32_H _PK_H_(0x19, 0x32) ++#define REG_SC_BK19_33_L _PK_L_(0x19, 0x33) ++#define REG_SC_BK19_33_H _PK_H_(0x19, 0x33) ++#define REG_SC_BK19_34_L _PK_L_(0x19, 0x34) ++#define REG_SC_BK19_34_H _PK_H_(0x19, 0x34) ++#define REG_SC_BK19_35_L _PK_L_(0x19, 0x35) ++#define REG_SC_BK19_35_H _PK_H_(0x19, 0x35) ++#define REG_SC_BK19_36_L _PK_L_(0x19, 0x36) ++#define REG_SC_BK19_36_H _PK_H_(0x19, 0x36) ++#define REG_SC_BK19_37_L _PK_L_(0x19, 0x37) ++#define REG_SC_BK19_37_H _PK_H_(0x19, 0x37) ++#define REG_SC_BK19_38_L _PK_L_(0x19, 0x38) ++#define REG_SC_BK19_38_H _PK_H_(0x19, 0x38) ++#define REG_SC_BK19_39_L _PK_L_(0x19, 0x39) ++#define REG_SC_BK19_39_H _PK_H_(0x19, 0x39) ++#define REG_SC_BK19_3A_L _PK_L_(0x19, 0x3A) ++#define REG_SC_BK19_3A_H _PK_H_(0x19, 0x3A) ++#define REG_SC_BK19_3B_L _PK_L_(0x19, 0x3B) ++#define REG_SC_BK19_3B_H _PK_H_(0x19, 0x3B) ++#define REG_SC_BK19_3C_L _PK_L_(0x19, 0x3C) ++#define REG_SC_BK19_3C_H _PK_H_(0x19, 0x3C) ++#define REG_SC_BK19_3D_L _PK_L_(0x19, 0x3D) ++#define REG_SC_BK19_3D_H _PK_H_(0x19, 0x3D) ++#define REG_SC_BK19_3E_L _PK_L_(0x19, 0x3E) ++#define REG_SC_BK19_3E_H _PK_H_(0x19, 0x3E) ++#define REG_SC_BK19_3F_L _PK_L_(0x19, 0x3F) ++#define REG_SC_BK19_3F_H _PK_H_(0x19, 0x3F) ++#define REG_SC_BK19_40_L _PK_L_(0x19, 0x40) ++#define REG_SC_BK19_40_H _PK_H_(0x19, 0x40) ++#define REG_SC_BK19_41_L _PK_L_(0x19, 0x41) ++#define REG_SC_BK19_41_H _PK_H_(0x19, 0x41) ++#define REG_SC_BK19_42_L _PK_L_(0x19, 0x42) ++#define REG_SC_BK19_42_H _PK_H_(0x19, 0x42) ++#define REG_SC_BK19_43_L _PK_L_(0x19, 0x43) ++#define REG_SC_BK19_43_H _PK_H_(0x19, 0x43) ++#define REG_SC_BK19_44_L _PK_L_(0x19, 0x44) ++#define REG_SC_BK19_44_H _PK_H_(0x19, 0x44) ++#define REG_SC_BK19_45_L _PK_L_(0x19, 0x45) ++#define REG_SC_BK19_45_H _PK_H_(0x19, 0x45) ++#define REG_SC_BK19_46_L _PK_L_(0x19, 0x46) ++#define REG_SC_BK19_46_H _PK_H_(0x19, 0x46) ++#define REG_SC_BK19_47_L _PK_L_(0x19, 0x47) ++#define REG_SC_BK19_47_H _PK_H_(0x19, 0x47) ++#define REG_SC_BK19_48_L _PK_L_(0x19, 0x48) ++#define REG_SC_BK19_48_H _PK_H_(0x19, 0x48) ++#define REG_SC_BK19_49_L _PK_L_(0x19, 0x49) ++#define REG_SC_BK19_49_H _PK_H_(0x19, 0x49) ++#define REG_SC_BK19_4A_L _PK_L_(0x19, 0x4A) ++#define REG_SC_BK19_4A_H _PK_H_(0x19, 0x4A) ++#define REG_SC_BK19_4B_L _PK_L_(0x19, 0x4B) ++#define REG_SC_BK19_4B_H _PK_H_(0x19, 0x4B) ++#define REG_SC_BK19_4C_L _PK_L_(0x19, 0x4C) ++#define REG_SC_BK19_4C_H _PK_H_(0x19, 0x4C) ++#define REG_SC_BK19_4D_L _PK_L_(0x19, 0x4D) ++#define REG_SC_BK19_4D_H _PK_H_(0x19, 0x4D) ++#define REG_SC_BK19_4E_L _PK_L_(0x19, 0x4E) ++#define REG_SC_BK19_4E_H _PK_H_(0x19, 0x4E) ++#define REG_SC_BK19_4F_L _PK_L_(0x19, 0x4F) ++#define REG_SC_BK19_4F_H _PK_H_(0x19, 0x4F) ++#define REG_SC_BK19_50_L _PK_L_(0x19, 0x50) ++#define REG_SC_BK19_50_H _PK_H_(0x19, 0x50) ++#define REG_SC_BK19_51_L _PK_L_(0x19, 0x51) ++#define REG_SC_BK19_51_H _PK_H_(0x19, 0x51) ++#define REG_SC_BK19_52_L _PK_L_(0x19, 0x52) ++#define REG_SC_BK19_52_H _PK_H_(0x19, 0x52) ++#define REG_SC_BK19_53_L _PK_L_(0x19, 0x53) ++#define REG_SC_BK19_53_H _PK_H_(0x19, 0x53) ++#define REG_SC_BK19_54_L _PK_L_(0x19, 0x54) ++#define REG_SC_BK19_54_H _PK_H_(0x19, 0x54) ++#define REG_SC_BK19_55_L _PK_L_(0x19, 0x55) ++#define REG_SC_BK19_55_H _PK_H_(0x19, 0x55) ++#define REG_SC_BK19_56_L _PK_L_(0x19, 0x56) ++#define REG_SC_BK19_56_H _PK_H_(0x19, 0x56) ++#define REG_SC_BK19_57_L _PK_L_(0x19, 0x57) ++#define REG_SC_BK19_57_H _PK_H_(0x19, 0x57) ++#define REG_SC_BK19_58_L _PK_L_(0x19, 0x58) ++#define REG_SC_BK19_58_H _PK_H_(0x19, 0x58) ++#define REG_SC_BK19_59_L _PK_L_(0x19, 0x59) ++#define REG_SC_BK19_59_H _PK_H_(0x19, 0x59) ++#define REG_SC_BK19_5A_L _PK_L_(0x19, 0x5A) ++#define REG_SC_BK19_5A_H _PK_H_(0x19, 0x5A) ++#define REG_SC_BK19_5B_L _PK_L_(0x19, 0x5B) ++#define REG_SC_BK19_5B_H _PK_H_(0x19, 0x5B) ++#define REG_SC_BK19_5C_L _PK_L_(0x19, 0x5C) ++#define REG_SC_BK19_5C_H _PK_H_(0x19, 0x5C) ++#define REG_SC_BK19_5D_L _PK_L_(0x19, 0x5D) ++#define REG_SC_BK19_5D_H _PK_H_(0x19, 0x5D) ++#define REG_SC_BK19_5E_L _PK_L_(0x19, 0x5E) ++#define REG_SC_BK19_5E_H _PK_H_(0x19, 0x5E) ++#define REG_SC_BK19_5F_L _PK_L_(0x19, 0x5F) ++#define REG_SC_BK19_5F_H _PK_H_(0x19, 0x5F) ++#define REG_SC_BK19_60_L _PK_L_(0x19, 0x60) ++#define REG_SC_BK19_60_H _PK_H_(0x19, 0x60) ++#define REG_SC_BK19_61_L _PK_L_(0x19, 0x61) ++#define REG_SC_BK19_61_H _PK_H_(0x19, 0x61) ++#define REG_SC_BK19_62_L _PK_L_(0x19, 0x62) ++#define REG_SC_BK19_62_H _PK_H_(0x19, 0x62) ++#define REG_SC_BK19_63_L _PK_L_(0x19, 0x63) ++#define REG_SC_BK19_63_H _PK_H_(0x19, 0x63) ++#define REG_SC_BK19_64_L _PK_L_(0x19, 0x64) ++#define REG_SC_BK19_64_H _PK_H_(0x19, 0x64) ++#define REG_SC_BK19_65_L _PK_L_(0x19, 0x65) ++#define REG_SC_BK19_65_H _PK_H_(0x19, 0x65) ++#define REG_SC_BK19_66_L _PK_L_(0x19, 0x66) ++#define REG_SC_BK19_66_H _PK_H_(0x19, 0x66) ++#define REG_SC_BK19_67_L _PK_L_(0x19, 0x67) ++#define REG_SC_BK19_67_H _PK_H_(0x19, 0x67) ++#define REG_SC_BK19_68_L _PK_L_(0x19, 0x68) ++#define REG_SC_BK19_68_H _PK_H_(0x19, 0x68) ++#define REG_SC_BK19_69_L _PK_L_(0x19, 0x69) ++#define REG_SC_BK19_69_H _PK_H_(0x19, 0x69) ++#define REG_SC_BK19_6A_L _PK_L_(0x19, 0x6A) ++#define REG_SC_BK19_6A_H _PK_H_(0x19, 0x6A) ++#define REG_SC_BK19_6B_L _PK_L_(0x19, 0x6B) ++#define REG_SC_BK19_6B_H _PK_H_(0x19, 0x6B) ++#define REG_SC_BK19_6C_L _PK_L_(0x19, 0x6C) ++#define REG_SC_BK19_6C_H _PK_H_(0x19, 0x6C) ++#define REG_SC_BK19_6D_L _PK_L_(0x19, 0x6D) ++#define REG_SC_BK19_6D_H _PK_H_(0x19, 0x6D) ++#define REG_SC_BK19_6E_L _PK_L_(0x19, 0x6E) ++#define REG_SC_BK19_6E_H _PK_H_(0x19, 0x6E) ++#define REG_SC_BK19_6F_L _PK_L_(0x19, 0x6F) ++#define REG_SC_BK19_6F_H _PK_H_(0x19, 0x6F) ++#define REG_SC_BK19_70_L _PK_L_(0x19, 0x70) ++#define REG_SC_BK19_70_H _PK_H_(0x19, 0x70) ++#define REG_SC_BK19_71_L _PK_L_(0x19, 0x71) ++#define REG_SC_BK19_71_H _PK_H_(0x19, 0x71) ++#define REG_SC_BK19_72_L _PK_L_(0x19, 0x72) ++#define REG_SC_BK19_72_H _PK_H_(0x19, 0x72) ++#define REG_SC_BK19_73_L _PK_L_(0x19, 0x73) ++#define REG_SC_BK19_73_H _PK_H_(0x19, 0x73) ++#define REG_SC_BK19_74_L _PK_L_(0x19, 0x74) ++#define REG_SC_BK19_74_H _PK_H_(0x19, 0x74) ++#define REG_SC_BK19_75_L _PK_L_(0x19, 0x75) ++#define REG_SC_BK19_75_H _PK_H_(0x19, 0x75) ++#define REG_SC_BK19_76_L _PK_L_(0x19, 0x76) ++#define REG_SC_BK19_76_H _PK_H_(0x19, 0x76) ++#define REG_SC_BK19_77_L _PK_L_(0x19, 0x77) ++#define REG_SC_BK19_77_H _PK_H_(0x19, 0x77) ++#define REG_SC_BK19_78_L _PK_L_(0x19, 0x78) ++#define REG_SC_BK19_78_H _PK_H_(0x19, 0x78) ++#define REG_SC_BK19_79_L _PK_L_(0x19, 0x79) ++#define REG_SC_BK19_79_H _PK_H_(0x19, 0x79) ++#define REG_SC_BK19_7A_L _PK_L_(0x19, 0x7A) ++#define REG_SC_BK19_7A_H _PK_H_(0x19, 0x7A) ++#define REG_SC_BK19_7B_L _PK_L_(0x19, 0x7B) ++#define REG_SC_BK19_7B_H _PK_H_(0x19, 0x7B) ++#define REG_SC_BK19_7C_L _PK_L_(0x19, 0x7C) ++#define REG_SC_BK19_7C_H _PK_H_(0x19, 0x7C) ++#define REG_SC_BK19_7D_L _PK_L_(0x19, 0x7D) ++#define REG_SC_BK19_7D_H _PK_H_(0x19, 0x7D) ++#define REG_SC_BK19_7E_L _PK_L_(0x19, 0x7E) ++#define REG_SC_BK19_7E_H _PK_H_(0x19, 0x7E) ++#define REG_SC_BK19_7F_L _PK_L_(0x19, 0x7F) ++#define REG_SC_BK19_7F_H _PK_H_(0x19, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1A_00_L _PK_L_(0x1A, 0x00) ++#define REG_SC_BK1A_00_H _PK_H_(0x1A, 0x00) ++#define REG_SC_BK1A_01_L _PK_L_(0x1A, 0x01) ++#define REG_SC_BK1A_01_H _PK_H_(0x1A, 0x01) ++#define REG_SC_BK1A_02_L _PK_L_(0x1A, 0x02) ++#define REG_SC_BK1A_02_H _PK_H_(0x1A, 0x02) ++#define REG_SC_BK1A_03_L _PK_L_(0x1A, 0x03) ++#define REG_SC_BK1A_03_H _PK_H_(0x1A, 0x03) ++#define REG_SC_BK1A_04_L _PK_L_(0x1A, 0x04) ++#define REG_SC_BK1A_04_H _PK_H_(0x1A, 0x04) ++#define REG_SC_BK1A_05_L _PK_L_(0x1A, 0x05) ++#define REG_SC_BK1A_05_H _PK_H_(0x1A, 0x05) ++#define REG_SC_BK1A_06_L _PK_L_(0x1A, 0x06) ++#define REG_SC_BK1A_06_H _PK_H_(0x1A, 0x06) ++#define REG_SC_BK1A_07_L _PK_L_(0x1A, 0x07) ++#define REG_SC_BK1A_07_H _PK_H_(0x1A, 0x07) ++#define REG_SC_BK1A_08_L _PK_L_(0x1A, 0x08) ++#define REG_SC_BK1A_08_H _PK_H_(0x1A, 0x08) ++#define REG_SC_BK1A_09_L _PK_L_(0x1A, 0x09) ++#define REG_SC_BK1A_09_H _PK_H_(0x1A, 0x09) ++#define REG_SC_BK1A_0A_L _PK_L_(0x1A, 0x0A) ++#define REG_SC_BK1A_0A_H _PK_H_(0x1A, 0x0A) ++#define REG_SC_BK1A_0B_L _PK_L_(0x1A, 0x0B) ++#define REG_SC_BK1A_0B_H _PK_H_(0x1A, 0x0B) ++#define REG_SC_BK1A_0C_L _PK_L_(0x1A, 0x0C) ++#define REG_SC_BK1A_0C_H _PK_H_(0x1A, 0x0C) ++#define REG_SC_BK1A_0D_L _PK_L_(0x1A, 0x0D) ++#define REG_SC_BK1A_0D_H _PK_H_(0x1A, 0x0D) ++#define REG_SC_BK1A_0E_L _PK_L_(0x1A, 0x0E) ++#define REG_SC_BK1A_0E_H _PK_H_(0x1A, 0x0E) ++#define REG_SC_BK1A_0F_L _PK_L_(0x1A, 0x0F) ++#define REG_SC_BK1A_0F_H _PK_H_(0x1A, 0x0F) ++#define REG_SC_BK1A_10_L _PK_L_(0x1A, 0x10) ++#define REG_SC_BK1A_10_H _PK_H_(0x1A, 0x10) ++#define REG_SC_BK1A_11_L _PK_L_(0x1A, 0x11) ++#define REG_SC_BK1A_11_H _PK_H_(0x1A, 0x11) ++#define REG_SC_BK1A_12_L _PK_L_(0x1A, 0x12) ++#define REG_SC_BK1A_12_H _PK_H_(0x1A, 0x12) ++#define REG_SC_BK1A_13_L _PK_L_(0x1A, 0x13) ++#define REG_SC_BK1A_13_H _PK_H_(0x1A, 0x13) ++#define REG_SC_BK1A_14_L _PK_L_(0x1A, 0x14) ++#define REG_SC_BK1A_14_H _PK_H_(0x1A, 0x14) ++#define REG_SC_BK1A_15_L _PK_L_(0x1A, 0x15) ++#define REG_SC_BK1A_15_H _PK_H_(0x1A, 0x15) ++#define REG_SC_BK1A_16_L _PK_L_(0x1A, 0x16) ++#define REG_SC_BK1A_16_H _PK_H_(0x1A, 0x16) ++#define REG_SC_BK1A_17_L _PK_L_(0x1A, 0x17) ++#define REG_SC_BK1A_17_H _PK_H_(0x1A, 0x17) ++#define REG_SC_BK1A_18_L _PK_L_(0x1A, 0x18) ++#define REG_SC_BK1A_18_H _PK_H_(0x1A, 0x18) ++#define REG_SC_BK1A_19_L _PK_L_(0x1A, 0x19) ++#define REG_SC_BK1A_19_H _PK_H_(0x1A, 0x19) ++#define REG_SC_BK1A_1A_L _PK_L_(0x1A, 0x1A) ++#define REG_SC_BK1A_1A_H _PK_H_(0x1A, 0x1A) ++#define REG_SC_BK1A_1B_L _PK_L_(0x1A, 0x1B) ++#define REG_SC_BK1A_1B_H _PK_H_(0x1A, 0x1B) ++#define REG_SC_BK1A_1C_L _PK_L_(0x1A, 0x1C) ++#define REG_SC_BK1A_1C_H _PK_H_(0x1A, 0x1C) ++#define REG_SC_BK1A_1D_L _PK_L_(0x1A, 0x1D) ++#define REG_SC_BK1A_1D_H _PK_H_(0x1A, 0x1D) ++#define REG_SC_BK1A_1E_L _PK_L_(0x1A, 0x1E) ++#define REG_SC_BK1A_1E_H _PK_H_(0x1A, 0x1E) ++#define REG_SC_BK1A_1F_L _PK_L_(0x1A, 0x1F) ++#define REG_SC_BK1A_1F_H _PK_H_(0x1A, 0x1F) ++#define REG_SC_BK1A_20_L _PK_L_(0x1A, 0x20) ++#define REG_SC_BK1A_20_H _PK_H_(0x1A, 0x20) ++#define REG_SC_BK1A_21_L _PK_L_(0x1A, 0x21) ++#define REG_SC_BK1A_21_H _PK_H_(0x1A, 0x21) ++#define REG_SC_BK1A_22_L _PK_L_(0x1A, 0x22) ++#define REG_SC_BK1A_22_H _PK_H_(0x1A, 0x22) ++#define REG_SC_BK1A_23_L _PK_L_(0x1A, 0x23) ++#define REG_SC_BK1A_23_H _PK_H_(0x1A, 0x23) ++#define REG_SC_BK1A_24_L _PK_L_(0x1A, 0x24) ++#define REG_SC_BK1A_24_H _PK_H_(0x1A, 0x24) ++#define REG_SC_BK1A_25_L _PK_L_(0x1A, 0x25) ++#define REG_SC_BK1A_25_H _PK_H_(0x1A, 0x25) ++#define REG_SC_BK1A_26_L _PK_L_(0x1A, 0x26) ++#define REG_SC_BK1A_26_H _PK_H_(0x1A, 0x26) ++#define REG_SC_BK1A_27_L _PK_L_(0x1A, 0x27) ++#define REG_SC_BK1A_27_H _PK_H_(0x1A, 0x27) ++#define REG_SC_BK1A_28_L _PK_L_(0x1A, 0x28) ++#define REG_SC_BK1A_28_H _PK_H_(0x1A, 0x28) ++#define REG_SC_BK1A_29_L _PK_L_(0x1A, 0x29) ++#define REG_SC_BK1A_29_H _PK_H_(0x1A, 0x29) ++#define REG_SC_BK1A_2A_L _PK_L_(0x1A, 0x2A) ++#define REG_SC_BK1A_2A_H _PK_H_(0x1A, 0x2A) ++#define REG_SC_BK1A_2B_L _PK_L_(0x1A, 0x2B) ++#define REG_SC_BK1A_2B_H _PK_H_(0x1A, 0x2B) ++#define REG_SC_BK1A_2C_L _PK_L_(0x1A, 0x2C) ++#define REG_SC_BK1A_2C_H _PK_H_(0x1A, 0x2C) ++#define REG_SC_BK1A_2D_L _PK_L_(0x1A, 0x2D) ++#define REG_SC_BK1A_2D_H _PK_H_(0x1A, 0x2D) ++#define REG_SC_BK1A_2E_L _PK_L_(0x1A, 0x2E) ++#define REG_SC_BK1A_2E_H _PK_H_(0x1A, 0x2E) ++#define REG_SC_BK1A_2F_L _PK_L_(0x1A, 0x2F) ++#define REG_SC_BK1A_2F_H _PK_H_(0x1A, 0x2F) ++#define REG_SC_BK1A_30_L _PK_L_(0x1A, 0x30) ++#define REG_SC_BK1A_30_H _PK_H_(0x1A, 0x30) ++#define REG_SC_BK1A_31_L _PK_L_(0x1A, 0x31) ++#define REG_SC_BK1A_31_H _PK_H_(0x1A, 0x31) ++#define REG_SC_BK1A_32_L _PK_L_(0x1A, 0x32) ++#define REG_SC_BK1A_32_H _PK_H_(0x1A, 0x32) ++#define REG_SC_BK1A_33_L _PK_L_(0x1A, 0x33) ++#define REG_SC_BK1A_33_H _PK_H_(0x1A, 0x33) ++#define REG_SC_BK1A_34_L _PK_L_(0x1A, 0x34) ++#define REG_SC_BK1A_34_H _PK_H_(0x1A, 0x34) ++#define REG_SC_BK1A_35_L _PK_L_(0x1A, 0x35) ++#define REG_SC_BK1A_35_H _PK_H_(0x1A, 0x35) ++#define REG_SC_BK1A_36_L _PK_L_(0x1A, 0x36) ++#define REG_SC_BK1A_36_H _PK_H_(0x1A, 0x36) ++#define REG_SC_BK1A_37_L _PK_L_(0x1A, 0x37) ++#define REG_SC_BK1A_37_H _PK_H_(0x1A, 0x37) ++#define REG_SC_BK1A_38_L _PK_L_(0x1A, 0x38) ++#define REG_SC_BK1A_38_H _PK_H_(0x1A, 0x38) ++#define REG_SC_BK1A_39_L _PK_L_(0x1A, 0x39) ++#define REG_SC_BK1A_39_H _PK_H_(0x1A, 0x39) ++#define REG_SC_BK1A_3A_L _PK_L_(0x1A, 0x3A) ++#define REG_SC_BK1A_3A_H _PK_H_(0x1A, 0x3A) ++#define REG_SC_BK1A_3B_L _PK_L_(0x1A, 0x3B) ++#define REG_SC_BK1A_3B_H _PK_H_(0x1A, 0x3B) ++#define REG_SC_BK1A_3C_L _PK_L_(0x1A, 0x3C) ++#define REG_SC_BK1A_3C_H _PK_H_(0x1A, 0x3C) ++#define REG_SC_BK1A_3D_L _PK_L_(0x1A, 0x3D) ++#define REG_SC_BK1A_3D_H _PK_H_(0x1A, 0x3D) ++#define REG_SC_BK1A_3E_L _PK_L_(0x1A, 0x3E) ++#define REG_SC_BK1A_3E_H _PK_H_(0x1A, 0x3E) ++#define REG_SC_BK1A_3F_L _PK_L_(0x1A, 0x3F) ++#define REG_SC_BK1A_3F_H _PK_H_(0x1A, 0x3F) ++#define REG_SC_BK1A_40_L _PK_L_(0x1A, 0x40) ++#define REG_SC_BK1A_40_H _PK_H_(0x1A, 0x40) ++#define REG_SC_BK1A_41_L _PK_L_(0x1A, 0x41) ++#define REG_SC_BK1A_41_H _PK_H_(0x1A, 0x41) ++#define REG_SC_BK1A_42_L _PK_L_(0x1A, 0x42) ++#define REG_SC_BK1A_42_H _PK_H_(0x1A, 0x42) ++#define REG_SC_BK1A_43_L _PK_L_(0x1A, 0x43) ++#define REG_SC_BK1A_43_H _PK_H_(0x1A, 0x43) ++#define REG_SC_BK1A_44_L _PK_L_(0x1A, 0x44) ++#define REG_SC_BK1A_44_H _PK_H_(0x1A, 0x44) ++#define REG_SC_BK1A_45_L _PK_L_(0x1A, 0x45) ++#define REG_SC_BK1A_45_H _PK_H_(0x1A, 0x45) ++#define REG_SC_BK1A_46_L _PK_L_(0x1A, 0x46) ++#define REG_SC_BK1A_46_H _PK_H_(0x1A, 0x46) ++#define REG_SC_BK1A_47_L _PK_L_(0x1A, 0x47) ++#define REG_SC_BK1A_47_H _PK_H_(0x1A, 0x47) ++#define REG_SC_BK1A_48_L _PK_L_(0x1A, 0x48) ++#define REG_SC_BK1A_48_H _PK_H_(0x1A, 0x48) ++#define REG_SC_BK1A_49_L _PK_L_(0x1A, 0x49) ++#define REG_SC_BK1A_49_H _PK_H_(0x1A, 0x49) ++#define REG_SC_BK1A_4A_L _PK_L_(0x1A, 0x4A) ++#define REG_SC_BK1A_4A_H _PK_H_(0x1A, 0x4A) ++#define REG_SC_BK1A_4B_L _PK_L_(0x1A, 0x4B) ++#define REG_SC_BK1A_4B_H _PK_H_(0x1A, 0x4B) ++#define REG_SC_BK1A_4C_L _PK_L_(0x1A, 0x4C) ++#define REG_SC_BK1A_4C_H _PK_H_(0x1A, 0x4C) ++#define REG_SC_BK1A_4D_L _PK_L_(0x1A, 0x4D) ++#define REG_SC_BK1A_4D_H _PK_H_(0x1A, 0x4D) ++#define REG_SC_BK1A_4E_L _PK_L_(0x1A, 0x4E) ++#define REG_SC_BK1A_4E_H _PK_H_(0x1A, 0x4E) ++#define REG_SC_BK1A_4F_L _PK_L_(0x1A, 0x4F) ++#define REG_SC_BK1A_4F_H _PK_H_(0x1A, 0x4F) ++#define REG_SC_BK1A_50_L _PK_L_(0x1A, 0x50) ++#define REG_SC_BK1A_50_H _PK_H_(0x1A, 0x50) ++#define REG_SC_BK1A_51_L _PK_L_(0x1A, 0x51) ++#define REG_SC_BK1A_51_H _PK_H_(0x1A, 0x51) ++#define REG_SC_BK1A_52_L _PK_L_(0x1A, 0x52) ++#define REG_SC_BK1A_52_H _PK_H_(0x1A, 0x52) ++#define REG_SC_BK1A_53_L _PK_L_(0x1A, 0x53) ++#define REG_SC_BK1A_53_H _PK_H_(0x1A, 0x53) ++#define REG_SC_BK1A_54_L _PK_L_(0x1A, 0x54) ++#define REG_SC_BK1A_54_H _PK_H_(0x1A, 0x54) ++#define REG_SC_BK1A_55_L _PK_L_(0x1A, 0x55) ++#define REG_SC_BK1A_55_H _PK_H_(0x1A, 0x55) ++#define REG_SC_BK1A_56_L _PK_L_(0x1A, 0x56) ++#define REG_SC_BK1A_56_H _PK_H_(0x1A, 0x56) ++#define REG_SC_BK1A_57_L _PK_L_(0x1A, 0x57) ++#define REG_SC_BK1A_57_H _PK_H_(0x1A, 0x57) ++#define REG_SC_BK1A_58_L _PK_L_(0x1A, 0x58) ++#define REG_SC_BK1A_58_H _PK_H_(0x1A, 0x58) ++#define REG_SC_BK1A_59_L _PK_L_(0x1A, 0x59) ++#define REG_SC_BK1A_59_H _PK_H_(0x1A, 0x59) ++#define REG_SC_BK1A_5A_L _PK_L_(0x1A, 0x5A) ++#define REG_SC_BK1A_5A_H _PK_H_(0x1A, 0x5A) ++#define REG_SC_BK1A_5B_L _PK_L_(0x1A, 0x5B) ++#define REG_SC_BK1A_5B_H _PK_H_(0x1A, 0x5B) ++#define REG_SC_BK1A_5C_L _PK_L_(0x1A, 0x5C) ++#define REG_SC_BK1A_5C_H _PK_H_(0x1A, 0x5C) ++#define REG_SC_BK1A_5D_L _PK_L_(0x1A, 0x5D) ++#define REG_SC_BK1A_5D_H _PK_H_(0x1A, 0x5D) ++#define REG_SC_BK1A_5E_L _PK_L_(0x1A, 0x5E) ++#define REG_SC_BK1A_5E_H _PK_H_(0x1A, 0x5E) ++#define REG_SC_BK1A_5F_L _PK_L_(0x1A, 0x5F) ++#define REG_SC_BK1A_5F_H _PK_H_(0x1A, 0x5F) ++#define REG_SC_BK1A_60_L _PK_L_(0x1A, 0x60) ++#define REG_SC_BK1A_60_H _PK_H_(0x1A, 0x60) ++#define REG_SC_BK1A_61_L _PK_L_(0x1A, 0x61) ++#define REG_SC_BK1A_61_H _PK_H_(0x1A, 0x61) ++#define REG_SC_BK1A_62_L _PK_L_(0x1A, 0x62) ++#define REG_SC_BK1A_62_H _PK_H_(0x1A, 0x62) ++#define REG_SC_BK1A_63_L _PK_L_(0x1A, 0x63) ++#define REG_SC_BK1A_63_H _PK_H_(0x1A, 0x63) ++#define REG_SC_BK1A_64_L _PK_L_(0x1A, 0x64) ++#define REG_SC_BK1A_64_H _PK_H_(0x1A, 0x64) ++#define REG_SC_BK1A_65_L _PK_L_(0x1A, 0x65) ++#define REG_SC_BK1A_65_H _PK_H_(0x1A, 0x65) ++#define REG_SC_BK1A_66_L _PK_L_(0x1A, 0x66) ++#define REG_SC_BK1A_66_H _PK_H_(0x1A, 0x66) ++#define REG_SC_BK1A_67_L _PK_L_(0x1A, 0x67) ++#define REG_SC_BK1A_67_H _PK_H_(0x1A, 0x67) ++#define REG_SC_BK1A_68_L _PK_L_(0x1A, 0x68) ++#define REG_SC_BK1A_68_H _PK_H_(0x1A, 0x68) ++#define REG_SC_BK1A_69_L _PK_L_(0x1A, 0x69) ++#define REG_SC_BK1A_69_H _PK_H_(0x1A, 0x69) ++#define REG_SC_BK1A_6A_L _PK_L_(0x1A, 0x6A) ++#define REG_SC_BK1A_6A_H _PK_H_(0x1A, 0x6A) ++#define REG_SC_BK1A_6B_L _PK_L_(0x1A, 0x6B) ++#define REG_SC_BK1A_6B_H _PK_H_(0x1A, 0x6B) ++#define REG_SC_BK1A_6C_L _PK_L_(0x1A, 0x6C) ++#define REG_SC_BK1A_6C_H _PK_H_(0x1A, 0x6C) ++#define REG_SC_BK1A_6D_L _PK_L_(0x1A, 0x6D) ++#define REG_SC_BK1A_6D_H _PK_H_(0x1A, 0x6D) ++#define REG_SC_BK1A_6E_L _PK_L_(0x1A, 0x6E) ++#define REG_SC_BK1A_6E_H _PK_H_(0x1A, 0x6E) ++#define REG_SC_BK1A_6F_L _PK_L_(0x1A, 0x6F) ++#define REG_SC_BK1A_6F_H _PK_H_(0x1A, 0x6F) ++#define REG_SC_BK1A_70_L _PK_L_(0x1A, 0x70) ++#define REG_SC_BK1A_70_H _PK_H_(0x1A, 0x70) ++#define REG_SC_BK1A_71_L _PK_L_(0x1A, 0x71) ++#define REG_SC_BK1A_71_H _PK_H_(0x1A, 0x71) ++#define REG_SC_BK1A_72_L _PK_L_(0x1A, 0x72) ++#define REG_SC_BK1A_72_H _PK_H_(0x1A, 0x72) ++#define REG_SC_BK1A_73_L _PK_L_(0x1A, 0x73) ++#define REG_SC_BK1A_73_H _PK_H_(0x1A, 0x73) ++#define REG_SC_BK1A_74_L _PK_L_(0x1A, 0x74) ++#define REG_SC_BK1A_74_H _PK_H_(0x1A, 0x74) ++#define REG_SC_BK1A_75_L _PK_L_(0x1A, 0x75) ++#define REG_SC_BK1A_75_H _PK_H_(0x1A, 0x75) ++#define REG_SC_BK1A_76_L _PK_L_(0x1A, 0x76) ++#define REG_SC_BK1A_76_H _PK_H_(0x1A, 0x76) ++#define REG_SC_BK1A_77_L _PK_L_(0x1A, 0x77) ++#define REG_SC_BK1A_77_H _PK_H_(0x1A, 0x77) ++#define REG_SC_BK1A_78_L _PK_L_(0x1A, 0x78) ++#define REG_SC_BK1A_78_H _PK_H_(0x1A, 0x78) ++#define REG_SC_BK1A_79_L _PK_L_(0x1A, 0x79) ++#define REG_SC_BK1A_79_H _PK_H_(0x1A, 0x79) ++#define REG_SC_BK1A_7A_L _PK_L_(0x1A, 0x7A) ++#define REG_SC_BK1A_7A_H _PK_H_(0x1A, 0x7A) ++#define REG_SC_BK1A_7B_L _PK_L_(0x1A, 0x7B) ++#define REG_SC_BK1A_7B_H _PK_H_(0x1A, 0x7B) ++#define REG_SC_BK1A_7C_L _PK_L_(0x1A, 0x7C) ++#define REG_SC_BK1A_7C_H _PK_H_(0x1A, 0x7C) ++#define REG_SC_BK1A_7D_L _PK_L_(0x1A, 0x7D) ++#define REG_SC_BK1A_7D_H _PK_H_(0x1A, 0x7D) ++#define REG_SC_BK1A_7E_L _PK_L_(0x1A, 0x7E) ++#define REG_SC_BK1A_7E_H _PK_H_(0x1A, 0x7E) ++#define REG_SC_BK1A_7F_L _PK_L_(0x1A, 0x7F) ++#define REG_SC_BK1A_7F_H _PK_H_(0x1A, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1B_00_L _PK_L_(0x1B, 0x00) ++#define REG_SC_BK1B_00_H _PK_H_(0x1B, 0x00) ++#define REG_SC_BK1B_01_L _PK_L_(0x1B, 0x01) ++#define REG_SC_BK1B_01_H _PK_H_(0x1B, 0x01) ++#define REG_SC_BK1B_02_L _PK_L_(0x1B, 0x02) ++#define REG_SC_BK1B_02_H _PK_H_(0x1B, 0x02) ++#define REG_SC_BK1B_03_L _PK_L_(0x1B, 0x03) ++#define REG_SC_BK1B_03_H _PK_H_(0x1B, 0x03) ++#define REG_SC_BK1B_04_L _PK_L_(0x1B, 0x04) ++#define REG_SC_BK1B_04_H _PK_H_(0x1B, 0x04) ++#define REG_SC_BK1B_05_L _PK_L_(0x1B, 0x05) ++#define REG_SC_BK1B_05_H _PK_H_(0x1B, 0x05) ++#define REG_SC_BK1B_06_L _PK_L_(0x1B, 0x06) ++#define REG_SC_BK1B_06_H _PK_H_(0x1B, 0x06) ++#define REG_SC_BK1B_07_L _PK_L_(0x1B, 0x07) ++#define REG_SC_BK1B_07_H _PK_H_(0x1B, 0x07) ++#define REG_SC_BK1B_08_L _PK_L_(0x1B, 0x08) ++#define REG_SC_BK1B_08_H _PK_H_(0x1B, 0x08) ++#define REG_SC_BK1B_09_L _PK_L_(0x1B, 0x09) ++#define REG_SC_BK1B_09_H _PK_H_(0x1B, 0x09) ++#define REG_SC_BK1B_0A_L _PK_L_(0x1B, 0x0A) ++#define REG_SC_BK1B_0A_H _PK_H_(0x1B, 0x0A) ++#define REG_SC_BK1B_0B_L _PK_L_(0x1B, 0x0B) ++#define REG_SC_BK1B_0B_H _PK_H_(0x1B, 0x0B) ++#define REG_SC_BK1B_0C_L _PK_L_(0x1B, 0x0C) ++#define REG_SC_BK1B_0C_H _PK_H_(0x1B, 0x0C) ++#define REG_SC_BK1B_0D_L _PK_L_(0x1B, 0x0D) ++#define REG_SC_BK1B_0D_H _PK_H_(0x1B, 0x0D) ++#define REG_SC_BK1B_0E_L _PK_L_(0x1B, 0x0E) ++#define REG_SC_BK1B_0E_H _PK_H_(0x1B, 0x0E) ++#define REG_SC_BK1B_0F_L _PK_L_(0x1B, 0x0F) ++#define REG_SC_BK1B_0F_H _PK_H_(0x1B, 0x0F) ++#define REG_SC_BK1B_10_L _PK_L_(0x1B, 0x10) ++#define REG_SC_BK1B_10_H _PK_H_(0x1B, 0x10) ++#define REG_SC_BK1B_11_L _PK_L_(0x1B, 0x11) ++#define REG_SC_BK1B_11_H _PK_H_(0x1B, 0x11) ++#define REG_SC_BK1B_12_L _PK_L_(0x1B, 0x12) ++#define REG_SC_BK1B_12_H _PK_H_(0x1B, 0x12) ++#define REG_SC_BK1B_13_L _PK_L_(0x1B, 0x13) ++#define REG_SC_BK1B_13_H _PK_H_(0x1B, 0x13) ++#define REG_SC_BK1B_14_L _PK_L_(0x1B, 0x14) ++#define REG_SC_BK1B_14_H _PK_H_(0x1B, 0x14) ++#define REG_SC_BK1B_15_L _PK_L_(0x1B, 0x15) ++#define REG_SC_BK1B_15_H _PK_H_(0x1B, 0x15) ++#define REG_SC_BK1B_16_L _PK_L_(0x1B, 0x16) ++#define REG_SC_BK1B_16_H _PK_H_(0x1B, 0x16) ++#define REG_SC_BK1B_17_L _PK_L_(0x1B, 0x17) ++#define REG_SC_BK1B_17_H _PK_H_(0x1B, 0x17) ++#define REG_SC_BK1B_18_L _PK_L_(0x1B, 0x18) ++#define REG_SC_BK1B_18_H _PK_H_(0x1B, 0x18) ++#define REG_SC_BK1B_19_L _PK_L_(0x1B, 0x19) ++#define REG_SC_BK1B_19_H _PK_H_(0x1B, 0x19) ++#define REG_SC_BK1B_1A_L _PK_L_(0x1B, 0x1A) ++#define REG_SC_BK1B_1A_H _PK_H_(0x1B, 0x1A) ++#define REG_SC_BK1B_1B_L _PK_L_(0x1B, 0x1B) ++#define REG_SC_BK1B_1B_H _PK_H_(0x1B, 0x1B) ++#define REG_SC_BK1B_1C_L _PK_L_(0x1B, 0x1C) ++#define REG_SC_BK1B_1C_H _PK_H_(0x1B, 0x1C) ++#define REG_SC_BK1B_1D_L _PK_L_(0x1B, 0x1D) ++#define REG_SC_BK1B_1D_H _PK_H_(0x1B, 0x1D) ++#define REG_SC_BK1B_1E_L _PK_L_(0x1B, 0x1E) ++#define REG_SC_BK1B_1E_H _PK_H_(0x1B, 0x1E) ++#define REG_SC_BK1B_1F_L _PK_L_(0x1B, 0x1F) ++#define REG_SC_BK1B_1F_H _PK_H_(0x1B, 0x1F) ++#define REG_SC_BK1B_20_L _PK_L_(0x1B, 0x20) ++#define REG_SC_BK1B_20_H _PK_H_(0x1B, 0x20) ++#define REG_SC_BK1B_21_L _PK_L_(0x1B, 0x21) ++#define REG_SC_BK1B_21_H _PK_H_(0x1B, 0x21) ++#define REG_SC_BK1B_22_L _PK_L_(0x1B, 0x22) ++#define REG_SC_BK1B_22_H _PK_H_(0x1B, 0x22) ++#define REG_SC_BK1B_23_L _PK_L_(0x1B, 0x23) ++#define REG_SC_BK1B_23_H _PK_H_(0x1B, 0x23) ++#define REG_SC_BK1B_24_L _PK_L_(0x1B, 0x24) ++#define REG_SC_BK1B_24_H _PK_H_(0x1B, 0x24) ++#define REG_SC_BK1B_25_L _PK_L_(0x1B, 0x25) ++#define REG_SC_BK1B_25_H _PK_H_(0x1B, 0x25) ++#define REG_SC_BK1B_26_L _PK_L_(0x1B, 0x26) ++#define REG_SC_BK1B_26_H _PK_H_(0x1B, 0x26) ++#define REG_SC_BK1B_27_L _PK_L_(0x1B, 0x27) ++#define REG_SC_BK1B_27_H _PK_H_(0x1B, 0x27) ++#define REG_SC_BK1B_28_L _PK_L_(0x1B, 0x28) ++#define REG_SC_BK1B_28_H _PK_H_(0x1B, 0x28) ++#define REG_SC_BK1B_29_L _PK_L_(0x1B, 0x29) ++#define REG_SC_BK1B_29_H _PK_H_(0x1B, 0x29) ++#define REG_SC_BK1B_2A_L _PK_L_(0x1B, 0x2A) ++#define REG_SC_BK1B_2A_H _PK_H_(0x1B, 0x2A) ++#define REG_SC_BK1B_2B_L _PK_L_(0x1B, 0x2B) ++#define REG_SC_BK1B_2B_H _PK_H_(0x1B, 0x2B) ++#define REG_SC_BK1B_2C_L _PK_L_(0x1B, 0x2C) ++#define REG_SC_BK1B_2C_H _PK_H_(0x1B, 0x2C) ++#define REG_SC_BK1B_2D_L _PK_L_(0x1B, 0x2D) ++#define REG_SC_BK1B_2D_H _PK_H_(0x1B, 0x2D) ++#define REG_SC_BK1B_2E_L _PK_L_(0x1B, 0x2E) ++#define REG_SC_BK1B_2E_H _PK_H_(0x1B, 0x2E) ++#define REG_SC_BK1B_2F_L _PK_L_(0x1B, 0x2F) ++#define REG_SC_BK1B_2F_H _PK_H_(0x1B, 0x2F) ++#define REG_SC_BK1B_30_L _PK_L_(0x1B, 0x30) ++#define REG_SC_BK1B_30_H _PK_H_(0x1B, 0x30) ++#define REG_SC_BK1B_31_L _PK_L_(0x1B, 0x31) ++#define REG_SC_BK1B_31_H _PK_H_(0x1B, 0x31) ++#define REG_SC_BK1B_32_L _PK_L_(0x1B, 0x32) ++#define REG_SC_BK1B_32_H _PK_H_(0x1B, 0x32) ++#define REG_SC_BK1B_33_L _PK_L_(0x1B, 0x33) ++#define REG_SC_BK1B_33_H _PK_H_(0x1B, 0x33) ++#define REG_SC_BK1B_34_L _PK_L_(0x1B, 0x34) ++#define REG_SC_BK1B_34_H _PK_H_(0x1B, 0x34) ++#define REG_SC_BK1B_35_L _PK_L_(0x1B, 0x35) ++#define REG_SC_BK1B_35_H _PK_H_(0x1B, 0x35) ++#define REG_SC_BK1B_36_L _PK_L_(0x1B, 0x36) ++#define REG_SC_BK1B_36_H _PK_H_(0x1B, 0x36) ++#define REG_SC_BK1B_37_L _PK_L_(0x1B, 0x37) ++#define REG_SC_BK1B_37_H _PK_H_(0x1B, 0x37) ++#define REG_SC_BK1B_38_L _PK_L_(0x1B, 0x38) ++#define REG_SC_BK1B_38_H _PK_H_(0x1B, 0x38) ++#define REG_SC_BK1B_39_L _PK_L_(0x1B, 0x39) ++#define REG_SC_BK1B_39_H _PK_H_(0x1B, 0x39) ++#define REG_SC_BK1B_3A_L _PK_L_(0x1B, 0x3A) ++#define REG_SC_BK1B_3A_H _PK_H_(0x1B, 0x3A) ++#define REG_SC_BK1B_3B_L _PK_L_(0x1B, 0x3B) ++#define REG_SC_BK1B_3B_H _PK_H_(0x1B, 0x3B) ++#define REG_SC_BK1B_3C_L _PK_L_(0x1B, 0x3C) ++#define REG_SC_BK1B_3C_H _PK_H_(0x1B, 0x3C) ++#define REG_SC_BK1B_3D_L _PK_L_(0x1B, 0x3D) ++#define REG_SC_BK1B_3D_H _PK_H_(0x1B, 0x3D) ++#define REG_SC_BK1B_3E_L _PK_L_(0x1B, 0x3E) ++#define REG_SC_BK1B_3E_H _PK_H_(0x1B, 0x3E) ++#define REG_SC_BK1B_3F_L _PK_L_(0x1B, 0x3F) ++#define REG_SC_BK1B_3F_H _PK_H_(0x1B, 0x3F) ++#define REG_SC_BK1B_40_L _PK_L_(0x1B, 0x40) ++#define REG_SC_BK1B_40_H _PK_H_(0x1B, 0x40) ++#define REG_SC_BK1B_41_L _PK_L_(0x1B, 0x41) ++#define REG_SC_BK1B_41_H _PK_H_(0x1B, 0x41) ++#define REG_SC_BK1B_42_L _PK_L_(0x1B, 0x42) ++#define REG_SC_BK1B_42_H _PK_H_(0x1B, 0x42) ++#define REG_SC_BK1B_43_L _PK_L_(0x1B, 0x43) ++#define REG_SC_BK1B_43_H _PK_H_(0x1B, 0x43) ++#define REG_SC_BK1B_44_L _PK_L_(0x1B, 0x44) ++#define REG_SC_BK1B_44_H _PK_H_(0x1B, 0x44) ++#define REG_SC_BK1B_45_L _PK_L_(0x1B, 0x45) ++#define REG_SC_BK1B_45_H _PK_H_(0x1B, 0x45) ++#define REG_SC_BK1B_46_L _PK_L_(0x1B, 0x46) ++#define REG_SC_BK1B_46_H _PK_H_(0x1B, 0x46) ++#define REG_SC_BK1B_47_L _PK_L_(0x1B, 0x47) ++#define REG_SC_BK1B_47_H _PK_H_(0x1B, 0x47) ++#define REG_SC_BK1B_48_L _PK_L_(0x1B, 0x48) ++#define REG_SC_BK1B_48_H _PK_H_(0x1B, 0x48) ++#define REG_SC_BK1B_49_L _PK_L_(0x1B, 0x49) ++#define REG_SC_BK1B_49_H _PK_H_(0x1B, 0x49) ++#define REG_SC_BK1B_4A_L _PK_L_(0x1B, 0x4A) ++#define REG_SC_BK1B_4A_H _PK_H_(0x1B, 0x4A) ++#define REG_SC_BK1B_4B_L _PK_L_(0x1B, 0x4B) ++#define REG_SC_BK1B_4B_H _PK_H_(0x1B, 0x4B) ++#define REG_SC_BK1B_4C_L _PK_L_(0x1B, 0x4C) ++#define REG_SC_BK1B_4C_H _PK_H_(0x1B, 0x4C) ++#define REG_SC_BK1B_4D_L _PK_L_(0x1B, 0x4D) ++#define REG_SC_BK1B_4D_H _PK_H_(0x1B, 0x4D) ++#define REG_SC_BK1B_4E_L _PK_L_(0x1B, 0x4E) ++#define REG_SC_BK1B_4E_H _PK_H_(0x1B, 0x4E) ++#define REG_SC_BK1B_4F_L _PK_L_(0x1B, 0x4F) ++#define REG_SC_BK1B_4F_H _PK_H_(0x1B, 0x4F) ++#define REG_SC_BK1B_50_L _PK_L_(0x1B, 0x50) ++#define REG_SC_BK1B_50_H _PK_H_(0x1B, 0x50) ++#define REG_SC_BK1B_51_L _PK_L_(0x1B, 0x51) ++#define REG_SC_BK1B_51_H _PK_H_(0x1B, 0x51) ++#define REG_SC_BK1B_52_L _PK_L_(0x1B, 0x52) ++#define REG_SC_BK1B_52_H _PK_H_(0x1B, 0x52) ++#define REG_SC_BK1B_53_L _PK_L_(0x1B, 0x53) ++#define REG_SC_BK1B_53_H _PK_H_(0x1B, 0x53) ++#define REG_SC_BK1B_54_L _PK_L_(0x1B, 0x54) ++#define REG_SC_BK1B_54_H _PK_H_(0x1B, 0x54) ++#define REG_SC_BK1B_55_L _PK_L_(0x1B, 0x55) ++#define REG_SC_BK1B_55_H _PK_H_(0x1B, 0x55) ++#define REG_SC_BK1B_56_L _PK_L_(0x1B, 0x56) ++#define REG_SC_BK1B_56_H _PK_H_(0x1B, 0x56) ++#define REG_SC_BK1B_57_L _PK_L_(0x1B, 0x57) ++#define REG_SC_BK1B_57_H _PK_H_(0x1B, 0x57) ++#define REG_SC_BK1B_58_L _PK_L_(0x1B, 0x58) ++#define REG_SC_BK1B_58_H _PK_H_(0x1B, 0x58) ++#define REG_SC_BK1B_59_L _PK_L_(0x1B, 0x59) ++#define REG_SC_BK1B_59_H _PK_H_(0x1B, 0x59) ++#define REG_SC_BK1B_5A_L _PK_L_(0x1B, 0x5A) ++#define REG_SC_BK1B_5A_H _PK_H_(0x1B, 0x5A) ++#define REG_SC_BK1B_5B_L _PK_L_(0x1B, 0x5B) ++#define REG_SC_BK1B_5B_H _PK_H_(0x1B, 0x5B) ++#define REG_SC_BK1B_5C_L _PK_L_(0x1B, 0x5C) ++#define REG_SC_BK1B_5C_H _PK_H_(0x1B, 0x5C) ++#define REG_SC_BK1B_5D_L _PK_L_(0x1B, 0x5D) ++#define REG_SC_BK1B_5D_H _PK_H_(0x1B, 0x5D) ++#define REG_SC_BK1B_5E_L _PK_L_(0x1B, 0x5E) ++#define REG_SC_BK1B_5E_H _PK_H_(0x1B, 0x5E) ++#define REG_SC_BK1B_5F_L _PK_L_(0x1B, 0x5F) ++#define REG_SC_BK1B_5F_H _PK_H_(0x1B, 0x5F) ++#define REG_SC_BK1B_60_L _PK_L_(0x1B, 0x60) ++#define REG_SC_BK1B_60_H _PK_H_(0x1B, 0x60) ++#define REG_SC_BK1B_61_L _PK_L_(0x1B, 0x61) ++#define REG_SC_BK1B_61_H _PK_H_(0x1B, 0x61) ++#define REG_SC_BK1B_62_L _PK_L_(0x1B, 0x62) ++#define REG_SC_BK1B_62_H _PK_H_(0x1B, 0x62) ++#define REG_SC_BK1B_63_L _PK_L_(0x1B, 0x63) ++#define REG_SC_BK1B_63_H _PK_H_(0x1B, 0x63) ++#define REG_SC_BK1B_64_L _PK_L_(0x1B, 0x64) ++#define REG_SC_BK1B_64_H _PK_H_(0x1B, 0x64) ++#define REG_SC_BK1B_65_L _PK_L_(0x1B, 0x65) ++#define REG_SC_BK1B_65_H _PK_H_(0x1B, 0x65) ++#define REG_SC_BK1B_66_L _PK_L_(0x1B, 0x66) ++#define REG_SC_BK1B_66_H _PK_H_(0x1B, 0x66) ++#define REG_SC_BK1B_67_L _PK_L_(0x1B, 0x67) ++#define REG_SC_BK1B_67_H _PK_H_(0x1B, 0x67) ++#define REG_SC_BK1B_68_L _PK_L_(0x1B, 0x68) ++#define REG_SC_BK1B_68_H _PK_H_(0x1B, 0x68) ++#define REG_SC_BK1B_69_L _PK_L_(0x1B, 0x69) ++#define REG_SC_BK1B_69_H _PK_H_(0x1B, 0x69) ++#define REG_SC_BK1B_6A_L _PK_L_(0x1B, 0x6A) ++#define REG_SC_BK1B_6A_H _PK_H_(0x1B, 0x6A) ++#define REG_SC_BK1B_6B_L _PK_L_(0x1B, 0x6B) ++#define REG_SC_BK1B_6B_H _PK_H_(0x1B, 0x6B) ++#define REG_SC_BK1B_6C_L _PK_L_(0x1B, 0x6C) ++#define REG_SC_BK1B_6C_H _PK_H_(0x1B, 0x6C) ++#define REG_SC_BK1B_6D_L _PK_L_(0x1B, 0x6D) ++#define REG_SC_BK1B_6D_H _PK_H_(0x1B, 0x6D) ++#define REG_SC_BK1B_6E_L _PK_L_(0x1B, 0x6E) ++#define REG_SC_BK1B_6E_H _PK_H_(0x1B, 0x6E) ++#define REG_SC_BK1B_6F_L _PK_L_(0x1B, 0x6F) ++#define REG_SC_BK1B_6F_H _PK_H_(0x1B, 0x6F) ++#define REG_SC_BK1B_70_L _PK_L_(0x1B, 0x70) ++#define REG_SC_BK1B_70_H _PK_H_(0x1B, 0x70) ++#define REG_SC_BK1B_71_L _PK_L_(0x1B, 0x71) ++#define REG_SC_BK1B_71_H _PK_H_(0x1B, 0x71) ++#define REG_SC_BK1B_72_L _PK_L_(0x1B, 0x72) ++#define REG_SC_BK1B_72_H _PK_H_(0x1B, 0x72) ++#define REG_SC_BK1B_73_L _PK_L_(0x1B, 0x73) ++#define REG_SC_BK1B_73_H _PK_H_(0x1B, 0x73) ++#define REG_SC_BK1B_74_L _PK_L_(0x1B, 0x74) ++#define REG_SC_BK1B_74_H _PK_H_(0x1B, 0x74) ++#define REG_SC_BK1B_75_L _PK_L_(0x1B, 0x75) ++#define REG_SC_BK1B_75_H _PK_H_(0x1B, 0x75) ++#define REG_SC_BK1B_76_L _PK_L_(0x1B, 0x76) ++#define REG_SC_BK1B_76_H _PK_H_(0x1B, 0x76) ++#define REG_SC_BK1B_77_L _PK_L_(0x1B, 0x77) ++#define REG_SC_BK1B_77_H _PK_H_(0x1B, 0x77) ++#define REG_SC_BK1B_78_L _PK_L_(0x1B, 0x78) ++#define REG_SC_BK1B_78_H _PK_H_(0x1B, 0x78) ++#define REG_SC_BK1B_79_L _PK_L_(0x1B, 0x79) ++#define REG_SC_BK1B_79_H _PK_H_(0x1B, 0x79) ++#define REG_SC_BK1B_7A_L _PK_L_(0x1B, 0x7A) ++#define REG_SC_BK1B_7A_H _PK_H_(0x1B, 0x7A) ++#define REG_SC_BK1B_7B_L _PK_L_(0x1B, 0x7B) ++#define REG_SC_BK1B_7B_H _PK_H_(0x1B, 0x7B) ++#define REG_SC_BK1B_7C_L _PK_L_(0x1B, 0x7C) ++#define REG_SC_BK1B_7C_H _PK_H_(0x1B, 0x7C) ++#define REG_SC_BK1B_7D_L _PK_L_(0x1B, 0x7D) ++#define REG_SC_BK1B_7D_H _PK_H_(0x1B, 0x7D) ++#define REG_SC_BK1B_7E_L _PK_L_(0x1B, 0x7E) ++#define REG_SC_BK1B_7E_H _PK_H_(0x1B, 0x7E) ++#define REG_SC_BK1B_7F_L _PK_L_(0x1B, 0x7F) ++#define REG_SC_BK1B_7F_H _PK_H_(0x1B, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1C_00_L _PK_L_(0x1C, 0x00) ++#define REG_SC_BK1C_00_H _PK_H_(0x1C, 0x00) ++#define REG_SC_BK1C_01_L _PK_L_(0x1C, 0x01) ++#define REG_SC_BK1C_01_H _PK_H_(0x1C, 0x01) ++#define REG_SC_BK1C_02_L _PK_L_(0x1C, 0x02) ++#define REG_SC_BK1C_02_H _PK_H_(0x1C, 0x02) ++#define REG_SC_BK1C_03_L _PK_L_(0x1C, 0x03) ++#define REG_SC_BK1C_03_H _PK_H_(0x1C, 0x03) ++#define REG_SC_BK1C_04_L _PK_L_(0x1C, 0x04) ++#define REG_SC_BK1C_04_H _PK_H_(0x1C, 0x04) ++#define REG_SC_BK1C_05_L _PK_L_(0x1C, 0x05) ++#define REG_SC_BK1C_05_H _PK_H_(0x1C, 0x05) ++#define REG_SC_BK1C_06_L _PK_L_(0x1C, 0x06) ++#define REG_SC_BK1C_06_H _PK_H_(0x1C, 0x06) ++#define REG_SC_BK1C_07_L _PK_L_(0x1C, 0x07) ++#define REG_SC_BK1C_07_H _PK_H_(0x1C, 0x07) ++#define REG_SC_BK1C_08_L _PK_L_(0x1C, 0x08) ++#define REG_SC_BK1C_08_H _PK_H_(0x1C, 0x08) ++#define REG_SC_BK1C_09_L _PK_L_(0x1C, 0x09) ++#define REG_SC_BK1C_09_H _PK_H_(0x1C, 0x09) ++#define REG_SC_BK1C_0A_L _PK_L_(0x1C, 0x0A) ++#define REG_SC_BK1C_0A_H _PK_H_(0x1C, 0x0A) ++#define REG_SC_BK1C_0B_L _PK_L_(0x1C, 0x0B) ++#define REG_SC_BK1C_0B_H _PK_H_(0x1C, 0x0B) ++#define REG_SC_BK1C_0C_L _PK_L_(0x1C, 0x0C) ++#define REG_SC_BK1C_0C_H _PK_H_(0x1C, 0x0C) ++#define REG_SC_BK1C_0D_L _PK_L_(0x1C, 0x0D) ++#define REG_SC_BK1C_0D_H _PK_H_(0x1C, 0x0D) ++#define REG_SC_BK1C_0E_L _PK_L_(0x1C, 0x0E) ++#define REG_SC_BK1C_0E_H _PK_H_(0x1C, 0x0E) ++#define REG_SC_BK1C_0F_L _PK_L_(0x1C, 0x0F) ++#define REG_SC_BK1C_0F_H _PK_H_(0x1C, 0x0F) ++#define REG_SC_BK1C_10_L _PK_L_(0x1C, 0x10) ++#define REG_SC_BK1C_10_H _PK_H_(0x1C, 0x10) ++#define REG_SC_BK1C_11_L _PK_L_(0x1C, 0x11) ++#define REG_SC_BK1C_11_H _PK_H_(0x1C, 0x11) ++#define REG_SC_BK1C_12_L _PK_L_(0x1C, 0x12) ++#define REG_SC_BK1C_12_H _PK_H_(0x1C, 0x12) ++#define REG_SC_BK1C_13_L _PK_L_(0x1C, 0x13) ++#define REG_SC_BK1C_13_H _PK_H_(0x1C, 0x13) ++#define REG_SC_BK1C_14_L _PK_L_(0x1C, 0x14) ++#define REG_SC_BK1C_14_H _PK_H_(0x1C, 0x14) ++#define REG_SC_BK1C_15_L _PK_L_(0x1C, 0x15) ++#define REG_SC_BK1C_15_H _PK_H_(0x1C, 0x15) ++#define REG_SC_BK1C_16_L _PK_L_(0x1C, 0x16) ++#define REG_SC_BK1C_16_H _PK_H_(0x1C, 0x16) ++#define REG_SC_BK1C_17_L _PK_L_(0x1C, 0x17) ++#define REG_SC_BK1C_17_H _PK_H_(0x1C, 0x17) ++#define REG_SC_BK1C_18_L _PK_L_(0x1C, 0x18) ++#define REG_SC_BK1C_18_H _PK_H_(0x1C, 0x18) ++#define REG_SC_BK1C_19_L _PK_L_(0x1C, 0x19) ++#define REG_SC_BK1C_19_H _PK_H_(0x1C, 0x19) ++#define REG_SC_BK1C_1A_L _PK_L_(0x1C, 0x1A) ++#define REG_SC_BK1C_1A_H _PK_H_(0x1C, 0x1A) ++#define REG_SC_BK1C_1B_L _PK_L_(0x1C, 0x1B) ++#define REG_SC_BK1C_1B_H _PK_H_(0x1C, 0x1B) ++#define REG_SC_BK1C_1C_L _PK_L_(0x1C, 0x1C) ++#define REG_SC_BK1C_1C_H _PK_H_(0x1C, 0x1C) ++#define REG_SC_BK1C_1D_L _PK_L_(0x1C, 0x1D) ++#define REG_SC_BK1C_1D_H _PK_H_(0x1C, 0x1D) ++#define REG_SC_BK1C_1E_L _PK_L_(0x1C, 0x1E) ++#define REG_SC_BK1C_1E_H _PK_H_(0x1C, 0x1E) ++#define REG_SC_BK1C_1F_L _PK_L_(0x1C, 0x1F) ++#define REG_SC_BK1C_1F_H _PK_H_(0x1C, 0x1F) ++#define REG_SC_BK1C_20_L _PK_L_(0x1C, 0x20) ++#define REG_SC_BK1C_20_H _PK_H_(0x1C, 0x20) ++#define REG_SC_BK1C_21_L _PK_L_(0x1C, 0x21) ++#define REG_SC_BK1C_21_H _PK_H_(0x1C, 0x21) ++#define REG_SC_BK1C_22_L _PK_L_(0x1C, 0x22) ++#define REG_SC_BK1C_22_H _PK_H_(0x1C, 0x22) ++#define REG_SC_BK1C_23_L _PK_L_(0x1C, 0x23) ++#define REG_SC_BK1C_23_H _PK_H_(0x1C, 0x23) ++#define REG_SC_BK1C_24_L _PK_L_(0x1C, 0x24) ++#define REG_SC_BK1C_24_H _PK_H_(0x1C, 0x24) ++#define REG_SC_BK1C_25_L _PK_L_(0x1C, 0x25) ++#define REG_SC_BK1C_25_H _PK_H_(0x1C, 0x25) ++#define REG_SC_BK1C_26_L _PK_L_(0x1C, 0x26) ++#define REG_SC_BK1C_26_H _PK_H_(0x1C, 0x26) ++#define REG_SC_BK1C_27_L _PK_L_(0x1C, 0x27) ++#define REG_SC_BK1C_27_H _PK_H_(0x1C, 0x27) ++#define REG_SC_BK1C_28_L _PK_L_(0x1C, 0x28) ++#define REG_SC_BK1C_28_H _PK_H_(0x1C, 0x28) ++#define REG_SC_BK1C_29_L _PK_L_(0x1C, 0x29) ++#define REG_SC_BK1C_29_H _PK_H_(0x1C, 0x29) ++#define REG_SC_BK1C_2A_L _PK_L_(0x1C, 0x2A) ++#define REG_SC_BK1C_2A_H _PK_H_(0x1C, 0x2A) ++#define REG_SC_BK1C_2B_L _PK_L_(0x1C, 0x2B) ++#define REG_SC_BK1C_2B_H _PK_H_(0x1C, 0x2B) ++#define REG_SC_BK1C_2C_L _PK_L_(0x1C, 0x2C) ++#define REG_SC_BK1C_2C_H _PK_H_(0x1C, 0x2C) ++#define REG_SC_BK1C_2D_L _PK_L_(0x1C, 0x2D) ++#define REG_SC_BK1C_2D_H _PK_H_(0x1C, 0x2D) ++#define REG_SC_BK1C_2E_L _PK_L_(0x1C, 0x2E) ++#define REG_SC_BK1C_2E_H _PK_H_(0x1C, 0x2E) ++#define REG_SC_BK1C_2F_L _PK_L_(0x1C, 0x2F) ++#define REG_SC_BK1C_2F_H _PK_H_(0x1C, 0x2F) ++#define REG_SC_BK1C_30_L _PK_L_(0x1C, 0x30) ++#define REG_SC_BK1C_30_H _PK_H_(0x1C, 0x30) ++#define REG_SC_BK1C_31_L _PK_L_(0x1C, 0x31) ++#define REG_SC_BK1C_31_H _PK_H_(0x1C, 0x31) ++#define REG_SC_BK1C_32_L _PK_L_(0x1C, 0x32) ++#define REG_SC_BK1C_32_H _PK_H_(0x1C, 0x32) ++#define REG_SC_BK1C_33_L _PK_L_(0x1C, 0x33) ++#define REG_SC_BK1C_33_H _PK_H_(0x1C, 0x33) ++#define REG_SC_BK1C_34_L _PK_L_(0x1C, 0x34) ++#define REG_SC_BK1C_34_H _PK_H_(0x1C, 0x34) ++#define REG_SC_BK1C_35_L _PK_L_(0x1C, 0x35) ++#define REG_SC_BK1C_35_H _PK_H_(0x1C, 0x35) ++#define REG_SC_BK1C_36_L _PK_L_(0x1C, 0x36) ++#define REG_SC_BK1C_36_H _PK_H_(0x1C, 0x36) ++#define REG_SC_BK1C_37_L _PK_L_(0x1C, 0x37) ++#define REG_SC_BK1C_37_H _PK_H_(0x1C, 0x37) ++#define REG_SC_BK1C_38_L _PK_L_(0x1C, 0x38) ++#define REG_SC_BK1C_38_H _PK_H_(0x1C, 0x38) ++#define REG_SC_BK1C_39_L _PK_L_(0x1C, 0x39) ++#define REG_SC_BK1C_39_H _PK_H_(0x1C, 0x39) ++#define REG_SC_BK1C_3A_L _PK_L_(0x1C, 0x3A) ++#define REG_SC_BK1C_3A_H _PK_H_(0x1C, 0x3A) ++#define REG_SC_BK1C_3B_L _PK_L_(0x1C, 0x3B) ++#define REG_SC_BK1C_3B_H _PK_H_(0x1C, 0x3B) ++#define REG_SC_BK1C_3C_L _PK_L_(0x1C, 0x3C) ++#define REG_SC_BK1C_3C_H _PK_H_(0x1C, 0x3C) ++#define REG_SC_BK1C_3D_L _PK_L_(0x1C, 0x3D) ++#define REG_SC_BK1C_3D_H _PK_H_(0x1C, 0x3D) ++#define REG_SC_BK1C_3E_L _PK_L_(0x1C, 0x3E) ++#define REG_SC_BK1C_3E_H _PK_H_(0x1C, 0x3E) ++#define REG_SC_BK1C_3F_L _PK_L_(0x1C, 0x3F) ++#define REG_SC_BK1C_3F_H _PK_H_(0x1C, 0x3F) ++#define REG_SC_BK1C_40_L _PK_L_(0x1C, 0x40) ++#define REG_SC_BK1C_40_H _PK_H_(0x1C, 0x40) ++#define REG_SC_BK1C_41_L _PK_L_(0x1C, 0x41) ++#define REG_SC_BK1C_41_H _PK_H_(0x1C, 0x41) ++#define REG_SC_BK1C_42_L _PK_L_(0x1C, 0x42) ++#define REG_SC_BK1C_42_H _PK_H_(0x1C, 0x42) ++#define REG_SC_BK1C_43_L _PK_L_(0x1C, 0x43) ++#define REG_SC_BK1C_43_H _PK_H_(0x1C, 0x43) ++#define REG_SC_BK1C_44_L _PK_L_(0x1C, 0x44) ++#define REG_SC_BK1C_44_H _PK_H_(0x1C, 0x44) ++#define REG_SC_BK1C_45_L _PK_L_(0x1C, 0x45) ++#define REG_SC_BK1C_45_H _PK_H_(0x1C, 0x45) ++#define REG_SC_BK1C_46_L _PK_L_(0x1C, 0x46) ++#define REG_SC_BK1C_46_H _PK_H_(0x1C, 0x46) ++#define REG_SC_BK1C_47_L _PK_L_(0x1C, 0x47) ++#define REG_SC_BK1C_47_H _PK_H_(0x1C, 0x47) ++#define REG_SC_BK1C_48_L _PK_L_(0x1C, 0x48) ++#define REG_SC_BK1C_48_H _PK_H_(0x1C, 0x48) ++#define REG_SC_BK1C_49_L _PK_L_(0x1C, 0x49) ++#define REG_SC_BK1C_49_H _PK_H_(0x1C, 0x49) ++#define REG_SC_BK1C_4A_L _PK_L_(0x1C, 0x4A) ++#define REG_SC_BK1C_4A_H _PK_H_(0x1C, 0x4A) ++#define REG_SC_BK1C_4B_L _PK_L_(0x1C, 0x4B) ++#define REG_SC_BK1C_4B_H _PK_H_(0x1C, 0x4B) ++#define REG_SC_BK1C_4C_L _PK_L_(0x1C, 0x4C) ++#define REG_SC_BK1C_4C_H _PK_H_(0x1C, 0x4C) ++#define REG_SC_BK1C_4D_L _PK_L_(0x1C, 0x4D) ++#define REG_SC_BK1C_4D_H _PK_H_(0x1C, 0x4D) ++#define REG_SC_BK1C_4E_L _PK_L_(0x1C, 0x4E) ++#define REG_SC_BK1C_4E_H _PK_H_(0x1C, 0x4E) ++#define REG_SC_BK1C_4F_L _PK_L_(0x1C, 0x4F) ++#define REG_SC_BK1C_4F_H _PK_H_(0x1C, 0x4F) ++#define REG_SC_BK1C_50_L _PK_L_(0x1C, 0x50) ++#define REG_SC_BK1C_50_H _PK_H_(0x1C, 0x50) ++#define REG_SC_BK1C_51_L _PK_L_(0x1C, 0x51) ++#define REG_SC_BK1C_51_H _PK_H_(0x1C, 0x51) ++#define REG_SC_BK1C_52_L _PK_L_(0x1C, 0x52) ++#define REG_SC_BK1C_52_H _PK_H_(0x1C, 0x52) ++#define REG_SC_BK1C_53_L _PK_L_(0x1C, 0x53) ++#define REG_SC_BK1C_53_H _PK_H_(0x1C, 0x53) ++#define REG_SC_BK1C_54_L _PK_L_(0x1C, 0x54) ++#define REG_SC_BK1C_54_H _PK_H_(0x1C, 0x54) ++#define REG_SC_BK1C_55_L _PK_L_(0x1C, 0x55) ++#define REG_SC_BK1C_55_H _PK_H_(0x1C, 0x55) ++#define REG_SC_BK1C_56_L _PK_L_(0x1C, 0x56) ++#define REG_SC_BK1C_56_H _PK_H_(0x1C, 0x56) ++#define REG_SC_BK1C_57_L _PK_L_(0x1C, 0x57) ++#define REG_SC_BK1C_57_H _PK_H_(0x1C, 0x57) ++#define REG_SC_BK1C_58_L _PK_L_(0x1C, 0x58) ++#define REG_SC_BK1C_58_H _PK_H_(0x1C, 0x58) ++#define REG_SC_BK1C_59_L _PK_L_(0x1C, 0x59) ++#define REG_SC_BK1C_59_H _PK_H_(0x1C, 0x59) ++#define REG_SC_BK1C_5A_L _PK_L_(0x1C, 0x5A) ++#define REG_SC_BK1C_5A_H _PK_H_(0x1C, 0x5A) ++#define REG_SC_BK1C_5B_L _PK_L_(0x1C, 0x5B) ++#define REG_SC_BK1C_5B_H _PK_H_(0x1C, 0x5B) ++#define REG_SC_BK1C_5C_L _PK_L_(0x1C, 0x5C) ++#define REG_SC_BK1C_5C_H _PK_H_(0x1C, 0x5C) ++#define REG_SC_BK1C_5D_L _PK_L_(0x1C, 0x5D) ++#define REG_SC_BK1C_5D_H _PK_H_(0x1C, 0x5D) ++#define REG_SC_BK1C_5E_L _PK_L_(0x1C, 0x5E) ++#define REG_SC_BK1C_5E_H _PK_H_(0x1C, 0x5E) ++#define REG_SC_BK1C_5F_L _PK_L_(0x1C, 0x5F) ++#define REG_SC_BK1C_5F_H _PK_H_(0x1C, 0x5F) ++#define REG_SC_BK1C_60_L _PK_L_(0x1C, 0x60) ++#define REG_SC_BK1C_60_H _PK_H_(0x1C, 0x60) ++#define REG_SC_BK1C_61_L _PK_L_(0x1C, 0x61) ++#define REG_SC_BK1C_61_H _PK_H_(0x1C, 0x61) ++#define REG_SC_BK1C_62_L _PK_L_(0x1C, 0x62) ++#define REG_SC_BK1C_62_H _PK_H_(0x1C, 0x62) ++#define REG_SC_BK1C_63_L _PK_L_(0x1C, 0x63) ++#define REG_SC_BK1C_63_H _PK_H_(0x1C, 0x63) ++#define REG_SC_BK1C_64_L _PK_L_(0x1C, 0x64) ++#define REG_SC_BK1C_64_H _PK_H_(0x1C, 0x64) ++#define REG_SC_BK1C_65_L _PK_L_(0x1C, 0x65) ++#define REG_SC_BK1C_65_H _PK_H_(0x1C, 0x65) ++#define REG_SC_BK1C_66_L _PK_L_(0x1C, 0x66) ++#define REG_SC_BK1C_66_H _PK_H_(0x1C, 0x66) ++#define REG_SC_BK1C_67_L _PK_L_(0x1C, 0x67) ++#define REG_SC_BK1C_67_H _PK_H_(0x1C, 0x67) ++#define REG_SC_BK1C_68_L _PK_L_(0x1C, 0x68) ++#define REG_SC_BK1C_68_H _PK_H_(0x1C, 0x68) ++#define REG_SC_BK1C_69_L _PK_L_(0x1C, 0x69) ++#define REG_SC_BK1C_69_H _PK_H_(0x1C, 0x69) ++#define REG_SC_BK1C_6A_L _PK_L_(0x1C, 0x6A) ++#define REG_SC_BK1C_6A_H _PK_H_(0x1C, 0x6A) ++#define REG_SC_BK1C_6B_L _PK_L_(0x1C, 0x6B) ++#define REG_SC_BK1C_6B_H _PK_H_(0x1C, 0x6B) ++#define REG_SC_BK1C_6C_L _PK_L_(0x1C, 0x6C) ++#define REG_SC_BK1C_6C_H _PK_H_(0x1C, 0x6C) ++#define REG_SC_BK1C_6D_L _PK_L_(0x1C, 0x6D) ++#define REG_SC_BK1C_6D_H _PK_H_(0x1C, 0x6D) ++#define REG_SC_BK1C_6E_L _PK_L_(0x1C, 0x6E) ++#define REG_SC_BK1C_6E_H _PK_H_(0x1C, 0x6E) ++#define REG_SC_BK1C_6F_L _PK_L_(0x1C, 0x6F) ++#define REG_SC_BK1C_6F_H _PK_H_(0x1C, 0x6F) ++#define REG_SC_BK1C_70_L _PK_L_(0x1C, 0x70) ++#define REG_SC_BK1C_70_H _PK_H_(0x1C, 0x70) ++#define REG_SC_BK1C_71_L _PK_L_(0x1C, 0x71) ++#define REG_SC_BK1C_71_H _PK_H_(0x1C, 0x71) ++#define REG_SC_BK1C_72_L _PK_L_(0x1C, 0x72) ++#define REG_SC_BK1C_72_H _PK_H_(0x1C, 0x72) ++#define REG_SC_BK1C_73_L _PK_L_(0x1C, 0x73) ++#define REG_SC_BK1C_73_H _PK_H_(0x1C, 0x73) ++#define REG_SC_BK1C_74_L _PK_L_(0x1C, 0x74) ++#define REG_SC_BK1C_74_H _PK_H_(0x1C, 0x74) ++#define REG_SC_BK1C_75_L _PK_L_(0x1C, 0x75) ++#define REG_SC_BK1C_75_H _PK_H_(0x1C, 0x75) ++#define REG_SC_BK1C_76_L _PK_L_(0x1C, 0x76) ++#define REG_SC_BK1C_76_H _PK_H_(0x1C, 0x76) ++#define REG_SC_BK1C_77_L _PK_L_(0x1C, 0x77) ++#define REG_SC_BK1C_77_H _PK_H_(0x1C, 0x77) ++#define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) ++#define REG_SC_BK1C_78_H _PK_H_(0x1C, 0x78) ++#define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) ++#define REG_SC_BK1C_79_H _PK_H_(0x1C, 0x79) ++#define REG_SC_BK1C_7A_L _PK_L_(0x1C, 0x7A) ++#define REG_SC_BK1C_7A_H _PK_H_(0x1C, 0x7A) ++#define REG_SC_BK1C_7B_L _PK_L_(0x1C, 0x7B) ++#define REG_SC_BK1C_7B_H _PK_H_(0x1C, 0x7B) ++#define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) ++#define REG_SC_BK1C_7C_H _PK_H_(0x1C, 0x7C) ++#define REG_SC_BK1C_7D_L _PK_L_(0x1C, 0x7D) ++#define REG_SC_BK1C_7D_H _PK_H_(0x1C, 0x7D) ++#define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) ++#define REG_SC_BK1C_7E_H _PK_H_(0x1C, 0x7E) ++#define REG_SC_BK1C_7F_L _PK_L_(0x1C, 0x7F) ++#define REG_SC_BK1C_7F_H _PK_H_(0x1C, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1D_00_L _PK_L_(0x1D, 0x00) ++#define REG_SC_BK1D_00_H _PK_H_(0x1D, 0x00) ++#define REG_SC_BK1D_01_L _PK_L_(0x1D, 0x01) ++#define REG_SC_BK1D_01_H _PK_H_(0x1D, 0x01) ++#define REG_SC_BK1D_02_L _PK_L_(0x1D, 0x02) ++#define REG_SC_BK1D_02_H _PK_H_(0x1D, 0x02) ++#define REG_SC_BK1D_03_L _PK_L_(0x1D, 0x03) ++#define REG_SC_BK1D_03_H _PK_H_(0x1D, 0x03) ++#define REG_SC_BK1D_04_L _PK_L_(0x1D, 0x04) ++#define REG_SC_BK1D_04_H _PK_H_(0x1D, 0x04) ++#define REG_SC_BK1D_05_L _PK_L_(0x1D, 0x05) ++#define REG_SC_BK1D_05_H _PK_H_(0x1D, 0x05) ++#define REG_SC_BK1D_06_L _PK_L_(0x1D, 0x06) ++#define REG_SC_BK1D_06_H _PK_H_(0x1D, 0x06) ++#define REG_SC_BK1D_07_L _PK_L_(0x1D, 0x07) ++#define REG_SC_BK1D_07_H _PK_H_(0x1D, 0x07) ++#define REG_SC_BK1D_08_L _PK_L_(0x1D, 0x08) ++#define REG_SC_BK1D_08_H _PK_H_(0x1D, 0x08) ++#define REG_SC_BK1D_09_L _PK_L_(0x1D, 0x09) ++#define REG_SC_BK1D_09_H _PK_H_(0x1D, 0x09) ++#define REG_SC_BK1D_0A_L _PK_L_(0x1D, 0x0A) ++#define REG_SC_BK1D_0A_H _PK_H_(0x1D, 0x0A) ++#define REG_SC_BK1D_0B_L _PK_L_(0x1D, 0x0B) ++#define REG_SC_BK1D_0B_H _PK_H_(0x1D, 0x0B) ++#define REG_SC_BK1D_0C_L _PK_L_(0x1D, 0x0C) ++#define REG_SC_BK1D_0C_H _PK_H_(0x1D, 0x0C) ++#define REG_SC_BK1D_0D_L _PK_L_(0x1D, 0x0D) ++#define REG_SC_BK1D_0D_H _PK_H_(0x1D, 0x0D) ++#define REG_SC_BK1D_0E_L _PK_L_(0x1D, 0x0E) ++#define REG_SC_BK1D_0E_H _PK_H_(0x1D, 0x0E) ++#define REG_SC_BK1D_0F_L _PK_L_(0x1D, 0x0F) ++#define REG_SC_BK1D_0F_H _PK_H_(0x1D, 0x0F) ++#define REG_SC_BK1D_10_L _PK_L_(0x1D, 0x10) ++#define REG_SC_BK1D_10_H _PK_H_(0x1D, 0x10) ++#define REG_SC_BK1D_11_L _PK_L_(0x1D, 0x11) ++#define REG_SC_BK1D_11_H _PK_H_(0x1D, 0x11) ++#define REG_SC_BK1D_12_L _PK_L_(0x1D, 0x12) ++#define REG_SC_BK1D_12_H _PK_H_(0x1D, 0x12) ++#define REG_SC_BK1D_13_L _PK_L_(0x1D, 0x13) ++#define REG_SC_BK1D_13_H _PK_H_(0x1D, 0x13) ++#define REG_SC_BK1D_14_L _PK_L_(0x1D, 0x14) ++#define REG_SC_BK1D_14_H _PK_H_(0x1D, 0x14) ++#define REG_SC_BK1D_15_L _PK_L_(0x1D, 0x15) ++#define REG_SC_BK1D_15_H _PK_H_(0x1D, 0x15) ++#define REG_SC_BK1D_16_L _PK_L_(0x1D, 0x16) ++#define REG_SC_BK1D_16_H _PK_H_(0x1D, 0x16) ++#define REG_SC_BK1D_17_L _PK_L_(0x1D, 0x17) ++#define REG_SC_BK1D_17_H _PK_H_(0x1D, 0x17) ++#define REG_SC_BK1D_18_L _PK_L_(0x1D, 0x18) ++#define REG_SC_BK1D_18_H _PK_H_(0x1D, 0x18) ++#define REG_SC_BK1D_19_L _PK_L_(0x1D, 0x19) ++#define REG_SC_BK1D_19_H _PK_H_(0x1D, 0x19) ++#define REG_SC_BK1D_1A_L _PK_L_(0x1D, 0x1A) ++#define REG_SC_BK1D_1A_H _PK_H_(0x1D, 0x1A) ++#define REG_SC_BK1D_1B_L _PK_L_(0x1D, 0x1B) ++#define REG_SC_BK1D_1B_H _PK_H_(0x1D, 0x1B) ++#define REG_SC_BK1D_1C_L _PK_L_(0x1D, 0x1C) ++#define REG_SC_BK1D_1C_H _PK_H_(0x1D, 0x1C) ++#define REG_SC_BK1D_1D_L _PK_L_(0x1D, 0x1D) ++#define REG_SC_BK1D_1D_H _PK_H_(0x1D, 0x1D) ++#define REG_SC_BK1D_1E_L _PK_L_(0x1D, 0x1E) ++#define REG_SC_BK1D_1E_H _PK_H_(0x1D, 0x1E) ++#define REG_SC_BK1D_1F_L _PK_L_(0x1D, 0x1F) ++#define REG_SC_BK1D_1F_H _PK_H_(0x1D, 0x1F) ++#define REG_SC_BK1D_20_L _PK_L_(0x1D, 0x20) ++#define REG_SC_BK1D_20_H _PK_H_(0x1D, 0x20) ++#define REG_SC_BK1D_21_L _PK_L_(0x1D, 0x21) ++#define REG_SC_BK1D_21_H _PK_H_(0x1D, 0x21) ++#define REG_SC_BK1D_22_L _PK_L_(0x1D, 0x22) ++#define REG_SC_BK1D_22_H _PK_H_(0x1D, 0x22) ++#define REG_SC_BK1D_23_L _PK_L_(0x1D, 0x23) ++#define REG_SC_BK1D_23_H _PK_H_(0x1D, 0x23) ++#define REG_SC_BK1D_24_L _PK_L_(0x1D, 0x24) ++#define REG_SC_BK1D_24_H _PK_H_(0x1D, 0x24) ++#define REG_SC_BK1D_25_L _PK_L_(0x1D, 0x25) ++#define REG_SC_BK1D_25_H _PK_H_(0x1D, 0x25) ++#define REG_SC_BK1D_26_L _PK_L_(0x1D, 0x26) ++#define REG_SC_BK1D_26_H _PK_H_(0x1D, 0x26) ++#define REG_SC_BK1D_27_L _PK_L_(0x1D, 0x27) ++#define REG_SC_BK1D_27_H _PK_H_(0x1D, 0x27) ++#define REG_SC_BK1D_28_L _PK_L_(0x1D, 0x28) ++#define REG_SC_BK1D_28_H _PK_H_(0x1D, 0x28) ++#define REG_SC_BK1D_29_L _PK_L_(0x1D, 0x29) ++#define REG_SC_BK1D_29_H _PK_H_(0x1D, 0x29) ++#define REG_SC_BK1D_2A_L _PK_L_(0x1D, 0x2A) ++#define REG_SC_BK1D_2A_H _PK_H_(0x1D, 0x2A) ++#define REG_SC_BK1D_2B_L _PK_L_(0x1D, 0x2B) ++#define REG_SC_BK1D_2B_H _PK_H_(0x1D, 0x2B) ++#define REG_SC_BK1D_2C_L _PK_L_(0x1D, 0x2C) ++#define REG_SC_BK1D_2C_H _PK_H_(0x1D, 0x2C) ++#define REG_SC_BK1D_2D_L _PK_L_(0x1D, 0x2D) ++#define REG_SC_BK1D_2D_H _PK_H_(0x1D, 0x2D) ++#define REG_SC_BK1D_2E_L _PK_L_(0x1D, 0x2E) ++#define REG_SC_BK1D_2E_H _PK_H_(0x1D, 0x2E) ++#define REG_SC_BK1D_2F_L _PK_L_(0x1D, 0x2F) ++#define REG_SC_BK1D_2F_H _PK_H_(0x1D, 0x2F) ++#define REG_SC_BK1D_30_L _PK_L_(0x1D, 0x30) ++#define REG_SC_BK1D_30_H _PK_H_(0x1D, 0x30) ++#define REG_SC_BK1D_31_L _PK_L_(0x1D, 0x31) ++#define REG_SC_BK1D_31_H _PK_H_(0x1D, 0x31) ++#define REG_SC_BK1D_32_L _PK_L_(0x1D, 0x32) ++#define REG_SC_BK1D_32_H _PK_H_(0x1D, 0x32) ++#define REG_SC_BK1D_33_L _PK_L_(0x1D, 0x33) ++#define REG_SC_BK1D_33_H _PK_H_(0x1D, 0x33) ++#define REG_SC_BK1D_34_L _PK_L_(0x1D, 0x34) ++#define REG_SC_BK1D_34_H _PK_H_(0x1D, 0x34) ++#define REG_SC_BK1D_35_L _PK_L_(0x1D, 0x35) ++#define REG_SC_BK1D_35_H _PK_H_(0x1D, 0x35) ++#define REG_SC_BK1D_36_L _PK_L_(0x1D, 0x36) ++#define REG_SC_BK1D_36_H _PK_H_(0x1D, 0x36) ++#define REG_SC_BK1D_37_L _PK_L_(0x1D, 0x37) ++#define REG_SC_BK1D_37_H _PK_H_(0x1D, 0x37) ++#define REG_SC_BK1D_38_L _PK_L_(0x1D, 0x38) ++#define REG_SC_BK1D_38_H _PK_H_(0x1D, 0x38) ++#define REG_SC_BK1D_39_L _PK_L_(0x1D, 0x39) ++#define REG_SC_BK1D_39_H _PK_H_(0x1D, 0x39) ++#define REG_SC_BK1D_3A_L _PK_L_(0x1D, 0x3A) ++#define REG_SC_BK1D_3A_H _PK_H_(0x1D, 0x3A) ++#define REG_SC_BK1D_3B_L _PK_L_(0x1D, 0x3B) ++#define REG_SC_BK1D_3B_H _PK_H_(0x1D, 0x3B) ++#define REG_SC_BK1D_3C_L _PK_L_(0x1D, 0x3C) ++#define REG_SC_BK1D_3C_H _PK_H_(0x1D, 0x3C) ++#define REG_SC_BK1D_3D_L _PK_L_(0x1D, 0x3D) ++#define REG_SC_BK1D_3D_H _PK_H_(0x1D, 0x3D) ++#define REG_SC_BK1D_3E_L _PK_L_(0x1D, 0x3E) ++#define REG_SC_BK1D_3E_H _PK_H_(0x1D, 0x3E) ++#define REG_SC_BK1D_3F_L _PK_L_(0x1D, 0x3F) ++#define REG_SC_BK1D_3F_H _PK_H_(0x1D, 0x3F) ++#define REG_SC_BK1D_40_L _PK_L_(0x1D, 0x40) ++#define REG_SC_BK1D_40_H _PK_H_(0x1D, 0x40) ++#define REG_SC_BK1D_41_L _PK_L_(0x1D, 0x41) ++#define REG_SC_BK1D_41_H _PK_H_(0x1D, 0x41) ++#define REG_SC_BK1D_42_L _PK_L_(0x1D, 0x42) ++#define REG_SC_BK1D_42_H _PK_H_(0x1D, 0x42) ++#define REG_SC_BK1D_43_L _PK_L_(0x1D, 0x43) ++#define REG_SC_BK1D_43_H _PK_H_(0x1D, 0x43) ++#define REG_SC_BK1D_44_L _PK_L_(0x1D, 0x44) ++#define REG_SC_BK1D_44_H _PK_H_(0x1D, 0x44) ++#define REG_SC_BK1D_45_L _PK_L_(0x1D, 0x45) ++#define REG_SC_BK1D_45_H _PK_H_(0x1D, 0x45) ++#define REG_SC_BK1D_46_L _PK_L_(0x1D, 0x46) ++#define REG_SC_BK1D_46_H _PK_H_(0x1D, 0x46) ++#define REG_SC_BK1D_47_L _PK_L_(0x1D, 0x47) ++#define REG_SC_BK1D_47_H _PK_H_(0x1D, 0x47) ++#define REG_SC_BK1D_48_L _PK_L_(0x1D, 0x48) ++#define REG_SC_BK1D_48_H _PK_H_(0x1D, 0x48) ++#define REG_SC_BK1D_49_L _PK_L_(0x1D, 0x49) ++#define REG_SC_BK1D_49_H _PK_H_(0x1D, 0x49) ++#define REG_SC_BK1D_4A_L _PK_L_(0x1D, 0x4A) ++#define REG_SC_BK1D_4A_H _PK_H_(0x1D, 0x4A) ++#define REG_SC_BK1D_4B_L _PK_L_(0x1D, 0x4B) ++#define REG_SC_BK1D_4B_H _PK_H_(0x1D, 0x4B) ++#define REG_SC_BK1D_4C_L _PK_L_(0x1D, 0x4C) ++#define REG_SC_BK1D_4C_H _PK_H_(0x1D, 0x4C) ++#define REG_SC_BK1D_4D_L _PK_L_(0x1D, 0x4D) ++#define REG_SC_BK1D_4D_H _PK_H_(0x1D, 0x4D) ++#define REG_SC_BK1D_4E_L _PK_L_(0x1D, 0x4E) ++#define REG_SC_BK1D_4E_H _PK_H_(0x1D, 0x4E) ++#define REG_SC_BK1D_4F_L _PK_L_(0x1D, 0x4F) ++#define REG_SC_BK1D_4F_H _PK_H_(0x1D, 0x4F) ++#define REG_SC_BK1D_50_L _PK_L_(0x1D, 0x50) ++#define REG_SC_BK1D_50_H _PK_H_(0x1D, 0x50) ++#define REG_SC_BK1D_51_L _PK_L_(0x1D, 0x51) ++#define REG_SC_BK1D_51_H _PK_H_(0x1D, 0x51) ++#define REG_SC_BK1D_52_L _PK_L_(0x1D, 0x52) ++#define REG_SC_BK1D_52_H _PK_H_(0x1D, 0x52) ++#define REG_SC_BK1D_53_L _PK_L_(0x1D, 0x53) ++#define REG_SC_BK1D_53_H _PK_H_(0x1D, 0x53) ++#define REG_SC_BK1D_54_L _PK_L_(0x1D, 0x54) ++#define REG_SC_BK1D_54_H _PK_H_(0x1D, 0x54) ++#define REG_SC_BK1D_55_L _PK_L_(0x1D, 0x55) ++#define REG_SC_BK1D_55_H _PK_H_(0x1D, 0x55) ++#define REG_SC_BK1D_56_L _PK_L_(0x1D, 0x56) ++#define REG_SC_BK1D_56_H _PK_H_(0x1D, 0x56) ++#define REG_SC_BK1D_57_L _PK_L_(0x1D, 0x57) ++#define REG_SC_BK1D_57_H _PK_H_(0x1D, 0x57) ++#define REG_SC_BK1D_58_L _PK_L_(0x1D, 0x58) ++#define REG_SC_BK1D_58_H _PK_H_(0x1D, 0x58) ++#define REG_SC_BK1D_59_L _PK_L_(0x1D, 0x59) ++#define REG_SC_BK1D_59_H _PK_H_(0x1D, 0x59) ++#define REG_SC_BK1D_5A_L _PK_L_(0x1D, 0x5A) ++#define REG_SC_BK1D_5A_H _PK_H_(0x1D, 0x5A) ++#define REG_SC_BK1D_5B_L _PK_L_(0x1D, 0x5B) ++#define REG_SC_BK1D_5B_H _PK_H_(0x1D, 0x5B) ++#define REG_SC_BK1D_5C_L _PK_L_(0x1D, 0x5C) ++#define REG_SC_BK1D_5C_H _PK_H_(0x1D, 0x5C) ++#define REG_SC_BK1D_5D_L _PK_L_(0x1D, 0x5D) ++#define REG_SC_BK1D_5D_H _PK_H_(0x1D, 0x5D) ++#define REG_SC_BK1D_5E_L _PK_L_(0x1D, 0x5E) ++#define REG_SC_BK1D_5E_H _PK_H_(0x1D, 0x5E) ++#define REG_SC_BK1D_5F_L _PK_L_(0x1D, 0x5F) ++#define REG_SC_BK1D_5F_H _PK_H_(0x1D, 0x5F) ++#define REG_SC_BK1D_60_L _PK_L_(0x1D, 0x60) ++#define REG_SC_BK1D_60_H _PK_H_(0x1D, 0x60) ++#define REG_SC_BK1D_61_L _PK_L_(0x1D, 0x61) ++#define REG_SC_BK1D_61_H _PK_H_(0x1D, 0x61) ++#define REG_SC_BK1D_62_L _PK_L_(0x1D, 0x62) ++#define REG_SC_BK1D_62_H _PK_H_(0x1D, 0x62) ++#define REG_SC_BK1D_63_L _PK_L_(0x1D, 0x63) ++#define REG_SC_BK1D_63_H _PK_H_(0x1D, 0x63) ++#define REG_SC_BK1D_64_L _PK_L_(0x1D, 0x64) ++#define REG_SC_BK1D_64_H _PK_H_(0x1D, 0x64) ++#define REG_SC_BK1D_65_L _PK_L_(0x1D, 0x65) ++#define REG_SC_BK1D_65_H _PK_H_(0x1D, 0x65) ++#define REG_SC_BK1D_66_L _PK_L_(0x1D, 0x66) ++#define REG_SC_BK1D_66_H _PK_H_(0x1D, 0x66) ++#define REG_SC_BK1D_67_L _PK_L_(0x1D, 0x67) ++#define REG_SC_BK1D_67_H _PK_H_(0x1D, 0x67) ++#define REG_SC_BK1D_68_L _PK_L_(0x1D, 0x68) ++#define REG_SC_BK1D_68_H _PK_H_(0x1D, 0x68) ++#define REG_SC_BK1D_69_L _PK_L_(0x1D, 0x69) ++#define REG_SC_BK1D_69_H _PK_H_(0x1D, 0x69) ++#define REG_SC_BK1D_6A_L _PK_L_(0x1D, 0x6A) ++#define REG_SC_BK1D_6A_H _PK_H_(0x1D, 0x6A) ++#define REG_SC_BK1D_6B_L _PK_L_(0x1D, 0x6B) ++#define REG_SC_BK1D_6B_H _PK_H_(0x1D, 0x6B) ++#define REG_SC_BK1D_6C_L _PK_L_(0x1D, 0x6C) ++#define REG_SC_BK1D_6C_H _PK_H_(0x1D, 0x6C) ++#define REG_SC_BK1D_6D_L _PK_L_(0x1D, 0x6D) ++#define REG_SC_BK1D_6D_H _PK_H_(0x1D, 0x6D) ++#define REG_SC_BK1D_6E_L _PK_L_(0x1D, 0x6E) ++#define REG_SC_BK1D_6E_H _PK_H_(0x1D, 0x6E) ++#define REG_SC_BK1D_6F_L _PK_L_(0x1D, 0x6F) ++#define REG_SC_BK1D_6F_H _PK_H_(0x1D, 0x6F) ++#define REG_SC_BK1D_70_L _PK_L_(0x1D, 0x70) ++#define REG_SC_BK1D_70_H _PK_H_(0x1D, 0x70) ++#define REG_SC_BK1D_71_L _PK_L_(0x1D, 0x71) ++#define REG_SC_BK1D_71_H _PK_H_(0x1D, 0x71) ++#define REG_SC_BK1D_72_L _PK_L_(0x1D, 0x72) ++#define REG_SC_BK1D_72_H _PK_H_(0x1D, 0x72) ++#define REG_SC_BK1D_73_L _PK_L_(0x1D, 0x73) ++#define REG_SC_BK1D_73_H _PK_H_(0x1D, 0x73) ++#define REG_SC_BK1D_74_L _PK_L_(0x1D, 0x74) ++#define REG_SC_BK1D_74_H _PK_H_(0x1D, 0x74) ++#define REG_SC_BK1D_75_L _PK_L_(0x1D, 0x75) ++#define REG_SC_BK1D_75_H _PK_H_(0x1D, 0x75) ++#define REG_SC_BK1D_76_L _PK_L_(0x1D, 0x76) ++#define REG_SC_BK1D_76_H _PK_H_(0x1D, 0x76) ++#define REG_SC_BK1D_77_L _PK_L_(0x1D, 0x77) ++#define REG_SC_BK1D_77_H _PK_H_(0x1D, 0x77) ++#define REG_SC_BK1D_78_L _PK_L_(0x1D, 0x78) ++#define REG_SC_BK1D_78_H _PK_H_(0x1D, 0x78) ++#define REG_SC_BK1D_79_L _PK_L_(0x1D, 0x79) ++#define REG_SC_BK1D_79_H _PK_H_(0x1D, 0x79) ++#define REG_SC_BK1D_7A_L _PK_L_(0x1D, 0x7A) ++#define REG_SC_BK1D_7A_H _PK_H_(0x1D, 0x7A) ++#define REG_SC_BK1D_7B_L _PK_L_(0x1D, 0x7B) ++#define REG_SC_BK1D_7B_H _PK_H_(0x1D, 0x7B) ++#define REG_SC_BK1D_7C_L _PK_L_(0x1D, 0x7C) ++#define REG_SC_BK1D_7C_H _PK_H_(0x1D, 0x7C) ++#define REG_SC_BK1D_7D_L _PK_L_(0x1D, 0x7D) ++#define REG_SC_BK1D_7D_H _PK_H_(0x1D, 0x7D) ++#define REG_SC_BK1D_7E_L _PK_L_(0x1D, 0x7E) ++#define REG_SC_BK1D_7E_H _PK_H_(0x1D, 0x7E) ++#define REG_SC_BK1D_7F_L _PK_L_(0x1D, 0x7F) ++#define REG_SC_BK1D_7F_H _PK_H_(0x1D, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1E_00_L _PK_L_(0x1E, 0x00) ++#define REG_SC_BK1E_00_H _PK_H_(0x1E, 0x00) ++#define REG_SC_BK1E_01_L _PK_L_(0x1E, 0x01) ++#define REG_SC_BK1E_01_H _PK_H_(0x1E, 0x01) ++#define REG_SC_BK1E_02_L _PK_L_(0x1E, 0x02) ++#define REG_SC_BK1E_02_H _PK_H_(0x1E, 0x02) ++#define REG_SC_BK1E_03_L _PK_L_(0x1E, 0x03) ++#define REG_SC_BK1E_03_H _PK_H_(0x1E, 0x03) ++#define REG_SC_BK1E_04_L _PK_L_(0x1E, 0x04) ++#define REG_SC_BK1E_04_H _PK_H_(0x1E, 0x04) ++#define REG_SC_BK1E_05_L _PK_L_(0x1E, 0x05) ++#define REG_SC_BK1E_05_H _PK_H_(0x1E, 0x05) ++#define REG_SC_BK1E_06_L _PK_L_(0x1E, 0x06) ++#define REG_SC_BK1E_06_H _PK_H_(0x1E, 0x06) ++#define REG_SC_BK1E_07_L _PK_L_(0x1E, 0x07) ++#define REG_SC_BK1E_07_H _PK_H_(0x1E, 0x07) ++#define REG_SC_BK1E_08_L _PK_L_(0x1E, 0x08) ++#define REG_SC_BK1E_08_H _PK_H_(0x1E, 0x08) ++#define REG_SC_BK1E_09_L _PK_L_(0x1E, 0x09) ++#define REG_SC_BK1E_09_H _PK_H_(0x1E, 0x09) ++#define REG_SC_BK1E_0A_L _PK_L_(0x1E, 0x0A) ++#define REG_SC_BK1E_0A_H _PK_H_(0x1E, 0x0A) ++#define REG_SC_BK1E_0B_L _PK_L_(0x1E, 0x0B) ++#define REG_SC_BK1E_0B_H _PK_H_(0x1E, 0x0B) ++#define REG_SC_BK1E_0C_L _PK_L_(0x1E, 0x0C) ++#define REG_SC_BK1E_0C_H _PK_H_(0x1E, 0x0C) ++#define REG_SC_BK1E_0D_L _PK_L_(0x1E, 0x0D) ++#define REG_SC_BK1E_0D_H _PK_H_(0x1E, 0x0D) ++#define REG_SC_BK1E_0E_L _PK_L_(0x1E, 0x0E) ++#define REG_SC_BK1E_0E_H _PK_H_(0x1E, 0x0E) ++#define REG_SC_BK1E_0F_L _PK_L_(0x1E, 0x0F) ++#define REG_SC_BK1E_0F_H _PK_H_(0x1E, 0x0F) ++#define REG_SC_BK1E_10_L _PK_L_(0x1E, 0x10) ++#define REG_SC_BK1E_10_H _PK_H_(0x1E, 0x10) ++#define REG_SC_BK1E_11_L _PK_L_(0x1E, 0x11) ++#define REG_SC_BK1E_11_H _PK_H_(0x1E, 0x11) ++#define REG_SC_BK1E_12_L _PK_L_(0x1E, 0x12) ++#define REG_SC_BK1E_12_H _PK_H_(0x1E, 0x12) ++#define REG_SC_BK1E_13_L _PK_L_(0x1E, 0x13) ++#define REG_SC_BK1E_13_H _PK_H_(0x1E, 0x13) ++#define REG_SC_BK1E_14_L _PK_L_(0x1E, 0x14) ++#define REG_SC_BK1E_14_H _PK_H_(0x1E, 0x14) ++#define REG_SC_BK1E_15_L _PK_L_(0x1E, 0x15) ++#define REG_SC_BK1E_15_H _PK_H_(0x1E, 0x15) ++#define REG_SC_BK1E_16_L _PK_L_(0x1E, 0x16) ++#define REG_SC_BK1E_16_H _PK_H_(0x1E, 0x16) ++#define REG_SC_BK1E_17_L _PK_L_(0x1E, 0x17) ++#define REG_SC_BK1E_17_H _PK_H_(0x1E, 0x17) ++#define REG_SC_BK1E_18_L _PK_L_(0x1E, 0x18) ++#define REG_SC_BK1E_18_H _PK_H_(0x1E, 0x18) ++#define REG_SC_BK1E_19_L _PK_L_(0x1E, 0x19) ++#define REG_SC_BK1E_19_H _PK_H_(0x1E, 0x19) ++#define REG_SC_BK1E_1A_L _PK_L_(0x1E, 0x1A) ++#define REG_SC_BK1E_1A_H _PK_H_(0x1E, 0x1A) ++#define REG_SC_BK1E_1B_L _PK_L_(0x1E, 0x1B) ++#define REG_SC_BK1E_1B_H _PK_H_(0x1E, 0x1B) ++#define REG_SC_BK1E_1C_L _PK_L_(0x1E, 0x1C) ++#define REG_SC_BK1E_1C_H _PK_H_(0x1E, 0x1C) ++#define REG_SC_BK1E_1D_L _PK_L_(0x1E, 0x1D) ++#define REG_SC_BK1E_1D_H _PK_H_(0x1E, 0x1D) ++#define REG_SC_BK1E_1E_L _PK_L_(0x1E, 0x1E) ++#define REG_SC_BK1E_1E_H _PK_H_(0x1E, 0x1E) ++#define REG_SC_BK1E_1F_L _PK_L_(0x1E, 0x1F) ++#define REG_SC_BK1E_1F_H _PK_H_(0x1E, 0x1F) ++#define REG_SC_BK1E_20_L _PK_L_(0x1E, 0x20) ++#define REG_SC_BK1E_20_H _PK_H_(0x1E, 0x20) ++#define REG_SC_BK1E_21_L _PK_L_(0x1E, 0x21) ++#define REG_SC_BK1E_21_H _PK_H_(0x1E, 0x21) ++#define REG_SC_BK1E_22_L _PK_L_(0x1E, 0x22) ++#define REG_SC_BK1E_22_H _PK_H_(0x1E, 0x22) ++#define REG_SC_BK1E_23_L _PK_L_(0x1E, 0x23) ++#define REG_SC_BK1E_23_H _PK_H_(0x1E, 0x23) ++#define REG_SC_BK1E_24_L _PK_L_(0x1E, 0x24) ++#define REG_SC_BK1E_24_H _PK_H_(0x1E, 0x24) ++#define REG_SC_BK1E_25_L _PK_L_(0x1E, 0x25) ++#define REG_SC_BK1E_25_H _PK_H_(0x1E, 0x25) ++#define REG_SC_BK1E_26_L _PK_L_(0x1E, 0x26) ++#define REG_SC_BK1E_26_H _PK_H_(0x1E, 0x26) ++#define REG_SC_BK1E_27_L _PK_L_(0x1E, 0x27) ++#define REG_SC_BK1E_27_H _PK_H_(0x1E, 0x27) ++#define REG_SC_BK1E_28_L _PK_L_(0x1E, 0x28) ++#define REG_SC_BK1E_28_H _PK_H_(0x1E, 0x28) ++#define REG_SC_BK1E_29_L _PK_L_(0x1E, 0x29) ++#define REG_SC_BK1E_29_H _PK_H_(0x1E, 0x29) ++#define REG_SC_BK1E_2A_L _PK_L_(0x1E, 0x2A) ++#define REG_SC_BK1E_2A_H _PK_H_(0x1E, 0x2A) ++#define REG_SC_BK1E_2B_L _PK_L_(0x1E, 0x2B) ++#define REG_SC_BK1E_2B_H _PK_H_(0x1E, 0x2B) ++#define REG_SC_BK1E_2C_L _PK_L_(0x1E, 0x2C) ++#define REG_SC_BK1E_2C_H _PK_H_(0x1E, 0x2C) ++#define REG_SC_BK1E_2D_L _PK_L_(0x1E, 0x2D) ++#define REG_SC_BK1E_2D_H _PK_H_(0x1E, 0x2D) ++#define REG_SC_BK1E_2E_L _PK_L_(0x1E, 0x2E) ++#define REG_SC_BK1E_2E_H _PK_H_(0x1E, 0x2E) ++#define REG_SC_BK1E_2F_L _PK_L_(0x1E, 0x2F) ++#define REG_SC_BK1E_2F_H _PK_H_(0x1E, 0x2F) ++#define REG_SC_BK1E_30_L _PK_L_(0x1E, 0x30) ++#define REG_SC_BK1E_30_H _PK_H_(0x1E, 0x30) ++#define REG_SC_BK1E_31_L _PK_L_(0x1E, 0x31) ++#define REG_SC_BK1E_31_H _PK_H_(0x1E, 0x31) ++#define REG_SC_BK1E_32_L _PK_L_(0x1E, 0x32) ++#define REG_SC_BK1E_32_H _PK_H_(0x1E, 0x32) ++#define REG_SC_BK1E_33_L _PK_L_(0x1E, 0x33) ++#define REG_SC_BK1E_33_H _PK_H_(0x1E, 0x33) ++#define REG_SC_BK1E_34_L _PK_L_(0x1E, 0x34) ++#define REG_SC_BK1E_34_H _PK_H_(0x1E, 0x34) ++#define REG_SC_BK1E_35_L _PK_L_(0x1E, 0x35) ++#define REG_SC_BK1E_35_H _PK_H_(0x1E, 0x35) ++#define REG_SC_BK1E_36_L _PK_L_(0x1E, 0x36) ++#define REG_SC_BK1E_36_H _PK_H_(0x1E, 0x36) ++#define REG_SC_BK1E_37_L _PK_L_(0x1E, 0x37) ++#define REG_SC_BK1E_37_H _PK_H_(0x1E, 0x37) ++#define REG_SC_BK1E_38_L _PK_L_(0x1E, 0x38) ++#define REG_SC_BK1E_38_H _PK_H_(0x1E, 0x38) ++#define REG_SC_BK1E_39_L _PK_L_(0x1E, 0x39) ++#define REG_SC_BK1E_39_H _PK_H_(0x1E, 0x39) ++#define REG_SC_BK1E_3A_L _PK_L_(0x1E, 0x3A) ++#define REG_SC_BK1E_3A_H _PK_H_(0x1E, 0x3A) ++#define REG_SC_BK1E_3B_L _PK_L_(0x1E, 0x3B) ++#define REG_SC_BK1E_3B_H _PK_H_(0x1E, 0x3B) ++#define REG_SC_BK1E_3C_L _PK_L_(0x1E, 0x3C) ++#define REG_SC_BK1E_3C_H _PK_H_(0x1E, 0x3C) ++#define REG_SC_BK1E_3D_L _PK_L_(0x1E, 0x3D) ++#define REG_SC_BK1E_3D_H _PK_H_(0x1E, 0x3D) ++#define REG_SC_BK1E_3E_L _PK_L_(0x1E, 0x3E) ++#define REG_SC_BK1E_3E_H _PK_H_(0x1E, 0x3E) ++#define REG_SC_BK1E_3F_L _PK_L_(0x1E, 0x3F) ++#define REG_SC_BK1E_3F_H _PK_H_(0x1E, 0x3F) ++#define REG_SC_BK1E_40_L _PK_L_(0x1E, 0x40) ++#define REG_SC_BK1E_40_H _PK_H_(0x1E, 0x40) ++#define REG_SC_BK1E_41_L _PK_L_(0x1E, 0x41) ++#define REG_SC_BK1E_41_H _PK_H_(0x1E, 0x41) ++#define REG_SC_BK1E_42_L _PK_L_(0x1E, 0x42) ++#define REG_SC_BK1E_42_H _PK_H_(0x1E, 0x42) ++#define REG_SC_BK1E_43_L _PK_L_(0x1E, 0x43) ++#define REG_SC_BK1E_43_H _PK_H_(0x1E, 0x43) ++#define REG_SC_BK1E_44_L _PK_L_(0x1E, 0x44) ++#define REG_SC_BK1E_44_H _PK_H_(0x1E, 0x44) ++#define REG_SC_BK1E_45_L _PK_L_(0x1E, 0x45) ++#define REG_SC_BK1E_45_H _PK_H_(0x1E, 0x45) ++#define REG_SC_BK1E_46_L _PK_L_(0x1E, 0x46) ++#define REG_SC_BK1E_46_H _PK_H_(0x1E, 0x46) ++#define REG_SC_BK1E_47_L _PK_L_(0x1E, 0x47) ++#define REG_SC_BK1E_47_H _PK_H_(0x1E, 0x47) ++#define REG_SC_BK1E_48_L _PK_L_(0x1E, 0x48) ++#define REG_SC_BK1E_48_H _PK_H_(0x1E, 0x48) ++#define REG_SC_BK1E_49_L _PK_L_(0x1E, 0x49) ++#define REG_SC_BK1E_49_H _PK_H_(0x1E, 0x49) ++#define REG_SC_BK1E_4A_L _PK_L_(0x1E, 0x4A) ++#define REG_SC_BK1E_4A_H _PK_H_(0x1E, 0x4A) ++#define REG_SC_BK1E_4B_L _PK_L_(0x1E, 0x4B) ++#define REG_SC_BK1E_4B_H _PK_H_(0x1E, 0x4B) ++#define REG_SC_BK1E_4C_L _PK_L_(0x1E, 0x4C) ++#define REG_SC_BK1E_4C_H _PK_H_(0x1E, 0x4C) ++#define REG_SC_BK1E_4D_L _PK_L_(0x1E, 0x4D) ++#define REG_SC_BK1E_4D_H _PK_H_(0x1E, 0x4D) ++#define REG_SC_BK1E_4E_L _PK_L_(0x1E, 0x4E) ++#define REG_SC_BK1E_4E_H _PK_H_(0x1E, 0x4E) ++#define REG_SC_BK1E_4F_L _PK_L_(0x1E, 0x4F) ++#define REG_SC_BK1E_4F_H _PK_H_(0x1E, 0x4F) ++#define REG_SC_BK1E_50_L _PK_L_(0x1E, 0x50) ++#define REG_SC_BK1E_50_H _PK_H_(0x1E, 0x50) ++#define REG_SC_BK1E_51_L _PK_L_(0x1E, 0x51) ++#define REG_SC_BK1E_51_H _PK_H_(0x1E, 0x51) ++#define REG_SC_BK1E_52_L _PK_L_(0x1E, 0x52) ++#define REG_SC_BK1E_52_H _PK_H_(0x1E, 0x52) ++#define REG_SC_BK1E_53_L _PK_L_(0x1E, 0x53) ++#define REG_SC_BK1E_53_H _PK_H_(0x1E, 0x53) ++#define REG_SC_BK1E_54_L _PK_L_(0x1E, 0x54) ++#define REG_SC_BK1E_54_H _PK_H_(0x1E, 0x54) ++#define REG_SC_BK1E_55_L _PK_L_(0x1E, 0x55) ++#define REG_SC_BK1E_55_H _PK_H_(0x1E, 0x55) ++#define REG_SC_BK1E_56_L _PK_L_(0x1E, 0x56) ++#define REG_SC_BK1E_56_H _PK_H_(0x1E, 0x56) ++#define REG_SC_BK1E_57_L _PK_L_(0x1E, 0x57) ++#define REG_SC_BK1E_57_H _PK_H_(0x1E, 0x57) ++#define REG_SC_BK1E_58_L _PK_L_(0x1E, 0x58) ++#define REG_SC_BK1E_58_H _PK_H_(0x1E, 0x58) ++#define REG_SC_BK1E_59_L _PK_L_(0x1E, 0x59) ++#define REG_SC_BK1E_59_H _PK_H_(0x1E, 0x59) ++#define REG_SC_BK1E_5A_L _PK_L_(0x1E, 0x5A) ++#define REG_SC_BK1E_5A_H _PK_H_(0x1E, 0x5A) ++#define REG_SC_BK1E_5B_L _PK_L_(0x1E, 0x5B) ++#define REG_SC_BK1E_5B_H _PK_H_(0x1E, 0x5B) ++#define REG_SC_BK1E_5C_L _PK_L_(0x1E, 0x5C) ++#define REG_SC_BK1E_5C_H _PK_H_(0x1E, 0x5C) ++#define REG_SC_BK1E_5D_L _PK_L_(0x1E, 0x5D) ++#define REG_SC_BK1E_5D_H _PK_H_(0x1E, 0x5D) ++#define REG_SC_BK1E_5E_L _PK_L_(0x1E, 0x5E) ++#define REG_SC_BK1E_5E_H _PK_H_(0x1E, 0x5E) ++#define REG_SC_BK1E_5F_L _PK_L_(0x1E, 0x5F) ++#define REG_SC_BK1E_5F_H _PK_H_(0x1E, 0x5F) ++#define REG_SC_BK1E_60_L _PK_L_(0x1E, 0x60) ++#define REG_SC_BK1E_60_H _PK_H_(0x1E, 0x60) ++#define REG_SC_BK1E_61_L _PK_L_(0x1E, 0x61) ++#define REG_SC_BK1E_61_H _PK_H_(0x1E, 0x61) ++#define REG_SC_BK1E_62_L _PK_L_(0x1E, 0x62) ++#define REG_SC_BK1E_62_H _PK_H_(0x1E, 0x62) ++#define REG_SC_BK1E_63_L _PK_L_(0x1E, 0x63) ++#define REG_SC_BK1E_63_H _PK_H_(0x1E, 0x63) ++#define REG_SC_BK1E_64_L _PK_L_(0x1E, 0x64) ++#define REG_SC_BK1E_64_H _PK_H_(0x1E, 0x64) ++#define REG_SC_BK1E_65_L _PK_L_(0x1E, 0x65) ++#define REG_SC_BK1E_65_H _PK_H_(0x1E, 0x65) ++#define REG_SC_BK1E_66_L _PK_L_(0x1E, 0x66) ++#define REG_SC_BK1E_66_H _PK_H_(0x1E, 0x66) ++#define REG_SC_BK1E_67_L _PK_L_(0x1E, 0x67) ++#define REG_SC_BK1E_67_H _PK_H_(0x1E, 0x67) ++#define REG_SC_BK1E_68_L _PK_L_(0x1E, 0x68) ++#define REG_SC_BK1E_68_H _PK_H_(0x1E, 0x68) ++#define REG_SC_BK1E_69_L _PK_L_(0x1E, 0x69) ++#define REG_SC_BK1E_69_H _PK_H_(0x1E, 0x69) ++#define REG_SC_BK1E_6A_L _PK_L_(0x1E, 0x6A) ++#define REG_SC_BK1E_6A_H _PK_H_(0x1E, 0x6A) ++#define REG_SC_BK1E_6B_L _PK_L_(0x1E, 0x6B) ++#define REG_SC_BK1E_6B_H _PK_H_(0x1E, 0x6B) ++#define REG_SC_BK1E_6C_L _PK_L_(0x1E, 0x6C) ++#define REG_SC_BK1E_6C_H _PK_H_(0x1E, 0x6C) ++#define REG_SC_BK1E_6D_L _PK_L_(0x1E, 0x6D) ++#define REG_SC_BK1E_6D_H _PK_H_(0x1E, 0x6D) ++#define REG_SC_BK1E_6E_L _PK_L_(0x1E, 0x6E) ++#define REG_SC_BK1E_6E_H _PK_H_(0x1E, 0x6E) ++#define REG_SC_BK1E_6F_L _PK_L_(0x1E, 0x6F) ++#define REG_SC_BK1E_6F_H _PK_H_(0x1E, 0x6F) ++#define REG_SC_BK1E_70_L _PK_L_(0x1E, 0x70) ++#define REG_SC_BK1E_70_H _PK_H_(0x1E, 0x70) ++#define REG_SC_BK1E_71_L _PK_L_(0x1E, 0x71) ++#define REG_SC_BK1E_71_H _PK_H_(0x1E, 0x71) ++#define REG_SC_BK1E_72_L _PK_L_(0x1E, 0x72) ++#define REG_SC_BK1E_72_H _PK_H_(0x1E, 0x72) ++#define REG_SC_BK1E_73_L _PK_L_(0x1E, 0x73) ++#define REG_SC_BK1E_73_H _PK_H_(0x1E, 0x73) ++#define REG_SC_BK1E_74_L _PK_L_(0x1E, 0x74) ++#define REG_SC_BK1E_74_H _PK_H_(0x1E, 0x74) ++#define REG_SC_BK1E_75_L _PK_L_(0x1E, 0x75) ++#define REG_SC_BK1E_75_H _PK_H_(0x1E, 0x75) ++#define REG_SC_BK1E_76_L _PK_L_(0x1E, 0x76) ++#define REG_SC_BK1E_76_H _PK_H_(0x1E, 0x76) ++#define REG_SC_BK1E_77_L _PK_L_(0x1E, 0x77) ++#define REG_SC_BK1E_77_H _PK_H_(0x1E, 0x77) ++#define REG_SC_BK1E_78_L _PK_L_(0x1E, 0x78) ++#define REG_SC_BK1E_78_H _PK_H_(0x1E, 0x78) ++#define REG_SC_BK1E_79_L _PK_L_(0x1E, 0x79) ++#define REG_SC_BK1E_79_H _PK_H_(0x1E, 0x79) ++#define REG_SC_BK1E_7A_L _PK_L_(0x1E, 0x7A) ++#define REG_SC_BK1E_7A_H _PK_H_(0x1E, 0x7A) ++#define REG_SC_BK1E_7B_L _PK_L_(0x1E, 0x7B) ++#define REG_SC_BK1E_7B_H _PK_H_(0x1E, 0x7B) ++#define REG_SC_BK1E_7C_L _PK_L_(0x1E, 0x7C) ++#define REG_SC_BK1E_7C_H _PK_H_(0x1E, 0x7C) ++#define REG_SC_BK1E_7D_L _PK_L_(0x1E, 0x7D) ++#define REG_SC_BK1E_7D_H _PK_H_(0x1E, 0x7D) ++#define REG_SC_BK1E_7E_L _PK_L_(0x1E, 0x7E) ++#define REG_SC_BK1E_7E_H _PK_H_(0x1E, 0x7E) ++#define REG_SC_BK1E_7F_L _PK_L_(0x1E, 0x7F) ++#define REG_SC_BK1E_7F_H _PK_H_(0x1E, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1F_00_L _PK_L_(0x1F, 0x00) ++#define REG_SC_BK1F_00_H _PK_H_(0x1F, 0x00) ++#define REG_SC_BK1F_01_L _PK_L_(0x1F, 0x01) ++#define REG_SC_BK1F_01_H _PK_H_(0x1F, 0x01) ++#define REG_SC_BK1F_02_L _PK_L_(0x1F, 0x02) ++#define REG_SC_BK1F_02_H _PK_H_(0x1F, 0x02) ++#define REG_SC_BK1F_03_L _PK_L_(0x1F, 0x03) ++#define REG_SC_BK1F_03_H _PK_H_(0x1F, 0x03) ++#define REG_SC_BK1F_04_L _PK_L_(0x1F, 0x04) ++#define REG_SC_BK1F_04_H _PK_H_(0x1F, 0x04) ++#define REG_SC_BK1F_05_L _PK_L_(0x1F, 0x05) ++#define REG_SC_BK1F_05_H _PK_H_(0x1F, 0x05) ++#define REG_SC_BK1F_06_L _PK_L_(0x1F, 0x06) ++#define REG_SC_BK1F_06_H _PK_H_(0x1F, 0x06) ++#define REG_SC_BK1F_07_L _PK_L_(0x1F, 0x07) ++#define REG_SC_BK1F_07_H _PK_H_(0x1F, 0x07) ++#define REG_SC_BK1F_08_L _PK_L_(0x1F, 0x08) ++#define REG_SC_BK1F_08_H _PK_H_(0x1F, 0x08) ++#define REG_SC_BK1F_09_L _PK_L_(0x1F, 0x09) ++#define REG_SC_BK1F_09_H _PK_H_(0x1F, 0x09) ++#define REG_SC_BK1F_0A_L _PK_L_(0x1F, 0x0A) ++#define REG_SC_BK1F_0A_H _PK_H_(0x1F, 0x0A) ++#define REG_SC_BK1F_0B_L _PK_L_(0x1F, 0x0B) ++#define REG_SC_BK1F_0B_H _PK_H_(0x1F, 0x0B) ++#define REG_SC_BK1F_0C_L _PK_L_(0x1F, 0x0C) ++#define REG_SC_BK1F_0C_H _PK_H_(0x1F, 0x0C) ++#define REG_SC_BK1F_0D_L _PK_L_(0x1F, 0x0D) ++#define REG_SC_BK1F_0D_H _PK_H_(0x1F, 0x0D) ++#define REG_SC_BK1F_0E_L _PK_L_(0x1F, 0x0E) ++#define REG_SC_BK1F_0E_H _PK_H_(0x1F, 0x0E) ++#define REG_SC_BK1F_0F_L _PK_L_(0x1F, 0x0F) ++#define REG_SC_BK1F_0F_H _PK_H_(0x1F, 0x0F) ++#define REG_SC_BK1F_10_L _PK_L_(0x1F, 0x10) ++#define REG_SC_BK1F_10_H _PK_H_(0x1F, 0x10) ++#define REG_SC_BK1F_11_L _PK_L_(0x1F, 0x11) ++#define REG_SC_BK1F_11_H _PK_H_(0x1F, 0x11) ++#define REG_SC_BK1F_12_L _PK_L_(0x1F, 0x12) ++#define REG_SC_BK1F_12_H _PK_H_(0x1F, 0x12) ++#define REG_SC_BK1F_13_L _PK_L_(0x1F, 0x13) ++#define REG_SC_BK1F_13_H _PK_H_(0x1F, 0x13) ++#define REG_SC_BK1F_14_L _PK_L_(0x1F, 0x14) ++#define REG_SC_BK1F_14_H _PK_H_(0x1F, 0x14) ++#define REG_SC_BK1F_15_L _PK_L_(0x1F, 0x15) ++#define REG_SC_BK1F_15_H _PK_H_(0x1F, 0x15) ++#define REG_SC_BK1F_16_L _PK_L_(0x1F, 0x16) ++#define REG_SC_BK1F_16_H _PK_H_(0x1F, 0x16) ++#define REG_SC_BK1F_17_L _PK_L_(0x1F, 0x17) ++#define REG_SC_BK1F_17_H _PK_H_(0x1F, 0x17) ++#define REG_SC_BK1F_18_L _PK_L_(0x1F, 0x18) ++#define REG_SC_BK1F_18_H _PK_H_(0x1F, 0x18) ++#define REG_SC_BK1F_19_L _PK_L_(0x1F, 0x19) ++#define REG_SC_BK1F_19_H _PK_H_(0x1F, 0x19) ++#define REG_SC_BK1F_1A_L _PK_L_(0x1F, 0x1A) ++#define REG_SC_BK1F_1A_H _PK_H_(0x1F, 0x1A) ++#define REG_SC_BK1F_1B_L _PK_L_(0x1F, 0x1B) ++#define REG_SC_BK1F_1B_H _PK_H_(0x1F, 0x1B) ++#define REG_SC_BK1F_1C_L _PK_L_(0x1F, 0x1C) ++#define REG_SC_BK1F_1C_H _PK_H_(0x1F, 0x1C) ++#define REG_SC_BK1F_1D_L _PK_L_(0x1F, 0x1D) ++#define REG_SC_BK1F_1D_H _PK_H_(0x1F, 0x1D) ++#define REG_SC_BK1F_1E_L _PK_L_(0x1F, 0x1E) ++#define REG_SC_BK1F_1E_H _PK_H_(0x1F, 0x1E) ++#define REG_SC_BK1F_1F_L _PK_L_(0x1F, 0x1F) ++#define REG_SC_BK1F_1F_H _PK_H_(0x1F, 0x1F) ++#define REG_SC_BK1F_20_L _PK_L_(0x1F, 0x20) ++#define REG_SC_BK1F_20_H _PK_H_(0x1F, 0x20) ++#define REG_SC_BK1F_21_L _PK_L_(0x1F, 0x21) ++#define REG_SC_BK1F_21_H _PK_H_(0x1F, 0x21) ++#define REG_SC_BK1F_22_L _PK_L_(0x1F, 0x22) ++#define REG_SC_BK1F_22_H _PK_H_(0x1F, 0x22) ++#define REG_SC_BK1F_23_L _PK_L_(0x1F, 0x23) ++#define REG_SC_BK1F_23_H _PK_H_(0x1F, 0x23) ++#define REG_SC_BK1F_24_L _PK_L_(0x1F, 0x24) ++#define REG_SC_BK1F_24_H _PK_H_(0x1F, 0x24) ++#define REG_SC_BK1F_25_L _PK_L_(0x1F, 0x25) ++#define REG_SC_BK1F_25_H _PK_H_(0x1F, 0x25) ++#define REG_SC_BK1F_26_L _PK_L_(0x1F, 0x26) ++#define REG_SC_BK1F_26_H _PK_H_(0x1F, 0x26) ++#define REG_SC_BK1F_27_L _PK_L_(0x1F, 0x27) ++#define REG_SC_BK1F_27_H _PK_H_(0x1F, 0x27) ++#define REG_SC_BK1F_28_L _PK_L_(0x1F, 0x28) ++#define REG_SC_BK1F_28_H _PK_H_(0x1F, 0x28) ++#define REG_SC_BK1F_29_L _PK_L_(0x1F, 0x29) ++#define REG_SC_BK1F_29_H _PK_H_(0x1F, 0x29) ++#define REG_SC_BK1F_2A_L _PK_L_(0x1F, 0x2A) ++#define REG_SC_BK1F_2A_H _PK_H_(0x1F, 0x2A) ++#define REG_SC_BK1F_2B_L _PK_L_(0x1F, 0x2B) ++#define REG_SC_BK1F_2B_H _PK_H_(0x1F, 0x2B) ++#define REG_SC_BK1F_2C_L _PK_L_(0x1F, 0x2C) ++#define REG_SC_BK1F_2C_H _PK_H_(0x1F, 0x2C) ++#define REG_SC_BK1F_2D_L _PK_L_(0x1F, 0x2D) ++#define REG_SC_BK1F_2D_H _PK_H_(0x1F, 0x2D) ++#define REG_SC_BK1F_2E_L _PK_L_(0x1F, 0x2E) ++#define REG_SC_BK1F_2E_H _PK_H_(0x1F, 0x2E) ++#define REG_SC_BK1F_2F_L _PK_L_(0x1F, 0x2F) ++#define REG_SC_BK1F_2F_H _PK_H_(0x1F, 0x2F) ++#define REG_SC_BK1F_30_L _PK_L_(0x1F, 0x30) ++#define REG_SC_BK1F_30_H _PK_H_(0x1F, 0x30) ++#define REG_SC_BK1F_31_L _PK_L_(0x1F, 0x31) ++#define REG_SC_BK1F_31_H _PK_H_(0x1F, 0x31) ++#define REG_SC_BK1F_32_L _PK_L_(0x1F, 0x32) ++#define REG_SC_BK1F_32_H _PK_H_(0x1F, 0x32) ++#define REG_SC_BK1F_33_L _PK_L_(0x1F, 0x33) ++#define REG_SC_BK1F_33_H _PK_H_(0x1F, 0x33) ++#define REG_SC_BK1F_34_L _PK_L_(0x1F, 0x34) ++#define REG_SC_BK1F_34_H _PK_H_(0x1F, 0x34) ++#define REG_SC_BK1F_35_L _PK_L_(0x1F, 0x35) ++#define REG_SC_BK1F_35_H _PK_H_(0x1F, 0x35) ++#define REG_SC_BK1F_36_L _PK_L_(0x1F, 0x36) ++#define REG_SC_BK1F_36_H _PK_H_(0x1F, 0x36) ++#define REG_SC_BK1F_37_L _PK_L_(0x1F, 0x37) ++#define REG_SC_BK1F_37_H _PK_H_(0x1F, 0x37) ++#define REG_SC_BK1F_38_L _PK_L_(0x1F, 0x38) ++#define REG_SC_BK1F_38_H _PK_H_(0x1F, 0x38) ++#define REG_SC_BK1F_39_L _PK_L_(0x1F, 0x39) ++#define REG_SC_BK1F_39_H _PK_H_(0x1F, 0x39) ++#define REG_SC_BK1F_3A_L _PK_L_(0x1F, 0x3A) ++#define REG_SC_BK1F_3A_H _PK_H_(0x1F, 0x3A) ++#define REG_SC_BK1F_3B_L _PK_L_(0x1F, 0x3B) ++#define REG_SC_BK1F_3B_H _PK_H_(0x1F, 0x3B) ++#define REG_SC_BK1F_3C_L _PK_L_(0x1F, 0x3C) ++#define REG_SC_BK1F_3C_H _PK_H_(0x1F, 0x3C) ++#define REG_SC_BK1F_3D_L _PK_L_(0x1F, 0x3D) ++#define REG_SC_BK1F_3D_H _PK_H_(0x1F, 0x3D) ++#define REG_SC_BK1F_3E_L _PK_L_(0x1F, 0x3E) ++#define REG_SC_BK1F_3E_H _PK_H_(0x1F, 0x3E) ++#define REG_SC_BK1F_3F_L _PK_L_(0x1F, 0x3F) ++#define REG_SC_BK1F_3F_H _PK_H_(0x1F, 0x3F) ++#define REG_SC_BK1F_40_L _PK_L_(0x1F, 0x40) ++#define REG_SC_BK1F_40_H _PK_H_(0x1F, 0x40) ++#define REG_SC_BK1F_41_L _PK_L_(0x1F, 0x41) ++#define REG_SC_BK1F_41_H _PK_H_(0x1F, 0x41) ++#define REG_SC_BK1F_42_L _PK_L_(0x1F, 0x42) ++#define REG_SC_BK1F_42_H _PK_H_(0x1F, 0x42) ++#define REG_SC_BK1F_43_L _PK_L_(0x1F, 0x43) ++#define REG_SC_BK1F_43_H _PK_H_(0x1F, 0x43) ++#define REG_SC_BK1F_44_L _PK_L_(0x1F, 0x44) ++#define REG_SC_BK1F_44_H _PK_H_(0x1F, 0x44) ++#define REG_SC_BK1F_45_L _PK_L_(0x1F, 0x45) ++#define REG_SC_BK1F_45_H _PK_H_(0x1F, 0x45) ++#define REG_SC_BK1F_46_L _PK_L_(0x1F, 0x46) ++#define REG_SC_BK1F_46_H _PK_H_(0x1F, 0x46) ++#define REG_SC_BK1F_47_L _PK_L_(0x1F, 0x47) ++#define REG_SC_BK1F_47_H _PK_H_(0x1F, 0x47) ++#define REG_SC_BK1F_48_L _PK_L_(0x1F, 0x48) ++#define REG_SC_BK1F_48_H _PK_H_(0x1F, 0x48) ++#define REG_SC_BK1F_49_L _PK_L_(0x1F, 0x49) ++#define REG_SC_BK1F_49_H _PK_H_(0x1F, 0x49) ++#define REG_SC_BK1F_4A_L _PK_L_(0x1F, 0x4A) ++#define REG_SC_BK1F_4A_H _PK_H_(0x1F, 0x4A) ++#define REG_SC_BK1F_4B_L _PK_L_(0x1F, 0x4B) ++#define REG_SC_BK1F_4B_H _PK_H_(0x1F, 0x4B) ++#define REG_SC_BK1F_4C_L _PK_L_(0x1F, 0x4C) ++#define REG_SC_BK1F_4C_H _PK_H_(0x1F, 0x4C) ++#define REG_SC_BK1F_4D_L _PK_L_(0x1F, 0x4D) ++#define REG_SC_BK1F_4D_H _PK_H_(0x1F, 0x4D) ++#define REG_SC_BK1F_4E_L _PK_L_(0x1F, 0x4E) ++#define REG_SC_BK1F_4E_H _PK_H_(0x1F, 0x4E) ++#define REG_SC_BK1F_4F_L _PK_L_(0x1F, 0x4F) ++#define REG_SC_BK1F_4F_H _PK_H_(0x1F, 0x4F) ++#define REG_SC_BK1F_50_L _PK_L_(0x1F, 0x50) ++#define REG_SC_BK1F_50_H _PK_H_(0x1F, 0x50) ++#define REG_SC_BK1F_51_L _PK_L_(0x1F, 0x51) ++#define REG_SC_BK1F_51_H _PK_H_(0x1F, 0x51) ++#define REG_SC_BK1F_52_L _PK_L_(0x1F, 0x52) ++#define REG_SC_BK1F_52_H _PK_H_(0x1F, 0x52) ++#define REG_SC_BK1F_53_L _PK_L_(0x1F, 0x53) ++#define REG_SC_BK1F_53_H _PK_H_(0x1F, 0x53) ++#define REG_SC_BK1F_54_L _PK_L_(0x1F, 0x54) ++#define REG_SC_BK1F_54_H _PK_H_(0x1F, 0x54) ++#define REG_SC_BK1F_55_L _PK_L_(0x1F, 0x55) ++#define REG_SC_BK1F_55_H _PK_H_(0x1F, 0x55) ++#define REG_SC_BK1F_56_L _PK_L_(0x1F, 0x56) ++#define REG_SC_BK1F_56_H _PK_H_(0x1F, 0x56) ++#define REG_SC_BK1F_57_L _PK_L_(0x1F, 0x57) ++#define REG_SC_BK1F_57_H _PK_H_(0x1F, 0x57) ++#define REG_SC_BK1F_58_L _PK_L_(0x1F, 0x58) ++#define REG_SC_BK1F_58_H _PK_H_(0x1F, 0x58) ++#define REG_SC_BK1F_59_L _PK_L_(0x1F, 0x59) ++#define REG_SC_BK1F_59_H _PK_H_(0x1F, 0x59) ++#define REG_SC_BK1F_5A_L _PK_L_(0x1F, 0x5A) ++#define REG_SC_BK1F_5A_H _PK_H_(0x1F, 0x5A) ++#define REG_SC_BK1F_5B_L _PK_L_(0x1F, 0x5B) ++#define REG_SC_BK1F_5B_H _PK_H_(0x1F, 0x5B) ++#define REG_SC_BK1F_5C_L _PK_L_(0x1F, 0x5C) ++#define REG_SC_BK1F_5C_H _PK_H_(0x1F, 0x5C) ++#define REG_SC_BK1F_5D_L _PK_L_(0x1F, 0x5D) ++#define REG_SC_BK1F_5D_H _PK_H_(0x1F, 0x5D) ++#define REG_SC_BK1F_5E_L _PK_L_(0x1F, 0x5E) ++#define REG_SC_BK1F_5E_H _PK_H_(0x1F, 0x5E) ++#define REG_SC_BK1F_5F_L _PK_L_(0x1F, 0x5F) ++#define REG_SC_BK1F_5F_H _PK_H_(0x1F, 0x5F) ++#define REG_SC_BK1F_60_L _PK_L_(0x1F, 0x60) ++#define REG_SC_BK1F_60_H _PK_H_(0x1F, 0x60) ++#define REG_SC_BK1F_61_L _PK_L_(0x1F, 0x61) ++#define REG_SC_BK1F_61_H _PK_H_(0x1F, 0x61) ++#define REG_SC_BK1F_62_L _PK_L_(0x1F, 0x62) ++#define REG_SC_BK1F_62_H _PK_H_(0x1F, 0x62) ++#define REG_SC_BK1F_63_L _PK_L_(0x1F, 0x63) ++#define REG_SC_BK1F_63_H _PK_H_(0x1F, 0x63) ++#define REG_SC_BK1F_64_L _PK_L_(0x1F, 0x64) ++#define REG_SC_BK1F_64_H _PK_H_(0x1F, 0x64) ++#define REG_SC_BK1F_65_L _PK_L_(0x1F, 0x65) ++#define REG_SC_BK1F_65_H _PK_H_(0x1F, 0x65) ++#define REG_SC_BK1F_66_L _PK_L_(0x1F, 0x66) ++#define REG_SC_BK1F_66_H _PK_H_(0x1F, 0x66) ++#define REG_SC_BK1F_67_L _PK_L_(0x1F, 0x67) ++#define REG_SC_BK1F_67_H _PK_H_(0x1F, 0x67) ++#define REG_SC_BK1F_68_L _PK_L_(0x1F, 0x68) ++#define REG_SC_BK1F_68_H _PK_H_(0x1F, 0x68) ++#define REG_SC_BK1F_69_L _PK_L_(0x1F, 0x69) ++#define REG_SC_BK1F_69_H _PK_H_(0x1F, 0x69) ++#define REG_SC_BK1F_6A_L _PK_L_(0x1F, 0x6A) ++#define REG_SC_BK1F_6A_H _PK_H_(0x1F, 0x6A) ++#define REG_SC_BK1F_6B_L _PK_L_(0x1F, 0x6B) ++#define REG_SC_BK1F_6B_H _PK_H_(0x1F, 0x6B) ++#define REG_SC_BK1F_6C_L _PK_L_(0x1F, 0x6C) ++#define REG_SC_BK1F_6C_H _PK_H_(0x1F, 0x6C) ++#define REG_SC_BK1F_6D_L _PK_L_(0x1F, 0x6D) ++#define REG_SC_BK1F_6D_H _PK_H_(0x1F, 0x6D) ++#define REG_SC_BK1F_6E_L _PK_L_(0x1F, 0x6E) ++#define REG_SC_BK1F_6E_H _PK_H_(0x1F, 0x6E) ++#define REG_SC_BK1F_6F_L _PK_L_(0x1F, 0x6F) ++#define REG_SC_BK1F_6F_H _PK_H_(0x1F, 0x6F) ++#define REG_SC_BK1F_70_L _PK_L_(0x1F, 0x70) ++#define REG_SC_BK1F_70_H _PK_H_(0x1F, 0x70) ++#define REG_SC_BK1F_71_L _PK_L_(0x1F, 0x71) ++#define REG_SC_BK1F_71_H _PK_H_(0x1F, 0x71) ++#define REG_SC_BK1F_72_L _PK_L_(0x1F, 0x72) ++#define REG_SC_BK1F_72_H _PK_H_(0x1F, 0x72) ++#define REG_SC_BK1F_73_L _PK_L_(0x1F, 0x73) ++#define REG_SC_BK1F_73_H _PK_H_(0x1F, 0x73) ++#define REG_SC_BK1F_74_L _PK_L_(0x1F, 0x74) ++#define REG_SC_BK1F_74_H _PK_H_(0x1F, 0x74) ++#define REG_SC_BK1F_75_L _PK_L_(0x1F, 0x75) ++#define REG_SC_BK1F_75_H _PK_H_(0x1F, 0x75) ++#define REG_SC_BK1F_76_L _PK_L_(0x1F, 0x76) ++#define REG_SC_BK1F_76_H _PK_H_(0x1F, 0x76) ++#define REG_SC_BK1F_77_L _PK_L_(0x1F, 0x77) ++#define REG_SC_BK1F_77_H _PK_H_(0x1F, 0x77) ++#define REG_SC_BK1F_78_L _PK_L_(0x1F, 0x78) ++#define REG_SC_BK1F_78_H _PK_H_(0x1F, 0x78) ++#define REG_SC_BK1F_79_L _PK_L_(0x1F, 0x79) ++#define REG_SC_BK1F_79_H _PK_H_(0x1F, 0x79) ++#define REG_SC_BK1F_7A_L _PK_L_(0x1F, 0x7A) ++#define REG_SC_BK1F_7A_H _PK_H_(0x1F, 0x7A) ++#define REG_SC_BK1F_7B_L _PK_L_(0x1F, 0x7B) ++#define REG_SC_BK1F_7B_H _PK_H_(0x1F, 0x7B) ++#define REG_SC_BK1F_7C_L _PK_L_(0x1F, 0x7C) ++#define REG_SC_BK1F_7C_H _PK_H_(0x1F, 0x7C) ++#define REG_SC_BK1F_7D_L _PK_L_(0x1F, 0x7D) ++#define REG_SC_BK1F_7D_H _PK_H_(0x1F, 0x7D) ++#define REG_SC_BK1F_7E_L _PK_L_(0x1F, 0x7E) ++#define REG_SC_BK1F_7E_H _PK_H_(0x1F, 0x7E) ++#define REG_SC_BK1F_7F_L _PK_L_(0x1F, 0x7F) ++#define REG_SC_BK1F_7F_H _PK_H_(0x1F, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK20_00_L _PK_L_(0x20, 0x00) ++#define REG_SC_BK20_00_H _PK_H_(0x20, 0x00) ++#define REG_SC_BK20_01_L _PK_L_(0x20, 0x01) ++#define REG_SC_BK20_01_H _PK_H_(0x20, 0x01) ++#define REG_SC_BK20_02_L _PK_L_(0x20, 0x02) ++#define REG_SC_BK20_02_H _PK_H_(0x20, 0x02) ++#define REG_SC_BK20_03_L _PK_L_(0x20, 0x03) ++#define REG_SC_BK20_03_H _PK_H_(0x20, 0x03) ++#define REG_SC_BK20_04_L _PK_L_(0x20, 0x04) ++#define REG_SC_BK20_04_H _PK_H_(0x20, 0x04) ++#define REG_SC_BK20_05_L _PK_L_(0x20, 0x05) ++#define REG_SC_BK20_05_H _PK_H_(0x20, 0x05) ++#define REG_SC_BK20_06_L _PK_L_(0x20, 0x06) ++#define REG_SC_BK20_06_H _PK_H_(0x20, 0x06) ++#define REG_SC_BK20_07_L _PK_L_(0x20, 0x07) ++#define REG_SC_BK20_07_H _PK_H_(0x20, 0x07) ++#define REG_SC_BK20_08_L _PK_L_(0x20, 0x08) ++#define REG_SC_BK20_08_H _PK_H_(0x20, 0x08) ++#define REG_SC_BK20_09_L _PK_L_(0x20, 0x09) ++#define REG_SC_BK20_09_H _PK_H_(0x20, 0x09) ++#define REG_SC_BK20_0A_L _PK_L_(0x20, 0x0A) ++#define REG_SC_BK20_0A_H _PK_H_(0x20, 0x0A) ++#define REG_SC_BK20_0B_L _PK_L_(0x20, 0x0B) ++#define REG_SC_BK20_0B_H _PK_H_(0x20, 0x0B) ++#define REG_SC_BK20_0C_L _PK_L_(0x20, 0x0C) ++#define REG_SC_BK20_0C_H _PK_H_(0x20, 0x0C) ++#define REG_SC_BK20_0D_L _PK_L_(0x20, 0x0D) ++#define REG_SC_BK20_0D_H _PK_H_(0x20, 0x0D) ++#define REG_SC_BK20_0E_L _PK_L_(0x20, 0x0E) ++#define REG_SC_BK20_0E_H _PK_H_(0x20, 0x0E) ++#define REG_SC_BK20_0F_L _PK_L_(0x20, 0x0F) ++#define REG_SC_BK20_0F_H _PK_H_(0x20, 0x0F) ++#define REG_SC_BK20_10_L _PK_L_(0x20, 0x10) ++#define REG_SC_BK20_10_H _PK_H_(0x20, 0x10) ++#define REG_SC_BK20_11_L _PK_L_(0x20, 0x11) ++#define REG_SC_BK20_11_H _PK_H_(0x20, 0x11) ++#define REG_SC_BK20_12_L _PK_L_(0x20, 0x12) ++#define REG_SC_BK20_12_H _PK_H_(0x20, 0x12) ++#define REG_SC_BK20_13_L _PK_L_(0x20, 0x13) ++#define REG_SC_BK20_13_H _PK_H_(0x20, 0x13) ++#define REG_SC_BK20_14_L _PK_L_(0x20, 0x14) ++#define REG_SC_BK20_14_H _PK_H_(0x20, 0x14) ++#define REG_SC_BK20_15_L _PK_L_(0x20, 0x15) ++#define REG_SC_BK20_15_H _PK_H_(0x20, 0x15) ++#define REG_SC_BK20_16_L _PK_L_(0x20, 0x16) ++#define REG_SC_BK20_16_H _PK_H_(0x20, 0x16) ++#define REG_SC_BK20_17_L _PK_L_(0x20, 0x17) ++#define REG_SC_BK20_17_H _PK_H_(0x20, 0x17) ++#define REG_SC_BK20_18_L _PK_L_(0x20, 0x18) ++#define REG_SC_BK20_18_H _PK_H_(0x20, 0x18) ++#define REG_SC_BK20_19_L _PK_L_(0x20, 0x19) ++#define REG_SC_BK20_19_H _PK_H_(0x20, 0x19) ++#define REG_SC_BK20_1A_L _PK_L_(0x20, 0x1A) ++#define REG_SC_BK20_1A_H _PK_H_(0x20, 0x1A) ++#define REG_SC_BK20_1B_L _PK_L_(0x20, 0x1B) ++#define REG_SC_BK20_1B_H _PK_H_(0x20, 0x1B) ++#define REG_SC_BK20_1C_L _PK_L_(0x20, 0x1C) ++#define REG_SC_BK20_1C_H _PK_H_(0x20, 0x1C) ++#define REG_SC_BK20_1D_L _PK_L_(0x20, 0x1D) ++#define REG_SC_BK20_1D_H _PK_H_(0x20, 0x1D) ++#define REG_SC_BK20_1E_L _PK_L_(0x20, 0x1E) ++#define REG_SC_BK20_1E_H _PK_H_(0x20, 0x1E) ++#define REG_SC_BK20_1F_L _PK_L_(0x20, 0x1F) ++#define REG_SC_BK20_1F_H _PK_H_(0x20, 0x1F) ++#define REG_SC_BK20_20_L _PK_L_(0x20, 0x20) ++#define REG_SC_BK20_20_H _PK_H_(0x20, 0x20) ++#define REG_SC_BK20_21_L _PK_L_(0x20, 0x21) ++#define REG_SC_BK20_21_H _PK_H_(0x20, 0x21) ++#define REG_SC_BK20_22_L _PK_L_(0x20, 0x22) ++#define REG_SC_BK20_22_H _PK_H_(0x20, 0x22) ++#define REG_SC_BK20_23_L _PK_L_(0x20, 0x23) ++#define REG_SC_BK20_23_H _PK_H_(0x20, 0x23) ++#define REG_SC_BK20_24_L _PK_L_(0x20, 0x24) ++#define REG_SC_BK20_24_H _PK_H_(0x20, 0x24) ++#define REG_SC_BK20_25_L _PK_L_(0x20, 0x25) ++#define REG_SC_BK20_25_H _PK_H_(0x20, 0x25) ++#define REG_SC_BK20_26_L _PK_L_(0x20, 0x26) ++#define REG_SC_BK20_26_H _PK_H_(0x20, 0x26) ++#define REG_SC_BK20_27_L _PK_L_(0x20, 0x27) ++#define REG_SC_BK20_27_H _PK_H_(0x20, 0x27) ++#define REG_SC_BK20_28_L _PK_L_(0x20, 0x28) ++#define REG_SC_BK20_28_H _PK_H_(0x20, 0x28) ++#define REG_SC_BK20_29_L _PK_L_(0x20, 0x29) ++#define REG_SC_BK20_29_H _PK_H_(0x20, 0x29) ++#define REG_SC_BK20_2A_L _PK_L_(0x20, 0x2A) ++#define REG_SC_BK20_2A_H _PK_H_(0x20, 0x2A) ++#define REG_SC_BK20_2B_L _PK_L_(0x20, 0x2B) ++#define REG_SC_BK20_2B_H _PK_H_(0x20, 0x2B) ++#define REG_SC_BK20_2C_L _PK_L_(0x20, 0x2C) ++#define REG_SC_BK20_2C_H _PK_H_(0x20, 0x2C) ++#define REG_SC_BK20_2D_L _PK_L_(0x20, 0x2D) ++#define REG_SC_BK20_2D_H _PK_H_(0x20, 0x2D) ++#define REG_SC_BK20_2E_L _PK_L_(0x20, 0x2E) ++#define REG_SC_BK20_2E_H _PK_H_(0x20, 0x2E) ++#define REG_SC_BK20_2F_L _PK_L_(0x20, 0x2F) ++#define REG_SC_BK20_2F_H _PK_H_(0x20, 0x2F) ++#define REG_SC_BK20_30_L _PK_L_(0x20, 0x30) ++#define REG_SC_BK20_30_H _PK_H_(0x20, 0x30) ++#define REG_SC_BK20_31_L _PK_L_(0x20, 0x31) ++#define REG_SC_BK20_31_H _PK_H_(0x20, 0x31) ++#define REG_SC_BK20_32_L _PK_L_(0x20, 0x32) ++#define REG_SC_BK20_32_H _PK_H_(0x20, 0x32) ++#define REG_SC_BK20_33_L _PK_L_(0x20, 0x33) ++#define REG_SC_BK20_33_H _PK_H_(0x20, 0x33) ++#define REG_SC_BK20_34_L _PK_L_(0x20, 0x34) ++#define REG_SC_BK20_34_H _PK_H_(0x20, 0x34) ++#define REG_SC_BK20_35_L _PK_L_(0x20, 0x35) ++#define REG_SC_BK20_35_H _PK_H_(0x20, 0x35) ++#define REG_SC_BK20_36_L _PK_L_(0x20, 0x36) ++#define REG_SC_BK20_36_H _PK_H_(0x20, 0x36) ++#define REG_SC_BK20_37_L _PK_L_(0x20, 0x37) ++#define REG_SC_BK20_37_H _PK_H_(0x20, 0x37) ++#define REG_SC_BK20_38_L _PK_L_(0x20, 0x38) ++#define REG_SC_BK20_38_H _PK_H_(0x20, 0x38) ++#define REG_SC_BK20_39_L _PK_L_(0x20, 0x39) ++#define REG_SC_BK20_39_H _PK_H_(0x20, 0x39) ++#define REG_SC_BK20_3A_L _PK_L_(0x20, 0x3A) ++#define REG_SC_BK20_3A_H _PK_H_(0x20, 0x3A) ++#define REG_SC_BK20_3B_L _PK_L_(0x20, 0x3B) ++#define REG_SC_BK20_3B_H _PK_H_(0x20, 0x3B) ++#define REG_SC_BK20_3C_L _PK_L_(0x20, 0x3C) ++#define REG_SC_BK20_3C_H _PK_H_(0x20, 0x3C) ++#define REG_SC_BK20_3D_L _PK_L_(0x20, 0x3D) ++#define REG_SC_BK20_3D_H _PK_H_(0x20, 0x3D) ++#define REG_SC_BK20_3E_L _PK_L_(0x20, 0x3E) ++#define REG_SC_BK20_3E_H _PK_H_(0x20, 0x3E) ++#define REG_SC_BK20_3F_L _PK_L_(0x20, 0x3F) ++#define REG_SC_BK20_3F_H _PK_H_(0x20, 0x3F) ++#define REG_SC_BK20_40_L _PK_L_(0x20, 0x40) ++#define REG_SC_BK20_40_H _PK_H_(0x20, 0x40) ++#define REG_SC_BK20_41_L _PK_L_(0x20, 0x41) ++#define REG_SC_BK20_41_H _PK_H_(0x20, 0x41) ++#define REG_SC_BK20_42_L _PK_L_(0x20, 0x42) ++#define REG_SC_BK20_42_H _PK_H_(0x20, 0x42) ++#define REG_SC_BK20_43_L _PK_L_(0x20, 0x43) ++#define REG_SC_BK20_43_H _PK_H_(0x20, 0x43) ++#define REG_SC_BK20_44_L _PK_L_(0x20, 0x44) ++#define REG_SC_BK20_44_H _PK_H_(0x20, 0x44) ++#define REG_SC_BK20_45_L _PK_L_(0x20, 0x45) ++#define REG_SC_BK20_45_H _PK_H_(0x20, 0x45) ++#define REG_SC_BK20_46_L _PK_L_(0x20, 0x46) ++#define REG_SC_BK20_46_H _PK_H_(0x20, 0x46) ++#define REG_SC_BK20_47_L _PK_L_(0x20, 0x47) ++#define REG_SC_BK20_47_H _PK_H_(0x20, 0x47) ++#define REG_SC_BK20_48_L _PK_L_(0x20, 0x48) ++#define REG_SC_BK20_48_H _PK_H_(0x20, 0x48) ++#define REG_SC_BK20_49_L _PK_L_(0x20, 0x49) ++#define REG_SC_BK20_49_H _PK_H_(0x20, 0x49) ++#define REG_SC_BK20_4A_L _PK_L_(0x20, 0x4A) ++#define REG_SC_BK20_4A_H _PK_H_(0x20, 0x4A) ++#define REG_SC_BK20_4B_L _PK_L_(0x20, 0x4B) ++#define REG_SC_BK20_4B_H _PK_H_(0x20, 0x4B) ++#define REG_SC_BK20_4C_L _PK_L_(0x20, 0x4C) ++#define REG_SC_BK20_4C_H _PK_H_(0x20, 0x4C) ++#define REG_SC_BK20_4D_L _PK_L_(0x20, 0x4D) ++#define REG_SC_BK20_4D_H _PK_H_(0x20, 0x4D) ++#define REG_SC_BK20_4E_L _PK_L_(0x20, 0x4E) ++#define REG_SC_BK20_4E_H _PK_H_(0x20, 0x4E) ++#define REG_SC_BK20_4F_L _PK_L_(0x20, 0x4F) ++#define REG_SC_BK20_4F_H _PK_H_(0x20, 0x4F) ++#define REG_SC_BK20_50_L _PK_L_(0x20, 0x50) ++#define REG_SC_BK20_50_H _PK_H_(0x20, 0x50) ++#define REG_SC_BK20_51_L _PK_L_(0x20, 0x51) ++#define REG_SC_BK20_51_H _PK_H_(0x20, 0x51) ++#define REG_SC_BK20_52_L _PK_L_(0x20, 0x52) ++#define REG_SC_BK20_52_H _PK_H_(0x20, 0x52) ++#define REG_SC_BK20_53_L _PK_L_(0x20, 0x53) ++#define REG_SC_BK20_53_H _PK_H_(0x20, 0x53) ++#define REG_SC_BK20_54_L _PK_L_(0x20, 0x54) ++#define REG_SC_BK20_54_H _PK_H_(0x20, 0x54) ++#define REG_SC_BK20_55_L _PK_L_(0x20, 0x55) ++#define REG_SC_BK20_55_H _PK_H_(0x20, 0x55) ++#define REG_SC_BK20_56_L _PK_L_(0x20, 0x56) ++#define REG_SC_BK20_56_H _PK_H_(0x20, 0x56) ++#define REG_SC_BK20_57_L _PK_L_(0x20, 0x57) ++#define REG_SC_BK20_57_H _PK_H_(0x20, 0x57) ++#define REG_SC_BK20_58_L _PK_L_(0x20, 0x58) ++#define REG_SC_BK20_58_H _PK_H_(0x20, 0x58) ++#define REG_SC_BK20_59_L _PK_L_(0x20, 0x59) ++#define REG_SC_BK20_59_H _PK_H_(0x20, 0x59) ++#define REG_SC_BK20_5A_L _PK_L_(0x20, 0x5A) ++#define REG_SC_BK20_5A_H _PK_H_(0x20, 0x5A) ++#define REG_SC_BK20_5B_L _PK_L_(0x20, 0x5B) ++#define REG_SC_BK20_5B_H _PK_H_(0x20, 0x5B) ++#define REG_SC_BK20_5C_L _PK_L_(0x20, 0x5C) ++#define REG_SC_BK20_5C_H _PK_H_(0x20, 0x5C) ++#define REG_SC_BK20_5D_L _PK_L_(0x20, 0x5D) ++#define REG_SC_BK20_5D_H _PK_H_(0x20, 0x5D) ++#define REG_SC_BK20_5E_L _PK_L_(0x20, 0x5E) ++#define REG_SC_BK20_5E_H _PK_H_(0x20, 0x5E) ++#define REG_SC_BK20_5F_L _PK_L_(0x20, 0x5F) ++#define REG_SC_BK20_5F_H _PK_H_(0x20, 0x5F) ++#define REG_SC_BK20_60_L _PK_L_(0x20, 0x60) ++#define REG_SC_BK20_60_H _PK_H_(0x20, 0x60) ++#define REG_SC_BK20_61_L _PK_L_(0x20, 0x61) ++#define REG_SC_BK20_61_H _PK_H_(0x20, 0x61) ++#define REG_SC_BK20_62_L _PK_L_(0x20, 0x62) ++#define REG_SC_BK20_62_H _PK_H_(0x20, 0x62) ++#define REG_SC_BK20_63_L _PK_L_(0x20, 0x63) ++#define REG_SC_BK20_63_H _PK_H_(0x20, 0x63) ++#define REG_SC_BK20_64_L _PK_L_(0x20, 0x64) ++#define REG_SC_BK20_64_H _PK_H_(0x20, 0x64) ++#define REG_SC_BK20_65_L _PK_L_(0x20, 0x65) ++#define REG_SC_BK20_65_H _PK_H_(0x20, 0x65) ++#define REG_SC_BK20_66_L _PK_L_(0x20, 0x66) ++#define REG_SC_BK20_66_H _PK_H_(0x20, 0x66) ++#define REG_SC_BK20_67_L _PK_L_(0x20, 0x67) ++#define REG_SC_BK20_67_H _PK_H_(0x20, 0x67) ++#define REG_SC_BK20_68_L _PK_L_(0x20, 0x68) ++#define REG_SC_BK20_68_H _PK_H_(0x20, 0x68) ++#define REG_SC_BK20_69_L _PK_L_(0x20, 0x69) ++#define REG_SC_BK20_69_H _PK_H_(0x20, 0x69) ++#define REG_SC_BK20_6A_L _PK_L_(0x20, 0x6A) ++#define REG_SC_BK20_6A_H _PK_H_(0x20, 0x6A) ++#define REG_SC_BK20_6B_L _PK_L_(0x20, 0x6B) ++#define REG_SC_BK20_6B_H _PK_H_(0x20, 0x6B) ++#define REG_SC_BK20_6C_L _PK_L_(0x20, 0x6C) ++#define REG_SC_BK20_6C_H _PK_H_(0x20, 0x6C) ++#define REG_SC_BK20_6D_L _PK_L_(0x20, 0x6D) ++#define REG_SC_BK20_6D_H _PK_H_(0x20, 0x6D) ++#define REG_SC_BK20_6E_L _PK_L_(0x20, 0x6E) ++#define REG_SC_BK20_6E_H _PK_H_(0x20, 0x6E) ++#define REG_SC_BK20_6F_L _PK_L_(0x20, 0x6F) ++#define REG_SC_BK20_6F_H _PK_H_(0x20, 0x6F) ++#define REG_SC_BK20_70_L _PK_L_(0x20, 0x70) ++#define REG_SC_BK20_70_H _PK_H_(0x20, 0x70) ++#define REG_SC_BK20_71_L _PK_L_(0x20, 0x71) ++#define REG_SC_BK20_71_H _PK_H_(0x20, 0x71) ++#define REG_SC_BK20_72_L _PK_L_(0x20, 0x72) ++#define REG_SC_BK20_72_H _PK_H_(0x20, 0x72) ++#define REG_SC_BK20_73_L _PK_L_(0x20, 0x73) ++#define REG_SC_BK20_73_H _PK_H_(0x20, 0x73) ++#define REG_SC_BK20_74_L _PK_L_(0x20, 0x74) ++#define REG_SC_BK20_74_H _PK_H_(0x20, 0x74) ++#define REG_SC_BK20_75_L _PK_L_(0x20, 0x75) ++#define REG_SC_BK20_75_H _PK_H_(0x20, 0x75) ++#define REG_SC_BK20_76_L _PK_L_(0x20, 0x76) ++#define REG_SC_BK20_76_H _PK_H_(0x20, 0x76) ++#define REG_SC_BK20_77_L _PK_L_(0x20, 0x77) ++#define REG_SC_BK20_77_H _PK_H_(0x20, 0x77) ++#define REG_SC_BK20_78_L _PK_L_(0x20, 0x78) ++#define REG_SC_BK20_78_H _PK_H_(0x20, 0x78) ++#define REG_SC_BK20_79_L _PK_L_(0x20, 0x79) ++#define REG_SC_BK20_79_H _PK_H_(0x20, 0x79) ++#define REG_SC_BK20_7A_L _PK_L_(0x20, 0x7A) ++#define REG_SC_BK20_7A_H _PK_H_(0x20, 0x7A) ++#define REG_SC_BK20_7B_L _PK_L_(0x20, 0x7B) ++#define REG_SC_BK20_7B_H _PK_H_(0x20, 0x7B) ++#define REG_SC_BK20_7C_L _PK_L_(0x20, 0x7C) ++#define REG_SC_BK20_7C_H _PK_H_(0x20, 0x7C) ++#define REG_SC_BK20_7D_L _PK_L_(0x20, 0x7D) ++#define REG_SC_BK20_7D_H _PK_H_(0x20, 0x7D) ++#define REG_SC_BK20_7E_L _PK_L_(0x20, 0x7E) ++#define REG_SC_BK20_7E_H _PK_H_(0x20, 0x7E) ++#define REG_SC_BK20_7F_L _PK_L_(0x20, 0x7F) ++#define REG_SC_BK20_7F_H _PK_H_(0x20, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK21_00_L _PK_L_(0x21, 0x00) ++#define REG_SC_BK21_00_H _PK_H_(0x21, 0x00) ++#define REG_SC_BK21_01_L _PK_L_(0x21, 0x01) ++#define REG_SC_BK21_01_H _PK_H_(0x21, 0x01) ++#define REG_SC_BK21_02_L _PK_L_(0x21, 0x02) ++#define REG_SC_BK21_02_H _PK_H_(0x21, 0x02) ++#define REG_SC_BK21_03_L _PK_L_(0x21, 0x03) ++#define REG_SC_BK21_03_H _PK_H_(0x21, 0x03) ++#define REG_SC_BK21_04_L _PK_L_(0x21, 0x04) ++#define REG_SC_BK21_04_H _PK_H_(0x21, 0x04) ++#define REG_SC_BK21_05_L _PK_L_(0x21, 0x05) ++#define REG_SC_BK21_05_H _PK_H_(0x21, 0x05) ++#define REG_SC_BK21_06_L _PK_L_(0x21, 0x06) ++#define REG_SC_BK21_06_H _PK_H_(0x21, 0x06) ++#define REG_SC_BK21_07_L _PK_L_(0x21, 0x07) ++#define REG_SC_BK21_07_H _PK_H_(0x21, 0x07) ++#define REG_SC_BK21_08_L _PK_L_(0x21, 0x08) ++#define REG_SC_BK21_08_H _PK_H_(0x21, 0x08) ++#define REG_SC_BK21_09_L _PK_L_(0x21, 0x09) ++#define REG_SC_BK21_09_H _PK_H_(0x21, 0x09) ++#define REG_SC_BK21_0A_L _PK_L_(0x21, 0x0A) ++#define REG_SC_BK21_0A_H _PK_H_(0x21, 0x0A) ++#define REG_SC_BK21_0B_L _PK_L_(0x21, 0x0B) ++#define REG_SC_BK21_0B_H _PK_H_(0x21, 0x0B) ++#define REG_SC_BK21_0C_L _PK_L_(0x21, 0x0C) ++#define REG_SC_BK21_0C_H _PK_H_(0x21, 0x0C) ++#define REG_SC_BK21_0D_L _PK_L_(0x21, 0x0D) ++#define REG_SC_BK21_0D_H _PK_H_(0x21, 0x0D) ++#define REG_SC_BK21_0E_L _PK_L_(0x21, 0x0E) ++#define REG_SC_BK21_0E_H _PK_H_(0x21, 0x0E) ++#define REG_SC_BK21_0F_L _PK_L_(0x21, 0x0F) ++#define REG_SC_BK21_0F_H _PK_H_(0x21, 0x0F) ++#define REG_SC_BK21_10_L _PK_L_(0x21, 0x10) ++#define REG_SC_BK21_10_H _PK_H_(0x21, 0x10) ++#define REG_SC_BK21_11_L _PK_L_(0x21, 0x11) ++#define REG_SC_BK21_11_H _PK_H_(0x21, 0x11) ++#define REG_SC_BK21_12_L _PK_L_(0x21, 0x12) ++#define REG_SC_BK21_12_H _PK_H_(0x21, 0x12) ++#define REG_SC_BK21_13_L _PK_L_(0x21, 0x13) ++#define REG_SC_BK21_13_H _PK_H_(0x21, 0x13) ++#define REG_SC_BK21_14_L _PK_L_(0x21, 0x14) ++#define REG_SC_BK21_14_H _PK_H_(0x21, 0x14) ++#define REG_SC_BK21_15_L _PK_L_(0x21, 0x15) ++#define REG_SC_BK21_15_H _PK_H_(0x21, 0x15) ++#define REG_SC_BK21_16_L _PK_L_(0x21, 0x16) ++#define REG_SC_BK21_16_H _PK_H_(0x21, 0x16) ++#define REG_SC_BK21_17_L _PK_L_(0x21, 0x17) ++#define REG_SC_BK21_17_H _PK_H_(0x21, 0x17) ++#define REG_SC_BK21_18_L _PK_L_(0x21, 0x18) ++#define REG_SC_BK21_18_H _PK_H_(0x21, 0x18) ++#define REG_SC_BK21_19_L _PK_L_(0x21, 0x19) ++#define REG_SC_BK21_19_H _PK_H_(0x21, 0x19) ++#define REG_SC_BK21_1A_L _PK_L_(0x21, 0x1A) ++#define REG_SC_BK21_1A_H _PK_H_(0x21, 0x1A) ++#define REG_SC_BK21_1B_L _PK_L_(0x21, 0x1B) ++#define REG_SC_BK21_1B_H _PK_H_(0x21, 0x1B) ++#define REG_SC_BK21_1C_L _PK_L_(0x21, 0x1C) ++#define REG_SC_BK21_1C_H _PK_H_(0x21, 0x1C) ++#define REG_SC_BK21_1D_L _PK_L_(0x21, 0x1D) ++#define REG_SC_BK21_1D_H _PK_H_(0x21, 0x1D) ++#define REG_SC_BK21_1E_L _PK_L_(0x21, 0x1E) ++#define REG_SC_BK21_1E_H _PK_H_(0x21, 0x1E) ++#define REG_SC_BK21_1F_L _PK_L_(0x21, 0x1F) ++#define REG_SC_BK21_1F_H _PK_H_(0x21, 0x1F) ++#define REG_SC_BK21_20_L _PK_L_(0x21, 0x20) ++#define REG_SC_BK21_20_H _PK_H_(0x21, 0x20) ++#define REG_SC_BK21_21_L _PK_L_(0x21, 0x21) ++#define REG_SC_BK21_21_H _PK_H_(0x21, 0x21) ++#define REG_SC_BK21_22_L _PK_L_(0x21, 0x22) ++#define REG_SC_BK21_22_H _PK_H_(0x21, 0x22) ++#define REG_SC_BK21_23_L _PK_L_(0x21, 0x23) ++#define REG_SC_BK21_23_H _PK_H_(0x21, 0x23) ++#define REG_SC_BK21_24_L _PK_L_(0x21, 0x24) ++#define REG_SC_BK21_24_H _PK_H_(0x21, 0x24) ++#define REG_SC_BK21_25_L _PK_L_(0x21, 0x25) ++#define REG_SC_BK21_25_H _PK_H_(0x21, 0x25) ++#define REG_SC_BK21_26_L _PK_L_(0x21, 0x26) ++#define REG_SC_BK21_26_H _PK_H_(0x21, 0x26) ++#define REG_SC_BK21_27_L _PK_L_(0x21, 0x27) ++#define REG_SC_BK21_27_H _PK_H_(0x21, 0x27) ++#define REG_SC_BK21_28_L _PK_L_(0x21, 0x28) ++#define REG_SC_BK21_28_H _PK_H_(0x21, 0x28) ++#define REG_SC_BK21_29_L _PK_L_(0x21, 0x29) ++#define REG_SC_BK21_29_H _PK_H_(0x21, 0x29) ++#define REG_SC_BK21_2A_L _PK_L_(0x21, 0x2A) ++#define REG_SC_BK21_2A_H _PK_H_(0x21, 0x2A) ++#define REG_SC_BK21_2B_L _PK_L_(0x21, 0x2B) ++#define REG_SC_BK21_2B_H _PK_H_(0x21, 0x2B) ++#define REG_SC_BK21_2C_L _PK_L_(0x21, 0x2C) ++#define REG_SC_BK21_2C_H _PK_H_(0x21, 0x2C) ++#define REG_SC_BK21_2D_L _PK_L_(0x21, 0x2D) ++#define REG_SC_BK21_2D_H _PK_H_(0x21, 0x2D) ++#define REG_SC_BK21_2E_L _PK_L_(0x21, 0x2E) ++#define REG_SC_BK21_2E_H _PK_H_(0x21, 0x2E) ++#define REG_SC_BK21_2F_L _PK_L_(0x21, 0x2F) ++#define REG_SC_BK21_2F_H _PK_H_(0x21, 0x2F) ++#define REG_SC_BK21_30_L _PK_L_(0x21, 0x30) ++#define REG_SC_BK21_30_H _PK_H_(0x21, 0x30) ++#define REG_SC_BK21_31_L _PK_L_(0x21, 0x31) ++#define REG_SC_BK21_31_H _PK_H_(0x21, 0x31) ++#define REG_SC_BK21_32_L _PK_L_(0x21, 0x32) ++#define REG_SC_BK21_32_H _PK_H_(0x21, 0x32) ++#define REG_SC_BK21_33_L _PK_L_(0x21, 0x33) ++#define REG_SC_BK21_33_H _PK_H_(0x21, 0x33) ++#define REG_SC_BK21_34_L _PK_L_(0x21, 0x34) ++#define REG_SC_BK21_34_H _PK_H_(0x21, 0x34) ++#define REG_SC_BK21_35_L _PK_L_(0x21, 0x35) ++#define REG_SC_BK21_35_H _PK_H_(0x21, 0x35) ++#define REG_SC_BK21_36_L _PK_L_(0x21, 0x36) ++#define REG_SC_BK21_36_H _PK_H_(0x21, 0x36) ++#define REG_SC_BK21_37_L _PK_L_(0x21, 0x37) ++#define REG_SC_BK21_37_H _PK_H_(0x21, 0x37) ++#define REG_SC_BK21_38_L _PK_L_(0x21, 0x38) ++#define REG_SC_BK21_38_H _PK_H_(0x21, 0x38) ++#define REG_SC_BK21_39_L _PK_L_(0x21, 0x39) ++#define REG_SC_BK21_39_H _PK_H_(0x21, 0x39) ++#define REG_SC_BK21_3A_L _PK_L_(0x21, 0x3A) ++#define REG_SC_BK21_3A_H _PK_H_(0x21, 0x3A) ++#define REG_SC_BK21_3B_L _PK_L_(0x21, 0x3B) ++#define REG_SC_BK21_3B_H _PK_H_(0x21, 0x3B) ++#define REG_SC_BK21_3C_L _PK_L_(0x21, 0x3C) ++#define REG_SC_BK21_3C_H _PK_H_(0x21, 0x3C) ++#define REG_SC_BK21_3D_L _PK_L_(0x21, 0x3D) ++#define REG_SC_BK21_3D_H _PK_H_(0x21, 0x3D) ++#define REG_SC_BK21_3E_L _PK_L_(0x21, 0x3E) ++#define REG_SC_BK21_3E_H _PK_H_(0x21, 0x3E) ++#define REG_SC_BK21_3F_L _PK_L_(0x21, 0x3F) ++#define REG_SC_BK21_3F_H _PK_H_(0x21, 0x3F) ++#define REG_SC_BK21_40_L _PK_L_(0x21, 0x40) ++#define REG_SC_BK21_40_H _PK_H_(0x21, 0x40) ++#define REG_SC_BK21_41_L _PK_L_(0x21, 0x41) ++#define REG_SC_BK21_41_H _PK_H_(0x21, 0x41) ++#define REG_SC_BK21_42_L _PK_L_(0x21, 0x42) ++#define REG_SC_BK21_42_H _PK_H_(0x21, 0x42) ++#define REG_SC_BK21_43_L _PK_L_(0x21, 0x43) ++#define REG_SC_BK21_43_H _PK_H_(0x21, 0x43) ++#define REG_SC_BK21_44_L _PK_L_(0x21, 0x44) ++#define REG_SC_BK21_44_H _PK_H_(0x21, 0x44) ++#define REG_SC_BK21_45_L _PK_L_(0x21, 0x45) ++#define REG_SC_BK21_45_H _PK_H_(0x21, 0x45) ++#define REG_SC_BK21_46_L _PK_L_(0x21, 0x46) ++#define REG_SC_BK21_46_H _PK_H_(0x21, 0x46) ++#define REG_SC_BK21_47_L _PK_L_(0x21, 0x47) ++#define REG_SC_BK21_47_H _PK_H_(0x21, 0x47) ++#define REG_SC_BK21_48_L _PK_L_(0x21, 0x48) ++#define REG_SC_BK21_48_H _PK_H_(0x21, 0x48) ++#define REG_SC_BK21_49_L _PK_L_(0x21, 0x49) ++#define REG_SC_BK21_49_H _PK_H_(0x21, 0x49) ++#define REG_SC_BK21_4A_L _PK_L_(0x21, 0x4A) ++#define REG_SC_BK21_4A_H _PK_H_(0x21, 0x4A) ++#define REG_SC_BK21_4B_L _PK_L_(0x21, 0x4B) ++#define REG_SC_BK21_4B_H _PK_H_(0x21, 0x4B) ++#define REG_SC_BK21_4C_L _PK_L_(0x21, 0x4C) ++#define REG_SC_BK21_4C_H _PK_H_(0x21, 0x4C) ++#define REG_SC_BK21_4D_L _PK_L_(0x21, 0x4D) ++#define REG_SC_BK21_4D_H _PK_H_(0x21, 0x4D) ++#define REG_SC_BK21_4E_L _PK_L_(0x21, 0x4E) ++#define REG_SC_BK21_4E_H _PK_H_(0x21, 0x4E) ++#define REG_SC_BK21_4F_L _PK_L_(0x21, 0x4F) ++#define REG_SC_BK21_4F_H _PK_H_(0x21, 0x4F) ++#define REG_SC_BK21_50_L _PK_L_(0x21, 0x50) ++#define REG_SC_BK21_50_H _PK_H_(0x21, 0x50) ++#define REG_SC_BK21_51_L _PK_L_(0x21, 0x51) ++#define REG_SC_BK21_51_H _PK_H_(0x21, 0x51) ++#define REG_SC_BK21_52_L _PK_L_(0x21, 0x52) ++#define REG_SC_BK21_52_H _PK_H_(0x21, 0x52) ++#define REG_SC_BK21_53_L _PK_L_(0x21, 0x53) ++#define REG_SC_BK21_53_H _PK_H_(0x21, 0x53) ++#define REG_SC_BK21_54_L _PK_L_(0x21, 0x54) ++#define REG_SC_BK21_54_H _PK_H_(0x21, 0x54) ++#define REG_SC_BK21_55_L _PK_L_(0x21, 0x55) ++#define REG_SC_BK21_55_H _PK_H_(0x21, 0x55) ++#define REG_SC_BK21_56_L _PK_L_(0x21, 0x56) ++#define REG_SC_BK21_56_H _PK_H_(0x21, 0x56) ++#define REG_SC_BK21_57_L _PK_L_(0x21, 0x57) ++#define REG_SC_BK21_57_H _PK_H_(0x21, 0x57) ++#define REG_SC_BK21_58_L _PK_L_(0x21, 0x58) ++#define REG_SC_BK21_58_H _PK_H_(0x21, 0x58) ++#define REG_SC_BK21_59_L _PK_L_(0x21, 0x59) ++#define REG_SC_BK21_59_H _PK_H_(0x21, 0x59) ++#define REG_SC_BK21_5A_L _PK_L_(0x21, 0x5A) ++#define REG_SC_BK21_5A_H _PK_H_(0x21, 0x5A) ++#define REG_SC_BK21_5B_L _PK_L_(0x21, 0x5B) ++#define REG_SC_BK21_5B_H _PK_H_(0x21, 0x5B) ++#define REG_SC_BK21_5C_L _PK_L_(0x21, 0x5C) ++#define REG_SC_BK21_5C_H _PK_H_(0x21, 0x5C) ++#define REG_SC_BK21_5D_L _PK_L_(0x21, 0x5D) ++#define REG_SC_BK21_5D_H _PK_H_(0x21, 0x5D) ++#define REG_SC_BK21_5E_L _PK_L_(0x21, 0x5E) ++#define REG_SC_BK21_5E_H _PK_H_(0x21, 0x5E) ++#define REG_SC_BK21_5F_L _PK_L_(0x21, 0x5F) ++#define REG_SC_BK21_5F_H _PK_H_(0x21, 0x5F) ++#define REG_SC_BK21_60_L _PK_L_(0x21, 0x60) ++#define REG_SC_BK21_60_H _PK_H_(0x21, 0x60) ++#define REG_SC_BK21_61_L _PK_L_(0x21, 0x61) ++#define REG_SC_BK21_61_H _PK_H_(0x21, 0x61) ++#define REG_SC_BK21_62_L _PK_L_(0x21, 0x62) ++#define REG_SC_BK21_62_H _PK_H_(0x21, 0x62) ++#define REG_SC_BK21_63_L _PK_L_(0x21, 0x63) ++#define REG_SC_BK21_63_H _PK_H_(0x21, 0x63) ++#define REG_SC_BK21_64_L _PK_L_(0x21, 0x64) ++#define REG_SC_BK21_64_H _PK_H_(0x21, 0x64) ++#define REG_SC_BK21_65_L _PK_L_(0x21, 0x65) ++#define REG_SC_BK21_65_H _PK_H_(0x21, 0x65) ++#define REG_SC_BK21_66_L _PK_L_(0x21, 0x66) ++#define REG_SC_BK21_66_H _PK_H_(0x21, 0x66) ++#define REG_SC_BK21_67_L _PK_L_(0x21, 0x67) ++#define REG_SC_BK21_67_H _PK_H_(0x21, 0x67) ++#define REG_SC_BK21_68_L _PK_L_(0x21, 0x68) ++#define REG_SC_BK21_68_H _PK_H_(0x21, 0x68) ++#define REG_SC_BK21_69_L _PK_L_(0x21, 0x69) ++#define REG_SC_BK21_69_H _PK_H_(0x21, 0x69) ++#define REG_SC_BK21_6A_L _PK_L_(0x21, 0x6A) ++#define REG_SC_BK21_6A_H _PK_H_(0x21, 0x6A) ++#define REG_SC_BK21_6B_L _PK_L_(0x21, 0x6B) ++#define REG_SC_BK21_6B_H _PK_H_(0x21, 0x6B) ++#define REG_SC_BK21_6C_L _PK_L_(0x21, 0x6C) ++#define REG_SC_BK21_6C_H _PK_H_(0x21, 0x6C) ++#define REG_SC_BK21_6D_L _PK_L_(0x21, 0x6D) ++#define REG_SC_BK21_6D_H _PK_H_(0x21, 0x6D) ++#define REG_SC_BK21_6E_L _PK_L_(0x21, 0x6E) ++#define REG_SC_BK21_6E_H _PK_H_(0x21, 0x6E) ++#define REG_SC_BK21_6F_L _PK_L_(0x21, 0x6F) ++#define REG_SC_BK21_6F_H _PK_H_(0x21, 0x6F) ++#define REG_SC_BK21_70_L _PK_L_(0x21, 0x70) ++#define REG_SC_BK21_70_H _PK_H_(0x21, 0x70) ++#define REG_SC_BK21_71_L _PK_L_(0x21, 0x71) ++#define REG_SC_BK21_71_H _PK_H_(0x21, 0x71) ++#define REG_SC_BK21_72_L _PK_L_(0x21, 0x72) ++#define REG_SC_BK21_72_H _PK_H_(0x21, 0x72) ++#define REG_SC_BK21_73_L _PK_L_(0x21, 0x73) ++#define REG_SC_BK21_73_H _PK_H_(0x21, 0x73) ++#define REG_SC_BK21_74_L _PK_L_(0x21, 0x74) ++#define REG_SC_BK21_74_H _PK_H_(0x21, 0x74) ++#define REG_SC_BK21_75_L _PK_L_(0x21, 0x75) ++#define REG_SC_BK21_75_H _PK_H_(0x21, 0x75) ++#define REG_SC_BK21_76_L _PK_L_(0x21, 0x76) ++#define REG_SC_BK21_76_H _PK_H_(0x21, 0x76) ++#define REG_SC_BK21_77_L _PK_L_(0x21, 0x77) ++#define REG_SC_BK21_77_H _PK_H_(0x21, 0x77) ++#define REG_SC_BK21_78_L _PK_L_(0x21, 0x78) ++#define REG_SC_BK21_78_H _PK_H_(0x21, 0x78) ++#define REG_SC_BK21_79_L _PK_L_(0x21, 0x79) ++#define REG_SC_BK21_79_H _PK_H_(0x21, 0x79) ++#define REG_SC_BK21_7A_L _PK_L_(0x21, 0x7A) ++#define REG_SC_BK21_7A_H _PK_H_(0x21, 0x7A) ++#define REG_SC_BK21_7B_L _PK_L_(0x21, 0x7B) ++#define REG_SC_BK21_7B_H _PK_H_(0x21, 0x7B) ++#define REG_SC_BK21_7C_L _PK_L_(0x21, 0x7C) ++#define REG_SC_BK21_7C_H _PK_H_(0x21, 0x7C) ++#define REG_SC_BK21_7D_L _PK_L_(0x21, 0x7D) ++#define REG_SC_BK21_7D_H _PK_H_(0x21, 0x7D) ++#define REG_SC_BK21_7E_L _PK_L_(0x21, 0x7E) ++#define REG_SC_BK21_7E_H _PK_H_(0x21, 0x7E) ++#define REG_SC_BK21_7F_L _PK_L_(0x21, 0x7F) ++#define REG_SC_BK21_7F_H _PK_H_(0x21, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK22_00_L _PK_L_(0x22, 0x00) ++#define REG_SC_BK22_00_H _PK_H_(0x22, 0x00) ++#define REG_SC_BK22_01_L _PK_L_(0x22, 0x01) ++#define REG_SC_BK22_01_H _PK_H_(0x22, 0x01) ++#define REG_SC_BK22_02_L _PK_L_(0x22, 0x02) ++#define REG_SC_BK22_02_H _PK_H_(0x22, 0x02) ++#define REG_SC_BK22_03_L _PK_L_(0x22, 0x03) ++#define REG_SC_BK22_03_H _PK_H_(0x22, 0x03) ++#define REG_SC_BK22_04_L _PK_L_(0x22, 0x04) ++#define REG_SC_BK22_04_H _PK_H_(0x22, 0x04) ++#define REG_SC_BK22_05_L _PK_L_(0x22, 0x05) ++#define REG_SC_BK22_05_H _PK_H_(0x22, 0x05) ++#define REG_SC_BK22_06_L _PK_L_(0x22, 0x06) ++#define REG_SC_BK22_06_H _PK_H_(0x22, 0x06) ++#define REG_SC_BK22_07_L _PK_L_(0x22, 0x07) ++#define REG_SC_BK22_07_H _PK_H_(0x22, 0x07) ++#define REG_SC_BK22_08_L _PK_L_(0x22, 0x08) ++#define REG_SC_BK22_08_H _PK_H_(0x22, 0x08) ++#define REG_SC_BK22_09_L _PK_L_(0x22, 0x09) ++#define REG_SC_BK22_09_H _PK_H_(0x22, 0x09) ++#define REG_SC_BK22_0A_L _PK_L_(0x22, 0x0A) ++#define REG_SC_BK22_0A_H _PK_H_(0x22, 0x0A) ++#define REG_SC_BK22_0B_L _PK_L_(0x22, 0x0B) ++#define REG_SC_BK22_0B_H _PK_H_(0x22, 0x0B) ++#define REG_SC_BK22_0C_L _PK_L_(0x22, 0x0C) ++#define REG_SC_BK22_0C_H _PK_H_(0x22, 0x0C) ++#define REG_SC_BK22_0D_L _PK_L_(0x22, 0x0D) ++#define REG_SC_BK22_0D_H _PK_H_(0x22, 0x0D) ++#define REG_SC_BK22_0E_L _PK_L_(0x22, 0x0E) ++#define REG_SC_BK22_0E_H _PK_H_(0x22, 0x0E) ++#define REG_SC_BK22_0F_L _PK_L_(0x22, 0x0F) ++#define REG_SC_BK22_0F_H _PK_H_(0x22, 0x0F) ++#define REG_SC_BK22_10_L _PK_L_(0x22, 0x10) ++#define REG_SC_BK22_10_H _PK_H_(0x22, 0x10) ++#define REG_SC_BK22_11_L _PK_L_(0x22, 0x11) ++#define REG_SC_BK22_11_H _PK_H_(0x22, 0x11) ++#define REG_SC_BK22_12_L _PK_L_(0x22, 0x12) ++#define REG_SC_BK22_12_H _PK_H_(0x22, 0x12) ++#define REG_SC_BK22_13_L _PK_L_(0x22, 0x13) ++#define REG_SC_BK22_13_H _PK_H_(0x22, 0x13) ++#define REG_SC_BK22_14_L _PK_L_(0x22, 0x14) ++#define REG_SC_BK22_14_H _PK_H_(0x22, 0x14) ++#define REG_SC_BK22_15_L _PK_L_(0x22, 0x15) ++#define REG_SC_BK22_15_H _PK_H_(0x22, 0x15) ++#define REG_SC_BK22_16_L _PK_L_(0x22, 0x16) ++#define REG_SC_BK22_16_H _PK_H_(0x22, 0x16) ++#define REG_SC_BK22_17_L _PK_L_(0x22, 0x17) ++#define REG_SC_BK22_17_H _PK_H_(0x22, 0x17) ++#define REG_SC_BK22_18_L _PK_L_(0x22, 0x18) ++#define REG_SC_BK22_18_H _PK_H_(0x22, 0x18) ++#define REG_SC_BK22_19_L _PK_L_(0x22, 0x19) ++#define REG_SC_BK22_19_H _PK_H_(0x22, 0x19) ++#define REG_SC_BK22_1A_L _PK_L_(0x22, 0x1A) ++#define REG_SC_BK22_1A_H _PK_H_(0x22, 0x1A) ++#define REG_SC_BK22_1B_L _PK_L_(0x22, 0x1B) ++#define REG_SC_BK22_1B_H _PK_H_(0x22, 0x1B) ++#define REG_SC_BK22_1C_L _PK_L_(0x22, 0x1C) ++#define REG_SC_BK22_1C_H _PK_H_(0x22, 0x1C) ++#define REG_SC_BK22_1D_L _PK_L_(0x22, 0x1D) ++#define REG_SC_BK22_1D_H _PK_H_(0x22, 0x1D) ++#define REG_SC_BK22_1E_L _PK_L_(0x22, 0x1E) ++#define REG_SC_BK22_1E_H _PK_H_(0x22, 0x1E) ++#define REG_SC_BK22_1F_L _PK_L_(0x22, 0x1F) ++#define REG_SC_BK22_1F_H _PK_H_(0x22, 0x1F) ++#define REG_SC_BK22_20_L _PK_L_(0x22, 0x20) ++#define REG_SC_BK22_20_H _PK_H_(0x22, 0x20) ++#define REG_SC_BK22_21_L _PK_L_(0x22, 0x21) ++#define REG_SC_BK22_21_H _PK_H_(0x22, 0x21) ++#define REG_SC_BK22_22_L _PK_L_(0x22, 0x22) ++#define REG_SC_BK22_22_H _PK_H_(0x22, 0x22) ++#define REG_SC_BK22_23_L _PK_L_(0x22, 0x23) ++#define REG_SC_BK22_23_H _PK_H_(0x22, 0x23) ++#define REG_SC_BK22_24_L _PK_L_(0x22, 0x24) ++#define REG_SC_BK22_24_H _PK_H_(0x22, 0x24) ++#define REG_SC_BK22_25_L _PK_L_(0x22, 0x25) ++#define REG_SC_BK22_25_H _PK_H_(0x22, 0x25) ++#define REG_SC_BK22_26_L _PK_L_(0x22, 0x26) ++#define REG_SC_BK22_26_H _PK_H_(0x22, 0x26) ++#define REG_SC_BK22_27_L _PK_L_(0x22, 0x27) ++#define REG_SC_BK22_27_H _PK_H_(0x22, 0x27) ++#define REG_SC_BK22_28_L _PK_L_(0x22, 0x28) ++#define REG_SC_BK22_28_H _PK_H_(0x22, 0x28) ++#define REG_SC_BK22_29_L _PK_L_(0x22, 0x29) ++#define REG_SC_BK22_29_H _PK_H_(0x22, 0x29) ++#define REG_SC_BK22_2A_L _PK_L_(0x22, 0x2A) ++#define REG_SC_BK22_2A_H _PK_H_(0x22, 0x2A) ++#define REG_SC_BK22_2B_L _PK_L_(0x22, 0x2B) ++#define REG_SC_BK22_2B_H _PK_H_(0x22, 0x2B) ++#define REG_SC_BK22_2C_L _PK_L_(0x22, 0x2C) ++#define REG_SC_BK22_2C_H _PK_H_(0x22, 0x2C) ++#define REG_SC_BK22_2D_L _PK_L_(0x22, 0x2D) ++#define REG_SC_BK22_2D_H _PK_H_(0x22, 0x2D) ++#define REG_SC_BK22_2E_L _PK_L_(0x22, 0x2E) ++#define REG_SC_BK22_2E_H _PK_H_(0x22, 0x2E) ++#define REG_SC_BK22_2F_L _PK_L_(0x22, 0x2F) ++#define REG_SC_BK22_2F_H _PK_H_(0x22, 0x2F) ++#define REG_SC_BK22_30_L _PK_L_(0x22, 0x30) ++#define REG_SC_BK22_30_H _PK_H_(0x22, 0x30) ++#define REG_SC_BK22_31_L _PK_L_(0x22, 0x31) ++#define REG_SC_BK22_31_H _PK_H_(0x22, 0x31) ++#define REG_SC_BK22_32_L _PK_L_(0x22, 0x32) ++#define REG_SC_BK22_32_H _PK_H_(0x22, 0x32) ++#define REG_SC_BK22_33_L _PK_L_(0x22, 0x33) ++#define REG_SC_BK22_33_H _PK_H_(0x22, 0x33) ++#define REG_SC_BK22_34_L _PK_L_(0x22, 0x34) ++#define REG_SC_BK22_34_H _PK_H_(0x22, 0x34) ++#define REG_SC_BK22_35_L _PK_L_(0x22, 0x35) ++#define REG_SC_BK22_35_H _PK_H_(0x22, 0x35) ++#define REG_SC_BK22_36_L _PK_L_(0x22, 0x36) ++#define REG_SC_BK22_36_H _PK_H_(0x22, 0x36) ++#define REG_SC_BK22_37_L _PK_L_(0x22, 0x37) ++#define REG_SC_BK22_37_H _PK_H_(0x22, 0x37) ++#define REG_SC_BK22_38_L _PK_L_(0x22, 0x38) ++#define REG_SC_BK22_38_H _PK_H_(0x22, 0x38) ++#define REG_SC_BK22_39_L _PK_L_(0x22, 0x39) ++#define REG_SC_BK22_39_H _PK_H_(0x22, 0x39) ++#define REG_SC_BK22_3A_L _PK_L_(0x22, 0x3A) ++#define REG_SC_BK22_3A_H _PK_H_(0x22, 0x3A) ++#define REG_SC_BK22_3B_L _PK_L_(0x22, 0x3B) ++#define REG_SC_BK22_3B_H _PK_H_(0x22, 0x3B) ++#define REG_SC_BK22_3C_L _PK_L_(0x22, 0x3C) ++#define REG_SC_BK22_3C_H _PK_H_(0x22, 0x3C) ++#define REG_SC_BK22_3D_L _PK_L_(0x22, 0x3D) ++#define REG_SC_BK22_3D_H _PK_H_(0x22, 0x3D) ++#define REG_SC_BK22_3E_L _PK_L_(0x22, 0x3E) ++#define REG_SC_BK22_3E_H _PK_H_(0x22, 0x3E) ++#define REG_SC_BK22_3F_L _PK_L_(0x22, 0x3F) ++#define REG_SC_BK22_3F_H _PK_H_(0x22, 0x3F) ++#define REG_SC_BK22_40_L _PK_L_(0x22, 0x40) ++#define REG_SC_BK22_40_H _PK_H_(0x22, 0x40) ++#define REG_SC_BK22_41_L _PK_L_(0x22, 0x41) ++#define REG_SC_BK22_41_H _PK_H_(0x22, 0x41) ++#define REG_SC_BK22_42_L _PK_L_(0x22, 0x42) ++#define REG_SC_BK22_42_H _PK_H_(0x22, 0x42) ++#define REG_SC_BK22_43_L _PK_L_(0x22, 0x43) ++#define REG_SC_BK22_43_H _PK_H_(0x22, 0x43) ++#define REG_SC_BK22_44_L _PK_L_(0x22, 0x44) ++#define REG_SC_BK22_44_H _PK_H_(0x22, 0x44) ++#define REG_SC_BK22_45_L _PK_L_(0x22, 0x45) ++#define REG_SC_BK22_45_H _PK_H_(0x22, 0x45) ++#define REG_SC_BK22_46_L _PK_L_(0x22, 0x46) ++#define REG_SC_BK22_46_H _PK_H_(0x22, 0x46) ++#define REG_SC_BK22_47_L _PK_L_(0x22, 0x47) ++#define REG_SC_BK22_47_H _PK_H_(0x22, 0x47) ++#define REG_SC_BK22_48_L _PK_L_(0x22, 0x48) ++#define REG_SC_BK22_48_H _PK_H_(0x22, 0x48) ++#define REG_SC_BK22_49_L _PK_L_(0x22, 0x49) ++#define REG_SC_BK22_49_H _PK_H_(0x22, 0x49) ++#define REG_SC_BK22_4A_L _PK_L_(0x22, 0x4A) ++#define REG_SC_BK22_4A_H _PK_H_(0x22, 0x4A) ++#define REG_SC_BK22_4B_L _PK_L_(0x22, 0x4B) ++#define REG_SC_BK22_4B_H _PK_H_(0x22, 0x4B) ++#define REG_SC_BK22_4C_L _PK_L_(0x22, 0x4C) ++#define REG_SC_BK22_4C_H _PK_H_(0x22, 0x4C) ++#define REG_SC_BK22_4D_L _PK_L_(0x22, 0x4D) ++#define REG_SC_BK22_4D_H _PK_H_(0x22, 0x4D) ++#define REG_SC_BK22_4E_L _PK_L_(0x22, 0x4E) ++#define REG_SC_BK22_4E_H _PK_H_(0x22, 0x4E) ++#define REG_SC_BK22_4F_L _PK_L_(0x22, 0x4F) ++#define REG_SC_BK22_4F_H _PK_H_(0x22, 0x4F) ++#define REG_SC_BK22_50_L _PK_L_(0x22, 0x50) ++#define REG_SC_BK22_50_H _PK_H_(0x22, 0x50) ++#define REG_SC_BK22_51_L _PK_L_(0x22, 0x51) ++#define REG_SC_BK22_51_H _PK_H_(0x22, 0x51) ++#define REG_SC_BK22_52_L _PK_L_(0x22, 0x52) ++#define REG_SC_BK22_52_H _PK_H_(0x22, 0x52) ++#define REG_SC_BK22_53_L _PK_L_(0x22, 0x53) ++#define REG_SC_BK22_53_H _PK_H_(0x22, 0x53) ++#define REG_SC_BK22_54_L _PK_L_(0x22, 0x54) ++#define REG_SC_BK22_54_H _PK_H_(0x22, 0x54) ++#define REG_SC_BK22_55_L _PK_L_(0x22, 0x55) ++#define REG_SC_BK22_55_H _PK_H_(0x22, 0x55) ++#define REG_SC_BK22_56_L _PK_L_(0x22, 0x56) ++#define REG_SC_BK22_56_H _PK_H_(0x22, 0x56) ++#define REG_SC_BK22_57_L _PK_L_(0x22, 0x57) ++#define REG_SC_BK22_57_H _PK_H_(0x22, 0x57) ++#define REG_SC_BK22_58_L _PK_L_(0x22, 0x58) ++#define REG_SC_BK22_58_H _PK_H_(0x22, 0x58) ++#define REG_SC_BK22_59_L _PK_L_(0x22, 0x59) ++#define REG_SC_BK22_59_H _PK_H_(0x22, 0x59) ++#define REG_SC_BK22_5A_L _PK_L_(0x22, 0x5A) ++#define REG_SC_BK22_5A_H _PK_H_(0x22, 0x5A) ++#define REG_SC_BK22_5B_L _PK_L_(0x22, 0x5B) ++#define REG_SC_BK22_5B_H _PK_H_(0x22, 0x5B) ++#define REG_SC_BK22_5C_L _PK_L_(0x22, 0x5C) ++#define REG_SC_BK22_5C_H _PK_H_(0x22, 0x5C) ++#define REG_SC_BK22_5D_L _PK_L_(0x22, 0x5D) ++#define REG_SC_BK22_5D_H _PK_H_(0x22, 0x5D) ++#define REG_SC_BK22_5E_L _PK_L_(0x22, 0x5E) ++#define REG_SC_BK22_5E_H _PK_H_(0x22, 0x5E) ++#define REG_SC_BK22_5F_L _PK_L_(0x22, 0x5F) ++#define REG_SC_BK22_5F_H _PK_H_(0x22, 0x5F) ++#define REG_SC_BK22_60_L _PK_L_(0x22, 0x60) ++#define REG_SC_BK22_60_H _PK_H_(0x22, 0x60) ++#define REG_SC_BK22_61_L _PK_L_(0x22, 0x61) ++#define REG_SC_BK22_61_H _PK_H_(0x22, 0x61) ++#define REG_SC_BK22_62_L _PK_L_(0x22, 0x62) ++#define REG_SC_BK22_62_H _PK_H_(0x22, 0x62) ++#define REG_SC_BK22_63_L _PK_L_(0x22, 0x63) ++#define REG_SC_BK22_63_H _PK_H_(0x22, 0x63) ++#define REG_SC_BK22_64_L _PK_L_(0x22, 0x64) ++#define REG_SC_BK22_64_H _PK_H_(0x22, 0x64) ++#define REG_SC_BK22_65_L _PK_L_(0x22, 0x65) ++#define REG_SC_BK22_65_H _PK_H_(0x22, 0x65) ++#define REG_SC_BK22_66_L _PK_L_(0x22, 0x66) ++#define REG_SC_BK22_66_H _PK_H_(0x22, 0x66) ++#define REG_SC_BK22_67_L _PK_L_(0x22, 0x67) ++#define REG_SC_BK22_67_H _PK_H_(0x22, 0x67) ++#define REG_SC_BK22_68_L _PK_L_(0x22, 0x68) ++#define REG_SC_BK22_68_H _PK_H_(0x22, 0x68) ++#define REG_SC_BK22_69_L _PK_L_(0x22, 0x69) ++#define REG_SC_BK22_69_H _PK_H_(0x22, 0x69) ++#define REG_SC_BK22_6A_L _PK_L_(0x22, 0x6A) ++#define REG_SC_BK22_6A_H _PK_H_(0x22, 0x6A) ++#define REG_SC_BK22_6B_L _PK_L_(0x22, 0x6B) ++#define REG_SC_BK22_6B_H _PK_H_(0x22, 0x6B) ++#define REG_SC_BK22_6C_L _PK_L_(0x22, 0x6C) ++#define REG_SC_BK22_6C_H _PK_H_(0x22, 0x6C) ++#define REG_SC_BK22_6D_L _PK_L_(0x22, 0x6D) ++#define REG_SC_BK22_6D_H _PK_H_(0x22, 0x6D) ++#define REG_SC_BK22_6E_L _PK_L_(0x22, 0x6E) ++#define REG_SC_BK22_6E_H _PK_H_(0x22, 0x6E) ++#define REG_SC_BK22_6F_L _PK_L_(0x22, 0x6F) ++#define REG_SC_BK22_6F_H _PK_H_(0x22, 0x6F) ++#define REG_SC_BK22_70_L _PK_L_(0x22, 0x70) ++#define REG_SC_BK22_70_H _PK_H_(0x22, 0x70) ++#define REG_SC_BK22_71_L _PK_L_(0x22, 0x71) ++#define REG_SC_BK22_71_H _PK_H_(0x22, 0x71) ++#define REG_SC_BK22_72_L _PK_L_(0x22, 0x72) ++#define REG_SC_BK22_72_H _PK_H_(0x22, 0x72) ++#define REG_SC_BK22_73_L _PK_L_(0x22, 0x73) ++#define REG_SC_BK22_73_H _PK_H_(0x22, 0x73) ++#define REG_SC_BK22_74_L _PK_L_(0x22, 0x74) ++#define REG_SC_BK22_74_H _PK_H_(0x22, 0x74) ++#define REG_SC_BK22_75_L _PK_L_(0x22, 0x75) ++#define REG_SC_BK22_75_H _PK_H_(0x22, 0x75) ++#define REG_SC_BK22_76_L _PK_L_(0x22, 0x76) ++#define REG_SC_BK22_76_H _PK_H_(0x22, 0x76) ++#define REG_SC_BK22_77_L _PK_L_(0x22, 0x77) ++#define REG_SC_BK22_77_H _PK_H_(0x22, 0x77) ++#define REG_SC_BK22_78_L _PK_L_(0x22, 0x78) ++#define REG_SC_BK22_78_H _PK_H_(0x22, 0x78) ++#define REG_SC_BK22_79_L _PK_L_(0x22, 0x79) ++#define REG_SC_BK22_79_H _PK_H_(0x22, 0x79) ++#define REG_SC_BK22_7A_L _PK_L_(0x22, 0x7A) ++#define REG_SC_BK22_7A_H _PK_H_(0x22, 0x7A) ++#define REG_SC_BK22_7B_L _PK_L_(0x22, 0x7B) ++#define REG_SC_BK22_7B_H _PK_H_(0x22, 0x7B) ++#define REG_SC_BK22_7C_L _PK_L_(0x22, 0x7C) ++#define REG_SC_BK22_7C_H _PK_H_(0x22, 0x7C) ++#define REG_SC_BK22_7D_L _PK_L_(0x22, 0x7D) ++#define REG_SC_BK22_7D_H _PK_H_(0x22, 0x7D) ++#define REG_SC_BK22_7E_L _PK_L_(0x22, 0x7E) ++#define REG_SC_BK22_7E_H _PK_H_(0x22, 0x7E) ++#define REG_SC_BK22_7F_L _PK_L_(0x22, 0x7F) ++#define REG_SC_BK22_7F_H _PK_H_(0x22, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK23_00_L _PK_L_(0x23, 0x00) ++#define REG_SC_BK23_00_H _PK_H_(0x23, 0x00) ++#define REG_SC_BK23_01_L _PK_L_(0x23, 0x01) ++#define REG_SC_BK23_01_H _PK_H_(0x23, 0x01) ++#define REG_SC_BK23_02_L _PK_L_(0x23, 0x02) ++#define REG_SC_BK23_02_H _PK_H_(0x23, 0x02) ++#define REG_SC_BK23_03_L _PK_L_(0x23, 0x03) ++#define REG_SC_BK23_03_H _PK_H_(0x23, 0x03) ++#define REG_SC_BK23_04_L _PK_L_(0x23, 0x04) ++#define REG_SC_BK23_04_H _PK_H_(0x23, 0x04) ++#define REG_SC_BK23_05_L _PK_L_(0x23, 0x05) ++#define REG_SC_BK23_05_H _PK_H_(0x23, 0x05) ++#define REG_SC_BK23_06_L _PK_L_(0x23, 0x06) ++#define REG_SC_BK23_06_H _PK_H_(0x23, 0x06) ++#define REG_SC_BK23_07_L _PK_L_(0x23, 0x07) ++#define REG_SC_BK23_07_H _PK_H_(0x23, 0x07) ++#define REG_SC_BK23_08_L _PK_L_(0x23, 0x08) ++#define REG_SC_BK23_08_H _PK_H_(0x23, 0x08) ++#define REG_SC_BK23_09_L _PK_L_(0x23, 0x09) ++#define REG_SC_BK23_09_H _PK_H_(0x23, 0x09) ++#define REG_SC_BK23_0A_L _PK_L_(0x23, 0x0A) ++#define REG_SC_BK23_0A_H _PK_H_(0x23, 0x0A) ++#define REG_SC_BK23_0B_L _PK_L_(0x23, 0x0B) ++#define REG_SC_BK23_0B_H _PK_H_(0x23, 0x0B) ++#define REG_SC_BK23_0C_L _PK_L_(0x23, 0x0C) ++#define REG_SC_BK23_0C_H _PK_H_(0x23, 0x0C) ++#define REG_SC_BK23_0D_L _PK_L_(0x23, 0x0D) ++#define REG_SC_BK23_0D_H _PK_H_(0x23, 0x0D) ++#define REG_SC_BK23_0E_L _PK_L_(0x23, 0x0E) ++#define REG_SC_BK23_0E_H _PK_H_(0x23, 0x0E) ++#define REG_SC_BK23_0F_L _PK_L_(0x23, 0x0F) ++#define REG_SC_BK23_0F_H _PK_H_(0x23, 0x0F) ++#define REG_SC_BK23_10_L _PK_L_(0x23, 0x10) ++#define REG_SC_BK23_10_H _PK_H_(0x23, 0x10) ++#define REG_SC_BK23_11_L _PK_L_(0x23, 0x11) ++#define REG_SC_BK23_11_H _PK_H_(0x23, 0x11) ++#define REG_SC_BK23_12_L _PK_L_(0x23, 0x12) ++#define REG_SC_BK23_12_H _PK_H_(0x23, 0x12) ++#define REG_SC_BK23_13_L _PK_L_(0x23, 0x13) ++#define REG_SC_BK23_13_H _PK_H_(0x23, 0x13) ++#define REG_SC_BK23_14_L _PK_L_(0x23, 0x14) ++#define REG_SC_BK23_14_H _PK_H_(0x23, 0x14) ++#define REG_SC_BK23_15_L _PK_L_(0x23, 0x15) ++#define REG_SC_BK23_15_H _PK_H_(0x23, 0x15) ++#define REG_SC_BK23_16_L _PK_L_(0x23, 0x16) ++#define REG_SC_BK23_16_H _PK_H_(0x23, 0x16) ++#define REG_SC_BK23_17_L _PK_L_(0x23, 0x17) ++#define REG_SC_BK23_17_H _PK_H_(0x23, 0x17) ++#define REG_SC_BK23_18_L _PK_L_(0x23, 0x18) ++#define REG_SC_BK23_18_H _PK_H_(0x23, 0x18) ++#define REG_SC_BK23_19_L _PK_L_(0x23, 0x19) ++#define REG_SC_BK23_19_H _PK_H_(0x23, 0x19) ++#define REG_SC_BK23_1A_L _PK_L_(0x23, 0x1A) ++#define REG_SC_BK23_1A_H _PK_H_(0x23, 0x1A) ++#define REG_SC_BK23_1B_L _PK_L_(0x23, 0x1B) ++#define REG_SC_BK23_1B_H _PK_H_(0x23, 0x1B) ++#define REG_SC_BK23_1C_L _PK_L_(0x23, 0x1C) ++#define REG_SC_BK23_1C_H _PK_H_(0x23, 0x1C) ++#define REG_SC_BK23_1D_L _PK_L_(0x23, 0x1D) ++#define REG_SC_BK23_1D_H _PK_H_(0x23, 0x1D) ++#define REG_SC_BK23_1E_L _PK_L_(0x23, 0x1E) ++#define REG_SC_BK23_1E_H _PK_H_(0x23, 0x1E) ++#define REG_SC_BK23_1F_L _PK_L_(0x23, 0x1F) ++#define REG_SC_BK23_1F_H _PK_H_(0x23, 0x1F) ++#define REG_SC_BK23_20_L _PK_L_(0x23, 0x20) ++#define REG_SC_BK23_20_H _PK_H_(0x23, 0x20) ++#define REG_SC_BK23_21_L _PK_L_(0x23, 0x21) ++#define REG_SC_BK23_21_H _PK_H_(0x23, 0x21) ++#define REG_SC_BK23_22_L _PK_L_(0x23, 0x22) ++#define REG_SC_BK23_22_H _PK_H_(0x23, 0x22) ++#define REG_SC_BK23_23_L _PK_L_(0x23, 0x23) ++#define REG_SC_BK23_23_H _PK_H_(0x23, 0x23) ++#define REG_SC_BK23_24_L _PK_L_(0x23, 0x24) ++#define REG_SC_BK23_24_H _PK_H_(0x23, 0x24) ++#define REG_SC_BK23_25_L _PK_L_(0x23, 0x25) ++#define REG_SC_BK23_25_H _PK_H_(0x23, 0x25) ++#define REG_SC_BK23_26_L _PK_L_(0x23, 0x26) ++#define REG_SC_BK23_26_H _PK_H_(0x23, 0x26) ++#define REG_SC_BK23_27_L _PK_L_(0x23, 0x27) ++#define REG_SC_BK23_27_H _PK_H_(0x23, 0x27) ++#define REG_SC_BK23_28_L _PK_L_(0x23, 0x28) ++#define REG_SC_BK23_28_H _PK_H_(0x23, 0x28) ++#define REG_SC_BK23_29_L _PK_L_(0x23, 0x29) ++#define REG_SC_BK23_29_H _PK_H_(0x23, 0x29) ++#define REG_SC_BK23_2A_L _PK_L_(0x23, 0x2A) ++#define REG_SC_BK23_2A_H _PK_H_(0x23, 0x2A) ++#define REG_SC_BK23_2B_L _PK_L_(0x23, 0x2B) ++#define REG_SC_BK23_2B_H _PK_H_(0x23, 0x2B) ++#define REG_SC_BK23_2C_L _PK_L_(0x23, 0x2C) ++#define REG_SC_BK23_2C_H _PK_H_(0x23, 0x2C) ++#define REG_SC_BK23_2D_L _PK_L_(0x23, 0x2D) ++#define REG_SC_BK23_2D_H _PK_H_(0x23, 0x2D) ++#define REG_SC_BK23_2E_L _PK_L_(0x23, 0x2E) ++#define REG_SC_BK23_2E_H _PK_H_(0x23, 0x2E) ++#define REG_SC_BK23_2F_L _PK_L_(0x23, 0x2F) ++#define REG_SC_BK23_2F_H _PK_H_(0x23, 0x2F) ++#define REG_SC_BK23_30_L _PK_L_(0x23, 0x30) ++#define REG_SC_BK23_30_H _PK_H_(0x23, 0x30) ++#define REG_SC_BK23_31_L _PK_L_(0x23, 0x31) ++#define REG_SC_BK23_31_H _PK_H_(0x23, 0x31) ++#define REG_SC_BK23_32_L _PK_L_(0x23, 0x32) ++#define REG_SC_BK23_32_H _PK_H_(0x23, 0x32) ++#define REG_SC_BK23_33_L _PK_L_(0x23, 0x33) ++#define REG_SC_BK23_33_H _PK_H_(0x23, 0x33) ++#define REG_SC_BK23_34_L _PK_L_(0x23, 0x34) ++#define REG_SC_BK23_34_H _PK_H_(0x23, 0x34) ++#define REG_SC_BK23_35_L _PK_L_(0x23, 0x35) ++#define REG_SC_BK23_35_H _PK_H_(0x23, 0x35) ++#define REG_SC_BK23_36_L _PK_L_(0x23, 0x36) ++#define REG_SC_BK23_36_H _PK_H_(0x23, 0x36) ++#define REG_SC_BK23_37_L _PK_L_(0x23, 0x37) ++#define REG_SC_BK23_37_H _PK_H_(0x23, 0x37) ++#define REG_SC_BK23_38_L _PK_L_(0x23, 0x38) ++#define REG_SC_BK23_38_H _PK_H_(0x23, 0x38) ++#define REG_SC_BK23_39_L _PK_L_(0x23, 0x39) ++#define REG_SC_BK23_39_H _PK_H_(0x23, 0x39) ++#define REG_SC_BK23_3A_L _PK_L_(0x23, 0x3A) ++#define REG_SC_BK23_3A_H _PK_H_(0x23, 0x3A) ++#define REG_SC_BK23_3B_L _PK_L_(0x23, 0x3B) ++#define REG_SC_BK23_3B_H _PK_H_(0x23, 0x3B) ++#define REG_SC_BK23_3C_L _PK_L_(0x23, 0x3C) ++#define REG_SC_BK23_3C_H _PK_H_(0x23, 0x3C) ++#define REG_SC_BK23_3D_L _PK_L_(0x23, 0x3D) ++#define REG_SC_BK23_3D_H _PK_H_(0x23, 0x3D) ++#define REG_SC_BK23_3E_L _PK_L_(0x23, 0x3E) ++#define REG_SC_BK23_3E_H _PK_H_(0x23, 0x3E) ++#define REG_SC_BK23_3F_L _PK_L_(0x23, 0x3F) ++#define REG_SC_BK23_3F_H _PK_H_(0x23, 0x3F) ++#define REG_SC_BK23_40_L _PK_L_(0x23, 0x40) ++#define REG_SC_BK23_40_H _PK_H_(0x23, 0x40) ++#define REG_SC_BK23_41_L _PK_L_(0x23, 0x41) ++#define REG_SC_BK23_41_H _PK_H_(0x23, 0x41) ++#define REG_SC_BK23_42_L _PK_L_(0x23, 0x42) ++#define REG_SC_BK23_42_H _PK_H_(0x23, 0x42) ++#define REG_SC_BK23_43_L _PK_L_(0x23, 0x43) ++#define REG_SC_BK23_43_H _PK_H_(0x23, 0x43) ++#define REG_SC_BK23_44_L _PK_L_(0x23, 0x44) ++#define REG_SC_BK23_44_H _PK_H_(0x23, 0x44) ++#define REG_SC_BK23_45_L _PK_L_(0x23, 0x45) ++#define REG_SC_BK23_45_H _PK_H_(0x23, 0x45) ++#define REG_SC_BK23_46_L _PK_L_(0x23, 0x46) ++#define REG_SC_BK23_46_H _PK_H_(0x23, 0x46) ++#define REG_SC_BK23_47_L _PK_L_(0x23, 0x47) ++#define REG_SC_BK23_47_H _PK_H_(0x23, 0x47) ++#define REG_SC_BK23_48_L _PK_L_(0x23, 0x48) ++#define REG_SC_BK23_48_H _PK_H_(0x23, 0x48) ++#define REG_SC_BK23_49_L _PK_L_(0x23, 0x49) ++#define REG_SC_BK23_49_H _PK_H_(0x23, 0x49) ++#define REG_SC_BK23_4A_L _PK_L_(0x23, 0x4A) ++#define REG_SC_BK23_4A_H _PK_H_(0x23, 0x4A) ++#define REG_SC_BK23_4B_L _PK_L_(0x23, 0x4B) ++#define REG_SC_BK23_4B_H _PK_H_(0x23, 0x4B) ++#define REG_SC_BK23_4C_L _PK_L_(0x23, 0x4C) ++#define REG_SC_BK23_4C_H _PK_H_(0x23, 0x4C) ++#define REG_SC_BK23_4D_L _PK_L_(0x23, 0x4D) ++#define REG_SC_BK23_4D_H _PK_H_(0x23, 0x4D) ++#define REG_SC_BK23_4E_L _PK_L_(0x23, 0x4E) ++#define REG_SC_BK23_4E_H _PK_H_(0x23, 0x4E) ++#define REG_SC_BK23_4F_L _PK_L_(0x23, 0x4F) ++#define REG_SC_BK23_4F_H _PK_H_(0x23, 0x4F) ++#define REG_SC_BK23_50_L _PK_L_(0x23, 0x50) ++#define REG_SC_BK23_50_H _PK_H_(0x23, 0x50) ++#define REG_SC_BK23_51_L _PK_L_(0x23, 0x51) ++#define REG_SC_BK23_51_H _PK_H_(0x23, 0x51) ++#define REG_SC_BK23_52_L _PK_L_(0x23, 0x52) ++#define REG_SC_BK23_52_H _PK_H_(0x23, 0x52) ++#define REG_SC_BK23_53_L _PK_L_(0x23, 0x53) ++#define REG_SC_BK23_53_H _PK_H_(0x23, 0x53) ++#define REG_SC_BK23_54_L _PK_L_(0x23, 0x54) ++#define REG_SC_BK23_54_H _PK_H_(0x23, 0x54) ++#define REG_SC_BK23_55_L _PK_L_(0x23, 0x55) ++#define REG_SC_BK23_55_H _PK_H_(0x23, 0x55) ++#define REG_SC_BK23_56_L _PK_L_(0x23, 0x56) ++#define REG_SC_BK23_56_H _PK_H_(0x23, 0x56) ++#define REG_SC_BK23_57_L _PK_L_(0x23, 0x57) ++#define REG_SC_BK23_57_H _PK_H_(0x23, 0x57) ++#define REG_SC_BK23_58_L _PK_L_(0x23, 0x58) ++#define REG_SC_BK23_58_H _PK_H_(0x23, 0x58) ++#define REG_SC_BK23_59_L _PK_L_(0x23, 0x59) ++#define REG_SC_BK23_59_H _PK_H_(0x23, 0x59) ++#define REG_SC_BK23_5A_L _PK_L_(0x23, 0x5A) ++#define REG_SC_BK23_5A_H _PK_H_(0x23, 0x5A) ++#define REG_SC_BK23_5B_L _PK_L_(0x23, 0x5B) ++#define REG_SC_BK23_5B_H _PK_H_(0x23, 0x5B) ++#define REG_SC_BK23_5C_L _PK_L_(0x23, 0x5C) ++#define REG_SC_BK23_5C_H _PK_H_(0x23, 0x5C) ++#define REG_SC_BK23_5D_L _PK_L_(0x23, 0x5D) ++#define REG_SC_BK23_5D_H _PK_H_(0x23, 0x5D) ++#define REG_SC_BK23_5E_L _PK_L_(0x23, 0x5E) ++#define REG_SC_BK23_5E_H _PK_H_(0x23, 0x5E) ++#define REG_SC_BK23_5F_L _PK_L_(0x23, 0x5F) ++#define REG_SC_BK23_5F_H _PK_H_(0x23, 0x5F) ++#define REG_SC_BK23_60_L _PK_L_(0x23, 0x60) ++#define REG_SC_BK23_60_H _PK_H_(0x23, 0x60) ++#define REG_SC_BK23_61_L _PK_L_(0x23, 0x61) ++#define REG_SC_BK23_61_H _PK_H_(0x23, 0x61) ++#define REG_SC_BK23_62_L _PK_L_(0x23, 0x62) ++#define REG_SC_BK23_62_H _PK_H_(0x23, 0x62) ++#define REG_SC_BK23_63_L _PK_L_(0x23, 0x63) ++#define REG_SC_BK23_63_H _PK_H_(0x23, 0x63) ++#define REG_SC_BK23_64_L _PK_L_(0x23, 0x64) ++#define REG_SC_BK23_64_H _PK_H_(0x23, 0x64) ++#define REG_SC_BK23_65_L _PK_L_(0x23, 0x65) ++#define REG_SC_BK23_65_H _PK_H_(0x23, 0x65) ++#define REG_SC_BK23_66_L _PK_L_(0x23, 0x66) ++#define REG_SC_BK23_66_H _PK_H_(0x23, 0x66) ++#define REG_SC_BK23_67_L _PK_L_(0x23, 0x67) ++#define REG_SC_BK23_67_H _PK_H_(0x23, 0x67) ++#define REG_SC_BK23_68_L _PK_L_(0x23, 0x68) ++#define REG_SC_BK23_68_H _PK_H_(0x23, 0x68) ++#define REG_SC_BK23_69_L _PK_L_(0x23, 0x69) ++#define REG_SC_BK23_69_H _PK_H_(0x23, 0x69) ++#define REG_SC_BK23_6A_L _PK_L_(0x23, 0x6A) ++#define REG_SC_BK23_6A_H _PK_H_(0x23, 0x6A) ++#define REG_SC_BK23_6B_L _PK_L_(0x23, 0x6B) ++#define REG_SC_BK23_6B_H _PK_H_(0x23, 0x6B) ++#define REG_SC_BK23_6C_L _PK_L_(0x23, 0x6C) ++#define REG_SC_BK23_6C_H _PK_H_(0x23, 0x6C) ++#define REG_SC_BK23_6D_L _PK_L_(0x23, 0x6D) ++#define REG_SC_BK23_6D_H _PK_H_(0x23, 0x6D) ++#define REG_SC_BK23_6E_L _PK_L_(0x23, 0x6E) ++#define REG_SC_BK23_6E_H _PK_H_(0x23, 0x6E) ++#define REG_SC_BK23_6F_L _PK_L_(0x23, 0x6F) ++#define REG_SC_BK23_6F_H _PK_H_(0x23, 0x6F) ++#define REG_SC_BK23_70_L _PK_L_(0x23, 0x70) ++#define REG_SC_BK23_70_H _PK_H_(0x23, 0x70) ++#define REG_SC_BK23_71_L _PK_L_(0x23, 0x71) ++#define REG_SC_BK23_71_H _PK_H_(0x23, 0x71) ++#define REG_SC_BK23_72_L _PK_L_(0x23, 0x72) ++#define REG_SC_BK23_72_H _PK_H_(0x23, 0x72) ++#define REG_SC_BK23_73_L _PK_L_(0x23, 0x73) ++#define REG_SC_BK23_73_H _PK_H_(0x23, 0x73) ++#define REG_SC_BK23_74_L _PK_L_(0x23, 0x74) ++#define REG_SC_BK23_74_H _PK_H_(0x23, 0x74) ++#define REG_SC_BK23_75_L _PK_L_(0x23, 0x75) ++#define REG_SC_BK23_75_H _PK_H_(0x23, 0x75) ++#define REG_SC_BK23_76_L _PK_L_(0x23, 0x76) ++#define REG_SC_BK23_76_H _PK_H_(0x23, 0x76) ++#define REG_SC_BK23_77_L _PK_L_(0x23, 0x77) ++#define REG_SC_BK23_77_H _PK_H_(0x23, 0x77) ++#define REG_SC_BK23_78_L _PK_L_(0x23, 0x78) ++#define REG_SC_BK23_78_H _PK_H_(0x23, 0x78) ++#define REG_SC_BK23_79_L _PK_L_(0x23, 0x79) ++#define REG_SC_BK23_79_H _PK_H_(0x23, 0x79) ++#define REG_SC_BK23_7A_L _PK_L_(0x23, 0x7A) ++#define REG_SC_BK23_7A_H _PK_H_(0x23, 0x7A) ++#define REG_SC_BK23_7B_L _PK_L_(0x23, 0x7B) ++#define REG_SC_BK23_7B_H _PK_H_(0x23, 0x7B) ++#define REG_SC_BK23_7C_L _PK_L_(0x23, 0x7C) ++#define REG_SC_BK23_7C_H _PK_H_(0x23, 0x7C) ++#define REG_SC_BK23_7D_L _PK_L_(0x23, 0x7D) ++#define REG_SC_BK23_7D_H _PK_H_(0x23, 0x7D) ++#define REG_SC_BK23_7E_L _PK_L_(0x23, 0x7E) ++#define REG_SC_BK23_7E_H _PK_H_(0x23, 0x7E) ++#define REG_SC_BK23_7F_L _PK_L_(0x23, 0x7F) ++#define REG_SC_BK23_7F_H _PK_H_(0x23, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK24_00_L _PK_L_(0x24, 0x00) ++#define REG_SC_BK24_00_H _PK_H_(0x24, 0x00) ++#define REG_SC_BK24_01_L _PK_L_(0x24, 0x01) ++#define REG_SC_BK24_01_H _PK_H_(0x24, 0x01) ++#define REG_SC_BK24_02_L _PK_L_(0x24, 0x02) ++#define REG_SC_BK24_02_H _PK_H_(0x24, 0x02) ++#define REG_SC_BK24_03_L _PK_L_(0x24, 0x03) ++#define REG_SC_BK24_03_H _PK_H_(0x24, 0x03) ++#define REG_SC_BK24_04_L _PK_L_(0x24, 0x04) ++#define REG_SC_BK24_04_H _PK_H_(0x24, 0x04) ++#define REG_SC_BK24_05_L _PK_L_(0x24, 0x05) ++#define REG_SC_BK24_05_H _PK_H_(0x24, 0x05) ++#define REG_SC_BK24_06_L _PK_L_(0x24, 0x06) ++#define REG_SC_BK24_06_H _PK_H_(0x24, 0x06) ++#define REG_SC_BK24_07_L _PK_L_(0x24, 0x07) ++#define REG_SC_BK24_07_H _PK_H_(0x24, 0x07) ++#define REG_SC_BK24_08_L _PK_L_(0x24, 0x08) ++#define REG_SC_BK24_08_H _PK_H_(0x24, 0x08) ++#define REG_SC_BK24_09_L _PK_L_(0x24, 0x09) ++#define REG_SC_BK24_09_H _PK_H_(0x24, 0x09) ++#define REG_SC_BK24_0A_L _PK_L_(0x24, 0x0A) ++#define REG_SC_BK24_0A_H _PK_H_(0x24, 0x0A) ++#define REG_SC_BK24_0B_L _PK_L_(0x24, 0x0B) ++#define REG_SC_BK24_0B_H _PK_H_(0x24, 0x0B) ++#define REG_SC_BK24_0C_L _PK_L_(0x24, 0x0C) ++#define REG_SC_BK24_0C_H _PK_H_(0x24, 0x0C) ++#define REG_SC_BK24_0D_L _PK_L_(0x24, 0x0D) ++#define REG_SC_BK24_0D_H _PK_H_(0x24, 0x0D) ++#define REG_SC_BK24_0E_L _PK_L_(0x24, 0x0E) ++#define REG_SC_BK24_0E_H _PK_H_(0x24, 0x0E) ++#define REG_SC_BK24_0F_L _PK_L_(0x24, 0x0F) ++#define REG_SC_BK24_0F_H _PK_H_(0x24, 0x0F) ++#define REG_SC_BK24_10_L _PK_L_(0x24, 0x10) ++#define REG_SC_BK24_10_H _PK_H_(0x24, 0x10) ++#define REG_SC_BK24_11_L _PK_L_(0x24, 0x11) ++#define REG_SC_BK24_11_H _PK_H_(0x24, 0x11) ++#define REG_SC_BK24_12_L _PK_L_(0x24, 0x12) ++#define REG_SC_BK24_12_H _PK_H_(0x24, 0x12) ++#define REG_SC_BK24_13_L _PK_L_(0x24, 0x13) ++#define REG_SC_BK24_13_H _PK_H_(0x24, 0x13) ++#define REG_SC_BK24_14_L _PK_L_(0x24, 0x14) ++#define REG_SC_BK24_14_H _PK_H_(0x24, 0x14) ++#define REG_SC_BK24_15_L _PK_L_(0x24, 0x15) ++#define REG_SC_BK24_15_H _PK_H_(0x24, 0x15) ++#define REG_SC_BK24_16_L _PK_L_(0x24, 0x16) ++#define REG_SC_BK24_16_H _PK_H_(0x24, 0x16) ++#define REG_SC_BK24_17_L _PK_L_(0x24, 0x17) ++#define REG_SC_BK24_17_H _PK_H_(0x24, 0x17) ++#define REG_SC_BK24_18_L _PK_L_(0x24, 0x18) ++#define REG_SC_BK24_18_H _PK_H_(0x24, 0x18) ++#define REG_SC_BK24_19_L _PK_L_(0x24, 0x19) ++#define REG_SC_BK24_19_H _PK_H_(0x24, 0x19) ++#define REG_SC_BK24_1A_L _PK_L_(0x24, 0x1A) ++#define REG_SC_BK24_1A_H _PK_H_(0x24, 0x1A) ++#define REG_SC_BK24_1B_L _PK_L_(0x24, 0x1B) ++#define REG_SC_BK24_1B_H _PK_H_(0x24, 0x1B) ++#define REG_SC_BK24_1C_L _PK_L_(0x24, 0x1C) ++#define REG_SC_BK24_1C_H _PK_H_(0x24, 0x1C) ++#define REG_SC_BK24_1D_L _PK_L_(0x24, 0x1D) ++#define REG_SC_BK24_1D_H _PK_H_(0x24, 0x1D) ++#define REG_SC_BK24_1E_L _PK_L_(0x24, 0x1E) ++#define REG_SC_BK24_1E_H _PK_H_(0x24, 0x1E) ++#define REG_SC_BK24_1F_L _PK_L_(0x24, 0x1F) ++#define REG_SC_BK24_1F_H _PK_H_(0x24, 0x1F) ++#define REG_SC_BK24_20_L _PK_L_(0x24, 0x20) ++#define REG_SC_BK24_20_H _PK_H_(0x24, 0x20) ++#define REG_SC_BK24_21_L _PK_L_(0x24, 0x21) ++#define REG_SC_BK24_21_H _PK_H_(0x24, 0x21) ++#define REG_SC_BK24_22_L _PK_L_(0x24, 0x22) ++#define REG_SC_BK24_22_H _PK_H_(0x24, 0x22) ++#define REG_SC_BK24_23_L _PK_L_(0x24, 0x23) ++#define REG_SC_BK24_23_H _PK_H_(0x24, 0x23) ++#define REG_SC_BK24_24_L _PK_L_(0x24, 0x24) ++#define REG_SC_BK24_24_H _PK_H_(0x24, 0x24) ++#define REG_SC_BK24_25_L _PK_L_(0x24, 0x25) ++#define REG_SC_BK24_25_H _PK_H_(0x24, 0x25) ++#define REG_SC_BK24_26_L _PK_L_(0x24, 0x26) ++#define REG_SC_BK24_26_H _PK_H_(0x24, 0x26) ++#define REG_SC_BK24_27_L _PK_L_(0x24, 0x27) ++#define REG_SC_BK24_27_H _PK_H_(0x24, 0x27) ++#define REG_SC_BK24_28_L _PK_L_(0x24, 0x28) ++#define REG_SC_BK24_28_H _PK_H_(0x24, 0x28) ++#define REG_SC_BK24_29_L _PK_L_(0x24, 0x29) ++#define REG_SC_BK24_29_H _PK_H_(0x24, 0x29) ++#define REG_SC_BK24_2A_L _PK_L_(0x24, 0x2A) ++#define REG_SC_BK24_2A_H _PK_H_(0x24, 0x2A) ++#define REG_SC_BK24_2B_L _PK_L_(0x24, 0x2B) ++#define REG_SC_BK24_2B_H _PK_H_(0x24, 0x2B) ++#define REG_SC_BK24_2C_L _PK_L_(0x24, 0x2C) ++#define REG_SC_BK24_2C_H _PK_H_(0x24, 0x2C) ++#define REG_SC_BK24_2D_L _PK_L_(0x24, 0x2D) ++#define REG_SC_BK24_2D_H _PK_H_(0x24, 0x2D) ++#define REG_SC_BK24_2E_L _PK_L_(0x24, 0x2E) ++#define REG_SC_BK24_2E_H _PK_H_(0x24, 0x2E) ++#define REG_SC_BK24_2F_L _PK_L_(0x24, 0x2F) ++#define REG_SC_BK24_2F_H _PK_H_(0x24, 0x2F) ++#define REG_SC_BK24_30_L _PK_L_(0x24, 0x30) ++#define REG_SC_BK24_30_H _PK_H_(0x24, 0x30) ++#define REG_SC_BK24_31_L _PK_L_(0x24, 0x31) ++#define REG_SC_BK24_31_H _PK_H_(0x24, 0x31) ++#define REG_SC_BK24_32_L _PK_L_(0x24, 0x32) ++#define REG_SC_BK24_32_H _PK_H_(0x24, 0x32) ++#define REG_SC_BK24_33_L _PK_L_(0x24, 0x33) ++#define REG_SC_BK24_33_H _PK_H_(0x24, 0x33) ++#define REG_SC_BK24_34_L _PK_L_(0x24, 0x34) ++#define REG_SC_BK24_34_H _PK_H_(0x24, 0x34) ++#define REG_SC_BK24_35_L _PK_L_(0x24, 0x35) ++#define REG_SC_BK24_35_H _PK_H_(0x24, 0x35) ++#define REG_SC_BK24_36_L _PK_L_(0x24, 0x36) ++#define REG_SC_BK24_36_H _PK_H_(0x24, 0x36) ++#define REG_SC_BK24_37_L _PK_L_(0x24, 0x37) ++#define REG_SC_BK24_37_H _PK_H_(0x24, 0x37) ++#define REG_SC_BK24_38_L _PK_L_(0x24, 0x38) ++#define REG_SC_BK24_38_H _PK_H_(0x24, 0x38) ++#define REG_SC_BK24_39_L _PK_L_(0x24, 0x39) ++#define REG_SC_BK24_39_H _PK_H_(0x24, 0x39) ++#define REG_SC_BK24_3A_L _PK_L_(0x24, 0x3A) ++#define REG_SC_BK24_3A_H _PK_H_(0x24, 0x3A) ++#define REG_SC_BK24_3B_L _PK_L_(0x24, 0x3B) ++#define REG_SC_BK24_3B_H _PK_H_(0x24, 0x3B) ++#define REG_SC_BK24_3C_L _PK_L_(0x24, 0x3C) ++#define REG_SC_BK24_3C_H _PK_H_(0x24, 0x3C) ++#define REG_SC_BK24_3D_L _PK_L_(0x24, 0x3D) ++#define REG_SC_BK24_3D_H _PK_H_(0x24, 0x3D) ++#define REG_SC_BK24_3E_L _PK_L_(0x24, 0x3E) ++#define REG_SC_BK24_3E_H _PK_H_(0x24, 0x3E) ++#define REG_SC_BK24_3F_L _PK_L_(0x24, 0x3F) ++#define REG_SC_BK24_3F_H _PK_H_(0x24, 0x3F) ++#define REG_SC_BK24_40_L _PK_L_(0x24, 0x40) ++#define REG_SC_BK24_40_H _PK_H_(0x24, 0x40) ++#define REG_SC_BK24_41_L _PK_L_(0x24, 0x41) ++#define REG_SC_BK24_41_H _PK_H_(0x24, 0x41) ++#define REG_SC_BK24_42_L _PK_L_(0x24, 0x42) ++#define REG_SC_BK24_42_H _PK_H_(0x24, 0x42) ++#define REG_SC_BK24_43_L _PK_L_(0x24, 0x43) ++#define REG_SC_BK24_43_H _PK_H_(0x24, 0x43) ++#define REG_SC_BK24_44_L _PK_L_(0x24, 0x44) ++#define REG_SC_BK24_44_H _PK_H_(0x24, 0x44) ++#define REG_SC_BK24_45_L _PK_L_(0x24, 0x45) ++#define REG_SC_BK24_45_H _PK_H_(0x24, 0x45) ++#define REG_SC_BK24_46_L _PK_L_(0x24, 0x46) ++#define REG_SC_BK24_46_H _PK_H_(0x24, 0x46) ++#define REG_SC_BK24_47_L _PK_L_(0x24, 0x47) ++#define REG_SC_BK24_47_H _PK_H_(0x24, 0x47) ++#define REG_SC_BK24_48_L _PK_L_(0x24, 0x48) ++#define REG_SC_BK24_48_H _PK_H_(0x24, 0x48) ++#define REG_SC_BK24_49_L _PK_L_(0x24, 0x49) ++#define REG_SC_BK24_49_H _PK_H_(0x24, 0x49) ++#define REG_SC_BK24_4A_L _PK_L_(0x24, 0x4A) ++#define REG_SC_BK24_4A_H _PK_H_(0x24, 0x4A) ++#define REG_SC_BK24_4B_L _PK_L_(0x24, 0x4B) ++#define REG_SC_BK24_4B_H _PK_H_(0x24, 0x4B) ++#define REG_SC_BK24_4C_L _PK_L_(0x24, 0x4C) ++#define REG_SC_BK24_4C_H _PK_H_(0x24, 0x4C) ++#define REG_SC_BK24_4D_L _PK_L_(0x24, 0x4D) ++#define REG_SC_BK24_4D_H _PK_H_(0x24, 0x4D) ++#define REG_SC_BK24_4E_L _PK_L_(0x24, 0x4E) ++#define REG_SC_BK24_4E_H _PK_H_(0x24, 0x4E) ++#define REG_SC_BK24_4F_L _PK_L_(0x24, 0x4F) ++#define REG_SC_BK24_4F_H _PK_H_(0x24, 0x4F) ++#define REG_SC_BK24_50_L _PK_L_(0x24, 0x50) ++#define REG_SC_BK24_50_H _PK_H_(0x24, 0x50) ++#define REG_SC_BK24_51_L _PK_L_(0x24, 0x51) ++#define REG_SC_BK24_51_H _PK_H_(0x24, 0x51) ++#define REG_SC_BK24_52_L _PK_L_(0x24, 0x52) ++#define REG_SC_BK24_52_H _PK_H_(0x24, 0x52) ++#define REG_SC_BK24_53_L _PK_L_(0x24, 0x53) ++#define REG_SC_BK24_53_H _PK_H_(0x24, 0x53) ++#define REG_SC_BK24_54_L _PK_L_(0x24, 0x54) ++#define REG_SC_BK24_54_H _PK_H_(0x24, 0x54) ++#define REG_SC_BK24_55_L _PK_L_(0x24, 0x55) ++#define REG_SC_BK24_55_H _PK_H_(0x24, 0x55) ++#define REG_SC_BK24_56_L _PK_L_(0x24, 0x56) ++#define REG_SC_BK24_56_H _PK_H_(0x24, 0x56) ++#define REG_SC_BK24_57_L _PK_L_(0x24, 0x57) ++#define REG_SC_BK24_57_H _PK_H_(0x24, 0x57) ++#define REG_SC_BK24_58_L _PK_L_(0x24, 0x58) ++#define REG_SC_BK24_58_H _PK_H_(0x24, 0x58) ++#define REG_SC_BK24_59_L _PK_L_(0x24, 0x59) ++#define REG_SC_BK24_59_H _PK_H_(0x24, 0x59) ++#define REG_SC_BK24_5A_L _PK_L_(0x24, 0x5A) ++#define REG_SC_BK24_5A_H _PK_H_(0x24, 0x5A) ++#define REG_SC_BK24_5B_L _PK_L_(0x24, 0x5B) ++#define REG_SC_BK24_5B_H _PK_H_(0x24, 0x5B) ++#define REG_SC_BK24_5C_L _PK_L_(0x24, 0x5C) ++#define REG_SC_BK24_5C_H _PK_H_(0x24, 0x5C) ++#define REG_SC_BK24_5D_L _PK_L_(0x24, 0x5D) ++#define REG_SC_BK24_5D_H _PK_H_(0x24, 0x5D) ++#define REG_SC_BK24_5E_L _PK_L_(0x24, 0x5E) ++#define REG_SC_BK24_5E_H _PK_H_(0x24, 0x5E) ++#define REG_SC_BK24_5F_L _PK_L_(0x24, 0x5F) ++#define REG_SC_BK24_5F_H _PK_H_(0x24, 0x5F) ++#define REG_SC_BK24_60_L _PK_L_(0x24, 0x60) ++#define REG_SC_BK24_60_H _PK_H_(0x24, 0x60) ++#define REG_SC_BK24_61_L _PK_L_(0x24, 0x61) ++#define REG_SC_BK24_61_H _PK_H_(0x24, 0x61) ++#define REG_SC_BK24_62_L _PK_L_(0x24, 0x62) ++#define REG_SC_BK24_62_H _PK_H_(0x24, 0x62) ++#define REG_SC_BK24_63_L _PK_L_(0x24, 0x63) ++#define REG_SC_BK24_63_H _PK_H_(0x24, 0x63) ++#define REG_SC_BK24_64_L _PK_L_(0x24, 0x64) ++#define REG_SC_BK24_64_H _PK_H_(0x24, 0x64) ++#define REG_SC_BK24_65_L _PK_L_(0x24, 0x65) ++#define REG_SC_BK24_65_H _PK_H_(0x24, 0x65) ++#define REG_SC_BK24_66_L _PK_L_(0x24, 0x66) ++#define REG_SC_BK24_66_H _PK_H_(0x24, 0x66) ++#define REG_SC_BK24_67_L _PK_L_(0x24, 0x67) ++#define REG_SC_BK24_67_H _PK_H_(0x24, 0x67) ++#define REG_SC_BK24_68_L _PK_L_(0x24, 0x68) ++#define REG_SC_BK24_68_H _PK_H_(0x24, 0x68) ++#define REG_SC_BK24_69_L _PK_L_(0x24, 0x69) ++#define REG_SC_BK24_69_H _PK_H_(0x24, 0x69) ++#define REG_SC_BK24_6A_L _PK_L_(0x24, 0x6A) ++#define REG_SC_BK24_6A_H _PK_H_(0x24, 0x6A) ++#define REG_SC_BK24_6B_L _PK_L_(0x24, 0x6B) ++#define REG_SC_BK24_6B_H _PK_H_(0x24, 0x6B) ++#define REG_SC_BK24_6C_L _PK_L_(0x24, 0x6C) ++#define REG_SC_BK24_6C_H _PK_H_(0x24, 0x6C) ++#define REG_SC_BK24_6D_L _PK_L_(0x24, 0x6D) ++#define REG_SC_BK24_6D_H _PK_H_(0x24, 0x6D) ++#define REG_SC_BK24_6E_L _PK_L_(0x24, 0x6E) ++#define REG_SC_BK24_6E_H _PK_H_(0x24, 0x6E) ++#define REG_SC_BK24_6F_L _PK_L_(0x24, 0x6F) ++#define REG_SC_BK24_6F_H _PK_H_(0x24, 0x6F) ++#define REG_SC_BK24_70_L _PK_L_(0x24, 0x70) ++#define REG_SC_BK24_70_H _PK_H_(0x24, 0x70) ++#define REG_SC_BK24_71_L _PK_L_(0x24, 0x71) ++#define REG_SC_BK24_71_H _PK_H_(0x24, 0x71) ++#define REG_SC_BK24_72_L _PK_L_(0x24, 0x72) ++#define REG_SC_BK24_72_H _PK_H_(0x24, 0x72) ++#define REG_SC_BK24_73_L _PK_L_(0x24, 0x73) ++#define REG_SC_BK24_73_H _PK_H_(0x24, 0x73) ++#define REG_SC_BK24_74_L _PK_L_(0x24, 0x74) ++#define REG_SC_BK24_74_H _PK_H_(0x24, 0x74) ++#define REG_SC_BK24_75_L _PK_L_(0x24, 0x75) ++#define REG_SC_BK24_75_H _PK_H_(0x24, 0x75) ++#define REG_SC_BK24_76_L _PK_L_(0x24, 0x76) ++#define REG_SC_BK24_76_H _PK_H_(0x24, 0x76) ++#define REG_SC_BK24_77_L _PK_L_(0x24, 0x77) ++#define REG_SC_BK24_77_H _PK_H_(0x24, 0x77) ++#define REG_SC_BK24_78_L _PK_L_(0x24, 0x78) ++#define REG_SC_BK24_78_H _PK_H_(0x24, 0x78) ++#define REG_SC_BK24_79_L _PK_L_(0x24, 0x79) ++#define REG_SC_BK24_79_H _PK_H_(0x24, 0x79) ++#define REG_SC_BK24_7A_L _PK_L_(0x24, 0x7A) ++#define REG_SC_BK24_7A_H _PK_H_(0x24, 0x7A) ++#define REG_SC_BK24_7B_L _PK_L_(0x24, 0x7B) ++#define REG_SC_BK24_7B_H _PK_H_(0x24, 0x7B) ++#define REG_SC_BK24_7C_L _PK_L_(0x24, 0x7C) ++#define REG_SC_BK24_7C_H _PK_H_(0x24, 0x7C) ++#define REG_SC_BK24_7D_L _PK_L_(0x24, 0x7D) ++#define REG_SC_BK24_7D_H _PK_H_(0x24, 0x7D) ++#define REG_SC_BK24_7E_L _PK_L_(0x24, 0x7E) ++#define REG_SC_BK24_7E_H _PK_H_(0x24, 0x7E) ++#define REG_SC_BK24_7F_L _PK_L_(0x24, 0x7F) ++#define REG_SC_BK24_7F_H _PK_H_(0x24, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK25_00_L _PK_L_(0x25, 0x00) ++#define REG_SC_BK25_00_H _PK_H_(0x25, 0x00) ++#define REG_SC_BK25_01_L _PK_L_(0x25, 0x01) ++#define REG_SC_BK25_01_H _PK_H_(0x25, 0x01) ++#define REG_SC_BK25_02_L _PK_L_(0x25, 0x02) ++#define REG_SC_BK25_02_H _PK_H_(0x25, 0x02) ++#define REG_SC_BK25_03_L _PK_L_(0x25, 0x03) ++#define REG_SC_BK25_03_H _PK_H_(0x25, 0x03) ++#define REG_SC_BK25_04_L _PK_L_(0x25, 0x04) ++#define REG_SC_BK25_04_H _PK_H_(0x25, 0x04) ++#define REG_SC_BK25_05_L _PK_L_(0x25, 0x05) ++#define REG_SC_BK25_05_H _PK_H_(0x25, 0x05) ++#define REG_SC_BK25_06_L _PK_L_(0x25, 0x06) ++#define REG_SC_BK25_06_H _PK_H_(0x25, 0x06) ++#define REG_SC_BK25_07_L _PK_L_(0x25, 0x07) ++#define REG_SC_BK25_07_H _PK_H_(0x25, 0x07) ++#define REG_SC_BK25_08_L _PK_L_(0x25, 0x08) ++#define REG_SC_BK25_08_H _PK_H_(0x25, 0x08) ++#define REG_SC_BK25_09_L _PK_L_(0x25, 0x09) ++#define REG_SC_BK25_09_H _PK_H_(0x25, 0x09) ++#define REG_SC_BK25_0A_L _PK_L_(0x25, 0x0A) ++#define REG_SC_BK25_0A_H _PK_H_(0x25, 0x0A) ++#define REG_SC_BK25_0B_L _PK_L_(0x25, 0x0B) ++#define REG_SC_BK25_0B_H _PK_H_(0x25, 0x0B) ++#define REG_SC_BK25_0C_L _PK_L_(0x25, 0x0C) ++#define REG_SC_BK25_0C_H _PK_H_(0x25, 0x0C) ++#define REG_SC_BK25_0D_L _PK_L_(0x25, 0x0D) ++#define REG_SC_BK25_0D_H _PK_H_(0x25, 0x0D) ++#define REG_SC_BK25_0E_L _PK_L_(0x25, 0x0E) ++#define REG_SC_BK25_0E_H _PK_H_(0x25, 0x0E) ++#define REG_SC_BK25_0F_L _PK_L_(0x25, 0x0F) ++#define REG_SC_BK25_0F_H _PK_H_(0x25, 0x0F) ++#define REG_SC_BK25_10_L _PK_L_(0x25, 0x10) ++#define REG_SC_BK25_10_H _PK_H_(0x25, 0x10) ++#define REG_SC_BK25_11_L _PK_L_(0x25, 0x11) ++#define REG_SC_BK25_11_H _PK_H_(0x25, 0x11) ++#define REG_SC_BK25_12_L _PK_L_(0x25, 0x12) ++#define REG_SC_BK25_12_H _PK_H_(0x25, 0x12) ++#define REG_SC_BK25_13_L _PK_L_(0x25, 0x13) ++#define REG_SC_BK25_13_H _PK_H_(0x25, 0x13) ++#define REG_SC_BK25_14_L _PK_L_(0x25, 0x14) ++#define REG_SC_BK25_14_H _PK_H_(0x25, 0x14) ++#define REG_SC_BK25_15_L _PK_L_(0x25, 0x15) ++#define REG_SC_BK25_15_H _PK_H_(0x25, 0x15) ++#define REG_SC_BK25_16_L _PK_L_(0x25, 0x16) ++#define REG_SC_BK25_16_H _PK_H_(0x25, 0x16) ++#define REG_SC_BK25_17_L _PK_L_(0x25, 0x17) ++#define REG_SC_BK25_17_H _PK_H_(0x25, 0x17) ++#define REG_SC_BK25_18_L _PK_L_(0x25, 0x18) ++#define REG_SC_BK25_18_H _PK_H_(0x25, 0x18) ++#define REG_SC_BK25_19_L _PK_L_(0x25, 0x19) ++#define REG_SC_BK25_19_H _PK_H_(0x25, 0x19) ++#define REG_SC_BK25_1A_L _PK_L_(0x25, 0x1A) ++#define REG_SC_BK25_1A_H _PK_H_(0x25, 0x1A) ++#define REG_SC_BK25_1B_L _PK_L_(0x25, 0x1B) ++#define REG_SC_BK25_1B_H _PK_H_(0x25, 0x1B) ++#define REG_SC_BK25_1C_L _PK_L_(0x25, 0x1C) ++#define REG_SC_BK25_1C_H _PK_H_(0x25, 0x1C) ++#define REG_SC_BK25_1D_L _PK_L_(0x25, 0x1D) ++#define REG_SC_BK25_1D_H _PK_H_(0x25, 0x1D) ++#define REG_SC_BK25_1E_L _PK_L_(0x25, 0x1E) ++#define REG_SC_BK25_1E_H _PK_H_(0x25, 0x1E) ++#define REG_SC_BK25_1F_L _PK_L_(0x25, 0x1F) ++#define REG_SC_BK25_1F_H _PK_H_(0x25, 0x1F) ++#define REG_SC_BK25_20_L _PK_L_(0x25, 0x20) ++#define REG_SC_BK25_20_H _PK_H_(0x25, 0x20) ++#define REG_SC_BK25_21_L _PK_L_(0x25, 0x21) ++#define REG_SC_BK25_21_H _PK_H_(0x25, 0x21) ++#define REG_SC_BK25_22_L _PK_L_(0x25, 0x22) ++#define REG_SC_BK25_22_H _PK_H_(0x25, 0x22) ++#define REG_SC_BK25_23_L _PK_L_(0x25, 0x23) ++#define REG_SC_BK25_23_H _PK_H_(0x25, 0x23) ++#define REG_SC_BK25_24_L _PK_L_(0x25, 0x24) ++#define REG_SC_BK25_24_H _PK_H_(0x25, 0x24) ++#define REG_SC_BK25_25_L _PK_L_(0x25, 0x25) ++#define REG_SC_BK25_25_H _PK_H_(0x25, 0x25) ++#define REG_SC_BK25_26_L _PK_L_(0x25, 0x26) ++#define REG_SC_BK25_26_H _PK_H_(0x25, 0x26) ++#define REG_SC_BK25_27_L _PK_L_(0x25, 0x27) ++#define REG_SC_BK25_27_H _PK_H_(0x25, 0x27) ++#define REG_SC_BK25_28_L _PK_L_(0x25, 0x28) ++#define REG_SC_BK25_28_H _PK_H_(0x25, 0x28) ++#define REG_SC_BK25_29_L _PK_L_(0x25, 0x29) ++#define REG_SC_BK25_29_H _PK_H_(0x25, 0x29) ++#define REG_SC_BK25_2A_L _PK_L_(0x25, 0x2A) ++#define REG_SC_BK25_2A_H _PK_H_(0x25, 0x2A) ++#define REG_SC_BK25_2B_L _PK_L_(0x25, 0x2B) ++#define REG_SC_BK25_2B_H _PK_H_(0x25, 0x2B) ++#define REG_SC_BK25_2C_L _PK_L_(0x25, 0x2C) ++#define REG_SC_BK25_2C_H _PK_H_(0x25, 0x2C) ++#define REG_SC_BK25_2D_L _PK_L_(0x25, 0x2D) ++#define REG_SC_BK25_2D_H _PK_H_(0x25, 0x2D) ++#define REG_SC_BK25_2E_L _PK_L_(0x25, 0x2E) ++#define REG_SC_BK25_2E_H _PK_H_(0x25, 0x2E) ++#define REG_SC_BK25_2F_L _PK_L_(0x25, 0x2F) ++#define REG_SC_BK25_2F_H _PK_H_(0x25, 0x2F) ++#define REG_SC_BK25_30_L _PK_L_(0x25, 0x30) ++#define REG_SC_BK25_30_H _PK_H_(0x25, 0x30) ++#define REG_SC_BK25_31_L _PK_L_(0x25, 0x31) ++#define REG_SC_BK25_31_H _PK_H_(0x25, 0x31) ++#define REG_SC_BK25_32_L _PK_L_(0x25, 0x32) ++#define REG_SC_BK25_32_H _PK_H_(0x25, 0x32) ++#define REG_SC_BK25_33_L _PK_L_(0x25, 0x33) ++#define REG_SC_BK25_33_H _PK_H_(0x25, 0x33) ++#define REG_SC_BK25_34_L _PK_L_(0x25, 0x34) ++#define REG_SC_BK25_34_H _PK_H_(0x25, 0x34) ++#define REG_SC_BK25_35_L _PK_L_(0x25, 0x35) ++#define REG_SC_BK25_35_H _PK_H_(0x25, 0x35) ++#define REG_SC_BK25_36_L _PK_L_(0x25, 0x36) ++#define REG_SC_BK25_36_H _PK_H_(0x25, 0x36) ++#define REG_SC_BK25_37_L _PK_L_(0x25, 0x37) ++#define REG_SC_BK25_37_H _PK_H_(0x25, 0x37) ++#define REG_SC_BK25_38_L _PK_L_(0x25, 0x38) ++#define REG_SC_BK25_38_H _PK_H_(0x25, 0x38) ++#define REG_SC_BK25_39_L _PK_L_(0x25, 0x39) ++#define REG_SC_BK25_39_H _PK_H_(0x25, 0x39) ++#define REG_SC_BK25_3A_L _PK_L_(0x25, 0x3A) ++#define REG_SC_BK25_3A_H _PK_H_(0x25, 0x3A) ++#define REG_SC_BK25_3B_L _PK_L_(0x25, 0x3B) ++#define REG_SC_BK25_3B_H _PK_H_(0x25, 0x3B) ++#define REG_SC_BK25_3C_L _PK_L_(0x25, 0x3C) ++#define REG_SC_BK25_3C_H _PK_H_(0x25, 0x3C) ++#define REG_SC_BK25_3D_L _PK_L_(0x25, 0x3D) ++#define REG_SC_BK25_3D_H _PK_H_(0x25, 0x3D) ++#define REG_SC_BK25_3E_L _PK_L_(0x25, 0x3E) ++#define REG_SC_BK25_3E_H _PK_H_(0x25, 0x3E) ++#define REG_SC_BK25_3F_L _PK_L_(0x25, 0x3F) ++#define REG_SC_BK25_3F_H _PK_H_(0x25, 0x3F) ++#define REG_SC_BK25_40_L _PK_L_(0x25, 0x40) ++#define REG_SC_BK25_40_H _PK_H_(0x25, 0x40) ++#define REG_SC_BK25_41_L _PK_L_(0x25, 0x41) ++#define REG_SC_BK25_41_H _PK_H_(0x25, 0x41) ++#define REG_SC_BK25_42_L _PK_L_(0x25, 0x42) ++#define REG_SC_BK25_42_H _PK_H_(0x25, 0x42) ++#define REG_SC_BK25_43_L _PK_L_(0x25, 0x43) ++#define REG_SC_BK25_43_H _PK_H_(0x25, 0x43) ++#define REG_SC_BK25_44_L _PK_L_(0x25, 0x44) ++#define REG_SC_BK25_44_H _PK_H_(0x25, 0x44) ++#define REG_SC_BK25_45_L _PK_L_(0x25, 0x45) ++#define REG_SC_BK25_45_H _PK_H_(0x25, 0x45) ++#define REG_SC_BK25_46_L _PK_L_(0x25, 0x46) ++#define REG_SC_BK25_46_H _PK_H_(0x25, 0x46) ++#define REG_SC_BK25_47_L _PK_L_(0x25, 0x47) ++#define REG_SC_BK25_47_H _PK_H_(0x25, 0x47) ++#define REG_SC_BK25_48_L _PK_L_(0x25, 0x48) ++#define REG_SC_BK25_48_H _PK_H_(0x25, 0x48) ++#define REG_SC_BK25_49_L _PK_L_(0x25, 0x49) ++#define REG_SC_BK25_49_H _PK_H_(0x25, 0x49) ++#define REG_SC_BK25_4A_L _PK_L_(0x25, 0x4A) ++#define REG_SC_BK25_4A_H _PK_H_(0x25, 0x4A) ++#define REG_SC_BK25_4B_L _PK_L_(0x25, 0x4B) ++#define REG_SC_BK25_4B_H _PK_H_(0x25, 0x4B) ++#define REG_SC_BK25_4C_L _PK_L_(0x25, 0x4C) ++#define REG_SC_BK25_4C_H _PK_H_(0x25, 0x4C) ++#define REG_SC_BK25_4D_L _PK_L_(0x25, 0x4D) ++#define REG_SC_BK25_4D_H _PK_H_(0x25, 0x4D) ++#define REG_SC_BK25_4E_L _PK_L_(0x25, 0x4E) ++#define REG_SC_BK25_4E_H _PK_H_(0x25, 0x4E) ++#define REG_SC_BK25_4F_L _PK_L_(0x25, 0x4F) ++#define REG_SC_BK25_4F_H _PK_H_(0x25, 0x4F) ++#define REG_SC_BK25_50_L _PK_L_(0x25, 0x50) ++#define REG_SC_BK25_50_H _PK_H_(0x25, 0x50) ++#define REG_SC_BK25_51_L _PK_L_(0x25, 0x51) ++#define REG_SC_BK25_51_H _PK_H_(0x25, 0x51) ++#define REG_SC_BK25_52_L _PK_L_(0x25, 0x52) ++#define REG_SC_BK25_52_H _PK_H_(0x25, 0x52) ++#define REG_SC_BK25_53_L _PK_L_(0x25, 0x53) ++#define REG_SC_BK25_53_H _PK_H_(0x25, 0x53) ++#define REG_SC_BK25_54_L _PK_L_(0x25, 0x54) ++#define REG_SC_BK25_54_H _PK_H_(0x25, 0x54) ++#define REG_SC_BK25_55_L _PK_L_(0x25, 0x55) ++#define REG_SC_BK25_55_H _PK_H_(0x25, 0x55) ++#define REG_SC_BK25_56_L _PK_L_(0x25, 0x56) ++#define REG_SC_BK25_56_H _PK_H_(0x25, 0x56) ++#define REG_SC_BK25_57_L _PK_L_(0x25, 0x57) ++#define REG_SC_BK25_57_H _PK_H_(0x25, 0x57) ++#define REG_SC_BK25_58_L _PK_L_(0x25, 0x58) ++#define REG_SC_BK25_58_H _PK_H_(0x25, 0x58) ++#define REG_SC_BK25_59_L _PK_L_(0x25, 0x59) ++#define REG_SC_BK25_59_H _PK_H_(0x25, 0x59) ++#define REG_SC_BK25_5A_L _PK_L_(0x25, 0x5A) ++#define REG_SC_BK25_5A_H _PK_H_(0x25, 0x5A) ++#define REG_SC_BK25_5B_L _PK_L_(0x25, 0x5B) ++#define REG_SC_BK25_5B_H _PK_H_(0x25, 0x5B) ++#define REG_SC_BK25_5C_L _PK_L_(0x25, 0x5C) ++#define REG_SC_BK25_5C_H _PK_H_(0x25, 0x5C) ++#define REG_SC_BK25_5D_L _PK_L_(0x25, 0x5D) ++#define REG_SC_BK25_5D_H _PK_H_(0x25, 0x5D) ++#define REG_SC_BK25_5E_L _PK_L_(0x25, 0x5E) ++#define REG_SC_BK25_5E_H _PK_H_(0x25, 0x5E) ++#define REG_SC_BK25_5F_L _PK_L_(0x25, 0x5F) ++#define REG_SC_BK25_5F_H _PK_H_(0x25, 0x5F) ++#define REG_SC_BK25_60_L _PK_L_(0x25, 0x60) ++#define REG_SC_BK25_60_H _PK_H_(0x25, 0x60) ++#define REG_SC_BK25_61_L _PK_L_(0x25, 0x61) ++#define REG_SC_BK25_61_H _PK_H_(0x25, 0x61) ++#define REG_SC_BK25_62_L _PK_L_(0x25, 0x62) ++#define REG_SC_BK25_62_H _PK_H_(0x25, 0x62) ++#define REG_SC_BK25_63_L _PK_L_(0x25, 0x63) ++#define REG_SC_BK25_63_H _PK_H_(0x25, 0x63) ++#define REG_SC_BK25_64_L _PK_L_(0x25, 0x64) ++#define REG_SC_BK25_64_H _PK_H_(0x25, 0x64) ++#define REG_SC_BK25_65_L _PK_L_(0x25, 0x65) ++#define REG_SC_BK25_65_H _PK_H_(0x25, 0x65) ++#define REG_SC_BK25_66_L _PK_L_(0x25, 0x66) ++#define REG_SC_BK25_66_H _PK_H_(0x25, 0x66) ++#define REG_SC_BK25_67_L _PK_L_(0x25, 0x67) ++#define REG_SC_BK25_67_H _PK_H_(0x25, 0x67) ++#define REG_SC_BK25_68_L _PK_L_(0x25, 0x68) ++#define REG_SC_BK25_68_H _PK_H_(0x25, 0x68) ++#define REG_SC_BK25_69_L _PK_L_(0x25, 0x69) ++#define REG_SC_BK25_69_H _PK_H_(0x25, 0x69) ++#define REG_SC_BK25_6A_L _PK_L_(0x25, 0x6A) ++#define REG_SC_BK25_6A_H _PK_H_(0x25, 0x6A) ++#define REG_SC_BK25_6B_L _PK_L_(0x25, 0x6B) ++#define REG_SC_BK25_6B_H _PK_H_(0x25, 0x6B) ++#define REG_SC_BK25_6C_L _PK_L_(0x25, 0x6C) ++#define REG_SC_BK25_6C_H _PK_H_(0x25, 0x6C) ++#define REG_SC_BK25_6D_L _PK_L_(0x25, 0x6D) ++#define REG_SC_BK25_6D_H _PK_H_(0x25, 0x6D) ++#define REG_SC_BK25_6E_L _PK_L_(0x25, 0x6E) ++#define REG_SC_BK25_6E_H _PK_H_(0x25, 0x6E) ++#define REG_SC_BK25_6F_L _PK_L_(0x25, 0x6F) ++#define REG_SC_BK25_6F_H _PK_H_(0x25, 0x6F) ++#define REG_SC_BK25_70_L _PK_L_(0x25, 0x70) ++#define REG_SC_BK25_70_H _PK_H_(0x25, 0x70) ++#define REG_SC_BK25_71_L _PK_L_(0x25, 0x71) ++#define REG_SC_BK25_71_H _PK_H_(0x25, 0x71) ++#define REG_SC_BK25_72_L _PK_L_(0x25, 0x72) ++#define REG_SC_BK25_72_H _PK_H_(0x25, 0x72) ++#define REG_SC_BK25_73_L _PK_L_(0x25, 0x73) ++#define REG_SC_BK25_73_H _PK_H_(0x25, 0x73) ++#define REG_SC_BK25_74_L _PK_L_(0x25, 0x74) ++#define REG_SC_BK25_74_H _PK_H_(0x25, 0x74) ++#define REG_SC_BK25_75_L _PK_L_(0x25, 0x75) ++#define REG_SC_BK25_75_H _PK_H_(0x25, 0x75) ++#define REG_SC_BK25_76_L _PK_L_(0x25, 0x76) ++#define REG_SC_BK25_76_H _PK_H_(0x25, 0x76) ++#define REG_SC_BK25_77_L _PK_L_(0x25, 0x77) ++#define REG_SC_BK25_77_H _PK_H_(0x25, 0x77) ++#define REG_SC_BK25_78_L _PK_L_(0x25, 0x78) ++#define REG_SC_BK25_78_H _PK_H_(0x25, 0x78) ++#define REG_SC_BK25_79_L _PK_L_(0x25, 0x79) ++#define REG_SC_BK25_79_H _PK_H_(0x25, 0x79) ++#define REG_SC_BK25_7A_L _PK_L_(0x25, 0x7A) ++#define REG_SC_BK25_7A_H _PK_H_(0x25, 0x7A) ++#define REG_SC_BK25_7B_L _PK_L_(0x25, 0x7B) ++#define REG_SC_BK25_7B_H _PK_H_(0x25, 0x7B) ++#define REG_SC_BK25_7C_L _PK_L_(0x25, 0x7C) ++#define REG_SC_BK25_7C_H _PK_H_(0x25, 0x7C) ++#define REG_SC_BK25_7D_L _PK_L_(0x25, 0x7D) ++#define REG_SC_BK25_7D_H _PK_H_(0x25, 0x7D) ++#define REG_SC_BK25_7E_L _PK_L_(0x25, 0x7E) ++#define REG_SC_BK25_7E_H _PK_H_(0x25, 0x7E) ++#define REG_SC_BK25_7F_L _PK_L_(0x25, 0x7F) ++#define REG_SC_BK25_7F_H _PK_H_(0x25, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK26_00_L _PK_L_(0x26, 0x00) ++#define REG_SC_BK26_00_H _PK_H_(0x26, 0x00) ++#define REG_SC_BK26_01_L _PK_L_(0x26, 0x01) ++#define REG_SC_BK26_01_H _PK_H_(0x26, 0x01) ++#define REG_SC_BK26_02_L _PK_L_(0x26, 0x02) ++#define REG_SC_BK26_02_H _PK_H_(0x26, 0x02) ++#define REG_SC_BK26_03_L _PK_L_(0x26, 0x03) ++#define REG_SC_BK26_03_H _PK_H_(0x26, 0x03) ++#define REG_SC_BK26_04_L _PK_L_(0x26, 0x04) ++#define REG_SC_BK26_04_H _PK_H_(0x26, 0x04) ++#define REG_SC_BK26_05_L _PK_L_(0x26, 0x05) ++#define REG_SC_BK26_05_H _PK_H_(0x26, 0x05) ++#define REG_SC_BK26_06_L _PK_L_(0x26, 0x06) ++#define REG_SC_BK26_06_H _PK_H_(0x26, 0x06) ++#define REG_SC_BK26_07_L _PK_L_(0x26, 0x07) ++#define REG_SC_BK26_07_H _PK_H_(0x26, 0x07) ++#define REG_SC_BK26_08_L _PK_L_(0x26, 0x08) ++#define REG_SC_BK26_08_H _PK_H_(0x26, 0x08) ++#define REG_SC_BK26_09_L _PK_L_(0x26, 0x09) ++#define REG_SC_BK26_09_H _PK_H_(0x26, 0x09) ++#define REG_SC_BK26_0A_L _PK_L_(0x26, 0x0A) ++#define REG_SC_BK26_0A_H _PK_H_(0x26, 0x0A) ++#define REG_SC_BK26_0B_L _PK_L_(0x26, 0x0B) ++#define REG_SC_BK26_0B_H _PK_H_(0x26, 0x0B) ++#define REG_SC_BK26_0C_L _PK_L_(0x26, 0x0C) ++#define REG_SC_BK26_0C_H _PK_H_(0x26, 0x0C) ++#define REG_SC_BK26_0D_L _PK_L_(0x26, 0x0D) ++#define REG_SC_BK26_0D_H _PK_H_(0x26, 0x0D) ++#define REG_SC_BK26_0E_L _PK_L_(0x26, 0x0E) ++#define REG_SC_BK26_0E_H _PK_H_(0x26, 0x0E) ++#define REG_SC_BK26_0F_L _PK_L_(0x26, 0x0F) ++#define REG_SC_BK26_0F_H _PK_H_(0x26, 0x0F) ++#define REG_SC_BK26_10_L _PK_L_(0x26, 0x10) ++#define REG_SC_BK26_10_H _PK_H_(0x26, 0x10) ++#define REG_SC_BK26_11_L _PK_L_(0x26, 0x11) ++#define REG_SC_BK26_11_H _PK_H_(0x26, 0x11) ++#define REG_SC_BK26_12_L _PK_L_(0x26, 0x12) ++#define REG_SC_BK26_12_H _PK_H_(0x26, 0x12) ++#define REG_SC_BK26_13_L _PK_L_(0x26, 0x13) ++#define REG_SC_BK26_13_H _PK_H_(0x26, 0x13) ++#define REG_SC_BK26_14_L _PK_L_(0x26, 0x14) ++#define REG_SC_BK26_14_H _PK_H_(0x26, 0x14) ++#define REG_SC_BK26_15_L _PK_L_(0x26, 0x15) ++#define REG_SC_BK26_15_H _PK_H_(0x26, 0x15) ++#define REG_SC_BK26_16_L _PK_L_(0x26, 0x16) ++#define REG_SC_BK26_16_H _PK_H_(0x26, 0x16) ++#define REG_SC_BK26_17_L _PK_L_(0x26, 0x17) ++#define REG_SC_BK26_17_H _PK_H_(0x26, 0x17) ++#define REG_SC_BK26_18_L _PK_L_(0x26, 0x18) ++#define REG_SC_BK26_18_H _PK_H_(0x26, 0x18) ++#define REG_SC_BK26_19_L _PK_L_(0x26, 0x19) ++#define REG_SC_BK26_19_H _PK_H_(0x26, 0x19) ++#define REG_SC_BK26_1A_L _PK_L_(0x26, 0x1A) ++#define REG_SC_BK26_1A_H _PK_H_(0x26, 0x1A) ++#define REG_SC_BK26_1B_L _PK_L_(0x26, 0x1B) ++#define REG_SC_BK26_1B_H _PK_H_(0x26, 0x1B) ++#define REG_SC_BK26_1C_L _PK_L_(0x26, 0x1C) ++#define REG_SC_BK26_1C_H _PK_H_(0x26, 0x1C) ++#define REG_SC_BK26_1D_L _PK_L_(0x26, 0x1D) ++#define REG_SC_BK26_1D_H _PK_H_(0x26, 0x1D) ++#define REG_SC_BK26_1E_L _PK_L_(0x26, 0x1E) ++#define REG_SC_BK26_1E_H _PK_H_(0x26, 0x1E) ++#define REG_SC_BK26_1F_L _PK_L_(0x26, 0x1F) ++#define REG_SC_BK26_1F_H _PK_H_(0x26, 0x1F) ++#define REG_SC_BK26_20_L _PK_L_(0x26, 0x20) ++#define REG_SC_BK26_20_H _PK_H_(0x26, 0x20) ++#define REG_SC_BK26_21_L _PK_L_(0x26, 0x21) ++#define REG_SC_BK26_21_H _PK_H_(0x26, 0x21) ++#define REG_SC_BK26_22_L _PK_L_(0x26, 0x22) ++#define REG_SC_BK26_22_H _PK_H_(0x26, 0x22) ++#define REG_SC_BK26_23_L _PK_L_(0x26, 0x23) ++#define REG_SC_BK26_23_H _PK_H_(0x26, 0x23) ++#define REG_SC_BK26_24_L _PK_L_(0x26, 0x24) ++#define REG_SC_BK26_24_H _PK_H_(0x26, 0x24) ++#define REG_SC_BK26_25_L _PK_L_(0x26, 0x25) ++#define REG_SC_BK26_25_H _PK_H_(0x26, 0x25) ++#define REG_SC_BK26_26_L _PK_L_(0x26, 0x26) ++#define REG_SC_BK26_26_H _PK_H_(0x26, 0x26) ++#define REG_SC_BK26_27_L _PK_L_(0x26, 0x27) ++#define REG_SC_BK26_27_H _PK_H_(0x26, 0x27) ++#define REG_SC_BK26_28_L _PK_L_(0x26, 0x28) ++#define REG_SC_BK26_28_H _PK_H_(0x26, 0x28) ++#define REG_SC_BK26_29_L _PK_L_(0x26, 0x29) ++#define REG_SC_BK26_29_H _PK_H_(0x26, 0x29) ++#define REG_SC_BK26_2A_L _PK_L_(0x26, 0x2A) ++#define REG_SC_BK26_2A_H _PK_H_(0x26, 0x2A) ++#define REG_SC_BK26_2B_L _PK_L_(0x26, 0x2B) ++#define REG_SC_BK26_2B_H _PK_H_(0x26, 0x2B) ++#define REG_SC_BK26_2C_L _PK_L_(0x26, 0x2C) ++#define REG_SC_BK26_2C_H _PK_H_(0x26, 0x2C) ++#define REG_SC_BK26_2D_L _PK_L_(0x26, 0x2D) ++#define REG_SC_BK26_2D_H _PK_H_(0x26, 0x2D) ++#define REG_SC_BK26_2E_L _PK_L_(0x26, 0x2E) ++#define REG_SC_BK26_2E_H _PK_H_(0x26, 0x2E) ++#define REG_SC_BK26_2F_L _PK_L_(0x26, 0x2F) ++#define REG_SC_BK26_2F_H _PK_H_(0x26, 0x2F) ++#define REG_SC_BK26_30_L _PK_L_(0x26, 0x30) ++#define REG_SC_BK26_30_H _PK_H_(0x26, 0x30) ++#define REG_SC_BK26_31_L _PK_L_(0x26, 0x31) ++#define REG_SC_BK26_31_H _PK_H_(0x26, 0x31) ++#define REG_SC_BK26_32_L _PK_L_(0x26, 0x32) ++#define REG_SC_BK26_32_H _PK_H_(0x26, 0x32) ++#define REG_SC_BK26_33_L _PK_L_(0x26, 0x33) ++#define REG_SC_BK26_33_H _PK_H_(0x26, 0x33) ++#define REG_SC_BK26_34_L _PK_L_(0x26, 0x34) ++#define REG_SC_BK26_34_H _PK_H_(0x26, 0x34) ++#define REG_SC_BK26_35_L _PK_L_(0x26, 0x35) ++#define REG_SC_BK26_35_H _PK_H_(0x26, 0x35) ++#define REG_SC_BK26_36_L _PK_L_(0x26, 0x36) ++#define REG_SC_BK26_36_H _PK_H_(0x26, 0x36) ++#define REG_SC_BK26_37_L _PK_L_(0x26, 0x37) ++#define REG_SC_BK26_37_H _PK_H_(0x26, 0x37) ++#define REG_SC_BK26_38_L _PK_L_(0x26, 0x38) ++#define REG_SC_BK26_38_H _PK_H_(0x26, 0x38) ++#define REG_SC_BK26_39_L _PK_L_(0x26, 0x39) ++#define REG_SC_BK26_39_H _PK_H_(0x26, 0x39) ++#define REG_SC_BK26_3A_L _PK_L_(0x26, 0x3A) ++#define REG_SC_BK26_3A_H _PK_H_(0x26, 0x3A) ++#define REG_SC_BK26_3B_L _PK_L_(0x26, 0x3B) ++#define REG_SC_BK26_3B_H _PK_H_(0x26, 0x3B) ++#define REG_SC_BK26_3C_L _PK_L_(0x26, 0x3C) ++#define REG_SC_BK26_3C_H _PK_H_(0x26, 0x3C) ++#define REG_SC_BK26_3D_L _PK_L_(0x26, 0x3D) ++#define REG_SC_BK26_3D_H _PK_H_(0x26, 0x3D) ++#define REG_SC_BK26_3E_L _PK_L_(0x26, 0x3E) ++#define REG_SC_BK26_3E_H _PK_H_(0x26, 0x3E) ++#define REG_SC_BK26_3F_L _PK_L_(0x26, 0x3F) ++#define REG_SC_BK26_3F_H _PK_H_(0x26, 0x3F) ++#define REG_SC_BK26_40_L _PK_L_(0x26, 0x40) ++#define REG_SC_BK26_40_H _PK_H_(0x26, 0x40) ++#define REG_SC_BK26_41_L _PK_L_(0x26, 0x41) ++#define REG_SC_BK26_41_H _PK_H_(0x26, 0x41) ++#define REG_SC_BK26_42_L _PK_L_(0x26, 0x42) ++#define REG_SC_BK26_42_H _PK_H_(0x26, 0x42) ++#define REG_SC_BK26_43_L _PK_L_(0x26, 0x43) ++#define REG_SC_BK26_43_H _PK_H_(0x26, 0x43) ++#define REG_SC_BK26_44_L _PK_L_(0x26, 0x44) ++#define REG_SC_BK26_44_H _PK_H_(0x26, 0x44) ++#define REG_SC_BK26_45_L _PK_L_(0x26, 0x45) ++#define REG_SC_BK26_45_H _PK_H_(0x26, 0x45) ++#define REG_SC_BK26_46_L _PK_L_(0x26, 0x46) ++#define REG_SC_BK26_46_H _PK_H_(0x26, 0x46) ++#define REG_SC_BK26_47_L _PK_L_(0x26, 0x47) ++#define REG_SC_BK26_47_H _PK_H_(0x26, 0x47) ++#define REG_SC_BK26_48_L _PK_L_(0x26, 0x48) ++#define REG_SC_BK26_48_H _PK_H_(0x26, 0x48) ++#define REG_SC_BK26_49_L _PK_L_(0x26, 0x49) ++#define REG_SC_BK26_49_H _PK_H_(0x26, 0x49) ++#define REG_SC_BK26_4A_L _PK_L_(0x26, 0x4A) ++#define REG_SC_BK26_4A_H _PK_H_(0x26, 0x4A) ++#define REG_SC_BK26_4B_L _PK_L_(0x26, 0x4B) ++#define REG_SC_BK26_4B_H _PK_H_(0x26, 0x4B) ++#define REG_SC_BK26_4C_L _PK_L_(0x26, 0x4C) ++#define REG_SC_BK26_4C_H _PK_H_(0x26, 0x4C) ++#define REG_SC_BK26_4D_L _PK_L_(0x26, 0x4D) ++#define REG_SC_BK26_4D_H _PK_H_(0x26, 0x4D) ++#define REG_SC_BK26_4E_L _PK_L_(0x26, 0x4E) ++#define REG_SC_BK26_4E_H _PK_H_(0x26, 0x4E) ++#define REG_SC_BK26_4F_L _PK_L_(0x26, 0x4F) ++#define REG_SC_BK26_4F_H _PK_H_(0x26, 0x4F) ++#define REG_SC_BK26_50_L _PK_L_(0x26, 0x50) ++#define REG_SC_BK26_50_H _PK_H_(0x26, 0x50) ++#define REG_SC_BK26_51_L _PK_L_(0x26, 0x51) ++#define REG_SC_BK26_51_H _PK_H_(0x26, 0x51) ++#define REG_SC_BK26_52_L _PK_L_(0x26, 0x52) ++#define REG_SC_BK26_52_H _PK_H_(0x26, 0x52) ++#define REG_SC_BK26_53_L _PK_L_(0x26, 0x53) ++#define REG_SC_BK26_53_H _PK_H_(0x26, 0x53) ++#define REG_SC_BK26_54_L _PK_L_(0x26, 0x54) ++#define REG_SC_BK26_54_H _PK_H_(0x26, 0x54) ++#define REG_SC_BK26_55_L _PK_L_(0x26, 0x55) ++#define REG_SC_BK26_55_H _PK_H_(0x26, 0x55) ++#define REG_SC_BK26_56_L _PK_L_(0x26, 0x56) ++#define REG_SC_BK26_56_H _PK_H_(0x26, 0x56) ++#define REG_SC_BK26_57_L _PK_L_(0x26, 0x57) ++#define REG_SC_BK26_57_H _PK_H_(0x26, 0x57) ++#define REG_SC_BK26_58_L _PK_L_(0x26, 0x58) ++#define REG_SC_BK26_58_H _PK_H_(0x26, 0x58) ++#define REG_SC_BK26_59_L _PK_L_(0x26, 0x59) ++#define REG_SC_BK26_59_H _PK_H_(0x26, 0x59) ++#define REG_SC_BK26_5A_L _PK_L_(0x26, 0x5A) ++#define REG_SC_BK26_5A_H _PK_H_(0x26, 0x5A) ++#define REG_SC_BK26_5B_L _PK_L_(0x26, 0x5B) ++#define REG_SC_BK26_5B_H _PK_H_(0x26, 0x5B) ++#define REG_SC_BK26_5C_L _PK_L_(0x26, 0x5C) ++#define REG_SC_BK26_5C_H _PK_H_(0x26, 0x5C) ++#define REG_SC_BK26_5D_L _PK_L_(0x26, 0x5D) ++#define REG_SC_BK26_5D_H _PK_H_(0x26, 0x5D) ++#define REG_SC_BK26_5E_L _PK_L_(0x26, 0x5E) ++#define REG_SC_BK26_5E_H _PK_H_(0x26, 0x5E) ++#define REG_SC_BK26_5F_L _PK_L_(0x26, 0x5F) ++#define REG_SC_BK26_5F_H _PK_H_(0x26, 0x5F) ++#define REG_SC_BK26_60_L _PK_L_(0x26, 0x60) ++#define REG_SC_BK26_60_H _PK_H_(0x26, 0x60) ++#define REG_SC_BK26_61_L _PK_L_(0x26, 0x61) ++#define REG_SC_BK26_61_H _PK_H_(0x26, 0x61) ++#define REG_SC_BK26_62_L _PK_L_(0x26, 0x62) ++#define REG_SC_BK26_62_H _PK_H_(0x26, 0x62) ++#define REG_SC_BK26_63_L _PK_L_(0x26, 0x63) ++#define REG_SC_BK26_63_H _PK_H_(0x26, 0x63) ++#define REG_SC_BK26_64_L _PK_L_(0x26, 0x64) ++#define REG_SC_BK26_64_H _PK_H_(0x26, 0x64) ++#define REG_SC_BK26_65_L _PK_L_(0x26, 0x65) ++#define REG_SC_BK26_65_H _PK_H_(0x26, 0x65) ++#define REG_SC_BK26_66_L _PK_L_(0x26, 0x66) ++#define REG_SC_BK26_66_H _PK_H_(0x26, 0x66) ++#define REG_SC_BK26_67_L _PK_L_(0x26, 0x67) ++#define REG_SC_BK26_67_H _PK_H_(0x26, 0x67) ++#define REG_SC_BK26_68_L _PK_L_(0x26, 0x68) ++#define REG_SC_BK26_68_H _PK_H_(0x26, 0x68) ++#define REG_SC_BK26_69_L _PK_L_(0x26, 0x69) ++#define REG_SC_BK26_69_H _PK_H_(0x26, 0x69) ++#define REG_SC_BK26_6A_L _PK_L_(0x26, 0x6A) ++#define REG_SC_BK26_6A_H _PK_H_(0x26, 0x6A) ++#define REG_SC_BK26_6B_L _PK_L_(0x26, 0x6B) ++#define REG_SC_BK26_6B_H _PK_H_(0x26, 0x6B) ++#define REG_SC_BK26_6C_L _PK_L_(0x26, 0x6C) ++#define REG_SC_BK26_6C_H _PK_H_(0x26, 0x6C) ++#define REG_SC_BK26_6D_L _PK_L_(0x26, 0x6D) ++#define REG_SC_BK26_6D_H _PK_H_(0x26, 0x6D) ++#define REG_SC_BK26_6E_L _PK_L_(0x26, 0x6E) ++#define REG_SC_BK26_6E_H _PK_H_(0x26, 0x6E) ++#define REG_SC_BK26_6F_L _PK_L_(0x26, 0x6F) ++#define REG_SC_BK26_6F_H _PK_H_(0x26, 0x6F) ++#define REG_SC_BK26_70_L _PK_L_(0x26, 0x70) ++#define REG_SC_BK26_70_H _PK_H_(0x26, 0x70) ++#define REG_SC_BK26_71_L _PK_L_(0x26, 0x71) ++#define REG_SC_BK26_71_H _PK_H_(0x26, 0x71) ++#define REG_SC_BK26_72_L _PK_L_(0x26, 0x72) ++#define REG_SC_BK26_72_H _PK_H_(0x26, 0x72) ++#define REG_SC_BK26_73_L _PK_L_(0x26, 0x73) ++#define REG_SC_BK26_73_H _PK_H_(0x26, 0x73) ++#define REG_SC_BK26_74_L _PK_L_(0x26, 0x74) ++#define REG_SC_BK26_74_H _PK_H_(0x26, 0x74) ++#define REG_SC_BK26_75_L _PK_L_(0x26, 0x75) ++#define REG_SC_BK26_75_H _PK_H_(0x26, 0x75) ++#define REG_SC_BK26_76_L _PK_L_(0x26, 0x76) ++#define REG_SC_BK26_76_H _PK_H_(0x26, 0x76) ++#define REG_SC_BK26_77_L _PK_L_(0x26, 0x77) ++#define REG_SC_BK26_77_H _PK_H_(0x26, 0x77) ++#define REG_SC_BK26_78_L _PK_L_(0x26, 0x78) ++#define REG_SC_BK26_78_H _PK_H_(0x26, 0x78) ++#define REG_SC_BK26_79_L _PK_L_(0x26, 0x79) ++#define REG_SC_BK26_79_H _PK_H_(0x26, 0x79) ++#define REG_SC_BK26_7A_L _PK_L_(0x26, 0x7A) ++#define REG_SC_BK26_7A_H _PK_H_(0x26, 0x7A) ++#define REG_SC_BK26_7B_L _PK_L_(0x26, 0x7B) ++#define REG_SC_BK26_7B_H _PK_H_(0x26, 0x7B) ++#define REG_SC_BK26_7C_L _PK_L_(0x26, 0x7C) ++#define REG_SC_BK26_7C_H _PK_H_(0x26, 0x7C) ++#define REG_SC_BK26_7D_L _PK_L_(0x26, 0x7D) ++#define REG_SC_BK26_7D_H _PK_H_(0x26, 0x7D) ++#define REG_SC_BK26_7E_L _PK_L_(0x26, 0x7E) ++#define REG_SC_BK26_7E_H _PK_H_(0x26, 0x7E) ++#define REG_SC_BK26_7F_L _PK_L_(0x26, 0x7F) ++#define REG_SC_BK26_7F_H _PK_H_(0x26, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK27_00_L _PK_L_(0x27, 0x00) ++#define REG_SC_BK27_00_H _PK_H_(0x27, 0x00) ++#define REG_SC_BK27_01_L _PK_L_(0x27, 0x01) ++#define REG_SC_BK27_01_H _PK_H_(0x27, 0x01) ++#define REG_SC_BK27_02_L _PK_L_(0x27, 0x02) ++#define REG_SC_BK27_02_H _PK_H_(0x27, 0x02) ++#define REG_SC_BK27_03_L _PK_L_(0x27, 0x03) ++#define REG_SC_BK27_03_H _PK_H_(0x27, 0x03) ++#define REG_SC_BK27_04_L _PK_L_(0x27, 0x04) ++#define REG_SC_BK27_04_H _PK_H_(0x27, 0x04) ++#define REG_SC_BK27_05_L _PK_L_(0x27, 0x05) ++#define REG_SC_BK27_05_H _PK_H_(0x27, 0x05) ++#define REG_SC_BK27_06_L _PK_L_(0x27, 0x06) ++#define REG_SC_BK27_06_H _PK_H_(0x27, 0x06) ++#define REG_SC_BK27_07_L _PK_L_(0x27, 0x07) ++#define REG_SC_BK27_07_H _PK_H_(0x27, 0x07) ++#define REG_SC_BK27_08_L _PK_L_(0x27, 0x08) ++#define REG_SC_BK27_08_H _PK_H_(0x27, 0x08) ++#define REG_SC_BK27_09_L _PK_L_(0x27, 0x09) ++#define REG_SC_BK27_09_H _PK_H_(0x27, 0x09) ++#define REG_SC_BK27_0A_L _PK_L_(0x27, 0x0A) ++#define REG_SC_BK27_0A_H _PK_H_(0x27, 0x0A) ++#define REG_SC_BK27_0B_L _PK_L_(0x27, 0x0B) ++#define REG_SC_BK27_0B_H _PK_H_(0x27, 0x0B) ++#define REG_SC_BK27_0C_L _PK_L_(0x27, 0x0C) ++#define REG_SC_BK27_0C_H _PK_H_(0x27, 0x0C) ++#define REG_SC_BK27_0D_L _PK_L_(0x27, 0x0D) ++#define REG_SC_BK27_0D_H _PK_H_(0x27, 0x0D) ++#define REG_SC_BK27_0E_L _PK_L_(0x27, 0x0E) ++#define REG_SC_BK27_0E_H _PK_H_(0x27, 0x0E) ++#define REG_SC_BK27_0F_L _PK_L_(0x27, 0x0F) ++#define REG_SC_BK27_0F_H _PK_H_(0x27, 0x0F) ++#define REG_SC_BK27_10_L _PK_L_(0x27, 0x10) ++#define REG_SC_BK27_10_H _PK_H_(0x27, 0x10) ++#define REG_SC_BK27_11_L _PK_L_(0x27, 0x11) ++#define REG_SC_BK27_11_H _PK_H_(0x27, 0x11) ++#define REG_SC_BK27_12_L _PK_L_(0x27, 0x12) ++#define REG_SC_BK27_12_H _PK_H_(0x27, 0x12) ++#define REG_SC_BK27_13_L _PK_L_(0x27, 0x13) ++#define REG_SC_BK27_13_H _PK_H_(0x27, 0x13) ++#define REG_SC_BK27_14_L _PK_L_(0x27, 0x14) ++#define REG_SC_BK27_14_H _PK_H_(0x27, 0x14) ++#define REG_SC_BK27_15_L _PK_L_(0x27, 0x15) ++#define REG_SC_BK27_15_H _PK_H_(0x27, 0x15) ++#define REG_SC_BK27_16_L _PK_L_(0x27, 0x16) ++#define REG_SC_BK27_16_H _PK_H_(0x27, 0x16) ++#define REG_SC_BK27_17_L _PK_L_(0x27, 0x17) ++#define REG_SC_BK27_17_H _PK_H_(0x27, 0x17) ++#define REG_SC_BK27_18_L _PK_L_(0x27, 0x18) ++#define REG_SC_BK27_18_H _PK_H_(0x27, 0x18) ++#define REG_SC_BK27_19_L _PK_L_(0x27, 0x19) ++#define REG_SC_BK27_19_H _PK_H_(0x27, 0x19) ++#define REG_SC_BK27_1A_L _PK_L_(0x27, 0x1A) ++#define REG_SC_BK27_1A_H _PK_H_(0x27, 0x1A) ++#define REG_SC_BK27_1B_L _PK_L_(0x27, 0x1B) ++#define REG_SC_BK27_1B_H _PK_H_(0x27, 0x1B) ++#define REG_SC_BK27_1C_L _PK_L_(0x27, 0x1C) ++#define REG_SC_BK27_1C_H _PK_H_(0x27, 0x1C) ++#define REG_SC_BK27_1D_L _PK_L_(0x27, 0x1D) ++#define REG_SC_BK27_1D_H _PK_H_(0x27, 0x1D) ++#define REG_SC_BK27_1E_L _PK_L_(0x27, 0x1E) ++#define REG_SC_BK27_1E_H _PK_H_(0x27, 0x1E) ++#define REG_SC_BK27_1F_L _PK_L_(0x27, 0x1F) ++#define REG_SC_BK27_1F_H _PK_H_(0x27, 0x1F) ++#define REG_SC_BK27_20_L _PK_L_(0x27, 0x20) ++#define REG_SC_BK27_20_H _PK_H_(0x27, 0x20) ++#define REG_SC_BK27_21_L _PK_L_(0x27, 0x21) ++#define REG_SC_BK27_21_H _PK_H_(0x27, 0x21) ++#define REG_SC_BK27_22_L _PK_L_(0x27, 0x22) ++#define REG_SC_BK27_22_H _PK_H_(0x27, 0x22) ++#define REG_SC_BK27_23_L _PK_L_(0x27, 0x23) ++#define REG_SC_BK27_23_H _PK_H_(0x27, 0x23) ++#define REG_SC_BK27_24_L _PK_L_(0x27, 0x24) ++#define REG_SC_BK27_24_H _PK_H_(0x27, 0x24) ++#define REG_SC_BK27_25_L _PK_L_(0x27, 0x25) ++#define REG_SC_BK27_25_H _PK_H_(0x27, 0x25) ++#define REG_SC_BK27_26_L _PK_L_(0x27, 0x26) ++#define REG_SC_BK27_26_H _PK_H_(0x27, 0x26) ++#define REG_SC_BK27_27_L _PK_L_(0x27, 0x27) ++#define REG_SC_BK27_27_H _PK_H_(0x27, 0x27) ++#define REG_SC_BK27_28_L _PK_L_(0x27, 0x28) ++#define REG_SC_BK27_28_H _PK_H_(0x27, 0x28) ++#define REG_SC_BK27_29_L _PK_L_(0x27, 0x29) ++#define REG_SC_BK27_29_H _PK_H_(0x27, 0x29) ++#define REG_SC_BK27_2A_L _PK_L_(0x27, 0x2A) ++#define REG_SC_BK27_2A_H _PK_H_(0x27, 0x2A) ++#define REG_SC_BK27_2B_L _PK_L_(0x27, 0x2B) ++#define REG_SC_BK27_2B_H _PK_H_(0x27, 0x2B) ++#define REG_SC_BK27_2C_L _PK_L_(0x27, 0x2C) ++#define REG_SC_BK27_2C_H _PK_H_(0x27, 0x2C) ++#define REG_SC_BK27_2D_L _PK_L_(0x27, 0x2D) ++#define REG_SC_BK27_2D_H _PK_H_(0x27, 0x2D) ++#define REG_SC_BK27_2E_L _PK_L_(0x27, 0x2E) ++#define REG_SC_BK27_2E_H _PK_H_(0x27, 0x2E) ++#define REG_SC_BK27_2F_L _PK_L_(0x27, 0x2F) ++#define REG_SC_BK27_2F_H _PK_H_(0x27, 0x2F) ++#define REG_SC_BK27_30_L _PK_L_(0x27, 0x30) ++#define REG_SC_BK27_30_H _PK_H_(0x27, 0x30) ++#define REG_SC_BK27_31_L _PK_L_(0x27, 0x31) ++#define REG_SC_BK27_31_H _PK_H_(0x27, 0x31) ++#define REG_SC_BK27_32_L _PK_L_(0x27, 0x32) ++#define REG_SC_BK27_32_H _PK_H_(0x27, 0x32) ++#define REG_SC_BK27_33_L _PK_L_(0x27, 0x33) ++#define REG_SC_BK27_33_H _PK_H_(0x27, 0x33) ++#define REG_SC_BK27_34_L _PK_L_(0x27, 0x34) ++#define REG_SC_BK27_34_H _PK_H_(0x27, 0x34) ++#define REG_SC_BK27_35_L _PK_L_(0x27, 0x35) ++#define REG_SC_BK27_35_H _PK_H_(0x27, 0x35) ++#define REG_SC_BK27_36_L _PK_L_(0x27, 0x36) ++#define REG_SC_BK27_36_H _PK_H_(0x27, 0x36) ++#define REG_SC_BK27_37_L _PK_L_(0x27, 0x37) ++#define REG_SC_BK27_37_H _PK_H_(0x27, 0x37) ++#define REG_SC_BK27_38_L _PK_L_(0x27, 0x38) ++#define REG_SC_BK27_38_H _PK_H_(0x27, 0x38) ++#define REG_SC_BK27_39_L _PK_L_(0x27, 0x39) ++#define REG_SC_BK27_39_H _PK_H_(0x27, 0x39) ++#define REG_SC_BK27_3A_L _PK_L_(0x27, 0x3A) ++#define REG_SC_BK27_3A_H _PK_H_(0x27, 0x3A) ++#define REG_SC_BK27_3B_L _PK_L_(0x27, 0x3B) ++#define REG_SC_BK27_3B_H _PK_H_(0x27, 0x3B) ++#define REG_SC_BK27_3C_L _PK_L_(0x27, 0x3C) ++#define REG_SC_BK27_3C_H _PK_H_(0x27, 0x3C) ++#define REG_SC_BK27_3D_L _PK_L_(0x27, 0x3D) ++#define REG_SC_BK27_3D_H _PK_H_(0x27, 0x3D) ++#define REG_SC_BK27_3E_L _PK_L_(0x27, 0x3E) ++#define REG_SC_BK27_3E_H _PK_H_(0x27, 0x3E) ++#define REG_SC_BK27_3F_L _PK_L_(0x27, 0x3F) ++#define REG_SC_BK27_3F_H _PK_H_(0x27, 0x3F) ++#define REG_SC_BK27_40_L _PK_L_(0x27, 0x40) ++#define REG_SC_BK27_40_H _PK_H_(0x27, 0x40) ++#define REG_SC_BK27_41_L _PK_L_(0x27, 0x41) ++#define REG_SC_BK27_41_H _PK_H_(0x27, 0x41) ++#define REG_SC_BK27_42_L _PK_L_(0x27, 0x42) ++#define REG_SC_BK27_42_H _PK_H_(0x27, 0x42) ++#define REG_SC_BK27_43_L _PK_L_(0x27, 0x43) ++#define REG_SC_BK27_43_H _PK_H_(0x27, 0x43) ++#define REG_SC_BK27_44_L _PK_L_(0x27, 0x44) ++#define REG_SC_BK27_44_H _PK_H_(0x27, 0x44) ++#define REG_SC_BK27_45_L _PK_L_(0x27, 0x45) ++#define REG_SC_BK27_45_H _PK_H_(0x27, 0x45) ++#define REG_SC_BK27_46_L _PK_L_(0x27, 0x46) ++#define REG_SC_BK27_46_H _PK_H_(0x27, 0x46) ++#define REG_SC_BK27_47_L _PK_L_(0x27, 0x47) ++#define REG_SC_BK27_47_H _PK_H_(0x27, 0x47) ++#define REG_SC_BK27_48_L _PK_L_(0x27, 0x48) ++#define REG_SC_BK27_48_H _PK_H_(0x27, 0x48) ++#define REG_SC_BK27_49_L _PK_L_(0x27, 0x49) ++#define REG_SC_BK27_49_H _PK_H_(0x27, 0x49) ++#define REG_SC_BK27_4A_L _PK_L_(0x27, 0x4A) ++#define REG_SC_BK27_4A_H _PK_H_(0x27, 0x4A) ++#define REG_SC_BK27_4B_L _PK_L_(0x27, 0x4B) ++#define REG_SC_BK27_4B_H _PK_H_(0x27, 0x4B) ++#define REG_SC_BK27_4C_L _PK_L_(0x27, 0x4C) ++#define REG_SC_BK27_4C_H _PK_H_(0x27, 0x4C) ++#define REG_SC_BK27_4D_L _PK_L_(0x27, 0x4D) ++#define REG_SC_BK27_4D_H _PK_H_(0x27, 0x4D) ++#define REG_SC_BK27_4E_L _PK_L_(0x27, 0x4E) ++#define REG_SC_BK27_4E_H _PK_H_(0x27, 0x4E) ++#define REG_SC_BK27_4F_L _PK_L_(0x27, 0x4F) ++#define REG_SC_BK27_4F_H _PK_H_(0x27, 0x4F) ++#define REG_SC_BK27_50_L _PK_L_(0x27, 0x50) ++#define REG_SC_BK27_50_H _PK_H_(0x27, 0x50) ++#define REG_SC_BK27_51_L _PK_L_(0x27, 0x51) ++#define REG_SC_BK27_51_H _PK_H_(0x27, 0x51) ++#define REG_SC_BK27_52_L _PK_L_(0x27, 0x52) ++#define REG_SC_BK27_52_H _PK_H_(0x27, 0x52) ++#define REG_SC_BK27_53_L _PK_L_(0x27, 0x53) ++#define REG_SC_BK27_53_H _PK_H_(0x27, 0x53) ++#define REG_SC_BK27_54_L _PK_L_(0x27, 0x54) ++#define REG_SC_BK27_54_H _PK_H_(0x27, 0x54) ++#define REG_SC_BK27_55_L _PK_L_(0x27, 0x55) ++#define REG_SC_BK27_55_H _PK_H_(0x27, 0x55) ++#define REG_SC_BK27_56_L _PK_L_(0x27, 0x56) ++#define REG_SC_BK27_56_H _PK_H_(0x27, 0x56) ++#define REG_SC_BK27_57_L _PK_L_(0x27, 0x57) ++#define REG_SC_BK27_57_H _PK_H_(0x27, 0x57) ++#define REG_SC_BK27_58_L _PK_L_(0x27, 0x58) ++#define REG_SC_BK27_58_H _PK_H_(0x27, 0x58) ++#define REG_SC_BK27_59_L _PK_L_(0x27, 0x59) ++#define REG_SC_BK27_59_H _PK_H_(0x27, 0x59) ++#define REG_SC_BK27_5A_L _PK_L_(0x27, 0x5A) ++#define REG_SC_BK27_5A_H _PK_H_(0x27, 0x5A) ++#define REG_SC_BK27_5B_L _PK_L_(0x27, 0x5B) ++#define REG_SC_BK27_5B_H _PK_H_(0x27, 0x5B) ++#define REG_SC_BK27_5C_L _PK_L_(0x27, 0x5C) ++#define REG_SC_BK27_5C_H _PK_H_(0x27, 0x5C) ++#define REG_SC_BK27_5D_L _PK_L_(0x27, 0x5D) ++#define REG_SC_BK27_5D_H _PK_H_(0x27, 0x5D) ++#define REG_SC_BK27_5E_L _PK_L_(0x27, 0x5E) ++#define REG_SC_BK27_5E_H _PK_H_(0x27, 0x5E) ++#define REG_SC_BK27_5F_L _PK_L_(0x27, 0x5F) ++#define REG_SC_BK27_5F_H _PK_H_(0x27, 0x5F) ++#define REG_SC_BK27_60_L _PK_L_(0x27, 0x60) ++#define REG_SC_BK27_60_H _PK_H_(0x27, 0x60) ++#define REG_SC_BK27_61_L _PK_L_(0x27, 0x61) ++#define REG_SC_BK27_61_H _PK_H_(0x27, 0x61) ++#define REG_SC_BK27_62_L _PK_L_(0x27, 0x62) ++#define REG_SC_BK27_62_H _PK_H_(0x27, 0x62) ++#define REG_SC_BK27_63_L _PK_L_(0x27, 0x63) ++#define REG_SC_BK27_63_H _PK_H_(0x27, 0x63) ++#define REG_SC_BK27_64_L _PK_L_(0x27, 0x64) ++#define REG_SC_BK27_64_H _PK_H_(0x27, 0x64) ++#define REG_SC_BK27_65_L _PK_L_(0x27, 0x65) ++#define REG_SC_BK27_65_H _PK_H_(0x27, 0x65) ++#define REG_SC_BK27_66_L _PK_L_(0x27, 0x66) ++#define REG_SC_BK27_66_H _PK_H_(0x27, 0x66) ++#define REG_SC_BK27_67_L _PK_L_(0x27, 0x67) ++#define REG_SC_BK27_67_H _PK_H_(0x27, 0x67) ++#define REG_SC_BK27_68_L _PK_L_(0x27, 0x68) ++#define REG_SC_BK27_68_H _PK_H_(0x27, 0x68) ++#define REG_SC_BK27_69_L _PK_L_(0x27, 0x69) ++#define REG_SC_BK27_69_H _PK_H_(0x27, 0x69) ++#define REG_SC_BK27_6A_L _PK_L_(0x27, 0x6A) ++#define REG_SC_BK27_6A_H _PK_H_(0x27, 0x6A) ++#define REG_SC_BK27_6B_L _PK_L_(0x27, 0x6B) ++#define REG_SC_BK27_6B_H _PK_H_(0x27, 0x6B) ++#define REG_SC_BK27_6C_L _PK_L_(0x27, 0x6C) ++#define REG_SC_BK27_6C_H _PK_H_(0x27, 0x6C) ++#define REG_SC_BK27_6D_L _PK_L_(0x27, 0x6D) ++#define REG_SC_BK27_6D_H _PK_H_(0x27, 0x6D) ++#define REG_SC_BK27_6E_L _PK_L_(0x27, 0x6E) ++#define REG_SC_BK27_6E_H _PK_H_(0x27, 0x6E) ++#define REG_SC_BK27_6F_L _PK_L_(0x27, 0x6F) ++#define REG_SC_BK27_6F_H _PK_H_(0x27, 0x6F) ++#define REG_SC_BK27_70_L _PK_L_(0x27, 0x70) ++#define REG_SC_BK27_70_H _PK_H_(0x27, 0x70) ++#define REG_SC_BK27_71_L _PK_L_(0x27, 0x71) ++#define REG_SC_BK27_71_H _PK_H_(0x27, 0x71) ++#define REG_SC_BK27_72_L _PK_L_(0x27, 0x72) ++#define REG_SC_BK27_72_H _PK_H_(0x27, 0x72) ++#define REG_SC_BK27_73_L _PK_L_(0x27, 0x73) ++#define REG_SC_BK27_73_H _PK_H_(0x27, 0x73) ++#define REG_SC_BK27_74_L _PK_L_(0x27, 0x74) ++#define REG_SC_BK27_74_H _PK_H_(0x27, 0x74) ++#define REG_SC_BK27_75_L _PK_L_(0x27, 0x75) ++#define REG_SC_BK27_75_H _PK_H_(0x27, 0x75) ++#define REG_SC_BK27_76_L _PK_L_(0x27, 0x76) ++#define REG_SC_BK27_76_H _PK_H_(0x27, 0x76) ++#define REG_SC_BK27_77_L _PK_L_(0x27, 0x77) ++#define REG_SC_BK27_77_H _PK_H_(0x27, 0x77) ++#define REG_SC_BK27_78_L _PK_L_(0x27, 0x78) ++#define REG_SC_BK27_78_H _PK_H_(0x27, 0x78) ++#define REG_SC_BK27_79_L _PK_L_(0x27, 0x79) ++#define REG_SC_BK27_79_H _PK_H_(0x27, 0x79) ++#define REG_SC_BK27_7A_L _PK_L_(0x27, 0x7A) ++#define REG_SC_BK27_7A_H _PK_H_(0x27, 0x7A) ++#define REG_SC_BK27_7B_L _PK_L_(0x27, 0x7B) ++#define REG_SC_BK27_7B_H _PK_H_(0x27, 0x7B) ++#define REG_SC_BK27_7C_L _PK_L_(0x27, 0x7C) ++#define REG_SC_BK27_7C_H _PK_H_(0x27, 0x7C) ++#define REG_SC_BK27_7D_L _PK_L_(0x27, 0x7D) ++#define REG_SC_BK27_7D_H _PK_H_(0x27, 0x7D) ++#define REG_SC_BK27_7E_L _PK_L_(0x27, 0x7E) ++#define REG_SC_BK27_7E_H _PK_H_(0x27, 0x7E) ++#define REG_SC_BK27_7F_L _PK_L_(0x27, 0x7F) ++#define REG_SC_BK27_7F_H _PK_H_(0x27, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK28_00_L _PK_L_(0x28, 0x00) ++#define REG_SC_BK28_00_H _PK_H_(0x28, 0x00) ++#define REG_SC_BK28_01_L _PK_L_(0x28, 0x01) ++#define REG_SC_BK28_01_H _PK_H_(0x28, 0x01) ++#define REG_SC_BK28_02_L _PK_L_(0x28, 0x02) ++#define REG_SC_BK28_02_H _PK_H_(0x28, 0x02) ++#define REG_SC_BK28_03_L _PK_L_(0x28, 0x03) ++#define REG_SC_BK28_03_H _PK_H_(0x28, 0x03) ++#define REG_SC_BK28_04_L _PK_L_(0x28, 0x04) ++#define REG_SC_BK28_04_H _PK_H_(0x28, 0x04) ++#define REG_SC_BK28_05_L _PK_L_(0x28, 0x05) ++#define REG_SC_BK28_05_H _PK_H_(0x28, 0x05) ++#define REG_SC_BK28_06_L _PK_L_(0x28, 0x06) ++#define REG_SC_BK28_06_H _PK_H_(0x28, 0x06) ++#define REG_SC_BK28_07_L _PK_L_(0x28, 0x07) ++#define REG_SC_BK28_07_H _PK_H_(0x28, 0x07) ++#define REG_SC_BK28_08_L _PK_L_(0x28, 0x08) ++#define REG_SC_BK28_08_H _PK_H_(0x28, 0x08) ++#define REG_SC_BK28_09_L _PK_L_(0x28, 0x09) ++#define REG_SC_BK28_09_H _PK_H_(0x28, 0x09) ++#define REG_SC_BK28_0A_L _PK_L_(0x28, 0x0A) ++#define REG_SC_BK28_0A_H _PK_H_(0x28, 0x0A) ++#define REG_SC_BK28_0B_L _PK_L_(0x28, 0x0B) ++#define REG_SC_BK28_0B_H _PK_H_(0x28, 0x0B) ++#define REG_SC_BK28_0C_L _PK_L_(0x28, 0x0C) ++#define REG_SC_BK28_0C_H _PK_H_(0x28, 0x0C) ++#define REG_SC_BK28_0D_L _PK_L_(0x28, 0x0D) ++#define REG_SC_BK28_0D_H _PK_H_(0x28, 0x0D) ++#define REG_SC_BK28_0E_L _PK_L_(0x28, 0x0E) ++#define REG_SC_BK28_0E_H _PK_H_(0x28, 0x0E) ++#define REG_SC_BK28_0F_L _PK_L_(0x28, 0x0F) ++#define REG_SC_BK28_0F_H _PK_H_(0x28, 0x0F) ++#define REG_SC_BK28_10_L _PK_L_(0x28, 0x10) ++#define REG_SC_BK28_10_H _PK_H_(0x28, 0x10) ++#define REG_SC_BK28_11_L _PK_L_(0x28, 0x11) ++#define REG_SC_BK28_11_H _PK_H_(0x28, 0x11) ++#define REG_SC_BK28_12_L _PK_L_(0x28, 0x12) ++#define REG_SC_BK28_12_H _PK_H_(0x28, 0x12) ++#define REG_SC_BK28_13_L _PK_L_(0x28, 0x13) ++#define REG_SC_BK28_13_H _PK_H_(0x28, 0x13) ++#define REG_SC_BK28_14_L _PK_L_(0x28, 0x14) ++#define REG_SC_BK28_14_H _PK_H_(0x28, 0x14) ++#define REG_SC_BK28_15_L _PK_L_(0x28, 0x15) ++#define REG_SC_BK28_15_H _PK_H_(0x28, 0x15) ++#define REG_SC_BK28_16_L _PK_L_(0x28, 0x16) ++#define REG_SC_BK28_16_H _PK_H_(0x28, 0x16) ++#define REG_SC_BK28_17_L _PK_L_(0x28, 0x17) ++#define REG_SC_BK28_17_H _PK_H_(0x28, 0x17) ++#define REG_SC_BK28_18_L _PK_L_(0x28, 0x18) ++#define REG_SC_BK28_18_H _PK_H_(0x28, 0x18) ++#define REG_SC_BK28_19_L _PK_L_(0x28, 0x19) ++#define REG_SC_BK28_19_H _PK_H_(0x28, 0x19) ++#define REG_SC_BK28_1A_L _PK_L_(0x28, 0x1A) ++#define REG_SC_BK28_1A_H _PK_H_(0x28, 0x1A) ++#define REG_SC_BK28_1B_L _PK_L_(0x28, 0x1B) ++#define REG_SC_BK28_1B_H _PK_H_(0x28, 0x1B) ++#define REG_SC_BK28_1C_L _PK_L_(0x28, 0x1C) ++#define REG_SC_BK28_1C_H _PK_H_(0x28, 0x1C) ++#define REG_SC_BK28_1D_L _PK_L_(0x28, 0x1D) ++#define REG_SC_BK28_1D_H _PK_H_(0x28, 0x1D) ++#define REG_SC_BK28_1E_L _PK_L_(0x28, 0x1E) ++#define REG_SC_BK28_1E_H _PK_H_(0x28, 0x1E) ++#define REG_SC_BK28_1F_L _PK_L_(0x28, 0x1F) ++#define REG_SC_BK28_1F_H _PK_H_(0x28, 0x1F) ++#define REG_SC_BK28_20_L _PK_L_(0x28, 0x20) ++#define REG_SC_BK28_20_H _PK_H_(0x28, 0x20) ++#define REG_SC_BK28_21_L _PK_L_(0x28, 0x21) ++#define REG_SC_BK28_21_H _PK_H_(0x28, 0x21) ++#define REG_SC_BK28_22_L _PK_L_(0x28, 0x22) ++#define REG_SC_BK28_22_H _PK_H_(0x28, 0x22) ++#define REG_SC_BK28_23_L _PK_L_(0x28, 0x23) ++#define REG_SC_BK28_23_H _PK_H_(0x28, 0x23) ++#define REG_SC_BK28_24_L _PK_L_(0x28, 0x24) ++#define REG_SC_BK28_24_H _PK_H_(0x28, 0x24) ++#define REG_SC_BK28_25_L _PK_L_(0x28, 0x25) ++#define REG_SC_BK28_25_H _PK_H_(0x28, 0x25) ++#define REG_SC_BK28_26_L _PK_L_(0x28, 0x26) ++#define REG_SC_BK28_26_H _PK_H_(0x28, 0x26) ++#define REG_SC_BK28_27_L _PK_L_(0x28, 0x27) ++#define REG_SC_BK28_27_H _PK_H_(0x28, 0x27) ++#define REG_SC_BK28_28_L _PK_L_(0x28, 0x28) ++#define REG_SC_BK28_28_H _PK_H_(0x28, 0x28) ++#define REG_SC_BK28_29_L _PK_L_(0x28, 0x29) ++#define REG_SC_BK28_29_H _PK_H_(0x28, 0x29) ++#define REG_SC_BK28_2A_L _PK_L_(0x28, 0x2A) ++#define REG_SC_BK28_2A_H _PK_H_(0x28, 0x2A) ++#define REG_SC_BK28_2B_L _PK_L_(0x28, 0x2B) ++#define REG_SC_BK28_2B_H _PK_H_(0x28, 0x2B) ++#define REG_SC_BK28_2C_L _PK_L_(0x28, 0x2C) ++#define REG_SC_BK28_2C_H _PK_H_(0x28, 0x2C) ++#define REG_SC_BK28_2D_L _PK_L_(0x28, 0x2D) ++#define REG_SC_BK28_2D_H _PK_H_(0x28, 0x2D) ++#define REG_SC_BK28_2E_L _PK_L_(0x28, 0x2E) ++#define REG_SC_BK28_2E_H _PK_H_(0x28, 0x2E) ++#define REG_SC_BK28_2F_L _PK_L_(0x28, 0x2F) ++#define REG_SC_BK28_2F_H _PK_H_(0x28, 0x2F) ++#define REG_SC_BK28_30_L _PK_L_(0x28, 0x30) ++#define REG_SC_BK28_30_H _PK_H_(0x28, 0x30) ++#define REG_SC_BK28_31_L _PK_L_(0x28, 0x31) ++#define REG_SC_BK28_31_H _PK_H_(0x28, 0x31) ++#define REG_SC_BK28_32_L _PK_L_(0x28, 0x32) ++#define REG_SC_BK28_32_H _PK_H_(0x28, 0x32) ++#define REG_SC_BK28_33_L _PK_L_(0x28, 0x33) ++#define REG_SC_BK28_33_H _PK_H_(0x28, 0x33) ++#define REG_SC_BK28_34_L _PK_L_(0x28, 0x34) ++#define REG_SC_BK28_34_H _PK_H_(0x28, 0x34) ++#define REG_SC_BK28_35_L _PK_L_(0x28, 0x35) ++#define REG_SC_BK28_35_H _PK_H_(0x28, 0x35) ++#define REG_SC_BK28_36_L _PK_L_(0x28, 0x36) ++#define REG_SC_BK28_36_H _PK_H_(0x28, 0x36) ++#define REG_SC_BK28_37_L _PK_L_(0x28, 0x37) ++#define REG_SC_BK28_37_H _PK_H_(0x28, 0x37) ++#define REG_SC_BK28_38_L _PK_L_(0x28, 0x38) ++#define REG_SC_BK28_38_H _PK_H_(0x28, 0x38) ++#define REG_SC_BK28_39_L _PK_L_(0x28, 0x39) ++#define REG_SC_BK28_39_H _PK_H_(0x28, 0x39) ++#define REG_SC_BK28_3A_L _PK_L_(0x28, 0x3A) ++#define REG_SC_BK28_3A_H _PK_H_(0x28, 0x3A) ++#define REG_SC_BK28_3B_L _PK_L_(0x28, 0x3B) ++#define REG_SC_BK28_3B_H _PK_H_(0x28, 0x3B) ++#define REG_SC_BK28_3C_L _PK_L_(0x28, 0x3C) ++#define REG_SC_BK28_3C_H _PK_H_(0x28, 0x3C) ++#define REG_SC_BK28_3D_L _PK_L_(0x28, 0x3D) ++#define REG_SC_BK28_3D_H _PK_H_(0x28, 0x3D) ++#define REG_SC_BK28_3E_L _PK_L_(0x28, 0x3E) ++#define REG_SC_BK28_3E_H _PK_H_(0x28, 0x3E) ++#define REG_SC_BK28_3F_L _PK_L_(0x28, 0x3F) ++#define REG_SC_BK28_3F_H _PK_H_(0x28, 0x3F) ++#define REG_SC_BK28_40_L _PK_L_(0x28, 0x40) ++#define REG_SC_BK28_40_H _PK_H_(0x28, 0x40) ++#define REG_SC_BK28_41_L _PK_L_(0x28, 0x41) ++#define REG_SC_BK28_41_H _PK_H_(0x28, 0x41) ++#define REG_SC_BK28_42_L _PK_L_(0x28, 0x42) ++#define REG_SC_BK28_42_H _PK_H_(0x28, 0x42) ++#define REG_SC_BK28_43_L _PK_L_(0x28, 0x43) ++#define REG_SC_BK28_43_H _PK_H_(0x28, 0x43) ++#define REG_SC_BK28_44_L _PK_L_(0x28, 0x44) ++#define REG_SC_BK28_44_H _PK_H_(0x28, 0x44) ++#define REG_SC_BK28_45_L _PK_L_(0x28, 0x45) ++#define REG_SC_BK28_45_H _PK_H_(0x28, 0x45) ++#define REG_SC_BK28_46_L _PK_L_(0x28, 0x46) ++#define REG_SC_BK28_46_H _PK_H_(0x28, 0x46) ++#define REG_SC_BK28_47_L _PK_L_(0x28, 0x47) ++#define REG_SC_BK28_47_H _PK_H_(0x28, 0x47) ++#define REG_SC_BK28_48_L _PK_L_(0x28, 0x48) ++#define REG_SC_BK28_48_H _PK_H_(0x28, 0x48) ++#define REG_SC_BK28_49_L _PK_L_(0x28, 0x49) ++#define REG_SC_BK28_49_H _PK_H_(0x28, 0x49) ++#define REG_SC_BK28_4A_L _PK_L_(0x28, 0x4A) ++#define REG_SC_BK28_4A_H _PK_H_(0x28, 0x4A) ++#define REG_SC_BK28_4B_L _PK_L_(0x28, 0x4B) ++#define REG_SC_BK28_4B_H _PK_H_(0x28, 0x4B) ++#define REG_SC_BK28_4C_L _PK_L_(0x28, 0x4C) ++#define REG_SC_BK28_4C_H _PK_H_(0x28, 0x4C) ++#define REG_SC_BK28_4D_L _PK_L_(0x28, 0x4D) ++#define REG_SC_BK28_4D_H _PK_H_(0x28, 0x4D) ++#define REG_SC_BK28_4E_L _PK_L_(0x28, 0x4E) ++#define REG_SC_BK28_4E_H _PK_H_(0x28, 0x4E) ++#define REG_SC_BK28_4F_L _PK_L_(0x28, 0x4F) ++#define REG_SC_BK28_4F_H _PK_H_(0x28, 0x4F) ++#define REG_SC_BK28_50_L _PK_L_(0x28, 0x50) ++#define REG_SC_BK28_50_H _PK_H_(0x28, 0x50) ++#define REG_SC_BK28_51_L _PK_L_(0x28, 0x51) ++#define REG_SC_BK28_51_H _PK_H_(0x28, 0x51) ++#define REG_SC_BK28_52_L _PK_L_(0x28, 0x52) ++#define REG_SC_BK28_52_H _PK_H_(0x28, 0x52) ++#define REG_SC_BK28_53_L _PK_L_(0x28, 0x53) ++#define REG_SC_BK28_53_H _PK_H_(0x28, 0x53) ++#define REG_SC_BK28_54_L _PK_L_(0x28, 0x54) ++#define REG_SC_BK28_54_H _PK_H_(0x28, 0x54) ++#define REG_SC_BK28_55_L _PK_L_(0x28, 0x55) ++#define REG_SC_BK28_55_H _PK_H_(0x28, 0x55) ++#define REG_SC_BK28_56_L _PK_L_(0x28, 0x56) ++#define REG_SC_BK28_56_H _PK_H_(0x28, 0x56) ++#define REG_SC_BK28_57_L _PK_L_(0x28, 0x57) ++#define REG_SC_BK28_57_H _PK_H_(0x28, 0x57) ++#define REG_SC_BK28_58_L _PK_L_(0x28, 0x58) ++#define REG_SC_BK28_58_H _PK_H_(0x28, 0x58) ++#define REG_SC_BK28_59_L _PK_L_(0x28, 0x59) ++#define REG_SC_BK28_59_H _PK_H_(0x28, 0x59) ++#define REG_SC_BK28_5A_L _PK_L_(0x28, 0x5A) ++#define REG_SC_BK28_5A_H _PK_H_(0x28, 0x5A) ++#define REG_SC_BK28_5B_L _PK_L_(0x28, 0x5B) ++#define REG_SC_BK28_5B_H _PK_H_(0x28, 0x5B) ++#define REG_SC_BK28_5C_L _PK_L_(0x28, 0x5C) ++#define REG_SC_BK28_5C_H _PK_H_(0x28, 0x5C) ++#define REG_SC_BK28_5D_L _PK_L_(0x28, 0x5D) ++#define REG_SC_BK28_5D_H _PK_H_(0x28, 0x5D) ++#define REG_SC_BK28_5E_L _PK_L_(0x28, 0x5E) ++#define REG_SC_BK28_5E_H _PK_H_(0x28, 0x5E) ++#define REG_SC_BK28_5F_L _PK_L_(0x28, 0x5F) ++#define REG_SC_BK28_5F_H _PK_H_(0x28, 0x5F) ++#define REG_SC_BK28_60_L _PK_L_(0x28, 0x60) ++#define REG_SC_BK28_60_H _PK_H_(0x28, 0x60) ++#define REG_SC_BK28_61_L _PK_L_(0x28, 0x61) ++#define REG_SC_BK28_61_H _PK_H_(0x28, 0x61) ++#define REG_SC_BK28_62_L _PK_L_(0x28, 0x62) ++#define REG_SC_BK28_62_H _PK_H_(0x28, 0x62) ++#define REG_SC_BK28_63_L _PK_L_(0x28, 0x63) ++#define REG_SC_BK28_63_H _PK_H_(0x28, 0x63) ++#define REG_SC_BK28_64_L _PK_L_(0x28, 0x64) ++#define REG_SC_BK28_64_H _PK_H_(0x28, 0x64) ++#define REG_SC_BK28_65_L _PK_L_(0x28, 0x65) ++#define REG_SC_BK28_65_H _PK_H_(0x28, 0x65) ++#define REG_SC_BK28_66_L _PK_L_(0x28, 0x66) ++#define REG_SC_BK28_66_H _PK_H_(0x28, 0x66) ++#define REG_SC_BK28_67_L _PK_L_(0x28, 0x67) ++#define REG_SC_BK28_67_H _PK_H_(0x28, 0x67) ++#define REG_SC_BK28_68_L _PK_L_(0x28, 0x68) ++#define REG_SC_BK28_68_H _PK_H_(0x28, 0x68) ++#define REG_SC_BK28_69_L _PK_L_(0x28, 0x69) ++#define REG_SC_BK28_69_H _PK_H_(0x28, 0x69) ++#define REG_SC_BK28_6A_L _PK_L_(0x28, 0x6A) ++#define REG_SC_BK28_6A_H _PK_H_(0x28, 0x6A) ++#define REG_SC_BK28_6B_L _PK_L_(0x28, 0x6B) ++#define REG_SC_BK28_6B_H _PK_H_(0x28, 0x6B) ++#define REG_SC_BK28_6C_L _PK_L_(0x28, 0x6C) ++#define REG_SC_BK28_6C_H _PK_H_(0x28, 0x6C) ++#define REG_SC_BK28_6D_L _PK_L_(0x28, 0x6D) ++#define REG_SC_BK28_6D_H _PK_H_(0x28, 0x6D) ++#define REG_SC_BK28_6E_L _PK_L_(0x28, 0x6E) ++#define REG_SC_BK28_6E_H _PK_H_(0x28, 0x6E) ++#define REG_SC_BK28_6F_L _PK_L_(0x28, 0x6F) ++#define REG_SC_BK28_6F_H _PK_H_(0x28, 0x6F) ++#define REG_SC_BK28_70_L _PK_L_(0x28, 0x70) ++#define REG_SC_BK28_70_H _PK_H_(0x28, 0x70) ++#define REG_SC_BK28_71_L _PK_L_(0x28, 0x71) ++#define REG_SC_BK28_71_H _PK_H_(0x28, 0x71) ++#define REG_SC_BK28_72_L _PK_L_(0x28, 0x72) ++#define REG_SC_BK28_72_H _PK_H_(0x28, 0x72) ++#define REG_SC_BK28_73_L _PK_L_(0x28, 0x73) ++#define REG_SC_BK28_73_H _PK_H_(0x28, 0x73) ++#define REG_SC_BK28_74_L _PK_L_(0x28, 0x74) ++#define REG_SC_BK28_74_H _PK_H_(0x28, 0x74) ++#define REG_SC_BK28_75_L _PK_L_(0x28, 0x75) ++#define REG_SC_BK28_75_H _PK_H_(0x28, 0x75) ++#define REG_SC_BK28_76_L _PK_L_(0x28, 0x76) ++#define REG_SC_BK28_76_H _PK_H_(0x28, 0x76) ++#define REG_SC_BK28_77_L _PK_L_(0x28, 0x77) ++#define REG_SC_BK28_77_H _PK_H_(0x28, 0x77) ++#define REG_SC_BK28_78_L _PK_L_(0x28, 0x78) ++#define REG_SC_BK28_78_H _PK_H_(0x28, 0x78) ++#define REG_SC_BK28_79_L _PK_L_(0x28, 0x79) ++#define REG_SC_BK28_79_H _PK_H_(0x28, 0x79) ++#define REG_SC_BK28_7A_L _PK_L_(0x28, 0x7A) ++#define REG_SC_BK28_7A_H _PK_H_(0x28, 0x7A) ++#define REG_SC_BK28_7B_L _PK_L_(0x28, 0x7B) ++#define REG_SC_BK28_7B_H _PK_H_(0x28, 0x7B) ++#define REG_SC_BK28_7C_L _PK_L_(0x28, 0x7C) ++#define REG_SC_BK28_7C_H _PK_H_(0x28, 0x7C) ++#define REG_SC_BK28_7D_L _PK_L_(0x28, 0x7D) ++#define REG_SC_BK28_7D_H _PK_H_(0x28, 0x7D) ++#define REG_SC_BK28_7E_L _PK_L_(0x28, 0x7E) ++#define REG_SC_BK28_7E_H _PK_H_(0x28, 0x7E) ++#define REG_SC_BK28_7F_L _PK_L_(0x28, 0x7F) ++#define REG_SC_BK28_7F_H _PK_H_(0x28, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK2A_00_L _PK_L_(0x2A, 0x00) ++#define REG_SC_BK2A_00_H _PK_H_(0x2A, 0x00) ++#define REG_SC_BK2A_01_L _PK_L_(0x2A, 0x01) ++#define REG_SC_BK2A_01_H _PK_H_(0x2A, 0x01) ++#define REG_SC_BK2A_02_L _PK_L_(0x2A, 0x02) ++#define REG_SC_BK2A_02_H _PK_H_(0x2A, 0x02) ++#define REG_SC_BK2A_03_L _PK_L_(0x2A, 0x03) ++#define REG_SC_BK2A_03_H _PK_H_(0x2A, 0x03) ++#define REG_SC_BK2A_04_L _PK_L_(0x2A, 0x04) ++#define REG_SC_BK2A_04_H _PK_H_(0x2A, 0x04) ++#define REG_SC_BK2A_05_L _PK_L_(0x2A, 0x05) ++#define REG_SC_BK2A_05_H _PK_H_(0x2A, 0x05) ++#define REG_SC_BK2A_06_L _PK_L_(0x2A, 0x06) ++#define REG_SC_BK2A_06_H _PK_H_(0x2A, 0x06) ++#define REG_SC_BK2A_07_L _PK_L_(0x2A, 0x07) ++#define REG_SC_BK2A_07_H _PK_H_(0x2A, 0x07) ++#define REG_SC_BK2A_08_L _PK_L_(0x2A, 0x08) ++#define REG_SC_BK2A_08_H _PK_H_(0x2A, 0x08) ++#define REG_SC_BK2A_09_L _PK_L_(0x2A, 0x09) ++#define REG_SC_BK2A_09_H _PK_H_(0x2A, 0x09) ++#define REG_SC_BK2A_0A_L _PK_L_(0x2A, 0x0A) ++#define REG_SC_BK2A_0A_H _PK_H_(0x2A, 0x0A) ++#define REG_SC_BK2A_0B_L _PK_L_(0x2A, 0x0B) ++#define REG_SC_BK2A_0B_H _PK_H_(0x2A, 0x0B) ++#define REG_SC_BK2A_0C_L _PK_L_(0x2A, 0x0C) ++#define REG_SC_BK2A_0C_H _PK_H_(0x2A, 0x0C) ++#define REG_SC_BK2A_0D_L _PK_L_(0x2A, 0x0D) ++#define REG_SC_BK2A_0D_H _PK_H_(0x2A, 0x0D) ++#define REG_SC_BK2A_0E_L _PK_L_(0x2A, 0x0E) ++#define REG_SC_BK2A_0E_H _PK_H_(0x2A, 0x0E) ++#define REG_SC_BK2A_0F_L _PK_L_(0x2A, 0x0F) ++#define REG_SC_BK2A_0F_H _PK_H_(0x2A, 0x0F) ++#define REG_SC_BK2A_10_L _PK_L_(0x2A, 0x10) ++#define REG_SC_BK2A_10_H _PK_H_(0x2A, 0x10) ++#define REG_SC_BK2A_11_L _PK_L_(0x2A, 0x11) ++#define REG_SC_BK2A_11_H _PK_H_(0x2A, 0x11) ++#define REG_SC_BK2A_12_L _PK_L_(0x2A, 0x12) ++#define REG_SC_BK2A_12_H _PK_H_(0x2A, 0x12) ++#define REG_SC_BK2A_13_L _PK_L_(0x2A, 0x13) ++#define REG_SC_BK2A_13_H _PK_H_(0x2A, 0x13) ++#define REG_SC_BK2A_14_L _PK_L_(0x2A, 0x14) ++#define REG_SC_BK2A_14_H _PK_H_(0x2A, 0x14) ++#define REG_SC_BK2A_15_L _PK_L_(0x2A, 0x15) ++#define REG_SC_BK2A_15_H _PK_H_(0x2A, 0x15) ++#define REG_SC_BK2A_16_L _PK_L_(0x2A, 0x16) ++#define REG_SC_BK2A_16_H _PK_H_(0x2A, 0x16) ++#define REG_SC_BK2A_17_L _PK_L_(0x2A, 0x17) ++#define REG_SC_BK2A_17_H _PK_H_(0x2A, 0x17) ++#define REG_SC_BK2A_18_L _PK_L_(0x2A, 0x18) ++#define REG_SC_BK2A_18_H _PK_H_(0x2A, 0x18) ++#define REG_SC_BK2A_19_L _PK_L_(0x2A, 0x19) ++#define REG_SC_BK2A_19_H _PK_H_(0x2A, 0x19) ++#define REG_SC_BK2A_1A_L _PK_L_(0x2A, 0x1A) ++#define REG_SC_BK2A_1A_H _PK_H_(0x2A, 0x1A) ++#define REG_SC_BK2A_1B_L _PK_L_(0x2A, 0x1B) ++#define REG_SC_BK2A_1B_H _PK_H_(0x2A, 0x1B) ++#define REG_SC_BK2A_1C_L _PK_L_(0x2A, 0x1C) ++#define REG_SC_BK2A_1C_H _PK_H_(0x2A, 0x1C) ++#define REG_SC_BK2A_1D_L _PK_L_(0x2A, 0x1D) ++#define REG_SC_BK2A_1D_H _PK_H_(0x2A, 0x1D) ++#define REG_SC_BK2A_1E_L _PK_L_(0x2A, 0x1E) ++#define REG_SC_BK2A_1E_H _PK_H_(0x2A, 0x1E) ++#define REG_SC_BK2A_1F_L _PK_L_(0x2A, 0x1F) ++#define REG_SC_BK2A_1F_H _PK_H_(0x2A, 0x1F) ++#define REG_SC_BK2A_20_L _PK_L_(0x2A, 0x20) ++#define REG_SC_BK2A_20_H _PK_H_(0x2A, 0x20) ++#define REG_SC_BK2A_21_L _PK_L_(0x2A, 0x21) ++#define REG_SC_BK2A_21_H _PK_H_(0x2A, 0x21) ++#define REG_SC_BK2A_22_L _PK_L_(0x2A, 0x22) ++#define REG_SC_BK2A_22_H _PK_H_(0x2A, 0x22) ++#define REG_SC_BK2A_23_L _PK_L_(0x2A, 0x23) ++#define REG_SC_BK2A_23_H _PK_H_(0x2A, 0x23) ++#define REG_SC_BK2A_24_L _PK_L_(0x2A, 0x24) ++#define REG_SC_BK2A_24_H _PK_H_(0x2A, 0x24) ++#define REG_SC_BK2A_25_L _PK_L_(0x2A, 0x25) ++#define REG_SC_BK2A_25_H _PK_H_(0x2A, 0x25) ++#define REG_SC_BK2A_26_L _PK_L_(0x2A, 0x26) ++#define REG_SC_BK2A_26_H _PK_H_(0x2A, 0x26) ++#define REG_SC_BK2A_27_L _PK_L_(0x2A, 0x27) ++#define REG_SC_BK2A_27_H _PK_H_(0x2A, 0x27) ++#define REG_SC_BK2A_28_L _PK_L_(0x2A, 0x28) ++#define REG_SC_BK2A_28_H _PK_H_(0x2A, 0x28) ++#define REG_SC_BK2A_29_L _PK_L_(0x2A, 0x29) ++#define REG_SC_BK2A_29_H _PK_H_(0x2A, 0x29) ++#define REG_SC_BK2A_2A_L _PK_L_(0x2A, 0x2A) ++#define REG_SC_BK2A_2A_H _PK_H_(0x2A, 0x2A) ++#define REG_SC_BK2A_2B_L _PK_L_(0x2A, 0x2B) ++#define REG_SC_BK2A_2B_H _PK_H_(0x2A, 0x2B) ++#define REG_SC_BK2A_2C_L _PK_L_(0x2A, 0x2C) ++#define REG_SC_BK2A_2C_H _PK_H_(0x2A, 0x2C) ++#define REG_SC_BK2A_2D_L _PK_L_(0x2A, 0x2D) ++#define REG_SC_BK2A_2D_H _PK_H_(0x2A, 0x2D) ++#define REG_SC_BK2A_2E_L _PK_L_(0x2A, 0x2E) ++#define REG_SC_BK2A_2E_H _PK_H_(0x2A, 0x2E) ++#define REG_SC_BK2A_2F_L _PK_L_(0x2A, 0x2F) ++#define REG_SC_BK2A_2F_H _PK_H_(0x2A, 0x2F) ++#define REG_SC_BK2A_30_L _PK_L_(0x2A, 0x30) ++#define REG_SC_BK2A_30_H _PK_H_(0x2A, 0x30) ++#define REG_SC_BK2A_31_L _PK_L_(0x2A, 0x31) ++#define REG_SC_BK2A_31_H _PK_H_(0x2A, 0x31) ++#define REG_SC_BK2A_32_L _PK_L_(0x2A, 0x32) ++#define REG_SC_BK2A_32_H _PK_H_(0x2A, 0x32) ++#define REG_SC_BK2A_33_L _PK_L_(0x2A, 0x33) ++#define REG_SC_BK2A_33_H _PK_H_(0x2A, 0x33) ++#define REG_SC_BK2A_34_L _PK_L_(0x2A, 0x34) ++#define REG_SC_BK2A_34_H _PK_H_(0x2A, 0x34) ++#define REG_SC_BK2A_35_L _PK_L_(0x2A, 0x35) ++#define REG_SC_BK2A_35_H _PK_H_(0x2A, 0x35) ++#define REG_SC_BK2A_36_L _PK_L_(0x2A, 0x36) ++#define REG_SC_BK2A_36_H _PK_H_(0x2A, 0x36) ++#define REG_SC_BK2A_37_L _PK_L_(0x2A, 0x37) ++#define REG_SC_BK2A_37_H _PK_H_(0x2A, 0x37) ++#define REG_SC_BK2A_38_L _PK_L_(0x2A, 0x38) ++#define REG_SC_BK2A_38_H _PK_H_(0x2A, 0x38) ++#define REG_SC_BK2A_39_L _PK_L_(0x2A, 0x39) ++#define REG_SC_BK2A_39_H _PK_H_(0x2A, 0x39) ++#define REG_SC_BK2A_3A_L _PK_L_(0x2A, 0x3A) ++#define REG_SC_BK2A_3A_H _PK_H_(0x2A, 0x3A) ++#define REG_SC_BK2A_3B_L _PK_L_(0x2A, 0x3B) ++#define REG_SC_BK2A_3B_H _PK_H_(0x2A, 0x3B) ++#define REG_SC_BK2A_3C_L _PK_L_(0x2A, 0x3C) ++#define REG_SC_BK2A_3C_H _PK_H_(0x2A, 0x3C) ++#define REG_SC_BK2A_3D_L _PK_L_(0x2A, 0x3D) ++#define REG_SC_BK2A_3D_H _PK_H_(0x2A, 0x3D) ++#define REG_SC_BK2A_3E_L _PK_L_(0x2A, 0x3E) ++#define REG_SC_BK2A_3E_H _PK_H_(0x2A, 0x3E) ++#define REG_SC_BK2A_3F_L _PK_L_(0x2A, 0x3F) ++#define REG_SC_BK2A_3F_H _PK_H_(0x2A, 0x3F) ++#define REG_SC_BK2A_40_L _PK_L_(0x2A, 0x40) ++#define REG_SC_BK2A_40_H _PK_H_(0x2A, 0x40) ++#define REG_SC_BK2A_41_L _PK_L_(0x2A, 0x41) ++#define REG_SC_BK2A_41_H _PK_H_(0x2A, 0x41) ++#define REG_SC_BK2A_42_L _PK_L_(0x2A, 0x42) ++#define REG_SC_BK2A_42_H _PK_H_(0x2A, 0x42) ++#define REG_SC_BK2A_43_L _PK_L_(0x2A, 0x43) ++#define REG_SC_BK2A_43_H _PK_H_(0x2A, 0x43) ++#define REG_SC_BK2A_44_L _PK_L_(0x2A, 0x44) ++#define REG_SC_BK2A_44_H _PK_H_(0x2A, 0x44) ++#define REG_SC_BK2A_45_L _PK_L_(0x2A, 0x45) ++#define REG_SC_BK2A_45_H _PK_H_(0x2A, 0x45) ++#define REG_SC_BK2A_46_L _PK_L_(0x2A, 0x46) ++#define REG_SC_BK2A_46_H _PK_H_(0x2A, 0x46) ++#define REG_SC_BK2A_47_L _PK_L_(0x2A, 0x47) ++#define REG_SC_BK2A_47_H _PK_H_(0x2A, 0x47) ++#define REG_SC_BK2A_48_L _PK_L_(0x2A, 0x48) ++#define REG_SC_BK2A_48_H _PK_H_(0x2A, 0x48) ++#define REG_SC_BK2A_49_L _PK_L_(0x2A, 0x49) ++#define REG_SC_BK2A_49_H _PK_H_(0x2A, 0x49) ++#define REG_SC_BK2A_4A_L _PK_L_(0x2A, 0x4A) ++#define REG_SC_BK2A_4A_H _PK_H_(0x2A, 0x4A) ++#define REG_SC_BK2A_4B_L _PK_L_(0x2A, 0x4B) ++#define REG_SC_BK2A_4B_H _PK_H_(0x2A, 0x4B) ++#define REG_SC_BK2A_4C_L _PK_L_(0x2A, 0x4C) ++#define REG_SC_BK2A_4C_H _PK_H_(0x2A, 0x4C) ++#define REG_SC_BK2A_4D_L _PK_L_(0x2A, 0x4D) ++#define REG_SC_BK2A_4D_H _PK_H_(0x2A, 0x4D) ++#define REG_SC_BK2A_4E_L _PK_L_(0x2A, 0x4E) ++#define REG_SC_BK2A_4E_H _PK_H_(0x2A, 0x4E) ++#define REG_SC_BK2A_4F_L _PK_L_(0x2A, 0x4F) ++#define REG_SC_BK2A_4F_H _PK_H_(0x2A, 0x4F) ++#define REG_SC_BK2A_50_L _PK_L_(0x2A, 0x50) ++#define REG_SC_BK2A_50_H _PK_H_(0x2A, 0x50) ++#define REG_SC_BK2A_51_L _PK_L_(0x2A, 0x51) ++#define REG_SC_BK2A_51_H _PK_H_(0x2A, 0x51) ++#define REG_SC_BK2A_52_L _PK_L_(0x2A, 0x52) ++#define REG_SC_BK2A_52_H _PK_H_(0x2A, 0x52) ++#define REG_SC_BK2A_53_L _PK_L_(0x2A, 0x53) ++#define REG_SC_BK2A_53_H _PK_H_(0x2A, 0x53) ++#define REG_SC_BK2A_54_L _PK_L_(0x2A, 0x54) ++#define REG_SC_BK2A_54_H _PK_H_(0x2A, 0x54) ++#define REG_SC_BK2A_55_L _PK_L_(0x2A, 0x55) ++#define REG_SC_BK2A_55_H _PK_H_(0x2A, 0x55) ++#define REG_SC_BK2A_56_L _PK_L_(0x2A, 0x56) ++#define REG_SC_BK2A_56_H _PK_H_(0x2A, 0x56) ++#define REG_SC_BK2A_57_L _PK_L_(0x2A, 0x57) ++#define REG_SC_BK2A_57_H _PK_H_(0x2A, 0x57) ++#define REG_SC_BK2A_58_L _PK_L_(0x2A, 0x58) ++#define REG_SC_BK2A_58_H _PK_H_(0x2A, 0x58) ++#define REG_SC_BK2A_59_L _PK_L_(0x2A, 0x59) ++#define REG_SC_BK2A_59_H _PK_H_(0x2A, 0x59) ++#define REG_SC_BK2A_5A_L _PK_L_(0x2A, 0x5A) ++#define REG_SC_BK2A_5A_H _PK_H_(0x2A, 0x5A) ++#define REG_SC_BK2A_5B_L _PK_L_(0x2A, 0x5B) ++#define REG_SC_BK2A_5B_H _PK_H_(0x2A, 0x5B) ++#define REG_SC_BK2A_5C_L _PK_L_(0x2A, 0x5C) ++#define REG_SC_BK2A_5C_H _PK_H_(0x2A, 0x5C) ++#define REG_SC_BK2A_5D_L _PK_L_(0x2A, 0x5D) ++#define REG_SC_BK2A_5D_H _PK_H_(0x2A, 0x5D) ++#define REG_SC_BK2A_5E_L _PK_L_(0x2A, 0x5E) ++#define REG_SC_BK2A_5E_H _PK_H_(0x2A, 0x5E) ++#define REG_SC_BK2A_5F_L _PK_L_(0x2A, 0x5F) ++#define REG_SC_BK2A_5F_H _PK_H_(0x2A, 0x5F) ++#define REG_SC_BK2A_60_L _PK_L_(0x2A, 0x60) ++#define REG_SC_BK2A_60_H _PK_H_(0x2A, 0x60) ++#define REG_SC_BK2A_61_L _PK_L_(0x2A, 0x61) ++#define REG_SC_BK2A_61_H _PK_H_(0x2A, 0x61) ++#define REG_SC_BK2A_62_L _PK_L_(0x2A, 0x62) ++#define REG_SC_BK2A_62_H _PK_H_(0x2A, 0x62) ++#define REG_SC_BK2A_63_L _PK_L_(0x2A, 0x63) ++#define REG_SC_BK2A_63_H _PK_H_(0x2A, 0x63) ++#define REG_SC_BK2A_64_L _PK_L_(0x2A, 0x64) ++#define REG_SC_BK2A_64_H _PK_H_(0x2A, 0x64) ++#define REG_SC_BK2A_65_L _PK_L_(0x2A, 0x65) ++#define REG_SC_BK2A_65_H _PK_H_(0x2A, 0x65) ++#define REG_SC_BK2A_66_L _PK_L_(0x2A, 0x66) ++#define REG_SC_BK2A_66_H _PK_H_(0x2A, 0x66) ++#define REG_SC_BK2A_67_L _PK_L_(0x2A, 0x67) ++#define REG_SC_BK2A_67_H _PK_H_(0x2A, 0x67) ++#define REG_SC_BK2A_68_L _PK_L_(0x2A, 0x68) ++#define REG_SC_BK2A_68_H _PK_H_(0x2A, 0x68) ++#define REG_SC_BK2A_69_L _PK_L_(0x2A, 0x69) ++#define REG_SC_BK2A_69_H _PK_H_(0x2A, 0x69) ++#define REG_SC_BK2A_6A_L _PK_L_(0x2A, 0x6A) ++#define REG_SC_BK2A_6A_H _PK_H_(0x2A, 0x6A) ++#define REG_SC_BK2A_6B_L _PK_L_(0x2A, 0x6B) ++#define REG_SC_BK2A_6B_H _PK_H_(0x2A, 0x6B) ++#define REG_SC_BK2A_6C_L _PK_L_(0x2A, 0x6C) ++#define REG_SC_BK2A_6C_H _PK_H_(0x2A, 0x6C) ++#define REG_SC_BK2A_6D_L _PK_L_(0x2A, 0x6D) ++#define REG_SC_BK2A_6D_H _PK_H_(0x2A, 0x6D) ++#define REG_SC_BK2A_6E_L _PK_L_(0x2A, 0x6E) ++#define REG_SC_BK2A_6E_H _PK_H_(0x2A, 0x6E) ++#define REG_SC_BK2A_6F_L _PK_L_(0x2A, 0x6F) ++#define REG_SC_BK2A_6F_H _PK_H_(0x2A, 0x6F) ++#define REG_SC_BK2A_70_L _PK_L_(0x2A, 0x70) ++#define REG_SC_BK2A_70_H _PK_H_(0x2A, 0x70) ++#define REG_SC_BK2A_71_L _PK_L_(0x2A, 0x71) ++#define REG_SC_BK2A_71_H _PK_H_(0x2A, 0x71) ++#define REG_SC_BK2A_72_L _PK_L_(0x2A, 0x72) ++#define REG_SC_BK2A_72_H _PK_H_(0x2A, 0x72) ++#define REG_SC_BK2A_73_L _PK_L_(0x2A, 0x73) ++#define REG_SC_BK2A_73_H _PK_H_(0x2A, 0x73) ++#define REG_SC_BK2A_74_L _PK_L_(0x2A, 0x74) ++#define REG_SC_BK2A_74_H _PK_H_(0x2A, 0x74) ++#define REG_SC_BK2A_75_L _PK_L_(0x2A, 0x75) ++#define REG_SC_BK2A_75_H _PK_H_(0x2A, 0x75) ++#define REG_SC_BK2A_76_L _PK_L_(0x2A, 0x76) ++#define REG_SC_BK2A_76_H _PK_H_(0x2A, 0x76) ++#define REG_SC_BK2A_77_L _PK_L_(0x2A, 0x77) ++#define REG_SC_BK2A_77_H _PK_H_(0x2A, 0x77) ++#define REG_SC_BK2A_78_L _PK_L_(0x2A, 0x78) ++#define REG_SC_BK2A_78_H _PK_H_(0x2A, 0x78) ++#define REG_SC_BK2A_79_L _PK_L_(0x2A, 0x79) ++#define REG_SC_BK2A_79_H _PK_H_(0x2A, 0x79) ++#define REG_SC_BK2A_7A_L _PK_L_(0x2A, 0x7A) ++#define REG_SC_BK2A_7A_H _PK_H_(0x2A, 0x7A) ++#define REG_SC_BK2A_7B_L _PK_L_(0x2A, 0x7B) ++#define REG_SC_BK2A_7B_H _PK_H_(0x2A, 0x7B) ++#define REG_SC_BK2A_7C_L _PK_L_(0x2A, 0x7C) ++#define REG_SC_BK2A_7C_H _PK_H_(0x2A, 0x7C) ++#define REG_SC_BK2A_7D_L _PK_L_(0x2A, 0x7D) ++#define REG_SC_BK2A_7D_H _PK_H_(0x2A, 0x7D) ++#define REG_SC_BK2A_7E_L _PK_L_(0x2A, 0x7E) ++#define REG_SC_BK2A_7E_H _PK_H_(0x2A, 0x7E) ++#define REG_SC_BK2A_7F_L _PK_L_(0x2A, 0x7F) ++#define REG_SC_BK2A_7F_H _PK_H_(0x2A, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK2B_00_L _PK_L_(0x2B, 0x00) ++#define REG_SC_BK2B_00_H _PK_H_(0x2B, 0x00) ++#define REG_SC_BK2B_01_L _PK_L_(0x2B, 0x01) ++#define REG_SC_BK2B_01_H _PK_H_(0x2B, 0x01) ++#define REG_SC_BK2B_02_L _PK_L_(0x2B, 0x02) ++#define REG_SC_BK2B_02_H _PK_H_(0x2B, 0x02) ++#define REG_SC_BK2B_03_L _PK_L_(0x2B, 0x03) ++#define REG_SC_BK2B_03_H _PK_H_(0x2B, 0x03) ++#define REG_SC_BK2B_04_L _PK_L_(0x2B, 0x04) ++#define REG_SC_BK2B_04_H _PK_H_(0x2B, 0x04) ++#define REG_SC_BK2B_05_L _PK_L_(0x2B, 0x05) ++#define REG_SC_BK2B_05_H _PK_H_(0x2B, 0x05) ++#define REG_SC_BK2B_06_L _PK_L_(0x2B, 0x06) ++#define REG_SC_BK2B_06_H _PK_H_(0x2B, 0x06) ++#define REG_SC_BK2B_07_L _PK_L_(0x2B, 0x07) ++#define REG_SC_BK2B_07_H _PK_H_(0x2B, 0x07) ++#define REG_SC_BK2B_08_L _PK_L_(0x2B, 0x08) ++#define REG_SC_BK2B_08_H _PK_H_(0x2B, 0x08) ++#define REG_SC_BK2B_09_L _PK_L_(0x2B, 0x09) ++#define REG_SC_BK2B_09_H _PK_H_(0x2B, 0x09) ++#define REG_SC_BK2B_0A_L _PK_L_(0x2B, 0x0A) ++#define REG_SC_BK2B_0A_H _PK_H_(0x2B, 0x0A) ++#define REG_SC_BK2B_0B_L _PK_L_(0x2B, 0x0B) ++#define REG_SC_BK2B_0B_H _PK_H_(0x2B, 0x0B) ++#define REG_SC_BK2B_0C_L _PK_L_(0x2B, 0x0C) ++#define REG_SC_BK2B_0C_H _PK_H_(0x2B, 0x0C) ++#define REG_SC_BK2B_0D_L _PK_L_(0x2B, 0x0D) ++#define REG_SC_BK2B_0D_H _PK_H_(0x2B, 0x0D) ++#define REG_SC_BK2B_0E_L _PK_L_(0x2B, 0x0E) ++#define REG_SC_BK2B_0E_H _PK_H_(0x2B, 0x0E) ++#define REG_SC_BK2B_0F_L _PK_L_(0x2B, 0x0F) ++#define REG_SC_BK2B_0F_H _PK_H_(0x2B, 0x0F) ++#define REG_SC_BK2B_10_L _PK_L_(0x2B, 0x10) ++#define REG_SC_BK2B_10_H _PK_H_(0x2B, 0x10) ++#define REG_SC_BK2B_11_L _PK_L_(0x2B, 0x11) ++#define REG_SC_BK2B_11_H _PK_H_(0x2B, 0x11) ++#define REG_SC_BK2B_12_L _PK_L_(0x2B, 0x12) ++#define REG_SC_BK2B_12_H _PK_H_(0x2B, 0x12) ++#define REG_SC_BK2B_13_L _PK_L_(0x2B, 0x13) ++#define REG_SC_BK2B_13_H _PK_H_(0x2B, 0x13) ++#define REG_SC_BK2B_14_L _PK_L_(0x2B, 0x14) ++#define REG_SC_BK2B_14_H _PK_H_(0x2B, 0x14) ++#define REG_SC_BK2B_15_L _PK_L_(0x2B, 0x15) ++#define REG_SC_BK2B_15_H _PK_H_(0x2B, 0x15) ++#define REG_SC_BK2B_16_L _PK_L_(0x2B, 0x16) ++#define REG_SC_BK2B_16_H _PK_H_(0x2B, 0x16) ++#define REG_SC_BK2B_17_L _PK_L_(0x2B, 0x17) ++#define REG_SC_BK2B_17_H _PK_H_(0x2B, 0x17) ++#define REG_SC_BK2B_18_L _PK_L_(0x2B, 0x18) ++#define REG_SC_BK2B_18_H _PK_H_(0x2B, 0x18) ++#define REG_SC_BK2B_19_L _PK_L_(0x2B, 0x19) ++#define REG_SC_BK2B_19_H _PK_H_(0x2B, 0x19) ++#define REG_SC_BK2B_1A_L _PK_L_(0x2B, 0x1A) ++#define REG_SC_BK2B_1A_H _PK_H_(0x2B, 0x1A) ++#define REG_SC_BK2B_1B_L _PK_L_(0x2B, 0x1B) ++#define REG_SC_BK2B_1B_H _PK_H_(0x2B, 0x1B) ++#define REG_SC_BK2B_1C_L _PK_L_(0x2B, 0x1C) ++#define REG_SC_BK2B_1C_H _PK_H_(0x2B, 0x1C) ++#define REG_SC_BK2B_1D_L _PK_L_(0x2B, 0x1D) ++#define REG_SC_BK2B_1D_H _PK_H_(0x2B, 0x1D) ++#define REG_SC_BK2B_1E_L _PK_L_(0x2B, 0x1E) ++#define REG_SC_BK2B_1E_H _PK_H_(0x2B, 0x1E) ++#define REG_SC_BK2B_1F_L _PK_L_(0x2B, 0x1F) ++#define REG_SC_BK2B_1F_H _PK_H_(0x2B, 0x1F) ++#define REG_SC_BK2B_20_L _PK_L_(0x2B, 0x20) ++#define REG_SC_BK2B_20_H _PK_H_(0x2B, 0x20) ++#define REG_SC_BK2B_21_L _PK_L_(0x2B, 0x21) ++#define REG_SC_BK2B_21_H _PK_H_(0x2B, 0x21) ++#define REG_SC_BK2B_22_L _PK_L_(0x2B, 0x22) ++#define REG_SC_BK2B_22_H _PK_H_(0x2B, 0x22) ++#define REG_SC_BK2B_23_L _PK_L_(0x2B, 0x23) ++#define REG_SC_BK2B_23_H _PK_H_(0x2B, 0x23) ++#define REG_SC_BK2B_24_L _PK_L_(0x2B, 0x24) ++#define REG_SC_BK2B_24_H _PK_H_(0x2B, 0x24) ++#define REG_SC_BK2B_25_L _PK_L_(0x2B, 0x25) ++#define REG_SC_BK2B_25_H _PK_H_(0x2B, 0x25) ++#define REG_SC_BK2B_26_L _PK_L_(0x2B, 0x26) ++#define REG_SC_BK2B_26_H _PK_H_(0x2B, 0x26) ++#define REG_SC_BK2B_27_L _PK_L_(0x2B, 0x27) ++#define REG_SC_BK2B_27_H _PK_H_(0x2B, 0x27) ++#define REG_SC_BK2B_28_L _PK_L_(0x2B, 0x28) ++#define REG_SC_BK2B_28_H _PK_H_(0x2B, 0x28) ++#define REG_SC_BK2B_29_L _PK_L_(0x2B, 0x29) ++#define REG_SC_BK2B_29_H _PK_H_(0x2B, 0x29) ++#define REG_SC_BK2B_2A_L _PK_L_(0x2B, 0x2A) ++#define REG_SC_BK2B_2A_H _PK_H_(0x2B, 0x2A) ++#define REG_SC_BK2B_2B_L _PK_L_(0x2B, 0x2B) ++#define REG_SC_BK2B_2B_H _PK_H_(0x2B, 0x2B) ++#define REG_SC_BK2B_2C_L _PK_L_(0x2B, 0x2C) ++#define REG_SC_BK2B_2C_H _PK_H_(0x2B, 0x2C) ++#define REG_SC_BK2B_2D_L _PK_L_(0x2B, 0x2D) ++#define REG_SC_BK2B_2D_H _PK_H_(0x2B, 0x2D) ++#define REG_SC_BK2B_2E_L _PK_L_(0x2B, 0x2E) ++#define REG_SC_BK2B_2E_H _PK_H_(0x2B, 0x2E) ++#define REG_SC_BK2B_2F_L _PK_L_(0x2B, 0x2F) ++#define REG_SC_BK2B_2F_H _PK_H_(0x2B, 0x2F) ++#define REG_SC_BK2B_30_L _PK_L_(0x2B, 0x30) ++#define REG_SC_BK2B_30_H _PK_H_(0x2B, 0x30) ++#define REG_SC_BK2B_31_L _PK_L_(0x2B, 0x31) ++#define REG_SC_BK2B_31_H _PK_H_(0x2B, 0x31) ++#define REG_SC_BK2B_32_L _PK_L_(0x2B, 0x32) ++#define REG_SC_BK2B_32_H _PK_H_(0x2B, 0x32) ++#define REG_SC_BK2B_33_L _PK_L_(0x2B, 0x33) ++#define REG_SC_BK2B_33_H _PK_H_(0x2B, 0x33) ++#define REG_SC_BK2B_34_L _PK_L_(0x2B, 0x34) ++#define REG_SC_BK2B_34_H _PK_H_(0x2B, 0x34) ++#define REG_SC_BK2B_35_L _PK_L_(0x2B, 0x35) ++#define REG_SC_BK2B_35_H _PK_H_(0x2B, 0x35) ++#define REG_SC_BK2B_36_L _PK_L_(0x2B, 0x36) ++#define REG_SC_BK2B_36_H _PK_H_(0x2B, 0x36) ++#define REG_SC_BK2B_37_L _PK_L_(0x2B, 0x37) ++#define REG_SC_BK2B_37_H _PK_H_(0x2B, 0x37) ++#define REG_SC_BK2B_38_L _PK_L_(0x2B, 0x38) ++#define REG_SC_BK2B_38_H _PK_H_(0x2B, 0x38) ++#define REG_SC_BK2B_39_L _PK_L_(0x2B, 0x39) ++#define REG_SC_BK2B_39_H _PK_H_(0x2B, 0x39) ++#define REG_SC_BK2B_3A_L _PK_L_(0x2B, 0x3A) ++#define REG_SC_BK2B_3A_H _PK_H_(0x2B, 0x3A) ++#define REG_SC_BK2B_3B_L _PK_L_(0x2B, 0x3B) ++#define REG_SC_BK2B_3B_H _PK_H_(0x2B, 0x3B) ++#define REG_SC_BK2B_3C_L _PK_L_(0x2B, 0x3C) ++#define REG_SC_BK2B_3C_H _PK_H_(0x2B, 0x3C) ++#define REG_SC_BK2B_3D_L _PK_L_(0x2B, 0x3D) ++#define REG_SC_BK2B_3D_H _PK_H_(0x2B, 0x3D) ++#define REG_SC_BK2B_3E_L _PK_L_(0x2B, 0x3E) ++#define REG_SC_BK2B_3E_H _PK_H_(0x2B, 0x3E) ++#define REG_SC_BK2B_3F_L _PK_L_(0x2B, 0x3F) ++#define REG_SC_BK2B_3F_H _PK_H_(0x2B, 0x3F) ++#define REG_SC_BK2B_40_L _PK_L_(0x2B, 0x40) ++#define REG_SC_BK2B_40_H _PK_H_(0x2B, 0x40) ++#define REG_SC_BK2B_41_L _PK_L_(0x2B, 0x41) ++#define REG_SC_BK2B_41_H _PK_H_(0x2B, 0x41) ++#define REG_SC_BK2B_42_L _PK_L_(0x2B, 0x42) ++#define REG_SC_BK2B_42_H _PK_H_(0x2B, 0x42) ++#define REG_SC_BK2B_43_L _PK_L_(0x2B, 0x43) ++#define REG_SC_BK2B_43_H _PK_H_(0x2B, 0x43) ++#define REG_SC_BK2B_44_L _PK_L_(0x2B, 0x44) ++#define REG_SC_BK2B_44_H _PK_H_(0x2B, 0x44) ++#define REG_SC_BK2B_45_L _PK_L_(0x2B, 0x45) ++#define REG_SC_BK2B_45_H _PK_H_(0x2B, 0x45) ++#define REG_SC_BK2B_46_L _PK_L_(0x2B, 0x46) ++#define REG_SC_BK2B_46_H _PK_H_(0x2B, 0x46) ++#define REG_SC_BK2B_47_L _PK_L_(0x2B, 0x47) ++#define REG_SC_BK2B_47_H _PK_H_(0x2B, 0x47) ++#define REG_SC_BK2B_48_L _PK_L_(0x2B, 0x48) ++#define REG_SC_BK2B_48_H _PK_H_(0x2B, 0x48) ++#define REG_SC_BK2B_49_L _PK_L_(0x2B, 0x49) ++#define REG_SC_BK2B_49_H _PK_H_(0x2B, 0x49) ++#define REG_SC_BK2B_4A_L _PK_L_(0x2B, 0x4A) ++#define REG_SC_BK2B_4A_H _PK_H_(0x2B, 0x4A) ++#define REG_SC_BK2B_4B_L _PK_L_(0x2B, 0x4B) ++#define REG_SC_BK2B_4B_H _PK_H_(0x2B, 0x4B) ++#define REG_SC_BK2B_4C_L _PK_L_(0x2B, 0x4C) ++#define REG_SC_BK2B_4C_H _PK_H_(0x2B, 0x4C) ++#define REG_SC_BK2B_4D_L _PK_L_(0x2B, 0x4D) ++#define REG_SC_BK2B_4D_H _PK_H_(0x2B, 0x4D) ++#define REG_SC_BK2B_4E_L _PK_L_(0x2B, 0x4E) ++#define REG_SC_BK2B_4E_H _PK_H_(0x2B, 0x4E) ++#define REG_SC_BK2B_4F_L _PK_L_(0x2B, 0x4F) ++#define REG_SC_BK2B_4F_H _PK_H_(0x2B, 0x4F) ++#define REG_SC_BK2B_50_L _PK_L_(0x2B, 0x50) ++#define REG_SC_BK2B_50_H _PK_H_(0x2B, 0x50) ++#define REG_SC_BK2B_51_L _PK_L_(0x2B, 0x51) ++#define REG_SC_BK2B_51_H _PK_H_(0x2B, 0x51) ++#define REG_SC_BK2B_52_L _PK_L_(0x2B, 0x52) ++#define REG_SC_BK2B_52_H _PK_H_(0x2B, 0x52) ++#define REG_SC_BK2B_53_L _PK_L_(0x2B, 0x53) ++#define REG_SC_BK2B_53_H _PK_H_(0x2B, 0x53) ++#define REG_SC_BK2B_54_L _PK_L_(0x2B, 0x54) ++#define REG_SC_BK2B_54_H _PK_H_(0x2B, 0x54) ++#define REG_SC_BK2B_55_L _PK_L_(0x2B, 0x55) ++#define REG_SC_BK2B_55_H _PK_H_(0x2B, 0x55) ++#define REG_SC_BK2B_56_L _PK_L_(0x2B, 0x56) ++#define REG_SC_BK2B_56_H _PK_H_(0x2B, 0x56) ++#define REG_SC_BK2B_57_L _PK_L_(0x2B, 0x57) ++#define REG_SC_BK2B_57_H _PK_H_(0x2B, 0x57) ++#define REG_SC_BK2B_58_L _PK_L_(0x2B, 0x58) ++#define REG_SC_BK2B_58_H _PK_H_(0x2B, 0x58) ++#define REG_SC_BK2B_59_L _PK_L_(0x2B, 0x59) ++#define REG_SC_BK2B_59_H _PK_H_(0x2B, 0x59) ++#define REG_SC_BK2B_5A_L _PK_L_(0x2B, 0x5A) ++#define REG_SC_BK2B_5A_H _PK_H_(0x2B, 0x5A) ++#define REG_SC_BK2B_5B_L _PK_L_(0x2B, 0x5B) ++#define REG_SC_BK2B_5B_H _PK_H_(0x2B, 0x5B) ++#define REG_SC_BK2B_5C_L _PK_L_(0x2B, 0x5C) ++#define REG_SC_BK2B_5C_H _PK_H_(0x2B, 0x5C) ++#define REG_SC_BK2B_5D_L _PK_L_(0x2B, 0x5D) ++#define REG_SC_BK2B_5D_H _PK_H_(0x2B, 0x5D) ++#define REG_SC_BK2B_5E_L _PK_L_(0x2B, 0x5E) ++#define REG_SC_BK2B_5E_H _PK_H_(0x2B, 0x5E) ++#define REG_SC_BK2B_5F_L _PK_L_(0x2B, 0x5F) ++#define REG_SC_BK2B_5F_H _PK_H_(0x2B, 0x5F) ++#define REG_SC_BK2B_60_L _PK_L_(0x2B, 0x60) ++#define REG_SC_BK2B_60_H _PK_H_(0x2B, 0x60) ++#define REG_SC_BK2B_61_L _PK_L_(0x2B, 0x61) ++#define REG_SC_BK2B_61_H _PK_H_(0x2B, 0x61) ++#define REG_SC_BK2B_62_L _PK_L_(0x2B, 0x62) ++#define REG_SC_BK2B_62_H _PK_H_(0x2B, 0x62) ++#define REG_SC_BK2B_63_L _PK_L_(0x2B, 0x63) ++#define REG_SC_BK2B_63_H _PK_H_(0x2B, 0x63) ++#define REG_SC_BK2B_64_L _PK_L_(0x2B, 0x64) ++#define REG_SC_BK2B_64_H _PK_H_(0x2B, 0x64) ++#define REG_SC_BK2B_65_L _PK_L_(0x2B, 0x65) ++#define REG_SC_BK2B_65_H _PK_H_(0x2B, 0x65) ++#define REG_SC_BK2B_66_L _PK_L_(0x2B, 0x66) ++#define REG_SC_BK2B_66_H _PK_H_(0x2B, 0x66) ++#define REG_SC_BK2B_67_L _PK_L_(0x2B, 0x67) ++#define REG_SC_BK2B_67_H _PK_H_(0x2B, 0x67) ++#define REG_SC_BK2B_68_L _PK_L_(0x2B, 0x68) ++#define REG_SC_BK2B_68_H _PK_H_(0x2B, 0x68) ++#define REG_SC_BK2B_69_L _PK_L_(0x2B, 0x69) ++#define REG_SC_BK2B_69_H _PK_H_(0x2B, 0x69) ++#define REG_SC_BK2B_6A_L _PK_L_(0x2B, 0x6A) ++#define REG_SC_BK2B_6A_H _PK_H_(0x2B, 0x6A) ++#define REG_SC_BK2B_6B_L _PK_L_(0x2B, 0x6B) ++#define REG_SC_BK2B_6B_H _PK_H_(0x2B, 0x6B) ++#define REG_SC_BK2B_6C_L _PK_L_(0x2B, 0x6C) ++#define REG_SC_BK2B_6C_H _PK_H_(0x2B, 0x6C) ++#define REG_SC_BK2B_6D_L _PK_L_(0x2B, 0x6D) ++#define REG_SC_BK2B_6D_H _PK_H_(0x2B, 0x6D) ++#define REG_SC_BK2B_6E_L _PK_L_(0x2B, 0x6E) ++#define REG_SC_BK2B_6E_H _PK_H_(0x2B, 0x6E) ++#define REG_SC_BK2B_6F_L _PK_L_(0x2B, 0x6F) ++#define REG_SC_BK2B_6F_H _PK_H_(0x2B, 0x6F) ++#define REG_SC_BK2B_70_L _PK_L_(0x2B, 0x70) ++#define REG_SC_BK2B_70_H _PK_H_(0x2B, 0x70) ++#define REG_SC_BK2B_71_L _PK_L_(0x2B, 0x71) ++#define REG_SC_BK2B_71_H _PK_H_(0x2B, 0x71) ++#define REG_SC_BK2B_72_L _PK_L_(0x2B, 0x72) ++#define REG_SC_BK2B_72_H _PK_H_(0x2B, 0x72) ++#define REG_SC_BK2B_73_L _PK_L_(0x2B, 0x73) ++#define REG_SC_BK2B_73_H _PK_H_(0x2B, 0x73) ++#define REG_SC_BK2B_74_L _PK_L_(0x2B, 0x74) ++#define REG_SC_BK2B_74_H _PK_H_(0x2B, 0x74) ++#define REG_SC_BK2B_75_L _PK_L_(0x2B, 0x75) ++#define REG_SC_BK2B_75_H _PK_H_(0x2B, 0x75) ++#define REG_SC_BK2B_76_L _PK_L_(0x2B, 0x76) ++#define REG_SC_BK2B_76_H _PK_H_(0x2B, 0x76) ++#define REG_SC_BK2B_77_L _PK_L_(0x2B, 0x77) ++#define REG_SC_BK2B_77_H _PK_H_(0x2B, 0x77) ++#define REG_SC_BK2B_78_L _PK_L_(0x2B, 0x78) ++#define REG_SC_BK2B_78_H _PK_H_(0x2B, 0x78) ++#define REG_SC_BK2B_79_L _PK_L_(0x2B, 0x79) ++#define REG_SC_BK2B_79_H _PK_H_(0x2B, 0x79) ++#define REG_SC_BK2B_7A_L _PK_L_(0x2B, 0x7A) ++#define REG_SC_BK2B_7A_H _PK_H_(0x2B, 0x7A) ++#define REG_SC_BK2B_7B_L _PK_L_(0x2B, 0x7B) ++#define REG_SC_BK2B_7B_H _PK_H_(0x2B, 0x7B) ++#define REG_SC_BK2B_7C_L _PK_L_(0x2B, 0x7C) ++#define REG_SC_BK2B_7C_H _PK_H_(0x2B, 0x7C) ++#define REG_SC_BK2B_7D_L _PK_L_(0x2B, 0x7D) ++#define REG_SC_BK2B_7D_H _PK_H_(0x2B, 0x7D) ++#define REG_SC_BK2B_7E_L _PK_L_(0x2B, 0x7E) ++#define REG_SC_BK2B_7E_H _PK_H_(0x2B, 0x7E) ++#define REG_SC_BK2B_7F_L _PK_L_(0x2B, 0x7F) ++#define REG_SC_BK2B_7F_H _PK_H_(0x2B, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK2C_00_L _PK_L_(0x2C, 0x00) ++#define REG_SC_BK2C_00_H _PK_H_(0x2C, 0x00) ++#define REG_SC_BK2C_01_L _PK_L_(0x2C, 0x01) ++#define REG_SC_BK2C_01_H _PK_H_(0x2C, 0x01) ++#define REG_SC_BK2C_02_L _PK_L_(0x2C, 0x02) ++#define REG_SC_BK2C_02_H _PK_H_(0x2C, 0x02) ++#define REG_SC_BK2C_03_L _PK_L_(0x2C, 0x03) ++#define REG_SC_BK2C_03_H _PK_H_(0x2C, 0x03) ++#define REG_SC_BK2C_04_L _PK_L_(0x2C, 0x04) ++#define REG_SC_BK2C_04_H _PK_H_(0x2C, 0x04) ++#define REG_SC_BK2C_05_L _PK_L_(0x2C, 0x05) ++#define REG_SC_BK2C_05_H _PK_H_(0x2C, 0x05) ++#define REG_SC_BK2C_06_L _PK_L_(0x2C, 0x06) ++#define REG_SC_BK2C_06_H _PK_H_(0x2C, 0x06) ++#define REG_SC_BK2C_07_L _PK_L_(0x2C, 0x07) ++#define REG_SC_BK2C_07_H _PK_H_(0x2C, 0x07) ++#define REG_SC_BK2C_08_L _PK_L_(0x2C, 0x08) ++#define REG_SC_BK2C_08_H _PK_H_(0x2C, 0x08) ++#define REG_SC_BK2C_09_L _PK_L_(0x2C, 0x09) ++#define REG_SC_BK2C_09_H _PK_H_(0x2C, 0x09) ++#define REG_SC_BK2C_0A_L _PK_L_(0x2C, 0x0A) ++#define REG_SC_BK2C_0A_H _PK_H_(0x2C, 0x0A) ++#define REG_SC_BK2C_0B_L _PK_L_(0x2C, 0x0B) ++#define REG_SC_BK2C_0B_H _PK_H_(0x2C, 0x0B) ++#define REG_SC_BK2C_0C_L _PK_L_(0x2C, 0x0C) ++#define REG_SC_BK2C_0C_H _PK_H_(0x2C, 0x0C) ++#define REG_SC_BK2C_0D_L _PK_L_(0x2C, 0x0D) ++#define REG_SC_BK2C_0D_H _PK_H_(0x2C, 0x0D) ++#define REG_SC_BK2C_0E_L _PK_L_(0x2C, 0x0E) ++#define REG_SC_BK2C_0E_H _PK_H_(0x2C, 0x0E) ++#define REG_SC_BK2C_0F_L _PK_L_(0x2C, 0x0F) ++#define REG_SC_BK2C_0F_H _PK_H_(0x2C, 0x0F) ++#define REG_SC_BK2C_10_L _PK_L_(0x2C, 0x10) ++#define REG_SC_BK2C_10_H _PK_H_(0x2C, 0x10) ++#define REG_SC_BK2C_11_L _PK_L_(0x2C, 0x11) ++#define REG_SC_BK2C_11_H _PK_H_(0x2C, 0x11) ++#define REG_SC_BK2C_12_L _PK_L_(0x2C, 0x12) ++#define REG_SC_BK2C_12_H _PK_H_(0x2C, 0x12) ++#define REG_SC_BK2C_13_L _PK_L_(0x2C, 0x13) ++#define REG_SC_BK2C_13_H _PK_H_(0x2C, 0x13) ++#define REG_SC_BK2C_14_L _PK_L_(0x2C, 0x14) ++#define REG_SC_BK2C_14_H _PK_H_(0x2C, 0x14) ++#define REG_SC_BK2C_15_L _PK_L_(0x2C, 0x15) ++#define REG_SC_BK2C_15_H _PK_H_(0x2C, 0x15) ++#define REG_SC_BK2C_16_L _PK_L_(0x2C, 0x16) ++#define REG_SC_BK2C_16_H _PK_H_(0x2C, 0x16) ++#define REG_SC_BK2C_17_L _PK_L_(0x2C, 0x17) ++#define REG_SC_BK2C_17_H _PK_H_(0x2C, 0x17) ++#define REG_SC_BK2C_18_L _PK_L_(0x2C, 0x18) ++#define REG_SC_BK2C_18_H _PK_H_(0x2C, 0x18) ++#define REG_SC_BK2C_19_L _PK_L_(0x2C, 0x19) ++#define REG_SC_BK2C_19_H _PK_H_(0x2C, 0x19) ++#define REG_SC_BK2C_1A_L _PK_L_(0x2C, 0x1A) ++#define REG_SC_BK2C_1A_H _PK_H_(0x2C, 0x1A) ++#define REG_SC_BK2C_1B_L _PK_L_(0x2C, 0x1B) ++#define REG_SC_BK2C_1B_H _PK_H_(0x2C, 0x1B) ++#define REG_SC_BK2C_1C_L _PK_L_(0x2C, 0x1C) ++#define REG_SC_BK2C_1C_H _PK_H_(0x2C, 0x1C) ++#define REG_SC_BK2C_1D_L _PK_L_(0x2C, 0x1D) ++#define REG_SC_BK2C_1D_H _PK_H_(0x2C, 0x1D) ++#define REG_SC_BK2C_1E_L _PK_L_(0x2C, 0x1E) ++#define REG_SC_BK2C_1E_H _PK_H_(0x2C, 0x1E) ++#define REG_SC_BK2C_1F_L _PK_L_(0x2C, 0x1F) ++#define REG_SC_BK2C_1F_H _PK_H_(0x2C, 0x1F) ++#define REG_SC_BK2C_20_L _PK_L_(0x2C, 0x20) ++#define REG_SC_BK2C_20_H _PK_H_(0x2C, 0x20) ++#define REG_SC_BK2C_21_L _PK_L_(0x2C, 0x21) ++#define REG_SC_BK2C_21_H _PK_H_(0x2C, 0x21) ++#define REG_SC_BK2C_22_L _PK_L_(0x2C, 0x22) ++#define REG_SC_BK2C_22_H _PK_H_(0x2C, 0x22) ++#define REG_SC_BK2C_23_L _PK_L_(0x2C, 0x23) ++#define REG_SC_BK2C_23_H _PK_H_(0x2C, 0x23) ++#define REG_SC_BK2C_24_L _PK_L_(0x2C, 0x24) ++#define REG_SC_BK2C_24_H _PK_H_(0x2C, 0x24) ++#define REG_SC_BK2C_25_L _PK_L_(0x2C, 0x25) ++#define REG_SC_BK2C_25_H _PK_H_(0x2C, 0x25) ++#define REG_SC_BK2C_26_L _PK_L_(0x2C, 0x26) ++#define REG_SC_BK2C_26_H _PK_H_(0x2C, 0x26) ++#define REG_SC_BK2C_27_L _PK_L_(0x2C, 0x27) ++#define REG_SC_BK2C_27_H _PK_H_(0x2C, 0x27) ++#define REG_SC_BK2C_28_L _PK_L_(0x2C, 0x28) ++#define REG_SC_BK2C_28_H _PK_H_(0x2C, 0x28) ++#define REG_SC_BK2C_29_L _PK_L_(0x2C, 0x29) ++#define REG_SC_BK2C_29_H _PK_H_(0x2C, 0x29) ++#define REG_SC_BK2C_2A_L _PK_L_(0x2C, 0x2A) ++#define REG_SC_BK2C_2A_H _PK_H_(0x2C, 0x2A) ++#define REG_SC_BK2C_2B_L _PK_L_(0x2C, 0x2B) ++#define REG_SC_BK2C_2B_H _PK_H_(0x2C, 0x2B) ++#define REG_SC_BK2C_2C_L _PK_L_(0x2C, 0x2C) ++#define REG_SC_BK2C_2C_H _PK_H_(0x2C, 0x2C) ++#define REG_SC_BK2C_2D_L _PK_L_(0x2C, 0x2D) ++#define REG_SC_BK2C_2D_H _PK_H_(0x2C, 0x2D) ++#define REG_SC_BK2C_2E_L _PK_L_(0x2C, 0x2E) ++#define REG_SC_BK2C_2E_H _PK_H_(0x2C, 0x2E) ++#define REG_SC_BK2C_2F_L _PK_L_(0x2C, 0x2F) ++#define REG_SC_BK2C_2F_H _PK_H_(0x2C, 0x2F) ++#define REG_SC_BK2C_30_L _PK_L_(0x2C, 0x30) ++#define REG_SC_BK2C_30_H _PK_H_(0x2C, 0x30) ++#define REG_SC_BK2C_31_L _PK_L_(0x2C, 0x31) ++#define REG_SC_BK2C_31_H _PK_H_(0x2C, 0x31) ++#define REG_SC_BK2C_32_L _PK_L_(0x2C, 0x32) ++#define REG_SC_BK2C_32_H _PK_H_(0x2C, 0x32) ++#define REG_SC_BK2C_33_L _PK_L_(0x2C, 0x33) ++#define REG_SC_BK2C_33_H _PK_H_(0x2C, 0x33) ++#define REG_SC_BK2C_34_L _PK_L_(0x2C, 0x34) ++#define REG_SC_BK2C_34_H _PK_H_(0x2C, 0x34) ++#define REG_SC_BK2C_35_L _PK_L_(0x2C, 0x35) ++#define REG_SC_BK2C_35_H _PK_H_(0x2C, 0x35) ++#define REG_SC_BK2C_36_L _PK_L_(0x2C, 0x36) ++#define REG_SC_BK2C_36_H _PK_H_(0x2C, 0x36) ++#define REG_SC_BK2C_37_L _PK_L_(0x2C, 0x37) ++#define REG_SC_BK2C_37_H _PK_H_(0x2C, 0x37) ++#define REG_SC_BK2C_38_L _PK_L_(0x2C, 0x38) ++#define REG_SC_BK2C_38_H _PK_H_(0x2C, 0x38) ++#define REG_SC_BK2C_39_L _PK_L_(0x2C, 0x39) ++#define REG_SC_BK2C_39_H _PK_H_(0x2C, 0x39) ++#define REG_SC_BK2C_3A_L _PK_L_(0x2C, 0x3A) ++#define REG_SC_BK2C_3A_H _PK_H_(0x2C, 0x3A) ++#define REG_SC_BK2C_3B_L _PK_L_(0x2C, 0x3B) ++#define REG_SC_BK2C_3B_H _PK_H_(0x2C, 0x3B) ++#define REG_SC_BK2C_3C_L _PK_L_(0x2C, 0x3C) ++#define REG_SC_BK2C_3C_H _PK_H_(0x2C, 0x3C) ++#define REG_SC_BK2C_3D_L _PK_L_(0x2C, 0x3D) ++#define REG_SC_BK2C_3D_H _PK_H_(0x2C, 0x3D) ++#define REG_SC_BK2C_3E_L _PK_L_(0x2C, 0x3E) ++#define REG_SC_BK2C_3E_H _PK_H_(0x2C, 0x3E) ++#define REG_SC_BK2C_3F_L _PK_L_(0x2C, 0x3F) ++#define REG_SC_BK2C_3F_H _PK_H_(0x2C, 0x3F) ++#define REG_SC_BK2C_40_L _PK_L_(0x2C, 0x40) ++#define REG_SC_BK2C_40_H _PK_H_(0x2C, 0x40) ++#define REG_SC_BK2C_41_L _PK_L_(0x2C, 0x41) ++#define REG_SC_BK2C_41_H _PK_H_(0x2C, 0x41) ++#define REG_SC_BK2C_42_L _PK_L_(0x2C, 0x42) ++#define REG_SC_BK2C_42_H _PK_H_(0x2C, 0x42) ++#define REG_SC_BK2C_43_L _PK_L_(0x2C, 0x43) ++#define REG_SC_BK2C_43_H _PK_H_(0x2C, 0x43) ++#define REG_SC_BK2C_44_L _PK_L_(0x2C, 0x44) ++#define REG_SC_BK2C_44_H _PK_H_(0x2C, 0x44) ++#define REG_SC_BK2C_45_L _PK_L_(0x2C, 0x45) ++#define REG_SC_BK2C_45_H _PK_H_(0x2C, 0x45) ++#define REG_SC_BK2C_46_L _PK_L_(0x2C, 0x46) ++#define REG_SC_BK2C_46_H _PK_H_(0x2C, 0x46) ++#define REG_SC_BK2C_47_L _PK_L_(0x2C, 0x47) ++#define REG_SC_BK2C_47_H _PK_H_(0x2C, 0x47) ++#define REG_SC_BK2C_48_L _PK_L_(0x2C, 0x48) ++#define REG_SC_BK2C_48_H _PK_H_(0x2C, 0x48) ++#define REG_SC_BK2C_49_L _PK_L_(0x2C, 0x49) ++#define REG_SC_BK2C_49_H _PK_H_(0x2C, 0x49) ++#define REG_SC_BK2C_4A_L _PK_L_(0x2C, 0x4A) ++#define REG_SC_BK2C_4A_H _PK_H_(0x2C, 0x4A) ++#define REG_SC_BK2C_4B_L _PK_L_(0x2C, 0x4B) ++#define REG_SC_BK2C_4B_H _PK_H_(0x2C, 0x4B) ++#define REG_SC_BK2C_4C_L _PK_L_(0x2C, 0x4C) ++#define REG_SC_BK2C_4C_H _PK_H_(0x2C, 0x4C) ++#define REG_SC_BK2C_4D_L _PK_L_(0x2C, 0x4D) ++#define REG_SC_BK2C_4D_H _PK_H_(0x2C, 0x4D) ++#define REG_SC_BK2C_4E_L _PK_L_(0x2C, 0x4E) ++#define REG_SC_BK2C_4E_H _PK_H_(0x2C, 0x4E) ++#define REG_SC_BK2C_4F_L _PK_L_(0x2C, 0x4F) ++#define REG_SC_BK2C_4F_H _PK_H_(0x2C, 0x4F) ++#define REG_SC_BK2C_50_L _PK_L_(0x2C, 0x50) ++#define REG_SC_BK2C_50_H _PK_H_(0x2C, 0x50) ++#define REG_SC_BK2C_51_L _PK_L_(0x2C, 0x51) ++#define REG_SC_BK2C_51_H _PK_H_(0x2C, 0x51) ++#define REG_SC_BK2C_52_L _PK_L_(0x2C, 0x52) ++#define REG_SC_BK2C_52_H _PK_H_(0x2C, 0x52) ++#define REG_SC_BK2C_53_L _PK_L_(0x2C, 0x53) ++#define REG_SC_BK2C_53_H _PK_H_(0x2C, 0x53) ++#define REG_SC_BK2C_54_L _PK_L_(0x2C, 0x54) ++#define REG_SC_BK2C_54_H _PK_H_(0x2C, 0x54) ++#define REG_SC_BK2C_55_L _PK_L_(0x2C, 0x55) ++#define REG_SC_BK2C_55_H _PK_H_(0x2C, 0x55) ++#define REG_SC_BK2C_56_L _PK_L_(0x2C, 0x56) ++#define REG_SC_BK2C_56_H _PK_H_(0x2C, 0x56) ++#define REG_SC_BK2C_57_L _PK_L_(0x2C, 0x57) ++#define REG_SC_BK2C_57_H _PK_H_(0x2C, 0x57) ++#define REG_SC_BK2C_58_L _PK_L_(0x2C, 0x58) ++#define REG_SC_BK2C_58_H _PK_H_(0x2C, 0x58) ++#define REG_SC_BK2C_59_L _PK_L_(0x2C, 0x59) ++#define REG_SC_BK2C_59_H _PK_H_(0x2C, 0x59) ++#define REG_SC_BK2C_5A_L _PK_L_(0x2C, 0x5A) ++#define REG_SC_BK2C_5A_H _PK_H_(0x2C, 0x5A) ++#define REG_SC_BK2C_5B_L _PK_L_(0x2C, 0x5B) ++#define REG_SC_BK2C_5B_H _PK_H_(0x2C, 0x5B) ++#define REG_SC_BK2C_5C_L _PK_L_(0x2C, 0x5C) ++#define REG_SC_BK2C_5C_H _PK_H_(0x2C, 0x5C) ++#define REG_SC_BK2C_5D_L _PK_L_(0x2C, 0x5D) ++#define REG_SC_BK2C_5D_H _PK_H_(0x2C, 0x5D) ++#define REG_SC_BK2C_5E_L _PK_L_(0x2C, 0x5E) ++#define REG_SC_BK2C_5E_H _PK_H_(0x2C, 0x5E) ++#define REG_SC_BK2C_5F_L _PK_L_(0x2C, 0x5F) ++#define REG_SC_BK2C_5F_H _PK_H_(0x2C, 0x5F) ++#define REG_SC_BK2C_60_L _PK_L_(0x2C, 0x60) ++#define REG_SC_BK2C_60_H _PK_H_(0x2C, 0x60) ++#define REG_SC_BK2C_61_L _PK_L_(0x2C, 0x61) ++#define REG_SC_BK2C_61_H _PK_H_(0x2C, 0x61) ++#define REG_SC_BK2C_62_L _PK_L_(0x2C, 0x62) ++#define REG_SC_BK2C_62_H _PK_H_(0x2C, 0x62) ++#define REG_SC_BK2C_63_L _PK_L_(0x2C, 0x63) ++#define REG_SC_BK2C_63_H _PK_H_(0x2C, 0x63) ++#define REG_SC_BK2C_64_L _PK_L_(0x2C, 0x64) ++#define REG_SC_BK2C_64_H _PK_H_(0x2C, 0x64) ++#define REG_SC_BK2C_65_L _PK_L_(0x2C, 0x65) ++#define REG_SC_BK2C_65_H _PK_H_(0x2C, 0x65) ++#define REG_SC_BK2C_66_L _PK_L_(0x2C, 0x66) ++#define REG_SC_BK2C_66_H _PK_H_(0x2C, 0x66) ++#define REG_SC_BK2C_67_L _PK_L_(0x2C, 0x67) ++#define REG_SC_BK2C_67_H _PK_H_(0x2C, 0x67) ++#define REG_SC_BK2C_68_L _PK_L_(0x2C, 0x68) ++#define REG_SC_BK2C_68_H _PK_H_(0x2C, 0x68) ++#define REG_SC_BK2C_69_L _PK_L_(0x2C, 0x69) ++#define REG_SC_BK2C_69_H _PK_H_(0x2C, 0x69) ++#define REG_SC_BK2C_6A_L _PK_L_(0x2C, 0x6A) ++#define REG_SC_BK2C_6A_H _PK_H_(0x2C, 0x6A) ++#define REG_SC_BK2C_6B_L _PK_L_(0x2C, 0x6B) ++#define REG_SC_BK2C_6B_H _PK_H_(0x2C, 0x6B) ++#define REG_SC_BK2C_6C_L _PK_L_(0x2C, 0x6C) ++#define REG_SC_BK2C_6C_H _PK_H_(0x2C, 0x6C) ++#define REG_SC_BK2C_6D_L _PK_L_(0x2C, 0x6D) ++#define REG_SC_BK2C_6D_H _PK_H_(0x2C, 0x6D) ++#define REG_SC_BK2C_6E_L _PK_L_(0x2C, 0x6E) ++#define REG_SC_BK2C_6E_H _PK_H_(0x2C, 0x6E) ++#define REG_SC_BK2C_6F_L _PK_L_(0x2C, 0x6F) ++#define REG_SC_BK2C_6F_H _PK_H_(0x2C, 0x6F) ++#define REG_SC_BK2C_70_L _PK_L_(0x2C, 0x70) ++#define REG_SC_BK2C_70_H _PK_H_(0x2C, 0x70) ++#define REG_SC_BK2C_71_L _PK_L_(0x2C, 0x71) ++#define REG_SC_BK2C_71_H _PK_H_(0x2C, 0x71) ++#define REG_SC_BK2C_72_L _PK_L_(0x2C, 0x72) ++#define REG_SC_BK2C_72_H _PK_H_(0x2C, 0x72) ++#define REG_SC_BK2C_73_L _PK_L_(0x2C, 0x73) ++#define REG_SC_BK2C_73_H _PK_H_(0x2C, 0x73) ++#define REG_SC_BK2C_74_L _PK_L_(0x2C, 0x74) ++#define REG_SC_BK2C_74_H _PK_H_(0x2C, 0x74) ++#define REG_SC_BK2C_75_L _PK_L_(0x2C, 0x75) ++#define REG_SC_BK2C_75_H _PK_H_(0x2C, 0x75) ++#define REG_SC_BK2C_76_L _PK_L_(0x2C, 0x76) ++#define REG_SC_BK2C_76_H _PK_H_(0x2C, 0x76) ++#define REG_SC_BK2C_77_L _PK_L_(0x2C, 0x77) ++#define REG_SC_BK2C_77_H _PK_H_(0x2C, 0x77) ++#define REG_SC_BK2C_78_L _PK_L_(0x2C, 0x78) ++#define REG_SC_BK2C_78_H _PK_H_(0x2C, 0x78) ++#define REG_SC_BK2C_79_L _PK_L_(0x2C, 0x79) ++#define REG_SC_BK2C_79_H _PK_H_(0x2C, 0x79) ++#define REG_SC_BK2C_7A_L _PK_L_(0x2C, 0x7A) ++#define REG_SC_BK2C_7A_H _PK_H_(0x2C, 0x7A) ++#define REG_SC_BK2C_7B_L _PK_L_(0x2C, 0x7B) ++#define REG_SC_BK2C_7B_H _PK_H_(0x2C, 0x7B) ++#define REG_SC_BK2C_7C_L _PK_L_(0x2C, 0x7C) ++#define REG_SC_BK2C_7C_H _PK_H_(0x2C, 0x7C) ++#define REG_SC_BK2C_7D_L _PK_L_(0x2C, 0x7D) ++#define REG_SC_BK2C_7D_H _PK_H_(0x2C, 0x7D) ++#define REG_SC_BK2C_7E_L _PK_L_(0x2C, 0x7E) ++#define REG_SC_BK2C_7E_H _PK_H_(0x2C, 0x7E) ++#define REG_SC_BK2C_7F_L _PK_L_(0x2C, 0x7F) ++#define REG_SC_BK2C_7F_H _PK_H_(0x2C, 0x7F) ++#define REG_SC_BK30_01_L _PK_L_(0x30, 0x01) ++#define REG_SC_BK30_01_H _PK_H_(0x30, 0x01) ++#define REG_SC_BK30_02_L _PK_L_(0x30, 0x02) ++#define REG_SC_BK30_02_H _PK_H_(0x30, 0x02) ++#define REG_SC_BK30_03_L _PK_L_(0x30, 0x03) ++#define REG_SC_BK30_03_H _PK_H_(0x30, 0x03) ++//---------------------------------------------- ++#define REG_BK35_00_L 0x3500 ++#define REG_BK35_00_H 0x3501 ++#define REG_BK35_01_L 0x3502 ++#define REG_BK35_01_H 0x3503 ++#define REG_BK35_02_L 0x3504 ++#define REG_BK35_02_H 0x3505 ++#define REG_BK35_03_L 0x3506 ++#define REG_BK35_03_H 0x3507 ++#define REG_BK35_04_L 0x3508 ++#define REG_BK35_04_H 0x3509 ++#define REG_BK35_05_L 0x350A ++#define REG_BK35_05_H 0x350B ++#define REG_BK35_06_L 0x350C ++#define REG_BK35_06_H 0x350D ++#define REG_BK35_07_L 0x350E ++#define REG_BK35_07_H 0x350F ++#define REG_BK35_08_L 0x3510 ++#define REG_BK35_08_H 0x3511 ++#define REG_BK35_09_L 0x3512 ++#define REG_BK35_09_H 0x3513 ++#define REG_BK35_0A_L 0x3514 ++#define REG_BK35_0A_H 0x3515 ++#define REG_BK35_0B_L 0x3516 ++#define REG_BK35_0B_H 0x3517 ++#define REG_BK35_0C_L 0x3518 ++#define REG_BK35_0C_H 0x3519 ++#define REG_BK35_0D_L 0x351A ++#define REG_BK35_0D_H 0x351B ++#define REG_BK35_0E_L 0x351C ++#define REG_BK35_0E_H 0x351D ++#define REG_BK35_0F_L 0x351E ++#define REG_BK35_0F_H 0x351F ++#define REG_BK35_10_L 0x3520 ++#define REG_BK35_10_H 0x3521 ++#define REG_BK35_11_L 0x3522 ++#define REG_BK35_11_H 0x3523 ++#define REG_BK35_12_L 0x3524 ++#define REG_BK35_12_H 0x3525 ++#define REG_BK35_13_L 0x3526 ++#define REG_BK35_13_H 0x3527 ++#define REG_BK35_14_L 0x3528 ++#define REG_BK35_14_H 0x3529 ++#define REG_BK35_15_L 0x352A ++#define REG_BK35_15_H 0x352B ++#define REG_BK35_16_L 0x352C ++#define REG_BK35_16_H 0x352D ++#define REG_BK35_17_L 0x352E ++#define REG_BK35_17_H 0x352F ++#define REG_BK35_18_L 0x3530 ++#define REG_BK35_18_H 0x3531 ++#define REG_BK35_19_L 0x3532 ++#define REG_BK35_19_H 0x3533 ++#define REG_BK35_1A_L 0x3534 ++#define REG_BK35_1A_H 0x3535 ++#define REG_BK35_1B_L 0x3536 ++#define REG_BK35_1B_H 0x3537 ++#define REG_BK35_1C_L 0x3538 ++#define REG_BK35_1C_H 0x3539 ++#define REG_BK35_1D_L 0x353A ++#define REG_BK35_1D_H 0x353B ++#define REG_BK35_1E_L 0x353C ++#define REG_BK35_1E_H 0x353D ++#define REG_BK35_1F_L 0x353E ++#define REG_BK35_1F_H 0x353F ++#define REG_BK35_20_L 0x3540 ++#define REG_BK35_20_H 0x3541 ++#define REG_BK35_21_L 0x3542 ++#define REG_BK35_21_H 0x3543 ++#define REG_BK35_22_L 0x3544 ++#define REG_BK35_22_H 0x3545 ++#define REG_BK35_23_L 0x3546 ++#define REG_BK35_23_H 0x3547 ++#define REG_BK35_24_L 0x3548 ++#define REG_BK35_24_H 0x3549 ++#define REG_BK35_25_L 0x354A ++#define REG_BK35_25_H 0x354B ++#define REG_BK35_26_L 0x354C ++#define REG_BK35_26_H 0x354D ++#define REG_BK35_27_L 0x354E ++#define REG_BK35_27_H 0x354F ++#define REG_BK35_28_L 0x3550 ++#define REG_BK35_28_H 0x3551 ++#define REG_BK35_29_L 0x3552 ++#define REG_BK35_29_H 0x3553 ++#define REG_BK35_2A_L 0x3554 ++#define REG_BK35_2A_H 0x3555 ++#define REG_BK35_2B_L 0x3556 ++#define REG_BK35_2B_H 0x3557 ++#define REG_BK35_2C_L 0x3558 ++#define REG_BK35_2C_H 0x3559 ++#define REG_BK35_2D_L 0x355A ++#define REG_BK35_2D_H 0x355B ++#define REG_BK35_2E_L 0x355C ++#define REG_BK35_2E_H 0x355D ++#define REG_BK35_2F_L 0x355E ++#define REG_BK35_2F_H 0x355F ++#define REG_BK35_30_L 0x3560 ++#define REG_BK35_30_H 0x3561 ++#define REG_BK35_31_L 0x3562 ++#define REG_BK35_31_H 0x3563 ++#define REG_BK35_32_L 0x3564 ++#define REG_BK35_32_H 0x3565 ++#define REG_BK35_33_L 0x3566 ++#define REG_BK35_33_H 0x3567 ++#define REG_BK35_34_L 0x3568 ++#define REG_BK35_34_H 0x3569 ++#define REG_BK35_35_L 0x356A ++#define REG_BK35_35_H 0x356B ++#define REG_BK35_36_L 0x356C ++#define REG_BK35_36_H 0x356D ++#define REG_BK35_37_L 0x356E ++#define REG_BK35_37_H 0x356F ++#define REG_BK35_38_L 0x3570 ++#define REG_BK35_38_H 0x3571 ++#define REG_BK35_39_L 0x3572 ++#define REG_BK35_39_H 0x3573 ++#define REG_BK35_3A_L 0x3574 ++#define REG_BK35_3A_H 0x3575 ++#define REG_BK35_3B_L 0x3576 ++#define REG_BK35_3B_H 0x3577 ++#define REG_BK35_3C_L 0x3578 ++#define REG_BK35_3C_H 0x3579 ++#define REG_BK35_3D_L 0x357A ++#define REG_BK35_3D_H 0x357B ++#define REG_BK35_3E_L 0x357C ++#define REG_BK35_3E_H 0x357D ++#define REG_BK35_3F_L 0x357E ++#define REG_BK35_3F_H 0x357F ++#define REG_BK35_40_L 0x3580 ++#define REG_BK35_40_H 0x3581 ++#define REG_BK35_41_L 0x3582 ++#define REG_BK35_41_H 0x3583 ++#define REG_BK35_42_L 0x3584 ++#define REG_BK35_42_H 0x3585 ++#define REG_BK35_43_L 0x3586 ++#define REG_BK35_43_H 0x3587 ++#define REG_BK35_44_L 0x3588 ++#define REG_BK35_44_H 0x3589 ++#define REG_BK35_45_L 0x358A ++#define REG_BK35_45_H 0x358B ++#define REG_BK35_46_L 0x358C ++#define REG_BK35_46_H 0x358D ++#define REG_BK35_47_L 0x358E ++#define REG_BK35_47_H 0x358F ++#define REG_BK35_48_L 0x3590 ++#define REG_BK35_48_H 0x3591 ++#define REG_BK35_49_L 0x3592 ++#define REG_BK35_49_H 0x3593 ++#define REG_BK35_4A_L 0x3594 ++#define REG_BK35_4A_H 0x3595 ++#define REG_BK35_4B_L 0x3596 ++#define REG_BK35_4B_H 0x3597 ++#define REG_BK35_4C_L 0x3598 ++#define REG_BK35_4C_H 0x3599 ++#define REG_BK35_4D_L 0x359A ++#define REG_BK35_4D_H 0x359B ++#define REG_BK35_4E_L 0x359C ++#define REG_BK35_4E_H 0x359D ++#define REG_BK35_4F_L 0x359E ++#define REG_BK35_4F_H 0x359F ++#define REG_BK35_50_L 0x35A0 ++#define REG_BK35_50_H 0x35A1 ++#define REG_BK35_51_L 0x35A2 ++#define REG_BK35_51_H 0x35A3 ++#define REG_BK35_52_L 0x35A4 ++#define REG_BK35_52_H 0x35A5 ++#define REG_BK35_53_L 0x35A6 ++#define REG_BK35_53_H 0x35A7 ++#define REG_BK35_54_L 0x35A8 ++#define REG_BK35_54_H 0x35A9 ++#define REG_BK35_55_L 0x35AA ++#define REG_BK35_55_H 0x35AB ++#define REG_BK35_56_L 0x35AC ++#define REG_BK35_56_H 0x35AD ++#define REG_BK35_57_L 0x35AE ++#define REG_BK35_57_H 0x35AF ++#define REG_BK35_58_L 0x35B0 ++#define REG_BK35_58_H 0x35B1 ++#define REG_BK35_59_L 0x35B2 ++#define REG_BK35_59_H 0x35B3 ++#define REG_BK35_5A_L 0x35B4 ++#define REG_BK35_5A_H 0x35B5 ++#define REG_BK35_5B_L 0x35B6 ++#define REG_BK35_5B_H 0x35B7 ++#define REG_BK35_5C_L 0x35B8 ++#define REG_BK35_5C_H 0x35B9 ++#define REG_BK35_5D_L 0x35BA ++#define REG_BK35_5D_H 0x35BB ++#define REG_BK35_5E_L 0x35BC ++#define REG_BK35_5E_H 0x35BD ++#define REG_BK35_5F_L 0x35BE ++#define REG_BK35_5F_H 0x35BF ++#define REG_BK35_60_L 0x35C0 ++#define REG_BK35_60_H 0x35C1 ++#define REG_BK35_61_L 0x35C2 ++#define REG_BK35_61_H 0x35C3 ++#define REG_BK35_62_L 0x35C4 ++#define REG_BK35_62_H 0x35C5 ++#define REG_BK35_63_L 0x35C6 ++#define REG_BK35_63_H 0x35C7 ++#define REG_BK35_64_L 0x35C8 ++#define REG_BK35_64_H 0x35C9 ++#define REG_BK35_65_L 0x35CA ++#define REG_BK35_65_H 0x35CB ++#define REG_BK35_66_L 0x35CC ++#define REG_BK35_66_H 0x35CD ++#define REG_BK35_67_L 0x35CE ++#define REG_BK35_67_H 0x35CF ++#define REG_BK35_68_L 0x35D0 ++#define REG_BK35_68_H 0x35D1 ++#define REG_BK35_69_L 0x35D2 ++#define REG_BK35_69_H 0x35D3 ++#define REG_BK35_6A_L 0x35D4 ++#define REG_BK35_6A_H 0x35D5 ++#define REG_BK35_6B_L 0x35D6 ++#define REG_BK35_6B_H 0x35D7 ++#define REG_BK35_6C_L 0x35D8 ++#define REG_BK35_6C_H 0x35D9 ++#define REG_BK35_6D_L 0x35DA ++#define REG_BK35_6D_H 0x35DB ++#define REG_BK35_6E_L 0x35DC ++#define REG_BK35_6E_H 0x35DD ++#define REG_BK35_6F_L 0x35DE ++#define REG_BK35_6F_H 0x35DF ++#define REG_BK35_70_L 0x35E0 ++#define REG_BK35_70_H 0x35E1 ++#define REG_BK35_71_L 0x35E2 ++#define REG_BK35_71_H 0x35E3 ++#define REG_BK35_72_L 0x35E4 ++#define REG_BK35_72_H 0x35E5 ++#define REG_BK35_73_L 0x35E6 ++#define REG_BK35_73_H 0x35E7 ++#define REG_BK35_74_L 0x35E8 ++#define REG_BK35_74_H 0x35E9 ++#define REG_BK35_75_L 0x35EA ++#define REG_BK35_75_H 0x35EB ++#define REG_BK35_76_L 0x35EC ++#define REG_BK35_76_H 0x35ED ++#define REG_BK35_77_L 0x35EE ++#define REG_BK35_77_H 0x35EF ++#define REG_BK35_78_L 0x35F0 ++#define REG_BK35_78_H 0x35F1 ++#define REG_BK35_79_L 0x35F2 ++#define REG_BK35_79_H 0x35F3 ++#define REG_BK35_7A_L 0x35F4 ++#define REG_BK35_7A_H 0x35F5 ++#define REG_BK35_7B_L 0x35F6 ++#define REG_BK35_7B_H 0x35F7 ++#define REG_BK35_7C_L 0x35F8 ++#define REG_BK35_7C_H 0x35F9 ++#define REG_BK35_7D_L 0x35FA ++#define REG_BK35_7D_H 0x35FB ++#define REG_BK35_7E_L 0x35FC ++#define REG_BK35_7E_H 0x35FD ++#define REG_BK35_7F_L 0x35FE ++#define REG_BK35_7F_H 0x35FF ++//---------------------------------------------- ++#define REG_COMB_BK00_00_L _PK_L_(0x00, 0x00) ++#define REG_COMB_BK00_00_H _PK_H_(0x00, 0x00) ++#define REG_COMB_BK00_01_L _PK_L_(0x00, 0x01) ++#define REG_COMB_BK00_01_H _PK_H_(0x00, 0x01) ++#define REG_COMB_BK00_02_L _PK_L_(0x00, 0x02) ++#define REG_COMB_BK00_02_H _PK_H_(0x00, 0x02) ++#define REG_COMB_BK00_03_L _PK_L_(0x00, 0x03) ++#define REG_COMB_BK00_03_H _PK_H_(0x00, 0x03) ++#define REG_COMB_BK00_04_L _PK_L_(0x00, 0x04) ++#define REG_COMB_BK00_04_H _PK_H_(0x00, 0x04) ++#define REG_COMB_BK00_05_L _PK_L_(0x00, 0x05) ++#define REG_COMB_BK00_05_H _PK_H_(0x00, 0x05) ++#define REG_COMB_BK00_06_L _PK_L_(0x00, 0x06) ++#define REG_COMB_BK00_06_H _PK_H_(0x00, 0x06) ++#define REG_COMB_BK00_07_L _PK_L_(0x00, 0x07) ++#define REG_COMB_BK00_07_H _PK_H_(0x00, 0x07) ++#define REG_COMB_BK00_08_L _PK_L_(0x00, 0x08) ++#define REG_COMB_BK00_08_H _PK_H_(0x00, 0x08) ++#define REG_COMB_BK00_09_L _PK_L_(0x00, 0x09) ++#define REG_COMB_BK00_09_H _PK_H_(0x00, 0x09) ++#define REG_COMB_BK00_0A_L _PK_L_(0x00, 0x0A) ++#define REG_COMB_BK00_0A_H _PK_H_(0x00, 0x0A) ++#define REG_COMB_BK00_0B_L _PK_L_(0x00, 0x0B) ++#define REG_COMB_BK00_0B_H _PK_H_(0x00, 0x0B) ++#define REG_COMB_BK00_0C_L _PK_L_(0x00, 0x0C) ++#define REG_COMB_BK00_0C_H _PK_H_(0x00, 0x0C) ++#define REG_COMB_BK00_0D_L _PK_L_(0x00, 0x0D) ++#define REG_COMB_BK00_0D_H _PK_H_(0x00, 0x0D) ++#define REG_COMB_BK00_0E_L _PK_L_(0x00, 0x0E) ++#define REG_COMB_BK00_0E_H _PK_H_(0x00, 0x0E) ++#define REG_COMB_BK00_0F_L _PK_L_(0x00, 0x0F) ++#define REG_COMB_BK00_0F_H _PK_H_(0x00, 0x0F) ++#define REG_COMB_BK00_10_L _PK_L_(0x00, 0x10) ++#define REG_COMB_BK00_10_H _PK_H_(0x00, 0x10) ++#define REG_COMB_BK00_11_L _PK_L_(0x00, 0x11) ++#define REG_COMB_BK00_11_H _PK_H_(0x00, 0x11) ++#define REG_COMB_BK00_12_L _PK_L_(0x00, 0x12) ++#define REG_COMB_BK00_12_H _PK_H_(0x00, 0x12) ++#define REG_COMB_BK00_13_L _PK_L_(0x00, 0x13) ++#define REG_COMB_BK00_13_H _PK_H_(0x00, 0x13) ++#define REG_COMB_BK00_14_L _PK_L_(0x00, 0x14) ++#define REG_COMB_BK00_14_H _PK_H_(0x00, 0x14) ++#define REG_COMB_BK00_15_L _PK_L_(0x00, 0x15) ++#define REG_COMB_BK00_15_H _PK_H_(0x00, 0x15) ++#define REG_COMB_BK00_16_L _PK_L_(0x00, 0x16) ++#define REG_COMB_BK00_16_H _PK_H_(0x00, 0x16) ++#define REG_COMB_BK00_17_L _PK_L_(0x00, 0x17) ++#define REG_COMB_BK00_17_H _PK_H_(0x00, 0x17) ++#define REG_COMB_BK00_18_L _PK_L_(0x00, 0x18) ++#define REG_COMB_BK00_18_H _PK_H_(0x00, 0x18) ++#define REG_COMB_BK00_19_L _PK_L_(0x00, 0x19) ++#define REG_COMB_BK00_19_H _PK_H_(0x00, 0x19) ++#define REG_COMB_BK00_1A_L _PK_L_(0x00, 0x1A) ++#define REG_COMB_BK00_1A_H _PK_H_(0x00, 0x1A) ++#define REG_COMB_BK00_1B_L _PK_L_(0x00, 0x1B) ++#define REG_COMB_BK00_1B_H _PK_H_(0x00, 0x1B) ++#define REG_COMB_BK00_1C_L _PK_L_(0x00, 0x1C) ++#define REG_COMB_BK00_1C_H _PK_H_(0x00, 0x1C) ++#define REG_COMB_BK00_1D_L _PK_L_(0x00, 0x1D) ++#define REG_COMB_BK00_1D_H _PK_H_(0x00, 0x1D) ++#define REG_COMB_BK00_1E_L _PK_L_(0x00, 0x1E) ++#define REG_COMB_BK00_1E_H _PK_H_(0x00, 0x1E) ++#define REG_COMB_BK00_1F_L _PK_L_(0x00, 0x1F) ++#define REG_COMB_BK00_1F_H _PK_H_(0x00, 0x1F) ++#define REG_COMB_BK00_20_L _PK_L_(0x00, 0x20) ++#define REG_COMB_BK00_20_H _PK_H_(0x00, 0x20) ++#define REG_COMB_BK00_21_L _PK_L_(0x00, 0x21) ++#define REG_COMB_BK00_21_H _PK_H_(0x00, 0x21) ++#define REG_COMB_BK00_22_L _PK_L_(0x00, 0x22) ++#define REG_COMB_BK00_22_H _PK_H_(0x00, 0x22) ++#define REG_COMB_BK00_23_L _PK_L_(0x00, 0x23) ++#define REG_COMB_BK00_23_H _PK_H_(0x00, 0x23) ++#define REG_COMB_BK00_24_L _PK_L_(0x00, 0x24) ++#define REG_COMB_BK00_24_H _PK_H_(0x00, 0x24) ++#define REG_COMB_BK00_25_L _PK_L_(0x00, 0x25) ++#define REG_COMB_BK00_25_H _PK_H_(0x00, 0x25) ++#define REG_COMB_BK00_26_L _PK_L_(0x00, 0x26) ++#define REG_COMB_BK00_26_H _PK_H_(0x00, 0x26) ++#define REG_COMB_BK00_27_L _PK_L_(0x00, 0x27) ++#define REG_COMB_BK00_27_H _PK_H_(0x00, 0x27) ++#define REG_COMB_BK00_28_L _PK_L_(0x00, 0x28) ++#define REG_COMB_BK00_28_H _PK_H_(0x00, 0x28) ++#define REG_COMB_BK00_29_L _PK_L_(0x00, 0x29) ++#define REG_COMB_BK00_29_H _PK_H_(0x00, 0x29) ++#define REG_COMB_BK00_2A_L _PK_L_(0x00, 0x2A) ++#define REG_COMB_BK00_2A_H _PK_H_(0x00, 0x2A) ++#define REG_COMB_BK00_2B_L _PK_L_(0x00, 0x2B) ++#define REG_COMB_BK00_2B_H _PK_H_(0x00, 0x2B) ++#define REG_COMB_BK00_2C_L _PK_L_(0x00, 0x2C) ++#define REG_COMB_BK00_2C_H _PK_H_(0x00, 0x2C) ++#define REG_COMB_BK00_2D_L _PK_L_(0x00, 0x2D) ++#define REG_COMB_BK00_2D_H _PK_H_(0x00, 0x2D) ++#define REG_COMB_BK00_2E_L _PK_L_(0x00, 0x2E) ++#define REG_COMB_BK00_2E_H _PK_H_(0x00, 0x2E) ++#define REG_COMB_BK00_2F_L _PK_L_(0x00, 0x2F) ++#define REG_COMB_BK00_2F_H _PK_H_(0x00, 0x2F) ++#define REG_COMB_BK00_30_L _PK_L_(0x00, 0x30) ++#define REG_COMB_BK00_30_H _PK_H_(0x00, 0x30) ++#define REG_COMB_BK00_31_L _PK_L_(0x00, 0x31) ++#define REG_COMB_BK00_31_H _PK_H_(0x00, 0x31) ++#define REG_COMB_BK00_32_L _PK_L_(0x00, 0x32) ++#define REG_COMB_BK00_32_H _PK_H_(0x00, 0x32) ++#define REG_COMB_BK00_33_L _PK_L_(0x00, 0x33) ++#define REG_COMB_BK00_33_H _PK_H_(0x00, 0x33) ++#define REG_COMB_BK00_34_L _PK_L_(0x00, 0x34) ++#define REG_COMB_BK00_34_H _PK_H_(0x00, 0x34) ++#define REG_COMB_BK00_35_L _PK_L_(0x00, 0x35) ++#define REG_COMB_BK00_35_H _PK_H_(0x00, 0x35) ++#define REG_COMB_BK00_36_L _PK_L_(0x00, 0x36) ++#define REG_COMB_BK00_36_H _PK_H_(0x00, 0x36) ++#define REG_COMB_BK00_37_L _PK_L_(0x00, 0x37) ++#define REG_COMB_BK00_37_H _PK_H_(0x00, 0x37) ++#define REG_COMB_BK00_38_L _PK_L_(0x00, 0x38) ++#define REG_COMB_BK00_38_H _PK_H_(0x00, 0x38) ++#define REG_COMB_BK00_39_L _PK_L_(0x00, 0x39) ++#define REG_COMB_BK00_39_H _PK_H_(0x00, 0x39) ++#define REG_COMB_BK00_3A_L _PK_L_(0x00, 0x3A) ++#define REG_COMB_BK00_3A_H _PK_H_(0x00, 0x3A) ++#define REG_COMB_BK00_3B_L _PK_L_(0x00, 0x3B) ++#define REG_COMB_BK00_3B_H _PK_H_(0x00, 0x3B) ++#define REG_COMB_BK00_3C_L _PK_L_(0x00, 0x3C) ++#define REG_COMB_BK00_3C_H _PK_H_(0x00, 0x3C) ++#define REG_COMB_BK00_3D_L _PK_L_(0x00, 0x3D) ++#define REG_COMB_BK00_3D_H _PK_H_(0x00, 0x3D) ++#define REG_COMB_BK00_3E_L _PK_L_(0x00, 0x3E) ++#define REG_COMB_BK00_3E_H _PK_H_(0x00, 0x3E) ++#define REG_COMB_BK00_3F_L _PK_L_(0x00, 0x3F) ++#define REG_COMB_BK00_3F_H _PK_H_(0x00, 0x3F) ++#define REG_COMB_BK00_40_L _PK_L_(0x00, 0x40) ++#define REG_COMB_BK00_40_H _PK_H_(0x00, 0x40) ++#define REG_COMB_BK00_41_L _PK_L_(0x00, 0x41) ++#define REG_COMB_BK00_41_H _PK_H_(0x00, 0x41) ++#define REG_COMB_BK00_42_L _PK_L_(0x00, 0x42) ++#define REG_COMB_BK00_42_H _PK_H_(0x00, 0x42) ++#define REG_COMB_BK00_43_L _PK_L_(0x00, 0x43) ++#define REG_COMB_BK00_43_H _PK_H_(0x00, 0x43) ++#define REG_COMB_BK00_44_L _PK_L_(0x00, 0x44) ++#define REG_COMB_BK00_44_H _PK_H_(0x00, 0x44) ++#define REG_COMB_BK00_45_L _PK_L_(0x00, 0x45) ++#define REG_COMB_BK00_45_H _PK_H_(0x00, 0x45) ++#define REG_COMB_BK00_46_L _PK_L_(0x00, 0x46) ++#define REG_COMB_BK00_46_H _PK_H_(0x00, 0x46) ++#define REG_COMB_BK00_47_L _PK_L_(0x00, 0x47) ++#define REG_COMB_BK00_47_H _PK_H_(0x00, 0x47) ++#define REG_COMB_BK00_48_L _PK_L_(0x00, 0x48) ++#define REG_COMB_BK00_48_H _PK_H_(0x00, 0x48) ++#define REG_COMB_BK00_49_L _PK_L_(0x00, 0x49) ++#define REG_COMB_BK00_49_H _PK_H_(0x00, 0x49) ++#define REG_COMB_BK00_4A_L _PK_L_(0x00, 0x4A) ++#define REG_COMB_BK00_4A_H _PK_H_(0x00, 0x4A) ++#define REG_COMB_BK00_4B_L _PK_L_(0x00, 0x4B) ++#define REG_COMB_BK00_4B_H _PK_H_(0x00, 0x4B) ++#define REG_COMB_BK00_4C_L _PK_L_(0x00, 0x4C) ++#define REG_COMB_BK00_4C_H _PK_H_(0x00, 0x4C) ++#define REG_COMB_BK00_4D_L _PK_L_(0x00, 0x4D) ++#define REG_COMB_BK00_4D_H _PK_H_(0x00, 0x4D) ++#define REG_COMB_BK00_4E_L _PK_L_(0x00, 0x4E) ++#define REG_COMB_BK00_4E_H _PK_H_(0x00, 0x4E) ++#define REG_COMB_BK00_4F_L _PK_L_(0x00, 0x4F) ++#define REG_COMB_BK00_4F_H _PK_H_(0x00, 0x4F) ++#define REG_COMB_BK00_50_L _PK_L_(0x00, 0x50) ++#define REG_COMB_BK00_50_H _PK_H_(0x00, 0x50) ++#define REG_COMB_BK00_51_L _PK_L_(0x00, 0x51) ++#define REG_COMB_BK00_51_H _PK_H_(0x00, 0x51) ++#define REG_COMB_BK00_52_L _PK_L_(0x00, 0x52) ++#define REG_COMB_BK00_52_H _PK_H_(0x00, 0x52) ++#define REG_COMB_BK00_53_L _PK_L_(0x00, 0x53) ++#define REG_COMB_BK00_53_H _PK_H_(0x00, 0x53) ++#define REG_COMB_BK00_54_L _PK_L_(0x00, 0x54) ++#define REG_COMB_BK00_54_H _PK_H_(0x00, 0x54) ++#define REG_COMB_BK00_55_L _PK_L_(0x00, 0x55) ++#define REG_COMB_BK00_55_H _PK_H_(0x00, 0x55) ++#define REG_COMB_BK00_56_L _PK_L_(0x00, 0x56) ++#define REG_COMB_BK00_56_H _PK_H_(0x00, 0x56) ++#define REG_COMB_BK00_57_L _PK_L_(0x00, 0x57) ++#define REG_COMB_BK00_57_H _PK_H_(0x00, 0x57) ++#define REG_COMB_BK00_58_L _PK_L_(0x00, 0x58) ++#define REG_COMB_BK00_58_H _PK_H_(0x00, 0x58) ++#define REG_COMB_BK00_59_L _PK_L_(0x00, 0x59) ++#define REG_COMB_BK00_59_H _PK_H_(0x00, 0x59) ++#define REG_COMB_BK00_5A_L _PK_L_(0x00, 0x5A) ++#define REG_COMB_BK00_5A_H _PK_H_(0x00, 0x5A) ++#define REG_COMB_BK00_5B_L _PK_L_(0x00, 0x5B) ++#define REG_COMB_BK00_5B_H _PK_H_(0x00, 0x5B) ++#define REG_COMB_BK00_5C_L _PK_L_(0x00, 0x5C) ++#define REG_COMB_BK00_5C_H _PK_H_(0x00, 0x5C) ++#define REG_COMB_BK00_5D_L _PK_L_(0x00, 0x5D) ++#define REG_COMB_BK00_5D_H _PK_H_(0x00, 0x5D) ++#define REG_COMB_BK00_5E_L _PK_L_(0x00, 0x5E) ++#define REG_COMB_BK00_5E_H _PK_H_(0x00, 0x5E) ++#define REG_COMB_BK00_5F_L _PK_L_(0x00, 0x5F) ++#define REG_COMB_BK00_5F_H _PK_H_(0x00, 0x5F) ++#define REG_COMB_BK00_60_L _PK_L_(0x00, 0x60) ++#define REG_COMB_BK00_60_H _PK_H_(0x00, 0x60) ++#define REG_COMB_BK00_61_L _PK_L_(0x00, 0x61) ++#define REG_COMB_BK00_61_H _PK_H_(0x00, 0x61) ++#define REG_COMB_BK00_62_L _PK_L_(0x00, 0x62) ++#define REG_COMB_BK00_62_H _PK_H_(0x00, 0x62) ++#define REG_COMB_BK00_63_L _PK_L_(0x00, 0x63) ++#define REG_COMB_BK00_63_H _PK_H_(0x00, 0x63) ++#define REG_COMB_BK00_64_L _PK_L_(0x00, 0x64) ++#define REG_COMB_BK00_64_H _PK_H_(0x00, 0x64) ++#define REG_COMB_BK00_65_L _PK_L_(0x00, 0x65) ++#define REG_COMB_BK00_65_H _PK_H_(0x00, 0x65) ++#define REG_COMB_BK00_66_L _PK_L_(0x00, 0x66) ++#define REG_COMB_BK00_66_H _PK_H_(0x00, 0x66) ++#define REG_COMB_BK00_67_L _PK_L_(0x00, 0x67) ++#define REG_COMB_BK00_67_H _PK_H_(0x00, 0x67) ++#define REG_COMB_BK00_68_L _PK_L_(0x00, 0x68) ++#define REG_COMB_BK00_68_H _PK_H_(0x00, 0x68) ++#define REG_COMB_BK00_69_L _PK_L_(0x00, 0x69) ++#define REG_COMB_BK00_69_H _PK_H_(0x00, 0x69) ++#define REG_COMB_BK00_6A_L _PK_L_(0x00, 0x6A) ++#define REG_COMB_BK00_6A_H _PK_H_(0x00, 0x6A) ++#define REG_COMB_BK00_6B_L _PK_L_(0x00, 0x6B) ++#define REG_COMB_BK00_6B_H _PK_H_(0x00, 0x6B) ++#define REG_COMB_BK00_6C_L _PK_L_(0x00, 0x6C) ++#define REG_COMB_BK00_6C_H _PK_H_(0x00, 0x6C) ++#define REG_COMB_BK00_6D_L _PK_L_(0x00, 0x6D) ++#define REG_COMB_BK00_6D_H _PK_H_(0x00, 0x6D) ++#define REG_COMB_BK00_6E_L _PK_L_(0x00, 0x6E) ++#define REG_COMB_BK00_6E_H _PK_H_(0x00, 0x6E) ++#define REG_COMB_BK00_6F_L _PK_L_(0x00, 0x6F) ++#define REG_COMB_BK00_6F_H _PK_H_(0x00, 0x6F) ++#define REG_COMB_BK00_70_L _PK_L_(0x00, 0x70) ++#define REG_COMB_BK00_70_H _PK_H_(0x00, 0x70) ++#define REG_COMB_BK00_71_L _PK_L_(0x00, 0x71) ++#define REG_COMB_BK00_71_H _PK_H_(0x00, 0x71) ++#define REG_COMB_BK00_72_L _PK_L_(0x00, 0x72) ++#define REG_COMB_BK00_72_H _PK_H_(0x00, 0x72) ++#define REG_COMB_BK00_73_L _PK_L_(0x00, 0x73) ++#define REG_COMB_BK00_73_H _PK_H_(0x00, 0x73) ++#define REG_COMB_BK00_74_L _PK_L_(0x00, 0x74) ++#define REG_COMB_BK00_74_H _PK_H_(0x00, 0x74) ++#define REG_COMB_BK00_75_L _PK_L_(0x00, 0x75) ++#define REG_COMB_BK00_75_H _PK_H_(0x00, 0x75) ++#define REG_COMB_BK00_76_L _PK_L_(0x00, 0x76) ++#define REG_COMB_BK00_76_H _PK_H_(0x00, 0x76) ++#define REG_COMB_BK00_77_L _PK_L_(0x00, 0x77) ++#define REG_COMB_BK00_77_H _PK_H_(0x00, 0x77) ++#define REG_COMB_BK00_78_L _PK_L_(0x00, 0x78) ++#define REG_COMB_BK00_78_H _PK_H_(0x00, 0x78) ++#define REG_COMB_BK00_79_L _PK_L_(0x00, 0x79) ++#define REG_COMB_BK00_79_H _PK_H_(0x00, 0x79) ++#define REG_COMB_BK00_7A_L _PK_L_(0x00, 0x7A) ++#define REG_COMB_BK00_7A_H _PK_H_(0x00, 0x7A) ++#define REG_COMB_BK00_7B_L _PK_L_(0x00, 0x7B) ++#define REG_COMB_BK00_7B_H _PK_H_(0x00, 0x7B) ++#define REG_COMB_BK00_7C_L _PK_L_(0x00, 0x7C) ++#define REG_COMB_BK00_7C_H _PK_H_(0x00, 0x7C) ++#define REG_COMB_BK00_7D_L _PK_L_(0x00, 0x7D) ++#define REG_COMB_BK00_7D_H _PK_H_(0x00, 0x7D) ++#define REG_COMB_BK00_7E_L _PK_L_(0x00, 0x7E) ++#define REG_COMB_BK00_7E_H _PK_H_(0x00, 0x7E) ++#define REG_COMB_BK00_7F_L _PK_L_(0x00, 0x7F) ++#define REG_COMB_BK00_7F_H _PK_H_(0x00, 0x7F) ++//---------------------------------------------- ++#define REG_COMB_BK01_00_L _PK_L_(0x01, 0x00) ++#define REG_COMB_BK01_00_H _PK_H_(0x01, 0x00) ++#define REG_COMB_BK01_01_L _PK_L_(0x01, 0x01) ++#define REG_COMB_BK01_01_H _PK_H_(0x01, 0x01) ++#define REG_COMB_BK01_02_L _PK_L_(0x01, 0x02) ++#define REG_COMB_BK01_02_H _PK_H_(0x01, 0x02) ++#define REG_COMB_BK01_03_L _PK_L_(0x01, 0x03) ++#define REG_COMB_BK01_03_H _PK_H_(0x01, 0x03) ++#define REG_COMB_BK01_04_L _PK_L_(0x01, 0x04) ++#define REG_COMB_BK01_04_H _PK_H_(0x01, 0x04) ++#define REG_COMB_BK01_05_L _PK_L_(0x01, 0x05) ++#define REG_COMB_BK01_05_H _PK_H_(0x01, 0x05) ++#define REG_COMB_BK01_06_L _PK_L_(0x01, 0x06) ++#define REG_COMB_BK01_06_H _PK_H_(0x01, 0x06) ++#define REG_COMB_BK01_07_L _PK_L_(0x01, 0x07) ++#define REG_COMB_BK01_07_H _PK_H_(0x01, 0x07) ++#define REG_COMB_BK01_08_L _PK_L_(0x01, 0x08) ++#define REG_COMB_BK01_08_H _PK_H_(0x01, 0x08) ++#define REG_COMB_BK01_09_L _PK_L_(0x01, 0x09) ++#define REG_COMB_BK01_09_H _PK_H_(0x01, 0x09) ++#define REG_COMB_BK01_0A_L _PK_L_(0x01, 0x0A) ++#define REG_COMB_BK01_0A_H _PK_H_(0x01, 0x0A) ++#define REG_COMB_BK01_0B_L _PK_L_(0x01, 0x0B) ++#define REG_COMB_BK01_0B_H _PK_H_(0x01, 0x0B) ++#define REG_COMB_BK01_0C_L _PK_L_(0x01, 0x0C) ++#define REG_COMB_BK01_0C_H _PK_H_(0x01, 0x0C) ++#define REG_COMB_BK01_0D_L _PK_L_(0x01, 0x0D) ++#define REG_COMB_BK01_0D_H _PK_H_(0x01, 0x0D) ++#define REG_COMB_BK01_0E_L _PK_L_(0x01, 0x0E) ++#define REG_COMB_BK01_0E_H _PK_H_(0x01, 0x0E) ++#define REG_COMB_BK01_0F_L _PK_L_(0x01, 0x0F) ++#define REG_COMB_BK01_0F_H _PK_H_(0x01, 0x0F) ++#define REG_COMB_BK01_10_L _PK_L_(0x01, 0x10) ++#define REG_COMB_BK01_10_H _PK_H_(0x01, 0x10) ++#define REG_COMB_BK01_11_L _PK_L_(0x01, 0x11) ++#define REG_COMB_BK01_11_H _PK_H_(0x01, 0x11) ++#define REG_COMB_BK01_12_L _PK_L_(0x01, 0x12) ++#define REG_COMB_BK01_12_H _PK_H_(0x01, 0x12) ++#define REG_COMB_BK01_13_L _PK_L_(0x01, 0x13) ++#define REG_COMB_BK01_13_H _PK_H_(0x01, 0x13) ++#define REG_COMB_BK01_14_L _PK_L_(0x01, 0x14) ++#define REG_COMB_BK01_14_H _PK_H_(0x01, 0x14) ++#define REG_COMB_BK01_15_L _PK_L_(0x01, 0x15) ++#define REG_COMB_BK01_15_H _PK_H_(0x01, 0x15) ++#define REG_COMB_BK01_16_L _PK_L_(0x01, 0x16) ++#define REG_COMB_BK01_16_H _PK_H_(0x01, 0x16) ++#define REG_COMB_BK01_17_L _PK_L_(0x01, 0x17) ++#define REG_COMB_BK01_17_H _PK_H_(0x01, 0x17) ++#define REG_COMB_BK01_18_L _PK_L_(0x01, 0x18) ++#define REG_COMB_BK01_18_H _PK_H_(0x01, 0x18) ++#define REG_COMB_BK01_19_L _PK_L_(0x01, 0x19) ++#define REG_COMB_BK01_19_H _PK_H_(0x01, 0x19) ++#define REG_COMB_BK01_1A_L _PK_L_(0x01, 0x1A) ++#define REG_COMB_BK01_1A_H _PK_H_(0x01, 0x1A) ++#define REG_COMB_BK01_1B_L _PK_L_(0x01, 0x1B) ++#define REG_COMB_BK01_1B_H _PK_H_(0x01, 0x1B) ++#define REG_COMB_BK01_1C_L _PK_L_(0x01, 0x1C) ++#define REG_COMB_BK01_1C_H _PK_H_(0x01, 0x1C) ++#define REG_COMB_BK01_1D_L _PK_L_(0x01, 0x1D) ++#define REG_COMB_BK01_1D_H _PK_H_(0x01, 0x1D) ++#define REG_COMB_BK01_1E_L _PK_L_(0x01, 0x1E) ++#define REG_COMB_BK01_1E_H _PK_H_(0x01, 0x1E) ++#define REG_COMB_BK01_1F_L _PK_L_(0x01, 0x1F) ++#define REG_COMB_BK01_1F_H _PK_H_(0x01, 0x1F) ++#define REG_COMB_BK01_20_L _PK_L_(0x01, 0x20) ++#define REG_COMB_BK01_20_H _PK_H_(0x01, 0x20) ++#define REG_COMB_BK01_21_L _PK_L_(0x01, 0x21) ++#define REG_COMB_BK01_21_H _PK_H_(0x01, 0x21) ++#define REG_COMB_BK01_22_L _PK_L_(0x01, 0x22) ++#define REG_COMB_BK01_22_H _PK_H_(0x01, 0x22) ++#define REG_COMB_BK01_23_L _PK_L_(0x01, 0x23) ++#define REG_COMB_BK01_23_H _PK_H_(0x01, 0x23) ++#define REG_COMB_BK01_24_L _PK_L_(0x01, 0x24) ++#define REG_COMB_BK01_24_H _PK_H_(0x01, 0x24) ++#define REG_COMB_BK01_25_L _PK_L_(0x01, 0x25) ++#define REG_COMB_BK01_25_H _PK_H_(0x01, 0x25) ++#define REG_COMB_BK01_26_L _PK_L_(0x01, 0x26) ++#define REG_COMB_BK01_26_H _PK_H_(0x01, 0x26) ++#define REG_COMB_BK01_27_L _PK_L_(0x01, 0x27) ++#define REG_COMB_BK01_27_H _PK_H_(0x01, 0x27) ++#define REG_COMB_BK01_28_L _PK_L_(0x01, 0x28) ++#define REG_COMB_BK01_28_H _PK_H_(0x01, 0x28) ++#define REG_COMB_BK01_29_L _PK_L_(0x01, 0x29) ++#define REG_COMB_BK01_29_H _PK_H_(0x01, 0x29) ++#define REG_COMB_BK01_2A_L _PK_L_(0x01, 0x2A) ++#define REG_COMB_BK01_2A_H _PK_H_(0x01, 0x2A) ++#define REG_COMB_BK01_2B_L _PK_L_(0x01, 0x2B) ++#define REG_COMB_BK01_2B_H _PK_H_(0x01, 0x2B) ++#define REG_COMB_BK01_2C_L _PK_L_(0x01, 0x2C) ++#define REG_COMB_BK01_2C_H _PK_H_(0x01, 0x2C) ++#define REG_COMB_BK01_2D_L _PK_L_(0x01, 0x2D) ++#define REG_COMB_BK01_2D_H _PK_H_(0x01, 0x2D) ++#define REG_COMB_BK01_2E_L _PK_L_(0x01, 0x2E) ++#define REG_COMB_BK01_2E_H _PK_H_(0x01, 0x2E) ++#define REG_COMB_BK01_2F_L _PK_L_(0x01, 0x2F) ++#define REG_COMB_BK01_2F_H _PK_H_(0x01, 0x2F) ++#define REG_COMB_BK01_30_L _PK_L_(0x01, 0x30) ++#define REG_COMB_BK01_30_H _PK_H_(0x01, 0x30) ++#define REG_COMB_BK01_31_L _PK_L_(0x01, 0x31) ++#define REG_COMB_BK01_31_H _PK_H_(0x01, 0x31) ++#define REG_COMB_BK01_32_L _PK_L_(0x01, 0x32) ++#define REG_COMB_BK01_32_H _PK_H_(0x01, 0x32) ++#define REG_COMB_BK01_33_L _PK_L_(0x01, 0x33) ++#define REG_COMB_BK01_33_H _PK_H_(0x01, 0x33) ++#define REG_COMB_BK01_34_L _PK_L_(0x01, 0x34) ++#define REG_COMB_BK01_34_H _PK_H_(0x01, 0x34) ++#define REG_COMB_BK01_35_L _PK_L_(0x01, 0x35) ++#define REG_COMB_BK01_35_H _PK_H_(0x01, 0x35) ++#define REG_COMB_BK01_36_L _PK_L_(0x01, 0x36) ++#define REG_COMB_BK01_36_H _PK_H_(0x01, 0x36) ++#define REG_COMB_BK01_37_L _PK_L_(0x01, 0x37) ++#define REG_COMB_BK01_37_H _PK_H_(0x01, 0x37) ++#define REG_COMB_BK01_38_L _PK_L_(0x01, 0x38) ++#define REG_COMB_BK01_38_H _PK_H_(0x01, 0x38) ++#define REG_COMB_BK01_39_L _PK_L_(0x01, 0x39) ++#define REG_COMB_BK01_39_H _PK_H_(0x01, 0x39) ++#define REG_COMB_BK01_3A_L _PK_L_(0x01, 0x3A) ++#define REG_COMB_BK01_3A_H _PK_H_(0x01, 0x3A) ++#define REG_COMB_BK01_3B_L _PK_L_(0x01, 0x3B) ++#define REG_COMB_BK01_3B_H _PK_H_(0x01, 0x3B) ++#define REG_COMB_BK01_3C_L _PK_L_(0x01, 0x3C) ++#define REG_COMB_BK01_3C_H _PK_H_(0x01, 0x3C) ++#define REG_COMB_BK01_3D_L _PK_L_(0x01, 0x3D) ++#define REG_COMB_BK01_3D_H _PK_H_(0x01, 0x3D) ++#define REG_COMB_BK01_3E_L _PK_L_(0x01, 0x3E) ++#define REG_COMB_BK01_3E_H _PK_H_(0x01, 0x3E) ++#define REG_COMB_BK01_3F_L _PK_L_(0x01, 0x3F) ++#define REG_COMB_BK01_3F_H _PK_H_(0x01, 0x3F) ++#define REG_COMB_BK01_40_L _PK_L_(0x01, 0x40) ++#define REG_COMB_BK01_40_H _PK_H_(0x01, 0x40) ++#define REG_COMB_BK01_41_L _PK_L_(0x01, 0x41) ++#define REG_COMB_BK01_41_H _PK_H_(0x01, 0x41) ++#define REG_COMB_BK01_42_L _PK_L_(0x01, 0x42) ++#define REG_COMB_BK01_42_H _PK_H_(0x01, 0x42) ++#define REG_COMB_BK01_43_L _PK_L_(0x01, 0x43) ++#define REG_COMB_BK01_43_H _PK_H_(0x01, 0x43) ++#define REG_COMB_BK01_44_L _PK_L_(0x01, 0x44) ++#define REG_COMB_BK01_44_H _PK_H_(0x01, 0x44) ++#define REG_COMB_BK01_45_L _PK_L_(0x01, 0x45) ++#define REG_COMB_BK01_45_H _PK_H_(0x01, 0x45) ++#define REG_COMB_BK01_46_L _PK_L_(0x01, 0x46) ++#define REG_COMB_BK01_46_H _PK_H_(0x01, 0x46) ++#define REG_COMB_BK01_47_L _PK_L_(0x01, 0x47) ++#define REG_COMB_BK01_47_H _PK_H_(0x01, 0x47) ++#define REG_COMB_BK01_48_L _PK_L_(0x01, 0x48) ++#define REG_COMB_BK01_48_H _PK_H_(0x01, 0x48) ++#define REG_COMB_BK01_49_L _PK_L_(0x01, 0x49) ++#define REG_COMB_BK01_49_H _PK_H_(0x01, 0x49) ++#define REG_COMB_BK01_4A_L _PK_L_(0x01, 0x4A) ++#define REG_COMB_BK01_4A_H _PK_H_(0x01, 0x4A) ++#define REG_COMB_BK01_4B_L _PK_L_(0x01, 0x4B) ++#define REG_COMB_BK01_4B_H _PK_H_(0x01, 0x4B) ++#define REG_COMB_BK01_4C_L _PK_L_(0x01, 0x4C) ++#define REG_COMB_BK01_4C_H _PK_H_(0x01, 0x4C) ++#define REG_COMB_BK01_4D_L _PK_L_(0x01, 0x4D) ++#define REG_COMB_BK01_4D_H _PK_H_(0x01, 0x4D) ++#define REG_COMB_BK01_4E_L _PK_L_(0x01, 0x4E) ++#define REG_COMB_BK01_4E_H _PK_H_(0x01, 0x4E) ++#define REG_COMB_BK01_4F_L _PK_L_(0x01, 0x4F) ++#define REG_COMB_BK01_4F_H _PK_H_(0x01, 0x4F) ++#define REG_COMB_BK01_50_L _PK_L_(0x01, 0x50) ++#define REG_COMB_BK01_50_H _PK_H_(0x01, 0x50) ++#define REG_COMB_BK01_51_L _PK_L_(0x01, 0x51) ++#define REG_COMB_BK01_51_H _PK_H_(0x01, 0x51) ++#define REG_COMB_BK01_52_L _PK_L_(0x01, 0x52) ++#define REG_COMB_BK01_52_H _PK_H_(0x01, 0x52) ++#define REG_COMB_BK01_53_L _PK_L_(0x01, 0x53) ++#define REG_COMB_BK01_53_H _PK_H_(0x01, 0x53) ++#define REG_COMB_BK01_54_L _PK_L_(0x01, 0x54) ++#define REG_COMB_BK01_54_H _PK_H_(0x01, 0x54) ++#define REG_COMB_BK01_55_L _PK_L_(0x01, 0x55) ++#define REG_COMB_BK01_55_H _PK_H_(0x01, 0x55) ++#define REG_COMB_BK01_56_L _PK_L_(0x01, 0x56) ++#define REG_COMB_BK01_56_H _PK_H_(0x01, 0x56) ++#define REG_COMB_BK01_57_L _PK_L_(0x01, 0x57) ++#define REG_COMB_BK01_57_H _PK_H_(0x01, 0x57) ++#define REG_COMB_BK01_58_L _PK_L_(0x01, 0x58) ++#define REG_COMB_BK01_58_H _PK_H_(0x01, 0x58) ++#define REG_COMB_BK01_59_L _PK_L_(0x01, 0x59) ++#define REG_COMB_BK01_59_H _PK_H_(0x01, 0x59) ++#define REG_COMB_BK01_5A_L _PK_L_(0x01, 0x5A) ++#define REG_COMB_BK01_5A_H _PK_H_(0x01, 0x5A) ++#define REG_COMB_BK01_5B_L _PK_L_(0x01, 0x5B) ++#define REG_COMB_BK01_5B_H _PK_H_(0x01, 0x5B) ++#define REG_COMB_BK01_5C_L _PK_L_(0x01, 0x5C) ++#define REG_COMB_BK01_5C_H _PK_H_(0x01, 0x5C) ++#define REG_COMB_BK01_5D_L _PK_L_(0x01, 0x5D) ++#define REG_COMB_BK01_5D_H _PK_H_(0x01, 0x5D) ++#define REG_COMB_BK01_5E_L _PK_L_(0x01, 0x5E) ++#define REG_COMB_BK01_5E_H _PK_H_(0x01, 0x5E) ++#define REG_COMB_BK01_5F_L _PK_L_(0x01, 0x5F) ++#define REG_COMB_BK01_5F_H _PK_H_(0x01, 0x5F) ++#define REG_COMB_BK01_60_L _PK_L_(0x01, 0x60) ++#define REG_COMB_BK01_60_H _PK_H_(0x01, 0x60) ++#define REG_COMB_BK01_61_L _PK_L_(0x01, 0x61) ++#define REG_COMB_BK01_61_H _PK_H_(0x01, 0x61) ++#define REG_COMB_BK01_62_L _PK_L_(0x01, 0x62) ++#define REG_COMB_BK01_62_H _PK_H_(0x01, 0x62) ++#define REG_COMB_BK01_63_L _PK_L_(0x01, 0x63) ++#define REG_COMB_BK01_63_H _PK_H_(0x01, 0x63) ++#define REG_COMB_BK01_64_L _PK_L_(0x01, 0x64) ++#define REG_COMB_BK01_64_H _PK_H_(0x01, 0x64) ++#define REG_COMB_BK01_65_L _PK_L_(0x01, 0x65) ++#define REG_COMB_BK01_65_H _PK_H_(0x01, 0x65) ++#define REG_COMB_BK01_66_L _PK_L_(0x01, 0x66) ++#define REG_COMB_BK01_66_H _PK_H_(0x01, 0x66) ++#define REG_COMB_BK01_67_L _PK_L_(0x01, 0x67) ++#define REG_COMB_BK01_67_H _PK_H_(0x01, 0x67) ++#define REG_COMB_BK01_68_L _PK_L_(0x01, 0x68) ++#define REG_COMB_BK01_68_H _PK_H_(0x01, 0x68) ++#define REG_COMB_BK01_69_L _PK_L_(0x01, 0x69) ++#define REG_COMB_BK01_69_H _PK_H_(0x01, 0x69) ++#define REG_COMB_BK01_6A_L _PK_L_(0x01, 0x6A) ++#define REG_COMB_BK01_6A_H _PK_H_(0x01, 0x6A) ++#define REG_COMB_BK01_6B_L _PK_L_(0x01, 0x6B) ++#define REG_COMB_BK01_6B_H _PK_H_(0x01, 0x6B) ++#define REG_COMB_BK01_6C_L _PK_L_(0x01, 0x6C) ++#define REG_COMB_BK01_6C_H _PK_H_(0x01, 0x6C) ++#define REG_COMB_BK01_6D_L _PK_L_(0x01, 0x6D) ++#define REG_COMB_BK01_6D_H _PK_H_(0x01, 0x6D) ++#define REG_COMB_BK01_6E_L _PK_L_(0x01, 0x6E) ++#define REG_COMB_BK01_6E_H _PK_H_(0x01, 0x6E) ++#define REG_COMB_BK01_6F_L _PK_L_(0x01, 0x6F) ++#define REG_COMB_BK01_6F_H _PK_H_(0x01, 0x6F) ++#define REG_COMB_BK01_70_L _PK_L_(0x01, 0x70) ++#define REG_COMB_BK01_70_H _PK_H_(0x01, 0x70) ++#define REG_COMB_BK01_71_L _PK_L_(0x01, 0x71) ++#define REG_COMB_BK01_71_H _PK_H_(0x01, 0x71) ++#define REG_COMB_BK01_72_L _PK_L_(0x01, 0x72) ++#define REG_COMB_BK01_72_H _PK_H_(0x01, 0x72) ++#define REG_COMB_BK01_73_L _PK_L_(0x01, 0x73) ++#define REG_COMB_BK01_73_H _PK_H_(0x01, 0x73) ++#define REG_COMB_BK01_74_L _PK_L_(0x01, 0x74) ++#define REG_COMB_BK01_74_H _PK_H_(0x01, 0x74) ++#define REG_COMB_BK01_75_L _PK_L_(0x01, 0x75) ++#define REG_COMB_BK01_75_H _PK_H_(0x01, 0x75) ++#define REG_COMB_BK01_76_L _PK_L_(0x01, 0x76) ++#define REG_COMB_BK01_76_H _PK_H_(0x01, 0x76) ++#define REG_COMB_BK01_77_L _PK_L_(0x01, 0x77) ++#define REG_COMB_BK01_77_H _PK_H_(0x01, 0x77) ++#define REG_COMB_BK01_78_L _PK_L_(0x01, 0x78) ++#define REG_COMB_BK01_78_H _PK_H_(0x01, 0x78) ++#define REG_COMB_BK01_79_L _PK_L_(0x01, 0x79) ++#define REG_COMB_BK01_79_H _PK_H_(0x01, 0x79) ++#define REG_COMB_BK01_7A_L _PK_L_(0x01, 0x7A) ++#define REG_COMB_BK01_7A_H _PK_H_(0x01, 0x7A) ++#define REG_COMB_BK01_7B_L _PK_L_(0x01, 0x7B) ++#define REG_COMB_BK01_7B_H _PK_H_(0x01, 0x7B) ++#define REG_COMB_BK01_7C_L _PK_L_(0x01, 0x7C) ++#define REG_COMB_BK01_7C_H _PK_H_(0x01, 0x7C) ++#define REG_COMB_BK01_7D_L _PK_L_(0x01, 0x7D) ++#define REG_COMB_BK01_7D_H _PK_H_(0x01, 0x7D) ++#define REG_COMB_BK01_7E_L _PK_L_(0x01, 0x7E) ++#define REG_COMB_BK01_7E_H _PK_H_(0x01, 0x7E) ++#define REG_COMB_BK01_7F_L _PK_L_(0x01, 0x7F) ++#define REG_COMB_BK01_7F_H _PK_H_(0x01, 0x7F) ++//---------------------------------------------- ++#define REG_COMB_BK02_00_L _PK_L_(0x02, 0x00) ++#define REG_COMB_BK02_00_H _PK_H_(0x02, 0x00) ++#define REG_COMB_BK02_01_L _PK_L_(0x02, 0x01) ++#define REG_COMB_BK02_01_H _PK_H_(0x02, 0x01) ++#define REG_COMB_BK02_02_L _PK_L_(0x02, 0x02) ++#define REG_COMB_BK02_02_H _PK_H_(0x02, 0x02) ++#define REG_COMB_BK02_03_L _PK_L_(0x02, 0x03) ++#define REG_COMB_BK02_03_H _PK_H_(0x02, 0x03) ++#define REG_COMB_BK02_04_L _PK_L_(0x02, 0x04) ++#define REG_COMB_BK02_04_H _PK_H_(0x02, 0x04) ++#define REG_COMB_BK02_05_L _PK_L_(0x02, 0x05) ++#define REG_COMB_BK02_05_H _PK_H_(0x02, 0x05) ++#define REG_COMB_BK02_06_L _PK_L_(0x02, 0x06) ++#define REG_COMB_BK02_06_H _PK_H_(0x02, 0x06) ++#define REG_COMB_BK02_07_L _PK_L_(0x02, 0x07) ++#define REG_COMB_BK02_07_H _PK_H_(0x02, 0x07) ++#define REG_COMB_BK02_08_L _PK_L_(0x02, 0x08) ++#define REG_COMB_BK02_08_H _PK_H_(0x02, 0x08) ++#define REG_COMB_BK02_09_L _PK_L_(0x02, 0x09) ++#define REG_COMB_BK02_09_H _PK_H_(0x02, 0x09) ++#define REG_COMB_BK02_0A_L _PK_L_(0x02, 0x0A) ++#define REG_COMB_BK02_0A_H _PK_H_(0x02, 0x0A) ++#define REG_COMB_BK02_0B_L _PK_L_(0x02, 0x0B) ++#define REG_COMB_BK02_0B_H _PK_H_(0x02, 0x0B) ++#define REG_COMB_BK02_0C_L _PK_L_(0x02, 0x0C) ++#define REG_COMB_BK02_0C_H _PK_H_(0x02, 0x0C) ++#define REG_COMB_BK02_0D_L _PK_L_(0x02, 0x0D) ++#define REG_COMB_BK02_0D_H _PK_H_(0x02, 0x0D) ++#define REG_COMB_BK02_0E_L _PK_L_(0x02, 0x0E) ++#define REG_COMB_BK02_0E_H _PK_H_(0x02, 0x0E) ++#define REG_COMB_BK02_0F_L _PK_L_(0x02, 0x0F) ++#define REG_COMB_BK02_0F_H _PK_H_(0x02, 0x0F) ++#define REG_COMB_BK02_10_L _PK_L_(0x02, 0x10) ++#define REG_COMB_BK02_10_H _PK_H_(0x02, 0x10) ++#define REG_COMB_BK02_11_L _PK_L_(0x02, 0x11) ++#define REG_COMB_BK02_11_H _PK_H_(0x02, 0x11) ++#define REG_COMB_BK02_12_L _PK_L_(0x02, 0x12) ++#define REG_COMB_BK02_12_H _PK_H_(0x02, 0x12) ++#define REG_COMB_BK02_13_L _PK_L_(0x02, 0x13) ++#define REG_COMB_BK02_13_H _PK_H_(0x02, 0x13) ++#define REG_COMB_BK02_14_L _PK_L_(0x02, 0x14) ++#define REG_COMB_BK02_14_H _PK_H_(0x02, 0x14) ++#define REG_COMB_BK02_15_L _PK_L_(0x02, 0x15) ++#define REG_COMB_BK02_15_H _PK_H_(0x02, 0x15) ++#define REG_COMB_BK02_16_L _PK_L_(0x02, 0x16) ++#define REG_COMB_BK02_16_H _PK_H_(0x02, 0x16) ++#define REG_COMB_BK02_17_L _PK_L_(0x02, 0x17) ++#define REG_COMB_BK02_17_H _PK_H_(0x02, 0x17) ++#define REG_COMB_BK02_18_L _PK_L_(0x02, 0x18) ++#define REG_COMB_BK02_18_H _PK_H_(0x02, 0x18) ++#define REG_COMB_BK02_19_L _PK_L_(0x02, 0x19) ++#define REG_COMB_BK02_19_H _PK_H_(0x02, 0x19) ++#define REG_COMB_BK02_1A_L _PK_L_(0x02, 0x1A) ++#define REG_COMB_BK02_1A_H _PK_H_(0x02, 0x1A) ++#define REG_COMB_BK02_1B_L _PK_L_(0x02, 0x1B) ++#define REG_COMB_BK02_1B_H _PK_H_(0x02, 0x1B) ++#define REG_COMB_BK02_1C_L _PK_L_(0x02, 0x1C) ++#define REG_COMB_BK02_1C_H _PK_H_(0x02, 0x1C) ++#define REG_COMB_BK02_1D_L _PK_L_(0x02, 0x1D) ++#define REG_COMB_BK02_1D_H _PK_H_(0x02, 0x1D) ++#define REG_COMB_BK02_1E_L _PK_L_(0x02, 0x1E) ++#define REG_COMB_BK02_1E_H _PK_H_(0x02, 0x1E) ++#define REG_COMB_BK02_1F_L _PK_L_(0x02, 0x1F) ++#define REG_COMB_BK02_1F_H _PK_H_(0x02, 0x1F) ++#define REG_COMB_BK02_20_L _PK_L_(0x02, 0x20) ++#define REG_COMB_BK02_20_H _PK_H_(0x02, 0x20) ++#define REG_COMB_BK02_21_L _PK_L_(0x02, 0x21) ++#define REG_COMB_BK02_21_H _PK_H_(0x02, 0x21) ++#define REG_COMB_BK02_22_L _PK_L_(0x02, 0x22) ++#define REG_COMB_BK02_22_H _PK_H_(0x02, 0x22) ++#define REG_COMB_BK02_23_L _PK_L_(0x02, 0x23) ++#define REG_COMB_BK02_23_H _PK_H_(0x02, 0x23) ++#define REG_COMB_BK02_24_L _PK_L_(0x02, 0x24) ++#define REG_COMB_BK02_24_H _PK_H_(0x02, 0x24) ++#define REG_COMB_BK02_25_L _PK_L_(0x02, 0x25) ++#define REG_COMB_BK02_25_H _PK_H_(0x02, 0x25) ++#define REG_COMB_BK02_26_L _PK_L_(0x02, 0x26) ++#define REG_COMB_BK02_26_H _PK_H_(0x02, 0x26) ++#define REG_COMB_BK02_27_L _PK_L_(0x02, 0x27) ++#define REG_COMB_BK02_27_H _PK_H_(0x02, 0x27) ++#define REG_COMB_BK02_28_L _PK_L_(0x02, 0x28) ++#define REG_COMB_BK02_28_H _PK_H_(0x02, 0x28) ++#define REG_COMB_BK02_29_L _PK_L_(0x02, 0x29) ++#define REG_COMB_BK02_29_H _PK_H_(0x02, 0x29) ++#define REG_COMB_BK02_2A_L _PK_L_(0x02, 0x2A) ++#define REG_COMB_BK02_2A_H _PK_H_(0x02, 0x2A) ++#define REG_COMB_BK02_2B_L _PK_L_(0x02, 0x2B) ++#define REG_COMB_BK02_2B_H _PK_H_(0x02, 0x2B) ++#define REG_COMB_BK02_2C_L _PK_L_(0x02, 0x2C) ++#define REG_COMB_BK02_2C_H _PK_H_(0x02, 0x2C) ++#define REG_COMB_BK02_2D_L _PK_L_(0x02, 0x2D) ++#define REG_COMB_BK02_2D_H _PK_H_(0x02, 0x2D) ++#define REG_COMB_BK02_2E_L _PK_L_(0x02, 0x2E) ++#define REG_COMB_BK02_2E_H _PK_H_(0x02, 0x2E) ++#define REG_COMB_BK02_2F_L _PK_L_(0x02, 0x2F) ++#define REG_COMB_BK02_2F_H _PK_H_(0x02, 0x2F) ++#define REG_COMB_BK02_30_L _PK_L_(0x02, 0x30) ++#define REG_COMB_BK02_30_H _PK_H_(0x02, 0x30) ++#define REG_COMB_BK02_31_L _PK_L_(0x02, 0x31) ++#define REG_COMB_BK02_31_H _PK_H_(0x02, 0x31) ++#define REG_COMB_BK02_32_L _PK_L_(0x02, 0x32) ++#define REG_COMB_BK02_32_H _PK_H_(0x02, 0x32) ++#define REG_COMB_BK02_33_L _PK_L_(0x02, 0x33) ++#define REG_COMB_BK02_33_H _PK_H_(0x02, 0x33) ++#define REG_COMB_BK02_34_L _PK_L_(0x02, 0x34) ++#define REG_COMB_BK02_34_H _PK_H_(0x02, 0x34) ++#define REG_COMB_BK02_35_L _PK_L_(0x02, 0x35) ++#define REG_COMB_BK02_35_H _PK_H_(0x02, 0x35) ++#define REG_COMB_BK02_36_L _PK_L_(0x02, 0x36) ++#define REG_COMB_BK02_36_H _PK_H_(0x02, 0x36) ++#define REG_COMB_BK02_37_L _PK_L_(0x02, 0x37) ++#define REG_COMB_BK02_37_H _PK_H_(0x02, 0x37) ++#define REG_COMB_BK02_38_L _PK_L_(0x02, 0x38) ++#define REG_COMB_BK02_38_H _PK_H_(0x02, 0x38) ++#define REG_COMB_BK02_39_L _PK_L_(0x02, 0x39) ++#define REG_COMB_BK02_39_H _PK_H_(0x02, 0x39) ++#define REG_COMB_BK02_3A_L _PK_L_(0x02, 0x3A) ++#define REG_COMB_BK02_3A_H _PK_H_(0x02, 0x3A) ++#define REG_COMB_BK02_3B_L _PK_L_(0x02, 0x3B) ++#define REG_COMB_BK02_3B_H _PK_H_(0x02, 0x3B) ++#define REG_COMB_BK02_3C_L _PK_L_(0x02, 0x3C) ++#define REG_COMB_BK02_3C_H _PK_H_(0x02, 0x3C) ++#define REG_COMB_BK02_3D_L _PK_L_(0x02, 0x3D) ++#define REG_COMB_BK02_3D_H _PK_H_(0x02, 0x3D) ++#define REG_COMB_BK02_3E_L _PK_L_(0x02, 0x3E) ++#define REG_COMB_BK02_3E_H _PK_H_(0x02, 0x3E) ++#define REG_COMB_BK02_3F_L _PK_L_(0x02, 0x3F) ++#define REG_COMB_BK02_3F_H _PK_H_(0x02, 0x3F) ++#define REG_COMB_BK02_40_L _PK_L_(0x02, 0x40) ++#define REG_COMB_BK02_40_H _PK_H_(0x02, 0x40) ++#define REG_COMB_BK02_41_L _PK_L_(0x02, 0x41) ++#define REG_COMB_BK02_41_H _PK_H_(0x02, 0x41) ++#define REG_COMB_BK02_42_L _PK_L_(0x02, 0x42) ++#define REG_COMB_BK02_42_H _PK_H_(0x02, 0x42) ++#define REG_COMB_BK02_43_L _PK_L_(0x02, 0x43) ++#define REG_COMB_BK02_43_H _PK_H_(0x02, 0x43) ++#define REG_COMB_BK02_44_L _PK_L_(0x02, 0x44) ++#define REG_COMB_BK02_44_H _PK_H_(0x02, 0x44) ++#define REG_COMB_BK02_45_L _PK_L_(0x02, 0x45) ++#define REG_COMB_BK02_45_H _PK_H_(0x02, 0x45) ++#define REG_COMB_BK02_46_L _PK_L_(0x02, 0x46) ++#define REG_COMB_BK02_46_H _PK_H_(0x02, 0x46) ++#define REG_COMB_BK02_47_L _PK_L_(0x02, 0x47) ++#define REG_COMB_BK02_47_H _PK_H_(0x02, 0x47) ++#define REG_COMB_BK02_48_L _PK_L_(0x02, 0x48) ++#define REG_COMB_BK02_48_H _PK_H_(0x02, 0x48) ++#define REG_COMB_BK02_49_L _PK_L_(0x02, 0x49) ++#define REG_COMB_BK02_49_H _PK_H_(0x02, 0x49) ++#define REG_COMB_BK02_4A_L _PK_L_(0x02, 0x4A) ++#define REG_COMB_BK02_4A_H _PK_H_(0x02, 0x4A) ++#define REG_COMB_BK02_4B_L _PK_L_(0x02, 0x4B) ++#define REG_COMB_BK02_4B_H _PK_H_(0x02, 0x4B) ++#define REG_COMB_BK02_4C_L _PK_L_(0x02, 0x4C) ++#define REG_COMB_BK02_4C_H _PK_H_(0x02, 0x4C) ++#define REG_COMB_BK02_4D_L _PK_L_(0x02, 0x4D) ++#define REG_COMB_BK02_4D_H _PK_H_(0x02, 0x4D) ++#define REG_COMB_BK02_4E_L _PK_L_(0x02, 0x4E) ++#define REG_COMB_BK02_4E_H _PK_H_(0x02, 0x4E) ++#define REG_COMB_BK02_4F_L _PK_L_(0x02, 0x4F) ++#define REG_COMB_BK02_4F_H _PK_H_(0x02, 0x4F) ++#define REG_COMB_BK02_50_L _PK_L_(0x02, 0x50) ++#define REG_COMB_BK02_50_H _PK_H_(0x02, 0x50) ++#define REG_COMB_BK02_51_L _PK_L_(0x02, 0x51) ++#define REG_COMB_BK02_51_H _PK_H_(0x02, 0x51) ++#define REG_COMB_BK02_52_L _PK_L_(0x02, 0x52) ++#define REG_COMB_BK02_52_H _PK_H_(0x02, 0x52) ++#define REG_COMB_BK02_53_L _PK_L_(0x02, 0x53) ++#define REG_COMB_BK02_53_H _PK_H_(0x02, 0x53) ++#define REG_COMB_BK02_54_L _PK_L_(0x02, 0x54) ++#define REG_COMB_BK02_54_H _PK_H_(0x02, 0x54) ++#define REG_COMB_BK02_55_L _PK_L_(0x02, 0x55) ++#define REG_COMB_BK02_55_H _PK_H_(0x02, 0x55) ++#define REG_COMB_BK02_56_L _PK_L_(0x02, 0x56) ++#define REG_COMB_BK02_56_H _PK_H_(0x02, 0x56) ++#define REG_COMB_BK02_57_L _PK_L_(0x02, 0x57) ++#define REG_COMB_BK02_57_H _PK_H_(0x02, 0x57) ++#define REG_COMB_BK02_58_L _PK_L_(0x02, 0x58) ++#define REG_COMB_BK02_58_H _PK_H_(0x02, 0x58) ++#define REG_COMB_BK02_59_L _PK_L_(0x02, 0x59) ++#define REG_COMB_BK02_59_H _PK_H_(0x02, 0x59) ++#define REG_COMB_BK02_5A_L _PK_L_(0x02, 0x5A) ++#define REG_COMB_BK02_5A_H _PK_H_(0x02, 0x5A) ++#define REG_COMB_BK02_5B_L _PK_L_(0x02, 0x5B) ++#define REG_COMB_BK02_5B_H _PK_H_(0x02, 0x5B) ++#define REG_COMB_BK02_5C_L _PK_L_(0x02, 0x5C) ++#define REG_COMB_BK02_5C_H _PK_H_(0x02, 0x5C) ++#define REG_COMB_BK02_5D_L _PK_L_(0x02, 0x5D) ++#define REG_COMB_BK02_5D_H _PK_H_(0x02, 0x5D) ++#define REG_COMB_BK02_5E_L _PK_L_(0x02, 0x5E) ++#define REG_COMB_BK02_5E_H _PK_H_(0x02, 0x5E) ++#define REG_COMB_BK02_5F_L _PK_L_(0x02, 0x5F) ++#define REG_COMB_BK02_5F_H _PK_H_(0x02, 0x5F) ++#define REG_COMB_BK02_60_L _PK_L_(0x02, 0x60) ++#define REG_COMB_BK02_60_H _PK_H_(0x02, 0x60) ++#define REG_COMB_BK02_61_L _PK_L_(0x02, 0x61) ++#define REG_COMB_BK02_61_H _PK_H_(0x02, 0x61) ++#define REG_COMB_BK02_62_L _PK_L_(0x02, 0x62) ++#define REG_COMB_BK02_62_H _PK_H_(0x02, 0x62) ++#define REG_COMB_BK02_63_L _PK_L_(0x02, 0x63) ++#define REG_COMB_BK02_63_H _PK_H_(0x02, 0x63) ++#define REG_COMB_BK02_64_L _PK_L_(0x02, 0x64) ++#define REG_COMB_BK02_64_H _PK_H_(0x02, 0x64) ++#define REG_COMB_BK02_65_L _PK_L_(0x02, 0x65) ++#define REG_COMB_BK02_65_H _PK_H_(0x02, 0x65) ++#define REG_COMB_BK02_66_L _PK_L_(0x02, 0x66) ++#define REG_COMB_BK02_66_H _PK_H_(0x02, 0x66) ++#define REG_COMB_BK02_67_L _PK_L_(0x02, 0x67) ++#define REG_COMB_BK02_67_H _PK_H_(0x02, 0x67) ++#define REG_COMB_BK02_68_L _PK_L_(0x02, 0x68) ++#define REG_COMB_BK02_68_H _PK_H_(0x02, 0x68) ++#define REG_COMB_BK02_69_L _PK_L_(0x02, 0x69) ++#define REG_COMB_BK02_69_H _PK_H_(0x02, 0x69) ++#define REG_COMB_BK02_6A_L _PK_L_(0x02, 0x6A) ++#define REG_COMB_BK02_6A_H _PK_H_(0x02, 0x6A) ++#define REG_COMB_BK02_6B_L _PK_L_(0x02, 0x6B) ++#define REG_COMB_BK02_6B_H _PK_H_(0x02, 0x6B) ++#define REG_COMB_BK02_6C_L _PK_L_(0x02, 0x6C) ++#define REG_COMB_BK02_6C_H _PK_H_(0x02, 0x6C) ++#define REG_COMB_BK02_6D_L _PK_L_(0x02, 0x6D) ++#define REG_COMB_BK02_6D_H _PK_H_(0x02, 0x6D) ++#define REG_COMB_BK02_6E_L _PK_L_(0x02, 0x6E) ++#define REG_COMB_BK02_6E_H _PK_H_(0x02, 0x6E) ++#define REG_COMB_BK02_6F_L _PK_L_(0x02, 0x6F) ++#define REG_COMB_BK02_6F_H _PK_H_(0x02, 0x6F) ++#define REG_COMB_BK02_70_L _PK_L_(0x02, 0x70) ++#define REG_COMB_BK02_70_H _PK_H_(0x02, 0x70) ++#define REG_COMB_BK02_71_L _PK_L_(0x02, 0x71) ++#define REG_COMB_BK02_71_H _PK_H_(0x02, 0x71) ++#define REG_COMB_BK02_72_L _PK_L_(0x02, 0x72) ++#define REG_COMB_BK02_72_H _PK_H_(0x02, 0x72) ++#define REG_COMB_BK02_73_L _PK_L_(0x02, 0x73) ++#define REG_COMB_BK02_73_H _PK_H_(0x02, 0x73) ++#define REG_COMB_BK02_74_L _PK_L_(0x02, 0x74) ++#define REG_COMB_BK02_74_H _PK_H_(0x02, 0x74) ++#define REG_COMB_BK02_75_L _PK_L_(0x02, 0x75) ++#define REG_COMB_BK02_75_H _PK_H_(0x02, 0x75) ++#define REG_COMB_BK02_76_L _PK_L_(0x02, 0x76) ++#define REG_COMB_BK02_76_H _PK_H_(0x02, 0x76) ++#define REG_COMB_BK02_77_L _PK_L_(0x02, 0x77) ++#define REG_COMB_BK02_77_H _PK_H_(0x02, 0x77) ++#define REG_COMB_BK02_78_L _PK_L_(0x02, 0x78) ++#define REG_COMB_BK02_78_H _PK_H_(0x02, 0x78) ++#define REG_COMB_BK02_79_L _PK_L_(0x02, 0x79) ++#define REG_COMB_BK02_79_H _PK_H_(0x02, 0x79) ++#define REG_COMB_BK02_7A_L _PK_L_(0x02, 0x7A) ++#define REG_COMB_BK02_7A_H _PK_H_(0x02, 0x7A) ++#define REG_COMB_BK02_7B_L _PK_L_(0x02, 0x7B) ++#define REG_COMB_BK02_7B_H _PK_H_(0x02, 0x7B) ++#define REG_COMB_BK02_7C_L _PK_L_(0x02, 0x7C) ++#define REG_COMB_BK02_7C_H _PK_H_(0x02, 0x7C) ++#define REG_COMB_BK02_7D_L _PK_L_(0x02, 0x7D) ++#define REG_COMB_BK02_7D_H _PK_H_(0x02, 0x7D) ++#define REG_COMB_BK02_7E_L _PK_L_(0x02, 0x7E) ++#define REG_COMB_BK02_7E_H _PK_H_(0x02, 0x7E) ++#define REG_COMB_BK02_7F_L _PK_L_(0x02, 0x7F) ++#define REG_COMB_BK02_7F_H _PK_H_(0x02, 0x7F) ++#define REG_COMB_BK03_00_L _PK_L_(0x03, 0x00) ++#define REG_COMB_BK03_00_H _PK_H_(0x03, 0x00) ++#define REG_COMB_BK03_01_L _PK_L_(0x03, 0x01) ++#define REG_COMB_BK03_01_H _PK_H_(0x03, 0x01) ++#define REG_COMB_BK03_02_L _PK_L_(0x03, 0x02) ++#define REG_COMB_BK03_02_H _PK_H_(0x03, 0x02) ++#define REG_COMB_BK03_03_L _PK_L_(0x03, 0x03) ++#define REG_COMB_BK03_03_H _PK_H_(0x03, 0x03) ++#define REG_COMB_BK03_04_L _PK_L_(0x03, 0x04) ++#define REG_COMB_BK03_04_H _PK_H_(0x03, 0x04) ++#define REG_COMB_BK03_05_L _PK_L_(0x03, 0x05) ++#define REG_COMB_BK03_05_H _PK_H_(0x03, 0x05) ++#define REG_COMB_BK03_06_L _PK_L_(0x03, 0x06) ++#define REG_COMB_BK03_06_H _PK_H_(0x03, 0x06) ++#define REG_COMB_BK03_07_L _PK_L_(0x03, 0x07) ++#define REG_COMB_BK03_07_H _PK_H_(0x03, 0x07) ++#define REG_COMB_BK03_08_L _PK_L_(0x03, 0x08) ++#define REG_COMB_BK03_08_H _PK_H_(0x03, 0x08) ++#define REG_COMB_BK03_09_L _PK_L_(0x03, 0x09) ++#define REG_COMB_BK03_09_H _PK_H_(0x03, 0x09) ++#define REG_COMB_BK03_0A_L _PK_L_(0x03, 0x0A) ++#define REG_COMB_BK03_0A_H _PK_H_(0x03, 0x0A) ++#define REG_COMB_BK03_0B_L _PK_L_(0x03, 0x0B) ++#define REG_COMB_BK03_0B_H _PK_H_(0x03, 0x0B) ++#define REG_COMB_BK03_0C_L _PK_L_(0x03, 0x0C) ++#define REG_COMB_BK03_0C_H _PK_H_(0x03, 0x0C) ++#define REG_COMB_BK03_0D_L _PK_L_(0x03, 0x0D) ++#define REG_COMB_BK03_0D_H _PK_H_(0x03, 0x0D) ++#define REG_COMB_BK03_0E_L _PK_L_(0x03, 0x0E) ++#define REG_COMB_BK03_0E_H _PK_H_(0x03, 0x0E) ++#define REG_COMB_BK03_0F_L _PK_L_(0x03, 0x0F) ++#define REG_COMB_BK03_0F_H _PK_H_(0x03, 0x0F) ++#define REG_COMB_BK03_10_L _PK_L_(0x03, 0x10) ++#define REG_COMB_BK03_10_H _PK_H_(0x03, 0x10) ++#define REG_COMB_BK03_11_L _PK_L_(0x03, 0x11) ++#define REG_COMB_BK03_11_H _PK_H_(0x03, 0x11) ++#define REG_COMB_BK03_12_L _PK_L_(0x03, 0x12) ++#define REG_COMB_BK03_12_H _PK_H_(0x03, 0x12) ++#define REG_COMB_BK03_13_L _PK_L_(0x03, 0x13) ++#define REG_COMB_BK03_13_H _PK_H_(0x03, 0x13) ++#define REG_COMB_BK03_14_L _PK_L_(0x03, 0x14) ++#define REG_COMB_BK03_14_H _PK_H_(0x03, 0x14) ++#define REG_COMB_BK03_15_L _PK_L_(0x03, 0x15) ++#define REG_COMB_BK03_15_H _PK_H_(0x03, 0x15) ++#define REG_COMB_BK03_16_L _PK_L_(0x03, 0x16) ++#define REG_COMB_BK03_16_H _PK_H_(0x03, 0x16) ++#define REG_COMB_BK03_17_L _PK_L_(0x03, 0x17) ++#define REG_COMB_BK03_17_H _PK_H_(0x03, 0x17) ++#define REG_COMB_BK03_18_L _PK_L_(0x03, 0x18) ++#define REG_COMB_BK03_18_H _PK_H_(0x03, 0x18) ++#define REG_COMB_BK03_19_L _PK_L_(0x03, 0x19) ++#define REG_COMB_BK03_19_H _PK_H_(0x03, 0x19) ++#define REG_COMB_BK03_1A_L _PK_L_(0x03, 0x1A) ++#define REG_COMB_BK03_1A_H _PK_H_(0x03, 0x1A) ++#define REG_COMB_BK03_1B_L _PK_L_(0x03, 0x1B) ++#define REG_COMB_BK03_1B_H _PK_H_(0x03, 0x1B) ++#define REG_COMB_BK03_1C_L _PK_L_(0x03, 0x1C) ++#define REG_COMB_BK03_1C_H _PK_H_(0x03, 0x1C) ++#define REG_COMB_BK03_1D_L _PK_L_(0x03, 0x1D) ++#define REG_COMB_BK03_1D_H _PK_H_(0x03, 0x1D) ++#define REG_COMB_BK03_1E_L _PK_L_(0x03, 0x1E) ++#define REG_COMB_BK03_1E_H _PK_H_(0x03, 0x1E) ++#define REG_COMB_BK03_1F_L _PK_L_(0x03, 0x1F) ++#define REG_COMB_BK03_1F_H _PK_H_(0x03, 0x1F) ++#define REG_COMB_BK03_20_L _PK_L_(0x03, 0x20) ++#define REG_COMB_BK03_20_H _PK_H_(0x03, 0x20) ++#define REG_COMB_BK03_21_L _PK_L_(0x03, 0x21) ++#define REG_COMB_BK03_21_H _PK_H_(0x03, 0x21) ++#define REG_COMB_BK03_22_L _PK_L_(0x03, 0x22) ++#define REG_COMB_BK03_22_H _PK_H_(0x03, 0x22) ++#define REG_COMB_BK03_23_L _PK_L_(0x03, 0x23) ++#define REG_COMB_BK03_23_H _PK_H_(0x03, 0x23) ++#define REG_COMB_BK03_24_L _PK_L_(0x03, 0x24) ++#define REG_COMB_BK03_24_H _PK_H_(0x03, 0x24) ++#define REG_COMB_BK03_25_L _PK_L_(0x03, 0x25) ++#define REG_COMB_BK03_25_H _PK_H_(0x03, 0x25) ++#define REG_COMB_BK03_26_L _PK_L_(0x03, 0x26) ++#define REG_COMB_BK03_26_H _PK_H_(0x03, 0x26) ++#define REG_COMB_BK03_27_L _PK_L_(0x03, 0x27) ++#define REG_COMB_BK03_27_H _PK_H_(0x03, 0x27) ++#define REG_COMB_BK03_28_L _PK_L_(0x03, 0x28) ++#define REG_COMB_BK03_28_H _PK_H_(0x03, 0x28) ++#define REG_COMB_BK03_29_L _PK_L_(0x03, 0x29) ++#define REG_COMB_BK03_29_H _PK_H_(0x03, 0x29) ++#define REG_COMB_BK03_2A_L _PK_L_(0x03, 0x2A) ++#define REG_COMB_BK03_2A_H _PK_H_(0x03, 0x2A) ++#define REG_COMB_BK03_2B_L _PK_L_(0x03, 0x2B) ++#define REG_COMB_BK03_2B_H _PK_H_(0x03, 0x2B) ++#define REG_COMB_BK03_2C_L _PK_L_(0x03, 0x2C) ++#define REG_COMB_BK03_2C_H _PK_H_(0x03, 0x2C) ++#define REG_COMB_BK03_2D_L _PK_L_(0x03, 0x2D) ++#define REG_COMB_BK03_2D_H _PK_H_(0x03, 0x2D) ++#define REG_COMB_BK03_2E_L _PK_L_(0x03, 0x2E) ++#define REG_COMB_BK03_2E_H _PK_H_(0x03, 0x2E) ++#define REG_COMB_BK03_2F_L _PK_L_(0x03, 0x2F) ++#define REG_COMB_BK03_2F_H _PK_H_(0x03, 0x2F) ++#define REG_COMB_BK03_30_L _PK_L_(0x03, 0x30) ++#define REG_COMB_BK03_30_H _PK_H_(0x03, 0x30) ++#define REG_COMB_BK03_31_L _PK_L_(0x03, 0x31) ++#define REG_COMB_BK03_31_H _PK_H_(0x03, 0x31) ++#define REG_COMB_BK03_32_L _PK_L_(0x03, 0x32) ++#define REG_COMB_BK03_32_H _PK_H_(0x03, 0x32) ++#define REG_COMB_BK03_33_L _PK_L_(0x03, 0x33) ++#define REG_COMB_BK03_33_H _PK_H_(0x03, 0x33) ++#define REG_COMB_BK03_34_L _PK_L_(0x03, 0x34) ++#define REG_COMB_BK03_34_H _PK_H_(0x03, 0x34) ++#define REG_COMB_BK03_35_L _PK_L_(0x03, 0x35) ++#define REG_COMB_BK03_35_H _PK_H_(0x03, 0x35) ++#define REG_COMB_BK03_36_L _PK_L_(0x03, 0x36) ++#define REG_COMB_BK03_36_H _PK_H_(0x03, 0x36) ++#define REG_COMB_BK03_37_L _PK_L_(0x03, 0x37) ++#define REG_COMB_BK03_37_H _PK_H_(0x03, 0x37) ++#define REG_COMB_BK03_38_L _PK_L_(0x03, 0x38) ++#define REG_COMB_BK03_38_H _PK_H_(0x03, 0x38) ++#define REG_COMB_BK03_39_L _PK_L_(0x03, 0x39) ++#define REG_COMB_BK03_39_H _PK_H_(0x03, 0x39) ++#define REG_COMB_BK03_3A_L _PK_L_(0x03, 0x3A) ++#define REG_COMB_BK03_3A_H _PK_H_(0x03, 0x3A) ++#define REG_COMB_BK03_3B_L _PK_L_(0x03, 0x3B) ++#define REG_COMB_BK03_3B_H _PK_H_(0x03, 0x3B) ++#define REG_COMB_BK03_3C_L _PK_L_(0x03, 0x3C) ++#define REG_COMB_BK03_3C_H _PK_H_(0x03, 0x3C) ++#define REG_COMB_BK03_3D_L _PK_L_(0x03, 0x3D) ++#define REG_COMB_BK03_3D_H _PK_H_(0x03, 0x3D) ++#define REG_COMB_BK03_3E_L _PK_L_(0x03, 0x3E) ++#define REG_COMB_BK03_3E_H _PK_H_(0x03, 0x3E) ++#define REG_COMB_BK03_3F_L _PK_L_(0x03, 0x3F) ++#define REG_COMB_BK03_3F_H _PK_H_(0x03, 0x3F) ++#define REG_COMB_BK03_40_L _PK_L_(0x03, 0x40) ++#define REG_COMB_BK03_40_H _PK_H_(0x03, 0x40) ++#define REG_COMB_BK03_41_L _PK_L_(0x03, 0x41) ++#define REG_COMB_BK03_41_H _PK_H_(0x03, 0x41) ++#define REG_COMB_BK03_42_L _PK_L_(0x03, 0x42) ++#define REG_COMB_BK03_42_H _PK_H_(0x03, 0x42) ++#define REG_COMB_BK03_43_L _PK_L_(0x03, 0x43) ++#define REG_COMB_BK03_43_H _PK_H_(0x03, 0x43) ++#define REG_COMB_BK03_44_L _PK_L_(0x03, 0x44) ++#define REG_COMB_BK03_44_H _PK_H_(0x03, 0x44) ++#define REG_COMB_BK03_45_L _PK_L_(0x03, 0x45) ++#define REG_COMB_BK03_45_H _PK_H_(0x03, 0x45) ++#define REG_COMB_BK03_46_L _PK_L_(0x03, 0x46) ++#define REG_COMB_BK03_46_H _PK_H_(0x03, 0x46) ++#define REG_COMB_BK03_47_L _PK_L_(0x03, 0x47) ++#define REG_COMB_BK03_47_H _PK_H_(0x03, 0x47) ++#define REG_COMB_BK03_48_L _PK_L_(0x03, 0x48) ++#define REG_COMB_BK03_48_H _PK_H_(0x03, 0x48) ++#define REG_COMB_BK03_49_L _PK_L_(0x03, 0x49) ++#define REG_COMB_BK03_49_H _PK_H_(0x03, 0x49) ++#define REG_COMB_BK03_4A_L _PK_L_(0x03, 0x4A) ++#define REG_COMB_BK03_4A_H _PK_H_(0x03, 0x4A) ++#define REG_COMB_BK03_4B_L _PK_L_(0x03, 0x4B) ++#define REG_COMB_BK03_4B_H _PK_H_(0x03, 0x4B) ++#define REG_COMB_BK03_4C_L _PK_L_(0x03, 0x4C) ++#define REG_COMB_BK03_4C_H _PK_H_(0x03, 0x4C) ++#define REG_COMB_BK03_4D_L _PK_L_(0x03, 0x4D) ++#define REG_COMB_BK03_4D_H _PK_H_(0x03, 0x4D) ++#define REG_COMB_BK03_4E_L _PK_L_(0x03, 0x4E) ++#define REG_COMB_BK03_4E_H _PK_H_(0x03, 0x4E) ++#define REG_COMB_BK03_4F_L _PK_L_(0x03, 0x4F) ++#define REG_COMB_BK03_4F_H _PK_H_(0x03, 0x4F) ++#define REG_COMB_BK03_50_L _PK_L_(0x03, 0x50) ++#define REG_COMB_BK03_50_H _PK_H_(0x03, 0x50) ++#define REG_COMB_BK03_51_L _PK_L_(0x03, 0x51) ++#define REG_COMB_BK03_51_H _PK_H_(0x03, 0x51) ++#define REG_COMB_BK03_52_L _PK_L_(0x03, 0x52) ++#define REG_COMB_BK03_52_H _PK_H_(0x03, 0x52) ++#define REG_COMB_BK03_53_L _PK_L_(0x03, 0x53) ++#define REG_COMB_BK03_53_H _PK_H_(0x03, 0x53) ++#define REG_COMB_BK03_54_L _PK_L_(0x03, 0x54) ++#define REG_COMB_BK03_54_H _PK_H_(0x03, 0x54) ++#define REG_COMB_BK03_55_L _PK_L_(0x03, 0x55) ++#define REG_COMB_BK03_55_H _PK_H_(0x03, 0x55) ++#define REG_COMB_BK03_56_L _PK_L_(0x03, 0x56) ++#define REG_COMB_BK03_56_H _PK_H_(0x03, 0x56) ++#define REG_COMB_BK03_57_L _PK_L_(0x03, 0x57) ++#define REG_COMB_BK03_57_H _PK_H_(0x03, 0x57) ++#define REG_COMB_BK03_58_L _PK_L_(0x03, 0x58) ++#define REG_COMB_BK03_58_H _PK_H_(0x03, 0x58) ++#define REG_COMB_BK03_59_L _PK_L_(0x03, 0x59) ++#define REG_COMB_BK03_59_H _PK_H_(0x03, 0x59) ++#define REG_COMB_BK03_5A_L _PK_L_(0x03, 0x5A) ++#define REG_COMB_BK03_5A_H _PK_H_(0x03, 0x5A) ++#define REG_COMB_BK03_5B_L _PK_L_(0x03, 0x5B) ++#define REG_COMB_BK03_5B_H _PK_H_(0x03, 0x5B) ++#define REG_COMB_BK03_5C_L _PK_L_(0x03, 0x5C) ++#define REG_COMB_BK03_5C_H _PK_H_(0x03, 0x5C) ++#define REG_COMB_BK03_5D_L _PK_L_(0x03, 0x5D) ++#define REG_COMB_BK03_5D_H _PK_H_(0x03, 0x5D) ++#define REG_COMB_BK03_5E_L _PK_L_(0x03, 0x5E) ++#define REG_COMB_BK03_5E_H _PK_H_(0x03, 0x5E) ++#define REG_COMB_BK03_5F_L _PK_L_(0x03, 0x5F) ++#define REG_COMB_BK03_5F_H _PK_H_(0x03, 0x5F) ++#define REG_COMB_BK03_60_L _PK_L_(0x03, 0x60) ++#define REG_COMB_BK03_60_H _PK_H_(0x03, 0x60) ++#define REG_COMB_BK03_61_L _PK_L_(0x03, 0x61) ++#define REG_COMB_BK03_61_H _PK_H_(0x03, 0x61) ++#define REG_COMB_BK03_62_L _PK_L_(0x03, 0x62) ++#define REG_COMB_BK03_62_H _PK_H_(0x03, 0x62) ++#define REG_COMB_BK03_63_L _PK_L_(0x03, 0x63) ++#define REG_COMB_BK03_63_H _PK_H_(0x03, 0x63) ++#define REG_COMB_BK03_64_L _PK_L_(0x03, 0x64) ++#define REG_COMB_BK03_64_H _PK_H_(0x03, 0x64) ++#define REG_COMB_BK03_65_L _PK_L_(0x03, 0x65) ++#define REG_COMB_BK03_65_H _PK_H_(0x03, 0x65) ++#define REG_COMB_BK03_66_L _PK_L_(0x03, 0x66) ++#define REG_COMB_BK03_66_H _PK_H_(0x03, 0x66) ++#define REG_COMB_BK03_67_L _PK_L_(0x03, 0x67) ++#define REG_COMB_BK03_67_H _PK_H_(0x03, 0x67) ++#define REG_COMB_BK03_68_L _PK_L_(0x03, 0x68) ++#define REG_COMB_BK03_68_H _PK_H_(0x03, 0x68) ++#define REG_COMB_BK03_69_L _PK_L_(0x03, 0x69) ++#define REG_COMB_BK03_69_H _PK_H_(0x03, 0x69) ++#define REG_COMB_BK03_6A_L _PK_L_(0x03, 0x6A) ++#define REG_COMB_BK03_6A_H _PK_H_(0x03, 0x6A) ++#define REG_COMB_BK03_6B_L _PK_L_(0x03, 0x6B) ++#define REG_COMB_BK03_6B_H _PK_H_(0x03, 0x6B) ++#define REG_COMB_BK03_6C_L _PK_L_(0x03, 0x6C) ++#define REG_COMB_BK03_6C_H _PK_H_(0x03, 0x6C) ++#define REG_COMB_BK03_6D_L _PK_L_(0x03, 0x6D) ++#define REG_COMB_BK03_6D_H _PK_H_(0x03, 0x6D) ++#define REG_COMB_BK03_6E_L _PK_L_(0x03, 0x6E) ++#define REG_COMB_BK03_6E_H _PK_H_(0x03, 0x6E) ++#define REG_COMB_BK03_6F_L _PK_L_(0x03, 0x6F) ++#define REG_COMB_BK03_6F_H _PK_H_(0x03, 0x6F) ++#define REG_COMB_BK03_70_L _PK_L_(0x03, 0x70) ++#define REG_COMB_BK03_70_H _PK_H_(0x03, 0x70) ++#define REG_COMB_BK03_71_L _PK_L_(0x03, 0x71) ++#define REG_COMB_BK03_71_H _PK_H_(0x03, 0x71) ++#define REG_COMB_BK03_72_L _PK_L_(0x03, 0x72) ++#define REG_COMB_BK03_72_H _PK_H_(0x03, 0x72) ++#define REG_COMB_BK03_73_L _PK_L_(0x03, 0x73) ++#define REG_COMB_BK03_73_H _PK_H_(0x03, 0x73) ++#define REG_COMB_BK03_74_L _PK_L_(0x03, 0x74) ++#define REG_COMB_BK03_74_H _PK_H_(0x03, 0x74) ++#define REG_COMB_BK03_75_L _PK_L_(0x03, 0x75) ++#define REG_COMB_BK03_75_H _PK_H_(0x03, 0x75) ++#define REG_COMB_BK03_76_L _PK_L_(0x03, 0x76) ++#define REG_COMB_BK03_76_H _PK_H_(0x03, 0x76) ++#define REG_COMB_BK03_77_L _PK_L_(0x03, 0x77) ++#define REG_COMB_BK03_77_H _PK_H_(0x03, 0x77) ++#define REG_COMB_BK03_78_L _PK_L_(0x03, 0x78) ++#define REG_COMB_BK03_78_H _PK_H_(0x03, 0x78) ++#define REG_COMB_BK03_79_L _PK_L_(0x03, 0x79) ++#define REG_COMB_BK03_79_H _PK_H_(0x03, 0x79) ++#define REG_COMB_BK03_7A_L _PK_L_(0x03, 0x7A) ++#define REG_COMB_BK03_7A_H _PK_H_(0x03, 0x7A) ++#define REG_COMB_BK03_7B_L _PK_L_(0x03, 0x7B) ++#define REG_COMB_BK03_7B_H _PK_H_(0x03, 0x7B) ++#define REG_COMB_BK03_7C_L _PK_L_(0x03, 0x7C) ++#define REG_COMB_BK03_7C_H _PK_H_(0x03, 0x7C) ++#define REG_COMB_BK03_7D_L _PK_L_(0x03, 0x7D) ++#define REG_COMB_BK03_7D_H _PK_H_(0x03, 0x7D) ++#define REG_COMB_BK03_7E_L _PK_L_(0x03, 0x7E) ++#define REG_COMB_BK03_7E_H _PK_H_(0x03, 0x7E) ++#define REG_COMB_BK03_7F_L _PK_L_(0x03, 0x7F) ++#define REG_COMB_BK03_7F_H _PK_H_(0x03, 0x7F) ++#define REG_COMB_BK04_00_L _PK_L_(0x04, 0x00) ++#define REG_COMB_BK04_00_H _PK_H_(0x04, 0x00) ++#define REG_COMB_BK04_01_L _PK_L_(0x04, 0x01) ++#define REG_COMB_BK04_01_H _PK_H_(0x04, 0x01) ++#define REG_COMB_BK04_02_L _PK_L_(0x04, 0x02) ++#define REG_COMB_BK04_02_H _PK_H_(0x04, 0x02) ++#define REG_COMB_BK04_03_L _PK_L_(0x04, 0x03) ++#define REG_COMB_BK04_03_H _PK_H_(0x04, 0x03) ++#define REG_COMB_BK04_04_L _PK_L_(0x04, 0x04) ++#define REG_COMB_BK04_04_H _PK_H_(0x04, 0x04) ++#define REG_COMB_BK04_05_L _PK_L_(0x04, 0x05) ++#define REG_COMB_BK04_05_H _PK_H_(0x04, 0x05) ++#define REG_COMB_BK04_06_L _PK_L_(0x04, 0x06) ++#define REG_COMB_BK04_06_H _PK_H_(0x04, 0x06) ++#define REG_COMB_BK04_07_L _PK_L_(0x04, 0x07) ++#define REG_COMB_BK04_07_H _PK_H_(0x04, 0x07) ++#define REG_COMB_BK04_08_L _PK_L_(0x04, 0x08) ++#define REG_COMB_BK04_08_H _PK_H_(0x04, 0x08) ++#define REG_COMB_BK04_09_L _PK_L_(0x04, 0x09) ++#define REG_COMB_BK04_09_H _PK_H_(0x04, 0x09) ++#define REG_COMB_BK04_0A_L _PK_L_(0x04, 0x0A) ++#define REG_COMB_BK04_0A_H _PK_H_(0x04, 0x0A) ++#define REG_COMB_BK04_0B_L _PK_L_(0x04, 0x0B) ++#define REG_COMB_BK04_0B_H _PK_H_(0x04, 0x0B) ++#define REG_COMB_BK04_0C_L _PK_L_(0x04, 0x0C) ++#define REG_COMB_BK04_0C_H _PK_H_(0x04, 0x0C) ++#define REG_COMB_BK04_0D_L _PK_L_(0x04, 0x0D) ++#define REG_COMB_BK04_0D_H _PK_H_(0x04, 0x0D) ++#define REG_COMB_BK04_0E_L _PK_L_(0x04, 0x0E) ++#define REG_COMB_BK04_0E_H _PK_H_(0x04, 0x0E) ++#define REG_COMB_BK04_0F_L _PK_L_(0x04, 0x0F) ++#define REG_COMB_BK04_0F_H _PK_H_(0x04, 0x0F) ++#define REG_COMB_BK04_10_L _PK_L_(0x04, 0x10) ++#define REG_COMB_BK04_10_H _PK_H_(0x04, 0x10) ++#define REG_COMB_BK04_11_L _PK_L_(0x04, 0x11) ++#define REG_COMB_BK04_11_H _PK_H_(0x04, 0x11) ++#define REG_COMB_BK04_12_L _PK_L_(0x04, 0x12) ++#define REG_COMB_BK04_12_H _PK_H_(0x04, 0x12) ++#define REG_COMB_BK04_13_L _PK_L_(0x04, 0x13) ++#define REG_COMB_BK04_13_H _PK_H_(0x04, 0x13) ++#define REG_COMB_BK04_14_L _PK_L_(0x04, 0x14) ++#define REG_COMB_BK04_14_H _PK_H_(0x04, 0x14) ++#define REG_COMB_BK04_15_L _PK_L_(0x04, 0x15) ++#define REG_COMB_BK04_15_H _PK_H_(0x04, 0x15) ++#define REG_COMB_BK04_16_L _PK_L_(0x04, 0x16) ++#define REG_COMB_BK04_16_H _PK_H_(0x04, 0x16) ++#define REG_COMB_BK04_17_L _PK_L_(0x04, 0x17) ++#define REG_COMB_BK04_17_H _PK_H_(0x04, 0x17) ++#define REG_COMB_BK04_18_L _PK_L_(0x04, 0x18) ++#define REG_COMB_BK04_18_H _PK_H_(0x04, 0x18) ++#define REG_COMB_BK04_19_L _PK_L_(0x04, 0x19) ++#define REG_COMB_BK04_19_H _PK_H_(0x04, 0x19) ++#define REG_COMB_BK04_1A_L _PK_L_(0x04, 0x1A) ++#define REG_COMB_BK04_1A_H _PK_H_(0x04, 0x1A) ++#define REG_COMB_BK04_1B_L _PK_L_(0x04, 0x1B) ++#define REG_COMB_BK04_1B_H _PK_H_(0x04, 0x1B) ++#define REG_COMB_BK04_1C_L _PK_L_(0x04, 0x1C) ++#define REG_COMB_BK04_1C_H _PK_H_(0x04, 0x1C) ++#define REG_COMB_BK04_1D_L _PK_L_(0x04, 0x1D) ++#define REG_COMB_BK04_1D_H _PK_H_(0x04, 0x1D) ++#define REG_COMB_BK04_1E_L _PK_L_(0x04, 0x1E) ++#define REG_COMB_BK04_1E_H _PK_H_(0x04, 0x1E) ++#define REG_COMB_BK04_1F_L _PK_L_(0x04, 0x1F) ++#define REG_COMB_BK04_1F_H _PK_H_(0x04, 0x1F) ++#define REG_COMB_BK04_20_L _PK_L_(0x04, 0x20) ++#define REG_COMB_BK04_20_H _PK_H_(0x04, 0x20) ++#define REG_COMB_BK04_21_L _PK_L_(0x04, 0x21) ++#define REG_COMB_BK04_21_H _PK_H_(0x04, 0x21) ++#define REG_COMB_BK04_22_L _PK_L_(0x04, 0x22) ++#define REG_COMB_BK04_22_H _PK_H_(0x04, 0x22) ++#define REG_COMB_BK04_23_L _PK_L_(0x04, 0x23) ++#define REG_COMB_BK04_23_H _PK_H_(0x04, 0x23) ++#define REG_COMB_BK04_24_L _PK_L_(0x04, 0x24) ++#define REG_COMB_BK04_24_H _PK_H_(0x04, 0x24) ++#define REG_COMB_BK04_25_L _PK_L_(0x04, 0x25) ++#define REG_COMB_BK04_25_H _PK_H_(0x04, 0x25) ++#define REG_COMB_BK04_26_L _PK_L_(0x04, 0x26) ++#define REG_COMB_BK04_26_H _PK_H_(0x04, 0x26) ++#define REG_COMB_BK04_27_L _PK_L_(0x04, 0x27) ++#define REG_COMB_BK04_27_H _PK_H_(0x04, 0x27) ++#define REG_COMB_BK04_28_L _PK_L_(0x04, 0x28) ++#define REG_COMB_BK04_28_H _PK_H_(0x04, 0x28) ++#define REG_COMB_BK04_29_L _PK_L_(0x04, 0x29) ++#define REG_COMB_BK04_29_H _PK_H_(0x04, 0x29) ++#define REG_COMB_BK04_2A_L _PK_L_(0x04, 0x2A) ++#define REG_COMB_BK04_2A_H _PK_H_(0x04, 0x2A) ++#define REG_COMB_BK04_2B_L _PK_L_(0x04, 0x2B) ++#define REG_COMB_BK04_2B_H _PK_H_(0x04, 0x2B) ++#define REG_COMB_BK04_2C_L _PK_L_(0x04, 0x2C) ++#define REG_COMB_BK04_2C_H _PK_H_(0x04, 0x2C) ++#define REG_COMB_BK04_2D_L _PK_L_(0x04, 0x2D) ++#define REG_COMB_BK04_2D_H _PK_H_(0x04, 0x2D) ++#define REG_COMB_BK04_2E_L _PK_L_(0x04, 0x2E) ++#define REG_COMB_BK04_2E_H _PK_H_(0x04, 0x2E) ++#define REG_COMB_BK04_2F_L _PK_L_(0x04, 0x2F) ++#define REG_COMB_BK04_2F_H _PK_H_(0x04, 0x2F) ++#define REG_COMB_BK04_30_L _PK_L_(0x04, 0x30) ++#define REG_COMB_BK04_30_H _PK_H_(0x04, 0x30) ++#define REG_COMB_BK04_31_L _PK_L_(0x04, 0x31) ++#define REG_COMB_BK04_31_H _PK_H_(0x04, 0x31) ++#define REG_COMB_BK04_32_L _PK_L_(0x04, 0x32) ++#define REG_COMB_BK04_32_H _PK_H_(0x04, 0x32) ++#define REG_COMB_BK04_33_L _PK_L_(0x04, 0x33) ++#define REG_COMB_BK04_33_H _PK_H_(0x04, 0x33) ++#define REG_COMB_BK04_34_L _PK_L_(0x04, 0x34) ++#define REG_COMB_BK04_34_H _PK_H_(0x04, 0x34) ++#define REG_COMB_BK04_35_L _PK_L_(0x04, 0x35) ++#define REG_COMB_BK04_35_H _PK_H_(0x04, 0x35) ++#define REG_COMB_BK04_36_L _PK_L_(0x04, 0x36) ++#define REG_COMB_BK04_36_H _PK_H_(0x04, 0x36) ++#define REG_COMB_BK04_37_L _PK_L_(0x04, 0x37) ++#define REG_COMB_BK04_37_H _PK_H_(0x04, 0x37) ++#define REG_COMB_BK04_38_L _PK_L_(0x04, 0x38) ++#define REG_COMB_BK04_38_H _PK_H_(0x04, 0x38) ++#define REG_COMB_BK04_39_L _PK_L_(0x04, 0x39) ++#define REG_COMB_BK04_39_H _PK_H_(0x04, 0x39) ++#define REG_COMB_BK04_3A_L _PK_L_(0x04, 0x3A) ++#define REG_COMB_BK04_3A_H _PK_H_(0x04, 0x3A) ++#define REG_COMB_BK04_3B_L _PK_L_(0x04, 0x3B) ++#define REG_COMB_BK04_3B_H _PK_H_(0x04, 0x3B) ++#define REG_COMB_BK04_3C_L _PK_L_(0x04, 0x3C) ++#define REG_COMB_BK04_3C_H _PK_H_(0x04, 0x3C) ++#define REG_COMB_BK04_3D_L _PK_L_(0x04, 0x3D) ++#define REG_COMB_BK04_3D_H _PK_H_(0x04, 0x3D) ++#define REG_COMB_BK04_3E_L _PK_L_(0x04, 0x3E) ++#define REG_COMB_BK04_3E_H _PK_H_(0x04, 0x3E) ++#define REG_COMB_BK04_3F_L _PK_L_(0x04, 0x3F) ++#define REG_COMB_BK04_3F_H _PK_H_(0x04, 0x3F) ++#define REG_COMB_BK04_40_L _PK_L_(0x04, 0x40) ++#define REG_COMB_BK04_40_H _PK_H_(0x04, 0x40) ++#define REG_COMB_BK04_41_L _PK_L_(0x04, 0x41) ++#define REG_COMB_BK04_41_H _PK_H_(0x04, 0x41) ++#define REG_COMB_BK04_42_L _PK_L_(0x04, 0x42) ++#define REG_COMB_BK04_42_H _PK_H_(0x04, 0x42) ++#define REG_COMB_BK04_43_L _PK_L_(0x04, 0x43) ++#define REG_COMB_BK04_43_H _PK_H_(0x04, 0x43) ++#define REG_COMB_BK04_44_L _PK_L_(0x04, 0x44) ++#define REG_COMB_BK04_44_H _PK_H_(0x04, 0x44) ++#define REG_COMB_BK04_45_L _PK_L_(0x04, 0x45) ++#define REG_COMB_BK04_45_H _PK_H_(0x04, 0x45) ++#define REG_COMB_BK04_46_L _PK_L_(0x04, 0x46) ++#define REG_COMB_BK04_46_H _PK_H_(0x04, 0x46) ++#define REG_COMB_BK04_47_L _PK_L_(0x04, 0x47) ++#define REG_COMB_BK04_47_H _PK_H_(0x04, 0x47) ++#define REG_COMB_BK04_48_L _PK_L_(0x04, 0x48) ++#define REG_COMB_BK04_48_H _PK_H_(0x04, 0x48) ++#define REG_COMB_BK04_49_L _PK_L_(0x04, 0x49) ++#define REG_COMB_BK04_49_H _PK_H_(0x04, 0x49) ++#define REG_COMB_BK04_4A_L _PK_L_(0x04, 0x4A) ++#define REG_COMB_BK04_4A_H _PK_H_(0x04, 0x4A) ++#define REG_COMB_BK04_4B_L _PK_L_(0x04, 0x4B) ++#define REG_COMB_BK04_4B_H _PK_H_(0x04, 0x4B) ++#define REG_COMB_BK04_4C_L _PK_L_(0x04, 0x4C) ++#define REG_COMB_BK04_4C_H _PK_H_(0x04, 0x4C) ++#define REG_COMB_BK04_4D_L _PK_L_(0x04, 0x4D) ++#define REG_COMB_BK04_4D_H _PK_H_(0x04, 0x4D) ++#define REG_COMB_BK04_4E_L _PK_L_(0x04, 0x4E) ++#define REG_COMB_BK04_4E_H _PK_H_(0x04, 0x4E) ++#define REG_COMB_BK04_4F_L _PK_L_(0x04, 0x4F) ++#define REG_COMB_BK04_4F_H _PK_H_(0x04, 0x4F) ++#define REG_COMB_BK04_50_L _PK_L_(0x04, 0x50) ++#define REG_COMB_BK04_50_H _PK_H_(0x04, 0x50) ++#define REG_COMB_BK04_51_L _PK_L_(0x04, 0x51) ++#define REG_COMB_BK04_51_H _PK_H_(0x04, 0x51) ++#define REG_COMB_BK04_52_L _PK_L_(0x04, 0x52) ++#define REG_COMB_BK04_52_H _PK_H_(0x04, 0x52) ++#define REG_COMB_BK04_53_L _PK_L_(0x04, 0x53) ++#define REG_COMB_BK04_53_H _PK_H_(0x04, 0x53) ++#define REG_COMB_BK04_54_L _PK_L_(0x04, 0x54) ++#define REG_COMB_BK04_54_H _PK_H_(0x04, 0x54) ++#define REG_COMB_BK04_55_L _PK_L_(0x04, 0x55) ++#define REG_COMB_BK04_55_H _PK_H_(0x04, 0x55) ++#define REG_COMB_BK04_56_L _PK_L_(0x04, 0x56) ++#define REG_COMB_BK04_56_H _PK_H_(0x04, 0x56) ++#define REG_COMB_BK04_57_L _PK_L_(0x04, 0x57) ++#define REG_COMB_BK04_57_H _PK_H_(0x04, 0x57) ++#define REG_COMB_BK04_58_L _PK_L_(0x04, 0x58) ++#define REG_COMB_BK04_58_H _PK_H_(0x04, 0x58) ++#define REG_COMB_BK04_59_L _PK_L_(0x04, 0x59) ++#define REG_COMB_BK04_59_H _PK_H_(0x04, 0x59) ++#define REG_COMB_BK04_5A_L _PK_L_(0x04, 0x5A) ++#define REG_COMB_BK04_5A_H _PK_H_(0x04, 0x5A) ++#define REG_COMB_BK04_5B_L _PK_L_(0x04, 0x5B) ++#define REG_COMB_BK04_5B_H _PK_H_(0x04, 0x5B) ++#define REG_COMB_BK04_5C_L _PK_L_(0x04, 0x5C) ++#define REG_COMB_BK04_5C_H _PK_H_(0x04, 0x5C) ++#define REG_COMB_BK04_5D_L _PK_L_(0x04, 0x5D) ++#define REG_COMB_BK04_5D_H _PK_H_(0x04, 0x5D) ++#define REG_COMB_BK04_5E_L _PK_L_(0x04, 0x5E) ++#define REG_COMB_BK04_5E_H _PK_H_(0x04, 0x5E) ++#define REG_COMB_BK04_5F_L _PK_L_(0x04, 0x5F) ++#define REG_COMB_BK04_5F_H _PK_H_(0x04, 0x5F) ++#define REG_COMB_BK04_60_L _PK_L_(0x04, 0x60) ++#define REG_COMB_BK04_60_H _PK_H_(0x04, 0x60) ++#define REG_COMB_BK04_61_L _PK_L_(0x04, 0x61) ++#define REG_COMB_BK04_61_H _PK_H_(0x04, 0x61) ++#define REG_COMB_BK04_62_L _PK_L_(0x04, 0x62) ++#define REG_COMB_BK04_62_H _PK_H_(0x04, 0x62) ++#define REG_COMB_BK04_63_L _PK_L_(0x04, 0x63) ++#define REG_COMB_BK04_63_H _PK_H_(0x04, 0x63) ++#define REG_COMB_BK04_64_L _PK_L_(0x04, 0x64) ++#define REG_COMB_BK04_64_H _PK_H_(0x04, 0x64) ++#define REG_COMB_BK04_65_L _PK_L_(0x04, 0x65) ++#define REG_COMB_BK04_65_H _PK_H_(0x04, 0x65) ++#define REG_COMB_BK04_66_L _PK_L_(0x04, 0x66) ++#define REG_COMB_BK04_66_H _PK_H_(0x04, 0x66) ++#define REG_COMB_BK04_67_L _PK_L_(0x04, 0x67) ++#define REG_COMB_BK04_67_H _PK_H_(0x04, 0x67) ++#define REG_COMB_BK04_68_L _PK_L_(0x04, 0x68) ++#define REG_COMB_BK04_68_H _PK_H_(0x04, 0x68) ++#define REG_COMB_BK04_69_L _PK_L_(0x04, 0x69) ++#define REG_COMB_BK04_69_H _PK_H_(0x04, 0x69) ++#define REG_COMB_BK04_6A_L _PK_L_(0x04, 0x6A) ++#define REG_COMB_BK04_6A_H _PK_H_(0x04, 0x6A) ++#define REG_COMB_BK04_6B_L _PK_L_(0x04, 0x6B) ++#define REG_COMB_BK04_6B_H _PK_H_(0x04, 0x6B) ++#define REG_COMB_BK04_6C_L _PK_L_(0x04, 0x6C) ++#define REG_COMB_BK04_6C_H _PK_H_(0x04, 0x6C) ++#define REG_COMB_BK04_6D_L _PK_L_(0x04, 0x6D) ++#define REG_COMB_BK04_6D_H _PK_H_(0x04, 0x6D) ++#define REG_COMB_BK04_6E_L _PK_L_(0x04, 0x6E) ++#define REG_COMB_BK04_6E_H _PK_H_(0x04, 0x6E) ++#define REG_COMB_BK04_6F_L _PK_L_(0x04, 0x6F) ++#define REG_COMB_BK04_6F_H _PK_H_(0x04, 0x6F) ++#define REG_COMB_BK04_70_L _PK_L_(0x04, 0x70) ++#define REG_COMB_BK04_70_H _PK_H_(0x04, 0x70) ++#define REG_COMB_BK04_71_L _PK_L_(0x04, 0x71) ++#define REG_COMB_BK04_71_H _PK_H_(0x04, 0x71) ++#define REG_COMB_BK04_72_L _PK_L_(0x04, 0x72) ++#define REG_COMB_BK04_72_H _PK_H_(0x04, 0x72) ++#define REG_COMB_BK04_73_L _PK_L_(0x04, 0x73) ++#define REG_COMB_BK04_73_H _PK_H_(0x04, 0x73) ++#define REG_COMB_BK04_74_L _PK_L_(0x04, 0x74) ++#define REG_COMB_BK04_74_H _PK_H_(0x04, 0x74) ++#define REG_COMB_BK04_75_L _PK_L_(0x04, 0x75) ++#define REG_COMB_BK04_75_H _PK_H_(0x04, 0x75) ++#define REG_COMB_BK04_76_L _PK_L_(0x04, 0x76) ++#define REG_COMB_BK04_76_H _PK_H_(0x04, 0x76) ++#define REG_COMB_BK04_77_L _PK_L_(0x04, 0x77) ++#define REG_COMB_BK04_77_H _PK_H_(0x04, 0x77) ++#define REG_COMB_BK04_78_L _PK_L_(0x04, 0x78) ++#define REG_COMB_BK04_78_H _PK_H_(0x04, 0x78) ++#define REG_COMB_BK04_79_L _PK_L_(0x04, 0x79) ++#define REG_COMB_BK04_79_H _PK_H_(0x04, 0x79) ++#define REG_COMB_BK04_7A_L _PK_L_(0x04, 0x7A) ++#define REG_COMB_BK04_7A_H _PK_H_(0x04, 0x7A) ++#define REG_COMB_BK04_7B_L _PK_L_(0x04, 0x7B) ++#define REG_COMB_BK04_7B_H _PK_H_(0x04, 0x7B) ++#define REG_COMB_BK04_7C_L _PK_L_(0x04, 0x7C) ++#define REG_COMB_BK04_7C_H _PK_H_(0x04, 0x7C) ++#define REG_COMB_BK04_7D_L _PK_L_(0x04, 0x7D) ++#define REG_COMB_BK04_7D_H _PK_H_(0x04, 0x7D) ++#define REG_COMB_BK04_7E_L _PK_L_(0x04, 0x7E) ++#define REG_COMB_BK04_7E_H _PK_H_(0x04, 0x7E) ++#define REG_COMB_BK04_7F_L _PK_L_(0x04, 0x7F) ++#define REG_COMB_BK04_7F_H _PK_H_(0x04, 0x7F) ++#define REG_COMB_BK05_00_L _PK_L_(0x05, 0x00) ++#define REG_COMB_BK05_00_H _PK_H_(0x05, 0x00) ++#define REG_COMB_BK05_01_L _PK_L_(0x05, 0x01) ++#define REG_COMB_BK05_01_H _PK_H_(0x05, 0x01) ++#define REG_COMB_BK05_02_L _PK_L_(0x05, 0x02) ++#define REG_COMB_BK05_02_H _PK_H_(0x05, 0x02) ++#define REG_COMB_BK05_03_L _PK_L_(0x05, 0x03) ++#define REG_COMB_BK05_03_H _PK_H_(0x05, 0x03) ++#define REG_COMB_BK05_04_L _PK_L_(0x05, 0x04) ++#define REG_COMB_BK05_04_H _PK_H_(0x05, 0x04) ++#define REG_COMB_BK05_05_L _PK_L_(0x05, 0x05) ++#define REG_COMB_BK05_05_H _PK_H_(0x05, 0x05) ++#define REG_COMB_BK05_06_L _PK_L_(0x05, 0x06) ++#define REG_COMB_BK05_06_H _PK_H_(0x05, 0x06) ++#define REG_COMB_BK05_07_L _PK_L_(0x05, 0x07) ++#define REG_COMB_BK05_07_H _PK_H_(0x05, 0x07) ++#define REG_COMB_BK05_08_L _PK_L_(0x05, 0x08) ++#define REG_COMB_BK05_08_H _PK_H_(0x05, 0x08) ++#define REG_COMB_BK05_09_L _PK_L_(0x05, 0x09) ++#define REG_COMB_BK05_09_H _PK_H_(0x05, 0x09) ++#define REG_COMB_BK05_0A_L _PK_L_(0x05, 0x0A) ++#define REG_COMB_BK05_0A_H _PK_H_(0x05, 0x0A) ++#define REG_COMB_BK05_0B_L _PK_L_(0x05, 0x0B) ++#define REG_COMB_BK05_0B_H _PK_H_(0x05, 0x0B) ++#define REG_COMB_BK05_0C_L _PK_L_(0x05, 0x0C) ++#define REG_COMB_BK05_0C_H _PK_H_(0x05, 0x0C) ++#define REG_COMB_BK05_0D_L _PK_L_(0x05, 0x0D) ++#define REG_COMB_BK05_0D_H _PK_H_(0x05, 0x0D) ++#define REG_COMB_BK05_0E_L _PK_L_(0x05, 0x0E) ++#define REG_COMB_BK05_0E_H _PK_H_(0x05, 0x0E) ++#define REG_COMB_BK05_0F_L _PK_L_(0x05, 0x0F) ++#define REG_COMB_BK05_0F_H _PK_H_(0x05, 0x0F) ++#define REG_COMB_BK05_10_L _PK_L_(0x05, 0x10) ++#define REG_COMB_BK05_10_H _PK_H_(0x05, 0x10) ++#define REG_COMB_BK05_11_L _PK_L_(0x05, 0x11) ++#define REG_COMB_BK05_11_H _PK_H_(0x05, 0x11) ++#define REG_COMB_BK05_12_L _PK_L_(0x05, 0x12) ++#define REG_COMB_BK05_12_H _PK_H_(0x05, 0x12) ++#define REG_COMB_BK05_13_L _PK_L_(0x05, 0x13) ++#define REG_COMB_BK05_13_H _PK_H_(0x05, 0x13) ++#define REG_COMB_BK05_14_L _PK_L_(0x05, 0x14) ++#define REG_COMB_BK05_14_H _PK_H_(0x05, 0x14) ++#define REG_COMB_BK05_15_L _PK_L_(0x05, 0x15) ++#define REG_COMB_BK05_15_H _PK_H_(0x05, 0x15) ++#define REG_COMB_BK05_16_L _PK_L_(0x05, 0x16) ++#define REG_COMB_BK05_16_H _PK_H_(0x05, 0x16) ++#define REG_COMB_BK05_17_L _PK_L_(0x05, 0x17) ++#define REG_COMB_BK05_17_H _PK_H_(0x05, 0x17) ++#define REG_COMB_BK05_18_L _PK_L_(0x05, 0x18) ++#define REG_COMB_BK05_18_H _PK_H_(0x05, 0x18) ++#define REG_COMB_BK05_19_L _PK_L_(0x05, 0x19) ++#define REG_COMB_BK05_19_H _PK_H_(0x05, 0x19) ++#define REG_COMB_BK05_1A_L _PK_L_(0x05, 0x1A) ++#define REG_COMB_BK05_1A_H _PK_H_(0x05, 0x1A) ++#define REG_COMB_BK05_1B_L _PK_L_(0x05, 0x1B) ++#define REG_COMB_BK05_1B_H _PK_H_(0x05, 0x1B) ++#define REG_COMB_BK05_1C_L _PK_L_(0x05, 0x1C) ++#define REG_COMB_BK05_1C_H _PK_H_(0x05, 0x1C) ++#define REG_COMB_BK05_1D_L _PK_L_(0x05, 0x1D) ++#define REG_COMB_BK05_1D_H _PK_H_(0x05, 0x1D) ++#define REG_COMB_BK05_1E_L _PK_L_(0x05, 0x1E) ++#define REG_COMB_BK05_1E_H _PK_H_(0x05, 0x1E) ++#define REG_COMB_BK05_1F_L _PK_L_(0x05, 0x1F) ++#define REG_COMB_BK05_1F_H _PK_H_(0x05, 0x1F) ++#define REG_COMB_BK05_20_L _PK_L_(0x05, 0x20) ++#define REG_COMB_BK05_20_H _PK_H_(0x05, 0x20) ++#define REG_COMB_BK05_21_L _PK_L_(0x05, 0x21) ++#define REG_COMB_BK05_21_H _PK_H_(0x05, 0x21) ++#define REG_COMB_BK05_22_L _PK_L_(0x05, 0x22) ++#define REG_COMB_BK05_22_H _PK_H_(0x05, 0x22) ++#define REG_COMB_BK05_23_L _PK_L_(0x05, 0x23) ++#define REG_COMB_BK05_23_H _PK_H_(0x05, 0x23) ++#define REG_COMB_BK05_24_L _PK_L_(0x05, 0x24) ++#define REG_COMB_BK05_24_H _PK_H_(0x05, 0x24) ++#define REG_COMB_BK05_25_L _PK_L_(0x05, 0x25) ++#define REG_COMB_BK05_25_H _PK_H_(0x05, 0x25) ++#define REG_COMB_BK05_26_L _PK_L_(0x05, 0x26) ++#define REG_COMB_BK05_26_H _PK_H_(0x05, 0x26) ++#define REG_COMB_BK05_27_L _PK_L_(0x05, 0x27) ++#define REG_COMB_BK05_27_H _PK_H_(0x05, 0x27) ++#define REG_COMB_BK05_28_L _PK_L_(0x05, 0x28) ++#define REG_COMB_BK05_28_H _PK_H_(0x05, 0x28) ++#define REG_COMB_BK05_29_L _PK_L_(0x05, 0x29) ++#define REG_COMB_BK05_29_H _PK_H_(0x05, 0x29) ++#define REG_COMB_BK05_2A_L _PK_L_(0x05, 0x2A) ++#define REG_COMB_BK05_2A_H _PK_H_(0x05, 0x2A) ++#define REG_COMB_BK05_2B_L _PK_L_(0x05, 0x2B) ++#define REG_COMB_BK05_2B_H _PK_H_(0x05, 0x2B) ++#define REG_COMB_BK05_2C_L _PK_L_(0x05, 0x2C) ++#define REG_COMB_BK05_2C_H _PK_H_(0x05, 0x2C) ++#define REG_COMB_BK05_2D_L _PK_L_(0x05, 0x2D) ++#define REG_COMB_BK05_2D_H _PK_H_(0x05, 0x2D) ++#define REG_COMB_BK05_2E_L _PK_L_(0x05, 0x2E) ++#define REG_COMB_BK05_2E_H _PK_H_(0x05, 0x2E) ++#define REG_COMB_BK05_2F_L _PK_L_(0x05, 0x2F) ++#define REG_COMB_BK05_2F_H _PK_H_(0x05, 0x2F) ++#define REG_COMB_BK05_30_L _PK_L_(0x05, 0x30) ++#define REG_COMB_BK05_30_H _PK_H_(0x05, 0x30) ++#define REG_COMB_BK05_31_L _PK_L_(0x05, 0x31) ++#define REG_COMB_BK05_31_H _PK_H_(0x05, 0x31) ++#define REG_COMB_BK05_32_L _PK_L_(0x05, 0x32) ++#define REG_COMB_BK05_32_H _PK_H_(0x05, 0x32) ++#define REG_COMB_BK05_33_L _PK_L_(0x05, 0x33) ++#define REG_COMB_BK05_33_H _PK_H_(0x05, 0x33) ++#define REG_COMB_BK05_34_L _PK_L_(0x05, 0x34) ++#define REG_COMB_BK05_34_H _PK_H_(0x05, 0x34) ++#define REG_COMB_BK05_35_L _PK_L_(0x05, 0x35) ++#define REG_COMB_BK05_35_H _PK_H_(0x05, 0x35) ++#define REG_COMB_BK05_36_L _PK_L_(0x05, 0x36) ++#define REG_COMB_BK05_36_H _PK_H_(0x05, 0x36) ++#define REG_COMB_BK05_37_L _PK_L_(0x05, 0x37) ++#define REG_COMB_BK05_37_H _PK_H_(0x05, 0x37) ++#define REG_COMB_BK05_38_L _PK_L_(0x05, 0x38) ++#define REG_COMB_BK05_38_H _PK_H_(0x05, 0x38) ++#define REG_COMB_BK05_39_L _PK_L_(0x05, 0x39) ++#define REG_COMB_BK05_39_H _PK_H_(0x05, 0x39) ++#define REG_COMB_BK05_3A_L _PK_L_(0x05, 0x3A) ++#define REG_COMB_BK05_3A_H _PK_H_(0x05, 0x3A) ++#define REG_COMB_BK05_3B_L _PK_L_(0x05, 0x3B) ++#define REG_COMB_BK05_3B_H _PK_H_(0x05, 0x3B) ++#define REG_COMB_BK05_3C_L _PK_L_(0x05, 0x3C) ++#define REG_COMB_BK05_3C_H _PK_H_(0x05, 0x3C) ++#define REG_COMB_BK05_3D_L _PK_L_(0x05, 0x3D) ++#define REG_COMB_BK05_3D_H _PK_H_(0x05, 0x3D) ++#define REG_COMB_BK05_3E_L _PK_L_(0x05, 0x3E) ++#define REG_COMB_BK05_3E_H _PK_H_(0x05, 0x3E) ++#define REG_COMB_BK05_3F_L _PK_L_(0x05, 0x3F) ++#define REG_COMB_BK05_3F_H _PK_H_(0x05, 0x3F) ++#define REG_COMB_BK05_40_L _PK_L_(0x05, 0x40) ++#define REG_COMB_BK05_40_H _PK_H_(0x05, 0x40) ++#define REG_COMB_BK05_41_L _PK_L_(0x05, 0x41) ++#define REG_COMB_BK05_41_H _PK_H_(0x05, 0x41) ++#define REG_COMB_BK05_42_L _PK_L_(0x05, 0x42) ++#define REG_COMB_BK05_42_H _PK_H_(0x05, 0x42) ++#define REG_COMB_BK05_43_L _PK_L_(0x05, 0x43) ++#define REG_COMB_BK05_43_H _PK_H_(0x05, 0x43) ++#define REG_COMB_BK05_44_L _PK_L_(0x05, 0x44) ++#define REG_COMB_BK05_44_H _PK_H_(0x05, 0x44) ++#define REG_COMB_BK05_45_L _PK_L_(0x05, 0x45) ++#define REG_COMB_BK05_45_H _PK_H_(0x05, 0x45) ++#define REG_COMB_BK05_46_L _PK_L_(0x05, 0x46) ++#define REG_COMB_BK05_46_H _PK_H_(0x05, 0x46) ++#define REG_COMB_BK05_47_L _PK_L_(0x05, 0x47) ++#define REG_COMB_BK05_47_H _PK_H_(0x05, 0x47) ++#define REG_COMB_BK05_48_L _PK_L_(0x05, 0x48) ++#define REG_COMB_BK05_48_H _PK_H_(0x05, 0x48) ++#define REG_COMB_BK05_49_L _PK_L_(0x05, 0x49) ++#define REG_COMB_BK05_49_H _PK_H_(0x05, 0x49) ++#define REG_COMB_BK05_4A_L _PK_L_(0x05, 0x4A) ++#define REG_COMB_BK05_4A_H _PK_H_(0x05, 0x4A) ++#define REG_COMB_BK05_4B_L _PK_L_(0x05, 0x4B) ++#define REG_COMB_BK05_4B_H _PK_H_(0x05, 0x4B) ++#define REG_COMB_BK05_4C_L _PK_L_(0x05, 0x4C) ++#define REG_COMB_BK05_4C_H _PK_H_(0x05, 0x4C) ++#define REG_COMB_BK05_4D_L _PK_L_(0x05, 0x4D) ++#define REG_COMB_BK05_4D_H _PK_H_(0x05, 0x4D) ++#define REG_COMB_BK05_4E_L _PK_L_(0x05, 0x4E) ++#define REG_COMB_BK05_4E_H _PK_H_(0x05, 0x4E) ++#define REG_COMB_BK05_4F_L _PK_L_(0x05, 0x4F) ++#define REG_COMB_BK05_4F_H _PK_H_(0x05, 0x4F) ++#define REG_COMB_BK05_50_L _PK_L_(0x05, 0x50) ++#define REG_COMB_BK05_50_H _PK_H_(0x05, 0x50) ++#define REG_COMB_BK05_51_L _PK_L_(0x05, 0x51) ++#define REG_COMB_BK05_51_H _PK_H_(0x05, 0x51) ++#define REG_COMB_BK05_52_L _PK_L_(0x05, 0x52) ++#define REG_COMB_BK05_52_H _PK_H_(0x05, 0x52) ++#define REG_COMB_BK05_53_L _PK_L_(0x05, 0x53) ++#define REG_COMB_BK05_53_H _PK_H_(0x05, 0x53) ++#define REG_COMB_BK05_54_L _PK_L_(0x05, 0x54) ++#define REG_COMB_BK05_54_H _PK_H_(0x05, 0x54) ++#define REG_COMB_BK05_55_L _PK_L_(0x05, 0x55) ++#define REG_COMB_BK05_55_H _PK_H_(0x05, 0x55) ++#define REG_COMB_BK05_56_L _PK_L_(0x05, 0x56) ++#define REG_COMB_BK05_56_H _PK_H_(0x05, 0x56) ++#define REG_COMB_BK05_57_L _PK_L_(0x05, 0x57) ++#define REG_COMB_BK05_57_H _PK_H_(0x05, 0x57) ++#define REG_COMB_BK05_58_L _PK_L_(0x05, 0x58) ++#define REG_COMB_BK05_58_H _PK_H_(0x05, 0x58) ++#define REG_COMB_BK05_59_L _PK_L_(0x05, 0x59) ++#define REG_COMB_BK05_59_H _PK_H_(0x05, 0x59) ++#define REG_COMB_BK05_5A_L _PK_L_(0x05, 0x5A) ++#define REG_COMB_BK05_5A_H _PK_H_(0x05, 0x5A) ++#define REG_COMB_BK05_5B_L _PK_L_(0x05, 0x5B) ++#define REG_COMB_BK05_5B_H _PK_H_(0x05, 0x5B) ++#define REG_COMB_BK05_5C_L _PK_L_(0x05, 0x5C) ++#define REG_COMB_BK05_5C_H _PK_H_(0x05, 0x5C) ++#define REG_COMB_BK05_5D_L _PK_L_(0x05, 0x5D) ++#define REG_COMB_BK05_5D_H _PK_H_(0x05, 0x5D) ++#define REG_COMB_BK05_5E_L _PK_L_(0x05, 0x5E) ++#define REG_COMB_BK05_5E_H _PK_H_(0x05, 0x5E) ++#define REG_COMB_BK05_5F_L _PK_L_(0x05, 0x5F) ++#define REG_COMB_BK05_5F_H _PK_H_(0x05, 0x5F) ++#define REG_COMB_BK05_60_L _PK_L_(0x05, 0x60) ++#define REG_COMB_BK05_60_H _PK_H_(0x05, 0x60) ++#define REG_COMB_BK05_61_L _PK_L_(0x05, 0x61) ++#define REG_COMB_BK05_61_H _PK_H_(0x05, 0x61) ++#define REG_COMB_BK05_62_L _PK_L_(0x05, 0x62) ++#define REG_COMB_BK05_62_H _PK_H_(0x05, 0x62) ++#define REG_COMB_BK05_63_L _PK_L_(0x05, 0x63) ++#define REG_COMB_BK05_63_H _PK_H_(0x05, 0x63) ++#define REG_COMB_BK05_64_L _PK_L_(0x05, 0x64) ++#define REG_COMB_BK05_64_H _PK_H_(0x05, 0x64) ++#define REG_COMB_BK05_65_L _PK_L_(0x05, 0x65) ++#define REG_COMB_BK05_65_H _PK_H_(0x05, 0x65) ++#define REG_COMB_BK05_66_L _PK_L_(0x05, 0x66) ++#define REG_COMB_BK05_66_H _PK_H_(0x05, 0x66) ++#define REG_COMB_BK05_67_L _PK_L_(0x05, 0x67) ++#define REG_COMB_BK05_67_H _PK_H_(0x05, 0x67) ++#define REG_COMB_BK05_68_L _PK_L_(0x05, 0x68) ++#define REG_COMB_BK05_68_H _PK_H_(0x05, 0x68) ++#define REG_COMB_BK05_69_L _PK_L_(0x05, 0x69) ++#define REG_COMB_BK05_69_H _PK_H_(0x05, 0x69) ++#define REG_COMB_BK05_6A_L _PK_L_(0x05, 0x6A) ++#define REG_COMB_BK05_6A_H _PK_H_(0x05, 0x6A) ++#define REG_COMB_BK05_6B_L _PK_L_(0x05, 0x6B) ++#define REG_COMB_BK05_6B_H _PK_H_(0x05, 0x6B) ++#define REG_COMB_BK05_6C_L _PK_L_(0x05, 0x6C) ++#define REG_COMB_BK05_6C_H _PK_H_(0x05, 0x6C) ++#define REG_COMB_BK05_6D_L _PK_L_(0x05, 0x6D) ++#define REG_COMB_BK05_6D_H _PK_H_(0x05, 0x6D) ++#define REG_COMB_BK05_6E_L _PK_L_(0x05, 0x6E) ++#define REG_COMB_BK05_6E_H _PK_H_(0x05, 0x6E) ++#define REG_COMB_BK05_6F_L _PK_L_(0x05, 0x6F) ++#define REG_COMB_BK05_6F_H _PK_H_(0x05, 0x6F) ++#define REG_COMB_BK05_70_L _PK_L_(0x05, 0x70) ++#define REG_COMB_BK05_70_H _PK_H_(0x05, 0x70) ++#define REG_COMB_BK05_71_L _PK_L_(0x05, 0x71) ++#define REG_COMB_BK05_71_H _PK_H_(0x05, 0x71) ++#define REG_COMB_BK05_72_L _PK_L_(0x05, 0x72) ++#define REG_COMB_BK05_72_H _PK_H_(0x05, 0x72) ++#define REG_COMB_BK05_73_L _PK_L_(0x05, 0x73) ++#define REG_COMB_BK05_73_H _PK_H_(0x05, 0x73) ++#define REG_COMB_BK05_74_L _PK_L_(0x05, 0x74) ++#define REG_COMB_BK05_74_H _PK_H_(0x05, 0x74) ++#define REG_COMB_BK05_75_L _PK_L_(0x05, 0x75) ++#define REG_COMB_BK05_75_H _PK_H_(0x05, 0x75) ++#define REG_COMB_BK05_76_L _PK_L_(0x05, 0x76) ++#define REG_COMB_BK05_76_H _PK_H_(0x05, 0x76) ++#define REG_COMB_BK05_77_L _PK_L_(0x05, 0x77) ++#define REG_COMB_BK05_77_H _PK_H_(0x05, 0x77) ++#define REG_COMB_BK05_78_L _PK_L_(0x05, 0x78) ++#define REG_COMB_BK05_78_H _PK_H_(0x05, 0x78) ++#define REG_COMB_BK05_79_L _PK_L_(0x05, 0x79) ++#define REG_COMB_BK05_79_H _PK_H_(0x05, 0x79) ++#define REG_COMB_BK05_7A_L _PK_L_(0x05, 0x7A) ++#define REG_COMB_BK05_7A_H _PK_H_(0x05, 0x7A) ++#define REG_COMB_BK05_7B_L _PK_L_(0x05, 0x7B) ++#define REG_COMB_BK05_7B_H _PK_H_(0x05, 0x7B) ++#define REG_COMB_BK05_7C_L _PK_L_(0x05, 0x7C) ++#define REG_COMB_BK05_7C_H _PK_H_(0x05, 0x7C) ++#define REG_COMB_BK05_7D_L _PK_L_(0x05, 0x7D) ++#define REG_COMB_BK05_7D_H _PK_H_(0x05, 0x7D) ++#define REG_COMB_BK05_7E_L _PK_L_(0x05, 0x7E) ++#define REG_COMB_BK05_7E_H _PK_H_(0x05, 0x7E) ++#define REG_COMB_BK05_7F_L _PK_L_(0x05, 0x7F) ++#define REG_COMB_BK05_7F_H _PK_H_(0x05, 0x7F) ++//---------------------------------------------- ++#define REG_BK2C_00_L 0x2C00 ++#define REG_BK2C_00_H 0x2C01 ++#define REG_BK2C_01_L 0x2C02 ++#define REG_BK2C_01_H 0x2C03 ++#define REG_BK2C_02_L 0x2C04 ++#define REG_BK2C_02_H 0x2C05 ++#define REG_BK2C_03_L 0x2C06 ++#define REG_BK2C_03_H 0x2C07 ++#define REG_BK2C_04_L 0x2C08 ++#define REG_BK2C_04_H 0x2C09 ++#define REG_BK2C_05_L 0x2C0A ++#define REG_BK2C_05_H 0x2C0B ++#define REG_BK2C_06_L 0x2C0C ++#define REG_BK2C_06_H 0x2C0D ++#define REG_BK2C_07_L 0x2C0E ++#define REG_BK2C_07_H 0x2C0F ++#define REG_BK2C_08_L 0x2C10 ++#define REG_BK2C_08_H 0x2C11 ++#define REG_BK2C_09_L 0x2C12 ++#define REG_BK2C_09_H 0x2C13 ++#define REG_BK2C_0A_L 0x2C14 ++#define REG_BK2C_0A_H 0x2C15 ++#define REG_BK2C_0B_L 0x2C16 ++#define REG_BK2C_0B_H 0x2C17 ++#define REG_BK2C_0C_L 0x2C18 ++#define REG_BK2C_0C_H 0x2C19 ++#define REG_BK2C_0D_L 0x2C1A ++#define REG_BK2C_0D_H 0x2C1B ++#define REG_BK2C_0E_L 0x2C1C ++#define REG_BK2C_0E_H 0x2C1D ++#define REG_BK2C_0F_L 0x2C1E ++#define REG_BK2C_0F_H 0x2C1F ++#define REG_BK2C_10_L 0x2C20 ++#define REG_BK2C_10_H 0x2C21 ++#define REG_BK2C_11_L 0x2C22 ++#define REG_BK2C_11_H 0x2C23 ++#define REG_BK2C_12_L 0x2C24 ++#define REG_BK2C_12_H 0x2C25 ++#define REG_BK2C_13_L 0x2C26 ++#define REG_BK2C_13_H 0x2C27 ++#define REG_BK2C_14_L 0x2C28 ++#define REG_BK2C_14_H 0x2C29 ++#define REG_BK2C_15_L 0x2C2A ++#define REG_BK2C_15_H 0x2C2B ++#define REG_BK2C_16_L 0x2C2C ++#define REG_BK2C_16_H 0x2C2D ++#define REG_BK2C_17_L 0x2C2E ++#define REG_BK2C_17_H 0x2C2F ++#define REG_BK2C_18_L 0x2C30 ++#define REG_BK2C_18_H 0x2C31 ++#define REG_BK2C_19_L 0x2C32 ++#define REG_BK2C_19_H 0x2C33 ++#define REG_BK2C_1A_L 0x2C34 ++#define REG_BK2C_1A_H 0x2C35 ++#define REG_BK2C_1B_L 0x2C36 ++#define REG_BK2C_1B_H 0x2C37 ++#define REG_BK2C_1C_L 0x2C38 ++#define REG_BK2C_1C_H 0x2C39 ++#define REG_BK2C_1D_L 0x2C3A ++#define REG_BK2C_1D_H 0x2C3B ++#define REG_BK2C_1E_L 0x2C3C ++#define REG_BK2C_1E_H 0x2C3D ++#define REG_BK2C_1F_L 0x2C3E ++#define REG_BK2C_1F_H 0x2C3F ++#define REG_BK2C_20_L 0x2C40 ++#define REG_BK2C_20_H 0x2C41 ++#define REG_BK2C_21_L 0x2C42 ++#define REG_BK2C_21_H 0x2C43 ++#define REG_BK2C_22_L 0x2C44 ++#define REG_BK2C_22_H 0x2C45 ++#define REG_BK2C_23_L 0x2C46 ++#define REG_BK2C_23_H 0x2C47 ++#define REG_BK2C_24_L 0x2C48 ++#define REG_BK2C_24_H 0x2C49 ++#define REG_BK2C_25_L 0x2C4A ++#define REG_BK2C_25_H 0x2C4B ++#define REG_BK2C_26_L 0x2C4C ++#define REG_BK2C_26_H 0x2C4D ++#define REG_BK2C_27_L 0x2C4E ++#define REG_BK2C_27_H 0x2C4F ++#define REG_BK2C_28_L 0x2C50 ++#define REG_BK2C_28_H 0x2C51 ++#define REG_BK2C_29_L 0x2C52 ++#define REG_BK2C_29_H 0x2C53 ++#define REG_BK2C_2A_L 0x2C54 ++#define REG_BK2C_2A_H 0x2C55 ++#define REG_BK2C_2B_L 0x2C56 ++#define REG_BK2C_2B_H 0x2C57 ++#define REG_BK2C_2C_L 0x2C58 ++#define REG_BK2C_2C_H 0x2C59 ++#define REG_BK2C_2D_L 0x2C5A ++#define REG_BK2C_2D_H 0x2C5B ++#define REG_BK2C_2E_L 0x2C5C ++#define REG_BK2C_2E_H 0x2C5D ++#define REG_BK2C_2F_L 0x2C5E ++#define REG_BK2C_2F_H 0x2C5F ++#define REG_BK2C_30_L 0x2C60 ++#define REG_BK2C_30_H 0x2C61 ++#define REG_BK2C_31_L 0x2C62 ++#define REG_BK2C_31_H 0x2C63 ++#define REG_BK2C_32_L 0x2C64 ++#define REG_BK2C_32_H 0x2C65 ++#define REG_BK2C_33_L 0x2C66 ++#define REG_BK2C_33_H 0x2C67 ++#define REG_BK2C_34_L 0x2C68 ++#define REG_BK2C_34_H 0x2C69 ++#define REG_BK2C_35_L 0x2C6A ++#define REG_BK2C_35_H 0x2C6B ++#define REG_BK2C_36_L 0x2C6C ++#define REG_BK2C_36_H 0x2C6D ++#define REG_BK2C_37_L 0x2C6E ++#define REG_BK2C_37_H 0x2C6F ++#define REG_BK2C_38_L 0x2C70 ++#define REG_BK2C_38_H 0x2C71 ++#define REG_BK2C_39_L 0x2C72 ++#define REG_BK2C_39_H 0x2C73 ++#define REG_BK2C_3A_L 0x2C74 ++#define REG_BK2C_3A_H 0x2C75 ++#define REG_BK2C_3B_L 0x2C76 ++#define REG_BK2C_3B_H 0x2C77 ++#define REG_BK2C_3C_L 0x2C78 ++#define REG_BK2C_3C_H 0x2C79 ++#define REG_BK2C_3D_L 0x2C7A ++#define REG_BK2C_3D_H 0x2C7B ++#define REG_BK2C_3E_L 0x2C7C ++#define REG_BK2C_3E_H 0x2C7D ++#define REG_BK2C_3F_L 0x2C7E ++#define REG_BK2C_3F_H 0x2C7F ++#define REG_BK2C_40_L 0x2C80 ++#define REG_BK2C_40_H 0x2C81 ++#define REG_BK2C_41_L 0x2C82 ++#define REG_BK2C_41_H 0x2C83 ++#define REG_BK2C_42_L 0x2C84 ++#define REG_BK2C_42_H 0x2C85 ++#define REG_BK2C_43_L 0x2C86 ++#define REG_BK2C_43_H 0x2C87 ++#define REG_BK2C_44_L 0x2C88 ++#define REG_BK2C_44_H 0x2C89 ++#define REG_BK2C_45_L 0x2C8A ++#define REG_BK2C_45_H 0x2C8B ++#define REG_BK2C_46_L 0x2C8C ++#define REG_BK2C_46_H 0x2C8D ++#define REG_BK2C_47_L 0x2C8E ++#define REG_BK2C_47_H 0x2C8F ++#define REG_BK2C_48_L 0x2C90 ++#define REG_BK2C_48_H 0x2C91 ++#define REG_BK2C_49_L 0x2C92 ++#define REG_BK2C_49_H 0x2C93 ++#define REG_BK2C_4A_L 0x2C94 ++#define REG_BK2C_4A_H 0x2C95 ++#define REG_BK2C_4B_L 0x2C96 ++#define REG_BK2C_4B_H 0x2C97 ++#define REG_BK2C_4C_L 0x2C98 ++#define REG_BK2C_4C_H 0x2C99 ++#define REG_BK2C_4D_L 0x2C9A ++#define REG_BK2C_4D_H 0x2C9B ++#define REG_BK2C_4E_L 0x2C9C ++#define REG_BK2C_4E_H 0x2C9D ++#define REG_BK2C_4F_L 0x2C9E ++#define REG_BK2C_4F_H 0x2C9F ++#define REG_BK2C_50_L 0x2CA0 ++#define REG_BK2C_50_H 0x2CA1 ++#define REG_BK2C_51_L 0x2CA2 ++#define REG_BK2C_51_H 0x2CA3 ++#define REG_BK2C_52_L 0x2CA4 ++#define REG_BK2C_52_H 0x2CA5 ++#define REG_BK2C_53_L 0x2CA6 ++#define REG_BK2C_53_H 0x2CA7 ++#define REG_BK2C_54_L 0x2CA8 ++#define REG_BK2C_54_H 0x2CA9 ++#define REG_BK2C_55_L 0x2CAA ++#define REG_BK2C_55_H 0x2CAB ++#define REG_BK2C_56_L 0x2CAC ++#define REG_BK2C_56_H 0x2CAD ++#define REG_BK2C_57_L 0x2CAE ++#define REG_BK2C_57_H 0x2CAF ++#define REG_BK2C_58_L 0x2CB0 ++#define REG_BK2C_58_H 0x2CB1 ++#define REG_BK2C_59_L 0x2CB2 ++#define REG_BK2C_59_H 0x2CB3 ++#define REG_BK2C_5A_L 0x2CB4 ++#define REG_BK2C_5A_H 0x2CB5 ++#define REG_BK2C_5B_L 0x2CB6 ++#define REG_BK2C_5B_H 0x2CB7 ++#define REG_BK2C_5C_L 0x2CB8 ++#define REG_BK2C_5C_H 0x2CB9 ++#define REG_BK2C_5D_L 0x2CBA ++#define REG_BK2C_5D_H 0x2CBB ++#define REG_BK2C_5E_L 0x2CBC ++#define REG_BK2C_5E_H 0x2CBD ++#define REG_BK2C_5F_L 0x2CBE ++#define REG_BK2C_5F_H 0x2CBF ++#define REG_BK2C_60_L 0x2CC0 ++#define REG_BK2C_60_H 0x2CC1 ++#define REG_BK2C_61_L 0x2CC2 ++#define REG_BK2C_61_H 0x2CC3 ++#define REG_BK2C_62_L 0x2CC4 ++#define REG_BK2C_62_H 0x2CC5 ++#define REG_BK2C_63_L 0x2CC6 ++#define REG_BK2C_63_H 0x2CC7 ++#define REG_BK2C_64_L 0x2CC8 ++#define REG_BK2C_64_H 0x2CC9 ++#define REG_BK2C_65_L 0x2CCA ++#define REG_BK2C_65_H 0x2CCB ++#define REG_BK2C_66_L 0x2CCC ++#define REG_BK2C_66_H 0x2CCD ++#define REG_BK2C_67_L 0x2CCE ++#define REG_BK2C_67_H 0x2CCF ++#define REG_BK2C_68_L 0x2CD0 ++#define REG_BK2C_68_H 0x2CD1 ++#define REG_BK2C_69_L 0x2CD2 ++#define REG_BK2C_69_H 0x2CD3 ++#define REG_BK2C_6A_L 0x2CD4 ++#define REG_BK2C_6A_H 0x2CD5 ++#define REG_BK2C_6B_L 0x2CD6 ++#define REG_BK2C_6B_H 0x2CD7 ++#define REG_BK2C_6C_L 0x2CD8 ++#define REG_BK2C_6C_H 0x2CD9 ++#define REG_BK2C_6D_L 0x2CDA ++#define REG_BK2C_6D_H 0x2CDB ++#define REG_BK2C_6E_L 0x2CDC ++#define REG_BK2C_6E_H 0x2CDD ++#define REG_BK2C_6F_L 0x2CDE ++#define REG_BK2C_6F_H 0x2CDF ++#define REG_BK2C_70_L 0x2CE0 ++#define REG_BK2C_70_H 0x2CE1 ++#define REG_BK2C_71_L 0x2CE2 ++#define REG_BK2C_71_H 0x2CE3 ++#define REG_BK2C_72_L 0x2CE4 ++#define REG_BK2C_72_H 0x2CE5 ++#define REG_BK2C_73_L 0x2CE6 ++#define REG_BK2C_73_H 0x2CE7 ++#define REG_BK2C_74_L 0x2CE8 ++#define REG_BK2C_74_H 0x2CE9 ++#define REG_BK2C_75_L 0x2CEA ++#define REG_BK2C_75_H 0x2CEB ++#define REG_BK2C_76_L 0x2CEC ++#define REG_BK2C_76_H 0x2CED ++#define REG_BK2C_77_L 0x2CEE ++#define REG_BK2C_77_H 0x2CEF ++#define REG_BK2C_78_L 0x2CF0 ++#define REG_BK2C_78_H 0x2CF1 ++#define REG_BK2C_79_L 0x2CF2 ++#define REG_BK2C_79_H 0x2CF3 ++#define REG_BK2C_7A_L 0x2CF4 ++#define REG_BK2C_7A_H 0x2CF5 ++#define REG_BK2C_7B_L 0x2CF6 ++#define REG_BK2C_7B_H 0x2CF7 ++#define REG_BK2C_7C_L 0x2CF8 ++#define REG_BK2C_7C_H 0x2CF9 ++#define REG_BK2C_7D_L 0x2CFA ++#define REG_BK2C_7D_H 0x2CFB ++#define REG_BK2C_7E_L 0x2CFC ++#define REG_BK2C_7E_H 0x2CFD ++#define REG_BK2C_7F_L 0x2CFE ++#define REG_BK2C_7F_H 0x2CFF ++//---------------------------------------------- ++#define REG_BK38_00_L 0x3800 ++#define REG_BK38_00_H 0x3801 ++#define REG_BK38_01_L 0x3802 ++#define REG_BK38_01_H 0x3803 ++#define REG_BK38_02_L 0x3804 ++#define REG_BK38_02_H 0x3805 ++#define REG_BK38_03_L 0x3806 ++#define REG_BK38_03_H 0x3807 ++#define REG_BK38_04_L 0x3808 ++#define REG_BK38_04_H 0x3809 ++#define REG_BK38_05_L 0x380A ++#define REG_BK38_05_H 0x380B ++#define REG_BK38_06_L 0x380C ++#define REG_BK38_06_H 0x380D ++#define REG_BK38_07_L 0x380E ++#define REG_BK38_07_H 0x380F ++#define REG_BK38_08_L 0x3810 ++#define REG_BK38_08_H 0x3811 ++#define REG_BK38_09_L 0x3812 ++#define REG_BK38_09_H 0x3813 ++#define REG_BK38_0A_L 0x3814 ++#define REG_BK38_0A_H 0x3815 ++#define REG_BK38_0B_L 0x3816 ++#define REG_BK38_0B_H 0x3817 ++#define REG_BK38_0C_L 0x3818 ++#define REG_BK38_0C_H 0x3819 ++#define REG_BK38_0D_L 0x381A ++#define REG_BK38_0D_H 0x381B ++#define REG_BK38_0E_L 0x381C ++#define REG_BK38_0E_H 0x381D ++#define REG_BK38_0F_L 0x381E ++#define REG_BK38_0F_H 0x381F ++#define REG_BK38_10_L 0x3820 ++#define REG_BK38_10_H 0x3821 ++#define REG_BK38_11_L 0x3822 ++#define REG_BK38_11_H 0x3823 ++#define REG_BK38_12_L 0x3824 ++#define REG_BK38_12_H 0x3825 ++#define REG_BK38_13_L 0x3826 ++#define REG_BK38_13_H 0x3827 ++#define REG_BK38_14_L 0x3828 ++#define REG_BK38_14_H 0x3829 ++#define REG_BK38_15_L 0x382A ++#define REG_BK38_15_H 0x382B ++#define REG_BK38_16_L 0x382C ++#define REG_BK38_16_H 0x382D ++#define REG_BK38_17_L 0x382E ++#define REG_BK38_17_H 0x382F ++#define REG_BK38_18_L 0x3830 ++#define REG_BK38_18_H 0x3831 ++#define REG_BK38_19_L 0x3832 ++#define REG_BK38_19_H 0x3833 ++#define REG_BK38_1A_L 0x3834 ++#define REG_BK38_1A_H 0x3835 ++#define REG_BK38_1B_L 0x3836 ++#define REG_BK38_1B_H 0x3837 ++#define REG_BK38_1C_L 0x3838 ++#define REG_BK38_1C_H 0x3839 ++#define REG_BK38_1D_L 0x383A ++#define REG_BK38_1D_H 0x383B ++#define REG_BK38_1E_L 0x383C ++#define REG_BK38_1E_H 0x383D ++#define REG_BK38_1F_L 0x383E ++#define REG_BK38_1F_H 0x383F ++#define REG_BK38_20_L 0x3840 ++#define REG_BK38_20_H 0x3841 ++#define REG_BK38_21_L 0x3842 ++#define REG_BK38_21_H 0x3843 ++#define REG_BK38_22_L 0x3844 ++#define REG_BK38_22_H 0x3845 ++#define REG_BK38_23_L 0x3846 ++#define REG_BK38_23_H 0x3847 ++#define REG_BK38_24_L 0x3848 ++#define REG_BK38_24_H 0x3849 ++#define REG_BK38_25_L 0x384A ++#define REG_BK38_25_H 0x384B ++#define REG_BK38_26_L 0x384C ++#define REG_BK38_26_H 0x384D ++#define REG_BK38_27_L 0x384E ++#define REG_BK38_27_H 0x384F ++#define REG_BK38_28_L 0x3850 ++#define REG_BK38_28_H 0x3851 ++#define REG_BK38_29_L 0x3852 ++#define REG_BK38_29_H 0x3853 ++#define REG_BK38_2A_L 0x3854 ++#define REG_BK38_2A_H 0x3855 ++#define REG_BK38_2B_L 0x3856 ++#define REG_BK38_2B_H 0x3857 ++#define REG_BK38_2C_L 0x3858 ++#define REG_BK38_2C_H 0x3859 ++#define REG_BK38_2D_L 0x385A ++#define REG_BK38_2D_H 0x385B ++#define REG_BK38_2E_L 0x385C ++#define REG_BK38_2E_H 0x385D ++#define REG_BK38_2F_L 0x385E ++#define REG_BK38_2F_H 0x385F ++#define REG_BK38_30_L 0x3860 ++#define REG_BK38_30_H 0x3861 ++#define REG_BK38_31_L 0x3862 ++#define REG_BK38_31_H 0x3863 ++#define REG_BK38_32_L 0x3864 ++#define REG_BK38_32_H 0x3865 ++#define REG_BK38_33_L 0x3866 ++#define REG_BK38_33_H 0x3867 ++#define REG_BK38_34_L 0x3868 ++#define REG_BK38_34_H 0x3869 ++#define REG_BK38_35_L 0x386A ++#define REG_BK38_35_H 0x386B ++#define REG_BK38_36_L 0x386C ++#define REG_BK38_36_H 0x386D ++#define REG_BK38_37_L 0x386E ++#define REG_BK38_37_H 0x386F ++#define REG_BK38_38_L 0x3870 ++#define REG_BK38_38_H 0x3871 ++#define REG_BK38_39_L 0x3872 ++#define REG_BK38_39_H 0x3873 ++#define REG_BK38_3A_L 0x3874 ++#define REG_BK38_3A_H 0x3875 ++#define REG_BK38_3B_L 0x3876 ++#define REG_BK38_3B_H 0x3877 ++#define REG_BK38_3C_L 0x3878 ++#define REG_BK38_3C_H 0x3879 ++#define REG_BK38_3D_L 0x387A ++#define REG_BK38_3D_H 0x387B ++#define REG_BK38_3E_L 0x387C ++#define REG_BK38_3E_H 0x387D ++#define REG_BK38_3F_L 0x387E ++#define REG_BK38_3F_H 0x387F ++#define REG_BK38_40_L 0x3880 ++#define REG_BK38_40_H 0x3881 ++#define REG_BK38_41_L 0x3882 ++#define REG_BK38_41_H 0x3883 ++#define REG_BK38_42_L 0x3884 ++#define REG_BK38_42_H 0x3885 ++#define REG_BK38_43_L 0x3886 ++#define REG_BK38_43_H 0x3887 ++#define REG_BK38_44_L 0x3888 ++#define REG_BK38_44_H 0x3889 ++#define REG_BK38_45_L 0x388A ++#define REG_BK38_45_H 0x388B ++#define REG_BK38_46_L 0x388C ++#define REG_BK38_46_H 0x388D ++#define REG_BK38_47_L 0x388E ++#define REG_BK38_47_H 0x388F ++#define REG_BK38_48_L 0x3890 ++#define REG_BK38_48_H 0x3891 ++#define REG_BK38_49_L 0x3892 ++#define REG_BK38_49_H 0x3893 ++#define REG_BK38_4A_L 0x3894 ++#define REG_BK38_4A_H 0x3895 ++#define REG_BK38_4B_L 0x3896 ++#define REG_BK38_4B_H 0x3897 ++#define REG_BK38_4C_L 0x3898 ++#define REG_BK38_4C_H 0x3899 ++#define REG_BK38_4D_L 0x389A ++#define REG_BK38_4D_H 0x389B ++#define REG_BK38_4E_L 0x389C ++#define REG_BK38_4E_H 0x389D ++#define REG_BK38_4F_L 0x389E ++#define REG_BK38_4F_H 0x389F ++#define REG_BK38_50_L 0x38A0 ++#define REG_BK38_50_H 0x38A1 ++#define REG_BK38_51_L 0x38A2 ++#define REG_BK38_51_H 0x38A3 ++#define REG_BK38_52_L 0x38A4 ++#define REG_BK38_52_H 0x38A5 ++#define REG_BK38_53_L 0x38A6 ++#define REG_BK38_53_H 0x38A7 ++#define REG_BK38_54_L 0x38A8 ++#define REG_BK38_54_H 0x38A9 ++#define REG_BK38_55_L 0x38AA ++#define REG_BK38_55_H 0x38AB ++#define REG_BK38_56_L 0x38AC ++#define REG_BK38_56_H 0x38AD ++#define REG_BK38_57_L 0x38AE ++#define REG_BK38_57_H 0x38AF ++#define REG_BK38_58_L 0x38B0 ++#define REG_BK38_58_H 0x38B1 ++#define REG_BK38_59_L 0x38B2 ++#define REG_BK38_59_H 0x38B3 ++#define REG_BK38_5A_L 0x38B4 ++#define REG_BK38_5A_H 0x38B5 ++#define REG_BK38_5B_L 0x38B6 ++#define REG_BK38_5B_H 0x38B7 ++#define REG_BK38_5C_L 0x38B8 ++#define REG_BK38_5C_H 0x38B9 ++#define REG_BK38_5D_L 0x38BA ++#define REG_BK38_5D_H 0x38BB ++#define REG_BK38_5E_L 0x38BC ++#define REG_BK38_5E_H 0x38BD ++#define REG_BK38_5F_L 0x38BE ++#define REG_BK38_5F_H 0x38BF ++#define REG_BK38_60_L 0x38C0 ++#define REG_BK38_60_H 0x38C1 ++#define REG_BK38_61_L 0x38C2 ++#define REG_BK38_61_H 0x38C3 ++#define REG_BK38_62_L 0x38C4 ++#define REG_BK38_62_H 0x38C5 ++#define REG_BK38_63_L 0x38C6 ++#define REG_BK38_63_H 0x38C7 ++#define REG_BK38_64_L 0x38C8 ++#define REG_BK38_64_H 0x38C9 ++#define REG_BK38_65_L 0x38CA ++#define REG_BK38_65_H 0x38CB ++#define REG_BK38_66_L 0x38CC ++#define REG_BK38_66_H 0x38CD ++#define REG_BK38_67_L 0x38CE ++#define REG_BK38_67_H 0x38CF ++#define REG_BK38_68_L 0x38D0 ++#define REG_BK38_68_H 0x38D1 ++#define REG_BK38_69_L 0x38D2 ++#define REG_BK38_69_H 0x38D3 ++#define REG_BK38_6A_L 0x38D4 ++#define REG_BK38_6A_H 0x38D5 ++#define REG_BK38_6B_L 0x38D6 ++#define REG_BK38_6B_H 0x38D7 ++#define REG_BK38_6C_L 0x38D8 ++#define REG_BK38_6C_H 0x38D9 ++#define REG_BK38_6D_L 0x38DA ++#define REG_BK38_6D_H 0x38DB ++#define REG_BK38_6E_L 0x38DC ++#define REG_BK38_6E_H 0x38DD ++#define REG_BK38_6F_L 0x38DE ++#define REG_BK38_6F_H 0x38DF ++#define REG_BK38_70_L 0x38E0 ++#define REG_BK38_70_H 0x38E1 ++#define REG_BK38_71_L 0x38E2 ++#define REG_BK38_71_H 0x38E3 ++#define REG_BK38_72_L 0x38E4 ++#define REG_BK38_72_H 0x38E5 ++#define REG_BK38_73_L 0x38E6 ++#define REG_BK38_73_H 0x38E7 ++#define REG_BK38_74_L 0x38E8 ++#define REG_BK38_74_H 0x38E9 ++#define REG_BK38_75_L 0x38EA ++#define REG_BK38_75_H 0x38EB ++#define REG_BK38_76_L 0x38EC ++#define REG_BK38_76_H 0x38ED ++#define REG_BK38_77_L 0x38EE ++#define REG_BK38_77_H 0x38EF ++#define REG_BK38_78_L 0x38F0 ++#define REG_BK38_78_H 0x38F1 ++#define REG_BK38_79_L 0x38F2 ++#define REG_BK38_79_H 0x38F3 ++#define REG_BK38_7A_L 0x38F4 ++#define REG_BK38_7A_H 0x38F5 ++#define REG_BK38_7B_L 0x38F6 ++#define REG_BK38_7B_H 0x38F7 ++#define REG_BK38_7C_L 0x38F8 ++#define REG_BK38_7C_H 0x38F9 ++#define REG_BK38_7D_L 0x38FA ++#define REG_BK38_7D_H 0x38FB ++#define REG_BK38_7E_L 0x38FC ++#define REG_BK38_7E_H 0x38FD ++#define REG_BK38_7F_L 0x38FE ++#define REG_BK38_7F_H 0x38FF ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/drvPQ_Declare.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/drvPQ_Declare.h +new file mode 100644 +index 00000000..656f5ea3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/drvPQ_Declare.h +@@ -0,0 +1,485 @@ ++#ifndef _DRVPQ_DECLARE_H ++#define _DRVPQ_DECLARE_H ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++// function macro ++// ++//### MDrv_PQ_DumpTable ++#define MDrv_PQ_DumpTable_(PQTABLE_NAME, pIP_Info) \ ++ MDrv_PQ_DumpTable_##PQTABLE_NAME(pIP_Info) ++ ++#define DECLARE_MDrv_PQ_DumpTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_DumpTable_##PQTABLE_NAME(EN_IP_Info* pIP_Info); ++ ++#define INSTALL_MDrv_PQ_DumpTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_DumpTable_##PQTABLE_NAME(EN_IP_Info* pIP_Info){ \ ++ _MDrv_PQ_DumpTable(pIP_Info); \ ++ } ++ ++ ++//### MDrv_PQ_GetIPNum ++#define MDrv_PQ_GetIPNum_(PQTABLE_NAME) \ ++ MDrv_PQ_GetIPNum_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_GetIPNum_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetIPNum_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_GetIPNum_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetIPNum_##PQTABLE_NAME(void){ \ ++ return _MDrv_PQ_GetIPNum(); \ ++ } ++ ++ ++//### MDrv_PQ_GetTableNum ++#define MDrv_PQ_GetTableNum_(PQTABLE_NAME, u8PQIPIdx) \ ++ MDrv_PQ_GetTableNum_##PQTABLE_NAME(u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetTableNum_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetTableNum_##PQTABLE_NAME(MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetTableNum_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetTableNum_##PQTABLE_NAME(MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetTableNum(u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_GetCurrentTableIndex ++#define MDrv_PQ_GetCurrentTableIndex_(PQTABLE_NAME, u8PQIPIdx) \ ++ MDrv_PQ_GetCurrentTableIndex_##PQTABLE_NAME(u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetCurrentTableIndex_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetCurrentTableIndex_##PQTABLE_NAME(MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetCurrentTableIndex_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetCurrentTableIndex_##PQTABLE_NAME(MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetCurrentTableIndex(u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_GetTableIndex ++#define MDrv_PQ_GetTableIndex_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_GetTableIndex_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetTableIndex_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetTableIndex_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetTableIndex_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetTableIndex_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetTableIndex(u16PQSrcType, u8PQIPIdx ); \ ++ } ++ ++ ++//### MDrv_PQ_GetTable ++#define MDrv_PQ_GetTable_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx) \ ++ MDrv_PQ_GetTable_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetTable_(PQTABLE_NAME) \ ++ extern EN_IP_Info MDrv_PQ_GetTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetTable_(PQTABLE_NAME) \ ++ EN_IP_Info MDrv_PQ_GetTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_LoadTableData ++#define MDrv_PQ_LoadTableData_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx, pTable, u16TableSize) \ ++ MDrv_PQ_LoadTableData_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx, pTable, u16TableSize) ++ ++#define DECLARE_MDrv_PQ_LoadTableData_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTableData_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize); ++ ++#define INSTALL_MDrv_PQ_LoadTableData_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTableData_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize){ \ ++ _MDrv_PQ_LoadTableData(u8TabIdx, u8PQIPIdx, pTable, u16TableSize); \ ++ } ++ ++//### MDrv_PQ_LoadTable ++#define MDrv_PQ_LoadTable_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx) \ ++ MDrv_PQ_LoadTable_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_LoadTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_LoadTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx){ \ ++ _MDrv_PQ_LoadTable(u8TabIdx, u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_LoadCommTable ++#define MDrv_PQ_LoadCommTable_(PQTABLE_NAME) \ ++ MDrv_PQ_LoadCommTable_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_LoadCommTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadCommTable_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_LoadCommTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadCommTable_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_LoadCommTable(); \ ++ } ++ ++ ++//### MDrv_PQ_AddTable ++#define MDrv_PQ_AddTable_(PQTABLE_NAME, pPQTableInfo) \ ++ MDrv_PQ_AddTable_##PQTABLE_NAME(pPQTableInfo) ++ ++#define DECLARE_MDrv_PQ_AddTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_AddTable_##PQTABLE_NAME(PQTABLE_INFO *pPQTableInfo); ++ ++ ++#define INSTALL_MDrv_PQ_AddTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_AddTable_##PQTABLE_NAME(PQTABLE_INFO *pPQTableInfo){ \ ++ _MDrv_PQ_AddTable(pPQTableInfo); \ ++ } ++ ++ ++//### MDrv_PQ_LoadTableBySrcType ++#define MDrv_PQ_LoadTableBySrcType_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_LoadTableBySrcType_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_LoadTableBySrcType_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_LoadTableBySrcType_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx){ \ ++ _MDrv_PQ_LoadTableBySrcType(u16PQSrcType, u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_Set_CmdqCfg ++#define MDrv_PQ_Set_CmdqCfg_(PQTABLE_NAME, CmdqCfg) \ ++ MDrv_PQ_Set_CmdqCfg_##PQTABLE_NAME(CmdqCfg) ++ ++#define DECLARE_MDrv_PQ_Set_CmdqCfg_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_CmdqCfg_##PQTABLE_NAME(PQ_CMDQ_CONFIG CmdqCfg); ++ ++#define INSTALL_MDrv_PQ_Set_CmdqCfg_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_CmdqCfg_##PQTABLE_NAME(PQ_CMDQ_CONFIG CmdqCfg) {\ ++ _MDrv_PQ_Set_CmdqCfg(CmdqCfg); \ ++ } ++ ++//### MDRv_PQ_Check_Reg ++#define MDrv_PQ_Check_Type_(PQTABLE_NAME, EnCheck) \ ++ MDrv_PQ_Check_Type_##PQTABLE_NAME(EnCheck) ++ ++#define DECLARE_MDrv_PQ_Check_Type_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Check_Type_##PQTABLE_NAME(PQ_CHECK_TYPE EnCheck); ++ ++#define INSTALL_MDrv_PQ_Check_Type_(PQTABLE_NAME) \ ++ void MDrv_PQ_Check_Type_##PQTABLE_NAME(PQ_CHECK_TYPE EnCheck) {\ ++ _MDrv_PQ_Check_Type(EnCheck); \ ++ } ++ ++ ++//### MDrv_PQ_LoadTableByData ++#define MDrv_PQ_LoadTableByData_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx, pData) \ ++ MDrv_PQ_LoadTableByData_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx, pData) ++ ++#define DECLARE_MDrv_PQ_LoadTableByData_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTableByData_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx, PQ_DATA_INFO *pData); ++ ++#define INSTALL_MDrv_PQ_LoadTableByData_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTableByData_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx, PQ_DATA_INFO *pData){ \ ++ _MDrv_PQ_LoadTableByData(u16PQSrcType, u8PQIPIdx, pData); \ ++ } ++ ++ ++//### MDrv_PQ_CheckCommTable ++#define MDrv_PQ_CheckCommTable_(PQTABLE_NAME) \ ++ MDrv_PQ_CheckCommTable_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_CheckCommTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_CheckCommTable_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_CheckCommTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_CheckCommTable_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_CheckCommTable(); \ ++ } ++ ++ ++//### MDrv_PQ_CheckTableBySrcType ++#define MDrv_PQ_CheckTableBySrcType_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_CheckTableBySrcType_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_CheckTableBySrcType_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_CheckTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_CheckTableBySrcType_(PQTABLE_NAME) \ ++ void MDrv_PQ_CheckTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx){ \ ++ _MDrv_PQ_CheckTableBySrcType(u16PQSrcType, u8PQIPIdx); \ ++ } ++ ++//### MDrv_PQ_GetXRuleIPIndex ++#define MDrv_PQ_GetXRuleIPIndex_(PQTABLE_NAME, u8XRuleType, u8XRuleIP) \ ++ MDrv_PQ_GetXRuleIPIndex_##PQTABLE_NAME(u8XRuleType, u8XRuleIP) ++ ++#define DECLARE_MDrv_PQ_GetXRuleIPIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetXRuleIPIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIP); ++ ++#define INSTALL_MDrv_PQ_GetXRuleIPIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetXRuleIPIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIP){ \ ++ return _MDrv_PQ_GetXRuleIPIndex(u8XRuleType, u8XRuleIP); \ ++ } ++ ++//### MDrv_PQ_GetXRuleTableIndex ++#define MDrv_PQ_GetXRuleTableIndex_(PQTABLE_NAME, u8XRuleType, u8XRuleIdx, u8XRuleIP) \ ++ MDrv_PQ_GetXRuleTableIndex_##PQTABLE_NAME(u8XRuleType, u8XRuleIdx, u8XRuleIP) ++ ++#define DECLARE_MDrv_PQ_GetXRuleTableIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetXRuleTableIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIdx, MS_U8 u8XRuleIP); ++ ++#define INSTALL_MDrv_PQ_GetXRuleTableIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetXRuleTableIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIdx, MS_U8 u8XRuleIP){ \ ++ return _MDrv_PQ_GetXRuleTableIndex(u8XRuleType, u8XRuleIdx, u8XRuleIP); \ ++ } ++ ++ ++//### MDrv_PQ_GetXRuleIPNum ++#define MDrv_PQ_GetXRuleIPNum_(PQTABLE_NAME, u8XRuleType) \ ++ MDrv_PQ_GetXRuleIPNum_##PQTABLE_NAME(u8XRuleType) ++ ++#define DECLARE_MDrv_PQ_GetXRuleIPNum_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetXRuleIPNum_##PQTABLE_NAME(MS_U8 u8XRuleType); ++ ++#define INSTALL_MDrv_PQ_GetXRuleIPNum_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetXRuleIPNum_##PQTABLE_NAME(MS_U8 u8XRuleType){ \ ++ return _MDrv_PQ_GetXRuleIPNum(u8XRuleType); \ ++ } ++ ++ ++//### MDrv_PQ_GetGRule_LevelIndex ++#define MDrv_PQ_GetGRule_LevelIndex_(PQTABLE_NAME, u8GRuleType, u8GRuleLevelIndex) \ ++ MDrv_PQ_GetGRule_LevelIndex_##PQTABLE_NAME(u8GRuleType, u8GRuleLevelIndex) ++ ++#define DECLARE_MDrv_PQ_GetGRule_LevelIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetGRule_LevelIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleLevelIndex); ++ ++#define INSTALL_MDrv_PQ_GetGRule_LevelIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetGRule_LevelIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleLevelIndex){ \ ++ return _MDrv_PQ_GetGRule_LevelIndex(u8GRuleType, u8GRuleLevelIndex); \ ++ } ++ ++ ++//### MDrv_PQ_GetGRule_IPIndex ++#define MDrv_PQ_GetGRule_IPIndex_(PQTABLE_NAME, u8GRuleType, u8GRuleIPIndex) \ ++ MDrv_PQ_GetGRule_IPIndex_##PQTABLE_NAME(u8GRuleType, u8GRuleIPIndex) ++ ++#define DECLARE_MDrv_PQ_GetGRule_IPIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetGRule_IPIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleIPIndex); ++ ++#define INSTALL_MDrv_PQ_GetGRule_IPIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetGRule_IPIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleIPIndex){ \ ++ return _MDrv_PQ_GetGRule_IPIndex(u8GRuleType, u8GRuleIPIndex); \ ++ } ++ ++ ++//### MDrv_PQ_GetGRule_TableIndex ++#define MDrv_PQ_GetGRule_TableIndex_(PQTABLE_NAME, u8GRuleType, u8PQSrcType, u8PQ_NRIdx, u8GRuleIPIndex) \ ++ MDrv_PQ_GetGRule_TableIndex_##PQTABLE_NAME(u8GRuleType, u8PQSrcType, u8PQ_NRIdx, u8GRuleIPIndex) ++ ++#define DECLARE_MDrv_PQ_GetGRule_TableIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetGRule_TableIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8PQSrcType, MS_U8 u8PQ_NRIdx, MS_U8 u8GRuleIPIndex); ++ ++#define INSTALL_MDrv_PQ_GetGRule_TableIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetGRule_TableIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8PQSrcType, MS_U8 u8PQ_NRIdx, MS_U8 u8GRuleIPIndex){ \ ++ return _MDrv_PQ_GetGRule_TableIndex(u8GRuleType, u8PQSrcType, u8PQ_NRIdx, u8GRuleIPIndex); \ ++ } ++ ++//### MDrv_PQ_Set_MLoadEn ++#define MDrv_PQ_Set_MLoadEn_(PQTABLE_NAME, bEn) \ ++ MDrv_PQ_Set_MLoadEn_##PQTABLE_NAME(bEn) ++ ++#define DECLARE_MDrv_PQ_Set_MLoadEn_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_MLoadEn_##PQTABLE_NAME(MS_BOOL bEn); ++ ++#define INSTALL_MDrv_PQ_Set_MLoadEn_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_MLoadEn_##PQTABLE_NAME(MS_BOOL bEn){ \ ++ _MDrv_PQ_Set_MLoadEn(bEn); \ ++ } ++ ++ ++//### MDrv_PQ_PreInitLoadTableInfo ++#define MDrv_PQ_PreInitLoadTableInfo(PQTABLE_NAME) \ ++ MDrv_PQ_PreInitLoadTableInfo_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_PreInitLoadTableInfo_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_PreInitLoadTableInfo_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_PreInitLoadTableInfo_(PQTABLE_NAME) \ ++ void MDrv_PQ_PreInitLoadTableInfo_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_PreInitLoadTableInfo(); \ ++ } ++ ++//### _MDrv_PQ_Set_LoadTableInfo_IP_Tab ++#define MDrv_PQ_Set_LoadTableInfo_IP_Tab(PQTABLE_NAME, u16IPIdx, u8TabIdx) \ ++ MDrv_PQ_Set_LoadTableInfo_IP_Tab_##PQTABLE_NAME(u16IPIdx, u8TabIdx) ++ ++#define DECLARE_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx, MS_U8 u8TabIdx); ++ ++#define INSTALL_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx, MS_U8 u8TabIdx){ \ ++ _MDrv_PQ_Set_LoadTableInfo_IP_Tab(u16IPIdx, u8TabIdx); \ ++ } ++ ++ ++//### _MDrv_PQ_Get_LoadTableInfo_IP_Tab ++#define MDrv_PQ_Get_LoadTableInfo_IP_Tab(PQTABLE_NAME, u16IPIdx) \ ++ MDrv_PQ_Get_LoadTableInfo_IP_Tab_##PQTABLE_NAME(u16IPIdx) ++ ++#define DECLARE_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_Get_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx); ++ ++#define INSTALL_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_Get_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx){ \ ++ return _MDrv_PQ_Get_LoadTableInfo_IP_Tab(u16IPIdx); \ ++ } ++ ++ ++//### _MDrv_PQ_Set_LoadTableInfo_SrcType ++#define MDrv_PQ_Set_LoadTableInfo_SrcType(PQTABLE_NAME, u16SrcType) \ ++ MDrv_PQ_Set_LoadTableInfo_SrcType_##PQTABLE_NAME(u16SrcType) ++ ++#define DECLARE_MDrv_PQ_Set_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_LoadTableInfo_SrcType_##PQTABLE_NAME(MS_U16 u16SrcType); ++ ++#define INSTALL_MDrv_PQ_Set_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_LoadTableInfo_SrcType_##PQTABLE_NAME(MS_U16 u16SrcType){ \ ++ _MDrv_PQ_Set_LoadTableInfo_SrcType(u16SrcType); \ ++ } ++ ++ ++//### _MDrv_PQ_Get_LoadTableInfo_SrcType ++#define MDrv_PQ_Get_LoadTableInfo_SrcType(PQTABLE_NAME) \ ++ MDrv_PQ_Get_LoadTableInfo_SrcType_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_Get_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_Get_LoadTableInfo_SrcType_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_Get_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_Get_LoadTableInfo_SrcType_##PQTABLE_NAME(void){ \ ++ return _MDrv_PQ_Get_LoadTableInfo_SrcType(); \ ++ } ++ ++ ++//### _MDrv_PQ_ClearTableIndex ++#define MDrv_PQ_ClearTableIndex(PQTABLE_NAME) \ ++ MDrv_PQ_ClearTableIndex_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_ClearTableIndex_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_ClearTableIndex_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_ClearTableIndex_(PQTABLE_NAME) \ ++ void MDrv_PQ_ClearTableIndex_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_ClearTableIndex(); \ ++ } ++ ++ ++//### MDrv_PQ_LoadPictureSetting ++#define MDrv_PQ_LoadPictureSetting_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx, pTable, u16TableSize) \ ++ MDrv_PQ_LoadPictureSetting_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx, pTable, u16TableSize) ++ ++#define DECLARE_MDrv_PQ_LoadPictureSetting_(PQTABLE_NAME) \ ++ extern MS_BOOL MDrv_PQ_LoadPictureSetting_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, void *pTable, MS_U16 u16TableSize); ++ ++#define INSTALL_MDrv_PQ_LoadPictureSetting_(PQTABLE_NAME) \ ++ MS_BOOL MDrv_PQ_LoadPictureSetting_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, void *pTable, MS_U16 u16TableSize){ \ ++ return _MDrv_PQ_LoadPictureSetting(u8TabIdx, u8PQIPIdx, pTable, u16TableSize); \ ++ } ++ ++ ++ ++#define DECLARE_PQ_FUNCTIONS(table_name) \ ++ DECLARE_MDrv_PQ_LoadCommTable_(table_name) \ ++ DECLARE_MDrv_PQ_DumpTable_(table_name) \ ++ DECLARE_MDrv_PQ_GetIPNum_(table_name) \ ++ DECLARE_MDrv_PQ_GetTableNum_(table_name) \ ++ DECLARE_MDrv_PQ_GetTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetCurrentTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetTable_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTableData_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTable_(table_name) \ ++ DECLARE_MDrv_PQ_LoadCommTable_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTableBySrcType_(table_name) \ ++ DECLARE_MDrv_PQ_Set_CmdqCfg_(table_name) \ ++ DECLARE_MDrv_PQ_Check_Type_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTableByData_(table_name) \ ++ DECLARE_MDrv_PQ_CheckCommTable_(table_name) \ ++ DECLARE_MDrv_PQ_CheckTableBySrcType_(table_name) \ ++ DECLARE_MDrv_PQ_AddTable_(table_name) \ ++ DECLARE_MDrv_PQ_GetXRuleIPIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetXRuleTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetXRuleIPNum_(table_name) \ ++ DECLARE_MDrv_PQ_GetGRule_LevelIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetGRule_IPIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetGRule_TableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_Set_MLoadEn_(table_name) \ ++ DECLARE_MDrv_PQ_PreInitLoadTableInfo_(table_name) \ ++ DECLARE_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(table_name) \ ++ DECLARE_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(table_name) \ ++ DECLARE_MDrv_PQ_Set_LoadTableInfo_SrcType_(table_name) \ ++ DECLARE_MDrv_PQ_Get_LoadTableInfo_SrcType_(table_name) \ ++ DECLARE_MDrv_PQ_ClearTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_LoadPictureSetting_(table_name) ++ ++ ++#if PQ_ENABLE_UNUSED_FUNC ++#define INSTALL_PQ_FUNCTIONS(table_name) \ ++ INSTALL_MDrv_PQ_DumpTable_(table_name) \ ++ INSTALL_MDrv_PQ_GetIPNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetCurrentTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetTable_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableData_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTable_(table_name) \ ++ INSTALL_MDrv_PQ_LoadCommTable_(table_name) \ ++ INSTALL_MDrv_PQ_Set_CmdqCfg_(table_name) \ ++ INSTALL_MDrv_PQ_Check_Type_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableByData_(table_name) \ ++ INSTALL_MDrv_PQ_CheckCommTable_(table_name) \ ++ INSTALL_MDrv_PQ_CheckTableBySrcType_(table_name) \ ++ INSTALL_MDrv_PQ_AddTable_(table_name) \ ++ INSTALL_MDrv_PQ_GetXRuleIPIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetXRuleTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetXRuleIPNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetGRule_LevelIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetGRule_IPIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetGRule_TableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_PreInitLoadTableInfo_(table_name) \ ++ INSTALL_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(table_name) \ ++ INSTALL_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(table_name) \ ++ INSTALL_MDrv_PQ_Set_LoadTableInfo_SrcType_(table_name) \ ++ INSTALL_MDrv_PQ_Get_LoadTableInfo_SrcType_(table_name) \ ++ INSTALL_MDrv_PQ_ClearTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_LoadPictureSetting_(table_name) ++#else ++ ++#define INSTALL_PQ_FUNCTIONS(table_name) \ ++ INSTALL_MDrv_PQ_DumpTable_(table_name) \ ++ INSTALL_MDrv_PQ_GetIPNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetCurrentTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetTable_(table_name) \ ++ INSTALL_MDrv_PQ_Set_CmdqCfg_(table_name) \ ++ INSTALL_MDrv_PQ_Check_Type_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableByData_(table_name) \ ++ INSTALL_MDrv_PQ_AddTable_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableBySrcType_(table_name) \ ++ INSTALL_MDrv_PQ_ClearTableIndex_(table_name) ++#endif ++ ++// TODO: declare PQ functions for all tables in this file ++DECLARE_PQ_FUNCTIONS(MAIN) // table config parameter ++ ++ ++// SC ++#include "Infinity_Main.h" // table config parameter ++#include "Infinity_Main_HSPRule.h" // table config parameter ++#include "Infinity_Main_VSPRule.h" // table config parameter ++#include "Infinity_Main_GRule.h" // table config parameter ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/drvPQ_Define.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/drvPQ_Define.h +new file mode 100644 +index 00000000..4f7fd26c +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/drvPQ_Define.h +@@ -0,0 +1,532 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRVPQ_DEFINE_H_ ++#define _DRVPQ_DEFINE_H_ ++ ++#define PQ_ONLY_SUPPORT_BIN 0 ++#define PQ_ENABLE_DEBUG 0 ++#define PQ_ENABLE_CHECK 0 ++ ++#define ENABLE_PQ_CMDQ 1 ++#define ENABLE_PQ_BIN 0 ++#define ENABLE_PQ_MLOAD 0 ++#define ENABLE_PQ_EX 0 ++ ++#define ENABLE_MULTI_SCALER 0 ++ ++#define PQ_ENABLE_420UPSAMPLING 0 ++#define PQ_ENABLE_NONLINEAR_SCALING 0 ++#define PQ_ENABLE_SETFILM_MODE 0 ++#define PQ_ENABLE_MEMFMT 0 ++#define PQ_ENABLE_CSCRULE 0 ++#define PQ_ENABLE_HSDRULE 0 ++#define PQ_ENABLE_PICTURE 0 ++#define PQ_ENABLE_UNUSED_FUNC 0 ++ ++#define PQ_ENABLE_VD_SAMPLING 0 ++#define PQ_ENABLE_PIP 0 ++#define PQ_ENABLE_3D_VIDEO 1 ++#define PQ_ENABLE_IOCTL 1 ++#define PQ_ENABLE_COLOR 1 ++ ++//!! for SC1 PIP setting !!// ++#define PQ_ENABLE_PIP_SC1 0 ++ ++#define PQ_QM_CVBS 0 ++#define PQ_QM_YPBPR 0 ++#define PQ_QM_PC 0 ++#define PQ_QM_HMDI 0 ++#define PQ_QM_HDMI_PC 0 ++#define PQ_QM_DTV 0 ++#define PQ_QM_MM_VIDEO 0 ++#define PQ_QM_MM_PHOTO 0 ++#define PQ_QM_ISP 1 ++#define PQ_QM_3D 0 ++#define PQ_EX_ENABLE 0 ++#define PQ_SKIPRULE_ENABLE 1 ++ ++#define PQ_GRULE_NR_ENABLE 0 ++#define PQ_GRULE_MPEG_NR_ENABLE 0 ++#define PQ_GRULE_DDR_SELECT_ENABLE 0 ++#define PQ_GRULE_OSD_BW_ENABLE 0 ++#define PQ_GRULE_FILM_MODE_ENABLE 0 ++#define PQ_GRULE_DYNAMIC_CONTRAST_ENABLE 0 ++#define PQ_GRULE_ULTRAT_CLEAR_ENABLE 0 ++#define PQ_GRULE_PTP_ENABLE 0 ++#define PQ_XRULE_DB_ENABLE 0 ++ ++#define ESTIMATE_AVAILABLE_RATE 85 ++#define PQ_ENABLE_FORCE_MADI 0 ++#define PQ_NEW_HSD_SAMPLING_TYPE 0 ++#define PQ_BW_H264_ENABLE 0 ++#define PQ_BW_MM_ENABLE 0 ++#define PQ_MADI_88X_MODE 0 ++#define PQ_UC_CTL 0 ++#define PQ_MADI_DFK 0 ++#define PQ_VIP_CTL 0 ++#define PQ_VIP_RGBCMY_CTL 0 ++ ++ ++#define PQ_EN_DMS_SW_CTRL FALSE ++#define PQ_ENABLE_RFBL FALSE ++#define PQ_EN_UCNR_OFF FALSE ++ ++#define MAIN_WINDOW 0 ++#define SUB_WINDOW 1 ++ ++extern MS_S32 _PQ_Mutex ; ++ ++#if defined (MSOS_TYPE_LINUX) ++extern pthread_mutex_t _PQ_MLoad_Mutex; ++#endif ++ ++#if PQ_ENABLE_DEBUG ++extern MS_BOOL _u16DbgSwitch; ++#define PQ_DBG(x) \ ++do{ \ ++ if (_u16DbgSwitch){ \ ++ x; \ ++ } \ ++}while(0) ++ ++#define PQ_DUMP_DBG(x) x ++#define PQ_DUMP_FILTER_DBG(x) x ++#else ++#define PQ_ERR(x) x ++#define PQ_DBG(x) ++#define PQ_DUMP_DBG(x) //x ++#define PQ_DUMP_FILTER_DBG(x) //x ++#endif ++ ++#define PQ_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF) ++#define REG_ADDR_SIZE 2 ++#define REG_MASK_SIZE 1 ++ ++#define PQ_IP_NULL 0xFF ++ ++#define PQTBL_EX 0x10 ++#define PQTBL_NORMAL 0x11 ++ ++#define E_XRULE_HSD 0 ++#define E_XRULE_VSD 1 ++#define E_XRULE_HSP 2 ++#define E_XRULE_VSP 3 ++#define E_XRULE_CSC 4 ++ ++#if PQ_XRULE_DB_ENABLE ++#define E_XRULE_DB_NTSC 5 ++#define E_XRULE_DB_PAL 6 ++#define E_XRULE_NUM 7 ++#else ++#define E_XRULE_NUM 5 ++#endif ++ ++//Here must be the same order as MST_GRule_Index_Main ++typedef enum { ++ E_GRULE_NR, ++#if(PQ_GRULE_OSD_BW_ENABLE == 1) ++ E_GRULE_OSD_BW, ++#endif ++#if(PQ_GRULE_MPEG_NR_ENABLE == 1) ++ E_GRULE_MPEG_NR, ++#endif ++#if(PQ_GRULE_FILM_MODE_ENABLE == 1) ++ E_GRULE_FilmMode, ++#endif ++#if(PQ_GRULE_DYNAMIC_CONTRAST_ENABLE == 1) ++ E_GRULE_DynContr, ++#endif ++#if(PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ E_GRULE_DDR_SELECT, ++#endif ++#if(PQ_GRULE_ULTRAT_CLEAR_ENABLE == 1) ++ E_GRULE_ULTRACLEAR, ++#endif ++#if(PQ_GRULE_PTP_ENABLE == 1) ++ E_GRULE_PTP, ++#endif ++ E_GRULE_NUM, ++} EN_GRULE_INDEX; ++ ++ ++#define _END_OF_TBL_ 0xFFFF ++ ++ ++typedef enum { ++ PQ_TABTYPE_GENERAL, ++ PQ_TABTYPE_COMB, ++ PQ_TABTYPE_SCALER, ++ PQ_TABTYPE_SRAM1, ++ PQ_TABTYPE_SRAM2, ++ PQ_TABTYPE_SRAM3, ++ PQ_TABTYPE_SRAM4, ++ PQ_TABTYPE_C_SRAM1, ++ PQ_TABTYPE_C_SRAM2, ++ PQ_TABTYPE_C_SRAM3, ++ PQ_TABTYPE_C_SRAM4, ++ PQ_TABTYPE_SRAM_COLOR_INDEX, ++ PQ_TABTYPE_SRAM_COLOR_GAIN_SNR, ++ PQ_TABTYPE_SRAM_COLOR_GAIN_DNR, ++ PQ_TABTYPE_VIP_IHC_CRD_SRAM, ++ PQ_TABTYPE_VIP_ICC_CRD_SRAM, ++ PQ_TABTYPE_XVYCC_DE_GAMMA_SRAM, ++ PQ_TABTYPE_XVYCC_GAMMA_SRAM, ++ PQ_TABTYPE_SWDRIVER, ++ PQ_TABTYPE_PICTURE_1, ++ PQ_TABTYPE_PICTURE_2, ++ ++} EN_PQ_TABTYPE; ++ ++ ++typedef enum ++{ ++ PQ_MD_720x480_60I, // 00 ++ PQ_MD_720x480_60P, // 01 ++ PQ_MD_720x576_50I, // 02 ++ PQ_MD_720x576_50P, // 03 ++ PQ_MD_1280x720_50P, // 04 ++ PQ_MD_1280x720_60P, // 05 ++ PQ_MD_1920x1080_50I, // 06 ++ PQ_MD_1920x1080_60I, // 07 ++ PQ_MD_1920x1080_24P, // 08 ++ PQ_MD_1920x1080_25P, // 09 ++ PQ_MD_1920x1080_30P, // 10 ++ PQ_MD_1920x1080_50P, // 11 ++ PQ_MD_1920x1080_60P, // 12 ++ PQ_MD_Num, ++}PQ_MODE_INDEX; ++ ++typedef enum ++{ ++ PQ_CHECK_OFF = 0, // reset before test ++ PQ_CHECK_REG = 1, // test register mode ++ PQ_CHECK_SIZE = 2, // test size mode ++ PQ_CHECK_NUM, ++}PQ_CHECK_TYPE; ++ ++typedef struct ++{ ++ MS_U8 *pIPCommTable; ++ MS_U8 *pIPTable; ++ MS_U8 u8TabNums; ++ MS_U8 u8TabType; ++} EN_IPTAB_INFO; ++ ++typedef struct ++{ ++ MS_U8 *pIPTable; ++ MS_U8 u8TabNums; ++ MS_U8 u8TabType; ++ MS_U8 u8TabIdx; ++} EN_IP_Info; ++ ++ ++enum ++{ ++ PQ_FUNC_DUMP_REG, ++ PQ_FUNC_CHK_REG, ++}; ++ ++#define PQ_MUX_DEBUG 0 ++ ++#define SCALER_REGISTER_SPREAD 1 ++ ++#if(SCALER_REGISTER_SPREAD) ++ #define BK_SCALER_BASE 0x120000 ++ ++ // no need to store bank for spread reg ++ #define SC_BK_STORE_NOMUTEX ++ ++ #define SC_BK_RESTORE_NOMUTEX ++ ++ ++ #if(PQ_MUX_DEBUG) ++ // no need to store bank for spread reg ++ #define SC_BK_STORE_MUTEX \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ printf("==========================\n"); \ ++ printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ ++ } ++ ++ // restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++ #else ++ #define SC_BK_STORE_MUTEX \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ } ++ ++ // restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++ #endif ++ ++ ++ ++ // switch bank ++ #define SC_BK_SWITCH(_x_) ++ ++ #define SC_BK_CURRENT (u8CurBank) ++#else ++ #define BK_SCALER_BASE 0x102F00 ++ ++ #define SC_BK_STORE_NOMUTEX \ ++ MS_U8 u8Bank; \ ++ u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) ++ ++ // restore bank ++ #define SC_BK_RESTORE_NOMUTEX MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); ++ ++#if(PQ_MUX_DEBUG) ++// store bank ++ #define SC_BK_STORE_MUTEX \ ++ MS_U8 u8Bank; \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ printf("==========================\n"); \ ++ printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ ++ } \ ++ u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) ++ ++// restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++#else ++ #define SC_BK_STORE_MUTEX \ ++ MS_U8 u8Bank; \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ } \ ++ u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) ++ ++// restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++#endif ++ ++// switch bank ++#define SC_BK_SWITCH(_x_)\ ++ MApi_XC_WriteByte(BK_SCALER_BASE, _x_) ++ ++#define SC_BK_CURRENT \ ++ MApi_XC_ReadByte(BK_SCALER_BASE) ++#endif ++ ++ ++ ++// store bank ++#define COMB_BK_STORE \ ++ MS_U8 u8Bank; \ ++ u8Bank = MApi_XC_ReadByte(COMB_REG_BASE) ++ ++// restore bank ++#define COMB_BK_RESTORE \ ++ MApi_XC_WriteByte(COMB_REG_BASE, u8Bank) ++// switch bank ++#define COMB_BK_SWITCH(_x_)\ ++ MApi_XC_WriteByte(COMB_REG_BASE, _x_) ++ ++#define COMB_BK_CURRENT \ ++ MApi_XC_ReadByte(COMB_REG_BASE) ++ ++ ++ ++#define PQ_IP_COMM 0xfe ++#define PQ_IP_ALL 0xff ++ ++ ++typedef enum ++{ ++ /// Main window ++ PQ_MAIN_WINDOW=0, ++ ++ /// The max support window of PQ ++ PQ_MAX_WINDOW ++}PQ_WIN; ++ ++ ++typedef struct { ++ PQ_WIN eWin; ++ MS_U8 u8PQ_InputType_Num; ++ MS_U8 u8PQ_IP_Num; ++ MS_U8 *pQuality_Map_Aray; ++ EN_IPTAB_INFO *pIPTAB_Info; ++ MS_U8 *pSkipRuleIP; ++ ++ MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM]; ++ MS_U8 *pXRule_IP_Index[E_XRULE_NUM]; ++ MS_U8 *pXRule_Array[E_XRULE_NUM]; ++ ++ MS_U8 u8PQ_GRule_Num[E_GRULE_NUM]; ++ MS_U8 u8PQ_GRule_IPNum[E_GRULE_NUM]; ++ MS_U8 u8PQ_GRule_LevelNum[E_GRULE_NUM]; ++ MS_U8 *pGRule_IP_Index[E_GRULE_NUM]; ++ MS_U8 *pGRule_Array[E_GRULE_NUM]; ++ MS_U8 *pGRule_Level[E_GRULE_NUM]; ++} PQTABLE_INFO; ++ ++/** ++ * FOURCE COLOR FMT ++ */ ++typedef enum ++{ ++ /// Default ++ PQ_FOURCE_COLOR_DEFAULT, ++ /// RGB ++ PQ_FOURCE_COLOR_RGB, ++ /// YUV ++ PQ_FOURCE_COLOR_YUV, ++}PQ_FOURCE_COLOR_FMT; ++ ++/** ++ * PQ DEINTERLACE MODE ++ */ ++typedef enum ++{ ++ /// off ++ PQ_DEINT_OFF=0, ++ /// 2DDI BOB ++ PQ_DEINT_2DDI_BOB, ++ /// 2DDI AVG ++ PQ_DEINT_2DDI_AVG, ++ /// 3DDI History(24 bit) ++ PQ_DEINT_3DDI_HISTORY, ++ /// 3DDI(16 bit) ++ PQ_DEINT_3DDI, ++} PQ_DEINTERLACE_MODE; ++/** ++ * Video data information to supply when in PQ mode. ++ */ ++typedef struct ++{ ++ /// is FBL or not ++ MS_BOOL bFBL; ++ /// is interlace mode or not ++ MS_BOOL bInterlace; ++ /// input Horizontal size ++ MS_U16 u16input_hsize; ++ /// input Vertical size ++ MS_U16 u16input_vsize; ++ /// input Vertical total ++ MS_U16 u16input_vtotal; ++ /// input Vertical frequency ++ MS_U16 u16input_vfreq; ++ /// output Vertical frequency ++ MS_U16 u16ouput_vfreq; ++ /// Display Horizontal size ++ MS_U16 u16display_hsize; ++ /// Display Vertical size ++ MS_U16 u16display_vsize; ++}MS_PQ_Mode_Info; ++ ++/** ++ * INPUT SOURCE TYPE ++ */ ++typedef enum ++{ ++ /// VGA ++ PQ_INPUT_SOURCE_VGA, ++ /// TV ++ PQ_INPUT_SOURCE_TV, ++ ++ /// CVBS ++ PQ_INPUT_SOURCE_CVBS, ++ ++ /// S-video ++ PQ_INPUT_SOURCE_SVIDEO, ++ ++ /// Component ++ PQ_INPUT_SOURCE_YPBPR, ++ /// Scart ++ PQ_INPUT_SOURCE_SCART, ++ ++ ++ /// HDMI ++ PQ_INPUT_SOURCE_HDMI, ++ ++ /// DTV ++ PQ_INPUT_SOURCE_DTV, ++ ++ /// DVI ++ PQ_INPUT_SOURCE_DVI, ++ ++ // Application source ++ /// Storage ++ PQ_INPUT_SOURCE_STORAGE, ++ /// KTV ++ PQ_INPUT_SOURCE_KTV, ++ /// JPEG ++ PQ_INPUT_SOURCE_JPEG, ++ ++ // BT656 ++ PQ_INPUT_SOURCE_BT656, ++ ++ // ISP ++ PQ_INPUT_SOURCE_ISP, ++ ++ /// The max support number of PQ input source ++ PQ_INPUT_SOURCE_NUM, ++ /// None ++ PQ_INPUT_SOURCE_NONE = PQ_INPUT_SOURCE_NUM, ++} PQ_INPUT_SOURCE_TYPE; ++ ++ ++// PQ Function ++typedef enum ++{ ++ E_PQ_IOCTL_NONE = 0x00000000, ++ E_PQ_IOCTL_HSD_SAMPLING = 0x00000001, ++ E_PQ_IOCTL_PREVSD_BILINEAR = 0x00000002, ++ E_PQ_IOCTL_ADC_SAMPLING = 0x00000003, ++ E_PQ_IOCTL_RFBL_CTRL = 0x00000004, ++ ++ E_PQ_IOCTL_NUM, ++}PQ_IOCTL_FLAG_TYPE; ++ ++ ++typedef struct ++{ ++ MS_U32 u32ratio; ++ MS_BOOL bADVMode; ++}PQ_HSD_SAMPLING_INFO; ++ ++typedef struct ++{ ++ PQ_INPUT_SOURCE_TYPE enPQSourceType; ++ MS_PQ_Mode_Info stPQModeInfo; ++ MS_U16 u16ratio; ++}PQ_ADC_SAMPLING_INFO; ++ ++typedef struct ++{ ++ MS_U8 *pBuf; ++ MS_U16 u16BufSize; ++}PQ_DATA_INFO; ++ ++typedef struct ++{ ++ MS_BOOL bEnFmCnt; ++ MS_U8 u8FmCnt; ++ MS_BOOL bfire; ++}PQ_CMDQ_CONFIG; ++ ++#endif /* _DRVPQ_DEFINE_H_ */ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/hwreg_pq.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/hwreg_pq.h +new file mode 100644 +index 00000000..5a8129cd +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/hwreg_pq.h +@@ -0,0 +1,20 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#define REG_SCALER_BASE 0x130000 ++#define COMB_REG_BASE 0x103600 ++#define NON_PM_BASE 0x100000 +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/mhal_pq.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/mhal_pq.h +new file mode 100644 +index 00000000..b37d7c82 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/mhal_pq.h +@@ -0,0 +1,103 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef MHAL_PQ_H ++#define MHAL_PQ_H ++ ++#define MEMFMT24BIT_YC10BIT_MOT 0xBB ++#define MEMFMT24BIT_YC8BIT_MOT 0xAA ++#define MEMFMT24BIT_YC10BIT 0x99 ++#define MEMFMT24BIT_YC8BIT 0x88 ++#define MEMFMT24BIT_CLEAR 0x00 ++ ++#define SC_FILTER_Y_SRAM1 0x00 ++#define SC_FILTER_Y_SRAM2 0x01 ++#define SC_FILTER_Y_SRAM3 0x02 ++#define SC_FILTER_Y_SRAM4 0x03 ++#define SC_FILTER_C_SRAM1 0x04 ++#define SC_FILTER_C_SRAM2 0x05 ++#define SC_FILTER_C_SRAM3 0x06 ++#define SC_FILTER_C_SRAM4 0x07 ++#define SC_FILTER_SRAM_COLOR_INDEX 0x08 ++#define SC_FILTER_SRAM_COLOR_GAIN_SNR 0x09 ++#define SC_FILTER_SRAM_COLOR_GAIN_DNR 0x0A ++#define SC_FILTER_SRAM_ICC_CRD 0x0B ++#define SC_FILTER_SRAM_IHC_CRD 0x0C ++#define SC_FILTER_SRAM_XVYCC_DE_GAMMA 0x0D ++#define SC_FILTER_SRAM_XVYCC_GAMMA 0x0E ++ ++#define FILTER_SRAM_SC1 0x00 ++#define FILTER_SRAM_SC2 0x01 ++#define FILTER_SRAM_SC3 0x02 ++ ++ ++ ++#define SUPPORT_SCMI_V2 TRUE ++#define SUPPORT_DYNAMIC_MEM_FMT TRUE ++ ++void Hal_PQ_init_riu_base(MS_U32 u32riu_base); ++MS_U8 Hal_PQ_get_sync_flag(PQ_WIN ePQWin); ++MS_U8 Hal_PQ_get_input_vsync_value(PQ_WIN ePQWin); ++MS_U8 Hal_PQ_get_output_vsync_value(PQ_WIN ePQWin); ++MS_U8 Hal_PQ_get_input_vsync_polarity(PQ_WIN ePQWin); ++void Hal_PQ_set_memfmt_doublebuffer(PQ_WIN ePQWin, MS_BOOL bEn); ++void Hal_PQ_set_sourceidx(PQ_WIN ePQWin, MS_U16 u16Idx); ++void Hal_PQ_set_mem_fmt(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask); ++void Hal_PQ_set_mem_fmt_en(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask); ++void Hal_PQ_set_420upSample(PQ_WIN ePQWin, MS_U16 u16value); ++void Hal_PQ_set_force_y_motion(PQ_WIN ePQWin, MS_U16 u16value); ++MS_U8 Hal_PQ_get_force_y_motion(PQ_WIN ePQWin); ++void Hal_PQ_set_force_c_motion(PQ_WIN ePQWin, MS_U16 u16value); ++MS_U8 Hal_PQ_get_force_c_motion(PQ_WIN ePQWin); ++void Hal_PQ_set_dipf_temporal(PQ_WIN ePQWin, MS_U16 u16val); ++MS_U16 Hal_PQ_get_dipf_temporal(PQ_WIN ePQWin); ++void Hal_PQ_set_dipf_spatial(PQ_WIN ePQWin, MS_U16 u16val); ++MS_U8 Hal_PQ_get_dipf_spatial(PQ_WIN ePQWin); ++void Hal_PQ_set_vsp_sram_filter(PQ_WIN ePQWin, MS_U8 u8vale); ++MS_U8 Hal_PQ_get_vsp_sram_filter(PQ_WIN ePQWin); ++void Hal_PQ_set_dnr(PQ_WIN ePQWin, MS_U8 u8val); ++MS_U8 Hal_PQ_get_dnr(PQ_WIN ePQWin); ++void Hal_PQ_set_presnr(PQ_WIN ePQWin, MS_U8 u8val); ++MS_U8 Hal_PQ_get_presnr(PQ_WIN ePQWin); ++void Hal_PQ_set_film(PQ_WIN ePQWin, MS_U16 u16val); ++MS_U8 Hal_PQ_get_film(PQ_WIN ePQWin); ++void Hal_PQ_set_yc_sram(MS_U8 enID, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_color_index_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_color_gain_snr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_color_gain_dnr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++MS_U16 Hal_PQ_get_420_cup_idx(MS_420_CUP_TYPE etype); ++MS_U16 Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_TYPE etype); ++MS_U16 Hal_PQ_get_422To444_idx(MS_422To444_TYPE etype); ++MS_U8 Hal_PQ_get_422To444_mode(MS_BOOL bMemFmt422); ++MS_U8 Hal_PQ_get_madi_fbl_mode(MS_BOOL bMemFmt422,MS_BOOL bInterlace); ++MS_U16 Hal_PQ_get_csc_ip_idx(MS_CSC_IP_TYPE enCSC); ++MS_U8 Hal_PQ_get_madi_fbl_mode(MS_BOOL bMemFmt422,MS_BOOL bInterlace); ++MS_U16 Hal_PQ_get_csc_ip_idx(MS_CSC_IP_TYPE enCSC); ++MS_U16 Hal_PQ_get_madi_idx(PQ_WIN ePQWin, MS_MADI_TYPE etype); ++MS_U16 Hal_PQ_get_sram_size(MS_U16 u16sramtype); ++MS_U16 Hal_PQ_get_ip_idx(MS_PQ_IP_TYPE eType); ++MS_U16 Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_TYPE eType); ++void Hal_PQ_OPWriteOff_Enable(MS_BOOL bEna); ++MS_U16 Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_TYPE eType); ++void Hal_PQ_set_sram_ihc_crd_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_icc_crd_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++MS_U16 Hal_PQ_get_rw_method(PQ_WIN ePQWin); ++void Hal_PQ_set_rw_method(PQ_WIN ePQWin, MS_U16 u16method); ++MS_BOOL HAL_PQ_user_mode_control(void); ++void HAL_PQ_set_SelectCSC(MS_U16 u16selection, PQ_WIN ePQWin); ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main.c +new file mode 100644 +index 00000000..289851ee +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main.c +@@ -0,0 +1,8213 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (; MStar; Confidential; Information; ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//**************************************************** ++// Quality Map CodeGen Version 4.0 ++// 1920 ++// Infinity ++// 8/12/2016 4:59:11 PM ++// 39630.43853 ++//**************************************************** ++ ++#ifndef _INFINITY_MAIN_C_ ++#define _INFINITY_MAIN_C_ ++ ++#if PQ_SKIPRULE_ENABLE ++ ++ unsigned char MST_SkipRule_IP_Main[PQ_IP_NUM_Main]= ++{ ++ /* PreSNR */ 0, /* DNR */ 0, /* DNR_Y */ 0, /* DNR_C */ 0, ++ /* LDC */ 0, /* LDC_422_444_422 */ 0, /* NLM */ 0, /* 422to444 */ 0, ++ /* VIP */ 1, /* VIP_pseudo */ 0, /* VIP_LineBuffer */ 0, /* VIP_HLPF */ 0, ++ /* VIP_HLPF_dither */ 0, /* VIP_VLPF_coef1 */ 0, /* VIP_VLPF_coef2 */ 0, /* VIP_VLPF_dither */ 0, ++ /* VIP_Peaking */ 0, /* VIP_Peaking_band */ 0, /* VIP_Peaking_adptive */ 0, /* VIP_Peaking_Pcoring */ 0, ++ /* VIP_Peaking_Pcoring_ad_Y */ 0, /* VIP_Peaking_gain */ 0, /* VIP_Peaking_gain_ad_Y */ 0, /* VIP_LCE */ 0, ++ /* VIP_LCE_dither */ 0, /* VIP_LCE_setting */ 0, /* VIP_LCE_curve */ 0, /* VIP_DLC_His_range */ 1, ++ /* VIP_DLC */ 0, /* VIP_DLC_dither */ 0, /* VIP_DLC_His_rangeH */ 1, /* VIP_DLC_His_rangeV */ 1, ++ /* VIP_DLC_PC */ 0, /* VIP_YC_gain_offset */ 0, /* VIP_UVC */ 0, /* VIP_FCC_full_range */ 0, ++ /* VIP_FCC_bdry_dist */ 0, /* VIP_FCC_T1 */ 0, /* VIP_FCC_T2 */ 0, /* VIP_FCC_T3 */ 0, ++ /* VIP_FCC_T4 */ 0, /* VIP_FCC_T5 */ 0, /* VIP_FCC_T6 */ 0, /* VIP_FCC_T7 */ 0, ++ /* VIP_FCC_T8 */ 0, /* VIP_FCC_T9 */ 0, /* VIP_IHC */ 0, /* VIP_IHC_Ymode */ 0, ++ /* VIP_IHC_dither */ 0, /* VIP_IHC_CRD_SRAM */ 0, /* VIP_IHC_SETTING */ 0, /* VIP_ICC */ 0, ++ /* VIP_ICC_Ymode */ 0, /* VIP_ICC_dither */ 0, /* VIP_ICC_CRD_SRAM */ 0, /* VIP_ICC_SETTING */ 0, ++ /* VIP_Ymode_Yvalue_ALL */ 0, /* VIP_Ymode_Yvalue_SETTING */ 0, /* VIP_IBC */ 0, /* VIP_IBC_dither */ 0, ++ /* VIP_IBC_SETTING */ 0, /* VIP_ACK */ 0, /* VIP_YCbCr_Clip */ 0, /* VSP_Y_SC1 */ 1, ++ /* VSP_C_SC1 */ 1, /* VSP_CoRing_SC1 */ 0, /* VSP_DeRing_SC1 */ 0, /* VSP_Dither_SC1 */ 0, ++ /* VSP_PreVBound_SC1 */ 0, /* AntiPAL_filter_SC1 */ 0, /* 422To444_SC1 */ 0, /* HSP_Y_SC1 */ 1, ++ /* HSP_C_SC1 */ 1, /* HSP_CoRing_SC1 */ 0, /* HSP_DeRing_SC1 */ 0, /* HSP_Dither_SC1 */ 0, ++ /* HnonLinear_SC1 */ 1, /* SRAM1 */ 0, /* SRAM2 */ 0, /* SRAM3 */ 0, ++ /* SRAM4 */ 0, /* C_SRAM1 */ 0, /* C_SRAM2 */ 0, /* C_SRAM3 */ 0, ++ /* C_SRAM4 */ 0, /* VSP_Y_SC2 */ 1, /* VSP_C_SC2 */ 1, /* VSP_CoRing_SC2 */ 0, ++ /* VSP_DeRing_SC2 */ 0, /* VSP_Dither_SC2 */ 0, /* VSP_PreVBound_SC2 */ 0, /* AntiPAL_filter_SC2 */ 0, ++ /* 422To444_SC2 */ 0, /* HSP_Y_SC2 */ 1, /* HSP_C_SC2 */ 1, /* HSP_CoRing_SC2 */ 0, ++ /* HSP_DeRing_SC2 */ 0, /* HSP_Dither_SC2 */ 0, /* HnonLinear_SC2 */ 1, /* VSP_Y_SC3 */ 1, ++ /* VSP_C_SC3 */ 1, /* VSP_CoRing_SC3 */ 0, /* VSP_DeRing_SC3 */ 0, /* VSP_Dither_SC3 */ 0, ++ /* VSP_PreVBound_SC3 */ 0, /* AntiPAL_filter_SC3 */ 0, /* 422To444_SC3 */ 0, /* HSP_Y_SC3 */ 1, ++ /* HSP_C_SC3 */ 1, /* HSP_CoRing_SC3 */ 0, /* HSP_DeRing_SC3 */ 0, /* HSP_Dither_SC3 */ 0, ++ /* HnonLinear_SC3 */ 1, /* SWDriver */ 0, /* SC_End */ 0, ++}; ++ ++#endif ++//**************************************************** ++// PreSNR ++//**************************************************** ++ unsigned char MST_PreSNR_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_PreSNR_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_PreSNR_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK16_22_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_22_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_2B_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_58_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_58_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_59_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_59_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_5A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_5A_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_5B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_5B_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// DNR ++//**************************************************** ++ unsigned char MST_DNR_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_DNR_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_DNR_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK16_21_L), 0x01, 0x00/*NR_OFF*/, ++ 0x01/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_21_L), 0x02, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK22_30_L), 0x01, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK22_30_L), 0x02, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_28_L), 0x01, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_28_L), 0x02, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_28_L), 0x10, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_28_H), 0x1F, 0x00/*NR_OFF*/, ++ 0x00/*DNR_OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// DNR_Y ++//**************************************************** ++ unsigned char MST_DNR_Y_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_DNR_Y_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_DNR_Y_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK16_21_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_26_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_26_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_27_L), 0x1C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_27_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_27_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_40_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_40_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_41_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_41_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_42_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_42_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_43_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_43_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_25_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// DNR_C ++//**************************************************** ++ unsigned char MST_DNR_C_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_DNR_C_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_DNR_C_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK16_21_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_26_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_26_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_27_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_27_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_27_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_44_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_44_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_45_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_45_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_46_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_46_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_47_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_47_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK16_25_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// LDC ++//**************************************************** ++ unsigned char MST_LDC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_LDC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_LDC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK18_03_H), 0x10, 0x00/*OFF*/, ++ 0x10/*ON*/, }, ++ { PQ_MAP_REG(REG_SC_BK24_00_L), 0x01, 0x00/*OFF*/, ++ 0x01/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// LDC_422_444_422 ++//**************************************************** ++ unsigned char MST_LDC_422_444_422_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_LDC_422_444_422_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_LDC_422_444_422_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK24_1F_L), 0x03, 0x02/*md1434_avg*/, }, ++ { PQ_MAP_REG(REG_SC_BK24_1F_L), 0x1C, 0x10/*md1434_avg*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// NLM ++//**************************************************** ++ unsigned char MST_NLM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_NLM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_NLM_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK17_01_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_L), 0x02, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_L), 0x04, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x04, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x08, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_02_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_03_L), 0x0F, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_03_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_04_L), 0x3F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_04_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_04_H), 0x60, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_20_H), 0x3F, 0x1C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_20_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_21_H), 0x3F, 0x18/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_21_L), 0x3F, 0x15/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_22_H), 0x3F, 0x12/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_22_L), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_23_H), 0x3F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_23_L), 0x3F, 0x0C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_24_H), 0x3F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_24_L), 0x3F, 0x09/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_25_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_25_L), 0x3F, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_26_H), 0x3F, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_26_L), 0x3F, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_27_H), 0x3F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_27_L), 0x3F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_28_H), 0x3F, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_28_L), 0x3F, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_29_H), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_29_L), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2A_H), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2A_L), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2B_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2B_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2C_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2C_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2D_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2D_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2E_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2E_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_30_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_30_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_31_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_31_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_32_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_32_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_33_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_33_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_34_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_34_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_35_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_35_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_36_H), 0x1F, 0x0C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_36_L), 0x1F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_37_H), 0x1F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_37_L), 0x1F, 0x0D/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_38_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_38_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_39_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_39_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3A_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3A_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3B_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3B_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3C_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3C_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3D_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3D_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3E_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3E_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3F_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3F_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_40_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_40_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_41_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_41_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_42_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_42_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_43_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_43_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_44_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_44_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_45_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_45_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_46_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_46_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_47_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_47_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_48_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_48_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_49_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_49_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4A_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4A_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4B_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4B_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4C_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4C_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4D_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4D_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4E_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4E_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4F_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4F_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_50_H), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_50_L), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_51_H), 0x3F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_51_L), 0x3F, 0x0F/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_52_H), 0x3F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_52_L), 0x3F, 0x0C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_53_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_53_L), 0x3F, 0x09/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_54_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_54_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_55_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_55_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_56_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_56_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_57_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_57_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_58_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_58_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_59_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_59_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5A_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5A_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5B_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5B_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5C_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422to444 ++//**************************************************** ++ unsigned char MST_422to444_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422to444_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422to444_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_72_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_72_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP ++//**************************************************** ++ unsigned char MST_VIP_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_70_L), 0x01, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_pseudo ++//**************************************************** ++ unsigned char MST_VIP_pseudo_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_pseudo_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_pseudo_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_78_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_78_L), 0x06, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LineBuffer ++//**************************************************** ++ unsigned char MST_VIP_LineBuffer_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LineBuffer_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LineBuffer_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_HLPF ++//**************************************************** ++ unsigned char MST_VIP_HLPF_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_HLPF_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_HLPF_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x70, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_HLPF_dither ++//**************************************************** ++ unsigned char MST_VIP_HLPF_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_HLPF_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_HLPF_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_VLPF_coef1 ++//**************************************************** ++ unsigned char MST_VIP_VLPF_coef1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_VLPF_coef1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_VLPF_coef1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_12_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_VLPF_coef2 ++//**************************************************** ++ unsigned char MST_VIP_VLPF_coef2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_VLPF_coef2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_VLPF_coef2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_12_H), 0x70, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_VLPF_dither ++//**************************************************** ++ unsigned char MST_VIP_VLPF_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_VLPF_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_VLPF_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking ++//**************************************************** ++ unsigned char MST_VIP_Peaking_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x01, 0x00/*OFF*/, ++ 0x01/*W2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x80, 0x80/*OFF*/, ++ 0x80/*W2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_0B_H), 0x40, 0x00/*OFF*/, ++ 0x40/*W2*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_band ++//**************************************************** ++ unsigned char MST_VIP_Peaking_band_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_band_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_band_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_18_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_18_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_19_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_19_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1A_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1A_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1B_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1B_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_20_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_20_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_21_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_21_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_22_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_22_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_23_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_23_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_24_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_24_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_25_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_25_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_26_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_26_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_27_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_27_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_38_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_adptive ++//**************************************************** ++ unsigned char MST_VIP_Peaking_adptive_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_adptive_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_adptive_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_40_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_40_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_41_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_41_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_42_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_42_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_43_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_43_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_44_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_44_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_45_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_45_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_46_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_46_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_47_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_47_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_48_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_48_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_49_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_49_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_68_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_68_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_69_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_69_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_Pcoring ++//**************************************************** ++ unsigned char MST_VIP_Peaking_Pcoring_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_Pcoring_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_Pcoring_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_13_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_13_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_30_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_Pcoring_ad_Y ++//**************************************************** ++ unsigned char MST_VIP_Peaking_Pcoring_ad_Y_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_Pcoring_ad_Y_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_Pcoring_ad_Y_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_70_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_70_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_70_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_70_L), 0x30, 0x30/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_71_L), 0x3F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_71_H), 0x3F, 0x50/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_72_L), 0x3F, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_72_H), 0x3F, 0x70/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_73_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_73_H), 0x3F, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_74_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_74_H), 0x3F, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_gain ++//**************************************************** ++ unsigned char MST_VIP_Peaking_gain_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_gain_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_gain_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_13_H), 0x7F, 0x10/*0x10*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_3E_L), 0x80, 0x00/*0x10*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_3E_L), 0x7F, 0x00/*0x10*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_3E_H), 0x7F, 0x00/*0x10*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_gain_ad_Y ++//**************************************************** ++ unsigned char MST_VIP_Peaking_gain_ad_Y_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_gain_ad_Y_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_gain_ad_Y_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_55_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_55_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_55_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_55_L), 0x30, 0x30/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_L), 0x0F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_L), 0xF0, 0x50/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_H), 0x0F, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_H), 0xF0, 0x70/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_L), 0x0F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_L), 0xF0, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_H), 0x0F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_H), 0xF0, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_YC_gain_offset ++//**************************************************** ++ unsigned char MST_VIP_YC_gain_offset_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_YC_gain_offset_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_YC_gain_offset_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_38_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_38_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_39_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_39_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3A_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3B_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3C_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3D_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3E_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3F_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3F_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE ++//**************************************************** ++ unsigned char MST_VIP_LCE_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE_dither ++//**************************************************** ++ unsigned char MST_VIP_LCE_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE_setting ++//**************************************************** ++ unsigned char MST_VIP_LCE_setting_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_setting_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_setting_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x02, 0x02/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x04, 0x04/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x10, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x40, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_H), 0x0F, 0x0B/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_H), 0xF0, 0x80/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_11_L), 0xFF, 0x02/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_11_H), 0xFF, 0x38/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_12_L), 0x7F, 0x3F/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_12_H), 0xFF, 0x50/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_13_L), 0x3F, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_13_H), 0xFF, 0x10/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_14_L), 0x0F, 0x04/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_14_H), 0x3F, 0x10/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_19_L), 0xFF, 0x40/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_1A_L), 0x3F, 0x10/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_1A_H), 0x0F, 0x08/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_1B_L), 0x1F, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE_curve ++//**************************************************** ++ unsigned char MST_VIP_LCE_curve_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_curve_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_curve_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_17_L), 0xFF, 0x08/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_17_H), 0xFF, 0x40/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_18_L), 0xFF, 0x96/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_18_H), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_30_L), 0xFF, 0x0A/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_30_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_31_L), 0xFF, 0x1B/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_31_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_32_L), 0xFF, 0x29/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_32_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_33_L), 0xFF, 0x35/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_33_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_34_L), 0xFF, 0x44/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_34_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_35_L), 0xFF, 0x56/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_35_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_36_L), 0xFF, 0x67/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_36_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_37_L), 0xFF, 0x78/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_37_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_38_L), 0xFF, 0x89/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_38_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_39_L), 0xFF, 0x99/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_39_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3A_L), 0xFF, 0xA8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3A_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3B_L), 0xFF, 0xB6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3B_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3C_L), 0xFF, 0xC5/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3C_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3D_L), 0xFF, 0xD6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3D_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3E_L), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3E_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3F_L), 0xFF, 0xF8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3F_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_40_L), 0xFF, 0x0A/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_40_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_41_L), 0xFF, 0x1B/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_41_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_42_L), 0xFF, 0x29/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_42_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_43_L), 0xFF, 0x35/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_43_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_44_L), 0xFF, 0x44/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_44_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_45_L), 0xFF, 0x56/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_45_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_46_L), 0xFF, 0x67/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_46_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_47_L), 0xFF, 0x78/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_47_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_48_L), 0xFF, 0x89/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_48_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_49_L), 0xFF, 0x99/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_49_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4A_L), 0xFF, 0xA8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4A_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4B_L), 0xFF, 0xB6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4B_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4C_L), 0xFF, 0xC5/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4C_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4D_L), 0xFF, 0xD6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4D_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4E_L), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4E_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4F_L), 0xFF, 0xF8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4F_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_50_L), 0xFF, 0x0A/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_50_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_51_L), 0xFF, 0x1B/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_51_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_52_L), 0xFF, 0x29/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_52_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_53_L), 0xFF, 0x35/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_53_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_54_L), 0xFF, 0x44/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_54_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_55_L), 0xFF, 0x56/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_55_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_56_L), 0xFF, 0x67/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_56_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_57_L), 0xFF, 0x78/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_57_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_58_L), 0xFF, 0x89/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_58_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_59_L), 0xFF, 0x99/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_59_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5A_L), 0xFF, 0xA8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5A_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5B_L), 0xFF, 0xB6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5B_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5C_L), 0xFF, 0xC5/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5C_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5D_L), 0xFF, 0xD6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5D_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5E_L), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5E_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5F_L), 0xFF, 0xF8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5F_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC ++//**************************************************** ++ unsigned char MST_VIP_DLC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_30_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_10_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_10_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_11_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_11_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_12_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_12_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_13_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_13_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_14_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_14_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_15_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_15_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_16_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_16_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_17_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_17_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_18_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_18_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_19_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_19_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1A_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1A_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1B_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1B_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1C_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1C_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1D_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1D_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1E_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1E_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1F_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1F_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_20_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_20_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_21_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_21_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_22_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_22_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_23_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_23_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_24_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_24_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_25_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_25_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_26_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_26_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_27_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_27_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_28_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_28_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_29_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_29_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2A_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2A_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2B_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2B_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2C_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2C_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2D_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2D_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2E_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2E_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2F_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2F_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_40_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_40_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_41_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_41_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_42_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_42_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_43_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_43_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_44_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_44_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_45_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_45_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_46_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_46_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_47_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_47_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_48_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_48_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_49_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_49_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4A_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4A_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4B_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4B_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4C_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4C_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4D_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4D_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4E_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4E_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4F_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4F_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_50_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_50_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_51_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_51_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_52_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_52_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_53_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_53_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_54_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_54_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_55_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_55_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_56_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_56_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_57_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_57_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_58_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_58_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_59_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_59_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5A_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5A_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5B_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5B_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5C_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5C_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5D_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5D_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5E_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5E_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5F_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5F_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_75_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_77_L), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_77_H), 0x40, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_76_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_76_H), 0x01, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_77_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_04_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_04_L), 0x02, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_dither ++//**************************************************** ++ unsigned char MST_VIP_DLC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_04_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_His_range ++//**************************************************** ++ unsigned char MST_VIP_DLC_His_range_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_His_range_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_His_range_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_08_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_His_rangeH ++//**************************************************** ++ unsigned char MST_VIP_DLC_His_rangeH_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_His_rangeH_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_His_rangeH_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1F_03_L), 0xFF, 0x0C/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_03_H), 0x01, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_04_L), 0xFF, 0xE4/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_04_H), 0x01, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_His_rangeV ++//**************************************************** ++ unsigned char MST_VIP_DLC_His_rangeV_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_His_rangeV_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_His_rangeV_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1F_01_L), 0xFF, 0x06/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_01_H), 0x03, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_02_L), 0xFF, 0x7A/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_02_H), 0x03, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_PC ++//**************************************************** ++ unsigned char MST_VIP_DLC_PC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_PC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_PC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_04_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_04_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_UVC ++//**************************************************** ++ unsigned char MST_VIP_UVC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_UVC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_UVC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_08_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_08_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_64_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_64_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_65_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_65_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_62_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_62_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_63_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_63_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_64_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7A_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7B_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_full_range ++//**************************************************** ++ unsigned char MST_VIP_FCC_full_range_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_full_range_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_full_range_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_40_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_48_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_48_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_49_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_49_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_45_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_50_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_50_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_51_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_51_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_52_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_52_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_53_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_53_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_54_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_54_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_55_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_55_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_56_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_56_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_57_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_57_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_45_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_58_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_58_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_59_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_59_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_46_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_60_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_60_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_61_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_61_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_62_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_62_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_63_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_63_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_64_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_64_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_65_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_65_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_66_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_66_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_67_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_67_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_46_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_bdry_dist ++//**************************************************** ++ unsigned char MST_VIP_FCC_bdry_dist_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_bdry_dist_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_bdry_dist_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T1 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_18_L), 0xFF, 0x73/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_18_H), 0xFF, 0x9B/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_L), 0x0F, 0x84/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0x03, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0x0C, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0x30, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0xC0, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_45_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_45_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_46_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_46_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_47_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_47_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_48_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_48_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T2 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_19_L), 0xFF, 0x6E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_19_H), 0xFF, 0xAC/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_L), 0xF0, 0x84/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0x03, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0x0C, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0x30, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0xC0, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_49_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_49_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T3 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1A_L), 0xFF, 0xA5/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1A_H), 0xFF, 0x70/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_H), 0x0F, 0x44/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4F_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4F_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_50_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_50_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T4 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T4_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T4_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T4_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1B_L), 0xFF, 0x53/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1B_H), 0xFF, 0xB3/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_H), 0xF0, 0x44/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_51_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_51_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_52_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_52_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_53_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_53_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_54_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_54_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T5 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T5_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T5_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T5_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1C_L), 0xFF, 0x5A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1C_H), 0xFF, 0x75/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_L), 0x0F, 0x88/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_55_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_55_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_56_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_56_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_57_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_57_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_58_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_58_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T6 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T6_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T6_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T6_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1D_L), 0xFF, 0xB0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1D_H), 0xFF, 0x48/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_L), 0xF0, 0x88/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_59_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_59_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_60_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_60_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_61_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_61_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_62_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_62_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T7 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T7_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T7_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T7_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1E_L), 0xFF, 0x74/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1E_H), 0xFF, 0xC8/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_H), 0x0F, 0x58/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0x03, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0x0C, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0x30, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0xC0, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_63_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_63_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_64_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_64_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_65_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_65_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_66_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_66_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T8 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T8_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T8_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T8_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1F_L), 0xFF, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1F_H), 0xFF, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_H), 0xF0, 0x58/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0x03, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0x0C, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0x30, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0xC0, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_67_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_67_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_68_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_68_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_69_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_69_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T9 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T9_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T9_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T9_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_22_L), 0x0F, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_28_L), 0x07, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_28_L), 0x38, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_10_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_43_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_43_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_44_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_44_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC ++//**************************************************** ++ unsigned char MST_VIP_IHC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_24_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC_Ymode ++//**************************************************** ++ unsigned char MST_VIP_IHC_Ymode_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_Ymode_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_Ymode_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_68_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_68_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC_dither ++//**************************************************** ++ unsigned char MST_VIP_IHC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_24_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC_CRD_SRAM ++//**************************************************** ++ unsigned char MST_VIP_IHC_CRD_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_CRD_SRAM_Main[][PQ_IP_VIP_IHC_CRD_SRAM_SIZE_Main]= ++{ ++{//15wins3 ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0xC2, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0x69, ++ 0x00, ++ 0x99, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x69, ++ 0x01, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xC4, ++ 0x01, ++ 0x34, ++ 0x01, ++ 0x84, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x82, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0x02, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0x42, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x79, ++ 0x01, ++ 0xE4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x74, ++ 0x01, ++ 0xA4, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x69, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x89, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x32, ++ 0x00, ++ 0x42, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0x82, ++ 0x00, ++ 0x39, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x62, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x52, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x52, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xE3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x89, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0x83, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0x06, ++ 0x01, ++ 0x16, ++ 0x01, ++ 0x26, ++ 0x01, ++ 0x46, ++ 0x01, ++ 0x66, ++ 0x01, ++ 0x96, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xF7, ++ 0x00, ++ 0x27, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x53, ++ 0x00, ++ 0x73, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0x66, ++ 0x01, ++ 0x76, ++ 0x01, ++ 0x96, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xBA, ++ 0x01, ++ 0x7A, ++ 0x01, ++ 0xE7, ++ 0x00, ++ 0xFC, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x13, ++ 0x00, ++ 0x96, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0x96, ++ 0x01, ++ 0x5A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0xAB, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x25, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0x46, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0x7A, ++ 0x01, ++ 0x4A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0x6A, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x61, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x35, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0xF5, ++ 0x00, ++ 0xC6, ++ 0x00, ++ 0x6A, ++ 0x01, ++ 0x3A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0x21, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0x81, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0x4A, ++ 0x00, ++ 0xDA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x9A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x01, ++ 0x01, ++ 0x31, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xA1, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0x00, ++ 0x00, ++ 0x4A, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xB1, ++ 0x00, ++ 0x41, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0x75, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xC1, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0x33, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0x63, ++ 0x01, ++ 0xF3, ++ 0x00, ++ 0x93, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x12, ++ 0x00, ++ 0x92, ++ 0x00, ++ 0xC2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x49, ++ 0x00, ++ 0x99, ++ 0x00, ++ 0xB9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0x94, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x84, ++ 0x01, ++ 0xD4, ++ 0x00, ++ 0x24, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x22, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x01, ++ 0x22, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xB9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xD4, ++ 0x01, ++ 0x04, ++ 0x01, ++ 0x34, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0x82, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x02, ++ 0x01, ++ 0x92, ++ 0x00, ++ 0x62, ++ 0x00, ++ 0xA9, ++ 0x00, ++ 0x49, ++ 0x01, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xE4, ++ 0x01, ++ 0xF3, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x32, ++ 0x00, ++ 0x89, ++ 0x00, ++ 0x59, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xB3, ++ 0x01, ++ 0xE2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x22, ++ 0x01, ++ 0x72, ++ 0x00, ++ 0x69, ++ 0x00, ++ 0x69, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x82, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0xF2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x29, ++ 0x00, ++ 0x84, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xD3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x94, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xE3, ++ 0x01, ++ 0xB3, ++ 0x01, ++ 0x93, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x63, ++ 0x01, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x98, ++ 0x00, ++ 0x3F, ++ 0x00, ++ 0xE4, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0x06, ++ 0x01, ++ 0x16, ++ 0x01, ++ 0x36, ++ 0x01, ++ 0x56, ++ 0x01, ++ 0x76, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xC7, ++ 0x00, ++ 0xF7, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x43, ++ 0x00, ++ 0x63, ++ 0x00, ++ 0x73, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0x66, ++ 0x01, ++ 0x86, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xAA, ++ 0x01, ++ 0x4A, ++ 0x01, ++ 0xBB, ++ 0x00, ++ 0xFE, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x35, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0xF5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x35, ++ 0x00, ++ 0x23, ++ 0x00, ++ 0xB6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0x7A, ++ 0x01, ++ 0x2A, ++ 0x01, ++ 0x9A, ++ 0x00, ++ 0xAB, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0xA1, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x55, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0xB6, ++ 0x01, ++ 0x9A, ++ 0x01, ++ 0x6A, ++ 0x01, ++ 0x1A, ++ 0x01, ++ 0xAA, ++ 0x00, ++ 0x31, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x31, ++ 0x01, ++ 0xC1, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xF5, ++ 0x00, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0xD5, ++ 0x00, ++ 0x4A, ++ 0x01, ++ 0x4A, ++ 0x01, ++ 0x0A, ++ 0x01, ++ 0xBA, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0xD1, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0xAA, ++ 0x00, ++ 0x0A, ++ 0x01, ++ 0xCA, ++ 0x00, ++ 0x6A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0x31, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xE1, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x35, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0xB5, ++ 0x00, ++ 0x1A, ++ 0x00, ++ 0x6A, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x41, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xF1, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x05, ++ 0x01, ++ 0x35, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0xF1, ++ 0x00, ++ 0x41, ++ 0x01, ++ 0x61, ++ 0x01, ++ 0xF1, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x22, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0xE2, ++ 0x00, ++ 0x82, ++ 0x00, ++ 0x59, ++ 0x00, ++ 0x89, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x69, ++ 0x01, ++ 0xD4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xB4, ++ 0x01, ++ 0xF4, ++ 0x00, ++ 0x34, ++ 0x00, ++ 0x12, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x82, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x79, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xE4, ++ 0x01, ++ 0x04, ++ 0x01, ++ 0x92, ++ 0x00, ++ 0x52, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xF2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x59, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x94, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xD3, ++ 0x01, ++ 0x52, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0x29, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xB4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x62, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x02, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xE4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x22, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xE3, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0x94, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0x83, ++ 0x01, ++ 0x63, ++ 0x01, ++ 0x43, ++ 0x01, ++ 0x43, ++ 0x01, ++ 0x33, ++ 0x01, ++ 0xD6, ++ 0x00, ++ 0xD6, ++ 0x00, ++ 0xE6, ++ 0x00, ++ 0xF6, ++ 0x00, ++ 0x06, ++ 0x01, ++ 0x26, ++ 0x01, ++ 0x66, ++ 0x01, ++ 0x4D, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0x73, ++ 0x00, ++ 0x93, ++ 0x00, ++ 0xA3, ++ 0x00, ++ 0xB3, ++ 0x00, ++ 0xB3, ++ 0x00, ++ 0x36, ++ 0x01, ++ 0x46, ++ 0x01, ++ 0x66, ++ 0x01, ++ 0x86, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0x67, ++ 0x00, ++ 0xF7, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x55, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x43, ++ 0x00, ++ 0x86, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0x9A, ++ 0x01, ++ 0x3A, ++ 0x01, ++ 0xAB, ++ 0x00, ++ 0xAB, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0x76, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xAA, ++ 0x01, ++ 0x7A, ++ 0x01, ++ 0x1A, ++ 0x01, ++ 0xAA, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x41, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x35, ++ 0x01, ++ 0xF5, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x06, ++ 0x01, ++ 0x8A, ++ 0x01, ++ 0x5A, ++ 0x01, ++ 0x1A, ++ 0x01, ++ 0xBA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0x01, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0x71, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0x8A, ++ 0x00, ++ 0x3A, ++ 0x01, ++ 0x0A, ++ 0x01, ++ 0xBA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0x91, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0x1A, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x31, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xB1, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0xF5, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x21, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xC1, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x23, ++ 0x00, ++ 0xD3, ++ 0x00, ++ 0x83, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x93, ++ 0x01, ++ 0x23, ++ 0x01, ++ 0xC3, ++ 0x00, ++ 0x63, ++ 0x00, ++ 0x35, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0xE2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0x49, ++ 0x00, ++ 0x89, ++ 0x00, ++ 0xB9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x54, ++ 0x01, ++ 0x94, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0xE2, ++ 0x00, ++ 0x82, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xA9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0xB4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x74, ++ 0x01, ++ 0x93, ++ 0x00, ++ 0xE2, ++ 0x00, ++ 0x82, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x22, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x99, ++ 0x00, ++ 0x49, ++ 0x01, ++ 0xD4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x53, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0xF2, ++ 0x00, ++ 0x22, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0x59, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0xE2, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0x49, ++ 0x00, ++ 0x79, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0xF2, ++ 0x00, ++ 0x42, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0x82, ++ 0x00, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xD3, ++ 0x01, ++ 0xB3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0xF4, ++ 0x00, ++ 0xF3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x53, ++ 0x01, ++ 0x43, ++ 0x01, ++ 0x33, ++ 0x01, ++ 0x33, ++ 0x01, ++ 0xD6, ++ 0x00, ++ 0xD6, ++ 0x00, ++ 0xE6, ++ 0x00, ++ 0xF6, ++ 0x00, ++ 0x16, ++ 0x01, ++ 0x46, ++ 0x01, ++ 0x4D, ++ 0x01, ++ 0xFD, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x53, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0x93, ++ 0x00, ++ 0xA3, ++ 0x00, ++ 0xB3, ++ 0x00, ++ 0xC3, ++ 0x00, ++ 0x46, ++ 0x01, ++ 0x56, ++ 0x01, ++ 0x76, ++ 0x01, ++ 0x96, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0x96, ++ 0x01, ++ 0xF7, ++ 0x00, ++ 0xFE, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x75, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x23, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x53, ++ 0x00, ++ 0x96, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0xB6, ++ 0x01, ++ 0xAA, ++ 0x01, ++ 0x6A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0xAB, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0x75, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xB6, ++ 0x01, ++ 0xA6, ++ 0x01, ++ 0x8A, ++ 0x01, ++ 0x4A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0x5A, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0xB1, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0x96, ++ 0x01, ++ 0x7A, ++ 0x01, ++ 0x3A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0x41, ++ 0x00, ++ 0x01, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0xD1, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x35, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0xFA, ++ 0x00, ++ 0x2A, ++ 0x01, ++ 0xEA, ++ 0x00, ++ 0x9A, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xE1, ++ 0x00, ++ 0x41, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0xF5, ++ 0x00, ++ 0x55, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0x5A, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0xC1, ++ 0x00, ++ 0x31, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xE1, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x41, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xF1, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x00, ++ 0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// VIP_IHC_SETTING ++//**************************************************** ++ unsigned char MST_VIP_IHC_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_25_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_38_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_40_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_48_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_25_H), 0x7F, 0x1E/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_38_H), 0x7F, 0x17/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_40_H), 0x7F, 0x24/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_48_H), 0x7F, 0x2A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_26_L), 0x7F, 0x67/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_39_L), 0x7F, 0x54/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_41_L), 0x7F, 0x6A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_49_L), 0x7F, 0x65/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_26_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_39_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_41_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_49_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_27_L), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3A_L), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_42_L), 0x7F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4A_L), 0x7F, 0x49/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_27_H), 0x7F, 0x50/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3A_H), 0x7F, 0x4F/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_42_H), 0x7F, 0x50/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4A_H), 0x7F, 0x50/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_28_L), 0x7F, 0x15/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3B_L), 0x7F, 0x1B/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_43_L), 0x7F, 0x1A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4B_L), 0x7F, 0x1D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_28_H), 0x7F, 0x21/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3B_H), 0x7F, 0x1E/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_43_H), 0x7F, 0x23/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4B_H), 0x7F, 0x1D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_29_L), 0x7F, 0x51/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3C_L), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_44_L), 0x7F, 0x15/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4C_L), 0x7F, 0x42/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_29_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3C_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_44_H), 0x7F, 0x4C/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4C_H), 0x7F, 0x54/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2A_L), 0x7F, 0x11/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3D_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_45_L), 0x7F, 0x0C/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4D_L), 0x7F, 0x19/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2A_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3D_H), 0x7F, 0x18/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_45_H), 0x7F, 0x1D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4D_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2B_L), 0x7F, 0x5D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3E_L), 0x7F, 0x1E/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_46_L), 0x7F, 0x1C/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4E_L), 0x7F, 0x22/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2B_H), 0x7F, 0x1A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3E_H), 0x7F, 0x14/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_46_H), 0x7F, 0x14/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4E_H), 0x7F, 0x27/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2C_L), 0x7F, 0x26/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3F_L), 0x7F, 0x2D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_47_L), 0x7F, 0x26/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4F_L), 0x7F, 0x41/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2C_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3F_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_47_H), 0x7F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4F_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC ++//**************************************************** ++ unsigned char MST_VIP_ICC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_60_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_60_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6B_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6B_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6C_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC_Ymode ++//**************************************************** ++ unsigned char MST_VIP_ICC_Ymode_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_Ymode_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_Ymode_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_50_L), 0x80, 0x80/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_50_L), 0x02, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_38_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_40_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_48_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_38_H), 0x0F, 0x07/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_40_H), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_48_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_39_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_41_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_49_L), 0x0F, 0x08/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_39_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_41_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_49_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3A_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x10, 0x10/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_42_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x10, 0x10/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4A_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3A_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_42_H), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4A_H), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3B_L), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_43_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4B_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3B_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_43_H), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4B_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3C_L), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_44_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4C_L), 0x0F, 0x08/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3C_H), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_44_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4C_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3D_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_45_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4D_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3D_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_45_H), 0x0F, 0x07/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4D_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3E_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_46_L), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4E_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3E_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_46_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4E_H), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3F_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_47_L), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4F_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3F_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_47_H), 0x0F, 0x07/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4F_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC_dither ++//**************************************************** ++ unsigned char MST_VIP_ICC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_60_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC_CRD_SRAM ++//**************************************************** ++ unsigned char MST_VIP_ICC_CRD_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_CRD_SRAM_Main[][PQ_IP_VIP_ICC_CRD_SRAM_SIZE_Main]= ++{ ++{//15wins3 ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0xC2, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0x69, ++ 0x00, ++ 0x99, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x69, ++ 0x01, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xC4, ++ 0x01, ++ 0x34, ++ 0x01, ++ 0x84, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x82, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0x02, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0x42, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x79, ++ 0x01, ++ 0xE4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x74, ++ 0x01, ++ 0xA4, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x69, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x89, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x32, ++ 0x00, ++ 0x42, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0x82, ++ 0x00, ++ 0x39, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x62, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x52, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x52, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xE3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x89, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0x83, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0x26, ++ 0x00, ++ 0x36, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x56, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x86, ++ 0x00, ++ 0xB6, ++ 0x00, ++ 0xF7, ++ 0x00, ++ 0x27, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x53, ++ 0x00, ++ 0x73, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x2A, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0xE7, ++ 0x00, ++ 0xFC, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x13, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x5B, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x25, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0x86, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x61, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x35, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0xF5, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0xDA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x9A, ++ 0x00, ++ 0x21, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0x81, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0x2A, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x01, ++ 0x01, ++ 0x31, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xA1, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0x00, ++ 0x00, ++ 0x4A, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xB1, ++ 0x00, ++ 0x41, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0x75, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xC1, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0x33, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0x63, ++ 0x01, ++ 0xF3, ++ 0x00, ++ 0x93, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x12, ++ 0x00, ++ 0x92, ++ 0x00, ++ 0xC2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x49, ++ 0x00, ++ 0x99, ++ 0x00, ++ 0xB9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0x94, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x84, ++ 0x01, ++ 0xD4, ++ 0x00, ++ 0x24, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x22, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x01, ++ 0x22, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xB9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xD4, ++ 0x01, ++ 0x04, ++ 0x01, ++ 0x34, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0x82, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x02, ++ 0x01, ++ 0x92, ++ 0x00, ++ 0x62, ++ 0x00, ++ 0xA9, ++ 0x00, ++ 0x49, ++ 0x01, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xE4, ++ 0x01, ++ 0xF3, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x32, ++ 0x00, ++ 0x89, ++ 0x00, ++ 0x59, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xB3, ++ 0x01, ++ 0xE2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x22, ++ 0x01, ++ 0x72, ++ 0x00, ++ 0x69, ++ 0x00, ++ 0x69, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x82, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0xF2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0x29, ++ 0x00, ++ 0x84, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xD2, ++ 0x00, ++ 0xC4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xD3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x94, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xE3, ++ 0x01, ++ 0xB3, ++ 0x01, ++ 0x93, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x63, ++ 0x01, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x88, ++ 0x00, ++ 0x3F, ++ 0x00, ++ 0xE4, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0xF3, ++ 0x00, ++ 0x36, ++ 0x00, ++ 0x36, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x56, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0xC7, ++ 0x00, ++ 0xF7, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x43, ++ 0x00, ++ 0x63, ++ 0x00, ++ 0x73, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x56, ++ 0x00, ++ 0x5A, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0xBB, ++ 0x00, ++ 0xFE, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x35, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0xF5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x35, ++ 0x00, ++ 0x23, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0xDA, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0xAB, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0xA1, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x55, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x6A, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0x31, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x31, ++ 0x01, ++ 0xC1, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xF5, ++ 0x00, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0xD5, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0xD1, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0x6A, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0x31, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xE1, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x35, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0xB5, ++ 0x00, ++ 0x1A, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x41, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xF1, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x05, ++ 0x01, ++ 0x35, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0xA1, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0xF1, ++ 0x00, ++ 0x41, ++ 0x01, ++ 0x61, ++ 0x01, ++ 0xF1, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x22, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0xE2, ++ 0x00, ++ 0x82, ++ 0x00, ++ 0x59, ++ 0x00, ++ 0x89, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x69, ++ 0x01, ++ 0xD4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xB4, ++ 0x01, ++ 0xF4, ++ 0x00, ++ 0x34, ++ 0x00, ++ 0x12, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x82, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x79, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xE4, ++ 0x01, ++ 0x04, ++ 0x01, ++ 0x92, ++ 0x00, ++ 0x52, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0xF2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x59, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0x94, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xD3, ++ 0x01, ++ 0x52, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x52, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0x29, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xB4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x62, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x02, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x02, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0xF9, ++ 0x00, ++ 0xE4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x22, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA8, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x52, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0xF9, ++ 0x00, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xE3, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0x94, ++ 0x01, ++ 0xC3, ++ 0x01, ++ 0x83, ++ 0x01, ++ 0x63, ++ 0x01, ++ 0x43, ++ 0x01, ++ 0x43, ++ 0x01, ++ 0x33, ++ 0x01, ++ 0x26, ++ 0x00, ++ 0x36, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x56, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x86, ++ 0x00, ++ 0xB6, ++ 0x00, ++ 0x4D, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0x73, ++ 0x00, ++ 0x93, ++ 0x00, ++ 0xA3, ++ 0x00, ++ 0xB3, ++ 0x00, ++ 0xB3, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0xB6, ++ 0x00, ++ 0xB6, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x67, ++ 0x00, ++ 0xF7, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x55, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x43, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0xDA, ++ 0x00, ++ 0x9B, ++ 0x00, ++ 0x7B, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0x86, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x5A, ++ 0x00, ++ 0x9A, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x41, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x35, ++ 0x01, ++ 0xF5, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x56, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0x01, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0x71, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0x3A, ++ 0x00, ++ 0xBA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0x91, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0x1A, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x11, ++ 0x01, ++ 0x31, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xB1, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0xF5, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0xC5, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x21, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0x21, ++ 0x01, ++ 0xC1, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x23, ++ 0x00, ++ 0xD3, ++ 0x00, ++ 0x83, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x93, ++ 0x01, ++ 0x23, ++ 0x01, ++ 0xC3, ++ 0x00, ++ 0x63, ++ 0x00, ++ 0x35, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0x15, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0xE2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0x42, ++ 0x00, ++ 0x89, ++ 0x00, ++ 0xB9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x54, ++ 0x01, ++ 0x94, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x72, ++ 0x00, ++ 0x32, ++ 0x01, ++ 0x82, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0xE2, ++ 0x00, ++ 0x82, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0xA9, ++ 0x00, ++ 0x39, ++ 0x01, ++ 0xB4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0x74, ++ 0x01, ++ 0x93, ++ 0x00, ++ 0xE2, ++ 0x00, ++ 0x82, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x22, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0x52, ++ 0x00, ++ 0x99, ++ 0x00, ++ 0x49, ++ 0x01, ++ 0xD4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0x53, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0x72, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0xF2, ++ 0x00, ++ 0x22, ++ 0x00, ++ 0x79, ++ 0x00, ++ 0x59, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xB2, ++ 0x00, ++ 0xE2, ++ 0x00, ++ 0x22, ++ 0x01, ++ 0x62, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x42, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0x49, ++ 0x00, ++ 0x79, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xB2, ++ 0x00, ++ 0xF2, ++ 0x00, ++ 0x42, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x12, ++ 0x01, ++ 0x82, ++ 0x00, ++ 0xA4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xA8, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0xA2, ++ 0x00, ++ 0x12, ++ 0x01, ++ 0x92, ++ 0x01, ++ 0x32, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF4, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xF3, ++ 0x01, ++ 0xD3, ++ 0x01, ++ 0xB3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD8, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0xD2, ++ 0x00, ++ 0xF4, ++ 0x00, ++ 0xF3, ++ 0x01, ++ 0xA3, ++ 0x01, ++ 0x73, ++ 0x01, ++ 0x53, ++ 0x01, ++ 0x43, ++ 0x01, ++ 0x33, ++ 0x01, ++ 0x33, ++ 0x01, ++ 0x36, ++ 0x00, ++ 0x36, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x56, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0x4D, ++ 0x01, ++ 0xFD, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x53, ++ 0x00, ++ 0x83, ++ 0x00, ++ 0x93, ++ 0x00, ++ 0xA3, ++ 0x00, ++ 0xB3, ++ 0x00, ++ 0xC3, ++ 0x00, ++ 0x96, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0xB6, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0xF7, ++ 0x00, ++ 0xFE, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x75, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0x65, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x23, ++ 0x00, ++ 0x33, ++ 0x00, ++ 0x53, ++ 0x00, ++ 0xA6, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x4A, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x7B, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0x75, ++ 0x01, ++ 0x45, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0xA5, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x45, ++ 0x00, ++ 0x76, ++ 0x00, ++ 0x46, ++ 0x00, ++ 0x7A, ++ 0x00, ++ 0xCA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x6A, ++ 0x00, ++ 0xD1, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0xB1, ++ 0x00, ++ 0x75, ++ 0x00, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x15, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0xB5, ++ 0x00, ++ 0x66, ++ 0x00, ++ 0x9A, ++ 0x00, ++ 0xDA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0x8A, ++ 0x00, ++ 0x41, ++ 0x00, ++ 0x01, ++ 0x01, ++ 0x41, ++ 0x01, ++ 0xD1, ++ 0x00, ++ 0x25, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x45, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x65, ++ 0x01, ++ 0x35, ++ 0x01, ++ 0x05, ++ 0x01, ++ 0x7A, ++ 0x00, ++ 0xDA, ++ 0x00, ++ 0xEA, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0x21, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xE1, ++ 0x00, ++ 0x41, ++ 0x00, ++ 0x85, ++ 0x00, ++ 0xF5, ++ 0x00, ++ 0x55, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0x75, ++ 0x01, ++ 0xE5, ++ 0x00, ++ 0x4A, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0xAA, ++ 0x00, ++ 0x51, ++ 0x00, ++ 0x91, ++ 0x00, ++ 0xC1, ++ 0x00, ++ 0x31, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xE1, ++ 0x00, ++ 0x71, ++ 0x00, ++ 0x55, ++ 0x00, ++ 0xC5, ++ 0x00, ++ 0x15, ++ 0x01, ++ 0x55, ++ 0x01, ++ 0x25, ++ 0x01, ++ 0x75, ++ 0x00, ++ 0x00, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x61, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0xB1, ++ 0x00, ++ 0xE1, ++ 0x00, ++ 0x41, ++ 0x01, ++ 0x51, ++ 0x01, ++ 0xF1, ++ 0x00, ++ 0x81, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x95, ++ 0x00, ++ 0xE5, ++ 0x00, ++ 0xD5, ++ 0x00, ++ 0x65, ++ 0x00, ++ 0x00, ++ 0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// VIP_ICC_SETTING ++//**************************************************** ++ unsigned char MST_VIP_ICC_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_61_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_61_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_62_L), 0x0F, 0x0A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_62_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x08, 0x08/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_63_L), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_63_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x20, 0x20/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_64_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_64_H), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_65_L), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_65_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_66_L), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_66_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_67_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_67_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_68_L), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_68_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Ymode_Yvalue_ALL ++//**************************************************** ++ unsigned char MST_VIP_Ymode_Yvalue_ALL_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Ymode_Yvalue_ALL_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Ymode_Yvalue_ALL_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_36_L), 0xFF, 0x20/*Y1*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_36_H), 0xFF, 0x40/*Y1*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_37_L), 0xFF, 0x60/*Y1*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_37_H), 0xFF, 0x80/*Y1*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Ymode_Yvalue_SETTING ++//**************************************************** ++ unsigned char MST_VIP_Ymode_Yvalue_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Ymode_Yvalue_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Ymode_Yvalue_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_08_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_08_H), 0xFF, 0x40/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_09_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_09_H), 0xFF, 0x80/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0A_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0A_H), 0xFF, 0x51/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0B_L), 0xFF, 0x9F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0B_H), 0xFF, 0xD7/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0C_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0C_H), 0xFF, 0x44/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0D_L), 0xFF, 0x7F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0D_H), 0xFF, 0xC8/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0E_L), 0xFF, 0x0E/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0E_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0F_L), 0xFF, 0x84/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0F_H), 0xFF, 0xBD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_10_L), 0xFF, 0x0C/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_10_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_11_L), 0xFF, 0x82/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_11_H), 0xFF, 0xCD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_12_L), 0xFF, 0x4A/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_12_H), 0xFF, 0x6A/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_13_L), 0xFF, 0xA1/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_13_H), 0xFF, 0xD3/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_14_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_14_H), 0xFF, 0x53/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_15_L), 0xFF, 0x8E/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_15_H), 0xFF, 0xCE/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_16_L), 0xFF, 0x22/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_16_H), 0xFF, 0x4F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_17_L), 0xFF, 0x94/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_17_H), 0xFF, 0xB1/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_18_L), 0xFF, 0x22/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_18_H), 0xFF, 0x46/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_19_L), 0xFF, 0xAA/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_19_H), 0xFF, 0xCD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1A_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1A_H), 0xFF, 0x40/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1B_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1B_H), 0xFF, 0x80/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1C_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1C_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1D_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1D_H), 0xFF, 0xBD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1E_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1E_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1F_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1F_H), 0xFF, 0x84/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_20_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_20_H), 0xFF, 0x58/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_21_L), 0xFF, 0x92/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_21_H), 0xFF, 0xED/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_22_L), 0xFF, 0x24/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_22_H), 0xFF, 0x4F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_23_L), 0xFF, 0x91/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_23_H), 0xFF, 0xAD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_24_L), 0xFF, 0x24/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_24_H), 0xFF, 0x4F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_25_L), 0xFF, 0x91/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_25_H), 0xFF, 0xAD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_26_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_26_H), 0xFF, 0x40/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_27_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_27_H), 0xFF, 0x80/*Y2*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IBC ++//**************************************************** ++ unsigned char MST_VIP_IBC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IBC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IBC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IBC_dither ++//**************************************************** ++ unsigned char MST_VIP_IBC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IBC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IBC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IBC_SETTING ++//**************************************************** ++ unsigned char MST_VIP_IBC_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IBC_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IBC_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_11_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_11_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_12_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_12_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_13_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_13_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_14_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_14_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_15_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_15_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_16_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_16_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_17_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_17_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_18_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_18_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_21_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_21_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ACK ++//**************************************************** ++ unsigned char MST_VIP_ACK_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ACK_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ACK_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_38_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_38_L), 0x10, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_38_L), 0x80, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_39_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_39_H), 0x3F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3A_L), 0x0F, 0xC0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3A_L), 0xF0, 0xC0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3A_H), 0x1F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_L), 0x7F, 0x3C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_L), 0x80, 0x3C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_H), 0x0F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_H), 0x60, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_YCbCr_Clip ++//**************************************************** ++ unsigned char MST_VIP_YCbCr_Clip_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_YCbCr_Clip_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_YCbCr_Clip_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_78_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_79_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_79_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7A_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7A_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7B_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7B_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7C_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7C_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7D_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7D_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7E_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7E_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Y_SC1 ++//**************************************************** ++ unsigned char MST_VSP_Y_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Y_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Y_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_C_SC1 ++//**************************************************** ++ unsigned char MST_VSP_C_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_C_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_C_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_CoRing_SC1 ++//**************************************************** ++ unsigned char MST_VSP_CoRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_CoRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_CoRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0E_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_DeRing_SC1 ++//**************************************************** ++ unsigned char MST_VSP_DeRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_DeRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_DeRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_11_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_11_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_20_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Dither_SC1 ++//**************************************************** ++ unsigned char MST_VSP_Dither_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Dither_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Dither_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_PreVBound_SC1 ++//**************************************************** ++ unsigned char MST_VSP_PreVBound_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_PreVBound_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_PreVBound_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_13_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// AntiPAL_filter_SC1 ++//**************************************************** ++ unsigned char MST_AntiPAL_filter_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_AntiPAL_filter_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AntiPAL_filter_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_68_L), 0x1F, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_69_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_69_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422To444_SC1 ++//**************************************************** ++ unsigned char MST_422To444_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422To444_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422To444_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_L), 0x80, 0x80/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Y_SC1 ++//**************************************************** ++ unsigned char MST_HSP_Y_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Y_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Y_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_C_SC1 ++//**************************************************** ++ unsigned char MST_HSP_C_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_C_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_C_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_CoRing_SC1 ++//**************************************************** ++ unsigned char MST_HSP_CoRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_CoRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_CoRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0D_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_DeRing_SC1 ++//**************************************************** ++ unsigned char MST_HSP_DeRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_DeRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_DeRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0F_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0F_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0F_H), 0X03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0F_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_L), 0X0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_20_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Dither_SC1 ++//**************************************************** ++ unsigned char MST_HSP_Dither_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Dither_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Dither_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HnonLinear_SC1 ++//**************************************************** ++ unsigned char MST_HnonLinear_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HnonLinear_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HnonLinear_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_13_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_14_L), 0xFF, 0x7E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_14_H), 0xFF, 0x72/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_15_L), 0xFF, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_15_H), 0x80, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_15_H), 0x7F, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_16_L), 0xFF, 0x21/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_16_H), 0xFF, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// SRAM1 ++//**************************************************** ++ unsigned char MST_SRAM1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM1_Main[][PQ_IP_SRAM1_SIZE_Main]= ++{ ++ {//InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G13 ++ 0x29,0x9b,0x82,0x41,0x86, ++ 0x29,0x99,0x62,0xc1,0x86, ++ 0x2b,0x97,0x32,0xc1,0x86, ++ 0x2c,0x97,0x12,0x41,0x87, ++ 0x2d,0x97,0x02,0x41,0x87, ++ 0x2e,0x95,0xc2,0x40,0x88, ++ 0x30,0x93,0x92,0x40,0x88, ++ 0x31,0x95,0x82,0xc0,0x88, ++ 0x32,0x93,0x62,0xc0,0x88, ++ 0x32,0x8b,0x22,0xc0,0x88, ++ 0x33,0x8d,0x12,0x40,0x89, ++ 0x34,0x8b,0x22,0x80,0x89, ++ 0x35,0x87,0x62,0x00,0x8a, ++ 0x36,0x87,0x72,0x00,0x8a, ++ 0x37,0x85,0xb2,0x00,0x8b, ++ 0x38,0x81,0xe2,0x00,0x8b, ++ 0x39,0x81,0x02,0x81,0x8b, ++ 0x39,0x7b,0x32,0x81,0x8b, ++ 0x3a,0x7b,0x52,0x01,0x8c, ++ 0x3b,0x77,0xa2,0x01,0x8d, ++ 0x3c,0x73,0xd2,0x01,0x8d, ++ 0x3d,0x71,0xf2,0x01,0x8d, ++ 0x3e,0x6d,0x32,0x82,0x8d, ++ 0x3d,0x69,0x62,0x82,0x8e, ++ 0x3e,0x63,0xa2,0x82,0x8e, ++ 0x3f,0x61,0xd2,0x02,0x8f, ++ 0x3f,0x59,0x12,0x03,0x8f, ++ 0x3f,0x57,0x42,0x03,0x90, ++ 0x40,0x53,0x82,0x83,0x90, ++ 0x40,0x4d,0xb2,0x83,0x90, ++ 0x40,0x4b,0xd2,0x03,0x91, ++ 0x41,0x47,0x02,0x04,0x91, ++ 0x42,0x41,0x62,0x04,0x92, ++ 0x41,0x3d,0x72,0x04,0x92, ++ 0x42,0x39,0xb2,0x84,0x92, ++ 0x41,0x31,0xf2,0x04,0x93, ++ 0x42,0x2d,0x22,0x05,0x93, ++ 0x42,0x29,0x62,0x05,0x94, ++ 0x42,0x23,0x92,0x05,0x94, ++ 0x42,0x1d,0xd2,0x85,0x94, ++ 0x43,0x19,0x12,0x06,0x95, ++ 0x42,0x11,0x42,0x06,0x95, ++ 0x43,0x0d,0x92,0x06,0x96, ++ 0x42,0x05,0xd2,0x86,0x96, ++ 0x42,0x01,0xf2,0x86,0x96, ++ 0x42,0xf7,0x51,0x07,0x97, ++ 0x42,0xf5,0x61,0x07,0x97, ++ 0x41,0xeb,0xc1,0x07,0x98, ++ 0x42,0xe5,0x11,0x88,0x98, ++ 0x41,0xdf,0x31,0x88,0x98, ++ 0x41,0xd9,0x71,0x08,0x99, ++ 0x40,0xcf,0xb1,0x08,0x99, ++ 0x41,0xcd,0xe1,0x88,0x99, ++ 0x40,0xc5,0x21,0x09,0x9a, ++ 0x40,0xbd,0x61,0x09,0x9a, ++ 0x3f,0xb5,0xa1,0x89,0x9a, ++ 0x3e,0xad,0xd1,0x89,0x9a, ++ 0x3e,0xa9,0x11,0x8a,0x9b, ++ 0x3e,0xa3,0x51,0x0a,0x9c, ++ 0x3e,0x9b,0xa1,0x8a,0x9c, ++ 0x3d,0x91,0xe1,0x8a,0x9c, ++ 0x3d,0x8b,0x21,0x0b,0x9d, ++ 0x3c,0x81,0x61,0x0b,0x9d, ++ 0x3c,0x7d,0x91,0x8b,0x9d ++ }, ++ ++}; ++ ++//**************************************************** ++// SRAM2 ++//**************************************************** ++ unsigned char MST_SRAM2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM2_Main[][PQ_IP_SRAM2_SIZE_Main]= ++{ ++ {//InvSinc4Tc4p4Fc45Apass01Astop40 ++ 0x3c,0xdc,0xd0,0x83,0x0c, ++ 0x3c,0xdc,0xe0,0x03,0x0c, ++ 0x3c,0xde,0xf0,0x03,0x0b, ++ 0x3c,0xe0,0x00,0x04,0x0a, ++ 0x3c,0xe0,0x10,0x84,0x09, ++ 0x3b,0xe2,0x20,0x04,0x09, ++ 0x3b,0xe2,0x30,0x84,0x08, ++ 0x3b,0xe4,0x30,0x04,0x08, ++ 0x3a,0xe4,0x40,0x04,0x08, ++ 0x3a,0xe4,0x50,0x84,0x07, ++ 0x39,0xe4,0x60,0x84,0x07, ++ 0x39,0xe6,0x70,0x84,0x06, ++ 0x38,0xe6,0x70,0x04,0x07, ++ 0x38,0xe6,0x80,0x84,0x06, ++ 0x37,0xe6,0x90,0x84,0x06, ++ 0x37,0xe6,0x90,0x84,0x06, ++ 0x36,0xe6,0xa0,0x84,0x06, ++ 0x35,0xe6,0xb0,0x84,0x06, ++ 0x35,0xe6,0xb0,0x84,0x06, ++ 0x34,0xe6,0xc0,0x84,0x06, ++ 0x34,0xe6,0xc0,0x84,0x06, ++ 0x33,0xe6,0xd0,0x84,0x06, ++ 0x33,0xe4,0xe0,0x84,0x06, ++ 0x32,0xe4,0xf0,0x84,0x06, ++ 0x31,0xe4,0x00,0x85,0x06, ++ 0x31,0xe4,0x00,0x85,0x06, ++ 0x30,0xe4,0x10,0x85,0x06, ++ 0x30,0xe4,0x10,0x85,0x06, ++ 0x2f,0xe2,0x20,0x05,0x07, ++ 0x2e,0xe2,0x30,0x05,0x07, ++ 0x2e,0xe2,0x30,0x05,0x07, ++ 0x2d,0xe2,0x40,0x05,0x07, ++ 0x2d,0xe0,0x40,0x85,0x07, ++ 0x2c,0xe0,0x50,0x85,0x07, ++ 0x2b,0xe0,0x60,0x85,0x07, ++ 0x2b,0xe0,0x60,0x85,0x07, ++ 0x2a,0xde,0x70,0x05,0x08, ++ 0x2a,0xde,0x70,0x05,0x08, ++ 0x29,0xde,0x70,0x85,0x08, ++ 0x29,0xdc,0x80,0x85,0x08, ++ 0x28,0xdc,0x90,0x85,0x08, ++ 0x27,0xdc,0x90,0x05,0x09, ++ 0x27,0xda,0xa0,0x05,0x09, ++ 0x26,0xda,0xa0,0x85,0x09, ++ 0x26,0xda,0xa0,0x85,0x09, ++ 0x25,0xd8,0xc0,0x85,0x09, ++ 0x25,0xd8,0xc0,0x85,0x09, ++ 0x24,0xd8,0xc0,0x05,0x0a, ++ 0x23,0xd6,0xd0,0x85,0x0a, ++ 0x23,0xd6,0xd0,0x85,0x0a, ++ 0x22,0xd4,0xf0,0x85,0x0a, ++ 0x22,0xd4,0xe0,0x05,0x0b, ++ 0x21,0xd4,0xf0,0x05,0x0b, ++ 0x21,0xd2,0x00,0x06,0x0b, ++ 0x20,0xd2,0x00,0x86,0x0b, ++ 0x20,0xd0,0x10,0x86,0x0b, ++ 0x1f,0xd0,0x10,0x06,0x0c, ++ 0x1f,0xd0,0x10,0x06,0x0c, ++ 0x1e,0xce,0x20,0x86,0x0c, ++ 0x1e,0xce,0x20,0x86,0x0c, ++ 0x1d,0xcc,0x30,0x06,0x0d, ++ 0x1d,0xcc,0x30,0x06,0x0d, ++ 0x1c,0xca,0x40,0x86,0x0d, ++ 0x1c,0xca,0x40,0x86,0x0d ++ }, ++ ++}; ++ ++//**************************************************** ++// SRAM3 ++//**************************************************** ++ unsigned char MST_SRAM3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM3_Main[][PQ_IP_SRAM3_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// SRAM4 ++//**************************************************** ++ unsigned char MST_SRAM4_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM4_Main[][PQ_IP_SRAM4_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM1 ++//**************************************************** ++ unsigned char MST_C_SRAM1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM1_Main[][PQ_IP_C_SRAM1_SIZE_Main]= ++{ ++{//C121 ++ 0x40,0x00,0x01,0x04,0x00, ++ 0x3f,0xfe,0x10,0x84,0x00, ++ 0x3f,0xfe,0x10,0x84,0x00, ++ 0x3e,0xfc,0x20,0x04,0x01, ++ 0x3e,0xfc,0x20,0x04,0x01, ++ 0x3d,0xfa,0x30,0x84,0x01, ++ 0x3d,0xfa,0x30,0x84,0x01, ++ 0x3c,0xf8,0x40,0x04,0x02, ++ 0x3c,0xf8,0x40,0x04,0x02, ++ 0x3b,0xf6,0x50,0x84,0x02, ++ 0x3b,0xf6,0x50,0x84,0x02, ++ 0x3a,0xf4,0x60,0x04,0x03, ++ 0x3a,0xf4,0x60,0x04,0x03, ++ 0x39,0xf2,0x70,0x84,0x03, ++ 0x39,0xf2,0x70,0x84,0x03, ++ 0x38,0xf0,0x80,0x04,0x04, ++ 0x38,0xf0,0x80,0x04,0x04, ++ 0x37,0xee,0x90,0x84,0x04, ++ 0x37,0xee,0x90,0x84,0x04, ++ 0x36,0xec,0xa0,0x04,0x05, ++ 0x36,0xec,0xa0,0x04,0x05, ++ 0x35,0xea,0xb0,0x84,0x05, ++ 0x35,0xea,0xb0,0x84,0x05, ++ 0x34,0xe8,0xc0,0x04,0x06, ++ 0x34,0xe8,0xc0,0x04,0x06, ++ 0x33,0xe6,0xd0,0x84,0x06, ++ 0x33,0xe6,0xd0,0x84,0x06, ++ 0x32,0xe4,0xe0,0x04,0x07, ++ 0x32,0xe4,0xe0,0x04,0x07, ++ 0x31,0xe2,0xf0,0x84,0x07, ++ 0x31,0xe2,0xf0,0x84,0x07, ++ 0x30,0xe0,0x00,0x05,0x08, ++ 0x30,0xe0,0x00,0x05,0x08, ++ 0x2f,0xde,0x10,0x85,0x08, ++ 0x2f,0xde,0x10,0x85,0x08, ++ 0x2e,0xdc,0x20,0x05,0x09, ++ 0x2e,0xdc,0x20,0x05,0x09, ++ 0x2d,0xda,0x30,0x85,0x09, ++ 0x2d,0xda,0x30,0x85,0x09, ++ 0x2c,0xd8,0x40,0x05,0x0a, ++ 0x2c,0xd8,0x40,0x05,0x0a, ++ 0x2b,0xd6,0x50,0x85,0x0a, ++ 0x2b,0xd6,0x50,0x85,0x0a, ++ 0x2a,0xd4,0x60,0x05,0x0b, ++ 0x2a,0xd4,0x60,0x05,0x0b, ++ 0x29,0xd2,0x70,0x85,0x0b, ++ 0x29,0xd2,0x70,0x85,0x0b, ++ 0x28,0xd0,0x80,0x05,0x0c, ++ 0x28,0xd0,0x80,0x05,0x0c, ++ 0x27,0xce,0x90,0x85,0x0c, ++ 0x27,0xce,0x90,0x85,0x0c, ++ 0x26,0xcc,0xa0,0x05,0x0d, ++ 0x26,0xcc,0xa0,0x05,0x0d, ++ 0x25,0xca,0xb0,0x85,0x0d, ++ 0x25,0xca,0xb0,0x85,0x0d, ++ 0x24,0xc8,0xc0,0x05,0x0e, ++ 0x24,0xc8,0xc0,0x05,0x0e, ++ 0x23,0xc6,0xd0,0x85,0x0e, ++ 0x23,0xc6,0xd0,0x85,0x0e, ++ 0x22,0xc4,0xe0,0x05,0x0f, ++ 0x22,0xc4,0xe0,0x05,0x0f, ++ 0x21,0xc2,0xf0,0x85,0x0f, ++ 0x21,0xc2,0xf0,0x85,0x0f, ++ 0x20,0xc0,0x00,0x06,0x10 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM2 ++//**************************************************** ++ unsigned char MST_C_SRAM2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM2_Main[][PQ_IP_C_SRAM2_SIZE_Main]= ++{ ++{//C2121 ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM3 ++//**************************************************** ++ unsigned char MST_C_SRAM3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM3_Main[][PQ_IP_C_SRAM3_SIZE_Main]= ++{ ++{//C161 ++ 0x20,0x80,0x01,0x02,0x00, ++ 0x20,0x7e,0x11,0x02,0x00, ++ 0x1f,0x7c,0x21,0x82,0x00, ++ 0x1f,0x78,0x41,0x82,0x00, ++ 0x1f,0x76,0x51,0x82,0x00, ++ 0x1f,0x74,0x61,0x82,0x00, ++ 0x1e,0x72,0x71,0x02,0x01, ++ 0x1e,0x6e,0x91,0x02,0x01, ++ 0x1e,0x6c,0xa1,0x02,0x01, ++ 0x1e,0x6a,0xb1,0x02,0x01, ++ 0x1d,0x68,0xc1,0x82,0x01, ++ 0x1d,0x64,0xe1,0x82,0x01, ++ 0x1d,0x62,0xf1,0x82,0x01, ++ 0x1d,0x60,0x01,0x83,0x01, ++ 0x1c,0x5e,0x11,0x03,0x02, ++ 0x1c,0x5a,0x31,0x03,0x02, ++ 0x1c,0x58,0x41,0x03,0x02, ++ 0x1c,0x56,0x51,0x03,0x02, ++ 0x1b,0x54,0x61,0x83,0x02, ++ 0x1b,0x50,0x81,0x83,0x02, ++ 0x1b,0x4e,0x91,0x83,0x02, ++ 0x1b,0x4c,0xa1,0x83,0x02, ++ 0x1a,0x4a,0xb1,0x03,0x03, ++ 0x1a,0x46,0xd1,0x03,0x03, ++ 0x1a,0x44,0xe1,0x03,0x03, ++ 0x1a,0x42,0xf1,0x03,0x03, ++ 0x19,0x40,0x01,0x84,0x03, ++ 0x19,0x3c,0x21,0x84,0x03, ++ 0x19,0x3a,0x31,0x84,0x03, ++ 0x19,0x38,0x41,0x84,0x03, ++ 0x18,0x36,0x51,0x04,0x04, ++ 0x18,0x32,0x71,0x04,0x04, ++ 0x18,0x30,0x81,0x04,0x04, ++ 0x18,0x2e,0x91,0x04,0x04, ++ 0x17,0x2c,0xa1,0x84,0x04, ++ 0x17,0x28,0xc1,0x84,0x04, ++ 0x17,0x26,0xd1,0x84,0x04, ++ 0x17,0x24,0xe1,0x84,0x04, ++ 0x16,0x22,0xf1,0x04,0x05, ++ 0x16,0x1e,0x11,0x05,0x05, ++ 0x16,0x1c,0x21,0x05,0x05, ++ 0x16,0x1a,0x31,0x05,0x05, ++ 0x15,0x18,0x41,0x85,0x05, ++ 0x15,0x14,0x61,0x85,0x05, ++ 0x15,0x12,0x71,0x85,0x05, ++ 0x15,0x10,0x81,0x85,0x05, ++ 0x14,0x0e,0x91,0x05,0x06, ++ 0x14,0x0a,0xb1,0x05,0x06, ++ 0x14,0x08,0xc1,0x05,0x06, ++ 0x14,0x06,0xd1,0x05,0x06, ++ 0x13,0x04,0xe1,0x85,0x06, ++ 0x13,0x00,0x01,0x86,0x06, ++ 0x13,0xfe,0x10,0x86,0x06, ++ 0x13,0xfc,0x20,0x86,0x06, ++ 0x12,0xfa,0x30,0x06,0x07, ++ 0x12,0xf6,0x50,0x06,0x07, ++ 0x12,0xf4,0x60,0x06,0x07, ++ 0x12,0xf2,0x70,0x06,0x07, ++ 0x11,0xf0,0x80,0x86,0x07, ++ 0x11,0xec,0xa0,0x86,0x07, ++ 0x11,0xea,0xb0,0x86,0x07, ++ 0x11,0xe8,0xc0,0x86,0x07, ++ 0x10,0xe6,0xd0,0x06,0x08, ++ 0x10,0xe2,0xf0,0x06,0x08 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM4 ++//**************************************************** ++ unsigned char MST_C_SRAM4_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM4_Main[][PQ_IP_C_SRAM4_SIZE_Main]= ++{ ++{//C2121 ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20 ++}, ++ ++}; ++ ++//**************************************************** ++// VSP_Y_SC2 ++//**************************************************** ++ unsigned char MST_VSP_Y_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Y_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Y_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_C_SC2 ++//**************************************************** ++ unsigned char MST_VSP_C_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_C_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_C_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_CoRing_SC2 ++//**************************************************** ++ unsigned char MST_VSP_CoRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_CoRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_CoRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0E_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_DeRing_SC2 ++//**************************************************** ++ unsigned char MST_VSP_DeRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_DeRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_DeRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_11_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_11_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_20_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Dither_SC2 ++//**************************************************** ++ unsigned char MST_VSP_Dither_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Dither_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Dither_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_PreVBound_SC2 ++//**************************************************** ++ unsigned char MST_VSP_PreVBound_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_PreVBound_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_PreVBound_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_13_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// AntiPAL_filter_SC2 ++//**************************************************** ++ unsigned char MST_AntiPAL_filter_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_AntiPAL_filter_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AntiPAL_filter_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_68_L), 0x1F, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_69_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_69_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422To444_SC2 ++//**************************************************** ++ unsigned char MST_422To444_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422To444_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422To444_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_L), 0x80, 0x80/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Y_SC2 ++//**************************************************** ++ unsigned char MST_HSP_Y_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Y_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Y_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_C_SC2 ++//**************************************************** ++ unsigned char MST_HSP_C_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_C_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_C_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x20, 0x00/*Bypass*/, ++ 0x02/*Bilinear*/, ++ 0x04/*C_SRAM_1*/, ++ 0x06/*C_SRAM_2*/, ++ 0x08/*C_SRAM_3*/, ++ 0x0A/*C_SRAM_4*/, ++ 0x10/*SRAM_1_4Tap*/, ++ 0x30/*SRAM_2_4Tap*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x10, 0x00/*Bypass*/, ++ 0x02/*Bilinear*/, ++ 0x04/*C_SRAM_1*/, ++ 0x06/*C_SRAM_2*/, ++ 0x08/*C_SRAM_3*/, ++ 0x0A/*C_SRAM_4*/, ++ 0x10/*SRAM_1_4Tap*/, ++ 0x30/*SRAM_2_4Tap*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x0E, 0x00/*Bypass*/, ++ 0x02/*Bilinear*/, ++ 0x04/*C_SRAM_1*/, ++ 0x06/*C_SRAM_2*/, ++ 0x08/*C_SRAM_3*/, ++ 0x0A/*C_SRAM_4*/, ++ 0x10/*SRAM_1_4Tap*/, ++ 0x30/*SRAM_2_4Tap*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_CoRing_SC2 ++//**************************************************** ++ unsigned char MST_HSP_CoRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_CoRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_CoRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0D_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_DeRing_SC2 ++//**************************************************** ++ unsigned char MST_HSP_DeRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_DeRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_DeRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0F_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0F_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0F_H), 0X03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0F_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_L), 0X0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_20_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Dither_SC2 ++//**************************************************** ++ unsigned char MST_HSP_Dither_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Dither_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Dither_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HnonLinear_SC2 ++//**************************************************** ++ unsigned char MST_HnonLinear_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HnonLinear_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HnonLinear_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_13_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_14_L), 0xFF, 0x7E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_14_H), 0xFF, 0x72/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_15_L), 0xFF, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_15_H), 0x80, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_15_H), 0x7F, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_16_L), 0xFF, 0x21/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_16_H), 0xFF, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Y_SC3 ++//**************************************************** ++ unsigned char MST_VSP_Y_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Y_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Y_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_C_SC3 ++//**************************************************** ++ unsigned char MST_VSP_C_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_C_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_C_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_CoRing_SC3 ++//**************************************************** ++ unsigned char MST_VSP_CoRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_CoRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_CoRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0E_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_DeRing_SC3 ++//**************************************************** ++ unsigned char MST_VSP_DeRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_DeRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_DeRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_11_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_11_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_20_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Dither_SC3 ++//**************************************************** ++ unsigned char MST_VSP_Dither_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Dither_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Dither_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_PreVBound_SC3 ++//**************************************************** ++ unsigned char MST_VSP_PreVBound_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_PreVBound_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_PreVBound_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_13_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// AntiPAL_filter_SC3 ++//**************************************************** ++ unsigned char MST_AntiPAL_filter_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_AntiPAL_filter_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AntiPAL_filter_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_68_L), 0x1F, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_69_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_69_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422To444_SC3 ++//**************************************************** ++ unsigned char MST_422To444_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422To444_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422To444_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_L), 0x80, 0x80/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Y_SC3 ++//**************************************************** ++ unsigned char MST_HSP_Y_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Y_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Y_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_C_SC3 ++//**************************************************** ++ unsigned char MST_HSP_C_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_C_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_C_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_CoRing_SC3 ++//**************************************************** ++ unsigned char MST_HSP_CoRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_CoRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_CoRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0D_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_DeRing_SC3 ++//**************************************************** ++ unsigned char MST_HSP_DeRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_DeRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_DeRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0F_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0F_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0F_H), 0X03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0F_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_L), 0X0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_20_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Dither_SC3 ++//**************************************************** ++ unsigned char MST_HSP_Dither_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Dither_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Dither_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HnonLinear_SC3 ++//**************************************************** ++ unsigned char MST_HnonLinear_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HnonLinear_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HnonLinear_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_13_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_14_L), 0xFF, 0x7E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_14_H), 0xFF, 0x72/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_15_L), 0xFF, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_15_H), 0x80, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_15_H), 0x7F, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_16_L), 0xFF, 0x21/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_16_H), 0xFF, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// SWDriver ++//**************************************************** ++ unsigned char MST_SWDriver_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SWDriver_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SWDriver_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// SC_End ++//**************************************************** ++ unsigned char MST_SC_End_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SC_End_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SC_End_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ ++ EN_IPTAB_INFO PQ_IPTAB_INFO_Main[]= ++{ ++{*MST_PreSNR_COM_Main, *MST_PreSNR_Main, PQ_IP_PreSNR_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_DNR_COM_Main, *MST_DNR_Main, PQ_IP_DNR_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_DNR_Y_COM_Main, *MST_DNR_Y_Main, PQ_IP_DNR_Y_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_DNR_C_COM_Main, *MST_DNR_C_Main, PQ_IP_DNR_C_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_LDC_COM_Main, *MST_LDC_Main, PQ_IP_LDC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_LDC_422_444_422_COM_Main, *MST_LDC_422_444_422_Main, PQ_IP_LDC_422_444_422_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_NLM_COM_Main, *MST_NLM_Main, PQ_IP_NLM_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422to444_COM_Main, *MST_422to444_Main, PQ_IP_422to444_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_COM_Main, *MST_VIP_Main, PQ_IP_VIP_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_pseudo_COM_Main, *MST_VIP_pseudo_Main, PQ_IP_VIP_pseudo_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LineBuffer_COM_Main, *MST_VIP_LineBuffer_Main, PQ_IP_VIP_LineBuffer_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_HLPF_COM_Main, *MST_VIP_HLPF_Main, PQ_IP_VIP_HLPF_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_HLPF_dither_COM_Main, *MST_VIP_HLPF_dither_Main, PQ_IP_VIP_HLPF_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_VLPF_coef1_COM_Main, *MST_VIP_VLPF_coef1_Main, PQ_IP_VIP_VLPF_coef1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_VLPF_coef2_COM_Main, *MST_VIP_VLPF_coef2_Main, PQ_IP_VIP_VLPF_coef2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_VLPF_dither_COM_Main, *MST_VIP_VLPF_dither_Main, PQ_IP_VIP_VLPF_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_COM_Main, *MST_VIP_Peaking_Main, PQ_IP_VIP_Peaking_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_band_COM_Main, *MST_VIP_Peaking_band_Main, PQ_IP_VIP_Peaking_band_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_adptive_COM_Main, *MST_VIP_Peaking_adptive_Main, PQ_IP_VIP_Peaking_adptive_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_Pcoring_COM_Main, *MST_VIP_Peaking_Pcoring_Main, PQ_IP_VIP_Peaking_Pcoring_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_Pcoring_ad_Y_COM_Main, *MST_VIP_Peaking_Pcoring_ad_Y_Main, PQ_IP_VIP_Peaking_Pcoring_ad_Y_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_gain_COM_Main, *MST_VIP_Peaking_gain_Main, PQ_IP_VIP_Peaking_gain_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_gain_ad_Y_COM_Main, *MST_VIP_Peaking_gain_ad_Y_Main, PQ_IP_VIP_Peaking_gain_ad_Y_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_COM_Main, *MST_VIP_LCE_Main, PQ_IP_VIP_LCE_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_dither_COM_Main, *MST_VIP_LCE_dither_Main, PQ_IP_VIP_LCE_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_setting_COM_Main, *MST_VIP_LCE_setting_Main, PQ_IP_VIP_LCE_setting_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_curve_COM_Main, *MST_VIP_LCE_curve_Main, PQ_IP_VIP_LCE_curve_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_His_range_COM_Main, *MST_VIP_DLC_His_range_Main, PQ_IP_VIP_DLC_His_range_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_COM_Main, *MST_VIP_DLC_Main, PQ_IP_VIP_DLC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_dither_COM_Main, *MST_VIP_DLC_dither_Main, PQ_IP_VIP_DLC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_His_rangeH_COM_Main, *MST_VIP_DLC_His_rangeH_Main, PQ_IP_VIP_DLC_His_rangeH_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_His_rangeV_COM_Main, *MST_VIP_DLC_His_rangeV_Main, PQ_IP_VIP_DLC_His_rangeV_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_PC_COM_Main, *MST_VIP_DLC_PC_Main, PQ_IP_VIP_DLC_PC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_YC_gain_offset_COM_Main, *MST_VIP_YC_gain_offset_Main, PQ_IP_VIP_YC_gain_offset_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_UVC_COM_Main, *MST_VIP_UVC_Main, PQ_IP_VIP_UVC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_full_range_COM_Main, *MST_VIP_FCC_full_range_Main, PQ_IP_VIP_FCC_full_range_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_bdry_dist_COM_Main, *MST_VIP_FCC_bdry_dist_Main, PQ_IP_VIP_FCC_bdry_dist_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T1_COM_Main, *MST_VIP_FCC_T1_Main, PQ_IP_VIP_FCC_T1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T2_COM_Main, *MST_VIP_FCC_T2_Main, PQ_IP_VIP_FCC_T2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T3_COM_Main, *MST_VIP_FCC_T3_Main, PQ_IP_VIP_FCC_T3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T4_COM_Main, *MST_VIP_FCC_T4_Main, PQ_IP_VIP_FCC_T4_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T5_COM_Main, *MST_VIP_FCC_T5_Main, PQ_IP_VIP_FCC_T5_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T6_COM_Main, *MST_VIP_FCC_T6_Main, PQ_IP_VIP_FCC_T6_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T7_COM_Main, *MST_VIP_FCC_T7_Main, PQ_IP_VIP_FCC_T7_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T8_COM_Main, *MST_VIP_FCC_T8_Main, PQ_IP_VIP_FCC_T8_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T9_COM_Main, *MST_VIP_FCC_T9_Main, PQ_IP_VIP_FCC_T9_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_COM_Main, *MST_VIP_IHC_Main, PQ_IP_VIP_IHC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_Ymode_COM_Main, *MST_VIP_IHC_Ymode_Main, PQ_IP_VIP_IHC_Ymode_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_dither_COM_Main, *MST_VIP_IHC_dither_Main, PQ_IP_VIP_IHC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_CRD_SRAM_COM_Main, *MST_VIP_IHC_CRD_SRAM_Main, PQ_IP_VIP_IHC_CRD_SRAM_NUMS_Main, PQ_TABTYPE_VIP_IHC_CRD_SRAM}, ++{*MST_VIP_IHC_SETTING_COM_Main, *MST_VIP_IHC_SETTING_Main, PQ_IP_VIP_IHC_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_COM_Main, *MST_VIP_ICC_Main, PQ_IP_VIP_ICC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_Ymode_COM_Main, *MST_VIP_ICC_Ymode_Main, PQ_IP_VIP_ICC_Ymode_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_dither_COM_Main, *MST_VIP_ICC_dither_Main, PQ_IP_VIP_ICC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_CRD_SRAM_COM_Main, *MST_VIP_ICC_CRD_SRAM_Main, PQ_IP_VIP_ICC_CRD_SRAM_NUMS_Main, PQ_TABTYPE_VIP_ICC_CRD_SRAM}, ++{*MST_VIP_ICC_SETTING_COM_Main, *MST_VIP_ICC_SETTING_Main, PQ_IP_VIP_ICC_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Ymode_Yvalue_ALL_COM_Main, *MST_VIP_Ymode_Yvalue_ALL_Main, PQ_IP_VIP_Ymode_Yvalue_ALL_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Ymode_Yvalue_SETTING_COM_Main, *MST_VIP_Ymode_Yvalue_SETTING_Main, PQ_IP_VIP_Ymode_Yvalue_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IBC_COM_Main, *MST_VIP_IBC_Main, PQ_IP_VIP_IBC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IBC_dither_COM_Main, *MST_VIP_IBC_dither_Main, PQ_IP_VIP_IBC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IBC_SETTING_COM_Main, *MST_VIP_IBC_SETTING_Main, PQ_IP_VIP_IBC_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ACK_COM_Main, *MST_VIP_ACK_Main, PQ_IP_VIP_ACK_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_YCbCr_Clip_COM_Main, *MST_VIP_YCbCr_Clip_Main, PQ_IP_VIP_YCbCr_Clip_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Y_SC1_COM_Main, *MST_VSP_Y_SC1_Main, PQ_IP_VSP_Y_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_C_SC1_COM_Main, *MST_VSP_C_SC1_Main, PQ_IP_VSP_C_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_CoRing_SC1_COM_Main, *MST_VSP_CoRing_SC1_Main, PQ_IP_VSP_CoRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_DeRing_SC1_COM_Main, *MST_VSP_DeRing_SC1_Main, PQ_IP_VSP_DeRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Dither_SC1_COM_Main, *MST_VSP_Dither_SC1_Main, PQ_IP_VSP_Dither_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_PreVBound_SC1_COM_Main, *MST_VSP_PreVBound_SC1_Main, PQ_IP_VSP_PreVBound_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_AntiPAL_filter_SC1_COM_Main, *MST_AntiPAL_filter_SC1_Main, PQ_IP_AntiPAL_filter_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422To444_SC1_COM_Main, *MST_422To444_SC1_Main, PQ_IP_422To444_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Y_SC1_COM_Main, *MST_HSP_Y_SC1_Main, PQ_IP_HSP_Y_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_C_SC1_COM_Main, *MST_HSP_C_SC1_Main, PQ_IP_HSP_C_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_CoRing_SC1_COM_Main, *MST_HSP_CoRing_SC1_Main, PQ_IP_HSP_CoRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_DeRing_SC1_COM_Main, *MST_HSP_DeRing_SC1_Main, PQ_IP_HSP_DeRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Dither_SC1_COM_Main, *MST_HSP_Dither_SC1_Main, PQ_IP_HSP_Dither_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HnonLinear_SC1_COM_Main, *MST_HnonLinear_SC1_Main, PQ_IP_HnonLinear_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_SRAM1_COM_Main, *MST_SRAM1_Main, PQ_IP_SRAM1_NUMS_Main, PQ_TABTYPE_SRAM1}, ++{*MST_SRAM2_COM_Main, *MST_SRAM2_Main, PQ_IP_SRAM2_NUMS_Main, PQ_TABTYPE_SRAM2}, ++{*MST_SRAM3_COM_Main, *MST_SRAM3_Main, PQ_IP_SRAM3_NUMS_Main, PQ_TABTYPE_SRAM3}, ++{*MST_SRAM4_COM_Main, *MST_SRAM4_Main, PQ_IP_SRAM4_NUMS_Main, PQ_TABTYPE_SRAM4}, ++{*MST_C_SRAM1_COM_Main, *MST_C_SRAM1_Main, PQ_IP_C_SRAM1_NUMS_Main, PQ_TABTYPE_C_SRAM1}, ++{*MST_C_SRAM2_COM_Main, *MST_C_SRAM2_Main, PQ_IP_C_SRAM2_NUMS_Main, PQ_TABTYPE_C_SRAM2}, ++{*MST_C_SRAM3_COM_Main, *MST_C_SRAM3_Main, PQ_IP_C_SRAM3_NUMS_Main, PQ_TABTYPE_C_SRAM3}, ++{*MST_C_SRAM4_COM_Main, *MST_C_SRAM4_Main, PQ_IP_C_SRAM4_NUMS_Main, PQ_TABTYPE_C_SRAM4}, ++{*MST_VSP_Y_SC2_COM_Main, *MST_VSP_Y_SC2_Main, PQ_IP_VSP_Y_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_C_SC2_COM_Main, *MST_VSP_C_SC2_Main, PQ_IP_VSP_C_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_CoRing_SC2_COM_Main, *MST_VSP_CoRing_SC2_Main, PQ_IP_VSP_CoRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_DeRing_SC2_COM_Main, *MST_VSP_DeRing_SC2_Main, PQ_IP_VSP_DeRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Dither_SC2_COM_Main, *MST_VSP_Dither_SC2_Main, PQ_IP_VSP_Dither_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_PreVBound_SC2_COM_Main, *MST_VSP_PreVBound_SC2_Main, PQ_IP_VSP_PreVBound_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_AntiPAL_filter_SC2_COM_Main, *MST_AntiPAL_filter_SC2_Main, PQ_IP_AntiPAL_filter_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422To444_SC2_COM_Main, *MST_422To444_SC2_Main, PQ_IP_422To444_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Y_SC2_COM_Main, *MST_HSP_Y_SC2_Main, PQ_IP_HSP_Y_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_C_SC2_COM_Main, *MST_HSP_C_SC2_Main, PQ_IP_HSP_C_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_CoRing_SC2_COM_Main, *MST_HSP_CoRing_SC2_Main, PQ_IP_HSP_CoRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_DeRing_SC2_COM_Main, *MST_HSP_DeRing_SC2_Main, PQ_IP_HSP_DeRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Dither_SC2_COM_Main, *MST_HSP_Dither_SC2_Main, PQ_IP_HSP_Dither_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HnonLinear_SC2_COM_Main, *MST_HnonLinear_SC2_Main, PQ_IP_HnonLinear_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Y_SC3_COM_Main, *MST_VSP_Y_SC3_Main, PQ_IP_VSP_Y_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_C_SC3_COM_Main, *MST_VSP_C_SC3_Main, PQ_IP_VSP_C_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_CoRing_SC3_COM_Main, *MST_VSP_CoRing_SC3_Main, PQ_IP_VSP_CoRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_DeRing_SC3_COM_Main, *MST_VSP_DeRing_SC3_Main, PQ_IP_VSP_DeRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Dither_SC3_COM_Main, *MST_VSP_Dither_SC3_Main, PQ_IP_VSP_Dither_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_PreVBound_SC3_COM_Main, *MST_VSP_PreVBound_SC3_Main, PQ_IP_VSP_PreVBound_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_AntiPAL_filter_SC3_COM_Main, *MST_AntiPAL_filter_SC3_Main, PQ_IP_AntiPAL_filter_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422To444_SC3_COM_Main, *MST_422To444_SC3_Main, PQ_IP_422To444_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Y_SC3_COM_Main, *MST_HSP_Y_SC3_Main, PQ_IP_HSP_Y_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_C_SC3_COM_Main, *MST_HSP_C_SC3_Main, PQ_IP_HSP_C_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_CoRing_SC3_COM_Main, *MST_HSP_CoRing_SC3_Main, PQ_IP_HSP_CoRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_DeRing_SC3_COM_Main, *MST_HSP_DeRing_SC3_Main, PQ_IP_HSP_DeRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Dither_SC3_COM_Main, *MST_HSP_Dither_SC3_Main, PQ_IP_HSP_Dither_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HnonLinear_SC3_COM_Main, *MST_HnonLinear_SC3_Main, PQ_IP_HnonLinear_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_SWDriver_COM_Main, *MST_SWDriver_Main, PQ_IP_SWDriver_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_SC_End_COM_Main, *MST_SC_End_Main, PQ_IP_SC_End_NUMS_Main, PQ_TABTYPE_SCALER}, ++}; ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main.h +new file mode 100644 +index 00000000..df0d0a5f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main.h +@@ -0,0 +1,998 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (; MStar; Confidential; Information; ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//**************************************************** ++// Quality Map CodeGen Version 4.0 ++// 1920 ++// Infinity ++// 8/12/2016 4:59:11 PM ++// 39630.43853 ++//**************************************************** ++ ++#ifndef _INFINITY_MAIN_H_ ++#define _INFINITY_MAIN_H_ ++ ++#define PQ_IP_NUM_Main 115 ++#define PQ_IP_VIP_IHC_CRD_SRAM_SIZE_Main 2178 ++#define PQ_IP_VIP_ICC_CRD_SRAM_SIZE_Main 2178 ++#define PQ_IP_SRAM1_SIZE_Main 320 ++#define PQ_IP_SRAM2_SIZE_Main 320 ++#define PQ_IP_SRAM3_SIZE_Main 640 ++#define PQ_IP_SRAM4_SIZE_Main 640 ++#define PQ_IP_C_SRAM1_SIZE_Main 320 ++#define PQ_IP_C_SRAM2_SIZE_Main 320 ++#define PQ_IP_C_SRAM3_SIZE_Main 320 ++#define PQ_IP_C_SRAM4_SIZE_Main 320 ++ ++typedef enum ++{ ++ #if PQ_QM_ISP ++ QM_FHD_YUV422_Main, //0 ++ #endif ++ QM_INPUTTYPE_NUM_Main, // 1 ++} SC_QUALITY_MAP_INDEX_e_Main; ++ ++typedef enum ++{ ++PQ_IP_PreSNR_Main, //0 ++PQ_IP_DNR_Main, //1 ++PQ_IP_DNR_Y_Main, //2 ++PQ_IP_DNR_C_Main, //3 ++PQ_IP_LDC_Main, //4 ++PQ_IP_LDC_422_444_422_Main, //5 ++PQ_IP_NLM_Main, //6 ++PQ_IP_422to444_Main, //7 ++PQ_IP_VIP_Main, //8 ++PQ_IP_VIP_pseudo_Main, //9 ++PQ_IP_VIP_LineBuffer_Main, //10 ++PQ_IP_VIP_HLPF_Main, //11 ++PQ_IP_VIP_HLPF_dither_Main, //12 ++PQ_IP_VIP_VLPF_coef1_Main, //13 ++PQ_IP_VIP_VLPF_coef2_Main, //14 ++PQ_IP_VIP_VLPF_dither_Main, //15 ++PQ_IP_VIP_Peaking_Main, //16 ++PQ_IP_VIP_Peaking_band_Main, //17 ++PQ_IP_VIP_Peaking_adptive_Main, //18 ++PQ_IP_VIP_Peaking_Pcoring_Main, //19 ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_Main, //20 ++PQ_IP_VIP_Peaking_gain_Main, //21 ++PQ_IP_VIP_Peaking_gain_ad_Y_Main, //22 ++PQ_IP_VIP_LCE_Main, //23 ++PQ_IP_VIP_LCE_dither_Main, //24 ++PQ_IP_VIP_LCE_setting_Main, //25 ++PQ_IP_VIP_LCE_curve_Main, //26 ++PQ_IP_VIP_DLC_His_range_Main, //27 ++PQ_IP_VIP_DLC_Main, //28 ++PQ_IP_VIP_DLC_dither_Main, //29 ++PQ_IP_VIP_DLC_His_rangeH_Main, //30 ++PQ_IP_VIP_DLC_His_rangeV_Main, //31 ++PQ_IP_VIP_DLC_PC_Main, //32 ++PQ_IP_VIP_YC_gain_offset_Main, //33 ++PQ_IP_VIP_UVC_Main, //34 ++PQ_IP_VIP_FCC_full_range_Main, //35 ++PQ_IP_VIP_FCC_bdry_dist_Main, //36 ++PQ_IP_VIP_FCC_T1_Main, //37 ++PQ_IP_VIP_FCC_T2_Main, //38 ++PQ_IP_VIP_FCC_T3_Main, //39 ++PQ_IP_VIP_FCC_T4_Main, //40 ++PQ_IP_VIP_FCC_T5_Main, //41 ++PQ_IP_VIP_FCC_T6_Main, //42 ++PQ_IP_VIP_FCC_T7_Main, //43 ++PQ_IP_VIP_FCC_T8_Main, //44 ++PQ_IP_VIP_FCC_T9_Main, //45 ++PQ_IP_VIP_IHC_Main, //46 ++PQ_IP_VIP_IHC_Ymode_Main, //47 ++PQ_IP_VIP_IHC_dither_Main, //48 ++PQ_IP_VIP_IHC_CRD_SRAM_Main, //49 ++PQ_IP_VIP_IHC_SETTING_Main, //50 ++PQ_IP_VIP_ICC_Main, //51 ++PQ_IP_VIP_ICC_Ymode_Main, //52 ++PQ_IP_VIP_ICC_dither_Main, //53 ++PQ_IP_VIP_ICC_CRD_SRAM_Main, //54 ++PQ_IP_VIP_ICC_SETTING_Main, //55 ++PQ_IP_VIP_Ymode_Yvalue_ALL_Main, //56 ++PQ_IP_VIP_Ymode_Yvalue_SETTING_Main, //57 ++PQ_IP_VIP_IBC_Main, //58 ++PQ_IP_VIP_IBC_dither_Main, //59 ++PQ_IP_VIP_IBC_SETTING_Main, //60 ++PQ_IP_VIP_ACK_Main, //61 ++PQ_IP_VIP_YCbCr_Clip_Main, //62 ++PQ_IP_VSP_Y_SC1_Main, //63 ++PQ_IP_VSP_C_SC1_Main, //64 ++PQ_IP_VSP_CoRing_SC1_Main, //65 ++PQ_IP_VSP_DeRing_SC1_Main, //66 ++PQ_IP_VSP_Dither_SC1_Main, //67 ++PQ_IP_VSP_PreVBound_SC1_Main, //68 ++PQ_IP_AntiPAL_filter_SC1_Main, //69 ++PQ_IP_422To444_SC1_Main, //70 ++PQ_IP_HSP_Y_SC1_Main, //71 ++PQ_IP_HSP_C_SC1_Main, //72 ++PQ_IP_HSP_CoRing_SC1_Main, //73 ++PQ_IP_HSP_DeRing_SC1_Main, //74 ++PQ_IP_HSP_Dither_SC1_Main, //75 ++PQ_IP_HnonLinear_SC1_Main, //76 ++PQ_IP_SRAM1_Main, //77 ++PQ_IP_SRAM2_Main, //78 ++PQ_IP_SRAM3_Main, //79 ++PQ_IP_SRAM4_Main, //80 ++PQ_IP_C_SRAM1_Main, //81 ++PQ_IP_C_SRAM2_Main, //82 ++PQ_IP_C_SRAM3_Main, //83 ++PQ_IP_C_SRAM4_Main, //84 ++PQ_IP_VSP_Y_SC2_Main, //85 ++PQ_IP_VSP_C_SC2_Main, //86 ++PQ_IP_VSP_CoRing_SC2_Main, //87 ++PQ_IP_VSP_DeRing_SC2_Main, //88 ++PQ_IP_VSP_Dither_SC2_Main, //89 ++PQ_IP_VSP_PreVBound_SC2_Main, //90 ++PQ_IP_AntiPAL_filter_SC2_Main, //91 ++PQ_IP_422To444_SC2_Main, //92 ++PQ_IP_HSP_Y_SC2_Main, //93 ++PQ_IP_HSP_C_SC2_Main, //94 ++PQ_IP_HSP_CoRing_SC2_Main, //95 ++PQ_IP_HSP_DeRing_SC2_Main, //96 ++PQ_IP_HSP_Dither_SC2_Main, //97 ++PQ_IP_HnonLinear_SC2_Main, //98 ++PQ_IP_VSP_Y_SC3_Main, //99 ++PQ_IP_VSP_C_SC3_Main, //100 ++PQ_IP_VSP_CoRing_SC3_Main, //101 ++PQ_IP_VSP_DeRing_SC3_Main, //102 ++PQ_IP_VSP_Dither_SC3_Main, //103 ++PQ_IP_VSP_PreVBound_SC3_Main, //104 ++PQ_IP_AntiPAL_filter_SC3_Main, //105 ++PQ_IP_422To444_SC3_Main, //106 ++PQ_IP_HSP_Y_SC3_Main, //107 ++PQ_IP_HSP_C_SC3_Main, //108 ++PQ_IP_HSP_CoRing_SC3_Main, //109 ++PQ_IP_HSP_DeRing_SC3_Main, //110 ++PQ_IP_HSP_Dither_SC3_Main, //111 ++PQ_IP_HnonLinear_SC3_Main, //112 ++PQ_IP_SWDriver_Main, //113 ++PQ_IP_SC_End_Main, //114 ++ } PQ_IPTYPE_Main; ++ ++typedef enum ++{ ++PQ_IP_PreSNR_COM_Main, //0 ++PQ_IP_DNR_COM_Main, //1 ++PQ_IP_DNR_Y_COM_Main, //2 ++PQ_IP_DNR_C_COM_Main, //3 ++PQ_IP_LDC_COM_Main, //4 ++PQ_IP_LDC_422_444_422_COM_Main, //5 ++PQ_IP_NLM_COM_Main, //6 ++PQ_IP_422to444_COM_Main, //7 ++PQ_IP_VIP_COM_Main, //8 ++PQ_IP_VIP_pseudo_COM_Main, //9 ++PQ_IP_VIP_LineBuffer_COM_Main, //10 ++PQ_IP_VIP_HLPF_COM_Main, //11 ++PQ_IP_VIP_HLPF_dither_COM_Main, //12 ++PQ_IP_VIP_VLPF_coef1_COM_Main, //13 ++PQ_IP_VIP_VLPF_coef2_COM_Main, //14 ++PQ_IP_VIP_VLPF_dither_COM_Main, //15 ++PQ_IP_VIP_Peaking_COM_Main, //16 ++PQ_IP_VIP_Peaking_band_COM_Main, //17 ++PQ_IP_VIP_Peaking_adptive_COM_Main, //18 ++PQ_IP_VIP_Peaking_Pcoring_COM_Main, //19 ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_COM_Main, //20 ++PQ_IP_VIP_Peaking_gain_COM_Main, //21 ++PQ_IP_VIP_Peaking_gain_ad_Y_COM_Main, //22 ++PQ_IP_VIP_LCE_COM_Main, //23 ++PQ_IP_VIP_LCE_dither_COM_Main, //24 ++PQ_IP_VIP_LCE_setting_COM_Main, //25 ++PQ_IP_VIP_LCE_curve_COM_Main, //26 ++PQ_IP_VIP_DLC_His_range_COM_Main, //27 ++PQ_IP_VIP_DLC_COM_Main, //28 ++PQ_IP_VIP_DLC_dither_COM_Main, //29 ++PQ_IP_VIP_DLC_His_rangeH_COM_Main, //30 ++PQ_IP_VIP_DLC_His_rangeV_COM_Main, //31 ++PQ_IP_VIP_DLC_PC_COM_Main, //32 ++PQ_IP_VIP_YC_gain_offset_COM_Main, //33 ++PQ_IP_VIP_UVC_COM_Main, //34 ++PQ_IP_VIP_FCC_full_range_COM_Main, //35 ++PQ_IP_VIP_FCC_bdry_dist_COM_Main, //36 ++PQ_IP_VIP_FCC_T1_COM_Main, //37 ++PQ_IP_VIP_FCC_T2_COM_Main, //38 ++PQ_IP_VIP_FCC_T3_COM_Main, //39 ++PQ_IP_VIP_FCC_T4_COM_Main, //40 ++PQ_IP_VIP_FCC_T5_COM_Main, //41 ++PQ_IP_VIP_FCC_T6_COM_Main, //42 ++PQ_IP_VIP_FCC_T7_COM_Main, //43 ++PQ_IP_VIP_FCC_T8_COM_Main, //44 ++PQ_IP_VIP_FCC_T9_COM_Main, //45 ++PQ_IP_VIP_IHC_COM_Main, //46 ++PQ_IP_VIP_IHC_Ymode_COM_Main, //47 ++PQ_IP_VIP_IHC_dither_COM_Main, //48 ++PQ_IP_VIP_IHC_CRD_SRAM_COM_Main, //49 ++PQ_IP_VIP_IHC_SETTING_COM_Main, //50 ++PQ_IP_VIP_ICC_COM_Main, //51 ++PQ_IP_VIP_ICC_Ymode_COM_Main, //52 ++PQ_IP_VIP_ICC_dither_COM_Main, //53 ++PQ_IP_VIP_ICC_CRD_SRAM_COM_Main, //54 ++PQ_IP_VIP_ICC_SETTING_COM_Main, //55 ++PQ_IP_VIP_Ymode_Yvalue_ALL_COM_Main, //56 ++PQ_IP_VIP_Ymode_Yvalue_SETTING_COM_Main, //57 ++PQ_IP_VIP_IBC_COM_Main, //58 ++PQ_IP_VIP_IBC_dither_COM_Main, //59 ++PQ_IP_VIP_IBC_SETTING_COM_Main, //60 ++PQ_IP_VIP_ACK_COM_Main, //61 ++PQ_IP_VIP_YCbCr_Clip_COM_Main, //62 ++PQ_IP_VSP_Y_SC1_COM_Main, //63 ++PQ_IP_VSP_C_SC1_COM_Main, //64 ++PQ_IP_VSP_CoRing_SC1_COM_Main, //65 ++PQ_IP_VSP_DeRing_SC1_COM_Main, //66 ++PQ_IP_VSP_Dither_SC1_COM_Main, //67 ++PQ_IP_VSP_PreVBound_SC1_COM_Main, //68 ++PQ_IP_AntiPAL_filter_SC1_COM_Main, //69 ++PQ_IP_422To444_SC1_COM_Main, //70 ++PQ_IP_HSP_Y_SC1_COM_Main, //71 ++PQ_IP_HSP_C_SC1_COM_Main, //72 ++PQ_IP_HSP_CoRing_SC1_COM_Main, //73 ++PQ_IP_HSP_DeRing_SC1_COM_Main, //74 ++PQ_IP_HSP_Dither_SC1_COM_Main, //75 ++PQ_IP_HnonLinear_SC1_COM_Main, //76 ++PQ_IP_SRAM1_COM_Main, //77 ++PQ_IP_SRAM2_COM_Main, //78 ++PQ_IP_SRAM3_COM_Main, //79 ++PQ_IP_SRAM4_COM_Main, //80 ++PQ_IP_C_SRAM1_COM_Main, //81 ++PQ_IP_C_SRAM2_COM_Main, //82 ++PQ_IP_C_SRAM3_COM_Main, //83 ++PQ_IP_C_SRAM4_COM_Main, //84 ++PQ_IP_VSP_Y_SC2_COM_Main, //85 ++PQ_IP_VSP_C_SC2_COM_Main, //86 ++PQ_IP_VSP_CoRing_SC2_COM_Main, //87 ++PQ_IP_VSP_DeRing_SC2_COM_Main, //88 ++PQ_IP_VSP_Dither_SC2_COM_Main, //89 ++PQ_IP_VSP_PreVBound_SC2_COM_Main, //90 ++PQ_IP_AntiPAL_filter_SC2_COM_Main, //91 ++PQ_IP_422To444_SC2_COM_Main, //92 ++PQ_IP_HSP_Y_SC2_COM_Main, //93 ++PQ_IP_HSP_C_SC2_COM_Main, //94 ++PQ_IP_HSP_CoRing_SC2_COM_Main, //95 ++PQ_IP_HSP_DeRing_SC2_COM_Main, //96 ++PQ_IP_HSP_Dither_SC2_COM_Main, //97 ++PQ_IP_HnonLinear_SC2_COM_Main, //98 ++PQ_IP_VSP_Y_SC3_COM_Main, //99 ++PQ_IP_VSP_C_SC3_COM_Main, //100 ++PQ_IP_VSP_CoRing_SC3_COM_Main, //101 ++PQ_IP_VSP_DeRing_SC3_COM_Main, //102 ++PQ_IP_VSP_Dither_SC3_COM_Main, //103 ++PQ_IP_VSP_PreVBound_SC3_COM_Main, //104 ++PQ_IP_AntiPAL_filter_SC3_COM_Main, //105 ++PQ_IP_422To444_SC3_COM_Main, //106 ++PQ_IP_HSP_Y_SC3_COM_Main, //107 ++PQ_IP_HSP_C_SC3_COM_Main, //108 ++PQ_IP_HSP_CoRing_SC3_COM_Main, //109 ++PQ_IP_HSP_DeRing_SC3_COM_Main, //110 ++PQ_IP_HSP_Dither_SC3_COM_Main, //111 ++PQ_IP_HnonLinear_SC3_COM_Main, //112 ++PQ_IP_SWDriver_COM_Main, //113 ++PQ_IP_SC_End_COM_Main, //114 ++PQ_IP_COM_NUMS_Main ++} PQ_IP_COM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_PreSNR_OFF_Main, ++PQ_IP_PreSNR_NUMS_Main ++} PQ_IP_PreSNR_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_DNR_NR_OFF_Main, ++PQ_IP_DNR_DNR_OFF_Main, ++PQ_IP_DNR_NUMS_Main ++} PQ_IP_DNR_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_DNR_Y_OFF_Main, ++PQ_IP_DNR_Y_NUMS_Main ++} PQ_IP_DNR_Y_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_DNR_C_OFF_Main, ++PQ_IP_DNR_C_NUMS_Main ++} PQ_IP_DNR_C_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_LDC_OFF_Main, ++PQ_IP_LDC_ON_Main, ++PQ_IP_LDC_NUMS_Main ++} PQ_IP_LDC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_LDC_422_444_422_md1434_avg_Main, ++PQ_IP_LDC_422_444_422_NUMS_Main ++} PQ_IP_LDC_422_444_422_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_NLM_OFF_Main, ++PQ_IP_NLM_NUMS_Main ++} PQ_IP_NLM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422to444_OFF_Main, ++PQ_IP_422to444_NUMS_Main ++} PQ_IP_422to444_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_OFF_Main, ++PQ_IP_VIP_NUMS_Main ++} PQ_IP_VIP_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_pseudo_OFF_Main, ++PQ_IP_VIP_pseudo_NUMS_Main ++} PQ_IP_VIP_pseudo_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LineBuffer_OFF_Main, ++PQ_IP_VIP_LineBuffer_NUMS_Main ++} PQ_IP_VIP_LineBuffer_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_HLPF_OFF_Main, ++PQ_IP_VIP_HLPF_NUMS_Main ++} PQ_IP_VIP_HLPF_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_HLPF_dither_OFF_Main, ++PQ_IP_VIP_HLPF_dither_NUMS_Main ++} PQ_IP_VIP_HLPF_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_VLPF_coef1_OFF_Main, ++PQ_IP_VIP_VLPF_coef1_NUMS_Main ++} PQ_IP_VIP_VLPF_coef1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_VLPF_coef2_OFF_Main, ++PQ_IP_VIP_VLPF_coef2_NUMS_Main ++} PQ_IP_VIP_VLPF_coef2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_VLPF_dither_OFF_Main, ++PQ_IP_VIP_VLPF_dither_NUMS_Main ++} PQ_IP_VIP_VLPF_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_OFF_Main, ++PQ_IP_VIP_Peaking_W2_Main, ++PQ_IP_VIP_Peaking_NUMS_Main ++} PQ_IP_VIP_Peaking_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_band_OFF_Main, ++PQ_IP_VIP_Peaking_band_NUMS_Main ++} PQ_IP_VIP_Peaking_band_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_adptive_OFF_Main, ++PQ_IP_VIP_Peaking_adptive_NUMS_Main ++} PQ_IP_VIP_Peaking_adptive_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_Pcoring_OFF_Main, ++PQ_IP_VIP_Peaking_Pcoring_NUMS_Main ++} PQ_IP_VIP_Peaking_Pcoring_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_OFF_Main, ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_NUMS_Main ++} PQ_IP_VIP_Peaking_Pcoring_ad_Y_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_gain_0x10_Main, ++PQ_IP_VIP_Peaking_gain_NUMS_Main ++} PQ_IP_VIP_Peaking_gain_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_gain_ad_Y_OFF_Main, ++PQ_IP_VIP_Peaking_gain_ad_Y_NUMS_Main ++} PQ_IP_VIP_Peaking_gain_ad_Y_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_YC_gain_offset_OFF_Main, ++PQ_IP_VIP_YC_gain_offset_NUMS_Main ++} PQ_IP_VIP_YC_gain_offset_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_OFF_Main, ++PQ_IP_VIP_LCE_NUMS_Main ++} PQ_IP_VIP_LCE_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_dither_OFF_Main, ++PQ_IP_VIP_LCE_dither_NUMS_Main ++} PQ_IP_VIP_LCE_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_setting_S3_Main, ++PQ_IP_VIP_LCE_setting_NUMS_Main ++} PQ_IP_VIP_LCE_setting_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_curve_CV1_Main, ++PQ_IP_VIP_LCE_curve_NUMS_Main ++} PQ_IP_VIP_LCE_curve_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_OFF_Main, ++PQ_IP_VIP_DLC_NUMS_Main ++} PQ_IP_VIP_DLC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_dither_OFF_Main, ++PQ_IP_VIP_DLC_dither_NUMS_Main ++} PQ_IP_VIP_DLC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_His_range_OFF_Main, ++PQ_IP_VIP_DLC_His_range_NUMS_Main ++} PQ_IP_VIP_DLC_His_range_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_His_rangeH_90pa_1920_Main, ++PQ_IP_VIP_DLC_His_rangeH_NUMS_Main ++} PQ_IP_VIP_DLC_His_rangeH_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_His_rangeV_90pa_1920_Main, ++PQ_IP_VIP_DLC_His_rangeV_NUMS_Main ++} PQ_IP_VIP_DLC_His_rangeV_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_PC_OFF_Main, ++PQ_IP_VIP_DLC_PC_NUMS_Main ++} PQ_IP_VIP_DLC_PC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_UVC_OFF_Main, ++PQ_IP_VIP_UVC_NUMS_Main ++} PQ_IP_VIP_UVC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_full_range_OFF_Main, ++PQ_IP_VIP_FCC_full_range_NUMS_Main ++} PQ_IP_VIP_FCC_full_range_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_bdry_dist_OFF_Main, ++PQ_IP_VIP_FCC_bdry_dist_NUMS_Main ++} PQ_IP_VIP_FCC_bdry_dist_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T1_OFF_Main, ++PQ_IP_VIP_FCC_T1_NUMS_Main ++} PQ_IP_VIP_FCC_T1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T2_OFF_Main, ++PQ_IP_VIP_FCC_T2_NUMS_Main ++} PQ_IP_VIP_FCC_T2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T3_OFF_Main, ++PQ_IP_VIP_FCC_T3_NUMS_Main ++} PQ_IP_VIP_FCC_T3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T4_OFF_Main, ++PQ_IP_VIP_FCC_T4_NUMS_Main ++} PQ_IP_VIP_FCC_T4_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T5_OFF_Main, ++PQ_IP_VIP_FCC_T5_NUMS_Main ++} PQ_IP_VIP_FCC_T5_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T6_OFF_Main, ++PQ_IP_VIP_FCC_T6_NUMS_Main ++} PQ_IP_VIP_FCC_T6_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T7_OFF_Main, ++PQ_IP_VIP_FCC_T7_NUMS_Main ++} PQ_IP_VIP_FCC_T7_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T8_OFF_Main, ++PQ_IP_VIP_FCC_T8_NUMS_Main ++} PQ_IP_VIP_FCC_T8_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T9_OFF_Main, ++PQ_IP_VIP_FCC_T9_NUMS_Main ++} PQ_IP_VIP_FCC_T9_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_OFF_Main, ++PQ_IP_VIP_IHC_NUMS_Main ++} PQ_IP_VIP_IHC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_Ymode_OFF_Main, ++PQ_IP_VIP_IHC_Ymode_NUMS_Main ++} PQ_IP_VIP_IHC_Ymode_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_dither_OFF_Main, ++PQ_IP_VIP_IHC_dither_NUMS_Main ++} PQ_IP_VIP_IHC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_CRD_SRAM_15wins3_Main, ++PQ_IP_VIP_IHC_CRD_SRAM_NUMS_Main ++} PQ_IP_VIP_IHC_CRD_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_SETTING_HDMI_HD_Main, ++PQ_IP_VIP_IHC_SETTING_NUMS_Main ++} PQ_IP_VIP_IHC_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_OFF_Main, ++PQ_IP_VIP_ICC_NUMS_Main ++} PQ_IP_VIP_ICC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_Ymode_HDMI_HD_Main, ++PQ_IP_VIP_ICC_Ymode_NUMS_Main ++} PQ_IP_VIP_ICC_Ymode_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_dither_OFF_Main, ++PQ_IP_VIP_ICC_dither_NUMS_Main ++} PQ_IP_VIP_ICC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_CRD_SRAM_15wins3_Main, ++PQ_IP_VIP_ICC_CRD_SRAM_NUMS_Main ++} PQ_IP_VIP_ICC_CRD_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_SETTING_HDMI_HD_Main, ++PQ_IP_VIP_ICC_SETTING_NUMS_Main ++} PQ_IP_VIP_ICC_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Ymode_Yvalue_ALL_Y1_Main, ++PQ_IP_VIP_Ymode_Yvalue_ALL_NUMS_Main ++} PQ_IP_VIP_Ymode_Yvalue_ALL_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Ymode_Yvalue_SETTING_Y2_Main, ++PQ_IP_VIP_Ymode_Yvalue_SETTING_NUMS_Main ++} PQ_IP_VIP_Ymode_Yvalue_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IBC_OFF_Main, ++PQ_IP_VIP_IBC_NUMS_Main ++} PQ_IP_VIP_IBC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IBC_dither_OFF_Main, ++PQ_IP_VIP_IBC_dither_NUMS_Main ++} PQ_IP_VIP_IBC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IBC_SETTING_OFF_Main, ++PQ_IP_VIP_IBC_SETTING_NUMS_Main ++} PQ_IP_VIP_IBC_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ACK_OFF_Main, ++PQ_IP_VIP_ACK_NUMS_Main ++} PQ_IP_VIP_ACK_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_YCbCr_Clip_OFF_Main, ++PQ_IP_VIP_YCbCr_Clip_NUMS_Main ++} PQ_IP_VIP_YCbCr_Clip_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Y_SC1_Bypass_Main, ++PQ_IP_VSP_Y_SC1_NUMS_Main ++} PQ_IP_VSP_Y_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_C_SC1_Bypass_Main, ++PQ_IP_VSP_C_SC1_NUMS_Main ++} PQ_IP_VSP_C_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_CoRing_SC1_OFF_Main, ++PQ_IP_VSP_CoRing_SC1_NUMS_Main ++} PQ_IP_VSP_CoRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_DeRing_SC1_OFF_Main, ++PQ_IP_VSP_DeRing_SC1_NUMS_Main ++} PQ_IP_VSP_DeRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Dither_SC1_OFF_Main, ++PQ_IP_VSP_Dither_SC1_NUMS_Main ++} PQ_IP_VSP_Dither_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_PreVBound_SC1_OFF_Main, ++PQ_IP_VSP_PreVBound_SC1_NUMS_Main ++} PQ_IP_VSP_PreVBound_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_AntiPAL_filter_SC1_OFF_Main, ++PQ_IP_AntiPAL_filter_SC1_NUMS_Main ++} PQ_IP_AntiPAL_filter_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422To444_SC1_ON_Main, ++PQ_IP_422To444_SC1_NUMS_Main ++} PQ_IP_422To444_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Y_SC1_Bypass_Main, ++PQ_IP_HSP_Y_SC1_NUMS_Main ++} PQ_IP_HSP_Y_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_C_SC1_Bypass_Main, ++PQ_IP_HSP_C_SC1_NUMS_Main ++} PQ_IP_HSP_C_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_CoRing_SC1_OFF_Main, ++PQ_IP_HSP_CoRing_SC1_NUMS_Main ++} PQ_IP_HSP_CoRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_DeRing_SC1_OFF_Main, ++PQ_IP_HSP_DeRing_SC1_NUMS_Main ++} PQ_IP_HSP_DeRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Dither_SC1_OFF_Main, ++PQ_IP_HSP_Dither_SC1_NUMS_Main ++} PQ_IP_HSP_Dither_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HnonLinear_SC1_OFF_Main, ++PQ_IP_HnonLinear_SC1_NUMS_Main ++} PQ_IP_HnonLinear_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM1_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G13_Main, ++PQ_IP_SRAM1_NUMS_Main ++} PQ_IP_SRAM1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM2_InvSinc4Tc4p4Fc45Apass01Astop40_Main, ++PQ_IP_SRAM2_NUMS_Main ++} PQ_IP_SRAM2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM3_OFF_Main, ++PQ_IP_SRAM3_NUMS_Main ++} PQ_IP_SRAM3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM4_OFF_Main, ++PQ_IP_SRAM4_NUMS_Main ++} PQ_IP_SRAM4_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM1_C121_Main, ++PQ_IP_C_SRAM1_NUMS_Main ++} PQ_IP_C_SRAM1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM2_C2121_Main, ++PQ_IP_C_SRAM2_NUMS_Main ++} PQ_IP_C_SRAM2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM3_C161_Main, ++PQ_IP_C_SRAM3_NUMS_Main ++} PQ_IP_C_SRAM3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM4_C2121_Main, ++PQ_IP_C_SRAM4_NUMS_Main ++} PQ_IP_C_SRAM4_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Y_SC2_Bypass_Main, ++PQ_IP_VSP_Y_SC2_NUMS_Main ++} PQ_IP_VSP_Y_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_C_SC2_Bypass_Main, ++PQ_IP_VSP_C_SC2_NUMS_Main ++} PQ_IP_VSP_C_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_CoRing_SC2_OFF_Main, ++PQ_IP_VSP_CoRing_SC2_NUMS_Main ++} PQ_IP_VSP_CoRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_DeRing_SC2_OFF_Main, ++PQ_IP_VSP_DeRing_SC2_NUMS_Main ++} PQ_IP_VSP_DeRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Dither_SC2_OFF_Main, ++PQ_IP_VSP_Dither_SC2_NUMS_Main ++} PQ_IP_VSP_Dither_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_PreVBound_SC2_OFF_Main, ++PQ_IP_VSP_PreVBound_SC2_NUMS_Main ++} PQ_IP_VSP_PreVBound_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_AntiPAL_filter_SC2_OFF_Main, ++PQ_IP_AntiPAL_filter_SC2_NUMS_Main ++} PQ_IP_AntiPAL_filter_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422To444_SC2_ON_Main, ++PQ_IP_422To444_SC2_NUMS_Main ++} PQ_IP_422To444_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Y_SC2_Bypass_Main, ++PQ_IP_HSP_Y_SC2_NUMS_Main ++} PQ_IP_HSP_Y_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_C_SC2_Bypass_Main, ++PQ_IP_HSP_C_SC2_Bilinear_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_1_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_2_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_3_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_4_Main, ++PQ_IP_HSP_C_SC2_SRAM_1_4Tap_Main, ++PQ_IP_HSP_C_SC2_SRAM_2_4Tap_Main, ++PQ_IP_HSP_C_SC2_NUMS_Main ++} PQ_IP_HSP_C_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_CoRing_SC2_OFF_Main, ++PQ_IP_HSP_CoRing_SC2_NUMS_Main ++} PQ_IP_HSP_CoRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_DeRing_SC2_OFF_Main, ++PQ_IP_HSP_DeRing_SC2_NUMS_Main ++} PQ_IP_HSP_DeRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Dither_SC2_OFF_Main, ++PQ_IP_HSP_Dither_SC2_NUMS_Main ++} PQ_IP_HSP_Dither_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HnonLinear_SC2_OFF_Main, ++PQ_IP_HnonLinear_SC2_NUMS_Main ++} PQ_IP_HnonLinear_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Y_SC3_Bypass_Main, ++PQ_IP_VSP_Y_SC3_NUMS_Main ++} PQ_IP_VSP_Y_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_C_SC3_Bypass_Main, ++PQ_IP_VSP_C_SC3_NUMS_Main ++} PQ_IP_VSP_C_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_CoRing_SC3_OFF_Main, ++PQ_IP_VSP_CoRing_SC3_NUMS_Main ++} PQ_IP_VSP_CoRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_DeRing_SC3_OFF_Main, ++PQ_IP_VSP_DeRing_SC3_NUMS_Main ++} PQ_IP_VSP_DeRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Dither_SC3_OFF_Main, ++PQ_IP_VSP_Dither_SC3_NUMS_Main ++} PQ_IP_VSP_Dither_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_PreVBound_SC3_OFF_Main, ++PQ_IP_VSP_PreVBound_SC3_NUMS_Main ++} PQ_IP_VSP_PreVBound_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_AntiPAL_filter_SC3_OFF_Main, ++PQ_IP_AntiPAL_filter_SC3_NUMS_Main ++} PQ_IP_AntiPAL_filter_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422To444_SC3_ON_Main, ++PQ_IP_422To444_SC3_NUMS_Main ++} PQ_IP_422To444_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Y_SC3_Bypass_Main, ++PQ_IP_HSP_Y_SC3_NUMS_Main ++} PQ_IP_HSP_Y_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_C_SC3_Bypass_Main, ++PQ_IP_HSP_C_SC3_NUMS_Main ++} PQ_IP_HSP_C_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_CoRing_SC3_OFF_Main, ++PQ_IP_HSP_CoRing_SC3_NUMS_Main ++} PQ_IP_HSP_CoRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_DeRing_SC3_OFF_Main, ++PQ_IP_HSP_DeRing_SC3_NUMS_Main ++} PQ_IP_HSP_DeRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Dither_SC3_OFF_Main, ++PQ_IP_HSP_Dither_SC3_NUMS_Main ++} PQ_IP_HSP_Dither_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HnonLinear_SC3_OFF_Main, ++PQ_IP_HnonLinear_SC3_NUMS_Main ++} PQ_IP_HnonLinear_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SWDriver_OFF_Main, ++PQ_IP_SWDriver_ON_Main, ++PQ_IP_SWDriver_SD_FRC_Main, ++PQ_IP_SWDriver_NUMS_Main ++} PQ_IP_SWDriver_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SC_End_End_Main, ++PQ_IP_SC_End_NUMS_Main ++} PQ_IP_SC_End_Group_Main; ++ ++extern unsigned char MST_SkipRule_IP_Main[PQ_IP_NUM_Main]; ++extern EN_IPTAB_INFO PQ_IPTAB_INFO_Main[]; ++extern unsigned char MST_VIP_IHC_CRD_SRAM_Main[][PQ_IP_VIP_IHC_CRD_SRAM_SIZE_Main]; ++extern unsigned char MST_VIP_ICC_CRD_SRAM_Main[][PQ_IP_VIP_ICC_CRD_SRAM_SIZE_Main]; ++extern unsigned char MST_SRAM1_Main[][PQ_IP_SRAM1_SIZE_Main]; ++extern unsigned char MST_C_SRAM1_Main[][PQ_IP_C_SRAM1_SIZE_Main]; ++extern unsigned char MST_SRAM2_Main[][PQ_IP_SRAM2_SIZE_Main]; ++extern unsigned char MST_C_SRAM2_Main[][PQ_IP_C_SRAM2_SIZE_Main]; ++extern unsigned char QMAP_1920_Main[QM_INPUTTYPE_NUM_Main][PQ_IP_NUM_Main]; ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_1920.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_1920.c +new file mode 100644 +index 00000000..f1f6d3d9 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_1920.c +@@ -0,0 +1,31 @@ ++ ++ unsigned char QMAP_1920_Main[QM_INPUTTYPE_NUM_Main][PQ_IP_NUM_Main]= ++{ ++ #if PQ_QM_ISP ++ {//1920 FHD_YUV422, 0 ++ PQ_IP_PreSNR_OFF_Main, PQ_IP_DNR_NR_OFF_Main, PQ_IP_DNR_Y_OFF_Main, PQ_IP_DNR_C_OFF_Main, PQ_IP_LDC_OFF_Main, ++ PQ_IP_LDC_422_444_422_md1434_avg_Main, PQ_IP_NLM_OFF_Main, PQ_IP_422to444_OFF_Main, PQ_IP_VIP_OFF_Main, PQ_IP_VIP_pseudo_OFF_Main, ++ PQ_IP_VIP_LineBuffer_OFF_Main, PQ_IP_VIP_HLPF_OFF_Main, PQ_IP_VIP_HLPF_dither_OFF_Main, PQ_IP_VIP_VLPF_coef1_OFF_Main, PQ_IP_VIP_VLPF_coef2_OFF_Main, ++ PQ_IP_VIP_VLPF_dither_OFF_Main, PQ_IP_VIP_Peaking_W2_Main, PQ_IP_VIP_Peaking_band_OFF_Main, PQ_IP_VIP_Peaking_adptive_OFF_Main, PQ_IP_VIP_Peaking_Pcoring_OFF_Main, ++ PQ_IP_VIP_Peaking_Pcoring_ad_Y_OFF_Main, PQ_IP_VIP_Peaking_gain_0x10_Main, PQ_IP_VIP_Peaking_gain_ad_Y_OFF_Main, PQ_IP_VIP_LCE_OFF_Main, PQ_IP_VIP_LCE_dither_OFF_Main, ++ PQ_IP_VIP_LCE_setting_S3_Main, PQ_IP_VIP_LCE_curve_CV1_Main, PQ_IP_VIP_DLC_His_range_OFF_Main, PQ_IP_VIP_DLC_OFF_Main, PQ_IP_VIP_DLC_dither_OFF_Main, ++ PQ_IP_VIP_DLC_His_rangeH_90pa_1920_Main, PQ_IP_VIP_DLC_His_rangeV_90pa_1920_Main, PQ_IP_VIP_DLC_PC_OFF_Main, PQ_IP_VIP_YC_gain_offset_OFF_Main, PQ_IP_VIP_UVC_OFF_Main, ++ PQ_IP_VIP_FCC_full_range_OFF_Main, PQ_IP_VIP_FCC_bdry_dist_OFF_Main, PQ_IP_VIP_FCC_T1_OFF_Main, PQ_IP_VIP_FCC_T2_OFF_Main, PQ_IP_VIP_FCC_T3_OFF_Main, ++ PQ_IP_VIP_FCC_T4_OFF_Main, PQ_IP_VIP_FCC_T5_OFF_Main, PQ_IP_VIP_FCC_T6_OFF_Main, PQ_IP_VIP_FCC_T7_OFF_Main, PQ_IP_VIP_FCC_T8_OFF_Main, ++ PQ_IP_VIP_FCC_T9_OFF_Main, PQ_IP_VIP_IHC_OFF_Main, PQ_IP_VIP_IHC_Ymode_OFF_Main, PQ_IP_VIP_IHC_dither_OFF_Main, PQ_IP_VIP_IHC_CRD_SRAM_15wins3_Main, ++ PQ_IP_VIP_IHC_SETTING_HDMI_HD_Main, PQ_IP_VIP_ICC_OFF_Main, PQ_IP_VIP_ICC_Ymode_HDMI_HD_Main, PQ_IP_VIP_ICC_dither_OFF_Main, PQ_IP_VIP_ICC_CRD_SRAM_15wins3_Main, ++ PQ_IP_VIP_ICC_SETTING_HDMI_HD_Main, PQ_IP_VIP_Ymode_Yvalue_ALL_Y1_Main, PQ_IP_VIP_Ymode_Yvalue_SETTING_Y2_Main, PQ_IP_VIP_IBC_OFF_Main, PQ_IP_VIP_IBC_dither_OFF_Main, ++ PQ_IP_VIP_IBC_SETTING_OFF_Main, PQ_IP_VIP_ACK_OFF_Main, PQ_IP_VIP_YCbCr_Clip_OFF_Main, PQ_IP_VSP_Y_SC1_Bypass_Main, PQ_IP_VSP_C_SC1_Bypass_Main, ++ PQ_IP_VSP_CoRing_SC1_OFF_Main, PQ_IP_VSP_DeRing_SC1_OFF_Main, PQ_IP_VSP_Dither_SC1_OFF_Main, PQ_IP_VSP_PreVBound_SC1_OFF_Main, PQ_IP_AntiPAL_filter_SC1_OFF_Main, ++ PQ_IP_422To444_SC1_ON_Main, PQ_IP_HSP_Y_SC1_Bypass_Main, PQ_IP_HSP_C_SC1_Bypass_Main, PQ_IP_HSP_CoRing_SC1_OFF_Main, PQ_IP_HSP_DeRing_SC1_OFF_Main, ++ PQ_IP_HSP_Dither_SC1_OFF_Main, PQ_IP_HnonLinear_SC1_OFF_Main, PQ_IP_SRAM1_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G13_Main, PQ_IP_SRAM2_InvSinc4Tc4p4Fc45Apass01Astop40_Main, PQ_IP_SRAM3_OFF_Main, ++ PQ_IP_SRAM4_OFF_Main, PQ_IP_C_SRAM1_C121_Main, PQ_IP_C_SRAM2_C2121_Main, PQ_IP_C_SRAM3_C161_Main, PQ_IP_C_SRAM4_C2121_Main, ++ PQ_IP_VSP_Y_SC2_Bypass_Main, PQ_IP_VSP_C_SC2_Bypass_Main, PQ_IP_VSP_CoRing_SC2_OFF_Main, PQ_IP_VSP_DeRing_SC2_OFF_Main, PQ_IP_VSP_Dither_SC2_OFF_Main, ++ PQ_IP_VSP_PreVBound_SC2_OFF_Main, PQ_IP_AntiPAL_filter_SC2_OFF_Main, PQ_IP_422To444_SC2_ON_Main, PQ_IP_HSP_Y_SC2_Bypass_Main, PQ_IP_HSP_C_SC2_Bypass_Main, ++ PQ_IP_HSP_CoRing_SC2_OFF_Main, PQ_IP_HSP_DeRing_SC2_OFF_Main, PQ_IP_HSP_Dither_SC2_OFF_Main, PQ_IP_HnonLinear_SC2_OFF_Main, PQ_IP_VSP_Y_SC3_Bypass_Main, ++ PQ_IP_VSP_C_SC3_Bypass_Main, PQ_IP_VSP_CoRing_SC3_OFF_Main, PQ_IP_VSP_DeRing_SC3_OFF_Main, PQ_IP_VSP_Dither_SC3_OFF_Main, PQ_IP_VSP_PreVBound_SC3_OFF_Main, ++ PQ_IP_AntiPAL_filter_SC3_OFF_Main, PQ_IP_422To444_SC3_ON_Main, PQ_IP_HSP_Y_SC3_Bypass_Main, PQ_IP_HSP_C_SC3_Bypass_Main, PQ_IP_HSP_CoRing_SC3_OFF_Main, ++ PQ_IP_HSP_DeRing_SC3_OFF_Main, PQ_IP_HSP_Dither_SC3_OFF_Main, PQ_IP_HnonLinear_SC3_OFF_Main, PQ_IP_SWDriver_ON_Main, PQ_IP_SC_End_End_Main, ++ }, ++ #endif ++}; +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_1920_GRule.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_1920_GRule.c +new file mode 100644 +index 00000000..e7fcd0cc +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_1920_GRule.c +@@ -0,0 +1,8 @@ ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ unsigned char MST_GRule_1920_DYNAMIC_CONTRAST_Main[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_Main]= ++{ ++ PQ_GRule_DYNAMIC_CONTRAST_Off_Main, ++ PQ_GRule_DYNAMIC_CONTRAST_On_Main, ++}; ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_GRule.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_GRule.c +new file mode 100644 +index 00000000..6e035057 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_GRule.c +@@ -0,0 +1,24 @@ ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ unsigned char MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main[PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]= ++{ ++ PQ_IP_VIP_DLC_Main, ++}; ++#endif ++ ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ unsigned char MST_GRule_DYNAMIC_CONTRAST_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]= ++{ ++ #if PQ_QM_ISP ++ {//FHD_YUV422, 0 ++ {//Off ++ PQ_IP_VIP_DLC_OFF_Main, ++ }, ++ {//On ++ PQ_IP_VIP_DLC_OFF_Main, ++ }, ++ }, ++ #endif ++}; ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_GRule.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_GRule.h +new file mode 100644 +index 00000000..b5795054 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_GRule.h +@@ -0,0 +1,48 @@ ++#define PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 1 ++#define PQ_GRULE_DEFINE_AUTO_GEN 1 ++#if (PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE) ++typedef enum ++{ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ PQ_GRule_DYNAMIC_CONTRAST_Main, ++#endif ++ ++} ++MST_GRule_Index_Main; ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++typedef enum ++{ ++ PQ_GRule_DYNAMIC_CONTRAST_Off_Main, ++ PQ_GRule_DYNAMIC_CONTRAST_On_Main, ++} ++MST_GRule_DYNAMIC_CONTRAST_Index_Main; ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++typedef enum ++{ ++ PQ_GRule_Lvl_DYNAMIC_CONTRAST_Off_Main, ++ PQ_GRule_Lvl_DYNAMIC_CONTRAST_On_Main, ++} ++MST_GRule_DYNAMIC_CONTRAST_LvL_Index_Main; ++#endif ++ ++ ++#define PQ_GRULE_RULE_NUM_Main 1 ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++#define PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main 1 ++#define PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main 2 ++#define PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_Main 2 ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++extern unsigned char MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main[PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]; ++extern unsigned char MST_GRule_DYNAMIC_CONTRAST_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]; ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++extern unsigned char MST_GRule_1920_DYNAMIC_CONTRAST_Main[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_Main]; ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_HSPRule.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_HSPRule.c +new file mode 100644 +index 00000000..5b99a066 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_HSPRule.c +@@ -0,0 +1,84 @@ ++ ++ unsigned char MST_HSPRule_IP_Index_Main[PQ_HSPRule_IP_NUM_Main]= ++{ ++ PQ_IP_HSP_Y_SC1_Main, ++ PQ_IP_HSP_C_SC1_Main, ++ PQ_IP_SRAM2_Main, ++}; ++ ++ ++ unsigned char MST_HSPRule_Array_Main[PQ_HSPRule_NUM_Main][PQ_HSPRule_IP_NUM_Main]= ++{ ++ {//PreV_ScalingDown_Interlace, 0 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//PreV_ScalingDown_Progressive, 1 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_YUV, 2 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_RGB, 3 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_YUV, 4 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_RGB, 5 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_YUV, 6 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_RGB, 7 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_YUV, 8 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_RGB, 9 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_YUV, 10 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_RGB, 11 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_YUV, 12 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_RGB, 13 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_YUV, 14 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_RGB, 15 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_YUV, 16 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_RGB, 17 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_YUV, 18 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_RGB, 19 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_YUV, 20 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_RGB, 21 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_YUV, 22 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_RGB, 23 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++}; +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_HSPRule.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_HSPRule.h +new file mode 100644 +index 00000000..1f0fd410 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_HSPRule.h +@@ -0,0 +1,35 @@ ++#define PQ_HSPRule_ID_Main 0 ++#define PQ_HSPRule_IP_NUM_Main 3 ++#define PQ_HSPRule_NUM_Main 24 ++ ++ ++typedef enum ++{ ++PQ_HSPRule_PreV_ScalingDown_Interlace_Main, ++PQ_HSPRule_PreV_ScalingDown_Progressive_Main, ++PQ_HSPRule_ScalingDown_00x_YUV_Main, ++PQ_HSPRule_ScalingDown_00x_RGB_Main, ++PQ_HSPRule_ScalingDown_01x_YUV_Main, ++PQ_HSPRule_ScalingDown_01x_RGB_Main, ++PQ_HSPRule_ScalingDown_02x_YUV_Main, ++PQ_HSPRule_ScalingDown_02x_RGB_Main, ++PQ_HSPRule_ScalingDown_03x_YUV_Main, ++PQ_HSPRule_ScalingDown_03x_RGB_Main, ++PQ_HSPRule_ScalingDown_04x_YUV_Main, ++PQ_HSPRule_ScalingDown_04x_RGB_Main, ++PQ_HSPRule_ScalingDown_05x_YUV_Main, ++PQ_HSPRule_ScalingDown_05x_RGB_Main, ++PQ_HSPRule_ScalingDown_06x_YUV_Main, ++PQ_HSPRule_ScalingDown_06x_RGB_Main, ++PQ_HSPRule_ScalingDown_07x_YUV_Main, ++PQ_HSPRule_ScalingDown_07x_RGB_Main, ++PQ_HSPRule_ScalingDown_08x_YUV_Main, ++PQ_HSPRule_ScalingDown_08x_RGB_Main, ++PQ_HSPRule_ScalingDown_09x_YUV_Main, ++PQ_HSPRule_ScalingDown_09x_RGB_Main, ++PQ_HSPRule_ScalingDown_10x_YUV_Main, ++PQ_HSPRule_ScalingDown_10x_RGB_Main, ++} ++MST_HSPRule_Index_Main; ++extern unsigned char MST_HSPRule_IP_Index_Main[PQ_HSPRule_IP_NUM_Main]; ++extern unsigned char MST_HSPRule_Array_Main[PQ_HSPRule_NUM_Main][PQ_HSPRule_IP_NUM_Main]; +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_VSPRule.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_VSPRule.c +new file mode 100644 +index 00000000..a06e045d +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_VSPRule.c +@@ -0,0 +1,84 @@ ++ ++ unsigned char MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]= ++{ ++ PQ_IP_VSP_Y_SC1_Main, ++ PQ_IP_VSP_C_SC1_Main, ++ PQ_IP_SRAM1_Main, ++}; ++ ++ ++ unsigned char MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]= ++{ ++ {//PreV_ScalingDown_Interlace, 0 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//PreV_ScalingDown_Progressive, 1 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_YUV, 2 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_RGB, 3 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_YUV, 4 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_RGB, 5 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_YUV, 6 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_RGB, 7 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_YUV, 8 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_RGB, 9 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_YUV, 10 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_RGB, 11 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_YUV, 12 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_RGB, 13 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_YUV, 14 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_RGB, 15 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_YUV, 16 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_RGB, 17 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_YUV, 18 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_RGB, 19 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_YUV, 20 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_RGB, 21 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_YUV, 22 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_RGB, 23 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++}; +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_VSPRule.h b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_VSPRule.h +new file mode 100644 +index 00000000..d600dcfc +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_Main_VSPRule.h +@@ -0,0 +1,35 @@ ++#define PQ_VSPRule_ID_Main 1 ++#define PQ_VSPRule_IP_NUM_Main 3 ++#define PQ_VSPRule_NUM_Main 24 ++ ++ ++typedef enum ++{ ++PQ_VSPRule_PreV_ScalingDown_Interlace_Main, ++PQ_VSPRule_PreV_ScalingDown_Progressive_Main, ++PQ_VSPRule_ScalingDown_00x_YUV_Main, ++PQ_VSPRule_ScalingDown_00x_RGB_Main, ++PQ_VSPRule_ScalingDown_01x_YUV_Main, ++PQ_VSPRule_ScalingDown_01x_RGB_Main, ++PQ_VSPRule_ScalingDown_02x_YUV_Main, ++PQ_VSPRule_ScalingDown_02x_RGB_Main, ++PQ_VSPRule_ScalingDown_03x_YUV_Main, ++PQ_VSPRule_ScalingDown_03x_RGB_Main, ++PQ_VSPRule_ScalingDown_04x_YUV_Main, ++PQ_VSPRule_ScalingDown_04x_RGB_Main, ++PQ_VSPRule_ScalingDown_05x_YUV_Main, ++PQ_VSPRule_ScalingDown_05x_RGB_Main, ++PQ_VSPRule_ScalingDown_06x_YUV_Main, ++PQ_VSPRule_ScalingDown_06x_RGB_Main, ++PQ_VSPRule_ScalingDown_07x_YUV_Main, ++PQ_VSPRule_ScalingDown_07x_RGB_Main, ++PQ_VSPRule_ScalingDown_08x_YUV_Main, ++PQ_VSPRule_ScalingDown_08x_RGB_Main, ++PQ_VSPRule_ScalingDown_09x_YUV_Main, ++PQ_VSPRule_ScalingDown_09x_RGB_Main, ++PQ_VSPRule_ScalingDown_10x_YUV_Main, ++PQ_VSPRule_ScalingDown_10x_RGB_Main, ++} ++MST_VSPRule_Index_Main; ++extern unsigned char MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]; ++extern unsigned char MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]; +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_QualityMap_Simplify.xls b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_QualityMap_Simplify.xls +new file mode 100644 +index 00000000..e6dff655 +Binary files /dev/null and b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/include/sc/Infinity_QualityMap_Simplify.xls differ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/hal/mhal_pq.c b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/mhal_pq.c +new file mode 100644 +index 00000000..01194ac4 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/hal/mhal_pq.c +@@ -0,0 +1,608 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// $Change: 617839 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define MHAL_PQ_C ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg_utility2.h" ++#include "hwreg.h" ++#include "drvPQ_Define.h" ++ ++#include "Infinity_Main.h" // table config parameter ++ ++ ++#include "drvPQ_Datatypes.h" ++#include "mhal_pq.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++MS_U32 PQ_RIU_BASE; ++ ++// Put this function here because hwreg_utility2 only for hal. ++void Hal_PQ_init_riu_base(MS_U32 u32riu_base) ++{ ++ PQ_RIU_BASE = u32riu_base; ++} ++ ++#if (PQ_ENABLE_UNUSED_FUNC) ++ ++MS_U8 Hal_PQ_get_sync_flag(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++ ++MS_U8 Hal_PQ_get_input_vsync_value(PQ_WIN ePQWin) ++{ ++ return (Hal_PQ_get_sync_flag(ePQWin) & 0x04) ? 1:0; ++} ++ ++MS_U8 Hal_PQ_get_output_vsync_value(PQ_WIN ePQWin) ++{ ++ return (Hal_PQ_get_sync_flag(ePQWin) & 0x01) ? 1 : 0; ++} ++ ++MS_U8 Hal_PQ_get_input_vsync_polarity(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_memfmt_doublebuffer(PQ_WIN ePQWin, MS_BOOL bEn) ++{ ++ ++} ++#endif ++ ++void Hal_PQ_set_sourceidx(PQ_WIN ePQWin, MS_U16 u16Idx) ++{ ++ ++} ++ ++#if (PQ_ENABLE_UNUSED_FUNC) ++ ++void Hal_PQ_set_mem_fmt(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask) ++{ ++ ++} ++ ++void Hal_PQ_set_mem_fmt_en(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask) ++{ ++ ++} ++ ++void Hal_PQ_set_420upSample(PQ_WIN ePQWin, MS_U16 u16value) ++{ ++ ++} ++ ++void Hal_PQ_set_force_y_motion(PQ_WIN ePQWin, MS_U16 u16value) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_force_y_motion(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_force_c_motion(PQ_WIN ePQWin, MS_U16 u16value) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_force_c_motion(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_dipf_temporal(PQ_WIN ePQWin, MS_U16 u16val) ++{ ++} ++ ++MS_U16 Hal_PQ_get_dipf_temporal(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_dipf_spatial(PQ_WIN ePQWin, MS_U16 u16val) ++{ ++} ++ ++MS_U8 Hal_PQ_get_dipf_spatial(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_vsp_sram_filter(PQ_WIN ePQWin, MS_U8 u8vale) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_vsp_sram_filter(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_dnr(PQ_WIN ePQWin, MS_U8 u8val) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_dnr(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++ ++void Hal_PQ_set_presnr(PQ_WIN ePQWin, MS_U8 u8val) ++{ ++} ++ ++MS_U8 Hal_PQ_get_presnr(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_film(PQ_WIN ePQWin, MS_U16 u16val) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_film(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++#endif ++ ++void Hal_PQ_set_yc_sram(MS_U8 enID, MS_U8 u8sramtype, void *pData) ++{ ++ MS_U32 u32reg_41, u32reg_42, u32reg_43; ++ MS_U32 u32Addr; ++ MS_U8 u8Ramcode[10]; ++ MS_U16 u16IdxBase = 0; ++ MS_U16 i, j, x; ++ MS_BOOL bC_SRAM; ++ ++#ifdef C3_SIM ++ return; ++#endif ++ ++ if(enID == FILTER_SRAM_SC2) ++ { ++ u32reg_41 = REG_SCL_HVSP1_41_L; ++ u32reg_42 = REG_SCL_HVSP1_42_L; ++ u32reg_43 = REG_SCL_HVSP1_43_L; ++ } ++ else if(enID == FILTER_SRAM_SC3) ++ { ++ u32reg_41 = REG_SCL_HVSP2_41_L; ++ u32reg_42 = REG_SCL_HVSP2_43_L; ++ u32reg_43 = REG_SCL_HVSP2_43_L; ++ } ++ else ++ { ++ u32reg_41 = REG_SCL_HVSP0_41_L; ++ u32reg_42 = REG_SCL_HVSP0_42_L; ++ u32reg_43 = REG_SCL_HVSP0_43_L; ++ } ++ ++ bC_SRAM = u8sramtype >= SC_FILTER_C_SRAM1 ? TRUE : FALSE; ++ ++ if(u8sramtype == SC_FILTER_Y_SRAM1 || u8sramtype == SC_FILTER_C_SRAM1) ++ { ++ u16IdxBase = 0x00; ++ } ++ else if(u8sramtype == SC_FILTER_Y_SRAM2 || u8sramtype == SC_FILTER_C_SRAM2) ++ { ++ u16IdxBase = 0x40; ++ } ++ else if(u8sramtype == SC_FILTER_Y_SRAM3 || u8sramtype == SC_FILTER_C_SRAM3) ++ { ++ u16IdxBase = 0x80; ++ } ++ else ++ { ++ u16IdxBase = 0xC0; ++ } ++ ++ u32Addr = (MS_U32)pData; ++ ++ W2BYTEMSK(u32reg_41, bC_SRAM ? BIT1 : BIT0, BIT1|BIT0); // reg_cram_rw_en ++ ++ for(i=0; i<64; i++) ++ { ++ while(MApi_XC_R2BYTE(u32reg_41) & BIT8); ++ j=i*5; ++ ++ MApi_XC_W2BYTEMSK(u32reg_42,(i|u16IdxBase), 0x00FF); ++ for ( x=0;x<5;x++ ) ++ { ++ u8Ramcode[x] = *((MS_U8 *)(u32Addr + (j+x))); ++ } ++ ++ MApi_XC_W2BYTEMSK(u32reg_43+0x00, (((MS_U16)u8Ramcode[1])<<8|(MS_U16)u8Ramcode[0]), 0xFFFF); ++ MApi_XC_W2BYTEMSK(u32reg_43+0x02, (((MS_U16)u8Ramcode[3])<<8|(MS_U16)u8Ramcode[2]), 0xFFFF); ++ MApi_XC_W2BYTEMSK(u32reg_43+0x04, ((MS_U16)u8Ramcode[4]), 0x00FF); ++ ++ ++ MApi_XC_W2BYTEMSK(u32reg_41, BIT8, BIT8); ++ } ++} ++ ++void Hal_PQ_set_sram_color_index_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ //ToDo ++ ++} ++ ++void Hal_PQ_set_sram_color_gain_snr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ ++} ++ ++ ++void Hal_PQ_set_sram_color_gain_dnr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ ++} ++ ++#define ICC_H_SIZE 32 ++#define ICC_V_SIZE 32 ++void Hal_PQ_set_sram_icc_crd_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ MS_U16 i; ++ MS_U16 u16Ramcode_L,u16Ramcode_H; ++ MS_U16 u16Ramcode; ++ MS_U32 u32Addr; ++ MS_U32 u32BK18_78, u32BK18_79, u32BK18_7A; ++ ++ if(u8sramtype != SC_FILTER_SRAM_ICC_CRD) ++ { ++ return; ++ } ++ ++ if(ePQWin == PQ_MAIN_WINDOW) ++ { ++ u32BK18_78 = REG_VIP_ACE2_78_L; ++ u32BK18_79 = REG_VIP_ACE2_79_L; ++ u32BK18_7A = REG_VIP_ACE2_7A_L; ++ } ++ else ++ { ++ return; ++ } ++ ++ u32Addr = (MS_U32)pData; ++ ++ MApi_XC_W2BYTEMSK(u32BK18_78, BIT(0), BIT(0)); // io_en disable ++ ++ for(i=0; i<(ICC_H_SIZE*ICC_V_SIZE); i++) ++ { ++ u16Ramcode_L = *((MS_U8 *)(u32Addr + (2*i))); ++ u16Ramcode_H = *((MS_U8 *)(u32Addr + (2*i+1))); ++ u16Ramcode = ((u16Ramcode_H & 0x01)<<8)+u16Ramcode_L; ++ ++ //while (MApi_XC_R2BYTE(u32BK18_7A) & BIT(15)); ++ MApi_XC_W2BYTEMSK(u32BK18_79, i, 0x03FF); // address ++ MApi_XC_W2BYTEMSK(u32BK18_7A, (u16Ramcode & 0x1FF), 0x01FF); //data[8:0] ++ MApi_XC_W2BYTEMSK(u32BK18_7A, BIT(15), BIT(15)); // io_w enable ++ ++ } ++ ++ MApi_XC_W2BYTEMSK(u32BK18_78, 0, BIT(0)); // io_en enable ++} ++ ++ ++#define IHC_H_SIZE 33 ++#define IHC_V_SIZE 33 ++#define BUF_BYTE_SIZE (IHC_H_SIZE*IHC_V_SIZE) ++#define MAX_SRAM_SIZE 0x124 ++ ++#define SRAM1_IHC_COUNT 289//81 ++#define SRAM2_IHC_COUNT 272//72 ++#define SRAM3_IHC_COUNT 272//72 ++#define SRAM4_IHC_COUNT 256//64 ++ ++#define SRAM1_IHC_OFFSET 0 ++#define SRAM2_IHC_OFFSET SRAM1_IHC_COUNT ++#define SRAM3_IHC_OFFSET (SRAM2_IHC_OFFSET + SRAM2_IHC_COUNT) ++#define SRAM4_IHC_OFFSET (SRAM3_IHC_OFFSET + SRAM3_IHC_COUNT) ++ ++#define SRAM_IHC_TOTAL_COUNT SRAM1_IHC_COUNT + SRAM2_IHC_COUNT + SRAM3_IHC_COUNT + SRAM4_IHC_COUNT ++ ++ ++void _Hal_PQ_set_sram_ihc_crd_table(PQ_WIN ePQWin, MS_U16 *pBuf, MS_U8 u8SRAM_Idx, MS_U16 u16Cnt) ++{ ++ MS_U16 i; ++ MS_U32 u32BK18_7C, u32BK18_7D, u32BK18_7E; ++ ++ if(u8SRAM_Idx > 3) ++ { ++ u8SRAM_Idx = 0; ++ } ++ ++ if(ePQWin == PQ_MAIN_WINDOW) ++ { ++ u32BK18_7C = REG_VIP_ACE2_7C_L; ++ u32BK18_7D = REG_VIP_ACE2_7D_L; ++ u32BK18_7E = REG_VIP_ACE2_7E_L; ++ } ++ else ++ { ++ return; ++ } ++ ++ ++ MApi_XC_W2BYTEMSK(u32BK18_7C, BIT(0), BIT(0)); // io_en disable ++ MApi_XC_W2BYTEMSK(u32BK18_7C, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select ++ ++ for(i=0; i u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hup_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_444_PC_Hup_Vno_Main; ++ } ++ } ++ else if (u16Input_HSize > u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hdown_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hdown_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_444_PC_Hdown_Vno_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hno_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hno_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_444_PC_Hno_Vno_Main; ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceHDMI(enInputSourceType) ++ #if(PQ_ENABLE_UNUSED_FUNC) ++ && QM_HDMIPC_COLORYUV422(eWindow) ++ #endif ++ ) ++ { ++#if (PQ_QM_HDMI_PC) ++ // PC YUV422 ++ if (u16Input_HSize < u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hup_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hup_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_422_PC_Hup_Vno_Main; ++ } ++ } ++ else if (u16Input_HSize > u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hdown_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hdown_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_422_PC_Hdown_Vno_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hno_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hno_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_422_PC_Hno_Vno_Main; ++ } ++ } ++#endif ++ } ++ else //(QM_HDMIPC_COLORRGB(eWindow)) & default ++ { ++#if (PQ_QM_PC) ++ // PC RGB ++ if (u16Input_HSize < u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vno_Main; ++ } ++ } ++ else if (u16Input_HSize > u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vno_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_Main; ++ } ++ } ++#endif ++ } ++ } ++ else if (QM_IsSourceHDMI(enInputSourceType) ++#if ENABLE_VGA_EIA_TIMING ++ || QM_IsSourceVGA(enInputSourceType) //interlace VGA comes here ++#endif ++ ) ++ { ++#if (PQ_QM_HMDI) ++#if 0//debug message ++ if(QM_HDMIPC_COLORRGB(eWindow)) ++ printf("HDMI RGB\n"); ++ else if(QM_HDMIPC_COLORYUV444(eWindow)) ++ printf("HDMI YUV 444\n"); ++ else ++ printf("HDMI YUV 422\n"); ++#endif ++ if( QM_IsSourceHDMI(enInputSourceType) && QM_HDMIPC_COLORRGB(eWindow) && ++ (MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) && (!bIsInterlaced)) ++ { ++ // HDMI RGB progressive ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_Main; ++ } ++ else if( QM_IsSourceHDMI(enInputSourceType) && QM_HDMIPC_COLORYUV444(eWindow) && ++ (MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) && (!bIsInterlaced)) ++ { ++ // HDMI YUV444 progressive ++ u16SrcType = QM_HDMI_444_PC_Hno_Vno_Main; ++ } ++ else ++ { ++ // HDMI ++ if ((u16Input_HSize < 800) && (u16Input_VSize < 500)) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_HDMI_480i_Main; ++ else ++ u16SrcType = QM_HDMI_480p_Main; ++ } ++ else if ((u16Input_HSize < 800) && (u16Input_VSize < 600)) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_HDMI_576i_Main; ++ else ++ u16SrcType = QM_HDMI_576p_Main; ++ } ++ else if ((u16Input_HSize < 1300) && (u16Input_VSize < 800) && (!bIsInterlaced)) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_HDMI_720p_60hz_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_HDMI_720p_50hz_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_720p_24hz_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_HDMI_1080i_60hz_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_1080i_50hz_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_HDMI_1080p_60hz_Main; ++ } ++ else if(u16Input_VFreq > 450) ++ { ++ u16SrcType = QM_HDMI_1080p_50hz_Main; ++ } ++ else // Other timing ++ { ++ u16SrcType = QM_HDMI_1080p_24hz_Main; ++ } ++ } ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceYPbPr(enInputSourceType)) ++ { ++#if (PQ_QM_YPBPR) ++ if( QM_IsSourceYPbPr(enInputSourceType) && ++ (MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) && (!bIsInterlaced)) ++ { ++ // YUV444 progressive ++ u16SrcType = QM_HDMI_444_PC_Hno_Vno_Main; ++ } ++ else if (QM_IsYPbPr_720x480_60I(eWindow)){ ++ u16SrcType = QM_YPbPr_480i_Main; ++ } ++ else if (QM_IsYPbPr_720x480_60P(eWindow)){ ++ u16SrcType = QM_YPbPr_480p_Main; ++ } ++ else if (QM_IsYPbPr_720x576_50I(eWindow)){ ++ u16SrcType = QM_YPbPr_576i_Main; ++ } ++ else if (QM_IsYPbPr_720x576_50P(eWindow)){ ++ u16SrcType = QM_YPbPr_576p_Main; ++ } ++ else if (QM_IsYPbPr_1280x720_50P(eWindow)){ ++ u16SrcType = QM_YPbPr_720p_50hz_Main; ++ } ++ else if (QM_IsYPbPr_1280x720_60P(eWindow)){ ++ u16SrcType = QM_YPbPr_720p_60hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_50I(eWindow)){ ++ u16SrcType = QM_YPbPr_1080i_50hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_60I(eWindow)){ ++ u16SrcType = QM_YPbPr_1080i_60hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_24P(eWindow) || QM_IsYPbPr_1920x1080_30P(eWindow) || QM_IsYPbPr_1920x1080_25P(eWindow) ){ ++ u16SrcType = QM_YPbPr_1080p_24hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_50P(eWindow)){ ++ u16SrcType = QM_YPbPr_1080p_50hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_60P(eWindow)){ ++ u16SrcType = QM_YPbPr_1080p_60hz_Main; ++ } ++ else { ++ u16SrcType = QM_YPbPr_720p_24hz_Main; ++ } ++#endif ++ } ++ else if(QM_IsSrource656(enInputSourceType)) ++ { ++#if (PQ_QM_CVBS) ++ if(u16Input_VSize <= 480) ++ { ++ if(bIsInterlaced) ++ { ++ u16SrcType = QM_HDMI_480i_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_480p_Main; ++ } ++ } ++ else ++ { ++ if(bIsInterlaced) ++ { ++ u16SrcType = QM_HDMI_576i_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_576p_Main; ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceDTV(enInputSourceType)) ++ { ++#if (PQ_QM_DTV) ++ if(QM_IsDTV_IFRAME(eWindow)) ++ { ++ #if 1 //( CHIP_FAMILY_TYPE != CHIP_FAMILY_S7J) ++ //If PQ has devide the iframe setting according to P/I mode, then use new PQ srctype ++ if (u16Input_VSize < 720) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_iFrame_SD_interlace_Main; ++ else ++ u16SrcType = QM_DTV_iFrame_SD_progressive_Main; ++ } ++ else ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_iFrame_HD_interlace_Main; ++ else ++ u16SrcType = QM_DTV_iFrame_HD_progressive_Main; ++ } ++ #else ++ u16SrcType = QM_DTV_iFrame_Main; ++ #endif ++ } ++ else if (QM_IsDTV_MPEG2(eWindow)) ++ { ++ if (u16Input_VSize < 500) ++ { ++ if ((u16Input_HSize < 400) && bIsInterlaced) ++ { ++ u16SrcType = QM_DTV_480i_352x480_MPEG2_Main; ++ } ++ else ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_480i_MPEG2_Main; ++ else ++ u16SrcType = QM_DTV_480p_MPEG2_Main; ++ } ++ } ++ else if (u16Input_VSize < 650) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_576i_MPEG2_Main; ++ else ++ u16SrcType = QM_DTV_576p_MPEG2_Main; ++ } ++ else if ((u16Input_VSize < 900) && (bIsInterlaced==0)) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_720p_60hz_MPEG2_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_720p_50hz_MPEG2_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_720p_24hz_MPEG2_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080i_60hz_MPEG2_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080i_50hz_MPEG2_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080p_60hz_MPEG2_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_1080p_50hz_MPEG2_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080p_24hz_MPEG2_Main; ++ } ++ ++ } ++ } ++ } ++ else // QM_IsDTV_H264(eWindow) ++ { ++ if ((u16Input_HSize < 1260) && (u16Input_VSize < 650)) ++ { ++ if (u16Input_VSize < 500) ++ { ++ if ((u16Input_HSize < 400) && bIsInterlaced) ++ { ++ u16SrcType = QM_DTV_480i_352x480_H264_Main; ++ } ++ else ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_480i_H264_Main; ++ else ++ u16SrcType = QM_DTV_480p_H264_Main; ++ } ++ } ++ else if (u16Input_VSize < 650) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_576i_H264_Main; ++ else ++ u16SrcType = QM_DTV_576p_H264_Main; ++ } ++ } ++ else ++ { ++ if ((u16Input_VSize < 900) && (bIsInterlaced==0)) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_720p_60hz_H264_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_720p_50hz_H264_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_720p_24hz_H264_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080i_60hz_H264_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080i_50hz_H264_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080p_60hz_H264_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_1080p_50hz_H264_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080p_24hz_H264_Main; ++ } ++ } ++ } ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceMultiMedia(enInputSourceType)) ++ { ++#if (PQ_QM_MM_VIDEO) || (PQ_QM_MM_PHOTO) ++ if (QM_IsMultiMediaMOVIE(eWindow)) ++ { ++ if ((u16Input_HSize <= 720) && (u16Input_VSize <= 576)) ++ { ++ if (bIsInterlaced) ++ { ++ u16SrcType = QM_Multimedia_video_SD_interlace_Main; ++ } ++ else ++ { ++ u16SrcType = QM_Multimedia_video_SD_progressive_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ u16SrcType = QM_Multimedia_video_HD_interlace_Main; ++ } ++ else ++ { ++ u16SrcType = QM_Multimedia_video_HD_progressive_Main; ++ } ++ } ++ } ++ else //QM_IsMultiMediaPHOTO(eWindow) ++ { ++ if ((u16Input_HSize <= 720) && (u16Input_VSize <= 576)) ++ { ++ u16SrcType = QM_Multimedia_photo_SD_progressive_Main; ++ } ++ else ++ { ++ u16SrcType = QM_Multimedia_photo_HD_progressive_Main; ++ } ++ } ++#endif ++ } ++#if (PQ_ENABLE_UNUSED_FUNC) ++ else if (QM_IsSourceScartRGB(enInputSourceType, eWindow)) ++ { ++#if (PQ_QM_CVBS) ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_SCART_RGB_NTSC_Main; ++ } ++ else ++ { ++ u16SrcType = QM_SCART_RGB_PAL_Main; ++ } ++#endif ++ } ++ else if (QM_IsSourceScartCVBS(enInputSourceType, eWindow)) ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_SCART_AV_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_SCART_AV_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_SCART_AV_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_SCART_AV_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_SCART_AV_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_SCART_AV_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_SCART_AV_PAL_BGHI_Main; ++ break; ++ } ++#endif ++ } ++#endif ++ else if (QM_IsSourceATV(enInputSourceType)) ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ if (QM_FRONTEND_RFIN(eWindow)) ++ { ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_RF_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_RF_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_RF_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_RF_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_RF_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_RF_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_RF_PAL_BGHI_Main; ++ break; ++ } ++ } ++ else // QM_FRONTEND_VIFIN(eWindow) ++ { ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_VIF_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_VIF_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_VIF_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_VIF_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_VIF_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_VIF_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_VIF_PAL_BGHI_Main; ++ break; ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceSV(enInputSourceType)) ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_SV_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_SV_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_SV_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_SV_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_SV_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_SV_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_SV_PAL_BGHI_Main; ++ break; ++ } ++#endif ++ } ++ ++ else if(QM_IsSourceISP(enInputSourceType)) ++ { ++#if (PQ_QM_ISP) ++ u16SrcType = QM_FHD_YUV422_Main; ++#endif ++ } ++ else // AV ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_AV_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_AV_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_AV_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_AV_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_AV_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_AV_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_AV_PAL_BGHI_Main; ++ break; ++ } ++#endif ++ } ++ return u16SrcType; ++ ++} +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/include/QualityMode.h b/drivers/mstar/scl/infinity/src/mxlib/pq/include/QualityMode.h +new file mode 100644 +index 00000000..ed0e302f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/include/QualityMode.h +@@ -0,0 +1,78 @@ ++ ++ ++#define QM_IsSourceVGA(x) ((x)==PQ_INPUT_SOURCE_VGA) ++#define QM_IsSourceHDMI(x) ((x)==PQ_INPUT_SOURCE_HDMI) ++#define QM_IsSourceDVI_HDMIPC(x,y) (QM_IsSourceHDMI(x) && (_stHDMI_Info[y].bIsHDMI == FALSE)) ++#define QM_IsSourceHDMI_Video(x,y) (QM_IsSourceHDMI(x) && (_stHDMI_Info[y].bIsHDMI == TRUE) && (_stHDMI_Info[y].bIsHDMIPC == FALSE)) ++#define QM_IsSourceHDMI_PC(x,y) (QM_IsSourceHDMI(x) && (_stHDMI_Info[y].bIsHDMI == TRUE) && (_stHDMI_Info[y].bIsHDMIPC == TRUE)) ++ ++#define QM_HDMIPC_COLORRGB(x) (_stHDMI_Info[x].enColorFmt == PQ_HDMI_COLOR_RGB) ++#define QM_HDMIPC_COLORYUV422(x) (_stHDMI_Info[x].enColorFmt == PQ_HDMI_COLOR_YUV_422) ++#define QM_HDMIPC_COLORYUV444(x) (_stHDMI_Info[x].enColorFmt == PQ_HDMI_COLOR_YUV_444) ++ ++#define QM_IsSrource656(x) ((x)== PQ_INPUT_SOURCE_BT656) ++ ++#define QM_IsSourceYPbPr(x) ((x)==PQ_INPUT_SOURCE_YPBPR) ++ ++#define QM_IsSourceYPbPrSD(x,y) (QM_IsSourceYPbPr(x) \ ++ && ( _u8ModeIndex[y] == PQ_MD_720x480_60I \ ++ ||_u8ModeIndex[y] == PQ_MD_720x480_60P \ ++ ||_u8ModeIndex[y] == PQ_MD_720x576_50I \ ++ ||_u8ModeIndex[y] == PQ_MD_720x576_50P) ) ++ ++#define QM_IsSourceDTV(x) ((x)==PQ_INPUT_SOURCE_DTV) ++#define QM_IsSourceMultiMedia(x) (((x)>=PQ_INPUT_SOURCE_STORAGE) && ((x)<=PQ_INPUT_SOURCE_JPEG)) ++ ++#define QM_IsMultiMediaMOVIE(x) (_stMultiMedia_Info[x].eType == E_PQ_MULTIMEDIA_MOVIE) ++#define QM_IsMultiMediaPHOTO(x) (_stMultiMedia_Info[x].eType == E_PQ_MULTIMEDIA_PHOTO) ++ ++#define QM_IsDTV_MPEG2(x) (_stDTV_Info[x].eType == E_PQ_DTV_MPEG2) ++#define QM_IsDTV_H264(x) (_stDTV_Info[x].eType == E_PQ_DTV_H264) ++#define QM_IsDTV_IFRAME(x) (_stDTV_Info[x].eType == E_PQ_DTV_IFRAME) ++ ++#define QM_IsSourceScartRGB(x,y) (((x)==PQ_INPUT_SOURCE_SCART) && (_stVD_Info[y].bIsSCART_RGB == TRUE)) ++#define QM_IsSourceScartCVBS(x,y) (((x)==PQ_INPUT_SOURCE_SCART) && (_stVD_Info[y].bIsSCART_RGB == FALSE)) ++#define QM_IsSourceScart(x) ((x)==PQ_INPUT_SOURCE_SCART) ++#define QM_IsSourceATV(x) ((x)==PQ_INPUT_SOURCE_TV) ++#define QM_IsSourceSV(x) ((x)==PQ_INPUT_SOURCE_SVIDEO) ++#define QM_IsSourceAV(x) ((x)==PQ_INPUT_SOURCE_CVBS) ++#define QM_IsSourceVD(x) ( QM_IsSourceATV(x) \ ++ || QM_IsSourceAV(x) \ ++ || QM_IsSourceSV(x) \ ++ || QM_IsSourceScart(x) ) ++#define QM_IsSourceISP(x) ((x) == PQ_INPUT_SOURCE_ISP) ++#define QM_Is3DVideo() (_gIs3D_En == TRUE) ++ ++#define QM_FRONTEND_RFIN(x) (!_stVD_Info[x].bIsVIFIN) ++#define QM_FRONTEND_VIFIN(x) (_stVD_Info[x].bIsVIFIN) ++ ++#define QM_GetInputHSize(x) (_stMode_Info[x].u16input_hsize) ++#define QM_GetInputVSize(x) (_stMode_Info[x].u16input_vsize) ++ ++#define QM_H_Size_Check_x1(x, y) ( ((x) < ((y)*1+50)) && ((x) > ((y)*1-50)) ) ++#define QM_H_Size_Check_x2(x, y) ( ((x) < ((y)*2+50)) && ((x) > ((y)*2-50)) ) ++#define QM_H_Size_Check_x4(x, y) ( ((x) < ((y)*4+50)) && ((x) > ((y)*4-50)) ) ++#define QM_H_Size_Check_x8(x, y) ( ((x) < ((y)*8+50)) && ((x) > ((y)*8-50)) ) ++ ++#define QM_IsYPbPr_720x480_60I(x) (_u8ModeIndex[x] == PQ_MD_720x480_60I) ++#define QM_IsYPbPr_720x480_60P(x) (_u8ModeIndex[x] == PQ_MD_720x480_60P) ++#define QM_IsYPbPr_720x576_50I(x) (_u8ModeIndex[x] == PQ_MD_720x576_50I) ++#define QM_IsYPbPr_720x576_50P(x) (_u8ModeIndex[x] == PQ_MD_720x576_50P) ++#define QM_IsYPbPr_1280x720_50P(x) (_u8ModeIndex[x] == PQ_MD_1280x720_50P) ++#define QM_IsYPbPr_1280x720_60P(x) (_u8ModeIndex[x] == PQ_MD_1280x720_60P) ++#define QM_IsYPbPr_1920x1080_50I(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_50I) ++#define QM_IsYPbPr_1920x1080_60I(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_60I) ++ ++#define QM_IsYPbPr_1920x1080_24P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_24P) ++#define QM_IsYPbPr_1920x1080_25P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_25P) ++#define QM_IsYPbPr_1920x1080_30P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_30P) ++#define QM_IsYPbPr_1920x1080_50P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_50P) ++#define QM_IsYPbPr_1920x1080_60P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_60P) ++ ++#define QM_GetInputVFreq(x) (_stMode_Info[x].u16input_vfreq) ++#define QM_IsInterlaced(x) (_stMode_Info[x].bInterlace) ++ ++#define QM_GetDispHSize(x) (_stMode_Info[x].u16display_hsize) ++#define QM_GetDispVSize(x) (_stMode_Info[x].u16display_vsize) ++ ++#define QM_GetATVStandard(x) (_stVD_Info[x].enVideoStandard) +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/include/drvPQ.h b/drivers/mstar/scl/infinity/src/mxlib/pq/include/drvPQ.h +new file mode 100644 +index 00000000..ff0ab217 +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/include/drvPQ.h +@@ -0,0 +1,1397 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file drvPQ.h ++/// @brief PQ interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRVPQ_H_ ++#define _DRVPQ_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MSIF_PQ_TAG {'M','S','I','F'} // MSIF ++#define MSIF_PQ_CLASS {'0','0'} // DRV/API (DDI) ++#define MSIF_PQ_CUS 0x0000 // MStar Common library ++#define MSIF_PQ_MOD 0x0000 // MStar Common library ++#define MSIF_PQ_CHIP 0x0000 ++#define MSIF_PQ_CPU '0' ++#define MSIF_PQ_OS '0' ++ ++// library information ++ ++/// the PQ lib code ++#define MSIF_PQ_LIB_CODE {'P','Q','_','_'} ++/// the PQ lib version ++#define MSIF_PQ_LIBVER {'0','0'} ++/// the PQ build number ++#define MSIF_PQ_BUILDNUM {'0','7'} ++/// the PQ CL ++#define MSIF_PQ_CHANGELIST {'0','0','3','5','3','5','7','6'} ++ ++/// the PQ driver version ++#define PQ_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_PQ_TAG, /* 'MSIF' */ \ ++ MSIF_PQ_CLASS, /* '00' */ \ ++ MSIF_PQ_CUS, /* 0x0000 */ \ ++ MSIF_PQ_MOD, /* 0x0000 */ \ ++ MSIF_PQ_CHIP, \ ++ MSIF_PQ_CPU, \ ++ MSIF_PQ_LIB_CODE , /* IP__ */ \ ++ MSIF_PQ_LIBVER , /* 0.0 ~ Z.Z */ \ ++ MSIF_PQ_BUILDNUM , /* 00 ~ 99 */ \ ++ MSIF_PQ_CHANGELIST, /* CL# */ \ ++ MSIF_PQ_OS ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#define ENABLE_PQ_LOAD_TABLE_INFO 0 ///= CMDQ_MAX_CMD_SIZE) \ ++ { \ ++ _u16CMDQCmdCnt = CMDQ_MAX_CMD_SIZE-1; \ ++ } \ ++ \ ++ }while(0) ++#endif ++ ++ ++#if (PQ_ENABLE_CHECK == 0) ++ #define PQ_REG_FUNC_READ( u32Reg) MApi_XC_ReadByte(u32Reg) ++ #define PQ_REG_FUNC( u32Reg, u8Value, u8Mask ) MApi_XC_WriteByteMask( u32Reg, u8Value, u8Mask ) ++ #define PQ_REG_FUNC_xc( u32Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if(u32Reg %2){ \ ++ MApi_XC_W2BYTEMSK(u32Reg-1, ((MS_U16)u8Value)<<8, ((MS_U16)u8Mask)<<8); \ ++ }else{ \ ++ MApi_XC_W2BYTEMSK(u32Reg, u8Value, u8Mask); \ ++ }\ ++ }while(0) ++ ++ #define PQ_REG_MLOAD_WRITE_CMD(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg-1; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask)<<8; \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value)<<8; \ ++ } \ ++ else \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask); \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value); \ ++ } \ ++ _u16MLoadCmdCnt++; \ ++ if(_u16MLoadCmdCnt >= MLOAD_MAX_CMD)\ ++ {\ ++ printf("[PQ ERROR] ====ML overflow !!! \r\n");\ ++ _u16MLoadCmdCnt = MLOAD_MAX_CMD - 1; \ ++ }\ ++ }while(0) ++ ++ #define PQ_REG_MLOAD_FUNC(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg-1, ((MS_U16)u8Value)<<8, ((MS_U16)u8Mask)<<8); \ ++ } \ ++ else \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg, u8Value, u8Mask); \ ++ } \ ++ }while(0) ++ ++ #define PQ_SWREG_FUNC( u16Reg, u8Value, u8Mask ) SWReg_WriteByteMask( u16Reg, u8Value, u8Mask ) ++ ++ ++#else // #if(PQ_ENABLE_CHECK == 1) ++ ++static MS_U8 _u8PQfunction = PQ_FUNC_DUMP_REG; ++ ++static void _MDrv_PQ_SetFunction(MS_U8 u8Func) ++{ ++ _u8PQfunction = u8Func; ++} ++ ++#define PQ_REG_FUNC( u16Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if (_u8PQfunction == PQ_FUNC_DUMP_REG){ \ ++ MApi_XC_WriteByteMask( (MS_U32)u16Reg, u8Value, u8Mask ); \ ++ }else{ \ ++ if ((MApi_XC_ReadByte((MS_U32)u16Reg) & u8Mask) != ((u8Value) & (u8Mask))){ \ ++ printf("[PQRegErr] "); \ ++ if (((u16Reg) >> 8) == 0x2F){ \ ++ printf("bk=%02x, ", (MS_U16)SC_BK_CURRENT); \ ++ } \ ++ else if (((u16Reg) >> 8) == 0x36){ \ ++ printf("bk=%02x, ", (MS_U16)COMB_BK_CURRENT); \ ++ } \ ++ printf("addr=%04x, mask=%02x, val=%02x[%02x]\r\n", \ ++ u16Reg, (MS_U16)u8Mask, (MS_U16)MApi_XC_ReadByte((MS_U32)u16Reg), (MS_U16)u8Value); \ ++ } \ ++ } \ ++ }while(0) ++ ++#define PQ_SWREG_FUNC( u16Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if (_u8PQfunction == PQ_FUNC_DUMP_REG){ \ ++ SWReg_WriteByteMask( u16Reg, u8Value, u8Mask ); \ ++ }else{ \ ++ if (SWReg[u16Reg] & (u8Mask) != (u8Value) & (u8Mask)){ \ ++ printf("[PQSWRegErr] "); \ ++ printf("addr=%04x, mask=%02x, val=%02x[%02x]\r\n", \ ++ u16Reg, (MS_U16)u8Mask, (MS_U16)SWReg[u16Reg], (MS_U16)u8Value); \ ++ } \ ++ } \ ++ }while(0) ++ ++#endif //#if (PQ_ENABLE_CHECK) ++ ++ ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if 0 ++static void _MDrv_PQ_Set_MLoadEn(MS_BOOL bEn) ++{ ++ MS_U16 i; ++ if(bEn == DISABLE) ++ { ++ //if spread reg, no need to use mutex, but it's ok to use mutex ++ // (because it's not MApi_XC_W2BYTE(), which has mutex already) ++ //if not spread reg, must use mutex to protect MLoad_trigger func. ++ SC_BK_STORE_MUTEX; ++ ++ if(_u16MLoadCmdCnt) ++ { ++ for(i=1; i<_u16MLoadCmdCnt; i++) ++ { ++ if(_u32MLoadCmd[i-1] == _u32MLoadCmd[i]) ++ { ++ _u16MLoadMsk[i] |= _u16MLoadMsk[i-1]; ++ _u16MLoadVal[i] |= _u16MLoadVal[i-1]; ++ } ++ } ++ #if(ENABLE_PQ_MLOAD) ++ ++ MApi_XC_MLoad_WriteCmds_And_Fire( ++ &_u32MLoadCmd[0], &_u16MLoadVal[0], &_u16MLoadMsk[0], _u16MLoadCmdCnt); ++ #endif ++ _u16MLoadCmdCnt = 0; ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++ } ++ else ++ { ++ //_u16MLoadCmdCnt = 0; ++ } ++ ++ _bMLoadEn = bEn; ++} ++#endif ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ ++static void _MDrv_PQ_PreInitLoadTableInfo(void) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++ MS_U16 u16IPIdx; ++ g_PQLoadTableInfo._u16CurInputSrcType = -1; ++ for( u16IPIdx = 0; u16IPIdx < MAX_IP_NUM; ++ u16IPIdx ) ++ { ++ g_PQLoadTableInfo._au8IPGroupIdx[u16IPIdx] = 0xFF; ++ } ++#endif ++ ++} ++ ++static void _MDrv_PQ_Set_LoadTableInfo_IP_Tab(MS_U16 u16IPIdx, MS_U8 u8TabIdx) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ g_PQLoadTableInfo._au8IPGroupIdx[u16IPIdx] = u8TabIdx; ++#else ++ UNUSED(u16IPIdx); ++ UNUSED(u8TabIdx); ++#endif ++ ++} ++ ++static MS_U8 _MDrv_PQ_Get_LoadTableInfo_IP_Tab(MS_U16 u16IPIdx) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ return g_PQLoadTableInfo._au8IPGroupIdx[u16IPIdx]; ++#else ++ UNUSED(u16IPIdx); ++ return 0xFF; ++#endif ++} ++ ++static void _MDrv_PQ_Set_LoadTableInfo_SrcType(MS_U16 u16SrcType) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ g_PQLoadTableInfo._u16CurInputSrcType = u16SrcType; ++#else ++ UNUSED(u16SrcType); ++#endif ++} ++ ++static MS_U16 _MDrv_PQ_Get_LoadTableInfo_SrcType(void) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ return g_PQLoadTableInfo._u16CurInputSrcType; ++#else ++ return 0xFFFF; ++#endif ++} ++#endif ++ ++static void _MDrv_PQ_DumpGeneralRegTable(EN_IP_Info* pIP_Info) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ ++ PQ_DUMP_DBG(printf("tab: general\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: General Reg Table\r\n")); ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pIP_Info->pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ break; ++ ++ u32Addr |= NON_PM_BASE; ++ PQ_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\r\n", u32Addr, u8Mask, u8Value)); ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ } ++} ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ ++static void _MDrv_PQ_DumpCombRegTable(EN_IP_Info* pIP_Info) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ COMB_BK_STORE; ++ ++ PQ_DUMP_DBG(printf("tab: comb\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Comb Reg Table\r\n")); ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pIP_Info->pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ break; ++ ++ u8CurBank = (MS_U8)(u32Addr >> 8); ++ if (u8CurBank != COMB_BK_CURRENT) ++ { ++ PQ_DUMP_DBG(printf("<>\r\n", u8CurBank)); ++ COMB_BK_SWITCH(u8CurBank); ++ } ++ ++ u32Addr = COMB_REG_BASE | (u32Addr & 0x00FF); ++ ++ PQ_DUMP_DBG(printf("[addr=%04x, msk=%02x, val=%02x]\r\n", (int)u32Addr, u8Mask, u8Value)); ++ ++/* ++//Only works for T4, obsolete in main trunk. ++ #if (CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD) ++ // patch Comb register H part can not be written by 16 bits riu ++ if((u32Addr == (COMB_REG_BASE + 0x47)) || ++ (u32Addr == (COMB_REG_BASE + 0x5F)) || ++ (u32Addr == (COMB_REG_BASE + 0x8F)) || ++ (u32Addr == (COMB_REG_BASE + 0xD7)) || ++ (u32Addr == (COMB_REG_BASE + 0xDF))) ++ { ++ MS_U8 u8low, u8High; ++ MS_U16 u16value; ++ ++ u8low = MApi_XC_ReadByte(u32Addr-1); ++ u8High = MApi_XC_ReadByte(u32Addr); ++ u16value = (u8High & ~u8Mask) | (u8Value & u8Mask); ++ u16value = (u16value<<8) | u16value; ++ ++ MApi_XC_Write2ByteMask(u32Addr-1, u16value, 0xFFFF); ++ PQ_REG_FUNC(u32Addr-1, u8low, 0xFF); ++ } ++ else ++ #endif ++*/ ++ { ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ } ++ ++ COMB_BK_RESTORE; ++} ++#endif ++ ++static void _MDrv_PQ_CMDQ_Fire(MS_U8 u8FmCnt) ++{ ++ MS_U16 i; ++ ++ for(i=0; i<_u16CMDQCmdCnt; i++) ++ { ++ Drv_CMDQ_AssignFrameWriteCmd( _u32CMDQ_Cmd[i], _u16CMDQ_Val[i], _u16CMDQ_Msk[i], u8FmCnt); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, "Cmdq:: ADD:%04lX, VAL:%02X, MSK:%02X, FMCnt:%02X\n" ++ ,_u32CMDQ_Cmd[i], _u16CMDQ_Val[i],_u16CMDQ_Msk[i], u8FmCnt); ++ } ++ ++ _u16CMDQCmdCnt = 0; ++ if(_bfire_En) ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++} ++ ++ ++static void _MDrv_PQ_DumpSclaerRegTableByData(EN_IP_Info* pIP_Info, PQ_DATA_INFO *pData) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ MS_U16 u16DataIdx; ++ ++ ++ SC_BK_STORE_MUTEX; ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "[PQ]%s %d:: CmdqEn:%d, CmdqFmCnt=%d\n" ++ , __FUNCTION__, __LINE__, _bCMDQ_En, _u8CMDQ_FmCnt); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums) ++ { ++ PQ_ERR(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ ++ SC_BK_RESTORE_MUTEX; ++ ++ return; ++ } ++ ++ u16DataIdx = 0; ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pData->pBuf[u16DataIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ { ++ break; ++ } ++ u8CurBank = (MS_U8)(u32Addr >> 8); ++ ++ #if (SCALER_REGISTER_SPREAD) ++ u32Addr = BK_SCALER_BASE | u32Addr; ++ #else ++ if (u8CurBank != SC_BK_CURRENT) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "<>\r\n",u8CurBank); ++ SC_BK_SWITCH(u8CurBank); ++ } ++ ++ u32Addr = BK_SCALER_BASE | (u32Addr & 0x00FF); ++ #endif ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "BK =%04X, addr=%02X, msk=%02X, value=%02X\r\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)u8Value); ++ #if (ENABLE_PQ_CMDQ) ++ ++ if(_bCMDQ_En) ++ { ++ PQ_REG_CMDQ_Write(u32Addr, u8Value, u8Mask); ++ } ++ else if(_bcheckReg) ++ { ++ MS_U8 u8MaskL; ++ MS_U8 u8Value_CMDQ; ++ MS_U32 u32Addr_CMDQ; ++ u8Value_CMDQ=PQ_REG_FUNC_READ(u32Addr); ++ if((u8Value_CMDQ&u8Mask)!=(u8Value&u8Mask)) ++ { ++ (printf("BK =%04X, addr=%02X, msk=%02X, value=%02X ckvalue=%02X\r\n",(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)(u8Value&u8Mask), (MS_U16)(u8Value_CMDQ))); ++ } ++ else if(((u8Value)==(0xFF))&&((u8Value_CMDQ&u8Mask)!=u8Mask)) ++ { ++ (printf("BK =%04X, addr=%02X, msk=%02X, value=%02X ckvalue=%02X\r\n",(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)(u8Value&u8Mask), (MS_U16)(u8Value_CMDQ))); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "pass BK =%04X, addr=%02X value=%02X ckvalue=%02X\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)(u8Value&u8Mask), (MS_U16)(u8Value_CMDQ&u8Mask)); ++ } ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ u32Addr_CMDQ = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ if(((u32Addr%2)&&(((u32Addr&0xFF)-1)==((u32Addr_CMDQ&0xFF))))&&(u32Addr_CMDQ != _END_OF_TBL_))//is H level and next L level ++ { ++ u8MaskL = pIP_Info->pIPTable[2]; ++ if(u8MaskL==0xFF) ++ { ++ (printf("[warning HL]BK =%04X, addr=%02X\r\n",(MS_U16)((u32Addr&0xFFFF00)>>8),(MS_U16)(u32Addr&0xFF) )); ++ } ++ } ++ pIP_Info->pIPTable-=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // roll back ++ } ++ else if(_bcheckPQsize) ++ { ++ if((u8Mask & u8Value)==0 &&(u8Value!=0)) ++ { ++ (printf("[PQ-major]BK =%04X, addr=%02X, msk=%02X, value=%02X ,msk&val=%02X \r\n",(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask,(MS_U16)(u8Value) ,(MS_U16)(u8Value&u8Mask))); ++ } ++ else if((u8Value!=0 && u8Value!=0xFF) &&(~u8Mask & u8Value)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "[PQ-minor]BK =%04X, addr=%02X, msk=%02X, value=%02X ,msk&val=%02X \r\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask,(MS_U16)(u8Value) ,(MS_U16)(u8Value&u8Mask)); ++ } ++ } ++ else ++ #endif ++ { ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ u16DataIdx++; ++ if(u16DataIdx > pData->u16BufSize) ++ { ++ printf("%s %d, Data size is smaller than PQ table, idx:%d size:%d\n", ++ __FUNCTION__, __LINE__, u16DataIdx, pData->u16BufSize); ++ break; ++ } ++ } ++ ++#if (ENABLE_PQ_CMDQ) ++ if(_bCMDQ_En) ++ { ++ _MDrv_PQ_CMDQ_Fire(_u8CMDQ_FmCnt); ++ } ++#endif ++ if(u16DataIdx != pData->u16BufSize) ++ { ++ printf("%s %d, Data size is bigger than PQ table, idx:%d, size:%d\n", ++ __FUNCTION__, __LINE__, u16DataIdx, pData->u16BufSize); ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++} ++ ++ ++ ++static void _MDrv_PQ_DumpScalerRegTable(EN_IP_Info* pIP_Info) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ pthread_mutex_lock(&_PQ_MLoad_Mutex); ++ #endif ++#endif ++ ++ SC_BK_STORE_MUTEX; ++ PQ_DUMP_DBG(printf("tab: sc\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums) ++ { ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ ++ SC_BK_RESTORE_MUTEX; ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++ #endif ++#endif ++ ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pIP_Info->pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ break; ++ ++ u8CurBank = (MS_U8)(u32Addr >> 8); ++ PQ_DUMP_DBG(printf("XC bk =%x, addr=%x, msk=%x, value=%x\r\n", (MS_U16)((u32Addr&0xFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)u8Value)); ++#if(ENABLE_PQ_MLOAD) ++ if(_bMLoadEn) ++ { ++ //printf("MLad: %lx, %x, %x\r\n", u32Addr, u8Value, u8Mask); ++ PQ_REG_MLOAD_WRITE_CMD(u32Addr, u8Value, u8Mask); ++ //PQ_REG_MLOAD_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ else ++#endif ++ { ++ #if (SCALER_REGISTER_SPREAD) ++ u32Addr = BK_SCALER_BASE | u32Addr; ++ #else ++ if (u8CurBank != SC_BK_CURRENT) ++ { ++ PQ_DUMP_DBG(printf("<>\r\n", u8CurBank)); ++ SC_BK_SWITCH(u8CurBank); ++ } ++ ++ u32Addr = BK_SCALER_BASE | (u32Addr & 0x00FF); ++ #endif ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ } ++ ++ ++ SC_BK_RESTORE_MUTEX; ++ ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++ #endif ++#endif ++} ++ ++static void _MDrv_PQ_DumpFilterTable(EN_IP_Info* pIP_Info) ++{ ++ ++ PQ_DUMP_FILTER_DBG(printf("tab: sram\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: SRAM Table\r\n")); ++ return; ++ } ++ PQ_DUMP_FILTER_DBG(printf("pIP_Info->u8TabType: %u\r\n",pIP_Info->u8TabType)); ++ switch(pIP_Info->u8TabType) ++ { ++ case PQ_TABTYPE_SRAM_COLOR_INDEX: ++ Hal_PQ_set_sram_color_index_table(_PQTableInfo.eWin, SC_FILTER_SRAM_COLOR_INDEX, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_COLOR_INDEX)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_SNR: ++ Hal_PQ_set_sram_color_gain_snr_table(_PQTableInfo.eWin, SC_FILTER_SRAM_COLOR_GAIN_SNR, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_COLOR_GAIN_SNR)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_DNR: ++ Hal_PQ_set_sram_color_gain_snr_table(_PQTableInfo.eWin, SC_FILTER_SRAM_COLOR_GAIN_DNR, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_COLOR_GAIN_DNR)])); ++ break; ++ ++ case PQ_TABTYPE_VIP_ICC_CRD_SRAM: ++ Hal_PQ_set_sram_icc_crd_table(_PQTableInfo.eWin, SC_FILTER_SRAM_ICC_CRD, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_ICC_CRD)])); ++ break; ++ ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ Hal_PQ_set_sram_ihc_crd_table(_PQTableInfo.eWin, SC_FILTER_SRAM_IHC_CRD, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_IHC_CRD)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM1: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM1 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM1)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM2: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM2 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM2)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM3: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM3 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM3)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM4: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM4 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM4)])); ++ break; ++ ++ default: ++ printf("[PQ]Unknown sram type %u\r\n", pIP_Info->u8TabType); ++ break; ++ } ++ PQ_DUMP_FILTER_DBG(printf("tab load finish\r\n")); ++} ++ ++static void _MDrv_PQ_ClearTableIndex(void) ++{ ++ ++ _u8ICC_CRD_Table = 0xFF; ++ _u8IHC_CRD_Table = 0xFF; ++ _u8SRAM1Table = 0xFF; ++ _u8SRAM2Table = 0xFF; ++ _u8SRAM3Table =0xFF; ++ _u8SRAM4Table = 0xFF; ++ _u8CSRAM1Table = 0xFF; ++ _u8CSRAM2Table = 0xFF; ++ _u8CSRAM3Table = 0xFF; ++ _u8CSRAM4Table = 0xFF; ++} ++ ++ ++static void _MDrv_PQ_DumpTable(EN_IP_Info* pIP_Info) ++{ ++ // to save loading SRAM table time, SRAM are only downloaded ++ // when current SRAM table is different to previous SRAM table ++ if (pIP_Info->pIPTable == NULL) ++ { ++ PQ_DUMP_DBG(printf("NULL Table\r\n")); ++ return; ++ } ++ PQ_DUMP_DBG(printf("Table Type =%x, Index =%x\r\n", (MS_U16)pIP_Info->u8TabType, (MS_U16)pIP_Info->u8TabIdx)); ++ switch(pIP_Info->u8TabType ) ++ { ++ ++ case PQ_TABTYPE_SCALER: ++ _MDrv_PQ_DumpScalerRegTable(pIP_Info); ++ break; ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ case PQ_TABTYPE_COMB: ++ _MDrv_PQ_DumpCombRegTable(pIP_Info); ++ break; ++#endif ++ ++ case PQ_TABTYPE_SRAM1: ++ if (_u8SRAM1Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old sram1: %u, new sram1: %u\r\n", ++ (MS_U16)_u8SRAM1Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM1Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram1: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM2: ++ if (_u8SRAM2Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old sram2: %u, new sram2: %u\r\n", ++ (MS_U16)_u8SRAM2Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM2Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram2: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_SRAM3: ++ if (_u8SRAM3Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old sram3: %u, new sram3: %u\r\n", ++ (MS_U16)_u8SRAM3Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM3Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram3: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_SRAM4: ++ if (_u8SRAM4Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old s ram4: %u, new sram4: %u\r\n", ++ (MS_U16)_u8SRAM4Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM4Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram4: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ ++ case PQ_TABTYPE_C_SRAM1: ++ if (_u8CSRAM1Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram1: %u, new Csram1: %u\r\n", ++ (MS_U16)_u8CSRAM1Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM1Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same Csram1: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM2: ++ if (_u8CSRAM2Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram2: %u, new Csram2: %u\r\n", ++ (MS_U16)_u8CSRAM2Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM2Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same Csram2: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_C_SRAM3: ++ if (_u8CSRAM3Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram3: %u, new Csram3: %u\r\n", ++ (MS_U16)_u8CSRAM3Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM3Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram3: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_C_SRAM4: ++ if (_u8SRAM4Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram4: %u, new Csram4: %u\r\n", ++ (MS_U16)_u8CSRAM4Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM4Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same Csram4: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_VIP_ICC_CRD_SRAM: ++ if( _u8ICC_CRD_Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old ICC_CRD_SRAM: %u, new ICC_CRD_SRAM: %u\r\n", ++ (MS_U16)_u8ICC_CRD_Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8ICC_CRD_Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ ++ } ++ break; ++ ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ if( _u8IHC_CRD_Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old IHC_CRD_SRAM: %u, new IHC_CRD_SRAM: %u\r\n", ++ (MS_U16)_u8IHC_CRD_Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8IHC_CRD_Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ ++ } ++ break; ++ ++ case PQ_TABTYPE_GENERAL: ++ _MDrv_PQ_DumpGeneralRegTable(pIP_Info); ++ break; ++ ++ case PQ_TABTYPE_PICTURE_1: ++ case PQ_TABTYPE_PICTURE_2: ++ break; ++ ++ default: ++ PQ_DUMP_DBG(printf("[PQ]DumpTable:unknown type: %u\r\n", pIP_Info->u8TabType)); ++ break; ++ } ++} ++ ++// return total IP count ++static MS_U16 _MDrv_PQ_GetIPNum(void) ++{ ++ PQ_DBG(printf("[PQ]IPNum=%u\r\n",_PQTableInfo.u8PQ_IP_Num)); ++ return (MS_U16)_PQTableInfo.u8PQ_IP_Num; ++} ++ ++// return total table count of given IP ++static MS_U16 _MDrv_PQ_GetTableNum(MS_U8 u8PQIPIdx) ++{ ++ PQ_DBG(printf("[PQ]TabNum=%u\r\n", _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabNums)); ++ return (MS_U16)_PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabNums; ++} ++ ++// return current used table index of given IP ++static MS_U16 _MDrv_PQ_GetCurrentTableIndex(MS_U8 u8PQIPIdx) ++{ ++ PQ_DBG(printf("[PQ]CurrTableIdx=%u\r\n", _u8PQTabIdx[u8PQIPIdx])); ++ return (MS_U16)_u8PQTabIdx[u8PQIPIdx]; ++} ++ ++static MS_U16 _MDrv_PQ_GetTableIndex(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx) ++{ ++ if (u16PQSrcType >=_PQTableInfo.u8PQ_InputType_Num){ ++ PQ_DBG(printf("[PQ]invalid input type\r\n")); ++ return PQ_IP_NULL; ++ } ++ if (u8PQIPIdx >= _PQTableInfo.u8PQ_IP_Num){ ++ PQ_DBG(printf("[PQ]invalid ip type\r\n")); ++ return PQ_IP_NULL; ++ } ++ ++ PQ_DBG(printf("[PQ]TableIdx=%u\r\n",(MS_U16)_PQTableInfo.pQuality_Map_Aray[u16PQSrcType * _PQTableInfo.u8PQ_IP_Num + u8PQIPIdx])); ++ ++ return (MS_U16)_PQTableInfo.pQuality_Map_Aray[u16PQSrcType * _PQTableInfo.u8PQ_IP_Num + u8PQIPIdx]; ++} ++ ++static EN_IP_Info _MDrv_PQ_GetTable(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ _u8PQTabIdx[u8PQIPIdx] = u8TabIdx; ++ if (u8TabIdx != PQ_IP_NULL && u8TabIdx != PQ_IP_COMM) { ++ ip_Info.pIPTable = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].pIPTable; ++ ip_Info.u8TabNums = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabNums; ++ ip_Info.u8TabType = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabType; ++ ip_Info.u8TabIdx = u8TabIdx; ++ } ++ else if (u8TabIdx == PQ_IP_COMM) { ++ ip_Info.pIPTable = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].pIPCommTable; ++ ip_Info.u8TabNums = 1; ++ ip_Info.u8TabType = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabType; ++ ip_Info.u8TabIdx = 0; ++ } ++ else { ++ ip_Info.pIPTable = 0; ++ ip_Info.u8TabNums = 0; ++ ip_Info.u8TabType = 0; ++ ip_Info.u8TabIdx = 0; ++ } ++ return ip_Info; ++} ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ ++static void _MDrv_PQ_LoadTableData(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize) ++{ ++ EN_IP_Info ip_Info; ++ MS_U32 u32Addr; ++ MS_U16 u16Idx = 0; ++ ++ ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ if (ip_Info.u8TabIdx >= ip_Info.u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (ip_Info.pIPTable[0]<<8) + ip_Info.pIPTable[1]; ++ pTable[u16Idx++] = ip_Info.pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+ip_Info.u8TabIdx]; ++ ++ if(u16Idx > u16TableSize || u32Addr == _END_OF_TBL_) ++ break; ++ ++ ip_Info.pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+ip_Info.u8TabNums); // next ++ } ++} ++ ++static void _MDrv_PQ_LoadTable(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ _MDrv_PQ_DumpTable(&ip_Info); ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ _MDrv_PQ_Set_LoadTableInfo_IP_Tab(u8PQIPIdx, u8TabIdx); ++#endif ++ ++} ++ ++static MS_BOOL _MDrv_PQ_LoadPictureSetting(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, void *pTable, MS_U16 u16TableSize) ++{ ++ EN_IP_Info ip_Info; ++ MS_U32 u32Addr; ++ ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ if (ip_Info.u8TabIdx >= ip_Info.u8TabNums) ++ { ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ return FALSE; ++ } ++ ++ //printf("TabType:%d TabNums:%d, TabIdx:%d addr:%x \r\n", ip_Info.u8TabType, ip_Info.u8TabNums, ip_Info.u8TabIdx, ip_Info.pIPTable); ++ ++ u32Addr = u16TableSize * ip_Info.u8TabIdx; ++ if(ip_Info.u8TabType == PQ_TABTYPE_PICTURE_1) ++ { ++ MS_U8 *pu8PQTbl = (MS_U8 *)ip_Info.pIPTable; ++ MsOS_Memcpy((MS_U8 *)pTable, &pu8PQTbl[u32Addr], sizeof(MS_U8)*u16TableSize); ++ } ++ else if(ip_Info.u8TabType == PQ_TABTYPE_PICTURE_2) ++ { ++ MS_U16 *pu16PQTbl = (MS_U16 *)ip_Info.pIPTable; ++ MsOS_Memcpy((MS_U16 *)pTable, &pu16PQTbl[u32Addr], sizeof(MS_U16)*u16TableSize); ++ ++ } ++ else ++ { ++ return FALSE; ++ } ++ ++#if 0 ++{ ++ MS_U16 u16Idx = 0; ++ for(u16Idx=0; u16Idx= PQ_TABTYPE_SRAM1 && ip_Info.u8TabType <= PQ_TABTYPE_C_SRAM1) || ++ ip_Info.u8TabType == PQ_TABTYPE_VIP_IHC_CRD_SRAM || ++ ip_Info.u8TabType == PQ_TABTYPE_VIP_ICC_CRD_SRAM) ++ { ++ continue; ++ } ++ #endif ++ _MDrv_PQ_DumpTable(&ip_Info); ++ } ++} ++ ++ ++static MS_U8 _MDrv_PQ_GetXRuleTableIndex(MS_U8 u8XRuleType, MS_U8 u8XRuleIdx, MS_U8 u8XRuleIP) ++{ ++ MS_U8 *pArray = _PQTableInfo.pXRule_Array[u8XRuleType]; ++ return pArray[((MS_U16)u8XRuleIdx) * _PQTableInfo.u8PQ_XRule_IP_Num[u8XRuleType] + u8XRuleIP]; ++} ++ ++static MS_U8 _MDrv_PQ_GetXRuleIPIndex(MS_U8 u8XRuleType, MS_U8 u8XRuleIP) ++{ ++ MS_U8 *pArray = _PQTableInfo.pXRule_IP_Index[u8XRuleType]; ++ return pArray[u8XRuleIP]; ++} ++ ++static MS_U8 _MDrv_PQ_GetXRuleIPNum(MS_U8 u8XRuleType) ++{ ++ return _PQTableInfo.u8PQ_XRule_IP_Num[u8XRuleType]; ++} ++ ++static MS_U8 _MDrv_PQ_GetGRule_LevelIndex(MS_U8 u8GRuleType, MS_U8 u8GRuleLvlIndex) ++{ ++ MS_U8 *pArray = _PQTableInfo.pGRule_Level[u8GRuleType]; ++ return pArray[u8GRuleLvlIndex]; ++} ++ ++static MS_U8 _MDrv_PQ_GetGRule_IPIndex(MS_U8 u8GRuleType, MS_U8 u8GRuleIPIndex) ++{ ++ MS_U8 *pArray = _PQTableInfo.pGRule_IP_Index[u8GRuleType]; ++ return pArray[u8GRuleIPIndex]; ++} ++ ++static MS_U8 _MDrv_PQ_GetGRule_TableIndex(MS_U8 u8GRuleType, MS_U8 u8PQSrcType, MS_U8 u8PQ_NRIdx, MS_U8 u8GRuleIPIndex) ++{ ++// return _PQTableInfo.pGRule_Array[u8PQSrcType][u8PQ_NRIdx][u8GRuleIPIndex]; ++ MS_U16 u16index; ++ MS_U8 *pArray = _PQTableInfo.pGRule_Array[u8GRuleType]; ++ ++ u16index = ((MS_U16)u8PQSrcType) * _PQTableInfo.u8PQ_GRule_Num[u8GRuleType] * _PQTableInfo.u8PQ_GRule_IPNum[u8GRuleType] + ++ ((MS_U16)u8PQ_NRIdx) * _PQTableInfo.u8PQ_GRule_IPNum[u8GRuleType] + ++ u8GRuleIPIndex; ++ return pArray[u16index]; ++} ++#endif ++ ++static void _MDrv_PQ_Set_CmdqCfg(PQ_CMDQ_CONFIG CmdqCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "[PQ]%s %d:: En=%d, FmCnt=%d\n",__FUNCTION__, __LINE__, CmdqCfg.bEnFmCnt, CmdqCfg.u8FmCnt); ++#if (ENABLE_PQ_CMDQ) ++ _bCMDQ_En = CmdqCfg.bEnFmCnt; ++ _u8CMDQ_FmCnt = CmdqCfg.bEnFmCnt ? CmdqCfg.u8FmCnt : 0; ++ _bfire_En = CmdqCfg.bfire; ++ _u16CMDQCmdCnt = 0; ++#endif ++} ++ ++static void _MDrv_PQ_Check_Type(PQ_CHECK_TYPE EnCheck) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "[PQ]%s %d:: En=%d\n", __FUNCTION__, __LINE__, EnCheck); ++ if(EnCheck == PQ_CHECK_REG) ++ { ++ _bcheckReg = 1; ++ } ++ else if(EnCheck == PQ_CHECK_SIZE) ++ { ++ _bcheckPQsize= 1; ++ } ++ else if(EnCheck == PQ_CHECK_OFF) ++ { ++ _bcheckReg = 0; ++ _bcheckPQsize= 0; ++ } ++} ++ ++ ++static void _MDrv_PQ_LoadTableByData(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx, PQ_DATA_INFO *pData) ++{ ++ EN_IP_Info ip_Info; ++ MS_U8 u8TabIdx; ++ ++ u8TabIdx = (MS_U8)_MDrv_PQ_GetTableIndex(u16PQSrcType, u8PQIPIdx); ++ ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ SCL_DBG(SCL_DBG_LV_DRVPQ(), "[PQ]%s %d::SrcType=%d, IPIdx=%d, TabType=%d\r\n" ++ ,__FUNCTION__, __LINE__, u16PQSrcType, u8PQIPIdx, ip_Info.u8TabType); ++ ++ ++ switch(ip_Info.u8TabType) ++ { ++ case PQ_TABTYPE_SCALER: ++ _MDrv_PQ_DumpSclaerRegTableByData(&ip_Info, pData); ++ break; ++ ++ default: ++ printf("[PQ]%s %d: Unsupport TabType:%d\n", __FUNCTION__, __LINE__, ip_Info.u8TabType); ++ break; ++ } ++} ++ ++ ++static void _MDrv_PQ_LoadTableBySrcType(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ MS_U8 QMIPtype_size,i; ++ MS_U8 u8TabIdx; ++ //XC_ApiStatusEx stXCStatusEx; Ryan ++ ++ if (u8PQIPIdx==PQ_IP_ALL) ++ { ++ QMIPtype_size=_PQTableInfo.u8PQ_IP_Num; ++ u8PQIPIdx=0; ++ } ++ else ++ { ++ QMIPtype_size=1; ++ } ++ ++ //for debug ++ //msAPI_Scaler_SetBlueScreen(DISABLE, 0x00); ++ //MApi_XC_GenerateBlackVideo(FALSE); ++ ++ for(i=0; i> 8)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \ ++ } \ ++ RIU_MACRO_END ++ ++#define MDrv_Write2Byte_ve( u32Reg, u16Val ) \ ++ RIU_MACRO_START \ ++ if ( ((u32Reg) & 0x01) ) \ ++ { \ ++ RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ ++ RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \ ++ } \ ++ RIU_MACRO_END ++ ++ ++#define MDrv_Write3Byte( u32Reg, u32Val ) \ ++ RIU_MACRO_START \ ++ if ((u32Reg) & 0x01) \ ++ { \ ++ RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ ++ RIU_WRITE_2BYTE( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ ++ } \ ++ RIU_MACRO_END ++ ++#define MDrv_Write4Byte( u32Reg, u32Val ) \ ++ RIU_MACRO_START \ ++ if ((u32Reg) & 0x01) \ ++ { \ ++ RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ ++ RIU_WRITE_2BYTE( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ ++ RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( (u32Reg) <<1 , u32Val); \ ++ RIU_WRITE_2BYTE( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ ++ } \ ++ RIU_MACRO_END ++ ++#define MDrv_WriteByteMask( u32Reg, u8Val, u8Msk ) \ ++ RIU_MACRO_START \ ++ RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ ++ RIU_MACRO_END ++//============================================================= ++// Just for Scaler ++ ++#define SC_R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1) & (u16mask) ) ) ++#define SC_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ ( ( RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) )) ++#define SC_W2BYTE( u32Reg, u16Val)\ ++ ( ( RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1 , u16Val ) ) ) ++#define SC_R4BYTE( u32Reg )\ ++ ( ( RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + 2 ) << 1 )) << 16)) ++#define SC_W4BYTE( u32Reg, u32Val)\ ++ RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ ++ RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) ) ++#define SC_R2BYTE( u32Reg ) \ ++ ( ( RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) <<1 ) ) ) ++ ++ ++//============================================================= ++//General ( Make sure u32Reg is not ODD ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++#define W2BYTEMSK1( u32Reg, u16Val, u16Mask)\ ++ ( ( RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ) ) ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++#define MApi_XC_ReadByte(u32Reg) MDrv_ReadByte(u32Reg) ++#define MApi_XC_WriteByteMask(u32Reg, u8Val, u8Msk) MDrv_WriteByteMask( u32Reg, u8Val, u8Msk ) ++#define MApi_XC_WriteByte(u32Reg, u8Val) MDrv_WriteByte( u32Reg, u8Val ) ++ ++#define MApi_XC_R2BYTE(u32Reg) SC_R2BYTE( u32Reg ) ++#define MApi_XC_R2BYTEMSK(u32Reg, u16mask) SC_R2BYTEMSK( u32Reg, u16mask) ++ ++#define MApi_XC_W2BYTE(u32Reg, u16Val) SC_W2BYTE( u32Reg, u16Val) ++#define MApi_XC_W2BYTEMSK(u32Reg, u16Val, u16mask) SC_W2BYTEMSK( u32Reg, u16Val, u16mask) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/include/msAPI_Scaler_Adaptive.h b/drivers/mstar/scl/infinity/src/mxlib/pq/include/msAPI_Scaler_Adaptive.h +new file mode 100644 +index 00000000..5d33151f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/include/msAPI_Scaler_Adaptive.h +@@ -0,0 +1,76 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef DRV_SCALER_ADAPTIVE_H ++#define DRV_SCALER_ADAPTIVE_H ++ ++/******************************************************************************/ ++/* Macro */ ++/* ****************************************************************************/ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++/******************************************************************************/ ++/* definition */ ++/* ****************************************************************************/ ++ ++#ifdef DRV_SCALER_NR_C ++#define INTERFACE ++#else ++#define INTERFACE extern ++#endif ++ ++/******************************************************************************/ ++/* Global Variables */ ++/******************************************************************************/ ++ ++//************************************************************************* ++// Enums ++//************************************************************************* ++ ++//************************************************************************* ++// Structures ++//************************************************************************* ++typedef enum ++{ ++ Level_Low=0, ++ Level_MID, ++ Level_High, ++ ++ MAX_Level ++}XC_CTRL_LEVEL; ++ ++/********************************************************************************/ ++/* Function Prototypes */ ++/********************************************************************************/ ++INTERFACE MS_U8 MApi_XC_GetCurrentMotionValue(void); ++INTERFACE void MApi_XC_AdaptiveTuning(void); ++INTERFACE void MApi_XC_FilmMode_AnyCandence_Enable(MS_BOOL bEnable); ++INTERFACE void MApi_XC_DBK_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel); ++INTERFACE void MApi_XC_DMS_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel); ++INTERFACE void MApi_XC_SotreCurrentValue(void); ++INTERFACE void MApi_XC_ReSotreToDefault(void); ++ ++#undef INTERFACE ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif /* DRV_SCALER_ADAPTIVE_H */ +diff --git a/drivers/mstar/scl/infinity/src/mxlib/pq/msAPI_Scaler_Adaptive.c b/drivers/mstar/scl/infinity/src/mxlib/pq/msAPI_Scaler_Adaptive.c +new file mode 100644 +index 00000000..91ee1a3f +--- /dev/null ++++ b/drivers/mstar/scl/infinity/src/mxlib/pq/msAPI_Scaler_Adaptive.c +@@ -0,0 +1,4406 @@ ++// $Change: 616729 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file drvTEMP.c ++/// @brief TEMP Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#define DRV_SCALER_ADAPTIVE_C ++ ++#ifdef UTOPIA ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++ ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++#include "MsTypes.h" ++ ++// Internal Definition ++#include "color_reg.h" ++#include "color_SC1_reg.h" ++#include "color_SC2_reg.h" ++ ++#include "drvXC_IOPort.h" ++ ++#include "apiXC.h" ++//#include "apiXC_Dlc.h" ++#include "msAPI_Scaler_Adaptive.h" ++ ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#define DRVSCA_DBG(x) //x ++#define DBG_DEFEATHERING 0 ++#define DBG_DEFLICKERING 0 ++#define DBG_DEBOUNCING 0 ++#define DBG_DYNAMIC_SNR 0 ++#define DBG_DYNAMIC_DNR 0 ++ ++// DeFeathering ++#define MDP_CNT 2 ++#define ENABLE_MDP 0 //Motion decrase progressively enable ++ ++#define DEFETHERING_LV1_TH 30000 ++#define DEFETHERING_LV2_TH 5000 ++#define DEFETHERING_LV3_TH 2000 ++#define DEFETHERING_LV1_CNT 25 ++#define DEFETHERING_LV2_CNT 20 ++#define DEFETHERING_LV3_CNT 5 ++ ++#define SST_STATIC_CORE_TH_LV1_VALUE 0x14 //ryan update ++#define SST_STATIC_CORE_TH_LV2_VALUE 0x0C //ryan update ++#define SST_STATIC_CORE_TH_LV3_VALUE 0x06 //ryan update ++#define SST_STATIC_CORE_TH_LV4_VALUE 0x00 //ryan update ++ ++// DeFlickering ++#define DEFLICKERING_TH 52000 ++#define DEFLICKERING_CNT 150 ++ ++// DeBouncing ++#define DEBOUNCING_TH 35000 ++#define DEBOUNCING_CNT 10 ++ ++// Dynamic SNR ++#define DYNAMIC_SNR_TH 2000 ++#define DYNAMIC_SNR_CNT 30 ++ ++// Dynamic DNR ++//#define DYNAMIC_DNR_TH 6000 ++ ++#define DNR_TABLEY_0L_Zero_VALUE 0xDD ++#define DNR_TABLEY_0H_Zero_VALUE 0xBD ++#define DNR_TABLEY_1L_Zero_VALUE 0x79 ++#define DNR_TABLEY_1H_Zero_VALUE 0x35 ++#define DNR_TABLEY_2L_Zero_VALUE 0x11 ++#define DNR_TABLEY_2H_Zero_VALUE 0x00 ++#define DNR_TABLEY_3L_Zero_VALUE 0x00 ++#define DNR_TABLEY_3H_Zero_VALUE 0x00 ++ ++#define DNR_TABLEY_0L_LV2_VALUE 0xCC ++#define DNR_TABLEY_0H_LV2_VALUE 0xAC ++#define DNR_TABLEY_1L_LV2_VALUE 0x68 ++#define DNR_TABLEY_1H_LV2_VALUE 0x24 ++#define DNR_TABLEY_2L_LV2_VALUE 0x00 ++#define DNR_TABLEY_2H_LV2_VALUE 0x00 ++#define DNR_TABLEY_3L_LV2_VALUE 0x00 ++#define DNR_TABLEY_3H_LV2_VALUE 0x00 ++ ++#define DNR_TABLEY_0L_LV3_VALUE 0x67 ++#define DNR_TABLEY_0H_LV3_VALUE 0x45 ++#define DNR_TABLEY_1L_LV3_VALUE 0x33 ++#define DNR_TABLEY_1H_LV3_VALUE 0x22 ++#define DNR_TABLEY_2L_LV3_VALUE 0x11 ++#define DNR_TABLEY_2H_LV3_VALUE 0x00 ++#define DNR_TABLEY_3L_LV3_VALUE 0x00 ++#define DNR_TABLEY_3H_LV3_VALUE 0x00 ++ ++// Dynamic Film 22 ++#define DYNAMIC_FILM22_TH 520000 ++ ++extern MS_U16 _u16PQSrcType_DBK_Detect[PQ_MAX_WINDOW]; //For Auto_DBK SW driver used ++static MS_U16 _u16PQPre_SrcType = 255; //For Auto_DBK SW driver used ++static MS_BOOL data_read = true; //For Auto_DBK SW driver used ++ ++ ++#define Auto_DeBlock_En TRUE ++//------------------------------------------------------------------------------------------------- ++// Local Structurs ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL g_bAnyCandenceEnable = TRUE; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8)MApi_XC_R2BYTEMSK(REG_SC_BK22_7C_L, 0xFF); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl2(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8)(MApi_XC_R2BYTEMSK(REG_SC_BK22_7C_L, 0xFF00) >> 8); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl3(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8) (MApi_XC_R2BYTEMSK(REG_SC_BK30_01_L, 0x8000) >> 8); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl4(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8)(MS_U8)MApi_XC_R2BYTEMSK(REG_SC_BK22_7E_L, 0xFF); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Read motion value (F2 motion status) ++///@return MS_U8: Motion value ++/******************************************************************************/ ++MS_U32 MDrv_SC_read_motion_value1(void) ++{ ++ ++ MS_U32 u32MotionValue; ++ MS_U32 u32RegMadi_1C, u32RegMadi_1B, u32RegMadi_1A; ++ ++ u32RegMadi_1C = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0E_L, 0x3F); ++ u32RegMadi_1B = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0D_L, 0xFF00); ++ u32RegMadi_1A = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0D_L, 0x00FF); ++ ++ u32RegMadi_1C = u32RegMadi_1C * 0x10000UL; ++ ++ u32MotionValue = (u32RegMadi_1C + u32RegMadi_1B + u32RegMadi_1A) ; ++ ++ DRVSCA_DBG(printf("MotionValue = 0x%lx\n", u32MotionValue)); ++ ++ return u32MotionValue; ++} ++ ++/******************************************************************************/ ++///Read motion value (Motion count status) ++///@return MS_U8: Motion value ++/******************************************************************************/ ++MS_U32 MDrv_SC_read_motion_value2(void) ++{ ++ ++ MS_U32 u32MotionValue; ++ ++ u32MotionValue = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK0A_1A_L, 0x7F); ++ ++ return u32MotionValue; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Read motion value (Motion count status) ++/// @return MS_U8: Motion value ++//------------------------------------------------------------------------------------------------- ++MS_U8 MApi_XC_GetCurrentMotionValue(void) ++{ ++ ++ MS_U8 u8MotionValue; ++ ++ u8MotionValue = (MS_U8)((MApi_XC_R2BYTEMSK(REG_SC_BK22_0E_L, 0x3F) << 2) | ++ (MApi_XC_R2BYTEMSK(REG_SC_BK22_0D_L, 0xC000) >> 6)); ++ ++ return u8MotionValue; ++} ++ ++/******************************************************************************/ ++///Read VCnt value ++///@return MS_U8: VCnt value ++/******************************************************************************/ ++MS_U8 MDrv_SC_read_v_cnt(void) ++{ ++ MS_U8 u8VCnt; ++ ++ u8VCnt = (MS_U8)(MApi_XC_R2BYTEMSK(REG_SC_BK22_0E_L, 0xC0) >> 6); ++ return u8VCnt; ++} ++ ++/******************************************************************************/ ++///Read SDHDD Detect Threshold value ++///@return MS_U16: HDSDD_Det_Threshold value ++/******************************************************************************/ ++MS_U16 MDrv_SC_read_HDSDD_Det_Threshold_value(void) ++{ ++ ++ MS_U16 u16Value; ++ ++ u16Value = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ return u16Value; ++} ++ ++/******************************************************************************/ ++///MCDi Driver ++/******************************************************************************/ ++#define ENABLE_XXX_V_MOVING 0x01 ++#define ENABLE_XXX_SST 0x02 ++#define ENABLE_XXX_EodiWeight 0x04 ++ ++ ++void MDrv_SC_mcdi_driver(MS_U32 u32MotionValue) ++{ ++ MS_U32 u32Reg78, u32Reg79, u32Reg7A, u32Reg7B, u32Reg7C, u32Reg7D, u32Reg7E, filmFeatherCount; ++ MS_U32 curCounter3, cntDiff; ++ MS_U8 u8xxxCtrl; ++ MS_BOOL verticalMovingU, horizontalMoving, slowMotion, featheringScene, featheringScene2; ++ static MS_U8 u8SkipCnt; ++ static MS_U8 featheringFrameCount; ++ static MS_U8 s8DeBouncingCnt; ++ static MS_U8 stillFrameCnt; ++ static MS_U8 filmCnt = 0; ++ static MS_U32 preCounter3 = 0; ++ static MS_U8 eodiCnt = 0; ++ MS_BOOL skipCond; ++ MS_BOOL verticalMoving2; ++ MS_BOOL filmDisableMCDiDFK; ++ ++ MS_U16 reg_debouncing_th, reg_debouncing_cnt; ++ MS_BOOL film; ++ ++ u8xxxCtrl = 0xFF; //MApi_XC_R2BYTE(REG_SC_BK2A_1F_L) >> 8; ++ ++ u32Reg78 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ u32Reg79 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ u32Reg7A = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ u32Reg7B = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); ++ u32Reg7C = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32Reg7D = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32Reg7E = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ filmFeatherCount = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ //if(!MirrorEnable) ++ if(MApi_XC_GetMirrorModeType(MAIN_WINDOW) == MIRROR_NORMAL) ++ { ++ //Non_Mirror ++ verticalMovingU = (u32Reg7E > 0x0100) && (u32Reg7E > 8 * u32Reg7C) && (u32Reg7E > 8 * u32Reg7D); ++ verticalMoving2 = (((u32Reg7E > 0x200) && (u32Reg7E > u32Reg7C)) || ((u32Reg7D > 0x200) && (u32Reg7D > u32Reg7C))); ++ horizontalMoving = (u32Reg79 > 0x200) && (u32Reg7B < 0x40) && (u32Reg79 > u32Reg78) && (!verticalMoving2); ++ slowMotion = (u32Reg7A > 0x200) && (u32Reg7B < 0x40) && (!verticalMoving2); ++ //featheringScene = (u32MotionValue > 0x0F) && (u32Reg7B > 0x800); ++ featheringScene = (u32Reg7B > 0x100) && (u32Reg7B > u32Reg79 / 4) && (u32Reg7B > u32Reg7A / 4); ++ skipCond = (u32Reg7A > 8 * u32Reg79) && (u32Reg7B > 0x600); ++ featheringScene2 = (u32Reg7B > 0x200) && (u32Reg7B > u32Reg79 / 8) && (u32Reg7B > u32Reg7A / 8); ++ } ++ else ++ { ++ //Mirror ++ verticalMovingU = (u32Reg7D > 0x0100) && (u32Reg7D > 8 * u32Reg7C) && (u32Reg7D > 8 * u32Reg7E); ++ verticalMoving2 = (((u32Reg7D > 0x200) && (u32Reg7D > u32Reg7C)) || ((u32Reg7E > 0x200) && (u32Reg7E > u32Reg7C))); ++ horizontalMoving = (u32Reg79 > 0x200) && (u32Reg7B < 0x40) && (u32Reg79 > u32Reg78) && (!verticalMoving2); ++ slowMotion = (u32Reg7A > 0x200) && (u32Reg7B < 0x40) && (!verticalMoving2); ++ //featheringScene = (u32MotionValue > 0x0F) && (u32Reg7B > 0x800); ++ featheringScene = (u32Reg7B > 0x100) && (u32Reg7B > u32Reg79 / 4) && (u32Reg7B > u32Reg7A / 4); ++ skipCond = (u32Reg7A > 8 * u32Reg79) && (u32Reg7B > 0x600); ++ featheringScene2 = (u32Reg7B > 0x200) && (u32Reg7B > u32Reg79 / 8) && (u32Reg7B > u32Reg7A / 8); ++ } ++ ++ if(false == skipCond) ++ { ++ if(u8SkipCnt == 0) ++ u8SkipCnt = 0; ++ else ++ u8SkipCnt--; ++ } ++ else ++ { ++ if(u8SkipCnt > 0x40) ++ u8SkipCnt = 0x40; ++ else ++ u8SkipCnt++; ++ } ++ ++ if(filmFeatherCount > 0x100) ++ { ++ if(featheringFrameCount < 0x80) ++ featheringFrameCount ++; ++ } ++ else ++ { ++ featheringFrameCount = 0; ++ } ++ ++ if((u32MotionValue == 0) && (u32Reg7B < 0x20)) ++ { ++ if(stillFrameCnt < 0x20) ++ stillFrameCnt ++; ++ } ++ else ++ { ++ stillFrameCnt = 0; ++ } ++ ++ //////////////////////////////////////////////////////////////// ++ // film content disable mcdi/dfk ++ //////////////////////////////////////////////////////////////// ++ ++ curCounter3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ cntDiff = (preCounter3 > curCounter3) ? preCounter3 - curCounter3 : curCounter3 - preCounter3; ++ ++ if(cntDiff > 0x1500) ++ { ++ if(filmCnt != 10) ++ filmCnt++; ++ } ++ else if(filmCnt != 0) ++ { ++ filmCnt--; ++ } ++ ++ preCounter3 = curCounter3; ++ //printf("filmCnt = [%x]\n", filmCnt); ++ filmDisableMCDiDFK = (filmCnt > 5); ++ ++ //////////////////////////////////////////////////////////////// ++ // eodi counter ++ //////////////////////////////////////////////////////////////// ++ ++ if(featheringScene2) ++ { ++ if(eodiCnt < 40) ++ eodiCnt += 4; ++ } ++ else ++ { ++ if(eodiCnt > 0) ++ eodiCnt--; ++ } ++ ++ ++ ///////////////////////////////////////////////////////////////// ++ // SST (De-Feathering) ++ ///////////////////////////////////////////////////////////////// ++ if(u8xxxCtrl & ENABLE_XXX_SST) ++ { ++ if(featheringScene || filmDisableMCDiDFK) // moving & feather ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x3100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0100, 0x0F00); // SST motion shift1 ++ } ++ else if((u32Reg79 > 0x200) && (u32Reg7B < 0x40)) // patch sony temple ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x1100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0200, 0x0F00); // SST motion shift1 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x3100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0100, 0x0F00); // SST motion shift1 ++ } ++ } ++ ++ // disable DFK when verticalMovingU ++ if((true == verticalMovingU) || (u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // default DFK ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x2000, 0xF000); // default DFK ++ } ++ ++ // Favor MCDi-V when verticalMovingU ++ if(true == verticalMovingU) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0800, 0x0800); // Enable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x0FF0, 0xFFFF); // favor MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x2800, 0x3C00); // enable MCDi U for blending and history ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // reduce motion history ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0000, 0x0800); // Disable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x8888, 0xFFFF); // default MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x0000, 0x3C00); // Use MCDi-H as default ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // default MCDi motion history ++ } ++ ++ // DFK EodiW1, 2 ++ if((s8DeBouncingCnt < 0x3) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if((true == verticalMovingU) || verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW -> LG tower ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x2c30, 0xFF30); // disable EodiW for DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x18F1, 0xFF30); // default ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0040, 0x00F0); // default DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c10, 0xFF30); // default ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4488, 0x00F0); ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x0020, 0x00F0); ++ ++ // DFK check feathering gain ++ if((stillFrameCnt > 0x8) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0100, 0x0F00); ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // reduce DFK feathering weight ++ } ++ else if(u32Reg7B > 0x100) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // feather -> increase ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // default for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // default ++ } ++ ++ // EodiWeight for MCDi ++ if(true == verticalMovingU) ++ { ++ //if ( u32Reg7A > 0x200 && u32Reg7A/4 > u32Reg79 ) // not-found >> horizontal : Church ++ if((u32Reg7A > 0x100) && (u32Reg7A / 2 > u32Reg79)) // not-found >> horizontal : Church ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); // church ++ } ++ else // LG Tower ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4200, 0xFF0F); // LG Tower ++ } ++ } ++ else if((false == verticalMovingU) && horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x1800, 0xFF0F); // reduce EodiW for MCDi ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4408, 0xFF0F); ++ } ++ else if(eodiCnt > 25) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0001, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4400, 0xFF0F); ++ } ++ else if(eodiCnt < 10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC830, 0xFFFF); // reduce EodiW on MCDi ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC832, 0xFFFF); // reduce EodiW on MCDi ++ ++ // MCDi check Feathering weight ++ if((true == verticalMovingU) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight -> for church ++ } ++ else if(horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0060, 0x00F0); // default MCDi Feathering Weight ++ } ++ // multi-burst skip ++ if((u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0000, 0x0080); // disable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(u8SkipCnt < 0x10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0080, 0x0080); // enable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xc000, 0xF000); // ++ ++ ///////////////////////////////////////////////////////////////// ++ // De-bouncing ++ ///////////////////////////////////////////////////////////////// ++ ++ ++ ++ reg_debouncing_th = 0x0A; ++ reg_debouncing_cnt = 0x03; ++ ++ if(u32MotionValue <= reg_debouncing_th) ++ { ++ s8DeBouncingCnt = 0; ++ } ++ else ++ { ++ if(s8DeBouncingCnt < 0xff) ++ s8DeBouncingCnt++; ++ } ++ ++ ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ if((s8DeBouncingCnt >= reg_debouncing_cnt) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x0004, 0x000e); // history weight = 1 ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 1 ++ } ++ /* ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_17_L, (MS_U16)0x02c0, 0xFFFF); // fetch no. ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_07_L, (MS_U16)0x2088, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x1000, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_12_L, (MS_U16)0x0000, 0x0001); // disable CCS ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, (MS_U16)0x0000, 0x0001); // disable DHD ++ */ ++} ++ ++void MDrv_SC_mcdi_driver_new(MS_U32 u32MotionValue, MS_U8 u8MotLvl) ++{ ++ MS_U32 u32Reg78, u32Reg79, u32Reg7A, u32Reg7B, u32Reg7C, u32Reg7D, u32Reg7E, filmFeatherCount; ++ MS_U32 curCounter3, cntDiff; ++ MS_U8 u8xxxCtrl; ++ MS_BOOL verticalMovingU, horizontalMoving, slowMotion, featheringScene, featheringScene2, movingScene; ++ static MS_U8 u8SkipCnt; ++ static MS_U8 featheringFrameCount; ++ static MS_U8 s8DeBouncingCnt; ++ //static MS_U8 stillFrameCnt; ++ static MS_U8 filmCnt = 0; ++ static MS_U32 preCounter3 = 0; ++ static MS_U8 eodiCnt = 0; ++ static MS_U8 verticalMovingUCnt = 0; ++ MS_BOOL skipCond; ++ MS_BOOL verticalMoving2; ++ MS_BOOL filmDisableMCDiDFK; ++ ++ MS_BOOL film; ++ ++ ++ u8xxxCtrl = 0xFF; //MApi_XC_R2BYTE(REG_SC_BK2A_1F_L) >> 8; ++ u32Reg78 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); // isMV0 ++ u32Reg79 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); // Horzontal Moving ++ u32Reg7A = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); // MV not found ++ u32Reg7B = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); // Feathering ++ u32Reg7C = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32Reg7D = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32Reg7E = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ filmFeatherCount = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ //printf("motion level = %x\n", u8MotLvl ); ++// if(!MirrorEnable) ++ if(MApi_XC_GetMirrorModeType(MAIN_WINDOW) == MIRROR_NORMAL) ++ { ++ //Non_Mirror ++ verticalMovingU = ((u32Reg7E > 0x0100) && (u32Reg7E / 8 > u32Reg7C) && (u32Reg7E / 8 > u32Reg7D) && (u32Reg78 > u32Reg79 / 8)) || ++ ((u32Reg7E > 0x0040) && (u32Reg7E / 32 > u32Reg7C) && (u32Reg7E / 32 > u32Reg7D) && (u32Reg78 > u32Reg79 / 8)); ++ movingScene = (u32Reg7E > 0x0080) && (u32Reg7E / 4 > u32Reg7C) && (u32Reg7E / 4 > u32Reg7D) && // V-moving-up && ++ (u32Reg79 > 0x0200) && (u32Reg79 / 4 > u32Reg78); // H-moving ++ } ++ else ++ { ++ //Mirror ++ verticalMovingU = ((u32Reg7D > 0x0100) && (u32Reg7D / 8 > u32Reg7C) && (u32Reg7D / 8 > u32Reg7E) && (u32Reg78 > u32Reg79 / 8)) || ++ ((u32Reg7D > 0x0040) && (u32Reg7D / 32 > u32Reg7C) && (u32Reg7D / 32 > u32Reg7E) && (u32Reg78 > u32Reg79 / 8)); ++ movingScene = (u32Reg7D > 0x0080) && (u32Reg7D / 4 > u32Reg7C) && (u32Reg7D / 4 > u32Reg7E) && // V-moving-up && ++ (u32Reg79 > 0x0200) && (u32Reg79 / 4 > u32Reg78); // H-moving ++ } ++ ++ verticalMoving2 = (((u32Reg7E > 0x200) && (u32Reg7E > u32Reg7C)) || ((u32Reg7D > 0x200) && (u32Reg7D > u32Reg7C))) && (u32Reg78 > u32Reg79 / 8); ++ ++ /*verticalMovingU = ( (u32Reg7E > 0x0100) && (u32Reg7E/8 > u32Reg7C) && (u32Reg7E/8 > u32Reg7D) && (u32Reg78 > u32Reg79) ) || ++ ( (u32Reg7E > 0x0040) && (u32Reg7E/32 > u32Reg7C) && (u32Reg7E/32 > u32Reg7D) && (u32Reg78 > u32Reg79) ); ++ verticalMoving2 = ( ( u32Reg7E > 0x200 && u32Reg7E > u32Reg7C ) || ( u32Reg7D > 0x200 && u32Reg7D > u32Reg7C ) ) && (u32Reg78 > u32Reg79); ++ *///ian ++ ++ //horizontalMoving = u32Reg79 > 0x200 && u32Reg7B < 0x40 && u32Reg79 > u32Reg78 && !verticalMoving2; ++ horizontalMoving = (u32Reg79 > 0x200) && (u32Reg79 / 16 > u32Reg78) && (u32Reg79 > u32Reg7A / 2) && ++ (u32Reg7C > 0x100) && (u32Reg7C / 2 > u32Reg7D) && (u32Reg7C / 2 > u32Reg7E) ; ++ ++ /* horizontalMoving = u32Reg79 > 0x200 && u32Reg79/16 > u32Reg78 && u32Reg79/4 > u32Reg7A && ++ u32Reg7C > 0x100 && u32Reg7C/4 > u32Reg7D && u32Reg7C/4 > u32Reg7E ; ++ *///ian ++ ++ slowMotion = (u32Reg7A > 0x200) && (u32Reg7B < 0x40) && (!verticalMoving2); ++ //featheringScene = (u32MotionValue > 0x0F) && (u32Reg7B > 0x800); ++ featheringScene = (u32Reg7B > 0x100) && (u32Reg7B > u32Reg79 / 4) && (u32Reg7B > u32Reg7A / 4) && (u32MotionValue > 0x10); ++ skipCond = (u32Reg7A > 8 * u32Reg79) && (u32Reg7B > 0x600); ++ featheringScene2 = (u32Reg7B > 0x200) && (u32Reg7B > u32Reg79 / 8) && (u32Reg7B > u32Reg7A / 8) && (!horizontalMoving) && (u32MotionValue > 0x10); ++ ++#if 0 ++ if(true == verticalMovingU) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x1000, 0xFFFF); // show verticalMovingU ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x0000, 0xFFFF); // show verticalMovingU ++ } ++#endif ++ ++ if(verticalMovingU) ++ { ++ if(verticalMovingUCnt != 0xff) ++ { ++ verticalMovingUCnt ++; ++ } ++ } ++ else ++ { ++ verticalMovingUCnt = 0; ++ } ++ ++ if(false == skipCond) ++ { ++ if(u8SkipCnt == 0) ++ u8SkipCnt = 0; ++ else ++ u8SkipCnt--; ++ } ++ else ++ { ++ if(u8SkipCnt > 0x40) ++ u8SkipCnt = 0x40; ++ else ++ u8SkipCnt++; ++ } ++ ++ if(filmFeatherCount > 0x100) ++ { ++ if(featheringFrameCount < 0x80) ++ featheringFrameCount ++; ++ } ++ else ++ { ++ featheringFrameCount = 0; ++ } ++ /* ++ if ( u32MotionValue == 0 && u32Reg7B < 0x20 ) ++ { ++ stillFrameCnt = 0x20; ++ } ++ else ++ { ++ stillFrameCnt = 0; ++ } ++ */ ++ //////////////////////////////////////////////////////////////// ++ // film content disable mcdi/dfk ++ //////////////////////////////////////////////////////////////// ++ ++ curCounter3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ cntDiff = (preCounter3 > curCounter3) ? preCounter3 - curCounter3 : curCounter3 - preCounter3; ++ ++ if(cntDiff > 0x1500) ++ { ++ if(filmCnt != 10) ++ filmCnt++; ++ } ++ else if(filmCnt != 0) ++ { ++ filmCnt--; ++ } ++ ++ preCounter3 = curCounter3; ++ //printf("filmCnt = [%x]\n", filmCnt); ++ filmDisableMCDiDFK = (filmCnt > 5); ++ ++ //////////////////////////////////////////////////////////////// ++ // eodi counter ++ //////////////////////////////////////////////////////////////// ++ ++ if(featheringScene2) ++ { ++ if(eodiCnt < 40) ++ eodiCnt += 4; ++ } ++ else ++ { ++ if(eodiCnt > 0) ++ eodiCnt--; ++ } ++ ++ ///////////////////////////////////////////////////////////////// ++ // SST (De-Feathering) ++ ///////////////////////////////////////////////////////////////// ++ if(u8xxxCtrl & ENABLE_XXX_SST) ++ { ++ if(movingScene || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0xF100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x0F00); // SST motion shift1 ++ } ++ /* ++ else if ( (u32Reg79 > 0x200 && u32Reg7B < 0x40) || (stillFrameCnt>=10) ) // patch sony temple, but champion bubble !? ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x1100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0200, 0x0F00); // SST motion shift1 ++ } ++ */ ++ else if((u32MotionValue < 0x10) && (u32Reg7B > 0x1000)) // special patch for Toshiba... -> tend to still ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x3100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0200, 0x0F00); // SST motion shift1 ++ } ++ else if(featheringScene) // moving & feather ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0xF100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x0F00); // SST motion shift1 ++ } ++ else if((u8MotLvl >= 3) && (u32Reg7B > 0x40) && (u32Reg7B > u32Reg7A / 16)) // for sony champion bubbles ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0xF100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x0F00); // SST motion shift1 ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x2100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0100, 0x0F00); // SST motion shift1 ++ } ++ } ++ ++ // disable DFK when verticalMovingU ++ if((true == verticalMovingU) || (u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // default DFK ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x2000, 0xF000); // default DFK ++ } ++ ++ if(verticalMovingUCnt > 0x20) // for church ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x0FF0, 0xFFFF); // favor MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x2800, 0x3C0F); // enable MCDi U for blending and history ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x8888, 0xFFFF); // default MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x0000, 0x3C0F); // Use MCDi-H as default ++ } ++ ++ // Favor MCDi-V when verticalMovingU ++ if(1) //true == verticalMovingU ) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0800, 0x0800); // Enable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // reduce motion history ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0800, 0x0800); // Disable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // default MCDi motion history ++ } ++ ++ // DFK EodiW1, 2 ++ if((s8DeBouncingCnt < 0x3) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if((true == verticalMovingU) || verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW -> LG tower ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x2c30, 0xFF30); // disable EodiW for DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x18F1, 0xFF30); // default ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0040, 0x00F0); // default DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c10, 0xFF30); // default ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4488, 0x00F0); ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x0020, 0x00F0); ++ ++ // DFK check feathering gain ++ if(filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xf000, 0xF000); // ++ } ++ else if(u32MotionValue == 0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // reduce DFK feathering weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x1000, 0xF000); // ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // reduce DFK feathering weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x1000, 0xF000); // ++ } ++ else if(u32Reg7B > 0x100) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // feather -> increase ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xc000, 0xF000); // ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // default for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // default ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x4000, 0xF000); // ++ } ++ ++ // EodiWeight for MCDi ++ if(true == verticalMovingU) ++ { ++ //if ( u32Reg7A > 0x200 && u32Reg7A/4 > u32Reg79 ) // not-found >> horizontal : Church ++ if((u32Reg7A > 0x100) && (u32Reg7A / 2 > u32Reg79)) // not-found >> horizontal : Church ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); // church ++ } ++ else // LG Tower ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4200, 0xFF0F); // LG Tower ++ } ++ } ++ else if((false == verticalMovingU) && horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x1800, 0xFF0F); // reduce EodiW for MCDi ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4408, 0xFF0F); ++ } ++ else if(eodiCnt > 25) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0001, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4400, 0xFF0F); ++ } ++ else if(eodiCnt < 10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8)) && (!horizontalMoving)) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC830, 0xFFFF); // reduce EodiW on MCDi ++ else if(!horizontalMoving) ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC832, 0xFFFF); // reduce EodiW on MCDi ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC836, 0xFFFF); ++ ++ // MCDi check Feathering weight ++ if(filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0060, 0x00F0); // reduce MCDi feathering weight -> for church ++ } ++ else if(true == verticalMovingU) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight -> for church ++ } ++ else if(horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0060, 0x00F0); // default MCDi Feathering Weight ++ } ++ // multi-burst skip ++ if((u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0000, 0x0080); // disable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(u8SkipCnt < 0x10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0080, 0x0080); // enable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK ++ } ++ ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xc000, 0xF000); // ++ if(u32MotionValue == 0) // still picture -> tend to still ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x0800, 0x0FFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x00FF); // ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x0888, 0x0FFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0088, 0x00FF); // ++ } ++ ++ ///////////////////////////////////////////////////////////////// ++ // De-bouncing ++ ///////////////////////////////////////////////////////////////// ++#if 0 ++ MS_U16 reg_debouncing_th, reg_debouncing_cnt; ++ ++ reg_debouncing_th = 0x0A; ++ reg_debouncing_cnt = 0x03; ++ ++ if(u32MotionValue <= reg_debouncing_th) ++ { ++ s8DeBouncingCnt = 0; ++ } ++ else ++ { ++ if(s8DeBouncingCnt < 0xff) ++ s8DeBouncingCnt++; ++ } ++ ++ MS_BOOL film; ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ ++ if((s8DeBouncingCnt >= reg_debouncing_cnt) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x0004, 0x000e); // history weight = 2 ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 1 ++ } ++#endif ++ ++ ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ if((u8MotLvl >= 1) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x0004, 0x000e); // history weight = 2 ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 1 ++ } ++ /* ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_17_L, (MS_U16)0x02c0, 0xFFFF); // fetch no. ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_07_L, (MS_U16)0x2088, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x1000, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_12_L, (MS_U16)0x0000, 0x0001); // disable CCS ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, (MS_U16)0x0000, 0x0001); // disable DHD ++ */ ++} ++ ++#define MF_Gain 30 ++MS_U32 MDrv_SC_T12_UC_SmallMoving(void) ++{ ++ MS_U32 before_MC_feather; ++ MS_U32 nonMV0_Comfirm, MV_Contradict; ++ MS_U32 MovingFeather, MV_Confirm; ++ static MS_U32 PrevMV_Confirm = 0; ++ ++ before_MC_feather = MApi_XC_R2BYTE(REG_SC_BK2A_77_L) ; ++ nonMV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ MV_Contradict = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ MV_Confirm = (nonMV0_Comfirm + MV_Contradict) >> 1; ++ ++ MV_Confirm = (PrevMV_Confirm * 3 + MV_Confirm) >> 2; ++ PrevMV_Confirm = MV_Confirm; ++ ++ if(MV_Confirm > (before_MC_feather * MF_Gain)) ++ MovingFeather = MV_Confirm - ((before_MC_feather * MF_Gain)) ; ++ else ++ MovingFeather = 0; ++ ++ return MovingFeather; // "Big": in seach range "Small": out of seach range ++} ++ ++#define OOSRF_Gain 4 ++#define OOSRF_Power 2 ++MS_U32 MDrv_SC_T12_UC_InSearchRange_Feather(void) ++{ ++ MS_U32 before_MC_feather, after_MC_feather; ++ MS_U32 MC_OOSRF; ++ static MS_U32 Prev_before_MC_feather = 0; ++ static MS_U32 Prev_after_MC_feather = 0; ++ ++ before_MC_feather = MApi_XC_R2BYTE(REG_SC_BK2A_77_L) ; ++ after_MC_feather = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); ++ ++ before_MC_feather = (Prev_before_MC_feather * 3 + before_MC_feather) >> 2; ++ Prev_before_MC_feather = before_MC_feather; ++ ++ after_MC_feather = (Prev_after_MC_feather * 3 + after_MC_feather) >> 2; ++ Prev_after_MC_feather = after_MC_feather; ++ ++ if(before_MC_feather > (after_MC_feather * OOSRF_Gain) >> OOSRF_Power) ++ MC_OOSRF = before_MC_feather - ((after_MC_feather * OOSRF_Gain) >> OOSRF_Power) ; ++ else ++ MC_OOSRF = 0; ++ ++ return MC_OOSRF; // "Big": in seach range "Small": out of seach range ++} ++ ++ ++#define OOSRMC_Gain 20 ++MS_U32 MDrv_SC_T12_UC_InSearchRange_MvComfirm(void) ++{ ++ MS_U32 MV0_Comfirm, nonMV0_Comfirm, MV_Contradict; ++ static MS_U32 Prev_MV0_Comfirm = 0; ++ static MS_U32 Prev_nonMV0_Comfirm = 0; ++ static MS_U32 Prev_MV_Contradict = 0; ++ MS_U32 MV_Comfirm, MC_OOSRMC; ++ ++ MV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ nonMV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ MV_Contradict = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ MV0_Comfirm = (Prev_MV0_Comfirm * 3 + MV0_Comfirm) >> 2; ++ Prev_MV0_Comfirm = MV0_Comfirm; ++ ++ nonMV0_Comfirm = (Prev_nonMV0_Comfirm * 3 + nonMV0_Comfirm) >> 2; ++ Prev_nonMV0_Comfirm = nonMV0_Comfirm; ++ ++ MV_Contradict = (Prev_MV_Contradict * 3 + MV_Contradict) >> 2; ++ Prev_MV_Contradict = MV_Contradict; ++ ++ MV_Comfirm = MV0_Comfirm + nonMV0_Comfirm; ++ ++ if(MV_Comfirm > MV_Contradict * OOSRMC_Gain) ++ MC_OOSRMC = MV_Comfirm - MV_Contradict * OOSRMC_Gain; ++ else ++ MC_OOSRMC = 0; ++ ++ return MC_OOSRMC; // "Big": in seach range "Small": out of seach range ++ ++} ++ ++#define ISR_NONMV0_Gain 15 ++MS_U32 MDrv_SC_T12_UC_InSearchRange_nonMv0Comfirm(void) ++{ ++ MS_U32 MV0_Comfirm, nonMV0_Comfirm, MV_Contradict; ++ static MS_U32 Prev_MV0_Comfirm = 0; ++ static MS_U32 Prev_nonMV0_Comfirm = 0; ++ static MS_U32 Prev_MV_Contradict = 0; ++ MS_U32 MV_Comfirm, Comfirm_Value; ++ ++ MV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ nonMV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ MV_Contradict = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ MV0_Comfirm = (Prev_MV0_Comfirm * 3 + MV0_Comfirm) >> 2; ++ Prev_MV0_Comfirm = MV0_Comfirm; ++ ++ nonMV0_Comfirm = (Prev_nonMV0_Comfirm * 3 + nonMV0_Comfirm) >> 2; ++ Prev_nonMV0_Comfirm = nonMV0_Comfirm; ++ ++ MV_Contradict = (Prev_MV_Contradict * 3 + MV_Contradict) >> 2; ++ Prev_MV_Contradict = MV_Contradict; ++ ++ MV_Comfirm = /*MV0_Comfim +*/nonMV0_Comfirm; ++ ++ if(MV_Comfirm > MV_Contradict * ISR_NONMV0_Gain) ++ Comfirm_Value = MV_Comfirm - MV_Contradict * ISR_NONMV0_Gain; ++ else ++ Comfirm_Value = 0; ++ ++ return Comfirm_Value; // "Big": in seach range "Small": out of seach range ++ ++} ++ ++void MDrv_SC_T12_DIPF_TemporalGainControl(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 TemporalGainControl = 0x0F; ++ ++ //printf("====OOSRMC=%x===\n",OOSRMC); ++ //printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(TemporalGainControl > 0x00) ++ TemporalGainControl--; ++ else ++ TemporalGainControl = 0; ++ } ++ else ++ { ++ if(TemporalGainControl < 0x0F) ++ TemporalGainControl++; ++ else ++ TemporalGainControl = 0x0F; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_14_L, (MS_U16)TemporalGainControl, 0x000F); ++ ++} ++ ++#define ComplexOffset_MaxValue 0x06 ++#define ComplexOffset_MinValue 0x00 ++void MDrv_SC_T12_UCDi_ComplexOffset(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 ComplexOffset = ComplexOffset_MaxValue; ++ ++ //printf("====OOSRMC=%x===\n",OOSRMC); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(ComplexOffset > ComplexOffset_MinValue) ++ ComplexOffset--; ++ else ++ ComplexOffset = ComplexOffset_MinValue; ++ } ++ else ++ { ++ if(ComplexOffset < ComplexOffset_MaxValue) ++ ComplexOffset++; ++ else ++ ComplexOffset = ComplexOffset_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)ComplexOffset << 4, 0x00F0); ++ ++} ++ ++#define OP1_HisWeight_MaxValue 0x0E ++#define OP1_HisWeight_MinValue 0x04 ++void MDrv_SC_T12_UCDi_OP1_HisWeight(MS_U8 u8MotLvl) ++{ ++ MS_BOOL film; ++ ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ if((u8MotLvl >= 1) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, OP1_HisWeight_MaxValue, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, OP1_HisWeight_MinValue, 0x000e); // history weight = 2 ++ } ++} ++ ++#define A5_HIS_MOTION_TH 0x0A ++void MDrv_SC_A5_UCDi_OP1_HisWeight(const MS_U32 u32MotionValue) ++{ ++ //MS_BOOL film; ++ static MS_U32 reg_his_weight = OP1_HisWeight_MinValue; ++ ++ //MS_U8 motion_level; ++ static MS_U32 u32MotionValue_prev = 0; ++ ++ if( u32MotionValue_prev < u32MotionValue ) ++ u32MotionValue_prev = ((u32MotionValue_prev*3 )+ u32MotionValue ) >> 2; ++ else ++ u32MotionValue_prev = u32MotionValue; ++ ++ //printf("===u32MotionValue_prev==%x=\n",u32MotionValue_prev); ++ //printf("===u16_unmatch_3==%x=\n",u16_unmatch_3); ++ ++ if( u32MotionValue_prev < A5_HIS_MOTION_TH ) ++ { ++ if( reg_his_weight > OP1_HisWeight_MinValue ) ++ reg_his_weight--; ++ else ++ reg_his_weight = OP1_HisWeight_MinValue; ++ } ++ else ++ { ++ if( reg_his_weight < OP1_HisWeight_MaxValue ) ++ reg_his_weight++; ++ else ++ reg_his_weight = OP1_HisWeight_MaxValue; ++ } ++ ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)reg_his_weight, 0x000E); ++ ++} ++ ++#define FeatherValueGain_MaxValue 0x02 ++#define FeatherValueGain_MinValue 0x00 ++void MDrv_SC_T12_UCDi_FeatherValueGain(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 FeatherValue = FeatherValueGain_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ // printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(FeatherValue > FeatherValueGain_MinValue) ++ FeatherValue--; ++ else ++ FeatherValue = FeatherValueGain_MinValue; ++ } ++ else ++ { ++ if(FeatherValue < FeatherValueGain_MaxValue) ++ FeatherValue++; ++ else ++ FeatherValue = FeatherValueGain_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2D_L, (MS_U16)FeatherValue << 12, 0xF000); ++ ++} ++ ++#define W2SadGain_MaxValue 0x0C ++#define W2SadGain_MinValue 0x08 ++void MDrv_SC_T12_UCDi_W2SadGain(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 W2SadGain = FeatherValueGain_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(W2SadGain < W2SadGain_MaxValue) ++ W2SadGain++; ++ else ++ W2SadGain = W2SadGain_MaxValue; ++ } ++ else ++ { ++ if(W2SadGain > W2SadGain_MinValue) ++ W2SadGain--; ++ else ++ W2SadGain = W2SadGain_MinValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2D_L, (MS_U16)W2SadGain << 8, 0x0F00); ++ ++} ++ ++#define VerticalMovingUdRatio_MaxValue 0x0F ++#define VerticalMovingUdRatio_MinValue 0x07 ++void MDrv_SC_T12_UCDi_VerticalMovingUdRatio(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 VerticalMovingUdRatioValue = VerticalMovingUdRatio_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ // printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ UNUSED(ISR_NONMV0); ++ ++ //if( ISR_NONMV0 > 1000) ++ if( OOSRF > 0x300 ) ++ { ++ if(VerticalMovingUdRatioValue > VerticalMovingUdRatio_MinValue) ++ VerticalMovingUdRatioValue--; ++ else ++ VerticalMovingUdRatioValue = VerticalMovingUdRatio_MinValue; ++ } ++ else ++ { ++ if(VerticalMovingUdRatioValue < VerticalMovingUdRatio_MaxValue) ++ VerticalMovingUdRatioValue++; ++ else ++ VerticalMovingUdRatioValue = VerticalMovingUdRatio_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)VerticalMovingUdRatioValue, 0x000F); ++ ++} ++ ++#define KFC_8bitMotionGain_MaxValue 0x08 ++#define KFC_8bitMotionGain_MinValue 0x04 //0 have feather issue. ++void MDrv_SC_T12_KFC_8bitMotionGain(MS_U32 SmallMoving) ++{ ++ static MS_U16 KFC_8bitMotionGainValue = KFC_8bitMotionGain_MaxValue; ++ ++ //printf("====SmallMoving=%x===\n",SmallMoving); ++ //MApi_XC_W2BYTEMSK(REG_SC_BK20_1D_L, 0x0008, 0x003F); ++ ++ if(SmallMoving > 500) ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x1000, 0x1000); ++ if(KFC_8bitMotionGainValue > KFC_8bitMotionGain_MinValue) ++ KFC_8bitMotionGainValue--; ++ else ++ KFC_8bitMotionGainValue = KFC_8bitMotionGain_MinValue; ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x0000, 0x1000); ++ if(KFC_8bitMotionGainValue < KFC_8bitMotionGain_MaxValue) ++ KFC_8bitMotionGainValue++; ++ else ++ KFC_8bitMotionGainValue = KFC_8bitMotionGain_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_3B_L, (MS_U16)KFC_8bitMotionGainValue << 4, 0x00F0); ++ ++} ++ ++#define UCDi_EODiWGain_MaxValue 0x0F ++#define UCDi_EODiWGain_MinValue 0x00 ++void MDrv_SC_T12_UCDi_EODiWGain(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 EODiWGainValue = UCDi_EODiWGain_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ // printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ ++ if((ISR_NONMV0 > 1000) && (OOSRF > 50)) ++ { ++ if(EODiWGainValue > UCDi_EODiWGain_MinValue) ++ EODiWGainValue--; ++ else ++ EODiWGainValue = UCDi_EODiWGain_MinValue; ++ } ++ else ++ { ++ if(EODiWGainValue < UCDi_EODiWGain_MaxValue) ++ EODiWGainValue++; ++ else ++ EODiWGainValue = UCDi_EODiWGain_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)EODiWGainValue << 12, 0xF000); ++ ++} ++ ++#define UCDi_HistoryRatio_MaxValue 0x07 ++#define UCDi_HistoryRatio_MinValue 0x04 ++void MDrv_SC_T12_UCDi_HistoryRatio(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 HistoryRatioValue = UCDi_HistoryRatio_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ ++ // MApi_XC_W2BYTEMSK(REG_SC_BK20_1D_L, 0x0008, 0x00FF); ++ UNUSED(OOSRMC); ++ ++ if((ISR_NONMV0 > 1000) && (OOSRF > 50)) ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x1000, 0x1000); ++ if(HistoryRatioValue > UCDi_HistoryRatio_MinValue) ++ HistoryRatioValue--; ++ else ++ HistoryRatioValue = UCDi_HistoryRatio_MinValue; ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x0000, 0x1000); ++ if(HistoryRatioValue < UCDi_HistoryRatio_MaxValue) ++ HistoryRatioValue++; ++ else ++ HistoryRatioValue = UCDi_HistoryRatio_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)HistoryRatioValue << 12, 0xF000); ++ ++} ++ ++#define KFC_EODIW_GAIN_MAX 4 ++#define KFC_EODIW_GAIN_MIN 0 ++void MDrv_SC_A5_KFC_EODiW(const MS_U32 IsVerticalMoving) ++{ ++ MS_U32 Statistics_cplx_pixel; ++ //MS_U32 meVerticalMoving; ++ static MS_U32 Statistics_cplx_pixel_iir = KFC_EODIW_GAIN_MIN; ++ static MS_U32 reg_kfc_eodiw_gain = KFC_EODIW_GAIN_MAX ; ++ ++ Statistics_cplx_pixel = ((Statistics_cplx_pixel_iir*3 )+ MApi_XC_R2BYTE(REG_SC_BK2A_7F_L) ) >> 2; ++ Statistics_cplx_pixel_iir = Statistics_cplx_pixel; ++ ++ if( (IsVerticalMoving < 0x150) && (Statistics_cplx_pixel_iir > 0x1000) ) ++ { ++ if( reg_kfc_eodiw_gain > KFC_EODIW_GAIN_MIN ) ++ reg_kfc_eodiw_gain--; ++ else ++ reg_kfc_eodiw_gain = KFC_EODIW_GAIN_MIN; ++ //reg_kfc_eodiw_gain = MAX(KFC_EODIW_GAIN_MIN, reg_kfc_eodiw_gain - 1); ++ } ++ else ++ { ++ if( reg_kfc_eodiw_gain < KFC_EODIW_GAIN_MAX ) ++ reg_kfc_eodiw_gain++; ++ else ++ reg_kfc_eodiw_gain = KFC_EODIW_GAIN_MAX; ++ //reg_kfc_eodiw_gain = MIN(KFC_EODIW_GAIN_MAX, reg_kfc_eodiw_gain + 1); ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)reg_kfc_eodiw_gain << 12, 0xF000); ++} ++ ++#define SONYC_KFC_EN_MAX 1 ++#define SONYC_KFC_EN_MIN 0 ++#define SONYC_CPLX_GAIN_MAX 4 ++#define SONYC_CPLX_GAIN_MIN 0 ++void MDrv_SC_A5_SonyChurch(const MS_U32 IsVerticalMoving, const MS_U32 IsHorizontalMoving, const MS_U32 u32MotionValue, const MS_BOOL lg107_en) ++{ ++ static MS_U32 reg_kfc_en = SONYC_KFC_EN_MAX ; ++ static MS_U32 reg_mcdi_cplx_gain = SONYC_CPLX_GAIN_MAX; ++ ++ //IsHorizontalMoving=IsHorizontalMoving; ++ ++ if( (IsVerticalMoving > 0xF0) && (IsHorizontalMoving < 1) && (u32MotionValue > 0x40000) ) ++ { ++ if( reg_mcdi_cplx_gain > SONYC_CPLX_GAIN_MIN ) ++ reg_mcdi_cplx_gain--; ++ else ++ reg_mcdi_cplx_gain = SONYC_CPLX_GAIN_MIN; ++ ++ if( reg_kfc_en > SONYC_KFC_EN_MIN ) ++ reg_kfc_en--; ++ else ++ reg_kfc_en = SONYC_KFC_EN_MIN; ++ } ++ else ++ { ++ if( reg_mcdi_cplx_gain < SONYC_CPLX_GAIN_MAX ) ++ reg_mcdi_cplx_gain++; ++ else ++ reg_mcdi_cplx_gain = SONYC_CPLX_GAIN_MAX; ++ ++ if( reg_kfc_en < SONYC_KFC_EN_MAX ) ++ reg_kfc_en++; ++ else ++ reg_kfc_en = SONYC_KFC_EN_MAX; ++ } ++ ++ if( !lg107_en ) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)reg_kfc_en<<1, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)reg_mcdi_cplx_gain<<8, 0x0F00); ++ } ++} ++ ++#define LG107_FEATHER_GAIN_MAX 2 ++#define LG107_FEATHER_GAIN_MIN 0 ++#define LG107_CPLX_OFFSET_MAX 6 ++#define LG107_CPLX_OFFSET_MIN 0 ++#define LG107_CPLX_GAIN_MAX 15 ++#define LG107_CPLX_GAIN_MIN 4 ++MS_BOOL MDrv_SC_A5_LG107(const MS_U32 IsVerticalMoving, const MS_U32 IsHorizontalMoving, const MS_U32 total_feather, const MS_U32 mvComfirm, const MS_U32 colorSum,const MS_U32 u32MotionValue, const MS_U32 uComplex ) ++{ ++ static MS_U32 reg_mcdi_feather_gain = LG107_FEATHER_GAIN_MAX ; ++ static MS_U32 reg_mcdi_cplx_offset = LG107_CPLX_OFFSET_MAX ; ++ static MS_U32 reg_mcdi_cplx_gain = LG107_CPLX_GAIN_MIN ; ++ MS_BOOL lg107_en; ++ //printf("====IsVerticalMoving=%x===\n",IsVerticalMoving); ++ //printf("====IsHorizontalMoving=%x===\n",IsHorizontalMoving); ++ //printf("====total_feather=%x===\n",total_feather); ++ //printf("====mvComfirm=%x===\n",mvComfirm); ++ //printf("====colorSum=%x===\n",colorSum); ++ // printf("====u32MotionValue=%x===\n",u32MotionValue); ++ ++ if( (IsVerticalMoving < 20) && (IsHorizontalMoving < 200) && (total_feather < 100) && (mvComfirm > 200) && (colorSum > 200) && (u32MotionValue > 0x3500) && (uComplex < 0x700)) ++ { ++ lg107_en = TRUE; ++ ++ if( reg_mcdi_feather_gain > LG107_FEATHER_GAIN_MIN ) ++ reg_mcdi_feather_gain--; ++ else ++ reg_mcdi_feather_gain = LG107_FEATHER_GAIN_MIN; ++ ++ if( reg_mcdi_cplx_offset > LG107_CPLX_OFFSET_MIN ) ++ reg_mcdi_cplx_offset--; ++ else ++ reg_mcdi_cplx_offset = LG107_CPLX_OFFSET_MIN; ++ ++ if( reg_mcdi_cplx_gain < LG107_CPLX_GAIN_MAX ) ++ reg_mcdi_cplx_gain++; ++ else ++ reg_mcdi_cplx_gain = LG107_CPLX_GAIN_MAX; ++ } ++ else ++ { ++ lg107_en = FALSE; ++ ++ if( reg_mcdi_feather_gain < LG107_FEATHER_GAIN_MAX ) ++ reg_mcdi_feather_gain++; ++ else ++ reg_mcdi_feather_gain = LG107_FEATHER_GAIN_MAX; ++ ++ if( reg_mcdi_cplx_offset < LG107_CPLX_OFFSET_MAX ) ++ reg_mcdi_cplx_offset++; ++ else ++ reg_mcdi_cplx_offset = LG107_CPLX_OFFSET_MAX; ++ ++ if( reg_mcdi_cplx_gain > LG107_CPLX_GAIN_MIN ) ++ reg_mcdi_cplx_gain--; ++ else ++ reg_mcdi_cplx_gain = LG107_CPLX_GAIN_MIN; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2D_L, (MS_U16)reg_mcdi_feather_gain<<12, 0xF000); // 2 to 0 ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)reg_mcdi_cplx_offset<<4, 0x00F0);// 6 to 0 ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)reg_mcdi_cplx_gain<<8, 0x0F00);// 4 to F ++ ++return lg107_en; ++} ++ ++MS_U32 MDrv_SC_A5_ComplexSum(void) ++{ ++ static MS_U32 IsComplex_iir = 0xFFFF; ++ MS_U32 IsComplex; ++ ++ IsComplex = MApi_XC_R2BYTE(REG_SC_BK2A_7F_L); ++ ++ IsComplex = (IsComplex_iir*3 + IsComplex ) >> 2; ++ IsComplex_iir = IsComplex; ++ ++ return IsComplex_iir; ++} ++ ++MS_U32 MDrv_SC_A5_KFC_IsVerticalMoving(void) ++{ ++ MS_U32 u32_mvc, u32_mvu, u32_mvd; ++ MS_U32 me_vertical; ++ static MS_U32 IsVerticalMoving_iir = 0; ++ ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ if ((u32_mvu > u32_mvc) && (u32_mvu > u32_mvd) /*&& (u32_mvu > 0x200*/) ++ { ++ if( u32_mvu > (u32_mvc+u32_mvd)/2 ) ++ me_vertical = (u32_mvu - (u32_mvc+u32_mvd)/2); ++ else ++ me_vertical = 0; ++ //me_vertical = MAX(0, u32_mvu - (u32_mvc+u32_mvd)/2); ++ } ++ else if((u32_mvd > u32_mvc) && (u32_mvd > u32_mvu) /*&& (u32_mvd > 0x200)*/) ++ { ++ if( u32_mvd > (u32_mvc+u32_mvu)/2 ) ++ me_vertical = (u32_mvd - (u32_mvc+u32_mvu)/2); ++ else ++ me_vertical = 0; ++ //me_vertical = MAX(0, u32_mvd - (u32_mvc+u32_mvu)/2); ++ } ++ else ++ { ++ me_vertical = 0; ++ } ++ ++ if( me_vertical > 255 ) ++ me_vertical = 255; ++ ++ me_vertical = (IsVerticalMoving_iir*3 + me_vertical ) >> 2; ++ IsVerticalMoving_iir = me_vertical; ++ ++ return me_vertical; ++} ++ ++MS_U32 MDrv_SC_A5_IsHorizontalMoving(void) ++{ ++ MS_U32 u32_mvc, u32_mvu, u32_mvd; ++ MS_U32 me_horizontal; ++ static MS_U32 IsHorizontalMoving_iir = 0; ++ ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ if ((u32_mvc > u32_mvu) && (u32_mvc > u32_mvd) /*&& (u32_mvu > 0x200*/) ++ { ++ if( u32_mvc > (u32_mvu+u32_mvd)/2 ) ++ me_horizontal = (u32_mvc - (u32_mvu+u32_mvd)/2); ++ else ++ me_horizontal = 0; ++ } ++ else ++ { ++ me_horizontal = 0; ++ } ++ ++ if( me_horizontal > 255 ) ++ me_horizontal = 255; ++ ++ me_horizontal = (IsHorizontalMoving_iir*3 + me_horizontal ) >> 2; ++ IsHorizontalMoving_iir = me_horizontal; ++ ++ return me_horizontal; ++} ++ ++ ++MS_U32 MDrv_SC_A5_ColorPixelSum(void) ++{ ++ MS_U32 colorSum; ++ static MS_U32 colorSum_iir = 0; ++ ++ colorSum = MApi_XC_R2BYTE(REG_SC_BK1A_6E_L); ++ colorSum = colorSum / 8; ++ ++ if( colorSum > 255 ) ++ colorSum = 255; ++ ++ colorSum = ((colorSum_iir*3 )+ colorSum ) >> 2; ++ colorSum_iir = colorSum; ++ ++ return colorSum_iir; ++} ++ ++ ++MS_U32 MDrv_SC_A5_TotalFeather(void) ++{ ++ MS_U32 mv0_feather, nonMv0_feather; ++ MS_U32 total_feather; ++ static MS_U32 total_feather_iir = 255; ++ ++ mv0_feather = MApi_XC_R2BYTE(REG_SC_BK2A_77_L); ++ nonMv0_feather = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); ++ ++ total_feather = ( mv0_feather + nonMv0_feather ) / 4; ++ ++ if( total_feather > 255 ) ++ total_feather = 255; ++ ++ total_feather = ((total_feather_iir*3 )+ total_feather ) >> 2; ++ total_feather_iir = total_feather; ++ ++ return total_feather_iir; ++} ++ ++#define TOTAL_MV_TIME 10 ++MS_U32 MDrv_SC_A5_TotalMvComfirm(void) ++{ ++ MS_U32 mv0, nonMv0, notFound; ++ MS_U32 total_mv, mvComfirm; ++ static MS_U32 mvComfirm_iir = 0; ++ ++ mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ nonMv0 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ notFound = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ total_mv = mv0 + nonMv0; ++ ++ if( total_mv > notFound*TOTAL_MV_TIME ) ++ mvComfirm = total_mv - notFound*TOTAL_MV_TIME; ++ else ++ mvComfirm = 0; ++ ++ if( mvComfirm > 255 ) ++ mvComfirm = 255; ++ ++ mvComfirm = ((mvComfirm_iir*3 )+ mvComfirm ) >> 2; ++ mvComfirm_iir = mvComfirm; ++ ++ return mvComfirm_iir; ++} ++ ++/******************************************************************************/ ++///Extend MCNR Driver ++/******************************************************************************/ ++void MDrv_SC_Extend_UCNR_driver(void) ++{ ++ MS_U32 u32_is_mv0, u32_non_mv0, u32_mvNotFound, u32_mvc, u32_mvu, u32_mvd; ++ MS_BOOL me_not_confirm , me_vertical, still_pattern; ++ static MS_U8 u8notConfirmCnt; ++ static MS_U32 last_u32_mvNotFound; ++ ++ u32_is_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ u32_non_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ u32_mvNotFound = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ ///////////////////////////////////////////////////////////////// ++ // NR Patch 1 ++ ///////////////////////////////////////////////////////////////// ++ ++ me_not_confirm = (u32_is_mv0 < 0x0200) && (u32_non_mv0 < 0x0200) ; ++ me_vertical = ((u32_mvu > u32_mvc) && (u32_mvu > u32_mvd) && (u32_mvu > 0x200)) || ++ ((u32_mvd > u32_mvc) && (u32_mvd > u32_mvu) && (u32_mvd > 0x200)); ++ ++ still_pattern = (u32_is_mv0 < 0x0020) && (u32_non_mv0 < 0x0020) && (u32_mvNotFound < 0x0020); ++ ++ if(!still_pattern) ++ { ++ if(false == me_not_confirm) ++ { ++ if(u8notConfirmCnt > 0) ++ { ++ u8notConfirmCnt--; ++ } ++ } ++ else ++ { ++ if(u8notConfirmCnt <= 0x40) ++ { ++ u8notConfirmCnt++; ++ } ++ } ++ } ++ ++ if(1) ++ { ++ if ( (u8notConfirmCnt > 0x30)|| me_vertical ) // low nr strength ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else if(u8notConfirmCnt < 0x10) ++ { ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ } ++ ++ if ( (u32_is_mv0 > 0x200) && ((u32_is_mv0/2) > u32_non_mv0) && ((u32_is_mv0/2) > u32_mvNotFound) ) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // still picture, reduce random motion ++ } ++ else if(u32_non_mv0 > u32_is_mv0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // default random motion ++ } ++ } ++ ++ last_u32_mvNotFound = u32_mvNotFound; ++} ++ ++/******************************************************************************/ ++///MCNR Driver ++/******************************************************************************/ ++ ++void MDrv_SC_mcnr_driver(void) ++{ ++ MS_U32 u32_is_mv0, u32_non_mv0, u32_mvNotFound, u32_mvc, u32_mvu, u32_mvd; ++ MS_BOOL me_not_confirm , me_vertical; ++ static MS_U8 u8notConfirmCnt; ++ static MS_U32 last_u32_mvNotFound; ++ ++ u32_is_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ u32_non_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ u32_mvNotFound = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ ++ ///////////////////////////////////////////////////////////////// ++ // NR Patch 1 ++ ///////////////////////////////////////////////////////////////// ++ ++ me_not_confirm = (u32_is_mv0 < 0x0200) && (u32_non_mv0 < 0x0200); ++ me_vertical = ((u32_mvu > u32_mvc) && (u32_mvu > u32_mvd) && (u32_mvu > 0x200)) || ++ ((u32_mvd > u32_mvc) && (u32_mvd > u32_mvu) && (u32_mvd > 0x200)); ++ ++ if(false == me_not_confirm) ++ { ++ if(u8notConfirmCnt > 0) ++ { ++ u8notConfirmCnt--; ++ } ++ } ++ else ++ { ++ if(u8notConfirmCnt <= 0x40) ++ { ++ u8notConfirmCnt++; ++ } ++ } ++ ++ if(1) ++ { ++ if((u8notConfirmCnt > 0x30) || me_vertical) // low nr strength ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else if(u8notConfirmCnt < 0x10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ } ++ ++ if((u32_is_mv0 > 0x200) && (u32_is_mv0 / 2 > u32_non_mv0) && (u32_is_mv0 / 2 > u32_mvNotFound)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // still picture, reduce random motion ++ } ++ else if(u32_non_mv0 > u32_is_mv0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // default random motion ++ } ++ } ++ ++ last_u32_mvNotFound = u32_mvNotFound; ++} ++ ++/******************************************************************************/ ++///DeFeathering ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_de_feathering(MS_U32 u32MotionValue) ++{ ++ static MS_U32 u32DeFeatherCntLv1 = 0; ++ static MS_U32 u32DeFeatherCntLv2 = 0; ++ static MS_U32 u32DeFeatherCntLv3 = 0; ++ MS_U8 u8SST_Static_Core_TH; ++ MS_U32 reg_defethering_lv1_cnt; ++ MS_U32 reg_defethering_lv2_cnt; ++ MS_U32 reg_mdp_cnt; ++ ++ reg_defethering_lv1_cnt = 0x0A; ++ reg_defethering_lv2_cnt = 0x08; ++ reg_mdp_cnt = 0x01; ++ ++ // motion level count ++ if(u32MotionValue >= DEFETHERING_LV1_TH) ++ { ++ if(u32DeFeatherCntLv1 < reg_defethering_lv1_cnt) ++ u32DeFeatherCntLv1++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv1 >= reg_mdp_cnt) ++ u32DeFeatherCntLv1 = u32DeFeatherCntLv1 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv1 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV2_TH) ++ { ++ if(u32DeFeatherCntLv2 < reg_defethering_lv2_cnt) ++ u32DeFeatherCntLv2++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv2 >= reg_mdp_cnt) ++ u32DeFeatherCntLv2 = u32DeFeatherCntLv2 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv2 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV3_TH) ++ { ++ if(u32DeFeatherCntLv3 < DEFETHERING_LV3_CNT) ++ u32DeFeatherCntLv3++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv3 >= reg_mdp_cnt) ++ u32DeFeatherCntLv3 = u32DeFeatherCntLv3 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv3 = 0; ++ } ++ ++ //DeFeathering begin ++ if(u32DeFeatherCntLv1 >= reg_defethering_lv1_cnt) ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV1_VALUE; ++ } ++ else if(u32DeFeatherCntLv2 >= reg_defethering_lv2_cnt) ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV2_VALUE; ++ } ++ else if(u32DeFeatherCntLv3 >= DEFETHERING_LV3_CNT) ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV3_VALUE; ++ } ++ else ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV4_VALUE; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_1A_L, (MS_U16)u8SST_Static_Core_TH, 0xFF); ++} ++ ++ ++int MDrv_SC_motion_level(MS_U32 u32MotionValue) ++{ ++ static MS_U32 u32DeFeatherCntLv1 = 0; ++ static MS_U32 u32DeFeatherCntLv2 = 0; ++ static MS_U32 u32DeFeatherCntLv3 = 0; ++ MS_U8 u8MotLvl; ++ MS_U32 reg_defethering_lv1_cnt; ++ MS_U32 reg_defethering_lv2_cnt; ++ MS_U32 reg_mdp_cnt; ++ ++ reg_defethering_lv1_cnt = 0x0A; ++ reg_defethering_lv2_cnt = 0x08; ++ reg_mdp_cnt = 0x01; ++ ++ // motion level count ++ if(u32MotionValue >= DEFETHERING_LV1_TH) ++ { ++ if(u32DeFeatherCntLv1 < reg_defethering_lv1_cnt) ++ u32DeFeatherCntLv1++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv1 >= reg_mdp_cnt) ++ u32DeFeatherCntLv1 = u32DeFeatherCntLv1 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv1 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV2_TH) ++ { ++ if(u32DeFeatherCntLv2 < reg_defethering_lv2_cnt) ++ u32DeFeatherCntLv2++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv2 >= reg_mdp_cnt) ++ u32DeFeatherCntLv2 = u32DeFeatherCntLv2 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv2 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV3_TH) ++ { ++ if(u32DeFeatherCntLv3 < DEFETHERING_LV3_CNT) ++ u32DeFeatherCntLv3++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv3 >= reg_mdp_cnt) ++ u32DeFeatherCntLv3 = u32DeFeatherCntLv3 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv3 = 0; ++ } ++ ++ //level begin ++ if(u32DeFeatherCntLv1 >= reg_defethering_lv1_cnt) ++ { ++ u8MotLvl = 3; ++ } ++ else if(u32DeFeatherCntLv2 >= reg_defethering_lv2_cnt) ++ { ++ u8MotLvl = 2; ++ } ++ else if(u32DeFeatherCntLv3 >= DEFETHERING_LV3_CNT) ++ { ++ u8MotLvl = 1; ++ } ++ else ++ { ++ u8MotLvl = 0; ++ } ++ ++ return u8MotLvl; ++ ++} ++ ++ ++/******************************************************************************/ ++///DeFlickering ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_de_flickering(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DeFlickerCnt = 0; ++ MS_U32 reg_m_feat_smooth_hle_th, reg_m_feat_smooth_shrink; ++ ++ reg_m_feat_smooth_hle_th = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_1E_L, 0xF000); // Feat Smooth HLE TH ++ reg_m_feat_smooth_shrink = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_1E_L, 0x8F); ++ ++ if(u32MotionValue >= DEFLICKERING_TH) ++ { ++ if(s32DeFlickerCnt < 65535) ++ s32DeFlickerCnt++; ++ } ++ else ++ { ++ s32DeFlickerCnt = 0; ++ } ++ ++ if(s32DeFlickerCnt >= DEFLICKERING_CNT) ++ { ++ reg_m_feat_smooth_hle_th += 0x0300; ++ reg_m_feat_smooth_shrink += 0x10; ++ } ++ else ++ { ++ reg_m_feat_smooth_hle_th += 0x0700; ++ reg_m_feat_smooth_shrink += 0x30; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_1E_L, (MS_U16)reg_m_feat_smooth_shrink, 0xFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_1E_L, (MS_U16)reg_m_feat_smooth_hle_th, 0xFF00); ++ ++} ++ ++/******************************************************************************/ ++///DeBouncing ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++#define DEBOUNCING_GAIN 1 //0 ++void MDrv_SC_de_bouncing(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DeBouncingCnt = 0; ++ MS_U32 reg_his_wt_f2; ++ MS_U32 reg_debouncing_th; ++ int reg_debouncing_cnt; ++ ++ reg_debouncing_th = 0x0A; ++ reg_debouncing_cnt = 0x03; ++ ++ reg_his_wt_f2 = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0A_L, 0xF8); // history ratio weighting ++ ++ if(u32MotionValue <= reg_debouncing_th * DEBOUNCING_GAIN) ++ { ++ s32DeBouncingCnt = 0; ++ } ++ else ++ { ++ if(s32DeBouncingCnt < 65535) ++ s32DeBouncingCnt++; ++ } ++ ++ if(s32DeBouncingCnt >= reg_debouncing_cnt) ++ { ++ reg_his_wt_f2 += 0x06; // history = 6 moving ++ } ++ else ++ { ++ reg_his_wt_f2 += 0x03; // history = 3 still ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_0A_L, (MS_U16)reg_his_wt_f2, 0xFF); ++} ++ ++/******************************************************************************/ ++///DePreSNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_de_pre_snr(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DePreSNRCnt = 0; ++ MS_U8 reg_preSnr_en = 0; ++ MS_U32 reg_preSnr_th; ++ int reg_preSnr_cnt; ++ ++ reg_preSnr_th = 0x06; ++ reg_preSnr_cnt = 0x01; ++ ++ if(u32MotionValue <= reg_preSnr_th * DEBOUNCING_GAIN) ++ { ++ s32DePreSNRCnt = 0; ++ } ++ else ++ { ++ if(s32DePreSNRCnt < 65535) ++ s32DePreSNRCnt++; ++ } ++ ++ if(s32DePreSNRCnt >= reg_preSnr_cnt) ++ { ++ reg_preSnr_en = 0x01; // enable pre-snr ++ } ++ else ++ { ++ reg_preSnr_en = 0x00; // disable pre-snr ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK06_22_L, (MS_U16)reg_preSnr_en, BIT(0)); ++} ++ ++/******************************************************************************/ ++///Dynamic SNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_dynamic_snr(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DynamicSnrCnt = 0; ++#if (DBG_DYNAMIC_SNR) ++ static MS_S32 s32CurrentLevel = -1; ++ static MS_S32 s32LastLevel = -1; ++#endif ++ MS_U8 u8SNR_Bypass; ++ MS_U32 reg_snr_cnt; ++ ++ reg_snr_cnt = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK0B_77_L, 0xFF); ++ ++ if(u32MotionValue <= DYNAMIC_SNR_TH) ++ { ++ s32DynamicSnrCnt = 0; ++ } ++ else ++ { ++ if(s32DynamicSnrCnt < 65535) ++ s32DynamicSnrCnt++; ++ } ++ ++ if(s32DynamicSnrCnt >= (MS_S32)reg_snr_cnt) ++ { ++ u8SNR_Bypass = 0; // SNR enable ++ ++#if (DBG_DYNAMIC_SNR) ++ s32CurrentLevel = 1; ++#endif ++ } ++ else ++ { ++ u8SNR_Bypass = 1; // SNR disable ++ ++#if (DBG_DYNAMIC_SNR) ++ s32CurrentLevel = 2; ++#endif ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_70_L, (MS_U16)u8SNR_Bypass, 0xFF); ++ ++#if (DBG_DYNAMIC_SNR) ++ if(s32CurrentLevel != s32LastLevel) ++ { ++ if(s32CurrentLevel == 1) ++ printf("SNR = Enable[%x]\n", s32CurrentLevel); ++ else ++ printf("SNR = Disable[%x]\n", s32CurrentLevel); ++ ++ s32LastLevel = s32CurrentLevel; ++ } ++#endif ++} ++ ++/******************************************************************************/ ++///FantasticDNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_fantastic_dnr(void) ++{ ++ static MS_S32 s32Cnt = 0; ++ MS_U8 u8DNR_TblY_0L, u8DNR_TblY_0H, u8DNR_TblY_1L, u8DNR_TblY_1H; ++ MS_U8 u8DNR_TblY_2L, u8DNR_TblY_2H, u8DNR_TblY_3L, u8DNR_TblY_3H; ++ ++ s32Cnt++; ++ ++ if(s32Cnt % 2 == 0) ++ { ++ u8DNR_TblY_0L = 0xDE; ++ u8DNR_TblY_0H = 0xDD; ++ u8DNR_TblY_1L = 0x79; ++ u8DNR_TblY_1H = 0x67; ++ u8DNR_TblY_2L = 0x56; ++ u8DNR_TblY_2H = 0x45; ++ u8DNR_TblY_3L = 0x11; ++ u8DNR_TblY_3H = 0x00; ++ } ++ else ++ { ++ u8DNR_TblY_0L = 0xCD; ++ u8DNR_TblY_0H = 0x39; ++ u8DNR_TblY_1L = 0x34; ++ u8DNR_TblY_1H = 0x11; ++ u8DNR_TblY_2L = 0x00; ++ u8DNR_TblY_2H = 0x00; ++ u8DNR_TblY_3L = 0x00; ++ u8DNR_TblY_3H = 0x00; ++ } ++ MApi_XC_W2BYTE(REG_SC_BK06_40_L, ((MS_U16)u8DNR_TblY_0L | (((MS_U16) u8DNR_TblY_0H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_41_L, ((MS_U16)u8DNR_TblY_1L | (((MS_U16) u8DNR_TblY_1H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_42_L, ((MS_U16)u8DNR_TblY_2L | (((MS_U16) u8DNR_TblY_2H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_43_L, ((MS_U16)u8DNR_TblY_3L | (((MS_U16) u8DNR_TblY_3H) << 8))); ++ ++} ++ ++/******************************************************************************/ ++///Dynamic DNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++#define DYNAMIC_DNR_TH 1000 ++void MDrv_SC_dynamic_dnr(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32ZeroCnt = 0; ++ static MS_S32 s32StillCnt = 0; ++ MS_U8 u8DNR_TblY_0L, u8DNR_TblY_0H, u8DNR_TblY_1L, u8DNR_TblY_1H; ++ MS_U8 u8DNR_TblY_2L, u8DNR_TblY_2H, u8DNR_TblY_3L, u8DNR_TblY_3H; ++ ++ if(u32MotionValue <= DYNAMIC_DNR_TH) ++ { ++ if(s32StillCnt < 65535) ++ s32StillCnt++; ++ } ++ else ++ { ++ s32StillCnt = 0; ++ } ++ ++ if(u32MotionValue == 0) ++ { ++ if(s32ZeroCnt < 65535) ++ s32ZeroCnt++; ++ } ++ else ++ { ++ s32ZeroCnt = 0; ++ } ++ ++ if(s32ZeroCnt >= 18) ++ { ++ u8DNR_TblY_0L = 0xDE; ++ u8DNR_TblY_0H = 0xDD; ++ u8DNR_TblY_1L = 0x79; ++ u8DNR_TblY_1H = 0x67; ++ u8DNR_TblY_2L = 0x56; ++ u8DNR_TblY_2H = 0x45; ++ u8DNR_TblY_3L = 0x11; ++ u8DNR_TblY_3H = 0x00; ++ } ++ else if(s32StillCnt >= 8) //still ++ { ++ u8DNR_TblY_0L = 0xCE; ++ u8DNR_TblY_0H = 0xAC; ++ u8DNR_TblY_1L = 0x78; ++ u8DNR_TblY_1H = 0x34; ++ u8DNR_TblY_2L = 0x12; ++ u8DNR_TblY_2H = 0x00; ++ u8DNR_TblY_3L = 0x00; ++ u8DNR_TblY_3H = 0x00; ++ ++ } ++ else //moving ++ { ++ u8DNR_TblY_0L = 0xCD; ++ u8DNR_TblY_0H = 0x39; ++ u8DNR_TblY_1L = 0x34; ++ u8DNR_TblY_1H = 0x11; ++ u8DNR_TblY_2L = 0x00; ++ u8DNR_TblY_2H = 0x00; ++ u8DNR_TblY_3L = 0x00; ++ u8DNR_TblY_3H = 0x00; ++ } ++ MApi_XC_W2BYTE(REG_SC_BK06_40_L, ((MS_U16)u8DNR_TblY_0L | (((MS_U16) u8DNR_TblY_0H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_41_L, ((MS_U16)u8DNR_TblY_1L | (((MS_U16) u8DNR_TblY_1H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_42_L, ((MS_U16)u8DNR_TblY_2L | (((MS_U16) u8DNR_TblY_2H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_43_L, ((MS_U16)u8DNR_TblY_3L | (((MS_U16) u8DNR_TblY_3H) << 8))); ++ ++} ++ ++void MDrv_SC_dynamic_film_mode(void) ++{ ++ MS_U8 u8Value; ++ MS_U16 u16_unmatch_3; ++ static MS_U8 u8PrevLuma, u8_unmatch_3_Cnt; ++ static MS_U16 _u16BackupReg0x10 = 0; ++ static MS_U16 _u16BackupReg0x24 = 0; ++ static MS_BOOL _bEnableFilmMode = FALSE; ++ XC_ApiStatus stXCStatus; ++ ++ MS_U32 u32MotionValue; ++ ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ if(stXCStatus.bDoneFPLL && _bEnableFilmMode) ++ { ++ _bEnableFilmMode = FALSE; ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, _u16BackupReg0x10, BIT(14)|BIT(15)); //f2 22/32 film mode enable ++ if(g_bAnyCandenceEnable) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, _u16BackupReg0x24, BIT(15)); //film any cadance enable f2 ++ } ++ } ++ ++ if(stXCStatus.bInterlace) ++ { ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(3)))//only active at Film22 ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x02)<<8, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x02) << 8, 0xFF00); ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(4))) // only active at Film32 ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x06) << 8, 0x1F00); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F) << 8, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x10) << 8, 0xFF00); ++ } ++ ++///--> new for T3 ++ //T3 add new feature for film mode to enhance the film lock or not ++ MApi_XC_FilmMode_P(); ++///--> end ++ } ++ ++ #if 0 ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3 + MApi_XC_DLC_GetAverageValue()) >> 2); ++ #else ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3) >> 2); ++ #endif ++ ++ u8PrevLuma = u8Value; ++ u32MotionValue = MDrv_SC_read_motion_value1(); ++ if(u32MotionValue < 1200) ++ { ++ if(u8Value < 0x48) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x00); ++ } ++ else if((u8Value<0x88)&(u8Value >= 0x48)) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x0011); ++ } ++ else ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x1111); ++ } ++ } ++ else ++ { ++ if(u8Value < 0x48) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x2222); ++ } ++ else if((u8Value<0x88)&(u8Value >= 0x48)) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x5555); ++ } ++ else ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0xAAAA); ++ } ++ } ++#if 0 ++ // for Fulke 4 vertical line pattern ++ ++ if(ucValue < 0x18) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, 0x1000, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_0C_L, 0x0400, 0xFFFF); ++ } ++#endif ++ ++ if( (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(14) ) == BIT(14) ) // Film22 On,f2 22 film mode enable ++ || (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(15) ) == BIT(15) ) ) // Film32 On,f2 32 film mode enable ++ { ++ if (!stXCStatus.bDoneFPLL) // Make not frame LOCKED then turn off FilmMode ++ { ++ _bEnableFilmMode = TRUE; ++ _u16BackupReg0x10 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_10_L, BIT(14)|BIT(15)); ++ _u16BackupReg0x24 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_24_L, BIT(15)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, 0x0, BIT(14)|BIT(15)); //f2 22/32 film mode disable ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, 0x0, BIT(15)); //film any cadance disable f2 ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, BIT(1), BIT(1)); //hardware film mode DISABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, BIT(1)|BIT(2), BIT(1) | BIT(2)); //software film mode DISABLE ++ } ++ else // Make sure frame LOCKED then turn on FilmMode ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); //hardware film mode ENABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); //software film mode ENABLE ++ ++ ///--> new add function for skip film mode in still pattern ++ if((!MApi_XC_R2BYTEMSK(REG_SC_BK12_03_L, BIT(1)))&&(!MApi_XC_R2BYTEMSK(REG_SC_BK0A_02_L, BIT(14)))) // 2R mode can't enter this loop ++ { ++ u16_unmatch_3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ if( (u16_unmatch_3 > 0x100) ) ++ u8_unmatch_3_Cnt = 0; ++ else if(u8_unmatch_3_Cnt == 0xFF) ++ u8_unmatch_3_Cnt = 0xFF; ++ else ++ u8_unmatch_3_Cnt = u8_unmatch_3_Cnt + 1; ++ ++ if(u8_unmatch_3_Cnt > 0x05) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0002, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0006, 0x0006); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0000, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0000, 0x0006); ++ } ++ } ++ } ++ } ++ else ++ { ++ // DEFAULT value of hardware and software film mode suggested by SY.Shih ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); ++ } ++} ++ ++ ++void MDrv_SC_film_driver(MS_U16 u16Width) ++{ ++ XC_ApiStatus stXCStatus; ++ static MS_U8 u8FilmCnt,u8_unmatch_3_Cnt; ++ static MS_U16 _u16BackupReg0x10 = 0; ++ static MS_U16 _u16BackupReg0x24 = 0; ++ static MS_BOOL _bEnableFilmMode = FALSE; ++ ++ MS_U32 u32Reg7C, u32Reg7D, u32Reg7E, u16_unmatch_3; ++ MS_BOOL verticalMovingU, sd_source=true; ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ u32Reg7C = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32Reg7D = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32Reg7E = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ // for all chip ++ if(u16Width >= 1280) ++ { ++ sd_source = false; ++ } ++ // for MCNR only ++ verticalMovingU = (u32Reg7E > 0x0100) && (u32Reg7E > 8 * u32Reg7C) && (u32Reg7E > 8 * u32Reg7D); ++ ++ ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ if(stXCStatus.bDoneFPLL && _bEnableFilmMode) ++ { ++ _bEnableFilmMode = FALSE; ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, _u16BackupReg0x10, BIT(14)|BIT(15)); //f2 22/32 film mode enable ++ if(g_bAnyCandenceEnable) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, _u16BackupReg0x24, BIT(15)); //film any cadance enable f2 ++ } ++ } ++ ++ if(stXCStatus.bInterlace) ++ { ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(3)))//only active at Film22 ++ { ++ if(sd_source) // SD: smaller counter 1 th easier to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x01) << 8, 0x1F00); ++ } ++ else // HD: bigger counter 1 th harder to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F)<<8, 0x1F00); ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x02) << 8, 0xFF00); ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(4))) // only active at Film32 ++ { ++ if(sd_source) // SD: smaller counter 1 th easier to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x06) << 8, 0x1F00); ++ } ++ else // HD: bigger counter 1 th harder to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F)<<8, 0x1F00); ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x10) << 8, 0xFF00); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F) << 8, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x10) << 8, 0xFF00); ++ } ++ ++///--> new for T3 ++ //T3 add new feature for film mode to enhance the film lock or not ++ MApi_XC_FilmMode_P(); ++///--> end ++ ++ if( (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(14) ) == BIT(14) ) // Film22 On,f2 22 film mode enable ++ || (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(15) ) == BIT(15) ) ) // Film32 On,f2 32 film mode enable ++ { ++ if (!stXCStatus.bDoneFPLL) // Make not frame LOCKED then turn off FilmMode ++ { ++ _bEnableFilmMode = TRUE; ++ _u16BackupReg0x10 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_10_L, BIT(14)|BIT(15)); ++ _u16BackupReg0x24 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_24_L, BIT(15)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, 0x0, BIT(14)|BIT(15)); //f2 22/32 film mode disable ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, 0x0, BIT(15)); //film any cadance disable f2 ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, BIT(1), BIT(1)); //hardware film mode DISABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, BIT(1)|BIT(2), BIT(1) | BIT(2)); //software film mode DISABLE ++ } ++ else // Make sure frame LOCKED then turn on FilmMode ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); //hardware film mode ENABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); //software film mode ENABLE ++ ++ ///--> new add function for skip film mode in still pattern ++ if((!MApi_XC_R2BYTEMSK(REG_SC_BK12_03_L, BIT(1)))&&(!MApi_XC_R2BYTEMSK(REG_SC_BK0A_02_L, BIT(14)))) // 2R mode can't enter this loop ++ { ++ u16_unmatch_3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ if((u16_unmatch_3 > 0x100)) ++ u8_unmatch_3_Cnt = 0; ++ else if(u8_unmatch_3_Cnt == 0xFF) ++ u8_unmatch_3_Cnt = 0xFF; ++ else ++ u8_unmatch_3_Cnt = u8_unmatch_3_Cnt + 1; ++ ++ ///--> Jump out Film for LG tower ++ if( !verticalMovingU ) ++ u8FilmCnt = 0; ++ else if(u8FilmCnt == 0xFF) ++ u8FilmCnt = 0xFF; ++ else ++ u8FilmCnt = u8FilmCnt + 1; ++ ++ ++ if(u8FilmCnt>0x05) // vertical moving, fake out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0002, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0006, 0x0006); ++ } ++ else if(u8_unmatch_3_Cnt > 0x05) // still video, fake out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0002, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0006, 0x0006); ++ } ++ else // default setting, turn off fake out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0000, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0000, 0x0006); ++ } ++ } ++ } ++ } ++ else ++ { ++ // DEFAULT value of hardware and software film mode suggested by SY.Shih ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); ++ } ++ ++ ++///--> end ++ ++#if 0 ++ if(true == verticalMovingU) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_02_L, 0x2122); ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x2222); ++ } ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, 0x0000, 0x2000); ++#endif ++ // for debug usage ++ //MApi_XC_W2BYTE(REG_SC_BK22_7A_L, 0x1000); ++ //MApi_XC_W2BYTE(REG_SC_BK20_1D_L, 0x0000); ++ ++ } // end interlace loop ++} ++ ++void MDrv_SC_Janus_DHD_driver(void) ++{ ++ // dhd shining line patch ++ static MS_U32 u32videoCnt = 0; ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(3))) // film22 ++ u32videoCnt = 0; ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(4))) // film32 ++ u32videoCnt = 0; ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(6))) ++ u32videoCnt = 0; ++ else if(u32videoCnt >= 10000) ++ u32videoCnt = 10000; ++ else ++ u32videoCnt++; ++ ++ if(u32videoCnt >= 60) // 2 sec ++ { ++ // turn on dhd, 6R ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_05_L, 0x8000, 0x8000); // 6R ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, 0x0001, 0x0001); // dhd on ++ } ++ else ++ { ++ // turn off dhd, 4R ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_05_L, 0x0000, 0x8000); // 4R ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, 0x0000, 0x0001); // dhd off ++ } ++ ++} ++ ++#define HD_ACT_TH 10 ++#define HDSDD_SPEED 1 ++#define HDSDD_DIV 0 ++#define HD_SPEED 2 ++#define SD_SPEED 8 ++ ++void MDrv_SC_SDHD_DETECT_driver(void) ++{ ++ MS_U8 u8Value; ++ MS_U16 u16MinPixel, u16MaxPixel, MaxMinPixel; ++ MS_U32 HDcnt_Act; ++ //MS_U32 HDcnt_NonAct; ++ MS_U32 SDcnt_Act; ++ //MS_U32 SDcnt_NonAct; ++ static MS_U16 HD_ConfirmCnt = 0xFF; // 0x7FFF == 0 ++ static MS_U8 u8PrevLuma = 0; ++ static MS_U16 u16PrevMinPixel = 0; ++ static MS_U16 u16PrevMaxPixel = 0; ++ MS_U32 HD_ConfirmCnt_Reg; ++ MS_U16 HDSDD_Det_threshold, HDSDD_Det_offset; ++ ++ //HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ //SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ HDSDD_Det_offset = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ //printf("====HDcnt_Act===%x\n",HDcnt_Act); ++ //printf("====SDcnt_Act===%x\n",SDcnt_Act); ++ //printf("====HDcnt_NonAct===%x\n",HDcnt_NonAct); ++ //printf("====SDcnt_NonAct===%x\n",SDcnt_NonAct); ++ ++ #if 0 ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3 + MApi_XC_DLC_GetAverageValue()) >> 2); ++ #else ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3) >> 2); ++ #endif ++ u8PrevLuma = u8Value; ++ ++ u16MaxPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0x00FF); ++ u16MaxPixel = (u16PrevMaxPixel * 3 + u16MaxPixel) >> 2; ++ u16PrevMaxPixel = u16MaxPixel; ++ ++ u16MinPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0xFF00) >> 8; ++ u16MinPixel = (u16PrevMinPixel * 3 + u16MinPixel) >> 2; ++ u16PrevMinPixel = u16MinPixel; ++ ++ MaxMinPixel = u16MaxPixel - u16MinPixel; ++ //printf("===u8MinPixel=%x==\n",u16MinPixel); ++ //printf("===MaxMinPixel=%x==\n",MaxMinPixel); ++ ++ if(u8Value >= 0xFF) ++ u8Value = 0xFF; ++ //printf("===AvgLuma=%x==\n",u8Value); ++ ++ HDSDD_Det_threshold = HDSDD_Det_offset + ((MaxMinPixel * 6) >> 2) + ((u8Value * 5) >> 2); ++ //printf("===HDSDD_Det_threshold=%x==\n",HDSDD_Det_threshold); ++ ++#if 0 ++ { ++ if(u8Value > 0x80) ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++ else if(u8Value > 0x40) ++ Cur_HDSDD_Det_threshold = ((u16HDSDD_Det_Threshold * 3) >> 2); ++ else if(u8Value > 0x20) ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold >> 1); ++ else ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold >> 2); ++ } ++ else ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++#endif ++ ++ if(HDSDD_Det_threshold >= 0xFFFF) ++ { ++ HDSDD_Det_threshold = 0xFFFF; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_71_L, (MS_U16)HDSDD_Det_threshold, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_72_L, (MS_U16)(HDSDD_Det_threshold >> 1), 0xFFFF); ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ ++ if((HDcnt_Act > HD_ACT_TH) && (SDcnt_Act != 0)) ++ { ++ if(HD_ConfirmCnt < HD_SPEED) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - HD_SPEED; ++ } ++ else if(SDcnt_Act != 0) //&& HDcnt_NonAct !=0) // && (HDcnt_NonAct < 0x90000)) ++ { ++ if(HD_ConfirmCnt > (0xFF - SD_SPEED)) ++ HD_ConfirmCnt = 0xFF; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt + SD_SPEED; ++ } ++ else ++ { ++ if(HD_ConfirmCnt < 1) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - 1; ++ } ++ ++ if(HD_ConfirmCnt > 0x80) ++ HD_ConfirmCnt_Reg = HD_ConfirmCnt - 0x80; ++ else ++ HD_ConfirmCnt_Reg = 0; ++ ++ HD_ConfirmCnt_Reg = (HD_ConfirmCnt_Reg * HDSDD_SPEED) >> HDSDD_DIV; ++ ++ if(HD_ConfirmCnt_Reg > 0x3F) ++ HD_ConfirmCnt_Reg = 0x3F; ++ ++ //printf("====HD_ConfirmCnt_Reg===%x\n",HD_ConfirmCnt_Reg); ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK23_54_L, (MS_U16)HD_ConfirmCnt_Reg, 0x003F); ++ ++} ++ ++void MDrv_SC_NEW_SDHD_DETECT_driver(void) ++{ ++ MS_U8 u8Value,FEATHER_CNT_TH; ++ MS_U16 u16MinPixel,u16MaxPixel, MaxMinPixel; ++ MS_U32 HDcnt_Act; ++ //MS_U32 HDcnt_NonAct; ++ MS_U32 FeatherCnt; ++ MS_U32 SDcnt_Act; ++ //MS_U32 SDcnt_NonAct; ++ static MS_U32 PreFeatherCnt = 0; ++ static MS_U16 HD_ConfirmCnt = 0xFF; // 0x7FFF == 0 ++ static MS_U8 u8PrevLuma = 0; ++ static MS_U16 u16PrevMinPixel = 0; ++ static MS_U16 u16PrevMaxPixel = 0; ++ MS_U32 HD_ConfirmCnt_Reg; ++ MS_U16 HDSDD_Det_threshold,HDSDD_Det_offset; ++ ++ //HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ //SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ HDSDD_Det_offset = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ FeatherCnt = MApi_XC_R2BYTE(REG_SC_BK23_56_L); //New add for A1 chip ++ FEATHER_CNT_TH = MApi_XC_R2BYTEMSK(REG_SC_BK22_7D_L, 0xFF00)>>8; ++ ++ //printf("====HDcnt_Act===%x\n",HDcnt_Act); ++ //printf("====SDcnt_Act===%x\n",SDcnt_Act); ++ //printf("====HDcnt_NonAct===%x\n",HDcnt_NonAct); ++ //printf("====SDcnt_NonAct===%x\n",SDcnt_NonAct); ++ ++ FeatherCnt = ( PreFeatherCnt*3 + FeatherCnt ) >> 2; ++ PreFeatherCnt = FeatherCnt; ++ ++ #if 0 ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3 + MApi_XC_DLC_GetAverageValue())>>2); ++ #else ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3)>>2); ++ #endif ++ ++ u8PrevLuma = u8Value; ++ ++ u16MaxPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0x00FF); ++ u16MaxPixel = (u16PrevMaxPixel*3 + u16MaxPixel ) >> 2; ++ u16PrevMaxPixel = u16MaxPixel; ++ ++ u16MinPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0xFF00)>>8; ++ u16MinPixel = (u16PrevMinPixel*3 + u16MinPixel ) >> 2; ++ u16PrevMinPixel = u16MinPixel; ++ ++ MaxMinPixel = u16MaxPixel - u16MinPixel; ++ //printf("===u8MinPixel=%x==\n",u16MinPixel); ++ //printf("===MaxMinPixel=%x==\n",MaxMinPixel); ++ ++ ++ if(u8Value>=0xFF) ++ u8Value = 0xFF; ++ //printf("===AvgLuma=%x==\n",u8Value); ++ ++ HDSDD_Det_threshold = HDSDD_Det_offset +((MaxMinPixel*6)>>2) + ((u8Value*5)>>2); ++ //printf("===HDSDD_Det_threshold=%x==\n",HDSDD_Det_threshold); ++ ++ #if 0 ++ { ++ if( u8Value > 0x80) ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++ else if( u8Value > 0x40) ++ Cur_HDSDD_Det_threshold = ((u16HDSDD_Det_Threshold*3)>>2); ++ else if( u8Value > 0x20) ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold>>1); ++ else ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold>>2); ++ } ++ else ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++ #endif ++ ++ if(HDSDD_Det_threshold >=0xFFFF) ++ { ++ HDSDD_Det_threshold=0xFFFF; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_71_L, (MS_U16)HDSDD_Det_threshold, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_72_L, (MS_U16)(HDSDD_Det_threshold>>1), 0xFFFF); ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ ++ ++ if( (HDcnt_Act > HD_ACT_TH) && (SDcnt_Act != 0) ) ++ { ++ if(HD_ConfirmCnt < HD_SPEED) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - HD_SPEED; ++ } ++ else if( (SDcnt_Act != 0) && (FeatherCnt > FEATHER_CNT_TH) )//&& HDcnt_NonAct !=0) // && (HDcnt_NonAct < 0x90000)) ++ { ++ if(HD_ConfirmCnt > (0xFF - SD_SPEED)) ++ HD_ConfirmCnt = 0xFF; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt + SD_SPEED;; ++ ++ } ++ else ++ { ++ if(HD_ConfirmCnt < 1) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - 1; ++ } ++ ++ if( HD_ConfirmCnt > 0x80 ) ++ HD_ConfirmCnt_Reg = HD_ConfirmCnt - 0x80; ++ else ++ HD_ConfirmCnt_Reg = 0; ++ ++ HD_ConfirmCnt_Reg = (HD_ConfirmCnt_Reg*HDSDD_SPEED) >> HDSDD_DIV; ++ ++ if( HD_ConfirmCnt_Reg > 0x3F ) ++ HD_ConfirmCnt_Reg = 0x3F; ++ ++ //Debug mode for SDHDD detection function ++#if 0 ++ if( HD_ConfirmCnt_Reg == 0x3F ) ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x1000, 0x1000); ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x0000, 0x1000); ++ ++#endif ++ //printf("====HD_ConfirmCnt_Reg===%x\n",HD_ConfirmCnt_Reg); ++ MApi_XC_W2BYTEMSK(REG_SC_BK23_54_L, (MS_U16)HD_ConfirmCnt_Reg, 0x003F); ++ ++} ++ ++ ++MS_U8 MDrv_SC_NEW_SDHD_DETECT_report(void) ++{ ++ MS_U8 u8Value; ++ MS_U16 u16MinPixel,u16MaxPixel, MaxMinPixel; ++ MS_U32 HDcnt_Act, FeatherCnt; ++ MS_U32 SDcnt_Act, SDcnt_NonAct; ++ static MS_U32 PreFeatherCnt = 0; ++ static MS_U16 HD_ConfirmCnt = 0xFF; // 0x7FFF == 0 ++ static MS_U8 u8PrevLuma = 0; ++ static MS_U16 u16PrevMinPixel = 0; ++ static MS_U16 u16PrevMaxPixel = 0; ++ MS_U32 HD_ConfirmCnt_Reg; ++ MS_U16 HDSDD_Det_threshold,HDSDD_Det_offset; ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ HDSDD_Det_offset = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ FeatherCnt = MApi_XC_R2BYTE(REG_SC_BK23_56_L); //New add for A1 chip ++ //FEATHER_CNT_TH = MApi_XC_R2BYTEMSK(REG_SC_BK22_7D_L, 0xFF00)>>8; ++ //printf("====HDcnt_Act===%x\n",HDcnt_Act); ++ //printf("====SDcnt_Act===%x\n",SDcnt_Act); ++ //printf("====HDcnt_NonAct===%x\n",HDcnt_NonAct); ++ //printf("====SDcnt_NonAct===%x\n",SDcnt_NonAct); ++ ++ FeatherCnt = ( PreFeatherCnt*3 + FeatherCnt ) >> 2; ++ PreFeatherCnt = FeatherCnt; ++ ++ #if 0 ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3 + MApi_XC_DLC_GetAverageValue())>>2); ++ #else ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3)>>2); ++ #endif ++ u8PrevLuma = u8Value; ++ ++ u16MaxPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0x00FF); ++ u16MaxPixel = (u16PrevMaxPixel*3 + u16MaxPixel ) >> 2; ++ u16PrevMaxPixel = u16MaxPixel; ++ ++ u16MinPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0xFF00)>>8; ++ u16MinPixel = (u16PrevMinPixel*3 + u16MinPixel ) >> 2; ++ u16PrevMinPixel = u16MinPixel; ++ ++ MaxMinPixel = u16MaxPixel - u16MinPixel; ++ //printf("===u8MinPixel=%x==\n",u16MinPixel); ++ //printf("===MaxMinPixel=%x==\n",MaxMinPixel); ++ ++ if(u8Value>=0xFF) ++ u8Value = 0xFF; ++ //printf("===AvgLuma=%x==\n",u8Value); ++ ++ HDSDD_Det_threshold = HDSDD_Det_offset +((MaxMinPixel*6)>>2) + ((u8Value*5)>>2); ++ //printf("===HDSDD_Det_threshold=%x==\n",HDSDD_Det_threshold); ++ ++ if(HDSDD_Det_threshold >=0xFFFF) ++ { ++ HDSDD_Det_threshold=0xFFFF; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_71_L, (MS_U16)HDSDD_Det_threshold, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_72_L, (MS_U16)(HDSDD_Det_threshold>>1), 0xFFFF); ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ ++ if( (HDcnt_Act > HD_ACT_TH) && (SDcnt_Act != 0) ) ++ { ++ if(HD_ConfirmCnt < HD_SPEED) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - HD_SPEED; ++ } ++ else if( SDcnt_Act != 0 ) //*&& FeatherCnt > FEATHER_CNT_TH*/ )//&& HDcnt_NonAct !=0) // && (HDcnt_NonAct < 0x90000)) ++ { ++ if(HD_ConfirmCnt > (0xFF - SD_SPEED)) ++ HD_ConfirmCnt = 0xFF; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt + SD_SPEED; ++ } ++ else ++ { ++ if(HD_ConfirmCnt < 1) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - 1; ++ } ++ ++ if( HD_ConfirmCnt > 0x80 ) ++ HD_ConfirmCnt_Reg = HD_ConfirmCnt - 0x80; ++ else ++ HD_ConfirmCnt_Reg = 0; ++ ++ HD_ConfirmCnt_Reg = (HD_ConfirmCnt_Reg*HDSDD_SPEED) >> HDSDD_DIV; ++ ++ if( HD_ConfirmCnt_Reg > 0x3F ) ++ HD_ConfirmCnt_Reg = 0x3F; ++ ++ return ((MS_U8)(HD_ConfirmCnt_Reg&0x003F)); ++} ++ ++ ++#if (Auto_DeBlock_En) ++#define ADBW_HD_Loop_Ini_Start 40 ++#define ADBW_HD_Max_Range_End 1440 ++#define ADBW_SD_Loop_Ini_Start 20 ++#define ADBW_SD_Max_Range_End 720 ++static MS_U32 Auto_DBK_Width_val = 8; ++static MS_U32 Auto_DBK_Width_val_tmp = 32; // format is xxxxx.xx ++static MS_U32 Pre_DBK_Width_val = 8; ++ ++void MDrv_SC_Auto_Detect_Blocking_Width_driver(MS_U8 u8SD2HDValue) ++{ ++ int data_ack_en; ++ //int temp_data; ++ int blkwidth_data[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; ++ int blkwidth_s_data[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; ++ long blockiness_data[1440]; ++ MS_BOOL blocking_peakidx[1440]; ++ int bin; ++ int check_width = MApi_XC_R2BYTEMSK(REG_SC_BK12_0F_L, 0xFFFF); ++ int Loop_Ini_Start = (check_width>0x700) ? ADBW_HD_Loop_Ini_Start : ADBW_SD_Loop_Ini_Start; ++ int Max_Range_End = (check_width>0x700) ? ADBW_HD_Max_Range_End : ADBW_SD_Max_Range_End; ++ long fme_blockiness; ++ long frame_maxin_d = 0; ++ long local_maxin_d; ++ int left7,right7; ++ int left2 = 0; ++ int right2 = 0; ++ int left1,right1; ++ int bestblock_width = 8; ++ MS_U32 iir_strength = 2; ++ MS_U8 NMY_DBK_en = 1; ++ //MS_U8 NMY_DBK_gain = 0x10; ++ MS_U32 DBK_frame_blockiness = 0; ++ MS_U32 DBK_frame_blockiness_sum = 0; ++ static MS_U32 DBK_frame_blockiness_iir = 0; ++ MS_U16 test_dummy = MApi_XC_R2BYTEMSK(REG_SC_BK30_01_L, 0x7FFF); ++ MS_U16 test_dummy2 = MApi_XC_R2BYTEMSK(REG_SC_BK30_02_L, 0xFFFF); ++ MS_U16 test_dummy3 = MApi_XC_R2BYTEMSK(REG_SC_BK30_03_L, 0x00FF); ++ MS_U16 dbk_debug_enable = MApi_XC_R2BYTEMSK(REG_SC_BK30_03_L, 0xFFFF)>>15; ++ MS_U16 dbk_iir_diff_thrd = MApi_XC_R2BYTEMSK(REG_SC_BK30_03_L, 0x7F00)>>8; ++ static MS_U16 NMR_Ctrl=0; ++ static MS_U16 NMR_Strength=0; ++ MS_U32 iir_strength_NM = 2; ++ MS_S32 DBK_frame_blockiness_diff=0; ++ //MS_S32 DBK_frame_blockiness_offset=0; ++ static MS_U32 pre_DBK_frame_blockiness=0; ++ int peak_from_blkwidth_data=0; ++ ++ int loc_max = 0; ++ int loc_min = 65535; ++ int cnt; ++ int bestblock_cnt_m = 0; ++ int bestblock_lf1 = 0; ++ int bestblock_idx = 0; ++ int bestblock_rt1 = 0; ++ int bestblock_cnt_m2 = 0; ++ int bestblock_idx2 = 0; ++ int bestblock_cnt_m3 = 0; ++ int bestblock_idx3 = 0; ++ int start_idx = 0; ++ int Currx2_0 = 0; ++ int Lf12x1_1 = 0; ++ int Rt12x1_1 = 0; ++ int Currx1 = 0; ++ int Loc_Maxx0_99 = 0; ++ int local_maxin_dx3= 0; ++ int Pre_DBK_Width_val_tmp; ++ ++ ++ MS_BOOL condition1 = FALSE; ++ MS_BOOL condition2 = FALSE; ++ MS_BOOL condition3 = FALSE; ++ MS_BOOL condition4 = FALSE; ++ ++ ++ // setting HD mode enable ++ if(check_width>0x700) ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_41_L, 0x1, 0x0001); // HD mode ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_41_L, 0x0, 0x0001); // SD mode ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_38_L, 0x4, 0x0004); // setting vertical iir enable ++ ++ //--------- Blockiness Histogram Request start ---------// ++ ++ // write 0 to request register ++ //MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 0, 0x0001); ++ // write 1 to request register ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 1, 0x0001); ++ ++ //--------- Blockiness Histogram Request end ---------// ++ ++ //--------- Blockiness Histogram Acknowledge start ---------// ++ ++ data_ack_en = MApi_XC_R2BYTEMSK(REG_SC_BK0C_0D_L, 0x0002); ++ ++ //--------- Blockiness Histogram Acknowledge end ---------// ++ ++ //--------- Function Process start ---------// ++ if(data_ack_en) ++ { ++ // write 1 to sram_io_en register ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 0x100, 0x0100); ++ for(bin = 0; bin < Max_Range_End; bin++) ++ { ++ // write address ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0E_L, (MS_U16)(0x8000 + bin), 0xFFFF); ++ // read data from selected address ++ blockiness_data[bin] = MApi_XC_R2BYTEMSK(REG_SC_BK0C_0F_L, 0xFFFF); ++ //printf("blockiness[%4d] is %d\n",bin,blockiness_data[bin]); ++ } ++ ++ //printf("blockiness is %d\n",bin); ++ //read frame blockiness data ++ fme_blockiness = ((MApi_XC_R2BYTEMSK(REG_SC_BK0C_61_L, 0xFFFF))<<16) | (MApi_XC_R2BYTEMSK(REG_SC_BK0C_60_L, 0xFFFF)); // frame blockiness data report 32 bit ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 0, 0x0001); ++ //printf("fme_blockiness is %d\n\n",fme_blockiness); ++ ++ //------- find the max local minmax difference start -------// ++ for(bin = Loop_Ini_Start; bin < (Max_Range_End - 40); bin++) ++ { ++ left2 = bin - 2; ++ right2 = bin + 2; ++ ++ loc_max = 0; ++ loc_min = 65535; ++ ++ for(cnt = left2; cnt <= right2; cnt++) ++ { ++ //find max ++ if(blockiness_data[cnt] > loc_max) ++ loc_max = blockiness_data[cnt]; ++ ++ //find min ++ if(blockiness_data[cnt] < loc_min) ++ loc_min = blockiness_data[cnt]; ++ } ++ ++ if(loc_max > loc_min) ++ local_maxin_d = loc_max - loc_min; ++ else ++ local_maxin_d = 0; ++ ++ if(local_maxin_d > frame_maxin_d) ++ frame_maxin_d = local_maxin_d; ++ ++ } ++ //------- find the max local minmax difference end -------// ++ ++ for(bin = 0; bin < Max_Range_End; bin++) ++ blocking_peakidx[bin] = false; ++ ++ //------- find peak index start -------// ++ for(bin = 0; bin < (Max_Range_End - 40); bin++) ++ { ++ left7 = (bin < 7) ? 0 : bin - 7; ++ left1 = (bin < 1) ? 0 : bin - 1; ++ right1 = bin + 1; ++ right7 = bin + 7; ++ ++ loc_max = 0; ++ loc_min = 65535; ++ ++ for(cnt = left7; cnt <= right7; cnt++) ++ { ++ //find max ++ if(blockiness_data[cnt] > loc_max) ++ loc_max = blockiness_data[cnt]; ++ ++ //find min ++ if(blockiness_data[cnt] < loc_min) ++ loc_min = blockiness_data[cnt]; ++ } ++ ++ if(loc_max > loc_min) ++ local_maxin_d = loc_max - loc_min; ++ else ++ local_maxin_d = 0; ++ ++ Currx2_0 = (blockiness_data[bin]<<1); // data x 2 ++ Lf12x1_1 = ((blockiness_data[left1] + blockiness_data[left2])*11)/10; // data x 1.1 ++ Rt12x1_1 = ((blockiness_data[right1] + blockiness_data[right2])*11)/10; // data x 1.1 ++ Currx1 = blockiness_data[bin]; // data x 1 ++ Loc_Maxx0_99 = (loc_max*85)/100; // data x 0.85 // ori is data x 0.99 ++ local_maxin_dx3 = local_maxin_d*3; // data x 3 ++ ++ if((Currx2_0>Lf12x1_1)&&(Currx2_0>Rt12x1_1)&&(Currx1>Loc_Maxx0_99)&&(local_maxin_dx3>frame_maxin_d) && (blockiness_data[bin] > blockiness_data[left1]) && (blockiness_data[bin] > blockiness_data[right1])) ++ blocking_peakidx[cnt] = true; ++ } ++ //------- find peak index end -------// ++ ++ //------- find best block width start -------// ++ start_idx = 0; ++ ++ for(bin = 0; bin < Max_Range_End; bin++) ++ { ++ if((blocking_peakidx[bin]==true)&&(bin!=start_idx)) ++ { ++ cnt = bin - start_idx; ++ if( cnt < 31) ++ blkwidth_data[cnt] += 1; ++ ++ start_idx = bin; ++ } ++ } ++ //------- find best block width end -------// ++ peak_from_blkwidth_data = 0; ++ for(bin = 8; bin < 31; bin ++) ++ { ++ if( blkwidth_data[bin]> peak_from_blkwidth_data ) ++ peak_from_blkwidth_data = blkwidth_data[bin]; ++ } ++ //------- summarize 1x3 on blkwidth start -------// ++ ++ for(bin = 5; bin < 31; bin ++) ++ { ++ left1 = (bin < 1) ? 0 : bin - 1; ++ right1 = (bin >= 31) ? 30 : bin + 1; ++ ++ loc_max = 0; ++ ++ for(cnt = left1; cnt <= right1; cnt++) ++ { ++ //find max ++ if(blkwidth_data[cnt] > loc_max) ++ loc_max = blkwidth_data[cnt]; ++ } ++ ++ if(blkwidth_data[bin] > (loc_max>>1)) ++ blkwidth_s_data[bin] = blkwidth_data[left1] + blkwidth_data[bin] + blkwidth_data[right1]; ++ } ++ ++ //------- summarize 1x3 on blkwidth end -------// ++ ++ //------- find the 1st max block width start -------// ++ ++ for(bin = 5; bin < 31; bin++) ++ { ++ if(blkwidth_s_data[bin] > bestblock_cnt_m) ++ { ++ bestblock_cnt_m = blkwidth_s_data[bin]; ++ bestblock_idx = bin; ++ } ++ } ++ ++ bestblock_lf1 = bestblock_idx - 1; ++ bestblock_rt1 = bestblock_idx + 1; ++ blkwidth_s_data[bestblock_idx] = 0; ++ ++ //printf("1st width is %d | cnt is %d\n",bestblock_idx,bestblock_cnt_m); ++ //------- find the 1st max block width end -------// ++ ++ //------- find the 2nd max block width start -------// ++ ++ ++ for(bin = 5; bin < 31; bin++) ++ { ++ if((blkwidth_s_data[bin] > bestblock_cnt_m2)&&((bin > bestblock_rt1) || (bin < bestblock_lf1))) ++ { ++ bestblock_cnt_m2 = blkwidth_s_data[bin]; ++ bestblock_idx2 = bin; ++ } ++ } ++ ++ bestblock_lf1 = bestblock_idx2 - 1; ++ bestblock_rt1 = bestblock_idx2 + 1; ++ blkwidth_s_data[bestblock_idx2] = 0; ++ ++ //printf("2nd width is %d | cnt is %d\n",bestblock_idx2,bestblock_cnt_m2); ++ //------- find the 2nd max block width end -------// ++ ++ //------- find the 3rd max block width start -------// ++ ++ ++ for(bin = 5; bin < 31; bin++) ++ { ++ if((blkwidth_s_data[bin] > bestblock_cnt_m3)&&((bin > bestblock_rt1) || (bin < bestblock_lf1))) ++ { ++ bestblock_cnt_m3 = blkwidth_s_data[bin]; ++ bestblock_idx3 = bin; ++ } ++ } ++ ++ //printf("3rd width is %d | cnt is %d\n",bestblock_idx3,bestblock_cnt_m3); ++ //------- find the 3rd max block width end -------// ++ ++ //printf("SD2HD is %d\n",u8SD2HDValue); ++ ++ if((u8SD2HDValue>=60)&&(check_width>0x700)) ++ { ++ if((bestblock_idx>=20)&&(bestblock_idx<=22)) ++ { ++ bestblock_cnt_m = 100; ++ //printf("SD2HD is 1st\n"); ++ } ++ else if((bestblock_idx2>=20)&&(bestblock_idx2<=22)) ++ { ++ bestblock_idx = bestblock_idx2; ++ bestblock_cnt_m = 100; ++ //printf("SD2HD is 2nd\n"); ++ } ++ else if((bestblock_idx3>=20)&&(bestblock_idx3<=22)) ++ { ++ bestblock_idx = bestblock_idx3; ++ bestblock_cnt_m = 100; ++ //printf("SD2HD is 3rd\n"); ++ } ++ } ++ ++ //------- calculate best block width start -------// ++ condition1 = ((bestblock_cnt_m<<1) >= (bestblock_cnt_m2*3)) ? true : false; // m1 >= m2*1.5 ++ condition2 = ((bestblock_cnt_m ) >= (bestblock_cnt_m3<<1)) ? true : false; // m1 >= m3*2 ++ condition3 = (bestblock_cnt_m > 15) ? true : false; ++ condition4 = (bestblock_idx > 6) ? true : false; ++ ++ if(condition1&& condition2&&condition3&&condition4) ++ { ++ bestblock_width = bestblock_idx; ++ ++ if((u8SD2HDValue==00)&&(check_width>0x700)&&(bestblock_width==16)) ++ bestblock_width = 8; ++ ++ Pre_DBK_Width_val = bestblock_width; ++ //printf("##bestblock_width is %d##\n",bestblock_width); ++ } ++ //printf("Pre_DBK_Width_val is %d\n",Pre_DBK_Width_val); ++ ++ // iir ++ Pre_DBK_Width_val_tmp = (Pre_DBK_Width_val<<2); // format is xxxxx.xx ++ Auto_DBK_Width_val_tmp = ((iir_strength*Pre_DBK_Width_val_tmp) + (8-iir_strength)*Auto_DBK_Width_val_tmp)/8; // format is xxxxx.xx ++ Auto_DBK_Width_val = (Auto_DBK_Width_val_tmp>>2); // format is xxxxx.0 ++ ++ if(Auto_DBK_Width_val<=8) ++ { ++ Auto_DBK_Width_val = 8; ++ left1 = 8; ++ right1 = 8; ++ } ++ else ++ { ++ left1 = (Auto_DBK_Width_val < 1) ? 0 : Auto_DBK_Width_val - 1; ++ right1 = (Auto_DBK_Width_val >=31) ? 31 : Auto_DBK_Width_val + 1; ++ } ++ ++ // write interval left && interval right ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_39_L, (MS_U16)((right1<<8)|left1), 0xFFFF); ++ //------- calculate best block width end -------// ++ //printf("Final width is %d <=====\n",Auto_DBK_Width_val); ++ ++ if(data_read) ++ { ++ NMR_Ctrl = MApi_XC_R2BYTEMSK(REG_SC_BK0C_50_L, 0x0001); ++ NMR_Strength = MApi_XC_R2BYTEMSK(REG_SC_BK0C_54_L, 0x003F); ++ data_read = false; ++ } ++ ++ DBK_frame_blockiness_sum=0; ++ for(bin = 0; bin < (Max_Range_End ); bin=bin+Auto_DBK_Width_val) ++ { ++ loc_max = 0; ++ loc_min = 0xFFFFFFFF; ++ ++ for(cnt = 0; ((MS_U32)cnt) <= Auto_DBK_Width_val-1; cnt++) ++ { ++ //find max ++ if(((MS_U32)blockiness_data[bin+cnt] > ((MS_U32)loc_max))&&((bin+cnt)<1440)) ++ loc_max = (MS_U32)blockiness_data[bin+cnt]; ++ ++ //find min ++ if(((MS_U32)blockiness_data[bin+cnt] < ((MS_U32)loc_min))&&((bin+cnt)<1440)) ++ loc_min = (MS_U32)blockiness_data[bin+cnt]; ++ } ++ ++ if(loc_max > loc_min) ++ { ++ local_maxin_d = loc_max - loc_min; ++ } ++ else ++ { ++ local_maxin_d = 0; ++ } ++ DBK_frame_blockiness_sum += local_maxin_d; ++ } ++ //printf("====DBK_frame_blockiness_sum= %x \n",DBK_frame_blockiness_sum); ++ ++ DBK_frame_blockiness = DBK_frame_blockiness_sum*Auto_DBK_Width_val / (Max_Range_End) ; ++ ++ //printf("====DBK_frame_blockiness= %x \n",DBK_frame_blockiness); ++ ++ if(pre_DBK_frame_blockiness >= DBK_frame_blockiness) ++ { ++ DBK_frame_blockiness_diff = pre_DBK_frame_blockiness - DBK_frame_blockiness; ++ } ++ else ++ { ++ DBK_frame_blockiness_diff = DBK_frame_blockiness - pre_DBK_frame_blockiness; ++ } ++ /* ++ if(u8SD2HDValue>=60) ++ { ++ DBK_frame_blockiness_offset= 0xB00; ++ } ++ else ++ { ++ DBK_frame_blockiness_offset = 0 ; ++ } ++ */ ++ ++ if( DBK_frame_blockiness_diff > ((dbk_iir_diff_thrd<<8) )) ++ { ++ iir_strength_NM = 8; ++ } ++ else ++ { ++ iir_strength_NM = 2; ++ } ++ ++ DBK_frame_blockiness_iir = (DBK_frame_blockiness*iir_strength_NM+ DBK_frame_blockiness_iir*(8-iir_strength_NM))/8; ++ ++ if(dbk_debug_enable) ++ { ++ printf("DBK_frame_blockiness_sum is %lx <=====\n",DBK_frame_blockiness_sum); ++ printf("DBK_frame_blockiness is %lx <=====\n",DBK_frame_blockiness); ++ printf("DBK_frame_blockiness_iir is %lx <=====\n",DBK_frame_blockiness_iir); ++ printf("u8SD2HDValue is %x <=====\n",u8SD2HDValue); ++ } ++ ++ pre_DBK_frame_blockiness = DBK_frame_blockiness; ++ ++ if((fme_blockiness>= (test_dummy3 <<8)) && (peak_from_blkwidth_data>=10) ) //0x100000 // multiburst pan ++ { ++ if(DBK_frame_blockiness_iir>= (test_dummy)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMY_DBK_en, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, 0x1F, 0x003F); ++ } ++ else if((DBK_frame_blockiness_iir< (test_dummy)) && (DBK_frame_blockiness_iir >= (test_dummy2))) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMY_DBK_en, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, 0x15, 0x003F); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMR_Ctrl, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, NMR_Strength, 0x003F); ++ } ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMR_Ctrl, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, NMR_Strength, 0x003F); ++ } ++ ++ //printf("====End==%lx=\n",MsOS_GetSystemTime()); ++ } ++ //--------- Function Process end ---------// ++} ++#endif ++ ++static MS_U32 md_adjust_level_iir = 0; ++static MS_U32 psnr_std_level_thrd_iir = 0; ++static MS_U32 dnr_std_thrd_iir = 0; ++static MS_U32 luma_sum_pre=0; ++ ++//static MS_U32 hismatch_level_thrd_iir=0 ; ++static MS_U16 dnr_md_high_thrd_level_iir =0; ++static MS_U16 dnr_md_low_thrd_level_iir =0; ++ ++//void MDrv_SC_HISNR_T9_driver(U16 u16Width, U16 u16Height) ++void MDrv_SC_HISNR_driver(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ MS_BOOL histogram_ack_en=0; ++ MS_U16 noise_histogram[16]; ++ MS_U16 noise_histogram_scaled[16]; ++ MS_U32 scaled_ratio = 4; ++ //MS_U16 rounding_bit=0; ++ MS_U16 bin; ++ // define value ++ MS_U16 noise_level_low_thrd_0 = 0x0; ++ MS_U16 noise_level_low_thrd_1 = 0x18; ++ MS_U16 noise_level_low_thrd_2 = 0x28; ++ MS_U16 noise_level_low_thrd_3 = 0x38; ++ MS_U16 noise_level_high_thrd_3 = 0x60; ++ // AUTO NR, HISDNR ++ MS_U16 noise_bin_step = 0x00; ++ MS_U16 noise_bin_thrd = 0x4C; ++ MS_U16 pause_ack = 0; ++ // ++ //MS_U16 hismatch_level0,hismatch_level1,hismatch_level2,hismatch_level3; ++ MS_U16 dnr_std_level0,dnr_std_level1,dnr_std_level2, dnr_std_level3; ++ MS_U16 md_adjust_level0,md_adjust_level1,md_adjust_level2, md_adjust_level3; ++ MS_U16 psnr_std_level0_thrd,psnr_std_level1_thrd,psnr_std_level2_thrd, psnr_std_level3_thrd; ++ MS_U16 dnr_md_high_thrd_level0,dnr_md_low_thrd_level0; ++ MS_U16 dnr_md_high_thrd_level1,dnr_md_low_thrd_level1; ++ MS_U16 dnr_md_high_thrd_level2,dnr_md_low_thrd_level2; ++ MS_U16 dnr_md_high_thrd_level3,dnr_md_low_thrd_level3; ++ // ++ //MS_U16 hismatch_level_thrd=0; ++ MS_U16 dnr_std_level=0; ++ MS_U16 dnr_md_high_thrd_level=0; ++ MS_U16 dnr_md_low_thrd_level=0; ++ MS_U16 md_adjust_level=0; ++ MS_U16 psnr_std_level_thrd=0; ++ // MS_U16 PSNR_his_bs_bit; ++ MS_U16 md_pre_shift=0; ++ MS_U16 md_pre_gain=0; ++ ++ MS_U16 u16Height_div; ++ MS_U16 V_start_height; ++ MS_U16 V_end_height; ++ MS_U16 V_active_height; ++ MS_U16 H_start_width,H_end_width; ++ ++ MS_U16 H_active_width; ++ MS_U32 pixel_number; // directly take ++ MS_U16 LargerThanHigh; ++ MS_U16 Off_from_low; ++ //MS_U16 cond_diagonal; ++ MS_U16 adjust_alpha; ++ MS_U32 weighted_sum; ++ MS_U32 weighted_sumother=0; ++ MS_U32 luma_sum; ++ MS_S32 luma_avg_pre; // 16bits ++ MS_S32 luma_avg; ++ MS_S32 luma_avg_diff; ++ MS_U32 iir_strength; ++ MS_U16 histogram_max = 0; ++ MS_U16 histogram_maxdiff=0; ++ MS_U16 BitsValue_4; ++ MS_U16 max_bin = 0; ++ MS_U16 max_value = 0; ++ MS_U16 result; ++ MS_U32 adjust_result; ++ MS_U16 calculated_result; ++ MS_U16 noise_level_int=0; ++ MS_U16 noise_strength; ++ MS_S16 md_adjust_level_offset=md_adjust_level; ++ ++ XC_ApiStatus stXCStatus; ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ if(stXCStatus.bInterlace) ++ u16Height_div = u16Height / 2 ; ++ else ++ u16Height_div = u16Height ; ++ ++ ++ scaled_ratio = (MS_U32)(4.0 * (u16Width*u16Height_div/172800)); // 720*240 = 172800 ++ ++ if(scaled_ratio<4) ++ scaled_ratio =4; ++ ++ if(u16Width<=1000) ++ V_start_height = u16Height_div/240; ++ else ++ V_start_height = 0x10; ++ ++ V_end_height = (u16Height_div - V_start_height*8)/8; ++ V_active_height = (V_end_height-V_start_height)*8; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_32_L, V_start_height, 0x00FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_32_L, V_end_height<<8, 0xFF00); ++ ++ H_start_width = 0; ++ H_end_width = u16Width/8; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_31_L, H_start_width, 0x00FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_31_L, H_end_width<<8, 0xFF00); ++ ++ H_active_width = (H_end_width-H_start_width)*8; ++ pixel_number =(H_active_width*V_active_height) ; // directly take ++ ++ //------------------------------------------------------- ++ while ( !histogram_ack_en ) ++ histogram_ack_en = (MApi_XC_R2BYTEMSK(REG_SC_BK0E_01_L, BIT(2))?TRUE:FALSE); ++ ++ if (histogram_ack_en) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_01_L, 1, BIT(2)); ++ ++ noise_histogram[0] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_10_L, 0xFFFF); ++ noise_histogram[1] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_11_L, 0xFFFF); ++ noise_histogram[2] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_12_L, 0xFFFF); ++ noise_histogram[3] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_13_L, 0xFFFF); ++ noise_histogram[4] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_14_L, 0xFFFF); ++ noise_histogram[5] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_15_L, 0xFFFF); ++ noise_histogram[6] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_16_L, 0xFFFF); ++ noise_histogram[7] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_17_L, 0xFFFF); ++ noise_histogram[8] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_18_L, 0xFFFF); ++ noise_histogram[9] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_19_L, 0xFFFF); ++ noise_histogram[10] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1A_L, 0xFFFF); ++ noise_histogram[11] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1B_L, 0xFFFF); ++ noise_histogram[12] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1C_L, 0xFFFF); ++ noise_histogram[13] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1D_L, 0xFFFF); ++ noise_histogram[14] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1E_L, 0xFFFF); ++ noise_histogram[15] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1F_L, 0xFFFF); ++ ++ for(bin=0; bin<16; bin++) ++ noise_histogram_scaled[bin] = (MS_U16)((MS_S32)noise_histogram[bin]/scaled_ratio); ++ ++ weighted_sum = noise_histogram_scaled[0]*64*scaled_ratio; // 6bits ++ ++ for(bin=5; bin<16; bin++) ++ weighted_sumother += noise_histogram_scaled[bin]; ++ // read luma sum ++ luma_sum = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_48_L, 0xFFFF); ++ ++ // get image size 480i,1080i ++ ++ //------- ++ luma_avg_pre = (luma_sum_pre*16384)/pixel_number; // 16bits ++ luma_avg = (luma_sum*16384)/pixel_number; ++ luma_avg_diff = (MS_U16) abs(luma_avg_pre-luma_avg); ++ ++ luma_sum_pre = luma_sum; ++ ++ iir_strength=2; ++ ++ // remove pause_ack ++ if(luma_avg_diff>=20) ++ iir_strength=8; ++ ++ // alpha before moodify ++ if( (weighted_sum >= (3*pixel_number/4)) && (weighted_sumother!=0)) ++ { ++ pause_ack = 2; ++ } ++ ++ //if(pause_ack==0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_20_L, noise_histogram_scaled[0], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_21_L, noise_histogram_scaled[1], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_22_L, noise_histogram_scaled[2], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_23_L, noise_histogram_scaled[3], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_24_L, noise_histogram_scaled[4], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_25_L, noise_histogram_scaled[5], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_26_L, noise_histogram_scaled[6], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_27_L, noise_histogram_scaled[7], 0x03FF); ++ } ++ ++ //hismatch_level0 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_07_L, 0x00FF); ++ //hismatch_level1 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_08_L, 0x00FF); ++ //hismatch_level2 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_09_L, 0x00FF); ++ //hismatch_level3 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_49_L, 0xFF00)>>8); ++ ++ dnr_std_level0 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_07_L, 0xFF00)>>8); ++ dnr_std_level1 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_08_L, 0xFF00)>>8); ++ dnr_std_level2 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_09_L, 0xFF00)>>8); ++ dnr_std_level3 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_4B_L, 0x00FF); ++ ++ dnr_md_high_thrd_level0 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_03_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level0 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_03_L, 0x00FF); ++ dnr_md_high_thrd_level1 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_04_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level1 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_04_L, 0x00FF); ++ dnr_md_high_thrd_level2 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_05_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level2 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_05_L, 0x00FF); ++ dnr_md_high_thrd_level3 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_4A_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level3 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_4A_L, 0x00FF); ++ ++ md_adjust_level0 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_06_L, 0x000F)>>0); ++ md_adjust_level1 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_06_L, 0x00F0)>>4); ++ md_adjust_level2 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_06_L, 0x0F00)>>8); ++ md_adjust_level3 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_49_L, 0x000F)>>0); ++ ++ psnr_std_level0_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2A_L, 0x00FF)>>0); ++ psnr_std_level1_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2B_L, 0xFF00)>>8); ++ psnr_std_level2_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2C_L, 0x00FF)>>0); ++ psnr_std_level3_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2D_L, 0x00FF)>>0); ++ ++ for (bin =0; bin<8;bin++) ++ { ++ if(histogram_max<=noise_histogram_scaled[bin]) ++ histogram_max=noise_histogram_scaled[bin] ; ++ } ++ ++ for (bin =0; bin<8;bin++) ++ histogram_maxdiff +=abs(histogram_max-noise_histogram_scaled[bin]) ; ++ ++ if( histogram_maxdiff > noise_bin_thrd ) ++ { ++ //cond_diagonal = 1; ++ adjust_alpha = 0xF; ++ } ++ else ++ { ++ Off_from_low = noise_bin_thrd - histogram_maxdiff; ++ //cond_diagonal = 0; ++ switch( noise_bin_step ) ++ { ++ case 0: BitsValue_4 = Off_from_low &0xF; ++ LargerThanHigh = ( ( Off_from_low >> 4) >0 ) ? 1 : 0; ++ break; ++ case 1: BitsValue_4 = (Off_from_low>>1 )&0xF; ++ LargerThanHigh = ( ( Off_from_low >>5) >0 ) ? 1 : 0; ++ break; ++ case 2: BitsValue_4 = ( Off_from_low >>2)&0xF; ++ LargerThanHigh = ( ( Off_from_low >>6) >0 ) ? 1 : 0; ++ break; ++ case 3: BitsValue_4 = ( Off_from_low>>3 )&0xF; ++ LargerThanHigh = ( ( Off_from_low >>7) >0 ) ? 1 : 0; ++ break; ++ ++ default: ++ break; ++ } // end switch ++ ++ if( LargerThanHigh == 1) ++ adjust_alpha = 0; ++ else ++ adjust_alpha = ~BitsValue_4; ++ adjust_alpha = adjust_alpha &0x0F; ++ ++ } // end of diag switch ++ ++ //MS_U16 max_result = 0; ++ ++ for(bin=0; bin<5;bin++) ++ { ++ if(noise_histogram_scaled[bin]+noise_histogram_scaled[bin+1]>=max_value) ++ max_value = noise_histogram_scaled[bin]+noise_histogram_scaled[bin+1]; ++ } ++ ++ for (bin=0; bin<5;bin++) ++ { ++ if( (noise_histogram_scaled[bin]+noise_histogram_scaled[bin+1])==max_value) ++ max_bin = bin; ++ } ++ ++ if ( 0 == max_bin ) //34 is ok , wh ++ result = 16; ++ else if ( 1 == max_bin) ++ result = 32; ++ else if ( 2 == max_bin) ++ result = 48; ++ else if(3 == max_bin) ++ result =64; ++ else if( (4 == max_bin) || (5 == max_bin) ) ++ result = 80; // 70 @@@@@@@@@ ++ else ++ result= 16; ++ ++ adjust_result = (MS_U32)((result * adjust_alpha+8)/16.0); ++ calculated_result = (MS_U16)(adjust_result); ++ ++ if ( (noise_level_low_thrd_0 <= calculated_result) && (calculated_result < noise_level_low_thrd_1)) //34 is ok , wh ++ { ++ noise_level_int = 0; ++ } ++ else if ( (noise_level_low_thrd_1 <= calculated_result) && (calculated_result< noise_level_low_thrd_2)) ++ { ++ noise_level_int = 1; ++ } ++ else if ( (noise_level_low_thrd_2 <= calculated_result) && (calculated_result< noise_level_low_thrd_3)) ++ { ++ noise_level_int = 2; ++ } ++ else if((noise_level_low_thrd_3 <= calculated_result) && (calculated_result < noise_level_high_thrd_3)) ++ { ++ noise_level_int =3; ++ } ++ ++ noise_strength = MApi_XC_R2BYTEMSK(REG_SC_BK0E_4B_L, 0xFF00)>>8; ++ ++ if(noise_level_int==0) ++ { ++ //hismatch_level_thrd = hismatch_level0; ++ dnr_std_level = dnr_std_level0; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level0; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level0; ++ md_adjust_level = md_adjust_level0; ++ psnr_std_level_thrd = psnr_std_level0_thrd; ++ md_pre_shift = 5; ++ md_pre_gain = 6; ++ } ++ else if(noise_level_int==1) ++ { ++ //hismatch_level_thrd = hismatch_level1; ++ dnr_std_level = dnr_std_level1; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level1; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level1; ++ md_adjust_level = md_adjust_level1; ++ psnr_std_level_thrd = psnr_std_level1_thrd; ++ md_pre_shift = 2; ++ md_pre_gain = 1; ++ } ++ else if(noise_level_int==2) ++ { ++ //hismatch_level_thrd = hismatch_level2; ++ dnr_std_level = dnr_std_level2; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level2; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level2; ++ md_adjust_level = md_adjust_level2; ++ psnr_std_level_thrd = psnr_std_level2_thrd; ++ md_pre_shift = 2; ++ md_pre_gain = 1; ++ ++ } ++ else if(noise_level_int==3 ) ++ { ++ //hismatch_level_thrd = hismatch_level3 ; ++ dnr_std_level = dnr_std_level3; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level3; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level3; ++ md_adjust_level = md_adjust_level3; ++ psnr_std_level_thrd = psnr_std_level3_thrd; ++ md_pre_shift = 2; ++ md_pre_gain = 1; ++ ++ } ++ ++ md_adjust_level_offset = md_adjust_level; ++ ++ if(noise_strength==0) ++ md_adjust_level_offset = (md_adjust_level-2); ++ else if(noise_strength==1) ++ md_adjust_level_offset = (md_adjust_level-1); ++ else if(noise_strength==3) ++ md_adjust_level_offset = (md_adjust_level+1); ++ else if(noise_strength==4) ++ md_adjust_level_offset = (md_adjust_level+2); ++ ++ if(md_adjust_level_offset<0) ++ md_adjust_level_offset = 0; ++ else if(md_adjust_level_offset>0xF) ++ md_adjust_level_offset = 0xF; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_30_L, md_pre_gain, 0x003F); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_30_L, (md_pre_shift<<8), 0x0700); ++ ++ //if(pause_ack == 0) ++ //{ ++ // hismatch_level_thrd_iir= (iir_strength*hismatch_level_thrd + (8-iir_strength)*hismatch_level_thrd_iir)/8 ; ++ // rounding_bit = (iir_strength*hismatch_level_thrd + (8-iir_strength)*hismatch_level_thrd_iir)&0x04; ++ //} ++ //MApi_XC_W2BYTEMSK(REG_SC_BK0E_0C_L, (MS_U16)(hismatch_level_thrd_iir+rounding_bit/4) , 0x00FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0C_L, 0 , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ dnr_std_thrd_iir = (iir_strength*dnr_std_level *4+ (8-iir_strength)*dnr_std_thrd_iir)/8 ; // *4/8(iir) = /2 ==> X.2 format ++ //rounding_bit = (iir_strength*dnr_std_level + (8-iir_strength)*dnr_std_thrd_iir)&0x04; ++ } ++ if(pause_ack == 2) ++ dnr_std_thrd_iir= 5*4 ; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0D_L, (MS_U16)( dnr_std_thrd_iir/4 + (dnr_std_thrd_iir&0x02)/2 ) , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ //dnr_md_high_thrd_level_iir= (iir_strength*dnr_md_high_thrd_level + (8-iir_strength)*dnr_md_high_thrd_level_iir)/2.0 ; // *4/8(iir) = /2 ==> X.2 format ++ dnr_md_high_thrd_level_iir= (MS_U16)((iir_strength*dnr_md_high_thrd_level *4+ (8-iir_strength)*dnr_md_high_thrd_level_iir)/8) ; // *4/8(iir) = /2 ==> X.2 format ++ //rounding_bit = (iir_strength*dnr_md_high_thrd_level + (8-iir_strength)*dnr_md_high_thrd_level_iir)&0x04; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0B_L, (MS_U16)(dnr_md_high_thrd_level_iir/4 + (dnr_md_high_thrd_level_iir&0x02)/2) , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ dnr_md_low_thrd_level_iir= (MS_U16)((iir_strength*dnr_md_low_thrd_level*4+ (8-iir_strength)*dnr_md_low_thrd_level_iir)/8) ; // *4/8(iir) = /2 ==> X.2 format ++ //rounding_bit = (iir_strength*dnr_md_low_thrd_level + (8-iir_strength)*dnr_md_low_thrd_level_iir)&0x04; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0A_L, (MS_U16)(dnr_md_low_thrd_level_iir/4 + (dnr_md_low_thrd_level_iir&0x02)/2 ) , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ md_adjust_level_iir= (iir_strength*md_adjust_level_offset*4 +(8-iir_strength)*md_adjust_level_iir)/8 ; ++ //rounding_bit = (iir_strength*md_adjust_level +(8-iir_strength)*md_adjust_level_iir)&0x04; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_06_L, ((MS_U16)(md_adjust_level_iir/4 + (md_adjust_level_iir&0x02)/2) )<<0xC , 0xF000); ++ ++ //if(pause_ack == 0) ++ { ++ psnr_std_level_thrd_iir= (iir_strength*psnr_std_level_thrd*4 + (8-iir_strength)*psnr_std_level_thrd_iir)/8 ; ++ //rounding_bit = (iir_strength*psnr_std_level_thrd + (8-iir_strength)*psnr_std_level_thrd_iir)&0x04; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_2D_L, ((MS_U16)( psnr_std_level_thrd_iir/4 + (psnr_std_level_thrd_iir&0x02)/2 ) )<<0x8 , 0xFF00); ++ } ++ ++} ++ ++ ++static MS_U16 g_u16BK0A_24 = 0; ++static MS_U16 g_u16BK0C_10 = 0; ++static MS_U16 g_u16BK0C_39 = 0; ++static MS_U16 g_u16BK0C_3A = 0; ++static MS_U16 g_u16BK0C_40 = 0; ++static MS_U16 g_u16BK0C_41 = 0; ++static MS_U16 g_u16BK0C_42 = 0; ++static MS_U16 g_u16BK26_10 = 0; ++static MS_U16 g_u16BK26_11 = 0; ++static MS_U16 g_u16BK26_12 = 0; ++static MS_U16 g_u16BK26_13 = 0; ++static MS_U16 g_u16BK26_18 = 0; ++ ++/******************************************************************************/ ++///Film mode control for Any Candence ++///@param bEnable \ IN: Enable/Disable control ++/******************************************************************************/ ++void MApi_XC_FilmMode_AnyCandence_Enable(MS_BOOL bEnable) ++{ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, (bEnable ? (BIT(15)) : 0), BIT(15)); ++ g_bAnyCandenceEnable = bEnable; ++} ++ ++/******************************************************************************/ ++///De-Blocking Control ++///@param bEnable \ IN: Enable/Disable control ++/******************************************************************************/ ++void MApi_XC_DBK_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel) ++{ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, bEnable, BIT(0)); ++ if(bEnable) ++ { ++ switch(eLevel) ++ { ++ default: ++ case Level_Low: ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, (0x1F) << 8, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, 0x0709); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_3A_L, 0x06, 0x00FF); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, 0x0563); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, 0x0442); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, 0x0412); ++ break; ++ case Level_MID: ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, (0x40) << 8, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, 0x0709); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_3A_L, 0x05, 0x00FF); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, 0x0767); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, 0x0742); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, 0x0912); ++ break; ++ case Level_High: ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, (0x80) << 8, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, 0x0709); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_3A_L, 0x05, 0x00FF); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, 0x0767); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, 0x0742); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, 0x0902); ++ break; ++ } ++ } ++} ++ ++ ++/******************************************************************************/ ++///De-Mosquito Control ++///@param bEnable \ IN: Enable/Disable control ++/******************************************************************************/ ++void MApi_XC_DMS_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel) ++{ ++ MApi_XC_W2BYTEMSK(REG_SC_BK26_10_L, bEnable, BIT(0)); ++ if(bEnable) ++ { ++ switch(eLevel) ++ { ++ default: ++ case Level_Low: ++ MApi_XC_W2BYTEMSK(REG_SC_BK26_10_L, 0x1000, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK26_11_L, 0x0110); ++ MApi_XC_W2BYTE(REG_SC_BK26_12_L, 0x0000); ++ MApi_XC_W2BYTE(REG_SC_BK26_13_L, 0x0006); ++ MApi_XC_W2BYTE(REG_SC_BK26_18_L, 0x0020); ++ break; ++ case Level_MID: ++ break; ++ case Level_High: ++ MApi_XC_W2BYTEMSK(REG_SC_BK26_10_L, 0x1500, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK26_11_L, 0x0110); ++ MApi_XC_W2BYTE(REG_SC_BK26_12_L, 0x0000); ++ MApi_XC_W2BYTE(REG_SC_BK26_13_L, 0x0110); ++ MApi_XC_W2BYTE(REG_SC_BK26_18_L, 0x0000); ++ break; ++ } ++ } ++ ++} ++ ++/******************************************************************************/ ++///Store the Current value ++/******************************************************************************/ ++void MApi_XC_SotreCurrentValue(void) ++{ ++ //for AnyCandence Film Mode ++ g_u16BK0A_24 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_24_L, BIT(15)); ++ ++ //for DBK ++ g_u16BK0C_10 = MApi_XC_R2BYTE(REG_SC_BK0C_10_L); ++ g_u16BK0C_39 = MApi_XC_R2BYTE(REG_SC_BK0C_39_L); ++ g_u16BK0C_3A = MApi_XC_R2BYTE(REG_SC_BK0C_3A_L); ++ g_u16BK0C_40 = MApi_XC_R2BYTE(REG_SC_BK0C_40_L); ++ g_u16BK0C_41 = MApi_XC_R2BYTE(REG_SC_BK0C_41_L); ++ g_u16BK0C_42 = MApi_XC_R2BYTE(REG_SC_BK0C_42_L); ++ ++ //for DMS ++ g_u16BK26_10 = MApi_XC_R2BYTE(REG_SC_BK26_10_L); ++ g_u16BK26_11 = MApi_XC_R2BYTE(REG_SC_BK26_11_L); ++ g_u16BK26_12 = MApi_XC_R2BYTE(REG_SC_BK26_12_L); ++ g_u16BK26_13 = MApi_XC_R2BYTE(REG_SC_BK26_13_L); ++ g_u16BK26_18 = MApi_XC_R2BYTE(REG_SC_BK26_18_L); ++} ++ ++/******************************************************************************/ ++///Store the Current value ++/******************************************************************************/ ++void MApi_XC_ReSotreToDefault(void) ++{ ++ //for AnyCandence Film Mode ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, g_u16BK0A_24, BIT(15)); ++ ++ //for DBK ++ MApi_XC_W2BYTE(REG_SC_BK0C_10_L, g_u16BK0C_10); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, g_u16BK0C_39); ++ MApi_XC_W2BYTE(REG_SC_BK0C_3A_L, g_u16BK0C_3A); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, g_u16BK0C_40); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, g_u16BK0C_41); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, g_u16BK0C_42); ++ ++ //for DMS ++ MApi_XC_W2BYTE(REG_SC_BK26_10_L, g_u16BK26_10); ++ MApi_XC_W2BYTE(REG_SC_BK26_11_L, g_u16BK26_11); ++ MApi_XC_W2BYTE(REG_SC_BK26_12_L, g_u16BK26_12); ++ MApi_XC_W2BYTE(REG_SC_BK26_13_L, g_u16BK26_13); ++ MApi_XC_W2BYTE(REG_SC_BK26_18_L, g_u16BK26_18); ++} ++ ++#define ENABLE_SCALER_DEFEATHERING 0x01 //BK22_7C_L ++#define ENABLE_SCALER_DEFLICKERING 0x02 ++#define ENABLE_SCALER_DEBOUNCING 0x04 ++#define ENABLE_SCALER_DYNAMIC_SNR 0x08 ++#define ENABLE_SCALER_DYNAMIC_DNR 0x10 ++#define ENABLE_SCALER_DYNAMIC_FILM22 0x20 ++#define ENABLE_SCALER_DEPRESNR 0x40 ++#define ENABLE_SCALER_FANTASTICDNR 0x80 ++#define ENABLE_SCALER_MCDI_DRIVER 0x01 //BK22_7C_H ++#define ENABLE_SCALER_MCNR_DRIVER 0x02 ++#define ENABLE_SCALER_FILM_DRIVER 0x04 ++#define ENABLE_SCALER_JANUS_DHD_DRIVER 0x08 ++#define ENABLE_SCALER_HISDNR_DRIVER 0x10 ++#define ENABLE_SCALER_SDHD_DETECT_DRIVER 0x20 ++#define ENABLE_SCALER_T12_UCDI_DRIVER 0x40 ++#define ENABLE_SCALER_NEW_SDHD_DETECT_DRIVER 0x80 ++#define ENABLE_SCALER_EXTEND_UCDI_DRIVER 0x01 //BK22_7E_L ++#define ENABLE_SCALER_NEW_FILM_DRIVER 0x02 ++#define ENABLE_SCALER_EXTEND_UCNR_DRIVER 0x04 ++#define ENABLE_SCALER_AUTO_DBK_DRIVER 0x80 // BK30_01_L[15] ++ ++//------------------------------------------------------------------------------------------------- ++/// this function does adaptive tuning periodic ++//------------------------------------------------------------------------------------------------- ++void MApi_XC_AdaptiveTuning(void) ++{ ++ static MS_U8 u8PreviousVcnt = 0; ++ MS_U8 u8CurrentVcnt; ++ MS_U8 u8Ctrl,ColorSum; ++ MS_U8 u8Ctrl2; ++ MS_U8 u8Ctrl3; ++ MS_U8 u8Ctrl4; ++ MS_U32 u32MotionValue,u32MotionValue2,OOSRMC,OOSRF,ISR_NONMV0,SmallMoving,VerticalMoving,HorizontalMoving,TotalFeather,TotalMvComfirm; ++ MS_U32 uComplex; ++ MS_U8 u8MotLvl,u8SDHDDReportValue; ++ XC_ApiStatus stXCStatus; ++ MS_BOOL lg107_en; ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ // ++ // Check VCnt ++ // ++ u8CurrentVcnt = MDrv_SC_read_v_cnt(); ++ if (u8PreviousVcnt == u8CurrentVcnt) ++ { ++ return; ++ } ++ else ++ { ++ u8PreviousVcnt = u8CurrentVcnt; ++ } ++ ++ // ++ // Get adaptive function control ++ // ++ u8Ctrl = MDrv_SC_get_adaptive_ctrl(); ++ u8Ctrl2 = MDrv_SC_get_adaptive_ctrl2(); ++ u8Ctrl3 = MDrv_SC_get_adaptive_ctrl3(); ++ u8Ctrl4 = MDrv_SC_get_adaptive_ctrl4(); ++ // ++ // Get motion value ++ // ++ u32MotionValue = MDrv_SC_read_motion_value1(); ++ u32MotionValue2 = MDrv_SC_read_motion_value2(); ++ ++ // ++ // Get UCDi status ++ // ++ OOSRMC = MDrv_SC_T12_UC_InSearchRange_MvComfirm(); ++ OOSRF = MDrv_SC_T12_UC_InSearchRange_Feather(); ++ ISR_NONMV0 = MDrv_SC_T12_UC_InSearchRange_nonMv0Comfirm(); ++ SmallMoving = MDrv_SC_T12_UC_SmallMoving(); ++ VerticalMoving = MDrv_SC_A5_KFC_IsVerticalMoving(); ++ ++ HorizontalMoving = MDrv_SC_A5_IsHorizontalMoving(); ++ TotalFeather = MDrv_SC_A5_TotalFeather(); ++ TotalMvComfirm = MDrv_SC_A5_TotalMvComfirm(); ++ ColorSum = (MS_U8)MDrv_SC_A5_ColorPixelSum(); ++ uComplex = MDrv_SC_A5_ComplexSum(); ++ ++ //printf("===VerticalMoving==%x=\n",VerticalMoving); ++ //printf("===HorizontalMoving==%x=\n",HorizontalMoving); ++ //printf("===u32MotionValue==%x=\n",u32MotionValue); ++ //printf("===OOSRF==%x=\n",OOSRF); ++ //printf("===ISR_NONMV0==%x=\n",ISR_NONMV0); ++ // ++ // Adaptive functions ++ // ++ ++ if(_u16PQPre_SrcType != _u16PQSrcType_DBK_Detect[PQ_MAIN_WINDOW]) //For Auto_DBK SW driver used ++ { ++ _u16PQPre_SrcType = _u16PQSrcType_DBK_Detect[PQ_MAIN_WINDOW]; ++ data_read = true; ++ } ++ ++ ++ if (u8Ctrl3 & ENABLE_SCALER_AUTO_DBK_DRIVER) //New Add for AUTO DBK Test ++ { ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ u8SDHDDReportValue = MDrv_SC_NEW_SDHD_DETECT_report(); // W/O Feather detect ++ MDrv_SC_Auto_Detect_Blocking_Width_driver(u8SDHDDReportValue); // Auto_Detect_Blocking_Width ++ } ++ ++ if(u8Ctrl4 & ENABLE_SCALER_EXTEND_UCDI_DRIVER) ++ { ++ ++ } ++ else ++ { ++ // ++ // T12 UCDi function ++ // ++ if (u8Ctrl2 & ENABLE_SCALER_T12_UCDI_DRIVER) ++ { ++ //u8MotLvl = MDrv_SC_motion_level(u32MotionValue); ++ //MDrv_SC_T12_UCDi_OP1_HisWeight(u8MotLvl); ++ MDrv_SC_T12_UCDi_FeatherValueGain(OOSRMC, OOSRF, ISR_NONMV0); ++ //MDrv_SC_T12_DIPF_TemporalGainControl(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_VerticalMovingUdRatio(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_ComplexOffset(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_W2SadGain(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_KFC_8bitMotionGain(SmallMoving); ++ MDrv_SC_T12_UCDi_EODiWGain(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_HistoryRatio(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_A5_UCDi_OP1_HisWeight(u32MotionValue2); ++ MDrv_SC_A5_KFC_EODiW(VerticalMoving); ++ lg107_en = MDrv_SC_A5_LG107(VerticalMoving, HorizontalMoving, TotalFeather, TotalMvComfirm,ColorSum,u32MotionValue, uComplex); ++ MDrv_SC_A5_SonyChurch(VerticalMoving, HorizontalMoving, u32MotionValue, lg107_en ); ++ } ++ else ++ { ++ if (u8Ctrl2 & ENABLE_SCALER_MCDI_DRIVER) ++ { ++ MDrv_SC_mcdi_driver(u32MotionValue2); ++ } ++ else ++ { ++ u8MotLvl = MDrv_SC_motion_level(u32MotionValue); ++ MDrv_SC_mcdi_driver_new(u32MotionValue2, u8MotLvl); ++ } ++ ++ } ++ } ++ ++ if(u8Ctrl4 & ENABLE_SCALER_EXTEND_UCNR_DRIVER) ++ { ++ MDrv_SC_Extend_UCNR_driver(); ++ } ++ else ++ { ++ if (u8Ctrl2 & ENABLE_SCALER_MCNR_DRIVER) ++ { ++ MDrv_SC_mcnr_driver(); ++ } ++ } ++ if (u8Ctrl2 & ENABLE_SCALER_SDHD_DETECT_DRIVER) ++ { ++ MDrv_SC_SDHD_DETECT_driver(); ++ } ++ ++ if (u8Ctrl2 & ENABLE_SCALER_NEW_SDHD_DETECT_DRIVER) ++ { ++ MDrv_SC_NEW_SDHD_DETECT_driver(); ++ } ++ ++ if(u8Ctrl4 & ENABLE_SCALER_NEW_FILM_DRIVER) ++ { ++ ++ } ++ else ++ { ++ if (u8Ctrl2 & ENABLE_SCALER_FILM_DRIVER) ++ { ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ MDrv_SC_film_driver(stXCStatus.u16H_SizeAfterPreScaling); ++ } ++ else ++ { ++ MDrv_SC_dynamic_film_mode(); // for T2 and before ++ } ++ } ++ ++ if (u8Ctrl2 & ENABLE_SCALER_JANUS_DHD_DRIVER) ++ { ++ MDrv_SC_Janus_DHD_driver(); ++ } ++ ++ if (u8Ctrl2 & ENABLE_SCALER_HISDNR_DRIVER) ++ { ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ MDrv_SC_HISNR_driver(stXCStatus.stCropWin.width, stXCStatus.stCropWin.height); ++ } ++// else ++// { ++//dnr_md_high_thrd_level_iir=0; ++//dnr_md_low_thrd_level_iir=0; ++// } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEFEATHERING) ++ { ++ MDrv_SC_de_feathering(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEFLICKERING) ++ { ++ MDrv_SC_de_flickering(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEBOUNCING) ++ { ++ MDrv_SC_de_bouncing(u32MotionValue2); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DYNAMIC_SNR) ++ { ++ MDrv_SC_dynamic_snr(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DYNAMIC_DNR) ++ { ++ MDrv_SC_dynamic_dnr(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEPRESNR) ++ { ++ MDrv_SC_de_pre_snr(u32MotionValue2); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_FANTASTICDNR) ++ { ++ MDrv_SC_fantastic_dnr(); ++ } ++} ++ ++#endif //#ifdef UTOPIA ++ ++#undef DRV_SCALER_ADAPTIVE_C +diff --git a/drivers/mstar/scl/infinity3/Makefile b/drivers/mstar/scl/infinity3/Makefile +new file mode 100644 +index 00000000..5d05724a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/Makefile +@@ -0,0 +1,97 @@ ++MS_ARCH_NAME=infinity3 ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/infinity3 ++ ++# ++# Makefile for MStar HVSP drivers. ++# ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/inc ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/inc ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/msos ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip ++ ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/cmdq ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/cmdq ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/pnl/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/pnl ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/pnl/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/pnl ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/sclirq/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/sclirq ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/sclirq/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/sclirq ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/vip/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/vip ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/vip ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/hvsp/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/hvsp ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/hvsp/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/hvsp ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/scldma/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/drv/scldma ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/scldma/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/hal/scldma ++ ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/hal/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/hal/include ++EXTRA_CFLAGS += -Idrivers/mstar/scl/$(MS_ARCH_NAME)/src/mxlib/pq/hal/include/sc ++ ++EXTRA_CFLAGS += -Werror ++ ++# specific options ++# ++EXTRA_CFLAGS += -DMSOS_TYPE_LINUX_KERNEL ++ ++ccflags-$(CONFIG_ARCH_CEDRIC) += -DC3_SIM ++ ++ ++obj-$(CONFIG_MS_SCL_INFINITY3) += mdrv_scl.o ++ ++mdrv_scl-y := src/mxlib/msos/MsOS.o\ ++ src/mdrv_multiinst.o \ ++ mdrv_hvsp1_io.o\ ++ mdrv_hvsp2_io.o\ ++ mdrv_hvsp3_io.o\ ++ src/mdrv_hvsp.o\ ++ src/mxlib/hal/hvsp/halhvsp.o\ ++ src/mxlib/drv/hvsp/drvhvsp.o\ ++ mdrv_scldma1_io.o\ ++ mdrv_scldma2_io.o\ ++ mdrv_scldma3_io.o\ ++ mdrv_scldma4_io.o\ ++ src/mdrv_scldma.o\ ++ src/mxlib/hal/sclirq/halsclirq.o\ ++ src/mxlib/drv/sclirq/drvsclirq.o\ ++ src/mxlib/hal/scldma/halscldma.o\ ++ src/mxlib/drv/scldma/drvscldma.o\ ++ mdrv_pnl_io.o\ ++ src/mdrv_pnl.o\ ++ src/mxlib/hal/pnl/halpnl.o\ ++ src/mxlib/drv/pnl/drvpnl.o\ ++ mdrv_vip_io.o\ ++ src/mdrv_vip.o\ ++ src/mxlib/hal/vip/halvip.o\ ++ src/mxlib/drv/vip/drvvip.o\ ++ src/mxlib/drv/cmdq/drvCMDQ.o\ ++ src/mxlib/hal/cmdq/halCMDQ.o\ ++ src/mxlib/pq/drvPQ.o\ ++ src/mxlib/pq/drvPQ_Bin.o\ ++ src/mxlib/pq/hal/mhal_pq.o\ ++ src/mxlib/pq/hal/QualityMap_Main.o\ +diff --git a/drivers/mstar/scl/infinity3/inc/mdrv_hvsp.h b/drivers/mstar/scl/infinity3/inc/mdrv_hvsp.h +new file mode 100644 +index 00000000..4784d656 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/inc/mdrv_hvsp.h +@@ -0,0 +1,308 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MDRV_HVSP_H ++#define _MDRV_HVSP_H ++ ++ ++ ++#define MDRV_HVSP_CROP_NUM 2 ++#define DNRBufferMode 1 // depend on DNR Buffer ++#define IPMPATH ++#define PriMaskNum 10 ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_MDRV_HVSP_ID_1, ++ E_MDRV_HVSP_ID_2, ++ E_MDRV_HVSP_ID_3, ++ E_MDRV_HVSP_ID_MAX, //I1 has 3 HVSP ++}EN_MDRV_HVSP_ID_TYPE; ++typedef enum ++{ ++ E_MDRV_HVSP_SRC_ISP, ///< input source: ISP ++ E_MDRV_HVSP_SRC_BT656, ///< input source: BT656 ++ E_MDRV_HVSP_SRC_DRAM, ///< input source: DRAM ++ E_MDRV_HVSP_SRC_HVSP, ///< input source: HVSP1 ++ E_MDRV_HVSP_SRC_PAT_TGEN, ///< input source: PATGEN ++ E_MDRV_HVSP_SRC_NUM, ///< The max number of input source ++}EN_MDRV_HVSP_SRC_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_COLOR_RGB, ///< color format:RGB ++ E_MDRV_HVSP_COLOR_YUV444, ///< color format:YUV444 ++ E_MDRV_HVSP_COLOR_YUV422, ///< color format:YUV422 ++ E_MDRV_HVSP_COLOR_YUV420, ///< color format:YUV420 ++ E_MDRV_HVSP_COLOR_NUM, ///< The max number of color format ++}EN_MDRV_HVSP_COLOR_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_MCNR_YCM_R = 0x1, ///< IP only read ++ E_MDRV_HVSP_MCNR_YCM_W = 0x2, ///< IP only write ++ E_MDRV_HVSP_MCNR_YCM_RW = 0x3, ///< IP R/W ++ E_MDRV_HVSP_MCNR_CIIR_R = 0x4, ///< IP only read ++ E_MDRV_HVSP_MCNR_CIIR_W = 0x8, ///< IP only write ++ E_MDRV_HVSP_MCNR_CIIR_RW = 0xC, ///< IP R/W ++ E_MDRV_HVSP_MCNR_NON = 0x10, ///< IP none open ++}EN_MDRV_HVSP_MCNR_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_IPMPATH_R = 0x1, ///< IP only read ++ E_MDRV_HVSP_IPMPATH_W = 0x2, ///< IP only write ++ E_MDRV_HVSP_IPMPATH_RW = 0x3, ///< IP R/W ++ E_MDRV_HVSP_IPMPATH_NON = 0x10, ///< IP none open ++}EN_MDRV_HVSP_IPMPATH_TYPE; ++ ++ ++typedef enum ++{ ++ E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30, // FHD PT GEN ++ E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60, // HD PT gEN ++ E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60, // SD PT GEN ++ E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED, // random size ++ E_MDRV_HVSP_PAT_TGEN_TIMING_MAX, // 4type ++}EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE; ++ ++typedef enum ++{ ++ E_MDRV_HVSP_MISC_CMD_SET_REG = 0, ++ ++ E_MDRV_HVSP_MISC_CMD_MAX, // MISC set 1 type ++}EN_MDRV_HVSP_MISC_CMD_TYPE; ++ ++typedef enum ++{ ++ EN_MDRV_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ EN_MDRV_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_MDRV_HVSP_OSD_LOC_TYPE; ++ ++typedef enum ++{ ++ EN_MDRV_HVSP_MONITOR_CROPCHECK = 1, ///< crop ++ EN_MDRV_HVSP_MONITOR_DMA1FRMCHECK = 2, ///< dma1frm ++ EN_MDRV_HVSP_MONITOR_DMA1SNPCHECK = 3, ///< dma1frm ++ EN_MDRV_HVSP_MONITOR_DMA2FRMCHECK = 4, ///< dma1frm ++ EN_MDRV_HVSP_MONITOR_DMA3FRMCHECK = 5, ///< dma1frm ++}EN_MDRV_HVSP_MONITOR_TYPE; ++ ++typedef enum ++{ ++ EN_MDRV_HVSP_CALLPATGEN_STATIC = 0, ///< crop ++ EN_MDRV_HVSP_CALLPATGEN_DYNAMIC = 1, ///< dma1frm ++}EN_MDRV_HVSP_CALLPATGEN_TYPE; ++typedef enum ++{ ++ EN_MDRV_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_MDRV_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_MDRV_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_MDRV_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_MDRV_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_MDRV_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_MDRV_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_MDRV_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_MDRV_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++ EN_MDRV_HVSP_FBMG_SET_PRVCROP_ON = 0x1000, ++ EN_MDRV_HVSP_FBMG_SET_PRVCROP_OFF = 0x2000, ++ EN_MDRV_HVSP_FBMG_SET_CIIR_ON = 0x4000, ++ EN_MDRV_HVSP_FBMG_SET_CIIR_OFF = 0x8000, ++ EN_MDRV_HVSP_FBMG_SET_LOCK = 0x10000, ++}EN_MDRV_HVSP_FBMG_SET_TYPE; ++typedef struct ++{ ++ unsigned short u16X; ///< crop frame start x point ++ unsigned short u16Y; ///< crop frame start y point ++ unsigned short u16Width; ///< crop width size ++ unsigned short u16Height; ///< crop height size ++}ST_MDRV_HVSP_WINDOW_CONFIG; ++typedef struct ++{ ++ unsigned char bInterlace; ///< is interlace or progressive ++ unsigned short u16Htotal; ///< Htt ++ unsigned short u16Vtotal; ///< Vtt ++ unsigned short u16Vfrequency; ///< Vfreq ++}ST_MDRV_HVSPTIMING_CONFIG; ++ ++typedef struct ++{ ++ unsigned long u32Riubase; ++ unsigned long u32IRQNUM;//scl ++ unsigned long u32CMDQIRQNUM;//cmdq ++}ST_MDRV_HVSP_INIT_CONFIG; ++ ++ ++typedef struct ++{ ++ unsigned long u32IRQNum; ++ unsigned long u32CMDQIRQNum;//cmdq ++}ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG; ++ ++typedef struct ++{ ++ EN_MDRV_HVSP_MCNR_TYPE enRW; ++ unsigned long u32YCPhyAddr; ++ unsigned long u32MPhyAddr; ++ unsigned long u32CIIRPhyAddr; ++ unsigned short u16Width; ++ unsigned short u16Height; ++ unsigned long u32MemSize; ++}ST_MDRV_HVSP_IPM_CONFIG; ++ ++typedef struct ++{ ++ unsigned char bEn; ++ unsigned short u16X; ++ unsigned short u16Y; ++ unsigned short u16Width; ++ unsigned short u16Height; ++}ST_MDRV_HVSP_CROP_WINDOW_CONFIG; ++typedef struct ++{ ++ void* idclk; ++ void* fclk1; ++ void* fclk2; ++ void* odclk; ++}ST_MDRV_HVSP_CLK_CONFIG; ++ ++typedef struct ++{ ++ unsigned short u16Src_Width; ++ unsigned short u16Src_Height; ++ unsigned short u16Dsp_Width; ++ unsigned short u16Dsp_Height; ++ ST_MDRV_HVSP_CROP_WINDOW_CONFIG stCropWin; ++ ST_MDRV_HVSP_CLK_CONFIG *stclk; ///< clk framework ++}ST_MDRV_HVSP_SCALING_CONFIG; ++ ++typedef struct ++{ ++ unsigned char bOSDEn; ///< OSD en ++ unsigned char bOSDBypass; ///< OSD en ++ unsigned char bWTMBypass; ///< OSD en ++}ST_MDRV_HVSP_OSD_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ EN_MDRV_HVSP_OSD_LOC_TYPE enOSD_loc; ///< OSD locate ++ ST_MDRV_HVSP_OSD_ONOFF_CONFIG stOsdOnOff; ++}ST_MDRV_HVSP_OSD_CONFIG; ++typedef struct ++{ ++ unsigned char bMask; /// ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++#include "ms_msys.h" ++#include "mdrv_hvsp_io_i3_st.h" ++#include "mdrv_hvsp_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++#define MDRV_MS_HVSP_DEVICE_COUNT 1 ++#define MDRV_MS_HVSP_NAME "mhvsp1" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_HVSP "mhvsp1" ++#define MDRV_MAJOR_HVSP 0xea ++#define MDRV_MINOR_HVSP 0x01 ++ ++#define CMD_PARSING(x) (x==IOCTL_HVSP_SET_IN_CONFIG ? "IOCTL_HVSP_SET_IN_CONFIG" : \ ++ x==IOCTL_HVSP_SET_OUT_CONFIG ? "IOCTL_HVSP_SET_OUT_CONFIG" : \ ++ x==IOCTL_HVSP_SET_SCALING_CONFIG ? "IOCTL_HVSP_SET_SCALING_CONFIG" : \ ++ x==IOCTL_HVSP_REQ_MEM_CONFIG ? "IOCTL_HVSP_REQ_MEM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_MISC_CONFIG ? "IOCTL_HVSP_SET_MISC_CONFIG" : \ ++ x==IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ? "IOCTL_HVSP_GET_PRIVATE_ID_CONFIG" : \ ++ x==IOCTL_HVSP_GET_INFORM_CONFIG ? "IOCTL_HVSP_GET_INFORM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_PRIMASK_CONFIG ? "IOCTL_HVSP_SET_PRIMASK_CONFIG" : \ ++ x==IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG ? "IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG" : \ ++ "UNKNOWN") ++ ++#define FHDWidth 1920 ++#define FHDHeight 1080 ++#define _3MWidth 2048 ++#define _3MHeight 1536 ++//------------------------------------------------------------------------------------------------- ++ ++#define _ms_hvsp1_mem_bus_to_miu(x) (x-0x2000000) ++#define CMDQIRQ_ID ++#define SCLIRQ_ID ++#define CIIROPEN gbCIIR ++//------------------------------------------------------------------------------------------------- ++ ++int mdrv_ms_hvsp1_open(struct inode *inode, struct file *filp); ++int mdrv_ms_hvsp1_release(struct inode *inode, struct file *filp); ++long mdrv_ms_hvsp1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_hvsp1_probe(struct platform_device *pdev); ++static int mdrv_ms_hvsp1_remove(struct platform_device *pdev); ++static int mdrv_ms_hvsp1_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_hvsp1_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_hvsp1_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//------------------------------------------------------------------------------------------------- ++static u_long sg_hvsp1_mcnr_size = 1920*1080*2*2 ; ++dma_addr_t sg_hvsp1_mcnr_yc_bus_addr = 0; ++static void *sg_hvsp1_mcnr_yc_vir_addr = NULL; ++const static char* KEY_DMEM_SCL_MCNR_YC="SCL_MCNR_YC"; ++dma_addr_t sg_hvsp1_mcnr_ciir_bus_addr = 0; ++static void *sg_hvsp1_mcnr_ciir_vir_addr = NULL; ++const static char* KEY_DMEM_SCL_MCNR_CIIR="SCL_MCNR_CIIR"; ++dma_addr_t sg_hvsp1_mcnr_m_bus_addr = 0; ++static void *sg_hvsp1_mcnr_m_vir_addr = NULL; ++const static char* KEY_DMEM_SCL_MCNR_M="SCL_MCNR_M"; ++unsigned int gu8FrameBufferReadyNum=0;//extern ++unsigned char gbdbgmessage[EN_DBGMG_NUM_CONFIG];//extern ++#if CONFIG_OF ++unsigned int gbProbeAlready = 0;//extern ++#endif ++dma_addr_t sg_hvsp1_release_mcnr_size; ++unsigned char gbCIIR; ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ unsigned char flag; ++ struct task_struct *pThread; ++}ST_IOCTL_HVSP_THREAD_CONFIG; ++ST_IOCTL_HVSP_THREAD_CONFIG gstThCfg={0,NULL}; ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_HVSP_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_HVSP; ++ ++static ST_DEV_HVSP _dev_ms_hvsp1 = ++{ ++ .s32Major = MDRV_MAJOR_HVSP, ++ .s32Minor = MDRV_MINOR_HVSP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_HVSP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_hvsp1_open, ++ .release = mdrv_ms_hvsp1_release, ++ .unlocked_ioctl = mdrv_ms_hvsp1_ioctl, ++ .poll = mdrv_ms_hvsp1_poll, ++ }, ++}; ++ ++static struct class * m_hvsp1_class = NULL; ++static char * hvsp1_classname = "m_hvsp1_class"; ++ ++ ++static const struct of_device_id ms_hvsp1_of_match_table[] = ++{ ++ { .compatible = "mstar,hvsp1" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_hvsp1_driver = ++{ ++ .probe = mdrv_ms_hvsp1_probe, ++ .remove = mdrv_ms_hvsp1_remove, ++ .suspend = mdrv_ms_hvsp1_suspend, ++ .resume = mdrv_ms_hvsp1_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_HVSP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_hvsp1_of_match_table), ++ }, ++}; ++ ++static u64 ms_hvsp1_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_hvsp1_device = ++{ ++ .name = "mhvsp1", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_hvsp1_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++MS_U8 gu8first; ++ ++//------------------------------------------------------------------------------------------------- ++// internal function ++//------------------------------------------------------------------------------------------------- ++void _mdrv_hvsp1_SetInputTestPatternAndTgen(unsigned short Width,unsigned short Height) ++{ ++ ST_MDRV_HVSP_MISC_CONFIG stHvspMiscCfg; ++ unsigned char u8InputTgenSetBuf[] = ++ { ++ 0x18, 0x12, 0x80, 0x07, 0xFF,// 4 ++ 0x18, 0x12, 0x81, 0x80, 0xFF,// 9 ++ 0x18, 0x12, 0x82, 0x30, 0xFF, ++ 0x18, 0x12, 0x83, 0x30, 0xFF, ++ 0x18, 0x12, 0x84, 0x10, 0xFF, ++ 0x18, 0x12, 0x85, 0x10, 0xFF, ++ 0x18, 0x12, 0x86, 0x02, 0xFF, ++ 0x18, 0x12, 0x87, 0x00, 0xFF, ++ 0x18, 0x12, 0x88, 0x21, 0xFF, ++ 0x18, 0x12, 0x89, 0x0C, 0xFF, ++ 0x18, 0x12, 0xE0, 0x01, 0xFF, ++ 0x18, 0x12, 0xE1, 0x00, 0xFF, ++ 0x18, 0x12, 0xE2, 0x01, 0xFF, ++ 0x18, 0x12, 0xE3, 0x00, 0xFF, ++ 0x18, 0x12, 0xE4, 0x03, 0xFF, ++ 0x18, 0x12, 0xE5, 0x00, 0xFF, ++ 0x18, 0x12, 0xE6, 0x05, 0xFF, ++ 0x18, 0x12, 0xE7, 0x00, 0xFF, ++ 0x18, 0x12, 0xE8, 0xE4, 0xFF,//94 ++ 0x18, 0x12, 0xE9, 0x01, 0xFF,//99 ++ 0x18, 0x12, 0xEA, 0x05, 0xFF, ++ 0x18, 0x12, 0xEB, 0x00, 0xFF, ++ 0x18, 0x12, 0xEC, 0xE4, 0xFF,//114 ++ 0x18, 0x12, 0xED, 0x01, 0xFF,//119 ++ 0x18, 0x12, 0xEE, 0x72, 0xFF,//124 ++ 0x18, 0x12, 0xEF, 0x02, 0xFF,//129 ++ 0x18, 0x12, 0xF2, 0x04, 0xFF, ++ 0x18, 0x12, 0xF3, 0x00, 0xFF, ++ 0x18, 0x12, 0xF4, 0x7F, 0xFF, ++ 0x18, 0x12, 0xF5, 0x00, 0xFF, ++ 0x18, 0x12, 0xF6, 0xA8, 0xFF, ++ 0x18, 0x12, 0xF7, 0x00, 0xFF, ++ 0x18, 0x12, 0xF8, 0xA7, 0xFF,//164 ++ 0x18, 0x12, 0xF9, 0x01, 0xFF,//169 ++ 0x18, 0x12, 0xFA, 0xA8, 0xFF, ++ 0x18, 0x12, 0xFB, 0x00, 0xFF, ++ 0x18, 0x12, 0xFC, 0xA7, 0xFF,//184 ++ 0x18, 0x12, 0xFD, 0x01, 0xFF,//189 ++ 0x18, 0x12, 0xFE, 0x1F, 0xFF,//194 ++ 0x18, 0x12, 0xFF, 0x04, 0xFF,//199 ++ 0x21, 0x12, 0xE0, 0x01, 0x01,//vip ++ 0x1E, 0x12, 0x70, 0x00, 0xFF, ++ 0x1E, 0x12, 0x71, 0x04, 0x07, ++ 0x1E, 0x12, 0x72, 0x00, 0xFF, ++ 0x1E, 0x12, 0x73, 0x00, 0x01, ++ 0x1E, 0x12, 0x74, 0x00, 0xFF, ++ 0x1E, 0x12, 0x75, 0x04, 0x07, ++ 0x1E, 0x12, 0x76, 0x00, 0xFF, ++ 0x1E, 0x12, 0x77, 0x00, 0x01, ++ 0x1E, 0x12, 0x78, 0x00, 0xFF, ++ 0x1E, 0x12, 0x79, 0x04, 0x07, ++ 0x1E, 0x12, 0x7A, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7B, 0x00, 0x01, ++ 0x1E, 0x12, 0x7C, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7D, 0x04, 0x07, ++ 0x1E, 0x12, 0x7E, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7F, 0x00, 0x01, ++ }; ++ ++ // Input tgen setting ++ u8InputTgenSetBuf[93] = (unsigned char)((0x4+Height)&0x00FF); ++ u8InputTgenSetBuf[98] = (unsigned char)(((0x4+Height)&0xFF00)>>8); ++ u8InputTgenSetBuf[113] = (unsigned char)((0x4+Height)&0x00FF); ++ u8InputTgenSetBuf[118] = (unsigned char)(((0x4+Height)&0xFF00)>>8); ++ u8InputTgenSetBuf[123] = 0xFF; ++ u8InputTgenSetBuf[128] = 0x08; ++ u8InputTgenSetBuf[163] = (unsigned char)((0xA7+Width)&0x00FF); ++ u8InputTgenSetBuf[168] = (unsigned char)(((0xA7+Width)&0xFF00)>>8); ++ u8InputTgenSetBuf[183] = (unsigned char)((0xA7+Width)&0x00FF); ++ u8InputTgenSetBuf[188] = (unsigned char)(((0xA7+Width)&0xFF00)>>8); ++ u8InputTgenSetBuf[193] = 0xFF; ++ u8InputTgenSetBuf[198] = 0x08; ++ ++ stHvspMiscCfg.u8Cmd = 0; ++ stHvspMiscCfg.u32Size = sizeof(u8InputTgenSetBuf); ++ stHvspMiscCfg.u32Addr = (unsigned long)u8InputTgenSetBuf; ++ MDrv_HVSP_SetMiscConfigForKernel(&stHvspMiscCfg); ++} ++ ++void _mdrv_hvsp1_OpenInputTestPatternAndTgen(void) ++{ ++ ST_MDRV_HVSP_SCINFORM_CONFIG stCfg; ++ MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_1,&stCfg); ++ if(stCfg.u16crop2inWidth && stCfg.u16crop2inHeight) ++ { ++ MDrv_HVSP_SetPatTgenStatus(TRUE); ++ _mdrv_hvsp1_SetInputTestPatternAndTgen(stCfg.u16crop2inWidth,stCfg.u16crop2inHeight); ++ } ++ else ++ { ++ MDrv_HVSP_SetPatTgenStatus(TRUE); ++ _mdrv_hvsp1_SetInputTestPatternAndTgen(FHDWidth,FHDHeight); ++ SCL_ERR( "[HVSP1]Open Input Test Pattern And Tgen Default FHD\n"); ++ } ++} ++ ++void _mdrv_hvsp1_OpenTestPatternByISPTgen(unsigned char bDynamic) ++{ ++ ST_MDRV_HVSP_MISC_CONFIG stHvspMiscCfg; ++ unsigned char input_tgen_buf[] = ++ { ++ 0x18, 0x12, 0x80, 0x03, 0xFF,// 4 ++ 0x18, 0x12, 0x81, 0x80, 0xFF,// 9 ++ 0x18, 0x12, 0x82, 0x30, 0xFF, ++ 0x18, 0x12, 0x83, 0x30, 0xFF, ++ 0x18, 0x12, 0x84, 0x10, 0xFF, ++ 0x18, 0x12, 0x85, 0x10, 0xFF, ++ 0x18, 0x12, 0x86, 0x02, 0xFF, ++ 0x18, 0x12, 0x87, 0x00, 0xFF, ++ 0x18, 0x12, 0x88, 0x21, 0xFF, ++ 0x18, 0x12, 0x89, 0x0C, 0xFF, ++ 0x21, 0x12, 0xE0, 0x01, 0x01,//vip ++ 0x1E, 0x12, 0x70, 0x00, 0xFF, ++ 0x1E, 0x12, 0x71, 0x04, 0x07, ++ 0x1E, 0x12, 0x72, 0x00, 0xFF, ++ 0x1E, 0x12, 0x73, 0x00, 0x01, ++ 0x1E, 0x12, 0x74, 0x00, 0xFF, ++ 0x1E, 0x12, 0x75, 0x04, 0x07, ++ 0x1E, 0x12, 0x76, 0x00, 0xFF, ++ 0x1E, 0x12, 0x77, 0x00, 0x01, ++ 0x1E, 0x12, 0x78, 0x00, 0xFF, ++ 0x1E, 0x12, 0x79, 0x04, 0x07, ++ 0x1E, 0x12, 0x7A, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7B, 0x00, 0x01, ++ 0x1E, 0x12, 0x7C, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7D, 0x04, 0x07, ++ 0x1E, 0x12, 0x7E, 0x00, 0xFF, ++ 0x1E, 0x12, 0x7F, 0x00, 0x01, ++ }; ++ if(bDynamic) ++ { ++ input_tgen_buf[3] = (unsigned char)0x7; ++ } ++ stHvspMiscCfg.u8Cmd = 0; ++ stHvspMiscCfg.u32Size = sizeof(input_tgen_buf); ++ stHvspMiscCfg.u32Addr = (unsigned long)input_tgen_buf; ++ MDrv_HVSP_SetMiscConfigForKernel(&stHvspMiscCfg); ++ ++} ++void _mdrv_hvsp1_CloseTestPatternByISPTgen(void) ++{ ++ ST_MDRV_HVSP_MISC_CONFIG stHvspMiscCfg; ++ unsigned char input_tgen_buf[] = ++ { ++ 0x18, 0x12, 0x80, 0x00, 0xFF,// 4 ++ 0x18, 0x12, 0x81, 0x00, 0xFF,// 9 ++ 0x18, 0x12, 0x86, 0x02, 0xFF, ++ 0x18, 0x12, 0x88, 0x20, 0xFF, ++ 0x18, 0x12, 0x89, 0x0C, 0xFF, ++ 0x18, 0x12, 0xE0, 0x00, 0xFF, ++ 0x18, 0x12, 0xE1, 0x00, 0xFF, ++ 0x21, 0x12, 0xE0, 0x00, 0x01, ++ }; ++ stHvspMiscCfg.u8Cmd = 0; ++ stHvspMiscCfg.u32Size = sizeof(input_tgen_buf); ++ stHvspMiscCfg.u32Addr = (unsigned long)input_tgen_buf; ++ MDrv_HVSP_SetPatTgenStatus(FALSE); ++ MDrv_HVSP_SetMiscConfigForKernel(&stHvspMiscCfg); ++ ++} ++ ++unsigned char _mdrv_hvsp1_InputVSyncMonitor(void) ++{ ++ if(MDrv_HVSP_InputVSyncMonitor()) ++ { ++ return 1; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++static ssize_t ptgen_call_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]ptgen_call_store OK %d\n",(int)*str); ++ _mdrv_hvsp1_OpenTestPatternByISPTgen(EN_MDRV_HVSP_CALLPATGEN_STATIC); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "[HVSP1]ptgen_call_close %d\n",(int)*str); ++ _mdrv_hvsp1_CloseTestPatternByISPTgen(); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[HVSP1]dynamic ptgen OK %d\n",(int)*str); ++ _mdrv_hvsp1_OpenTestPatternByISPTgen(EN_MDRV_HVSP_CALLPATGEN_DYNAMIC); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[HVSP1]ptgen_call SCL INPUT Tgen %d\n",(int)*str); ++ _mdrv_hvsp1_OpenInputTestPatternAndTgen(); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t ptgen_call_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf,"0:close\n1:open static ptgen\n2:open dynamic ptgen\n3:open scl time gen pattern"); ++} ++ ++static DEVICE_ATTR(ptgen,0644, ptgen_call_show, ptgen_call_store); ++ ++ ++ ++static ssize_t check_clk_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ ST_MDRV_HVSP_CLK_CONFIG *stclk = NULL; ++ stclk = &(_dev_ms_hvsp1.stclk); ++ return MDrv_HVSP_ClkFrameworkShow(buf,stclk); ++} ++ ++static ssize_t check_clk_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 ++ { ++ SCL_ERR( "[CLK]open force mode %d\n",(int)*str); ++ MDrv_HVSP_SetCLKForcemode(1); ++ } ++ else if((int)*str == 48) //input 0 ++ { ++ SCL_ERR( "[CLK]close force mode %d\n",(int)*str); ++ MDrv_HVSP_SetCLKForcemode(0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[CLK]fclk1 max %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk1,0); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[CLK]fclk1 med %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk1,1); ++ } ++ else if((int)*str == 69) //input E ++ { ++ SCL_ERR( "[CLK]fclk1 216 %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk1,2); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ SCL_ERR( "[CLK]fclk1 open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk1,1); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ SCL_ERR( "[CLK]fclk1 close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk1,0); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ SCL_ERR( "[CLK]fclk2 172 %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk2,0); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ SCL_ERR( "[CLK]fclk2 86 %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk2,1); ++ } ++ else if((int)*str == 70) //input F ++ { ++ SCL_ERR( "[CLK]fclk2 216 %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.fclk2,2); ++ } ++ else if((int)*str == 56) //input 8 ++ { ++ SCL_ERR( "[CLK]fclk2 open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk2,1); ++ } ++ else if((int)*str == 57) //input 9 ++ { ++ SCL_ERR( "[CLK]fclk2 close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.fclk2,0); ++ } ++ else if((int)*str == 58) //input : ++ { ++ SCL_ERR( "[CLK]idclk ISP %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.idclk,0x10); ++ } ++ else if((int)*str == 68) //input D ++ { ++ SCL_ERR( "[CLK]idclk BT656 %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.idclk,0x21); ++ } ++ else if((int)*str == 66) //input B ++ { ++ SCL_ERR( "[CLK]idclk Open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.idclk,1); ++ } ++ else if((int)*str == 61) //input = ++ { ++ SCL_ERR( "[CLK]idclk Close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.idclk,0); ++ } ++ else if((int)*str == 67) //input C ++ { ++ SCL_ERR( "[CLK]odclk MAX %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.odclk,0); ++ } ++ else if((int)*str == 63) //input ? ++ { ++ SCL_ERR( "[CLK]odclk LPLL %d\n",(int)*str); ++ MDrv_HVSP_SetCLKRate(_dev_ms_hvsp1.stclk.odclk,3); ++ } ++ else if((int)*str == 64) //input @ ++ { ++ SCL_ERR( "[CLK]odclk open %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.odclk,1); ++ } ++ else if((int)*str == 65) //input A ++ { ++ SCL_ERR( "[CLK]odclk close %d\n",(int)*str); ++ MDrv_HVSP_SetCLKOnOff(_dev_ms_hvsp1.stclk.odclk,0); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++ ++static DEVICE_ATTR(clk,0644, check_clk_show, check_clk_store); ++static ssize_t check_osd_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ MDrv_HVSP_OsdStore(buf,E_MDRV_HVSP_ID_1); ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t check_osd_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_OsdShow(buf); ++} ++static DEVICE_ATTR(osd,0644, check_osd_show, check_osd_store); ++static ssize_t check_od_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_OdShow(buf); ++} ++static DEVICE_ATTR(od,0444, check_od_show, NULL); ++static ssize_t check_fbmg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ const char *str = buf; ++ if(NULL!=buf) ++ { ++ //if(!) ++ if((int)*str == 49) //input 1 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_LDCPATH_ON); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_LDCPATH_OFF); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_DNR_Read_ON); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_DNR_Read_OFF); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_DNR_Write_ON); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_DNR_Write_OFF); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_DNR_BUFFER_1); ++ } ++ else if((int)*str == 56) //input 8 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_DNR_BUFFER_2); ++ } ++ else if((int)*str == 57) //input 9 ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_UNLOCK); ++ } ++ else if((int)*str == 65) //input A ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_PRVCROP_ON); ++ } ++ else if((int)*str == 66) //input B ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_PRVCROP_OFF); ++ } ++ else if((int)*str == 67) //input C ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ gbCIIR = 1; ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_CIIR_ON); ++ } ++ else if((int)*str == 68) //input D ++ { ++ SCL_ERR( "[FB]Set %d\n",(int)*str); ++ gbCIIR = 0; ++ MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_CIIR_OFF); ++ } ++ ++ ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t check_fbmg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_FBMGShow(buf); ++} ++ ++static DEVICE_ATTR(fbmg,0644, check_fbmg_show, check_fbmg_store); ++ ++static ssize_t check_SCIQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ MDrv_HVSP_SCIQStore(buf,E_MDRV_HVSP_ID_1); ++ return n; ++} ++static ssize_t check_SCIQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_SCIQShow(buf,E_MDRV_HVSP_ID_1); ++} ++ ++static DEVICE_ATTR(SCIQ,0644, check_SCIQ_show, check_SCIQ_store); ++ ++static ssize_t check_proc_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_ProcShow(buf); ++} ++static DEVICE_ATTR(proc,0444, check_proc_show, NULL); ++ ++static ssize_t check_ints_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_IntsShow(buf); ++} ++static DEVICE_ATTR(ints,0444, check_ints_show, NULL); ++ ++ ++static ssize_t check_dbgmg_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_DbgmgFlagShow(buf); ++} ++static unsigned char _mdrv_hvsp1_Changebuf2hex(int u32num) ++{ ++ unsigned char u8level = 0; ++ if(u32num==10) ++ { ++ u8level = 1; ++ } ++ else if(u32num==48) ++ { ++ u8level = 0; ++ } ++ else if(u32num==49) ++ { ++ u8level = 0x1; ++ } ++ else if(u32num==50) ++ { ++ u8level = 0x2; ++ } ++ else if(u32num==51) ++ { ++ u8level = 0x3; ++ } ++ else if(u32num==52) ++ { ++ u8level = 0x4; ++ } ++ else if(u32num==53) ++ { ++ u8level = 0x5; ++ } ++ else if(u32num==54) ++ { ++ u8level = 0x6; ++ } ++ else if(u32num==55) ++ { ++ u8level = 0x7; ++ } ++ else if(u32num==56) ++ { ++ u8level = 0x8; ++ } ++ else if(u32num==57) ++ { ++ u8level = 0x9; ++ } ++ else if(u32num==65) ++ { ++ u8level = 0xa; ++ } ++ else if(u32num==66) ++ { ++ u8level = 0xb; ++ } ++ else if(u32num==67) ++ { ++ u8level = 0xc; ++ } ++ else if(u32num==68) ++ { ++ u8level = 0xd; ++ } ++ else if(u32num==69) ++ { ++ u8level = 0xe; ++ } ++ else if(u32num==70) ++ { ++ u8level = 0xf; ++ } ++ else if(u32num==97) ++ { ++ u8level = 0xa; ++ } ++ else if(u32num==98) ++ { ++ u8level = 0xb; ++ } ++ else if(u32num==99) ++ { ++ u8level = 0xc; ++ } ++ else if(u32num==100) ++ { ++ u8level = 0xd; ++ } ++ else if(u32num==101) ++ { ++ u8level = 0xe; ++ } ++ else if(u32num==102) ++ { ++ u8level = 0xf; ++ } ++ return u8level; ++} ++ ++static ssize_t check_dbgmg_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ unsigned char u8level; ++ SCL_ERR( "[HVSP1]check_dbgmg_store OK %d\n",(int)*str); ++ SCL_ERR( "[HVSP1]check_dbgmg_store level %d\n",(int)*(str+1)); ++ SCL_ERR( "[HVSP1]check_dbgmg_store level2 %d\n",(int)*(str+2)); ++ if(((int)*(str+2))>=48)//LF :line feed ++ { ++ u8level = _mdrv_hvsp1_Changebuf2hex((int)*(str+2)); ++ u8level |= (_mdrv_hvsp1_Changebuf2hex((int)*(str+1))<<4); ++ } ++ else ++ { ++ u8level = _mdrv_hvsp1_Changebuf2hex((int)*(str+1)); ++ } ++ ++ if((int)*str == 48) //input 1 echo 0 > ++ { ++ Reset_DBGMG_FLAG(); ++ } ++ else if((int)*str == 49) //input 1 echo 1 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_MDRV_CONFIG,u8level); ++ } ++ else if((int)*str == 50) //input 1 echo 2 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_IOCTL_CONFIG,u8level); ++ } ++ else if((int)*str == 51) //input 1 echo 3 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_HVSP_CONFIG,u8level); ++ } ++ else if((int)*str == 52) //input 1 echo 4 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_SCLDMA_CONFIG,u8level); ++ } ++ else if((int)*str == 53) //input 1 echo 5 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_PNL_CONFIG,u8level); ++ } ++ else if((int)*str == 54) //input 1 echo 6 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_VIP_CONFIG,u8level); ++ } ++ else if((int)*str == 55) //input 1 echo 7 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVPQ_CONFIG,u8level); ++ } ++ else if((int)*str == 56) //input 1 echo 8 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_INST_ENTRY_CONFIG,u8level); ++ } ++ else if((int)*str == 57) //input 1 echo 9 > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_INST_LOCK_CONFIG,u8level); ++ } ++ else if((int)*str == 65) //input 1 echo A > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_INST_FUNC_CONFIG,u8level); ++ } ++ else if((int)*str == 66) //input 1 echo B > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVHVSP_CONFIG,u8level); ++ } ++ else if((int)*str == 67) //input 1 echo C > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVSCLDMA_CONFIG,u8level); ++ } ++ else if((int)*str == 68) //input 1 echo D > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVSCLIRQ_CONFIG,u8level); ++ } ++ else if((int)*str == 69) //input 1 echo E > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVCMDQ_CONFIG,u8level); ++ } ++ else if((int)*str == 70) //input 1 echo F > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_DRVVIP_CONFIG,u8level); ++ } ++ else if((int)*str == 71) //input 1 echo G > ++ { ++ Set_DBGMG_FLAG(EN_DBGMG_PRIORITY_CONFIG,1); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(dbgmg,0644, check_dbgmg_show, check_dbgmg_store); ++static ssize_t check_lock_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_LockShow(buf); ++} ++static ssize_t check_lock_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 76) //input 1 echo L > ++ { ++ if(!MsOS_ReleaseMutexAll()) ++ { ++ SCL_DBGERR("[HVSP]!!!!!!!!!!!!!!!!!!! HVSP Release Mutex fail\n"); ++ } ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(mutex,0644, check_lock_show, check_lock_store); ++ ++static void* _ms_hvsp1_AllocDmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ if(0 != msys_request_dmem(&dmem)) ++ { ++ return NULL; ++ } ++ else ++ { ++ gu8FrameBufferReadyNum = (Mdrv_HVSP_GetFrameBufferCountInformation()); ++ sg_hvsp1_release_mcnr_size = sg_hvsp1_mcnr_size; ++ } ++ *addr = dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void _ms_hvsp1_FreeDmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ dmem.kvirt = (unsigned long long)((uintptr_t)virt); ++ dmem.phys = (unsigned long long)((uintptr_t)addr); ++ msys_release_dmem(&dmem); ++} ++ ++void _ms_hvsp1_mem_freeYCbuffer(void) ++{ ++ if(sg_hvsp1_mcnr_yc_vir_addr != 0) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, "[HVSP1] YC free\n"); ++ _ms_hvsp1_FreeDmem(KEY_DMEM_SCL_MCNR_YC, ++ PAGE_ALIGN(sg_hvsp1_mcnr_size), ++ sg_hvsp1_mcnr_yc_vir_addr, ++ sg_hvsp1_mcnr_yc_bus_addr); ++ ++ sg_hvsp1_mcnr_yc_vir_addr = 0; ++ sg_hvsp1_mcnr_yc_bus_addr = 0; ++ gu8FrameBufferReadyNum = 0; ++ } ++} ++void _ms_hvsp1_mem_freeMbuffer(void) ++{ ++ if(sg_hvsp1_mcnr_m_vir_addr != 0) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, "[HVSP1] Motion free\n"); ++ _ms_hvsp1_FreeDmem(KEY_DMEM_SCL_MCNR_M, ++ PAGE_ALIGN(sg_hvsp1_mcnr_size/4), ++ sg_hvsp1_mcnr_m_vir_addr, ++ sg_hvsp1_mcnr_m_bus_addr); ++ ++ sg_hvsp1_mcnr_m_vir_addr = 0; ++ sg_hvsp1_mcnr_m_bus_addr = 0; ++ } ++} ++void _ms_hvsp1_mem_freeCIIRbuffer(void) ++{ ++ if(sg_hvsp1_mcnr_ciir_vir_addr != 0) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, "[HVSP1] CIIR free\n"); ++ _ms_hvsp1_FreeDmem(KEY_DMEM_SCL_MCNR_CIIR, ++ PAGE_ALIGN(sg_hvsp1_mcnr_size/2), ++ sg_hvsp1_mcnr_ciir_vir_addr, ++ sg_hvsp1_mcnr_ciir_bus_addr); ++ ++ sg_hvsp1_mcnr_ciir_vir_addr = 0; ++ sg_hvsp1_mcnr_ciir_bus_addr = 0; ++ } ++} ++ ++static int _ms_hvsp1_mem_allocate(void) ++{ ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, "[HVSP1] allocate memory\n"); ++ ++ if (!(sg_hvsp1_mcnr_yc_vir_addr = _ms_hvsp1_AllocDmem(KEY_DMEM_SCL_MCNR_YC, ++ PAGE_ALIGN(sg_hvsp1_mcnr_size), ++ &sg_hvsp1_mcnr_yc_bus_addr))) ++ { ++ SCL_ERR( "%s: unable to allocate YC memory\n", __FUNCTION__); ++ return 0; ++ } ++ if (!(sg_hvsp1_mcnr_m_vir_addr = _ms_hvsp1_AllocDmem(KEY_DMEM_SCL_MCNR_M, ++ PAGE_ALIGN(sg_hvsp1_mcnr_size/4), ++ &sg_hvsp1_mcnr_m_bus_addr))) ++ { ++ SCL_ERR( "%s: unable to allocate Montion memory\n", __FUNCTION__); ++ _ms_hvsp1_mem_freeYCbuffer(); ++ return 0; ++ } ++ if(CIIROPEN) ++ { ++ if (!(sg_hvsp1_mcnr_ciir_vir_addr = _ms_hvsp1_AllocDmem(KEY_DMEM_SCL_MCNR_CIIR, ++ PAGE_ALIGN(sg_hvsp1_mcnr_size/2), ++ &sg_hvsp1_mcnr_ciir_bus_addr))) ++ { ++ SCL_ERR( "%s: unable to allocate CIIR memory\n", __FUNCTION__); ++ return 0; ++ } ++ else ++ { ++ gu8FrameBufferReadyNum |= (Mdrv_HVSP_GetFrameBufferCountInformation()<<2); ++ } ++ } ++ ++ SCL_ERR( "[HVSP1]: MCNR YC: Phy:%x Vir:%x\n", sg_hvsp1_mcnr_yc_bus_addr, (u32)sg_hvsp1_mcnr_yc_vir_addr); ++ SCL_ERR( "[HVSP1]: MCNR CIIR: Phy:%x Vir:%x\n", sg_hvsp1_mcnr_ciir_bus_addr, (u32)sg_hvsp1_mcnr_ciir_vir_addr); ++ SCL_ERR( "[HVSP1]: MCNR M: Phy:%x Vir:%x\n", sg_hvsp1_mcnr_m_bus_addr, (u32)sg_hvsp1_mcnr_m_vir_addr); ++ return 1; ++} ++ ++static void _ms_hvsp1_mem_free(void) ++{ ++ _ms_hvsp1_mem_freeYCbuffer(); ++ _ms_hvsp1_mem_freeMbuffer(); ++ _ms_hvsp1_mem_freeCIIRbuffer(); ++} ++static int _ms_hvsp1_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++void _mdrv_ms_hvsp1_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_HVSP_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_hvsp1_io_version_check(ST_MDRV_HVSP_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP1] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[HVSP1] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[HVSP1] Size(%d) \n",stVersion->u32StructSize ); ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP1] No Header !!! \n"); ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++MS_BOOL _mdrv_hvsp1_CheckModifyMemSize(ST_IOCTL_HVSP_REQ_MEM_CONFIG *stReqMemCfg) ++{ ++ if( (stReqMemCfg->u16Vsize & (15)) || (stReqMemCfg->u16Pitch & (15))) ++ { ++ SCL_ERR( ++ "[HVSP1] Size must be align 16, Vsize=%d, Pitch=%d\n",stReqMemCfg->u16Vsize, stReqMemCfg->u16Pitch); ++ if((stReqMemCfg->u16Pitch & (15))&&(stReqMemCfg->u16Vsize & (15))) ++ { ++ stReqMemCfg->u32MemSize = (((stReqMemCfg->u16Vsize/16)+1)*16) * ((stReqMemCfg->u16Pitch/16)+1)*16 * 4; ++ } ++ else if(stReqMemCfg->u16Pitch & (15)) ++ { ++ stReqMemCfg->u32MemSize = (stReqMemCfg->u16Vsize) * ((stReqMemCfg->u16Pitch/16)+1)*16 * 4; ++ } ++ else if(stReqMemCfg->u16Vsize & (15)) ++ { ++ stReqMemCfg->u32MemSize = (((stReqMemCfg->u16Vsize/16)+1)*16) * stReqMemCfg->u16Pitch * 4; ++ } ++ } ++ else ++ { ++ stReqMemCfg->u32MemSize = (stReqMemCfg->u16Vsize) *(stReqMemCfg->u16Pitch) *4; ++ } ++ if(Mdrv_HVSP_GetFrameBufferCountInformation()== 1) ++ { ++ SCL_ERR( ++ "[HVSP1] Buffer is single, Vsize=%d, Pitch=%d\n",stReqMemCfg->u16Vsize, stReqMemCfg->u16Pitch); ++ stReqMemCfg->u32MemSize = stReqMemCfg->u32MemSize /2 ; ++ } ++ sg_hvsp1_mcnr_size = stReqMemCfg->u32MemSize; ++ if(Mdrv_HVSP_GetFrameBufferCountInformation()== 1) ++ { ++ if((unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 2) > stReqMemCfg->u32MemSize) ++ { ++ SCL_ERR( "[HVSP1] Memory size is too small, Vsize*Pitch*2=%lx, MemSize=%lx\n", ++ (unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 2), stReqMemCfg->u32MemSize); ++ return -EFAULT; ++ } ++ } ++ else if((unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 4) > stReqMemCfg->u32MemSize) ++ { ++ SCL_ERR( "[HVSP1] Memory size is too small, Vsize*Pitch*4=%lx, MemSize=%lx\n", ++ (unsigned long)(stReqMemCfg->u16Vsize * stReqMemCfg->u16Pitch * 4), stReqMemCfg->u32MemSize); ++ return -EFAULT; ++ } ++ SCL_DBG(SCL_DBG_LV_HVSP()&EN_DBGMG_HVSPLEVEL_HVSP1, ++ "[HVSP1], Vsize=%d, Pitch=%d, Size=%lx\n", stReqMemCfg->u16Vsize, stReqMemCfg->u16Pitch,stReqMemCfg->u32MemSize); ++ return 0; ++} ++ ++void _mdrv_hvsp1_FrameBufferMemoryAllocate(void) ++{ ++ if(gu8FrameBufferReadyNum == 0) ++ { ++ _ms_hvsp1_mem_allocate(); ++ MDrv_HVSP_SetMemoryAllocateReady(gu8FrameBufferReadyNum); ++ } ++ else if(gu8FrameBufferReadyNum != 0 && sg_hvsp1_mcnr_size > sg_hvsp1_release_mcnr_size) ++ { ++ _ms_hvsp1_mem_free(); ++ gu8FrameBufferReadyNum = 0; ++ _ms_hvsp1_mem_allocate(); ++ MDrv_HVSP_SetMemoryAllocateReady((gu8FrameBufferReadyNum > 0) ? 1 :0); ++ } ++} ++void _mdrv_hvsp1_FillIPMStructForDriver(ST_IOCTL_HVSP_REQ_MEM_CONFIG *stReqMemCfg,ST_MDRV_HVSP_IPM_CONFIG *stIPMCfg) ++{ ++ stIPMCfg->u16Height = stReqMemCfg->u16Vsize; ++ stIPMCfg->u16Width = stReqMemCfg->u16Pitch; ++ stIPMCfg->u32MemSize = stReqMemCfg->u32MemSize; ++ if(gu8FrameBufferReadyNum & 0x3) ++ { ++ if((stIPMCfg->u16Height <= (FHDWidth)) && (stIPMCfg->u16Width <= FHDWidth)) ++ { ++ stIPMCfg->enRW = E_MDRV_HVSP_MCNR_YCM_W; ++ } ++ else ++ { ++ stIPMCfg->enRW = E_MDRV_HVSP_MCNR_YCM_RW; ++ } ++ sg_hvsp1_mcnr_size = stReqMemCfg->u32MemSize; ++ } ++ else ++ { ++ stIPMCfg->enRW = E_MDRV_HVSP_MCNR_NON; ++ sg_hvsp1_mcnr_size = stReqMemCfg->u32MemSize; ++ } ++ if(sg_hvsp1_mcnr_yc_bus_addr) ++ { ++ stIPMCfg->u32YCPhyAddr = Chip_Phys_to_MIU(sg_hvsp1_mcnr_yc_bus_addr); ++ } ++ if(sg_hvsp1_mcnr_m_bus_addr) ++ { ++ stIPMCfg->u32MPhyAddr = Chip_Phys_to_MIU(sg_hvsp1_mcnr_m_bus_addr); ++ } ++ if(sg_hvsp1_mcnr_ciir_bus_addr) ++ { ++ stIPMCfg->u32CIIRPhyAddr = Chip_Phys_to_MIU(sg_hvsp1_mcnr_ciir_bus_addr); ++ } ++} ++ ++ ++int _mdrv_ms_hvsp1_io_set_input_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_INPUT_CONFIG stInCfg; ++ ST_IOCTL_HVSP_INPUT_CONFIG stIOInCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_INPUT_CONFIG), ++ (((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOInCfg, (__user ST_IOCTL_HVSP_INPUT_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_INPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stInCfg.enColor = (EN_MDRV_HVSP_COLOR_TYPE)stIOInCfg.enColor; ++ stInCfg.enSrcType = (EN_MDRV_HVSP_SRC_TYPE)stIOInCfg.enSrcType; ++ memcpy(&stInCfg.stCaptureWin , &stIOInCfg.stCaptureWin,sizeof(ST_MDRV_HVSP_WINDOW_CONFIG)); ++ memcpy(&stInCfg.stTimingCfg , &stIOInCfg.stTimingCfg,sizeof(ST_MDRV_HVSPTIMING_CONFIG)); ++ } ++ ++ } ++ stInCfg.stclk = &(_dev_ms_hvsp1.stclk); ++ ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG, (void *)&stInCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInputConfig(E_MDRV_HVSP_ID_1, &stInCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_hvsp1_io_set_output_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_OUTPUT_CONFIG stOutCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG), ++ (((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stOutCfg, (__user ST_IOCTL_HVSP_OUTPUT_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++int _mdrv_ms_hvsp1_io_set_scaling_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCALING_CONFIG stIOSclCfg; ++ ST_MDRV_HVSP_SCALING_CONFIG stSclCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SCALING_CONFIG), ++ (((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOSclCfg, (__user ST_IOCTL_HVSP_SCALING_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_SCALING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stSclCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp1.stclk); ++ stSclCfg.stCropWin.bEn = stIOSclCfg.bCropEn; ++ stSclCfg.stCropWin.u16Height = stIOSclCfg.stCropWin.u16Height; ++ stSclCfg.stCropWin.u16Width = stIOSclCfg.stCropWin.u16Width; ++ stSclCfg.stCropWin.u16X = stIOSclCfg.stCropWin.u16X; ++ stSclCfg.stCropWin.u16Y = stIOSclCfg.stCropWin.u16Y; ++ stSclCfg.u16Dsp_Height = stIOSclCfg.u16Dsp_Height; ++ stSclCfg.u16Dsp_Width = stIOSclCfg.u16Dsp_Width; ++ stSclCfg.u16Src_Height = stIOSclCfg.u16Src_Height; ++ stSclCfg.u16Src_Width = stIOSclCfg.u16Src_Width; ++ } ++ } ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG, (void *)&stSclCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ MDrv_HVSP_SetPriMaskInstId(MDrv_MultiInst_GetHvspQuantifyPreInstId()); ++ if(!MDrv_HVSP_SetScalingConfig(E_MDRV_HVSP_ID_1, &stSclCfg )) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++int _mdrv_ms_hvsp1_io_req_mem_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_REQ_MEM_CONFIG stReqMemCfg; ++ ST_MDRV_HVSP_IPM_CONFIG stIPMCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ MsOS_Memset(&stReqMemCfg,0,sizeof(ST_IOCTL_HVSP_REQ_MEM_CONFIG)); ++ MsOS_Memset(&stIPMCfg,0,sizeof(ST_MDRV_HVSP_IPM_CONFIG)); ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_REQ_MEM_CONFIG), ++ (((ST_IOCTL_HVSP_REQ_MEM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_REQ_MEM_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stReqMemCfg, (__user ST_IOCTL_HVSP_REQ_MEM_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_REQ_MEM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ret = _mdrv_hvsp1_CheckModifyMemSize(&stReqMemCfg); ++ _mdrv_hvsp1_FrameBufferMemoryAllocate(); ++ _mdrv_hvsp1_FillIPMStructForDriver(&stReqMemCfg,&stIPMCfg); ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_MEM_REQ_CONFIG, (void *)&stIPMCfg, filp->private_data)) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInitIPMConfig(E_MDRV_HVSP_ID_1, &stIPMCfg)) ++ { ++ return -EFAULT; ++ } ++ } ++ if(gu8FrameBufferReadyNum == 0) ++ { ++ return -EFAULT; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_set_misc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_MISC_CONFIG stIOMiscCfg; ++ ST_MDRV_HVSP_MISC_CONFIG stMiscCfg; ++ MsOS_Memset(&stIOMiscCfg,0,sizeof(ST_IOCTL_HVSP_MISC_CONFIG)); ++ MsOS_Memset(&stMiscCfg,0,sizeof(ST_MDRV_HVSP_MISC_CONFIG)); ++ if(copy_from_user(&stIOMiscCfg, (__user ST_IOCTL_HVSP_MISC_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_MISC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ if(stIOMiscCfg.u32Addr && stIOMiscCfg.u32Size>0 && stIOMiscCfg.u32Size< 0xFFFF) ++ { ++ stMiscCfg.u32Addr = stIOMiscCfg.u32Addr; ++ stMiscCfg.u32Size = stIOMiscCfg.u32Size; ++ stMiscCfg.u8Cmd = stIOMiscCfg.u8Cmd; ++ } ++ else ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(MDrv_HVSP_SetMiscConfig(&stMiscCfg)) ++ { ++ return 0; ++ } ++ else ++ { ++ return -EFAULT; ++ } ++} ++ ++int _mdrv_ms_hvsp1_io_set_post_crop_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_POSTCROP_CONFIG stIOPostCfg; ++ ST_MDRV_HVSP_POSTCROP_CONFIG stPostCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_POSTCROP_CONFIG), ++ (((ST_IOCTL_HVSP_POSTCROP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_POSTCROP_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOPostCfg, (__user ST_IOCTL_HVSP_POSTCROP_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_POSTCROP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stPostCfg.bCropEn = stIOPostCfg.bCropEn; ++ stPostCfg.bFmCntEn = stIOPostCfg.bFmCntEn; ++ stPostCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp1.stclk); ++ stPostCfg.u16Height = stIOPostCfg.u16Height; ++ stPostCfg.u16Width = stIOPostCfg.u16Width; ++ stPostCfg.u16X = stIOPostCfg.u16X; ++ stPostCfg.u16Y = stIOPostCfg.u16Y; ++ stPostCfg.u8FmCnt = stIOPostCfg.u8FmCnt; ++ } ++ } ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_POST_CROP_CONFIG, (void *)&stPostCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ MDrv_HVSP_SetPriMaskInstId(MDrv_MultiInst_GetHvspQuantifyPreInstId()); ++ if(!MDrv_HVSP_SetPostCropConfig(E_MDRV_HVSP_ID_1, &stPostCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_HVSP_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_hvsp1_io_get_inform_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCINFORM_CONFIG stIOInfoCfg; ++ ST_MDRV_HVSP_SCINFORM_CONFIG stInfoCfg; ++ int Ret = 0; ++ if(!MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_1, &stInfoCfg)) ++ { ++ Ret = -EFAULT; ++ } ++ else ++ { ++ memcpy(&stIOInfoCfg, &stInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG)); ++ if(copy_to_user((ST_IOCTL_HVSP_SCINFORM_CONFIG __user *)arg, &stIOInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG))) ++ { ++ Ret = -EFAULT; ++ } ++ else ++ { ++ Ret = 0; ++ } ++ } ++ ++ return Ret; ++} ++ ++int _mdrv_ms_hvsp1_io_release_mem_config(struct file *filp, unsigned long arg) ++{ ++ _ms_hvsp1_mem_free(); ++ return 0; ++} ++ ++int _mdrv_ms_hvsp1_io_set_osd_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_OSD_CONFIG stOSDCfg; ++ ST_IOCTL_HVSP_OSD_CONFIG stIOOSDCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OSD_CONFIG), ++ (((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOOSDCfg, (__user ST_IOCTL_HVSP_OSD_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_OSD_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stOSDCfg.enOSD_loc = (EN_MDRV_HVSP_OSD_LOC_TYPE)stIOOSDCfg.enOSD_loc; ++ stOSDCfg.stOsdOnOff.bOSDEn = stIOOSDCfg.bEn; ++ stOSDCfg.stOsdOnOff.bOSDBypass = stIOOSDCfg.bOSDBypass; ++ stOSDCfg.stOsdOnOff.bWTMBypass = stIOOSDCfg.bWTMBypass; ++ } ++ } ++ if(_ms_hvsp1_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG, (void *)&stOSDCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetOSDConfig(E_MDRV_HVSP_ID_1, &stOSDCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_set_primask_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_PRIMASK_CONFIG stCfg; ++ ST_IOCTL_HVSP_PRIMASK_CONFIG stIOCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ MsOS_Memset(&stIOCfg,0,sizeof(ST_IOCTL_HVSP_PRIMASK_CONFIG)); ++ MsOS_Memset(&stCfg,0,sizeof(ST_MDRV_HVSP_PRIMASK_CONFIG)); ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_PRIMASK_CONFIG), ++ (((ST_IOCTL_HVSP_PRIMASK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_PRIMASK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stIOCfg, (__user ST_IOCTL_HVSP_PRIMASK_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_PRIMASK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stCfg.bMask = stIOCfg.bMask; ++ if(stIOCfg.u8idx>= PriMaskNum) ++ { ++ return -EINVAL; ++ } ++ stCfg.u8idx = stIOCfg.u8idx; ++ memcpy(&stCfg.stMaskWin,&stIOCfg.stMaskWin,sizeof(ST_IOCTL_HVSP_WINDOW_CONFIG)); ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ MDrv_HVSP_SetPriMaskInstId(MDrv_MultiInst_GetHvspQuantifyPreInstId()); ++ if(!MDrv_HVSP_SetPriMaskConfig(&stCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_primask_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG stIOCfg; ++ unsigned char bEn; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG), ++ (((ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOCfg, (__user ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ bEn= stIOCfg.bEn; ++ } ++ } ++ if(!MDrv_HVSP_SetPriMaskTrigger(bEn)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_set_fb_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG stFbMgCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp1_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG), ++ (((ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stFbMgCfg, (__user ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_SET_FB_MANAGE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(!MDrv_HVSP_SetFbManageConfig((EN_MDRV_HVSP_FBMG_SET_TYPE)stFbMgCfg.enSet)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp1_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_HVSP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[HVSP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_HVSP_VERSION_CONFIG), ++ (((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_HVSP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_HVSP_VERSION); ++ stCfg.u32Version = IOCTL_HVSP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP] No Header !!! \n"); ++ SCL_ERR( "[HVSP]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_hvsp1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_hvsp1.refCnt <= 0) ++ { ++ SCL_ERR( "[HVSP1] HVSP1IO_IOCTL refCnt =%d!!! \n", _dev_ms_hvsp1.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_HVSP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_HVSP_MAX_NR) ++ { ++ SCL_ERR( "[HVSP1] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1, "[HVSP1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_input_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OUT_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_output_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_scaling_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_REQ_MEM_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_req_mem_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_MISC_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_misc_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_POST_CROP_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_post_crop_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_INFORM_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_get_inform_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_RELEASE_MEM_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_release_mem_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OSD_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_osd_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_SET_PRIMASK_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_primask_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_PRIMASK_TRIGGER_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_primask_trigger_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_SET_FB_MANAGE_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_set_fb_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_hvsp1_io_get_version(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[HVSP1] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_hvsp1_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1, "[HVSP1]start %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = (wait_queue_head_t *)MDrv_HVSP_GetWaitQueueHead(); ++ MDrv_HVSP_SetPollWait(filp, pWaitQueueHead, wait); ++ if(gu8first) ++ { ++ ret = POLLIN; ++ gu8first = 0; ++ } ++ else if(MDrv_HVSP_GetCMDQDoneStatus(E_MDRV_HVSP_ID_1)) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_hvsp1_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if(MDrv_HVSP_Suspend(E_MDRV_HVSP_ID_1, &stHvspSuspendResumeCfg)) ++ { ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++static int mdrv_ms_hvsp1_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if(MDrv_HVSP_Resume(E_MDRV_HVSP_ID_1, &stHvspSuspendResumeCfg)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp1_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_ASSERT(_dev_ms_hvsp1.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ if(_dev_ms_hvsp1.refCnt == 0) ++ { ++ MDrv_HVSP_Open(E_MDRV_HVSP_ID_1); ++ } ++ if(!ret) ++ { ++ _dev_ms_hvsp1.refCnt++; ++ } ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,_dev_ms_hvsp1.refCnt); ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp1_release(struct inode *inode, struct file *filp) ++{ ++ ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1, filp->private_data); ++ filp->private_data = NULL; ++ _dev_ms_hvsp1.refCnt--; ++ SCL_ASSERT(_dev_ms_hvsp1.refCnt>=0); ++ if(_dev_ms_hvsp1.refCnt == 0) ++ { ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ MDrv_HVSP_Release(E_MDRV_HVSP_ID_1); ++ gu8first = 1; ++ } ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,_dev_ms_hvsp1.refCnt); ++ return 0; ++} ++#if CONFIG_OF ++static int mdrv_ms_hvsp1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ unsigned char ret; ++ int s32Ret; ++ unsigned int u32Dropmode; ++ dev_t dev; ++ //struct resource *res_irq; ++ //struct device_node *np; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,__LINE__); ++//mod init ++ if(_dev_ms_hvsp1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp1.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP1] Unable to get major %d\n", _dev_ms_hvsp1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp1.cdev, &_dev_ms_hvsp1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp1.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ m_hvsp1_class = msys_get_sysfs_class(); ++ if(!m_hvsp1_class) ++ { ++ m_hvsp1_class = class_create(THIS_MODULE, hvsp1_classname); ++ } ++ if(IS_ERR(m_hvsp1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_hvsp1.devicenode = device_create(m_hvsp1_class, NULL, dev,NULL, "mhvsp1"); ++ _dev_ms_hvsp1.devicenode->dma_mask=&ms_hvsp1_dma_mask; ++ _dev_ms_hvsp1.devicenode->coherent_dma_mask=ms_hvsp1_dma_mask; ++ } ++ ++//probe ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ if(of_property_read_u32(pdev->dev.of_node, "DigitalZoom-Dropmode", &u32Dropmode)) ++ { ++ printk(KERN_WARNING "[HVSP] Failed to read CMDQ-mode property, default on/n"); ++ u32Dropmode = 1; //if can't get, default on ++ } ++ if(u32Dropmode) ++ { ++ printk(KERN_WARNING "[HVSP]u32Dropmode on/n"); ++ MsOS_SetHVSPDigitalZoomMode(u32Dropmode); ++ } ++ else ++ { ++ printk(KERN_WARNING "[HVSP]u32Dropmode off/n"); ++ MsOS_SetHVSPDigitalZoomMode(u32Dropmode); ++ } ++ //res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);// return NULL ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ //if (res_irq) ++ //{ ++ //SCL_IRQ_ID = res_irq->start; ++ //SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] Get resource IORESOURCE_IRQ = 0x%x\n",SCL_IRQ_ID); ++ //} ++ //else ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stHVSPInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stHVSPInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_1, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_hvsp1_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_hvsp1.stclk.idclk = of_clk_get(st_ms_hvsp1_device.dev.of_node,0); ++ _dev_ms_hvsp1.stclk.fclk1 = of_clk_get(st_ms_hvsp1_device.dev.of_node,1); ++ _dev_ms_hvsp1.stclk.fclk2 = of_clk_get(st_ms_hvsp1_device.dev.of_node,2); ++ _dev_ms_hvsp1.stclk.odclk = of_clk_get(st_ms_hvsp1_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_hvsp1.stclk.idclk) || IS_ERR(_dev_ms_hvsp1.stclk.fclk1) || IS_ERR(_dev_ms_hvsp1.stclk.fclk2)|| IS_ERR(_dev_ms_hvsp1.stclk.odclk)) ++ { ++ SCL_ERR( "[HVSP1] Can't Get CLK\n"); ++ return 0 ; ++ } ++ //create device ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_ptgen); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_clk); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_proc); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_SCIQ); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_ints); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_dbgmg); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_osd); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_od); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_fbmg); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_mutex); ++ gbCIIR = 1; ++ Reset_DBGMG_FLAG(); ++ if (ret != 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] attr ok\n"); ++ } ++ gbProbeAlready |= EN_DBG_HVSP1_CONFIG; ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1); ++ gu8first = 1; ++ return 0; ++} ++static int mdrv_ms_hvsp1_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ _ms_hvsp1_mem_free(); ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_HVSP1_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_HVSP_Exit(1); ++ } ++ else if(!(gbProbeAlready& (EN_DBG_HVSP1_CONFIG|EN_DBG_HVSP2_CONFIG|EN_DBG_HVSP3_CONFIG))) ++ { ++ MDrv_HVSP_Exit(0); ++ } ++ cdev_del(&_dev_ms_hvsp1.cdev); ++ device_destroy(m_hvsp1_class, MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor)); ++ class_destroy(m_hvsp1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_hvsp1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ unsigned char ret; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ stHVSPInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stHVSPInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_1, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ //no device tree use hardcode ++ //create device ++ ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_ptgen); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_monitorHW); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_clk); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_proc); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_ints); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_dbgmg); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_osd); ++ ret = device_create_file(_dev_ms_hvsp1.devicenode, &dev_attr_fbmg); ++ Reset_DBGMG_FLAG(); ++ if (ret != 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ptgen_call sysfs files: %d\n", ret); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP1); ++ return 0; ++} ++static int mdrv_ms_hvsp1_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ _ms_hvsp1_mem_free(); ++ MDrv_HVSP_IDCLKRelease(&_dev_ms_hvsp1.stclk); ++ ++ return 0; ++} ++ ++#endif ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_hvsp1_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_hvsp1_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_HVSP1_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++} ++#else ++ ++int _mdrv_ms_hvsp1_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ //struct device_node *np; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ //np = of_find_compatible_node(NULL, NULL, "mstar,hvsp1"); ++ //if (np) ++ //{ ++ // SCL_DBG(SCL_DBG_LV_MDRV_IO(), "Find scl dts node\n"); ++ // st_ms_hvsp1_device.dev.of_node = of_node_get(np); ++ // of_node_put(np); ++ //} ++ //else ++ //{ ++ // return -ENODEV; ++ //} ++ ++ if(_dev_ms_hvsp1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp1.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP1] Unable to get major %d\n", _dev_ms_hvsp1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp1.cdev, &_dev_ms_hvsp1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp1.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp1_class = class_create(THIS_MODULE, hvsp1_classname); ++ if(IS_ERR(m_hvsp1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_hvsp1_class, NULL, dev,NULL, "mhvsp1"); ++ } ++ ++ ret = platform_driver_register(&st_ms_hvsp1_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_hvsp1_device); ++ if (ret) // if register device fail, then unregister the driver. ++ { ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++ SCL_ERR( "[HVSP1] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_hvsp1.cdev); ++ device_destroy(m_hvsp1_class, MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor)); ++ class_destroy(m_hvsp1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp1.s32Major, _dev_ms_hvsp1.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_hvsp1_driver); ++} ++ ++#endif ++ ++ ++module_init(_mdrv_ms_hvsp1_init); ++module_exit(_mdrv_ms_hvsp1_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms hvsp1 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_hvsp2_io.c b/drivers/mstar/scl/infinity3/mdrv_hvsp2_io.c +new file mode 100644 +index 00000000..1585e7ce +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_hvsp2_io.c +@@ -0,0 +1,1001 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_msys.h" ++#include "mdrv_hvsp_io_i3_st.h" ++#include "mdrv_hvsp_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_HVSP_DEVICE_COUNT 1 ++#define MDRV_MS_HVSP_NAME "mhvsp2" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_HVSP "mhvsp2" ++#define MDRV_MAJOR_HVSP 0xea ++#define MDRV_MINOR_HVSP 0x02 ++//------------------------------------------------------------------------------------------------- ++ ++#define CMD_PARSING(x) (x==IOCTL_HVSP_SET_IN_CONFIG ? "IOCTL_HVSP_SET_IN_CONFIG" : \ ++ x==IOCTL_HVSP_SET_OUT_CONFIG ? "IOCTL_HVSP_SET_OUT_CONFIG" : \ ++ x==IOCTL_HVSP_SET_SCALING_CONFIG ? "IOCTL_HVSP_SET_SCALING_CONFIG" : \ ++ x==IOCTL_HVSP_REQ_MEM_CONFIG ? "IOCTL_HVSP_REQ_MEM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_MISC_CONFIG ? "IOCTL_HVSP_SET_MISC_CONFIG" : \ ++ x==IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ? "IOCTL_HVSP_GET_PRIVATE_ID_CONFIG" : \ ++ "UNKNOWN") ++ ++//------------------------------------------------------------------------------------------------- ++ ++int mdrv_ms_hvsp2_open(struct inode *inode, struct file *filp); ++int mdrv_ms_hvsp2_release(struct inode *inode, struct file *filp); ++long mdrv_ms_hvsp2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_hvsp2_probe(struct platform_device *pdev); ++static int mdrv_ms_hvsp2_remove(struct platform_device *pdev); ++static int mdrv_ms_hvsp2_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_hvsp2_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_hvsp2_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_HVSP_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_HVSP; ++ ++static ST_DEV_HVSP _dev_ms_hvsp2 = ++{ ++ .s32Major = MDRV_MAJOR_HVSP, ++ .s32Minor = MDRV_MINOR_HVSP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_HVSP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_hvsp2_open, ++ .release = mdrv_ms_hvsp2_release, ++ .unlocked_ioctl = mdrv_ms_hvsp2_ioctl, ++ .poll = mdrv_ms_hvsp2_poll, ++ } ++}; ++ ++static struct class * m_hvsp2_class = NULL; ++static char * hvsp2_classname = "m_hvsp2_class"; ++ ++ ++static const struct of_device_id ms_hvsp2_of_match_table[] = ++{ ++ { .compatible = "mstar,hvsp2" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_hvsp2_driver = ++{ ++ .probe = mdrv_ms_hvsp2_probe, ++ .remove = mdrv_ms_hvsp2_remove, ++ .suspend = mdrv_ms_hvsp2_suspend, ++ .resume = mdrv_ms_hvsp2_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_HVSP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_hvsp2_of_match_table), ++ }, ++}; ++ ++static u64 ms_hvsp2_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_hvsp2_device = ++{ ++ .name = "mhvsp2", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_hvsp2_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++MS_U8 gu8sc2first; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_osd_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ MDrv_HVSP_OsdStore(buf,E_MDRV_HVSP_ID_2); ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t check_osd_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_OsdShow(buf); ++} ++static DEVICE_ATTR(osd,0644, check_osd_show, check_osd_store); ++static ssize_t check_SCIQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ MDrv_HVSP_SCIQStore(buf,E_MDRV_HVSP_ID_2); ++ return n; ++} ++static ssize_t check_SCIQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_SCIQShow(buf,E_MDRV_HVSP_ID_2); ++} ++ ++static DEVICE_ATTR(SCIQ,0644, check_SCIQ_show, check_SCIQ_store); ++void _mdrv_ms_hvsp2_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_HVSP_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_hvsp2_io_version_check(ST_MDRV_HVSP_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP2] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[HVSP2] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP2] No Header !!! \n"); ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++ ++static int _ms_hvsp2_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp2_io_set_input_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_INPUT_CONFIG stInCfg; ++ ST_IOCTL_HVSP_INPUT_CONFIG stIOInCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_INPUT_CONFIG), ++ (((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOInCfg, (__user ST_IOCTL_HVSP_INPUT_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_INPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stInCfg.enColor = (EN_MDRV_HVSP_COLOR_TYPE)stIOInCfg.enColor; ++ stInCfg.enSrcType = (EN_MDRV_HVSP_SRC_TYPE)stIOInCfg.enSrcType; ++ memcpy(&stInCfg.stCaptureWin , &stIOInCfg.stCaptureWin,sizeof(ST_MDRV_HVSP_WINDOW_CONFIG)); ++ memcpy(&stInCfg.stTimingCfg , &stIOInCfg.stTimingCfg,sizeof(ST_MDRV_HVSPTIMING_CONFIG)); ++ } ++ ++ } ++ ++ if(_ms_hvsp2_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG, (void *)&stInCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInputConfig(E_MDRV_HVSP_ID_2, &stInCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_hvsp2_io_set_output_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_OUTPUT_CONFIG stOutCfg; ++ int ret = 0; ++ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG), ++ (((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stOutCfg, (__user ST_IOCTL_HVSP_OUTPUT_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++int _mdrv_ms_hvsp2_io_set_scaling_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCALING_CONFIG stIOSclCfg; ++ ST_MDRV_HVSP_SCALING_CONFIG stSclCfg; ++ int ret = 0; ++ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SCALING_CONFIG), ++ (((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOSclCfg, (__user ST_IOCTL_HVSP_SCALING_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_SCALING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stSclCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp2.stclk); ++ stSclCfg.stCropWin.bEn = stIOSclCfg.bCropEn; ++ stSclCfg.stCropWin.u16Height = stIOSclCfg.stCropWin.u16Height; ++ stSclCfg.stCropWin.u16Width = stIOSclCfg.stCropWin.u16Width; ++ stSclCfg.stCropWin.u16X = stIOSclCfg.stCropWin.u16X; ++ stSclCfg.stCropWin.u16Y = stIOSclCfg.stCropWin.u16Y; ++ stSclCfg.u16Dsp_Height = stIOSclCfg.u16Dsp_Height; ++ stSclCfg.u16Dsp_Width = stIOSclCfg.u16Dsp_Width; ++ stSclCfg.u16Src_Height = stIOSclCfg.u16Src_Height; ++ stSclCfg.u16Src_Width = stIOSclCfg.u16Src_Width; ++ } ++ } ++ if(_ms_hvsp2_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG, (void *)&stSclCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetScalingConfig(E_MDRV_HVSP_ID_2, &stSclCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp2_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_HVSP_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_hvsp2_io_get_inform_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCINFORM_CONFIG stIOInfoCfg; ++ ST_MDRV_HVSP_SCINFORM_CONFIG stInfoCfg; ++ int ret = 0; ++ if(!MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_2, &stInfoCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ memcpy(&stIOInfoCfg, &stInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG)); ++ if(copy_to_user((ST_IOCTL_HVSP_SCINFORM_CONFIG __user *)arg, &stIOInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp2_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_HVSP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[HVSP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_HVSP_VERSION_CONFIG), ++ (((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_HVSP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_HVSP_VERSION); ++ stCfg.u32Version = IOCTL_HVSP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP] No Header !!! \n"); ++ SCL_ERR( "[HVSP]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++int _mdrv_ms_hvsp2_io_set_osd_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_OSD_CONFIG stOSDCfg; ++ ST_IOCTL_HVSP_OSD_CONFIG stIOOSDCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp2_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OSD_CONFIG), ++ (((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOOSDCfg, (__user ST_IOCTL_HVSP_OSD_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_OSD_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stOSDCfg.enOSD_loc = (EN_MDRV_HVSP_OSD_LOC_TYPE)stIOOSDCfg.enOSD_loc; ++ stOSDCfg.stOsdOnOff.bOSDEn = stIOOSDCfg.bEn; ++ } ++ } ++ if(_ms_hvsp2_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG, (void *)&stOSDCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetOSDConfig(E_MDRV_HVSP_ID_3, &stOSDCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_hvsp2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_hvsp2.refCnt <= 0) ++ { ++ SCL_ERR( "[HVSP2] HVSP2IO_IOCTL refCnt =%d!!! \n", _dev_ms_hvsp2.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_HVSP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_HVSP_MAX_NR) ++ { ++ SCL_ERR( "[HVSP2] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP2] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2, "[HVSP2] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_input_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OUT_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_output_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_scaling_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OSD_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_set_osd_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_SET_FB_MANAGE_CONFIG: ++ case IOCTL_HVSP_REQ_MEM_CONFIG: ++ case IOCTL_HVSP_SET_MISC_CONFIG: ++ case IOCTL_HVSP_SET_POST_CROP_CONFIG: ++ SCL_ERR( "[HVSP2] Not Support IOCTL %x\n ",u32Cmd); ++ retval = -EINVAL; ++ break; ++ case IOCTL_HVSP_GET_INFORM_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_get_inform_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_hvsp2_io_get_version(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[HVSP2] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_hvsp2_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2, "[SCLDMA1]start %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = (wait_queue_head_t *)MDrv_HVSP_GetWaitQueueHead(); ++ MDrv_HVSP_SetPollWait(filp, pWaitQueueHead, wait); ++ if(gu8sc2first) ++ { ++ ret = POLLIN; ++ gu8sc2first = 0; ++ } ++ else if(MDrv_HVSP_GetCMDQDoneStatus(E_MDRV_HVSP_ID_2)) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_hvsp2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s:%d\n",__FUNCTION__,__LINE__); ++//mod init ++ if(_dev_ms_hvsp2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp2.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP2] Unable to get major %d\n", _dev_ms_hvsp2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp2.cdev, &_dev_ms_hvsp2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp2.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp2_class = msys_get_sysfs_class(); ++ if(!m_hvsp2_class) ++ { ++ m_hvsp2_class = class_create(THIS_MODULE, hvsp2_classname); ++ } ++ if(IS_ERR(m_hvsp2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_hvsp2.devicenode = device_create(m_hvsp2_class, NULL, dev,NULL, "mhvsp2"); ++ _dev_ms_hvsp2.devicenode->dma_mask=&ms_hvsp2_dma_mask; ++ _dev_ms_hvsp2.devicenode->coherent_dma_mask=ms_hvsp2_dma_mask; ++ } ++ ++//probe ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ stHVSPInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stHVSPInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_2, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_hvsp2_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_hvsp2.stclk.idclk = of_clk_get(st_ms_hvsp2_device.dev.of_node,0); ++ _dev_ms_hvsp2.stclk.fclk1 = of_clk_get(st_ms_hvsp2_device.dev.of_node,1); ++ _dev_ms_hvsp2.stclk.fclk2 = of_clk_get(st_ms_hvsp2_device.dev.of_node,2); ++ _dev_ms_hvsp2.stclk.odclk = of_clk_get(st_ms_hvsp2_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_hvsp2.stclk.idclk) || IS_ERR(_dev_ms_hvsp2.stclk.fclk1) ++ || IS_ERR(_dev_ms_hvsp2.stclk.fclk2)|| IS_ERR(_dev_ms_hvsp2.stclk.odclk)) ++ { ++ SCL_ERR( "[HVSP2] Can't Get CLK\n"); ++ return 0 ; ++ } ++ device_create_file(_dev_ms_hvsp2.devicenode, &dev_attr_osd); ++ device_create_file(_dev_ms_hvsp2.devicenode, &dev_attr_SCIQ); ++ //sysfs_create_link(&pdev->dev.parent->kobj, &pdev->dev.kobj, "mhvsp2"); ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2); ++ gbProbeAlready |= EN_DBG_HVSP2_CONFIG; ++ gu8sc2first = 1; ++ return 0; ++} ++static int mdrv_ms_hvsp2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_HVSP2_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_HVSP_Exit(1); ++ } ++ else ++ { ++ MDrv_HVSP_Exit(0); ++ } ++ cdev_del(&_dev_ms_hvsp2.cdev); ++ device_destroy(m_hvsp2_class, MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor)); ++ class_destroy(m_hvsp2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ return 0; ++} ++ ++#else ++static int mdrv_ms_hvsp2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_2, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2); ++ ++ return 0; ++} ++ ++static int mdrv_ms_hvsp2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ return 0; ++} ++#endif ++static int mdrv_ms_hvsp2_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Suspend(E_MDRV_HVSP_ID_2, &stHvspSuspendResumeCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++static int mdrv_ms_hvsp2_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet ; ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Resume(E_MDRV_HVSP_ID_2, &stHvspSuspendResumeCfg)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp2_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_hvsp2.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ if(!ret) ++ { ++ _dev_ms_hvsp2.refCnt++; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp2_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_HVSP2, filp->private_data); ++ ++ _dev_ms_hvsp2.refCnt--; ++ SCL_ASSERT(_dev_ms_hvsp2.refCnt >= 0); ++ if(_dev_ms_hvsp2.refCnt == 0) ++ { ++ MDrv_HVSP_Release(E_MDRV_HVSP_ID_2); ++ gu8sc2first = 1; ++ } ++ //free_irq(INT_IRQ_HVSP2W, MDrv_HVSP2W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_hvsp2_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_hvsp2_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_HVSP2_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[HVSP2] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP2] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++} ++#else ++int _mdrv_ms_hvsp2_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ struct device_node *np = NULL; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_hvsp2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp2.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP2] Unable to get major %d\n", _dev_ms_hvsp2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp2.cdev, &_dev_ms_hvsp2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp2.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp2_class = class_create(THIS_MODULE, hvsp2_classname); ++ if(IS_ERR(m_hvsp2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_hvsp2_class, NULL, dev,NULL, "mhvsp2"); ++ } ++ ++ /* initial the whole HVSP2 Driver */ ++ ret = platform_driver_register(&st_ms_hvsp2_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_hvsp2_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++ SCL_ERR( "[HVSP2] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP2] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_hvsp2.cdev); ++ device_destroy(m_hvsp2_class, MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor)); ++ class_destroy(m_hvsp2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp2.s32Major, _dev_ms_hvsp2.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_hvsp2_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_hvsp2_init); ++module_exit(_mdrv_ms_hvsp2_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms hvsp2 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_hvsp3_io.c b/drivers/mstar/scl/infinity3/mdrv_hvsp3_io.c +new file mode 100644 +index 00000000..089f56a8 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_hvsp3_io.c +@@ -0,0 +1,1022 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_msys.h" ++#include "mdrv_hvsp_io_i3_st.h" ++#include "mdrv_hvsp_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_HVSP_DEVICE_COUNT 1 ++#define MDRV_MS_HVSP_NAME "mhvsp3" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_HVSP "mhvsp3" ++#define MDRV_MAJOR_HVSP 0xea ++#define MDRV_MINOR_HVSP 0x03 ++//------------------------------------------------------------------------------------------------- ++ ++#define CMD_PARSING(x) (x==IOCTL_HVSP_SET_IN_CONFIG ? "IOCTL_HVSP_SET_IN_CONFIG" : \ ++ x==IOCTL_HVSP_SET_OUT_CONFIG ? "IOCTL_HVSP_SET_OUT_CONFIG" : \ ++ x==IOCTL_HVSP_SET_SCALING_CONFIG ? "IOCTL_HVSP_SET_SCALING_CONFIG" : \ ++ x==IOCTL_HVSP_REQ_MEM_CONFIG ? "IOCTL_HVSP_REQ_MEM_CONFIG" : \ ++ x==IOCTL_HVSP_SET_MISC_CONFIG ? "IOCTL_HVSP_SET_MISC_CONFIG" : \ ++ x==IOCTL_HVSP_GET_PRIVATE_ID_CONFIG ? "IOCTL_HVSP_GET_PRIVATE_ID_CONFIG" : \ ++ "UNKNOWN") ++ ++//------------------------------------------------------------------------------------------------- ++ ++int mdrv_ms_hvsp3_open(struct inode *inode, struct file *filp); ++int mdrv_ms_hvsp3_release(struct inode *inode, struct file *filp); ++long mdrv_ms_hvsp3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_hvsp3_probe(struct platform_device *pdev); ++static int mdrv_ms_hvsp3_remove(struct platform_device *pdev); ++static int mdrv_ms_hvsp3_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_hvsp3_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_hvsp3_poll(struct file *filp, struct poll_table_struct *wait); ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_HVSP_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_HVSP; ++ ++static ST_DEV_HVSP _dev_ms_hvsp3 = ++{ ++ .s32Major = MDRV_MAJOR_HVSP, ++ .s32Minor = MDRV_MINOR_HVSP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_HVSP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_hvsp3_open, ++ .release = mdrv_ms_hvsp3_release, ++ .unlocked_ioctl = mdrv_ms_hvsp3_ioctl, ++ .poll = mdrv_ms_hvsp3_poll, ++ } ++}; ++ ++static struct class * m_hvsp3_class = NULL; ++static char * hvsp3_classname = "m_hvsp3_class"; ++ ++ ++static const struct of_device_id ms_hvsp3_of_match_table[] = ++{ ++ { .compatible = "mstar,hvsp3" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_hvsp3_driver = ++{ ++ .probe = mdrv_ms_hvsp3_probe, ++ .remove = mdrv_ms_hvsp3_remove, ++ .suspend = mdrv_ms_hvsp3_suspend, ++ .resume = mdrv_ms_hvsp3_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_HVSP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_hvsp3_of_match_table), ++ }, ++}; ++ ++static u64 ms_hvsp3_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_hvsp3_device = ++{ ++ .name = "mhvsp3", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_hvsp3_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Instance function ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_osd_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ MDrv_HVSP_OsdStore(buf,E_MDRV_HVSP_ID_3); ++ return n; ++ } ++ ++ return 0; ++} ++static ssize_t check_osd_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_OsdShow(buf); ++} ++static DEVICE_ATTR(osd,0644, check_osd_show, check_osd_store); ++static ssize_t check_SCIQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ MDrv_HVSP_SCIQStore(buf,E_MDRV_HVSP_ID_3); ++ return n; ++} ++static ssize_t check_SCIQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_HVSP_SCIQShow(buf,E_MDRV_HVSP_ID_3); ++} ++ ++static DEVICE_ATTR(SCIQ,0644, check_SCIQ_show, check_SCIQ_store); ++EN_MDRV_MULTI_INST_CMD_TYPE _mdrv_ms_hvsp3_translate_multiinst_cmd(unsigned int u32Cmd) ++{ ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd; ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ enCmd =E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG; ++ break; ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ enCmd =E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG; ++ break; ++ default: ++ enCmd =E_MDRV_MULTI_INST_CMD_MAX; ++ break; ++ } ++ ++ return enCmd; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++void _mdrv_ms_hvsp3_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_HVSP_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_hvsp3_io_version_check(ST_MDRV_HVSP_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP3] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[HVSP3] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP3] No Header !!! \n"); ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++ ++static int _ms_hvsp3_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_hvsp3_io_set_input_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_INPUT_CONFIG stInCfg; ++ ST_IOCTL_HVSP_INPUT_CONFIG stIOInCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_INPUT_CONFIG), ++ (((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_INPUT_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOInCfg, (__user ST_IOCTL_HVSP_INPUT_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_INPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stInCfg.enColor = (EN_MDRV_HVSP_COLOR_TYPE)stIOInCfg.enColor; ++ stInCfg.enSrcType = (EN_MDRV_HVSP_SRC_TYPE)stIOInCfg.enSrcType; ++ memcpy(&stInCfg.stCaptureWin , &stIOInCfg.stCaptureWin,sizeof(ST_MDRV_HVSP_WINDOW_CONFIG)); ++ memcpy(&stInCfg.stTimingCfg , &stIOInCfg.stTimingCfg,sizeof(ST_MDRV_HVSPTIMING_CONFIG)); ++ } ++ } ++ ++ if(_ms_hvsp3_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG, (void *)&stInCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetInputConfig(E_MDRV_HVSP_ID_3, &stInCfg )) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_hvsp3_io_set_output_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_OUTPUT_CONFIG stOutCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG), ++ (((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OUTPUT_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stOutCfg, (__user ST_IOCTL_HVSP_OUTPUT_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_OUTPUT_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++int _mdrv_ms_hvsp3_io_set_scaling_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCALING_CONFIG stIOSclCfg; ++ ST_MDRV_HVSP_SCALING_CONFIG stSclCfg; ++ int ret = 0; ++ ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_SCALING_CONFIG), ++ (((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_SCALING_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOSclCfg, (__user ST_IOCTL_HVSP_SCALING_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_SCALING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stSclCfg.stclk = (ST_MDRV_HVSP_CLK_CONFIG *)&(_dev_ms_hvsp3.stclk); ++ stSclCfg.stCropWin.bEn = stIOSclCfg.bCropEn; ++ stSclCfg.stCropWin.u16Height = stIOSclCfg.stCropWin.u16Height; ++ stSclCfg.stCropWin.u16Width = stIOSclCfg.stCropWin.u16Width; ++ stSclCfg.stCropWin.u16X = stIOSclCfg.stCropWin.u16X; ++ stSclCfg.stCropWin.u16Y = stIOSclCfg.stCropWin.u16Y; ++ stSclCfg.u16Dsp_Height = stIOSclCfg.u16Dsp_Height; ++ stSclCfg.u16Dsp_Width = stIOSclCfg.u16Dsp_Width; ++ stSclCfg.u16Src_Height = stIOSclCfg.u16Src_Height; ++ stSclCfg.u16Src_Width = stIOSclCfg.u16Src_Width; ++ } ++ } ++ if(_ms_hvsp3_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG, (void *)&stSclCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetScalingConfig(E_MDRV_HVSP_ID_3, &stSclCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp3_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_HVSP_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_hvsp3_io_get_inform_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_HVSP_SCINFORM_CONFIG stIOInfoCfg; ++ ST_MDRV_HVSP_SCINFORM_CONFIG stInfoCfg; ++ int ret = 0; ++ if(!MDrv_HVSP_GetSCLInform(E_MDRV_HVSP_ID_3, &stInfoCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ memcpy(&stIOInfoCfg, &stInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG)); ++ if(copy_to_user((ST_IOCTL_HVSP_SCINFORM_CONFIG __user *)arg, &stIOInfoCfg, sizeof(ST_IOCTL_HVSP_SCINFORM_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_hvsp3_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_HVSP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[HVSP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_HVSP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_HVSP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[HVSP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_HVSP_VERSION_CONFIG), ++ (((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_HVSP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_HVSP_VERSION); ++ stCfg.u32Version = IOCTL_HVSP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_HVSP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_HVSP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[HVSP] No Header !!! \n"); ++ SCL_ERR( "[HVSP]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++int _mdrv_ms_hvsp3_io_set_osd_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_HVSP_OSD_CONFIG stOSDCfg; ++ ST_IOCTL_HVSP_OSD_CONFIG stIOOSDCfg; ++ int ret = 0; ++ ST_MDRV_HVSP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_hvsp3_io_fill_versionchkstruct(sizeof(ST_IOCTL_HVSP_OSD_CONFIG), ++ (((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_HVSP_OSD_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_hvsp3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[HVSP3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOOSDCfg, (__user ST_IOCTL_HVSP_OSD_CONFIG *)arg, sizeof(ST_IOCTL_HVSP_OSD_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stOSDCfg.enOSD_loc = (EN_MDRV_HVSP_OSD_LOC_TYPE)stIOOSDCfg.enOSD_loc; ++ stOSDCfg.stOsdOnOff.bOSDEn = stIOOSDCfg.bEn; ++ } ++ } ++ if(_ms_hvsp3_multiinstSet(E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG, (void *)&stOSDCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_HVSP_SetOSDConfig(E_MDRV_HVSP_ID_3, &stOSDCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_hvsp3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_hvsp3.refCnt <= 0) ++ { ++ SCL_ERR( "[HVSP3] HVSP3IO_IOCTL refCnt =%d!!! \n", _dev_ms_hvsp3.refCnt); ++ return -EFAULT; ++ } ++ ++ /* check u32Cmd valid */ ++ if(IOCTL_HVSP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_HVSP_MAX_NR) ++ { ++ SCL_ERR( "[HVSP3] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP3] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[HVSP3] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_HVSP_SET_IN_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_input_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OUT_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_output_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_SCALING_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_scaling_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_SET_OSD_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_set_osd_config(filp, u32Arg); ++ break; ++ case IOCTL_HVSP_SET_FB_MANAGE_CONFIG: ++ case IOCTL_HVSP_REQ_MEM_CONFIG: ++ case IOCTL_HVSP_SET_MISC_CONFIG: ++ case IOCTL_HVSP_SET_POST_CROP_CONFIG: ++ SCL_ERR( "[HVSP2] Not Support IOCTL %x\n ",u32Cmd); ++ retval = -EINVAL; ++ break; ++ case IOCTL_HVSP_GET_INFORM_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_get_inform_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_HVSP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_hvsp3_io_get_version(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[HVSP3] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_hvsp3_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[SCLDMA1]start %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = (wait_queue_head_t *)MDrv_HVSP_GetWaitQueueHead(); ++ MDrv_HVSP_SetPollWait(filp, pWaitQueueHead, wait); ++ if(MDrv_HVSP_GetCMDQDoneStatus(E_MDRV_HVSP_ID_3)) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_hvsp3_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s:%d\n",__FUNCTION__,__LINE__); ++//mod init ++ if(_dev_ms_hvsp3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp3.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP3] Unable to get major %d\n", _dev_ms_hvsp3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp3.cdev, &_dev_ms_hvsp3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp3.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp3_class = msys_get_sysfs_class(); ++ if(!m_hvsp3_class) ++ { ++ m_hvsp3_class = class_create(THIS_MODULE, hvsp3_classname); ++ } ++ if(IS_ERR(m_hvsp3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_hvsp3.devicenode = device_create(m_hvsp3_class, NULL, dev,NULL, "mhvsp3"); ++ _dev_ms_hvsp3.devicenode->dma_mask=&ms_hvsp3_dma_mask; ++ _dev_ms_hvsp3.devicenode->coherent_dma_mask=ms_hvsp3_dma_mask; ++ } ++ ++//probe ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ stHVSPInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stHVSPInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_3, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_hvsp3_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_hvsp3.stclk.idclk = of_clk_get(st_ms_hvsp3_device.dev.of_node,0); ++ _dev_ms_hvsp3.stclk.fclk1 = of_clk_get(st_ms_hvsp3_device.dev.of_node,1); ++ _dev_ms_hvsp3.stclk.fclk2 = of_clk_get(st_ms_hvsp3_device.dev.of_node,2); ++ _dev_ms_hvsp3.stclk.odclk = of_clk_get(st_ms_hvsp3_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_hvsp3.stclk.idclk) || IS_ERR(_dev_ms_hvsp3.stclk.fclk1) ++ || IS_ERR(_dev_ms_hvsp3.stclk.fclk2)|| IS_ERR(_dev_ms_hvsp3.stclk.odclk)) ++ { ++ SCL_ERR( "[HVSP3] Can't Get CLK\n"); ++ return 0 ; ++ } ++ //sysfs_create_link(&pdev->dev.parent->kobj, &pdev->dev.kobj, "mhvsp3"); ++ device_create_file(_dev_ms_hvsp3.devicenode, &dev_attr_osd); ++ device_create_file(_dev_ms_hvsp3.devicenode, &dev_attr_SCIQ); ++ gbProbeAlready |= EN_DBG_HVSP3_CONFIG; ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3); ++ return 0; ++} ++static int mdrv_ms_hvsp3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_HVSP3_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_HVSP_Exit(1); ++ } ++ else ++ { ++ MDrv_HVSP_Exit(0); ++ } ++ cdev_del(&_dev_ms_hvsp3.cdev); ++ device_destroy(m_hvsp3_class, MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor)); ++ class_destroy(m_hvsp3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ return 0; ++} ++ ++#else ++ ++static int mdrv_ms_hvsp3_probe(struct platform_device *pdev) ++{ ++ ++ ST_MDRV_HVSP_INIT_CONFIG stHVSPInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ stHVSPInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_HVSP_Init(E_MDRV_HVSP_ID_3, &stHVSPInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3); ++ ++ return 0; ++} ++ ++static int mdrv_ms_hvsp3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ return 0; ++} ++ ++#endif ++static int mdrv_ms_hvsp3_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Suspend(E_MDRV_HVSP_ID_3, &stHvspSuspendResumeCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++static int mdrv_ms_hvsp3_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet ; ++ ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG stHvspSuspendResumeCfg; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ stHvspSuspendResumeCfg.u32IRQNum = 0xFFFFFFFF; ++ stHvspSuspendResumeCfg.u32CMDQIRQNum = 0xFFFFFFFF; ++ if(MDrv_HVSP_Resume(E_MDRV_HVSP_ID_3, &stHvspSuspendResumeCfg)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP1] %s: Fail\n",__FUNCTION__); ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++int mdrv_ms_hvsp3_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_hvsp3.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ ++ } ++ if(!ret) ++ { ++ _dev_ms_hvsp3.refCnt++; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_hvsp3_release(struct inode *inode, struct file *filp) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_HVSP3, filp->private_data); ++ ++ _dev_ms_hvsp3.refCnt--; ++ SCL_ASSERT(_dev_ms_hvsp3.refCnt>=0); ++ if(_dev_ms_hvsp3.refCnt == 0) ++ { ++ MDrv_HVSP_Release(E_MDRV_HVSP_ID_3); ++ } ++ //free_irq(INT_IRQ_HVSP3W, MDrv_HVSP3W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_hvsp3_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_hvsp3_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_HVSP3_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[HVSP3] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[HVSP3] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_hvsp3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++} ++ ++#else ++int _mdrv_ms_hvsp3_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_hvsp3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_hvsp3.s32Minor, MDRV_MS_HVSP_DEVICE_COUNT, MDRV_MS_HVSP_NAME); ++ _dev_ms_hvsp3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[HVSP3] Unable to get major %d\n", _dev_ms_hvsp3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_hvsp3.cdev, &_dev_ms_hvsp3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_hvsp3.cdev, dev, MDRV_MS_HVSP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[HVSP3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_HVSP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_hvsp3_class = class_create(THIS_MODULE, hvsp3_classname); ++ if(IS_ERR(m_hvsp3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_hvsp3_class, NULL, dev,NULL, "mhvsp3"); ++ } ++ ++ /* initial the whole HVSP3 Driver */ ++ ret = platform_driver_register(&st_ms_hvsp3_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_hvsp3_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++ SCL_ERR( "[HVSP3] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++void _mdrv_ms_hvsp3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP3] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_hvsp3.cdev); ++ device_destroy(m_hvsp3_class, MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor)); ++ class_destroy(m_hvsp3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_hvsp3.s32Major, _dev_ms_hvsp3.s32Minor), MDRV_MS_HVSP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_hvsp3_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_hvsp3_init); ++module_exit(_mdrv_ms_hvsp3_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms hvsp3 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_pnl_io.c b/drivers/mstar/scl/infinity3/mdrv_pnl_io.c +new file mode 100644 +index 00000000..9ed60ef7 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_pnl_io.c +@@ -0,0 +1,664 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "ms_msys.h" ++ ++#include "mdrv_pnl_io_st.h" ++#include "mdrv_pnl_io.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_pnl.h" ++#include "mdrv_verchk.h" ++#include "MsTypes.h" ++#include "halpnl_utility.h" ++ ++#define MDRV_MS_PNL_DEVICE_COUNT 1 ++#define MDRV_MS_PNL_NAME "mpnl" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_PNL "mpnl" ++#define MDRV_MAJOR_PNL 0xea ++#define MDRV_MINOR_PNL 0x08 ++ ++#define CMD_PARSING(x) (x==IOCTL_PNL_SET_TIMING_CONFIG ? "IOCTL_PNL_SET_TIMING_CONFIG" : \ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_pnl_open(struct inode *inode, struct file *filp); ++int mdrv_ms_pnl_release(struct inode *inode, struct file *filp); ++long mdrv_ms_pnl_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_pnl_probe(struct platform_device *pdev); ++static int mdrv_ms_pnl_remove(struct platform_device *pdev); ++static int mdrv_ms_pnl_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_pnl_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_pnl_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ struct device *devicenode; ++}ST_DEV_PNL; ++ ++static ST_DEV_PNL _dev_ms_pnl = ++{ ++ .s32Major = MDRV_MAJOR_PNL, ++ .s32Minor = MDRV_MINOR_PNL, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_PNL, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_pnl_open, ++ .release = mdrv_ms_pnl_release, ++ .unlocked_ioctl = mdrv_ms_pnl_ioctl, ++ .poll = mdrv_ms_pnl_poll, ++ } ++}; ++ ++static struct class * m_pnl_class = NULL; ++static char * pnl_classname = "m_pnl_class"; ++ ++ ++static const struct of_device_id ms_pnl_of_match_table[] = ++{ ++ { .compatible = "mstar,pnl" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_pnl_driver = ++{ ++ .probe = mdrv_ms_pnl_probe, ++ .remove = mdrv_ms_pnl_remove, ++ .suspend = mdrv_ms_pnl_suspend, ++ .resume = mdrv_ms_pnl_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_PNL, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_pnl_of_match_table), ++ }, ++}; ++#if (!CONFIG_OF) ++static u64 ms_pnl_dma_mask = 0xffffffffUL; ++static struct platform_device st_ms_pnl_device = ++{ ++ .name = "mpnl", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_pnl_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ ++//---------------------------------------------------------------------------------------------- ++int _mdrv_ms_pnl_io_set_timing_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_PNL_TIMING_CONFIG stCfg; ++ ++ if ( CHK_VERCHK_HEADER( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version), IOCTL_PNL_VERSION) ) ++ { ++ ++ VERCHK_ERR("[PNL] Version(%04x) < %04x!!! \n", ++ ((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_PNL_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCLT_PNL_TIMING_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[PNL] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCLT_PNL_TIMING_CONFIG), ++ (((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, &(((__user ST_IOCLT_PNL_TIMING_CONFIG *)arg)->u16Vsync_St), sizeof(ST_MDRV_PNL_TIMING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[PNL] No Header !!! \n"); ++ ++ if(copy_from_user(&stCfg, (__user ST_MDRV_PNL_TIMING_CONFIG *)arg, sizeof(ST_MDRV_PNL_TIMING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[PNL] Size(%04d) \n",(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size) ); ++ ++ ++ if(!MDrv_PNL_Set_Timing_Config(&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_pnl_io_set_lpll_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_PNL_TIMING_CONFIG stCfg; ++ ++ if ( CHK_VERCHK_HEADER( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version), IOCTL_PNL_VERSION) ) ++ { ++ ++ VERCHK_ERR("[PNL] Version(%04x) < %04x!!! \n", ++ ((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_PNL_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCLT_PNL_TIMING_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[PNL] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCLT_PNL_TIMING_CONFIG), ++ (((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size)); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, &(((__user ST_IOCLT_PNL_TIMING_CONFIG *)arg)->u16Vsync_St), sizeof(ST_MDRV_PNL_TIMING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[PNL] No Header !!! \n"); ++ ++ if(copy_from_user(&stCfg, (__user ST_MDRV_PNL_TIMING_CONFIG *)arg, sizeof(ST_MDRV_PNL_TIMING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[PNL] Size(%04d) \n",(((ST_IOCLT_PNL_TIMING_CONFIG __user *)arg)->VerChk_Size) ); ++ ++ if(!MDrv_PNL_Set_LPLL_Config(&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_pnl_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_VERSION_LESS( &(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_PNL_VERSION) ) ++ { ++ ++ VERCHK_ERR("[PNL] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_PNL_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_PNL_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[PNL] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_PNL_VERSION_CONFIG), ++ (((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_PNL_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_PNL_VERSION); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[PNL] Size(%04d) \n",(((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg)->VerChk_Size) ); ++ stCfg.u32Version = IOCTL_PNL_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_PNL_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_PNL_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[PNL] No Header !!! \n"); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++ ++//============================================================================== ++long mdrv_ms_pnl_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_pnl.refCnt <= 0) ++ { ++ SCL_ERR( "[PNL] PNLIO_IOCTL refCnt =%d!!! \n", _dev_ms_pnl.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_PNL_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_PNL_MAX_NR) ++ { ++ SCL_ERR( "[PNL] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[PNL] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_LCD, "[PNL] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_PNL_SET_TIMING_CONFIG: ++ retval = _mdrv_ms_pnl_io_set_timing_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_PNL_SET_LPLL_CONFIG: ++ retval = _mdrv_ms_pnl_io_set_lpll_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_PNL_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_pnl_io_get_version(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[PNL] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_pnl_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ++ return 0; ++} ++#if CONFIG_OF ++static int mdrv_ms_pnl_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_PNL_INIT_CONFIG stPnlInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ if(_dev_ms_pnl.s32Major) ++ { ++ dev = MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_pnl.s32Minor, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ _dev_ms_pnl.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[PNL] Unable to get major %d\n", _dev_ms_pnl.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_pnl.cdev, &_dev_ms_pnl.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_pnl.cdev, dev, MDRV_MS_PNL_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[PNL] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_pnl_class = msys_get_sysfs_class(); ++ if(!m_pnl_class) ++ { ++ m_pnl_class = class_create(THIS_MODULE, pnl_classname); ++ } ++ if(IS_ERR(m_pnl_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_pnl.devicenode =device_create(m_pnl_class, NULL, dev,NULL, "mpnl"); ++ } ++ stPnlInitCfg.u32RiuBase = 0x1F000000; ++ if(of_property_read_u32(pdev->dev.of_node, "jtag-mode", &gu32JTAGmode)) ++ { ++ printk(KERN_WARNING "[PNL] Failed to read jtag-mode property, default on/n"); ++ gu32JTAGmode = 1; //if can't get, default off ++ } ++ if(MDrv_PNL_Init(&stPnlInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ gbProbeAlready |= EN_DBG_PNL_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_pnl_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_PNL_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_PNL_Exit(1); ++ } ++ else ++ { ++ MDrv_PNL_Exit(0); ++ } ++ cdev_del(&_dev_ms_pnl.cdev); ++ device_destroy(m_pnl_class, MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor)); ++ class_destroy(m_pnl_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor), MDRV_MS_PNL_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_pnl_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_PNL_INIT_CONFIG stPnlInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ stPnlInitCfg.u32RiuBase = 0x1F000000; ++ if(MDrv_PNL_Init(&stPnlInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++static int mdrv_ms_pnl_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_pnl_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ return 0; ++} ++ ++ ++static int mdrv_ms_pnl_resume(struct platform_device *dev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ MDrv_PNL_Resume(); ++ return 0; ++} ++ ++ ++int mdrv_ms_pnl_open(struct inode *inode, struct file *filp) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_pnl.refCnt>=0); ++ _dev_ms_pnl.refCnt++; ++ ++ ++ ++ return 0; ++} ++ ++ ++int mdrv_ms_pnl_release(struct inode *inode, struct file *filp) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ _dev_ms_pnl.refCnt--; ++ SCL_ASSERT(_dev_ms_pnl.refCnt>=0); ++ if(_dev_ms_pnl.refCnt==0) ++ { ++ MDrv_PNL_Release(); ++ } ++ //free_irq(INT_IRQ_PNLW, MDrv_PNLW_isr); ++ ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_pnl_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_pnl_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_PNL_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[PNL] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[PNL] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_pnl_driver); ++ } ++ ++ return ret; ++} ++void _mdrv_ms_pnl_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_pnl_driver); ++} ++#else ++int _mdrv_ms_pnl_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_pnl.s32Major) ++ { ++ dev = MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_pnl.s32Minor, MDRV_MS_PNL_DEVICE_COUNT, MDRV_MS_PNL_NAME); ++ _dev_ms_pnl.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[PNL] Unable to get major %d\n", _dev_ms_pnl.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_pnl.cdev, &_dev_ms_pnl.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_pnl.cdev, dev, MDRV_MS_PNL_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[PNL] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_PNL_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_pnl_class = class_create(THIS_MODULE, pnl_classname); ++ if(IS_ERR(m_pnl_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_pnl_class, NULL, dev,NULL, "mpnl"); ++ } ++ ++ /* initial the whole PNL Driver */ ++ ret = platform_driver_register(&st_ms_pnl_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_pnl_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_pnl_driver); ++ SCL_ERR( "[PNL] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_pnl_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[PNL] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_pnl.cdev); ++ device_destroy(m_pnl_class, MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor)); ++ class_destroy(m_pnl_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_pnl.s32Major, _dev_ms_pnl.s32Minor), MDRV_MS_PNL_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_pnl_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_pnl_init); ++module_exit(_mdrv_ms_pnl_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms pnl ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_scldma1_io.c b/drivers/mstar/scl/infinity3/mdrv_scldma1_io.c +new file mode 100644 +index 00000000..20d17bbf +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_scldma1_io.c +@@ -0,0 +1,1402 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_msys.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++#include "mdrv_scldma_io_i3_st.h" ++#include "mdrv_scldma_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma1" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma1" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x04 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG ? "IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG" :\ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_scldma1_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma1_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma1_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma1_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma1_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma1_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma1_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma1 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma1_open, ++ .release = mdrv_ms_scldma1_release, ++ .unlocked_ioctl = mdrv_ms_scldma1_ioctl, ++ .poll = mdrv_ms_scldma1_poll, ++ } ++}; ++ ++static struct class * m_scldma1_class = NULL; ++static char * scldma1_classname = "m_scldma1_class"; ++ ++static const struct of_device_id ms_scldma1_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma1" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma1_driver = ++{ ++ .probe = mdrv_ms_scldma1_probe, ++ .remove = mdrv_ms_scldma1_remove, ++ .suspend = mdrv_ms_scldma1_suspend, ++ .resume = mdrv_ms_scldma1_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma1_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma1_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma1_device = ++{ ++ .name = "mscldma1", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma1_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++ ++static ssize_t check_snp_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_SNP,0); ++} ++static ssize_t check_snp_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_SNP,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_SNP,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_SNP,0,0); ++ } ++ return n; ++ } ++ return 0; ++} ++static DEVICE_ATTR(cksnp,0600, check_snp_show, check_snp_store); ++ ++ ++static ssize_t check_frm_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_FRM,0); ++} ++static ssize_t check_frm_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >ptgen_call ++ { ++ SCL_ERR( "All dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountAllClient(); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_FRM,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_1,E_MDRV_SCLDMA_MEM_FRM,0,0); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm,0600, check_frm_show, check_frm_store); ++static ssize_t check_db_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ //out =0,in=1 ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "Double buffer Status:%hhd\n",MDrv_SCLDMA_GetDoubleBufferStatus()); ++ return (p8StrBuf - buf); ++} ++static ssize_t check_db_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 >ptgen_call ++ { ++ SCL_ERR( "DB default ON %d\n",(int)*str); ++ MDrv_SCLDMA_SetDoubleBufferConfig(1); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "DB default OFF %d\n",(int)*str); ++ MDrv_SCLDMA_SetDoubleBufferConfig(0); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(db,0600, check_db_show, check_db_store); ++void _mdrv_ms_scldma1_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_scldma1_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA1] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA1] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[SCLDMA1] Size(%d) \n",stVersion->u32StructSize ); ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA1] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++static int _ms_scldma1_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_set_in_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA1] not support IOCTL_SCLDMA_SET_IN_BUFFER_CONFIGn"); ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma1_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA1] not support IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG"); ++ ++ return -EFAULT; ++} ++void _mdrv_ms_scldma1_io_fillbufferconfig(ST_IOCTL_SCLDMA_BUFFER_CONFIG *stIODMABufferCfg,ST_MDRV_SCLDMA_BUFFER_CONFIG *stDMABufferCfg) ++{ ++ stDMABufferCfg->u8Flag = stIODMABufferCfg->u8Flag; ++ stDMABufferCfg->enBufMDType = (EN_MDRV_SCLDMA_BUFFER_MODE_TYPE)stIODMABufferCfg->enBufMDType; ++ stDMABufferCfg->enColorType = (EN_MDRV_SCLDMA_COLOR_TYPE)stIODMABufferCfg->enColorType; ++ stDMABufferCfg->enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIODMABufferCfg->enMemType; ++ stDMABufferCfg->u16BufNum = stIODMABufferCfg->u16BufNum; ++ stDMABufferCfg->u16Height = stIODMABufferCfg->u16Height; ++ stDMABufferCfg->u16Width = stIODMABufferCfg->u16Width; ++ memcpy(stDMABufferCfg->u32Base_Y,stIODMABufferCfg->u32Base_Y,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_C,stIODMABufferCfg->u32Base_C,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_V,stIODMABufferCfg->u32Base_V,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ ++} ++ ++int _mdrv_ms_scldma1_io_set_out_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg; ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ _mdrv_ms_scldma1_io_fillbufferconfig(&stIODMABufferCfg,&stDMABufferCfg); ++ } ++ } ++ ++ if(_ms_scldma1_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientConfig(E_MDRV_SCLDMA_ID_1, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (__user ST_IOCTL_SCLDMA_TRIGGER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOTrigCfg.enMemType; ++ } ++ } ++ ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma1.stclk); ++ if(_ms_scldma1_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientTrigger(E_MDRV_SCLDMA_ID_1, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx = 0; ++ ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ MsOS_Memset(&stDmaInfo,0,sizeof(ST_MDRV_SCLDMA_ATTR_TYPE)); ++ MsOS_Memset(&stIOGetCfg,0,sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG)); ++ _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (__user ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_FRM,0,&stDmaInfo); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_SNP) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_SNP,0,&stDmaInfo); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_IMI) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_IMI,0,&stDmaInfo); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = (EN_IOCTL_SCLDMA_BUFFER_MODE_TYPE)stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = (EN_IOCTL_SCLDMA_COLOR_TYPE)stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32BufferidxVerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = (EN_MDRV_SCLDMA_USED_BUFFER_QUEUE_TYPE)stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_1, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, ++ &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (__user ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma1.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx(E_MDRV_SCLDMA_ID_1, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = (EN_IOCTL_SCLDMA_MEM_TYPE)stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u64FRMDoneTime = stActiveCfg.u64FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma1_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma1_io_set_lock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ signed long *ps32PrivateID = NULL; ++ MsOS_Memset(&stCfg,0,sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG)); ++ _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_SCLDMA_LOCK_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.u8BufSize == 0 || stCfg.u8BufSize>10) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.ps32IdBuf == NULL) ++ { ++ SCL_ERR( "[SCLDMA1] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ else ++ { ++ ps32PrivateID = MsOS_VirMemalloc(stCfg.u8BufSize * sizeof(signed long)); ++ if(ps32PrivateID == NULL) ++ { ++ SCL_ERR( "[SCLDMA1] not free alloc buffer"); ++ return -EFAULT; ++ } ++ if(copy_from_user(ps32PrivateID, (__user signed long *)stCfg.ps32IdBuf, stCfg.u8BufSize*sizeof(signed long))) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++#if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ SCL_ERR( "[SCLDMA1]%s ps32PrivateID:%lx %lx %lx\n",__FUNCTION__,(MS_U32)ps32PrivateID,*ps32PrivateID,*(ps32PrivateID+1)); ++#endif ++ } ++ stMultiInstLockCfg.ps32PrivateID = ps32PrivateID; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ if( !MDrv_MultiInst_Lock_Alloc(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2, &stMultiInstLockCfg) ) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EINVAL; ++ } ++ MsOS_VirMemFree(ps32PrivateID); ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma1_io_set_unlock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ signed long *ps32PrivateID = NULL; ++ MsOS_Memset(&stCfg,0,sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG)); ++ _mdrv_ms_scldma1_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma1_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA1] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_SCLDMA_LOCK_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.u8BufSize == 0 || stCfg.u8BufSize>10) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.ps32IdBuf == NULL) ++ { ++ SCL_ERR( "[SCLDMA1] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ else ++ { ++ ps32PrivateID = MsOS_VirMemalloc(stCfg.u8BufSize * sizeof(signed long)); ++ if(ps32PrivateID == NULL) ++ { ++ SCL_ERR( "[SCLDMA1] not free alloc buffer"); ++ return -EFAULT; ++ } ++ if(copy_from_user(ps32PrivateID, (__user signed long *)stCfg.ps32IdBuf, stCfg.u8BufSize*sizeof(signed long))) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++#if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ SCL_ERR( "[SCLDMA1]%s ps32PrivateID:%lx %lx %lx\n",__FUNCTION__,(MS_U32)ps32PrivateID,*ps32PrivateID,*(ps32PrivateID+1)); ++#endif ++ } ++ stMultiInstLockCfg.ps32PrivateID = ps32PrivateID; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2, &stMultiInstLockCfg) ) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++ MsOS_VirMemFree(ps32PrivateID); ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma1_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, ++ &stCfg, sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma1_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma1.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA1] SCLDMA1IO_IOCTL refCnt =%d!!! \n", _dev_ms_scldma1.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA1] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ if(u32Cmd == IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ++ || u32Cmd == IOCTL_SCLDMA_GET_VERSION_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1, "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1HLEVEL, ++ "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma1_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_information_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_lock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ retval = _mdrv_ms_scldma1_io_set_unlock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma1_io_get_version(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA1] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma1_poll(struct file *filp, struct poll_table_struct *pstPollQueue) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMDone; ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = (wait_queue_head_t *)MDrv_SCLDMA_GetWaitQueueHead(E_MDRV_SCLDMA_ID_1); ++ MDrv_SCLDMA_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++ if(MDrv_SCLDMA_GetOutBufferDoneEvent(E_MDRV_SCLDMA_ID_1, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMDone = (stDoneCfg.bDone == 0x1 )? 0x1 : ++ (stDoneCfg.bDone == 0x2 )? 0x2 : ++ (stDoneCfg.bDone == 0x3 )? 0x3 : ++ (stDoneCfg.bDone == 0xF ) ? 0xF : 0; ++ } ++ else ++ { ++ bFRMDone = 0; ++ } ++ if(bFRMDone &&bFRMDone!=0xF) ++ { ++ if(bFRMDone& 0x1) ++ { ++ ret |= POLLIN; /* read */ ++ } ++ if(bFRMDone& 0x2) ++ { ++ ret |= POLLPRI; ++ } ++ } ++ else if(bFRMDone ==0) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = POLLERR; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC1HLEVEL, "[SCLDMA1] %s ret=%x\n",__FUNCTION__,ret); ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma1.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA1] Unable to get major %d\n", _dev_ms_scldma1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma1.cdev, &_dev_ms_scldma1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma1.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma1_class = msys_get_sysfs_class(); ++ if(!m_scldma1_class) ++ { ++ m_scldma1_class = class_create(THIS_MODULE, scldma1_classname); ++ } ++ if(IS_ERR(m_scldma1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma1.devicenode =device_create(m_scldma1_class, NULL, dev,NULL, "mscldma1"); ++ _dev_ms_scldma1.devicenode->dma_mask=&ms_scldma1_dma_mask; ++ _dev_ms_scldma1.devicenode->coherent_dma_mask=ms_scldma1_dma_mask; ++ } ++ //probe ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stSCLDMAInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stSCLDMAInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_1, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ st_ms_scldma1_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma1.stclk.idclk = of_clk_get(st_ms_scldma1_device.dev.of_node,0); ++ _dev_ms_scldma1.stclk.fclk1 = of_clk_get(st_ms_scldma1_device.dev.of_node,1); ++ _dev_ms_scldma1.stclk.fclk2 = of_clk_get(st_ms_scldma1_device.dev.of_node,2); ++ _dev_ms_scldma1.stclk.odclk = of_clk_get(st_ms_scldma1_device.dev.of_node,3); ++ if (IS_ERR(_dev_ms_scldma1.stclk.idclk) || IS_ERR(_dev_ms_scldma1.stclk.fclk1) || IS_ERR(_dev_ms_scldma1.stclk.fclk2)) ++ { ++ SCL_ERR( "[SCLDMA1] Can't Get CLK\n"); ++ return 0 ; ++ } ++ ++ //create device ++ if (device_create_file(_dev_ms_scldma1.devicenode, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(_dev_ms_scldma1.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma1.devicenode, &dev_attr_cksnp)!= 0) ++ { ++ dev_err(_dev_ms_scldma1.devicenode, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma1.devicenode, &dev_attr_db)!= 0) ++ { ++ dev_err(_dev_ms_scldma1.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ gbProbeAlready |= EN_DBG_SCLDMA1_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma1_remove(struct platform_device *pdev) ++{ ++ SCL_ERR( "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma1.stclk)); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_SCLDMA1_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_SCLDMA_Exit(1); ++ } ++ else if(!(gbProbeAlready& (EN_DBG_SCLDMA1_CONFIG|EN_DBG_SCLDMA2_CONFIG|EN_DBG_SCLDMA3_CONFIG|EN_DBG_SCLDMA4_CONFIG))) ++ { ++ MDrv_SCLDMA_Exit(0); ++ } ++ cdev_del(&_dev_ms_scldma1.cdev); ++ device_destroy(m_scldma1_class, MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor)); ++ class_destroy(m_scldma1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma1_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_1, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ //clk enable ++ ++ //create device ++ ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_cksnp)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ return 0; ++} ++ ++static int mdrv_ms_scldma1_remove(struct platform_device *pdev) ++{ ++ SCL_ERR( "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma1.stclk)); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma1_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_1)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma1.stclk)); ++ MDrv_SCLDMA_Sys_Init(0); ++ ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++static int mdrv_ms_scldma1_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_1)) ++ { ++ MDrv_SCLDMA_Sys_Init(1); ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma1_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma1.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ if(_dev_ms_scldma1.refCnt==0) ++ { ++ MDrv_SCLDMA_Sys_Init(1); ++ } ++ if(!ret) ++ { ++ _dev_ms_scldma1.refCnt++; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma1_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_1_2, NULL); ++ filp->private_data = NULL; ++ ++ _dev_ms_scldma1.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma1.refCnt>=0); ++ if(_dev_ms_scldma1.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_1,&(_dev_ms_scldma1.stclk)); ++ } ++ //free_irq(INT_IRQ_SCLDMA1W, MDrv_SCLDMA1W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma1_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma1_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA1_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA1] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma1_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma1_driver); ++} ++ ++#else ++int _mdrv_ms_scldma1_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma1.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma1.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma1.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA1] Unable to get major %d\n", _dev_ms_scldma1.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma1.cdev, &_dev_ms_scldma1.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma1.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA1] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma1_class = class_create(THIS_MODULE, scldma1_classname); ++ if(IS_ERR(m_scldma1_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma1_class, NULL, dev,NULL, "mscldma1"); ++ } ++ ++ /* initial the whole SCLDMA1 Driver */ ++ ret = platform_driver_register(&st_ms_scldma1_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma1_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma1_driver); ++ SCL_ERR( "[SCLDMA1] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma1_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA1] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma1.cdev); ++ device_destroy(m_scldma1_class, MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor)); ++ class_destroy(m_scldma1_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma1.s32Major, _dev_ms_scldma1.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma1_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_scldma1_init); ++module_exit(_mdrv_ms_scldma1_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma1 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_scldma2_io.c b/drivers/mstar/scl/infinity3/mdrv_scldma2_io.c +new file mode 100644 +index 00000000..82953d41 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_scldma2_io.c +@@ -0,0 +1,1220 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include "ms_msys.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++#include "mdrv_scldma_io_i3_st.h" ++#include "mdrv_scldma_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma2" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma2" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x05 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ "UNKNOWN") ++ ++int mdrv_ms_scldma2_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma2_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma2_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma2_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma2_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma2_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma2_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma2 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma2_open, ++ .release = mdrv_ms_scldma2_release, ++ .unlocked_ioctl = mdrv_ms_scldma2_ioctl, ++ .poll = mdrv_ms_scldma2_poll, ++ } ++}; ++ ++static struct class * m_scldma2_class = NULL; ++static char * scldma2_classname = "m_scldma2_class"; ++ ++ ++static const struct of_device_id ms_scldma2_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma2" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma2_driver = ++{ ++ .probe = mdrv_ms_scldma2_probe, ++ .remove = mdrv_ms_scldma2_remove, ++ .suspend = mdrv_ms_scldma2_suspend, ++ .resume = mdrv_ms_scldma2_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma2_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma2_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma2_device = ++{ ++ .name = "mscldma2", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma2_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_frm_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM,0); ++} ++static ssize_t check_frm_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM,0,0); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm,0600, check_frm_show, check_frm_store); ++static ssize_t check_frm2_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM2,0); ++} ++static ssize_t check_frm2_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM2,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM2,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_2,E_MDRV_SCLDMA_MEM_FRM2,0,0); ++ } ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm2,0600, check_frm2_show, check_frm2_store); ++ ++void _mdrv_ms_scldma2_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_scldma2_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA2] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA2] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA2] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++static int _ms_scldma2_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++void _mdrv_ms_scldma2_io_fillbufferconfig(ST_IOCTL_SCLDMA_BUFFER_CONFIG *stIODMABufferCfg,ST_MDRV_SCLDMA_BUFFER_CONFIG *stDMABufferCfg) ++{ ++ stDMABufferCfg->u8Flag = stIODMABufferCfg->u8Flag; ++ stDMABufferCfg->enBufMDType = (EN_MDRV_SCLDMA_BUFFER_MODE_TYPE)stIODMABufferCfg->enBufMDType; ++ stDMABufferCfg->enColorType = (EN_MDRV_SCLDMA_COLOR_TYPE)stIODMABufferCfg->enColorType; ++ stDMABufferCfg->enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIODMABufferCfg->enMemType; ++ stDMABufferCfg->u16BufNum = stIODMABufferCfg->u16BufNum; ++ stDMABufferCfg->u16Height = stIODMABufferCfg->u16Height; ++ stDMABufferCfg->u16Width = stIODMABufferCfg->u16Width; ++ memcpy(stDMABufferCfg->u32Base_Y,stIODMABufferCfg->u32Base_Y,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_C,stIODMABufferCfg->u32Base_C,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_V,stIODMABufferCfg->u32Base_V,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++} ++ ++int _mdrv_ms_scldma2_io_set_in_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA2] not support IOCTL_SCLDMA_SET_IN_BUFFER_CONFIGn"); ++ ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma2_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ++ SCL_ERR( "[SCLDMA2] not support IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG"); ++ return -EFAULT; ++} ++ ++int _mdrv_ms_scldma2_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ MsOS_Memset(&stDmaInfo,0,sizeof(ST_MDRV_SCLDMA_ATTR_TYPE)); ++ MsOS_Memset(&stIOGetCfg,0,sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG)); ++ if(_mdrv_ms_scldma2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (__user ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM,0,&stDmaInfo); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM2) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM2,0,&stDmaInfo); ++ } ++ else if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_IMI) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_IMI,0,&stDmaInfo); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = (EN_IOCTL_SCLDMA_BUFFER_MODE_TYPE)stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = (EN_IOCTL_SCLDMA_COLOR_TYPE)stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32BufferidxVerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ _mdrv_ms_scldma2_io_fillbufferconfig(&stIODMABufferCfg,&stDMABufferCfg); ++ } ++ } ++ if(_ms_scldma2_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientConfig(E_MDRV_SCLDMA_ID_2, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma2_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (__user ST_IOCTL_SCLDMA_TRIGGER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType =(EN_MDRV_SCLDMA_MEM_TYPE) stIOTrigCfg.enMemType; ++ } ++ } ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma2.stclk); ++ if(_ms_scldma2_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientTrigger(E_MDRV_SCLDMA_ID_2, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma2_io_get_in_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA2] not support IOCTL_SCLDMA_GET_ACTIVE_BUFFER_CONFIG"); ++ ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma2_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (__user ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType =(EN_MDRV_SCLDMA_MEM_TYPE) stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma2.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx(E_MDRV_SCLDMA_ID_2, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType =(EN_IOCTL_SCLDMA_MEM_TYPE) stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u64FRMDoneTime = stActiveCfg.u64FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++int _mdrv_ms_scldma2_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data, &stCfg.s32Id)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma2_io_buffer_queue_handle_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG stIOBufferQCfg; ++ ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG stBufferQCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ _mdrv_ms_scldma2_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma2_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA2] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType =(EN_MDRV_SCLDMA_MEM_TYPE) stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType =(EN_MDRV_SCLDMA_USED_BUFFER_QUEUE_TYPE) stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_2, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, ++ &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma2_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, &stCfg, ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma2_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma2.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA2] SCLDMA2IO_IOCTL refCnt =%d!!! \n", _dev_ms_scldma2.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA2] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ if(u32Cmd == IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ++ || u32Cmd == IOCTL_SCLDMA_GET_VERSION_CONFIG || u32Cmd == IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2, "[SCLDMA2] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2HLEVEL, "[SCLDMA2] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ } ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma2_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_information_config(filp, u32Arg); ++ break; ++ ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ SCL_ERR( "[SCLDMA2] Not Support IOCTL %x\n ",u32Cmd); ++ retval = -EINVAL; ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma2_io_get_version(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA2] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma2_poll(struct file *filp, struct poll_table_struct *pstPollQueue) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMDone; ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC2HLEVEL, "[SCLDMA2] %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ pWaitQueueHead = (wait_queue_head_t *)MDrv_SCLDMA_GetWaitQueueHead(E_MDRV_SCLDMA_ID_2); ++ MDrv_SCLDMA_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++ if(MDrv_SCLDMA_GetOutBufferDoneEvent(E_MDRV_SCLDMA_ID_2, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMDone = (stDoneCfg.bDone == 0x1 )? 0x1 : ++ (stDoneCfg.bDone == 0x2 )? 0x2 : ++ (stDoneCfg.bDone == 0x3 )? 0x3 : ++ (stDoneCfg.bDone == 0xF ) ? 0xF : 0; ++ } ++ else ++ { ++ bFRMDone = 0; ++ } ++ if(bFRMDone &&bFRMDone!=0xF) ++ { ++ if(bFRMDone& 0x1) ++ { ++ ret |= POLLIN; /* read */ ++ } ++ if(bFRMDone& 0x2) ++ { ++ ret |= POLLPRI; ++ } ++ } ++ else if(bFRMDone ==0) ++ { ++ ret = 0; ++ } ++ else ++ { ++ ret = POLLERR; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma2.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA2] Unable to get major %d\n", _dev_ms_scldma2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma2.cdev, &_dev_ms_scldma2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma2.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma2_class = msys_get_sysfs_class(); ++ if(!m_scldma2_class) ++ { ++ m_scldma2_class = class_create(THIS_MODULE, scldma2_classname); ++ } ++ if(IS_ERR(m_scldma2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma2.devicenode = device_create(m_scldma2_class, NULL, dev,NULL, "mscldma2"); ++ _dev_ms_scldma2.devicenode->dma_mask=&ms_scldma2_dma_mask; ++ _dev_ms_scldma2.devicenode->coherent_dma_mask=ms_scldma2_dma_mask; ++ } ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stSCLDMAInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stSCLDMAInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_2, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ st_ms_scldma2_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma2.stclk.idclk = of_clk_get(st_ms_scldma2_device.dev.of_node,0); ++ _dev_ms_scldma2.stclk.fclk1 = of_clk_get(st_ms_scldma2_device.dev.of_node,1); ++ _dev_ms_scldma2.stclk.fclk2 = of_clk_get(st_ms_scldma2_device.dev.of_node,2); ++ _dev_ms_scldma2.stclk.odclk = of_clk_get(st_ms_scldma2_device.dev.of_node,3); ++ if (device_create_file(_dev_ms_scldma2.devicenode, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(_dev_ms_scldma2.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma2.devicenode, &dev_attr_ckfrm2)!= 0) ++ { ++ dev_err(_dev_ms_scldma2.devicenode, ++ "Failed to create ckfrm2 sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2); ++ gbProbeAlready |= EN_DBG_SCLDMA2_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma2.stclk)); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_SCLDMA2_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_SCLDMA_Exit(1); ++ } ++ else if(!(gbProbeAlready& (EN_DBG_SCLDMA1_CONFIG|EN_DBG_SCLDMA2_CONFIG|EN_DBG_SCLDMA3_CONFIG|EN_DBG_SCLDMA4_CONFIG))) ++ { ++ MDrv_SCLDMA_Exit(0); ++ } ++ cdev_del(&_dev_ms_scldma2.cdev); ++ device_destroy(m_scldma2_class, MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor)); ++ class_destroy(m_scldma2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma2_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_2, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2); ++ return 0; ++} ++ ++static int mdrv_ms_scldma2_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma2.stclk)); ++ cdev_del(&_dev_ms_scldma2.cdev); ++ device_destroy(m_scldma2_class, MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor)); ++ class_destroy(m_scldma2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma2_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_2)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma2.stclk)); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_scldma2_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_2)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma2_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma2.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ if(!ret) ++ { ++ _dev_ms_scldma2.refCnt++; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma2_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2, filp->private_data); ++ ++ _dev_ms_scldma2.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma2.refCnt>=0); ++ ++ //free_irq(INT_IRQ_SCLDMA2W, MDrv_SCLDMA2W_isr); ++ if(_dev_ms_scldma2.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_2,&(_dev_ms_scldma2.stclk)); ++ } ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma2_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma2_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA2_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA2] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma2_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma2_driver); ++} ++ ++#else ++int _mdrv_ms_scldma2_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma2.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma2.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma2.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA2] Unable to get major %d\n", _dev_ms_scldma2.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma2.cdev, &_dev_ms_scldma2.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma2.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA2] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma2_class = class_create(THIS_MODULE, scldma2_classname); ++ if(IS_ERR(m_scldma2_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma2_class, NULL, dev,NULL, "mscldma2"); ++ } ++ ++ /* initial the whole SCLDMA2 Driver */ ++ ret = platform_driver_register(&st_ms_scldma2_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma2_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma2_driver); ++ SCL_ERR( "[SCLDMA2] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma2_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA2] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma2.cdev); ++ device_destroy(m_scldma2_class, MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor)); ++ class_destroy(m_scldma2_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma2.s32Major, _dev_ms_scldma2.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma2_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_scldma2_init); ++module_exit(_mdrv_ms_scldma2_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma2 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_scldma3_io.c b/drivers/mstar/scl/infinity3/mdrv_scldma3_io.c +new file mode 100644 +index 00000000..8dbbc4f6 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_scldma3_io.c +@@ -0,0 +1,1473 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_msys.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++#include "mdrv_scldma_io_i3_st.h" ++#include "mdrv_scldma_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma3" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma3" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x06 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_scldma3_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma3_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma3_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma3_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma3_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma3_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma3_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma3 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma3_open, ++ .release = mdrv_ms_scldma3_release, ++ .unlocked_ioctl = mdrv_ms_scldma3_ioctl, ++ .poll = mdrv_ms_scldma3_poll, ++ } ++}; ++ ++static struct class * m_scldma3_class = NULL; ++static char * scldma3_classname = "m_scldma3_class"; ++ ++ ++static const struct of_device_id ms_scldma3_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma3" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma3_driver = ++{ ++ .probe = mdrv_ms_scldma3_probe, ++ .remove = mdrv_ms_scldma3_remove, ++ .suspend = mdrv_ms_scldma3_suspend, ++ .resume = mdrv_ms_scldma3_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma3_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma3_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma3_device = ++{ ++ .name = "mscldma3", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma3_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++ ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_frmR_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM,1); ++} ++static ssize_t check_frmR_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,1); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,1,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,1,0); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrmR,0600, check_frmR_show, check_frmR_store); ++ ++ ++static ssize_t check_frmW_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM,0); ++} ++static ssize_t check_frmW_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL!=buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,0); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OPEN %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,0,1); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "dma count FORCE CLOSE OVER %d\n",(int)*str); ++ MDrv_SCLDMA_SetForceCloseDMAClient(E_MDRV_SCLDMA_ID_3,E_MDRV_SCLDMA_MEM_FRM,0,0); ++ } ++ return n; ++ } ++ return 0; ++} ++static DEVICE_ATTR(ckfrmW,0600, check_frmW_show, check_frmW_store); ++void _mdrv_ms_scldma3_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_scldma3_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA3] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA3] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA3] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++static int _ms_scldma3_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ MsOS_Memset(&stDmaInfo,0,sizeof(ST_MDRV_SCLDMA_ATTR_TYPE)); ++ MsOS_Memset(&stIOGetCfg,0,sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG)); ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (__user ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM,0,&stDmaInfo); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = (EN_IOCTL_SCLDMA_BUFFER_MODE_TYPE)stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = (EN_IOCTL_SCLDMA_COLOR_TYPE)stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32Bufferidxu8Flag = stIODMABufferCfg->u8Flag; ++ stDMABufferCfg->enBufMDType = (EN_MDRV_SCLDMA_BUFFER_MODE_TYPE)stIODMABufferCfg->enBufMDType; ++ stDMABufferCfg->enColorType = (EN_MDRV_SCLDMA_COLOR_TYPE)stIODMABufferCfg->enColorType; ++ stDMABufferCfg->enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIODMABufferCfg->enMemType; ++ stDMABufferCfg->u16BufNum = stIODMABufferCfg->u16BufNum; ++ stDMABufferCfg->u16Height = stIODMABufferCfg->u16Height; ++ stDMABufferCfg->u16Width = stIODMABufferCfg->u16Width; ++ memcpy(stDMABufferCfg->u32Base_Y,stIODMABufferCfg->u32Base_Y,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_C,stIODMABufferCfg->u32Base_C,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_V,stIODMABufferCfg->u32Base_V,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++} ++ ++int _mdrv_ms_scldma3_io_set_in_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg; ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ _mdrv_ms_scldma3_io_fillbufferconfig(&stIODMABufferCfg,&stDMABufferCfg); ++ } ++ } ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientConfig(E_MDRV_SCLDMA_ID_3, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_scldma3_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (__user ST_IOCTL_SCLDMA_TRIGGER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOTrigCfg.enMemType; ++ } ++ } ++ ++ stDrvTrigCfg.stclk =& (_dev_ms_scldma3.stclk); ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientTrigger(E_MDRV_SCLDMA_ID_3, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_set_out_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg; ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ _mdrv_ms_scldma3_io_fillbufferconfig(&stIODMABufferCfg,&stDMABufferCfg); ++ } ++ } ++ ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientConfig(E_MDRV_SCLDMA_ID_3, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (__user ST_IOCTL_SCLDMA_TRIGGER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOTrigCfg.enMemType; ++ } ++ } ++ ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma3.stclk); ++ if(_ms_scldma3_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAWriteClientTrigger(E_MDRV_SCLDMA_ID_3, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_in_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (__user ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma3.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAReadBufferActiveIdx(E_MDRV_SCLDMA_ID_3, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = (EN_IOCTL_SCLDMA_MEM_TYPE)stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u64FRMDoneTime = stActiveCfg.u64FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (__user ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma3.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx(E_MDRV_SCLDMA_ID_3, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = (EN_IOCTL_SCLDMA_MEM_TYPE)stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u64FRMDoneTime = stActiveCfg.u64FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_buffer_queue_handle_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG stIOBufferQCfg; ++ ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG stBufferQCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, (__user ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = (EN_MDRV_SCLDMA_USED_BUFFER_QUEUE_TYPE)stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_3, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma3_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma3_io_set_lock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ signed long *ps32PrivateID = NULL; ++ MsOS_Memset(&stCfg,0,sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG)); ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_SCLDMA_LOCK_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.u8BufSize == 0 || stCfg.u8BufSize>10) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.ps32IdBuf == NULL) ++ { ++ SCL_ERR( "[SCLDMA3] not alloc multiinst buffer"); ++ return -EFAULT; ++ } ++ else ++ { ++ ps32PrivateID = MsOS_VirMemalloc(stCfg.u8BufSize * sizeof(signed long)); ++ if(ps32PrivateID == NULL) ++ { ++ SCL_ERR( "[SCLDMA3] not free alloc buffer"); ++ return -EFAULT; ++ } ++ if(copy_from_user(ps32PrivateID, (__user signed long *)stCfg.ps32IdBuf, stCfg.u8BufSize *sizeof(signed long))) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++#if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ SCL_ERR( "[SCLDMA3]%s ps32PrivateID:%lx %lx Size :%hhd\n",__FUNCTION__,(MS_U32)ps32PrivateID,*ps32PrivateID,stCfg.u8BufSize); ++#endif ++ } ++ stMultiInstLockCfg.ps32PrivateID = ps32PrivateID; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Alloc(E_MDRV_MULTI_INST_LOCK_ID_SC_3, &stMultiInstLockCfg) ) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EINVAL; ++ } ++ MsOS_VirMemFree(ps32PrivateID); ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma3_io_set_unlock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ signed long *ps32PrivateID = NULL; ++ MsOS_Memset(&stCfg,0,sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG)); ++ _mdrv_ms_scldma3_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma3_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_SCLDMA_LOCK_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.u8BufSize == 0 || stCfg.u8BufSize>10) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.ps32IdBuf == NULL) ++ { ++ SCL_ERR( "[SCLDMA3] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ else ++ { ++ ps32PrivateID = MsOS_VirMemalloc(stCfg.u8BufSize * sizeof(signed long)); ++ if(ps32PrivateID == NULL) ++ { ++ SCL_ERR( "[SCLDMA3] not free alloc buffer"); ++ return -EFAULT; ++ } ++ if(copy_from_user(ps32PrivateID, (__user signed long *)stCfg.ps32IdBuf, stCfg.u8BufSize*sizeof(signed long))) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++#if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ SCL_ERR( "[SCLDMA3]%s ps32PrivateID:%lx %lx %lx\n",__FUNCTION__,(MS_U32)ps32PrivateID,*ps32PrivateID,*(ps32PrivateID+1)); ++#endif ++ } ++ stMultiInstLockCfg.ps32PrivateID = ps32PrivateID; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_3, &stMultiInstLockCfg) ) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++ MsOS_VirMemFree(ps32PrivateID); ++ ++ return 0; ++} ++ ++int _mdrv_ms_scldma3_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, ++ &stCfg, sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma3_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma3.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA3] SCLDMA3IO_IOCTL refCnt =%d!!! \n", _dev_ms_scldma3.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA3] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_lock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ retval = _mdrv_ms_scldma3_io_set_unlock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma3_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_version(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma3_io_get_information_config(filp, u32Arg); ++ break; ++ ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA3] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma3_poll(struct file *filp, struct poll_table_struct *pstPollQueue) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMR_Done = 0; ++ unsigned char bFRMW_Done = 0; ++ unsigned int ret = 0; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ wait_queue_head_t *pWaitQueueHead = NULL; ++ ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_SC3, "[SCLDMA3] %s ret=%x\n",__FUNCTION__,ret); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ bFRMR_Done = 0; ++ pWaitQueueHead = (wait_queue_head_t *)MDrv_SCLDMA_GetWaitQueueHead(E_MDRV_SCLDMA_ID_3); ++ MDrv_SCLDMA_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++ if(MDrv_SCLDMA_GetOutBufferDoneEvent(E_MDRV_SCLDMA_ID_3, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMW_Done = stDoneCfg.bDone ? 1: 0; ++ } ++ else ++ { ++ bFRMW_Done = 2; ++ } ++ ++ if(bFRMW_Done == 1) ++ { ++ ret |= (POLLIN | POLLOUT); ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma3_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma3.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA3] Unable to get major %d\n", _dev_ms_scldma3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma3.cdev, &_dev_ms_scldma3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma3.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma3_class = msys_get_sysfs_class(); ++ if(!m_scldma3_class) ++ { ++ m_scldma3_class = class_create(THIS_MODULE, scldma3_classname); ++ } ++ if(IS_ERR(m_scldma3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma3.devicenode =device_create(m_scldma3_class, NULL, dev,NULL, "mscldma3"); ++ _dev_ms_scldma3.devicenode->dma_mask=&ms_scldma3_dma_mask; ++ _dev_ms_scldma3.devicenode->coherent_dma_mask=ms_scldma3_dma_mask; ++ } ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stSCLDMAInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stSCLDMAInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_3, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ st_ms_scldma3_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma3.stclk.idclk = of_clk_get(st_ms_scldma3_device.dev.of_node,0); ++ _dev_ms_scldma3.stclk.fclk1 = of_clk_get(st_ms_scldma3_device.dev.of_node,1); ++ _dev_ms_scldma3.stclk.fclk2 = of_clk_get(st_ms_scldma3_device.dev.of_node,2); ++ _dev_ms_scldma3.stclk.odclk = of_clk_get(st_ms_scldma3_device.dev.of_node,3); ++ if (device_create_file(_dev_ms_scldma3.devicenode, &dev_attr_ckfrmW)!= 0) ++ { ++ dev_err(_dev_ms_scldma3.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_scldma3.devicenode, &dev_attr_ckfrmR)!= 0) ++ { ++ dev_err(_dev_ms_scldma3.devicenode, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ gbProbeAlready |= EN_DBG_SCLDMA3_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma3.stclk)); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_SCLDMA3_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_SCLDMA_Exit(1); ++ } ++ else if(!(gbProbeAlready& (EN_DBG_SCLDMA1_CONFIG|EN_DBG_SCLDMA2_CONFIG|EN_DBG_SCLDMA3_CONFIG|EN_DBG_SCLDMA4_CONFIG))) ++ { ++ MDrv_SCLDMA_Exit(0); ++ } ++ cdev_del(&_dev_ms_scldma3.cdev); ++ device_destroy(m_scldma3_class, MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor)); ++ class_destroy(m_scldma3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma3_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_3, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrmW)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrmR)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create cksnp sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ return 0; ++} ++ ++static int mdrv_ms_scldma3_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_SC_3); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma3.stclk)); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma3_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_3)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma3.stclk)); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_scldma3_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_3)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma3_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma3.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ ++ } ++ if(!ret) ++ { ++ _dev_ms_scldma3.refCnt++; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma3_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3, filp->private_data); ++ ++ MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_SC_3, NULL); ++ ++ _dev_ms_scldma3.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma3.refCnt>=0); ++ if(_dev_ms_scldma3.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_3,&(_dev_ms_scldma3.stclk)); ++ } ++ //free_irq(INT_IRQ_SCLDMA3W, MDrv_SCLDMA3W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma3_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma3_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA3_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA3] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma3_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma3_driver); ++} ++ ++#else ++ ++int _mdrv_ms_scldma3_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma3.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma3.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma3.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA3] Unable to get major %d\n", _dev_ms_scldma3.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma3.cdev, &_dev_ms_scldma3.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma3.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA3] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma3_class = class_create(THIS_MODULE, scldma3_classname); ++ if(IS_ERR(m_scldma3_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma3_class, NULL, dev,NULL, "mscldma3"); ++ } ++ ++ /* initial the whole SCLDMA3 Driver */ ++ ret = platform_driver_register(&st_ms_scldma3_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma3_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma3_driver); ++ SCL_ERR( "[SCLDMA3] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma3_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA3] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma3.cdev); ++ device_destroy(m_scldma3_class, MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor)); ++ class_destroy(m_scldma3_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma3.s32Major, _dev_ms_scldma3.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma3_driver); ++} ++ ++#endif ++module_init(_mdrv_ms_scldma3_init); ++module_exit(_mdrv_ms_scldma3_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma3 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_scldma4_io.c b/drivers/mstar/scl/infinity3/mdrv_scldma4_io.c +new file mode 100644 +index 00000000..4eb92b03 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_scldma4_io.c +@@ -0,0 +1,1265 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include "ms_msys.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++#include "mdrv_scldma_io_i3_st.h" ++#include "mdrv_scldma_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst.h" ++#include "mdrv_verchk.h" ++//------------------------------------------------------------------------------------------------- ++ ++#define MDRV_MS_SCLDMA_DEVICE_COUNT 1 ++#define MDRV_MS_SCLDMA_NAME "mscldma4" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_SCLDMA "mscldma4" ++#define MDRV_MAJOR_SCLDMA 0xea ++#define MDRV_MINOR_SCLDMA 0x09 ++ ++#define CMD_PARSING(x) (x==IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG" : \ ++ x==IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG ? "IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG" : \ ++ x==IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG ? "IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG" :\ ++ x==IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG ? "IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_LOCK_CONFIG ? "IOCTL_SCLDMA_SET_LOCK_CONFIG" :\ ++ x==IOCTL_SCLDMA_SET_UNLOCK_CONFIG ? "IOCTL_SCLDMA_SET_UNLOCK_CONFIG" :\ ++ "UNKNOWN") ++ ++ ++int mdrv_ms_scldma4_open(struct inode *inode, struct file *filp); ++int mdrv_ms_scldma4_release(struct inode *inode, struct file *filp); ++long mdrv_ms_scldma4_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_scldma4_probe(struct platform_device *pdev); ++static int mdrv_ms_scldma4_remove(struct platform_device *pdev); ++static int mdrv_ms_scldma4_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_scldma4_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_scldma4_poll(struct file *filp, struct poll_table_struct *wait); ++ ++ ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ ST_MDRV_SCLDMA_CLK_CONFIG stclk; ++ struct device *devicenode; ++}ST_DEV_SCLDMA; ++ ++static ST_DEV_SCLDMA _dev_ms_scldma4 = ++{ ++ .s32Major = MDRV_MAJOR_SCLDMA, ++ .s32Minor = MDRV_MINOR_SCLDMA, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_SCLDMA, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_scldma4_open, ++ .release = mdrv_ms_scldma4_release, ++ .unlocked_ioctl = mdrv_ms_scldma4_ioctl, ++ .poll = mdrv_ms_scldma4_poll, ++ } ++}; ++ ++static struct class * m_scldma4_class = NULL; ++static char * scldma4_classname = "m_scldma4_class"; ++ ++ ++static const struct of_device_id ms_scldma4_of_match_table[] = ++{ ++ { .compatible = "mstar,scldma4" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_scldma4_driver = ++{ ++ .probe = mdrv_ms_scldma4_probe, ++ .remove = mdrv_ms_scldma4_remove, ++ .suspend = mdrv_ms_scldma4_suspend, ++ .resume = mdrv_ms_scldma4_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_SCLDMA, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_scldma4_of_match_table), ++ }, ++}; ++ ++static u64 ms_scldma4_dma_mask = 0xffffffffUL; ++ ++static struct platform_device st_ms_scldma4_device = ++{ ++ .name = "mscldma4", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_scldma4_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_frm_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_SCLDMA_ProcShow(buf,E_MDRV_SCLDMA_ID_PNL, E_MDRV_SCLDMA_MEM_FRM,1); ++} ++static ssize_t check_frm_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 48) //input 0 echo 0 >ptgen_call ++ { ++ SCL_ERR( "dma count reset %d\n",(int)*str); ++ MDrv_SCLDMA_ResetTrigCountByClient(E_MDRV_SCLDMA_ID_PNL,E_MDRV_SCLDMA_MEM_FRM,1); ++ } ++ return n; ++ } ++ return 0; ++} ++ ++static DEVICE_ATTR(ckfrm,0600, check_frm_show, check_frm_store); ++void _mdrv_ms_scldma4_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_scldma4_io_version_check(ST_MDRV_SCLDMA_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA3] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA3] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA3] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA3] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++ ++static int _ms_scldma4_multiinstSet(EN_MDRV_MULTI_INST_CMD_TYPE enType, void *stCfg ,void *privatedata) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData(E_MDRV_MULTI_INST_ENTRY_ID_DISP,privatedata ,enType,stCfg); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if (enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma4_io_get_information_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stDmaInfo; ++ ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG stIOGetCfg; ++ int u32Bufferidx; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ MsOS_Memset(&stDmaInfo,0,sizeof(ST_MDRV_SCLDMA_ATTR_TYPE)); ++ MsOS_Memset(&stIOGetCfg,0,sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG)); ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG), ++ (((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOGetCfg, ++ (__user ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_GET_INFORMATION_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(stIOGetCfg.enMemType == E_IOCTL_SCLDMA_MEM_FRM) ++ { ++ MDrv_SCLDMA_GetDMAInformationByClient(E_MDRV_SCLDMA_ID_PNL, E_MDRV_SCLDMA_MEM_FRM,0,&stDmaInfo); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] not support\n"); ++ } ++ stIOGetCfg.enBufMDType = (EN_IOCTL_SCLDMA_BUFFER_MODE_TYPE)stDmaInfo.enBufMDType; ++ stIOGetCfg.enColorType = (EN_IOCTL_SCLDMA_COLOR_TYPE)stDmaInfo.enColorType; ++ stIOGetCfg.u16BufNum = stDmaInfo.u16BufNum; ++ stIOGetCfg.u16DMAH = stDmaInfo.u16DMAH; ++ stIOGetCfg.u16DMAV = stDmaInfo.u16DMAV; ++ for(u32Bufferidx=0;u32Bufferidxu8Flag = stIODMABufferCfg->u8Flag; ++ stDMABufferCfg->enBufMDType = (EN_MDRV_SCLDMA_BUFFER_MODE_TYPE)stIODMABufferCfg->enBufMDType; ++ stDMABufferCfg->enColorType = (EN_MDRV_SCLDMA_COLOR_TYPE)stIODMABufferCfg->enColorType; ++ stDMABufferCfg->enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIODMABufferCfg->enMemType; ++ stDMABufferCfg->u16BufNum = stIODMABufferCfg->u16BufNum; ++ stDMABufferCfg->u16Height = stIODMABufferCfg->u16Height; ++ stDMABufferCfg->u16Width = stIODMABufferCfg->u16Width; ++ memcpy(stDMABufferCfg->u32Base_Y,stIODMABufferCfg->u32Base_Y,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_C,stIODMABufferCfg->u32Base_C,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++ memcpy(stDMABufferCfg->u32Base_V,stIODMABufferCfg->u32Base_V,sizeof(unsigned long)*BUFFER_BE_ALLOCATED_MAX); ++} ++ ++int _mdrv_ms_scldma4_io_set_in_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_CONFIG stIODMABufferCfg; ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stDMABufferCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIODMABufferCfg, ++ (__user ST_IOCTL_SCLDMA_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ _mdrv_ms_scldma4_io_fillbufferconfig(&stIODMABufferCfg,&stDMABufferCfg); ++ } ++ } ++ ++ if(_ms_scldma4_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG, (void *)&stDMABufferCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientConfig(E_MDRV_SCLDMA_ID_PNL, &stDMABufferCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++ ++} ++ ++int _mdrv_ms_scldma4_io_set_in_trigger_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stDrvTrigCfg; ++ ST_IOCTL_SCLDMA_TRIGGER_CONFIG stIOTrigCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG), ++ (((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_TRIGGER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOTrigCfg, ++ (__user ST_IOCTL_SCLDMA_TRIGGER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_TRIGGER_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stDrvTrigCfg.bEn = stIOTrigCfg.bEn; ++ stDrvTrigCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOTrigCfg.enMemType; ++ } ++ } ++ stDrvTrigCfg.stclk=&(_dev_ms_scldma4.stclk); ++ if(_ms_scldma4_multiinstSet(E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG, (void *)&stDrvTrigCfg, filp->private_data)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_SetDMAReadClientTrigger(E_MDRV_SCLDMA_ID_PNL, &stDrvTrigCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_scldma4_io_set_out_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA4] not support IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG"); ++ ++ return -EFAULT; ++ ++} ++ ++int _mdrv_ms_scldma4_io_set_out_trigger_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA4] not support IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG"); ++ ++ return -EFAULT; ++} ++ ++int _mdrv_ms_scldma4_io_get_in_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG stIOActiveCfg; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ MsOS_Memset(&stActiveCfg,0,sizeof(ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG)); ++ MsOS_Memset(&stIOActiveCfg,0,sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG)); ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG), ++ (((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOActiveCfg, ++ (__user ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stActiveCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOActiveCfg.enMemType; ++ stActiveCfg.u8ActiveBuffer = stIOActiveCfg.u8ActiveBuffer; ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data); ++ stActiveCfg.stOnOff.stclk=&(_dev_ms_scldma4.stclk); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ stActiveCfg.u8ActiveBuffer = 0xFF; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_GetDMAReadBufferActiveIdx(E_MDRV_SCLDMA_ID_PNL, &stActiveCfg)) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ stIOActiveCfg.u8ActiveBuffer = stActiveCfg.u8ActiveBuffer; ++ stIOActiveCfg.enMemType = (EN_IOCTL_SCLDMA_MEM_TYPE)stActiveCfg.enMemType; ++ stIOActiveCfg.u8ISPcount = stActiveCfg.u8ISPcount; ++ stIOActiveCfg.u64FRMDoneTime = stActiveCfg.u64FRMDoneTime; ++ if(copy_to_user((ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG __user *)arg, ++ &stIOActiveCfg, sizeof(ST_IOCTL_SCLDMA_ACTIVE_BUFFER_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ } ++ return ret; ++} ++ ++int _mdrv_ms_scldma4_io_get_out_active_buffer_config(struct file *filp, unsigned long arg) ++{ ++ SCL_ERR( "[SCLDMA4] not support IOCTL_SCLDMA_GET_ACTIVE_BUFFER_CONFIG"); ++ ++ return -EFAULT; ++} ++ ++int _mdrv_ms_scldma4_io_buffer_queue_handle_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG stIOBufferQCfg; ++ ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG stBufferQCfg; ++ int ret = 0; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG), ++ (((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOBufferQCfg, (__user ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stBufferQCfg.enMemType = (EN_MDRV_SCLDMA_MEM_TYPE)stIOBufferQCfg.enMemType; ++ stBufferQCfg.enUsedType = (EN_MDRV_SCLDMA_USED_BUFFER_QUEUE_TYPE)stIOBufferQCfg.enUsedType; ++ stBufferQCfg.u8EnqueueIdx = stIOBufferQCfg.u8EnqueueIdx; ++ } ++ } ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1, filp->private_data); ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_LOCKED) ++ { ++ ret = -EINVAL; ++ } ++ else if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_FAIL) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ if(!MDrv_SCLDMA_BufferQueueHandle(E_MDRV_SCLDMA_ID_PNL, &stBufferQCfg)) ++ { ++ ret = 0; ++ } ++ else ++ { ++ memcpy(&stIOBufferQCfg.stRead,&stBufferQCfg.stRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ stIOBufferQCfg.u8InQueueCount = stBufferQCfg.u8InQueueCount; ++ stIOBufferQCfg.u8EnqueueIdx = stBufferQCfg.u8EnqueueIdx; ++ if(copy_to_user((ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG __user *)arg, &stIOBufferQCfg, sizeof(ST_IOCTL_SCLDMA_BUFFER_QUEUE_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ return ret; ++} ++ ++ ++int _mdrv_ms_scldma4_io_get_private_id_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG stCfg; ++ ++ if(!MDrv_MultiInst_Entry_GetPirvateId(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data, &stCfg.s32Id)) ++ { ++ return -EFAULT; ++ } ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_SCLDMA_PRIVATE_ID_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++ ++} ++ ++int _mdrv_ms_scldma4_io_set_lock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ signed long *ps32PrivateID = NULL; ++ MsOS_Memset(&stCfg,0,sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG)); ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_SCLDMA_LOCK_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.u8BufSize == 0 || stCfg.u8BufSize>10) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.ps32IdBuf == NULL) ++ { ++ SCL_ERR( "[SCLDMA4] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ else ++ { ++ ps32PrivateID = MsOS_VirMemalloc(stCfg.u8BufSize * sizeof(signed long)); ++ if(ps32PrivateID == NULL) ++ { ++ SCL_ERR( "[SCLDMA4] not free alloc buffer"); ++ return -EFAULT; ++ } ++ if(copy_from_user(ps32PrivateID, (__user signed long *)stCfg.ps32IdBuf, stCfg.u8BufSize*sizeof(signed long))) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++#if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ SCL_ERR( "[SCLDMA4]%s ps32PrivateID:%lx %lx %lx\n",__FUNCTION__,(MS_U32)ps32PrivateID,*ps32PrivateID,*(ps32PrivateID+1)); ++#endif ++ } ++ stMultiInstLockCfg.ps32PrivateID = ps32PrivateID; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Alloc(E_MDRV_MULTI_INST_LOCK_ID_DISP, &stMultiInstLockCfg) ) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EINVAL; ++ } ++ MsOS_VirMemFree(ps32PrivateID); ++ return 0; ++} ++ ++int _mdrv_ms_scldma4_io_set_unlock_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_SCLDMA_LOCK_CONFIG stCfg; ++ ST_MDRV_MULTI_INST_LOCK_CONFIG stMultiInstLockCfg; ++ ST_MDRV_SCLDMA_VERSIONCHK_CONFIG stVersion; ++ signed long *ps32PrivateID = NULL; ++ MsOS_Memset(&stCfg,0,sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG)); ++ _mdrv_ms_scldma4_io_fill_versionchkstruct(sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG), ++ (((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_SCLDMA_LOCK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_scldma4_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[SCLDMA4] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_SCLDMA_LOCK_CONFIG *)arg, sizeof(ST_IOCTL_SCLDMA_LOCK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.u8BufSize == 0 || stCfg.u8BufSize>10) ++ { ++ return -EFAULT; ++ } ++ if(stCfg.ps32IdBuf == NULL) ++ { ++ SCL_ERR( "[SCLDMA1] not free multiinst buffer"); ++ return -EFAULT; ++ } ++ else ++ { ++ ps32PrivateID = MsOS_VirMemalloc(stCfg.u8BufSize * sizeof(signed long)); ++ if(ps32PrivateID == NULL) ++ { ++ SCL_ERR( "[SCLDMA4] not free alloc buffer"); ++ return -EFAULT; ++ } ++ if(copy_from_user(ps32PrivateID, (__user signed long *)stCfg.ps32IdBuf, stCfg.u8BufSize*sizeof(signed long))) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++#if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ SCL_ERR( "[SCLDMA1]%s ps32PrivateID:%lx %lx %lx\n",__FUNCTION__,(MS_U32)ps32PrivateID,*ps32PrivateID,*(ps32PrivateID+1)); ++#endif ++ } ++ stMultiInstLockCfg.ps32PrivateID = ps32PrivateID; ++ stMultiInstLockCfg.u8IDNum = stCfg.u8BufSize; ++ ++ if( !MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_DISP, &stMultiInstLockCfg) ) ++ { ++ MsOS_VirMemFree(ps32PrivateID); ++ return -EFAULT; ++ } ++ MsOS_VirMemFree(ps32PrivateID); ++ return 0; ++} ++ ++ ++int _mdrv_ms_scldma4_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version), ++ IOCTL_SCLDMA_VERSION) ) ++ { ++ ++ VERCHK_ERR("[SCLDMA] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_SCLDMA_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size), ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[SCLDMA] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG), ++ (((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_SCLDMA_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_SCLDMA_VERSION); ++ stCfg.u32Version = IOCTL_SCLDMA_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_SCLDMA_VERSION_CONFIG __user *)arg, ++ &stCfg, sizeof(ST_IOCTL_SCLDMA_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[SCLDMA] No Header !!! \n"); ++ SCL_ERR( "[SCLDMA]%s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_scldma4_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int retval = 0; ++ ++ if(_dev_ms_scldma4.refCnt <= 0) ++ { ++ SCL_ERR( "[SCLDMA4] SCLDMA_IOCTL refCnt =%d!!! \n", _dev_ms_scldma4.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_SCLDMA_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_SCLDMA_MAX_NR) ++ { ++ SCL_ERR( "[SCLDMA4] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_LCD, "[SCLDMA1] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ ++ switch(u32Cmd) ++ { ++ case IOCTL_SCLDMA_SET_IN_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_in_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_IN_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_in_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_out_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_OUT_TRIGGER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_out_trigger_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_IN_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_in_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_OUT_ACTIVE_BUFFER_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_out_active_buffer_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_PRIVATE_ID_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_private_id_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_LOCK_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_lock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_SET_UNLOCK_CONFIG: ++ retval = _mdrv_ms_scldma4_io_set_unlock_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_version(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_GET_INFORMATION_CONFIG: ++ retval = _mdrv_ms_scldma4_io_get_information_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_SCLDMA_BUFFER_QUEUE_HANDLE_CONFIG: ++ retval = _mdrv_ms_scldma4_io_buffer_queue_handle_config(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[SCLDMA4] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_scldma4_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG stDoneCfg; ++ unsigned char bFRMR_Done; ++ unsigned int ret; ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ ++ enMultiInstRet = MDrv_MultiInst_Etnry_IsFree(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data); ++ ++ if(enMultiInstRet == E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ if(MDrv_SCLDMA_GetInBufferDoneEvent(E_MDRV_SCLDMA_ID_PNL, E_MDRV_SCLDMA_MEM_FRM, &stDoneCfg)) ++ { ++ bFRMR_Done = stDoneCfg.bDone ? 1: 0; ++ } ++ else ++ { ++ bFRMR_Done = 2; ++ } ++ ++ if(bFRMR_Done==1) ++ { ++ ret = (POLLOUT | POLLWRNORM); //writable ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ ++ return ret; ++} ++#if CONFIG_OF ++static int mdrv_ms_scldma4_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ //module ++ if(_dev_ms_scldma4.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma4.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma4.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA4] Unable to get major %d\n", _dev_ms_scldma4.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma4.cdev, &_dev_ms_scldma4.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma4.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA4] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma4_class = msys_get_sysfs_class(); ++ if(!m_scldma4_class) ++ { ++ m_scldma4_class = class_create(THIS_MODULE, scldma4_classname); ++ } ++ if(IS_ERR(m_scldma4_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_scldma4.devicenode =device_create(m_scldma4_class, NULL, dev,NULL, "mscldma4"); ++ _dev_ms_scldma4.devicenode->dma_mask=&ms_scldma4_dma_mask; ++ _dev_ms_scldma4.devicenode->coherent_dma_mask=ms_scldma4_dma_mask; ++ } ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ MsOS_SetSclIrqIDFormSys(pdev,0,E_SCLIRQ_SC0); ++ MsOS_SetCmdqIrqIDFormSys(pdev,1,E_CMDQIRQ_CMDQ0); ++ stSCLDMAInitCfg.u32IRQNUM = MsOS_GetIrqIDSCL(E_SCLIRQ_SC0); ++ stSCLDMAInitCfg.u32CMDQIRQNUM = MsOS_GetIrqIDCMDQ(E_CMDQIRQ_CMDQ0); ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_PNL, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ st_ms_scldma4_device.dev.of_node = pdev->dev.of_node; ++ _dev_ms_scldma4.stclk.idclk = of_clk_get(st_ms_scldma4_device.dev.of_node,0); ++ _dev_ms_scldma4.stclk.fclk1 = of_clk_get(st_ms_scldma4_device.dev.of_node,1); ++ _dev_ms_scldma4.stclk.fclk2 = of_clk_get(st_ms_scldma4_device.dev.of_node,2); ++ _dev_ms_scldma4.stclk.odclk = of_clk_get(st_ms_scldma4_device.dev.of_node,3); ++ if (device_create_file(_dev_ms_scldma4.devicenode, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(_dev_ms_scldma4.devicenode, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_DISP); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ gbProbeAlready |= EN_DBG_SCLDMA4_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_scldma4_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma4.stclk)); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_SCLDMA4_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_SCLDMA_Exit(1); ++ } ++ else if(!(gbProbeAlready& (EN_DBG_SCLDMA1_CONFIG|EN_DBG_SCLDMA2_CONFIG|EN_DBG_SCLDMA3_CONFIG|EN_DBG_SCLDMA4_CONFIG))) ++ { ++ MDrv_SCLDMA_Exit(0); ++ } ++ cdev_del(&_dev_ms_scldma4.cdev); ++ device_destroy(m_scldma4_class, MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor)); ++ class_destroy(m_scldma4_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return 0; ++} ++#else ++static int mdrv_ms_scldma4_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_SCLDMA_INIT_CONFIG stSCLDMAInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ stSCLDMAInitCfg.u32Riubase = 0x1F000000; //ToDo ++ ++ if( MDrv_SCLDMA_Init(E_MDRV_SCLDMA_ID_PNL, &stSCLDMAInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckfrm)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create ckfrm sysfs files\n"); ++ } ++ MDrv_MultiInst_Entry_Init_Variable(E_MDRV_MULTI_INST_ENTRY_ID_DISP); ++ ++ MDrv_MultiInst_Lock_Init(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ ++ return 0; ++} ++ ++static int mdrv_ms_scldma4_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Lock_Exit(E_MDRV_MULTI_INST_LOCK_ID_DISP); ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma4.stclk)); ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_scldma4_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Suspend(E_MDRV_SCLDMA_ID_PNL)) ++ { ++ MDrv_SCLDMA_ClkClose(&(_dev_ms_scldma4.stclk)); ++ ret = 0; ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ return ret; ++} ++ ++ ++static int mdrv_ms_scldma4_resume(struct platform_device *dev) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enMultiInstRet; ++ int ret = 0; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ if(MDrv_SCLDMA_Resume(E_MDRV_SCLDMA_ID_PNL)) ++ { ++ enMultiInstRet = MDrv_MultiInst_Entry_FlashData( ++ E_MDRV_MULTI_INST_ENTRY_ID_DISP, ++ NULL, ++ E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG, ++ NULL); ++ ++ ++ if(enMultiInstRet != E_MDRV_MULTI_INST_STATUS_SUCCESS) ++ { ++ ret = -EINVAL; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = -EFAULT; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma4_open(struct inode *inode, struct file *filp) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ SCL_ASSERT(_dev_ms_scldma4.refCnt>=0); ++ ++ if(filp->private_data == NULL) ++ { ++ if(MDrv_MultiInst_Entry_Alloc(E_MDRV_MULTI_INST_ENTRY_ID_DISP, &filp->private_data) == 0) ++ { ++ ret = -EFAULT; ++ } ++ } ++ if(!ret) ++ { ++ _dev_ms_scldma4.refCnt++; ++ } ++ ++ return ret; ++} ++ ++ ++int mdrv_ms_scldma4_release(struct inode *inode, struct file *filp) ++{ ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ MDrv_MultiInst_Entry_Free(E_MDRV_MULTI_INST_ENTRY_ID_DISP, filp->private_data); ++ ++ MDrv_MultiInst_Lock_Free(E_MDRV_MULTI_INST_LOCK_ID_DISP, NULL); ++ ++ _dev_ms_scldma4.refCnt--; ++ SCL_ASSERT(_dev_ms_scldma4.refCnt>=0); ++ if(_dev_ms_scldma4.refCnt==0) ++ { ++ MDrv_SCLDMA_Release(E_MDRV_SCLDMA_ID_PNL,&(_dev_ms_scldma4.stclk)); ++ } ++ //free_irq(INT_IRQ_SCLDMA4W, MDrv_SCLDMA4W_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_scldma4_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_scldma4_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_SCLDMA4_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA4] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_scldma4_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_scldma4_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_scldma4_driver); ++} ++ ++#else ++ ++int _mdrv_ms_scldma4_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_scldma4.s32Major) ++ { ++ dev = MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_scldma4.s32Minor, MDRV_MS_SCLDMA_DEVICE_COUNT, MDRV_MS_SCLDMA_NAME); ++ _dev_ms_scldma4.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[SCLDMA4] Unable to get major %d\n", _dev_ms_scldma4.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_scldma4.cdev, &_dev_ms_scldma4.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_scldma4.cdev, dev, MDRV_MS_SCLDMA_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[SCLDMA4] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_SCLDMA_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_scldma4_class = class_create(THIS_MODULE, scldma4_classname); ++ if(IS_ERR(m_scldma4_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_scldma4_class, NULL, dev,NULL, "mscldma4"); ++ } ++ ++ /* initial the whole SCLDMA4 Driver */ ++ ret = platform_driver_register(&st_ms_scldma4_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_scldma4_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_scldma4_driver); ++ SCL_ERR( "[SCLDMA4] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_scldma4_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[SCLDMA4] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_scldma4.cdev); ++ device_destroy(m_scldma4_class, MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor)); ++ class_destroy(m_scldma4_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_scldma4.s32Major, _dev_ms_scldma4.s32Minor), MDRV_MS_SCLDMA_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_scldma4_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_scldma4_init); ++module_exit(_mdrv_ms_scldma4_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms scldma4 ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/mdrv_vip_io.c b/drivers/mstar/scl/infinity3/mdrv_vip_io.c +new file mode 100644 +index 00000000..18a4a83e +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/mdrv_vip_io.c +@@ -0,0 +1,1973 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include "ms_platform.h" ++#include "registers.h" ++ ++#include "ms_msys.h" ++ ++#include "mdrv_vip_io_i3_st.h" ++#include "mdrv_vip_io_i3.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_vip_st.h" ++#include "mdrv_vip.h" ++#include "mdrv_verchk.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++ ++#define MDRV_MS_VIP_DEVICE_COUNT 1 ++#define MDRV_MS_VIP_NAME "mvip" ++#define MAX_FILE_HANDLE_SUPPRT 64 ++#define MDRV_NAME_VIP "mvip" ++#define MDRV_MAJOR_VIP 0xea ++#define MDRV_MINOR_VIP 0x07 ++#define _ms_vip_mem_bus_to_miu(x) (x-0x20000000) ++#define CMD_PARSING(x) ( x == IOCTL_VIP_SET_MCNR_CONFIG ? "IOCTL_VIP_SET_MCNR_CONFIG" : \ ++ x == IOCTL_VIP_SET_PEAKING_CONFIG ? "IOCTL_VIP_SET_PEAKING_CONFIG" : \ ++ x == IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG ? "IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG" : \ ++ x == IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ? "IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT" : \ ++ x == IOCTL_VIP_SET_DLC_CONFIG ? "IOCTL_VIP_SET_DLC_CONFIG" : \ ++ x == IOCTL_VIP_SET_LCE_CONFIG ? "IOCTL_VIP_SET_LCE_CONFIG" : \ ++ x == IOCTL_VIP_SET_UVC_CONFIG ? "IOCTL_VIP_SET_UVC_CONFIG" : \ ++ x == IOCTL_VIP_SET_IHC_CONFIG ? "IOCTL_VIP_SET_IHC_CONFIG" : \ ++ x == IOCTL_VIP_SET_ICE_CONFIG ? "IOCTL_VIP_SET_ICE_CONFIG" : \ ++ x == IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG ? "IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG" : \ ++ x == IOCTL_VIP_SET_IBC_CONFIG ? "IOCTL_VIP_SET_IBC_CONFIG" : \ ++ x == IOCTL_VIP_SET_FCC_CONFIG ? "IOCTL_VIP_SET_FCC_CONFIG" : \ ++ x == IOCTL_VIP_CMDQ_WRITE_CONFIG ? "IOCTL_VIP_CMDQ_WRITE_CONFIG" :\ ++ x == IOCTL_VIP_SET_LDC_CONFIG ? "IOCTL_VIP_SET_LDC_OnOff_CONFIG" : \ ++ x == IOCTL_VIP_SET_LDC_MD_CONFIG ? "IOCTL_VIP_SET_LDC_MD_CONFIG" : \ ++ x == IOCTL_VIP_SET_LDC_DMAP_CONFIG ? "IOCTL_VIP_SET_LDC_DMAP_CONFIG" : \ ++ x == IOCTL_VIP_SET_LDC_SRAM_CONFIG ? "IOCTL_VIP_SET_LDC_SRAM_CONFIG" : \ ++ x == IOCTL_VIP_SET_ACK_CONFIG ? "IOCTL_VIP_SET_ACK_CONFIG" : \ ++ x == IOCTL_VIP_SET_NLM_CONFIG ? "IOCTL_VIP_SET_NLM_CONFIG" : \ ++ x == IOCTL_VIP_SET_AIP_SRAM_CONFIG ? "IOCTL_VIP_SET_AIP_SRAM_CONFIG" : \ ++ x == IOCTL_VIP_SET_VIP_CONFIG ? "IOCTL_VIP_SET_VIP_CONFIG" : \ ++ x == IOCTL_VIP_SET_AIP_CONFIG ? "IOCTL_VIP_SET_AIP_CONFIG" : \ ++ x == IOCTL_VIP_SET_VTRACK_CONFIG ? "IOCTL_VIP_SET_VTRACK_CONFIG" : \ ++ x == IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG ? "IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG" : \ ++ "UNKNOWN") ++#define AIP_PARSING(x) ( x == EN_VIP_MDRV_AIP_YEE ? "EN_VIP_MDRV_AIP_YEE" : \ ++ x == EN_VIP_MDRV_AIP_YEE_AC_LUT ? "EN_VIP_MDRV_AIP_YEE_AC_LUT" : \ ++ x == EN_VIP_MDRV_AIP_WDR_GLOB ? "EN_VIP_MDRV_AIP_WDR_GLOB" : \ ++ x == EN_VIP_MDRV_AIP_WDR_LOC ? "EN_VIP_MDRV_AIP_WDR_LOC" : \ ++ x == EN_VIP_MDRV_AIP_MXNR ? "EN_VIP_MDRV_AIP_MXNR" : \ ++ x == EN_VIP_MDRV_AIP_UVADJ ? "EN_VIP_MDRV_AIP_UVADJ" : \ ++ x == EN_VIP_MDRV_AIP_XNR ? "EN_VIP_MDRV_AIP_XNR" : \ ++ x == EN_VIP_MDRV_AIP_YCUVM ? "EN_VIP_MDRV_AIP_YCUVM" : \ ++ x == EN_VIP_MDRV_AIP_COLORTRAN ? "EN_VIP_MDRV_AIP_COLORTRAN" : \ ++ x == EN_VIP_MDRV_AIP_GAMMA ? "EN_VIP_MDRV_AIP_GAMMA" : \ ++ x == EN_VIP_MDRV_AIP_422TO444 ? "EN_VIP_MDRV_AIP_422TO444" : \ ++ x == EN_VIP_MDRV_AIP_YUVTORGB ? "EN_VIP_MDRV_AIP_YUVTORGB" : \ ++ x == EN_VIP_MDRV_AIP_GM10TO12 ? "EN_VIP_MDRV_AIP_GM10TO12" :\ ++ x == EN_VIP_MDRV_AIP_CCM ? "EN_VIP_MDRV_AIP_CCM" : \ ++ x == EN_VIP_MDRV_AIP_HSV ? "EN_VIP_MDRV_AIP_HSV" : \ ++ x == EN_VIP_MDRV_AIP_GM12TO10 ? "EN_VIP_MDRV_AIP_GM12TO10" : \ ++ x == EN_VIP_MDRV_AIP_RGBTOYUV ? "EN_VIP_MDRV_AIP_RGBTOYUV" : \ ++ x == EN_VIP_MDRV_AIP_444TO422 ? "EN_VIP_MDRV_AIP_444TO422" : \ ++ "UNKNOWN") ++ ++int mdrv_ms_vip_open(struct inode *inode, struct file *filp); ++int mdrv_ms_vip_release(struct inode *inode, struct file *filp); ++long mdrv_ms_vip_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg); ++static int mdrv_ms_vip_probe(struct platform_device *pdev); ++static int mdrv_ms_vip_remove(struct platform_device *pdev); ++static int mdrv_ms_vip_suspend(struct platform_device *dev, pm_message_t state); ++static int mdrv_ms_vip_resume(struct platform_device *dev); ++static unsigned int mdrv_ms_vip_poll(struct file *filp, struct poll_table_struct *wait); ++ ++//extern atomic_t SC1W_intr_count; ++ ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ int s32Major; ++ int s32Minor; ++ int refCnt; ++ struct cdev cdev; ++ struct file_operations fops; ++ struct device *devicenode; ++}ST_DEV_VIP; ++ ++static ST_DEV_VIP _dev_ms_vip = ++{ ++ .s32Major = MDRV_MAJOR_VIP, ++ .s32Minor = MDRV_MINOR_VIP, ++ .refCnt = 0, ++ .cdev = ++ { ++ .kobj = {.name= MDRV_NAME_VIP, }, ++ .owner = THIS_MODULE, ++ }, ++ .fops = ++ { ++ .open = mdrv_ms_vip_open, ++ .release = mdrv_ms_vip_release, ++ .unlocked_ioctl = mdrv_ms_vip_ioctl, ++ .poll = mdrv_ms_vip_poll, ++ } ++}; ++ ++static struct class * m_vip_class = NULL; ++static char * vip_classname = "m_vip_class"; ++ ++ ++static const struct of_device_id ms_vip_of_match_table[] = ++{ ++ { .compatible = "mstar,vip" }, ++ {} ++}; ++ ++static struct platform_driver st_ms_vip_driver = ++{ ++ .probe = mdrv_ms_vip_probe, ++ .remove = mdrv_ms_vip_remove, ++ .suspend = mdrv_ms_vip_suspend, ++ .resume = mdrv_ms_vip_resume, ++ .driver = ++ { ++ .name = MDRV_NAME_VIP, ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_vip_of_match_table), ++ }, ++}; ++static u64 ms_vip_dma_mask = 0xffffffffUL; ++#if (!CONFIG_OF) ++ ++static struct platform_device st_ms_vip_device = ++{ ++ .name = "mvip", ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &ms_vip_dma_mask, ++ .coherent_dma_mask = 0xffffffffUL ++ } ++}; ++#endif ++//------------------------------------------------------------------------------------------------- ++static const char* KEY_DMEM_VIP_CMDQ="VIP_CMDQ"; ++static unsigned char g_bVIPSysInitReady = 0; ++dma_addr_t sg_vip_cmdq_bus_addr; ++static u_long sg_vip_cmdq_size = VIP_CMDQ_MEM_256K;//128kb 1F400 ++static void *sg_vip_cmdq_vir_addr = NULL; ++ST_VIP_CMDQ_INIT_CONFIG gstInitCMDQCfg; ++unsigned int gu32CMDQmode = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// IOCtrl Driver interface functions ++//------------------------------------------------------------------------------------------------- ++static ssize_t check_bypass_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_ProcShow(buf); ++} ++static ssize_t check_bypass_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ EN_VIP_MDRV_AIP_TYPE enAIPtype; ++ if((int)*str == 49) //input 1 echo 1 >bypass OPEN ++ { ++ SCL_ERR( "[HVSP1]bypass OPEN %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig((EN_VIP_MDRV_CONFIG_TYPE)0x7FFFF); ++ for(enAIPtype = EN_VIP_MDRV_AIP_YEE;enAIPtypebypass CLOSE ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_MDRV_CONFIG); ++ } ++ else if((int)*str == 51) //input 3 echo 3 >MCNR bypass ++ { ++ SCL_ERR( "[HVSP1]MCNR bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_MDRV_MCNR_CONFIG); ++ } ++ else if((int)*str == 53) //input 5 echo 5 >NLM bypass ++ { ++ SCL_ERR( "[HVSP1]NLM bypass %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_MDRV_NLM_CONFIG); ++ } ++ else if((int)*str == 54) //input 6 echo 6 >LDC bypass ++ { ++ SCL_ERR( "[HVSP1]LDC bypass %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig(EN_VIP_MDRV_LDC_CONFIG); ++ } ++ else if((int)*str == 52) //input 4 echo 4 >YEE bypass ++ { ++ SCL_ERR( "[HVSP1]YEE bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_YEE); ++ } ++ else if((int)*str == 55) //input 7 echo 7 >YEE bypass ++ { ++ SCL_ERR( "[HVSP1]WDR GLOBAL bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_WDR_GLOB); ++ } ++ else if((int)*str == 56) //input 8 echo 8 >WDR loc bypass ++ { ++ SCL_ERR( "[HVSP1]WDR LOC bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_WDR_LOC); ++ } ++ else if((int)*str == 57) //input 9 echo 9 >MXNR bypass ++ { ++ SCL_ERR( "[HVSP1]MXNR bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_MXNR); ++ } ++ else if((int)*str == 65) //input A echo A >YUVADJ bypass ++ { ++ SCL_ERR( "[HVSP1]YUVADJ bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_UVADJ); ++ } ++ else if((int)*str == 66) //input B echo B >XNR bypass ++ { ++ SCL_ERR( "[HVSP1]XNR bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_XNR); ++ } ++ else if((int)*str == 67) //input C echo C >YCUVM bypass ++ { ++ SCL_ERR( "[HVSP1]YCUVM bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_YCUVM); ++ } ++ else if((int)*str == 68) //input D echo D >COLOR TRAN bypass ++ { ++ SCL_ERR( "[HVSP1]COLOR TRAN bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_COLORTRAN); ++ } ++ else if((int)*str == 69) //input E echo E >YUV GAMMA bypass ++ { ++ SCL_ERR( "[HVSP1]YUV GAMMA bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_GAMMA); ++ } ++ else if((int)*str == 70) //input F echo F >Y2R bypass ++ { ++ SCL_ERR( "[HVSP1]Y2R bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_YUVTORGB); ++ } ++ else if((int)*str == 71) //input G echo G >GM10to12 bypass ++ { ++ SCL_ERR( "[HVSP1]GM10to12 bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_GM10TO12); ++ } ++ else if((int)*str == 72) //input H echo H >CCM bypass ++ { ++ SCL_ERR( "[HVSP1]CCM bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_CCM); ++ } ++ else if((int)*str == 73) //input I echo I >HSV bypass ++ { ++ SCL_ERR( "[HVSP1]HSV bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_HSV); ++ } ++ else if((int)*str == 74) //input J echo J >GM12to10 bypass ++ { ++ SCL_ERR( "[HVSP1]GM12to10 bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_GM12TO10); ++ } ++ else if((int)*str == 75) //input K echo J >R2Y bypass ++ { ++ SCL_ERR( "[HVSP1]R2Y bypass %d\n",(int)*str); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_RGBTOYUV); ++ } ++ else if((int)*str == 48) //input 0 echo 0 >all bypass ++ { ++ SCL_ERR( "[HVSP1]bypass CLOSE %d\n",(int)*str); ++ MDrv_VIP_SetVIPBypassConfig((EN_VIP_MDRV_CONFIG_TYPE)0); ++ MDrv_VIP_SetAIPBypassConfig(EN_VIP_MDRV_AIP_NUM); ++ } ++ ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(bypass,0600, check_bypass_show, check_bypass_store); ++ ++static ssize_t check_CMDQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "echo 1 > ckCMDQ :by already setting\n"); ++ str += scnprintf(str, end - str, "echo 2 > ckCMDQ :by auto testing\n"); ++ return (str - buf); ++} ++ ++static ssize_t check_CMDQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 > ++ { ++ SCL_ERR( "[CMDQ]CMDQ check by already setting %d\n",(int)*str); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_ALREADY_SETINNG); ++ MDrv_VIP_ResetEachIP(); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_RETURN_ORI); ++ MDrv_VIP_SetCheckMode(EN_VIP_CMDQ_CHECK_PQ); ++ MDrv_VIP_CheckRegister(); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_RETURN_ORI); ++ } ++ else if((int)*str == 50) //input 2 echo 2 > ++ { ++ SCL_ERR( "[CMDQ]CMDQ check by auto testing %d\n",(int)*str); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_AUTOSETTING); ++ MDrv_VIP_ResetEachIP(); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_RETURN_ORI); ++ MDrv_VIP_SetCheckMode(EN_VIP_CMDQ_CHECK_PQ); ++ MDrv_VIP_CheckRegister(); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_RETURN_ORI); ++ } ++ ++ return n; ++ } ++ ++ return 0; ++} ++ ++static DEVICE_ATTR(ckCMDQ,0600, check_CMDQ_show, check_CMDQ_store); ++ ++static ssize_t check_PQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += scnprintf(str, end - str, "echo 1 > ckPQ :by already setting\n"); ++ str += scnprintf(str, end - str, "echo 2 > ckPQ :by auto testing\n"); ++ ++ return (str - buf); ++} ++ ++static ssize_t check_PQ_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 > ++ { ++ SCL_ERR( "[HVSP1]PQ check by already setting %d\n",(int)*str); ++ MDrv_VIP_SetCheckMode(EN_VIP_CMDQ_CHECK_PQ); ++ MDrv_VIP_CheckConsist(); //consistency ++ MDrv_VIP_CheckRegister(); //basic check register ++ MDrv_VIP_SetCheckMode(EN_VIP_CMDQ_CHECK_RETURN_ORI); //a ++ } ++ /* ++ else if((int)*str == 50) //input 2 echo 2 > ++ { ++ SCL_ERR( "[HVSP1]PQ check by auto testing %d\n",(int)*str); ++ MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_PQ); ++ MDrv_VIP_ResetEachIP(); ++ MDrv_VIP_CheckRegister(); //basic check register ++ MDrv_VIP_SetCheckMode(EN_VIP_CMDQ_CHECK_RETURN_ORI); //b ++ }*/ ++ ++ return n; ++ } ++ ++ return 0; ++} ++static DEVICE_ATTR(ckPQ,0600, check_PQ_show, check_PQ_store); ++static ssize_t VIPSetRule_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_VIPSetRuleShow(buf); ++} ++ ++static ssize_t VIPSetRule_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ if(NULL != buf) ++ { ++ const char *str = buf; ++ if((int)*str == 49) //input 1 echo 1 > ++ { ++ MsOS_SetVIPSetRule(E_VIPSetRule_CMDQAct); ++ } ++ else if((int)*str == 48) //input 0 echo 0 > ++ { ++ MsOS_SetVIPSetRule(E_VIPSetRule_Default); ++ } ++ else if((int)*str == 50) //input 2 echo 2 > ++ { ++ MsOS_SetVIPSetRule(E_VIPSetRule_CMDQCheck); ++ } ++ else if((int)*str == 51) //input 3 echo 3 > ++ { ++ MsOS_SetVIPSetRule(E_VIPSetRule_CMDQAll); ++ } ++ else if((int)*str == 52) //input 4 echo 4 > ++ { ++ MsOS_SetVIPSetRule(E_VIPSetRule_CMDQAllONLYSRAMCheck); ++ } ++ else if((int)*str == 53) //input 4 echo 5 > ++ { ++ MsOS_SetVIPSetRule(E_VIPSetRule_CMDQAllCheck); ++ } ++ ++ return n; ++ } ++ ++ return 0; ++} ++static DEVICE_ATTR(VIPSetRule,0600, VIPSetRule_show, VIPSetRule_store); ++ ++static ssize_t CMDQ_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_CMDQShow(buf); ++} ++ ++ ++static DEVICE_ATTR(CMDQ,0400, CMDQ_show, NULL); ++static ssize_t VIP_show(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return MDrv_VIP_VIPShow(buf); ++} ++static ssize_t VIP_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t n) ++{ ++ MDrv_VIP_VIPStore(buf); ++ return n; ++} ++ ++static DEVICE_ATTR(VIPStatus,0600, VIP_show, VIP_store); ++ ++void _mdrv_ms_vip_LogConfigStruct(ST_MDRV_VIP_SETPQ_CONFIG *stSetPQCfg) ++{ ++ unsigned char u8offset; ++ unsigned char *pu8value = NULL; ++ for(u8offset = 0;u8offset < stSetPQCfg->u32StructSize;u8offset++) ++ { ++ pu8value = stSetPQCfg->pPointToCfg + u8offset*1; ++ SCL_DBG(SCL_DBG_LV_VIP_LOG(), "[VIP] offset%hhd:%hhx \n",u8offset,*pu8value); ++ ++ } ++} ++void _mdrv_ms_vip_LogConfigByIP(EN_VIP_CONFIG_TYPE enVIPtype,unsigned char *pPointToCfg) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ MDrv_VIP_FillBasicStructSetPQCfg((EN_VIP_MDRV_CONFIG_TYPE)enVIPtype,pPointToCfg,&stSetPQCfg); ++ _mdrv_ms_vip_LogConfigStruct(&stSetPQCfg); ++} ++void _mdrv_ms_vip_io_fill_versionchkstruct ++(unsigned int u32StructSize,unsigned int u32VersionSize,unsigned int *pVersion,ST_MDRV_VIP_VERSIONCHK_CONFIG *stVersion) ++{ ++ stVersion->u32StructSize = (unsigned int)u32StructSize; ++ stVersion->u32VersionSize = (unsigned int)u32VersionSize; ++ stVersion->pVersion = (unsigned int *)pVersion; ++} ++int _mdrv_ms_vip_io_version_check(ST_MDRV_VIP_VERSIONCHK_CONFIG *stVersion) ++{ ++ if ( CHK_VERCHK_HEADER(stVersion->pVersion) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( stVersion->pVersion, IOCTL_VIP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[VIP] Version(%04x) < %04x!!! \n", ++ *(stVersion->pVersion) & VERCHK_VERSION_MASK, ++ IOCTL_VIP_VERSION); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &stVersion->u32VersionSize, stVersion->u32StructSize) == 0 ) ++ { ++ VERCHK_ERR("[VIP] Size(%04x) != %04x!!! \n", ++ stVersion->u32StructSize, ++ stVersion->u32VersionSize); ++ ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[VIP] Size(%d) \n",stVersion->u32StructSize ); ++ return VersionCheckSuccess; ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[VIP] No Header !!! \n"); ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EFAULT; ++ } ++} ++int _mdrv_ms_vip_io_set_peaking_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_PEAKING_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_PEAKING_CONFIG), ++ (((ST_IOCTL_VIP_PEAKING_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_PEAKING_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_PEAKING_CONFIG *)arg, sizeof(ST_IOCTL_VIP_PEAKING_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_PEAKING_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetPeakingConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_dlc_histogram_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG), ++ (((ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG *)arg, sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_DLC_HISTOGRAM_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetHistogramConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_get_dlc_histogram_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT stCfg; ++ ++ if(!MDrv_VIP_GetDLCHistogramReport((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ if (copy_to_user( (ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT __user *)arg, &stCfg, sizeof(ST_IOCTL_VIP_DLC_HISTOGRAM_REPORT) )) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_dlc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_DLC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_DLC_CONFIG), ++ (((ST_IOCTL_VIP_DLC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_DLC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_DLC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_DLC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_DLC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetDLCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_lce_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LCE_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LCE_CONFIG), ++ (((ST_IOCTL_VIP_LCE_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LCE_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_LCE_CONFIG *)arg, sizeof(ST_IOCTL_VIP_LCE_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LCE_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLCEConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_uvc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_UVC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_UVC_CONFIG), ++ (((ST_IOCTL_VIP_UVC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_UVC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_UVC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_UVC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_UVC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetUVCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_ihc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_IHC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_IHC_CONFIG), ++ (((ST_IOCTL_VIP_IHC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_IHC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_IHC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_IHC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_IHC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetIHCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_icc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_ICC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_ICC_CONFIG), ++ (((ST_IOCTL_VIP_ICC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_ICC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_ICC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_ICC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_ICC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetICEConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ihc_ice_adp_y_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_IHCICC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_IHCICC_CONFIG), ++ (((ST_IOCTL_VIP_IHCICC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_IHCICC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_IHCICC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_IHCICC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_IHCICC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetIHCICCADPYConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ibc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_IBC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_IBC_CONFIG), ++ (((ST_IOCTL_VIP_IBC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_IBC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_IBC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_IBC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_IBC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetIBCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_fcc_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_FCC_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_FCC_CONFIG), ++ (((ST_IOCTL_VIP_FCC_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_FCC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_FCC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_FCC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_FCC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetFCCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_nlm_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_NLM_CONFIG stIOCfg; ++ ST_MDRV_VIP_NLM_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_NLM_CONFIG), ++ (((ST_IOCTL_VIP_NLM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_NLM_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stIOCfg, (__user ST_IOCTL_VIP_NLM_CONFIG *)arg, sizeof(ST_IOCTL_VIP_NLM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ memcpy(&stCfg,&stIOCfg,sizeof(ST_IOCTL_VIP_NLM_CONFIG)); ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_NLM_CONFIG,(unsigned char *)&stIOCfg); ++ if(!MDrv_VIP_SetNLMConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ if(stIOCfg.stSRAM.bEn) ++ { ++ MDrv_VIP_SetNLMSRAMConfig(&stCfg.stSRAM); ++ } ++ else if(!stIOCfg.stSRAM.bEn && stIOCfg.stSRAM.u32viradr) ++ { ++ MDrv_VIP_SetNLMSRAMConfig(&stCfg.stSRAM); ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ack_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_ACK_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_ACK_CONFIG), ++ (((ST_IOCTL_VIP_ACK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_ACK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_ACK_CONFIG *)arg, sizeof(ST_IOCTL_VIP_ACK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_ACK_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetACKConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_set_mcnr_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_MCNR_CONFIG stioCfg; ++ ST_MDRV_VIP_MCNR_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_MCNR_CONFIG), ++ (((ST_IOCTL_VIP_MCNR_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_MCNR_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stioCfg, (__user ST_IOCTL_VIP_MCNR_CONFIG *)arg, sizeof(ST_IOCTL_VIP_MCNR_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stCfg.u32Viraddr = stioCfg.u32Viraddr; ++ stCfg.bEnMCNR = stioCfg.bEnMCNR; ++ stCfg.bEnCIIR = stioCfg.bEnCIIR; ++ memcpy(&stCfg.stFCfg,&stioCfg.stFCfg,sizeof(ST_MDRV_VIP_FC_CONFIG)); ++ } ++ } ++ if(!MDrv_VIP_SetMCNRConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_aip_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_AIP_CONFIG stioCfg; ++ ST_MDRV_VIP_AIP_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ MsOS_Memset(&stioCfg,0,sizeof(ST_IOCTL_VIP_AIP_CONFIG)); ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_AIP_CONFIG), ++ (((ST_IOCTL_VIP_AIP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_AIP_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stioCfg, (__user ST_IOCTL_VIP_AIP_CONFIG *)arg, sizeof(ST_IOCTL_VIP_AIP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stCfg.u32Viraddr = stioCfg.u32Viraddr; ++ if(stioCfg.enAIPTypeVerChk_Size), ++ &(((ST_IOCTL_VIP_AIP_SRAM_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ if(copy_from_user(&stioCfg, (__user ST_IOCTL_VIP_AIP_SRAM_CONFIG *)arg, sizeof(ST_IOCTL_VIP_AIP_SRAM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ else ++ { ++ stCfg.u32Viraddr = stioCfg.u32Viraddr; ++ if(stioCfg.enAIPTypeVerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_LDC_CONFIG *)arg, sizeof(ST_IOCTL_VIP_LDC_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_vip_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_CONFIG), ++ (((ST_IOCTL_VIP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_CONFIG *)arg, sizeof(ST_IOCTL_VIP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_SetVIPOtherConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_md_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_MD_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_MD_CONFIG), ++ (((ST_IOCTL_VIP_LDC_MD_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_MD_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_LDC_MD_CONFIG *)arg, sizeof(ST_IOCTL_VIP_LDC_MD_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_MD_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCmdConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_dmap_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_DMAP_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_DMAP_CONFIG), ++ (((ST_IOCTL_VIP_LDC_DMAP_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_DMAP_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_LDC_DMAP_CONFIG *)arg, sizeof(ST_IOCTL_VIP_LDC_DMAP_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_DMAP_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCDmapConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_ldc_sram_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_LDC_SRAM_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_LDC_SRAM_CONFIG), ++ (((ST_IOCTL_VIP_LDC_SRAM_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_LDC_SRAM_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_LDC_SRAM_CONFIG *)arg, sizeof(ST_IOCTL_VIP_LDC_SRAM_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ _mdrv_ms_vip_LogConfigByIP(EN_VIP_LDC_SRAM_CONFIG,(unsigned char *)&stCfg); ++ if(!MDrv_VIP_SetLDCSRAMConfig((void *)&stCfg)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_vtrack_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_VTRACK_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_VTRACK_CONFIG), ++ (((ST_IOCTL_VIP_VTRACK_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_VTRACK_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_VTRACK_CONFIG *)arg, sizeof(ST_IOCTL_VIP_VTRACK_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(stCfg.bSetKey) ++ { ++ MDrv_VIP_VtrackSetPayloadData(stCfg.u16Timecode,stCfg.u8OperatorID); ++ MDrv_VIP_VtrackSetKey(stCfg.bSetKey,stCfg.u8SetKey); ++ } ++ else ++ { ++ MDrv_VIP_VtrackSetPayloadData(stCfg.u16Timecode,stCfg.u8OperatorID); ++ MDrv_VIP_VtrackSetKey(0,NULL); ++ } ++ if(stCfg.bSetUserDef) ++ { ++ MDrv_VIP_VtrackSetUserDefindedSetting(stCfg.bSetUserDef,stCfg.u8SetUserDef); ++ } ++ else ++ { ++ MDrv_VIP_VtrackSetUserDefindedSetting(0,NULL); ++ } ++ return 0; ++} ++ ++int _mdrv_ms_vip_io_set_vtrack_onoff_config(struct file *filp, unsigned long arg) ++{ ++ ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG stCfg; ++ ST_MDRV_VIP_VERSIONCHK_CONFIG stVersion; ++ ++ _mdrv_ms_vip_io_fill_versionchkstruct(sizeof(ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG), ++ (((ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG __user *)arg)->VerChk_Size), ++ &(((ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG __user *)arg)->VerChk_Version),&stVersion); ++ if(_mdrv_ms_vip_io_version_check(&stVersion)) ++ { ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ return -EINVAL; ++ } ++ else ++ { ++ if(copy_from_user(&stCfg, (__user ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG *)arg, sizeof(ST_IOCTL_VIP_VTRACK_ONOFF_CONFIG))) ++ { ++ return -EFAULT; ++ } ++ } ++ ++ if(!MDrv_VIP_VtrackEnable(stCfg.u8framerate,(EN_VIP_MDRV_VTRACK_ENABLE_TYPE)stCfg.EnType)) ++ { ++ return -EFAULT; ++ } ++ ++ return 0; ++} ++ ++ ++int _mdrv_ms_vip_io_get_version(struct file *filp, unsigned long arg) ++{ ++ int ret = 0; ++ ++ if (CHK_VERCHK_HEADER( &(((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Version)) ) ++ { ++ if( CHK_VERCHK_MAJORVERSION_LESS( &(((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Version), IOCTL_VIP_VERSION) ) ++ { ++ ++ VERCHK_ERR("[VIP] Version(%04x) < %04x!!! \n", ++ ((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Version & VERCHK_VERSION_MASK, ++ IOCTL_VIP_VERSION); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ if( CHK_VERCHK_SIZE( &(((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Size), sizeof(ST_IOCTL_VIP_VERSION_CONFIG)) == 0 ) ++ { ++ VERCHK_ERR("[VIP] Size(%04x) != %04x!!! \n", ++ sizeof(ST_IOCTL_VIP_VERSION_CONFIG), ++ (((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg)->VerChk_Size)); ++ ++ ret = -EINVAL; ++ } ++ else ++ { ++ ST_IOCTL_VIP_VERSION_CONFIG stCfg; ++ ++ stCfg = FILL_VERCHK_TYPE(stCfg, stCfg.VerChk_Version, stCfg.VerChk_Size, IOCTL_VIP_VERSION); ++ stCfg.u32Version = IOCTL_VIP_VERSION; ++ ++ if(copy_to_user((ST_IOCTL_VIP_VERSION_CONFIG __user *)arg, &stCfg, sizeof(ST_IOCTL_VIP_VERSION_CONFIG))) ++ { ++ ret = -EFAULT; ++ } ++ else ++ { ++ ret = 0; ++ } ++ } ++ } ++ } ++ else ++ { ++ VERCHK_ERR("[VIP] No Header !!! \n"); ++ SCL_ERR( "[VIP] %s \n", __FUNCTION__); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++} ++ ++int _mdrv_ms_vip_io_set_allvip(struct file *filp, unsigned long arg) ++{ ++ return 0; ++} ++ ++//---------------------------------------------------------------------------------------------- ++ ++ ++//============================================================================== ++long mdrv_ms_vip_ioctl(struct file *filp, unsigned int u32Cmd, unsigned long u32Arg) ++{ ++ int err = 0; ++ int inswitch; ++ int retval = 0; ++ //static unsigned long long u64diffTime = 0; ++ unsigned long long u64Time = 0; ++ unsigned long long u64DiffTime = 0; ++ u64Time = MsOS_GetSystemTimeStamp(); ++ if(_dev_ms_vip.refCnt <= 0) ++ { ++ SCL_ERR( "[VIP] VIPIO_IOCTL refCnt =%d!!! \n", _dev_ms_vip.refCnt); ++ return -EFAULT; ++ } ++ /* check u32Cmd valid */ ++ if(IOCTL_VIP_MAGIC == _IOC_TYPE(u32Cmd)) ++ { ++ if(_IOC_NR(u32Cmd) >= IOCTL_VIP_MAX_NR) ++ { ++ SCL_ERR( "[VIP] IOCtl NR Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ } ++ else ++ { ++ SCL_ERR( "[VIP] IOCtl MAGIC Error!!! (Cmd=%x)\n",u32Cmd); ++ return -ENOTTY; ++ } ++ ++ /* verify Access */ ++ if (_IOC_DIR(u32Cmd) & _IOC_READ) ++ { ++ err = !access_ok(VERIFY_WRITE, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ else if (_IOC_DIR(u32Cmd) & _IOC_WRITE) ++ { ++ err = !access_ok(VERIFY_READ, (void __user *)u32Arg, _IOC_SIZE(u32Cmd)); ++ } ++ if (err) ++ { ++ return -EFAULT; ++ } ++ /* not allow query or command once driver suspend */ ++ // TODO: CMDQ ++ if(VIPSETRULE()) ++ { ++ inswitch = 1; ++ } ++ else ++ { ++ if(MDrv_VIP_GetIsBlankingRegion()) ++ { ++ inswitch = 1; ++ } ++ else ++ { ++ inswitch = 0; ++ } ++ } ++ if(inswitch) ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_VIP, "[VIP] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ switch(u32Cmd) ++ { ++ case IOCTL_VIP_CMDQ_WRITE_CONFIG: ++ retval = _mdrv_ms_vip_io_cmdq_write_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_MD_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_md_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_DMAP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_dmap_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LDC_SRAM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ldc_sram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_MCNR_CONFIG: ++ retval = _mdrv_ms_vip_io_set_mcnr_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_PEAKING_CONFIG: ++ retval = _mdrv_ms_vip_io_set_peaking_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_DLC_HISTOGRAM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_dlc_histogram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT: ++ retval = _mdrv_ms_vip_io_get_dlc_histogram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_DLC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_dlc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_LCE_CONFIG: ++ retval = _mdrv_ms_vip_io_set_lce_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_UVC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_uvc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_IHC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ihc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_ICE_CONFIG: ++ retval = _mdrv_ms_vip_io_set_icc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_IHC_ICE_ADP_Y_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ihc_ice_adp_y_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_IBC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ibc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_FCC_CONFIG: ++ retval = _mdrv_ms_vip_io_set_fcc_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_ACK_CONFIG: ++ retval = _mdrv_ms_vip_io_set_ack_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_NLM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_nlm_config(filp, u32Arg); ++ break; ++ ++ case IOCTL_VIP_SET_VIP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_vip_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_AIP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_aip_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_AIP_SRAM_CONFIG: ++ retval = _mdrv_ms_vip_io_set_aip_sram_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_VTRACK_CONFIG: ++ retval = _mdrv_ms_vip_io_set_vtrack_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_SET_VTRACK_ONOFF_CONFIG: ++ retval = _mdrv_ms_vip_io_set_vtrack_onoff_config(filp, u32Arg); ++ break; ++ case IOCTL_VIP_GET_VERSION_CONFIG: ++ retval = _mdrv_ms_vip_io_get_version(filp, u32Arg); ++ break; ++ case IOCLT_VIP_SET_ALLVIP_CONFIG: ++ retval = _mdrv_ms_vip_io_set_allvip(filp, u32Arg); ++ break; ++ default: /* redundant, as cmd was checked against MAXNR */ ++ SCL_ERR( "[VIP] ERROR IOCtl number %x\n ",u32Cmd); ++ retval = -ENOTTY; ++ break; ++ } ++ } ++ else if(u32Cmd == IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT) ++ { ++ retval = _mdrv_ms_vip_io_get_dlc_histogram_config(filp, u32Arg); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_VIP, "[VIP] IOCTL_NUM:: == %s == \n", (CMD_PARSING(u32Cmd))); ++ SCL_DBGERR( "[VIP] Not In Blanking \n"); ++ retval = -EIO; ++ } ++ u64DiffTime = MsOS_GetSystemTimeStamp() - u64Time; ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_ELSE, "[VIP]= %s = Diff:%llu \n", (CMD_PARSING(u32Cmd)),u64DiffTime); ++ return retval; ++} ++ ++ ++static unsigned int mdrv_ms_vip_poll(struct file *filp, struct poll_table_struct *wait) ++{ ++ unsigned int ret = 0; ++ wait_queue_head_t *event_wait_queue = NULL; ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_VIP, "[VIP]start %s ret=%x\n",__FUNCTION__,ret); ++ event_wait_queue = (wait_queue_head_t *)MDrv_VIP_GetWaitQueueHead(); ++ MDrv_VIP_SetPollWait(filp, event_wait_queue, wait); ++ if(MDrv_VIP_GetCMDQHWDone()) ++ { ++ ret = POLLIN; ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++static void* alloc_dmem(const char* name, unsigned int size, dma_addr_t *addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ //void *virr; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ /* ++ virr = MsOS_Memalloc(size,GFP_KERNEL); ++ if(!virr) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init virr Fail\n", __FUNCTION__, __LINE__); ++ return NULL; ++ } ++ MsOS_Memset(virr,0,size); ++ dmem.kvirt = (unsigned long)virr; ++ dmem.phys = dmem.kvirt&0x1FFFFFFF; ++ */ ++ if(0 != msys_request_dmem(&dmem)){ ++ return NULL; ++ } ++ *addr = dmem.phys; ++ return (void *)((uintptr_t)dmem.kvirt); ++} ++ ++static void free_dmem(const char* name, unsigned int size, void *virt, dma_addr_t addr) ++{ ++ MSYS_DMEM_INFO dmem; ++ memcpy(dmem.name,name,strlen(name)+1); ++ dmem.length = size; ++ dmem.kvirt = (unsigned long long)((uintptr_t)virt); ++ dmem.phys = (unsigned long long)((uintptr_t)addr); ++ //msys_release_dmem(&dmem); ++ MsOS_MemFree(virt); ++} ++ ++static int _ms_vip_mem_allocate(void) ++{ ++ if (!(sg_vip_cmdq_vir_addr = alloc_dmem(KEY_DMEM_VIP_CMDQ, ++ PAGE_ALIGN(sg_vip_cmdq_size), ++ &sg_vip_cmdq_bus_addr))) ++ { ++ SCL_ERR( "%s: unable to allocate screen memory\n", __FUNCTION__); ++ return 0; ++ } ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[CMDQ]: CMDQ: Phy:%x Vir:%x\n", sg_vip_cmdq_bus_addr, (u32)sg_vip_cmdq_vir_addr); ++ gstInitCMDQCfg.u32CMDQ_Phy = Chip_Phys_to_MIU(sg_vip_cmdq_bus_addr); ++ //gstInitCMDQCfg.u32CMDQ_Phy = sg_vip_cmdq_bus_addr; ++ gstInitCMDQCfg.u32CMDQ_Size = sg_vip_cmdq_size; ++ gstInitCMDQCfg.u32CMDQ_Vir = (unsigned long)sg_vip_cmdq_vir_addr; ++ return 1; ++} ++ ++static void _ms_vip_mem_free(void) ++{ ++ free_dmem(KEY_DMEM_VIP_CMDQ, ++ PAGE_ALIGN(sg_vip_cmdq_size), ++ sg_vip_cmdq_vir_addr, ++ sg_vip_cmdq_bus_addr); ++ ++} ++#if CONFIG_OF ++static int mdrv_ms_vip_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ int s32Ret; ++ dev_t dev; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ //mod ++ if(_dev_ms_vip.s32Major) ++ { ++ dev = MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_vip.s32Minor, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ _dev_ms_vip.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[VIP] Unable to get major %d\n", _dev_ms_vip.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_vip.cdev, &_dev_ms_vip.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_vip.cdev, dev, MDRV_MS_VIP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[VIP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_vip_class = msys_get_sysfs_class(); ++ if(!m_vip_class) ++ { ++ m_vip_class = class_create(THIS_MODULE, vip_classname); ++ } ++ if(IS_ERR(m_vip_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ _dev_ms_vip.devicenode =device_create(m_vip_class, NULL, dev,NULL, "mvip"); ++ _dev_ms_vip.devicenode->dma_mask=&ms_vip_dma_mask; ++ _dev_ms_vip.devicenode->coherent_dma_mask=ms_vip_dma_mask; ++ } ++ //probe ++ if(of_property_read_u32(pdev->dev.of_node, "CMDQ-mode", &gu32CMDQmode)) ++ { ++ printk(KERN_WARNING "[VIP] Failed to read CMDQ-mode property, default on/n"); ++ gu32CMDQmode = 1; //if can't get, default on ++ } ++ if(!gu32CMDQmode) ++ { ++ printk(KERN_WARNING "[VIP]gu32CMDQmode off/n"); ++ sg_vip_cmdq_size = VIP_CMDQ_MEM_16K; ++ MsOS_SetVIPSetRule(E_VIPSetRule_Default); ++ } ++ else ++ { ++ MsOS_SetVIPSetRule(VIPDEFAULTSETRULE); ++ } ++ if( _ms_vip_mem_allocate() == 0 ) ++ { ++ return -EFAULT; ++ } ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ stVipInitCfg.CMDQCfg.u32CMDQ_Phy = gstInitCMDQCfg.u32CMDQ_Phy; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Size = gstInitCMDQCfg.u32CMDQ_Size; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Vir = gstInitCMDQCfg.u32CMDQ_Vir; ++ if(MDrv_VIP_Init(&stVipInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_VIP_SuspendResetFlagInit(); ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_bypass)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_CMDQ)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_VIPStatus)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_ckCMDQ)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create dev_attr_ckCMDQ sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_ckPQ)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create dev_attr_ckPQ sysfs files\n"); ++ } ++ if (device_create_file(_dev_ms_vip.devicenode, &dev_attr_VIPSetRule)!= 0) ++ { ++ dev_err(_dev_ms_vip.devicenode, ++ "Failed to create dev_attr_VIPSetRule sysfs files\n"); ++ } ++ gbProbeAlready |= EN_DBG_VIP_CONFIG; ++ return 0; ++} ++ ++static int mdrv_ms_vip_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ gbProbeAlready = (gbProbeAlready&(~EN_DBG_VIP_CONFIG)); ++ if(gbProbeAlready == 0) ++ { ++ MDrv_VIP_Delete(1); ++ } ++ else ++ { ++ MDrv_VIP_Delete(0); ++ } ++ MDrv_VIP_FreeMemory(); ++ _ms_vip_mem_free(); ++ g_bVIPSysInitReady = 0; ++ cdev_del(&_dev_ms_vip.cdev); ++ device_destroy(m_vip_class, MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor)); ++ class_destroy(m_vip_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor), MDRV_MS_VIP_DEVICE_COUNT); ++ return 0; ++} ++ ++#else ++static int mdrv_ms_vip_probe(struct platform_device *pdev) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ if( _ms_vip_mem_allocate() == 0 ) ++ { ++ return -EFAULT; ++ } ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ stVipInitCfg.CMDQCfg.u32CMDQ_Phy = gstInitCMDQCfg.u32CMDQ_Phy; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Size = gstInitCMDQCfg.u32CMDQ_Size; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Vir = gstInitCMDQCfg.u32CMDQ_Vir; ++ if(MDrv_VIP_Init(&stVipInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ MDrv_VIP_SuspendResetFlagInit(); ++ if (device_create_file(&pdev->dev, &dev_attr_bypass)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create bypass sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckCMDQ)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create dev_attr_ckCMDQ sysfs files\n"); ++ } ++ if (device_create_file(&pdev->dev, &dev_attr_ckPQ)!= 0) ++ { ++ dev_err(&pdev->dev, ++ "Failed to create dev_attr_ckPQ sysfs files\n"); ++ } ++ ++ return 0; ++} ++ ++static int mdrv_ms_vip_remove(struct platform_device *pdev) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ MDrv_VIP_Delete(); ++ _ms_vip_mem_free(); ++ g_bVIPSysInitReady = 0; ++ return 0; ++} ++#endif ++ ++static int mdrv_ms_vip_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ g_bVIPSysInitReady = 0; ++ MDrv_VIP_Supend(); ++ ++ return 0; ++} ++ ++ ++static int mdrv_ms_vip_resume(struct platform_device *dev) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ stVipInitCfg.CMDQCfg.u32CMDQ_Phy = gstInitCMDQCfg.u32CMDQ_Phy; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Size = gstInitCMDQCfg.u32CMDQ_Size; ++ stVipInitCfg.CMDQCfg.u32CMDQ_Vir = gstInitCMDQCfg.u32CMDQ_Vir; ++ MDrv_VIP_Resume(&stVipInitCfg); ++ MDrv_VIP_ResetEachIP(); ++ MDrv_VIP_Sys_Init(&stVipInitCfg); ++ MDrv_VIP_SuspendResetFlagInit(); ++ g_bVIPSysInitReady = 1; ++ return 0; ++} ++ ++ ++int mdrv_ms_vip_open(struct inode *inode, struct file *filp) ++{ ++ ST_MDRV_VIP_INIT_CONFIG stVipInitCfg; ++ ++ stVipInitCfg.u32RiuBase = 0x1F000000; //ToDo ++ if(g_bVIPSysInitReady == 0) ++ { ++ if(_dev_ms_vip.refCnt==0) ++ { ++ if(MDrv_VIP_Sys_Init(&stVipInitCfg) == 0) ++ { ++ return -EFAULT; ++ } ++ g_bVIPSysInitReady = 1; ++ } ++ } ++ ++ SCL_ASSERT(_dev_ms_vip.refCnt >= 0); ++ _dev_ms_vip.refCnt++; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,_dev_ms_vip.refCnt); ++ ++ ++ return 0; ++} ++ ++ ++int mdrv_ms_vip_release(struct inode *inode, struct file *filp) ++{ ++ _dev_ms_vip.refCnt--; ++ if(_dev_ms_vip.refCnt==0) ++ { ++ MDrv_VIP_Release(); ++ g_bVIPSysInitReady = 0; ++ } ++ SCL_ASSERT(_dev_ms_vip.refCnt >= 0); ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[HVSP1] %s:%d\n",__FUNCTION__,_dev_ms_vip.refCnt); ++ //free_irq(INT_IRQ_VIPW, MDrv_VIPW_isr); ++ return 0; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Module functions ++//------------------------------------------------------------------------------------------------- ++#if CONFIG_OF ++int _mdrv_ms_vip_init(void) ++{ ++ int ret = 0; ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s:%d\n",__FUNCTION__,__LINE__); ++ ret = platform_driver_register(&st_ms_vip_driver); ++ if (!ret) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] platform_driver_register success\n"); ++ if(gbProbeAlready&EN_DBG_VIP_CONFIG) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] Probe success\n"); ++ } ++ else ++ { ++ SCL_ERR( "[VIP] Probe Fail\n"); ++ } ++ if(gbProbeAlready==EN_DBG_SCL_CONFIG) ++ { ++ SCL_ERR( "[SCL] SCL init success\n"); ++ } ++ } ++ else ++ { ++ SCL_ERR( "[VIP] platform_driver_register failed\n"); ++ platform_driver_unregister(&st_ms_vip_driver); ++ } ++ ++ ++ return ret; ++} ++void _mdrv_ms_vip_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ platform_driver_unregister(&st_ms_vip_driver); ++} ++#else ++int _mdrv_ms_vip_init(void) ++{ ++ int ret = 0; ++ int s32Ret; ++ dev_t dev; ++ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ ++ if(_dev_ms_vip.s32Major) ++ { ++ dev = MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor); ++ s32Ret = register_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ } ++ else ++ { ++ s32Ret = alloc_chrdev_region(&dev, _dev_ms_vip.s32Minor, MDRV_MS_VIP_DEVICE_COUNT, MDRV_MS_VIP_NAME); ++ _dev_ms_vip.s32Major = MAJOR(dev); ++ } ++ ++ if (0 > s32Ret) ++ { ++ SCL_ERR( "[VIP] Unable to get major %d\n", _dev_ms_vip.s32Major); ++ return s32Ret; ++ } ++ ++ cdev_init(&_dev_ms_vip.cdev, &_dev_ms_vip.fops); ++ if (0 != (s32Ret= cdev_add(&_dev_ms_vip.cdev, dev, MDRV_MS_VIP_DEVICE_COUNT))) ++ { ++ SCL_ERR( "[VIP] Unable add a character device\n"); ++ unregister_chrdev_region(dev, MDRV_MS_VIP_DEVICE_COUNT); ++ return s32Ret; ++ } ++ ++ m_vip_class = class_create(THIS_MODULE, vip_classname); ++ if(IS_ERR(m_vip_class)) ++ { ++ printk(KERN_WARNING"Failed at class_create().Please exec [mknod] before operate the device/n"); ++ } ++ else ++ { ++ device_create(m_vip_class, NULL, dev,NULL, "mvip"); ++ } ++ ++ /* initial the whole VIP Driver */ ++ ret = platform_driver_register(&st_ms_vip_driver); ++ ++ if (!ret) ++ { ++ ret = platform_device_register(&st_ms_vip_device); ++ if (ret) /* if register device fail, then unregister the driver.*/ ++ { ++ platform_driver_unregister(&st_ms_vip_driver); ++ SCL_ERR( "[VIP] platform_driver_register failed\n"); ++ ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] platform_driver_register success\n"); ++ } ++ } ++ ++ ++ return ret; ++} ++ ++ ++void _mdrv_ms_vip_exit(void) ++{ ++ /*de-initial the who GFLIPDriver */ ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[VIP] %s\n",__FUNCTION__); ++ ++ cdev_del(&_dev_ms_vip.cdev); ++ device_destroy(m_vip_class, MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor)); ++ class_destroy(m_vip_class); ++ unregister_chrdev_region(MKDEV(_dev_ms_vip.s32Major, _dev_ms_vip.s32Minor), MDRV_MS_VIP_DEVICE_COUNT); ++ platform_driver_unregister(&st_ms_vip_driver); ++} ++#endif ++ ++module_init(_mdrv_ms_vip_init); ++module_exit(_mdrv_ms_vip_exit); ++ ++MODULE_AUTHOR("MSTAR"); ++MODULE_DESCRIPTION("ms vip ioctrl driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/mstar/scl/infinity3/src/mdrv_hvsp.c b/drivers/mstar/scl/infinity3/src/mdrv_hvsp.c +new file mode 100644 +index 00000000..cbe581d3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mdrv_hvsp.c +@@ -0,0 +1,1771 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_HVSP_C ++ ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++//#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++ ++//#include "mdrv_hvsp_io_i3_st.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_multiinst.h" ++#include "drvpnl.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define PARSING_PAT_TGEN_TIMING(x) (x == E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30 ? "E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30" : \ ++ x == E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60 ? "E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60" : \ ++ x == E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60 ? "E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60" : \ ++ x == E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED ? "E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED" : \ ++ "UNKNOWN") ++#define Is_Wrong_Type(enHVSP_ID,enSrcType)((enHVSP_ID == E_MDRV_HVSP_ID_1 && (enSrcType == E_MDRV_HVSP_SRC_DRAM)) ||\ ++ (enHVSP_ID == E_MDRV_HVSP_ID_2 && enSrcType != E_MDRV_HVSP_SRC_HVSP) ||\ ++ (enHVSP_ID == E_MDRV_HVSP_ID_3 && enSrcType != E_MDRV_HVSP_SRC_DRAM)) ++#define Is_PTGEN_FHD(u16Htotal,u16Vtotal,u16Vfrequency) ((u16Htotal) == 2200 && (u16Vtotal) == 1125 && (u16Vfrequency) == 30) ++#define Is_PTGEN_HD(u16Htotal,u16Vtotal,u16Vfrequency) ((u16Htotal) == 1344 && (u16Vtotal) == 806 && (u16Vfrequency) == 60) ++#define Is_PTGEN_SD(u16Htotal,u16Vtotal,u16Vfrequency) ((u16Htotal) == 800 && (u16Vtotal) == 525 && (u16Vfrequency) == 60) ++#define IS_HVSPNotOpen(u16Src_Width,u16Dsp_Width) (u16Src_Width == 0 && u16Dsp_Width == 0) ++#define IS_NotScalingAfterCrop(bEn,u16Dsp_Height,u16Height,u16Dsp_Width,u16Width) (bEn && \ ++ (u16Dsp_Height == u16Height) && (u16Dsp_Width== u16Width)) ++#define RATIO_CONFIG 512 ++#define CAL_HVSP_RATIO(input,output) ((unsigned long)((unsigned long long)((unsigned long)input * RATIO_CONFIG )/(unsigned long)output)) ++#define SCALE(numerator, denominator,value) ((unsigned short)((unsigned long)(value * RATIO_CONFIG * numerator) / (denominator * RATIO_CONFIG))) ++ ++#define PriMaskPercentBase 10000 ++#define MDRV_HVSP_MUTEX_LOCK() MsOS_ObtainMutex(_MHVSP_Mutex,MSOS_WAIT_FOREVER) ++#define MDRV_HVSP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_MHVSP_Mutex) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ST_MDRV_HVSP_SCALING_CONFIG gstHvspScalingCfg; ++ST_MDRV_HVSP_POSTCROP_CONFIG gstHvspPostCropCfg; ++ST_MDRV_HVSP_PRIMASK_CONFIG gstHvspPriMaskCfg[MDRV_MULTI_INST_PRIVATE_ID_NUM][PriMaskNum]; ++unsigned char gu8PriMaskNum[MDRV_MULTI_INST_PRIVATE_ID_NUM]; ++unsigned char gu8PriMaskInst; ++///////////////// ++/// gbMemReadyForMdrv ++/// if True ,DNR buffer was allocated. ++//////////////// ++unsigned char gbMemReadyForMdrv; ++unsigned char gu8IPMBufferNum; ++ST_DRV_HVSP_PAT_TGEN_CONFIG gstPatTgenCfg[E_MDRV_HVSP_PAT_TGEN_TIMING_MAX] = ++{ ++ {1125, 4, 5, 36, 1080, 2200, 88, 44, 148, 1920}, // 1920_1080_30 ++ { 806, 3, 6, 29, 768, 1344, 24, 136, 160, 1024}, // 1024_768_60 ++ { 525, 33, 2, 10, 480, 800, 16, 96, 48, 640}, // 640_480_60 ++ { 0, 20, 10, 20, 0, 0, 30, 15, 30, 0}, // undefined ++}; ++MS_S32 _MHVSP_Mutex = -1; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++unsigned char MDrv_HVSP_GetCMDQDoneStatus(EN_MDRV_HVSP_ID_TYPE enHVSP_ID) ++{ ++ EN_HVSP_POLL_ID_TYPE enPollId; ++ enPollId = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_POLL_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_POLL_ID_3 : ++ E_HVSP_POLL_ID_1; ++ return Drv_HVSP_GetCMDQDoneStatus(enPollId); ++} ++ ++void * MDrv_HVSP_GetWaitQueueHead(void) ++{ ++ return Drv_HVSP_GetWaitQueueHead(); ++} ++void MDrv_HVSP_SetPollWait ++ (void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ MsOS_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++} ++unsigned char MDrv_HVSP_Suspend(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_HVSP_SUSPEND_RESUME_CONFIG stSuspendResumeCfg; ++ unsigned char bRet = TRUE;; ++ MsOS_Memset(&stSuspendResumeCfg,0,sizeof(ST_HVSP_SUSPEND_RESUME_CONFIG)); ++ stSuspendResumeCfg.u32IRQNUM = pCfg->u32IRQNum; ++ stSuspendResumeCfg.u32CMDQIRQNUM = pCfg->u32CMDQIRQNum; ++ if(Drv_HVSP_Suspend(&stSuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP]%s Suspend Fail\n", __FUNCTION__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++ ++unsigned char MDrv_HVSP_Resume(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_HVSP_SUSPEND_RESUME_CONFIG stSuspendResumeCfg; ++ unsigned char bRet = TRUE;; ++ MsOS_Memset(&stSuspendResumeCfg,0,sizeof(ST_HVSP_SUSPEND_RESUME_CONFIG)); ++ stSuspendResumeCfg.u32IRQNUM = pCfg->u32IRQNum; ++ stSuspendResumeCfg.u32CMDQIRQNUM = pCfg->u32CMDQIRQNum; ++ if(Drv_HVSP_Resume(&stSuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP]%s Resume Fail\n", __FUNCTION__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++void _MDrv_HVSP_ResetPriMaskStorage(void) ++{ ++ MDRV_HVSP_MUTEX_LOCK(); ++ MsOS_Memset(&gstHvspPriMaskCfg[gu8PriMaskInst], 0, sizeof(ST_MDRV_HVSP_PRIMASK_CONFIG)*PriMaskNum); ++ gu8PriMaskNum[gu8PriMaskInst] = 0; ++ MDRV_HVSP_MUTEX_UNLOCK(); ++} ++void _MDrv_HVSP_SWinit(void) ++{ ++ unsigned char i; ++ MDRV_HVSP_MUTEX_LOCK(); ++ MsOS_Memset(&gstHvspScalingCfg, 0, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ MsOS_Memset(&gstHvspPostCropCfg, 0, sizeof(ST_MDRV_HVSP_POSTCROP_CONFIG)); ++ MDRV_HVSP_MUTEX_UNLOCK(); ++ for(i = 0 ;i u32Riubase; ++ stInitCfg.u32IRQNUM = pCfg ->u32IRQNUM; ++ stInitCfg.u32CMDQIRQNUM = pCfg ->u32CMDQIRQNUM; ++ gu8IPMBufferNum = DNRBufferMode; ++ Drv_HVSP_SetBufferNum(gu8IPMBufferNum); ++ if(Drv_HVSP_Init(&stInitCfg) == FALSE) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP]%s Init Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ else ++ { ++ if(bInit == FALSE) ++ { ++ _MDrv_HVSP_SWinit(); ++ } ++ bInit = TRUE; ++ ++ return TRUE; ++ } ++ ++} ++void MDrv_HVSP_SetMemoryAllocateReady(unsigned char bEn) ++{ ++ MDRV_HVSP_MUTEX_LOCK(); ++ gbMemReadyForMdrv = bEn; ++ MDRV_HVSP_MUTEX_UNLOCK(); ++ Drv_HVSP_SetMemoryAllocateReady(gbMemReadyForMdrv); ++} ++void _MDrv_HVSP_FillIPMStruct(ST_MDRV_HVSP_IPM_CONFIG *pCfg,ST_HVSP_IPM_CONFIG *stIPMCfg) ++{ ++ stIPMCfg->u16Fetch = pCfg->u16Width; ++ stIPMCfg->u16Vsize = pCfg->u16Height; ++ stIPMCfg->bYCMRead = (unsigned char)((pCfg->enRW)&E_MDRV_HVSP_MCNR_YCM_R); ++ stIPMCfg->bYCMWrite = (unsigned char)(((pCfg->enRW)&E_MDRV_HVSP_MCNR_YCM_W)>>1); ++ stIPMCfg->bCIIRRead = (unsigned char)(((pCfg->enRW)&E_MDRV_HVSP_MCNR_CIIR_R)>>2); ++ stIPMCfg->bCIIRWrite = (unsigned char)(((pCfg->enRW)&E_MDRV_HVSP_MCNR_CIIR_W)>>3); ++ stIPMCfg->u32YCBaseAddr = pCfg->u32YCPhyAddr; ++ stIPMCfg->u32MBaseAddr = pCfg->u32MPhyAddr; ++ stIPMCfg->u32CIIRBaseAddr = pCfg->u32CIIRPhyAddr; ++ stIPMCfg->u32MemSize = pCfg->u32MemSize; ++} ++ ++void _MDrv_HVSP_FillLDCStruct ++ (ST_MDRV_HVSP_IPM_CONFIG *pCfg, MS_BOOL bWrite,ST_HVSP_LDC_FRAMEBUFFER_CONFIG *stLDCCfg) ++{ ++ stLDCCfg->bEnSWMode = 0x00; ++ stLDCCfg->enLDCType = EN_DRV_HVSP_LDCLCBANKMODE_128; ++ stLDCCfg->u16Height = pCfg->u16Height; ++ if(pCfg->u16Width == 2048) ++ { ++ stLDCCfg->u16Width = pCfg->u16Width -1; ++ } ++ else ++ { ++ stLDCCfg->u16Width = pCfg->u16Width; ++ } ++ stLDCCfg->u32FBaddr = pCfg->u32YCPhyAddr; ++ stLDCCfg->u8FBidx = 0x00; ++ stLDCCfg->u8FBrwdiff = SCL_DELAY2FRAMEINDOUBLEBUFFERMode ? 0x0 : 0x1; ++ // delay 1 frame, set 1 is true, because Frame_buffer_idx = hw_w_idx - reg_ldc_fb_hw_rw_diff ++ // So ,if want delay 2 frame, need to set '0' for 2 DNR buffer. ++ //if only 1 DNR buffer , set '0' also delay 1 frame. ++ stLDCCfg->bEnDNR = bWrite; ++} ++unsigned char MDrv_HVSP_SetInitIPMConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_IPM_CONFIG *pCfg) ++{ ++ ST_HVSP_IPM_CONFIG stIPMCfg; ++ ST_HVSP_LDC_FRAMEBUFFER_CONFIG stLDCCfg; ++ if(enHVSP_ID != E_MDRV_HVSP_ID_1) ++ { ++ SCL_ERR( "[HVSP]%s ID not correct: %d\n", __FUNCTION__, enHVSP_ID); ++ return FALSE; ++ } ++ MsOS_Memset(&stIPMCfg,0,sizeof(ST_HVSP_IPM_CONFIG)); ++ MsOS_Memset(&stLDCCfg,0,sizeof(ST_HVSP_LDC_FRAMEBUFFER_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s:%d:PhyAddr=%lx, width=%x, height=%x \n", __FUNCTION__,enHVSP_ID, pCfg->u32YCPhyAddr, pCfg->u16Width, pCfg->u16Height); ++ _MDrv_HVSP_FillIPMStruct(pCfg,&stIPMCfg); ++ _MDrv_HVSP_FillLDCStruct(pCfg, (stIPMCfg.bYCMRead ? 0 :1),&stLDCCfg); ++ Drv_HVSP_SetLDCFrameBuffer_Config(&stLDCCfg); ++ // ToDo ++ // Drv_HVSP_SetPrv2CropOnOff(stIPMCfg.bYCMRead); ++ if(Drv_HVSP_Set_IPM_Config(&stIPMCfg) == FALSE) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP] Set IPM Config Fail\n"); ++ return FALSE; ++ } ++ else ++ { ++ return TRUE;; ++ } ++} ++ ++ ++EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE _MDrv_HVSP_GetPatTGenTiming(ST_MDRV_HVSPTIMING_CONFIG *pTiming) ++{ ++ EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE enTiming; ++ ++ if(Is_PTGEN_FHD(pTiming->u16Htotal,pTiming->u16Vtotal,pTiming->u16Vfrequency)) ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_1920_1080_30; ++ } ++ else if(Is_PTGEN_HD(pTiming->u16Htotal,pTiming->u16Vtotal,pTiming->u16Vfrequency)) ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_1024_768_60; ++ } ++ else if(Is_PTGEN_SD(pTiming->u16Htotal,pTiming->u16Vtotal,pTiming->u16Vfrequency)) ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_640_480_60; ++ } ++ else ++ { ++ enTiming = E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED; ++ } ++ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "[HVSP]%s(%d) Timing:%s(%d)", __FUNCTION__, __LINE__, PARSING_PAT_TGEN_TIMING(enTiming), enTiming); ++ return enTiming; ++} ++ ++//--------------------------------------------------------------------------------------------------------- ++// IOCTL function ++//--------------------------------------------------------------------------------------------------------- ++MS_BOOL _MDrv_HVSP_IsInputSrcPatternGen(EN_HVSP_IP_MUX_TYPE enIPMux, ST_MDRV_HVSP_INPUT_CONFIG *pCfg) ++{ ++ if(enIPMux == E_HVSP_IP_MUX_PAT_TGEN) ++ { ++ EN_MDRV_HVSP_PAT_TGEN_TIMING_TYPE enPatTgenTiming; ++ ST_DRV_HVSP_PAT_TGEN_CONFIG stPatTgenCfg; ++ ++ enPatTgenTiming = _MDrv_HVSP_GetPatTGenTiming(&pCfg->stTimingCfg); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:%d type:%d\n", __FUNCTION__,E_MDRV_HVSP_ID_1,enPatTgenTiming); ++ MsOS_Memcpy(&stPatTgenCfg, &gstPatTgenCfg[enPatTgenTiming],sizeof(ST_DRV_HVSP_PAT_TGEN_CONFIG)); ++ if(enPatTgenTiming == E_MDRV_HVSP_PAT_TGEN_TIMING_UNDEFINED) ++ { ++ stPatTgenCfg.u16HActive = pCfg->stCaptureWin.u16Width; ++ stPatTgenCfg.u16VActive = pCfg->stCaptureWin.u16Height; ++ stPatTgenCfg.u16Htt = stPatTgenCfg.u16HActive + ++ stPatTgenCfg.u16HBackPorch + ++ stPatTgenCfg.u16HFrontPorch + ++ stPatTgenCfg.u16HSyncWidth; ++ ++ stPatTgenCfg.u16Vtt = stPatTgenCfg.u16VActive + ++ stPatTgenCfg.u16VBackPorch + ++ stPatTgenCfg.u16VFrontPorch + ++ stPatTgenCfg.u16VSyncWidth; ++ ++ } ++ return (unsigned char)Drv_HVSP_SetPatTgen(TRUE, &stPatTgenCfg); ++ } ++ else ++ { ++ return 0; ++ } ++} ++void _MDrv_HVSP_FillPriMaskConfig(ST_MDRV_HVSP_PRIMASK_CONFIG *stCfg,ST_HVSP_PRIMASK_CONFIG *stPriMaskCfg) ++{ ++ stPriMaskCfg->bMask = stCfg->bMask; ++ stPriMaskCfg->u16Height = stCfg->stMaskWin.u16Height; ++ stPriMaskCfg->u16Width = stCfg->stMaskWin.u16Width; ++ stPriMaskCfg->u16X = stCfg->stMaskWin.u16X; ++ stPriMaskCfg->u16Y = stCfg->stMaskWin.u16Y; ++} ++unsigned short _MDrv_HVSP_GetScaleParameter(unsigned short u16Src, unsigned short u16Dsp, unsigned short u16Val) ++{ ++ //((unsigned short)((unsigned long)(value * RATIO_CONFIG * numerator) / (denominator * RATIO_CONFIG))) ++ unsigned long u32input; ++ unsigned short u16output; ++ u32input = u16Src *u16Val; ++ u16output = (unsigned short)(u32input/u16Dsp); ++ if((u32input%u16Dsp)) ++ { ++ u16output ++; ++ } ++ return u16output; ++} ++void _MDrv_HVSP_TransPercentToPriCfg ++ (ST_MDRV_HVSP_PRIMASK_CONFIG *stCfg ,ST_MDRV_HVSP_SCALING_CONFIG *sthvspCfg,ST_MDRV_HVSP_PRIMASK_CONFIG *stPerCfg) ++{ ++ //gstHvspPriMaskCfg[gu8PriMaskInst][idx] ++ //stPerCfg ++ //ST_MDRV_HVSP_PRIMASK_CONFIG stCfg; ++ stCfg->stMaskWin.u16X = (stPerCfg->stMaskWin.u16X * sthvspCfg->u16Dsp_Width) % PriMaskPercentBase; ++ if(stCfg->stMaskWin.u16X > 0) ++ { ++ stCfg->stMaskWin.u16X = (stPerCfg->stMaskWin.u16X * sthvspCfg->u16Dsp_Width) / PriMaskPercentBase; ++ stCfg->stMaskWin.u16X++; ++ } ++ else ++ { ++ stCfg->stMaskWin.u16X = (stPerCfg->stMaskWin.u16X * sthvspCfg->u16Dsp_Width) / PriMaskPercentBase; ++ } ++ stCfg->stMaskWin.u16Y = (stPerCfg->stMaskWin.u16Y * sthvspCfg->u16Dsp_Height) % PriMaskPercentBase; ++ if(stCfg->stMaskWin.u16Y > 0) ++ { ++ stCfg->stMaskWin.u16Y = (stPerCfg->stMaskWin.u16Y * sthvspCfg->u16Dsp_Height) / PriMaskPercentBase; ++ stCfg->stMaskWin.u16Y++; ++ } ++ else ++ { ++ stCfg->stMaskWin.u16Y = (stPerCfg->stMaskWin.u16Y * sthvspCfg->u16Dsp_Height) / PriMaskPercentBase; ++ } ++ stCfg->stMaskWin.u16Width = (stPerCfg->stMaskWin.u16Width * sthvspCfg->u16Dsp_Width) % PriMaskPercentBase; ++ if(stCfg->stMaskWin.u16Width > 0) ++ { ++ stCfg->stMaskWin.u16Width= (stPerCfg->stMaskWin.u16Width * sthvspCfg->u16Dsp_Width) / PriMaskPercentBase; ++ stCfg->stMaskWin.u16Width++; ++ } ++ else ++ { ++ stCfg->stMaskWin.u16Width= (stPerCfg->stMaskWin.u16Width * sthvspCfg->u16Dsp_Width) / PriMaskPercentBase; ++ } ++ stCfg->stMaskWin.u16Height = (stPerCfg->stMaskWin.u16Height * sthvspCfg->u16Dsp_Height) % PriMaskPercentBase; ++ if(stCfg->stMaskWin.u16Height > 0) ++ { ++ stCfg->stMaskWin.u16Height= (stPerCfg->stMaskWin.u16Height * sthvspCfg->u16Dsp_Height) / PriMaskPercentBase; ++ stCfg->stMaskWin.u16Height++; ++ } ++ else ++ { ++ stCfg->stMaskWin.u16Height= (stPerCfg->stMaskWin.u16Height * sthvspCfg->u16Dsp_Height) / PriMaskPercentBase; ++ } ++ stCfg->bMask = stPerCfg->bMask; ++ stCfg->u8idx = stPerCfg->u8idx; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:MASK OnOff:%hhd ,Position:(%hd,%hd),w=%hd h=%hd \n", ++ __FUNCTION__,stCfg->bMask,stCfg->stMaskWin.u16X,stCfg->stMaskWin.u16Y,stCfg->stMaskWin.u16Width, ++ stCfg->stMaskWin.u16Height); ++} ++void _MDrv_HVSP_TransPriCfgToPercent ++ (ST_MDRV_HVSP_PRIMASK_CONFIG *stCfg ,ST_MDRV_HVSP_SCALING_CONFIG *sthvspCfg,ST_MDRV_HVSP_PRIMASK_CONFIG *stPerCfg) ++{ ++ stPerCfg->stMaskWin.u16X = (stCfg->stMaskWin.u16X * PriMaskPercentBase) / sthvspCfg->u16Dsp_Width; ++ stPerCfg->stMaskWin.u16Y = (stCfg->stMaskWin.u16Y * PriMaskPercentBase) / sthvspCfg->u16Dsp_Height; ++ stPerCfg->stMaskWin.u16Width = (stCfg->stMaskWin.u16Width * PriMaskPercentBase) / sthvspCfg->u16Dsp_Width; ++ stPerCfg->stMaskWin.u16Height = (stCfg->stMaskWin.u16Height * PriMaskPercentBase) / sthvspCfg->u16Dsp_Height; ++ stPerCfg->bMask = stCfg->bMask; ++ stPerCfg->u8idx = stCfg->u8idx; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:MASK OnOff:%hhd ,Position:(%hd,%hd),w=%hd h=%hd (/10000)\n", ++ __FUNCTION__,stPerCfg->bMask,stPerCfg->stMaskWin.u16X,stPerCfg->stMaskWin.u16Y, ++ stPerCfg->stMaskWin.u16Height,stPerCfg->stMaskWin.u16Width); ++} ++ ++void _MDrv_HVSP_GetPriMaskConfig ++ (ST_MDRV_HVSP_PRIMASK_CONFIG *stCfg, ST_MDRV_HVSP_SCALING_CONFIG *sthvspCfg,ST_HVSP_PRIMASK_CONFIG *stPriMaskCfg) ++{ ++ if(IS_HVSPNotOpen(sthvspCfg->u16Src_Width,sthvspCfg->u16Dsp_Width)) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:, Still Not Setting HVSP ,MASK OnOff:%hhd ,Area =%ld ,Position:(%hd,%hd)\n", ++ __FUNCTION__,stCfg->bMask, ++ (unsigned long)((unsigned long)stCfg->stMaskWin.u16Height*(unsigned long)stCfg->stMaskWin.u16Width), ++ stCfg->stMaskWin.u16X,stCfg->stMaskWin.u16Y); ++ } ++ else ++ { ++ if(IS_NotScalingAfterCrop(sthvspCfg->stCropWin.bEn, ++ sthvspCfg->u16Dsp_Height,sthvspCfg->stCropWin.u16Height, ++ sthvspCfg->u16Dsp_Width,sthvspCfg->stCropWin.u16Width)) ++ { ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:, NotScalingAfterCrop, Not need to handler,MASK OnOff:%hhd ,Area =%ld ,Position:(%hd,%hd)\n", ++ __FUNCTION__,stCfg->bMask, ++ (unsigned long)((unsigned long)stCfg->stMaskWin.u16Height*(unsigned long)stCfg->stMaskWin.u16Width), ++ stCfg->stMaskWin.u16X,stCfg->stMaskWin.u16Y); ++ } ++ else ++ { ++ if(sthvspCfg->stCropWin.bEn) ++ { ++ stCfg->stMaskWin.u16X = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->stCropWin.u16Width,sthvspCfg->u16Dsp_Width,stCfg->stMaskWin.u16X)); ++ stCfg->stMaskWin.u16Y = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->stCropWin.u16Height,sthvspCfg->u16Dsp_Height,stCfg->stMaskWin.u16Y)); ++ stCfg->stMaskWin.u16Height = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->stCropWin.u16Height,sthvspCfg->u16Dsp_Height,stCfg->stMaskWin.u16Height)); ++ stCfg->stMaskWin.u16Width = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->stCropWin.u16Width,sthvspCfg->u16Dsp_Width,stCfg->stMaskWin.u16Width)); ++ } ++ else ++ { ++ stCfg->stMaskWin.u16X = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->u16Src_Width,sthvspCfg->u16Dsp_Width,stCfg->stMaskWin.u16X)); ++ stCfg->stMaskWin.u16Y = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->u16Src_Height,sthvspCfg->u16Dsp_Height,stCfg->stMaskWin.u16Y)); ++ stCfg->stMaskWin.u16Height = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->u16Src_Height,sthvspCfg->u16Dsp_Height,stCfg->stMaskWin.u16Height)); ++ stCfg->stMaskWin.u16Width = (_MDrv_HVSP_GetScaleParameter ++ (sthvspCfg->u16Src_Width,sthvspCfg->u16Dsp_Width,stCfg->stMaskWin.u16Width)); ++ } ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s:, Mask move,MASK OnOff:%hhd ,H =%ld,W=%ld ,Position:(%hd,%hd)\n", ++ __FUNCTION__,stCfg->bMask, ++ (unsigned long)stCfg->stMaskWin.u16Height,(unsigned long)stCfg->stMaskWin.u16Width, ++ stCfg->stMaskWin.u16X,stCfg->stMaskWin.u16Y); ++ } ++ } ++ _MDrv_HVSP_FillPriMaskConfig(stCfg,stPriMaskCfg); ++} ++unsigned char _MDrv_HVSP_FindUnusePriMask(void) ++{ ++ unsigned char u8Num; ++ unsigned char u8lastTimeNum = 0; ++ for(u8Num=0;u8Numu8idx],stPriMaskCfg,sizeof(ST_HVSP_PRIMASK_CONFIG)); ++ MDRV_HVSP_MUTEX_UNLOCK(); ++} ++void MDrv_HVSP_SetPatTgenStatus(unsigned char bEn) ++{ ++ Drv_HVSP_SetPatTgen(bEn, NULL); ++} ++unsigned char MDrv_HVSP_SetInputConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_INPUT_CONFIG *pCfg) ++{ ++ unsigned char Ret = TRUE; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s:%d\n", __FUNCTION__,enHVSP_ID); ++ ++ //SCL_ERR("clk1:%d, clk2:%d\n",(int)pCfg->stclk->idclk,(int)pCfg->stclk->fclk1); ++ ++ if(Is_Wrong_Type(enHVSP_ID,pCfg->enSrcType)) ++ { ++ SCL_ERR( "[HVSP] Wrong Input Type: %d, %d\n", enHVSP_ID, pCfg->enSrcType); ++ return FALSE; ++ } ++ if(enHVSP_ID == E_MDRV_HVSP_ID_1) ++ { ++ EN_HVSP_IP_MUX_TYPE enIPMux; ++ enIPMux = pCfg->enSrcType == E_MDRV_HVSP_SRC_ISP ? E_HVSP_IP_MUX_ISP : ++ pCfg->enSrcType == E_MDRV_HVSP_SRC_BT656 ? E_HVSP_IP_MUX_BT656 : ++ pCfg->enSrcType == E_MDRV_HVSP_SRC_HVSP ? E_HVSP_IP_MUX_HVSP : ++ pCfg->enSrcType == E_MDRV_HVSP_SRC_PAT_TGEN ? E_HVSP_IP_MUX_PAT_TGEN : ++ E_HVSP_IP_MUX_MAX; ++ Ret &= (unsigned char)Drv_HVSP_SetInputMux(enIPMux,(ST_HVSP_CLK_CONFIG *)pCfg->stclk); ++ Drv_HVSP_SetInputSrcSize(pCfg->stCaptureWin.u16Height,pCfg->stCaptureWin.u16Width); ++ //Drv_HVSP_SetCropWindowSize(); ++ if(_MDrv_HVSP_IsInputSrcPatternGen(enIPMux, pCfg)) ++ { ++ Ret &= TRUE; ++ } ++ else ++ { ++ Ret &= (unsigned char)Drv_HVSP_SetPatTgen(FALSE, NULL); ++ } ++ ++ } ++ return Ret; ++} ++ ++unsigned char MDrv_HVSP_SetPostCropConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_POSTCROP_CONFIG *pCfg) ++{ ++ EN_HVSP_ID_TYPE enID; ++ ST_HVSP_SCALING_CONFIG stScalingCfg; ++ unsigned char ret; ++ MsOS_Memset(&stScalingCfg,0,sizeof(ST_HVSP_SCALING_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s\n", __FUNCTION__); ++ ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ MDRV_HVSP_MUTEX_LOCK(); ++ MsOS_Memcpy(&gstHvspPostCropCfg, pCfg, sizeof(ST_MDRV_HVSP_POSTCROP_CONFIG)); ++ MDRV_HVSP_MUTEX_UNLOCK(); ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_1] = 0; ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_2] = pCfg->bCropEn; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_2] = pCfg->u16X; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_2] = pCfg->u16Y; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_2] = pCfg->u16Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_2] = pCfg->u16Height; ++ ++ stScalingCfg.u16Src_Width = gstHvspScalingCfg.u16Src_Width; ++ stScalingCfg.u16Src_Height = gstHvspScalingCfg.u16Src_Height; ++ stScalingCfg.u16Dsp_Width = gstHvspScalingCfg.u16Dsp_Width; ++ stScalingCfg.u16Dsp_Height = gstHvspScalingCfg.u16Dsp_Height; ++ ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_NONE; //ToDo ++ ++ ret = Drv_HVSP_SetScaling(enID, &stScalingCfg,(ST_HVSP_CLK_CONFIG *)pCfg->stclk); ++ return ret; ++ ++ ++} ++unsigned char _MDrv_HVSP_bChangePri(ST_MDRV_HVSP_SCALING_CONFIG *pCfg ) ++{ ++ unsigned char bChangePri; ++ if( pCfg->stCropWin.bEn == gstHvspScalingCfg.stCropWin.bEn) ++ { ++ bChangePri = 0; ++ } ++ else ++ { ++ return 1; ++ } ++ if(pCfg->stCropWin.u16X == gstHvspScalingCfg.stCropWin.u16X) ++ { ++ bChangePri = 0; ++ } ++ else ++ { ++ return 1; ++ } ++ if(pCfg->stCropWin.u16Y == gstHvspScalingCfg.stCropWin.u16Y) ++ { ++ bChangePri = 0; ++ } ++ else ++ { ++ return 1; ++ } ++ if(pCfg->stCropWin.u16Width == gstHvspScalingCfg.stCropWin.u16Width) ++ { ++ bChangePri = 0; ++ } ++ else ++ { ++ return 1; ++ } ++ if(pCfg->stCropWin.u16Height == gstHvspScalingCfg.stCropWin.u16Height) ++ { ++ bChangePri = 0; ++ } ++ else ++ { ++ return 1; ++ } ++ ++ return bChangePri; ++} ++void _MDrv_HVSP_ChangebyZoomSizeLimitation ++ (ST_HVSP_SCALING_CONFIG *stCfg ,ST_MDRV_HVSP_SCALING_CONFIG *stRet) ++{ ++ unsigned char u16cropType; ++ if( SetPostCrop) ++ { ++ u16cropType = 1; ++ } ++ else ++ { ++ u16cropType = 0; ++ } ++ stRet->stCropWin.bEn = stCfg->bCropEn[u16cropType]; ++ stRet->stCropWin.u16Height = stCfg->u16Crop_Height[u16cropType]; ++ stRet->stCropWin.u16Width = stCfg->u16Crop_Width[u16cropType] ; ++ stRet->stCropWin.u16X = stCfg->u16Crop_X[u16cropType]; ++ stRet->stCropWin.u16Y = stCfg->u16Crop_Y[u16cropType]; ++ stRet->u16Dsp_Height = gstHvspScalingCfg.u16Dsp_Height; ++ stRet->u16Dsp_Width = gstHvspScalingCfg.u16Dsp_Width; ++ stRet->u16Src_Height = gstHvspScalingCfg.u16Src_Height; ++ stRet->u16Src_Width = gstHvspScalingCfg.u16Src_Width; ++} ++unsigned char MDrv_HVSP_SetScalingConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SCALING_CONFIG *pCfg ) ++{ ++ EN_HVSP_ID_TYPE enID; ++ ST_HVSP_SCALING_CONFIG stScalingCfg; ++ unsigned char ret = 0; ++ unsigned char idx = 0; ++ unsigned char bChangePri = 0; ++ ST_HVSP_PRIMASK_CONFIG stPriMaskCfg; ++ ST_MDRV_HVSP_PRIMASK_CONFIG stPriMaskStore; ++ ST_MDRV_HVSP_SCALING_CONFIG stChange; ++ MsOS_Memset(&stScalingCfg,0,sizeof(ST_HVSP_SCALING_CONFIG)); ++ MsOS_Memset(&stChange,0,sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ MsOS_Memset(&stPriMaskCfg,0,sizeof(ST_MDRV_HVSP_PRIMASK_CONFIG)); ++ MsOS_Memset(&stPriMaskStore,0,sizeof(ST_HVSP_PRIMASK_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "%s:%d\n", __FUNCTION__,enHVSP_ID); ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ if(enID == E_HVSP_ID_1) ++ { ++ bChangePri = _MDrv_HVSP_bChangePri(pCfg); ++ MDRV_HVSP_MUTEX_LOCK(); ++ MsOS_Memcpy(&gstHvspScalingCfg, pCfg, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ MDRV_HVSP_MUTEX_UNLOCK(); ++ } ++ ++ if( SetPostCrop || (Drv_HVSP_GetInputSrcMux()==E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_1] = 0; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_1] = 0; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_1] = 0; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_1] = pCfg->u16Src_Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_1] = pCfg->u16Src_Height; ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_2] = pCfg->stCropWin.bEn; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16X; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Y; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Height; ++ } ++ else ++ { ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_1] = pCfg->stCropWin.bEn; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_1] = pCfg->stCropWin.u16X; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_1] = pCfg->stCropWin.u16Y; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_1] = pCfg->stCropWin.u16Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_1] = pCfg->stCropWin.u16Height; ++ stScalingCfg.bCropEn[DRV_HVSP_CROP_2] = 0; ++ stScalingCfg.u16Crop_X[DRV_HVSP_CROP_2] = 0; ++ stScalingCfg.u16Crop_Y[DRV_HVSP_CROP_2] = 0; ++ stScalingCfg.u16Crop_Width[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Width; ++ stScalingCfg.u16Crop_Height[DRV_HVSP_CROP_2] = pCfg->stCropWin.u16Height; ++ } ++ stScalingCfg.u16Src_Width = pCfg->u16Src_Width; ++ stScalingCfg.u16Src_Height = pCfg->u16Src_Height; ++ stScalingCfg.u16Dsp_Width = pCfg->u16Dsp_Width; ++ stScalingCfg.u16Dsp_Height = pCfg->u16Dsp_Height; ++ if(enHVSP_ID==E_MDRV_HVSP_ID_1 || enHVSP_ID==E_MDRV_HVSP_ID_2) ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_CMDQ_LDC_SYNC; //ToDo ++ } ++ else if(enHVSP_ID==E_MDRV_HVSP_ID_3) ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_NONE; //ToDo ++ } ++ else ++ { ++ stScalingCfg.stCmdTrigCfg.enType = E_HVSP_CMD_TRIG_POLL_LDC_SYNC; //ToDo ++ } ++ stScalingCfg.stCmdTrigCfg.u8Fmcnt = 0; ++ ret = Drv_HVSP_SetScaling(enID, &stScalingCfg,(ST_HVSP_CLK_CONFIG *)pCfg->stclk); ++ ++ if(enID == E_HVSP_ID_1) ++ { ++ if(!ret) ++ { ++ _MDrv_HVSP_ChangebyZoomSizeLimitation(&stScalingCfg,&stChange); ++ } ++ else ++ { ++ MsOS_Memcpy(&stChange, &gstHvspScalingCfg, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ } ++ if(gu8PriMaskNum[gu8PriMaskInst] && bChangePri) ++ { ++ //disable trigger ++ Drv_HVSP_SetPriMaskTrigger(EN_HVSP_PRIMASK_DISABLE); ++ for(idx=0;idxu32Size, GFP_KERNEL); ++ ++ if(pBuf == NULL) ++ { ++ SCL_ERR( "[HVSP1] allocate buffer fail\n"); ++ return 0; ++ } ++ ++ ++ if(MsOS_copy_from_user(pBuf, (__user ST_MDRV_HVSP_MISC_CONFIG *)pCfg->u32Addr, pCfg->u32Size)) ++ { ++ SCL_ERR( "[HVSP1] copy msic buffer error\n"); ++ MsOS_MemFree(pBuf); ++ return 0; ++ } ++ ++ switch(pCfg->u8Cmd) ++ { ++ case E_MDRV_HVSP_MISC_CMD_SET_REG: ++ _MDrv_HVSP_SetRegisterForce(pCfg->u32Size, pBuf); ++ break; ++ ++ default: ++ break; ++ } ++ ++ MsOS_MemFree(pBuf); ++ ++ return 1; ++} ++ ++unsigned char MDrv_HVSP_SetMiscConfigForKernel(ST_MDRV_HVSP_MISC_CONFIG *pCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "%s\n", __FUNCTION__); ++ switch(pCfg->u8Cmd) ++ { ++ case E_MDRV_HVSP_MISC_CMD_SET_REG: ++ _MDrv_HVSP_SetRegisterForce(pCfg->u32Size, (MS_U8 *)pCfg->u32Addr); ++ break; ++ ++ default: ++ break; ++ } ++ return 1; ++} ++ ++unsigned char MDrv_HVSP_GetSCLInform(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_SCINFORM_CONFIG *pstCfg) ++{ ++ ST_DRV_HVSP_SCINFORM_CONFIG stInformCfg; ++ EN_HVSP_ID_TYPE enID; ++ unsigned char bRet = 1; ++ MsOS_Memset(&stInformCfg,0,sizeof(ST_DRV_HVSP_SCINFORM_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[HVSP1]%s\n", __FUNCTION__); ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ Drv_HVSP_GetSCLInform(enID, &stInformCfg); ++ MsOS_Memcpy(pstCfg, &stInformCfg, sizeof(ST_MDRV_HVSP_SCINFORM_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[HVSP1]u16Height:%hd u16Width:%hd\n",stInformCfg.u16Height, stInformCfg.u16Width); ++ return bRet; ++} ++ ++unsigned char MDrv_HVSP_SetOSDConfig(EN_MDRV_HVSP_ID_TYPE enHVSP_ID, ST_MDRV_HVSP_OSD_CONFIG* pstCfg) ++{ ++ unsigned char Ret = TRUE; ++ ST_DRV_HVSP_OSD_CONFIG stOSdCfg; ++ EN_HVSP_ID_TYPE enID; ++ MsOS_Memset(&stOSdCfg,0,sizeof(ST_DRV_HVSP_OSD_CONFIG)); ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ MsOS_Memcpy(pstCfg, &stOSdCfg, sizeof(ST_MDRV_HVSP_OSD_CONFIG)); ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(enID)), ++ "%s::ID:%d, OnOff:%hhd ,Bypass:%hhd\n", ++ __FUNCTION__,enID,stOSdCfg.stOsdOnOff.bOSDEn,stOSdCfg.stOsdOnOff.bOSDBypass); ++ return Ret; ++} ++unsigned char MDrv_HVSP_SetPriMaskConfig(ST_MDRV_HVSP_PRIMASK_CONFIG *stCfg) ++{ ++ unsigned char Ret = TRUE; ++ unsigned char u8idx = 0; ++ ST_HVSP_PRIMASK_CONFIG stPriMaskCfg; ++ ST_MDRV_HVSP_PRIMASK_CONFIG stPriMaskStore; ++ MsOS_Memset(&stPriMaskCfg,0,sizeof(ST_HVSP_PRIMASK_CONFIG)); ++ MsOS_Memset(&stPriMaskStore,0,sizeof(ST_MDRV_HVSP_PRIMASK_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s::ID:%d, OnOff:%hhd id:%hhd\n",__FUNCTION__,E_MDRV_HVSP_ID_1,stCfg->bMask,stCfg->u8idx); ++ //need to turn off mask ++ //1.turn off same idx ++ //2.turn on others idx ++ if(stCfg->u8idx == gstHvspPriMaskCfg[gu8PriMaskInst][stCfg->u8idx].u8idx && ++ gstHvspPriMaskCfg[gu8PriMaskInst][stCfg->u8idx].bMask) ++ { ++ Drv_HVSP_PriMaskBufferReset(); ++ //ReOpen to avoid disable repeat region. ++ for(u8idx = 0 ; u8idxu8idx) ++ { ++ continue; ++ } ++ else if(u8idx == gstHvspPriMaskCfg[gu8PriMaskInst][u8idx].u8idx ++ && gstHvspPriMaskCfg[gu8PriMaskInst][u8idx].bMask) ++ { ++ _MDrv_HVSP_TransPercentToPriCfg(&stPriMaskStore,&gstHvspScalingCfg,&gstHvspPriMaskCfg[gu8PriMaskInst][u8idx]); ++ _MDrv_HVSP_GetPriMaskConfig(&stPriMaskStore,&gstHvspScalingCfg,&stPriMaskCfg); ++ Drv_HVSP_SetPriMaskConfig(&stPriMaskCfg); ++ } ++ } ++ } ++ _MDrv_HVSP_TransPriCfgToPercent(stCfg,&gstHvspScalingCfg,&stPriMaskStore); ++ _MDrv_HVSP_SetPriMaskStorage(&stPriMaskStore); ++ _MDrv_HVSP_GetPriMaskConfig(stCfg,&gstHvspScalingCfg,&stPriMaskCfg); ++ if(stPriMaskCfg.bMask) ++ { ++ Drv_HVSP_SetPriMaskConfig(&stPriMaskCfg); ++ } ++ return Ret; ++} ++unsigned char MDrv_HVSP_SetPriMaskTrigger(unsigned char bEn) ++{ ++ unsigned char Ret = TRUE; ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(E_MDRV_HVSP_ID_1)), ++ "%s, OnOff:%hhd\n",__FUNCTION__,bEn); ++ Drv_HVSP_SetPriMaskTrigger(bEn ? EN_HVSP_PRIMASK_ENABLE : EN_HVSP_PRIMASK_DISABLE); ++ if(bEn == EN_HVSP_PRIMASK_DISABLE) ++ { ++ _MDrv_HVSP_ResetPriMaskStorage(); ++ } ++ return Ret; ++} ++ ++unsigned char Mdrv_HVSP_GetFrameBufferCountInformation(void) ++{ ++ return gu8IPMBufferNum; ++} ++ ++unsigned char MDrv_HVSP_SetFbManageConfig(EN_MDRV_HVSP_FBMG_SET_TYPE enSet) ++{ ++ unsigned char Ret = TRUE; ++ ST_DRV_HVSP_SET_FB_MANAGE_CONFIG stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(ST_DRV_HVSP_SET_FB_MANAGE_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "%s\n", __FUNCTION__); ++ stCfg.enSet = (EN_DRV_HVSP_FBMG_SET_TYPE)enSet; ++ if (stCfg.enSet & EN_DRV_HVSP_FBMG_SET_DNR_COMDE_ON) ++ { ++ SCL_ERR( "COMDE_ON\n"); ++ MDrv_VIP_SetMCNRConpressForDebug(1); ++ } ++ else if (stCfg.enSet & EN_DRV_HVSP_FBMG_SET_DNR_COMDE_OFF) ++ { ++ SCL_ERR( "COMDE_OFF\n"); ++ MDrv_VIP_SetMCNRConpressForDebug(0); ++ } ++ else if (stCfg.enSet & EN_DRV_HVSP_FBMG_SET_DNR_COMDE_265OFF) ++ { ++ SCL_ERR( "COMDE_265OFF\n"); ++ MDrv_VIP_SetMCNRConpressForDebug(0); ++ } ++ if(stCfg.enSet &EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_1) ++ { ++ gu8IPMBufferNum = 1; ++ Drv_HVSP_SetBufferNum(gu8IPMBufferNum); ++ } ++ else if (stCfg.enSet &EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_2) ++ { ++ gu8IPMBufferNum = 2; ++ Drv_HVSP_SetBufferNum(gu8IPMBufferNum); ++ } ++ Drv_HVSP_SetFbManageConfig(&stCfg); ++ return Ret; ++} ++void MDrv_HVSP_IDCLKRelease(ST_MDRV_HVSP_CLK_CONFIG* stclk) ++{ ++ SCL_DBG(SCL_DBG_LV_HVSP()&(Get_DBGMG_HVSP(3)), "%s\n", __FUNCTION__); ++ Drv_HVSP_IDCLKRelease((ST_HVSP_CLK_CONFIG *)stclk); ++} ++ ++ ++ ++unsigned char MDrv_HVSP_InputVSyncMonitor(void) ++{ ++ if(Drv_HVSP_CheckInputVSync()) ++ { ++ return 1; ++ } ++ else ++ { ++ return 0; ++ } ++} ++#if 1 ++void MDrv_HVSP_SetCLKForcemode(unsigned char bEn) ++{ ++ Drv_HVSP_SetCLKForcemode(bEn); ++} ++void MDrv_HVSP_SetCLKRate(void* adjclk,unsigned char u8Idx) ++{ ++ MSOS_ST_CLK* pstclock = NULL; ++ Drv_HVSP_SetCLKRate(u8Idx); ++ if (MsOS_clk_get_enable_count((MSOS_ST_CLK*)adjclk)==0) ++ { ++ } ++ else ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index((MSOS_ST_CLK*)adjclk, (u8Idx &0x0F)))) ++ { ++ MsOS_clk_set_parent((MSOS_ST_CLK*)adjclk, pstclock); ++ } ++ } ++} ++void MDrv_HVSP_SetCLKOnOff(void* adjclk,unsigned char bEn) ++{ ++ MSOS_ST_CLK* pstclock = NULL; ++ if (MsOS_clk_get_enable_count((MSOS_ST_CLK*)adjclk)==0 &&bEn) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index((MSOS_ST_CLK*)adjclk, 0))) ++ { ++ MsOS_clk_set_parent((MSOS_ST_CLK*)adjclk, pstclock); ++ MsOS_clk_prepare_enable((MSOS_ST_CLK*)adjclk); ++ } ++ } ++ else if(MsOS_clk_get_enable_count((MSOS_ST_CLK*)adjclk)!=0 && !bEn) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index((MSOS_ST_CLK*)adjclk, 0))) ++ { ++ MsOS_clk_set_parent((MSOS_ST_CLK*)adjclk, pstclock); ++ MsOS_clk_disable_unprepare((MSOS_ST_CLK*)adjclk); ++ } ++ } ++} ++ssize_t MDrv_HVSP_monitorHWShow(char *buf,int VsyncCount ,int MonitorErrCount) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "========================SCL monitor HW BUTTON======================\n"); ++ str += MsOS_scnprintf(str, end - str, "CROP Monitor :1\n"); ++ str += MsOS_scnprintf(str, end - str, "DMA1FRM Monitor :2\n"); ++ str += MsOS_scnprintf(str, end - str, "DMA1SNP Monitor :3\n"); ++ str += MsOS_scnprintf(str, end - str, "DMA2FRM Monitor :4\n"); ++ str += MsOS_scnprintf(str, end - str, "DMA3FRM Monitor :5\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL monitor HW ======================\n"); ++ str += MsOS_scnprintf(str, end - str, "vysnc count:%d",VsyncCount); ++ str += MsOS_scnprintf(str, end - str, "Monitor Err count:%d\n",MonitorErrCount); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_DbgmgFlagShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "========================SCL Debug Message BUTTON======================\n"); ++ str += MsOS_scnprintf(str, end - str, "CONFIG ECHO STATUS\n"); ++ str += MsOS_scnprintf(str, end - str, "MDRV_CONFIG (1) 0x%x\n",gbdbgmessage[EN_DBGMG_MDRV_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "IOCTL_CONFIG (2) 0x%x\n",gbdbgmessage[EN_DBGMG_IOCTL_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "HVSP_CONFIG (3) 0x%x\n",gbdbgmessage[EN_DBGMG_HVSP_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "SCLDMA_CONFIG (4) 0x%x\n",gbdbgmessage[EN_DBGMG_SCLDMA_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "PNL_CONFIG (5) 0x%x\n",gbdbgmessage[EN_DBGMG_PNL_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "VIP_CONFIG (6) 0x%x\n",gbdbgmessage[EN_DBGMG_VIP_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "DRVPQ_CONFIG (7) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVPQ_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "INST_ENTRY_CONFIG (8) 0x%x\n",gbdbgmessage[EN_DBGMG_INST_ENTRY_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "INST_LOCK_CONFIG (9) 0x%x\n",gbdbgmessage[EN_DBGMG_INST_LOCK_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "INST_FUNC_CONFIG (A) 0x%x\n",gbdbgmessage[EN_DBGMG_INST_FUNC_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "DRVHVSP_CONFIG (B) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVHVSP_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "DRVSCLDMA_CONFIG (C) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVSCLDMA_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "DRVSCLIRQ_CONFIG (D) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVSCLIRQ_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "DRVCMDQ_CONFIG (E) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVCMDQ_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "DRVVIP_CONFIG (F) 0x%x\n",gbdbgmessage[EN_DBGMG_DRVVIP_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "PRIORITY_CONFIG (G) 0x%x\n",gbdbgmessage[EN_DBGMG_PRIORITY_CONFIG]); ++ str += MsOS_scnprintf(str, end - str, "ALL Reset (0)\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL Debug Message BUTTON======================\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL Debug Message LEVEL======================\n"); ++ str += MsOS_scnprintf(str, end - str, "default is level 1\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------IOCTL LEVEL---------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : SC1\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : SC2\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : SC3\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : VIP\n"); ++ str += MsOS_scnprintf(str, end - str, "0x10 : SC1HLEVEL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x20 : SC2HLEVEL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x40 : LCD\n"); ++ str += MsOS_scnprintf(str, end - str, "0x80 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------HVSP LEVEL---------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : HVSP1\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : HVSP2\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : HVSP3\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------SCLDMA LEVEL-------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : SC1 FRM\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : SC1 SNP \n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : SC2 FRM\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : SC3 FRM\n"); ++ str += MsOS_scnprintf(str, end - str, "0x10 : SC1 FRM HL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x20 : SC1 SNP HL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x40 : SC2 FRM HL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x80 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------VIP LEVEL(IOlevel)-------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : NORMAL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : VIP LOG \n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : VIP SUSPEND\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "------------------------------MULTI LEVEL---------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : SC1\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : SC3\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : DISP\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------PQ LEVEL---------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : befor crop\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : color eng\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : VIP Y\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : VIP C\n"); ++ str += MsOS_scnprintf(str, end - str, "0x10 : AIP\n"); ++ str += MsOS_scnprintf(str, end - str, "0x20 : AIP post\n"); ++ str += MsOS_scnprintf(str, end - str, "0x40 : HVSP\n"); ++ str += MsOS_scnprintf(str, end - str, "0x80 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------SCLIRQ LEVEL(drvlevel)---------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : NORMAL\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : SC1RINGA \n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : SC1RINGN\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : SC1SINGLE\n"); ++ str += MsOS_scnprintf(str, end - str, "0x10 : SC2RINGA\n"); ++ str += MsOS_scnprintf(str, end - str, "0x20 : SC2RINGN \n"); ++ str += MsOS_scnprintf(str, end - str, "0x40 : SC3SINGLE\n"); ++ str += MsOS_scnprintf(str, end - str, "0x80 : ELSE\n"); ++ str += MsOS_scnprintf(str, end - str, "-------------------------------CMDQ LEVEL(drvlevel)-----------------\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 1 : LOW\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 2 : NORMAL \n"); ++ str += MsOS_scnprintf(str, end - str, "0x 4 : HIGH\n"); ++ str += MsOS_scnprintf(str, end - str, "0x 8 : ISR\n"); ++ str += MsOS_scnprintf(str, end - str, "0x10 : ISR check\n"); ++ str += MsOS_scnprintf(str, end - str, "0x10 : SRAM check\n"); ++ str += MsOS_scnprintf(str, end - str, "\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL Debug Message LEVEL======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_IntsShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ST_HVSP_SCINTS_TYPE stInts; ++ unsigned long u32val; ++ MsOS_Memset(&stInts,0,sizeof(ST_HVSP_SCINTS_TYPE)); ++ Drv_HVSP_GetSCLInts(&stInts); ++ str += MsOS_scnprintf(str, end - str, "========================SCL INTS======================\n"); ++ str += MsOS_scnprintf(str, end - str, "AFF Count: %lu\n",stInts.u32AffCount); ++ str += MsOS_scnprintf(str, end - str, "DMAERROR Count: %lu\n",stInts.u32ErrorCount); ++ str += MsOS_scnprintf(str, end - str, "ISPIn Count: %lu\n",stInts.u32ISPInCount); ++ str += MsOS_scnprintf(str, end - str, "ISPDone Count: %lu\n",stInts.u32ISPDoneCount); ++ str += MsOS_scnprintf(str, end - str, "DIFF Count: %lu\n",(stInts.u32ISPInCount-stInts.u32ISPDoneCount)); ++ str += MsOS_scnprintf(str, end - str, "ResetCount Count: %hhu\n",stInts.u8CountReset); ++ str += MsOS_scnprintf(str, end - str, "SC1FrmDone Count: %lu\n",stInts.u32SC1FrmDoneCount); ++ str += MsOS_scnprintf(str, end - str, "SC1SnpDone Count: %lu\n",stInts.u32SC1SnpDoneCount); ++ str += MsOS_scnprintf(str, end - str, "SC2FrmDone Count: %lu\n",stInts.u32SC2FrmDoneCount); ++ str += MsOS_scnprintf(str, end - str, "SC2Frm2Done Count: %lu\n",stInts.u32SC2Frm2DoneCount); ++ str += MsOS_scnprintf(str, end - str, "SC3Done Count: %lu\n",stInts.u32SC3DoneCount); ++ str += MsOS_scnprintf(str, end - str, "SCLMainDone Count: %lu\n",stInts.u32SCLMainDoneCount); ++ if(stInts.u32SC1FrmDoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32SC1FrmActiveTime/stInts.u32SC1FrmDoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32SC1FrmActiveTime; ++ } ++ str += MsOS_scnprintf(str, end - str, "SC1Frm ActiveTime: %lu (us)\n",u32val); ++ if(stInts.u32SC1SnpDoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32SC1SnpActiveTime/stInts.u32SC1SnpDoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32SC1SnpActiveTime; ++ } ++ str += MsOS_scnprintf(str, end - str, "SC1Snp ActiveTime: %lu (us)\n",u32val); ++ if(stInts.u32SC2FrmDoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32SC2FrmActiveTime/stInts.u32SC2FrmDoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32SC2FrmDoneCount; ++ } ++ str += MsOS_scnprintf(str, end - str, "SC2Frm ActiveTime: %lu (us)\n",u32val); ++ if(stInts.u32SC2Frm2DoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32SC2Frm2ActiveTime/stInts.u32SC2Frm2DoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32SC2Frm2DoneCount; ++ } ++ str += MsOS_scnprintf(str, end - str, "SC2Frm2 ActiveTime: %lu (us)\n",u32val); ++ if(stInts.u32SC3DoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32SC3ActiveTime/stInts.u32SC3DoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32SC3DoneCount; ++ } ++ str += MsOS_scnprintf(str, end - str, "SC3 ActiveTime: %lu (us)\n",u32val); ++ if(stInts.u32SCLMainDoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32SCLMainActiveTime/stInts.u32SCLMainDoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32SCLMainActiveTime; ++ } ++ str += MsOS_scnprintf(str, end - str, "SCLMain ActiveTime: %lu (us)\n",u32val); ++ if(stInts.u32ISPDoneCount) ++ { ++ u32val = (unsigned long)(stInts.u32ISPTime/stInts.u32ISPDoneCount); ++ } ++ else ++ { ++ u32val = stInts.u32ISPTime; ++ } ++ str += MsOS_scnprintf(str, end - str, "ISP ActiveTime: %lu (us)\n",u32val); ++ str += MsOS_scnprintf(str, end - str, "ISP BlankingTime: %lu (us)\n",stInts.u32ISPBlankingTime); ++ str += MsOS_scnprintf(str, end - str, "========================SCL INTS======================\n"); ++ return (str - buf); ++} ++void MDrv_HVSP_SCIQStore(const char *buf,EN_MDRV_HVSP_ID_TYPE enHVSP_ID) ++{ ++ const char *str = buf; ++ EN_HVSP_ID_TYPE enID; ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ if(NULL!=buf) ++ { ++ //if(!) ++ if((int)*str == 49) //input 1 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_H_Tbl0); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_H_Tbl1); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_H_Tbl2); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_H_Tbl3); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_H_BYPASS); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_H_BILINEAR); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_V_Tbl0); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 56) //input 8 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_V_Tbl1); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 57) //input 9 ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_V_Tbl2); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 65) //input A ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_V_Tbl3); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 66) //input B ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_V_BYPASS); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ else if((int)*str == 67) //input C ++ { ++ Drv_HVSP_SCLIQ(enID,EN_DRV_HVSP_IQ_V_BILINEAR); ++ SCL_ERR( "[SCLIQ]Set %d\n",(int)*str); ++ } ++ } ++} ++ssize_t MDrv_HVSP_SCIQShow(char *buf, EN_MDRV_HVSP_ID_TYPE enHVSP_ID) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvspformCfg; ++ MsOS_Memset(&sthvspformCfg,0,sizeof(ST_DRV_HVSP_HVSPINFORM_CONFIG)); ++ Drv_HVSP_GetHVSPAttribute((EN_HVSP_ID_TYPE)enHVSP_ID,&sthvspformCfg); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL IQ----------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "H en :%hhx\n",sthvspformCfg.bEn&0x1); ++ str += MsOS_scnprintf(str, end - str, "H function :%hhx\n",(sthvspformCfg.bEn&0xC0)>>6); ++ str += MsOS_scnprintf(str, end - str, "V en :%hhx\n",(sthvspformCfg.bEn&0x2)>>1); ++ str += MsOS_scnprintf(str, end - str, "V function :%hhx\n",(sthvspformCfg.bEn&0x30)>>4); ++ str += MsOS_scnprintf(str, end - str, "SC H :1~6\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 0 :1\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 1 :2\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 2 :3\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 3 :4\n"); ++ str += MsOS_scnprintf(str, end - str, "SC bypass :5\n"); ++ str += MsOS_scnprintf(str, end - str, "SC bilinear :6\n"); ++ str += MsOS_scnprintf(str, end - str, "SC V :7~C\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 0 :7\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 1 :8\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 2 :9\n"); ++ str += MsOS_scnprintf(str, end - str, "SC table 3 :A\n"); ++ str += MsOS_scnprintf(str, end - str, "SC bypass :B\n"); ++ str += MsOS_scnprintf(str, end - str, "SC bilinear :C\n"); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL IQ----------------------\n"); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_ProcShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvspformCfg; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvsp2formCfg; ++ ST_DRV_HVSP_HVSPINFORM_CONFIG sthvsp3formCfg; ++ ST_DRV_HVSP_SCINFORM_CONFIG stzoomformCfg; ++ ST_HVSP_IPM_CONFIG stIpmformCfg; ++ ST_DRV_HVSP_INPUTINFORM_CONFIG stInformCfg; ++ unsigned char bLDCorPrvCrop; ++ ST_DRV_HVSP_OSD_CONFIG stOsdCfg; ++ Drv_HVSP_GetCrop12Inform(&stInformCfg); ++ Drv_HVSP_GetSCLInform(E_HVSP_ID_1,&stzoomformCfg); ++ Drv_HVSP_GetHVSPAttribute(E_HVSP_ID_1,&sthvspformCfg); ++ Drv_HVSP_GetHVSPAttribute(E_HVSP_ID_2,&sthvsp2formCfg); ++ Drv_HVSP_GetHVSPAttribute(E_HVSP_ID_3,&sthvsp3formCfg); ++ Drv_HVSP_GetOSDAttribute(E_HVSP_ID_1,&stOsdCfg); ++ bLDCorPrvCrop = Drv_HVSP_GetFrameBufferAttribute(E_HVSP_ID_1,&stIpmformCfg); ++ str += MsOS_scnprintf(str, end - str, "========================SCL PROC FRAMEWORK======================\n"); ++ str += MsOS_scnprintf(str, end - str, "\n"); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL INPUT MUX----------------------\n"); ++ if(stInformCfg.enMux==0) ++ { ++ str += MsOS_scnprintf(str, end - str, "Input SRC :BT656\n"); ++ } ++ else if(stInformCfg.enMux==1) ++ { ++ str += MsOS_scnprintf(str, end - str, "Input SRC :ISP\n"); ++ } ++ else if(stInformCfg.enMux==3) ++ { ++ str += MsOS_scnprintf(str, end - str, "Input SRC :PTGEN\n"); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "Input SRC :OTHER\n"); ++ } ++ str += MsOS_scnprintf(str, end - str, "Input H :%hd\n",stInformCfg.u16inWidth); ++ str += MsOS_scnprintf(str, end - str, "Input V :%hd\n",stInformCfg.u16inHeight); ++ str += MsOS_scnprintf(str, end - str, "Receive H :%hd\n",stInformCfg.u16inWidthcount); ++ str += MsOS_scnprintf(str, end - str, "Receive V :%hd\n",stInformCfg.u16inHeightcount); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL FB-----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "FB H :%hd\n",stIpmformCfg.u16Fetch); ++ str += MsOS_scnprintf(str, end - str, "FB V :%hd\n",stIpmformCfg.u16Vsize); ++ str += MsOS_scnprintf(str, end - str, "FB Addr :%lx\n",stIpmformCfg.u32YCBaseAddr); ++ str += MsOS_scnprintf(str, end - str, "FB memsize :%ld\n",stIpmformCfg.u32MemSize); ++ str += MsOS_scnprintf(str, end - str, "FB Buffer :%hhd\n",gu8IPMBufferNum); ++ str += MsOS_scnprintf(str, end - str, "FB Write :%hhd\n",stIpmformCfg.bYCMWrite); ++ if(bLDCorPrvCrop &0x1) ++ { ++ str += MsOS_scnprintf(str, end - str, "READ PATH :LDC\n"); ++ } ++ else if(bLDCorPrvCrop &0x2) ++ { ++ str += MsOS_scnprintf(str, end - str, "READ PATH :PrvCrop\n"); ++ } ++ else if(stIpmformCfg.bYCMRead) ++ { ++ str += MsOS_scnprintf(str, end - str, "READ PATH :MCNR\n"); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "READ PATH :NONE\n"); ++ } ++ str += MsOS_scnprintf(str, end - str, "FRAME DELAY :%hhd\n",MsOS_GetSCLFrameDelay()); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL Crop----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "Crop :%hhd\n",stInformCfg.bEn); ++ str += MsOS_scnprintf(str, end - str, "CropX :%hd\n",stInformCfg.u16inCropX); ++ str += MsOS_scnprintf(str, end - str, "CropY :%hd\n",stInformCfg.u16inCropY); ++ str += MsOS_scnprintf(str, end - str, "CropOutW :%hd\n",stInformCfg.u16inCropWidth); ++ str += MsOS_scnprintf(str, end - str, "CropOutH :%hd\n",stInformCfg.u16inCropHeight); ++ str += MsOS_scnprintf(str, end - str, "SrcW :%hd\n",stInformCfg.u16inWidth); ++ str += MsOS_scnprintf(str, end - str, "SrcH :%hd\n",stInformCfg.u16inHeight); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL Zoom----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "Zoom :%hhd\n",stzoomformCfg.bEn); ++ str += MsOS_scnprintf(str, end - str, "ZoomX :%hd\n",stzoomformCfg.u16X); ++ str += MsOS_scnprintf(str, end - str, "ZoomY :%hd\n",stzoomformCfg.u16Y); ++ str += MsOS_scnprintf(str, end - str, "ZoomOutW :%hd\n",stzoomformCfg.u16crop2OutWidth); ++ str += MsOS_scnprintf(str, end - str, "ZoomOutH :%hd\n",stzoomformCfg.u16crop2OutHeight); ++ str += MsOS_scnprintf(str, end - str, "SrcW :%hd\n",stzoomformCfg.u16crop2inWidth); ++ str += MsOS_scnprintf(str, end - str, "SrcH :%hd\n",stzoomformCfg.u16crop2inHeight); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL OSD----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "ONOFF :%hhd\n",stOsdCfg.stOsdOnOff.bOSDEn); ++ if(stOsdCfg.enOSD_loc) ++ { ++ str += MsOS_scnprintf(str, end - str, "Locate: Before\n"); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "Locate: After\n"); ++ } ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL HVSP1----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "InputH :%hd\n",sthvspformCfg.u16inWidth); ++ str += MsOS_scnprintf(str, end - str, "InputV :%hd\n",sthvspformCfg.u16inHeight); ++ str += MsOS_scnprintf(str, end - str, "OutputH :%hd\n",sthvspformCfg.u16Width); ++ str += MsOS_scnprintf(str, end - str, "OutputV :%hd\n",sthvspformCfg.u16Height); ++ str += MsOS_scnprintf(str, end - str, "H en :%hhx\n",sthvspformCfg.bEn&0x1); ++ str += MsOS_scnprintf(str, end - str, "H function :%hhx\n",(sthvspformCfg.bEn&0xC0)>>6); ++ str += MsOS_scnprintf(str, end - str, "V en :%hhx\n",(sthvspformCfg.bEn&0x2)>>1); ++ str += MsOS_scnprintf(str, end - str, "V function :%hhx\n",(sthvspformCfg.bEn&0x30)>>4); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL HVSP2----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "InputH :%hd\n",sthvsp2formCfg.u16inWidth); ++ str += MsOS_scnprintf(str, end - str, "InputV :%hd\n",sthvsp2formCfg.u16inHeight); ++ str += MsOS_scnprintf(str, end - str, "OutputH :%hd\n",sthvsp2formCfg.u16Width); ++ str += MsOS_scnprintf(str, end - str, "OutputV :%hd\n",sthvsp2formCfg.u16Height); ++ str += MsOS_scnprintf(str, end - str, "H en :%hhx\n",sthvsp2formCfg.bEn&0x1); ++ str += MsOS_scnprintf(str, end - str, "H function :%hhx\n",(sthvsp2formCfg.bEn&0xC0)>>6); ++ str += MsOS_scnprintf(str, end - str, "V en :%hhx\n",(sthvsp2formCfg.bEn&0x2)>>1); ++ str += MsOS_scnprintf(str, end - str, "V function :%hhx\n",(sthvsp2formCfg.bEn&0x30)>>4); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL HVSP3----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "InputH :%hd\n",sthvsp3formCfg.u16inWidth); ++ str += MsOS_scnprintf(str, end - str, "InputV :%hd\n",sthvsp3formCfg.u16inHeight); ++ str += MsOS_scnprintf(str, end - str, "OutputH :%hd\n",sthvsp3formCfg.u16Width); ++ str += MsOS_scnprintf(str, end - str, "OutputV :%hd\n",sthvsp3formCfg.u16Height); ++ str += MsOS_scnprintf(str, end - str, "H en :%hhx\n",sthvsp3formCfg.bEn&0x1); ++ str += MsOS_scnprintf(str, end - str, "H function :%hhx\n",(sthvsp3formCfg.bEn&0xC0)>>6); ++ str += MsOS_scnprintf(str, end - str, "V en :%hhx\n",(sthvsp3formCfg.bEn&0x2)>>1); ++ str += MsOS_scnprintf(str, end - str, "V function :%hhx\n",(sthvsp3formCfg.bEn&0x30)>>4); ++ str += MsOS_scnprintf(str, end - str, "\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL PROC FRAMEWORK======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_ClkFrameworkShow(char *buf,ST_MDRV_HVSP_CLK_CONFIG* stclk) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "========================SCL CLK FRAMEWORK======================\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 1 > clk :open force mode\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 0 > clk :close force mode\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 2 > clk :fclk1 172\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 3 > clk :fclk1 86\n"); ++ str += MsOS_scnprintf(str, end - str, "echo E > clk :fclk1 216\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 4 > clk :fclk1 open\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 5 > clk :fclk1 close\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 6 > clk :fclk2 172\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 7 > clk :fclk2 86\n"); ++ str += MsOS_scnprintf(str, end - str, "echo F > clk :fclk2 216\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 8 > clk :fclk2 open\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 9 > clk :fclk2 close\n"); ++ str += MsOS_scnprintf(str, end - str, "echo : > clk :idclk ISP\n"); ++ str += MsOS_scnprintf(str, end - str, "echo D > clk :idclk BT656\n"); ++ str += MsOS_scnprintf(str, end - str, "echo B > clk :idclk open\n"); ++ str += MsOS_scnprintf(str, end - str, "echo = > clk :idclk close\n"); ++ str += MsOS_scnprintf(str, end - str, "echo C > clk :odclk MAX\n"); ++ str += MsOS_scnprintf(str, end - str, "echo ? > clk :odclk LPLL\n"); ++ str += MsOS_scnprintf(str, end - str, "echo @ > clk :odclk open\n"); ++ str += MsOS_scnprintf(str, end - str, "echo A > clk :odclk close\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL CLK STATUS======================\n"); ++ str += MsOS_scnprintf(str, end - str, "force mode :%hhd\n",Drv_HVSP_GetCLKForcemode()); ++ if(MsOS_clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk1)) ++ { ++ str += MsOS_scnprintf(str, end - str, "fclk1 open :%d ,%ld\n", ++ MsOS_clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk1),MsOS_clk_get_rate((MSOS_ST_CLK*)stclk->fclk1)); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "fclk1 close\n"); ++ } ++ if(MsOS_clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk2)) ++ { ++ str += MsOS_scnprintf(str, end - str, "fclk2 open :%d,%ld\n", ++ MsOS_clk_get_enable_count((MSOS_ST_CLK*)stclk->fclk2),MsOS_clk_get_rate((MSOS_ST_CLK*)stclk->fclk2)); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "fclk2 close\n"); ++ } ++ if(MsOS_clk_get_enable_count((MSOS_ST_CLK*)stclk->idclk)) ++ { ++ if(MsOS_clk_get_rate((MSOS_ST_CLK*)stclk->idclk) > 10) ++ { ++ str += MsOS_scnprintf(str, end - str, "idclk open :ISP\n"); ++ } ++ else if(MsOS_clk_get_rate((MSOS_ST_CLK*)stclk->idclk) == 1) ++ { ++ str += MsOS_scnprintf(str, end - str, "idclk open :BT656\n"); ++ } ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "idclk close\n"); ++ } ++ if(MsOS_clk_get_enable_count((MSOS_ST_CLK*)stclk->odclk)) ++ { ++ if(MsOS_clk_get_rate((MSOS_ST_CLK*)stclk->odclk) == 432000000) ++ { ++ str += MsOS_scnprintf(str, end - str, "odclk open LPLL:%ld\n",((MS_U32)Drv_PNL_GetLPLLDclk()/10000)*10000); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "odclk open :%ld\n",MsOS_clk_get_rate(stclk->odclk)); ++ } ++ } ++ else if(Drv_PNL_GetPnlOpen()) ++ { ++ str += MsOS_scnprintf(str, end - str, "odclk manual open LPLL:%ld\n",((MS_U32)Drv_PNL_GetLPLLDclk()/10000)*10000); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "odclk close\n"); ++ } ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_FBMGShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL FBMG----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "LDCPATH_ON :1\n"); ++ str += MsOS_scnprintf(str, end - str, "LDCPATH_OFF :2\n"); ++ str += MsOS_scnprintf(str, end - str, "DNRRead_ON :3\n"); ++ str += MsOS_scnprintf(str, end - str, "DNRRead_OFF :4\n"); ++ str += MsOS_scnprintf(str, end - str, "DNRWrite_ON :5\n"); ++ str += MsOS_scnprintf(str, end - str, "DNRWrite_OFF :6\n"); ++ str += MsOS_scnprintf(str, end - str, "DNRBuf1 :7\n"); ++ str += MsOS_scnprintf(str, end - str, "DNRBuf2 :8\n"); ++ str += MsOS_scnprintf(str, end - str, "UNLOCK :9\n"); ++ str += MsOS_scnprintf(str, end - str, "PrvCrop_ON :A\n"); ++ str += MsOS_scnprintf(str, end - str, "PrvCrop_OFF :B\n"); ++ str += MsOS_scnprintf(str, end - str, "CIIR_ON :C\n"); ++ str += MsOS_scnprintf(str, end - str, "CIIR_OFF :D\n"); ++ str += MsOS_scnprintf(str, end - str, "LOCK :E\n"); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL FBMG----------------------------\n"); ++ return (str - buf); ++} ++ssize_t MDrv_HVSP_OdShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned char u8idx = 0; ++ unsigned char u8idy = 0; ++ unsigned char u8idz = 0; ++ unsigned short u16val = 0; ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL OD----------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, ++ "------0---------320-------640-------960-------1280------1600------1920------2240------2560\n"); ++ for(u8idy = 0;u8idy<=(gstHvspScalingCfg.stCropWin.u16Height/32)+1;u8idy++) ++ { ++ if(u8idy==10) ++ { ++ str += MsOS_scnprintf(str, end - str, "|320 "); ++ } ++ else if(u8idy==20) ++ { ++ str += MsOS_scnprintf(str, end - str, "|640 "); ++ } ++ else if(u8idy==30) ++ { ++ str += MsOS_scnprintf(str, end - str, "|960 "); ++ } ++ else if(u8idy==40) ++ { ++ str += MsOS_scnprintf(str, end - str, "|1280 "); ++ } ++ else if(u8idy==50) ++ { ++ str += MsOS_scnprintf(str, end - str, "|1600 "); ++ } ++ else ++ { ++ str += MsOS_scnprintf(str, end - str, "| "); ++ } ++ for(u8idx =0;u8idx<=(gstHvspScalingCfg.stCropWin.u16Width/(16*32));u8idx++) ++ { ++ u16val = 0; ++ u16val = Drv_HVSP_PriMaskGetSRAM(u8idx, u8idy); ++ for(u8idz = 0;u8idz<16;u8idz++) ++ { ++ if(u16val &(0x1 < OSD :open OSD\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 0 > OSD :close OSD\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 2 > OSD :Set OSD before\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 3 > OSD :Set OSD After\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 4 > OSD :Set OSD Bypass\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 5 > OSD :Set OSD Bypass Off\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 6 > OSD :Set OSD WTM Bypass\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 7 > OSD :Set OSD WTM Bypass Off\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 8 > OSD :Set Privacy Mask On\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 9 > OSD :Set Privacy Mask Off\n"); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL OSD----------------------------\n"); ++ return (str - buf); ++} ++void MDrv_HVSP_OsdStore(const char *buf,EN_MDRV_HVSP_ID_TYPE enHVSP_ID) ++{ ++ const char *str = buf; ++ ST_DRV_HVSP_OSD_CONFIG stOSdCfg; ++ EN_HVSP_ID_TYPE enID; ++ enID = enHVSP_ID == E_MDRV_HVSP_ID_2 ? E_HVSP_ID_2 : ++ enHVSP_ID == E_MDRV_HVSP_ID_3 ? E_HVSP_ID_3 : ++ E_HVSP_ID_1; ++ ++ Drv_HVSP_GetOSDAttribute(enID,&stOSdCfg); ++ if((int)*str == 49) //input 1 ++ { ++ SCL_ERR( "[OSD]open OSD %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDEn = 1; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 48) //input 0 ++ { ++ SCL_ERR( "[OSD]close OSD %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDEn = 0; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 50) //input 2 ++ { ++ SCL_ERR( "[OSD]Set OSD before %d\n",(int)*str); ++ stOSdCfg.enOSD_loc = EN_DRV_HVSP_OSD_LOC_BEFORE; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 51) //input 3 ++ { ++ SCL_ERR( "[OSD]Set OSD After %d\n",(int)*str); ++ stOSdCfg.enOSD_loc = EN_DRV_HVSP_OSD_LOC_AFTER; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 52) //input 4 ++ { ++ SCL_ERR( "[OSD]Set OSD Bypass %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDBypass = 1; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 53) //input 5 ++ { ++ SCL_ERR( "[OSD]Set OSD Bypass Off %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bOSDBypass = 0; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 54) //input 6 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bWTMBypass = 1; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 55) //input 7 ++ { ++ SCL_ERR( "[OSD]Set OSD WTM Bypass Off %d\n",(int)*str); ++ stOSdCfg.stOsdOnOff.bWTMBypass = 0; ++ Drv_HVSP_SetOSDConfig(enID, &stOSdCfg); ++ } ++ else if((int)*str == 56) //input 8 ++ { ++ SCL_ERR( "[OSD]Set OD ON %d\n",(int)*str); ++ Drv_HVSP_SetPriMaskTrigger(EN_HVSP_PRIMASK_ENABLE); ++ } ++ else if((int)*str == 57) //input 9 ++ { ++ SCL_ERR( "[OSD]Set OD Off %d\n",(int)*str); ++ Drv_HVSP_SetPriMaskTrigger(EN_HVSP_PRIMASK_ONLYHWOFF); ++ } ++} ++ssize_t MDrv_HVSP_LockShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL Lock----------------------------\n"); ++ str = MsOS_CheckMutex(str,end); ++ str += MsOS_scnprintf(str, end - str, "------------------------SCL Lock----------------------------\n"); ++ return (str - buf); ++} ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mdrv_multiinst.c b/drivers/mstar/scl/infinity3/src/mdrv_multiinst.c +new file mode 100644 +index 00000000..4cdb5c5b +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mdrv_multiinst.c +@@ -0,0 +1,1379 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_MULTI_INST_C ++#include ++#include ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvpnl.h" ++ ++ ++#include "mdrv_scl_dbg.h" ++#include "mdrv_hvsp_io_i3_st.h" ++#include "mdrv_scldma_io_i3_st.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++#include "mdrv_hvsp.h" ++#include "mdrv_scldma.h" ++#include "mdrv_multiinst_st.h" ++#include "mdrv_multiinst.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define MULTIINST_SEM_DBG 0 ++#define _MULTIINST_SEM_TIMIE_OUT 5000 ++ ++#define MULTIINST_WAIT_SEM_FOREVER(_sem) down(&_sem) ++#define MULTIINST_RELEASE_SEM_FOREVER(_sem) up(&_sem) ++#define DRV_SC1_MUTEX_LOCK() MsOS_ObtainMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2],MSOS_WAIT_FOREVER) ++#define DRV_SC1_MUTEX_UNLOCK() MsOS_ReleaseMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2]) ++#define DRV_SC3_MUTEX_LOCK() MsOS_ObtainMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3],MSOS_WAIT_FOREVER) ++#define DRV_SC3_MUTEX_UNLOCK() MsOS_ReleaseMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3]) ++#define DRV_DSP_MUTEX_LOCK() MsOS_ObtainMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP],MSOS_WAIT_FOREVER) ++#define DRV_DSP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP]) ++#if MULTIINST_SEM_DBG ++ ++#define MULTIINST_WAIT_SEM(_sem) \ ++ printk(KERN_INFO "+++ [LOCK][%s]_1_[%d] \n", __FUNCTION__, __LINE__); \ ++ if(down_timeout(&_sem, msecs_to_jiffies(_MULTIINST_SEM_TIMIE_OUT)) < 0) \ ++ { \ ++ printk(KERN_INFO "[LOCK][%s] [%d], LOCK3 Mutex Time Out \n", __FUNCTION__, __LINE__); \ ++ } \ ++ printk(KERN_INFO "+++ [LOCK][%s]_2_[%d] \n", __FUNCTION__, __LINE__); ++ ++ ++#define MULTIINST_RELEASE_SEM(_sem) \ ++ printk(KERN_INFO "--- [LOCK][%s] [%d] \n", __FUNCTION__, __LINE__); \ ++ up(&_sem); ++ ++ ++#else ++#define MULTIINST_WAIT_SEM(_sem) \ ++ if(down_timeout(&_sem, msecs_to_jiffies(_MULTIINST_SEM_TIMIE_OUT)) < 0) \ ++ { \ ++ printk(KERN_INFO "[LOCK][%s] [%d], LOCK3 Mutex Time Out \n", __FUNCTION__, __LINE__); \ ++ } ++ ++#define MULTIINST_RELEASE_SEM(_sem) up(&_sem) ++ ++#endif //MULTIINST_SEM_DBG ++ ++ ++#define MDRV_MULTI_INST_HVSP_PRIVATE_ID_HEADER 0xA00000 ++#define MDRV_MULTI_INST_SCLDMA_PRIVATE_ID_HEADER 0xD00000 ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++struct semaphore gMultiInstLockSem[E_MDRV_MULTI_INST_LOCK_ID_MAX]; ++struct semaphore gMultiInstHvspEntrySem[E_MDRV_MULTI_INST_HVSP_DATA_ID_MAX]; ++struct semaphore gMultiInstScldmaEntrySem[E_MDRV_MULTI_INST_SCLDMA_DATA_ID_MAX]; ++ ++ST_MDRV_MULTI_INST_LOCK_CONFIG gstMultiInstLockCfg[E_MDRV_MULTI_INST_LOCK_ID_MAX]; ++ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG gstMultiInstScldmaEntryCfg[E_MDRV_MULTI_INST_SCLDMA_DATA_ID_MAX][MDRV_MULTI_INST_SCLDMA_NUM]; ++ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG gstMultiInstHvspEntryCfg[E_MDRV_MULTI_INST_HVSP_DATA_ID_MAX][MDRV_MULTI_INST_HVSP_NUM]; ++signed long gs32PreMultiInstScldmaPrivateId[E_MDRV_MULTI_INST_SCLDMA_DATA_ID_MAX]; ++signed long gs32PreMultiInstHvspPrivateId[E_MDRV_MULTI_INST_HVSP_DATA_ID_MAX]; ++ ++MS_S32 _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_MAX]={-1,-1,-1}; ++MS_BOOL _LOCK_Mutex_flag[E_MDRV_MULTI_INST_LOCK_ID_MAX]={0,0,0}; ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++ ++//---------------------------------------------------------------------------------------------------------------- ++// ++// Multi Instance Lock ++// ++//---------------------------------------------------------------------------------------------------------------- ++ ++unsigned char _MDrv_MultiInst_Lock_Get_PrivateID_Num(EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID) ++{ ++ unsigned char u8Num; ++ ++ switch(enLock_ID) ++ { ++ case E_MDRV_MULTI_INST_LOCK_ID_SC_1_2: ++ u8Num = 4; ++ break; ++ case E_MDRV_MULTI_INST_LOCK_ID_SC_3: ++ u8Num = 2; ++ break; ++ case E_MDRV_MULTI_INST_LOCK_ID_DISP: ++ u8Num = 1; ++ break; ++ default: ++ u8Num = 0; ++ break; ++ } ++ ++ return u8Num; ++} ++ ++ ++unsigned char MDrv_MultiInst_Lock_Init(EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID) ++{ ++ unsigned char bRet = 1; ++ unsigned char i; ++ unsigned char u8PrivateIDNum = 0; ++ char word[] = {"_SC1_Mutex"}; ++ char word2[] = {"_SC3_Mutex"}; ++ char word3[] = {"_DSP_Mutex"}; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enLock_ID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ u8PrivateIDNum = _MDrv_MultiInst_Lock_Get_PrivateID_Num(enLock_ID); ++ if(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2] == -1) ++ { ++ _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2] = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ } ++ if(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3] == -1) ++ { ++ _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_SC_3] = MsOS_CreateMutex(E_MSOS_FIFO, word2, MSOS_PROCESS_SHARED); ++ } ++ if(_LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP] == -1) ++ { ++ _LOCK_Mutex[E_MDRV_MULTI_INST_LOCK_ID_DISP] = MsOS_CreateMutex(E_MSOS_FIFO, word3, MSOS_PROCESS_SHARED); ++ } ++ if(gstMultiInstLockCfg[enLock_ID].ps32PrivateID == NULL) ++ { ++ gstMultiInstLockCfg[enLock_ID].u8IDNum = u8PrivateIDNum; ++ gstMultiInstLockCfg[enLock_ID].ps32PrivateID = MsOS_Memalloc(sizeof(signed long)*u8PrivateIDNum, GFP_KERNEL); ++ if(gstMultiInstLockCfg[enLock_ID].ps32PrivateID) ++ { ++ for(i=0; ips32PrivateID[0]); ++ if(stCfg->u8IDNum != u8PrivateIDNum) ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d) LockAlloc fail LockID:%d, %d!=%d\n", ++ __FUNCTION__, __LINE__, enLock_ID, stCfg->u8IDNum, u8PrivateIDNum); ++ ++ return 0; ++ } ++ if(enLock_ID == E_MDRV_MULTI_INST_LOCK_ID_SC_1_2) ++ { ++ DRV_SC1_MUTEX_LOCK(); ++ MULTIINST_WAIT_SEM(gMultiInstLockSem[enLock_ID]); ++ _LOCK_Mutex_flag[E_MDRV_MULTI_INST_LOCK_ID_SC_1_2] = 1; ++ MULTIINST_RELEASE_SEM(gMultiInstLockSem[enLock_ID]); ++ } ++ else if(enLock_ID == E_MDRV_MULTI_INST_LOCK_ID_SC_3) ++ { ++ DRV_SC3_MUTEX_LOCK(); ++ MULTIINST_WAIT_SEM(gMultiInstLockSem[enLock_ID]); ++ _LOCK_Mutex_flag[E_MDRV_MULTI_INST_LOCK_ID_SC_3] = 1; ++ MULTIINST_RELEASE_SEM(gMultiInstLockSem[enLock_ID]); ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enLock_ID)), "[MULTIINST]LOCK !! Id:%ld\n",stCfg->ps32PrivateID[0]); ++ } ++ else if(enLock_ID == E_MDRV_MULTI_INST_LOCK_ID_DISP) ++ { ++ DRV_DSP_MUTEX_LOCK(); ++ MULTIINST_WAIT_SEM(gMultiInstLockSem[enLock_ID]); ++ _LOCK_Mutex_flag[E_MDRV_MULTI_INST_LOCK_ID_DISP] = 1; ++ MULTIINST_RELEASE_SEM(gMultiInstLockSem[enLock_ID]); ++ } ++ ++ ++ MULTIINST_WAIT_SEM(gMultiInstLockSem[enLock_ID]); ++ ++ for(i=0; ips32PrivateID[i]); ++ ++ gstMultiInstLockCfg[enLock_ID].ps32PrivateID[i] = stCfg->ps32PrivateID[i]; ++ } ++ ++ bRet = 1; ++ } ++ else ++ { ++ ++ #if SCL_DBG_LV_MULTI_INST_LOCK_LOG ++ for(i=0;ips32PrivateID[i]); ++ } ++ #endif ++ bRet = 0; ++ } ++ ++ MULTIINST_RELEASE_SEM(gMultiInstLockSem[enLock_ID]); ++ return bRet; ++ ++} ++ ++//---------------------------------------------------------------------------------------------------------------- ++// ++// Multi Instance Data ++// ++//---------------------------------------------------------------------------------------------------------------- ++unsigned char MDrv_MultiInst_Lock_Free(EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID, ST_MDRV_MULTI_INST_LOCK_CONFIG *pstCfg) ++{ ++ unsigned char i; ++ unsigned char bRet = 1; ++ unsigned char u8PrivateIDNum = _MDrv_MultiInst_Lock_Get_PrivateID_Num(enLock_ID); ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enLock_ID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ MULTIINST_WAIT_SEM(gMultiInstLockSem[enLock_ID]); ++ ++ if(pstCfg) ++ { ++ for(i=0; ips32PrivateID[i]) ++ { ++ bRet = 0; ++ break; ++ } ++ } ++ } ++ ++ if(bRet) ++ { ++ for(i=0;istData.stFlag.bInCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stInCfg, (ST_MDRV_HVSP_INPUT_CONFIG *)pData, sizeof(ST_MDRV_HVSP_INPUT_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG) ++ { ++ pEntry->stData.stFlag.bScaleCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stScaleCfg, (ST_MDRV_HVSP_SCALING_CONFIG *)pData, sizeof(ST_MDRV_HVSP_SCALING_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_POST_CROP_CONFIG) ++ { ++ pEntry->stData.stFlag.bPostCropCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stPostCropCfg, (ST_MDRV_HVSP_POSTCROP_CONFIG *)pData, sizeof(ST_MDRV_HVSP_POSTCROP_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_MEM_REQ_CONFIG) ++ { ++ pEntry->stData.stFlag.bMemCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stMemCfg, (ST_MDRV_HVSP_IPM_CONFIG *)pData, sizeof(ST_MDRV_HVSP_IPM_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG) ++ { ++ pEntry->stData.stFlag.bOSDCfg= 1; ++ MsOS_Memcpy(&pEntry->stData.stOSDCfg, (ST_MDRV_HVSP_OSD_CONFIG*)pData, sizeof(ST_MDRV_HVSP_OSD_CONFIG)); ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): PrivateId:%lx, bMem:%d, bIn:%d, bScale:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, pEntry->stData.stFlag.bMemCfg, pEntry->stData.stFlag.bInCfg, ++ pEntry->stData.stFlag.bScaleCfg); ++ ++ MULTIINST_RELEASE_SEM(gMultiInstHvspEntrySem[enID]); ++ bRet = 1; ++ } ++ ++ return bRet; ++} ++ ++unsigned char _MDrv_MultiInst_Entry_SaveScldmaData( ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ unsigned char bRet = 1; ++ unsigned char index = 0; ++ if(pEntry == NULL) ++ { ++ bRet = 0; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): ScldmaSaveData fail: PrivateId:NULL\n", __FUNCTION__, __LINE__); ++ return bRet; ++ } ++ else ++ { ++ MULTIINST_WAIT_SEM(gMultiInstScldmaEntrySem[enID]); ++ if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG) ++ { ++ pEntry->stData.stFlag.bInBufCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stInBufCfg, (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG) ++ { ++ ST_MDRV_SCLDMA_BUFFER_CONFIG stCfg; ++ MsOS_Memcpy(&stCfg, (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ index = stCfg.enMemType; ++ if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_FRM) ++ { ++ pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_FRM], (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_SNP) ++ { ++ pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_SNP], (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_IMI) ++ { ++ pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_IMI], (ST_MDRV_SCLDMA_BUFFER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_BUFFER_CONFIG)); ++ } ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG) ++ { ++ pEntry->stData.stFlag.bInTrigCfg = 1; ++ MsOS_Memcpy(&pEntry->stData.stInTrigCfg, (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG) ++ { ++ ST_MDRV_SCLDMA_TRIGGER_CONFIG stCfg; ++ MsOS_Memcpy(&stCfg, (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ index = stCfg.enMemType; ++ if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_FRM) ++ { ++ pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM], (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_SNP) ++ { ++ pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP], (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ else if(stCfg.enMemType == E_MDRV_SCLDMA_MEM_IMI) ++ { ++ pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]= 1; ++ MsOS_Memcpy(&pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI], (ST_MDRV_SCLDMA_TRIGGER_CONFIG *)pData, sizeof(ST_MDRV_SCLDMA_TRIGGER_CONFIG)); ++ } ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): PrivateId:%lx, bInBuf:%d, bOutBuf[%hhd]:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, pEntry->stData.stFlag.bInBufCfg, index,pEntry->stData.stFlag.bOutBufCfg[index]); ++ ++ MULTIINST_RELEASE_SEM(gMultiInstScldmaEntrySem[enID]); ++ bRet = 1; ++ } ++ ++ return bRet; ++} ++ ++unsigned char _MDrv_MultiInst_Entry_ReloadHvspData( ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd) ++{ ++ unsigned char bRet = 1; ++ ST_MDRV_MULTI_INST_HVSP_FLAG_TYPE stFlag; ++ EN_MDRV_HVSP_ID_TYPE enHvspId = enID == E_MDRV_MULTI_INST_HVSP_DATA_ID_1 ? E_MDRV_HVSP_ID_1 : ++ enID == E_MDRV_MULTI_INST_HVSP_DATA_ID_2 ? E_MDRV_HVSP_ID_2 : ++ enID == E_MDRV_MULTI_INST_HVSP_DATA_ID_3 ? E_MDRV_HVSP_ID_3 : ++ E_MDRV_HVSP_ID_MAX ; ++ MsOS_Memset(&stFlag, 0, sizeof(ST_MDRV_MULTI_INST_HVSP_FLAG_TYPE)); ++ ++ MULTIINST_WAIT_SEM(gMultiInstHvspEntrySem[enID]); ++ ++ if(pEntry) ++ { ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ++ { ++ //Reload ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(pEntry->s32PivateId != gs32PreMultiInstHvspPrivateId[enID] && ++ gs32PreMultiInstHvspPrivateId[enID] != -1) ++ { ++ //if not the same fd,reload others setting.(ioctl will set itself,so just set others configuration) ++ if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_IN_CONFIG) ++ { ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SCALING_CONFIG) ++ { ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_POST_CROP_CONFIG) ++ { ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ stFlag.bOSDCfg = pEntry->stData.stFlag.bOSDCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_HVSP_SET_OSD_CONFIG) ++ { ++ stFlag.bInCfg = pEntry->stData.stFlag.bInCfg; ++ stFlag.bScaleCfg = pEntry->stData.stFlag.bScaleCfg; ++ stFlag.bPostCropCfg = pEntry->stData.stFlag.bPostCropCfg; ++ stFlag.bMemCfg = pEntry->stData.stFlag.bMemCfg; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::The first time\n", __FUNCTION__, __LINE__); ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::PrivateId:%lx, bMem:%d, bIn:%d, bScale:%d,bPostCrop:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, stFlag.bMemCfg, stFlag.bInCfg, ++ stFlag.bScaleCfg, stFlag.bPostCropCfg); ++ ++ bRet = 1; ++ ++ if(stFlag.bMemCfg) ++ { ++ ST_HVSP_CMD_TRIG_CONFIG stHvspCmdTrigCfg; ++ Drv_HVSP_SetCMDQTrigTypeByRIU(&stHvspCmdTrigCfg); ++ ++ bRet &= MDrv_HVSP_SetInitIPMConfig(enHvspId, &pEntry->stData.stMemCfg); ++ ++ Drv_HVSP_SetCMDQTrigType(&stHvspCmdTrigCfg); ++ } ++ ++ if(stFlag.bInCfg) ++ { ++ bRet &= MDrv_HVSP_SetInputConfig(enHvspId, &pEntry->stData.stInCfg); ++ } ++ ++ ++ if(stFlag.bScaleCfg) ++ { ++ bRet &= MDrv_HVSP_SetScalingConfig(enHvspId, &pEntry->stData.stScaleCfg); ++ } ++ ++ if(stFlag.bPostCropCfg) ++ { ++ bRet &= MDrv_HVSP_SetPostCropConfig(enHvspId, &pEntry->stData.stPostCropCfg); ++ } ++ ++ if(stFlag.bOSDCfg) ++ { ++ bRet &= MDrv_HVSP_SetOSDConfig(enHvspId, &pEntry->stData.stOSDCfg); ++ } ++ ++ gs32PreMultiInstHvspPrivateId[enID] = pEntry->s32PivateId; ++ } ++ else ++ { ++ bRet = 0; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d):: ReloadHvsp Fail, hvspId:%d\n", ++ __FUNCTION__, __LINE__, enID); ++ } ++ ++ MULTIINST_RELEASE_SEM(gMultiInstHvspEntrySem[enID]); ++ ++ return bRet; ++} ++ ++ ++unsigned char _MDrv_MultiInst_Entry_ReloadScldmaData( ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd) ++{ ++ unsigned char bRet; ++ ST_MDRV_MULTI_INST_SCLDMA_FLAG_TYPE stFlag; ++ EN_MDRV_SCLDMA_ID_TYPE enScldmaId = enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_1 ? E_MDRV_SCLDMA_ID_1 : ++ enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_2 ? E_MDRV_SCLDMA_ID_2 : ++ enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_3 ? E_MDRV_SCLDMA_ID_3 : ++ enID == E_MDRV_MULTI_INST_SCLDMA_DATA_ID_4 ? E_MDRV_SCLDMA_ID_PNL : ++ E_MDRV_SCLDMA_ID_NUM; ++ MsOS_Memset(&stFlag, 0, sizeof(ST_MDRV_MULTI_INST_SCLDMA_FLAG_TYPE)); ++ ++ MULTIINST_WAIT_SEM(gMultiInstScldmaEntrySem[enID]); ++ ++ if(pEntry) ++ { ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ++ { ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ stFlag.bInBufCfg = pEntry->stData.stFlag.bInBufCfg; ++ stFlag.bInTrigCfg = pEntry->stData.stFlag.bInTrigCfg; ++ if(pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_FRM].enBufMDType==E_MDRV_SCLDMA_BUFFER_MD_RING ++ &&(enScldmaId==E_MDRV_SCLDMA_ID_1 || enScldmaId==E_MDRV_SCLDMA_ID_2)) ++ { ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM] = 0; ++ } ++ else ++ { ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ } ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ } ++ else if(pEntry->s32PivateId != gs32PreMultiInstScldmaPrivateId[enID] && ++ gs32PreMultiInstScldmaPrivateId[enID] != -1) ++ { ++ if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_BUFFER_CONFIG) ++ { ++ //for Sc3 , Sc1,Sc2 ignore ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_BUFFER_CONFIG) ++ { ++ //for Sc3 , Sc1,Sc2 ignore ++ stFlag.bInBufCfg = pEntry->stData.stFlag.bInBufCfg; ++ } ++ else if(enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_IN_TRIGGER_CONFIG || ++ enCmd == E_MDRV_MULTI_INST_CMD_SCLDMA_OUT_TRIGGER_CONFIG ++ ) ++ { ++ stFlag.bInBufCfg = pEntry->stData.stFlag.bInBufCfg; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]; ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI] = pEntry->stData.stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::The first time\n", __FUNCTION__, __LINE__); ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)::PrivateId:%lx, bInBuf:%d,bOutBuf_FRM:%d, bOutBuf_SNP:%d, bOutBuf_IMI:%d, bInTrig:%d, bOutTrig_FRM:%d, bOutTrig_SNP:%d, bOutTrig_IMI:%d\n", ++ __FUNCTION__, __LINE__, ++ pEntry->s32PivateId, stFlag.bInBufCfg, ++ stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM],stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP],stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI], ++ stFlag.bInTrigCfg, ++ stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM],stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP],stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]); ++ ++ bRet = 1; ++ if(stFlag.bInBufCfg) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAReadClientConfig(enScldmaId, &pEntry->stData.stInBufCfg); ++ } ++ ++ if(stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientConfig(enScldmaId, &pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_FRM]); ++ } ++ ++ ++ if(stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientConfig(enScldmaId, &pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_SNP]); ++ } ++ ++ ++ if(stFlag.bOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientConfig(enScldmaId, &pEntry->stData.stOutBufCfg[E_MDRV_SCLDMA_MEM_IMI]); ++ } ++ ++ if(stFlag.bInTrigCfg) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAReadClientTrigger(enScldmaId, &pEntry->stData.stInTrigCfg); ++ } ++ ++ if(stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientTrigger(enScldmaId, &pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_FRM]); ++ } ++ ++ if(stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientTrigger(enScldmaId, &pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_SNP]); ++ } ++ ++ if(stFlag.bOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]) ++ { ++ bRet &= MDrv_SCLDMA_SetDMAWriteClientTrigger(enScldmaId, &pEntry->stData.stOutTrigCfg[E_MDRV_SCLDMA_MEM_IMI]); ++ } ++ ++ gs32PreMultiInstScldmaPrivateId[enID] = pEntry->s32PivateId; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d):: ReloadScldmaFail, ScldmaId:%d\n", ++ __FUNCTION__, __LINE__, enID); ++ ++ bRet = 0; ++ } ++ ++ MULTIINST_RELEASE_SEM(gMultiInstScldmaEntrySem[enID]); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_MultiInst_GetHvspQuantifyPreInstId(void) ++{ ++ unsigned char i; ++ unsigned char Ret = 0; ++ for(i=0; is32PivateId) ) ++ { ++ // Reload Data ++ bReload = _MDrv_MultiInst_Entry_ReloadHvspData(enID, pEntry, enCmd); ++ // Save Data ++ bSave = (enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ? ++ 1 : ++ _MDrv_MultiInst_Entry_SaveHvspData(enID, pEntry, enCmd, pData); ++ ++ if(bReload & bSave) ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashHvspData fail, PrivateId=%lx, R:%d, S:%d\n", ++ __FUNCTION__, __LINE__, pEntry->s32PivateId, bReload, bSave); ++ } ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashHvspData LOCKED, PrivateId=%lx\n", ++ __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ } ++ } ++ return enRet; ++} ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE _MDrv_MultiInst_Entry_FlashScldmaData( ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enID, ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLockID; ++ unsigned char bSave, bReload ; ++ ++ if(enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG && pEntry == NULL) ++ { ++ MS_U8 i; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): Force_Relaod, PrivateId=%lx\n", ++ __FUNCTION__, __LINE__, gs32PreMultiInstScldmaPrivateId[enID]); ++ ++ for(i=0; is32PivateId) ) ++ { ++ // Reload Data ++ bReload = _MDrv_MultiInst_Entry_ReloadScldmaData(enID, pEntry, enCmd); ++ ++ // Save Data ++ bSave = (enCmd == E_MDRV_MULTI_INST_CMD_FORCE_RELOAD_CONFIG) ? ++ 1 : ++ _MDrv_MultiInst_Entry_SaveScldmaData(enID, pEntry, enCmd, pData); ++ ++ if(bReload && bSave) ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashScldmaData fail, PrivateId=%lx, R:%d, S:%d\n", ++ __FUNCTION__, __LINE__, pEntry->s32PivateId, bReload, bSave); ++ } ++ } ++ else ++ { ++ enRet = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashScldmaData LOCKED, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ } ++ } ++ } ++ ++ return enRet; ++} ++ ++ ++ ++unsigned char MDrv_MultiInst_Entry_Init_Variable(EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID) ++{ ++ unsigned char bRet = 1; ++ unsigned short i; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enHvspId; ++ ++ if( _MDrv_MultiInst_Trans_HvspID(enID, &enHvspId)) ++ { ++ for(i=0;ibUsed = 0; ++ MsOS_Memset(&pEntry->stData, 0, sizeof(ST_MDRV_MULTI_INST_HVSP_DATA_TYPE)); ++ MULTIINST_RELEASE_SEM(gMultiInstHvspEntrySem[enHvspId]); ++ ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): Free fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enSlcmdaId; ++ if( _MDrv_MultiInst_Trans_ScldmaID(enID, &enSlcmdaId) && pPrivate_Data) ++ { ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = NULL; ++ ++ MULTIINST_WAIT_SEM(gMultiInstScldmaEntrySem[enSlcmdaId]); ++ pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivate_Data; ++ pEntry->bUsed = 0; ++ MsOS_Memset(&pEntry->stData, 0, sizeof(ST_MDRV_MULTI_INST_SCLDMA_DATA_TYPE)); ++ MULTIINST_RELEASE_SEM(gMultiInstScldmaEntrySem[enSlcmdaId]); ++ ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): Free fail EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): Free fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ ++ return bRet; ++} ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE MDrv_MultiInst_Entry_FlashData( ++ EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID, ++ void *pPrivateData, ++ EN_MDRV_MULTI_INST_CMD_TYPE enCmd, ++ void *pData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enRet; ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ EN_MDRV_MULTI_INST_HVSP_DATA_ID_TYPE enHvspId; ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *)pPrivateData; ++ if(_MDrv_MultiInst_Trans_HvspID(enID, &enHvspId)) ++ { ++ enRet = _MDrv_MultiInst_Entry_FlashHvspData(enHvspId, pEntry, enCmd, pData); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashData fail, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ EN_MDRV_MULTI_INST_SCLDMA_DATA_ID_TYPE enSclmdaId; ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivateData; ++ if(_MDrv_MultiInst_Trans_ScldmaID(enID, &enSclmdaId )) ++ { ++ enRet = _MDrv_MultiInst_Entry_FlashScldmaData(enSclmdaId, pEntry, enCmd, pData); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d): FlashData fail, PrivateId=%lx\n", __FUNCTION__, __LINE__, pEntry->s32PivateId); ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): FlashData fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ enRet = E_MDRV_MULTI_INST_STATUS_FAIL; ++ return enRet; ++ } ++ ++ return enRet; ++} ++ ++ ++unsigned char MDrv_MultiInst_Entry_GetPirvateId(EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID, void *pPrivateData, signed long *ps32PrivateId) ++{ ++ unsigned char bRet; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *)pPrivateData; ++ ++ if(pEntry) ++ { ++ *ps32PrivateId = pEntry->s32PivateId; ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): GetPrivateID fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ *ps32PrivateId = -1; ++ bRet = 0; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP) ++ { ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivateData; ++ if(pEntry) ++ { ++ *ps32PrivateId = pEntry->s32PivateId; ++ bRet = 1; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): GetPrivateID fail, EntryId=%d\n", __FUNCTION__, __LINE__, enID); ++ *ps32PrivateId = -1; ++ bRet = 0; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): GetPrivateID fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ bRet = 0; ++ } ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ENTRY()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d) EntryId:%x PrivateID=%lx\n", ++ __FUNCTION__, __LINE__, enID, *ps32PrivateId); ++ return bRet; ++} ++ ++EN_MDRV_MULTI_INST_STATUS_TYPE MDrv_MultiInst_Etnry_IsFree(EN_MDRV_MULTI_INST_ENTRY_ID_TYPE enID, void *pPrivateData) ++{ ++ EN_MDRV_MULTI_INST_STATUS_TYPE enIsFree; ++ EN_MDRV_MULTI_INST_LOCK_ID_TYPE enLock_ID; ++ ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_FUNC()&(Get_DBGMG_MULTI(enID)), "[MULTIINST]%s(%d)\n", __FUNCTION__, __LINE__); ++ ++ if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_HVSP_ENTRY_CONFIG *)pPrivateData; ++ ++ enLock_ID = (enID == E_MDRV_MULTI_INST_ENTRY_ID_HVSP1) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_HVSP2) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ E_MDRV_MULTI_INST_LOCK_ID_SC_3 ; ++ if(pEntry) ++ { ++ if( MDrv_MultiInst_Lock_IsFree(enLock_ID, pEntry->s32PivateId) ) ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): EntryIsFree fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ enIsFree = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else if(enID <= E_MDRV_MULTI_INST_ENTRY_ID_DISP && enID > E_MDRV_MULTI_INST_ENTRY_ID_HVSP3) ++ { ++ ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *pEntry = (ST_MDRV_MULTI_INST_SCLDMA_ENTRY_CONFIG *)pPrivateData; ++ enLock_ID = (enID == E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA1) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA2) ? E_MDRV_MULTI_INST_LOCK_ID_SC_1_2 : ++ (enID == E_MDRV_MULTI_INST_ENTRY_ID_SCLDMA3) ? E_MDRV_MULTI_INST_LOCK_ID_SC_3 : ++ E_MDRV_MULTI_INST_LOCK_ID_DISP; ++ if(pEntry) ++ { ++ if( MDrv_MultiInst_Lock_IsFree(enLock_ID, pEntry->s32PivateId) ) ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_SUCCESS; ++ } ++ else ++ { ++ enIsFree = E_MDRV_MULTI_INST_STATUS_LOCKED; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): EntryIsFree fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ enIsFree = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MULTI_INST_ERR, "[MULTIINST]%s(%d): EntryIsFree fail, EntryId:%d\n", __FUNCTION__, __LINE__, enID); ++ enIsFree = E_MDRV_MULTI_INST_STATUS_FAIL; ++ } ++ ++ return enIsFree; ++} +diff --git a/drivers/mstar/scl/infinity3/src/mdrv_pnl.c b/drivers/mstar/scl/infinity3/src/mdrv_pnl.c +new file mode 100644 +index 00000000..29eeda7e +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mdrv_pnl.c +@@ -0,0 +1,145 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_PNL_C ++#include ++#include ++#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvpnl.h" ++ ++#include "mdrv_pnl_io_st.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_pnl.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// gstCfg ++/// use in suspend/resume to save information ++//////////////// ++ST_MDRV_PNL_TIMING_CONFIG gstCfg; ++ST_MDRV_PNL_TIMING_CONFIG gstLPLLCfg; ++///////////////// ++/// gbResume ++/// use to determine whether need to set timing config as resume. ++//////////////// ++unsigned char gbResume=0; ++unsigned char gbResumeLPLL=0; ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void MDrv_PNL_Release(void) ++{ ++ if(gbResume|| gbResumeLPLL) ++ { ++ Drv_PNL_Release(); ++ } ++} ++void MDrv_PNL_Exit(unsigned char bCloseISR) ++{ ++ Drv_PNL_Exit(bCloseISR); ++} ++unsigned char MDrv_PNL_Init(ST_MDRV_PNL_INIT_CONFIG *pCfg) ++{ ++ ST_PNL_INIT_CONFIG stInitCfg; ++ stInitCfg.u32RiuBase = pCfg->u32RiuBase; ++ ++ if(Drv_PNL_Init(&stInitCfg) == 0) ++ { ++ SCL_ERR("[PNL]%s, Init Fail\n", __FUNCTION__); ++ return 0; ++ } ++ else ++ { ++ return 1; ++ } ++} ++void MDrv_PNL_Resume(void) ++{ ++ Drv_PNL_Resume(); ++ if(gbResume) ++ { ++ MDrv_PNL_Set_Timing_Config(&gstCfg); ++ } ++ if(gbResumeLPLL) ++ { ++ MDrv_PNL_Set_LPLL_Config(&gstLPLLCfg); ++ } ++} ++ ++unsigned char MDrv_PNL_Set_LPLL_Config(ST_MDRV_PNL_TIMING_CONFIG *pCfg) ++{ ++ ST_PNL_TIMING_CONFIG stTimingCfg; ++ ++ stTimingCfg.u16Vtt = pCfg->u16Vtt; ++ stTimingCfg.u16Htt = pCfg->u16Htt; ++ stTimingCfg.u16VFreqx10 = pCfg->u16VFreqx10; ++ MsOS_Memcpy(&gstLPLLCfg, pCfg,sizeof(ST_MDRV_PNL_TIMING_CONFIG)); ++ gbResumeLPLL=1; ++ if(Drv_PNL_Set_LPLL_Config(&stTimingCfg) == 0) ++ { ++ SCL_ERR("[PNL]%s, Set Timing Fail\n", __FUNCTION__); ++ return 0; ++ } ++ else ++ { ++ return 1; ++ } ++ ++} ++ ++unsigned char MDrv_PNL_Set_Timing_Config(ST_MDRV_PNL_TIMING_CONFIG *pCfg) ++{ ++ ST_PNL_TIMING_CONFIG stTimingCfg; ++ ++ stTimingCfg.u16Vsync_St = pCfg->u16Vsync_St; ++ stTimingCfg.u16Vsync_End = pCfg->u16Vsync_End; ++ stTimingCfg.u16Vde_St = pCfg->u16Vde_St; ++ stTimingCfg.u16Vde_End = pCfg->u16Vde_End; ++ stTimingCfg.u16Vfde_St = pCfg->u16Vfde_St; ++ stTimingCfg.u16Vfde_End = pCfg->u16Vfde_End; ++ stTimingCfg.u16Vtt = pCfg->u16Vtt; ++ ++ stTimingCfg.u16Hsync_St = pCfg->u16Hsync_St; ++ stTimingCfg.u16Hsync_End = pCfg->u16Hsync_End; ++ stTimingCfg.u16Hde_St = pCfg->u16Hde_St; ++ stTimingCfg.u16Hde_End = pCfg->u16Hde_End; ++ stTimingCfg.u16Hfde_St = pCfg->u16Hfde_St; ++ stTimingCfg.u16Hfde_End = pCfg->u16Hfde_End; ++ ++ stTimingCfg.u16Htt = pCfg->u16Htt; ++ ++ stTimingCfg.u16VFreqx10 = pCfg->u16VFreqx10; ++ MsOS_Memcpy(&gstCfg, pCfg,sizeof(ST_MDRV_PNL_TIMING_CONFIG)); ++ gbResume=1; ++ if( Drv_PNL_Set_Timing_Config(&stTimingCfg) == 0) ++ { ++ SCL_ERR("[PNL]%s, Set Timing Fail\n", __FUNCTION__); ++ return 0; ++ } ++ else ++ { ++ return 1; ++ } ++ ++} +diff --git a/drivers/mstar/scl/infinity3/src/mdrv_scldma.c b/drivers/mstar/scl/infinity3/src/mdrv_scldma.c +new file mode 100644 +index 00000000..332640f5 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mdrv_scldma.c +@@ -0,0 +1,674 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2011 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define _MDRV_SCLDMA_C ++ ++//#include ++//#include ++//#include ++ ++//#include "mdrv_types.h" ++//#include "mdrv_scldma_io_i3_st.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_scldma.h" ++#include "drvscldma_st.h" ++#include "drvscldma.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define BUFFER_NUMBER_TO_HWIDX_OFFSET 1 ++#define _ISQueueNeedCopyToUser(enUsedType) (enUsedType==EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_PEEKQUEUE \ ++ || enUsedType==EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_DEQUEUE) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void _MDrv_SCLDMA_BufferQueueHandlerByUsedType ++(EN_MDRV_SCLDMA_USED_BUFFER_QUEUE_TYPE enUsedType,ST_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg) ++{ ++ switch(enUsedType) ++ { ++ case EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_PEEKQUEUE: ++ Drv_SCLDMA_PeekBufferQueue(pstCfg); ++ break; ++ case EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_DEQUEUE: ++ Drv_SCLDMA_BufferDeQueue(pstCfg); ++ break; ++ case EN_MDRV_SCLDMA_BUFFER_QUEUE_TYPE_ENQUEUE: ++ Drv_SCLDMA_EnableBufferAccess(pstCfg); ++ break; ++ default : ++ SCL_ERR( "[SCLDMA]%s NO this Queue Handler Type\n", __FUNCTION__); ++ break; ++ } ++} ++ ++EN_SCLDMA_RW_MODE_TYPE _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer ++(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,EN_SCLDMA_ID_TYPE *enID) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode = E_SCLDMA_RW_NUM; ++ switch(enSCLDMA_ID) ++ { ++ case E_MDRV_SCLDMA_ID_3: ++ *enID = E_SCLDMA_ID_3_R; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_R : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ case E_MDRV_SCLDMA_ID_PNL: ++ *enID = E_SCLDMA_ID_PNL_R; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_DBG_R : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ default: ++ case E_MDRV_SCLDMA_ID_1: ++ case E_MDRV_SCLDMA_ID_2: ++ SCL_ERR( "[SCLDMA]%s %d::Not support In TRIGGER\n",__FUNCTION__, __LINE__); ++ break; ++ } ++ return enRWMode; ++} ++EN_SCLDMA_RW_MODE_TYPE _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer ++(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,EN_SCLDMA_ID_TYPE *enID) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode = E_SCLDMA_RW_NUM; ++ switch(enSCLDMA_ID) ++ { ++ case E_MDRV_SCLDMA_ID_1: ++ *enID = E_SCLDMA_ID_1_W; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_W : ++ enMemType == E_MDRV_SCLDMA_MEM_SNP ? E_SCLDMA_SNP_W : ++ enMemType == E_MDRV_SCLDMA_MEM_IMI ? E_SCLDMA_IMI_W : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ case E_MDRV_SCLDMA_ID_2: ++ *enID = E_SCLDMA_ID_2_W; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_W : ++ enMemType == E_MDRV_SCLDMA_MEM_FRM2 ? E_SCLDMA_FRM2_W : ++ enMemType == E_MDRV_SCLDMA_MEM_IMI ? E_SCLDMA_IMI_W : ++ E_SCLDMA_RW_NUM; ++ ++ break; ++ ++ case E_MDRV_SCLDMA_ID_3: ++ *enID = E_SCLDMA_ID_3_W; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_FRM_W : ++ E_SCLDMA_RW_NUM; ++ break; ++ ++ case E_MDRV_SCLDMA_ID_PNL: ++ *enID = E_SCLDMA_ID_PNL_R; ++ enRWMode = enMemType == E_MDRV_SCLDMA_MEM_FRM ? E_SCLDMA_DBG_R: ++ E_SCLDMA_RW_NUM; ++ break; ++ default: ++ SCL_ERR( "[SCLDMA]%s %d::Not support In SCLDMA\n",__FUNCTION__, __LINE__); ++ enRWMode = E_SCLDMA_RW_NUM; ++ break; ++ } ++ return enRWMode; ++} ++EN_SCLDMA_RW_MODE_TYPE _MDrv_SCLDMA_SwitchIDForDriverlayer ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,EN_SCLDMA_ID_TYPE *enID,unsigned char bReadDMAMode) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ if(bReadDMAMode) ++ { ++ enRWMode = _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer(enSCLDMA_ID,enMemType,enID); ++ } ++ else ++ { ++ enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,enMemType,enID); ++ } ++ return enRWMode; ++} ++void _MDrv_SCLDMA_FillDMAInfoStruct(ST_SCLDMA_ATTR_TYPE *stDrvDMACfg,ST_MDRV_SCLDMA_ATTR_TYPE *stSendToIOCfg) ++{ ++ int u32BufferIdx; ++ stSendToIOCfg->u16DMAcount = stDrvDMACfg->u16DMAcount; ++ stSendToIOCfg->u32Trigcount = stDrvDMACfg->u32Trigcount; ++ stSendToIOCfg->u16DMAH = stDrvDMACfg->u16DMAH; ++ stSendToIOCfg->u16DMAV = stDrvDMACfg->u16DMAV; ++ stSendToIOCfg->enBufMDType = (EN_MDRV_SCLDMA_BUFFER_MODE_TYPE)stDrvDMACfg->enBuffMode; ++ stSendToIOCfg->enColorType = (EN_MDRV_SCLDMA_COLOR_TYPE)stDrvDMACfg->enColor; ++ stSendToIOCfg->u16BufNum = stDrvDMACfg->u8MaxIdx+1; ++ stSendToIOCfg->bDMAEn = stDrvDMACfg->bDMAEn; ++ for(u32BufferIdx=0;u32BufferIdxu16BufNum;u32BufferIdx++) ++ { ++ stSendToIOCfg->u32Base_Y[u32BufferIdx] = stDrvDMACfg->u32Base_Y[u32BufferIdx]; ++ stSendToIOCfg->u32Base_C[u32BufferIdx] = stDrvDMACfg->u32Base_C[u32BufferIdx]; ++ stSendToIOCfg->u32Base_V[u32BufferIdx] = stDrvDMACfg->u32Base_V[u32BufferIdx]; ++ } ++ stSendToIOCfg->bDMAFlag = stDrvDMACfg->bDMAFlag; ++ stSendToIOCfg->bDMAReadIdx = stDrvDMACfg->bDMAReadIdx; ++ stSendToIOCfg->bDMAWriteIdx = stDrvDMACfg->bDMAWriteIdx; ++ stSendToIOCfg->bSendPoll = stDrvDMACfg->bSendPoll; ++ stSendToIOCfg->u32FrameDoneTime = stDrvDMACfg->u32FrameDoneTime; ++ stSendToIOCfg->u32SendTime = stDrvDMACfg->u32SendTime; ++ stSendToIOCfg->u8Count= stDrvDMACfg->u8Count; ++ stSendToIOCfg->u8ResetCount= stDrvDMACfg->u8ResetCount; ++ stSendToIOCfg->u8DMAErrCount= stDrvDMACfg->u8DMAErrCount; ++} ++ ++void _MDrv_SCLDMA_FillActiveBufferStruct ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg, ++ EN_SCLDMA_ID_TYPE *enID,unsigned char bReadDMAMode,ST_SCLDMA_ACTIVE_BUFFER_CONFIG *stActiveCfg) ++{ ++ stActiveCfg->u8ActiveBuffer = pstCfg->u8ActiveBuffer; ++ stActiveCfg->enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,pstCfg->enMemType,enID,bReadDMAMode); ++ stActiveCfg->stOnOff.bEn = pstCfg->stOnOff.bEn; ++ stActiveCfg->stOnOff.enRWMode =stActiveCfg->enRWMode; ++ stActiveCfg->stOnOff.stclk=(ST_SCLDMA_CLK_CONFIG *)(pstCfg->stOnOff.stclk); ++} ++ ++unsigned char _MDrv_SCLDMA_GetDMABufferActiveIdx ++ (EN_SCLDMA_ID_TYPE enID,ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg,ST_SCLDMA_ACTIVE_BUFFER_CONFIG *stActiveCfg) ++{ ++ if(DoubleBufferStatus) ++ { ++ if(Drv_SCLDMA_GetDMABufferDoneIdx(enID, stActiveCfg)) ++ { ++ pstCfg->u8ActiveBuffer = stActiveCfg->u8ActiveBuffer; ++ pstCfg->u8ISPcount = stActiveCfg->u8ISPcount; ++ pstCfg->u64FRMDoneTime = stActiveCfg->u64FRMDoneTime; ++ return TRUE; ++ } ++ else ++ { ++ pstCfg->u8ActiveBuffer = 0xFF; ++ pstCfg->u8ISPcount = 0; ++ pstCfg->u64FRMDoneTime = 0; ++ return FALSE; ++ } ++ } ++ else ++ { ++ if(Drv_SCLDMA_GetDMABufferDoneIdxWithoutDoublebuffer(enID, stActiveCfg)) ++ { ++ pstCfg->u8ActiveBuffer = stActiveCfg->u8ActiveBuffer; ++ pstCfg->u8ISPcount = stActiveCfg->u8ISPcount; ++ pstCfg->u64FRMDoneTime = stActiveCfg->u64FRMDoneTime; ++ return TRUE; ++ } ++ else ++ { ++ pstCfg->u8ActiveBuffer = 0xFF; ++ pstCfg->u8ISPcount = 0; ++ pstCfg->u64FRMDoneTime = 0; ++ return FALSE; ++ } ++ } ++} ++void _MDrv_SCLDMA_FillRWCfgStruct ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,ST_MDRV_SCLDMA_BUFFER_CONFIG *pCfg, ++ EN_SCLDMA_ID_TYPE *enID,unsigned char bReadDMAMode,ST_SCLDMA_RW_CONFIG *stSCLDMACfg) ++{ ++ unsigned short u16BufferIdx; ++ MsOS_Memset(stSCLDMACfg, 0, sizeof(ST_SCLDMA_RW_CONFIG)); ++ stSCLDMACfg->enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,pCfg->enMemType,enID,bReadDMAMode); ++ stSCLDMACfg->u16Height = pCfg->u16Height; ++ stSCLDMACfg->u16Width = pCfg->u16Width; ++ stSCLDMACfg->u8MaxIdx = pCfg->u16BufNum -BUFFER_NUMBER_TO_HWIDX_OFFSET; ++ stSCLDMACfg->u8Flag = pCfg->u8Flag; ++ stSCLDMACfg->enBuffMode= (pCfg->enBufMDType == E_MDRV_SCLDMA_BUFFER_MD_RING) ? E_SCLDMA_BUF_MD_RING : ++ (pCfg->enBufMDType == E_MDRV_SCLDMA_BUFFER_MD_SWRING) ? E_SCLDMA_BUF_MD_SWRING : ++ E_SCLDMA_BUF_MD_SINGLE; ++ ++ for(u16BufferIdx=0; u16BufferIdxu16BufNum; u16BufferIdx++) ++ { ++ stSCLDMACfg->u32Base_Y[u16BufferIdx] = _Phys2Miu(pCfg->u32Base_Y[u16BufferIdx]); ++ stSCLDMACfg->u32Base_C[u16BufferIdx] = _Phys2Miu(pCfg->u32Base_C[u16BufferIdx]); ++ stSCLDMACfg->u32Base_V[u16BufferIdx] = _Phys2Miu(pCfg->u32Base_V[u16BufferIdx]); ++ } ++ ++ stSCLDMACfg->enColor = pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YUV422 ? E_SCLDMA_COLOR_YUV422 : ++ pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YUV420 ? E_SCLDMA_COLOR_YUV420 : ++ pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YCSep422 ? E_SCLDMA_COLOR_YCSep422 : ++ pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YUVSep422 ? E_SCLDMA_COLOR_YUVSep422 : ++ pCfg->enColorType == E_MDRV_SCLDMA_COLOR_YUVSep420 ? E_SCLDMA_COLOR_YUVSep420 : ++ E_SCLDMA_COLOR_NUM; ++} ++void MDrv_SCLDMA_SetPollWait ++ (void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ MsOS_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++} ++unsigned char MDrv_SCLDMA_Suspend(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ ST_SCLDMA_SUSPEND_RESUME_CONFIG stSCLDMASuspendResumeCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet = TRUE; ++ ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_PNL ? E_SCLDMA_ID_PNL_R : ++ E_SCLDMA_ID_MAX; ++ MsOS_Memset(&stSCLDMASuspendResumeCfg, 0, sizeof(ST_SCLDMA_SUSPEND_RESUME_CONFIG)); ++ ++ ++ if(Drv_SCLDMA_Suspend(enID, &stSCLDMASuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA]%s %d::Suspend Fail\n",__FUNCTION__, __LINE__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_Resume(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ ST_SCLDMA_SUSPEND_RESUME_CONFIG stSCLDMASuspendResumeCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet = TRUE;; ++ ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_PNL ? E_SCLDMA_ID_PNL_R : ++ E_SCLDMA_ID_MAX; ++ ++ MsOS_Memset(&stSCLDMASuspendResumeCfg, 0, sizeof(ST_SCLDMA_SUSPEND_RESUME_CONFIG)); ++ ++ if(Drv_SCLDMA_Resume(enID, &stSCLDMASuspendResumeCfg)) ++ { ++ bRet = TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[SCLDMA]%s %d::Resume Fail\n",__FUNCTION__, __LINE__); ++ bRet = FALSE; ++ } ++ ++ return bRet; ++} ++unsigned char MDrv_SCLDMA_Exit(unsigned char bCloseISR) ++{ ++ Drv_SCLDMA_Exit(bCloseISR); ++ return 1; ++} ++ ++unsigned char MDrv_SCLDMA_Init(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_INIT_CONFIG *pCfg) ++{ ++ unsigned char bRet = FALSE; ++ ST_SCLDMA_INIT_CONFIG stDMAInitCfg; ++ MsOS_Memset(&stDMAInitCfg,0,sizeof(ST_SCLDMA_INIT_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,0,0)), "[SCLDMA]%s\n", __FUNCTION__); ++ ++ stDMAInitCfg.u32RIUBase = pCfg->u32Riubase; ++ if(Drv_SCLDMA_Init(&stDMAInitCfg) == FALSE) ++ { ++ SCL_ERR( "[SCLDMA]%s %d::Init Fail\n",__FUNCTION__, __LINE__); ++ bRet = FALSE; ++ } ++ else ++ { ++ bRet = TRUE; ++ } ++ ++ return bRet; ++} ++void MDrv_SCLDMA_Sys_Init(unsigned char bEn) ++{ ++ Drv_SCLDMA_Sys_Init(bEn); ++} ++unsigned char MDrv_SCLDMA_GetDoubleBufferStatus(void) ++{ ++ return DoubleBufferStatus; ++} ++void MDrv_SCLDMA_SetDoubleBufferConfig(unsigned char bEn) ++{ ++ gbDBStatus = bEn; ++} ++void MDrv_SCLDMA_Release(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,ST_MDRV_SCLDMA_CLK_CONFIG *stclkcfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_CLK_CONFIG *stclk; ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_PNL ? E_SCLDMA_ID_PNL_R : ++ E_SCLDMA_ID_MAX; ++ ++ stclk = (ST_SCLDMA_CLK_CONFIG *)(stclkcfg); ++ Drv_SCLDMA_Release(enID,stclk); ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAReadClientConfig ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_RW_CONFIG stSCLDMACfg; ++ unsigned char bRet; ++ MsOS_Memset(&stSCLDMACfg,0,sizeof(ST_SCLDMA_RW_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,0)), "[SCLDMA]%s\n", __FUNCTION__); ++ ++ _MDrv_SCLDMA_FillRWCfgStruct(enSCLDMA_ID,pCfg,&enID,1,&stSCLDMACfg); ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientConfig(enID, &stSCLDMACfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAReadClientTrigger ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_TRIGGER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_ONOFF_CONFIG stOnOffCfg; ++ unsigned char bRet; ++ MsOS_Memset(&stOnOffCfg,0,sizeof(ST_SCLDMA_ONOFF_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ stOnOffCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer(enSCLDMA_ID,pCfg->enMemType,&enID); ++ stOnOffCfg.bEn = pCfg->bEn; ++ stOnOffCfg.stclk = (ST_SCLDMA_CLK_CONFIG *)(pCfg->stclk); ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientOnOff(enID ,&stOnOffCfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAWriteClientConfig ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_RW_CONFIG stSCLDMACfg; ++ unsigned char bRet; ++ MsOS_Memset(&stSCLDMACfg,0,sizeof(ST_SCLDMA_RW_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,0)), ++ "[SCLDMA]%s ID:%d\n", __FUNCTION__,enSCLDMA_ID); ++ ++ _MDrv_SCLDMA_FillRWCfgStruct(enSCLDMA_ID,pCfg,&enID,0,&stSCLDMACfg); ++ ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientConfig(enID, &stSCLDMACfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_SetDMAWriteClientTrigger ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_TRIGGER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_ONOFF_CONFIG stOnOffCfg; ++ unsigned char bRet; ++ MsOS_Memset(&stOnOffCfg,0,sizeof(ST_SCLDMA_ONOFF_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ ++ stOnOffCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,pCfg->enMemType,&enID); ++ stOnOffCfg.bEn = pCfg->bEn; ++ stOnOffCfg.stclk = (ST_SCLDMA_CLK_CONFIG *)(pCfg->stclk); ++ ++ bRet = (unsigned char)Drv_SCLDMA_SetDMAClientOnOff(enID ,&stOnOffCfg); ++ ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_GetInBufferDoneEvent ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, EN_MDRV_SCLDMA_MEM_TYPE enMemType, ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG *pCfg) ++{ ++ unsigned char bRet; ++ ST_SCLDMA_DONE_CONFIG stDonCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ MsOS_Memset(&stDonCfg,0,sizeof(ST_SCLDMA_DONE_CONFIG)); ++ stDonCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoReadModeForDriverlayer(enSCLDMA_ID,enMemType,&enID); ++ bRet = (unsigned char)Drv_SCLDMA_GetDMADoneEvent(enID, &stDonCfg); ++ pCfg->bDone = (unsigned char)stDonCfg.bDone; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,enMemType,1)), ++ "[SCLDMA]%s: ID:%d, bRet: %d, BufferDone:%d\n", __FUNCTION__, enID, bRet, stDonCfg.bDone); ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_GetOutBufferDoneEvent ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, EN_MDRV_SCLDMA_MEM_TYPE enMemType, ST_MDRV_SCLDMA_BUFFER_DONE_CONFIG *pCfg) ++{ ++ unsigned char bRet; ++ ST_SCLDMA_DONE_CONFIG stDonCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ MsOS_Memset(&stDonCfg,0,sizeof(ST_SCLDMA_DONE_CONFIG)); ++ stDonCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,enMemType,&enID); ++ bRet = (unsigned char)Drv_SCLDMA_GetDMADoneEvent(enID, &stDonCfg); ++ pCfg->bDone = (unsigned char)stDonCfg.bDone; ++ ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,enMemType,1)), "[SCLDMA]%s: ID:%d, bRet: %d, BufferDone:%d\n", __FUNCTION__, enID, bRet, stDonCfg.bDone); ++ return bRet; ++} ++ ++unsigned char MDrv_SCLDMA_GetDMAReadBufferActiveIdx ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg) ++{ ++ ST_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet; ++ MsOS_Memset(&stActiveCfg,0,sizeof(ST_SCLDMA_ACTIVE_BUFFER_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pstCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ _MDrv_SCLDMA_FillActiveBufferStruct(enSCLDMA_ID,pstCfg,&enID,1,&stActiveCfg); ++ bRet = _MDrv_SCLDMA_GetDMABufferActiveIdx(enID, pstCfg, &stActiveCfg); ++ return bRet; ++ ++} ++unsigned char MDrv_SCLDMA_BufferQueueHandle ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg) ++{ ++ unsigned char bRet =0; ++ EN_SCLDMA_ID_TYPE enID; ++ ST_SCLDMA_BUFFER_QUEUE_CONFIG stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(ST_SCLDMA_BUFFER_QUEUE_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID,pstCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ stCfg.enRWMode = _MDrv_SCLDMA_SwitchIDtoWriteModeForDriverlayer(enSCLDMA_ID,pstCfg->enMemType,&enID); ++ stCfg.enID = enID; ++ stCfg.u8AccessId = pstCfg->u8EnqueueIdx; ++ _MDrv_SCLDMA_BufferQueueHandlerByUsedType(pstCfg->enUsedType,&stCfg); ++ if(_ISQueueNeedCopyToUser(pstCfg->enUsedType)) ++ { ++ if(stCfg.pstRead != NULL) ++ { ++ MsOS_Memcpy(&pstCfg->stRead,stCfg.pstRead,MDRV_SCLDMA_BUFFER_QUEUE_OFFSET); ++ pstCfg->u8InQueueCount = stCfg.u8InQueueCount; ++ pstCfg->u8EnqueueIdx = stCfg.u8AccessId; ++ bRet = 1; ++ } ++ } ++ return bRet; ++} ++unsigned char MDrv_SCLDMA_GetDMAWriteBufferAcitveIdx ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID, ST_MDRV_SCLDMA_ACTIVE_BUFFER_CONFIG *pstCfg) ++{ ++ ST_SCLDMA_ACTIVE_BUFFER_CONFIG stActiveCfg; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bRet; ++ MsOS_Memset(&stActiveCfg,0,sizeof(ST_SCLDMA_ACTIVE_BUFFER_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_SCLDMA()&(Get_DBGMG_SCLDMA(enSCLDMA_ID, pstCfg->enMemType,1)), "[SCLDMA]%s\n", __FUNCTION__); ++ _MDrv_SCLDMA_FillActiveBufferStruct(enSCLDMA_ID, pstCfg, &enID,0,&stActiveCfg); ++ bRet = _MDrv_SCLDMA_GetDMABufferActiveIdx(enID, pstCfg, &stActiveCfg); ++ return bRet; ++} ++void MDrv_SCLDMA_SetForceCloseDMAClient ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType, ++ unsigned char bReadDMAMode,unsigned char bEnForceClose) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,enMemType,&enID,bReadDMAMode); ++ Drv_SCLDMA_SetForceCloseDMA(enID,enRWMode,bEnForceClose); ++} ++void MDrv_SCLDMA_ResetTrigCountByClient ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,unsigned char bReadDMAMode) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,enMemType,&enID,bReadDMAMode); ++ Drv_SCLDMA_ResetTrigCountByClient(enID,enRWMode); ++} ++ ++void MDrv_SCLDMA_ResetTrigCountAllClient(void) ++{ ++ Drv_SCLDMA_ResetTrigCountByClient(E_SCLDMA_ID_MAX,E_SCLDMA_RW_NUM); ++} ++ ++void MDrv_SCLDMA_ClkClose(ST_MDRV_SCLDMA_CLK_CONFIG* stclk) ++{ ++ Drv_SCLDMA_ClkClose((ST_SCLDMA_CLK_CONFIG *)stclk); ++} ++void * MDrv_SCLDMA_GetWaitQueueHead(EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ ++ enID = enSCLDMA_ID == E_MDRV_SCLDMA_ID_1 ? E_SCLDMA_ID_1_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_2 ? E_SCLDMA_ID_2_W : ++ enSCLDMA_ID == E_MDRV_SCLDMA_ID_3 ? E_SCLDMA_ID_3_W : ++ E_SCLDMA_ID_MAX; ++ if(enID == E_SCLDMA_ID_MAX) ++ { ++ return 0; ++ } ++ else ++ { ++ return Drv_SCLDMA_GetWaitQueueHead(enID); ++ } ++} ++ ++void MDrv_SCLDMA_GetDMAInformationByClient ++ (EN_MDRV_SCLDMA_ID_TYPE enSCLDMA_ID,EN_MDRV_SCLDMA_MEM_TYPE enMemType,unsigned char bReadDMAMode,ST_MDRV_SCLDMA_ATTR_TYPE *stSendToIOCfg) ++{ ++ EN_SCLDMA_ID_TYPE enID; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ ST_SCLDMA_ATTR_TYPE stDrvDMACfg; ++ MsOS_Memset(&stDrvDMACfg,0,sizeof(ST_SCLDMA_ATTR_TYPE)); ++ enRWMode = _MDrv_SCLDMA_SwitchIDForDriverlayer(enSCLDMA_ID,enMemType,&enID,bReadDMAMode); ++ Drv_SCLDMA_GetDMAInformationByClient(enID, enRWMode,&stDrvDMACfg); ++ _MDrv_SCLDMA_FillDMAInfoStruct(&stDrvDMACfg,stSendToIOCfg); ++} ++unsigned char _MDrv_IsClosedPacking(ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr) ++{ ++ unsigned char bEn = 0; ++ if(stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUV422 ) ++ { ++ bEn = 1; ++ } ++ else if(stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YCSep422 || ++ stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUV420) ++ { ++ bEn = ((stScldmaAttr.u32Base_Y[0]+(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV))==stScldmaAttr.u32Base_C[0]) ? 1 :0 ; ++ } ++ else if(stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUVSep422 || ++ stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUVSep420) ++ { ++ bEn = ((stScldmaAttr.u32Base_Y[0]+(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV))==stScldmaAttr.u32Base_C[0]) ? 1 :0 ; ++ if(stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUVSep422 && bEn) ++ { ++ bEn = ((stScldmaAttr.u32Base_C[0]+(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV/2))==stScldmaAttr.u32Base_V[0]) ? 1 :0 ; ++ } ++ else if(stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUVSep420 && bEn) ++ { ++ bEn = ((stScldmaAttr.u32Base_C[0]+(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV/4))==stScldmaAttr.u32Base_V[0]) ? 1 :0 ; ++ } ++ } ++ return bEn; ++} ++ssize_t MDrv_SCLDMA_ProcShow ++ (char *buf, EN_MDRV_SCLDMA_ID_TYPE enID, EN_MDRV_SCLDMA_MEM_TYPE enMem, unsigned char bRread) ++{ ++ ST_MDRV_SCLDMA_ATTR_TYPE stScldmaAttr; ++ //out =0,in=1 ++ char *p8StrBuf = buf; ++ char *p8StrEnd = buf + PAGE_SIZE; ++ int u32idx; ++ unsigned u8bCP; ++ //out =0,in=1 ++ MsOS_Memset(&stScldmaAttr,0,sizeof(ST_MDRV_SCLDMA_ATTR_TYPE)); ++ MDrv_SCLDMA_GetDMAInformationByClient(enID, enMem,bRread,&stScldmaAttr); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "========================SCL PROC FRAMEWORK======================\n"); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "------------------------ %s %s CLIENT----------------------\n", ++ PARSING_SCLDMA_IOID(enID),PARSING_SCLDMA_IOMEM(enMem)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Enable: %hhd\n",stScldmaAttr.bDMAEn); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "output width: %hd, output height: %hd\n",stScldmaAttr.u16DMAH,stScldmaAttr.u16DMAV); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA color format: %s\n",PARSING_SCLDMA_IOCOLOR(stScldmaAttr.enColorType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA trigger mode: %s\n",PARSING_SCLDMA_IOBUFMD(stScldmaAttr.enBufMDType)); ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer Num: %hd\n",stScldmaAttr.u16BufNum); ++ if(stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUV422 || ++ stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YUVSep422|| ++ stScldmaAttr.enColorType == E_MDRV_SCLDMA_COLOR_YCSep422) ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*2)); ++ } ++ else ++ { ++ p8StrBuf += scnprintf(p8StrBuf, p8StrEnd - p8StrBuf ++ , "DMA Buffer length(presume): %d\n",(int)(stScldmaAttr.u16DMAH*stScldmaAttr.u16DMAV*3/2)); ++ } ++ for(u32idx=0 ;u32idx ++//#include ++//#include ++//#include ++//#include ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvvip.h" ++#include "drvCMDQ.h" ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++#include "ms_platform.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_vip_st.h" ++#include "mdrv_vip.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "hwreg.h" ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define MDRV_CMDQ_MUTEX_LOCK(enIP,bEn) (bEn ? Drv_CMDQ_GetModuleMutex(enIP,1) : 0) ++#define MDRV_CMDQ_MUTEX_UNLOCK(enIP,bEn) (bEn ? Drv_CMDQ_GetModuleMutex(enIP,0) : 0) ++#define MDRV_VIP_MUTEX_LOCK() MsOS_ObtainMutex(_MVIP_Mutex,MSOS_WAIT_FOREVER) ++#define MDRV_VIP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_MVIP_Mutex) ++#define _IsFrameBufferAllocatedReady() (gu8FrameBufferReadyNum &0x3) ++#define _IsCIIRBufferAllocatedReady() (gu8FrameBufferReadyNum &0xC) ++#define _IsCMDQNeedToReturnOrigin() (gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_RETURN_ORI) ++#define _IsCMDQAlreadySetting() (gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_ALREADY_SETINNG) ++#define _IsSetCMDQ() (gbVIPCheckCMDQorPQ >= EN_VIP_CMDQ_CHECK_ALREADY_SETINNG) ++#define _IsAutoSetting() (gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_AUTOSETTING\ ++ || gbVIPCheckCMDQorPQ == EN_VIP_CMDQ_CHECK_PQ) ++#define _Set_SuspendResetFlag(u32flag) (gstSupCfg.bresetflag |= u32flag) ++#define _IsSuspendResetFlag(enType) ((gstSupCfg.bresetflag &enType)>0) ++#define _Set_SuspendAIPResetFlag(u32flag) (gstSupCfg.bAIPreflag |= (0x1 << u32flag)) ++#define _IsSuspendAIPResetFlag(enType) (gstSupCfg.bAIPreflag &(0x1 << enType)) ++#define _Set_AIPBypassFlag(u32flag) (gu32AIPOpenBypass |= (0x1 << u32flag)) ++#define _Is_AIPBypassFlag(u32flag) (gu32AIPOpenBypass &(0x1 << u32flag)) ++#define _IsCheckPQorCMDQmode() (gbVIPCheckCMDQorPQ) ++#define _IsNotToCheckPQorCMDQmode() (!gbVIPCheckCMDQorPQ) ++#define _IsOpenVIPBypass() (gu32OpenBypass) ++#define _IsNotOpenVIPBypass(enType) (!(gu32OpenBypass & enType)) ++#define AIPOffset PQ_IP_YEE_Main ++#define _GetAIPOffset(u32Type) (u32Type +AIPOffset) ++#define _IsVIPCMDQSetFlag(enType) (gbVIPCMDQSet &enType) ++#define _IsAIPCMDQSetFlag(enType) (gbAIPCMDQSet &(0x1 << enType)) ++#define _Set_VIPCMDQSetFlag(u32flag) (gbVIPCMDQSet |= u32flag) ++#define _Set_AIPCMDQSetFlag(u32flag) (gbAIPCMDQSet |= (0x1 << u32flag)) ++#define _ReSet_VIPCMDQSetFlag(u32flag) (gbVIPCMDQSet &= ~(u32flag)) ++#define _ReSet_AIPCMDQSetFlag(u32flag) (gbAIPCMDQSet &= ~(0x1 << (u32flag))) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// gstSupCfg ++/// save data for suspend/resume and test Qmap. ++//////////////// ++ST_MDRV_VIP_SUSPEND_CONFIG gstSupCfg; ++///////////////// ++/// gbVIPCheckCMDQorPQ ++/// if True ,is check PQ mode. ++//////////////// ++unsigned char gbVIPCheckCMDQorPQ = 0; ++unsigned long gu32OpenBypass = 0; ++unsigned long gu32AIPOpenBypass = 0; ++unsigned long gbVIPCMDQSet; ++unsigned long gbAIPCMDQSet; ++unsigned char gbAlreadyOpenGamma = 0; ++VIPDAZAEvent genVipDazaEvent; ++MS_S32 _MVIP_Mutex = -1; ++MS_S32 _MVIP_TASK = -1; ++MS_BOOL b_MVIP_TASKEn = 1; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Function ++//------------------------------------------------------------------------------------------------- ++void _MDrv_VIP_SetDAZATaskWork(VIPDAZAEvent enEvent) ++{ ++ genVipDazaEvent |= enEvent; ++ MsOS_SetTaskWork(_MVIP_TASK); ++ //SCL_DBGERR("[VIP]%s :task:%hhx\n",__FUNCTION__,bret); ++} ++ ++unsigned short _MDrv_VIP_ChioceStructSizeFromPQType(MS_U8 u8PQIPIdx) ++{ ++ MS_U16 u16DataSize; ++ switch(u8PQIPIdx) ++ { ++ case PQ_IP_LDC_Main: ++ u16DataSize = PQ_IP_LDC_Size; ++ break; ++ case PQ_IP_LDC_422_444_422_Main: ++ u16DataSize = PQ_IP_LDC_422_444_422_Size; ++ break; ++ case PQ_IP_NLM_Main: ++ u16DataSize = PQ_IP_NLM_Size; ++ break; ++ case PQ_IP_422to444_Main: ++ u16DataSize = PQ_IP_422to444_Size; ++ break; ++ case PQ_IP_VIP_Main: ++ u16DataSize = PQ_IP_VIP_Size; ++ break; ++ case PQ_IP_VIP_LineBuffer_Main: ++ u16DataSize = PQ_IP_VIP_LineBuffer_Size; ++ break; ++ case PQ_IP_VIP_HLPF_Main: ++ u16DataSize = PQ_IP_VIP_HLPF_Size; ++ break; ++ case PQ_IP_VIP_HLPF_dither_Main: ++ u16DataSize = PQ_IP_VIP_HLPF_dither_Size; ++ break; ++ case PQ_IP_VIP_VLPF_coef1_Main: ++ case PQ_IP_VIP_VLPF_coef2_Main: ++ u16DataSize = PQ_IP_VIP_VLPF_coef1_Size; ++ break; ++ case PQ_IP_VIP_VLPF_dither_Main: ++ u16DataSize = PQ_IP_VIP_VLPF_dither_Size; ++ break; ++ case PQ_IP_VIP_Peaking_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_Size; ++ break; ++ case PQ_IP_VIP_Peaking_band_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_band_Size; ++ break; ++ case PQ_IP_VIP_Peaking_adptive_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_adptive_Size; ++ break; ++ case PQ_IP_VIP_Peaking_Pcoring_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_Pcoring_Size; ++ break; ++ case PQ_IP_VIP_Peaking_Pcoring_ad_Y_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_Pcoring_ad_Y_Size; ++ break; ++ case PQ_IP_VIP_Peaking_gain_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_gain_Size; ++ break; ++ case PQ_IP_VIP_Peaking_gain_ad_Y_Main: ++ u16DataSize = PQ_IP_VIP_Peaking_gain_ad_Y_Size; ++ break; ++ case PQ_IP_VIP_YC_gain_offset_Main: ++ u16DataSize = PQ_IP_VIP_YC_gain_offset_Size; ++ break; ++ case PQ_IP_VIP_LCE_Main: ++ u16DataSize = PQ_IP_VIP_LCE_Size; ++ break; ++ case PQ_IP_VIP_LCE_dither_Main: ++ u16DataSize = PQ_IP_VIP_LCE_dither_Size; ++ break; ++ case PQ_IP_VIP_LCE_setting_Main: ++ u16DataSize = PQ_IP_VIP_LCE_setting_Size; ++ break; ++ case PQ_IP_VIP_LCE_curve_Main: ++ u16DataSize = PQ_IP_VIP_LCE_curve_Size; ++ break; ++ case PQ_IP_VIP_DLC_Main: ++ u16DataSize = PQ_IP_VIP_DLC_Size; ++ break; ++ case PQ_IP_VIP_DLC_dither_Main: ++ u16DataSize = PQ_IP_VIP_DLC_dither_Size; ++ break; ++ case PQ_IP_VIP_DLC_His_range_Main: ++ u16DataSize = PQ_IP_VIP_DLC_His_range_Size; ++ break; ++ case PQ_IP_VIP_DLC_His_rangeH_Main: ++ u16DataSize = PQ_IP_VIP_DLC_His_rangeH_Size; ++ break; ++ case PQ_IP_VIP_DLC_His_rangeV_Main: ++ u16DataSize = PQ_IP_VIP_DLC_His_rangeV_Size; ++ break; ++ case PQ_IP_VIP_DLC_PC_Main: ++ u16DataSize = PQ_IP_VIP_DLC_PC_Size; ++ break; ++ case PQ_IP_VIP_UVC_Main: ++ u16DataSize = PQ_IP_VIP_UVC_Size; ++ break; ++ case PQ_IP_VIP_FCC_full_range_Main: ++ u16DataSize = PQ_IP_VIP_FCC_full_range_Size; ++ break; ++ case PQ_IP_VIP_FCC_T1_Main: ++ case PQ_IP_VIP_FCC_T2_Main: ++ case PQ_IP_VIP_FCC_T3_Main: ++ case PQ_IP_VIP_FCC_T4_Main: ++ case PQ_IP_VIP_FCC_T5_Main: ++ case PQ_IP_VIP_FCC_T6_Main: ++ case PQ_IP_VIP_FCC_T7_Main: ++ case PQ_IP_VIP_FCC_T8_Main: ++ u16DataSize = PQ_IP_VIP_FCC_T1_Size; ++ break; ++ case PQ_IP_VIP_FCC_T9_Main: ++ u16DataSize = PQ_IP_VIP_FCC_T9_Size; ++ break; ++ case PQ_IP_VIP_IHC_Main: ++ u16DataSize = PQ_IP_VIP_IHC_Size; ++ break; ++ case PQ_IP_VIP_IHC_Ymode_Main: ++ u16DataSize = PQ_IP_VIP_IHC_Ymode_Size; ++ break; ++ case PQ_IP_VIP_IHC_dither_Main: ++ u16DataSize = PQ_IP_VIP_IHC_dither_Size; ++ break; ++ case PQ_IP_VIP_IHC_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_IHC_SETTING_Size; ++ break; ++ case PQ_IP_VIP_ICC_Main: ++ u16DataSize = PQ_IP_VIP_ICC_Size; ++ break; ++ case PQ_IP_VIP_ICC_Ymode_Main: ++ u16DataSize = PQ_IP_VIP_ICC_Ymode_Size; ++ break; ++ case PQ_IP_VIP_ICC_dither_Main: ++ u16DataSize = PQ_IP_VIP_ICC_dither_Size; ++ break; ++ case PQ_IP_VIP_ICC_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_ICC_SETTING_Size; ++ break; ++ case PQ_IP_VIP_Ymode_Yvalue_ALL_Main: ++ u16DataSize = PQ_IP_VIP_Ymode_Yvalue_ALL_Size; ++ break; ++ case PQ_IP_VIP_Ymode_Yvalue_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_Ymode_Yvalue_SETTING_Size; ++ break; ++ case PQ_IP_VIP_IBC_Main: ++ u16DataSize = PQ_IP_VIP_IBC_Size; ++ break; ++ case PQ_IP_VIP_IBC_dither_Main: ++ u16DataSize = PQ_IP_VIP_IBC_dither_Size; ++ break; ++ case PQ_IP_VIP_IBC_SETTING_Main: ++ u16DataSize = PQ_IP_VIP_IBC_SETTING_Size; ++ break; ++ case PQ_IP_VIP_ACK_Main: ++ u16DataSize = PQ_IP_VIP_ACK_Size; ++ break; ++ case PQ_IP_VIP_YCbCr_Clip_Main: ++ u16DataSize = PQ_IP_VIP_YCbCr_Clip_Size; ++ break; ++ default: ++ u16DataSize = 0; ++ ++ break; ++ } ++ return u16DataSize; ++} ++void _MDrv_VIP_FillPQCfgByType ++ (MS_U8 u8PQIPIdx, MS_U8 *pData, MS_U16 u16DataSize,ST_MDRV_VIP_SETPQ_CONFIG *stSetPQCfg) ++{ ++ stSetPQCfg->enPQIPType = u8PQIPIdx; ++ stSetPQCfg->pPointToCfg = pData; ++ stSetPQCfg->u32StructSize = u16DataSize; ++} ++unsigned char MDrv_VIP_GetIsBlankingRegion(void) ++{ ++ return Drv_VIP_GetIsBlankingRegion(); ++} ++ ++void _MDrv_VIP_FillstFCfgBelongGlobal(EN_VIP_MDRV_CONFIG_TYPE enVIPtype,unsigned char bEn,unsigned char u8framecnt) ++{ ++ switch(enVIPtype) ++ { ++ case EN_VIP_MDRV_MCNR_CONFIG: ++ gstSupCfg.stmcnr.stFCfg.bEn = bEn ; ++ gstSupCfg.stmcnr.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_ACK_CONFIG: ++ gstSupCfg.stack.stFCfg.bEn = bEn ; ++ gstSupCfg.stack.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_IBC_CONFIG: ++ gstSupCfg.stibc.stFCfg.bEn = bEn ; ++ gstSupCfg.stibc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_IHCICC_CONFIG: ++ gstSupCfg.stihcicc.stFCfg.bEn = bEn ; ++ gstSupCfg.stihcicc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_ICC_CONFIG: ++ gstSupCfg.sticc.stFCfg.bEn = bEn ; ++ gstSupCfg.sticc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_IHC_CONFIG: ++ gstSupCfg.stihc.stFCfg.bEn = bEn ; ++ gstSupCfg.stihc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_FCC_CONFIG: ++ gstSupCfg.stfcc.stFCfg.bEn = bEn ; ++ gstSupCfg.stfcc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_MDRV_UVC_CONFIG: ++ gstSupCfg.stuvc.stFCfg.bEn = bEn ; ++ gstSupCfg.stuvc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_DLC_CONFIG: ++ gstSupCfg.stdlc.stFCfg.bEn = bEn ; ++ gstSupCfg.stdlc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_DLC_HISTOGRAM_CONFIG: ++ gstSupCfg.sthist.stFCfg.bEn = bEn ; ++ gstSupCfg.sthist.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_LCE_CONFIG: ++ gstSupCfg.stlce.stFCfg.bEn = bEn ; ++ gstSupCfg.stlce.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_PEAKING_CONFIG: ++ gstSupCfg.stpk.stFCfg.bEn = bEn ; ++ gstSupCfg.stpk.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_LDC_MD_CONFIG: ++ gstSupCfg.stldcmd.stFCfg.bEn = bEn ; ++ gstSupCfg.stldcmd.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_LDC_DMAP_CONFIG: ++ gstSupCfg.stldcdmap.stFCfg.bEn = bEn ; ++ gstSupCfg.stldcdmap.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_LDC_SRAM_CONFIG: ++ gstSupCfg.stldcsram.stFCfg.bEn = bEn ; ++ gstSupCfg.stldcsram.stFCfg.u8framecnt = u8framecnt; ++ break; ++ ++ case EN_VIP_MDRV_NLM_CONFIG: ++ gstSupCfg.stnlm.stFCfg.bEn = bEn ; ++ gstSupCfg.stnlm.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_MDRV_LDC_CONFIG: ++ gstSupCfg.stldc.stFCfg.bEn = bEn ; ++ gstSupCfg.stldc.stFCfg.u8framecnt = u8framecnt; ++ break; ++ case EN_VIP_MDRV_CONFIG: ++ gstSupCfg.stack.stFCfg.bEn = bEn ; ++ gstSupCfg.stack.stFCfg.u8framecnt = u8framecnt; ++ break; ++ default: ++ gstSupCfg.stvip.stFCfg.bEn = 0 ; ++ gstSupCfg.stvip.stFCfg.u8framecnt = 0; ++ break; ++ ++ } ++} ++void _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_CONFIG_TYPE enVIPtype,void *pCfg) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ MsOS_Memset(&stSetPQCfg,0,sizeof(ST_MDRV_VIP_SETPQ_CONFIG)); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,pCfg,&stSetPQCfg); ++ MsOS_Memcpy(stSetPQCfg.pGolbalStructAddr, stSetPQCfg.pPointToCfg,stSetPQCfg.u32StructSize); ++ _MDrv_VIP_FillstFCfgBelongGlobal(enVIPtype,0,0); ++ _Set_SuspendResetFlag(enVIPtype); ++ } ++} ++void _MDrv_VIP_ResetAlreadySetting(ST_MDRV_VIP_SETPQ_CONFIG *stSetPQCfg) ++{ ++ void * pvPQSetParameter; ++ pvPQSetParameter = MsOS_Memalloc(stSetPQCfg->u32StructSize, GFP_KERNEL); ++ if(!pvPQSetParameter) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init pvPQSetParameter Fail\n", __FUNCTION__, __LINE__); ++ return ; ++ } ++ MsOS_Memset(pvPQSetParameter, 0, stSetPQCfg->u32StructSize); ++ stSetPQCfg->pfForSet(pvPQSetParameter); ++ MsOS_MemFree(pvPQSetParameter); ++} ++void _MDrv_VIP_ModifyAIPAlreadySetting(EN_VIP_MDRV_AIP_TYPE enAIPtype, EN_VIP_RESET_TYPE enRe) ++{ ++ ST_MDRV_VIP_AIP_CONFIG staip; ++ unsigned char bSet; ++ unsigned long u32viraddr; ++ MsOS_Memset(&staip,0,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ bSet = (enRe == EN_VIP_RESET_ZERO) ? 0 : 0xFF; ++ staip = gstSupCfg.staip[enAIPtype]; ++ staip.u32Viraddr =(unsigned long)MsOS_VirMemalloc(MDrv_PQ_GetIPRegCount(_GetAIPOffset(enAIPtype))); ++ if(!staip.u32Viraddr) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init staip.u32Viraddr Fail\n", __FUNCTION__, __LINE__); ++ return ; ++ } ++ MsOS_Memset((void*)staip.u32Viraddr, bSet, MDrv_PQ_GetIPRegCount(_GetAIPOffset(enAIPtype))); ++ if(enRe == EN_VIP_RESET_ZERO) ++ { ++ MDrv_VIP_SetAIPConfig(&staip); ++ } ++ else if(enRe == EN_VIP_RESET_ALREADY) ++ { ++ if(gstSupCfg.staip[enAIPtype].u32Viraddr) ++ { ++ MDrv_VIP_SetAIPConfig(&gstSupCfg.staip[enAIPtype]); ++ } ++ } ++ else if (enRe == EN_VIP_FILL_GOLBAL_FULL) ++ { ++ u32viraddr = gstSupCfg.staip[enAIPtype].u32Viraddr; ++ gstSupCfg.staip[enAIPtype].u32Viraddr = staip.u32Viraddr; ++ gstSupCfg.staip[enAIPtype].u16AIPType = enAIPtype; ++ staip.u32Viraddr = u32viraddr; ++ } ++ MsOS_VirMemFree((void *)staip.u32Viraddr); ++} ++void _MDrv_VIP_FillAutoSetStruct(ST_MDRV_VIP_SETPQ_CONFIG *stSetPQCfg) ++{ ++ void * pvPQSetParameter; ++ pvPQSetParameter = MsOS_Memalloc(stSetPQCfg->u32StructSize, GFP_KERNEL); ++ if(!pvPQSetParameter) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init pvPQSetParameter Fail\n", __FUNCTION__, __LINE__); ++ return ; ++ } ++ MsOS_Memset(pvPQSetParameter, 0xFF, stSetPQCfg->u32StructSize); ++ MsOS_Memcpy(stSetPQCfg->pGolbalStructAddr, pvPQSetParameter, stSetPQCfg->u32StructSize); ++ MsOS_MemFree(pvPQSetParameter); ++} ++void _Mdrv_VIP_ModifyMCNRAlreadySetting(EN_VIP_RESET_TYPE enRe) ++{ ++ ST_MDRV_VIP_MCNR_CONFIG stmcnr; ++ unsigned char bSet; ++ unsigned long u32viraddr; ++ SCL_ERR("[MVIP]%s",__FUNCTION__); ++ MsOS_Memset(&stmcnr,0,sizeof(ST_MDRV_VIP_MCNR_CONFIG)); ++ bSet = (enRe == EN_VIP_RESET_ZERO) ? 0 : 0xFF; ++ stmcnr = gstSupCfg.stmcnr; ++ stmcnr.u32Viraddr = (unsigned long)MsOS_VirMemalloc(MDrv_PQ_GetIPRegCount(PQ_IP_MCNR_Main)); ++ if(!stmcnr.u32Viraddr) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init stmcnr.u32Viraddr Fail\n", __FUNCTION__, __LINE__); ++ return ; ++ } ++ stmcnr.bEnMCNR = (enRe == EN_VIP_RESET_ZERO) ? 0 : ++ (enRe == EN_VIP_FILL_GOLBAL_FULL) ? 1 : ++ gstSupCfg.stmcnr.bEnMCNR; ++ ++ stmcnr.bEnCIIR = (enRe == EN_VIP_RESET_ZERO) ? 0 : ++ (enRe == EN_VIP_FILL_GOLBAL_FULL) ? 1 : ++ gstSupCfg.stmcnr.bEnCIIR; ++ stmcnr.stFCfg.bEn = 0; ++ stmcnr.stFCfg.u8framecnt = 0; ++ MsOS_Memset((void*)stmcnr.u32Viraddr, bSet, MDrv_PQ_GetIPRegCount(PQ_IP_MCNR_Main)); ++ MDRV_VIP_MUTEX_LOCK(); ++ gu32OpenBypass |= EN_VIP_MDRV_MCNR_CONFIG; ++ MDRV_VIP_MUTEX_UNLOCK(); ++ if(enRe == EN_VIP_RESET_ZERO) ++ { ++ MDrv_VIP_SetMCNRConfig(&stmcnr); ++ } ++ else if(enRe == EN_VIP_RESET_ALREADY) ++ { ++ MDrv_VIP_SetMCNRConfig(&gstSupCfg.stmcnr); ++ } ++ else if (enRe == EN_VIP_FILL_GOLBAL_FULL) ++ { ++ u32viraddr = gstSupCfg.stmcnr.u32Viraddr; ++ gstSupCfg.stmcnr.u32Viraddr = stmcnr.u32Viraddr; ++ stmcnr.u32Viraddr = u32viraddr; ++ gstSupCfg.stmcnr.bEnMCNR = stmcnr.bEnMCNR; ++ gstSupCfg.stmcnr.bEnCIIR = stmcnr.bEnCIIR; ++ } ++ MsOS_VirMemFree((void *)stmcnr.u32Viraddr); ++} ++void _MDrv_VIP_PrepareCheckSetting(EN_VIP_MDRV_CONFIG_TYPE enVIPtype) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ unsigned char bEn,u8framecount; ++ MsOS_Memset(&stSetPQCfg,0,sizeof(ST_MDRV_VIP_SETPQ_CONFIG)); ++ bEn = (_IsSetCMDQ()) ? 1 : 0 ; ++ u8framecount = 0; ++ MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,NULL,&stSetPQCfg); ++ if(_IsCMDQAlreadySetting()) ++ { ++ if(enVIPtype ==EN_VIP_MDRV_MCNR_CONFIG) ++ { ++ _Mdrv_VIP_ModifyMCNRAlreadySetting(EN_VIP_RESET_ZERO); ++ } ++ else ++ { ++ _MDrv_VIP_ResetAlreadySetting(&stSetPQCfg); ++ } ++ } ++ else if(_IsAutoSetting()) ++ { ++ if(enVIPtype ==EN_VIP_MDRV_MCNR_CONFIG) ++ { ++ _Mdrv_VIP_ModifyMCNRAlreadySetting(EN_VIP_FILL_GOLBAL_FULL); ++ } ++ else ++ { ++ _MDrv_VIP_FillAutoSetStruct(&stSetPQCfg); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, ++ "[VIP]%x:addr:%lx\n",enVIPtype,(unsigned long)stSetPQCfg.pGolbalStructAddr); ++ } ++ } ++ _MDrv_VIP_FillstFCfgBelongGlobal(enVIPtype,bEn,u8framecount); ++} ++void _MDrv_VIP_PrepareAIPCheckSetting(EN_VIP_MDRV_AIP_TYPE enAIPtype) ++{ ++ unsigned char bEn,u8framecount; ++ bEn = (_IsSetCMDQ()) ? 1 : 0 ; ++ u8framecount = 0; ++ if(_IsCMDQAlreadySetting()) ++ { ++ _MDrv_VIP_ModifyAIPAlreadySetting(enAIPtype,EN_VIP_RESET_ZERO); ++ } ++ else if(_IsAutoSetting()) ++ { ++ _MDrv_VIP_ModifyAIPAlreadySetting(enAIPtype,EN_VIP_FILL_GOLBAL_FULL); ++ } ++ gstSupCfg.staip[enAIPtype].stFCfg.bEn = bEn; ++ gstSupCfg.staip[enAIPtype].stFCfg.u8framecnt = u8framecount; ++} ++void _MDrv_VIP_For_PrepareCheckSetting(void) ++{ ++ EN_VIP_MDRV_CONFIG_TYPE enVIPtype; ++ EN_VIP_MDRV_AIP_TYPE enAIPType; ++ for(enVIPtype =EN_VIP_MDRV_ACK_CONFIG;enVIPtype<=EN_VIP_MDRV_MCNR_CONFIG;(enVIPtype*=2)) ++ { ++ if(_IsSuspendResetFlag(enVIPtype)) ++ { ++ _MDrv_VIP_PrepareCheckSetting(enVIPtype); ++ } ++ } ++ for(enAIPType =EN_VIP_MDRV_AIP_YEE;enAIPType1000) ++ { ++ printf("[VIP]!!!!Timeout\n"); ++ break; ++ } ++ } ++} ++void _MDrv_VIP_For_SetEachIP(void) ++{ ++ EN_VIP_MDRV_CONFIG_TYPE enVIPtype; ++ EN_VIP_MDRV_AIP_TYPE enAIPType; ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ MsOS_Memset(&stSetPQCfg,0,sizeof(ST_MDRV_VIP_SETPQ_CONFIG)); ++ for(enVIPtype =EN_VIP_MDRV_ACK_CONFIG;enVIPtype<=EN_VIP_MDRV_MCNR_CONFIG;(enVIPtype*=2)) ++ { ++ if(_IsSuspendResetFlag(enVIPtype)) ++ { ++ MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,NULL,&stSetPQCfg); ++ stSetPQCfg.pfForSet((void *)stSetPQCfg.pGolbalStructAddr); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, "[MDRVVIP]%s %d \n", __FUNCTION__,enVIPtype); ++ } ++ } ++ for(enAIPType =EN_VIP_MDRV_AIP_YEE;enAIPTypepPointToCfg, 0,stSetBypassCfg->u32StructSize); ++ } ++ else ++ { ++ if(stSetBypassCfg->bSetConfigFlag) ++ { ++ MsOS_Memcpy(stSetBypassCfg->pPointToCfg,stSetBypassCfg->pGolbalStructAddr ,stSetBypassCfg->u32StructSize); ++ } ++ } ++} ++unsigned char _MDrv_VIP_SetCMDQStatus(unsigned char bFire,unsigned char bEn,unsigned char u8framecnt) ++{ ++ static unsigned char stu8ISPCnt = 0; ++ static unsigned char bEnCMDQ = 0; ++ unsigned char bRet = 0; ++ // TODO: CMDQ ++ if(_IsNotToCheckPQorCMDQmode() && (VIPSETRULE()== E_VIPSetRule_CMDQAll || VIPSETRULE()== E_VIPSetRule_CMDQAllCheck ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck))) ++ { ++ if(Drv_VIP_GetEachDMAEn()) ++ { ++ stu8ISPCnt = Drv_CMDQ_GetISPHWCnt(); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,1,stu8ISPCnt,bFire); ++ if(!bFire) ++ { ++ bEnCMDQ = 1; ++ } ++ else ++ { ++ bEnCMDQ = 0; ++ stu8ISPCnt = 0; ++ } ++ bRet = 1; ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[MVIP]ALL CMDQ framecnt:%hhd\n",Drv_CMDQ_GetISPHWCnt()); ++ } ++ else if(bFire && bEnCMDQ) ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,bEnCMDQ,stu8ISPCnt,bFire); ++ bEnCMDQ = 0; ++ stu8ISPCnt = 0; ++ bRet = 1; ++ } ++ else ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,bEn,u8framecnt,bFire); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, "[MVIP]CMDQ:%hhd,framecnt:%hhd\n" ++ ,bEn,u8framecnt); ++ if(bEn) ++ { ++ bRet = 1; ++ } ++ } ++ } ++ else if(_IsNotToCheckPQorCMDQmode() && VIPSETRULE()) ++ { ++ if((!MDrv_VIP_GetIsBlankingRegion())&&(!bEn)) ++ { ++ stu8ISPCnt = Drv_CMDQ_GetISPHWCnt(); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,1,stu8ISPCnt,bFire); ++ if(!bFire) ++ { ++ bEnCMDQ = 1; ++ } ++ else ++ { ++ bEnCMDQ = 0; ++ stu8ISPCnt = 0; ++ } ++ bRet = 1; ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[MVIP]framecnt:%hhd\n",Drv_CMDQ_GetISPHWCnt()); ++ } ++ else if(bFire && bEnCMDQ) ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,bEnCMDQ,stu8ISPCnt,bFire); ++ bEnCMDQ = 0; ++ stu8ISPCnt = 0; ++ bRet = 1; ++ } ++ else ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,bEn,u8framecnt,bFire); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, "[MVIP]CMDQ:%hhd,framecnt:%hhd\n" ++ ,bEn,u8framecnt); ++ if(bEn) ++ { ++ bRet = 1; ++ } ++ } ++ } ++ else ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,bEn,u8framecnt,bFire); ++ } ++ return bRet; ++} ++void _MDrv_VIP_SetPQParameter(ST_MDRV_VIP_SETPQ_CONFIG *stSetBypassCfg) ++{ ++ MDrv_PQ_LoadSettingByData(PQ_MAIN_WINDOW,stSetBypassCfg->enPQIPType,stSetBypassCfg->pPointToCfg,stSetBypassCfg->u32StructSize); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MVIP]enPQIPType:%ld,u32StructSize:%ld\n" ++ ,stSetBypassCfg->enPQIPType,stSetBypassCfg->u32StructSize); ++} ++void _MDrv_VIP_SetPQByType(MS_U8 u8PQIPIdx, MS_U8 *pData) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ MS_U16 u16Structsize; ++ MsOS_Memset(&stSetPQCfg,0,sizeof(ST_MDRV_VIP_SETPQ_CONFIG)); ++ if(u8PQIPIdx>=AIPOffset || u8PQIPIdx==PQ_IP_MCNR_Main) ++ { ++ u16Structsize = MDrv_PQ_GetIPRegCount(u8PQIPIdx); ++ } ++ else ++ { ++ u16Structsize = _MDrv_VIP_ChioceStructSizeFromPQType(u8PQIPIdx); ++ } ++ _MDrv_VIP_FillPQCfgByType(u8PQIPIdx,pData,u16Structsize,&stSetPQCfg); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MVIP]Struct size:%hd,%hd\n" ++ ,u16Structsize,MDrv_PQ_GetIPRegCount(u8PQIPIdx)); ++ _MDrv_VIP_SetPQParameter(&stSetPQCfg); ++} ++void _MDrv_VIP_SetMCNR(ST_MDRV_VIP_MCNR_CONFIG *pstCfg) ++{ ++ Drv_VIP_SetMCNRIPMRead(pstCfg->bEnMCNR); ++ Drv_VIP_SetIPMConpress(pstCfg->bEnMCNR); ++ if(MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&E_SCLIRQ_EVENT_BCLOSECIIR) ++ { ++ Drv_VIP_SetCIIRRead(0); ++ Drv_VIP_SetCIIRWrite(0); ++ } ++ else if(_IsCIIRBufferAllocatedReady()) ++ { ++ Drv_VIP_SetCIIRRead(pstCfg->bEnCIIR); ++ Drv_VIP_SetCIIRWrite(pstCfg->bEnCIIR); ++ } ++ else ++ { ++ //SCL_DBGERR( "[MDRVVIP]%s,CIIR buffer not alloc \n", __FUNCTION__); ++ } ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_MCNR_Main,(unsigned char *)pstCfg->u32Viraddr); ++} ++static int VIP_DazaIST(void *arg) ++{ ++ MS_U32 u32Events; ++ VIPDAZAEvent enDAZAEvent; ++ unsigned short u16AIPsheet; ++ while(b_MVIP_TASKEn) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[DRVVIP]%s:going event:%x @:%lu\n" ++ ,__FUNCTION__,genVipDazaEvent,((MS_U32)MsOS_GetSystemTimeStamp())); ++ if(genVipDazaEvent) ++ { ++ if((MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC)) ++ !=(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC)) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_ISPFRMEND, &u32Events, E_OR, 2000); // get status: FRM END ++ MsOS_DelayTaskUs(100); ++ } ++ MDRV_VIP_MUTEX_LOCK(); ++ enDAZAEvent = genVipDazaEvent; ++ MDRV_VIP_MUTEX_UNLOCK(); ++ if(enDAZAEvent &E_VIP_DAZA_BMCNR) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[DRVVIP]E_VIP_DAZA_BMCNR\n"); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,0,0,1); ++ _MDrv_VIP_SetMCNR(&gstSupCfg.stmcnr); ++ genVipDazaEvent &= (~E_VIP_DAZA_BMCNR); ++ } ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ // avoid one blanking region can't set all cmd,double switch. ++ else if(enDAZAEvent &E_VIP_DAZA_BGMA2C) ++ { ++ u16AIPsheet = _GetAIPOffset(EN_VIP_MDRV_AIP_GM10TO12); ++ MDRV_VIP_MUTEX_LOCK(); ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[DRVVIP]E_VIP_DAZA_BGMA2C\n"); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,0,0,1); ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_SCL0_01_L, BIT3, BIT3); ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)gstSupCfg.staip[EN_VIP_MDRV_AIP_GM10TO12].u32Viraddr); ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_SCL0_01_L, 0, BIT3); ++ genVipDazaEvent &= (~E_VIP_DAZA_BGMA2C); ++ } ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ if(enDAZAEvent &E_VIP_DAZA_BNLM) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[DRVVIP]E_VIP_DAZA_BNLM\n"); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,0,0,1); ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_NLM_Main,(MS_U8 *)&gstSupCfg.stnlm.stNLM); ++ genVipDazaEvent &= (~E_VIP_DAZA_BNLM); ++ } ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ else if(enDAZAEvent &E_VIP_DAZA_BGMC2A) ++ { ++ u16AIPsheet = _GetAIPOffset(EN_VIP_MDRV_AIP_GM12TO10); ++ MDRV_VIP_MUTEX_LOCK(); ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[DRVVIP]E_VIP_DAZA_BGMC2A\n"); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,0,0,1); ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_SCL0_01_L, BIT3, BIT3); ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)gstSupCfg.staip[EN_VIP_MDRV_AIP_GM12TO10].u32Viraddr); ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_SCL0_01_L, 0, BIT3); ++ genVipDazaEvent &= (~E_VIP_DAZA_BGMC2A); ++ } ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ if(enDAZAEvent &E_VIP_DAZA_BXNR) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_NORMAL, "[DRVVIP]E_VIP_DAZA_BXNR\n"); ++ u16AIPsheet = _GetAIPOffset(EN_VIP_MDRV_AIP_XNR); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,0,0,1); ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)gstSupCfg.staip[EN_VIP_MDRV_AIP_XNR].u32Viraddr); ++ genVipDazaEvent &= (~E_VIP_DAZA_BXNR); ++ } ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ } ++ else ++ { ++ MsOS_SleepTaskWork(_MVIP_TASK); ++ } ++ } ++ return 0; ++} ++unsigned char _MDrv_VIP_For_SetEachPQTypeByIP ++ (unsigned char u8FirstType,unsigned char u8LastType,ST_MDRV_VIP_FC_CONFIG *stFCfg,MS_U8 ** pPointToData) ++{ ++ unsigned char u8PQType; ++ unsigned char bRet = 0; ++ for(u8PQType = u8FirstType;u8PQType<=u8LastType;u8PQType++) ++ { ++ if(u8PQType == u8FirstType) ++ { ++ bRet = _MDrv_VIP_SetCMDQStatus(0,stFCfg->bEn,stFCfg->u8framecnt); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,bRet); ++ } ++ else if(u8PQType == u8LastType) ++ { ++ bRet = _MDrv_VIP_SetCMDQStatus(1,stFCfg->bEn,stFCfg->u8framecnt); ++ } ++ _MDrv_VIP_SetPQByType(u8PQType,pPointToData[u8PQType-u8FirstType]); ++ if(u8PQType == u8LastType) ++ { ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ } ++ } ++ return bRet; ++} ++unsigned char _MDrv_VIP_SetBypassIP(unsigned long bBypass,EN_VIP_MDRV_CONFIG_TYPE enVIPtype) ++{ ++ ST_MDRV_VIP_SETPQ_CONFIG stSetBypassCfg; ++ MsOS_Memset(&stSetBypassCfg,0,sizeof(ST_MDRV_VIP_SETPQ_CONFIG)); ++ stSetBypassCfg.bSetConfigFlag = _IsSuspendResetFlag(enVIPtype); ++ switch(enVIPtype) ++ { ++ case EN_VIP_MDRV_MCNR_CONFIG: ++ MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,NULL,&stSetBypassCfg); ++ if(bBypass) ++ { ++ _Mdrv_VIP_ModifyMCNRAlreadySetting(EN_VIP_RESET_ZERO); ++ } ++ else ++ { ++ stSetBypassCfg.pfForSet((void *)stSetBypassCfg.pGolbalStructAddr); ++ } ++ break; ++ case EN_VIP_MDRV_NLM_CONFIG: ++ stSetBypassCfg.u32StructSize = sizeof(ST_MDRV_VIP_NLM_MAIN_CONFIG); ++ stSetBypassCfg.pGolbalStructAddr = (unsigned char *)&gstSupCfg.stnlm.stNLM; ++ stSetBypassCfg.enPQIPType = PQ_IP_NLM_Main; ++ stSetBypassCfg.pPointToCfg = MsOS_Memalloc(stSetBypassCfg.u32StructSize, GFP_KERNEL); ++ if(!stSetBypassCfg.pPointToCfg) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init stSetBypassCfg.pPointToCfg Fail\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ _MDrv_VIP_PrepareBypassFunctionStruct(bBypass,&stSetBypassCfg); ++ if(stSetBypassCfg.bSetConfigFlag) ++ { ++ _MDrv_VIP_SetPQParameter(&stSetBypassCfg); ++ } ++ MsOS_MemFree(stSetBypassCfg.pPointToCfg); ++ break; ++ case EN_VIP_MDRV_LDC_CONFIG: ++ Drv_VIP_SetLDCOnConfig(!bBypass); ++ break; ++ case EN_VIP_MDRV_CONFIG: ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,0,0,0); ++ stSetBypassCfg.u32StructSize = sizeof(ST_MDRV_VIP_BYPASS_CONFIG); ++ stSetBypassCfg.enPQIPType = PQ_IP_VIP_Main; ++ stSetBypassCfg.pPointToCfg = MsOS_Memalloc(stSetBypassCfg.u32StructSize, GFP_KERNEL); ++ if(!stSetBypassCfg.pPointToCfg) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init stSetBypassCfg.pPointToCfg Fail\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ MsOS_Memset(stSetBypassCfg.pPointToCfg, (bBypass) ? 0x1 :0,stSetBypassCfg.u32StructSize); ++ _MDrv_VIP_SetPQParameter(&stSetBypassCfg); ++ MsOS_MemFree(stSetBypassCfg.pPointToCfg); ++ break; ++ default: ++ return 0; ++ ++ } ++ return 1; ++} ++unsigned long _MDrv_VIP_FillSettingBuffer(MS_U16 u16PQIPIdx, MS_U32 u32pstViraddr, MS_U32 *u32gpViraddr) ++{ ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MS_U16 u16StructSize; ++ MS_U32 u32ViraddrOri; ++ MS_U32 u32Viraddr; ++ u16StructSize = MDrv_PQ_GetIPRegCount(u16PQIPIdx); ++ u32ViraddrOri = u32pstViraddr; ++ if(*u32gpViraddr) ++ { ++ u32Viraddr = *u32gpViraddr; ++ } ++ else ++ { ++ *u32gpViraddr = (unsigned long)MsOS_VirMemalloc(u16StructSize); ++ if(!*u32gpViraddr) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init *u32gpViraddr Fail\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ MsOS_Memset((void *)*u32gpViraddr,0,u16StructSize); ++ u32Viraddr = *u32gpViraddr; ++ } ++ if(u32Viraddr != u32ViraddrOri) ++ { ++ if(MsOS_copy_from_user((void *)u32Viraddr, (__user void *)u32ViraddrOri, u16StructSize)) ++ { ++ if((u32ViraddrOri&MIU0Vir_BASE)==MIU0Vir_BASE) ++ { ++ MsOS_Memcpy((void *)u32Viraddr, (void *)u32ViraddrOri, u16StructSize); ++ } ++ else ++ { ++ SCL_ERR( "[VIP] copy buffer error Ori:%lx ,%lx\n",u32ViraddrOri,u32Viraddr); ++ return 0; ++ } ++ } ++ } ++ return u32Viraddr; ++ } ++ else ++ { ++ return u32pstViraddr; ++ } ++} ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void MDrv_VIP_FillBasicStructSetPQCfg(EN_VIP_MDRV_CONFIG_TYPE enVIPtype,void *pPointToCfg,ST_MDRV_VIP_SETPQ_CONFIG *stSetPQCfg) ++{ ++ stSetPQCfg->bSetConfigFlag = _IsSuspendResetFlag(enVIPtype); ++ stSetPQCfg->pPointToCfg = pPointToCfg; ++ switch(enVIPtype) ++ { ++ case EN_VIP_MDRV_MCNR_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_MCNR_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stmcnr; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetMCNRConfig; ++ break; ++ ++ case EN_VIP_MDRV_ACK_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_ACK_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stack; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetACKConfig; ++ break; ++ ++ case EN_VIP_MDRV_IBC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_IBC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stibc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetIBCConfig; ++ break; ++ ++ case EN_VIP_MDRV_IHCICC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_IHCICC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stihcicc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetIHCICCADPYConfig; ++ break; ++ ++ case EN_VIP_MDRV_ICC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_ICC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.sticc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetICEConfig; ++ break; ++ ++ case EN_VIP_MDRV_IHC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_IHC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stihc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetIHCConfig; ++ break; ++ ++ case EN_VIP_MDRV_FCC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_FCC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stfcc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetFCCConfig; ++ break; ++ case EN_VIP_MDRV_UVC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_UVC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stuvc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetUVCConfig; ++ break; ++ ++ case EN_VIP_MDRV_DLC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_DLC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stdlc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetDLCConfig; ++ break; ++ ++ case EN_VIP_MDRV_DLC_HISTOGRAM_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_DLC_HISTOGRAM_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.sthist; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetHistogramConfig; ++ break; ++ ++ case EN_VIP_MDRV_LCE_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_LCE_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stlce; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetLCEConfig; ++ break; ++ ++ case EN_VIP_MDRV_PEAKING_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_PEAKING_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stpk; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetPeakingConfig; ++ break; ++ ++ case EN_VIP_MDRV_LDC_MD_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_LDC_MD_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldcmd; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetLDCmdConfig; ++ break; ++ ++ case EN_VIP_MDRV_LDC_DMAP_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_LDC_DMAP_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldcdmap; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetLDCDmapConfig; ++ break; ++ ++ case EN_VIP_MDRV_LDC_SRAM_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_LDC_SRAM_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldcsram; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetLDCSRAMConfig; ++ break; ++ ++ case EN_VIP_MDRV_NLM_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_NLM_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stnlm; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetNLMConfig; ++ break; ++ case EN_VIP_MDRV_LDC_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_LDC_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stldc; ++ stSetPQCfg->pfForSet = MDrv_VIP_SetLDCConfig; ++ break; ++ case EN_VIP_MDRV_CONFIG: ++ stSetPQCfg->u32StructSize = sizeof(ST_MDRV_VIP_CONFIG); ++ stSetPQCfg->pGolbalStructAddr = (unsigned char *)&gstSupCfg.stvip; ++ stSetPQCfg->pfForSet = MDrv_SetVIPOtherConfig; ++ break; ++ default: ++ stSetPQCfg->u32StructSize = 0; ++ stSetPQCfg->pGolbalStructAddr = NULL; ++ stSetPQCfg->bSetConfigFlag = 0; ++ stSetPQCfg->pfForSet = NULL; ++ break; ++ ++ } ++} ++void _MDrv_VIP_InitSupCfg(void) ++{ ++ MsOS_Memset(&gstSupCfg, 0, sizeof(ST_MDRV_VIP_SUSPEND_CONFIG)); ++} ++void MDrv_VIP_FreeMemory(void) ++{ ++ EN_VIP_MDRV_AIP_TYPE enVIPtype; ++ if(gstSupCfg.stmcnr.u32Viraddr) ++ { ++ MsOS_VirMemFree((void *)gstSupCfg.stmcnr.u32Viraddr); ++ gstSupCfg.stmcnr.u32Viraddr = NULL; ++ } ++ for(enVIPtype = EN_VIP_MDRV_AIP_YEE;enVIPtypeu32RiuBase; ++ stCMDQIniCfg.u32CMDQ_Phy[0] = pCfg->CMDQCfg.u32CMDQ_Phy; ++ stCMDQIniCfg.u32CMDQ_Size[0] = pCfg->CMDQCfg.u32CMDQ_Size; ++ stCMDQIniCfg.u32CMDQ_Vir[0] = pCfg->CMDQCfg.u32CMDQ_Vir; ++ Drv_VIP_HWInit(); ++ MDrv_VIP_VtrackInit(); ++ Drv_CMDQ_Init(&stCMDQIniCfg); ++ MDRV_VIP_MUTEX_LOCK(); ++ gu32OpenBypass = 0; ++ gu32AIPOpenBypass = 0; ++ gbVIPCMDQSet = 0; ++ gbAIPCMDQSet = 0; ++ gbAlreadyOpenGamma = 0; ++ MDRV_VIP_MUTEX_UNLOCK(); ++ Drv_VIP_SRAM_Dump(); ++} ++ ++unsigned char MDrv_VIP_Init(ST_MDRV_VIP_INIT_CONFIG *pCfg) ++{ ++ ST_VIP_INIT_CONFIG stIniCfg; ++ ST_VIP_OPEN_CONFIG stCMDQIniCfg; ++ MS_PQ_Init_Info stPQInitInfo; ++ unsigned char ret = FALSE; ++ char word[] = {"_MVIP_Mutex"}; ++ _MVIP_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ if (_MVIP_Mutex == -1) ++ { ++ SCL_ERR("[MDRVVIP]%s create mutex fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ b_MVIP_TASKEn = 1; ++ _MVIP_TASK = MsOS_CreateTask((TaskEntry)VIP_DazaIST,(MS_U32)NULL,TRUE,(const char*)"VIPDazaTask"); ++ if (_MVIP_TASK == -1) ++ { ++ SCL_ERR("[MDRVVIP]%s create task fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ MsOS_Memset(&stCMDQIniCfg,0,sizeof(ST_VIP_OPEN_CONFIG)); ++ MsOS_Memset(&stIniCfg,0,sizeof(ST_VIP_INIT_CONFIG)); ++ stIniCfg.u32RiuBase = pCfg->u32RiuBase; ++ stCMDQIniCfg.u32RiuBase = pCfg->u32RiuBase; ++ stCMDQIniCfg.u32CMDQ_Phy[0] = pCfg->CMDQCfg.u32CMDQ_Phy; ++ stCMDQIniCfg.u32CMDQ_Size[0] = pCfg->CMDQCfg.u32CMDQ_Size; ++ stCMDQIniCfg.u32CMDQ_Vir[0] = pCfg->CMDQCfg.u32CMDQ_Vir; ++ if(Drv_VIP_Init(&stIniCfg) == 0) ++ { ++ SCL_ERR( "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ Drv_VIP_HWInit(); ++ MDrv_VIP_VtrackInit(); ++ MDrv_PQ_init_RIU(pCfg->u32RiuBase); ++ Drv_CMDQ_Init(&stCMDQIniCfg); ++ MsOS_Memset(&stPQInitInfo, 0, sizeof(MS_PQ_Init_Info)); ++ MDRV_VIP_MUTEX_LOCK(); ++ gu32OpenBypass = 0; ++ gu32AIPOpenBypass = 0; ++ gbVIPCMDQSet = 0; ++ gbAIPCMDQSet = 0; ++ gbAlreadyOpenGamma = 0; ++ MDRV_VIP_MUTEX_UNLOCK(); ++ // Init PQ ++ stPQInitInfo.u16PnlWidth = 1920; ++ stPQInitInfo.u8PQBinCnt = 0; ++ stPQInitInfo.u8PQTextBinCnt = 0; ++ if(MDrv_PQ_Init(&stPQInitInfo)) ++ { ++ MDrv_PQ_DesideSrcType(PQ_MAIN_WINDOW, PQ_INPUT_SOURCE_ISP); ++ MDrv_PQ_LoadSettings(PQ_MAIN_WINDOW); ++ ret = TRUE; ++ } ++ else ++ { ++ ret = FALSE; ++ } ++ _MDrv_VIP_InitSupCfg(); ++ return ret; ++} ++void MDrv_VIP_Delete(unsigned char bCloseISR) ++{ ++ b_MVIP_TASKEn = 0; ++ MsOS_DeleteTask(_MVIP_TASK); ++ _MVIP_TASK = -1; ++ if (_MVIP_Mutex != -1) ++ { ++ MsOS_DeleteMutex(_MVIP_Mutex); ++ _MVIP_Mutex = -1; ++ } ++ if(bCloseISR) ++ { ++ Drv_SCLIRQ_Exit(); ++ } ++ Drv_VIP_Exit(); ++ Drv_CMDQ_Delete(EN_CMDQ_TYPE_IP0); ++} ++void MDrv_VIP_Supend(void) ++{ ++ Drv_CMDQ_Delete(EN_CMDQ_TYPE_IP0); ++} ++void MDrv_VIP_Release(void) ++{ ++ unsigned long u32Events; ++ Drv_CMDQ_release(EN_CMDQ_TYPE_IP0); ++ MDRV_VIP_MUTEX_LOCK(); ++ gbVIPCMDQSet = 0; ++ gbAIPCMDQSet = 0; ++ gbAlreadyOpenGamma = 0; ++ MDRV_VIP_MUTEX_UNLOCK(); ++ if(!MDrv_VIP_GetIsBlankingRegion()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 200); // get status: FRM END ++ } ++ Drv_VIP_SetIPMConpress(0); ++ MDrv_PQ_LoadSettings(PQ_MAIN_WINDOW); ++} ++unsigned char MDrv_VIP_GetCMDQHWDone(void) ++{ ++ return Drv_VIP_GetCMDQHWDone(); ++} ++ ++void * MDrv_VIP_GetWaitQueueHead(void) ++{ ++ return Drv_VIP_GetWaitQueueHead(); ++} ++void MDrv_VIP_SetPollWait ++ (void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ MsOS_SetPollWait(filp, pWaitQueueHead, pstPollQueue); ++} ++ ++void MDrv_VIP_SuspendResetFlagInit(void) ++{ ++ gstSupCfg.bresetflag = 0; ++} ++void MDrv_VIP_SetAllVIPOneshot(ST_MDRV_VIP_SUSPEND_CONFIG *stvipCfg) ++{ ++ EN_VIP_MDRV_CONFIG_TYPE enVIPtype; ++ EN_VIP_MDRV_AIP_TYPE enAIPtype; ++ ST_MDRV_VIP_SETPQ_CONFIG stSetPQCfg; ++ unsigned long u32StructSize = sizeof(unsigned long); ++ MsOS_Memset(&stSetPQCfg,0,sizeof(ST_MDRV_VIP_SETPQ_CONFIG)); ++ gstSupCfg.bresetflag = stvipCfg->bresetflag; ++ gstSupCfg.bresetflag &= 0x2FFFF; ++ gstSupCfg.bAIPreflag = stvipCfg->bAIPreflag; ++ for(enVIPtype =EN_VIP_MDRV_ACK_CONFIG;enVIPtype<=EN_VIP_MDRV_MCNR_CONFIG;(enVIPtype*=2)) ++ { ++ MDrv_VIP_FillBasicStructSetPQCfg(enVIPtype,(void *)((unsigned long)stvipCfg+u32StructSize),&stSetPQCfg); ++ if(_IsSuspendResetFlag(enVIPtype)) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPSUP, ++ "enVIPtype :%d pGolbalStructAddr: %lx,pPointToCfg: %lx,size:%lx\n",enVIPtype, ++ (unsigned long)stSetPQCfg.pGolbalStructAddr,(unsigned long)stSetPQCfg.pPointToCfg,stSetPQCfg.u32StructSize); ++ MsOS_Memcpy(stSetPQCfg.pGolbalStructAddr,stSetPQCfg.pPointToCfg,stSetPQCfg.u32StructSize); ++ } ++ u32StructSize += stSetPQCfg.u32StructSize; ++ } ++ for(enAIPtype =EN_VIP_MDRV_AIP_YEE;enAIPtypestaip[enAIPtype].u32Viraddr,&gstSupCfg.staip[enAIPtype].u32Viraddr); ++ gstSupCfg.staip[enAIPtype].stFCfg.bEn = stvipCfg->staip[enAIPtype].stFCfg.bEn; ++ gstSupCfg.staip[enAIPtype].stFCfg.u8framecnt = stvipCfg->staip[enAIPtype].stFCfg.u8framecnt; ++ gstSupCfg.staip[enAIPtype].u16AIPType = stvipCfg->staip[enAIPtype].u16AIPType; ++ } ++ } ++ _MDrv_VIP_For_SetEachIP(); ++} ++void MDrv_VIP_ResetEachIP(void) ++{ ++ _MDrv_VIP_For_SetEachIP(); ++ _MDrv_VIP_ResumeDumpSRAM(); ++ if(gbVIPCheckCMDQorPQ >= EN_VIP_CMDQ_CHECK_ALREADY_SETINNG) ++ { ++ Drv_CMDQ_BeTrigger(EN_CMDQ_TYPE_IP0,1); ++ } ++} ++ ++unsigned char MDrv_VIP_Sys_Init(ST_MDRV_VIP_INIT_CONFIG *pCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s %d\n", __FUNCTION__,__LINE__); ++ Drv_CMDQ_Enable(1,EN_CMDQ_TYPE_IP0); ++ Drv_VIP_Open(); ++ return TRUE; ++} ++void MDrv_VIP_SetMCNRConpressForDebug(unsigned char bEn) ++{ ++ if(gstSupCfg.stmcnr.bEnMCNR) ++ { ++ Drv_VIP_SetIPMConpress(bEn); ++ } ++} ++void _MDrv_VIP_CopyAIPConfigToGlobal(EN_VIP_MDRV_AIP_TYPE enVIPtype, void *pCfg, unsigned long u32StructSize) ++{ ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MsOS_Memcpy(&gstSupCfg.staip[enVIPtype], pCfg,u32StructSize); ++ gstSupCfg.staip[enVIPtype].stFCfg.bEn = 0 ; ++ gstSupCfg.staip[enVIPtype].stFCfg.u8framecnt = 0; ++ gstSupCfg.staip[enVIPtype].u16AIPType= enVIPtype; ++ _Set_SuspendAIPResetFlag(enVIPtype); ++ } ++} ++unsigned char MDrv_VIP_SetMCNRConfig(void *pCfg) ++{ ++ ST_MDRV_VIP_MCNR_CONFIG *pstCfg = pCfg; ++ static MS_BOOL bbypass = 0; ++ if(_IsFrameBufferAllocatedReady()) ++ { ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(_IsNotOpenVIPBypass(EN_VIP_MDRV_MCNR_CONFIG)) ++ { ++ bbypass = 0; ++ pstCfg->u32Viraddr = ++ _MDrv_VIP_FillSettingBuffer(PQ_IP_MCNR_Main,pstCfg->u32Viraddr,&gstSupCfg.stmcnr.u32Viraddr); ++ if(!pstCfg->u32Viraddr) ++ { ++ return 0; ++ } ++ //_MDrv_VIP_SetCMDQStatus(1,pstCfg->stFCfg.bEn,pstCfg->stFCfg.u8framecnt); ++ if(((MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC)) ++ !=(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC))&&(_IsNotToCheckPQorCMDQmode())) ++ { ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_MCNR_CONFIG,(void *)pstCfg); ++ _MDrv_VIP_SetDAZATaskWork(E_VIP_DAZA_BMCNR); ++ } ++ else ++ { ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pstCfg->stFCfg.bEn); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,pstCfg->stFCfg.bEn,pstCfg->stFCfg.u8framecnt,1); ++ _MDrv_VIP_SetMCNR(pstCfg); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pstCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_MCNR_CONFIG,(void *)pstCfg); ++ } ++ } ++ else if(bbypass==0) ++ { ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pstCfg->stFCfg.bEn); ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,pstCfg->stFCfg.bEn,pstCfg->stFCfg.u8framecnt,1); ++ _MDrv_VIP_SetMCNR(pstCfg); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pstCfg->stFCfg.bEn); ++ bbypass = 1; ++ } ++ else ++ { ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_MCNR_CONFIG,(void *)pstCfg); ++ } ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&(gstSupCfg.stmcnr),gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,MCNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++ return 1; ++} ++ ++ ++unsigned char MDrv_VIP_SetPeakingConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_PEAKING_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_Peaking_gain_ad_Y_Main-PQ_IP_VIP_HLPF_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stHLPF); ++ p8PQType[1] = (MS_U8*)&(pCfg->stHLPFDith); ++ p8PQType[2] = (MS_U8*)&(pCfg->stVLPFcoef1); ++ p8PQType[3] = (MS_U8*)&(pCfg->stVLPFcoef2); ++ p8PQType[4] = (MS_U8*)&(pCfg->stVLPFDith); ++ p8PQType[5] = (MS_U8*)&(pCfg->stOnOff); ++ p8PQType[6] = (MS_U8*)&(pCfg->stBand); ++ p8PQType[7] = (MS_U8*)&(pCfg->stAdp); ++ p8PQType[8] = (MS_U8*)&(pCfg->stPcor); ++ p8PQType[9] = (MS_U8*)&(pCfg->stAdpY); ++ p8PQType[10] = (MS_U8*)&(pCfg->stGain); ++ p8PQType[11] = (MS_U8*)&(pCfg->stGainAdpY); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_HLPF_Main,(MS_U8)PQ_IP_VIP_Peaking_gain_ad_Y_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_PEAKING_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_PEAKING_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stpk,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetHistogramConfig(void *pvCfg) ++{ ++ ST_VIP_DLC_HISTOGRAM_CONFIG stDLCCfg; ++ MS_U16 i; ++ ST_MDRV_VIP_DLC_HISTOGRAM_CONFIG *pCfg = pvCfg; ++ MsOS_Memset(&stDLCCfg,0,sizeof(ST_VIP_DLC_HISTOGRAM_CONFIG)); ++ stDLCCfg.bVariable_Section = pCfg->bVariable_Section; ++ stDLCCfg.bstat_MIU = pCfg->bstat_MIU; ++ stDLCCfg.bcurve_fit_en = pCfg->bcurve_fit_en; ++ stDLCCfg.bcurve_fit_rgb_en = pCfg->bcurve_fit_rgb_en; ++ stDLCCfg.bDLCdither_en = pCfg->bDLCdither_en; ++ stDLCCfg.bhis_y_rgb_mode_en = pCfg->bhis_y_rgb_mode_en; ++ stDLCCfg.bstatic = pCfg->bstatic; ++ stDLCCfg.bRange = pCfg->bRange; ++ stDLCCfg.u16Vst = pCfg->u16Vst; ++ stDLCCfg.u16Hst = pCfg->u16Hst; ++ stDLCCfg.u16Vnd = pCfg->u16Vnd; ++ stDLCCfg.u16Hnd = pCfg->u16Hnd; ++ stDLCCfg.u8HistSft = pCfg->u8HistSft; ++ stDLCCfg.u8trig_ref_mode = pCfg->u8trig_ref_mode; ++ stDLCCfg.u32StatBase[0] = _Phys2Miu(pCfg->u32StatBase[0]); ++ stDLCCfg.u32StatBase[1] = _Phys2Miu(pCfg->u32StatBase[1]); ++ stDLCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stDLCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ ++ for(i=0;iu8Histogram_Range[i]; ++ } ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,stDLCCfg.stFCfg.bEn); ++ ++ if(Drv_VIP_SetDLCHistogramConfig(&stDLCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,stDLCCfg.stFCfg.bEn); ++ MDRV_VIP_MUTEX_UNLOCK(); ++ return FALSE; ++ } ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,stDLCCfg.stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_DLC_HISTOGRAM_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.sthist,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_GetDLCHistogramReport(void *pvCfg) ++{ ++ ST_VIP_DLC_HISTOGRAM_REPORT stDLCCfg; ++ MS_U16 i; ++ ST_MDRV_VIP_DLC_HISTOGRAM_REPORT *pCfg = pvCfg; ++ MsOS_Memset(&stDLCCfg,0,sizeof(ST_VIP_DLC_HISTOGRAM_REPORT)); ++ Drv_VIP_GetDLCHistogramConfig(&stDLCCfg); ++ pCfg->u32PixelWeight = stDLCCfg.u32PixelWeight; ++ pCfg->u32PixelCount = stDLCCfg.u32PixelCount; ++ pCfg->u8MaxPixel = stDLCCfg.u8MaxPixel; ++ pCfg->u8MinPixel = stDLCCfg.u8MinPixel; ++ pCfg->u8Baseidx = stDLCCfg.u8Baseidx; ++ for(i=0;iu32Histogram[i] = stDLCCfg.u32Histogram[i]; ++ } ++ ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetDLCConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_DLC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_YC_gain_offset_Main-PQ_IP_VIP_DLC_His_range_Main+1)];//add PQ_IP_VIP_YC_gain_offset_Main ++ p8PQType[0] = (MS_U8*)&(pCfg->sthist); ++ p8PQType[1] = (MS_U8*)&(pCfg->stEn); ++ p8PQType[2] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[3] = (MS_U8*)&(pCfg->stHistH); ++ p8PQType[4] = (MS_U8*)&(pCfg->stHistV); ++ p8PQType[5] = (MS_U8*)&(pCfg->stPC); ++ p8PQType[6] = (MS_U8*)&(pCfg->stGainOffset); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_DLC_His_range_Main,(MS_U8)PQ_IP_VIP_YC_gain_offset_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_DLC_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_DLC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stdlc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetLCEConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_LCE_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_LCE_curve_Main-PQ_IP_VIP_LCE_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stOnOff); ++ p8PQType[1] = (MS_U8*)&(pCfg->stDITHER); ++ p8PQType[2] = (MS_U8*)&(pCfg->stSet); ++ p8PQType[3] = (MS_U8*)&(pCfg->stCurve); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_LCE_Main,(MS_U8)PQ_IP_VIP_LCE_curve_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_LCE_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_LCE_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stlce,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetUVCConfig(void *pvCfg) ++{ ++ MS_U8 *pUVC = NULL; ++ MS_U8 bRet = 0; ++ ST_MDRV_VIP_UVC_CONFIG *pCfg = pvCfg; ++ pUVC = (MS_U8*)&(pCfg->stUVC); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ if(_MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt)) ++ { ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,1); ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_UVC_CONFIG); ++ bRet = 1; ++ } ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_VIP_UVC_Main,pUVC); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_UVC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stuvc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++ ++unsigned char MDrv_VIP_SetIHCConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_IHC_CONFIG *pCfg = pvCfg; ++ MS_U8 bRet = 0; ++ MS_U8 *p8PQType[(PQ_IP_VIP_IHC_dither_Main-PQ_IP_VIP_IHC_Main+2)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stOnOff); ++ p8PQType[1] = (MS_U8*)&(pCfg->stYmd); ++ p8PQType[2] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[3] = (MS_U8*)&(pCfg->stset); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ bRet = _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,bRet); ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_VIP_IHC_SETTING_Main,p8PQType[3]); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_IHC_Main,(MS_U8)PQ_IP_VIP_IHC_dither_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_IHC_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_IHC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stihc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetICEConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_ICC_CONFIG *pCfg = pvCfg; ++ MS_U8 bRet = 0; ++ MS_U8 *p8PQType[(PQ_IP_VIP_ICC_SETTING_Main-PQ_IP_VIP_ICC_dither_Main+2)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stEn); ++ p8PQType[1] = (MS_U8*)&(pCfg->stYmd); ++ p8PQType[2] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[3] = (MS_U8*)&(pCfg->stSet); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ bRet = _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,bRet); ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_VIP_ICC_SETTING_Main,p8PQType[3]); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_ICC_Main,(MS_U8)PQ_IP_VIP_ICC_dither_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_ICC_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_ICC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.sticc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++ ++unsigned char MDrv_VIP_SetIHCICCADPYConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_IHCICC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_Ymode_Yvalue_SETTING_Main-PQ_IP_VIP_Ymode_Yvalue_ALL_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stYmdall); ++ p8PQType[1] = (MS_U8*)&(pCfg->stYmdset); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_Ymode_Yvalue_ALL_Main,(MS_U8)PQ_IP_VIP_Ymode_Yvalue_SETTING_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_IHCICC_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_IHCICC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stihcicc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetIBCConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_IBC_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_IBC_SETTING_Main-PQ_IP_VIP_IBC_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stEn); ++ p8PQType[1] = (MS_U8*)&(pCfg->stDither); ++ p8PQType[2] = (MS_U8*)&(pCfg->stSet); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_IBC_Main,(MS_U8)PQ_IP_VIP_IBC_SETTING_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_IBC_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_IBC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stibc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetFCCConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_FCC_CONFIG *pCfg = pvCfg; ++ MS_U8 bRet = 0; ++ MS_U8 *p8PQType[(PQ_IP_VIP_FCC_T9_Main-PQ_IP_VIP_FCC_T1_Main+2)]; ++ p8PQType[9] = (MS_U8*)&(pCfg->stfr); ++ p8PQType[0] = (MS_U8*)&(pCfg->stT[0]); ++ p8PQType[1] = (MS_U8*)&(pCfg->stT[1]); ++ p8PQType[2] = (MS_U8*)&(pCfg->stT[2]); ++ p8PQType[3] = (MS_U8*)&(pCfg->stT[3]); ++ p8PQType[4] = (MS_U8*)&(pCfg->stT[4]); ++ p8PQType[5] = (MS_U8*)&(pCfg->stT[5]); ++ p8PQType[6] = (MS_U8*)&(pCfg->stT[6]); ++ p8PQType[7] = (MS_U8*)&(pCfg->stT[7]); ++ p8PQType[8] = (MS_U8*)&(pCfg->stT9); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ bRet = _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,bRet); ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_VIP_FCC_full_range_Main,p8PQType[9]); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_FCC_T1_Main,(MS_U8)PQ_IP_VIP_FCC_T9_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_FCC_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_FCC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stfcc,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++ ++unsigned char MDrv_VIP_SetACKConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_ACK_CONFIG *pCfg = pvCfg; ++ MS_U8 *p8PQType[(PQ_IP_VIP_YCbCr_Clip_Main-PQ_IP_VIP_ACK_Main+1)]; ++ p8PQType[0] = (MS_U8*)&(pCfg->stACK); ++ p8PQType[1] = (MS_U8*)&(pCfg->stclip); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_VIP_ACK_Main,(MS_U8)PQ_IP_VIP_YCbCr_Clip_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_ACK_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_ACK_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stack,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetNLMConfig(void *pvCfg) ++{ ++ MS_U8 *stNLM = NULL; ++ ST_MDRV_VIP_NLM_CONFIG *pCfg = pvCfg; ++ stNLM = (MS_U8*)&(pCfg->stNLM); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(_IsNotOpenVIPBypass(EN_VIP_MDRV_NLM_CONFIG)) ++ { ++ //_MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ if(((MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC)) ++ !=(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC))&&(_IsNotToCheckPQorCMDQmode())) ++ { ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_NLM_CONFIG,(void *)pCfg); ++ _MDrv_VIP_SetDAZATaskWork(E_VIP_DAZA_BNLM); ++ } ++ else ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt,1); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_NLM_Main,stNLM); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,pCfg->stFCfg.bEn); ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_NLM_CONFIG,(void *)pCfg); ++ } ++ } ++ else ++ { ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_NLM_CONFIG,(void *)pCfg); ++ } ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stnlm,gstSupCfg.bresetflag); ++ return TRUE; ++} ++ ++unsigned char MDrv_VIP_SetNLMSRAMConfig(ST_MDRV_VIP_NLM_SRAM_CONFIG *stSRAM) ++{ ++ ST_VIP_NLM_SRAM_CONFIG stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(ST_VIP_NLM_SRAM_CONFIG)); ++ stCfg.u32baseadr = _Phys2Miu(stSRAM->u32Baseadr); ++ stCfg.bCLientEn = stSRAM->bEn; ++ stCfg.u32viradr = stSRAM->u32viradr; ++ stCfg.btrigContinue = 0; //single ++ stCfg.u16depth = VIP_NLM_ENTRY_NUM; // entry ++ stCfg.u16reqlen = VIP_NLM_ENTRY_NUM; ++ stCfg.u16iniaddr = 0; ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s, flag:%hhx ,addr:%lx,addr:%lx \n", __FUNCTION__,stSRAM->bEn,stSRAM->u32viradr,stSRAM->u32Baseadr); ++ Drv_VIP_SetNLMSRAMConfig(&stCfg); ++ return TRUE; ++} ++ ++unsigned char MDrv_SetVIPOtherConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_CONFIG *pCfg = pvCfg; ++ MS_U8 bRet = 0; ++ MS_U8 *p8PQType[2]; ++ p8PQType[0] = (MS_U8*)&(pCfg->st422_444); ++ p8PQType[1] = (MS_U8*)&(pCfg->stBypass); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ bRet = _MDrv_VIP_SetCMDQStatus(0,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt); ++ if(_MDrv_VIP_For_SetEachPQTypeByIP((MS_U8)PQ_IP_422to444_Main,(MS_U8)PQ_IP_VIP_Main,&pCfg->stFCfg,p8PQType)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_CONFIG); ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ return TRUE; ++} ++void MDrv_VIP_CheckRegister(void) ++{ ++ SCL_ERR( "[MDRVVIP]%s \n", __FUNCTION__); ++ MDRv_PQ_Check_Type(PQ_MAIN_WINDOW,PQ_CHECK_REG); ++ MDrv_VIP_ResetEachIP(); ++ MDRv_PQ_Check_Type(PQ_MAIN_WINDOW,PQ_CHECK_OFF); ++} ++ ++void MDrv_VIP_CheckConsist(void) ++{ ++ SCL_ERR( "[MDRVVIP]%s \n", __FUNCTION__); ++ MDRv_PQ_Check_Type(PQ_MAIN_WINDOW,PQ_CHECK_SIZE); ++ MDrv_VIP_ResetEachIP(); ++ MDRv_PQ_Check_Type(PQ_MAIN_WINDOW,PQ_CHECK_OFF); ++} ++void MDrv_VIP_PrepareStructToCheckRegister(EN_VIP_CMDQ_CHECK_TYPE enCheckType) ++{ ++ EN_VIP_MDRV_AIP_TYPE enIdx; ++ SCL_ERR( "[MDRVVIP]%s CHECK_TYPE:%hhd \n", __FUNCTION__,enCheckType); ++ MDrv_VIP_SetCheckMode(enCheckType); ++ if(_IsAutoSetting()) ++ { ++ _Set_SuspendResetFlag(0x2FFFF); ++ for(enIdx = EN_VIP_MDRV_AIP_YEE;enIdxbfire; ++ u32Addr = pCfg->u32Addr; ++ u16Data = pCfg->u16Data; ++ u16Mask = pCfg->u16Mask; ++ if(bfire) ++ { ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,bfire); ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, fire\n", __FUNCTION__); ++ } ++ else ++ { ++ Drv_CMDQ_FillCmd(&stCfg, u32Addr, u16Data, u16Mask); ++ if(Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s,No frame cmd Write Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ } ++ return TRUE; ++ ++} ++unsigned char MDrv_VIP_SetLDCConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_LDC_CONFIG *pCfg = pvCfg; ++ MS_U8 bRet = 0; ++ if(_IsFrameBufferAllocatedReady()) ++ { ++ MS_U8 *stEn = NULL,*stmd = NULL; ++ stEn = (MS_U8*)&(pCfg->stEn); ++ stmd = (MS_U8*)&(pCfg->stmd); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ if(Drv_VIP_CheckIPMResolution()) ++ { ++ ++ if(_MDrv_VIP_SetCMDQStatus(1,pCfg->stFCfg.bEn,pCfg->stFCfg.u8framecnt)) ++ { ++ _Set_VIPCMDQSetFlag(EN_VIP_MDRV_LDC_CONFIG); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,1); ++ bRet = 1; ++ } ++ _MDrv_VIP_SetPQByType((MS_U8)PQ_IP_LDC_422_444_422_Main,stmd); ++ Drv_VIP_SetLDCBank_Mode((EN_DRV_VIP_LDCLCBANKMODE_TYPE)pCfg->enLDCType); ++ Drv_VIP_SetLDCOnConfig(pCfg->stEn.bEn_ldc); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ ++ } ++ else ++ { ++ SCL_ERR("[MDRVVIP]LDC Resolution Over Spec \n"); ++ } ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_LDC_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldc,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,MCNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++unsigned char MDrv_VIP_SetLDCmdConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_LDC_MD_CONFIG *pCfg = pvCfg; ++ if(_IsFrameBufferAllocatedReady()) ++ { ++ ST_VIP_LDC_MD_CONFIG stLDCCfg; ++ stLDCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stLDCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ stLDCCfg.bEnSWMode = pCfg->bEnSWMode; ++ stLDCCfg.u8FBidx = pCfg->u8FBidx; ++ stLDCCfg.u8FBrwdiff = pCfg->u8FBrwdiff; ++ stLDCCfg.enbypass = (EN_VIP_LDC_BYPASS_Drv_TYPE)pCfg->enbypass; ++ stLDCCfg.enLDCType = (EN_DRV_VIP_LDCLCBANKMODE_TYPE)pCfg->enLDCType; ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(Drv_VIP_SetLDCMdConfig(&stLDCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_LDC_MD_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldcmd,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,MCNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++unsigned char MDrv_VIP_SetLDCDmapConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_LDC_DMAP_CONFIG *pCfg = pvCfg; ++ if(_IsFrameBufferAllocatedReady()) ++ { ++ ST_VIP_LDC_DMAP_CONFIG stLDCCfg; ++ stLDCCfg.bEnPowerSave = pCfg->bEnPowerSave; ++ stLDCCfg.u32DMAPaddr = _Phys2Miu(pCfg->u32DMAPaddr); ++ stLDCCfg.u16DMAPWidth = pCfg->u16DMAPWidth; ++ stLDCCfg.u8DMAPoffset = pCfg->u8DMAPoffset; ++ stLDCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stLDCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(Drv_VIP_SetLDCDmapConfig(&stLDCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_LDC_DMAP_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldcdmap,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,MCNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++unsigned char MDrv_VIP_SetLDCSRAMConfig(void *pvCfg) ++{ ++ ST_MDRV_VIP_LDC_SRAM_CONFIG *pCfg = pvCfg; ++ if(_IsFrameBufferAllocatedReady()) ++ { ++ ST_VIP_LDC_SRAM_CONFIG stLDCCfg; ++ stLDCCfg.u16SRAMhorstr = pCfg->u16SRAMhorstr; ++ stLDCCfg.u16SRAMverstr = pCfg->u16SRAMverstr; ++ stLDCCfg.u32loadhoraddr = _Phys2Miu(pCfg->u32loadhoraddr); ++ stLDCCfg.u32loadveraddr = _Phys2Miu(pCfg->u32loadveraddr); ++ stLDCCfg.u16SRAMhoramount = pCfg->u16SRAMhoramount; ++ stLDCCfg.u16SRAMveramount = pCfg->u16SRAMveramount; ++ stLDCCfg.stFCfg.bEn = pCfg->stFCfg.bEn; ++ stLDCCfg.stFCfg.u8framecnt = pCfg->stFCfg.u8framecnt; ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ ++ if(Drv_VIP_SetLDCSRAMConfig(&stLDCCfg) == 0) ++ { ++ SCL_DBG(SCL_DBG_LV_VIP(), "[MDRVVIP]%s, Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _MDrv_VIP_CopyIPConfigToGlobal(EN_VIP_MDRV_LDC_SRAM_CONFIG,(void *)pCfg); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ SCL_DBG(SCL_DBG_LV_VIP(), ++ "[MDRVVIP]%s,addr:%lx flag:%lx \n", __FUNCTION__,(MS_U32)&gstSupCfg.stldcsram,gstSupCfg.bresetflag); ++ return TRUE; ++ } ++ else ++ { ++ SCL_ERR( "[MDRVVIP]%s,MCNR buffer not alloc \n", __FUNCTION__); ++ return FALSE; ++ } ++} ++ ++MS_BOOL MDrv_VIP_VtrackEnable( unsigned char u8FrameRate, EN_VIP_MDRV_VTRACK_ENABLE_TYPE bEnable) ++{ ++ Drv_VIP_VtrackEnable(u8FrameRate, (EN_VIP_DRVVTRACK_ENABLE_TYPE)bEnable); ++ return 1; ++} ++MS_BOOL MDrv_VIP_VtrackSetPayloadData(unsigned short u16Timecode, unsigned char u8OperatorID) ++{ ++ Drv_VIP_VtrackSetPayloadData(u16Timecode,u8OperatorID); ++ return 1; ++} ++MS_BOOL MDrv_VIP_VtrackSetKey(unsigned char bUserDefinded, unsigned char *pu8Setting) ++{ ++ Drv_VIP_VtrackSetKey(bUserDefinded,pu8Setting); ++ return 1; ++} ++ ++MS_BOOL MDrv_VIP_VtrackSetUserDefindedSetting(unsigned char bUserDefinded, unsigned char *pu8Setting) ++{ ++ Drv_VIP_VtrackSetUserDefindedSetting(bUserDefinded,pu8Setting); ++ return 1; ++} ++MS_BOOL MDrv_VIP_VtrackInit(void) ++{ ++ Drv_VIP_VtrackSetUserDefindedSetting(0,NULL); ++ Drv_VIP_VtrackSetPayloadData(0,0); ++ Drv_VIP_VtrackSetKey(0,NULL); ++ return 1; ++} ++void _MDrv_VIP_AIPSettingDebugMessage ++ (ST_MDRV_VIP_AIP_CONFIG *stCfg,void * pvPQSetParameter,MS_U16 u16StructSize) ++{ ++ unsigned short u16AIPsheet; ++ unsigned char word1,word2; ++ unsigned short u16idx; ++ u16AIPsheet = _GetAIPOffset(stCfg->u16AIPType); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]Sheet:%hd,size:%hd\n",u16AIPsheet,u16StructSize); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]copy addr:%lx,vir addr:%lx\n" ++ ,(unsigned long)pvPQSetParameter,(unsigned long)stCfg->u32Viraddr); ++ if(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG) ++ { ++ for(u16idx =0 ;u16idxu32Viraddr+u16idx); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]idx :%hd, copy value:%hhx,vir value:%hhx\n" ++ ,u16idx,(unsigned char)(word1),(unsigned char)(word2)); ++ } ++ } ++} ++void _MDrv_VIP_AIPSRAMSettingDebugMessage ++ (ST_MDRV_VIP_AIP_SRAM_CONFIG *stCfg,void * pvPQSetParameter,MS_U16 u16StructSize) ++{ ++ unsigned char word1,word2; ++ unsigned short u16idx; ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]%s\n",__FUNCTION__); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]enType:%hd,size:%hd\n",stCfg->enAIPType,u16StructSize); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]copy addr:%lx,vir addr:%lx\n" ++ ,(unsigned long)pvPQSetParameter,(unsigned long)stCfg->u32Viraddr); ++ if(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG) ++ { ++ for(u16idx =0 ;u16idxu32Viraddr+u16idx); ++ SCL_DBG(SCL_DBG_LV_VIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[MDRVVIP]idx :%hd, copy value:%hhx,vir value:%hhx\n" ++ ,u16idx,(unsigned char)(word1),(unsigned char)(word2)); ++ } ++ } ++} ++unsigned char MDrv_VIP_SetAIPConfig(ST_MDRV_VIP_AIP_CONFIG *stCfg) ++{ ++ void * pvPQSetParameter; ++ MS_U16 u16StructSize; ++ unsigned short u16AIPsheet; ++ MS_U8 bRet = 0; ++ MS_U32 u32Events; ++ if(!_Is_AIPBypassFlag(stCfg->u16AIPType)) ++ { ++ u16AIPsheet = _GetAIPOffset(stCfg->u16AIPType); ++ u16StructSize = MDrv_PQ_GetIPRegCount(u16AIPsheet); ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ pvPQSetParameter = (void *) ++ _MDrv_VIP_FillSettingBuffer(u16AIPsheet,stCfg->u32Viraddr,&gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr); ++ if(!pvPQSetParameter) ++ { ++ return 0; ++ } ++ _MDrv_VIP_AIPSettingDebugMessage(stCfg,pvPQSetParameter,u16StructSize); ++ if(stCfg->u16AIPType!=EN_VIP_MDRV_AIP_XNR && ++ stCfg->u16AIPType!=EN_VIP_MDRV_AIP_GM10TO12 && ++ stCfg->u16AIPType!=EN_VIP_MDRV_AIP_GM12TO10 && ++ stCfg->u16AIPType!=EN_VIP_MDRV_AIP_WDR_LOC) ++ { ++ if(_MDrv_VIP_SetCMDQStatus(1,stCfg->stFCfg.bEn,stCfg->stFCfg.u8framecnt)) ++ { ++ _Set_AIPCMDQSetFlag(stCfg->u16AIPType); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,1); ++ bRet = 1; ++ } ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)pvPQSetParameter); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ } ++ else if(stCfg->u16AIPType==EN_VIP_MDRV_AIP_WDR_LOC) ++ { ++ if(WDR_USE_CMDQ()) ++ { ++ if(_MDrv_VIP_SetCMDQStatus(1,stCfg->stFCfg.bEn,stCfg->stFCfg.u8framecnt)) ++ { ++ _Set_AIPCMDQSetFlag(stCfg->u16AIPType); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,1); ++ bRet = 1; ++ } ++ } ++ else ++ { ++ if(!Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,stCfg->stFCfg.bEn,stCfg->stFCfg.u8framecnt,1); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,stCfg->stFCfg.bEn); ++ } ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)pvPQSetParameter); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,bRet); ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ } ++ else if (stCfg->u16AIPType==EN_VIP_MDRV_AIP_XNR) ++ { ++ SCL_DBG(SCL_DBG_LV_IOCTL()&EN_DBGMG_IOCTLEVEL_VIP, "[MDRVVIP]%s @:%lu\n",__FUNCTION__,(MS_U32)MsOS_GetSystemTimeStamp()); ++ if(((MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC)) ++ !=(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC))&&(_IsNotToCheckPQorCMDQmode())) ++ { ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ _MDrv_VIP_SetDAZATaskWork(E_VIP_DAZA_BXNR); ++ } ++ else ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,stCfg->stFCfg.bEn,stCfg->stFCfg.u8framecnt,1); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,stCfg->stFCfg.bEn); ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)pvPQSetParameter); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,stCfg->stFCfg.bEn); ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ } ++ } ++ else if (((stCfg->u16AIPType==EN_VIP_MDRV_AIP_GM10TO12&& !(gbAlreadyOpenGamma&EN_VIP_MDRV_GAMMA_ENABLE_GM10TO12)) ++ ||(stCfg->u16AIPType==EN_VIP_MDRV_AIP_GM12TO10 && !(gbAlreadyOpenGamma&EN_VIP_MDRV_GAMMA_ENABLE_GM12TO10)))&& ++ MDrv_VIP_GetSCLFrameEndCount()<40) ++ { ++ // for hw bug : gamma can't setting in blanking region ++ if(stCfg->u16AIPType==EN_VIP_MDRV_AIP_GM10TO12) ++ { ++ gbAlreadyOpenGamma |= EN_VIP_MDRV_GAMMA_ENABLE_GM10TO12; ++ } ++ else if(stCfg->u16AIPType==EN_VIP_MDRV_AIP_GM12TO10) ++ { ++ gbAlreadyOpenGamma |= EN_VIP_MDRV_GAMMA_ENABLE_GM12TO10; ++ } ++ // for XNR protect ++ if(((MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC)) ++ !=(E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC))&&(_IsNotToCheckPQorCMDQmode())) ++ { ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ if(stCfg->u16AIPType==EN_VIP_MDRV_AIP_GM10TO12) ++ { ++ _MDrv_VIP_SetDAZATaskWork(E_VIP_DAZA_BGMA2C); ++ } ++ else if(stCfg->u16AIPType==EN_VIP_MDRV_AIP_GM12TO10) ++ { ++ _MDrv_VIP_SetDAZATaskWork(E_VIP_DAZA_BGMC2A); ++ } ++ } ++ else ++ { ++ MDRv_PQ_Set_CmdqCfg(PQ_MAIN_WINDOW,stCfg->stFCfg.bEn,stCfg->stFCfg.u8framecnt,1); ++ MDRV_CMDQ_MUTEX_LOCK(EN_CMDQ_TYPE_IP0,stCfg->stFCfg.bEn); ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_SCL0_01_L, BIT3, BIT3); ++ _MDrv_VIP_SetPQByType((MS_U8)u16AIPsheet,(MS_U8 *)pvPQSetParameter); ++ _Drv_CMDQ_WriteRegWithMaskDirect(REG_SCL0_01_L, 0, BIT3); ++ MDRV_CMDQ_MUTEX_UNLOCK(EN_CMDQ_TYPE_IP0,stCfg->stFCfg.bEn); ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ } ++ } ++ else ++ { ++ if(gstSupCfg.staip[stCfg->u16AIPType].u32Viraddr != stCfg->u32Viraddr) ++ { ++ stCfg->u32Viraddr = (unsigned long)pvPQSetParameter; ++ _MDrv_VIP_CopyAIPConfigToGlobal((EN_VIP_MDRV_AIP_TYPE)stCfg->u16AIPType,(void *)stCfg,sizeof(ST_MDRV_VIP_AIP_CONFIG)); ++ } ++ } ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ } ++ else ++ { ++ SCL_DBGERR("[AIP]Bypass AIP:%d\n",stCfg->u16AIPType); ++ } ++ //MsOS_VirMemFree(pvPQSetParameter); ++ return 1; ++} ++ ++MS_U16 _MDrv_VIP_GetSRAMBufferSize(EN_VIP_MDRV_AIP_SRAM_TYPE enAIPType) ++{ ++ MS_U16 u16StructSize; ++ switch(enAIPType) ++ { ++ case EN_VIP_MDRV_AIP_SRAM_GAMMA_Y: ++ u16StructSize = PQ_IP_YUV_Gamma_tblY_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GAMMA_U: ++ u16StructSize = PQ_IP_YUV_Gamma_tblU_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GAMMA_V: ++ u16StructSize = PQ_IP_YUV_Gamma_tblV_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GM10to12_R: ++ u16StructSize = PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GM10to12_G: ++ u16StructSize = PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GM10to12_B: ++ u16StructSize = PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GM12to10_R: ++ u16StructSize = PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GM12to10_G: ++ u16StructSize = PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_GM12to10_B: ++ u16StructSize = PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_SIZE_Main; ++ break; ++ case EN_VIP_MDRV_AIP_SRAM_WDR: ++ u16StructSize = (81*2 *8); ++ break; ++ default: ++ u16StructSize = 0; ++ break; ++ } ++ return u16StructSize; ++} ++ ++unsigned char MDrv_VIP_SetAIPSRAMConfig(ST_MDRV_VIP_AIP_SRAM_CONFIG *stCfg) ++{ ++ void * pvPQSetParameter; ++ void * pvPQSetPara; ++ MS_U16 u16StructSize; ++ EN_VIP_DRV_AIP_SRAM_TYPE enAIPType; ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_LOCK(); ++ } ++ u16StructSize = _MDrv_VIP_GetSRAMBufferSize(stCfg->enAIPType); ++ pvPQSetParameter = MsOS_VirMemalloc(u16StructSize); ++ if(!pvPQSetParameter) ++ { ++ SCL_ERR("[MDRVIP]%s(%d) Init pvPQSetParameter Fail\n", __FUNCTION__, __LINE__); ++ return 0; ++ } ++ MsOS_Memset(pvPQSetParameter,0,u16StructSize); ++ if(MsOS_copy_from_user(pvPQSetParameter, (__user void *)stCfg->u32Viraddr, u16StructSize)) ++ { ++ if((stCfg->u32Viraddr&MIU0Vir_BASE)==MIU0Vir_BASE) ++ { ++ MsOS_Memcpy(pvPQSetParameter, (void *)stCfg->u32Viraddr, u16StructSize); ++ } ++ else ++ { ++ SCL_ERR( "[VIP] copy buffer error\n"); ++ MsOS_VirMemFree(pvPQSetParameter); ++ return 0; ++ } ++ } ++ enAIPType = ((EN_VIP_DRV_AIP_SRAM_TYPE)stCfg->enAIPType); ++ _MDrv_VIP_AIPSRAMSettingDebugMessage(stCfg,pvPQSetParameter,u16StructSize); ++ // NOt need to lock CMDQ ,because hal will do it. ++ pvPQSetPara = Drv_VIP_SetAIPSRAMConfig(pvPQSetParameter,enAIPType); ++ if(pvPQSetPara!=NULL) ++ { ++ MsOS_VirMemFree(pvPQSetPara); ++ } ++ if(_IsNotToCheckPQorCMDQmode()) ++ { ++ MDRV_VIP_MUTEX_UNLOCK(); ++ } ++ return Drv_VIP_GetSRAMCheckPass(); ++} ++ ++unsigned long MDrv_VIP_GetSCLFrameEndCount(void) ++{ ++ ST_SCLIRQ_SCINTS_TYPE *stints; ++ stints = Drv_SCLIRQ_GetSCLInts(); ++ if(stints->u8CountReset) ++ { ++ return 100; ++ } ++ else ++ { ++ return stints->u32SCLMainDoneCount; ++ } ++} ++ ++ssize_t MDrv_VIP_ProcShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ str += MsOS_scnprintf(str, end - str, "Command IP Status\n"); ++ str += MsOS_scnprintf(str, end - str, "----------------------------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, " 0 Normal ALL %s\n",(gu32OpenBypass) ? "No" :"Yes"); ++ str += MsOS_scnprintf(str, end - str, " 1 Bypass ALL %s\n",(gu32OpenBypass==0x7FFFF) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " 2 VIP Bypass %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_CONFIG) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " 3 MCNR %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_MCNR_CONFIG) ? "Bypass" :"ON"); ++ str += MsOS_scnprintf(str, end - str, " 5 NLM %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_NLM_CONFIG) ? "Bypass" :"ON"); ++ str += MsOS_scnprintf(str, end - str, " 6 LDC %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_LDC_CONFIG) ? "Bypass" :"ON"); ++ str += MsOS_scnprintf(str, end - str, "-------------------AIP------------------------\n"); ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " 4 EE %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE].u32Viraddr)+71)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_GLOB].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " 7 WDR GLOB %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_GLOB].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_LOC].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " 8 WDR LOCAL %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_LOC].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_MXNR].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " 9 MXNR %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_MXNR].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_UVADJ].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " A YUVADJ %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_UVADJ].u32Viraddr)+1)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_XNR].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " B XNR %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_XNR].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YCUVM].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " C YCUVM %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YCUVM].u32Viraddr)+0)) ? "Bypass" :"ON"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_COLORTRAN].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " D COLOR TRAN %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_COLORTRAN].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_GAMMA].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " E YUV GAMMA %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_GAMMA].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ str += MsOS_scnprintf(str, end - str, "---------------COLOR ENGINE--------------------\n"); ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YUVTORGB].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " F Y2R %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YUVTORGB].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM10TO12].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " G GM10to12 %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM10TO12].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_CCM].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " H CCM %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_CCM].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_HSV].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " I HSV %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_HSV].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM12TO10].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " J GM12to10 %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM12TO10].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_RGBTOYUV].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " K R2Y %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_RGBTOYUV].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ str += MsOS_scnprintf(str, end - str, "----------------------------------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_VIP_VIPSetRuleShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "========================SCL VIPSetRule======================\n"); ++ str += MsOS_scnprintf(str, end - str, "NOW Rule:%d\n",MsOS_GetVIPSetRule()); ++ str += MsOS_scnprintf(str, end - str, "echo 0 > VIPSetRule :Default (RIU+assCMDQ)\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 1 > VIPSetRule :CMDQ in active (RIU blanking+CMDQ active)\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 2 > VIPSetRule :CMDQ & checking(like 1,but add IST to check)\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 3 > VIPSetRule :ALLCMDQ (Rule 4)\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 4 > VIPSetRule :ALLCMDQ & checking(like 4,but add IST to checkSRAM)\n"); ++ str += MsOS_scnprintf(str, end - str, "echo 5 > VIPSetRule :ALLCMDQ & checking(like 4,but add IST to check)\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL VIPSetRule======================\n"); ++ return (str - buf); ++} ++ ++ssize_t MDrv_VIP_CMDQShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ unsigned long long u64DramMsg; ++ unsigned short u16Count; ++ unsigned short idx,reserve = 0; ++ unsigned char bRotate = 0; ++ MS_CMDQ_Info *stCMDQinfo = Drv_CMDQ_GetCMDQInformation(EN_CMDQ_TYPE_IP0); ++ if(stCMDQinfo->u16WPoint >= stCMDQinfo->u16LPoint) ++ { ++ u16Count = stCMDQinfo->u16WPoint - stCMDQinfo->u16LPoint; ++ } ++ else ++ { ++ u16Count = stCMDQinfo->u16WPoint + stCMDQinfo->u16MaxCmdCnt-stCMDQinfo->u16LPoint; ++ bRotate = 1; ++ } ++ str += MsOS_scnprintf(str, end - str, "========================CMDQ STATUS======================\n"); ++ str += MsOS_scnprintf(str, end - str, "---------------------- SW INFORMATION -------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "CMDQ Current CMD End Pointer :%hd\n",stCMDQinfo->u16WPoint); ++ str += MsOS_scnprintf(str, end - str, "CMDQ Last Time Trigger Pointer :%hd\n",stCMDQinfo->u16RPoint); ++ str += MsOS_scnprintf(str, end - str, "CMDQ Last Time Trigger COUNT :%hd\n",u16Count); ++ str += MsOS_scnprintf(str, end - str, "CMDQ Fire Pointer :%hd\n",stCMDQinfo->u16FPoint); ++ str += MsOS_scnprintf(str, end - str, "---------------------- HW INFORMATION -------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "CMDQ Start :%lx\n",stCMDQinfo->PhyAddr); ++ str += MsOS_scnprintf(str, end - str, "CMDQ End :%lx\n",stCMDQinfo->PhyAddrEnd); ++ str += MsOS_scnprintf(str, end - str, "CMDQ Max CMD One shot :%hu\n",stCMDQinfo->u16MaxCmdCnt); ++ str += MsOS_scnprintf(str, end - str, "---------------------- DRAM INFORMATION -----------------\n"); ++ for(idx=0;idxu16LPoint+idx+1)<=stCMDQinfo->u16MaxCmdCnt) ++ { ++ u64DramMsg = Drv_CMDQ_GetCMDFromPoint(EN_CMDQ_TYPE_IP0,stCMDQinfo->u16LPoint+idx); ++ } ++ else ++ { ++ u64DramMsg = Drv_CMDQ_GetCMDFromPoint(EN_CMDQ_TYPE_IP0,reserve); ++ reserve++; ++ } ++ SCL_DBGERR("%hd:%llx => %lx\n",idx,u64DramMsg,Drv_CMDQ_GetCMDBankFromCMD(u64DramMsg)); ++ //str += MsOS_scnprintf(str, end - str, "%hd:%llx => %lx\n",idx,u64DramMsg,Drv_CMDQ_GetCMDBankFromCMD(u64DramMsg)); ++ } ++ else ++ { ++ u64DramMsg = Drv_CMDQ_GetCMDFromPoint(EN_CMDQ_TYPE_IP0,stCMDQinfo->u16LPoint+idx); ++ ++ SCL_DBGERR("%hd:%llx => %lx\n",idx,u64DramMsg,Drv_CMDQ_GetCMDBankFromCMD(u64DramMsg)); ++ //str += MsOS_scnprintf(str, end - str, "%hd:%llx => %lx\n",idx,u64DramMsg,Drv_CMDQ_GetCMDBankFromCMD(u64DramMsg)); ++ } ++ } ++ str += MsOS_scnprintf(str, end - str, "========================CMDQ STATUS======================\n"); ++ return (str - buf); ++} ++ssize_t MDrv_VIP_VIPShow(char *buf) ++{ ++ char *str = buf; ++ char *end = buf + PAGE_SIZE; ++ str += MsOS_scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ str += MsOS_scnprintf(str, end - str, " IP Status\n"); ++ str += MsOS_scnprintf(str, end - str, "---------------VIP---------------------\n"); ++ str += MsOS_scnprintf(str, end - str, " Normal ALL %s\n",(gu32OpenBypass) ? "No" :"Yes"); ++ str += MsOS_scnprintf(str, end - str, " Bypass ALL %s\n",(gu32OpenBypass==0x7FFFF) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " VIP Bypass %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_CONFIG) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " MCNR %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_MCNR_CONFIG) ? "Bypass" :"ON"); ++ str += MsOS_scnprintf(str, end - str, " NLM %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_NLM_CONFIG) ? "Bypass" :"ON"); ++ str += MsOS_scnprintf(str, end - str, " LDC %s\n", Drv_VIP_GetBypassStatus((EN_VIP_DRV_CONFIG_TYPE)EN_VIP_MDRV_LDC_CONFIG) ? "Bypass" :"ON"); ++ str += MsOS_scnprintf(str, end - str, " ACK %s\n", gstSupCfg.stack.stACK.backen ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " IBC %s\n", gstSupCfg.stibc.stEn.bIBC_en ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " ICC %s\n", gstSupCfg.sticc.stEn.bICC_en ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " IHC %s\n", gstSupCfg.stihc.stOnOff.bIHC_en? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC1 %s\n", gstSupCfg.stfcc.stT[0].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC2 %s\n", gstSupCfg.stfcc.stT[1].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC3 %s\n", gstSupCfg.stfcc.stT[2].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC4 %s\n", gstSupCfg.stfcc.stT[3].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC5 %s\n", gstSupCfg.stfcc.stT[4].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC6 %s\n", gstSupCfg.stfcc.stT[5].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC7 %s\n", gstSupCfg.stfcc.stT[6].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC8 %s\n", gstSupCfg.stfcc.stT[7].bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " FCC9 %s\n", gstSupCfg.stfcc.stT9.bEn ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " UVC %s\n", gstSupCfg.stuvc.stUVC.buvc_en? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " DLC CURVEFITPW %s\n", gstSupCfg.stdlc.stEn.bcurve_fit_var_pw_en? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " DLC CURVEFIT %s\n", gstSupCfg.stdlc.stEn.bcurve_fit_en? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " DLC STATISTIC %s\n", gstSupCfg.stdlc.stEn.bstatistic_en? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " LCE %s\n", gstSupCfg.stlce.stOnOff.bLCE_En ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " PK %s\n", gstSupCfg.stpk.stOnOff.bpost_peaking_en ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, "---------------AIP--------------------\n"); ++ ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " EE %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE].u32Viraddr)+71)) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " EYEE %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE].u32Viraddr)+70)) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " YEE Merge %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE].u32Viraddr)+204)) ? "ON" :"OFF"); ++ } ++ ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE_AC_LUT].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " YC SEC From %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE_AC_LUT].u32Viraddr)+64)==0) ? "YEE" : ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE_AC_LUT].u32Viraddr)+64)==0x1) ? "2DPK" : ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YEE_AC_LUT].u32Viraddr)+64)==0x2) ? "MIX" :"Debug mode" ); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_GLOB].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " WDR GLOB %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_GLOB].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_LOC].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " WDR LOCAL %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_WDR_LOC].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_MXNR].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " MXNR %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_MXNR].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_UVADJ].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " YUVADJ %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_UVADJ].u32Viraddr)+1)) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " UVADJbyY %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_UVADJ].u32Viraddr)+0)) ? "ON" :"OFF"); ++ str += MsOS_scnprintf(str, end - str, " UVADJbyS %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_UVADJ].u32Viraddr)+2)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_XNR].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " XNR %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_XNR].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YCUVM].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " YCUVM %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YCUVM].u32Viraddr)+0)) ? "Bypass" :"ON"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_COLORTRAN].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " COLOR TRAN %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_COLORTRAN].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_GAMMA].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " YUV GAMMA %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_GAMMA].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ str += MsOS_scnprintf(str, end - str, "---------------COLOR ENGINE--------------------\n"); ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_YUVTORGB].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " Y2R %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_YUVTORGB].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM10TO12].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " GM10to12 %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM10TO12].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_CCM].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " CCM %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_CCM].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_HSV].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " HSV %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_HSV].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM12TO10].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " GM12to10 %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_GM12TO10].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ if(gstSupCfg.staip[EN_VIP_MDRV_AIP_RGBTOYUV].u32Viraddr) ++ { ++ str += MsOS_scnprintf(str, end - str, " R2Y %s\n", ++ (*((unsigned char *)(gstSupCfg.staip[EN_VIP_MDRV_AIP_RGBTOYUV].u32Viraddr)+0)) ? "ON" :"OFF"); ++ } ++ str += MsOS_scnprintf(str, end - str, "---------------SRAM--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-1-----------Y GAMMA--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-2-----------U GAMMA--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-3-----------V GAMMA--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-4-----------R GAMMAA2C--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-5-----------G GAMMAA2C--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-6-----------B GAMMAA2C--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-7-----------R GAMMAC2A--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-8-----------G GAMMAC2A--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-9-----------B GAMMAC2A--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "-A-----------WDR--------------------\n"); ++ str += MsOS_scnprintf(str, end - str, "========================SCL VIP STATUS======================\n"); ++ return (str - buf); ++} ++void MDrv_VIP_VIPStore(const char *buf) ++{ ++ const char *str = buf; ++ if(NULL != buf) ++ { ++ if((int)*str == 49) //input 1 echo 1 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GAMMA_Y); ++ } ++ else if((int)*str == 50) //input 2 echo 2 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GAMMA_U); ++ } ++ else if((int)*str == 51) //input 3 echo 3 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GAMMA_V); ++ } ++ else if((int)*str == 52) //input 4 echo 4 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GM10to12_R); ++ } ++ else if((int)*str == 53) //input 5 echo 5 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GM10to12_G); ++ } ++ else if((int)*str == 54) //input 6 echo 6 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GM10to12_B); ++ } ++ else if((int)*str == 55) //input 7 echo 7 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GM12to10_R); ++ } ++ else if((int)*str == 56) //input 8 echo 8 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GM12to10_G); ++ } ++ else if((int)*str == 57) //input 9 echo 9 > ++ { ++ Drv_CMDQ_CheckVIPSRAM(E_SCLIRQ_EVENT_GM12to10_B); ++ } ++ else if((int)*str == 65) //input A echo A > ++ { ++ } ++ ++ } ++} +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/cmdq/drvCMDQ.c b/drivers/mstar/scl/infinity3/src/mxlib/drv/cmdq/drvCMDQ.c +new file mode 100644 +index 00000000..23678246 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/cmdq/drvCMDQ.c +@@ -0,0 +1,1095 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// ++// file drvCMDQ.c ++// @brief CMDQ Driver ++// @author MStar Semiconductor,Inc. ++// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++#define DRV_CMDQ_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsIRQ.h" ++#include "MsOS.h" ++#include "MsVersion.h" ++#include "MsDevice.h" ++ ++//#include ++//#include ++#include "drvvip.h" ++#include "drvCMDQ.h" ++#include "halCMDQ.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "halCHIP.h" ++#include "irqs.h" ++//#include ++#include "mdrv_scl_dbg.h" ++ ++static MS_CMDQ_Info gstCMDQInfo[EN_CMDQ_TYPE_MAX] = {{0,0,0,0,0,FALSE,0,0,NULL}}; ++static MS_U8 gCMDQStatusFlag[EN_CMDQ_TYPE_MAX]; ++static MS_U8 gbCMDQBuferrFull[EN_CMDQ_TYPE_MAX]; ++static CMDQ_Buffer_MIU gstMIUSel[EN_CMDQ_TYPE_MAX]; ++//-------------------------------------------------------------------------------------------------- ++// Global Variable ++//-------------------------------------------------------------------------------------------------- ++static MS_U32 gu32CMDQMode; ++static EN_CMDQ_IP_TYPE gstCurrworkIP; ++static MS_U32 gu32LasttimeFramecnt;//1.last time isp cnt ++MS_BOOL gbISRopen; ++MS_U16 gu16ISRflag; ++MS_S32 _gCMDQHVSPMUTEX[EN_CMDQ_TYPE_MAX] = {-1,-1,-1}; ++static MS_S32 _gs32CMDQMutex = -1; ++#define CMDQ_MUTEX_CREATE() _gs32CMDQMutex = MsOS_CreateMutex(E_MSOS_FIFO, "CMDQMUTEX" , MSOS_PROCESS_SHARED) ++#define CMDQ_MUTEX_LOCK() MsOS_ObtainMutex(_gs32CMDQMutex,MSOS_WAIT_FOREVER) ++#define CMDQ_MUTEX_UNLOCK() MsOS_ReleaseMutex(_gs32CMDQMutex) ++#define CMDQ_MUTEX_DELETE() MsOS_DeleteMutex(_gs32CMDQMutex) ++#define _AlignTo(value, align) ( ((value) + ((align)-1)) & ~((align)-1) ) ++#define _CMDQGetAddr(u16Point) (gstCMDQInfo[gstCurrworkIP].u32VirAddr + ((u16Point)* MS_CMDQ_CMD_LEN) ) ++#define _CMDQGetCMD(u8type,u32Addr,u16Data,u16Mask) ((MS_U64)(((MS_U64)(u8type)<<(14*4))|((MS_U64)(u32Addr)<<(8*4))|\ ++ ((MS_U64)(u16Data)<<(4*4))|((MS_U64)(u16Mask)))) ++#define _IsIspCountReset(u8isp_cnt,u8framecnt) (((gu32LasttimeFramecnt)>(u8isp_cnt))&&\ ++ ((gu32LasttimeFramecnt)>(u8framecnt))) ++#define _IsAssignCountReset(u8isp_cnt,u8framecnt) ((u8framecnt=(u8framecnt))) ++#define _IsFrameCountError(u8isp_cnt,u8framecnt,u8allowframeerror) (((MS_S16)u8isp_cnt)>(MS_S16)((u8framecnt)+(u8allowframeerror)))\ ++ &&((u8isp_cnt-u8framecnt)<10) ++#define _IsFrameCountWarn(u8isp_cnt,u8framecnt,u8allowframeerror) (((MS_S16)(u8isp_cnt)-(MS_S16)(u8framecnt))>=0&&\ ++ ((MS_S16)(u8isp_cnt)-(MS_S16)(u8framecnt))<=(u8allowframeerror)) ++#define _IsCMDQExecuteDone(enIPType) (Hal_CMDQ_GetFinalIrq(enIPType, 0x0003)==0x3 && Hal_CMDQ_GetRawIrq(enIPType, 0x0800)) ++#define _IsCMDQExecuteDoneISR(enIPType) (((gu16ISRflag&0x4) == 0x4) && Hal_CMDQ_GetRawIrq(enIPType, 0x0800)) ++#define _IsCMDQIPIdle(enIPType) (Hal_CMDQ_GetRawIrq(enIPType, 0x0800)) ++#define _IsCMDQDMADone(enIPType) (Hal_CMDQ_GetRawIrq(enIPType, 0x0002)) ++#define _IsCMDQFlagType(IpNum,u8type) (gCMDQStatusFlag[IpNum] & (u8type)) ++#define _SetCMDQFlagType(IpNum,u8type) (gCMDQStatusFlag[IpNum] |= (u8type)) ++#define _ReSetCMDQFlagType(IpNum,u8type) (gCMDQStatusFlag[IpNum] &= ~(u8type)) ++#define _IsThisCmdAddrAlreadyExist(u32addr,u64cpcmd) (u32addr==((MS_U32)((u64cpcmd &0xFFFFFFFF00000000)>>32))) ++#define _IsIdxLargeThan(u32ShiftIdx,u16Num) (u32ShiftIdx>u16Num) ++//-------------------------------------------------------------------------------------------------- ++// Debug Function ++//-------------------------------------------------------------------------------------------------- ++#define CMDQDBG(x) ++#define CMDQERR(x) x ++#define CMDQCMD128 0 //one cmd 64bit but add one null cmd ++#define NotToCheckSameAddr 1 ++#define ToCheckSameAddr 0 ++#define RETURN_ERROR 2 ++#define CheckingTimes 35 ++//#define INT_IRQ_CMDQ 52 ++//-------------------------------------------------------------------------------------------------- ++// Global Function ++//-------------------------------------------------------------------------------------------------- ++ ++//--------------------------------------------------------------------------- ++///Get MMIO_Base and set struct _REG_CMDQCtrl * _CMDQCtrl ++//--------------------------------------------------------------------------- ++void Drv_CMDQ_SetForceSkip(bool bEn) ++{ ++} ++ ++ ++//DRV----------------------------------------------------------------------------------------------- ++MS_U32 _Drv_CMDQ_SetRingTrigPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr) ++{ ++ Hal_CMDQ_SetOffsetPointer(enIPType,StartAddr); ++ return 1; ++} ++ ++MS_U32 _Drv_CMDQ_SetStartPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr) ++{ ++ Hal_CMDQ_SetStartPointer(enIPType,StartAddr); ++ return DRVCMDQ_OK; ++} ++ ++MS_U32 _Drv_CMDQ_SetEndPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 EndAddr) ++{ ++ Hal_CMDQ_SetEndPointer(enIPType,EndAddr); ++ return DRVCMDQ_OK; ++} ++ ++MS_U32 _Drv_CMDQ_SetTimerRatio(EN_CMDQ_IP_TYPE enIPType,MS_U32 u32time,MS_U32 u32ratio) ++{ ++ Hal_CMDQ_SetTimer(enIPType, u32time); ++ Hal_CMDQ_SetRatio(enIPType, u32ratio); ++ return DRVCMDQ_OK; ++} ++MS_U64 *_Drv_CMDQ_GetPointerFromPoint(MS_U16 u16Point,MS_U64 *pu32Addr) ++{ ++ MS_PHYADDR DstAddr; ++ DstAddr = _CMDQGetAddr(u16Point); ++ pu32Addr = (MS_U64 *)(DstAddr); ++ return pu32Addr; ++} ++void _Drv_CMDQ_SetCmdToPointer(MS_U64 u64Cmd ,MS_BOOL bSkipCheckSameAddr,MS_U64 *pu32Addr) ++{ ++ if(!bSkipCheckSameAddr) ++ { ++ *pu32Addr = ((u64Cmd &0xFFFFFFFFFFFF0000)|0x0000); ++ } ++ else ++ { ++ *pu32Addr =u64Cmd ; ++ } ++} ++MS_BOOL _Drv_CMDQ_AddCmd(MS_U64 u64Cmd ,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_U64 *pu32Addr = NULL; ++ if(gbCMDQBuferrFull[gstCurrworkIP]) ++ { ++ return 0; ++ } ++ pu32Addr = _Drv_CMDQ_GetPointerFromPoint(gstCMDQInfo[gstCurrworkIP].u16WPoint,pu32Addr); ++ _Drv_CMDQ_SetCmdToPointer(u64Cmd,bSkipCheckSameAddr,pu32Addr); ++ gstCMDQInfo[gstCurrworkIP].u16WPoint++; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]add u16WPoint=%d \n" ++ ,gstCMDQInfo[gstCurrworkIP].u16WPoint); ++ if( ((gstCMDQInfo[gstCurrworkIP].u16WPoint)) ==((gstCMDQInfo[gstCurrworkIP].u16DPoint))) ++ { ++ gbCMDQBuferrFull[gstCurrworkIP] = 1; ++ SCL_ERR("[CMDQ]CMDQ BUFFER FULL @:%lu\n",((MS_U32)MsOS_GetSystemTimeStamp())); ++ SCL_ERR("[CMDQ]add u16DPoint=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[gstCurrworkIP].u16DPoint,gstCMDQInfo[gstCurrworkIP].u16WPoint); ++ } ++ gu32LasttimeFramecnt++; ++ return 1; ++} ++ ++void _Drv_CMDQ_ResetCmdPointIfBottom(EN_CMDQ_IP_TYPE enIPType) ++{ ++ if(gstCMDQInfo[enIPType].u16WPoint >= gstCMDQInfo[enIPType].u16MaxCmdCnt) ++ { ++ gstCMDQInfo[enIPType].u16WPoint = 0; ++ //SCL_DBGERR("[CMDQ]CMDQ BUFFER ResetCmdPoint @:%lu\n",((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++} ++void _Drv_CMDQ_AddNull(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U64 nullcmd = MS_CMDQ_NULL_CMD; ++ do ++ { ++ _Drv_CMDQ_AddCmd((MS_U64)nullcmd, ToCheckSameAddr); ++ _Drv_CMDQ_ResetCmdPointIfBottom(enIPType); ++ }while (gstCMDQInfo[enIPType].u16WPoint%MS_CMDQ_CMD_ALIGN != 0); ++} ++ ++void _Drv_CMDQ_WriteRegDirect(MS_U32 u32Addr,MS_U16 u16Data) ++{ ++ Hal_CMDQ_WriteRegDirect(u32Addr,u16Data); ++} ++ ++MS_U32 _Drv_CMDQ_PrintfCrashCommand(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 Command_15_0_bit, Command_31_16_bit, Command_55_32_bit, Command_63_56_bit,read_addr; ++ Command_15_0_bit = Hal_CMDQ_ErrorCommand(enIPType,CMDQ_CRASH_15_0_BIT); ++ Command_31_16_bit = Hal_CMDQ_ErrorCommand(enIPType,CMDQ_CRASH_31_16_BIT); ++ Command_55_32_bit = Hal_CMDQ_ErrorCommand(enIPType,CMDQ_CRASH_55_32_BIT); ++ Command_63_56_bit = Hal_CMDQ_ErrorCommand(enIPType,CMDQ_CRASH_63_56_BIT); ++ read_addr = Hal_CMDQ_GetMIUReadAddr(enIPType); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]\033[35mCommand _bits: %lx, %lx, %lx, %lx read_addr: %lx\033[m\n" ++ , Command_63_56_bit, Command_55_32_bit, Command_31_16_bit, Command_15_0_bit,read_addr); ++ return DRVCMDQ_OK; ++} ++MS_U32 Drv_CMDQ_BeTrigger(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart) ++{ ++ if(bStart) ++ { ++ Hal_CMDQ_Enable(enIPType,bStart); ++ Hal_CMDQ_Start(enIPType,bStart); ++ _Drv_CMDQ_PrintfCrashCommand(enIPType); ++ Drv_CMDQ_SetDPoint(enIPType); ++ return DRVCMDQ_OK; ++ } ++ else ++ { ++ CMDQERR(printf("bStart %d, \n",bStart)); ++ return DRVCMDQ_FAIL; ++ } ++} ++void _Drv_CMDQ_CheckMIUAddr(void) ++{ ++ MS_U64 *pu32Addr = NULL; ++ #if CMDQCMD128 ++ pu32Addr = _Drv_CMDQ_GetPointerFromPoint((gstCMDQInfo[gstCurrworkIP].u16WPoint -2),pu32Addr); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ] WP:%hd MIU:%llx" ++ ,gstCMDQInfo[gstCurrworkIP].u16WPoint -2,*pu32Addr); ++ #else ++ pu32Addr = _Drv_CMDQ_GetPointerFromPoint((gstCMDQInfo[gstCurrworkIP].u16WPoint -1),pu32Addr); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ] WP:%hd MIU:%llx" ++ ,gstCMDQInfo[gstCurrworkIP].u16WPoint -1,*pu32Addr); ++ #endif ++} ++void Drv_CMDQ_SetRPoint(EN_CMDQ_IP_TYPE enIPType) ++{ ++ gstCMDQInfo[enIPType].u16RPoint = ++ (gstCMDQInfo[enIPType].u16FPoint>0)? (gstCMDQInfo[enIPType].u16FPoint-1): gstCMDQInfo[enIPType].u16MaxCmdCnt; ++} ++void Drv_CMDQ_SetDPoint(EN_CMDQ_IP_TYPE enIPType) ++{ ++ gstCMDQInfo[enIPType].u16DPoint = ++ (gstCMDQInfo[enIPType].u16FPoint>0)? (gstCMDQInfo[enIPType].u16FPoint-1): gstCMDQInfo[enIPType].u16MaxCmdCnt; ++} ++void Drv_CMDQ_SetLPoint(EN_CMDQ_IP_TYPE enIPType) ++{ ++ static MS_U16 u16lp=0; ++ gstCMDQInfo[enIPType].u16LPoint = u16lp; ++ u16lp = gstCMDQInfo[enIPType].u16DPoint; ++ _Drv_CMDQ_PrintfCrashCommand(enIPType); ++} ++MS_U32 _Drv_CMDQ_GetEndCmdAddr(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 u32EndAddr = 0; ++ gstCMDQInfo[enIPType].u16FPoint = gstCMDQInfo[enIPType].u16WPoint + 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]u16WPoint=%u u16RPoint=%u u16DPoint=%u\n", ++ gstCMDQInfo[enIPType].u16WPoint,gstCMDQInfo[enIPType].u16RPoint,gstCMDQInfo[enIPType].u16DPoint); ++ ++ u32EndAddr = gstCMDQInfo[enIPType].PhyAddr+ ++ (((gstCMDQInfo[enIPType].u16FPoint)/MS_CMDQ_CMD_ALIGN)*MS_CMDQ_MEM_BASE_UNIT); ++ return u32EndAddr; ++} ++void _Drv_CMDQ_ReSetBuferrFull(EN_CMDQ_IP_TYPE enIPType) ++{ ++ gbCMDQBuferrFull[enIPType] = 0; ++} ++void _Drv_CMDQ_FillInitIPInfo ++ (EN_CMDQ_IP_TYPE enIPType,MS_PHYADDR IP0PhyAddr, MS_U32 u32IP0VirAddr, MS_U32 u32CMDQBufSize) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]PhyAddr:%lx u32VirAddr:%lx \n",IP0PhyAddr,u32IP0VirAddr); ++ gstCMDQInfo[enIPType].bEnable = FALSE; ++ gstCMDQInfo[enIPType].u16RPoint = 0; //last trig ++ gstCMDQInfo[enIPType].u16DPoint = 0; //last done ++ gstCMDQInfo[enIPType].u16WPoint = 0; //current cmd end ++ gstCMDQInfo[enIPType].u16FPoint = 0; //fire point (128 bit/unit) ++ gstCMDQInfo[enIPType].u16MaxCmdCnt = (MS_U16)(u32CMDQBufSize / MS_CMDQ_CMD_LEN); ++ gstCMDQInfo[enIPType].PhyAddr = IP0PhyAddr; ++ gstCMDQInfo[enIPType].u32VirAddr = u32IP0VirAddr; ++ gstCMDQInfo[enIPType].PhyAddrEnd = IP0PhyAddr+ ++ (gstCMDQInfo[enIPType].u16MaxCmdCnt/2)*MS_CMDQ_MEM_BASE_UNIT; ++ gCMDQStatusFlag[enIPType] = (CMDQ_FLAG_FIRE); ++ gbCMDQBuferrFull[enIPType] = 0; ++} ++void _Drv_CMDQ_Init(MS_U32 phyAddr1) ++{ ++ if (phyAddr1 >= HAL_MIU1_BASE) ++ { ++ gstMIUSel[0].u8MIUSel_IP = EN_CMDQ_MIU_1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]%s: Init BF1 at MIU 1\n" ++ ,__FUNCTION__); ++ } ++ else ++ { ++ gstMIUSel[0].u8MIUSel_IP = EN_CMDQ_MIU_0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]%s: Init BF1 at MIU 0 \n" ++ ,__FUNCTION__); ++ } ++ gu32CMDQMode = RING_BUFFER_MODE; ++ gu32LasttimeFramecnt = 0; ++ gstCurrworkIP = EN_CMDQ_TYPE_IP0; ++} ++void _Drv_CMDQ_Reset(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 u32CMDQBufSize = ++ (gstCMDQInfo[enIPType].u16MaxCmdCnt)*MS_CMDQ_CMD_LEN; ++ _Drv_CMDQ_FillInitIPInfo(enIPType, gstCMDQInfo[enIPType].PhyAddr, ++ gstCMDQInfo[enIPType].u32VirAddr,u32CMDQBufSize); ++ Drv_CMDQ_Enable(1,enIPType); ++ _Drv_CMDQ_Init(gstCMDQInfo[enIPType].PhyAddr); ++ Hal_CMDQ_Reset(enIPType, ENABLE); ++ Hal_CMDQ_Reset(enIPType, DISABLE); ++ _Drv_CMDQ_AddNull(enIPType);//add 2 null ++ gstCMDQInfo[enIPType].u16FPoint = gstCMDQInfo[enIPType].u16WPoint + 1; ++} ++MS_BOOL _Drv_CMDQ_Fire(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart) ++{ ++ MS_U32 u32EndAddr = 0; ++ MS_U8 ret=0; ++ MS_U32 u32Events=0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW,"[CMDQ]%s count:%ld\n",__FUNCTION__,gu32LasttimeFramecnt); ++ if(gbCMDQBuferrFull[enIPType]) ++ { ++ gstCMDQInfo[enIPType].u16WPoint = gstCMDQInfo[enIPType].u16RPoint; ++ ret=0; ++ } ++ else ++ { ++ gu32LasttimeFramecnt = 0; ++ u32EndAddr = _Drv_CMDQ_GetEndCmdAddr(enIPType); ++ ret =_Drv_CMDQ_SetRingTrigPointer(enIPType,u32EndAddr); //in function,addr already add 1 ++ } ++ if(ret) ++ { ++ //MsOS_ChipFlushCacheRange(gstCMDQInfo[enIPType].u32VirAddr,(gstCMDQInfo[enIPType].u16MaxCmdCnt*MS_CMDQ_CMD_LEN)); ++ MsOS_WaitForCPUWriteToDMem(); ++ _Drv_CMDQ_CheckMIUAddr(); ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),E_SCLIRQ_EVENT_CMDQ); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_CMDQFIRE); ++ //_Drv_CMDQ_BeTrigger(enIPType,bStart); ++ Drv_CMDQ_SetRPoint(enIPType); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]go CMDQ u32EndAddr:%lx\n",u32EndAddr); ++ } ++ else ++ { ++ CMDQERR(printf("[CMDQ]Block Fire for CMDQ FULL!!!\n")); ++ if(MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ E_SCLIRQ_EVENT_CMDQDONE, &u32Events, E_OR, 1000)) ++ { ++ _Drv_CMDQ_ReSetBuferrFull(enIPType); ++ } ++ else ++ { ++ _Drv_CMDQ_Reset(enIPType); ++ _Drv_CMDQ_ReSetBuferrFull(enIPType); ++ CMDQERR(printf("[CMDQ]Reset CMDQ!!!\n")); ++ } ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++MS_U8 _Drv_CMDQ_SetBufferConfig(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr, MS_U32 EndAddr) ++{ ++ MS_U8 ret,ret2; ++ ret = _Drv_CMDQ_SetStartPointer(enIPType,StartAddr); ++ ret2 = _Drv_CMDQ_SetEndPointer(enIPType,EndAddr); ++ _Drv_CMDQ_SetRingTrigPointer(enIPType,StartAddr); ++ if((ret==DRVCMDQ_OK)&&(ret2==DRVCMDQ_OK)) ++ return 1; ++ else ++ return 0; ++} ++void _Drv_CMDQ_initSCtopIRQ(void) ++{ ++ Hal_CMDQ_WriteRegDirect(0x12183C,0xFFFF);//clear sctop irq ++ Hal_CMDQ_WriteRegDirect(0x121838,0xFFFD);//mask ++} ++MS_U32 _Drv_CMDQ_InitByIP(EN_CMDQ_IP_TYPE enIPType) ++{ ++ char word[] = {"_CMDQ_Mutex"}; ++ char word1[] = {"_CMDQ1_Mutex"}; ++ char word2[] = {"_CMDQ2_Mutex"}; ++ Hal_CMDQ_Setmiusel(enIPType, gstMIUSel[enIPType].u8MIUSel_IP); ++ _Drv_CMDQ_AddNull(enIPType);//add 2 null ++ gstCMDQInfo[enIPType].u16FPoint = gstCMDQInfo[enIPType].u16WPoint + 1; ++ Hal_CMDQ_SetBaseEn(enIPType, ENABLE); ++ Hal_CMDQ_SetTrigAlways(enIPType, ENABLE); ++ Hal_CMDQ_Reset(enIPType, ENABLE); ++ Hal_CMDQ_Reset(enIPType, DISABLE); ++ ++ if(FALSE == Hal_CMDQ_SetDMAMode(enIPType, gu32CMDQMode)) ++ { ++ CMDQERR(printf("[CMDQ]\033[35mCMDQ Set Mode FAIL!!\033[m\n")); ++ return DRVCMDQ_FAIL; ++ } ++ ++ /* the polling_timer is for re-checking polling value, ++ if the time_interval is too small, cmdq will polling RIU frequently, so that RIU will very busy */ ++ _Drv_CMDQ_SetTimerRatio(enIPType, CMDQ_poll_timer, CMDQ_timer_ratio); ++ // set time / ratio, total wait time is (wait_time * (ratio + 1)) => ( FF * (F + 1) / 216 MHz ) = sec ++ //4D*1=4D~=77 *(216/M) 1 ~=60(frame/s) ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(enIPType, 0); ++ _Drv_CMDQ_SetBufferConfig(enIPType, gstCMDQInfo[enIPType].PhyAddr,gstCMDQInfo[enIPType].PhyAddrEnd); ++ _Drv_CMDQ_initSCtopIRQ(); ++ Hal_CMDQ_ResetSoftInterrupt(enIPType); ++ Hal_CMDQ_SetISRMSK(enIPType,0xE0F8); ++ Hal_CMDQ_SetRegPassWaitPoll(enIPType,1); ++ _gCMDQHVSPMUTEX[enIPType] = MsOS_CreateMutex(E_MSOS_FIFO, ++ (enIPType==EN_CMDQ_TYPE_IP0) ? word : (enIPType==EN_CMDQ_TYPE_IP1) ? word1 : word2, MSOS_PROCESS_SHARED); ++ if (_gCMDQHVSPMUTEX[enIPType] == -1) ++ { ++ CMDQERR(printf("%s: Init MUTEX fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++//--------------------------- irq ++ return DRVCMDQ_OK; ++} ++//function----------------------------------------------------------------------------- ++MS_BOOL _Drv_CMDQ_FillCheckCmdInfo(MS_U64 u64Cmd,CMDQ_CheckCmdinfo *stCMDQChkinfo) ++{ ++ stCMDQChkinfo->Ret = 0; ++ stCMDQChkinfo->u32addr = (MS_U32)((u64Cmd &0xFFFFFFFF00000000)>>32); ++ stCMDQChkinfo->u16mask = (MS_U16)(u64Cmd &0xFFFF); ++ stCMDQChkinfo->u16data = (MS_U16)((u64Cmd>>16) &0xFFFF); ++ stCMDQChkinfo->u16StartPoint = gstCMDQInfo[gstCurrworkIP].u16DPoint; ++ if(gstCMDQInfo[gstCurrworkIP].u16WPoint>0) ++ { ++ stCMDQChkinfo->u16EndPoint = gstCMDQInfo[gstCurrworkIP].u16WPoint-1;//for read last time cmd ++ } ++ else ++ { ++ stCMDQChkinfo->u16EndPoint = gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt-1; ++ } ++ ++ if (stCMDQChkinfo->u16EndPoint+1==stCMDQChkinfo->u16StartPoint) ++ { ++ stCMDQChkinfo->Ret = 1; ++ return stCMDQChkinfo->Ret; ++ } ++ ++ if(stCMDQChkinfo->u16EndPoint+1>=stCMDQChkinfo->u16StartPoint) ++ { ++ stCMDQChkinfo->u32CmdDiffCnt = stCMDQChkinfo->u16EndPoint+1-stCMDQChkinfo->u16StartPoint; ++ } ++ else //ring ++ { ++ stCMDQChkinfo->u32CmdDiffCnt = ++ stCMDQChkinfo->u16EndPoint+1+(gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt-stCMDQChkinfo->u16StartPoint); ++ } ++ ++ return stCMDQChkinfo->Ret; ++} ++MS_U16 _Drv_CMDQ_GetCurrentCmdPoint(CMDQ_CheckCmdinfo *stCMDQChkinfo, MS_U32 u32ShiftIdx) ++{ ++ MS_U16 u16CurrentPoint; ++ MS_U16 u16Temp; ++ if(((stCMDQChkinfo->u16EndPoint+1)>=stCMDQChkinfo->u16StartPoint)) ++ { ++ u16CurrentPoint = (stCMDQChkinfo->u16EndPoint-u32ShiftIdx); ++ } ++ else if(((stCMDQChkinfo->u16EndPoint+1)u16StartPoint)) ++ { ++ if((stCMDQChkinfo->u16EndPoint)>=u32ShiftIdx)//top ++ { ++ u16CurrentPoint = (stCMDQChkinfo->u16EndPoint-u32ShiftIdx); ++ } ++ else//bottom ++ { ++ u16Temp = u32ShiftIdx-stCMDQChkinfo->u16EndPoint; ++ u16CurrentPoint = (gstCMDQInfo[gstCurrworkIP].u16MaxCmdCnt-u16Temp); ++ } ++ } ++ else ++ { ++ u16CurrentPoint = (stCMDQChkinfo->u16EndPoint-u32ShiftIdx); ++ } ++ return u16CurrentPoint; ++} ++MS_BOOL _Drv_CMDQ_CheckingAlreadyExist(CMDQ_CheckCmdinfo *stCMDQChkinfo) ++{ ++ MS_U64 u64ExistedCmd; ++ MS_U16 u16ExistCmdData; ++ MS_U32 u32ShiftIdx; ++ MS_U16 u16CurrentPoint; ++ for(u32ShiftIdx = 0;u32ShiftIdxu32CmdDiffCnt;u32ShiftIdx++) ++ { ++ //doing ++ u16CurrentPoint = _Drv_CMDQ_GetCurrentCmdPoint(stCMDQChkinfo,u32ShiftIdx); ++ stCMDQChkinfo->pu32Addr = _Drv_CMDQ_GetPointerFromPoint(u16CurrentPoint,stCMDQChkinfo->pu32Addr); ++ u64ExistedCmd = *stCMDQChkinfo->pu32Addr; ++ if(_IsThisCmdAddrAlreadyExist(stCMDQChkinfo->u32addr,u64ExistedCmd)) ++ { ++ //there is same address ++ u16ExistCmdData = (MS_U16)((u64ExistedCmd>>16) &0xFFFF); ++ u16ExistCmdData = ((u16ExistCmdData&stCMDQChkinfo->u16mask) | (~stCMDQChkinfo->u16mask&stCMDQChkinfo->u16data)); ++ u64ExistedCmd = ((u64ExistedCmd &0xFFFFFFFF00000000)|((MS_U32)u16ExistCmdData<<16)|0x0000); ++ if( _IsIdxLargeThan(u32ShiftIdx,10)) // TO avoid this cmd too far away next cmd. ++ { ++ _Drv_CMDQ_AddCmd(u64ExistedCmd,0); ++#if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++#endif ++ *stCMDQChkinfo->pu32Addr = MS_CMDQ_NULL_CMD; ++ } ++ else ++ { ++ *stCMDQChkinfo->pu32Addr = u64ExistedCmd; ++ } ++ stCMDQChkinfo->Ret = 0; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]find cmd same address %lx\n" ++ ,stCMDQChkinfo->u32addr); ++ break; ++ } ++#if CMDQCMD128 ++ else if(_IsIdxLargeThan(u32ShiftIdx,CheckingTimes*2)) ++ { ++ stCMDQChkinfo->Ret = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]check over 20\n"); ++ break; ++ } ++#else ++ else if(_IsIdxLargeThan(u32ShiftIdx,CheckingTimes)) ++ { ++ stCMDQChkinfo->Ret = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]check over 10\n"); ++ break; ++ } ++#endif ++ else ++ { ++ stCMDQChkinfo->Ret = 1; ++ } ++ ++ } ++ return stCMDQChkinfo->Ret; ++} ++MS_BOOL _Drv_CMDQ_CheckAddedCmdSameRegPos(MS_U64 u64Cmd,MS_BOOL bSkipCheckSameAddr) ++{ ++ CMDQ_CheckCmdinfo stCMDQChkinfo; ++ MsOS_Memset(&stCMDQChkinfo,0,sizeof(CMDQ_CheckCmdinfo)); ++ if (bSkipCheckSameAddr) ++ { ++ stCMDQChkinfo.Ret = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]bSkipCheckSameAddr check cmd repeat:%hhx\n" ++ ,bSkipCheckSameAddr); ++ return stCMDQChkinfo.Ret; ++ } ++ _Drv_CMDQ_FillCheckCmdInfo(u64Cmd,&stCMDQChkinfo); ++ if(stCMDQChkinfo.Ret) ++ { ++ return stCMDQChkinfo.Ret; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_HIGH,"[CMDQ]u16EndPoint:%hd u16StartPoint:%hd u32CmdDiffCnt:%ld\n" ++ ,stCMDQChkinfo.u16EndPoint,stCMDQChkinfo.u16StartPoint,stCMDQChkinfo.u32CmdDiffCnt); ++ //checking ++ stCMDQChkinfo.Ret = _Drv_CMDQ_CheckingAlreadyExist(&stCMDQChkinfo); ++ return stCMDQChkinfo.Ret; ++} ++ ++MS_BOOL _Drv_CMDQ_BufferEmpty(EN_CMDQ_IP_TYPE eCMDQBuf) ++{ ++ if((gstCMDQInfo[eCMDQBuf].u16WPoint == gstCMDQInfo[eCMDQBuf].u16RPoint) && ++ (gstCMDQInfo[eCMDQBuf].u16WPoint == gstCMDQInfo[eCMDQBuf].u16FPoint)) ++ return TRUE; ++ else ++ return FALSE; ++} ++MS_BOOL _Drv_CMDQ_WriteCmd(MS_U64 u64Cmd,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_BOOL bRet = 0; ++ MS_U16 u16DummyCmdIdx; ++ EN_CMDQ_IP_TYPE enCMDQIP = gstCurrworkIP; ++ CMDQDBG(printf("[CMDQ] u64Cmd:%llx\n",u64Cmd)); ++ if( _Drv_CMDQ_BufferEmpty(enCMDQIP) ) ++ { ++ CMDQERR(printf("[CMDQ] buffer empty init\n")); ++ gstCMDQInfo[enCMDQIP].u16RPoint = 0; ++ gstCMDQInfo[enCMDQIP].u16WPoint = 0; ++ gstCMDQInfo[enCMDQIP].u16FPoint = 0; ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ bRet = TRUE; ++ } ++ else ++ { ++ ++ u16DummyCmdIdx=(gstCMDQInfo[enCMDQIP].u16WPoint/2+1)*2; ++ if(u16DummyCmdIdx < gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//med ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,bSkipCheckSameAddr)) ++ { ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ #endif ++ } ++ bRet = TRUE; ++ } ++ else if(u16DummyCmdIdx == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last ++ { ++ if(gstCMDQInfo[enCMDQIP].u16WPoint+1 < gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last+2 ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,bSkipCheckSameAddr)) ++ { ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ #endif ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]FC last+2 u16MaxCmdCnt=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16MaxCmdCnt,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ bRet = TRUE; ++ } ++ else if(gstCMDQInfo[enCMDQIP].u16WPoint+1 == gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last+1 ++ { ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,bSkipCheckSameAddr)) ++ { ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, ++ "[CMDQ]FC last+1 u16MaxCmdCnt=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16MaxCmdCnt,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ _Drv_CMDQ_ResetCmdPointIfBottom(enCMDQIP); ++ bRet = TRUE; ++ } ++ ++ } ++ else if(u16DummyCmdIdx > gstCMDQInfo[enCMDQIP].u16MaxCmdCnt)//last ++ { ++ _Drv_CMDQ_ResetCmdPointIfBottom(enCMDQIP); ++ if(_Drv_CMDQ_CheckAddedCmdSameRegPos(u64Cmd,bSkipCheckSameAddr)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ] frame cnt buffer full -->reset\n"); ++ _Drv_CMDQ_AddCmd(u64Cmd,bSkipCheckSameAddr); ++ #if CMDQCMD128 ++ _Drv_CMDQ_AddNull(gstCurrworkIP); ++ #endif ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]FC last u16MaxCmdCnt=%d u16WPoint=%d\n" ++ ,gstCMDQInfo[enCMDQIP].u16MaxCmdCnt,gstCMDQInfo[enCMDQIP].u16WPoint); ++ } ++ bRet = TRUE; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ ++ ++ } ++ return bRet; ++} ++MS_U64 _Drv_CMDQ_GetCmd(MS_U8 u8type,MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask) ++{ ++ MS_U16 u16Bank; ++ MS_U8 u8addr; ++ MS_CMDQ_CMD data; ++ u16Bank = (MS_U16)((u32Addr >> 8) & 0xFFFF); ++ u8addr = (MS_U8)((u32Addr & 0xFF) ); ++ if(u8addr%2) //Hbyte ++ { ++ data.u16Mask=~(u16Mask<<8); ++ data.u16Data = (Hal_CMDQ_Read2ByteReg(u32Addr-1) & ~(u16Mask<<8)) | ((u16Data & u16Mask)<<8); ++ } ++ else ++ { ++ data.u16Mask=~(u16Mask); ++ if( u16Mask == 0xFFFF ) ++ { ++ data.u16Data = u16Data; ++ } ++ else ++ { ++ data.u16Data = (Hal_CMDQ_Read2ByteReg(u32Addr) & ~u16Mask) | (u16Data & u16Mask); ++ } ++ } ++ ++ data.u8type = u8type; ++ data.u32Addr =((((MS_U32)u16Bank<<4)*8)|((MS_U32)u8addr/2)); ++ data.u64Cmd = _CMDQGetCMD(data.u8type,data.u32Addr,data.u16Data,data.u16Mask); ++ return data.u64Cmd; ++} ++void _Drv_CMDQ_PutCmd(MS_U8 u8type, MS_CMDQ_CMDReg *stCfg,MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_U64 u64CMD; ++ u64CMD = _Drv_CMDQ_GetCmd(u8type,stCfg->u32Addr,stCfg->u16Data,stCfg->u16Mask); ++ _Drv_CMDQ_WriteCmd(u64CMD,bSkipCheckSameAddr);//cmd:real cmd ++} ++void _Drv_CMDQ_AddWaitLDCTrigCMD(EN_CMDQ_IP_TYPE enIPType) ++{ ++ #if 0 ++ _Drv_CMDQ_AddNull(enIPType); ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,0x12183C,0xFFFD,0xFFFF,1); ++ Drv_CMDQ_WaitCmd(sc2cmdq_lv_trig);//wait ++ _Drv_CMDQ_AddNull(enIPType); ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,0x12183C,0xFFFF,0xFFFF,1); ++ #endif ++} ++//-------------------------------------------------------------------------------------------------- ++// In ring-buffer mode, this function will trig for update reg_sw_wr_mi_wadr ++// The CMDQ will keep on executing cmd until reg_rd_mi_radr reach reg_sw_wr_mi_wadr ++//-------------------------------------------------------------------------------------------------- ++ ++//API-------------------------------------------------------------------------------------------------- ++void _Drv_CMDQ_WriteRegWithMaskDirect(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask) ++{ ++ Hal_CMDQ_WriteRegMaskDirect(u32Addr,u16Data,u16Mask); ++} ++ ++MS_U64 Drv_CMDQ_GetCMDFromPoint(EN_CMDQ_IP_TYPE enIPType ,MS_U16 u16Point) ++{ ++ MS_U64 *pu32Addr = NULL; ++ CMDQ_MUTEX_LOCK(); ++ gstCurrworkIP = enIPType; ++ pu32Addr = _Drv_CMDQ_GetPointerFromPoint((u16Point),pu32Addr); ++ CMDQ_MUTEX_UNLOCK(); ++ return (MS_U64)(*pu32Addr); ++} ++MS_U32 Drv_CMDQ_GetCMDBankFromCMD(MS_U64 u64Cmd) ++{ ++ MS_U32 u32BankAddr; ++ MS_U16 u16Addr; ++ MS_U32 u32Bank; ++ u32BankAddr = (MS_U32)((u64Cmd &0x00FFFFFF00000000 )>>32) ; ++ if((u32BankAddr&0x0000FF)>=0x80) // odd bank ++ { ++ u16Addr = (MS_U16)((u32BankAddr&0x0000FF)-0x80); ++ } ++ else // even bank ++ { ++ u16Addr = (MS_U16)(u32BankAddr&0x0000FF); ++ } ++ u32Bank = (MS_U32)(((u32BankAddr - u16Addr))*2) ; ++ u32BankAddr = (MS_U32)(u32Bank + u16Addr); ++ ++ return u32BankAddr; ++} ++ ++MS_U8 Drv_CMDQ_GetISPHWCnt(void) ++{ ++ MS_U16 isp_cnt; ++ isp_cnt = Hal_CMDQ_Get_ISP_Cnt(); ++ isp_cnt = ((isp_cnt>>8)&0x7F); ++ return (MS_U8)isp_cnt; ++ ++} ++ ++void Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_IP_TYPE enIPType ,MS_U16 bEn) ++{ ++ Hal_CMDQ_SetSkipPollWhenWaitTimeout(enIPType,bEn); ++ Hal_CMDQ_SetTimeoutAmount(enIPType); ++} ++ ++void Drv_CMDQ_Enable(MS_BOOL bEnable,EN_CMDQ_IP_TYPE enIPType) ++{ ++ CMDQ_MUTEX_LOCK(); ++ if(bEnable) ++ { ++ gstCMDQInfo[enIPType].bEnable++; ++ } ++ else ++ { ++ if(gstCMDQInfo[enIPType].bEnable) ++ { ++ gstCMDQInfo[enIPType].bEnable--; ++ } ++ } ++ CMDQ_MUTEX_UNLOCK(); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW, "[CMDQ]%s enable:%hhd\n" ++ ,__FUNCTION__,gstCMDQInfo[enIPType].bEnable); ++} ++void Drv_CMDQ_Init(ST_VIP_OPEN_CONFIG *stCMDQIniCfg) ++{ ++ MS_PHYADDR IP0PhyAddr; ++ MS_U32 u32CMDQBufSize; ++ MS_U32 u32IP0VirAddr; ++ EN_CMDQ_IP_TYPE i; ++ Hal_CMDQ_InitRIUBase(stCMDQIniCfg->u32RiuBase); ++ CMDQ_MUTEX_CREATE(); ++ for(i=EN_CMDQ_TYPE_IP0 ;iu32CMDQ_Phy[i] && stCMDQIniCfg->u32CMDQ_Vir[i]&& stCMDQIniCfg->u32CMDQ_Size[i]) ++ { ++ u32CMDQBufSize = stCMDQIniCfg->u32CMDQ_Size[i] / CMDQ_NUMBER;// 0x4000/2 ++ IP0PhyAddr = stCMDQIniCfg->u32CMDQ_Phy[i]; ++ u32IP0VirAddr = stCMDQIniCfg->u32CMDQ_Vir[i]; ++ MsOS_Memset((void *)stCMDQIniCfg->u32CMDQ_Vir[i], 0x00, stCMDQIniCfg->u32CMDQ_Size[i]); ++ ++ CMDQ_MUTEX_LOCK(); ++ _Drv_CMDQ_Init(IP0PhyAddr); ++ _Drv_CMDQ_FillInitIPInfo(i, IP0PhyAddr, ++ u32IP0VirAddr, u32CMDQBufSize); ++ _Drv_CMDQ_InitByIP(i); ++ CMDQ_MUTEX_UNLOCK(); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW, "[CMDQ]init %s: 0x%lx,0x%lx, 0x%lx\n" ++ , __FUNCTION__, stCMDQIniCfg->u32CMDQ_Phy[i],stCMDQIniCfg->u32CMDQ_Vir[i], stCMDQIniCfg->u32CMDQ_Size[i]); ++ } ++ } ++ ++} ++void Drv_CMDQ_Delete(EN_CMDQ_IP_TYPE enIPType) ++{ ++ Hal_CMDQ_ClearIRQByFlag(enIPType,0x0800); //clear idle ++ while(1) ++ { ++ if(_IsCMDQIPIdle(enIPType)) // wait idle ++ { ++ break; ++ } ++ } ++ Hal_CMDQ_SetISRMSK(enIPType,0xFFFF); ++ Hal_CMDQ_ResetSoftInterrupt(enIPType); ++ CMDQ_MUTEX_DELETE(); ++ if (_gCMDQHVSPMUTEX[enIPType] != -1) ++ { ++ MsOS_DeleteMutex(_gCMDQHVSPMUTEX[enIPType]); ++ } ++} ++void Drv_CMDQ_release(EN_CMDQ_IP_TYPE enIPType) ++{ ++ int u32Time; ++ if(gstCMDQInfo[enIPType].bEnable == 1 || gstCMDQInfo[enIPType].bEnable == 0) ++ { ++ u32Time = MsOS_GetSystemTime(); ++ Drv_CMDQ_BeTrigger(enIPType,1); ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(enIPType,1); ++ while(1) ++ { ++ if(Drv_CMDQ_CheckIPAlreadyDone(enIPType)) ++ { ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(enIPType,0); ++ break; ++ } ++ else if(MsOS_Timer_DiffTimeFromNow(u32Time)>1000) ++ { ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(enIPType,0); ++ break; ++ } ++ } ++ _Drv_CMDQ_Reset(enIPType); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_LOW, "[CMDQ]%s enable:%hhd\n" ++ ,__FUNCTION__,gstCMDQInfo[0].bEnable); ++ } ++ else ++ { ++ Drv_CMDQ_Enable(0,enIPType); ++ } ++} ++void Drv_CMDQ_FillCmd(MS_CMDQ_CMDReg *stCfg,MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask) ++{ ++ stCfg->u16Data = u16Data; ++ stCfg->u32Addr = u32Addr; ++ stCfg->u16Mask = u16Mask; ++} ++ ++//u32Addr :8bit addr ++MS_BOOL Drv_CMDQ_WriteCmd(EN_CMDQ_IP_TYPE enIPType, MS_CMDQ_CMDReg *stCfg, MS_BOOL bSkipCheckSameAddr) ++{ ++ MS_BOOL bRet=1; ++ if(_gs32CMDQMutex == -1 || gstCMDQInfo[enIPType].bEnable==0) ++ { ++ return 0; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]%s\n",__FUNCTION__); ++ CMDQ_MUTEX_LOCK(); ++ gstCurrworkIP = enIPType; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]Write: %04lx %04x %04x flag: %hhx\n" ++ ,stCfg->u32Addr, stCfg->u16Data, stCfg->u16Mask,gCMDQStatusFlag[enIPType]); ++ #if USE_Utility ++ Hal_CMDQ_WriteRegMaskBuffer(stCfg->u32Addr,stCfg->u16Data, stCfg->u16Mask); ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,stCfg,NotToCheckSameAddr); ++ #else ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_WRITE,stCfg,bSkipCheckSameAddr); ++ #endif ++ CMDQ_MUTEX_UNLOCK(); ++ return bRet; ++} ++MS_CMDQ_Info *Drv_CMDQ_GetCMDQInformation(EN_CMDQ_IP_TYPE enIPType) ++{ ++ return &gstCMDQInfo[enIPType]; ++} ++void Drv_CMDQ_GetModuleMutex(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ static MS_BOOL block = 0; ++ if(bEn) ++ { ++ MsOS_ObtainMutex(_gCMDQHVSPMUTEX[enIPType],MSOS_WAIT_FOREVER); ++ block = 1; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]IN Mutex\n"); ++ } ++ else if(block && !bEn) ++ { ++ block = 0; ++ MsOS_ReleaseMutex(_gCMDQHVSPMUTEX[enIPType]); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL,"[CMDQ]Out Mutex\n"); ++ } ++} ++void Drv_CMDQ_InitRIUBase(MS_U32 u32RIUBase) ++{ ++ Hal_CMDQ_InitRIUBase(u32RIUBase); ++} ++MS_U16 Drv_CMDQ_GetFinalIrq(EN_CMDQ_IP_TYPE enIPType) ++{ ++ gu16ISRflag = Hal_CMDQ_GetFinalIrq(enIPType, 0xFFFF); ++ return gu16ISRflag; ++} ++void Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Irq) ++{ ++ Hal_CMDQ_ClearIRQByFlag(enIPType,u16Irq); ++} ++void Drv_CMDQ_SetISRStatus(MS_BOOL bEn) ++{ ++ gbISRopen = bEn; ++} ++//------------------------------------------------------------------------------------------------- ++/// Fire the commands ++/// @return TRUE if succeed, FALSE if failed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_Fire(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart) ++{ ++ if(_gs32CMDQMutex == -1 || gstCMDQInfo[enIPType].bEnable==0) ++ { ++ SCL_DBGERR("[CMDQ]%s can't use\n",__FUNCTION__); ++ return 0; ++ } ++ CMDQ_MUTEX_LOCK(); ++ gstCurrworkIP = enIPType; ++#if (CMDQCMD128==0) ++ if(gstCMDQInfo[enIPType].u16WPoint%2) ++ { ++ _Drv_CMDQ_AddNull(enIPType); ++ } ++#endif ++ _Drv_CMDQ_Fire(enIPType,1); ++ _SetCMDQFlagType(enIPType,CMDQ_FLAG_FIRE); ++ CMDQ_MUTEX_UNLOCK(); ++ ++ return true; ++ ++} ++void Drv_CMDQ_SetEventForFire(void) ++{ ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_VIP); ++} ++void Drv_CMDQ_WaitCmd(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16bus) ++{ ++ MS_U64 u64Cmd; ++ CMDQ_MUTEX_LOCK(); ++ gstCurrworkIP = enIPType; ++ u64Cmd = MS_CMDQ_WAIT_CMD + u16bus; ++ _Drv_CMDQ_WriteCmd((MS_U64)u64Cmd, NotToCheckSameAddr); ++ CMDQ_MUTEX_UNLOCK(); ++} ++ ++void Drv_CMDQ_PollingEqCmd(EN_CMDQ_IP_TYPE enIPType,MS_CMDQ_CMDReg *stCfg) ++{ ++ CMDQ_MUTEX_LOCK(); ++ gstCurrworkIP = enIPType; ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_POLLEQ,stCfg,NotToCheckSameAddr); ++ CMDQ_MUTEX_UNLOCK(); ++} ++ ++void Drv_CMDQ_PollingNeqCmd(EN_CMDQ_IP_TYPE enIPType,MS_CMDQ_CMDReg *stCfg) ++{ ++ CMDQ_MUTEX_LOCK(); ++ gstCurrworkIP = enIPType; ++ _Drv_CMDQ_PutCmd(CMDQ_CMDTYPE_POLLNEQ,stCfg,NotToCheckSameAddr); ++ CMDQ_MUTEX_UNLOCK(); ++} ++void Drv_CMDQ_CheckVIPSRAM(MS_U32 u32Type) ++{ ++ Drv_VIP_CheckVIPSRAM(u32Type); ++} ++MS_BOOL Drv_CMDQ_CheckIPAlreadyDone(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_BOOL bEn; ++ if(_IsCMDQDMADone(enIPType)) //cmdq dma done ++ { ++ bEn = TRUE; ++ Hal_CMDQ_ClearIRQByFlag(enIPType,0x0003); ++ } ++ else if(gbISRopen) ++ { ++ if(_IsCMDQExecuteDoneISR(enIPType)) ++ { ++ bEn = TRUE; ++ } ++ else if(MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&E_SCLIRQ_EVENT_CMDQDONE) ++ { ++ bEn = TRUE; ++ } ++ else ++ { ++ bEn = FALSE; ++ } ++ } ++ else if(_IsCMDQExecuteDone(enIPType)) ++ { ++ bEn = TRUE; ++ Hal_CMDQ_ClearIRQByFlag(enIPType,0x0003); ++ } ++ else ++ { ++ bEn = FALSE; ++ } ++ return bEn; ++} +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/cmdq/drvCMDQ.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/cmdq/drvCMDQ.h +new file mode 100644 +index 00000000..c7a23e3b +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/cmdq/drvCMDQ.h +@@ -0,0 +1,371 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. 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If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file drvCMDQ.h ++/// @brief CMDQ Driver Interface ++/// @author MStar Semiconductor,Inc. ++/// ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRVCMDQ_H_ ++#define _DRVCMDQ_H_ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//#include "MsTypes.h" ++#include "MsCommon.h" ++#include "MsTypes.h" ++//#include ++ ++ ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Define ++//-------------------------------------------------------------------------------------------------- ++#define DIRECT_MODE 0x01 // direct mode :nonuse ++#define INCREMENT_MODE 0x00 // increment mode :nonuse ++#define RING_BUFFER_MODE 0x04 // ring mode ++#define CMDQ_DBUF 0 // whether double buffer ++#define CMDQ_irq 0 // isr open ++#define CMDQ_nonuse_Function 0 // mark no use function ++#define CMDQ_poll_timer 0x4D // poll timer ++#define CMDQ_timer_ratio 0x0 // time ratio ++#define CMDQ_base_amount 0x1FFFF // wait count amount ++#define CMDQ_timeout_amount 0x40 // wait timeout amount ++#define CMDQ_NUMBER 1 // number of CMDQ ip ++#define CMDQ_ADD_DELAYFRAME_SCLSELF 0 // when=1 is delay 2 frame ,when =0 is delay 2frame but input isp count add 1 itself. ++#define CMDQ_ALLOW_ERROR_COUNT 1 // allow overpass count ++#define CMDQ_IRQ_STATE_TRIG (1 << 0) ++#define CMDQ_IRQ_STATE_DONE (1 << 2) ++#define CMDQ_IRQ_WAIT_TIMEOUT (1 << 10) ++#define CMDQ_CMDTYPE_WRITE 0x10 ++#define CMDQ_CMDTYPE_WAIT 0x20 ++#define CMDQ_CMDTYPE_POLLEQ 0x30 ++#define CMDQ_CMDTYPE_POLLNEQ 0xb0 ++//-------------------------------------------------------------------------------------------------- ++// Driver Capability ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Local variable ++//----------------------------------------------------------------------------------------------- ++extern MS_U32 _CMDQ_RIU_BASE; ++ ++//-------------------------------------------------------------------------------------------------- ++// Type and Structure ++//-------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ EN_CMDQ_TYPE_IP0 , ++ EN_CMDQ_TYPE_IP1 , ++ EN_CMDQ_TYPE_IP2 , ++ EN_CMDQ_TYPE_MAX, ++}EN_CMDQ_IP_TYPE; ++ ++typedef enum ++{ ++ EN_CMDQ_MIU_0 , ++ EN_CMDQ_MIU_1 , ++}EN_CMDQ_MIU_TYPE; ++ ++typedef enum ++{ ++ CMDQ_FLAG_FIRE = 0x1, // whether already fire or need to fire ++}CMDQ_FLAG_TYPE; ++typedef struct ++{ ++ MS_U16 u16WPoint; // current cmd end ++ MS_U16 u16RPoint; // last trig ++ MS_U16 u16FPoint; // fire point (128 bit/unit) ++ MS_PHYADDR PhyAddr; // by Chip_Phys_to_MIU ++ MS_U16 u16MaxCmdCnt; // assframe buf count ++ MS_BOOL bEnable; // CMDQ enable ((nonuse ++ MS_U32 u32VirAddr; // kernel virtul after allocate ++ MS_PHYADDR PhyAddrEnd; // by Chip_Phys_to_MIU+cnt ++ MS_U16 u16LPoint; // To get trig Count ++ MS_U16 u16DPoint; // last done ++}MS_CMDQ_Info; ++ ++typedef struct ++{ ++ MS_U8 u8MIUSel_IP; ++}CMDQ_Buffer_MIU; ++typedef struct ++{ ++ MS_U16 u16StartPoint; ++ MS_U16 u16EndPoint; ++ MS_U32 u32CmdDiffCnt; ++ MS_U32 u32ActualCmdDiffCnt; ++ MS_BOOL Ret; ++ MS_U32 u32addr; ++ MS_U16 u16mask; ++ MS_U16 u16data; ++ MS_U64 *pu32Addr; ++}CMDQ_CheckCmdinfo; ++ ++typedef struct ++{ ++ MS_U8 u8type; // CMD type(write,wait,poll) ++ MS_U16 u16Data; // 16bit data ++ MS_U32 u32Addr; // 16bit Bank addr + 8bit 16bit-regaddr ++ MS_U16 u16Mask; // inverse normal case ++ MS_U64 u64Cmd; // 64bit to consist CMDQ CMD ++ MS_U8 u8AssignFramecnt; ++ MS_U8 bCntWarn; ++ MS_U8 bAddPollFunc; ++}MS_CMDQ_CMD; ++ ++typedef struct ++{ ++ MS_U16 u16Data; // 16bit data ++ MS_U32 u32Addr; // 16bit Bank addr + 8bit 16bit-regaddr ++ MS_U16 u16Mask; // inverse normal case ++}MS_CMDQ_CMDReg; ++ ++typedef enum ++{ ++ E_CMDQ_EVENT_RUN = 0x00000001, ++ E_CMDQ_EVENT_IRQ = 0x00000002, ++} MDrvHDMITXEvent; ++ ++#define DRVCMDQ_OK 0x00000000 ++#define DRVCMDQ_FAIL 0x00000001 ++ ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++ MS_U32 u32CMDQ_Phy[EN_CMDQ_TYPE_MAX]; ++ MS_U32 u32CMDQ_Size[EN_CMDQ_TYPE_MAX]; ++ MS_U32 u32CMDQ_Vir[EN_CMDQ_TYPE_MAX]; ++}ST_VIP_OPEN_CONFIG; ++ ++//-------------------------------------------------------------------------------------------------- ++// Function Prototype ++//-------------------------------------------------------------------------------------------------- ++//==============================Enable=============================================== ++ void Drv_CMDQ_Enable(MS_BOOL bEnable,EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_SetForceSkip(bool bEn); ++ ++//==============================Delete=============================================== ++void Drv_CMDQ_Delete(EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_SetRPoint(EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_SetDPoint(EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_SetLPoint(EN_CMDQ_IP_TYPE enIPType); ++MS_U32 Drv_CMDQ_BeTrigger(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart); ++MS_U64 Drv_CMDQ_GetCMDFromPoint(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Point); ++MS_U32 Drv_CMDQ_GetCMDBankFromCMD(MS_U64 u64Cmd); ++void _Drv_CMDQ_WriteRegWithMaskDirect(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask); ++//===============================init============================================== ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_Init ++/// is CMDQ IP init function, to set timer,address and size ++/// @param PhyAddr1 \b IN: from msys_request_dmem,and transform to MIU address ++/// @param u32VirAddr1 \b IN:like phyaddr,map to kernel virtual ++/// @param u32BufByteLen \b IN:already allocate memory size ++/// @param u32RIUBase \b IN:RIU's base shift ++//------------------------------------------------------------------------------------------------- ++ void Drv_CMDQ_Init(ST_VIP_OPEN_CONFIG *stCMDQIniCfg); ++void Drv_CMDQ_InitRIUBase(MS_U32 u32RIUBase); ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_Set_timer_ratio ++/// set poll times in 1sec ++/// set time / ratio, total wait time is (wait_time * (ratio + 1)) =>ex. ( FF * (F + 1) / 216 MHz ) = sec ++/// 4D*1=4D~=77 *(216/M) 1 ~=60(frame/s) ++/// the polling_timer is for re-checking polling value, if the time_interval is too small, cmdq will polling RIU frequently, so that RIU will very busy ++/// @param time \b IN: poll wait time :#CMDQ_poll_timer ++/// @param ratio \b IN: time ratio :# CMDQ_timer_ratio ++/// retval : OK ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_SetSkipPollWhenWaitTimeOut ++/// set wait timeout count and whether jump timeout ++/// @param u16bjump \b IN:if true, timeout will jump wait, and carry out command ++//------------------------------------------------------------------------------------------------- ++void Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_IP_TYPE enIPType,MS_U16 bEn); ++//-------------------------------------------------------------------------------------------------- ++// Drv_CMDQ_Set_Buffer ++// set addr st and end pointer ,and set move range ++// In ring-buffer mode, this function will trig for update reg_sw_wr_mi_wadr ++// The CMDQ will keep on executing cmd until reg_rd_mi_radr reach reg_sw_wr_mi_wadr ++/// @param StartAddr \b IN:MIU addr(byte base) --> IP need 16byte addr,so function inside will /16 ++/// @param EndAddr \b IN:MIU addr ++//-------------------------------------------------------------------------------------------------- ++MS_U16 Drv_CMDQ_GetFinalIrq(EN_CMDQ_IP_TYPE enIPType); ++void Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Irq); ++void Drv_CMDQ_SetISRStatus(MS_BOOL bEn); ++void Drv_CMDQ_GetModuleMutex(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_CMDQ_Info* Drv_CMDQ_GetCMDQInformation(EN_CMDQ_IP_TYPE enIPType); ++ ++//===============================write============================================== ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_WriteCmd ++/// write cmd API for any case ,to add cmd to MIU ++/// @param u32Addr \b IN: 8bit-addr ++/// @param u16Data \b IN: 16bit data ++/// @param u16Mask \b IN: 16bit ~mask, ++/// @param bSkipCheckSameAddr \b IN:if true,don't need to check .if false don't use mask(for RIU 32bit) ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_WriteCmd(EN_CMDQ_IP_TYPE enIPType, MS_CMDQ_CMDReg *stCfg, MS_BOOL bSkipCheckSameAddr); ++void Drv_CMDQ_FillCmd(MS_CMDQ_CMDReg *stCfg,MS_U32 u32Addr, MS_U16 u16Data, MS_U16 u16Mask); ++ ++void Drv_CMDQ_release(EN_CMDQ_IP_TYPE enIPType); ++MS_U8 Drv_CMDQ_GetISPHWCnt(void); ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_AddCmd ++/// To add CMD to MIU, _Buf is use to nonframe count ++/// @param u64Cmd \b IN: the CMD want to write to MIU ++/// @param bSkipCheckSameAddr \b IN: if true,don't need to check .if false don't use mask(for RIU 32bit) ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_MoveBufCmd ++/// To move nonframe count CMD form nonframe count region to assframe count region ++/// @param enIPType \b IN: Buf number,nonuse ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_AddCmd_Check ++/// To check the CMD whether already exist. if yes ,to handle it. ++/// @param u64Cmd \b IN: the CMD want to write to MIU ++/// @param bframecount \b IN: if true, is frame count case. ++/// @param bSkipCheckSameAddr \b IN:if true,don't need to check .if false don't use mask(for RIU 32bit) ++//------------------------------------------------------------------------------------------------- ++ ++ //===============================wait============================================== ++ //------------------------------------------------------------------------------------------------- ++ /// Drv_CMDQ_WaitCmd ++ /// To add wait CMD ++ /// @param u16bus \b IN: wait trigger bus ++ //------------------------------------------------------------------------------------------------- ++ void Drv_CMDQ_WaitCmd(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16bus); ++ ++ //===============================poll============================================== ++ //------------------------------------------------------------------------------------------------- ++ /// Drv_CMDQ_PollingEqCmd ++ /// add Polling CMD ,or neq CMD ++ /// @param u32Addr \b IN: 8bit-addr ++ /// @param u16Data \b IN: 16bit data ++ /// @param u16Mask \b IN: 16bit ~mask, ++ //------------------------------------------------------------------------------------------------- ++ void Drv_CMDQ_PollingEqCmd(EN_CMDQ_IP_TYPE enIPType,MS_CMDQ_CMDReg *stCfg); ++ void Drv_CMDQ_PollingNeqCmd(EN_CMDQ_IP_TYPE enIPType,MS_CMDQ_CMDReg *stCfg); ++ void Drv_CMDQ_CheckVIPSRAM(MS_U32 u32Type); ++ ++ //===============================fire============================================== ++ //------------------------------------------------------------------------------------------------- ++ /// Drv_CMDQ_Fire ++ /// To trig CMDQ ++ /// @param bStart \b IN: trig ++ //------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_Fire(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bStart); ++ void Drv_CMDQ_SetEventForFire(void); ++ ++//===============================check============================================== ++//------------------------------------------------------------------------------------------------- ++/// Drv_CMDQ_CheckIPAlreadyDone ++/// To check CMDQ status ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_CMDQ_CheckIPAlreadyDone(EN_CMDQ_IP_TYPE enIPType); ++ ++//===============================write Register============================================== ++#endif // _DRVCMDQ_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp.c b/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp.c +new file mode 100644 +index 00000000..6f025456 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp.c +@@ -0,0 +1,2178 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_HVSP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++#include ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "MsDbg.h" ++//#include ++//#include ++//#include ++//#include ++ ++#include "drvhvsp_st.h" ++#include "halhvsp.h" ++#include "drvhvsp.h" ++#include "drvscldma_st.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "irqs.h" ++#include "mdrv_scl_dbg.h" ++#include "hwreg.h" ++#include "drvCMDQ.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_HVSP_DBG(x) ++#define DRV_HVSP_ERR(x) x ++#define DRV_HVSP_MUTEX_LOCK() MsOS_ObtainMutex(_HVSP_Mutex,MSOS_WAIT_FOREVER) ++#define DRV_HVSP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_HVSP_Mutex) ++#define FHD_Width 1920 ++#define FHD_Height 1080 ++#define _3M_Width 2048 ++#define _3M_Height 1536 ++#define HD_Width 1280 ++#define HD_Height 720 ++#define D_Width 704 ++#define D_Height 576 ++#define PNL_Width 800 ++#define PNL_Height 480 ++#define SRAMFORSCALDOWN 0x10 ++#define SRAMFORSCALUP 0x21 ++#define SRAMFORSC2ALDOWN 0x20 ++#define SRAMFORSC2ALUP 0x21 ++#define SRAMFORSC3HDOWN 0x00 ++#define SRAMFORSC3HUP 0x21 ++#define SRAMFORSC3VDOWN 0x00 ++#define SRAMFORSC3VUP 0x21 ++#define HeightRange (gstSrcSize.u16Height ? ((gstSrcSize.u16Height+1)/20) : (FHD_Height/20)) ++#define Is_StartAndEndInSameByte(u16XStartoffsetbit,u16idx,u16Xoffset) \ ++ (u16XStartoffsetbit && (u16idx ==0) && (u16Xoffset==1)) ++#define Is_StartByteOffsetBit(u16XStartoffsetbit,u16idx) \ ++ (u16XStartoffsetbit && (u16idx ==0)) ++#define Is_EndByteOffsetBit(u16XEndoffsetbit,u16Xoffset,u16idx) \ ++ (u16XEndoffsetbit && (u16idx ==(u16Xoffset-1))) ++#define Is_DNRBufferReady() (gbMemReadyForDrv) ++#define Is_FrameBufferTooSmall(u32ReqMemSize,u32IPMMemSize) (u32ReqMemSize > u32IPMMemSize) ++#define Is_PreCropWidthNeedToOpen() (gstSrcSize.u16Width > gstIPMCfg.u16Fetch) ++#define Is_PreCropHeightNeedToOpen() (gstSrcSize.u16Height> gstIPMCfg.u16Vsize) ++#define Is_InputSrcRotate() (gstSrcSize.u16Height > gstSrcSize.u16Width) ++#define Is_IPM_NotSetReady() (gstIPMCfg.u16Fetch == 0 || gstIPMCfg.u16Vsize == 0) ++#define Is_INPUTMUX_SetReady() (gstSrcSize.bSet == 1) ++#define Is_PreCropNotNeedToOpen() ((gstIPMCfg.u16Fetch == gstSrcSize.u16Width) && \ ++ (gstIPMCfg.u16Vsize == gstSrcSize.u16Height)) ++#define HVSP_ID_SRAM_V_OFFSET 2 ++#define HVSP_ID_SRAM_H_OFFSET 15 ++#define HVSP_RATIO(input, output) ((MS_U32)((MS_U64)((input) * 1048576) / (output))) ++#define HVSP_CROP_RATIO(u16src, u16crop1, u16crop2) ((MS_U16)(((MS_U32)u16crop2 * (MS_U32)u16crop1) / (MS_U32)u16src )) ++#define HVSP_CROP_CHECK(u16croph,u16cropch,u16cropv,u16cropcv) (((u16croph) != (u16cropch))|| ((u16cropv) != (u16cropcv))) ++#define HVSP_DMA_CHECK(u16cropv,u16cropcv) (((u16cropv) != (u16cropcv))) ++#define _Change_SRAM_V_Qmap(enHVSP_ID,up) (((gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height\ ++ > gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height)&&(up)) || (((gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height\ ++ < gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height) && !(up)))) ++#define _Change_SRAM_H_Qmap(enHVSP_ID,up) (((gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width\ ++ > gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width)&&(up)) || (((gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width\ ++ < gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width) && !(up)))) ++ ++#define _Is_SingleBufferAndZoomSizeBiggerthanLimitation(u8buffernum,cropV,DspV) (((u8buffernum)==1) && \ ++ ((DspV) > (cropV))) ++#define _Is_SingleBufferAndNOLDCZoomSizeBiggerthanLimitation(bnoLDC,u8buffernum,cropV,DspV) ((bnoLDC)&&((u8buffernum)==1) && \ ++ ((DspV) > (cropV))) ++#define _Is_Src5MSize() ((gstSrcSize.u16Height*gstSrcSize.u16Width) >= 4500000 &&(gstSrcSize.bSet)) ++#define _IsChangeFBBufferResolution(u16Width ,u16Height) ((u16Width !=gstIPMCfg.u16Fetch)||(u16Height !=gstIPMCfg.u16Vsize)) ++#define _IsChangePreCropPosition(u16X ,u16Y ,u16oriX ,u16oriY ) (((u16X !=u16oriX)||(u16Y !=u16oriY))) ++#define _IsZoomOut(u16Width ,u16Height) ((u16Width < gstIPMCfg.u16Fetch)||(u16Height < gstIPMCfg.u16Vsize)) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++ST_HVSP_SCALING_INFO gstScalinInfo[E_HVSP_ID_MAX]; ++ST_HVSP_IPM_CONFIG gstIPMCfg = {0}; ++ST_HVSP_SIZE_CONFIG gstSrcSize; ++unsigned char gbPriMaskPending; ++unsigned char *gpu8PriMaskBuf; ++///////////////// ++/// gbMemReadyForDrv ++/// if True ,DNR buffer was allocated. ++//////////////// ++MS_BOOL gbMemReadyForDrv; ++///////////////// ++/// bLDCEn ++/// if True ,LDC is open.(To sync VIP and HVSP driver) ++//////////////// ++MS_BOOL gbLDCEn=0; ++MS_U8 gu8FBBufferNum ; ++///////////////// ++/// gbHvspSuspend ++/// To Save suspend status. ++//////////////// ++MS_BOOL gbHvspSuspend = 0; ++///////////////// ++/// bclkforcemode ++/// use in Drvscldma and Drvhvsp ++/// if True ,can't dynamic set Clk ++//////////////// ++unsigned char gbclkforcemode = 0;//extern ++MS_S32 _HVSP_Mutex = -1; ++static MS_BOOL gbVScalingup[E_HVSP_ID_MAX] ={1,0,0}; ++static MS_BOOL gbHScalingup[E_HVSP_ID_MAX] ={1,0,0}; ++MS_BOOL gbSc3FirstHSet = 1; ++MS_BOOL gbSc3FirstVSet = 1; ++ ++//------------------------------------------------------------------------------------------------- ++// Private Functions ++//------------------------------------------------------------------------------------------------- ++void _Drv_HVSP_InitSWVarialbe(EN_HVSP_ID_TYPE HVSP_IP) ++{ ++ MsOS_Memset(&gstScalinInfo[HVSP_IP], 0, sizeof(ST_HVSP_SCALING_INFO)); ++ gbVScalingup[HVSP_IP] = 0; ++ gbHScalingup[HVSP_IP] = 0; ++ gbSc3FirstHSet = 1; ++ gbSc3FirstVSet = 1; ++ if(HVSP_IP == E_HVSP_ID_1) ++ { ++ MsOS_Memset(&gstIPMCfg, 0, sizeof(ST_HVSP_IPM_CONFIG)); ++ gbLDCEn = 0; ++ gbPriMaskPending = 0; ++ gbVScalingup[HVSP_IP] = SRAMFORSCALUP; ++ gbHScalingup[HVSP_IP] = SRAMFORSCALUP; ++ gstSrcSize.u16Height = FHD_Height; ++ gstSrcSize.u16Width = FHD_Width; ++ gstSrcSize.bSet = 0; ++ Hal_HVSP_SetInputSrcSize(&gstSrcSize); ++ } ++ else if(HVSP_IP == E_HVSP_ID_2) ++ { ++ gbVScalingup[HVSP_IP] = SRAMFORSC2ALDOWN; ++ gbHScalingup[HVSP_IP] = SRAMFORSC2ALDOWN; ++ } ++ else if(HVSP_IP == E_HVSP_ID_3) ++ { ++ ++ gbVScalingup[HVSP_IP] = SRAMFORSC3VDOWN; ++ gbHScalingup[HVSP_IP] = SRAMFORSC3HDOWN; ++ } ++ ++} ++ ++void _Drv_HVSP_FillPreCropInfo(ST_HVSP_CROP_INFO *stCropInfo) ++{ ++ if(Is_IPM_NotSetReady() || Is_PreCropNotNeedToOpen()) ++ { ++ if(Is_IPM_NotSetReady()) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: IPM without setting\n", __FUNCTION__, __LINE__)); ++ } ++ stCropInfo->bEn = 0; ++ stCropInfo->u16Vst = 0; ++ stCropInfo->u16Hst = 0; ++ stCropInfo->u16Hsize = 0; ++ stCropInfo->u16Vsize = 0; ++ } ++ else ++ { ++ stCropInfo->bEn = 1; ++ if(Is_InputSrcRotate())//rotate ++ { ++ stCropInfo->u16Hst = 0; ++ stCropInfo->u16Vst = 0; ++ } ++ else if(Is_PreCropWidthNeedToOpen() || Is_PreCropHeightNeedToOpen()) ++ { ++ if(Is_PreCropWidthNeedToOpen()) ++ { ++ stCropInfo->u16Hst = (gstSrcSize.u16Width - gstIPMCfg.u16Fetch)/2; ++ } ++ if(Is_PreCropHeightNeedToOpen()) ++ { ++ stCropInfo->u16Vst = (gstSrcSize.u16Height - gstIPMCfg.u16Vsize)/2; ++ } ++ } ++ else ++ { ++ stCropInfo->u16Hst = 0; ++ stCropInfo->u16Vst = 0; ++ } ++ stCropInfo->u16Hsize = gstIPMCfg.u16Fetch; ++ stCropInfo->u16Vsize = gstIPMCfg.u16Vsize; ++ } ++ // crop1 ++ stCropInfo->u16In_hsize = gstSrcSize.u16Width; ++ stCropInfo->u16In_vsize = gstSrcSize.u16Height; ++ if(stCropInfo->u16In_hsize == 0) ++ { ++ stCropInfo->u16In_hsize = FHD_Width; ++ } ++ if(stCropInfo->u16In_vsize == 0) ++ { ++ stCropInfo->u16In_vsize = FHD_Height; ++ } ++} ++void _Drv_HVSP_SetCoringThrdOn(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ Hal_HVSP_SetHspCoringThrdC(enHVSP_ID,0x1); ++ Hal_HVSP_SetHspCoringThrdY(enHVSP_ID,0x1); ++ Hal_HVSP_SetVspCoringThrdC(enHVSP_ID,0x1); ++ Hal_HVSP_SetVspCoringThrdY(enHVSP_ID,0x1); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Public Functions ++//------------------------------------------------------------------------------------------------- ++MS_BOOL Drv_HVSP_SetCMDQTrigType(ST_HVSP_CMD_TRIG_CONFIG *stCmdTrigCfg) ++{ ++ Hal_HVSP_SetCMDQTrigCfg(stCmdTrigCfg); ++ Hal_HVSP_SetCMDQTrigFrameCnt(0); ++ return TRUE; ++} ++ ++MS_BOOL Drv_HVSP_GetCMDQTrigType(ST_HVSP_CMD_TRIG_CONFIG *pCfg) ++{ ++ Hal_HVSP_GetCMDQTrigCfg(pCfg); ++ return TRUE; ++} ++ ++MS_BOOL Drv_HVSP_GetCMDQDoneStatus(EN_HVSP_POLL_ID_TYPE enPollId) ++{ ++ MS_U32 u32Events = 0; ++ static MS_BOOL sbDone = 0; ++ MS_BOOL bRet = 0; ++ ++ if(((sbDone&(0x1<u32IRQNUM; ++ stSclirq.u32CMDQIRQNUM = pCfg->u32CMDQIRQNUM; ++ if(Drv_SCLIRQ_Suspend(&stSclirq)) ++ { ++ bRet = TRUE; ++ gbHvspSuspend = 1; ++ } ++ else ++ { ++ bRet = FALSE; ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) Suspend IRQ Fail\n", __FUNCTION__, __LINE__)); ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(3)), "[DRVHVSP]%s(%d) alrady suspned\n", __FUNCTION__, __LINE__); ++ bRet = TRUE; ++ } ++ ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ ++ return bRet; ++} ++void _Drv_HVSP_PriMaskInit(void) ++{ ++ Hal_HVSP_PriMask_ColorY(0x0); ++ Hal_HVSP_PriMask_ColorU(0x200); ++ Hal_HVSP_PriMask_ColorV(0x200); ++} ++void _Drv_HVSP_SetHWinit(void) ++{ ++ _Drv_HVSP_PriMaskInit(); ++ Hal_HVSP_SetTestPatCfg(); ++ Hal_HVSP_SetVpsSRAMEn(1); ++ Hal_HVSP_SetIPMBufferNumber(gu8FBBufferNum); ++ Hal_HVSP_SetOSDbypass(E_HVSP_ID_1, 1); ++ Hal_HVSP_SetOSDbypassWTM(E_HVSP_ID_1, 1); ++ Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_HVSP_V,SRAMFORSCALUP); ++ Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_HVSP_V_1,SRAMFORSC2ALDOWN); ++ Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_HVSP_V_2,SRAMFORSC3VDOWN); ++ Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_HVSP_H,SRAMFORSCALUP); ++ Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_HVSP_H_1,SRAMFORSC2ALDOWN); ++ Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_HVSP_H_2,SRAMFORSC3HDOWN); ++ gbVScalingup[E_HVSP_ID_3] = SRAMFORSC3VDOWN; ++ gbHScalingup[E_HVSP_ID_3] = SRAMFORSC3HDOWN; ++} ++ ++MS_BOOL Drv_HVSP_Resume(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_SCLIRQ_SUSPEND_RESUME_CONFIG stSclirq; ++ MS_BOOL bRet = TRUE; ++ MsOS_Memset(&stSclirq,0,sizeof(ST_SCLIRQ_SUSPEND_RESUME_CONFIG)); ++ MsOS_ObtainMutex(_HVSP_Mutex, MSOS_WAIT_FOREVER); ++ ++ //printf("%s,(%d) %d\n", __FUNCTION__, __LINE__, gbHvspSuspend); ++ if(gbHvspSuspend == 1) ++ { ++ stSclirq.u32IRQNUM = pCfg->u32IRQNUM; ++ stSclirq.u32CMDQIRQNUM = pCfg->u32CMDQIRQNUM; ++ if(Drv_SCLIRQ_Resume(&stSclirq)) ++ { ++ Drv_SCLIRQ_InterruptEnable(SCLIRQ_VSYNC_FCLK_LDC); ++ Hal_HVSP_SetTestPatCfg(); ++ gbHvspSuspend = 0; ++ bRet = TRUE; ++ } ++ else ++ { ++ ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) Resume IRQ Fail\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ _Drv_HVSP_SetHWinit(); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(3)), "[DRVHVSP]%s(%d) alrady resume\n", __FUNCTION__, __LINE__); ++ bRet = TRUE; ++ } ++ ++ MsOS_ReleaseMutex(_HVSP_Mutex); ++ ++ return bRet; ++} ++void Drv_HVSP_SetBufferNum(MS_U8 u8Num) ++{ ++ gu8FBBufferNum = u8Num; ++} ++MS_BOOL Drv_HVSP_GetBufferNum(void) ++{ ++ return gu8FBBufferNum; ++} ++void Drv_HVSP_PriMaskBufferReset(void) ++{ ++ DRV_HVSP_MUTEX_LOCK(); ++ MsOS_Memset(gpu8PriMaskBuf,0,HVSP_PRIMASK_SIZE); ++ DRV_HVSP_MUTEX_UNLOCK(); ++} ++void Drv_HVSP_Exit(unsigned char bCloseISR) ++{ ++ if(_HVSP_Mutex != -1) ++ { ++ MsOS_DeleteMutex(_HVSP_Mutex); ++ _HVSP_Mutex = -1; ++ } ++ if(bCloseISR) ++ { ++ Drv_SCLIRQ_Exit(); ++ } ++ if(gpu8PriMaskBuf) ++ { ++ MsOS_VirMemFree(gpu8PriMaskBuf); //probe ,free ++ gpu8PriMaskBuf = NULL; ++ } ++ Hal_HVSP_Exit(); ++ gbMemReadyForDrv = 0; ++ gu8FBBufferNum = 0; ++ gbclkforcemode = 0; ++} ++ ++MS_BOOL Drv_HVSP_Init(ST_HVSP_INIT_CONFIG *pInitCfg) ++{ ++ char word[] = {"_HVSP_Mutex"}; ++ ST_SCLIRQ_INIT_CONFIG stIRQInitCfg; ++ MS_U8 u8IDidx; ++ ST_HVSP_CMD_TRIG_CONFIG stori; ++ MsOS_Memset(&stIRQInitCfg,0,sizeof(ST_SCLIRQ_INIT_CONFIG)); ++ MsOS_Memset(&stori,0,sizeof(ST_HVSP_CMD_TRIG_CONFIG)); ++ if(_HVSP_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(3)), "[DRVHVSP]%s(%d) alrady done\n", __FUNCTION__, __LINE__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) MsOS_Init Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ _HVSP_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ ++ if (_HVSP_Mutex == -1) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d): create mutex fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ stIRQInitCfg.u32RiuBase = pInitCfg->u32RIUBase; ++ stIRQInitCfg.u32IRQNUM = pInitCfg->u32IRQNUM; ++ stIRQInitCfg.u32CMDQIRQNUM = pInitCfg->u32CMDQIRQNUM; ++ if(Drv_SCLIRQ_Init(&stIRQInitCfg) == FALSE) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d) Init IRQ Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ Hal_HVSP_SetRiuBase(pInitCfg->u32RIUBase); ++ DRV_HVSP_MUTEX_LOCK(); ++ Hal_HVSP_Set_Reset(); ++ for(u8IDidx = E_HVSP_ID_1; u8IDidxu32YCBaseAddr, stCfg->u16Fetch, stCfg->u16Vsize); ++ MsOS_Memcpy(&gstIPMCfg, stCfg, sizeof(ST_HVSP_IPM_CONFIG)); ++ DRV_HVSP_MUTEX_LOCK(); ++ if(gstIPMCfg.u16Fetch%2) ++ { ++ gstIPMCfg.u16Fetch--; ++ stCfg->u16Fetch--; ++ SCL_ERR("[DRVHVSP]IPM Width not align 2\n"); ++ } ++ Drv_HVSP_SetCMDQTrigTypeByRIU(&stCmdTrigCfg); ++ //_Drv_HVSP_SetPreCropWhenInputMuxReady(); ++ Hal_HVSP_SetBT656SrcConfig(1,stCfg->u16Fetch); ++ Hal_HVSP_SetIPMYCBase(stCfg->u32YCBaseAddr); ++ Hal_HVSP_SetIPMMotionBase(stCfg->u32MBaseAddr); ++ Hal_HVSP_SetIPMCIIRBase(stCfg->u32CIIRBaseAddr); ++ Hal_HVSP_SetIPMFetchNum(stCfg->u16Fetch); ++ Hal_HVSP_SetIPMLineOffset(stCfg->u16Fetch); ++ Hal_HVSP_SetIPMvSize(stCfg->u16Vsize); ++ Hal_HVSP_SetIPMYCMReadEn(stCfg->bYCMRead); ++ Hal_HVSP_SetIPMYCMWriteEn(stCfg->bYCMWrite); ++ Hal_HVSP_SetIPMCIIRReadEn(stCfg->bCIIRRead); ++ Hal_HVSP_SetIPMCIIRWriteEn(stCfg->bCIIRWrite); ++ Drv_HVSP_SetCMDQTrigType(&stCmdTrigCfg); ++ DRV_HVSP_MUTEX_UNLOCK(); ++ return TRUE; ++} ++void Drv_HVSP_SetFbManageConfig(ST_DRV_HVSP_SET_FB_MANAGE_CONFIG *stCfg) ++{ ++ (printf("[DRVHVSP]%s(%d):%x \n", ++ __FUNCTION__, __LINE__, stCfg->enSet)); ++ Hal_HVSP_SetFrameBufferManageLock(0); ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_LDCPATH_ON) ++ { ++ Hal_HVSP_SetLDCPathSel(1); ++ printf("LDC ON\n"); ++ } ++ else if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_LDCPATH_OFF) ++ { ++ Hal_HVSP_SetLDCPathSel(0); ++ printf("LDC OFF\n"); ++ } ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_PRVCROP_ON) ++ { ++ Hal_HVSP_SetPrv2CropOnOff(1); ++ printf("PRVCROP ON\n"); ++ } ++ else if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_PRVCROP_OFF) ++ { ++ Hal_HVSP_SetPrv2CropOnOff(0); ++ printf("PRVCROP OFF\n"); ++ } ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_DNR_Read_ON) ++ { ++ Hal_HVSP_SetIPMYCMReadEn(1); ++ printf("DNRR ON\n"); ++ } ++ else if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_DNR_Read_OFF) ++ { ++ Hal_HVSP_SetIPMYCMReadEn(0); ++ printf("DNRR OFF\n"); ++ } ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_CIIR_ON) ++ { ++ Hal_HVSP_SetIPMCIIRReadEn(1); ++ Hal_HVSP_SetIPMCIIRWriteEn(1); ++ printf("DNRR ON\n"); ++ } ++ else if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_CIIR_OFF) ++ { ++ Hal_HVSP_SetIPMCIIRReadEn(0); ++ Hal_HVSP_SetIPMCIIRWriteEn(0); ++ printf("DNRR OFF\n"); ++ } ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_DNR_Write_ON) ++ { ++ Hal_HVSP_SetIPMYCMWriteEn(1); ++ printf("DNRW ON\n"); ++ } ++ else if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_DNR_Write_OFF) ++ { ++ Hal_HVSP_SetIPMYCMWriteEn(0); ++ printf("DNRW OFF\n"); ++ } ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_1) ++ { ++ Hal_HVSP_SetIPMBufferNumber(1); ++ printf("DNRB 1\n"); ++ } ++ else if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_2) ++ { ++ Hal_HVSP_SetIPMBufferNumber(2); ++ printf("DNRB 2\n"); ++ } ++ Hal_HVSP_SetFrameBufferManageLock(1); ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_UNLOCK) ++ { ++ Hal_HVSP_SetFrameBufferManageLock(0); ++ Drv_SCLIRQ_SetDNRLock(0); ++ printf("UNLOCK\n"); ++ } ++ if(stCfg->enSet & EN_DRV_HVSP_FBMG_SET_LOCK) ++ { ++ Hal_HVSP_SetFrameBufferManageLock(1); ++ Drv_SCLIRQ_SetDNRLock(1); ++ printf("LOCK\n"); ++ } ++} ++ ++void _Drv_HVSP_SetCMDQTrigFire(ST_HVSP_CMD_TRIG_CONFIG *stCmdTrigCfg,EN_HVSP_ID_TYPE HVSP_IP) ++{ ++ MS_U32 u32Events = 0; ++ if(stCmdTrigCfg->enType != E_HVSP_CMD_TRIG_NONE) ++ { ++ if(stCmdTrigCfg->enType == E_HVSP_CMD_TRIG_POLL_LDC_SYNC) ++ { ++ if(HVSP_IP == E_HVSP_ID_3) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SC3EventID(), ++ E_SCLIRQ_SC3EVENT_HVSPST, &u32Events, E_OR, MSOS_WAIT_FOREVER); // get status: FRM END ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SC3EventID(),E_SCLIRQ_SC3EVENT_HVSPST); ++ } ++ else ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_EventID(), ++ E_SCLIRQ_EVENT_HVSPST, &u32Events, E_OR, MSOS_WAIT_FOREVER); // get status: FRM END ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_EventID(),E_SCLIRQ_EVENT_HVSPST); ++ } ++ } ++ Hal_HVSP_SetCMDQTrigFire(); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(HVSP_IP)), ++ "[DRVHVSP]%s id:%d @:%lu\n", __FUNCTION__,HVSP_IP,(MS_U32)MsOS_GetSystemTime()); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(HVSP_IP)), ++ "[DRVHVSP]%s Not Support id:%d @:%lu\n", __FUNCTION__,HVSP_IP,(MS_U32)MsOS_GetSystemTime()); ++ } ++} ++void Drv_HVSP_SetMemoryAllocateReady(MS_BOOL bEn) ++{ ++ gbMemReadyForDrv = bEn; ++} ++MS_U8 _Drv_HVSP_GetScalingHRatioConfig(EN_HVSP_ID_TYPE enHVSP_ID,MS_U8 bUp) ++{ ++ MS_U8 bret = 0; ++ if(bUp) ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ bret = SRAMFORSCALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ bret = SRAMFORSC2ALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ bret = SRAMFORSC3HUP; ++ } ++ } ++ else ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ bret = SRAMFORSCALDOWN; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width >=HD_Width) ++ { ++ bret = SRAMFORSCALDOWN; ++ } ++ else ++ { ++ bret = SRAMFORSC2ALDOWN; ++ } ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ // if sc 2 output > 704x576 use talbe 1. ++ if(gstScalinInfo[E_HVSP_ID_2].stSizeAfterScaling.u16Width >=D_Width) ++ { ++ bret = SRAMFORSC2ALDOWN; ++ } ++ else ++ { ++ bret = SRAMFORSC3HDOWN; ++ } ++ } ++ } ++ return bret; ++} ++MS_U8 _Drv_HVSP_GetScalingVRatioConfig(EN_HVSP_ID_TYPE enHVSP_ID,MS_U8 bUp) ++{ ++ MS_U8 bret = 0; ++ if(bUp) ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ bret = SRAMFORSCALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ bret = SRAMFORSC2ALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ bret = SRAMFORSC3VUP; ++ } ++ } ++ else ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ bret = SRAMFORSCALDOWN; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height >=HD_Height) ++ { ++ bret = SRAMFORSCALDOWN; ++ } ++ else ++ { ++ bret = SRAMFORSC2ALDOWN; ++ } ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ // if sc 2 output > 704x576 use talbe 1. ++ if(gstScalinInfo[E_HVSP_ID_2].stSizeAfterScaling.u16Height >=D_Height) ++ { ++ bret = SRAMFORSCALDOWN; ++ } ++ else ++ { ++ bret = SRAMFORSC3VDOWN; ++ } ++ } ++ } ++ return bret; ++} ++void _Drv_HVSP_SetHorizotnalScalingConfig(EN_HVSP_ID_TYPE enHVSP_ID,MS_BOOL bEn) ++{ ++ ++ Hal_HVSP_SetScalingHoEn(enHVSP_ID, bEn); ++ Hal_HVSP_SetScalingHoFacotr(enHVSP_ID, bEn ? gstScalinInfo[enHVSP_ID].u32ScalingRatio_H: 0); ++ Hal_HVSP_SetModeYHo(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_SRAM_0: E_HVSP_FILTER_MODE_BYPASS); ++ Hal_HVSP_SetModeCHo(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_BILINEAR: E_HVSP_FILTER_MODE_BYPASS,E_HVSP_SRAM_SEL_0); ++ Hal_HVSP_SetHspDithEn(enHVSP_ID,bEn); ++ Hal_HVSP_SetHspCoringEnC(enHVSP_ID,bEn); ++ Hal_HVSP_SetHspCoringEnY(enHVSP_ID,bEn); ++} ++void _Drv_HVSP_SetHTbl(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ if(gbHScalingup[enHVSP_ID] &0x1) ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSCALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSC2ALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSC3HUP; ++ } ++ } ++ else ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSCALDOWN; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width >=HD_Width) ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSCALDOWN; ++ } ++ else ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSC2ALDOWN; ++ } ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ // if sc 2 output > 704x576 use talbe 1. ++ if(gstScalinInfo[E_HVSP_ID_2].stSizeAfterScaling.u16Width >=D_Width) ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSC2ALDOWN; ++ } ++ else ++ { ++ gbHScalingup[enHVSP_ID] = SRAMFORSC3HDOWN; ++ } ++ } ++ } ++} ++void _Drv_HVSP_SetVTbl(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ if(gbVScalingup[enHVSP_ID] &0x1) ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSCALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSC2ALUP; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSC3VUP; ++ } ++ } ++ else ++ { ++ if(enHVSP_ID ==E_HVSP_ID_1) ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSCALDOWN; ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_2) ++ { ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height>=HD_Height) ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSCALDOWN; ++ } ++ else ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSC2ALDOWN; ++ } ++ } ++ else if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ if(gstScalinInfo[E_HVSP_ID_2].stSizeAfterScaling.u16Height >=D_Height) ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSCALDOWN; ++ } ++ else ++ { ++ gbVScalingup[enHVSP_ID] = SRAMFORSC3VDOWN; ++ } ++ } ++ } ++} ++void _Drv_HVSP_SetHorizotnalSRAMTbl(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ MS_U32 u32flag; ++ if((_Change_SRAM_H_Qmap(enHVSP_ID,(gbHScalingup[enHVSP_ID]&0x1)))) ++ { ++ gbHScalingup[enHVSP_ID] &= 0x1; ++ gbHScalingup[enHVSP_ID] = (gbHScalingup[enHVSP_ID]^1);//XOR 1 :reverse ++ //gbHScalingup[enHVSP_ID] |= ((_Drv_HVSP_GetScalingHRatioConfig(enHVSP_ID,gbHScalingup[enHVSP_ID]&0x1))<<4); ++ _Drv_HVSP_SetHTbl(enHVSP_ID); ++ u32flag = (enHVSP_ID==E_HVSP_ID_1) ? E_SCLIRQ_EVENT_SC1HSRAMSET : ++ (enHVSP_ID==E_HVSP_ID_2) ? E_SCLIRQ_EVENT_SC2HSRAMSET : ++ E_SCLIRQ_EVENT_SC3HSRAMSET; ++ if(Drv_SCLIRQ_GetIsBlankingRegion()|| enHVSP_ID ==E_HVSP_ID_3 || VIPSETRULE()) ++ { ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_H_OFFSET),gbHScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change and do H Qmap SRAM id:%d scaling UP:%hhx\n",enHVSP_ID,gbHScalingup[enHVSP_ID]); ++ } ++ else ++ { ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), u32flag); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change H Qmap SRAM id:%d scaling UP:%hhx\n",enHVSP_ID,gbHScalingup[enHVSP_ID]); ++ } ++ } ++ else if(gbSc3FirstHSet && enHVSP_ID ==E_HVSP_ID_3) ++ { ++ gbSc3FirstHSet = 0; ++ _Drv_HVSP_SetHTbl(enHVSP_ID); ++ if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_H_OFFSET),gbHScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change and do H Qmap SRAM id:%d scaling static UP:%hhx\n",enHVSP_ID,gbHScalingup[enHVSP_ID]); ++ } ++ } ++ else if(enHVSP_ID !=E_HVSP_ID_3 && ((_Drv_HVSP_GetScalingHRatioConfig(enHVSP_ID,gbHScalingup[enHVSP_ID]&0x1))!= ++ ((gbHScalingup[enHVSP_ID])))) ++ { ++ //gbHScalingup[enHVSP_ID] &= 0x1; ++ //gbHScalingup[enHVSP_ID] |= ((_Drv_HVSP_GetScalingHRatioConfig(enHVSP_ID,gbHScalingup[enHVSP_ID]&0x1))<<4); ++ _Drv_HVSP_SetHTbl(enHVSP_ID); ++ u32flag = (enHVSP_ID==E_HVSP_ID_1) ? E_SCLIRQ_EVENT_SC1HSRAMSET : ++ (enHVSP_ID==E_HVSP_ID_2) ? E_SCLIRQ_EVENT_SC2HSRAMSET : ++ E_SCLIRQ_EVENT_SC3HSRAMSET; ++ if(Drv_SCLIRQ_GetIsBlankingRegion()|| enHVSP_ID ==E_HVSP_ID_3 || VIPSETRULE()) ++ { ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_H_OFFSET),gbHScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change and do H Qmap SRAM id:%d scaling RUP:%hhx\n",enHVSP_ID,gbHScalingup[enHVSP_ID]); ++ } ++ else ++ { ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), u32flag); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change H Qmap SRAM id:%d scaling RUP:%hhx\n",enHVSP_ID,gbHScalingup[enHVSP_ID]); ++ } ++ } ++} ++void _Drv_HVSP_SetVerticalScalingConfig(EN_HVSP_ID_TYPE enHVSP_ID,MS_BOOL bEn) ++{ ++ Hal_HVSP_SetScalingVeEn(enHVSP_ID, bEn); ++ Hal_HVSP_SetScalingVeFactor(enHVSP_ID, bEn ? gstScalinInfo[enHVSP_ID].u32ScalingRatio_V: 0); ++ Hal_HVSP_SetModeYVe(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_SRAM_0: E_HVSP_FILTER_MODE_BYPASS); ++ Hal_HVSP_SetModeCVe(enHVSP_ID,bEn ? E_HVSP_FILTER_MODE_BILINEAR: E_HVSP_FILTER_MODE_BYPASS,E_HVSP_SRAM_SEL_0); ++ Hal_HVSP_SetVspDithEn(enHVSP_ID,bEn); ++ Hal_HVSP_SetVspCoringEnC(enHVSP_ID,bEn); ++ Hal_HVSP_SetVspCoringEnY(enHVSP_ID,bEn); ++} ++void _Drv_HVSP_SetVerticalSRAMTbl(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ MS_U32 u32flag; ++ if(_Change_SRAM_V_Qmap(enHVSP_ID,(gbVScalingup[enHVSP_ID]&0x1))) ++ { ++ gbVScalingup[enHVSP_ID] &= 0x1; ++ gbVScalingup[enHVSP_ID] = (gbVScalingup[enHVSP_ID]^1);//XOR 1 :reverse ++ //gbVScalingup[enHVSP_ID] |= ((_Drv_HVSP_GetScalingVRatioConfig(enHVSP_ID,gbVScalingup[enHVSP_ID]&0x1))<<4); ++ _Drv_HVSP_SetVTbl(enHVSP_ID); ++ u32flag = (enHVSP_ID==E_HVSP_ID_1) ? E_SCLIRQ_EVENT_SC1VSRAMSET : ++ (enHVSP_ID==E_HVSP_ID_2) ? E_SCLIRQ_EVENT_SC2VSRAMSET : ++ E_SCLIRQ_EVENT_SC3VSRAMSET; ++ ++ if(Drv_SCLIRQ_GetIsBlankingRegion()|| enHVSP_ID ==E_HVSP_ID_3 || VIPSETRULE()) ++ { ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_V_OFFSET),gbVScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change and do V Qmap SRAM id:%d scaling UP:%hhx\n",enHVSP_ID,gbVScalingup[enHVSP_ID]); ++ } ++ else ++ { ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), u32flag); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change V Qmap SRAM id:%d scaling UP:%hhx\n",enHVSP_ID,gbVScalingup[enHVSP_ID]); ++ } ++ } ++ else if(gbSc3FirstVSet && enHVSP_ID ==E_HVSP_ID_3) ++ { ++ gbSc3FirstVSet = 0; ++ _Drv_HVSP_SetVTbl(enHVSP_ID); ++ if(enHVSP_ID ==E_HVSP_ID_3) ++ { ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_V_OFFSET),gbVScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change and do V Qmap SRAM id:%d scaling static UP:%hhx\n",enHVSP_ID,gbVScalingup[enHVSP_ID]); ++ } ++ } ++ else if(enHVSP_ID !=E_HVSP_ID_3 && ((_Drv_HVSP_GetScalingVRatioConfig(enHVSP_ID,gbVScalingup[enHVSP_ID]&0x1))!= ++ ((gbVScalingup[enHVSP_ID])))) ++ { ++ //gbVScalingup[enHVSP_ID] &= 0x1; ++ //gbVScalingup[enHVSP_ID] |= ((_Drv_HVSP_GetScalingVRatioConfig(enHVSP_ID,gbVScalingup[enHVSP_ID]&0x1))<<4); ++ _Drv_HVSP_SetVTbl(enHVSP_ID); ++ u32flag = (enHVSP_ID==E_HVSP_ID_1) ? E_SCLIRQ_EVENT_SC1VSRAMSET : ++ (enHVSP_ID==E_HVSP_ID_2) ? E_SCLIRQ_EVENT_SC2VSRAMSET : ++ E_SCLIRQ_EVENT_SC3VSRAMSET; ++ ++ if(Drv_SCLIRQ_GetIsBlankingRegion()|| enHVSP_ID ==E_HVSP_ID_3 || VIPSETRULE()) ++ { ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_V_OFFSET),gbVScalingup[enHVSP_ID]); //level 1 :up 0:down ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change and do V Qmap SRAM id:%d scaling RUP:%hhx\n",enHVSP_ID,gbVScalingup[enHVSP_ID]); ++ } ++ else ++ { ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), u32flag); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Change V Qmap SRAM id:%d scaling RUP:%hhx\n",enHVSP_ID,gbVScalingup[enHVSP_ID]); ++ } ++ } ++} ++void _Drv_HVSP_SetCrop(MS_BOOL u8CropID,ST_HVSP_SCALING_CONFIG *stCfg,ST_HVSP_CROP_INFO *stCropInfo) ++{ ++ MS_U16 u16In_hsize; ++ MS_U16 u16In_vsize; ++ u16In_hsize = (u8CropID ==DRV_HVSP_CROP_1) ? stCfg->u16Src_Width : stCfg->u16Crop_Width[DRV_HVSP_CROP_1]; ++ u16In_vsize = (u8CropID ==DRV_HVSP_CROP_1) ? stCfg->u16Src_Height : stCfg->u16Crop_Height[DRV_HVSP_CROP_1]; ++ if(stCfg->bCropEn[u8CropID]) ++ { ++ stCropInfo->bEn = stCfg->bCropEn[u8CropID]; ++ if(u16In_hsize && u16In_vsize) ++ { ++ stCropInfo->u16In_hsize = u16In_hsize; ++ stCropInfo->u16In_vsize = u16In_vsize; ++ } ++ else ++ { ++ stCropInfo->u16In_hsize = stCfg->u16Src_Width; ++ stCropInfo->u16In_vsize = stCfg->u16Src_Height; ++ } ++ stCropInfo->u16Hsize = stCfg->u16Crop_Width[u8CropID]; ++ stCropInfo->u16Vsize = stCfg->u16Crop_Height[u8CropID]; ++ if(stCfg->u16Crop_Width[u8CropID]%2) ++ { ++ stCropInfo->u16Hsize = stCfg->u16Crop_Width[u8CropID]-1; ++ } ++ if(u8CropID == DRV_HVSP_CROP_1) ++ { ++ gstIPMCfg.u16Fetch = stCropInfo->u16Hsize; ++ gstIPMCfg.u16Vsize = stCropInfo->u16Vsize; ++ Drv_HVSP_SetInputSrcSize(stCfg->u16Src_Width,stCfg->u16Src_Height); ++ } ++ if(stCfg->u16Crop_X[u8CropID]%2) ++ { ++ stCropInfo->u16Hst = stCfg->u16Crop_X[u8CropID]-1; ++ } ++ else ++ { ++ stCropInfo->u16Hst = stCfg->u16Crop_X[u8CropID]; ++ } ++ stCropInfo->u16Vst = stCfg->u16Crop_Y[u8CropID]; ++ } ++ else ++ { ++ stCropInfo->bEn = 0; ++ if(u16In_hsize && u16In_vsize) ++ { ++ stCropInfo->u16In_hsize = u16In_hsize; ++ stCropInfo->u16In_vsize = u16In_vsize; ++ stCropInfo->u16Hsize = u16In_hsize;//stCfg.u16Src_Width; ++ stCropInfo->u16Vsize = u16In_vsize;//stCfg.u16Src_Height; ++ } ++ else ++ { ++ stCropInfo->u16In_hsize = stCfg->u16Src_Width; ++ stCropInfo->u16In_vsize = stCfg->u16Src_Height; ++ stCropInfo->u16Hsize = stCfg->u16Src_Width;//stCfg.u16Src_Width; ++ stCropInfo->u16Vsize = stCfg->u16Src_Height;//stCfg.u16Src_Height; ++ } ++ if(u8CropID == DRV_HVSP_CROP_1) ++ { ++ gstIPMCfg.u16Fetch = stCropInfo->u16Hsize; ++ gstIPMCfg.u16Vsize = stCropInfo->u16Vsize; ++ Drv_HVSP_SetInputSrcSize(stCropInfo->u16In_hsize,stCropInfo->u16In_vsize); ++ } ++ stCropInfo->u16Hst = 0; ++ stCropInfo->u16Vst = 0; ++ } ++} ++void _Drv_HVSP_SetScalingRetVal(ST_HVSP_CROP_INFO *stCropInfo_1, ST_HVSP_CROP_INFO *stCropInfo_2, ST_HVSP_SCALING_CONFIG *stCfg) ++{ ++ stCfg->bCropEn[DRV_HVSP_CROP_1] = stCropInfo_1->bEn; ++ stCfg->u16Crop_Height[DRV_HVSP_CROP_1] = stCropInfo_1->u16Vsize; ++ stCfg->u16Crop_Width[DRV_HVSP_CROP_1] = stCropInfo_1->u16Hsize; ++ stCfg->u16Crop_X[DRV_HVSP_CROP_1] = stCropInfo_1->u16Hst; ++ stCfg->u16Crop_Y[DRV_HVSP_CROP_1] = stCropInfo_1->u16Vst; ++ stCfg->bCropEn[DRV_HVSP_CROP_2] = stCropInfo_2->bEn; ++ stCfg->u16Crop_Height[DRV_HVSP_CROP_2] = stCropInfo_2->u16Vsize; ++ stCfg->u16Crop_Width[DRV_HVSP_CROP_2] = stCropInfo_2->u16Hsize; ++ stCfg->u16Crop_X[DRV_HVSP_CROP_2] = stCropInfo_2->u16Hst; ++ stCfg->u16Crop_Y[DRV_HVSP_CROP_2] = stCropInfo_2->u16Vst; ++} ++MS_BOOL Drv_HVSP_SetScaling(EN_HVSP_ID_TYPE enHVSP_ID, ST_HVSP_SCALING_CONFIG *stCfg, ST_HVSP_CLK_CONFIG* stclk) ++{ ++ unsigned char u8FBbuffer = Drv_HVSP_GetBufferNum(); ++ EN_HVSP_ISPCLK_TYPE enISPClkType = Hal_HVSP_GetISPClkType(); ++ ST_HVSP_CROP_INFO stCropInfo_2; ++ ST_HVSP_CROP_INFO stCropInfo_1; ++ MS_U16 u16Hst = Hal_HVSP_Get_Crop_X(); ++ MS_U16 u16Vst = Hal_HVSP_Get_Crop_Y(); ++ MS_BOOL bChangePreCropPosition = 0; ++ MS_U16 u16FBWidth = gstIPMCfg.u16Fetch; ++ MS_U16 u16FBHeight = gstIPMCfg.u16Vsize; ++ MS_U32 u32bLDCEvent = 0; ++ MS_U64 u64temp; ++ MsOS_Memset(&stCropInfo_2,0,sizeof(ST_HVSP_CROP_INFO)); ++ MsOS_Memset(&stCropInfo_1,0,sizeof(ST_HVSP_CROP_INFO)); ++ stCropInfo_1.bEn = 0; ++ stCropInfo_2.bEn = 0; ++ stCfg->bRet = 1; ++ if(enHVSP_ID == E_HVSP_ID_1) ++ { ++ MS_U32 u32FrameBufferMemSize = gstIPMCfg.u32MemSize; ++ MS_U32 u32ReqMemSize = stCfg->u16Src_Width * stCfg->u16Src_Height * 2 * u8FBbuffer; ++ ++ ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), "[DRVHVSP]%s id:%d @:%lu\n", ++ __FUNCTION__,enHVSP_ID,(MS_U32)MsOS_GetSystemTime()); ++ ++ if(Is_DNRBufferReady()) ++ { ++ if(Is_FrameBufferTooSmall(u32ReqMemSize, u32FrameBufferMemSize)) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: Out of memory\n", __FUNCTION__, __LINE__)); ++ stCfg->bRet = 0; ++ return stCfg->bRet; ++ } ++ } ++ else ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: Can't Use DNR (FB Not Ready)\n", __FUNCTION__, __LINE__)); ++ if(Is_FrameBufferTooSmall(u32ReqMemSize, u32FrameBufferMemSize)) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s %d:: Out of memory\n", __FUNCTION__, __LINE__)); ++ } ++ } ++ if(stCfg->u16Src_Width != gstIPMCfg.u16Fetch) ++ { ++ SCL_DBGERR("[DRVHVSP]%s %d:: H Src Size Mismatch(%hd,%hd)\n", ++ __FUNCTION__, __LINE__,stCfg->u16Src_Width,gstIPMCfg.u16Fetch); ++ } ++ if(stCfg->u16Src_Height != gstIPMCfg.u16Vsize) ++ { ++ SCL_DBGERR("[DRVHVSP]%s %d:: V Src Size Mismatch(%hd,%hd)\n", ++ __FUNCTION__, __LINE__,stCfg->u16Src_Height,gstIPMCfg.u16Vsize); ++ } ++ ++ // setup cmd trig config ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_HVSP_SetCMDQTrigType(&stCfg->stCmdTrigCfg); ++ _Drv_HVSP_SetCrop(DRV_HVSP_CROP_1,stCfg,&stCropInfo_1); ++ _Drv_HVSP_SetCrop(DRV_HVSP_CROP_2,stCfg,&stCropInfo_2); ++ if(_Is_SingleBufferAndZoomSizeBiggerthanLimitation ++ (u8FBbuffer,stCropInfo_2.u16Vsize, Hal_HVSP_GetLimitationByISPClk ++ (enISPClkType, stCropInfo_1.u16Hsize ,stCfg->u16Dsp_Height))) ++ { ++ if(stCfg->bCropEn[DRV_HVSP_CROP_1]) ++ { ++ stCfg->u16Crop_Height[DRV_HVSP_CROP_1] = ++ Hal_HVSP_GetLimitationByISPClk(enISPClkType, stCropInfo_1.u16Hsize ,stCfg->u16Dsp_Height) ; ++ stCropInfo_1.u16Vsize = stCfg->u16Crop_Height[DRV_HVSP_CROP_1]; ++ stCropInfo_1.u16Vst = ((stCropInfo_1.u16Vst+stCropInfo_1.u16Vsize)>stCropInfo_1.u16In_vsize) ? ++ (stCropInfo_1.u16In_vsize - stCropInfo_1.u16Vsize) : stCropInfo_1.u16Vst; ++ gstIPMCfg.u16Vsize = stCropInfo_1.u16Vsize; ++ stCropInfo_2.u16In_vsize = gstIPMCfg.u16Vsize; ++ stCropInfo_2.u16Vsize = gstIPMCfg.u16Vsize;//stCfg.u16Src_Height; ++ SCL_ERR("[DRVHVSP]%s %d:: Buffer num : %hhd ,Zoom size bigger than Limitation and force to change(%hd,%hd,%hd,%hd)\n" ++ , __FUNCTION__, __LINE__,u8FBbuffer,stCropInfo_1.u16Hst,stCropInfo_1.u16Vst, ++ stCfg->u16Crop_Width[DRV_HVSP_CROP_1],stCfg->u16Crop_Height[DRV_HVSP_CROP_1]); ++ } ++ if(stCfg->bCropEn[DRV_HVSP_CROP_2]) ++ { ++ stCfg->u16Crop_Height[DRV_HVSP_CROP_2] = ++ Hal_HVSP_GetLimitationByISPClk(enISPClkType, stCropInfo_2.u16Hsize ,stCfg->u16Dsp_Height); ++ stCropInfo_2.u16Vsize = stCfg->u16Crop_Height[DRV_HVSP_CROP_2]; ++ stCropInfo_2.u16Vst = ((stCropInfo_2.u16Vst+stCropInfo_2.u16Vsize)>stCropInfo_2.u16In_vsize) ? ++ (stCropInfo_2.u16In_vsize - stCropInfo_2.u16Vsize) : stCropInfo_2.u16Vst; ++ SCL_ERR("[DRVHVSP]%s %d:: Buffer num : %hhd ,Zoom size bigger than Limitation and force to change(%hd,%hd,%hd,%hd)\n" ++ , __FUNCTION__, __LINE__,u8FBbuffer,stCropInfo_2.u16Hst,stCropInfo_2.u16Vst, ++ stCfg->u16Crop_Width[DRV_HVSP_CROP_2],stCfg->u16Crop_Height[DRV_HVSP_CROP_2]); ++ } ++ _Drv_HVSP_SetScalingRetVal(&stCropInfo_1,&stCropInfo_2,stCfg); ++ stCfg->bRet = 0; ++ } ++ ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width = stCropInfo_2.u16Hsize;//stCfg.u16Src_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height = stCropInfo_2.u16Vsize;//stCfg.u16Src_Height; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width = stCfg->u16Dsp_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height = stCfg->u16Dsp_Height; ++ gstIPMCfg.u16Fetch = stCropInfo_2.u16In_hsize; ++ gstIPMCfg.u16Vsize = stCropInfo_2.u16In_vsize; ++ // Crop1 ++ Hal_HVSP_SetCropConfig(E_HVSP_CROP_ID_1, &stCropInfo_1); ++ // Crop2 ++ Hal_HVSP_SetCropConfig(E_HVSP_CROP_ID_2, &stCropInfo_2); ++ Hal_HVSP_SetIPMvSize(stCropInfo_2.u16In_vsize); ++ Hal_HVSP_SetIPMLineOffset(stCropInfo_2.u16In_hsize); ++ Hal_HVSP_SetIPMFetchNum(stCropInfo_2.u16In_hsize); ++ Hal_HVSP_SetLDCWidth(stCropInfo_2.u16In_hsize); ++ Hal_HVSP_SetLDCHeight(stCropInfo_2.u16In_vsize); ++ if(stCfg->bCropEn[DRV_HVSP_CROP_1]) ++ { ++ // ToDo ++ //for rotate ++ if(stCropInfo_2.u16In_hsize <= FHD_Width && stCropInfo_2.u16In_vsize <= FHD_Width) ++ { ++ Drv_HVSP_SetPrv2CropOnOff(0); ++ Hal_HVSP_SetLDCPathSel(stCfg->bCropEn[DRV_HVSP_CROP_1]); ++ u32bLDCEvent = stCfg->bCropEn[DRV_HVSP_CROP_1]; ++ } ++ else ++ { ++ Hal_HVSP_SetLDCPathSel(0); ++ u32bLDCEvent = 0; ++ // disable for BW issue ++ //Drv_HVSP_SetPrv2CropOnOff(stCfg.bCropEn[DRV_HVSP_CROP_1]); ++ } ++ } ++ else ++ { ++ if(Hal_HVSP_GetPrv2CropOnOff()) ++ { ++ Drv_HVSP_SetPrv2CropOnOff(stCfg->bCropEn[DRV_HVSP_CROP_1]); ++ } ++ //for rotate ++ else if(gstSrcSize.u16Width >FHD_Width || gstSrcSize.u16Height >FHD_Width) ++ { ++ Hal_HVSP_SetLDCPathSel(stCfg->bCropEn[DRV_HVSP_CROP_1]); ++ u32bLDCEvent = stCfg->bCropEn[DRV_HVSP_CROP_1]; ++ } ++ else ++ { ++ u32bLDCEvent = Hal_HVSP_GetLDCPathSel(); ++ } ++ } ++ // NLM size ++ Hal_HVSP_SetVIPSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_SetNLMLineBufferSize(stCropInfo_2.u16In_hsize,stCropInfo_2.u16In_vsize); ++ Hal_HVSP_SetNLMEn(1); ++ //AIP size ++ Hal_HVSP_SetXNRSize(stCropInfo_2.u16In_hsize,stCropInfo_2.u16In_vsize); ++ Hal_HVSP_SetWDRGlobalSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_SetWDRLocalSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_SetMXNRSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_SetUVadjSize(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ Hal_HVSP_PriMask_Width(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width); ++ Hal_HVSP_PriMask_Height(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ if(gbPriMaskPending) ++ { ++ gbPriMaskPending = 0; ++ Hal_HVSP_PriMask_bEn(EN_HVSP_TRIGGER_CMDQ); ++ } ++ bChangePreCropPosition = _IsChangePreCropPosition(stCropInfo_1.u16Hst,stCropInfo_1.u16Vst,u16Hst,u16Vst); ++ } ++ else ++ { ++ if(enHVSP_ID == E_HVSP_ID_3 &&_IsFlagType(E_SCLDMA_3_FRM_W,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ stCfg->bRet = 0; ++ return stCfg->bRet; ++ } ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_HVSP_SetCMDQTrigType(&stCfg->stCmdTrigCfg); ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width = stCfg->u16Src_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height = stCfg->u16Src_Height; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width = stCfg->u16Dsp_Width; ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height = stCfg->u16Dsp_Height; ++ } ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width>1 && (gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width>1)) ++ { ++ u64temp = (((MS_U64)gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width) * 1048576); ++ do_div(u64temp, gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width); ++ gstScalinInfo[enHVSP_ID].u32ScalingRatio_H = (MS_U32)u64temp; ++ } ++ else ++ { ++ SCL_ERR("[DRVHVSP]%d Ratio Error\n",enHVSP_ID); ++ } ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height>1 && (gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height>1)) ++ { ++ u64temp = (((MS_U64)gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height) * 1048576); ++ do_div(u64temp, gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++ gstScalinInfo[enHVSP_ID].u32ScalingRatio_V = (MS_U32)u64temp; ++ } ++ else ++ { ++ SCL_ERR("[DRVHVSP]%d Ratio Error\n",enHVSP_ID); ++ } ++/* ++ gstScalinInfo[enHVSP_ID].u32ScalingRatio_H = (MS_U32)HVSP_RATIO(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width); ++ ++ gstScalinInfo[enHVSP_ID].u32ScalingRatio_V = (MS_U32)HVSP_RATIO(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++*/ ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]%s(%d):: HVSP_%d, AfterCrop(%d, %d)\n", __FUNCTION__, __LINE__, ++ enHVSP_ID, gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]%s(%d):: HVSP_%d, AfterScaling(%d, %d)\n", __FUNCTION__, __LINE__, ++ enHVSP_ID, gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width, gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]%s(%d):: HVSP_%d, Ratio(%lx, %lx)\n", __FUNCTION__, __LINE__, ++ enHVSP_ID, gstScalinInfo[enHVSP_ID].u32ScalingRatio_H, gstScalinInfo[enHVSP_ID].u32ScalingRatio_V); ++ ++ // horizotnal HVSP Scaling ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width == gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width) ++ { ++ _Drv_HVSP_SetHorizotnalScalingConfig(enHVSP_ID, FALSE); ++ } ++ else ++ { ++ _Drv_HVSP_SetHorizotnalScalingConfig(enHVSP_ID, TRUE); ++ _Drv_HVSP_SetHorizotnalSRAMTbl(enHVSP_ID); ++ } ++ ++ // vertical HVSP Scaling ++ if(gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height == gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height) ++ { ++ _Drv_HVSP_SetVerticalScalingConfig(enHVSP_ID, FALSE); ++ } ++ else ++ { ++ _Drv_HVSP_SetVerticalScalingConfig(enHVSP_ID, TRUE); ++ _Drv_HVSP_SetVerticalSRAMTbl(enHVSP_ID); ++ } ++ ++ // HVSP In size ++ Hal_HVSP_SetHVSPInputSize(enHVSP_ID, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterCrop.u16Height); ++ ++ // HVSP Out size ++ Hal_HVSP_SetHVSPOutputSize(enHVSP_ID, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Width, ++ gstScalinInfo[enHVSP_ID].stSizeAfterScaling.u16Height); ++ if(enHVSP_ID == E_HVSP_ID_3) ++ { ++ if(!gbclkforcemode) ++ { ++ Hal_HVSP_FCLK2(stclk); ++ } ++ } ++ else ++ { ++ if(!gbclkforcemode) ++ { ++ Hal_HVSP_FCLK1(stclk); ++ } ++ } ++ if(ISZOOMDROPFRAME) ++ { ++ _Drv_HVSP_SetCMDQTrigFire(&stCfg->stCmdTrigCfg,enHVSP_ID); ++ if(_IsChangeFBBufferResolution(u16FBWidth,u16FBHeight) || bChangePreCropPosition) ++ { ++ //for 3DNR ++ Drv_SCLIRQ_SetDropFrameFromCMDQDone(1); ++ } ++ } ++ else ++ { ++ if(_IsChangeFBBufferResolution(u16FBWidth,u16FBHeight) || bChangePreCropPosition) ++ { ++ if(u32bLDCEvent) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)),"[DRVHVSP]Without Drop frame LDC close\n"); ++ Hal_HVSP_SetResetDNR(1); ++ _Drv_HVSP_SetCMDQTrigFire(&stCfg->stCmdTrigCfg,enHVSP_ID); ++#if SCALING_BLOCK ++#else ++ if(Drv_SCLIRQ_GetEachDMAEn()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_CHANGESIZEDONE, &u32bLDCEvent, E_OR, 100); ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_CHANGESIZEDONE)); ++ } ++#endif ++ Hal_HVSP_SetLDCPathSel(1); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)),"[DRVHVSP]Without Drop frame \n"); ++ Hal_HVSP_SetResetDNR(1); ++ } ++ } ++ _Drv_HVSP_SetCMDQTrigFire(&stCfg->stCmdTrigCfg,enHVSP_ID); ++ } ++#if SCALING_BLOCK ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)),"[DRVHVSP]Set Scaling factor Done\n"); ++#endif ++/* ++ if(stCfg.bCropEn[DRV_HVSP_CROP_1]) ++ { ++ Drv_HVSP_SetCMDQTrigType(stCfg.stCmdTrigCfg); ++ _Drv_HVSP_SetCMDQTrigFire(stCfg.stCmdTrigCfg,enHVSP_ID); ++ } ++*/ ++ DRV_HVSP_MUTEX_UNLOCK(); ++ stCfg->bRet = 1; ++ return stCfg->bRet; ++} ++void Drv_HVSP_SetInputSrcSize(MS_U16 u16Height,MS_U16 u16Width) ++{ ++ if(u16Height > 0) ++ { ++ gstSrcSize.u16Height = u16Height; ++ } ++ if(u16Width > 0) ++ { ++ gstSrcSize.u16Width = u16Width; ++ } ++ gstSrcSize.bSet = 1; ++ Hal_HVSP_SetInputSrcSize(&gstSrcSize); ++} ++void Drv_HVSP_SetCropWindowSize(void) ++{ ++ ST_HVSP_CROP_INFO stCropInfo_1; ++ ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg; ++ MsOS_Memset(&stCropInfo_1,0,sizeof(ST_HVSP_CROP_INFO)); ++ MsOS_Memset(&stCmdTrigCfg,0,sizeof(ST_HVSP_CMD_TRIG_CONFIG)); ++ _Drv_HVSP_FillPreCropInfo(&stCropInfo_1); ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_HVSP_SetCMDQTrigTypeByRIU(&stCmdTrigCfg); ++ Hal_HVSP_SetCropConfig(E_HVSP_CROP_ID_1, &stCropInfo_1); ++ Drv_HVSP_SetCMDQTrigType(&stCmdTrigCfg); ++ DRV_HVSP_MUTEX_UNLOCK(); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s Input:(%hd,%hd) Crop:(%hd,%hd)\n", __FUNCTION__, ++ stCropInfo_1.u16In_hsize,stCropInfo_1.u16In_vsize,stCropInfo_1.u16Hsize,stCropInfo_1.u16Vsize); ++} ++ ++EN_HVSP_IP_MUX_TYPE Drv_HVSP_GetInputSrcMux(void) ++{ ++ return Hal_HVSP_GetInputSrcMux(); ++} ++ ++MS_BOOL Drv_HVSP_SetInputMux(EN_HVSP_IP_MUX_TYPE enIP,ST_HVSP_CLK_CONFIG* stclk) ++{ ++ DRV_HVSP_DBG(printf("[DRVHVSP]%s(%d): IP=%x\n", __FUNCTION__, __LINE__,enIP)); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s(%d): IP=%x\n", __FUNCTION__, __LINE__,enIP); ++ Hal_HVSP_SetInputMuxType(enIP); ++ if(!gbclkforcemode && stclk != NULL) ++ { ++ Hal_HVSP_SetIdclkOnOff(1,stclk); ++ } ++ if(enIP >= E_HVSP_IP_MUX_MAX) ++ { ++ DRV_HVSP_ERR(printf("[DRVHVSP]%s(%d):: Wrong IP Type\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ Hal_HVSP_SetHWInputMux(enIP); ++ return TRUE; ++} ++ ++MS_BOOL Drv_HVSP_SetRegisterForce(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Msk) ++{ ++ Hal_HVSP_Set_Reg(u32Reg, u8Val, u8Msk); ++ return TRUE; ++} ++void Drv_HVSP_SetSCIQVSRAM(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Doing V Qmap SRAM id:%d scaling UP:%hhx\n",enHVSP_ID,gbVScalingup[enHVSP_ID]); ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_V_OFFSET),gbVScalingup[enHVSP_ID]); //level 1 :up 0:down ++} ++void Drv_HVSP_SetSCIQHSRAM(EN_HVSP_ID_TYPE enHVSP_ID) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(enHVSP_ID)), ++ "[DRVHVSP]Doing H Qmap SRAM id:%d scaling UP:%hhx\n",enHVSP_ID,gbHScalingup[enHVSP_ID]); ++ Hal_HVSP_SRAM_Dump((EN_HVSP_SRAM_DUMP_TYPE)(enHVSP_ID+HVSP_ID_SRAM_H_OFFSET),gbHScalingup[enHVSP_ID]); //level 1 :up 0:down ++} ++void Drv_HVSP_SetOSDConfig(EN_HVSP_ID_TYPE enID, ST_DRV_HVSP_OSD_CONFIG *stOSdCfg) ++{ ++ Hal_HVSP_SetOSDLocate(enID,stOSdCfg->enOSD_loc); ++ Hal_HVSP_SetOSDOnOff(enID,stOSdCfg->stOsdOnOff.bOSDEn); ++ Hal_HVSP_SetOSDbypass(enID,stOSdCfg->stOsdOnOff.bOSDBypass); ++ Hal_HVSP_SetOSDbypassWTM(enID,stOSdCfg->stOsdOnOff.bWTMBypass); ++} ++void _Drv_HVSP_SetPriMaskBufferByByte(unsigned char * pu8Addr,unsigned char u8MaskVal) ++{ ++ *pu8Addr = u8MaskVal; ++} ++void _Drv_HVSP_SetPriMaskBufferByBit(unsigned char * pu8Addr,unsigned char u8MaskVal,unsigned char mask) ++{ ++ unsigned char u8val; ++ u8val = *pu8Addr; ++ *pu8Addr = ((u8val&mask)|u8MaskVal); ++} ++unsigned char _Drv_HVSP_GetPriMaskBufferByByte(unsigned char * pu8Addr) ++{ ++ unsigned char u8val; ++ u8val = *pu8Addr; ++ return u8val; ++} ++unsigned char * _Drv_HVSP_GetPriMaskStartPoint(unsigned short u16X,unsigned short u16Y) ++{ ++ unsigned char *pu8StartPoint; ++ unsigned short u16newX; ++ unsigned short u16newY; ++ u16newX = (u16X/HVSP_PRIMASK_BLOCK_SIZE); // bit/shift,ex.300 ->300/32 = 9.xx ->bit9 start(9th end is 288 10th start is 289) ++ u16newY = (u16Y/HVSP_PRIMASK_BLOCK_SIZE); // bit/shift (line) ++ pu8StartPoint = gpu8PriMaskBuf + (HVSP_PRIMASK_Width_SIZE*(u16newY))+(u16newX/BYTESIZE); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s u16newX = %hd,u16newY = %hd,pu8StartPoint = %lx\n" ++ ,__FUNCTION__, u16newX,u16newY,(unsigned long)pu8StartPoint); ++ return pu8StartPoint; ++} ++unsigned short _Drv_HVSP_GetPriMaskOffsetbit(unsigned short u16P) ++{ ++ unsigned short u16Offsetbit; ++ unsigned short u16Xbyte; ++ u16Offsetbit = u16P/HVSP_PRIMASK_BLOCK_SIZE; // bit/shift,ex.300 ->300/32 = 9.xx ->bit9 start(9th end is 288 10th start is 289) ++ u16Xbyte = u16Offsetbit/BYTESIZE; ++ u16Offsetbit = u16Offsetbit - (u16Xbyte*BYTESIZE); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s offset = %hd\n",__FUNCTION__, u16Offsetbit); ++ return u16Offsetbit; ++} ++unsigned short _Drv_HVSP_GetPriMaskXOffset ++ (unsigned short u16P,unsigned short u16Leng) ++{ ++ unsigned short u16Offeset; ++ unsigned short u16Offsetnow; ++ unsigned short u16lastOffeset; ++ unsigned short u16XOffset=0; ++ u16Offeset = u16Leng;//256 ++ u16Offsetnow = (u16P/HVSP_PRIMASK_BLOCK_SIZE);// 4 ++ u16Offsetnow = u16Offsetnow/BYTESIZE;// 0 ++ u16lastOffeset = ((u16Offeset)/HVSP_PRIMASK_BLOCK_SIZE);// 8 ++ u16lastOffeset = u16lastOffeset/BYTESIZE;// 1 ++ if(u16Offeset%(BYTESIZE*HVSP_PRIMASK_BLOCK_SIZE)) ++ { ++ u16XOffset = u16lastOffeset-u16Offsetnow+1;// 2 ++ } ++ else ++ { ++ u16XOffset = u16lastOffeset-u16Offsetnow;// 1 full byte ++ } ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s offset = %hd\n",__FUNCTION__, u16XOffset); ++ return u16XOffset; ++} ++unsigned short _Drv_HVSP_GetPriMaskOffset(unsigned short u16Leng) ++{ ++ unsigned short u16newOffeset; ++ u16newOffeset = u16Leng/HVSP_PRIMASK_BLOCK_SIZE; ++ if(((u16Leng)%HVSP_PRIMASK_BLOCK_SIZE)>(HVSP_PRIMASK_BLOCK_SIZE/2)) ++ { ++ u16newOffeset+=1; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s offset = %hd\n",__FUNCTION__, u16newOffeset); ++ return u16newOffeset; ++} ++void Drv_HVSP_SetPriMaskConfig(ST_HVSP_PRIMASK_CONFIG *stCfg) ++{ ++ unsigned char *pu8StartPoint; ++ unsigned short u16X;//x ++ unsigned short u16Y;//x ++ unsigned short u16Xend;//x+width ++ unsigned short u16XStartoffsetbit;//first byte ++ unsigned short u16XEndoffsetbit;//last byte ++ unsigned short u16Xoffset; ++ unsigned short u16Yoffset; ++ unsigned short u16idx; ++ unsigned short u16idy; ++ unsigned char u8mask; ++ unsigned char u8orimask; ++ u16X = ((stCfg->u16X/HVSP_PRIMASK_BLOCK_SIZE)*HVSP_PRIMASK_BLOCK_SIZE); ++ if((stCfg->u16X%HVSP_PRIMASK_BLOCK_SIZE)>(HVSP_PRIMASK_BLOCK_SIZE/2)) ++ { ++ u16X+=HVSP_PRIMASK_BLOCK_SIZE; ++ } ++ u16Y = ((stCfg->u16Y/HVSP_PRIMASK_BLOCK_SIZE)*HVSP_PRIMASK_BLOCK_SIZE); ++ if((stCfg->u16Y%HVSP_PRIMASK_BLOCK_SIZE)>(HVSP_PRIMASK_BLOCK_SIZE/2)) ++ { ++ u16Y+=HVSP_PRIMASK_BLOCK_SIZE; ++ } ++ u16Xend = (((stCfg->u16X+stCfg->u16Width)/HVSP_PRIMASK_BLOCK_SIZE)*HVSP_PRIMASK_BLOCK_SIZE); ++ if(((stCfg->u16X+stCfg->u16Width)%HVSP_PRIMASK_BLOCK_SIZE)>(HVSP_PRIMASK_BLOCK_SIZE/2)) ++ { ++ u16Xend+=HVSP_PRIMASK_BLOCK_SIZE; ++ } ++ pu8StartPoint = _Drv_HVSP_GetPriMaskStartPoint(u16X,u16Y);//byte/unit ++ u16XStartoffsetbit = _Drv_HVSP_GetPriMaskOffsetbit(u16X);// bit/unit ++ u16XEndoffsetbit = _Drv_HVSP_GetPriMaskOffsetbit(u16Xend);// bit/unit ++ if(u16XEndoffsetbit) ++ { ++ u16XEndoffsetbit = BYTESIZE-u16XEndoffsetbit; ++ } ++ u16Xoffset = _Drv_HVSP_GetPriMaskXOffset(u16X,u16Xend);//byte/unit ++ u16Yoffset = _Drv_HVSP_GetPriMaskOffset(stCfg->u16Height);// bit/unit ++ for(u16idy = 0;u16idybMask) ? 0xFF :0; ++ if(Is_StartAndEndInSameByte(u16XStartoffsetbit,u16idx,u16Xoffset)) ++ { ++ u8orimask = _Drv_HVSP_GetPriMaskBufferByByte(pu8StartPoint+(u16idy*HVSP_PRIMASK_Width_SIZE)); ++ if(stCfg->bMask) ++ { ++ u8mask = u8orimask | ((0xFF>>u16XEndoffsetbit)&(0xFF<>u16XEndoffsetbit)&(0xFF<bMask) ++ { ++ u8mask = u8orimask | (u8mask&(0xFF<bMask) ++ { ++ u8mask = u8orimask | (u8mask&(0xFF>>(u16XEndoffsetbit))); ++ } ++ else ++ { ++ u8mask = u8orimask &(~(0xFF>>(u16XEndoffsetbit))); ++ } ++ } ++ _Drv_HVSP_SetPriMaskBufferByByte(pu8StartPoint+u16idx+(u16idy*HVSP_PRIMASK_Width_SIZE),u8mask); ++ } ++ } ++} ++unsigned short Drv_HVSP_PriMaskGetSRAM(unsigned char u8idx, unsigned char u8idy) ++{ ++ unsigned short u16val = 0; ++ unsigned char* p8valpoint; ++ p8valpoint = (unsigned char*)gpu8PriMaskBuf; ++ u16val = 0; ++ if(u8idx==(HVSP_PRIMASK_Width_SIZE/2)) ++ { ++ u16val = (*(p8valpoint+(u8idx*2)+(u8idy*HVSP_PRIMASK_Width_SIZE))); ++ } ++ else ++ { ++ u16val = (*(p8valpoint+(u8idx*2)+(u8idy*HVSP_PRIMASK_Width_SIZE))| ++ (*(p8valpoint+(u8idx*2)+1+(u8idy*HVSP_PRIMASK_Width_SIZE)))<<8); ++ } ++ return u16val; ++} ++void _Drv_HVSP_PriMaskFillSRAM(void) ++{ ++ unsigned char u8idx = 0; ++ unsigned char u8idy = 0; ++ unsigned short u16val = 0; ++ unsigned char* p8valpoint; ++ p8valpoint = (unsigned char*)gpu8PriMaskBuf; ++ _Drv_HVSP_PriMaskInit(); ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ for(u8idy = 0;u8idyu16X = Hal_HVSP_GetCrop2Xinfo(); ++ stInformCfg->u16Y = Hal_HVSP_GetCrop2Yinfo(); ++ stInformCfg->u16Width = Hal_HVSP_GetHVSPOutputWidth(enID); ++ stInformCfg->u16Height = Hal_HVSP_GetHVSPOutputHeight(enID); ++ stInformCfg->u16crop2inWidth = Hal_HVSP_GetCrop2InputWidth(); ++ stInformCfg->u16crop2inHeight = Hal_HVSP_GetCrop2InputHeight(); ++ stInformCfg->u16crop2OutWidth = Hal_HVSP_GetCrop2OutputWidth(); ++ stInformCfg->u16crop2OutHeight = Hal_HVSP_GetCrop2OutputHeight(); ++ stInformCfg->bEn = Hal_HVSP_GetCrop2En(); ++ return TRUE; ++} ++MS_BOOL Drv_HVSP_GetHVSPAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_HVSPINFORM_CONFIG *stInformCfg) ++{ ++ stInformCfg->u16Width = Hal_HVSP_GetHVSPOutputWidth(enID); ++ stInformCfg->u16Height = Hal_HVSP_GetHVSPOutputHeight(enID); ++ stInformCfg->u16inWidth = Hal_HVSP_GetHVSPInputWidth(enID); ++ stInformCfg->u16inHeight = Hal_HVSP_GetHVSPInputHeight(enID); ++ stInformCfg->bEn = Hal_HVSP_GetScalingFunctionStatus(enID); ++ stInformCfg->bEn |= (gbVScalingup[enID]&0xF0); ++ stInformCfg->bEn |= ((gbHScalingup[enID]&0xF0)<<2); ++ return TRUE; ++} ++void Drv_HVSP_GetOSDAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_OSD_CONFIG *stOsdCfg) ++{ ++ stOsdCfg->enOSD_loc = Hal_HVSP_GetOSDLocate(enID); ++ stOsdCfg->stOsdOnOff.bOSDEn = Hal_HVSP_GetOSDOnOff(enID); ++ stOsdCfg->stOsdOnOff.bOSDBypass = Hal_HVSP_GetOSDbypass(enID); ++ stOsdCfg->stOsdOnOff.bWTMBypass = Hal_HVSP_GetOSDbypassWTM(enID); ++} ++MS_BOOL Drv_HVSP_GetFrameBufferAttribute(EN_HVSP_ID_TYPE enID,ST_HVSP_IPM_CONFIG *stInformCfg) ++{ ++ MS_BOOL bLDCorPrvCrop; ++ stInformCfg->bYCMWrite = gstIPMCfg.bYCMWrite; ++ stInformCfg->u16Fetch = gstIPMCfg.u16Fetch; ++ stInformCfg->u16Vsize = gstIPMCfg.u16Vsize; ++ stInformCfg->u32YCBaseAddr = gstIPMCfg.u32YCBaseAddr+0x20000000; ++ stInformCfg->u32MemSize = gstIPMCfg.u32MemSize; ++ stInformCfg->bYCMRead = gstIPMCfg.bYCMRead; ++ bLDCorPrvCrop = (Hal_HVSP_GetLDCPathSel()) ? 1 : ++ (Hal_HVSP_GetPrv2CropOnOff())? 2 : 0; ++ return bLDCorPrvCrop; ++} ++MS_BOOL Drv_HVSP_SetLDCFrameBuffer_Config(ST_HVSP_LDC_FRAMEBUFFER_CONFIG *stLDCCfg) ++{ ++ ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg; ++ MsOS_Memset(&stCmdTrigCfg,0,sizeof(ST_HVSP_CMD_TRIG_CONFIG)); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&(Get_DBGMG_HVSP(0)), "[DRVHVSP]%s(%d): Width=%hx,Height:%x\n", __FUNCTION__, ++ __LINE__, stLDCCfg->u16Width,stLDCCfg->u16Height); ++ DRV_HVSP_MUTEX_LOCK(); ++ Drv_HVSP_SetCMDQTrigTypeByRIU(&stCmdTrigCfg); ++ Hal_HVSP_SetLDCWidth(stLDCCfg->u16Width); ++ Hal_HVSP_SetLDCHeight(stLDCCfg->u16Height); ++ Hal_HVSP_SetLDCBase(stLDCCfg->u32FBaddr); ++ Hal_HVSP_SetLDCHWrwDiff(((MS_U16)stLDCCfg->u8FBrwdiff)); ++ Hal_HVSP_SetLDCSW_Idx(stLDCCfg->u8FBidx); ++ Hal_HVSP_SetLDCSW_Mode(stLDCCfg->bEnSWMode); ++ Hal_HVSP_SetLDCBank_Mode(stLDCCfg->enLDCType); ++ Hal_HVSP_SetLDCPathSel(stLDCCfg->bEnDNR); ++ if(!gbLDCEn) ++ { ++ Hal_HVSP_SetLDCBypass(1); ++ } ++ Drv_HVSP_SetCMDQTrigType(&stCmdTrigCfg); ++ DRV_HVSP_MUTEX_UNLOCK(); ++ return TRUE; ++} ++void Drv_HVSP_SetLDCONOFF(MS_BOOL bEn) ++{ ++ unsigned long u32Events; ++ static MS_BOOL bEnPrv2Crop = 0; ++ //ToDo ++ if(Hal_HVSP_GetLDCPathSel()!= bEn) ++ { ++ if(!Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 1000); // get status: FRM END ++ } ++ if(Hal_HVSP_GetPrv2CropOnOff() == bEn) ++ { ++ if(bEnPrv2Crop &&(!bEn)) ++ { ++ Drv_HVSP_SetPrv2CropOnOff(1); ++ } ++ else ++ { ++ Drv_HVSP_SetPrv2CropOnOff(0); ++ } ++ bEnPrv2Crop = bEn; ++ } ++ Hal_HVSP_SetLDCPathSel(bEn); ++ } ++ gbLDCEn = bEn; ++} ++MS_BOOL Drv_HVSP_SetPatTgen(MS_BOOL bEn, ST_DRV_HVSP_PAT_TGEN_CONFIG *pCfg) ++{ ++ MS_U16 u16VSync_St, u16HSync_St; ++ MS_BOOL bRet = TRUE; ++ Drv_SCLIRQ_SetPTGenStatus(bEn); ++ if(bEn) ++ { ++ u16VSync_St = 1; ++ u16HSync_St = 0; ++ if(pCfg) ++ { ++ if((u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch + pCfg->u16VActive - 1 )<1125) ++ { ++ Hal_HVSP_SetPatTgVtt(1800); //scaling up need bigger Vtt, , using vtt of 1920x1080 for all timing ++ } ++ else ++ { ++ Hal_HVSP_SetPatTgVtt(2500); //rotate ++ } ++ Hal_HVSP_SetPatTgVsyncSt(u16VSync_St); ++ Hal_HVSP_SetPatTgVsyncEnd(u16VSync_St + pCfg->u16VSyncWidth - 1); ++ Hal_HVSP_SetPatTgVdeSt(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch); ++ Hal_HVSP_SetPatTgVdeEnd(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch + pCfg->u16VActive - 1); ++ Hal_HVSP_SetPatTgVfdeSt(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch); ++ Hal_HVSP_SetPatTgVfdeEnd(u16VSync_St + pCfg->u16VSyncWidth + pCfg->u16VBackPorch + pCfg->u16VActive - 1); ++ ++ Hal_HVSP_SetPatTgHtt(2750); // scaling up need bigger Vtt, , using vtt of 1920x1080 for all timing ++ Hal_HVSP_SetPatTgHsyncSt(u16HSync_St); ++ Hal_HVSP_SetPatTgHsyncEnd(u16HSync_St + pCfg->u16HSyncWidth - 1); ++ Hal_HVSP_SetPatTgHdeSt(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch); ++ Hal_HVSP_SetPatTgHdeEnd(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch + pCfg->u16HActive - 1); ++ Hal_HVSP_SetPatTgHfdeSt(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch); ++ Hal_HVSP_SetPatTgHfdeEnd(u16HSync_St + pCfg->u16HSyncWidth + pCfg->u16HBackPorch + pCfg->u16HActive - 1); ++ ++ Hal_HVSP_SetPatTgEn(TRUE); ++ bRet = TRUE; ++ } ++ else ++ { ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ Hal_HVSP_SetPatTgEn(FALSE); ++ bRet = TRUE; ++ } ++ return bRet; ++} ++void Drv_HVSP_IDCLKRelease(ST_HVSP_CLK_CONFIG* stclk) ++{ ++ if(!gbclkforcemode) ++ Hal_HVSP_SetIdclkOnOff(0,stclk); ++} ++unsigned long Drv_HVSP_CMDQStatusReport(void) ++{ ++ unsigned long u32Reg; ++ static MS_U32 u32savereg; ++ u32Reg = Hal_HVSP_GetCMDQStatus(); ++ if(u32savereg == u32Reg) ++ { ++ return 0; ++ } ++ else ++ { ++ u32savereg = u32Reg; ++ return u32Reg ; ++ } ++} ++unsigned long Drv_HVSP_CropCheck(void) ++{ ++ MS_U16 u16croph,u16cropv,u16cropch,u16cropcv; ++ static MS_BOOL sbPrint = 0; ++ if(!sbPrint) ++ { ++ Drv_SCLIRQ_Set_Checkcropflag(EN_HVSP_MONITOR_CROPCHECK); ++ printf("[DRVHVSP]check crop\n"); ++ } ++ u16croph = Hal_HVSP_GetCrop1Width(); ++ u16cropv = Hal_HVSP_GetCrop1Height(); ++ u16cropch = Hal_HVSP_GetCrop1WidthCount(); ++ u16cropcv = Hal_HVSP_GetCrop1HeightCount(); ++ if(HVSP_CROP_CHECK(u16croph,u16cropch,u16cropv,u16cropcv)) ++ { ++ (printf("[DRVHVSP]crop set :(H,V)=(%hd,%hd)\n crop receive:(H,V)=(%hd,%hd)\n", ++ u16croph,u16cropv,u16cropch+1,u16cropcv )); ++ return 1; ++ } ++ sbPrint = 1 ; ++ return 0; ++} ++unsigned long Drv_HVSP_DMACheck(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 u16dmav,u16dmacv,bEn,u16hvsp,u16hvsp2,u16hvsp3; ++ MS_U32 u32Time; ++ static MS_BOOL sbPrint = 0; ++ if(!sbPrint) ++ { ++ Drv_SCLIRQ_Set_Checkcropflag(enMonitorType); ++ printf("[DRVHVSP]check DMA:%d\n",enMonitorType); ++ } ++ u16dmav = Hal_HVSP_GetDMAHeight(enMonitorType); ++ u16dmacv = Hal_HVSP_GetDMAHeightCount(enMonitorType); ++ bEn = Hal_HVSP_GetDMAEn(enMonitorType); ++ if(HVSP_DMA_CHECK(u16dmav,u16dmacv)&& bEn) ++ { ++ u32Time = ((MS_U32)MsOS_GetSystemTime()); ++ u16hvsp = Hal_HVSP_GetHVSPOutputHeightCount(E_HVSP_ID_1); ++ u16hvsp2= Hal_HVSP_GetHVSPOutputHeightCount(E_HVSP_ID_2); ++ u16hvsp3= Hal_HVSP_GetHVSPOutputHeightCount(E_HVSP_ID_3); ++ (printf("[DRVHVSP]dma set :(V)=(%hd) @%lu\n dma receive:(V)=(%hd) hvsp(3,2,1):(%hd,%hd,%hd)\n", ++ u16dmav,u32Time,u16dmacv,u16hvsp3,u16hvsp2,u16hvsp )); ++ return 1; ++ } ++ sbPrint = 1 ; ++ return 0; ++} ++void Drv_HVSP_GetCrop12Inform(ST_DRV_HVSP_INPUTINFORM_CONFIG *stInformCfg) ++{ ++ stInformCfg->bEn = Hal_HVSP_GetCrop1En(); ++ stInformCfg->u16inWidth = Hal_HVSP_GetCrop1Width(); ++ stInformCfg->u16inHeight = Hal_HVSP_GetCrop1Height(); ++ stInformCfg->u16inCropWidth = Hal_HVSP_GetCrop2InputWidth(); ++ stInformCfg->u16inCropHeight = Hal_HVSP_GetCrop2InputHeight(); ++ stInformCfg->u16inCropX = Hal_HVSP_Get_Crop_X(); ++ stInformCfg->u16inCropY = Hal_HVSP_Get_Crop_Y(); ++ stInformCfg->u16inWidthcount = Hal_HVSP_GetCrop1WidthCount(); ++ if(stInformCfg->u16inWidthcount) ++ { ++ stInformCfg->u16inWidthcount++; ++ } ++ stInformCfg->u16inHeightcount = Hal_HVSP_GetCrop1HeightCount(); ++ stInformCfg->enMux = Hal_HVSP_GetInputSrcMux(); ++ ++} ++void Drv_HVSP_SetCLKForcemode(unsigned char bEn) ++{ ++ gbclkforcemode = bEn; ++} ++MS_BOOL Drv_HVSP_GetCLKForcemode(void) ++{ ++ return gbclkforcemode; ++} ++void Drv_HVSP_SetCLKRate(unsigned char u8Idx) ++{ ++ if(gbclkforcemode) ++ { ++ u8Idx |= EN_HVSP_CLKATTR_FORCEMODE; ++ } ++ Hal_HVSP_SetCLKRate(u8Idx); ++} ++MS_U8 Drv_HVSP_CheckInputVSync(void) ++{ ++ MS_U32 u32Events = 0; ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_SYNC, &u32Events, E_OR, MSOS_WAIT_FOREVER); // get status: FRM END ++ if(u32Events) ++ { ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_SYNC)); ++ return 1; ++ } ++ return 0; ++} ++#undef DRV_HVSP_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp.h +new file mode 100644 +index 00000000..89781986 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp.h +@@ -0,0 +1,165 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_HVSP_H ++#define _DRV_HVSP_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_HVSP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++#define HVSP_irq 0 ++INTERFACE void Drv_HVSP_SetMemoryAllocateReady(MS_BOOL bEn); ++INTERFACE MS_BOOL Drv_HVSP_Init(ST_HVSP_INIT_CONFIG *pInitCfg); ++INTERFACE void Drv_HVSP_PriMaskBufferReset(void); ++INTERFACE void Drv_HVSP_Exit(unsigned char bCloseISR); ++INTERFACE void Drv_HVSP_PriMaskBufferReset(void); ++INTERFACE void Drv_HVSP_SetBufferNum(MS_U8 u8Num); ++INTERFACE MS_BOOL Drv_HVSP_GetBufferNum(void); ++INTERFACE MS_BOOL Drv_HVSP_Set_IPM_Config(ST_HVSP_IPM_CONFIG *stCfg); ++INTERFACE void Drv_HVSP_SetFbManageConfig(ST_DRV_HVSP_SET_FB_MANAGE_CONFIG *stCfg); ++INTERFACE MS_BOOL Drv_HVSP_SetScaling(EN_HVSP_ID_TYPE enHVSP_ID, ST_HVSP_SCALING_CONFIG *stCfg, ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE MS_BOOL Drv_HVSP_SetInputMux(EN_HVSP_IP_MUX_TYPE enIP,ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE EN_HVSP_IP_MUX_TYPE Drv_HVSP_GetInputSrcMux(void); ++INTERFACE MS_BOOL Drv_HVSP_SetRegisterForce(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Msk); ++INTERFACE void Drv_HVSP_SetSCIQHSRAM(EN_HVSP_ID_TYPE enHVSP_ID); ++INTERFACE void Drv_HVSP_SetSCIQVSRAM(EN_HVSP_ID_TYPE enHVSP_ID); ++INTERFACE MS_BOOL Drv_HVSP_SetLDCFrameBuffer_Config(ST_HVSP_LDC_FRAMEBUFFER_CONFIG *stLDCCfg); ++INTERFACE MS_BOOL Drv_HVSP_SetPatTgen(MS_BOOL bEn, ST_DRV_HVSP_PAT_TGEN_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_HVSP_GetSCLInform(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_SCINFORM_CONFIG *stInformCfg); ++INTERFACE void Drv_HVSP_SCLIQ(EN_HVSP_ID_TYPE enID,EN_DRV_HVSP_IQ_TYPE enIQ); ++INTERFACE void Drv_HVSP_SetPrv2CropOnOff(unsigned char bEn); ++INTERFACE void Drv_HVSP_GetSCLInts(ST_HVSP_SCINTS_TYPE *sthvspints); ++INTERFACE void Drv_HVSP_SetOSDConfig(EN_HVSP_ID_TYPE enID, ST_DRV_HVSP_OSD_CONFIG *stOSdCfg); ++INTERFACE void Drv_HVSP_SetPriMaskConfig(ST_HVSP_PRIMASK_CONFIG *stCfg); ++INTERFACE unsigned short Drv_HVSP_PriMaskGetSRAM(unsigned char u8idx, unsigned char u8idy); ++INTERFACE void Drv_HVSP_SetPriMaskTrigger(EN_HVSP_PRIMASK_TYPE enType); ++INTERFACE void Drv_HVSP_IDCLKRelease(ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE unsigned long Drv_HVSP_CropCheck(void); ++INTERFACE unsigned long Drv_HVSP_DMACheck(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_U8 Drv_HVSP_CheckInputVSync(void); ++INTERFACE void Drv_HVSP_GetCrop12Inform(ST_DRV_HVSP_INPUTINFORM_CONFIG *stInformCfg); ++INTERFACE MS_BOOL Drv_HVSP_GetFrameBufferAttribute(EN_HVSP_ID_TYPE enID,ST_HVSP_IPM_CONFIG *stInformCfg); ++INTERFACE MS_BOOL Drv_HVSP_GetHVSPAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_HVSPINFORM_CONFIG *stInformCfg); ++INTERFACE void Drv_HVSP_GetOSDAttribute(EN_HVSP_ID_TYPE enID,ST_DRV_HVSP_OSD_CONFIG *stOsdCfg); ++INTERFACE MS_BOOL Drv_HVSP_Suspend(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_HVSP_Resume(ST_HVSP_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE void Drv_HVSP_Release(EN_HVSP_ID_TYPE HVSP_IP); ++INTERFACE void Drv_HVSP_Open(EN_HVSP_ID_TYPE HVSP_IP); ++INTERFACE MS_BOOL Drv_HVSP_SetCMDQTrigType(ST_HVSP_CMD_TRIG_CONFIG *stCmdTrigCfg); ++INTERFACE void Drv_HVSP_SetCMDQTrigTypeByRIU(ST_HVSP_CMD_TRIG_CONFIG *stCmdTrigCfg); ++INTERFACE void Drv_HVSP_SetCLKForcemode(unsigned char bEn); ++INTERFACE MS_BOOL Drv_HVSP_GetCLKForcemode(void); ++INTERFACE void Drv_HVSP_SetCLKRate(unsigned char u8Idx); ++INTERFACE unsigned long Drv_HVSP_CMDQStatusReport(void); ++INTERFACE void Drv_HVSP_SetLDCONOFF(MS_BOOL bEn); ++INTERFACE void * Drv_HVSP_GetWaitQueueHead(void); ++INTERFACE MS_BOOL Drv_HVSP_GetCMDQDoneStatus(EN_HVSP_POLL_ID_TYPE enPollId); ++INTERFACE void Drv_HVSP_SetCropWindowSize(void); ++INTERFACE void Drv_HVSP_SetInputSrcSize(MS_U16 u16Height,MS_U16 u16Width); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp_st.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp_st.h +new file mode 100644 +index 00000000..e14e6835 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/hvsp/drvhvsp_st.h +@@ -0,0 +1,410 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_HVSP_ST_H ++#define _DRV_HVSP_ST_H ++ ++#define DRV_HVSP_CROP_1 0 ++#define DRV_HVSP_CROP_2 1 ++#define DRV_HVSP_CROP_NUM 2 ++#define SetPostCrop 0 ++#define HVSP_PRIMASK_SIZE 11*84 ++#define HVSP_PRIMASK_Width_SIZE 11 ++#define HVSP_PRIMASK_Height_SIZE 84 ++#define HVSP_PRIMASK_BLOCK_SIZE 32 ++#define BYTESIZE 8 ++#define SCALING_BLOCK 0 ++//------------------------------------------------------------------------------------------------- ++// Defines & enum ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_HVSP_CROP_ID_1, ++ E_HVSP_CROP_ID_2, ++ E_HVSP_CROP_ID_MAX, // I1 has 2 crop IP ++}EN_HVSP_CROP_ID_TYPE; ++typedef enum ++{ ++ E_HVSP_POLL_ID_1 = 0, ++ E_HVSP_POLL_ID_2, ++ E_HVSP_POLL_ID_3, ++ E_HVSP_POLL_ID_VIP, ++ E_HVSP_POLL_ID_MAX, //I1 has 3 HVSP 1VIP ++}EN_HVSP_POLL_ID_TYPE; ++ ++typedef enum ++{ ++ E_HVSP_IP_MUX_BT656 , //I1 HW only has BT656 and ISP input source ++ E_HVSP_IP_MUX_ISP , ++ E_HVSP_IP_MUX_HVSP , //SW used in HVSP 2 ++ E_HVSP_IP_MUX_PAT_TGEN, // SW used in debug pat ++ E_HVSP_IP_MUX_MAX, // 4 main type, 2 hw type, 2 sw type ++}EN_HVSP_IP_MUX_TYPE; ++ ++typedef enum ++{ ++ EN_HVSP_MONITOR_CROPCHECK = 1, ///< crop ++ EN_HVSP_MONITOR_DMA1FRMCHECK = 2, ///< dma1frm ++ EN_HVSP_MONITOR_DMA1SNPCHECK = 3, ///< dma1frm ++ EN_HVSP_MONITOR_DMA2FRMCHECK = 4, ///< dma1frm ++ EN_HVSP_MONITOR_DMA3FRMCHECK = 5, ///< dma1frm ++}EN_HVSP_MONITOR_TYPE; ++typedef enum ++{ ++ EN_DRV_HVSP_OSD_LOC_AFTER = 0, ///< after hvsp ++ EN_DRV_HVSP_OSD_LOC_BEFORE = 1, ///< before hvsp ++}EN_DRV_HVSP_OSD_LOC_TYPE; ++ ++ ++typedef enum ++{ ++ E_HVSP_ID_1, ++ E_HVSP_ID_2, ++ E_HVSP_ID_3, ++ E_HVSP_ID_MAX, //I1 has 3 HVSP ++}EN_HVSP_ID_TYPE; ++ ++typedef enum ++{ ++ EN_HVSP_PRIMASK_DISABLE =0, ++ EN_HVSP_PRIMASK_ENABLE, ++ EN_HVSP_PRIMASK_PENDING, ++ EN_HVSP_PRIMASK_ONLYHWOFF, ++ EN_HVSP_PRIMASK_MAX, //I3 has 3mode ++}EN_HVSP_PRIMASK_TYPE; ++ ++typedef enum ++{ ++ E_HVSP_CMD_TRIG_NONE, //RIU ++ E_HVSP_CMD_TRIG_POLL_LDC_SYNC, //polling blanking region RIU ++ E_HVSP_CMD_TRIG_CMDQ_FRMCNT, //wait framecnt CMDQ ++ E_HVSP_CMD_TRIG_CMDQ_LDC_SYNC, //used CMDQ in blanking region ++ E_HVSP_CMD_TRIG_MAX, //HVSP has 4 type to set register,2 RIU,2 CMDQ ++}EN_HVSP_CMD_TRIG_TYPE; ++typedef enum ++{ ++ E_HVSP_EVENT_RUN = 0x00000001, ++ E_HVSP_EVENT_IRQ = 0x00000002, ++} MDrvHVSPTXEvent; ++typedef enum ++{ ++ EN_DRV_HVSP_FBMG_SET_LDCPATH_ON = 0x1, ++ EN_DRV_HVSP_FBMG_SET_LDCPATH_OFF = 0x2, ++ EN_DRV_HVSP_FBMG_SET_DNR_Read_ON = 0x4, ++ EN_DRV_HVSP_FBMG_SET_DNR_Read_OFF = 0x8, ++ EN_DRV_HVSP_FBMG_SET_DNR_Write_ON = 0x10, ++ EN_DRV_HVSP_FBMG_SET_DNR_Write_OFF = 0x20, ++ EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_1 = 0x40, ++ EN_DRV_HVSP_FBMG_SET_DNR_BUFFER_2 = 0x80, ++ EN_DRV_HVSP_FBMG_SET_UNLOCK = 0x100, ++ EN_DRV_HVSP_FBMG_SET_DNR_COMDE_ON = 0x200, ++ EN_DRV_HVSP_FBMG_SET_DNR_COMDE_OFF = 0x400, ++ EN_DRV_HVSP_FBMG_SET_DNR_COMDE_265OFF = 0x800, ++ EN_DRV_HVSP_FBMG_SET_PRVCROP_ON = 0x1000, ++ EN_DRV_HVSP_FBMG_SET_PRVCROP_OFF = 0x2000, ++ EN_DRV_HVSP_FBMG_SET_CIIR_ON = 0x4000, ++ EN_DRV_HVSP_FBMG_SET_CIIR_OFF = 0x8000, ++ EN_DRV_HVSP_FBMG_SET_LOCK = 0x10000, ++}EN_DRV_HVSP_FBMG_SET_TYPE; ++typedef enum ++{ ++ EN_DRV_HVSP_IQ_H_Tbl0, ++ EN_DRV_HVSP_IQ_H_Tbl1, ++ EN_DRV_HVSP_IQ_H_Tbl2, ++ EN_DRV_HVSP_IQ_H_Tbl3, ++ EN_DRV_HVSP_IQ_H_BYPASS, ++ EN_DRV_HVSP_IQ_H_BILINEAR, ++ EN_DRV_HVSP_IQ_V_Tbl0, ++ EN_DRV_HVSP_IQ_V_Tbl1, ++ EN_DRV_HVSP_IQ_V_Tbl2, ++ EN_DRV_HVSP_IQ_V_Tbl3, ++ EN_DRV_HVSP_IQ_V_BYPASS, ++ EN_DRV_HVSP_IQ_V_BILINEAR, ++ EN_DRV_HVSP_IQ_NUM, ++}EN_DRV_HVSP_IQ_TYPE; ++typedef enum ++{ ++ EN_DRV_HVSP_LDCLCBANKMODE_64, ++ EN_DRV_HVSP_LDCLCBANKMODE_128, ++}EN_DRV_HVSP_LDCLCBANKMODE_TYPE; ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ MS_U32 u32RIUBase; // I1 :0x1F000000 ++ MS_U32 u32IRQNUM; // scl irq num by device tree ++ MS_U32 u32CMDQIRQNUM; // cmdq irq ++}ST_HVSP_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32IRQNUM; ++ MS_U32 u32CMDQIRQNUM; // cmdq irq ++}ST_HVSP_SUSPEND_RESUME_CONFIG; ++ ++typedef struct ++{ ++ MSOS_ST_CLK* idclk; // I1 scl clk 1.idclk(for before crop) ++ MSOS_ST_CLK* fclk1; // 2. fclk1(scl main clk) ++ MSOS_ST_CLK* fclk2; // 3.fclk2(scl hvsp3 only) ++ MSOS_ST_CLK* odclk; // 4.odclk(ttl only ) ++}ST_HVSP_CLK_CONFIG; ++typedef struct ++{ ++ MS_BOOL bYCMRead; // DNR IP can Read from Buffer (if can read then DNR availability) ++ MS_BOOL bYCMWrite; // DNR IP can Write to Buffer ++ MS_BOOL bCIIRRead; // DNR IP can Read from Buffer (if can read then DNR availability) ++ MS_BOOL bCIIRWrite; // DNR IP can Write to Buffer ++ MS_U32 u32YCBaseAddr;// YC Buffer phycal address(unit:Byte) ++ MS_U32 u32MBaseAddr;// M Buffer phycal address(unit:Byte) ++ MS_U32 u32CIIRBaseAddr;// CIIR Buffer phycal address(unit:Byte) ++ MS_U16 u16Vsize; // DNR Frame Height size ++ MS_U16 u16Fetch; // DNR Frame Width size ++ MS_U32 u32MemSize; // DNR buffer size ++}ST_HVSP_IPM_CONFIG; ++typedef struct ++{ ++ MS_U32 u32AffCount; ++ MS_U32 u32ISPInCount; ++ MS_U32 u32ISPDoneCount; ++ MS_U32 u32SC1FrmDoneCount; ++ MS_U32 u32SC1SnpDoneCount; ++ MS_U32 u32SC2FrmDoneCount; ++ MS_U32 u32SC2Frm2DoneCount; ++ MS_U32 u32SC3DoneCount; ++ MS_U32 u32SCLMainDoneCount; ++ MS_U32 u32SC1FrmActiveTime; ++ MS_U32 u32SC1SnpActiveTime; ++ MS_U32 u32SC2FrmActiveTime; ++ MS_U32 u32SC2Frm2ActiveTime; ++ MS_U32 u32SC3ActiveTime; ++ MS_U32 u32SCLMainActiveTime; ++ MS_U32 u32ISPTime; ++ MS_U32 u32ISPBlanking; ++ MS_U32 u32ISPBlankingTime; ++ MS_U32 u32ErrorCount; ++ MS_U8 u8CountReset; ++}ST_HVSP_SCINTS_TYPE; ++ ++ ++typedef struct ++{ ++ EN_HVSP_CMD_TRIG_TYPE enType; ++ MS_U8 u8Fmcnt; ++}ST_HVSP_CMD_TRIG_CONFIG; ++ ++typedef struct ++{ ++ ST_HVSP_CMD_TRIG_CONFIG stCmdTrigCfg; ++ MS_U16 u16Src_Width; // Input source width(post crop1) ++ MS_U16 u16Src_Height; // Input source height(post crop1) ++ MS_BOOL bCropEn[DRV_HVSP_CROP_NUM]; // crop enable ++ MS_U16 u16Crop_X[DRV_HVSP_CROP_NUM]; // crop x ++ MS_U16 u16Crop_Y[DRV_HVSP_CROP_NUM]; // crop y ++ MS_U16 u16Crop_Width[DRV_HVSP_CROP_NUM]; // post crop2 width ++ MS_U16 u16Crop_Height[DRV_HVSP_CROP_NUM]; // post crop2 height ++ MS_U16 u16Dsp_Width; // After scl display width ++ MS_U16 u16Dsp_Height; // After scl display height ++ MS_BOOL bRet; ++}ST_HVSP_SCALING_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bSet; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++}ST_HVSP_SIZE_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bCropEn; ++ ++ ST_HVSP_SIZE_CONFIG stSizeAfterCrop; ++ ST_HVSP_SIZE_CONFIG stSizeAfterScaling; ++ MS_U32 u32ScalingRatio_H; ++ MS_U32 u32ScalingRatio_V; ++}ST_HVSP_SCALING_INFO; ++ ++typedef struct ++{ ++ unsigned short u16Width; // LDC FB width ++ unsigned short u16Height; // LDC FB Heigh ++ unsigned long u32FBaddr; // DNR Buffer ++ unsigned char u8FBidx; // idx assign by sw ++ unsigned char u8FBrwdiff; // delay frame from DNR buffer ++ unsigned char bEnSWMode; // enable idx assign sw mode ++ unsigned char bEnDNR; // DNR enable? ++ EN_DRV_HVSP_LDCLCBANKMODE_TYPE enLDCType; ++}ST_HVSP_LDC_FRAMEBUFFER_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Vtt; ++ MS_U16 u16VBackPorch; ++ MS_U16 u16VSyncWidth; ++ MS_U16 u16VFrontPorch; ++ MS_U16 u16VActive; ++ MS_U16 u16Htt; ++ MS_U16 u16HBackPorch; ++ MS_U16 u16HSyncWidth; ++ MS_U16 u16HFrontPorch; ++ MS_U16 u16HActive; ++}ST_DRV_HVSP_PAT_TGEN_CONFIG; ++ ++typedef struct ++{ ++ unsigned short u16X; //isp crop x ++ unsigned short u16Y; // isp crop y ++ unsigned short u16Width; // display width ++ unsigned short u16Height; // display height ++ unsigned short u16crop2inWidth; // after isp crop width ++ unsigned short u16crop2inHeight;// after isp crop height ++ unsigned short u16crop2OutWidth; // after isp crop width ++ unsigned short u16crop2OutHeight;// after isp crop height ++ unsigned char bEn; //crop En ++}ST_DRV_HVSP_SCINFORM_CONFIG; ++typedef struct ++{ ++ unsigned short u16Width; // display width ++ unsigned short u16Height; // display height ++ unsigned short u16inWidth; // after hvsp width ++ unsigned short u16inHeight;// after hvsp height ++ unsigned char bEn; //function En ++}ST_DRV_HVSP_HVSPINFORM_CONFIG; ++typedef struct ++{ ++ EN_HVSP_IP_MUX_TYPE enMux; // display width ++ unsigned short u16inWidth; // isp width ++ unsigned short u16inHeight;// isp height ++ unsigned short u16inCropWidth; // isp crop width ++ unsigned short u16inCropHeight;// isp crop height ++ unsigned short u16inCropX; // isp crop X ++ unsigned short u16inCropY;// isp crop Y ++ unsigned short u16inWidthcount; // isp width ++ unsigned short u16inHeightcount;// isp height ++ unsigned char bEn; //function En ++}ST_DRV_HVSP_INPUTINFORM_CONFIG; ++typedef struct ++{ ++ EN_DRV_HVSP_FBMG_SET_TYPE enSet; ++}ST_DRV_HVSP_SET_FB_MANAGE_CONFIG; ++typedef struct ++{ ++ unsigned char bOSDEn; ///< OSD en ++ unsigned char bOSDBypass; ///< OSD en ++ unsigned char bWTMBypass; ///< OSD en ++}ST_DRV_HVSP_OSD_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ EN_DRV_HVSP_OSD_LOC_TYPE enOSD_loc; ///< OSD locate ++ ST_DRV_HVSP_OSD_ONOFF_CONFIG stOsdOnOff; ++}ST_DRV_HVSP_OSD_CONFIG; ++typedef struct ++{ ++ unsigned char bMask; /// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_PNL_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++ ++#include "halpnl.h" ++#include "drvpnl.h" ++#include "mdrv_scl_dbg.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_PNL_DBG(x) ++#define DRV_PNL_ERR(x) x ++#define ENLPLLCLK 1 //open lpll clk ++#define DISLPLLCLK 0 //close lpll clk ++#define FACTOR 10*1000000 ++#define LVDS_MPLL_CLOCK_MHZ 432 //ToDo ++#define PNL_CAL_LPLL_DCLK(Vtt,Htt,Freq) ((MS_U64)((Vtt) * (Htt) * (Freq))) ++#define PNL_CAL_DCLK_FACKTOR(Lpll_Gain) ((MS_U64)LVDS_MPLL_CLOCK_MHZ * (MS_U64)524288 * (MS_U64)(Lpll_Gain)) ++#define PNL_CAL_LPLL_SET(DclkFacktor,Dclk_x10,Lpll_Div) (((DclkFacktor) * (FACTOR)) + (((MS_U64)(Dclk_x10) * (MS_U64)(Lpll_Div)) >> 1)) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_S32 _PNL_Mutex = -1; ++MS_BOOL gPnlOpen; ++MS_U64 gu64Dclk; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Drv_PNL_Exit(unsigned char bCloseISR) ++{ ++ if(_PNL_Mutex != -1) ++ { ++ MsOS_DeleteMutex(_PNL_Mutex); ++ _PNL_Mutex = -1; ++ } ++ if(bCloseISR) ++ { ++ Drv_SCLIRQ_Exit(); ++ } ++} ++MS_BOOL Drv_PNL_Init(ST_PNL_INIT_CONFIG *pCfg) ++{ ++ char word[] = {"_PNL_Mutex"}; ++ ++ if(_PNL_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s already done\n", __FUNCTION__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s MsOs_Init Fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ _PNL_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ ++ if (_PNL_Mutex == -1) ++ { ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s create mutex fail\n", __FUNCTION__); ++ return FALSE; ++ } ++ ++ Hal_PNL_Set_Riu_Base(pCfg->u32RiuBase); ++ Hal_PNL_Set_Init_Y2R(); ++ gPnlOpen = 0; ++ ++ return TRUE; ++} ++MS_BOOL Drv_PNL_GetPnlOpen(void) ++{ ++ return gPnlOpen ; ++} ++void Drv_PNL_Release(void) ++{ ++ if(!gbclkforcemode && gPnlOpen) ++ { ++ Hal_PNL_Set_OpenLpll_CLK(DISLPLLCLK); ++ gPnlOpen = 0; ++ } ++} ++void Drv_PNL_Resume(void) ++{ ++ Hal_PNL_Set_Init_Y2R(); ++} ++MS_U64 Drv_PNL_GetLPLLDclk(void) ++{ ++ return gu64Dclk; ++} ++MS_BOOL Drv_PNL_Set_Timing_Config(ST_PNL_TIMING_CONFIG *pCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s, V:[%d %d %d %d], H:[%d %d %d %d]\n " ++ , __FUNCTION__, pCfg->u16Vsync_St, pCfg->u16Vsync_End, pCfg->u16Vde_St, pCfg->u16Vde_End, ++ pCfg->u16Hsync_St, pCfg->u16Hsync_End, pCfg->u16Hde_St, pCfg->u16Hde_End); ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s, Htt:%d, Vtt:%d, VFreqx10:%d\n " ++ ,__FUNCTION__, pCfg->u16Htt, pCfg->u16Vtt, pCfg->u16VFreqx10); ++ ++ ++ // LPLL setting ++ Drv_PNL_Set_LPLL_Config(pCfg); ++ //Tgen setting ++ Hal_PNL_Set_VSync_St(pCfg->u16Vsync_St); ++ Hal_PNL_Set_VSync_End(pCfg->u16Vsync_End); ++ Hal_PNL_Set_Vfde_St(pCfg->u16Vfde_St); ++ Hal_PNL_Set_Vfde_End(pCfg->u16Vfde_End); ++ Hal_PNL_Set_Vde_St(pCfg->u16Vde_St); ++ Hal_PNL_Set_Vde_End(pCfg->u16Vde_End); ++ Hal_PNL_Set_Vtt(pCfg->u16Vtt); ++ ++ Hal_PNL_Set_HSync_St(pCfg->u16Hsync_St); ++ Hal_PNL_Set_HSync_End(pCfg->u16Hsync_End); ++ Hal_PNL_Set_Hfde_St(pCfg->u16Hfde_St); ++ Hal_PNL_Set_Hfde_End(pCfg->u16Hfde_End); ++ Hal_PNL_Set_Hde_St(pCfg->u16Hde_St); ++ Hal_PNL_Set_Hde_End(pCfg->u16Hde_End); ++ Hal_PNL_Set_Htt(pCfg->u16Htt); ++ Hal_PNL_Set_FrameColr_En(0); ++ Hal_PNL_Set_Chiptop(1); ++ ++ return TRUE; ++} ++ ++MS_BOOL Drv_PNL_Set_LPLL_Config(ST_PNL_TIMING_CONFIG *pCfg) ++{ ++ MS_U16 u16LpllIdx; ++ MS_U32 u32Lpll_Gain, u32Lpll_Div; ++ MS_U64 u64Dclk_x10, u64DclkFacktor, u64LpllSet,u64Dclk; ++ // LPLL setting ++ u64Dclk_x10 = PNL_CAL_LPLL_DCLK((MS_U64)pCfg->u16Vtt,(MS_U64)pCfg->u16Htt,(MS_U64)(pCfg->u16VFreqx10)); ++ u64Dclk = PNL_CAL_LPLL_DCLK((MS_U64)pCfg->u16Vtt,(MS_U64)pCfg->u16Htt,(MS_U64)(pCfg->u16VFreqx10/10)); ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%sDCLK:%lld\n ", __FUNCTION__, u64Dclk); ++ gu64Dclk = u64Dclk; ++ u16LpllIdx = Hal_PNL_Get_Lpll_Idx(u64Dclk); ++ if(u16LpllIdx == 0xFF) ++ { ++ DRV_PNL_ERR(printf("[DRVPNL]%s:: LPLL Clk is out of range\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ u32Lpll_Gain = Hal_PNL_Get_Lpll_Gain(u16LpllIdx); ++ u32Lpll_Div = Hal_PNL_Get_Lpll_Div(u16LpllIdx); ++ ++ u64DclkFacktor = PNL_CAL_DCLK_FACKTOR(u32Lpll_Gain); ++ u64LpllSet = PNL_CAL_LPLL_SET(u64DclkFacktor,u64Dclk_x10,u32Lpll_Div); ++ ++ if(u64Dclk_x10>1 && u64LpllSet>1) ++ { ++ do_div(u64LpllSet, u64Dclk_x10); ++ } ++ ++ if(u32Lpll_Div >1 && u64LpllSet>1) ++ { ++ do_div(u64LpllSet, u32Lpll_Div); ++ } ++ SCL_DBG(SCL_DBG_LV_PNL(), "[DRVPNL]%s::LpllIdx=%d, Gain:%d, Div:%d, LpllSet=%x\n " ++ ,__FUNCTION__, (int)u16LpllIdx, (int)u32Lpll_Gain, (int)u32Lpll_Div, (int)u64LpllSet); ++ ++ Hal_PNL_Dump_Lpll_Setting(u16LpllIdx); ++ Hal_PNL_Set_Lpll_Set((MS_U32)u64LpllSet); ++ if(!gbclkforcemode) ++ { ++ Hal_PNL_Set_OpenLpll_CLK(ENLPLLCLK); ++ gPnlOpen = 1; ++ } ++ ++ return TRUE; ++} ++ ++ ++MS_BOOL Drv_PNL_Set_CSC_Y2R_Config(ST_PNL_CSC_Y2R_CONFIG *pCfg) ++{ ++ Hal_PNL_Set_CSC_Y2R_En(pCfg->bEn); ++ Hal_PNL_Set_CSC_Y2R_Offset(pCfg->u8YOffset, pCfg->u8CbOffset, pCfg->u8CrOffset); ++ Hal_PNL_Set_CSC_Y2R_Coef(&pCfg->u16Coef[0]); ++ ++ return TRUE; ++} ++ ++#undef DRV_PNL_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/pnl/drvpnl.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/pnl/drvpnl.h +new file mode 100644 +index 00000000..51e7405a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/pnl/drvpnl.h +@@ -0,0 +1,156 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_PNL_H ++#define _DRV_PNL_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++}ST_PNL_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16Vsync_St; ++ MS_U16 u16Vsync_End; ++ MS_U16 u16Vde_St; ++ MS_U16 u16Vde_End; ++ MS_U16 u16Vfde_St; ++ MS_U16 u16Vfde_End; ++ MS_U16 u16Vtt; ++ MS_U16 u16Hsync_St; ++ MS_U16 u16Hsync_End; ++ MS_U16 u16Hde_St; ++ MS_U16 u16Hde_End; ++ MS_U16 u16Hfde_St; ++ MS_U16 u16Hfde_End; ++ MS_U16 u16Htt; ++ MS_U16 u16VFreqx10; ++}ST_PNL_TIMING_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U8 u8YOffset; ++ MS_U8 u8CbOffset; ++ MS_U8 u8CrOffset; ++ MS_U16 u16Coef[9]; ++}ST_PNL_CSC_Y2R_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_PNL_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++ ++INTERFACE MS_BOOL Drv_PNL_Init(ST_PNL_INIT_CONFIG *pCfg); ++INTERFACE void Drv_PNL_Exit(unsigned char bCloseISR); ++INTERFACE MS_BOOL Drv_PNL_Set_Timing_Config(ST_PNL_TIMING_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_PNL_Set_LPLL_Config(ST_PNL_TIMING_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_PNL_Set_CSC_Y2R_Config(ST_PNL_CSC_Y2R_CONFIG *pCfg); ++INTERFACE void Drv_PNL_Resume(void); ++INTERFACE MS_U64 Drv_PNL_GetLPLLDclk(void); ++INTERFACE void Drv_PNL_Release(void); ++INTERFACE MS_BOOL Drv_PNL_GetPnlOpen(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma.c b/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma.c +new file mode 100644 +index 00000000..0246f148 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma.c +@@ -0,0 +1,2844 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_SCLDMA_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++//#include ++//#include ++//#include ++//#include /* seems do not need this */ ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "drvscldma_st.h" ++#include "halscldma.h" ++#include "drvscldma.h" ++#include "mdrv_scl_dbg.h" ++#include "MsDbg.h" ++#include "ms_msys.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_SCLDMA_DBG(x) ++#define DRV_SCLDMA_DBG_H(x) ++#define DRV_SCLDMA_ERR(x) x ++#define FHD_Width 1920 ++#define FHD_Height 1080 ++#define HD_Width 1280 ++#define HD_Height 720 ++#define PNL_Width 800 ++#define PNL_Height 480 ++#define SINGLE_SKIP 0xF ++#define FRM_POLLIN 0x1 ++#define SNP_POLLIN 0x2 ++#define FRM2_POLLIN 0x2 ++#define SCL_IMIinitAddr 0x14000 ++ ++#define SINGLE_BUFF_ACTIVE_TIMIEOUT 100 ++#define _Is_SC1EventNotBeFatch() (!(gu32FRMEvents & (E_SCLIRQ_EVENT_SC1POLL))) ++#define _Is_SC2EventNotBeFatch() (!(gu32SC2FRMEvents & (E_SCLIRQ_EVENT_SC2POLL))) ++#define _Is_SWRingModeBufferNotReady(enClientType) (gstScldmaBufferQueue[enClientType].bUsed ==0) ++#define _Is_SWRingModeBufferReady(enClientType) (gstScldmaBufferQueue[enClientType].bUsed) ++#define _Is_SWRingModeBufferNotFull(enClientType) (!gstScldmaBufferQueue[enClientType].bFull) ++#define _Is_SWRingModeBufferFull(enClientType) (gstScldmaBufferQueue[enClientType].bFull) ++#define _Is_RingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_RING) ++#define _Is_SingleMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SINGLE) ++#define _Is_SWRingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SWRING) ++#define _Is_DMACanReOpen(bReOpen,bRpchange) ((bReOpen)&&(bRpchange)) ++#define _Is_DMAClientOn(enClientType) (gstScldmaInfo.bDMAOnOff[enClientType]) ++#define _Is_DMAClientOff(enClientType) (!gstScldmaInfo.bDMAOnOff[enClientType]) ++#define _IsQueueWriteLargeRead(enClientType) \ ++ (gstScldmaBufferQueue[enClientType].pstWrite > gstScldmaBufferQueue[enClientType].pstRead) ++#define _IsQueueWriteSmallRead(enClientType) \ ++ (gstScldmaBufferQueue[enClientType].pstWrite < gstScldmaBufferQueue[enClientType].pstRead) ++#define _GetInQueueCountIfLarge(enClientType)\ ++ gstScldmaBufferQueue[enClientType].u8InQueueCount =\ ++ (gstScldmaBufferQueue[enClientType].pstWrite - gstScldmaBufferQueue[enClientType].pstRead)/1; ++#define _GetInQueueCountIfSmall(enClientType)\ ++ gstScldmaBufferQueue[enClientType].u8InQueueCount =\ ++ ((gstScldmaBufferQueue[enClientType].pstWrite- gstScldmaBufferQueue[enClientType].pstHead)+\ ++ (gstScldmaBufferQueue[enClientType].pstTail- gstScldmaBufferQueue[enClientType].pstRead))\ ++ /1; ++#define _Is_IdxRingCircuit(enClientType,idx) (idx == (gstScldmaInfo.bMaxid[enClientType]-1)) ++ ++#define _Is_SC3Singlemode(enClientType) (_Is_SingleMode(enClientType) && \ ++ (enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W)) ++#define _Is_SC3Ringmode(enClientType) (_Is_RingMode(enClientType) && \ ++ (enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W)) ++#define _Is_SC3SWRingmode(enClientType) (_Is_SWRingMode(enClientType) && \ ++ (enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W)) ++ ++#define _Is_OnlySC1SNPSingleDone(u32Event) (u32Event == E_SCLIRQ_EVENT_ISTSC1SNP &&_Is_SingleMode(E_SCLDMA_1_SNP_W)) ++#define _Is_OnlySC1FRMSingleDone(u32Event) (u32Event == E_SCLIRQ_EVENT_ISTSC1FRM &&_Is_SingleMode(E_SCLDMA_1_FRM_W)) ++#define _Is_OnlySC2FRMSingleDone(u32Event) (u32Event == E_SCLIRQ_EVENT_ISTSC2FRM &&_Is_SingleMode(E_SCLDMA_2_FRM_W)) ++#define _Is_VsrcId(enSCLDMA_ID) ((enSCLDMA_ID ==E_SCLDMA_ID_1_W)||(enSCLDMA_ID ==E_SCLDMA_ID_2_W)) ++#define _Is_VsrcDoubleBufferNotOpen() (gVsrcDBnotOpen) ++#define _Is_VsrcDoubleBufferOpen() (!gVsrcDBnotOpen) ++#define _ResetTrigCount(enClientType) (gu32TrigCount[enClientType]--) ++#define SCLDMA_SIZE_ALIGN(x, align) ((x+align) & ~(align-1)) ++#define SCLDMA_CHECK_ALIGN(x, align) (x & (align-1)) ++ ++#define DRV_SCLDMA_MUTEX_LOCK() MsOS_ObtainMutex(_SCLDMA_Mutex,MSOS_WAIT_FOREVER) ++#define DRV_SCLDMA_MUTEX_UNLOCK() MsOS_ReleaseMutex(_SCLDMA_Mutex) ++#if USE_RTK ++#define DRV_SCLDMA_MUTEX_LOCK_ISR() MsOS_ObtainMutex(_SCLIRQ_SCLDMA_Mutex,MSOS_WAIT_FOREVER); ++#define DRV_SCLDMA_MUTEX_UNLOCK_ISR() MsOS_ReleaseMutex(_SCLIRQ_SCLDMA_Mutex); ++#else ++#define DRV_SCLDMA_MUTEX_LOCK_ISR() MsOS_ObtainMutex_IRQ(_SCLIRQ_SCLDMA_Mutex); ++#define DRV_SCLDMA_MUTEX_UNLOCK_ISR() MsOS_ReleaseMutex_IRQ(_SCLIRQ_SCLDMA_Mutex); ++#endif ++ ++#define PARSING_SCLDMA_ID(x) (x==E_SCLDMA_ID_1_W ? "SCLDMA_1_W" : \ ++ x==E_SCLDMA_ID_2_W ? "SCLDMA_2_W" : \ ++ x==E_SCLDMA_ID_3_W ? "SCLDMA_3_W" : \ ++ x==E_SCLDMA_ID_3_R ? "SCLDMA_3_R" : \ ++ x==E_SCLDMA_ID_PNL_R ? "SCLDMA_PNL_R" : \ ++ "UNKNOWN") ++ ++ ++ ++#define PARSING_SCLDMA_RWMD(x) (x==E_SCLDMA_FRM_W ? "FRM_W" : \ ++ x==E_SCLDMA_SNP_W ? "SNP_W" : \ ++ x==E_SCLDMA_IMI_W ? "IMI_W" : \ ++ x==E_SCLDMA_FRM_R ? "FRM_R" : \ ++ x==E_SCLDMA_DBG_R ? "DBG_R" : \ ++ x==E_SCLDMA_FRM2_W ? "FRM2_W" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_BUFMD(x) (x==E_SCLDMA_BUF_MD_RING ? "RING" : \ ++ x==E_SCLDMA_BUF_MD_SWRING ? "SWRING" : \ ++ x==E_SCLDMA_BUF_MD_SINGLE ? "SINGLE" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_COLOR(x) (x==E_SCLDMA_COLOR_YUV422? "422PACK" : \ ++ x==E_SCLDMA_COLOR_YUV420 ? "YCSep420" : \ ++ x==E_SCLDMA_COLOR_YCSep422 ? "YCSep422" : \ ++ x==E_SCLDMA_COLOR_YUVSep422 ? "YUVSep422" : \ ++ x==E_SCLDMA_COLOR_YUVSep420 ? "YUVSep420" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_CLIENT(x) (x==E_SCLDMA_1_FRM_W ? "E_SCLDMA_1_FRM_W" : \ ++ x==E_SCLDMA_1_SNP_W ? "E_SCLDMA_1_SNP_W" : \ ++ x==E_SCLDMA_1_IMI_W ? "E_SCLDMA_1_IMI_W" : \ ++ x==E_SCLDMA_2_FRM_W ? "E_SCLDMA_2_FRM_W" : \ ++ x==E_SCLDMA_2_FRM2_W ? "E_SCLDMA_2_FRM2_W" : \ ++ x==E_SCLDMA_2_IMI_W ? "E_SCLDMA_2_IMI_W" : \ ++ x==E_SCLDMA_3_FRM_W ? "E_SCLDMA_3_FRM_W" : \ ++ x==E_SCLDMA_3_FRM_R ? "E_SCLDMA_3_FRM_R" : \ ++ x==E_SCLDMA_4_FRM_R ? "E_SCLDMA_4_FRM_R" : \ ++ "UNKNOWN") ++ ++#define PARSING_SCLDMA_ISR_LOG(x) (x==E_SCLDMA_ISR_LOG_ISPOFF ? "ISPOFF" : \ ++ x==E_SCLDMA_ISR_LOG_SNPONLY ? "SNPONLY" : \ ++ x==E_SCLDMA_ISR_LOG_SNPISR ? "SNPISR" : \ ++ x==E_SCLDMA_ISR_LOG_ISPON ? "ISPON" : \ ++ x==E_SCLDMA_ISR_LOG_SC1ON ? "SC1ON" : \ ++ x==E_SCLDMA_ISR_LOG_SC1OFF ? "SC1OFF" : \ ++ x==E_SCLDMA_ISR_LOG_SC2ON ? "SC2ON" : \ ++ x==E_SCLDMA_ISR_LOG_SC2OFF ? "SC2OFF" : \ ++ x==E_SCLDMA_ISR_LOG_SC1A ? "SC1A" : \ ++ x==E_SCLDMA_ISR_LOG_SC1N ? "SC1N" : \ ++ x==E_SCLDMA_ISR_LOG_SC2A ? "SC2A" : \ ++ x==E_SCLDMA_ISR_LOG_SC2N ? "SC2N" : \ ++ x==E_SCLDMA_ISR_LOG_FRMEND ? "FRMEND" : \ ++ "UNKNOWN") ++ ++#define OMX_VSPL_POLLTIME 80*1000 ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// _SCLDMA_Mutex ++/// use in scldma mutex,not include isr ++//////////////// ++MS_S32 _SCLDMA_Mutex = -1; ++ ++///////////////// ++/// _SCLIRQ_SCLDMA_Mutex ++/// scldma and sclirq mutex, include isr ++//////////////// ++MS_S32 _SCLIRQ_SCLDMA_Mutex = -1; ++ ++///////////////// ++/// gVsrcDBnotOpen ++/// if True ,DMA switch Double buffer not open ++//////////////// ++MS_BOOL gVsrcDBnotOpen; ++ ++///////////////// ++/// gu32FRMEvents ++/// used to save DMA event for diffenent client ++//////////////// ++MS_U32 gu32FRMEvents; ++MS_U32 gu32SC2FRMEvents; ++ ++///////////////// ++/// gu8ISPcount ++/// save frame count from ISP_hw - scl_delay ++//////////////// ++MS_U8 gu8ISPcount; ++ ++///////////////// ++/// gu64FRMDoneTime ++/// save frame done time. ++//////////////// ++MS_U64 gu64FRMDoneTime[E_SCLDMA_CLIENT_NUM][MAX_BUFFER_COUNT+1]; ++MS_U32 gu32SendTime[E_SCLDMA_CLIENT_NUM]; ++MS_U8 gbSendPoll[E_SCLDMA_CLIENT_NUM]; ++ ++///////////////// ++/// gu32TrigCount ++/// save dma trig off times. ++//////////////// ++MS_U32 gu32TrigCount[E_SCLDMA_CLIENT_NUM]; ++MS_BOOL gbForceClose[E_SCLDMA_CLIENT_NUM]; ++MS_U8 gu8ResetCount[E_SCLDMA_CLIENT_NUM]; ++MS_U8 gu8DMAErrCount[E_SCLDMA_CLIENT_NUM]; ++ST_SCLDMA_INFO_TYPE gstScldmaInfo; ++ST_SCLDMA_BUFFER_QUEUE_CONFIG gstScldmaBufferQueue[E_SCLDMA_CLIENT_NUM]; ++ ++MS_BOOL gbScldmaSuspend; ++MS_BOOL gbDBStatus; ++#if SCLDMA_IRQ_EN ++EN_SCLDMA_IRQ_MODE_TYPE genIrqMode[E_SCLDMA_CLIENT_NUM]; ++#endif ++//------------------------------------------------------------------------------------------------- ++// Functions/ ++//------------------------------------------------------------------------------------------------- ++void Drv_SCLDMA_SetThreadOnOffFlag(MS_BOOL bEn,ST_SCLDMA_THREAD_CONFIG *stthcfg) ++{ ++ stthcfg->flag = bEn; ++} ++void _Drv_SCLDMA_SC1OnOff(EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn) ++{ ++ Hal_SCLDMA_SetSC1HandshakeForce(enRW, bEn); ++ Hal_SCLDMA_SetSC1DMAEn(enRW, bEn); ++} ++void _Drv_SCLDMA_SC1OnOffWithoutDoubleBuffer ++ (EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn,EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ _Drv_SCLDMA_SC1OnOff(enRW, bEn); ++ } ++ else ++ { ++ if(bEn) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_ON); ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_OFF); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_OFF); ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_ON); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&(Get_DBGMG_SCLDMAclient(enClientType,1)), ++ "[DRMSCLDMA]%s %d wait for blanking\n", ++ __FUNCTION__,enClientType); ++ } ++} ++void _Drv_SCLDMA_SC2OnOff(EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn) ++{ ++ Hal_SCLDMA_SetSC2HandshakeForce(enRW, bEn); ++ Hal_SCLDMA_SetSC1ToSC2HandshakeForce(bEn); ++ Hal_SCLDMA_SetSC2DMAEn(enRW, bEn); ++} ++void _Drv_SCLDMA_SC2OnOffWithoutDoubleBuffer ++ (EN_SCLDMA_RW_MODE_TYPE enRW,MS_BOOL bEn,EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ if(Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ _Drv_SCLDMA_SC2OnOff(enRW, bEn); ++ } ++ else ++ { ++ if(bEn) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_ON); ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_OFF); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_OFF); ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_NEXT_ON); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&(Get_DBGMG_SCLDMAclient(enClientType,1)), ++ "[DRMSCLDMA]%s %d wait for blanking\n", ++ __FUNCTION__,enClientType); ++ } ++} ++void _Drv_SCLDMA_SWRegenVSyncTrigger(EN_SCLDMA_VS_ID_TYPE enIDType) ++{ ++ Hal_SCLDMA_TrigRegenVSync(enIDType,1); ++} ++void _Drv_SCLDMA_SetVsyncRegenMode(EN_SCLDMA_VS_ID_TYPE enIDType, EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigType) ++{ ++ Hal_SCLDMA_SetVSyncRegenMode(enIDType,enTrigType); ++} ++void _Drv_SCLDMA_SetVsyncTrigConfig(EN_SCLDMA_VS_ID_TYPE enIDType) ++{ ++ //hard code by hw setting ++ Hal_SCLDAM_SetRegenVSyncStartPoint(enIDType,10); ++ Hal_SCLDAM_SetRegenVSyncWidth(enIDType,40); ++} ++void _Drv_SCLDMA_ResetGlobalParameter(void) ++{ ++ MS_U8 u8ClientIdx; ++ MS_U8 y; ++ DRV_SCLDMA_MUTEX_LOCK(); ++ for(u8ClientIdx=0; u8ClientIdxu32IRQNum; ++ if(Drv_SCLIRQ_Suspend(&stSclIrqCfg)) ++ { ++ bRet = TRUE; ++ gbScldmaSuspend = 1; ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s Suspend fail\n", __FUNCTION__)); ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s not all scldma suspend\n",__FUNCTION__); ++ bRet = TRUE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s already suspend\n",__FUNCTION__); ++ bRet = TRUE; ++ } ++ ++ return bRet; ++} ++ ++MS_BOOL Drv_SCLDMA_Resume(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ ST_SCLIRQ_SUSPEND_RESUME_CONFIG stSclIrqCfg; ++ MS_BOOL bRet = TRUE; ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s(%d), ID:%s(%d), bSuspend=%d\n", ++ __FUNCTION__, __LINE__, PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID, gbScldmaSuspend); ++ MsOS_Memset(&stSclIrqCfg,0,sizeof(ST_SCLIRQ_SUSPEND_RESUME_CONFIG)); ++ if(gbScldmaSuspend == 1) ++ { ++ stSclIrqCfg.u32IRQNUM = pCfg->u32IRQNum; ++ if(Drv_SCLIRQ_Resume(&stSclIrqCfg)) ++ { ++ DRV_SCLDMA_MUTEX_LOCK(); ++ gstScldmaInfo.u64mask = 0; ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ _Drv_SCLDMA_HWInitProcess(); ++ gbScldmaSuspend = 0; ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_EventID(), E_SCLIRQ_EVENT_RESUME); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SC3EventID(), E_SCLIRQ_SC3EVENT_RESUME); ++ bRet = TRUE; ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s Resume fail\n", __FUNCTION__)); ++ bRet = FALSE; ++ } ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s already Resume\n",__FUNCTION__); ++ bRet = TRUE; ++ } ++ ++ return bRet; ++} ++void Drv_SCLDMA_Exit(unsigned char bCloseISR) ++{ ++ if(_SCLDMA_Mutex != -1) ++ { ++ MsOS_DeleteMutex(_SCLDMA_Mutex); ++ _SCLDMA_Mutex = -1; ++ } ++ if(_SCLIRQ_SCLDMA_Mutex != -1) ++ { ++ MsOS_DeleteSpinlock(_SCLIRQ_SCLDMA_Mutex); ++ _SCLDMA_Mutex = -1; ++ } ++ if(bCloseISR) ++ { ++ Drv_SCLIRQ_Exit(); ++ } ++} ++MS_BOOL Drv_SCLDMA_Init(ST_SCLDMA_INIT_CONFIG *pInitCfg) ++{ ++ char word[] = {"_SCLDMA_Mutex"}; ++ char word2[] = {"_IRQDMA_Mutex"}; ++ //int i; ++ ST_SCLIRQ_INIT_CONFIG stIRQInitCfg; ++ MsOS_Memset(&stIRQInitCfg,0,sizeof(ST_SCLIRQ_INIT_CONFIG)); ++ if(_SCLDMA_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&EN_DBGMG_SCLDMALEVEL_ELSE, "[DRVSCLDMA]%s already done\n",__FUNCTION__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s MsOS_Init Fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ _SCLDMA_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ #if USE_RTK ++ _SCLIRQ_SCLDMA_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word2, MSOS_PROCESS_SHARED); ++ #else ++ _SCLIRQ_SCLDMA_Mutex = MsOS_CreateSpinlock(E_MSOS_FIFO, word2, MSOS_PROCESS_SHARED); ++ #endif ++ if (_SCLDMA_Mutex == -1) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s create mutex fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++ ++ stIRQInitCfg.u32RiuBase = pInitCfg->u32RIUBase; ++ ++ ++ // init processing ++ ++ Hal_SCLDMA_SetRiuBase(pInitCfg->u32RIUBase); ++ if(Drv_SCLIRQ_Init(&stIRQInitCfg) == FALSE) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s Init IRQ Fail\n", __FUNCTION__)); ++ return FALSE; ++ } ++ _Drv_SCLDMA_InitVariable(); ++ ++#if SCLDMA_IRQ_EN ++ ++ gstScldmaInfo.s32IrqEventId = MsOS_CreateEventGroup("SCLDMA_IRQ_EVENT"); ++ ++ if(gstScldmaInfo.s32IrqEventId < 0) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s(%d) Create Event Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ gstScldmaInfo.s32IrqTaskid = MsOS_CreateTask((TaskEntry)_Drv_SCLDMA_Irq_Event_Task, ++ (MS_U32)NULL, ++ TRUE, ++ (const char*)"DrvScldma_Event_Task"); ++ ++ if(gstScldmaInfo.s32IrqTaskid < 0) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s(%d) Create Task Fail\n", __FUNCTION__, __LINE__)); ++ MsOS_DeleteEventGroup(gstScldmaInfo.s32IrqEventId); ++ return FALSE; ++ } ++ ++ gstScldmaInfo.s32IrqTimerId = MsOS_CreateTimer( _Drv_SCLDMA_CheckIrq_TimerCallback, ++ 5, ++ 5, ++ TRUE, ++ (char*)"SCLDMA_IRQ_TIMER"); ++ ++ if(gstScldmaInfo.s32IrqTimerId < 0) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s(%d) Create Timer Fail\n", __FUNCTION__, __LINE__)); ++ MsOS_DeleteEventGroup(gstScldmaInfo.s32IrqEventId); ++ MsOS_DeleteTask(gstScldmaInfo.s32IrqTaskid); ++ return FALSE; ++ } ++#endif ++ ++ _Drv_SCLDMA_HWInitProcess(); ++ ++ return TRUE; ++} ++ ++void Drv_SCLDMA_Sys_Init(MS_BOOL bEn) ++{ ++#if ENABLE_RING_DB ++ if(bEn) ++ { ++ ST_SCLDMA_RW_CONFIG stIMICfg; ++ MsOS_Memset(&stIMICfg,0,sizeof(ST_SCLDMA_RW_CONFIG)); ++ stIMICfg.enRWMode = E_SCLDMA_IMI_W; ++ stIMICfg.u16Height = HD_Height; ++ stIMICfg.u16Width = HD_Width; ++ stIMICfg.u8MaxIdx = 0; ++ stIMICfg.u8Flag = 1; ++ stIMICfg.enBuffMode = E_SCLDMA_BUF_MD_RING; ++ stIMICfg.u32Base_Y[0] = SCL_IMIinitAddr; ++ stIMICfg.u32Base_C[0] = SCL_IMIinitAddr; ++ stIMICfg.u32Base_V[0] = SCL_IMIinitAddr; ++ stIMICfg.enColor = E_SCLDMA_COLOR_YUV420 ; ++ Drv_SCLDMA_SetDMAClientConfig(E_SCLDMA_ID_1_W,&stIMICfg); ++ } ++ else ++ { ++ Hal_SCLDMA_SetIMIClientReset(); ++ } ++#endif ++ ++ printf("[DRVSCLDMA] Double Buffer Status :%hhd\n",gbDBStatus); ++} ++void _Drv_SCLDMA_ResetGlobalSwitchByID(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ EN_SCLDMA_CLIENT_TYPE u8ClientIdx; ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ for(u8ClientIdx=E_SCLDMA_1_FRM_W; u8ClientIdxenBuffMode; ++ gstScldmaInfo.bMaxid[enClientType] = stCfg->u8MaxIdx; ++ gstScldmaInfo.u64mask = _Drv_SCLDMA_GetIRQMask(); ++ gstScldmaInfo.enColor[enClientType] = stCfg->enColor; ++ gstScldmaInfo.u16FrameWidth[enClientType] = stCfg->u16Width; ++ gstScldmaInfo.u16FrameHeight[enClientType] = stCfg->u16Height; ++ for (u8BufferIdx = 0; u8BufferIdx <= stCfg->u8MaxIdx; u8BufferIdx++) ++ { ++ gstScldmaInfo.u32Base_Y[enClientType][u8BufferIdx] = stCfg->u32Base_Y[u8BufferIdx]; ++ gstScldmaInfo.u32Base_C[enClientType][u8BufferIdx] = stCfg->u32Base_C[u8BufferIdx]; ++ gstScldmaInfo.u32Base_V[enClientType][u8BufferIdx] = stCfg->u32Base_V[u8BufferIdx]; ++ } ++ Drv_SCLIRQ_Set_Mask(gstScldmaInfo.u64mask); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ if(_Is_SWRingMode(enClientType) && _Is_SWRingModeBufferNotReady(enClientType)) ++ { ++ gstScldmaBufferQueue[enClientType].pstHead = MsOS_VirMemalloc(SCLDMA_BUFFER_QUEUE_OFFSET*stCfg->u8MaxIdx); ++ if(!gstScldmaBufferQueue[enClientType].pstHead) ++ { ++ SCL_ERR("[DRVSCLDMA]%s(%d) Init gstScldmaBufferQueue Fail\n", __FUNCTION__, __LINE__); ++ return ; ++ } ++ gstScldmaBufferQueue[enClientType].pstTail = gstScldmaBufferQueue[enClientType].pstHead ++ + 1* stCfg->u8MaxIdx; ++ gstScldmaBufferQueue[enClientType].pstWrite = gstScldmaBufferQueue[enClientType].pstHead; ++ gstScldmaBufferQueue[enClientType].pstRead = gstScldmaBufferQueue[enClientType].pstHead; ++ gstScldmaBufferQueue[enClientType].pstWriteAlready = gstScldmaBufferQueue[enClientType].pstHead; ++ gstScldmaBufferQueue[enClientType].bUsed = 1; ++ gstScldmaBufferQueue[enClientType].u8Bufferflag= stCfg->u8Flag; ++ stCfg->u8MaxIdx = 0;//single change buffer ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++} ++void _Drv_SCLDMA_SetVsyncTrigMode(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ if(_Is_SC3Singlemode(enClientType)) ++ { ++ _Drv_SCLDMA_SetVsyncTrigConfig(E_SCLDMA_VS_ID_SC3); ++ _Drv_SCLDMA_SetVsyncRegenMode(E_SCLDMA_VS_ID_SC3, E_SCLDMA_VS_TRIG_MODE_SWTRIGGER); ++ } ++ else if(_Is_SC3Ringmode(enClientType)|| _Is_SC3SWRingmode(enClientType)) ++ { ++ _Drv_SCLDMA_SetVsyncRegenMode(E_SCLDMA_VS_ID_SC3, E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC); ++ } ++} ++MS_BOOL Drv_SCLDMA_SetDMAClientConfig(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_RW_CONFIG *stCfg) ++{ ++ MS_BOOL bRet = TRUE; ++ MS_U8 u8BufferIdx; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ MS_U32 u32Time = 0; ++ MS_U32 u32Events; ++ u32Time = (((MS_U32)MsOS_GetSystemTimeStamp())); ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,stCfg->enRWMode); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,0), ++ "[DRVSCLDMA]%s %d, DmaID:%s(%d), Flag:%x, RW:%s(%d), Buf:%s(%d), color:%s(%d), (W:%d, H:%d)\n", ++ __FUNCTION__, __LINE__, ++ PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID, ++ stCfg->u8Flag, ++ PARSING_SCLDMA_RWMD(stCfg->enRWMode), stCfg->enRWMode, ++ PARSING_SCLDMA_BUFMD(stCfg->enBuffMode), stCfg->enBuffMode, ++ PARSING_SCLDMA_COLOR(stCfg->enColor), stCfg->enColor, ++ stCfg->u16Width, stCfg->u16Height); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,0), ++ "[DRVSCLDMA]%s %d, maxbuf:%d, (%lx, %lx, %lx), (%lx, %lx, %lx),(%lx, %lx, %lx), (%lx, %lx, %lx) \n", ++ __FUNCTION__, __LINE__, ++ stCfg->u8MaxIdx, ++ stCfg->u32Base_Y[0], stCfg->u32Base_C[0],stCfg->u32Base_V[0], ++ stCfg->u32Base_Y[1], stCfg->u32Base_C[1],stCfg->u32Base_V[1], ++ stCfg->u32Base_Y[2], stCfg->u32Base_C[2],stCfg->u32Base_V[2], ++ stCfg->u32Base_Y[3], stCfg->u32Base_C[3],stCfg->u32Base_V[3]); ++ ++ // check ++ if(SCLDMA_CHECK_ALIGN(stCfg->u16Height, 2)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]: Height must be align 2\n")); ++ bRet = FALSE; ++ } ++ ++ if(stCfg->enColor == E_SCLDMA_COLOR_YUV422 && SCLDMA_CHECK_ALIGN(stCfg->u16Width, 8)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: Width must be align 8\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ else if(stCfg->enColor == E_SCLDMA_COLOR_YUV420 &&SCLDMA_CHECK_ALIGN(stCfg->u16Width, 16)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: Width must be align 16\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ else if(stCfg->enColor == E_SCLDMA_COLOR_YCSep422 &&SCLDMA_CHECK_ALIGN(stCfg->u16Width, 16)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: Width must be align 16\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ else if(stCfg->enColor == E_SCLDMA_COLOR_YUVSep422 &&SCLDMA_CHECK_ALIGN(stCfg->u16Width, 16)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: Width must be align 16\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ else if(stCfg->enColor == E_SCLDMA_COLOR_YUVSep420 &&SCLDMA_CHECK_ALIGN(stCfg->u16Width, 16)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: Width must be align 16\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ ++ if(stCfg->enBuffMode == E_SCLDMA_BUF_MD_SINGLE && stCfg->u8MaxIdx > 1) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: More than 1 buffer to SINGLE mode\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ ++ if(stCfg->enRWMode == E_SCLDMA_RW_NUM) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: RW mode is not coreect\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ } ++ ++ for(u8BufferIdx=0; u8BufferIdx<=stCfg->u8MaxIdx; u8BufferIdx++) ++ { ++ if( SCLDMA_CHECK_ALIGN(stCfg->u32Base_Y[u8BufferIdx], 8)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: YBase must be 8 byte align\n", __FUNCTION__, __LINE__)); ++ bRet = FALSE; ++ break; ++ } ++ ++ if(((stCfg->enColor == E_SCLDMA_COLOR_YUV420)||(stCfg->enColor == E_SCLDMA_COLOR_YCSep422)) && ++ SCLDMA_CHECK_ALIGN(stCfg->u32Base_C[u8BufferIdx], 8)) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]%s %d: CBase must be 8 byte align DmaID:%s(%d)\n", __FUNCTION__, __LINE__,PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID)); ++ bRet = FALSE; ++ break; ++ } ++ } ++ ++ if(stCfg->enColor == E_SCLDMA_COLOR_YUV422) ++ { ++ for(u8BufferIdx=0; u8BufferIdx<=stCfg->u8MaxIdx; u8BufferIdx++) ++ { ++ if((stCfg->u32Base_C[u8BufferIdx] != (stCfg->u32Base_Y[u8BufferIdx] + 16) )) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA]Error:%s %d: YUV422 CBase_%08lx, YBase_%08lx, \n", ++ __FUNCTION__, __LINE__, stCfg->u32Base_Y[u8BufferIdx], stCfg->u32Base_C[u8BufferIdx])); ++ bRet = FALSE; ++ } ++ } ++ } ++ if(_IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ if(enSCLDMA_ID ==E_SCLDMA_ID_3_W || enSCLDMA_ID ==E_SCLDMA_ID_3_R) ++ { ++ if(_IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SC3EventID(), E_SCLIRQ_SC3EVENT_DONE, &u32Events, E_OR, 100); // get status: FRM END ++ _ReSetFlagType(E_SCLDMA_3_FRM_R,E_SCLDMA_FLAG_ACTIVE); ++ _ReSetFlagType(E_SCLDMA_3_FRM_W,E_SCLDMA_FLAG_ACTIVE); ++ } ++ } ++ else ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 1000); // get status: FRM END ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE); ++ } ++ SCL_ERR("[DRVSCLDMA] %s::%d %s_%s still R/W @:%lu\n", ++ __FUNCTION__,enClientType, PARSING_SCLDMA_ID(enSCLDMA_ID), PARSING_SCLDMA_RWMD(stCfg->enRWMode),u32Time); ++ ++ } ++ ++ if(bRet == FALSE) ++ { ++ return FALSE; ++ } ++ ++ _Drv_SCLDMA_SetDMAInformationForGlobal(enClientType, stCfg); ++ _Drv_SCLDMA_SetVsyncTrigMode(enClientType); ++ ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetSC1DMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ case E_SCLDMA_ID_2_W: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetSC2DMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ case E_SCLDMA_ID_3_W: ++ case E_SCLDMA_ID_3_R: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetSC3DMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ case E_SCLDMA_ID_PNL_R: ++ DRV_SCLDMA_MUTEX_LOCK(); ++ Hal_SCLDMA_SetDisplayDMAConfig(stCfg); ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ break; ++ ++ default: ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++MS_U16 _Drv_SCLDMA_GetActiveIRQNum(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16IrqNum; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16IrqNum = SCLIRQ_SC1_FRM_W_ACTIVE; ++ break; ++ case E_SCLDMA_1_SNP_W: ++ u16IrqNum = SCLIRQ_SC1_SNP_W_ACTIVE; ++ break; ++ case E_SCLDMA_1_IMI_W: ++ u16IrqNum = SCLIRQ_SC1_SNPI_W_ACTIVE; ++ break; ++ case E_SCLDMA_2_FRM_W: ++ u16IrqNum = SCLIRQ_SC2_FRM_W_ACTIVE; ++ break; ++ case E_SCLDMA_2_FRM2_W: ++ u16IrqNum = SCLIRQ_SC2_FRM2_W_ACTIVE; ++ break; ++ case E_SCLDMA_2_IMI_W: ++ u16IrqNum = SCLIRQ_SC2_FRMI_W_ACTIVE; ++ break; ++ case E_SCLDMA_3_FRM_W: ++ u16IrqNum = SCLIRQ_SC3_DMA_W_ACTIVE; ++ break; ++ case E_SCLDMA_3_FRM_R: ++ u16IrqNum = SCLIRQ_SC3_DMA_R_ACTIVE; ++ break; ++ case E_SCLDMA_4_FRM_R: ++ u16IrqNum = SCLIRQ_SC1_DBG_R_ACTIVE; ++ break; ++ default: ++ u16IrqNum = SCLIRQ_RESERVED; ++ break; ++ } ++ ++ return u16IrqNum; ++} ++void _Drv_SCLDMA_ResetTrigCount(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn) ++{ ++ if(!bEn) ++ { ++ gu32TrigCount[enClientType]++; ++ if(gu32TrigCount[enClientType]==0xEFFFFFFE) ++ { ++ gu32TrigCount[enClientType] = 1; ++ } ++ } ++} ++void Drv_SCLDMA_SetSWReTrigCount(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn) ++{ ++ //for ISR don;t need to lock ++ if(bEn) ++ { ++ gu8ResetCount[enClientType]++; ++ } ++ else ++ { ++ if(gu8ResetCount[enClientType]) ++ { ++ gu8ResetCount[enClientType]--; ++ } ++ ++ } ++} ++void Drv_SCLDMA_SetDMAIgnoreCount(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn) ++{ ++ //for ISR don;t need to lock ++ if(bEn) ++ { ++ gu8DMAErrCount[enClientType]++; ++ } ++ else ++ { ++ if(gu8DMAErrCount[enClientType]) ++ { ++ gu8DMAErrCount[enClientType]--; ++ } ++ ++ } ++} ++MS_BOOL Drv_SCLDMA_SetISRHandlerDMAOff(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn) ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ MS_U64 u64ActN; ++ MS_BOOL bRet = 0; ++ if(gstScldmaInfo.bDMAOnOff[enClientType] == bEn &&_Is_RingMode(enClientType)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClientType,1), ++ "[DRVSCLDMA] %s:: enClientType:%d still ON/OFF %hhd\n", ++ __FUNCTION__,enClientType,bEn); ++ } ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ case E_SCLDMA_2_FRM_W: ++ case E_SCLDMA_3_FRM_W: ++ enRWMode = E_SCLDMA_FRM_W; ++ break; ++ case E_SCLDMA_1_SNP_W: ++ enRWMode = E_SCLDMA_SNP_W; ++ break; ++ case E_SCLDMA_2_FRM2_W: ++ enRWMode = E_SCLDMA_FRM2_W; ++ break; ++ case E_SCLDMA_1_IMI_W: ++ case E_SCLDMA_2_IMI_W: ++ enRWMode = E_SCLDMA_IMI_W; ++ break; ++ case E_SCLDMA_3_FRM_R: ++ enRWMode = E_SCLDMA_FRM_R; ++ break; ++ case E_SCLDMA_4_FRM_R: ++ enRWMode = E_SCLDMA_DBG_R; ++ break; ++ default: ++ enRWMode = E_SCLDMA_RW_NUM; ++ break; ++ ++ } ++ if(enClientType == E_SCLDMA_1_FRM_W || enClientType == E_SCLDMA_1_SNP_W || enClientType == E_SCLDMA_1_IMI_W) ++ { ++ if(bEn && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_Get_Flag((_Drv_SCLDMA_GetActiveIRQNum(enClientType)+1), &u64ActN); ++ if(!u64ActN) ++ { ++ _Drv_SCLDMA_SC1OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ } ++ else ++ { ++ _Drv_SCLDMA_SC1OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ else if(enClientType == E_SCLDMA_2_FRM_W || enClientType == E_SCLDMA_2_IMI_W || enClientType == E_SCLDMA_2_FRM2_W) ++ { ++ if(bEn && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_Get_Flag((_Drv_SCLDMA_GetActiveIRQNum(enClientType)+1), &u64ActN); ++ if(!u64ActN) ++ { ++ _Drv_SCLDMA_SC2OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ } ++ else ++ { ++ _Drv_SCLDMA_SC2OnOff(enRWMode, bEn); ++ bRet = bEn; ++ } ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ else if(enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ if(bEn && DoubleBufferStatus) ++ { ++ Drv_SCLIRQ_Get_Flag((_Drv_SCLDMA_GetActiveIRQNum(enClientType)+1), &u64ActN); ++ if(!u64ActN) ++ { ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_R, bEn); ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_W, bEn); ++ bRet = bEn; ++ } ++ } ++ else ++ { ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_R, bEn); ++ Hal_SCLDMA_SetSC3DMAEn(E_SCLDMA_FRM_W, bEn); ++ bRet = bEn; ++ } ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ else ++ { ++ Hal_SCLDMA_SetDisplayDMAEn(enRWMode, bEn); ++ _Drv_SCLDMA_ResetTrigCount(enClientType,bEn); ++ } ++ ++ if(enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClientType,1), "[DRVSCLDMA]%s Client:%s trig off\n", ++ __FUNCTION__,PARSING_SCLDMA_CLIENT(enClientType)); ++ } ++ else ++ { ++ if(bEn) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(8,1), "[DRVSCLDMA]%s Client:%s trig on\n", ++ __FUNCTION__,PARSING_SCLDMA_CLIENT(enClientType)); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(8,1), "[DRVSCLDMA]%s Client:%s trig off\n", ++ __FUNCTION__,PARSING_SCLDMA_CLIENT(enClientType)); ++ } ++ } ++ return bRet; ++} ++void Drv_SCLDMA_DoubleBufferOnOffById(MS_BOOL bEn, EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ if(enSCLDMA_ID <= E_SCLDMA_ID_2_W) ++ { ++ Hal_SCLDMA_SetHandshakeDoubleBuffer(bEn); ++ gVsrcDBnotOpen = !bEn; ++ } ++ Hal_SCLDMA_SetDMAEnableDoubleBuffer(bEn,enSCLDMA_ID); ++} ++void Drv_SCLDMA_SetISPFrameCount(void) ++{ ++ gu8ISPcount = Hal_SCLDMA_GetISPFrameCountReg(); ++ if(SCL_DELAYFRAME == 1) ++ { ++ gu8ISPcount = (gu8ISPcount==0) ? 0x7F : (gu8ISPcount -1); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()==EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLDMA]ISP Count:%hhx\n",gu8ISPcount); ++} ++void Drv_SCLDMA_SetSclFrameDoneTime(EN_SCLDMA_CLIENT_TYPE enClientType, MS_U64 u64FRMDoneTime) ++{ ++ MS_U16 u16RealIdx; ++ if(_Is_RingMode(enClientType)) ++ { ++ u16RealIdx = _GetIdxType(enClientType,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ } ++ else ++ { ++ u16RealIdx = 0; ++ } ++ gu64FRMDoneTime[enClientType][u16RealIdx] = (MS_U64)u64FRMDoneTime; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()==EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLDMA]%d FRMDoneTime:%llu\n",enClientType,u64FRMDoneTime); ++} ++MS_U64 Drv_SCLDMA_GetSclFrameDoneTime(EN_SCLDMA_CLIENT_TYPE enClientType, MS_U8 u8Count) ++{ ++ return gu64FRMDoneTime[enClientType][u8Count]; ++} ++EN_SCLDMA_DB_STATUS_TYPE Drv_SCLDMA_GetVsrcDoubleBufferStatus(MS_U32 u32Event) ++{ ++ MS_U32 enClientIdx; ++ MS_U8 bNeedOff = 0; ++ if(_Is_OnlySC1SNPSingleDone(u32Event))//only sc1 snp ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE,"[DRVSCLDMA] ONLY_SC1_SNP_SI_NEED_OFF \n"); ++ return EN_SCLDMA_DB_STATUS_NEED_OFF;//db off ++ } ++ else if(_Is_OnlySC1FRMSingleDone(u32Event))//only sc1 frm snp ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE,"[DRVSCLDMA] ONLY_SC1_FRM_SI_NEED_OFF \n"); ++ return EN_SCLDMA_DB_STATUS_NEED_OFF;//db off ++ } ++ else if(_Is_OnlySC2FRMSingleDone(u32Event))//only sc2 frm snp ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE,"[DRVSCLDMA] ONLY_SC2_FRM_SI_NEED_OFF \n"); ++ return EN_SCLDMA_DB_STATUS_NEED_OFF;//db off ++ } ++ else ++ { ++ for(enClientIdx= E_SCLDMA_1_FRM_W; enClientIdxenRWMode); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%s(%d), DmaID:%s(%d), RW:%s(%d), En:%d @:%lu\n", ++ __FUNCTION__, __LINE__, ++ PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID, ++ PARSING_SCLDMA_RWMD(stCfg->enRWMode), stCfg->enRWMode, ++ stCfg->bEn,u32Time); ++ if(gstScldmaInfo.bDMAOnOff[enClientType] == 1 && gstScldmaInfo.bDMAOnOff[enClientType] == stCfg->bEn) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] %s:: %s_%s still R/W \n", ++ __FUNCTION__, PARSING_SCLDMA_ID(enSCLDMA_ID), PARSING_SCLDMA_RWMD(stCfg->enRWMode))); ++ return FALSE; ++ } ++ if(gbForceClose[enClientType]) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] %s:: %s_%s BLOCK \n", ++ __FUNCTION__, PARSING_SCLDMA_ID(enSCLDMA_ID), PARSING_SCLDMA_RWMD(stCfg->enRWMode))); ++ return FALSE; ++ } ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ gstScldmaInfo.bDMAOnOff[enClientType] = stCfg->bEn; ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if(stCfg->bEn) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ gstScldmaInfo.bDmaflag[enClientType] = E_SCLDMA_FLAG_BLANKING; ++ gstScldmaInfo.bDMAidx[enClientType] = (E_SCLDMA_ACTIVE_BUFFER_SCL|(gstScldmaInfo.bMaxid[enClientType]<<4)); ++ if(enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ gstScldmaInfo.bDMAidx[enClientType] = (E_SCLDMA_ACTIVE_BUFFER_SCL|(0x5<<4)); ++ gstScldmaInfo.bDmaflag[enClientType] = 0; ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ if(stCfg->bEn) ++ { ++ _Drv_SCLDMA_SetClkOnOff(enSCLDMA_ID,stCfg->stclk,1); ++ } ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ _Drv_SCLDMA_SC1OnOff(stCfg->enRWMode, stCfg->bEn); ++ break; ++ ++ case E_SCLDMA_ID_2_W: ++ _Drv_SCLDMA_SC2OnOff(stCfg->enRWMode, stCfg->bEn); ++ break; ++ ++ case E_SCLDMA_ID_3_W: ++ Hal_SCLDMA_SetSC3DMAEn(stCfg->enRWMode, stCfg->bEn); ++ if(stCfg->bEn) ++ { ++ Hal_SCLDMA_TrigRegenVSync(E_SCLDMA_VS_ID_SC3,0); ++ } ++ break; ++ ++ case E_SCLDMA_ID_3_R: ++ Hal_SCLDMA_SetSC3DMAEn(stCfg->enRWMode, stCfg->bEn); ++ break; ++ ++ case E_SCLDMA_ID_PNL_R: ++ Hal_SCLDMA_SetDisplayDMAEn(stCfg->enRWMode, stCfg->bEn); ++ ++ break; ++ ++ default: ++ return FALSE; ++ } ++ return TRUE; ++} ++MS_BOOL _Drv_SCLDMA_SetDMAOnOff(EN_SCLDMA_ID_TYPE enSCLDMA_ID,ST_SCLDMA_ONOFF_CONFIG *stCfg) ++{ ++ MS_BOOL bSingleMode; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,stCfg->enRWMode); ++ bSingleMode = gstScldmaInfo.enBuffMode[enClientType] == E_SCLDMA_BUF_MD_SINGLE ? TRUE : FALSE; ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ if(DoubleBufferStatus) ++ { ++ _Drv_SCLDMA_SC1OnOff(stCfg->enRWMode, stCfg->bEn); ++ } ++ else ++ { ++ _Drv_SCLDMA_SC1OnOffWithoutDoubleBuffer(stCfg->enRWMode, stCfg->bEn,enClientType); ++ } ++ break; ++ ++ case E_SCLDMA_ID_2_W: ++ if(DoubleBufferStatus) ++ { ++ _Drv_SCLDMA_SC2OnOff(stCfg->enRWMode, stCfg->bEn); ++ } ++ else ++ { ++ _Drv_SCLDMA_SC2OnOffWithoutDoubleBuffer(stCfg->enRWMode, stCfg->bEn,enClientType); ++ } ++ break; ++ ++ case E_SCLDMA_ID_3_W: ++ Hal_SCLDMA_SetSC3DMAEn(stCfg->enRWMode, stCfg->bEn); ++ if(bSingleMode && stCfg->bEn) ++ { ++ _Drv_SCLDMA_SWRegenVSyncTrigger(E_SCLDMA_VS_ID_SC3); ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetFlagType(E_SCLDMA_3_FRM_W,E_SCLDMA_FLAG_EVERDMAON,~(E_SCLDMA_FLAG_DMAOFF)); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else if(!bSingleMode && stCfg->bEn) ++ { ++ _Drv_SCLDMA_SetVsyncRegenMode(E_SCLDMA_VS_ID_SC3,E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC); ++ } ++ break; ++ ++ case E_SCLDMA_ID_3_R: ++ Hal_SCLDMA_SetSC3DMAEn(stCfg->enRWMode, stCfg->bEn); ++ break; ++ ++ case E_SCLDMA_ID_PNL_R: ++ Hal_SCLDMA_SetDisplayDMAEn(stCfg->enRWMode, stCfg->bEn); ++ if(bSingleMode && stCfg->bEn) ++ { ++ Drv_SCLDMA_DoubleBufferOnOffById(TRUE,E_SCLDMA_ID_PNL_R); ++ } ++ ++ break; ++ ++ default: ++ return FALSE; ++ } ++ return TRUE; ++} ++MS_BOOL Drv_SCLDMA_SetDMAClientOnOff(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ONOFF_CONFIG *stCfg ) ++{ ++ MS_BOOL bSingleMode; ++ MS_U32 u32Time = 0; ++ MS_U32 u32Events; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ static MS_U16 u16count[E_SCLDMA_CLIENT_NUM] = {0,0,0,0,0,0,0,0,0}; ++ u32Time = (((MS_U32)MsOS_GetSystemTimeStamp())); ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,stCfg->enRWMode); ++ if(_Is_SWRingMode(enClientType)) ++ { ++ _Drv_SCLDMA_SetSWRingModeDMAClientOnOff(enSCLDMA_ID,stCfg); ++ return 1; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%s(%d), DmaID:%s(%d), RW:%s(%d), En:%d @:%lu\n", ++ __FUNCTION__, __LINE__, ++ PARSING_SCLDMA_ID(enSCLDMA_ID), enSCLDMA_ID, ++ PARSING_SCLDMA_RWMD(stCfg->enRWMode), stCfg->enRWMode, ++ stCfg->bEn,u32Time); ++ bSingleMode = gstScldmaInfo.enBuffMode[enClientType] == E_SCLDMA_BUF_MD_SINGLE ? TRUE : FALSE; ++ if(bSingleMode) ++ { ++ if(stCfg->bEn && _IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE) && ++ ((enClientType==E_SCLDMA_3_FRM_W)||(enClientType==E_SCLDMA_3_FRM_R))) ++ { ++ u16count[enClientType]++; ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] %s::%d %s_%s still R/W @:%lu\n", ++ __FUNCTION__,enClientType, PARSING_SCLDMA_ID(enSCLDMA_ID), PARSING_SCLDMA_RWMD(stCfg->enRWMode),u32Time)); ++ if(u16count[enClientType]<2) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SC3EventID(),E_SCLIRQ_SC3EVENT_DONE, &u32Events, E_OR, 50); ++ if(_IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ _ReSetFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE); ++ } ++ u16count[enClientType] = 0; ++ } ++ else ++ { ++ u16count[enClientType] = 0; ++ } ++ } ++ else ++ { ++ u16count[enClientType] = 0; ++ } ++ if(gbForceClose[enClientType]) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] %s:: %s_%s BLOCK \n", ++ __FUNCTION__, PARSING_SCLDMA_ID(enSCLDMA_ID), PARSING_SCLDMA_RWMD(stCfg->enRWMode))); ++ return FALSE; ++ } ++ } ++ else ++ { ++ if(gbForceClose[enClientType]) ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] %s:: %s_%s BLOCK \n", ++ __FUNCTION__, PARSING_SCLDMA_ID(enSCLDMA_ID), PARSING_SCLDMA_RWMD(stCfg->enRWMode))); ++ return FALSE; ++ } ++ } ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ gstScldmaInfo.bDMAOnOff[enClientType] = stCfg->bEn; ++ if(stCfg->bEn) ++ { ++ if(!bSingleMode) ++ { ++ gstScldmaInfo.bDmaflag[enClientType] = E_SCLDMA_FLAG_BLANKING; ++ gstScldmaInfo.bDMAidx[enClientType] = (E_SCLDMA_ACTIVE_BUFFER_SCL|(gstScldmaInfo.bMaxid[enClientType]<<4)); ++ if(enClientType == E_SCLDMA_3_FRM_R || enClientType == E_SCLDMA_3_FRM_W) ++ { ++ gstScldmaInfo.bDMAidx[enClientType] = (E_SCLDMA_ACTIVE_BUFFER_SCL|(0x5<<4)); ++ gstScldmaInfo.bDmaflag[enClientType] = 0; ++ } ++ } ++ else ++ { ++ gstScldmaInfo.bDmaflag[enClientType] &= ~E_SCLDMA_FLAG_DMAFORCEOFF; ++ } ++ } ++ else ++ { ++ gstScldmaInfo.bDmaflag[enClientType] |= E_SCLDMA_FLAG_DMAFORCEOFF; ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if(stCfg->bEn) ++ { ++ _Drv_SCLDMA_SetClkOnOff(enSCLDMA_ID,stCfg->stclk,1); ++ } ++#if ENABLE_RING_DB ++ if(_Is_VsrcDoubleBufferNotOpen() && _Is_VsrcId(enSCLDMA_ID) && DoubleBufferStatus) ++ { ++ gVsrcDBnotOpen = 0; ++ _Drv_SCLDMA_SetDoubleBufferOn(E_SCLDMA_ID_1_W, SCLIRQ_SC1_SNPI_W_ACTIVE, E_SCLDMA_1_IMI_W); ++ } ++#endif ++ return _Drv_SCLDMA_SetDMAOnOff(enSCLDMA_ID,stCfg); ++} ++void _Drv_SCLDMA_GetInQueueCount(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ //printf("[GetInQueueCount] %hhd ,%lx,%lx\n",gstScldmaBufferQueue[enClientType].u8InQueueCount,(long)gstScldmaBufferQueue[enClientType].pstWrite,(long)gstScldmaBufferQueue[enClientType].pstRead); ++ if(_IsQueueWriteLargeRead(enClientType)) ++ { ++ _GetInQueueCountIfLarge(enClientType); ++ } ++ else if (_IsQueueWriteSmallRead(enClientType)) ++ { ++ _GetInQueueCountIfSmall(enClientType); ++ } ++ else if(_Is_SWRingModeBufferFull(enClientType)) ++ { ++ gstScldmaBufferQueue[enClientType].u8InQueueCount = gstScldmaInfo.bMaxid[enClientType]; ++ } ++ else ++ { ++ gstScldmaBufferQueue[enClientType].u8InQueueCount = 0; ++ } ++} ++ ++void Drv_SCLDMA_PeekBufferQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ enClientType = _Drv_SCLDMA_TransToClientType(pCfg->enID ,pCfg->enRWMode); ++ if(_Is_SWRingModeBufferReady(enClientType)) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _Drv_SCLDMA_GetInQueueCount(enClientType); ++ pCfg->pstRead = gstScldmaBufferQueue[enClientType].pstRead; ++ pCfg->u8InQueueCount = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ pCfg->u8AccessId = gstScldmaBufferQueue[enClientType].u8AccessId; ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ //printf("[DRVSCLDMA]%d PEEK W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ //pCfg->pstWriteAlready->u8FrameAddrIdx, pCfg->pstRead->u8FrameAddrIdx,pCfg->u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ pCfg->pstWrite->u8FrameAddrIdx, pCfg->pstRead->u8FrameAddrIdx,pCfg->u8InQueueCount,((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d non-used Buffer Queue\n",enClientType )); ++ } ++} ++void _Drv_SCLDMA_BufferClearQueue(EN_SCLDMA_CLIENT_TYPE enClientType,unsigned char u8idx) ++{ ++ ST_SCLDMA_FRAME_BUFFER_CONFIG *stCfg; ++ unsigned char u8BufferIdx; ++ if(_Is_SWRingModeBufferReady(enClientType)) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ stCfg = gstScldmaBufferQueue[enClientType].pstHead; ++ for(u8BufferIdx = 0; u8BufferIdx<=gstScldmaInfo.bMaxid[enClientType]; u8BufferIdx++) ++ { ++ if(stCfg->u8FrameAddrIdx == u8idx && stCfg->u32FrameAddr != 0) ++ { ++ MsOS_Memset(stCfg,0,SCLDMA_BUFFER_QUEUE_OFFSET); ++ break; ++ } ++ else ++ { ++ stCfg += 1; ++ } ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++} ++ST_SCLDMA_FRAME_BUFFER_CONFIG * _Drv_SCLDMA_MoveBufferQueueReadPoint(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstCfg; ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ pstCfg = gstScldmaBufferQueue[enClientType].pstRead; ++ gstScldmaBufferQueue[enClientType].pstRead = gstScldmaBufferQueue[enClientType].pstRead + 1; ++ if(gstScldmaBufferQueue[enClientType].pstRead >=gstScldmaBufferQueue[enClientType].pstTail) ++ { ++ gstScldmaBufferQueue[enClientType].pstRead = gstScldmaBufferQueue[enClientType].pstHead; ++ } ++ if(_Is_SWRingModeBufferFull(enClientType)) ++ { ++ gstScldmaBufferQueue[enClientType].bFull = 0; ++ } ++ _SetANDGetIdxType(enClientType,(pstCfg->u8FrameAddrIdx<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ return pstCfg; ++} ++void Drv_SCLDMA_BufferDeQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ unsigned char u8count; ++ enClientType = _Drv_SCLDMA_TransToClientType(pCfg->enID ,pCfg->enRWMode); ++ if(_Is_SWRingModeBufferReady(enClientType)) ++ { ++ u8count = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ if(u8count) ++ { ++ pCfg->pstRead = _Drv_SCLDMA_MoveBufferQueueReadPoint(enClientType); ++ } ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _Drv_SCLDMA_GetInQueueCount(enClientType); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ pCfg->pstHead = gstScldmaBufferQueue[enClientType].pstHead; ++ pCfg->pstTail = gstScldmaBufferQueue[enClientType].pstTail; ++ pCfg->pstWrite = gstScldmaBufferQueue[enClientType].pstWrite; ++ pCfg->pstWriteAlready = gstScldmaBufferQueue[enClientType].pstWriteAlready; ++ pCfg->u8InQueueCount = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ //printf("[DRVSCLDMA]%d DeQueue :R_P:%lx R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ // pCfg->pstRead->u32FrameAddr, pCfg->pstRead->u8FrameAddrIdx,gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d DeQueue :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ pCfg->pstWriteAlready->u8FrameAddrIdx,gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx,gstScldmaBufferQueue[enClientType].u8InQueueCount,((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d non-used Buffer Queue\n",enClientType )); ++ } ++} ++void _Drv_SCLDMA_BufferFillQueue(ST_SCLDMA_FRAME_BUFFER_CONFIG *stCfg,const ST_SCLDMA_FRAME_BUFFER_CONFIG *stTarget) ++{ ++ MsOS_Memcpy(stCfg,stTarget,SCLDMA_BUFFER_QUEUE_OFFSET); ++} ++void _Drv_SCLDMA_MoveBufferQueueWritePoint(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ gstScldmaBufferQueue[enClientType].pstWriteAlready = gstScldmaBufferQueue[enClientType].pstWrite; ++ gstScldmaBufferQueue[enClientType].pstWrite += 1; ++ if(gstScldmaBufferQueue[enClientType].pstWrite >=gstScldmaBufferQueue[enClientType].pstTail) ++ { ++ gstScldmaBufferQueue[enClientType].pstWrite = gstScldmaBufferQueue[enClientType].pstHead; ++ } ++ ++ if(gstScldmaBufferQueue[enClientType].pstWrite == gstScldmaBufferQueue[enClientType].pstRead) ++ { ++ gstScldmaBufferQueue[enClientType].bFull = 1; ++ } ++} ++unsigned char Drv_SCLDMA_GetDoneBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ unsigned char u8BufIdx; ++ u8BufIdx = gstScldmaBufferQueue[enClientType].pstWriteAlready->u8FrameAddrIdx; ++ return u8BufIdx; ++} ++unsigned char Drv_SCLDMA_GetNextBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ unsigned char u8BufIdx; ++ u8BufIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ if(u8BufIdx == gstScldmaInfo.bMaxid[enClientType]) ++ { ++ u8BufIdx = 0; ++ } ++ else ++ { ++ u8BufIdx++; ++ } ++ return u8BufIdx; ++} ++unsigned char Drv_SCLDMA_GetActiveBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ unsigned char u8BufIdx; ++ u8BufIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ return u8BufIdx; ++} ++void _Drv_SCLDMA_DisableBufferAccess(EN_SCLDMA_CLIENT_TYPE enClientType,MS_U8 u8FrameAddrIdx) ++{ ++ gstScldmaBufferQueue[enClientType].u8Bufferflag &= ~(0x1<enID ,pCfg->enRWMode); ++ //printf("[DRVSCLDMA]EnableBufferAccess%d :%hhd\n",enClientType,pCfg->u8NextActiveId); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]EnableBufferAccess%d :%hhd\n",enClientType,pCfg->u8AccessId); ++ _Drv_SCLDMA_BufferClearQueue(enClientType,pCfg->u8AccessId); ++ _Drv_SCLDMA_EnableBufferAccess(enClientType,pCfg->u8AccessId); ++} ++MS_BOOL Drv_SCLDMA_MakeSureNextActiveId(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U8 u8BufferIdx; ++ MS_U8 u8FrameAddrIdx; ++ u8FrameAddrIdx = Drv_SCLDMA_GetNextBufferIdx(enClientType); ++ for(u8BufferIdx = 0; u8BufferIdxgstScldmaInfo.bMaxid[enClientType]) ++ { ++ u8FrameAddrIdx = 0; ++ } ++ ++ if(_Is_IdxRingCircuit(enClientType,u8BufferIdx)) ++ { ++ //DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d ChangeBufferIdx Fail\n",enClientType)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA] enClientType:%d ChangeBufferIdx Fail\n",enClientType); ++ } ++ } ++ } ++ return 0; ++} ++void _Drv_SCLDMA_ChangeSC3RBufferOnlyForSC3Mode(EN_SCLDMA_CLIENT_TYPE enClientType,MS_U8 u8FrameAddrIdx) ++{ ++ if(enClientType ==E_SCLDMA_3_FRM_W) ++ { ++ Hal_SCLDMA_SetDMAOutputBufferAddr(E_SCLDMA_3_FRM_R, ++ gstScldmaInfo.u32Base_Y[enClientType][u8FrameAddrIdx], ++ gstScldmaInfo.u32Base_C[enClientType][u8FrameAddrIdx], ++ gstScldmaInfo.u32Base_V[enClientType][u8FrameAddrIdx]); ++ } ++} ++void Drv_SCLDMA_ChangeBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U8 u8FrameAddrIdx; ++ u8FrameAddrIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ Hal_SCLDMA_SetDMAOutputBufferAddr(enClientType, ++ gstScldmaInfo.u32Base_Y[enClientType][u8FrameAddrIdx], ++ gstScldmaInfo.u32Base_C[enClientType][u8FrameAddrIdx], ++ gstScldmaInfo.u32Base_V[enClientType][u8FrameAddrIdx]); ++ _Drv_SCLDMA_ChangeSC3RBufferOnlyForSC3Mode(enClientType,u8FrameAddrIdx); ++ ++} ++unsigned char _Drv_SCLDMA_GetISPCount(void) ++{ ++ return ((gu8ISPcount==0x7F) ? 0 : (gu8ISPcount +1)); ++} ++void Drv_SCLDMA_SetFrameResolution(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ gstScldmaInfo.u16FrameHeight[enClientType] = Hal_SCLDMA_GetOutputVsize(enClientType); ++ gstScldmaInfo.u16FrameWidth[enClientType] = Hal_SCLDMA_GetOutputHsize(enClientType); ++} ++unsigned char Drv_SCLDMA_BufferEnQueue(EN_SCLDMA_CLIENT_TYPE enClientType,ST_SCLDMA_FRAME_BUFFER_CONFIG *stTarget) ++{ ++ if(_Is_SWRingModeBufferReady(enClientType) && _Is_SWRingModeBufferNotFull(enClientType)) ++ { ++ stTarget->u8ISPcount = _Drv_SCLDMA_GetISPCount(); ++ _Drv_SCLDMA_BufferFillQueue(gstScldmaBufferQueue[enClientType].pstWrite,stTarget); ++ _Drv_SCLDMA_MoveBufferQueueWritePoint(enClientType); ++ _Drv_SCLDMA_DisableBufferAccess(enClientType,stTarget->u8FrameAddrIdx); ++ _Drv_SCLDMA_GetInQueueCount(enClientType); ++ ++ //printf("[DRVSCLDMA]%d EnQueue :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ //gstScldmaBufferQueue[enClientType].pstWriteAlready->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d EnQueue :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ gstScldmaBufferQueue[enClientType].pstWriteAlready->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].u8InQueueCount,((MS_U32)MsOS_GetSystemTimeStamp())); ++ return 1; ++ } ++ else if(_Is_SWRingModeBufferFull(enClientType)) ++ { ++ //printf("[DRVSCLDMA]%d EnQueue Fail (FULL) :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ //gstScldmaBufferQueue[enClientType].pstWrite->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ //gstScldmaBufferQueue[enClientType].u8InQueueCount,(MS_U32)MsOS_GetSystemTime()); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%d EnQueue Fail (FULL) :W_P:%hhd R_P:%hhd Count:%hhd@:%lu\n",enClientType, ++ gstScldmaBufferQueue[enClientType].pstWrite->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].pstRead->u8FrameAddrIdx, ++ gstScldmaBufferQueue[enClientType].u8InQueueCount,((MS_U32)MsOS_GetSystemTimeStamp())); ++ return 0; ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] enClientType:%d non-used Buffer Queue\n",enClientType )); ++ return 0; ++ } ++} ++MS_BOOL _Drv_SCLDMA_IsVsrcEventNotBeFatch(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_ID_1_W) ++ { ++ return _Is_SC1EventNotBeFatch(); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_ID_2_W) ++ { ++ return _Is_SC2EventNotBeFatch(); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf("[DRVSCLDMA] error ID:%d\n",enSCLDMA_ID )); ++ return 0; ++ } ++} ++MS_U32 _Drv_SCLDMA_GetEventById(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U32 u32Events; ++ MS_U32 *p32PointToStatic = (enSCLDMA_ID ==E_SCLDMA_ID_1_W) ? &gu32FRMEvents: &gu32SC2FRMEvents; ++ MS_U32 *p32PointToOtherStatic = (enSCLDMA_ID ==E_SCLDMA_ID_1_W) ? &gu32SC2FRMEvents: &gu32FRMEvents; ++ SCLIRQTXEvent enClearEventById = (enSCLDMA_ID ==E_SCLDMA_ID_1_W)? E_SCLIRQ_EVENT_SC1POLL : E_SCLIRQ_EVENT_SC2POLL; ++ SCLIRQTXEvent enRemainEventById = (enSCLDMA_ID ==E_SCLDMA_ID_1_W) ? E_SCLIRQ_EVENT_SC2POLL : E_SCLIRQ_EVENT_SC1POLL; ++ if(_Drv_SCLDMA_IsVsrcEventNotBeFatch(enSCLDMA_ID)) ++ { ++ u32Events = MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_EventID()); ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_EventID(),(u32Events & (E_SCLIRQ_EVENT_ALLPOLL))); ++ DRV_SCLDMA_MUTEX_LOCK(); ++ if(*p32PointToOtherStatic ==0) ++ { ++ *p32PointToOtherStatic = u32Events& (E_SCLIRQ_EVENT_ALLPOLL) ; ++ *p32PointToOtherStatic &= ~enClearEventById; ++ } ++ else ++ { ++ *p32PointToOtherStatic = *p32PointToOtherStatic | (u32Events & (enRemainEventById)); ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ } ++ else ++ { ++ DRV_SCLDMA_MUTEX_LOCK(); ++ u32Events = *p32PointToStatic; ++ *p32PointToStatic = 0; ++ DRV_SCLDMA_MUTEX_UNLOCK(); ++ } ++ return u32Events; ++} ++MS_BOOL _Drv_SCLDMA_GetSC3DoneFlagAndClearSC3Event(MS_U32 u32Events) ++{ ++ MS_BOOL bDone; ++ if((u32Events & E_SCLIRQ_SC3EVENT_DONE) == E_SCLIRQ_SC3EVENT_DONE) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_SC3EVENT_RESTART))) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if(u32Events & E_SCLIRQ_EVENT_RESUME) ++ { ++ bDone = FRM_POLLIN; ++ } ++ else //timeout ++ { ++ bDone = FALSE; ++ } ++ if(bDone) ++ { ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SC3EventID(),(u32Events & E_SCLIRQ_SC3EVENT_POLL)); ++ } ++ return bDone; ++} ++MS_BOOL _Drv_SCLDMA_GetSC2DoneFlag(MS_U32 u32Events) ++{ ++ MS_BOOL bSINGLE_SKIP = 0; ++ MS_BOOL bDone; ++ bSINGLE_SKIP = (u32Events&E_SCLIRQ_EVENT_SC2FRM)? ++ ((_IsFlagType(E_SCLDMA_2_FRM_W,E_SCLDMA_FLAG_DROP)) || !(_IsFlagType(E_SCLDMA_2_FRM_W,E_SCLDMA_FLAG_FRMIN))): ++ (u32Events&E_SCLIRQ_EVENT_SC2FRM2)? ++ ((_IsFlagType(E_SCLDMA_2_FRM2_W,E_SCLDMA_FLAG_DROP)) || !(_IsFlagType(E_SCLDMA_2_FRM2_W,E_SCLDMA_FLAG_FRMIN))) ++ : 0; ++ if((u32Events & (E_SCLIRQ_EVENT_SC2)) && bSINGLE_SKIP) //ISP FIFO FULL ++ { ++ bDone = SINGLE_SKIP; ++ if((!_Is_RingMode(E_SCLDMA_2_FRM_W) && u32Events&E_SCLIRQ_EVENT_SC2FRM)|| ++ (!_Is_RingMode(E_SCLDMA_2_FRM2_W)&& u32Events&E_SCLIRQ_EVENT_SC2FRM2)) ++ { ++ if((u32Events&E_SCLIRQ_EVENT_SC2)==E_SCLIRQ_EVENT_SC2) ++ { ++ bDone = FRM_POLLIN|FRM2_POLLIN; ++ } ++ else if(u32Events&E_SCLIRQ_EVENT_SC2FRM) ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if(u32Events&E_SCLIRQ_EVENT_SC2FRM2) ++ { ++ bDone = FRM2_POLLIN; ++ } ++ } ++ if((u32Events & (E_SCLIRQ_EVENT_FRM2RESTART|E_SCLIRQ_EVENT_SC2RESTART))== ++ (E_SCLIRQ_EVENT_FRM2RESTART|E_SCLIRQ_EVENT_SC2RESTART)) //frmrestart ++ { ++ bDone = FRM_POLLIN|FRM2_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_RESUME))) //frmrestart ++ { ++ bDone = FRM_POLLIN|FRM2_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_FRM2RESTART))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC2RESTART))) //frmrestart ++ { ++ bDone = FRM2_POLLIN; ++ } ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC2))==(E_SCLIRQ_EVENT_SC2)) ++ { ++ bDone = FRM_POLLIN |FRM2_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_FRM2RESTART|E_SCLIRQ_EVENT_SC2RESTART))== ++ (E_SCLIRQ_EVENT_FRM2RESTART|E_SCLIRQ_EVENT_SC2RESTART)) //frmrestart ++ { ++ bDone = FRM_POLLIN|FRM2_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC2FRM))) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC2FRM2))) //frmend ++ { ++ bDone = FRM2_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC2RESTART))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_FRM2RESTART))) //frmrestart ++ { ++ bDone = FRM2_POLLIN; ++ } ++ else if(u32Events & E_SCLIRQ_EVENT_RESUME) ++ { ++ bDone = FRM_POLLIN|FRM2_POLLIN; ++ } ++ else //timeout ++ { ++ bDone = FALSE; ++ } ++ return bDone; ++} ++MS_BOOL _Drv_SCLDMA_GetSC1DoneFlag(MS_U32 u32Events) ++{ ++ MS_BOOL bSINGLE_SKIP = 0; ++ MS_BOOL bDone; ++ bSINGLE_SKIP = (u32Events&E_SCLIRQ_EVENT_SC1SNP)? ++ ((_IsFlagType(E_SCLDMA_1_SNP_W,E_SCLDMA_FLAG_DROP)) || !(_IsFlagType(E_SCLDMA_1_SNP_W,E_SCLDMA_FLAG_FRMIN))): ++ (u32Events&E_SCLIRQ_EVENT_SC1FRM)? ++ ((_IsFlagType(E_SCLDMA_1_FRM_W,E_SCLDMA_FLAG_DROP)) || !(_IsFlagType(E_SCLDMA_1_FRM_W,E_SCLDMA_FLAG_FRMIN))) ++ : 0; ++ if((u32Events & (E_SCLIRQ_EVENT_SC1)) && bSINGLE_SKIP) //ISP FIFO FULL ++ { ++ bDone = SINGLE_SKIP; ++ if((!_Is_RingMode(E_SCLDMA_1_FRM_W) && u32Events&E_SCLIRQ_EVENT_SC1FRM)|| ++ (!_Is_RingMode(E_SCLDMA_1_SNP_W)&& u32Events&E_SCLIRQ_EVENT_SC1SNP)) ++ { ++ if((u32Events&E_SCLIRQ_EVENT_SC1)==E_SCLIRQ_EVENT_SC1) ++ { ++ bDone = FRM_POLLIN|SNP_POLLIN; ++ } ++ else if(u32Events&E_SCLIRQ_EVENT_SC1FRM) ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if(u32Events&E_SCLIRQ_EVENT_SC1FRM) ++ { ++ bDone = SNP_POLLIN; ++ } ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_SNPRESTART))== ++ (E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_SNPRESTART)) //frmrestart ++ { ++ bDone = FRM_POLLIN|SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1RESTART))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SNPRESTART))) //frmrestart ++ { ++ bDone = SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_RESUME))) //frmrestart ++ { ++ bDone = FRM_POLLIN|SNP_POLLIN; ++ } ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1))==(E_SCLIRQ_EVENT_SC1)) ++ { ++ bDone = FRM_POLLIN |SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_SNPRESTART))== ++ (E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_SNPRESTART)) //frmrestart ++ { ++ bDone = FRM_POLLIN|SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1FRM))) //frmend ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1SNP))) //frmend ++ { ++ bDone = SNP_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SC1RESTART))) //frmrestart ++ { ++ bDone = FRM_POLLIN; ++ } ++ else if((u32Events & (E_SCLIRQ_EVENT_SNPRESTART))) //frmrestart ++ { ++ bDone = SNP_POLLIN; ++ } ++ else if(u32Events & E_SCLIRQ_EVENT_RESUME) ++ { ++ bDone = FRM_POLLIN|SNP_POLLIN; ++ } ++ else //timeout ++ { ++ bDone = FALSE; ++ } ++ return bDone; ++} ++MS_BOOL _Drv_SCLDMA_GetReadDoneEvent(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_BOOL bDone; ++ if( _Is_SingleMode(enClientType)) ++ { ++ MS_U16 u16IrqNum; ++ MS_U64 u64Flag, u64Flag_N; ++ ++ u16IrqNum = _Drv_SCLDMA_GetActiveIRQNum(enClientType); ++ ++ Drv_SCLIRQ_Get_Flag(u16IrqNum, &u64Flag); ++ Drv_SCLIRQ_Get_Flag(u16IrqNum+1, &u64Flag_N); ++ if(u64Flag && u64Flag_N ) ++ { ++ bDone = TRUE; ++ } ++ else ++ { ++ bDone = FALSE; ++ } ++ } ++ else if ( _Is_RingMode(enClientType)) ++ { ++ bDone = TRUE; ++ } ++ else if(_Is_SWRingMode(enClientType)) ++ { ++ bDone = TRUE; ++ } ++ else ++ { ++ bDone = FALSE; ++ } ++ return bDone; ++} ++MS_BOOL Drv_SCLDMA_GetDMADoneEvent(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_DONE_CONFIG *pCfg) ++{ ++ MS_BOOL bRet = 1; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ MS_U32 u32Time = 0; ++ MS_U32 u32DiffTime = 0; ++ static MS_U32 u32SC3Polltime = 0; ++ MS_U32 u32Events = 0; ++ MS_U8 u8Count = 0; ++ u32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,pCfg->enRWMode); ++ if(enSCLDMA_ID ==E_SCLDMA_ID_PNL_R || enSCLDMA_ID ==E_SCLDMA_ID_3_R ) ++ { ++ _Drv_SCLDMA_GetReadDoneEvent(enClientType); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA]%s:: Client:%s bDone=%x @:%lu\n", ++ __FUNCTION__, PARSING_SCLDMA_ID(enSCLDMA_ID), pCfg->bDone,u32Time); ++ } ++ else if(enSCLDMA_ID ==E_SCLDMA_ID_3_W ) ++ { ++ u32Events = MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SC3EventID()); ++ pCfg->bDone = _Drv_SCLDMA_GetSC3DoneFlagAndClearSC3Event(u32Events); ++ u32DiffTime = (u32Time>=u32SC3Polltime) ? (u32Time-u32SC3Polltime): u32Time; ++ if(pCfg->bDone) ++ { ++ gu32SendTime[E_SCLDMA_3_FRM_R] = u32Time; ++ gbSendPoll[E_SCLDMA_3_FRM_R] = pCfg->bDone; ++ gu32SendTime[E_SCLDMA_3_FRM_W] = u32Time; ++ gbSendPoll[E_SCLDMA_3_FRM_W] = pCfg->bDone; ++ if(gstScldmaInfo.bDMAOnOff[E_SCLDMA_3_FRM_W]) ++ { ++ SCL_DBGERR("%s Delaly\n",__FUNCTION__); ++ MsOS_DelayTask(20); ++ } ++ } ++ else if(gbSendPoll[E_SCLDMA_3_FRM_W]&0x10 && (u32DiffTime>OMX_VSPL_POLLTIME)) ++ { ++ //poll time out ++ if(gstScldmaInfo.enBuffMode[E_SCLDMA_3_FRM_W]== E_SCLDMA_BUF_MD_SINGLE && gstScldmaInfo.bDMAOnOff[E_SCLDMA_3_FRM_W]) ++ { ++ while(!pCfg->bDone) ++ { ++ _Drv_SCLDMA_SWRegenVSyncTrigger(E_SCLDMA_VS_ID_SC3); ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SC3EventID(),E_SCLIRQ_SC3EVENT_DONE, &u32Events, E_OR, 50); ++ pCfg->bDone = _Drv_SCLDMA_GetSC3DoneFlagAndClearSC3Event(u32Events); ++ u8Count++; ++ if(u8Count > 5) ++ { ++ SCL_DBGERR("[SCLDMA]SC3 ERR\n"); ++ break; ++ } ++ } ++ if(pCfg->bDone) ++ { ++ gu32SendTime[E_SCLDMA_3_FRM_R] = u32Time; ++ gbSendPoll[E_SCLDMA_3_FRM_R] = pCfg->bDone; ++ gu32SendTime[E_SCLDMA_3_FRM_W] = u32Time; ++ gbSendPoll[E_SCLDMA_3_FRM_W] = pCfg->bDone; ++ } ++ } ++ } ++ else ++ { ++ if(!(gbSendPoll[E_SCLDMA_3_FRM_W]&0x10)) ++ { ++ u32SC3Polltime = u32Time; ++ } ++ gbSendPoll[E_SCLDMA_3_FRM_R] |= 0x10; ++ gbSendPoll[E_SCLDMA_3_FRM_W] |= 0x10; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,0), ++ "[DRVSCLDMA]%s:: Client:%s Event:%lx bDone=%x flag:%hhx@:%lu\n", ++ __FUNCTION__, PARSING_SCLDMA_CLIENT(enClientType),u32Events, pCfg->bDone, ++ gstScldmaInfo.bDmaflag[enClientType],u32Time); ++ } ++ else ++ { ++ if(enSCLDMA_ID ==E_SCLDMA_ID_1_W) ++ { ++ u32Events = _Drv_SCLDMA_GetEventById(E_SCLDMA_ID_1_W); ++ pCfg->bDone = _Drv_SCLDMA_GetSC1DoneFlag(u32Events); ++ gu32FRMEvents = 0; ++ if(pCfg->bDone) ++ { ++ if((pCfg->bDone&(SNP_POLLIN))||pCfg->bDone==SINGLE_SKIP) ++ { ++ gu32SendTime[E_SCLDMA_1_SNP_W] = u32Time; ++ gbSendPoll[E_SCLDMA_1_SNP_W] = pCfg->bDone; ++ } ++ if((pCfg->bDone&(FRM_POLLIN))||pCfg->bDone==SINGLE_SKIP) ++ { ++ gu32SendTime[E_SCLDMA_1_FRM_W] = u32Time; ++ gbSendPoll[E_SCLDMA_1_FRM_W] = pCfg->bDone; ++ } ++ } ++ else ++ { ++ gbSendPoll[E_SCLDMA_1_SNP_W] |= 0x10; ++ gbSendPoll[E_SCLDMA_1_FRM_W] |= 0x10; ++ } ++ } ++ else if(enSCLDMA_ID ==E_SCLDMA_ID_2_W) ++ { ++ u32Events = _Drv_SCLDMA_GetEventById(E_SCLDMA_ID_2_W); ++ pCfg->bDone = _Drv_SCLDMA_GetSC2DoneFlag(u32Events); ++ gu32SC2FRMEvents = 0; ++ if(pCfg->bDone) ++ { ++ if((pCfg->bDone&(FRM2_POLLIN))||pCfg->bDone==SINGLE_SKIP) ++ { ++ gu32SendTime[E_SCLDMA_2_FRM2_W] = u32Time; ++ gbSendPoll[E_SCLDMA_2_FRM2_W] = pCfg->bDone; ++ } ++ if((pCfg->bDone&(FRM_POLLIN))||pCfg->bDone==SINGLE_SKIP) ++ { ++ gu32SendTime[E_SCLDMA_2_FRM_W] = u32Time; ++ gbSendPoll[E_SCLDMA_2_FRM_W] = pCfg->bDone; ++ } ++ } ++ else ++ { ++ gbSendPoll[E_SCLDMA_2_FRM2_W] |= 0x10; ++ gbSendPoll[E_SCLDMA_2_FRM_W] |= 0x10; ++ } ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1),"[DRVSCLDMA]%s:: Client:%s Event:%lx bDone=%x\n", ++ __FUNCTION__, PARSING_SCLDMA_CLIENT(enClientType),u32Events, pCfg->bDone); ++ } ++ return bRet; ++} ++MS_BOOL _Drv_SCLDMA_GetLastTimePoint(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U8 u8LPoint = 0; ++ u8LPoint = _GetIdxType(enClientType,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ return u8LPoint; ++} ++MS_BOOL _Drv_SCLDMA_GetDMAWritePoint(EN_SCLDMA_CLIENT_TYPE enClientType, MS_U8 u8LPoint) ++{ ++ MS_U8 u8WPoint = 0; ++ if(_Is_DMAClientOn(enClientType) &&_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING)) ++ { ++ u8WPoint = 0x0F; ++ } ++ else if( _IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ u8WPoint =(u8LPoint==0) ? gstScldmaInfo.bMaxid[enClientType] : u8LPoint-1; ++ } ++ else ++ { ++ u8WPoint = u8LPoint; ++ } ++ return u8WPoint; ++} ++MS_BOOL _Drv_SCLDMA_GetAppReadPoint(EN_SCLDMA_CLIENT_TYPE enClientType ,MS_U8 u8AppInfo) ++{ ++ MS_U8 u8RPoint = 0; ++ if(_Is_DMAClientOn(enClientType) &&(_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING))) ++ { ++ u8RPoint = gstScldmaInfo.bMaxid[enClientType]; ++ } ++ else ++ { ++ u8RPoint = (u8AppInfo & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG) ? ++ (u8AppInfo &0x0F ) : (gstScldmaInfo.bDMAidx[enClientType]>>4)&E_SCLDMA_ACTIVE_BUFFER_SCL ; ++ if((u8AppInfo & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(enClientType,1), ++ "[DRVSCLDMA] enClientType:%d Update Rp %hhd \n",enClientType,u8RPoint); ++ } ++ } ++ return u8RPoint; ++} ++void _Drv_SCLDMA_DMAOffAtActiveTimeWhetherNeedReOpen(ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ if(stPointCfg->bRWequal&&(_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_DMAOFF))) ++ { ++ if(Drv_SCLDMA_SetISRHandlerDMAOff(stPointCfg->enClientType,1)) ++ { ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _ReSetFlagType(stPointCfg->enClientType,(E_SCLDMA_FLAG_EVERDMAON|E_SCLDMA_FLAG_DMAOFF)); ++ _ResetTrigCount(stPointCfg->enClientType); ++ Drv_SCLDMA_SetSWReTrigCount(stPointCfg->enClientType,0); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ SCL_DBG(SCL_DBG_LV_DRVSCLDMA()&Get_DBGMG_SCLDMAclient(stPointCfg->enClientType,1), ++ "[DRVSCLDMA] enClientType:%d ReOpen \n",stPointCfg->enClientType); ++ } ++ else ++ { ++ DRV_SCLDMA_ERR(printf( ++ "[DRVSCLDMA] enClientType:%d strong collisionR:%hhd\n",stPointCfg->enClientType,stPointCfg->u8RPoint )); ++ } ++ } ++} ++void _Drv_SCLDMA_SetDMAOnWhenDMAOff ++ (EN_SCLDMA_ID_TYPE enSCLDMA_ID, EN_SCLDMA_CLIENT_TYPE enClientType, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ SCLIRQTXEvent enType; ++ pCfg->stOnOff.bEn = 1; ++ enType = (enClientType==E_SCLDMA_1_FRM_W) ? E_SCLIRQ_EVENT_SC1RESTART : ++ (enClientType==E_SCLDMA_1_SNP_W) ? E_SCLIRQ_EVENT_SNPRESTART : ++ (enClientType==E_SCLDMA_2_FRM_W) ? E_SCLIRQ_EVENT_SC2RESTART : ++ (enClientType==E_SCLDMA_2_FRM2_W) ? E_SCLIRQ_EVENT_FRM2RESTART : ++ E_SCLIRQ_EVENT_CLEAR; ++ Drv_SCLDMA_SetDMAClientOnOff(enSCLDMA_ID ,&pCfg->stOnOff); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_EventID(), enType); ++} ++MS_U8 _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOff(ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ MS_U8 u8ActiveBuffer; ++ if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && !stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL | E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ } ++ else if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint|E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _ReSetFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG; ++ } ++ return u8ActiveBuffer; ++} ++MS_U8 _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOn(ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ MS_U8 u8ActiveBuffer; ++ if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && !stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint | E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL; ++ } ++ else if((_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON)) && stPointCfg->bRPointChange) ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint; ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _ReSetFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_EVERDMAON); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ else ++ { ++ u8ActiveBuffer = stPointCfg->u8WPoint; ++ } ++ return u8ActiveBuffer; ++} ++void _Drv_SCLDMA_GetPointConfig(EN_SCLDMA_CLIENT_TYPE enClientType ,MS_U8 u8AppInfo,ST_SCLDMA_POINT_CONFIG *stPointCfg) ++{ ++ stPointCfg->u8LPoint = _Drv_SCLDMA_GetLastTimePoint(enClientType); ++ stPointCfg->u8WPoint = _Drv_SCLDMA_GetDMAWritePoint(enClientType, stPointCfg->u8LPoint); ++ stPointCfg->u8RPoint = _Drv_SCLDMA_GetAppReadPoint(enClientType,u8AppInfo); ++ stPointCfg->bRWequal = (stPointCfg->u8WPoint == stPointCfg->u8RPoint)? 1 : 0; ++ stPointCfg->bRPointChange = (u8AppInfo & E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG)? 1 : 0; ++ stPointCfg->enClientType = enClientType; ++} ++void _Drv_SCLDMA_HandlerBufferWhenDMAOff ++ (EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_POINT_CONFIG *stPointCfg, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ if(_Is_DMACanReOpen(stPointCfg->bRWequal,stPointCfg->bRPointChange) && ++ !(_IsFlagType(stPointCfg->enClientType,E_SCLDMA_FLAG_DMAFORCEOFF)))// for issue race condition of OMX update Rp and ioctl. ++ { ++ _Drv_SCLDMA_SetDMAOnWhenDMAOff(enSCLDMA_ID,stPointCfg->enClientType,pCfg); ++ pCfg->u8ActiveBuffer = 0x0F ; ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOff(stPointCfg); ++ } ++} ++void _Drv_SCLDMA_HandlerBufferWhenDMAOn ++ (ST_SCLDMA_POINT_CONFIG *stPointCfg, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ _Drv_SCLDMA_DMAOffAtActiveTimeWhetherNeedReOpen(stPointCfg); ++ pCfg->u8ActiveBuffer = _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOn(stPointCfg); ++} ++MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdx(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ ST_SCLDMA_POINT_CONFIG stPointCfg; ++ MsOS_Memset(&stPointCfg,0,sizeof(ST_SCLDMA_POINT_CONFIG)); ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,pCfg->enRWMode); ++#if ENABLE_RING_DB ++ if(_Is_VsrcDoubleBufferNotOpen() && _Is_VsrcId(enSCLDMA_ID) && DoubleBufferStatus) ++ { ++ gVsrcDBnotOpen = 0; ++ _Drv_SCLDMA_SetDoubleBufferOn(E_SCLDMA_ID_1_W, SCLIRQ_SC1_SNPI_W_ACTIVE, E_SCLDMA_1_IMI_W); ++ } ++#endif ++ if(_Is_RingMode(enClientType)) ++ { ++ _Drv_SCLDMA_GetPointConfig(enClientType,pCfg->u8ActiveBuffer,&stPointCfg); ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetIdxType(enClientType,(stPointCfg.u8RPoint<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if(_Is_DMAClientOn(enClientType)) ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOn(&stPointCfg,pCfg); ++ } ++ else ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOff(enSCLDMA_ID,&stPointCfg,pCfg); ++ } ++ if(pCfg->u8ActiveBuffer == 0xF) ++ { ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][MAX_BUFFER_COUNT]; ++ } ++ else ++ { ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][stPointCfg.u8WPoint]; ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ gu64FRMDoneTime[enClientType][MAX_BUFFER_COUNT] = pCfg->u64FRMDoneTime; ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ } ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = 0xFF; ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][0]; ++ } ++ pCfg->u8ISPcount = gu8ISPcount; ++ return 1; ++} ++void _Drv_SCLDMA_HandlerBufferWhenDMAOnWithoutDoublebuffer ++ (ST_SCLDMA_POINT_CONFIG *stPointCfg, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ pCfg->u8ActiveBuffer = _Drv_SCLDMA_GetDoneIdxAndFlagWhenDMAOn(stPointCfg); ++} ++MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdxWithoutDoublebuffer ++ (EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ ST_SCLDMA_POINT_CONFIG stPointCfg; ++ MsOS_Memset(&stPointCfg,0,sizeof(ST_SCLDMA_POINT_CONFIG)); ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,pCfg->enRWMode); ++ if(_Is_RingMode(enClientType)) ++ { ++ _Drv_SCLDMA_GetPointConfig(enClientType,pCfg->u8ActiveBuffer,&stPointCfg); ++ DRV_SCLDMA_MUTEX_LOCK_ISR(); ++ _SetANDGetIdxType(enClientType,(stPointCfg.u8RPoint<<4),E_SCLDMA_ACTIVE_BUFFER_SCL); ++ if(stPointCfg.u8WPoint == 0xF) ++ { ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][MAX_BUFFER_COUNT]; ++ } ++ else ++ { ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][stPointCfg.u8WPoint]; ++ gu64FRMDoneTime[enClientType][MAX_BUFFER_COUNT] = pCfg->u64FRMDoneTime; ++ } ++ DRV_SCLDMA_MUTEX_UNLOCK_ISR(); ++ if(_Is_DMAClientOn(enClientType)) ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOnWithoutDoublebuffer(&stPointCfg,pCfg); ++ } ++ else ++ { ++ _Drv_SCLDMA_HandlerBufferWhenDMAOff(enSCLDMA_ID,&stPointCfg,pCfg); ++ } ++ } ++ else if(_Is_SingleMode(enClientType)) ++ { ++ if(_IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ pCfg->u8ActiveBuffer = 0xFF; ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = (0xFF | ~E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG); ++ } ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][0]; ++ } ++ else ++ { ++ pCfg->u8ActiveBuffer = 0xFF; ++ pCfg->u64FRMDoneTime = gu64FRMDoneTime[enClientType][0]; ++ } ++ pCfg->u8ISPcount = gu8ISPcount; ++ return 1; ++} ++void Drv_SCLDMA_SetForceCloseDMA(EN_SCLDMA_ID_TYPE enID,EN_SCLDMA_RW_MODE_TYPE enRWMode,MS_BOOL bEn) ++{ ++ EN_SCLDMA_CLIENT_TYPE client; ++ client = _Drv_SCLDMA_TransToClientType(enID ,enRWMode); ++ gbForceClose[client] = bEn; ++} ++ ++void Drv_SCLDMA_ResetTrigCountByClient(EN_SCLDMA_ID_TYPE enSCLDMA_ID,EN_SCLDMA_RW_MODE_TYPE enRWMode) ++{ ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++ MS_U8 u8ClientIdx; ++ enClientType = _Drv_SCLDMA_TransToClientType(enSCLDMA_ID ,enRWMode); ++ if(enClientType == E_SCLDMA_CLIENT_NUM) ++ { ++ for(u8ClientIdx=0; u8ClientIdxu16DMAcount = Hal_SCLDMA_GetDMAOutputCount(enClientType); ++ stAttr->u16DMAH = Hal_SCLDMA_GetOutputHsize(enClientType); ++ stAttr->u16DMAV = Hal_SCLDMA_GetOutputVsize(enClientType); ++ stAttr->u32Trigcount = gu32TrigCount[enClientType]; ++ stAttr->enBuffMode = gstScldmaInfo.enBuffMode[enClientType]; ++ stAttr->enColor = gstScldmaInfo.enColor[enClientType]; ++ stAttr->u8MaxIdx = gstScldmaInfo.bMaxid[enClientType]; ++ for(u8BufferIdx=0;u8BufferIdx<=stAttr->u8MaxIdx;u8BufferIdx++) ++ { ++ stAttr->u32Base_Y[u8BufferIdx] = gstScldmaInfo.u32Base_Y[enClientType][u8BufferIdx]; ++ stAttr->u32Base_C[u8BufferIdx] = gstScldmaInfo.u32Base_C[enClientType][u8BufferIdx]; ++ stAttr->u32Base_V[u8BufferIdx] = gstScldmaInfo.u32Base_V[enClientType][u8BufferIdx]; ++ } ++ stAttr->bDMAEn = gstScldmaInfo.bDMAOnOff[enClientType]; ++ if(stAttr->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ stAttr->bDMAReadIdx = (gstScldmaInfo.bDMAidx[enClientType]>>4)&E_SCLDMA_ACTIVE_BUFFER_SCL; ++ stAttr->bDMAWriteIdx = gstScldmaInfo.bDMAidx[enClientType]&E_SCLDMA_ACTIVE_BUFFER_SCL; ++ if(stAttr->bDMAReadIdx>stAttr->bDMAWriteIdx) ++ { ++ stAttr->u8Count = (stAttr->u8MaxIdx+1)-(stAttr->bDMAReadIdx-stAttr->bDMAWriteIdx); ++ } ++ else ++ { ++ stAttr->u8Count = (stAttr->u8MaxIdx+1)-(stAttr->bDMAWriteIdx-stAttr->bDMAReadIdx); ++ } ++ } ++ else ++ { ++ stAttr->bDMAReadIdx = gstScldmaBufferQueue[enClientType].u8AccessId; ++ stAttr->bDMAWriteIdx = gstScldmaBufferQueue[enClientType].u8NextActiveId; ++ stAttr->u8Count = gstScldmaBufferQueue[enClientType].u8InQueueCount; ++ } ++ stAttr->bDMAFlag = gstScldmaInfo.bDmaflag[enClientType]; ++ stAttr->bSendPoll = gbSendPoll[enClientType]; ++ u8LP = (_GetIdxType(enClientType,E_SCLDMA_ACTIVE_BUFFER_SCL)); ++ if( _IsFlagType(enClientType,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ u8WP =(u8LP==0) ? gstScldmaInfo.bMaxid[enClientType] : u8LP-1; ++ } ++ else if(_Is_DMAClientOn(enClientType) &&_IsFlagType(enClientType,E_SCLDMA_FLAG_BLANKING)) ++ { ++ u8WP = MAX_BUFFER_COUNT; ++ } ++ else ++ { ++ u8WP = u8LP; ++ } ++ if(stAttr->enBuffMode == E_SCLDMA_BUF_MD_SINGLE) ++ { ++ stAttr->u32FrameDoneTime = (MS_U32)gu64FRMDoneTime[enClientType][0]; ++ } ++ else ++ { ++ stAttr->u32FrameDoneTime = (MS_U32)gu64FRMDoneTime[enClientType][u8WP]; ++ } ++ stAttr->u32SendTime = gu32SendTime[enClientType]; ++ stAttr->u8ResetCount = gu8ResetCount[enClientType]; ++ stAttr->u8DMAErrCount = gu8DMAErrCount[enClientType]; ++} ++void Drv_SCLDMA_ClkClose(ST_SCLDMA_CLK_CONFIG* stclk) ++{ ++ if(!gbclkforcemode) ++ { ++ Hal_SCLDMA_CLKInit(0,stclk); ++ Hal_SCLDMA_SC3CLKInit(0,stclk); ++ Hal_SCLDMA_ODCLKInit(0,stclk); ++ } ++} ++void * Drv_SCLDMA_GetWaitQueueHead(EN_SCLDMA_ID_TYPE enID) ++{ ++ return Drv_SCLIRQ_GetWaitQueueHead(enID); ++} ++ ++#undef DRV_SCLDMA_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma.h +new file mode 100644 +index 00000000..72e03382 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma.h +@@ -0,0 +1,157 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef DRV_SCLDMA_H ++#define DRV_SCLDMA_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_SCLDMA_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void isp_enable_input(u32 enable); ++INTERFACE MS_BOOL Drv_SCLDMA_Init(ST_SCLDMA_INIT_CONFIG *pInitCfg); ++INTERFACE void Drv_SCLDMA_Exit(unsigned char bCloseISR); ++INTERFACE MS_BOOL Drv_SCLDMA_SetDMAClientConfig(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_RW_CONFIG *stCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_SetDMAClientOnOff(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ONOFF_CONFIG *stCfg ); ++INTERFACE EN_SCLDMA_DB_STATUS_TYPE Drv_SCLDMA_GetVsrcDoubleBufferStatus(MS_U32 u32Event); ++INTERFACE void Drv_SCLDMA_DoubleBufferOnOffById(MS_BOOL bEn, EN_SCLDMA_ID_TYPE enSCLDMA_ID); ++INTERFACE MS_BOOL Drv_SCLDMA_Set_VsConfig(EN_SCLDMA_VS_ID_TYPE enVsID, ST_SCLDMA_VS_CONFIG stCfg); ++INTERFACE void Drv_SCLDMA_Release(EN_SCLDMA_ID_TYPE enSCLDMA_ID,ST_SCLDMA_CLK_CONFIG *stclk); ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMADoneEvent(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_DONE_CONFIG *pCfg); ++INTERFACE void Drv_SCLDMA_PeekBufferQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg); ++INTERFACE void Drv_SCLDMA_BufferDeQueue(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pstCfg); ++INTERFACE unsigned char Drv_SCLDMA_GetActiveBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE unsigned char Drv_SCLDMA_GetDoneBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE unsigned char Drv_SCLDMA_GetNextBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE void Drv_SCLDMA_SetFrameResolution(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE unsigned char Drv_SCLDMA_BufferEnQueue(EN_SCLDMA_CLIENT_TYPE enClientType,ST_SCLDMA_FRAME_BUFFER_CONFIG *stTarget); ++INTERFACE void Drv_SCLDMA_ChangeBufferIdx(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE MS_BOOL Drv_SCLDMA_MakeSureNextActiveId(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE void Drv_SCLDMA_EnableBufferAccess(ST_SCLDMA_BUFFER_QUEUE_CONFIG *pCfg); ++ ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMABufferActiveIdx(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdx(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_GetDMABufferDoneIdxWithoutDoublebuffer(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_ACTIVE_BUFFER_CONFIG *pCfg); ++INTERFACE void Drv_SCLDMA_SetThreadOnOffFlag(MS_BOOL bEn,ST_SCLDMA_THREAD_CONFIG *stthcfg); ++INTERFACE void Drv_SCLDMA_GetDMAInformationByClient(EN_SCLDMA_ID_TYPE enSCLDMA_ID,EN_SCLDMA_RW_MODE_TYPE enRWMode,ST_SCLDMA_ATTR_TYPE *stAttr); ++INTERFACE MS_BOOL Drv_SCLDMA_SetISRHandlerDMAOff(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_ResetTrigCountByClient(EN_SCLDMA_ID_TYPE enSCLDMA_ID,EN_SCLDMA_RW_MODE_TYPE enRWMode); ++INTERFACE void Drv_SCLDMA_SetForceCloseDMA(EN_SCLDMA_ID_TYPE enID,EN_SCLDMA_RW_MODE_TYPE enRWMode,MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_Sys_Init(MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_ClkClose(ST_SCLDMA_CLK_CONFIG* stclk); ++INTERFACE MS_BOOL Drv_SCLDMA_Resume(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLDMA_Suspend(EN_SCLDMA_ID_TYPE enSCLDMA_ID, ST_SCLDMA_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE void * Drv_SCLDMA_GetWaitQueueHead(EN_SCLDMA_ID_TYPE enID); ++INTERFACE MS_S32* Drv_SCLDMA_GetDMAandIRQCommonMutex(void); ++INTERFACE void Drv_SCLDMA_SetISPFrameCount(void); ++INTERFACE void Drv_SCLDMA_SetSclFrameDoneTime(EN_SCLDMA_CLIENT_TYPE enClientType,MS_U64 u64FRMDoneTime); ++INTERFACE MS_U64 Drv_SCLDMA_GetSclFrameDoneTime(EN_SCLDMA_CLIENT_TYPE enClientType, MS_U8 u8Count); ++INTERFACE void Drv_SCLDMA_SetSWReTrigCount(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn); ++INTERFACE void Drv_SCLDMA_SetDMAIgnoreCount(EN_SCLDMA_CLIENT_TYPE enClientType,MS_BOOL bEn); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma_st.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma_st.h +new file mode 100644 +index 00000000..132e8f3a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/scldma/drvscldma_st.h +@@ -0,0 +1,472 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef DRV_SCLDMA_ST_H ++#define DRV_SCLDMA_ST_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// DEFINE ++//------------------------------------------------------------------------------------------------- ++#define SCLTASKHANDLERMAX 5 ++#define SCLTASKIDMAX 2 ++#define SCLDMA_DBG_Thread 0 ++#define DoubleBufferDefaultSet 0 // 0 close 1 open ++#define DoubleBufferStatus gbDBStatus ++#define ENABLE_RING_DB 1 ++#define SCLDMA_IRQ_EN 0 ++#define ENABLE_ACTIVEID_ISR 1 ++#define SCLDMA_BUFFER_QUEUE_OFFSET sizeof(ST_SCLDMA_FRAME_BUFFER_CONFIG) ++#define SCLDMA_IRQ_EVENT_ID_MSK 0xFF000000 ++#define SCLDMA_IRQ_EVENT_CLIENT_MSK 0x000000FF ++#define SCLDMA_IRQ_EVENT_CLEAR_IRQNUM_MSK 0x0000FF00 ++#define SCLDMA_IRQ_EVENT_CLEAR_MODE_MSK 0x00FF0000 ++ ++#define GET_SCLDMA_IRQ_EVENT_CLIENT(x) (x & SCLDMA_IRQ_EVENT_CLIENT_MSK) ++#define GET_SCLDMA_IRQ_EVENT_CLEAR_IRQNUM(x) ((x & SCLDMA_IRQ_EVENT_CLEAR_IRQNUM_MSK) >> 8) ++#define GET_SCLDMA_IRQ_EVENT_CLEAR_MODE(x) ((x & SCLDMA_IRQ_EVENT_CLEAR_MODE_MSK) >> 16) ++ ++#define SET_SCLDMA_IRQ_EVENT_PENDING(client) (E_SCLDMA_IRQ_EVENT_PENDING | \ ++ (client & 0x000000FF)) ++ ++#define SET_SCLDMA_IRQ_EVENT_CLEAR(client, mode, irqnum) (E_SCLDMA_IRQ_EVENT_CLEAR | \ ++ (client & 0xFF) | \ ++ ((irqnum & 0xFF) << 8) | \ ++ ((mode & 0xFF)<<16)) ++#define MAX_BUFFER_COUNT 4 ++//------------------------------------------------------------------------------------------------- ++// ENUM ++//------------------------------------------------------------------------------------------------- ++ ++typedef enum ++{ ++ E_SCLDMA_ID_1_W, ++ E_SCLDMA_ID_2_W, ++ E_SCLDMA_ID_3_W, ++ E_SCLDMA_ID_3_R, ++ E_SCLDMA_ID_PNL_R, ++ E_SCLDMA_ID_MAX, //scldma ID type,I1 has 1_W,2_W,3_R,3_R,PNL_R ++}EN_SCLDMA_ID_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_FRM_W, ++ E_SCLDMA_SNP_W, ++ E_SCLDMA_IMI_W, ++ E_SCLDMA_FRM_R, ++ E_SCLDMA_DBG_R, ++ E_SCLDMA_IMI_R, ++ E_SCLDMA_FRM2_W, ++ E_SCLDMA_RW_NUM, //scldma rwmode, I1 has FRM,SNP,IMI RW ++}EN_SCLDMA_RW_MODE_TYPE; ++ ++typedef enum ++{ ++ EN_SCLDMA_DB_STATUS_NEED_OFF, ++ EN_SCLDMA_DB_STATUS_NEED_ON, ++ EN_SCLDMA_DB_STATUS_KEEP, ++ EN_SCLDMA_DB_STATUS_NUM, //double buffer switcher status, 3 choise ++}EN_SCLDMA_DB_STATUS_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_1_FRM_W = 0, ++ E_SCLDMA_1_SNP_W = 1, ++ E_SCLDMA_2_FRM_W = 2, ++ E_SCLDMA_2_FRM2_W = 3, ++ E_SCLDMA_1_IMI_W = 4, ++ E_SCLDMA_2_IMI_W = 5, ++ E_SCLDMA_3_FRM_R = 6, ++ E_SCLDMA_3_FRM_W = 7, ++ E_SCLDMA_4_FRM_R = 8, ++ E_SCLDMA_3_IMI_R = 9, ++ E_SCLDMA_CLIENT_NUM, //scldma client ,I1 has dma_1:3 cli dma_2 :2cli dma_3:In/Out debug:pnl &dma_3_IMIR ++}EN_SCLDMA_CLIENT_TYPE; ++ ++ ++typedef enum ++{ ++ E_SCLDMA_BUF_MD_RING, ++ E_SCLDMA_BUF_MD_SINGLE, ++ E_SCLDMA_BUF_MD_SWRING, ++ E_SCLDMA_BUF_MD_NUM, //scldma DMA write mode,I1 has 2 type: Ring(HW),Single(HW+SW) ++}EN_SCLDMA_BUFFER_MODE_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_COLOR_YUV422, ///< color format: 422Pack ++ E_SCLDMA_COLOR_YUV420, ///< color format: YCSep420 ++ E_SCLDMA_COLOR_YCSep422, ///< color format: YC422 ++ E_SCLDMA_COLOR_YUVSep422, ///< color format: YUVSep422 ++ E_SCLDMA_COLOR_YUVSep420, ///< color format: YUVSep420 ++ E_SCLDMA_COLOR_NUM, //I3 dma has 5 color type 422,420 ++}EN_SCLDMA_COLOR_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_VS_ID_SC = 0, ++ E_SCLDMA_VS_ID_AFF = 1, ++ E_SCLDMA_VS_ID_LDC = 2, ++ E_SCLDMA_VS_ID_SC3 = 3, ++ E_SCLDMA_VS_ID_DISP = 4, ++ E_SCLDMA_VS_ID_NUM = 5, //scl handle vsync type,I1 can handle in AFF,LDC,SC3,DISP, suggest sc1 use HW mode ,sc3 use regen mode ++}EN_SCLDMA_VS_ID_TYPE; ++ ++ ++ ++typedef enum ++{ ++ E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC = 0, ++ E_SCLDMA_VS_TRIG_MODE_HW_DELAY = 1, ++ E_SCLDMA_VS_TRIG_MODE_SWTRIGGER = 2, ++ E_SCLDMA_VS_TRIG_MODE_DISP_FM_END = 3, ++ E_SCLDMA_VS_TRIG_MODE_NUM = 4, ++}EN_SCLDMA_VS_TRIG_MODE_TYPE; ++ ++ ++typedef enum ++{ ++ E_SCLDMA_REF_VS_REF_MODE_FALLING = 0, ++ E_SCLDMA_REF_VS_REF_MODE_RASING = 1, ++ E_SCLDMA_REF_VS_REF_MODE_NUM = 2, ++}EN_SCLDMA_REGEN_VS_REF_MODE_TYPE; ++ ++ ++typedef enum ++{ ++ E_SCLDMA_IRQ_EVENT_TIMER = 0x01000000, ++ E_SCLDMA_IRQ_EVENT_PENDING = 0x02000000, ++ E_SCLDMA_IRQ_EVENT_CLEAR = 0x03000000, ++ E_SCLDMA_IRQ_EVENT_ALL = 0x0FFFFFFF, ++}EN_SCLDMA_IRQ_EVENT_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_IRQ_MODE_PENDING = 0x00, ++ E_SCLDMA_IRQ_MODE_ACTIVE = 0x01, ++ E_SCLDMA_IRQ_MODE_ACTIVE_N = 0x02, ++ E_SCLDMA_IRQ_MODE_SIDONE = 0x03, ++ E_SCLDMA_IRQ_MODE_END = 0x04, ++ E_SCLDMA_IRQ_MODE_DONE = 0x06, ++ E_SCLDMA_IRQ_MODE_ALL = 0x07, ++}EN_SCLDMA_IRQ_MODE_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_ACTIVE_BUFFER_OMX = 0xF0, // OMX buffer status ,driver reserve. ++ E_SCLDMA_ACTIVE_BUFFER_SCL = 0x03, // SCL buffer status, save active/done buffer idx ++ E_SCLDMA_ACTIVE_BUFFER_OFF = 0x04, // already not use ++ E_SCLDMA_ACTIVE_BUFFER_ACT = 0x08, // already not use ++ E_SCLDMA_ACTIVE_BUFFER_SCLANDFLAG = 0x0F, // like E_SCLDMA_ACTIVE_BUFFER_SCL ++ E_SCLDMA_ACTIVE_BUFFER_OMX_FLAG = 0x10, // it's represent OMX is update empty buffer to buffer ++ E_SCLDMA_ACTIVE_BUFFER_OMX_TRIG = 0x20, // it's represent dma turn off and driver update to OMX ++ E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL = 0x40, // it's represent dma already done one buffer, but OMX isn't to receive. ++}EN_SCLDMA_ACTIVE_BUFFER_TYPE; ++ ++//bit0 next time off , bit 1 blanking ,bit 2 DMAonoff, bit3 no DMA on ,bit4 ever DMA on ,but already off or open again ++typedef enum ++{ ++ E_SCLDMA_FLAG_NEXT_ON = 0x01, // for non double buffer mode, if active wait for blanking ++ E_SCLDMA_FLAG_BLANKING = 0x02, // if reset dma,active id is temporarily state, need to handle until first frame done. ++ E_SCLDMA_FLAG_DMAOFF = 0x04, // ref E_SCLDMA_ACTIVE_BUFFER_OFF,dma off ++ E_SCLDMA_FLAG_ACTIVE = 0x08, // ref E_SCLDMA_ACTIVE_BUFFER_ACT,dma act ++ E_SCLDMA_FLAG_EVERDMAON = 0x10, // like E_SCLDMA_ACTIVE_BUFFER_OMX_RINGFULL ++ E_SCLDMA_FLAG_FRMIN = 0x20, // this frame is integrate. ++ E_SCLDMA_FLAG_FRMDONE = 0x40, // dma done.(idle) ++ E_SCLDMA_FLAG_FRMIGNORE = 0x80, // dma done but ignore. ++ E_SCLDMA_FLAG_DROP = 0x100, // set drop this frame ++ E_SCLDMA_FLAG_NEXT_OFF = 0x200, // for non double buffer mode, if active wait for blanking ++ E_SCLDMA_FLAG_DMAFORCEOFF = 0x400, // ref E_SCLDMA_ACTIVE_BUFFER_OFF,dma off ++}EN_SCLDMA_FLAG_TYPE; ++ ++typedef enum ++{ ++ E_SCLDMA_ISR_LOG_ISPOFF = 0x1, ++ E_SCLDMA_ISR_LOG_SNPONLY = 0x2, ++ E_SCLDMA_ISR_LOG_SNPISR = 0x3, ++ E_SCLDMA_ISR_LOG_ISPON = 0x4, ++ E_SCLDMA_ISR_LOG_SC1ON = 0x5, ++ E_SCLDMA_ISR_LOG_SC1OFF = 0x6, ++ E_SCLDMA_ISR_LOG_SC2ON = 0x7, ++ E_SCLDMA_ISR_LOG_SC2OFF = 0x8, ++ E_SCLDMA_ISR_LOG_SC1A = 0x9, ++ E_SCLDMA_ISR_LOG_SC1N = 0xA, ++ E_SCLDMA_ISR_LOG_SC2A = 0xB, ++ E_SCLDMA_ISR_LOG_SC2N = 0xC, ++ E_SCLDMA_ISR_LOG_FRMEND = 0xD,//isr log status ++}EN_SCLDMA_ISR_LOG_TYPE; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ MS_U8 u8RPoint;//R-OMX ++ MS_U8 u8WPoint;//W-SCL ++ MS_U8 u8LPoint;// L-last time scl ++ MS_BOOL bRWequal; ++ MS_BOOL bRPointChange; ++ EN_SCLDMA_CLIENT_TYPE enClientType; ++}ST_SCLDMA_POINT_CONFIG; ++typedef struct ++{ ++ MS_BOOL flag; ++ MS_S32 s32Taskid[SCLTASKIDMAX]; ++ MS_S32 s32HandlerId[SCLTASKHANDLERMAX]; ++ MSOS_ST_TASKSTRUCT sttask; ++}ST_SCLDMA_THREAD_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32RIUBase; ++}ST_SCLDMA_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32IRQNum; ++}ST_SCLDMA_SUSPEND_RESUME_CONFIG; ++ ++typedef struct ++{ ++ MS_U8 btsBase_0 : 1; ++ MS_U8 btsBase_1 : 1; ++ MS_U8 btsBase_2 : 1; ++ MS_U8 btsBase_3 : 1; ++ MS_U8 btsReserved : 4; ++}ST_SCLDMA_RW_FLGA_TYPE; ++ ++typedef struct ++{ ++ union ++ { ++ MS_U8 u8Flag; ++ ST_SCLDMA_RW_FLGA_TYPE bvFlag; ++ }; ++ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ EN_SCLDMA_COLOR_TYPE enColor; ++ EN_SCLDMA_BUFFER_MODE_TYPE enBuffMode; ++ MS_U32 u32Base_Y[MAX_BUFFER_COUNT]; ++ MS_U32 u32Base_C[MAX_BUFFER_COUNT]; ++ MS_U32 u32Base_V[MAX_BUFFER_COUNT]; ++ MS_U8 u8MaxIdx; ++ MS_U16 u16Width; ++ MS_U16 u16Height; ++}ST_SCLDMA_RW_CONFIG; ++ ++typedef struct ++{ ++ MSOS_ST_CLK* idclk; ++ MSOS_ST_CLK* fclk1; ++ MSOS_ST_CLK* fclk2; ++ MSOS_ST_CLK* odclk; ++}ST_SCLDMA_CLK_CONFIG; ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ ST_SCLDMA_CLK_CONFIG *stclk; ++}ST_SCLDMA_ONOFF_CONFIG; ++ ++typedef struct ++{ ++ EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigMd; ++ EN_SCLDMA_REGEN_VS_REF_MODE_TYPE enVsRefMd; ++ MS_U16 u16Vs_Width; ++ MS_U16 u16Vs_St; ++}ST_SCLDMA_VS_CONFIG; ++ ++ ++typedef struct ++{ ++ MS_BOOL bDone; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++}ST_SCLDMA_DONE_CONFIG; ++ ++typedef struct ++{ ++ MS_U8 u8ActiveBuffer; ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ ST_SCLDMA_ONOFF_CONFIG stOnOff; ++ MS_U8 u8ISPcount; ++ MS_U64 u64FRMDoneTime; ++}ST_SCLDMA_ACTIVE_BUFFER_CONFIG; ++typedef struct ++{ ++ unsigned char u8FrameAddrIdx; ///< ID of Frame address ++ unsigned long u32FrameAddr; ///< Frame Address ++ unsigned char u8ISPcount; ///< ISP counter ++ unsigned short u16FrameWidth; ///< Frame Width ++ unsigned short u16FrameHeight; ///< Frame Height ++ unsigned long long u64FRMDoneTime; ///< Time of FRMDone ++}__attribute__ ((__packed__))ST_SCLDMA_FRAME_BUFFER_CONFIG; ++ ++typedef struct ++{ ++ EN_SCLDMA_RW_MODE_TYPE enRWMode; ++ EN_SCLDMA_ID_TYPE enID; ++ unsigned char bUsed; ++ unsigned char bFull; ++ unsigned char u8Bufferflag; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstHead; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstTail; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstWrite; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstWriteAlready; ++ ST_SCLDMA_FRAME_BUFFER_CONFIG* pstRead; ++ unsigned char u8InQueueCount; ++ unsigned char u8NextActiveId; ++ unsigned char u8AccessId; ++}ST_SCLDMA_BUFFER_QUEUE_CONFIG; ++ ++typedef struct ++{ ++ ST_SCLDMA_VS_CONFIG stVsCfg[E_SCLDMA_VS_ID_NUM]; ++ EN_SCLDMA_BUFFER_MODE_TYPE enBuffMode[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bDMAOnOff[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bDMAidx[E_SCLDMA_CLIENT_NUM]; ++ MS_BOOL bMaxid[E_SCLDMA_CLIENT_NUM]; ++ MS_U16 bDmaflag[E_SCLDMA_CLIENT_NUM];//bit0 next time off , bit 1 blanking ,bit 2 DMAonoff, bit3 no DMA on ++ MS_U64 u64mask; ++ EN_SCLDMA_COLOR_TYPE enColor[E_SCLDMA_CLIENT_NUM]; ++ MS_U32 u32Base_Y[E_SCLDMA_CLIENT_NUM][MAX_BUFFER_COUNT]; ++ MS_U32 u32Base_C[E_SCLDMA_CLIENT_NUM][MAX_BUFFER_COUNT]; ++ MS_U32 u32Base_V[E_SCLDMA_CLIENT_NUM][MAX_BUFFER_COUNT]; ++ MS_U16 u16FrameWidth[E_SCLDMA_CLIENT_NUM]; ++ MS_U16 u16FrameHeight[E_SCLDMA_CLIENT_NUM]; ++#if SCLDMA_IRQ_EN ++ MS_S32 s32IrqTaskid; ++ MS_S32 s32IrqEventId; ++ MS_S32 s32IrqTimerId; ++#endif ++}ST_SCLDMA_INFO_TYPE; ++typedef struct ++{ ++ MS_U16 u16DMAcount; ++ MS_U16 u16DMAH; ++ MS_U16 u16DMAV; ++ MS_U32 u32Trigcount; ++ EN_SCLDMA_COLOR_TYPE enColor; ++ EN_SCLDMA_BUFFER_MODE_TYPE enBuffMode; ++ MS_U32 u32Base_Y[MAX_BUFFER_COUNT]; ++ MS_U32 u32Base_C[MAX_BUFFER_COUNT]; ++ MS_U32 u32Base_V[MAX_BUFFER_COUNT]; ++ MS_U8 u8MaxIdx; ++ MS_U8 bDMAEn; ++ MS_U8 bDMAReadIdx; ++ MS_U8 bDMAWriteIdx; ++ MS_U8 bDMAFlag; ++ MS_U8 bSendPoll; ++ MS_U32 u32FrameDoneTime; ++ MS_U32 u32SendTime; ++ MS_U8 u8Count; ++ MS_U8 u8ResetCount; ++ MS_U8 u8DMAErrCount; ++}ST_SCLDMA_ATTR_TYPE; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// extern Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// ScldmaInfo ++/// use in Drvscldma and Drvsclirq ++/// record all DMA client status ++//////////////// ++extern ST_SCLDMA_INFO_TYPE gstScldmaInfo; ++extern MS_BOOL gbDBStatus; ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/sclirq/drvsclirq.c b/drivers/mstar/scl/infinity3/src/mxlib/drv/sclirq/drvsclirq.c +new file mode 100644 +index 00000000..7e2659fe +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/sclirq/drvsclirq.c +@@ -0,0 +1,2613 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_SCLIRQ_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "irqs.h" ++//#include ++#include "hwreg.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "mdrv_scl_dbg.h" ++#include "drvscldma_st.h" ++#include "halscldma.h" ++#include "drvscldma.h" ++#include "regCMDQ.h" ++#include "drvCMDQ.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++#include "halsclirq.h" ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_SCLIRQ_DBG(x) ++#define DRV_SCLIRQ_DBG_H(x) ++#define DRV_SCLIRQ_ERR(x) x ++#define TASKLET_ALREADY 0x8000000000000000 ++#define IN_TASKLET_ALREADY(u64flag) (((MS_U64)u64flag & TASKLET_ALREADY)!= 0) ++#define freerunID 5 ++#define ENABLE_ISR 0 ++#define ENABLE_ACTIVEID_ISR 1 ++#define ENABLE_CMDQ_ISR 1 ++#define CRITICAL_SECTION_TIME 80 ++#define CHANGE_CRITICAL_SECTION_TIMING_RANGE 3000 // (ns) ++#define CHANGE_CRITICAL_SECTION_TIMING_COUNT 60 // (ns) ++#define CRITICAL_SECTION_TIMING_MIN 500 // (ns) ++#define _Is_SCLDMA_RingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_RING) ++#define _Is_SCLDMA_SingleMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SINGLE) ++#define _Is_SCLDMA_SWRingMode(enClientType) (gstScldmaInfo.enBuffMode[(enClientType)] == E_SCLDMA_BUF_MD_SWRING) ++#define _IsFrmIN_Vsync() (gbFRMInFlag & (E_SCLIRQ_FRM_IN_COUNT_NOW )) ++#define _IsFrmIN() (gbFRMInFlag & (E_SCLIRQ_FRM_IN_COUNT_NOW << SCL_DELAYFRAME)) ++#define _IsFrmIN_Last() (gbFRMInFlag & (E_SCLIRQ_FRM_IN_COUNT_NOW<< (SCL_DELAYFRAME+1) )) ++#define _IsFrmDrop() (gstDropFrameCount) ++#if USE_RTK ++#define DRV_SCLIRQ_MUTEX_LOCK_ISR() MsOS_ObtainMutex(*_pSCLIRQ_SCLDMA_Mutex, MSOS_WAIT_FOREVER) ++#define DRV_SCLIRQ_MUTEX_UNLOCK_ISR() MsOS_ReleaseMutex(*_pSCLIRQ_SCLDMA_Mutex) ++#else ++#define DRV_SCLIRQ_MUTEX_LOCK_ISR() MsOS_ObtainMutex_IRQ(*_pSCLIRQ_SCLDMA_Mutex) ++#define DRV_SCLIRQ_MUTEX_UNLOCK_ISR() MsOS_ReleaseMutex_IRQ(*_pSCLIRQ_SCLDMA_Mutex) ++#endif ++#define DRV_SCLIRQ_MUTEX_LOCK() MsOS_ObtainMutex(_SCLIRQ_Mutex , MSOS_WAIT_FOREVER) ++#define DRV_SCLIRQ_MUTEX_UNLOCK() MsOS_ReleaseMutex(_SCLIRQ_Mutex) ++#define INT_COUNT_TOLERANCE 13 ++//------------------------------------------------------------------------------------------------- ++// structure ++//------------------------------------------------------------------------------------------------- ++#if (ENABLE_ISR) ++typedef struct ++{ ++ MS_U64 u64IRQ; ++ MS_U64 u64Flag; ++ MS_U8 u8Count[E_SCLDMA_CLIENT_NUM]; ++}ST_SCLIRQ_IFNO_TYPE; ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// _SCLIRQ_Mutex ++/// use in sclirq mutex,not include isr ++//////////////// ++MS_S32 _SCLIRQ_Mutex = -1; ++ ++///////////////// ++/// _pSCLIRQ_SCLDMA_Mutex ++/// scldma and sclirq mutex, include isr, send form scldma ++//////////////// ++MS_S32* _pSCLIRQ_SCLDMA_Mutex = NULL; ++ ++///////////////// ++/// gsclirqstate ++/// record irq state and set event as frame done ++//////////////// ++SCLIRQTXEvent gsclirqstate; ++MS_U32 gu32Time; ++MS_U32 gu32FrmEndTime; ++ ++///////////////// ++/// gscl3irqstate ++/// record irq state and set event as frame done ++//////////////// ++SCLIRQSC3Event gscl3irqstate; ++ ++///////////////// ++/// _bSCLIRQ_Suspend ++/// record Suspend ++//////////////// ++MS_BOOL _bSCLIRQ_Suspend = 0; ++ ++///////////////// ++/// gu32IRQNUM ++/// record IRQ number to exit ++//////////////// ++MS_U32 gu32IRQNUM; ++MS_U32 gu32CMDQIRQNUM; ++///////////////// ++/// _s32FRMENDEventId ++/// the frame done wait queue ID ++//////////////// ++MS_S32 _s32FRMENDEventId; ++ ++///////////////// ++/// _s32SYNCEventId ++/// the fclk sync wait queue ID ++//////////////// ++MS_S32 _s32SYNCEventId; ++ ++///////////////// ++/// _s32SC3EventId ++/// the Sc3 wait queue ID ++//////////////// ++MS_S32 _s32SC3EventId; ++MS_S32 _s32IRQEventId[EN_SCLIRQ_SCIRQ_MAX]; ++ ++///////////////// ++/// gbFRMInFlag ++/// use in Drvhvsp and Drvsclirq, and pass to Drvscldma ++/// if pre-crop (ISP) is receive full count ,ISR will set this TRUE; ++//////////////// ++MS_BOOL gbFRMInFlag; ++ ++///////////////// ++/// gbPtgenMode ++/// use in Drvscldma,Drvhvsp and Drvsclirq ++/// if True ,is debug ptgen mode. interrupt FRM_IN is inefficacy,so need to ignore. ++//////////////// ++unsigned char gbPtgenMode; ++unsigned char gbDMADoneEarlyISP; ++ ++///////////////// ++/// gstThreadCfg ++/// IST thread ++//////////////// ++ST_SCLDMA_THREAD_CONFIG gstThreadCfg; ++SCLIRQDAZAEvent genDAZAEvent; ++ ++///////////////// ++/// gbMonitorCropMode ++/// it use by device attribute to judge checking type ++//////////////// ++unsigned char gbMonitorCropMode; ++///////////////// ++/// gbEachDMAEnable ++/// record frame status ++//////////////// ++static MS_BOOL gbEachDMAEnable; ++MS_BOOL gbBypassDNR; ++volatile MS_BOOL gbInBlanking; ++ST_SCLIRQ_SCINTS_TYPE gstSCInts; ++MS_U8 gstDropFrameCount; ++MS_BOOL gbsc2frame2reopen = 0; ++#if (ENABLE_ISR) ++ST_SCLIRQ_IFNO_TYPE gstSCLIrqInfo; ++#endif ++ST_SCLIRQ_DMAHANG_CNT gstDmaHang; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++#if (ENABLE_CMDQ_ISR) ++#if USE_RTK ++irqreturn_t _Drv_SCLIRQ_CMDQ_isr(int eIntNum, void* dev_id) ++{ ++ MS_U32 u32IrqFlag; ++ MS_U32 u32Time; ++ u32IrqFlag = Drv_CMDQ_GetFinalIrq(EN_CMDQ_TYPE_IP0); ++ Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_TYPE_IP0,u32IrqFlag); ++ u32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ if(u32IrqFlag & CMDQ_IRQ_STATE_TRIG) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_CMDQ0TRIG); ++ } ++ if(u32IrqFlag & CMDQ_IRQ_STATE_DONE) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_CMDQ0DONE); ++ } ++ MsOS_QueueWork(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_IRQ], ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEIRQ],0); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISR, "[CMDQ]u32IrqFlag:%lx %lu\n",u32IrqFlag,u32Time); ++ return IRQ_HANDLED; ++} ++ ++#else ++void _Drv_SCLIRQ_CMDQ_StateTrig(void) ++{ ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CMDQGOING); ++} ++void _Drv_SCLIRQ_CMDQ_StateDone(void) ++{ ++ MS_U32 u32Events; ++ MS_BOOL bLDC = 0; ++ u32Events = MsOS_GetEvent(_s32SYNCEventId); ++ if(u32Events & E_SCLIRQ_EVENT_BRESETDNR) ++ { ++ SCL_DBGERR("[DRVSCLIRQ]%s:!!!E_SCLIRQ_DAZA_BRESETDNR@:%lu\n",__FUNCTION__,((MS_U32)MsOS_GetSystemTimeStamp())); ++ Hal_SCLIRQ_Set_Reg(REG_SCL0_03_L, 0, BIT12); //LDC path close ++ Hal_SCLIRQ_SetDNRBypass(1); ++ gbBypassDNR = 1; ++ MsOS_SetSCLFrameDelay(0); ++ MsOS_ClearEvent(_s32SYNCEventId,(E_SCLIRQ_EVENT_BRESETDNR)); ++ } ++ if(u32Events & E_SCLIRQ_EVENT_SETDELAY) ++ { ++ bLDC = ((Hal_SCLIRQ_Get_RegVal(REG_SCL0_03_L)&BIT12)? 1 : 0); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISR, ++ "[DRVSCLIRQ]%s:!!!E_SCLIRQ_EVENT_SETDELAY %hhd@:%lu\n",__FUNCTION__,bLDC,((MS_U32)MsOS_GetSystemTimeStamp())); ++ MsOS_SetSCLFrameDelay(bLDC); ++ MsOS_ClearEvent(_s32SYNCEventId,(E_SCLIRQ_EVENT_SETDELAY)); ++ } ++ if(u32Events & E_SCLIRQ_EVENT_SETCHANGESIZE) ++ { ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CHANGESIZEDONE); ++ MsOS_ClearEvent(_s32SYNCEventId,(E_SCLIRQ_EVENT_SETCHANGESIZE)); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISR, ++ "[DRVSCLIRQ]%s:E_SCLIRQ_EVENT_SETCHANGESIZE Done@:%lu\n",__FUNCTION__,((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CMDQDONE); ++ MsOS_QueueWork(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA], ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUECMDQ],0); ++ Drv_CMDQ_SetLPoint(EN_CMDQ_TYPE_IP0); ++} ++ ++irqreturn_t _Drv_SCLIRQ_CMDQ_isr(int eIntNum, void* dev_id) ++{ ++ MS_U32 u32IrqFlag; ++ MS_U32 u32Time; ++ u32IrqFlag = Drv_CMDQ_GetFinalIrq(EN_CMDQ_TYPE_IP0); ++ Drv_CMDQ_ClearIrqByFlag(EN_CMDQ_TYPE_IP0,u32IrqFlag); ++ u32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ if(u32IrqFlag & CMDQ_IRQ_STATE_TRIG) ++ { ++ _Drv_SCLIRQ_CMDQ_StateTrig(); ++ } ++ if(u32IrqFlag & CMDQ_IRQ_STATE_DONE) ++ { ++ _Drv_SCLIRQ_CMDQ_StateDone(); ++ } ++ if(u32IrqFlag & (0x700)) ++ { ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_TYPE_IP0,1); ++ SCL_ERR("[CMDQ]POLL/Wait timeout\n"); ++ Drv_CMDQ_SetSkipPollWhenWaitTimeOut(EN_CMDQ_TYPE_IP0,0); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISR, "[CMDQ]u32IrqFlag:%lx %lu\n",u32IrqFlag,u32Time); ++ return IRQ_HANDLED; ++} ++#endif ++#endif ++void _Drv_SCLIRQ_SclFrameEndConnectToISP(void) ++{ ++ scl_ve_isr(); ++} ++void _Drv_SCLIRQ_SclFrameStartConnectToISP(void) ++{ ++ scl_vs_isr(); ++} ++#if ENABLE_ISR ++irqreturn_t _Drv_SCLIRQ_isr(int eIntNum, void* dev_id) ++{ ++ MS_U64 u64Flag = Hal_SCLIRQ_Get_Flag(EN_SCLIRQ_SCTOP_0,0xFFFFFFFFFF); ++ ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,u64Flag, 1); ++ ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,u64Flag, 0); ++ ++ return IRQ_HANDLED; ++} ++ ++#elif ENABLE_ACTIVEID_ISR ++SCLIRQTXEvent _Drv_SCLIRQ_GetISTEventFlag(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ switch(enClient) ++ { ++ case E_SCLDMA_1_FRM_W: ++ return E_SCLIRQ_EVENT_ISTSC1FRM; ++ case E_SCLDMA_1_SNP_W: ++ return E_SCLIRQ_EVENT_ISTSC1SNP; ++ case E_SCLDMA_2_FRM_W: ++ return E_SCLIRQ_EVENT_ISTSC2FRM; ++ case E_SCLDMA_2_FRM2_W: ++ return E_SCLIRQ_EVENT_ISTSC2FRM2; ++ default : ++ return E_SCLIRQ_EVENT_CLEAR; ++ } ++} ++void _Drv_SCLIRQ_SetIsBlankingRegion(MS_BOOL bBk) ++{ ++ gbInBlanking = bBk; ++} ++MS_BOOL Drv_SCLIRQ_GetIsVIPBlankingRegion(void) ++{ ++ MS_U32 u32Time; ++ u32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ if(gbInBlanking && gu32FrmEndTime && gstSCInts.u32ISPDoneCount&& ++ ((u32Time - gu32FrmEndTime)>((gstSCInts.u32ISPBlankingTime)))) ++ { ++ if((u32Time - gu32FrmEndTime)>((gstSCInts.u32ISPBlankingTime)*2)) ++ { ++ // error ++ return gbInBlanking; ++ } ++ return 0; ++ } ++ else if(MsOS_GetEvent(_s32SYNCEventId) & E_SCLIRQ_EVENT_CMDQDONE) ++ { ++ return gbInBlanking; ++ } ++ else ++ { ++ return gbInBlanking; ++ } ++} ++MS_BOOL Drv_SCLIRQ_GetIsBlankingRegion(void) ++{ ++ MS_BOOL bRet = gbInBlanking; ++ MS_U32 u32Time; ++ u32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ //critical section ++ if(gbInBlanking && gu32FrmEndTime && gstSCInts.u32ISPDoneCount&& ++ ((u32Time - gu32FrmEndTime)>((gstSCInts.u32ISPBlankingTime)-CRITICAL_SECTION_TIME))) ++ { ++ bRet = 0; ++ if((u32Time - gu32FrmEndTime)>((gstSCInts.u32ISPBlankingTime)*2)) ++ { ++ // error ++ bRet = gbInBlanking; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()==(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "[SCLIRQ]Blanking Critical Section (%ld ,%ld)\n", ++ (u32Time - gu32FrmEndTime),((gstSCInts.u32ISPBlankingTime)-CRITICAL_SECTION_TIME)); ++ } ++ } ++ else ++ { ++ bRet = gbInBlanking; ++ } ++ return bRet; ++} ++void _Drv_SCLIRQ_SetSingleModeDMAInfo(EN_SCLDMA_CLIENT_TYPE enclient, MS_U32 u32Events) ++{ ++ if ((u32Events & (SCLIRQ_ISTEVENT_BASE << enclient)) && _Is_SCLDMA_SingleMode(enclient)) ++ { ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ gstScldmaInfo.bDMAOnOff[enclient] = 0; ++ Drv_SCLDMA_SetFrameResolution(enclient); ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++ } ++} ++void _Drv_SCLIRQ_SetSingleModeDMAInfoNoLock(EN_SCLDMA_CLIENT_TYPE enclient, MS_U32 u32Events) ++{ ++ if ((u32Events & (SCLIRQ_ISTEVENT_BASE << enclient)) && _Is_SCLDMA_SingleMode(enclient)) ++ { ++ gstScldmaInfo.bDMAOnOff[enclient] = 0; ++ Drv_SCLDMA_SetFrameResolution(enclient); ++ } ++} ++static void Drv_SCLIRQ_RingMode_Active(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U8 u8RPoint = 0; ++ MS_U32 u32Time; ++ MS_U16 u16RealIdx; ++ u32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ u8RPoint = (_GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_OMX))>>4; ++ if(!_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ u16RealIdx = Hal_SCLDMA_Get_RW_Idx(enClient); ++ } ++ else ++ { ++ u16RealIdx = _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ } ++ Drv_SCLDMA_SetFrameResolution(enClient); ++ if(u8RPoint==u16RealIdx && !_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING))//5 is debug freerun ++ { ++ //trig off ++ if(u8RPoint != freerunID ) ++ { ++ Drv_SCLDMA_SetISRHandlerDMAOff(enClient,0); ++ _SetFlagType(enClient,E_SCLDMA_FLAG_EVERDMAON); ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ _SetFlagType(enClient,(E_SCLDMA_FLAG_DMAOFF|E_SCLDMA_FLAG_ACTIVE)); ++ } ++ else ++ { ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_DMAOFF)); ++ } ++ } ++ else ++ { ++ _SetANDGetIdxType(enClient,u16RealIdx,E_SCLDMA_ACTIVE_BUFFER_OMX); ++ _SetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,0), ++ "[DRVSCLDMA]%d ISR R_P=%hhx RealIdx=%hx flag:%hx @:%lu\n" ++ ,enClient,u8RPoint,u16RealIdx,gstScldmaInfo.bDmaflag[enClient],u32Time); ++} ++static void Drv_SCLIRQ_RingMode_Active_N(EN_SCLDMA_CLIENT_TYPE enclient) ++{ ++ _SetANDGetFlagType(enclient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_ACTIVE); ++ if(_IsFlagType(enclient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ gstScldmaInfo.bDMAOnOff[enclient] = 0; ++ } ++ if(_IsFlagType(enclient,E_SCLDMA_FLAG_BLANKING)) ++ { ++ _ReSetFlagType(enclient,E_SCLDMA_FLAG_BLANKING); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enclient,1), "[DRVSCLDMA]%d ISR actN flag:%hx idx:%hhd @:%lu\n" ++ ,enclient,gstScldmaInfo.bDmaflag[enclient],gstScldmaInfo.bDMAidx[enclient],((MS_U32)MsOS_GetSystemTimeStamp())); ++ //printf("ACTIVE_N:%lu\n",u32Time); ++} ++static void Drv_SCLIRQ_RingMode_ActiveWithoutDoublebuffer(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U8 u8RPoint = 0; ++ MS_U16 u16RealIdx; ++ if(_IsFlagType(enClient,E_SCLDMA_FLAG_ACTIVE)) ++ { ++ _SetFlagType(enClient,E_SCLDMA_FLAG_FRMIGNORE); ++ SCL_DBGERR("[DRVSCLIRQ]%d!!!!!!!!!!!!double active\n",enClient); ++ } ++ else ++ { ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_ACTIVE,(~E_SCLDMA_FLAG_FRMDONE)); ++ } ++ u8RPoint = (_GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_OMX))>>4; ++ if(!_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ u16RealIdx = Hal_SCLDMA_Get_RW_Idx(enClient); ++ if(u16RealIdx == 0 && _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL) != gstScldmaInfo.bMaxid[enClient]&& ++ !(_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING))) ++ { ++ _SetFlagType(enClient,E_SCLDMA_FLAG_FRMIGNORE); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,0), ++ "[DRVSCLDMA]%d wodb ISR ignore\n" ++ ,enClient); ++ } ++ } ++ else ++ { ++ u16RealIdx = _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ } ++ Drv_SCLDMA_SetFrameResolution(enClient); ++ _SetANDGetIdxType(enClient,u16RealIdx,E_SCLDMA_ACTIVE_BUFFER_OMX); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,0), ++ "[DRVSCLDMA]%d wodb ISR R_P=%hhx RealIdx=%hx flag:%hx @:%lu\n" ++ ,enClient,u8RPoint,u16RealIdx,gstScldmaInfo.bDmaflag[enClient],gu32Time); ++} ++static MS_BOOL Drv_SCLIRQ_RingMode_Active_NWithoutDoublebuffer(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U8 u8RPoint = 0; ++ MS_U16 u16RealIdx; ++ if((!_IsFlagType(enClient,E_SCLDMA_FLAG_FRMIN))) ++ { ++ _SetFlagType(enClient,E_SCLDMA_FLAG_FRMIGNORE); ++ } ++ if(!_IsFlagType(enClient,E_SCLDMA_FLAG_FRMIGNORE)) ++ { ++ u8RPoint = (_GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_OMX))>>4; ++ u16RealIdx = _GetIdxType(enClient,E_SCLDMA_ACTIVE_BUFFER_SCL); ++ if(u8RPoint==u16RealIdx && !_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING))//5 is debug freerun ++ { ++ //trig off ++ if(u8RPoint != freerunID ) ++ { ++ Drv_SCLDMA_SetSWReTrigCount(enClient,1); ++ Drv_SCLDMA_SetISRHandlerDMAOff(enClient,0); ++ _SetANDGetFlagType ++ (enClient,E_SCLDMA_FLAG_FRMDONE|E_SCLDMA_FLAG_EVERDMAON|E_SCLDMA_FLAG_DMAOFF,(~E_SCLDMA_FLAG_ACTIVE)); ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ } ++ else ++ { ++ _SetANDGetIdxType(enClient,(u16RealIdx),(E_SCLDMA_ACTIVE_BUFFER_OMX)); ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_FRMDONE,(~(E_SCLDMA_FLAG_DMAOFF|E_SCLDMA_FLAG_ACTIVE))); ++ } ++ } ++ else ++ { ++ _SetANDGetFlagType(enClient,E_SCLDMA_FLAG_FRMDONE,(~E_SCLDMA_FLAG_ACTIVE)); ++ } ++ if(_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ gstScldmaInfo.bDMAOnOff[enClient] = 0; ++ } ++ if(_IsFlagType(enClient,E_SCLDMA_FLAG_BLANKING)) ++ { ++ _ReSetFlagType(enClient,E_SCLDMA_FLAG_BLANKING); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,1), "[DRVSCLDMA]%d ISR actN wodb flag:%hx idx:%hhx @:%lu\n" ++ ,enClient,gstScldmaInfo.bDmaflag[enClient],gstScldmaInfo.bDMAidx[enClient],((MS_U32)MsOS_GetSystemTimeStamp())); ++ return 1; ++ } ++ else ++ { ++ _ReSetFlagType(enClient,E_SCLDMA_FLAG_FRMIGNORE); ++ if(u8RPoint != freerunID ) ++ { ++ Drv_SCLDMA_SetDMAIgnoreCount(enClient,1); ++ Drv_SCLDMA_SetISRHandlerDMAOff(enClient,0); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&Get_DBGMG_SCLIRQclient(enClient,1), ++ "[DRVSCLDMA]%d ISR actN wodb ignore flag:%hx\n" ++ ,enClient,gstScldmaInfo.bDmaflag[(enClient)]); ++ _SetANDGetFlagType ++ (enClient,E_SCLDMA_FLAG_FRMDONE|E_SCLDMA_FLAG_EVERDMAON|E_SCLDMA_FLAG_DMAOFF,(~(E_SCLDMA_FLAG_ACTIVE))); ++ } ++ if(_IsFlagType(enClient,E_SCLDMA_FLAG_DMAOFF)) ++ { ++ gstScldmaInfo.bDMAOnOff[enClient] = 0; ++ } ++ _ReSetFlagType(enClient,E_SCLDMA_FLAG_FRMIN); ++ MsOS_SetEvent(_s32FRMENDEventId, (0x1 < u64lasttime) ++ { ++ u64lasttime = u64Time; ++ } ++ else ++ { ++ printf("[DRVSCLIRQ]!!!!!!!! system time reset last:%lld this:%lld\n",u64lasttime,u64Time); ++ u64lasttime = u64Time; ++ } ++} ++void _Drv_SCLIRQ_FrmDoneEventHandler(void) ++{ ++ SCLIRQTXEvent enEvent = gsclirqstate; ++ if(enEvent) ++ { ++ enEvent |= (E_SCLIRQ_EVENT_IRQ|E_SCLIRQ_EVENT_HVSPST); ++ MsOS_SetEvent(_s32FRMENDEventId, enEvent); ++ if(gsclirqstate &E_SCLIRQ_EVENT_SC1FRM && (gbMonitorCropMode == 2)) ++ { ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_SYNC); ++ } ++ gsclirqstate &= (~enEvent); ++ gsclirqstate |= E_SCLIRQ_EVENT_SET; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "%s @:%lu\n",__FUNCTION__,gu32Time); ++ } ++} ++void _Drv_SCLIRQ_CMDQBlankingHandler(void) ++{ ++ if(MsOS_GetEvent(_s32SYNCEventId)&E_SCLIRQ_EVENT_CMDQFIRE ) ++ { ++ Drv_CMDQ_BeTrigger(EN_CMDQ_TYPE_IP0,1); ++ MsOS_ClearEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_CMDQFIRE)); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&(EN_DBGMG_CMDQEVEL_ISR), ++ "%s @:%lu\n",__FUNCTION__,gu32Time); ++ } ++} ++void _Drv_SCLIRQ_SetFRMINWhenDMADoneEarlyISP(MS_BOOL bEn) ++{ ++ if(bEn) ++ { ++ _SetFlagType(E_SCLDMA_1_FRM_W,E_SCLDMA_FLAG_FRMIN); ++ _SetFlagType(E_SCLDMA_1_SNP_W,E_SCLDMA_FLAG_FRMIN); ++ _SetFlagType(E_SCLDMA_2_FRM_W,E_SCLDMA_FLAG_FRMIN); ++ _SetFlagType(E_SCLDMA_2_FRM2_W,E_SCLDMA_FLAG_FRMIN); ++ } ++ else ++ { ++ _ReSetFlagType(E_SCLDMA_1_FRM_W,E_SCLDMA_FLAG_FRMIN); ++ _ReSetFlagType(E_SCLDMA_1_SNP_W,E_SCLDMA_FLAG_FRMIN); ++ _ReSetFlagType(E_SCLDMA_2_FRM_W,E_SCLDMA_FLAG_FRMIN); ++ _ReSetFlagType(E_SCLDMA_2_FRM2_W,E_SCLDMA_FLAG_FRMIN); ++ } ++} ++void _Drv_SCLIRQ_FrmEndhandler(void) ++{ ++ unsigned char idx; ++ unsigned char loop = 0; ++ if(!gbEachDMAEnable) ++ { ++ gbEachDMAEnable = 1; ++ } ++ else if(gsclirqstate) ++ { ++ } ++ else ++ { ++ for(idx = 0;idx2) ++ { ++ *bAffcount = 0; ++ Drv_SCLIRQ_SetDAZAQueueWork(E_SCLIRQ_DAZA_BRESETFCLK); ++ if(gstDropFrameCount <= 1) ++ { ++ gstDropFrameCount = 1; ++ } ++ u8framecount = 0; ++ } ++} ++void _Drv_SCLIRQ_AffFullHandler(MS_BOOL *bAffFull ,MS_BOOL *bAffcount) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "SC AFF FULL %lu @:%lu\n",gstSCInts.u32AffCount,gu32Time); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "CROP H:%hd V:%hd \n",Hal_SCLIRQ_Get_RegVal(REG_SCL2_70_L),Hal_SCLIRQ_Get_RegVal(REG_SCL2_71_L)); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "CROP2 H:%hd V:%hd \n",Hal_SCLIRQ_Get_RegVal(REG_SCL2_72_L),Hal_SCLIRQ_Get_RegVal(REG_SCL2_73_L)); ++ *bAffFull = 1; ++ Drv_SCLIRQ_Disable(SCLIRQ_AFF_FULL); ++ _Drv_SCLIRQ_IsAffFullContinue(bAffFull,bAffcount); ++ if(gstSCInts.u32AffCount == INT_COUNT_TOLERANCE) ++ { ++ Drv_SCLIRQ_SetDAZAQueueWork(E_SCLIRQ_DAZA_BCLOSECIIR); ++ } ++ else if(gstSCInts.u32AffCount == 30) ++ { ++ MsOS_ClearEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_BCLOSECIIR); ++ } ++ else if(gstSCInts.u32AffCount == 40) ++ { ++ Drv_SCLIRQ_SetDAZAQueueWork(E_SCLIRQ_DAZA_BCLOSECIIR); ++ } ++} ++void _Drv_SCLIRQ_FrameInEndHandler(MS_BOOL *bNonFRMEndCount,MS_BOOL *bISPFramePerfect,MS_BOOL *bAffFull) ++{ ++ if(MsOS_GetEvent(_s32SYNCEventId)&E_SCLIRQ_EVENT_FRMENDSYNC) ++ { ++ Drv_SCLIRQ_SetDMADoneEarlyISP(1); ++ } ++ else ++ { ++ Drv_SCLIRQ_SetDMADoneEarlyISP(0); ++ } ++ Drv_SCLDMA_SetISPFrameCount(); ++ *bISPFramePerfect = 1; ++ //_Drv_SCLIRQ_HandlerFRMIN((*bAffFull) ? 0 : 1); //for AFF drop ++ _Drv_SCLIRQ_HandlerFRMIN(1); ++ if(gbBypassDNR) ++ { ++ Hal_SCLIRQ_SetDNRBypass(0); ++ gbBypassDNR = 0; ++ } ++ if(gbDMADoneEarlyISP) ++ { ++ if(!SCL_DELAYFRAME) ++ { ++ _Drv_SCLIRQ_SetFRMINWhenDMADoneEarlyISP(1); ++ //TODO:not open this time ++ _Drv_SCLIRQ_FrmDoneEventHandler(); ++ } ++ _Drv_SCLIRQ_CMDQBlankingHandler(); ++ } ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_ISPFRMEND); ++} ++void _Drv_SCLIRQ_IDCLKVsyncInRealTimeHandler(void) ++{ ++ MsOS_SetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_LDCSYNC); ++ MsOS_ClearEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_FRMENDSYNC|E_SCLIRQ_EVENT_ISPFRMEND)); ++ if(gbEachDMAEnable) ++ { ++ _Drv_SCLIRQ_SetIsBlankingRegion(0); ++ } ++ //disable dnr for ISP not perfect ++ if(!_IsFrmIN_Vsync()) ++ { ++ Hal_SCLIRQ_SetDNRBypass(1); ++ gbBypassDNR = 1; ++ } ++ if(gsclirqstate &E_SCLIRQ_EVENT_SET) ++ { ++ gsclirqstate = E_SCLIRQ_EVENT_CLEAR; ++ } ++ else if(gsclirqstate) ++ { ++ gstSCInts.u32ErrorCount++; ++ if(gbDMADoneEarlyISP) ++ { ++ if(!SCL_DELAYFRAME) ++ { ++ SCL_DBGERR("[LDC]:ISP_IN lost:%lu\n",gstSCInts.u32ErrorCount); ++ _Drv_SCLIRQ_SetFRMINWhenDMADoneEarlyISP(0); ++ //TODO:not open this time ++ _Drv_SCLIRQ_FrmDoneEventHandler(); ++ if(gsclirqstate &E_SCLIRQ_EVENT_SET) ++ { ++ gsclirqstate = E_SCLIRQ_EVENT_CLEAR; ++ } ++ } ++ _Drv_SCLIRQ_CMDQBlankingHandler(); ++ } ++ } ++ else if(gbDMADoneEarlyISP && !_IsFrmIN_Vsync()) ++ { ++ // for rotate make stream hang up ++ SCL_DBGERR("[LDC]ISP_IN lost:%lu\n",gstSCInts.u32ErrorCount); ++ _Drv_SCLIRQ_CMDQBlankingHandler(); ++ } ++} ++void _Drv_SCLIRQ_LDCVsyncInRealTimeHandler(void) ++{ ++ unsigned char idx; ++ unsigned char loop = 0; ++ if(gbEachDMAEnable) ++ { ++ if(!(MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_FRMENDSYNC))) ++ { ++ //not in framedone ++ for(idx = 0;idx100) ++ { ++ if(gstDmaHang.bResetHangCnt<3) ++ { ++ Drv_SCLIRQ_SetDAZAQueueWork(E_SCLIRQ_DAZA_BRESETLDCP); ++ gstDmaHang.bResetHangCnt++; ++ gstDmaHang.bLDCEvenOpen = 0; ++ gstDmaHang.bLDCEvenOpenCount = 0; ++ } ++ else ++ { ++ gstDmaHang.bLDCEvenOpen = 0; ++ gstDmaHang.bLDCEvenOpenCount = 0; ++ } ++ } ++ if(gstDmaHang.bVsyncWithVend > INT_COUNT_TOLERANCE && (Hal_SCLIRQ_Get_RegVal(REG_SCL0_03_L)&BIT12)) ++ { ++ Drv_SCLIRQ_SetDAZAQueueWork(E_SCLIRQ_DAZA_BCLOSELDCP); ++ gstDmaHang.bLDCEvenOpen = 1; ++ gstDmaHang.bVsyncWithVend = 0; ++ gstDmaHang.bLDCEvenOpenCount = 0; ++ } ++} ++MS_BOOL _Drv_SCLIRQ_ISTWork(ST_SCLDMA_THREAD_CONFIG *pstThread) ++{ ++ if (IS_ERR(pstThread->sttask.pThread)) ++ { ++ pstThread->sttask.pThread = NULL; ++ Drv_SCLDMA_SetThreadOnOffFlag(0,pstThread); ++ DRV_SCLIRQ_ERR(printf("[DRVSCLDMA]Fail:creat thread\n")); ++ return FALSE; ++ } ++ else ++ { ++ Drv_SCLDMA_SetThreadOnOffFlag(1,pstThread); ++ return TRUE; ++ } ++} ++void _Drv_SCLIRQ_SetISPBlankingTime(MS_U32 u32DiffTime) ++{ ++ static MS_BOOL bChangeTimingCount = 0; ++ if(gstSCInts.u32ISPBlankingTime > u32DiffTime && (u32DiffTime > CRITICAL_SECTION_TIMING_MIN)) ++ { ++ //for get most critical ++ gstSCInts.u32ISPBlankingTime = u32DiffTime; ++ } ++ else if(gstSCInts.u32ISPBlankingTime == 0) ++ { ++ //for get inital ++ gstSCInts.u32ISPBlankingTime = u32DiffTime; ++ } ++ else if (gstSCInts.u32ISPBlankingTime < u32DiffTime) ++ { ++ if(u32DiffTime - gstSCInts.u32ISPBlankingTime > CHANGE_CRITICAL_SECTION_TIMING_RANGE) ++ { ++ // for timing change ++ bChangeTimingCount ++; ++ } ++ else ++ { ++ bChangeTimingCount = 0; ++ } ++ if(bChangeTimingCount > CHANGE_CRITICAL_SECTION_TIMING_COUNT) ++ { ++ // for ensure timing change ++ gstSCInts.u32ISPBlankingTime = u32DiffTime; ++ SCL_DBGERR("[SCLIRQ]chang time :%lu\n",gstSCInts.u32ISPBlankingTime); ++ bChangeTimingCount = 0; ++ } ++ } ++} ++MS_U64 _Drv_SCLIRQ_FlagRefine(MS_U64 u64Flag) ++{ ++ static MS_BOOL bDMAHangUp = 0; ++ // for ensure blanking is real if interrupt not stable. ++ ++ if((u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC)&&(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END)&&(u64Flag &SCLIRQ_MSK_SC_IN_FRM_END)) ++ { ++ // for no handle case ++ bDMAHangUp = 0; ++ return u64Flag; ++ } ++ if((u64Flag &SCLIRQ_MSK_SC_IN_FRM_END)&&(bDMAHangUp)) ++ { ++ // shift frame end to real blanking when interrupt not stable. ++ u64Flag |=(SCLIRQ_MSK_SC1_ENG_FRM_END); ++ bDMAHangUp = 0; ++ } ++ if((u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC)&&(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END)) ++ { ++ // for make sure frame end is blanking ++ u64Flag &=(~SCLIRQ_MSK_SC1_ENG_FRM_END); ++ bDMAHangUp = 1; ++ } ++ else if((u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC) && bDMAHangUp &&!(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END)) ++ { ++ // for already recover ++ bDMAHangUp = 0; ++ } ++ else if((u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END) && bDMAHangUp &&!(u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC)) ++ { ++ // for already recover ++ bDMAHangUp = 0; ++ } ++ return u64Flag; ++} ++#if USE_RTK ++void _Drv_SCLIRQ_CMDQ_StateTrig(void) ++{ ++ MsOS_ClearEvent(_s32SYNCEventId,E_SCLIRQ_EVENT_CMDQ); ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CMDQGOING); ++} ++void _Drv_SCLIRQ_CMDQ_StateDone(void) ++{ ++ MsOS_SetEvent(_s32SYNCEventId, E_SCLIRQ_EVENT_CMDQDONE); ++ Drv_CMDQ_SetRPoint(EN_CMDQ_TYPE_IP0); ++ MsOS_QueueWork(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA], ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUECMDQ],0); ++} ++static int SCLIRQ_IST(void *arg) ++{ ++ static MS_BOOL bAffFull = 0,bAffcount=0; ++ static MS_BOOL bISPFramePerfect = 0; ++ static MS_BOOL bNonFRMEndCount = 0; ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE, "[DRVSCLIRQ]%s:going \n",__FUNCTION__); ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_AFFFULL)) ++ { ++ _Drv_SCLIRQ_AffFullHandler(&bAffFull, &bAffcount); ++ } ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_INFRMEND)) ++ { ++ _Drv_SCLIRQ_FrameInEndHandler(&bNonFRMEndCount,&bISPFramePerfect,&bAffFull); ++ } ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_FCLKLDC)) ++ { ++ _Drv_SCLIRQ_LDCVsyncInHandler(&bISPFramePerfect,&bAffFull); ++ bAffFull = 0; ++ } ++ // SC1 FRM ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC1FRMWACTIVE)) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_1_FRM_W); ++ } ++ ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC1FRMWACTIVE_N)) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_1_FRM_W)) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC1FRM|E_SCLIRQ_EVENT_ISTSC1FRM); ++ } ++ } ++ ++ ++ // SC2 FRM ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC2FRMWACTIVE)) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_2_FRM_W); ++ } ++ ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC2FRMWACTIVE_N)) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_2_FRM_W)) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC2FRM|E_SCLIRQ_EVENT_ISTSC2FRM); ++ } ++ } ++ // SC2 FRM2 ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC2FRM2WACTIVE)) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_2_FRM2_W); ++ } ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC2FRM2WACTIVE_N)) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_2_FRM2_W)) ++ { ++ MsOS_SetEvent(_s32FRMENDEventId, (E_SCLIRQ_EVENT_SC2FRM2|E_SCLIRQ_EVENT_ISTSC2FRM2)); ++ } ++ } ++ ++ // SC1 SNP ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC1SNPWACTIVE)) ++ { ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_1_SNP_W); ++ } ++ ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC1SNPWACTIVE_N)) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_1_SNP_W)) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC1SNP|E_SCLIRQ_EVENT_ISTSC1SNP); ++ } ++ } ++ // SC SRC FRMEND ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SCTOPFRMEND)) ++ { ++ Drv_SCLIRQ_SetFrmEndInterruptStatus(gu32Time); ++ bNonFRMEndCount = 0; ++ _Drv_SCLIRQ_IsAffFullContinually(&bAffFull, &bAffcount); ++ } ++ // SC3 FRM ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC3FRMWACTIVE)) ++ { ++ gscl3irqstate = E_SCLIRQ_SC3EVENT_CLEAR; ++ gscl3irqstate |= (E_SCLIRQ_SC3EVENT_ACTIVE | E_SCLIRQ_SC3EVENT_ISTACTIVE); ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_3_FRM_W); ++ } ++ ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_SC3FRMWACTIVE_N)) ++ { ++ gscl3irqstate |= (E_SCLIRQ_SC3EVENT_ACTIVEN | E_SCLIRQ_SC3EVENT_ISTACTIVEN | E_SCLIRQ_SC3EVENT_IRQ); ++ _Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_3_FRM_W); ++ } ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_CMDQ0TRIG)) ++ { ++ _Drv_SCLIRQ_CMDQ_StateTrig(); ++ } ++ ++ if(MsOS_GetandClearEventRing(EN_SCLIRQ_SCIRQ_CMDQ0DONE)) ++ { ++ _Drv_SCLIRQ_CMDQ_StateDone(); ++ } ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++ return 0; ++ ++} ++MS_BOOL _Delete_SCLIRQ_IST(void) ++{ ++ gstThreadCfg.flag = 0; ++ MsOS_FlushWorkQueue(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA]); ++ MsOS_FlushWorkQueue(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_IRQ]); ++ MsOS_DestroyWorkQueueTask(gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA]); ++ MsOS_DestroyWorkQueueTask(gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_IRQ]); ++ return 0; ++} ++MS_BOOL _Create_SCLIRQ_IST(void) ++{ ++ char *pName2={"SCLDAZA_THREAD"}; ++ char *pName={"SCLIRQ_THREAD"}; ++ unsigned char bRet = 0; ++ gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA] = MsOS_CreateWorkQueueTask(pName2); ++ gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_IRQ] = MsOS_CreateWorkQueueTask(pName); ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUECMDQ] = MsOS_CreateWorkQueueEvent((void*)SCLIRQ_CMDQIST); ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEDAZA] = MsOS_CreateWorkQueueEvent((void*)SCLIRQ_DazaIST); ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEIRQ] = MsOS_CreateWorkQueueEvent((void*)SCLIRQ_IST); ++ return bRet; ++} ++irqreturn_t _Drv_SCLIRQ_isr(int eIntNum, void* dev_id) ++{ ++ static MS_U32 u32ActTime[7]; ++ MS_U64 u64Flag,u64Mask=0x0; ++ MS_U32 u32DiffTime; ++ u64Mask = gstScldmaInfo.u64mask; ++ u64Flag = Hal_SCLIRQ_Get_Flag(EN_SCLIRQ_SCTOP_0,0xFFFFFFFFFFFF); ++ if(_bSCLIRQ_Suspend) ++ { ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,0xFFFFFFFFFFFF, 1); ++ } ++ ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,(~u64Mask)&u64Flag, 1); ++ gu32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ if(u64Flag &SCLIRQ_MSK_AFF_FULL) ++ { ++ gstSCInts.u32AffCount++; ++ if(u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC) ++ { ++ // HW bug : aff fifo full error report ++ } ++ else ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_AFFFULL); ++ } ++ } ++ // next frame IN . because of receive and send in same time.(ISP in frame end) ++ // 1.frame coming(vsync) ++ // 2.frame receive done.(irq get sc_frm_in_end)keep in DNR ++ // 3.active from dnr(LDC_trig) ++ if(u64Flag &SCLIRQ_MSK_SC_IN_FRM_END) ++ { ++ gstSCInts.u32ISPDoneCount++; ++ u32DiffTime = gu32Time - u32ActTime[5]; ++ gstSCInts.u32ISPTime += u32DiffTime; ++ if(gstSCInts.u32ISPDoneCount > 256) ++ { ++ gstSCInts.u32ISPTime = gstSCInts.u32ISPTime/gstSCInts.u32ISPDoneCount; ++ gstSCInts.u32ISPInCount = (gstSCInts.u32ISPInCount-gstSCInts.u32ISPDoneCount)+1; ++ gstSCInts.u32ISPDoneCount = 1; ++ } ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_INFRMEND); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[FRMIN]@%lu\n",((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC) ++ { ++ u32ActTime[5] = gu32Time; ++ gstSCInts.u32ISPInCount++; ++ if(MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_FRMENDSYNC)) ++ { ++ u32DiffTime = gu32Time - u32ActTime[6]; ++ gstSCInts.u32ISPBlanking += u32DiffTime; ++ } ++ _Drv_SCLIRQ_LDCVsyncInRealTimeHandler(); ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_FCLKLDC); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[FRMLDC]Flag:%llx @%lu\n",u64Flag,gu32Time); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_IDCLK) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[IDCLK]Flag:%llx @%lu\n",u64Flag,gu32Time); ++ } ++ // SC1 FRM ++ if(u64Flag & SCLIRQ_MSK_SC1_FRM_W_ACTIVE) ++ { ++ u32ActTime[0] = gu32Time; ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC1FRMWACTIVE); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC1FRMWACTIVE_N); ++ gstSCInts.u32SC1FrmDoneCount++; ++ u32DiffTime = gu32Time - u32ActTime[0]; ++ gstSCInts.u32SC1FrmActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC1FrmDoneCount > 256) ++ { ++ gstSCInts.u32SC1FrmActiveTime = gstSCInts.u32SC1FrmActiveTime/gstSCInts.u32SC1FrmDoneCount; ++ gstSCInts.u32SC1FrmDoneCount = 1; ++ } ++ } ++ ++ ++ // SC2 FRM ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM_W_ACTIVE) ++ { ++ u32ActTime[1] = gu32Time; ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC2FRMWACTIVE); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC2FRMWACTIVE_N); ++ gstSCInts.u32SC2FrmDoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[1]; ++ gstSCInts.u32SC2FrmActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC2FrmDoneCount > 256) ++ { ++ gstSCInts.u32SC2FrmActiveTime = gstSCInts.u32SC2FrmActiveTime/gstSCInts.u32SC2FrmDoneCount; ++ gstSCInts.u32SC2FrmDoneCount = 1; ++ } ++ } ++ // SC2 FRM2 ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE) ++ { ++ u32ActTime[2] = gu32Time; ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC2FRM2WACTIVE); ++ } ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE_N) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC2FRM2WACTIVE_N); ++ // for HW bug ++ //gsclirqstate |= (E_SCLIRQ_EVENT_SC2FRM2|E_SCLIRQ_EVENT_ISTSC2FRM2); ++ if(gbsc2frame2reopen) ++ { ++ gbsc2frame2reopen = 0; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "[FRMEND]SC2 FRM2 reopen\n"); ++ if((!gbDMADoneEarlyISP) || (gbPtgenMode)) ++ { ++ _Drv_SCLIRQ_CMDQBlankingHandler(); ++ } ++ _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBufferHandler(); ++ } ++ gstSCInts.u32SC2Frm2DoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[2]; ++ gstSCInts.u32SC2Frm2ActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC2Frm2DoneCount > 256) ++ { ++ gstSCInts.u32SC2Frm2ActiveTime = gstSCInts.u32SC2Frm2ActiveTime/gstSCInts.u32SC2Frm2DoneCount; ++ gstSCInts.u32SC2Frm2DoneCount = 1; ++ } ++ } ++ ++ // SC1 SNP ++ if(u64Flag & SCLIRQ_MSK_SC1_SNP_W_ACTIVE) ++ { ++ u32ActTime[3] = gu32Time; ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC1SNPWACTIVE); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC1SNPWACTIVE_N); ++ gstSCInts.u32SC1SnpDoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[3]; ++ gstSCInts.u32SC1SnpActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC1SnpDoneCount > 256) ++ { ++ gstSCInts.u32SC1SnpActiveTime = gstSCInts.u32SC1SnpActiveTime/gstSCInts.u32SC1SnpDoneCount; ++ gstSCInts.u32SC1SnpDoneCount = 1; ++ } ++ } ++ // SC SRC FRMEND ++ if(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END) ++ { ++ Drv_SCLIRQ_SetRealTimeFrmEndHandler(gu32Time); ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SCTOPFRMEND); ++ gstSCInts.u32SCLMainDoneCount++; ++ u32ActTime[6] = gu32Time; ++ gu32FrmEndTime = gu32Time; ++ u32DiffTime = gu32Time -u32ActTime[5]; ++ gstSCInts.u32SCLMainActiveTime += u32DiffTime; ++ if(gstSCInts.u32SCLMainDoneCount > 256) ++ { ++ gstSCInts.u32ISPBlanking = gstSCInts.u32ISPBlankingTime; ++ gstSCInts.u32SCLMainActiveTime = gstSCInts.u32SCLMainActiveTime/gstSCInts.u32SCLMainDoneCount; ++ gstSCInts.u32SCLMainDoneCount = 1; ++ gstSCInts.u8CountReset ++; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "[FRMEND]%x flag:%llx,%lu\n",gsclirqstate,u64Flag,((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++ ++ // SC3 FRM_W ++ if(u64Flag & SCLIRQ_MSK_SC3_DMA_W_ACTIVE) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC3FRMWACTIVE); ++ u32ActTime[4] = gu32Time; ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N) ++ { ++ MsOS_SetEventRing(EN_SCLIRQ_SCIRQ_SC3FRMWACTIVE_N); ++ gstSCInts.u32SC3DoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[4]; ++ gstSCInts.u32SC3ActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC3DoneCount > 256) ++ { ++ gstSCInts.u32SC3ActiveTime = gstSCInts.u32SC3ActiveTime/gstSCInts.u32SC3DoneCount; ++ gstSCInts.u32SC3DoneCount = 1; ++ } ++ } ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,(~u64Mask)&u64Flag, 0); ++ u32DiffTime = ((MS_U32)MsOS_GetSystemTimeStamp())-gu32Time; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_NORMAL), ++ "[ISR]Diff:%lu(ns)\n",u32DiffTime); ++ MsOS_QueueWork(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_IRQ], ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEIRQ],0); ++ return IRQ_HANDLED; ++} ++#else ++MS_BOOL _Delete_SCLIRQ_IST(void) ++{ ++ gstThreadCfg.flag = 0; ++ MsOS_FlushWorkQueue(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA]); ++ MsOS_DestroyWorkQueueTask(gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA]); ++ return 0; ++} ++MS_BOOL _Create_SCLIRQ_IST(void) ++{ ++ char pName2[] = {"SCLDAZA_THREAD"}; ++ unsigned char bRet = 0; ++ gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA] = MsOS_CreateWorkQueueTask(pName2); ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUECMDQ] = MsOS_CreateWorkQueueEvent((void*)SCLIRQ_CMDQIST); ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEDAZA] = MsOS_CreateWorkQueueEvent((void*)SCLIRQ_DazaIST); ++ return bRet; ++} ++irqreturn_t _Drv_SCLIRQ_isr(int eIntNum, void* dev_id) ++{ ++ static MS_U32 u32ActTime[7]; ++ static MS_BOOL bAffFull = 0,bAffcount=0; ++ static MS_BOOL bISPFramePerfect = 0; ++ static MS_BOOL bNonFRMEndCount = 0; ++ MS_U64 u64Flag,u64Mask=0x0; ++ MS_U32 u32DiffTime; ++ u64Mask = gstScldmaInfo.u64mask; ++ u64Flag = Hal_SCLIRQ_Get_Flag(EN_SCLIRQ_SCTOP_0,0xFFFFFFFFFFFF); ++ if(_bSCLIRQ_Suspend) ++ { ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,0xFFFFFFFFFFFF, 1); ++ } ++ ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,(~u64Mask)&u64Flag, 1); ++ gu32Time = ((MS_U32)MsOS_GetSystemTimeStamp()); ++ //u64Flag = _Drv_SCLIRQ_FlagRefine(u64Flag); ++ if(u64Flag &SCLIRQ_MSK_AFF_FULL) ++ { ++ if(u64Flag &(SCLIRQ_MSK_VSYNC_FCLK_LDC|SCLIRQ_MSK_VSYNC_IDCLK)) ++ { ++ // HW bug : aff fifo full error report ++ } ++ else ++ { ++ if((MsOS_GetEvent(_s32SYNCEventId)& E_SCLIRQ_EVENT_BRESETFCLK) ==0) ++ { ++ gstSCInts.u32AffCount++; ++ } ++ _Drv_SCLIRQ_AffFullHandler(&bAffFull, &bAffcount); ++ } ++ } ++ // next frame IN . because of receive and send in same time.(ISP in frame end) ++ // 1.frame coming(vsync) ++ // 2.frame receive done.(irq get sc_frm_in_end)keep in DNR ++ // 3.active from dnr(LDC_trig) ++ if(u64Flag &SCLIRQ_MSK_SC_IN_FRM_END) ++ { ++ _Drv_SCLIRQ_FrameInEndHandler(&bNonFRMEndCount,&bISPFramePerfect,&bAffFull); ++ gstSCInts.u32ISPDoneCount++; ++ u32DiffTime = gu32Time - u32ActTime[5]; ++ gstSCInts.u32ISPTime += u32DiffTime; ++ if(gstSCInts.u32ISPDoneCount > 256) ++ { ++ gstSCInts.u32ISPTime = gstSCInts.u32ISPTime/gstSCInts.u32ISPDoneCount; ++ gstSCInts.u32ISPInCount = (gstSCInts.u32ISPInCount-gstSCInts.u32ISPDoneCount)+1; ++ gstSCInts.u32ISPDoneCount = 1; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[FRMIN]@%lu\n",gu32Time); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_IDCLK) ++ { ++ gstSCInts.u32ISPInCount++; ++ if(MsOS_GetEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID())&(E_SCLIRQ_EVENT_FRMENDSYNC)) ++ { ++ u32DiffTime = gu32Time - u32ActTime[6]; ++ if(!(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END)) ++ { ++ _Drv_SCLIRQ_SetISPBlankingTime(u32DiffTime); ++ } ++ gstSCInts.u32ISPBlanking += u32DiffTime; ++ } ++ _Drv_SCLIRQ_IDCLKVsyncInRealTimeHandler(); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[IDCLK]Flag:%llx @%lu\n",u64Flag,gu32Time); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_SC1_HVSP_FINISH) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[HVSP_FINISH]Flag:%llx @%lu\n",u64Flag,gu32Time); ++ } ++ if(u64Flag &SCLIRQ_MSK_VSYNC_FCLK_LDC) ++ { ++ u32ActTime[5] = gu32Time; ++ _Drv_SCLIRQ_LDCVsyncInRealTimeHandler(); ++ _Drv_SCLIRQ_LDCVsyncInHandler(&bISPFramePerfect,&bAffFull); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE),"[FRMLDC]Flag:%llx @%lu\n",u64Flag,gu32Time); ++ } ++ // SC1 FRM ++ if(u64Flag & SCLIRQ_MSK_SC1_FRM_W_ACTIVE) ++ { ++ u32ActTime[0] = gu32Time; ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_1_FRM_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_1_FRM_W)) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC1FRM|E_SCLIRQ_EVENT_ISTSC1FRM); ++ } ++ gstSCInts.u32SC1FrmDoneCount++; ++ u32DiffTime = gu32Time - u32ActTime[0]; ++ gstSCInts.u32SC1FrmActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC1FrmDoneCount > 256) ++ { ++ gstSCInts.u32SC1FrmActiveTime = gstSCInts.u32SC1FrmActiveTime/gstSCInts.u32SC1FrmDoneCount; ++ gstSCInts.u32SC1FrmDoneCount = 1; ++ } ++ } ++ ++ ++ // SC2 FRM ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM_W_ACTIVE) ++ { ++ u32ActTime[1] = gu32Time; ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_2_FRM_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_2_FRM_W)) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC2FRM|E_SCLIRQ_EVENT_ISTSC2FRM); ++ } ++ gstSCInts.u32SC2FrmDoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[1]; ++ gstSCInts.u32SC2FrmActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC2FrmDoneCount > 256) ++ { ++ gstSCInts.u32SC2FrmActiveTime = gstSCInts.u32SC2FrmActiveTime/gstSCInts.u32SC2FrmDoneCount; ++ gstSCInts.u32SC2FrmDoneCount = 1; ++ } ++ } ++ // SC2 FRM2 ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE) ++ { ++ u32ActTime[2] = gu32Time; ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_2_FRM2_W); ++ } ++ if(u64Flag & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE_N) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_2_FRM2_W)) ++ { ++ MsOS_SetEvent(_s32FRMENDEventId, (E_SCLIRQ_EVENT_SC2FRM2|E_SCLIRQ_EVENT_ISTSC2FRM2)); ++ } ++ else ++ { ++ if(gbsc2frame2reopen && (u64Flag & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE)) ++ { ++ gbsc2frame2reopen = 0; ++ _Drv_SCLIRQ_ReduceDropFrameCount(); ++ } ++ } ++ // for HW bug ++ //gsclirqstate |= (E_SCLIRQ_EVENT_SC2FRM2|E_SCLIRQ_EVENT_ISTSC2FRM2); ++ if(gbsc2frame2reopen) ++ { ++ gbsc2frame2reopen = 0; ++ _Drv_SCLIRQ_ReduceDropFrameCount(); ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "[FRMEND]SC2 FRM2 reopen\n"); ++ _Drv_SCLIRQ_SetDMAOnOffWithoutDoubleBufferHandler(); ++ if((!gbDMADoneEarlyISP) || (gbPtgenMode)) ++ { ++ _Drv_SCLIRQ_CMDQBlankingHandler(); ++ } ++ } ++ gstSCInts.u32SC2Frm2DoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[2]; ++ gstSCInts.u32SC2Frm2ActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC2Frm2DoneCount > 256) ++ { ++ gstSCInts.u32SC2Frm2ActiveTime = gstSCInts.u32SC2Frm2ActiveTime/gstSCInts.u32SC2Frm2DoneCount; ++ gstSCInts.u32SC2Frm2DoneCount = 1; ++ } ++ } ++ ++ // SC1 SNP ++ if(u64Flag & SCLIRQ_MSK_SC1_SNP_W_ACTIVE) ++ { ++ u32ActTime[3] = gu32Time; ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_1_SNP_W); ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N) ++ { ++ if(_Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_1_SNP_W)) ++ { ++ gsclirqstate |= (E_SCLIRQ_EVENT_SC1SNP|E_SCLIRQ_EVENT_ISTSC1SNP); ++ } ++ gstSCInts.u32SC1SnpDoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[3]; ++ gstSCInts.u32SC1SnpActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC1SnpDoneCount > 256) ++ { ++ gstSCInts.u32SC1SnpActiveTime = gstSCInts.u32SC1SnpActiveTime/gstSCInts.u32SC1SnpDoneCount; ++ gstSCInts.u32SC1SnpDoneCount = 1; ++ } ++ } ++ // SC SRC FRMEND ++ if(u64Flag &SCLIRQ_MSK_SC1_ENG_FRM_END) ++ { ++ Drv_SCLIRQ_SetRealTimeFrmEndHandler(gu32Time); ++ Drv_SCLIRQ_SetFrmEndInterruptStatus(gu32Time); ++ _Drv_SCLIRQ_IsAffFullContinually(&bAffFull, &bAffcount); ++ _Drv_SCLIRQ_IsDMAHangUp(u64Flag); ++ bNonFRMEndCount = 0; ++ u32ActTime[6] = gu32Time; ++ gu32FrmEndTime = gu32Time; ++ u32DiffTime = gu32Time -u32ActTime[5]; ++ gstSCInts.u32SCLMainActiveTime += u32DiffTime; ++ if(gstSCInts.u32ISPBlanking) ++ { ++ gstSCInts.u32SCLMainDoneCount++; ++ } ++ if(gstSCInts.u32SCLMainDoneCount > 256) ++ { ++ gstSCInts.u32ISPBlanking = gstSCInts.u32ISPBlankingTime; ++ gstSCInts.u32SCLMainActiveTime = gstSCInts.u32SCLMainActiveTime/gstSCInts.u32SCLMainDoneCount; ++ gstSCInts.u32SCLMainDoneCount = 1; ++ gstSCInts.u8CountReset ++; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_ELSE), ++ "[FRMEND]%x flag:%llx,%lu\n",gsclirqstate,u64Flag,((MS_U32)MsOS_GetSystemTimeStamp())); ++ } ++ ++ // SC3 FRM_W ++ if(u64Flag & SCLIRQ_MSK_SC3_DMA_W_ACTIVE) ++ { ++ gscl3irqstate = E_SCLIRQ_SC3EVENT_CLEAR; ++ gscl3irqstate |= (E_SCLIRQ_SC3EVENT_ACTIVE | E_SCLIRQ_SC3EVENT_ISTACTIVE); ++ _Drv_SCLIRQ_DMAActiveHandler(E_SCLDMA_3_FRM_W); ++ u32ActTime[4] = gu32Time; ++ } ++ ++ if(u64Flag & SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N) ++ { ++ gscl3irqstate |= (E_SCLIRQ_SC3EVENT_ACTIVEN | E_SCLIRQ_SC3EVENT_ISTACTIVEN | E_SCLIRQ_SC3EVENT_IRQ); ++ _Drv_SCLIRQ_DMAActive_NHandler(E_SCLDMA_3_FRM_W); ++ gstSCInts.u32SC3DoneCount++; ++ u32DiffTime = gu32Time -u32ActTime[4]; ++ gstSCInts.u32SC3ActiveTime += u32DiffTime; ++ if(gstSCInts.u32SC3DoneCount > 256) ++ { ++ gstSCInts.u32SC3ActiveTime = gstSCInts.u32SC3ActiveTime/gstSCInts.u32SC3DoneCount; ++ gstSCInts.u32SC3DoneCount = 1; ++ } ++ } ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,(~u64Mask)&u64Flag, 0); ++ u32DiffTime = ((MS_U32)MsOS_GetSystemTimeStamp())-gu32Time; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&(EN_DBGMG_SCLIRQLEVEL_NORMAL), ++ "[ISR]Diff:%lu(ns)\n",u32DiffTime); ++ return IRQ_HANDLED; ++} ++ ++#endif //RTK ++ ++#endif //ENABLE_ACTIVEID_ISR ++ ++ ++void Drv_SCLIRQ_SetDNRLock(MS_BOOL bEn) ++{ ++ Hal_SCLIRQ_SetDNRLock(bEn); ++} ++void Drv_SCLIRQ_SetDropFrameFromCMDQDone(unsigned char u8Count) ++{ ++ #if SCALING_BLOCK ++ #else ++ MS_U32 u32Events; ++ if(Drv_SCLIRQ_GetEachDMAEn()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_CMDQDONE, &u32Events, E_OR, 2000); // get status: CMDQ Done ++ } ++ #endif ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ if(gstDropFrameCount<=u8Count) ++ { ++ gstDropFrameCount = u8Count; ++ } ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++} ++void Drv_SCLIRQ_SetDropFrameFromISP(unsigned char u8Count) ++{ ++ SCL_ERR("[SCLIRQ]ISP drop Frame Count:%hhd \n",u8Count); ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ if(gstDropFrameCount<=u8Count) ++ { ++ gstDropFrameCount = u8Count; ++ } ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++} ++void Drv_SCLIRQ_SetDAZAQueueWorkISR(SCLIRQDAZAEvent enEvent) ++{ ++ if(!(genDAZAEvent&enEvent)) ++ { ++ DRV_SCLIRQ_MUTEX_LOCK_ISR(); ++ genDAZAEvent |= enEvent; ++ DRV_SCLIRQ_MUTEX_UNLOCK_ISR(); ++ MsOS_QueueWork(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA], ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEDAZA],0); ++ } ++} ++void Drv_SCLIRQ_SetDAZAQueueWork(SCLIRQDAZAEvent enEvent) ++{ ++ if(!(genDAZAEvent&enEvent)) ++ { ++ genDAZAEvent |= enEvent; ++ MsOS_QueueWork(1,gstThreadCfg.s32Taskid[EN_SCLIRQ_SCTASKID_DAZA], ++ gstThreadCfg.s32HandlerId[EN_SCLIRQ_SCTASK_WORKQUEUEDAZA],0); ++ } ++} ++MS_BOOL Drv_SCLIRQ_InitVariable(void) ++{ ++ MS_U64 u64Flag; ++#if (ENABLE_ISR) ++ MsOS_Memset(&gstSCLIrqInfo, 0, sizeof(ST_SCLIRQ_IFNO_TYPE)); ++#endif ++ gsclirqstate = E_SCLIRQ_EVENT_CLEAR; ++ gscl3irqstate = E_SCLIRQ_SC3EVENT_CLEAR; ++ _bSCLIRQ_Suspend = 0; ++ gbFRMInFlag = 0; ++ gbPtgenMode = 0; ++ gbDMADoneEarlyISP = 0; ++ genDAZAEvent = E_SCLIRQ_DAZA_OFF; ++ gbMonitorCropMode = 0; ++ gbEachDMAEnable = 0; ++ gbBypassDNR = 0; ++ gstDropFrameCount = 0; ++ gbsc2frame2reopen = 0; ++ gu32FrmEndTime = 0; ++ MsOS_Memset(&gstDmaHang,0x0,sizeof(ST_SCLIRQ_DMAHANG_CNT)); ++ MsOS_Memset(&gstSCInts,0x0,sizeof(ST_SCLIRQ_SCINTS_TYPE)); ++ _Drv_SCLIRQ_SetIsBlankingRegion(1); ++ ++ MsOS_ClearEventIRQ(_s32SYNCEventId,0xFFFFFFFF); ++ MsOS_ClearEventIRQ(_s32FRMENDEventId,0xFFFFFFFF); ++ MsOS_ClearEventIRQ(_s32SC3EventId,0xFFFFFFFF); ++ u64Flag = Hal_SCLIRQ_Get_Flag(EN_SCLIRQ_SCTOP_0,0xFFFFFFFFFF); ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,u64Flag, 1); ++ Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_0,u64Flag, 0); ++ return TRUE; ++} ++void Drv_SCLIRQ_SetPTGenStatus(MS_BOOL bPTGen) ++{ ++ DRV_SCLIRQ_MUTEX_LOCK(); ++ gbPtgenMode = bPTGen; ++ if(bPTGen) ++ { ++ gbFRMInFlag = 0xF; ++ } ++ DRV_SCLIRQ_MUTEX_UNLOCK(); ++} ++void Drv_SCLIRQ_SetDMADoneEarlyISP(MS_BOOL bDMADoneEarlyISP) ++{ ++ // LDC patch open,crop open, ++ gbDMADoneEarlyISP = bDMADoneEarlyISP; ++} ++ ++void Drv_SCLIRQ_Set_Checkcropflag(MS_BOOL bcheck) ++{ ++ DRV_SCLIRQ_MUTEX_LOCK(); ++ gbMonitorCropMode = bcheck; ++ DRV_SCLIRQ_MUTEX_UNLOCK(); ++} ++MS_U8 Drv_SCLIRQ_Get_Checkcropflag(void) ++{ ++ return gbMonitorCropMode; ++} ++MS_U8 Drv_SCLIRQ_GetEachDMAEn(void) ++{ ++ return gbEachDMAEnable; ++} ++MS_U8 Drv_SCLIRQ_GetISPIN(void) ++{ ++ return ((MsOS_GetEvent(_s32SYNCEventId)&E_SCLIRQ_EVENT_LDCSYNC)? 1 : 0); ++} ++ST_SCLIRQ_SCINTS_TYPE* Drv_SCLIRQ_GetSCLInts(void) ++{ ++ return &gstSCInts; ++} ++ ++MS_BOOL Drv_SCLIRQ_Init(ST_SCLIRQ_INIT_CONFIG *pCfg) ++{ ++ char mutx_word[] = {"_SCLIRQ_Mutex"}; ++ ++ MS_U8 i; ++ ++ if(_SCLIRQ_Mutex != -1) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, "[DRVSCLIRQ]%s(%d)::Already Done\n", __FUNCTION__, __LINE__); ++ return TRUE; ++ } ++ ++ if(MsOS_Init() == FALSE) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d)::MsOS_Init Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ _SCLIRQ_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, mutx_word, MSOS_PROCESS_SHARED); ++ _pSCLIRQ_SCLDMA_Mutex = Drv_SCLDMA_GetDMAandIRQCommonMutex(); ++ if (_SCLIRQ_Mutex == -1) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d)::Create Mutex Flag Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ ++ Hal_SCLIRQ_Set_Riu_Base(pCfg->u32RiuBase); ++ ++ // disable all interrupt first ++ for(i=0; iu32IRQNUM; ++ if(MsOS_AttachInterrupt((InterruptNum)pCfg->u32IRQNUM, (InterruptCb)_Drv_SCLIRQ_isr ,IRQF_DISABLED, "SCLINTR")) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d):: Request IRQ Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ MsOS_DisableInterrupt((InterruptNum)pCfg->u32IRQNUM); ++ MsOS_EnableInterrupt((InterruptNum)pCfg->u32IRQNUM); ++ _Create_SCLIRQ_IST(); ++#endif ++#if (ENABLE_CMDQ_ISR) ++ Drv_CMDQ_InitRIUBase(pCfg->u32RiuBase); ++ if(MsOS_AttachInterrupt((InterruptNum)pCfg->u32CMDQIRQNUM, (InterruptCb)_Drv_SCLIRQ_CMDQ_isr ,NULL, "CMDQINTR")) ++ { ++ DRV_SCLIRQ_ERR(printf("[DRVSCLIRQ]%s(%d):: Request IRQ Fail\n", __FUNCTION__, __LINE__)); ++ return FALSE; ++ } ++ gu32CMDQIRQNUM = pCfg->u32CMDQIRQNUM; ++ MsOS_DisableInterrupt((InterruptNum)pCfg->u32CMDQIRQNUM); ++ MsOS_EnableInterrupt((InterruptNum)pCfg->u32CMDQIRQNUM); ++ Drv_CMDQ_SetISRStatus(1); ++#endif ++ ++ ++ return TRUE; ++} ++void * Drv_SCLIRQ_GetWaitQueueHead(MS_U32 enID) ++{ ++ if(enID == E_SCLDMA_ID_3_W) ++ { ++ return MsOS_GetEventQueue(_s32SC3EventId); ++ } ++ else ++ { ++ return MsOS_GetEventQueue(_s32FRMENDEventId); ++ } ++} ++ ++void * Drv_SCLIRQ_GetSyncQueue(void) ++{ ++ return MsOS_GetEventQueue(_s32SYNCEventId); ++} ++ ++MS_S32 Drv_SCLIRQ_Get_IRQ_EventID(void) ++{ ++ return _s32FRMENDEventId; ++} ++MS_S32 Drv_SCLIRQ_Get_IRQ_SYNCEventID(void) ++{ ++ return _s32SYNCEventId; ++} ++MS_S32 Drv_SCLIRQ_Get_IRQ_SC3EventID(void) ++{ ++ return _s32SC3EventId; ++} ++ ++MS_BOOL Drv_SCLIRQ_Suspend(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, "%s(%d), bSuspend=%d\n", __FUNCTION__, __LINE__, _bSCLIRQ_Suspend); ++ _bSCLIRQ_Suspend = 1; ++ _Drv_SCLIRQ_SetIsBlankingRegion(1); ++ return TRUE; ++} ++ ++MS_BOOL Drv_SCLIRQ_Resume(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg) ++{ ++ MS_U16 i; ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_NORMAL, "%s(%d), bResume=%d\n", __FUNCTION__, __LINE__, _bSCLIRQ_Suspend); ++ ++ if(_bSCLIRQ_Suspend == 1) ++ { ++ // disable all interrupt first ++ for(i=0; i ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_SCLIRQ_H ++#define _DRV_SCLIRQ_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Enum ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++ MS_U32 u32IRQNUM; ++ MS_U32 u32CMDQIRQNUM; ++}ST_SCLIRQ_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32IRQNUM; ++ MS_U32 u32CMDQIRQNUM; ++}ST_SCLIRQ_SUSPEND_RESUME_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_SCLIRQ_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void * Drv_SCLIRQ_GetWaitQueueHead(MS_U32 enID); ++INTERFACE void Drv_SCLIRQ_SetPTGenStatus(MS_BOOL bPTGen); ++INTERFACE void Drv_SCLIRQ_SetDMADoneEarlyISP(MS_BOOL bDMADoneEarlyISP); ++INTERFACE void Drv_SCLIRQ_Set_Checkcropflag(MS_BOOL bcheck); ++INTERFACE MS_U8 Drv_SCLIRQ_Get_Checkcropflag(void); ++INTERFACE MS_U8 Drv_SCLIRQ_GetEachDMAEn(void); ++INTERFACE MS_U8 Drv_SCLIRQ_GetISPIN(void); ++INTERFACE ST_SCLIRQ_SCINTS_TYPE* Drv_SCLIRQ_GetSCLInts(void); ++INTERFACE void Drv_SCLIRQ_SetDropFrameFromCMDQDone(unsigned char u8Count); ++INTERFACE void Drv_SCLIRQ_SetDropFrameFromISP(unsigned char u8Count); ++INTERFACE void Drv_SCLIRQ_SetDAZAQueueWork(SCLIRQDAZAEvent enEvent); ++INTERFACE void Drv_SCLIRQ_SetDAZAQueueWorkISR(SCLIRQDAZAEvent enEvent); ++INTERFACE void Drv_SCLIRQ_SetDNRLock(MS_BOOL bEn); ++ ++INTERFACE MS_BOOL Drv_SCLIRQ_InitVariable(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_GetIsBlankingRegion(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_GetIsVIPBlankingRegion(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_Init(ST_SCLIRQ_INIT_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLIRQ_Exit(void); ++INTERFACE MS_BOOL Drv_SCLIRQ_InterruptEnable(MS_U16 u16IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Disable(MS_U16 u16IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Get_Flag(MS_U16 u16IRQ, MS_U64 *pFlag); ++INTERFACE MS_BOOL Drv_SCLIRQ_Set_Clear(MS_U16 u16IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Get_Flags_Msk(MS_U64 u64IrqMsk, MS_U64 *pFlags); ++INTERFACE MS_BOOL Drv_SCLIRQ_Set_Clear_Msk(MS_U64 u64IrqMsk); ++INTERFACE MS_BOOL Drv_SCLIRQ_Set_Mask(MS_U64 u64IRQ); ++INTERFACE MS_BOOL Drv_SCLIRQ_Suspend(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_BOOL Drv_SCLIRQ_Resume(ST_SCLIRQ_SUSPEND_RESUME_CONFIG *pCfg); ++INTERFACE MS_S32 Drv_SCLIRQ_Get_IRQ_EventID(void); ++INTERFACE MS_S32 Drv_SCLIRQ_Get_IRQ_SYNCEventID(void); ++INTERFACE MS_S32 Drv_SCLIRQ_Get_IRQ_SC3EventID(void); ++INTERFACE void * Drv_SCLIRQ_GetSyncQueue(void); ++INTERFACE void scl_ve_isr(void); ++INTERFACE void scl_vs_isr(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/sclirq/drvsclirq_st.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/sclirq/drvsclirq_st.h +new file mode 100644 +index 00000000..7df8963d +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/sclirq/drvsclirq_st.h +@@ -0,0 +1,424 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef DRV_SCLIRQ_ST_H ++#define DRV_SCLIRQ_ST_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & enum ++//------------------------------------------------------------------------------------------------- ++#define SCLIRQ_MSK_SC_IN_FRM_END (((MS_U64)1)<<0) ++#define SCLIRQ_MSK_SC3_ENG_FRM_END (((MS_U64)1)<<1) ++#define SCLIRQ_MSK_SC1_ENG_FRM_END (((MS_U64)1)<<2) ++#define SCLIRQ_MSK_DISP_DMA_END (((MS_U64)1)<<3) ++#define SCLIRQ_MSK_VSYNC_IDCLK (((MS_U64)1)<<4) ++#define SCLIRQ_MSK_VSYNC_FCLK (((MS_U64)1)<<5) ++#define SCLIRQ_MSK_VSYNC_SC1_HVSP_FINISH (((MS_U64)1)<<6) ++#define SCLIRQ_MSK_SC1_FRM_W_ACTIVE (((MS_U64)1)<<7) ++#define SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N (((MS_U64)1)<<8) ++#define SCLIRQ_MSK_SC1_SNP_W_ACTIVE (((MS_U64)1)<<9) ++#define SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N (((MS_U64)1)<<10) ++#define SCLIRQ_MSK_SC1_SNPI_W_ACTIVE (((MS_U64)1)<<11) ++#define SCLIRQ_MSK_SC1_SNPI_W_ACTIVE_N (((MS_U64)1)<<12) ++#define SCLIRQ_MSK_TRIG_LDC (((MS_U64)1)<<13) ++#define SCLIRQ_MSK_AFF_FULL (((MS_U64)1)<<14) ++#define SCLIRQ_MSK_VIP_HIST_DONE (((MS_U64)1)<<15) ++#define SCLIRQ_MSK_SC1_DBG_R_ACTIVE (((MS_U64)1)<<17) ++#define SCLIRQ_MSK_SC1_DBG_R_ACTIVE_N (((MS_U64)1)<<18) ++#define SCLIRQ_MSK_TTL_VS (((MS_U64)1)<<19) ++#define SCLIRQ_MSK_TTL_VDE (((MS_U64)1)<<20) ++#define SCLIRQ_MSK_TTL_VDE_N (((MS_U64)1)<<21) ++#define SCLIRQ_MSK_TRIG_DBG (((MS_U64)1)<<22) ++#define SCLIRQ_MSK_SC2_FRM_W_ACTIVE (((MS_U64)1)<<23) ++#define SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N (((MS_U64)1)<<24) ++#define SCLIRQ_MSK_SC2_FRMI_W_ACTIVE (((MS_U64)1)<<25) ++#define SCLIRQ_MSK_SC2_FRMI_W_ACTIVE_N (((MS_U64)1)<<26) ++#define SCLIRQ_MSK_SC2_HVSP_FINISH (((MS_U64)1)<<27) ++#define SCLIRQ_MSK_VSYNC_FCLK2 (((MS_U64)1)<<28) ++#define SCLIRQ_MSK_SC3_HVSP_FINISH (((MS_U64)1)<<29) ++#define SCLIRQ_MSK_TRIG_SC3_DMA_R (((MS_U64)1)<<30) ++#define SCLIRQ_MSK_SC3_DMA_R_ACTIVE (((MS_U64)1)<<31) ++#define SCLIRQ_MSK_SC3_DMA_R_ACTIVE_N (((MS_U64)1)<<32) ++#define SCLIRQ_MSK_SC3_DMA_W_ACTIVE (((MS_U64)1)<<33) ++#define SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N (((MS_U64)1)<<34) ++#define SCLIRQ_MSK_VSYNC_FCLK_LDC (((MS_U64)1)<<35) ++#define SCLIRQ_MSK_SC2_FRM2_W_ACTIVE_N (((MS_U64)1)<<36) ++#define SCLIRQ_MSK_SC2_FRM2_W_ACTIVE (((MS_U64)1)<<37) ++ ++#define SCLIRQ_SC_IN_FRM_END 0 ++#define SCLIRQ_SC3_ENG_FRM_END 1 ++#define SCLIRQ_SC1_ENG_FRM_END 2 ++#define SCLIRQ_DISP_DMA_END 3 ++#define SCLIRQ_VSYNC_IDCLK 4 ++#define SCLIRQ_VSYNC_FCLK 5 ++#define SCLIRQ_SC1_HVSP_FINISH 6 ++#define SCLIRQ_SC1_FRM_W_ACTIVE 7 ++#define SCLIRQ_SC1_FRM_W_ACTIVE_N 8 ++#define SCLIRQ_SC1_SNP_W_ACTIVE 9 ++#define SCLIRQ_SC1_SNP_W_ACTIVE_N 10 ++#define SCLIRQ_SC1_SNPI_W_ACTIVE 11 ++#define SCLIRQ_SC1_SNPI_W_ACTIVE_N 12 ++#define SCLIRQ_TRIG_LDC 13 ++#define SCLIRQ_AFF_FULL 14 ++#define SCLIRQ_VIP_HIST_DONE 15 ++#define SCLIRQ_RESERVED_00 16 ++#define SCLIRQ_SC1_DBG_R_ACTIVE 17 ++#define SCLIRQ_SC1_DBG_R_ACTIVE_N 18 ++#define SCLIRQ_TTL_VS 19 ++#define SCLIRQ_TTL_VDE 20 ++#define SCLIRQ_TTL_VDE_N 21 ++#define SCLIRQ_TRIG_DBG 22 ++#define SCLIRQ_SC2_FRM_W_ACTIVE 23 ++#define SCLIRQ_SC2_FRM_W_ACTIVE_N 24 ++#define SCLIRQ_SC2_FRMI_W_ACTIVE 25 ++#define SCLIRQ_SC2_FRMI_W_ACTIVE_N 26 ++#define SCLIRQ_SC2_HVSP_FINISH 27 ++#define SCLIRQ_VSYNC_FCLK2 28 ++#define SCLIRQ_SC3_HVSP_FINISH 29 ++#define SCLIRQ_TRIG_SC3_DMA_R 30 ++#define SCLIRQ_SC3_DMA_R_ACTIVE 31 ++#define SCLIRQ_SC3_DMA_R_ACTIVE_N 32 ++#define SCLIRQ_SC3_DMA_W_ACTIVE 33 ++#define SCLIRQ_SC3_DMA_W_ACTIVE_N 34 ++#define SCLIRQ_VSYNC_FCLK_LDC 35 ++#define SCLIRQ_SC2_FRM2_W_ACTIVE 36 ++#define SCLIRQ_SC2_FRM2_W_ACTIVE_N 37 ++#define SCLIRQ_RESERVED 48 ++#define SCLIRQ_NUM 48 //I1 interrupt ++ ++ ++ ++#define SCLIRQ_ISTEVENT_BASE 0x10 ++ ++ ++ ++ ++ ++#define PARSING_IRQ_MSK(x) ( (x & SCLIRQ_MSK_SC_IN_FRM_END ) ? "SCLIRQ_MSK_SC_IN_FRM_END " : \ ++ (x & SCLIRQ_MSK_SC3_ENG_FRM_END ) ? "SCLIRQ_MSK_SC3_ENG_FRM_END " : \ ++ (x & SCLIRQ_MSK_SC1_ENG_FRM_END ) ? "SCLIRQ_MSK_SC1_ENG_FRM_END " : \ ++ (x & SCLIRQ_MSK_DISP_DMA_END ) ? "SCLIRQ_MSK_DISP_DMA_END " : \ ++ (x & SCLIRQ_MSK_SC1_FRM_W_ACTIVE ) ? "SCLIRQ_MSK_SC1_FRM_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC1_FRM_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC1_SNP_W_ACTIVE ) ? "SCLIRQ_MSK_SC1_SNP_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC1_SNP_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC1_SNPI_W_ACTIVE ) ? "SCLIRQ_MSK_SC1_SNPI_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_SNPI_W_ACTIVE_N) ? "SCLIRQ_MSK_SC1_SNPI_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_TRIG_LDC ) ? "SCLIRQ_MSK_TRIG_LDC " : \ ++ (x & SCLIRQ_MSK_AFF_FULL ) ? "SCLIRQ_MSK_AFF_FULL " : \ ++ (x & SCLIRQ_MSK_VIP_HIST_DONE ) ? "SCLIRQ_MSK_VIP_HIST_DONE " : \ ++ (x & SCLIRQ_MSK_SC1_DBG_R_ACTIVE ) ? "SCLIRQ_MSK_SC1_DBG_R_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC1_DBG_R_ACTIVE_N ) ? "SCLIRQ_MSK_SC1_DBG_R_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_TTL_VS ) ? "SCLIRQ_MSK_TTL_VS " : \ ++ (x & SCLIRQ_MSK_TTL_VDE ) ? "SCLIRQ_MSK_TTL_VDE " : \ ++ (x & SCLIRQ_MSK_TTL_VDE_N ) ? "SCLIRQ_MSK_TTL_VDE_N " : \ ++ (x & SCLIRQ_MSK_TRIG_DBG ) ? "SCLIRQ_MSK_TRIG_DBG " : \ ++ (x & SCLIRQ_MSK_SC2_FRM_W_ACTIVE ) ? "SCLIRQ_MSK_SC2_FRM_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC2_FRM_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC2_FRMI_W_ACTIVE ) ? "SCLIRQ_MSK_SC2_FRMI_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC2_FRMI_W_ACTIVE_N) ? "SCLIRQ_MSK_SC2_FRMI_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC2_HVSP_FINISH ) ? "SCLIRQ_MSK_SC2_HVSP_FINISH " : \ ++ (x & SCLIRQ_MSK_VSYNC_FCLK2 ) ? "SCLIRQ_MSK_VSYNC_FCLK2 " : \ ++ (x & SCLIRQ_MSK_SC3_HVSP_FINISH ) ? "SCLIRQ_MSK_SC3_HVSP_FINISH " : \ ++ (x & SCLIRQ_MSK_TRIG_SC3_DMA_R ) ? "SCLIRQ_MSK_TRIG_SC3_DMA_R " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_R_ACTIVE ) ? "SCLIRQ_MSK_SC3_DMA_R_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_R_ACTIVE_N ) ? "SCLIRQ_MSK_SC3_DMA_R_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_W_ACTIVE ) ? "SCLIRQ_MSK_SC3_DMA_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC3_DMA_W_ACTIVE_N " : \ ++ (x & SCLIRQ_MSK_VSYNC_FCLK_LDC ) ? "SCLIRQ_MSK_VSYNC_FCLK_LDC " : \ ++ (x & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE ) ? "SCLIRQ_MSK_SC2_FRM2_W_ACTIVE " : \ ++ (x & SCLIRQ_MSK_SC2_FRM2_W_ACTIVE_N ) ? "SCLIRQ_MSK_SC2_FRM2_W_ACTIVE_N " : \ ++ "UNKNOWN") ++#define _IsFlagType(u8client,u8type) (gstScldmaInfo.bDmaflag[(u8client)] & (u8type)) ++#define _SetANDGetFlagType(u8client,u8Set,u8get) (gstScldmaInfo.bDmaflag[(u8client)]=((gstScldmaInfo.bDmaflag[(u8client)]&(u8get))|(u8Set))) ++#define _SetFlagType(u8client,u8type) (gstScldmaInfo.bDmaflag[(u8client)] |= (u8type)) ++#define _ReSetFlagType(u8client,u8type) (gstScldmaInfo.bDmaflag[(u8client)] &= ~(u8type)) ++#define _GetIdxType(u8client,u8type) (gstScldmaInfo.bDMAidx[(u8client)] & (u8type)) ++#define _SetANDGetIdxType(u8client,u8Set,u8get) (gstScldmaInfo.bDMAidx[(u8client)]=((gstScldmaInfo.bDMAidx[(u8client)]&(u8get))|(u8Set))) ++#define _SetIdxType(u8client,u8type) (gstScldmaInfo.bDMAidx[(u8client)] |= (u8type)) ++#define _ReSetIdxType(u8client,u8type) (gstScldmaInfo.bDMAidx[(u8client)] &= ~(u8type)) ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_SCLIRQ_EVENT_CLEAR = 0x00000000, // no event ++ E_SCLIRQ_EVENT_SC1FRM = 0x00000001, // SC1FRM done (for scldma done,avoid flag to update but not poll,keep it status) ++ E_SCLIRQ_EVENT_SC1SNP = 0x00000002, // SC1SNP done ++ E_SCLIRQ_EVENT_SC1 = (E_SCLIRQ_EVENT_SC1SNP|E_SCLIRQ_EVENT_SC1FRM), // SC1all done ++ E_SCLIRQ_EVENT_SC2FRM = 0x00000004, // SC2 FRM done ++ E_SCLIRQ_EVENT_SC2FRM2 = 0x00000008, // SC2 FRM2 done ++ E_SCLIRQ_EVENT_SC2 = (E_SCLIRQ_EVENT_SC2FRM|E_SCLIRQ_EVENT_SC2FRM2), // SC2all done ++ E_SCLIRQ_EVENT_FRMEND = (E_SCLIRQ_EVENT_SC2|E_SCLIRQ_EVENT_SC1), // SC1 &SC2 done ++ E_SCLIRQ_EVENT_IRQ = 0x00002000, // any one FRM done ++ E_SCLIRQ_EVENT_ISTSC1FRM = 0x00000010, // SC1FRM done for IST ++ E_SCLIRQ_EVENT_ISTSC1SNP = 0x00000020, // SC1SNP done for IST ++ E_SCLIRQ_EVENT_ISTSC1 = (E_SCLIRQ_EVENT_ISTSC1FRM|E_SCLIRQ_EVENT_ISTSC1SNP), // SC1all done for IST ++ E_SCLIRQ_EVENT_ISTSC2FRM = 0x00000040, // SC2 FRM done for IST ++ E_SCLIRQ_EVENT_ISTSC2FRM2 = 0x00000080, // SC2 FRM done for IST ++ E_SCLIRQ_EVENT_ISTSC2 = (E_SCLIRQ_EVENT_ISTSC2FRM|E_SCLIRQ_EVENT_ISTSC2FRM2), // SC1all done for IST ++ E_SCLIRQ_EVENT_ISTFRMEND = (E_SCLIRQ_EVENT_ISTSC2|E_SCLIRQ_EVENT_ISTSC1), // SC1 &SC2 done for IST ++ E_SCLIRQ_EVENT_SC1RESTART = 0x00000100, // SC1 FRM re-start ++ E_SCLIRQ_EVENT_SNPRESTART = 0x00000200, // SC2 FRM re-start ++ E_SCLIRQ_EVENT_SC2RESTART = 0x00000400, // SC1 FRM re-start ++ E_SCLIRQ_EVENT_FRM2RESTART = 0x00000800, // SC2 FRM re-start ++ E_SCLIRQ_EVENT_ALLRESEART = (E_SCLIRQ_EVENT_SC2RESTART|E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_SNPRESTART|E_SCLIRQ_EVENT_FRM2RESTART), // SC1 SC2 restart ++ E_SCLIRQ_EVENT_RESUME = 0x00004000, // Suspend/Resume ++ E_SCLIRQ_EVENT_HVSPST = 0x00008000, ++ E_SCLIRQ_EVENT_SET = 0x00001000, ++ E_SCLIRQ_EVENT_SC1RE = (E_SCLIRQ_EVENT_SC1RESTART | E_SCLIRQ_EVENT_RESUME | E_SCLIRQ_EVENT_SNPRESTART), ++ E_SCLIRQ_EVENT_SC2RE = (E_SCLIRQ_EVENT_SC2RESTART | E_SCLIRQ_EVENT_RESUME | E_SCLIRQ_EVENT_FRM2RESTART), ++ E_SCLIRQ_EVENT_SC1POLL = (E_SCLIRQ_EVENT_SC1|E_SCLIRQ_EVENT_SC1RESTART|E_SCLIRQ_EVENT_RESUME | E_SCLIRQ_EVENT_SNPRESTART), ++ E_SCLIRQ_EVENT_SC2POLL = (E_SCLIRQ_EVENT_SC2|E_SCLIRQ_EVENT_SC2RESTART|E_SCLIRQ_EVENT_RESUME | E_SCLIRQ_EVENT_FRM2RESTART), ++ E_SCLIRQ_EVENT_ALLPOLL = (E_SCLIRQ_EVENT_FRMEND|E_SCLIRQ_EVENT_ALLRESEART|E_SCLIRQ_EVENT_RESUME), ++} SCLIRQTXEvent; ++ ++typedef enum ++{ ++ E_SCLIRQ_SC3EVENT_CLEAR = 0x00000000, // no event ++ E_SCLIRQ_SC3EVENT_ACTIVE = 0x00000001, // SC3FRM act ++ E_SCLIRQ_SC3EVENT_ACTIVEN = 0x00000002, // SC3FRM act_N ++ E_SCLIRQ_SC3EVENT_END = 0x00000003, ++ E_SCLIRQ_SC3EVENT_DONE = 0x00000004, // SC3FRM done ++ E_SCLIRQ_SC3EVENT_IRQ = 0x00000008, // any one ISR need to handle ++ E_SCLIRQ_SC3EVENT_ISTACTIVE = 0x00000010, // SC3 FRM act for IST ++ E_SCLIRQ_SC3EVENT_ISTACTIVEN = 0x00000020, // SC3 done for IST ++ E_SCLIRQ_SC3EVENT_ISTDONE = 0x00000030, // SC3 done for IST ++ E_SCLIRQ_SC3EVENT_RESTART = 0x00000100, // SC3 FRM re-start ++ E_SCLIRQ_SC3EVENT_RESUME = 0x00000400, // Suspend/Resume ++ E_SCLIRQ_SC3EVENT_HVSPST = 0x00000800, ++ E_SCLIRQ_SC3EVENT_ISTCLEAR = (E_SCLIRQ_SC3EVENT_IRQ | E_SCLIRQ_SC3EVENT_ISTDONE | E_SCLIRQ_SC3EVENT_END), ++ E_SCLIRQ_SC3EVENT_POLL = (E_SCLIRQ_SC3EVENT_HVSPST | E_SCLIRQ_SC3EVENT_DONE|E_SCLIRQ_SC3EVENT_RESTART|E_SCLIRQ_SC3EVENT_RESUME), ++} SCLIRQSC3Event; ++ ++typedef enum ++{ ++ E_SCLIRQ_EVENT_SYNC = 0x00000001, // Ldc trig ++ E_SCLIRQ_EVENT_FRMENDSYNC = 0x00000002, // frame end ++ E_SCLIRQ_EVENT_ISPFRMEND = 0x00000004, // ISP frame end ++ E_SCLIRQ_EVENT_LDCSYNC = 0x00000008, // frame start ++ E_SCLIRQ_EVENT_CMDQGOING = 0x00000010, // CMDQ going ++ E_SCLIRQ_EVENT_CMDQIDLE = 0x00000020, // CMDQ idle ++ E_SCLIRQ_EVENT_CMDQDONE = 0x00000040, // CMDQ done ++ E_SCLIRQ_EVENT_CMDQFIRE = 0x00000080, // CMDQ done ++ E_SCLIRQ_EVENT_CMDQ = (E_SCLIRQ_EVENT_CMDQGOING|E_SCLIRQ_EVENT_CMDQIDLE|E_SCLIRQ_EVENT_CMDQDONE), ++ E_SCLIRQ_EVENT_GAMMA_Y = 0x00000100, // YUVGAMMA, ++ E_SCLIRQ_EVENT_GAMMA_U = 0x00000200, // YUVGAMMA, ++ E_SCLIRQ_EVENT_GAMMA_V = 0x00000400, // YUVGAMMA, ++ E_SCLIRQ_EVENT_GM10to12_R = 0x00000800, // RGBGAMMA, ++ E_SCLIRQ_EVENT_GM10to12_G = 0x00001000, // RGBGAMMA, ++ E_SCLIRQ_EVENT_GM10to12_B = 0x00002000, // RGBGAMMA, ++ E_SCLIRQ_EVENT_GM12to10_R = 0x00004000, // RGBGAMMA, ++ E_SCLIRQ_EVENT_GM12to10_G = 0x00008000, // RGBGAMMA, ++ E_SCLIRQ_EVENT_GM12to10_B = 0x00010000, // RGBGAMMA, ++ E_SCLIRQ_EVENT_VIP = 0x00020000, // VIP, ++ E_SCLIRQ_EVENT_SC1HSRAMSET = 0x00040000, ++ E_SCLIRQ_EVENT_SC2HSRAMSET = 0x00080000, ++ E_SCLIRQ_EVENT_SC3HSRAMSET = 0x00100000, ++ E_SCLIRQ_EVENT_SC1VSRAMSET = 0x00200000, ++ E_SCLIRQ_EVENT_SC2VSRAMSET = 0x00400000, ++ E_SCLIRQ_EVENT_SC3VSRAMSET = 0x00800000, ++ E_SCLIRQ_EVENT_BRESETFCLK = 0x01000000, ++ E_SCLIRQ_EVENT_BCLOSECIIR = 0x02000000, ++ E_SCLIRQ_EVENT_BRESETDNR = 0x04000000, ++ E_SCLIRQ_EVENT_SETDELAY = 0x08000000, ++ E_SCLIRQ_EVENT_SETCHANGESIZE = 0x10000000, ++ E_SCLIRQ_EVENT_CHANGESIZEDONE = 0x20000000, ++}SCLIRQRXEvent; ++typedef enum ++{ ++ E_SCLIRQ_DAZA_OFF = 0x00000000, ++ E_SCLIRQ_DAZA_BRESETFCLK = 0x00000001, ++ E_SCLIRQ_DAZA_BCLOSECIIR = 0x00000002, ++ E_SCLIRQ_DAZA_BCLOSELDCP = 0x00000004, ++ E_SCLIRQ_DAZA_BRESETLDCP = 0x00000008, ++}SCLIRQDAZAEvent; ++ ++typedef enum ++{ ++ E_SCLIRQ_FRM_IN_COUNT_NOW = 0x1, // FRAMEIN NOW ++ E_SCLIRQ_FRM_IN_COUNT_DELAYONE = 0x2, // delay one ++ E_SCLIRQ_FRM_IN_COUNT_DELAYTWO = 0x4, // delay two ++}E_SCLIRQ_FRM_IN_COUNT_TYPE; ++ ++typedef enum ++{ ++ EN_SCLIRQ_SCTOP_0 = 0, // sc_top_int ++ EN_SCLIRQ_SCTOP_1 = 1, // sc1_top ++ EN_SCLIRQ_SCTOP_2 = 2, // sc2_top ++ EN_SCLIRQ_SCTOP_NUM, ++}EN_SCLIRQ_SCTOP_TYPE; ++typedef enum ++{ ++ EN_SCLIRQ_SCTASKID_DAZA = 0, // sc_top_int ++ EN_SCLIRQ_SCTASKID_IRQ = 1, // sc1_top ++ EN_SCLIRQ_SCTASKID_MAX, ++}EN_SCLIRQ_SCTASKID_TYPE; ++ ++typedef enum ++{ ++ EN_SCLIRQ_SCTASK_TASKLETSCTOP = 0, // sc_top_int ++ EN_SCLIRQ_SCTASK_WORKQUEUECMDQ = 1, // sc1_top ++ EN_SCLIRQ_SCTASK_TASKLETSC3 = 2, // sc3 ++ EN_SCLIRQ_SCTASK_WORKQUEUEDAZA = 3, // sc1_top ++ EN_SCLIRQ_SCTASK_WORKQUEUEIRQ = 4, // sc1_top ++ EN_SCLIRQ_SCTASK_MAX, ++}EN_SCLIRQ_SCTASK_TYPE; ++ ++typedef enum ++{ ++ EN_SCLIRQ_SCIRQ_INFRMEND = 0, // sc_top_int ++ EN_SCLIRQ_SCIRQ_FCLKLDC = 1, // sc1_top ++ EN_SCLIRQ_SCIRQ_AFFFULL = 2, // sc3 ++ EN_SCLIRQ_SCIRQ_SC1FRMWACTIVE = 3, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC1FRMWACTIVE_N = 4, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC1SNPWACTIVE = 5, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC1SNPWACTIVE_N = 6, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC2FRMWACTIVE = 7, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC2FRMWACTIVE_N = 8, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC2FRM2WACTIVE = 9, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC2FRM2WACTIVE_N = 10, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC3FRMWACTIVE = 11, // sc1_top ++ EN_SCLIRQ_SCIRQ_SC3FRMWACTIVE_N = 12, // sc1_top ++ EN_SCLIRQ_SCIRQ_SCTOPFRMEND = 13, // sc1_top ++ EN_SCLIRQ_SCIRQ_CMDQ0TRIG = 14, // cmdq0_top ++ EN_SCLIRQ_SCIRQ_CMDQ0DONE = 15, // cmdq0_top ++ EN_SCLIRQ_SCIRQ_MAX, ++}EN_SCLIRQ_SCIRQ_TYPE; ++ ++typedef struct ++{ ++ MS_U32 u32AffCount; ++ MS_U32 u32ISPInCount; ++ MS_U32 u32ISPDoneCount; ++ MS_U32 u32SC1FrmDoneCount; ++ MS_U32 u32SC1SnpDoneCount; ++ MS_U32 u32SC2FrmDoneCount; ++ MS_U32 u32SC2Frm2DoneCount; ++ MS_U32 u32SC3DoneCount; ++ MS_U32 u32SCLMainDoneCount; ++ MS_U32 u32SC1FrmActiveTime; ++ MS_U32 u32SC1SnpActiveTime; ++ MS_U32 u32SC2FrmActiveTime; ++ MS_U32 u32SC2Frm2ActiveTime; ++ MS_U32 u32SC3ActiveTime; ++ MS_U32 u32SCLMainActiveTime; ++ MS_U32 u32ISPTime; ++ MS_U32 u32ISPBlanking; ++ MS_U32 u32ISPBlankingTime; ++ MS_U32 u32ErrorCount; ++ MS_U8 u8CountReset; ++}ST_SCLIRQ_SCINTS_TYPE; ++typedef struct ++{ ++ MS_BOOL bVsyncWithVend; ++ MS_BOOL bLDCEvenOpen; ++ MS_BOOL bLDCEvenOpenCount; ++ MS_BOOL bResetHangCnt; ++}ST_SCLIRQ_DMAHANG_CNT; ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// extern Variable ++//------------------------------------------------------------------------------------------------- ++///////////////// ++/// bclkforcemode ++/// use in Drvscldma and Drvhvsp ++/// if True ,can't dynamic set Clk ++//////////////// ++extern unsigned char gbclkforcemode; ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/vip/drvvip.c b/drivers/mstar/scl/infinity3/src/mxlib/drv/vip/drvvip.c +new file mode 100644 +index 00000000..6ed3f85a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/vip/drvvip.c +@@ -0,0 +1,1141 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define DRV_VIP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++#include "hwreg.h" ++#include "drvvip.h" ++#include "halvip.h" ++#include "mdrv_scl_dbg.h" ++#include "drvCMDQ.h" ++#include "drvhvsp_st.h" ++#include "drvhvsp.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DRV_VIP_DBG 0 ++#define DRV_VIP_LDC_DMAP_align(x,align) ((x+align) & ~(align-1)) ++#define DMAPBLOCKUNIT 32 ++#define DMAPBLOCKUNITBYTE 4 ++#define DMAPBLOCKALIGN 4 ++#define DEFAULTLDCMD 0x1 ++#define SRAMNORMAL NULL ++ ++#define DLCVariableSection 8 ++#define DLCCurveFitEnable 7 ++#define DLCCurveFitRGBEnable 13 ++#define DLCDitherEnable 5 ++#define DLCHistYRGBEnable 10 ++#define DLCStaticEnable 1 ++#define LDCFBRWDiff 4 ++#define LDCSWModeEnable 10 ++#define LDCAppointFBidx 2 ++#define FHD_Width 1920 ++#define FHD_Height 1080 ++#define DRV_VIP_MUTEX_LOCK() MsOS_ObtainMutex(_VIP_Mutex,MSOS_WAIT_FOREVER) ++#define DRV_VIP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_VIP_Mutex) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_S32 _VIP_Mutex = -1; ++void *gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_NUM]; ++MS_BOOL gbSRAMCkeckPass = 1; ++//------------------------------------------------------------------------------------------------- ++// Loacl Functions ++//------------------------------------------------------------------------------------------------- ++MS_U16 _Drv_VIP_GetDLCEnableSetting(ST_VIP_DLC_HISTOGRAM_CONFIG *stDLCCfg) ++{ ++ MS_U16 u16valueForReg1Eh04; ++ u16valueForReg1Eh04 = ((MS_U16)stDLCCfg->bVariable_Section<bcurve_fit_en<bcurve_fit_rgb_en<bDLCdither_en<bhis_y_rgb_mode_en<bstatic<stFCfg.bEn) ++ { ++ for(u16sec=0;u16secu8Histogram_Range[u16sec]); ++ ++ } ++ else ++ { ++ u16Mask = 0xFF00; ++ u16tvalue = ((MS_U16)stDLCCfg->u8Histogram_Range[u16sec])<<8; ++ } ++ Drv_CMDQ_FillCmd(&stCfg,u32Reg,(u16tvalue),u16Mask); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ } ++ } ++ else ++ { ++ for(u16sec=0;u16secu8Histogram_Range[u16sec],u16sec+1); ++ } ++ } ++} ++void _Drv_VIP_SetDLCHistogramCMDQConfig ++ (ST_VIP_DLC_HISTOGRAM_CONFIG *stDLCCfg,MS_U16 u16valueForReg1Eh04) ++{ ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_DLC_04_L,(u16valueForReg1Eh04),0x25a2); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_DLC_03_L,(stDLCCfg->u8HistSft),0x0007); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_15_L,(stDLCCfg->bstat_MIU),0x0001); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_1C_L,((MS_U16)stDLCCfg->u8trig_ref_mode)<<2,0x0004); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_18_L,((MS_U16)stDLCCfg->u32StatBase[0]>>4),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_19_L,(MS_U16)(stDLCCfg->u32StatBase[0]>>20),0x07FF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_1A_L,(MS_U16)stDLCCfg->u32StatBase[1]>>4,0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_1B_L,(MS_U16)((MS_U32)stDLCCfg->u32StatBase[1]>>20),0x07FF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_DLC_08_L,((MS_U16)stDLCCfg->bRange)<<7,0x0080); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_01_L,stDLCCfg->u16Vst,0x03FF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_02_L,stDLCCfg->u16Vnd,0x03FF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_03_L,stDLCCfg->u16Hst,0x01FF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_VIP_MWE_04_L,stDLCCfg->u16Vnd,0x01FF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ ++ _Drv_VIP_For_SetDLCHistRangeEachSection(stDLCCfg); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++} ++void _Drv_VIP_SetDLCHistogramRIUConfig(ST_VIP_DLC_HISTOGRAM_CONFIG *stDLCCfg,MS_U16 u16valueForReg1Eh04) ++{ ++ Hal_VIP_DLCHistVarOnOff(u16valueForReg1Eh04); ++ Hal_VIP_SetDLCstatMIU(stDLCCfg->bstat_MIU,stDLCCfg->u32StatBase[0],stDLCCfg->u32StatBase[1]); ++ Hal_VIP_SetDLCshift(stDLCCfg->u8HistSft); ++ HAl_VIP_SetDLCmode(stDLCCfg->u8trig_ref_mode); ++ Hal_VIP_SetDLCActWin(stDLCCfg->bRange,stDLCCfg->u16Vst,stDLCCfg->u16Hst,stDLCCfg->u16Vnd,stDLCCfg->u16Hnd); ++ _Drv_VIP_For_SetDLCHistRangeEachSection(stDLCCfg); ++} ++void _Drv_VIP_GetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_REPORT *stdlc) ++{ ++ stdlc->u32PixelCount = Hal_VIP_DLCGetPC(); ++ stdlc->u32PixelWeight = Hal_VIP_DLCGetPW(); ++ stdlc->u8Baseidx = Hal_VIP_DLCGetBaseidx(); ++ stdlc->u8MaxPixel = Hal_VIP_DLCGetMaxP(); ++ stdlc->u8MinPixel = Hal_VIP_DLCGetMinP(); ++} ++MS_BOOL _Drv_VIP_SetLDCFrameBufferConfig(ST_VIP_LDC_MD_CONFIG *stLDCCfg) ++{ ++ Hal_VIP_SetLDCBypass(stLDCCfg->enbypass); ++ Hal_VIP_SetLDCHWrwDiff(((MS_U16)stLDCCfg->u8FBrwdiff)); ++ Hal_VIP_SetLDCSW_Idx(stLDCCfg->u8FBidx); ++ Hal_VIP_SetLDCSW_Mode(stLDCCfg->bEnSWMode); ++ if(!stLDCCfg->enbypass) ++ { ++ //HW issue: 64pixel mode bypass can't use; ++ Drv_VIP_SetLDCBank_Mode(stLDCCfg->enLDCType); ++ } ++ else ++ { ++ Drv_VIP_SetLDCBank_Mode(EN_DRV_VIP_LDCLCBANKMODE_128); ++ } ++ return TRUE; ++} ++void Drv_VIP_SetLDCBank_Mode(EN_DRV_VIP_LDCLCBANKMODE_TYPE enType) ++{ ++ Hal_VIP_SetLDCBank_Mode(enType); ++} ++MS_BOOL _Drv_VIP_SetLDCFrameBufferConfigByCMDQ(ST_VIP_LDC_MD_CONFIG *stLDCCfg) ++{ ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_10_L,stLDCCfg->u8FBidx,BIT1|BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_11_L,stLDCCfg->u8FBrwdiff,BIT1|BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_12_L,stLDCCfg->bEnSWMode,BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_0F_L,((MS_U16)stLDCCfg->enbypass),0x0001); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ if(!stLDCCfg->enbypass) ++ { ++ //HW issue: 64pixel mode bypass can't use; ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_09_L, ++ ((MS_U16)stLDCCfg->enLDCType == EN_DRV_HVSP_LDCLCBANKMODE_64)? BIT0 :0,BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ } ++ else ++ { ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_09_L,0,BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ } ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++ return TRUE; ++} ++void _Drv_VIP_SetNLMSRAMbyAutodownload(ST_VIP_NLM_SRAM_CONFIG *stCfg) ++{ ++ Hal_VIP_SetAutodownloadAddr(stCfg->u32baseadr,stCfg->u16iniaddr,VIP_NLM_AUTODOWNLOAD_CLIENT); ++ Hal_VIP_SetAutodownloadReq(stCfg->u16depth,stCfg->u16reqlen,VIP_NLM_AUTODOWNLOAD_CLIENT); ++ Hal_VIP_SetAutodownload(stCfg->bCLientEn,stCfg->btrigContinue,VIP_NLM_AUTODOWNLOAD_CLIENT); ++#if DRV_VIP_DBG ++ MS_U16 u16entry; ++ for(u16entry=0;u16entryu32viradr + u16entry * VIP_NLM_AUTODOWNLOAD_BASE_UNIT ;// 1entry cost 16 byte(128 bit) ++ pu32Addr = (MS_U32 *)(u32addr); ++ u32value = *pu32Addr; ++ Hal_VIP_SetNLMSRAMbyCPU(u16entry,u32value); ++#if DRV_VIP_DBG ++ Hal_VIP_GetNLMSRAM(u16entry); ++#endif ++ } ++} ++MS_U32 _Drv_VIP_GetLDCDmapPitch(ST_VIP_LDC_DMAP_CONFIG *stLDCCfg) ++{ ++ MS_U32 u32DMAP_pitch; ++ u32DMAP_pitch = ((stLDCCfg->u16DMAPWidth/DMAPBLOCKUNIT)+1); ++ u32DMAP_pitch = DRV_VIP_LDC_DMAP_align(u32DMAP_pitch,DMAPBLOCKALIGN); ++ u32DMAP_pitch = u32DMAP_pitch * DMAPBLOCKUNITBYTE; ++ return u32DMAP_pitch; ++} ++void _Drv_VIP_Set_LDCDmapByCMDQ(ST_VIP_LDC_DMAP_CONFIG *stLDCCfg,MS_U32 u32DMAP_pitch) ++{ ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_0A_L,((MS_U16)stLDCCfg->u32DMAPaddr),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_0B_L,((MS_U16)(stLDCCfg->u32DMAPaddr>>16)),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_0C_L,((MS_U16)u32DMAP_pitch),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_0E_L,(((MS_U16)stLDCCfg->bEnPowerSave)<<6|((MS_U16)stLDCCfg->u8DMAPoffset)),0x007F); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++} ++void _Drv_VIP_SetLDCDmap(ST_VIP_LDC_DMAP_CONFIG *stLDCCfg,MS_U32 u32DMAP_pitch) ++{ ++ Hal_VIP_SetLDCDmapBase(stLDCCfg->u32DMAPaddr); ++ Hal_VIP_SetLDCDmapPitch(u32DMAP_pitch); ++ Hal_VIP_SetLDCDmapOffset(stLDCCfg->u8DMAPoffset); ++ Hal_VIP_SetLDCDmapPS(stLDCCfg->bEnPowerSave); ++} ++void _Drv_VIP_SetLDCSRAMCfgByCMDQ(ST_VIP_LDC_SRAM_CONFIG *stLDCCfg) ++{ ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_22_L,((MS_U16)stLDCCfg->u16SRAMhoramount),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_2A_L,((MS_U16)stLDCCfg->u16SRAMveramount),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_24_L,((MS_U16)(stLDCCfg->u32loadhoraddr>>4)),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_25_L,((MS_U16)(stLDCCfg->u32loadhoraddr>>20)),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_2C_L,((MS_U16)(stLDCCfg->u32loadveraddr>>4)),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_2D_L,((MS_U16)(stLDCCfg->u32loadveraddr>>20)),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_23_L,((MS_U16)stLDCCfg->u16SRAMhorstr),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_FillCmd(&stCfg,REG_SCL_LDC_2B_L,((MS_U16)stLDCCfg->u16SRAMverstr),0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++} ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Drv_VIP_Exit(void) ++{ ++ int i; ++ if(_VIP_Mutex != -1) ++ { ++ MsOS_DeleteMutex(_VIP_Mutex); ++ _VIP_Mutex = -1; ++ } ++ for(i=0;iu32RiuBase); ++ Drv_VIP_SRAM_Dump(); ++ for(idx=0;idxbCLientEn) ++ { ++ _Drv_VIP_SetNLMSRAMbyAutodownload(stCfg); ++ } ++ else ++ { ++ _Drv_VIP_SetNLMSRAMbyCPU(stCfg); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_CONFIG *stDLCCfg) ++{ ++ MS_U16 u16valueForReg1Eh04; ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s: ", __FUNCTION__); ++ u16valueForReg1Eh04 = _Drv_VIP_GetDLCEnableSetting(stDLCCfg); ++ if(stDLCCfg->stFCfg.bEn) ++ { ++ _Drv_VIP_SetDLCHistogramCMDQConfig(stDLCCfg,u16valueForReg1Eh04); ++ } ++ else ++ { ++ _Drv_VIP_SetDLCHistogramRIUConfig(stDLCCfg,u16valueForReg1Eh04); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), ++ "[DRVVIP]u16valueForReg1Eh04:%hx ,stDLCCfg->u32StatBase[0]:%lx,stDLCCfg->u32StatBase[1]%lx,stDLCCfg->bstat_MIU:%hhd\n" ++ ,u16valueForReg1Eh04,stDLCCfg->u32StatBase[0],stDLCCfg->u32StatBase[1],stDLCCfg->bstat_MIU); ++ } ++ ++ return TRUE; ++} ++ ++MS_U32 Drv_VIP_GetDLCHistogramReport(MS_U16 u16range) ++{ ++ MS_U32 u32value; ++ u32value = Hal_VIP_DLC_Hist_GetRange(u16range); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s Histogram_%hd:%lx \n", __FUNCTION__,u16range,u32value); ++ return u32value; ++} ++void Drv_VIP_GetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_REPORT *stdlc) ++{ ++ _Drv_VIP_GetDLCHistogramConfig(stdlc); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s PixelCount:%lx,PixelWeight:%lx,Baseidx:%hhx \n" ++ ,__FUNCTION__, stdlc->u32PixelCount,stdlc->u32PixelWeight,stdlc->u8Baseidx); ++} ++MS_BOOL Drv_VIP_SetLDCMdConfig(ST_VIP_LDC_MD_CONFIG *stLDCCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ MsOS_WaitForCPUWriteToDMem(); ++ if(stLDCCfg->stFCfg.bEn) ++ { ++ _Drv_VIP_SetLDCFrameBufferConfigByCMDQ(stLDCCfg); ++ } ++ else ++ { ++ _Drv_VIP_SetLDCFrameBufferConfig(stLDCCfg); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetLDCOnConfig(MS_BOOL bEn) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s: bEn:%hhd\n", __FUNCTION__,bEn); ++ MsOS_WaitForCPUWriteToDMem(); ++ if(!bEn) ++ { ++ //HW issue: 64pixel mode bypass can't use; ++ Drv_VIP_SetLDCBank_Mode(EN_DRV_VIP_LDCLCBANKMODE_128); ++ } ++ Hal_VIP_SetLDCBypass(!bEn); ++ Drv_HVSP_SetLDCONOFF(bEn); ++ return TRUE; ++} ++MS_BOOL Drv_VIP_SetLDCDmapConfig(ST_VIP_LDC_DMAP_CONFIG *stLDCCfg) ++{ ++ MS_U32 u32DMAP_pitch =_Drv_VIP_GetLDCDmapPitch(stLDCCfg); ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), ++ "[DRVVIP]%s DMAP_pitch:%lx,DMAPaddr:%lx \n",__FUNCTION__,u32DMAP_pitch,stLDCCfg->u32DMAPaddr); ++ if(stLDCCfg->stFCfg.bEn) ++ { ++ _Drv_VIP_Set_LDCDmapByCMDQ(stLDCCfg,u32DMAP_pitch); ++ } ++ else ++ { ++ _Drv_VIP_SetLDCDmap(stLDCCfg,u32DMAP_pitch); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_CheckIPMResolution(void) ++{ ++ MS_BOOL bRet = 0; ++ ST_HVSP_IPM_CONFIG stInformCfg; ++ MsOS_Memset(&stInformCfg,0,sizeof(ST_HVSP_IPM_CONFIG)); ++ Drv_HVSP_GetFrameBufferAttribute(E_HVSP_ID_1, &stInformCfg); ++ if(stInformCfg.u16Fetch<=FHD_Width && stInformCfg.u16Vsize<=FHD_Width) ++ { ++ bRet = 1; ++ } ++ return bRet; ++} ++MS_BOOL Drv_VIP_SetLDCSRAMConfig(ST_VIP_LDC_SRAM_CONFIG *stLDCCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s loadhoraddr:%lx,loadveraddr:%lx \n" ++ ,__FUNCTION__,stLDCCfg->u32loadhoraddr,stLDCCfg->u32loadveraddr); ++ if(stLDCCfg->stFCfg.bEn) ++ { ++ _Drv_VIP_SetLDCSRAMCfgByCMDQ(stLDCCfg); ++ } ++ else ++ { ++ Hal_VIP_SetLDCSramAmount(stLDCCfg->u16SRAMhoramount,stLDCCfg->u16SRAMveramount); ++ Hal_VIP_SetLDCSramBase(stLDCCfg->u32loadhoraddr,stLDCCfg->u32loadveraddr); ++ Hal_VIP_SetLDCSramStr(stLDCCfg->u16SRAMhorstr,stLDCCfg->u16SRAMverstr); ++ } ++ return TRUE; ++} ++MS_BOOL Drv_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackSetPayloadData(u16Timecode, u8OperatorID); ++ return 1; ++} ++MS_BOOL Drv_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackSetKey(bUserDefinded, pu8Setting); ++ return 1; ++} ++MS_BOOL Drv_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackSetUserDefindedSetting(bUserDefinded, pu8Setting); ++ return 1; ++} ++MS_BOOL Drv_VIP_VtrackEnable( MS_U8 u8FrameRate, EN_VIP_DRVVTRACK_ENABLE_TYPE bEnable) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVVIP(), "[DRVVIP]%s \n", __FUNCTION__); ++ Hal_VIP_VtrackEnable(u8FrameRate, (EN_VIP_VTRACK_ENABLE_TYPE)bEnable); ++ return 1; ++} ++MS_BOOL Drv_VIP_GetBypassStatus(EN_VIP_DRV_CONFIG_TYPE enIPType) ++{ ++ MS_BOOL bRet; ++ switch(enIPType) ++ { ++ case EN_VIP_DRV_CONFIG: ++ bRet = Hal_VIP_GetVIPBypass(); ++ break; ++ ++ case EN_VIP_DRV_MCNR_CONFIG: ++ bRet = Hal_VIP_GetMCNRBypass(); ++ break; ++ ++ case EN_VIP_DRV_LDC_CONFIG: ++ bRet = Hal_VIP_GetLDCBypass(); ++ break; ++ ++ case EN_VIP_DRV_NLM_CONFIG: ++ bRet = Hal_VIP_GetNLMBypass(); ++ break; ++ default: ++ bRet = 0; ++ break; ++ } ++ return bRet; ++} ++void Drv_VIP_CheckVIPSRAM(MS_U32 u32Type) ++{ ++ MS_U32 u32Events; ++ if(!Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ DRV_VIP_MUTEX_LOCK(); ++ switch(u32Type) ++ { ++ case E_SCLIRQ_EVENT_GAMMA_Y: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_GAMMA_Y, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_Y],REG_VIP_SCNR_41_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_GAMMA_Y, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_Y],REG_VIP_SCNR_41_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_GAMMA_Y, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_Y],REG_VIP_SCNR_41_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_GAMMA_Y, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_Y],REG_VIP_SCNR_41_L); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GAMMA_U: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_GAMMA_U, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_U],REG_VIP_SCNR_41_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_GAMMA_U, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_U],REG_VIP_SCNR_41_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_GAMMA_U, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_U],REG_VIP_SCNR_41_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_GAMMA_U, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_U],REG_VIP_SCNR_41_L); ++ break; ++ } ++ } ++ case E_SCLIRQ_EVENT_GAMMA_V: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_GAMMA_V, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_V],REG_VIP_SCNR_41_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_GAMMA_V, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_V],REG_VIP_SCNR_41_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_GAMMA_V, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_V],REG_VIP_SCNR_41_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_GAMMA_V, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GAMMA_V],REG_VIP_SCNR_41_L); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GM10to12_R: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM10to12_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_R],REG_SCL_HVSP1_7A_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM10to12_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_R],REG_SCL_HVSP1_7A_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM10to12_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_R],REG_SCL_HVSP1_7A_L)) ++ { ++ break; ++ } ++ else ++ { ++ do ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ while(!Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM10to12_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_R],REG_SCL_HVSP1_7A_L)); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GM10to12_G: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM10to12_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_G],REG_SCL_HVSP1_7A_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM10to12_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_G],REG_SCL_HVSP1_7A_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM10to12_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_G],REG_SCL_HVSP1_7A_L)) ++ { ++ break; ++ } ++ else ++ { ++ do ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ while(!Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM10to12_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_G],REG_SCL_HVSP1_7A_L)); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GM10to12_B: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM10to12_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_B],REG_SCL_HVSP1_7A_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM10to12_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_B],REG_SCL_HVSP1_7A_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM10to12_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_B],REG_SCL_HVSP1_7A_L)) ++ { ++ break; ++ } ++ else ++ { ++ do ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ while(!Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM10to12_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM10to12_B],REG_SCL_HVSP1_7A_L)); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GM12to10_R: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM12to10_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_R],REG_SCL_HVSP1_7D_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM12to10_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_R],REG_SCL_HVSP1_7D_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM12to10_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_R],REG_SCL_HVSP1_7D_L)) ++ { ++ break; ++ } ++ else ++ { ++ do ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ while(!Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM12to10_R, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_R],REG_SCL_HVSP1_7D_L)); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GM12to10_G: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM12to10_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_G],REG_SCL_HVSP1_7D_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM12to10_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_G],REG_SCL_HVSP1_7D_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM12to10_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_G],REG_SCL_HVSP1_7D_L)) ++ { ++ break; ++ } ++ else ++ { ++ do ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ while(!Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM12to10_G, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_G],REG_SCL_HVSP1_7D_L)); ++ break; ++ } ++ } ++ ++ case E_SCLIRQ_EVENT_GM12to10_B: ++ if((VIPSETRULE() == E_VIPSetRule_CMDQCheck)||(VIPSETRULE() == E_VIPSetRule_CMDQAllCheck) ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck)) ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM12to10_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_B],REG_SCL_HVSP1_7D_L)) ++ { ++ break; ++ } ++ else ++ { ++ ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_GM12to10_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_B],REG_SCL_HVSP1_7D_L); ++ break; ++ } ++ } ++ else ++ { ++ if(Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM12to10_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_B],REG_SCL_HVSP1_7D_L)) ++ { ++ break; ++ } ++ else ++ { ++ do ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_FRMENDSYNC, &u32Events, E_OR, 2000); // get status: FRM END ++ } ++ while(!Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_GM12to10_B, ++ gpvSRAMBuffer[EN_VIP_DRV_AIP_SRAM_GM12to10_B],REG_SCL_HVSP1_7D_L)); ++ break; ++ } ++ } ++ ++ default: ++ break; ++ } ++ DRV_VIP_MUTEX_UNLOCK(); ++} ++ ++#undef DRV_VIP_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/drv/vip/drvvip.h b/drivers/mstar/scl/infinity3/src/mxlib/drv/vip/drvvip.h +new file mode 100644 +index 00000000..f7e71313 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/drv/vip/drvvip.h +@@ -0,0 +1,319 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _DRV_VIP_H ++#define _DRV_VIP_H ++//============================================================================= ++// Defines ++//============================================================================= ++// ++#define VIP_DLC_HISTOGRAM_SECTION_NUM 7 ++#define VIP_DLC_HISTOGRAM_REPORT_NUM 8 ++#define VIP_NLM_ENTRY_NUM 1104 ++#define VIP_NLM_AUTODOWNLOAD_BASE_UNIT 16 ++#define VIP_NLM_AUTODOWNLOAD_CLIENT 9 ++#define DRV_VIP_MUTEX_LOCK() MsOS_ObtainMutex(_VIP_Mutex,MSOS_WAIT_FOREVER) ++#define DRV_VIP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_VIP_Mutex) ++// ++typedef enum ++{ ++ E_VIP_LDC_Drv_MENULOAD, ++ E_VIP_LDC_Drv_BYPASS, ++ E_VIP_LDC_BYPASS_Drv_TYPE_NUM, ++}EN_VIP_LDC_BYPASS_Drv_TYPE; ++// ++typedef enum ++{ ++ EN_VIP_DRVVTRACK_ENABLE_ON, ++ EN_VIP_DRVVTRACK_ENABLE_OFF, ++ EN_VIP_DRVVTRACK_ENABLE_DEBUG, ++}EN_VIP_DRVVTRACK_ENABLE_TYPE; ++typedef enum ++{ ++ EN_VIP_DRV_ACK_CONFIG = 0x1, ///< ACK ++ EN_VIP_DRV_IBC_CONFIG = 0x2, ///< IBC ++ EN_VIP_DRV_IHCICC_CONFIG = 0x4, ///< ICCIHC ++ EN_VIP_DRV_ICC_CONFIG = 0x8, ///< ICE ++ EN_VIP_DRV_IHC_CONFIG = 0x10, ///< IHC ++ EN_VIP_DRV_FCC_CONFIG = 0x20, ///< FCC ++ EN_VIP_DRV_UVC_CONFIG = 0x40, ///< UVC ++ EN_VIP_DRV_DLC_HISTOGRAM_CONFIG = 0x80, ///< HIST ++ EN_VIP_DRV_DLC_CONFIG = 0x100, ///< DLC ++ EN_VIP_DRV_LCE_CONFIG = 0x200, ///< LCE ++ EN_VIP_DRV_PEAKING_CONFIG = 0x400, ///< PK ++ EN_VIP_DRV_NLM_CONFIG = 0x800, ///< NLM ++ EN_VIP_DRV_LDC_MD_CONFIG = 0x1000, ///< LDCMD ++ EN_VIP_DRV_LDC_DMAP_CONFIG = 0x2000, ///< LDCDMAP ++ EN_VIP_DRV_LDC_SRAM_CONFIG = 0x4000, ///< LDC SRAM ++ EN_VIP_DRV_LDC_CONFIG = 0x8000, ///< LDC ++ EN_VIP_DRV_CONFIG = 0x10000, ///< 19 bit to control 19 IOCTL ++ EN_VIP_DRV_MCNR_CONFIG = 0x20000, ///< MCNR ++}EN_VIP_DRV_CONFIG_TYPE; ++typedef enum ++{ ++ EN_DRV_VIP_LDCLCBANKMODE_64, ++ EN_DRV_VIP_LDCLCBANKMODE_128, ++}EN_DRV_VIP_LDCLCBANKMODE_TYPE; ++typedef enum ++{ ++ EN_VIP_DRV_AIP_SRAM_GAMMA_Y = 0, ///< gamma y ++ EN_VIP_DRV_AIP_SRAM_GAMMA_U, ///< gamma u ++ EN_VIP_DRV_AIP_SRAM_GAMMA_V, ///< gamma v ++ EN_VIP_DRV_AIP_SRAM_GM10to12_R, ///< gamma R ++ EN_VIP_DRV_AIP_SRAM_GM10to12_G, ///< gamma G ++ EN_VIP_DRV_AIP_SRAM_GM10to12_B, ///< gamma B ++ EN_VIP_DRV_AIP_SRAM_GM12to10_R, ///< gamma R ++ EN_VIP_DRV_AIP_SRAM_GM12to10_G, ///< gamma G ++ EN_VIP_DRV_AIP_SRAM_GM12to10_B, ///< gamma B ++ EN_VIP_DRV_AIP_SRAM_WDR, ///< wdr ++ EN_VIP_DRV_AIP_SRAM_NUM, ///< wdr ++}EN_VIP_DRV_AIP_SRAM_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Structure ++//------------------------------------------------------------------------------------------------- ++// IOCTL_VIP_SET_DNR_CONFIG ++typedef struct ++{ ++ unsigned char bEn; ++ unsigned char u8framecnt; ++}ST_VIP_FC_CONFIG; ++typedef struct ++{ ++ MS_U32 u32RiuBase; ++}ST_VIP_INIT_CONFIG; ++ ++typedef struct ++{ ++ MS_U32 u32baseadr; ++ MS_U16 u16depth; ++ MS_U16 u16reqlen; ++ MS_BOOL bCLientEn; ++ MS_BOOL btrigContinue; ++ MS_U16 u16iniaddr; ++ MS_U32 u32viradr; ++}ST_VIP_NLM_SRAM_CONFIG; ++ ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned char u8FBidx; ++ unsigned char u8FBrwdiff; ++ unsigned char bEnSWMode; ++ EN_VIP_LDC_BYPASS_Drv_TYPE enbypass; ++ EN_DRV_VIP_LDCLCBANKMODE_TYPE enLDCType; ++}ST_VIP_LDC_MD_CONFIG; ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned long u32DMAPaddr; ++ unsigned short u16DMAPWidth; ++ unsigned char u8DMAPoffset; ++ unsigned char bEnPowerSave; ++}ST_VIP_LDC_DMAP_CONFIG; ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned long u32loadhoraddr; ++ unsigned short u16SRAMhorstr; ++ unsigned short u16SRAMhoramount; ++ unsigned long u32loadveraddr; ++ unsigned short u16SRAMverstr; ++ unsigned short u16SRAMveramount; ++}ST_VIP_LDC_SRAM_CONFIG; ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned char bVariable_Section;//1E04 ++ unsigned char bstatic; //1E04 ++ unsigned char bcurve_fit_en;//1E04 ++ unsigned char bhis_y_rgb_mode_en;//1E04 ++ unsigned char bcurve_fit_rgb_en;//1E04 ++ unsigned char bDLCdither_en;//1E04 ++ unsigned char u8Histogram_Range[VIP_DLC_HISTOGRAM_SECTION_NUM]; ++ unsigned char bstat_MIU; ++ unsigned char bRange; ++ unsigned short u16Vst; ++ unsigned short u16Vnd; ++ unsigned short u16Hst; ++ unsigned short u16Hnd; ++ unsigned char u8HistSft; ++ unsigned char u8trig_ref_mode; ++ unsigned long u32StatBase[2]; ++}ST_VIP_DLC_HISTOGRAM_CONFIG; ++ ++//IOCTL_VIP_GET_DLC_HISTOGRAM_REPORT ++typedef struct ++{ ++ unsigned int u32Histogram[VIP_DLC_HISTOGRAM_REPORT_NUM]; ++ unsigned long u32PixelWeight; ++ unsigned long u32PixelCount; ++ unsigned char u8MinPixel; ++ unsigned char u8MaxPixel; ++ unsigned char u8Baseidx; ++}ST_VIP_DLC_HISTOGRAM_REPORT; ++ ++//IOCTL_VIP_SET_FCC_ADP_YWIN_CONFIG ++ ++ ++typedef struct ++{ ++ ST_VIP_FC_CONFIG stFCfg; ++ unsigned long u32Addr; ++ unsigned short u16Data; ++ unsigned short u16Mask; ++ unsigned char u8framecnt; ++ unsigned char bfire; ++ unsigned char bCnt; ++}ST_VIP_CMDQ_CONFIG; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef DRV_VIP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE MS_BOOL Drv_VIP_SetLDCOnConfig(MS_BOOL bEn); ++INTERFACE void Drv_VIP_GetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_REPORT *stdlc); ++INTERFACE MS_BOOL Drv_VIP_Init(ST_VIP_INIT_CONFIG *pCfg); ++INTERFACE void Drv_VIP_Exit(void); ++INTERFACE MS_BOOL Drv_VIP_SetDLCHistogramConfig(ST_VIP_DLC_HISTOGRAM_CONFIG *stDLCCfg); ++INTERFACE MS_U32 Drv_VIP_GetDLCHistogramReport(MS_U16 u16range); ++INTERFACE MS_BOOL Drv_VIP_SetLDCMdConfig(ST_VIP_LDC_MD_CONFIG *stLDCCfg); ++INTERFACE MS_BOOL Drv_VIP_SetLDCDmapConfig(ST_VIP_LDC_DMAP_CONFIG *stLDCCfg); ++INTERFACE MS_BOOL Drv_VIP_SetLDCSRAMConfig(ST_VIP_LDC_SRAM_CONFIG *stLDCCfg); ++INTERFACE MS_BOOL Drv_VIP_CheckIPMResolution(void); ++INTERFACE void Drv_VIP_HWInit(void); ++INTERFACE MS_BOOL Drv_VIP_GetIsBlankingRegion(void); ++INTERFACE void Drv_VIP_Open(void); ++INTERFACE MS_BOOL Drv_VIP_GetEachDMAEn(void); ++INTERFACE void * Drv_VIP_GeSRAMGlobal(EN_VIP_DRV_AIP_SRAM_TYPE enAIPType); ++INTERFACE void * Drv_VIP_SetAIPSRAMConfig ++ (void * pvPQSetParameter, EN_VIP_DRV_AIP_SRAM_TYPE enAIPType); ++INTERFACE void Drv_VIP_DNR_Init(void); ++INTERFACE void Drv_VIP_SetLDCBank_Mode(EN_DRV_VIP_LDCLCBANKMODE_TYPE enType); ++INTERFACE void Drv_VIP_PK_Init(void); ++INTERFACE void Drv_VIP_DLC_Init(void); ++INTERFACE void Drv_VIP_UVC_Init(void); ++INTERFACE void Drv_VIP_ICE_Init(void); ++INTERFACE void Drv_VIP_IHC_Init(void); ++INTERFACE void Drv_VIP_FCC_Init(void); ++INTERFACE void Drv_VIP_LCE_Init(void); ++INTERFACE unsigned char Drv_VIP_SetNLMSRAMConfig(ST_VIP_NLM_SRAM_CONFIG *stCfg); ++INTERFACE void Drv_VIP_SRAM_Dump(void); ++INTERFACE MS_BOOL Drv_VIP_GetSRAMCheckPass(void); ++INTERFACE void Drv_VIP_SetMCNRIPMRead(MS_BOOL bEn); ++INTERFACE void Drv_VIP_SetIPMConpress(MS_BOOL bEn); ++INTERFACE void Drv_VIP_SetCIIRRead(MS_BOOL bEn); ++INTERFACE void Drv_VIP_SetCIIRWrite(MS_BOOL bEn); ++INTERFACE MS_BOOL Drv_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID); ++INTERFACE MS_BOOL Drv_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE MS_BOOL Drv_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE MS_BOOL Drv_VIP_VtrackEnable( MS_U8 u8FrameRate, EN_VIP_DRVVTRACK_ENABLE_TYPE bEnable); ++INTERFACE MS_BOOL Drv_VIP_GetBypassStatus(EN_VIP_DRV_CONFIG_TYPE enIPType); ++INTERFACE void Drv_VIP_CheckVIPSRAM(MS_U32 u32Type); ++INTERFACE void * Drv_VIP_GetWaitQueueHead(void); ++INTERFACE MS_BOOL Drv_VIP_GetCMDQHWDone(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/halCMDQ.c b/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/halCMDQ.c +new file mode 100644 +index 00000000..37174585 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/halCMDQ.c +@@ -0,0 +1,489 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// file halCMDQ.c ++// @brief CMDQ HAL ++// @author MStar Semiconductor,Inc. ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++#include "MsCommon.h" ++#include "MsTypes.h" ++ ++#include "hwreg.h" ++#include "regCMDQ.h" ++#include "drvCMDQ.h" ++#include "halCMDQ.h" ++ ++#define CMDQDBG(x) ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Driver Compiler Option ++//-------------------------------------------------------------------------------------------------- ++ ++//-------------------------------------------------------------------------------------------------- ++// Macro of bit operations ++//-------------------------------------------------------------------------------------------------- ++MS_U32 _CMDQ_RIU_BASE; ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Inline Function ++//-------------------------------------------------------------------------------------------------- ++ ++void Hal_CMDQ_InitRIUBase(MS_U32 u32PM_riu_base) ++{ ++ _CMDQ_RIU_BASE = u32PM_riu_base ; ++} ++ ++//--------------------------------------------------------------------------- ++///set the element of _CMDQCtrl ++/// .CMDQ_Enable ++/// .CMDQ_Length_ReadMode ++/// .CMDQ_Mask_Setting ++//--------------------------------------------------------------------------- ++MS_U32 Hal_CMDQ_GetRegFromIPID(EN_CMDQ_IP_TYPE enIPType, MS_U8 u8addr) ++{ ++ MS_U32 Reg = 0; ++ switch(enIPType) ++ { ++ case EN_CMDQ_TYPE_IP0: ++ Reg = REG_CMDQ_BASE; ++ break; ++ ++ case EN_CMDQ_TYPE_IP1: ++ Reg = REG_CMDQ1_BASE; ++ break; ++ case EN_CMDQ_TYPE_IP2: ++ Reg = REG_CMDQ2_BASE; ++ break; ++ default: ++ Reg = REG_CMDQ_BASE; ++ break; ++ } ++ Reg += (u8addr*2); ++ return Reg; ++ ++} ++void Hal_CMDQ_SetRegPassWaitPoll(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x24); ++ W2BYTEMSK(Reg,bEn ? 0xE : 0,0xE); ++} ++MS_U16 Hal_CMDQ_GetFinalIrq(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Mask) ++{ ++ MS_U16 u16val; ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x44); ++ u16val = R2BYTEMSK(Reg, u16Mask);; ++ return u16val; ++} ++MS_U16 Hal_CMDQ_GetRawIrq(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Mask) ++{ ++ MS_U16 u16val; ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x45); ++ u16val = R2BYTEMSK(Reg, u16Mask);; ++ return u16val; ++} ++ ++void Hal_CMDQ_Enable(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x1); ++ if(bEn) ++ { ++ W2BYTEMSK(Reg, 0x01, 0x01); ++ ++ } ++ else ++ { ++ W2BYTEMSK(Reg, 0x00, 0x01); ++ ++ } ++ ++} ++void Hal_CMDQ_SetBaseEn(EN_CMDQ_IP_TYPE enIPType, MS_BOOL bEn) ++{ ++ MS_U32 Reg = 0; ++ MS_U32 Reg1 = 0; ++ MS_U32 Reg2 = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x1); ++ Reg1 = Hal_CMDQ_GetRegFromIPID(enIPType ,0x11); ++ Reg2 = Hal_CMDQ_GetRegFromIPID(enIPType ,0x20); ++ if(bEn) ++ { ++ W2BYTEMSK(Reg, 0x01, 0x01); ++ W2BYTEMSK(Reg1, 0x190d, 0x1FFF); ++ W2BYTEMSK(Reg2, 0x0080, 0x0080); ++ } ++ else ++ { ++ ++ W2BYTEMSK(Reg1, 0x00, 0x10FF); ++ W2BYTEMSK(Reg2, 0x00, 0x0080); ++ } ++ ++} ++ ++ ++//--------------------------------------------------------------------------- ++///set the element of _CMDQCtrl ++/// .CMDQ_En_Clk_Miu ++//--------------------------------------------------------------------------- ++void Hal_CMDQ_Reset(EN_CMDQ_IP_TYPE enIPType, MS_BOOL bEn) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x31); ++ if(bEn) ++ { ++ W2BYTEMSK(Reg, 0x00, 0x01); ++ } ++ else ++ { ++ W2BYTEMSK(Reg, 0x01, 0x01); ++ } ++} ++void Hal_CMDQ_SetTrigAlways(EN_CMDQ_IP_TYPE enIPType, MS_BOOL bEn) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x2); ++ if(bEn) ++ W2BYTEMSK(Reg, 0x00, 0x01); ++ else ++ W2BYTEMSK(Reg, 0x01, 0x01); ++} ++MS_BOOL Hal_CMDQ_SetDMAMode(EN_CMDQ_IP_TYPE enIPType,int ModeSel) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x2); ++ if (ModeSel==1) ++ { ++ W2BYTEMSK(Reg, 0x00, 0x02); ++ return TRUE; ++ } ++ else if(ModeSel==0) ++ { ++ W2BYTEMSK(Reg, 0x01, 0x02); ++ return TRUE; ++ } ++ else ++ { ++ W2BYTEMSK(Reg, 0x04, 0x04); ++ return TRUE; ++ } ++} ++ ++void Hal_CMDQ_SetStartPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr) ++{ ++ MS_U32 temp; ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x4); ++ temp=(MS_U32)(StartAddr); ++ temp=temp/16; ++ W4BYTE(Reg,temp); ++} ++ ++void Hal_CMDQ_SetEndPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 EndAddr) ++{ ++ MS_U32 temp; ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x6); ++ temp=(MS_U32)(EndAddr); ++ temp=temp/16; ++ W4BYTE(Reg,temp); ++} ++ ++void Hal_CMDQ_SetOffsetPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 OffsetAddr) ++{ ++ MS_U32 temp; ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x8); ++ temp=(MS_U32)(OffsetAddr); ++ temp=temp>>4; ++ CMDQDBG(printf("End_Pointer _bits:%lx\n", temp)); ++ W4BYTE(Reg,temp); ++} ++ ++void Hal_CMDQ_SetTimer(EN_CMDQ_IP_TYPE enIPType,MS_U32 time) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x4A); ++ W2BYTE(Reg , time); ++} ++ ++void Hal_CMDQ_SetRatio(EN_CMDQ_IP_TYPE enIPType,MS_U32 Ratio) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x4B); ++ W2BYTEMSK(Reg, Ratio, 0x00FF); ++} ++void Hal_CMDQ_Set_Waittrig(EN_CMDQ_IP_TYPE enIPType,MS_U16 trig) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x22); ++ W2BYTEMSK(Reg, trig, 0x00FF); ++} ++void Hal_CMDQ_SetSkipPollWhenWaitTimeout(EN_CMDQ_IP_TYPE enIPType,MS_BOOL ben) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x29); ++ if(ben) ++ W2BYTEMSK(Reg, 0x0080, 0x0080); ++ else ++ W2BYTEMSK(Reg, 0x0000, 0x0080); ++} ++void Hal_CMDQ_SetTimeoutAmount(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 Reg = 0; ++ MS_U32 Reg1 = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x28); ++ Reg1 = Hal_CMDQ_GetRegFromIPID(enIPType ,0x29); ++ W2BYTE(Reg, (MS_U16)(CMDQ_base_amount&0xFFFF)); ++ W2BYTEMSK(Reg1, (MS_U16)((CMDQ_base_amount>>16) &0xF), 0x000F); ++ W2BYTEMSK(Reg1, (MS_U16)(CMDQ_timeout_amount <<8), 0xFF00); ++ ++} ++void Hal_CMDQ_ClearIRQByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16IRQ) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x48); ++ W2BYTE(Reg, u16IRQ); ++ W2BYTE(Reg, 0x0); ++} ++void Hal_CMDQ_ResetSoftInterrupt(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x48); ++ W2BYTE(Reg, 0xFFFF); ++ W2BYTE(Reg, 0x0); ++} ++ ++void Hal_CMDQ_SetISRMSK(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Msk) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x47); ++ W2BYTE(Reg, u16Msk); ++} ++ ++void Hal_CMDQ_WriteRegDirect(MS_U32 u32Addr,MS_U16 u16Data) ++{ ++ W2BYTE(u32Addr, u16Data); ++} ++void Hal_CMDQ_WriteRegMaskDirect(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask) ++{ ++ W2BYTEMSK(u32Addr,u16Data,u16Mask); ++ ++} ++MS_U16 Hal_CMDQ_Read2ByteReg(MS_U32 u32Addr) ++{ ++ MS_U16 u16val; ++ u16val = R2BYTE(u32Addr); ++ return u16val; ++} ++MS_U16 Hal_CMDQ_Read2ByteMaskDirect(MS_U32 u32Addr,MS_U16 u16Mask) ++{ ++ MS_U16 u16val; ++ u16val = R2BYTEMSK(u32Addr, u16Mask); ++ return u16val; ++} ++MS_U16 Hal_CMDQ_Get_ISP_Cnt(void) ++{ ++ MS_U16 isp_cnt; ++ MS_U32 reg; ++ reg=0x1302f4; ++ isp_cnt=R2BYTE(reg); ++ return isp_cnt; ++} ++//--------------------------------------------------------------------------- ++///Trigger for update start pointer and end pointer ++//--------------------------------------------------------------------------- ++void Hal_CMDQ_Start(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x3); ++ if (bEn) ++ { ++ W2BYTEMSK(Reg, 0x0002, 0x0002); ++ } ++ ++} ++MS_U32 Hal_CMDQ_GetMIUReadAddr(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 reg_value=0; ++ MS_U32 Reg = 0; ++ MS_U32 Reg1 = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x3); ++ Reg1 = Hal_CMDQ_GetRegFromIPID(enIPType ,0xA); ++ W2BYTEMSK(Reg,0x0100 , 0x0100); ++ reg_value=R4BYTE(Reg1); ++ return reg_value; ++} ++ ++//--------------------------------------------------------------------------- ++///Set Previous Dummy Register bit to be 1(which means this CAF is already write to DRAM) ++//--------------------------------------------------------------------------- ++MS_U32 Hal_CMDQ_ErrorCommand(EN_CMDQ_IP_TYPE enIPType,MS_U32 select_bit) ++{ ++ MS_U32 reg_value=0; ++ MS_U32 Reg = 0; ++ MS_U32 Reg1 = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x43); ++ Reg1 = Hal_CMDQ_GetRegFromIPID(enIPType ,0x40); ++ W2BYTEMSK(Reg,select_bit , 0x0007); ++ reg_value= R2BYTE(Reg1); ++ return reg_value; ++ ++} ++ ++void Hal_CMDQ_Setmiusel(EN_CMDQ_IP_TYPE enIPType, MS_U8 u8MIUSel) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x10); ++ if (u8MIUSel == 0) ++ { ++ W2BYTEMSK(Reg, 0x0000, 0x0002); ++ } ++ else ++ { ++ W2BYTEMSK(Reg, 0x0002, 0x0002); ++ } ++} ++#if CMDQ_nonuse_Function ++/* ++MS_U32 Hal_CMDQ_Read_Start_Pointer(void) ++{ ++ MS_U32 reg_value=0; ++ reg_value=R4BYTE(REG_CMDQ_04_L); ++ return reg_value; ++} ++ ++MS_U32 Hal_CMDQ_Read_End_Pointer(void) ++{ ++ MS_U32 reg_value=0; ++ reg_value=R4BYTE(REG_CMDQ_06_L); ++ return reg_value; ++} ++*/ ++void Hal_CMDQ_Reset_Start_Pointer_bit(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x3); ++ W2BYTEMSK(Reg, 0x0004, 0x0004); ++} ++MS_U16 Hal_CMDQ_get_status(EN_CMDQ_IP_TYPE enIPType) ++{ ++ MS_U32 Reg = 0; ++ Reg = Hal_CMDQ_GetRegFromIPID(enIPType ,0x1); ++ return ((R2BYTE(Reg) & 0x0001)); ++} ++MS_BOOL Hal_CMDQ_Get_LDCtirg(void) ++{ ++ MS_U16 trig; ++ MS_BOOL ret; ++ trig=(R2BYTE(0x12183E)&0x0800)>>11; ++ ret= trig == 0x1 ? 0 :1; ++ return ret; ++} ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/halCMDQ.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/halCMDQ.h +new file mode 100644 +index 00000000..6016cb4d +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/halCMDQ.h +@@ -0,0 +1,173 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-20012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// file halCMDQ.h ++// @brief CMDQ HAL ++// @author MStar Semiconductor,Inc. ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++#ifndef __HAL_CMDQ_H__ ++#define __HAL_CMDQ_H__ ++ ++ ++ ++// Trigger Bus inverse mask ++#define isp2cmdq_frame_done 0xFFFE // 0 ++#define isp2cmdq_vs_r 0xFFFD // 1 ++#define sc2cmdq_lv_trig 0xFFFB // 2 ++#define cmdq_dma_finished 0xFFF7 // 3 ++ ++ ++#define MS_CMDQ_CMD_LEN 8 // 8byte =64bit ++#define MS_CMDQ_MEM_BASE_UNIT 16 // MIU 128bit ++#define MS_CMDQ_CMD_ALIGN 2 // (cmd/membase) ++#define MS_CMDQ_END_CMD 0x100802010000FFFE // nonuse ++#define MS_CMDQ_NULL_CMD 0x000000000000FFFF // null cmd ++#define MS_CMDQ_NULLTEST_CMD 0x00000000FFFFFFFF // null cmd ++#define MS_CMDQ_WRITE_CMD 0x1000000000000000 // write base head ++#define MS_CMDQ_ALLNULL_CMD 0x0000000000000000 // clean ++#define MS_CMDQ_WAIT_CMD 0x2000000000000000 // wait base head ++#define MS_CMDQ_POLL_EQ_CMD 0x3000000000000000 // polleq base head ++#define MS_CMDQ_POLL_NEQ_CMD 0xB000000000000000 // pollneq base head ++#define CMDQ_CRASH_15_0_BIT 0x0000 //0x43 bit:3 command[15:0] ++#define CMDQ_CRASH_31_16_BIT 0x0001 //0x43 bit:3 command[31:16] ++#define CMDQ_CRASH_55_32_BIT 0x0002 //0x43 bit:3 command[55:32] ++#define CMDQ_CRASH_63_56_BIT 0x0003 //0x43 bit:3 command[63:56] ++ ++//-------------------------------------------------------------------------------------------------- ++//-------------------------------------------------------------------------------------------------- ++// Macro of bit operations ++//-------------------------------------------------------------------------------------------------- ++ ++//////////////////////////////////////////////// ++// HAL ++//////////////////////////////////////////////// ++ ++; ++void Hal_CMDQ_SetBaseEn(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++void Hal_CMDQ_Reset(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++void Hal_CMDQ_SetTrigAlways(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_BOOL Hal_CMDQ_SetDMAMode(EN_CMDQ_IP_TYPE enIPType,int ModeSel); ++void Hal_CMDQ_SetStartPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 StartAddr); ++void Hal_CMDQ_SetEndPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 EndAddr); ++void Hal_CMDQ_SetOffsetPointer(EN_CMDQ_IP_TYPE enIPType,MS_U32 OffsetAddr); ++void Hal_CMDQ_SetTimer(EN_CMDQ_IP_TYPE enIPType,MS_U32 time); ++void Hal_CMDQ_SetRatio(EN_CMDQ_IP_TYPE enIPType,MS_U32 Ratio); ++void Hal_CMDQ_Start(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_U32 Hal_CMDQ_ErrorCommand(EN_CMDQ_IP_TYPE enIPType,MS_U32 select_bit); ++void Hal_CMDQ_Setmiusel(EN_CMDQ_IP_TYPE enIPType, MS_U8 u8MIUSel); ++void Hal_CMDQ_InitRIUBase(MS_U32 u32PM_riu_base); ++MS_U16 Hal_CMDQ_GetFinalIrq(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Mask); ++void Hal_CMDQ_SetRegPassWaitPoll(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_U16 Hal_CMDQ_GetRawIrq(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Mask); ++void Hal_CMDQ_Enable(EN_CMDQ_IP_TYPE enIPType,MS_BOOL bEn); ++MS_U32 Hal_CMDQ_GetMIUReadAddr(EN_CMDQ_IP_TYPE enIPType); ++void Hal_CMDQ_Set_Waittrig(EN_CMDQ_IP_TYPE enIPType,MS_U16 trig); ++void Hal_CMDQ_SetSkipPollWhenWaitTimeout(EN_CMDQ_IP_TYPE enIPType,MS_BOOL ben); ++void Hal_CMDQ_SetTimeoutAmount(EN_CMDQ_IP_TYPE enIPType); ++void Hal_CMDQ_WriteRegDirect(MS_U32 u32Addr,MS_U16 u16Data); ++void Hal_CMDQ_WriteRegMaskDirect(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask); ++void Hal_CMDQ_WriteRegMaskBuffer(MS_U32 u32Addr,MS_U16 u16Data,MS_U16 u16Mask); ++MS_U16 Hal_CMDQ_Read2ByteReg(MS_U32 u32Addr); ++MS_U16 Hal_CMDQ_Read2ByteMaskDirect(MS_U32 u32Addr,MS_U16 u16Mask); ++MS_U16 Hal_CMDQ_Get_ISP_Cnt(void); ++void Hal_CMDQ_ResetSoftInterrupt(EN_CMDQ_IP_TYPE enIPType); ++void Hal_CMDQ_ClearIRQByFlag(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16IRQ); ++void Hal_CMDQ_Reset_Start_Pointer_bit(EN_CMDQ_IP_TYPE enIPType); ++MS_U16 Hal_CMDQ_get_status(EN_CMDQ_IP_TYPE enIPType); ++MS_BOOL Hal_CMDQ_Get_LDCtirg(void); ++void Hal_CMDQ_SetISRMSK(EN_CMDQ_IP_TYPE enIPType,MS_U16 u16Msk); ++ ++ ++#endif // #ifndef _CMDQ_REG_MCU_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/regCMDQ.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/regCMDQ.h +new file mode 100644 +index 00000000..cab0c2cd +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/cmdq/regCMDQ.h +@@ -0,0 +1,181 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-20012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++// file: regCMDQ.h ++// Description: CMDQ Register Definition ++// @author MStar Semiconductor,Inc. ++//////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _CMDQ_REG_MCU_H_ ++#define _CMDQ_REG_MCU_H_ ++#include "MsTypes.h" ++ ++ ++//#include "MsCommon.h" ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Global Definition ++//-------------------------------------------------------------------------------------------------- ++ ++ ++ ++//-------------------------------------------------------------------------------------------------- ++// Compliation Option ++//-------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Harware Capability ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 _CMDQ_RIU_BASE; ++//============================================================= ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++#define RIU_READ_BYTE(addr) ( READ_BYTE( _CMDQ_RIU_BASE + (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( _CMDQ_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( _CMDQ_RIU_BASE + (addr), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( _CMDQ_RIU_BASE + (addr), val) ++ ++//============================================================= ++// Standard Form ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++ ++//============================================================= ++//CMDQ ++#ifndef REG_TABLE_END ++#define REG_TABLE_END 0xFFFF ++#endif ++ ++ ++#define CMDQ_CRASH_15_0_BIT 0x0000 //0x43 bit:3 command[15:0] ++#define CMDQ_CRASH_31_16_BIT 0x0001 //0x43 bit:3 command[31:16] ++#define CMDQ_CRASH_55_32_BIT 0x0002 //0x43 bit:3 command[55:32] ++#define CMDQ_CRASH_63_56_BIT 0x0003 //0x43 bit:3 command[63:56] ++ ++ ++ ++#endif // #ifndef _CMDQ_REG_MCU_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/halCHIP.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/halCHIP.h +new file mode 100644 +index 00000000..5023077f +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/halCHIP.h +@@ -0,0 +1,60 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _HAL_CHIP_H_ ++#define _HAL_CHIP_H_ ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#define ARM_CLOCK_FREQ 900000000 ++#define AEON_CLOCK_FREQ 240000000 ++#define XTAL_CLOCK_FREQ 12000000 ++ ++#define HAL_MIU1_BASE 0x60000000 // 1512MB ++#define HAL_MIU1_BUS_BASE 0xA0000000 // MIU1 Low 256MB ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++//void CHIP_InitISR(void); ++//MS_BOOL CHIP_InISRContext(void); ++//MS_BOOL CHIP_AttachISR(InterruptNum eIntNum, InterruptCb pIntCb); ++//MS_BOOL CHIP_DetachISR(InterruptNum eIntNum); ++//MS_BOOL CHIP_EnableIRQ(InterruptNum eIntNum); ++//MS_BOOL CHIP_DisableIRQ(InterruptNum eIntNum); ++//MS_BOOL CHIP_EnableAllInterrupt(void); ++//MS_BOOL CHIP_DisableAllInterrupt(void); ++ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _HAL_CHIP_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/halhvsp.c b/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/halhvsp.c +new file mode 100644 +index 00000000..ad0afa15 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/halhvsp.c +@@ -0,0 +1,2883 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_HVSP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsOS.h" ++// Internal Definition ++#include "hwreg.h" ++#include "halhvsp_utility.h" ++#include "drvhvsp_st.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "halhvsp.h" ++#include "drvCMDQ.h" ++#include "MsDbg.h" ++#include "mdrv_scl_dbg.h" ++#include "drvPQ_Define.h" ++#include "Infinity3e_Main.h" // table config parameter ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define HVSP_CMD_TRIG_BUFFER_SIZE 100 ++#define Is_InputSource(Src) (genIpType == (Src)) ++#define Is_CLK_Increase(height,width,rate) (((height) > 720 || (width) > 1280)&& (rate) < 172000000) ++#define Is_CLK_Decrease(height,width,rate) (((height) <= 720 && (width) <= 1280)&& (rate) >= 172000000) ++#define Is_Reg_Type(type) (gstHvspCmdTrigCfg.enType == (type)) ++#define Is_IP_First_Set(ip) (gbhvspset[(ip)]==0) ++#define HAL_HVSP_RATIO(input, output) ((MS_U32)((MS_U64)((input) * 1048576) / (output))) ++#define DISABLE_CLK 0x1 ++#define LOW_CLK 0x4 ++#define LOCK_FB() (gblockfbmg) ++#define _SetHVSPType(ID,u8type) (gstSclFea[(ID)].u16ModeYCVH |= (u8type)) ++#define _ReSetHVSPType(ID,u8type) (gstSclFea[(ID)].u16ModeYCVH &= ~(u8type)) ++#define Is_CannotUseCMDQToSetReg() (gbUseCMDQ == 0) ++ ++typedef struct ++{ ++ MS_U32 u32Reg; ++ MS_U16 u16Msk; ++ MS_U16 u16Val; ++}ST_HVSP_CMD_TRIG_BUFFER_TYPE; ++ ++typedef struct ++{ ++ ST_HVSP_CMD_TRIG_BUFFER_TYPE stCmdTrigBuf[HVSP_CMD_TRIG_BUFFER_SIZE]; ++ MS_U16 u16Idx; ++}ST_HVSP_CMD_TRIG_BUFFER_CONFIG; ++ ++typedef struct ++{ ++ MS_U16 u16ModeYCVH; ++ MS_U16 u16DithCoring; ++}ST_HVSP_SCALING_FEATURE_CONFIG; ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_U32 HVSP_RIU_BASE; ++///////////////// ++/// gstHvspCmdTrigCfg ++/// To save set Register type and used in scaling function. ++//////////////// ++ST_HVSP_CMD_TRIG_CONFIG gstHvspCmdTrigCfg; ++///////////////// ++/// gstHvspCmdTrigBufCfg ++/// To save CMD and used in scaling function. ++//////////////// ++ST_HVSP_CMD_TRIG_BUFFER_CONFIG gstHvspCmdTrigBufCfg; ++///////////////// ++/// genIpType ++/// To save Input Source Type. ++//////////////// ++EN_HVSP_IP_MUX_TYPE genIpType; ++///////////////// ++/// gu16height ++/// To save resolution and used in dynamic change clk. ++//////////////// ++MS_U16 gu16height[2]={0,0}; ++///////////////// ++/// gu16height ++/// To save resolution and used in dynamic change clk. ++//////////////// ++MS_U16 gu16width[2]={0,0}; ++///////////////// ++/// genFilterMode ++/// To save scaling type for handle CMDQ can't mask issue. ++//////////////// ++EN_HVSP_FILTER_MODE genFilterMode; ++///////////////// ++/// gbhvspset ++/// The first time set HVSP scaling config can't use CMDQ(no sync to trig),so need to save this information. ++//////////////// ++MS_BOOL gbhvspset[E_HVSP_ID_MAX]={0,0,0}; ++ST_HVSP_SCALING_FEATURE_CONFIG gstSclFea[E_HVSP_ID_MAX]; ++MS_BOOL gbUseCMDQ; ++MS_BOOL gbResetDNR; ++MS_BOOL gblockfbmg = 0; ++ST_HVSP_SIZE_CONFIG gstHalSrcSize; ++MS_BOOL gbSramCMDQ = 0; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_Exit(void) ++{ ++ gblockfbmg = 0; ++ genIpType = E_HVSP_IP_MUX_ISP; ++ genFilterMode = E_HVSP_FILTER_MODE_BYPASS; ++ gu16width[0]=0; ++ gu16height[0]=0; ++ gu16width[1]=0; ++ gu16height[1]=0; ++ MsOS_Memset(&gstHvspCmdTrigCfg, 0,sizeof(ST_HVSP_CMD_TRIG_CONFIG)); ++ MsOS_Memset(&gstHvspCmdTrigBufCfg, 0,sizeof(ST_HVSP_CMD_TRIG_BUFFER_CONFIG)); ++} ++//============CLK================================ ++#if CONFIG_OF ++void Hal_HVSP_SetIdclkOnOff(MS_BOOL bEn,ST_HVSP_CLK_CONFIG* stclk) ++{ ++ struct clk* pstclock = NULL; ++ MS_U32 u32Events; ++ if(Drv_SCLIRQ_GetEachDMAEn()||(!Drv_SCLIRQ_GetIsBlankingRegion())) ++ { ++ SCL_ERR("[IDCLK]%s %d,Wait\n", __FUNCTION__, __LINE__); ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ (E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC), &u32Events, E_AND, 200); // get status: FRM END ++ } ++ if(bEn) ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ if (MsOS_clk_get_enable_count(stclk->idclk)==0) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->idclk, 1))) ++ { ++ MsOS_clk_set_parent(stclk->idclk, pstclock); ++ MsOS_clk_prepare_enable(stclk->idclk); ++ //printf("[idclk]enable count=%d\n", MsOS_clk_get_enable_count(stclk->idclk)); ++ } ++ else ++ { ++ printf("[idclk]BT656 NULL\n"); ++ ++ } ++ } ++ } ++ else ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ if (MsOS_clk_get_enable_count(stclk->idclk)==0) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->idclk, 0))) ++ { ++ MsOS_clk_set_parent(stclk->idclk, pstclock); ++ MsOS_clk_prepare_enable(stclk->idclk); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ } ++ } ++ } ++ else ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0100,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0005,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->idclk, 0))) ++ { ++ MsOS_clk_set_parent(stclk->idclk, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ while (MsOS_clk_get_enable_count(stclk->idclk)) ++ { ++ MsOS_clk_disable_unprepare(stclk->idclk); ++ } ++ } ++ else ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0001,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->idclk, 0))) ++ { ++ MsOS_clk_set_parent(stclk->idclk, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ while (MsOS_clk_get_enable_count(stclk->idclk)) ++ { ++ MsOS_clk_disable_unprepare(stclk->idclk); ++ } ++ } ++ ++ } ++} ++void Hal_HVSP_SetCLKRate(unsigned char u8Idx) ++{ ++ if((u8Idx &EN_HVSP_CLKATTR_BT656))//BT656 ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ } ++ else if((u8Idx &EN_HVSP_CLKATTR_ISP))//ISP ++ { ++ printf("[hal]ISP xxxxxxxxx\n"); ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ } ++ if((u8Idx &EN_HVSP_CLKATTR_FORCEMODE)) ++ { ++ printf("[hal]FORCEMODE xxxxxxxxx\n"); ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++} ++ ++void Hal_HVSP_FCLK1(ST_HVSP_CLK_CONFIG *stclk) ++{ ++#if CLKDynamic ++ struct clk* pstclock = NULL; ++ if (MsOS_clk_get_enable_count(stclk->fclk1)==0) ++ { ++ } ++ else ++ { ++ if(Is_CLK_Increase(gu16height[0],gu16width[0],MsOS_clk_get_rate(stclk->fclk1))) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #if OSDinverseBug ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #endif ++ } ++ else if(Is_CLK_Decrease(gu16height[0],gu16width[0],MsOS_clk_get_rate(stclk->fclk1))) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #if OSDinverseBug ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #endif ++ } ++ } ++#endif ++} ++ ++void Hal_HVSP_FCLK2(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ #if OSDinverseBug ++ #else ++ struct clk* pstclock = NULL; ++ if (MsOS_clk_get_enable_count(stclk->fclk2)==0) ++ { ++ } ++ else ++ { ++ if(Is_CLK_Increase(gu16height[1],gu16width[1],MsOS_clk_get_rate(stclk->fclk2))) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ //printf("[HVSP]CLK UP\n"); ++ } ++ else if(Is_CLK_Decrease(gu16height[1],gu16width[1],MsOS_clk_get_rate(stclk->fclk2))) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ //printf("[HVSP]CLK down\n"); ++ } ++ } ++#endif ++} ++ ++#else ++void Hal_HVSP_SetIdclkOnOff(MS_BOOL bEn,ST_HVSP_CLK_CONFIG* stclk) ++{ ++ printf("[hal]NO OF\n"); ++ if(bEn) ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ if ((R2BYTE(REG_SCL_CLK_63_L)&DISABLE_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0004,0x000F);//h63 ++ } ++ } ++ else ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ if ((R2BYTE(REG_SCL_CLK_63_L)&DISABLE_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0000,0x000F);//h63 ++ } ++ } ++ ++ } ++ else ++ { ++ if(Is_InputSource(E_HVSP_IP_MUX_PAT_TGEN)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0100,0x0F00);//h61 ++ } ++ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656)) ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0005,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0005,0x000F);//h63 ++ } ++ else ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0001,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_SCL_CLK_63_L,0x0001,0x000F);//h63 ++ } ++ ++ } ++} ++void Hal_HVSP_SetCLKRate(unsigned char u8Idx) ++{ ++ if((u8Idx &EN_HVSP_CLKATTR_BT656))//BT656 ++ { ++ W2BYTEMSK(REG_BLOCK_24_L,0x0004,0x0005);//idclk ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0010,0x0010);//ccir mode ++ } ++ else if((u8Idx &EN_HVSP_CLKATTR_ISP))//ISP ++ { ++ printf("[hal]ISP xxxxxxxxx\n"); ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0010);//ccir mode ++ W2BYTEMSK(REG_BLOCK_24_L,0x0000,0x0005);//idclk ++ } ++ if((u8Idx &EN_HVSP_CLKATTR_FORCEMODE)) ++ { ++ printf("[hal]FORCEMODE xxxxxxxxx\n"); ++ W2BYTEMSK(REG_SCL_CLK_61_L,0x0000,0x0F00);//h61 ++ } ++} ++ ++void Hal_HVSP_FCLK1(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ if ((R2BYTE(REG_SCL_CLK_64_L)&DISABLE_CLK)) ++ { ++ } ++ else ++ { ++ if((gu16height[0]>720||gu16width[0]>1280) && (R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//h61 ++ } ++ else if((gu16height[0]<=720 && ,gu16width[0]<=1280)&& !(R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,LOW_CLK,0x000F);//h61 ++ } ++ } ++ ++} ++ ++void Hal_HVSP_FCLK2(ST_HVSP_CLK_CONFIG *stclk) ++{ ++ if ((R2BYTE(REG_SCL_CLK_65_L)&DISABLE_CLK)) ++ { ++ } ++ else ++ { ++ if((gu16height[1]>720||gu16width[1]>1280) && (R2BYTE(REG_SCL_CLK_65_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0000,0x000F);//h61 ++ } ++ else if((gu16height[1]<=720 && ,gu16width[1]<=1280) && !(R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,LOW_CLK,0x000F);//h61 ++ } ++ } ++} ++ ++ ++#endif ++ ++//=========================================================== ++void Hal_HVSP_SetFrameBufferManageLock(MS_BOOL bEn) ++{ ++ gblockfbmg = bEn; ++} ++void Hal_HVSP_SetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG *stCmdTrigCfg) ++{ ++ gbUseCMDQ = Drv_SCLIRQ_GetEachDMAEn(); ++ gstHvspCmdTrigCfg.enType = stCmdTrigCfg->enType; ++ gstHvspCmdTrigCfg.u8Fmcnt = stCmdTrigCfg->u8Fmcnt; ++} ++void Hal_HVSP_SetResetDNR(MS_BOOL bEn) ++{ ++ gbResetDNR = bEn; ++} ++void Hal_HVSP_GetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG *pCfg) ++{ ++ MsOS_Memcpy(pCfg, &gstHvspCmdTrigCfg, sizeof(ST_HVSP_CMD_TRIG_CONFIG)); ++} ++ ++void Hal_HVSP_SetCMDQTrigFrameCnt(MS_U16 u16Idx) ++{ ++ gstHvspCmdTrigBufCfg.u16Idx = u16Idx; ++} ++ ++void Hal_HVSP_SetCMDQTrigFire(void) ++{ ++ MS_U16 i; ++ MS_CMDQ_CMDReg stCfg; ++#if SCALING_BLOCK ++ MS_U32 u32Events = 0; ++#endif ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ //printf("[HVSP]Hal_HVSP_SetCMDQTrigFire gstHvspCmdTrigCfg.enType:%d \n",gstHvspCmdTrigCfg.enType); ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_CMDQ_LDC_SYNC)) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ for(i=0; i< gstHvspCmdTrigBufCfg.u16Idx; i++) ++ { ++ Drv_CMDQ_FillCmd(&stCfg, gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u32Reg, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Val, gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Msk); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,0); ++ } ++ if(gbResetDNR) ++ { ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_BRESETDNR); ++ gbResetDNR = 0; ++ } ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_CHANGESIZEDONE)); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_SETCHANGESIZE); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ #if SCALING_BLOCK ++ if(gstHvspCmdTrigBufCfg.u16Idx &&Drv_SCLIRQ_GetEachDMAEn()) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_CHANGESIZEDONE, &u32Events, E_OR, MSOS_WAIT_FOREVER); ++ MsOS_ClearEventIRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(),(E_SCLIRQ_EVENT_CHANGESIZEDONE)); ++ } ++ #endif ++ } ++ else if(Is_Reg_Type(E_HVSP_CMD_TRIG_POLL_LDC_SYNC)) ++ { ++ for(i=0; i< gstHvspCmdTrigBufCfg.u16Idx; i++) ++ { ++ W2BYTEMSK(gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u32Reg, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Val, ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[i].u16Msk); ++ } ++ } ++ ++} ++ ++ ++MS_BOOL _Hal_HVSP_Write_Cmd(MS_U32 u32Reg, MS_U16 u16Val, MS_U16 u16Msk) ++{ ++ MS_U16 u16idx = gstHvspCmdTrigBufCfg.u16Idx; ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[u16idx].u32Reg = u32Reg; ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[u16idx].u16Msk = u16Msk; ++ gstHvspCmdTrigBufCfg.stCmdTrigBuf[u16idx].u16Val = u16Val; ++ //printf("[HVSP]_Hal_HVSP_Write_Cmd u32Reg:%lx u16Msk:%hx u16Val:%hx \n",u32Reg,u16Msk,u16Val); ++ gstHvspCmdTrigBufCfg.u16Idx++; ++ if(gstHvspCmdTrigBufCfg.u16Idx >= HVSP_CMD_TRIG_BUFFER_SIZE) ++ { ++ gstHvspCmdTrigBufCfg.u16Idx = HVSP_CMD_TRIG_BUFFER_SIZE-1; ++ SCL_ERR("[HVSP]CMDQ FULL\n"); ++ return FALSE; ++ } ++ else ++ { ++ return TRUE; ++ } ++} ++ ++void Hal_HVSP_SetRiuBase(MS_U32 u32RiuBase) ++{ ++ HVSP_RIU_BASE = u32RiuBase; ++} ++void Hal_HVSP_SetInputSrcSize(ST_HVSP_SIZE_CONFIG *stSrc) ++{ ++ MsOS_Memcpy(&gstHalSrcSize,stSrc,sizeof(ST_HVSP_SIZE_CONFIG) ); ++} ++ ++void Hal_HVSP_Set_Reset(void) ++{ ++ gbhvspset[0]= 0; ++ gbhvspset[1]= 0; ++ gbhvspset[2]= 0; ++ gbUseCMDQ = 0; ++ gstSclFea[0].u16ModeYCVH= 0; ++ gstSclFea[1].u16ModeYCVH= 0; ++ gstSclFea[2].u16ModeYCVH= 0; ++ gstSclFea[0].u16DithCoring= 0; ++ gstSclFea[1].u16DithCoring= 0; ++ gstSclFea[2].u16DithCoring= 0; ++ Hal_HVSP_SetNLMEn(0); ++ //Hal_HVSP_SetHWInputMux(E_HVSP_IP_MUX_BT656); ++ W2BYTEMSK(REG_SCL2_50_L, 0, BIT0);//crop1 ++ W2BYTEMSK(REG_SCL2_58_L, 0, BIT0);//crop2 ++ Hal_HVSP_SetIPMYCMReadEn(0); ++ Hal_HVSP_SetIPMYCMWriteEn(0); ++ Hal_HVSP_SetIPMCIIRReadEn(0); ++ Hal_HVSP_SetIPMCIIRWriteEn(0); ++ Hal_HVSP_SetLDCPathSel(0); ++ Hal_HVSP_SetLDCBypass(1); ++ Hal_HVSP_SetPrv2CropOnOff(0); ++ Hal_HVSP_PriMask_bEn(EN_HVSP_TRIGGER_OFF); ++ Hal_HVSP_Set_DNR_Reset(1); ++ Hal_HVSP_Set_SW_Reset(1); ++} ++void Hal_HVSP_Set_CLKOFF(void) ++{ ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0001,0x000F);// ToDo ++} ++void Hal_HVSP_SetVIPSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_LCE_6E_L, u16Width, 0x0FFF); ++ W2BYTEMSK(REG_VIP_LCE_6F_L, u16Height, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_LCE_6E_L, u16Width, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_LCE_6F_L, u16Height, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetWDRGlobalSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_WDR_35_L, u16Width-1, 0x0FFF); ++ W2BYTEMSK(REG_VIP_WDR_36_L, u16Height-1, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_WDR_35_L, u16Width-1, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_WDR_36_L, u16Height-1, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetWDRLocalSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_WDR_7C_L, u16Width-1, 0x0FFF); ++ W2BYTEMSK(REG_VIP_WDR_7D_L, u16Height-1, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_WDR_7C_L, u16Width-1, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_WDR_7D_L, u16Height-1, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetMXNRSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_SCNR_0A_L, u16Width -1, 0x0FFF); ++ W2BYTEMSK(REG_VIP_SCNR_0B_L, u16Height -1, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_0A_L, u16Width -1, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_0B_L, u16Height -1, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetUVadjSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_SCNR_3B_L, u16Width-1, 0x0FFF); ++ W2BYTEMSK(REG_VIP_SCNR_3C_L, u16Height-1, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_3B_L, u16Width-1, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_3C_L, u16Height-1, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetXNRSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_SCNR_5C_L, u16Width-1, 0x0FFF); ++ W2BYTEMSK(REG_VIP_SCNR_5D_L, u16Height-1, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_5C_L, u16Width-1, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_5D_L, u16Height-1, 0x1FFF); ++ } ++} ++void Hal_HVSP_PriMask_Width(MS_U16 u16W) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTE(REG_VIP_SCNR_15_L, u16W-1); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_15_L, u16W-1, 0x0FFF); ++ } ++} ++void Hal_HVSP_PriMask_Height(MS_U16 u16H) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTE(REG_VIP_SCNR_16_L, u16H-1); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_16_L, u16H-1, 0x0FFF); ++ } ++} ++ ++void Hal_HVSP_Set_SW_Reset(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_01_L, bEn ? BIT0 : 0, BIT0); ++ W2BYTEMSK(REG_SCL0_01_L, 0, BIT0); ++} ++void Hal_HVSP_Set_DNR_Reset(MS_BOOL bEn) ++{ ++// for issue reset rstz_ctrl_clk_miu_sc_dnr cause to overwrite 0x0 ++ W2BYTEMSK(REG_SCL_DNR1_24_L, bEn ? BIT6 : 0, BIT6); ++ W2BYTEMSK(REG_SCL_DNR1_60_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++void Hal_HVSP_SetNLMLineBufferSize(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ W2BYTEMSK(REG_SCL0_19_L, 0x8000, 0x8000); ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL0_1A_L, u16Width, 0x0FFF); ++ W2BYTEMSK(REG_SCL0_1B_L, u16Height, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL0_1A_L, u16Width, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL0_1B_L, u16Height, 0x1FFF); ++ } ++} ++ ++void Hal_HVSP_SetNLMEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_18_L, bEn ? BIT0 : 0, BIT0); ++} ++void Hal_HVSP_SetVpsSRAMEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_VIP_PK_10_L, bEn ? BIT7 : 0, BIT7); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Crop ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_SetBT656SrcConfig(MS_BOOL bEn,MS_U16 u16Lineoffset) ++{ ++ if(Is_InputSource(E_HVSP_IP_MUX_BT656) ) ++ { ++ W2BYTEMSK(REG_SCL0_61_L, bEn ? BIT7 : 0, BIT7); ++ W2BYTEMSK(REG_SCL0_63_L, u16Lineoffset, 0x07FF); ++ W2BYTEMSK(REG_SCL0_62_L, 8, 0x07FF); ++ } ++} ++ ++ ++void Hal_HVSP_SetCropConfig(EN_HVSP_CROP_ID_TYPE enID, ST_HVSP_CROP_INFO *stCropInfo) ++{ ++ MS_U32 u32reg_idx = enID == E_HVSP_CROP_ID_1 ? 0x00 : 0x10; ++ ++ //Crop01: 0x50 ++ //Crop02: 0x58 ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ if((stCropInfo->u16In_hsize == stCropInfo->u16Hsize) && (stCropInfo->u16Vsize == stCropInfo->u16In_vsize)) ++ { ++ W2BYTEMSK(REG_SCL2_50_L + u32reg_idx, 0, BIT0); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL2_50_L + u32reg_idx, stCropInfo->bEn ? BIT0 : 0, BIT0); ++ } ++ W2BYTEMSK(REG_SCL2_51_L + u32reg_idx, stCropInfo->u16In_hsize, 0x0FFF); ++ W2BYTEMSK(REG_SCL2_52_L + u32reg_idx, stCropInfo->u16In_vsize, 0x0FFF); ++ W2BYTEMSK(REG_SCL2_53_L + u32reg_idx, stCropInfo->u16Hst, 0x0FFF); ++ W2BYTEMSK(REG_SCL2_54_L + u32reg_idx, stCropInfo->u16Hsize, 0x0FFF); ++ W2BYTEMSK(REG_SCL2_55_L + u32reg_idx, stCropInfo->u16Vst, 0x0FFF); ++ W2BYTEMSK(REG_SCL2_56_L + u32reg_idx, stCropInfo->u16Vsize, 0x0FFF); ++ } ++ else ++ { ++ if((stCropInfo->u16In_hsize == stCropInfo->u16Hsize) && (stCropInfo->u16Vsize == stCropInfo->u16In_vsize)) ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL2_50_L + u32reg_idx, 0, BIT0); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL2_50_L + u32reg_idx, stCropInfo->bEn ? BIT0 : 0, BIT0); ++ } ++ _Hal_HVSP_Write_Cmd(REG_SCL2_51_L + u32reg_idx, stCropInfo->u16In_hsize, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_52_L + u32reg_idx, stCropInfo->u16In_vsize, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_53_L + u32reg_idx, stCropInfo->u16Hst, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_54_L + u32reg_idx, stCropInfo->u16Hsize, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_55_L + u32reg_idx, stCropInfo->u16Vst, 0x0FFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL2_56_L + u32reg_idx, stCropInfo->u16Vsize, 0x0FFF); ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++// IP Mux ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_SetInputMuxType(EN_HVSP_IP_MUX_TYPE enIpType) ++{ ++ genIpType = enIpType; ++} ++ ++EN_HVSP_IP_MUX_TYPE Hal_HVSP_GetInputSrcMux(void) ++{ ++ return genIpType; ++} ++ ++void Hal_HVSP_SetHWInputMux(EN_HVSP_IP_MUX_TYPE enIpType) ++{ ++ W2BYTEMSK(REG_SCL0_60_L, enIpType == E_HVSP_IP_MUX_BT656 ? 0 : BIT0, BIT0); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++// IPM ++//------------------------------------------------------------------------------------------------- ++void Hal_HVSP_SetIPMYCMReadEn(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++void Hal_HVSP_SetIPMYCMWriteEn(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT1 : 0, BIT1); ++} ++void Hal_HVSP_SetIPMCIIRReadEn(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT2 : 0, BIT2); ++} ++ ++void Hal_HVSP_SetIPMCIIRWriteEn(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT3 : 0, BIT3); ++} ++ ++void Hal_HVSP_SetIPMYCBase(MS_U32 u32Base) ++{ ++ MS_U16 u16Base_Lo, u16Base_Hi; ++ u32Base = u32Base>>4; ++ u16Base_Lo = u32Base & 0xFFFF; ++ u16Base_Hi = (u32Base & 0x07FF0000) >> 16; ++ W2BYTE(REG_SCL_DNR1_08_L, u16Base_Lo); ++ W2BYTE(REG_SCL_DNR1_09_L, u16Base_Hi); ++} ++void Hal_HVSP_SetIPMMotionBase(MS_U32 u32Base) ++{ ++ MS_U16 u16Base_Lo, u16Base_Hi; ++ u32Base = u32Base>>4; ++ u16Base_Lo = u32Base & 0xFFFF; ++ u16Base_Hi = (u32Base & 0x07FF0000) >> 16; ++ W2BYTE(REG_SCL_DNR1_10_L, u16Base_Lo); ++ W2BYTE(REG_SCL_DNR1_11_L, u16Base_Hi); ++} ++void Hal_HVSP_SetIPMCIIRBase(MS_U32 u32Base) ++{ ++ MS_U16 u16Base_Lo, u16Base_Hi; ++ u32Base = u32Base>>4; ++ u16Base_Lo = u32Base & 0xFFFF; ++ u16Base_Hi = (u32Base & 0x07FF0000) >> 16; ++ W2BYTE(REG_SCL_DNR1_18_L, u16Base_Lo); ++ W2BYTE(REG_SCL_DNR1_19_L, u16Base_Hi); ++} ++ ++#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_Set_IPM_Read_Req(MS_U8 u8Thrd, MS_U8 u8Limit) ++{ ++ W2BYTE(REG_SCL_DNR1_0A_L, ((((MS_U16)u8Limit)<<8) | ((MS_U16)u8Thrd))); ++} ++ ++void Hal_HVSP_Set_IPM_Write_Req(MS_U8 u8Thrd, MS_U8 u8Limit) ++{ ++ W2BYTE(REG_SCL_DNR1_0B_L, ((((MS_U16)u8Limit)<<8) | ((MS_U16)u8Thrd))); ++} ++#endif ++ ++void Hal_HVSP_SetIPMvSize(MS_U16 u16Vsize) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_0D_L, u16Vsize, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_0D_L, u16Vsize, 0x1FFF); ++ } ++ gu16height[0] = u16Vsize; ++} ++ ++void Hal_HVSP_SetIPMLineOffset(MS_U16 u16Lineoffset) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_0E_L, u16Lineoffset, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_0E_L, u16Lineoffset, 0x1FFF); ++ } ++ gu16width[0] = u16Lineoffset; ++} ++ ++void Hal_HVSP_SetIPMFetchNum(MS_U16 u16FetchNum) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_0F_L, u16FetchNum, 0x1FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_0F_L, u16FetchNum, 0x1FFF); ++ } ++} ++void Hal_HVSP_SetIPMBufferNumber(MS_U8 u8Num) ++{ ++ if(!LOCK_FB()) ++ W2BYTEMSK(REG_SCL_DNR1_02_L, u8Num , 0x7); ++} ++ ++//------------------------------------------------------------------------------------------------- ++// Scaling ++//------------------------------------------------------------------------------------------------- ++ ++void Hal_HVSP_SetScalingVeEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0A_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0A_L : ++ REG_SCL_HVSP0_0A_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++} ++void Hal_HVSP_SetScalingVeFactor(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_09_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_09_L : ++ REG_SCL_HVSP0_09_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W3BYTE(u32reg, u32Ratio); ++ } ++ else ++ { ++ MS_U16 u16val_L = u32Ratio & 0xFFFF; ++ MS_U16 u16val_H = (u32Ratio >> 16) & 0x00FF; ++ if(u32Ratio) ++ { ++ u16val_H=(u16val_H|0x0100); ++ } ++ _Hal_HVSP_Write_Cmd(u32reg, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(u32reg+2, u16val_H, 0x01FF); ++ } ++} ++ ++void Hal_HVSP_SetScalingHoEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_08_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_08_L : ++ REG_SCL_HVSP0_08_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, ben ? BIT8 : 0, BIT8); ++ } ++} ++ ++void Hal_HVSP_SetScalingHoFacotr(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_07_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_07_L : ++ REG_SCL_HVSP0_07_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W3BYTE(u32reg, u32Ratio); ++ } ++ else ++ { ++ MS_U16 u16val_L = u32Ratio & 0xFFFF; ++ MS_U16 u16val_H = (u32Ratio >> 16) & 0x00FF; ++ if(u32Ratio) ++ { ++ u16val_H=(u16val_H|0x0100); ++ } ++ _Hal_HVSP_Write_Cmd(u32reg, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(u32reg+2, u16val_H, 0x01FF); ++ } ++} ++void Hal_HVSP_SetModeYHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ genFilterMode=enFilterMode; ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? 0 : BIT0, BIT0); ++ W2BYTEMSK(u32reg, (enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 || enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ? BIT6 : 0, BIT6); ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_1 ? BIT7 : 0, BIT7); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bBypass ? 0 : BIT0, BIT0); ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT0|BIT6|BIT7); ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT0); ++ _ReSetHVSPType(enID,BIT6|BIT7); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT0|BIT6); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT7); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT7); ++ } ++ } ++ } ++} ++ ++void Hal_HVSP_SetModeYVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? 0 : BIT8, BIT8); ++ W2BYTEMSK(u32reg, (enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 || enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ? BIT14 : 0, BIT14); ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_1 ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT15|BIT14|BIT8); ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT8); ++ _ReSetHVSPType(enID,BIT14|BIT15); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT8|BIT14); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT15); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT15); ++ } ++ } ++ //_Hal_HVSP_Write_Cmd(u32reg, bBypass ? 0 : BIT8, BIT8); ++ } ++} ++ ++void Hal_HVSP_SetModeCHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS || enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? (0<<1) : (1<<1), (BIT3|BIT2|BIT1)); ++ W2BYTEMSK(u32reg, 0x0000, BIT4); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<5) : (1<<5), BIT5); //ram_sel ++ } ++ else ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 ? (2<<1) : (3<<1), (BIT3|BIT2|BIT1)); ++ W2BYTEMSK(u32reg, BIT4, BIT4); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<5) : (1<<5), BIT5); //ram_sel ++ } ++ } ++ else ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT3|BIT2|BIT1|BIT4); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT5); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT5); ++ } ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT1); ++ _ReSetHVSPType(enID,BIT3|BIT2|BIT4); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT5); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT5); ++ } ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT4|BIT2); ++ _ReSetHVSPType(enID,BIT3); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT1); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT1); ++ } ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT5); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT5); ++ } ++ } ++ } ++} ++ ++void Hal_HVSP_SetModeCVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0B_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0B_L : ++ REG_SCL_HVSP0_0B_L; ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS || enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_BYPASS ? (0<<9) : (1<<9), (BIT11|BIT10|BIT9)); ++ W2BYTEMSK(u32reg, 0x0000, BIT12); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<13) : (1<<13), BIT13); //ram_sel ++ } ++ else ++ { ++ W2BYTEMSK(u32reg, enFilterMode == E_HVSP_FILTER_MODE_SRAM_0 ? (2<<9) : (3<<9), (BIT11|BIT10|BIT9)); ++ W2BYTEMSK(u32reg, BIT12, BIT12); // ram_en ++ W2BYTEMSK(u32reg, enSramSel == E_HVSP_SRAM_SEL_0 ? (0<<13) : (1<<13), BIT13); //ram_sel ++ } ++ } ++ else ++ { ++ if(enFilterMode == E_HVSP_FILTER_MODE_BYPASS) ++ { ++ _ReSetHVSPType(enID,BIT9|BIT10|BIT11|BIT12); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT13); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT13); ++ } ++ } ++ else if(enFilterMode == E_HVSP_FILTER_MODE_BILINEAR) ++ { ++ _SetHVSPType(enID,BIT9); ++ _ReSetHVSPType(enID,BIT10|BIT11|BIT12); ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT13); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT13); ++ } ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT10|BIT12); ++ _ReSetHVSPType(enID,BIT11); ++ if(enFilterMode == E_HVSP_FILTER_MODE_SRAM_1) ++ { ++ _SetHVSPType(enID,BIT9); ++ } ++ else ++ { ++ _ReSetHVSPType(enID,BIT9); ++ } ++ if(enSramSel == E_HVSP_SRAM_SEL_0) ++ { ++ _ReSetHVSPType(enID,BIT13); ++ } ++ else ++ { ++ _SetHVSPType(enID,BIT13); ++ } ++ } ++ _Hal_HVSP_Write_Cmd(u32reg,gstSclFea[enID].u16ModeYCVH,0xFFFF); ++ } ++ ++} ++ ++void Hal_HVSP_SetHspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT0) : (0), BIT0); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT0) : (0), BIT0); ++ } ++} ++ ++ ++void Hal_HVSP_SetVspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT1) : (0), BIT1); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT1) : (0), BIT1); ++ } ++} ++ ++void Hal_HVSP_SetHspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT8) : (0), BIT8); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT8) : (0), BIT8); ++ } ++} ++ ++void Hal_HVSP_SetHspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT9) : (0), BIT9); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT11|BIT10|BIT9|BIT8|BIT1|BIT0) : (0), BIT11|BIT10|BIT9|BIT8|BIT1|BIT0); ++ } ++} ++ ++void Hal_HVSP_SetVspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT10) : (0), BIT10); ++ } ++ else ++ { ++ //_Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT10) : (0), BIT10); ++ } ++} ++ ++void Hal_HVSP_SetVspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0C_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0C_L : ++ REG_SCL_HVSP0_0C_L; ++ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(enID)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(u32reg, bEn ? (BIT11) : (0), BIT11); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(u32reg, bEn ? (BIT11|BIT10|BIT9|BIT8|BIT1|BIT0) : (0), BIT11|BIT10|BIT9|BIT8|BIT1|BIT0); ++ } ++} ++ ++void Hal_HVSP_SetHspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0D_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0D_L : ++ REG_SCL_HVSP0_0D_L; ++ ++ W2BYTEMSK(u32reg, u16Thread, 0x00FF); ++} ++ ++void Hal_HVSP_SetHspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0D_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0D_L : ++ REG_SCL_HVSP0_0D_L; ++ ++ W2BYTEMSK(u32reg, u16Thread<<8, 0xFF00); ++} ++ ++void Hal_HVSP_SetVspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0E_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0E_L : ++ REG_SCL_HVSP0_0E_L; ++ ++ W2BYTEMSK(u32reg, u16Thread, 0x00FF); ++} ++ ++void Hal_HVSP_SetVspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread) ++{ ++ MS_U32 u32reg = enID == E_HVSP_ID_2 ? REG_SCL_HVSP1_0E_L : ++ enID == E_HVSP_ID_3 ? REG_SCL_HVSP2_0E_L : ++ REG_SCL_HVSP0_0E_L; ++ ++ W2BYTEMSK(u32reg, u16Thread<<8, 0xFF00); ++} ++#if ENABLE_HVSP_UNUSED_FUNCTION ++ ++void Hal_HVSP_Set_Hvsp_Sram_Coeff(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_SRAM_SEL_TYPE enSramSel, MS_BOOL bC_SRAM, MS_U8 *pData) ++{ ++ MS_U32 u32reg_41, u32reg_42, u32reg_43; ++ MS_U8 u8Ramcode[10]; ++ MS_U16 u16IdxBase = 0; ++ MS_U16 i, j, x; ++ ++ if(enID == E_HVSP_ID_2) ++ { ++ u32reg_41 = REG_SCL_HVSP1_41_L; ++ u32reg_42 = REG_SCL_HVSP1_42_L; ++ u32reg_43 = REG_SCL_HVSP1_43_L; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u32reg_41 = REG_SCL_HVSP2_41_L; ++ u32reg_42 = REG_SCL_HVSP2_42_L; ++ u32reg_43 = REG_SCL_HVSP2_43_L; ++ } ++ else ++ { ++ u32reg_41 = REG_SCL_HVSP0_41_L; ++ u32reg_42 = REG_SCL_HVSP0_42_L; ++ u32reg_43 = REG_SCL_HVSP0_43_L; ++ } ++ ++ u16IdxBase = enSramSel == E_HVSP_FILTER_SRAM_SEL_1 ? 0x00 : ++ enSramSel == E_HVSP_FILTER_SRAM_SEL_2 ? 0x40 : ++ enSramSel == E_HVSP_FILTER_SRAM_SEL_3 ? 0x80 : ++ 0xC0 ; ++ ++ W2BYTEMSK(u32reg_41, bC_SRAM ? BIT1 : BIT0, BIT1|BIT0); // reg_cram_rw_en ++ ++ for(i=0; i<64; i++) ++ { ++ while(R2BYTE(u32reg_41) & BIT8); ++ j=i*5; ++ ++ W2BYTEMSK(u32reg_42,(i|u16IdxBase), 0x00FF); ++ for ( x=0;x<5;x++ ) ++ { ++ u8Ramcode[x] = pData[j+x]; ++ } ++ ++ W2BYTE(u32reg_43+0x00, (((MS_U16)u8Ramcode[1])<<8|(MS_U16)u8Ramcode[0])); ++ W2BYTE(u32reg_43+0x02, (((MS_U16)u8Ramcode[3])<<8|(MS_U16)u8Ramcode[2])); ++ W2BYTEMSK(u32reg_43+0x04, ((MS_U16)u8Ramcode[4]), 0x00FF); ++ ++ ++ W2BYTEMSK(u32reg_41, BIT8, BIT8); ++ } ++} ++#endif ++ ++void Hal_HVSP_SetHVSPInputSize(EN_HVSP_ID_TYPE enID, MS_U16 u16Width, MS_U16 u16Height) ++{ ++ MS_U32 u32reg_20, u32reg_21; ++ ++ if(enID == E_HVSP_ID_2) ++ { ++ u32reg_20 = REG_SCL_HVSP1_20_L; ++ u32reg_21 = REG_SCL_HVSP1_21_L; ++ gu16height[0] = (gu16height[0]> 16) & 0x00FF; ++ u16val_H = (u16val_H|0x0100); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_07_L, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_07_L+2, u16val_H, 0x01FF); ++ } ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_20_L, u16Width,0xFFFF); ++ } ++ } ++ if((R2BYTE(REG_SCL_HVSP1_21_L) != u16Height)&&(gbhvspset[E_HVSP_ID_2])) ++ { ++ u16val_SC1 = R2BYTE(REG_SCL_HVSP1_23_L); ++ if(u16val_SC1) ++ { ++ u64temp = ((MS_U64)u16Height * 1048576); ++ do_div(u64temp,u16val_SC1); ++ u32ratio = (MS_U32)u64temp; ++ if(u32ratio) ++ { ++ u16val_L = u32ratio & 0xFFFF; ++ u16val_H = (u32ratio >> 16) & 0x00FF; ++ u16val_H = (u16val_H|0x0100); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_09_L, u16val_L, 0xFFFF); ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_09_L+2, u16val_H, 0x01FF); ++ } ++ _Hal_HVSP_Write_Cmd(REG_SCL_HVSP1_21_L, u16Height,0xFFFF); ++ } ++ } ++ } ++ else if(enID ==E_HVSP_ID_2) ++ { ++ if(R2BYTE(REG_SCL_DMA0_62_L) != u16Width) ++ _Hal_HVSP_Write_Cmd(REG_SCL_DMA0_62_L, u16Width, 0xFFFF); ++ if(R2BYTE(REG_SCL_DMA0_63_L) != u16Height) ++ _Hal_HVSP_Write_Cmd(REG_SCL_DMA0_63_L, u16Height,0xFFFF); ++ if(R2BYTE(REG_SCL_DMA1_62_L) != u16Width) ++ _Hal_HVSP_Write_Cmd(REG_SCL_DMA1_62_L, u16Width, 0xFFFF); ++ if(R2BYTE(REG_SCL_DMA1_63_L) != u16Height) ++ _Hal_HVSP_Write_Cmd(REG_SCL_DMA1_63_L, u16Height,0xFFFF); ++ } ++ } ++} ++ ++// input tgen ++void Hal_HVSP_SetPatTgEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_40_L, bEn ? (BIT0|BIT1|BIT2|BIT15) : 0, BIT0|BIT1|BIT2|BIT15); ++ W2BYTEMSK(REG_SCL0_70_L, bEn ? BIT0 : 0, BIT0); ++ W2BYTEMSK(REG_SCL0_44_L, bEn ? BIT0 : 0, BIT0); // h/v ++} ++ ++void Hal_HVSP_SetTestPatCfg(void) ++{ ++ W2BYTE(REG_SCL0_42_L, 0x1010); // cb h/v width ++ W2BYTE(REG_SCL0_43_L, 0x0008); // shfit time ++ W2BYTE(REG_SCL0_44_L, 0x0C20); // h/v ++} ++ ++ ++void Hal_HVSP_SetPatTgVsyncSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_71_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVsyncEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_72_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVfdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_73_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVfdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_74_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_75_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_76_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgVtt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_77_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHsyncSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_79_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHsyncEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7A_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHfdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7B_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHfdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7C_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHdeSt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7D_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHdeEnd(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7E_L, u16Val, 0x0FFF); ++} ++ ++void Hal_HVSP_SetPatTgHtt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL0_7F_L, u16Val, 0x0FFF); ++} ++ ++ ++// LDC frame control ++//#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_SetLDCPathSel(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ { ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL0_03_L, bEn ? BIT12 : 0, BIT12); ++ MsOS_SetSCLFrameDelay(bEn ? 1 : 0); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL0_03_L, bEn ? BIT12 : 0, BIT12); ++ MsOS_SetEvent_IRQ(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), E_SCLIRQ_EVENT_SETDELAY); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "LDC:%hhd\n", bEn); ++ } ++} ++ ++MS_BOOL Hal_HVSP_GetLDCPathSel(void) ++{ ++ MS_U16 bEn; ++ bEn = R2BYTE(REG_SCL0_03_L); ++ return (MS_BOOL)((bEn&BIT12)>>12); ++} ++MS_U16 Hal_HVSP_GetShiftMultipleByISPClk(EN_HVSP_ISPCLK_TYPE enISPClkType) ++{ ++ MS_U16 u16DspH; ++ switch(enISPClkType) ++ { ++ case EN_HVSP_ISPCLK_123M: ++ u16DspH = 8;//40% ++ break; ++ case EN_HVSP_ISPCLK_86M: ++ u16DspH = 6;//30% ++ break; ++ case EN_HVSP_ISPCLK_72M: ++ u16DspH = 5; //25 % ++ break; ++ case EN_HVSP_ISPCLK_54M: ++ u16DspH = 4; //20% ++ break; ++ case EN_HVSP_ISPCLK_144M: ++ u16DspH = 9; //45% ++ break; ++ case EN_HVSP_ISPCLK_OFF: ++ default: ++ u16DspH = 0; ++ break; ++ } ++ return u16DspH; ++} ++ ++MS_U16 Hal_HVSP_GetLimitationByISPClk(EN_HVSP_ISPCLK_TYPE enISPClkType, MS_U16 u16SrcWidth, MS_U16 u16DspHeight) ++{ ++ MS_U16 u16CropHeightLim; ++ if (u16SrcWidth<=1920)//for LDC issue ++ { ++ switch(enISPClkType) ++ { ++ case EN_HVSP_ISPCLK_123M: ++ if(gstHalSrcSize.u16Height*gstHalSrcSize.u16Width >= 4500000 &&gstHalSrcSize.bSet) ++ { ++ u16CropHeightLim = u16DspHeight;//92% 1.1X ++ } ++ else ++ { ++ u16CropHeightLim = (u16DspHeight/20)*15;//75% 1.33X ++ } ++ break; ++ case EN_HVSP_ISPCLK_86M: ++ u16CropHeightLim = (u16DspHeight/20)*10;//50% ++ break; ++ case EN_HVSP_ISPCLK_72M: ++ u16CropHeightLim = (u16DspHeight/3); //33 % ++ break; ++ case EN_HVSP_ISPCLK_54M: ++ u16CropHeightLim = u16DspHeight/3; //33% ++ break; ++ case EN_HVSP_ISPCLK_144M: ++ if(gstHalSrcSize.u16Height*gstHalSrcSize.u16Width >= 4500000 &&gstHalSrcSize.bSet) ++ { ++ u16CropHeightLim = u16DspHeight;//90% 1.1X ++ } ++ else ++ { ++ u16CropHeightLim = (u16DspHeight/20)*15;//75% 1.33X ++ } ++ break; ++ case EN_HVSP_ISPCLK_OFF: ++ default: ++ u16CropHeightLim = u16DspHeight; ++ break; ++ } ++ } ++ else ++ { ++ if(gstHalSrcSize.u16Height*gstHalSrcSize.u16Width >= 4500000 &&gstHalSrcSize.bSet) ++ { ++ u16CropHeightLim = u16DspHeight;//90% 1.1X ++ } ++ else ++ { ++ u16CropHeightLim = (u16DspHeight/20)*15;//75% 1.33X ++ } ++ } ++ return u16CropHeightLim; ++} ++ ++EN_HVSP_ISPCLK_TYPE Hal_HVSP_GetISPClkType(void) ++{ ++ MS_U16 u16clk; ++ EN_HVSP_ISPCLK_TYPE enISPClkType; ++ u16clk = (R2BYTE(REG_SCL_CLK_61_L)&0x1F00)>>8; ++ switch(u16clk) ++ { ++ case EN_HVSP_ISPCLK_123M: ++ enISPClkType = EN_HVSP_ISPCLK_123M; ++ break; ++ case EN_HVSP_ISPCLK_OFF: ++ enISPClkType = EN_HVSP_ISPCLK_OFF; ++ break; ++ case EN_HVSP_ISPCLK_86M: ++ enISPClkType = EN_HVSP_ISPCLK_86M; ++ break; ++ case EN_HVSP_ISPCLK_72M: ++ enISPClkType = EN_HVSP_ISPCLK_72M; ++ break; ++ case EN_HVSP_ISPCLK_54M: ++ enISPClkType = EN_HVSP_ISPCLK_54M; ++ break; ++ case EN_HVSP_ISPCLK_144M: ++ enISPClkType = EN_HVSP_ISPCLK_144M; ++ break; ++ default: ++ enISPClkType = EN_HVSP_ISPCLK_NUM; ++ break; ++ } ++ return enISPClkType; ++} ++ ++void Hal_HVSP_SetLDCBypass(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0F_L, bEn ? BIT0 : 0, BIT0); ++} ++//#endif ++ ++void Hal_HVSP_SetLDCWidth(MS_U16 u16Width) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL_LDC_03_L, u16Width, 0x0FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_LDC_03_L, u16Width, 0x0FFF); ++ } ++} ++ ++void Hal_HVSP_SetLDCHeight(MS_U16 u16Height) ++{ ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL_LDC_04_L, u16Height, 0x0FFF); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_LDC_04_L, u16Height, 0x0FFF); ++ } ++} ++ ++void Hal_HVSP_SetLDCBase(MS_U32 u32Base) ++{ ++ W4BYTE(REG_SCL_LDC_05_L, u32Base); ++} ++ ++void Hal_HVSP_SetLDCHWrwDiff(MS_U16 u8Val) ++{ ++ W2BYTEMSK(REG_SCL_LDC_11_L, ((MS_U16)u8Val), BIT1|BIT0); ++} ++void Hal_HVSP_SetLDCSW_Idx(MS_U8 idx) ++{ ++ W2BYTEMSK(REG_SCL_LDC_10_L, ((MS_U16)idx), BIT1|BIT0); ++} ++void Hal_HVSP_SetLDCSW_Mode(MS_U8 bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_12_L, ((MS_U16)bEn)? BIT0 :0, BIT0); ++} ++void Hal_HVSP_SetLDCBank_Mode(EN_DRV_HVSP_LDCLCBANKMODE_TYPE enType) ++{ ++ W2BYTEMSK(REG_SCL_LDC_09_L, ((MS_U16)enType == EN_DRV_HVSP_LDCLCBANKMODE_64)? BIT0 :0, BIT0); ++} ++ ++#if ENABLE_HVSP_UNUSED_FUNCTION ++void Hal_HVSP_SetLDCPitch(MS_U32 u32Pitch) ++{ ++ W4BYTE(REG_SCL_LDC_07_L, u32Pitch); ++} ++ ++ ++void Hal_HVSP_SetLDCDmap_Base(MS_U32 u32Base) ++{ ++ W4BYTE(REG_SCL_LDC_0A_L, u32Base); ++} ++ ++void Hal_HVSP_SetLDCDmap_Pitch(MS_U32 u32Pitch) ++{ ++ W4BYTE(REG_SCL_LDC_0C_L, u32Pitch); ++} ++#endif ++void Hal_HVSP_SetOSDLocate(EN_HVSP_ID_TYPE enID,EN_DRV_HVSP_OSD_LOC_TYPE enLoc) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ W2BYTEMSK(REG_SCL2_64_L, (enLoc==EN_DRV_HVSP_OSD_LOC_BEFORE) ? BIT1: 0, BIT1); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ W2BYTEMSK(REG_SCL2_68_L, (enLoc==EN_DRV_HVSP_OSD_LOC_BEFORE) ? BIT1: 0, BIT1); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL2_60_L, (enLoc==EN_DRV_HVSP_OSD_LOC_BEFORE) ? BIT1: 0, BIT1); ++ } ++} ++void Hal_HVSP_SetOSDOnOff(EN_HVSP_ID_TYPE enID,MS_BOOL bEn) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ W2BYTEMSK(REG_SCL2_64_L, bEn? BIT0: 0, BIT0); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ W2BYTEMSK(REG_SCL2_68_L, bEn? BIT0: 0, BIT0); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL2_60_L, bEn? BIT0: 0, BIT0); ++ } ++} ++void Hal_HVSP_SetOSDbypass(EN_HVSP_ID_TYPE enID,MS_BOOL bEn) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ W2BYTEMSK(REG_SCL2_67_L, bEn? BIT7: 0, BIT7); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ W2BYTEMSK(REG_SCL2_6B_L, bEn? BIT7: 0, BIT7); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL2_63_L, bEn? BIT7: 0, BIT7); ++ } ++} ++void Hal_HVSP_SetOSDbypassWTM(EN_HVSP_ID_TYPE enID,MS_BOOL bEn) ++{ ++ if(enID == E_HVSP_ID_2) ++ { ++ W2BYTEMSK(REG_SCL2_64_L, bEn? BIT7: 0, BIT7); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ W2BYTEMSK(REG_SCL2_68_L, bEn? BIT7: 0, BIT7); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL2_60_L, bEn? BIT7: 0, BIT7); ++ } ++} ++EN_DRV_HVSP_OSD_LOC_TYPE Hal_HVSP_GetOSDLocate(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16En = 0; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16En = (R2BYTE(REG_SCL2_64_L)& BIT1)>>1; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16En = (R2BYTE(REG_SCL2_68_L)& BIT1)>>1; ++ } ++ else ++ { ++ u16En = (R2BYTE(REG_SCL2_60_L)& BIT1)>>1; ++ } ++ return u16En ? EN_DRV_HVSP_OSD_LOC_BEFORE : EN_DRV_HVSP_OSD_LOC_AFTER; ++} ++MS_BOOL Hal_HVSP_GetOSDOnOff(EN_HVSP_ID_TYPE enID) ++{ ++ MS_BOOL bEn = 0; ++ if(enID == E_HVSP_ID_2) ++ { ++ bEn = R2BYTE(REG_SCL2_64_L)& BIT0; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ bEn = R2BYTE(REG_SCL2_68_L)& BIT0; ++ } ++ else ++ { ++ bEn = R2BYTE(REG_SCL2_60_L)& BIT0; ++ } ++ return bEn; ++} ++MS_BOOL Hal_HVSP_GetOSDbypass(EN_HVSP_ID_TYPE enID) ++{ ++ MS_BOOL bEn; ++ if(enID == E_HVSP_ID_2) ++ { ++ bEn = (R2BYTE(REG_SCL2_67_L)& BIT7)>>7; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ bEn = (R2BYTE(REG_SCL2_6B_L)& BIT7)>>7; ++ } ++ else ++ { ++ bEn = (R2BYTE(REG_SCL2_63_L)& BIT7)>>7; ++ } ++ return bEn; ++} ++MS_BOOL Hal_HVSP_GetOSDbypassWTM(EN_HVSP_ID_TYPE enID) ++{ ++ MS_BOOL bEn; ++ if(enID == E_HVSP_ID_2) ++ { ++ bEn = (R2BYTE(REG_SCL2_64_L)& BIT7)>>7; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ bEn = (R2BYTE(REG_SCL2_68_L)& BIT7)>>7; ++ } ++ else ++ { ++ bEn = (R2BYTE(REG_SCL2_60_L)& BIT7)>>7; ++ } ++ return bEn; ++} ++ ++void Hal_HVSP_Set_Reg(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask) ++{ ++ WBYTEMSK(u32Reg, u8Val, u8Mask); ++} ++void Hal_HVSP_Set_2ByteReg(MS_U32 u32Reg, MS_U16 u16Val, MS_U16 u16Mask) ++{ ++ WBYTEMSK(u32Reg, u16Val, u16Mask); ++} ++MS_U16 Hal_HVSP_Get_2ByteReg(MS_U32 u32Reg) ++{ ++ MS_U16 u16Val; ++ u16Val = R2BYTE(u32Reg); ++ return u16Val; ++} ++ ++MS_U16 Hal_HVSP_Get_Crop_X(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_53_L); ++ return u16crop1; ++} ++ ++MS_U16 Hal_HVSP_Get_Crop_Y(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_55_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop2Xinfo(void) ++{ ++ MS_U16 u16crop2; ++ u16crop2 = R2BYTE(REG_SCL2_5B_L); ++ return u16crop2; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2Yinfo(void) ++{ ++ MS_U16 u16crop2; ++ u16crop2 = R2BYTE(REG_SCL2_5D_L); ++ return u16crop2; ++} ++ ++MS_U16 Hal_HVSP_GetCrop1WidthCount(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_70_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop1HeightCount(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_71_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_Get_Crop2_CountH(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_72_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_Get_Crop2_CountV(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_73_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop1Width(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_51_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetCrop1Height(void) ++{ ++ MS_U16 u16crop1; ++ u16crop1 = R2BYTE(REG_SCL2_52_L); ++ return u16crop1; ++} ++MS_U16 Hal_HVSP_GetDMAHeight(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 u16def; ++ ++ switch(enMonitorType) ++ { ++ case EN_HVSP_MONITOR_DMA1FRMCHECK: ++ u16def = R2BYTE(REG_SCL_DMA0_1B_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA1SNPCHECK: ++ u16def = R2BYTE(REG_SCL_DMA0_4B_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA2FRMCHECK: ++ u16def = R2BYTE(REG_SCL_DMA0_63_L); ++ break; ++ case EN_HVSP_MONITOR_DMA3FRMCHECK: ++ u16def = R2BYTE(REG_SCL_DMA1_1B_L); ++ break; ++ default: ++ u16def = 0x0; ++ break; ++ } ++ return ((u16def )); ++} ++MS_U16 Hal_HVSP_GetDMAHeightCount(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 u16Idx; ++ ++ switch(enMonitorType) ++ { ++ case EN_HVSP_MONITOR_DMA1FRMCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_10_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA1SNPCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_12_L); ++ break; ++ ++ case EN_HVSP_MONITOR_DMA2FRMCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_13_L); ++ break; ++ case EN_HVSP_MONITOR_DMA3FRMCHECK: ++ u16Idx = R2BYTE(REG_SCL_DMA2_15_L); ++ break; ++ default: ++ u16Idx = 0x0; ++ break; ++ } ++ return ((u16Idx)); ++} ++ ++MS_U16 Hal_HVSP_GetDMAEn(EN_HVSP_MONITOR_TYPE enMonitorType) ++{ ++ MS_U16 bEn; ++ switch(enMonitorType) ++ { ++ case EN_HVSP_MONITOR_DMA1FRMCHECK: ++ bEn = R2BYTE(REG_SCL_DMA0_01_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ ++ case EN_HVSP_MONITOR_DMA1SNPCHECK: ++ bEn = R2BYTE(REG_SCL_DMA0_03_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ ++ case EN_HVSP_MONITOR_DMA2FRMCHECK: ++ bEn = R2BYTE(REG_SCL_DMA0_04_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ case EN_HVSP_MONITOR_DMA3FRMCHECK: ++ bEn = R2BYTE(REG_SCL_DMA1_01_L); ++ bEn = (bEn & 0x8000)>>15; ++ break; ++ default: ++ bEn = 0x0; ++ break; ++ } ++ return bEn; ++} ++MS_U16 Hal_HVSP_GetHVSPInputWidth(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_20_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_20_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_20_L); ++ } ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetHVSPOutputWidth(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_22_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_22_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_22_L); ++ } ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2InputWidth(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_59_L); ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2InputHeight(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_5A_L); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetCrop2OutputWidth(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_5C_L); ++ return u16size; ++} ++ ++MS_U16 Hal_HVSP_GetCrop2OutputHeight(void) ++{ ++ MS_U16 u16size; ++ u16size = R2BYTE(REG_SCL2_5E_L); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetCrop1En(void) ++{ ++ MS_U16 u16size; ++ u16size = (R2BYTE(REG_SCL2_50_L) & BIT0); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetCrop2En(void) ++{ ++ MS_U16 u16size; ++ u16size = (R2BYTE(REG_SCL2_58_L) & BIT0); ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetHVSPOutputHeight(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_23_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_23_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_23_L); ++ } ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetHVSPInputHeight(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_21_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_21_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_21_L); ++ } ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetScalingFunctionStatus(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = (R2BYTE(REG_SCL_HVSP1_08_L) & BIT8)>>8; ++ u16size |= (R2BYTE(REG_SCL_HVSP1_0A_L)& BIT8)>>7; ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = (R2BYTE(REG_SCL_HVSP2_08_L) & BIT8)>>8; ++ u16size |= (R2BYTE(REG_SCL_HVSP2_0A_L)& BIT8)>>7; ++ } ++ else ++ { ++ u16size = (R2BYTE(REG_SCL_HVSP0_08_L) & BIT8)>>8; ++ u16size |= (R2BYTE(REG_SCL_HVSP0_0A_L)& BIT8)>>7; ++ } ++ return u16size; ++} ++MS_U16 Hal_HVSP_GetHVSPOutputHeightCount(EN_HVSP_ID_TYPE enID) ++{ ++ MS_U16 u16size; ++ if(enID == E_HVSP_ID_2) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP1_25_L); ++ } ++ else if(enID == E_HVSP_ID_3) ++ { ++ u16size = R2BYTE(REG_SCL_HVSP2_26_L); ++ } ++ else ++ { ++ u16size = R2BYTE(REG_SCL_HVSP0_26_L); ++ } ++ return u16size; ++} ++MS_U32 Hal_HVSP_GetCMDQStatus(void) ++{ ++ return R2BYTE(0x11208A); ++} ++void Hal_HVSP_PriMask_ColorY(MS_U16 u16Y) ++{ ++ W2BYTE(REG_VIP_SCNR_12_L, u16Y); ++} ++void Hal_HVSP_PriMask_ColorU(MS_U16 u16U) ++{ ++ W2BYTE(REG_VIP_SCNR_13_L, u16U); ++} ++void Hal_HVSP_PriMask_ColorV(MS_U16 u16V) ++{ ++ W2BYTE(REG_VIP_SCNR_14_L, u16V); ++} ++ ++void Hal_HVSP_SetPrv2CropOnOff(MS_BOOL bEn) ++{ ++ if(!LOCK_FB()) ++ { ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT5 : 0, BIT5); ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_01_L, bEn ? BIT5 : 0, BIT5); ++ } ++ MsOS_SetSCLFrameDelay(bEn ? 1 :0); ++ if(bEn) ++ { ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1)|| Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_MCNR_01_L,BIT0, BIT0); ++ if(!(R2BYTE(REG_SCL_DNR1_01_L)&BIT0)) ++ { ++ W2BYTEMSK(REG_SCL_DNR1_01_L, BIT0 , BIT0); ++ } ++ } ++ else ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_MCNR_01_L,BIT0, BIT0); ++ if(!(R2BYTE(REG_SCL_DNR1_01_L)&BIT0)) ++ { ++ _Hal_HVSP_Write_Cmd(REG_SCL_DNR1_01_L,BIT0, BIT0); ++ } ++ } ++ } ++ } ++ ++} ++MS_BOOL Hal_HVSP_GetPrv2CropOnOff(void) ++{ ++ MS_U16 u16Reg; ++ u16Reg = R2BYTE(REG_SCL_DNR1_01_L); ++ return ((u16Reg &BIT5)>>5); ++} ++ ++void Hal_HVSP_PriMask_bEn(MS_BOOL bEn) ++{ ++ MS_U32 u32Events; ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ if(Is_Reg_Type(E_HVSP_CMD_TRIG_NONE) || Is_IP_First_Set(E_HVSP_ID_1) || Is_CannotUseCMDQToSetReg()) ++ { ++ W2BYTEMSK(REG_VIP_SCNR_10_L, bEn ? BIT0 : 0, BIT0); ++ } ++ else if(bEn == EN_HVSP_TRIGGER_OFF) ++ { ++ if(Drv_SCLIRQ_GetEachDMAEn()&& VIPSETRULE()) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ Drv_CMDQ_FillCmd(&stCfg, REG_VIP_SCNR_10_L, 0, BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,1); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ } ++ else ++ { ++ if(Drv_SCLIRQ_GetEachDMAEn()||(!Drv_SCLIRQ_GetIsBlankingRegion())) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ (E_SCLIRQ_EVENT_FRMENDSYNC), &u32Events, E_AND, 2000); // get status: FRM END ++ } ++ W2BYTEMSK(REG_VIP_SCNR_10_L,0, BIT0); ++ } ++ } ++ else if(bEn == EN_HVSP_TRIGGER_ON) ++ { ++ if(Drv_SCLIRQ_GetEachDMAEn()&& VIPSETRULE()) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ Drv_CMDQ_FillCmd(&stCfg, REG_VIP_SCNR_10_L, BIT0, BIT0); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,1); ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ } ++ else ++ { ++ if(Drv_SCLIRQ_GetEachDMAEn()||(!Drv_SCLIRQ_GetIsBlankingRegion())) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ (E_SCLIRQ_EVENT_FRMENDSYNC), &u32Events, E_AND, 2000); // get status: FRM END ++ } ++ W2BYTEMSK(REG_VIP_SCNR_10_L,BIT0, BIT0); ++ } ++ } ++ else if(bEn == EN_HVSP_TRIGGER_CMDQ) ++ { ++ _Hal_HVSP_Write_Cmd(REG_VIP_SCNR_10_L,BIT0, BIT0); ++ } ++} ++void Hal_HVSP_PriMask_SRAMEn(MS_BOOL bEn,MS_U8 u8Idx) ++{ ++ MS_U32 u32Events; ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ if(Drv_SCLIRQ_GetEachDMAEn()&& VIPSETRULE()) ++ { ++ if(bEn) ++ { ++ Drv_CMDQ_FillCmd(&stCfg, REG_VIP_SCNR_11_L, ((MS_U16)(u8Idx<<8)| 0x1 ), 0xFF01); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,1); ++ } ++ else ++ { ++ Drv_CMDQ_FillCmd(&stCfg, REG_VIP_SCNR_11_L, ((MS_U16)(u8Idx<<8)), 0xFF01); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,1); ++ } ++ } ++ else ++ { ++ if(Drv_SCLIRQ_GetEachDMAEn()||(!Drv_SCLIRQ_GetIsBlankingRegion())) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ (E_SCLIRQ_EVENT_FRMENDSYNC), &u32Events, E_AND, 2000); // get status: FRM END ++ } ++ W2BYTEMSK(REG_VIP_SCNR_11_L, (MS_U16)(u8Idx<<8), 0xFF00); ++ W2BYTEMSK(REG_VIP_SCNR_11_L, bEn ? BIT0 : 0, BIT0); ++ } ++} ++void Hal_HVSP_PriMask_Fire(void) ++{ ++ if(VIPSETRULE()) ++ { ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ } ++} ++ ++void Hal_HVSP_PriMask_SRAMOffsetRe(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_VIP_SCNR_11_L, bEn ? BIT1 : 0, BIT1); ++} ++void Hal_HVSP_PriMask_SRAMRdIdx(MS_U8 u8Idx) ++{ ++ W2BYTEMSK(REG_VIP_SCNR_11_L, u8Idx<<5, BIT5|BIT6|BIT7); ++} ++void Hal_HVSP_PriMask_SRAMWriteIdx(MS_U8 u8Idx) ++{ ++ W2BYTEMSK(REG_VIP_SCNR_11_L, (MS_U16)(u8Idx<<8), 0xFF00); ++} ++void Hal_HVSP_PriMaskSetSRAM(MS_U8 u8idx,MS_U16 u16val) ++{ ++ MS_U32 u32Events; ++ MS_CMDQ_CMDReg stCfg; ++ MS_U32 u32reg = (u8idx == 0) ? REG_VIP_SCNR_17_L : ++ (u8idx == 1) ? REG_VIP_SCNR_18_L : ++ (u8idx == 2) ? REG_VIP_SCNR_19_L : ++ (u8idx == 3) ? REG_VIP_SCNR_1A_L : ++ (u8idx == 4) ? REG_VIP_SCNR_1B_L : ++ (u8idx == 5) ? REG_VIP_SCNR_1C_L : ++ REG_VIP_SCNR_17_L; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ if(Drv_SCLIRQ_GetEachDMAEn()&& VIPSETRULE()) ++ { ++ Drv_CMDQ_FillCmd(&stCfg, u32reg, u16val, 0xFFFF); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0,&stCfg,1); ++ } ++ else ++ { ++ if(Drv_SCLIRQ_GetEachDMAEn()||(!Drv_SCLIRQ_GetIsBlankingRegion())) ++ { ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ (E_SCLIRQ_EVENT_FRMENDSYNC), &u32Events, E_AND, 2000); // get status: FRM END ++ } ++ W2BYTE(u32reg, u16val); ++ } ++ ++} ++MS_U16 Hal_HVSP_PriMask_GetSRAMData(void) ++{ ++ return R2BYTE(REG_VIP_SCNR_1D_L); ++} ++void Hal_HVSP_SetWriteRegType(MS_BOOL bEn) ++{ ++ if(bEn && (VIPSETRULE()==E_VIPSetRule_CMDQAll || VIPSETRULE()==E_VIPSetRule_CMDQAllCheck ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck))) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ Drv_CMDQ_SetForceSkip(1); ++ if(Drv_SCLIRQ_GetEachDMAEn()) ++ { ++ gbSramCMDQ = 1; ++ } ++ else ++ { ++ gbSramCMDQ = 0; ++ } ++ } ++ else if(bEn && VIPSETRULE()) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ Drv_CMDQ_SetForceSkip(1); ++ if(Drv_SCLIRQ_GetEachDMAEn()&& !Drv_SCLIRQ_GetIsBlankingRegion()) ++ { ++ gbSramCMDQ = 1; ++ } ++ else ++ { ++ gbSramCMDQ = 0; ++ } ++ } ++ else ++ { ++ gbSramCMDQ = 0; ++ Drv_CMDQ_SetForceSkip(0); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ } ++} ++void Hal_HVSP_WriteReg(MS_U32 u32Reg,MS_U16 u16Val,MS_U16 u16Mask) ++{ ++ MS_CMDQ_CMDReg stCfg; ++ MsOS_Memset(&stCfg,0,sizeof(MS_CMDQ_CMDReg)); ++ if(gbSramCMDQ) ++ { ++ Drv_CMDQ_FillCmd(&stCfg, u32Reg, u16Val, u16Mask); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0, &stCfg, 1); ++ } ++ else ++ { ++ W2BYTEMSK(u32Reg, u16Val, u16Mask);//sec ++ } ++} ++void Hal_HVSP_SRAMDumpHSP(MS_U32 u32Sram,MS_U32 u32reg) ++{ ++ MS_U16 u16addr = 0,u16tvalue = 0,u16tcount = 0,u16readdata; ++ //clear ++ for(u16addr = 64;u16addr<128;u16addr++) ++ { ++ Hal_HVSP_WriteReg(u32reg, BIT0, BIT0);//Yenable ++ Hal_HVSP_WriteReg(u32reg+2, u16addr, 0xFF); ++ Hal_HVSP_WriteReg(u32reg+4, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+6, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+8, 0, 0xFF); ++ Hal_HVSP_WriteReg(u32reg, BIT0|BIT8, BIT0|BIT8);//W pulse ++ Hal_HVSP_WriteReg(u32reg, 0, BIT0);//Yenable ++ ++ Hal_HVSP_WriteReg(u32reg, BIT1, BIT1);//Cenable ++ Hal_HVSP_WriteReg(u32reg+4, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+6, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+8, 0, 0xFF); ++ Hal_HVSP_WriteReg(u32reg, BIT1|BIT8, BIT1|BIT8);//W pulse ++ Hal_HVSP_WriteReg(u32reg, 0, BIT1);//Cenable ++ } ++ //SRAM 0 //0~64 entry is V 65~127 is H ++ ++ for(u16addr=0;u16addr<(PQ_IP_SRAM1_SIZE_Main/5);u16addr++) ++ { ++ // 64~127 ++ Hal_HVSP_WriteReg(u32reg, BIT0, BIT0);//Yenable ++ Hal_HVSP_WriteReg(u32reg+2, u16addr+64, 0xFF); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]VYtval12:%hx\n", u16tvalue); ++ Hal_HVSP_WriteReg(u32reg+4, u16tvalue, 0xFFFF); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ Hal_HVSP_WriteReg(u32reg+6, u16tvalue, 0xFFFF); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]VYtval34:%hx\n", u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vtval5:%hx\n", u16tvalue); ++ Hal_HVSP_WriteReg(u32reg+8, u16tvalue, 0xFF); ++ Hal_HVSP_WriteReg(u32reg, BIT0|BIT8|BIT9, BIT0|BIT8|BIT9);//8 W pulse//9 R pulse ++ //if(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE) ++ if(!gbSramCMDQ) ++ { ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vread Yval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vread Yval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vread Yval 5:%hx\n", u16readdata); ++ } ++ Hal_HVSP_WriteReg(u32reg, 0, BIT0);//Yenable ++ ++ Hal_HVSP_WriteReg(u32reg, BIT1, BIT1);//Cenable ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount] | (MST_C_SRAM1_Main[0][u16tcount+1]<<8); ++ Hal_HVSP_WriteReg(u32reg+4, u16tvalue, 0xFFFF); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+2] | (MST_C_SRAM1_Main[0][u16tcount+3]<<8); ++ Hal_HVSP_WriteReg(u32reg+6, u16tvalue, 0xFFFF); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+4]; ++ Hal_HVSP_WriteReg(u32reg+8, u16tvalue, 0xFF); ++ Hal_HVSP_WriteReg(u32reg, BIT1|BIT8|BIT9, BIT1|BIT8|BIT9);//8 W pulse 9R pulse ++ //if(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE) ++ if(!gbSramCMDQ) ++ { ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vread Cval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vread Cval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Vread Cval 5:%hx\n", u16readdata); ++ } ++ Hal_HVSP_WriteReg(u32reg, 0, BIT1);//Cenable ++ u16tcount += 5; ++ } ++ //SRAM 1 //128~256 entry link to 0~127 , so do not use ++} ++void Hal_HVSP_SRAMDumpVSP(MS_U32 u32Sram,MS_U32 u32reg) ++{ ++ MS_U16 u16addr = 0,u16tvalue = 0,u16tcount = 0,u16readdata; ++ //clear ++ for(u16addr = 0;u16addr<64;u16addr++) ++ { ++ Hal_HVSP_WriteReg(u32reg, BIT0, BIT0);//Yenable ++ Hal_HVSP_WriteReg(u32reg+2, u16addr, 0xFF); ++ Hal_HVSP_WriteReg(u32reg+4, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+6, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+8, 0, 0xFF); ++ Hal_HVSP_WriteReg(u32reg, BIT8|BIT0, BIT0|BIT8);//W pulse ++ Hal_HVSP_WriteReg(u32reg, 0, BIT0);//Yenable ++ ++ Hal_HVSP_WriteReg(u32reg, BIT1, BIT1);//Cenable ++ Hal_HVSP_WriteReg(u32reg+4, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+6, 0, 0xFFFF); ++ Hal_HVSP_WriteReg(u32reg+8, 0, 0xFF); ++ Hal_HVSP_WriteReg(u32reg, BIT1|BIT8, BIT1|BIT8);//W pulse ++ Hal_HVSP_WriteReg(u32reg, 0, BIT1);//Cenable ++ } ++ //SRAM 0 ///0~64 entry is V 65~127 is H ++ ++ for(u16addr=0;u16addr<(PQ_IP_SRAM1_SIZE_Main/5);u16addr++) ++ { ++ Hal_HVSP_WriteReg(u32reg, BIT0, BIT0);//Yenable ++ Hal_HVSP_WriteReg(u32reg+2, u16addr, 0xFF); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ Hal_HVSP_WriteReg(u32reg+4, u16tvalue, 0xFFFF); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Ytval12:%hx\n", u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ Hal_HVSP_WriteReg(u32reg+6, u16tvalue, 0xFFFF); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Ytval34:%hx\n", u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ Hal_HVSP_WriteReg(u32reg+8, u16tvalue, 0xFF); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Ytval5:%hx\n", u16tvalue); ++ Hal_HVSP_WriteReg(u32reg, BIT0|BIT8|BIT9, BIT0|BIT8|BIT9);//8 W pulse 9R ++ //if(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE) ++ if(!gbSramCMDQ) ++ { ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]read Yval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]read Yval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]read Yval 5:%hx\n", u16readdata); ++ } ++ Hal_HVSP_WriteReg(u32reg, 0, BIT0);//Yenable ++ ++ Hal_HVSP_WriteReg(u32reg, BIT1, BIT1);//Cenable ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount] | (MST_C_SRAM1_Main[0][u16tcount+1]<<8); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Ctval12:%hx\n", u16tvalue); ++ Hal_HVSP_WriteReg(u32reg+4, u16tvalue, 0xFFFF); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+2] | (MST_C_SRAM1_Main[0][u16tcount+3]<<8); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Ctval34:%hx\n", u16tvalue); ++ Hal_HVSP_WriteReg(u32reg+6, u16tvalue, 0xFFFF); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+4]; ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]Ctval5:%hx\n", u16tvalue); ++ Hal_HVSP_WriteReg(u32reg+8, u16tvalue, 0xFF); ++ ++ //if(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE) ++ Hal_HVSP_WriteReg(u32reg, BIT1|BIT8|BIT9, BIT1|BIT8|BIT9);//8W 9R pulse ++ if(!gbSramCMDQ) ++ { ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]read Cval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]read Cval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVHVSP()&EN_DBGMG_HVSPLEVEL_ELSE, "[HVSP]read Cval 5:%hx\n", u16readdata); ++ } ++ Hal_HVSP_WriteReg(u32reg, 0, BIT1);//Cenable ++ u16tcount += 5; ++ } ++ //SRAM 1 //128~256 entry link to 0~127 , so do not use ++} ++MS_BOOL Hal_HVSP_SetSRAMDump(EN_HVSP_SRAM_DUMP_TYPE endump,MS_U32 u32Sram,MS_U32 u32reg) ++{ ++ if(endump == EN_HVSP_SRAM_DUMP_HVSP_V || endump == EN_HVSP_SRAM_DUMP_HVSP_V_1|| ++ endump == EN_HVSP_SRAM_DUMP_HVSP_V_2) ++ { ++ Hal_HVSP_SRAMDumpVSP(u32Sram,u32reg); ++ } ++ else if(endump == EN_HVSP_SRAM_DUMP_HVSP_H || endump == EN_HVSP_SRAM_DUMP_HVSP_H_1|| ++ endump == EN_HVSP_SRAM_DUMP_HVSP_H_2) ++ { ++ Hal_HVSP_SRAMDumpHSP(u32Sram,u32reg); ++ } ++ return 1; ++} ++MS_BOOL Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_TYPE endump,MS_U32 u32Sram) ++{ ++ MS_U16 u16clkreg; ++ MS_BOOL bRet; ++ MS_U32 u32reg = endump == EN_HVSP_SRAM_DUMP_HVSP_V ? REG_SCL_HVSP0_41_L: ++ endump == EN_HVSP_SRAM_DUMP_HVSP_V_1 ? REG_SCL_HVSP1_41_L: ++ endump == EN_HVSP_SRAM_DUMP_HVSP_V_2 ? REG_SCL_HVSP2_41_L: ++ endump == EN_HVSP_SRAM_DUMP_HVSP_H ? REG_SCL_HVSP0_41_L: ++ endump == EN_HVSP_SRAM_DUMP_HVSP_H_1 ? REG_SCL_HVSP1_41_L: ++ endump == EN_HVSP_SRAM_DUMP_HVSP_H_2 ? REG_SCL_HVSP2_41_L: ++ 0; ++ //clk open ++ if(endump == EN_HVSP_SRAM_DUMP_HVSP_V_2 || endump == EN_HVSP_SRAM_DUMP_HVSP_H_2) ++ { ++ u16clkreg = R2BYTE(REG_SCL_CLK_65_L); ++ W2BYTE(REG_SCL_CLK_65_L,0x0); ++ } ++ else ++ { ++ u16clkreg = R2BYTE(REG_SCL_CLK_64_L); ++ W2BYTE(REG_SCL_CLK_64_L,0x0); ++ Hal_HVSP_SetWriteRegType(1); ++ } ++ bRet = Hal_HVSP_SetSRAMDump(endump,u32Sram,u32reg); ++ ++ //clk close ++ if(endump == EN_HVSP_SRAM_DUMP_HVSP_V_2|| endump == EN_HVSP_SRAM_DUMP_HVSP_H_2) ++ { ++ W2BYTE(REG_SCL_CLK_65_L,u16clkreg); ++ } ++ else ++ { ++ if(gbSramCMDQ) ++ { ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ } ++ Hal_HVSP_SetWriteRegType(0); ++ W2BYTE(REG_SCL_CLK_64_L,u16clkreg); ++ } ++ return bRet; ++} ++ ++#undef HAL_HVSP_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/include/halhvsp.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/include/halhvsp.h +new file mode 100644 +index 00000000..0bcca11a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/include/halhvsp.h +@@ -0,0 +1,359 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. 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These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_HVSP_H ++#define _HAL_HVSP_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ E_HVSP_FILTER_MODE_BYPASS, ++ E_HVSP_FILTER_MODE_BILINEAR, ++ E_HVSP_FILTER_MODE_SRAM_0, ++ E_HVSP_FILTER_MODE_SRAM_1, ++}EN_HVSP_FILTER_MODE; ++ ++typedef enum ++{ ++ E_HVSP_SRAM_SEL_0, ++ E_HVSP_SRAM_SEL_1, ++}EN_HVSP_SRAM_SEL_TYPE; ++ ++typedef enum ++{ ++ E_HVSP_FILTER_SRAM_SEL_1, ++ E_HVSP_FILTER_SRAM_SEL_2, ++ E_HVSP_FILTER_SRAM_SEL_3, ++ E_HVSP_FILTER_SRAM_SEL_4, ++}EN_HVSP_FILTER_SRAM_SEL_TYPE; ++ ++typedef enum ++{ ++ EN_HVSP_CLKATTR_ISP=0x10, ++ EN_HVSP_CLKATTR_BT656=0x20, ++ EN_HVSP_CLKATTR_FORCEMODE=0x40, ++}EN_HVSP_CLKATTR_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++typedef struct ++{ ++ MS_BOOL bEn; ++ MS_U16 u16In_hsize; ++ MS_U16 u16In_vsize; ++ MS_U16 u16Hst; ++ MS_U16 u16Hsize; ++ MS_U16 u16Vst; ++ MS_U16 u16Vsize; ++}ST_HVSP_CROP_INFO; ++typedef enum ++{ ++ EN_HVSP_SRAM_DUMP_ICC, ++ EN_HVSP_SRAM_DUMP_IHC, ++ EN_HVSP_SRAM_DUMP_HVSP_V, ++ EN_HVSP_SRAM_DUMP_HVSP_V_1, ++ EN_HVSP_SRAM_DUMP_HVSP_V_2, ++ EN_HVSP_SRAM_DUMP_WDR, ++ EN_HVSP_SRAM_DUMP_GAMMA_Y, ++ EN_HVSP_SRAM_DUMP_GAMMA_U, ++ EN_HVSP_SRAM_DUMP_GAMMA_V, ++ EN_HVSP_SRAM_DUMP_GM10to12_R, ++ EN_HVSP_SRAM_DUMP_GM10to12_G, ++ EN_HVSP_SRAM_DUMP_GM10to12_B, ++ EN_HVSP_SRAM_DUMP_GM12to10_R, ++ EN_HVSP_SRAM_DUMP_GM12to10_G, ++ EN_HVSP_SRAM_DUMP_GM12to10_B, ++ EN_HVSP_SRAM_DUMP_HVSP_H, ++ EN_HVSP_SRAM_DUMP_HVSP_H_1, ++ EN_HVSP_SRAM_DUMP_HVSP_H_2, ++ EN_HVSP_SRAM_DUMP_NUM, ++}EN_HVSP_SRAM_DUMP_TYPE; ++typedef enum ++{ ++ EN_HVSP_TRIGGER_OFF = 0, ++ EN_HVSP_TRIGGER_ON, ++ EN_HVSP_TRIGGER_CMDQ, ++ EN_HVSP_TRIGGER_CMDQOFF, ++}EN_HVSP_PRIMASK_TRIGGER_TYPE; ++ ++typedef enum ++{ ++ EN_HVSP_ISPCLK_123M = 0x0, ++ EN_HVSP_ISPCLK_OFF = 0x1, ++ EN_HVSP_ISPCLK_86M = 0x4, ++ EN_HVSP_ISPCLK_72M = 0x8, ++ EN_HVSP_ISPCLK_54M = 0xC, ++ EN_HVSP_ISPCLK_144M = 0x10, ++ EN_HVSP_ISPCLK_NUM, ++}EN_HVSP_ISPCLK_TYPE; ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++ ++#ifndef MHAL_HVSP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++INTERFACE void Hal_HVSP_Exit(void); ++INTERFACE void Hal_HVSP_SetRiuBase(MS_U32 u32RiuBase); ++INTERFACE void Hal_HVSP_SetInputSrcSize(ST_HVSP_SIZE_CONFIG *stSrc); ++INTERFACE void Hal_HVSP_SetCropConfig(EN_HVSP_CROP_ID_TYPE enID, ST_HVSP_CROP_INFO *stCropInfo); ++INTERFACE void Hal_HVSP_SetHWInputMux(EN_HVSP_IP_MUX_TYPE enIpType); ++INTERFACE void Hal_HVSP_SetInputMuxType(EN_HVSP_IP_MUX_TYPE enIpType); ++INTERFACE EN_HVSP_IP_MUX_TYPE Hal_HVSP_GetInputSrcMux(void); ++INTERFACE void Hal_HVSP_Set_Reset(void); ++INTERFACE void Hal_HVSP_Set_CLKOFF(void); ++INTERFACE void Hal_HVSP_Set_SW_Reset(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_Set_DNR_Reset(MS_BOOL bEn); ++ ++// NLM ++INTERFACE void Hal_HVSP_SetVIPSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetNLMEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetNLMLineBufferSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetVpsSRAMEn(MS_BOOL bEn); ++//AIP ++INTERFACE void Hal_HVSP_SetWDRGlobalSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetWDRLocalSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetMXNRSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetUVadjSize(MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetXNRSize(MS_U16 u16Width, MS_U16 u16Height); ++ ++// IPM ++INTERFACE void Hal_HVSP_SetIPMYCMReadEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetIPMYCMWriteEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetIPMCIIRReadEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetIPMCIIRWriteEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetIPMYCBase(MS_U32 u32Base); ++INTERFACE void Hal_HVSP_SetIPMMotionBase(MS_U32 u32Base); ++INTERFACE void Hal_HVSP_SetIPMCIIRBase(MS_U32 u32Base); ++INTERFACE void Hal_HVSP_SetIPMvSize(MS_U16 u16Vsize); ++INTERFACE void Hal_HVSP_SetIPMLineOffset(MS_U16 u16Lineoffset); ++INTERFACE void Hal_HVSP_SetIPMFetchNum(MS_U16 u16FetchNum); ++INTERFACE void Hal_HVSP_Set_IPM_Read_Req(MS_U8 u8Thrd, MS_U8 u8Limit); ++INTERFACE void Hal_HVSP_Set_IPM_Write_Req(MS_U8 u8Thrd, MS_U8 u8Limit); ++INTERFACE void Hal_HVSP_SetIPMBufferNumber(MS_U8 u8Num); ++ ++ ++// Scaling ++INTERFACE void Hal_HVSP_SetScalingVeEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben); ++INTERFACE void Hal_HVSP_SetScalingVeFactor(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio); ++INTERFACE void Hal_HVSP_SetScalingHoEn(EN_HVSP_ID_TYPE enID, MS_BOOL ben); ++INTERFACE void Hal_HVSP_SetScalingHoFacotr(EN_HVSP_ID_TYPE enID, MS_U32 u32Ratio); ++INTERFACE void Hal_HVSP_SetModeYHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode); ++INTERFACE void Hal_HVSP_SetModeYVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode); ++INTERFACE void Hal_HVSP_SetModeCHo(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel); ++INTERFACE void Hal_HVSP_SetModeCVe(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_MODE enFilterMode, EN_HVSP_SRAM_SEL_TYPE enSramSel); ++INTERFACE void Hal_HVSP_SetHspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetVspDithEn(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetHspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetHspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetVspCoringEnC(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetVspCoringEnY(EN_HVSP_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetHspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_SetHspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_SetVspCoringThrdC(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_SetVspCoringThrdY(EN_HVSP_ID_TYPE enID, MS_U16 u16Thread); ++INTERFACE void Hal_HVSP_Set_Sram_Coeff(EN_HVSP_ID_TYPE enID, EN_HVSP_FILTER_SRAM_SEL_TYPE enSramSel, MS_BOOL bC_SRAM, MS_U8 *pData); ++INTERFACE void Hal_HVSP_SetHVSPInputSize(EN_HVSP_ID_TYPE enID, MS_U16 u16Width, MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetHVSPOutputSize(EN_HVSP_ID_TYPE enID, MS_U16 u16Width, MS_U16 u16Height); ++ ++// PatTg ++INTERFACE void Hal_HVSP_SetPatTgEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetPatTgVsyncSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVsyncEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVfdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVfdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgVtt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHsyncSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHsyncEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHfdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHfdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHdeSt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHdeEnd(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetPatTgHtt(MS_U16 u16Val); ++INTERFACE void Hal_HVSP_SetTestPatCfg(void); ++// REG W ++INTERFACE void Hal_HVSP_Set_Reg(MS_U32 u32Reg, MS_U8 u8Val, MS_U8 u8Mask); ++ ++// CMD buffer ++INTERFACE void Hal_HVSP_SetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG *stCmdTrigCfg); ++INTERFACE void Hal_HVSP_GetCMDQTrigCfg(ST_HVSP_CMD_TRIG_CONFIG *pCfg); ++INTERFACE void Hal_HVSP_SetResetDNR(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetCMDQTrigFrameCnt(MS_U16 u16Idx); ++INTERFACE void Hal_HVSP_SetCMDQTrigFire(void); ++INTERFACE void Hal_HVSP_SetFrameBufferManageLock(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetLDCPathSel(MS_BOOL bEn); ++INTERFACE MS_BOOL Hal_HVSP_GetLDCPathSel(void); ++INTERFACE MS_U16 Hal_HVSP_GetShiftMultipleByISPClk(EN_HVSP_ISPCLK_TYPE enISPClkType); ++INTERFACE EN_HVSP_ISPCLK_TYPE Hal_HVSP_GetISPClkType(void); ++INTERFACE MS_U16 Hal_HVSP_GetLimitationByISPClk(EN_HVSP_ISPCLK_TYPE enISPClkType, MS_U16 u16SrcWidth, MS_U16 u16DspHeight); ++INTERFACE void Hal_HVSP_SetLDCBypass(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetLDCHeight(MS_U16 u16Height); ++INTERFACE void Hal_HVSP_SetLDCWidth(MS_U16 u16Width); ++INTERFACE void Hal_HVSP_SetLDCPitch(MS_U32 u32Pitch); ++INTERFACE void Hal_HVSP_SetLDCBase(MS_U32 u32Base); ++INTERFACE void Hal_HVSP_SetLDCHWrwDiff(MS_U16 u8Val); ++INTERFACE void Hal_HVSP_SetLDCSW_Mode(MS_U8 bEn); ++INTERFACE void Hal_HVSP_SetLDCBank_Mode(EN_DRV_HVSP_LDCLCBANKMODE_TYPE enType); ++INTERFACE void Hal_HVSP_SetLDCSW_Idx(MS_U8 idx); ++INTERFACE void Hal_HVSP_SetOSDLocate(EN_HVSP_ID_TYPE enID,EN_DRV_HVSP_OSD_LOC_TYPE enLoc); ++INTERFACE void Hal_HVSP_SetOSDbypass(EN_HVSP_ID_TYPE enID,MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetOSDOnOff(EN_HVSP_ID_TYPE enID,MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetOSDbypassWTM(EN_HVSP_ID_TYPE enID,MS_BOOL bEn); ++INTERFACE EN_DRV_HVSP_OSD_LOC_TYPE Hal_HVSP_GetOSDLocate(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_BOOL Hal_HVSP_GetOSDbypass(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_BOOL Hal_HVSP_GetOSDOnOff(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_BOOL Hal_HVSP_GetOSDbypassWTM(EN_HVSP_ID_TYPE enID); ++INTERFACE void Hal_HVSP_SetIdclkOnOff(MS_BOOL bEn,ST_HVSP_CLK_CONFIG* stclk); ++INTERFACE void Hal_HVSP_FCLK1(ST_HVSP_CLK_CONFIG *stclk); ++INTERFACE void Hal_HVSP_FCLK2(ST_HVSP_CLK_CONFIG *stclk); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPOutputHeight(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPOutputHeightCount(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetScalingFunctionStatus(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPInputHeight(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPInputWidth(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop_X(void); ++INTERFACE MS_U16 Hal_HVSP_GetHVSPOutputWidth(EN_HVSP_ID_TYPE enID); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop_Y(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2Yinfo(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2Xinfo(void); ++INTERFACE void Hal_HVSP_SetBT656SrcConfig(MS_BOOL bEn,MS_U16 u16Lineoffset); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1WidthCount(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1HeightCount(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1Width(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1Height(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2InputWidth(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2InputHeight(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2OutputWidth(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2OutputHeight(void); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop2_CountH(void); ++INTERFACE MS_U16 Hal_HVSP_Get_Crop2_CountV(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop2En(void); ++INTERFACE MS_U16 Hal_HVSP_GetCrop1En(void); ++INTERFACE void Hal_HVSP_SetCLKRate(unsigned char u8Idx); ++INTERFACE MS_U32 Hal_HVSP_GetCMDQStatus(void); ++INTERFACE void Hal_HVSP_PriMask_ColorY(MS_U16 u16Y); ++INTERFACE void Hal_HVSP_PriMask_ColorU(MS_U16 u16U); ++INTERFACE void Hal_HVSP_PriMask_ColorV(MS_U16 u16V); ++INTERFACE void Hal_HVSP_PriMask_Width(MS_U16 u16W); ++INTERFACE void Hal_HVSP_PriMask_Height(MS_U16 u16H); ++INTERFACE void Hal_HVSP_PriMask_bEn(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_SetPrv2CropOnOff(MS_BOOL bEn); ++INTERFACE MS_BOOL Hal_HVSP_GetPrv2CropOnOff(void); ++INTERFACE void Hal_HVSP_PriMask_SRAMEn(MS_BOOL bEn,MS_U8 u8Idx); ++INTERFACE void Hal_HVSP_PriMask_Fire(void); ++INTERFACE void Hal_HVSP_PriMask_SRAMOffsetRe(MS_BOOL bEn); ++INTERFACE void Hal_HVSP_PriMask_SRAMRdIdx(MS_U8 u8Idx); ++INTERFACE void Hal_HVSP_PriMask_SRAMWriteIdx(MS_U8 u8Idx); ++INTERFACE void Hal_HVSP_PriMaskSetSRAM(MS_U8 u8idx,MS_U16 u16val); ++INTERFACE MS_U16 Hal_HVSP_PriMask_GetSRAMData(void); ++INTERFACE MS_U16 Hal_HVSP_GetDMAHeight(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_U16 Hal_HVSP_GetDMAHeightCount(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_U16 Hal_HVSP_GetDMAEn(EN_HVSP_MONITOR_TYPE enMonitorType); ++INTERFACE MS_BOOL Hal_HVSP_SRAM_Dump(EN_HVSP_SRAM_DUMP_TYPE endump,MS_U32 u32Sram); ++INTERFACE MS_U16 Hal_HVSP_Get_2ByteReg(MS_U32 u32Reg); ++INTERFACE void Hal_HVSP_Set_2ByteReg(MS_U32 u32Reg, MS_U16 u16Val, MS_U16 u16Mask); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/include/halhvsp_utility.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/include/halhvsp_utility.h +new file mode 100644 +index 00000000..9b525d94 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/hvsp/include/halhvsp_utility.h +@@ -0,0 +1,69 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCL_UTILITY_H_ ++#define _HALSCL_UTILITY_H_ ++ ++//!! Do not include this header in driver or api level ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 HVSP_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( HVSP_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( HVSP_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (HVSP_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( HVSP_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++ ++#define WBYTEMSK(u32Reg, u8Val, u8Mask) \ ++ RIU_WRITE_BYTE( (((u32Reg)<<1) - ((u32Reg) & 1)), ( RIU_READ_BYTE( (((u32Reg)<<1) - ((u32Reg) & 1)) ) & ~(u8Mask)) | ((u8Val) & (u8Mask)) ) ++ ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/hwreg.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/hwreg.h +new file mode 100644 +index 00000000..477a55a7 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/hwreg.h +@@ -0,0 +1,8349 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HWREG_H_ ++#define _HWREG_H_ ++ ++//------------------------------------------------------------------------------------- ++#define REG_CHIPTOP_BASE 0x101E00 ++#define REG_ISP_BASE 0x130200 ++#define REG_SCL_LPLL_BASE 0x103300 ++#define REG_SCL_CLK_BASE 0x103800 ++#define REG_BLOCK_BASE 0x113300 ++#define REG_SCL_HVSP0_BASE 0x121000 ++#define REG_SCL_HVSP1_BASE 0x121100 ++#define REG_SCL_HVSP2_BASE 0x121200 ++#define REG_SCL_DMA0_BASE 0x121300 ++#define REG_SCL_DMA1_BASE 0x121400 ++#define REG_SCL_DMA2_BASE 0x121500 ++#define REG_SCL_DNR0_BASE 0x121600 ++#define REG_SCL_NLM0_BASE 0x121700 ++#define REG_SCL0_BASE 0x121800 ++#define REG_SCL1_BASE 0x121900 ++#define REG_SCL2_BASE 0x121A00 ++#define REG_VIP_ACE3_BASE 0x121B00 ++#define REG_VIP_ACE_BASE 0x121C00 ++#define REG_VIP_PK_BASE 0x121D00 ++#define REG_VIP_DLC_BASE 0x121E00 ++#define REG_VIP_MWE_BASE 0x121F00 ++#define REG_VIP_ACE2_BASE 0x122000 ++#define REG_VIP_LCE_BASE 0x122100 ++#define REG_SCL_DNR1_BASE 0x122200 ++#define REG_SCL_DNR2_BASE 0x122300 ++#define REG_SCL_LDC_BASE 0x122400 ++#define REG_SCL3_BASE 0x122500 ++#define REG_VIP_SCNR_BASE 0x122600 ++#define REG_VIP_WDR_BASE 0x122700 ++#define REG_VIP_YEE_BASE 0x122800 ++#define REG_VIP_MCNR_BASE 0x122900 ++#define REG_MCM_BASE 0x113200 ++#define REG_CMDQ_BASE 0x112000 ++#define REG_CMDQ1_BASE 0x112300 ++#define REG_CMDQ2_BASE 0x112400 ++ ++//------------------------------------------------------------------------------------- ++#define REG_ISP_7A_L (REG_ISP_BASE + 0xF4) ++#define REG_ISP_7A_H (REG_ISP_BASE + 0xF5) ++//------------------------------------------------------------------------------------- ++#define REG_CMDQ_00_L (REG_CMDQ_BASE + 0x00) ++#define REG_CMDQ_00_H (REG_CMDQ_BASE + 0x01) ++#define REG_CMDQ_01_L (REG_CMDQ_BASE + 0x02) ++#define REG_CMDQ_01_H (REG_CMDQ_BASE + 0x03) ++#define REG_CMDQ_02_L (REG_CMDQ_BASE + 0x04) ++#define REG_CMDQ_02_H (REG_CMDQ_BASE + 0x05) ++#define REG_CMDQ_03_L (REG_CMDQ_BASE + 0x06) ++#define REG_CMDQ_03_H (REG_CMDQ_BASE + 0x07) ++#define REG_CMDQ_04_L (REG_CMDQ_BASE + 0x08) ++#define REG_CMDQ_04_H (REG_CMDQ_BASE + 0x09) ++#define REG_CMDQ_05_L (REG_CMDQ_BASE + 0x0A) ++#define REG_CMDQ_05_H (REG_CMDQ_BASE + 0x0B) ++#define REG_CMDQ_06_L (REG_CMDQ_BASE + 0x0C) ++#define REG_CMDQ_06_H (REG_CMDQ_BASE + 0x0D) ++#define REG_CMDQ_07_L (REG_CMDQ_BASE + 0x0E) ++#define REG_CMDQ_07_H (REG_CMDQ_BASE + 0x0F) ++#define REG_CMDQ_08_L (REG_CMDQ_BASE + 0x10) ++#define REG_CMDQ_08_H (REG_CMDQ_BASE + 0x11) ++#define REG_CMDQ_09_L (REG_CMDQ_BASE + 0x12) ++#define REG_CMDQ_09_H (REG_CMDQ_BASE + 0x13) ++#define REG_CMDQ_0A_L (REG_CMDQ_BASE + 0x14) ++#define REG_CMDQ_0A_H (REG_CMDQ_BASE + 0x15) ++#define REG_CMDQ_0B_L (REG_CMDQ_BASE + 0x16) ++#define REG_CMDQ_0B_H (REG_CMDQ_BASE + 0x17) ++#define REG_CMDQ_0C_L (REG_CMDQ_BASE + 0x18) ++#define REG_CMDQ_0C_H (REG_CMDQ_BASE + 0x19) ++#define REG_CMDQ_0D_L (REG_CMDQ_BASE + 0x1A) ++#define REG_CMDQ_0D_H (REG_CMDQ_BASE + 0x1B) ++#define REG_CMDQ_0E_L (REG_CMDQ_BASE + 0x1C) ++#define REG_CMDQ_0E_H (REG_CMDQ_BASE + 0x1D) ++#define REG_CMDQ_0F_L (REG_CMDQ_BASE + 0x1E) ++#define REG_CMDQ_0F_H (REG_CMDQ_BASE + 0x1F) ++#define REG_CMDQ_10_L (REG_CMDQ_BASE + 0x20) ++#define REG_CMDQ_10_H (REG_CMDQ_BASE + 0x21) ++#define REG_CMDQ_11_L (REG_CMDQ_BASE + 0x22) ++#define REG_CMDQ_11_H (REG_CMDQ_BASE + 0x23) ++#define REG_CMDQ_12_L (REG_CMDQ_BASE + 0x24) ++#define REG_CMDQ_12_H (REG_CMDQ_BASE + 0x25) ++#define REG_CMDQ_13_L (REG_CMDQ_BASE + 0x26) ++#define REG_CMDQ_13_H (REG_CMDQ_BASE + 0x27) ++#define REG_CMDQ_14_L (REG_CMDQ_BASE + 0x28) ++#define REG_CMDQ_14_H (REG_CMDQ_BASE + 0x29) ++#define REG_CMDQ_15_L (REG_CMDQ_BASE + 0x2A) ++#define REG_CMDQ_15_H (REG_CMDQ_BASE + 0x2B) ++#define REG_CMDQ_16_L (REG_CMDQ_BASE + 0x2C) ++#define REG_CMDQ_16_H (REG_CMDQ_BASE + 0x2D) ++#define REG_CMDQ_17_L (REG_CMDQ_BASE + 0x2E) ++#define REG_CMDQ_17_H (REG_CMDQ_BASE + 0x2F) ++#define REG_CMDQ_18_L (REG_CMDQ_BASE + 0x30) ++#define REG_CMDQ_18_H (REG_CMDQ_BASE + 0x31) ++#define REG_CMDQ_19_L (REG_CMDQ_BASE + 0x32) ++#define REG_CMDQ_19_H (REG_CMDQ_BASE + 0x33) ++#define REG_CMDQ_1A_L (REG_CMDQ_BASE + 0x34) ++#define REG_CMDQ_1A_H (REG_CMDQ_BASE + 0x35) ++#define REG_CMDQ_1B_L (REG_CMDQ_BASE + 0x36) ++#define REG_CMDQ_1B_H (REG_CMDQ_BASE + 0x37) ++#define REG_CMDQ_1C_L (REG_CMDQ_BASE + 0x38) ++#define REG_CMDQ_1C_H (REG_CMDQ_BASE + 0x39) ++#define REG_CMDQ_1D_L (REG_CMDQ_BASE + 0x3A) ++#define REG_CMDQ_1D_H (REG_CMDQ_BASE + 0x3B) ++#define REG_CMDQ_1E_L (REG_CMDQ_BASE + 0x3C) ++#define REG_CMDQ_1E_H (REG_CMDQ_BASE + 0x3D) ++#define REG_CMDQ_1F_L (REG_CMDQ_BASE + 0x3E) ++#define REG_CMDQ_1F_H (REG_CMDQ_BASE + 0x3F) ++#define REG_CMDQ_20_L (REG_CMDQ_BASE + 0x40) ++#define REG_CMDQ_20_H (REG_CMDQ_BASE + 0x41) ++#define REG_CMDQ_21_L (REG_CMDQ_BASE + 0x42) ++#define REG_CMDQ_21_H (REG_CMDQ_BASE + 0x43) ++#define REG_CMDQ_22_L (REG_CMDQ_BASE + 0x44) ++#define REG_CMDQ_22_H (REG_CMDQ_BASE + 0x45) ++#define REG_CMDQ_23_L (REG_CMDQ_BASE + 0x46) ++#define REG_CMDQ_23_H (REG_CMDQ_BASE + 0x47) ++#define REG_CMDQ_24_L (REG_CMDQ_BASE + 0x48) ++#define REG_CMDQ_24_H (REG_CMDQ_BASE + 0x49) ++#define REG_CMDQ_25_L (REG_CMDQ_BASE + 0x4A) ++#define REG_CMDQ_25_H (REG_CMDQ_BASE + 0x4B) ++#define REG_CMDQ_26_L (REG_CMDQ_BASE + 0x4C) ++#define REG_CMDQ_26_H (REG_CMDQ_BASE + 0x4D) ++#define REG_CMDQ_27_L (REG_CMDQ_BASE + 0x4E) ++#define REG_CMDQ_27_H (REG_CMDQ_BASE + 0x4F) ++#define REG_CMDQ_28_L (REG_CMDQ_BASE + 0x50) ++#define REG_CMDQ_28_H (REG_CMDQ_BASE + 0x51) ++#define REG_CMDQ_29_L (REG_CMDQ_BASE + 0x52) ++#define REG_CMDQ_29_H (REG_CMDQ_BASE + 0x53) ++#define REG_CMDQ_2A_L (REG_CMDQ_BASE + 0x54) ++#define REG_CMDQ_2A_H (REG_CMDQ_BASE + 0x55) ++#define REG_CMDQ_2B_L (REG_CMDQ_BASE + 0x56) ++#define REG_CMDQ_2B_H (REG_CMDQ_BASE + 0x57) ++#define REG_CMDQ_2C_L (REG_CMDQ_BASE + 0x58) ++#define REG_CMDQ_2C_H (REG_CMDQ_BASE + 0x59) ++#define REG_CMDQ_2D_L (REG_CMDQ_BASE + 0x5A) ++#define REG_CMDQ_2D_H (REG_CMDQ_BASE + 0x5B) ++#define REG_CMDQ_2E_L (REG_CMDQ_BASE + 0x5C) ++#define REG_CMDQ_2E_H (REG_CMDQ_BASE + 0x5D) ++#define REG_CMDQ_2F_L (REG_CMDQ_BASE + 0x5E) ++#define REG_CMDQ_2F_H (REG_CMDQ_BASE + 0x5F) ++#define REG_CMDQ_30_L (REG_CMDQ_BASE + 0x60) ++#define REG_CMDQ_30_H (REG_CMDQ_BASE + 0x61) ++#define REG_CMDQ_31_L (REG_CMDQ_BASE + 0x62) ++#define REG_CMDQ_31_H (REG_CMDQ_BASE + 0x63) ++#define REG_CMDQ_32_L (REG_CMDQ_BASE + 0x64) ++#define REG_CMDQ_32_H (REG_CMDQ_BASE + 0x65) ++#define REG_CMDQ_33_L (REG_CMDQ_BASE + 0x66) ++#define REG_CMDQ_33_H (REG_CMDQ_BASE + 0x67) ++#define REG_CMDQ_34_L (REG_CMDQ_BASE + 0x68) ++#define REG_CMDQ_34_H (REG_CMDQ_BASE + 0x69) ++#define REG_CMDQ_35_L (REG_CMDQ_BASE + 0x6A) ++#define REG_CMDQ_35_H (REG_CMDQ_BASE + 0x6B) ++#define REG_CMDQ_36_L (REG_CMDQ_BASE + 0x6C) ++#define REG_CMDQ_36_H (REG_CMDQ_BASE + 0x6D) ++#define REG_CMDQ_37_L (REG_CMDQ_BASE + 0x6E) ++#define REG_CMDQ_37_H (REG_CMDQ_BASE + 0x6F) ++#define REG_CMDQ_38_L (REG_CMDQ_BASE + 0x70) ++#define REG_CMDQ_38_H (REG_CMDQ_BASE + 0x71) ++#define REG_CMDQ_39_L (REG_CMDQ_BASE + 0x72) ++#define REG_CMDQ_39_H (REG_CMDQ_BASE + 0x73) ++#define REG_CMDQ_3A_L (REG_CMDQ_BASE + 0x74) ++#define REG_CMDQ_3A_H (REG_CMDQ_BASE + 0x75) ++#define REG_CMDQ_3B_L (REG_CMDQ_BASE + 0x76) ++#define REG_CMDQ_3B_H (REG_CMDQ_BASE + 0x77) ++#define REG_CMDQ_3C_L (REG_CMDQ_BASE + 0x78) ++#define REG_CMDQ_3C_H (REG_CMDQ_BASE + 0x79) ++#define REG_CMDQ_3D_L (REG_CMDQ_BASE + 0x7A) ++#define REG_CMDQ_3D_H (REG_CMDQ_BASE + 0x7B) ++#define REG_CMDQ_3E_L (REG_CMDQ_BASE + 0x7C) ++#define REG_CMDQ_3E_H (REG_CMDQ_BASE + 0x7D) ++#define REG_CMDQ_3F_L (REG_CMDQ_BASE + 0x7E) ++#define REG_CMDQ_3F_H (REG_CMDQ_BASE + 0x7F) ++#define REG_CMDQ_40_L (REG_CMDQ_BASE + 0x80) ++#define REG_CMDQ_40_H (REG_CMDQ_BASE + 0x81) ++#define REG_CMDQ_41_L (REG_CMDQ_BASE + 0x82) ++#define REG_CMDQ_41_H (REG_CMDQ_BASE + 0x83) ++#define REG_CMDQ_42_L (REG_CMDQ_BASE + 0x84) ++#define REG_CMDQ_42_H (REG_CMDQ_BASE + 0x85) ++#define REG_CMDQ_43_L (REG_CMDQ_BASE + 0x86) ++#define REG_CMDQ_43_H (REG_CMDQ_BASE + 0x87) ++#define REG_CMDQ_44_L (REG_CMDQ_BASE + 0x88) ++#define REG_CMDQ_44_H (REG_CMDQ_BASE + 0x89) ++#define REG_CMDQ_45_L (REG_CMDQ_BASE + 0x8A) ++#define REG_CMDQ_45_H (REG_CMDQ_BASE + 0x8B) ++#define REG_CMDQ_46_L (REG_CMDQ_BASE + 0x8C) ++#define REG_CMDQ_46_H (REG_CMDQ_BASE + 0x8D) ++#define REG_CMDQ_47_L (REG_CMDQ_BASE + 0x8E) ++#define REG_CMDQ_47_H (REG_CMDQ_BASE + 0x8F) ++#define REG_CMDQ_48_L (REG_CMDQ_BASE + 0x90) ++#define REG_CMDQ_48_H (REG_CMDQ_BASE + 0x91) ++#define REG_CMDQ_49_L (REG_CMDQ_BASE + 0x92) ++#define REG_CMDQ_49_H (REG_CMDQ_BASE + 0x93) ++#define REG_CMDQ_4A_L (REG_CMDQ_BASE + 0x94) ++#define REG_CMDQ_4A_H (REG_CMDQ_BASE + 0x95) ++#define REG_CMDQ_4B_L (REG_CMDQ_BASE + 0x96) ++#define REG_CMDQ_4B_H (REG_CMDQ_BASE + 0x97) ++#define REG_CMDQ_4C_L (REG_CMDQ_BASE + 0x98) ++#define REG_CMDQ_4C_H (REG_CMDQ_BASE + 0x99) ++#define REG_CMDQ_4D_L (REG_CMDQ_BASE + 0x9A) ++#define REG_CMDQ_4D_H (REG_CMDQ_BASE + 0x9B) ++#define REG_CMDQ_4E_L (REG_CMDQ_BASE + 0x9C) ++#define REG_CMDQ_4E_H (REG_CMDQ_BASE + 0x9D) ++#define REG_CMDQ_4F_L (REG_CMDQ_BASE + 0x9E) ++#define REG_CMDQ_4F_H (REG_CMDQ_BASE + 0x9F) ++#define REG_CMDQ_50_L (REG_CMDQ_BASE + 0xA0) ++#define REG_CMDQ_50_H (REG_CMDQ_BASE + 0xA1) ++#define REG_CMDQ_51_L (REG_CMDQ_BASE + 0xA2) ++#define REG_CMDQ_51_H (REG_CMDQ_BASE + 0xA3) ++#define REG_CMDQ_52_L (REG_CMDQ_BASE + 0xA4) ++#define REG_CMDQ_52_H (REG_CMDQ_BASE + 0xA5) ++#define REG_CMDQ_53_L (REG_CMDQ_BASE + 0xA6) ++#define REG_CMDQ_53_H (REG_CMDQ_BASE + 0xA7) ++#define REG_CMDQ_54_L (REG_CMDQ_BASE + 0xA8) ++#define REG_CMDQ_54_H (REG_CMDQ_BASE + 0xA9) ++#define REG_CMDQ_55_L (REG_CMDQ_BASE + 0xAA) ++#define REG_CMDQ_55_H (REG_CMDQ_BASE + 0xAB) ++#define REG_CMDQ_56_L (REG_CMDQ_BASE + 0xAC) ++#define REG_CMDQ_56_H (REG_CMDQ_BASE + 0xAD) ++#define REG_CMDQ_57_L (REG_CMDQ_BASE + 0xAE) ++#define REG_CMDQ_57_H (REG_CMDQ_BASE + 0xAF) ++#define REG_CMDQ_58_L (REG_CMDQ_BASE + 0xB0) ++#define REG_CMDQ_58_H (REG_CMDQ_BASE + 0xB1) ++#define REG_CMDQ_59_L (REG_CMDQ_BASE + 0xB2) ++#define REG_CMDQ_59_H (REG_CMDQ_BASE + 0xB3) ++#define REG_CMDQ_5A_L (REG_CMDQ_BASE + 0xB4) ++#define REG_CMDQ_5A_H (REG_CMDQ_BASE + 0xB5) ++#define REG_CMDQ_5B_L (REG_CMDQ_BASE + 0xB6) ++#define REG_CMDQ_5B_H (REG_CMDQ_BASE + 0xB7) ++#define REG_CMDQ_5C_L (REG_CMDQ_BASE + 0xB8) ++#define REG_CMDQ_5C_H (REG_CMDQ_BASE + 0xB9) ++#define REG_CMDQ_5D_L (REG_CMDQ_BASE + 0xBA) ++#define REG_CMDQ_5D_H (REG_CMDQ_BASE + 0xBB) ++#define REG_CMDQ_5E_L (REG_CMDQ_BASE + 0xBC) ++#define REG_CMDQ_5E_H (REG_CMDQ_BASE + 0xBD) ++#define REG_CMDQ_5F_L (REG_CMDQ_BASE + 0xBE) ++#define REG_CMDQ_5F_H (REG_CMDQ_BASE + 0xBF) ++#define REG_CMDQ_60_L (REG_CMDQ_BASE + 0xC0) ++#define REG_CMDQ_60_H (REG_CMDQ_BASE + 0xC1) ++#define REG_CMDQ_61_L (REG_CMDQ_BASE + 0xC2) ++#define REG_CMDQ_61_H (REG_CMDQ_BASE + 0xC3) ++#define REG_CMDQ_62_L (REG_CMDQ_BASE + 0xC4) ++#define REG_CMDQ_62_H (REG_CMDQ_BASE + 0xC5) ++#define REG_CMDQ_63_L (REG_CMDQ_BASE + 0xC6) ++#define REG_CMDQ_63_H (REG_CMDQ_BASE + 0xC7) ++#define REG_CMDQ_64_L (REG_CMDQ_BASE + 0xC8) ++#define REG_CMDQ_64_H (REG_CMDQ_BASE + 0xC9) ++#define REG_CMDQ_65_L (REG_CMDQ_BASE + 0xCA) ++#define REG_CMDQ_65_H (REG_CMDQ_BASE + 0xCB) ++#define REG_CMDQ_66_L (REG_CMDQ_BASE + 0xCC) ++#define REG_CMDQ_66_H (REG_CMDQ_BASE + 0xCD) ++#define REG_CMDQ_67_L (REG_CMDQ_BASE + 0xCE) ++#define REG_CMDQ_67_H (REG_CMDQ_BASE + 0xCF) ++#define REG_CMDQ_68_L (REG_CMDQ_BASE + 0xD0) ++#define REG_CMDQ_68_H (REG_CMDQ_BASE + 0xD1) ++#define REG_CMDQ_69_L (REG_CMDQ_BASE + 0xD2) ++#define REG_CMDQ_69_H (REG_CMDQ_BASE + 0xD3) ++#define REG_CMDQ_6A_L (REG_CMDQ_BASE + 0xD4) ++#define REG_CMDQ_6A_H (REG_CMDQ_BASE + 0xD5) ++#define REG_CMDQ_6B_L (REG_CMDQ_BASE + 0xD6) ++#define REG_CMDQ_6B_H (REG_CMDQ_BASE + 0xD7) ++#define REG_CMDQ_6C_L (REG_CMDQ_BASE + 0xD8) ++#define REG_CMDQ_6C_H (REG_CMDQ_BASE + 0xD9) ++#define REG_CMDQ_6D_L (REG_CMDQ_BASE + 0xDA) ++#define REG_CMDQ_6D_H (REG_CMDQ_BASE + 0xDB) ++#define REG_CMDQ_6E_L (REG_CMDQ_BASE + 0xDC) ++#define REG_CMDQ_6E_H (REG_CMDQ_BASE + 0xDD) ++#define REG_CMDQ_6F_L (REG_CMDQ_BASE + 0xDE) ++#define REG_CMDQ_6F_H (REG_CMDQ_BASE + 0xDF) ++#define REG_CMDQ_70_L (REG_CMDQ_BASE + 0xE0) ++#define REG_CMDQ_70_H (REG_CMDQ_BASE + 0xE1) ++#define REG_CMDQ_71_L (REG_CMDQ_BASE + 0xE2) ++#define REG_CMDQ_71_H (REG_CMDQ_BASE + 0xE3) ++#define REG_CMDQ_72_L (REG_CMDQ_BASE + 0xE4) ++#define REG_CMDQ_72_H (REG_CMDQ_BASE + 0xE5) ++#define REG_CMDQ_73_L (REG_CMDQ_BASE + 0xE6) ++#define REG_CMDQ_73_H (REG_CMDQ_BASE + 0xE7) ++#define REG_CMDQ_74_L (REG_CMDQ_BASE + 0xE8) ++#define REG_CMDQ_74_H (REG_CMDQ_BASE + 0xE9) ++#define REG_CMDQ_75_L (REG_CMDQ_BASE + 0xEA) ++#define REG_CMDQ_75_H (REG_CMDQ_BASE + 0xEB) ++#define REG_CMDQ_76_L (REG_CMDQ_BASE + 0xEC) ++#define REG_CMDQ_76_H (REG_CMDQ_BASE + 0xED) ++#define REG_CMDQ_77_L (REG_CMDQ_BASE + 0xEE) ++#define REG_CMDQ_77_H (REG_CMDQ_BASE + 0xEF) ++#define REG_CMDQ_78_L (REG_CMDQ_BASE + 0xF0) ++#define REG_CMDQ_78_H (REG_CMDQ_BASE + 0xF1) ++#define REG_CMDQ_79_L (REG_CMDQ_BASE + 0xF2) ++#define REG_CMDQ_79_H (REG_CMDQ_BASE + 0xF3) ++#define REG_CMDQ_7A_L (REG_CMDQ_BASE + 0xF4) ++#define REG_CMDQ_7A_H (REG_CMDQ_BASE + 0xF5) ++#define REG_CMDQ_7B_L (REG_CMDQ_BASE + 0xF6) ++#define REG_CMDQ_7B_H (REG_CMDQ_BASE + 0xF7) ++#define REG_CMDQ_7C_L (REG_CMDQ_BASE + 0xF8) ++#define REG_CMDQ_7C_H (REG_CMDQ_BASE + 0xF9) ++#define REG_CMDQ_7D_L (REG_CMDQ_BASE + 0xFA) ++#define REG_CMDQ_7D_H (REG_CMDQ_BASE + 0xFB) ++#define REG_CMDQ_7E_L (REG_CMDQ_BASE + 0xFC) ++#define REG_CMDQ_7E_H (REG_CMDQ_BASE + 0xFD) ++#define REG_CMDQ_7F_L (REG_CMDQ_BASE + 0xFE) ++#define REG_CMDQ_7F_H (REG_CMDQ_BASE + 0xFF) ++#define REG_CMDQ1_00_L (REG_CMDQ1_BASE + 0x00) ++#define REG_CMDQ1_00_H (REG_CMDQ1_BASE + 0x01) ++#define REG_CMDQ1_01_L (REG_CMDQ1_BASE + 0x02) ++#define REG_CMDQ1_01_H (REG_CMDQ1_BASE + 0x03) ++#define REG_CMDQ1_02_L (REG_CMDQ1_BASE + 0x04) ++#define REG_CMDQ1_02_H (REG_CMDQ1_BASE + 0x05) ++#define REG_CMDQ1_03_L (REG_CMDQ1_BASE + 0x06) ++#define REG_CMDQ1_03_H (REG_CMDQ1_BASE + 0x07) ++#define REG_CMDQ1_04_L (REG_CMDQ1_BASE + 0x08) ++#define REG_CMDQ1_04_H (REG_CMDQ1_BASE + 0x09) ++#define REG_CMDQ1_05_L (REG_CMDQ1_BASE + 0x0A) ++#define REG_CMDQ1_05_H (REG_CMDQ1_BASE + 0x0B) ++#define REG_CMDQ1_06_L (REG_CMDQ1_BASE + 0x0C) ++#define REG_CMDQ1_06_H (REG_CMDQ1_BASE + 0x0D) ++#define REG_CMDQ1_07_L (REG_CMDQ1_BASE + 0x0E) ++#define REG_CMDQ1_07_H (REG_CMDQ1_BASE + 0x0F) ++#define REG_CMDQ1_08_L (REG_CMDQ1_BASE + 0x10) ++#define REG_CMDQ1_08_H (REG_CMDQ1_BASE + 0x11) ++#define REG_CMDQ1_09_L (REG_CMDQ1_BASE + 0x12) ++#define REG_CMDQ1_09_H (REG_CMDQ1_BASE + 0x13) ++#define REG_CMDQ1_0A_L (REG_CMDQ1_BASE + 0x14) ++#define REG_CMDQ1_0A_H (REG_CMDQ1_BASE + 0x15) ++#define REG_CMDQ1_0B_L (REG_CMDQ1_BASE + 0x16) ++#define REG_CMDQ1_0B_H (REG_CMDQ1_BASE + 0x17) ++#define REG_CMDQ1_0C_L (REG_CMDQ1_BASE + 0x18) ++#define REG_CMDQ1_0C_H (REG_CMDQ1_BASE + 0x19) ++#define REG_CMDQ1_0D_L (REG_CMDQ1_BASE + 0x1A) ++#define REG_CMDQ1_0D_H (REG_CMDQ1_BASE + 0x1B) ++#define REG_CMDQ1_0E_L (REG_CMDQ1_BASE + 0x1C) ++#define REG_CMDQ1_0E_H (REG_CMDQ1_BASE + 0x1D) ++#define REG_CMDQ1_0F_L (REG_CMDQ1_BASE + 0x1E) ++#define REG_CMDQ1_0F_H (REG_CMDQ1_BASE + 0x1F) ++#define REG_CMDQ1_10_L (REG_CMDQ1_BASE + 0x20) ++#define REG_CMDQ1_10_H (REG_CMDQ1_BASE + 0x21) ++#define REG_CMDQ1_11_L (REG_CMDQ1_BASE + 0x22) ++#define REG_CMDQ1_11_H (REG_CMDQ1_BASE + 0x23) ++#define REG_CMDQ1_12_L (REG_CMDQ1_BASE + 0x24) ++#define REG_CMDQ1_12_H (REG_CMDQ1_BASE + 0x25) ++#define REG_CMDQ1_13_L (REG_CMDQ1_BASE + 0x26) ++#define REG_CMDQ1_13_H (REG_CMDQ1_BASE + 0x27) ++#define REG_CMDQ1_14_L (REG_CMDQ1_BASE + 0x28) ++#define REG_CMDQ1_14_H (REG_CMDQ1_BASE + 0x29) ++#define REG_CMDQ1_15_L (REG_CMDQ1_BASE + 0x2A) ++#define REG_CMDQ1_15_H (REG_CMDQ1_BASE + 0x2B) ++#define REG_CMDQ1_16_L (REG_CMDQ1_BASE + 0x2C) ++#define REG_CMDQ1_16_H (REG_CMDQ1_BASE + 0x2D) ++#define REG_CMDQ1_17_L (REG_CMDQ1_BASE + 0x2E) ++#define REG_CMDQ1_17_H (REG_CMDQ1_BASE + 0x2F) ++#define REG_CMDQ1_18_L (REG_CMDQ1_BASE + 0x30) ++#define REG_CMDQ1_18_H (REG_CMDQ1_BASE + 0x31) ++#define REG_CMDQ1_19_L (REG_CMDQ1_BASE + 0x32) ++#define REG_CMDQ1_19_H (REG_CMDQ1_BASE + 0x33) ++#define REG_CMDQ1_1A_L (REG_CMDQ1_BASE + 0x34) ++#define REG_CMDQ1_1A_H (REG_CMDQ1_BASE + 0x35) ++#define REG_CMDQ1_1B_L (REG_CMDQ1_BASE + 0x36) ++#define REG_CMDQ1_1B_H (REG_CMDQ1_BASE + 0x37) ++#define REG_CMDQ1_1C_L (REG_CMDQ1_BASE + 0x38) ++#define REG_CMDQ1_1C_H (REG_CMDQ1_BASE + 0x39) ++#define REG_CMDQ1_1D_L (REG_CMDQ1_BASE + 0x3A) ++#define REG_CMDQ1_1D_H (REG_CMDQ1_BASE + 0x3B) ++#define REG_CMDQ1_1E_L (REG_CMDQ1_BASE + 0x3C) ++#define REG_CMDQ1_1E_H (REG_CMDQ1_BASE + 0x3D) ++#define REG_CMDQ1_1F_L (REG_CMDQ1_BASE + 0x3E) ++#define REG_CMDQ1_1F_H (REG_CMDQ1_BASE + 0x3F) ++#define REG_CMDQ1_20_L (REG_CMDQ1_BASE + 0x40) ++#define REG_CMDQ1_20_H (REG_CMDQ1_BASE + 0x41) ++#define REG_CMDQ1_21_L (REG_CMDQ1_BASE + 0x42) ++#define REG_CMDQ1_21_H (REG_CMDQ1_BASE + 0x43) ++#define REG_CMDQ1_22_L (REG_CMDQ1_BASE + 0x44) ++#define REG_CMDQ1_22_H (REG_CMDQ1_BASE + 0x45) ++#define REG_CMDQ1_23_L (REG_CMDQ1_BASE + 0x46) ++#define REG_CMDQ1_23_H (REG_CMDQ1_BASE + 0x47) ++#define REG_CMDQ1_24_L (REG_CMDQ1_BASE + 0x48) ++#define REG_CMDQ1_24_H (REG_CMDQ1_BASE + 0x49) ++#define REG_CMDQ1_25_L (REG_CMDQ1_BASE + 0x4A) ++#define REG_CMDQ1_25_H (REG_CMDQ1_BASE + 0x4B) ++#define REG_CMDQ1_26_L (REG_CMDQ1_BASE + 0x4C) ++#define REG_CMDQ1_26_H (REG_CMDQ1_BASE + 0x4D) ++#define REG_CMDQ1_27_L (REG_CMDQ1_BASE + 0x4E) ++#define REG_CMDQ1_27_H (REG_CMDQ1_BASE + 0x4F) ++#define REG_CMDQ1_28_L (REG_CMDQ1_BASE + 0x50) ++#define REG_CMDQ1_28_H (REG_CMDQ1_BASE + 0x51) ++#define REG_CMDQ1_29_L (REG_CMDQ1_BASE + 0x52) ++#define REG_CMDQ1_29_H (REG_CMDQ1_BASE + 0x53) ++#define REG_CMDQ1_2A_L (REG_CMDQ1_BASE + 0x54) ++#define REG_CMDQ1_2A_H (REG_CMDQ1_BASE + 0x55) ++#define REG_CMDQ1_2B_L (REG_CMDQ1_BASE + 0x56) ++#define REG_CMDQ1_2B_H (REG_CMDQ1_BASE + 0x57) ++#define REG_CMDQ1_2C_L (REG_CMDQ1_BASE + 0x58) ++#define REG_CMDQ1_2C_H (REG_CMDQ1_BASE + 0x59) ++#define REG_CMDQ1_2D_L (REG_CMDQ1_BASE + 0x5A) ++#define REG_CMDQ1_2D_H (REG_CMDQ1_BASE + 0x5B) ++#define REG_CMDQ1_2E_L (REG_CMDQ1_BASE + 0x5C) ++#define REG_CMDQ1_2E_H (REG_CMDQ1_BASE + 0x5D) ++#define REG_CMDQ1_2F_L (REG_CMDQ1_BASE + 0x5E) ++#define REG_CMDQ1_2F_H (REG_CMDQ1_BASE + 0x5F) ++#define REG_CMDQ1_30_L (REG_CMDQ1_BASE + 0x60) ++#define REG_CMDQ1_30_H (REG_CMDQ1_BASE + 0x61) ++#define REG_CMDQ1_31_L (REG_CMDQ1_BASE + 0x62) ++#define REG_CMDQ1_31_H (REG_CMDQ1_BASE + 0x63) ++#define REG_CMDQ1_32_L (REG_CMDQ1_BASE + 0x64) ++#define REG_CMDQ1_32_H (REG_CMDQ1_BASE + 0x65) ++#define REG_CMDQ1_33_L (REG_CMDQ1_BASE + 0x66) ++#define REG_CMDQ1_33_H (REG_CMDQ1_BASE + 0x67) ++#define REG_CMDQ1_34_L (REG_CMDQ1_BASE + 0x68) ++#define REG_CMDQ1_34_H (REG_CMDQ1_BASE + 0x69) ++#define REG_CMDQ1_35_L (REG_CMDQ1_BASE + 0x6A) ++#define REG_CMDQ1_35_H (REG_CMDQ1_BASE + 0x6B) ++#define REG_CMDQ1_36_L (REG_CMDQ1_BASE + 0x6C) ++#define REG_CMDQ1_36_H (REG_CMDQ1_BASE + 0x6D) ++#define REG_CMDQ1_37_L (REG_CMDQ1_BASE + 0x6E) ++#define REG_CMDQ1_37_H (REG_CMDQ1_BASE + 0x6F) ++#define REG_CMDQ1_38_L (REG_CMDQ1_BASE + 0x70) ++#define REG_CMDQ1_38_H (REG_CMDQ1_BASE + 0x71) ++#define REG_CMDQ1_39_L (REG_CMDQ1_BASE + 0x72) ++#define REG_CMDQ1_39_H (REG_CMDQ1_BASE + 0x73) ++#define REG_CMDQ1_3A_L (REG_CMDQ1_BASE + 0x74) ++#define REG_CMDQ1_3A_H (REG_CMDQ1_BASE + 0x75) ++#define REG_CMDQ1_3B_L (REG_CMDQ1_BASE + 0x76) ++#define REG_CMDQ1_3B_H (REG_CMDQ1_BASE + 0x77) ++#define REG_CMDQ1_3C_L (REG_CMDQ1_BASE + 0x78) ++#define REG_CMDQ1_3C_H (REG_CMDQ1_BASE + 0x79) ++#define REG_CMDQ1_3D_L (REG_CMDQ1_BASE + 0x7A) ++#define REG_CMDQ1_3D_H (REG_CMDQ1_BASE + 0x7B) ++#define REG_CMDQ1_3E_L (REG_CMDQ1_BASE + 0x7C) ++#define REG_CMDQ1_3E_H (REG_CMDQ1_BASE + 0x7D) ++#define REG_CMDQ1_3F_L (REG_CMDQ1_BASE + 0x7E) ++#define REG_CMDQ1_3F_H (REG_CMDQ1_BASE + 0x7F) ++#define REG_CMDQ1_40_L (REG_CMDQ1_BASE + 0x80) ++#define REG_CMDQ1_40_H (REG_CMDQ1_BASE + 0x81) ++#define REG_CMDQ1_41_L (REG_CMDQ1_BASE + 0x82) ++#define REG_CMDQ1_41_H (REG_CMDQ1_BASE + 0x83) ++#define REG_CMDQ1_42_L (REG_CMDQ1_BASE + 0x84) ++#define REG_CMDQ1_42_H (REG_CMDQ1_BASE + 0x85) ++#define REG_CMDQ1_43_L (REG_CMDQ1_BASE + 0x86) ++#define REG_CMDQ1_43_H (REG_CMDQ1_BASE + 0x87) ++#define REG_CMDQ1_44_L (REG_CMDQ1_BASE + 0x88) ++#define REG_CMDQ1_44_H (REG_CMDQ1_BASE + 0x89) ++#define REG_CMDQ1_45_L (REG_CMDQ1_BASE + 0x8A) ++#define REG_CMDQ1_45_H (REG_CMDQ1_BASE + 0x8B) ++#define REG_CMDQ1_46_L (REG_CMDQ1_BASE + 0x8C) ++#define REG_CMDQ1_46_H (REG_CMDQ1_BASE + 0x8D) ++#define REG_CMDQ1_47_L (REG_CMDQ1_BASE + 0x8E) ++#define REG_CMDQ1_47_H (REG_CMDQ1_BASE + 0x8F) ++#define REG_CMDQ1_48_L (REG_CMDQ1_BASE + 0x90) ++#define REG_CMDQ1_48_H (REG_CMDQ1_BASE + 0x91) ++#define REG_CMDQ1_49_L (REG_CMDQ1_BASE + 0x92) ++#define REG_CMDQ1_49_H (REG_CMDQ1_BASE + 0x93) ++#define REG_CMDQ1_4A_L (REG_CMDQ1_BASE + 0x94) ++#define REG_CMDQ1_4A_H (REG_CMDQ1_BASE + 0x95) ++#define REG_CMDQ1_4B_L (REG_CMDQ1_BASE + 0x96) ++#define REG_CMDQ1_4B_H (REG_CMDQ1_BASE + 0x97) ++#define REG_CMDQ1_4C_L (REG_CMDQ1_BASE + 0x98) ++#define REG_CMDQ1_4C_H (REG_CMDQ1_BASE + 0x99) ++#define REG_CMDQ1_4D_L (REG_CMDQ1_BASE + 0x9A) ++#define REG_CMDQ1_4D_H (REG_CMDQ1_BASE + 0x9B) ++#define REG_CMDQ1_4E_L (REG_CMDQ1_BASE + 0x9C) ++#define REG_CMDQ1_4E_H (REG_CMDQ1_BASE + 0x9D) ++#define REG_CMDQ1_4F_L (REG_CMDQ1_BASE + 0x9E) ++#define REG_CMDQ1_4F_H (REG_CMDQ1_BASE + 0x9F) ++#define REG_CMDQ1_50_L (REG_CMDQ1_BASE + 0xA0) ++#define REG_CMDQ1_50_H (REG_CMDQ1_BASE + 0xA1) ++#define REG_CMDQ1_51_L (REG_CMDQ1_BASE + 0xA2) ++#define REG_CMDQ1_51_H (REG_CMDQ1_BASE + 0xA3) ++#define REG_CMDQ1_52_L (REG_CMDQ1_BASE + 0xA4) ++#define REG_CMDQ1_52_H (REG_CMDQ1_BASE + 0xA5) ++#define REG_CMDQ1_53_L (REG_CMDQ1_BASE + 0xA6) ++#define REG_CMDQ1_53_H (REG_CMDQ1_BASE + 0xA7) ++#define REG_CMDQ1_54_L (REG_CMDQ1_BASE + 0xA8) ++#define REG_CMDQ1_54_H (REG_CMDQ1_BASE + 0xA9) ++#define REG_CMDQ1_55_L (REG_CMDQ1_BASE + 0xAA) ++#define REG_CMDQ1_55_H (REG_CMDQ1_BASE + 0xAB) ++#define REG_CMDQ1_56_L (REG_CMDQ1_BASE + 0xAC) ++#define REG_CMDQ1_56_H (REG_CMDQ1_BASE + 0xAD) ++#define REG_CMDQ1_57_L (REG_CMDQ1_BASE + 0xAE) ++#define REG_CMDQ1_57_H (REG_CMDQ1_BASE + 0xAF) ++#define REG_CMDQ1_58_L (REG_CMDQ1_BASE + 0xB0) ++#define REG_CMDQ1_58_H (REG_CMDQ1_BASE + 0xB1) ++#define REG_CMDQ1_59_L (REG_CMDQ1_BASE + 0xB2) ++#define REG_CMDQ1_59_H (REG_CMDQ1_BASE + 0xB3) ++#define REG_CMDQ1_5A_L (REG_CMDQ1_BASE + 0xB4) ++#define REG_CMDQ1_5A_H (REG_CMDQ1_BASE + 0xB5) ++#define REG_CMDQ1_5B_L (REG_CMDQ1_BASE + 0xB6) ++#define REG_CMDQ1_5B_H (REG_CMDQ1_BASE + 0xB7) ++#define REG_CMDQ1_5C_L (REG_CMDQ1_BASE + 0xB8) ++#define REG_CMDQ1_5C_H (REG_CMDQ1_BASE + 0xB9) ++#define REG_CMDQ1_5D_L (REG_CMDQ1_BASE + 0xBA) ++#define REG_CMDQ1_5D_H (REG_CMDQ1_BASE + 0xBB) ++#define REG_CMDQ1_5E_L (REG_CMDQ1_BASE + 0xBC) ++#define REG_CMDQ1_5E_H (REG_CMDQ1_BASE + 0xBD) ++#define REG_CMDQ1_5F_L (REG_CMDQ1_BASE + 0xBE) ++#define REG_CMDQ1_5F_H (REG_CMDQ1_BASE + 0xBF) ++#define REG_CMDQ1_60_L (REG_CMDQ1_BASE + 0xC0) ++#define REG_CMDQ1_60_H (REG_CMDQ1_BASE + 0xC1) ++#define REG_CMDQ1_61_L (REG_CMDQ1_BASE + 0xC2) ++#define REG_CMDQ1_61_H (REG_CMDQ1_BASE + 0xC3) ++#define REG_CMDQ1_62_L (REG_CMDQ1_BASE + 0xC4) ++#define REG_CMDQ1_62_H (REG_CMDQ1_BASE + 0xC5) ++#define REG_CMDQ1_63_L (REG_CMDQ1_BASE + 0xC6) ++#define REG_CMDQ1_63_H (REG_CMDQ1_BASE + 0xC7) ++#define REG_CMDQ1_64_L (REG_CMDQ1_BASE + 0xC8) ++#define REG_CMDQ1_64_H (REG_CMDQ1_BASE + 0xC9) ++#define REG_CMDQ1_65_L (REG_CMDQ1_BASE + 0xCA) ++#define REG_CMDQ1_65_H (REG_CMDQ1_BASE + 0xCB) ++#define REG_CMDQ1_66_L (REG_CMDQ1_BASE + 0xCC) ++#define REG_CMDQ1_66_H (REG_CMDQ1_BASE + 0xCD) ++#define REG_CMDQ1_67_L (REG_CMDQ1_BASE + 0xCE) ++#define REG_CMDQ1_67_H (REG_CMDQ1_BASE + 0xCF) ++#define REG_CMDQ1_68_L (REG_CMDQ1_BASE + 0xD0) ++#define REG_CMDQ1_68_H (REG_CMDQ1_BASE + 0xD1) ++#define REG_CMDQ1_69_L (REG_CMDQ1_BASE + 0xD2) ++#define REG_CMDQ1_69_H (REG_CMDQ1_BASE + 0xD3) ++#define REG_CMDQ1_6A_L (REG_CMDQ1_BASE + 0xD4) ++#define REG_CMDQ1_6A_H (REG_CMDQ1_BASE + 0xD5) ++#define REG_CMDQ1_6B_L (REG_CMDQ1_BASE + 0xD6) ++#define REG_CMDQ1_6B_H (REG_CMDQ1_BASE + 0xD7) ++#define REG_CMDQ1_6C_L (REG_CMDQ1_BASE + 0xD8) ++#define REG_CMDQ1_6C_H (REG_CMDQ1_BASE + 0xD9) ++#define REG_CMDQ1_6D_L (REG_CMDQ1_BASE + 0xDA) ++#define REG_CMDQ1_6D_H (REG_CMDQ1_BASE + 0xDB) ++#define REG_CMDQ1_6E_L (REG_CMDQ1_BASE + 0xDC) ++#define REG_CMDQ1_6E_H (REG_CMDQ1_BASE + 0xDD) ++#define REG_CMDQ1_6F_L (REG_CMDQ1_BASE + 0xDE) ++#define REG_CMDQ1_6F_H (REG_CMDQ1_BASE + 0xDF) ++#define REG_CMDQ1_70_L (REG_CMDQ1_BASE + 0xE0) ++#define REG_CMDQ1_70_H (REG_CMDQ1_BASE + 0xE1) ++#define REG_CMDQ1_71_L (REG_CMDQ1_BASE + 0xE2) ++#define REG_CMDQ1_71_H (REG_CMDQ1_BASE + 0xE3) ++#define REG_CMDQ1_72_L (REG_CMDQ1_BASE + 0xE4) ++#define REG_CMDQ1_72_H (REG_CMDQ1_BASE + 0xE5) ++#define REG_CMDQ1_73_L (REG_CMDQ1_BASE + 0xE6) ++#define REG_CMDQ1_73_H (REG_CMDQ1_BASE + 0xE7) ++#define REG_CMDQ1_74_L (REG_CMDQ1_BASE + 0xE8) ++#define REG_CMDQ1_74_H (REG_CMDQ1_BASE + 0xE9) ++#define REG_CMDQ1_75_L (REG_CMDQ1_BASE + 0xEA) ++#define REG_CMDQ1_75_H (REG_CMDQ1_BASE + 0xEB) ++#define REG_CMDQ1_76_L (REG_CMDQ1_BASE + 0xEC) ++#define REG_CMDQ1_76_H (REG_CMDQ1_BASE + 0xED) ++#define REG_CMDQ1_77_L (REG_CMDQ1_BASE + 0xEE) ++#define REG_CMDQ1_77_H (REG_CMDQ1_BASE + 0xEF) ++#define REG_CMDQ1_78_L (REG_CMDQ1_BASE + 0xF0) ++#define REG_CMDQ1_78_H (REG_CMDQ1_BASE + 0xF1) ++#define REG_CMDQ1_79_L (REG_CMDQ1_BASE + 0xF2) ++#define REG_CMDQ1_79_H (REG_CMDQ1_BASE + 0xF3) ++#define REG_CMDQ1_7A_L (REG_CMDQ1_BASE + 0xF4) ++#define REG_CMDQ1_7A_H (REG_CMDQ1_BASE + 0xF5) ++#define REG_CMDQ1_7B_L (REG_CMDQ1_BASE + 0xF6) ++#define REG_CMDQ1_7B_H (REG_CMDQ1_BASE + 0xF7) ++#define REG_CMDQ1_7C_L (REG_CMDQ1_BASE + 0xF8) ++#define REG_CMDQ1_7C_H (REG_CMDQ1_BASE + 0xF9) ++#define REG_CMDQ1_7D_L (REG_CMDQ1_BASE + 0xFA) ++#define REG_CMDQ1_7D_H (REG_CMDQ1_BASE + 0xFB) ++#define REG_CMDQ1_7E_L (REG_CMDQ1_BASE + 0xFC) ++#define REG_CMDQ1_7E_H (REG_CMDQ1_BASE + 0xFD) ++#define REG_CMDQ1_7F_L (REG_CMDQ1_BASE + 0xFE) ++#define REG_CMDQ1_7F_H (REG_CMDQ1_BASE + 0xFF) ++#define REG_CMDQ2_00_L (REG_CMDQ2_BASE + 0x00) ++#define REG_CMDQ2_00_H (REG_CMDQ2_BASE + 0x01) ++#define REG_CMDQ2_01_L (REG_CMDQ2_BASE + 0x02) ++#define REG_CMDQ2_01_H (REG_CMDQ2_BASE + 0x03) ++#define REG_CMDQ2_02_L (REG_CMDQ2_BASE + 0x04) ++#define REG_CMDQ2_02_H (REG_CMDQ2_BASE + 0x05) ++#define REG_CMDQ2_03_L (REG_CMDQ2_BASE + 0x06) ++#define REG_CMDQ2_03_H (REG_CMDQ2_BASE + 0x07) ++#define REG_CMDQ2_04_L (REG_CMDQ2_BASE + 0x08) ++#define REG_CMDQ2_04_H (REG_CMDQ2_BASE + 0x09) ++#define REG_CMDQ2_05_L (REG_CMDQ2_BASE + 0x0A) ++#define REG_CMDQ2_05_H (REG_CMDQ2_BASE + 0x0B) ++#define REG_CMDQ2_06_L (REG_CMDQ2_BASE + 0x0C) ++#define REG_CMDQ2_06_H (REG_CMDQ2_BASE + 0x0D) ++#define REG_CMDQ2_07_L (REG_CMDQ2_BASE + 0x0E) ++#define REG_CMDQ2_07_H (REG_CMDQ2_BASE + 0x0F) ++#define REG_CMDQ2_08_L (REG_CMDQ2_BASE + 0x10) ++#define REG_CMDQ2_08_H (REG_CMDQ2_BASE + 0x11) ++#define REG_CMDQ2_09_L (REG_CMDQ2_BASE + 0x12) ++#define REG_CMDQ2_09_H (REG_CMDQ2_BASE + 0x13) ++#define REG_CMDQ2_0A_L (REG_CMDQ2_BASE + 0x14) ++#define REG_CMDQ2_0A_H (REG_CMDQ2_BASE + 0x15) ++#define REG_CMDQ2_0B_L (REG_CMDQ2_BASE + 0x16) ++#define REG_CMDQ2_0B_H (REG_CMDQ2_BASE + 0x17) ++#define REG_CMDQ2_0C_L (REG_CMDQ2_BASE + 0x18) ++#define REG_CMDQ2_0C_H (REG_CMDQ2_BASE + 0x19) ++#define REG_CMDQ2_0D_L (REG_CMDQ2_BASE + 0x1A) ++#define REG_CMDQ2_0D_H (REG_CMDQ2_BASE + 0x1B) ++#define REG_CMDQ2_0E_L (REG_CMDQ2_BASE + 0x1C) ++#define REG_CMDQ2_0E_H (REG_CMDQ2_BASE + 0x1D) ++#define REG_CMDQ2_0F_L (REG_CMDQ2_BASE + 0x1E) ++#define REG_CMDQ2_0F_H (REG_CMDQ2_BASE + 0x1F) ++#define REG_CMDQ2_10_L (REG_CMDQ2_BASE + 0x20) ++#define REG_CMDQ2_10_H (REG_CMDQ2_BASE + 0x21) ++#define REG_CMDQ2_11_L (REG_CMDQ2_BASE + 0x22) ++#define REG_CMDQ2_11_H (REG_CMDQ2_BASE + 0x23) ++#define REG_CMDQ2_12_L (REG_CMDQ2_BASE + 0x24) ++#define REG_CMDQ2_12_H (REG_CMDQ2_BASE + 0x25) ++#define REG_CMDQ2_13_L (REG_CMDQ2_BASE + 0x26) ++#define REG_CMDQ2_13_H (REG_CMDQ2_BASE + 0x27) ++#define REG_CMDQ2_14_L (REG_CMDQ2_BASE + 0x28) ++#define REG_CMDQ2_14_H (REG_CMDQ2_BASE + 0x29) ++#define REG_CMDQ2_15_L (REG_CMDQ2_BASE + 0x2A) ++#define REG_CMDQ2_15_H (REG_CMDQ2_BASE + 0x2B) ++#define REG_CMDQ2_16_L (REG_CMDQ2_BASE + 0x2C) ++#define REG_CMDQ2_16_H (REG_CMDQ2_BASE + 0x2D) ++#define REG_CMDQ2_17_L (REG_CMDQ2_BASE + 0x2E) ++#define REG_CMDQ2_17_H (REG_CMDQ2_BASE + 0x2F) ++#define REG_CMDQ2_18_L (REG_CMDQ2_BASE + 0x30) ++#define REG_CMDQ2_18_H (REG_CMDQ2_BASE + 0x31) ++#define REG_CMDQ2_19_L (REG_CMDQ2_BASE + 0x32) ++#define REG_CMDQ2_19_H (REG_CMDQ2_BASE + 0x33) ++#define REG_CMDQ2_1A_L (REG_CMDQ2_BASE + 0x34) ++#define REG_CMDQ2_1A_H (REG_CMDQ2_BASE + 0x35) ++#define REG_CMDQ2_1B_L (REG_CMDQ2_BASE + 0x36) ++#define REG_CMDQ2_1B_H (REG_CMDQ2_BASE + 0x37) ++#define REG_CMDQ2_1C_L (REG_CMDQ2_BASE + 0x38) ++#define REG_CMDQ2_1C_H (REG_CMDQ2_BASE + 0x39) ++#define REG_CMDQ2_1D_L (REG_CMDQ2_BASE + 0x3A) ++#define REG_CMDQ2_1D_H (REG_CMDQ2_BASE + 0x3B) ++#define REG_CMDQ2_1E_L (REG_CMDQ2_BASE + 0x3C) ++#define REG_CMDQ2_1E_H (REG_CMDQ2_BASE + 0x3D) ++#define REG_CMDQ2_1F_L (REG_CMDQ2_BASE + 0x3E) ++#define REG_CMDQ2_1F_H (REG_CMDQ2_BASE + 0x3F) ++#define REG_CMDQ2_20_L (REG_CMDQ2_BASE + 0x40) ++#define REG_CMDQ2_20_H (REG_CMDQ2_BASE + 0x41) ++#define REG_CMDQ2_21_L (REG_CMDQ2_BASE + 0x42) ++#define REG_CMDQ2_21_H (REG_CMDQ2_BASE + 0x43) ++#define REG_CMDQ2_22_L (REG_CMDQ2_BASE + 0x44) ++#define REG_CMDQ2_22_H (REG_CMDQ2_BASE + 0x45) ++#define REG_CMDQ2_23_L (REG_CMDQ2_BASE + 0x46) ++#define REG_CMDQ2_23_H (REG_CMDQ2_BASE + 0x47) ++#define REG_CMDQ2_24_L (REG_CMDQ2_BASE + 0x48) ++#define REG_CMDQ2_24_H (REG_CMDQ2_BASE + 0x49) ++#define REG_CMDQ2_25_L (REG_CMDQ2_BASE + 0x4A) ++#define REG_CMDQ2_25_H (REG_CMDQ2_BASE + 0x4B) ++#define REG_CMDQ2_26_L (REG_CMDQ2_BASE + 0x4C) ++#define REG_CMDQ2_26_H (REG_CMDQ2_BASE + 0x4D) ++#define REG_CMDQ2_27_L (REG_CMDQ2_BASE + 0x4E) ++#define REG_CMDQ2_27_H (REG_CMDQ2_BASE + 0x4F) ++#define REG_CMDQ2_28_L (REG_CMDQ2_BASE + 0x50) ++#define REG_CMDQ2_28_H (REG_CMDQ2_BASE + 0x51) ++#define REG_CMDQ2_29_L (REG_CMDQ2_BASE + 0x52) ++#define REG_CMDQ2_29_H (REG_CMDQ2_BASE + 0x53) ++#define REG_CMDQ2_2A_L (REG_CMDQ2_BASE + 0x54) ++#define REG_CMDQ2_2A_H (REG_CMDQ2_BASE + 0x55) ++#define REG_CMDQ2_2B_L (REG_CMDQ2_BASE + 0x56) ++#define REG_CMDQ2_2B_H (REG_CMDQ2_BASE + 0x57) ++#define REG_CMDQ2_2C_L (REG_CMDQ2_BASE + 0x58) ++#define REG_CMDQ2_2C_H (REG_CMDQ2_BASE + 0x59) ++#define REG_CMDQ2_2D_L (REG_CMDQ2_BASE + 0x5A) ++#define REG_CMDQ2_2D_H (REG_CMDQ2_BASE + 0x5B) ++#define REG_CMDQ2_2E_L (REG_CMDQ2_BASE + 0x5C) ++#define REG_CMDQ2_2E_H (REG_CMDQ2_BASE + 0x5D) ++#define REG_CMDQ2_2F_L (REG_CMDQ2_BASE + 0x5E) ++#define REG_CMDQ2_2F_H (REG_CMDQ2_BASE + 0x5F) ++#define REG_CMDQ2_30_L (REG_CMDQ2_BASE + 0x60) ++#define REG_CMDQ2_30_H (REG_CMDQ2_BASE + 0x61) ++#define REG_CMDQ2_31_L (REG_CMDQ2_BASE + 0x62) ++#define REG_CMDQ2_31_H (REG_CMDQ2_BASE + 0x63) ++#define REG_CMDQ2_32_L (REG_CMDQ2_BASE + 0x64) ++#define REG_CMDQ2_32_H (REG_CMDQ2_BASE + 0x65) ++#define REG_CMDQ2_33_L (REG_CMDQ2_BASE + 0x66) ++#define REG_CMDQ2_33_H (REG_CMDQ2_BASE + 0x67) ++#define REG_CMDQ2_34_L (REG_CMDQ2_BASE + 0x68) ++#define REG_CMDQ2_34_H (REG_CMDQ2_BASE + 0x69) ++#define REG_CMDQ2_35_L (REG_CMDQ2_BASE + 0x6A) ++#define REG_CMDQ2_35_H (REG_CMDQ2_BASE + 0x6B) ++#define REG_CMDQ2_36_L (REG_CMDQ2_BASE + 0x6C) ++#define REG_CMDQ2_36_H (REG_CMDQ2_BASE + 0x6D) ++#define REG_CMDQ2_37_L (REG_CMDQ2_BASE + 0x6E) ++#define REG_CMDQ2_37_H (REG_CMDQ2_BASE + 0x6F) ++#define REG_CMDQ2_38_L (REG_CMDQ2_BASE + 0x70) ++#define REG_CMDQ2_38_H (REG_CMDQ2_BASE + 0x71) ++#define REG_CMDQ2_39_L (REG_CMDQ2_BASE + 0x72) ++#define REG_CMDQ2_39_H (REG_CMDQ2_BASE + 0x73) ++#define REG_CMDQ2_3A_L (REG_CMDQ2_BASE + 0x74) ++#define REG_CMDQ2_3A_H (REG_CMDQ2_BASE + 0x75) ++#define REG_CMDQ2_3B_L (REG_CMDQ2_BASE + 0x76) ++#define REG_CMDQ2_3B_H (REG_CMDQ2_BASE + 0x77) ++#define REG_CMDQ2_3C_L (REG_CMDQ2_BASE + 0x78) ++#define REG_CMDQ2_3C_H (REG_CMDQ2_BASE + 0x79) ++#define REG_CMDQ2_3D_L (REG_CMDQ2_BASE + 0x7A) ++#define REG_CMDQ2_3D_H (REG_CMDQ2_BASE + 0x7B) ++#define REG_CMDQ2_3E_L (REG_CMDQ2_BASE + 0x7C) ++#define REG_CMDQ2_3E_H (REG_CMDQ2_BASE + 0x7D) ++#define REG_CMDQ2_3F_L (REG_CMDQ2_BASE + 0x7E) ++#define REG_CMDQ2_3F_H (REG_CMDQ2_BASE + 0x7F) ++#define REG_CMDQ2_40_L (REG_CMDQ2_BASE + 0x80) ++#define REG_CMDQ2_40_H (REG_CMDQ2_BASE + 0x81) ++#define REG_CMDQ2_41_L (REG_CMDQ2_BASE + 0x82) ++#define REG_CMDQ2_41_H (REG_CMDQ2_BASE + 0x83) ++#define REG_CMDQ2_42_L (REG_CMDQ2_BASE + 0x84) ++#define REG_CMDQ2_42_H (REG_CMDQ2_BASE + 0x85) ++#define REG_CMDQ2_43_L (REG_CMDQ2_BASE + 0x86) ++#define REG_CMDQ2_43_H (REG_CMDQ2_BASE + 0x87) ++#define REG_CMDQ2_44_L (REG_CMDQ2_BASE + 0x88) ++#define REG_CMDQ2_44_H (REG_CMDQ2_BASE + 0x89) ++#define REG_CMDQ2_45_L (REG_CMDQ2_BASE + 0x8A) ++#define REG_CMDQ2_45_H (REG_CMDQ2_BASE + 0x8B) ++#define REG_CMDQ2_46_L (REG_CMDQ2_BASE + 0x8C) ++#define REG_CMDQ2_46_H (REG_CMDQ2_BASE + 0x8D) ++#define REG_CMDQ2_47_L (REG_CMDQ2_BASE + 0x8E) ++#define REG_CMDQ2_47_H (REG_CMDQ2_BASE + 0x8F) ++#define REG_CMDQ2_48_L (REG_CMDQ2_BASE + 0x90) ++#define REG_CMDQ2_48_H (REG_CMDQ2_BASE + 0x91) ++#define REG_CMDQ2_49_L (REG_CMDQ2_BASE + 0x92) ++#define REG_CMDQ2_49_H (REG_CMDQ2_BASE + 0x93) ++#define REG_CMDQ2_4A_L (REG_CMDQ2_BASE + 0x94) ++#define REG_CMDQ2_4A_H (REG_CMDQ2_BASE + 0x95) ++#define REG_CMDQ2_4B_L (REG_CMDQ2_BASE + 0x96) ++#define REG_CMDQ2_4B_H (REG_CMDQ2_BASE + 0x97) ++#define REG_CMDQ2_4C_L (REG_CMDQ2_BASE + 0x98) ++#define REG_CMDQ2_4C_H (REG_CMDQ2_BASE + 0x99) ++#define REG_CMDQ2_4D_L (REG_CMDQ2_BASE + 0x9A) ++#define REG_CMDQ2_4D_H (REG_CMDQ2_BASE + 0x9B) ++#define REG_CMDQ2_4E_L (REG_CMDQ2_BASE + 0x9C) ++#define REG_CMDQ2_4E_H (REG_CMDQ2_BASE + 0x9D) ++#define REG_CMDQ2_4F_L (REG_CMDQ2_BASE + 0x9E) ++#define REG_CMDQ2_4F_H (REG_CMDQ2_BASE + 0x9F) ++#define REG_CMDQ2_50_L (REG_CMDQ2_BASE + 0xA0) ++#define REG_CMDQ2_50_H (REG_CMDQ2_BASE + 0xA1) ++#define REG_CMDQ2_51_L (REG_CMDQ2_BASE + 0xA2) ++#define REG_CMDQ2_51_H (REG_CMDQ2_BASE + 0xA3) ++#define REG_CMDQ2_52_L (REG_CMDQ2_BASE + 0xA4) ++#define REG_CMDQ2_52_H (REG_CMDQ2_BASE + 0xA5) ++#define REG_CMDQ2_53_L (REG_CMDQ2_BASE + 0xA6) ++#define REG_CMDQ2_53_H (REG_CMDQ2_BASE + 0xA7) ++#define REG_CMDQ2_54_L (REG_CMDQ2_BASE + 0xA8) ++#define REG_CMDQ2_54_H (REG_CMDQ2_BASE + 0xA9) ++#define REG_CMDQ2_55_L (REG_CMDQ2_BASE + 0xAA) ++#define REG_CMDQ2_55_H (REG_CMDQ2_BASE + 0xAB) ++#define REG_CMDQ2_56_L (REG_CMDQ2_BASE + 0xAC) ++#define REG_CMDQ2_56_H (REG_CMDQ2_BASE + 0xAD) ++#define REG_CMDQ2_57_L (REG_CMDQ2_BASE + 0xAE) ++#define REG_CMDQ2_57_H (REG_CMDQ2_BASE + 0xAF) ++#define REG_CMDQ2_58_L (REG_CMDQ2_BASE + 0xB0) ++#define REG_CMDQ2_58_H (REG_CMDQ2_BASE + 0xB1) ++#define REG_CMDQ2_59_L (REG_CMDQ2_BASE + 0xB2) ++#define REG_CMDQ2_59_H (REG_CMDQ2_BASE + 0xB3) ++#define REG_CMDQ2_5A_L (REG_CMDQ2_BASE + 0xB4) ++#define REG_CMDQ2_5A_H (REG_CMDQ2_BASE + 0xB5) ++#define REG_CMDQ2_5B_L (REG_CMDQ2_BASE + 0xB6) ++#define REG_CMDQ2_5B_H (REG_CMDQ2_BASE + 0xB7) ++#define REG_CMDQ2_5C_L (REG_CMDQ2_BASE + 0xB8) ++#define REG_CMDQ2_5C_H (REG_CMDQ2_BASE + 0xB9) ++#define REG_CMDQ2_5D_L (REG_CMDQ2_BASE + 0xBA) ++#define REG_CMDQ2_5D_H (REG_CMDQ2_BASE + 0xBB) ++#define REG_CMDQ2_5E_L (REG_CMDQ2_BASE + 0xBC) ++#define REG_CMDQ2_5E_H (REG_CMDQ2_BASE + 0xBD) ++#define REG_CMDQ2_5F_L (REG_CMDQ2_BASE + 0xBE) ++#define REG_CMDQ2_5F_H (REG_CMDQ2_BASE + 0xBF) ++#define REG_CMDQ2_60_L (REG_CMDQ2_BASE + 0xC0) ++#define REG_CMDQ2_60_H (REG_CMDQ2_BASE + 0xC1) ++#define REG_CMDQ2_61_L (REG_CMDQ2_BASE + 0xC2) ++#define REG_CMDQ2_61_H (REG_CMDQ2_BASE + 0xC3) ++#define REG_CMDQ2_62_L (REG_CMDQ2_BASE + 0xC4) ++#define REG_CMDQ2_62_H (REG_CMDQ2_BASE + 0xC5) ++#define REG_CMDQ2_63_L (REG_CMDQ2_BASE + 0xC6) ++#define REG_CMDQ2_63_H (REG_CMDQ2_BASE + 0xC7) ++#define REG_CMDQ2_64_L (REG_CMDQ2_BASE + 0xC8) ++#define REG_CMDQ2_64_H (REG_CMDQ2_BASE + 0xC9) ++#define REG_CMDQ2_65_L (REG_CMDQ2_BASE + 0xCA) ++#define REG_CMDQ2_65_H (REG_CMDQ2_BASE + 0xCB) ++#define REG_CMDQ2_66_L (REG_CMDQ2_BASE + 0xCC) ++#define REG_CMDQ2_66_H (REG_CMDQ2_BASE + 0xCD) ++#define REG_CMDQ2_67_L (REG_CMDQ2_BASE + 0xCE) ++#define REG_CMDQ2_67_H (REG_CMDQ2_BASE + 0xCF) ++#define REG_CMDQ2_68_L (REG_CMDQ2_BASE + 0xD0) ++#define REG_CMDQ2_68_H (REG_CMDQ2_BASE + 0xD1) ++#define REG_CMDQ2_69_L (REG_CMDQ2_BASE + 0xD2) ++#define REG_CMDQ2_69_H (REG_CMDQ2_BASE + 0xD3) ++#define REG_CMDQ2_6A_L (REG_CMDQ2_BASE + 0xD4) ++#define REG_CMDQ2_6A_H (REG_CMDQ2_BASE + 0xD5) ++#define REG_CMDQ2_6B_L (REG_CMDQ2_BASE + 0xD6) ++#define REG_CMDQ2_6B_H (REG_CMDQ2_BASE + 0xD7) ++#define REG_CMDQ2_6C_L (REG_CMDQ2_BASE + 0xD8) ++#define REG_CMDQ2_6C_H (REG_CMDQ2_BASE + 0xD9) ++#define REG_CMDQ2_6D_L (REG_CMDQ2_BASE + 0xDA) ++#define REG_CMDQ2_6D_H (REG_CMDQ2_BASE + 0xDB) ++#define REG_CMDQ2_6E_L (REG_CMDQ2_BASE + 0xDC) ++#define REG_CMDQ2_6E_H (REG_CMDQ2_BASE + 0xDD) ++#define REG_CMDQ2_6F_L (REG_CMDQ2_BASE + 0xDE) ++#define REG_CMDQ2_6F_H (REG_CMDQ2_BASE + 0xDF) ++#define REG_CMDQ2_70_L (REG_CMDQ2_BASE + 0xE0) ++#define REG_CMDQ2_70_H (REG_CMDQ2_BASE + 0xE1) ++#define REG_CMDQ2_71_L (REG_CMDQ2_BASE + 0xE2) ++#define REG_CMDQ2_71_H (REG_CMDQ2_BASE + 0xE3) ++#define REG_CMDQ2_72_L (REG_CMDQ2_BASE + 0xE4) ++#define REG_CMDQ2_72_H (REG_CMDQ2_BASE + 0xE5) ++#define REG_CMDQ2_73_L (REG_CMDQ2_BASE + 0xE6) ++#define REG_CMDQ2_73_H (REG_CMDQ2_BASE + 0xE7) ++#define REG_CMDQ2_74_L (REG_CMDQ2_BASE + 0xE8) ++#define REG_CMDQ2_74_H (REG_CMDQ2_BASE + 0xE9) ++#define REG_CMDQ2_75_L (REG_CMDQ2_BASE + 0xEA) ++#define REG_CMDQ2_75_H (REG_CMDQ2_BASE + 0xEB) ++#define REG_CMDQ2_76_L (REG_CMDQ2_BASE + 0xEC) ++#define REG_CMDQ2_76_H (REG_CMDQ2_BASE + 0xED) ++#define REG_CMDQ2_77_L (REG_CMDQ2_BASE + 0xEE) ++#define REG_CMDQ2_77_H (REG_CMDQ2_BASE + 0xEF) ++#define REG_CMDQ2_78_L (REG_CMDQ2_BASE + 0xF0) ++#define REG_CMDQ2_78_H (REG_CMDQ2_BASE + 0xF1) ++#define REG_CMDQ2_79_L (REG_CMDQ2_BASE + 0xF2) ++#define REG_CMDQ2_79_H (REG_CMDQ2_BASE + 0xF3) ++#define REG_CMDQ2_7A_L (REG_CMDQ2_BASE + 0xF4) ++#define REG_CMDQ2_7A_H (REG_CMDQ2_BASE + 0xF5) ++#define REG_CMDQ2_7B_L (REG_CMDQ2_BASE + 0xF6) ++#define REG_CMDQ2_7B_H (REG_CMDQ2_BASE + 0xF7) ++#define REG_CMDQ2_7C_L (REG_CMDQ2_BASE + 0xF8) ++#define REG_CMDQ2_7C_H (REG_CMDQ2_BASE + 0xF9) ++#define REG_CMDQ2_7D_L (REG_CMDQ2_BASE + 0xFA) ++#define REG_CMDQ2_7D_H (REG_CMDQ2_BASE + 0xFB) ++#define REG_CMDQ2_7E_L (REG_CMDQ2_BASE + 0xFC) ++#define REG_CMDQ2_7E_H (REG_CMDQ2_BASE + 0xFD) ++#define REG_CMDQ2_7F_L (REG_CMDQ2_BASE + 0xFE) ++#define REG_CMDQ2_7F_H (REG_CMDQ2_BASE + 0xFF) ++ ++//------------------------------------------------------------------------------------- ++#define REG_MCM_00_L (REG_MCM_BASE + 0x00) ++#define REG_MCM_00_H (REG_MCM_BASE + 0x01) ++#define REG_MCM_01_L (REG_MCM_BASE + 0x02) ++#define REG_MCM_01_H (REG_MCM_BASE + 0x03) ++#define REG_MCM_02_L (REG_MCM_BASE + 0x04) ++#define REG_MCM_02_H (REG_MCM_BASE + 0x05) ++#define REG_MCM_03_L (REG_MCM_BASE + 0x06) ++#define REG_MCM_03_H (REG_MCM_BASE + 0x07) ++#define REG_MCM_04_L (REG_MCM_BASE + 0x08) ++#define REG_MCM_04_H (REG_MCM_BASE + 0x09) ++#define REG_MCM_05_L (REG_MCM_BASE + 0x0A) ++#define REG_MCM_05_H (REG_MCM_BASE + 0x0B) ++#define REG_MCM_06_L (REG_MCM_BASE + 0x0C) ++#define REG_MCM_06_H (REG_MCM_BASE + 0x0D) ++#define REG_MCM_07_L (REG_MCM_BASE + 0x0E) ++#define REG_MCM_07_H (REG_MCM_BASE + 0x0F) ++#define REG_MCM_08_L (REG_MCM_BASE + 0x10) ++#define REG_MCM_08_H (REG_MCM_BASE + 0x11) ++#define REG_MCM_09_L (REG_MCM_BASE + 0x12) ++#define REG_MCM_09_H (REG_MCM_BASE + 0x13) ++#define REG_MCM_0A_L (REG_MCM_BASE + 0x14) ++#define REG_MCM_0A_H (REG_MCM_BASE + 0x15) ++#define REG_MCM_0B_L (REG_MCM_BASE + 0x16) ++#define REG_MCM_0B_H (REG_MCM_BASE + 0x17) ++#define REG_MCM_0C_L (REG_MCM_BASE + 0x18) ++#define REG_MCM_0C_H (REG_MCM_BASE + 0x19) ++#define REG_MCM_0D_L (REG_MCM_BASE + 0x1A) ++#define REG_MCM_0D_H (REG_MCM_BASE + 0x1B) ++#define REG_MCM_0E_L (REG_MCM_BASE + 0x1C) ++#define REG_MCM_0E_H (REG_MCM_BASE + 0x1D) ++#define REG_MCM_0F_L (REG_MCM_BASE + 0x1E) ++#define REG_MCM_0F_H (REG_MCM_BASE + 0x1F) ++#define REG_MCM_10_L (REG_MCM_BASE + 0x20) ++#define REG_MCM_10_H (REG_MCM_BASE + 0x21) ++#define REG_MCM_11_L (REG_MCM_BASE + 0x22) ++#define REG_MCM_11_H (REG_MCM_BASE + 0x23) ++#define REG_MCM_12_L (REG_MCM_BASE + 0x24) ++#define REG_MCM_12_H (REG_MCM_BASE + 0x25) ++#define REG_MCM_13_L (REG_MCM_BASE + 0x26) ++#define REG_MCM_13_H (REG_MCM_BASE + 0x27) ++#define REG_MCM_14_L (REG_MCM_BASE + 0x28) ++#define REG_MCM_14_H (REG_MCM_BASE + 0x29) ++#define REG_MCM_15_L (REG_MCM_BASE + 0x2A) ++#define REG_MCM_15_H (REG_MCM_BASE + 0x2B) ++#define REG_MCM_16_L (REG_MCM_BASE + 0x2C) ++#define REG_MCM_16_H (REG_MCM_BASE + 0x2D) ++#define REG_MCM_17_L (REG_MCM_BASE + 0x2E) ++#define REG_MCM_17_H (REG_MCM_BASE + 0x2F) ++#define REG_MCM_18_L (REG_MCM_BASE + 0x30) ++#define REG_MCM_18_H (REG_MCM_BASE + 0x31) ++#define REG_MCM_19_L (REG_MCM_BASE + 0x32) ++#define REG_MCM_19_H (REG_MCM_BASE + 0x33) ++#define REG_MCM_1A_L (REG_MCM_BASE + 0x34) ++#define REG_MCM_1A_H (REG_MCM_BASE + 0x35) ++#define REG_MCM_1B_L (REG_MCM_BASE + 0x36) ++#define REG_MCM_1B_H (REG_MCM_BASE + 0x37) ++#define REG_MCM_1C_L (REG_MCM_BASE + 0x38) ++#define REG_MCM_1C_H (REG_MCM_BASE + 0x39) ++#define REG_MCM_1D_L (REG_MCM_BASE + 0x3A) ++#define REG_MCM_1D_H (REG_MCM_BASE + 0x3B) ++#define REG_MCM_1E_L (REG_MCM_BASE + 0x3C) ++#define REG_MCM_1E_H (REG_MCM_BASE + 0x3D) ++#define REG_MCM_1F_L (REG_MCM_BASE + 0x3E) ++#define REG_MCM_1F_H (REG_MCM_BASE + 0x3F) ++ ++//-------------- ++#define REG_CHIPTOP_00_L (REG_CHIPTOP_BASE + 0x00) ++#define REG_CHIPTOP_00_H (REG_CHIPTOP_BASE + 0x01) ++#define REG_CHIPTOP_01_L (REG_CHIPTOP_BASE + 0x02) ++#define REG_CHIPTOP_01_H (REG_CHIPTOP_BASE + 0x03) ++#define REG_CHIPTOP_02_L (REG_CHIPTOP_BASE + 0x04) ++#define REG_CHIPTOP_02_H (REG_CHIPTOP_BASE + 0x05) ++#define REG_CHIPTOP_03_L (REG_CHIPTOP_BASE + 0x06) ++#define REG_CHIPTOP_03_H (REG_CHIPTOP_BASE + 0x07) ++#define REG_CHIPTOP_04_L (REG_CHIPTOP_BASE + 0x08) ++#define REG_CHIPTOP_04_H (REG_CHIPTOP_BASE + 0x09) ++#define REG_CHIPTOP_05_L (REG_CHIPTOP_BASE + 0x0A) ++#define REG_CHIPTOP_05_H (REG_CHIPTOP_BASE + 0x0B) ++#define REG_CHIPTOP_06_L (REG_CHIPTOP_BASE + 0x0C) ++#define REG_CHIPTOP_06_H (REG_CHIPTOP_BASE + 0x0D) ++#define REG_CHIPTOP_07_L (REG_CHIPTOP_BASE + 0x0E) ++#define REG_CHIPTOP_07_H (REG_CHIPTOP_BASE + 0x0F) ++#define REG_CHIPTOP_08_L (REG_CHIPTOP_BASE + 0x10) ++#define REG_CHIPTOP_08_H (REG_CHIPTOP_BASE + 0x11) ++#define REG_CHIPTOP_09_L (REG_CHIPTOP_BASE + 0x12) ++#define REG_CHIPTOP_09_H (REG_CHIPTOP_BASE + 0x13) ++#define REG_CHIPTOP_0A_L (REG_CHIPTOP_BASE + 0x14) ++#define REG_CHIPTOP_0A_H (REG_CHIPTOP_BASE + 0x15) ++#define REG_CHIPTOP_0B_L (REG_CHIPTOP_BASE + 0x16) ++#define REG_CHIPTOP_0B_H (REG_CHIPTOP_BASE + 0x17) ++#define REG_CHIPTOP_0C_L (REG_CHIPTOP_BASE + 0x18) ++#define REG_CHIPTOP_0C_H (REG_CHIPTOP_BASE + 0x19) ++#define REG_CHIPTOP_0D_L (REG_CHIPTOP_BASE + 0x1A) ++#define REG_CHIPTOP_0D_H (REG_CHIPTOP_BASE + 0x1B) ++#define REG_CHIPTOP_0E_L (REG_CHIPTOP_BASE + 0x1C) ++#define REG_CHIPTOP_0E_H (REG_CHIPTOP_BASE + 0x1D) ++#define REG_CHIPTOP_0F_L (REG_CHIPTOP_BASE + 0x1E) ++#define REG_CHIPTOP_0F_H (REG_CHIPTOP_BASE + 0x1F) ++#define REG_CHIPTOP_10_L (REG_CHIPTOP_BASE + 0x20) ++#define REG_CHIPTOP_10_H (REG_CHIPTOP_BASE + 0x21) ++#define REG_CHIPTOP_11_L (REG_CHIPTOP_BASE + 0x22) ++#define REG_CHIPTOP_11_H (REG_CHIPTOP_BASE + 0x23) ++#define REG_CHIPTOP_12_L (REG_CHIPTOP_BASE + 0x24) ++#define REG_CHIPTOP_12_H (REG_CHIPTOP_BASE + 0x25) ++#define REG_CHIPTOP_13_L (REG_CHIPTOP_BASE + 0x26) ++#define REG_CHIPTOP_13_H (REG_CHIPTOP_BASE + 0x27) ++#define REG_CHIPTOP_14_L (REG_CHIPTOP_BASE + 0x28) ++#define REG_CHIPTOP_14_H (REG_CHIPTOP_BASE + 0x29) ++#define REG_CHIPTOP_15_L (REG_CHIPTOP_BASE + 0x2A) ++#define REG_CHIPTOP_15_H (REG_CHIPTOP_BASE + 0x2B) ++#define REG_CHIPTOP_16_L (REG_CHIPTOP_BASE + 0x2C) ++#define REG_CHIPTOP_16_H (REG_CHIPTOP_BASE + 0x2D) ++#define REG_CHIPTOP_17_L (REG_CHIPTOP_BASE + 0x2E) ++#define REG_CHIPTOP_17_H (REG_CHIPTOP_BASE + 0x2F) ++#define REG_CHIPTOP_18_L (REG_CHIPTOP_BASE + 0x30) ++#define REG_CHIPTOP_18_H (REG_CHIPTOP_BASE + 0x31) ++#define REG_CHIPTOP_19_L (REG_CHIPTOP_BASE + 0x32) ++#define REG_CHIPTOP_19_H (REG_CHIPTOP_BASE + 0x33) ++#define REG_CHIPTOP_1A_L (REG_CHIPTOP_BASE + 0x34) ++#define REG_CHIPTOP_1A_H (REG_CHIPTOP_BASE + 0x35) ++#define REG_CHIPTOP_1B_L (REG_CHIPTOP_BASE + 0x36) ++#define REG_CHIPTOP_1B_H (REG_CHIPTOP_BASE + 0x37) ++#define REG_CHIPTOP_1C_L (REG_CHIPTOP_BASE + 0x38) ++#define REG_CHIPTOP_1C_H (REG_CHIPTOP_BASE + 0x39) ++#define REG_CHIPTOP_1D_L (REG_CHIPTOP_BASE + 0x3A) ++#define REG_CHIPTOP_1D_H (REG_CHIPTOP_BASE + 0x3B) ++#define REG_CHIPTOP_1E_L (REG_CHIPTOP_BASE + 0x3C) ++#define REG_CHIPTOP_1E_H (REG_CHIPTOP_BASE + 0x3D) ++#define REG_CHIPTOP_1F_L (REG_CHIPTOP_BASE + 0x3E) ++#define REG_CHIPTOP_1F_H (REG_CHIPTOP_BASE + 0x3F) ++#define REG_CHIPTOP_20_L (REG_CHIPTOP_BASE + 0x40) ++#define REG_CHIPTOP_20_H (REG_CHIPTOP_BASE + 0x41) ++#define REG_CHIPTOP_21_L (REG_CHIPTOP_BASE + 0x42) ++#define REG_CHIPTOP_21_H (REG_CHIPTOP_BASE + 0x43) ++#define REG_CHIPTOP_22_L (REG_CHIPTOP_BASE + 0x44) ++#define REG_CHIPTOP_22_H (REG_CHIPTOP_BASE + 0x45) ++#define REG_CHIPTOP_23_L (REG_CHIPTOP_BASE + 0x46) ++#define REG_CHIPTOP_23_H (REG_CHIPTOP_BASE + 0x47) ++#define REG_CHIPTOP_24_L (REG_CHIPTOP_BASE + 0x48) ++#define REG_CHIPTOP_24_H (REG_CHIPTOP_BASE + 0x49) ++#define REG_CHIPTOP_25_L (REG_CHIPTOP_BASE + 0x4A) ++#define REG_CHIPTOP_25_H (REG_CHIPTOP_BASE + 0x4B) ++#define REG_CHIPTOP_26_L (REG_CHIPTOP_BASE + 0x4C) ++#define REG_CHIPTOP_26_H (REG_CHIPTOP_BASE + 0x4D) ++#define REG_CHIPTOP_27_L (REG_CHIPTOP_BASE + 0x4E) ++#define REG_CHIPTOP_27_H (REG_CHIPTOP_BASE + 0x4F) ++#define REG_CHIPTOP_28_L (REG_CHIPTOP_BASE + 0x50) ++#define REG_CHIPTOP_28_H (REG_CHIPTOP_BASE + 0x51) ++#define REG_CHIPTOP_29_L (REG_CHIPTOP_BASE + 0x52) ++#define REG_CHIPTOP_29_H (REG_CHIPTOP_BASE + 0x53) ++#define REG_CHIPTOP_2A_L (REG_CHIPTOP_BASE + 0x54) ++#define REG_CHIPTOP_2A_H (REG_CHIPTOP_BASE + 0x55) ++#define REG_CHIPTOP_2B_L (REG_CHIPTOP_BASE + 0x56) ++#define REG_CHIPTOP_2B_H (REG_CHIPTOP_BASE + 0x57) ++#define REG_CHIPTOP_2C_L (REG_CHIPTOP_BASE + 0x58) ++#define REG_CHIPTOP_2C_H (REG_CHIPTOP_BASE + 0x59) ++#define REG_CHIPTOP_2D_L (REG_CHIPTOP_BASE + 0x5A) ++#define REG_CHIPTOP_2D_H (REG_CHIPTOP_BASE + 0x5B) ++#define REG_CHIPTOP_2E_L (REG_CHIPTOP_BASE + 0x5C) ++#define REG_CHIPTOP_2E_H (REG_CHIPTOP_BASE + 0x5D) ++#define REG_CHIPTOP_2F_L (REG_CHIPTOP_BASE + 0x5E) ++#define REG_CHIPTOP_2F_H (REG_CHIPTOP_BASE + 0x5F) ++#define REG_CHIPTOP_30_L (REG_CHIPTOP_BASE + 0x60) ++#define REG_CHIPTOP_30_H (REG_CHIPTOP_BASE + 0x61) ++#define REG_CHIPTOP_31_L (REG_CHIPTOP_BASE + 0x62) ++#define REG_CHIPTOP_31_H (REG_CHIPTOP_BASE + 0x63) ++#define REG_CHIPTOP_32_L (REG_CHIPTOP_BASE + 0x64) ++#define REG_CHIPTOP_32_H (REG_CHIPTOP_BASE + 0x65) ++#define REG_CHIPTOP_33_L (REG_CHIPTOP_BASE + 0x66) ++#define REG_CHIPTOP_33_H (REG_CHIPTOP_BASE + 0x67) ++#define REG_CHIPTOP_34_L (REG_CHIPTOP_BASE + 0x68) ++#define REG_CHIPTOP_34_H (REG_CHIPTOP_BASE + 0x69) ++#define REG_CHIPTOP_35_L (REG_CHIPTOP_BASE + 0x6A) ++#define REG_CHIPTOP_35_H (REG_CHIPTOP_BASE + 0x6B) ++#define REG_CHIPTOP_36_L (REG_CHIPTOP_BASE + 0x6C) ++#define REG_CHIPTOP_36_H (REG_CHIPTOP_BASE + 0x6D) ++#define REG_CHIPTOP_37_L (REG_CHIPTOP_BASE + 0x6E) ++#define REG_CHIPTOP_37_H (REG_CHIPTOP_BASE + 0x6F) ++#define REG_CHIPTOP_38_L (REG_CHIPTOP_BASE + 0x70) ++#define REG_CHIPTOP_38_H (REG_CHIPTOP_BASE + 0x71) ++#define REG_CHIPTOP_39_L (REG_CHIPTOP_BASE + 0x72) ++#define REG_CHIPTOP_39_H (REG_CHIPTOP_BASE + 0x73) ++#define REG_CHIPTOP_3A_L (REG_CHIPTOP_BASE + 0x74) ++#define REG_CHIPTOP_3A_H (REG_CHIPTOP_BASE + 0x75) ++#define REG_CHIPTOP_3B_L (REG_CHIPTOP_BASE + 0x76) ++#define REG_CHIPTOP_3B_H (REG_CHIPTOP_BASE + 0x77) ++#define REG_CHIPTOP_3C_L (REG_CHIPTOP_BASE + 0x78) ++#define REG_CHIPTOP_3C_H (REG_CHIPTOP_BASE + 0x79) ++#define REG_CHIPTOP_3D_L (REG_CHIPTOP_BASE + 0x7A) ++#define REG_CHIPTOP_3D_H (REG_CHIPTOP_BASE + 0x7B) ++#define REG_CHIPTOP_3E_L (REG_CHIPTOP_BASE + 0x7C) ++#define REG_CHIPTOP_3E_H (REG_CHIPTOP_BASE + 0x7D) ++#define REG_CHIPTOP_3F_L (REG_CHIPTOP_BASE + 0x7E) ++#define REG_CHIPTOP_3F_H (REG_CHIPTOP_BASE + 0x7F) ++#define REG_CHIPTOP_40_L (REG_CHIPTOP_BASE + 0x80) ++#define REG_CHIPTOP_40_H (REG_CHIPTOP_BASE + 0x81) ++#define REG_CHIPTOP_41_L (REG_CHIPTOP_BASE + 0x82) ++#define REG_CHIPTOP_41_H (REG_CHIPTOP_BASE + 0x83) ++#define REG_CHIPTOP_42_L (REG_CHIPTOP_BASE + 0x84) ++#define REG_CHIPTOP_42_H (REG_CHIPTOP_BASE + 0x85) ++#define REG_CHIPTOP_43_L (REG_CHIPTOP_BASE + 0x86) ++#define REG_CHIPTOP_43_H (REG_CHIPTOP_BASE + 0x87) ++#define REG_CHIPTOP_44_L (REG_CHIPTOP_BASE + 0x88) ++#define REG_CHIPTOP_44_H (REG_CHIPTOP_BASE + 0x89) ++#define REG_CHIPTOP_45_L (REG_CHIPTOP_BASE + 0x8A) ++#define REG_CHIPTOP_45_H (REG_CHIPTOP_BASE + 0x8B) ++#define REG_CHIPTOP_46_L (REG_CHIPTOP_BASE + 0x8C) ++#define REG_CHIPTOP_46_H (REG_CHIPTOP_BASE + 0x8D) ++#define REG_CHIPTOP_47_L (REG_CHIPTOP_BASE + 0x8E) ++#define REG_CHIPTOP_47_H (REG_CHIPTOP_BASE + 0x8F) ++#define REG_CHIPTOP_48_L (REG_CHIPTOP_BASE + 0x90) ++#define REG_CHIPTOP_48_H (REG_CHIPTOP_BASE + 0x91) ++#define REG_CHIPTOP_49_L (REG_CHIPTOP_BASE + 0x92) ++#define REG_CHIPTOP_49_H (REG_CHIPTOP_BASE + 0x93) ++#define REG_CHIPTOP_4A_L (REG_CHIPTOP_BASE + 0x94) ++#define REG_CHIPTOP_4A_H (REG_CHIPTOP_BASE + 0x95) ++#define REG_CHIPTOP_4B_L (REG_CHIPTOP_BASE + 0x96) ++#define REG_CHIPTOP_4B_H (REG_CHIPTOP_BASE + 0x97) ++#define REG_CHIPTOP_4C_L (REG_CHIPTOP_BASE + 0x98) ++#define REG_CHIPTOP_4C_H (REG_CHIPTOP_BASE + 0x99) ++#define REG_CHIPTOP_4D_L (REG_CHIPTOP_BASE + 0x9A) ++#define REG_CHIPTOP_4D_H (REG_CHIPTOP_BASE + 0x9B) ++#define REG_CHIPTOP_4E_L (REG_CHIPTOP_BASE + 0x9C) ++#define REG_CHIPTOP_4E_H (REG_CHIPTOP_BASE + 0x9D) ++#define REG_CHIPTOP_4F_L (REG_CHIPTOP_BASE + 0x9E) ++#define REG_CHIPTOP_4F_H (REG_CHIPTOP_BASE + 0x9F) ++#define REG_CHIPTOP_50_L (REG_CHIPTOP_BASE + 0xA0) ++#define REG_CHIPTOP_50_H (REG_CHIPTOP_BASE + 0xA1) ++#define REG_CHIPTOP_51_L (REG_CHIPTOP_BASE + 0xA2) ++#define REG_CHIPTOP_51_H (REG_CHIPTOP_BASE + 0xA3) ++#define REG_CHIPTOP_52_L (REG_CHIPTOP_BASE + 0xA4) ++#define REG_CHIPTOP_52_H (REG_CHIPTOP_BASE + 0xA5) ++#define REG_CHIPTOP_53_L (REG_CHIPTOP_BASE + 0xA6) ++#define REG_CHIPTOP_53_H (REG_CHIPTOP_BASE + 0xA7) ++#define REG_CHIPTOP_54_L (REG_CHIPTOP_BASE + 0xA8) ++#define REG_CHIPTOP_54_H (REG_CHIPTOP_BASE + 0xA9) ++#define REG_CHIPTOP_55_L (REG_CHIPTOP_BASE + 0xAA) ++#define REG_CHIPTOP_55_H (REG_CHIPTOP_BASE + 0xAB) ++#define REG_CHIPTOP_56_L (REG_CHIPTOP_BASE + 0xAC) ++#define REG_CHIPTOP_56_H (REG_CHIPTOP_BASE + 0xAD) ++#define REG_CHIPTOP_57_L (REG_CHIPTOP_BASE + 0xAE) ++#define REG_CHIPTOP_57_H (REG_CHIPTOP_BASE + 0xAF) ++#define REG_CHIPTOP_58_L (REG_CHIPTOP_BASE + 0xB0) ++#define REG_CHIPTOP_58_H (REG_CHIPTOP_BASE + 0xB1) ++#define REG_CHIPTOP_59_L (REG_CHIPTOP_BASE + 0xB2) ++#define REG_CHIPTOP_59_H (REG_CHIPTOP_BASE + 0xB3) ++#define REG_CHIPTOP_5A_L (REG_CHIPTOP_BASE + 0xB4) ++#define REG_CHIPTOP_5A_H (REG_CHIPTOP_BASE + 0xB5) ++#define REG_CHIPTOP_5B_L (REG_CHIPTOP_BASE + 0xB6) ++#define REG_CHIPTOP_5B_H (REG_CHIPTOP_BASE + 0xB7) ++#define REG_CHIPTOP_5C_L (REG_CHIPTOP_BASE + 0xB8) ++#define REG_CHIPTOP_5C_H (REG_CHIPTOP_BASE + 0xB9) ++#define REG_CHIPTOP_5D_L (REG_CHIPTOP_BASE + 0xBA) ++#define REG_CHIPTOP_5D_H (REG_CHIPTOP_BASE + 0xBB) ++#define REG_CHIPTOP_5E_L (REG_CHIPTOP_BASE + 0xBC) ++#define REG_CHIPTOP_5E_H (REG_CHIPTOP_BASE + 0xBD) ++#define REG_CHIPTOP_5F_L (REG_CHIPTOP_BASE + 0xBE) ++#define REG_CHIPTOP_5F_H (REG_CHIPTOP_BASE + 0xBF) ++#define REG_CHIPTOP_60_L (REG_CHIPTOP_BASE + 0xC0) ++#define REG_CHIPTOP_60_H (REG_CHIPTOP_BASE + 0xC1) ++#define REG_CHIPTOP_61_L (REG_CHIPTOP_BASE + 0xC2) ++#define REG_CHIPTOP_61_H (REG_CHIPTOP_BASE + 0xC3) ++#define REG_CHIPTOP_62_L (REG_CHIPTOP_BASE + 0xC4) ++#define REG_CHIPTOP_62_H (REG_CHIPTOP_BASE + 0xC5) ++#define REG_CHIPTOP_63_L (REG_CHIPTOP_BASE + 0xC6) ++#define REG_CHIPTOP_63_H (REG_CHIPTOP_BASE + 0xC7) ++#define REG_CHIPTOP_64_L (REG_CHIPTOP_BASE + 0xC8) ++#define REG_CHIPTOP_64_H (REG_CHIPTOP_BASE + 0xC9) ++#define REG_CHIPTOP_65_L (REG_CHIPTOP_BASE + 0xCA) ++#define REG_CHIPTOP_65_H (REG_CHIPTOP_BASE + 0xCB) ++#define REG_CHIPTOP_66_L (REG_CHIPTOP_BASE + 0xCC) ++#define REG_CHIPTOP_66_H (REG_CHIPTOP_BASE + 0xCD) ++#define REG_CHIPTOP_67_L (REG_CHIPTOP_BASE + 0xCE) ++#define REG_CHIPTOP_67_H (REG_CHIPTOP_BASE + 0xCF) ++#define REG_CHIPTOP_68_L (REG_CHIPTOP_BASE + 0xD0) ++#define REG_CHIPTOP_68_H (REG_CHIPTOP_BASE + 0xD1) ++#define REG_CHIPTOP_69_L (REG_CHIPTOP_BASE + 0xD2) ++#define REG_CHIPTOP_69_H (REG_CHIPTOP_BASE + 0xD3) ++#define REG_CHIPTOP_6A_L (REG_CHIPTOP_BASE + 0xD4) ++#define REG_CHIPTOP_6A_H (REG_CHIPTOP_BASE + 0xD5) ++#define REG_CHIPTOP_6B_L (REG_CHIPTOP_BASE + 0xD6) ++#define REG_CHIPTOP_6B_H (REG_CHIPTOP_BASE + 0xD7) ++#define REG_CHIPTOP_6C_L (REG_CHIPTOP_BASE + 0xD8) ++#define REG_CHIPTOP_6C_H (REG_CHIPTOP_BASE + 0xD9) ++#define REG_CHIPTOP_6D_L (REG_CHIPTOP_BASE + 0xDA) ++#define REG_CHIPTOP_6D_H (REG_CHIPTOP_BASE + 0xDB) ++#define REG_CHIPTOP_6E_L (REG_CHIPTOP_BASE + 0xDC) ++#define REG_CHIPTOP_6E_H (REG_CHIPTOP_BASE + 0xDD) ++#define REG_CHIPTOP_6F_L (REG_CHIPTOP_BASE + 0xDE) ++#define REG_CHIPTOP_6F_H (REG_CHIPTOP_BASE + 0xDF) ++#define REG_CHIPTOP_70_L (REG_CHIPTOP_BASE + 0xE0) ++#define REG_CHIPTOP_70_H (REG_CHIPTOP_BASE + 0xE1) ++#define REG_CHIPTOP_71_L (REG_CHIPTOP_BASE + 0xE2) ++#define REG_CHIPTOP_71_H (REG_CHIPTOP_BASE + 0xE3) ++#define REG_CHIPTOP_72_L (REG_CHIPTOP_BASE + 0xE4) ++#define REG_CHIPTOP_72_H (REG_CHIPTOP_BASE + 0xE5) ++#define REG_CHIPTOP_73_L (REG_CHIPTOP_BASE + 0xE6) ++#define REG_CHIPTOP_73_H (REG_CHIPTOP_BASE + 0xE7) ++#define REG_CHIPTOP_74_L (REG_CHIPTOP_BASE + 0xE8) ++#define REG_CHIPTOP_74_H (REG_CHIPTOP_BASE + 0xE9) ++#define REG_CHIPTOP_75_L (REG_CHIPTOP_BASE + 0xEA) ++#define REG_CHIPTOP_75_H (REG_CHIPTOP_BASE + 0xEB) ++#define REG_CHIPTOP_76_L (REG_CHIPTOP_BASE + 0xEC) ++#define REG_CHIPTOP_76_H (REG_CHIPTOP_BASE + 0xED) ++#define REG_CHIPTOP_77_L (REG_CHIPTOP_BASE + 0xEE) ++#define REG_CHIPTOP_77_H (REG_CHIPTOP_BASE + 0xEF) ++#define REG_CHIPTOP_78_L (REG_CHIPTOP_BASE + 0xF0) ++#define REG_CHIPTOP_78_H (REG_CHIPTOP_BASE + 0xF1) ++#define REG_CHIPTOP_79_L (REG_CHIPTOP_BASE + 0xF2) ++#define REG_CHIPTOP_79_H (REG_CHIPTOP_BASE + 0xF3) ++#define REG_CHIPTOP_7A_L (REG_CHIPTOP_BASE + 0xF4) ++#define REG_CHIPTOP_7A_H (REG_CHIPTOP_BASE + 0xF5) ++#define REG_CHIPTOP_7B_L (REG_CHIPTOP_BASE + 0xF6) ++#define REG_CHIPTOP_7B_H (REG_CHIPTOP_BASE + 0xF7) ++#define REG_CHIPTOP_7C_L (REG_CHIPTOP_BASE + 0xF8) ++#define REG_CHIPTOP_7C_H (REG_CHIPTOP_BASE + 0xF9) ++#define REG_CHIPTOP_7D_L (REG_CHIPTOP_BASE + 0xFA) ++#define REG_CHIPTOP_7D_H (REG_CHIPTOP_BASE + 0xFB) ++#define REG_CHIPTOP_7E_L (REG_CHIPTOP_BASE + 0xFC) ++#define REG_CHIPTOP_7E_H (REG_CHIPTOP_BASE + 0xFD) ++#define REG_CHIPTOP_7F_L (REG_CHIPTOP_BASE + 0xFE) ++#define REG_CHIPTOP_7F_H (REG_CHIPTOP_BASE + 0xFF) ++ ++ ++#define REG_SCL_CLK_00_L (REG_SCL_CLK_BASE + 0x00) ++#define REG_SCL_CLK_00_H (REG_SCL_CLK_BASE + 0x01) ++#define REG_SCL_CLK_01_L (REG_SCL_CLK_BASE + 0x02) ++#define REG_SCL_CLK_01_H (REG_SCL_CLK_BASE + 0x03) ++#define REG_SCL_CLK_02_L (REG_SCL_CLK_BASE + 0x04) ++#define REG_SCL_CLK_02_H (REG_SCL_CLK_BASE + 0x05) ++#define REG_SCL_CLK_03_L (REG_SCL_CLK_BASE + 0x06) ++#define REG_SCL_CLK_03_H (REG_SCL_CLK_BASE + 0x07) ++#define REG_SCL_CLK_04_L (REG_SCL_CLK_BASE + 0x08) ++#define REG_SCL_CLK_04_H (REG_SCL_CLK_BASE + 0x09) ++#define REG_SCL_CLK_05_L (REG_SCL_CLK_BASE + 0x0A) ++#define REG_SCL_CLK_05_H (REG_SCL_CLK_BASE + 0x0B) ++#define REG_SCL_CLK_06_L (REG_SCL_CLK_BASE + 0x0C) ++#define REG_SCL_CLK_06_H (REG_SCL_CLK_BASE + 0x0D) ++#define REG_SCL_CLK_07_L (REG_SCL_CLK_BASE + 0x0E) ++#define REG_SCL_CLK_07_H (REG_SCL_CLK_BASE + 0x0F) ++#define REG_SCL_CLK_08_L (REG_SCL_CLK_BASE + 0x10) ++#define REG_SCL_CLK_08_H (REG_SCL_CLK_BASE + 0x11) ++#define REG_SCL_CLK_09_L (REG_SCL_CLK_BASE + 0x12) ++#define REG_SCL_CLK_09_H (REG_SCL_CLK_BASE + 0x13) ++#define REG_SCL_CLK_0A_L (REG_SCL_CLK_BASE + 0x14) ++#define REG_SCL_CLK_0A_H (REG_SCL_CLK_BASE + 0x15) ++#define REG_SCL_CLK_0B_L (REG_SCL_CLK_BASE + 0x16) ++#define REG_SCL_CLK_0B_H (REG_SCL_CLK_BASE + 0x17) ++#define REG_SCL_CLK_0C_L (REG_SCL_CLK_BASE + 0x18) ++#define REG_SCL_CLK_0C_H (REG_SCL_CLK_BASE + 0x19) ++#define REG_SCL_CLK_0D_L (REG_SCL_CLK_BASE + 0x1A) ++#define REG_SCL_CLK_0D_H (REG_SCL_CLK_BASE + 0x1B) ++#define REG_SCL_CLK_0E_L (REG_SCL_CLK_BASE + 0x1C) ++#define REG_SCL_CLK_0E_H (REG_SCL_CLK_BASE + 0x1D) ++#define REG_SCL_CLK_0F_L (REG_SCL_CLK_BASE + 0x1E) ++#define REG_SCL_CLK_0F_H (REG_SCL_CLK_BASE + 0x1F) ++#define REG_SCL_CLK_10_L (REG_SCL_CLK_BASE + 0x20) ++#define REG_SCL_CLK_10_H (REG_SCL_CLK_BASE + 0x21) ++#define REG_SCL_CLK_11_L (REG_SCL_CLK_BASE + 0x22) ++#define REG_SCL_CLK_11_H (REG_SCL_CLK_BASE + 0x23) ++#define REG_SCL_CLK_12_L (REG_SCL_CLK_BASE + 0x24) ++#define REG_SCL_CLK_12_H (REG_SCL_CLK_BASE + 0x25) ++#define REG_SCL_CLK_13_L (REG_SCL_CLK_BASE + 0x26) ++#define REG_SCL_CLK_13_H (REG_SCL_CLK_BASE + 0x27) ++#define REG_SCL_CLK_14_L (REG_SCL_CLK_BASE + 0x28) ++#define REG_SCL_CLK_14_H (REG_SCL_CLK_BASE + 0x29) ++#define REG_SCL_CLK_15_L (REG_SCL_CLK_BASE + 0x2A) ++#define REG_SCL_CLK_15_H (REG_SCL_CLK_BASE + 0x2B) ++#define REG_SCL_CLK_16_L (REG_SCL_CLK_BASE + 0x2C) ++#define REG_SCL_CLK_16_H (REG_SCL_CLK_BASE + 0x2D) ++#define REG_SCL_CLK_17_L (REG_SCL_CLK_BASE + 0x2E) ++#define REG_SCL_CLK_17_H (REG_SCL_CLK_BASE + 0x2F) ++#define REG_SCL_CLK_18_L (REG_SCL_CLK_BASE + 0x30) ++#define REG_SCL_CLK_18_H (REG_SCL_CLK_BASE + 0x31) ++#define REG_SCL_CLK_19_L (REG_SCL_CLK_BASE + 0x32) ++#define REG_SCL_CLK_19_H (REG_SCL_CLK_BASE + 0x33) ++#define REG_SCL_CLK_1A_L (REG_SCL_CLK_BASE + 0x34) ++#define REG_SCL_CLK_1A_H (REG_SCL_CLK_BASE + 0x35) ++#define REG_SCL_CLK_1B_L (REG_SCL_CLK_BASE + 0x36) ++#define REG_SCL_CLK_1B_H (REG_SCL_CLK_BASE + 0x37) ++#define REG_SCL_CLK_1C_L (REG_SCL_CLK_BASE + 0x38) ++#define REG_SCL_CLK_1C_H (REG_SCL_CLK_BASE + 0x39) ++#define REG_SCL_CLK_1D_L (REG_SCL_CLK_BASE + 0x3A) ++#define REG_SCL_CLK_1D_H (REG_SCL_CLK_BASE + 0x3B) ++#define REG_SCL_CLK_1E_L (REG_SCL_CLK_BASE + 0x3C) ++#define REG_SCL_CLK_1E_H (REG_SCL_CLK_BASE + 0x3D) ++#define REG_SCL_CLK_1F_L (REG_SCL_CLK_BASE + 0x3E) ++#define REG_SCL_CLK_1F_H (REG_SCL_CLK_BASE + 0x3F) ++#define REG_SCL_CLK_20_L (REG_SCL_CLK_BASE + 0x40) ++#define REG_SCL_CLK_20_H (REG_SCL_CLK_BASE + 0x41) ++#define REG_SCL_CLK_21_L (REG_SCL_CLK_BASE + 0x42) ++#define REG_SCL_CLK_21_H (REG_SCL_CLK_BASE + 0x43) ++#define REG_SCL_CLK_22_L (REG_SCL_CLK_BASE + 0x44) ++#define REG_SCL_CLK_22_H (REG_SCL_CLK_BASE + 0x45) ++#define REG_SCL_CLK_23_L (REG_SCL_CLK_BASE + 0x46) ++#define REG_SCL_CLK_23_H (REG_SCL_CLK_BASE + 0x47) ++#define REG_SCL_CLK_24_L (REG_SCL_CLK_BASE + 0x48) ++#define REG_SCL_CLK_24_H (REG_SCL_CLK_BASE + 0x49) ++#define REG_SCL_CLK_25_L (REG_SCL_CLK_BASE + 0x4A) ++#define REG_SCL_CLK_25_H (REG_SCL_CLK_BASE + 0x4B) ++#define REG_SCL_CLK_26_L (REG_SCL_CLK_BASE + 0x4C) ++#define REG_SCL_CLK_26_H (REG_SCL_CLK_BASE + 0x4D) ++#define REG_SCL_CLK_27_L (REG_SCL_CLK_BASE + 0x4E) ++#define REG_SCL_CLK_27_H (REG_SCL_CLK_BASE + 0x4F) ++#define REG_SCL_CLK_28_L (REG_SCL_CLK_BASE + 0x50) ++#define REG_SCL_CLK_28_H (REG_SCL_CLK_BASE + 0x51) ++#define REG_SCL_CLK_29_L (REG_SCL_CLK_BASE + 0x52) ++#define REG_SCL_CLK_29_H (REG_SCL_CLK_BASE + 0x53) ++#define REG_SCL_CLK_2A_L (REG_SCL_CLK_BASE + 0x54) ++#define REG_SCL_CLK_2A_H (REG_SCL_CLK_BASE + 0x55) ++#define REG_SCL_CLK_2B_L (REG_SCL_CLK_BASE + 0x56) ++#define REG_SCL_CLK_2B_H (REG_SCL_CLK_BASE + 0x57) ++#define REG_SCL_CLK_2C_L (REG_SCL_CLK_BASE + 0x58) ++#define REG_SCL_CLK_2C_H (REG_SCL_CLK_BASE + 0x59) ++#define REG_SCL_CLK_2D_L (REG_SCL_CLK_BASE + 0x5A) ++#define REG_SCL_CLK_2D_H (REG_SCL_CLK_BASE + 0x5B) ++#define REG_SCL_CLK_2E_L (REG_SCL_CLK_BASE + 0x5C) ++#define REG_SCL_CLK_2E_H (REG_SCL_CLK_BASE + 0x5D) ++#define REG_SCL_CLK_2F_L (REG_SCL_CLK_BASE + 0x5E) ++#define REG_SCL_CLK_2F_H (REG_SCL_CLK_BASE + 0x5F) ++#define REG_SCL_CLK_30_L (REG_SCL_CLK_BASE + 0x60) ++#define REG_SCL_CLK_30_H (REG_SCL_CLK_BASE + 0x61) ++#define REG_SCL_CLK_31_L (REG_SCL_CLK_BASE + 0x62) ++#define REG_SCL_CLK_31_H (REG_SCL_CLK_BASE + 0x63) ++#define REG_SCL_CLK_32_L (REG_SCL_CLK_BASE + 0x64) ++#define REG_SCL_CLK_32_H (REG_SCL_CLK_BASE + 0x65) ++#define REG_SCL_CLK_33_L (REG_SCL_CLK_BASE + 0x66) ++#define REG_SCL_CLK_33_H (REG_SCL_CLK_BASE + 0x67) ++#define REG_SCL_CLK_34_L (REG_SCL_CLK_BASE + 0x68) ++#define REG_SCL_CLK_34_H (REG_SCL_CLK_BASE + 0x69) ++#define REG_SCL_CLK_35_L (REG_SCL_CLK_BASE + 0x6A) ++#define REG_SCL_CLK_35_H (REG_SCL_CLK_BASE + 0x6B) ++#define REG_SCL_CLK_36_L (REG_SCL_CLK_BASE + 0x6C) ++#define REG_SCL_CLK_36_H (REG_SCL_CLK_BASE + 0x6D) ++#define REG_SCL_CLK_37_L (REG_SCL_CLK_BASE + 0x6E) ++#define REG_SCL_CLK_37_H (REG_SCL_CLK_BASE + 0x6F) ++#define REG_SCL_CLK_38_L (REG_SCL_CLK_BASE + 0x70) ++#define REG_SCL_CLK_38_H (REG_SCL_CLK_BASE + 0x71) ++#define REG_SCL_CLK_39_L (REG_SCL_CLK_BASE + 0x72) ++#define REG_SCL_CLK_39_H (REG_SCL_CLK_BASE + 0x73) ++#define REG_SCL_CLK_3A_L (REG_SCL_CLK_BASE + 0x74) ++#define REG_SCL_CLK_3A_H (REG_SCL_CLK_BASE + 0x75) ++#define REG_SCL_CLK_3B_L (REG_SCL_CLK_BASE + 0x76) ++#define REG_SCL_CLK_3B_H (REG_SCL_CLK_BASE + 0x77) ++#define REG_SCL_CLK_3C_L (REG_SCL_CLK_BASE + 0x78) ++#define REG_SCL_CLK_3C_H (REG_SCL_CLK_BASE + 0x79) ++#define REG_SCL_CLK_3D_L (REG_SCL_CLK_BASE + 0x7A) ++#define REG_SCL_CLK_3D_H (REG_SCL_CLK_BASE + 0x7B) ++#define REG_SCL_CLK_3E_L (REG_SCL_CLK_BASE + 0x7C) ++#define REG_SCL_CLK_3E_H (REG_SCL_CLK_BASE + 0x7D) ++#define REG_SCL_CLK_3F_L (REG_SCL_CLK_BASE + 0x7E) ++#define REG_SCL_CLK_3F_H (REG_SCL_CLK_BASE + 0x7F) ++#define REG_SCL_CLK_40_L (REG_SCL_CLK_BASE + 0x80) ++#define REG_SCL_CLK_40_H (REG_SCL_CLK_BASE + 0x81) ++#define REG_SCL_CLK_41_L (REG_SCL_CLK_BASE + 0x82) ++#define REG_SCL_CLK_41_H (REG_SCL_CLK_BASE + 0x83) ++#define REG_SCL_CLK_42_L (REG_SCL_CLK_BASE + 0x84) ++#define REG_SCL_CLK_42_H (REG_SCL_CLK_BASE + 0x85) ++#define REG_SCL_CLK_43_L (REG_SCL_CLK_BASE + 0x86) ++#define REG_SCL_CLK_43_H (REG_SCL_CLK_BASE + 0x87) ++#define REG_SCL_CLK_44_L (REG_SCL_CLK_BASE + 0x88) ++#define REG_SCL_CLK_44_H (REG_SCL_CLK_BASE + 0x89) ++#define REG_SCL_CLK_45_L (REG_SCL_CLK_BASE + 0x8A) ++#define REG_SCL_CLK_45_H (REG_SCL_CLK_BASE + 0x8B) ++#define REG_SCL_CLK_46_L (REG_SCL_CLK_BASE + 0x8C) ++#define REG_SCL_CLK_46_H (REG_SCL_CLK_BASE + 0x8D) ++#define REG_SCL_CLK_47_L (REG_SCL_CLK_BASE + 0x8E) ++#define REG_SCL_CLK_47_H (REG_SCL_CLK_BASE + 0x8F) ++#define REG_SCL_CLK_48_L (REG_SCL_CLK_BASE + 0x90) ++#define REG_SCL_CLK_48_H (REG_SCL_CLK_BASE + 0x91) ++#define REG_SCL_CLK_49_L (REG_SCL_CLK_BASE + 0x92) ++#define REG_SCL_CLK_49_H (REG_SCL_CLK_BASE + 0x93) ++#define REG_SCL_CLK_4A_L (REG_SCL_CLK_BASE + 0x94) ++#define REG_SCL_CLK_4A_H (REG_SCL_CLK_BASE + 0x95) ++#define REG_SCL_CLK_4B_L (REG_SCL_CLK_BASE + 0x96) ++#define REG_SCL_CLK_4B_H (REG_SCL_CLK_BASE + 0x97) ++#define REG_SCL_CLK_4C_L (REG_SCL_CLK_BASE + 0x98) ++#define REG_SCL_CLK_4C_H (REG_SCL_CLK_BASE + 0x99) ++#define REG_SCL_CLK_4D_L (REG_SCL_CLK_BASE + 0x9A) ++#define REG_SCL_CLK_4D_H (REG_SCL_CLK_BASE + 0x9B) ++#define REG_SCL_CLK_4E_L (REG_SCL_CLK_BASE + 0x9C) ++#define REG_SCL_CLK_4E_H (REG_SCL_CLK_BASE + 0x9D) ++#define REG_SCL_CLK_4F_L (REG_SCL_CLK_BASE + 0x9E) ++#define REG_SCL_CLK_4F_H (REG_SCL_CLK_BASE + 0x9F) ++#define REG_SCL_CLK_50_L (REG_SCL_CLK_BASE + 0xA0) ++#define REG_SCL_CLK_50_H (REG_SCL_CLK_BASE + 0xA1) ++#define REG_SCL_CLK_51_L (REG_SCL_CLK_BASE + 0xA2) ++#define REG_SCL_CLK_51_H (REG_SCL_CLK_BASE + 0xA3) ++#define REG_SCL_CLK_52_L (REG_SCL_CLK_BASE + 0xA4) ++#define REG_SCL_CLK_52_H (REG_SCL_CLK_BASE + 0xA5) ++#define REG_SCL_CLK_53_L (REG_SCL_CLK_BASE + 0xA6) ++#define REG_SCL_CLK_53_H (REG_SCL_CLK_BASE + 0xA7) ++#define REG_SCL_CLK_54_L (REG_SCL_CLK_BASE + 0xA8) ++#define REG_SCL_CLK_54_H (REG_SCL_CLK_BASE + 0xA9) ++#define REG_SCL_CLK_55_L (REG_SCL_CLK_BASE + 0xAA) ++#define REG_SCL_CLK_55_H (REG_SCL_CLK_BASE + 0xAB) ++#define REG_SCL_CLK_56_L (REG_SCL_CLK_BASE + 0xAC) ++#define REG_SCL_CLK_56_H (REG_SCL_CLK_BASE + 0xAD) ++#define REG_SCL_CLK_57_L (REG_SCL_CLK_BASE + 0xAE) ++#define REG_SCL_CLK_57_H (REG_SCL_CLK_BASE + 0xAF) ++#define REG_SCL_CLK_58_L (REG_SCL_CLK_BASE + 0xB0) ++#define REG_SCL_CLK_58_H (REG_SCL_CLK_BASE + 0xB1) ++#define REG_SCL_CLK_59_L (REG_SCL_CLK_BASE + 0xB2) ++#define REG_SCL_CLK_59_H (REG_SCL_CLK_BASE + 0xB3) ++#define REG_SCL_CLK_5A_L (REG_SCL_CLK_BASE + 0xB4) ++#define REG_SCL_CLK_5A_H (REG_SCL_CLK_BASE + 0xB5) ++#define REG_SCL_CLK_5B_L (REG_SCL_CLK_BASE + 0xB6) ++#define REG_SCL_CLK_5B_H (REG_SCL_CLK_BASE + 0xB7) ++#define REG_SCL_CLK_5C_L (REG_SCL_CLK_BASE + 0xB8) ++#define REG_SCL_CLK_5C_H (REG_SCL_CLK_BASE + 0xB9) ++#define REG_SCL_CLK_5D_L (REG_SCL_CLK_BASE + 0xBA) ++#define REG_SCL_CLK_5D_H (REG_SCL_CLK_BASE + 0xBB) ++#define REG_SCL_CLK_5E_L (REG_SCL_CLK_BASE + 0xBC) ++#define REG_SCL_CLK_5E_H (REG_SCL_CLK_BASE + 0xBD) ++#define REG_SCL_CLK_5F_L (REG_SCL_CLK_BASE + 0xBE) ++#define REG_SCL_CLK_5F_H (REG_SCL_CLK_BASE + 0xBF) ++#define REG_SCL_CLK_60_L (REG_SCL_CLK_BASE + 0xC0) ++#define REG_SCL_CLK_60_H (REG_SCL_CLK_BASE + 0xC1) ++#define REG_SCL_CLK_61_L (REG_SCL_CLK_BASE + 0xC2) ++#define REG_SCL_CLK_61_H (REG_SCL_CLK_BASE + 0xC3) ++#define REG_SCL_CLK_62_L (REG_SCL_CLK_BASE + 0xC4) ++#define REG_SCL_CLK_62_H (REG_SCL_CLK_BASE + 0xC5) ++#define REG_SCL_CLK_63_L (REG_SCL_CLK_BASE + 0xC6) ++#define REG_SCL_CLK_63_H (REG_SCL_CLK_BASE + 0xC7) ++#define REG_SCL_CLK_64_L (REG_SCL_CLK_BASE + 0xC8) ++#define REG_SCL_CLK_64_H (REG_SCL_CLK_BASE + 0xC9) ++#define REG_SCL_CLK_65_L (REG_SCL_CLK_BASE + 0xCA) ++#define REG_SCL_CLK_65_H (REG_SCL_CLK_BASE + 0xCB) ++#define REG_SCL_CLK_66_L (REG_SCL_CLK_BASE + 0xCC) ++#define REG_SCL_CLK_66_H (REG_SCL_CLK_BASE + 0xCD) ++#define REG_SCL_CLK_67_L (REG_SCL_CLK_BASE + 0xCE) ++#define REG_SCL_CLK_67_H (REG_SCL_CLK_BASE + 0xCF) ++#define REG_SCL_CLK_68_L (REG_SCL_CLK_BASE + 0xD0) ++#define REG_SCL_CLK_68_H (REG_SCL_CLK_BASE + 0xD1) ++#define REG_SCL_CLK_69_L (REG_SCL_CLK_BASE + 0xD2) ++#define REG_SCL_CLK_69_H (REG_SCL_CLK_BASE + 0xD3) ++#define REG_SCL_CLK_6A_L (REG_SCL_CLK_BASE + 0xD4) ++#define REG_SCL_CLK_6A_H (REG_SCL_CLK_BASE + 0xD5) ++#define REG_SCL_CLK_6B_L (REG_SCL_CLK_BASE + 0xD6) ++#define REG_SCL_CLK_6B_H (REG_SCL_CLK_BASE + 0xD7) ++#define REG_SCL_CLK_6C_L (REG_SCL_CLK_BASE + 0xD8) ++#define REG_SCL_CLK_6C_H (REG_SCL_CLK_BASE + 0xD9) ++#define REG_SCL_CLK_6D_L (REG_SCL_CLK_BASE + 0xDA) ++#define REG_SCL_CLK_6D_H (REG_SCL_CLK_BASE + 0xDB) ++#define REG_SCL_CLK_6E_L (REG_SCL_CLK_BASE + 0xDC) ++#define REG_SCL_CLK_6E_H (REG_SCL_CLK_BASE + 0xDD) ++#define REG_SCL_CLK_6F_L (REG_SCL_CLK_BASE + 0xDE) ++#define REG_SCL_CLK_6F_H (REG_SCL_CLK_BASE + 0xDF) ++#define REG_SCL_CLK_70_L (REG_SCL_CLK_BASE + 0xE0) ++#define REG_SCL_CLK_70_H (REG_SCL_CLK_BASE + 0xE1) ++#define REG_SCL_CLK_71_L (REG_SCL_CLK_BASE + 0xE2) ++#define REG_SCL_CLK_71_H (REG_SCL_CLK_BASE + 0xE3) ++#define REG_SCL_CLK_72_L (REG_SCL_CLK_BASE + 0xE4) ++#define REG_SCL_CLK_72_H (REG_SCL_CLK_BASE + 0xE5) ++#define REG_SCL_CLK_73_L (REG_SCL_CLK_BASE + 0xE6) ++#define REG_SCL_CLK_73_H (REG_SCL_CLK_BASE + 0xE7) ++#define REG_SCL_CLK_74_L (REG_SCL_CLK_BASE + 0xE8) ++#define REG_SCL_CLK_74_H (REG_SCL_CLK_BASE + 0xE9) ++#define REG_SCL_CLK_75_L (REG_SCL_CLK_BASE + 0xEA) ++#define REG_SCL_CLK_75_H (REG_SCL_CLK_BASE + 0xEB) ++#define REG_SCL_CLK_76_L (REG_SCL_CLK_BASE + 0xEC) ++#define REG_SCL_CLK_76_H (REG_SCL_CLK_BASE + 0xED) ++#define REG_SCL_CLK_77_L (REG_SCL_CLK_BASE + 0xEE) ++#define REG_SCL_CLK_77_H (REG_SCL_CLK_BASE + 0xEF) ++#define REG_SCL_CLK_78_L (REG_SCL_CLK_BASE + 0xF0) ++#define REG_SCL_CLK_78_H (REG_SCL_CLK_BASE + 0xF1) ++#define REG_SCL_CLK_79_L (REG_SCL_CLK_BASE + 0xF2) ++#define REG_SCL_CLK_79_H (REG_SCL_CLK_BASE + 0xF3) ++#define REG_SCL_CLK_7A_L (REG_SCL_CLK_BASE + 0xF4) ++#define REG_SCL_CLK_7A_H (REG_SCL_CLK_BASE + 0xF5) ++#define REG_SCL_CLK_7B_L (REG_SCL_CLK_BASE + 0xF6) ++#define REG_SCL_CLK_7B_H (REG_SCL_CLK_BASE + 0xF7) ++#define REG_SCL_CLK_7C_L (REG_SCL_CLK_BASE + 0xF8) ++#define REG_SCL_CLK_7C_H (REG_SCL_CLK_BASE + 0xF9) ++#define REG_SCL_CLK_7D_L (REG_SCL_CLK_BASE + 0xFA) ++#define REG_SCL_CLK_7D_H (REG_SCL_CLK_BASE + 0xFB) ++#define REG_SCL_CLK_7E_L (REG_SCL_CLK_BASE + 0xFC) ++#define REG_SCL_CLK_7E_H (REG_SCL_CLK_BASE + 0xFD) ++#define REG_SCL_CLK_7F_L (REG_SCL_CLK_BASE + 0xFE) ++#define REG_SCL_CLK_7F_H (REG_SCL_CLK_BASE + 0xFF) ++ ++#define REG_BLOCK_24_L (REG_BLOCK_BASE + 0x48) ++#define REG_BLOCK_24_H (REG_BLOCK_BASE + 0x49) ++ ++#define REG_SCL_LPLL_00_L (REG_SCL_LPLL_BASE + 0x00) ++#define REG_SCL_LPLL_00_H (REG_SCL_LPLL_BASE + 0x01) ++#define REG_SCL_LPLL_01_L (REG_SCL_LPLL_BASE + 0x02) ++#define REG_SCL_LPLL_01_H (REG_SCL_LPLL_BASE + 0x03) ++#define REG_SCL_LPLL_02_L (REG_SCL_LPLL_BASE + 0x04) ++#define REG_SCL_LPLL_02_H (REG_SCL_LPLL_BASE + 0x05) ++#define REG_SCL_LPLL_03_L (REG_SCL_LPLL_BASE + 0x06) ++#define REG_SCL_LPLL_03_H (REG_SCL_LPLL_BASE + 0x07) ++#define REG_SCL_LPLL_04_L (REG_SCL_LPLL_BASE + 0x08) ++#define REG_SCL_LPLL_04_H (REG_SCL_LPLL_BASE + 0x09) ++#define REG_SCL_LPLL_05_L (REG_SCL_LPLL_BASE + 0x0A) ++#define REG_SCL_LPLL_05_H (REG_SCL_LPLL_BASE + 0x0B) ++#define REG_SCL_LPLL_06_L (REG_SCL_LPLL_BASE + 0x0C) ++#define REG_SCL_LPLL_06_H (REG_SCL_LPLL_BASE + 0x0D) ++#define REG_SCL_LPLL_07_L (REG_SCL_LPLL_BASE + 0x0E) ++#define REG_SCL_LPLL_07_H (REG_SCL_LPLL_BASE + 0x0F) ++#define REG_SCL_LPLL_08_L (REG_SCL_LPLL_BASE + 0x10) ++#define REG_SCL_LPLL_08_H (REG_SCL_LPLL_BASE + 0x11) ++#define REG_SCL_LPLL_09_L (REG_SCL_LPLL_BASE + 0x12) ++#define REG_SCL_LPLL_09_H (REG_SCL_LPLL_BASE + 0x13) ++#define REG_SCL_LPLL_0A_L (REG_SCL_LPLL_BASE + 0x14) ++#define REG_SCL_LPLL_0A_H (REG_SCL_LPLL_BASE + 0x15) ++#define REG_SCL_LPLL_0B_L (REG_SCL_LPLL_BASE + 0x16) ++#define REG_SCL_LPLL_0B_H (REG_SCL_LPLL_BASE + 0x17) ++#define REG_SCL_LPLL_0C_L (REG_SCL_LPLL_BASE + 0x18) ++#define REG_SCL_LPLL_0C_H (REG_SCL_LPLL_BASE + 0x19) ++#define REG_SCL_LPLL_0D_L (REG_SCL_LPLL_BASE + 0x1A) ++#define REG_SCL_LPLL_0D_H (REG_SCL_LPLL_BASE + 0x1B) ++#define REG_SCL_LPLL_0E_L (REG_SCL_LPLL_BASE + 0x1C) ++#define REG_SCL_LPLL_0E_H (REG_SCL_LPLL_BASE + 0x1D) ++#define REG_SCL_LPLL_0F_L (REG_SCL_LPLL_BASE + 0x1E) ++#define REG_SCL_LPLL_0F_H (REG_SCL_LPLL_BASE + 0x1F) ++#define REG_SCL_LPLL_10_L (REG_SCL_LPLL_BASE + 0x20) ++#define REG_SCL_LPLL_10_H (REG_SCL_LPLL_BASE + 0x21) ++#define REG_SCL_LPLL_11_L (REG_SCL_LPLL_BASE + 0x22) ++#define REG_SCL_LPLL_11_H (REG_SCL_LPLL_BASE + 0x23) ++#define REG_SCL_LPLL_12_L (REG_SCL_LPLL_BASE + 0x24) ++#define REG_SCL_LPLL_12_H (REG_SCL_LPLL_BASE + 0x25) ++#define REG_SCL_LPLL_13_L (REG_SCL_LPLL_BASE + 0x26) ++#define REG_SCL_LPLL_13_H (REG_SCL_LPLL_BASE + 0x27) ++#define REG_SCL_LPLL_14_L (REG_SCL_LPLL_BASE + 0x28) ++#define REG_SCL_LPLL_14_H (REG_SCL_LPLL_BASE + 0x29) ++#define REG_SCL_LPLL_15_L (REG_SCL_LPLL_BASE + 0x2A) ++#define REG_SCL_LPLL_15_H (REG_SCL_LPLL_BASE + 0x2B) ++#define REG_SCL_LPLL_16_L (REG_SCL_LPLL_BASE + 0x2C) ++#define REG_SCL_LPLL_16_H (REG_SCL_LPLL_BASE + 0x2D) ++#define REG_SCL_LPLL_17_L (REG_SCL_LPLL_BASE + 0x2E) ++#define REG_SCL_LPLL_17_H (REG_SCL_LPLL_BASE + 0x2F) ++#define REG_SCL_LPLL_18_L (REG_SCL_LPLL_BASE + 0x30) ++#define REG_SCL_LPLL_18_H (REG_SCL_LPLL_BASE + 0x31) ++#define REG_SCL_LPLL_19_L (REG_SCL_LPLL_BASE + 0x32) ++#define REG_SCL_LPLL_19_H (REG_SCL_LPLL_BASE + 0x33) ++#define REG_SCL_LPLL_1A_L (REG_SCL_LPLL_BASE + 0x34) ++#define REG_SCL_LPLL_1A_H (REG_SCL_LPLL_BASE + 0x35) ++#define REG_SCL_LPLL_1B_L (REG_SCL_LPLL_BASE + 0x36) ++#define REG_SCL_LPLL_1B_H (REG_SCL_LPLL_BASE + 0x37) ++#define REG_SCL_LPLL_1C_L (REG_SCL_LPLL_BASE + 0x38) ++#define REG_SCL_LPLL_1C_H (REG_SCL_LPLL_BASE + 0x39) ++#define REG_SCL_LPLL_1D_L (REG_SCL_LPLL_BASE + 0x3A) ++#define REG_SCL_LPLL_1D_H (REG_SCL_LPLL_BASE + 0x3B) ++#define REG_SCL_LPLL_1E_L (REG_SCL_LPLL_BASE + 0x3C) ++#define REG_SCL_LPLL_1E_H (REG_SCL_LPLL_BASE + 0x3D) ++#define REG_SCL_LPLL_1F_L (REG_SCL_LPLL_BASE + 0x3E) ++#define REG_SCL_LPLL_1F_H (REG_SCL_LPLL_BASE + 0x3F) ++#define REG_SCL_LPLL_20_L (REG_SCL_LPLL_BASE + 0x40) ++#define REG_SCL_LPLL_20_H (REG_SCL_LPLL_BASE + 0x41) ++#define REG_SCL_LPLL_21_L (REG_SCL_LPLL_BASE + 0x42) ++#define REG_SCL_LPLL_21_H (REG_SCL_LPLL_BASE + 0x43) ++#define REG_SCL_LPLL_22_L (REG_SCL_LPLL_BASE + 0x44) ++#define REG_SCL_LPLL_22_H (REG_SCL_LPLL_BASE + 0x45) ++#define REG_SCL_LPLL_23_L (REG_SCL_LPLL_BASE + 0x46) ++#define REG_SCL_LPLL_23_H (REG_SCL_LPLL_BASE + 0x47) ++#define REG_SCL_LPLL_24_L (REG_SCL_LPLL_BASE + 0x48) ++#define REG_SCL_LPLL_24_H (REG_SCL_LPLL_BASE + 0x49) ++#define REG_SCL_LPLL_25_L (REG_SCL_LPLL_BASE + 0x4A) ++#define REG_SCL_LPLL_25_H (REG_SCL_LPLL_BASE + 0x4B) ++#define REG_SCL_LPLL_26_L (REG_SCL_LPLL_BASE + 0x4C) ++#define REG_SCL_LPLL_26_H (REG_SCL_LPLL_BASE + 0x4D) ++#define REG_SCL_LPLL_27_L (REG_SCL_LPLL_BASE + 0x4E) ++#define REG_SCL_LPLL_27_H (REG_SCL_LPLL_BASE + 0x4F) ++#define REG_SCL_LPLL_28_L (REG_SCL_LPLL_BASE + 0x50) ++#define REG_SCL_LPLL_28_H (REG_SCL_LPLL_BASE + 0x51) ++#define REG_SCL_LPLL_29_L (REG_SCL_LPLL_BASE + 0x52) ++#define REG_SCL_LPLL_29_H (REG_SCL_LPLL_BASE + 0x53) ++#define REG_SCL_LPLL_2A_L (REG_SCL_LPLL_BASE + 0x54) ++#define REG_SCL_LPLL_2A_H (REG_SCL_LPLL_BASE + 0x55) ++#define REG_SCL_LPLL_2B_L (REG_SCL_LPLL_BASE + 0x56) ++#define REG_SCL_LPLL_2B_H (REG_SCL_LPLL_BASE + 0x57) ++#define REG_SCL_LPLL_2C_L (REG_SCL_LPLL_BASE + 0x58) ++#define REG_SCL_LPLL_2C_H (REG_SCL_LPLL_BASE + 0x59) ++#define REG_SCL_LPLL_2D_L (REG_SCL_LPLL_BASE + 0x5A) ++#define REG_SCL_LPLL_2D_H (REG_SCL_LPLL_BASE + 0x5B) ++#define REG_SCL_LPLL_2E_L (REG_SCL_LPLL_BASE + 0x5C) ++#define REG_SCL_LPLL_2E_H (REG_SCL_LPLL_BASE + 0x5D) ++#define REG_SCL_LPLL_2F_L (REG_SCL_LPLL_BASE + 0x5E) ++#define REG_SCL_LPLL_2F_H (REG_SCL_LPLL_BASE + 0x5F) ++#define REG_SCL_LPLL_30_L (REG_SCL_LPLL_BASE + 0x60) ++#define REG_SCL_LPLL_30_H (REG_SCL_LPLL_BASE + 0x61) ++#define REG_SCL_LPLL_31_L (REG_SCL_LPLL_BASE + 0x62) ++#define REG_SCL_LPLL_31_H (REG_SCL_LPLL_BASE + 0x63) ++#define REG_SCL_LPLL_32_L (REG_SCL_LPLL_BASE + 0x64) ++#define REG_SCL_LPLL_32_H (REG_SCL_LPLL_BASE + 0x65) ++#define REG_SCL_LPLL_33_L (REG_SCL_LPLL_BASE + 0x66) ++#define REG_SCL_LPLL_33_H (REG_SCL_LPLL_BASE + 0x67) ++#define REG_SCL_LPLL_34_L (REG_SCL_LPLL_BASE + 0x68) ++#define REG_SCL_LPLL_34_H (REG_SCL_LPLL_BASE + 0x69) ++#define REG_SCL_LPLL_35_L (REG_SCL_LPLL_BASE + 0x6A) ++#define REG_SCL_LPLL_35_H (REG_SCL_LPLL_BASE + 0x6B) ++#define REG_SCL_LPLL_36_L (REG_SCL_LPLL_BASE + 0x6C) ++#define REG_SCL_LPLL_36_H (REG_SCL_LPLL_BASE + 0x6D) ++#define REG_SCL_LPLL_37_L (REG_SCL_LPLL_BASE + 0x6E) ++#define REG_SCL_LPLL_37_H (REG_SCL_LPLL_BASE + 0x6F) ++#define REG_SCL_LPLL_38_L (REG_SCL_LPLL_BASE + 0x70) ++#define REG_SCL_LPLL_38_H (REG_SCL_LPLL_BASE + 0x71) ++#define REG_SCL_LPLL_39_L (REG_SCL_LPLL_BASE + 0x72) ++#define REG_SCL_LPLL_39_H (REG_SCL_LPLL_BASE + 0x73) ++#define REG_SCL_LPLL_3A_L (REG_SCL_LPLL_BASE + 0x74) ++#define REG_SCL_LPLL_3A_H (REG_SCL_LPLL_BASE + 0x75) ++#define REG_SCL_LPLL_3B_L (REG_SCL_LPLL_BASE + 0x76) ++#define REG_SCL_LPLL_3B_H (REG_SCL_LPLL_BASE + 0x77) ++#define REG_SCL_LPLL_3C_L (REG_SCL_LPLL_BASE + 0x78) ++#define REG_SCL_LPLL_3C_H (REG_SCL_LPLL_BASE + 0x79) ++#define REG_SCL_LPLL_3D_L (REG_SCL_LPLL_BASE + 0x7A) ++#define REG_SCL_LPLL_3D_H (REG_SCL_LPLL_BASE + 0x7B) ++#define REG_SCL_LPLL_3E_L (REG_SCL_LPLL_BASE + 0x7C) ++#define REG_SCL_LPLL_3E_H (REG_SCL_LPLL_BASE + 0x7D) ++#define REG_SCL_LPLL_3F_L (REG_SCL_LPLL_BASE + 0x7E) ++#define REG_SCL_LPLL_3F_H (REG_SCL_LPLL_BASE + 0x7F) ++#define REG_SCL_LPLL_40_L (REG_SCL_LPLL_BASE + 0x80) ++#define REG_SCL_LPLL_40_H (REG_SCL_LPLL_BASE + 0x81) ++#define REG_SCL_LPLL_41_L (REG_SCL_LPLL_BASE + 0x82) ++#define REG_SCL_LPLL_41_H (REG_SCL_LPLL_BASE + 0x83) ++#define REG_SCL_LPLL_42_L (REG_SCL_LPLL_BASE + 0x84) ++#define REG_SCL_LPLL_42_H (REG_SCL_LPLL_BASE + 0x85) ++#define REG_SCL_LPLL_43_L (REG_SCL_LPLL_BASE + 0x86) ++#define REG_SCL_LPLL_43_H (REG_SCL_LPLL_BASE + 0x87) ++#define REG_SCL_LPLL_44_L (REG_SCL_LPLL_BASE + 0x88) ++#define REG_SCL_LPLL_44_H (REG_SCL_LPLL_BASE + 0x89) ++#define REG_SCL_LPLL_45_L (REG_SCL_LPLL_BASE + 0x8A) ++#define REG_SCL_LPLL_45_H (REG_SCL_LPLL_BASE + 0x8B) ++#define REG_SCL_LPLL_46_L (REG_SCL_LPLL_BASE + 0x8C) ++#define REG_SCL_LPLL_46_H (REG_SCL_LPLL_BASE + 0x8D) ++#define REG_SCL_LPLL_47_L (REG_SCL_LPLL_BASE + 0x8E) ++#define REG_SCL_LPLL_47_H (REG_SCL_LPLL_BASE + 0x8F) ++#define REG_SCL_LPLL_48_L (REG_SCL_LPLL_BASE + 0x90) ++#define REG_SCL_LPLL_48_H (REG_SCL_LPLL_BASE + 0x91) ++#define REG_SCL_LPLL_49_L (REG_SCL_LPLL_BASE + 0x92) ++#define REG_SCL_LPLL_49_H (REG_SCL_LPLL_BASE + 0x93) ++#define REG_SCL_LPLL_4A_L (REG_SCL_LPLL_BASE + 0x94) ++#define REG_SCL_LPLL_4A_H (REG_SCL_LPLL_BASE + 0x95) ++#define REG_SCL_LPLL_4B_L (REG_SCL_LPLL_BASE + 0x96) ++#define REG_SCL_LPLL_4B_H (REG_SCL_LPLL_BASE + 0x97) ++#define REG_SCL_LPLL_4C_L (REG_SCL_LPLL_BASE + 0x98) ++#define REG_SCL_LPLL_4C_H (REG_SCL_LPLL_BASE + 0x99) ++#define REG_SCL_LPLL_4D_L (REG_SCL_LPLL_BASE + 0x9A) ++#define REG_SCL_LPLL_4D_H (REG_SCL_LPLL_BASE + 0x9B) ++#define REG_SCL_LPLL_4E_L (REG_SCL_LPLL_BASE + 0x9C) ++#define REG_SCL_LPLL_4E_H (REG_SCL_LPLL_BASE + 0x9D) ++#define REG_SCL_LPLL_4F_L (REG_SCL_LPLL_BASE + 0x9E) ++#define REG_SCL_LPLL_4F_H (REG_SCL_LPLL_BASE + 0x9F) ++#define REG_SCL_LPLL_50_L (REG_SCL_LPLL_BASE + 0xA0) ++#define REG_SCL_LPLL_50_H (REG_SCL_LPLL_BASE + 0xA1) ++#define REG_SCL_LPLL_51_L (REG_SCL_LPLL_BASE + 0xA2) ++#define REG_SCL_LPLL_51_H (REG_SCL_LPLL_BASE + 0xA3) ++#define REG_SCL_LPLL_52_L (REG_SCL_LPLL_BASE + 0xA4) ++#define REG_SCL_LPLL_52_H (REG_SCL_LPLL_BASE + 0xA5) ++#define REG_SCL_LPLL_53_L (REG_SCL_LPLL_BASE + 0xA6) ++#define REG_SCL_LPLL_53_H (REG_SCL_LPLL_BASE + 0xA7) ++#define REG_SCL_LPLL_54_L (REG_SCL_LPLL_BASE + 0xA8) ++#define REG_SCL_LPLL_54_H (REG_SCL_LPLL_BASE + 0xA9) ++#define REG_SCL_LPLL_55_L (REG_SCL_LPLL_BASE + 0xAA) ++#define REG_SCL_LPLL_55_H (REG_SCL_LPLL_BASE + 0xAB) ++#define REG_SCL_LPLL_56_L (REG_SCL_LPLL_BASE + 0xAC) ++#define REG_SCL_LPLL_56_H (REG_SCL_LPLL_BASE + 0xAD) ++#define REG_SCL_LPLL_57_L (REG_SCL_LPLL_BASE + 0xAE) ++#define REG_SCL_LPLL_57_H (REG_SCL_LPLL_BASE + 0xAF) ++#define REG_SCL_LPLL_58_L (REG_SCL_LPLL_BASE + 0xB0) ++#define REG_SCL_LPLL_58_H (REG_SCL_LPLL_BASE + 0xB1) ++#define REG_SCL_LPLL_59_L (REG_SCL_LPLL_BASE + 0xB2) ++#define REG_SCL_LPLL_59_H (REG_SCL_LPLL_BASE + 0xB3) ++#define REG_SCL_LPLL_5A_L (REG_SCL_LPLL_BASE + 0xB4) ++#define REG_SCL_LPLL_5A_H (REG_SCL_LPLL_BASE + 0xB5) ++#define REG_SCL_LPLL_5B_L (REG_SCL_LPLL_BASE + 0xB6) ++#define REG_SCL_LPLL_5B_H (REG_SCL_LPLL_BASE + 0xB7) ++#define REG_SCL_LPLL_5C_L (REG_SCL_LPLL_BASE + 0xB8) ++#define REG_SCL_LPLL_5C_H (REG_SCL_LPLL_BASE + 0xB9) ++#define REG_SCL_LPLL_5D_L (REG_SCL_LPLL_BASE + 0xBA) ++#define REG_SCL_LPLL_5D_H (REG_SCL_LPLL_BASE + 0xBB) ++#define REG_SCL_LPLL_5E_L (REG_SCL_LPLL_BASE + 0xBC) ++#define REG_SCL_LPLL_5E_H (REG_SCL_LPLL_BASE + 0xBD) ++#define REG_SCL_LPLL_5F_L (REG_SCL_LPLL_BASE + 0xBE) ++#define REG_SCL_LPLL_5F_H (REG_SCL_LPLL_BASE + 0xBF) ++#define REG_SCL_LPLL_60_L (REG_SCL_LPLL_BASE + 0xC0) ++#define REG_SCL_LPLL_60_H (REG_SCL_LPLL_BASE + 0xC1) ++#define REG_SCL_LPLL_61_L (REG_SCL_LPLL_BASE + 0xC2) ++#define REG_SCL_LPLL_61_H (REG_SCL_LPLL_BASE + 0xC3) ++#define REG_SCL_LPLL_62_L (REG_SCL_LPLL_BASE + 0xC4) ++#define REG_SCL_LPLL_62_H (REG_SCL_LPLL_BASE + 0xC5) ++#define REG_SCL_LPLL_63_L (REG_SCL_LPLL_BASE + 0xC6) ++#define REG_SCL_LPLL_63_H (REG_SCL_LPLL_BASE + 0xC7) ++#define REG_SCL_LPLL_64_L (REG_SCL_LPLL_BASE + 0xC8) ++#define REG_SCL_LPLL_64_H (REG_SCL_LPLL_BASE + 0xC9) ++#define REG_SCL_LPLL_65_L (REG_SCL_LPLL_BASE + 0xCA) ++#define REG_SCL_LPLL_65_H (REG_SCL_LPLL_BASE + 0xCB) ++#define REG_SCL_LPLL_66_L (REG_SCL_LPLL_BASE + 0xCC) ++#define REG_SCL_LPLL_66_H (REG_SCL_LPLL_BASE + 0xCD) ++#define REG_SCL_LPLL_67_L (REG_SCL_LPLL_BASE + 0xCE) ++#define REG_SCL_LPLL_67_H (REG_SCL_LPLL_BASE + 0xCF) ++#define REG_SCL_LPLL_68_L (REG_SCL_LPLL_BASE + 0xD0) ++#define REG_SCL_LPLL_68_H (REG_SCL_LPLL_BASE + 0xD1) ++#define REG_SCL_LPLL_69_L (REG_SCL_LPLL_BASE + 0xD2) ++#define REG_SCL_LPLL_69_H (REG_SCL_LPLL_BASE + 0xD3) ++#define REG_SCL_LPLL_6A_L (REG_SCL_LPLL_BASE + 0xD4) ++#define REG_SCL_LPLL_6A_H (REG_SCL_LPLL_BASE + 0xD5) ++#define REG_SCL_LPLL_6B_L (REG_SCL_LPLL_BASE + 0xD6) ++#define REG_SCL_LPLL_6B_H (REG_SCL_LPLL_BASE + 0xD7) ++#define REG_SCL_LPLL_6C_L (REG_SCL_LPLL_BASE + 0xD8) ++#define REG_SCL_LPLL_6C_H (REG_SCL_LPLL_BASE + 0xD9) ++#define REG_SCL_LPLL_6D_L (REG_SCL_LPLL_BASE + 0xDA) ++#define REG_SCL_LPLL_6D_H (REG_SCL_LPLL_BASE + 0xDB) ++#define REG_SCL_LPLL_6E_L (REG_SCL_LPLL_BASE + 0xDC) ++#define REG_SCL_LPLL_6E_H (REG_SCL_LPLL_BASE + 0xDD) ++#define REG_SCL_LPLL_6F_L (REG_SCL_LPLL_BASE + 0xDE) ++#define REG_SCL_LPLL_6F_H (REG_SCL_LPLL_BASE + 0xDF) ++#define REG_SCL_LPLL_70_L (REG_SCL_LPLL_BASE + 0xE0) ++#define REG_SCL_LPLL_70_H (REG_SCL_LPLL_BASE + 0xE1) ++#define REG_SCL_LPLL_71_L (REG_SCL_LPLL_BASE + 0xE2) ++#define REG_SCL_LPLL_71_H (REG_SCL_LPLL_BASE + 0xE3) ++#define REG_SCL_LPLL_72_L (REG_SCL_LPLL_BASE + 0xE4) ++#define REG_SCL_LPLL_72_H (REG_SCL_LPLL_BASE + 0xE5) ++#define REG_SCL_LPLL_73_L (REG_SCL_LPLL_BASE + 0xE6) ++#define REG_SCL_LPLL_73_H (REG_SCL_LPLL_BASE + 0xE7) ++#define REG_SCL_LPLL_74_L (REG_SCL_LPLL_BASE + 0xE8) ++#define REG_SCL_LPLL_74_H (REG_SCL_LPLL_BASE + 0xE9) ++#define REG_SCL_LPLL_75_L (REG_SCL_LPLL_BASE + 0xEA) ++#define REG_SCL_LPLL_75_H (REG_SCL_LPLL_BASE + 0xEB) ++#define REG_SCL_LPLL_76_L (REG_SCL_LPLL_BASE + 0xEC) ++#define REG_SCL_LPLL_76_H (REG_SCL_LPLL_BASE + 0xED) ++#define REG_SCL_LPLL_77_L (REG_SCL_LPLL_BASE + 0xEE) ++#define REG_SCL_LPLL_77_H (REG_SCL_LPLL_BASE + 0xEF) ++#define REG_SCL_LPLL_78_L (REG_SCL_LPLL_BASE + 0xF0) ++#define REG_SCL_LPLL_78_H (REG_SCL_LPLL_BASE + 0xF1) ++#define REG_SCL_LPLL_79_L (REG_SCL_LPLL_BASE + 0xF2) ++#define REG_SCL_LPLL_79_H (REG_SCL_LPLL_BASE + 0xF3) ++#define REG_SCL_LPLL_7A_L (REG_SCL_LPLL_BASE + 0xF4) ++#define REG_SCL_LPLL_7A_H (REG_SCL_LPLL_BASE + 0xF5) ++#define REG_SCL_LPLL_7B_L (REG_SCL_LPLL_BASE + 0xF6) ++#define REG_SCL_LPLL_7B_H (REG_SCL_LPLL_BASE + 0xF7) ++#define REG_SCL_LPLL_7C_L (REG_SCL_LPLL_BASE + 0xF8) ++#define REG_SCL_LPLL_7C_H (REG_SCL_LPLL_BASE + 0xF9) ++#define REG_SCL_LPLL_7D_L (REG_SCL_LPLL_BASE + 0xFA) ++#define REG_SCL_LPLL_7D_H (REG_SCL_LPLL_BASE + 0xFB) ++#define REG_SCL_LPLL_7E_L (REG_SCL_LPLL_BASE + 0xFC) ++#define REG_SCL_LPLL_7E_H (REG_SCL_LPLL_BASE + 0xFD) ++#define REG_SCL_LPLL_7F_L (REG_SCL_LPLL_BASE + 0xFE) ++#define REG_SCL_LPLL_7F_H (REG_SCL_LPLL_BASE + 0xFF) ++ ++#define REG_SCL_HVSP0_00_L (REG_SCL_HVSP0_BASE + 0x00) ++#define REG_SCL_HVSP0_00_H (REG_SCL_HVSP0_BASE + 0x01) ++#define REG_SCL_HVSP0_01_L (REG_SCL_HVSP0_BASE + 0x02) ++#define REG_SCL_HVSP0_01_H (REG_SCL_HVSP0_BASE + 0x03) ++#define REG_SCL_HVSP0_02_L (REG_SCL_HVSP0_BASE + 0x04) ++#define REG_SCL_HVSP0_02_H (REG_SCL_HVSP0_BASE + 0x05) ++#define REG_SCL_HVSP0_03_L (REG_SCL_HVSP0_BASE + 0x06) ++#define REG_SCL_HVSP0_03_H (REG_SCL_HVSP0_BASE + 0x07) ++#define REG_SCL_HVSP0_04_L (REG_SCL_HVSP0_BASE + 0x08) ++#define REG_SCL_HVSP0_04_H (REG_SCL_HVSP0_BASE + 0x09) ++#define REG_SCL_HVSP0_05_L (REG_SCL_HVSP0_BASE + 0x0A) ++#define REG_SCL_HVSP0_05_H (REG_SCL_HVSP0_BASE + 0x0B) ++#define REG_SCL_HVSP0_06_L (REG_SCL_HVSP0_BASE + 0x0C) ++#define REG_SCL_HVSP0_06_H (REG_SCL_HVSP0_BASE + 0x0D) ++#define REG_SCL_HVSP0_07_L (REG_SCL_HVSP0_BASE + 0x0E) ++#define REG_SCL_HVSP0_07_H (REG_SCL_HVSP0_BASE + 0x0F) ++#define REG_SCL_HVSP0_08_L (REG_SCL_HVSP0_BASE + 0x10) ++#define REG_SCL_HVSP0_08_H (REG_SCL_HVSP0_BASE + 0x11) ++#define REG_SCL_HVSP0_09_L (REG_SCL_HVSP0_BASE + 0x12) ++#define REG_SCL_HVSP0_09_H (REG_SCL_HVSP0_BASE + 0x13) ++#define REG_SCL_HVSP0_0A_L (REG_SCL_HVSP0_BASE + 0x14) ++#define REG_SCL_HVSP0_0A_H (REG_SCL_HVSP0_BASE + 0x15) ++#define REG_SCL_HVSP0_0B_L (REG_SCL_HVSP0_BASE + 0x16) ++#define REG_SCL_HVSP0_0B_H (REG_SCL_HVSP0_BASE + 0x17) ++#define REG_SCL_HVSP0_0C_L (REG_SCL_HVSP0_BASE + 0x18) ++#define REG_SCL_HVSP0_0C_H (REG_SCL_HVSP0_BASE + 0x19) ++#define REG_SCL_HVSP0_0D_L (REG_SCL_HVSP0_BASE + 0x1A) ++#define REG_SCL_HVSP0_0D_H (REG_SCL_HVSP0_BASE + 0x1B) ++#define REG_SCL_HVSP0_0E_L (REG_SCL_HVSP0_BASE + 0x1C) ++#define REG_SCL_HVSP0_0E_H (REG_SCL_HVSP0_BASE + 0x1D) ++#define REG_SCL_HVSP0_0F_L (REG_SCL_HVSP0_BASE + 0x1E) ++#define REG_SCL_HVSP0_0F_H (REG_SCL_HVSP0_BASE + 0x1F) ++#define REG_SCL_HVSP0_10_L (REG_SCL_HVSP0_BASE + 0x20) ++#define REG_SCL_HVSP0_10_H (REG_SCL_HVSP0_BASE + 0x21) ++#define REG_SCL_HVSP0_11_L (REG_SCL_HVSP0_BASE + 0x22) ++#define REG_SCL_HVSP0_11_H (REG_SCL_HVSP0_BASE + 0x23) ++#define REG_SCL_HVSP0_12_L (REG_SCL_HVSP0_BASE + 0x24) ++#define REG_SCL_HVSP0_12_H (REG_SCL_HVSP0_BASE + 0x25) ++#define REG_SCL_HVSP0_13_L (REG_SCL_HVSP0_BASE + 0x26) ++#define REG_SCL_HVSP0_13_H (REG_SCL_HVSP0_BASE + 0x27) ++#define REG_SCL_HVSP0_14_L (REG_SCL_HVSP0_BASE + 0x28) ++#define REG_SCL_HVSP0_14_H (REG_SCL_HVSP0_BASE + 0x29) ++#define REG_SCL_HVSP0_15_L (REG_SCL_HVSP0_BASE + 0x2A) ++#define REG_SCL_HVSP0_15_H (REG_SCL_HVSP0_BASE + 0x2B) ++#define REG_SCL_HVSP0_16_L (REG_SCL_HVSP0_BASE + 0x2C) ++#define REG_SCL_HVSP0_16_H (REG_SCL_HVSP0_BASE + 0x2D) ++#define REG_SCL_HVSP0_17_L (REG_SCL_HVSP0_BASE + 0x2E) ++#define REG_SCL_HVSP0_17_H (REG_SCL_HVSP0_BASE + 0x2F) ++#define REG_SCL_HVSP0_18_L (REG_SCL_HVSP0_BASE + 0x30) ++#define REG_SCL_HVSP0_18_H (REG_SCL_HVSP0_BASE + 0x31) ++#define REG_SCL_HVSP0_19_L (REG_SCL_HVSP0_BASE + 0x32) ++#define REG_SCL_HVSP0_19_H (REG_SCL_HVSP0_BASE + 0x33) ++#define REG_SCL_HVSP0_1A_L (REG_SCL_HVSP0_BASE + 0x34) ++#define REG_SCL_HVSP0_1A_H (REG_SCL_HVSP0_BASE + 0x35) ++#define REG_SCL_HVSP0_1B_L (REG_SCL_HVSP0_BASE + 0x36) ++#define REG_SCL_HVSP0_1B_H (REG_SCL_HVSP0_BASE + 0x37) ++#define REG_SCL_HVSP0_1C_L (REG_SCL_HVSP0_BASE + 0x38) ++#define REG_SCL_HVSP0_1C_H (REG_SCL_HVSP0_BASE + 0x39) ++#define REG_SCL_HVSP0_1D_L (REG_SCL_HVSP0_BASE + 0x3A) ++#define REG_SCL_HVSP0_1D_H (REG_SCL_HVSP0_BASE + 0x3B) ++#define REG_SCL_HVSP0_1E_L (REG_SCL_HVSP0_BASE + 0x3C) ++#define REG_SCL_HVSP0_1E_H (REG_SCL_HVSP0_BASE + 0x3D) ++#define REG_SCL_HVSP0_1F_L (REG_SCL_HVSP0_BASE + 0x3E) ++#define REG_SCL_HVSP0_1F_H (REG_SCL_HVSP0_BASE + 0x3F) ++#define REG_SCL_HVSP0_20_L (REG_SCL_HVSP0_BASE + 0x40) ++#define REG_SCL_HVSP0_20_H (REG_SCL_HVSP0_BASE + 0x41) ++#define REG_SCL_HVSP0_21_L (REG_SCL_HVSP0_BASE + 0x42) ++#define REG_SCL_HVSP0_21_H (REG_SCL_HVSP0_BASE + 0x43) ++#define REG_SCL_HVSP0_22_L (REG_SCL_HVSP0_BASE + 0x44) ++#define REG_SCL_HVSP0_22_H (REG_SCL_HVSP0_BASE + 0x45) ++#define REG_SCL_HVSP0_23_L (REG_SCL_HVSP0_BASE + 0x46) ++#define REG_SCL_HVSP0_23_H (REG_SCL_HVSP0_BASE + 0x47) ++#define REG_SCL_HVSP0_24_L (REG_SCL_HVSP0_BASE + 0x48) ++#define REG_SCL_HVSP0_24_H (REG_SCL_HVSP0_BASE + 0x49) ++#define REG_SCL_HVSP0_25_L (REG_SCL_HVSP0_BASE + 0x4A) ++#define REG_SCL_HVSP0_25_H (REG_SCL_HVSP0_BASE + 0x4B) ++#define REG_SCL_HVSP0_26_L (REG_SCL_HVSP0_BASE + 0x4C) ++#define REG_SCL_HVSP0_26_H (REG_SCL_HVSP0_BASE + 0x4D) ++#define REG_SCL_HVSP0_27_L (REG_SCL_HVSP0_BASE + 0x4E) ++#define REG_SCL_HVSP0_27_H (REG_SCL_HVSP0_BASE + 0x4F) ++#define REG_SCL_HVSP0_28_L (REG_SCL_HVSP0_BASE + 0x50) ++#define REG_SCL_HVSP0_28_H (REG_SCL_HVSP0_BASE + 0x51) ++#define REG_SCL_HVSP0_29_L (REG_SCL_HVSP0_BASE + 0x52) ++#define REG_SCL_HVSP0_29_H (REG_SCL_HVSP0_BASE + 0x53) ++#define REG_SCL_HVSP0_2A_L (REG_SCL_HVSP0_BASE + 0x54) ++#define REG_SCL_HVSP0_2A_H (REG_SCL_HVSP0_BASE + 0x55) ++#define REG_SCL_HVSP0_2B_L (REG_SCL_HVSP0_BASE + 0x56) ++#define REG_SCL_HVSP0_2B_H (REG_SCL_HVSP0_BASE + 0x57) ++#define REG_SCL_HVSP0_2C_L (REG_SCL_HVSP0_BASE + 0x58) ++#define REG_SCL_HVSP0_2C_H (REG_SCL_HVSP0_BASE + 0x59) ++#define REG_SCL_HVSP0_2D_L (REG_SCL_HVSP0_BASE + 0x5A) ++#define REG_SCL_HVSP0_2D_H (REG_SCL_HVSP0_BASE + 0x5B) ++#define REG_SCL_HVSP0_2E_L (REG_SCL_HVSP0_BASE + 0x5C) ++#define REG_SCL_HVSP0_2E_H (REG_SCL_HVSP0_BASE + 0x5D) ++#define REG_SCL_HVSP0_2F_L (REG_SCL_HVSP0_BASE + 0x5E) ++#define REG_SCL_HVSP0_2F_H (REG_SCL_HVSP0_BASE + 0x5F) ++#define REG_SCL_HVSP0_30_L (REG_SCL_HVSP0_BASE + 0x60) ++#define REG_SCL_HVSP0_30_H (REG_SCL_HVSP0_BASE + 0x61) ++#define REG_SCL_HVSP0_31_L (REG_SCL_HVSP0_BASE + 0x62) ++#define REG_SCL_HVSP0_31_H (REG_SCL_HVSP0_BASE + 0x63) ++#define REG_SCL_HVSP0_32_L (REG_SCL_HVSP0_BASE + 0x64) ++#define REG_SCL_HVSP0_32_H (REG_SCL_HVSP0_BASE + 0x65) ++#define REG_SCL_HVSP0_33_L (REG_SCL_HVSP0_BASE + 0x66) ++#define REG_SCL_HVSP0_33_H (REG_SCL_HVSP0_BASE + 0x67) ++#define REG_SCL_HVSP0_34_L (REG_SCL_HVSP0_BASE + 0x68) ++#define REG_SCL_HVSP0_34_H (REG_SCL_HVSP0_BASE + 0x69) ++#define REG_SCL_HVSP0_35_L (REG_SCL_HVSP0_BASE + 0x6A) ++#define REG_SCL_HVSP0_35_H (REG_SCL_HVSP0_BASE + 0x6B) ++#define REG_SCL_HVSP0_36_L (REG_SCL_HVSP0_BASE + 0x6C) ++#define REG_SCL_HVSP0_36_H (REG_SCL_HVSP0_BASE + 0x6D) ++#define REG_SCL_HVSP0_37_L (REG_SCL_HVSP0_BASE + 0x6E) ++#define REG_SCL_HVSP0_37_H (REG_SCL_HVSP0_BASE + 0x6F) ++#define REG_SCL_HVSP0_38_L (REG_SCL_HVSP0_BASE + 0x70) ++#define REG_SCL_HVSP0_38_H (REG_SCL_HVSP0_BASE + 0x71) ++#define REG_SCL_HVSP0_39_L (REG_SCL_HVSP0_BASE + 0x72) ++#define REG_SCL_HVSP0_39_H (REG_SCL_HVSP0_BASE + 0x73) ++#define REG_SCL_HVSP0_3A_L (REG_SCL_HVSP0_BASE + 0x74) ++#define REG_SCL_HVSP0_3A_H (REG_SCL_HVSP0_BASE + 0x75) ++#define REG_SCL_HVSP0_3B_L (REG_SCL_HVSP0_BASE + 0x76) ++#define REG_SCL_HVSP0_3B_H (REG_SCL_HVSP0_BASE + 0x77) ++#define REG_SCL_HVSP0_3C_L (REG_SCL_HVSP0_BASE + 0x78) ++#define REG_SCL_HVSP0_3C_H (REG_SCL_HVSP0_BASE + 0x79) ++#define REG_SCL_HVSP0_3D_L (REG_SCL_HVSP0_BASE + 0x7A) ++#define REG_SCL_HVSP0_3D_H (REG_SCL_HVSP0_BASE + 0x7B) ++#define REG_SCL_HVSP0_3E_L (REG_SCL_HVSP0_BASE + 0x7C) ++#define REG_SCL_HVSP0_3E_H (REG_SCL_HVSP0_BASE + 0x7D) ++#define REG_SCL_HVSP0_3F_L (REG_SCL_HVSP0_BASE + 0x7E) ++#define REG_SCL_HVSP0_3F_H (REG_SCL_HVSP0_BASE + 0x7F) ++#define REG_SCL_HVSP0_40_L (REG_SCL_HVSP0_BASE + 0x80) ++#define REG_SCL_HVSP0_40_H (REG_SCL_HVSP0_BASE + 0x81) ++#define REG_SCL_HVSP0_41_L (REG_SCL_HVSP0_BASE + 0x82) ++#define REG_SCL_HVSP0_41_H (REG_SCL_HVSP0_BASE + 0x83) ++#define REG_SCL_HVSP0_42_L (REG_SCL_HVSP0_BASE + 0x84) ++#define REG_SCL_HVSP0_42_H (REG_SCL_HVSP0_BASE + 0x85) ++#define REG_SCL_HVSP0_43_L (REG_SCL_HVSP0_BASE + 0x86) ++#define REG_SCL_HVSP0_43_H (REG_SCL_HVSP0_BASE + 0x87) ++#define REG_SCL_HVSP0_44_L (REG_SCL_HVSP0_BASE + 0x88) ++#define REG_SCL_HVSP0_44_H (REG_SCL_HVSP0_BASE + 0x89) ++#define REG_SCL_HVSP0_45_L (REG_SCL_HVSP0_BASE + 0x8A) ++#define REG_SCL_HVSP0_45_H (REG_SCL_HVSP0_BASE + 0x8B) ++#define REG_SCL_HVSP0_46_L (REG_SCL_HVSP0_BASE + 0x8C) ++#define REG_SCL_HVSP0_46_H (REG_SCL_HVSP0_BASE + 0x8D) ++#define REG_SCL_HVSP0_47_L (REG_SCL_HVSP0_BASE + 0x8E) ++#define REG_SCL_HVSP0_47_H (REG_SCL_HVSP0_BASE + 0x8F) ++#define REG_SCL_HVSP0_48_L (REG_SCL_HVSP0_BASE + 0x90) ++#define REG_SCL_HVSP0_48_H (REG_SCL_HVSP0_BASE + 0x91) ++#define REG_SCL_HVSP0_49_L (REG_SCL_HVSP0_BASE + 0x92) ++#define REG_SCL_HVSP0_49_H (REG_SCL_HVSP0_BASE + 0x93) ++#define REG_SCL_HVSP0_4A_L (REG_SCL_HVSP0_BASE + 0x94) ++#define REG_SCL_HVSP0_4A_H (REG_SCL_HVSP0_BASE + 0x95) ++#define REG_SCL_HVSP0_4B_L (REG_SCL_HVSP0_BASE + 0x96) ++#define REG_SCL_HVSP0_4B_H (REG_SCL_HVSP0_BASE + 0x97) ++#define REG_SCL_HVSP0_4C_L (REG_SCL_HVSP0_BASE + 0x98) ++#define REG_SCL_HVSP0_4C_H (REG_SCL_HVSP0_BASE + 0x99) ++#define REG_SCL_HVSP0_4D_L (REG_SCL_HVSP0_BASE + 0x9A) ++#define REG_SCL_HVSP0_4D_H (REG_SCL_HVSP0_BASE + 0x9B) ++#define REG_SCL_HVSP0_4E_L (REG_SCL_HVSP0_BASE + 0x9C) ++#define REG_SCL_HVSP0_4E_H (REG_SCL_HVSP0_BASE + 0x9D) ++#define REG_SCL_HVSP0_4F_L (REG_SCL_HVSP0_BASE + 0x9E) ++#define REG_SCL_HVSP0_4F_H (REG_SCL_HVSP0_BASE + 0x9F) ++#define REG_SCL_HVSP0_50_L (REG_SCL_HVSP0_BASE + 0xA0) ++#define REG_SCL_HVSP0_50_H (REG_SCL_HVSP0_BASE + 0xA1) ++#define REG_SCL_HVSP0_51_L (REG_SCL_HVSP0_BASE + 0xA2) ++#define REG_SCL_HVSP0_51_H (REG_SCL_HVSP0_BASE + 0xA3) ++#define REG_SCL_HVSP0_52_L (REG_SCL_HVSP0_BASE + 0xA4) ++#define REG_SCL_HVSP0_52_H (REG_SCL_HVSP0_BASE + 0xA5) ++#define REG_SCL_HVSP0_53_L (REG_SCL_HVSP0_BASE + 0xA6) ++#define REG_SCL_HVSP0_53_H (REG_SCL_HVSP0_BASE + 0xA7) ++#define REG_SCL_HVSP0_54_L (REG_SCL_HVSP0_BASE + 0xA8) ++#define REG_SCL_HVSP0_54_H (REG_SCL_HVSP0_BASE + 0xA9) ++#define REG_SCL_HVSP0_55_L (REG_SCL_HVSP0_BASE + 0xAA) ++#define REG_SCL_HVSP0_55_H (REG_SCL_HVSP0_BASE + 0xAB) ++#define REG_SCL_HVSP0_56_L (REG_SCL_HVSP0_BASE + 0xAC) ++#define REG_SCL_HVSP0_56_H (REG_SCL_HVSP0_BASE + 0xAD) ++#define REG_SCL_HVSP0_57_L (REG_SCL_HVSP0_BASE + 0xAE) ++#define REG_SCL_HVSP0_57_H (REG_SCL_HVSP0_BASE + 0xAF) ++#define REG_SCL_HVSP0_58_L (REG_SCL_HVSP0_BASE + 0xB0) ++#define REG_SCL_HVSP0_58_H (REG_SCL_HVSP0_BASE + 0xB1) ++#define REG_SCL_HVSP0_59_L (REG_SCL_HVSP0_BASE + 0xB2) ++#define REG_SCL_HVSP0_59_H (REG_SCL_HVSP0_BASE + 0xB3) ++#define REG_SCL_HVSP0_5A_L (REG_SCL_HVSP0_BASE + 0xB4) ++#define REG_SCL_HVSP0_5A_H (REG_SCL_HVSP0_BASE + 0xB5) ++#define REG_SCL_HVSP0_5B_L (REG_SCL_HVSP0_BASE + 0xB6) ++#define REG_SCL_HVSP0_5B_H (REG_SCL_HVSP0_BASE + 0xB7) ++#define REG_SCL_HVSP0_5C_L (REG_SCL_HVSP0_BASE + 0xB8) ++#define REG_SCL_HVSP0_5C_H (REG_SCL_HVSP0_BASE + 0xB9) ++#define REG_SCL_HVSP0_5D_L (REG_SCL_HVSP0_BASE + 0xBA) ++#define REG_SCL_HVSP0_5D_H (REG_SCL_HVSP0_BASE + 0xBB) ++#define REG_SCL_HVSP0_5E_L (REG_SCL_HVSP0_BASE + 0xBC) ++#define REG_SCL_HVSP0_5E_H (REG_SCL_HVSP0_BASE + 0xBD) ++#define REG_SCL_HVSP0_5F_L (REG_SCL_HVSP0_BASE + 0xBE) ++#define REG_SCL_HVSP0_5F_H (REG_SCL_HVSP0_BASE + 0xBF) ++#define REG_SCL_HVSP0_60_L (REG_SCL_HVSP0_BASE + 0xC0) ++#define REG_SCL_HVSP0_60_H (REG_SCL_HVSP0_BASE + 0xC1) ++#define REG_SCL_HVSP0_61_L (REG_SCL_HVSP0_BASE + 0xC2) ++#define REG_SCL_HVSP0_61_H (REG_SCL_HVSP0_BASE + 0xC3) ++#define REG_SCL_HVSP0_62_L (REG_SCL_HVSP0_BASE + 0xC4) ++#define REG_SCL_HVSP0_62_H (REG_SCL_HVSP0_BASE + 0xC5) ++#define REG_SCL_HVSP0_63_L (REG_SCL_HVSP0_BASE + 0xC6) ++#define REG_SCL_HVSP0_63_H (REG_SCL_HVSP0_BASE + 0xC7) ++#define REG_SCL_HVSP0_64_L (REG_SCL_HVSP0_BASE + 0xC8) ++#define REG_SCL_HVSP0_64_H (REG_SCL_HVSP0_BASE + 0xC9) ++#define REG_SCL_HVSP0_65_L (REG_SCL_HVSP0_BASE + 0xCA) ++#define REG_SCL_HVSP0_65_H (REG_SCL_HVSP0_BASE + 0xCB) ++#define REG_SCL_HVSP0_66_L (REG_SCL_HVSP0_BASE + 0xCC) ++#define REG_SCL_HVSP0_66_H (REG_SCL_HVSP0_BASE + 0xCD) ++#define REG_SCL_HVSP0_67_L (REG_SCL_HVSP0_BASE + 0xCE) ++#define REG_SCL_HVSP0_67_H (REG_SCL_HVSP0_BASE + 0xCF) ++#define REG_SCL_HVSP0_68_L (REG_SCL_HVSP0_BASE + 0xD0) ++#define REG_SCL_HVSP0_68_H (REG_SCL_HVSP0_BASE + 0xD1) ++#define REG_SCL_HVSP0_69_L (REG_SCL_HVSP0_BASE + 0xD2) ++#define REG_SCL_HVSP0_69_H (REG_SCL_HVSP0_BASE + 0xD3) ++#define REG_SCL_HVSP0_6A_L (REG_SCL_HVSP0_BASE + 0xD4) ++#define REG_SCL_HVSP0_6A_H (REG_SCL_HVSP0_BASE + 0xD5) ++#define REG_SCL_HVSP0_6B_L (REG_SCL_HVSP0_BASE + 0xD6) ++#define REG_SCL_HVSP0_6B_H (REG_SCL_HVSP0_BASE + 0xD7) ++#define REG_SCL_HVSP0_6C_L (REG_SCL_HVSP0_BASE + 0xD8) ++#define REG_SCL_HVSP0_6C_H (REG_SCL_HVSP0_BASE + 0xD9) ++#define REG_SCL_HVSP0_6D_L (REG_SCL_HVSP0_BASE + 0xDA) ++#define REG_SCL_HVSP0_6D_H (REG_SCL_HVSP0_BASE + 0xDB) ++#define REG_SCL_HVSP0_6E_L (REG_SCL_HVSP0_BASE + 0xDC) ++#define REG_SCL_HVSP0_6E_H (REG_SCL_HVSP0_BASE + 0xDD) ++#define REG_SCL_HVSP0_6F_L (REG_SCL_HVSP0_BASE + 0xDE) ++#define REG_SCL_HVSP0_6F_H (REG_SCL_HVSP0_BASE + 0xDF) ++#define REG_SCL_HVSP0_70_L (REG_SCL_HVSP0_BASE + 0xE0) ++#define REG_SCL_HVSP0_70_H (REG_SCL_HVSP0_BASE + 0xE1) ++#define REG_SCL_HVSP0_71_L (REG_SCL_HVSP0_BASE + 0xE2) ++#define REG_SCL_HVSP0_71_H (REG_SCL_HVSP0_BASE + 0xE3) ++#define REG_SCL_HVSP0_72_L (REG_SCL_HVSP0_BASE + 0xE4) ++#define REG_SCL_HVSP0_72_H (REG_SCL_HVSP0_BASE + 0xE5) ++#define REG_SCL_HVSP0_73_L (REG_SCL_HVSP0_BASE + 0xE6) ++#define REG_SCL_HVSP0_73_H (REG_SCL_HVSP0_BASE + 0xE7) ++#define REG_SCL_HVSP0_74_L (REG_SCL_HVSP0_BASE + 0xE8) ++#define REG_SCL_HVSP0_74_H (REG_SCL_HVSP0_BASE + 0xE9) ++#define REG_SCL_HVSP0_75_L (REG_SCL_HVSP0_BASE + 0xEA) ++#define REG_SCL_HVSP0_75_H (REG_SCL_HVSP0_BASE + 0xEB) ++#define REG_SCL_HVSP0_76_L (REG_SCL_HVSP0_BASE + 0xEC) ++#define REG_SCL_HVSP0_76_H (REG_SCL_HVSP0_BASE + 0xED) ++#define REG_SCL_HVSP0_77_L (REG_SCL_HVSP0_BASE + 0xEE) ++#define REG_SCL_HVSP0_77_H (REG_SCL_HVSP0_BASE + 0xEF) ++#define REG_SCL_HVSP0_78_L (REG_SCL_HVSP0_BASE + 0xF0) ++#define REG_SCL_HVSP0_78_H (REG_SCL_HVSP0_BASE + 0xF1) ++#define REG_SCL_HVSP0_79_L (REG_SCL_HVSP0_BASE + 0xF2) ++#define REG_SCL_HVSP0_79_H (REG_SCL_HVSP0_BASE + 0xF3) ++#define REG_SCL_HVSP0_7A_L (REG_SCL_HVSP0_BASE + 0xF4) ++#define REG_SCL_HVSP0_7A_H (REG_SCL_HVSP0_BASE + 0xF5) ++#define REG_SCL_HVSP0_7B_L (REG_SCL_HVSP0_BASE + 0xF6) ++#define REG_SCL_HVSP0_7B_H (REG_SCL_HVSP0_BASE + 0xF7) ++#define REG_SCL_HVSP0_7C_L (REG_SCL_HVSP0_BASE + 0xF8) ++#define REG_SCL_HVSP0_7C_H (REG_SCL_HVSP0_BASE + 0xF9) ++#define REG_SCL_HVSP0_7D_L (REG_SCL_HVSP0_BASE + 0xFA) ++#define REG_SCL_HVSP0_7D_H (REG_SCL_HVSP0_BASE + 0xFB) ++#define REG_SCL_HVSP0_7E_L (REG_SCL_HVSP0_BASE + 0xFC) ++#define REG_SCL_HVSP0_7E_H (REG_SCL_HVSP0_BASE + 0xFD) ++#define REG_SCL_HVSP0_7F_L (REG_SCL_HVSP0_BASE + 0xFE) ++#define REG_SCL_HVSP0_7F_H (REG_SCL_HVSP0_BASE + 0xFF) ++ ++#define REG_SCL_HVSP1_00_L (REG_SCL_HVSP1_BASE + 0x00) ++#define REG_SCL_HVSP1_00_H (REG_SCL_HVSP1_BASE + 0x01) ++#define REG_SCL_HVSP1_01_L (REG_SCL_HVSP1_BASE + 0x02) ++#define REG_SCL_HVSP1_01_H (REG_SCL_HVSP1_BASE + 0x03) ++#define REG_SCL_HVSP1_02_L (REG_SCL_HVSP1_BASE + 0x04) ++#define REG_SCL_HVSP1_02_H (REG_SCL_HVSP1_BASE + 0x05) ++#define REG_SCL_HVSP1_03_L (REG_SCL_HVSP1_BASE + 0x06) ++#define REG_SCL_HVSP1_03_H (REG_SCL_HVSP1_BASE + 0x07) ++#define REG_SCL_HVSP1_04_L (REG_SCL_HVSP1_BASE + 0x08) ++#define REG_SCL_HVSP1_04_H (REG_SCL_HVSP1_BASE + 0x09) ++#define REG_SCL_HVSP1_05_L (REG_SCL_HVSP1_BASE + 0x0A) ++#define REG_SCL_HVSP1_05_H (REG_SCL_HVSP1_BASE + 0x0B) ++#define REG_SCL_HVSP1_06_L (REG_SCL_HVSP1_BASE + 0x0C) ++#define REG_SCL_HVSP1_06_H (REG_SCL_HVSP1_BASE + 0x0D) ++#define REG_SCL_HVSP1_07_L (REG_SCL_HVSP1_BASE + 0x0E) ++#define REG_SCL_HVSP1_07_H (REG_SCL_HVSP1_BASE + 0x0F) ++#define REG_SCL_HVSP1_08_L (REG_SCL_HVSP1_BASE + 0x10) ++#define REG_SCL_HVSP1_08_H (REG_SCL_HVSP1_BASE + 0x11) ++#define REG_SCL_HVSP1_09_L (REG_SCL_HVSP1_BASE + 0x12) ++#define REG_SCL_HVSP1_09_H (REG_SCL_HVSP1_BASE + 0x13) ++#define REG_SCL_HVSP1_0A_L (REG_SCL_HVSP1_BASE + 0x14) ++#define REG_SCL_HVSP1_0A_H (REG_SCL_HVSP1_BASE + 0x15) ++#define REG_SCL_HVSP1_0B_L (REG_SCL_HVSP1_BASE + 0x16) ++#define REG_SCL_HVSP1_0B_H (REG_SCL_HVSP1_BASE + 0x17) ++#define REG_SCL_HVSP1_0C_L (REG_SCL_HVSP1_BASE + 0x18) ++#define REG_SCL_HVSP1_0C_H (REG_SCL_HVSP1_BASE + 0x19) ++#define REG_SCL_HVSP1_0D_L (REG_SCL_HVSP1_BASE + 0x1A) ++#define REG_SCL_HVSP1_0D_H (REG_SCL_HVSP1_BASE + 0x1B) ++#define REG_SCL_HVSP1_0E_L (REG_SCL_HVSP1_BASE + 0x1C) ++#define REG_SCL_HVSP1_0E_H (REG_SCL_HVSP1_BASE + 0x1D) ++#define REG_SCL_HVSP1_0F_L (REG_SCL_HVSP1_BASE + 0x1E) ++#define REG_SCL_HVSP1_0F_H (REG_SCL_HVSP1_BASE + 0x1F) ++#define REG_SCL_HVSP1_10_L (REG_SCL_HVSP1_BASE + 0x20) ++#define REG_SCL_HVSP1_10_H (REG_SCL_HVSP1_BASE + 0x21) ++#define REG_SCL_HVSP1_11_L (REG_SCL_HVSP1_BASE + 0x22) ++#define REG_SCL_HVSP1_11_H (REG_SCL_HVSP1_BASE + 0x23) ++#define REG_SCL_HVSP1_12_L (REG_SCL_HVSP1_BASE + 0x24) ++#define REG_SCL_HVSP1_12_H (REG_SCL_HVSP1_BASE + 0x25) ++#define REG_SCL_HVSP1_13_L (REG_SCL_HVSP1_BASE + 0x26) ++#define REG_SCL_HVSP1_13_H (REG_SCL_HVSP1_BASE + 0x27) ++#define REG_SCL_HVSP1_14_L (REG_SCL_HVSP1_BASE + 0x28) ++#define REG_SCL_HVSP1_14_H (REG_SCL_HVSP1_BASE + 0x29) ++#define REG_SCL_HVSP1_15_L (REG_SCL_HVSP1_BASE + 0x2A) ++#define REG_SCL_HVSP1_15_H (REG_SCL_HVSP1_BASE + 0x2B) ++#define REG_SCL_HVSP1_16_L (REG_SCL_HVSP1_BASE + 0x2C) ++#define REG_SCL_HVSP1_16_H (REG_SCL_HVSP1_BASE + 0x2D) ++#define REG_SCL_HVSP1_17_L (REG_SCL_HVSP1_BASE + 0x2E) ++#define REG_SCL_HVSP1_17_H (REG_SCL_HVSP1_BASE + 0x2F) ++#define REG_SCL_HVSP1_18_L (REG_SCL_HVSP1_BASE + 0x30) ++#define REG_SCL_HVSP1_18_H (REG_SCL_HVSP1_BASE + 0x31) ++#define REG_SCL_HVSP1_19_L (REG_SCL_HVSP1_BASE + 0x32) ++#define REG_SCL_HVSP1_19_H (REG_SCL_HVSP1_BASE + 0x33) ++#define REG_SCL_HVSP1_1A_L (REG_SCL_HVSP1_BASE + 0x34) ++#define REG_SCL_HVSP1_1A_H (REG_SCL_HVSP1_BASE + 0x35) ++#define REG_SCL_HVSP1_1B_L (REG_SCL_HVSP1_BASE + 0x36) ++#define REG_SCL_HVSP1_1B_H (REG_SCL_HVSP1_BASE + 0x37) ++#define REG_SCL_HVSP1_1C_L (REG_SCL_HVSP1_BASE + 0x38) ++#define REG_SCL_HVSP1_1C_H (REG_SCL_HVSP1_BASE + 0x39) ++#define REG_SCL_HVSP1_1D_L (REG_SCL_HVSP1_BASE + 0x3A) ++#define REG_SCL_HVSP1_1D_H (REG_SCL_HVSP1_BASE + 0x3B) ++#define REG_SCL_HVSP1_1E_L (REG_SCL_HVSP1_BASE + 0x3C) ++#define REG_SCL_HVSP1_1E_H (REG_SCL_HVSP1_BASE + 0x3D) ++#define REG_SCL_HVSP1_1F_L (REG_SCL_HVSP1_BASE + 0x3E) ++#define REG_SCL_HVSP1_1F_H (REG_SCL_HVSP1_BASE + 0x3F) ++#define REG_SCL_HVSP1_20_L (REG_SCL_HVSP1_BASE + 0x40) ++#define REG_SCL_HVSP1_20_H (REG_SCL_HVSP1_BASE + 0x41) ++#define REG_SCL_HVSP1_21_L (REG_SCL_HVSP1_BASE + 0x42) ++#define REG_SCL_HVSP1_21_H (REG_SCL_HVSP1_BASE + 0x43) ++#define REG_SCL_HVSP1_22_L (REG_SCL_HVSP1_BASE + 0x44) ++#define REG_SCL_HVSP1_22_H (REG_SCL_HVSP1_BASE + 0x45) ++#define REG_SCL_HVSP1_23_L (REG_SCL_HVSP1_BASE + 0x46) ++#define REG_SCL_HVSP1_23_H (REG_SCL_HVSP1_BASE + 0x47) ++#define REG_SCL_HVSP1_24_L (REG_SCL_HVSP1_BASE + 0x48) ++#define REG_SCL_HVSP1_24_H (REG_SCL_HVSP1_BASE + 0x49) ++#define REG_SCL_HVSP1_25_L (REG_SCL_HVSP1_BASE + 0x4A) ++#define REG_SCL_HVSP1_25_H (REG_SCL_HVSP1_BASE + 0x4B) ++#define REG_SCL_HVSP1_26_L (REG_SCL_HVSP1_BASE + 0x4C) ++#define REG_SCL_HVSP1_26_H (REG_SCL_HVSP1_BASE + 0x4D) ++#define REG_SCL_HVSP1_27_L (REG_SCL_HVSP1_BASE + 0x4E) ++#define REG_SCL_HVSP1_27_H (REG_SCL_HVSP1_BASE + 0x4F) ++#define REG_SCL_HVSP1_28_L (REG_SCL_HVSP1_BASE + 0x50) ++#define REG_SCL_HVSP1_28_H (REG_SCL_HVSP1_BASE + 0x51) ++#define REG_SCL_HVSP1_29_L (REG_SCL_HVSP1_BASE + 0x52) ++#define REG_SCL_HVSP1_29_H (REG_SCL_HVSP1_BASE + 0x53) ++#define REG_SCL_HVSP1_2A_L (REG_SCL_HVSP1_BASE + 0x54) ++#define REG_SCL_HVSP1_2A_H (REG_SCL_HVSP1_BASE + 0x55) ++#define REG_SCL_HVSP1_2B_L (REG_SCL_HVSP1_BASE + 0x56) ++#define REG_SCL_HVSP1_2B_H (REG_SCL_HVSP1_BASE + 0x57) ++#define REG_SCL_HVSP1_2C_L (REG_SCL_HVSP1_BASE + 0x58) ++#define REG_SCL_HVSP1_2C_H (REG_SCL_HVSP1_BASE + 0x59) ++#define REG_SCL_HVSP1_2D_L (REG_SCL_HVSP1_BASE + 0x5A) ++#define REG_SCL_HVSP1_2D_H (REG_SCL_HVSP1_BASE + 0x5B) ++#define REG_SCL_HVSP1_2E_L (REG_SCL_HVSP1_BASE + 0x5C) ++#define REG_SCL_HVSP1_2E_H (REG_SCL_HVSP1_BASE + 0x5D) ++#define REG_SCL_HVSP1_2F_L (REG_SCL_HVSP1_BASE + 0x5E) ++#define REG_SCL_HVSP1_2F_H (REG_SCL_HVSP1_BASE + 0x5F) ++#define REG_SCL_HVSP1_30_L (REG_SCL_HVSP1_BASE + 0x60) ++#define REG_SCL_HVSP1_30_H (REG_SCL_HVSP1_BASE + 0x61) ++#define REG_SCL_HVSP1_31_L (REG_SCL_HVSP1_BASE + 0x62) ++#define REG_SCL_HVSP1_31_H (REG_SCL_HVSP1_BASE + 0x63) ++#define REG_SCL_HVSP1_32_L (REG_SCL_HVSP1_BASE + 0x64) ++#define REG_SCL_HVSP1_32_H (REG_SCL_HVSP1_BASE + 0x65) ++#define REG_SCL_HVSP1_33_L (REG_SCL_HVSP1_BASE + 0x66) ++#define REG_SCL_HVSP1_33_H (REG_SCL_HVSP1_BASE + 0x67) ++#define REG_SCL_HVSP1_34_L (REG_SCL_HVSP1_BASE + 0x68) ++#define REG_SCL_HVSP1_34_H (REG_SCL_HVSP1_BASE + 0x69) ++#define REG_SCL_HVSP1_35_L (REG_SCL_HVSP1_BASE + 0x6A) ++#define REG_SCL_HVSP1_35_H (REG_SCL_HVSP1_BASE + 0x6B) ++#define REG_SCL_HVSP1_36_L (REG_SCL_HVSP1_BASE + 0x6C) ++#define REG_SCL_HVSP1_36_H (REG_SCL_HVSP1_BASE + 0x6D) ++#define REG_SCL_HVSP1_37_L (REG_SCL_HVSP1_BASE + 0x6E) ++#define REG_SCL_HVSP1_37_H (REG_SCL_HVSP1_BASE + 0x6F) ++#define REG_SCL_HVSP1_38_L (REG_SCL_HVSP1_BASE + 0x70) ++#define REG_SCL_HVSP1_38_H (REG_SCL_HVSP1_BASE + 0x71) ++#define REG_SCL_HVSP1_39_L (REG_SCL_HVSP1_BASE + 0x72) ++#define REG_SCL_HVSP1_39_H (REG_SCL_HVSP1_BASE + 0x73) ++#define REG_SCL_HVSP1_3A_L (REG_SCL_HVSP1_BASE + 0x74) ++#define REG_SCL_HVSP1_3A_H (REG_SCL_HVSP1_BASE + 0x75) ++#define REG_SCL_HVSP1_3B_L (REG_SCL_HVSP1_BASE + 0x76) ++#define REG_SCL_HVSP1_3B_H (REG_SCL_HVSP1_BASE + 0x77) ++#define REG_SCL_HVSP1_3C_L (REG_SCL_HVSP1_BASE + 0x78) ++#define REG_SCL_HVSP1_3C_H (REG_SCL_HVSP1_BASE + 0x79) ++#define REG_SCL_HVSP1_3D_L (REG_SCL_HVSP1_BASE + 0x7A) ++#define REG_SCL_HVSP1_3D_H (REG_SCL_HVSP1_BASE + 0x7B) ++#define REG_SCL_HVSP1_3E_L (REG_SCL_HVSP1_BASE + 0x7C) ++#define REG_SCL_HVSP1_3E_H (REG_SCL_HVSP1_BASE + 0x7D) ++#define REG_SCL_HVSP1_3F_L (REG_SCL_HVSP1_BASE + 0x7E) ++#define REG_SCL_HVSP1_3F_H (REG_SCL_HVSP1_BASE + 0x7F) ++#define REG_SCL_HVSP1_40_L (REG_SCL_HVSP1_BASE + 0x80) ++#define REG_SCL_HVSP1_40_H (REG_SCL_HVSP1_BASE + 0x81) ++#define REG_SCL_HVSP1_41_L (REG_SCL_HVSP1_BASE + 0x82) ++#define REG_SCL_HVSP1_41_H (REG_SCL_HVSP1_BASE + 0x83) ++#define REG_SCL_HVSP1_42_L (REG_SCL_HVSP1_BASE + 0x84) ++#define REG_SCL_HVSP1_42_H (REG_SCL_HVSP1_BASE + 0x85) ++#define REG_SCL_HVSP1_43_L (REG_SCL_HVSP1_BASE + 0x86) ++#define REG_SCL_HVSP1_43_H (REG_SCL_HVSP1_BASE + 0x87) ++#define REG_SCL_HVSP1_44_L (REG_SCL_HVSP1_BASE + 0x88) ++#define REG_SCL_HVSP1_44_H (REG_SCL_HVSP1_BASE + 0x89) ++#define REG_SCL_HVSP1_45_L (REG_SCL_HVSP1_BASE + 0x8A) ++#define REG_SCL_HVSP1_45_H (REG_SCL_HVSP1_BASE + 0x8B) ++#define REG_SCL_HVSP1_46_L (REG_SCL_HVSP1_BASE + 0x8C) ++#define REG_SCL_HVSP1_46_H (REG_SCL_HVSP1_BASE + 0x8D) ++#define REG_SCL_HVSP1_47_L (REG_SCL_HVSP1_BASE + 0x8E) ++#define REG_SCL_HVSP1_47_H (REG_SCL_HVSP1_BASE + 0x8F) ++#define REG_SCL_HVSP1_48_L (REG_SCL_HVSP1_BASE + 0x90) ++#define REG_SCL_HVSP1_48_H (REG_SCL_HVSP1_BASE + 0x91) ++#define REG_SCL_HVSP1_49_L (REG_SCL_HVSP1_BASE + 0x92) ++#define REG_SCL_HVSP1_49_H (REG_SCL_HVSP1_BASE + 0x93) ++#define REG_SCL_HVSP1_4A_L (REG_SCL_HVSP1_BASE + 0x94) ++#define REG_SCL_HVSP1_4A_H (REG_SCL_HVSP1_BASE + 0x95) ++#define REG_SCL_HVSP1_4B_L (REG_SCL_HVSP1_BASE + 0x96) ++#define REG_SCL_HVSP1_4B_H (REG_SCL_HVSP1_BASE + 0x97) ++#define REG_SCL_HVSP1_4C_L (REG_SCL_HVSP1_BASE + 0x98) ++#define REG_SCL_HVSP1_4C_H (REG_SCL_HVSP1_BASE + 0x99) ++#define REG_SCL_HVSP1_4D_L (REG_SCL_HVSP1_BASE + 0x9A) ++#define REG_SCL_HVSP1_4D_H (REG_SCL_HVSP1_BASE + 0x9B) ++#define REG_SCL_HVSP1_4E_L (REG_SCL_HVSP1_BASE + 0x9C) ++#define REG_SCL_HVSP1_4E_H (REG_SCL_HVSP1_BASE + 0x9D) ++#define REG_SCL_HVSP1_4F_L (REG_SCL_HVSP1_BASE + 0x9E) ++#define REG_SCL_HVSP1_4F_H (REG_SCL_HVSP1_BASE + 0x9F) ++#define REG_SCL_HVSP1_50_L (REG_SCL_HVSP1_BASE + 0xA0) ++#define REG_SCL_HVSP1_50_H (REG_SCL_HVSP1_BASE + 0xA1) ++#define REG_SCL_HVSP1_51_L (REG_SCL_HVSP1_BASE + 0xA2) ++#define REG_SCL_HVSP1_51_H (REG_SCL_HVSP1_BASE + 0xA3) ++#define REG_SCL_HVSP1_52_L (REG_SCL_HVSP1_BASE + 0xA4) ++#define REG_SCL_HVSP1_52_H (REG_SCL_HVSP1_BASE + 0xA5) ++#define REG_SCL_HVSP1_53_L (REG_SCL_HVSP1_BASE + 0xA6) ++#define REG_SCL_HVSP1_53_H (REG_SCL_HVSP1_BASE + 0xA7) ++#define REG_SCL_HVSP1_54_L (REG_SCL_HVSP1_BASE + 0xA8) ++#define REG_SCL_HVSP1_54_H (REG_SCL_HVSP1_BASE + 0xA9) ++#define REG_SCL_HVSP1_55_L (REG_SCL_HVSP1_BASE + 0xAA) ++#define REG_SCL_HVSP1_55_H (REG_SCL_HVSP1_BASE + 0xAB) ++#define REG_SCL_HVSP1_56_L (REG_SCL_HVSP1_BASE + 0xAC) ++#define REG_SCL_HVSP1_56_H (REG_SCL_HVSP1_BASE + 0xAD) ++#define REG_SCL_HVSP1_57_L (REG_SCL_HVSP1_BASE + 0xAE) ++#define REG_SCL_HVSP1_57_H (REG_SCL_HVSP1_BASE + 0xAF) ++#define REG_SCL_HVSP1_58_L (REG_SCL_HVSP1_BASE + 0xB0) ++#define REG_SCL_HVSP1_58_H (REG_SCL_HVSP1_BASE + 0xB1) ++#define REG_SCL_HVSP1_59_L (REG_SCL_HVSP1_BASE + 0xB2) ++#define REG_SCL_HVSP1_59_H (REG_SCL_HVSP1_BASE + 0xB3) ++#define REG_SCL_HVSP1_5A_L (REG_SCL_HVSP1_BASE + 0xB4) ++#define REG_SCL_HVSP1_5A_H (REG_SCL_HVSP1_BASE + 0xB5) ++#define REG_SCL_HVSP1_5B_L (REG_SCL_HVSP1_BASE + 0xB6) ++#define REG_SCL_HVSP1_5B_H (REG_SCL_HVSP1_BASE + 0xB7) ++#define REG_SCL_HVSP1_5C_L (REG_SCL_HVSP1_BASE + 0xB8) ++#define REG_SCL_HVSP1_5C_H (REG_SCL_HVSP1_BASE + 0xB9) ++#define REG_SCL_HVSP1_5D_L (REG_SCL_HVSP1_BASE + 0xBA) ++#define REG_SCL_HVSP1_5D_H (REG_SCL_HVSP1_BASE + 0xBB) ++#define REG_SCL_HVSP1_5E_L (REG_SCL_HVSP1_BASE + 0xBC) ++#define REG_SCL_HVSP1_5E_H (REG_SCL_HVSP1_BASE + 0xBD) ++#define REG_SCL_HVSP1_5F_L (REG_SCL_HVSP1_BASE + 0xBE) ++#define REG_SCL_HVSP1_5F_H (REG_SCL_HVSP1_BASE + 0xBF) ++#define REG_SCL_HVSP1_60_L (REG_SCL_HVSP1_BASE + 0xC0) ++#define REG_SCL_HVSP1_60_H (REG_SCL_HVSP1_BASE + 0xC1) ++#define REG_SCL_HVSP1_61_L (REG_SCL_HVSP1_BASE + 0xC2) ++#define REG_SCL_HVSP1_61_H (REG_SCL_HVSP1_BASE + 0xC3) ++#define REG_SCL_HVSP1_62_L (REG_SCL_HVSP1_BASE + 0xC4) ++#define REG_SCL_HVSP1_62_H (REG_SCL_HVSP1_BASE + 0xC5) ++#define REG_SCL_HVSP1_63_L (REG_SCL_HVSP1_BASE + 0xC6) ++#define REG_SCL_HVSP1_63_H (REG_SCL_HVSP1_BASE + 0xC7) ++#define REG_SCL_HVSP1_64_L (REG_SCL_HVSP1_BASE + 0xC8) ++#define REG_SCL_HVSP1_64_H (REG_SCL_HVSP1_BASE + 0xC9) ++#define REG_SCL_HVSP1_65_L (REG_SCL_HVSP1_BASE + 0xCA) ++#define REG_SCL_HVSP1_65_H (REG_SCL_HVSP1_BASE + 0xCB) ++#define REG_SCL_HVSP1_66_L (REG_SCL_HVSP1_BASE + 0xCC) ++#define REG_SCL_HVSP1_66_H (REG_SCL_HVSP1_BASE + 0xCD) ++#define REG_SCL_HVSP1_67_L (REG_SCL_HVSP1_BASE + 0xCE) ++#define REG_SCL_HVSP1_67_H (REG_SCL_HVSP1_BASE + 0xCF) ++#define REG_SCL_HVSP1_68_L (REG_SCL_HVSP1_BASE + 0xD0) ++#define REG_SCL_HVSP1_68_H (REG_SCL_HVSP1_BASE + 0xD1) ++#define REG_SCL_HVSP1_69_L (REG_SCL_HVSP1_BASE + 0xD2) ++#define REG_SCL_HVSP1_69_H (REG_SCL_HVSP1_BASE + 0xD3) ++#define REG_SCL_HVSP1_6A_L (REG_SCL_HVSP1_BASE + 0xD4) ++#define REG_SCL_HVSP1_6A_H (REG_SCL_HVSP1_BASE + 0xD5) ++#define REG_SCL_HVSP1_6B_L (REG_SCL_HVSP1_BASE + 0xD6) ++#define REG_SCL_HVSP1_6B_H (REG_SCL_HVSP1_BASE + 0xD7) ++#define REG_SCL_HVSP1_6C_L (REG_SCL_HVSP1_BASE + 0xD8) ++#define REG_SCL_HVSP1_6C_H (REG_SCL_HVSP1_BASE + 0xD9) ++#define REG_SCL_HVSP1_6D_L (REG_SCL_HVSP1_BASE + 0xDA) ++#define REG_SCL_HVSP1_6D_H (REG_SCL_HVSP1_BASE + 0xDB) ++#define REG_SCL_HVSP1_6E_L (REG_SCL_HVSP1_BASE + 0xDC) ++#define REG_SCL_HVSP1_6E_H (REG_SCL_HVSP1_BASE + 0xDD) ++#define REG_SCL_HVSP1_6F_L (REG_SCL_HVSP1_BASE + 0xDE) ++#define REG_SCL_HVSP1_6F_H (REG_SCL_HVSP1_BASE + 0xDF) ++#define REG_SCL_HVSP1_70_L (REG_SCL_HVSP1_BASE + 0xE0) ++#define REG_SCL_HVSP1_70_H (REG_SCL_HVSP1_BASE + 0xE1) ++#define REG_SCL_HVSP1_71_L (REG_SCL_HVSP1_BASE + 0xE2) ++#define REG_SCL_HVSP1_71_H (REG_SCL_HVSP1_BASE + 0xE3) ++#define REG_SCL_HVSP1_72_L (REG_SCL_HVSP1_BASE + 0xE4) ++#define REG_SCL_HVSP1_72_H (REG_SCL_HVSP1_BASE + 0xE5) ++#define REG_SCL_HVSP1_73_L (REG_SCL_HVSP1_BASE + 0xE6) ++#define REG_SCL_HVSP1_73_H (REG_SCL_HVSP1_BASE + 0xE7) ++#define REG_SCL_HVSP1_74_L (REG_SCL_HVSP1_BASE + 0xE8) ++#define REG_SCL_HVSP1_74_H (REG_SCL_HVSP1_BASE + 0xE9) ++#define REG_SCL_HVSP1_75_L (REG_SCL_HVSP1_BASE + 0xEA) ++#define REG_SCL_HVSP1_75_H (REG_SCL_HVSP1_BASE + 0xEB) ++#define REG_SCL_HVSP1_76_L (REG_SCL_HVSP1_BASE + 0xEC) ++#define REG_SCL_HVSP1_76_H (REG_SCL_HVSP1_BASE + 0xED) ++#define REG_SCL_HVSP1_77_L (REG_SCL_HVSP1_BASE + 0xEE) ++#define REG_SCL_HVSP1_77_H (REG_SCL_HVSP1_BASE + 0xEF) ++#define REG_SCL_HVSP1_78_L (REG_SCL_HVSP1_BASE + 0xF0) ++#define REG_SCL_HVSP1_78_H (REG_SCL_HVSP1_BASE + 0xF1) ++#define REG_SCL_HVSP1_79_L (REG_SCL_HVSP1_BASE + 0xF2) ++#define REG_SCL_HVSP1_79_H (REG_SCL_HVSP1_BASE + 0xF3) ++#define REG_SCL_HVSP1_7A_L (REG_SCL_HVSP1_BASE + 0xF4) ++#define REG_SCL_HVSP1_7A_H (REG_SCL_HVSP1_BASE + 0xF5) ++#define REG_SCL_HVSP1_7B_L (REG_SCL_HVSP1_BASE + 0xF6) ++#define REG_SCL_HVSP1_7B_H (REG_SCL_HVSP1_BASE + 0xF7) ++#define REG_SCL_HVSP1_7C_L (REG_SCL_HVSP1_BASE + 0xF8) ++#define REG_SCL_HVSP1_7C_H (REG_SCL_HVSP1_BASE + 0xF9) ++#define REG_SCL_HVSP1_7D_L (REG_SCL_HVSP1_BASE + 0xFA) ++#define REG_SCL_HVSP1_7D_H (REG_SCL_HVSP1_BASE + 0xFB) ++#define REG_SCL_HVSP1_7E_L (REG_SCL_HVSP1_BASE + 0xFC) ++#define REG_SCL_HVSP1_7E_H (REG_SCL_HVSP1_BASE + 0xFD) ++#define REG_SCL_HVSP1_7F_L (REG_SCL_HVSP1_BASE + 0xFE) ++#define REG_SCL_HVSP1_7F_H (REG_SCL_HVSP1_BASE + 0xFF) ++ ++#define REG_SCL_HVSP2_00_L (REG_SCL_HVSP2_BASE + 0x00) ++#define REG_SCL_HVSP2_00_H (REG_SCL_HVSP2_BASE + 0x01) ++#define REG_SCL_HVSP2_01_L (REG_SCL_HVSP2_BASE + 0x02) ++#define REG_SCL_HVSP2_01_H (REG_SCL_HVSP2_BASE + 0x03) ++#define REG_SCL_HVSP2_02_L (REG_SCL_HVSP2_BASE + 0x04) ++#define REG_SCL_HVSP2_02_H (REG_SCL_HVSP2_BASE + 0x05) ++#define REG_SCL_HVSP2_03_L (REG_SCL_HVSP2_BASE + 0x06) ++#define REG_SCL_HVSP2_03_H (REG_SCL_HVSP2_BASE + 0x07) ++#define REG_SCL_HVSP2_04_L (REG_SCL_HVSP2_BASE + 0x08) ++#define REG_SCL_HVSP2_04_H (REG_SCL_HVSP2_BASE + 0x09) ++#define REG_SCL_HVSP2_05_L (REG_SCL_HVSP2_BASE + 0x0A) ++#define REG_SCL_HVSP2_05_H (REG_SCL_HVSP2_BASE + 0x0B) ++#define REG_SCL_HVSP2_06_L (REG_SCL_HVSP2_BASE + 0x0C) ++#define REG_SCL_HVSP2_06_H (REG_SCL_HVSP2_BASE + 0x0D) ++#define REG_SCL_HVSP2_07_L (REG_SCL_HVSP2_BASE + 0x0E) ++#define REG_SCL_HVSP2_07_H (REG_SCL_HVSP2_BASE + 0x0F) ++#define REG_SCL_HVSP2_08_L (REG_SCL_HVSP2_BASE + 0x10) ++#define REG_SCL_HVSP2_08_H (REG_SCL_HVSP2_BASE + 0x11) ++#define REG_SCL_HVSP2_09_L (REG_SCL_HVSP2_BASE + 0x12) ++#define REG_SCL_HVSP2_09_H (REG_SCL_HVSP2_BASE + 0x13) ++#define REG_SCL_HVSP2_0A_L (REG_SCL_HVSP2_BASE + 0x14) ++#define REG_SCL_HVSP2_0A_H (REG_SCL_HVSP2_BASE + 0x15) ++#define REG_SCL_HVSP2_0B_L (REG_SCL_HVSP2_BASE + 0x16) ++#define REG_SCL_HVSP2_0B_H (REG_SCL_HVSP2_BASE + 0x17) ++#define REG_SCL_HVSP2_0C_L (REG_SCL_HVSP2_BASE + 0x18) ++#define REG_SCL_HVSP2_0C_H (REG_SCL_HVSP2_BASE + 0x19) ++#define REG_SCL_HVSP2_0D_L (REG_SCL_HVSP2_BASE + 0x1A) ++#define REG_SCL_HVSP2_0D_H (REG_SCL_HVSP2_BASE + 0x1B) ++#define REG_SCL_HVSP2_0E_L (REG_SCL_HVSP2_BASE + 0x1C) ++#define REG_SCL_HVSP2_0E_H (REG_SCL_HVSP2_BASE + 0x1D) ++#define REG_SCL_HVSP2_0F_L (REG_SCL_HVSP2_BASE + 0x1E) ++#define REG_SCL_HVSP2_0F_H (REG_SCL_HVSP2_BASE + 0x1F) ++#define REG_SCL_HVSP2_10_L (REG_SCL_HVSP2_BASE + 0x20) ++#define REG_SCL_HVSP2_10_H (REG_SCL_HVSP2_BASE + 0x21) ++#define REG_SCL_HVSP2_11_L (REG_SCL_HVSP2_BASE + 0x22) ++#define REG_SCL_HVSP2_11_H (REG_SCL_HVSP2_BASE + 0x23) ++#define REG_SCL_HVSP2_12_L (REG_SCL_HVSP2_BASE + 0x24) ++#define REG_SCL_HVSP2_12_H (REG_SCL_HVSP2_BASE + 0x25) ++#define REG_SCL_HVSP2_13_L (REG_SCL_HVSP2_BASE + 0x26) ++#define REG_SCL_HVSP2_13_H (REG_SCL_HVSP2_BASE + 0x27) ++#define REG_SCL_HVSP2_14_L (REG_SCL_HVSP2_BASE + 0x28) ++#define REG_SCL_HVSP2_14_H (REG_SCL_HVSP2_BASE + 0x29) ++#define REG_SCL_HVSP2_15_L (REG_SCL_HVSP2_BASE + 0x2A) ++#define REG_SCL_HVSP2_15_H (REG_SCL_HVSP2_BASE + 0x2B) ++#define REG_SCL_HVSP2_16_L (REG_SCL_HVSP2_BASE + 0x2C) ++#define REG_SCL_HVSP2_16_H (REG_SCL_HVSP2_BASE + 0x2D) ++#define REG_SCL_HVSP2_17_L (REG_SCL_HVSP2_BASE + 0x2E) ++#define REG_SCL_HVSP2_17_H (REG_SCL_HVSP2_BASE + 0x2F) ++#define REG_SCL_HVSP2_18_L (REG_SCL_HVSP2_BASE + 0x30) ++#define REG_SCL_HVSP2_18_H (REG_SCL_HVSP2_BASE + 0x31) ++#define REG_SCL_HVSP2_19_L (REG_SCL_HVSP2_BASE + 0x32) ++#define REG_SCL_HVSP2_19_H (REG_SCL_HVSP2_BASE + 0x33) ++#define REG_SCL_HVSP2_1A_L (REG_SCL_HVSP2_BASE + 0x34) ++#define REG_SCL_HVSP2_1A_H (REG_SCL_HVSP2_BASE + 0x35) ++#define REG_SCL_HVSP2_1B_L (REG_SCL_HVSP2_BASE + 0x36) ++#define REG_SCL_HVSP2_1B_H (REG_SCL_HVSP2_BASE + 0x37) ++#define REG_SCL_HVSP2_1C_L (REG_SCL_HVSP2_BASE + 0x38) ++#define REG_SCL_HVSP2_1C_H (REG_SCL_HVSP2_BASE + 0x39) ++#define REG_SCL_HVSP2_1D_L (REG_SCL_HVSP2_BASE + 0x3A) ++#define REG_SCL_HVSP2_1D_H (REG_SCL_HVSP2_BASE + 0x3B) ++#define REG_SCL_HVSP2_1E_L (REG_SCL_HVSP2_BASE + 0x3C) ++#define REG_SCL_HVSP2_1E_H (REG_SCL_HVSP2_BASE + 0x3D) ++#define REG_SCL_HVSP2_1F_L (REG_SCL_HVSP2_BASE + 0x3E) ++#define REG_SCL_HVSP2_1F_H (REG_SCL_HVSP2_BASE + 0x3F) ++#define REG_SCL_HVSP2_20_L (REG_SCL_HVSP2_BASE + 0x40) ++#define REG_SCL_HVSP2_20_H (REG_SCL_HVSP2_BASE + 0x41) ++#define REG_SCL_HVSP2_21_L (REG_SCL_HVSP2_BASE + 0x42) ++#define REG_SCL_HVSP2_21_H (REG_SCL_HVSP2_BASE + 0x43) ++#define REG_SCL_HVSP2_22_L (REG_SCL_HVSP2_BASE + 0x44) ++#define REG_SCL_HVSP2_22_H (REG_SCL_HVSP2_BASE + 0x45) ++#define REG_SCL_HVSP2_23_L (REG_SCL_HVSP2_BASE + 0x46) ++#define REG_SCL_HVSP2_23_H (REG_SCL_HVSP2_BASE + 0x47) ++#define REG_SCL_HVSP2_24_L (REG_SCL_HVSP2_BASE + 0x48) ++#define REG_SCL_HVSP2_24_H (REG_SCL_HVSP2_BASE + 0x49) ++#define REG_SCL_HVSP2_25_L (REG_SCL_HVSP2_BASE + 0x4A) ++#define REG_SCL_HVSP2_25_H (REG_SCL_HVSP2_BASE + 0x4B) ++#define REG_SCL_HVSP2_26_L (REG_SCL_HVSP2_BASE + 0x4C) ++#define REG_SCL_HVSP2_26_H (REG_SCL_HVSP2_BASE + 0x4D) ++#define REG_SCL_HVSP2_27_L (REG_SCL_HVSP2_BASE + 0x4E) ++#define REG_SCL_HVSP2_27_H (REG_SCL_HVSP2_BASE + 0x4F) ++#define REG_SCL_HVSP2_28_L (REG_SCL_HVSP2_BASE + 0x50) ++#define REG_SCL_HVSP2_28_H (REG_SCL_HVSP2_BASE + 0x51) ++#define REG_SCL_HVSP2_29_L (REG_SCL_HVSP2_BASE + 0x52) ++#define REG_SCL_HVSP2_29_H (REG_SCL_HVSP2_BASE + 0x53) ++#define REG_SCL_HVSP2_2A_L (REG_SCL_HVSP2_BASE + 0x54) ++#define REG_SCL_HVSP2_2A_H (REG_SCL_HVSP2_BASE + 0x55) ++#define REG_SCL_HVSP2_2B_L (REG_SCL_HVSP2_BASE + 0x56) ++#define REG_SCL_HVSP2_2B_H (REG_SCL_HVSP2_BASE + 0x57) ++#define REG_SCL_HVSP2_2C_L (REG_SCL_HVSP2_BASE + 0x58) ++#define REG_SCL_HVSP2_2C_H (REG_SCL_HVSP2_BASE + 0x59) ++#define REG_SCL_HVSP2_2D_L (REG_SCL_HVSP2_BASE + 0x5A) ++#define REG_SCL_HVSP2_2D_H (REG_SCL_HVSP2_BASE + 0x5B) ++#define REG_SCL_HVSP2_2E_L (REG_SCL_HVSP2_BASE + 0x5C) ++#define REG_SCL_HVSP2_2E_H (REG_SCL_HVSP2_BASE + 0x5D) ++#define REG_SCL_HVSP2_2F_L (REG_SCL_HVSP2_BASE + 0x5E) ++#define REG_SCL_HVSP2_2F_H (REG_SCL_HVSP2_BASE + 0x5F) ++#define REG_SCL_HVSP2_30_L (REG_SCL_HVSP2_BASE + 0x60) ++#define REG_SCL_HVSP2_30_H (REG_SCL_HVSP2_BASE + 0x61) ++#define REG_SCL_HVSP2_31_L (REG_SCL_HVSP2_BASE + 0x62) ++#define REG_SCL_HVSP2_31_H (REG_SCL_HVSP2_BASE + 0x63) ++#define REG_SCL_HVSP2_32_L (REG_SCL_HVSP2_BASE + 0x64) ++#define REG_SCL_HVSP2_32_H (REG_SCL_HVSP2_BASE + 0x65) ++#define REG_SCL_HVSP2_33_L (REG_SCL_HVSP2_BASE + 0x66) ++#define REG_SCL_HVSP2_33_H (REG_SCL_HVSP2_BASE + 0x67) ++#define REG_SCL_HVSP2_34_L (REG_SCL_HVSP2_BASE + 0x68) ++#define REG_SCL_HVSP2_34_H (REG_SCL_HVSP2_BASE + 0x69) ++#define REG_SCL_HVSP2_35_L (REG_SCL_HVSP2_BASE + 0x6A) ++#define REG_SCL_HVSP2_35_H (REG_SCL_HVSP2_BASE + 0x6B) ++#define REG_SCL_HVSP2_36_L (REG_SCL_HVSP2_BASE + 0x6C) ++#define REG_SCL_HVSP2_36_H (REG_SCL_HVSP2_BASE + 0x6D) ++#define REG_SCL_HVSP2_37_L (REG_SCL_HVSP2_BASE + 0x6E) ++#define REG_SCL_HVSP2_37_H (REG_SCL_HVSP2_BASE + 0x6F) ++#define REG_SCL_HVSP2_38_L (REG_SCL_HVSP2_BASE + 0x70) ++#define REG_SCL_HVSP2_38_H (REG_SCL_HVSP2_BASE + 0x71) ++#define REG_SCL_HVSP2_39_L (REG_SCL_HVSP2_BASE + 0x72) ++#define REG_SCL_HVSP2_39_H (REG_SCL_HVSP2_BASE + 0x73) ++#define REG_SCL_HVSP2_3A_L (REG_SCL_HVSP2_BASE + 0x74) ++#define REG_SCL_HVSP2_3A_H (REG_SCL_HVSP2_BASE + 0x75) ++#define REG_SCL_HVSP2_3B_L (REG_SCL_HVSP2_BASE + 0x76) ++#define REG_SCL_HVSP2_3B_H (REG_SCL_HVSP2_BASE + 0x77) ++#define REG_SCL_HVSP2_3C_L (REG_SCL_HVSP2_BASE + 0x78) ++#define REG_SCL_HVSP2_3C_H (REG_SCL_HVSP2_BASE + 0x79) ++#define REG_SCL_HVSP2_3D_L (REG_SCL_HVSP2_BASE + 0x7A) ++#define REG_SCL_HVSP2_3D_H (REG_SCL_HVSP2_BASE + 0x7B) ++#define REG_SCL_HVSP2_3E_L (REG_SCL_HVSP2_BASE + 0x7C) ++#define REG_SCL_HVSP2_3E_H (REG_SCL_HVSP2_BASE + 0x7D) ++#define REG_SCL_HVSP2_3F_L (REG_SCL_HVSP2_BASE + 0x7E) ++#define REG_SCL_HVSP2_3F_H (REG_SCL_HVSP2_BASE + 0x7F) ++#define REG_SCL_HVSP2_40_L (REG_SCL_HVSP2_BASE + 0x80) ++#define REG_SCL_HVSP2_40_H (REG_SCL_HVSP2_BASE + 0x81) ++#define REG_SCL_HVSP2_41_L (REG_SCL_HVSP2_BASE + 0x82) ++#define REG_SCL_HVSP2_41_H (REG_SCL_HVSP2_BASE + 0x83) ++#define REG_SCL_HVSP2_42_L (REG_SCL_HVSP2_BASE + 0x84) ++#define REG_SCL_HVSP2_42_H (REG_SCL_HVSP2_BASE + 0x85) ++#define REG_SCL_HVSP2_43_L (REG_SCL_HVSP2_BASE + 0x86) ++#define REG_SCL_HVSP2_43_H (REG_SCL_HVSP2_BASE + 0x87) ++#define REG_SCL_HVSP2_44_L (REG_SCL_HVSP2_BASE + 0x88) ++#define REG_SCL_HVSP2_44_H (REG_SCL_HVSP2_BASE + 0x89) ++#define REG_SCL_HVSP2_45_L (REG_SCL_HVSP2_BASE + 0x8A) ++#define REG_SCL_HVSP2_45_H (REG_SCL_HVSP2_BASE + 0x8B) ++#define REG_SCL_HVSP2_46_L (REG_SCL_HVSP2_BASE + 0x8C) ++#define REG_SCL_HVSP2_46_H (REG_SCL_HVSP2_BASE + 0x8D) ++#define REG_SCL_HVSP2_47_L (REG_SCL_HVSP2_BASE + 0x8E) ++#define REG_SCL_HVSP2_47_H (REG_SCL_HVSP2_BASE + 0x8F) ++#define REG_SCL_HVSP2_48_L (REG_SCL_HVSP2_BASE + 0x90) ++#define REG_SCL_HVSP2_48_H (REG_SCL_HVSP2_BASE + 0x91) ++#define REG_SCL_HVSP2_49_L (REG_SCL_HVSP2_BASE + 0x92) ++#define REG_SCL_HVSP2_49_H (REG_SCL_HVSP2_BASE + 0x93) ++#define REG_SCL_HVSP2_4A_L (REG_SCL_HVSP2_BASE + 0x94) ++#define REG_SCL_HVSP2_4A_H (REG_SCL_HVSP2_BASE + 0x95) ++#define REG_SCL_HVSP2_4B_L (REG_SCL_HVSP2_BASE + 0x96) ++#define REG_SCL_HVSP2_4B_H (REG_SCL_HVSP2_BASE + 0x97) ++#define REG_SCL_HVSP2_4C_L (REG_SCL_HVSP2_BASE + 0x98) ++#define REG_SCL_HVSP2_4C_H (REG_SCL_HVSP2_BASE + 0x99) ++#define REG_SCL_HVSP2_4D_L (REG_SCL_HVSP2_BASE + 0x9A) ++#define REG_SCL_HVSP2_4D_H (REG_SCL_HVSP2_BASE + 0x9B) ++#define REG_SCL_HVSP2_4E_L (REG_SCL_HVSP2_BASE + 0x9C) ++#define REG_SCL_HVSP2_4E_H (REG_SCL_HVSP2_BASE + 0x9D) ++#define REG_SCL_HVSP2_4F_L (REG_SCL_HVSP2_BASE + 0x9E) ++#define REG_SCL_HVSP2_4F_H (REG_SCL_HVSP2_BASE + 0x9F) ++#define REG_SCL_HVSP2_50_L (REG_SCL_HVSP2_BASE + 0xA0) ++#define REG_SCL_HVSP2_50_H (REG_SCL_HVSP2_BASE + 0xA1) ++#define REG_SCL_HVSP2_51_L (REG_SCL_HVSP2_BASE + 0xA2) ++#define REG_SCL_HVSP2_51_H (REG_SCL_HVSP2_BASE + 0xA3) ++#define REG_SCL_HVSP2_52_L (REG_SCL_HVSP2_BASE + 0xA4) ++#define REG_SCL_HVSP2_52_H (REG_SCL_HVSP2_BASE + 0xA5) ++#define REG_SCL_HVSP2_53_L (REG_SCL_HVSP2_BASE + 0xA6) ++#define REG_SCL_HVSP2_53_H (REG_SCL_HVSP2_BASE + 0xA7) ++#define REG_SCL_HVSP2_54_L (REG_SCL_HVSP2_BASE + 0xA8) ++#define REG_SCL_HVSP2_54_H (REG_SCL_HVSP2_BASE + 0xA9) ++#define REG_SCL_HVSP2_55_L (REG_SCL_HVSP2_BASE + 0xAA) ++#define REG_SCL_HVSP2_55_H (REG_SCL_HVSP2_BASE + 0xAB) ++#define REG_SCL_HVSP2_56_L (REG_SCL_HVSP2_BASE + 0xAC) ++#define REG_SCL_HVSP2_56_H (REG_SCL_HVSP2_BASE + 0xAD) ++#define REG_SCL_HVSP2_57_L (REG_SCL_HVSP2_BASE + 0xAE) ++#define REG_SCL_HVSP2_57_H (REG_SCL_HVSP2_BASE + 0xAF) ++#define REG_SCL_HVSP2_58_L (REG_SCL_HVSP2_BASE + 0xB0) ++#define REG_SCL_HVSP2_58_H (REG_SCL_HVSP2_BASE + 0xB1) ++#define REG_SCL_HVSP2_59_L (REG_SCL_HVSP2_BASE + 0xB2) ++#define REG_SCL_HVSP2_59_H (REG_SCL_HVSP2_BASE + 0xB3) ++#define REG_SCL_HVSP2_5A_L (REG_SCL_HVSP2_BASE + 0xB4) ++#define REG_SCL_HVSP2_5A_H (REG_SCL_HVSP2_BASE + 0xB5) ++#define REG_SCL_HVSP2_5B_L (REG_SCL_HVSP2_BASE + 0xB6) ++#define REG_SCL_HVSP2_5B_H (REG_SCL_HVSP2_BASE + 0xB7) ++#define REG_SCL_HVSP2_5C_L (REG_SCL_HVSP2_BASE + 0xB8) ++#define REG_SCL_HVSP2_5C_H (REG_SCL_HVSP2_BASE + 0xB9) ++#define REG_SCL_HVSP2_5D_L (REG_SCL_HVSP2_BASE + 0xBA) ++#define REG_SCL_HVSP2_5D_H (REG_SCL_HVSP2_BASE + 0xBB) ++#define REG_SCL_HVSP2_5E_L (REG_SCL_HVSP2_BASE + 0xBC) ++#define REG_SCL_HVSP2_5E_H (REG_SCL_HVSP2_BASE + 0xBD) ++#define REG_SCL_HVSP2_5F_L (REG_SCL_HVSP2_BASE + 0xBE) ++#define REG_SCL_HVSP2_5F_H (REG_SCL_HVSP2_BASE + 0xBF) ++#define REG_SCL_HVSP2_60_L (REG_SCL_HVSP2_BASE + 0xC0) ++#define REG_SCL_HVSP2_60_H (REG_SCL_HVSP2_BASE + 0xC1) ++#define REG_SCL_HVSP2_61_L (REG_SCL_HVSP2_BASE + 0xC2) ++#define REG_SCL_HVSP2_61_H (REG_SCL_HVSP2_BASE + 0xC3) ++#define REG_SCL_HVSP2_62_L (REG_SCL_HVSP2_BASE + 0xC4) ++#define REG_SCL_HVSP2_62_H (REG_SCL_HVSP2_BASE + 0xC5) ++#define REG_SCL_HVSP2_63_L (REG_SCL_HVSP2_BASE + 0xC6) ++#define REG_SCL_HVSP2_63_H (REG_SCL_HVSP2_BASE + 0xC7) ++#define REG_SCL_HVSP2_64_L (REG_SCL_HVSP2_BASE + 0xC8) ++#define REG_SCL_HVSP2_64_H (REG_SCL_HVSP2_BASE + 0xC9) ++#define REG_SCL_HVSP2_65_L (REG_SCL_HVSP2_BASE + 0xCA) ++#define REG_SCL_HVSP2_65_H (REG_SCL_HVSP2_BASE + 0xCB) ++#define REG_SCL_HVSP2_66_L (REG_SCL_HVSP2_BASE + 0xCC) ++#define REG_SCL_HVSP2_66_H (REG_SCL_HVSP2_BASE + 0xCD) ++#define REG_SCL_HVSP2_67_L (REG_SCL_HVSP2_BASE + 0xCE) ++#define REG_SCL_HVSP2_67_H (REG_SCL_HVSP2_BASE + 0xCF) ++#define REG_SCL_HVSP2_68_L (REG_SCL_HVSP2_BASE + 0xD0) ++#define REG_SCL_HVSP2_68_H (REG_SCL_HVSP2_BASE + 0xD1) ++#define REG_SCL_HVSP2_69_L (REG_SCL_HVSP2_BASE + 0xD2) ++#define REG_SCL_HVSP2_69_H (REG_SCL_HVSP2_BASE + 0xD3) ++#define REG_SCL_HVSP2_6A_L (REG_SCL_HVSP2_BASE + 0xD4) ++#define REG_SCL_HVSP2_6A_H (REG_SCL_HVSP2_BASE + 0xD5) ++#define REG_SCL_HVSP2_6B_L (REG_SCL_HVSP2_BASE + 0xD6) ++#define REG_SCL_HVSP2_6B_H (REG_SCL_HVSP2_BASE + 0xD7) ++#define REG_SCL_HVSP2_6C_L (REG_SCL_HVSP2_BASE + 0xD8) ++#define REG_SCL_HVSP2_6C_H (REG_SCL_HVSP2_BASE + 0xD9) ++#define REG_SCL_HVSP2_6D_L (REG_SCL_HVSP2_BASE + 0xDA) ++#define REG_SCL_HVSP2_6D_H (REG_SCL_HVSP2_BASE + 0xDB) ++#define REG_SCL_HVSP2_6E_L (REG_SCL_HVSP2_BASE + 0xDC) ++#define REG_SCL_HVSP2_6E_H (REG_SCL_HVSP2_BASE + 0xDD) ++#define REG_SCL_HVSP2_6F_L (REG_SCL_HVSP2_BASE + 0xDE) ++#define REG_SCL_HVSP2_6F_H (REG_SCL_HVSP2_BASE + 0xDF) ++#define REG_SCL_HVSP2_70_L (REG_SCL_HVSP2_BASE + 0xE0) ++#define REG_SCL_HVSP2_70_H (REG_SCL_HVSP2_BASE + 0xE1) ++#define REG_SCL_HVSP2_71_L (REG_SCL_HVSP2_BASE + 0xE2) ++#define REG_SCL_HVSP2_71_H (REG_SCL_HVSP2_BASE + 0xE3) ++#define REG_SCL_HVSP2_72_L (REG_SCL_HVSP2_BASE + 0xE4) ++#define REG_SCL_HVSP2_72_H (REG_SCL_HVSP2_BASE + 0xE5) ++#define REG_SCL_HVSP2_73_L (REG_SCL_HVSP2_BASE + 0xE6) ++#define REG_SCL_HVSP2_73_H (REG_SCL_HVSP2_BASE + 0xE7) ++#define REG_SCL_HVSP2_74_L (REG_SCL_HVSP2_BASE + 0xE8) ++#define REG_SCL_HVSP2_74_H (REG_SCL_HVSP2_BASE + 0xE9) ++#define REG_SCL_HVSP2_75_L (REG_SCL_HVSP2_BASE + 0xEA) ++#define REG_SCL_HVSP2_75_H (REG_SCL_HVSP2_BASE + 0xEB) ++#define REG_SCL_HVSP2_76_L (REG_SCL_HVSP2_BASE + 0xEC) ++#define REG_SCL_HVSP2_76_H (REG_SCL_HVSP2_BASE + 0xED) ++#define REG_SCL_HVSP2_77_L (REG_SCL_HVSP2_BASE + 0xEE) ++#define REG_SCL_HVSP2_77_H (REG_SCL_HVSP2_BASE + 0xEF) ++#define REG_SCL_HVSP2_78_L (REG_SCL_HVSP2_BASE + 0xF0) ++#define REG_SCL_HVSP2_78_H (REG_SCL_HVSP2_BASE + 0xF1) ++#define REG_SCL_HVSP2_79_L (REG_SCL_HVSP2_BASE + 0xF2) ++#define REG_SCL_HVSP2_79_H (REG_SCL_HVSP2_BASE + 0xF3) ++#define REG_SCL_HVSP2_7A_L (REG_SCL_HVSP2_BASE + 0xF4) ++#define REG_SCL_HVSP2_7A_H (REG_SCL_HVSP2_BASE + 0xF5) ++#define REG_SCL_HVSP2_7B_L (REG_SCL_HVSP2_BASE + 0xF6) ++#define REG_SCL_HVSP2_7B_H (REG_SCL_HVSP2_BASE + 0xF7) ++#define REG_SCL_HVSP2_7C_L (REG_SCL_HVSP2_BASE + 0xF8) ++#define REG_SCL_HVSP2_7C_H (REG_SCL_HVSP2_BASE + 0xF9) ++#define REG_SCL_HVSP2_7D_L (REG_SCL_HVSP2_BASE + 0xFA) ++#define REG_SCL_HVSP2_7D_H (REG_SCL_HVSP2_BASE + 0xFB) ++#define REG_SCL_HVSP2_7E_L (REG_SCL_HVSP2_BASE + 0xFC) ++#define REG_SCL_HVSP2_7E_H (REG_SCL_HVSP2_BASE + 0xFD) ++#define REG_SCL_HVSP2_7F_L (REG_SCL_HVSP2_BASE + 0xFE) ++#define REG_SCL_HVSP2_7F_H (REG_SCL_HVSP2_BASE + 0xFF) ++ ++#define REG_SCL_LDC_00_L (REG_SCL_LDC_BASE + 0x00) ++#define REG_SCL_LDC_00_H (REG_SCL_LDC_BASE + 0x01) ++#define REG_SCL_LDC_01_L (REG_SCL_LDC_BASE + 0x02) ++#define REG_SCL_LDC_01_H (REG_SCL_LDC_BASE + 0x03) ++#define REG_SCL_LDC_02_L (REG_SCL_LDC_BASE + 0x04) ++#define REG_SCL_LDC_02_H (REG_SCL_LDC_BASE + 0x05) ++#define REG_SCL_LDC_03_L (REG_SCL_LDC_BASE + 0x06) ++#define REG_SCL_LDC_03_H (REG_SCL_LDC_BASE + 0x07) ++#define REG_SCL_LDC_04_L (REG_SCL_LDC_BASE + 0x08) ++#define REG_SCL_LDC_04_H (REG_SCL_LDC_BASE + 0x09) ++#define REG_SCL_LDC_05_L (REG_SCL_LDC_BASE + 0x0A) ++#define REG_SCL_LDC_05_H (REG_SCL_LDC_BASE + 0x0B) ++#define REG_SCL_LDC_06_L (REG_SCL_LDC_BASE + 0x0C) ++#define REG_SCL_LDC_06_H (REG_SCL_LDC_BASE + 0x0D) ++#define REG_SCL_LDC_07_L (REG_SCL_LDC_BASE + 0x0E) ++#define REG_SCL_LDC_07_H (REG_SCL_LDC_BASE + 0x0F) ++#define REG_SCL_LDC_08_L (REG_SCL_LDC_BASE + 0x10) ++#define REG_SCL_LDC_08_H (REG_SCL_LDC_BASE + 0x11) ++#define REG_SCL_LDC_09_L (REG_SCL_LDC_BASE + 0x12) ++#define REG_SCL_LDC_09_H (REG_SCL_LDC_BASE + 0x13) ++#define REG_SCL_LDC_0A_L (REG_SCL_LDC_BASE + 0x14) ++#define REG_SCL_LDC_0A_H (REG_SCL_LDC_BASE + 0x15) ++#define REG_SCL_LDC_0B_L (REG_SCL_LDC_BASE + 0x16) ++#define REG_SCL_LDC_0B_H (REG_SCL_LDC_BASE + 0x17) ++#define REG_SCL_LDC_0C_L (REG_SCL_LDC_BASE + 0x18) ++#define REG_SCL_LDC_0C_H (REG_SCL_LDC_BASE + 0x19) ++#define REG_SCL_LDC_0D_L (REG_SCL_LDC_BASE + 0x1A) ++#define REG_SCL_LDC_0D_H (REG_SCL_LDC_BASE + 0x1B) ++#define REG_SCL_LDC_0E_L (REG_SCL_LDC_BASE + 0x1C) ++#define REG_SCL_LDC_0E_H (REG_SCL_LDC_BASE + 0x1D) ++#define REG_SCL_LDC_0F_L (REG_SCL_LDC_BASE + 0x1E) ++#define REG_SCL_LDC_0F_H (REG_SCL_LDC_BASE + 0x1F) ++#define REG_SCL_LDC_10_L (REG_SCL_LDC_BASE + 0x20) ++#define REG_SCL_LDC_10_H (REG_SCL_LDC_BASE + 0x21) ++#define REG_SCL_LDC_11_L (REG_SCL_LDC_BASE + 0x22) ++#define REG_SCL_LDC_11_H (REG_SCL_LDC_BASE + 0x23) ++#define REG_SCL_LDC_12_L (REG_SCL_LDC_BASE + 0x24) ++#define REG_SCL_LDC_12_H (REG_SCL_LDC_BASE + 0x25) ++#define REG_SCL_LDC_13_L (REG_SCL_LDC_BASE + 0x26) ++#define REG_SCL_LDC_13_H (REG_SCL_LDC_BASE + 0x27) ++#define REG_SCL_LDC_14_L (REG_SCL_LDC_BASE + 0x28) ++#define REG_SCL_LDC_14_H (REG_SCL_LDC_BASE + 0x29) ++#define REG_SCL_LDC_15_L (REG_SCL_LDC_BASE + 0x2A) ++#define REG_SCL_LDC_15_H (REG_SCL_LDC_BASE + 0x2B) ++#define REG_SCL_LDC_16_L (REG_SCL_LDC_BASE + 0x2C) ++#define REG_SCL_LDC_16_H (REG_SCL_LDC_BASE + 0x2D) ++#define REG_SCL_LDC_17_L (REG_SCL_LDC_BASE + 0x2E) ++#define REG_SCL_LDC_17_H (REG_SCL_LDC_BASE + 0x2F) ++#define REG_SCL_LDC_18_L (REG_SCL_LDC_BASE + 0x30) ++#define REG_SCL_LDC_18_H (REG_SCL_LDC_BASE + 0x31) ++#define REG_SCL_LDC_19_L (REG_SCL_LDC_BASE + 0x32) ++#define REG_SCL_LDC_19_H (REG_SCL_LDC_BASE + 0x33) ++#define REG_SCL_LDC_1A_L (REG_SCL_LDC_BASE + 0x34) ++#define REG_SCL_LDC_1A_H (REG_SCL_LDC_BASE + 0x35) ++#define REG_SCL_LDC_1B_L (REG_SCL_LDC_BASE + 0x36) ++#define REG_SCL_LDC_1B_H (REG_SCL_LDC_BASE + 0x37) ++#define REG_SCL_LDC_1C_L (REG_SCL_LDC_BASE + 0x38) ++#define REG_SCL_LDC_1C_H (REG_SCL_LDC_BASE + 0x39) ++#define REG_SCL_LDC_1D_L (REG_SCL_LDC_BASE + 0x3A) ++#define REG_SCL_LDC_1D_H (REG_SCL_LDC_BASE + 0x3B) ++#define REG_SCL_LDC_1E_L (REG_SCL_LDC_BASE + 0x3C) ++#define REG_SCL_LDC_1E_H (REG_SCL_LDC_BASE + 0x3D) ++#define REG_SCL_LDC_1F_L (REG_SCL_LDC_BASE + 0x3E) ++#define REG_SCL_LDC_1F_H (REG_SCL_LDC_BASE + 0x3F) ++#define REG_SCL_LDC_20_L (REG_SCL_LDC_BASE + 0x40) ++#define REG_SCL_LDC_20_H (REG_SCL_LDC_BASE + 0x41) ++#define REG_SCL_LDC_21_L (REG_SCL_LDC_BASE + 0x42) ++#define REG_SCL_LDC_21_H (REG_SCL_LDC_BASE + 0x43) ++#define REG_SCL_LDC_22_L (REG_SCL_LDC_BASE + 0x44) ++#define REG_SCL_LDC_22_H (REG_SCL_LDC_BASE + 0x45) ++#define REG_SCL_LDC_23_L (REG_SCL_LDC_BASE + 0x46) ++#define REG_SCL_LDC_23_H (REG_SCL_LDC_BASE + 0x47) ++#define REG_SCL_LDC_24_L (REG_SCL_LDC_BASE + 0x48) ++#define REG_SCL_LDC_24_H (REG_SCL_LDC_BASE + 0x49) ++#define REG_SCL_LDC_25_L (REG_SCL_LDC_BASE + 0x4A) ++#define REG_SCL_LDC_25_H (REG_SCL_LDC_BASE + 0x4B) ++#define REG_SCL_LDC_26_L (REG_SCL_LDC_BASE + 0x4C) ++#define REG_SCL_LDC_26_H (REG_SCL_LDC_BASE + 0x4D) ++#define REG_SCL_LDC_27_L (REG_SCL_LDC_BASE + 0x4E) ++#define REG_SCL_LDC_27_H (REG_SCL_LDC_BASE + 0x4F) ++#define REG_SCL_LDC_28_L (REG_SCL_LDC_BASE + 0x50) ++#define REG_SCL_LDC_28_H (REG_SCL_LDC_BASE + 0x51) ++#define REG_SCL_LDC_29_L (REG_SCL_LDC_BASE + 0x52) ++#define REG_SCL_LDC_29_H (REG_SCL_LDC_BASE + 0x53) ++#define REG_SCL_LDC_2A_L (REG_SCL_LDC_BASE + 0x54) ++#define REG_SCL_LDC_2A_H (REG_SCL_LDC_BASE + 0x55) ++#define REG_SCL_LDC_2B_L (REG_SCL_LDC_BASE + 0x56) ++#define REG_SCL_LDC_2B_H (REG_SCL_LDC_BASE + 0x57) ++#define REG_SCL_LDC_2C_L (REG_SCL_LDC_BASE + 0x58) ++#define REG_SCL_LDC_2C_H (REG_SCL_LDC_BASE + 0x59) ++#define REG_SCL_LDC_2D_L (REG_SCL_LDC_BASE + 0x5A) ++#define REG_SCL_LDC_2D_H (REG_SCL_LDC_BASE + 0x5B) ++#define REG_SCL_LDC_2E_L (REG_SCL_LDC_BASE + 0x5C) ++#define REG_SCL_LDC_2E_H (REG_SCL_LDC_BASE + 0x5D) ++#define REG_SCL_LDC_2F_L (REG_SCL_LDC_BASE + 0x5E) ++#define REG_SCL_LDC_2F_H (REG_SCL_LDC_BASE + 0x5F) ++#define REG_SCL_LDC_30_L (REG_SCL_LDC_BASE + 0x60) ++#define REG_SCL_LDC_30_H (REG_SCL_LDC_BASE + 0x61) ++#define REG_SCL_LDC_31_L (REG_SCL_LDC_BASE + 0x62) ++#define REG_SCL_LDC_31_H (REG_SCL_LDC_BASE + 0x63) ++#define REG_SCL_LDC_32_L (REG_SCL_LDC_BASE + 0x64) ++#define REG_SCL_LDC_32_H (REG_SCL_LDC_BASE + 0x65) ++#define REG_SCL_LDC_33_L (REG_SCL_LDC_BASE + 0x66) ++#define REG_SCL_LDC_33_H (REG_SCL_LDC_BASE + 0x67) ++#define REG_SCL_LDC_34_L (REG_SCL_LDC_BASE + 0x68) ++#define REG_SCL_LDC_34_H (REG_SCL_LDC_BASE + 0x69) ++#define REG_SCL_LDC_35_L (REG_SCL_LDC_BASE + 0x6A) ++#define REG_SCL_LDC_35_H (REG_SCL_LDC_BASE + 0x6B) ++#define REG_SCL_LDC_36_L (REG_SCL_LDC_BASE + 0x6C) ++#define REG_SCL_LDC_36_H (REG_SCL_LDC_BASE + 0x6D) ++#define REG_SCL_LDC_37_L (REG_SCL_LDC_BASE + 0x6E) ++#define REG_SCL_LDC_37_H (REG_SCL_LDC_BASE + 0x6F) ++#define REG_SCL_LDC_38_L (REG_SCL_LDC_BASE + 0x70) ++#define REG_SCL_LDC_38_H (REG_SCL_LDC_BASE + 0x71) ++#define REG_SCL_LDC_39_L (REG_SCL_LDC_BASE + 0x72) ++#define REG_SCL_LDC_39_H (REG_SCL_LDC_BASE + 0x73) ++#define REG_SCL_LDC_3A_L (REG_SCL_LDC_BASE + 0x74) ++#define REG_SCL_LDC_3A_H (REG_SCL_LDC_BASE + 0x75) ++#define REG_SCL_LDC_3B_L (REG_SCL_LDC_BASE + 0x76) ++#define REG_SCL_LDC_3B_H (REG_SCL_LDC_BASE + 0x77) ++#define REG_SCL_LDC_3C_L (REG_SCL_LDC_BASE + 0x78) ++#define REG_SCL_LDC_3C_H (REG_SCL_LDC_BASE + 0x79) ++#define REG_SCL_LDC_3D_L (REG_SCL_LDC_BASE + 0x7A) ++#define REG_SCL_LDC_3D_H (REG_SCL_LDC_BASE + 0x7B) ++#define REG_SCL_LDC_3E_L (REG_SCL_LDC_BASE + 0x7C) ++#define REG_SCL_LDC_3E_H (REG_SCL_LDC_BASE + 0x7D) ++#define REG_SCL_LDC_3F_L (REG_SCL_LDC_BASE + 0x7E) ++#define REG_SCL_LDC_3F_H (REG_SCL_LDC_BASE + 0x7F) ++#define REG_SCL_LDC_40_L (REG_SCL_LDC_BASE + 0x80) ++#define REG_SCL_LDC_40_H (REG_SCL_LDC_BASE + 0x81) ++#define REG_SCL_LDC_41_L (REG_SCL_LDC_BASE + 0x82) ++#define REG_SCL_LDC_41_H (REG_SCL_LDC_BASE + 0x83) ++#define REG_SCL_LDC_42_L (REG_SCL_LDC_BASE + 0x84) ++#define REG_SCL_LDC_42_H (REG_SCL_LDC_BASE + 0x85) ++#define REG_SCL_LDC_43_L (REG_SCL_LDC_BASE + 0x86) ++#define REG_SCL_LDC_43_H (REG_SCL_LDC_BASE + 0x87) ++#define REG_SCL_LDC_44_L (REG_SCL_LDC_BASE + 0x88) ++#define REG_SCL_LDC_44_H (REG_SCL_LDC_BASE + 0x89) ++#define REG_SCL_LDC_45_L (REG_SCL_LDC_BASE + 0x8A) ++#define REG_SCL_LDC_45_H (REG_SCL_LDC_BASE + 0x8B) ++#define REG_SCL_LDC_46_L (REG_SCL_LDC_BASE + 0x8C) ++#define REG_SCL_LDC_46_H (REG_SCL_LDC_BASE + 0x8D) ++#define REG_SCL_LDC_47_L (REG_SCL_LDC_BASE + 0x8E) ++#define REG_SCL_LDC_47_H (REG_SCL_LDC_BASE + 0x8F) ++#define REG_SCL_LDC_48_L (REG_SCL_LDC_BASE + 0x90) ++#define REG_SCL_LDC_48_H (REG_SCL_LDC_BASE + 0x91) ++#define REG_SCL_LDC_49_L (REG_SCL_LDC_BASE + 0x92) ++#define REG_SCL_LDC_49_H (REG_SCL_LDC_BASE + 0x93) ++#define REG_SCL_LDC_4A_L (REG_SCL_LDC_BASE + 0x94) ++#define REG_SCL_LDC_4A_H (REG_SCL_LDC_BASE + 0x95) ++#define REG_SCL_LDC_4B_L (REG_SCL_LDC_BASE + 0x96) ++#define REG_SCL_LDC_4B_H (REG_SCL_LDC_BASE + 0x97) ++#define REG_SCL_LDC_4C_L (REG_SCL_LDC_BASE + 0x98) ++#define REG_SCL_LDC_4C_H (REG_SCL_LDC_BASE + 0x99) ++#define REG_SCL_LDC_4D_L (REG_SCL_LDC_BASE + 0x9A) ++#define REG_SCL_LDC_4D_H (REG_SCL_LDC_BASE + 0x9B) ++#define REG_SCL_LDC_4E_L (REG_SCL_LDC_BASE + 0x9C) ++#define REG_SCL_LDC_4E_H (REG_SCL_LDC_BASE + 0x9D) ++#define REG_SCL_LDC_4F_L (REG_SCL_LDC_BASE + 0x9E) ++#define REG_SCL_LDC_4F_H (REG_SCL_LDC_BASE + 0x9F) ++#define REG_SCL_LDC_50_L (REG_SCL_LDC_BASE + 0xA0) ++#define REG_SCL_LDC_50_H (REG_SCL_LDC_BASE + 0xA1) ++#define REG_SCL_LDC_51_L (REG_SCL_LDC_BASE + 0xA2) ++#define REG_SCL_LDC_51_H (REG_SCL_LDC_BASE + 0xA3) ++#define REG_SCL_LDC_52_L (REG_SCL_LDC_BASE + 0xA4) ++#define REG_SCL_LDC_52_H (REG_SCL_LDC_BASE + 0xA5) ++#define REG_SCL_LDC_53_L (REG_SCL_LDC_BASE + 0xA6) ++#define REG_SCL_LDC_53_H (REG_SCL_LDC_BASE + 0xA7) ++#define REG_SCL_LDC_54_L (REG_SCL_LDC_BASE + 0xA8) ++#define REG_SCL_LDC_54_H (REG_SCL_LDC_BASE + 0xA9) ++#define REG_SCL_LDC_55_L (REG_SCL_LDC_BASE + 0xAA) ++#define REG_SCL_LDC_55_H (REG_SCL_LDC_BASE + 0xAB) ++#define REG_SCL_LDC_56_L (REG_SCL_LDC_BASE + 0xAC) ++#define REG_SCL_LDC_56_H (REG_SCL_LDC_BASE + 0xAD) ++#define REG_SCL_LDC_57_L (REG_SCL_LDC_BASE + 0xAE) ++#define REG_SCL_LDC_57_H (REG_SCL_LDC_BASE + 0xAF) ++#define REG_SCL_LDC_58_L (REG_SCL_LDC_BASE + 0xB0) ++#define REG_SCL_LDC_58_H (REG_SCL_LDC_BASE + 0xB1) ++#define REG_SCL_LDC_59_L (REG_SCL_LDC_BASE + 0xB2) ++#define REG_SCL_LDC_59_H (REG_SCL_LDC_BASE + 0xB3) ++#define REG_SCL_LDC_5A_L (REG_SCL_LDC_BASE + 0xB4) ++#define REG_SCL_LDC_5A_H (REG_SCL_LDC_BASE + 0xB5) ++#define REG_SCL_LDC_5B_L (REG_SCL_LDC_BASE + 0xB6) ++#define REG_SCL_LDC_5B_H (REG_SCL_LDC_BASE + 0xB7) ++#define REG_SCL_LDC_5C_L (REG_SCL_LDC_BASE + 0xB8) ++#define REG_SCL_LDC_5C_H (REG_SCL_LDC_BASE + 0xB9) ++#define REG_SCL_LDC_5D_L (REG_SCL_LDC_BASE + 0xBA) ++#define REG_SCL_LDC_5D_H (REG_SCL_LDC_BASE + 0xBB) ++#define REG_SCL_LDC_5E_L (REG_SCL_LDC_BASE + 0xBC) ++#define REG_SCL_LDC_5E_H (REG_SCL_LDC_BASE + 0xBD) ++#define REG_SCL_LDC_5F_L (REG_SCL_LDC_BASE + 0xBE) ++#define REG_SCL_LDC_5F_H (REG_SCL_LDC_BASE + 0xBF) ++#define REG_SCL_LDC_60_L (REG_SCL_LDC_BASE + 0xC0) ++#define REG_SCL_LDC_60_H (REG_SCL_LDC_BASE + 0xC1) ++#define REG_SCL_LDC_61_L (REG_SCL_LDC_BASE + 0xC2) ++#define REG_SCL_LDC_61_H (REG_SCL_LDC_BASE + 0xC3) ++#define REG_SCL_LDC_62_L (REG_SCL_LDC_BASE + 0xC4) ++#define REG_SCL_LDC_62_H (REG_SCL_LDC_BASE + 0xC5) ++#define REG_SCL_LDC_63_L (REG_SCL_LDC_BASE + 0xC6) ++#define REG_SCL_LDC_63_H (REG_SCL_LDC_BASE + 0xC7) ++#define REG_SCL_LDC_64_L (REG_SCL_LDC_BASE + 0xC8) ++#define REG_SCL_LDC_64_H (REG_SCL_LDC_BASE + 0xC9) ++#define REG_SCL_LDC_65_L (REG_SCL_LDC_BASE + 0xCA) ++#define REG_SCL_LDC_65_H (REG_SCL_LDC_BASE + 0xCB) ++#define REG_SCL_LDC_66_L (REG_SCL_LDC_BASE + 0xCC) ++#define REG_SCL_LDC_66_H (REG_SCL_LDC_BASE + 0xCD) ++#define REG_SCL_LDC_67_L (REG_SCL_LDC_BASE + 0xCE) ++#define REG_SCL_LDC_67_H (REG_SCL_LDC_BASE + 0xCF) ++#define REG_SCL_LDC_68_L (REG_SCL_LDC_BASE + 0xD0) ++#define REG_SCL_LDC_68_H (REG_SCL_LDC_BASE + 0xD1) ++#define REG_SCL_LDC_69_L (REG_SCL_LDC_BASE + 0xD2) ++#define REG_SCL_LDC_69_H (REG_SCL_LDC_BASE + 0xD3) ++#define REG_SCL_LDC_6A_L (REG_SCL_LDC_BASE + 0xD4) ++#define REG_SCL_LDC_6A_H (REG_SCL_LDC_BASE + 0xD5) ++#define REG_SCL_LDC_6B_L (REG_SCL_LDC_BASE + 0xD6) ++#define REG_SCL_LDC_6B_H (REG_SCL_LDC_BASE + 0xD7) ++#define REG_SCL_LDC_6C_L (REG_SCL_LDC_BASE + 0xD8) ++#define REG_SCL_LDC_6C_H (REG_SCL_LDC_BASE + 0xD9) ++#define REG_SCL_LDC_6D_L (REG_SCL_LDC_BASE + 0xDA) ++#define REG_SCL_LDC_6D_H (REG_SCL_LDC_BASE + 0xDB) ++#define REG_SCL_LDC_6E_L (REG_SCL_LDC_BASE + 0xDC) ++#define REG_SCL_LDC_6E_H (REG_SCL_LDC_BASE + 0xDD) ++#define REG_SCL_LDC_6F_L (REG_SCL_LDC_BASE + 0xDE) ++#define REG_SCL_LDC_6F_H (REG_SCL_LDC_BASE + 0xDF) ++#define REG_SCL_LDC_70_L (REG_SCL_LDC_BASE + 0xE0) ++#define REG_SCL_LDC_70_H (REG_SCL_LDC_BASE + 0xE1) ++#define REG_SCL_LDC_71_L (REG_SCL_LDC_BASE + 0xE2) ++#define REG_SCL_LDC_71_H (REG_SCL_LDC_BASE + 0xE3) ++#define REG_SCL_LDC_72_L (REG_SCL_LDC_BASE + 0xE4) ++#define REG_SCL_LDC_72_H (REG_SCL_LDC_BASE + 0xE5) ++#define REG_SCL_LDC_73_L (REG_SCL_LDC_BASE + 0xE6) ++#define REG_SCL_LDC_73_H (REG_SCL_LDC_BASE + 0xE7) ++#define REG_SCL_LDC_74_L (REG_SCL_LDC_BASE + 0xE8) ++#define REG_SCL_LDC_74_H (REG_SCL_LDC_BASE + 0xE9) ++#define REG_SCL_LDC_75_L (REG_SCL_LDC_BASE + 0xEA) ++#define REG_SCL_LDC_75_H (REG_SCL_LDC_BASE + 0xEB) ++#define REG_SCL_LDC_76_L (REG_SCL_LDC_BASE + 0xEC) ++#define REG_SCL_LDC_76_H (REG_SCL_LDC_BASE + 0xED) ++#define REG_SCL_LDC_77_L (REG_SCL_LDC_BASE + 0xEE) ++#define REG_SCL_LDC_77_H (REG_SCL_LDC_BASE + 0xEF) ++#define REG_SCL_LDC_78_L (REG_SCL_LDC_BASE + 0xF0) ++#define REG_SCL_LDC_78_H (REG_SCL_LDC_BASE + 0xF1) ++#define REG_SCL_LDC_79_L (REG_SCL_LDC_BASE + 0xF2) ++#define REG_SCL_LDC_79_H (REG_SCL_LDC_BASE + 0xF3) ++#define REG_SCL_LDC_7A_L (REG_SCL_LDC_BASE + 0xF4) ++#define REG_SCL_LDC_7A_H (REG_SCL_LDC_BASE + 0xF5) ++#define REG_SCL_LDC_7B_L (REG_SCL_LDC_BASE + 0xF6) ++#define REG_SCL_LDC_7B_H (REG_SCL_LDC_BASE + 0xF7) ++#define REG_SCL_LDC_7C_L (REG_SCL_LDC_BASE + 0xF8) ++#define REG_SCL_LDC_7C_H (REG_SCL_LDC_BASE + 0xF9) ++#define REG_SCL_LDC_7D_L (REG_SCL_LDC_BASE + 0xFA) ++#define REG_SCL_LDC_7D_H (REG_SCL_LDC_BASE + 0xFB) ++#define REG_SCL_LDC_7E_L (REG_SCL_LDC_BASE + 0xFC) ++#define REG_SCL_LDC_7E_H (REG_SCL_LDC_BASE + 0xFD) ++#define REG_SCL_LDC_7F_L (REG_SCL_LDC_BASE + 0xFE) ++#define REG_SCL_LDC_7F_H (REG_SCL_LDC_BASE + 0xFF) ++ ++#define REG_SCL_DMA0_00_L (REG_SCL_DMA0_BASE + 0x00) ++#define REG_SCL_DMA0_00_H (REG_SCL_DMA0_BASE + 0x01) ++#define REG_SCL_DMA0_01_L (REG_SCL_DMA0_BASE + 0x02) ++#define REG_SCL_DMA0_01_H (REG_SCL_DMA0_BASE + 0x03) ++#define REG_SCL_DMA0_02_L (REG_SCL_DMA0_BASE + 0x04) ++#define REG_SCL_DMA0_02_H (REG_SCL_DMA0_BASE + 0x05) ++#define REG_SCL_DMA0_03_L (REG_SCL_DMA0_BASE + 0x06) ++#define REG_SCL_DMA0_03_H (REG_SCL_DMA0_BASE + 0x07) ++#define REG_SCL_DMA0_04_L (REG_SCL_DMA0_BASE + 0x08) ++#define REG_SCL_DMA0_04_H (REG_SCL_DMA0_BASE + 0x09) ++#define REG_SCL_DMA0_05_L (REG_SCL_DMA0_BASE + 0x0A) ++#define REG_SCL_DMA0_05_H (REG_SCL_DMA0_BASE + 0x0B) ++#define REG_SCL_DMA0_06_L (REG_SCL_DMA0_BASE + 0x0C) ++#define REG_SCL_DMA0_06_H (REG_SCL_DMA0_BASE + 0x0D) ++#define REG_SCL_DMA0_07_L (REG_SCL_DMA0_BASE + 0x0E) ++#define REG_SCL_DMA0_07_H (REG_SCL_DMA0_BASE + 0x0F) ++#define REG_SCL_DMA0_08_L (REG_SCL_DMA0_BASE + 0x10) ++#define REG_SCL_DMA0_08_H (REG_SCL_DMA0_BASE + 0x11) ++#define REG_SCL_DMA0_09_L (REG_SCL_DMA0_BASE + 0x12) ++#define REG_SCL_DMA0_09_H (REG_SCL_DMA0_BASE + 0x13) ++#define REG_SCL_DMA0_0A_L (REG_SCL_DMA0_BASE + 0x14) ++#define REG_SCL_DMA0_0A_H (REG_SCL_DMA0_BASE + 0x15) ++#define REG_SCL_DMA0_0B_L (REG_SCL_DMA0_BASE + 0x16) ++#define REG_SCL_DMA0_0B_H (REG_SCL_DMA0_BASE + 0x17) ++#define REG_SCL_DMA0_0C_L (REG_SCL_DMA0_BASE + 0x18) ++#define REG_SCL_DMA0_0C_H (REG_SCL_DMA0_BASE + 0x19) ++#define REG_SCL_DMA0_0D_L (REG_SCL_DMA0_BASE + 0x1A) ++#define REG_SCL_DMA0_0D_H (REG_SCL_DMA0_BASE + 0x1B) ++#define REG_SCL_DMA0_0E_L (REG_SCL_DMA0_BASE + 0x1C) ++#define REG_SCL_DMA0_0E_H (REG_SCL_DMA0_BASE + 0x1D) ++#define REG_SCL_DMA0_0F_L (REG_SCL_DMA0_BASE + 0x1E) ++#define REG_SCL_DMA0_0F_H (REG_SCL_DMA0_BASE + 0x1F) ++#define REG_SCL_DMA0_10_L (REG_SCL_DMA0_BASE + 0x20) ++#define REG_SCL_DMA0_10_H (REG_SCL_DMA0_BASE + 0x21) ++#define REG_SCL_DMA0_11_L (REG_SCL_DMA0_BASE + 0x22) ++#define REG_SCL_DMA0_11_H (REG_SCL_DMA0_BASE + 0x23) ++#define REG_SCL_DMA0_12_L (REG_SCL_DMA0_BASE + 0x24) ++#define REG_SCL_DMA0_12_H (REG_SCL_DMA0_BASE + 0x25) ++#define REG_SCL_DMA0_13_L (REG_SCL_DMA0_BASE + 0x26) ++#define REG_SCL_DMA0_13_H (REG_SCL_DMA0_BASE + 0x27) ++#define REG_SCL_DMA0_14_L (REG_SCL_DMA0_BASE + 0x28) ++#define REG_SCL_DMA0_14_H (REG_SCL_DMA0_BASE + 0x29) ++#define REG_SCL_DMA0_15_L (REG_SCL_DMA0_BASE + 0x2A) ++#define REG_SCL_DMA0_15_H (REG_SCL_DMA0_BASE + 0x2B) ++#define REG_SCL_DMA0_16_L (REG_SCL_DMA0_BASE + 0x2C) ++#define REG_SCL_DMA0_16_H (REG_SCL_DMA0_BASE + 0x2D) ++#define REG_SCL_DMA0_17_L (REG_SCL_DMA0_BASE + 0x2E) ++#define REG_SCL_DMA0_17_H (REG_SCL_DMA0_BASE + 0x2F) ++#define REG_SCL_DMA0_18_L (REG_SCL_DMA0_BASE + 0x30) ++#define REG_SCL_DMA0_18_H (REG_SCL_DMA0_BASE + 0x31) ++#define REG_SCL_DMA0_19_L (REG_SCL_DMA0_BASE + 0x32) ++#define REG_SCL_DMA0_19_H (REG_SCL_DMA0_BASE + 0x33) ++#define REG_SCL_DMA0_1A_L (REG_SCL_DMA0_BASE + 0x34) ++#define REG_SCL_DMA0_1A_H (REG_SCL_DMA0_BASE + 0x35) ++#define REG_SCL_DMA0_1B_L (REG_SCL_DMA0_BASE + 0x36) ++#define REG_SCL_DMA0_1B_H (REG_SCL_DMA0_BASE + 0x37) ++#define REG_SCL_DMA0_1C_L (REG_SCL_DMA0_BASE + 0x38) ++#define REG_SCL_DMA0_1C_H (REG_SCL_DMA0_BASE + 0x39) ++#define REG_SCL_DMA0_1D_L (REG_SCL_DMA0_BASE + 0x3A) ++#define REG_SCL_DMA0_1D_H (REG_SCL_DMA0_BASE + 0x3B) ++#define REG_SCL_DMA0_1E_L (REG_SCL_DMA0_BASE + 0x3C) ++#define REG_SCL_DMA0_1E_H (REG_SCL_DMA0_BASE + 0x3D) ++#define REG_SCL_DMA0_1F_L (REG_SCL_DMA0_BASE + 0x3E) ++#define REG_SCL_DMA0_1F_H (REG_SCL_DMA0_BASE + 0x3F) ++#define REG_SCL_DMA0_20_L (REG_SCL_DMA0_BASE + 0x40) ++#define REG_SCL_DMA0_20_H (REG_SCL_DMA0_BASE + 0x41) ++#define REG_SCL_DMA0_21_L (REG_SCL_DMA0_BASE + 0x42) ++#define REG_SCL_DMA0_21_H (REG_SCL_DMA0_BASE + 0x43) ++#define REG_SCL_DMA0_22_L (REG_SCL_DMA0_BASE + 0x44) ++#define REG_SCL_DMA0_22_H (REG_SCL_DMA0_BASE + 0x45) ++#define REG_SCL_DMA0_23_L (REG_SCL_DMA0_BASE + 0x46) ++#define REG_SCL_DMA0_23_H (REG_SCL_DMA0_BASE + 0x47) ++#define REG_SCL_DMA0_24_L (REG_SCL_DMA0_BASE + 0x48) ++#define REG_SCL_DMA0_24_H (REG_SCL_DMA0_BASE + 0x49) ++#define REG_SCL_DMA0_25_L (REG_SCL_DMA0_BASE + 0x4A) ++#define REG_SCL_DMA0_25_H (REG_SCL_DMA0_BASE + 0x4B) ++#define REG_SCL_DMA0_26_L (REG_SCL_DMA0_BASE + 0x4C) ++#define REG_SCL_DMA0_26_H (REG_SCL_DMA0_BASE + 0x4D) ++#define REG_SCL_DMA0_27_L (REG_SCL_DMA0_BASE + 0x4E) ++#define REG_SCL_DMA0_27_H (REG_SCL_DMA0_BASE + 0x4F) ++#define REG_SCL_DMA0_28_L (REG_SCL_DMA0_BASE + 0x50) ++#define REG_SCL_DMA0_28_H (REG_SCL_DMA0_BASE + 0x51) ++#define REG_SCL_DMA0_29_L (REG_SCL_DMA0_BASE + 0x52) ++#define REG_SCL_DMA0_29_H (REG_SCL_DMA0_BASE + 0x53) ++#define REG_SCL_DMA0_2A_L (REG_SCL_DMA0_BASE + 0x54) ++#define REG_SCL_DMA0_2A_H (REG_SCL_DMA0_BASE + 0x55) ++#define REG_SCL_DMA0_2B_L (REG_SCL_DMA0_BASE + 0x56) ++#define REG_SCL_DMA0_2B_H (REG_SCL_DMA0_BASE + 0x57) ++#define REG_SCL_DMA0_2C_L (REG_SCL_DMA0_BASE + 0x58) ++#define REG_SCL_DMA0_2C_H (REG_SCL_DMA0_BASE + 0x59) ++#define REG_SCL_DMA0_2D_L (REG_SCL_DMA0_BASE + 0x5A) ++#define REG_SCL_DMA0_2D_H (REG_SCL_DMA0_BASE + 0x5B) ++#define REG_SCL_DMA0_2E_L (REG_SCL_DMA0_BASE + 0x5C) ++#define REG_SCL_DMA0_2E_H (REG_SCL_DMA0_BASE + 0x5D) ++#define REG_SCL_DMA0_2F_L (REG_SCL_DMA0_BASE + 0x5E) ++#define REG_SCL_DMA0_2F_H (REG_SCL_DMA0_BASE + 0x5F) ++#define REG_SCL_DMA0_30_L (REG_SCL_DMA0_BASE + 0x60) ++#define REG_SCL_DMA0_30_H (REG_SCL_DMA0_BASE + 0x61) ++#define REG_SCL_DMA0_31_L (REG_SCL_DMA0_BASE + 0x62) ++#define REG_SCL_DMA0_31_H (REG_SCL_DMA0_BASE + 0x63) ++#define REG_SCL_DMA0_32_L (REG_SCL_DMA0_BASE + 0x64) ++#define REG_SCL_DMA0_32_H (REG_SCL_DMA0_BASE + 0x65) ++#define REG_SCL_DMA0_33_L (REG_SCL_DMA0_BASE + 0x66) ++#define REG_SCL_DMA0_33_H (REG_SCL_DMA0_BASE + 0x67) ++#define REG_SCL_DMA0_34_L (REG_SCL_DMA0_BASE + 0x68) ++#define REG_SCL_DMA0_34_H (REG_SCL_DMA0_BASE + 0x69) ++#define REG_SCL_DMA0_35_L (REG_SCL_DMA0_BASE + 0x6A) ++#define REG_SCL_DMA0_35_H (REG_SCL_DMA0_BASE + 0x6B) ++#define REG_SCL_DMA0_36_L (REG_SCL_DMA0_BASE + 0x6C) ++#define REG_SCL_DMA0_36_H (REG_SCL_DMA0_BASE + 0x6D) ++#define REG_SCL_DMA0_37_L (REG_SCL_DMA0_BASE + 0x6E) ++#define REG_SCL_DMA0_37_H (REG_SCL_DMA0_BASE + 0x6F) ++#define REG_SCL_DMA0_38_L (REG_SCL_DMA0_BASE + 0x70) ++#define REG_SCL_DMA0_38_H (REG_SCL_DMA0_BASE + 0x71) ++#define REG_SCL_DMA0_39_L (REG_SCL_DMA0_BASE + 0x72) ++#define REG_SCL_DMA0_39_H (REG_SCL_DMA0_BASE + 0x73) ++#define REG_SCL_DMA0_3A_L (REG_SCL_DMA0_BASE + 0x74) ++#define REG_SCL_DMA0_3A_H (REG_SCL_DMA0_BASE + 0x75) ++#define REG_SCL_DMA0_3B_L (REG_SCL_DMA0_BASE + 0x76) ++#define REG_SCL_DMA0_3B_H (REG_SCL_DMA0_BASE + 0x77) ++#define REG_SCL_DMA0_3C_L (REG_SCL_DMA0_BASE + 0x78) ++#define REG_SCL_DMA0_3C_H (REG_SCL_DMA0_BASE + 0x79) ++#define REG_SCL_DMA0_3D_L (REG_SCL_DMA0_BASE + 0x7A) ++#define REG_SCL_DMA0_3D_H (REG_SCL_DMA0_BASE + 0x7B) ++#define REG_SCL_DMA0_3E_L (REG_SCL_DMA0_BASE + 0x7C) ++#define REG_SCL_DMA0_3E_H (REG_SCL_DMA0_BASE + 0x7D) ++#define REG_SCL_DMA0_3F_L (REG_SCL_DMA0_BASE + 0x7E) ++#define REG_SCL_DMA0_3F_H (REG_SCL_DMA0_BASE + 0x7F) ++#define REG_SCL_DMA0_40_L (REG_SCL_DMA0_BASE + 0x80) ++#define REG_SCL_DMA0_40_H (REG_SCL_DMA0_BASE + 0x81) ++#define REG_SCL_DMA0_41_L (REG_SCL_DMA0_BASE + 0x82) ++#define REG_SCL_DMA0_41_H (REG_SCL_DMA0_BASE + 0x83) ++#define REG_SCL_DMA0_42_L (REG_SCL_DMA0_BASE + 0x84) ++#define REG_SCL_DMA0_42_H (REG_SCL_DMA0_BASE + 0x85) ++#define REG_SCL_DMA0_43_L (REG_SCL_DMA0_BASE + 0x86) ++#define REG_SCL_DMA0_43_H (REG_SCL_DMA0_BASE + 0x87) ++#define REG_SCL_DMA0_44_L (REG_SCL_DMA0_BASE + 0x88) ++#define REG_SCL_DMA0_44_H (REG_SCL_DMA0_BASE + 0x89) ++#define REG_SCL_DMA0_45_L (REG_SCL_DMA0_BASE + 0x8A) ++#define REG_SCL_DMA0_45_H (REG_SCL_DMA0_BASE + 0x8B) ++#define REG_SCL_DMA0_46_L (REG_SCL_DMA0_BASE + 0x8C) ++#define REG_SCL_DMA0_46_H (REG_SCL_DMA0_BASE + 0x8D) ++#define REG_SCL_DMA0_47_L (REG_SCL_DMA0_BASE + 0x8E) ++#define REG_SCL_DMA0_47_H (REG_SCL_DMA0_BASE + 0x8F) ++#define REG_SCL_DMA0_48_L (REG_SCL_DMA0_BASE + 0x90) ++#define REG_SCL_DMA0_48_H (REG_SCL_DMA0_BASE + 0x91) ++#define REG_SCL_DMA0_49_L (REG_SCL_DMA0_BASE + 0x92) ++#define REG_SCL_DMA0_49_H (REG_SCL_DMA0_BASE + 0x93) ++#define REG_SCL_DMA0_4A_L (REG_SCL_DMA0_BASE + 0x94) ++#define REG_SCL_DMA0_4A_H (REG_SCL_DMA0_BASE + 0x95) ++#define REG_SCL_DMA0_4B_L (REG_SCL_DMA0_BASE + 0x96) ++#define REG_SCL_DMA0_4B_H (REG_SCL_DMA0_BASE + 0x97) ++#define REG_SCL_DMA0_4C_L (REG_SCL_DMA0_BASE + 0x98) ++#define REG_SCL_DMA0_4C_H (REG_SCL_DMA0_BASE + 0x99) ++#define REG_SCL_DMA0_4D_L (REG_SCL_DMA0_BASE + 0x9A) ++#define REG_SCL_DMA0_4D_H (REG_SCL_DMA0_BASE + 0x9B) ++#define REG_SCL_DMA0_4E_L (REG_SCL_DMA0_BASE + 0x9C) ++#define REG_SCL_DMA0_4E_H (REG_SCL_DMA0_BASE + 0x9D) ++#define REG_SCL_DMA0_4F_L (REG_SCL_DMA0_BASE + 0x9E) ++#define REG_SCL_DMA0_4F_H (REG_SCL_DMA0_BASE + 0x9F) ++#define REG_SCL_DMA0_50_L (REG_SCL_DMA0_BASE + 0xA0) ++#define REG_SCL_DMA0_50_H (REG_SCL_DMA0_BASE + 0xA1) ++#define REG_SCL_DMA0_51_L (REG_SCL_DMA0_BASE + 0xA2) ++#define REG_SCL_DMA0_51_H (REG_SCL_DMA0_BASE + 0xA3) ++#define REG_SCL_DMA0_52_L (REG_SCL_DMA0_BASE + 0xA4) ++#define REG_SCL_DMA0_52_H (REG_SCL_DMA0_BASE + 0xA5) ++#define REG_SCL_DMA0_53_L (REG_SCL_DMA0_BASE + 0xA6) ++#define REG_SCL_DMA0_53_H (REG_SCL_DMA0_BASE + 0xA7) ++#define REG_SCL_DMA0_54_L (REG_SCL_DMA0_BASE + 0xA8) ++#define REG_SCL_DMA0_54_H (REG_SCL_DMA0_BASE + 0xA9) ++#define REG_SCL_DMA0_55_L (REG_SCL_DMA0_BASE + 0xAA) ++#define REG_SCL_DMA0_55_H (REG_SCL_DMA0_BASE + 0xAB) ++#define REG_SCL_DMA0_56_L (REG_SCL_DMA0_BASE + 0xAC) ++#define REG_SCL_DMA0_56_H (REG_SCL_DMA0_BASE + 0xAD) ++#define REG_SCL_DMA0_57_L (REG_SCL_DMA0_BASE + 0xAE) ++#define REG_SCL_DMA0_57_H (REG_SCL_DMA0_BASE + 0xAF) ++#define REG_SCL_DMA0_58_L (REG_SCL_DMA0_BASE + 0xB0) ++#define REG_SCL_DMA0_58_H (REG_SCL_DMA0_BASE + 0xB1) ++#define REG_SCL_DMA0_59_L (REG_SCL_DMA0_BASE + 0xB2) ++#define REG_SCL_DMA0_59_H (REG_SCL_DMA0_BASE + 0xB3) ++#define REG_SCL_DMA0_5A_L (REG_SCL_DMA0_BASE + 0xB4) ++#define REG_SCL_DMA0_5A_H (REG_SCL_DMA0_BASE + 0xB5) ++#define REG_SCL_DMA0_5B_L (REG_SCL_DMA0_BASE + 0xB6) ++#define REG_SCL_DMA0_5B_H (REG_SCL_DMA0_BASE + 0xB7) ++#define REG_SCL_DMA0_5C_L (REG_SCL_DMA0_BASE + 0xB8) ++#define REG_SCL_DMA0_5C_H (REG_SCL_DMA0_BASE + 0xB9) ++#define REG_SCL_DMA0_5D_L (REG_SCL_DMA0_BASE + 0xBA) ++#define REG_SCL_DMA0_5D_H (REG_SCL_DMA0_BASE + 0xBB) ++#define REG_SCL_DMA0_5E_L (REG_SCL_DMA0_BASE + 0xBC) ++#define REG_SCL_DMA0_5E_H (REG_SCL_DMA0_BASE + 0xBD) ++#define REG_SCL_DMA0_5F_L (REG_SCL_DMA0_BASE + 0xBE) ++#define REG_SCL_DMA0_5F_H (REG_SCL_DMA0_BASE + 0xBF) ++#define REG_SCL_DMA0_60_L (REG_SCL_DMA0_BASE + 0xC0) ++#define REG_SCL_DMA0_60_H (REG_SCL_DMA0_BASE + 0xC1) ++#define REG_SCL_DMA0_61_L (REG_SCL_DMA0_BASE + 0xC2) ++#define REG_SCL_DMA0_61_H (REG_SCL_DMA0_BASE + 0xC3) ++#define REG_SCL_DMA0_62_L (REG_SCL_DMA0_BASE + 0xC4) ++#define REG_SCL_DMA0_62_H (REG_SCL_DMA0_BASE + 0xC5) ++#define REG_SCL_DMA0_63_L (REG_SCL_DMA0_BASE + 0xC6) ++#define REG_SCL_DMA0_63_H (REG_SCL_DMA0_BASE + 0xC7) ++#define REG_SCL_DMA0_64_L (REG_SCL_DMA0_BASE + 0xC8) ++#define REG_SCL_DMA0_64_H (REG_SCL_DMA0_BASE + 0xC9) ++#define REG_SCL_DMA0_65_L (REG_SCL_DMA0_BASE + 0xCA) ++#define REG_SCL_DMA0_65_H (REG_SCL_DMA0_BASE + 0xCB) ++#define REG_SCL_DMA0_66_L (REG_SCL_DMA0_BASE + 0xCC) ++#define REG_SCL_DMA0_66_H (REG_SCL_DMA0_BASE + 0xCD) ++#define REG_SCL_DMA0_67_L (REG_SCL_DMA0_BASE + 0xCE) ++#define REG_SCL_DMA0_67_H (REG_SCL_DMA0_BASE + 0xCF) ++#define REG_SCL_DMA0_68_L (REG_SCL_DMA0_BASE + 0xD0) ++#define REG_SCL_DMA0_68_H (REG_SCL_DMA0_BASE + 0xD1) ++#define REG_SCL_DMA0_69_L (REG_SCL_DMA0_BASE + 0xD2) ++#define REG_SCL_DMA0_69_H (REG_SCL_DMA0_BASE + 0xD3) ++#define REG_SCL_DMA0_6A_L (REG_SCL_DMA0_BASE + 0xD4) ++#define REG_SCL_DMA0_6A_H (REG_SCL_DMA0_BASE + 0xD5) ++#define REG_SCL_DMA0_6B_L (REG_SCL_DMA0_BASE + 0xD6) ++#define REG_SCL_DMA0_6B_H (REG_SCL_DMA0_BASE + 0xD7) ++#define REG_SCL_DMA0_6C_L (REG_SCL_DMA0_BASE + 0xD8) ++#define REG_SCL_DMA0_6C_H (REG_SCL_DMA0_BASE + 0xD9) ++#define REG_SCL_DMA0_6D_L (REG_SCL_DMA0_BASE + 0xDA) ++#define REG_SCL_DMA0_6D_H (REG_SCL_DMA0_BASE + 0xDB) ++#define REG_SCL_DMA0_6E_L (REG_SCL_DMA0_BASE + 0xDC) ++#define REG_SCL_DMA0_6E_H (REG_SCL_DMA0_BASE + 0xDD) ++#define REG_SCL_DMA0_6F_L (REG_SCL_DMA0_BASE + 0xDE) ++#define REG_SCL_DMA0_6F_H (REG_SCL_DMA0_BASE + 0xDF) ++#define REG_SCL_DMA0_70_L (REG_SCL_DMA0_BASE + 0xE0) ++#define REG_SCL_DMA0_70_H (REG_SCL_DMA0_BASE + 0xE1) ++#define REG_SCL_DMA0_71_L (REG_SCL_DMA0_BASE + 0xE2) ++#define REG_SCL_DMA0_71_H (REG_SCL_DMA0_BASE + 0xE3) ++#define REG_SCL_DMA0_72_L (REG_SCL_DMA0_BASE + 0xE4) ++#define REG_SCL_DMA0_72_H (REG_SCL_DMA0_BASE + 0xE5) ++#define REG_SCL_DMA0_73_L (REG_SCL_DMA0_BASE + 0xE6) ++#define REG_SCL_DMA0_73_H (REG_SCL_DMA0_BASE + 0xE7) ++#define REG_SCL_DMA0_74_L (REG_SCL_DMA0_BASE + 0xE8) ++#define REG_SCL_DMA0_74_H (REG_SCL_DMA0_BASE + 0xE9) ++#define REG_SCL_DMA0_75_L (REG_SCL_DMA0_BASE + 0xEA) ++#define REG_SCL_DMA0_75_H (REG_SCL_DMA0_BASE + 0xEB) ++#define REG_SCL_DMA0_76_L (REG_SCL_DMA0_BASE + 0xEC) ++#define REG_SCL_DMA0_76_H (REG_SCL_DMA0_BASE + 0xED) ++#define REG_SCL_DMA0_77_L (REG_SCL_DMA0_BASE + 0xEE) ++#define REG_SCL_DMA0_77_H (REG_SCL_DMA0_BASE + 0xEF) ++#define REG_SCL_DMA0_78_L (REG_SCL_DMA0_BASE + 0xF0) ++#define REG_SCL_DMA0_78_H (REG_SCL_DMA0_BASE + 0xF1) ++#define REG_SCL_DMA0_79_L (REG_SCL_DMA0_BASE + 0xF2) ++#define REG_SCL_DMA0_79_H (REG_SCL_DMA0_BASE + 0xF3) ++#define REG_SCL_DMA0_7A_L (REG_SCL_DMA0_BASE + 0xF4) ++#define REG_SCL_DMA0_7A_H (REG_SCL_DMA0_BASE + 0xF5) ++#define REG_SCL_DMA0_7B_L (REG_SCL_DMA0_BASE + 0xF6) ++#define REG_SCL_DMA0_7B_H (REG_SCL_DMA0_BASE + 0xF7) ++#define REG_SCL_DMA0_7C_L (REG_SCL_DMA0_BASE + 0xF8) ++#define REG_SCL_DMA0_7C_H (REG_SCL_DMA0_BASE + 0xF9) ++#define REG_SCL_DMA0_7D_L (REG_SCL_DMA0_BASE + 0xFA) ++#define REG_SCL_DMA0_7D_H (REG_SCL_DMA0_BASE + 0xFB) ++#define REG_SCL_DMA0_7E_L (REG_SCL_DMA0_BASE + 0xFC) ++#define REG_SCL_DMA0_7E_H (REG_SCL_DMA0_BASE + 0xFD) ++#define REG_SCL_DMA0_7F_L (REG_SCL_DMA0_BASE + 0xFE) ++#define REG_SCL_DMA0_7F_H (REG_SCL_DMA0_BASE + 0xFF) ++ ++#define REG_SCL_DMA1_00_L (REG_SCL_DMA1_BASE + 0x00) ++#define REG_SCL_DMA1_00_H (REG_SCL_DMA1_BASE + 0x01) ++#define REG_SCL_DMA1_01_L (REG_SCL_DMA1_BASE + 0x02) ++#define REG_SCL_DMA1_01_H (REG_SCL_DMA1_BASE + 0x03) ++#define REG_SCL_DMA1_02_L (REG_SCL_DMA1_BASE + 0x04) ++#define REG_SCL_DMA1_02_H (REG_SCL_DMA1_BASE + 0x05) ++#define REG_SCL_DMA1_03_L (REG_SCL_DMA1_BASE + 0x06) ++#define REG_SCL_DMA1_03_H (REG_SCL_DMA1_BASE + 0x07) ++#define REG_SCL_DMA1_04_L (REG_SCL_DMA1_BASE + 0x08) ++#define REG_SCL_DMA1_04_H (REG_SCL_DMA1_BASE + 0x09) ++#define REG_SCL_DMA1_05_L (REG_SCL_DMA1_BASE + 0x0A) ++#define REG_SCL_DMA1_05_H (REG_SCL_DMA1_BASE + 0x0B) ++#define REG_SCL_DMA1_06_L (REG_SCL_DMA1_BASE + 0x0C) ++#define REG_SCL_DMA1_06_H (REG_SCL_DMA1_BASE + 0x0D) ++#define REG_SCL_DMA1_07_L (REG_SCL_DMA1_BASE + 0x0E) ++#define REG_SCL_DMA1_07_H (REG_SCL_DMA1_BASE + 0x0F) ++#define REG_SCL_DMA1_08_L (REG_SCL_DMA1_BASE + 0x10) ++#define REG_SCL_DMA1_08_H (REG_SCL_DMA1_BASE + 0x11) ++#define REG_SCL_DMA1_09_L (REG_SCL_DMA1_BASE + 0x12) ++#define REG_SCL_DMA1_09_H (REG_SCL_DMA1_BASE + 0x13) ++#define REG_SCL_DMA1_0A_L (REG_SCL_DMA1_BASE + 0x14) ++#define REG_SCL_DMA1_0A_H (REG_SCL_DMA1_BASE + 0x15) ++#define REG_SCL_DMA1_0B_L (REG_SCL_DMA1_BASE + 0x16) ++#define REG_SCL_DMA1_0B_H (REG_SCL_DMA1_BASE + 0x17) ++#define REG_SCL_DMA1_0C_L (REG_SCL_DMA1_BASE + 0x18) ++#define REG_SCL_DMA1_0C_H (REG_SCL_DMA1_BASE + 0x19) ++#define REG_SCL_DMA1_0D_L (REG_SCL_DMA1_BASE + 0x1A) ++#define REG_SCL_DMA1_0D_H (REG_SCL_DMA1_BASE + 0x1B) ++#define REG_SCL_DMA1_0E_L (REG_SCL_DMA1_BASE + 0x1C) ++#define REG_SCL_DMA1_0E_H (REG_SCL_DMA1_BASE + 0x1D) ++#define REG_SCL_DMA1_0F_L (REG_SCL_DMA1_BASE + 0x1E) ++#define REG_SCL_DMA1_0F_H (REG_SCL_DMA1_BASE + 0x1F) ++#define REG_SCL_DMA1_10_L (REG_SCL_DMA1_BASE + 0x20) ++#define REG_SCL_DMA1_10_H (REG_SCL_DMA1_BASE + 0x21) ++#define REG_SCL_DMA1_11_L (REG_SCL_DMA1_BASE + 0x22) ++#define REG_SCL_DMA1_11_H (REG_SCL_DMA1_BASE + 0x23) ++#define REG_SCL_DMA1_12_L (REG_SCL_DMA1_BASE + 0x24) ++#define REG_SCL_DMA1_12_H (REG_SCL_DMA1_BASE + 0x25) ++#define REG_SCL_DMA1_13_L (REG_SCL_DMA1_BASE + 0x26) ++#define REG_SCL_DMA1_13_H (REG_SCL_DMA1_BASE + 0x27) ++#define REG_SCL_DMA1_14_L (REG_SCL_DMA1_BASE + 0x28) ++#define REG_SCL_DMA1_14_H (REG_SCL_DMA1_BASE + 0x29) ++#define REG_SCL_DMA1_15_L (REG_SCL_DMA1_BASE + 0x2A) ++#define REG_SCL_DMA1_15_H (REG_SCL_DMA1_BASE + 0x2B) ++#define REG_SCL_DMA1_16_L (REG_SCL_DMA1_BASE + 0x2C) ++#define REG_SCL_DMA1_16_H (REG_SCL_DMA1_BASE + 0x2D) ++#define REG_SCL_DMA1_17_L (REG_SCL_DMA1_BASE + 0x2E) ++#define REG_SCL_DMA1_17_H (REG_SCL_DMA1_BASE + 0x2F) ++#define REG_SCL_DMA1_18_L (REG_SCL_DMA1_BASE + 0x30) ++#define REG_SCL_DMA1_18_H (REG_SCL_DMA1_BASE + 0x31) ++#define REG_SCL_DMA1_19_L (REG_SCL_DMA1_BASE + 0x32) ++#define REG_SCL_DMA1_19_H (REG_SCL_DMA1_BASE + 0x33) ++#define REG_SCL_DMA1_1A_L (REG_SCL_DMA1_BASE + 0x34) ++#define REG_SCL_DMA1_1A_H (REG_SCL_DMA1_BASE + 0x35) ++#define REG_SCL_DMA1_1B_L (REG_SCL_DMA1_BASE + 0x36) ++#define REG_SCL_DMA1_1B_H (REG_SCL_DMA1_BASE + 0x37) ++#define REG_SCL_DMA1_1C_L (REG_SCL_DMA1_BASE + 0x38) ++#define REG_SCL_DMA1_1C_H (REG_SCL_DMA1_BASE + 0x39) ++#define REG_SCL_DMA1_1D_L (REG_SCL_DMA1_BASE + 0x3A) ++#define REG_SCL_DMA1_1D_H (REG_SCL_DMA1_BASE + 0x3B) ++#define REG_SCL_DMA1_1E_L (REG_SCL_DMA1_BASE + 0x3C) ++#define REG_SCL_DMA1_1E_H (REG_SCL_DMA1_BASE + 0x3D) ++#define REG_SCL_DMA1_1F_L (REG_SCL_DMA1_BASE + 0x3E) ++#define REG_SCL_DMA1_1F_H (REG_SCL_DMA1_BASE + 0x3F) ++#define REG_SCL_DMA1_20_L (REG_SCL_DMA1_BASE + 0x40) ++#define REG_SCL_DMA1_20_H (REG_SCL_DMA1_BASE + 0x41) ++#define REG_SCL_DMA1_21_L (REG_SCL_DMA1_BASE + 0x42) ++#define REG_SCL_DMA1_21_H (REG_SCL_DMA1_BASE + 0x43) ++#define REG_SCL_DMA1_22_L (REG_SCL_DMA1_BASE + 0x44) ++#define REG_SCL_DMA1_22_H (REG_SCL_DMA1_BASE + 0x45) ++#define REG_SCL_DMA1_23_L (REG_SCL_DMA1_BASE + 0x46) ++#define REG_SCL_DMA1_23_H (REG_SCL_DMA1_BASE + 0x47) ++#define REG_SCL_DMA1_24_L (REG_SCL_DMA1_BASE + 0x48) ++#define REG_SCL_DMA1_24_H (REG_SCL_DMA1_BASE + 0x49) ++#define REG_SCL_DMA1_25_L (REG_SCL_DMA1_BASE + 0x4A) ++#define REG_SCL_DMA1_25_H (REG_SCL_DMA1_BASE + 0x4B) ++#define REG_SCL_DMA1_26_L (REG_SCL_DMA1_BASE + 0x4C) ++#define REG_SCL_DMA1_26_H (REG_SCL_DMA1_BASE + 0x4D) ++#define REG_SCL_DMA1_27_L (REG_SCL_DMA1_BASE + 0x4E) ++#define REG_SCL_DMA1_27_H (REG_SCL_DMA1_BASE + 0x4F) ++#define REG_SCL_DMA1_28_L (REG_SCL_DMA1_BASE + 0x50) ++#define REG_SCL_DMA1_28_H (REG_SCL_DMA1_BASE + 0x51) ++#define REG_SCL_DMA1_29_L (REG_SCL_DMA1_BASE + 0x52) ++#define REG_SCL_DMA1_29_H (REG_SCL_DMA1_BASE + 0x53) ++#define REG_SCL_DMA1_2A_L (REG_SCL_DMA1_BASE + 0x54) ++#define REG_SCL_DMA1_2A_H (REG_SCL_DMA1_BASE + 0x55) ++#define REG_SCL_DMA1_2B_L (REG_SCL_DMA1_BASE + 0x56) ++#define REG_SCL_DMA1_2B_H (REG_SCL_DMA1_BASE + 0x57) ++#define REG_SCL_DMA1_2C_L (REG_SCL_DMA1_BASE + 0x58) ++#define REG_SCL_DMA1_2C_H (REG_SCL_DMA1_BASE + 0x59) ++#define REG_SCL_DMA1_2D_L (REG_SCL_DMA1_BASE + 0x5A) ++#define REG_SCL_DMA1_2D_H (REG_SCL_DMA1_BASE + 0x5B) ++#define REG_SCL_DMA1_2E_L (REG_SCL_DMA1_BASE + 0x5C) ++#define REG_SCL_DMA1_2E_H (REG_SCL_DMA1_BASE + 0x5D) ++#define REG_SCL_DMA1_2F_L (REG_SCL_DMA1_BASE + 0x5E) ++#define REG_SCL_DMA1_2F_H (REG_SCL_DMA1_BASE + 0x5F) ++#define REG_SCL_DMA1_30_L (REG_SCL_DMA1_BASE + 0x60) ++#define REG_SCL_DMA1_30_H (REG_SCL_DMA1_BASE + 0x61) ++#define REG_SCL_DMA1_31_L (REG_SCL_DMA1_BASE + 0x62) ++#define REG_SCL_DMA1_31_H (REG_SCL_DMA1_BASE + 0x63) ++#define REG_SCL_DMA1_32_L (REG_SCL_DMA1_BASE + 0x64) ++#define REG_SCL_DMA1_32_H (REG_SCL_DMA1_BASE + 0x65) ++#define REG_SCL_DMA1_33_L (REG_SCL_DMA1_BASE + 0x66) ++#define REG_SCL_DMA1_33_H (REG_SCL_DMA1_BASE + 0x67) ++#define REG_SCL_DMA1_34_L (REG_SCL_DMA1_BASE + 0x68) ++#define REG_SCL_DMA1_34_H (REG_SCL_DMA1_BASE + 0x69) ++#define REG_SCL_DMA1_35_L (REG_SCL_DMA1_BASE + 0x6A) ++#define REG_SCL_DMA1_35_H (REG_SCL_DMA1_BASE + 0x6B) ++#define REG_SCL_DMA1_36_L (REG_SCL_DMA1_BASE + 0x6C) ++#define REG_SCL_DMA1_36_H (REG_SCL_DMA1_BASE + 0x6D) ++#define REG_SCL_DMA1_37_L (REG_SCL_DMA1_BASE + 0x6E) ++#define REG_SCL_DMA1_37_H (REG_SCL_DMA1_BASE + 0x6F) ++#define REG_SCL_DMA1_38_L (REG_SCL_DMA1_BASE + 0x70) ++#define REG_SCL_DMA1_38_H (REG_SCL_DMA1_BASE + 0x71) ++#define REG_SCL_DMA1_39_L (REG_SCL_DMA1_BASE + 0x72) ++#define REG_SCL_DMA1_39_H (REG_SCL_DMA1_BASE + 0x73) ++#define REG_SCL_DMA1_3A_L (REG_SCL_DMA1_BASE + 0x74) ++#define REG_SCL_DMA1_3A_H (REG_SCL_DMA1_BASE + 0x75) ++#define REG_SCL_DMA1_3B_L (REG_SCL_DMA1_BASE + 0x76) ++#define REG_SCL_DMA1_3B_H (REG_SCL_DMA1_BASE + 0x77) ++#define REG_SCL_DMA1_3C_L (REG_SCL_DMA1_BASE + 0x78) ++#define REG_SCL_DMA1_3C_H (REG_SCL_DMA1_BASE + 0x79) ++#define REG_SCL_DMA1_3D_L (REG_SCL_DMA1_BASE + 0x7A) ++#define REG_SCL_DMA1_3D_H (REG_SCL_DMA1_BASE + 0x7B) ++#define REG_SCL_DMA1_3E_L (REG_SCL_DMA1_BASE + 0x7C) ++#define REG_SCL_DMA1_3E_H (REG_SCL_DMA1_BASE + 0x7D) ++#define REG_SCL_DMA1_3F_L (REG_SCL_DMA1_BASE + 0x7E) ++#define REG_SCL_DMA1_3F_H (REG_SCL_DMA1_BASE + 0x7F) ++#define REG_SCL_DMA1_40_L (REG_SCL_DMA1_BASE + 0x80) ++#define REG_SCL_DMA1_40_H (REG_SCL_DMA1_BASE + 0x81) ++#define REG_SCL_DMA1_41_L (REG_SCL_DMA1_BASE + 0x82) ++#define REG_SCL_DMA1_41_H (REG_SCL_DMA1_BASE + 0x83) ++#define REG_SCL_DMA1_42_L (REG_SCL_DMA1_BASE + 0x84) ++#define REG_SCL_DMA1_42_H (REG_SCL_DMA1_BASE + 0x85) ++#define REG_SCL_DMA1_43_L (REG_SCL_DMA1_BASE + 0x86) ++#define REG_SCL_DMA1_43_H (REG_SCL_DMA1_BASE + 0x87) ++#define REG_SCL_DMA1_44_L (REG_SCL_DMA1_BASE + 0x88) ++#define REG_SCL_DMA1_44_H (REG_SCL_DMA1_BASE + 0x89) ++#define REG_SCL_DMA1_45_L (REG_SCL_DMA1_BASE + 0x8A) ++#define REG_SCL_DMA1_45_H (REG_SCL_DMA1_BASE + 0x8B) ++#define REG_SCL_DMA1_46_L (REG_SCL_DMA1_BASE + 0x8C) ++#define REG_SCL_DMA1_46_H (REG_SCL_DMA1_BASE + 0x8D) ++#define REG_SCL_DMA1_47_L (REG_SCL_DMA1_BASE + 0x8E) ++#define REG_SCL_DMA1_47_H (REG_SCL_DMA1_BASE + 0x8F) ++#define REG_SCL_DMA1_48_L (REG_SCL_DMA1_BASE + 0x90) ++#define REG_SCL_DMA1_48_H (REG_SCL_DMA1_BASE + 0x91) ++#define REG_SCL_DMA1_49_L (REG_SCL_DMA1_BASE + 0x92) ++#define REG_SCL_DMA1_49_H (REG_SCL_DMA1_BASE + 0x93) ++#define REG_SCL_DMA1_4A_L (REG_SCL_DMA1_BASE + 0x94) ++#define REG_SCL_DMA1_4A_H (REG_SCL_DMA1_BASE + 0x95) ++#define REG_SCL_DMA1_4B_L (REG_SCL_DMA1_BASE + 0x96) ++#define REG_SCL_DMA1_4B_H (REG_SCL_DMA1_BASE + 0x97) ++#define REG_SCL_DMA1_4C_L (REG_SCL_DMA1_BASE + 0x98) ++#define REG_SCL_DMA1_4C_H (REG_SCL_DMA1_BASE + 0x99) ++#define REG_SCL_DMA1_4D_L (REG_SCL_DMA1_BASE + 0x9A) ++#define REG_SCL_DMA1_4D_H (REG_SCL_DMA1_BASE + 0x9B) ++#define REG_SCL_DMA1_4E_L (REG_SCL_DMA1_BASE + 0x9C) ++#define REG_SCL_DMA1_4E_H (REG_SCL_DMA1_BASE + 0x9D) ++#define REG_SCL_DMA1_4F_L (REG_SCL_DMA1_BASE + 0x9E) ++#define REG_SCL_DMA1_4F_H (REG_SCL_DMA1_BASE + 0x9F) ++#define REG_SCL_DMA1_50_L (REG_SCL_DMA1_BASE + 0xA0) ++#define REG_SCL_DMA1_50_H (REG_SCL_DMA1_BASE + 0xA1) ++#define REG_SCL_DMA1_51_L (REG_SCL_DMA1_BASE + 0xA2) ++#define REG_SCL_DMA1_51_H (REG_SCL_DMA1_BASE + 0xA3) ++#define REG_SCL_DMA1_52_L (REG_SCL_DMA1_BASE + 0xA4) ++#define REG_SCL_DMA1_52_H (REG_SCL_DMA1_BASE + 0xA5) ++#define REG_SCL_DMA1_53_L (REG_SCL_DMA1_BASE + 0xA6) ++#define REG_SCL_DMA1_53_H (REG_SCL_DMA1_BASE + 0xA7) ++#define REG_SCL_DMA1_54_L (REG_SCL_DMA1_BASE + 0xA8) ++#define REG_SCL_DMA1_54_H (REG_SCL_DMA1_BASE + 0xA9) ++#define REG_SCL_DMA1_55_L (REG_SCL_DMA1_BASE + 0xAA) ++#define REG_SCL_DMA1_55_H (REG_SCL_DMA1_BASE + 0xAB) ++#define REG_SCL_DMA1_56_L (REG_SCL_DMA1_BASE + 0xAC) ++#define REG_SCL_DMA1_56_H (REG_SCL_DMA1_BASE + 0xAD) ++#define REG_SCL_DMA1_57_L (REG_SCL_DMA1_BASE + 0xAE) ++#define REG_SCL_DMA1_57_H (REG_SCL_DMA1_BASE + 0xAF) ++#define REG_SCL_DMA1_58_L (REG_SCL_DMA1_BASE + 0xB0) ++#define REG_SCL_DMA1_58_H (REG_SCL_DMA1_BASE + 0xB1) ++#define REG_SCL_DMA1_59_L (REG_SCL_DMA1_BASE + 0xB2) ++#define REG_SCL_DMA1_59_H (REG_SCL_DMA1_BASE + 0xB3) ++#define REG_SCL_DMA1_5A_L (REG_SCL_DMA1_BASE + 0xB4) ++#define REG_SCL_DMA1_5A_H (REG_SCL_DMA1_BASE + 0xB5) ++#define REG_SCL_DMA1_5B_L (REG_SCL_DMA1_BASE + 0xB6) ++#define REG_SCL_DMA1_5B_H (REG_SCL_DMA1_BASE + 0xB7) ++#define REG_SCL_DMA1_5C_L (REG_SCL_DMA1_BASE + 0xB8) ++#define REG_SCL_DMA1_5C_H (REG_SCL_DMA1_BASE + 0xB9) ++#define REG_SCL_DMA1_5D_L (REG_SCL_DMA1_BASE + 0xBA) ++#define REG_SCL_DMA1_5D_H (REG_SCL_DMA1_BASE + 0xBB) ++#define REG_SCL_DMA1_5E_L (REG_SCL_DMA1_BASE + 0xBC) ++#define REG_SCL_DMA1_5E_H (REG_SCL_DMA1_BASE + 0xBD) ++#define REG_SCL_DMA1_5F_L (REG_SCL_DMA1_BASE + 0xBE) ++#define REG_SCL_DMA1_5F_H (REG_SCL_DMA1_BASE + 0xBF) ++#define REG_SCL_DMA1_60_L (REG_SCL_DMA1_BASE + 0xC0) ++#define REG_SCL_DMA1_60_H (REG_SCL_DMA1_BASE + 0xC1) ++#define REG_SCL_DMA1_61_L (REG_SCL_DMA1_BASE + 0xC2) ++#define REG_SCL_DMA1_61_H (REG_SCL_DMA1_BASE + 0xC3) ++#define REG_SCL_DMA1_62_L (REG_SCL_DMA1_BASE + 0xC4) ++#define REG_SCL_DMA1_62_H (REG_SCL_DMA1_BASE + 0xC5) ++#define REG_SCL_DMA1_63_L (REG_SCL_DMA1_BASE + 0xC6) ++#define REG_SCL_DMA1_63_H (REG_SCL_DMA1_BASE + 0xC7) ++#define REG_SCL_DMA1_64_L (REG_SCL_DMA1_BASE + 0xC8) ++#define REG_SCL_DMA1_64_H (REG_SCL_DMA1_BASE + 0xC9) ++#define REG_SCL_DMA1_65_L (REG_SCL_DMA1_BASE + 0xCA) ++#define REG_SCL_DMA1_65_H (REG_SCL_DMA1_BASE + 0xCB) ++#define REG_SCL_DMA1_66_L (REG_SCL_DMA1_BASE + 0xCC) ++#define REG_SCL_DMA1_66_H (REG_SCL_DMA1_BASE + 0xCD) ++#define REG_SCL_DMA1_67_L (REG_SCL_DMA1_BASE + 0xCE) ++#define REG_SCL_DMA1_67_H (REG_SCL_DMA1_BASE + 0xCF) ++#define REG_SCL_DMA1_68_L (REG_SCL_DMA1_BASE + 0xD0) ++#define REG_SCL_DMA1_68_H (REG_SCL_DMA1_BASE + 0xD1) ++#define REG_SCL_DMA1_69_L (REG_SCL_DMA1_BASE + 0xD2) ++#define REG_SCL_DMA1_69_H (REG_SCL_DMA1_BASE + 0xD3) ++#define REG_SCL_DMA1_6A_L (REG_SCL_DMA1_BASE + 0xD4) ++#define REG_SCL_DMA1_6A_H (REG_SCL_DMA1_BASE + 0xD5) ++#define REG_SCL_DMA1_6B_L (REG_SCL_DMA1_BASE + 0xD6) ++#define REG_SCL_DMA1_6B_H (REG_SCL_DMA1_BASE + 0xD7) ++#define REG_SCL_DMA1_6C_L (REG_SCL_DMA1_BASE + 0xD8) ++#define REG_SCL_DMA1_6C_H (REG_SCL_DMA1_BASE + 0xD9) ++#define REG_SCL_DMA1_6D_L (REG_SCL_DMA1_BASE + 0xDA) ++#define REG_SCL_DMA1_6D_H (REG_SCL_DMA1_BASE + 0xDB) ++#define REG_SCL_DMA1_6E_L (REG_SCL_DMA1_BASE + 0xDC) ++#define REG_SCL_DMA1_6E_H (REG_SCL_DMA1_BASE + 0xDD) ++#define REG_SCL_DMA1_6F_L (REG_SCL_DMA1_BASE + 0xDE) ++#define REG_SCL_DMA1_6F_H (REG_SCL_DMA1_BASE + 0xDF) ++#define REG_SCL_DMA1_70_L (REG_SCL_DMA1_BASE + 0xE0) ++#define REG_SCL_DMA1_70_H (REG_SCL_DMA1_BASE + 0xE1) ++#define REG_SCL_DMA1_71_L (REG_SCL_DMA1_BASE + 0xE2) ++#define REG_SCL_DMA1_71_H (REG_SCL_DMA1_BASE + 0xE3) ++#define REG_SCL_DMA1_72_L (REG_SCL_DMA1_BASE + 0xE4) ++#define REG_SCL_DMA1_72_H (REG_SCL_DMA1_BASE + 0xE5) ++#define REG_SCL_DMA1_73_L (REG_SCL_DMA1_BASE + 0xE6) ++#define REG_SCL_DMA1_73_H (REG_SCL_DMA1_BASE + 0xE7) ++#define REG_SCL_DMA1_74_L (REG_SCL_DMA1_BASE + 0xE8) ++#define REG_SCL_DMA1_74_H (REG_SCL_DMA1_BASE + 0xE9) ++#define REG_SCL_DMA1_75_L (REG_SCL_DMA1_BASE + 0xEA) ++#define REG_SCL_DMA1_75_H (REG_SCL_DMA1_BASE + 0xEB) ++#define REG_SCL_DMA1_76_L (REG_SCL_DMA1_BASE + 0xEC) ++#define REG_SCL_DMA1_76_H (REG_SCL_DMA1_BASE + 0xED) ++#define REG_SCL_DMA1_77_L (REG_SCL_DMA1_BASE + 0xEE) ++#define REG_SCL_DMA1_77_H (REG_SCL_DMA1_BASE + 0xEF) ++#define REG_SCL_DMA1_78_L (REG_SCL_DMA1_BASE + 0xF0) ++#define REG_SCL_DMA1_78_H (REG_SCL_DMA1_BASE + 0xF1) ++#define REG_SCL_DMA1_79_L (REG_SCL_DMA1_BASE + 0xF2) ++#define REG_SCL_DMA1_79_H (REG_SCL_DMA1_BASE + 0xF3) ++#define REG_SCL_DMA1_7A_L (REG_SCL_DMA1_BASE + 0xF4) ++#define REG_SCL_DMA1_7A_H (REG_SCL_DMA1_BASE + 0xF5) ++#define REG_SCL_DMA1_7B_L (REG_SCL_DMA1_BASE + 0xF6) ++#define REG_SCL_DMA1_7B_H (REG_SCL_DMA1_BASE + 0xF7) ++#define REG_SCL_DMA1_7C_L (REG_SCL_DMA1_BASE + 0xF8) ++#define REG_SCL_DMA1_7C_H (REG_SCL_DMA1_BASE + 0xF9) ++#define REG_SCL_DMA1_7D_L (REG_SCL_DMA1_BASE + 0xFA) ++#define REG_SCL_DMA1_7D_H (REG_SCL_DMA1_BASE + 0xFB) ++#define REG_SCL_DMA1_7E_L (REG_SCL_DMA1_BASE + 0xFC) ++#define REG_SCL_DMA1_7E_H (REG_SCL_DMA1_BASE + 0xFD) ++#define REG_SCL_DMA1_7F_L (REG_SCL_DMA1_BASE + 0xFE) ++#define REG_SCL_DMA1_7F_H (REG_SCL_DMA1_BASE + 0xFF) ++ ++#define REG_SCL_DMA2_00_L (REG_SCL_DMA2_BASE + 0x00) ++#define REG_SCL_DMA2_00_H (REG_SCL_DMA2_BASE + 0x01) ++#define REG_SCL_DMA2_01_L (REG_SCL_DMA2_BASE + 0x02) ++#define REG_SCL_DMA2_01_H (REG_SCL_DMA2_BASE + 0x03) ++#define REG_SCL_DMA2_02_L (REG_SCL_DMA2_BASE + 0x04) ++#define REG_SCL_DMA2_02_H (REG_SCL_DMA2_BASE + 0x05) ++#define REG_SCL_DMA2_03_L (REG_SCL_DMA2_BASE + 0x06) ++#define REG_SCL_DMA2_03_H (REG_SCL_DMA2_BASE + 0x07) ++#define REG_SCL_DMA2_04_L (REG_SCL_DMA2_BASE + 0x08) ++#define REG_SCL_DMA2_04_H (REG_SCL_DMA2_BASE + 0x09) ++#define REG_SCL_DMA2_05_L (REG_SCL_DMA2_BASE + 0x0A) ++#define REG_SCL_DMA2_05_H (REG_SCL_DMA2_BASE + 0x0B) ++#define REG_SCL_DMA2_06_L (REG_SCL_DMA2_BASE + 0x0C) ++#define REG_SCL_DMA2_06_H (REG_SCL_DMA2_BASE + 0x0D) ++#define REG_SCL_DMA2_07_L (REG_SCL_DMA2_BASE + 0x0E) ++#define REG_SCL_DMA2_07_H (REG_SCL_DMA2_BASE + 0x0F) ++#define REG_SCL_DMA2_08_L (REG_SCL_DMA2_BASE + 0x10) ++#define REG_SCL_DMA2_08_H (REG_SCL_DMA2_BASE + 0x11) ++#define REG_SCL_DMA2_09_L (REG_SCL_DMA2_BASE + 0x12) ++#define REG_SCL_DMA2_09_H (REG_SCL_DMA2_BASE + 0x13) ++#define REG_SCL_DMA2_0A_L (REG_SCL_DMA2_BASE + 0x14) ++#define REG_SCL_DMA2_0A_H (REG_SCL_DMA2_BASE + 0x15) ++#define REG_SCL_DMA2_0B_L (REG_SCL_DMA2_BASE + 0x16) ++#define REG_SCL_DMA2_0B_H (REG_SCL_DMA2_BASE + 0x17) ++#define REG_SCL_DMA2_0C_L (REG_SCL_DMA2_BASE + 0x18) ++#define REG_SCL_DMA2_0C_H (REG_SCL_DMA2_BASE + 0x19) ++#define REG_SCL_DMA2_0D_L (REG_SCL_DMA2_BASE + 0x1A) ++#define REG_SCL_DMA2_0D_H (REG_SCL_DMA2_BASE + 0x1B) ++#define REG_SCL_DMA2_0E_L (REG_SCL_DMA2_BASE + 0x1C) ++#define REG_SCL_DMA2_0E_H (REG_SCL_DMA2_BASE + 0x1D) ++#define REG_SCL_DMA2_0F_L (REG_SCL_DMA2_BASE + 0x1E) ++#define REG_SCL_DMA2_0F_H (REG_SCL_DMA2_BASE + 0x1F) ++#define REG_SCL_DMA2_10_L (REG_SCL_DMA2_BASE + 0x20) ++#define REG_SCL_DMA2_10_H (REG_SCL_DMA2_BASE + 0x21) ++#define REG_SCL_DMA2_11_L (REG_SCL_DMA2_BASE + 0x22) ++#define REG_SCL_DMA2_11_H (REG_SCL_DMA2_BASE + 0x23) ++#define REG_SCL_DMA2_12_L (REG_SCL_DMA2_BASE + 0x24) ++#define REG_SCL_DMA2_12_H (REG_SCL_DMA2_BASE + 0x25) ++#define REG_SCL_DMA2_13_L (REG_SCL_DMA2_BASE + 0x26) ++#define REG_SCL_DMA2_13_H (REG_SCL_DMA2_BASE + 0x27) ++#define REG_SCL_DMA2_14_L (REG_SCL_DMA2_BASE + 0x28) ++#define REG_SCL_DMA2_14_H (REG_SCL_DMA2_BASE + 0x29) ++#define REG_SCL_DMA2_15_L (REG_SCL_DMA2_BASE + 0x2A) ++#define REG_SCL_DMA2_15_H (REG_SCL_DMA2_BASE + 0x2B) ++#define REG_SCL_DMA2_16_L (REG_SCL_DMA2_BASE + 0x2C) ++#define REG_SCL_DMA2_16_H (REG_SCL_DMA2_BASE + 0x2D) ++#define REG_SCL_DMA2_17_L (REG_SCL_DMA2_BASE + 0x2E) ++#define REG_SCL_DMA2_17_H (REG_SCL_DMA2_BASE + 0x2F) ++#define REG_SCL_DMA2_18_L (REG_SCL_DMA2_BASE + 0x30) ++#define REG_SCL_DMA2_18_H (REG_SCL_DMA2_BASE + 0x31) ++#define REG_SCL_DMA2_19_L (REG_SCL_DMA2_BASE + 0x32) ++#define REG_SCL_DMA2_19_H (REG_SCL_DMA2_BASE + 0x33) ++#define REG_SCL_DMA2_1A_L (REG_SCL_DMA2_BASE + 0x34) ++#define REG_SCL_DMA2_1A_H (REG_SCL_DMA2_BASE + 0x35) ++#define REG_SCL_DMA2_1B_L (REG_SCL_DMA2_BASE + 0x36) ++#define REG_SCL_DMA2_1B_H (REG_SCL_DMA2_BASE + 0x37) ++#define REG_SCL_DMA2_1C_L (REG_SCL_DMA2_BASE + 0x38) ++#define REG_SCL_DMA2_1C_H (REG_SCL_DMA2_BASE + 0x39) ++#define REG_SCL_DMA2_1D_L (REG_SCL_DMA2_BASE + 0x3A) ++#define REG_SCL_DMA2_1D_H (REG_SCL_DMA2_BASE + 0x3B) ++#define REG_SCL_DMA2_1E_L (REG_SCL_DMA2_BASE + 0x3C) ++#define REG_SCL_DMA2_1E_H (REG_SCL_DMA2_BASE + 0x3D) ++#define REG_SCL_DMA2_1F_L (REG_SCL_DMA2_BASE + 0x3E) ++#define REG_SCL_DMA2_1F_H (REG_SCL_DMA2_BASE + 0x3F) ++#define REG_SCL_DMA2_20_L (REG_SCL_DMA2_BASE + 0x40) ++#define REG_SCL_DMA2_20_H (REG_SCL_DMA2_BASE + 0x41) ++#define REG_SCL_DMA2_21_L (REG_SCL_DMA2_BASE + 0x42) ++#define REG_SCL_DMA2_21_H (REG_SCL_DMA2_BASE + 0x43) ++#define REG_SCL_DMA2_22_L (REG_SCL_DMA2_BASE + 0x44) ++#define REG_SCL_DMA2_22_H (REG_SCL_DMA2_BASE + 0x45) ++#define REG_SCL_DMA2_23_L (REG_SCL_DMA2_BASE + 0x46) ++#define REG_SCL_DMA2_23_H (REG_SCL_DMA2_BASE + 0x47) ++#define REG_SCL_DMA2_24_L (REG_SCL_DMA2_BASE + 0x48) ++#define REG_SCL_DMA2_24_H (REG_SCL_DMA2_BASE + 0x49) ++#define REG_SCL_DMA2_25_L (REG_SCL_DMA2_BASE + 0x4A) ++#define REG_SCL_DMA2_25_H (REG_SCL_DMA2_BASE + 0x4B) ++#define REG_SCL_DMA2_26_L (REG_SCL_DMA2_BASE + 0x4C) ++#define REG_SCL_DMA2_26_H (REG_SCL_DMA2_BASE + 0x4D) ++#define REG_SCL_DMA2_27_L (REG_SCL_DMA2_BASE + 0x4E) ++#define REG_SCL_DMA2_27_H (REG_SCL_DMA2_BASE + 0x4F) ++#define REG_SCL_DMA2_28_L (REG_SCL_DMA2_BASE + 0x50) ++#define REG_SCL_DMA2_28_H (REG_SCL_DMA2_BASE + 0x51) ++#define REG_SCL_DMA2_29_L (REG_SCL_DMA2_BASE + 0x52) ++#define REG_SCL_DMA2_29_H (REG_SCL_DMA2_BASE + 0x53) ++#define REG_SCL_DMA2_2A_L (REG_SCL_DMA2_BASE + 0x54) ++#define REG_SCL_DMA2_2A_H (REG_SCL_DMA2_BASE + 0x55) ++#define REG_SCL_DMA2_2B_L (REG_SCL_DMA2_BASE + 0x56) ++#define REG_SCL_DMA2_2B_H (REG_SCL_DMA2_BASE + 0x57) ++#define REG_SCL_DMA2_2C_L (REG_SCL_DMA2_BASE + 0x58) ++#define REG_SCL_DMA2_2C_H (REG_SCL_DMA2_BASE + 0x59) ++#define REG_SCL_DMA2_2D_L (REG_SCL_DMA2_BASE + 0x5A) ++#define REG_SCL_DMA2_2D_H (REG_SCL_DMA2_BASE + 0x5B) ++#define REG_SCL_DMA2_2E_L (REG_SCL_DMA2_BASE + 0x5C) ++#define REG_SCL_DMA2_2E_H (REG_SCL_DMA2_BASE + 0x5D) ++#define REG_SCL_DMA2_2F_L (REG_SCL_DMA2_BASE + 0x5E) ++#define REG_SCL_DMA2_2F_H (REG_SCL_DMA2_BASE + 0x5F) ++#define REG_SCL_DMA2_30_L (REG_SCL_DMA2_BASE + 0x60) ++#define REG_SCL_DMA2_30_H (REG_SCL_DMA2_BASE + 0x61) ++#define REG_SCL_DMA2_31_L (REG_SCL_DMA2_BASE + 0x62) ++#define REG_SCL_DMA2_31_H (REG_SCL_DMA2_BASE + 0x63) ++#define REG_SCL_DMA2_32_L (REG_SCL_DMA2_BASE + 0x64) ++#define REG_SCL_DMA2_32_H (REG_SCL_DMA2_BASE + 0x65) ++#define REG_SCL_DMA2_33_L (REG_SCL_DMA2_BASE + 0x66) ++#define REG_SCL_DMA2_33_H (REG_SCL_DMA2_BASE + 0x67) ++#define REG_SCL_DMA2_34_L (REG_SCL_DMA2_BASE + 0x68) ++#define REG_SCL_DMA2_34_H (REG_SCL_DMA2_BASE + 0x69) ++#define REG_SCL_DMA2_35_L (REG_SCL_DMA2_BASE + 0x6A) ++#define REG_SCL_DMA2_35_H (REG_SCL_DMA2_BASE + 0x6B) ++#define REG_SCL_DMA2_36_L (REG_SCL_DMA2_BASE + 0x6C) ++#define REG_SCL_DMA2_36_H (REG_SCL_DMA2_BASE + 0x6D) ++#define REG_SCL_DMA2_37_L (REG_SCL_DMA2_BASE + 0x6E) ++#define REG_SCL_DMA2_37_H (REG_SCL_DMA2_BASE + 0x6F) ++#define REG_SCL_DMA2_38_L (REG_SCL_DMA2_BASE + 0x70) ++#define REG_SCL_DMA2_38_H (REG_SCL_DMA2_BASE + 0x71) ++#define REG_SCL_DMA2_39_L (REG_SCL_DMA2_BASE + 0x72) ++#define REG_SCL_DMA2_39_H (REG_SCL_DMA2_BASE + 0x73) ++#define REG_SCL_DMA2_3A_L (REG_SCL_DMA2_BASE + 0x74) ++#define REG_SCL_DMA2_3A_H (REG_SCL_DMA2_BASE + 0x75) ++#define REG_SCL_DMA2_3B_L (REG_SCL_DMA2_BASE + 0x76) ++#define REG_SCL_DMA2_3B_H (REG_SCL_DMA2_BASE + 0x77) ++#define REG_SCL_DMA2_3C_L (REG_SCL_DMA2_BASE + 0x78) ++#define REG_SCL_DMA2_3C_H (REG_SCL_DMA2_BASE + 0x79) ++#define REG_SCL_DMA2_3D_L (REG_SCL_DMA2_BASE + 0x7A) ++#define REG_SCL_DMA2_3D_H (REG_SCL_DMA2_BASE + 0x7B) ++#define REG_SCL_DMA2_3E_L (REG_SCL_DMA2_BASE + 0x7C) ++#define REG_SCL_DMA2_3E_H (REG_SCL_DMA2_BASE + 0x7D) ++#define REG_SCL_DMA2_3F_L (REG_SCL_DMA2_BASE + 0x7E) ++#define REG_SCL_DMA2_3F_H (REG_SCL_DMA2_BASE + 0x7F) ++#define REG_SCL_DMA2_40_L (REG_SCL_DMA2_BASE + 0x80) ++#define REG_SCL_DMA2_40_H (REG_SCL_DMA2_BASE + 0x81) ++#define REG_SCL_DMA2_41_L (REG_SCL_DMA2_BASE + 0x82) ++#define REG_SCL_DMA2_41_H (REG_SCL_DMA2_BASE + 0x83) ++#define REG_SCL_DMA2_42_L (REG_SCL_DMA2_BASE + 0x84) ++#define REG_SCL_DMA2_42_H (REG_SCL_DMA2_BASE + 0x85) ++#define REG_SCL_DMA2_43_L (REG_SCL_DMA2_BASE + 0x86) ++#define REG_SCL_DMA2_43_H (REG_SCL_DMA2_BASE + 0x87) ++#define REG_SCL_DMA2_44_L (REG_SCL_DMA2_BASE + 0x88) ++#define REG_SCL_DMA2_44_H (REG_SCL_DMA2_BASE + 0x89) ++#define REG_SCL_DMA2_45_L (REG_SCL_DMA2_BASE + 0x8A) ++#define REG_SCL_DMA2_45_H (REG_SCL_DMA2_BASE + 0x8B) ++#define REG_SCL_DMA2_46_L (REG_SCL_DMA2_BASE + 0x8C) ++#define REG_SCL_DMA2_46_H (REG_SCL_DMA2_BASE + 0x8D) ++#define REG_SCL_DMA2_47_L (REG_SCL_DMA2_BASE + 0x8E) ++#define REG_SCL_DMA2_47_H (REG_SCL_DMA2_BASE + 0x8F) ++#define REG_SCL_DMA2_48_L (REG_SCL_DMA2_BASE + 0x90) ++#define REG_SCL_DMA2_48_H (REG_SCL_DMA2_BASE + 0x91) ++#define REG_SCL_DMA2_49_L (REG_SCL_DMA2_BASE + 0x92) ++#define REG_SCL_DMA2_49_H (REG_SCL_DMA2_BASE + 0x93) ++#define REG_SCL_DMA2_4A_L (REG_SCL_DMA2_BASE + 0x94) ++#define REG_SCL_DMA2_4A_H (REG_SCL_DMA2_BASE + 0x95) ++#define REG_SCL_DMA2_4B_L (REG_SCL_DMA2_BASE + 0x96) ++#define REG_SCL_DMA2_4B_H (REG_SCL_DMA2_BASE + 0x97) ++#define REG_SCL_DMA2_4C_L (REG_SCL_DMA2_BASE + 0x98) ++#define REG_SCL_DMA2_4C_H (REG_SCL_DMA2_BASE + 0x99) ++#define REG_SCL_DMA2_4D_L (REG_SCL_DMA2_BASE + 0x9A) ++#define REG_SCL_DMA2_4D_H (REG_SCL_DMA2_BASE + 0x9B) ++#define REG_SCL_DMA2_4E_L (REG_SCL_DMA2_BASE + 0x9C) ++#define REG_SCL_DMA2_4E_H (REG_SCL_DMA2_BASE + 0x9D) ++#define REG_SCL_DMA2_4F_L (REG_SCL_DMA2_BASE + 0x9E) ++#define REG_SCL_DMA2_4F_H (REG_SCL_DMA2_BASE + 0x9F) ++#define REG_SCL_DMA2_50_L (REG_SCL_DMA2_BASE + 0xA0) ++#define REG_SCL_DMA2_50_H (REG_SCL_DMA2_BASE + 0xA1) ++#define REG_SCL_DMA2_51_L (REG_SCL_DMA2_BASE + 0xA2) ++#define REG_SCL_DMA2_51_H (REG_SCL_DMA2_BASE + 0xA3) ++#define REG_SCL_DMA2_52_L (REG_SCL_DMA2_BASE + 0xA4) ++#define REG_SCL_DMA2_52_H (REG_SCL_DMA2_BASE + 0xA5) ++#define REG_SCL_DMA2_53_L (REG_SCL_DMA2_BASE + 0xA6) ++#define REG_SCL_DMA2_53_H (REG_SCL_DMA2_BASE + 0xA7) ++#define REG_SCL_DMA2_54_L (REG_SCL_DMA2_BASE + 0xA8) ++#define REG_SCL_DMA2_54_H (REG_SCL_DMA2_BASE + 0xA9) ++#define REG_SCL_DMA2_55_L (REG_SCL_DMA2_BASE + 0xAA) ++#define REG_SCL_DMA2_55_H (REG_SCL_DMA2_BASE + 0xAB) ++#define REG_SCL_DMA2_56_L (REG_SCL_DMA2_BASE + 0xAC) ++#define REG_SCL_DMA2_56_H (REG_SCL_DMA2_BASE + 0xAD) ++#define REG_SCL_DMA2_57_L (REG_SCL_DMA2_BASE + 0xAE) ++#define REG_SCL_DMA2_57_H (REG_SCL_DMA2_BASE + 0xAF) ++#define REG_SCL_DMA2_58_L (REG_SCL_DMA2_BASE + 0xB0) ++#define REG_SCL_DMA2_58_H (REG_SCL_DMA2_BASE + 0xB1) ++#define REG_SCL_DMA2_59_L (REG_SCL_DMA2_BASE + 0xB2) ++#define REG_SCL_DMA2_59_H (REG_SCL_DMA2_BASE + 0xB3) ++#define REG_SCL_DMA2_5A_L (REG_SCL_DMA2_BASE + 0xB4) ++#define REG_SCL_DMA2_5A_H (REG_SCL_DMA2_BASE + 0xB5) ++#define REG_SCL_DMA2_5B_L (REG_SCL_DMA2_BASE + 0xB6) ++#define REG_SCL_DMA2_5B_H (REG_SCL_DMA2_BASE + 0xB7) ++#define REG_SCL_DMA2_5C_L (REG_SCL_DMA2_BASE + 0xB8) ++#define REG_SCL_DMA2_5C_H (REG_SCL_DMA2_BASE + 0xB9) ++#define REG_SCL_DMA2_5D_L (REG_SCL_DMA2_BASE + 0xBA) ++#define REG_SCL_DMA2_5D_H (REG_SCL_DMA2_BASE + 0xBB) ++#define REG_SCL_DMA2_5E_L (REG_SCL_DMA2_BASE + 0xBC) ++#define REG_SCL_DMA2_5E_H (REG_SCL_DMA2_BASE + 0xBD) ++#define REG_SCL_DMA2_5F_L (REG_SCL_DMA2_BASE + 0xBE) ++#define REG_SCL_DMA2_5F_H (REG_SCL_DMA2_BASE + 0xBF) ++#define REG_SCL_DMA2_60_L (REG_SCL_DMA2_BASE + 0xC0) ++#define REG_SCL_DMA2_60_H (REG_SCL_DMA2_BASE + 0xC1) ++#define REG_SCL_DMA2_61_L (REG_SCL_DMA2_BASE + 0xC2) ++#define REG_SCL_DMA2_61_H (REG_SCL_DMA2_BASE + 0xC3) ++#define REG_SCL_DMA2_62_L (REG_SCL_DMA2_BASE + 0xC4) ++#define REG_SCL_DMA2_62_H (REG_SCL_DMA2_BASE + 0xC5) ++#define REG_SCL_DMA2_63_L (REG_SCL_DMA2_BASE + 0xC6) ++#define REG_SCL_DMA2_63_H (REG_SCL_DMA2_BASE + 0xC7) ++#define REG_SCL_DMA2_64_L (REG_SCL_DMA2_BASE + 0xC8) ++#define REG_SCL_DMA2_64_H (REG_SCL_DMA2_BASE + 0xC9) ++#define REG_SCL_DMA2_65_L (REG_SCL_DMA2_BASE + 0xCA) ++#define REG_SCL_DMA2_65_H (REG_SCL_DMA2_BASE + 0xCB) ++#define REG_SCL_DMA2_66_L (REG_SCL_DMA2_BASE + 0xCC) ++#define REG_SCL_DMA2_66_H (REG_SCL_DMA2_BASE + 0xCD) ++#define REG_SCL_DMA2_67_L (REG_SCL_DMA2_BASE + 0xCE) ++#define REG_SCL_DMA2_67_H (REG_SCL_DMA2_BASE + 0xCF) ++#define REG_SCL_DMA2_68_L (REG_SCL_DMA2_BASE + 0xD0) ++#define REG_SCL_DMA2_68_H (REG_SCL_DMA2_BASE + 0xD1) ++#define REG_SCL_DMA2_69_L (REG_SCL_DMA2_BASE + 0xD2) ++#define REG_SCL_DMA2_69_H (REG_SCL_DMA2_BASE + 0xD3) ++#define REG_SCL_DMA2_6A_L (REG_SCL_DMA2_BASE + 0xD4) ++#define REG_SCL_DMA2_6A_H (REG_SCL_DMA2_BASE + 0xD5) ++#define REG_SCL_DMA2_6B_L (REG_SCL_DMA2_BASE + 0xD6) ++#define REG_SCL_DMA2_6B_H (REG_SCL_DMA2_BASE + 0xD7) ++#define REG_SCL_DMA2_6C_L (REG_SCL_DMA2_BASE + 0xD8) ++#define REG_SCL_DMA2_6C_H (REG_SCL_DMA2_BASE + 0xD9) ++#define REG_SCL_DMA2_6D_L (REG_SCL_DMA2_BASE + 0xDA) ++#define REG_SCL_DMA2_6D_H (REG_SCL_DMA2_BASE + 0xDB) ++#define REG_SCL_DMA2_6E_L (REG_SCL_DMA2_BASE + 0xDC) ++#define REG_SCL_DMA2_6E_H (REG_SCL_DMA2_BASE + 0xDD) ++#define REG_SCL_DMA2_6F_L (REG_SCL_DMA2_BASE + 0xDE) ++#define REG_SCL_DMA2_6F_H (REG_SCL_DMA2_BASE + 0xDF) ++#define REG_SCL_DMA2_70_L (REG_SCL_DMA2_BASE + 0xE0) ++#define REG_SCL_DMA2_70_H (REG_SCL_DMA2_BASE + 0xE1) ++#define REG_SCL_DMA2_71_L (REG_SCL_DMA2_BASE + 0xE2) ++#define REG_SCL_DMA2_71_H (REG_SCL_DMA2_BASE + 0xE3) ++#define REG_SCL_DMA2_72_L (REG_SCL_DMA2_BASE + 0xE4) ++#define REG_SCL_DMA2_72_H (REG_SCL_DMA2_BASE + 0xE5) ++#define REG_SCL_DMA2_73_L (REG_SCL_DMA2_BASE + 0xE6) ++#define REG_SCL_DMA2_73_H (REG_SCL_DMA2_BASE + 0xE7) ++#define REG_SCL_DMA2_74_L (REG_SCL_DMA2_BASE + 0xE8) ++#define REG_SCL_DMA2_74_H (REG_SCL_DMA2_BASE + 0xE9) ++#define REG_SCL_DMA2_75_L (REG_SCL_DMA2_BASE + 0xEA) ++#define REG_SCL_DMA2_75_H (REG_SCL_DMA2_BASE + 0xEB) ++#define REG_SCL_DMA2_76_L (REG_SCL_DMA2_BASE + 0xEC) ++#define REG_SCL_DMA2_76_H (REG_SCL_DMA2_BASE + 0xED) ++#define REG_SCL_DMA2_77_L (REG_SCL_DMA2_BASE + 0xEE) ++#define REG_SCL_DMA2_77_H (REG_SCL_DMA2_BASE + 0xEF) ++#define REG_SCL_DMA2_78_L (REG_SCL_DMA2_BASE + 0xF0) ++#define REG_SCL_DMA2_78_H (REG_SCL_DMA2_BASE + 0xF1) ++#define REG_SCL_DMA2_79_L (REG_SCL_DMA2_BASE + 0xF2) ++#define REG_SCL_DMA2_79_H (REG_SCL_DMA2_BASE + 0xF3) ++#define REG_SCL_DMA2_7A_L (REG_SCL_DMA2_BASE + 0xF4) ++#define REG_SCL_DMA2_7A_H (REG_SCL_DMA2_BASE + 0xF5) ++#define REG_SCL_DMA2_7B_L (REG_SCL_DMA2_BASE + 0xF6) ++#define REG_SCL_DMA2_7B_H (REG_SCL_DMA2_BASE + 0xF7) ++#define REG_SCL_DMA2_7C_L (REG_SCL_DMA2_BASE + 0xF8) ++#define REG_SCL_DMA2_7C_H (REG_SCL_DMA2_BASE + 0xF9) ++#define REG_SCL_DMA2_7D_L (REG_SCL_DMA2_BASE + 0xFA) ++#define REG_SCL_DMA2_7D_H (REG_SCL_DMA2_BASE + 0xFB) ++#define REG_SCL_DMA2_7E_L (REG_SCL_DMA2_BASE + 0xFC) ++#define REG_SCL_DMA2_7E_H (REG_SCL_DMA2_BASE + 0xFD) ++#define REG_SCL_DMA2_7F_L (REG_SCL_DMA2_BASE + 0xFE) ++#define REG_SCL_DMA2_7F_H (REG_SCL_DMA2_BASE + 0xFF) ++ ++#define REG_SCL_DNR0_00_L (REG_SCL_DNR0_BASE + 0x00) ++#define REG_SCL_DNR0_00_H (REG_SCL_DNR0_BASE + 0x01) ++#define REG_SCL_DNR0_01_L (REG_SCL_DNR0_BASE + 0x02) ++#define REG_SCL_DNR0_01_H (REG_SCL_DNR0_BASE + 0x03) ++#define REG_SCL_DNR0_02_L (REG_SCL_DNR0_BASE + 0x04) ++#define REG_SCL_DNR0_02_H (REG_SCL_DNR0_BASE + 0x05) ++#define REG_SCL_DNR0_03_L (REG_SCL_DNR0_BASE + 0x06) ++#define REG_SCL_DNR0_03_H (REG_SCL_DNR0_BASE + 0x07) ++#define REG_SCL_DNR0_04_L (REG_SCL_DNR0_BASE + 0x08) ++#define REG_SCL_DNR0_04_H (REG_SCL_DNR0_BASE + 0x09) ++#define REG_SCL_DNR0_05_L (REG_SCL_DNR0_BASE + 0x0A) ++#define REG_SCL_DNR0_05_H (REG_SCL_DNR0_BASE + 0x0B) ++#define REG_SCL_DNR0_06_L (REG_SCL_DNR0_BASE + 0x0C) ++#define REG_SCL_DNR0_06_H (REG_SCL_DNR0_BASE + 0x0D) ++#define REG_SCL_DNR0_07_L (REG_SCL_DNR0_BASE + 0x0E) ++#define REG_SCL_DNR0_07_H (REG_SCL_DNR0_BASE + 0x0F) ++#define REG_SCL_DNR0_08_L (REG_SCL_DNR0_BASE + 0x10) ++#define REG_SCL_DNR0_08_H (REG_SCL_DNR0_BASE + 0x11) ++#define REG_SCL_DNR0_09_L (REG_SCL_DNR0_BASE + 0x12) ++#define REG_SCL_DNR0_09_H (REG_SCL_DNR0_BASE + 0x13) ++#define REG_SCL_DNR0_0A_L (REG_SCL_DNR0_BASE + 0x14) ++#define REG_SCL_DNR0_0A_H (REG_SCL_DNR0_BASE + 0x15) ++#define REG_SCL_DNR0_0B_L (REG_SCL_DNR0_BASE + 0x16) ++#define REG_SCL_DNR0_0B_H (REG_SCL_DNR0_BASE + 0x17) ++#define REG_SCL_DNR0_0C_L (REG_SCL_DNR0_BASE + 0x18) ++#define REG_SCL_DNR0_0C_H (REG_SCL_DNR0_BASE + 0x19) ++#define REG_SCL_DNR0_0D_L (REG_SCL_DNR0_BASE + 0x1A) ++#define REG_SCL_DNR0_0D_H (REG_SCL_DNR0_BASE + 0x1B) ++#define REG_SCL_DNR0_0E_L (REG_SCL_DNR0_BASE + 0x1C) ++#define REG_SCL_DNR0_0E_H (REG_SCL_DNR0_BASE + 0x1D) ++#define REG_SCL_DNR0_0F_L (REG_SCL_DNR0_BASE + 0x1E) ++#define REG_SCL_DNR0_0F_H (REG_SCL_DNR0_BASE + 0x1F) ++#define REG_SCL_DNR0_10_L (REG_SCL_DNR0_BASE + 0x20) ++#define REG_SCL_DNR0_10_H (REG_SCL_DNR0_BASE + 0x21) ++#define REG_SCL_DNR0_11_L (REG_SCL_DNR0_BASE + 0x22) ++#define REG_SCL_DNR0_11_H (REG_SCL_DNR0_BASE + 0x23) ++#define REG_SCL_DNR0_12_L (REG_SCL_DNR0_BASE + 0x24) ++#define REG_SCL_DNR0_12_H (REG_SCL_DNR0_BASE + 0x25) ++#define REG_SCL_DNR0_13_L (REG_SCL_DNR0_BASE + 0x26) ++#define REG_SCL_DNR0_13_H (REG_SCL_DNR0_BASE + 0x27) ++#define REG_SCL_DNR0_14_L (REG_SCL_DNR0_BASE + 0x28) ++#define REG_SCL_DNR0_14_H (REG_SCL_DNR0_BASE + 0x29) ++#define REG_SCL_DNR0_15_L (REG_SCL_DNR0_BASE + 0x2A) ++#define REG_SCL_DNR0_15_H (REG_SCL_DNR0_BASE + 0x2B) ++#define REG_SCL_DNR0_16_L (REG_SCL_DNR0_BASE + 0x2C) ++#define REG_SCL_DNR0_16_H (REG_SCL_DNR0_BASE + 0x2D) ++#define REG_SCL_DNR0_17_L (REG_SCL_DNR0_BASE + 0x2E) ++#define REG_SCL_DNR0_17_H (REG_SCL_DNR0_BASE + 0x2F) ++#define REG_SCL_DNR0_18_L (REG_SCL_DNR0_BASE + 0x30) ++#define REG_SCL_DNR0_18_H (REG_SCL_DNR0_BASE + 0x31) ++#define REG_SCL_DNR0_19_L (REG_SCL_DNR0_BASE + 0x32) ++#define REG_SCL_DNR0_19_H (REG_SCL_DNR0_BASE + 0x33) ++#define REG_SCL_DNR0_1A_L (REG_SCL_DNR0_BASE + 0x34) ++#define REG_SCL_DNR0_1A_H (REG_SCL_DNR0_BASE + 0x35) ++#define REG_SCL_DNR0_1B_L (REG_SCL_DNR0_BASE + 0x36) ++#define REG_SCL_DNR0_1B_H (REG_SCL_DNR0_BASE + 0x37) ++#define REG_SCL_DNR0_1C_L (REG_SCL_DNR0_BASE + 0x38) ++#define REG_SCL_DNR0_1C_H (REG_SCL_DNR0_BASE + 0x39) ++#define REG_SCL_DNR0_1D_L (REG_SCL_DNR0_BASE + 0x3A) ++#define REG_SCL_DNR0_1D_H (REG_SCL_DNR0_BASE + 0x3B) ++#define REG_SCL_DNR0_1E_L (REG_SCL_DNR0_BASE + 0x3C) ++#define REG_SCL_DNR0_1E_H (REG_SCL_DNR0_BASE + 0x3D) ++#define REG_SCL_DNR0_1F_L (REG_SCL_DNR0_BASE + 0x3E) ++#define REG_SCL_DNR0_1F_H (REG_SCL_DNR0_BASE + 0x3F) ++#define REG_SCL_DNR0_20_L (REG_SCL_DNR0_BASE + 0x40) ++#define REG_SCL_DNR0_20_H (REG_SCL_DNR0_BASE + 0x41) ++#define REG_SCL_DNR0_21_L (REG_SCL_DNR0_BASE + 0x42) ++#define REG_SCL_DNR0_21_H (REG_SCL_DNR0_BASE + 0x43) ++#define REG_SCL_DNR0_22_L (REG_SCL_DNR0_BASE + 0x44) ++#define REG_SCL_DNR0_22_H (REG_SCL_DNR0_BASE + 0x45) ++#define REG_SCL_DNR0_23_L (REG_SCL_DNR0_BASE + 0x46) ++#define REG_SCL_DNR0_23_H (REG_SCL_DNR0_BASE + 0x47) ++#define REG_SCL_DNR0_24_L (REG_SCL_DNR0_BASE + 0x48) ++#define REG_SCL_DNR0_24_H (REG_SCL_DNR0_BASE + 0x49) ++#define REG_SCL_DNR0_25_L (REG_SCL_DNR0_BASE + 0x4A) ++#define REG_SCL_DNR0_25_H (REG_SCL_DNR0_BASE + 0x4B) ++#define REG_SCL_DNR0_26_L (REG_SCL_DNR0_BASE + 0x4C) ++#define REG_SCL_DNR0_26_H (REG_SCL_DNR0_BASE + 0x4D) ++#define REG_SCL_DNR0_27_L (REG_SCL_DNR0_BASE + 0x4E) ++#define REG_SCL_DNR0_27_H (REG_SCL_DNR0_BASE + 0x4F) ++#define REG_SCL_DNR0_28_L (REG_SCL_DNR0_BASE + 0x50) ++#define REG_SCL_DNR0_28_H (REG_SCL_DNR0_BASE + 0x51) ++#define REG_SCL_DNR0_29_L (REG_SCL_DNR0_BASE + 0x52) ++#define REG_SCL_DNR0_29_H (REG_SCL_DNR0_BASE + 0x53) ++#define REG_SCL_DNR0_2A_L (REG_SCL_DNR0_BASE + 0x54) ++#define REG_SCL_DNR0_2A_H (REG_SCL_DNR0_BASE + 0x55) ++#define REG_SCL_DNR0_2B_L (REG_SCL_DNR0_BASE + 0x56) ++#define REG_SCL_DNR0_2B_H (REG_SCL_DNR0_BASE + 0x57) ++#define REG_SCL_DNR0_2C_L (REG_SCL_DNR0_BASE + 0x58) ++#define REG_SCL_DNR0_2C_H (REG_SCL_DNR0_BASE + 0x59) ++#define REG_SCL_DNR0_2D_L (REG_SCL_DNR0_BASE + 0x5A) ++#define REG_SCL_DNR0_2D_H (REG_SCL_DNR0_BASE + 0x5B) ++#define REG_SCL_DNR0_2E_L (REG_SCL_DNR0_BASE + 0x5C) ++#define REG_SCL_DNR0_2E_H (REG_SCL_DNR0_BASE + 0x5D) ++#define REG_SCL_DNR0_2F_L (REG_SCL_DNR0_BASE + 0x5E) ++#define REG_SCL_DNR0_2F_H (REG_SCL_DNR0_BASE + 0x5F) ++#define REG_SCL_DNR0_30_L (REG_SCL_DNR0_BASE + 0x60) ++#define REG_SCL_DNR0_30_H (REG_SCL_DNR0_BASE + 0x61) ++#define REG_SCL_DNR0_31_L (REG_SCL_DNR0_BASE + 0x62) ++#define REG_SCL_DNR0_31_H (REG_SCL_DNR0_BASE + 0x63) ++#define REG_SCL_DNR0_32_L (REG_SCL_DNR0_BASE + 0x64) ++#define REG_SCL_DNR0_32_H (REG_SCL_DNR0_BASE + 0x65) ++#define REG_SCL_DNR0_33_L (REG_SCL_DNR0_BASE + 0x66) ++#define REG_SCL_DNR0_33_H (REG_SCL_DNR0_BASE + 0x67) ++#define REG_SCL_DNR0_34_L (REG_SCL_DNR0_BASE + 0x68) ++#define REG_SCL_DNR0_34_H (REG_SCL_DNR0_BASE + 0x69) ++#define REG_SCL_DNR0_35_L (REG_SCL_DNR0_BASE + 0x6A) ++#define REG_SCL_DNR0_35_H (REG_SCL_DNR0_BASE + 0x6B) ++#define REG_SCL_DNR0_36_L (REG_SCL_DNR0_BASE + 0x6C) ++#define REG_SCL_DNR0_36_H (REG_SCL_DNR0_BASE + 0x6D) ++#define REG_SCL_DNR0_37_L (REG_SCL_DNR0_BASE + 0x6E) ++#define REG_SCL_DNR0_37_H (REG_SCL_DNR0_BASE + 0x6F) ++#define REG_SCL_DNR0_38_L (REG_SCL_DNR0_BASE + 0x70) ++#define REG_SCL_DNR0_38_H (REG_SCL_DNR0_BASE + 0x71) ++#define REG_SCL_DNR0_39_L (REG_SCL_DNR0_BASE + 0x72) ++#define REG_SCL_DNR0_39_H (REG_SCL_DNR0_BASE + 0x73) ++#define REG_SCL_DNR0_3A_L (REG_SCL_DNR0_BASE + 0x74) ++#define REG_SCL_DNR0_3A_H (REG_SCL_DNR0_BASE + 0x75) ++#define REG_SCL_DNR0_3B_L (REG_SCL_DNR0_BASE + 0x76) ++#define REG_SCL_DNR0_3B_H (REG_SCL_DNR0_BASE + 0x77) ++#define REG_SCL_DNR0_3C_L (REG_SCL_DNR0_BASE + 0x78) ++#define REG_SCL_DNR0_3C_H (REG_SCL_DNR0_BASE + 0x79) ++#define REG_SCL_DNR0_3D_L (REG_SCL_DNR0_BASE + 0x7A) ++#define REG_SCL_DNR0_3D_H (REG_SCL_DNR0_BASE + 0x7B) ++#define REG_SCL_DNR0_3E_L (REG_SCL_DNR0_BASE + 0x7C) ++#define REG_SCL_DNR0_3E_H (REG_SCL_DNR0_BASE + 0x7D) ++#define REG_SCL_DNR0_3F_L (REG_SCL_DNR0_BASE + 0x7E) ++#define REG_SCL_DNR0_3F_H (REG_SCL_DNR0_BASE + 0x7F) ++#define REG_SCL_DNR0_40_L (REG_SCL_DNR0_BASE + 0x80) ++#define REG_SCL_DNR0_40_H (REG_SCL_DNR0_BASE + 0x81) ++#define REG_SCL_DNR0_41_L (REG_SCL_DNR0_BASE + 0x82) ++#define REG_SCL_DNR0_41_H (REG_SCL_DNR0_BASE + 0x83) ++#define REG_SCL_DNR0_42_L (REG_SCL_DNR0_BASE + 0x84) ++#define REG_SCL_DNR0_42_H (REG_SCL_DNR0_BASE + 0x85) ++#define REG_SCL_DNR0_43_L (REG_SCL_DNR0_BASE + 0x86) ++#define REG_SCL_DNR0_43_H (REG_SCL_DNR0_BASE + 0x87) ++#define REG_SCL_DNR0_44_L (REG_SCL_DNR0_BASE + 0x88) ++#define REG_SCL_DNR0_44_H (REG_SCL_DNR0_BASE + 0x89) ++#define REG_SCL_DNR0_45_L (REG_SCL_DNR0_BASE + 0x8A) ++#define REG_SCL_DNR0_45_H (REG_SCL_DNR0_BASE + 0x8B) ++#define REG_SCL_DNR0_46_L (REG_SCL_DNR0_BASE + 0x8C) ++#define REG_SCL_DNR0_46_H (REG_SCL_DNR0_BASE + 0x8D) ++#define REG_SCL_DNR0_47_L (REG_SCL_DNR0_BASE + 0x8E) ++#define REG_SCL_DNR0_47_H (REG_SCL_DNR0_BASE + 0x8F) ++#define REG_SCL_DNR0_48_L (REG_SCL_DNR0_BASE + 0x90) ++#define REG_SCL_DNR0_48_H (REG_SCL_DNR0_BASE + 0x91) ++#define REG_SCL_DNR0_49_L (REG_SCL_DNR0_BASE + 0x92) ++#define REG_SCL_DNR0_49_H (REG_SCL_DNR0_BASE + 0x93) ++#define REG_SCL_DNR0_4A_L (REG_SCL_DNR0_BASE + 0x94) ++#define REG_SCL_DNR0_4A_H (REG_SCL_DNR0_BASE + 0x95) ++#define REG_SCL_DNR0_4B_L (REG_SCL_DNR0_BASE + 0x96) ++#define REG_SCL_DNR0_4B_H (REG_SCL_DNR0_BASE + 0x97) ++#define REG_SCL_DNR0_4C_L (REG_SCL_DNR0_BASE + 0x98) ++#define REG_SCL_DNR0_4C_H (REG_SCL_DNR0_BASE + 0x99) ++#define REG_SCL_DNR0_4D_L (REG_SCL_DNR0_BASE + 0x9A) ++#define REG_SCL_DNR0_4D_H (REG_SCL_DNR0_BASE + 0x9B) ++#define REG_SCL_DNR0_4E_L (REG_SCL_DNR0_BASE + 0x9C) ++#define REG_SCL_DNR0_4E_H (REG_SCL_DNR0_BASE + 0x9D) ++#define REG_SCL_DNR0_4F_L (REG_SCL_DNR0_BASE + 0x9E) ++#define REG_SCL_DNR0_4F_H (REG_SCL_DNR0_BASE + 0x9F) ++#define REG_SCL_DNR0_50_L (REG_SCL_DNR0_BASE + 0xA0) ++#define REG_SCL_DNR0_50_H (REG_SCL_DNR0_BASE + 0xA1) ++#define REG_SCL_DNR0_51_L (REG_SCL_DNR0_BASE + 0xA2) ++#define REG_SCL_DNR0_51_H (REG_SCL_DNR0_BASE + 0xA3) ++#define REG_SCL_DNR0_52_L (REG_SCL_DNR0_BASE + 0xA4) ++#define REG_SCL_DNR0_52_H (REG_SCL_DNR0_BASE + 0xA5) ++#define REG_SCL_DNR0_53_L (REG_SCL_DNR0_BASE + 0xA6) ++#define REG_SCL_DNR0_53_H (REG_SCL_DNR0_BASE + 0xA7) ++#define REG_SCL_DNR0_54_L (REG_SCL_DNR0_BASE + 0xA8) ++#define REG_SCL_DNR0_54_H (REG_SCL_DNR0_BASE + 0xA9) ++#define REG_SCL_DNR0_55_L (REG_SCL_DNR0_BASE + 0xAA) ++#define REG_SCL_DNR0_55_H (REG_SCL_DNR0_BASE + 0xAB) ++#define REG_SCL_DNR0_56_L (REG_SCL_DNR0_BASE + 0xAC) ++#define REG_SCL_DNR0_56_H (REG_SCL_DNR0_BASE + 0xAD) ++#define REG_SCL_DNR0_57_L (REG_SCL_DNR0_BASE + 0xAE) ++#define REG_SCL_DNR0_57_H (REG_SCL_DNR0_BASE + 0xAF) ++#define REG_SCL_DNR0_58_L (REG_SCL_DNR0_BASE + 0xB0) ++#define REG_SCL_DNR0_58_H (REG_SCL_DNR0_BASE + 0xB1) ++#define REG_SCL_DNR0_59_L (REG_SCL_DNR0_BASE + 0xB2) ++#define REG_SCL_DNR0_59_H (REG_SCL_DNR0_BASE + 0xB3) ++#define REG_SCL_DNR0_5A_L (REG_SCL_DNR0_BASE + 0xB4) ++#define REG_SCL_DNR0_5A_H (REG_SCL_DNR0_BASE + 0xB5) ++#define REG_SCL_DNR0_5B_L (REG_SCL_DNR0_BASE + 0xB6) ++#define REG_SCL_DNR0_5B_H (REG_SCL_DNR0_BASE + 0xB7) ++#define REG_SCL_DNR0_5C_L (REG_SCL_DNR0_BASE + 0xB8) ++#define REG_SCL_DNR0_5C_H (REG_SCL_DNR0_BASE + 0xB9) ++#define REG_SCL_DNR0_5D_L (REG_SCL_DNR0_BASE + 0xBA) ++#define REG_SCL_DNR0_5D_H (REG_SCL_DNR0_BASE + 0xBB) ++#define REG_SCL_DNR0_5E_L (REG_SCL_DNR0_BASE + 0xBC) ++#define REG_SCL_DNR0_5E_H (REG_SCL_DNR0_BASE + 0xBD) ++#define REG_SCL_DNR0_5F_L (REG_SCL_DNR0_BASE + 0xBE) ++#define REG_SCL_DNR0_5F_H (REG_SCL_DNR0_BASE + 0xBF) ++#define REG_SCL_DNR0_60_L (REG_SCL_DNR0_BASE + 0xC0) ++#define REG_SCL_DNR0_60_H (REG_SCL_DNR0_BASE + 0xC1) ++#define REG_SCL_DNR0_61_L (REG_SCL_DNR0_BASE + 0xC2) ++#define REG_SCL_DNR0_61_H (REG_SCL_DNR0_BASE + 0xC3) ++#define REG_SCL_DNR0_62_L (REG_SCL_DNR0_BASE + 0xC4) ++#define REG_SCL_DNR0_62_H (REG_SCL_DNR0_BASE + 0xC5) ++#define REG_SCL_DNR0_63_L (REG_SCL_DNR0_BASE + 0xC6) ++#define REG_SCL_DNR0_63_H (REG_SCL_DNR0_BASE + 0xC7) ++#define REG_SCL_DNR0_64_L (REG_SCL_DNR0_BASE + 0xC8) ++#define REG_SCL_DNR0_64_H (REG_SCL_DNR0_BASE + 0xC9) ++#define REG_SCL_DNR0_65_L (REG_SCL_DNR0_BASE + 0xCA) ++#define REG_SCL_DNR0_65_H (REG_SCL_DNR0_BASE + 0xCB) ++#define REG_SCL_DNR0_66_L (REG_SCL_DNR0_BASE + 0xCC) ++#define REG_SCL_DNR0_66_H (REG_SCL_DNR0_BASE + 0xCD) ++#define REG_SCL_DNR0_67_L (REG_SCL_DNR0_BASE + 0xCE) ++#define REG_SCL_DNR0_67_H (REG_SCL_DNR0_BASE + 0xCF) ++#define REG_SCL_DNR0_68_L (REG_SCL_DNR0_BASE + 0xD0) ++#define REG_SCL_DNR0_68_H (REG_SCL_DNR0_BASE + 0xD1) ++#define REG_SCL_DNR0_69_L (REG_SCL_DNR0_BASE + 0xD2) ++#define REG_SCL_DNR0_69_H (REG_SCL_DNR0_BASE + 0xD3) ++#define REG_SCL_DNR0_6A_L (REG_SCL_DNR0_BASE + 0xD4) ++#define REG_SCL_DNR0_6A_H (REG_SCL_DNR0_BASE + 0xD5) ++#define REG_SCL_DNR0_6B_L (REG_SCL_DNR0_BASE + 0xD6) ++#define REG_SCL_DNR0_6B_H (REG_SCL_DNR0_BASE + 0xD7) ++#define REG_SCL_DNR0_6C_L (REG_SCL_DNR0_BASE + 0xD8) ++#define REG_SCL_DNR0_6C_H (REG_SCL_DNR0_BASE + 0xD9) ++#define REG_SCL_DNR0_6D_L (REG_SCL_DNR0_BASE + 0xDA) ++#define REG_SCL_DNR0_6D_H (REG_SCL_DNR0_BASE + 0xDB) ++#define REG_SCL_DNR0_6E_L (REG_SCL_DNR0_BASE + 0xDC) ++#define REG_SCL_DNR0_6E_H (REG_SCL_DNR0_BASE + 0xDD) ++#define REG_SCL_DNR0_6F_L (REG_SCL_DNR0_BASE + 0xDE) ++#define REG_SCL_DNR0_6F_H (REG_SCL_DNR0_BASE + 0xDF) ++#define REG_SCL_DNR0_70_L (REG_SCL_DNR0_BASE + 0xE0) ++#define REG_SCL_DNR0_70_H (REG_SCL_DNR0_BASE + 0xE1) ++#define REG_SCL_DNR0_71_L (REG_SCL_DNR0_BASE + 0xE2) ++#define REG_SCL_DNR0_71_H (REG_SCL_DNR0_BASE + 0xE3) ++#define REG_SCL_DNR0_72_L (REG_SCL_DNR0_BASE + 0xE4) ++#define REG_SCL_DNR0_72_H (REG_SCL_DNR0_BASE + 0xE5) ++#define REG_SCL_DNR0_73_L (REG_SCL_DNR0_BASE + 0xE6) ++#define REG_SCL_DNR0_73_H (REG_SCL_DNR0_BASE + 0xE7) ++#define REG_SCL_DNR0_74_L (REG_SCL_DNR0_BASE + 0xE8) ++#define REG_SCL_DNR0_74_H (REG_SCL_DNR0_BASE + 0xE9) ++#define REG_SCL_DNR0_75_L (REG_SCL_DNR0_BASE + 0xEA) ++#define REG_SCL_DNR0_75_H (REG_SCL_DNR0_BASE + 0xEB) ++#define REG_SCL_DNR0_76_L (REG_SCL_DNR0_BASE + 0xEC) ++#define REG_SCL_DNR0_76_H (REG_SCL_DNR0_BASE + 0xED) ++#define REG_SCL_DNR0_77_L (REG_SCL_DNR0_BASE + 0xEE) ++#define REG_SCL_DNR0_77_H (REG_SCL_DNR0_BASE + 0xEF) ++#define REG_SCL_DNR0_78_L (REG_SCL_DNR0_BASE + 0xF0) ++#define REG_SCL_DNR0_78_H (REG_SCL_DNR0_BASE + 0xF1) ++#define REG_SCL_DNR0_79_L (REG_SCL_DNR0_BASE + 0xF2) ++#define REG_SCL_DNR0_79_H (REG_SCL_DNR0_BASE + 0xF3) ++#define REG_SCL_DNR0_7A_L (REG_SCL_DNR0_BASE + 0xF4) ++#define REG_SCL_DNR0_7A_H (REG_SCL_DNR0_BASE + 0xF5) ++#define REG_SCL_DNR0_7B_L (REG_SCL_DNR0_BASE + 0xF6) ++#define REG_SCL_DNR0_7B_H (REG_SCL_DNR0_BASE + 0xF7) ++#define REG_SCL_DNR0_7C_L (REG_SCL_DNR0_BASE + 0xF8) ++#define REG_SCL_DNR0_7C_H (REG_SCL_DNR0_BASE + 0xF9) ++#define REG_SCL_DNR0_7D_L (REG_SCL_DNR0_BASE + 0xFA) ++#define REG_SCL_DNR0_7D_H (REG_SCL_DNR0_BASE + 0xFB) ++#define REG_SCL_DNR0_7E_L (REG_SCL_DNR0_BASE + 0xFC) ++#define REG_SCL_DNR0_7E_H (REG_SCL_DNR0_BASE + 0xFD) ++#define REG_SCL_DNR0_7F_L (REG_SCL_DNR0_BASE + 0xFE) ++#define REG_SCL_DNR0_7F_H (REG_SCL_DNR0_BASE + 0xFF) ++ ++#define REG_SCL_DNR1_00_L (REG_SCL_DNR1_BASE + 0x00) ++#define REG_SCL_DNR1_00_H (REG_SCL_DNR1_BASE + 0x01) ++#define REG_SCL_DNR1_01_L (REG_SCL_DNR1_BASE + 0x02) ++#define REG_SCL_DNR1_01_H (REG_SCL_DNR1_BASE + 0x03) ++#define REG_SCL_DNR1_02_L (REG_SCL_DNR1_BASE + 0x04) ++#define REG_SCL_DNR1_02_H (REG_SCL_DNR1_BASE + 0x05) ++#define REG_SCL_DNR1_03_L (REG_SCL_DNR1_BASE + 0x06) ++#define REG_SCL_DNR1_03_H (REG_SCL_DNR1_BASE + 0x07) ++#define REG_SCL_DNR1_04_L (REG_SCL_DNR1_BASE + 0x08) ++#define REG_SCL_DNR1_04_H (REG_SCL_DNR1_BASE + 0x09) ++#define REG_SCL_DNR1_05_L (REG_SCL_DNR1_BASE + 0x0A) ++#define REG_SCL_DNR1_05_H (REG_SCL_DNR1_BASE + 0x0B) ++#define REG_SCL_DNR1_06_L (REG_SCL_DNR1_BASE + 0x0C) ++#define REG_SCL_DNR1_06_H (REG_SCL_DNR1_BASE + 0x0D) ++#define REG_SCL_DNR1_07_L (REG_SCL_DNR1_BASE + 0x0E) ++#define REG_SCL_DNR1_07_H (REG_SCL_DNR1_BASE + 0x0F) ++#define REG_SCL_DNR1_08_L (REG_SCL_DNR1_BASE + 0x10) ++#define REG_SCL_DNR1_08_H (REG_SCL_DNR1_BASE + 0x11) ++#define REG_SCL_DNR1_09_L (REG_SCL_DNR1_BASE + 0x12) ++#define REG_SCL_DNR1_09_H (REG_SCL_DNR1_BASE + 0x13) ++#define REG_SCL_DNR1_0A_L (REG_SCL_DNR1_BASE + 0x14) ++#define REG_SCL_DNR1_0A_H (REG_SCL_DNR1_BASE + 0x15) ++#define REG_SCL_DNR1_0B_L (REG_SCL_DNR1_BASE + 0x16) ++#define REG_SCL_DNR1_0B_H (REG_SCL_DNR1_BASE + 0x17) ++#define REG_SCL_DNR1_0C_L (REG_SCL_DNR1_BASE + 0x18) ++#define REG_SCL_DNR1_0C_H (REG_SCL_DNR1_BASE + 0x19) ++#define REG_SCL_DNR1_0D_L (REG_SCL_DNR1_BASE + 0x1A) ++#define REG_SCL_DNR1_0D_H (REG_SCL_DNR1_BASE + 0x1B) ++#define REG_SCL_DNR1_0E_L (REG_SCL_DNR1_BASE + 0x1C) ++#define REG_SCL_DNR1_0E_H (REG_SCL_DNR1_BASE + 0x1D) ++#define REG_SCL_DNR1_0F_L (REG_SCL_DNR1_BASE + 0x1E) ++#define REG_SCL_DNR1_0F_H (REG_SCL_DNR1_BASE + 0x1F) ++#define REG_SCL_DNR1_10_L (REG_SCL_DNR1_BASE + 0x20) ++#define REG_SCL_DNR1_10_H (REG_SCL_DNR1_BASE + 0x21) ++#define REG_SCL_DNR1_11_L (REG_SCL_DNR1_BASE + 0x22) ++#define REG_SCL_DNR1_11_H (REG_SCL_DNR1_BASE + 0x23) ++#define REG_SCL_DNR1_12_L (REG_SCL_DNR1_BASE + 0x24) ++#define REG_SCL_DNR1_12_H (REG_SCL_DNR1_BASE + 0x25) ++#define REG_SCL_DNR1_13_L (REG_SCL_DNR1_BASE + 0x26) ++#define REG_SCL_DNR1_13_H (REG_SCL_DNR1_BASE + 0x27) ++#define REG_SCL_DNR1_14_L (REG_SCL_DNR1_BASE + 0x28) ++#define REG_SCL_DNR1_14_H (REG_SCL_DNR1_BASE + 0x29) ++#define REG_SCL_DNR1_15_L (REG_SCL_DNR1_BASE + 0x2A) ++#define REG_SCL_DNR1_15_H (REG_SCL_DNR1_BASE + 0x2B) ++#define REG_SCL_DNR1_16_L (REG_SCL_DNR1_BASE + 0x2C) ++#define REG_SCL_DNR1_16_H (REG_SCL_DNR1_BASE + 0x2D) ++#define REG_SCL_DNR1_17_L (REG_SCL_DNR1_BASE + 0x2E) ++#define REG_SCL_DNR1_17_H (REG_SCL_DNR1_BASE + 0x2F) ++#define REG_SCL_DNR1_18_L (REG_SCL_DNR1_BASE + 0x30) ++#define REG_SCL_DNR1_18_H (REG_SCL_DNR1_BASE + 0x31) ++#define REG_SCL_DNR1_19_L (REG_SCL_DNR1_BASE + 0x32) ++#define REG_SCL_DNR1_19_H (REG_SCL_DNR1_BASE + 0x33) ++#define REG_SCL_DNR1_1A_L (REG_SCL_DNR1_BASE + 0x34) ++#define REG_SCL_DNR1_1A_H (REG_SCL_DNR1_BASE + 0x35) ++#define REG_SCL_DNR1_1B_L (REG_SCL_DNR1_BASE + 0x36) ++#define REG_SCL_DNR1_1B_H (REG_SCL_DNR1_BASE + 0x37) ++#define REG_SCL_DNR1_1C_L (REG_SCL_DNR1_BASE + 0x38) ++#define REG_SCL_DNR1_1C_H (REG_SCL_DNR1_BASE + 0x39) ++#define REG_SCL_DNR1_1D_L (REG_SCL_DNR1_BASE + 0x3A) ++#define REG_SCL_DNR1_1D_H (REG_SCL_DNR1_BASE + 0x3B) ++#define REG_SCL_DNR1_1E_L (REG_SCL_DNR1_BASE + 0x3C) ++#define REG_SCL_DNR1_1E_H (REG_SCL_DNR1_BASE + 0x3D) ++#define REG_SCL_DNR1_1F_L (REG_SCL_DNR1_BASE + 0x3E) ++#define REG_SCL_DNR1_1F_H (REG_SCL_DNR1_BASE + 0x3F) ++#define REG_SCL_DNR1_20_L (REG_SCL_DNR1_BASE + 0x40) ++#define REG_SCL_DNR1_20_H (REG_SCL_DNR1_BASE + 0x41) ++#define REG_SCL_DNR1_21_L (REG_SCL_DNR1_BASE + 0x42) ++#define REG_SCL_DNR1_21_H (REG_SCL_DNR1_BASE + 0x43) ++#define REG_SCL_DNR1_22_L (REG_SCL_DNR1_BASE + 0x44) ++#define REG_SCL_DNR1_22_H (REG_SCL_DNR1_BASE + 0x45) ++#define REG_SCL_DNR1_23_L (REG_SCL_DNR1_BASE + 0x46) ++#define REG_SCL_DNR1_23_H (REG_SCL_DNR1_BASE + 0x47) ++#define REG_SCL_DNR1_24_L (REG_SCL_DNR1_BASE + 0x48) ++#define REG_SCL_DNR1_24_H (REG_SCL_DNR1_BASE + 0x49) ++#define REG_SCL_DNR1_25_L (REG_SCL_DNR1_BASE + 0x4A) ++#define REG_SCL_DNR1_25_H (REG_SCL_DNR1_BASE + 0x4B) ++#define REG_SCL_DNR1_26_L (REG_SCL_DNR1_BASE + 0x4C) ++#define REG_SCL_DNR1_26_H (REG_SCL_DNR1_BASE + 0x4D) ++#define REG_SCL_DNR1_27_L (REG_SCL_DNR1_BASE + 0x4E) ++#define REG_SCL_DNR1_27_H (REG_SCL_DNR1_BASE + 0x4F) ++#define REG_SCL_DNR1_28_L (REG_SCL_DNR1_BASE + 0x50) ++#define REG_SCL_DNR1_28_H (REG_SCL_DNR1_BASE + 0x51) ++#define REG_SCL_DNR1_29_L (REG_SCL_DNR1_BASE + 0x52) ++#define REG_SCL_DNR1_29_H (REG_SCL_DNR1_BASE + 0x53) ++#define REG_SCL_DNR1_2A_L (REG_SCL_DNR1_BASE + 0x54) ++#define REG_SCL_DNR1_2A_H (REG_SCL_DNR1_BASE + 0x55) ++#define REG_SCL_DNR1_2B_L (REG_SCL_DNR1_BASE + 0x56) ++#define REG_SCL_DNR1_2B_H (REG_SCL_DNR1_BASE + 0x57) ++#define REG_SCL_DNR1_2C_L (REG_SCL_DNR1_BASE + 0x58) ++#define REG_SCL_DNR1_2C_H (REG_SCL_DNR1_BASE + 0x59) ++#define REG_SCL_DNR1_2D_L (REG_SCL_DNR1_BASE + 0x5A) ++#define REG_SCL_DNR1_2D_H (REG_SCL_DNR1_BASE + 0x5B) ++#define REG_SCL_DNR1_2E_L (REG_SCL_DNR1_BASE + 0x5C) ++#define REG_SCL_DNR1_2E_H (REG_SCL_DNR1_BASE + 0x5D) ++#define REG_SCL_DNR1_2F_L (REG_SCL_DNR1_BASE + 0x5E) ++#define REG_SCL_DNR1_2F_H (REG_SCL_DNR1_BASE + 0x5F) ++#define REG_SCL_DNR1_30_L (REG_SCL_DNR1_BASE + 0x60) ++#define REG_SCL_DNR1_30_H (REG_SCL_DNR1_BASE + 0x61) ++#define REG_SCL_DNR1_31_L (REG_SCL_DNR1_BASE + 0x62) ++#define REG_SCL_DNR1_31_H (REG_SCL_DNR1_BASE + 0x63) ++#define REG_SCL_DNR1_32_L (REG_SCL_DNR1_BASE + 0x64) ++#define REG_SCL_DNR1_32_H (REG_SCL_DNR1_BASE + 0x65) ++#define REG_SCL_DNR1_33_L (REG_SCL_DNR1_BASE + 0x66) ++#define REG_SCL_DNR1_33_H (REG_SCL_DNR1_BASE + 0x67) ++#define REG_SCL_DNR1_34_L (REG_SCL_DNR1_BASE + 0x68) ++#define REG_SCL_DNR1_34_H (REG_SCL_DNR1_BASE + 0x69) ++#define REG_SCL_DNR1_35_L (REG_SCL_DNR1_BASE + 0x6A) ++#define REG_SCL_DNR1_35_H (REG_SCL_DNR1_BASE + 0x6B) ++#define REG_SCL_DNR1_36_L (REG_SCL_DNR1_BASE + 0x6C) ++#define REG_SCL_DNR1_36_H (REG_SCL_DNR1_BASE + 0x6D) ++#define REG_SCL_DNR1_37_L (REG_SCL_DNR1_BASE + 0x6E) ++#define REG_SCL_DNR1_37_H (REG_SCL_DNR1_BASE + 0x6F) ++#define REG_SCL_DNR1_38_L (REG_SCL_DNR1_BASE + 0x70) ++#define REG_SCL_DNR1_38_H (REG_SCL_DNR1_BASE + 0x71) ++#define REG_SCL_DNR1_39_L (REG_SCL_DNR1_BASE + 0x72) ++#define REG_SCL_DNR1_39_H (REG_SCL_DNR1_BASE + 0x73) ++#define REG_SCL_DNR1_3A_L (REG_SCL_DNR1_BASE + 0x74) ++#define REG_SCL_DNR1_3A_H (REG_SCL_DNR1_BASE + 0x75) ++#define REG_SCL_DNR1_3B_L (REG_SCL_DNR1_BASE + 0x76) ++#define REG_SCL_DNR1_3B_H (REG_SCL_DNR1_BASE + 0x77) ++#define REG_SCL_DNR1_3C_L (REG_SCL_DNR1_BASE + 0x78) ++#define REG_SCL_DNR1_3C_H (REG_SCL_DNR1_BASE + 0x79) ++#define REG_SCL_DNR1_3D_L (REG_SCL_DNR1_BASE + 0x7A) ++#define REG_SCL_DNR1_3D_H (REG_SCL_DNR1_BASE + 0x7B) ++#define REG_SCL_DNR1_3E_L (REG_SCL_DNR1_BASE + 0x7C) ++#define REG_SCL_DNR1_3E_H (REG_SCL_DNR1_BASE + 0x7D) ++#define REG_SCL_DNR1_3F_L (REG_SCL_DNR1_BASE + 0x7E) ++#define REG_SCL_DNR1_3F_H (REG_SCL_DNR1_BASE + 0x7F) ++#define REG_SCL_DNR1_40_L (REG_SCL_DNR1_BASE + 0x80) ++#define REG_SCL_DNR1_40_H (REG_SCL_DNR1_BASE + 0x81) ++#define REG_SCL_DNR1_41_L (REG_SCL_DNR1_BASE + 0x82) ++#define REG_SCL_DNR1_41_H (REG_SCL_DNR1_BASE + 0x83) ++#define REG_SCL_DNR1_42_L (REG_SCL_DNR1_BASE + 0x84) ++#define REG_SCL_DNR1_42_H (REG_SCL_DNR1_BASE + 0x85) ++#define REG_SCL_DNR1_43_L (REG_SCL_DNR1_BASE + 0x86) ++#define REG_SCL_DNR1_43_H (REG_SCL_DNR1_BASE + 0x87) ++#define REG_SCL_DNR1_44_L (REG_SCL_DNR1_BASE + 0x88) ++#define REG_SCL_DNR1_44_H (REG_SCL_DNR1_BASE + 0x89) ++#define REG_SCL_DNR1_45_L (REG_SCL_DNR1_BASE + 0x8A) ++#define REG_SCL_DNR1_45_H (REG_SCL_DNR1_BASE + 0x8B) ++#define REG_SCL_DNR1_46_L (REG_SCL_DNR1_BASE + 0x8C) ++#define REG_SCL_DNR1_46_H (REG_SCL_DNR1_BASE + 0x8D) ++#define REG_SCL_DNR1_47_L (REG_SCL_DNR1_BASE + 0x8E) ++#define REG_SCL_DNR1_47_H (REG_SCL_DNR1_BASE + 0x8F) ++#define REG_SCL_DNR1_48_L (REG_SCL_DNR1_BASE + 0x90) ++#define REG_SCL_DNR1_48_H (REG_SCL_DNR1_BASE + 0x91) ++#define REG_SCL_DNR1_49_L (REG_SCL_DNR1_BASE + 0x92) ++#define REG_SCL_DNR1_49_H (REG_SCL_DNR1_BASE + 0x93) ++#define REG_SCL_DNR1_4A_L (REG_SCL_DNR1_BASE + 0x94) ++#define REG_SCL_DNR1_4A_H (REG_SCL_DNR1_BASE + 0x95) ++#define REG_SCL_DNR1_4B_L (REG_SCL_DNR1_BASE + 0x96) ++#define REG_SCL_DNR1_4B_H (REG_SCL_DNR1_BASE + 0x97) ++#define REG_SCL_DNR1_4C_L (REG_SCL_DNR1_BASE + 0x98) ++#define REG_SCL_DNR1_4C_H (REG_SCL_DNR1_BASE + 0x99) ++#define REG_SCL_DNR1_4D_L (REG_SCL_DNR1_BASE + 0x9A) ++#define REG_SCL_DNR1_4D_H (REG_SCL_DNR1_BASE + 0x9B) ++#define REG_SCL_DNR1_4E_L (REG_SCL_DNR1_BASE + 0x9C) ++#define REG_SCL_DNR1_4E_H (REG_SCL_DNR1_BASE + 0x9D) ++#define REG_SCL_DNR1_4F_L (REG_SCL_DNR1_BASE + 0x9E) ++#define REG_SCL_DNR1_4F_H (REG_SCL_DNR1_BASE + 0x9F) ++#define REG_SCL_DNR1_50_L (REG_SCL_DNR1_BASE + 0xA0) ++#define REG_SCL_DNR1_50_H (REG_SCL_DNR1_BASE + 0xA1) ++#define REG_SCL_DNR1_51_L (REG_SCL_DNR1_BASE + 0xA2) ++#define REG_SCL_DNR1_51_H (REG_SCL_DNR1_BASE + 0xA3) ++#define REG_SCL_DNR1_52_L (REG_SCL_DNR1_BASE + 0xA4) ++#define REG_SCL_DNR1_52_H (REG_SCL_DNR1_BASE + 0xA5) ++#define REG_SCL_DNR1_53_L (REG_SCL_DNR1_BASE + 0xA6) ++#define REG_SCL_DNR1_53_H (REG_SCL_DNR1_BASE + 0xA7) ++#define REG_SCL_DNR1_54_L (REG_SCL_DNR1_BASE + 0xA8) ++#define REG_SCL_DNR1_54_H (REG_SCL_DNR1_BASE + 0xA9) ++#define REG_SCL_DNR1_55_L (REG_SCL_DNR1_BASE + 0xAA) ++#define REG_SCL_DNR1_55_H (REG_SCL_DNR1_BASE + 0xAB) ++#define REG_SCL_DNR1_56_L (REG_SCL_DNR1_BASE + 0xAC) ++#define REG_SCL_DNR1_56_H (REG_SCL_DNR1_BASE + 0xAD) ++#define REG_SCL_DNR1_57_L (REG_SCL_DNR1_BASE + 0xAE) ++#define REG_SCL_DNR1_57_H (REG_SCL_DNR1_BASE + 0xAF) ++#define REG_SCL_DNR1_58_L (REG_SCL_DNR1_BASE + 0xB0) ++#define REG_SCL_DNR1_58_H (REG_SCL_DNR1_BASE + 0xB1) ++#define REG_SCL_DNR1_59_L (REG_SCL_DNR1_BASE + 0xB2) ++#define REG_SCL_DNR1_59_H (REG_SCL_DNR1_BASE + 0xB3) ++#define REG_SCL_DNR1_5A_L (REG_SCL_DNR1_BASE + 0xB4) ++#define REG_SCL_DNR1_5A_H (REG_SCL_DNR1_BASE + 0xB5) ++#define REG_SCL_DNR1_5B_L (REG_SCL_DNR1_BASE + 0xB6) ++#define REG_SCL_DNR1_5B_H (REG_SCL_DNR1_BASE + 0xB7) ++#define REG_SCL_DNR1_5C_L (REG_SCL_DNR1_BASE + 0xB8) ++#define REG_SCL_DNR1_5C_H (REG_SCL_DNR1_BASE + 0xB9) ++#define REG_SCL_DNR1_5D_L (REG_SCL_DNR1_BASE + 0xBA) ++#define REG_SCL_DNR1_5D_H (REG_SCL_DNR1_BASE + 0xBB) ++#define REG_SCL_DNR1_5E_L (REG_SCL_DNR1_BASE + 0xBC) ++#define REG_SCL_DNR1_5E_H (REG_SCL_DNR1_BASE + 0xBD) ++#define REG_SCL_DNR1_5F_L (REG_SCL_DNR1_BASE + 0xBE) ++#define REG_SCL_DNR1_5F_H (REG_SCL_DNR1_BASE + 0xBF) ++#define REG_SCL_DNR1_60_L (REG_SCL_DNR1_BASE + 0xC0) ++#define REG_SCL_DNR1_60_H (REG_SCL_DNR1_BASE + 0xC1) ++#define REG_SCL_DNR1_61_L (REG_SCL_DNR1_BASE + 0xC2) ++#define REG_SCL_DNR1_61_H (REG_SCL_DNR1_BASE + 0xC3) ++#define REG_SCL_DNR1_62_L (REG_SCL_DNR1_BASE + 0xC4) ++#define REG_SCL_DNR1_62_H (REG_SCL_DNR1_BASE + 0xC5) ++#define REG_SCL_DNR1_63_L (REG_SCL_DNR1_BASE + 0xC6) ++#define REG_SCL_DNR1_63_H (REG_SCL_DNR1_BASE + 0xC7) ++#define REG_SCL_DNR1_64_L (REG_SCL_DNR1_BASE + 0xC8) ++#define REG_SCL_DNR1_64_H (REG_SCL_DNR1_BASE + 0xC9) ++#define REG_SCL_DNR1_65_L (REG_SCL_DNR1_BASE + 0xCA) ++#define REG_SCL_DNR1_65_H (REG_SCL_DNR1_BASE + 0xCB) ++#define REG_SCL_DNR1_66_L (REG_SCL_DNR1_BASE + 0xCC) ++#define REG_SCL_DNR1_66_H (REG_SCL_DNR1_BASE + 0xCD) ++#define REG_SCL_DNR1_67_L (REG_SCL_DNR1_BASE + 0xCE) ++#define REG_SCL_DNR1_67_H (REG_SCL_DNR1_BASE + 0xCF) ++#define REG_SCL_DNR1_68_L (REG_SCL_DNR1_BASE + 0xD0) ++#define REG_SCL_DNR1_68_H (REG_SCL_DNR1_BASE + 0xD1) ++#define REG_SCL_DNR1_69_L (REG_SCL_DNR1_BASE + 0xD2) ++#define REG_SCL_DNR1_69_H (REG_SCL_DNR1_BASE + 0xD3) ++#define REG_SCL_DNR1_6A_L (REG_SCL_DNR1_BASE + 0xD4) ++#define REG_SCL_DNR1_6A_H (REG_SCL_DNR1_BASE + 0xD5) ++#define REG_SCL_DNR1_6B_L (REG_SCL_DNR1_BASE + 0xD6) ++#define REG_SCL_DNR1_6B_H (REG_SCL_DNR1_BASE + 0xD7) ++#define REG_SCL_DNR1_6C_L (REG_SCL_DNR1_BASE + 0xD8) ++#define REG_SCL_DNR1_6C_H (REG_SCL_DNR1_BASE + 0xD9) ++#define REG_SCL_DNR1_6D_L (REG_SCL_DNR1_BASE + 0xDA) ++#define REG_SCL_DNR1_6D_H (REG_SCL_DNR1_BASE + 0xDB) ++#define REG_SCL_DNR1_6E_L (REG_SCL_DNR1_BASE + 0xDC) ++#define REG_SCL_DNR1_6E_H (REG_SCL_DNR1_BASE + 0xDD) ++#define REG_SCL_DNR1_6F_L (REG_SCL_DNR1_BASE + 0xDE) ++#define REG_SCL_DNR1_6F_H (REG_SCL_DNR1_BASE + 0xDF) ++#define REG_SCL_DNR1_70_L (REG_SCL_DNR1_BASE + 0xE0) ++#define REG_SCL_DNR1_70_H (REG_SCL_DNR1_BASE + 0xE1) ++#define REG_SCL_DNR1_71_L (REG_SCL_DNR1_BASE + 0xE2) ++#define REG_SCL_DNR1_71_H (REG_SCL_DNR1_BASE + 0xE3) ++#define REG_SCL_DNR1_72_L (REG_SCL_DNR1_BASE + 0xE4) ++#define REG_SCL_DNR1_72_H (REG_SCL_DNR1_BASE + 0xE5) ++#define REG_SCL_DNR1_73_L (REG_SCL_DNR1_BASE + 0xE6) ++#define REG_SCL_DNR1_73_H (REG_SCL_DNR1_BASE + 0xE7) ++#define REG_SCL_DNR1_74_L (REG_SCL_DNR1_BASE + 0xE8) ++#define REG_SCL_DNR1_74_H (REG_SCL_DNR1_BASE + 0xE9) ++#define REG_SCL_DNR1_75_L (REG_SCL_DNR1_BASE + 0xEA) ++#define REG_SCL_DNR1_75_H (REG_SCL_DNR1_BASE + 0xEB) ++#define REG_SCL_DNR1_76_L (REG_SCL_DNR1_BASE + 0xEC) ++#define REG_SCL_DNR1_76_H (REG_SCL_DNR1_BASE + 0xED) ++#define REG_SCL_DNR1_77_L (REG_SCL_DNR1_BASE + 0xEE) ++#define REG_SCL_DNR1_77_H (REG_SCL_DNR1_BASE + 0xEF) ++#define REG_SCL_DNR1_78_L (REG_SCL_DNR1_BASE + 0xF0) ++#define REG_SCL_DNR1_78_H (REG_SCL_DNR1_BASE + 0xF1) ++#define REG_SCL_DNR1_79_L (REG_SCL_DNR1_BASE + 0xF2) ++#define REG_SCL_DNR1_79_H (REG_SCL_DNR1_BASE + 0xF3) ++#define REG_SCL_DNR1_7A_L (REG_SCL_DNR1_BASE + 0xF4) ++#define REG_SCL_DNR1_7A_H (REG_SCL_DNR1_BASE + 0xF5) ++#define REG_SCL_DNR1_7B_L (REG_SCL_DNR1_BASE + 0xF6) ++#define REG_SCL_DNR1_7B_H (REG_SCL_DNR1_BASE + 0xF7) ++#define REG_SCL_DNR1_7C_L (REG_SCL_DNR1_BASE + 0xF8) ++#define REG_SCL_DNR1_7C_H (REG_SCL_DNR1_BASE + 0xF9) ++#define REG_SCL_DNR1_7D_L (REG_SCL_DNR1_BASE + 0xFA) ++#define REG_SCL_DNR1_7D_H (REG_SCL_DNR1_BASE + 0xFB) ++#define REG_SCL_DNR1_7E_L (REG_SCL_DNR1_BASE + 0xFC) ++#define REG_SCL_DNR1_7E_H (REG_SCL_DNR1_BASE + 0xFD) ++#define REG_SCL_DNR1_7F_L (REG_SCL_DNR1_BASE + 0xFE) ++#define REG_SCL_DNR1_7F_H (REG_SCL_DNR1_BASE + 0xFF) ++ ++#define REG_SCL_DNR2_00_L (REG_SCL_DNR2_BASE + 0x00) ++#define REG_SCL_DNR2_00_H (REG_SCL_DNR2_BASE + 0x01) ++#define REG_SCL_DNR2_01_L (REG_SCL_DNR2_BASE + 0x02) ++#define REG_SCL_DNR2_01_H (REG_SCL_DNR2_BASE + 0x03) ++#define REG_SCL_DNR2_02_L (REG_SCL_DNR2_BASE + 0x04) ++#define REG_SCL_DNR2_02_H (REG_SCL_DNR2_BASE + 0x05) ++#define REG_SCL_DNR2_03_L (REG_SCL_DNR2_BASE + 0x06) ++#define REG_SCL_DNR2_03_H (REG_SCL_DNR2_BASE + 0x07) ++#define REG_SCL_DNR2_04_L (REG_SCL_DNR2_BASE + 0x08) ++#define REG_SCL_DNR2_04_H (REG_SCL_DNR2_BASE + 0x09) ++#define REG_SCL_DNR2_05_L (REG_SCL_DNR2_BASE + 0x0A) ++#define REG_SCL_DNR2_05_H (REG_SCL_DNR2_BASE + 0x0B) ++#define REG_SCL_DNR2_06_L (REG_SCL_DNR2_BASE + 0x0C) ++#define REG_SCL_DNR2_06_H (REG_SCL_DNR2_BASE + 0x0D) ++#define REG_SCL_DNR2_07_L (REG_SCL_DNR2_BASE + 0x0E) ++#define REG_SCL_DNR2_07_H (REG_SCL_DNR2_BASE + 0x0F) ++#define REG_SCL_DNR2_08_L (REG_SCL_DNR2_BASE + 0x10) ++#define REG_SCL_DNR2_08_H (REG_SCL_DNR2_BASE + 0x11) ++#define REG_SCL_DNR2_09_L (REG_SCL_DNR2_BASE + 0x12) ++#define REG_SCL_DNR2_09_H (REG_SCL_DNR2_BASE + 0x13) ++#define REG_SCL_DNR2_0A_L (REG_SCL_DNR2_BASE + 0x14) ++#define REG_SCL_DNR2_0A_H (REG_SCL_DNR2_BASE + 0x15) ++#define REG_SCL_DNR2_0B_L (REG_SCL_DNR2_BASE + 0x16) ++#define REG_SCL_DNR2_0B_H (REG_SCL_DNR2_BASE + 0x17) ++#define REG_SCL_DNR2_0C_L (REG_SCL_DNR2_BASE + 0x18) ++#define REG_SCL_DNR2_0C_H (REG_SCL_DNR2_BASE + 0x19) ++#define REG_SCL_DNR2_0D_L (REG_SCL_DNR2_BASE + 0x1A) ++#define REG_SCL_DNR2_0D_H (REG_SCL_DNR2_BASE + 0x1B) ++#define REG_SCL_DNR2_0E_L (REG_SCL_DNR2_BASE + 0x1C) ++#define REG_SCL_DNR2_0E_H (REG_SCL_DNR2_BASE + 0x1D) ++#define REG_SCL_DNR2_0F_L (REG_SCL_DNR2_BASE + 0x1E) ++#define REG_SCL_DNR2_0F_H (REG_SCL_DNR2_BASE + 0x1F) ++#define REG_SCL_DNR2_10_L (REG_SCL_DNR2_BASE + 0x20) ++#define REG_SCL_DNR2_10_H (REG_SCL_DNR2_BASE + 0x21) ++#define REG_SCL_DNR2_11_L (REG_SCL_DNR2_BASE + 0x22) ++#define REG_SCL_DNR2_11_H (REG_SCL_DNR2_BASE + 0x23) ++#define REG_SCL_DNR2_12_L (REG_SCL_DNR2_BASE + 0x24) ++#define REG_SCL_DNR2_12_H (REG_SCL_DNR2_BASE + 0x25) ++#define REG_SCL_DNR2_13_L (REG_SCL_DNR2_BASE + 0x26) ++#define REG_SCL_DNR2_13_H (REG_SCL_DNR2_BASE + 0x27) ++#define REG_SCL_DNR2_14_L (REG_SCL_DNR2_BASE + 0x28) ++#define REG_SCL_DNR2_14_H (REG_SCL_DNR2_BASE + 0x29) ++#define REG_SCL_DNR2_15_L (REG_SCL_DNR2_BASE + 0x2A) ++#define REG_SCL_DNR2_15_H (REG_SCL_DNR2_BASE + 0x2B) ++#define REG_SCL_DNR2_16_L (REG_SCL_DNR2_BASE + 0x2C) ++#define REG_SCL_DNR2_16_H (REG_SCL_DNR2_BASE + 0x2D) ++#define REG_SCL_DNR2_17_L (REG_SCL_DNR2_BASE + 0x2E) ++#define REG_SCL_DNR2_17_H (REG_SCL_DNR2_BASE + 0x2F) ++#define REG_SCL_DNR2_18_L (REG_SCL_DNR2_BASE + 0x30) ++#define REG_SCL_DNR2_18_H (REG_SCL_DNR2_BASE + 0x31) ++#define REG_SCL_DNR2_19_L (REG_SCL_DNR2_BASE + 0x32) ++#define REG_SCL_DNR2_19_H (REG_SCL_DNR2_BASE + 0x33) ++#define REG_SCL_DNR2_1A_L (REG_SCL_DNR2_BASE + 0x34) ++#define REG_SCL_DNR2_1A_H (REG_SCL_DNR2_BASE + 0x35) ++#define REG_SCL_DNR2_1B_L (REG_SCL_DNR2_BASE + 0x36) ++#define REG_SCL_DNR2_1B_H (REG_SCL_DNR2_BASE + 0x37) ++#define REG_SCL_DNR2_1C_L (REG_SCL_DNR2_BASE + 0x38) ++#define REG_SCL_DNR2_1C_H (REG_SCL_DNR2_BASE + 0x39) ++#define REG_SCL_DNR2_1D_L (REG_SCL_DNR2_BASE + 0x3A) ++#define REG_SCL_DNR2_1D_H (REG_SCL_DNR2_BASE + 0x3B) ++#define REG_SCL_DNR2_1E_L (REG_SCL_DNR2_BASE + 0x3C) ++#define REG_SCL_DNR2_1E_H (REG_SCL_DNR2_BASE + 0x3D) ++#define REG_SCL_DNR2_1F_L (REG_SCL_DNR2_BASE + 0x3E) ++#define REG_SCL_DNR2_1F_H (REG_SCL_DNR2_BASE + 0x3F) ++#define REG_SCL_DNR2_20_L (REG_SCL_DNR2_BASE + 0x40) ++#define REG_SCL_DNR2_20_H (REG_SCL_DNR2_BASE + 0x41) ++#define REG_SCL_DNR2_21_L (REG_SCL_DNR2_BASE + 0x42) ++#define REG_SCL_DNR2_21_H (REG_SCL_DNR2_BASE + 0x43) ++#define REG_SCL_DNR2_22_L (REG_SCL_DNR2_BASE + 0x44) ++#define REG_SCL_DNR2_22_H (REG_SCL_DNR2_BASE + 0x45) ++#define REG_SCL_DNR2_23_L (REG_SCL_DNR2_BASE + 0x46) ++#define REG_SCL_DNR2_23_H (REG_SCL_DNR2_BASE + 0x47) ++#define REG_SCL_DNR2_24_L (REG_SCL_DNR2_BASE + 0x48) ++#define REG_SCL_DNR2_24_H (REG_SCL_DNR2_BASE + 0x49) ++#define REG_SCL_DNR2_25_L (REG_SCL_DNR2_BASE + 0x4A) ++#define REG_SCL_DNR2_25_H (REG_SCL_DNR2_BASE + 0x4B) ++#define REG_SCL_DNR2_26_L (REG_SCL_DNR2_BASE + 0x4C) ++#define REG_SCL_DNR2_26_H (REG_SCL_DNR2_BASE + 0x4D) ++#define REG_SCL_DNR2_27_L (REG_SCL_DNR2_BASE + 0x4E) ++#define REG_SCL_DNR2_27_H (REG_SCL_DNR2_BASE + 0x4F) ++#define REG_SCL_DNR2_28_L (REG_SCL_DNR2_BASE + 0x50) ++#define REG_SCL_DNR2_28_H (REG_SCL_DNR2_BASE + 0x51) ++#define REG_SCL_DNR2_29_L (REG_SCL_DNR2_BASE + 0x52) ++#define REG_SCL_DNR2_29_H (REG_SCL_DNR2_BASE + 0x53) ++#define REG_SCL_DNR2_2A_L (REG_SCL_DNR2_BASE + 0x54) ++#define REG_SCL_DNR2_2A_H (REG_SCL_DNR2_BASE + 0x55) ++#define REG_SCL_DNR2_2B_L (REG_SCL_DNR2_BASE + 0x56) ++#define REG_SCL_DNR2_2B_H (REG_SCL_DNR2_BASE + 0x57) ++#define REG_SCL_DNR2_2C_L (REG_SCL_DNR2_BASE + 0x58) ++#define REG_SCL_DNR2_2C_H (REG_SCL_DNR2_BASE + 0x59) ++#define REG_SCL_DNR2_2D_L (REG_SCL_DNR2_BASE + 0x5A) ++#define REG_SCL_DNR2_2D_H (REG_SCL_DNR2_BASE + 0x5B) ++#define REG_SCL_DNR2_2E_L (REG_SCL_DNR2_BASE + 0x5C) ++#define REG_SCL_DNR2_2E_H (REG_SCL_DNR2_BASE + 0x5D) ++#define REG_SCL_DNR2_2F_L (REG_SCL_DNR2_BASE + 0x5E) ++#define REG_SCL_DNR2_2F_H (REG_SCL_DNR2_BASE + 0x5F) ++#define REG_SCL_DNR2_30_L (REG_SCL_DNR2_BASE + 0x60) ++#define REG_SCL_DNR2_30_H (REG_SCL_DNR2_BASE + 0x61) ++#define REG_SCL_DNR2_31_L (REG_SCL_DNR2_BASE + 0x62) ++#define REG_SCL_DNR2_31_H (REG_SCL_DNR2_BASE + 0x63) ++#define REG_SCL_DNR2_32_L (REG_SCL_DNR2_BASE + 0x64) ++#define REG_SCL_DNR2_32_H (REG_SCL_DNR2_BASE + 0x65) ++#define REG_SCL_DNR2_33_L (REG_SCL_DNR2_BASE + 0x66) ++#define REG_SCL_DNR2_33_H (REG_SCL_DNR2_BASE + 0x67) ++#define REG_SCL_DNR2_34_L (REG_SCL_DNR2_BASE + 0x68) ++#define REG_SCL_DNR2_34_H (REG_SCL_DNR2_BASE + 0x69) ++#define REG_SCL_DNR2_35_L (REG_SCL_DNR2_BASE + 0x6A) ++#define REG_SCL_DNR2_35_H (REG_SCL_DNR2_BASE + 0x6B) ++#define REG_SCL_DNR2_36_L (REG_SCL_DNR2_BASE + 0x6C) ++#define REG_SCL_DNR2_36_H (REG_SCL_DNR2_BASE + 0x6D) ++#define REG_SCL_DNR2_37_L (REG_SCL_DNR2_BASE + 0x6E) ++#define REG_SCL_DNR2_37_H (REG_SCL_DNR2_BASE + 0x6F) ++#define REG_SCL_DNR2_38_L (REG_SCL_DNR2_BASE + 0x70) ++#define REG_SCL_DNR2_38_H (REG_SCL_DNR2_BASE + 0x71) ++#define REG_SCL_DNR2_39_L (REG_SCL_DNR2_BASE + 0x72) ++#define REG_SCL_DNR2_39_H (REG_SCL_DNR2_BASE + 0x73) ++#define REG_SCL_DNR2_3A_L (REG_SCL_DNR2_BASE + 0x74) ++#define REG_SCL_DNR2_3A_H (REG_SCL_DNR2_BASE + 0x75) ++#define REG_SCL_DNR2_3B_L (REG_SCL_DNR2_BASE + 0x76) ++#define REG_SCL_DNR2_3B_H (REG_SCL_DNR2_BASE + 0x77) ++#define REG_SCL_DNR2_3C_L (REG_SCL_DNR2_BASE + 0x78) ++#define REG_SCL_DNR2_3C_H (REG_SCL_DNR2_BASE + 0x79) ++#define REG_SCL_DNR2_3D_L (REG_SCL_DNR2_BASE + 0x7A) ++#define REG_SCL_DNR2_3D_H (REG_SCL_DNR2_BASE + 0x7B) ++#define REG_SCL_DNR2_3E_L (REG_SCL_DNR2_BASE + 0x7C) ++#define REG_SCL_DNR2_3E_H (REG_SCL_DNR2_BASE + 0x7D) ++#define REG_SCL_DNR2_3F_L (REG_SCL_DNR2_BASE + 0x7E) ++#define REG_SCL_DNR2_3F_H (REG_SCL_DNR2_BASE + 0x7F) ++#define REG_SCL_DNR2_40_L (REG_SCL_DNR2_BASE + 0x80) ++#define REG_SCL_DNR2_40_H (REG_SCL_DNR2_BASE + 0x81) ++#define REG_SCL_DNR2_41_L (REG_SCL_DNR2_BASE + 0x82) ++#define REG_SCL_DNR2_41_H (REG_SCL_DNR2_BASE + 0x83) ++#define REG_SCL_DNR2_42_L (REG_SCL_DNR2_BASE + 0x84) ++#define REG_SCL_DNR2_42_H (REG_SCL_DNR2_BASE + 0x85) ++#define REG_SCL_DNR2_43_L (REG_SCL_DNR2_BASE + 0x86) ++#define REG_SCL_DNR2_43_H (REG_SCL_DNR2_BASE + 0x87) ++#define REG_SCL_DNR2_44_L (REG_SCL_DNR2_BASE + 0x88) ++#define REG_SCL_DNR2_44_H (REG_SCL_DNR2_BASE + 0x89) ++#define REG_SCL_DNR2_45_L (REG_SCL_DNR2_BASE + 0x8A) ++#define REG_SCL_DNR2_45_H (REG_SCL_DNR2_BASE + 0x8B) ++#define REG_SCL_DNR2_46_L (REG_SCL_DNR2_BASE + 0x8C) ++#define REG_SCL_DNR2_46_H (REG_SCL_DNR2_BASE + 0x8D) ++#define REG_SCL_DNR2_47_L (REG_SCL_DNR2_BASE + 0x8E) ++#define REG_SCL_DNR2_47_H (REG_SCL_DNR2_BASE + 0x8F) ++#define REG_SCL_DNR2_48_L (REG_SCL_DNR2_BASE + 0x90) ++#define REG_SCL_DNR2_48_H (REG_SCL_DNR2_BASE + 0x91) ++#define REG_SCL_DNR2_49_L (REG_SCL_DNR2_BASE + 0x92) ++#define REG_SCL_DNR2_49_H (REG_SCL_DNR2_BASE + 0x93) ++#define REG_SCL_DNR2_4A_L (REG_SCL_DNR2_BASE + 0x94) ++#define REG_SCL_DNR2_4A_H (REG_SCL_DNR2_BASE + 0x95) ++#define REG_SCL_DNR2_4B_L (REG_SCL_DNR2_BASE + 0x96) ++#define REG_SCL_DNR2_4B_H (REG_SCL_DNR2_BASE + 0x97) ++#define REG_SCL_DNR2_4C_L (REG_SCL_DNR2_BASE + 0x98) ++#define REG_SCL_DNR2_4C_H (REG_SCL_DNR2_BASE + 0x99) ++#define REG_SCL_DNR2_4D_L (REG_SCL_DNR2_BASE + 0x9A) ++#define REG_SCL_DNR2_4D_H (REG_SCL_DNR2_BASE + 0x9B) ++#define REG_SCL_DNR2_4E_L (REG_SCL_DNR2_BASE + 0x9C) ++#define REG_SCL_DNR2_4E_H (REG_SCL_DNR2_BASE + 0x9D) ++#define REG_SCL_DNR2_4F_L (REG_SCL_DNR2_BASE + 0x9E) ++#define REG_SCL_DNR2_4F_H (REG_SCL_DNR2_BASE + 0x9F) ++#define REG_SCL_DNR2_50_L (REG_SCL_DNR2_BASE + 0xA0) ++#define REG_SCL_DNR2_50_H (REG_SCL_DNR2_BASE + 0xA1) ++#define REG_SCL_DNR2_51_L (REG_SCL_DNR2_BASE + 0xA2) ++#define REG_SCL_DNR2_51_H (REG_SCL_DNR2_BASE + 0xA3) ++#define REG_SCL_DNR2_52_L (REG_SCL_DNR2_BASE + 0xA4) ++#define REG_SCL_DNR2_52_H (REG_SCL_DNR2_BASE + 0xA5) ++#define REG_SCL_DNR2_53_L (REG_SCL_DNR2_BASE + 0xA6) ++#define REG_SCL_DNR2_53_H (REG_SCL_DNR2_BASE + 0xA7) ++#define REG_SCL_DNR2_54_L (REG_SCL_DNR2_BASE + 0xA8) ++#define REG_SCL_DNR2_54_H (REG_SCL_DNR2_BASE + 0xA9) ++#define REG_SCL_DNR2_55_L (REG_SCL_DNR2_BASE + 0xAA) ++#define REG_SCL_DNR2_55_H (REG_SCL_DNR2_BASE + 0xAB) ++#define REG_SCL_DNR2_56_L (REG_SCL_DNR2_BASE + 0xAC) ++#define REG_SCL_DNR2_56_H (REG_SCL_DNR2_BASE + 0xAD) ++#define REG_SCL_DNR2_57_L (REG_SCL_DNR2_BASE + 0xAE) ++#define REG_SCL_DNR2_57_H (REG_SCL_DNR2_BASE + 0xAF) ++#define REG_SCL_DNR2_58_L (REG_SCL_DNR2_BASE + 0xB0) ++#define REG_SCL_DNR2_58_H (REG_SCL_DNR2_BASE + 0xB1) ++#define REG_SCL_DNR2_59_L (REG_SCL_DNR2_BASE + 0xB2) ++#define REG_SCL_DNR2_59_H (REG_SCL_DNR2_BASE + 0xB3) ++#define REG_SCL_DNR2_5A_L (REG_SCL_DNR2_BASE + 0xB4) ++#define REG_SCL_DNR2_5A_H (REG_SCL_DNR2_BASE + 0xB5) ++#define REG_SCL_DNR2_5B_L (REG_SCL_DNR2_BASE + 0xB6) ++#define REG_SCL_DNR2_5B_H (REG_SCL_DNR2_BASE + 0xB7) ++#define REG_SCL_DNR2_5C_L (REG_SCL_DNR2_BASE + 0xB8) ++#define REG_SCL_DNR2_5C_H (REG_SCL_DNR2_BASE + 0xB9) ++#define REG_SCL_DNR2_5D_L (REG_SCL_DNR2_BASE + 0xBA) ++#define REG_SCL_DNR2_5D_H (REG_SCL_DNR2_BASE + 0xBB) ++#define REG_SCL_DNR2_5E_L (REG_SCL_DNR2_BASE + 0xBC) ++#define REG_SCL_DNR2_5E_H (REG_SCL_DNR2_BASE + 0xBD) ++#define REG_SCL_DNR2_5F_L (REG_SCL_DNR2_BASE + 0xBE) ++#define REG_SCL_DNR2_5F_H (REG_SCL_DNR2_BASE + 0xBF) ++#define REG_SCL_DNR2_60_L (REG_SCL_DNR2_BASE + 0xC0) ++#define REG_SCL_DNR2_60_H (REG_SCL_DNR2_BASE + 0xC1) ++#define REG_SCL_DNR2_61_L (REG_SCL_DNR2_BASE + 0xC2) ++#define REG_SCL_DNR2_61_H (REG_SCL_DNR2_BASE + 0xC3) ++#define REG_SCL_DNR2_62_L (REG_SCL_DNR2_BASE + 0xC4) ++#define REG_SCL_DNR2_62_H (REG_SCL_DNR2_BASE + 0xC5) ++#define REG_SCL_DNR2_63_L (REG_SCL_DNR2_BASE + 0xC6) ++#define REG_SCL_DNR2_63_H (REG_SCL_DNR2_BASE + 0xC7) ++#define REG_SCL_DNR2_64_L (REG_SCL_DNR2_BASE + 0xC8) ++#define REG_SCL_DNR2_64_H (REG_SCL_DNR2_BASE + 0xC9) ++#define REG_SCL_DNR2_65_L (REG_SCL_DNR2_BASE + 0xCA) ++#define REG_SCL_DNR2_65_H (REG_SCL_DNR2_BASE + 0xCB) ++#define REG_SCL_DNR2_66_L (REG_SCL_DNR2_BASE + 0xCC) ++#define REG_SCL_DNR2_66_H (REG_SCL_DNR2_BASE + 0xCD) ++#define REG_SCL_DNR2_67_L (REG_SCL_DNR2_BASE + 0xCE) ++#define REG_SCL_DNR2_67_H (REG_SCL_DNR2_BASE + 0xCF) ++#define REG_SCL_DNR2_68_L (REG_SCL_DNR2_BASE + 0xD0) ++#define REG_SCL_DNR2_68_H (REG_SCL_DNR2_BASE + 0xD1) ++#define REG_SCL_DNR2_69_L (REG_SCL_DNR2_BASE + 0xD2) ++#define REG_SCL_DNR2_69_H (REG_SCL_DNR2_BASE + 0xD3) ++#define REG_SCL_DNR2_6A_L (REG_SCL_DNR2_BASE + 0xD4) ++#define REG_SCL_DNR2_6A_H (REG_SCL_DNR2_BASE + 0xD5) ++#define REG_SCL_DNR2_6B_L (REG_SCL_DNR2_BASE + 0xD6) ++#define REG_SCL_DNR2_6B_H (REG_SCL_DNR2_BASE + 0xD7) ++#define REG_SCL_DNR2_6C_L (REG_SCL_DNR2_BASE + 0xD8) ++#define REG_SCL_DNR2_6C_H (REG_SCL_DNR2_BASE + 0xD9) ++#define REG_SCL_DNR2_6D_L (REG_SCL_DNR2_BASE + 0xDA) ++#define REG_SCL_DNR2_6D_H (REG_SCL_DNR2_BASE + 0xDB) ++#define REG_SCL_DNR2_6E_L (REG_SCL_DNR2_BASE + 0xDC) ++#define REG_SCL_DNR2_6E_H (REG_SCL_DNR2_BASE + 0xDD) ++#define REG_SCL_DNR2_6F_L (REG_SCL_DNR2_BASE + 0xDE) ++#define REG_SCL_DNR2_6F_H (REG_SCL_DNR2_BASE + 0xDF) ++#define REG_SCL_DNR2_70_L (REG_SCL_DNR2_BASE + 0xE0) ++#define REG_SCL_DNR2_70_H (REG_SCL_DNR2_BASE + 0xE1) ++#define REG_SCL_DNR2_71_L (REG_SCL_DNR2_BASE + 0xE2) ++#define REG_SCL_DNR2_71_H (REG_SCL_DNR2_BASE + 0xE3) ++#define REG_SCL_DNR2_72_L (REG_SCL_DNR2_BASE + 0xE4) ++#define REG_SCL_DNR2_72_H (REG_SCL_DNR2_BASE + 0xE5) ++#define REG_SCL_DNR2_73_L (REG_SCL_DNR2_BASE + 0xE6) ++#define REG_SCL_DNR2_73_H (REG_SCL_DNR2_BASE + 0xE7) ++#define REG_SCL_DNR2_74_L (REG_SCL_DNR2_BASE + 0xE8) ++#define REG_SCL_DNR2_74_H (REG_SCL_DNR2_BASE + 0xE9) ++#define REG_SCL_DNR2_75_L (REG_SCL_DNR2_BASE + 0xEA) ++#define REG_SCL_DNR2_75_H (REG_SCL_DNR2_BASE + 0xEB) ++#define REG_SCL_DNR2_76_L (REG_SCL_DNR2_BASE + 0xEC) ++#define REG_SCL_DNR2_76_H (REG_SCL_DNR2_BASE + 0xED) ++#define REG_SCL_DNR2_77_L (REG_SCL_DNR2_BASE + 0xEE) ++#define REG_SCL_DNR2_77_H (REG_SCL_DNR2_BASE + 0xEF) ++#define REG_SCL_DNR2_78_L (REG_SCL_DNR2_BASE + 0xF0) ++#define REG_SCL_DNR2_78_H (REG_SCL_DNR2_BASE + 0xF1) ++#define REG_SCL_DNR2_79_L (REG_SCL_DNR2_BASE + 0xF2) ++#define REG_SCL_DNR2_79_H (REG_SCL_DNR2_BASE + 0xF3) ++#define REG_SCL_DNR2_7A_L (REG_SCL_DNR2_BASE + 0xF4) ++#define REG_SCL_DNR2_7A_H (REG_SCL_DNR2_BASE + 0xF5) ++#define REG_SCL_DNR2_7B_L (REG_SCL_DNR2_BASE + 0xF6) ++#define REG_SCL_DNR2_7B_H (REG_SCL_DNR2_BASE + 0xF7) ++#define REG_SCL_DNR2_7C_L (REG_SCL_DNR2_BASE + 0xF8) ++#define REG_SCL_DNR2_7C_H (REG_SCL_DNR2_BASE + 0xF9) ++#define REG_SCL_DNR2_7D_L (REG_SCL_DNR2_BASE + 0xFA) ++#define REG_SCL_DNR2_7D_H (REG_SCL_DNR2_BASE + 0xFB) ++#define REG_SCL_DNR2_7E_L (REG_SCL_DNR2_BASE + 0xFC) ++#define REG_SCL_DNR2_7E_H (REG_SCL_DNR2_BASE + 0xFD) ++#define REG_SCL_DNR2_7F_L (REG_SCL_DNR2_BASE + 0xFE) ++#define REG_SCL_DNR2_7F_H (REG_SCL_DNR2_BASE + 0xFF) ++ ++#define REG_SCL_NLM0_00_L (REG_SCL_NLM0_BASE + 0x00) ++#define REG_SCL_NLM0_00_H (REG_SCL_NLM0_BASE + 0x01) ++#define REG_SCL_NLM0_01_L (REG_SCL_NLM0_BASE + 0x02) ++#define REG_SCL_NLM0_01_H (REG_SCL_NLM0_BASE + 0x03) ++#define REG_SCL_NLM0_02_L (REG_SCL_NLM0_BASE + 0x04) ++#define REG_SCL_NLM0_02_H (REG_SCL_NLM0_BASE + 0x05) ++#define REG_SCL_NLM0_03_L (REG_SCL_NLM0_BASE + 0x06) ++#define REG_SCL_NLM0_03_H (REG_SCL_NLM0_BASE + 0x07) ++#define REG_SCL_NLM0_04_L (REG_SCL_NLM0_BASE + 0x08) ++#define REG_SCL_NLM0_04_H (REG_SCL_NLM0_BASE + 0x09) ++#define REG_SCL_NLM0_05_L (REG_SCL_NLM0_BASE + 0x0A) ++#define REG_SCL_NLM0_05_H (REG_SCL_NLM0_BASE + 0x0B) ++#define REG_SCL_NLM0_06_L (REG_SCL_NLM0_BASE + 0x0C) ++#define REG_SCL_NLM0_06_H (REG_SCL_NLM0_BASE + 0x0D) ++#define REG_SCL_NLM0_07_L (REG_SCL_NLM0_BASE + 0x0E) ++#define REG_SCL_NLM0_07_H (REG_SCL_NLM0_BASE + 0x0F) ++#define REG_SCL_NLM0_08_L (REG_SCL_NLM0_BASE + 0x10) ++#define REG_SCL_NLM0_08_H (REG_SCL_NLM0_BASE + 0x11) ++#define REG_SCL_NLM0_09_L (REG_SCL_NLM0_BASE + 0x12) ++#define REG_SCL_NLM0_09_H (REG_SCL_NLM0_BASE + 0x13) ++#define REG_SCL_NLM0_0A_L (REG_SCL_NLM0_BASE + 0x14) ++#define REG_SCL_NLM0_0A_H (REG_SCL_NLM0_BASE + 0x15) ++#define REG_SCL_NLM0_0B_L (REG_SCL_NLM0_BASE + 0x16) ++#define REG_SCL_NLM0_0B_H (REG_SCL_NLM0_BASE + 0x17) ++#define REG_SCL_NLM0_0C_L (REG_SCL_NLM0_BASE + 0x18) ++#define REG_SCL_NLM0_0C_H (REG_SCL_NLM0_BASE + 0x19) ++#define REG_SCL_NLM0_0D_L (REG_SCL_NLM0_BASE + 0x1A) ++#define REG_SCL_NLM0_0D_H (REG_SCL_NLM0_BASE + 0x1B) ++#define REG_SCL_NLM0_0E_L (REG_SCL_NLM0_BASE + 0x1C) ++#define REG_SCL_NLM0_0E_H (REG_SCL_NLM0_BASE + 0x1D) ++#define REG_SCL_NLM0_0F_L (REG_SCL_NLM0_BASE + 0x1E) ++#define REG_SCL_NLM0_0F_H (REG_SCL_NLM0_BASE + 0x1F) ++#define REG_SCL_NLM0_10_L (REG_SCL_NLM0_BASE + 0x20) ++#define REG_SCL_NLM0_10_H (REG_SCL_NLM0_BASE + 0x21) ++#define REG_SCL_NLM0_11_L (REG_SCL_NLM0_BASE + 0x22) ++#define REG_SCL_NLM0_11_H (REG_SCL_NLM0_BASE + 0x23) ++#define REG_SCL_NLM0_12_L (REG_SCL_NLM0_BASE + 0x24) ++#define REG_SCL_NLM0_12_H (REG_SCL_NLM0_BASE + 0x25) ++#define REG_SCL_NLM0_13_L (REG_SCL_NLM0_BASE + 0x26) ++#define REG_SCL_NLM0_13_H (REG_SCL_NLM0_BASE + 0x27) ++#define REG_SCL_NLM0_14_L (REG_SCL_NLM0_BASE + 0x28) ++#define REG_SCL_NLM0_14_H (REG_SCL_NLM0_BASE + 0x29) ++#define REG_SCL_NLM0_15_L (REG_SCL_NLM0_BASE + 0x2A) ++#define REG_SCL_NLM0_15_H (REG_SCL_NLM0_BASE + 0x2B) ++#define REG_SCL_NLM0_16_L (REG_SCL_NLM0_BASE + 0x2C) ++#define REG_SCL_NLM0_16_H (REG_SCL_NLM0_BASE + 0x2D) ++#define REG_SCL_NLM0_17_L (REG_SCL_NLM0_BASE + 0x2E) ++#define REG_SCL_NLM0_17_H (REG_SCL_NLM0_BASE + 0x2F) ++#define REG_SCL_NLM0_18_L (REG_SCL_NLM0_BASE + 0x30) ++#define REG_SCL_NLM0_18_H (REG_SCL_NLM0_BASE + 0x31) ++#define REG_SCL_NLM0_19_L (REG_SCL_NLM0_BASE + 0x32) ++#define REG_SCL_NLM0_19_H (REG_SCL_NLM0_BASE + 0x33) ++#define REG_SCL_NLM0_1A_L (REG_SCL_NLM0_BASE + 0x34) ++#define REG_SCL_NLM0_1A_H (REG_SCL_NLM0_BASE + 0x35) ++#define REG_SCL_NLM0_1B_L (REG_SCL_NLM0_BASE + 0x36) ++#define REG_SCL_NLM0_1B_H (REG_SCL_NLM0_BASE + 0x37) ++#define REG_SCL_NLM0_1C_L (REG_SCL_NLM0_BASE + 0x38) ++#define REG_SCL_NLM0_1C_H (REG_SCL_NLM0_BASE + 0x39) ++#define REG_SCL_NLM0_1D_L (REG_SCL_NLM0_BASE + 0x3A) ++#define REG_SCL_NLM0_1D_H (REG_SCL_NLM0_BASE + 0x3B) ++#define REG_SCL_NLM0_1E_L (REG_SCL_NLM0_BASE + 0x3C) ++#define REG_SCL_NLM0_1E_H (REG_SCL_NLM0_BASE + 0x3D) ++#define REG_SCL_NLM0_1F_L (REG_SCL_NLM0_BASE + 0x3E) ++#define REG_SCL_NLM0_1F_H (REG_SCL_NLM0_BASE + 0x3F) ++#define REG_SCL_NLM0_20_L (REG_SCL_NLM0_BASE + 0x40) ++#define REG_SCL_NLM0_20_H (REG_SCL_NLM0_BASE + 0x41) ++#define REG_SCL_NLM0_21_L (REG_SCL_NLM0_BASE + 0x42) ++#define REG_SCL_NLM0_21_H (REG_SCL_NLM0_BASE + 0x43) ++#define REG_SCL_NLM0_22_L (REG_SCL_NLM0_BASE + 0x44) ++#define REG_SCL_NLM0_22_H (REG_SCL_NLM0_BASE + 0x45) ++#define REG_SCL_NLM0_23_L (REG_SCL_NLM0_BASE + 0x46) ++#define REG_SCL_NLM0_23_H (REG_SCL_NLM0_BASE + 0x47) ++#define REG_SCL_NLM0_24_L (REG_SCL_NLM0_BASE + 0x48) ++#define REG_SCL_NLM0_24_H (REG_SCL_NLM0_BASE + 0x49) ++#define REG_SCL_NLM0_25_L (REG_SCL_NLM0_BASE + 0x4A) ++#define REG_SCL_NLM0_25_H (REG_SCL_NLM0_BASE + 0x4B) ++#define REG_SCL_NLM0_26_L (REG_SCL_NLM0_BASE + 0x4C) ++#define REG_SCL_NLM0_26_H (REG_SCL_NLM0_BASE + 0x4D) ++#define REG_SCL_NLM0_27_L (REG_SCL_NLM0_BASE + 0x4E) ++#define REG_SCL_NLM0_27_H (REG_SCL_NLM0_BASE + 0x4F) ++#define REG_SCL_NLM0_28_L (REG_SCL_NLM0_BASE + 0x50) ++#define REG_SCL_NLM0_28_H (REG_SCL_NLM0_BASE + 0x51) ++#define REG_SCL_NLM0_29_L (REG_SCL_NLM0_BASE + 0x52) ++#define REG_SCL_NLM0_29_H (REG_SCL_NLM0_BASE + 0x53) ++#define REG_SCL_NLM0_2A_L (REG_SCL_NLM0_BASE + 0x54) ++#define REG_SCL_NLM0_2A_H (REG_SCL_NLM0_BASE + 0x55) ++#define REG_SCL_NLM0_2B_L (REG_SCL_NLM0_BASE + 0x56) ++#define REG_SCL_NLM0_2B_H (REG_SCL_NLM0_BASE + 0x57) ++#define REG_SCL_NLM0_2C_L (REG_SCL_NLM0_BASE + 0x58) ++#define REG_SCL_NLM0_2C_H (REG_SCL_NLM0_BASE + 0x59) ++#define REG_SCL_NLM0_2D_L (REG_SCL_NLM0_BASE + 0x5A) ++#define REG_SCL_NLM0_2D_H (REG_SCL_NLM0_BASE + 0x5B) ++#define REG_SCL_NLM0_2E_L (REG_SCL_NLM0_BASE + 0x5C) ++#define REG_SCL_NLM0_2E_H (REG_SCL_NLM0_BASE + 0x5D) ++#define REG_SCL_NLM0_2F_L (REG_SCL_NLM0_BASE + 0x5E) ++#define REG_SCL_NLM0_2F_H (REG_SCL_NLM0_BASE + 0x5F) ++#define REG_SCL_NLM0_30_L (REG_SCL_NLM0_BASE + 0x60) ++#define REG_SCL_NLM0_30_H (REG_SCL_NLM0_BASE + 0x61) ++#define REG_SCL_NLM0_31_L (REG_SCL_NLM0_BASE + 0x62) ++#define REG_SCL_NLM0_31_H (REG_SCL_NLM0_BASE + 0x63) ++#define REG_SCL_NLM0_32_L (REG_SCL_NLM0_BASE + 0x64) ++#define REG_SCL_NLM0_32_H (REG_SCL_NLM0_BASE + 0x65) ++#define REG_SCL_NLM0_33_L (REG_SCL_NLM0_BASE + 0x66) ++#define REG_SCL_NLM0_33_H (REG_SCL_NLM0_BASE + 0x67) ++#define REG_SCL_NLM0_34_L (REG_SCL_NLM0_BASE + 0x68) ++#define REG_SCL_NLM0_34_H (REG_SCL_NLM0_BASE + 0x69) ++#define REG_SCL_NLM0_35_L (REG_SCL_NLM0_BASE + 0x6A) ++#define REG_SCL_NLM0_35_H (REG_SCL_NLM0_BASE + 0x6B) ++#define REG_SCL_NLM0_36_L (REG_SCL_NLM0_BASE + 0x6C) ++#define REG_SCL_NLM0_36_H (REG_SCL_NLM0_BASE + 0x6D) ++#define REG_SCL_NLM0_37_L (REG_SCL_NLM0_BASE + 0x6E) ++#define REG_SCL_NLM0_37_H (REG_SCL_NLM0_BASE + 0x6F) ++#define REG_SCL_NLM0_38_L (REG_SCL_NLM0_BASE + 0x70) ++#define REG_SCL_NLM0_38_H (REG_SCL_NLM0_BASE + 0x71) ++#define REG_SCL_NLM0_39_L (REG_SCL_NLM0_BASE + 0x72) ++#define REG_SCL_NLM0_39_H (REG_SCL_NLM0_BASE + 0x73) ++#define REG_SCL_NLM0_3A_L (REG_SCL_NLM0_BASE + 0x74) ++#define REG_SCL_NLM0_3A_H (REG_SCL_NLM0_BASE + 0x75) ++#define REG_SCL_NLM0_3B_L (REG_SCL_NLM0_BASE + 0x76) ++#define REG_SCL_NLM0_3B_H (REG_SCL_NLM0_BASE + 0x77) ++#define REG_SCL_NLM0_3C_L (REG_SCL_NLM0_BASE + 0x78) ++#define REG_SCL_NLM0_3C_H (REG_SCL_NLM0_BASE + 0x79) ++#define REG_SCL_NLM0_3D_L (REG_SCL_NLM0_BASE + 0x7A) ++#define REG_SCL_NLM0_3D_H (REG_SCL_NLM0_BASE + 0x7B) ++#define REG_SCL_NLM0_3E_L (REG_SCL_NLM0_BASE + 0x7C) ++#define REG_SCL_NLM0_3E_H (REG_SCL_NLM0_BASE + 0x7D) ++#define REG_SCL_NLM0_3F_L (REG_SCL_NLM0_BASE + 0x7E) ++#define REG_SCL_NLM0_3F_H (REG_SCL_NLM0_BASE + 0x7F) ++#define REG_SCL_NLM0_40_L (REG_SCL_NLM0_BASE + 0x80) ++#define REG_SCL_NLM0_40_H (REG_SCL_NLM0_BASE + 0x81) ++#define REG_SCL_NLM0_41_L (REG_SCL_NLM0_BASE + 0x82) ++#define REG_SCL_NLM0_41_H (REG_SCL_NLM0_BASE + 0x83) ++#define REG_SCL_NLM0_42_L (REG_SCL_NLM0_BASE + 0x84) ++#define REG_SCL_NLM0_42_H (REG_SCL_NLM0_BASE + 0x85) ++#define REG_SCL_NLM0_43_L (REG_SCL_NLM0_BASE + 0x86) ++#define REG_SCL_NLM0_43_H (REG_SCL_NLM0_BASE + 0x87) ++#define REG_SCL_NLM0_44_L (REG_SCL_NLM0_BASE + 0x88) ++#define REG_SCL_NLM0_44_H (REG_SCL_NLM0_BASE + 0x89) ++#define REG_SCL_NLM0_45_L (REG_SCL_NLM0_BASE + 0x8A) ++#define REG_SCL_NLM0_45_H (REG_SCL_NLM0_BASE + 0x8B) ++#define REG_SCL_NLM0_46_L (REG_SCL_NLM0_BASE + 0x8C) ++#define REG_SCL_NLM0_46_H (REG_SCL_NLM0_BASE + 0x8D) ++#define REG_SCL_NLM0_47_L (REG_SCL_NLM0_BASE + 0x8E) ++#define REG_SCL_NLM0_47_H (REG_SCL_NLM0_BASE + 0x8F) ++#define REG_SCL_NLM0_48_L (REG_SCL_NLM0_BASE + 0x90) ++#define REG_SCL_NLM0_48_H (REG_SCL_NLM0_BASE + 0x91) ++#define REG_SCL_NLM0_49_L (REG_SCL_NLM0_BASE + 0x92) ++#define REG_SCL_NLM0_49_H (REG_SCL_NLM0_BASE + 0x93) ++#define REG_SCL_NLM0_4A_L (REG_SCL_NLM0_BASE + 0x94) ++#define REG_SCL_NLM0_4A_H (REG_SCL_NLM0_BASE + 0x95) ++#define REG_SCL_NLM0_4B_L (REG_SCL_NLM0_BASE + 0x96) ++#define REG_SCL_NLM0_4B_H (REG_SCL_NLM0_BASE + 0x97) ++#define REG_SCL_NLM0_4C_L (REG_SCL_NLM0_BASE + 0x98) ++#define REG_SCL_NLM0_4C_H (REG_SCL_NLM0_BASE + 0x99) ++#define REG_SCL_NLM0_4D_L (REG_SCL_NLM0_BASE + 0x9A) ++#define REG_SCL_NLM0_4D_H (REG_SCL_NLM0_BASE + 0x9B) ++#define REG_SCL_NLM0_4E_L (REG_SCL_NLM0_BASE + 0x9C) ++#define REG_SCL_NLM0_4E_H (REG_SCL_NLM0_BASE + 0x9D) ++#define REG_SCL_NLM0_4F_L (REG_SCL_NLM0_BASE + 0x9E) ++#define REG_SCL_NLM0_4F_H (REG_SCL_NLM0_BASE + 0x9F) ++#define REG_SCL_NLM0_50_L (REG_SCL_NLM0_BASE + 0xA0) ++#define REG_SCL_NLM0_50_H (REG_SCL_NLM0_BASE + 0xA1) ++#define REG_SCL_NLM0_51_L (REG_SCL_NLM0_BASE + 0xA2) ++#define REG_SCL_NLM0_51_H (REG_SCL_NLM0_BASE + 0xA3) ++#define REG_SCL_NLM0_52_L (REG_SCL_NLM0_BASE + 0xA4) ++#define REG_SCL_NLM0_52_H (REG_SCL_NLM0_BASE + 0xA5) ++#define REG_SCL_NLM0_53_L (REG_SCL_NLM0_BASE + 0xA6) ++#define REG_SCL_NLM0_53_H (REG_SCL_NLM0_BASE + 0xA7) ++#define REG_SCL_NLM0_54_L (REG_SCL_NLM0_BASE + 0xA8) ++#define REG_SCL_NLM0_54_H (REG_SCL_NLM0_BASE + 0xA9) ++#define REG_SCL_NLM0_55_L (REG_SCL_NLM0_BASE + 0xAA) ++#define REG_SCL_NLM0_55_H (REG_SCL_NLM0_BASE + 0xAB) ++#define REG_SCL_NLM0_56_L (REG_SCL_NLM0_BASE + 0xAC) ++#define REG_SCL_NLM0_56_H (REG_SCL_NLM0_BASE + 0xAD) ++#define REG_SCL_NLM0_57_L (REG_SCL_NLM0_BASE + 0xAE) ++#define REG_SCL_NLM0_57_H (REG_SCL_NLM0_BASE + 0xAF) ++#define REG_SCL_NLM0_58_L (REG_SCL_NLM0_BASE + 0xB0) ++#define REG_SCL_NLM0_58_H (REG_SCL_NLM0_BASE + 0xB1) ++#define REG_SCL_NLM0_59_L (REG_SCL_NLM0_BASE + 0xB2) ++#define REG_SCL_NLM0_59_H (REG_SCL_NLM0_BASE + 0xB3) ++#define REG_SCL_NLM0_5A_L (REG_SCL_NLM0_BASE + 0xB4) ++#define REG_SCL_NLM0_5A_H (REG_SCL_NLM0_BASE + 0xB5) ++#define REG_SCL_NLM0_5B_L (REG_SCL_NLM0_BASE + 0xB6) ++#define REG_SCL_NLM0_5B_H (REG_SCL_NLM0_BASE + 0xB7) ++#define REG_SCL_NLM0_5C_L (REG_SCL_NLM0_BASE + 0xB8) ++#define REG_SCL_NLM0_5C_H (REG_SCL_NLM0_BASE + 0xB9) ++#define REG_SCL_NLM0_5D_L (REG_SCL_NLM0_BASE + 0xBA) ++#define REG_SCL_NLM0_5D_H (REG_SCL_NLM0_BASE + 0xBB) ++#define REG_SCL_NLM0_5E_L (REG_SCL_NLM0_BASE + 0xBC) ++#define REG_SCL_NLM0_5E_H (REG_SCL_NLM0_BASE + 0xBD) ++#define REG_SCL_NLM0_5F_L (REG_SCL_NLM0_BASE + 0xBE) ++#define REG_SCL_NLM0_5F_H (REG_SCL_NLM0_BASE + 0xBF) ++#define REG_SCL_NLM0_60_L (REG_SCL_NLM0_BASE + 0xC0) ++#define REG_SCL_NLM0_60_H (REG_SCL_NLM0_BASE + 0xC1) ++#define REG_SCL_NLM0_61_L (REG_SCL_NLM0_BASE + 0xC2) ++#define REG_SCL_NLM0_61_H (REG_SCL_NLM0_BASE + 0xC3) ++#define REG_SCL_NLM0_62_L (REG_SCL_NLM0_BASE + 0xC4) ++#define REG_SCL_NLM0_62_H (REG_SCL_NLM0_BASE + 0xC5) ++#define REG_SCL_NLM0_63_L (REG_SCL_NLM0_BASE + 0xC6) ++#define REG_SCL_NLM0_63_H (REG_SCL_NLM0_BASE + 0xC7) ++#define REG_SCL_NLM0_64_L (REG_SCL_NLM0_BASE + 0xC8) ++#define REG_SCL_NLM0_64_H (REG_SCL_NLM0_BASE + 0xC9) ++#define REG_SCL_NLM0_65_L (REG_SCL_NLM0_BASE + 0xCA) ++#define REG_SCL_NLM0_65_H (REG_SCL_NLM0_BASE + 0xCB) ++#define REG_SCL_NLM0_66_L (REG_SCL_NLM0_BASE + 0xCC) ++#define REG_SCL_NLM0_66_H (REG_SCL_NLM0_BASE + 0xCD) ++#define REG_SCL_NLM0_67_L (REG_SCL_NLM0_BASE + 0xCE) ++#define REG_SCL_NLM0_67_H (REG_SCL_NLM0_BASE + 0xCF) ++#define REG_SCL_NLM0_68_L (REG_SCL_NLM0_BASE + 0xD0) ++#define REG_SCL_NLM0_68_H (REG_SCL_NLM0_BASE + 0xD1) ++#define REG_SCL_NLM0_69_L (REG_SCL_NLM0_BASE + 0xD2) ++#define REG_SCL_NLM0_69_H (REG_SCL_NLM0_BASE + 0xD3) ++#define REG_SCL_NLM0_6A_L (REG_SCL_NLM0_BASE + 0xD4) ++#define REG_SCL_NLM0_6A_H (REG_SCL_NLM0_BASE + 0xD5) ++#define REG_SCL_NLM0_6B_L (REG_SCL_NLM0_BASE + 0xD6) ++#define REG_SCL_NLM0_6B_H (REG_SCL_NLM0_BASE + 0xD7) ++#define REG_SCL_NLM0_6C_L (REG_SCL_NLM0_BASE + 0xD8) ++#define REG_SCL_NLM0_6C_H (REG_SCL_NLM0_BASE + 0xD9) ++#define REG_SCL_NLM0_6D_L (REG_SCL_NLM0_BASE + 0xDA) ++#define REG_SCL_NLM0_6D_H (REG_SCL_NLM0_BASE + 0xDB) ++#define REG_SCL_NLM0_6E_L (REG_SCL_NLM0_BASE + 0xDC) ++#define REG_SCL_NLM0_6E_H (REG_SCL_NLM0_BASE + 0xDD) ++#define REG_SCL_NLM0_6F_L (REG_SCL_NLM0_BASE + 0xDE) ++#define REG_SCL_NLM0_6F_H (REG_SCL_NLM0_BASE + 0xDF) ++#define REG_SCL_NLM0_70_L (REG_SCL_NLM0_BASE + 0xE0) ++#define REG_SCL_NLM0_70_H (REG_SCL_NLM0_BASE + 0xE1) ++#define REG_SCL_NLM0_71_L (REG_SCL_NLM0_BASE + 0xE2) ++#define REG_SCL_NLM0_71_H (REG_SCL_NLM0_BASE + 0xE3) ++#define REG_SCL_NLM0_72_L (REG_SCL_NLM0_BASE + 0xE4) ++#define REG_SCL_NLM0_72_H (REG_SCL_NLM0_BASE + 0xE5) ++#define REG_SCL_NLM0_73_L (REG_SCL_NLM0_BASE + 0xE6) ++#define REG_SCL_NLM0_73_H (REG_SCL_NLM0_BASE + 0xE7) ++#define REG_SCL_NLM0_74_L (REG_SCL_NLM0_BASE + 0xE8) ++#define REG_SCL_NLM0_74_H (REG_SCL_NLM0_BASE + 0xE9) ++#define REG_SCL_NLM0_75_L (REG_SCL_NLM0_BASE + 0xEA) ++#define REG_SCL_NLM0_75_H (REG_SCL_NLM0_BASE + 0xEB) ++#define REG_SCL_NLM0_76_L (REG_SCL_NLM0_BASE + 0xEC) ++#define REG_SCL_NLM0_76_H (REG_SCL_NLM0_BASE + 0xED) ++#define REG_SCL_NLM0_77_L (REG_SCL_NLM0_BASE + 0xEE) ++#define REG_SCL_NLM0_77_H (REG_SCL_NLM0_BASE + 0xEF) ++#define REG_SCL_NLM0_78_L (REG_SCL_NLM0_BASE + 0xF0) ++#define REG_SCL_NLM0_78_H (REG_SCL_NLM0_BASE + 0xF1) ++#define REG_SCL_NLM0_79_L (REG_SCL_NLM0_BASE + 0xF2) ++#define REG_SCL_NLM0_79_H (REG_SCL_NLM0_BASE + 0xF3) ++#define REG_SCL_NLM0_7A_L (REG_SCL_NLM0_BASE + 0xF4) ++#define REG_SCL_NLM0_7A_H (REG_SCL_NLM0_BASE + 0xF5) ++#define REG_SCL_NLM0_7B_L (REG_SCL_NLM0_BASE + 0xF6) ++#define REG_SCL_NLM0_7B_H (REG_SCL_NLM0_BASE + 0xF7) ++#define REG_SCL_NLM0_7C_L (REG_SCL_NLM0_BASE + 0xF8) ++#define REG_SCL_NLM0_7C_H (REG_SCL_NLM0_BASE + 0xF9) ++#define REG_SCL_NLM0_7D_L (REG_SCL_NLM0_BASE + 0xFA) ++#define REG_SCL_NLM0_7D_H (REG_SCL_NLM0_BASE + 0xFB) ++#define REG_SCL_NLM0_7E_L (REG_SCL_NLM0_BASE + 0xFC) ++#define REG_SCL_NLM0_7E_H (REG_SCL_NLM0_BASE + 0xFD) ++#define REG_SCL_NLM0_7F_L (REG_SCL_NLM0_BASE + 0xFE) ++#define REG_SCL_NLM0_7F_H (REG_SCL_NLM0_BASE + 0xFF) ++ ++#define REG_SCL0_00_L (REG_SCL0_BASE + 0x00) ++#define REG_SCL0_00_H (REG_SCL0_BASE + 0x01) ++#define REG_SCL0_01_L (REG_SCL0_BASE + 0x02) ++#define REG_SCL0_01_H (REG_SCL0_BASE + 0x03) ++#define REG_SCL0_02_L (REG_SCL0_BASE + 0x04) ++#define REG_SCL0_02_H (REG_SCL0_BASE + 0x05) ++#define REG_SCL0_03_L (REG_SCL0_BASE + 0x06) ++#define REG_SCL0_03_H (REG_SCL0_BASE + 0x07) ++#define REG_SCL0_04_L (REG_SCL0_BASE + 0x08) ++#define REG_SCL0_04_H (REG_SCL0_BASE + 0x09) ++#define REG_SCL0_05_L (REG_SCL0_BASE + 0x0A) ++#define REG_SCL0_05_H (REG_SCL0_BASE + 0x0B) ++#define REG_SCL0_06_L (REG_SCL0_BASE + 0x0C) ++#define REG_SCL0_06_H (REG_SCL0_BASE + 0x0D) ++#define REG_SCL0_07_L (REG_SCL0_BASE + 0x0E) ++#define REG_SCL0_07_H (REG_SCL0_BASE + 0x0F) ++#define REG_SCL0_08_L (REG_SCL0_BASE + 0x10) ++#define REG_SCL0_08_H (REG_SCL0_BASE + 0x11) ++#define REG_SCL0_09_L (REG_SCL0_BASE + 0x12) ++#define REG_SCL0_09_H (REG_SCL0_BASE + 0x13) ++#define REG_SCL0_0A_L (REG_SCL0_BASE + 0x14) ++#define REG_SCL0_0A_H (REG_SCL0_BASE + 0x15) ++#define REG_SCL0_0B_L (REG_SCL0_BASE + 0x16) ++#define REG_SCL0_0B_H (REG_SCL0_BASE + 0x17) ++#define REG_SCL0_0C_L (REG_SCL0_BASE + 0x18) ++#define REG_SCL0_0C_H (REG_SCL0_BASE + 0x19) ++#define REG_SCL0_0D_L (REG_SCL0_BASE + 0x1A) ++#define REG_SCL0_0D_H (REG_SCL0_BASE + 0x1B) ++#define REG_SCL0_0E_L (REG_SCL0_BASE + 0x1C) ++#define REG_SCL0_0E_H (REG_SCL0_BASE + 0x1D) ++#define REG_SCL0_0F_L (REG_SCL0_BASE + 0x1E) ++#define REG_SCL0_0F_H (REG_SCL0_BASE + 0x1F) ++#define REG_SCL0_10_L (REG_SCL0_BASE + 0x20) ++#define REG_SCL0_10_H (REG_SCL0_BASE + 0x21) ++#define REG_SCL0_11_L (REG_SCL0_BASE + 0x22) ++#define REG_SCL0_11_H (REG_SCL0_BASE + 0x23) ++#define REG_SCL0_12_L (REG_SCL0_BASE + 0x24) ++#define REG_SCL0_12_H (REG_SCL0_BASE + 0x25) ++#define REG_SCL0_13_L (REG_SCL0_BASE + 0x26) ++#define REG_SCL0_13_H (REG_SCL0_BASE + 0x27) ++#define REG_SCL0_14_L (REG_SCL0_BASE + 0x28) ++#define REG_SCL0_14_H (REG_SCL0_BASE + 0x29) ++#define REG_SCL0_15_L (REG_SCL0_BASE + 0x2A) ++#define REG_SCL0_15_H (REG_SCL0_BASE + 0x2B) ++#define REG_SCL0_16_L (REG_SCL0_BASE + 0x2C) ++#define REG_SCL0_16_H (REG_SCL0_BASE + 0x2D) ++#define REG_SCL0_17_L (REG_SCL0_BASE + 0x2E) ++#define REG_SCL0_17_H (REG_SCL0_BASE + 0x2F) ++#define REG_SCL0_18_L (REG_SCL0_BASE + 0x30) ++#define REG_SCL0_18_H (REG_SCL0_BASE + 0x31) ++#define REG_SCL0_19_L (REG_SCL0_BASE + 0x32) ++#define REG_SCL0_19_H (REG_SCL0_BASE + 0x33) ++#define REG_SCL0_1A_L (REG_SCL0_BASE + 0x34) ++#define REG_SCL0_1A_H (REG_SCL0_BASE + 0x35) ++#define REG_SCL0_1B_L (REG_SCL0_BASE + 0x36) ++#define REG_SCL0_1B_H (REG_SCL0_BASE + 0x37) ++#define REG_SCL0_1C_L (REG_SCL0_BASE + 0x38) ++#define REG_SCL0_1C_H (REG_SCL0_BASE + 0x39) ++#define REG_SCL0_1D_L (REG_SCL0_BASE + 0x3A) ++#define REG_SCL0_1D_H (REG_SCL0_BASE + 0x3B) ++#define REG_SCL0_1E_L (REG_SCL0_BASE + 0x3C) ++#define REG_SCL0_1E_H (REG_SCL0_BASE + 0x3D) ++#define REG_SCL0_1F_L (REG_SCL0_BASE + 0x3E) ++#define REG_SCL0_1F_H (REG_SCL0_BASE + 0x3F) ++#define REG_SCL0_20_L (REG_SCL0_BASE + 0x40) ++#define REG_SCL0_20_H (REG_SCL0_BASE + 0x41) ++#define REG_SCL0_21_L (REG_SCL0_BASE + 0x42) ++#define REG_SCL0_21_H (REG_SCL0_BASE + 0x43) ++#define REG_SCL0_22_L (REG_SCL0_BASE + 0x44) ++#define REG_SCL0_22_H (REG_SCL0_BASE + 0x45) ++#define REG_SCL0_23_L (REG_SCL0_BASE + 0x46) ++#define REG_SCL0_23_H (REG_SCL0_BASE + 0x47) ++#define REG_SCL0_24_L (REG_SCL0_BASE + 0x48) ++#define REG_SCL0_24_H (REG_SCL0_BASE + 0x49) ++#define REG_SCL0_25_L (REG_SCL0_BASE + 0x4A) ++#define REG_SCL0_25_H (REG_SCL0_BASE + 0x4B) ++#define REG_SCL0_26_L (REG_SCL0_BASE + 0x4C) ++#define REG_SCL0_26_H (REG_SCL0_BASE + 0x4D) ++#define REG_SCL0_27_L (REG_SCL0_BASE + 0x4E) ++#define REG_SCL0_27_H (REG_SCL0_BASE + 0x4F) ++#define REG_SCL0_28_L (REG_SCL0_BASE + 0x50) ++#define REG_SCL0_28_H (REG_SCL0_BASE + 0x51) ++#define REG_SCL0_29_L (REG_SCL0_BASE + 0x52) ++#define REG_SCL0_29_H (REG_SCL0_BASE + 0x53) ++#define REG_SCL0_2A_L (REG_SCL0_BASE + 0x54) ++#define REG_SCL0_2A_H (REG_SCL0_BASE + 0x55) ++#define REG_SCL0_2B_L (REG_SCL0_BASE + 0x56) ++#define REG_SCL0_2B_H (REG_SCL0_BASE + 0x57) ++#define REG_SCL0_2C_L (REG_SCL0_BASE + 0x58) ++#define REG_SCL0_2C_H (REG_SCL0_BASE + 0x59) ++#define REG_SCL0_2D_L (REG_SCL0_BASE + 0x5A) ++#define REG_SCL0_2D_H (REG_SCL0_BASE + 0x5B) ++#define REG_SCL0_2E_L (REG_SCL0_BASE + 0x5C) ++#define REG_SCL0_2E_H (REG_SCL0_BASE + 0x5D) ++#define REG_SCL0_2F_L (REG_SCL0_BASE + 0x5E) ++#define REG_SCL0_2F_H (REG_SCL0_BASE + 0x5F) ++#define REG_SCL0_30_L (REG_SCL0_BASE + 0x60) ++#define REG_SCL0_30_H (REG_SCL0_BASE + 0x61) ++#define REG_SCL0_31_L (REG_SCL0_BASE + 0x62) ++#define REG_SCL0_31_H (REG_SCL0_BASE + 0x63) ++#define REG_SCL0_32_L (REG_SCL0_BASE + 0x64) ++#define REG_SCL0_32_H (REG_SCL0_BASE + 0x65) ++#define REG_SCL0_33_L (REG_SCL0_BASE + 0x66) ++#define REG_SCL0_33_H (REG_SCL0_BASE + 0x67) ++#define REG_SCL0_34_L (REG_SCL0_BASE + 0x68) ++#define REG_SCL0_34_H (REG_SCL0_BASE + 0x69) ++#define REG_SCL0_35_L (REG_SCL0_BASE + 0x6A) ++#define REG_SCL0_35_H (REG_SCL0_BASE + 0x6B) ++#define REG_SCL0_36_L (REG_SCL0_BASE + 0x6C) ++#define REG_SCL0_36_H (REG_SCL0_BASE + 0x6D) ++#define REG_SCL0_37_L (REG_SCL0_BASE + 0x6E) ++#define REG_SCL0_37_H (REG_SCL0_BASE + 0x6F) ++#define REG_SCL0_38_L (REG_SCL0_BASE + 0x70) ++#define REG_SCL0_38_H (REG_SCL0_BASE + 0x71) ++#define REG_SCL0_39_L (REG_SCL0_BASE + 0x72) ++#define REG_SCL0_39_H (REG_SCL0_BASE + 0x73) ++#define REG_SCL0_3A_L (REG_SCL0_BASE + 0x74) ++#define REG_SCL0_3A_H (REG_SCL0_BASE + 0x75) ++#define REG_SCL0_3B_L (REG_SCL0_BASE + 0x76) ++#define REG_SCL0_3B_H (REG_SCL0_BASE + 0x77) ++#define REG_SCL0_3C_L (REG_SCL0_BASE + 0x78) ++#define REG_SCL0_3C_H (REG_SCL0_BASE + 0x79) ++#define REG_SCL0_3D_L (REG_SCL0_BASE + 0x7A) ++#define REG_SCL0_3D_H (REG_SCL0_BASE + 0x7B) ++#define REG_SCL0_3E_L (REG_SCL0_BASE + 0x7C) ++#define REG_SCL0_3E_H (REG_SCL0_BASE + 0x7D) ++#define REG_SCL0_3F_L (REG_SCL0_BASE + 0x7E) ++#define REG_SCL0_3F_H (REG_SCL0_BASE + 0x7F) ++#define REG_SCL0_40_L (REG_SCL0_BASE + 0x80) ++#define REG_SCL0_40_H (REG_SCL0_BASE + 0x81) ++#define REG_SCL0_41_L (REG_SCL0_BASE + 0x82) ++#define REG_SCL0_41_H (REG_SCL0_BASE + 0x83) ++#define REG_SCL0_42_L (REG_SCL0_BASE + 0x84) ++#define REG_SCL0_42_H (REG_SCL0_BASE + 0x85) ++#define REG_SCL0_43_L (REG_SCL0_BASE + 0x86) ++#define REG_SCL0_43_H (REG_SCL0_BASE + 0x87) ++#define REG_SCL0_44_L (REG_SCL0_BASE + 0x88) ++#define REG_SCL0_44_H (REG_SCL0_BASE + 0x89) ++#define REG_SCL0_45_L (REG_SCL0_BASE + 0x8A) ++#define REG_SCL0_45_H (REG_SCL0_BASE + 0x8B) ++#define REG_SCL0_46_L (REG_SCL0_BASE + 0x8C) ++#define REG_SCL0_46_H (REG_SCL0_BASE + 0x8D) ++#define REG_SCL0_47_L (REG_SCL0_BASE + 0x8E) ++#define REG_SCL0_47_H (REG_SCL0_BASE + 0x8F) ++#define REG_SCL0_48_L (REG_SCL0_BASE + 0x90) ++#define REG_SCL0_48_H (REG_SCL0_BASE + 0x91) ++#define REG_SCL0_49_L (REG_SCL0_BASE + 0x92) ++#define REG_SCL0_49_H (REG_SCL0_BASE + 0x93) ++#define REG_SCL0_4A_L (REG_SCL0_BASE + 0x94) ++#define REG_SCL0_4A_H (REG_SCL0_BASE + 0x95) ++#define REG_SCL0_4B_L (REG_SCL0_BASE + 0x96) ++#define REG_SCL0_4B_H (REG_SCL0_BASE + 0x97) ++#define REG_SCL0_4C_L (REG_SCL0_BASE + 0x98) ++#define REG_SCL0_4C_H (REG_SCL0_BASE + 0x99) ++#define REG_SCL0_4D_L (REG_SCL0_BASE + 0x9A) ++#define REG_SCL0_4D_H (REG_SCL0_BASE + 0x9B) ++#define REG_SCL0_4E_L (REG_SCL0_BASE + 0x9C) ++#define REG_SCL0_4E_H (REG_SCL0_BASE + 0x9D) ++#define REG_SCL0_4F_L (REG_SCL0_BASE + 0x9E) ++#define REG_SCL0_4F_H (REG_SCL0_BASE + 0x9F) ++#define REG_SCL0_50_L (REG_SCL0_BASE + 0xA0) ++#define REG_SCL0_50_H (REG_SCL0_BASE + 0xA1) ++#define REG_SCL0_51_L (REG_SCL0_BASE + 0xA2) ++#define REG_SCL0_51_H (REG_SCL0_BASE + 0xA3) ++#define REG_SCL0_52_L (REG_SCL0_BASE + 0xA4) ++#define REG_SCL0_52_H (REG_SCL0_BASE + 0xA5) ++#define REG_SCL0_53_L (REG_SCL0_BASE + 0xA6) ++#define REG_SCL0_53_H (REG_SCL0_BASE + 0xA7) ++#define REG_SCL0_54_L (REG_SCL0_BASE + 0xA8) ++#define REG_SCL0_54_H (REG_SCL0_BASE + 0xA9) ++#define REG_SCL0_55_L (REG_SCL0_BASE + 0xAA) ++#define REG_SCL0_55_H (REG_SCL0_BASE + 0xAB) ++#define REG_SCL0_56_L (REG_SCL0_BASE + 0xAC) ++#define REG_SCL0_56_H (REG_SCL0_BASE + 0xAD) ++#define REG_SCL0_57_L (REG_SCL0_BASE + 0xAE) ++#define REG_SCL0_57_H (REG_SCL0_BASE + 0xAF) ++#define REG_SCL0_58_L (REG_SCL0_BASE + 0xB0) ++#define REG_SCL0_58_H (REG_SCL0_BASE + 0xB1) ++#define REG_SCL0_59_L (REG_SCL0_BASE + 0xB2) ++#define REG_SCL0_59_H (REG_SCL0_BASE + 0xB3) ++#define REG_SCL0_5A_L (REG_SCL0_BASE + 0xB4) ++#define REG_SCL0_5A_H (REG_SCL0_BASE + 0xB5) ++#define REG_SCL0_5B_L (REG_SCL0_BASE + 0xB6) ++#define REG_SCL0_5B_H (REG_SCL0_BASE + 0xB7) ++#define REG_SCL0_5C_L (REG_SCL0_BASE + 0xB8) ++#define REG_SCL0_5C_H (REG_SCL0_BASE + 0xB9) ++#define REG_SCL0_5D_L (REG_SCL0_BASE + 0xBA) ++#define REG_SCL0_5D_H (REG_SCL0_BASE + 0xBB) ++#define REG_SCL0_5E_L (REG_SCL0_BASE + 0xBC) ++#define REG_SCL0_5E_H (REG_SCL0_BASE + 0xBD) ++#define REG_SCL0_5F_L (REG_SCL0_BASE + 0xBE) ++#define REG_SCL0_5F_H (REG_SCL0_BASE + 0xBF) ++#define REG_SCL0_60_L (REG_SCL0_BASE + 0xC0) ++#define REG_SCL0_60_H (REG_SCL0_BASE + 0xC1) ++#define REG_SCL0_61_L (REG_SCL0_BASE + 0xC2) ++#define REG_SCL0_61_H (REG_SCL0_BASE + 0xC3) ++#define REG_SCL0_62_L (REG_SCL0_BASE + 0xC4) ++#define REG_SCL0_62_H (REG_SCL0_BASE + 0xC5) ++#define REG_SCL0_63_L (REG_SCL0_BASE + 0xC6) ++#define REG_SCL0_63_H (REG_SCL0_BASE + 0xC7) ++#define REG_SCL0_64_L (REG_SCL0_BASE + 0xC8) ++#define REG_SCL0_64_H (REG_SCL0_BASE + 0xC9) ++#define REG_SCL0_65_L (REG_SCL0_BASE + 0xCA) ++#define REG_SCL0_65_H (REG_SCL0_BASE + 0xCB) ++#define REG_SCL0_66_L (REG_SCL0_BASE + 0xCC) ++#define REG_SCL0_66_H (REG_SCL0_BASE + 0xCD) ++#define REG_SCL0_67_L (REG_SCL0_BASE + 0xCE) ++#define REG_SCL0_67_H (REG_SCL0_BASE + 0xCF) ++#define REG_SCL0_68_L (REG_SCL0_BASE + 0xD0) ++#define REG_SCL0_68_H (REG_SCL0_BASE + 0xD1) ++#define REG_SCL0_69_L (REG_SCL0_BASE + 0xD2) ++#define REG_SCL0_69_H (REG_SCL0_BASE + 0xD3) ++#define REG_SCL0_6A_L (REG_SCL0_BASE + 0xD4) ++#define REG_SCL0_6A_H (REG_SCL0_BASE + 0xD5) ++#define REG_SCL0_6B_L (REG_SCL0_BASE + 0xD6) ++#define REG_SCL0_6B_H (REG_SCL0_BASE + 0xD7) ++#define REG_SCL0_6C_L (REG_SCL0_BASE + 0xD8) ++#define REG_SCL0_6C_H (REG_SCL0_BASE + 0xD9) ++#define REG_SCL0_6D_L (REG_SCL0_BASE + 0xDA) ++#define REG_SCL0_6D_H (REG_SCL0_BASE + 0xDB) ++#define REG_SCL0_6E_L (REG_SCL0_BASE + 0xDC) ++#define REG_SCL0_6E_H (REG_SCL0_BASE + 0xDD) ++#define REG_SCL0_6F_L (REG_SCL0_BASE + 0xDE) ++#define REG_SCL0_6F_H (REG_SCL0_BASE + 0xDF) ++#define REG_SCL0_70_L (REG_SCL0_BASE + 0xE0) ++#define REG_SCL0_70_H (REG_SCL0_BASE + 0xE1) ++#define REG_SCL0_71_L (REG_SCL0_BASE + 0xE2) ++#define REG_SCL0_71_H (REG_SCL0_BASE + 0xE3) ++#define REG_SCL0_72_L (REG_SCL0_BASE + 0xE4) ++#define REG_SCL0_72_H (REG_SCL0_BASE + 0xE5) ++#define REG_SCL0_73_L (REG_SCL0_BASE + 0xE6) ++#define REG_SCL0_73_H (REG_SCL0_BASE + 0xE7) ++#define REG_SCL0_74_L (REG_SCL0_BASE + 0xE8) ++#define REG_SCL0_74_H (REG_SCL0_BASE + 0xE9) ++#define REG_SCL0_75_L (REG_SCL0_BASE + 0xEA) ++#define REG_SCL0_75_H (REG_SCL0_BASE + 0xEB) ++#define REG_SCL0_76_L (REG_SCL0_BASE + 0xEC) ++#define REG_SCL0_76_H (REG_SCL0_BASE + 0xED) ++#define REG_SCL0_77_L (REG_SCL0_BASE + 0xEE) ++#define REG_SCL0_77_H (REG_SCL0_BASE + 0xEF) ++#define REG_SCL0_78_L (REG_SCL0_BASE + 0xF0) ++#define REG_SCL0_78_H (REG_SCL0_BASE + 0xF1) ++#define REG_SCL0_79_L (REG_SCL0_BASE + 0xF2) ++#define REG_SCL0_79_H (REG_SCL0_BASE + 0xF3) ++#define REG_SCL0_7A_L (REG_SCL0_BASE + 0xF4) ++#define REG_SCL0_7A_H (REG_SCL0_BASE + 0xF5) ++#define REG_SCL0_7B_L (REG_SCL0_BASE + 0xF6) ++#define REG_SCL0_7B_H (REG_SCL0_BASE + 0xF7) ++#define REG_SCL0_7C_L (REG_SCL0_BASE + 0xF8) ++#define REG_SCL0_7C_H (REG_SCL0_BASE + 0xF9) ++#define REG_SCL0_7D_L (REG_SCL0_BASE + 0xFA) ++#define REG_SCL0_7D_H (REG_SCL0_BASE + 0xFB) ++#define REG_SCL0_7E_L (REG_SCL0_BASE + 0xFC) ++#define REG_SCL0_7E_H (REG_SCL0_BASE + 0xFD) ++#define REG_SCL0_7F_L (REG_SCL0_BASE + 0xFE) ++#define REG_SCL0_7F_H (REG_SCL0_BASE + 0xFF) ++ ++#define REG_SCL1_00_L (REG_SCL1_BASE + 0x00) ++#define REG_SCL1_00_H (REG_SCL1_BASE + 0x01) ++#define REG_SCL1_01_L (REG_SCL1_BASE + 0x02) ++#define REG_SCL1_01_H (REG_SCL1_BASE + 0x03) ++#define REG_SCL1_02_L (REG_SCL1_BASE + 0x04) ++#define REG_SCL1_02_H (REG_SCL1_BASE + 0x05) ++#define REG_SCL1_03_L (REG_SCL1_BASE + 0x06) ++#define REG_SCL1_03_H (REG_SCL1_BASE + 0x07) ++#define REG_SCL1_04_L (REG_SCL1_BASE + 0x08) ++#define REG_SCL1_04_H (REG_SCL1_BASE + 0x09) ++#define REG_SCL1_05_L (REG_SCL1_BASE + 0x0A) ++#define REG_SCL1_05_H (REG_SCL1_BASE + 0x0B) ++#define REG_SCL1_06_L (REG_SCL1_BASE + 0x0C) ++#define REG_SCL1_06_H (REG_SCL1_BASE + 0x0D) ++#define REG_SCL1_07_L (REG_SCL1_BASE + 0x0E) ++#define REG_SCL1_07_H (REG_SCL1_BASE + 0x0F) ++#define REG_SCL1_08_L (REG_SCL1_BASE + 0x10) ++#define REG_SCL1_08_H (REG_SCL1_BASE + 0x11) ++#define REG_SCL1_09_L (REG_SCL1_BASE + 0x12) ++#define REG_SCL1_09_H (REG_SCL1_BASE + 0x13) ++#define REG_SCL1_0A_L (REG_SCL1_BASE + 0x14) ++#define REG_SCL1_0A_H (REG_SCL1_BASE + 0x15) ++#define REG_SCL1_0B_L (REG_SCL1_BASE + 0x16) ++#define REG_SCL1_0B_H (REG_SCL1_BASE + 0x17) ++#define REG_SCL1_0C_L (REG_SCL1_BASE + 0x18) ++#define REG_SCL1_0C_H (REG_SCL1_BASE + 0x19) ++#define REG_SCL1_0D_L (REG_SCL1_BASE + 0x1A) ++#define REG_SCL1_0D_H (REG_SCL1_BASE + 0x1B) ++#define REG_SCL1_0E_L (REG_SCL1_BASE + 0x1C) ++#define REG_SCL1_0E_H (REG_SCL1_BASE + 0x1D) ++#define REG_SCL1_0F_L (REG_SCL1_BASE + 0x1E) ++#define REG_SCL1_0F_H (REG_SCL1_BASE + 0x1F) ++#define REG_SCL1_10_L (REG_SCL1_BASE + 0x20) ++#define REG_SCL1_10_H (REG_SCL1_BASE + 0x21) ++#define REG_SCL1_11_L (REG_SCL1_BASE + 0x22) ++#define REG_SCL1_11_H (REG_SCL1_BASE + 0x23) ++#define REG_SCL1_12_L (REG_SCL1_BASE + 0x24) ++#define REG_SCL1_12_H (REG_SCL1_BASE + 0x25) ++#define REG_SCL1_13_L (REG_SCL1_BASE + 0x26) ++#define REG_SCL1_13_H (REG_SCL1_BASE + 0x27) ++#define REG_SCL1_14_L (REG_SCL1_BASE + 0x28) ++#define REG_SCL1_14_H (REG_SCL1_BASE + 0x29) ++#define REG_SCL1_15_L (REG_SCL1_BASE + 0x2A) ++#define REG_SCL1_15_H (REG_SCL1_BASE + 0x2B) ++#define REG_SCL1_16_L (REG_SCL1_BASE + 0x2C) ++#define REG_SCL1_16_H (REG_SCL1_BASE + 0x2D) ++#define REG_SCL1_17_L (REG_SCL1_BASE + 0x2E) ++#define REG_SCL1_17_H (REG_SCL1_BASE + 0x2F) ++#define REG_SCL1_18_L (REG_SCL1_BASE + 0x30) ++#define REG_SCL1_18_H (REG_SCL1_BASE + 0x31) ++#define REG_SCL1_19_L (REG_SCL1_BASE + 0x32) ++#define REG_SCL1_19_H (REG_SCL1_BASE + 0x33) ++#define REG_SCL1_1A_L (REG_SCL1_BASE + 0x34) ++#define REG_SCL1_1A_H (REG_SCL1_BASE + 0x35) ++#define REG_SCL1_1B_L (REG_SCL1_BASE + 0x36) ++#define REG_SCL1_1B_H (REG_SCL1_BASE + 0x37) ++#define REG_SCL1_1C_L (REG_SCL1_BASE + 0x38) ++#define REG_SCL1_1C_H (REG_SCL1_BASE + 0x39) ++#define REG_SCL1_1D_L (REG_SCL1_BASE + 0x3A) ++#define REG_SCL1_1D_H (REG_SCL1_BASE + 0x3B) ++#define REG_SCL1_1E_L (REG_SCL1_BASE + 0x3C) ++#define REG_SCL1_1E_H (REG_SCL1_BASE + 0x3D) ++#define REG_SCL1_1F_L (REG_SCL1_BASE + 0x3E) ++#define REG_SCL1_1F_H (REG_SCL1_BASE + 0x3F) ++#define REG_SCL1_20_L (REG_SCL1_BASE + 0x40) ++#define REG_SCL1_20_H (REG_SCL1_BASE + 0x41) ++#define REG_SCL1_21_L (REG_SCL1_BASE + 0x42) ++#define REG_SCL1_21_H (REG_SCL1_BASE + 0x43) ++#define REG_SCL1_22_L (REG_SCL1_BASE + 0x44) ++#define REG_SCL1_22_H (REG_SCL1_BASE + 0x45) ++#define REG_SCL1_23_L (REG_SCL1_BASE + 0x46) ++#define REG_SCL1_23_H (REG_SCL1_BASE + 0x47) ++#define REG_SCL1_24_L (REG_SCL1_BASE + 0x48) ++#define REG_SCL1_24_H (REG_SCL1_BASE + 0x49) ++#define REG_SCL1_25_L (REG_SCL1_BASE + 0x4A) ++#define REG_SCL1_25_H (REG_SCL1_BASE + 0x4B) ++#define REG_SCL1_26_L (REG_SCL1_BASE + 0x4C) ++#define REG_SCL1_26_H (REG_SCL1_BASE + 0x4D) ++#define REG_SCL1_27_L (REG_SCL1_BASE + 0x4E) ++#define REG_SCL1_27_H (REG_SCL1_BASE + 0x4F) ++#define REG_SCL1_28_L (REG_SCL1_BASE + 0x50) ++#define REG_SCL1_28_H (REG_SCL1_BASE + 0x51) ++#define REG_SCL1_29_L (REG_SCL1_BASE + 0x52) ++#define REG_SCL1_29_H (REG_SCL1_BASE + 0x53) ++#define REG_SCL1_2A_L (REG_SCL1_BASE + 0x54) ++#define REG_SCL1_2A_H (REG_SCL1_BASE + 0x55) ++#define REG_SCL1_2B_L (REG_SCL1_BASE + 0x56) ++#define REG_SCL1_2B_H (REG_SCL1_BASE + 0x57) ++#define REG_SCL1_2C_L (REG_SCL1_BASE + 0x58) ++#define REG_SCL1_2C_H (REG_SCL1_BASE + 0x59) ++#define REG_SCL1_2D_L (REG_SCL1_BASE + 0x5A) ++#define REG_SCL1_2D_H (REG_SCL1_BASE + 0x5B) ++#define REG_SCL1_2E_L (REG_SCL1_BASE + 0x5C) ++#define REG_SCL1_2E_H (REG_SCL1_BASE + 0x5D) ++#define REG_SCL1_2F_L (REG_SCL1_BASE + 0x5E) ++#define REG_SCL1_2F_H (REG_SCL1_BASE + 0x5F) ++#define REG_SCL1_30_L (REG_SCL1_BASE + 0x60) ++#define REG_SCL1_30_H (REG_SCL1_BASE + 0x61) ++#define REG_SCL1_31_L (REG_SCL1_BASE + 0x62) ++#define REG_SCL1_31_H (REG_SCL1_BASE + 0x63) ++#define REG_SCL1_32_L (REG_SCL1_BASE + 0x64) ++#define REG_SCL1_32_H (REG_SCL1_BASE + 0x65) ++#define REG_SCL1_33_L (REG_SCL1_BASE + 0x66) ++#define REG_SCL1_33_H (REG_SCL1_BASE + 0x67) ++#define REG_SCL1_34_L (REG_SCL1_BASE + 0x68) ++#define REG_SCL1_34_H (REG_SCL1_BASE + 0x69) ++#define REG_SCL1_35_L (REG_SCL1_BASE + 0x6A) ++#define REG_SCL1_35_H (REG_SCL1_BASE + 0x6B) ++#define REG_SCL1_36_L (REG_SCL1_BASE + 0x6C) ++#define REG_SCL1_36_H (REG_SCL1_BASE + 0x6D) ++#define REG_SCL1_37_L (REG_SCL1_BASE + 0x6E) ++#define REG_SCL1_37_H (REG_SCL1_BASE + 0x6F) ++#define REG_SCL1_38_L (REG_SCL1_BASE + 0x70) ++#define REG_SCL1_38_H (REG_SCL1_BASE + 0x71) ++#define REG_SCL1_39_L (REG_SCL1_BASE + 0x72) ++#define REG_SCL1_39_H (REG_SCL1_BASE + 0x73) ++#define REG_SCL1_3A_L (REG_SCL1_BASE + 0x74) ++#define REG_SCL1_3A_H (REG_SCL1_BASE + 0x75) ++#define REG_SCL1_3B_L (REG_SCL1_BASE + 0x76) ++#define REG_SCL1_3B_H (REG_SCL1_BASE + 0x77) ++#define REG_SCL1_3C_L (REG_SCL1_BASE + 0x78) ++#define REG_SCL1_3C_H (REG_SCL1_BASE + 0x79) ++#define REG_SCL1_3D_L (REG_SCL1_BASE + 0x7A) ++#define REG_SCL1_3D_H (REG_SCL1_BASE + 0x7B) ++#define REG_SCL1_3E_L (REG_SCL1_BASE + 0x7C) ++#define REG_SCL1_3E_H (REG_SCL1_BASE + 0x7D) ++#define REG_SCL1_3F_L (REG_SCL1_BASE + 0x7E) ++#define REG_SCL1_3F_H (REG_SCL1_BASE + 0x7F) ++#define REG_SCL1_40_L (REG_SCL1_BASE + 0x80) ++#define REG_SCL1_40_H (REG_SCL1_BASE + 0x81) ++#define REG_SCL1_41_L (REG_SCL1_BASE + 0x82) ++#define REG_SCL1_41_H (REG_SCL1_BASE + 0x83) ++#define REG_SCL1_42_L (REG_SCL1_BASE + 0x84) ++#define REG_SCL1_42_H (REG_SCL1_BASE + 0x85) ++#define REG_SCL1_43_L (REG_SCL1_BASE + 0x86) ++#define REG_SCL1_43_H (REG_SCL1_BASE + 0x87) ++#define REG_SCL1_44_L (REG_SCL1_BASE + 0x88) ++#define REG_SCL1_44_H (REG_SCL1_BASE + 0x89) ++#define REG_SCL1_45_L (REG_SCL1_BASE + 0x8A) ++#define REG_SCL1_45_H (REG_SCL1_BASE + 0x8B) ++#define REG_SCL1_46_L (REG_SCL1_BASE + 0x8C) ++#define REG_SCL1_46_H (REG_SCL1_BASE + 0x8D) ++#define REG_SCL1_47_L (REG_SCL1_BASE + 0x8E) ++#define REG_SCL1_47_H (REG_SCL1_BASE + 0x8F) ++#define REG_SCL1_48_L (REG_SCL1_BASE + 0x90) ++#define REG_SCL1_48_H (REG_SCL1_BASE + 0x91) ++#define REG_SCL1_49_L (REG_SCL1_BASE + 0x92) ++#define REG_SCL1_49_H (REG_SCL1_BASE + 0x93) ++#define REG_SCL1_4A_L (REG_SCL1_BASE + 0x94) ++#define REG_SCL1_4A_H (REG_SCL1_BASE + 0x95) ++#define REG_SCL1_4B_L (REG_SCL1_BASE + 0x96) ++#define REG_SCL1_4B_H (REG_SCL1_BASE + 0x97) ++#define REG_SCL1_4C_L (REG_SCL1_BASE + 0x98) ++#define REG_SCL1_4C_H (REG_SCL1_BASE + 0x99) ++#define REG_SCL1_4D_L (REG_SCL1_BASE + 0x9A) ++#define REG_SCL1_4D_H (REG_SCL1_BASE + 0x9B) ++#define REG_SCL1_4E_L (REG_SCL1_BASE + 0x9C) ++#define REG_SCL1_4E_H (REG_SCL1_BASE + 0x9D) ++#define REG_SCL1_4F_L (REG_SCL1_BASE + 0x9E) ++#define REG_SCL1_4F_H (REG_SCL1_BASE + 0x9F) ++#define REG_SCL1_50_L (REG_SCL1_BASE + 0xA0) ++#define REG_SCL1_50_H (REG_SCL1_BASE + 0xA1) ++#define REG_SCL1_51_L (REG_SCL1_BASE + 0xA2) ++#define REG_SCL1_51_H (REG_SCL1_BASE + 0xA3) ++#define REG_SCL1_52_L (REG_SCL1_BASE + 0xA4) ++#define REG_SCL1_52_H (REG_SCL1_BASE + 0xA5) ++#define REG_SCL1_53_L (REG_SCL1_BASE + 0xA6) ++#define REG_SCL1_53_H (REG_SCL1_BASE + 0xA7) ++#define REG_SCL1_54_L (REG_SCL1_BASE + 0xA8) ++#define REG_SCL1_54_H (REG_SCL1_BASE + 0xA9) ++#define REG_SCL1_55_L (REG_SCL1_BASE + 0xAA) ++#define REG_SCL1_55_H (REG_SCL1_BASE + 0xAB) ++#define REG_SCL1_56_L (REG_SCL1_BASE + 0xAC) ++#define REG_SCL1_56_H (REG_SCL1_BASE + 0xAD) ++#define REG_SCL1_57_L (REG_SCL1_BASE + 0xAE) ++#define REG_SCL1_57_H (REG_SCL1_BASE + 0xAF) ++#define REG_SCL1_58_L (REG_SCL1_BASE + 0xB0) ++#define REG_SCL1_58_H (REG_SCL1_BASE + 0xB1) ++#define REG_SCL1_59_L (REG_SCL1_BASE + 0xB2) ++#define REG_SCL1_59_H (REG_SCL1_BASE + 0xB3) ++#define REG_SCL1_5A_L (REG_SCL1_BASE + 0xB4) ++#define REG_SCL1_5A_H (REG_SCL1_BASE + 0xB5) ++#define REG_SCL1_5B_L (REG_SCL1_BASE + 0xB6) ++#define REG_SCL1_5B_H (REG_SCL1_BASE + 0xB7) ++#define REG_SCL1_5C_L (REG_SCL1_BASE + 0xB8) ++#define REG_SCL1_5C_H (REG_SCL1_BASE + 0xB9) ++#define REG_SCL1_5D_L (REG_SCL1_BASE + 0xBA) ++#define REG_SCL1_5D_H (REG_SCL1_BASE + 0xBB) ++#define REG_SCL1_5E_L (REG_SCL1_BASE + 0xBC) ++#define REG_SCL1_5E_H (REG_SCL1_BASE + 0xBD) ++#define REG_SCL1_5F_L (REG_SCL1_BASE + 0xBE) ++#define REG_SCL1_5F_H (REG_SCL1_BASE + 0xBF) ++#define REG_SCL1_60_L (REG_SCL1_BASE + 0xC0) ++#define REG_SCL1_60_H (REG_SCL1_BASE + 0xC1) ++#define REG_SCL1_61_L (REG_SCL1_BASE + 0xC2) ++#define REG_SCL1_61_H (REG_SCL1_BASE + 0xC3) ++#define REG_SCL1_62_L (REG_SCL1_BASE + 0xC4) ++#define REG_SCL1_62_H (REG_SCL1_BASE + 0xC5) ++#define REG_SCL1_63_L (REG_SCL1_BASE + 0xC6) ++#define REG_SCL1_63_H (REG_SCL1_BASE + 0xC7) ++#define REG_SCL1_64_L (REG_SCL1_BASE + 0xC8) ++#define REG_SCL1_64_H (REG_SCL1_BASE + 0xC9) ++#define REG_SCL1_65_L (REG_SCL1_BASE + 0xCA) ++#define REG_SCL1_65_H (REG_SCL1_BASE + 0xCB) ++#define REG_SCL1_66_L (REG_SCL1_BASE + 0xCC) ++#define REG_SCL1_66_H (REG_SCL1_BASE + 0xCD) ++#define REG_SCL1_67_L (REG_SCL1_BASE + 0xCE) ++#define REG_SCL1_67_H (REG_SCL1_BASE + 0xCF) ++#define REG_SCL1_68_L (REG_SCL1_BASE + 0xD0) ++#define REG_SCL1_68_H (REG_SCL1_BASE + 0xD1) ++#define REG_SCL1_69_L (REG_SCL1_BASE + 0xD2) ++#define REG_SCL1_69_H (REG_SCL1_BASE + 0xD3) ++#define REG_SCL1_6A_L (REG_SCL1_BASE + 0xD4) ++#define REG_SCL1_6A_H (REG_SCL1_BASE + 0xD5) ++#define REG_SCL1_6B_L (REG_SCL1_BASE + 0xD6) ++#define REG_SCL1_6B_H (REG_SCL1_BASE + 0xD7) ++#define REG_SCL1_6C_L (REG_SCL1_BASE + 0xD8) ++#define REG_SCL1_6C_H (REG_SCL1_BASE + 0xD9) ++#define REG_SCL1_6D_L (REG_SCL1_BASE + 0xDA) ++#define REG_SCL1_6D_H (REG_SCL1_BASE + 0xDB) ++#define REG_SCL1_6E_L (REG_SCL1_BASE + 0xDC) ++#define REG_SCL1_6E_H (REG_SCL1_BASE + 0xDD) ++#define REG_SCL1_6F_L (REG_SCL1_BASE + 0xDE) ++#define REG_SCL1_6F_H (REG_SCL1_BASE + 0xDF) ++#define REG_SCL1_70_L (REG_SCL1_BASE + 0xE0) ++#define REG_SCL1_70_H (REG_SCL1_BASE + 0xE1) ++#define REG_SCL1_71_L (REG_SCL1_BASE + 0xE2) ++#define REG_SCL1_71_H (REG_SCL1_BASE + 0xE3) ++#define REG_SCL1_72_L (REG_SCL1_BASE + 0xE4) ++#define REG_SCL1_72_H (REG_SCL1_BASE + 0xE5) ++#define REG_SCL1_73_L (REG_SCL1_BASE + 0xE6) ++#define REG_SCL1_73_H (REG_SCL1_BASE + 0xE7) ++#define REG_SCL1_74_L (REG_SCL1_BASE + 0xE8) ++#define REG_SCL1_74_H (REG_SCL1_BASE + 0xE9) ++#define REG_SCL1_75_L (REG_SCL1_BASE + 0xEA) ++#define REG_SCL1_75_H (REG_SCL1_BASE + 0xEB) ++#define REG_SCL1_76_L (REG_SCL1_BASE + 0xEC) ++#define REG_SCL1_76_H (REG_SCL1_BASE + 0xED) ++#define REG_SCL1_77_L (REG_SCL1_BASE + 0xEE) ++#define REG_SCL1_77_H (REG_SCL1_BASE + 0xEF) ++#define REG_SCL1_78_L (REG_SCL1_BASE + 0xF0) ++#define REG_SCL1_78_H (REG_SCL1_BASE + 0xF1) ++#define REG_SCL1_79_L (REG_SCL1_BASE + 0xF2) ++#define REG_SCL1_79_H (REG_SCL1_BASE + 0xF3) ++#define REG_SCL1_7A_L (REG_SCL1_BASE + 0xF4) ++#define REG_SCL1_7A_H (REG_SCL1_BASE + 0xF5) ++#define REG_SCL1_7B_L (REG_SCL1_BASE + 0xF6) ++#define REG_SCL1_7B_H (REG_SCL1_BASE + 0xF7) ++#define REG_SCL1_7C_L (REG_SCL1_BASE + 0xF8) ++#define REG_SCL1_7C_H (REG_SCL1_BASE + 0xF9) ++#define REG_SCL1_7D_L (REG_SCL1_BASE + 0xFA) ++#define REG_SCL1_7D_H (REG_SCL1_BASE + 0xFB) ++#define REG_SCL1_7E_L (REG_SCL1_BASE + 0xFC) ++#define REG_SCL1_7E_H (REG_SCL1_BASE + 0xFD) ++#define REG_SCL1_7F_L (REG_SCL1_BASE + 0xFE) ++#define REG_SCL1_7F_H (REG_SCL1_BASE + 0xFF) ++ ++#define REG_SCL2_00_L (REG_SCL2_BASE + 0x00) ++#define REG_SCL2_00_H (REG_SCL2_BASE + 0x01) ++#define REG_SCL2_01_L (REG_SCL2_BASE + 0x02) ++#define REG_SCL2_01_H (REG_SCL2_BASE + 0x03) ++#define REG_SCL2_02_L (REG_SCL2_BASE + 0x04) ++#define REG_SCL2_02_H (REG_SCL2_BASE + 0x05) ++#define REG_SCL2_03_L (REG_SCL2_BASE + 0x06) ++#define REG_SCL2_03_H (REG_SCL2_BASE + 0x07) ++#define REG_SCL2_04_L (REG_SCL2_BASE + 0x08) ++#define REG_SCL2_04_H (REG_SCL2_BASE + 0x09) ++#define REG_SCL2_05_L (REG_SCL2_BASE + 0x0A) ++#define REG_SCL2_05_H (REG_SCL2_BASE + 0x0B) ++#define REG_SCL2_06_L (REG_SCL2_BASE + 0x0C) ++#define REG_SCL2_06_H (REG_SCL2_BASE + 0x0D) ++#define REG_SCL2_07_L (REG_SCL2_BASE + 0x0E) ++#define REG_SCL2_07_H (REG_SCL2_BASE + 0x0F) ++#define REG_SCL2_08_L (REG_SCL2_BASE + 0x10) ++#define REG_SCL2_08_H (REG_SCL2_BASE + 0x11) ++#define REG_SCL2_09_L (REG_SCL2_BASE + 0x12) ++#define REG_SCL2_09_H (REG_SCL2_BASE + 0x13) ++#define REG_SCL2_0A_L (REG_SCL2_BASE + 0x14) ++#define REG_SCL2_0A_H (REG_SCL2_BASE + 0x15) ++#define REG_SCL2_0B_L (REG_SCL2_BASE + 0x16) ++#define REG_SCL2_0B_H (REG_SCL2_BASE + 0x17) ++#define REG_SCL2_0C_L (REG_SCL2_BASE + 0x18) ++#define REG_SCL2_0C_H (REG_SCL2_BASE + 0x19) ++#define REG_SCL2_0D_L (REG_SCL2_BASE + 0x1A) ++#define REG_SCL2_0D_H (REG_SCL2_BASE + 0x1B) ++#define REG_SCL2_0E_L (REG_SCL2_BASE + 0x1C) ++#define REG_SCL2_0E_H (REG_SCL2_BASE + 0x1D) ++#define REG_SCL2_0F_L (REG_SCL2_BASE + 0x1E) ++#define REG_SCL2_0F_H (REG_SCL2_BASE + 0x1F) ++#define REG_SCL2_10_L (REG_SCL2_BASE + 0x20) ++#define REG_SCL2_10_H (REG_SCL2_BASE + 0x21) ++#define REG_SCL2_11_L (REG_SCL2_BASE + 0x22) ++#define REG_SCL2_11_H (REG_SCL2_BASE + 0x23) ++#define REG_SCL2_12_L (REG_SCL2_BASE + 0x24) ++#define REG_SCL2_12_H (REG_SCL2_BASE + 0x25) ++#define REG_SCL2_13_L (REG_SCL2_BASE + 0x26) ++#define REG_SCL2_13_H (REG_SCL2_BASE + 0x27) ++#define REG_SCL2_14_L (REG_SCL2_BASE + 0x28) ++#define REG_SCL2_14_H (REG_SCL2_BASE + 0x29) ++#define REG_SCL2_15_L (REG_SCL2_BASE + 0x2A) ++#define REG_SCL2_15_H (REG_SCL2_BASE + 0x2B) ++#define REG_SCL2_16_L (REG_SCL2_BASE + 0x2C) ++#define REG_SCL2_16_H (REG_SCL2_BASE + 0x2D) ++#define REG_SCL2_17_L (REG_SCL2_BASE + 0x2E) ++#define REG_SCL2_17_H (REG_SCL2_BASE + 0x2F) ++#define REG_SCL2_18_L (REG_SCL2_BASE + 0x30) ++#define REG_SCL2_18_H (REG_SCL2_BASE + 0x31) ++#define REG_SCL2_19_L (REG_SCL2_BASE + 0x32) ++#define REG_SCL2_19_H (REG_SCL2_BASE + 0x33) ++#define REG_SCL2_1A_L (REG_SCL2_BASE + 0x34) ++#define REG_SCL2_1A_H (REG_SCL2_BASE + 0x35) ++#define REG_SCL2_1B_L (REG_SCL2_BASE + 0x36) ++#define REG_SCL2_1B_H (REG_SCL2_BASE + 0x37) ++#define REG_SCL2_1C_L (REG_SCL2_BASE + 0x38) ++#define REG_SCL2_1C_H (REG_SCL2_BASE + 0x39) ++#define REG_SCL2_1D_L (REG_SCL2_BASE + 0x3A) ++#define REG_SCL2_1D_H (REG_SCL2_BASE + 0x3B) ++#define REG_SCL2_1E_L (REG_SCL2_BASE + 0x3C) ++#define REG_SCL2_1E_H (REG_SCL2_BASE + 0x3D) ++#define REG_SCL2_1F_L (REG_SCL2_BASE + 0x3E) ++#define REG_SCL2_1F_H (REG_SCL2_BASE + 0x3F) ++#define REG_SCL2_20_L (REG_SCL2_BASE + 0x40) ++#define REG_SCL2_20_H (REG_SCL2_BASE + 0x41) ++#define REG_SCL2_21_L (REG_SCL2_BASE + 0x42) ++#define REG_SCL2_21_H (REG_SCL2_BASE + 0x43) ++#define REG_SCL2_22_L (REG_SCL2_BASE + 0x44) ++#define REG_SCL2_22_H (REG_SCL2_BASE + 0x45) ++#define REG_SCL2_23_L (REG_SCL2_BASE + 0x46) ++#define REG_SCL2_23_H (REG_SCL2_BASE + 0x47) ++#define REG_SCL2_24_L (REG_SCL2_BASE + 0x48) ++#define REG_SCL2_24_H (REG_SCL2_BASE + 0x49) ++#define REG_SCL2_25_L (REG_SCL2_BASE + 0x4A) ++#define REG_SCL2_25_H (REG_SCL2_BASE + 0x4B) ++#define REG_SCL2_26_L (REG_SCL2_BASE + 0x4C) ++#define REG_SCL2_26_H (REG_SCL2_BASE + 0x4D) ++#define REG_SCL2_27_L (REG_SCL2_BASE + 0x4E) ++#define REG_SCL2_27_H (REG_SCL2_BASE + 0x4F) ++#define REG_SCL2_28_L (REG_SCL2_BASE + 0x50) ++#define REG_SCL2_28_H (REG_SCL2_BASE + 0x51) ++#define REG_SCL2_29_L (REG_SCL2_BASE + 0x52) ++#define REG_SCL2_29_H (REG_SCL2_BASE + 0x53) ++#define REG_SCL2_2A_L (REG_SCL2_BASE + 0x54) ++#define REG_SCL2_2A_H (REG_SCL2_BASE + 0x55) ++#define REG_SCL2_2B_L (REG_SCL2_BASE + 0x56) ++#define REG_SCL2_2B_H (REG_SCL2_BASE + 0x57) ++#define REG_SCL2_2C_L (REG_SCL2_BASE + 0x58) ++#define REG_SCL2_2C_H (REG_SCL2_BASE + 0x59) ++#define REG_SCL2_2D_L (REG_SCL2_BASE + 0x5A) ++#define REG_SCL2_2D_H (REG_SCL2_BASE + 0x5B) ++#define REG_SCL2_2E_L (REG_SCL2_BASE + 0x5C) ++#define REG_SCL2_2E_H (REG_SCL2_BASE + 0x5D) ++#define REG_SCL2_2F_L (REG_SCL2_BASE + 0x5E) ++#define REG_SCL2_2F_H (REG_SCL2_BASE + 0x5F) ++#define REG_SCL2_30_L (REG_SCL2_BASE + 0x60) ++#define REG_SCL2_30_H (REG_SCL2_BASE + 0x61) ++#define REG_SCL2_31_L (REG_SCL2_BASE + 0x62) ++#define REG_SCL2_31_H (REG_SCL2_BASE + 0x63) ++#define REG_SCL2_32_L (REG_SCL2_BASE + 0x64) ++#define REG_SCL2_32_H (REG_SCL2_BASE + 0x65) ++#define REG_SCL2_33_L (REG_SCL2_BASE + 0x66) ++#define REG_SCL2_33_H (REG_SCL2_BASE + 0x67) ++#define REG_SCL2_34_L (REG_SCL2_BASE + 0x68) ++#define REG_SCL2_34_H (REG_SCL2_BASE + 0x69) ++#define REG_SCL2_35_L (REG_SCL2_BASE + 0x6A) ++#define REG_SCL2_35_H (REG_SCL2_BASE + 0x6B) ++#define REG_SCL2_36_L (REG_SCL2_BASE + 0x6C) ++#define REG_SCL2_36_H (REG_SCL2_BASE + 0x6D) ++#define REG_SCL2_37_L (REG_SCL2_BASE + 0x6E) ++#define REG_SCL2_37_H (REG_SCL2_BASE + 0x6F) ++#define REG_SCL2_38_L (REG_SCL2_BASE + 0x70) ++#define REG_SCL2_38_H (REG_SCL2_BASE + 0x71) ++#define REG_SCL2_39_L (REG_SCL2_BASE + 0x72) ++#define REG_SCL2_39_H (REG_SCL2_BASE + 0x73) ++#define REG_SCL2_3A_L (REG_SCL2_BASE + 0x74) ++#define REG_SCL2_3A_H (REG_SCL2_BASE + 0x75) ++#define REG_SCL2_3B_L (REG_SCL2_BASE + 0x76) ++#define REG_SCL2_3B_H (REG_SCL2_BASE + 0x77) ++#define REG_SCL2_3C_L (REG_SCL2_BASE + 0x78) ++#define REG_SCL2_3C_H (REG_SCL2_BASE + 0x79) ++#define REG_SCL2_3D_L (REG_SCL2_BASE + 0x7A) ++#define REG_SCL2_3D_H (REG_SCL2_BASE + 0x7B) ++#define REG_SCL2_3E_L (REG_SCL2_BASE + 0x7C) ++#define REG_SCL2_3E_H (REG_SCL2_BASE + 0x7D) ++#define REG_SCL2_3F_L (REG_SCL2_BASE + 0x7E) ++#define REG_SCL2_3F_H (REG_SCL2_BASE + 0x7F) ++#define REG_SCL2_40_L (REG_SCL2_BASE + 0x80) ++#define REG_SCL2_40_H (REG_SCL2_BASE + 0x81) ++#define REG_SCL2_41_L (REG_SCL2_BASE + 0x82) ++#define REG_SCL2_41_H (REG_SCL2_BASE + 0x83) ++#define REG_SCL2_42_L (REG_SCL2_BASE + 0x84) ++#define REG_SCL2_42_H (REG_SCL2_BASE + 0x85) ++#define REG_SCL2_43_L (REG_SCL2_BASE + 0x86) ++#define REG_SCL2_43_H (REG_SCL2_BASE + 0x87) ++#define REG_SCL2_44_L (REG_SCL2_BASE + 0x88) ++#define REG_SCL2_44_H (REG_SCL2_BASE + 0x89) ++#define REG_SCL2_45_L (REG_SCL2_BASE + 0x8A) ++#define REG_SCL2_45_H (REG_SCL2_BASE + 0x8B) ++#define REG_SCL2_46_L (REG_SCL2_BASE + 0x8C) ++#define REG_SCL2_46_H (REG_SCL2_BASE + 0x8D) ++#define REG_SCL2_47_L (REG_SCL2_BASE + 0x8E) ++#define REG_SCL2_47_H (REG_SCL2_BASE + 0x8F) ++#define REG_SCL2_48_L (REG_SCL2_BASE + 0x90) ++#define REG_SCL2_48_H (REG_SCL2_BASE + 0x91) ++#define REG_SCL2_49_L (REG_SCL2_BASE + 0x92) ++#define REG_SCL2_49_H (REG_SCL2_BASE + 0x93) ++#define REG_SCL2_4A_L (REG_SCL2_BASE + 0x94) ++#define REG_SCL2_4A_H (REG_SCL2_BASE + 0x95) ++#define REG_SCL2_4B_L (REG_SCL2_BASE + 0x96) ++#define REG_SCL2_4B_H (REG_SCL2_BASE + 0x97) ++#define REG_SCL2_4C_L (REG_SCL2_BASE + 0x98) ++#define REG_SCL2_4C_H (REG_SCL2_BASE + 0x99) ++#define REG_SCL2_4D_L (REG_SCL2_BASE + 0x9A) ++#define REG_SCL2_4D_H (REG_SCL2_BASE + 0x9B) ++#define REG_SCL2_4E_L (REG_SCL2_BASE + 0x9C) ++#define REG_SCL2_4E_H (REG_SCL2_BASE + 0x9D) ++#define REG_SCL2_4F_L (REG_SCL2_BASE + 0x9E) ++#define REG_SCL2_4F_H (REG_SCL2_BASE + 0x9F) ++#define REG_SCL2_50_L (REG_SCL2_BASE + 0xA0) ++#define REG_SCL2_50_H (REG_SCL2_BASE + 0xA1) ++#define REG_SCL2_51_L (REG_SCL2_BASE + 0xA2) ++#define REG_SCL2_51_H (REG_SCL2_BASE + 0xA3) ++#define REG_SCL2_52_L (REG_SCL2_BASE + 0xA4) ++#define REG_SCL2_52_H (REG_SCL2_BASE + 0xA5) ++#define REG_SCL2_53_L (REG_SCL2_BASE + 0xA6) ++#define REG_SCL2_53_H (REG_SCL2_BASE + 0xA7) ++#define REG_SCL2_54_L (REG_SCL2_BASE + 0xA8) ++#define REG_SCL2_54_H (REG_SCL2_BASE + 0xA9) ++#define REG_SCL2_55_L (REG_SCL2_BASE + 0xAA) ++#define REG_SCL2_55_H (REG_SCL2_BASE + 0xAB) ++#define REG_SCL2_56_L (REG_SCL2_BASE + 0xAC) ++#define REG_SCL2_56_H (REG_SCL2_BASE + 0xAD) ++#define REG_SCL2_57_L (REG_SCL2_BASE + 0xAE) ++#define REG_SCL2_57_H (REG_SCL2_BASE + 0xAF) ++#define REG_SCL2_58_L (REG_SCL2_BASE + 0xB0) ++#define REG_SCL2_58_H (REG_SCL2_BASE + 0xB1) ++#define REG_SCL2_59_L (REG_SCL2_BASE + 0xB2) ++#define REG_SCL2_59_H (REG_SCL2_BASE + 0xB3) ++#define REG_SCL2_5A_L (REG_SCL2_BASE + 0xB4) ++#define REG_SCL2_5A_H (REG_SCL2_BASE + 0xB5) ++#define REG_SCL2_5B_L (REG_SCL2_BASE + 0xB6) ++#define REG_SCL2_5B_H (REG_SCL2_BASE + 0xB7) ++#define REG_SCL2_5C_L (REG_SCL2_BASE + 0xB8) ++#define REG_SCL2_5C_H (REG_SCL2_BASE + 0xB9) ++#define REG_SCL2_5D_L (REG_SCL2_BASE + 0xBA) ++#define REG_SCL2_5D_H (REG_SCL2_BASE + 0xBB) ++#define REG_SCL2_5E_L (REG_SCL2_BASE + 0xBC) ++#define REG_SCL2_5E_H (REG_SCL2_BASE + 0xBD) ++#define REG_SCL2_5F_L (REG_SCL2_BASE + 0xBE) ++#define REG_SCL2_5F_H (REG_SCL2_BASE + 0xBF) ++#define REG_SCL2_60_L (REG_SCL2_BASE + 0xC0) ++#define REG_SCL2_60_H (REG_SCL2_BASE + 0xC1) ++#define REG_SCL2_61_L (REG_SCL2_BASE + 0xC2) ++#define REG_SCL2_61_H (REG_SCL2_BASE + 0xC3) ++#define REG_SCL2_62_L (REG_SCL2_BASE + 0xC4) ++#define REG_SCL2_62_H (REG_SCL2_BASE + 0xC5) ++#define REG_SCL2_63_L (REG_SCL2_BASE + 0xC6) ++#define REG_SCL2_63_H (REG_SCL2_BASE + 0xC7) ++#define REG_SCL2_64_L (REG_SCL2_BASE + 0xC8) ++#define REG_SCL2_64_H (REG_SCL2_BASE + 0xC9) ++#define REG_SCL2_65_L (REG_SCL2_BASE + 0xCA) ++#define REG_SCL2_65_H (REG_SCL2_BASE + 0xCB) ++#define REG_SCL2_66_L (REG_SCL2_BASE + 0xCC) ++#define REG_SCL2_66_H (REG_SCL2_BASE + 0xCD) ++#define REG_SCL2_67_L (REG_SCL2_BASE + 0xCE) ++#define REG_SCL2_67_H (REG_SCL2_BASE + 0xCF) ++#define REG_SCL2_68_L (REG_SCL2_BASE + 0xD0) ++#define REG_SCL2_68_H (REG_SCL2_BASE + 0xD1) ++#define REG_SCL2_69_L (REG_SCL2_BASE + 0xD2) ++#define REG_SCL2_69_H (REG_SCL2_BASE + 0xD3) ++#define REG_SCL2_6A_L (REG_SCL2_BASE + 0xD4) ++#define REG_SCL2_6A_H (REG_SCL2_BASE + 0xD5) ++#define REG_SCL2_6B_L (REG_SCL2_BASE + 0xD6) ++#define REG_SCL2_6B_H (REG_SCL2_BASE + 0xD7) ++#define REG_SCL2_6C_L (REG_SCL2_BASE + 0xD8) ++#define REG_SCL2_6C_H (REG_SCL2_BASE + 0xD9) ++#define REG_SCL2_6D_L (REG_SCL2_BASE + 0xDA) ++#define REG_SCL2_6D_H (REG_SCL2_BASE + 0xDB) ++#define REG_SCL2_6E_L (REG_SCL2_BASE + 0xDC) ++#define REG_SCL2_6E_H (REG_SCL2_BASE + 0xDD) ++#define REG_SCL2_6F_L (REG_SCL2_BASE + 0xDE) ++#define REG_SCL2_6F_H (REG_SCL2_BASE + 0xDF) ++#define REG_SCL2_70_L (REG_SCL2_BASE + 0xE0) ++#define REG_SCL2_70_H (REG_SCL2_BASE + 0xE1) ++#define REG_SCL2_71_L (REG_SCL2_BASE + 0xE2) ++#define REG_SCL2_71_H (REG_SCL2_BASE + 0xE3) ++#define REG_SCL2_72_L (REG_SCL2_BASE + 0xE4) ++#define REG_SCL2_72_H (REG_SCL2_BASE + 0xE5) ++#define REG_SCL2_73_L (REG_SCL2_BASE + 0xE6) ++#define REG_SCL2_73_H (REG_SCL2_BASE + 0xE7) ++#define REG_SCL2_74_L (REG_SCL2_BASE + 0xE8) ++#define REG_SCL2_74_H (REG_SCL2_BASE + 0xE9) ++#define REG_SCL2_75_L (REG_SCL2_BASE + 0xEA) ++#define REG_SCL2_75_H (REG_SCL2_BASE + 0xEB) ++#define REG_SCL2_76_L (REG_SCL2_BASE + 0xEC) ++#define REG_SCL2_76_H (REG_SCL2_BASE + 0xED) ++#define REG_SCL2_77_L (REG_SCL2_BASE + 0xEE) ++#define REG_SCL2_77_H (REG_SCL2_BASE + 0xEF) ++#define REG_SCL2_78_L (REG_SCL2_BASE + 0xF0) ++#define REG_SCL2_78_H (REG_SCL2_BASE + 0xF1) ++#define REG_SCL2_79_L (REG_SCL2_BASE + 0xF2) ++#define REG_SCL2_79_H (REG_SCL2_BASE + 0xF3) ++#define REG_SCL2_7A_L (REG_SCL2_BASE + 0xF4) ++#define REG_SCL2_7A_H (REG_SCL2_BASE + 0xF5) ++#define REG_SCL2_7B_L (REG_SCL2_BASE + 0xF6) ++#define REG_SCL2_7B_H (REG_SCL2_BASE + 0xF7) ++#define REG_SCL2_7C_L (REG_SCL2_BASE + 0xF8) ++#define REG_SCL2_7C_H (REG_SCL2_BASE + 0xF9) ++#define REG_SCL2_7D_L (REG_SCL2_BASE + 0xFA) ++#define REG_SCL2_7D_H (REG_SCL2_BASE + 0xFB) ++#define REG_SCL2_7E_L (REG_SCL2_BASE + 0xFC) ++#define REG_SCL2_7E_H (REG_SCL2_BASE + 0xFD) ++#define REG_SCL2_7F_L (REG_SCL2_BASE + 0xFE) ++#define REG_SCL2_7F_H (REG_SCL2_BASE + 0xFF) ++ ++#define REG_SCL3_00_L (REG_SCL3_BASE + 0x00) ++#define REG_SCL3_00_H (REG_SCL3_BASE + 0x01) ++#define REG_SCL3_01_L (REG_SCL3_BASE + 0x02) ++#define REG_SCL3_01_H (REG_SCL3_BASE + 0x03) ++#define REG_SCL3_02_L (REG_SCL3_BASE + 0x04) ++#define REG_SCL3_02_H (REG_SCL3_BASE + 0x05) ++#define REG_SCL3_03_L (REG_SCL3_BASE + 0x06) ++#define REG_SCL3_03_H (REG_SCL3_BASE + 0x07) ++#define REG_SCL3_04_L (REG_SCL3_BASE + 0x08) ++#define REG_SCL3_04_H (REG_SCL3_BASE + 0x09) ++#define REG_SCL3_05_L (REG_SCL3_BASE + 0x0A) ++#define REG_SCL3_05_H (REG_SCL3_BASE + 0x0B) ++#define REG_SCL3_06_L (REG_SCL3_BASE + 0x0C) ++#define REG_SCL3_06_H (REG_SCL3_BASE + 0x0D) ++#define REG_SCL3_07_L (REG_SCL3_BASE + 0x0E) ++#define REG_SCL3_07_H (REG_SCL3_BASE + 0x0F) ++#define REG_SCL3_08_L (REG_SCL3_BASE + 0x10) ++#define REG_SCL3_08_H (REG_SCL3_BASE + 0x11) ++#define REG_SCL3_09_L (REG_SCL3_BASE + 0x12) ++#define REG_SCL3_09_H (REG_SCL3_BASE + 0x13) ++#define REG_SCL3_0A_L (REG_SCL3_BASE + 0x14) ++#define REG_SCL3_0A_H (REG_SCL3_BASE + 0x15) ++#define REG_SCL3_0B_L (REG_SCL3_BASE + 0x16) ++#define REG_SCL3_0B_H (REG_SCL3_BASE + 0x17) ++#define REG_SCL3_0C_L (REG_SCL3_BASE + 0x18) ++#define REG_SCL3_0C_H (REG_SCL3_BASE + 0x19) ++#define REG_SCL3_0D_L (REG_SCL3_BASE + 0x1A) ++#define REG_SCL3_0D_H (REG_SCL3_BASE + 0x1B) ++#define REG_SCL3_0E_L (REG_SCL3_BASE + 0x1C) ++#define REG_SCL3_0E_H (REG_SCL3_BASE + 0x1D) ++#define REG_SCL3_0F_L (REG_SCL3_BASE + 0x1E) ++#define REG_SCL3_0F_H (REG_SCL3_BASE + 0x1F) ++#define REG_SCL3_10_L (REG_SCL3_BASE + 0x20) ++#define REG_SCL3_10_H (REG_SCL3_BASE + 0x21) ++#define REG_SCL3_11_L (REG_SCL3_BASE + 0x22) ++#define REG_SCL3_11_H (REG_SCL3_BASE + 0x23) ++#define REG_SCL3_12_L (REG_SCL3_BASE + 0x24) ++#define REG_SCL3_12_H (REG_SCL3_BASE + 0x25) ++#define REG_SCL3_13_L (REG_SCL3_BASE + 0x26) ++#define REG_SCL3_13_H (REG_SCL3_BASE + 0x27) ++#define REG_SCL3_14_L (REG_SCL3_BASE + 0x28) ++#define REG_SCL3_14_H (REG_SCL3_BASE + 0x29) ++#define REG_SCL3_15_L (REG_SCL3_BASE + 0x2A) ++#define REG_SCL3_15_H (REG_SCL3_BASE + 0x2B) ++#define REG_SCL3_16_L (REG_SCL3_BASE + 0x2C) ++#define REG_SCL3_16_H (REG_SCL3_BASE + 0x2D) ++#define REG_SCL3_17_L (REG_SCL3_BASE + 0x2E) ++#define REG_SCL3_17_H (REG_SCL3_BASE + 0x2F) ++#define REG_SCL3_18_L (REG_SCL3_BASE + 0x30) ++#define REG_SCL3_18_H (REG_SCL3_BASE + 0x31) ++#define REG_SCL3_19_L (REG_SCL3_BASE + 0x32) ++#define REG_SCL3_19_H (REG_SCL3_BASE + 0x33) ++#define REG_SCL3_1A_L (REG_SCL3_BASE + 0x34) ++#define REG_SCL3_1A_H (REG_SCL3_BASE + 0x35) ++#define REG_SCL3_1B_L (REG_SCL3_BASE + 0x36) ++#define REG_SCL3_1B_H (REG_SCL3_BASE + 0x37) ++#define REG_SCL3_1C_L (REG_SCL3_BASE + 0x38) ++#define REG_SCL3_1C_H (REG_SCL3_BASE + 0x39) ++#define REG_SCL3_1D_L (REG_SCL3_BASE + 0x3A) ++#define REG_SCL3_1D_H (REG_SCL3_BASE + 0x3B) ++#define REG_SCL3_1E_L (REG_SCL3_BASE + 0x3C) ++#define REG_SCL3_1E_H (REG_SCL3_BASE + 0x3D) ++#define REG_SCL3_1F_L (REG_SCL3_BASE + 0x3E) ++#define REG_SCL3_1F_H (REG_SCL3_BASE + 0x3F) ++#define REG_SCL3_20_L (REG_SCL3_BASE + 0x40) ++#define REG_SCL3_20_H (REG_SCL3_BASE + 0x41) ++#define REG_SCL3_21_L (REG_SCL3_BASE + 0x42) ++#define REG_SCL3_21_H (REG_SCL3_BASE + 0x43) ++#define REG_SCL3_22_L (REG_SCL3_BASE + 0x44) ++#define REG_SCL3_22_H (REG_SCL3_BASE + 0x45) ++#define REG_SCL3_23_L (REG_SCL3_BASE + 0x46) ++#define REG_SCL3_23_H (REG_SCL3_BASE + 0x47) ++#define REG_SCL3_24_L (REG_SCL3_BASE + 0x48) ++#define REG_SCL3_24_H (REG_SCL3_BASE + 0x49) ++#define REG_SCL3_25_L (REG_SCL3_BASE + 0x4A) ++#define REG_SCL3_25_H (REG_SCL3_BASE + 0x4B) ++#define REG_SCL3_26_L (REG_SCL3_BASE + 0x4C) ++#define REG_SCL3_26_H (REG_SCL3_BASE + 0x4D) ++#define REG_SCL3_27_L (REG_SCL3_BASE + 0x4E) ++#define REG_SCL3_27_H (REG_SCL3_BASE + 0x4F) ++#define REG_SCL3_28_L (REG_SCL3_BASE + 0x50) ++#define REG_SCL3_28_H (REG_SCL3_BASE + 0x51) ++#define REG_SCL3_29_L (REG_SCL3_BASE + 0x52) ++#define REG_SCL3_29_H (REG_SCL3_BASE + 0x53) ++#define REG_SCL3_2A_L (REG_SCL3_BASE + 0x54) ++#define REG_SCL3_2A_H (REG_SCL3_BASE + 0x55) ++#define REG_SCL3_2B_L (REG_SCL3_BASE + 0x56) ++#define REG_SCL3_2B_H (REG_SCL3_BASE + 0x57) ++#define REG_SCL3_2C_L (REG_SCL3_BASE + 0x58) ++#define REG_SCL3_2C_H (REG_SCL3_BASE + 0x59) ++#define REG_SCL3_2D_L (REG_SCL3_BASE + 0x5A) ++#define REG_SCL3_2D_H (REG_SCL3_BASE + 0x5B) ++#define REG_SCL3_2E_L (REG_SCL3_BASE + 0x5C) ++#define REG_SCL3_2E_H (REG_SCL3_BASE + 0x5D) ++#define REG_SCL3_2F_L (REG_SCL3_BASE + 0x5E) ++#define REG_SCL3_2F_H (REG_SCL3_BASE + 0x5F) ++#define REG_SCL3_30_L (REG_SCL3_BASE + 0x60) ++#define REG_SCL3_30_H (REG_SCL3_BASE + 0x61) ++#define REG_SCL3_31_L (REG_SCL3_BASE + 0x62) ++#define REG_SCL3_31_H (REG_SCL3_BASE + 0x63) ++#define REG_SCL3_32_L (REG_SCL3_BASE + 0x64) ++#define REG_SCL3_32_H (REG_SCL3_BASE + 0x65) ++#define REG_SCL3_33_L (REG_SCL3_BASE + 0x66) ++#define REG_SCL3_33_H (REG_SCL3_BASE + 0x67) ++#define REG_SCL3_34_L (REG_SCL3_BASE + 0x68) ++#define REG_SCL3_34_H (REG_SCL3_BASE + 0x69) ++#define REG_SCL3_35_L (REG_SCL3_BASE + 0x6A) ++#define REG_SCL3_35_H (REG_SCL3_BASE + 0x6B) ++#define REG_SCL3_36_L (REG_SCL3_BASE + 0x6C) ++#define REG_SCL3_36_H (REG_SCL3_BASE + 0x6D) ++#define REG_SCL3_37_L (REG_SCL3_BASE + 0x6E) ++#define REG_SCL3_37_H (REG_SCL3_BASE + 0x6F) ++#define REG_SCL3_38_L (REG_SCL3_BASE + 0x70) ++#define REG_SCL3_38_H (REG_SCL3_BASE + 0x71) ++#define REG_SCL3_39_L (REG_SCL3_BASE + 0x72) ++#define REG_SCL3_39_H (REG_SCL3_BASE + 0x73) ++#define REG_SCL3_3A_L (REG_SCL3_BASE + 0x74) ++#define REG_SCL3_3A_H (REG_SCL3_BASE + 0x75) ++#define REG_SCL3_3B_L (REG_SCL3_BASE + 0x76) ++#define REG_SCL3_3B_H (REG_SCL3_BASE + 0x77) ++#define REG_SCL3_3C_L (REG_SCL3_BASE + 0x78) ++#define REG_SCL3_3C_H (REG_SCL3_BASE + 0x79) ++#define REG_SCL3_3D_L (REG_SCL3_BASE + 0x7A) ++#define REG_SCL3_3D_H (REG_SCL3_BASE + 0x7B) ++#define REG_SCL3_3E_L (REG_SCL3_BASE + 0x7C) ++#define REG_SCL3_3E_H (REG_SCL3_BASE + 0x7D) ++#define REG_SCL3_3F_L (REG_SCL3_BASE + 0x7E) ++#define REG_SCL3_3F_H (REG_SCL3_BASE + 0x7F) ++#define REG_SCL3_40_L (REG_SCL3_BASE + 0x80) ++#define REG_SCL3_40_H (REG_SCL3_BASE + 0x81) ++#define REG_SCL3_41_L (REG_SCL3_BASE + 0x82) ++#define REG_SCL3_41_H (REG_SCL3_BASE + 0x83) ++#define REG_SCL3_42_L (REG_SCL3_BASE + 0x84) ++#define REG_SCL3_42_H (REG_SCL3_BASE + 0x85) ++#define REG_SCL3_43_L (REG_SCL3_BASE + 0x86) ++#define REG_SCL3_43_H (REG_SCL3_BASE + 0x87) ++#define REG_SCL3_44_L (REG_SCL3_BASE + 0x88) ++#define REG_SCL3_44_H (REG_SCL3_BASE + 0x89) ++#define REG_SCL3_45_L (REG_SCL3_BASE + 0x8A) ++#define REG_SCL3_45_H (REG_SCL3_BASE + 0x8B) ++#define REG_SCL3_46_L (REG_SCL3_BASE + 0x8C) ++#define REG_SCL3_46_H (REG_SCL3_BASE + 0x8D) ++#define REG_SCL3_47_L (REG_SCL3_BASE + 0x8E) ++#define REG_SCL3_47_H (REG_SCL3_BASE + 0x8F) ++#define REG_SCL3_48_L (REG_SCL3_BASE + 0x90) ++#define REG_SCL3_48_H (REG_SCL3_BASE + 0x91) ++#define REG_SCL3_49_L (REG_SCL3_BASE + 0x92) ++#define REG_SCL3_49_H (REG_SCL3_BASE + 0x93) ++#define REG_SCL3_4A_L (REG_SCL3_BASE + 0x94) ++#define REG_SCL3_4A_H (REG_SCL3_BASE + 0x95) ++#define REG_SCL3_4B_L (REG_SCL3_BASE + 0x96) ++#define REG_SCL3_4B_H (REG_SCL3_BASE + 0x97) ++#define REG_SCL3_4C_L (REG_SCL3_BASE + 0x98) ++#define REG_SCL3_4C_H (REG_SCL3_BASE + 0x99) ++#define REG_SCL3_4D_L (REG_SCL3_BASE + 0x9A) ++#define REG_SCL3_4D_H (REG_SCL3_BASE + 0x9B) ++#define REG_SCL3_4E_L (REG_SCL3_BASE + 0x9C) ++#define REG_SCL3_4E_H (REG_SCL3_BASE + 0x9D) ++#define REG_SCL3_4F_L (REG_SCL3_BASE + 0x9E) ++#define REG_SCL3_4F_H (REG_SCL3_BASE + 0x9F) ++#define REG_SCL3_50_L (REG_SCL3_BASE + 0xA0) ++#define REG_SCL3_50_H (REG_SCL3_BASE + 0xA1) ++#define REG_SCL3_51_L (REG_SCL3_BASE + 0xA2) ++#define REG_SCL3_51_H (REG_SCL3_BASE + 0xA3) ++#define REG_SCL3_52_L (REG_SCL3_BASE + 0xA4) ++#define REG_SCL3_52_H (REG_SCL3_BASE + 0xA5) ++#define REG_SCL3_53_L (REG_SCL3_BASE + 0xA6) ++#define REG_SCL3_53_H (REG_SCL3_BASE + 0xA7) ++#define REG_SCL3_54_L (REG_SCL3_BASE + 0xA8) ++#define REG_SCL3_54_H (REG_SCL3_BASE + 0xA9) ++#define REG_SCL3_55_L (REG_SCL3_BASE + 0xAA) ++#define REG_SCL3_55_H (REG_SCL3_BASE + 0xAB) ++#define REG_SCL3_56_L (REG_SCL3_BASE + 0xAC) ++#define REG_SCL3_56_H (REG_SCL3_BASE + 0xAD) ++#define REG_SCL3_57_L (REG_SCL3_BASE + 0xAE) ++#define REG_SCL3_57_H (REG_SCL3_BASE + 0xAF) ++#define REG_SCL3_58_L (REG_SCL3_BASE + 0xB0) ++#define REG_SCL3_58_H (REG_SCL3_BASE + 0xB1) ++#define REG_SCL3_59_L (REG_SCL3_BASE + 0xB2) ++#define REG_SCL3_59_H (REG_SCL3_BASE + 0xB3) ++#define REG_SCL3_5A_L (REG_SCL3_BASE + 0xB4) ++#define REG_SCL3_5A_H (REG_SCL3_BASE + 0xB5) ++#define REG_SCL3_5B_L (REG_SCL3_BASE + 0xB6) ++#define REG_SCL3_5B_H (REG_SCL3_BASE + 0xB7) ++#define REG_SCL3_5C_L (REG_SCL3_BASE + 0xB8) ++#define REG_SCL3_5C_H (REG_SCL3_BASE + 0xB9) ++#define REG_SCL3_5D_L (REG_SCL3_BASE + 0xBA) ++#define REG_SCL3_5D_H (REG_SCL3_BASE + 0xBB) ++#define REG_SCL3_5E_L (REG_SCL3_BASE + 0xBC) ++#define REG_SCL3_5E_H (REG_SCL3_BASE + 0xBD) ++#define REG_SCL3_5F_L (REG_SCL3_BASE + 0xBE) ++#define REG_SCL3_5F_H (REG_SCL3_BASE + 0xBF) ++#define REG_SCL3_60_L (REG_SCL3_BASE + 0xC0) ++#define REG_SCL3_60_H (REG_SCL3_BASE + 0xC1) ++#define REG_SCL3_61_L (REG_SCL3_BASE + 0xC2) ++#define REG_SCL3_61_H (REG_SCL3_BASE + 0xC3) ++#define REG_SCL3_62_L (REG_SCL3_BASE + 0xC4) ++#define REG_SCL3_62_H (REG_SCL3_BASE + 0xC5) ++#define REG_SCL3_63_L (REG_SCL3_BASE + 0xC6) ++#define REG_SCL3_63_H (REG_SCL3_BASE + 0xC7) ++#define REG_SCL3_64_L (REG_SCL3_BASE + 0xC8) ++#define REG_SCL3_64_H (REG_SCL3_BASE + 0xC9) ++#define REG_SCL3_65_L (REG_SCL3_BASE + 0xCA) ++#define REG_SCL3_65_H (REG_SCL3_BASE + 0xCB) ++#define REG_SCL3_66_L (REG_SCL3_BASE + 0xCC) ++#define REG_SCL3_66_H (REG_SCL3_BASE + 0xCD) ++#define REG_SCL3_67_L (REG_SCL3_BASE + 0xCE) ++#define REG_SCL3_67_H (REG_SCL3_BASE + 0xCF) ++#define REG_SCL3_68_L (REG_SCL3_BASE + 0xD0) ++#define REG_SCL3_68_H (REG_SCL3_BASE + 0xD1) ++#define REG_SCL3_69_L (REG_SCL3_BASE + 0xD2) ++#define REG_SCL3_69_H (REG_SCL3_BASE + 0xD3) ++#define REG_SCL3_6A_L (REG_SCL3_BASE + 0xD4) ++#define REG_SCL3_6A_H (REG_SCL3_BASE + 0xD5) ++#define REG_SCL3_6B_L (REG_SCL3_BASE + 0xD6) ++#define REG_SCL3_6B_H (REG_SCL3_BASE + 0xD7) ++#define REG_SCL3_6C_L (REG_SCL3_BASE + 0xD8) ++#define REG_SCL3_6C_H (REG_SCL3_BASE + 0xD9) ++#define REG_SCL3_6D_L (REG_SCL3_BASE + 0xDA) ++#define REG_SCL3_6D_H (REG_SCL3_BASE + 0xDB) ++#define REG_SCL3_6E_L (REG_SCL3_BASE + 0xDC) ++#define REG_SCL3_6E_H (REG_SCL3_BASE + 0xDD) ++#define REG_SCL3_6F_L (REG_SCL3_BASE + 0xDE) ++#define REG_SCL3_6F_H (REG_SCL3_BASE + 0xDF) ++#define REG_SCL3_70_L (REG_SCL3_BASE + 0xE0) ++#define REG_SCL3_70_H (REG_SCL3_BASE + 0xE1) ++#define REG_SCL3_71_L (REG_SCL3_BASE + 0xE2) ++#define REG_SCL3_71_H (REG_SCL3_BASE + 0xE3) ++#define REG_SCL3_72_L (REG_SCL3_BASE + 0xE4) ++#define REG_SCL3_72_H (REG_SCL3_BASE + 0xE5) ++#define REG_SCL3_73_L (REG_SCL3_BASE + 0xE6) ++#define REG_SCL3_73_H (REG_SCL3_BASE + 0xE7) ++#define REG_SCL3_74_L (REG_SCL3_BASE + 0xE8) ++#define REG_SCL3_74_H (REG_SCL3_BASE + 0xE9) ++#define REG_SCL3_75_L (REG_SCL3_BASE + 0xEA) ++#define REG_SCL3_75_H (REG_SCL3_BASE + 0xEB) ++#define REG_SCL3_76_L (REG_SCL3_BASE + 0xEC) ++#define REG_SCL3_76_H (REG_SCL3_BASE + 0xED) ++#define REG_SCL3_77_L (REG_SCL3_BASE + 0xEE) ++#define REG_SCL3_77_H (REG_SCL3_BASE + 0xEF) ++#define REG_SCL3_78_L (REG_SCL3_BASE + 0xF0) ++#define REG_SCL3_78_H (REG_SCL3_BASE + 0xF1) ++#define REG_SCL3_79_L (REG_SCL3_BASE + 0xF2) ++#define REG_SCL3_79_H (REG_SCL3_BASE + 0xF3) ++#define REG_SCL3_7A_L (REG_SCL3_BASE + 0xF4) ++#define REG_SCL3_7A_H (REG_SCL3_BASE + 0xF5) ++#define REG_SCL3_7B_L (REG_SCL3_BASE + 0xF6) ++#define REG_SCL3_7B_H (REG_SCL3_BASE + 0xF7) ++#define REG_SCL3_7C_L (REG_SCL3_BASE + 0xF8) ++#define REG_SCL3_7C_H (REG_SCL3_BASE + 0xF9) ++#define REG_SCL3_7D_L (REG_SCL3_BASE + 0xFA) ++#define REG_SCL3_7D_H (REG_SCL3_BASE + 0xFB) ++#define REG_SCL3_7E_L (REG_SCL3_BASE + 0xFC) ++#define REG_SCL3_7E_H (REG_SCL3_BASE + 0xFD) ++#define REG_SCL3_7F_L (REG_SCL3_BASE + 0xFE) ++#define REG_SCL3_7F_H (REG_SCL3_BASE + 0xFF) ++ ++#define REG_VIP_SCNR_00_L (REG_VIP_SCNR_BASE + 0x00) ++#define REG_VIP_SCNR_00_H (REG_VIP_SCNR_BASE + 0x01) ++#define REG_VIP_SCNR_01_L (REG_VIP_SCNR_BASE + 0x02) ++#define REG_VIP_SCNR_01_H (REG_VIP_SCNR_BASE + 0x03) ++#define REG_VIP_SCNR_02_L (REG_VIP_SCNR_BASE + 0x04) ++#define REG_VIP_SCNR_02_H (REG_VIP_SCNR_BASE + 0x05) ++#define REG_VIP_SCNR_03_L (REG_VIP_SCNR_BASE + 0x06) ++#define REG_VIP_SCNR_03_H (REG_VIP_SCNR_BASE + 0x07) ++#define REG_VIP_SCNR_04_L (REG_VIP_SCNR_BASE + 0x08) ++#define REG_VIP_SCNR_04_H (REG_VIP_SCNR_BASE + 0x09) ++#define REG_VIP_SCNR_05_L (REG_VIP_SCNR_BASE + 0x0A) ++#define REG_VIP_SCNR_05_H (REG_VIP_SCNR_BASE + 0x0B) ++#define REG_VIP_SCNR_06_L (REG_VIP_SCNR_BASE + 0x0C) ++#define REG_VIP_SCNR_06_H (REG_VIP_SCNR_BASE + 0x0D) ++#define REG_VIP_SCNR_07_L (REG_VIP_SCNR_BASE + 0x0E) ++#define REG_VIP_SCNR_07_H (REG_VIP_SCNR_BASE + 0x0F) ++#define REG_VIP_SCNR_08_L (REG_VIP_SCNR_BASE + 0x10) ++#define REG_VIP_SCNR_08_H (REG_VIP_SCNR_BASE + 0x11) ++#define REG_VIP_SCNR_09_L (REG_VIP_SCNR_BASE + 0x12) ++#define REG_VIP_SCNR_09_H (REG_VIP_SCNR_BASE + 0x13) ++#define REG_VIP_SCNR_0A_L (REG_VIP_SCNR_BASE + 0x14) ++#define REG_VIP_SCNR_0A_H (REG_VIP_SCNR_BASE + 0x15) ++#define REG_VIP_SCNR_0B_L (REG_VIP_SCNR_BASE + 0x16) ++#define REG_VIP_SCNR_0B_H (REG_VIP_SCNR_BASE + 0x17) ++#define REG_VIP_SCNR_0C_L (REG_VIP_SCNR_BASE + 0x18) ++#define REG_VIP_SCNR_0C_H (REG_VIP_SCNR_BASE + 0x19) ++#define REG_VIP_SCNR_0D_L (REG_VIP_SCNR_BASE + 0x1A) ++#define REG_VIP_SCNR_0D_H (REG_VIP_SCNR_BASE + 0x1B) ++#define REG_VIP_SCNR_0E_L (REG_VIP_SCNR_BASE + 0x1C) ++#define REG_VIP_SCNR_0E_H (REG_VIP_SCNR_BASE + 0x1D) ++#define REG_VIP_SCNR_0F_L (REG_VIP_SCNR_BASE + 0x1E) ++#define REG_VIP_SCNR_0F_H (REG_VIP_SCNR_BASE + 0x1F) ++#define REG_VIP_SCNR_10_L (REG_VIP_SCNR_BASE + 0x20) ++#define REG_VIP_SCNR_10_H (REG_VIP_SCNR_BASE + 0x21) ++#define REG_VIP_SCNR_11_L (REG_VIP_SCNR_BASE + 0x22) ++#define REG_VIP_SCNR_11_H (REG_VIP_SCNR_BASE + 0x23) ++#define REG_VIP_SCNR_12_L (REG_VIP_SCNR_BASE + 0x24) ++#define REG_VIP_SCNR_12_H (REG_VIP_SCNR_BASE + 0x25) ++#define REG_VIP_SCNR_13_L (REG_VIP_SCNR_BASE + 0x26) ++#define REG_VIP_SCNR_13_H (REG_VIP_SCNR_BASE + 0x27) ++#define REG_VIP_SCNR_14_L (REG_VIP_SCNR_BASE + 0x28) ++#define REG_VIP_SCNR_14_H (REG_VIP_SCNR_BASE + 0x29) ++#define REG_VIP_SCNR_15_L (REG_VIP_SCNR_BASE + 0x2A) ++#define REG_VIP_SCNR_15_H (REG_VIP_SCNR_BASE + 0x2B) ++#define REG_VIP_SCNR_16_L (REG_VIP_SCNR_BASE + 0x2C) ++#define REG_VIP_SCNR_16_H (REG_VIP_SCNR_BASE + 0x2D) ++#define REG_VIP_SCNR_17_L (REG_VIP_SCNR_BASE + 0x2E) ++#define REG_VIP_SCNR_17_H (REG_VIP_SCNR_BASE + 0x2F) ++#define REG_VIP_SCNR_18_L (REG_VIP_SCNR_BASE + 0x30) ++#define REG_VIP_SCNR_18_H (REG_VIP_SCNR_BASE + 0x31) ++#define REG_VIP_SCNR_19_L (REG_VIP_SCNR_BASE + 0x32) ++#define REG_VIP_SCNR_19_H (REG_VIP_SCNR_BASE + 0x33) ++#define REG_VIP_SCNR_1A_L (REG_VIP_SCNR_BASE + 0x34) ++#define REG_VIP_SCNR_1A_H (REG_VIP_SCNR_BASE + 0x35) ++#define REG_VIP_SCNR_1B_L (REG_VIP_SCNR_BASE + 0x36) ++#define REG_VIP_SCNR_1B_H (REG_VIP_SCNR_BASE + 0x37) ++#define REG_VIP_SCNR_1C_L (REG_VIP_SCNR_BASE + 0x38) ++#define REG_VIP_SCNR_1C_H (REG_VIP_SCNR_BASE + 0x39) ++#define REG_VIP_SCNR_1D_L (REG_VIP_SCNR_BASE + 0x3A) ++#define REG_VIP_SCNR_1D_H (REG_VIP_SCNR_BASE + 0x3B) ++#define REG_VIP_SCNR_1E_L (REG_VIP_SCNR_BASE + 0x3C) ++#define REG_VIP_SCNR_1E_H (REG_VIP_SCNR_BASE + 0x3D) ++#define REG_VIP_SCNR_1F_L (REG_VIP_SCNR_BASE + 0x3E) ++#define REG_VIP_SCNR_1F_H (REG_VIP_SCNR_BASE + 0x3F) ++#define REG_VIP_SCNR_20_L (REG_VIP_SCNR_BASE + 0x40) ++#define REG_VIP_SCNR_20_H (REG_VIP_SCNR_BASE + 0x41) ++#define REG_VIP_SCNR_21_L (REG_VIP_SCNR_BASE + 0x42) ++#define REG_VIP_SCNR_21_H (REG_VIP_SCNR_BASE + 0x43) ++#define REG_VIP_SCNR_22_L (REG_VIP_SCNR_BASE + 0x44) ++#define REG_VIP_SCNR_22_H (REG_VIP_SCNR_BASE + 0x45) ++#define REG_VIP_SCNR_23_L (REG_VIP_SCNR_BASE + 0x46) ++#define REG_VIP_SCNR_23_H (REG_VIP_SCNR_BASE + 0x47) ++#define REG_VIP_SCNR_24_L (REG_VIP_SCNR_BASE + 0x48) ++#define REG_VIP_SCNR_24_H (REG_VIP_SCNR_BASE + 0x49) ++#define REG_VIP_SCNR_25_L (REG_VIP_SCNR_BASE + 0x4A) ++#define REG_VIP_SCNR_25_H (REG_VIP_SCNR_BASE + 0x4B) ++#define REG_VIP_SCNR_26_L (REG_VIP_SCNR_BASE + 0x4C) ++#define REG_VIP_SCNR_26_H (REG_VIP_SCNR_BASE + 0x4D) ++#define REG_VIP_SCNR_27_L (REG_VIP_SCNR_BASE + 0x4E) ++#define REG_VIP_SCNR_27_H (REG_VIP_SCNR_BASE + 0x4F) ++#define REG_VIP_SCNR_28_L (REG_VIP_SCNR_BASE + 0x50) ++#define REG_VIP_SCNR_28_H (REG_VIP_SCNR_BASE + 0x51) ++#define REG_VIP_SCNR_29_L (REG_VIP_SCNR_BASE + 0x52) ++#define REG_VIP_SCNR_29_H (REG_VIP_SCNR_BASE + 0x53) ++#define REG_VIP_SCNR_2A_L (REG_VIP_SCNR_BASE + 0x54) ++#define REG_VIP_SCNR_2A_H (REG_VIP_SCNR_BASE + 0x55) ++#define REG_VIP_SCNR_2B_L (REG_VIP_SCNR_BASE + 0x56) ++#define REG_VIP_SCNR_2B_H (REG_VIP_SCNR_BASE + 0x57) ++#define REG_VIP_SCNR_2C_L (REG_VIP_SCNR_BASE + 0x58) ++#define REG_VIP_SCNR_2C_H (REG_VIP_SCNR_BASE + 0x59) ++#define REG_VIP_SCNR_2D_L (REG_VIP_SCNR_BASE + 0x5A) ++#define REG_VIP_SCNR_2D_H (REG_VIP_SCNR_BASE + 0x5B) ++#define REG_VIP_SCNR_2E_L (REG_VIP_SCNR_BASE + 0x5C) ++#define REG_VIP_SCNR_2E_H (REG_VIP_SCNR_BASE + 0x5D) ++#define REG_VIP_SCNR_2F_L (REG_VIP_SCNR_BASE + 0x5E) ++#define REG_VIP_SCNR_2F_H (REG_VIP_SCNR_BASE + 0x5F) ++#define REG_VIP_SCNR_30_L (REG_VIP_SCNR_BASE + 0x60) ++#define REG_VIP_SCNR_30_H (REG_VIP_SCNR_BASE + 0x61) ++#define REG_VIP_SCNR_31_L (REG_VIP_SCNR_BASE + 0x62) ++#define REG_VIP_SCNR_31_H (REG_VIP_SCNR_BASE + 0x63) ++#define REG_VIP_SCNR_32_L (REG_VIP_SCNR_BASE + 0x64) ++#define REG_VIP_SCNR_32_H (REG_VIP_SCNR_BASE + 0x65) ++#define REG_VIP_SCNR_33_L (REG_VIP_SCNR_BASE + 0x66) ++#define REG_VIP_SCNR_33_H (REG_VIP_SCNR_BASE + 0x67) ++#define REG_VIP_SCNR_34_L (REG_VIP_SCNR_BASE + 0x68) ++#define REG_VIP_SCNR_34_H (REG_VIP_SCNR_BASE + 0x69) ++#define REG_VIP_SCNR_35_L (REG_VIP_SCNR_BASE + 0x6A) ++#define REG_VIP_SCNR_35_H (REG_VIP_SCNR_BASE + 0x6B) ++#define REG_VIP_SCNR_36_L (REG_VIP_SCNR_BASE + 0x6C) ++#define REG_VIP_SCNR_36_H (REG_VIP_SCNR_BASE + 0x6D) ++#define REG_VIP_SCNR_37_L (REG_VIP_SCNR_BASE + 0x6E) ++#define REG_VIP_SCNR_37_H (REG_VIP_SCNR_BASE + 0x6F) ++#define REG_VIP_SCNR_38_L (REG_VIP_SCNR_BASE + 0x70) ++#define REG_VIP_SCNR_38_H (REG_VIP_SCNR_BASE + 0x71) ++#define REG_VIP_SCNR_39_L (REG_VIP_SCNR_BASE + 0x72) ++#define REG_VIP_SCNR_39_H (REG_VIP_SCNR_BASE + 0x73) ++#define REG_VIP_SCNR_3A_L (REG_VIP_SCNR_BASE + 0x74) ++#define REG_VIP_SCNR_3A_H (REG_VIP_SCNR_BASE + 0x75) ++#define REG_VIP_SCNR_3B_L (REG_VIP_SCNR_BASE + 0x76) ++#define REG_VIP_SCNR_3B_H (REG_VIP_SCNR_BASE + 0x77) ++#define REG_VIP_SCNR_3C_L (REG_VIP_SCNR_BASE + 0x78) ++#define REG_VIP_SCNR_3C_H (REG_VIP_SCNR_BASE + 0x79) ++#define REG_VIP_SCNR_3D_L (REG_VIP_SCNR_BASE + 0x7A) ++#define REG_VIP_SCNR_3D_H (REG_VIP_SCNR_BASE + 0x7B) ++#define REG_VIP_SCNR_3E_L (REG_VIP_SCNR_BASE + 0x7C) ++#define REG_VIP_SCNR_3E_H (REG_VIP_SCNR_BASE + 0x7D) ++#define REG_VIP_SCNR_3F_L (REG_VIP_SCNR_BASE + 0x7E) ++#define REG_VIP_SCNR_3F_H (REG_VIP_SCNR_BASE + 0x7F) ++#define REG_VIP_SCNR_40_L (REG_VIP_SCNR_BASE + 0x80) ++#define REG_VIP_SCNR_40_H (REG_VIP_SCNR_BASE + 0x81) ++#define REG_VIP_SCNR_41_L (REG_VIP_SCNR_BASE + 0x82) ++#define REG_VIP_SCNR_41_H (REG_VIP_SCNR_BASE + 0x83) ++#define REG_VIP_SCNR_42_L (REG_VIP_SCNR_BASE + 0x84) ++#define REG_VIP_SCNR_42_H (REG_VIP_SCNR_BASE + 0x85) ++#define REG_VIP_SCNR_43_L (REG_VIP_SCNR_BASE + 0x86) ++#define REG_VIP_SCNR_43_H (REG_VIP_SCNR_BASE + 0x87) ++#define REG_VIP_SCNR_44_L (REG_VIP_SCNR_BASE + 0x88) ++#define REG_VIP_SCNR_44_H (REG_VIP_SCNR_BASE + 0x89) ++#define REG_VIP_SCNR_45_L (REG_VIP_SCNR_BASE + 0x8A) ++#define REG_VIP_SCNR_45_H (REG_VIP_SCNR_BASE + 0x8B) ++#define REG_VIP_SCNR_46_L (REG_VIP_SCNR_BASE + 0x8C) ++#define REG_VIP_SCNR_46_H (REG_VIP_SCNR_BASE + 0x8D) ++#define REG_VIP_SCNR_47_L (REG_VIP_SCNR_BASE + 0x8E) ++#define REG_VIP_SCNR_47_H (REG_VIP_SCNR_BASE + 0x8F) ++#define REG_VIP_SCNR_48_L (REG_VIP_SCNR_BASE + 0x90) ++#define REG_VIP_SCNR_48_H (REG_VIP_SCNR_BASE + 0x91) ++#define REG_VIP_SCNR_49_L (REG_VIP_SCNR_BASE + 0x92) ++#define REG_VIP_SCNR_49_H (REG_VIP_SCNR_BASE + 0x93) ++#define REG_VIP_SCNR_4A_L (REG_VIP_SCNR_BASE + 0x94) ++#define REG_VIP_SCNR_4A_H (REG_VIP_SCNR_BASE + 0x95) ++#define REG_VIP_SCNR_4B_L (REG_VIP_SCNR_BASE + 0x96) ++#define REG_VIP_SCNR_4B_H (REG_VIP_SCNR_BASE + 0x97) ++#define REG_VIP_SCNR_4C_L (REG_VIP_SCNR_BASE + 0x98) ++#define REG_VIP_SCNR_4C_H (REG_VIP_SCNR_BASE + 0x99) ++#define REG_VIP_SCNR_4D_L (REG_VIP_SCNR_BASE + 0x9A) ++#define REG_VIP_SCNR_4D_H (REG_VIP_SCNR_BASE + 0x9B) ++#define REG_VIP_SCNR_4E_L (REG_VIP_SCNR_BASE + 0x9C) ++#define REG_VIP_SCNR_4E_H (REG_VIP_SCNR_BASE + 0x9D) ++#define REG_VIP_SCNR_4F_L (REG_VIP_SCNR_BASE + 0x9E) ++#define REG_VIP_SCNR_4F_H (REG_VIP_SCNR_BASE + 0x9F) ++#define REG_VIP_SCNR_50_L (REG_VIP_SCNR_BASE + 0xA0) ++#define REG_VIP_SCNR_50_H (REG_VIP_SCNR_BASE + 0xA1) ++#define REG_VIP_SCNR_51_L (REG_VIP_SCNR_BASE + 0xA2) ++#define REG_VIP_SCNR_51_H (REG_VIP_SCNR_BASE + 0xA3) ++#define REG_VIP_SCNR_52_L (REG_VIP_SCNR_BASE + 0xA4) ++#define REG_VIP_SCNR_52_H (REG_VIP_SCNR_BASE + 0xA5) ++#define REG_VIP_SCNR_53_L (REG_VIP_SCNR_BASE + 0xA6) ++#define REG_VIP_SCNR_53_H (REG_VIP_SCNR_BASE + 0xA7) ++#define REG_VIP_SCNR_54_L (REG_VIP_SCNR_BASE + 0xA8) ++#define REG_VIP_SCNR_54_H (REG_VIP_SCNR_BASE + 0xA9) ++#define REG_VIP_SCNR_55_L (REG_VIP_SCNR_BASE + 0xAA) ++#define REG_VIP_SCNR_55_H (REG_VIP_SCNR_BASE + 0xAB) ++#define REG_VIP_SCNR_56_L (REG_VIP_SCNR_BASE + 0xAC) ++#define REG_VIP_SCNR_56_H (REG_VIP_SCNR_BASE + 0xAD) ++#define REG_VIP_SCNR_57_L (REG_VIP_SCNR_BASE + 0xAE) ++#define REG_VIP_SCNR_57_H (REG_VIP_SCNR_BASE + 0xAF) ++#define REG_VIP_SCNR_58_L (REG_VIP_SCNR_BASE + 0xB0) ++#define REG_VIP_SCNR_58_H (REG_VIP_SCNR_BASE + 0xB1) ++#define REG_VIP_SCNR_59_L (REG_VIP_SCNR_BASE + 0xB2) ++#define REG_VIP_SCNR_59_H (REG_VIP_SCNR_BASE + 0xB3) ++#define REG_VIP_SCNR_5A_L (REG_VIP_SCNR_BASE + 0xB4) ++#define REG_VIP_SCNR_5A_H (REG_VIP_SCNR_BASE + 0xB5) ++#define REG_VIP_SCNR_5B_L (REG_VIP_SCNR_BASE + 0xB6) ++#define REG_VIP_SCNR_5B_H (REG_VIP_SCNR_BASE + 0xB7) ++#define REG_VIP_SCNR_5C_L (REG_VIP_SCNR_BASE + 0xB8) ++#define REG_VIP_SCNR_5C_H (REG_VIP_SCNR_BASE + 0xB9) ++#define REG_VIP_SCNR_5D_L (REG_VIP_SCNR_BASE + 0xBA) ++#define REG_VIP_SCNR_5D_H (REG_VIP_SCNR_BASE + 0xBB) ++#define REG_VIP_SCNR_5E_L (REG_VIP_SCNR_BASE + 0xBC) ++#define REG_VIP_SCNR_5E_H (REG_VIP_SCNR_BASE + 0xBD) ++#define REG_VIP_SCNR_5F_L (REG_VIP_SCNR_BASE + 0xBE) ++#define REG_VIP_SCNR_5F_H (REG_VIP_SCNR_BASE + 0xBF) ++#define REG_VIP_SCNR_60_L (REG_VIP_SCNR_BASE + 0xC0) ++#define REG_VIP_SCNR_60_H (REG_VIP_SCNR_BASE + 0xC1) ++#define REG_VIP_SCNR_61_L (REG_VIP_SCNR_BASE + 0xC2) ++#define REG_VIP_SCNR_61_H (REG_VIP_SCNR_BASE + 0xC3) ++#define REG_VIP_SCNR_62_L (REG_VIP_SCNR_BASE + 0xC4) ++#define REG_VIP_SCNR_62_H (REG_VIP_SCNR_BASE + 0xC5) ++#define REG_VIP_SCNR_63_L (REG_VIP_SCNR_BASE + 0xC6) ++#define REG_VIP_SCNR_63_H (REG_VIP_SCNR_BASE + 0xC7) ++#define REG_VIP_SCNR_64_L (REG_VIP_SCNR_BASE + 0xC8) ++#define REG_VIP_SCNR_64_H (REG_VIP_SCNR_BASE + 0xC9) ++#define REG_VIP_SCNR_65_L (REG_VIP_SCNR_BASE + 0xCA) ++#define REG_VIP_SCNR_65_H (REG_VIP_SCNR_BASE + 0xCB) ++#define REG_VIP_SCNR_66_L (REG_VIP_SCNR_BASE + 0xCC) ++#define REG_VIP_SCNR_66_H (REG_VIP_SCNR_BASE + 0xCD) ++#define REG_VIP_SCNR_67_L (REG_VIP_SCNR_BASE + 0xCE) ++#define REG_VIP_SCNR_67_H (REG_VIP_SCNR_BASE + 0xCF) ++#define REG_VIP_SCNR_68_L (REG_VIP_SCNR_BASE + 0xD0) ++#define REG_VIP_SCNR_68_H (REG_VIP_SCNR_BASE + 0xD1) ++#define REG_VIP_SCNR_69_L (REG_VIP_SCNR_BASE + 0xD2) ++#define REG_VIP_SCNR_69_H (REG_VIP_SCNR_BASE + 0xD3) ++#define REG_VIP_SCNR_6A_L (REG_VIP_SCNR_BASE + 0xD4) ++#define REG_VIP_SCNR_6A_H (REG_VIP_SCNR_BASE + 0xD5) ++#define REG_VIP_SCNR_6B_L (REG_VIP_SCNR_BASE + 0xD6) ++#define REG_VIP_SCNR_6B_H (REG_VIP_SCNR_BASE + 0xD7) ++#define REG_VIP_SCNR_6C_L (REG_VIP_SCNR_BASE + 0xD8) ++#define REG_VIP_SCNR_6C_H (REG_VIP_SCNR_BASE + 0xD9) ++#define REG_VIP_SCNR_6D_L (REG_VIP_SCNR_BASE + 0xDA) ++#define REG_VIP_SCNR_6D_H (REG_VIP_SCNR_BASE + 0xDB) ++#define REG_VIP_SCNR_6E_L (REG_VIP_SCNR_BASE + 0xDC) ++#define REG_VIP_SCNR_6E_H (REG_VIP_SCNR_BASE + 0xDD) ++#define REG_VIP_SCNR_6F_L (REG_VIP_SCNR_BASE + 0xDE) ++#define REG_VIP_SCNR_6F_H (REG_VIP_SCNR_BASE + 0xDF) ++#define REG_VIP_SCNR_70_L (REG_VIP_SCNR_BASE + 0xE0) ++#define REG_VIP_SCNR_70_H (REG_VIP_SCNR_BASE + 0xE1) ++#define REG_VIP_SCNR_71_L (REG_VIP_SCNR_BASE + 0xE2) ++#define REG_VIP_SCNR_71_H (REG_VIP_SCNR_BASE + 0xE3) ++#define REG_VIP_SCNR_72_L (REG_VIP_SCNR_BASE + 0xE4) ++#define REG_VIP_SCNR_72_H (REG_VIP_SCNR_BASE + 0xE5) ++#define REG_VIP_SCNR_73_L (REG_VIP_SCNR_BASE + 0xE6) ++#define REG_VIP_SCNR_73_H (REG_VIP_SCNR_BASE + 0xE7) ++#define REG_VIP_SCNR_74_L (REG_VIP_SCNR_BASE + 0xE8) ++#define REG_VIP_SCNR_74_H (REG_VIP_SCNR_BASE + 0xE9) ++#define REG_VIP_SCNR_75_L (REG_VIP_SCNR_BASE + 0xEA) ++#define REG_VIP_SCNR_75_H (REG_VIP_SCNR_BASE + 0xEB) ++#define REG_VIP_SCNR_76_L (REG_VIP_SCNR_BASE + 0xEC) ++#define REG_VIP_SCNR_76_H (REG_VIP_SCNR_BASE + 0xED) ++#define REG_VIP_SCNR_77_L (REG_VIP_SCNR_BASE + 0xEE) ++#define REG_VIP_SCNR_77_H (REG_VIP_SCNR_BASE + 0xEF) ++#define REG_VIP_SCNR_78_L (REG_VIP_SCNR_BASE + 0xF0) ++#define REG_VIP_SCNR_78_H (REG_VIP_SCNR_BASE + 0xF1) ++#define REG_VIP_SCNR_79_L (REG_VIP_SCNR_BASE + 0xF2) ++#define REG_VIP_SCNR_79_H (REG_VIP_SCNR_BASE + 0xF3) ++#define REG_VIP_SCNR_7A_L (REG_VIP_SCNR_BASE + 0xF4) ++#define REG_VIP_SCNR_7A_H (REG_VIP_SCNR_BASE + 0xF5) ++#define REG_VIP_SCNR_7B_L (REG_VIP_SCNR_BASE + 0xF6) ++#define REG_VIP_SCNR_7B_H (REG_VIP_SCNR_BASE + 0xF7) ++#define REG_VIP_SCNR_7C_L (REG_VIP_SCNR_BASE + 0xF8) ++#define REG_VIP_SCNR_7C_H (REG_VIP_SCNR_BASE + 0xF9) ++#define REG_VIP_SCNR_7D_L (REG_VIP_SCNR_BASE + 0xFA) ++#define REG_VIP_SCNR_7D_H (REG_VIP_SCNR_BASE + 0xFB) ++#define REG_VIP_SCNR_7E_L (REG_VIP_SCNR_BASE + 0xFC) ++#define REG_VIP_SCNR_7E_H (REG_VIP_SCNR_BASE + 0xFD) ++#define REG_VIP_SCNR_7F_L (REG_VIP_SCNR_BASE + 0xFE) ++#define REG_VIP_SCNR_7F_H (REG_VIP_SCNR_BASE + 0xFF) ++ ++#define REG_VIP_WDR_00_L (REG_VIP_WDR_BASE + 0x00) ++#define REG_VIP_WDR_00_H (REG_VIP_WDR_BASE + 0x01) ++#define REG_VIP_WDR_01_L (REG_VIP_WDR_BASE + 0x02) ++#define REG_VIP_WDR_01_H (REG_VIP_WDR_BASE + 0x03) ++#define REG_VIP_WDR_02_L (REG_VIP_WDR_BASE + 0x04) ++#define REG_VIP_WDR_02_H (REG_VIP_WDR_BASE + 0x05) ++#define REG_VIP_WDR_03_L (REG_VIP_WDR_BASE + 0x06) ++#define REG_VIP_WDR_03_H (REG_VIP_WDR_BASE + 0x07) ++#define REG_VIP_WDR_04_L (REG_VIP_WDR_BASE + 0x08) ++#define REG_VIP_WDR_04_H (REG_VIP_WDR_BASE + 0x09) ++#define REG_VIP_WDR_05_L (REG_VIP_WDR_BASE + 0x0A) ++#define REG_VIP_WDR_05_H (REG_VIP_WDR_BASE + 0x0B) ++#define REG_VIP_WDR_06_L (REG_VIP_WDR_BASE + 0x0C) ++#define REG_VIP_WDR_06_H (REG_VIP_WDR_BASE + 0x0D) ++#define REG_VIP_WDR_07_L (REG_VIP_WDR_BASE + 0x0E) ++#define REG_VIP_WDR_07_H (REG_VIP_WDR_BASE + 0x0F) ++#define REG_VIP_WDR_08_L (REG_VIP_WDR_BASE + 0x10) ++#define REG_VIP_WDR_08_H (REG_VIP_WDR_BASE + 0x11) ++#define REG_VIP_WDR_09_L (REG_VIP_WDR_BASE + 0x12) ++#define REG_VIP_WDR_09_H (REG_VIP_WDR_BASE + 0x13) ++#define REG_VIP_WDR_0A_L (REG_VIP_WDR_BASE + 0x14) ++#define REG_VIP_WDR_0A_H (REG_VIP_WDR_BASE + 0x15) ++#define REG_VIP_WDR_0B_L (REG_VIP_WDR_BASE + 0x16) ++#define REG_VIP_WDR_0B_H (REG_VIP_WDR_BASE + 0x17) ++#define REG_VIP_WDR_0C_L (REG_VIP_WDR_BASE + 0x18) ++#define REG_VIP_WDR_0C_H (REG_VIP_WDR_BASE + 0x19) ++#define REG_VIP_WDR_0D_L (REG_VIP_WDR_BASE + 0x1A) ++#define REG_VIP_WDR_0D_H (REG_VIP_WDR_BASE + 0x1B) ++#define REG_VIP_WDR_0E_L (REG_VIP_WDR_BASE + 0x1C) ++#define REG_VIP_WDR_0E_H (REG_VIP_WDR_BASE + 0x1D) ++#define REG_VIP_WDR_0F_L (REG_VIP_WDR_BASE + 0x1E) ++#define REG_VIP_WDR_0F_H (REG_VIP_WDR_BASE + 0x1F) ++#define REG_VIP_WDR_10_L (REG_VIP_WDR_BASE + 0x20) ++#define REG_VIP_WDR_10_H (REG_VIP_WDR_BASE + 0x21) ++#define REG_VIP_WDR_11_L (REG_VIP_WDR_BASE + 0x22) ++#define REG_VIP_WDR_11_H (REG_VIP_WDR_BASE + 0x23) ++#define REG_VIP_WDR_12_L (REG_VIP_WDR_BASE + 0x24) ++#define REG_VIP_WDR_12_H (REG_VIP_WDR_BASE + 0x25) ++#define REG_VIP_WDR_13_L (REG_VIP_WDR_BASE + 0x26) ++#define REG_VIP_WDR_13_H (REG_VIP_WDR_BASE + 0x27) ++#define REG_VIP_WDR_14_L (REG_VIP_WDR_BASE + 0x28) ++#define REG_VIP_WDR_14_H (REG_VIP_WDR_BASE + 0x29) ++#define REG_VIP_WDR_15_L (REG_VIP_WDR_BASE + 0x2A) ++#define REG_VIP_WDR_15_H (REG_VIP_WDR_BASE + 0x2B) ++#define REG_VIP_WDR_16_L (REG_VIP_WDR_BASE + 0x2C) ++#define REG_VIP_WDR_16_H (REG_VIP_WDR_BASE + 0x2D) ++#define REG_VIP_WDR_17_L (REG_VIP_WDR_BASE + 0x2E) ++#define REG_VIP_WDR_17_H (REG_VIP_WDR_BASE + 0x2F) ++#define REG_VIP_WDR_18_L (REG_VIP_WDR_BASE + 0x30) ++#define REG_VIP_WDR_18_H (REG_VIP_WDR_BASE + 0x31) ++#define REG_VIP_WDR_19_L (REG_VIP_WDR_BASE + 0x32) ++#define REG_VIP_WDR_19_H (REG_VIP_WDR_BASE + 0x33) ++#define REG_VIP_WDR_1A_L (REG_VIP_WDR_BASE + 0x34) ++#define REG_VIP_WDR_1A_H (REG_VIP_WDR_BASE + 0x35) ++#define REG_VIP_WDR_1B_L (REG_VIP_WDR_BASE + 0x36) ++#define REG_VIP_WDR_1B_H (REG_VIP_WDR_BASE + 0x37) ++#define REG_VIP_WDR_1C_L (REG_VIP_WDR_BASE + 0x38) ++#define REG_VIP_WDR_1C_H (REG_VIP_WDR_BASE + 0x39) ++#define REG_VIP_WDR_1D_L (REG_VIP_WDR_BASE + 0x3A) ++#define REG_VIP_WDR_1D_H (REG_VIP_WDR_BASE + 0x3B) ++#define REG_VIP_WDR_1E_L (REG_VIP_WDR_BASE + 0x3C) ++#define REG_VIP_WDR_1E_H (REG_VIP_WDR_BASE + 0x3D) ++#define REG_VIP_WDR_1F_L (REG_VIP_WDR_BASE + 0x3E) ++#define REG_VIP_WDR_1F_H (REG_VIP_WDR_BASE + 0x3F) ++#define REG_VIP_WDR_20_L (REG_VIP_WDR_BASE + 0x40) ++#define REG_VIP_WDR_20_H (REG_VIP_WDR_BASE + 0x41) ++#define REG_VIP_WDR_21_L (REG_VIP_WDR_BASE + 0x42) ++#define REG_VIP_WDR_21_H (REG_VIP_WDR_BASE + 0x43) ++#define REG_VIP_WDR_22_L (REG_VIP_WDR_BASE + 0x44) ++#define REG_VIP_WDR_22_H (REG_VIP_WDR_BASE + 0x45) ++#define REG_VIP_WDR_23_L (REG_VIP_WDR_BASE + 0x46) ++#define REG_VIP_WDR_23_H (REG_VIP_WDR_BASE + 0x47) ++#define REG_VIP_WDR_24_L (REG_VIP_WDR_BASE + 0x48) ++#define REG_VIP_WDR_24_H (REG_VIP_WDR_BASE + 0x49) ++#define REG_VIP_WDR_25_L (REG_VIP_WDR_BASE + 0x4A) ++#define REG_VIP_WDR_25_H (REG_VIP_WDR_BASE + 0x4B) ++#define REG_VIP_WDR_26_L (REG_VIP_WDR_BASE + 0x4C) ++#define REG_VIP_WDR_26_H (REG_VIP_WDR_BASE + 0x4D) ++#define REG_VIP_WDR_27_L (REG_VIP_WDR_BASE + 0x4E) ++#define REG_VIP_WDR_27_H (REG_VIP_WDR_BASE + 0x4F) ++#define REG_VIP_WDR_28_L (REG_VIP_WDR_BASE + 0x50) ++#define REG_VIP_WDR_28_H (REG_VIP_WDR_BASE + 0x51) ++#define REG_VIP_WDR_29_L (REG_VIP_WDR_BASE + 0x52) ++#define REG_VIP_WDR_29_H (REG_VIP_WDR_BASE + 0x53) ++#define REG_VIP_WDR_2A_L (REG_VIP_WDR_BASE + 0x54) ++#define REG_VIP_WDR_2A_H (REG_VIP_WDR_BASE + 0x55) ++#define REG_VIP_WDR_2B_L (REG_VIP_WDR_BASE + 0x56) ++#define REG_VIP_WDR_2B_H (REG_VIP_WDR_BASE + 0x57) ++#define REG_VIP_WDR_2C_L (REG_VIP_WDR_BASE + 0x58) ++#define REG_VIP_WDR_2C_H (REG_VIP_WDR_BASE + 0x59) ++#define REG_VIP_WDR_2D_L (REG_VIP_WDR_BASE + 0x5A) ++#define REG_VIP_WDR_2D_H (REG_VIP_WDR_BASE + 0x5B) ++#define REG_VIP_WDR_2E_L (REG_VIP_WDR_BASE + 0x5C) ++#define REG_VIP_WDR_2E_H (REG_VIP_WDR_BASE + 0x5D) ++#define REG_VIP_WDR_2F_L (REG_VIP_WDR_BASE + 0x5E) ++#define REG_VIP_WDR_2F_H (REG_VIP_WDR_BASE + 0x5F) ++#define REG_VIP_WDR_30_L (REG_VIP_WDR_BASE + 0x60) ++#define REG_VIP_WDR_30_H (REG_VIP_WDR_BASE + 0x61) ++#define REG_VIP_WDR_31_L (REG_VIP_WDR_BASE + 0x62) ++#define REG_VIP_WDR_31_H (REG_VIP_WDR_BASE + 0x63) ++#define REG_VIP_WDR_32_L (REG_VIP_WDR_BASE + 0x64) ++#define REG_VIP_WDR_32_H (REG_VIP_WDR_BASE + 0x65) ++#define REG_VIP_WDR_33_L (REG_VIP_WDR_BASE + 0x66) ++#define REG_VIP_WDR_33_H (REG_VIP_WDR_BASE + 0x67) ++#define REG_VIP_WDR_34_L (REG_VIP_WDR_BASE + 0x68) ++#define REG_VIP_WDR_34_H (REG_VIP_WDR_BASE + 0x69) ++#define REG_VIP_WDR_35_L (REG_VIP_WDR_BASE + 0x6A) ++#define REG_VIP_WDR_35_H (REG_VIP_WDR_BASE + 0x6B) ++#define REG_VIP_WDR_36_L (REG_VIP_WDR_BASE + 0x6C) ++#define REG_VIP_WDR_36_H (REG_VIP_WDR_BASE + 0x6D) ++#define REG_VIP_WDR_37_L (REG_VIP_WDR_BASE + 0x6E) ++#define REG_VIP_WDR_37_H (REG_VIP_WDR_BASE + 0x6F) ++#define REG_VIP_WDR_38_L (REG_VIP_WDR_BASE + 0x70) ++#define REG_VIP_WDR_38_H (REG_VIP_WDR_BASE + 0x71) ++#define REG_VIP_WDR_39_L (REG_VIP_WDR_BASE + 0x72) ++#define REG_VIP_WDR_39_H (REG_VIP_WDR_BASE + 0x73) ++#define REG_VIP_WDR_3A_L (REG_VIP_WDR_BASE + 0x74) ++#define REG_VIP_WDR_3A_H (REG_VIP_WDR_BASE + 0x75) ++#define REG_VIP_WDR_3B_L (REG_VIP_WDR_BASE + 0x76) ++#define REG_VIP_WDR_3B_H (REG_VIP_WDR_BASE + 0x77) ++#define REG_VIP_WDR_3C_L (REG_VIP_WDR_BASE + 0x78) ++#define REG_VIP_WDR_3C_H (REG_VIP_WDR_BASE + 0x79) ++#define REG_VIP_WDR_3D_L (REG_VIP_WDR_BASE + 0x7A) ++#define REG_VIP_WDR_3D_H (REG_VIP_WDR_BASE + 0x7B) ++#define REG_VIP_WDR_3E_L (REG_VIP_WDR_BASE + 0x7C) ++#define REG_VIP_WDR_3E_H (REG_VIP_WDR_BASE + 0x7D) ++#define REG_VIP_WDR_3F_L (REG_VIP_WDR_BASE + 0x7E) ++#define REG_VIP_WDR_3F_H (REG_VIP_WDR_BASE + 0x7F) ++#define REG_VIP_WDR_40_L (REG_VIP_WDR_BASE + 0x80) ++#define REG_VIP_WDR_40_H (REG_VIP_WDR_BASE + 0x81) ++#define REG_VIP_WDR_41_L (REG_VIP_WDR_BASE + 0x82) ++#define REG_VIP_WDR_41_H (REG_VIP_WDR_BASE + 0x83) ++#define REG_VIP_WDR_42_L (REG_VIP_WDR_BASE + 0x84) ++#define REG_VIP_WDR_42_H (REG_VIP_WDR_BASE + 0x85) ++#define REG_VIP_WDR_43_L (REG_VIP_WDR_BASE + 0x86) ++#define REG_VIP_WDR_43_H (REG_VIP_WDR_BASE + 0x87) ++#define REG_VIP_WDR_44_L (REG_VIP_WDR_BASE + 0x88) ++#define REG_VIP_WDR_44_H (REG_VIP_WDR_BASE + 0x89) ++#define REG_VIP_WDR_45_L (REG_VIP_WDR_BASE + 0x8A) ++#define REG_VIP_WDR_45_H (REG_VIP_WDR_BASE + 0x8B) ++#define REG_VIP_WDR_46_L (REG_VIP_WDR_BASE + 0x8C) ++#define REG_VIP_WDR_46_H (REG_VIP_WDR_BASE + 0x8D) ++#define REG_VIP_WDR_47_L (REG_VIP_WDR_BASE + 0x8E) ++#define REG_VIP_WDR_47_H (REG_VIP_WDR_BASE + 0x8F) ++#define REG_VIP_WDR_48_L (REG_VIP_WDR_BASE + 0x90) ++#define REG_VIP_WDR_48_H (REG_VIP_WDR_BASE + 0x91) ++#define REG_VIP_WDR_49_L (REG_VIP_WDR_BASE + 0x92) ++#define REG_VIP_WDR_49_H (REG_VIP_WDR_BASE + 0x93) ++#define REG_VIP_WDR_4A_L (REG_VIP_WDR_BASE + 0x94) ++#define REG_VIP_WDR_4A_H (REG_VIP_WDR_BASE + 0x95) ++#define REG_VIP_WDR_4B_L (REG_VIP_WDR_BASE + 0x96) ++#define REG_VIP_WDR_4B_H (REG_VIP_WDR_BASE + 0x97) ++#define REG_VIP_WDR_4C_L (REG_VIP_WDR_BASE + 0x98) ++#define REG_VIP_WDR_4C_H (REG_VIP_WDR_BASE + 0x99) ++#define REG_VIP_WDR_4D_L (REG_VIP_WDR_BASE + 0x9A) ++#define REG_VIP_WDR_4D_H (REG_VIP_WDR_BASE + 0x9B) ++#define REG_VIP_WDR_4E_L (REG_VIP_WDR_BASE + 0x9C) ++#define REG_VIP_WDR_4E_H (REG_VIP_WDR_BASE + 0x9D) ++#define REG_VIP_WDR_4F_L (REG_VIP_WDR_BASE + 0x9E) ++#define REG_VIP_WDR_4F_H (REG_VIP_WDR_BASE + 0x9F) ++#define REG_VIP_WDR_50_L (REG_VIP_WDR_BASE + 0xA0) ++#define REG_VIP_WDR_50_H (REG_VIP_WDR_BASE + 0xA1) ++#define REG_VIP_WDR_51_L (REG_VIP_WDR_BASE + 0xA2) ++#define REG_VIP_WDR_51_H (REG_VIP_WDR_BASE + 0xA3) ++#define REG_VIP_WDR_52_L (REG_VIP_WDR_BASE + 0xA4) ++#define REG_VIP_WDR_52_H (REG_VIP_WDR_BASE + 0xA5) ++#define REG_VIP_WDR_53_L (REG_VIP_WDR_BASE + 0xA6) ++#define REG_VIP_WDR_53_H (REG_VIP_WDR_BASE + 0xA7) ++#define REG_VIP_WDR_54_L (REG_VIP_WDR_BASE + 0xA8) ++#define REG_VIP_WDR_54_H (REG_VIP_WDR_BASE + 0xA9) ++#define REG_VIP_WDR_55_L (REG_VIP_WDR_BASE + 0xAA) ++#define REG_VIP_WDR_55_H (REG_VIP_WDR_BASE + 0xAB) ++#define REG_VIP_WDR_56_L (REG_VIP_WDR_BASE + 0xAC) ++#define REG_VIP_WDR_56_H (REG_VIP_WDR_BASE + 0xAD) ++#define REG_VIP_WDR_57_L (REG_VIP_WDR_BASE + 0xAE) ++#define REG_VIP_WDR_57_H (REG_VIP_WDR_BASE + 0xAF) ++#define REG_VIP_WDR_58_L (REG_VIP_WDR_BASE + 0xB0) ++#define REG_VIP_WDR_58_H (REG_VIP_WDR_BASE + 0xB1) ++#define REG_VIP_WDR_59_L (REG_VIP_WDR_BASE + 0xB2) ++#define REG_VIP_WDR_59_H (REG_VIP_WDR_BASE + 0xB3) ++#define REG_VIP_WDR_5A_L (REG_VIP_WDR_BASE + 0xB4) ++#define REG_VIP_WDR_5A_H (REG_VIP_WDR_BASE + 0xB5) ++#define REG_VIP_WDR_5B_L (REG_VIP_WDR_BASE + 0xB6) ++#define REG_VIP_WDR_5B_H (REG_VIP_WDR_BASE + 0xB7) ++#define REG_VIP_WDR_5C_L (REG_VIP_WDR_BASE + 0xB8) ++#define REG_VIP_WDR_5C_H (REG_VIP_WDR_BASE + 0xB9) ++#define REG_VIP_WDR_5D_L (REG_VIP_WDR_BASE + 0xBA) ++#define REG_VIP_WDR_5D_H (REG_VIP_WDR_BASE + 0xBB) ++#define REG_VIP_WDR_5E_L (REG_VIP_WDR_BASE + 0xBC) ++#define REG_VIP_WDR_5E_H (REG_VIP_WDR_BASE + 0xBD) ++#define REG_VIP_WDR_5F_L (REG_VIP_WDR_BASE + 0xBE) ++#define REG_VIP_WDR_5F_H (REG_VIP_WDR_BASE + 0xBF) ++#define REG_VIP_WDR_60_L (REG_VIP_WDR_BASE + 0xC0) ++#define REG_VIP_WDR_60_H (REG_VIP_WDR_BASE + 0xC1) ++#define REG_VIP_WDR_61_L (REG_VIP_WDR_BASE + 0xC2) ++#define REG_VIP_WDR_61_H (REG_VIP_WDR_BASE + 0xC3) ++#define REG_VIP_WDR_62_L (REG_VIP_WDR_BASE + 0xC4) ++#define REG_VIP_WDR_62_H (REG_VIP_WDR_BASE + 0xC5) ++#define REG_VIP_WDR_63_L (REG_VIP_WDR_BASE + 0xC6) ++#define REG_VIP_WDR_63_H (REG_VIP_WDR_BASE + 0xC7) ++#define REG_VIP_WDR_64_L (REG_VIP_WDR_BASE + 0xC8) ++#define REG_VIP_WDR_64_H (REG_VIP_WDR_BASE + 0xC9) ++#define REG_VIP_WDR_65_L (REG_VIP_WDR_BASE + 0xCA) ++#define REG_VIP_WDR_65_H (REG_VIP_WDR_BASE + 0xCB) ++#define REG_VIP_WDR_66_L (REG_VIP_WDR_BASE + 0xCC) ++#define REG_VIP_WDR_66_H (REG_VIP_WDR_BASE + 0xCD) ++#define REG_VIP_WDR_67_L (REG_VIP_WDR_BASE + 0xCE) ++#define REG_VIP_WDR_67_H (REG_VIP_WDR_BASE + 0xCF) ++#define REG_VIP_WDR_68_L (REG_VIP_WDR_BASE + 0xD0) ++#define REG_VIP_WDR_68_H (REG_VIP_WDR_BASE + 0xD1) ++#define REG_VIP_WDR_69_L (REG_VIP_WDR_BASE + 0xD2) ++#define REG_VIP_WDR_69_H (REG_VIP_WDR_BASE + 0xD3) ++#define REG_VIP_WDR_6A_L (REG_VIP_WDR_BASE + 0xD4) ++#define REG_VIP_WDR_6A_H (REG_VIP_WDR_BASE + 0xD5) ++#define REG_VIP_WDR_6B_L (REG_VIP_WDR_BASE + 0xD6) ++#define REG_VIP_WDR_6B_H (REG_VIP_WDR_BASE + 0xD7) ++#define REG_VIP_WDR_6C_L (REG_VIP_WDR_BASE + 0xD8) ++#define REG_VIP_WDR_6C_H (REG_VIP_WDR_BASE + 0xD9) ++#define REG_VIP_WDR_6D_L (REG_VIP_WDR_BASE + 0xDA) ++#define REG_VIP_WDR_6D_H (REG_VIP_WDR_BASE + 0xDB) ++#define REG_VIP_WDR_6E_L (REG_VIP_WDR_BASE + 0xDC) ++#define REG_VIP_WDR_6E_H (REG_VIP_WDR_BASE + 0xDD) ++#define REG_VIP_WDR_6F_L (REG_VIP_WDR_BASE + 0xDE) ++#define REG_VIP_WDR_6F_H (REG_VIP_WDR_BASE + 0xDF) ++#define REG_VIP_WDR_70_L (REG_VIP_WDR_BASE + 0xE0) ++#define REG_VIP_WDR_70_H (REG_VIP_WDR_BASE + 0xE1) ++#define REG_VIP_WDR_71_L (REG_VIP_WDR_BASE + 0xE2) ++#define REG_VIP_WDR_71_H (REG_VIP_WDR_BASE + 0xE3) ++#define REG_VIP_WDR_72_L (REG_VIP_WDR_BASE + 0xE4) ++#define REG_VIP_WDR_72_H (REG_VIP_WDR_BASE + 0xE5) ++#define REG_VIP_WDR_73_L (REG_VIP_WDR_BASE + 0xE6) ++#define REG_VIP_WDR_73_H (REG_VIP_WDR_BASE + 0xE7) ++#define REG_VIP_WDR_74_L (REG_VIP_WDR_BASE + 0xE8) ++#define REG_VIP_WDR_74_H (REG_VIP_WDR_BASE + 0xE9) ++#define REG_VIP_WDR_75_L (REG_VIP_WDR_BASE + 0xEA) ++#define REG_VIP_WDR_75_H (REG_VIP_WDR_BASE + 0xEB) ++#define REG_VIP_WDR_76_L (REG_VIP_WDR_BASE + 0xEC) ++#define REG_VIP_WDR_76_H (REG_VIP_WDR_BASE + 0xED) ++#define REG_VIP_WDR_77_L (REG_VIP_WDR_BASE + 0xEE) ++#define REG_VIP_WDR_77_H (REG_VIP_WDR_BASE + 0xEF) ++#define REG_VIP_WDR_78_L (REG_VIP_WDR_BASE + 0xF0) ++#define REG_VIP_WDR_78_H (REG_VIP_WDR_BASE + 0xF1) ++#define REG_VIP_WDR_79_L (REG_VIP_WDR_BASE + 0xF2) ++#define REG_VIP_WDR_79_H (REG_VIP_WDR_BASE + 0xF3) ++#define REG_VIP_WDR_7A_L (REG_VIP_WDR_BASE + 0xF4) ++#define REG_VIP_WDR_7A_H (REG_VIP_WDR_BASE + 0xF5) ++#define REG_VIP_WDR_7B_L (REG_VIP_WDR_BASE + 0xF6) ++#define REG_VIP_WDR_7B_H (REG_VIP_WDR_BASE + 0xF7) ++#define REG_VIP_WDR_7C_L (REG_VIP_WDR_BASE + 0xF8) ++#define REG_VIP_WDR_7C_H (REG_VIP_WDR_BASE + 0xF9) ++#define REG_VIP_WDR_7D_L (REG_VIP_WDR_BASE + 0xFA) ++#define REG_VIP_WDR_7D_H (REG_VIP_WDR_BASE + 0xFB) ++#define REG_VIP_WDR_7E_L (REG_VIP_WDR_BASE + 0xFC) ++#define REG_VIP_WDR_7E_H (REG_VIP_WDR_BASE + 0xFD) ++#define REG_VIP_WDR_7F_L (REG_VIP_WDR_BASE + 0xFE) ++#define REG_VIP_WDR_7F_H (REG_VIP_WDR_BASE + 0xFF) ++ ++#define REG_VIP_YEE_00_L (REG_VIP_YEE_BASE + 0x00) ++#define REG_VIP_YEE_00_H (REG_VIP_YEE_BASE + 0x01) ++#define REG_VIP_YEE_01_L (REG_VIP_YEE_BASE + 0x02) ++#define REG_VIP_YEE_01_H (REG_VIP_YEE_BASE + 0x03) ++#define REG_VIP_YEE_02_L (REG_VIP_YEE_BASE + 0x04) ++#define REG_VIP_YEE_02_H (REG_VIP_YEE_BASE + 0x05) ++#define REG_VIP_YEE_03_L (REG_VIP_YEE_BASE + 0x06) ++#define REG_VIP_YEE_03_H (REG_VIP_YEE_BASE + 0x07) ++#define REG_VIP_YEE_04_L (REG_VIP_YEE_BASE + 0x08) ++#define REG_VIP_YEE_04_H (REG_VIP_YEE_BASE + 0x09) ++#define REG_VIP_YEE_05_L (REG_VIP_YEE_BASE + 0x0A) ++#define REG_VIP_YEE_05_H (REG_VIP_YEE_BASE + 0x0B) ++#define REG_VIP_YEE_06_L (REG_VIP_YEE_BASE + 0x0C) ++#define REG_VIP_YEE_06_H (REG_VIP_YEE_BASE + 0x0D) ++#define REG_VIP_YEE_07_L (REG_VIP_YEE_BASE + 0x0E) ++#define REG_VIP_YEE_07_H (REG_VIP_YEE_BASE + 0x0F) ++#define REG_VIP_YEE_08_L (REG_VIP_YEE_BASE + 0x10) ++#define REG_VIP_YEE_08_H (REG_VIP_YEE_BASE + 0x11) ++#define REG_VIP_YEE_09_L (REG_VIP_YEE_BASE + 0x12) ++#define REG_VIP_YEE_09_H (REG_VIP_YEE_BASE + 0x13) ++#define REG_VIP_YEE_0A_L (REG_VIP_YEE_BASE + 0x14) ++#define REG_VIP_YEE_0A_H (REG_VIP_YEE_BASE + 0x15) ++#define REG_VIP_YEE_0B_L (REG_VIP_YEE_BASE + 0x16) ++#define REG_VIP_YEE_0B_H (REG_VIP_YEE_BASE + 0x17) ++#define REG_VIP_YEE_0C_L (REG_VIP_YEE_BASE + 0x18) ++#define REG_VIP_YEE_0C_H (REG_VIP_YEE_BASE + 0x19) ++#define REG_VIP_YEE_0D_L (REG_VIP_YEE_BASE + 0x1A) ++#define REG_VIP_YEE_0D_H (REG_VIP_YEE_BASE + 0x1B) ++#define REG_VIP_YEE_0E_L (REG_VIP_YEE_BASE + 0x1C) ++#define REG_VIP_YEE_0E_H (REG_VIP_YEE_BASE + 0x1D) ++#define REG_VIP_YEE_0F_L (REG_VIP_YEE_BASE + 0x1E) ++#define REG_VIP_YEE_0F_H (REG_VIP_YEE_BASE + 0x1F) ++#define REG_VIP_YEE_10_L (REG_VIP_YEE_BASE + 0x20) ++#define REG_VIP_YEE_10_H (REG_VIP_YEE_BASE + 0x21) ++#define REG_VIP_YEE_11_L (REG_VIP_YEE_BASE + 0x22) ++#define REG_VIP_YEE_11_H (REG_VIP_YEE_BASE + 0x23) ++#define REG_VIP_YEE_12_L (REG_VIP_YEE_BASE + 0x24) ++#define REG_VIP_YEE_12_H (REG_VIP_YEE_BASE + 0x25) ++#define REG_VIP_YEE_13_L (REG_VIP_YEE_BASE + 0x26) ++#define REG_VIP_YEE_13_H (REG_VIP_YEE_BASE + 0x27) ++#define REG_VIP_YEE_14_L (REG_VIP_YEE_BASE + 0x28) ++#define REG_VIP_YEE_14_H (REG_VIP_YEE_BASE + 0x29) ++#define REG_VIP_YEE_15_L (REG_VIP_YEE_BASE + 0x2A) ++#define REG_VIP_YEE_15_H (REG_VIP_YEE_BASE + 0x2B) ++#define REG_VIP_YEE_16_L (REG_VIP_YEE_BASE + 0x2C) ++#define REG_VIP_YEE_16_H (REG_VIP_YEE_BASE + 0x2D) ++#define REG_VIP_YEE_17_L (REG_VIP_YEE_BASE + 0x2E) ++#define REG_VIP_YEE_17_H (REG_VIP_YEE_BASE + 0x2F) ++#define REG_VIP_YEE_18_L (REG_VIP_YEE_BASE + 0x30) ++#define REG_VIP_YEE_18_H (REG_VIP_YEE_BASE + 0x31) ++#define REG_VIP_YEE_19_L (REG_VIP_YEE_BASE + 0x32) ++#define REG_VIP_YEE_19_H (REG_VIP_YEE_BASE + 0x33) ++#define REG_VIP_YEE_1A_L (REG_VIP_YEE_BASE + 0x34) ++#define REG_VIP_YEE_1A_H (REG_VIP_YEE_BASE + 0x35) ++#define REG_VIP_YEE_1B_L (REG_VIP_YEE_BASE + 0x36) ++#define REG_VIP_YEE_1B_H (REG_VIP_YEE_BASE + 0x37) ++#define REG_VIP_YEE_1C_L (REG_VIP_YEE_BASE + 0x38) ++#define REG_VIP_YEE_1C_H (REG_VIP_YEE_BASE + 0x39) ++#define REG_VIP_YEE_1D_L (REG_VIP_YEE_BASE + 0x3A) ++#define REG_VIP_YEE_1D_H (REG_VIP_YEE_BASE + 0x3B) ++#define REG_VIP_YEE_1E_L (REG_VIP_YEE_BASE + 0x3C) ++#define REG_VIP_YEE_1E_H (REG_VIP_YEE_BASE + 0x3D) ++#define REG_VIP_YEE_1F_L (REG_VIP_YEE_BASE + 0x3E) ++#define REG_VIP_YEE_1F_H (REG_VIP_YEE_BASE + 0x3F) ++#define REG_VIP_YEE_20_L (REG_VIP_YEE_BASE + 0x40) ++#define REG_VIP_YEE_20_H (REG_VIP_YEE_BASE + 0x41) ++#define REG_VIP_YEE_21_L (REG_VIP_YEE_BASE + 0x42) ++#define REG_VIP_YEE_21_H (REG_VIP_YEE_BASE + 0x43) ++#define REG_VIP_YEE_22_L (REG_VIP_YEE_BASE + 0x44) ++#define REG_VIP_YEE_22_H (REG_VIP_YEE_BASE + 0x45) ++#define REG_VIP_YEE_23_L (REG_VIP_YEE_BASE + 0x46) ++#define REG_VIP_YEE_23_H (REG_VIP_YEE_BASE + 0x47) ++#define REG_VIP_YEE_24_L (REG_VIP_YEE_BASE + 0x48) ++#define REG_VIP_YEE_24_H (REG_VIP_YEE_BASE + 0x49) ++#define REG_VIP_YEE_25_L (REG_VIP_YEE_BASE + 0x4A) ++#define REG_VIP_YEE_25_H (REG_VIP_YEE_BASE + 0x4B) ++#define REG_VIP_YEE_26_L (REG_VIP_YEE_BASE + 0x4C) ++#define REG_VIP_YEE_26_H (REG_VIP_YEE_BASE + 0x4D) ++#define REG_VIP_YEE_27_L (REG_VIP_YEE_BASE + 0x4E) ++#define REG_VIP_YEE_27_H (REG_VIP_YEE_BASE + 0x4F) ++#define REG_VIP_YEE_28_L (REG_VIP_YEE_BASE + 0x50) ++#define REG_VIP_YEE_28_H (REG_VIP_YEE_BASE + 0x51) ++#define REG_VIP_YEE_29_L (REG_VIP_YEE_BASE + 0x52) ++#define REG_VIP_YEE_29_H (REG_VIP_YEE_BASE + 0x53) ++#define REG_VIP_YEE_2A_L (REG_VIP_YEE_BASE + 0x54) ++#define REG_VIP_YEE_2A_H (REG_VIP_YEE_BASE + 0x55) ++#define REG_VIP_YEE_2B_L (REG_VIP_YEE_BASE + 0x56) ++#define REG_VIP_YEE_2B_H (REG_VIP_YEE_BASE + 0x57) ++#define REG_VIP_YEE_2C_L (REG_VIP_YEE_BASE + 0x58) ++#define REG_VIP_YEE_2C_H (REG_VIP_YEE_BASE + 0x59) ++#define REG_VIP_YEE_2D_L (REG_VIP_YEE_BASE + 0x5A) ++#define REG_VIP_YEE_2D_H (REG_VIP_YEE_BASE + 0x5B) ++#define REG_VIP_YEE_2E_L (REG_VIP_YEE_BASE + 0x5C) ++#define REG_VIP_YEE_2E_H (REG_VIP_YEE_BASE + 0x5D) ++#define REG_VIP_YEE_2F_L (REG_VIP_YEE_BASE + 0x5E) ++#define REG_VIP_YEE_2F_H (REG_VIP_YEE_BASE + 0x5F) ++#define REG_VIP_YEE_30_L (REG_VIP_YEE_BASE + 0x60) ++#define REG_VIP_YEE_30_H (REG_VIP_YEE_BASE + 0x61) ++#define REG_VIP_YEE_31_L (REG_VIP_YEE_BASE + 0x62) ++#define REG_VIP_YEE_31_H (REG_VIP_YEE_BASE + 0x63) ++#define REG_VIP_YEE_32_L (REG_VIP_YEE_BASE + 0x64) ++#define REG_VIP_YEE_32_H (REG_VIP_YEE_BASE + 0x65) ++#define REG_VIP_YEE_33_L (REG_VIP_YEE_BASE + 0x66) ++#define REG_VIP_YEE_33_H (REG_VIP_YEE_BASE + 0x67) ++#define REG_VIP_YEE_34_L (REG_VIP_YEE_BASE + 0x68) ++#define REG_VIP_YEE_34_H (REG_VIP_YEE_BASE + 0x69) ++#define REG_VIP_YEE_35_L (REG_VIP_YEE_BASE + 0x6A) ++#define REG_VIP_YEE_35_H (REG_VIP_YEE_BASE + 0x6B) ++#define REG_VIP_YEE_36_L (REG_VIP_YEE_BASE + 0x6C) ++#define REG_VIP_YEE_36_H (REG_VIP_YEE_BASE + 0x6D) ++#define REG_VIP_YEE_37_L (REG_VIP_YEE_BASE + 0x6E) ++#define REG_VIP_YEE_37_H (REG_VIP_YEE_BASE + 0x6F) ++#define REG_VIP_YEE_38_L (REG_VIP_YEE_BASE + 0x70) ++#define REG_VIP_YEE_38_H (REG_VIP_YEE_BASE + 0x71) ++#define REG_VIP_YEE_39_L (REG_VIP_YEE_BASE + 0x72) ++#define REG_VIP_YEE_39_H (REG_VIP_YEE_BASE + 0x73) ++#define REG_VIP_YEE_3A_L (REG_VIP_YEE_BASE + 0x74) ++#define REG_VIP_YEE_3A_H (REG_VIP_YEE_BASE + 0x75) ++#define REG_VIP_YEE_3B_L (REG_VIP_YEE_BASE + 0x76) ++#define REG_VIP_YEE_3B_H (REG_VIP_YEE_BASE + 0x77) ++#define REG_VIP_YEE_3C_L (REG_VIP_YEE_BASE + 0x78) ++#define REG_VIP_YEE_3C_H (REG_VIP_YEE_BASE + 0x79) ++#define REG_VIP_YEE_3D_L (REG_VIP_YEE_BASE + 0x7A) ++#define REG_VIP_YEE_3D_H (REG_VIP_YEE_BASE + 0x7B) ++#define REG_VIP_YEE_3E_L (REG_VIP_YEE_BASE + 0x7C) ++#define REG_VIP_YEE_3E_H (REG_VIP_YEE_BASE + 0x7D) ++#define REG_VIP_YEE_3F_L (REG_VIP_YEE_BASE + 0x7E) ++#define REG_VIP_YEE_3F_H (REG_VIP_YEE_BASE + 0x7F) ++#define REG_VIP_YEE_40_L (REG_VIP_YEE_BASE + 0x80) ++#define REG_VIP_YEE_40_H (REG_VIP_YEE_BASE + 0x81) ++#define REG_VIP_YEE_41_L (REG_VIP_YEE_BASE + 0x82) ++#define REG_VIP_YEE_41_H (REG_VIP_YEE_BASE + 0x83) ++#define REG_VIP_YEE_42_L (REG_VIP_YEE_BASE + 0x84) ++#define REG_VIP_YEE_42_H (REG_VIP_YEE_BASE + 0x85) ++#define REG_VIP_YEE_43_L (REG_VIP_YEE_BASE + 0x86) ++#define REG_VIP_YEE_43_H (REG_VIP_YEE_BASE + 0x87) ++#define REG_VIP_YEE_44_L (REG_VIP_YEE_BASE + 0x88) ++#define REG_VIP_YEE_44_H (REG_VIP_YEE_BASE + 0x89) ++#define REG_VIP_YEE_45_L (REG_VIP_YEE_BASE + 0x8A) ++#define REG_VIP_YEE_45_H (REG_VIP_YEE_BASE + 0x8B) ++#define REG_VIP_YEE_46_L (REG_VIP_YEE_BASE + 0x8C) ++#define REG_VIP_YEE_46_H (REG_VIP_YEE_BASE + 0x8D) ++#define REG_VIP_YEE_47_L (REG_VIP_YEE_BASE + 0x8E) ++#define REG_VIP_YEE_47_H (REG_VIP_YEE_BASE + 0x8F) ++#define REG_VIP_YEE_48_L (REG_VIP_YEE_BASE + 0x90) ++#define REG_VIP_YEE_48_H (REG_VIP_YEE_BASE + 0x91) ++#define REG_VIP_YEE_49_L (REG_VIP_YEE_BASE + 0x92) ++#define REG_VIP_YEE_49_H (REG_VIP_YEE_BASE + 0x93) ++#define REG_VIP_YEE_4A_L (REG_VIP_YEE_BASE + 0x94) ++#define REG_VIP_YEE_4A_H (REG_VIP_YEE_BASE + 0x95) ++#define REG_VIP_YEE_4B_L (REG_VIP_YEE_BASE + 0x96) ++#define REG_VIP_YEE_4B_H (REG_VIP_YEE_BASE + 0x97) ++#define REG_VIP_YEE_4C_L (REG_VIP_YEE_BASE + 0x98) ++#define REG_VIP_YEE_4C_H (REG_VIP_YEE_BASE + 0x99) ++#define REG_VIP_YEE_4D_L (REG_VIP_YEE_BASE + 0x9A) ++#define REG_VIP_YEE_4D_H (REG_VIP_YEE_BASE + 0x9B) ++#define REG_VIP_YEE_4E_L (REG_VIP_YEE_BASE + 0x9C) ++#define REG_VIP_YEE_4E_H (REG_VIP_YEE_BASE + 0x9D) ++#define REG_VIP_YEE_4F_L (REG_VIP_YEE_BASE + 0x9E) ++#define REG_VIP_YEE_4F_H (REG_VIP_YEE_BASE + 0x9F) ++#define REG_VIP_YEE_50_L (REG_VIP_YEE_BASE + 0xA0) ++#define REG_VIP_YEE_50_H (REG_VIP_YEE_BASE + 0xA1) ++#define REG_VIP_YEE_51_L (REG_VIP_YEE_BASE + 0xA2) ++#define REG_VIP_YEE_51_H (REG_VIP_YEE_BASE + 0xA3) ++#define REG_VIP_YEE_52_L (REG_VIP_YEE_BASE + 0xA4) ++#define REG_VIP_YEE_52_H (REG_VIP_YEE_BASE + 0xA5) ++#define REG_VIP_YEE_53_L (REG_VIP_YEE_BASE + 0xA6) ++#define REG_VIP_YEE_53_H (REG_VIP_YEE_BASE + 0xA7) ++#define REG_VIP_YEE_54_L (REG_VIP_YEE_BASE + 0xA8) ++#define REG_VIP_YEE_54_H (REG_VIP_YEE_BASE + 0xA9) ++#define REG_VIP_YEE_55_L (REG_VIP_YEE_BASE + 0xAA) ++#define REG_VIP_YEE_55_H (REG_VIP_YEE_BASE + 0xAB) ++#define REG_VIP_YEE_56_L (REG_VIP_YEE_BASE + 0xAC) ++#define REG_VIP_YEE_56_H (REG_VIP_YEE_BASE + 0xAD) ++#define REG_VIP_YEE_57_L (REG_VIP_YEE_BASE + 0xAE) ++#define REG_VIP_YEE_57_H (REG_VIP_YEE_BASE + 0xAF) ++#define REG_VIP_YEE_58_L (REG_VIP_YEE_BASE + 0xB0) ++#define REG_VIP_YEE_58_H (REG_VIP_YEE_BASE + 0xB1) ++#define REG_VIP_YEE_59_L (REG_VIP_YEE_BASE + 0xB2) ++#define REG_VIP_YEE_59_H (REG_VIP_YEE_BASE + 0xB3) ++#define REG_VIP_YEE_5A_L (REG_VIP_YEE_BASE + 0xB4) ++#define REG_VIP_YEE_5A_H (REG_VIP_YEE_BASE + 0xB5) ++#define REG_VIP_YEE_5B_L (REG_VIP_YEE_BASE + 0xB6) ++#define REG_VIP_YEE_5B_H (REG_VIP_YEE_BASE + 0xB7) ++#define REG_VIP_YEE_5C_L (REG_VIP_YEE_BASE + 0xB8) ++#define REG_VIP_YEE_5C_H (REG_VIP_YEE_BASE + 0xB9) ++#define REG_VIP_YEE_5D_L (REG_VIP_YEE_BASE + 0xBA) ++#define REG_VIP_YEE_5D_H (REG_VIP_YEE_BASE + 0xBB) ++#define REG_VIP_YEE_5E_L (REG_VIP_YEE_BASE + 0xBC) ++#define REG_VIP_YEE_5E_H (REG_VIP_YEE_BASE + 0xBD) ++#define REG_VIP_YEE_5F_L (REG_VIP_YEE_BASE + 0xBE) ++#define REG_VIP_YEE_5F_H (REG_VIP_YEE_BASE + 0xBF) ++#define REG_VIP_YEE_60_L (REG_VIP_YEE_BASE + 0xC0) ++#define REG_VIP_YEE_60_H (REG_VIP_YEE_BASE + 0xC1) ++#define REG_VIP_YEE_61_L (REG_VIP_YEE_BASE + 0xC2) ++#define REG_VIP_YEE_61_H (REG_VIP_YEE_BASE + 0xC3) ++#define REG_VIP_YEE_62_L (REG_VIP_YEE_BASE + 0xC4) ++#define REG_VIP_YEE_62_H (REG_VIP_YEE_BASE + 0xC5) ++#define REG_VIP_YEE_63_L (REG_VIP_YEE_BASE + 0xC6) ++#define REG_VIP_YEE_63_H (REG_VIP_YEE_BASE + 0xC7) ++#define REG_VIP_YEE_64_L (REG_VIP_YEE_BASE + 0xC8) ++#define REG_VIP_YEE_64_H (REG_VIP_YEE_BASE + 0xC9) ++#define REG_VIP_YEE_65_L (REG_VIP_YEE_BASE + 0xCA) ++#define REG_VIP_YEE_65_H (REG_VIP_YEE_BASE + 0xCB) ++#define REG_VIP_YEE_66_L (REG_VIP_YEE_BASE + 0xCC) ++#define REG_VIP_YEE_66_H (REG_VIP_YEE_BASE + 0xCD) ++#define REG_VIP_YEE_67_L (REG_VIP_YEE_BASE + 0xCE) ++#define REG_VIP_YEE_67_H (REG_VIP_YEE_BASE + 0xCF) ++#define REG_VIP_YEE_68_L (REG_VIP_YEE_BASE + 0xD0) ++#define REG_VIP_YEE_68_H (REG_VIP_YEE_BASE + 0xD1) ++#define REG_VIP_YEE_69_L (REG_VIP_YEE_BASE + 0xD2) ++#define REG_VIP_YEE_69_H (REG_VIP_YEE_BASE + 0xD3) ++#define REG_VIP_YEE_6A_L (REG_VIP_YEE_BASE + 0xD4) ++#define REG_VIP_YEE_6A_H (REG_VIP_YEE_BASE + 0xD5) ++#define REG_VIP_YEE_6B_L (REG_VIP_YEE_BASE + 0xD6) ++#define REG_VIP_YEE_6B_H (REG_VIP_YEE_BASE + 0xD7) ++#define REG_VIP_YEE_6C_L (REG_VIP_YEE_BASE + 0xD8) ++#define REG_VIP_YEE_6C_H (REG_VIP_YEE_BASE + 0xD9) ++#define REG_VIP_YEE_6D_L (REG_VIP_YEE_BASE + 0xDA) ++#define REG_VIP_YEE_6D_H (REG_VIP_YEE_BASE + 0xDB) ++#define REG_VIP_YEE_6E_L (REG_VIP_YEE_BASE + 0xDC) ++#define REG_VIP_YEE_6E_H (REG_VIP_YEE_BASE + 0xDD) ++#define REG_VIP_YEE_6F_L (REG_VIP_YEE_BASE + 0xDE) ++#define REG_VIP_YEE_6F_H (REG_VIP_YEE_BASE + 0xDF) ++#define REG_VIP_YEE_70_L (REG_VIP_YEE_BASE + 0xE0) ++#define REG_VIP_YEE_70_H (REG_VIP_YEE_BASE + 0xE1) ++#define REG_VIP_YEE_71_L (REG_VIP_YEE_BASE + 0xE2) ++#define REG_VIP_YEE_71_H (REG_VIP_YEE_BASE + 0xE3) ++#define REG_VIP_YEE_72_L (REG_VIP_YEE_BASE + 0xE4) ++#define REG_VIP_YEE_72_H (REG_VIP_YEE_BASE + 0xE5) ++#define REG_VIP_YEE_73_L (REG_VIP_YEE_BASE + 0xE6) ++#define REG_VIP_YEE_73_H (REG_VIP_YEE_BASE + 0xE7) ++#define REG_VIP_YEE_74_L (REG_VIP_YEE_BASE + 0xE8) ++#define REG_VIP_YEE_74_H (REG_VIP_YEE_BASE + 0xE9) ++#define REG_VIP_YEE_75_L (REG_VIP_YEE_BASE + 0xEA) ++#define REG_VIP_YEE_75_H (REG_VIP_YEE_BASE + 0xEB) ++#define REG_VIP_YEE_76_L (REG_VIP_YEE_BASE + 0xEC) ++#define REG_VIP_YEE_76_H (REG_VIP_YEE_BASE + 0xED) ++#define REG_VIP_YEE_77_L (REG_VIP_YEE_BASE + 0xEE) ++#define REG_VIP_YEE_77_H (REG_VIP_YEE_BASE + 0xEF) ++#define REG_VIP_YEE_78_L (REG_VIP_YEE_BASE + 0xF0) ++#define REG_VIP_YEE_78_H (REG_VIP_YEE_BASE + 0xF1) ++#define REG_VIP_YEE_79_L (REG_VIP_YEE_BASE + 0xF2) ++#define REG_VIP_YEE_79_H (REG_VIP_YEE_BASE + 0xF3) ++#define REG_VIP_YEE_7A_L (REG_VIP_YEE_BASE + 0xF4) ++#define REG_VIP_YEE_7A_H (REG_VIP_YEE_BASE + 0xF5) ++#define REG_VIP_YEE_7B_L (REG_VIP_YEE_BASE + 0xF6) ++#define REG_VIP_YEE_7B_H (REG_VIP_YEE_BASE + 0xF7) ++#define REG_VIP_YEE_7C_L (REG_VIP_YEE_BASE + 0xF8) ++#define REG_VIP_YEE_7C_H (REG_VIP_YEE_BASE + 0xF9) ++#define REG_VIP_YEE_7D_L (REG_VIP_YEE_BASE + 0xFA) ++#define REG_VIP_YEE_7D_H (REG_VIP_YEE_BASE + 0xFB) ++#define REG_VIP_YEE_7E_L (REG_VIP_YEE_BASE + 0xFC) ++#define REG_VIP_YEE_7E_H (REG_VIP_YEE_BASE + 0xFD) ++#define REG_VIP_YEE_7F_L (REG_VIP_YEE_BASE + 0xFE) ++#define REG_VIP_YEE_7F_H (REG_VIP_YEE_BASE + 0xFF) ++ ++ ++#define REG_VIP_MCNR_00_L (REG_VIP_MCNR_BASE + 0x00) ++#define REG_VIP_MCNR_00_H (REG_VIP_MCNR_BASE + 0x01) ++#define REG_VIP_MCNR_01_L (REG_VIP_MCNR_BASE + 0x02) ++#define REG_VIP_MCNR_01_H (REG_VIP_MCNR_BASE + 0x03) ++#define REG_VIP_MCNR_02_L (REG_VIP_MCNR_BASE + 0x04) ++#define REG_VIP_MCNR_02_H (REG_VIP_MCNR_BASE + 0x05) ++#define REG_VIP_MCNR_03_L (REG_VIP_MCNR_BASE + 0x06) ++#define REG_VIP_MCNR_03_H (REG_VIP_MCNR_BASE + 0x07) ++#define REG_VIP_MCNR_04_L (REG_VIP_MCNR_BASE + 0x08) ++#define REG_VIP_MCNR_04_H (REG_VIP_MCNR_BASE + 0x09) ++#define REG_VIP_MCNR_05_L (REG_VIP_MCNR_BASE + 0x0A) ++#define REG_VIP_MCNR_05_H (REG_VIP_MCNR_BASE + 0x0B) ++#define REG_VIP_MCNR_06_L (REG_VIP_MCNR_BASE + 0x0C) ++#define REG_VIP_MCNR_06_H (REG_VIP_MCNR_BASE + 0x0D) ++#define REG_VIP_MCNR_07_L (REG_VIP_MCNR_BASE + 0x0E) ++#define REG_VIP_MCNR_07_H (REG_VIP_MCNR_BASE + 0x0F) ++#define REG_VIP_MCNR_08_L (REG_VIP_MCNR_BASE + 0x10) ++#define REG_VIP_MCNR_08_H (REG_VIP_MCNR_BASE + 0x11) ++#define REG_VIP_MCNR_09_L (REG_VIP_MCNR_BASE + 0x12) ++#define REG_VIP_MCNR_09_H (REG_VIP_MCNR_BASE + 0x13) ++#define REG_VIP_MCNR_0A_L (REG_VIP_MCNR_BASE + 0x14) ++#define REG_VIP_MCNR_0A_H (REG_VIP_MCNR_BASE + 0x15) ++#define REG_VIP_MCNR_0B_L (REG_VIP_MCNR_BASE + 0x16) ++#define REG_VIP_MCNR_0B_H (REG_VIP_MCNR_BASE + 0x17) ++#define REG_VIP_MCNR_0C_L (REG_VIP_MCNR_BASE + 0x18) ++#define REG_VIP_MCNR_0C_H (REG_VIP_MCNR_BASE + 0x19) ++#define REG_VIP_MCNR_0D_L (REG_VIP_MCNR_BASE + 0x1A) ++#define REG_VIP_MCNR_0D_H (REG_VIP_MCNR_BASE + 0x1B) ++#define REG_VIP_MCNR_0E_L (REG_VIP_MCNR_BASE + 0x1C) ++#define REG_VIP_MCNR_0E_H (REG_VIP_MCNR_BASE + 0x1D) ++#define REG_VIP_MCNR_0F_L (REG_VIP_MCNR_BASE + 0x1E) ++#define REG_VIP_MCNR_0F_H (REG_VIP_MCNR_BASE + 0x1F) ++#define REG_VIP_MCNR_10_L (REG_VIP_MCNR_BASE + 0x20) ++#define REG_VIP_MCNR_10_H (REG_VIP_MCNR_BASE + 0x21) ++#define REG_VIP_MCNR_11_L (REG_VIP_MCNR_BASE + 0x22) ++#define REG_VIP_MCNR_11_H (REG_VIP_MCNR_BASE + 0x23) ++#define REG_VIP_MCNR_12_L (REG_VIP_MCNR_BASE + 0x24) ++#define REG_VIP_MCNR_12_H (REG_VIP_MCNR_BASE + 0x25) ++#define REG_VIP_MCNR_13_L (REG_VIP_MCNR_BASE + 0x26) ++#define REG_VIP_MCNR_13_H (REG_VIP_MCNR_BASE + 0x27) ++#define REG_VIP_MCNR_14_L (REG_VIP_MCNR_BASE + 0x28) ++#define REG_VIP_MCNR_14_H (REG_VIP_MCNR_BASE + 0x29) ++#define REG_VIP_MCNR_15_L (REG_VIP_MCNR_BASE + 0x2A) ++#define REG_VIP_MCNR_15_H (REG_VIP_MCNR_BASE + 0x2B) ++#define REG_VIP_MCNR_16_L (REG_VIP_MCNR_BASE + 0x2C) ++#define REG_VIP_MCNR_16_H (REG_VIP_MCNR_BASE + 0x2D) ++#define REG_VIP_MCNR_17_L (REG_VIP_MCNR_BASE + 0x2E) ++#define REG_VIP_MCNR_17_H (REG_VIP_MCNR_BASE + 0x2F) ++#define REG_VIP_MCNR_18_L (REG_VIP_MCNR_BASE + 0x30) ++#define REG_VIP_MCNR_18_H (REG_VIP_MCNR_BASE + 0x31) ++#define REG_VIP_MCNR_19_L (REG_VIP_MCNR_BASE + 0x32) ++#define REG_VIP_MCNR_19_H (REG_VIP_MCNR_BASE + 0x33) ++#define REG_VIP_MCNR_1A_L (REG_VIP_MCNR_BASE + 0x34) ++#define REG_VIP_MCNR_1A_H (REG_VIP_MCNR_BASE + 0x35) ++#define REG_VIP_MCNR_1B_L (REG_VIP_MCNR_BASE + 0x36) ++#define REG_VIP_MCNR_1B_H (REG_VIP_MCNR_BASE + 0x37) ++#define REG_VIP_MCNR_1C_L (REG_VIP_MCNR_BASE + 0x38) ++#define REG_VIP_MCNR_1C_H (REG_VIP_MCNR_BASE + 0x39) ++#define REG_VIP_MCNR_1D_L (REG_VIP_MCNR_BASE + 0x3A) ++#define REG_VIP_MCNR_1D_H (REG_VIP_MCNR_BASE + 0x3B) ++#define REG_VIP_MCNR_1E_L (REG_VIP_MCNR_BASE + 0x3C) ++#define REG_VIP_MCNR_1E_H (REG_VIP_MCNR_BASE + 0x3D) ++#define REG_VIP_MCNR_1F_L (REG_VIP_MCNR_BASE + 0x3E) ++#define REG_VIP_MCNR_1F_H (REG_VIP_MCNR_BASE + 0x3F) ++#define REG_VIP_MCNR_20_L (REG_VIP_MCNR_BASE + 0x40) ++#define REG_VIP_MCNR_20_H (REG_VIP_MCNR_BASE + 0x41) ++#define REG_VIP_MCNR_21_L (REG_VIP_MCNR_BASE + 0x42) ++#define REG_VIP_MCNR_21_H (REG_VIP_MCNR_BASE + 0x43) ++#define REG_VIP_MCNR_22_L (REG_VIP_MCNR_BASE + 0x44) ++#define REG_VIP_MCNR_22_H (REG_VIP_MCNR_BASE + 0x45) ++#define REG_VIP_MCNR_23_L (REG_VIP_MCNR_BASE + 0x46) ++#define REG_VIP_MCNR_23_H (REG_VIP_MCNR_BASE + 0x47) ++#define REG_VIP_MCNR_24_L (REG_VIP_MCNR_BASE + 0x48) ++#define REG_VIP_MCNR_24_H (REG_VIP_MCNR_BASE + 0x49) ++#define REG_VIP_MCNR_25_L (REG_VIP_MCNR_BASE + 0x4A) ++#define REG_VIP_MCNR_25_H (REG_VIP_MCNR_BASE + 0x4B) ++#define REG_VIP_MCNR_26_L (REG_VIP_MCNR_BASE + 0x4C) ++#define REG_VIP_MCNR_26_H (REG_VIP_MCNR_BASE + 0x4D) ++#define REG_VIP_MCNR_27_L (REG_VIP_MCNR_BASE + 0x4E) ++#define REG_VIP_MCNR_27_H (REG_VIP_MCNR_BASE + 0x4F) ++#define REG_VIP_MCNR_28_L (REG_VIP_MCNR_BASE + 0x50) ++#define REG_VIP_MCNR_28_H (REG_VIP_MCNR_BASE + 0x51) ++#define REG_VIP_MCNR_29_L (REG_VIP_MCNR_BASE + 0x52) ++#define REG_VIP_MCNR_29_H (REG_VIP_MCNR_BASE + 0x53) ++#define REG_VIP_MCNR_2A_L (REG_VIP_MCNR_BASE + 0x54) ++#define REG_VIP_MCNR_2A_H (REG_VIP_MCNR_BASE + 0x55) ++#define REG_VIP_MCNR_2B_L (REG_VIP_MCNR_BASE + 0x56) ++#define REG_VIP_MCNR_2B_H (REG_VIP_MCNR_BASE + 0x57) ++#define REG_VIP_MCNR_2C_L (REG_VIP_MCNR_BASE + 0x58) ++#define REG_VIP_MCNR_2C_H (REG_VIP_MCNR_BASE + 0x59) ++#define REG_VIP_MCNR_2D_L (REG_VIP_MCNR_BASE + 0x5A) ++#define REG_VIP_MCNR_2D_H (REG_VIP_MCNR_BASE + 0x5B) ++#define REG_VIP_MCNR_2E_L (REG_VIP_MCNR_BASE + 0x5C) ++#define REG_VIP_MCNR_2E_H (REG_VIP_MCNR_BASE + 0x5D) ++#define REG_VIP_MCNR_2F_L (REG_VIP_MCNR_BASE + 0x5E) ++#define REG_VIP_MCNR_2F_H (REG_VIP_MCNR_BASE + 0x5F) ++#define REG_VIP_MCNR_30_L (REG_VIP_MCNR_BASE + 0x60) ++#define REG_VIP_MCNR_30_H (REG_VIP_MCNR_BASE + 0x61) ++#define REG_VIP_MCNR_31_L (REG_VIP_MCNR_BASE + 0x62) ++#define REG_VIP_MCNR_31_H (REG_VIP_MCNR_BASE + 0x63) ++#define REG_VIP_MCNR_32_L (REG_VIP_MCNR_BASE + 0x64) ++#define REG_VIP_MCNR_32_H (REG_VIP_MCNR_BASE + 0x65) ++#define REG_VIP_MCNR_33_L (REG_VIP_MCNR_BASE + 0x66) ++#define REG_VIP_MCNR_33_H (REG_VIP_MCNR_BASE + 0x67) ++#define REG_VIP_MCNR_34_L (REG_VIP_MCNR_BASE + 0x68) ++#define REG_VIP_MCNR_34_H (REG_VIP_MCNR_BASE + 0x69) ++#define REG_VIP_MCNR_35_L (REG_VIP_MCNR_BASE + 0x6A) ++#define REG_VIP_MCNR_35_H (REG_VIP_MCNR_BASE + 0x6B) ++#define REG_VIP_MCNR_36_L (REG_VIP_MCNR_BASE + 0x6C) ++#define REG_VIP_MCNR_36_H (REG_VIP_MCNR_BASE + 0x6D) ++#define REG_VIP_MCNR_37_L (REG_VIP_MCNR_BASE + 0x6E) ++#define REG_VIP_MCNR_37_H (REG_VIP_MCNR_BASE + 0x6F) ++#define REG_VIP_MCNR_38_L (REG_VIP_MCNR_BASE + 0x70) ++#define REG_VIP_MCNR_38_H (REG_VIP_MCNR_BASE + 0x71) ++#define REG_VIP_MCNR_39_L (REG_VIP_MCNR_BASE + 0x72) ++#define REG_VIP_MCNR_39_H (REG_VIP_MCNR_BASE + 0x73) ++#define REG_VIP_MCNR_3A_L (REG_VIP_MCNR_BASE + 0x74) ++#define REG_VIP_MCNR_3A_H (REG_VIP_MCNR_BASE + 0x75) ++#define REG_VIP_MCNR_3B_L (REG_VIP_MCNR_BASE + 0x76) ++#define REG_VIP_MCNR_3B_H (REG_VIP_MCNR_BASE + 0x77) ++#define REG_VIP_MCNR_3C_L (REG_VIP_MCNR_BASE + 0x78) ++#define REG_VIP_MCNR_3C_H (REG_VIP_MCNR_BASE + 0x79) ++#define REG_VIP_MCNR_3D_L (REG_VIP_MCNR_BASE + 0x7A) ++#define REG_VIP_MCNR_3D_H (REG_VIP_MCNR_BASE + 0x7B) ++#define REG_VIP_MCNR_3E_L (REG_VIP_MCNR_BASE + 0x7C) ++#define REG_VIP_MCNR_3E_H (REG_VIP_MCNR_BASE + 0x7D) ++#define REG_VIP_MCNR_3F_L (REG_VIP_MCNR_BASE + 0x7E) ++#define REG_VIP_MCNR_3F_H (REG_VIP_MCNR_BASE + 0x7F) ++#define REG_VIP_MCNR_40_L (REG_VIP_MCNR_BASE + 0x80) ++#define REG_VIP_MCNR_40_H (REG_VIP_MCNR_BASE + 0x81) ++#define REG_VIP_MCNR_41_L (REG_VIP_MCNR_BASE + 0x82) ++#define REG_VIP_MCNR_41_H (REG_VIP_MCNR_BASE + 0x83) ++#define REG_VIP_MCNR_42_L (REG_VIP_MCNR_BASE + 0x84) ++#define REG_VIP_MCNR_42_H (REG_VIP_MCNR_BASE + 0x85) ++#define REG_VIP_MCNR_43_L (REG_VIP_MCNR_BASE + 0x86) ++#define REG_VIP_MCNR_43_H (REG_VIP_MCNR_BASE + 0x87) ++#define REG_VIP_MCNR_44_L (REG_VIP_MCNR_BASE + 0x88) ++#define REG_VIP_MCNR_44_H (REG_VIP_MCNR_BASE + 0x89) ++#define REG_VIP_MCNR_45_L (REG_VIP_MCNR_BASE + 0x8A) ++#define REG_VIP_MCNR_45_H (REG_VIP_MCNR_BASE + 0x8B) ++#define REG_VIP_MCNR_46_L (REG_VIP_MCNR_BASE + 0x8C) ++#define REG_VIP_MCNR_46_H (REG_VIP_MCNR_BASE + 0x8D) ++#define REG_VIP_MCNR_47_L (REG_VIP_MCNR_BASE + 0x8E) ++#define REG_VIP_MCNR_47_H (REG_VIP_MCNR_BASE + 0x8F) ++#define REG_VIP_MCNR_48_L (REG_VIP_MCNR_BASE + 0x90) ++#define REG_VIP_MCNR_48_H (REG_VIP_MCNR_BASE + 0x91) ++#define REG_VIP_MCNR_49_L (REG_VIP_MCNR_BASE + 0x92) ++#define REG_VIP_MCNR_49_H (REG_VIP_MCNR_BASE + 0x93) ++#define REG_VIP_MCNR_4A_L (REG_VIP_MCNR_BASE + 0x94) ++#define REG_VIP_MCNR_4A_H (REG_VIP_MCNR_BASE + 0x95) ++#define REG_VIP_MCNR_4B_L (REG_VIP_MCNR_BASE + 0x96) ++#define REG_VIP_MCNR_4B_H (REG_VIP_MCNR_BASE + 0x97) ++#define REG_VIP_MCNR_4C_L (REG_VIP_MCNR_BASE + 0x98) ++#define REG_VIP_MCNR_4C_H (REG_VIP_MCNR_BASE + 0x99) ++#define REG_VIP_MCNR_4D_L (REG_VIP_MCNR_BASE + 0x9A) ++#define REG_VIP_MCNR_4D_H (REG_VIP_MCNR_BASE + 0x9B) ++#define REG_VIP_MCNR_4E_L (REG_VIP_MCNR_BASE + 0x9C) ++#define REG_VIP_MCNR_4E_H (REG_VIP_MCNR_BASE + 0x9D) ++#define REG_VIP_MCNR_4F_L (REG_VIP_MCNR_BASE + 0x9E) ++#define REG_VIP_MCNR_4F_H (REG_VIP_MCNR_BASE + 0x9F) ++#define REG_VIP_MCNR_50_L (REG_VIP_MCNR_BASE + 0xA0) ++#define REG_VIP_MCNR_50_H (REG_VIP_MCNR_BASE + 0xA1) ++#define REG_VIP_MCNR_51_L (REG_VIP_MCNR_BASE + 0xA2) ++#define REG_VIP_MCNR_51_H (REG_VIP_MCNR_BASE + 0xA3) ++#define REG_VIP_MCNR_52_L (REG_VIP_MCNR_BASE + 0xA4) ++#define REG_VIP_MCNR_52_H (REG_VIP_MCNR_BASE + 0xA5) ++#define REG_VIP_MCNR_53_L (REG_VIP_MCNR_BASE + 0xA6) ++#define REG_VIP_MCNR_53_H (REG_VIP_MCNR_BASE + 0xA7) ++#define REG_VIP_MCNR_54_L (REG_VIP_MCNR_BASE + 0xA8) ++#define REG_VIP_MCNR_54_H (REG_VIP_MCNR_BASE + 0xA9) ++#define REG_VIP_MCNR_55_L (REG_VIP_MCNR_BASE + 0xAA) ++#define REG_VIP_MCNR_55_H (REG_VIP_MCNR_BASE + 0xAB) ++#define REG_VIP_MCNR_56_L (REG_VIP_MCNR_BASE + 0xAC) ++#define REG_VIP_MCNR_56_H (REG_VIP_MCNR_BASE + 0xAD) ++#define REG_VIP_MCNR_57_L (REG_VIP_MCNR_BASE + 0xAE) ++#define REG_VIP_MCNR_57_H (REG_VIP_MCNR_BASE + 0xAF) ++#define REG_VIP_MCNR_58_L (REG_VIP_MCNR_BASE + 0xB0) ++#define REG_VIP_MCNR_58_H (REG_VIP_MCNR_BASE + 0xB1) ++#define REG_VIP_MCNR_59_L (REG_VIP_MCNR_BASE + 0xB2) ++#define REG_VIP_MCNR_59_H (REG_VIP_MCNR_BASE + 0xB3) ++#define REG_VIP_MCNR_5A_L (REG_VIP_MCNR_BASE + 0xB4) ++#define REG_VIP_MCNR_5A_H (REG_VIP_MCNR_BASE + 0xB5) ++#define REG_VIP_MCNR_5B_L (REG_VIP_MCNR_BASE + 0xB6) ++#define REG_VIP_MCNR_5B_H (REG_VIP_MCNR_BASE + 0xB7) ++#define REG_VIP_MCNR_5C_L (REG_VIP_MCNR_BASE + 0xB8) ++#define REG_VIP_MCNR_5C_H (REG_VIP_MCNR_BASE + 0xB9) ++#define REG_VIP_MCNR_5D_L (REG_VIP_MCNR_BASE + 0xBA) ++#define REG_VIP_MCNR_5D_H (REG_VIP_MCNR_BASE + 0xBB) ++#define REG_VIP_MCNR_5E_L (REG_VIP_MCNR_BASE + 0xBC) ++#define REG_VIP_MCNR_5E_H (REG_VIP_MCNR_BASE + 0xBD) ++#define REG_VIP_MCNR_5F_L (REG_VIP_MCNR_BASE + 0xBE) ++#define REG_VIP_MCNR_5F_H (REG_VIP_MCNR_BASE + 0xBF) ++#define REG_VIP_MCNR_60_L (REG_VIP_MCNR_BASE + 0xC0) ++#define REG_VIP_MCNR_60_H (REG_VIP_MCNR_BASE + 0xC1) ++#define REG_VIP_MCNR_61_L (REG_VIP_MCNR_BASE + 0xC2) ++#define REG_VIP_MCNR_61_H (REG_VIP_MCNR_BASE + 0xC3) ++#define REG_VIP_MCNR_62_L (REG_VIP_MCNR_BASE + 0xC4) ++#define REG_VIP_MCNR_62_H (REG_VIP_MCNR_BASE + 0xC5) ++#define REG_VIP_MCNR_63_L (REG_VIP_MCNR_BASE + 0xC6) ++#define REG_VIP_MCNR_63_H (REG_VIP_MCNR_BASE + 0xC7) ++#define REG_VIP_MCNR_64_L (REG_VIP_MCNR_BASE + 0xC8) ++#define REG_VIP_MCNR_64_H (REG_VIP_MCNR_BASE + 0xC9) ++#define REG_VIP_MCNR_65_L (REG_VIP_MCNR_BASE + 0xCA) ++#define REG_VIP_MCNR_65_H (REG_VIP_MCNR_BASE + 0xCB) ++#define REG_VIP_MCNR_66_L (REG_VIP_MCNR_BASE + 0xCC) ++#define REG_VIP_MCNR_66_H (REG_VIP_MCNR_BASE + 0xCD) ++#define REG_VIP_MCNR_67_L (REG_VIP_MCNR_BASE + 0xCE) ++#define REG_VIP_MCNR_67_H (REG_VIP_MCNR_BASE + 0xCF) ++#define REG_VIP_MCNR_68_L (REG_VIP_MCNR_BASE + 0xD0) ++#define REG_VIP_MCNR_68_H (REG_VIP_MCNR_BASE + 0xD1) ++#define REG_VIP_MCNR_69_L (REG_VIP_MCNR_BASE + 0xD2) ++#define REG_VIP_MCNR_69_H (REG_VIP_MCNR_BASE + 0xD3) ++#define REG_VIP_MCNR_6A_L (REG_VIP_MCNR_BASE + 0xD4) ++#define REG_VIP_MCNR_6A_H (REG_VIP_MCNR_BASE + 0xD5) ++#define REG_VIP_MCNR_6B_L (REG_VIP_MCNR_BASE + 0xD6) ++#define REG_VIP_MCNR_6B_H (REG_VIP_MCNR_BASE + 0xD7) ++#define REG_VIP_MCNR_6C_L (REG_VIP_MCNR_BASE + 0xD8) ++#define REG_VIP_MCNR_6C_H (REG_VIP_MCNR_BASE + 0xD9) ++#define REG_VIP_MCNR_6D_L (REG_VIP_MCNR_BASE + 0xDA) ++#define REG_VIP_MCNR_6D_H (REG_VIP_MCNR_BASE + 0xDB) ++#define REG_VIP_MCNR_6E_L (REG_VIP_MCNR_BASE + 0xDC) ++#define REG_VIP_MCNR_6E_H (REG_VIP_MCNR_BASE + 0xDD) ++#define REG_VIP_MCNR_6F_L (REG_VIP_MCNR_BASE + 0xDE) ++#define REG_VIP_MCNR_6F_H (REG_VIP_MCNR_BASE + 0xDF) ++#define REG_VIP_MCNR_70_L (REG_VIP_MCNR_BASE + 0xE0) ++#define REG_VIP_MCNR_70_H (REG_VIP_MCNR_BASE + 0xE1) ++#define REG_VIP_MCNR_71_L (REG_VIP_MCNR_BASE + 0xE2) ++#define REG_VIP_MCNR_71_H (REG_VIP_MCNR_BASE + 0xE3) ++#define REG_VIP_MCNR_72_L (REG_VIP_MCNR_BASE + 0xE4) ++#define REG_VIP_MCNR_72_H (REG_VIP_MCNR_BASE + 0xE5) ++#define REG_VIP_MCNR_73_L (REG_VIP_MCNR_BASE + 0xE6) ++#define REG_VIP_MCNR_73_H (REG_VIP_MCNR_BASE + 0xE7) ++#define REG_VIP_MCNR_74_L (REG_VIP_MCNR_BASE + 0xE8) ++#define REG_VIP_MCNR_74_H (REG_VIP_MCNR_BASE + 0xE9) ++#define REG_VIP_MCNR_75_L (REG_VIP_MCNR_BASE + 0xEA) ++#define REG_VIP_MCNR_75_H (REG_VIP_MCNR_BASE + 0xEB) ++#define REG_VIP_MCNR_76_L (REG_VIP_MCNR_BASE + 0xEC) ++#define REG_VIP_MCNR_76_H (REG_VIP_MCNR_BASE + 0xED) ++#define REG_VIP_MCNR_77_L (REG_VIP_MCNR_BASE + 0xEE) ++#define REG_VIP_MCNR_77_H (REG_VIP_MCNR_BASE + 0xEF) ++#define REG_VIP_MCNR_78_L (REG_VIP_MCNR_BASE + 0xF0) ++#define REG_VIP_MCNR_78_H (REG_VIP_MCNR_BASE + 0xF1) ++#define REG_VIP_MCNR_79_L (REG_VIP_MCNR_BASE + 0xF2) ++#define REG_VIP_MCNR_79_H (REG_VIP_MCNR_BASE + 0xF3) ++#define REG_VIP_MCNR_7A_L (REG_VIP_MCNR_BASE + 0xF4) ++#define REG_VIP_MCNR_7A_H (REG_VIP_MCNR_BASE + 0xF5) ++#define REG_VIP_MCNR_7B_L (REG_VIP_MCNR_BASE + 0xF6) ++#define REG_VIP_MCNR_7B_H (REG_VIP_MCNR_BASE + 0xF7) ++#define REG_VIP_MCNR_7C_L (REG_VIP_MCNR_BASE + 0xF8) ++#define REG_VIP_MCNR_7C_H (REG_VIP_MCNR_BASE + 0xF9) ++#define REG_VIP_MCNR_7D_L (REG_VIP_MCNR_BASE + 0xFA) ++#define REG_VIP_MCNR_7D_H (REG_VIP_MCNR_BASE + 0xFB) ++#define REG_VIP_MCNR_7E_L (REG_VIP_MCNR_BASE + 0xFC) ++#define REG_VIP_MCNR_7E_H (REG_VIP_MCNR_BASE + 0xFD) ++#define REG_VIP_MCNR_7F_L (REG_VIP_MCNR_BASE + 0xFE) ++#define REG_VIP_MCNR_7F_H (REG_VIP_MCNR_BASE + 0xFF) ++ ++ ++#define REG_VIP_ACE3_00_L (REG_VIP_ACE3_BASE + 0x00) ++#define REG_VIP_ACE3_00_H (REG_VIP_ACE3_BASE + 0x01) ++#define REG_VIP_ACE3_01_L (REG_VIP_ACE3_BASE + 0x02) ++#define REG_VIP_ACE3_01_H (REG_VIP_ACE3_BASE + 0x03) ++#define REG_VIP_ACE3_02_L (REG_VIP_ACE3_BASE + 0x04) ++#define REG_VIP_ACE3_02_H (REG_VIP_ACE3_BASE + 0x05) ++#define REG_VIP_ACE3_03_L (REG_VIP_ACE3_BASE + 0x06) ++#define REG_VIP_ACE3_03_H (REG_VIP_ACE3_BASE + 0x07) ++#define REG_VIP_ACE3_04_L (REG_VIP_ACE3_BASE + 0x08) ++#define REG_VIP_ACE3_04_H (REG_VIP_ACE3_BASE + 0x09) ++#define REG_VIP_ACE3_05_L (REG_VIP_ACE3_BASE + 0x0A) ++#define REG_VIP_ACE3_05_H (REG_VIP_ACE3_BASE + 0x0B) ++#define REG_VIP_ACE3_06_L (REG_VIP_ACE3_BASE + 0x0C) ++#define REG_VIP_ACE3_06_H (REG_VIP_ACE3_BASE + 0x0D) ++#define REG_VIP_ACE3_07_L (REG_VIP_ACE3_BASE + 0x0E) ++#define REG_VIP_ACE3_07_H (REG_VIP_ACE3_BASE + 0x0F) ++#define REG_VIP_ACE3_08_L (REG_VIP_ACE3_BASE + 0x10) ++#define REG_VIP_ACE3_08_H (REG_VIP_ACE3_BASE + 0x11) ++#define REG_VIP_ACE3_09_L (REG_VIP_ACE3_BASE + 0x12) ++#define REG_VIP_ACE3_09_H (REG_VIP_ACE3_BASE + 0x13) ++#define REG_VIP_ACE3_0A_L (REG_VIP_ACE3_BASE + 0x14) ++#define REG_VIP_ACE3_0A_H (REG_VIP_ACE3_BASE + 0x15) ++#define REG_VIP_ACE3_0B_L (REG_VIP_ACE3_BASE + 0x16) ++#define REG_VIP_ACE3_0B_H (REG_VIP_ACE3_BASE + 0x17) ++#define REG_VIP_ACE3_0C_L (REG_VIP_ACE3_BASE + 0x18) ++#define REG_VIP_ACE3_0C_H (REG_VIP_ACE3_BASE + 0x19) ++#define REG_VIP_ACE3_0D_L (REG_VIP_ACE3_BASE + 0x1A) ++#define REG_VIP_ACE3_0D_H (REG_VIP_ACE3_BASE + 0x1B) ++#define REG_VIP_ACE3_0E_L (REG_VIP_ACE3_BASE + 0x1C) ++#define REG_VIP_ACE3_0E_H (REG_VIP_ACE3_BASE + 0x1D) ++#define REG_VIP_ACE3_0F_L (REG_VIP_ACE3_BASE + 0x1E) ++#define REG_VIP_ACE3_0F_H (REG_VIP_ACE3_BASE + 0x1F) ++#define REG_VIP_ACE3_10_L (REG_VIP_ACE3_BASE + 0x20) ++#define REG_VIP_ACE3_10_H (REG_VIP_ACE3_BASE + 0x21) ++#define REG_VIP_ACE3_11_L (REG_VIP_ACE3_BASE + 0x22) ++#define REG_VIP_ACE3_11_H (REG_VIP_ACE3_BASE + 0x23) ++#define REG_VIP_ACE3_12_L (REG_VIP_ACE3_BASE + 0x24) ++#define REG_VIP_ACE3_12_H (REG_VIP_ACE3_BASE + 0x25) ++#define REG_VIP_ACE3_13_L (REG_VIP_ACE3_BASE + 0x26) ++#define REG_VIP_ACE3_13_H (REG_VIP_ACE3_BASE + 0x27) ++#define REG_VIP_ACE3_14_L (REG_VIP_ACE3_BASE + 0x28) ++#define REG_VIP_ACE3_14_H (REG_VIP_ACE3_BASE + 0x29) ++#define REG_VIP_ACE3_15_L (REG_VIP_ACE3_BASE + 0x2A) ++#define REG_VIP_ACE3_15_H (REG_VIP_ACE3_BASE + 0x2B) ++#define REG_VIP_ACE3_16_L (REG_VIP_ACE3_BASE + 0x2C) ++#define REG_VIP_ACE3_16_H (REG_VIP_ACE3_BASE + 0x2D) ++#define REG_VIP_ACE3_17_L (REG_VIP_ACE3_BASE + 0x2E) ++#define REG_VIP_ACE3_17_H (REG_VIP_ACE3_BASE + 0x2F) ++#define REG_VIP_ACE3_18_L (REG_VIP_ACE3_BASE + 0x30) ++#define REG_VIP_ACE3_18_H (REG_VIP_ACE3_BASE + 0x31) ++#define REG_VIP_ACE3_19_L (REG_VIP_ACE3_BASE + 0x32) ++#define REG_VIP_ACE3_19_H (REG_VIP_ACE3_BASE + 0x33) ++#define REG_VIP_ACE3_1A_L (REG_VIP_ACE3_BASE + 0x34) ++#define REG_VIP_ACE3_1A_H (REG_VIP_ACE3_BASE + 0x35) ++#define REG_VIP_ACE3_1B_L (REG_VIP_ACE3_BASE + 0x36) ++#define REG_VIP_ACE3_1B_H (REG_VIP_ACE3_BASE + 0x37) ++#define REG_VIP_ACE3_1C_L (REG_VIP_ACE3_BASE + 0x38) ++#define REG_VIP_ACE3_1C_H (REG_VIP_ACE3_BASE + 0x39) ++#define REG_VIP_ACE3_1D_L (REG_VIP_ACE3_BASE + 0x3A) ++#define REG_VIP_ACE3_1D_H (REG_VIP_ACE3_BASE + 0x3B) ++#define REG_VIP_ACE3_1E_L (REG_VIP_ACE3_BASE + 0x3C) ++#define REG_VIP_ACE3_1E_H (REG_VIP_ACE3_BASE + 0x3D) ++#define REG_VIP_ACE3_1F_L (REG_VIP_ACE3_BASE + 0x3E) ++#define REG_VIP_ACE3_1F_H (REG_VIP_ACE3_BASE + 0x3F) ++#define REG_VIP_ACE3_20_L (REG_VIP_ACE3_BASE + 0x40) ++#define REG_VIP_ACE3_20_H (REG_VIP_ACE3_BASE + 0x41) ++#define REG_VIP_ACE3_21_L (REG_VIP_ACE3_BASE + 0x42) ++#define REG_VIP_ACE3_21_H (REG_VIP_ACE3_BASE + 0x43) ++#define REG_VIP_ACE3_22_L (REG_VIP_ACE3_BASE + 0x44) ++#define REG_VIP_ACE3_22_H (REG_VIP_ACE3_BASE + 0x45) ++#define REG_VIP_ACE3_23_L (REG_VIP_ACE3_BASE + 0x46) ++#define REG_VIP_ACE3_23_H (REG_VIP_ACE3_BASE + 0x47) ++#define REG_VIP_ACE3_24_L (REG_VIP_ACE3_BASE + 0x48) ++#define REG_VIP_ACE3_24_H (REG_VIP_ACE3_BASE + 0x49) ++#define REG_VIP_ACE3_25_L (REG_VIP_ACE3_BASE + 0x4A) ++#define REG_VIP_ACE3_25_H (REG_VIP_ACE3_BASE + 0x4B) ++#define REG_VIP_ACE3_26_L (REG_VIP_ACE3_BASE + 0x4C) ++#define REG_VIP_ACE3_26_H (REG_VIP_ACE3_BASE + 0x4D) ++#define REG_VIP_ACE3_27_L (REG_VIP_ACE3_BASE + 0x4E) ++#define REG_VIP_ACE3_27_H (REG_VIP_ACE3_BASE + 0x4F) ++#define REG_VIP_ACE3_28_L (REG_VIP_ACE3_BASE + 0x50) ++#define REG_VIP_ACE3_28_H (REG_VIP_ACE3_BASE + 0x51) ++#define REG_VIP_ACE3_29_L (REG_VIP_ACE3_BASE + 0x52) ++#define REG_VIP_ACE3_29_H (REG_VIP_ACE3_BASE + 0x53) ++#define REG_VIP_ACE3_2A_L (REG_VIP_ACE3_BASE + 0x54) ++#define REG_VIP_ACE3_2A_H (REG_VIP_ACE3_BASE + 0x55) ++#define REG_VIP_ACE3_2B_L (REG_VIP_ACE3_BASE + 0x56) ++#define REG_VIP_ACE3_2B_H (REG_VIP_ACE3_BASE + 0x57) ++#define REG_VIP_ACE3_2C_L (REG_VIP_ACE3_BASE + 0x58) ++#define REG_VIP_ACE3_2C_H (REG_VIP_ACE3_BASE + 0x59) ++#define REG_VIP_ACE3_2D_L (REG_VIP_ACE3_BASE + 0x5A) ++#define REG_VIP_ACE3_2D_H (REG_VIP_ACE3_BASE + 0x5B) ++#define REG_VIP_ACE3_2E_L (REG_VIP_ACE3_BASE + 0x5C) ++#define REG_VIP_ACE3_2E_H (REG_VIP_ACE3_BASE + 0x5D) ++#define REG_VIP_ACE3_2F_L (REG_VIP_ACE3_BASE + 0x5E) ++#define REG_VIP_ACE3_2F_H (REG_VIP_ACE3_BASE + 0x5F) ++#define REG_VIP_ACE3_30_L (REG_VIP_ACE3_BASE + 0x60) ++#define REG_VIP_ACE3_30_H (REG_VIP_ACE3_BASE + 0x61) ++#define REG_VIP_ACE3_31_L (REG_VIP_ACE3_BASE + 0x62) ++#define REG_VIP_ACE3_31_H (REG_VIP_ACE3_BASE + 0x63) ++#define REG_VIP_ACE3_32_L (REG_VIP_ACE3_BASE + 0x64) ++#define REG_VIP_ACE3_32_H (REG_VIP_ACE3_BASE + 0x65) ++#define REG_VIP_ACE3_33_L (REG_VIP_ACE3_BASE + 0x66) ++#define REG_VIP_ACE3_33_H (REG_VIP_ACE3_BASE + 0x67) ++#define REG_VIP_ACE3_34_L (REG_VIP_ACE3_BASE + 0x68) ++#define REG_VIP_ACE3_34_H (REG_VIP_ACE3_BASE + 0x69) ++#define REG_VIP_ACE3_35_L (REG_VIP_ACE3_BASE + 0x6A) ++#define REG_VIP_ACE3_35_H (REG_VIP_ACE3_BASE + 0x6B) ++#define REG_VIP_ACE3_36_L (REG_VIP_ACE3_BASE + 0x6C) ++#define REG_VIP_ACE3_36_H (REG_VIP_ACE3_BASE + 0x6D) ++#define REG_VIP_ACE3_37_L (REG_VIP_ACE3_BASE + 0x6E) ++#define REG_VIP_ACE3_37_H (REG_VIP_ACE3_BASE + 0x6F) ++#define REG_VIP_ACE3_38_L (REG_VIP_ACE3_BASE + 0x70) ++#define REG_VIP_ACE3_38_H (REG_VIP_ACE3_BASE + 0x71) ++#define REG_VIP_ACE3_39_L (REG_VIP_ACE3_BASE + 0x72) ++#define REG_VIP_ACE3_39_H (REG_VIP_ACE3_BASE + 0x73) ++#define REG_VIP_ACE3_3A_L (REG_VIP_ACE3_BASE + 0x74) ++#define REG_VIP_ACE3_3A_H (REG_VIP_ACE3_BASE + 0x75) ++#define REG_VIP_ACE3_3B_L (REG_VIP_ACE3_BASE + 0x76) ++#define REG_VIP_ACE3_3B_H (REG_VIP_ACE3_BASE + 0x77) ++#define REG_VIP_ACE3_3C_L (REG_VIP_ACE3_BASE + 0x78) ++#define REG_VIP_ACE3_3C_H (REG_VIP_ACE3_BASE + 0x79) ++#define REG_VIP_ACE3_3D_L (REG_VIP_ACE3_BASE + 0x7A) ++#define REG_VIP_ACE3_3D_H (REG_VIP_ACE3_BASE + 0x7B) ++#define REG_VIP_ACE3_3E_L (REG_VIP_ACE3_BASE + 0x7C) ++#define REG_VIP_ACE3_3E_H (REG_VIP_ACE3_BASE + 0x7D) ++#define REG_VIP_ACE3_3F_L (REG_VIP_ACE3_BASE + 0x7E) ++#define REG_VIP_ACE3_3F_H (REG_VIP_ACE3_BASE + 0x7F) ++#define REG_VIP_ACE3_40_L (REG_VIP_ACE3_BASE + 0x80) ++#define REG_VIP_ACE3_40_H (REG_VIP_ACE3_BASE + 0x81) ++#define REG_VIP_ACE3_41_L (REG_VIP_ACE3_BASE + 0x82) ++#define REG_VIP_ACE3_41_H (REG_VIP_ACE3_BASE + 0x83) ++#define REG_VIP_ACE3_42_L (REG_VIP_ACE3_BASE + 0x84) ++#define REG_VIP_ACE3_42_H (REG_VIP_ACE3_BASE + 0x85) ++#define REG_VIP_ACE3_43_L (REG_VIP_ACE3_BASE + 0x86) ++#define REG_VIP_ACE3_43_H (REG_VIP_ACE3_BASE + 0x87) ++#define REG_VIP_ACE3_44_L (REG_VIP_ACE3_BASE + 0x88) ++#define REG_VIP_ACE3_44_H (REG_VIP_ACE3_BASE + 0x89) ++#define REG_VIP_ACE3_45_L (REG_VIP_ACE3_BASE + 0x8A) ++#define REG_VIP_ACE3_45_H (REG_VIP_ACE3_BASE + 0x8B) ++#define REG_VIP_ACE3_46_L (REG_VIP_ACE3_BASE + 0x8C) ++#define REG_VIP_ACE3_46_H (REG_VIP_ACE3_BASE + 0x8D) ++#define REG_VIP_ACE3_47_L (REG_VIP_ACE3_BASE + 0x8E) ++#define REG_VIP_ACE3_47_H (REG_VIP_ACE3_BASE + 0x8F) ++#define REG_VIP_ACE3_48_L (REG_VIP_ACE3_BASE + 0x90) ++#define REG_VIP_ACE3_48_H (REG_VIP_ACE3_BASE + 0x91) ++#define REG_VIP_ACE3_49_L (REG_VIP_ACE3_BASE + 0x92) ++#define REG_VIP_ACE3_49_H (REG_VIP_ACE3_BASE + 0x93) ++#define REG_VIP_ACE3_4A_L (REG_VIP_ACE3_BASE + 0x94) ++#define REG_VIP_ACE3_4A_H (REG_VIP_ACE3_BASE + 0x95) ++#define REG_VIP_ACE3_4B_L (REG_VIP_ACE3_BASE + 0x96) ++#define REG_VIP_ACE3_4B_H (REG_VIP_ACE3_BASE + 0x97) ++#define REG_VIP_ACE3_4C_L (REG_VIP_ACE3_BASE + 0x98) ++#define REG_VIP_ACE3_4C_H (REG_VIP_ACE3_BASE + 0x99) ++#define REG_VIP_ACE3_4D_L (REG_VIP_ACE3_BASE + 0x9A) ++#define REG_VIP_ACE3_4D_H (REG_VIP_ACE3_BASE + 0x9B) ++#define REG_VIP_ACE3_4E_L (REG_VIP_ACE3_BASE + 0x9C) ++#define REG_VIP_ACE3_4E_H (REG_VIP_ACE3_BASE + 0x9D) ++#define REG_VIP_ACE3_4F_L (REG_VIP_ACE3_BASE + 0x9E) ++#define REG_VIP_ACE3_4F_H (REG_VIP_ACE3_BASE + 0x9F) ++#define REG_VIP_ACE3_50_L (REG_VIP_ACE3_BASE + 0xA0) ++#define REG_VIP_ACE3_50_H (REG_VIP_ACE3_BASE + 0xA1) ++#define REG_VIP_ACE3_51_L (REG_VIP_ACE3_BASE + 0xA2) ++#define REG_VIP_ACE3_51_H (REG_VIP_ACE3_BASE + 0xA3) ++#define REG_VIP_ACE3_52_L (REG_VIP_ACE3_BASE + 0xA4) ++#define REG_VIP_ACE3_52_H (REG_VIP_ACE3_BASE + 0xA5) ++#define REG_VIP_ACE3_53_L (REG_VIP_ACE3_BASE + 0xA6) ++#define REG_VIP_ACE3_53_H (REG_VIP_ACE3_BASE + 0xA7) ++#define REG_VIP_ACE3_54_L (REG_VIP_ACE3_BASE + 0xA8) ++#define REG_VIP_ACE3_54_H (REG_VIP_ACE3_BASE + 0xA9) ++#define REG_VIP_ACE3_55_L (REG_VIP_ACE3_BASE + 0xAA) ++#define REG_VIP_ACE3_55_H (REG_VIP_ACE3_BASE + 0xAB) ++#define REG_VIP_ACE3_56_L (REG_VIP_ACE3_BASE + 0xAC) ++#define REG_VIP_ACE3_56_H (REG_VIP_ACE3_BASE + 0xAD) ++#define REG_VIP_ACE3_57_L (REG_VIP_ACE3_BASE + 0xAE) ++#define REG_VIP_ACE3_57_H (REG_VIP_ACE3_BASE + 0xAF) ++#define REG_VIP_ACE3_58_L (REG_VIP_ACE3_BASE + 0xB0) ++#define REG_VIP_ACE3_58_H (REG_VIP_ACE3_BASE + 0xB1) ++#define REG_VIP_ACE3_59_L (REG_VIP_ACE3_BASE + 0xB2) ++#define REG_VIP_ACE3_59_H (REG_VIP_ACE3_BASE + 0xB3) ++#define REG_VIP_ACE3_5A_L (REG_VIP_ACE3_BASE + 0xB4) ++#define REG_VIP_ACE3_5A_H (REG_VIP_ACE3_BASE + 0xB5) ++#define REG_VIP_ACE3_5B_L (REG_VIP_ACE3_BASE + 0xB6) ++#define REG_VIP_ACE3_5B_H (REG_VIP_ACE3_BASE + 0xB7) ++#define REG_VIP_ACE3_5C_L (REG_VIP_ACE3_BASE + 0xB8) ++#define REG_VIP_ACE3_5C_H (REG_VIP_ACE3_BASE + 0xB9) ++#define REG_VIP_ACE3_5D_L (REG_VIP_ACE3_BASE + 0xBA) ++#define REG_VIP_ACE3_5D_H (REG_VIP_ACE3_BASE + 0xBB) ++#define REG_VIP_ACE3_5E_L (REG_VIP_ACE3_BASE + 0xBC) ++#define REG_VIP_ACE3_5E_H (REG_VIP_ACE3_BASE + 0xBD) ++#define REG_VIP_ACE3_5F_L (REG_VIP_ACE3_BASE + 0xBE) ++#define REG_VIP_ACE3_5F_H (REG_VIP_ACE3_BASE + 0xBF) ++#define REG_VIP_ACE3_60_L (REG_VIP_ACE3_BASE + 0xC0) ++#define REG_VIP_ACE3_60_H (REG_VIP_ACE3_BASE + 0xC1) ++#define REG_VIP_ACE3_61_L (REG_VIP_ACE3_BASE + 0xC2) ++#define REG_VIP_ACE3_61_H (REG_VIP_ACE3_BASE + 0xC3) ++#define REG_VIP_ACE3_62_L (REG_VIP_ACE3_BASE + 0xC4) ++#define REG_VIP_ACE3_62_H (REG_VIP_ACE3_BASE + 0xC5) ++#define REG_VIP_ACE3_63_L (REG_VIP_ACE3_BASE + 0xC6) ++#define REG_VIP_ACE3_63_H (REG_VIP_ACE3_BASE + 0xC7) ++#define REG_VIP_ACE3_64_L (REG_VIP_ACE3_BASE + 0xC8) ++#define REG_VIP_ACE3_64_H (REG_VIP_ACE3_BASE + 0xC9) ++#define REG_VIP_ACE3_65_L (REG_VIP_ACE3_BASE + 0xCA) ++#define REG_VIP_ACE3_65_H (REG_VIP_ACE3_BASE + 0xCB) ++#define REG_VIP_ACE3_66_L (REG_VIP_ACE3_BASE + 0xCC) ++#define REG_VIP_ACE3_66_H (REG_VIP_ACE3_BASE + 0xCD) ++#define REG_VIP_ACE3_67_L (REG_VIP_ACE3_BASE + 0xCE) ++#define REG_VIP_ACE3_67_H (REG_VIP_ACE3_BASE + 0xCF) ++#define REG_VIP_ACE3_68_L (REG_VIP_ACE3_BASE + 0xD0) ++#define REG_VIP_ACE3_68_H (REG_VIP_ACE3_BASE + 0xD1) ++#define REG_VIP_ACE3_69_L (REG_VIP_ACE3_BASE + 0xD2) ++#define REG_VIP_ACE3_69_H (REG_VIP_ACE3_BASE + 0xD3) ++#define REG_VIP_ACE3_6A_L (REG_VIP_ACE3_BASE + 0xD4) ++#define REG_VIP_ACE3_6A_H (REG_VIP_ACE3_BASE + 0xD5) ++#define REG_VIP_ACE3_6B_L (REG_VIP_ACE3_BASE + 0xD6) ++#define REG_VIP_ACE3_6B_H (REG_VIP_ACE3_BASE + 0xD7) ++#define REG_VIP_ACE3_6C_L (REG_VIP_ACE3_BASE + 0xD8) ++#define REG_VIP_ACE3_6C_H (REG_VIP_ACE3_BASE + 0xD9) ++#define REG_VIP_ACE3_6D_L (REG_VIP_ACE3_BASE + 0xDA) ++#define REG_VIP_ACE3_6D_H (REG_VIP_ACE3_BASE + 0xDB) ++#define REG_VIP_ACE3_6E_L (REG_VIP_ACE3_BASE + 0xDC) ++#define REG_VIP_ACE3_6E_H (REG_VIP_ACE3_BASE + 0xDD) ++#define REG_VIP_ACE3_6F_L (REG_VIP_ACE3_BASE + 0xDE) ++#define REG_VIP_ACE3_6F_H (REG_VIP_ACE3_BASE + 0xDF) ++#define REG_VIP_ACE3_70_L (REG_VIP_ACE3_BASE + 0xE0) ++#define REG_VIP_ACE3_70_H (REG_VIP_ACE3_BASE + 0xE1) ++#define REG_VIP_ACE3_71_L (REG_VIP_ACE3_BASE + 0xE2) ++#define REG_VIP_ACE3_71_H (REG_VIP_ACE3_BASE + 0xE3) ++#define REG_VIP_ACE3_72_L (REG_VIP_ACE3_BASE + 0xE4) ++#define REG_VIP_ACE3_72_H (REG_VIP_ACE3_BASE + 0xE5) ++#define REG_VIP_ACE3_73_L (REG_VIP_ACE3_BASE + 0xE6) ++#define REG_VIP_ACE3_73_H (REG_VIP_ACE3_BASE + 0xE7) ++#define REG_VIP_ACE3_74_L (REG_VIP_ACE3_BASE + 0xE8) ++#define REG_VIP_ACE3_74_H (REG_VIP_ACE3_BASE + 0xE9) ++#define REG_VIP_ACE3_75_L (REG_VIP_ACE3_BASE + 0xEA) ++#define REG_VIP_ACE3_75_H (REG_VIP_ACE3_BASE + 0xEB) ++#define REG_VIP_ACE3_76_L (REG_VIP_ACE3_BASE + 0xEC) ++#define REG_VIP_ACE3_76_H (REG_VIP_ACE3_BASE + 0xED) ++#define REG_VIP_ACE3_77_L (REG_VIP_ACE3_BASE + 0xEE) ++#define REG_VIP_ACE3_77_H (REG_VIP_ACE3_BASE + 0xEF) ++#define REG_VIP_ACE3_78_L (REG_VIP_ACE3_BASE + 0xF0) ++#define REG_VIP_ACE3_78_H (REG_VIP_ACE3_BASE + 0xF1) ++#define REG_VIP_ACE3_79_L (REG_VIP_ACE3_BASE + 0xF2) ++#define REG_VIP_ACE3_79_H (REG_VIP_ACE3_BASE + 0xF3) ++#define REG_VIP_ACE3_7A_L (REG_VIP_ACE3_BASE + 0xF4) ++#define REG_VIP_ACE3_7A_H (REG_VIP_ACE3_BASE + 0xF5) ++#define REG_VIP_ACE3_7B_L (REG_VIP_ACE3_BASE + 0xF6) ++#define REG_VIP_ACE3_7B_H (REG_VIP_ACE3_BASE + 0xF7) ++#define REG_VIP_ACE3_7C_L (REG_VIP_ACE3_BASE + 0xF8) ++#define REG_VIP_ACE3_7C_H (REG_VIP_ACE3_BASE + 0xF9) ++#define REG_VIP_ACE3_7D_L (REG_VIP_ACE3_BASE + 0xFA) ++#define REG_VIP_ACE3_7D_H (REG_VIP_ACE3_BASE + 0xFB) ++#define REG_VIP_ACE3_7E_L (REG_VIP_ACE3_BASE + 0xFC) ++#define REG_VIP_ACE3_7E_H (REG_VIP_ACE3_BASE + 0xFD) ++#define REG_VIP_ACE3_7F_L (REG_VIP_ACE3_BASE + 0xFE) ++#define REG_VIP_ACE3_7F_H (REG_VIP_ACE3_BASE + 0xFF) ++ ++#define REG_VIP_ACE2_00_L (REG_VIP_ACE2_BASE + 0x00) ++#define REG_VIP_ACE2_00_H (REG_VIP_ACE2_BASE + 0x01) ++#define REG_VIP_ACE2_01_L (REG_VIP_ACE2_BASE + 0x02) ++#define REG_VIP_ACE2_01_H (REG_VIP_ACE2_BASE + 0x03) ++#define REG_VIP_ACE2_02_L (REG_VIP_ACE2_BASE + 0x04) ++#define REG_VIP_ACE2_02_H (REG_VIP_ACE2_BASE + 0x05) ++#define REG_VIP_ACE2_03_L (REG_VIP_ACE2_BASE + 0x06) ++#define REG_VIP_ACE2_03_H (REG_VIP_ACE2_BASE + 0x07) ++#define REG_VIP_ACE2_04_L (REG_VIP_ACE2_BASE + 0x08) ++#define REG_VIP_ACE2_04_H (REG_VIP_ACE2_BASE + 0x09) ++#define REG_VIP_ACE2_05_L (REG_VIP_ACE2_BASE + 0x0A) ++#define REG_VIP_ACE2_05_H (REG_VIP_ACE2_BASE + 0x0B) ++#define REG_VIP_ACE2_06_L (REG_VIP_ACE2_BASE + 0x0C) ++#define REG_VIP_ACE2_06_H (REG_VIP_ACE2_BASE + 0x0D) ++#define REG_VIP_ACE2_07_L (REG_VIP_ACE2_BASE + 0x0E) ++#define REG_VIP_ACE2_07_H (REG_VIP_ACE2_BASE + 0x0F) ++#define REG_VIP_ACE2_08_L (REG_VIP_ACE2_BASE + 0x10) ++#define REG_VIP_ACE2_08_H (REG_VIP_ACE2_BASE + 0x11) ++#define REG_VIP_ACE2_09_L (REG_VIP_ACE2_BASE + 0x12) ++#define REG_VIP_ACE2_09_H (REG_VIP_ACE2_BASE + 0x13) ++#define REG_VIP_ACE2_0A_L (REG_VIP_ACE2_BASE + 0x14) ++#define REG_VIP_ACE2_0A_H (REG_VIP_ACE2_BASE + 0x15) ++#define REG_VIP_ACE2_0B_L (REG_VIP_ACE2_BASE + 0x16) ++#define REG_VIP_ACE2_0B_H (REG_VIP_ACE2_BASE + 0x17) ++#define REG_VIP_ACE2_0C_L (REG_VIP_ACE2_BASE + 0x18) ++#define REG_VIP_ACE2_0C_H (REG_VIP_ACE2_BASE + 0x19) ++#define REG_VIP_ACE2_0D_L (REG_VIP_ACE2_BASE + 0x1A) ++#define REG_VIP_ACE2_0D_H (REG_VIP_ACE2_BASE + 0x1B) ++#define REG_VIP_ACE2_0E_L (REG_VIP_ACE2_BASE + 0x1C) ++#define REG_VIP_ACE2_0E_H (REG_VIP_ACE2_BASE + 0x1D) ++#define REG_VIP_ACE2_0F_L (REG_VIP_ACE2_BASE + 0x1E) ++#define REG_VIP_ACE2_0F_H (REG_VIP_ACE2_BASE + 0x1F) ++#define REG_VIP_ACE2_10_L (REG_VIP_ACE2_BASE + 0x20) ++#define REG_VIP_ACE2_10_H (REG_VIP_ACE2_BASE + 0x21) ++#define REG_VIP_ACE2_11_L (REG_VIP_ACE2_BASE + 0x22) ++#define REG_VIP_ACE2_11_H (REG_VIP_ACE2_BASE + 0x23) ++#define REG_VIP_ACE2_12_L (REG_VIP_ACE2_BASE + 0x24) ++#define REG_VIP_ACE2_12_H (REG_VIP_ACE2_BASE + 0x25) ++#define REG_VIP_ACE2_13_L (REG_VIP_ACE2_BASE + 0x26) ++#define REG_VIP_ACE2_13_H (REG_VIP_ACE2_BASE + 0x27) ++#define REG_VIP_ACE2_14_L (REG_VIP_ACE2_BASE + 0x28) ++#define REG_VIP_ACE2_14_H (REG_VIP_ACE2_BASE + 0x29) ++#define REG_VIP_ACE2_15_L (REG_VIP_ACE2_BASE + 0x2A) ++#define REG_VIP_ACE2_15_H (REG_VIP_ACE2_BASE + 0x2B) ++#define REG_VIP_ACE2_16_L (REG_VIP_ACE2_BASE + 0x2C) ++#define REG_VIP_ACE2_16_H (REG_VIP_ACE2_BASE + 0x2D) ++#define REG_VIP_ACE2_17_L (REG_VIP_ACE2_BASE + 0x2E) ++#define REG_VIP_ACE2_17_H (REG_VIP_ACE2_BASE + 0x2F) ++#define REG_VIP_ACE2_18_L (REG_VIP_ACE2_BASE + 0x30) ++#define REG_VIP_ACE2_18_H (REG_VIP_ACE2_BASE + 0x31) ++#define REG_VIP_ACE2_19_L (REG_VIP_ACE2_BASE + 0x32) ++#define REG_VIP_ACE2_19_H (REG_VIP_ACE2_BASE + 0x33) ++#define REG_VIP_ACE2_1A_L (REG_VIP_ACE2_BASE + 0x34) ++#define REG_VIP_ACE2_1A_H (REG_VIP_ACE2_BASE + 0x35) ++#define REG_VIP_ACE2_1B_L (REG_VIP_ACE2_BASE + 0x36) ++#define REG_VIP_ACE2_1B_H (REG_VIP_ACE2_BASE + 0x37) ++#define REG_VIP_ACE2_1C_L (REG_VIP_ACE2_BASE + 0x38) ++#define REG_VIP_ACE2_1C_H (REG_VIP_ACE2_BASE + 0x39) ++#define REG_VIP_ACE2_1D_L (REG_VIP_ACE2_BASE + 0x3A) ++#define REG_VIP_ACE2_1D_H (REG_VIP_ACE2_BASE + 0x3B) ++#define REG_VIP_ACE2_1E_L (REG_VIP_ACE2_BASE + 0x3C) ++#define REG_VIP_ACE2_1E_H (REG_VIP_ACE2_BASE + 0x3D) ++#define REG_VIP_ACE2_1F_L (REG_VIP_ACE2_BASE + 0x3E) ++#define REG_VIP_ACE2_1F_H (REG_VIP_ACE2_BASE + 0x3F) ++#define REG_VIP_ACE2_20_L (REG_VIP_ACE2_BASE + 0x40) ++#define REG_VIP_ACE2_20_H (REG_VIP_ACE2_BASE + 0x41) ++#define REG_VIP_ACE2_21_L (REG_VIP_ACE2_BASE + 0x42) ++#define REG_VIP_ACE2_21_H (REG_VIP_ACE2_BASE + 0x43) ++#define REG_VIP_ACE2_22_L (REG_VIP_ACE2_BASE + 0x44) ++#define REG_VIP_ACE2_22_H (REG_VIP_ACE2_BASE + 0x45) ++#define REG_VIP_ACE2_23_L (REG_VIP_ACE2_BASE + 0x46) ++#define REG_VIP_ACE2_23_H (REG_VIP_ACE2_BASE + 0x47) ++#define REG_VIP_ACE2_24_L (REG_VIP_ACE2_BASE + 0x48) ++#define REG_VIP_ACE2_24_H (REG_VIP_ACE2_BASE + 0x49) ++#define REG_VIP_ACE2_25_L (REG_VIP_ACE2_BASE + 0x4A) ++#define REG_VIP_ACE2_25_H (REG_VIP_ACE2_BASE + 0x4B) ++#define REG_VIP_ACE2_26_L (REG_VIP_ACE2_BASE + 0x4C) ++#define REG_VIP_ACE2_26_H (REG_VIP_ACE2_BASE + 0x4D) ++#define REG_VIP_ACE2_27_L (REG_VIP_ACE2_BASE + 0x4E) ++#define REG_VIP_ACE2_27_H (REG_VIP_ACE2_BASE + 0x4F) ++#define REG_VIP_ACE2_28_L (REG_VIP_ACE2_BASE + 0x50) ++#define REG_VIP_ACE2_28_H (REG_VIP_ACE2_BASE + 0x51) ++#define REG_VIP_ACE2_29_L (REG_VIP_ACE2_BASE + 0x52) ++#define REG_VIP_ACE2_29_H (REG_VIP_ACE2_BASE + 0x53) ++#define REG_VIP_ACE2_2A_L (REG_VIP_ACE2_BASE + 0x54) ++#define REG_VIP_ACE2_2A_H (REG_VIP_ACE2_BASE + 0x55) ++#define REG_VIP_ACE2_2B_L (REG_VIP_ACE2_BASE + 0x56) ++#define REG_VIP_ACE2_2B_H (REG_VIP_ACE2_BASE + 0x57) ++#define REG_VIP_ACE2_2C_L (REG_VIP_ACE2_BASE + 0x58) ++#define REG_VIP_ACE2_2C_H (REG_VIP_ACE2_BASE + 0x59) ++#define REG_VIP_ACE2_2D_L (REG_VIP_ACE2_BASE + 0x5A) ++#define REG_VIP_ACE2_2D_H (REG_VIP_ACE2_BASE + 0x5B) ++#define REG_VIP_ACE2_2E_L (REG_VIP_ACE2_BASE + 0x5C) ++#define REG_VIP_ACE2_2E_H (REG_VIP_ACE2_BASE + 0x5D) ++#define REG_VIP_ACE2_2F_L (REG_VIP_ACE2_BASE + 0x5E) ++#define REG_VIP_ACE2_2F_H (REG_VIP_ACE2_BASE + 0x5F) ++#define REG_VIP_ACE2_30_L (REG_VIP_ACE2_BASE + 0x60) ++#define REG_VIP_ACE2_30_H (REG_VIP_ACE2_BASE + 0x61) ++#define REG_VIP_ACE2_31_L (REG_VIP_ACE2_BASE + 0x62) ++#define REG_VIP_ACE2_31_H (REG_VIP_ACE2_BASE + 0x63) ++#define REG_VIP_ACE2_32_L (REG_VIP_ACE2_BASE + 0x64) ++#define REG_VIP_ACE2_32_H (REG_VIP_ACE2_BASE + 0x65) ++#define REG_VIP_ACE2_33_L (REG_VIP_ACE2_BASE + 0x66) ++#define REG_VIP_ACE2_33_H (REG_VIP_ACE2_BASE + 0x67) ++#define REG_VIP_ACE2_34_L (REG_VIP_ACE2_BASE + 0x68) ++#define REG_VIP_ACE2_34_H (REG_VIP_ACE2_BASE + 0x69) ++#define REG_VIP_ACE2_35_L (REG_VIP_ACE2_BASE + 0x6A) ++#define REG_VIP_ACE2_35_H (REG_VIP_ACE2_BASE + 0x6B) ++#define REG_VIP_ACE2_36_L (REG_VIP_ACE2_BASE + 0x6C) ++#define REG_VIP_ACE2_36_H (REG_VIP_ACE2_BASE + 0x6D) ++#define REG_VIP_ACE2_37_L (REG_VIP_ACE2_BASE + 0x6E) ++#define REG_VIP_ACE2_37_H (REG_VIP_ACE2_BASE + 0x6F) ++#define REG_VIP_ACE2_38_L (REG_VIP_ACE2_BASE + 0x70) ++#define REG_VIP_ACE2_38_H (REG_VIP_ACE2_BASE + 0x71) ++#define REG_VIP_ACE2_39_L (REG_VIP_ACE2_BASE + 0x72) ++#define REG_VIP_ACE2_39_H (REG_VIP_ACE2_BASE + 0x73) ++#define REG_VIP_ACE2_3A_L (REG_VIP_ACE2_BASE + 0x74) ++#define REG_VIP_ACE2_3A_H (REG_VIP_ACE2_BASE + 0x75) ++#define REG_VIP_ACE2_3B_L (REG_VIP_ACE2_BASE + 0x76) ++#define REG_VIP_ACE2_3B_H (REG_VIP_ACE2_BASE + 0x77) ++#define REG_VIP_ACE2_3C_L (REG_VIP_ACE2_BASE + 0x78) ++#define REG_VIP_ACE2_3C_H (REG_VIP_ACE2_BASE + 0x79) ++#define REG_VIP_ACE2_3D_L (REG_VIP_ACE2_BASE + 0x7A) ++#define REG_VIP_ACE2_3D_H (REG_VIP_ACE2_BASE + 0x7B) ++#define REG_VIP_ACE2_3E_L (REG_VIP_ACE2_BASE + 0x7C) ++#define REG_VIP_ACE2_3E_H (REG_VIP_ACE2_BASE + 0x7D) ++#define REG_VIP_ACE2_3F_L (REG_VIP_ACE2_BASE + 0x7E) ++#define REG_VIP_ACE2_3F_H (REG_VIP_ACE2_BASE + 0x7F) ++#define REG_VIP_ACE2_40_L (REG_VIP_ACE2_BASE + 0x80) ++#define REG_VIP_ACE2_40_H (REG_VIP_ACE2_BASE + 0x81) ++#define REG_VIP_ACE2_41_L (REG_VIP_ACE2_BASE + 0x82) ++#define REG_VIP_ACE2_41_H (REG_VIP_ACE2_BASE + 0x83) ++#define REG_VIP_ACE2_42_L (REG_VIP_ACE2_BASE + 0x84) ++#define REG_VIP_ACE2_42_H (REG_VIP_ACE2_BASE + 0x85) ++#define REG_VIP_ACE2_43_L (REG_VIP_ACE2_BASE + 0x86) ++#define REG_VIP_ACE2_43_H (REG_VIP_ACE2_BASE + 0x87) ++#define REG_VIP_ACE2_44_L (REG_VIP_ACE2_BASE + 0x88) ++#define REG_VIP_ACE2_44_H (REG_VIP_ACE2_BASE + 0x89) ++#define REG_VIP_ACE2_45_L (REG_VIP_ACE2_BASE + 0x8A) ++#define REG_VIP_ACE2_45_H (REG_VIP_ACE2_BASE + 0x8B) ++#define REG_VIP_ACE2_46_L (REG_VIP_ACE2_BASE + 0x8C) ++#define REG_VIP_ACE2_46_H (REG_VIP_ACE2_BASE + 0x8D) ++#define REG_VIP_ACE2_47_L (REG_VIP_ACE2_BASE + 0x8E) ++#define REG_VIP_ACE2_47_H (REG_VIP_ACE2_BASE + 0x8F) ++#define REG_VIP_ACE2_48_L (REG_VIP_ACE2_BASE + 0x90) ++#define REG_VIP_ACE2_48_H (REG_VIP_ACE2_BASE + 0x91) ++#define REG_VIP_ACE2_49_L (REG_VIP_ACE2_BASE + 0x92) ++#define REG_VIP_ACE2_49_H (REG_VIP_ACE2_BASE + 0x93) ++#define REG_VIP_ACE2_4A_L (REG_VIP_ACE2_BASE + 0x94) ++#define REG_VIP_ACE2_4A_H (REG_VIP_ACE2_BASE + 0x95) ++#define REG_VIP_ACE2_4B_L (REG_VIP_ACE2_BASE + 0x96) ++#define REG_VIP_ACE2_4B_H (REG_VIP_ACE2_BASE + 0x97) ++#define REG_VIP_ACE2_4C_L (REG_VIP_ACE2_BASE + 0x98) ++#define REG_VIP_ACE2_4C_H (REG_VIP_ACE2_BASE + 0x99) ++#define REG_VIP_ACE2_4D_L (REG_VIP_ACE2_BASE + 0x9A) ++#define REG_VIP_ACE2_4D_H (REG_VIP_ACE2_BASE + 0x9B) ++#define REG_VIP_ACE2_4E_L (REG_VIP_ACE2_BASE + 0x9C) ++#define REG_VIP_ACE2_4E_H (REG_VIP_ACE2_BASE + 0x9D) ++#define REG_VIP_ACE2_4F_L (REG_VIP_ACE2_BASE + 0x9E) ++#define REG_VIP_ACE2_4F_H (REG_VIP_ACE2_BASE + 0x9F) ++#define REG_VIP_ACE2_50_L (REG_VIP_ACE2_BASE + 0xA0) ++#define REG_VIP_ACE2_50_H (REG_VIP_ACE2_BASE + 0xA1) ++#define REG_VIP_ACE2_51_L (REG_VIP_ACE2_BASE + 0xA2) ++#define REG_VIP_ACE2_51_H (REG_VIP_ACE2_BASE + 0xA3) ++#define REG_VIP_ACE2_52_L (REG_VIP_ACE2_BASE + 0xA4) ++#define REG_VIP_ACE2_52_H (REG_VIP_ACE2_BASE + 0xA5) ++#define REG_VIP_ACE2_53_L (REG_VIP_ACE2_BASE + 0xA6) ++#define REG_VIP_ACE2_53_H (REG_VIP_ACE2_BASE + 0xA7) ++#define REG_VIP_ACE2_54_L (REG_VIP_ACE2_BASE + 0xA8) ++#define REG_VIP_ACE2_54_H (REG_VIP_ACE2_BASE + 0xA9) ++#define REG_VIP_ACE2_55_L (REG_VIP_ACE2_BASE + 0xAA) ++#define REG_VIP_ACE2_55_H (REG_VIP_ACE2_BASE + 0xAB) ++#define REG_VIP_ACE2_56_L (REG_VIP_ACE2_BASE + 0xAC) ++#define REG_VIP_ACE2_56_H (REG_VIP_ACE2_BASE + 0xAD) ++#define REG_VIP_ACE2_57_L (REG_VIP_ACE2_BASE + 0xAE) ++#define REG_VIP_ACE2_57_H (REG_VIP_ACE2_BASE + 0xAF) ++#define REG_VIP_ACE2_58_L (REG_VIP_ACE2_BASE + 0xB0) ++#define REG_VIP_ACE2_58_H (REG_VIP_ACE2_BASE + 0xB1) ++#define REG_VIP_ACE2_59_L (REG_VIP_ACE2_BASE + 0xB2) ++#define REG_VIP_ACE2_59_H (REG_VIP_ACE2_BASE + 0xB3) ++#define REG_VIP_ACE2_5A_L (REG_VIP_ACE2_BASE + 0xB4) ++#define REG_VIP_ACE2_5A_H (REG_VIP_ACE2_BASE + 0xB5) ++#define REG_VIP_ACE2_5B_L (REG_VIP_ACE2_BASE + 0xB6) ++#define REG_VIP_ACE2_5B_H (REG_VIP_ACE2_BASE + 0xB7) ++#define REG_VIP_ACE2_5C_L (REG_VIP_ACE2_BASE + 0xB8) ++#define REG_VIP_ACE2_5C_H (REG_VIP_ACE2_BASE + 0xB9) ++#define REG_VIP_ACE2_5D_L (REG_VIP_ACE2_BASE + 0xBA) ++#define REG_VIP_ACE2_5D_H (REG_VIP_ACE2_BASE + 0xBB) ++#define REG_VIP_ACE2_5E_L (REG_VIP_ACE2_BASE + 0xBC) ++#define REG_VIP_ACE2_5E_H (REG_VIP_ACE2_BASE + 0xBD) ++#define REG_VIP_ACE2_5F_L (REG_VIP_ACE2_BASE + 0xBE) ++#define REG_VIP_ACE2_5F_H (REG_VIP_ACE2_BASE + 0xBF) ++#define REG_VIP_ACE2_60_L (REG_VIP_ACE2_BASE + 0xC0) ++#define REG_VIP_ACE2_60_H (REG_VIP_ACE2_BASE + 0xC1) ++#define REG_VIP_ACE2_61_L (REG_VIP_ACE2_BASE + 0xC2) ++#define REG_VIP_ACE2_61_H (REG_VIP_ACE2_BASE + 0xC3) ++#define REG_VIP_ACE2_62_L (REG_VIP_ACE2_BASE + 0xC4) ++#define REG_VIP_ACE2_62_H (REG_VIP_ACE2_BASE + 0xC5) ++#define REG_VIP_ACE2_63_L (REG_VIP_ACE2_BASE + 0xC6) ++#define REG_VIP_ACE2_63_H (REG_VIP_ACE2_BASE + 0xC7) ++#define REG_VIP_ACE2_64_L (REG_VIP_ACE2_BASE + 0xC8) ++#define REG_VIP_ACE2_64_H (REG_VIP_ACE2_BASE + 0xC9) ++#define REG_VIP_ACE2_65_L (REG_VIP_ACE2_BASE + 0xCA) ++#define REG_VIP_ACE2_65_H (REG_VIP_ACE2_BASE + 0xCB) ++#define REG_VIP_ACE2_66_L (REG_VIP_ACE2_BASE + 0xCC) ++#define REG_VIP_ACE2_66_H (REG_VIP_ACE2_BASE + 0xCD) ++#define REG_VIP_ACE2_67_L (REG_VIP_ACE2_BASE + 0xCE) ++#define REG_VIP_ACE2_67_H (REG_VIP_ACE2_BASE + 0xCF) ++#define REG_VIP_ACE2_68_L (REG_VIP_ACE2_BASE + 0xD0) ++#define REG_VIP_ACE2_68_H (REG_VIP_ACE2_BASE + 0xD1) ++#define REG_VIP_ACE2_69_L (REG_VIP_ACE2_BASE + 0xD2) ++#define REG_VIP_ACE2_69_H (REG_VIP_ACE2_BASE + 0xD3) ++#define REG_VIP_ACE2_6A_L (REG_VIP_ACE2_BASE + 0xD4) ++#define REG_VIP_ACE2_6A_H (REG_VIP_ACE2_BASE + 0xD5) ++#define REG_VIP_ACE2_6B_L (REG_VIP_ACE2_BASE + 0xD6) ++#define REG_VIP_ACE2_6B_H (REG_VIP_ACE2_BASE + 0xD7) ++#define REG_VIP_ACE2_6C_L (REG_VIP_ACE2_BASE + 0xD8) ++#define REG_VIP_ACE2_6C_H (REG_VIP_ACE2_BASE + 0xD9) ++#define REG_VIP_ACE2_6D_L (REG_VIP_ACE2_BASE + 0xDA) ++#define REG_VIP_ACE2_6D_H (REG_VIP_ACE2_BASE + 0xDB) ++#define REG_VIP_ACE2_6E_L (REG_VIP_ACE2_BASE + 0xDC) ++#define REG_VIP_ACE2_6E_H (REG_VIP_ACE2_BASE + 0xDD) ++#define REG_VIP_ACE2_6F_L (REG_VIP_ACE2_BASE + 0xDE) ++#define REG_VIP_ACE2_6F_H (REG_VIP_ACE2_BASE + 0xDF) ++#define REG_VIP_ACE2_70_L (REG_VIP_ACE2_BASE + 0xE0) ++#define REG_VIP_ACE2_70_H (REG_VIP_ACE2_BASE + 0xE1) ++#define REG_VIP_ACE2_71_L (REG_VIP_ACE2_BASE + 0xE2) ++#define REG_VIP_ACE2_71_H (REG_VIP_ACE2_BASE + 0xE3) ++#define REG_VIP_ACE2_72_L (REG_VIP_ACE2_BASE + 0xE4) ++#define REG_VIP_ACE2_72_H (REG_VIP_ACE2_BASE + 0xE5) ++#define REG_VIP_ACE2_73_L (REG_VIP_ACE2_BASE + 0xE6) ++#define REG_VIP_ACE2_73_H (REG_VIP_ACE2_BASE + 0xE7) ++#define REG_VIP_ACE2_74_L (REG_VIP_ACE2_BASE + 0xE8) ++#define REG_VIP_ACE2_74_H (REG_VIP_ACE2_BASE + 0xE9) ++#define REG_VIP_ACE2_75_L (REG_VIP_ACE2_BASE + 0xEA) ++#define REG_VIP_ACE2_75_H (REG_VIP_ACE2_BASE + 0xEB) ++#define REG_VIP_ACE2_76_L (REG_VIP_ACE2_BASE + 0xEC) ++#define REG_VIP_ACE2_76_H (REG_VIP_ACE2_BASE + 0xED) ++#define REG_VIP_ACE2_77_L (REG_VIP_ACE2_BASE + 0xEE) ++#define REG_VIP_ACE2_77_H (REG_VIP_ACE2_BASE + 0xEF) ++#define REG_VIP_ACE2_78_L (REG_VIP_ACE2_BASE + 0xF0) ++#define REG_VIP_ACE2_78_H (REG_VIP_ACE2_BASE + 0xF1) ++#define REG_VIP_ACE2_79_L (REG_VIP_ACE2_BASE + 0xF2) ++#define REG_VIP_ACE2_79_H (REG_VIP_ACE2_BASE + 0xF3) ++#define REG_VIP_ACE2_7A_L (REG_VIP_ACE2_BASE + 0xF4) ++#define REG_VIP_ACE2_7A_H (REG_VIP_ACE2_BASE + 0xF5) ++#define REG_VIP_ACE2_7B_L (REG_VIP_ACE2_BASE + 0xF6) ++#define REG_VIP_ACE2_7B_H (REG_VIP_ACE2_BASE + 0xF7) ++#define REG_VIP_ACE2_7C_L (REG_VIP_ACE2_BASE + 0xF8) ++#define REG_VIP_ACE2_7C_H (REG_VIP_ACE2_BASE + 0xF9) ++#define REG_VIP_ACE2_7D_L (REG_VIP_ACE2_BASE + 0xFA) ++#define REG_VIP_ACE2_7D_H (REG_VIP_ACE2_BASE + 0xFB) ++#define REG_VIP_ACE2_7E_L (REG_VIP_ACE2_BASE + 0xFC) ++#define REG_VIP_ACE2_7E_H (REG_VIP_ACE2_BASE + 0xFD) ++#define REG_VIP_ACE2_7F_L (REG_VIP_ACE2_BASE + 0xFE) ++#define REG_VIP_ACE2_7F_H (REG_VIP_ACE2_BASE + 0xFF) ++ ++#define REG_VIP_ACE_00_L (REG_VIP_ACE_BASE + 0x00) ++#define REG_VIP_ACE_00_H (REG_VIP_ACE_BASE + 0x01) ++#define REG_VIP_ACE_01_L (REG_VIP_ACE_BASE + 0x02) ++#define REG_VIP_ACE_01_H (REG_VIP_ACE_BASE + 0x03) ++#define REG_VIP_ACE_02_L (REG_VIP_ACE_BASE + 0x04) ++#define REG_VIP_ACE_02_H (REG_VIP_ACE_BASE + 0x05) ++#define REG_VIP_ACE_03_L (REG_VIP_ACE_BASE + 0x06) ++#define REG_VIP_ACE_03_H (REG_VIP_ACE_BASE + 0x07) ++#define REG_VIP_ACE_04_L (REG_VIP_ACE_BASE + 0x08) ++#define REG_VIP_ACE_04_H (REG_VIP_ACE_BASE + 0x09) ++#define REG_VIP_ACE_05_L (REG_VIP_ACE_BASE + 0x0A) ++#define REG_VIP_ACE_05_H (REG_VIP_ACE_BASE + 0x0B) ++#define REG_VIP_ACE_06_L (REG_VIP_ACE_BASE + 0x0C) ++#define REG_VIP_ACE_06_H (REG_VIP_ACE_BASE + 0x0D) ++#define REG_VIP_ACE_07_L (REG_VIP_ACE_BASE + 0x0E) ++#define REG_VIP_ACE_07_H (REG_VIP_ACE_BASE + 0x0F) ++#define REG_VIP_ACE_08_L (REG_VIP_ACE_BASE + 0x10) ++#define REG_VIP_ACE_08_H (REG_VIP_ACE_BASE + 0x11) ++#define REG_VIP_ACE_09_L (REG_VIP_ACE_BASE + 0x12) ++#define REG_VIP_ACE_09_H (REG_VIP_ACE_BASE + 0x13) ++#define REG_VIP_ACE_0A_L (REG_VIP_ACE_BASE + 0x14) ++#define REG_VIP_ACE_0A_H (REG_VIP_ACE_BASE + 0x15) ++#define REG_VIP_ACE_0B_L (REG_VIP_ACE_BASE + 0x16) ++#define REG_VIP_ACE_0B_H (REG_VIP_ACE_BASE + 0x17) ++#define REG_VIP_ACE_0C_L (REG_VIP_ACE_BASE + 0x18) ++#define REG_VIP_ACE_0C_H (REG_VIP_ACE_BASE + 0x19) ++#define REG_VIP_ACE_0D_L (REG_VIP_ACE_BASE + 0x1A) ++#define REG_VIP_ACE_0D_H (REG_VIP_ACE_BASE + 0x1B) ++#define REG_VIP_ACE_0E_L (REG_VIP_ACE_BASE + 0x1C) ++#define REG_VIP_ACE_0E_H (REG_VIP_ACE_BASE + 0x1D) ++#define REG_VIP_ACE_0F_L (REG_VIP_ACE_BASE + 0x1E) ++#define REG_VIP_ACE_0F_H (REG_VIP_ACE_BASE + 0x1F) ++#define REG_VIP_ACE_10_L (REG_VIP_ACE_BASE + 0x20) ++#define REG_VIP_ACE_10_H (REG_VIP_ACE_BASE + 0x21) ++#define REG_VIP_ACE_11_L (REG_VIP_ACE_BASE + 0x22) ++#define REG_VIP_ACE_11_H (REG_VIP_ACE_BASE + 0x23) ++#define REG_VIP_ACE_12_L (REG_VIP_ACE_BASE + 0x24) ++#define REG_VIP_ACE_12_H (REG_VIP_ACE_BASE + 0x25) ++#define REG_VIP_ACE_13_L (REG_VIP_ACE_BASE + 0x26) ++#define REG_VIP_ACE_13_H (REG_VIP_ACE_BASE + 0x27) ++#define REG_VIP_ACE_14_L (REG_VIP_ACE_BASE + 0x28) ++#define REG_VIP_ACE_14_H (REG_VIP_ACE_BASE + 0x29) ++#define REG_VIP_ACE_15_L (REG_VIP_ACE_BASE + 0x2A) ++#define REG_VIP_ACE_15_H (REG_VIP_ACE_BASE + 0x2B) ++#define REG_VIP_ACE_16_L (REG_VIP_ACE_BASE + 0x2C) ++#define REG_VIP_ACE_16_H (REG_VIP_ACE_BASE + 0x2D) ++#define REG_VIP_ACE_17_L (REG_VIP_ACE_BASE + 0x2E) ++#define REG_VIP_ACE_17_H (REG_VIP_ACE_BASE + 0x2F) ++#define REG_VIP_ACE_18_L (REG_VIP_ACE_BASE + 0x30) ++#define REG_VIP_ACE_18_H (REG_VIP_ACE_BASE + 0x31) ++#define REG_VIP_ACE_19_L (REG_VIP_ACE_BASE + 0x32) ++#define REG_VIP_ACE_19_H (REG_VIP_ACE_BASE + 0x33) ++#define REG_VIP_ACE_1A_L (REG_VIP_ACE_BASE + 0x34) ++#define REG_VIP_ACE_1A_H (REG_VIP_ACE_BASE + 0x35) ++#define REG_VIP_ACE_1B_L (REG_VIP_ACE_BASE + 0x36) ++#define REG_VIP_ACE_1B_H (REG_VIP_ACE_BASE + 0x37) ++#define REG_VIP_ACE_1C_L (REG_VIP_ACE_BASE + 0x38) ++#define REG_VIP_ACE_1C_H (REG_VIP_ACE_BASE + 0x39) ++#define REG_VIP_ACE_1D_L (REG_VIP_ACE_BASE + 0x3A) ++#define REG_VIP_ACE_1D_H (REG_VIP_ACE_BASE + 0x3B) ++#define REG_VIP_ACE_1E_L (REG_VIP_ACE_BASE + 0x3C) ++#define REG_VIP_ACE_1E_H (REG_VIP_ACE_BASE + 0x3D) ++#define REG_VIP_ACE_1F_L (REG_VIP_ACE_BASE + 0x3E) ++#define REG_VIP_ACE_1F_H (REG_VIP_ACE_BASE + 0x3F) ++#define REG_VIP_ACE_20_L (REG_VIP_ACE_BASE + 0x40) ++#define REG_VIP_ACE_20_H (REG_VIP_ACE_BASE + 0x41) ++#define REG_VIP_ACE_21_L (REG_VIP_ACE_BASE + 0x42) ++#define REG_VIP_ACE_21_H (REG_VIP_ACE_BASE + 0x43) ++#define REG_VIP_ACE_22_L (REG_VIP_ACE_BASE + 0x44) ++#define REG_VIP_ACE_22_H (REG_VIP_ACE_BASE + 0x45) ++#define REG_VIP_ACE_23_L (REG_VIP_ACE_BASE + 0x46) ++#define REG_VIP_ACE_23_H (REG_VIP_ACE_BASE + 0x47) ++#define REG_VIP_ACE_24_L (REG_VIP_ACE_BASE + 0x48) ++#define REG_VIP_ACE_24_H (REG_VIP_ACE_BASE + 0x49) ++#define REG_VIP_ACE_25_L (REG_VIP_ACE_BASE + 0x4A) ++#define REG_VIP_ACE_25_H (REG_VIP_ACE_BASE + 0x4B) ++#define REG_VIP_ACE_26_L (REG_VIP_ACE_BASE + 0x4C) ++#define REG_VIP_ACE_26_H (REG_VIP_ACE_BASE + 0x4D) ++#define REG_VIP_ACE_27_L (REG_VIP_ACE_BASE + 0x4E) ++#define REG_VIP_ACE_27_H (REG_VIP_ACE_BASE + 0x4F) ++#define REG_VIP_ACE_28_L (REG_VIP_ACE_BASE + 0x50) ++#define REG_VIP_ACE_28_H (REG_VIP_ACE_BASE + 0x51) ++#define REG_VIP_ACE_29_L (REG_VIP_ACE_BASE + 0x52) ++#define REG_VIP_ACE_29_H (REG_VIP_ACE_BASE + 0x53) ++#define REG_VIP_ACE_2A_L (REG_VIP_ACE_BASE + 0x54) ++#define REG_VIP_ACE_2A_H (REG_VIP_ACE_BASE + 0x55) ++#define REG_VIP_ACE_2B_L (REG_VIP_ACE_BASE + 0x56) ++#define REG_VIP_ACE_2B_H (REG_VIP_ACE_BASE + 0x57) ++#define REG_VIP_ACE_2C_L (REG_VIP_ACE_BASE + 0x58) ++#define REG_VIP_ACE_2C_H (REG_VIP_ACE_BASE + 0x59) ++#define REG_VIP_ACE_2D_L (REG_VIP_ACE_BASE + 0x5A) ++#define REG_VIP_ACE_2D_H (REG_VIP_ACE_BASE + 0x5B) ++#define REG_VIP_ACE_2E_L (REG_VIP_ACE_BASE + 0x5C) ++#define REG_VIP_ACE_2E_H (REG_VIP_ACE_BASE + 0x5D) ++#define REG_VIP_ACE_2F_L (REG_VIP_ACE_BASE + 0x5E) ++#define REG_VIP_ACE_2F_H (REG_VIP_ACE_BASE + 0x5F) ++#define REG_VIP_ACE_30_L (REG_VIP_ACE_BASE + 0x60) ++#define REG_VIP_ACE_30_H (REG_VIP_ACE_BASE + 0x61) ++#define REG_VIP_ACE_31_L (REG_VIP_ACE_BASE + 0x62) ++#define REG_VIP_ACE_31_H (REG_VIP_ACE_BASE + 0x63) ++#define REG_VIP_ACE_32_L (REG_VIP_ACE_BASE + 0x64) ++#define REG_VIP_ACE_32_H (REG_VIP_ACE_BASE + 0x65) ++#define REG_VIP_ACE_33_L (REG_VIP_ACE_BASE + 0x66) ++#define REG_VIP_ACE_33_H (REG_VIP_ACE_BASE + 0x67) ++#define REG_VIP_ACE_34_L (REG_VIP_ACE_BASE + 0x68) ++#define REG_VIP_ACE_34_H (REG_VIP_ACE_BASE + 0x69) ++#define REG_VIP_ACE_35_L (REG_VIP_ACE_BASE + 0x6A) ++#define REG_VIP_ACE_35_H (REG_VIP_ACE_BASE + 0x6B) ++#define REG_VIP_ACE_36_L (REG_VIP_ACE_BASE + 0x6C) ++#define REG_VIP_ACE_36_H (REG_VIP_ACE_BASE + 0x6D) ++#define REG_VIP_ACE_37_L (REG_VIP_ACE_BASE + 0x6E) ++#define REG_VIP_ACE_37_H (REG_VIP_ACE_BASE + 0x6F) ++#define REG_VIP_ACE_38_L (REG_VIP_ACE_BASE + 0x70) ++#define REG_VIP_ACE_38_H (REG_VIP_ACE_BASE + 0x71) ++#define REG_VIP_ACE_39_L (REG_VIP_ACE_BASE + 0x72) ++#define REG_VIP_ACE_39_H (REG_VIP_ACE_BASE + 0x73) ++#define REG_VIP_ACE_3A_L (REG_VIP_ACE_BASE + 0x74) ++#define REG_VIP_ACE_3A_H (REG_VIP_ACE_BASE + 0x75) ++#define REG_VIP_ACE_3B_L (REG_VIP_ACE_BASE + 0x76) ++#define REG_VIP_ACE_3B_H (REG_VIP_ACE_BASE + 0x77) ++#define REG_VIP_ACE_3C_L (REG_VIP_ACE_BASE + 0x78) ++#define REG_VIP_ACE_3C_H (REG_VIP_ACE_BASE + 0x79) ++#define REG_VIP_ACE_3D_L (REG_VIP_ACE_BASE + 0x7A) ++#define REG_VIP_ACE_3D_H (REG_VIP_ACE_BASE + 0x7B) ++#define REG_VIP_ACE_3E_L (REG_VIP_ACE_BASE + 0x7C) ++#define REG_VIP_ACE_3E_H (REG_VIP_ACE_BASE + 0x7D) ++#define REG_VIP_ACE_3F_L (REG_VIP_ACE_BASE + 0x7E) ++#define REG_VIP_ACE_3F_H (REG_VIP_ACE_BASE + 0x7F) ++#define REG_VIP_ACE_40_L (REG_VIP_ACE_BASE + 0x80) ++#define REG_VIP_ACE_40_H (REG_VIP_ACE_BASE + 0x81) ++#define REG_VIP_ACE_41_L (REG_VIP_ACE_BASE + 0x82) ++#define REG_VIP_ACE_41_H (REG_VIP_ACE_BASE + 0x83) ++#define REG_VIP_ACE_42_L (REG_VIP_ACE_BASE + 0x84) ++#define REG_VIP_ACE_42_H (REG_VIP_ACE_BASE + 0x85) ++#define REG_VIP_ACE_43_L (REG_VIP_ACE_BASE + 0x86) ++#define REG_VIP_ACE_43_H (REG_VIP_ACE_BASE + 0x87) ++#define REG_VIP_ACE_44_L (REG_VIP_ACE_BASE + 0x88) ++#define REG_VIP_ACE_44_H (REG_VIP_ACE_BASE + 0x89) ++#define REG_VIP_ACE_45_L (REG_VIP_ACE_BASE + 0x8A) ++#define REG_VIP_ACE_45_H (REG_VIP_ACE_BASE + 0x8B) ++#define REG_VIP_ACE_46_L (REG_VIP_ACE_BASE + 0x8C) ++#define REG_VIP_ACE_46_H (REG_VIP_ACE_BASE + 0x8D) ++#define REG_VIP_ACE_47_L (REG_VIP_ACE_BASE + 0x8E) ++#define REG_VIP_ACE_47_H (REG_VIP_ACE_BASE + 0x8F) ++#define REG_VIP_ACE_48_L (REG_VIP_ACE_BASE + 0x90) ++#define REG_VIP_ACE_48_H (REG_VIP_ACE_BASE + 0x91) ++#define REG_VIP_ACE_49_L (REG_VIP_ACE_BASE + 0x92) ++#define REG_VIP_ACE_49_H (REG_VIP_ACE_BASE + 0x93) ++#define REG_VIP_ACE_4A_L (REG_VIP_ACE_BASE + 0x94) ++#define REG_VIP_ACE_4A_H (REG_VIP_ACE_BASE + 0x95) ++#define REG_VIP_ACE_4B_L (REG_VIP_ACE_BASE + 0x96) ++#define REG_VIP_ACE_4B_H (REG_VIP_ACE_BASE + 0x97) ++#define REG_VIP_ACE_4C_L (REG_VIP_ACE_BASE + 0x98) ++#define REG_VIP_ACE_4C_H (REG_VIP_ACE_BASE + 0x99) ++#define REG_VIP_ACE_4D_L (REG_VIP_ACE_BASE + 0x9A) ++#define REG_VIP_ACE_4D_H (REG_VIP_ACE_BASE + 0x9B) ++#define REG_VIP_ACE_4E_L (REG_VIP_ACE_BASE + 0x9C) ++#define REG_VIP_ACE_4E_H (REG_VIP_ACE_BASE + 0x9D) ++#define REG_VIP_ACE_4F_L (REG_VIP_ACE_BASE + 0x9E) ++#define REG_VIP_ACE_4F_H (REG_VIP_ACE_BASE + 0x9F) ++#define REG_VIP_ACE_50_L (REG_VIP_ACE_BASE + 0xA0) ++#define REG_VIP_ACE_50_H (REG_VIP_ACE_BASE + 0xA1) ++#define REG_VIP_ACE_51_L (REG_VIP_ACE_BASE + 0xA2) ++#define REG_VIP_ACE_51_H (REG_VIP_ACE_BASE + 0xA3) ++#define REG_VIP_ACE_52_L (REG_VIP_ACE_BASE + 0xA4) ++#define REG_VIP_ACE_52_H (REG_VIP_ACE_BASE + 0xA5) ++#define REG_VIP_ACE_53_L (REG_VIP_ACE_BASE + 0xA6) ++#define REG_VIP_ACE_53_H (REG_VIP_ACE_BASE + 0xA7) ++#define REG_VIP_ACE_54_L (REG_VIP_ACE_BASE + 0xA8) ++#define REG_VIP_ACE_54_H (REG_VIP_ACE_BASE + 0xA9) ++#define REG_VIP_ACE_55_L (REG_VIP_ACE_BASE + 0xAA) ++#define REG_VIP_ACE_55_H (REG_VIP_ACE_BASE + 0xAB) ++#define REG_VIP_ACE_56_L (REG_VIP_ACE_BASE + 0xAC) ++#define REG_VIP_ACE_56_H (REG_VIP_ACE_BASE + 0xAD) ++#define REG_VIP_ACE_57_L (REG_VIP_ACE_BASE + 0xAE) ++#define REG_VIP_ACE_57_H (REG_VIP_ACE_BASE + 0xAF) ++#define REG_VIP_ACE_58_L (REG_VIP_ACE_BASE + 0xB0) ++#define REG_VIP_ACE_58_H (REG_VIP_ACE_BASE + 0xB1) ++#define REG_VIP_ACE_59_L (REG_VIP_ACE_BASE + 0xB2) ++#define REG_VIP_ACE_59_H (REG_VIP_ACE_BASE + 0xB3) ++#define REG_VIP_ACE_5A_L (REG_VIP_ACE_BASE + 0xB4) ++#define REG_VIP_ACE_5A_H (REG_VIP_ACE_BASE + 0xB5) ++#define REG_VIP_ACE_5B_L (REG_VIP_ACE_BASE + 0xB6) ++#define REG_VIP_ACE_5B_H (REG_VIP_ACE_BASE + 0xB7) ++#define REG_VIP_ACE_5C_L (REG_VIP_ACE_BASE + 0xB8) ++#define REG_VIP_ACE_5C_H (REG_VIP_ACE_BASE + 0xB9) ++#define REG_VIP_ACE_5D_L (REG_VIP_ACE_BASE + 0xBA) ++#define REG_VIP_ACE_5D_H (REG_VIP_ACE_BASE + 0xBB) ++#define REG_VIP_ACE_5E_L (REG_VIP_ACE_BASE + 0xBC) ++#define REG_VIP_ACE_5E_H (REG_VIP_ACE_BASE + 0xBD) ++#define REG_VIP_ACE_5F_L (REG_VIP_ACE_BASE + 0xBE) ++#define REG_VIP_ACE_5F_H (REG_VIP_ACE_BASE + 0xBF) ++#define REG_VIP_ACE_60_L (REG_VIP_ACE_BASE + 0xC0) ++#define REG_VIP_ACE_60_H (REG_VIP_ACE_BASE + 0xC1) ++#define REG_VIP_ACE_61_L (REG_VIP_ACE_BASE + 0xC2) ++#define REG_VIP_ACE_61_H (REG_VIP_ACE_BASE + 0xC3) ++#define REG_VIP_ACE_62_L (REG_VIP_ACE_BASE + 0xC4) ++#define REG_VIP_ACE_62_H (REG_VIP_ACE_BASE + 0xC5) ++#define REG_VIP_ACE_63_L (REG_VIP_ACE_BASE + 0xC6) ++#define REG_VIP_ACE_63_H (REG_VIP_ACE_BASE + 0xC7) ++#define REG_VIP_ACE_64_L (REG_VIP_ACE_BASE + 0xC8) ++#define REG_VIP_ACE_64_H (REG_VIP_ACE_BASE + 0xC9) ++#define REG_VIP_ACE_65_L (REG_VIP_ACE_BASE + 0xCA) ++#define REG_VIP_ACE_65_H (REG_VIP_ACE_BASE + 0xCB) ++#define REG_VIP_ACE_66_L (REG_VIP_ACE_BASE + 0xCC) ++#define REG_VIP_ACE_66_H (REG_VIP_ACE_BASE + 0xCD) ++#define REG_VIP_ACE_67_L (REG_VIP_ACE_BASE + 0xCE) ++#define REG_VIP_ACE_67_H (REG_VIP_ACE_BASE + 0xCF) ++#define REG_VIP_ACE_68_L (REG_VIP_ACE_BASE + 0xD0) ++#define REG_VIP_ACE_68_H (REG_VIP_ACE_BASE + 0xD1) ++#define REG_VIP_ACE_69_L (REG_VIP_ACE_BASE + 0xD2) ++#define REG_VIP_ACE_69_H (REG_VIP_ACE_BASE + 0xD3) ++#define REG_VIP_ACE_6A_L (REG_VIP_ACE_BASE + 0xD4) ++#define REG_VIP_ACE_6A_H (REG_VIP_ACE_BASE + 0xD5) ++#define REG_VIP_ACE_6B_L (REG_VIP_ACE_BASE + 0xD6) ++#define REG_VIP_ACE_6B_H (REG_VIP_ACE_BASE + 0xD7) ++#define REG_VIP_ACE_6C_L (REG_VIP_ACE_BASE + 0xD8) ++#define REG_VIP_ACE_6C_H (REG_VIP_ACE_BASE + 0xD9) ++#define REG_VIP_ACE_6D_L (REG_VIP_ACE_BASE + 0xDA) ++#define REG_VIP_ACE_6D_H (REG_VIP_ACE_BASE + 0xDB) ++#define REG_VIP_ACE_6E_L (REG_VIP_ACE_BASE + 0xDC) ++#define REG_VIP_ACE_6E_H (REG_VIP_ACE_BASE + 0xDD) ++#define REG_VIP_ACE_6F_L (REG_VIP_ACE_BASE + 0xDE) ++#define REG_VIP_ACE_6F_H (REG_VIP_ACE_BASE + 0xDF) ++#define REG_VIP_ACE_70_L (REG_VIP_ACE_BASE + 0xE0) ++#define REG_VIP_ACE_70_H (REG_VIP_ACE_BASE + 0xE1) ++#define REG_VIP_ACE_71_L (REG_VIP_ACE_BASE + 0xE2) ++#define REG_VIP_ACE_71_H (REG_VIP_ACE_BASE + 0xE3) ++#define REG_VIP_ACE_72_L (REG_VIP_ACE_BASE + 0xE4) ++#define REG_VIP_ACE_72_H (REG_VIP_ACE_BASE + 0xE5) ++#define REG_VIP_ACE_73_L (REG_VIP_ACE_BASE + 0xE6) ++#define REG_VIP_ACE_73_H (REG_VIP_ACE_BASE + 0xE7) ++#define REG_VIP_ACE_74_L (REG_VIP_ACE_BASE + 0xE8) ++#define REG_VIP_ACE_74_H (REG_VIP_ACE_BASE + 0xE9) ++#define REG_VIP_ACE_75_L (REG_VIP_ACE_BASE + 0xEA) ++#define REG_VIP_ACE_75_H (REG_VIP_ACE_BASE + 0xEB) ++#define REG_VIP_ACE_76_L (REG_VIP_ACE_BASE + 0xEC) ++#define REG_VIP_ACE_76_H (REG_VIP_ACE_BASE + 0xED) ++#define REG_VIP_ACE_77_L (REG_VIP_ACE_BASE + 0xEE) ++#define REG_VIP_ACE_77_H (REG_VIP_ACE_BASE + 0xEF) ++#define REG_VIP_ACE_78_L (REG_VIP_ACE_BASE + 0xF0) ++#define REG_VIP_ACE_78_H (REG_VIP_ACE_BASE + 0xF1) ++#define REG_VIP_ACE_79_L (REG_VIP_ACE_BASE + 0xF2) ++#define REG_VIP_ACE_79_H (REG_VIP_ACE_BASE + 0xF3) ++#define REG_VIP_ACE_7A_L (REG_VIP_ACE_BASE + 0xF4) ++#define REG_VIP_ACE_7A_H (REG_VIP_ACE_BASE + 0xF5) ++#define REG_VIP_ACE_7B_L (REG_VIP_ACE_BASE + 0xF6) ++#define REG_VIP_ACE_7B_H (REG_VIP_ACE_BASE + 0xF7) ++#define REG_VIP_ACE_7C_L (REG_VIP_ACE_BASE + 0xF8) ++#define REG_VIP_ACE_7C_H (REG_VIP_ACE_BASE + 0xF9) ++#define REG_VIP_ACE_7D_L (REG_VIP_ACE_BASE + 0xFA) ++#define REG_VIP_ACE_7D_H (REG_VIP_ACE_BASE + 0xFB) ++#define REG_VIP_ACE_7E_L (REG_VIP_ACE_BASE + 0xFC) ++#define REG_VIP_ACE_7E_H (REG_VIP_ACE_BASE + 0xFD) ++#define REG_VIP_ACE_7F_L (REG_VIP_ACE_BASE + 0xFE) ++#define REG_VIP_ACE_7F_H (REG_VIP_ACE_BASE + 0xFF) ++ ++ ++#define REG_VIP_PK_00_L (REG_VIP_PK_BASE + 0x00) ++#define REG_VIP_PK_00_H (REG_VIP_PK_BASE + 0x01) ++#define REG_VIP_PK_01_L (REG_VIP_PK_BASE + 0x02) ++#define REG_VIP_PK_01_H (REG_VIP_PK_BASE + 0x03) ++#define REG_VIP_PK_02_L (REG_VIP_PK_BASE + 0x04) ++#define REG_VIP_PK_02_H (REG_VIP_PK_BASE + 0x05) ++#define REG_VIP_PK_03_L (REG_VIP_PK_BASE + 0x06) ++#define REG_VIP_PK_03_H (REG_VIP_PK_BASE + 0x07) ++#define REG_VIP_PK_04_L (REG_VIP_PK_BASE + 0x08) ++#define REG_VIP_PK_04_H (REG_VIP_PK_BASE + 0x09) ++#define REG_VIP_PK_05_L (REG_VIP_PK_BASE + 0x0A) ++#define REG_VIP_PK_05_H (REG_VIP_PK_BASE + 0x0B) ++#define REG_VIP_PK_06_L (REG_VIP_PK_BASE + 0x0C) ++#define REG_VIP_PK_06_H (REG_VIP_PK_BASE + 0x0D) ++#define REG_VIP_PK_07_L (REG_VIP_PK_BASE + 0x0E) ++#define REG_VIP_PK_07_H (REG_VIP_PK_BASE + 0x0F) ++#define REG_VIP_PK_08_L (REG_VIP_PK_BASE + 0x10) ++#define REG_VIP_PK_08_H (REG_VIP_PK_BASE + 0x11) ++#define REG_VIP_PK_09_L (REG_VIP_PK_BASE + 0x12) ++#define REG_VIP_PK_09_H (REG_VIP_PK_BASE + 0x13) ++#define REG_VIP_PK_0A_L (REG_VIP_PK_BASE + 0x14) ++#define REG_VIP_PK_0A_H (REG_VIP_PK_BASE + 0x15) ++#define REG_VIP_PK_0B_L (REG_VIP_PK_BASE + 0x16) ++#define REG_VIP_PK_0B_H (REG_VIP_PK_BASE + 0x17) ++#define REG_VIP_PK_0C_L (REG_VIP_PK_BASE + 0x18) ++#define REG_VIP_PK_0C_H (REG_VIP_PK_BASE + 0x19) ++#define REG_VIP_PK_0D_L (REG_VIP_PK_BASE + 0x1A) ++#define REG_VIP_PK_0D_H (REG_VIP_PK_BASE + 0x1B) ++#define REG_VIP_PK_0E_L (REG_VIP_PK_BASE + 0x1C) ++#define REG_VIP_PK_0E_H (REG_VIP_PK_BASE + 0x1D) ++#define REG_VIP_PK_0F_L (REG_VIP_PK_BASE + 0x1E) ++#define REG_VIP_PK_0F_H (REG_VIP_PK_BASE + 0x1F) ++#define REG_VIP_PK_10_L (REG_VIP_PK_BASE + 0x20) ++#define REG_VIP_PK_10_H (REG_VIP_PK_BASE + 0x21) ++#define REG_VIP_PK_11_L (REG_VIP_PK_BASE + 0x22) ++#define REG_VIP_PK_11_H (REG_VIP_PK_BASE + 0x23) ++#define REG_VIP_PK_12_L (REG_VIP_PK_BASE + 0x24) ++#define REG_VIP_PK_12_H (REG_VIP_PK_BASE + 0x25) ++#define REG_VIP_PK_13_L (REG_VIP_PK_BASE + 0x26) ++#define REG_VIP_PK_13_H (REG_VIP_PK_BASE + 0x27) ++#define REG_VIP_PK_14_L (REG_VIP_PK_BASE + 0x28) ++#define REG_VIP_PK_14_H (REG_VIP_PK_BASE + 0x29) ++#define REG_VIP_PK_15_L (REG_VIP_PK_BASE + 0x2A) ++#define REG_VIP_PK_15_H (REG_VIP_PK_BASE + 0x2B) ++#define REG_VIP_PK_16_L (REG_VIP_PK_BASE + 0x2C) ++#define REG_VIP_PK_16_H (REG_VIP_PK_BASE + 0x2D) ++#define REG_VIP_PK_17_L (REG_VIP_PK_BASE + 0x2E) ++#define REG_VIP_PK_17_H (REG_VIP_PK_BASE + 0x2F) ++#define REG_VIP_PK_18_L (REG_VIP_PK_BASE + 0x30) ++#define REG_VIP_PK_18_H (REG_VIP_PK_BASE + 0x31) ++#define REG_VIP_PK_19_L (REG_VIP_PK_BASE + 0x32) ++#define REG_VIP_PK_19_H (REG_VIP_PK_BASE + 0x33) ++#define REG_VIP_PK_1A_L (REG_VIP_PK_BASE + 0x34) ++#define REG_VIP_PK_1A_H (REG_VIP_PK_BASE + 0x35) ++#define REG_VIP_PK_1B_L (REG_VIP_PK_BASE + 0x36) ++#define REG_VIP_PK_1B_H (REG_VIP_PK_BASE + 0x37) ++#define REG_VIP_PK_1C_L (REG_VIP_PK_BASE + 0x38) ++#define REG_VIP_PK_1C_H (REG_VIP_PK_BASE + 0x39) ++#define REG_VIP_PK_1D_L (REG_VIP_PK_BASE + 0x3A) ++#define REG_VIP_PK_1D_H (REG_VIP_PK_BASE + 0x3B) ++#define REG_VIP_PK_1E_L (REG_VIP_PK_BASE + 0x3C) ++#define REG_VIP_PK_1E_H (REG_VIP_PK_BASE + 0x3D) ++#define REG_VIP_PK_1F_L (REG_VIP_PK_BASE + 0x3E) ++#define REG_VIP_PK_1F_H (REG_VIP_PK_BASE + 0x3F) ++#define REG_VIP_PK_20_L (REG_VIP_PK_BASE + 0x40) ++#define REG_VIP_PK_20_H (REG_VIP_PK_BASE + 0x41) ++#define REG_VIP_PK_21_L (REG_VIP_PK_BASE + 0x42) ++#define REG_VIP_PK_21_H (REG_VIP_PK_BASE + 0x43) ++#define REG_VIP_PK_22_L (REG_VIP_PK_BASE + 0x44) ++#define REG_VIP_PK_22_H (REG_VIP_PK_BASE + 0x45) ++#define REG_VIP_PK_23_L (REG_VIP_PK_BASE + 0x46) ++#define REG_VIP_PK_23_H (REG_VIP_PK_BASE + 0x47) ++#define REG_VIP_PK_24_L (REG_VIP_PK_BASE + 0x48) ++#define REG_VIP_PK_24_H (REG_VIP_PK_BASE + 0x49) ++#define REG_VIP_PK_25_L (REG_VIP_PK_BASE + 0x4A) ++#define REG_VIP_PK_25_H (REG_VIP_PK_BASE + 0x4B) ++#define REG_VIP_PK_26_L (REG_VIP_PK_BASE + 0x4C) ++#define REG_VIP_PK_26_H (REG_VIP_PK_BASE + 0x4D) ++#define REG_VIP_PK_27_L (REG_VIP_PK_BASE + 0x4E) ++#define REG_VIP_PK_27_H (REG_VIP_PK_BASE + 0x4F) ++#define REG_VIP_PK_28_L (REG_VIP_PK_BASE + 0x50) ++#define REG_VIP_PK_28_H (REG_VIP_PK_BASE + 0x51) ++#define REG_VIP_PK_29_L (REG_VIP_PK_BASE + 0x52) ++#define REG_VIP_PK_29_H (REG_VIP_PK_BASE + 0x53) ++#define REG_VIP_PK_2A_L (REG_VIP_PK_BASE + 0x54) ++#define REG_VIP_PK_2A_H (REG_VIP_PK_BASE + 0x55) ++#define REG_VIP_PK_2B_L (REG_VIP_PK_BASE + 0x56) ++#define REG_VIP_PK_2B_H (REG_VIP_PK_BASE + 0x57) ++#define REG_VIP_PK_2C_L (REG_VIP_PK_BASE + 0x58) ++#define REG_VIP_PK_2C_H (REG_VIP_PK_BASE + 0x59) ++#define REG_VIP_PK_2D_L (REG_VIP_PK_BASE + 0x5A) ++#define REG_VIP_PK_2D_H (REG_VIP_PK_BASE + 0x5B) ++#define REG_VIP_PK_2E_L (REG_VIP_PK_BASE + 0x5C) ++#define REG_VIP_PK_2E_H (REG_VIP_PK_BASE + 0x5D) ++#define REG_VIP_PK_2F_L (REG_VIP_PK_BASE + 0x5E) ++#define REG_VIP_PK_2F_H (REG_VIP_PK_BASE + 0x5F) ++#define REG_VIP_PK_30_L (REG_VIP_PK_BASE + 0x60) ++#define REG_VIP_PK_30_H (REG_VIP_PK_BASE + 0x61) ++#define REG_VIP_PK_31_L (REG_VIP_PK_BASE + 0x62) ++#define REG_VIP_PK_31_H (REG_VIP_PK_BASE + 0x63) ++#define REG_VIP_PK_32_L (REG_VIP_PK_BASE + 0x64) ++#define REG_VIP_PK_32_H (REG_VIP_PK_BASE + 0x65) ++#define REG_VIP_PK_33_L (REG_VIP_PK_BASE + 0x66) ++#define REG_VIP_PK_33_H (REG_VIP_PK_BASE + 0x67) ++#define REG_VIP_PK_34_L (REG_VIP_PK_BASE + 0x68) ++#define REG_VIP_PK_34_H (REG_VIP_PK_BASE + 0x69) ++#define REG_VIP_PK_35_L (REG_VIP_PK_BASE + 0x6A) ++#define REG_VIP_PK_35_H (REG_VIP_PK_BASE + 0x6B) ++#define REG_VIP_PK_36_L (REG_VIP_PK_BASE + 0x6C) ++#define REG_VIP_PK_36_H (REG_VIP_PK_BASE + 0x6D) ++#define REG_VIP_PK_37_L (REG_VIP_PK_BASE + 0x6E) ++#define REG_VIP_PK_37_H (REG_VIP_PK_BASE + 0x6F) ++#define REG_VIP_PK_38_L (REG_VIP_PK_BASE + 0x70) ++#define REG_VIP_PK_38_H (REG_VIP_PK_BASE + 0x71) ++#define REG_VIP_PK_39_L (REG_VIP_PK_BASE + 0x72) ++#define REG_VIP_PK_39_H (REG_VIP_PK_BASE + 0x73) ++#define REG_VIP_PK_3A_L (REG_VIP_PK_BASE + 0x74) ++#define REG_VIP_PK_3A_H (REG_VIP_PK_BASE + 0x75) ++#define REG_VIP_PK_3B_L (REG_VIP_PK_BASE + 0x76) ++#define REG_VIP_PK_3B_H (REG_VIP_PK_BASE + 0x77) ++#define REG_VIP_PK_3C_L (REG_VIP_PK_BASE + 0x78) ++#define REG_VIP_PK_3C_H (REG_VIP_PK_BASE + 0x79) ++#define REG_VIP_PK_3D_L (REG_VIP_PK_BASE + 0x7A) ++#define REG_VIP_PK_3D_H (REG_VIP_PK_BASE + 0x7B) ++#define REG_VIP_PK_3E_L (REG_VIP_PK_BASE + 0x7C) ++#define REG_VIP_PK_3E_H (REG_VIP_PK_BASE + 0x7D) ++#define REG_VIP_PK_3F_L (REG_VIP_PK_BASE + 0x7E) ++#define REG_VIP_PK_3F_H (REG_VIP_PK_BASE + 0x7F) ++#define REG_VIP_PK_40_L (REG_VIP_PK_BASE + 0x80) ++#define REG_VIP_PK_40_H (REG_VIP_PK_BASE + 0x81) ++#define REG_VIP_PK_41_L (REG_VIP_PK_BASE + 0x82) ++#define REG_VIP_PK_41_H (REG_VIP_PK_BASE + 0x83) ++#define REG_VIP_PK_42_L (REG_VIP_PK_BASE + 0x84) ++#define REG_VIP_PK_42_H (REG_VIP_PK_BASE + 0x85) ++#define REG_VIP_PK_43_L (REG_VIP_PK_BASE + 0x86) ++#define REG_VIP_PK_43_H (REG_VIP_PK_BASE + 0x87) ++#define REG_VIP_PK_44_L (REG_VIP_PK_BASE + 0x88) ++#define REG_VIP_PK_44_H (REG_VIP_PK_BASE + 0x89) ++#define REG_VIP_PK_45_L (REG_VIP_PK_BASE + 0x8A) ++#define REG_VIP_PK_45_H (REG_VIP_PK_BASE + 0x8B) ++#define REG_VIP_PK_46_L (REG_VIP_PK_BASE + 0x8C) ++#define REG_VIP_PK_46_H (REG_VIP_PK_BASE + 0x8D) ++#define REG_VIP_PK_47_L (REG_VIP_PK_BASE + 0x8E) ++#define REG_VIP_PK_47_H (REG_VIP_PK_BASE + 0x8F) ++#define REG_VIP_PK_48_L (REG_VIP_PK_BASE + 0x90) ++#define REG_VIP_PK_48_H (REG_VIP_PK_BASE + 0x91) ++#define REG_VIP_PK_49_L (REG_VIP_PK_BASE + 0x92) ++#define REG_VIP_PK_49_H (REG_VIP_PK_BASE + 0x93) ++#define REG_VIP_PK_4A_L (REG_VIP_PK_BASE + 0x94) ++#define REG_VIP_PK_4A_H (REG_VIP_PK_BASE + 0x95) ++#define REG_VIP_PK_4B_L (REG_VIP_PK_BASE + 0x96) ++#define REG_VIP_PK_4B_H (REG_VIP_PK_BASE + 0x97) ++#define REG_VIP_PK_4C_L (REG_VIP_PK_BASE + 0x98) ++#define REG_VIP_PK_4C_H (REG_VIP_PK_BASE + 0x99) ++#define REG_VIP_PK_4D_L (REG_VIP_PK_BASE + 0x9A) ++#define REG_VIP_PK_4D_H (REG_VIP_PK_BASE + 0x9B) ++#define REG_VIP_PK_4E_L (REG_VIP_PK_BASE + 0x9C) ++#define REG_VIP_PK_4E_H (REG_VIP_PK_BASE + 0x9D) ++#define REG_VIP_PK_4F_L (REG_VIP_PK_BASE + 0x9E) ++#define REG_VIP_PK_4F_H (REG_VIP_PK_BASE + 0x9F) ++#define REG_VIP_PK_50_L (REG_VIP_PK_BASE + 0xA0) ++#define REG_VIP_PK_50_H (REG_VIP_PK_BASE + 0xA1) ++#define REG_VIP_PK_51_L (REG_VIP_PK_BASE + 0xA2) ++#define REG_VIP_PK_51_H (REG_VIP_PK_BASE + 0xA3) ++#define REG_VIP_PK_52_L (REG_VIP_PK_BASE + 0xA4) ++#define REG_VIP_PK_52_H (REG_VIP_PK_BASE + 0xA5) ++#define REG_VIP_PK_53_L (REG_VIP_PK_BASE + 0xA6) ++#define REG_VIP_PK_53_H (REG_VIP_PK_BASE + 0xA7) ++#define REG_VIP_PK_54_L (REG_VIP_PK_BASE + 0xA8) ++#define REG_VIP_PK_54_H (REG_VIP_PK_BASE + 0xA9) ++#define REG_VIP_PK_55_L (REG_VIP_PK_BASE + 0xAA) ++#define REG_VIP_PK_55_H (REG_VIP_PK_BASE + 0xAB) ++#define REG_VIP_PK_56_L (REG_VIP_PK_BASE + 0xAC) ++#define REG_VIP_PK_56_H (REG_VIP_PK_BASE + 0xAD) ++#define REG_VIP_PK_57_L (REG_VIP_PK_BASE + 0xAE) ++#define REG_VIP_PK_57_H (REG_VIP_PK_BASE + 0xAF) ++#define REG_VIP_PK_58_L (REG_VIP_PK_BASE + 0xB0) ++#define REG_VIP_PK_58_H (REG_VIP_PK_BASE + 0xB1) ++#define REG_VIP_PK_59_L (REG_VIP_PK_BASE + 0xB2) ++#define REG_VIP_PK_59_H (REG_VIP_PK_BASE + 0xB3) ++#define REG_VIP_PK_5A_L (REG_VIP_PK_BASE + 0xB4) ++#define REG_VIP_PK_5A_H (REG_VIP_PK_BASE + 0xB5) ++#define REG_VIP_PK_5B_L (REG_VIP_PK_BASE + 0xB6) ++#define REG_VIP_PK_5B_H (REG_VIP_PK_BASE + 0xB7) ++#define REG_VIP_PK_5C_L (REG_VIP_PK_BASE + 0xB8) ++#define REG_VIP_PK_5C_H (REG_VIP_PK_BASE + 0xB9) ++#define REG_VIP_PK_5D_L (REG_VIP_PK_BASE + 0xBA) ++#define REG_VIP_PK_5D_H (REG_VIP_PK_BASE + 0xBB) ++#define REG_VIP_PK_5E_L (REG_VIP_PK_BASE + 0xBC) ++#define REG_VIP_PK_5E_H (REG_VIP_PK_BASE + 0xBD) ++#define REG_VIP_PK_5F_L (REG_VIP_PK_BASE + 0xBE) ++#define REG_VIP_PK_5F_H (REG_VIP_PK_BASE + 0xBF) ++#define REG_VIP_PK_60_L (REG_VIP_PK_BASE + 0xC0) ++#define REG_VIP_PK_60_H (REG_VIP_PK_BASE + 0xC1) ++#define REG_VIP_PK_61_L (REG_VIP_PK_BASE + 0xC2) ++#define REG_VIP_PK_61_H (REG_VIP_PK_BASE + 0xC3) ++#define REG_VIP_PK_62_L (REG_VIP_PK_BASE + 0xC4) ++#define REG_VIP_PK_62_H (REG_VIP_PK_BASE + 0xC5) ++#define REG_VIP_PK_63_L (REG_VIP_PK_BASE + 0xC6) ++#define REG_VIP_PK_63_H (REG_VIP_PK_BASE + 0xC7) ++#define REG_VIP_PK_64_L (REG_VIP_PK_BASE + 0xC8) ++#define REG_VIP_PK_64_H (REG_VIP_PK_BASE + 0xC9) ++#define REG_VIP_PK_65_L (REG_VIP_PK_BASE + 0xCA) ++#define REG_VIP_PK_65_H (REG_VIP_PK_BASE + 0xCB) ++#define REG_VIP_PK_66_L (REG_VIP_PK_BASE + 0xCC) ++#define REG_VIP_PK_66_H (REG_VIP_PK_BASE + 0xCD) ++#define REG_VIP_PK_67_L (REG_VIP_PK_BASE + 0xCE) ++#define REG_VIP_PK_67_H (REG_VIP_PK_BASE + 0xCF) ++#define REG_VIP_PK_68_L (REG_VIP_PK_BASE + 0xD0) ++#define REG_VIP_PK_68_H (REG_VIP_PK_BASE + 0xD1) ++#define REG_VIP_PK_69_L (REG_VIP_PK_BASE + 0xD2) ++#define REG_VIP_PK_69_H (REG_VIP_PK_BASE + 0xD3) ++#define REG_VIP_PK_6A_L (REG_VIP_PK_BASE + 0xD4) ++#define REG_VIP_PK_6A_H (REG_VIP_PK_BASE + 0xD5) ++#define REG_VIP_PK_6B_L (REG_VIP_PK_BASE + 0xD6) ++#define REG_VIP_PK_6B_H (REG_VIP_PK_BASE + 0xD7) ++#define REG_VIP_PK_6C_L (REG_VIP_PK_BASE + 0xD8) ++#define REG_VIP_PK_6C_H (REG_VIP_PK_BASE + 0xD9) ++#define REG_VIP_PK_6D_L (REG_VIP_PK_BASE + 0xDA) ++#define REG_VIP_PK_6D_H (REG_VIP_PK_BASE + 0xDB) ++#define REG_VIP_PK_6E_L (REG_VIP_PK_BASE + 0xDC) ++#define REG_VIP_PK_6E_H (REG_VIP_PK_BASE + 0xDD) ++#define REG_VIP_PK_6F_L (REG_VIP_PK_BASE + 0xDE) ++#define REG_VIP_PK_6F_H (REG_VIP_PK_BASE + 0xDF) ++#define REG_VIP_PK_70_L (REG_VIP_PK_BASE + 0xE0) ++#define REG_VIP_PK_70_H (REG_VIP_PK_BASE + 0xE1) ++#define REG_VIP_PK_71_L (REG_VIP_PK_BASE + 0xE2) ++#define REG_VIP_PK_71_H (REG_VIP_PK_BASE + 0xE3) ++#define REG_VIP_PK_72_L (REG_VIP_PK_BASE + 0xE4) ++#define REG_VIP_PK_72_H (REG_VIP_PK_BASE + 0xE5) ++#define REG_VIP_PK_73_L (REG_VIP_PK_BASE + 0xE6) ++#define REG_VIP_PK_73_H (REG_VIP_PK_BASE + 0xE7) ++#define REG_VIP_PK_74_L (REG_VIP_PK_BASE + 0xE8) ++#define REG_VIP_PK_74_H (REG_VIP_PK_BASE + 0xE9) ++#define REG_VIP_PK_75_L (REG_VIP_PK_BASE + 0xEA) ++#define REG_VIP_PK_75_H (REG_VIP_PK_BASE + 0xEB) ++#define REG_VIP_PK_76_L (REG_VIP_PK_BASE + 0xEC) ++#define REG_VIP_PK_76_H (REG_VIP_PK_BASE + 0xED) ++#define REG_VIP_PK_77_L (REG_VIP_PK_BASE + 0xEE) ++#define REG_VIP_PK_77_H (REG_VIP_PK_BASE + 0xEF) ++#define REG_VIP_PK_78_L (REG_VIP_PK_BASE + 0xF0) ++#define REG_VIP_PK_78_H (REG_VIP_PK_BASE + 0xF1) ++#define REG_VIP_PK_79_L (REG_VIP_PK_BASE + 0xF2) ++#define REG_VIP_PK_79_H (REG_VIP_PK_BASE + 0xF3) ++#define REG_VIP_PK_7A_L (REG_VIP_PK_BASE + 0xF4) ++#define REG_VIP_PK_7A_H (REG_VIP_PK_BASE + 0xF5) ++#define REG_VIP_PK_7B_L (REG_VIP_PK_BASE + 0xF6) ++#define REG_VIP_PK_7B_H (REG_VIP_PK_BASE + 0xF7) ++#define REG_VIP_PK_7C_L (REG_VIP_PK_BASE + 0xF8) ++#define REG_VIP_PK_7C_H (REG_VIP_PK_BASE + 0xF9) ++#define REG_VIP_PK_7D_L (REG_VIP_PK_BASE + 0xFA) ++#define REG_VIP_PK_7D_H (REG_VIP_PK_BASE + 0xFB) ++#define REG_VIP_PK_7E_L (REG_VIP_PK_BASE + 0xFC) ++#define REG_VIP_PK_7E_H (REG_VIP_PK_BASE + 0xFD) ++#define REG_VIP_PK_7F_L (REG_VIP_PK_BASE + 0xFE) ++#define REG_VIP_PK_7F_H (REG_VIP_PK_BASE + 0xFF) ++ ++#define REG_VIP_DLC_00_L (REG_VIP_DLC_BASE + 0x00) ++#define REG_VIP_DLC_00_H (REG_VIP_DLC_BASE + 0x01) ++#define REG_VIP_DLC_01_L (REG_VIP_DLC_BASE + 0x02) ++#define REG_VIP_DLC_01_H (REG_VIP_DLC_BASE + 0x03) ++#define REG_VIP_DLC_02_L (REG_VIP_DLC_BASE + 0x04) ++#define REG_VIP_DLC_02_H (REG_VIP_DLC_BASE + 0x05) ++#define REG_VIP_DLC_03_L (REG_VIP_DLC_BASE + 0x06) ++#define REG_VIP_DLC_03_H (REG_VIP_DLC_BASE + 0x07) ++#define REG_VIP_DLC_04_L (REG_VIP_DLC_BASE + 0x08) ++#define REG_VIP_DLC_04_H (REG_VIP_DLC_BASE + 0x09) ++#define REG_VIP_DLC_05_L (REG_VIP_DLC_BASE + 0x0A) ++#define REG_VIP_DLC_05_H (REG_VIP_DLC_BASE + 0x0B) ++#define REG_VIP_DLC_06_L (REG_VIP_DLC_BASE + 0x0C) ++#define REG_VIP_DLC_06_H (REG_VIP_DLC_BASE + 0x0D) ++#define REG_VIP_DLC_07_L (REG_VIP_DLC_BASE + 0x0E) ++#define REG_VIP_DLC_07_H (REG_VIP_DLC_BASE + 0x0F) ++#define REG_VIP_DLC_08_L (REG_VIP_DLC_BASE + 0x10) ++#define REG_VIP_DLC_08_H (REG_VIP_DLC_BASE + 0x11) ++#define REG_VIP_DLC_09_L (REG_VIP_DLC_BASE + 0x12) ++#define REG_VIP_DLC_09_H (REG_VIP_DLC_BASE + 0x13) ++#define REG_VIP_DLC_0A_L (REG_VIP_DLC_BASE + 0x14) ++#define REG_VIP_DLC_0A_H (REG_VIP_DLC_BASE + 0x15) ++#define REG_VIP_DLC_0B_L (REG_VIP_DLC_BASE + 0x16) ++#define REG_VIP_DLC_0B_H (REG_VIP_DLC_BASE + 0x17) ++#define REG_VIP_DLC_0C_L (REG_VIP_DLC_BASE + 0x18) ++#define REG_VIP_DLC_0C_H (REG_VIP_DLC_BASE + 0x19) ++#define REG_VIP_DLC_0D_L (REG_VIP_DLC_BASE + 0x1A) ++#define REG_VIP_DLC_0D_H (REG_VIP_DLC_BASE + 0x1B) ++#define REG_VIP_DLC_0E_L (REG_VIP_DLC_BASE + 0x1C) ++#define REG_VIP_DLC_0E_H (REG_VIP_DLC_BASE + 0x1D) ++#define REG_VIP_DLC_0F_L (REG_VIP_DLC_BASE + 0x1E) ++#define REG_VIP_DLC_0F_H (REG_VIP_DLC_BASE + 0x1F) ++#define REG_VIP_DLC_10_L (REG_VIP_DLC_BASE + 0x20) ++#define REG_VIP_DLC_10_H (REG_VIP_DLC_BASE + 0x21) ++#define REG_VIP_DLC_11_L (REG_VIP_DLC_BASE + 0x22) ++#define REG_VIP_DLC_11_H (REG_VIP_DLC_BASE + 0x23) ++#define REG_VIP_DLC_12_L (REG_VIP_DLC_BASE + 0x24) ++#define REG_VIP_DLC_12_H (REG_VIP_DLC_BASE + 0x25) ++#define REG_VIP_DLC_13_L (REG_VIP_DLC_BASE + 0x26) ++#define REG_VIP_DLC_13_H (REG_VIP_DLC_BASE + 0x27) ++#define REG_VIP_DLC_14_L (REG_VIP_DLC_BASE + 0x28) ++#define REG_VIP_DLC_14_H (REG_VIP_DLC_BASE + 0x29) ++#define REG_VIP_DLC_15_L (REG_VIP_DLC_BASE + 0x2A) ++#define REG_VIP_DLC_15_H (REG_VIP_DLC_BASE + 0x2B) ++#define REG_VIP_DLC_16_L (REG_VIP_DLC_BASE + 0x2C) ++#define REG_VIP_DLC_16_H (REG_VIP_DLC_BASE + 0x2D) ++#define REG_VIP_DLC_17_L (REG_VIP_DLC_BASE + 0x2E) ++#define REG_VIP_DLC_17_H (REG_VIP_DLC_BASE + 0x2F) ++#define REG_VIP_DLC_18_L (REG_VIP_DLC_BASE + 0x30) ++#define REG_VIP_DLC_18_H (REG_VIP_DLC_BASE + 0x31) ++#define REG_VIP_DLC_19_L (REG_VIP_DLC_BASE + 0x32) ++#define REG_VIP_DLC_19_H (REG_VIP_DLC_BASE + 0x33) ++#define REG_VIP_DLC_1A_L (REG_VIP_DLC_BASE + 0x34) ++#define REG_VIP_DLC_1A_H (REG_VIP_DLC_BASE + 0x35) ++#define REG_VIP_DLC_1B_L (REG_VIP_DLC_BASE + 0x36) ++#define REG_VIP_DLC_1B_H (REG_VIP_DLC_BASE + 0x37) ++#define REG_VIP_DLC_1C_L (REG_VIP_DLC_BASE + 0x38) ++#define REG_VIP_DLC_1C_H (REG_VIP_DLC_BASE + 0x39) ++#define REG_VIP_DLC_1D_L (REG_VIP_DLC_BASE + 0x3A) ++#define REG_VIP_DLC_1D_H (REG_VIP_DLC_BASE + 0x3B) ++#define REG_VIP_DLC_1E_L (REG_VIP_DLC_BASE + 0x3C) ++#define REG_VIP_DLC_1E_H (REG_VIP_DLC_BASE + 0x3D) ++#define REG_VIP_DLC_1F_L (REG_VIP_DLC_BASE + 0x3E) ++#define REG_VIP_DLC_1F_H (REG_VIP_DLC_BASE + 0x3F) ++#define REG_VIP_DLC_20_L (REG_VIP_DLC_BASE + 0x40) ++#define REG_VIP_DLC_20_H (REG_VIP_DLC_BASE + 0x41) ++#define REG_VIP_DLC_21_L (REG_VIP_DLC_BASE + 0x42) ++#define REG_VIP_DLC_21_H (REG_VIP_DLC_BASE + 0x43) ++#define REG_VIP_DLC_22_L (REG_VIP_DLC_BASE + 0x44) ++#define REG_VIP_DLC_22_H (REG_VIP_DLC_BASE + 0x45) ++#define REG_VIP_DLC_23_L (REG_VIP_DLC_BASE + 0x46) ++#define REG_VIP_DLC_23_H (REG_VIP_DLC_BASE + 0x47) ++#define REG_VIP_DLC_24_L (REG_VIP_DLC_BASE + 0x48) ++#define REG_VIP_DLC_24_H (REG_VIP_DLC_BASE + 0x49) ++#define REG_VIP_DLC_25_L (REG_VIP_DLC_BASE + 0x4A) ++#define REG_VIP_DLC_25_H (REG_VIP_DLC_BASE + 0x4B) ++#define REG_VIP_DLC_26_L (REG_VIP_DLC_BASE + 0x4C) ++#define REG_VIP_DLC_26_H (REG_VIP_DLC_BASE + 0x4D) ++#define REG_VIP_DLC_27_L (REG_VIP_DLC_BASE + 0x4E) ++#define REG_VIP_DLC_27_H (REG_VIP_DLC_BASE + 0x4F) ++#define REG_VIP_DLC_28_L (REG_VIP_DLC_BASE + 0x50) ++#define REG_VIP_DLC_28_H (REG_VIP_DLC_BASE + 0x51) ++#define REG_VIP_DLC_29_L (REG_VIP_DLC_BASE + 0x52) ++#define REG_VIP_DLC_29_H (REG_VIP_DLC_BASE + 0x53) ++#define REG_VIP_DLC_2A_L (REG_VIP_DLC_BASE + 0x54) ++#define REG_VIP_DLC_2A_H (REG_VIP_DLC_BASE + 0x55) ++#define REG_VIP_DLC_2B_L (REG_VIP_DLC_BASE + 0x56) ++#define REG_VIP_DLC_2B_H (REG_VIP_DLC_BASE + 0x57) ++#define REG_VIP_DLC_2C_L (REG_VIP_DLC_BASE + 0x58) ++#define REG_VIP_DLC_2C_H (REG_VIP_DLC_BASE + 0x59) ++#define REG_VIP_DLC_2D_L (REG_VIP_DLC_BASE + 0x5A) ++#define REG_VIP_DLC_2D_H (REG_VIP_DLC_BASE + 0x5B) ++#define REG_VIP_DLC_2E_L (REG_VIP_DLC_BASE + 0x5C) ++#define REG_VIP_DLC_2E_H (REG_VIP_DLC_BASE + 0x5D) ++#define REG_VIP_DLC_2F_L (REG_VIP_DLC_BASE + 0x5E) ++#define REG_VIP_DLC_2F_H (REG_VIP_DLC_BASE + 0x5F) ++#define REG_VIP_DLC_30_L (REG_VIP_DLC_BASE + 0x60) ++#define REG_VIP_DLC_30_H (REG_VIP_DLC_BASE + 0x61) ++#define REG_VIP_DLC_31_L (REG_VIP_DLC_BASE + 0x62) ++#define REG_VIP_DLC_31_H (REG_VIP_DLC_BASE + 0x63) ++#define REG_VIP_DLC_32_L (REG_VIP_DLC_BASE + 0x64) ++#define REG_VIP_DLC_32_H (REG_VIP_DLC_BASE + 0x65) ++#define REG_VIP_DLC_33_L (REG_VIP_DLC_BASE + 0x66) ++#define REG_VIP_DLC_33_H (REG_VIP_DLC_BASE + 0x67) ++#define REG_VIP_DLC_34_L (REG_VIP_DLC_BASE + 0x68) ++#define REG_VIP_DLC_34_H (REG_VIP_DLC_BASE + 0x69) ++#define REG_VIP_DLC_35_L (REG_VIP_DLC_BASE + 0x6A) ++#define REG_VIP_DLC_35_H (REG_VIP_DLC_BASE + 0x6B) ++#define REG_VIP_DLC_36_L (REG_VIP_DLC_BASE + 0x6C) ++#define REG_VIP_DLC_36_H (REG_VIP_DLC_BASE + 0x6D) ++#define REG_VIP_DLC_37_L (REG_VIP_DLC_BASE + 0x6E) ++#define REG_VIP_DLC_37_H (REG_VIP_DLC_BASE + 0x6F) ++#define REG_VIP_DLC_38_L (REG_VIP_DLC_BASE + 0x70) ++#define REG_VIP_DLC_38_H (REG_VIP_DLC_BASE + 0x71) ++#define REG_VIP_DLC_39_L (REG_VIP_DLC_BASE + 0x72) ++#define REG_VIP_DLC_39_H (REG_VIP_DLC_BASE + 0x73) ++#define REG_VIP_DLC_3A_L (REG_VIP_DLC_BASE + 0x74) ++#define REG_VIP_DLC_3A_H (REG_VIP_DLC_BASE + 0x75) ++#define REG_VIP_DLC_3B_L (REG_VIP_DLC_BASE + 0x76) ++#define REG_VIP_DLC_3B_H (REG_VIP_DLC_BASE + 0x77) ++#define REG_VIP_DLC_3C_L (REG_VIP_DLC_BASE + 0x78) ++#define REG_VIP_DLC_3C_H (REG_VIP_DLC_BASE + 0x79) ++#define REG_VIP_DLC_3D_L (REG_VIP_DLC_BASE + 0x7A) ++#define REG_VIP_DLC_3D_H (REG_VIP_DLC_BASE + 0x7B) ++#define REG_VIP_DLC_3E_L (REG_VIP_DLC_BASE + 0x7C) ++#define REG_VIP_DLC_3E_H (REG_VIP_DLC_BASE + 0x7D) ++#define REG_VIP_DLC_3F_L (REG_VIP_DLC_BASE + 0x7E) ++#define REG_VIP_DLC_3F_H (REG_VIP_DLC_BASE + 0x7F) ++#define REG_VIP_DLC_40_L (REG_VIP_DLC_BASE + 0x80) ++#define REG_VIP_DLC_40_H (REG_VIP_DLC_BASE + 0x81) ++#define REG_VIP_DLC_41_L (REG_VIP_DLC_BASE + 0x82) ++#define REG_VIP_DLC_41_H (REG_VIP_DLC_BASE + 0x83) ++#define REG_VIP_DLC_42_L (REG_VIP_DLC_BASE + 0x84) ++#define REG_VIP_DLC_42_H (REG_VIP_DLC_BASE + 0x85) ++#define REG_VIP_DLC_43_L (REG_VIP_DLC_BASE + 0x86) ++#define REG_VIP_DLC_43_H (REG_VIP_DLC_BASE + 0x87) ++#define REG_VIP_DLC_44_L (REG_VIP_DLC_BASE + 0x88) ++#define REG_VIP_DLC_44_H (REG_VIP_DLC_BASE + 0x89) ++#define REG_VIP_DLC_45_L (REG_VIP_DLC_BASE + 0x8A) ++#define REG_VIP_DLC_45_H (REG_VIP_DLC_BASE + 0x8B) ++#define REG_VIP_DLC_46_L (REG_VIP_DLC_BASE + 0x8C) ++#define REG_VIP_DLC_46_H (REG_VIP_DLC_BASE + 0x8D) ++#define REG_VIP_DLC_47_L (REG_VIP_DLC_BASE + 0x8E) ++#define REG_VIP_DLC_47_H (REG_VIP_DLC_BASE + 0x8F) ++#define REG_VIP_DLC_48_L (REG_VIP_DLC_BASE + 0x90) ++#define REG_VIP_DLC_48_H (REG_VIP_DLC_BASE + 0x91) ++#define REG_VIP_DLC_49_L (REG_VIP_DLC_BASE + 0x92) ++#define REG_VIP_DLC_49_H (REG_VIP_DLC_BASE + 0x93) ++#define REG_VIP_DLC_4A_L (REG_VIP_DLC_BASE + 0x94) ++#define REG_VIP_DLC_4A_H (REG_VIP_DLC_BASE + 0x95) ++#define REG_VIP_DLC_4B_L (REG_VIP_DLC_BASE + 0x96) ++#define REG_VIP_DLC_4B_H (REG_VIP_DLC_BASE + 0x97) ++#define REG_VIP_DLC_4C_L (REG_VIP_DLC_BASE + 0x98) ++#define REG_VIP_DLC_4C_H (REG_VIP_DLC_BASE + 0x99) ++#define REG_VIP_DLC_4D_L (REG_VIP_DLC_BASE + 0x9A) ++#define REG_VIP_DLC_4D_H (REG_VIP_DLC_BASE + 0x9B) ++#define REG_VIP_DLC_4E_L (REG_VIP_DLC_BASE + 0x9C) ++#define REG_VIP_DLC_4E_H (REG_VIP_DLC_BASE + 0x9D) ++#define REG_VIP_DLC_4F_L (REG_VIP_DLC_BASE + 0x9E) ++#define REG_VIP_DLC_4F_H (REG_VIP_DLC_BASE + 0x9F) ++#define REG_VIP_DLC_50_L (REG_VIP_DLC_BASE + 0xA0) ++#define REG_VIP_DLC_50_H (REG_VIP_DLC_BASE + 0xA1) ++#define REG_VIP_DLC_51_L (REG_VIP_DLC_BASE + 0xA2) ++#define REG_VIP_DLC_51_H (REG_VIP_DLC_BASE + 0xA3) ++#define REG_VIP_DLC_52_L (REG_VIP_DLC_BASE + 0xA4) ++#define REG_VIP_DLC_52_H (REG_VIP_DLC_BASE + 0xA5) ++#define REG_VIP_DLC_53_L (REG_VIP_DLC_BASE + 0xA6) ++#define REG_VIP_DLC_53_H (REG_VIP_DLC_BASE + 0xA7) ++#define REG_VIP_DLC_54_L (REG_VIP_DLC_BASE + 0xA8) ++#define REG_VIP_DLC_54_H (REG_VIP_DLC_BASE + 0xA9) ++#define REG_VIP_DLC_55_L (REG_VIP_DLC_BASE + 0xAA) ++#define REG_VIP_DLC_55_H (REG_VIP_DLC_BASE + 0xAB) ++#define REG_VIP_DLC_56_L (REG_VIP_DLC_BASE + 0xAC) ++#define REG_VIP_DLC_56_H (REG_VIP_DLC_BASE + 0xAD) ++#define REG_VIP_DLC_57_L (REG_VIP_DLC_BASE + 0xAE) ++#define REG_VIP_DLC_57_H (REG_VIP_DLC_BASE + 0xAF) ++#define REG_VIP_DLC_58_L (REG_VIP_DLC_BASE + 0xB0) ++#define REG_VIP_DLC_58_H (REG_VIP_DLC_BASE + 0xB1) ++#define REG_VIP_DLC_59_L (REG_VIP_DLC_BASE + 0xB2) ++#define REG_VIP_DLC_59_H (REG_VIP_DLC_BASE + 0xB3) ++#define REG_VIP_DLC_5A_L (REG_VIP_DLC_BASE + 0xB4) ++#define REG_VIP_DLC_5A_H (REG_VIP_DLC_BASE + 0xB5) ++#define REG_VIP_DLC_5B_L (REG_VIP_DLC_BASE + 0xB6) ++#define REG_VIP_DLC_5B_H (REG_VIP_DLC_BASE + 0xB7) ++#define REG_VIP_DLC_5C_L (REG_VIP_DLC_BASE + 0xB8) ++#define REG_VIP_DLC_5C_H (REG_VIP_DLC_BASE + 0xB9) ++#define REG_VIP_DLC_5D_L (REG_VIP_DLC_BASE + 0xBA) ++#define REG_VIP_DLC_5D_H (REG_VIP_DLC_BASE + 0xBB) ++#define REG_VIP_DLC_5E_L (REG_VIP_DLC_BASE + 0xBC) ++#define REG_VIP_DLC_5E_H (REG_VIP_DLC_BASE + 0xBD) ++#define REG_VIP_DLC_5F_L (REG_VIP_DLC_BASE + 0xBE) ++#define REG_VIP_DLC_5F_H (REG_VIP_DLC_BASE + 0xBF) ++#define REG_VIP_DLC_60_L (REG_VIP_DLC_BASE + 0xC0) ++#define REG_VIP_DLC_60_H (REG_VIP_DLC_BASE + 0xC1) ++#define REG_VIP_DLC_61_L (REG_VIP_DLC_BASE + 0xC2) ++#define REG_VIP_DLC_61_H (REG_VIP_DLC_BASE + 0xC3) ++#define REG_VIP_DLC_62_L (REG_VIP_DLC_BASE + 0xC4) ++#define REG_VIP_DLC_62_H (REG_VIP_DLC_BASE + 0xC5) ++#define REG_VIP_DLC_63_L (REG_VIP_DLC_BASE + 0xC6) ++#define REG_VIP_DLC_63_H (REG_VIP_DLC_BASE + 0xC7) ++#define REG_VIP_DLC_64_L (REG_VIP_DLC_BASE + 0xC8) ++#define REG_VIP_DLC_64_H (REG_VIP_DLC_BASE + 0xC9) ++#define REG_VIP_DLC_65_L (REG_VIP_DLC_BASE + 0xCA) ++#define REG_VIP_DLC_65_H (REG_VIP_DLC_BASE + 0xCB) ++#define REG_VIP_DLC_66_L (REG_VIP_DLC_BASE + 0xCC) ++#define REG_VIP_DLC_66_H (REG_VIP_DLC_BASE + 0xCD) ++#define REG_VIP_DLC_67_L (REG_VIP_DLC_BASE + 0xCE) ++#define REG_VIP_DLC_67_H (REG_VIP_DLC_BASE + 0xCF) ++#define REG_VIP_DLC_68_L (REG_VIP_DLC_BASE + 0xD0) ++#define REG_VIP_DLC_68_H (REG_VIP_DLC_BASE + 0xD1) ++#define REG_VIP_DLC_69_L (REG_VIP_DLC_BASE + 0xD2) ++#define REG_VIP_DLC_69_H (REG_VIP_DLC_BASE + 0xD3) ++#define REG_VIP_DLC_6A_L (REG_VIP_DLC_BASE + 0xD4) ++#define REG_VIP_DLC_6A_H (REG_VIP_DLC_BASE + 0xD5) ++#define REG_VIP_DLC_6B_L (REG_VIP_DLC_BASE + 0xD6) ++#define REG_VIP_DLC_6B_H (REG_VIP_DLC_BASE + 0xD7) ++#define REG_VIP_DLC_6C_L (REG_VIP_DLC_BASE + 0xD8) ++#define REG_VIP_DLC_6C_H (REG_VIP_DLC_BASE + 0xD9) ++#define REG_VIP_DLC_6D_L (REG_VIP_DLC_BASE + 0xDA) ++#define REG_VIP_DLC_6D_H (REG_VIP_DLC_BASE + 0xDB) ++#define REG_VIP_DLC_6E_L (REG_VIP_DLC_BASE + 0xDC) ++#define REG_VIP_DLC_6E_H (REG_VIP_DLC_BASE + 0xDD) ++#define REG_VIP_DLC_6F_L (REG_VIP_DLC_BASE + 0xDE) ++#define REG_VIP_DLC_6F_H (REG_VIP_DLC_BASE + 0xDF) ++#define REG_VIP_DLC_70_L (REG_VIP_DLC_BASE + 0xE0) ++#define REG_VIP_DLC_70_H (REG_VIP_DLC_BASE + 0xE1) ++#define REG_VIP_DLC_71_L (REG_VIP_DLC_BASE + 0xE2) ++#define REG_VIP_DLC_71_H (REG_VIP_DLC_BASE + 0xE3) ++#define REG_VIP_DLC_72_L (REG_VIP_DLC_BASE + 0xE4) ++#define REG_VIP_DLC_72_H (REG_VIP_DLC_BASE + 0xE5) ++#define REG_VIP_DLC_73_L (REG_VIP_DLC_BASE + 0xE6) ++#define REG_VIP_DLC_73_H (REG_VIP_DLC_BASE + 0xE7) ++#define REG_VIP_DLC_74_L (REG_VIP_DLC_BASE + 0xE8) ++#define REG_VIP_DLC_74_H (REG_VIP_DLC_BASE + 0xE9) ++#define REG_VIP_DLC_75_L (REG_VIP_DLC_BASE + 0xEA) ++#define REG_VIP_DLC_75_H (REG_VIP_DLC_BASE + 0xEB) ++#define REG_VIP_DLC_76_L (REG_VIP_DLC_BASE + 0xEC) ++#define REG_VIP_DLC_76_H (REG_VIP_DLC_BASE + 0xED) ++#define REG_VIP_DLC_77_L (REG_VIP_DLC_BASE + 0xEE) ++#define REG_VIP_DLC_77_H (REG_VIP_DLC_BASE + 0xEF) ++#define REG_VIP_DLC_78_L (REG_VIP_DLC_BASE + 0xF0) ++#define REG_VIP_DLC_78_H (REG_VIP_DLC_BASE + 0xF1) ++#define REG_VIP_DLC_79_L (REG_VIP_DLC_BASE + 0xF2) ++#define REG_VIP_DLC_79_H (REG_VIP_DLC_BASE + 0xF3) ++#define REG_VIP_DLC_7A_L (REG_VIP_DLC_BASE + 0xF4) ++#define REG_VIP_DLC_7A_H (REG_VIP_DLC_BASE + 0xF5) ++#define REG_VIP_DLC_7B_L (REG_VIP_DLC_BASE + 0xF6) ++#define REG_VIP_DLC_7B_H (REG_VIP_DLC_BASE + 0xF7) ++#define REG_VIP_DLC_7C_L (REG_VIP_DLC_BASE + 0xF8) ++#define REG_VIP_DLC_7C_H (REG_VIP_DLC_BASE + 0xF9) ++#define REG_VIP_DLC_7D_L (REG_VIP_DLC_BASE + 0xFA) ++#define REG_VIP_DLC_7D_H (REG_VIP_DLC_BASE + 0xFB) ++#define REG_VIP_DLC_7E_L (REG_VIP_DLC_BASE + 0xFC) ++#define REG_VIP_DLC_7E_H (REG_VIP_DLC_BASE + 0xFD) ++#define REG_VIP_DLC_7F_L (REG_VIP_DLC_BASE + 0xFE) ++#define REG_VIP_DLC_7F_H (REG_VIP_DLC_BASE + 0xFF) ++ ++#define REG_VIP_MWE_00_L (REG_VIP_MWE_BASE + 0x00) ++#define REG_VIP_MWE_00_H (REG_VIP_MWE_BASE + 0x01) ++#define REG_VIP_MWE_01_L (REG_VIP_MWE_BASE + 0x02) ++#define REG_VIP_MWE_01_H (REG_VIP_MWE_BASE + 0x03) ++#define REG_VIP_MWE_02_L (REG_VIP_MWE_BASE + 0x04) ++#define REG_VIP_MWE_02_H (REG_VIP_MWE_BASE + 0x05) ++#define REG_VIP_MWE_03_L (REG_VIP_MWE_BASE + 0x06) ++#define REG_VIP_MWE_03_H (REG_VIP_MWE_BASE + 0x07) ++#define REG_VIP_MWE_04_L (REG_VIP_MWE_BASE + 0x08) ++#define REG_VIP_MWE_04_H (REG_VIP_MWE_BASE + 0x09) ++#define REG_VIP_MWE_05_L (REG_VIP_MWE_BASE + 0x0A) ++#define REG_VIP_MWE_05_H (REG_VIP_MWE_BASE + 0x0B) ++#define REG_VIP_MWE_06_L (REG_VIP_MWE_BASE + 0x0C) ++#define REG_VIP_MWE_06_H (REG_VIP_MWE_BASE + 0x0D) ++#define REG_VIP_MWE_07_L (REG_VIP_MWE_BASE + 0x0E) ++#define REG_VIP_MWE_07_H (REG_VIP_MWE_BASE + 0x0F) ++#define REG_VIP_MWE_08_L (REG_VIP_MWE_BASE + 0x10) ++#define REG_VIP_MWE_08_H (REG_VIP_MWE_BASE + 0x11) ++#define REG_VIP_MWE_09_L (REG_VIP_MWE_BASE + 0x12) ++#define REG_VIP_MWE_09_H (REG_VIP_MWE_BASE + 0x13) ++#define REG_VIP_MWE_0A_L (REG_VIP_MWE_BASE + 0x14) ++#define REG_VIP_MWE_0A_H (REG_VIP_MWE_BASE + 0x15) ++#define REG_VIP_MWE_0B_L (REG_VIP_MWE_BASE + 0x16) ++#define REG_VIP_MWE_0B_H (REG_VIP_MWE_BASE + 0x17) ++#define REG_VIP_MWE_0C_L (REG_VIP_MWE_BASE + 0x18) ++#define REG_VIP_MWE_0C_H (REG_VIP_MWE_BASE + 0x19) ++#define REG_VIP_MWE_0D_L (REG_VIP_MWE_BASE + 0x1A) ++#define REG_VIP_MWE_0D_H (REG_VIP_MWE_BASE + 0x1B) ++#define REG_VIP_MWE_0E_L (REG_VIP_MWE_BASE + 0x1C) ++#define REG_VIP_MWE_0E_H (REG_VIP_MWE_BASE + 0x1D) ++#define REG_VIP_MWE_0F_L (REG_VIP_MWE_BASE + 0x1E) ++#define REG_VIP_MWE_0F_H (REG_VIP_MWE_BASE + 0x1F) ++#define REG_VIP_MWE_10_L (REG_VIP_MWE_BASE + 0x20) ++#define REG_VIP_MWE_10_H (REG_VIP_MWE_BASE + 0x21) ++#define REG_VIP_MWE_11_L (REG_VIP_MWE_BASE + 0x22) ++#define REG_VIP_MWE_11_H (REG_VIP_MWE_BASE + 0x23) ++#define REG_VIP_MWE_12_L (REG_VIP_MWE_BASE + 0x24) ++#define REG_VIP_MWE_12_H (REG_VIP_MWE_BASE + 0x25) ++#define REG_VIP_MWE_13_L (REG_VIP_MWE_BASE + 0x26) ++#define REG_VIP_MWE_13_H (REG_VIP_MWE_BASE + 0x27) ++#define REG_VIP_MWE_14_L (REG_VIP_MWE_BASE + 0x28) ++#define REG_VIP_MWE_14_H (REG_VIP_MWE_BASE + 0x29) ++#define REG_VIP_MWE_15_L (REG_VIP_MWE_BASE + 0x2A) ++#define REG_VIP_MWE_15_H (REG_VIP_MWE_BASE + 0x2B) ++#define REG_VIP_MWE_16_L (REG_VIP_MWE_BASE + 0x2C) ++#define REG_VIP_MWE_16_H (REG_VIP_MWE_BASE + 0x2D) ++#define REG_VIP_MWE_17_L (REG_VIP_MWE_BASE + 0x2E) ++#define REG_VIP_MWE_17_H (REG_VIP_MWE_BASE + 0x2F) ++#define REG_VIP_MWE_18_L (REG_VIP_MWE_BASE + 0x30) ++#define REG_VIP_MWE_18_H (REG_VIP_MWE_BASE + 0x31) ++#define REG_VIP_MWE_19_L (REG_VIP_MWE_BASE + 0x32) ++#define REG_VIP_MWE_19_H (REG_VIP_MWE_BASE + 0x33) ++#define REG_VIP_MWE_1A_L (REG_VIP_MWE_BASE + 0x34) ++#define REG_VIP_MWE_1A_H (REG_VIP_MWE_BASE + 0x35) ++#define REG_VIP_MWE_1B_L (REG_VIP_MWE_BASE + 0x36) ++#define REG_VIP_MWE_1B_H (REG_VIP_MWE_BASE + 0x37) ++#define REG_VIP_MWE_1C_L (REG_VIP_MWE_BASE + 0x38) ++#define REG_VIP_MWE_1C_H (REG_VIP_MWE_BASE + 0x39) ++#define REG_VIP_MWE_1D_L (REG_VIP_MWE_BASE + 0x3A) ++#define REG_VIP_MWE_1D_H (REG_VIP_MWE_BASE + 0x3B) ++#define REG_VIP_MWE_1E_L (REG_VIP_MWE_BASE + 0x3C) ++#define REG_VIP_MWE_1E_H (REG_VIP_MWE_BASE + 0x3D) ++#define REG_VIP_MWE_1F_L (REG_VIP_MWE_BASE + 0x3E) ++#define REG_VIP_MWE_1F_H (REG_VIP_MWE_BASE + 0x3F) ++#define REG_VIP_MWE_20_L (REG_VIP_MWE_BASE + 0x40) ++#define REG_VIP_MWE_20_H (REG_VIP_MWE_BASE + 0x41) ++#define REG_VIP_MWE_21_L (REG_VIP_MWE_BASE + 0x42) ++#define REG_VIP_MWE_21_H (REG_VIP_MWE_BASE + 0x43) ++#define REG_VIP_MWE_22_L (REG_VIP_MWE_BASE + 0x44) ++#define REG_VIP_MWE_22_H (REG_VIP_MWE_BASE + 0x45) ++#define REG_VIP_MWE_23_L (REG_VIP_MWE_BASE + 0x46) ++#define REG_VIP_MWE_23_H (REG_VIP_MWE_BASE + 0x47) ++#define REG_VIP_MWE_24_L (REG_VIP_MWE_BASE + 0x48) ++#define REG_VIP_MWE_24_H (REG_VIP_MWE_BASE + 0x49) ++#define REG_VIP_MWE_25_L (REG_VIP_MWE_BASE + 0x4A) ++#define REG_VIP_MWE_25_H (REG_VIP_MWE_BASE + 0x4B) ++#define REG_VIP_MWE_26_L (REG_VIP_MWE_BASE + 0x4C) ++#define REG_VIP_MWE_26_H (REG_VIP_MWE_BASE + 0x4D) ++#define REG_VIP_MWE_27_L (REG_VIP_MWE_BASE + 0x4E) ++#define REG_VIP_MWE_27_H (REG_VIP_MWE_BASE + 0x4F) ++#define REG_VIP_MWE_28_L (REG_VIP_MWE_BASE + 0x50) ++#define REG_VIP_MWE_28_H (REG_VIP_MWE_BASE + 0x51) ++#define REG_VIP_MWE_29_L (REG_VIP_MWE_BASE + 0x52) ++#define REG_VIP_MWE_29_H (REG_VIP_MWE_BASE + 0x53) ++#define REG_VIP_MWE_2A_L (REG_VIP_MWE_BASE + 0x54) ++#define REG_VIP_MWE_2A_H (REG_VIP_MWE_BASE + 0x55) ++#define REG_VIP_MWE_2B_L (REG_VIP_MWE_BASE + 0x56) ++#define REG_VIP_MWE_2B_H (REG_VIP_MWE_BASE + 0x57) ++#define REG_VIP_MWE_2C_L (REG_VIP_MWE_BASE + 0x58) ++#define REG_VIP_MWE_2C_H (REG_VIP_MWE_BASE + 0x59) ++#define REG_VIP_MWE_2D_L (REG_VIP_MWE_BASE + 0x5A) ++#define REG_VIP_MWE_2D_H (REG_VIP_MWE_BASE + 0x5B) ++#define REG_VIP_MWE_2E_L (REG_VIP_MWE_BASE + 0x5C) ++#define REG_VIP_MWE_2E_H (REG_VIP_MWE_BASE + 0x5D) ++#define REG_VIP_MWE_2F_L (REG_VIP_MWE_BASE + 0x5E) ++#define REG_VIP_MWE_2F_H (REG_VIP_MWE_BASE + 0x5F) ++#define REG_VIP_MWE_30_L (REG_VIP_MWE_BASE + 0x60) ++#define REG_VIP_MWE_30_H (REG_VIP_MWE_BASE + 0x61) ++#define REG_VIP_MWE_31_L (REG_VIP_MWE_BASE + 0x62) ++#define REG_VIP_MWE_31_H (REG_VIP_MWE_BASE + 0x63) ++#define REG_VIP_MWE_32_L (REG_VIP_MWE_BASE + 0x64) ++#define REG_VIP_MWE_32_H (REG_VIP_MWE_BASE + 0x65) ++#define REG_VIP_MWE_33_L (REG_VIP_MWE_BASE + 0x66) ++#define REG_VIP_MWE_33_H (REG_VIP_MWE_BASE + 0x67) ++#define REG_VIP_MWE_34_L (REG_VIP_MWE_BASE + 0x68) ++#define REG_VIP_MWE_34_H (REG_VIP_MWE_BASE + 0x69) ++#define REG_VIP_MWE_35_L (REG_VIP_MWE_BASE + 0x6A) ++#define REG_VIP_MWE_35_H (REG_VIP_MWE_BASE + 0x6B) ++#define REG_VIP_MWE_36_L (REG_VIP_MWE_BASE + 0x6C) ++#define REG_VIP_MWE_36_H (REG_VIP_MWE_BASE + 0x6D) ++#define REG_VIP_MWE_37_L (REG_VIP_MWE_BASE + 0x6E) ++#define REG_VIP_MWE_37_H (REG_VIP_MWE_BASE + 0x6F) ++#define REG_VIP_MWE_38_L (REG_VIP_MWE_BASE + 0x70) ++#define REG_VIP_MWE_38_H (REG_VIP_MWE_BASE + 0x71) ++#define REG_VIP_MWE_39_L (REG_VIP_MWE_BASE + 0x72) ++#define REG_VIP_MWE_39_H (REG_VIP_MWE_BASE + 0x73) ++#define REG_VIP_MWE_3A_L (REG_VIP_MWE_BASE + 0x74) ++#define REG_VIP_MWE_3A_H (REG_VIP_MWE_BASE + 0x75) ++#define REG_VIP_MWE_3B_L (REG_VIP_MWE_BASE + 0x76) ++#define REG_VIP_MWE_3B_H (REG_VIP_MWE_BASE + 0x77) ++#define REG_VIP_MWE_3C_L (REG_VIP_MWE_BASE + 0x78) ++#define REG_VIP_MWE_3C_H (REG_VIP_MWE_BASE + 0x79) ++#define REG_VIP_MWE_3D_L (REG_VIP_MWE_BASE + 0x7A) ++#define REG_VIP_MWE_3D_H (REG_VIP_MWE_BASE + 0x7B) ++#define REG_VIP_MWE_3E_L (REG_VIP_MWE_BASE + 0x7C) ++#define REG_VIP_MWE_3E_H (REG_VIP_MWE_BASE + 0x7D) ++#define REG_VIP_MWE_3F_L (REG_VIP_MWE_BASE + 0x7E) ++#define REG_VIP_MWE_3F_H (REG_VIP_MWE_BASE + 0x7F) ++#define REG_VIP_MWE_40_L (REG_VIP_MWE_BASE + 0x80) ++#define REG_VIP_MWE_40_H (REG_VIP_MWE_BASE + 0x81) ++#define REG_VIP_MWE_41_L (REG_VIP_MWE_BASE + 0x82) ++#define REG_VIP_MWE_41_H (REG_VIP_MWE_BASE + 0x83) ++#define REG_VIP_MWE_42_L (REG_VIP_MWE_BASE + 0x84) ++#define REG_VIP_MWE_42_H (REG_VIP_MWE_BASE + 0x85) ++#define REG_VIP_MWE_43_L (REG_VIP_MWE_BASE + 0x86) ++#define REG_VIP_MWE_43_H (REG_VIP_MWE_BASE + 0x87) ++#define REG_VIP_MWE_44_L (REG_VIP_MWE_BASE + 0x88) ++#define REG_VIP_MWE_44_H (REG_VIP_MWE_BASE + 0x89) ++#define REG_VIP_MWE_45_L (REG_VIP_MWE_BASE + 0x8A) ++#define REG_VIP_MWE_45_H (REG_VIP_MWE_BASE + 0x8B) ++#define REG_VIP_MWE_46_L (REG_VIP_MWE_BASE + 0x8C) ++#define REG_VIP_MWE_46_H (REG_VIP_MWE_BASE + 0x8D) ++#define REG_VIP_MWE_47_L (REG_VIP_MWE_BASE + 0x8E) ++#define REG_VIP_MWE_47_H (REG_VIP_MWE_BASE + 0x8F) ++#define REG_VIP_MWE_48_L (REG_VIP_MWE_BASE + 0x90) ++#define REG_VIP_MWE_48_H (REG_VIP_MWE_BASE + 0x91) ++#define REG_VIP_MWE_49_L (REG_VIP_MWE_BASE + 0x92) ++#define REG_VIP_MWE_49_H (REG_VIP_MWE_BASE + 0x93) ++#define REG_VIP_MWE_4A_L (REG_VIP_MWE_BASE + 0x94) ++#define REG_VIP_MWE_4A_H (REG_VIP_MWE_BASE + 0x95) ++#define REG_VIP_MWE_4B_L (REG_VIP_MWE_BASE + 0x96) ++#define REG_VIP_MWE_4B_H (REG_VIP_MWE_BASE + 0x97) ++#define REG_VIP_MWE_4C_L (REG_VIP_MWE_BASE + 0x98) ++#define REG_VIP_MWE_4C_H (REG_VIP_MWE_BASE + 0x99) ++#define REG_VIP_MWE_4D_L (REG_VIP_MWE_BASE + 0x9A) ++#define REG_VIP_MWE_4D_H (REG_VIP_MWE_BASE + 0x9B) ++#define REG_VIP_MWE_4E_L (REG_VIP_MWE_BASE + 0x9C) ++#define REG_VIP_MWE_4E_H (REG_VIP_MWE_BASE + 0x9D) ++#define REG_VIP_MWE_4F_L (REG_VIP_MWE_BASE + 0x9E) ++#define REG_VIP_MWE_4F_H (REG_VIP_MWE_BASE + 0x9F) ++#define REG_VIP_MWE_50_L (REG_VIP_MWE_BASE + 0xA0) ++#define REG_VIP_MWE_50_H (REG_VIP_MWE_BASE + 0xA1) ++#define REG_VIP_MWE_51_L (REG_VIP_MWE_BASE + 0xA2) ++#define REG_VIP_MWE_51_H (REG_VIP_MWE_BASE + 0xA3) ++#define REG_VIP_MWE_52_L (REG_VIP_MWE_BASE + 0xA4) ++#define REG_VIP_MWE_52_H (REG_VIP_MWE_BASE + 0xA5) ++#define REG_VIP_MWE_53_L (REG_VIP_MWE_BASE + 0xA6) ++#define REG_VIP_MWE_53_H (REG_VIP_MWE_BASE + 0xA7) ++#define REG_VIP_MWE_54_L (REG_VIP_MWE_BASE + 0xA8) ++#define REG_VIP_MWE_54_H (REG_VIP_MWE_BASE + 0xA9) ++#define REG_VIP_MWE_55_L (REG_VIP_MWE_BASE + 0xAA) ++#define REG_VIP_MWE_55_H (REG_VIP_MWE_BASE + 0xAB) ++#define REG_VIP_MWE_56_L (REG_VIP_MWE_BASE + 0xAC) ++#define REG_VIP_MWE_56_H (REG_VIP_MWE_BASE + 0xAD) ++#define REG_VIP_MWE_57_L (REG_VIP_MWE_BASE + 0xAE) ++#define REG_VIP_MWE_57_H (REG_VIP_MWE_BASE + 0xAF) ++#define REG_VIP_MWE_58_L (REG_VIP_MWE_BASE + 0xB0) ++#define REG_VIP_MWE_58_H (REG_VIP_MWE_BASE + 0xB1) ++#define REG_VIP_MWE_59_L (REG_VIP_MWE_BASE + 0xB2) ++#define REG_VIP_MWE_59_H (REG_VIP_MWE_BASE + 0xB3) ++#define REG_VIP_MWE_5A_L (REG_VIP_MWE_BASE + 0xB4) ++#define REG_VIP_MWE_5A_H (REG_VIP_MWE_BASE + 0xB5) ++#define REG_VIP_MWE_5B_L (REG_VIP_MWE_BASE + 0xB6) ++#define REG_VIP_MWE_5B_H (REG_VIP_MWE_BASE + 0xB7) ++#define REG_VIP_MWE_5C_L (REG_VIP_MWE_BASE + 0xB8) ++#define REG_VIP_MWE_5C_H (REG_VIP_MWE_BASE + 0xB9) ++#define REG_VIP_MWE_5D_L (REG_VIP_MWE_BASE + 0xBA) ++#define REG_VIP_MWE_5D_H (REG_VIP_MWE_BASE + 0xBB) ++#define REG_VIP_MWE_5E_L (REG_VIP_MWE_BASE + 0xBC) ++#define REG_VIP_MWE_5E_H (REG_VIP_MWE_BASE + 0xBD) ++#define REG_VIP_MWE_5F_L (REG_VIP_MWE_BASE + 0xBE) ++#define REG_VIP_MWE_5F_H (REG_VIP_MWE_BASE + 0xBF) ++#define REG_VIP_MWE_60_L (REG_VIP_MWE_BASE + 0xC0) ++#define REG_VIP_MWE_60_H (REG_VIP_MWE_BASE + 0xC1) ++#define REG_VIP_MWE_61_L (REG_VIP_MWE_BASE + 0xC2) ++#define REG_VIP_MWE_61_H (REG_VIP_MWE_BASE + 0xC3) ++#define REG_VIP_MWE_62_L (REG_VIP_MWE_BASE + 0xC4) ++#define REG_VIP_MWE_62_H (REG_VIP_MWE_BASE + 0xC5) ++#define REG_VIP_MWE_63_L (REG_VIP_MWE_BASE + 0xC6) ++#define REG_VIP_MWE_63_H (REG_VIP_MWE_BASE + 0xC7) ++#define REG_VIP_MWE_64_L (REG_VIP_MWE_BASE + 0xC8) ++#define REG_VIP_MWE_64_H (REG_VIP_MWE_BASE + 0xC9) ++#define REG_VIP_MWE_65_L (REG_VIP_MWE_BASE + 0xCA) ++#define REG_VIP_MWE_65_H (REG_VIP_MWE_BASE + 0xCB) ++#define REG_VIP_MWE_66_L (REG_VIP_MWE_BASE + 0xCC) ++#define REG_VIP_MWE_66_H (REG_VIP_MWE_BASE + 0xCD) ++#define REG_VIP_MWE_67_L (REG_VIP_MWE_BASE + 0xCE) ++#define REG_VIP_MWE_67_H (REG_VIP_MWE_BASE + 0xCF) ++#define REG_VIP_MWE_68_L (REG_VIP_MWE_BASE + 0xD0) ++#define REG_VIP_MWE_68_H (REG_VIP_MWE_BASE + 0xD1) ++#define REG_VIP_MWE_69_L (REG_VIP_MWE_BASE + 0xD2) ++#define REG_VIP_MWE_69_H (REG_VIP_MWE_BASE + 0xD3) ++#define REG_VIP_MWE_6A_L (REG_VIP_MWE_BASE + 0xD4) ++#define REG_VIP_MWE_6A_H (REG_VIP_MWE_BASE + 0xD5) ++#define REG_VIP_MWE_6B_L (REG_VIP_MWE_BASE + 0xD6) ++#define REG_VIP_MWE_6B_H (REG_VIP_MWE_BASE + 0xD7) ++#define REG_VIP_MWE_6C_L (REG_VIP_MWE_BASE + 0xD8) ++#define REG_VIP_MWE_6C_H (REG_VIP_MWE_BASE + 0xD9) ++#define REG_VIP_MWE_6D_L (REG_VIP_MWE_BASE + 0xDA) ++#define REG_VIP_MWE_6D_H (REG_VIP_MWE_BASE + 0xDB) ++#define REG_VIP_MWE_6E_L (REG_VIP_MWE_BASE + 0xDC) ++#define REG_VIP_MWE_6E_H (REG_VIP_MWE_BASE + 0xDD) ++#define REG_VIP_MWE_6F_L (REG_VIP_MWE_BASE + 0xDE) ++#define REG_VIP_MWE_6F_H (REG_VIP_MWE_BASE + 0xDF) ++#define REG_VIP_MWE_70_L (REG_VIP_MWE_BASE + 0xE0) ++#define REG_VIP_MWE_70_H (REG_VIP_MWE_BASE + 0xE1) ++#define REG_VIP_MWE_71_L (REG_VIP_MWE_BASE + 0xE2) ++#define REG_VIP_MWE_71_H (REG_VIP_MWE_BASE + 0xE3) ++#define REG_VIP_MWE_72_L (REG_VIP_MWE_BASE + 0xE4) ++#define REG_VIP_MWE_72_H (REG_VIP_MWE_BASE + 0xE5) ++#define REG_VIP_MWE_73_L (REG_VIP_MWE_BASE + 0xE6) ++#define REG_VIP_MWE_73_H (REG_VIP_MWE_BASE + 0xE7) ++#define REG_VIP_MWE_74_L (REG_VIP_MWE_BASE + 0xE8) ++#define REG_VIP_MWE_74_H (REG_VIP_MWE_BASE + 0xE9) ++#define REG_VIP_MWE_75_L (REG_VIP_MWE_BASE + 0xEA) ++#define REG_VIP_MWE_75_H (REG_VIP_MWE_BASE + 0xEB) ++#define REG_VIP_MWE_76_L (REG_VIP_MWE_BASE + 0xEC) ++#define REG_VIP_MWE_76_H (REG_VIP_MWE_BASE + 0xED) ++#define REG_VIP_MWE_77_L (REG_VIP_MWE_BASE + 0xEE) ++#define REG_VIP_MWE_77_H (REG_VIP_MWE_BASE + 0xEF) ++#define REG_VIP_MWE_78_L (REG_VIP_MWE_BASE + 0xF0) ++#define REG_VIP_MWE_78_H (REG_VIP_MWE_BASE + 0xF1) ++#define REG_VIP_MWE_79_L (REG_VIP_MWE_BASE + 0xF2) ++#define REG_VIP_MWE_79_H (REG_VIP_MWE_BASE + 0xF3) ++#define REG_VIP_MWE_7A_L (REG_VIP_MWE_BASE + 0xF4) ++#define REG_VIP_MWE_7A_H (REG_VIP_MWE_BASE + 0xF5) ++#define REG_VIP_MWE_7B_L (REG_VIP_MWE_BASE + 0xF6) ++#define REG_VIP_MWE_7B_H (REG_VIP_MWE_BASE + 0xF7) ++#define REG_VIP_MWE_7C_L (REG_VIP_MWE_BASE + 0xF8) ++#define REG_VIP_MWE_7C_H (REG_VIP_MWE_BASE + 0xF9) ++#define REG_VIP_MWE_7D_L (REG_VIP_MWE_BASE + 0xFA) ++#define REG_VIP_MWE_7D_H (REG_VIP_MWE_BASE + 0xFB) ++#define REG_VIP_MWE_7E_L (REG_VIP_MWE_BASE + 0xFC) ++#define REG_VIP_MWE_7E_H (REG_VIP_MWE_BASE + 0xFD) ++#define REG_VIP_MWE_7F_L (REG_VIP_MWE_BASE + 0xFE) ++#define REG_VIP_MWE_7F_H (REG_VIP_MWE_BASE + 0xFF) ++ ++#define REG_VIP_LCE_00_L (REG_VIP_LCE_BASE + 0x00) ++#define REG_VIP_LCE_00_H (REG_VIP_LCE_BASE + 0x01) ++#define REG_VIP_LCE_01_L (REG_VIP_LCE_BASE + 0x02) ++#define REG_VIP_LCE_01_H (REG_VIP_LCE_BASE + 0x03) ++#define REG_VIP_LCE_02_L (REG_VIP_LCE_BASE + 0x04) ++#define REG_VIP_LCE_02_H (REG_VIP_LCE_BASE + 0x05) ++#define REG_VIP_LCE_03_L (REG_VIP_LCE_BASE + 0x06) ++#define REG_VIP_LCE_03_H (REG_VIP_LCE_BASE + 0x07) ++#define REG_VIP_LCE_04_L (REG_VIP_LCE_BASE + 0x08) ++#define REG_VIP_LCE_04_H (REG_VIP_LCE_BASE + 0x09) ++#define REG_VIP_LCE_05_L (REG_VIP_LCE_BASE + 0x0A) ++#define REG_VIP_LCE_05_H (REG_VIP_LCE_BASE + 0x0B) ++#define REG_VIP_LCE_06_L (REG_VIP_LCE_BASE + 0x0C) ++#define REG_VIP_LCE_06_H (REG_VIP_LCE_BASE + 0x0D) ++#define REG_VIP_LCE_07_L (REG_VIP_LCE_BASE + 0x0E) ++#define REG_VIP_LCE_07_H (REG_VIP_LCE_BASE + 0x0F) ++#define REG_VIP_LCE_08_L (REG_VIP_LCE_BASE + 0x10) ++#define REG_VIP_LCE_08_H (REG_VIP_LCE_BASE + 0x11) ++#define REG_VIP_LCE_09_L (REG_VIP_LCE_BASE + 0x12) ++#define REG_VIP_LCE_09_H (REG_VIP_LCE_BASE + 0x13) ++#define REG_VIP_LCE_0A_L (REG_VIP_LCE_BASE + 0x14) ++#define REG_VIP_LCE_0A_H (REG_VIP_LCE_BASE + 0x15) ++#define REG_VIP_LCE_0B_L (REG_VIP_LCE_BASE + 0x16) ++#define REG_VIP_LCE_0B_H (REG_VIP_LCE_BASE + 0x17) ++#define REG_VIP_LCE_0C_L (REG_VIP_LCE_BASE + 0x18) ++#define REG_VIP_LCE_0C_H (REG_VIP_LCE_BASE + 0x19) ++#define REG_VIP_LCE_0D_L (REG_VIP_LCE_BASE + 0x1A) ++#define REG_VIP_LCE_0D_H (REG_VIP_LCE_BASE + 0x1B) ++#define REG_VIP_LCE_0E_L (REG_VIP_LCE_BASE + 0x1C) ++#define REG_VIP_LCE_0E_H (REG_VIP_LCE_BASE + 0x1D) ++#define REG_VIP_LCE_0F_L (REG_VIP_LCE_BASE + 0x1E) ++#define REG_VIP_LCE_0F_H (REG_VIP_LCE_BASE + 0x1F) ++#define REG_VIP_LCE_10_L (REG_VIP_LCE_BASE + 0x20) ++#define REG_VIP_LCE_10_H (REG_VIP_LCE_BASE + 0x21) ++#define REG_VIP_LCE_11_L (REG_VIP_LCE_BASE + 0x22) ++#define REG_VIP_LCE_11_H (REG_VIP_LCE_BASE + 0x23) ++#define REG_VIP_LCE_12_L (REG_VIP_LCE_BASE + 0x24) ++#define REG_VIP_LCE_12_H (REG_VIP_LCE_BASE + 0x25) ++#define REG_VIP_LCE_13_L (REG_VIP_LCE_BASE + 0x26) ++#define REG_VIP_LCE_13_H (REG_VIP_LCE_BASE + 0x27) ++#define REG_VIP_LCE_14_L (REG_VIP_LCE_BASE + 0x28) ++#define REG_VIP_LCE_14_H (REG_VIP_LCE_BASE + 0x29) ++#define REG_VIP_LCE_15_L (REG_VIP_LCE_BASE + 0x2A) ++#define REG_VIP_LCE_15_H (REG_VIP_LCE_BASE + 0x2B) ++#define REG_VIP_LCE_16_L (REG_VIP_LCE_BASE + 0x2C) ++#define REG_VIP_LCE_16_H (REG_VIP_LCE_BASE + 0x2D) ++#define REG_VIP_LCE_17_L (REG_VIP_LCE_BASE + 0x2E) ++#define REG_VIP_LCE_17_H (REG_VIP_LCE_BASE + 0x2F) ++#define REG_VIP_LCE_18_L (REG_VIP_LCE_BASE + 0x30) ++#define REG_VIP_LCE_18_H (REG_VIP_LCE_BASE + 0x31) ++#define REG_VIP_LCE_19_L (REG_VIP_LCE_BASE + 0x32) ++#define REG_VIP_LCE_19_H (REG_VIP_LCE_BASE + 0x33) ++#define REG_VIP_LCE_1A_L (REG_VIP_LCE_BASE + 0x34) ++#define REG_VIP_LCE_1A_H (REG_VIP_LCE_BASE + 0x35) ++#define REG_VIP_LCE_1B_L (REG_VIP_LCE_BASE + 0x36) ++#define REG_VIP_LCE_1B_H (REG_VIP_LCE_BASE + 0x37) ++#define REG_VIP_LCE_1C_L (REG_VIP_LCE_BASE + 0x38) ++#define REG_VIP_LCE_1C_H (REG_VIP_LCE_BASE + 0x39) ++#define REG_VIP_LCE_1D_L (REG_VIP_LCE_BASE + 0x3A) ++#define REG_VIP_LCE_1D_H (REG_VIP_LCE_BASE + 0x3B) ++#define REG_VIP_LCE_1E_L (REG_VIP_LCE_BASE + 0x3C) ++#define REG_VIP_LCE_1E_H (REG_VIP_LCE_BASE + 0x3D) ++#define REG_VIP_LCE_1F_L (REG_VIP_LCE_BASE + 0x3E) ++#define REG_VIP_LCE_1F_H (REG_VIP_LCE_BASE + 0x3F) ++#define REG_VIP_LCE_20_L (REG_VIP_LCE_BASE + 0x40) ++#define REG_VIP_LCE_20_H (REG_VIP_LCE_BASE + 0x41) ++#define REG_VIP_LCE_21_L (REG_VIP_LCE_BASE + 0x42) ++#define REG_VIP_LCE_21_H (REG_VIP_LCE_BASE + 0x43) ++#define REG_VIP_LCE_22_L (REG_VIP_LCE_BASE + 0x44) ++#define REG_VIP_LCE_22_H (REG_VIP_LCE_BASE + 0x45) ++#define REG_VIP_LCE_23_L (REG_VIP_LCE_BASE + 0x46) ++#define REG_VIP_LCE_23_H (REG_VIP_LCE_BASE + 0x47) ++#define REG_VIP_LCE_24_L (REG_VIP_LCE_BASE + 0x48) ++#define REG_VIP_LCE_24_H (REG_VIP_LCE_BASE + 0x49) ++#define REG_VIP_LCE_25_L (REG_VIP_LCE_BASE + 0x4A) ++#define REG_VIP_LCE_25_H (REG_VIP_LCE_BASE + 0x4B) ++#define REG_VIP_LCE_26_L (REG_VIP_LCE_BASE + 0x4C) ++#define REG_VIP_LCE_26_H (REG_VIP_LCE_BASE + 0x4D) ++#define REG_VIP_LCE_27_L (REG_VIP_LCE_BASE + 0x4E) ++#define REG_VIP_LCE_27_H (REG_VIP_LCE_BASE + 0x4F) ++#define REG_VIP_LCE_28_L (REG_VIP_LCE_BASE + 0x50) ++#define REG_VIP_LCE_28_H (REG_VIP_LCE_BASE + 0x51) ++#define REG_VIP_LCE_29_L (REG_VIP_LCE_BASE + 0x52) ++#define REG_VIP_LCE_29_H (REG_VIP_LCE_BASE + 0x53) ++#define REG_VIP_LCE_2A_L (REG_VIP_LCE_BASE + 0x54) ++#define REG_VIP_LCE_2A_H (REG_VIP_LCE_BASE + 0x55) ++#define REG_VIP_LCE_2B_L (REG_VIP_LCE_BASE + 0x56) ++#define REG_VIP_LCE_2B_H (REG_VIP_LCE_BASE + 0x57) ++#define REG_VIP_LCE_2C_L (REG_VIP_LCE_BASE + 0x58) ++#define REG_VIP_LCE_2C_H (REG_VIP_LCE_BASE + 0x59) ++#define REG_VIP_LCE_2D_L (REG_VIP_LCE_BASE + 0x5A) ++#define REG_VIP_LCE_2D_H (REG_VIP_LCE_BASE + 0x5B) ++#define REG_VIP_LCE_2E_L (REG_VIP_LCE_BASE + 0x5C) ++#define REG_VIP_LCE_2E_H (REG_VIP_LCE_BASE + 0x5D) ++#define REG_VIP_LCE_2F_L (REG_VIP_LCE_BASE + 0x5E) ++#define REG_VIP_LCE_2F_H (REG_VIP_LCE_BASE + 0x5F) ++#define REG_VIP_LCE_30_L (REG_VIP_LCE_BASE + 0x60) ++#define REG_VIP_LCE_30_H (REG_VIP_LCE_BASE + 0x61) ++#define REG_VIP_LCE_31_L (REG_VIP_LCE_BASE + 0x62) ++#define REG_VIP_LCE_31_H (REG_VIP_LCE_BASE + 0x63) ++#define REG_VIP_LCE_32_L (REG_VIP_LCE_BASE + 0x64) ++#define REG_VIP_LCE_32_H (REG_VIP_LCE_BASE + 0x65) ++#define REG_VIP_LCE_33_L (REG_VIP_LCE_BASE + 0x66) ++#define REG_VIP_LCE_33_H (REG_VIP_LCE_BASE + 0x67) ++#define REG_VIP_LCE_34_L (REG_VIP_LCE_BASE + 0x68) ++#define REG_VIP_LCE_34_H (REG_VIP_LCE_BASE + 0x69) ++#define REG_VIP_LCE_35_L (REG_VIP_LCE_BASE + 0x6A) ++#define REG_VIP_LCE_35_H (REG_VIP_LCE_BASE + 0x6B) ++#define REG_VIP_LCE_36_L (REG_VIP_LCE_BASE + 0x6C) ++#define REG_VIP_LCE_36_H (REG_VIP_LCE_BASE + 0x6D) ++#define REG_VIP_LCE_37_L (REG_VIP_LCE_BASE + 0x6E) ++#define REG_VIP_LCE_37_H (REG_VIP_LCE_BASE + 0x6F) ++#define REG_VIP_LCE_38_L (REG_VIP_LCE_BASE + 0x70) ++#define REG_VIP_LCE_38_H (REG_VIP_LCE_BASE + 0x71) ++#define REG_VIP_LCE_39_L (REG_VIP_LCE_BASE + 0x72) ++#define REG_VIP_LCE_39_H (REG_VIP_LCE_BASE + 0x73) ++#define REG_VIP_LCE_3A_L (REG_VIP_LCE_BASE + 0x74) ++#define REG_VIP_LCE_3A_H (REG_VIP_LCE_BASE + 0x75) ++#define REG_VIP_LCE_3B_L (REG_VIP_LCE_BASE + 0x76) ++#define REG_VIP_LCE_3B_H (REG_VIP_LCE_BASE + 0x77) ++#define REG_VIP_LCE_3C_L (REG_VIP_LCE_BASE + 0x78) ++#define REG_VIP_LCE_3C_H (REG_VIP_LCE_BASE + 0x79) ++#define REG_VIP_LCE_3D_L (REG_VIP_LCE_BASE + 0x7A) ++#define REG_VIP_LCE_3D_H (REG_VIP_LCE_BASE + 0x7B) ++#define REG_VIP_LCE_3E_L (REG_VIP_LCE_BASE + 0x7C) ++#define REG_VIP_LCE_3E_H (REG_VIP_LCE_BASE + 0x7D) ++#define REG_VIP_LCE_3F_L (REG_VIP_LCE_BASE + 0x7E) ++#define REG_VIP_LCE_3F_H (REG_VIP_LCE_BASE + 0x7F) ++#define REG_VIP_LCE_40_L (REG_VIP_LCE_BASE + 0x80) ++#define REG_VIP_LCE_40_H (REG_VIP_LCE_BASE + 0x81) ++#define REG_VIP_LCE_41_L (REG_VIP_LCE_BASE + 0x82) ++#define REG_VIP_LCE_41_H (REG_VIP_LCE_BASE + 0x83) ++#define REG_VIP_LCE_42_L (REG_VIP_LCE_BASE + 0x84) ++#define REG_VIP_LCE_42_H (REG_VIP_LCE_BASE + 0x85) ++#define REG_VIP_LCE_43_L (REG_VIP_LCE_BASE + 0x86) ++#define REG_VIP_LCE_43_H (REG_VIP_LCE_BASE + 0x87) ++#define REG_VIP_LCE_44_L (REG_VIP_LCE_BASE + 0x88) ++#define REG_VIP_LCE_44_H (REG_VIP_LCE_BASE + 0x89) ++#define REG_VIP_LCE_45_L (REG_VIP_LCE_BASE + 0x8A) ++#define REG_VIP_LCE_45_H (REG_VIP_LCE_BASE + 0x8B) ++#define REG_VIP_LCE_46_L (REG_VIP_LCE_BASE + 0x8C) ++#define REG_VIP_LCE_46_H (REG_VIP_LCE_BASE + 0x8D) ++#define REG_VIP_LCE_47_L (REG_VIP_LCE_BASE + 0x8E) ++#define REG_VIP_LCE_47_H (REG_VIP_LCE_BASE + 0x8F) ++#define REG_VIP_LCE_48_L (REG_VIP_LCE_BASE + 0x90) ++#define REG_VIP_LCE_48_H (REG_VIP_LCE_BASE + 0x91) ++#define REG_VIP_LCE_49_L (REG_VIP_LCE_BASE + 0x92) ++#define REG_VIP_LCE_49_H (REG_VIP_LCE_BASE + 0x93) ++#define REG_VIP_LCE_4A_L (REG_VIP_LCE_BASE + 0x94) ++#define REG_VIP_LCE_4A_H (REG_VIP_LCE_BASE + 0x95) ++#define REG_VIP_LCE_4B_L (REG_VIP_LCE_BASE + 0x96) ++#define REG_VIP_LCE_4B_H (REG_VIP_LCE_BASE + 0x97) ++#define REG_VIP_LCE_4C_L (REG_VIP_LCE_BASE + 0x98) ++#define REG_VIP_LCE_4C_H (REG_VIP_LCE_BASE + 0x99) ++#define REG_VIP_LCE_4D_L (REG_VIP_LCE_BASE + 0x9A) ++#define REG_VIP_LCE_4D_H (REG_VIP_LCE_BASE + 0x9B) ++#define REG_VIP_LCE_4E_L (REG_VIP_LCE_BASE + 0x9C) ++#define REG_VIP_LCE_4E_H (REG_VIP_LCE_BASE + 0x9D) ++#define REG_VIP_LCE_4F_L (REG_VIP_LCE_BASE + 0x9E) ++#define REG_VIP_LCE_4F_H (REG_VIP_LCE_BASE + 0x9F) ++#define REG_VIP_LCE_50_L (REG_VIP_LCE_BASE + 0xA0) ++#define REG_VIP_LCE_50_H (REG_VIP_LCE_BASE + 0xA1) ++#define REG_VIP_LCE_51_L (REG_VIP_LCE_BASE + 0xA2) ++#define REG_VIP_LCE_51_H (REG_VIP_LCE_BASE + 0xA3) ++#define REG_VIP_LCE_52_L (REG_VIP_LCE_BASE + 0xA4) ++#define REG_VIP_LCE_52_H (REG_VIP_LCE_BASE + 0xA5) ++#define REG_VIP_LCE_53_L (REG_VIP_LCE_BASE + 0xA6) ++#define REG_VIP_LCE_53_H (REG_VIP_LCE_BASE + 0xA7) ++#define REG_VIP_LCE_54_L (REG_VIP_LCE_BASE + 0xA8) ++#define REG_VIP_LCE_54_H (REG_VIP_LCE_BASE + 0xA9) ++#define REG_VIP_LCE_55_L (REG_VIP_LCE_BASE + 0xAA) ++#define REG_VIP_LCE_55_H (REG_VIP_LCE_BASE + 0xAB) ++#define REG_VIP_LCE_56_L (REG_VIP_LCE_BASE + 0xAC) ++#define REG_VIP_LCE_56_H (REG_VIP_LCE_BASE + 0xAD) ++#define REG_VIP_LCE_57_L (REG_VIP_LCE_BASE + 0xAE) ++#define REG_VIP_LCE_57_H (REG_VIP_LCE_BASE + 0xAF) ++#define REG_VIP_LCE_58_L (REG_VIP_LCE_BASE + 0xB0) ++#define REG_VIP_LCE_58_H (REG_VIP_LCE_BASE + 0xB1) ++#define REG_VIP_LCE_59_L (REG_VIP_LCE_BASE + 0xB2) ++#define REG_VIP_LCE_59_H (REG_VIP_LCE_BASE + 0xB3) ++#define REG_VIP_LCE_5A_L (REG_VIP_LCE_BASE + 0xB4) ++#define REG_VIP_LCE_5A_H (REG_VIP_LCE_BASE + 0xB5) ++#define REG_VIP_LCE_5B_L (REG_VIP_LCE_BASE + 0xB6) ++#define REG_VIP_LCE_5B_H (REG_VIP_LCE_BASE + 0xB7) ++#define REG_VIP_LCE_5C_L (REG_VIP_LCE_BASE + 0xB8) ++#define REG_VIP_LCE_5C_H (REG_VIP_LCE_BASE + 0xB9) ++#define REG_VIP_LCE_5D_L (REG_VIP_LCE_BASE + 0xBA) ++#define REG_VIP_LCE_5D_H (REG_VIP_LCE_BASE + 0xBB) ++#define REG_VIP_LCE_5E_L (REG_VIP_LCE_BASE + 0xBC) ++#define REG_VIP_LCE_5E_H (REG_VIP_LCE_BASE + 0xBD) ++#define REG_VIP_LCE_5F_L (REG_VIP_LCE_BASE + 0xBE) ++#define REG_VIP_LCE_5F_H (REG_VIP_LCE_BASE + 0xBF) ++#define REG_VIP_LCE_60_L (REG_VIP_LCE_BASE + 0xC0) ++#define REG_VIP_LCE_60_H (REG_VIP_LCE_BASE + 0xC1) ++#define REG_VIP_LCE_61_L (REG_VIP_LCE_BASE + 0xC2) ++#define REG_VIP_LCE_61_H (REG_VIP_LCE_BASE + 0xC3) ++#define REG_VIP_LCE_62_L (REG_VIP_LCE_BASE + 0xC4) ++#define REG_VIP_LCE_62_H (REG_VIP_LCE_BASE + 0xC5) ++#define REG_VIP_LCE_63_L (REG_VIP_LCE_BASE + 0xC6) ++#define REG_VIP_LCE_63_H (REG_VIP_LCE_BASE + 0xC7) ++#define REG_VIP_LCE_64_L (REG_VIP_LCE_BASE + 0xC8) ++#define REG_VIP_LCE_64_H (REG_VIP_LCE_BASE + 0xC9) ++#define REG_VIP_LCE_65_L (REG_VIP_LCE_BASE + 0xCA) ++#define REG_VIP_LCE_65_H (REG_VIP_LCE_BASE + 0xCB) ++#define REG_VIP_LCE_66_L (REG_VIP_LCE_BASE + 0xCC) ++#define REG_VIP_LCE_66_H (REG_VIP_LCE_BASE + 0xCD) ++#define REG_VIP_LCE_67_L (REG_VIP_LCE_BASE + 0xCE) ++#define REG_VIP_LCE_67_H (REG_VIP_LCE_BASE + 0xCF) ++#define REG_VIP_LCE_68_L (REG_VIP_LCE_BASE + 0xD0) ++#define REG_VIP_LCE_68_H (REG_VIP_LCE_BASE + 0xD1) ++#define REG_VIP_LCE_69_L (REG_VIP_LCE_BASE + 0xD2) ++#define REG_VIP_LCE_69_H (REG_VIP_LCE_BASE + 0xD3) ++#define REG_VIP_LCE_6A_L (REG_VIP_LCE_BASE + 0xD4) ++#define REG_VIP_LCE_6A_H (REG_VIP_LCE_BASE + 0xD5) ++#define REG_VIP_LCE_6B_L (REG_VIP_LCE_BASE + 0xD6) ++#define REG_VIP_LCE_6B_H (REG_VIP_LCE_BASE + 0xD7) ++#define REG_VIP_LCE_6C_L (REG_VIP_LCE_BASE + 0xD8) ++#define REG_VIP_LCE_6C_H (REG_VIP_LCE_BASE + 0xD9) ++#define REG_VIP_LCE_6D_L (REG_VIP_LCE_BASE + 0xDA) ++#define REG_VIP_LCE_6D_H (REG_VIP_LCE_BASE + 0xDB) ++#define REG_VIP_LCE_6E_L (REG_VIP_LCE_BASE + 0xDC) ++#define REG_VIP_LCE_6E_H (REG_VIP_LCE_BASE + 0xDD) ++#define REG_VIP_LCE_6F_L (REG_VIP_LCE_BASE + 0xDE) ++#define REG_VIP_LCE_6F_H (REG_VIP_LCE_BASE + 0xDF) ++#define REG_VIP_LCE_70_L (REG_VIP_LCE_BASE + 0xE0) ++#define REG_VIP_LCE_70_H (REG_VIP_LCE_BASE + 0xE1) ++#define REG_VIP_LCE_71_L (REG_VIP_LCE_BASE + 0xE2) ++#define REG_VIP_LCE_71_H (REG_VIP_LCE_BASE + 0xE3) ++#define REG_VIP_LCE_72_L (REG_VIP_LCE_BASE + 0xE4) ++#define REG_VIP_LCE_72_H (REG_VIP_LCE_BASE + 0xE5) ++#define REG_VIP_LCE_73_L (REG_VIP_LCE_BASE + 0xE6) ++#define REG_VIP_LCE_73_H (REG_VIP_LCE_BASE + 0xE7) ++#define REG_VIP_LCE_74_L (REG_VIP_LCE_BASE + 0xE8) ++#define REG_VIP_LCE_74_H (REG_VIP_LCE_BASE + 0xE9) ++#define REG_VIP_LCE_75_L (REG_VIP_LCE_BASE + 0xEA) ++#define REG_VIP_LCE_75_H (REG_VIP_LCE_BASE + 0xEB) ++#define REG_VIP_LCE_76_L (REG_VIP_LCE_BASE + 0xEC) ++#define REG_VIP_LCE_76_H (REG_VIP_LCE_BASE + 0xED) ++#define REG_VIP_LCE_77_L (REG_VIP_LCE_BASE + 0xEE) ++#define REG_VIP_LCE_77_H (REG_VIP_LCE_BASE + 0xEF) ++#define REG_VIP_LCE_78_L (REG_VIP_LCE_BASE + 0xF0) ++#define REG_VIP_LCE_78_H (REG_VIP_LCE_BASE + 0xF1) ++#define REG_VIP_LCE_79_L (REG_VIP_LCE_BASE + 0xF2) ++#define REG_VIP_LCE_79_H (REG_VIP_LCE_BASE + 0xF3) ++#define REG_VIP_LCE_7A_L (REG_VIP_LCE_BASE + 0xF4) ++#define REG_VIP_LCE_7A_H (REG_VIP_LCE_BASE + 0xF5) ++#define REG_VIP_LCE_7B_L (REG_VIP_LCE_BASE + 0xF6) ++#define REG_VIP_LCE_7B_H (REG_VIP_LCE_BASE + 0xF7) ++#define REG_VIP_LCE_7C_L (REG_VIP_LCE_BASE + 0xF8) ++#define REG_VIP_LCE_7C_H (REG_VIP_LCE_BASE + 0xF9) ++#define REG_VIP_LCE_7D_L (REG_VIP_LCE_BASE + 0xFA) ++#define REG_VIP_LCE_7D_H (REG_VIP_LCE_BASE + 0xFB) ++#define REG_VIP_LCE_7E_L (REG_VIP_LCE_BASE + 0xFC) ++#define REG_VIP_LCE_7E_H (REG_VIP_LCE_BASE + 0xFD) ++#define REG_VIP_LCE_7F_L (REG_VIP_LCE_BASE + 0xFE) ++#define REG_VIP_LCE_7F_H (REG_VIP_LCE_BASE + 0xFF) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/halpnl.c b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/halpnl.c +new file mode 100644 +index 00000000..baeb437e +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/halpnl.c +@@ -0,0 +1,363 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_PNL_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++#include "ms_platform.h" ++// Internal Definition ++#include "hwreg.h" ++#include "halpnl_utility.h" ++#include "halpnl.h" ++#include "Infinity_pnl_lpll_tbl.h" ++#include "MsDbg.h" ++#include "mdrv_scl_dbg.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define DCLK_5MHZ 5000000 ++#define DCLK_10MHZ 10000000 ++#define DCLK_20MHZ 20000000 ++#define DCLK_40MHZ 40000000 ++#define DCLK_80MHZ 80000000 ++#define Is_full_pin_TTL() (Chip_Get_Package_Type()==MS_I3_PACKAGE_BGA_128MB||\ ++ Chip_Get_Package_Type()==MS_I3_PACKAGE_BGA_256MB||Chip_Get_Package_Type()==MS_I3_PACKAGE_DDR3_1866_128MB\ ++ ||Chip_Get_Package_Type()== MS_I3_PACKAGE_DDR3_1866_256MB) ++#define Is_Dclk_Less5M(Dclk) ((Dclk) <= DCLK_5MHZ) ++#define Is_Dclk_5MTo10M(Dclk) ((Dclk > DCLK_5MHZ) && (Dclk <= DCLK_10MHZ)) ++#define Is_Dclk_10MTo20M(Dclk) ((Dclk > DCLK_10MHZ) && (Dclk <= DCLK_20MHZ)) ++#define Is_Dclk_20MTo40M(Dclk) ((Dclk > DCLK_20MHZ) && (Dclk <= DCLK_40MHZ)) ++#define Is_Dclk_40MTo80M(Dclk) ((Dclk > DCLK_40MHZ) && (Dclk <= DCLK_80MHZ)) ++//------------------------------------------------------------------------------------------------- ++// Variable ++ ++MS_U32 PNL_RIU_BASE = 0; ++unsigned int gu32JTAGmode; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_PNL_Set_Riu_Base(MS_U32 u32Riubase) ++{ ++ PNL_RIU_BASE = u32Riubase; ++} ++void Hal_PNL_Set_Chiptop(MS_BOOL bEn) ++{ ++ if(bEn) ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0040,0x0040); ++ SCL_DBGERR("[PNL] ttlmode = ON\n"); ++ } ++ else ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0040); ++ SCL_DBGERR("[PNL] ttlmode = OFF\n"); ++ } ++ if(gu32JTAGmode) ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0002,0x0002); ++ SCL_DBGERR("[PNL] JTAGmode = ON\n"); ++ } ++ else ++ { ++ W2BYTEMSK(REG_CHIPTOP_0F_L,0x0000,0x0002); ++ SCL_DBGERR("[PNL] JTAGmode = OFF\n"); ++ } ++} ++ ++ ++void Hal_PNL_Set_Init_Y2R(void) ++{ ++ MS_U16 u16Coef[9]={0xcc4,0x950,0x3ffc,0x397e,0x0950,0x3cde,0x3ffe,0x950,0x1024};//hw setting ++ Hal_PNL_Set_CSC_Y2R_En(1); ++ Hal_PNL_Set_CSC_Y2R_Offset(0x10,0x80,0x80); ++ Hal_PNL_Set_CSC_Y2R_Coef(u16Coef); ++} ++void Hal_PNL_Set_VSync_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_01_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_VSync_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_02_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vfde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_03_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vfde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_04_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_05_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_06_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Vtt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_07_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_HSync_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_09_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_HSync_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0A_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hfde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0B_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hfde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0C_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hde_St(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0D_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Hde_End(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0E_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_Htt(MS_U16 u16Val) ++{ ++ W2BYTEMSK(REG_SCL2_0F_L, u16Val, 0x07FF); ++} ++ ++void Hal_PNL_Set_FrameColr_En(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL2_10_L, bEn ? BIT8 : 0, BIT8); ++} ++ ++#if ENABLE_PNL_UNUSED_FUNCTION ++void Hal_PNL_Set_FrameColor(MS_U32 u32Color) ++{ ++ W4BYTE(REG_SCL2_11_L, u32Color); ++} ++#endif ++ ++MS_U16 Hal_PNL_Get_Lpll_Idx(MS_U64 u64Dclk) ++{ ++ MS_U16 u16Idx = 0; ++ ++ if(Is_Dclk_Less5M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ; ++ } ++ else if(Is_Dclk_5MTo10M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ; ++ } ++ else if(Is_Dclk_10MTo20M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ; ++ } ++ else if(Is_Dclk_20MTo40M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ; ++ } ++ else if(Is_Dclk_40MTo80M(u64Dclk)) ++ { ++ u16Idx = E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ; ++ } ++ else ++ { ++ u16Idx = 0xFF; ++ } ++ return u16Idx; ++} ++ ++MS_U16 Hal_PNL_Get_Lpll_Gain(MS_U16 u16Idx) ++{ ++ return u16LoopGain[u16Idx]; ++} ++ ++MS_U16 Hal_PNL_Get_Lpll_Div(MS_U16 u16Idx) ++{ ++ return u16LoopDiv[u16Idx]; ++} ++ ++void Hal_PNL_Dump_Lpll_Setting(MS_U16 u16Idx) ++{ ++ MS_U16 u16RegIdx; ++ ++ for(u16RegIdx=0; u16RegIdx < LPLL_REG_NUM; u16RegIdx++) ++ { ++ ++ if(LPLLSettingTBL[u16Idx][u16RegIdx].address == 0xFF) ++ { ++ MsOS_DelayTask(LPLLSettingTBL[u16Idx][u16RegIdx].value); ++ continue; ++ } ++ ++ W2BYTEMSK((REG_SCL_LPLL_BASE | ((MS_U32)LPLLSettingTBL[u16Idx][u16RegIdx].address *2)), ++ LPLLSettingTBL[u16Idx][u16RegIdx].value, ++ LPLLSettingTBL[u16Idx][u16RegIdx].mask); ++ } ++ ++} ++ ++void Hal_PNL_Set_Lpll_Set(MS_U32 u32LpllSet) ++{ ++ MS_U16 u16LpllSet_Lo, u16LpllSet_Hi; ++ u16LpllSet_Lo = (MS_U16)(u32LpllSet & 0x0000FFFF); ++ u16LpllSet_Hi = (MS_U16)((u32LpllSet & 0x00FF0000) >> 16); ++ W2BYTE(REG_SCL_LPLL_48_L, u16LpllSet_Lo); ++ W2BYTE(REG_SCL_LPLL_49_L, u16LpllSet_Hi); ++} ++ ++void Hal_PNL_Set_OpenLpll_CLK(MS_U8 bLpllClk) ++{ ++ W2BYTEMSK(REG_SCL_CLK_66_L, bLpllClk ? 0x000C : 0x1, 0x000F); ++ Hal_PNL_Set_Chiptop(bLpllClk); ++} ++// CSC Y2R ++void Hal_PNL_Set_CSC_Y2R_En(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL2_19_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++void Hal_PNL_Set_CSC_Y2R_Offset(MS_U8 u8Y, MS_U8 u8Cb, MS_U8 u8Cr) ++{ ++ W2BYTEMSK(REG_SCL2_19_L, ((MS_U16)u8Y << 8), 0xFF00); ++ W2BYTE(REG_SCL2_1A_L, (((MS_U16)u8Cb << 8)|((MS_U16)u8Cr))); ++} ++ ++void Hal_PNL_Set_CSC_Y2R_Coef(MS_U16 *pu16Coef) ++{ ++ ++ MS_U8 u8idx; ++ ++ for(u8idx=0; u8idx<9; u8idx++) ++ { ++ W2BYTEMSK(REG_SCL2_1B_L + (u8idx<<1), pu16Coef[u8idx], 0x3FFF); ++ } ++} ++ ++ ++#undef HAL_PNL_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/Infinity_pnl_lpll_tbl.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/Infinity_pnl_lpll_tbl.h +new file mode 100644 +index 00000000..4ccefde2 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/Infinity_pnl_lpll_tbl.h +@@ -0,0 +1,227 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++ ++#ifndef _LPLL_TBL_H_ ++#define _LPLL_TBL_H_ ++ ++#define LPLL_REG_NUM 17 ++ ++typedef enum ++{ ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ, //0 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ, //1 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ, //2 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ, //3 ++ E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ, //4 ++ ++ E_PNL_SUPPORTED_LPLL_MAX, //5 ++} E_PNL_SUPPORTED_LPLL_TYPE; ++ ++typedef struct ++{ ++ MS_U8 address; ++ MS_U16 value; ++ MS_U16 mask; ++}TBLStruct,*pTBLStruct; ++ ++TBLStruct LPLLSettingTBL[E_PNL_SUPPORTED_LPLL_MAX][LPLL_REG_NUM]= ++{ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ NO.0 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0002,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0050,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ NO.1 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0050,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ NO.2 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x00A0,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0000,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ NO.3 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0080,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++ { //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ NO.4 ++ //Address,Value,Mask ++ {0x40,0x0000,0x8000},//reg_lpll_ext_pd ++ {0x40,0x0001,0x0007},//reg_lpll_ext_ictrl ++ {0x41,0x0000,0x0003},//reg_lpll_ext_input_div_fst ++ {0x41,0x0020,0x0030},//reg_lpll_ext_loop_div_fst ++ {0x41,0x0300,0x0F00},//reg_lpll_ext_loop_div_sec ++ {0x42,0x0003,0x0003},//reg_lpll_ext_scalar_div_fst ++ {0x42,0x0080,0x00F0},//reg_lpll_ext_scalar_div_sec ++ {0x43,0x0007,0x0007},//reg_lpll_ext_skew_div ++ {0x42,0x0000,0x0700},//reg_lpll_ext_fifo_div ++ {0x43,0x0010,0x0010},//reg_lpll_ext_skew_en_fixclk ++ {0x40,0x0000,0x0800},//reg_lpll_ext_dual_lp_en ++ {0x40,0x0100,0x0100},//reg_lpll_ext_sdiv2p5_en ++ {0x40,0x2000,0x2000},//reg_lpll_ext_en_mini ++ {0x40,0x0000,0x0400},//reg_lpll_ext_en_fifo ++ {0x40,0x0200,0x0200},//reg_lpll_ext_en_scalar ++ {0x40,0x0000,0x1000},//reg_lpll_ext_fifo_div5_en ++ {0x40,0x0000,0x0008},//reg_lpll_ext_sdiv3p5_en ++ }, ++ ++}; ++MS_U16 u16LoopGain[E_PNL_SUPPORTED_LPLL_MAX]= ++{ ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ NO.0 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ NO.1 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ NO.2 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ NO.3 ++ 12, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ NO.4 ++}; ++MS_U16 u16LoopDiv[E_PNL_SUPPORTED_LPLL_MAX]= ++{ ++ 20, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_40TO80MHZ NO.0 ++ 40, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_20TO40MHZ NO.1 ++ 80, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_10TO20MHZ NO.2 ++ 160, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO10MHZ NO.3 ++ 160, //E_PNL_SUPPORTED_LPLL_HS_LVDS_CH_5TO5MHZ NO.4 ++}; ++ ++#endif //_LPLL_TBL_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/halpnl.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/halpnl.h +new file mode 100644 +index 00000000..a05c83c3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/halpnl.h +@@ -0,0 +1,148 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_PNL_H ++#define _HAL_PNL_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_PNL_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_PNL_Set_Riu_Base(MS_U32 u32Riubase); ++INTERFACE void Hal_PNL_Set_Chiptop(MS_BOOL bEn); ++INTERFACE void Hal_PNL_Set_Init_Y2R(void); ++INTERFACE void Hal_PNL_Set_VSync_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_VSync_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vfde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vfde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Vtt(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_HSync_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_HSync_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hfde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hfde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hde_St(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Hde_End(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_Htt(MS_U16 u16Val); ++INTERFACE void Hal_PNL_Set_FrameColr_En(MS_BOOL bEn); ++INTERFACE void Hal_PNL_Set_FrameColor(MS_U32 u32Color); ++INTERFACE void Hal_PNL_Dump_Lpll_Setting(MS_U16 u16Idx); ++INTERFACE void Hal_PNL_Set_Lpll_Set(MS_U32 u32LpllSet); ++INTERFACE MS_U16 Hal_PNL_Get_Lpll_Idx(MS_U64 u64Dclk); ++INTERFACE MS_U16 Hal_PNL_Get_Lpll_Gain(MS_U16 u16Idx); ++INTERFACE MS_U16 Hal_PNL_Get_Lpll_Div(MS_U16 u16Idx); ++INTERFACE void Hal_PNL_Set_CSC_Y2R_En(MS_BOOL bEn); ++INTERFACE void Hal_PNL_Set_CSC_Y2R_Offset(MS_U8 u8Y, MS_U8 u8Cb, MS_U8 u8Cr); ++INTERFACE void Hal_PNL_Set_CSC_Y2R_Coef(MS_U16 *pu16Coef); ++INTERFACE void Hal_PNL_Set_OpenLpll_CLK(MS_U8 bLpllClk); ++ ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/halpnl_utility.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/halpnl_utility.h +new file mode 100644 +index 00000000..f0349781 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/halpnl_utility.h +@@ -0,0 +1,54 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALPNL_UTILITY_H_ ++#define _HALPNL_UTILITY_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 PNL_RIU_BASE; // This should be inited before XC library starting. ++extern unsigned int gu32JTAGmode; ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( PNL_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( PNL_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (PNL_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( PNL_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/infinity_lpll_setting.xlsm b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/infinity_lpll_setting.xlsm +new file mode 100644 +index 00000000..d1835f45 +Binary files /dev/null and b/drivers/mstar/scl/infinity3/src/mxlib/hal/pnl/include/infinity_lpll_setting.xlsm differ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/halscldma.c b/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/halscldma.c +new file mode 100644 +index 00000000..c481da6a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/halscldma.c +@@ -0,0 +1,2026 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_SCLDMA_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++#endif ++//#include ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg.h" ++#include "halscldma_utility.h" ++#include "drvscldma_st.h" ++#include "halscldma.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "mdrv_scl_dbg.h" ++//#include ++//#include ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define HAL_SCLDMA_ERR(x) x ++#define DISABLE_CLK 0x1 ++#define LOW_CLK 0x4 ++#define Is_CLK_Increase(height,width,rate) (((height) > 720 || (width) > 1280)&& (rate) < 172000000) ++#define Is_CLK_Decrease(height,width,rate) (((height) <= 720 && (width) <= 1280)&& (rate) >= 172000000) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_U32 SCLDMA_RIU_BASE = 0; ++MS_U16 u16gheight[2] = {1080,720}; ++MS_U16 u16gwidth[2] = {1920,1280}; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_SCLDMA_SetRiuBase(MS_U32 u32riubase) ++{ ++ SCLDMA_RIU_BASE = u32riubase; ++} ++void Hal_SCLDMA_Set_SW_Reset(void) ++{ ++ W2BYTEMSK(REG_SCL0_01_L,0x1E,0x1E); ++ W2BYTEMSK(REG_SCL0_01_L,0,0x1E); ++} ++void Hal_SCLDMA_SetReqLen(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_19_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_49_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_49_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_61_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM2_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_61_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_79_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_31_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_19_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_31_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_SetReqTh(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_19_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_49_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_49_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_61_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM2_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_61_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_79_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_31_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_19_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_31_L, ((MS_U16)u8value), 0x00FF); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_SetPriThd(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_18_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_48_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_48_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_60_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM2_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_60_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_78_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_30_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_18_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_30_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_HKForceAuto(void) ++{ ++ // sc22sc2_hk_force_auto, sc2out_hk_force_auto ++ W2BYTEMSK(REG_SCL0_03_L, BIT11|BIT10|BIT9|BIT8|BIT2|BIT1|BIT0, BIT11|BIT10|BIT9|BIT8|BIT2|BIT1|BIT0); ++} ++void Hal_SCLDMA_SC3DbHWAuto(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_06_L, bEn ? BIT4 :0, BIT4); ++} ++void Hal_SCLDMA_DbHWAuto(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_06_L, bEn ? BIT3 :0, BIT3); ++} ++void Hal_SCLDMA_HKHWAutoMd(MS_BOOL bDbmode) ++{ ++ W2BYTEMSK(REG_SCL0_06_L, bDbmode ? BIT6 : 0, BIT6); ++} ++void Hal_SCLDMA_HKHWAuto(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_06_L, bEn ? BIT5 :0, BIT5); ++} ++void Hal_SCLDMA_HWInit(void) ++{ ++ Hal_SCLDMA_HKForceAuto(); ++ //Hal_SCLDMA_HKHWAuto(1); ++ Hal_SCLDMA_DbHWAuto(1); ++ Hal_SCLDMA_SetMCMByDMAClient(E_SCLDMA_1_SNP_W,0); ++ Hal_SCLDMA_SetPriThd(E_SCLDMA_3_FRM_R,0x08); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_3_FRM_R,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_3_FRM_R,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_3_FRM_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_3_FRM_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_1_FRM_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_1_FRM_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_1_SNP_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_1_SNP_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_2_FRM_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_2_FRM_W,0x12); ++ Hal_SCLDMA_SetReqLen(E_SCLDMA_2_FRM2_W,0x10); ++ Hal_SCLDMA_SetReqTh(E_SCLDMA_2_FRM2_W,0x12); ++ Hal_SCLDMA_Set_SW_Reset(); ++ ++} ++#if CONFIG_OF ++void Hal_SCLDMA_CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* stclock = NULL; ++ MS_U32 u32Events; ++ if(Drv_SCLIRQ_GetEachDMAEn()|| (!Drv_SCLIRQ_GetIsBlankingRegion())) ++ { ++ HAL_SCLDMA_ERR(printf("[FCLK]%s %d,Wait\n", __FUNCTION__, __LINE__)); ++ MsOS_WaitEvent(Drv_SCLIRQ_Get_IRQ_SYNCEventID(), ++ (E_SCLIRQ_EVENT_ISPFRMEND|E_SCLIRQ_EVENT_FRMENDSYNC), &u32Events, E_AND, 200); // get status: FRM END ++ } ++ if(bEn) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//To Do ++ if (MsOS_clk_get_enable_count(stclk->fclk1) == 0) ++ { ++#if CLKDynamic ++ if(Is_CLK_Increase(u16gheight[0],u16gwidth[0],0)) ++#else ++ if(1) ++#endif ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, stclock); ++ MsOS_clk_prepare_enable(stclk->fclk1); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ #if OSDinverseBug ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ MsOS_clk_prepare_enable(stclk->fclk2); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #endif ++ } ++ else ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, stclock); ++ MsOS_clk_prepare_enable(stclk->fclk1); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ #if OSDinverseBug ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ MsOS_clk_prepare_enable(stclk->fclk2); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #endif ++ } ++ } ++ #if CLKDynamic ++ else ++ { ++ if(Is_CLK_Increase(u16gheight[0],u16gwidth[0], MsOS_clk_get_rate(stclk->fclk1))) ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ #if OSDinverseBug ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #endif ++ } ++ else if(Is_CLK_Decrease(u16gheight[0],u16gwidth[0], MsOS_clk_get_rate(stclk->fclk1))) ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ #if OSDinverseBug ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++ #endif ++ } ++ } ++#endif ++ } ++ else ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk1, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk1, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++#if OSDinverseBug ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlHVSP]CLK Tree Not Ready \n"); ++ } ++#endif ++ while (MsOS_clk_get_enable_count(stclk->fclk1)) ++ { ++ MsOS_clk_disable_unprepare(stclk->fclk1); ++ } ++ #if OSDinverseBug ++ while (MsOS_clk_get_enable_count(stclk->fclk2)) ++ { ++ MsOS_clk_disable_unprepare(stclk->fclk2); ++ } ++ #endif ++ } ++} ++ ++void Hal_SCLDMA_SC3CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++#if OSDinverseBug ++#else ++ struct clk* stclock = NULL; ++ if(bEn) ++ { ++ if (MsOS_clk_get_enable_count(stclk->fclk2) == 0) ++ { ++ if(Is_CLK_Increase(u16gheight[1],u16gwidth[1],0)) ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ MsOS_clk_prepare_enable(stclk->fclk2); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ } ++ else ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ MsOS_clk_prepare_enable(stclk->fclk2); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ } ++ } ++ else ++ { ++ if(Is_CLK_Increase(u16gheight[1],u16gwidth[1], MsOS_clk_get_rate(stclk->fclk2))) ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ } ++ else if(Is_CLK_Decrease(u16gheight[1],u16gwidth[1], MsOS_clk_get_rate(stclk->fclk2))) ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 1))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ if (NULL != (stclock = MsOS_clk_get_parent_by_index(stclk->fclk2, 0))) ++ { ++ MsOS_clk_set_parent(stclk->fclk2, stclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ while (MsOS_clk_get_enable_count(stclk->fclk2)) ++ { ++ MsOS_clk_disable_unprepare(stclk->fclk2); ++ } ++ } ++#endif ++} ++void Hal_SCLDMA_ODCLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* pstclock = NULL; ++ if(bEn) ++ { ++ if(MsOS_clk_get_enable_count(stclk->odclk)==0) ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->odclk, 3))) ++ { ++ MsOS_clk_set_parent(stclk->odclk, pstclock); ++ MsOS_clk_prepare_enable(stclk->odclk); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ } ++ else ++ { ++ printf("[odclk]CAN'T/Already OPEN\n"); ++ } ++ ++ } ++ else ++ { ++ if (NULL != (pstclock = MsOS_clk_get_parent_by_index(stclk->odclk, 0))) ++ { ++ MsOS_clk_set_parent(stclk->odclk, pstclock); ++ } ++ else ++ { ++ SCL_ERR("[HAlSCLDMA]CLK Tree Not Ready \n"); ++ } ++ while (MsOS_clk_get_enable_count(stclk->odclk)) ++ { ++ MsOS_clk_disable_unprepare(stclk->odclk); ++ } ++ } ++} ++ ++#else ++void Hal_SCLDMA_CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ MS_U16 regclk; ++ printf("[hal]NO OF\n"); ++ if(bEn) ++ { ++ if ((R2BYTE(REG_SCL_CLK_64_L)&DISABLE_CLK)) ++ { ++ if(Is_CLK_Increase(u16gheight[0],u16gwidth[0],0)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ } ++ else ++ { ++ if((u16gheight[0] > 720 || u16gwidth[0] > 1280)&& (R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ else if((u16gheight[0] <= 720 && u16gwidth[0] <= 1280)&& !(R2BYTE(REG_SCL_CLK_64_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_64_L); ++ } ++ } ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_64_L,0x0,0x000F);//h61 ++ } ++} ++ ++void Hal_SCLDMA_SC3CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ MS_U16 regclk; ++ if(bEn) ++ { ++ if ((R2BYTE(REG_SCL_CLK_65_L)&DISABLE_CLK)) ++ { ++ if(Is_CLK_Increase(u16gheight[1],u16gwidth[1],0)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ } ++ else ++ { ++ if((u16gheight[1] > 720 || u16gwidth[1] > 1280) && (R2BYTE(REG_SCL_CLK_65_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0000,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ else if((u16gheight[1] <= 720 && u16gwidth[1] <= 1280) && !(R2BYTE(REG_SCL_CLK_65_L)&LOW_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,LOW_CLK,0x000F);//h61 ++ regclk = R2BYTE(REG_SCL_CLK_65_L); ++ } ++ } ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_65_L,0x0,0x000F);//h61 ++ } ++} ++void Hal_SCLDMA_ODCLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk) ++{ ++ struct clk* pstclock = NULL; ++ if(bEn) ++ { ++ if((R2BYTE(REG_SCL_CLK_66_L)&DISABLE_CLK)) ++ { ++ W2BYTEMSK(REG_SCL_CLK_66_L,0x000C,0x000F);//h66 ++ } ++ else ++ { ++ printf("[odclk]CAN'T/Already OPEN\n"); ++ } ++ ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_CLK_66_L,0x000D,0x000F);//h66 ++ } ++} ++ ++#endif ++ ++void Hal_SCLDMA_SetSC2HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT0, BIT0); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT1, BIT1); ++ } ++ else if(enRWMode == E_SCLDMA_FRM2_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT2, BIT2); ++ } ++} ++ ++void Hal_SCLDMA_SetSC1HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT9, BIT9); ++ } ++ else if(enRWMode == E_SCLDMA_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT10, BIT10); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, bEn ? 0 : BIT11, BIT11); ++ } ++ ++ //HAL_SCLDMA_ERR(printf("[HalSCLDMA]HK_Force:%hx\n", R2BYTE(REG_SCL0_02_L))); ++} ++ ++void Hal_SCLDMA_SetSC1ToSC2HandshakeForce(MS_BOOL bEn) ++{ ++ if((R2BYTE(REG_SCL0_02_L)&0x7) == 0x7 && bEn==0) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, BIT8, BIT8); ++ } ++ else if((R2BYTE(REG_SCL0_02_L)&0xF) != 0x7 && bEn) ++ { ++ W2BYTEMSK(REG_SCL0_02_L, 0, BIT8); ++ } ++} ++void Hal_SCLDMA_SetMCMByDMAClient(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_MCM_06_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_MCM_07_L, u8value, 0xFF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_MCM_10_L, u8value, 0xFF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_MCM_08_L, u8value, 0xFF); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_MCM_10_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_MCM_08_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_4_FRM_R) ++ { ++ W2BYTEMSK(REG_MCM_07_L, ((MS_U16)u8value<<8), 0xFF00); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++void Hal_SCLDMA_SetCheckFrmEndSignal(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_BOOL bEn) ++{ ++ if(enSCLDMA_ID == E_SCLDMA_1_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT11 : 0, BIT11); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT12 : 0, BIT12); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_1_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT13 : 0, BIT13); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT10 : 0, BIT10); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_FRM2_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT14 : 0, BIT14); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_2_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT9 : 0, BIT9); ++ } ++ else if(enSCLDMA_ID == E_SCLDMA_3_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT8 : 0, BIT8); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong enSCLDMA_ID: %d\n", __FUNCTION__, __LINE__, enSCLDMA_ID)); ++ } ++} ++ ++void Hal_SCLDMA_SetSC1DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_01_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_SNP_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_03_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_03_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ //HAL_SCLDMA_ERR(printf("[HalSCLDMA]DMA1_En:%hx\n", R2BYTE(REG_SCL_DMA0_01_L))); ++ ++} ++void Hal_SCLDMA_GetHVSPResolutionForEnsure(MS_U16 u16height) ++{ ++ MS_U16 u16Srcheight,u16Dspheight,u16FBheight; ++ MS_U16 u16Srcwidth,u16Dspwidth,u16FBwidth; ++ u16Srcheight = R2BYTE(REG_SCL_HVSP0_21_L); ++ u16Dspheight = R2BYTE(REG_SCL_HVSP0_23_L); ++ u16FBheight = R2BYTE(REG_SCL_DNR1_0D_L); ++ u16Srcwidth = R2BYTE(REG_SCL_HVSP0_20_L); ++ u16Dspwidth = R2BYTE(REG_SCL_HVSP0_22_L); ++ u16FBwidth = R2BYTE(REG_SCL_DNR1_0E_L); ++ if(u16Srcheight>0) ++ { ++ u16gheight[0] = (u16Srcheight>u16Dspheight) ? u16Srcheight : u16Dspheight ; ++ u16gheight[0] = (u16FBheight>u16gheight[0])? u16FBheight: u16gheight[0]; ++ u16gwidth[0] = (u16Srcwidth>u16Dspwidth) ? u16Srcwidth : u16Dspwidth ; ++ u16gwidth[0] = (u16FBwidth>u16gwidth[0])? u16FBwidth: u16gwidth[0]; ++ } ++ u16Srcheight = R2BYTE(REG_SCL_HVSP2_21_L); ++ u16Dspheight = R2BYTE(REG_SCL_HVSP2_23_L); ++ u16Srcwidth = R2BYTE(REG_SCL_HVSP2_20_L); ++ u16Dspwidth = R2BYTE(REG_SCL_HVSP2_22_L); ++ if(u16Srcheight>0) ++ { ++ u16gheight[1] = (u16Srcheight>u16Dspheight) ? u16Srcheight : u16Dspheight ; ++ u16gwidth[1] = (u16Srcwidth>u16Dspwidth) ? u16Srcwidth : u16Dspwidth ; ++ } ++ ++} ++MS_U16 Hal_GetHVSPOutputHSize(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U16 u16Width; ++ u16Width = (enSCLDMA_ID == E_SCLDMA_ID_1_W) ?R2BYTE(REG_SCL_HVSP0_22_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_2_W) ?R2BYTE(REG_SCL_HVSP1_22_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_W) ?R2BYTE(REG_SCL_HVSP2_22_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_R) ?R2BYTE(REG_SCL_HVSP2_20_L) : ++ 0; ++ return u16Width; ++} ++MS_U16 Hal_GetHVSPOutputVSize(EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ MS_U16 u16Height; ++ u16Height = (enSCLDMA_ID == E_SCLDMA_ID_1_W) ? R2BYTE(REG_SCL_HVSP0_23_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_2_W) ? R2BYTE(REG_SCL_HVSP1_23_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_W) ? R2BYTE(REG_SCL_HVSP2_23_L) : ++ (enSCLDMA_ID == E_SCLDMA_ID_3_R) ? R2BYTE(REG_SCL_HVSP2_21_L) : ++ 0; ++ return u16Height; ++} ++void Hal_SCLDMA_SetSC1DMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ MS_U8 u8420md; ++ MS_U8 u8DataMd; ++ if(stSCLDMACfg->enRWMode == E_SCLDMA_FRM_W) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_08_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_10_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_38_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_0A_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_12_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_3A_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_0C_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_14_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_3C_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_0E_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_16_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_3E_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_18_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_18_L, 0, BIT4|BIT3); ++ } ++ Hal_SCLDMA_GetHVSPResolutionForEnsure(stSCLDMACfg->u16Height); ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA0_1E_L, u8420md, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA0_1E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA0_01_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_20_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg->enRWMode == E_SCLDMA_SNP_W) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_38_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_40_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_40_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_3A_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_42_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_42_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_3C_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_44_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_44_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_3E_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_46_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_46_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_48_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_48_L, 0, BIT4|BIT3); ++ } ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA0_4E_L, u8420md, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA0_4E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA0_03_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_22_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg->enRWMode == E_SCLDMA_IMI_W) ++ { ++#if ENABLE_RING_DB ++ u32yoffset = 0x20; ++ u32coffset = 0x20; ++#else ++ if((stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420)||(stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420)) ++ { ++ u32yoffset=(stSCLDMACfg->u16Width*16)/8-1; ++ u32coffset=(stSCLDMACfg->u16Width*8)/8-1; ++ } ++ else ++ { ++ u32yoffset=(stSCLDMACfg->u16Width*16)/8-2; ++ u32coffset=(stSCLDMACfg->u16Width*16)/8-2; ++ } ++#endif ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_38_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_68_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_3A_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_42_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_6A_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_3C_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_44_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_6C_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_3E_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_46_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_6E_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_48_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA1_48_L, 0, BIT4|BIT3); ++ } ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, u8420md, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_03_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_2C_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ W4BYTE(REG_SCL_DMA2_40_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_42_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL0_64_L,0, BIT15); // sc1 open ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg->enRWMode)); ++ } ++ if(Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W)==stSCLDMACfg->u16Width ||(Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W) == 0)) ++ { ++ W2BYTE(REG_SCL_DMA0_1A_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA1_4A_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA0_4A_L, stSCLDMACfg->u16Width); ++ } ++ else ++ { ++ W2BYTE(REG_SCL_DMA0_1A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W)); ++ W2BYTE(REG_SCL_DMA1_4A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W)); ++ W2BYTE(REG_SCL_DMA0_4A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_1_W)); ++ } ++ if(Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W) == stSCLDMACfg->u16Height ||(Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W) == 0)) ++ { ++ W2BYTE(REG_SCL_DMA0_1B_L, stSCLDMACfg->u16Height); ++ W2BYTE(REG_SCL_DMA1_4B_L, stSCLDMACfg->u16Height); ++ W2BYTE(REG_SCL_DMA0_4B_L, stSCLDMACfg->u16Height); ++ } ++ else ++ { ++ W2BYTE(REG_SCL_DMA0_1B_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W)); ++ W2BYTE(REG_SCL_DMA1_4B_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W)); ++ W2BYTE(REG_SCL_DMA0_4B_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_1_W)); ++ } ++ ++} ++void Hal_SCLDMA_SetIMIClientReset(void) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ u32yoffset = 0x0; ++ u32coffset = 0x0; ++ W4BYTE(REG_SCL_DMA1_38_L, 0); ++ W4BYTE(REG_SCL_DMA1_40_L, 0); ++ W4BYTE(REG_SCL_DMA1_3A_L, 0); ++ W4BYTE(REG_SCL_DMA1_42_L, 0); ++ W4BYTE(REG_SCL_DMA1_3C_L, 0); ++ W4BYTE(REG_SCL_DMA1_44_L, 0); ++ W4BYTE(REG_SCL_DMA1_3E_L, 0); ++ W4BYTE(REG_SCL_DMA1_46_L, 0); ++ ++ W2BYTEMSK(REG_SCL_DMA1_48_L, 0, BIT4|BIT3); ++ W2BYTE(REG_SCL_DMA1_4A_L, 0); ++ W2BYTE(REG_SCL_DMA1_4B_L, 0); ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, 0, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA1_4E_L, 0, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_03_L, 0, BIT14); // w_422_pack[14] ++ W4BYTE(REG_SCL_DMA2_40_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_42_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL0_64_L,0, BIT15); // sc1 open ++ ++} ++void Hal_SCLDMA_SetDMAOutputBufferAddr ++ (EN_SCLDMA_CLIENT_TYPE enClientType,unsigned long u32YBufferAddr,unsigned long u32CBufferAddr,unsigned long u32VBufferAddr) ++{ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ W4BYTE(REG_SCL_DMA0_08_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_10_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_38_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ W4BYTE(REG_SCL_DMA1_38_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_68_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ W4BYTE(REG_SCL_DMA0_38_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_40_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_40_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ W4BYTE(REG_SCL_DMA0_50_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_58_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_48_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_2_FRM2_W: ++ W4BYTE(REG_SCL_DMA1_50_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_58_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_70_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ W4BYTE(REG_SCL_DMA1_38_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_40_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_50_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ W4BYTE(REG_SCL_DMA1_20_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_28_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_60_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ W4BYTE(REG_SCL_DMA1_08_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA1_10_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_58_L, u32CBufferAddr>>3); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ W4BYTE(REG_SCL_DMA0_20_L, u32YBufferAddr>>3); ++ W4BYTE(REG_SCL_DMA0_28_L, u32CBufferAddr>>3); ++ W4BYTE(REG_SCL3_30_L, u32CBufferAddr>>3); ++ break; ++ default: ++ break; ++ } ++ ++} ++ ++void Hal_SCLDMA_SetSC2DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_04_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_FRM2_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_04_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_IMI_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_05_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ ++} ++ ++void Hal_SCLDMA_SetSC2DMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ MS_U8 u8420md; ++ MS_U8 u8DataMd; ++ if(stSCLDMACfg->enRWMode == E_SCLDMA_FRM_W) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_50_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_58_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_48_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_52_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_5A_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_4A_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_54_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_5C_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_4C_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_56_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_5E_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_4E_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_60_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_60_L, 0, BIT4|BIT3); ++ } ++ W2BYTEMSK(REG_SCL_DMA0_66_L, BIT2, BIT2); ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA0_66_L, u8420md, BIT3); ++ W2BYTEMSK(REG_SCL_DMA0_04_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_24_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg->enRWMode == E_SCLDMA_FRM2_W) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_50_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_58_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_70_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_52_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_5A_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_72_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_54_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_5C_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_74_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_56_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_5E_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_76_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_60_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA1_60_L, 0, BIT4|BIT3); ++ } ++ W2BYTEMSK(REG_SCL_DMA1_66_L, BIT2, BIT2); ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA1_66_L, u8420md, BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_04_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_2E_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg->enRWMode == E_SCLDMA_IMI_W) ++ { ++ ++ if((stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420)||(stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420)) ++ { ++ u32yoffset=(stSCLDMACfg->u16Width*16)/8-1; ++ u32coffset=(stSCLDMACfg->u16Width*8)/8-1; ++ } ++ else ++ { ++ u32yoffset=(stSCLDMACfg->u16Width*16)/8-2; ++ u32coffset=(stSCLDMACfg->u16Width*16)/8-2; ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_68_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_70_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_50_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_6A_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_72_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_52_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_6C_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_74_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_54_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_6E_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_76_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_56_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_78_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_78_L, 0, BIT4|BIT3); ++ } ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA0_7E_L, u8420md, BIT3); // w_422to420_md[3] ++ W2BYTEMSK(REG_SCL_DMA0_7E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA0_05_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); // w_422_pack[14] ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_26_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ W4BYTE(REG_SCL_DMA2_44_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_46_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL0_64_L,BIT15, BIT15); //sc2 open ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg->enRWMode)); ++ } ++ if(Hal_GetHVSPOutputHSize(E_SCLDMA_ID_2_W)==stSCLDMACfg->u16Width ||(Hal_GetHVSPOutputHSize(E_SCLDMA_ID_2_W) == 0)) ++ { ++ W2BYTE(REG_SCL_DMA0_62_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA1_62_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA0_7A_L, stSCLDMACfg->u16Width); ++ } ++ else ++ { ++ W2BYTE(REG_SCL_DMA0_62_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_2_W)); ++ W2BYTE(REG_SCL_DMA1_62_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_2_W)); ++ W2BYTE(REG_SCL_DMA0_7A_L, Hal_GetHVSPOutputHSize(E_SCLDMA_ID_2_W)); ++ } ++ if(Hal_GetHVSPOutputVSize(E_SCLDMA_ID_2_W) == stSCLDMACfg->u16Height ||(Hal_GetHVSPOutputVSize(E_SCLDMA_ID_2_W) == 0)) ++ { ++ W2BYTE(REG_SCL_DMA0_63_L, stSCLDMACfg->u16Height); ++ W2BYTE(REG_SCL_DMA1_63_L, stSCLDMACfg->u16Height); ++ W2BYTE(REG_SCL_DMA0_7B_L, stSCLDMACfg->u16Height); ++ } ++ else ++ { ++ W2BYTE(REG_SCL_DMA0_63_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_2_W)); ++ W2BYTE(REG_SCL_DMA1_63_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_2_W)); ++ W2BYTE(REG_SCL_DMA0_7B_L, Hal_GetHVSPOutputVSize(E_SCLDMA_ID_2_W)); ++ } ++} ++ ++ ++void Hal_SCLDMA_SetSC3DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_FRM_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_02_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else if(enRWMode == E_SCLDMA_FRM_W) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_01_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ ++} ++ ++void Hal_SCLDMA_SetSC3DMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg) ++{ ++ MS_U32 u32yoffset; ++ MS_U32 u32coffset; ++ MS_U8 u8420md; ++ MS_U8 u8DataMd; ++ if(stSCLDMACfg->enRWMode == E_SCLDMA_FRM_R) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_20_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_28_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_60_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_22_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_2A_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_62_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_24_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_2C_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_64_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_26_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_2E_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_66_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_30_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA1_30_L, 0, BIT4|BIT3); ++ } ++ W2BYTE(REG_SCL_DMA1_32_L, stSCLDMACfg->u16Width ); ++ W2BYTE(REG_SCL_DMA1_33_L, stSCLDMACfg->u16Height); ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422? BIT7 : 0; ++ W2BYTEMSK(REG_SCL_DMA1_36_L, u8420md, BIT7); ++ W2BYTEMSK(REG_SCL_DMA1_36_L, 0x06, 0x0F); //422to444_md[1:0], 420to422_md[2], 420to422_md_avg[3] ++ W2BYTEMSK(REG_SCL_DMA1_02_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_2A_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ } ++ else if(stSCLDMACfg->enRWMode == E_SCLDMA_FRM_W) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_08_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_10_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_58_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_0A_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_12_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_5A_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_0C_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_14_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_5C_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_0E_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_16_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_5E_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA1_18_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA1_18_L, 0, BIT4|BIT3); ++ } ++ W2BYTE(REG_SCL_DMA1_1A_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA1_1B_L, stSCLDMACfg->u16Height); ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420 ? BIT3 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT3 : ++ 0; ++ W2BYTEMSK(REG_SCL_DMA1_1E_L, u8420md, BIT3); ++ W2BYTEMSK(REG_SCL_DMA1_1E_L, BIT2, BIT2); ++ W2BYTEMSK(REG_SCL_DMA1_01_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_28_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ Hal_SCLDMA_GetHVSPResolutionForEnsure(stSCLDMACfg->u16Height); ++ ++ } ++ else if(stSCLDMACfg->enRWMode == E_SCLDMA_IMI_R) ++ { ++ if((stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV420)||(stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420)) ++ { ++ u32yoffset=(stSCLDMACfg->u16Width*16)/8-1; ++ u32coffset=(stSCLDMACfg->u16Width*8)/8-1; ++ } ++ else ++ { ++ u32yoffset=(stSCLDMACfg->u16Width*16)/8-2; ++ u32coffset=(stSCLDMACfg->u16Width*16)/8-2; ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA1_20_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA1_28_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_60_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA1_22_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA1_2A_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_62_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA1_24_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA1_2C_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_64_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA1_26_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA1_2E_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_66_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ ++ W2BYTEMSK(REG_SCL_DMA1_30_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ W2BYTE(REG_SCL_DMA1_32_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA1_33_L, stSCLDMACfg->u16Height); ++ ++ W2BYTEMSK(REG_SCL_DMA1_36_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT7 : 0, BIT7); ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_2A_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ W2BYTEMSK(REG_SCL_DMA1_36_L, 0x06, 0x0F); //422to444_md[1:0], 420to422_md[2], 420to422_md_avg[3] ++ W4BYTE(REG_SCL_DMA2_48_L, u32yoffset); // imi offset y ++ W4BYTE(REG_SCL_DMA2_4A_L, u32coffset); // imi offset c ++ W2BYTEMSK(REG_SCL_DMA2_02_L, 0x01,0x01); // SC3 mode ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg->enRWMode)); ++ } ++ ++} ++ ++void Hal_SCLDMA_SetDisplayDMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn) ++{ ++ if(enRWMode == E_SCLDMA_DBG_R) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_02_L, bEn ? BIT15 : 0, BIT15); ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, enRWMode)); ++ } ++ ++} ++ ++ ++void Hal_SCLDMA_SetDisplayDMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg) ++{ ++ MS_U8 u8420md; ++ MS_U8 u8DataMd; ++ if(stSCLDMACfg->enRWMode == E_SCLDMA_DBG_R) ++ { ++ if(stSCLDMACfg->bvFlag.btsBase_0) ++ { ++ W4BYTE(REG_SCL_DMA0_20_L, stSCLDMACfg->u32Base_Y[0]>>3); ++ W4BYTE(REG_SCL_DMA0_28_L, stSCLDMACfg->u32Base_C[0]>>3); ++ W4BYTE(REG_SCL3_30_L, stSCLDMACfg->u32Base_V[0]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_1) ++ { ++ W4BYTE(REG_SCL_DMA0_22_L, stSCLDMACfg->u32Base_Y[1]>>3); ++ W4BYTE(REG_SCL_DMA0_2A_L, stSCLDMACfg->u32Base_C[1]>>3); ++ W4BYTE(REG_SCL3_32_L, stSCLDMACfg->u32Base_V[1]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_2) ++ { ++ W4BYTE(REG_SCL_DMA0_24_L, stSCLDMACfg->u32Base_Y[2]>>3); ++ W4BYTE(REG_SCL_DMA0_2C_L, stSCLDMACfg->u32Base_C[2]>>3); ++ W4BYTE(REG_SCL3_34_L, stSCLDMACfg->u32Base_V[2]>>3); ++ } ++ if(stSCLDMACfg->bvFlag.btsBase_3) ++ { ++ W4BYTE(REG_SCL_DMA0_26_L, stSCLDMACfg->u32Base_Y[3]>>3); ++ W4BYTE(REG_SCL_DMA0_2E_L, stSCLDMACfg->u32Base_C[3]>>3); ++ W4BYTE(REG_SCL3_36_L, stSCLDMACfg->u32Base_V[3]>>3); ++ } ++ if(stSCLDMACfg->enBuffMode == E_SCLDMA_BUF_MD_RING) ++ { ++ W2BYTEMSK(REG_SCL_DMA0_30_L, stSCLDMACfg->u8MaxIdx<<3, BIT4|BIT3); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL_DMA0_30_L, 0, BIT4|BIT3); ++ } ++ W2BYTE(REG_SCL_DMA0_32_L, stSCLDMACfg->u16Width); ++ W2BYTE(REG_SCL_DMA0_33_L, stSCLDMACfg->u16Height); ++ u8420md = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422? BIT7 : 0; ++ W2BYTEMSK(REG_SCL_DMA0_36_L, u8420md, BIT7); ++ W2BYTEMSK(REG_SCL_DMA0_36_L, 0x06, 0x0F); //422to444_md[1:0], 420to422_md[2], 420to422_md_avg[3] ++ W2BYTEMSK(REG_SCL_DMA0_02_L, stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUV422 ? BIT14 : 0, BIT14); ++ u8DataMd = stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep420 ? BIT0 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YCSep422 ? BIT1 : ++ stSCLDMACfg->enColor == E_SCLDMA_COLOR_YUVSep422 ? BIT2 : ++ 0; ++ W2BYTEMSK(REG_SCL3_1E_L, u8DataMd, BIT0|BIT1|BIT2); // w_422_pack[14] ++ } ++ else ++ { ++ HAL_SCLDMA_ERR(printf("%s %d, wrong RWmode: %d\n", __FUNCTION__, __LINE__, stSCLDMACfg->enRWMode)); ++ } ++} ++ ++ ++//SCLDMA Trig ++void Hal_SCLDMA_SetVSyncRegenMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigMd) ++{ ++ MS_U16 u16val, u16Mask; ++ MS_U32 u32Reg; ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0001 : ++ 0x0002; ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_26_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0100 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0200 : ++ 0x0300; ++ ++ u16Mask = BIT9|BIT8; ++ u32Reg = REG_SCL0_26_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0001 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0002 : ++ 0x0003 ; ++ ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_20_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0001 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0002 : ++ 0x0003 ; ++ ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_22_L; ++ ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ u16val = enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_IN_VSYNC ? 0x0000 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_HW_DELAY ? 0x0001 : ++ enTrigMd == E_SCLDMA_VS_TRIG_MODE_SWTRIGGER ? 0x0002 : ++ 0x0003 ; ++ ++ u16Mask = BIT1|BIT0; ++ u32Reg = REG_SCL0_24_L; ++ } ++ else ++ { ++ return; ++ } ++ ++ ++ W2BYTEMSK(u32Reg, u16val, u16Mask); ++} ++ ++void Hal_SCLDMA_SetRegenVSyncVariableWidthEn(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL0_2D_L, bEn ? BIT7 : 0, BIT7); ++ ++} ++ ++void Hal_SCLDMA_SetRegenVSyncRefEdgeMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_REGEN_VS_REF_MODE_TYPE enRefMd) ++{ ++ MS_U8 u16val = enRefMd == E_SCLDMA_REF_VS_REF_MODE_RASING ? 1 : 0; ++ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val, BIT0); ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<1, BIT1); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<2, BIT2); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<3, BIT3); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTEMSK(REG_SCL0_2D_L, u16val<<4, BIT4); ++ } ++ else ++ { ++ } ++} ++ ++void Hal_SCLDAM_SetRegenVSyncWidth(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_Width) ++{ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ W2BYTE(REG_SCL0_28_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTE(REG_SCL0_29_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTE(REG_SCL0_2A_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTE(REG_SCL0_2B_L, u16Vs_Width); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTE(REG_SCL0_2C_L, u16Vs_Width); ++ } ++ else ++ { ++ } ++} ++ ++ ++void Hal_SCLDAM_SetRegenVSyncStartPoint(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_St) ++{ ++ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTE(REG_SCL0_27_L, u16Vs_St); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTE(REG_SCL0_21_L, u16Vs_St); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTE(REG_SCL0_23_L, u16Vs_St); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTE(REG_SCL0_25_L, u16Vs_St); ++ } ++ else ++ { ++ } ++} ++ ++void Hal_SCLDMA_TrigRegenVSync(EN_SCLDMA_VS_ID_TYPE enID, MS_BOOL bEn) ++{ ++ if(enID == E_SCLDMA_VS_ID_SC) ++ { ++ } ++ else if(enID == E_SCLDMA_VS_ID_AFF) ++ { ++ W2BYTEMSK(REG_SCL0_26_L, bEn ? BIT10: 0, BIT10); ++ } ++ else if(enID == E_SCLDMA_VS_ID_LDC) ++ { ++ W2BYTEMSK(REG_SCL0_20_L, bEn ? BIT2: 0, BIT2); ++ } ++ else if(enID == E_SCLDMA_VS_ID_SC3) ++ { ++ W2BYTEMSK(REG_SCL0_22_L, bEn ? BIT2: 0, BIT2); ++ } ++ else if(enID == E_SCLDMA_VS_ID_DISP) ++ { ++ W2BYTEMSK(REG_SCL0_24_L, bEn ? BIT2: 0, BIT2); ++ } ++ else ++ { ++ } ++} ++ ++void Hal_SCLDMA_SetDMAEnableDoubleBuffer(MS_BOOL bEn,EN_SCLDMA_ID_TYPE enSCLDMA_ID) ++{ ++ switch(enSCLDMA_ID) ++ { ++ case E_SCLDMA_ID_1_W: ++ case E_SCLDMA_ID_2_W: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT4 : 0, BIT4); ++ break; ++ ++ case E_SCLDMA_ID_3_W: ++ case E_SCLDMA_ID_3_R: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT5 : 0, BIT5); ++ break; ++ ++ case E_SCLDMA_ID_PNL_R: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT6 : 0, BIT6); ++ break; ++ ++ default: ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT7 : 0, BIT7); ++ break; ++ ++ } ++} ++void Hal_SCLDMA_SetHandshakeDoubleBuffer(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DMA2_50_L, bEn ? BIT0 : 0, BIT0); ++ ++} ++MS_U8 Hal_SCLDMA_GetISPFrameCountReg(void) ++{ ++ MS_U8 u8Value = (MS_U8)((R2BYTE(REG_ISP_7A_L)>>8)&0x7F); ++ //u8Value = (u8Value==0) ? 0x7F : (u8Value - 1); ++ return u8Value; ++} ++MS_U16 Hal_SCLDMA_GetDMAOutputCount(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16Idx; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_10_L); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_11_L); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_12_L); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_13_L); ++ break; ++ ++ case E_SCLDMA_2_FRM2_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_18_L); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_14_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16Idx = R2BYTE(REG_SCL_DMA2_16_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16Idx = R2BYTE(REG_SCL_DMA2_15_L); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16Idx = R2BYTE(REG_SCL_DMA2_17_L); ++ break; ++ default: ++ u16Idx = 0x0; ++ break; ++ } ++ return ((u16Idx)); ++ ++} ++MS_U16 Hal_SCLDMA_GetOutputHsize(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16def; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_1A_L); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA1_4A_L); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16def = R2BYTE(REG_SCL_DMA0_4A_L); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_62_L); ++ break; ++ ++ case E_SCLDMA_2_FRM2_W: ++ u16def = R2BYTE(REG_SCL_DMA1_62_L); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA0_7A_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA1_32_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA1_1A_L); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA0_32_L); ++ break; ++ default: ++ u16def = 0x0; ++ break; ++ } ++ return ((u16def)); ++ ++} ++MS_U16 Hal_SCLDMA_GetOutputVsize(EN_SCLDMA_CLIENT_TYPE enClientType) ++{ ++ MS_U16 u16def; ++ ++ switch(enClientType) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_1B_L); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA1_4B_L); ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16def = R2BYTE(REG_SCL_DMA0_4B_L); ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA0_63_L); ++ break; ++ ++ case E_SCLDMA_2_FRM2_W: ++ u16def = R2BYTE(REG_SCL_DMA1_63_L); ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16def = R2BYTE(REG_SCL_DMA0_7B_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA1_33_L); ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16def = R2BYTE(REG_SCL_DMA1_1B_L); ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16def = R2BYTE(REG_SCL_DMA0_33_L); ++ break; ++ default: ++ return 0; ++ } ++ return ((u16def)); ++ ++} ++MS_U16 Hal_SCLDMA_Get_RW_Idx(EN_SCLDMA_CLIENT_TYPE enClient) ++{ ++ MS_U16 u16Idx; ++ switch(enClient) ++ { ++ case E_SCLDMA_1_FRM_W: ++ u16Idx = R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT1|BIT0)); ++ break; ++ ++ case E_SCLDMA_1_IMI_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT3|BIT2)))>>2; ++ break; ++ ++ case E_SCLDMA_1_SNP_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT5|BIT4)))>>4; ++ break; ++ ++ case E_SCLDMA_2_FRM_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT7|BIT6)))>>6; ++ break; ++ ++ case E_SCLDMA_2_FRM2_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT15|BIT14)))>>14; ++ break; ++ ++ case E_SCLDMA_2_IMI_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT9|BIT8)))>>8; ++ break; ++ ++ case E_SCLDMA_3_FRM_R: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT11|BIT10)))>>10; ++ break; ++ ++ case E_SCLDMA_3_FRM_W: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT13|BIT12)))>>12; ++ break; ++ ++ case E_SCLDMA_4_FRM_R: ++ u16Idx = (R2BYTEMSK(REG_SCL_DMA2_03_L, (BIT15|BIT14)))>>14; ++ break; ++ default: ++ u16Idx = 0xFF; ++ break; ++ } ++ return u16Idx; ++} ++ ++#undef HAL_SCLDMA_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/include/halscldma.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/include/halscldma.h +new file mode 100644 +index 00000000..e0beedf6 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/include/halscldma.h +@@ -0,0 +1,154 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_SCLDMA_H ++#define _HAL_SCLDMA_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_SCLDMA_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_SCLDMA_HWInit(void); ++INTERFACE void Hal_SCLDMA_CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk); ++INTERFACE void Hal_SCLDMA_SC3CLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk); ++void Hal_SCLDMA_ODCLKInit(MS_BOOL bEn,ST_SCLDMA_CLK_CONFIG *stclk); ++INTERFACE void Hal_SCLDMA_SetSC2HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC1HandshakeForce(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC1ToSC2HandshakeForce(MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetCheckFrmEndSignal(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetMCMByDMAClient(EN_SCLDMA_CLIENT_TYPE enSCLDMA_ID, MS_U8 u8value); ++INTERFACE void Hal_SCLDMA_SetIMIClientReset(void); ++INTERFACE void Hal_SCLDMA_SetDMAOutputBufferAddr ++ (EN_SCLDMA_CLIENT_TYPE enClientType,unsigned long u32YBufferAddr,unsigned long u32CBufferAddr,unsigned long u32VBufferAddr); ++INTERFACE void Hal_SCLDMA_SetRiuBase(MS_U32 u32riubase); ++INTERFACE void Hal_SCLDMA_SetSC1DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC1DMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetSC2DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC2DMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetSC3DMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetSC3DMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetDisplayDMAEn(EN_SCLDMA_RW_MODE_TYPE enRWMode, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetDisplayDMAConfig(ST_SCLDMA_RW_CONFIG *stSCLDMACfg); ++INTERFACE void Hal_SCLDMA_SetVSyncRegenMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_VS_TRIG_MODE_TYPE enTrigMd); ++INTERFACE void Hal_SCLDMA_SetRegenVSyncRefEdgeMode(EN_SCLDMA_VS_ID_TYPE enID, EN_SCLDMA_REGEN_VS_REF_MODE_TYPE enRefMd); ++INTERFACE void Hal_SCLDAM_SetRegenVSyncWidth(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_Width); ++INTERFACE void Hal_SCLDAM_SetRegenVSyncStartPoint(EN_SCLDMA_VS_ID_TYPE enID, MS_U16 u16Vs_St); ++INTERFACE void Hal_SCLDMA_TrigRegenVSync(EN_SCLDMA_VS_ID_TYPE enID, MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetRegenVSyncVariableWidthEn(MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_SetDMAEnableDoubleBuffer(MS_BOOL bEn,EN_SCLDMA_ID_TYPE enSCLDMA_ID); ++INTERFACE MS_U16 Hal_SCLDMA_Get_RW_Idx(EN_SCLDMA_CLIENT_TYPE enClient); ++INTERFACE MS_U16 Hal_SCLDMA_GetDMAOutputCount(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE MS_U16 Hal_SCLDMA_GetOutputHsize(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE MS_U16 Hal_SCLDMA_GetOutputVsize(EN_SCLDMA_CLIENT_TYPE enClientType); ++INTERFACE void Hal_SCLDMA_SetHandshakeDoubleBuffer(MS_BOOL bEn); ++INTERFACE void Hal_SCLDMA_Set_SW_Reset(void); ++INTERFACE MS_U8 Hal_SCLDMA_GetISPFrameCountReg(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/include/halscldma_utility.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/include/halscldma_utility.h +new file mode 100644 +index 00000000..510c8966 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/scldma/include/halscldma_utility.h +@@ -0,0 +1,64 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCL_UTILITY_H_ ++#define _HALSCL_UTILITY_H_ ++ ++//!! Do not include this header in driver or api level ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 SCLDMA_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( SCLDMA_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( SCLDMA_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (SCLDMA_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( SCLDMA_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/halsclirq.c b/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/halsclirq.c +new file mode 100644 +index 00000000..a6eb975b +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/halsclirq.c +@@ -0,0 +1,295 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_SCLIRQ_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg.h" ++#include "halsclirq_utility.h" ++#include "drvsclirq_st.h" ++#include "halsclirq.h" ++#include "mdrv_scl_dbg.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Variable ++ ++MS_U32 SCLIRQ_RIU_BASE = 0; ++MS_BOOL gblockdnr = 0; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_SCLIRQ_Set_Riu_Base(MS_U32 u32Riubase) ++{ ++ SCLIRQ_RIU_BASE = u32Riubase; ++} ++ ++ ++MS_U64 Hal_SCLIRQ_Get_Flag(EN_SCLIRQ_SCTOP_TYPE enType, MS_U64 u64IRQ) ++{ ++ MS_U32 u32Mask; ++ MS_U16 u16Mask; ++ MS_U64 u64Flag = 0; ++ MS_U32 u32Bank; ++ switch(enType) ++ { ++ case EN_SCLIRQ_SCTOP_0: ++ u32Bank = REG_SCL0_13_L; ++ break; ++ ++ case EN_SCLIRQ_SCTOP_1: ++ u32Bank = REG_SCL0_51_L; ++ break; ++ ++ case EN_SCLIRQ_SCTOP_2: ++ u32Bank = REG_SCL0_5D_L; ++ break; ++ default: ++ u32Bank = REG_SCL0_13_L; ++ break; ++ } ++ if(u64IRQ & 0x00000000FFFFFFFF) ++ { ++ u32Mask = (MS_U32)(u64IRQ & 0xFFFFFFFF); ++ u64Flag |= (MS_U64)(R4BYTE(u32Bank) & u32Mask); ++ } ++ ++ if(u64IRQ & 0x0000FFFF00000000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0x0000FFFF00000000)>>32); ++ u64Flag |= (((MS_U64)(R2BYTE(u32Bank+4) & u16Mask))<<32); ++ ++ } ++ ++ return u64Flag; ++} ++MS_U16 Hal_SCLIRQ_CMDQ_get_clear_irq(void) ++{ ++ return R2BYTEMSK(REG_SCL0_1E_L, 0xFFFF); ++} ++ ++ ++void Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_TYPE enType, MS_U64 u64IRQ, MS_BOOL bEn) ++{ ++ MS_U16 u16Mask; ++ MS_U32 u32Bank; ++ switch(enType) ++ { ++ case EN_SCLIRQ_SCTOP_0: ++ u32Bank = REG_SCL0_10_L; ++ break; ++ ++ case EN_SCLIRQ_SCTOP_1: ++ u32Bank = REG_SCL0_4E_L; ++ break; ++ ++ case EN_SCLIRQ_SCTOP_2: ++ u32Bank = REG_SCL0_5A_L; ++ break; ++ default: ++ u32Bank = REG_SCL0_10_L; ++ break; ++ } ++ ++ if(u64IRQ & 0x0000FFFF) ++ { ++ u16Mask = (MS_U16)(u64IRQ & 0x0000FFFF); ++ W2BYTEMSK(u32Bank, bEn ? u16Mask : 0, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFFFF0000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFFFF0000)>>16); ++ W2BYTEMSK(u32Bank+2, bEn ? u16Mask : 0, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFFFF00000000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFFFF00000000)>>32); ++ W2BYTEMSK(u32Bank+4, bEn ? u16Mask : 0, u16Mask); ++ } ++} ++MS_U16 Hal_SCLIRQ_Get_RegVal(MS_U32 u32Reg) ++{ ++ return R2BYTE(u32Reg); ++} ++void Hal_SCLIRQ_Set_Reg(MS_U32 u32Reg,MS_U16 u16Val,MS_U16 u16Mask) ++{ ++ W2BYTEMSK(u32Reg,u16Val,u16Mask); ++} ++void Hal_SCLIRQ_SetDNRBypass(MS_BOOL bEn) ++{ ++ static MS_U16 u16open = 0; ++ if(bEn) ++ { ++ u16open = R2BYTE(REG_VIP_MCNR_01_L); ++ } ++ if(!gblockdnr) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVSCLIRQ()&EN_DBGMG_SCLIRQLEVEL_ELSE, "[SCLIRQ]DNR bypass:%hhd\n", bEn); ++ W2BYTEMSK(REG_VIP_MCNR_01_L, bEn ? 0 : u16open, BIT1|BIT2);//IOenable ++ } ++} ++void Hal_SCLIRQ_SetDNRLock(MS_BOOL bEn) ++{ ++ gblockdnr = bEn; ++} ++ ++void Hal_SCLIRQ_Set_Mask(EN_SCLIRQ_SCTOP_TYPE enType, MS_U64 u64IRQ, MS_BOOL bMask) ++{ ++ MS_U16 u16val; ++ MS_U16 u16Mask; ++ MS_U32 u32Bank; ++ switch(enType) ++ { ++ case EN_SCLIRQ_SCTOP_0: ++ u32Bank = REG_SCL0_08_L; ++ break; ++ ++ case EN_SCLIRQ_SCTOP_1: ++ u32Bank = REG_SCL0_48_L; ++ break; ++ ++ case EN_SCLIRQ_SCTOP_2: ++ u32Bank = REG_SCL0_54_L; ++ break; ++ default: ++ u32Bank = REG_SCL0_08_L; ++ break; ++ } ++ if(u64IRQ & 0x0000FFFF) ++ { ++ u16Mask = (MS_U16)(u64IRQ & 0x0000FFFF); ++ u16val = bMask ? u16Mask : 0; ++ W2BYTEMSK(u32Bank, u16val, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFFFF0000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFFFF0000)>>16); ++ u16val = bMask ? u16Mask : 0; ++ W2BYTEMSK(u32Bank+2, u16val, u16Mask); ++ } ++ ++ if(u64IRQ & 0xFFFF00000000) ++ { ++ u16Mask = (MS_U16)((u64IRQ & 0xFFFF00000000)>>32); ++ u16val = bMask ? u16Mask : 0; ++ W2BYTEMSK(u32Bank+4, u16val, u16Mask); ++ } ++} ++ ++#undef HAL_SCLIRQ_C +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/include/halsclirq.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/include/halsclirq.h +new file mode 100644 +index 00000000..d43d246d +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/include/halsclirq.h +@@ -0,0 +1,128 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_SCLIRQ_H ++#define _HAL_SCLIRQ_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_SCLIRQ_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++ ++INTERFACE void Hal_SCLIRQ_Set_Riu_Base(MS_U32 u32Riubase); ++INTERFACE void Hal_SCLIRQ_Set_Mask(EN_SCLIRQ_SCTOP_TYPE enType, MS_U64 u64IRQ, MS_BOOL bMask); ++INTERFACE MS_U16 Hal_SCLIRQ_Get_RegVal(MS_U32 u32Reg); ++INTERFACE void Hal_SCLIRQ_Set_Reg(MS_U32 u32Reg,MS_U16 u16Val,MS_U16 u16Mask); ++INTERFACE void Hal_SCLIRQ_SetDNRBypass(MS_BOOL bEn); ++INTERFACE void Hal_SCLIRQ_SetDNRLock(MS_BOOL bEn); ++INTERFACE void Hal_SCLIRQ_Set_Clear(EN_SCLIRQ_SCTOP_TYPE enType, MS_U64 u64IRQ, MS_BOOL bEn); ++INTERFACE MS_U64 Hal_SCLIRQ_Get_Flag(EN_SCLIRQ_SCTOP_TYPE enType, MS_U64 u64IRQ); ++INTERFACE MS_U16 Hal_SCLIRQ_CMDQ_get_clear_irq(void); ++ ++#undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/include/halsclirq_utility.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/include/halsclirq_utility.h +new file mode 100644 +index 00000000..3cb8af12 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/sclirq/include/halsclirq_utility.h +@@ -0,0 +1,53 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCLIRQ_UTILITY_H_ ++#define _HALSCLIRQ_UTILITY_H_ ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 SCLIRQ_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( SCLIRQ_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( SCLIRQ_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (SCLIRQ_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( SCLIRQ_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/halvip.c b/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/halvip.c +new file mode 100644 +index 00000000..d2c5dfec +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/halvip.c +@@ -0,0 +1,1998 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define HAL_VIP_C ++ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++//#include ++//#include ++//#include ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg.h" ++#include "drvvip.h" ++#include "halvip_utility.h" ++#include "halvip.h" ++#include "drvCMDQ.h" ++#include "drvsclirq_st.h" ++#include "drvsclirq.h" ++#include "drvPQ_Define.h" ++#include "mdrv_scl_dbg.h" ++#include "Infinity3e_Main.h" // table config parameter ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & Macro ++//------------------------------------------------------------------------------------------------- ++#define HAL_VIP_DBG(x) ++#define HAL_VIP_MUTEX_LOCK() MsOS_ObtainMutex(_HalVIP_Mutex,MSOS_WAIT_FOREVER) ++#define HAL_VIP_MUTEX_UNLOCK() MsOS_ReleaseMutex(_HalVIP_Mutex) ++#define WDR_SRAM_NUM 8 ++#define WDR_SRAM_BYTENUM (PQ_IP_WDR_Loc_TBL_0_SRAM_SIZE_Main/2) ++#define WDR_SRAM_USERBYTENUM (81) ++#define GAMMAY_SRAM_BYTENUM (PQ_IP_YUV_Gamma_tblY_SRAM_SIZE_Main/4) ++#define GAMMAU_SRAM_BYTENUM (PQ_IP_YUV_Gamma_tblU_SRAM_SIZE_Main/4) ++#define GAMMAV_SRAM_BYTENUM (PQ_IP_YUV_Gamma_tblV_SRAM_SIZE_Main/4) ++#define GAMMA10to12R_SRAM_BYTENUM (PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_SIZE_Main/4) ++#define GAMMA10to12G_SRAM_BYTENUM (PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_SIZE_Main/4) ++#define GAMMA10to12B_SRAM_BYTENUM (PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_SIZE_Main/4) ++#define GAMMA12to10R_SRAM_BYTENUM (PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_SIZE_Main/4) ++#define GAMMA12to10G_SRAM_BYTENUM (PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_SIZE_Main/4) ++#define GAMMA12to10B_SRAM_BYTENUM (PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_SIZE_Main/4) ++//------------------------------------------------------------------------------------------------- ++// Variable ++//------------------------------------------------------------------------------------------------- ++MS_U32 VIP_RIU_BASE = 0; ++MS_BOOL gbCMDQ = 0; ++MS_S32 _HalVIP_Mutex = -1; ++ ++//------------------------------------------------------------------------------------------------- ++// Functions ++//------------------------------------------------------------------------------------------------- ++void Hal_VIP_Exit(void) ++{ ++ if(_HalVIP_Mutex != -1) ++ { ++ MsOS_DeleteMutex(_HalVIP_Mutex); ++ _HalVIP_Mutex = -1; ++ } ++} ++void Hal_VIP_Set_Riu_Base(MS_U32 u32riubase) ++{ ++ char word[] = {"_HalVIP_Mutex"}; ++ VIP_RIU_BASE = u32riubase; ++ _HalVIP_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, word, MSOS_PROCESS_SHARED); ++ ++ if (_HalVIP_Mutex == -1) ++ { ++ SCL_ERR("[DRVHVSP]%s(%d): create mutex fail\n", __FUNCTION__, __LINE__); ++ } ++} ++void Hal_VIP_SeMCNRIPMRead(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT0 : 0, BIT0);//IOenable ++} ++void Hal_VIP_SetIPMConpress(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DNR1_30_L, bEn ? BIT0 : 0, BIT0);//conpress ++ W2BYTEMSK(REG_SCL_DNR1_30_L, bEn ? BIT1 : 0, BIT1);//decon ++} ++void Hal_VIP_SeCIIRRead(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT2 : 0, BIT2);//IOenable ++} ++void Hal_VIP_SeCIIRWrite(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_DNR1_01_L, bEn ? BIT3 : 0, BIT3);//IOenable ++} ++void Hal_VIP_SRAMDumpIHCICC(EN_VIP_SRAM_DUMP_TYPE endump,MS_U32 u32reg) ++{ ++ MS_U8 u8sec = 0; ++ EN_VIP_SRAM_SEC_NUM enSecNum; ++ MS_U16 u16addr = 0,u16tvalue = 0,u16tcount = 0,u16readdata; ++ W2BYTEMSK(u32reg, BIT0, BIT0);//IOenable ++ for(u8sec=0;u8sec<4;u8sec++) ++ { ++ switch(u8sec) ++ { ++ case 0: ++ enSecNum = EN_VIP_SRAM_SEC_0; ++ break; ++ case 1: ++ enSecNum = EN_VIP_SRAM_SEC_1; ++ break; ++ case 2: ++ enSecNum = EN_VIP_SRAM_SEC_2; ++ break; ++ case 3: ++ enSecNum = EN_VIP_SRAM_SEC_3; ++ break; ++ } ++ W2BYTEMSK(u32reg, u8sec<<1, BIT1|BIT2);//sec ++ for(u16addr=0;u16addr>4)][u16tcount] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]VYtval12:%hx\n", u16tvalue); ++ W2BYTE(u32reg+4, u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ W2BYTE(u32reg+6, u16tvalue); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]VYtval34:%hx\n", u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vtval5:%hx\n", u16tvalue); ++ W2BYTEMSK(u32reg+8, u16tvalue, 0xFF); ++ W2BYTEMSK(u32reg, BIT8, BIT8);//W pulse ++ //if(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG) ++ { ++ W2BYTEMSK(u32reg, BIT9, BIT9);//R pulse ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vread Yval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vread Yval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vread Yval 5:%hx\n", u16readdata); ++ } ++ W2BYTEMSK(u32reg, 0, BIT0);//Yenable ++ ++ W2BYTEMSK(u32reg, BIT1, BIT1);//Cenable ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount] | (MST_C_SRAM1_Main[0][u16tcount+1]<<8); ++ W2BYTE(u32reg+4, u16tvalue); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+2] | (MST_C_SRAM1_Main[0][u16tcount+3]<<8); ++ W2BYTE(u32reg+6, u16tvalue); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+4]; ++ W2BYTEMSK(u32reg+8, u16tvalue, 0xFF); ++ W2BYTEMSK(u32reg, BIT8, BIT8);//W pulse ++ //if(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG) ++ { ++ W2BYTEMSK(u32reg, BIT9, BIT9);//R pulse ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vread Cval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vread Cval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Vread Cval 5:%hx\n", u16readdata); ++ } ++ W2BYTEMSK(u32reg, 0, BIT1);//Cenable ++ u16tcount += 5; ++ } ++ //SRAM 1 //128~256 entry link to 0~127 , so do not use ++} ++void Hal_VIP_SRAMDumpVSP(MS_U32 u32Sram,MS_U32 u32reg) ++{ ++ MS_U16 u16addr = 0,u16tvalue = 0,u16tcount = 0,u16readdata; ++ //clear ++ for(u16addr = 0;u16addr<64;u16addr++) ++ { ++ W2BYTEMSK(u32reg, BIT0, BIT0);//Yenable ++ W2BYTEMSK(u32reg+2, u16addr, 0xFF); ++ W2BYTE(u32reg+4, 0); ++ W2BYTE(u32reg+6, 0); ++ W2BYTEMSK(u32reg+8, 0, 0xFF); ++ W2BYTEMSK(u32reg, BIT8, BIT8);//W pulse ++ W2BYTEMSK(u32reg, 0, BIT0);//Yenable ++ ++ W2BYTEMSK(u32reg, BIT1, BIT1);//Cenable ++ W2BYTE(u32reg+4, 0); ++ W2BYTE(u32reg+6, 0); ++ W2BYTEMSK(u32reg+8, 0, 0xFF); ++ W2BYTEMSK(u32reg, BIT8, BIT8);//W pulse ++ W2BYTEMSK(u32reg, 0, BIT1);//Cenable ++ } ++ //SRAM 0 ///0~64 entry is V 65~127 is H ++ ++ for(u16addr=0;u16addr<(PQ_IP_SRAM1_SIZE_Main/5);u16addr++) ++ { ++ W2BYTEMSK(u32reg, BIT0, BIT0);//Yenable ++ W2BYTEMSK(u32reg+2, u16addr, 0xFF); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+1]<<8); ++ } ++ W2BYTE(u32reg+4, u16tvalue); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Ytval12:%hx\n", u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+2] | ++ (MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+3]<<8); ++ } ++ W2BYTE(u32reg+6, u16tvalue); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Ytval34:%hx\n", u16tvalue); ++ if(u32Sram&0x1) ++ { ++ u16tvalue = MST_SRAM1_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ else ++ { ++ u16tvalue = MST_SRAM2_Main[((u32Sram&0xF0)>>4)][u16tcount+4]; ++ } ++ W2BYTEMSK(u32reg+8, u16tvalue, 0xFF); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Ytval5:%hx\n", u16tvalue); ++ W2BYTEMSK(u32reg, BIT8, BIT8);//W pulse ++ //if(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG) ++ { ++ W2BYTEMSK(u32reg, BIT9, BIT9);//R pulse ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]read Yval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]read Yval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]read Yval 5:%hx\n", u16readdata); ++ } ++ W2BYTEMSK(u32reg, 0, BIT0);//Yenable ++ ++ W2BYTEMSK(u32reg, BIT1, BIT1);//Cenable ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount] | (MST_C_SRAM1_Main[0][u16tcount+1]<<8); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Ctval12:%hx\n", u16tvalue); ++ W2BYTE(u32reg+4, u16tvalue); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+2] | (MST_C_SRAM1_Main[0][u16tcount+3]<<8); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Ctval34:%hx\n", u16tvalue); ++ W2BYTE(u32reg+6, u16tvalue); ++ u16tvalue = MST_C_SRAM1_Main[0][u16tcount+4]; ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]Ctval5:%hx\n", u16tvalue); ++ W2BYTEMSK(u32reg+8, u16tvalue, 0xFF); ++ W2BYTEMSK(u32reg, BIT8, BIT8);//W pulse ++ ++ //if(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG) ++ { ++ W2BYTEMSK(u32reg, BIT9, BIT9);//R pulse ++ u16readdata = R2BYTE(u32reg+10); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]read Cval 12:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+12); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]read Cval 34:%hx\n", u16readdata); ++ u16readdata = R2BYTE(u32reg+14); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[HVSP]read Cval 5:%hx\n", u16readdata); ++ } ++ W2BYTEMSK(u32reg, 0, BIT1);//Cenable ++ u16tcount += 5; ++ } ++ //SRAM 1 //128~256 entry link to 0~127 , so do not use ++} ++MS_U16 Hal_VIP_GetWDRTvalue(MS_U8 u8sec, MS_U16 u16tcount, void* u32Sram) ++{ ++ MS_U16 u16tvalue; ++ MS_U8 *p8buffer; ++ MS_U32 u32Val = 0; ++ if(u32Sram) ++ { ++ p8buffer= (MS_U8 *)u32Sram; ++ u32Val = WDR_SRAM_USERBYTENUM*2 *u8sec ; ++ u16tvalue = (MS_U16)(*(p8buffer+u32Val+u16tcount) | (*(p8buffer+u32Val+u16tcount+1)<<8)); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[WDRTvalue]val:%ld\n",u32Val+u16tcount); ++ } ++ else ++ { ++ switch(u8sec) ++ { ++ case 0: ++ u16tvalue = MST_WDR_Loc_TBL_0_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_0_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 1: ++ u16tvalue = MST_WDR_Loc_TBL_1_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_1_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 2: ++ u16tvalue = MST_WDR_Loc_TBL_2_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_2_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 3: ++ u16tvalue = MST_WDR_Loc_TBL_3_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_3_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 4: ++ u16tvalue = MST_WDR_Loc_TBL_4_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_4_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 5: ++ u16tvalue = MST_WDR_Loc_TBL_5_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_5_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 6: ++ u16tvalue = MST_WDR_Loc_TBL_6_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_6_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ case 7: ++ u16tvalue = MST_WDR_Loc_TBL_7_SRAM_Main[0][u16tcount] | (MST_WDR_Loc_TBL_7_SRAM_Main[0][u16tcount+1]<<8); ++ break; ++ default: ++ u16tvalue = 0; ++ break; ++ } ++ } ++ return u16tvalue; ++} ++void Hal_VIP_SetWriteRegType(MS_BOOL bEn) ++{ ++ if(bEn && (VIPSETRULE()==E_VIPSetRule_CMDQAll || VIPSETRULE()==E_VIPSetRule_CMDQAllCheck ++ ||(VIPSETRULE() == E_VIPSetRule_CMDQAllONLYSRAMCheck))) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ Drv_CMDQ_SetForceSkip(1); ++ if(Drv_VIP_GetEachDMAEn()) ++ { ++ gbCMDQ = 1; ++ } ++ else ++ { ++ gbCMDQ = 0; ++ } ++ } ++ else if(bEn && VIPSETRULE()) ++ { ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,1); ++ Drv_CMDQ_SetForceSkip(1); ++ if(Drv_VIP_GetEachDMAEn()&& !Drv_VIP_GetIsBlankingRegion()) ++ { ++ gbCMDQ = 1; ++ } ++ else ++ { ++ gbCMDQ = 0; ++ } ++ } ++ else ++ { ++ gbCMDQ = 0; ++ Drv_CMDQ_SetForceSkip(0); ++ Drv_CMDQ_GetModuleMutex(EN_CMDQ_TYPE_IP0,0); ++ } ++} ++void Hal_VIP_WriteReg(MS_U32 u32Reg,MS_U16 u16Val,MS_U16 u16Mask) ++{ ++ MS_CMDQ_CMDReg stCfg; ++ if(gbCMDQ) ++ { ++ Drv_CMDQ_FillCmd(&stCfg, u32Reg, u16Val, u16Mask); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0, &stCfg, 1); ++ } ++ else ++ { ++ W2BYTEMSK(u32Reg, u16Val, u16Mask);//sec ++ } ++} ++MS_BOOL _Hal_VIP_CheckMonotonicallyIncreasing ++ (MS_U16 u16tvalueeven,MS_U16 u16tvalueodd,MS_U16 u16chkodd) ++{ ++ if((u16tvalueodd < u16tvalueeven)||(u16tvalueeven < u16chkodd)) ++ { ++ return 0; ++ } ++ else ++ { ++ return 1; ++ } ++} ++void Hal_VIP_SRAMDumpWDR(MS_U32 u32reg, void* u32Sram) ++{ ++ MS_U8 u8sec = 0; ++ MS_U16 u16addr = 0,u16tvalue = 0,u16tcount = 0; ++ MS_U16 u16addrmax; ++ MS_U32 u32Events; ++ MS_U8 u8Cnt = 0; ++ MS_U16 u16tvalueOri; ++ void* u32SramOri; ++ u32SramOri = Drv_VIP_GeSRAMGlobal(EN_VIP_DRV_AIP_SRAM_WDR); ++ if(u32Sram==NULL) ++ { ++ u16addrmax = WDR_SRAM_BYTENUM; ++ } ++ else ++ { ++ u16addrmax = WDR_SRAM_USERBYTENUM; ++ } ++ HAL_VIP_MUTEX_LOCK(); ++ if(WDR_USE_CMDQ()) ++ { ++ Hal_VIP_SetWriteRegType(1); ++ } ++ for(u8sec=0;u8sec= 2) ++ { ++ u16chkodd = Hal_VIP_GetGammaRGBTvalue(u16sec, u16tcount-2,(MS_U8 *)u32Sram,u8type); ++ } ++ else ++ { ++ u16chkodd = Hal_VIP_GetGammaRGBTvalue(u16sec, u16tcount,(MS_U8 *)u32Sram,u8type); ++ } ++ bRet = _Hal_VIP_CheckMonotonicallyIncreasing(u16readdata,u16tvalueodd,u16chkodd); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_DBG, ++ "[ISRCheck]RGBGamma:%hhx read val:%hx odd val:%hx ckodd val:%hx addr:%hd\n" ++ ,u16sec+u8type,u16readdata,u16tvalueodd,u16chkodd,u16addr); ++ if(!bRet) ++ { ++ Hal_VIP_SetWriteRegType(1); ++ flag = gbCMDQ; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISRCheck, "[ISRCheck]RGBGamma:%hhx ",u16sec+u8type); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISRCheck, "addr:%hx ,even val:%hx ",u16addr,u16tvalueeven); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISRCheck, "read val:%hx\n",u16readdata); ++ Hal_VIP_WriteReg(u32reg+2, (MS_U16)u16tvalueeven, 0xFFF);//data ++ Hal_VIP_WriteReg(u32reg, ((u16addr)|((MS_U16)u16sec<<8)|BIT11), 0xFFFF);//wen ++ Hal_VIP_WriteReg(u32reg, ((u16addr)|((MS_U16)u16sec<<8)|BIT12), 0xFFFF);//ren ++ Hal_VIP_SetWriteRegType(0); ++ } ++ } ++ Hal_VIP_WriteReg(u32reg, u16addr, 0x007F);//addr ++ Hal_VIP_WriteReg(u32reg, (u16sec+1)<<8, BIT8|BIT9|BIT10);//sec ++ Hal_VIP_WriteReg(u32reg, BIT12, BIT12);//ren ++ u16readdata=R2BYTE(u32reg+4); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_SRAMCheck, "RGBGamma:%hhx ",u16sec+u8type); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_SRAMCheck, "addr:%hx ,odd val:%hx ",u16addr,u16tvalueodd); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_SRAMCheck, "read val:%hx\n",u16readdata); ++ if(u16readdata != u16tvalueodd) ++ { ++ if(u16tcount< 4*(u16size-1)) ++ { ++ u16chkodd = Hal_VIP_GetGammaRGBTvalue(u16sec, u16tcount+4,(MS_U8 *)u32Sram,u8type); ++ } ++ else ++ { ++ u16chkodd = Hal_VIP_GetGammaRGBTvalue(u16sec, u16tcount+2,(MS_U8 *)u32Sram,u8type); ++ } ++ bRet = _Hal_VIP_CheckMonotonicallyIncreasing(u16readdata,u16chkodd,u16tvalueeven); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_DBG, ++ "[ISRCheck]RGBGamma:%hhx read val:%hx odd val:%hx ckeven val:%hx addr:%hd\n" ++ ,u16sec+u8type,u16readdata,u16chkodd,u16tvalueeven,u16addr); ++ if(!bRet) ++ { ++ Hal_VIP_SetWriteRegType(1); ++ flag = gbCMDQ; ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISRCheck, "[ISRCheck]RGBGamma:%hhx ",u16sec+u8type); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISRCheck, "addr:%hx ,odd val:%hx ",u16addr,u16tvalueodd); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISRCheck, "read val:%hx\n",u16readdata); ++ Hal_VIP_WriteReg(u32reg+2, (MS_U16)u16tvalueodd, 0xFFF);//data ++ Hal_VIP_WriteReg(u32reg, ((u16addr)|(((MS_U16)u16sec+1)<<8)|BIT11), 0xFFFF);//wen ++ Hal_VIP_WriteReg(u32reg, ((u16addr)|(((MS_U16)u16sec+1)<<8)|BIT12), 0xFFFF);//ren ++ Hal_VIP_SetWriteRegType(0); ++ } ++ } ++ u16tcount+=4; ++ } ++ u16chkNum[u16sec+u8type] = 0; ++ if(flag) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_DBG,"[ISRCheck]Fire\n"); ++ Hal_VIP_SetWriteRegType(1); ++ Hal_VIP_WriteReg(u32reg+2, 0, 0xFFF);//data ++ if(gbCMDQ) ++ { ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,1); ++ } ++ Hal_VIP_SetWriteRegType(0); ++ } ++ HAL_VIP_MUTEX_UNLOCK(); ++ return 1; ++} ++MS_BOOL Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_TYPE endump,void *u32Sram,MS_U32 u32reg) ++{ ++ MS_U16 u16sec = 0; ++ MS_U8 u8type = 0; ++ u8 flag = 0; ++ MS_U16 u16addr = 0,u16tvalueodd = 0,u16tvalueeven = 0,u16tcount = 0,u16readdata,u16size; ++ switch(endump) ++ { ++ case EN_VIP_SRAM_DUMP_GM10to12_R: ++ u16size = GAMMA10to12R_SRAM_BYTENUM; ++ u16sec = 0; ++ u8type = 0; ++ break; ++ case EN_VIP_SRAM_DUMP_GM10to12_G: ++ u16size = GAMMA10to12G_SRAM_BYTENUM; ++ u16sec = 2; ++ u8type = 0; ++ break; ++ case EN_VIP_SRAM_DUMP_GM10to12_B: ++ u16size = GAMMA10to12B_SRAM_BYTENUM; ++ u16sec = 4; ++ u8type = 0; ++ break; ++ case EN_VIP_SRAM_DUMP_GM12to10_R: ++ u16size = GAMMA12to10R_SRAM_BYTENUM; ++ u16sec = 0; ++ u8type = 1; ++ break; ++ case EN_VIP_SRAM_DUMP_GM12to10_G: ++ u16size = GAMMA12to10G_SRAM_BYTENUM; ++ u16sec = 2; ++ u8type = 1; ++ break; ++ case EN_VIP_SRAM_DUMP_GM12to10_B: ++ u16size = GAMMA12to10B_SRAM_BYTENUM; ++ u16sec = 4; ++ u8type = 1; ++ break; ++ default: ++ u16size = 0; ++ u16sec = 0; ++ u8type = 0; ++ break; ++ } ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_ISR, "RGBGamma:%hhx\n",u16sec+u8type); ++ HAL_VIP_MUTEX_LOCK(); ++ for(u16addr=0;u16addr>4); ++ W4BYTE(REG_VIP_MWE_1A_L,u32addr2>>4); ++} ++void Hal_VIP_SetDLCshift(MS_U8 u8value) ++{ ++ W2BYTEMSK(REG_VIP_DLC_03_L,u8value,0x0007); ++} ++void HAl_VIP_SetDLCmode(MS_U8 u8value) ++{ ++ W2BYTEMSK(REG_VIP_MWE_1C_L,u8value<<2,0x0004); ++} ++void Hal_VIP_SetDLCActWin(MS_BOOL bEn,MS_U16 u16Vst,MS_U16 u16Hst,MS_U16 u16Vnd,MS_U16 u16Hnd) ++{ ++ W2BYTEMSK(REG_VIP_DLC_08_L,bEn<<7,0x0080); ++ W2BYTEMSK(REG_VIP_MWE_01_L,u16Vst,0x03FF); ++ W2BYTEMSK(REG_VIP_MWE_02_L,u16Vnd,0x03FF); ++ W2BYTEMSK(REG_VIP_MWE_03_L,u16Hst,0x01FF); ++ W2BYTEMSK(REG_VIP_MWE_04_L,u16Hnd,0x01FF); ++} ++void Hal_VIP_DLCHistSetRange(MS_U8 u8value,MS_U8 u8range) ++{ ++ MS_U16 u16tvalue; ++ MS_U16 u16Mask; ++ MS_U32 u32Reg; ++ u8range = u8range-1; ++ u32Reg = REG_VIP_DLC_0C_L+(((u8range)/2)*2); ++ if((u8range%2) == 0) ++ { ++ u16Mask = 0x00FF; ++ u16tvalue = ((MS_U16)u8value); ++ ++ } ++ else ++ { ++ u16Mask = 0xFF00; ++ u16tvalue = ((MS_U16)u8value)<<8; ++ } ++ ++ W2BYTEMSK(u32Reg,(u16tvalue),u16Mask); ++ ++} ++MS_U32 Hal_VIP_DLC_Hist_GetRange(MS_U8 u8range) ++{ ++ MS_U32 u32tvalue; ++ MS_U32 u32Reg; ++ u32Reg = REG_VIP_MWE_20_L+(((u8range)*2)*2); ++ u32tvalue = R4BYTE(u32Reg); ++ return u32tvalue; ++ ++} ++ ++MS_U8 Hal_VIP_DLCGetBaseidx(void) ++{ ++ MS_U8 u8tvalue; ++ u8tvalue = R2BYTE(REG_VIP_MWE_15_L); ++ u8tvalue = (MS_U8)(u8tvalue&0x80)>>7; ++ return u8tvalue; ++} ++ ++MS_U32 Hal_VIP_DLCGetPC(void) ++{ ++ MS_U32 u32tvalue; ++ u32tvalue = R4BYTE(REG_VIP_MWE_08_L); ++ return u32tvalue; ++} ++ ++MS_U32 Hal_VIP_DLCGetPW(void) ++{ ++ MS_U32 u32tvalue; ++ u32tvalue = R4BYTE(REG_VIP_MWE_0A_L); ++ return u32tvalue; ++} ++ ++MS_U8 Hal_VIP_DLCGetMinP(void) ++{ ++ MS_U16 u16tvalue; ++ u16tvalue = R2BYTE(REG_VIP_DLC_62_L); ++ u16tvalue = (u16tvalue>>8); ++ return (MS_U8)u16tvalue; ++} ++ ++MS_U8 Hal_VIP_DLCGetMaxP(void) ++{ ++ MS_U16 u16tvalue; ++ u16tvalue = R2BYTE(REG_VIP_DLC_62_L); ++ return (MS_U8)u16tvalue; ++} ++// LDC frame control ++void Hal_VIP_SetLDCBypass(MS_BOOL bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0F_L, bEn ? BIT0 : 0, BIT0); ++} ++ ++ ++void Hal_VIP_SetLDCHWrwDiff(MS_U16 u8Val) ++{ ++ W2BYTEMSK(REG_SCL_LDC_11_L, ((MS_U16)u8Val), BIT1|BIT0); ++} ++void Hal_VIP_SetLDCSW_Idx(MS_U8 idx) ++{ ++ W2BYTEMSK(REG_SCL_LDC_10_L, ((MS_U16)idx), BIT1|BIT0); ++} ++void Hal_VIP_SetLDCSW_Mode(MS_U8 bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_12_L, ((MS_U16)bEn)? BIT0 :0, BIT0); ++} ++void Hal_VIP_SetLDCBank_Mode(EN_DRV_VIP_LDCLCBANKMODE_TYPE enType) ++{ ++ W2BYTEMSK(REG_SCL_LDC_09_L, ((MS_U16)enType == EN_DRV_VIP_LDCLCBANKMODE_64)? BIT0 :0, BIT0); ++} ++ ++void Hal_VIP_SetLDCDmapBase(MS_U32 u32Base) ++{ ++ W4BYTE(REG_SCL_LDC_0A_L, u32Base); ++} ++ ++void Hal_VIP_SetLDCDmapPitch(MS_U32 u32Pitch) ++{ ++ W4BYTE(REG_SCL_LDC_0C_L, u32Pitch); ++} ++void Hal_VIP_MCNRInit(void) ++{ ++ W2BYTEMSK(REG_SCL_DNR1_7F_L, 0x0007, BIT2|BIT1|BIT0); //for I3e ECO ++} ++void Hal_VIP_LDCECO(void) ++{ ++ W2BYTEMSK(REG_SCL_LDC_31_L, BIT0, BIT0); //for I3e ECO ++} ++void Hal_VIP_AIPDB(MS_U8 u8En) ++{ ++ W2BYTEMSK(REG_VIP_SCNR_7F_L, u8En ? 0 : BIT0, BIT0); ++} ++void Hal_VIP_SetLDC422_444_Md(MS_U8 u8md) ++{ ++ W2BYTEMSK(REG_SCL_LDC_1D_L, (MS_U16)u8md, BIT1|BIT0); ++} ++void Hal_VIP_SetLDC444_422_Md(MS_U8 u8md) ++{ ++ W2BYTEMSK(REG_SCL_LDC_1F_L, (MS_U16)u8md, BIT1|BIT0); ++} ++ ++void Hal_VIP_SetLDCDmapOffset(MS_U8 u8offset) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0E_L, (u8offset), 0x003F); ++} ++ ++void Hal_VIP_SetLDCDmapPS(MS_U8 bEn) ++{ ++ W2BYTEMSK(REG_SCL_LDC_0E_L, (bEn<<6), BIT6); ++} ++void Hal_VIP_SetLDCSramAmount(MS_U16 u16hor,MS_U16 u16ver) ++{ ++ W2BYTE(REG_SCL_LDC_22_L, ((MS_U16)u16hor)); ++ W2BYTE(REG_SCL_LDC_2A_L, ((MS_U16)u16ver)); ++} ++void Hal_VIP_SetLDCSramBase(MS_U32 u32hor,MS_U32 u32ver) ++{ ++ W4BYTE(REG_SCL_LDC_24_L, (u32hor>>4)); ++ W4BYTE(REG_SCL_LDC_2C_L, (u32ver>>4)); ++} ++void Hal_VIP_SetLDCSramStr(MS_U16 u16hor,MS_U16 u16ver) ++{ ++ ++ W2BYTE(REG_SCL_LDC_23_L, ((MS_U16)u16hor)); ++ W2BYTE(REG_SCL_LDC_2B_L, ((MS_U16)u16ver)); ++} ++ ++void Hal_VIP_SetAutodownloadAddr(MS_U32 u32baseadr,MS_U16 u16iniaddr,MS_U8 u8cli) ++{ ++ switch(u8cli) ++ { ++ case 9: ++ W2BYTE(REG_SCL1_73_L, (MS_U16)(u32baseadr>>4)); ++ W2BYTEMSK(REG_SCL1_74_L, (MS_U16)(u32baseadr>>20), 0x01FF); ++ W2BYTE(REG_SCL1_77_L, ((MS_U16)u16iniaddr)); ++ break; ++ default: ++ SCL_ERR("[HALVIP]default\n"); ++ return; ++ } ++} ++ ++void Hal_VIP_SetAutodownloadReq(MS_U16 u16depth,MS_U16 u16reqlen,MS_U8 u8cli) ++{ ++ switch(u8cli) ++ { ++ case 9: ++ W2BYTE(REG_SCL1_76_L, ((MS_U16)u16reqlen)); ++ W2BYTE(REG_SCL1_75_L, ((MS_U16)u16depth)); ++ break; ++ default: ++ SCL_ERR("[HALVIP]default\n"); ++ return; ++ } ++} ++ ++void Hal_VIP_SetAutodownload(MS_U8 bCLientEn,MS_U8 btrigContinue,MS_U8 u8cli) ++{ ++ switch(u8cli) ++ { ++ case 9: ++ W2BYTEMSK(REG_SCL1_72_L, bCLientEn|(btrigContinue<<1), 0x0003); ++ break; ++ default: ++ SCL_ERR("[HALVIP]default\n"); ++ return; ++ } ++} ++ ++void Hal_VIP_SetAutodownloadTimer(MS_U8 bCLientEn) ++{ ++ W2BYTEMSK(REG_SCL1_78_L, bCLientEn<<15, 0x8000); ++} ++void Hal_VIP_GetNLMSRAM(MS_U16 u16entry) ++{ ++ MS_U32 u32tvalue1,u32tvalue2; ++ W2BYTEMSK(REG_SCL_NLM0_62_L, u16entry, 0x07FF); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x8000, 0x8000); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x2000, 0x2000); ++ u32tvalue1 = R2BYTE(REG_SCL_NLM0_64_L); ++ u32tvalue2 = R2BYTE(REG_SCL_NLM0_65_L); ++ u32tvalue1 |= ((u32tvalue2&0x00F0)<<12); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x0000, 0x8000); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[Get_SRAM]entry%hx :%lx\n",u16entry,u32tvalue1); ++} ++ ++void Hal_VIP_SetNLMSRAMbyCPU(MS_U16 u16entry,MS_U32 u32tvalue) ++{ ++ W2BYTEMSK(REG_SCL_NLM0_62_L, u16entry, 0x07FF); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x8000, 0x8000); ++ W2BYTE(REG_SCL_NLM0_63_L, (MS_U16)u32tvalue); ++ W2BYTEMSK(REG_SCL_NLM0_65_L, (MS_U16)(u32tvalue>>16), 0x000F); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x4000, 0x4000); ++ W2BYTEMSK(REG_SCL_NLM0_62_L, 0x0000, 0x8000); ++ SCL_DBG(SCL_DBG_LV_DRVVIP()&EN_DBGMG_VIPLEVEL_VIPLOG, "[Set_SRAM]entry%hx :%lx\n",u16entry,u32tvalue); ++} ++ ++#define VTRACK_KEY_SETTING_LENGTH 8 ++ ++static MS_U8 u8VtrackKey[VTRACK_KEY_SETTING_LENGTH]= ++{ ++ 0xaa,0x13,0x46,0x90,0x28,0x35,0x29,0xFE, ++}; ++ ++void Hal_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ /* ++ * Default Setting: ++ * setting1 [0e] => 8'h00 ++ * setting2 [0f] => 8'h00 ++ * setting3 [1a:10] => 165'h04 21 08 418c6318c4 21084210842108421086318c53 ++ */ ++ ++ MS_U8 *pu8Data = NULL; ++ MS_U16 u16Index = 0; ++ MS_U16 u16Data = 0; ++ ++ if (bUserDefinded == TRUE) ++ { ++ pu8Data = pu8Setting; ++ } ++ else ++ { ++ pu8Data = &u8VtrackKey[0]; ++ } ++ for (u16Index = 0; u16Index < VTRACK_KEY_SETTING_LENGTH; u16Index = u16Index+2) ++ { ++ MS_U8 u8Offset = (( (u16Index) / 2) *2 ); ++ MS_U32 u32Addr = REG_SCL1_24_L + u8Offset; ++ ++ if ( (VTRACK_KEY_SETTING_LENGTH - u16Index) >= 2) ++ { ++ u16Data = (MS_U16)pu8Data[u16Index +1]; ++ u16Data = (u16Data << 8) + (MS_U16) pu8Data[u16Index]; ++ W2BYTE(u32Addr, u16Data); ++ } ++ } ++ ++} ++ ++void Hal_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID) ++{ ++ /* ++ * reg_payload_use from 0x28 to 0x2C (1B - 1F) ++ * {14'h0, TimeCode[55:40], Unique ID (OTP)[39:8], Operator ID[7:0]} ++ */ ++ ++ W2BYTEMSK(REG_SCL1_28_L, (MS_U16)u8OperatorID, 0x00ff); ++ W2BYTEMSK(REG_SCL1_2A_L, (u16Timecode << 8) , 0xff00); ++ W2BYTEMSK(REG_SCL1_2B_L, (u16Timecode >> 8) , 0x00ff); ++ ++} ++ ++#define VTRACK_SETTING_LENGTH 23 ++ ++static MS_U8 u8VtrackSetting[VTRACK_SETTING_LENGTH]= ++{ ++ 0x00, 0x00, 0xe8, 0x18, 0x32, ++ 0x86, 0x10, 0x42, 0x08, 0x21, ++ 0x84, 0x10, 0x42, 0x08, 0x21, ++ 0xc4, 0x18, 0x63, 0x8c, 0x41, ++ 0x08, 0x21, 0x04, ++}; ++ ++void Hal_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting) ++{ ++ /* ++ * Default Setting: ++ * setting1 [0e] => 8'h00 ++ * setting2 [0f] => 8'h00 ++ * setting3 [1a:10] => 165'h04 21 08 418c6318c4 21084210842108421086318c53 ++ */ ++ ++ MS_U8 *pu8Data = NULL; ++ MS_U16 u16Index = 0; ++ MS_U16 u16Data = 0; ++ ++ if (bUserDefinded == TRUE) ++ { ++ pu8Data = pu8Setting; ++ } ++ else ++ { ++ pu8Data = &u8VtrackSetting[0]; ++ } ++ //MenuLoad enable ++ W2BYTEMSK(REG_SCL1_2E_L, pu8Data[0], 0xff); ++ W2BYTEMSK(REG_SCL1_2F_L, pu8Data[1], 0xff); ++ for (u16Index = 2; u16Index < VTRACK_SETTING_LENGTH; u16Index = u16Index+2) ++ { ++ MS_U8 u8Offset = (( (u16Index - 2) / 2) *2 ); ++ MS_U32 u32Addr = REG_SCL1_30_L + u8Offset; ++ ++ if ( (VTRACK_SETTING_LENGTH - u16Index) >= 2) ++ { ++ u16Data = (MS_U16)pu8Data[u16Index +1]; ++ u16Data = (u16Data << 8) + (MS_U16) pu8Data[u16Index]; ++ W2BYTE(u32Addr, u16Data); ++ } ++ else ++ { ++ u16Data = (MS_U16) pu8Data[u16Index]; ++ W2BYTEMSK(u32Addr, u16Data, 0x00ff); ++ } ++ } ++ ++} ++ ++#define VIP_VTRACK_MODE 0x1c //[3]:v_sync_inv_en ;[2]:h_sync_inv_en [4]mux ++void Hal_VIP_VtrackEnable(MS_U8 u8FrameRate, EN_VIP_VTRACK_ENABLE_TYPE bEnable) ++{ ++ //FrameRateIn => 8'h1E ++ W2BYTEMSK(REG_SCL1_21_L , u8FrameRate, 0xFF); ++ ++ //EnableIn => 1 ++ //DebugEn => 0 ++ if (bEnable == EN_VIP_VTRACK_ENABLE_ON) ++ { ++ W2BYTEMSK(REG_SCL1_20_L , BIT(0), BIT(1)|BIT(0) ); ++ W2BYTEMSK(REG_SCL1_22_L , VIP_VTRACK_MODE, 0x3F ); ++ } ++ else if(bEnable == EN_VIP_VTRACK_ENABLE_DEBUG) ++ { ++ W2BYTEMSK(REG_SCL1_20_L , BIT(1)|BIT(0), BIT(1)|BIT(0) ); ++ W2BYTEMSK(REG_SCL1_22_L , VIP_VTRACK_MODE, 0x3F ); ++ } ++ else ++ { ++ W2BYTEMSK(REG_SCL1_20_L , 0x00, BIT(1)|BIT(0) ); ++ W2BYTEMSK(REG_SCL1_22_L , VIP_VTRACK_MODE, 0x3F ); ++ } ++} ++void Hal_VIP_InitY2R(void) ++{ ++ W2BYTEMSK(REG_SCL_HVSP2_60_L, 0x0A01, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_61_L, 0x59E, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_62_L, 0x401, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_63_L, 0x1FFF, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_64_L, 0x1D24, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_65_L, 0x400, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_66_L, 0x1E9F, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_67_L, 0x1FFF, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_68_L, 0x400, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP2_69_L, 0x719, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_6C_L, 0x181, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_6D_L, 0x1FF, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_6E_L, 0x1E54, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_6F_L, 0x1FAD, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_70_L, 0x132, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_71_L, 0x259, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_72_L, 0x75, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_73_L, 0x1F53, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_74_L, 0x1EAD, 0x1FFF); ++ W2BYTEMSK(REG_SCL_HVSP1_75_L, 0x1FF, 0x1FFF); ++} ++ ++MS_BOOL Hal_VIP_GetVIPBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = R2BYTE(REG_VIP_LCE_70_L)&BIT0; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetMCNRBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = R2BYTE(REG_VIP_MCNR_01_L)&(BIT0|BIT1); ++ bRet = (((bRet)>>1))? 0: 1; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetLDCBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = (R2BYTE(REG_SCL_LDC_0F_L)&BIT0)? 1: 0; ++ return bRet; ++} ++MS_BOOL Hal_VIP_GetNLMBypass(void) ++{ ++ MS_BOOL bRet; ++ bRet = (R2BYTE(REG_SCL_NLM0_01_L)&BIT0)? 0: 1; ++ return bRet; ++} +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/include/halvip.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/include/halvip.h +new file mode 100644 +index 00000000..14250991 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/include/halvip.h +@@ -0,0 +1,209 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. 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If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef _HAL_VIP_H ++#define _HAL_VIP_H ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Defines & ENUM ++//------------------------------------------------------------------------------------------------- ++typedef enum ++{ ++ EN_VIP_SRAM_SEC_0 =289, ++ EN_VIP_SRAM_SEC_1 =272, ++ EN_VIP_SRAM_SEC_2 =272, ++ EN_VIP_SRAM_SEC_3 =256, ++ EN_VIP_SRAM_SEC_TYPE , ++}EN_VIP_SRAM_SEC_NUM; ++ ++typedef enum ++{ ++ EN_VIP_SRAM_DUMP_ICC, ++ EN_VIP_SRAM_DUMP_IHC, ++ EN_VIP_SRAM_DUMP_HVSP_V, ++ EN_VIP_SRAM_DUMP_HVSP_V_1, ++ EN_VIP_SRAM_DUMP_HVSP_V_2, ++ EN_VIP_SRAM_DUMP_WDR, ++ EN_VIP_SRAM_DUMP_GAMMA_Y, ++ EN_VIP_SRAM_DUMP_GAMMA_U, ++ EN_VIP_SRAM_DUMP_GAMMA_V, ++ EN_VIP_SRAM_DUMP_GM10to12_R, ++ EN_VIP_SRAM_DUMP_GM10to12_G, ++ EN_VIP_SRAM_DUMP_GM10to12_B, ++ EN_VIP_SRAM_DUMP_GM12to10_R, ++ EN_VIP_SRAM_DUMP_GM12to10_G, ++ EN_VIP_SRAM_DUMP_GM12to10_B, ++ EN_VIP_SRAM_DUMP_HVSP_H, ++ EN_VIP_SRAM_DUMP_HVSP_H_1, ++ EN_VIP_SRAM_DUMP_HVSP_H_2, ++ EN_VIP_SRAM_DUMP_NUM, ++}EN_VIP_SRAM_DUMP_TYPE; ++typedef enum ++{ ++ EN_VIP_VTRACK_ENABLE_ON, ++ EN_VIP_VTRACK_ENABLE_OFF, ++ EN_VIP_VTRACK_ENABLE_DEBUG, ++}EN_VIP_VTRACK_ENABLE_TYPE; ++//------------------------------------------------------------------------------------------------- ++// Structure ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Prototype ++//------------------------------------------------------------------------------------------------- ++#ifndef HAL_VIP_C ++#define INTERFACE extern ++#else ++#define INTERFACE ++#endif ++INTERFACE void Hal_VIP_SetLDCHWrwDiff(MS_U16 u8Val); ++INTERFACE void Hal_VIP_SetLDCSW_Mode(MS_U8 bEn); ++INTERFACE void Hal_VIP_SetLDCBank_Mode(EN_DRV_VIP_LDCLCBANKMODE_TYPE enType); ++INTERFACE void Hal_VIP_SetLDCSW_Idx(MS_U8 idx); ++INTERFACE void Hal_VIP_SetLDC422_444_Md(MS_U8 u8md); ++INTERFACE void Hal_VIP_SetLDC444_422_Md(MS_U8 u8md); ++INTERFACE void Hal_VIP_AIPDB(MS_U8 u8En); ++INTERFACE void Hal_VIP_MCNRInit(void); ++INTERFACE MS_BOOL Hal_VIP_GetSRAMDumpGammaYUV(EN_VIP_SRAM_DUMP_TYPE endump,void *u32Sram,MS_U32 u32reg); ++INTERFACE MS_BOOL Hal_VIP_GetSRAMDumpGammaRGB(EN_VIP_SRAM_DUMP_TYPE endump,void *u32Sram,MS_U32 u32reg); ++INTERFACE MS_BOOL Hal_VIP_GetSRAMDumpGammaRGBCallback(EN_VIP_SRAM_DUMP_TYPE endump,void *u32Sram,MS_U32 u32reg); ++INTERFACE MS_BOOL Hal_VIP_GetSRAMDumpGammaYUVCallback(EN_VIP_SRAM_DUMP_TYPE endump,void *u32Sram ,MS_U32 u32reg); ++INTERFACE void Hal_VIP_LDCECO(void); ++INTERFACE void Hal_VIP_Set_Riu_Base(MS_U32 u32riubase); ++INTERFACE void Hal_VIP_Exit(void); ++INTERFACE void Hal_VIP_DLCHistVarOnOff(MS_U16 u16var); ++INTERFACE void Hal_VIP_SetDLCstatMIU(MS_U8 u8value,MS_U32 u32addr1,MS_U32 u32addr2); ++INTERFACE void Hal_VIP_SetDLCshift(MS_U8 u8value); ++INTERFACE void HAl_VIP_SetDLCmode(MS_U8 u8value); ++INTERFACE void Hal_VIP_DLCHistSetRange(MS_U8 u8value,MS_U8 u8range); ++INTERFACE MS_U32 Hal_VIP_DLC_Hist_GetRange(MS_U8 u8range); ++INTERFACE void Hal_VIP_SetLDCBypass(MS_BOOL bEn); ++INTERFACE void Hal_VIP_SetLDCDmapPitch(MS_U32 u32Pitch); ++INTERFACE void Hal_VIP_SetLDCDmapBase(MS_U32 u32Base); ++INTERFACE void Hal_VIP_SetLDCDmapPS(MS_U8 bEn); ++INTERFACE void Hal_VIP_SetLDCDmapOffset(MS_U8 u8offset); ++INTERFACE void Hal_VIP_SetLDCSramAmount(MS_U16 u16hor,MS_U16 u16ver); ++INTERFACE void Hal_VIP_SetLDCSramBase(MS_U32 u32hor,MS_U32 u32ver); ++INTERFACE void Hal_VIP_SetLDCSramStr(MS_U16 u16hor,MS_U16 u16ver); ++INTERFACE MS_U8 Hal_VIP_DLCGetBaseidx(void); ++INTERFACE MS_U32 Hal_VIP_DLCGetPC(void); ++INTERFACE MS_U32 Hal_VIP_DLCGetPW(void); ++INTERFACE MS_U8 Hal_VIP_DLCGetMinP(void); ++INTERFACE MS_U8 Hal_VIP_DLCGetMaxP(void); ++INTERFACE void Hal_VIP_SetDLCActWin(MS_BOOL bEn,MS_U16 u16Vst,MS_U16 u16Hst,MS_U16 u16Vnd,MS_U16 u16Hnd); ++INTERFACE void Hal_VIP_SeMCNRIPMRead(MS_BOOL bEn); ++INTERFACE void Hal_VIP_SetIPMConpress(MS_BOOL bEn); ++INTERFACE void Hal_VIP_SeCIIRRead(MS_BOOL bEn); ++INTERFACE void Hal_VIP_SeCIIRWrite(MS_BOOL bEn); ++ ++INTERFACE void Hal_VIP_SetAutodownloadAddr(MS_U32 u32baseadr,MS_U16 u16iniaddr,MS_U8 u8cli); ++INTERFACE void Hal_VIP_SetAutodownloadReq(MS_U16 u16depth,MS_U16 u16reqlen,MS_U8 u8cli); ++INTERFACE void Hal_VIP_SetAutodownload(MS_U8 bCLientEn,MS_U8 btrigContinue,MS_U8 u8cli); ++INTERFACE void Hal_VIP_SetAutodownloadTimer(MS_U8 bCLientEn); ++INTERFACE void Hal_VIP_GetNLMSRAM(MS_U16 u16entry); ++INTERFACE void Hal_VIP_SetNLMSRAMbyCPU(MS_U16 u16entry,MS_U32 u32tvalue); ++INTERFACE MS_U8 Hal_VIP_SRAM_Dump(EN_VIP_SRAM_DUMP_TYPE endump,void* u32Sram); ++INTERFACE void Hal_VIP_VtrackEnable(MS_U8 u8FrameRate, EN_VIP_VTRACK_ENABLE_TYPE bEnable); ++INTERFACE void Hal_VIP_VtrackSetUserDefindedSetting(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE void Hal_VIP_VtrackSetKey(MS_BOOL bUserDefinded, MS_U8 *pu8Setting); ++INTERFACE void Hal_VIP_VtrackSetPayloadData(MS_U16 u16Timecode, MS_U8 u8OperatorID); ++INTERFACE MS_BOOL Hal_VIP_GetVIPBypass(void); ++INTERFACE void Hal_VIP_InitY2R(void); ++INTERFACE MS_BOOL Hal_VIP_GetMCNRBypass(void); ++INTERFACE MS_BOOL Hal_VIP_GetLDCBypass(void); ++INTERFACE MS_BOOL Hal_VIP_GetNLMBypass(void); ++ #undef INTERFACE ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/include/halvip_utility.h b/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/include/halvip_utility.h +new file mode 100644 +index 00000000..5ddf71f7 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/hal/vip/include/halvip_utility.h +@@ -0,0 +1,64 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _HALSCL_UTILITY_H_ ++#define _HALSCL_UTILITY_H_ ++ ++//!! Do not include this header in driver or api level ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++extern MS_U32 SCL_RIU_BASE; // This should be inited before XC library starting. ++ ++ ++#define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) ++#define BITMASK(x) _BITMASK(1?x, 0?x) ++ ++#define HBMASK 0xFF00 ++#define LBMASK 0x00FF ++ ++#define RIU_MACRO_START do { ++#define RIU_MACRO_END } while (0) ++ ++ ++// Address bus of RIU is 16 bits. ++#define RIU_READ_BYTE(addr) ( READ_BYTE( VIP_RIU_BASE+ (addr) ) ) ++#define RIU_READ_2BYTE(addr) ( READ_WORD( VIP_RIU_BASE + (addr) ) ) ++#define RIU_WRITE_BYTE(addr, val) WRITE_BYTE( (VIP_RIU_BASE + (addr)), val) ++#define RIU_WRITE_2BYTE(addr, val) WRITE_WORD( VIP_RIU_BASE + (addr), val) ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++ ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++ ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++ ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/include/MsCommon.h b/drivers/mstar/scl/infinity3/src/mxlib/include/MsCommon.h +new file mode 100644 +index 00000000..f200f639 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/include/MsCommon.h +@@ -0,0 +1,208 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsCommon.h ++/// @brief MStar Common Interface Header File ++/// @author MStar Semiconductor Inc. ++/// @note MsCommon.h includes most command header files including basic data type, macro(MsTypes.h),\n ++/// board configuration(MsBoard.h), and OS related API(MsOS.h).\n ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_COMMON_H_ ++#define _MS_COMMON_H_ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include "ms_platform.h" ++#include ++#include ++ ++#endif ++ ++#ifndef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#else ++#endif ++ ++#include ++//#include ++ ++#include "MsTypes.h" ++#include "MsIRQ.h" ++//#include "MsVersion.h" ++#include "MsOS.h" // Plan to be obsoleted in next generation. ++#include "MsDevice.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Defines ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Macros ++//------------------------------------------------------------------------------------------------- ++#define GEN_EXCEP { while(1); } ++ ++//#define REG(addr) (*(volatile U32 *)(addr)) ++#if 0 ++#ifdef __aeon__ ++ ++//------------------------------------------------------------------------------------------------- ++// In order to keep the compatiblity of the source code from Venus, ++// keep these memory address translation for a while. ++// They will be removed in the future. ++//------------------------------------------------------------------------------------------------- ++#define CACHED_BASE ((void *)0x00000000) ++#define UNCACHED_BASE ((void *)0x80000000) ++ ++#define CACHED_SIZE ((void *)0x20000000) ++#define UNCACHED_SIZE ((void *)0x20000000) ++// 0xA0000000~0xA000FFFF belongs to RIU ++// 0xA1000000~ belongs to SPI ++ ++//cached/unchched segment ++#define KSEG0_BASE CACHED_BASE ++#define KSEG1_BASE UNCACHED_BASE ++#define KSEG0_SIZE CACHED_SIZE ++#define KSEG1_SIZE UNCACHED_SIZE ++ ++//cached <-> uncached ++#define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x80000000)) ++#define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x80000000)) ++ ++//virtual <-> physical ++#define VA2PA(addr) ((void *)(((U32)addr) & 0x1fffffff)) ++#define PA2KSEG0(addr) ((void *)(((U32)addr) | 0x00000000)) ++#define PA2KSEG1(addr) ((void *)(((U32)addr) | 0x80000000)) ++#endif ++ ++#if defined(__mips__) ++ ++//cached/unchched segment ++#define KSEG0_BASE ((void *)0x80000000) ++#define KSEG1_BASE ((void *)0xa0000000) ++#define KSEG0_SIZE 0x20000000 ++#define KSEG1_SIZE 0x20000000 ++ ++//cached addr <-> unchched addr ++#define KSEG02KSEG1(addr) ((void *)((MS_U32)(addr)|0x20000000)) //cached -> unchched ++#define KSEG12KSEG0(addr) ((void *)((MS_U32)(addr)&~0x20000000)) //unchched -> cached ++ ++//virtual addr <-> physical addr ++#define VA2PA(addr) ((void *)(((MS_U32)addr) & 0x1fffffff)) //virtual -> physical ++#define PA2KSEG0(addr) ((void *)(((MS_U32)addr) | 0x80000000)) //physical -> cached ++#define PA2KSEG1(addr) ((void *)(((MS_U32)addr) | 0xa0000000)) //physical -> unchched ++#endif ++#endif ++ ++#if 0 ++//cached/unchched segment ++#define KSEG0_BASE ((void *)0x80000000) ++#define KSEG1_BASE ((void *)0xa0000000) ++#define KSEG0_SIZE 0x20000000 ++#define KSEG1_SIZE 0x20000000 ++ ++//cached <-> unchched ++#define KSEG02KSEG1(addr) ((void *)((U32)(addr)|0x20000000)) ++#define KSEG12KSEG0(addr) ((void *)((U32)(addr)&~0x20000000)) ++ ++//virtual <-> physical ++#define VA2PA(addr) ((void *)(((U32)addr) & 0x1fffffff)) ++#define PA2KSEG0(addr) ((void *)(((U32)addr) | 0x80000000)) ++#define PA2KSEG1(addr) ((void *)(((U32)addr) | 0xa0000000)) ++#endif ++ ++//user-defined assert ++#ifdef MS_DEBUG ++#define MS_ASSERT(_bool_) \ ++ { \ ++ if ( ! ( _bool_ ) ) \ ++ { \ ++/* UTL_printf("ASSERT FAIL: %s, %s %s %d\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__); */ \ ++/* MAsm_CPU_SwDbgBp(); */ \ ++ } \ ++ } ++#else ++#define MS_ASSERT(_bool_) \ ++ { \ ++ if ( ! ( _bool_ ) ) \ ++ { \ ++/* UTL_printf("ASSERT FAIL: %s %s %s %d\n", #_bool_, __FILE__, __PRETTY_FUNCTION__, __LINE__); */ \ ++ } \ ++ } ++#endif ++ ++ ++#ifndef MIN ++#define MIN(_a_, _b_) ((_a_) < (_b_) ? (_a_) : (_b_)) ++#endif ++#ifndef MAX ++#define MAX(_a_, _b_) ((_a_) > (_b_) ? (_a_) : (_b_)) ++#endif ++ ++ ++#define ALIGN_4(_x_) (((_x_) + 3) & ~3) ++#define ALIGN_8(_x_) (((_x_) + 7) & ~7) ++#define ALIGN_16(_x_) (((_x_) + 15) & ~15) // No data type specified, optimized by complier ++#define ALIGN_32(_x_) (((_x_) + 31) & ~31) // No data type specified, optimized by complier ++ ++#define MASK(x) (((1<<(x##_BITS))-1) << x##_SHIFT) ++ ++ ++//!!! avoid warning of out-of-range integer !!!// ++#if defined(MSOS_TYPE_NOS) // for chip back verificatoin ++#define BIT(_bit_) (1UL << (_bit_)) ++#else ++ ++#ifndef BIT ++#define BIT(_bit_) (1 << (_bit_)) ++#endif ++ ++#endif ++ ++#define BIT_(x) BIT(x) //[OBSOLETED] //TODO: remove it later ++#define BITS(_bits_, _val_) ((BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) & (_val_<<((0)?_bits_))) ++#define BMASK(_bits_) (BIT(((1)?_bits_)+1)-BIT(((0)?_bits_))) ++ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++ ++#define READ_BYTE(x) ms_readb(x) ++#define READ_WORD(x) ms_readw(x) ++#define READ_LONG(x) ms_readl(x) ++#define WRITE_BYTE(x, y) ms_writeb((MS_U8)(y), x) ++#define WRITE_WORD(x, y) ms_writew((MS_U16)(y), x) ++#define WRITE_LONG(x, y) ms_writel((MS_U32)(y), x) ++ ++#else ++ ++#define READ_BYTE(_reg) (*(volatile MS_U8*)(_reg)) ++#define READ_WORD(_reg) (*(volatile MS_U16*)(_reg)) ++#define READ_LONG(_reg) (*(volatile MS_U32*)(_reg)) ++ ++#if ( defined(MSOS_TYPE_CE) || defined(MSOS_TYPE_NOS) ) ++ #define WRITE_BYTE(_reg, _val) (*((volatile MS_U8*)(_reg))) = (MS_U8)(_val) ++ #define WRITE_WORD(_reg, _val) (*((volatile MS_U16*)(_reg))) = (MS_U16)(_val) ++#else ++ #define WRITE_BYTE(_reg, _val) { (*((volatile MS_U8*)(_reg))) = (MS_U8)(_val); } ++ #define WRITE_WORD(_reg, _val) { (*((volatile MS_U16*)(_reg))) = (MS_U16)(_val); } ++#endif ++#define WRITE_LONG(_reg, _val) { (*((volatile MS_U32*)(_reg))) = (MS_U32)(_val); } ++#endif ++ ++#endif // _MS_COMMON_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/include/MsDbg.h b/drivers/mstar/scl/infinity3/src/mxlib/include/MsDbg.h +new file mode 100644 +index 00000000..76b831d5 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/include/MsDbg.h +@@ -0,0 +1,28 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MS_DBG_H_ ++#define _MS_DBG_H_ ++ ++#define ENABLE_HVSP_UNUSED_FUNCTION 0 ++#define ENABLE_PNL_UNUSED_FUNCTION 0 ++#define ENABLE_SCLDMA_UNUSED_FUNCTION 0 ++#define ENABLE_VIP_UNUSED_FUNCTION 0 ++#define ENABLE_PQ_UNUSED_FUNCTION 0 ++ ++#endif // _MS_DBG_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/include/MsDevice.h b/drivers/mstar/scl/infinity3/src/mxlib/include/MsDevice.h +new file mode 100644 +index 00000000..784a480e +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/include/MsDevice.h +@@ -0,0 +1,158 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef __PRANA_DEVICE_H__ ++#define __PRANA_DEVICE_H__ ++ ++#include "MsTypes.h" ++ ++#define DEVICE_NULL ((device_t)0) ++ ++typedef unsigned long device_t; ++ ++// ++// device PM event ++// ++typedef enum ++{ ++ E_EVT_SUSPEND = 1, ++ E_EVT_SHUTDOWN = 2, ++} eDEVEVT; ++ ++// ++// poll types ++// ++ ++#ifndef POLLIN ++#define POLLIN 0x01 ++#endif ++ ++#ifndef POLLOUT ++#define POLLOUT 0x02 ++#endif ++ ++#ifndef POLLHUP ++#define POLLHUP 0x04 ++#endif ++ ++// ++// device I/O operations ++// ++struct devio ++{ ++ int (*open) (device_t dev, int mode); ++ int (*close)(device_t dev); ++// int (*read) (device_t dev, char *buf, size_t len, int off); ++ int (*read) (device_t dev, char *buf, MS_U32 len, int off); ++// int (*write)(device_t dev, const char *buf, size_t len, int off); ++ int (*write)(device_t dev, const char *buf, MS_U32 len, int off); ++ int (*poll) (device_t dev, int types); ++ int (*ioctl)(device_t dev, int request, unsigned long arg); ++ int (*event)(eDEVEVT evt); ++}; ++ ++ ++#define DEVICE_MAGIC (('D' << 24) | ('E' << 16) | ('V' << 8) | 'I') ++ ++// ++// device structure ++// ++#if 0 ++struct device ++{ ++ int magic; // magic number ++ int refcnt; // reference count ++ int flags; // device characteristics ++ struct devio *devio; // device i/o table ++}; ++#endif ++ ++#define device_valid(dev) ((dev)->magic == DEVICE_MAGIC) ++#endif /* __PRANA_DEVICE_H__ */ ++ ++//MSTAR Module ID ++/******************************************************************************* ++!!!! WARNING NOT ALLOW MODIFY EXISTED VALUE !!!! ++!!!! ONLY ALLOW ADD NEW VALUE AFTER END OF THIS LIST !!!! ++*******************************************************************************/ ++#define MS_MODULE_HW 0x0000 ++ ++#define MS_MODULE_CHIPTOP 0x0011 ++#define MS_MODULE_MIU 0x0012 ++#define MS_MODULE_WDT 0x003C ++#define MS_MODULE_CFG 0x00F0 // Chip hard configuration info ++#define MS_MODULE_OTP 0x00F4 ++#define MS_MODULE_SPRAM 0x00F5 ++ ++#define MS_MODULE_ACE 0x0101 ++#define MS_MODULE_AUDIO 0x0102 ++#define MS_MODULE_AVD 0x0103 ++#define MS_MODULE_BDMA 0x0104 ++#define MS_MODULE_DLC 0x0105 ++#define MS_MODULE_FLASH 0x0106 ++#define MS_MODULE_GE 0x0107 ++#define MS_MODULE_GOP 0x0108 ++#define MS_MODULE_HVD 0x0109 ++#define MS_MODULE_HWI2C 0x010a ++#define MS_MODULE_IR 0x010b ++#define MS_MODULE_IRQ 0x010c ++#define MS_MODULE_JPD 0x010d ++#define MS_MODULE_MBX 0x010e ++#define MS_MODULE_MVD 0x010f ++#define MS_MODULE_MVOP 0x0120 ++#define MS_MODULE_RVD 0x0122 ++#define MS_MODULE_SC 0x0123 ++#define MS_MODULE_TSP 0x0124 ++#define MS_MODULE_UART 0x0125 ++#define MS_MODULE_VPU 0x0126 ++#define MS_MODULE_XC 0x0127 ++#define MS_MODULE_PNL 0x0128 ++#define MS_MODULE_ISP 0x0129 ++#define MS_MODULE_PFSH 0x012a ++#define MS_MODULE_GPIO 0x012b ++#define MS_MODULE_PM 0x012c ++#define MS_MODULE_VBI 0x012d ++#define MS_MODULE_PCMCIA 0x012e ++#define MS_MODULE_PIU 0x012f ++#define MS_MODULE_MHEG5 0x0130 ++#define MS_MODULE_RTC_0 0x0131 ++#define MS_MODULE_RTC_2 0x0132 ++#define MS_MODULE_VIF 0x0133 ++#define MS_MODULE_MFE 0x0134 ++#define MS_MODULE_DIP 0x0135 ++#define MS_MODULE_RASP 0x0136 ++#define MS_MODULE_MMFILEIN 0x0137 ++#define MS_MODULE_MPIF 0x0138 ++#define MS_MODULE_GPD 0x0139 ++#define MS_MODULE_TSO 0x013a ++#define MS_MODULE_IMI 0x013b // for C3 ++ ++ ++#define MS_MODULE_SEM 0x02f0 ++ ++#define MS_MODULE_CA 0x0300 // CA reserved ++#define MS_MODULE_NDS 0x0310 // NDS ++#define MS_MODULE_NSK 0x0311 ++#define MS_MODULE_CAM 0x0312 ++#define MS_MODULE_NGA 0x0313 ++ ++#define MS_MODULE_PWM 0x1032 ++#define MS_MODULE_DMD 0x1033 ++#define MS_MODULE_PWS 0x1034 ++#define MS_MODULE_EFUSE 0x1035 ++ ++#define MS_MODULE_FRC 0x2000 // A5 only +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/include/MsIRQ.h b/drivers/mstar/scl/infinity3/src/mxlib/include/MsIRQ.h +new file mode 100644 +index 00000000..832417cf +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/include/MsIRQ.h +@@ -0,0 +1,420 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file MsIRQ.h ++/// @brief MStar IRQ ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MS_IRQ_H_ ++#define _MS_IRQ_H_ ++ ++ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure Declaration ++//------------------------------------------------------------------------------------------------- ++#define MS_IRQ_MAX (128) //64 IRQs + 64 FIQs ++#define ENABLE_USB_PORT0 ++#define E_IRQ_FIQ_INVALID 0xFFFF ++ ++// Interrupt related ++typedef enum ++{ ++ // IRQ ++ E_INT_IRQ_0x00_START = 0x00, ++ E_INT_IRQ_UART0 = E_INT_IRQ_0x00_START+0, ++ E_INT_IRQ_BDMA_CH0 = E_INT_IRQ_0x00_START+1, ++ E_INT_IRQ_BDMA_CH1 = E_INT_IRQ_0x00_START+2, ++ E_INT_IRQ_MVD = E_INT_IRQ_0x00_START+3, ++ E_INT_IRQ_PS = E_INT_IRQ_0x00_START+4, ++ E_INT_IRQ_NFIE = E_INT_IRQ_0x00_START+5, ++ E_INT_IRQ_USB = E_INT_IRQ_0x00_START+6, ++ E_INT_IRQ_UHC = E_INT_IRQ_0x00_START+7, ++ E_INT_IRQ_EC_BRIDGE = E_INT_IRQ_0x00_START+8, ++ E_INT_IRQ_EMAC = E_INT_IRQ_0x00_START+9, ++ E_INT_IRQ_DISP = E_INT_IRQ_0x00_START+10, ++ E_INT_IRQ_DHC = E_INT_IRQ_0x00_START+11, ++ E_INT_IRQ_PMSLEEP = E_INT_IRQ_0x00_START+12, ++ E_INT_IRQ_SBM = E_INT_IRQ_0x00_START+13, ++ E_INT_IRQ_COMB = E_INT_IRQ_0x00_START+14, ++ E_INT_IRQ_ECC_DERR = E_INT_IRQ_0x00_START+15, ++ E_INT_IRQ_0x00_END = 0x0F, ++ ++ E_INT_IRQ_0x10_START = 0x10, ++ E_INT_IRQ_TSP2HK = E_INT_IRQ_0x10_START+0, ++ E_INT_IRQ_VE = E_INT_IRQ_0x10_START+1, ++ E_INT_IRQ_CIMAX2MCU = E_INT_IRQ_0x10_START+2, ++ E_INT_IRQ_DC = E_INT_IRQ_0x10_START+3, ++ E_INT_IRQ_GOP = E_INT_IRQ_0x10_START+4, ++ E_INT_IRQ_PCM = E_INT_IRQ_0x10_START+5, ++ E_INT_IRQ_IIC0 = E_INT_IRQ_0x10_START+6, ++ E_INT_IRQ_RTC = E_INT_IRQ_0x10_START+7, ++ E_INT_IRQ_KEYPAD = E_INT_IRQ_0x10_START+8, ++ E_INT_IRQ_PM = E_INT_IRQ_0x10_START+9, ++ E_INT_IRQ_DDC2BI = E_INT_IRQ_0x10_START+10, ++ E_INT_IRQ_SCM = E_INT_IRQ_0x10_START+11, ++ E_INT_IRQ_VBI = E_INT_IRQ_0x10_START+12, ++ E_INT_IRQ_M4VD = E_INT_IRQ_0x10_START+13, ++ E_INT_IRQ_FCIE2RIU = E_INT_IRQ_0x10_START+14, ++ E_INT_IRQ_ADCDVI2RIU = E_INT_IRQ_0x10_START+15, ++ E_INT_IRQ_0x10_END = 0x1F, ++ ++ // FIQ ++ E_INT_FIQ_0x20_START = 0x20, ++ E_INT_FIQ_EXTIMER0 = E_INT_FIQ_0x20_START+0, ++ E_INT_FIQ_EXTIMER1 = E_INT_FIQ_0x20_START+1, ++ E_INT_FIQ_WDT = E_INT_FIQ_0x20_START+2, ++ E_INT_FIQ_AEON_TO_8051 = E_INT_FIQ_0x20_START+3, ++ E_INT_FIQ_8051_TO_AEON = E_INT_FIQ_0x20_START+4, ++ E_INT_FIQ_8051_TO_BEON = E_INT_FIQ_0x20_START+5, ++ E_INT_FIQ_BEON_TO_8051 = E_INT_FIQ_0x20_START+6, ++ E_INT_FIQ_BEON_TO_AEON = E_INT_FIQ_0x20_START+7, ++ E_INT_FIQ_AEON_TO_BEON = E_INT_FIQ_0x20_START+8, ++ E_INT_FIQ_JPD = E_INT_FIQ_0x20_START+9, ++ E_INT_FIQ_MENULOAD = E_INT_FIQ_0x20_START+10, ++ E_INT_FIQ_HDMI_NON_PCM = E_INT_FIQ_0x20_START+11, ++ E_INT_FIQ_SPDIF_IN_NON_PCM = E_INT_FIQ_0x20_START+12, ++ E_INT_FIQ_EMAC = E_INT_FIQ_0x20_START+13, ++ E_INT_FIQ_SE_DSP2UP = E_INT_FIQ_0x20_START+14, ++ E_INT_FIQ_TSP2AEON = E_INT_FIQ_0x20_START+15, ++ E_INT_FIQ_0x20_END = 0x2F, ++ ++ E_INT_FIQ_0x30_START = 0x30, ++ E_INT_FIQ_VIVALDI_STR = E_INT_FIQ_0x30_START+0, ++ E_INT_FIQ_VIVALDI_PTS = E_INT_FIQ_0x30_START+1, ++ E_INT_FIQ_DSP_MIU_PROT = E_INT_FIQ_0x30_START+2, ++ E_INT_FIQ_XIU_TIMEOUT = E_INT_FIQ_0x30_START+3, ++ E_INT_FIQ_DMA_DONE = E_INT_FIQ_0x30_START+4, ++ E_INT_FIQ_VSYNC_VE4VBI = E_INT_FIQ_0x30_START+5, ++ E_INT_FIQ_FIELD_VE4VBI = E_INT_FIQ_0x30_START+6, ++ E_INT_FIQ_VDMCU2HK = E_INT_FIQ_0x30_START+7, ++ E_INT_FIQ_VE_DONE_TT = E_INT_FIQ_0x30_START+8, ++ E_INT_FIQ_INT_CCFL = E_INT_FIQ_0x30_START+9, ++ E_INT_FIQ_INT = E_INT_FIQ_0x30_START+10, ++ E_INT_FIQ_IR = E_INT_FIQ_0x30_START+11, ++ E_INT_FIQ_AFEC_VSYNC = E_INT_FIQ_0x30_START+12, ++ E_INT_FIQ_DEC_DSP2UP = E_INT_FIQ_0x30_START+13, ++ E_INT_FIQ_MIPS_WDT = E_INT_FIQ_0x30_START+14, //U3 ++ E_INT_FIQ_DEC_DSP2MIPS = E_INT_FIQ_0x30_START+15, ++ E_INT_FIQ_0x30_END = 0x3F, ++ ++ E_INT_IRQ_0x40_START = 0x40, ++ E_INT_IRQ_SVD_HVD = E_INT_IRQ_0x40_START+0, ++ E_INT_IRQ_USB2 = E_INT_IRQ_0x40_START+1, ++ E_INT_IRQ_UHC2 = E_INT_IRQ_0x40_START+2, ++ E_INT_IRQ_MIU = E_INT_IRQ_0x40_START+3, ++ E_INT_IRQ_GDMA = E_INT_IRQ_0x40_START+4, //U3 ++ E_INT_IRQ_UART2 = E_INT_IRQ_0x40_START+5, //U3 ++ E_INT_IRQ_UART1 = E_INT_IRQ_0x40_START+6, //U3 ++ E_INT_IRQ_DEMOD = E_INT_IRQ_0x40_START+7, //U3 ++ E_INT_IRQ_MPIF = E_INT_IRQ_0x40_START+8, //U3 ++ E_INT_IRQ_JPD = E_INT_IRQ_0x40_START+9, //U3 ++ E_INT_IRQ_AEON2HI = E_INT_IRQ_0x40_START+10, //U3 ++ E_INT_IRQ_BDMA0 = E_INT_IRQ_0x40_START+11, //U3 ++ E_INT_IRQ_BDMA1 = E_INT_IRQ_0x40_START+12, //U3 ++ E_INT_IRQ_OTG = E_INT_IRQ_0x40_START+13, //U3 ++ E_INT_IRQ_MVD_CHECKSUM_FAIL = E_INT_IRQ_0x40_START+14, //U3 ++ E_INT_IRQ_TSP_CHECKSUM_FAIL = E_INT_IRQ_0x40_START+15, //U3 ++ E_INT_IRQ_0x40_END = 0x4F, ++ ++ E_INT_IRQ_0x50_START = 0x50, ++ E_INT_IRQ_CA_I3 = E_INT_IRQ_0x50_START+0, //U3 ++ E_INT_IRQ_HDMI_LEVEL = E_INT_IRQ_0x50_START+1, //U3 ++ E_INT_IRQ_MIPS_WADR_ERR = E_INT_IRQ_0x50_START+2, //U3 ++ E_INT_IRQ_RASP = E_INT_IRQ_0x50_START+3, //U3 ++ E_INT_IRQ_CA_SVP = E_INT_IRQ_0x50_START+4, //U3 ++ E_INT_IRQ_UART2MCU = E_INT_IRQ_0x50_START+5, //U3 ++ E_INT_IRQ_URDMA2MCU = E_INT_IRQ_0x50_START+6, //U3 ++ E_INT_IRQ_IIC1 = E_INT_IRQ_0x50_START+7, //U3 ++ E_INT_IRQ_HDCP = E_INT_IRQ_0x50_START+8, //U3 ++ E_INT_IRQ_DMA_WADR_ERR = E_INT_IRQ_0x50_START+9, //U3 ++ E_INT_IRQ_UP_IRQ_UART_CA = E_INT_IRQ_0x50_START+10, //U3 ++ E_INT_IRQ_UP_IRQ_EMM_ECM = E_INT_IRQ_0x50_START+11, //U3 ++ E_INT_IRQ_ONIF = E_INT_IRQ_0x50_START+12, //T8 ++ E_INT_IRQ_USB1 = E_INT_IRQ_0x50_START+13, //T8 ++ E_INT_IRQ_UHC1 = E_INT_IRQ_0x50_START+14, //T8 ++ E_INT_IRQ_MFE = E_INT_IRQ_0x50_START+15, //T8 ++ E_INT_IRQ_0x50_END = 0x5F, ++ ++ E_INT_FIQ_0x60_START = 0x60, ++ E_INT_FIQ_IR_INT_RC = E_INT_FIQ_0x60_START+0, //U3 ++ E_INT_FIQ_HDMITX_IRQ_EDGE = E_INT_FIQ_0x60_START+1, //U3 ++ E_INT_FIQ_UP_IRQ_UART_CA = E_INT_FIQ_0x60_START+2, //U3 ++ E_INT_FIQ_UP_IRQ_EMM_ECM = E_INT_FIQ_0x60_START+3, //U3 ++ E_INT_FIQ_PVR2MI_INT0 = E_INT_FIQ_0x60_START+4, //U3 ++ E_INT_FIQ_PVR2MI_INT1 = E_INT_FIQ_0x60_START+5, //U3 ++ //E_INT_FIQ_8051_TO_AEON = E_INT_FIQ_0x60_START+6, //T3, E_INT_FIQ_8051_TO_AEON ++ //Not Used = E_INT_FIQ_0x60_START+7, ++ E_INT_FIQ_AEON_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+8, //T3, ++ E_INT_FIQ_AEON_TO_MIPS_VPE1 = E_INT_FIQ_0x60_START+9, //T3, E_INT_FIQ_AEON_TO_BEON ++ //E_INT_FIQ_AEON_TO_8051 = E_INT_FIQ_0x60_START+10, //T3, E_INT_FIQ_AEON_TO_8051 ++ //Not Used = E_INT_FIQ_0x60_START+11, ++ E_INT_FIQ_MIPS_VPE1_TO_MIPS_VPE0 = E_INT_FIQ_0x60_START+12, //T3 ++ E_INT_FIQ_MIPS_VPE1_TO_AEON = E_INT_FIQ_0x60_START+13, //T3 ++ E_INT_FIQ_MIPS_VPE1_TO_8051 = E_INT_FIQ_0x60_START+14, //T3 ++ //Not Used = E_INT_FIQ_0x60_START+15, ++ E_INT_FIQ_0x60_END = 0x6F, ++ ++ E_INT_FIQ_0x70_START = 0x70, ++ E_INT_FIQ_MIPS_VPE0_TO_MIPS_VPE1 = E_INT_FIQ_0x70_START+0, //T3 ++ E_INT_FIQ_MIPS_VPE0_TO_AEON = E_INT_FIQ_0x70_START+1, //T3, E_INT_FIQ_AEON_TO_BEON ++ E_INT_FIQ_MIPS_VPE0_TO_8051 = E_INT_FIQ_0x70_START+2, //T3, E_INT_FIQ_BEON_TO_8051 ++ E_INT_FIQ_IR_IN = E_INT_FIQ_0x70_START+3, //T8 ++ E_INT_FIQ_DMDMCU2HK = E_INT_FIQ_0x70_START+4, ++ E_INT_FIQ_R2TOMCU_INT0 = E_INT_FIQ_0x70_START+5, //T8 ++ E_INT_FIQ_R2TOMCU_INT1 = E_INT_FIQ_0x70_START+6, //T8 ++ E_INT_FIQ_DSPTOMCU_INT0 = E_INT_FIQ_0x70_START+7, //T8 ++ E_INT_FIQ_DSPTOMCU_INT1 = E_INT_FIQ_0x70_START+8, //T8 ++ E_INT_FIQ_USB = E_INT_FIQ_0x70_START+9, //T8 ++ E_INT_FIQ_UHC = E_INT_FIQ_0x70_START+10, //T8 ++ E_INT_FIQ_USB1 = E_INT_FIQ_0x70_START+11, //T8 ++ E_INT_FIQ_UHC1 = E_INT_FIQ_0x70_START+12, //T8 ++ E_INT_FIQ_USB2 = E_INT_FIQ_0x70_START+13, //T8 ++ E_INT_FIQ_UHC2 = E_INT_FIQ_0x70_START+14, //T8 ++ //Not Used = E_INT_FIQ_0x70_START+15, ++ E_INT_FIQ_0x70_END = 0x7F, ++ ++ ++ // Add IRQ from 0x80 ~ 0xBF, ++ // if IRQ enum from 0x00 ~ 0x1F, and 0x40 ~ 0x5F is occupied ++ E_INT_IRQ_0x80_START = 0x80, ++ E_INT_IRQ_MLINK = E_INT_IRQ_0x80_START+0, //U3 ++ E_INT_IRQ_AFEC = E_INT_IRQ_0x80_START+1, //T3 ++ E_INT_IRQ_DPTX = E_INT_IRQ_0x80_START+2, //T3 ++ E_INT_IRQ_TMDDRLINK = E_INT_IRQ_0x80_START+3, //T3 ++ E_INT_IRQ_DISPI = E_INT_IRQ_0x80_START+4, //T3 ++ E_INT_IRQ_EXP_MLINK = E_INT_IRQ_0x80_START+5, //T3 ++ E_INT_IRQ_M4VE = E_INT_IRQ_0x80_START+6, //T3 ++ E_INT_IRQ_DVI_HDMI_HDCP = E_INT_IRQ_0x80_START+7, //T3 ++ E_INT_IRQ_G3D2MCU = E_INT_IRQ_0x80_START+8, //T3 ++ E_INT_IRQ_VP6 = E_INT_IRQ_0x80_START+9, //A3 ++ //Not Used = E_INT_IRQ_0x80_START+10, ++ E_INT_IRQ_CEC = E_INT_IRQ_0x80_START+11, //T8 ++ E_INT_IRQ_HDCP_IIC = E_INT_IRQ_0x80_START+12, //T8 ++ E_INT_IRQ_HDCP_X74 = E_INT_IRQ_0x80_START+13, //T8 ++ E_INT_IRQ_WADR_ERR = E_INT_IRQ_0x80_START+14, //T8 ++ E_INT_IRQ_DCSUB = E_INT_IRQ_0x80_START+15, //T8 ++ E_INT_IRQ_0x80_END = 0x8F, ++ ++ E_INT_IRQ_0x90_START = 0x90, ++ E_INT_IRQ_GE = E_INT_IRQ_0x90_START+0, //T8 ++ E_INT_IRQ_SYNC_DET = E_INT_IRQ_0x90_START+1, //M10 ++ E_INT_IRQ_FSP = E_INT_IRQ_0x90_START+2, //M10 ++ E_INT_IRQ_PWM_RP_L = E_INT_IRQ_0x90_START+3, //M10 ++ E_INT_IRQ_PWM_FP_L = E_INT_IRQ_0x90_START+4, //M10 ++ E_INT_IRQ_PWM_RP_R = E_INT_IRQ_0x90_START+5, //M10 ++ E_INT_IRQ_PWM_FP_R = E_INT_IRQ_0x90_START+6, //M10 ++ E_INT_IRQ_FRC_SC = E_INT_IRQ_0x90_START+7, //A5 ++ E_INT_IRQ_FRC_INT_FIQ2HST0 = E_INT_IRQ_0x90_START+8, //A5 ++ E_INT_IRQ_SMART = E_INT_IRQ_0x90_START+9, //A5 ++ E_INT_IRQ_MVD2MIPS = E_INT_IRQ_0x90_START+10, //A5 ++ E_INT_IRQ_GPD = E_INT_IRQ_0x90_START+11, //A5 ++ //Not Used = E_INT_IRQ_0x90_START+12, //A5 ++ E_INT_IRQ_FRC_INT_IRQ2HST0 = E_INT_IRQ_0x90_START+13, //A5 ++ E_INT_IRQ_MIIC_DMA_INT3 = E_INT_IRQ_0x90_START+14, //A5 ++ E_INT_IRQ_MIIC_INT3 = E_INT_IRQ_0x90_START+15, //A5 ++ E_INT_IRQ_0x90_END = 0x9F, ++ ++ E_INT_IRQ_0xA0_START = 0xA0, ++ E_INT_IRQ_IIC2 = E_INT_IRQ_0xA0_START+0, //A1 ++ E_INT_IRQ_MIIC_DMA0 = E_INT_IRQ_0xA0_START+1, //A1 ++ E_INT_IRQ_MIIC_DMA1 = E_INT_IRQ_0xA0_START+2, //A1 ++ E_INT_IRQ_MIIC_DMA2 = E_INT_IRQ_0xA0_START+3, //A1 ++ E_INT_IRQ_MSPI0 = E_INT_IRQ_0xA0_START+4, //A1 ++ E_INT_IRQ_MSPI1 = E_INT_IRQ_0xA0_START+5, //A1 ++ E_INT_IRQ_EXT_GPIO0 = E_INT_IRQ_0xA0_START+6, //A1 ++ E_INT_IRQ_EXT_GPIO1 = E_INT_IRQ_0xA0_START+7, //A1 ++ E_INT_IRQ_EXT_GPIO2 = E_INT_IRQ_0xA0_START+8, //A1 ++ E_INT_IRQ_EXT_GPIO3 = E_INT_IRQ_0xA0_START+9, //A1 ++ E_INT_IRQ_EXT_GPIO4 = E_INT_IRQ_0xA0_START+10, //A1 ++ E_INT_IRQ_EXT_GPIO5 = E_INT_IRQ_0xA0_START+11, //A1 ++ E_INT_IRQ_EXT_GPIO6 = E_INT_IRQ_0xA0_START+12, //A1 ++ E_INT_IRQ_EXT_GPIO7 = E_INT_IRQ_0xA0_START+13, //A1 ++ E_INT_IRQ_MIIC_DMA_INT2 = E_INT_IRQ_0xA0_START+14, //A5 ++ E_INT_IRQ_MIIC_INT2 = E_INT_IRQ_0xA0_START+15, //A5 ++ E_INT_IRQ_0xA0_END = 0xAF, ++ ++ E_INT_IRQ_0xB0_START = 0xB0, ++ E_INT_IRQ_MIIC_DMA_INT1 = E_INT_IRQ_0xB0_START+0, //A5 ++ E_INT_IRQ_MIIC_INT1 = E_INT_IRQ_0xB0_START+1, //A5 ++ E_INT_IRQ_MIIC_DMA_INT0 = E_INT_IRQ_0xB0_START+2, //A5 ++ E_INT_IRQ_MIIC_INT0 = E_INT_IRQ_0xB0_START+3, //A5 ++ //Not Used = E_INT_IRQ_0xB0_START+4, ++ //Not Used = E_INT_IRQ_0xB0_START+5, ++ //Not Used = E_INT_IRQ_0xB0_START+6, ++ //Not Used = E_INT_IRQ_0xB0_START+7, ++ //Not Used = E_INT_IRQ_0xB0_START+8, ++ //Not Used = E_INT_IRQ_0xB0_START+9, ++ //Not Used = E_INT_IRQ_0xB0_START+10, ++ //Not Used = E_INT_IRQ_0xB0_START+11, ++ //Not Used = E_INT_IRQ_0xB0_START+12, ++ //Not Used = E_INT_IRQ_0xB0_START+13, ++ //Not Used = E_INT_IRQ_0xB0_START+14, ++ //Not Used = E_INT_IRQ_0xB0_START+15, ++ E_INT_IRQ_0xB0_END = 0xBF, ++ ++ ++ // Add FIQ from 0xC0 ~ 0xFD, ++ // if FIQ enum from 0x20 ~ 0x4F, and 0x60 ~ 0x7F is occupied ++ E_INT_FIQ_0xC0_START = 0xC0, ++ E_INT_FIQ_DMARD = E_INT_FIQ_0xC0_START+0, //U3 ++ E_INT_FIQ_AU_DMA_BUF_INT = E_INT_FIQ_0xC0_START+1, //T3 ++ E_INT_FIQ_8051_TO_MIPS_VPE1 = E_INT_FIQ_0xC0_START+2, //T3 ++ E_INT_FIQ_DVI_DET = E_INT_FIQ_0xC0_START+3, //M10 ++ E_INT_FIQ_PM_GPIO0 = E_INT_FIQ_0xC0_START+4, //M10 ++ E_INT_FIQ_PM_GPIO1 = E_INT_FIQ_0xC0_START+5, //M10 ++ E_INT_FIQ_PM_GPIO2 = E_INT_FIQ_0xC0_START+6, //M10 ++ E_INT_FIQ_PM_GPIO3 = E_INT_FIQ_0xC0_START+7, //M10 ++ E_INT_FIQ_PM_XIU_TIMEOUT = E_INT_FIQ_0xC0_START+8, //M10 ++ E_INT_FIQ_PWM_RP_RP_L = E_INT_FIQ_0xC0_START+9, //M10 ++ E_INT_FIQ_PWM_RP_FP_L = E_INT_FIQ_0xC0_START+10, //M10 ++ E_INT_FIQ_PWM_RP_RP_R = E_INT_FIQ_0xC0_START+11, //M10 ++ E_INT_FIQ_PWM_RP_FP_R = E_INT_FIQ_0xC0_START+12, //M10 ++ E_INT_FIQ_8051_TO_MIPS_VPE0 = E_INT_FIQ_0xC0_START+13, //A5 ++ E_INT_FIQ_FRC_R2_TO_MIPS = E_INT_FIQ_0xC0_START+14, ++ E_INT_FIQ_VP6 = E_INT_FIQ_0xC0_START+15, //A3 ++ E_INT_FIQ_0xC0_END = 0xCF, ++ ++ E_INT_FIQ_0xD0_START = 0xD0, ++ E_INT_FIQ_STRETCH = E_INT_FIQ_0xD0_START+0, ++ E_INT_FIQ_GPIO0 = E_INT_FIQ_0xD0_START+1, //T12 ++ E_INT_FIQ_GPIO1 = E_INT_FIQ_0xD0_START+2, //T12 ++ E_INT_FIQ_GPIO2 = E_INT_FIQ_0xD0_START+3, //T12 ++ E_INT_FIQ_GPIO3 = E_INT_FIQ_0xD0_START+4, //T12 ++ E_INT_FIQ_GPIO4 = E_INT_FIQ_0xD0_START+5, //T12 ++ E_INT_FIQ_GPIO5 = E_INT_FIQ_0xD0_START+6, //T12 ++ E_INT_FIQ_GPIO6 = E_INT_FIQ_0xD0_START+7, //T12 ++ E_INT_FIQ_GPIO7 = E_INT_FIQ_0xD0_START+8, //T12 ++ //Not Used = E_INT_FIQ_0xD0_START+9, ++ //Not Used = E_INT_FIQ_0xD0_START+10, ++ //Not Used = E_INT_FIQ_0xD0_START+11, ++ //Not Used = E_INT_FIQ_0xD0_START+12, ++ //Not Used = E_INT_FIQ_0xD0_START+13, ++ //Not Used = E_INT_FIQ_0xD0_START+14, ++ //Not Used = E_INT_FIQ_0xD0_START+15, ++ E_INT_FIQ_0xD0_END = 0xDF, ++ ++ E_INT_FIQ_0xE0_START = 0xE0, ++ E_INT_FIQ_LDM_DMA0 = E_INT_FIQ_0xE0_START+0, //A1 ++ E_INT_FIQ_LDM_DMA1 = E_INT_FIQ_0xE0_START+1, //A1 ++ E_INT_IRQ_SDIO = E_INT_FIQ_0xE0_START+2, //K2 ++ E_INT_IRQ_UHC3 = E_INT_FIQ_0xE0_START+3, //K2 ++ E_INT_IRQ_USB3 = E_INT_FIQ_0xE0_START+4, //K2 ++ //Not Used = E_INT_FIQ_0xE0_START+2, ++ //Not Used = E_INT_FIQ_0xE0_START+3, ++ //Not Used = E_INT_FIQ_0xE0_START+4, ++ //Not Used = E_INT_FIQ_0xE0_START+5, ++ //Not Used = E_INT_FIQ_0xE0_START+6, ++ //Not Used = E_INT_FIQ_0xE0_START+7, ++ //Not Used = E_INT_FIQ_0xE0_START+8, ++ //Not Used = E_INT_FIQ_0xE0_START+9, ++ //Not Used = E_INT_FIQ_0xE0_START+10, ++ //Not Used = E_INT_FIQ_0xE0_START+11, ++ //Not Used = E_INT_FIQ_0xE0_START+12, ++ //Not Used = E_INT_FIQ_0xE0_START+13, ++ //Not Used = E_INT_FIQ_0xE0_START+14, ++ //Not Used = E_INT_FIQ_0xE0_START+15, ++ E_INT_FIQ_0xE0_END = 0xEF, ++ ++ E_INT_FIQ_0xF0_START = 0xF0, ++ E_INT_FIQ_DEC_DSP2R2M = E_INT_FIQ_0xF0_START + 0, ++ E_INT_FIQ_AEON_TO_R2M = E_INT_FIQ_0xF0_START + 1, ++ E_INT_FIQ_R2M_TO_AEON = E_INT_FIQ_0xF0_START + 2, ++ E_INT_FIQ_R2M_TO_8051 = E_INT_FIQ_0xF0_START + 3, ++ E_INT_IRQ_VIVALDI_DMA_INTR2 = E_INT_FIQ_0xF0_START + 4, ++ E_INT_IRQ_VIVALDI_DMA_INTR1 = E_INT_FIQ_0xF0_START + 5, ++ E_INT_IRQ_AFEC_INT = E_INT_FIQ_0xF0_START + 6, ++ E_INT_IRQ_FRM_PM = E_INT_FIQ_0xF0_START + 11, ++ E_INT_FIQ_FRM_PM = E_INT_FIQ_0xF0_START + 12, ++ //Not Used = E_INT_FIQ_0xF0_START+0, ++ //Not Used = E_INT_FIQ_0xF0_START+1, ++ //Not Used = E_INT_FIQ_0xF0_START+2, ++ //Not Used = E_INT_FIQ_0xF0_START+3, ++ //Not Used = E_INT_FIQ_0xF0_START+4, ++ //Not Used = E_INT_FIQ_0xF0_START+5, ++ //Not Used = E_INT_FIQ_0xF0_START+6, ++ //Not Used = E_INT_FIQ_0xF0_START+7, ++ //Not Used = E_INT_FIQ_0xF0_START+8, ++ //Not Used = E_INT_FIQ_0xF0_START+9, ++ //Not Used = E_INT_FIQ_0xF0_START+10, ++ //Not Used = E_INT_FIQ_0xF0_START+11, ++ //Not Used = E_INT_FIQ_0xF0_START+12, ++ //Not Used = E_INT_FIQ_0xF0_START+13, ++ E_INT_IRQ_FIQ_NONE = E_INT_FIQ_0xF0_START+14, ++ E_INT_IRQ_FIQ_ALL = E_INT_FIQ_0xF0_START+15, ++ E_INT_FIQ_0xF0_END = 0xFF, ++ ++} InterruptNum; ++ ++ ++typedef enum ++{ ++ // IRQ ++ E_FRCINT_IRQ_0x00_START = 0x00, ++ E_FRCINT_IRQ_0x00_END = 0x0F, ++ ++ E_FRCINT_IRQ_0x10_START = 0x10, ++ E_FRCINT_IRQ_FRC_XIU_TIMEOUT = E_FRCINT_IRQ_0x10_START+5, ++ E_FRCINT_IRQ_PWM_RP_L = E_FRCINT_IRQ_0x10_START+6, ++ E_FRCINT_IRQ_PWM_FP_L = E_FRCINT_IRQ_0x10_START+7, ++ E_FRCINT_IRQ_PWM_RP_R = E_FRCINT_IRQ_0x10_START+8, ++ E_FRCINT_IRQ_PWM_FP_R = E_FRCINT_IRQ_0x10_START+9, ++ E_FRCINT_IRQ_SC = E_FRCINT_IRQ_0x10_START+10, ++ E_FRCINT_IRQ_D2B = E_FRCINT_IRQ_0x10_START+11, ++ E_FRCINT_IRQ_MSPI1 = E_FRCINT_IRQ_0x10_START+14, ++ E_FRCINT_IRQ_MSPI0 = E_FRCINT_IRQ_0x10_START+15, ++ E_FRCINT_IRQ_0x10_END = 0x1F, ++ ++ // FIQ ++ E_FRCINT_FIQ_0x20_START = 0x20, ++ E_FRCINT_FIQ_MIPS_TO_FRCR2 = E_FRCINT_FIQ_0x20_START+0, ++ E_FRCINT_FIQ_FRCR2_TO_MIPS = E_FRCINT_FIQ_0x20_START+4, ++ E_FRCINT_FIQ_0x20_END = 0x2F, ++ ++ E_FRCINT_FIQ_0x30_START = 0x30, ++ E_FRCINT_FIQ_PWM_RP_L = E_FRCINT_FIQ_0x30_START+6, ++ E_FRCINT_FIQ_PWM_FP_L = E_FRCINT_FIQ_0x30_START+7, ++ E_FRCINT_FIQ_PWM_RP_R = E_FRCINT_FIQ_0x30_START+8, ++ E_FRCINT_FIQ_PWM_FP_R = E_FRCINT_FIQ_0x30_START+9, ++ E_FRCINT_FIQ_LDM_DMA_DONE1 = E_FRCINT_FIQ_0x30_START+12, ++ E_FRCINT_FIQ_LDM_DMA_DONE0 = E_FRCINT_FIQ_0x30_START+13, ++ E_FRCINT_FIQ_SC = E_FRCINT_FIQ_0x30_START+14, ++ E_FRCINT_FIQ_OP2_VS = E_FRCINT_FIQ_0x30_START+15, ++ E_FRCINT_FIQ_0x30_END = 0x3F, ++ ++ // END ++ E_FRCINT_FIQ_0xF0_START = 0xF0, ++ E_FRCINT_IRQ_FIQ_NONE = E_FRCINT_FIQ_0xF0_START+14, ++ E_FRCINT_IRQ_FIQ_ALL = E_FRCINT_FIQ_0xF0_START+15, ++ E_FRCINT_FIQ_0xF0_END = 0xFF, ++ ++} InterruptNum_Frc; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _MS_IRQ_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/include/MsTypes.h b/drivers/mstar/scl/infinity3/src/mxlib/include/MsTypes.h +new file mode 100644 +index 00000000..1dd8dbf9 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/include/MsTypes.h +@@ -0,0 +1,232 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsTypes.h ++/// @brief MStar General Data Types ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_TYPES_H_ ++#define _MS_TYPES_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// System Data Type ++//------------------------------------------------------------------------------------------------- ++/// data type unsigned char, data length 1 byte ++#define MS_U8 unsigned char // 1 byte ++/// data type unsigned short, data length 2 byte ++#define MS_U16 unsigned short // 2 bytes ++/// data type unsigned int, data length 4 byte ++#define MS_U32 unsigned long // 4 bytes ++/// data type unsigned int, data length 8 byte ++#define MS_U64 unsigned long long // 8 bytes ++/// data type signed char, data length 1 byte ++#define MS_S8 signed char // 1 byte ++/// data type signed short, data length 2 byte ++#define MS_S16 signed short // 2 bytes ++/// data type signed int, data length 4 byte ++#define MS_S32 signed long // 4 bytes ++/// data type signed int, data length 8 byte ++#define MS_S64 signed long long // 8 bytes ++/// data type float, data length 4 byte ++#define MS_FLOAT float // 4 bytes ++/// data type null pointer ++#ifdef NULL ++#undef NULL ++#endif ++#define NULL 0 ++ ++#define MS_BOOL unsigned char ++ ++/// data type hardware physical address ++#define MS_PHYADDR unsigned long // 32bit physical address ++ ++ ++ ++#if !defined(BIT0) && !defined(BIT1) ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Software Data Type ++//------------------------------------------------------------------------------------------------- ++ ++//[TODO] use MS_U8, ... instead ++// data type for 8051 code ++//typedef MS_U16 WORD; ++//typedef MS_U8 BYTE; ++ ++ ++#ifndef true ++/// definition for true ++#define true 1 ++/// definition for false ++#define false 0 ++#endif ++ ++ ++#if !defined(TRUE) && !defined(FALSE) ++/// definition for TRUE ++#define TRUE 1 ++/// definition for FALSE ++#define FALSE 0 ++#endif ++ ++ ++#if defined(ENABLE) && (ENABLE!=1) ++#warning ENALBE is not 1 ++#else ++#define ENABLE 1 ++#endif ++ ++#if defined(DISABLE) && (DISABLE!=0) ++#warning DISABLE is not 0 ++#else ++#define DISABLE 0 ++#endif ++ ++ ++///Define MS FB Format, to share with GE,GOP ++/// FIXME THE NAME NEED TO BE REFINED, AND MUST REMOVE UNNESSARY FMT ++typedef enum ++{ ++ /// color format I1 ++ E_MS_FMT_I1 = 0x0, ++ /// color format I2 ++ E_MS_FMT_I2 = 0x1, ++ /// color format I4 ++ E_MS_FMT_I4 = 0x2, ++ /// color format palette 256(I8) ++ E_MS_FMT_I8 = 0x4, ++ /// color format blinking display ++ E_MS_FMT_FaBaFgBg2266 = 0x6, ++ /// color format for blinking display format ++ E_MS_FMT_1ABFgBg12355 = 0x7, ++ /// color format RGB565 ++ E_MS_FMT_RGB565 = 0x8, ++ /// color format ARGB1555 ++ /// @note [URANUS] ARGB1555 is only RGB555 ++ E_MS_FMT_ARGB1555 = 0x9, ++ /// color format ARGB4444 ++ E_MS_FMT_ARGB4444 = 0xa, ++ /// color format ARGB1555 DST ++ E_MS_FMT_ARGB1555_DST = 0xc, ++ /// color format YUV422 ++ E_MS_FMT_YUV422 = 0xe, ++ /// color format ARGB8888 ++ E_MS_FMT_ARGB8888 = 0xf, ++ /// color format RGBA5551 ++ E_MS_FMT_RGBA5551 = 0x10, ++ /// color format RGBA4444 ++ E_MS_FMT_RGBA4444 = 0x11, ++ /// color format ABGR8888 ++ E_MS_FMT_ABGR8888 = 0x1f, ++ ++ E_MS_FMT_GENERIC = 0xFFFF, ++ ++} MS_ColorFormat; ++ ++ ++typedef union _MSIF_Version ++{ ++ struct _DDI ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 model; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 change[8]; ++ MS_U8 os; ++ } MS_DDI; ++ struct _MW ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U16 customer; ++ MS_U16 mod; ++ MS_U16 chip; ++ MS_U8 cpu; ++ MS_U8 name[4]; ++ MS_U8 version[2]; ++ MS_U8 build[2]; ++ MS_U8 changelist[8]; ++ MS_U8 os; ++ } MW; ++ struct _APP ++ { ++ MS_U8 tag[4]; ++ MS_U8 type[2]; ++ MS_U8 id[4]; ++ MS_U8 quality; ++ MS_U8 version[4]; ++ MS_U8 time[6]; ++ MS_U8 changelist[8]; ++ MS_U8 reserve[3]; ++ } APP; ++} MSIF_Version; ++ ++typedef struct _MS_SW_VERSION_INFO ++{ ++ char UtopiaBspVersion[8]; //Utopia BSP Version ++ char MajorVersion[4]; //Major Version Number ++ char MinorVersion[4]; //Minor Version Number ++ char ChangeList_API[16]; //Sync Perforce Change List Number in API Folder ++ char ChangeList_DRV[16]; //Sync Perforce Change List Number in DRV Folder ++ char ChangeList_HAL[16]; //Sync Perforce Change List Number in HAL Folder ++ ++} MS_SW_VERSION_INFO; ++ ++#endif // _MS_TYPES_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/include/MsVersion.h b/drivers/mstar/scl/infinity3/src/mxlib/include/MsVersion.h +new file mode 100644 +index 00000000..1d2a7651 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/include/MsVersion.h +@@ -0,0 +1,118 @@ ++// ++//****************************************************************************** ++// MStar Software ++// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. ++// All software, firmware and related documentation herein ("MStar Software") are ++// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by ++// law, including, but not limited to, copyright law and international treaties. ++// Any use, modification, reproduction, retransmission, or republication of all ++// or part of MStar Software is expressly prohibited, unless prior written ++// permission has been granted by MStar. ++// ++// By accessing, browsing and/or using MStar Software, you acknowledge that you ++// have read, understood, and agree, to be bound by below terms ("Terms") and to ++// comply with all applicable laws and regulations: ++// ++// 1. MStar shall retain any and all right, ownership and interest to MStar ++// Software and any modification/derivatives thereof. ++// No right, ownership, or interest to MStar Software and any ++// modification/derivatives thereof is transferred to you under Terms. ++// ++// 2. You understand that MStar Software might include, incorporate or be ++// supplied together with third party`s software and the use of MStar ++// Software may require additional licenses from third parties. ++// Therefore, you hereby agree it is your sole responsibility to separately ++// obtain any and all third party right and license necessary for your use of ++// such third party`s software. ++// ++// 3. MStar Software and any modification/derivatives thereof shall be deemed as ++// MStar`s confidential information and you agree to keep MStar`s ++// confidential information in strictest confidence and not disclose to any ++// third party. ++// ++// 4. MStar Software is provided on an "AS IS" basis without warranties of any ++// kind. Any warranties are hereby expressly disclaimed by MStar, including ++// without limitation, any warranties of merchantability, non-infringement of ++// intellectual property rights, fitness for a particular purpose, error free ++// and in conformity with any international standard. You agree to waive any ++// claim against MStar for any loss, damage, cost or expense that you may ++// incur related to your use of MStar Software. ++// In no event shall MStar be liable for any direct, indirect, incidental or ++// consequential damages, including without limitation, lost of profit or ++// revenues, lost or damage of data, and unauthorized system use. ++// You agree that this Section 4 shall still apply without being affected ++// even if MStar Software has been modified by MStar in accordance with your ++// request or instruction for your use, except otherwise agreed by both ++// parties in writing. ++// ++// 5. If requested, MStar may from time to time provide technical supports or ++// services in relation with MStar Software to you for your use of ++// MStar Software in conjunction with your or your customer`s product ++// ("Services"). ++// You understand and agree that, except otherwise agreed by both parties in ++// writing, Services are provided on an "AS IS" basis and the warranty ++// disclaimer set forth in Section 4 above shall apply. ++// ++// 6. Nothing contained herein shall be construed as by implication, estoppels ++// or otherwise: ++// (a) conferring any license or right to use MStar name, trademark, service ++// mark, symbol or any other identification; ++// (b) obligating MStar or any of its affiliates to furnish any person, ++// including without limitation, you and your customers, any assistance ++// of any kind whatsoever, or any information; or ++// (c) conferring any license or right under any intellectual property right. ++// ++// 7. These terms shall be governed by and construed in accordance with the laws ++// of Taiwan, R.O.C., excluding its conflict of law rules. ++// Any and all dispute arising out hereof or related hereto shall be finally ++// settled by arbitration referred to the Chinese Arbitration Association, ++// Taipei in accordance with the ROC Arbitration Law and the Arbitration ++// Rules of the Association by three (3) arbitrators appointed in accordance ++// with the said Rules. ++// The place of arbitration shall be in Taipei, Taiwan and the language shall ++// be English. ++// The arbitration award shall be final and binding to both parties. ++// ++//****************************************************************************** ++// ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file MsVersion.h ++/// @brief MStar DDI Version Def ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _MS_VERSION_H_ ++#define _MS_VERSION_H_ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Version String Definition ++//------------------------------------------------------------------------------------------------- ++#define MSIF_TAG {'M','S','I','F'} // MSIF ++#define MSIF_CLASS {'0','0'} // DRV/API (DDI) ++#define MSIF_CUS 0x0000 // MStar Common library ++#define MSIF_MOD 0x0000 // MStar Common library ++#define MSIF_CHIP 0x000F ++#define MSIF_CPU '1' ++#define MSIF_OS '2' ++ ++ ++#endif // _MS_VERSION_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/msos/MsOS.c b/drivers/mstar/scl/infinity3/src/mxlib/msos/MsOS.c +new file mode 100644 +index 00000000..90b9c08b +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/msos/MsOS.c +@@ -0,0 +1,1917 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2007 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (?œMStar Confidential Information?? by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++/// ++ ++#define MS_OS_C ++ ++/******************************************************************************/ ++/* Header Files */ ++/* ****************************************************************************/ ++#ifdef MSOS_TYPE_LINUX_KERNEL ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* seems do not need this */ ++#include ++#include ++#include ++#endif ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "MsIRQ.h" ++#include "MsOS.h" ++#include "halCHIP.h" ++#include "mdrv_scl_dbg.h" ++#include "mdrv_vip_st.h" ++#include "mdrv_vip.h" ++ ++/********************************************************************************/ ++/* Macro */ ++/********************************************************************************/ ++#define MSOS_MUTEX_USE_SEM ++ ++#define MSOS_ID_PREFIX 0x76540000 ++#define MSOS_ID_PREFIX_MASK 0xFFFF0000 ++#define MSOS_ID_MASK 0x0000FFFF //~MSOS_ID_PREFIX_MASK ++ ++#define HAS_FLAG(flag, bit) ((flag) & (bit)) ++#define SET_FLAG(flag, bit) ((flag)|= (bit)) ++#define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) ++ ++ ++#ifndef MIN ++#define MIN(a, b) (((a) < (b)) ? (a) : (b)) ++#endif // #ifndef MIN ++ ++#ifndef MAX ++#define MAX(a, b) (((a) > (b)) ? (a) : (b)) ++#endif ++ ++#ifdef MSOS_MEMPOOL_MAX ++#undef MSOS_MEMPOOL_MAX ++#define MSOS_MEMPOOL_MAX 2 ++#endif // #ifdef MSOS_MEMPOOL_MAX ++ ++ ++ ++/********************************************************************************/ ++/* Constant */ ++/********************************************************************************/ ++ ++ ++/******************************************************************************/ ++/* Enum */ ++/******************************************************************************/ ++ ++ ++/******************************************************************************/ ++/* Global Variables */ ++/******************************************************************************/ ++// ++// Mutex ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++#ifdef MSOS_MUTEX_USE_SEM ++ struct semaphore stMutex; ++#else ++ spinlock_t stMutex; ++#endif ++ MS_U8 u8Name[MAX_MUTEX_NAME_LENGTH]; ++} MsOS_Mutex_Info; ++typedef struct ++{ ++ MS_BOOL bUsed; ++ spinlock_t stMutex; ++ MS_U8 u8Name[MAX_MUTEX_NAME_LENGTH]; ++} MsOS_Spinlock_Info; ++ ++static MsOS_Mutex_Info _MsOS_Mutex_Info[MSOS_MUTEX_MAX]; ++static MsOS_Spinlock_Info _MsOS_Spinlock_Info[MSOS_SPINLOCK_MAX]; ++unsigned char gu8SclFrameDelay; ++unsigned char gbDigitalZoomDropMode = 0; ++E_VIPSetRule_TYPE genVIPSetRule; ++#define SCL_IRQID_Default 0x54 ++#define CMDQ_IRQID_Default 0x51 ++MS_BOOL gbInit = FALSE; ++ ++static MS_U32 gSCLIRQID[E_SCLIRQ_MAX] = {SCL_IRQID_Default,(SCL_IRQID_Default+38),(SCL_IRQID_Default+39)}; //INT_IRQ_AU_SYSTEM; ++static MS_U32 gCMDQIRQID[E_CMDQIRQ_MAX] = {CMDQ_IRQID_Default,(CMDQ_IRQID_Default+35),(CMDQ_IRQID_Default+36)}; //INT_IRQ_AU_SYSTEM; ++ ++static DEFINE_SPINLOCK(_MsOS_Mutex_Mutex); ++#define MUTEX_MUTEX_LOCK() spin_lock(&_MsOS_Mutex_Mutex) ++#define MUTEX_MUTEX_UNLOCK() spin_unlock(&_MsOS_Mutex_Mutex) ++ ++// ++// Task Management ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++ struct task_struct* pstThreadInfo; ++} MsOS_Task_Info; ++typedef struct ++{ ++ MS_BOOL bUsed; ++ MSOS_ST_WORKQUEUE* pstWorkQueueInfo; ++} MsOS_WorkQueue_Info; ++typedef struct ++{ ++ MS_BOOL bUsed; ++ MSOS_ST_WORK stWorkEventInfo; ++} MsOS_WorkEvent_Info; ++typedef struct ++{ ++ MS_BOOL bUsed; ++ MSOS_ST_TASKLET stTaskletInfo; ++} MsOS_Tasklet_Info; ++ ++static MsOS_Task_Info _MsOS_Task_Info[MSOS_TASK_MAX]; ++static MsOS_WorkQueue_Info _MsOS_WorkQueue_Info[MSOS_WORKQUEUE_MAX]; ++static MsOS_WorkEvent_Info _MsOS_WorkEvent_Info[MSOS_WORK_MAX]; ++static MsOS_Tasklet_Info _MsOS_Tasklet_Info[MSOS_TASKLET_MAX]; ++ ++#ifdef MSOS_MUTEX_USE_SEM ++struct semaphore _MsOS_Task_Mutex; ++#define MUTEX_TASK_LOCK() down(&_MsOS_Task_Mutex) ++#define MUTEX_TASK_UNLOCK() up(&_MsOS_Task_Mutex) ++#else ++static DEFINE_SPINLOCK(_MsOS_Task_Mutex); ++#define MUTEX_TASK_LOCK() spin_lock(&_MsOS_Task_Mutex) ++#define MUTEX_TASK_UNLOCK() spin_unlock(&_MsOS_Task_Mutex) ++#endif ++ ++// ++// Event Group ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++ MS_U32 u32EventGroup; ++ spinlock_t stMutexEvent; ++ wait_queue_head_t stSemaphore; ++ // pthread_cond_t stSemaphore; // ????????????? ++} MsOS_EventGroup_Info; ++typedef struct ++{ ++ MS_BOOL bUsed; ++ MS_U32 u32EventGroup; ++ MS_U8 u8Wpoint; ++ MS_U8 u8Rpoint; ++} MsOS_RingEventGroup_Info; ++ ++static MsOS_EventGroup_Info _MsOS_EventGroup_Info[MSOS_EVENTGROUP_MAX]; ++#if USE_RTK ++static MsOS_RingEventGroup_Info _MsOS_RingEventGroup_Info[MSOS_EVENTGROUP_MAX]; ++#endif ++static DEFINE_SPINLOCK(_MsOS_EventGroup_Mutex); ++#define EVENT_MUTEX_LOCK() spin_lock(&_MsOS_EventGroup_Mutex) ++#define EVENT_MUTEX_UNLOCK() spin_unlock(&_MsOS_EventGroup_Mutex) ++ ++ ++// Timer ++// ++typedef struct ++{ ++ MS_BOOL bUsed; ++ TimerCb pTimerCb; ++ struct timer_list timer; ++ int period; ++ int first; ++} MsOS_Timer_Info; ++static MsOS_Timer_Info _MsOS_Timer_Info[MSOS_TIMER_MAX]; ++static DEFINE_SPINLOCK(_MsOS_Timer_Mutex); ++#define TIMER_MUTEX_LOCK() spin_lock(&_MsOS_Timer_Mutex) ++#define TIMER_MUTEX_UNLOCK() spin_unlock(&_MsOS_Timer_Mutex) ++ ++/******************************************************************************/ ++/* Local Variables */ ++/******************************************************************************/ ++ ++/******************************************************************************/ ++/* P r i v a t e F u n c t i o n s */ ++/******************************************************************************/ ++void MsOS_SetPollWait(void *filp, void *pWaitQueueHead, void *pstPollQueue) ++{ ++ poll_wait((struct file *)filp, (wait_queue_head_t *)pWaitQueueHead, (struct poll_table_struct *)pstPollQueue); ++} ++MS_U32 MsOS_GetSystemTime (void) ++{ ++ struct timespec ts; ++ ++ getnstimeofday(&ts); ++ return ts.tv_sec* 1000+ ts.tv_nsec/1000000; ++} ++MS_U64 MsOS_GetSystemTimeStamp (void) ++{ ++ struct timespec tv; ++ MS_U64 u64TimeStamp; ++ do_posix_clock_monotonic_gettime(&tv); ++ u64TimeStamp =(MS_U64)tv.tv_sec* 1000000ULL+ (MS_U64)(tv.tv_nsec/1000LL); ++ return u64TimeStamp; ++} ++ ++MS_U32 MsOS_Timer_DiffTimeFromNow(MS_U32 u32TaskTimer) //unit = ms ++{ ++ return (MsOS_GetSystemTime() - u32TaskTimer); ++} ++ ++void MsOS_DelayTask (MS_U32 u32Ms) ++{ ++ //sleep in spinlock will cause deadlock ++#ifdef MSOS_MUTEX_USE_SEM ++ msleep_interruptible((unsigned int)u32Ms); ++#else ++ mdelay(u32Ms); ++#endif ++} ++ ++ ++void MsOS_DelayTaskUs (MS_U32 u32Us) ++{ ++ //sleep in spinlock will cause deadlock ++ udelay(u32Us); ++} ++ ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// ++// Interrupt management ++// ++//------------------------------------------------------------------------------------------------- ++/// Attach the interrupt callback function to interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @param pIntCb \b IN: Interrupt callback function ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_AttachInterrupt (InterruptNum eIntNum, InterruptCb pIntCb,unsigned long flags,const char *name) ++{ ++ int i; ++ i = request_irq(eIntNum, (irq_handler_t)pIntCb, flags, name, NULL); ++ ++ return i; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Detach the interrupt callback function from interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DetachInterrupt (InterruptNum eIntNum) ++{ ++ // PTH_RET_CHK(pthread_mutex_lock(&_ISR_Mutex)); ++ //HAL_IRQ_Detech((int)eIntNum); TODo!! ++ // PTH_RET_CHK(pthread_mutex_unlock(&_ISR_Mutex)); ++ free_irq(eIntNum, NULL); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Enable (unmask) the interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_EnableInterrupt (InterruptNum eIntNum) ++{ ++ enable_irq((int)eIntNum); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Disable (mask) the interrupt # ++/// @param eIntNum \b IN: Interrupt number in enumerator InterruptNum ++/// @return TRUE : succeed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DisableInterrupt (InterruptNum eIntNum) ++{ ++ disable_irq((int)eIntNum); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Disable all interrupts (including timer interrupt), the scheduler is disabled. ++/// @return Interrupt register value before all interrupts disable ++//------------------------------------------------------------------------------------------------- ++MS_U32 MsOS_DisableAllInterrupts(void) ++{ ++#if 0 ++ return CHIP_DisableAllInterrupt() ; ++#else ++ return 0; ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Restore the interrupts from last MsOS_DisableAllInterrupts. ++/// @param u32OldInterrupts \b IN: Interrupt register value from @ref MsOS_DisableAllInterrupts ++/// @return TRUE : succeed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_RestoreAllInterrupts(MS_U32 u32OldInterrupts) ++{ ++ return TRUE; ++} ++//------------------------------------------------------------------------------------------------- ++/// Enable all CPU interrupts. ++/// @return TRUE : succeed ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_EnableAllInterrupts(void) ++{ ++#if 0 ++ return CHIP_EnableAllInterrupt() ; ++#else ++ return TRUE; ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// In Interuupt Context or not ++/// @return TRUE : Yes ++/// @return FALSE : No ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_In_Interrupt (void) ++{ ++#if 0 ++ return CHIP_InISRContext(); ++#else ++ return FALSE; ++#endif ++} ++ ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++ ++// ++// Mutex ++// ++//------------------------------------------------------------------------------------------------- ++/// Create a mutex in the unlocked state ++/// @param eAttribute \b IN: E_MSOS_FIFO: suspended in FIFO order ++/// @param pMutexName \b IN: mutex name ++/// @param u32Flag \b IN: process data shared flag ++/// @return >=0 : assigned mutex Id ++/// @return <0 : fail ++/// @note A mutex has the concept of an owner, whereas a semaphore does not. ++/// A mutex provides priority inheritance protocol against proiorty inversion, whereas a binary semaphore does not. ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_CreateMutex ( MsOSAttribute eAttribute, char *pMutexName1, MS_U32 u32Flag) ++{ ++ MS_S32 s32Id, s32LstUnused = MSOS_MUTEX_MAX; ++ MS_U8 pMutexName[MAX_MUTEX_NAME_LENGTH]; ++ MS_U32 u32MaxLen; ++ ++ if (NULL == pMutexName1) ++ { ++ return -1; ++ } ++ if (strlen(pMutexName1) >= (MAX_MUTEX_NAME_LENGTH-1)) ++ { ++ printk("%s: Warning strlen(%s) is longer than MAX_MUTEX_NAME_LENGTH(%d). Oversize char will be discard.\n", ++ __FUNCTION__,pMutexName1,MAX_MUTEX_NAME_LENGTH); ++ } ++ if (0 == (u32MaxLen = MIN(strlen(pMutexName1), (MAX_MUTEX_NAME_LENGTH-1)))) ++ { ++ return -1; ++ } ++ strncpy((char*)pMutexName, (const char*)pMutexName1, u32MaxLen); ++ pMutexName[u32MaxLen] = '\0'; ++ ++ MUTEX_MUTEX_LOCK(); ++ for(s32Id=0;s32Ids32LstUnused)) ++ { ++ _MsOS_Mutex_Info[s32LstUnused].bUsed = TRUE; ++ strcpy((char*)_MsOS_Mutex_Info[s32LstUnused].u8Name, (const char*)pMutexName); ++#ifdef MSOS_MUTEX_USE_SEM ++ sema_init(&_MsOS_Mutex_Info[s32LstUnused].stMutex, 1); ++#else ++ spin_lock_init(&_MsOS_Mutex_Info[s32LstUnused].stMutex); ++#endif ++ s32Id = s32LstUnused; ++ } ++ MUTEX_MUTEX_UNLOCK(); ++ ++ if(MSOS_MUTEX_MAX <= s32Id) ++ { ++ return -1; ++ } ++ ++ s32Id |= MSOS_ID_PREFIX; ++ ++ return s32Id; ++} ++MS_S32 MsOS_CreateSpinlock ( MsOSAttribute eAttribute, char *pMutexName1, MS_U32 u32Flag) ++{ ++ MS_S32 s32Id, s32LstUnused = MSOS_SPINLOCK_MAX; ++ MS_U8 pMutexName[MAX_MUTEX_NAME_LENGTH]; ++ MS_U32 u32MaxLen; ++ if (NULL == pMutexName1) ++ { ++ return -1; ++ } ++ if (strlen(pMutexName1) >= (MAX_MUTEX_NAME_LENGTH-1)) ++ { ++ printk("%s: Warning strlen(%s) is longer than MAX_MUTEX_NAME_LENGTH(%d). Oversize char will be discard.\n", ++ __FUNCTION__,pMutexName1,MAX_MUTEX_NAME_LENGTH); ++ } ++ if (0 == (u32MaxLen = MIN(strlen(pMutexName1), (MAX_MUTEX_NAME_LENGTH-1)))) ++ { ++ return -1; ++ } ++ strncpy((char*)pMutexName, (const char*)pMutexName1, u32MaxLen); ++ pMutexName[u32MaxLen] = '\0'; ++ ++ MUTEX_MUTEX_LOCK(); ++ for(s32Id=0;s32Ids32LstUnused)) ++ { ++ _MsOS_Spinlock_Info[s32LstUnused].bUsed = TRUE; ++ strcpy((char*)_MsOS_Spinlock_Info[s32LstUnused].u8Name, (const char*)pMutexName); ++ spin_lock_init(&_MsOS_Spinlock_Info[s32LstUnused].stMutex); ++ s32Id = s32LstUnused; ++ } ++ MUTEX_MUTEX_UNLOCK(); ++ ++ if(MSOS_SPINLOCK_MAX <= s32Id) ++ { ++ return -1; ++ } ++ ++ s32Id |= MSOS_ID_PREFIX; ++ ++ return s32Id; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete the specified mutex ++/// @param s32MutexId \b IN: mutex ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++/// @note It is important that the mutex be in the unlocked state when it is ++/// destroyed, or else the behavior is undefined. ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteMutex (MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ MUTEX_MUTEX_LOCK(); ++ ++ MS_ASSERT(_MsOS_Mutex_Info[s32MutexId].bUsed); ++ _MsOS_Mutex_Info[s32MutexId].bUsed = FALSE; ++ _MsOS_Mutex_Info[s32MutexId].u8Name[0] = '\0'; ++ ++ MUTEX_MUTEX_UNLOCK(); ++ return TRUE; ++} ++MS_BOOL MsOS_DeleteSpinlock (MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ MUTEX_MUTEX_LOCK(); ++ ++ MS_ASSERT(_MsOS_Spinlock_Info[s32MutexId].bUsed); ++ _MsOS_Spinlock_Info[s32MutexId].bUsed = FALSE; ++ _MsOS_Spinlock_Info[s32MutexId].u8Name[0] = '\0'; ++ ++ MUTEX_MUTEX_UNLOCK(); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Attempt to lock a mutex ++/// @param s32MutexId \b IN: mutex ID ++/// @param u32WaitMs \b IN: 0 ~ MSOS_WAIT_FOREVER: suspend time (ms) if the mutex is locked ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++// @FIXME: don't support time-out at this stage ++MS_BOOL MsOS_ObtainMutex_IRQ(MS_S32 s32MutexId) ++{ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ spin_lock_irq(&(_MsOS_Spinlock_Info[s32MutexId].stMutex)); ++ return TRUE; ++} ++MS_BOOL MsOS_ObtainMutex (MS_S32 s32MutexId, MS_U32 u32WaitMs) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ if ( (s32MutexId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32MutexId &= MSOS_ID_MASK; ++ } ++ ++ if (u32WaitMs==MSOS_WAIT_FOREVER) //blocking wait ++ { ++#ifdef MSOS_MUTEX_USE_SEM ++ down(&(_MsOS_Mutex_Info[s32MutexId].stMutex)); ++#else ++ spin_lock(&(_MsOS_Mutex_Info[s32MutexId].stMutex)); ++#endif ++ bRet = TRUE; ++ } ++ else if (u32WaitMs==0) //non-blocking ++ { ++#ifdef MSOS_MUTEX_USE_SEM ++ if (!down_trylock(&_MsOS_Mutex_Info[s32MutexId].stMutex)) ++#else ++ if (spin_trylock(&_MsOS_Mutex_Info[s32MutexId].stMutex)) ++#endif ++ { ++ bRet = TRUE; ++ } ++ } ++ else //blocking wait with timeout ++ { ++#ifndef MSOS_MUTEX_USE_SEM ++ MS_U32 u32CurTime = MsOS_GetSystemTime(); ++#endif ++ ++ while(1) ++ { ++#ifdef MSOS_MUTEX_USE_SEM ++ if (0 == down_timeout(&_MsOS_Mutex_Info[s32MutexId].stMutex, msecs_to_jiffies(u32WaitMs))) ++#else ++ if (spin_trylock(&_MsOS_Mutex_Info[s32MutexId].stMutex)) ++#endif ++ { ++ bRet = TRUE; ++ break; ++ } ++#ifdef MSOS_MUTEX_USE_SEM ++ else ++#else ++ else if((MsOS_GetSystemTime() - u32CurTime) > u32WaitMs) ++#endif ++ { ++ printf("Mutext TimeOut: ID:%x \n", (int)s32MutexId); ++ bRet = FALSE; ++ break; ++ } ++ ++ // msleep(5); ++ } ++ ++ } ++ return bRet; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Attempt to unlock a mutex ++/// @param s32MutexId \b IN: mutex ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++/// @note Only the owner thread of the mutex can unlock it. ++//------------------------------------------------------------------------------------------------- ++char * MsOS_CheckMutex(char *str,char *end) ++{ ++ MS_S32 s32MutexId; ++ for(s32MutexId=0;s32MutexId=0 : assigned Task ID ++/// @return < 0 : fail ++//------------------------------------------------------------------------------------------------- ++MSOS_ST_TASKSTRUCT MsOS_GetTaskinfo(MS_S32 s32Id) ++{ ++ MSOS_ST_TASKSTRUCT stTask; ++ stTask.pThread = _MsOS_Task_Info[(s32Id&0xFFFF)].pstThreadInfo; ++ return stTask; ++} ++void MsOS_SetUserNice(MSOS_ST_TASKSTRUCT *stTask, long nice) ++{ ++ set_user_nice(stTask->pThread,nice); ++} ++int MsOS_GetUserNice(MSOS_ST_TASKSTRUCT *stTask) ++{ ++ return (int)task_nice(stTask->pThread); ++} ++MS_BOOL MsOS_SleepTaskWork(MS_S32 s32TaskId) ++{ ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ set_current_state(TASK_INTERRUPTIBLE); ++ schedule(); ++ //schedule_timeout_interruptible(msecs_to_jiffies(10000)); ++ return 1; ++} ++MS_BOOL MsOS_SetTaskWork(MS_S32 s32TaskId) ++{ ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ wake_up_process(_MsOS_Task_Info[s32TaskId].pstThreadInfo); ++ return 1; ++} ++ ++MS_S32 MsOS_CreateTask (TaskEntry pTaskEntry, ++ MS_U32 u32TaskEntryData, ++ MS_BOOL bAutoStart, ++ const char *pTaskName) ++{ ++ // @FIXME: ++ // (1) eTaskPriority: Task priority is ignored here ++ // (2) pTaskName: is ignored here ++ // (3) Need mutex to protect critical section ++ ++ MS_S32 s32Id; ++ ++ MUTEX_TASK_LOCK(); ++ ++ for( s32Id=0; s32Id= MSOS_TASK_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_Task_Info[s32Id].bUsed = TRUE; ++ //_MsOS_Task_Info[s32Id].pstThreadInfo = kthread_create(((int)(void *)pTaskEntry), (void*)u32TaskEntryData, pTaskName); ++ _MsOS_Task_Info[s32Id].pstThreadInfo = kthread_create(pTaskEntry, (void*)u32TaskEntryData, pTaskName); ++ ++ MUTEX_TASK_UNLOCK(); ++ ++ if (bAutoStart) ++ { ++ wake_up_process(_MsOS_Task_Info[s32Id].pstThreadInfo); ++ } ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete a previously created task ++/// @param s32TaskId \b IN: task ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteTask (MS_S32 s32TaskId) ++{ ++#if 1 ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ ++ kthread_stop(_MsOS_Task_Info[s32TaskId].pstThreadInfo); ++ _MsOS_Task_Info[s32TaskId].bUsed = FALSE; ++#else ++ printk("[%s][%d] %s is not supported\n", __FUNCTION__, __LINE__, __FUNCTION__); ++#endif ++ return TRUE; ++} ++int MsOS_GetIrqIDSCL(E_SCLIRQ_TYPE enType) ++{ ++ return gSCLIRQID[enType]; ++} ++int MsOS_GetIrqIDCMDQ(E_CMDQIRQ_TYPE enType) ++{ ++ return gCMDQIRQID[enType]; ++} ++int MsOS_SetSclIrqIDFormSys(MSOS_ST_PLATFORMDEVICE *pdev,unsigned char u8idx,E_SCLIRQ_TYPE enType) ++{ ++ unsigned int SCL_IRQ_ID = 0; //INT_IRQ_AU_SYSTEM; ++ SCL_IRQ_ID = of_irq_to_resource(pdev->dev.of_node, u8idx, NULL); ++ if (!SCL_IRQ_ID) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[MSOS] Can't Get SCL_IRQ\n"); ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[MSOS] Get resource SCL_IRQ = 0x%x\n",SCL_IRQ_ID); ++ gSCLIRQID[enType] = SCL_IRQ_ID; ++ } ++ return 0; ++} ++int MsOS_SetCmdqIrqIDFormSys(MSOS_ST_PLATFORMDEVICE *pdev,unsigned char u8idx,E_CMDQIRQ_TYPE enType) ++{ ++ unsigned int CMDQ_IRQ_ID = 0; //INT_IRQ_AU_SYSTEM; ++ CMDQ_IRQ_ID = of_irq_to_resource(pdev->dev.of_node, u8idx, NULL); ++ if (!CMDQ_IRQ_ID) ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[MSOS] Can't Get CMDQ_IRQ\n"); ++ return -EINVAL; ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_MDRV_IO(), "[MSOS] Get resource CMDQ_IRQ = 0x%x\n",CMDQ_IRQ_ID); ++ gCMDQIRQID[enType] = CMDQ_IRQ_ID; ++ } ++ return 0; ++} ++ ++MS_BOOL MsOS_Init (void) ++{ ++ MS_U32 u32I; ++ if(gbInit) ++ { ++ return TRUE; ++ } ++ // ++ // Task Management ++ // ++#ifdef MSOS_MUTEX_USE_SEM ++ sema_init(&_MsOS_Task_Mutex, 1); ++#else ++ spin_lock_init(&_MsOS_Task_Mutex); ++#endif ++ for( u32I=0; u32I=0 : assigned Event Id ++/// @return <0 : fail ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_CreateEventGroup (char *pEventName) ++{ ++ MS_S32 s32Id; ++ EVENT_MUTEX_LOCK(); ++ for(s32Id=0; s32Id= MSOS_EVENTGROUP_MAX) ++ { ++ return -1; ++ } ++ spin_lock_init(&_MsOS_EventGroup_Info[s32Id].stMutexEvent); ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32Id].stMutexEvent); ++ _MsOS_EventGroup_Info[s32Id].u32EventGroup= 0; ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32Id].stMutexEvent); ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++#if USE_RTK ++MS_BOOL MsOS_CreateEventGroupRing (MS_U8 u8Id) ++{ ++ EVENT_MUTEX_LOCK(); ++ if(_MsOS_RingEventGroup_Info[u8Id].bUsed == TRUE) ++ { ++ return 0; ++ } ++ if(u8Id < MSOS_EVENTGROUP_MAX) ++ { ++ spin_lock(&_MsOS_EventGroup_Info[u8Id].stMutexEvent); ++ _MsOS_RingEventGroup_Info[u8Id].bUsed = TRUE; ++ _MsOS_RingEventGroup_Info[u8Id].u32EventGroup= 0; ++ _MsOS_RingEventGroup_Info[u8Id].u8Rpoint= 0; ++ _MsOS_RingEventGroup_Info[u8Id].u8Wpoint= 0; ++ spin_unlock(&_MsOS_EventGroup_Info[u8Id].stMutexEvent); ++ } ++ EVENT_MUTEX_UNLOCK(); ++ ++ if(u8Id >= MSOS_EVENTGROUP_MAX) ++ { ++ return 0; ++ } ++ u8Id |= MSOS_ID_PREFIX; ++ return 1; ++} ++#endif ++//------------------------------------------------------------------------------------------------- ++/// Delete the event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @return TRUE : succeed ++/// @return FALSE : fail, sb is waiting for the event flag ++/// @note event group that are being waited on must not be deleted ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteEventGroup (MS_S32 s32EventGroupId) ++{ ++ ++ // PTH_RET_CHK(pthread_mutex_destroy(&_MsOS_EventGroup_Info[s32EventGroupId].stMutex)); ++ EVENT_MUTEX_LOCK(); ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ init_waitqueue_head(&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++ _MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup= 0; ++ _MsOS_EventGroup_Info[s32EventGroupId].bUsed = FALSE; ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ EVENT_MUTEX_UNLOCK(); ++ return TRUE; ++} ++#if USE_RTK ++MS_BOOL MsOS_DeleteEventGroupRing (MS_S32 s32EventGroupId) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ EVENT_MUTEX_LOCK(); ++ MsOS_Memset(&_MsOS_RingEventGroup_Info[s32EventGroupId],0,sizeof(MsOS_RingEventGroup_Info)); ++ EVENT_MUTEX_UNLOCK(); ++ return TRUE; ++} ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++/// Set the event flag (bitwise OR w/ current value) in the specified event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @param u32EventFlag \b IN: event flag value ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++ ++MS_BOOL MsOS_SetEvent_IRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ SET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ wake_up(&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++ return TRUE; ++} ++MS_BOOL MsOS_SetEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ spin_lock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ SET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ wake_up(&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++ return TRUE; ++} ++#if USE_RTK ++MS_BOOL MsOS_SetEventRing (MS_S32 s32EventGroupId) ++{ ++ SET_FLAG(_MsOS_RingEventGroup_Info[s32EventGroupId].u32EventGroup, ++ (MS_U32)(0x1 << _MsOS_RingEventGroup_Info[s32EventGroupId].u8Wpoint)); ++ _MsOS_RingEventGroup_Info[s32EventGroupId].u8Wpoint++; ++ if(_MsOS_RingEventGroup_Info[s32EventGroupId].u8Wpoint>=32) ++ { ++ _MsOS_RingEventGroup_Info[s32EventGroupId].u8Wpoint = 0; ++ } ++ if(_MsOS_RingEventGroup_Info[s32EventGroupId].u8Wpoint == _MsOS_RingEventGroup_Info[s32EventGroupId].u8Rpoint) ++ { ++ SCL_ERR("SetEventRingBIT FULL W:%hhd ,R:%hhd\n",_MsOS_RingEventGroup_Info[s32EventGroupId].u8Wpoint, ++ _MsOS_RingEventGroup_Info[s32EventGroupId].u8Rpoint); ++ } ++ return TRUE; ++} ++MS_U32 MsOS_GetandClearEventRing(MS_U32 u32EventGroupId) ++{ ++ MS_U32 u32Event = 0; ++ MS_U8 u8Count = 0; ++ u32Event = HAS_FLAG(_MsOS_RingEventGroup_Info[u32EventGroupId].u32EventGroup, ++ (MS_U32)(0x1 << _MsOS_RingEventGroup_Info[u32EventGroupId].u8Rpoint)); ++ if(u32Event) ++ { ++ while(_MsOS_RingEventGroup_Info[u32EventGroupId].u8Rpoint != _MsOS_RingEventGroup_Info[u32EventGroupId].u8Wpoint) ++ { ++ RESET_FLAG(_MsOS_RingEventGroup_Info[u32EventGroupId].u32EventGroup, ++ (u32)(0x1 << _MsOS_RingEventGroup_Info[u32EventGroupId].u8Rpoint)); ++ _MsOS_RingEventGroup_Info[u32EventGroupId].u8Rpoint++; ++ if(_MsOS_RingEventGroup_Info[u32EventGroupId].u8Rpoint>=32) ++ { ++ _MsOS_RingEventGroup_Info[u32EventGroupId].u8Rpoint = 0; ++ } ++ u8Count++; ++ } ++ if(u8Count >1) ++ { ++ SCL_ERR("GetEvent Count:%hhd IST too late\n",u8Count); ++ } ++ return u8Count; ++ } ++ return 0; ++} ++#endif ++MS_U32 MsOS_GetEvent(MS_S32 s32EventGroupId) ++{ ++ MS_U32 u32Event; ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ u32Event = HAS_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, 0xFFFFFFFF); ++ return u32Event; ++} ++//------------------------------------------------------------------------------------------------- ++/// Clear the specified event flag (bitwise XOR operation) in the specified event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @param u32EventFlag \b IN: event flag value ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_ClearEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ spin_lock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ RESET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ return TRUE; ++} ++MS_BOOL MsOS_ClearEventIRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ RESET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32EventFlag); ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Wait for the specified event flag combination from the event group ++/// @param s32EventGroupId \b IN: event group ID ++/// @param u32WaitEventFlag \b IN: wait event flag value ++/// @param pu32RetrievedEventFlag \b OUT: retrieved event flag value ++/// @param eWaitMode \b IN: E_AND/E_OR/E_AND_CLEAR/E_OR_CLEAR ++/// @param u32WaitMs \b IN: 0 ~ MSOS_WAIT_FOREVER: suspend time (ms) if the event is not ready ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_WaitEvent (MS_S32 s32EventGroupId, ++ MS_U32 u32WaitEventFlag, ++ MS_U32 *pu32RetrievedEventFlag, ++ EventWaitMode eWaitMode, ++ MS_U32 u32WaitMs) ++{ ++ MS_BOOL bRet= FALSE; ++ MS_BOOL bAnd; ++ MS_BOOL bClear; ++ MS_BOOL bTimeout=0; ++ MS_U64 u64Time = 0; ++ MS_U64 u64DiffTime = 0; ++ *pu32RetrievedEventFlag = 0; ++ ++ if (!u32WaitEventFlag) ++ { ++ return FALSE; ++ } ++ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ ++ bClear= ((E_AND_CLEAR== eWaitMode) || (E_OR_CLEAR== eWaitMode))? TRUE: FALSE; ++ bAnd= ((E_AND== eWaitMode)|| (E_AND_CLEAR== eWaitMode))? TRUE: FALSE; ++ do{ ++/* ++ *pu32RetrievedEventFlag= HAS_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32WaitEventFlag); ++ if ((bAnd)? (*pu32RetrievedEventFlag== u32WaitEventFlag): (0!= *pu32RetrievedEventFlag)) ++ { ++ break; ++ } ++*/ ++ if (u32WaitMs== MSOS_WAIT_FOREVER) //blocking wait ++ { ++ if (bAnd) ++ { ++ if(((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) != u32WaitEventFlag)) ++ { ++ wait_event(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) == u32WaitEventFlag)); ++ } ++ else ++ { ++ bTimeout = 1; ++ } ++ } ++ else ++ { ++ if(((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) == 0)) ++ { ++ wait_event(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) != 0)); ++ } ++ else ++ { ++ bTimeout = 1; ++ } ++ } ++ } ++ else ++ { ++ u32WaitMs = msecs_to_jiffies(u32WaitMs); ++ u64Time = MsOS_GetSystemTimeStamp(); ++ if (bAnd) ++ { ++ if(((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) != u32WaitEventFlag)) ++ { ++ bTimeout = wait_event_timeout(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) == u32WaitEventFlag), ++ u32WaitMs); ++ } ++ else ++ { ++ bTimeout = 1; ++ } ++ } ++ else ++ { ++ if(((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) == 0)) ++ { ++ bTimeout = wait_event_timeout(_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore, ++ ((_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup & u32WaitEventFlag) != 0), ++ u32WaitMs); ++ } ++ else ++ { ++ bTimeout = 1; ++ } ++ } ++ u64DiffTime = MsOS_GetSystemTimeStamp() - u64Time; ++ if(!bTimeout) ++ SCL_DBGERR("[SCL_MSOS]wait timeout flag:%lx %llu\n",u32WaitEventFlag,u64DiffTime); ++ } ++ *pu32RetrievedEventFlag= HAS_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, u32WaitEventFlag); ++ } while (0); ++ bRet= (bAnd)? (*pu32RetrievedEventFlag== u32WaitEventFlag): (0!= *pu32RetrievedEventFlag); ++ if (bRet && bClear) ++ { ++ spin_lock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ RESET_FLAG(_MsOS_EventGroup_Info[s32EventGroupId].u32EventGroup, *pu32RetrievedEventFlag); ++ spin_unlock_irq(&_MsOS_EventGroup_Info[s32EventGroupId].stMutexEvent); ++ } ++ return bRet; ++} ++ ++wait_queue_head_t* MsOS_GetEventQueue (MS_S32 s32EventGroupId) ++{ ++ if ( (s32EventGroupId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32EventGroupId &= MSOS_ID_MASK; ++ } ++ return (&_MsOS_EventGroup_Info[s32EventGroupId].stSemaphore); ++} ++ ++ ++// ++// Timer management ++// ++static void _MsOS_TimerNotify(unsigned long data) ++{ ++ MS_S32 s32Id = (MS_S32) data; ++ ++ if (_MsOS_Timer_Info[s32Id].pTimerCb) ++ { ++ _MsOS_Timer_Info[s32Id].pTimerCb(0, s32Id| MSOS_ID_PREFIX); ++ } ++ _MsOS_Timer_Info[s32Id].timer.expires = jiffies + HZ*_MsOS_Timer_Info[s32Id].period/1000; ++ add_timer(&(_MsOS_Timer_Info[s32Id].timer)); ++} ++ ++ ++//------------------------------------------------------------------------------------------------- ++/// Create a Timer ++/// @param pTimerCb \b IN: timer callback function ++/// @param u32FirstTimeMs \b IN: first ms for timer expiration ++/// @param u32PeriodTimeMs \b IN: periodic ms for timer expiration after first expiration ++/// 0: one shot timer ++/// @param bStartTimer \b IN: TRUE: activates the timer after it is created ++/// FALSE: leaves the timer disabled after it is created ++/// @param pTimerName \b IN: Timer name (not used by eCos) ++/// @return >=0 : assigned Timer ID ++/// <0 : fail ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_CreateTimer (TimerCb pTimerCb, ++ MS_U32 u32FirstTimeMs, ++ MS_U32 u32PeriodTimeMs, ++ MS_BOOL bStartTimer, ++ char *pTimerName) ++{ ++ MS_S32 s32Id; ++ ++ TIMER_MUTEX_LOCK(); ++ for(s32Id=0;s32Id= MSOS_TIMER_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_Timer_Info[s32Id].pTimerCb= pTimerCb; ++ _MsOS_Timer_Info[s32Id].first = u32FirstTimeMs; ++ _MsOS_Timer_Info[s32Id].period = u32PeriodTimeMs; ++ _MsOS_Timer_Info[s32Id].timer.data = (unsigned long)s32Id; ++ _MsOS_Timer_Info[s32Id].timer.expires = jiffies + HZ*u32FirstTimeMs/1000; ++ _MsOS_Timer_Info[s32Id].timer.function = _MsOS_TimerNotify; ++ if (bStartTimer) ++ { ++ add_timer(&(_MsOS_Timer_Info[s32Id].timer)); ++ } ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Delete the Timer ++/// @param s32TimerId \b IN: Timer ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_DeleteTimer (MS_S32 s32TimerId) ++{ ++ //return FALSE; ++ ++ if ( (s32TimerId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TimerId &= MSOS_ID_MASK; ++ } ++ ++ if( _MsOS_Timer_Info[s32TimerId].bUsed ) ++ { ++ TIMER_MUTEX_LOCK(); ++ del_timer(&(_MsOS_Timer_Info[s32TimerId].timer)); ++ _MsOS_Timer_Info[s32TimerId].bUsed = FALSE; ++ ++ _MsOS_Timer_Info[s32TimerId].pTimerCb = NULL; ++ _MsOS_Timer_Info[s32TimerId].period = 0; ++ _MsOS_Timer_Info[s32TimerId].first = 0; ++ TIMER_MUTEX_UNLOCK(); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Start the Timer ++/// @param s32TimerId \b IN: Timer ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_StartTimer (MS_S32 s32TimerId) ++{ ++ //return FALSE; ++ ++ if ( (s32TimerId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TimerId &= MSOS_ID_MASK; ++ } ++ ++ if( _MsOS_Timer_Info[s32TimerId].bUsed ) ++ { ++ _MsOS_Timer_Info[s32TimerId].timer.expires = jiffies + _MsOS_Timer_Info[s32TimerId].period/1000; ++ add_timer(&(_MsOS_Timer_Info[s32TimerId].timer)); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Stop the Timer ++/// @param s32TimerId \b IN: Timer ID ++/// @return TRUE : succeed ++/// @return FALSE : fail ++/// @note MsOS_StopTimer then MsOS_StartTimer => The timer will trigger at the same relative ++/// intervals that it would have if it had not been disabled. ++//------------------------------------------------------------------------------------------------- ++MS_BOOL MsOS_StopTimer (MS_S32 s32TimerId) ++{ ++ //return FALSE; ++ ++ if ( (s32TimerId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TimerId &= MSOS_ID_MASK; ++ } ++ ++ if( _MsOS_Timer_Info[s32TimerId].bUsed ) ++ { ++ del_timer(&(_MsOS_Timer_Info[s32TimerId].timer)); ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++MS_S32 MsOS_CreateWorkQueueEvent(void * pTaskEntry) ++{ ++ MS_S32 s32Id; ++ MUTEX_TASK_LOCK(); ++ ++ for( s32Id=0; s32Id= MSOS_WORK_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_WorkEvent_Info[s32Id].bUsed = TRUE; ++ INIT_WORK(&_MsOS_WorkEvent_Info[s32Id].stWorkEventInfo, pTaskEntry); ++ ++ MUTEX_TASK_UNLOCK(); ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++MS_BOOL MsOS_DestroyWorkQueueTask(MS_S32 s32Id) ++{ ++ ++ if ( (s32Id & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32Id &= MSOS_ID_MASK; ++ } ++ MUTEX_TASK_LOCK(); ++ _MsOS_WorkQueue_Info[s32Id].bUsed = FALSE; ++ destroy_workqueue(_MsOS_WorkQueue_Info[s32Id].pstWorkQueueInfo); ++ _MsOS_WorkQueue_Info[s32Id].pstWorkQueueInfo = NULL; ++ ++ MUTEX_TASK_UNLOCK(); ++ return TRUE; ++} ++ ++MS_S32 MsOS_CreateWorkQueueTask(char *pTaskName) ++{ ++ MS_S32 s32Id; ++ MUTEX_TASK_LOCK(); ++ ++ for( s32Id=0; s32Id= MSOS_WORKQUEUE_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_WorkQueue_Info[s32Id].bUsed = TRUE; ++ _MsOS_WorkQueue_Info[s32Id].pstWorkQueueInfo = create_workqueue(pTaskName); ++ ++ MUTEX_TASK_UNLOCK(); ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++ ++MS_BOOL MsOS_QueueWork(MS_BOOL bTask, MS_S32 s32TaskId, MS_S32 s32QueueId, MS_U32 u32WaitMs) ++{ ++ MS_BOOL bRet; ++ if(bTask) ++ { ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ } ++ if ( (s32QueueId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32QueueId &= MSOS_ID_MASK; ++ } ++ MUTEX_TASK_LOCK(); ++ if(u32WaitMs) ++ { ++ u32WaitMs = msecs_to_jiffies(u32WaitMs); ++ if(bTask) ++ { ++ bRet = queue_delayed_work(_MsOS_WorkQueue_Info[s32TaskId].pstWorkQueueInfo , ++ to_delayed_work(&_MsOS_WorkEvent_Info[s32QueueId].stWorkEventInfo), ++ u32WaitMs); ++ } ++ else ++ { ++ bRet = schedule_delayed_work(to_delayed_work(&_MsOS_WorkEvent_Info[s32QueueId].stWorkEventInfo), u32WaitMs); ++ } ++ } ++ else ++ { ++ if(bTask) ++ { ++ bRet = queue_work(_MsOS_WorkQueue_Info[s32TaskId].pstWorkQueueInfo , ++ &_MsOS_WorkEvent_Info[s32QueueId].stWorkEventInfo); ++ } ++ else ++ { ++ bRet = schedule_work(&_MsOS_WorkEvent_Info[s32QueueId].stWorkEventInfo); ++ } ++ } ++ MUTEX_TASK_UNLOCK(); ++ return bRet; ++} ++MS_BOOL MsOS_FlushWorkQueue(MS_BOOL bTask, MS_S32 s32TaskId) ++{ ++ if(bTask) ++ { ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ } ++ MUTEX_TASK_LOCK(); ++ if(bTask) ++ { ++ flush_workqueue(_MsOS_WorkQueue_Info[s32TaskId].pstWorkQueueInfo); ++ } ++ else ++ { ++ flush_scheduled_work(); ++ } ++ MUTEX_TASK_UNLOCK(); ++ return TRUE; ++} ++MS_S32 MsOS_CreateTasklet(void * pTaskEntry,unsigned long u32data) ++{ ++ MS_S32 s32Id; ++ MUTEX_TASK_LOCK(); ++ ++ for( s32Id=0; s32Id= MSOS_TASKLET_MAX) ++ { ++ return -1; ++ } ++ ++ _MsOS_Tasklet_Info[s32Id].bUsed = TRUE; ++ tasklet_init(&_MsOS_Tasklet_Info[s32Id].stTaskletInfo, pTaskEntry,u32data); ++ MUTEX_TASK_UNLOCK(); ++ s32Id |= MSOS_ID_PREFIX; ++ return s32Id; ++} ++MS_BOOL MsOS_DestroyTasklet(MS_S32 s32Id) ++{ ++ ++ if ( (s32Id & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32Id &= MSOS_ID_MASK; ++ } ++ MUTEX_TASK_LOCK(); ++ _MsOS_Tasklet_Info[s32Id].bUsed = FALSE; ++ tasklet_kill(&_MsOS_Tasklet_Info[s32Id].stTaskletInfo); ++ ++ MUTEX_TASK_UNLOCK(); ++ return TRUE; ++} ++MS_BOOL MsOS_EnableTasklet (MS_S32 s32Id) ++{ ++ if ( (s32Id & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32Id &= MSOS_ID_MASK; ++ } ++ MUTEX_TASK_LOCK(); ++ tasklet_enable(&_MsOS_Tasklet_Info[s32Id].stTaskletInfo); ++ MUTEX_TASK_UNLOCK(); ++ return TRUE; ++} ++MS_BOOL MsOS_DisableTasklet (MS_S32 s32Id) ++{ ++ if ( (s32Id & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32Id &= MSOS_ID_MASK; ++ } ++ MUTEX_TASK_LOCK(); ++ tasklet_disable(&_MsOS_Tasklet_Info[s32Id].stTaskletInfo); ++ MUTEX_TASK_UNLOCK(); ++ return TRUE; ++} ++MS_BOOL MsOS_TaskletWork(MS_S32 s32TaskId) ++{ ++ MS_BOOL bRet = TRUE; ++ if ( (s32TaskId & MSOS_ID_PREFIX_MASK) != MSOS_ID_PREFIX ) ++ { ++ return FALSE; ++ } ++ else ++ { ++ s32TaskId &= MSOS_ID_MASK; ++ } ++ MUTEX_TASK_LOCK(); ++ tasklet_schedule(&_MsOS_Tasklet_Info[s32TaskId].stTaskletInfo); ++ MUTEX_TASK_UNLOCK(); ++ return bRet; ++} ++ ++// linux ++void* MsOS_Memalloc(size_t size, gfp_t flags) ++{ ++ return kmalloc(size, flags); ++} ++void MsOS_MemFree(void *pVirAddr) ++{ ++ kfree(pVirAddr); ++} ++void* MsOS_VirMemalloc(size_t size) ++{ ++ return vmalloc(size); ++} ++void MsOS_VirMemFree(void *pVirAddr) ++{ ++ vfree(pVirAddr); ++} ++void* MsOS_Memcpy(void *pstCfg,const void *pstInformCfg,__kernel_size_t size) ++{ ++ return memcpy(pstCfg, pstInformCfg, size); ++} ++void* MsOS_Memset(void *pstCfg,int val,__kernel_size_t size) ++{ ++ return memset(pstCfg, val, size); ++} ++unsigned int MsOS_clk_get_enable_count(MSOS_ST_CLK * clk) ++{ ++ return __clk_get_enable_count(clk); ++} ++ ++MSOS_ST_CLK * MsOS_clk_get_parent_by_index(MSOS_ST_CLK * clk,MS_U8 index) ++{ ++ return clk_get_parent_by_index(clk, index); ++} ++ ++int MsOS_clk_set_parent(MSOS_ST_CLK *clk, MSOS_ST_CLK *parent) ++{ ++ return clk_set_parent(clk, parent); ++} ++int MsOS_clk_prepare_enable(MSOS_ST_CLK *clk) ++{ ++ return clk_prepare_enable(clk); ++} ++void MsOS_clk_disable_unprepare(MSOS_ST_CLK *clk) ++{ ++ clk_disable_unprepare(clk); ++} ++unsigned long MsOS_clk_get_rate(MSOS_ST_CLK *clk) ++{ ++ return __clk_get_rate(clk); ++} ++unsigned long MsOS_copy_from_user(void *to, __user const void *from, unsigned long n) ++{ ++ return copy_from_user(to, from, n); ++} ++unsigned long MsOS_copy_to_user(void *to, const void __user *from, unsigned long n) ++{ ++ return copy_to_user(to, from, n); ++} ++void MsOS_WaitForCPUWriteToDMem(void) ++{ ++ Chip_Flush_MIU_Pipe(); //wait for CPU write to mem ++} ++void MsOS_ChipFlushCacheRange(unsigned long u32Addr, unsigned long u32Size) ++{ ++ Chip_Flush_Cache_Range(u32Addr,u32Size); //wait for CPU write to mem ++} ++unsigned char MsOS_GetSCLFrameDelay(void) ++{ ++ return gu8SclFrameDelay; ++} ++void MsOS_SetSCLFrameDelay(unsigned char u8delay) ++{ ++ gu8SclFrameDelay = u8delay; ++} ++E_VIPSetRule_TYPE MsOS_GetVIPSetRule(void) ++{ ++ return genVIPSetRule; ++} ++void MsOS_SetVIPSetRule(E_VIPSetRule_TYPE EnSetRule) ++{ ++ genVIPSetRule = EnSetRule; ++} ++MS_BOOL MsOS_GetHVSPDigitalZoomMode(void) ++{ ++ return gbDigitalZoomDropMode; ++} ++void MsOS_SetHVSPDigitalZoomMode(MS_BOOL bDrop) ++{ ++ gbDigitalZoomDropMode = bDrop; ++} ++ ++void MsOS_CheckEachIPByCMDQIST(void) ++{ ++ MDrv_VIP_CheckEachIPByCMDQIST(); ++} +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/msos/MsOS.h b/drivers/mstar/scl/infinity3/src/mxlib/msos/MsOS.h +new file mode 100644 +index 00000000..3453f57f +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/msos/MsOS.h +@@ -0,0 +1,946 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file MsOS.h ++/// @brief MStar OS Wrapper ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++ ++#ifndef _MS_OS_H_ ++#define _MS_OS_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Defines ++//------------------------------------------------------------------------------------------------- ++#define MSIF_MSOS_LIB_CODE {'M','S','O','S'} //Lib code ++#define MSIF_MSOS_LIBVER {'0','1'} //LIB version ++#define MSIF_MSOS_BUILDNUM {'0','1'} //Build Number ++#define MSIF_MSOS_CHANGELIST {'0','0','0','0','0','0','0','0'} //P4 ChangeList Number ++ ++#define MSOS_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_TAG, /* 'MSIF' */ \ ++ MSIF_CLASS, /* '00' */ \ ++ MSIF_CUS, /* 0x0000 */ \ ++ MSIF_MOD, /* 0x0000 */ \ ++ MSIF_CHIP, \ ++ MSIF_CPU, \ ++ MSIF_MSOS_LIB_CODE, /* IP__ */ \ ++ MSIF_MSOS_LIBVER, /* 0.0 ~ Z.Z */ \ ++ MSIF_MSOS_BUILDNUM, /* 00 ~ 99 */ \ ++ MSIF_MSOS_CHANGELIST, /* CL# */ \ ++ MSIF_OS ++ ++#define MSOS_TASK_MAX 32//(32+120) ++#define MSOS_WORKQUEUE_MAX 8//(8) ++#define MSOS_WORK_MAX 32//(8) ++#define MSOS_TASKLET_MAX 32//(8) ++#define MSOS_MEMPOOL_MAX (8+64) ++#define MSOS_FIXSIZE_MEMPOOL_MAX (8) ++#define MSOS_SEMAPHORE_MAX (32+150) ++#define MSOS_MUTEX_MAX 32//(64+240) ++#define MSOS_SPINLOCK_MAX 8 ++#define MSOS_EVENTGROUP_MAX 32//(64) ++#define MSOS_TIMER_MAX (32) ++#define MSOS_QUEUE_MAX (16+60) ++ ++#define MSOS_OS_MALLOC (0x7654FFFF) ++#define MSOS_MALLOC_ID (0x0000FFFF) ++#define SCL_DELAY2FRAMEINDOUBLEBUFFERMode 0 ++#define SCL_DELAYFRAME (MsOS_GetSCLFrameDelay()) ++#define ISZOOMDROPFRAME (MsOS_GetHVSPDigitalZoomMode()) ++#define MIU0_BASE 0x20000000 ++#define MIU0Vir_BASE 0xC0000000 ++#define _Phys2Miu(phys) ((phys&MIU0_BASE) ? (unsigned long)(phys - MIU0_BASE) :(unsigned long)(phys)) ++#define WDR_USE_CMDQ() MsOS_GetVIPSetRule() ++ ++//------------------------------------------------------------------------------------------------- ++// Macros ++//------------------------------------------------------------------------------------------------- ++//time and clock macros ++#define TICK_PER_ONE_MS (1) //Note: confirm Kernel fisrt ++#define MSOS_WAIT_FOREVER (0xffffff00/TICK_PER_ONE_MS) ++ ++#ifdef MSOS_PERF_DEBUG ++#define MSOS_PERF_PROFILE_DECL() MS_U32 u32time1=0, u32time2=0 ++#define MSOS_PERF_PROFILE_ON() u32time1 = MsOS_GetSystemTime() ++#define MSOS_PERF_PROFILE_OFF() u32time2 = MsOS_GetSystemTime(); \ ++ printf("[MSOS_DBG]%s:%d takes %6dms\n",__FILE__, __LINE__, u32time2-u32time1) ++#else ++#define MSOS_PERF_PROFILE_DECL() ++#define MSOS_PERF_PROFILE_ON() ++#define MSOS_PERF_PROFILE_OFF() ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure Declaration ++//------------------------------------------------------------------------------------------------- ++#if defined (MSOS_TYPE_ECOS) || defined (MSOS_TYPE_LINUX) || defined (MSOS_TYPE_NOS) || defined (MSOS_TYPE_UCOS) || defined (MSOS_TYPE_CE) ++ ++//compatible with Nucleus's task_entry ++typedef void ( *TaskEntry ) (MS_U32 argc, void *argv); ///< Task entry function argc: pass additional data to task entry; argv: not used by eCos ++typedef void ( *InterruptCb ) (InterruptNum eIntNum); ///< Interrupt callback function ++typedef void ( *SignalCb ) (MS_U32 u32Signals); ///< Signal callback function ++typedef void ( *TimerCb ) (MS_U32 u32StTimer, MS_U32 u32TimerID); ///< Timer callback function u32StTimer: not used; u32TimerID: Timer ID ++ ++typedef struct { ++ volatile MS_S32 s32Value; ++} MsOS_Atomic; ++ ++ ++#ifdef MSOS_TYPE_UCOS ++/// Task priority ++typedef enum ++{ ++ E_TASK_PRI_SYS = 0, ///< System priority task ( interrupt level driver, e.g. TSP, SMART ) ++ E_TASK_PRI_HIGHEST = 16, ///< Highest priority task ( background monitor driver, e.g. DVBC, HDMI ) ++ E_TASK_PRI_HIGH = 32, ///< High priority task ( service task ) ++ E_TASK_PRI_MEDIUM = 48, ///< Medium priority task ( application task ) ++ E_TASK_PRI_LOW = 64, ///< Low priority task ( nonbusy application task ) ++ E_TASK_PRI_LOWEST = 96, ///< Lowest priority task ( idle application task ) ++} TaskPriority; ++#else ++/// Task priority ++typedef enum ++{ ++ E_TASK_PRI_SYS = 0, ///< System priority task ( interrupt level driver, e.g. TSP, SMART ) ++ E_TASK_PRI_HIGHEST = 4, ///< Highest priority task ( background monitor driver, e.g. DVBC, HDMI ) ++ E_TASK_PRI_HIGH = 8, ///< High priority task ( service task ) ++ E_TASK_PRI_MEDIUM = 12, ///< Medium priority task ( application task ) ++ E_TASK_PRI_LOW = 16, ///< Low priority task ( nonbusy application task ) ++ E_TASK_PRI_LOWEST = 24, ///< Lowest priority task ( idle application task ) ++} TaskPriority; ++#endif ++ ++ ++/// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++/// Message size type ++typedef enum ++{ ++ E_MSG_FIXED_SIZE, ///< Fixed size message ++ E_MSG_VAR_SIZE, ///< Variable size message ++} MessageType; ++ ++/// Event mode ++typedef enum ++{ ++ E_AND, ///< Specify all of the requested events are require. ++ E_OR, ///< Specify any of the requested events are require. ++ E_AND_CLEAR, ///< Specify all of the requested events are require. If the request are successful, clear the event. ++ E_OR_CLEAR, ///< Specify any of the requested events are require. If the request are successful, clear the event. ++} EventWaitMode; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ MS_U32 uPoolSize; ++ MS_U32 u32MinAllocation; ++ MS_U32 u32Addr; ++ MsOSAttribute eAttribute; ++ char szName[16]; ++} MemoryPool_Info, *PMemoryPool_Info; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ TaskPriority ePriority; ++ void *pStack; ++ MS_U32 u32StackSize; ++ char szName[16]; ++} Task_Info, *PTask_Info; ++ ++typedef struct ++{ ++ unsigned int LX_MEM_ADDR; ++ unsigned int LX_MEM_LENGTH; ++ unsigned int LX_MEM2_ADDR; ++ unsigned int LX_MEM2_LENGTH; ++ unsigned int EMAC_ADDR; ++ unsigned int EMAC_LENGTH; ++ unsigned int DRAM_ADDR; ++ unsigned int DRAM_LENGTH; ++ unsigned int BB_ADDR; ++ unsigned int BB_LENGTH; ++ unsigned int MPOOL_MEM_ADDR; ++ unsigned int MPOOL_MEM_LENGTH; ++ unsigned int G3D_MEM0_ADDR; ++ unsigned int G3D_MEM0_LENGTH; ++ unsigned int G3D_MEM1_ADDR; ++ unsigned int G3D_MEM1_LENGTH; ++ unsigned int G3D_CMDQ_ADDR; ++ unsigned int G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t; ++ ++#elif defined (MSOS_TYPE_LINUX_KERNEL) ++ ++//#include ++//#include ++ ++//typedef void ( *TaskEntry ) (MS_U32 argc, void *argv); ///< Task entry function argc: pass additional data to task entry; argv: not used by eCos ++typedef int (*TaskEntry)(void *argv); ++//typedef void ( *InterruptCb ) (InterruptNum eIntNum); ///< Interrupt callback function ++typedef irqreturn_t ( *InterruptCb ) (InterruptNum eIntNum, void* dev_id); ++typedef void ( *SignalCb ) (MS_U32 u32Signals); ///< Signal callback function ++typedef void ( *TimerCb ) (MS_U32 u32StTimer, MS_U32 u32TimerID); ///< Timer callback function u32StTimer: not used; u32TimerID: Timer ID ++ ++typedef struct { ++ volatile MS_S32 s32Value; ++} MsOS_Atomic; ++ ++/// Task priority ++typedef enum ++{ ++ E_TASK_PRI_SYS = 0, ///< System priority task ( interrupt level driver, e.g. TSP, SMART ) ++ E_TASK_PRI_HIGHEST = 4, ///< Highest priority task ( background monitor driver, e.g. DVBC, HDMI ) ++ E_TASK_PRI_HIGH = 8, ///< High priority task ( service task ) ++ E_TASK_PRI_MEDIUM = 12, ///< Medium priority task ( application task ) ++ E_TASK_PRI_LOW = 16, ///< Low priority task ( nonbusy application task ) ++ E_TASK_PRI_LOWEST = 24, ///< Lowest priority task ( idle application task ) ++} TaskPriority; ++ ++/// Suspend type ++typedef enum ++{ ++ E_MSOS_PRIORITY, ///< Priority-order suspension ++ E_MSOS_FIFO, ///< FIFO-order suspension ++} MsOSAttribute; ++ ++/// Message size type ++typedef enum ++{ ++ E_MSG_FIXED_SIZE, ///< Fixed size message ++ E_MSG_VAR_SIZE, ///< Variable size message ++} MessageType; ++ ++/// Event mode ++typedef enum ++{ ++ E_AND, ///< Specify all of the requested events are require. ++ E_OR, ///< Specify any of the requested events are require. ++ E_AND_CLEAR, ///< Specify all of the requested events are require. If the request are successful, clear the event. ++ E_OR_CLEAR, ///< Specify any of the requested events are require. If the request are successful, clear the event. ++} EventWaitMode; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ MS_U32 uPoolSize; ++ MS_U32 u32MinAllocation; ++ MS_U32 u32Addr; ++ MsOSAttribute eAttribute; ++ char szName[16]; ++} MemoryPool_Info, *PMemoryPool_Info; ++ ++typedef struct ++{ ++ MS_S32 iId; ++ TaskPriority ePriority; ++ void *pStack; ++ MS_U32 u32StackSize; ++ char szName[16]; ++} Task_Info, *PTask_Info; ++ ++typedef struct ++{ ++ unsigned int LX_MEM_ADDR; ++ unsigned int LX_MEM_LENGTH; ++ unsigned int LX_MEM2_ADDR; ++ unsigned int LX_MEM2_LENGTH; ++ unsigned int EMAC_ADDR; ++ unsigned int EMAC_LENGTH; ++ unsigned int DRAM_ADDR; ++ unsigned int DRAM_LENGTH; ++ unsigned int BB_ADDR; ++ unsigned int BB_LENGTH; ++ unsigned int MPOOL_MEM_ADDR; ++ unsigned int MPOOL_MEM_LENGTH; ++ unsigned int G3D_MEM0_ADDR; ++ unsigned int G3D_MEM0_LENGTH; ++ unsigned int G3D_MEM1_ADDR; ++ unsigned int G3D_MEM1_LENGTH; ++ unsigned int G3D_CMDQ_ADDR; ++ unsigned int G3D_CMDQ_LENGTH; ++}IO_Sys_Info_t; ++ ++#elif defined (MSOS_TYPE_XXX) ++ ++#error "The OS is not supported now ..." ++ ++#endif ++ ++ ++///////////paul include for RTOS and LINUX ++typedef struct ++{ ++ struct task_struct *pThread; ++}MSOS_ST_TASKSTRUCT; ++typedef struct clk MSOS_ST_CLK; ++typedef struct workqueue_struct MSOS_ST_WORKQUEUE; ++typedef struct work_struct MSOS_ST_WORK; ++typedef struct tasklet_struct MSOS_ST_TASKLET; ++typedef struct platform_device MSOS_ST_PLATFORMDEVICE; ++typedef enum ++{ ++ E_VIPSetRule_Default = 0, ++ E_VIPSetRule_CMDQAct = 0x1, ++ E_VIPSetRule_CMDQCheck = 0x2, ++ E_VIPSetRule_CMDQAll = 0x4, ++ E_VIPSetRule_CMDQAllONLYSRAMCheck = 0x8, ++ E_VIPSetRule_CMDQAllCheck = 0x10, ++} E_VIPSetRule_TYPE; ++typedef enum ++{ ++ E_SCLIRQ_SC0 = 0, ++ E_SCLIRQ_SC1 , ++ E_SCLIRQ_SC2 , ++ E_SCLIRQ_MAX , ++} E_SCLIRQ_TYPE; ++typedef enum ++{ ++ E_CMDQIRQ_CMDQ0 = 0, ++ E_CMDQIRQ_CMDQ1 , ++ E_CMDQIRQ_CMDQ2 , ++ E_CMDQIRQ_MAX , ++} E_CMDQIRQ_TYPE; ++#define VIPSETRULE() (MsOS_GetVIPSetRule()) ++#define VIPDEFAULTSETRULE E_VIPSetRule_CMDQAll ++//for OSD bug, need to set same clk freq with fclk1 ++#define OSDinverseBug 1 ++#define CLKDynamic 0 ++#define USE_RTK 0 ++#define USE_Utility 0 ++#define VIR_RIUBASE 0xFD000000 ++//------------------------------------------------------------------------------------------------- ++// Extern Functions ++//------------------------------------------------------------------------------------------------- ++// ++// Init ++// ++MS_BOOL MsOS_Init (void); ++void MsOS_Exit (void); ++ ++ ++// ++// Memory management ++// ++MS_S32 MsOS_CreateMemoryPool (MS_U32 u32PoolSize, ++ MS_U32 u32MinAllocation, ++ void * pPoolAddr, ++ MsOSAttribute eAttribute, ++ char *pPoolName); ++ ++MS_BOOL MsOS_DeleteMemoryPool (MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_InfoMemoryPool (MS_S32 s32PoolId, ++ void **pPoolAddr, ++ MS_U32 *pu32PoolSize, ++ MS_U32 *pu32FreeSize, ++ MS_U32 *pu32LargestFreeBlockSize); ++ ++void * MsOS_AllocateMemory (MS_U32 u32Size, MS_S32 s32PoolId); ++ ++//void * MsOS_AllocateAlignedMemory (MS_U32 u32Size, MS_U32 u32AlignedByte, MS_S32 s32PoolId); ++ ++void * MsOS_ReallocateMemory (void *pOrgAddress, MS_U32 u32NewSize, MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_FreeMemory (void *pAddress, MS_S32 s32PoolId); ++ ++MS_S32 MsOS_CreateFixSizeMemoryPool (MS_U32 u32PoolSize, ++ MS_U32 u32BlockSize, ++ void * pPoolAddr, ++ MsOSAttribute eAttribute, ++ char *pPoolName); ++ ++MS_BOOL MsOS_DeleteFixSizeMemoryPool (MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_InfoFixSizeMemoryPool (MS_S32 s32PoolId, ++ void **pPoolAddr, ++ MS_U32 *pu32PoolSize, ++ MS_U32 *pu32FreeSize, ++ MS_U32 *pu32LargestFreeBlockSize); ++ ++void * MsOS_AllocateFixSizeMemory (MS_S32 s32PoolId); ++ ++MS_BOOL MsOS_FreeFixSizeMemory (void *pAddress, MS_S32 s32PoolId); ++ ++ ++// ++// Task ++// ++MS_S32 MsOS_CreateTask (TaskEntry pTaskEntry, ++ MS_U32 u32TaskEntryData, ++ MS_BOOL bAutoStart, ++ const char *pTaskName); ++MSOS_ST_TASKSTRUCT MsOS_GetTaskinfo(MS_S32 s32Id); ++int MsOS_GetUserNice(MSOS_ST_TASKSTRUCT *stTask); ++void MsOS_SetUserNice(MSOS_ST_TASKSTRUCT *stTask, long nice); ++MS_BOOL MsOS_DeleteTask (MS_S32 s32TaskId); ++int MsOS_SetSclIrqIDFormSys(MSOS_ST_PLATFORMDEVICE *pdev,unsigned char u8idx,E_SCLIRQ_TYPE enType); ++int MsOS_SetCmdqIrqIDFormSys(MSOS_ST_PLATFORMDEVICE *pdev,unsigned char u8idx,E_CMDQIRQ_TYPE enType); ++int MsOS_GetIrqIDCMDQ(E_CMDQIRQ_TYPE enType); ++int MsOS_GetIrqIDSCL(E_SCLIRQ_TYPE enType); ++ ++MS_BOOL MsOS_SetTaskWork(MS_S32 s32TaskId); ++MS_BOOL MsOS_SleepTaskWork(MS_S32 s32TaskId); ++ ++void MsOS_YieldTask (void); ++ ++void MsOS_DelayTask (MS_U32 u32Ms); ++ ++void MsOS_DelayTaskUs (MS_U32 u32Us); ++ ++MS_BOOL MsOS_ResumeTask (MS_S32 s32TaskId); ++ ++MS_BOOL MsOS_SuspendTask (MS_S32 s32TaskId); ++ ++MS_S32 MsOS_InfoTaskID (void); ++//------------------------------------------------------------------------------------------------- ++/// Get thread ID of current thread/process in OS ++/// @return : current thread ID ++//------------------------------------------------------------------------------------------------- ++MS_S32 MsOS_GetOSThreadID (void); ++ ++// ++// Mutex ++// ++#define MSOS_PROCESS_PRIVATE 0x00000000 ++#define MSOS_PROCESS_SHARED 0x00000001 ++#define MAX_MUTEX_NAME_LENGTH 16 ++MS_S32 MsOS_CreateMutex ( MsOSAttribute eAttribute, char *pMutexName, MS_U32 u32Flag); ++MS_S32 MsOS_CreateSpinlock ( MsOSAttribute eAttribute, char *pMutexName1, MS_U32 u32Flag); ++ ++MS_BOOL MsOS_DeleteMutex (MS_S32 s32MutexId); ++MS_BOOL MsOS_DeleteSpinlock (MS_S32 s32MutexId); ++MS_BOOL MsOS_ObtainMutex_IRQ(MS_S32 s32MutexId); ++MS_BOOL MsOS_ObtainMutex (MS_S32 s32MutexId, MS_U32 u32WaitMs); ++MS_BOOL MsOS_ReleaseMutex_IRQ (MS_S32 s32MutexId); ++char * MsOS_CheckMutex(char *str,char *end); ++MS_BOOL MsOS_ReleaseMutex (MS_S32 s32MutexId); ++MS_BOOL MsOS_ReleaseMutexAll (void); ++ ++MS_BOOL MsOS_InfoMutex (MS_S32 s32MutexId, MsOSAttribute *peAttribute, char *pMutexName); ++ ++ ++// ++// Semaphore ++// ++MS_S32 MsOS_CreateSemaphore (MS_U32 u32InitCnt, ++ MsOSAttribute eAttribute, ++ char *pName); ++ ++MS_BOOL MsOS_DeleteSemaphore (MS_S32 s32SemaphoreId); ++ ++MS_BOOL MsOS_ObtainSemaphore (MS_S32 s32SemaphoreId, MS_U32 u32WaitMs); ++ ++MS_BOOL MsOS_ReleaseSemaphore (MS_S32 s32SemaphoreId); ++ ++MS_BOOL MsOS_InfoSemaphore (MS_S32 s32SemaphoreId, MS_U32 *pu32Cnt, MsOSAttribute *peAttribute, char *pSemaphoreName); ++ ++ ++// ++// Event management ++// ++MS_S32 MsOS_CreateEventGroup (char *pName); ++ ++MS_BOOL MsOS_CreateEventGroupRing (MS_U8 u8Id); ++ ++MS_BOOL MsOS_DeleteEventGroup (MS_S32 s32EventGroupId); ++MS_BOOL MsOS_DeleteEventGroupRing (MS_S32 s32EventGroupId); ++MS_BOOL MsOS_SetEvent_IRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++ ++MS_BOOL MsOS_SetEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++MS_BOOL MsOS_SetEventRing (MS_S32 s32EventGroupId); ++MS_U32 MsOS_GetEvent(MS_S32 s32EventGroupId); ++MS_U32 MsOS_GetandClearEventRing(MS_U32 u32EventGroupId); ++MS_BOOL MsOS_ClearEventIRQ (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++MS_BOOL MsOS_ClearEvent (MS_S32 s32EventGroupId, MS_U32 u32EventFlag); ++MS_BOOL MsOS_WaitEvent (MS_S32 s32EventGroupId, ++ MS_U32 u32WaitEventFlag, ++ MS_U32 *pu32RetrievedEventFlag, ++ EventWaitMode eWaitMode, ++ MS_U32 u32WaitMs); ++wait_queue_head_t* MsOS_GetEventQueue (MS_S32 s32EventGroupId); ++ ++/* ++// ++// Signal management ++// ++MS_BOOL MsOS_CreateSignal (SignalCb pSignalCb); ++ ++MS_BOOL MsOS_ControlSignals (MS_U32 u32SignalMask); ++ ++MS_BOOL MsOS_SendSignals (MS_S32 s32TaskId, MS_U32 u32Signal); ++ ++MS_U32 MsOS_ReceiveSignals (void); ++*/ ++ ++// ++// Timer management ++// ++MS_S32 MsOS_CreateTimer (TimerCb pTimerCb, ++ MS_U32 u32FirstTimeMs, ++ MS_U32 u32PeriodTimeMs, ++ MS_BOOL bStartTimer, ++ char *pName); ++ ++MS_BOOL MsOS_DeleteTimer (MS_S32 s32TimerId); ++ ++MS_BOOL MsOS_StartTimer (MS_S32 s32TimerId); ++ ++MS_BOOL MsOS_StopTimer (MS_S32 s32TimerId); ++ ++MS_BOOL MsOS_ResetTimer (MS_S32 s32TimerId, ++ MS_U32 u32FirstTimeMs, ++ MS_U32 u32PeriodTimeMs, ++ MS_BOOL bStartTimer); ++void* MsOS_Memalloc(size_t size, gfp_t flags); ++MS_BOOL MsOS_FlushWorkQueue(MS_BOOL bTask, MS_S32 s32TaskId); ++MS_BOOL MsOS_QueueWork(MS_BOOL bTask, MS_S32 s32TaskId, MS_S32 s32QueueId, MS_U32 u32WaitMs); ++MS_S32 MsOS_CreateWorkQueueTask(char *pTaskName); ++MS_BOOL MsOS_DestroyWorkQueueTask(MS_S32 s32Id); ++MS_S32 MsOS_CreateWorkQueueEvent(void * pTaskEntry); ++MS_BOOL MsOS_TaskletWork(MS_S32 s32TaskId); ++MS_BOOL MsOS_DisableTasklet (MS_S32 s32Id); ++MS_BOOL MsOS_EnableTasklet (MS_S32 s32Id); ++MS_BOOL MsOS_DestroyTasklet(MS_S32 s32Id); ++MS_S32 MsOS_CreateTasklet(void * pTaskEntry,unsigned long u32data); ++void MsOS_MemFree(void *pVirAddr); ++void* MsOS_VirMemalloc(size_t size); ++void MsOS_VirMemFree(void *pVirAddr); ++void* MsOS_Memcpy(void *pstCfg,const void *pstInformCfg,__kernel_size_t size); ++void* MsOS_Memset(void *pstCfg,int val,__kernel_size_t size); ++unsigned int MsOS_clk_get_enable_count(MSOS_ST_CLK * clk); ++MSOS_ST_CLK * MsOS_clk_get_parent_by_index(MSOS_ST_CLK * clk,MS_U8 index); ++int MsOS_clk_set_parent(MSOS_ST_CLK *clk, MSOS_ST_CLK *parent); ++int MsOS_clk_prepare_enable(MSOS_ST_CLK *clk); ++void MsOS_clk_disable_unprepare(MSOS_ST_CLK *clk); ++unsigned long MsOS_clk_get_rate(MSOS_ST_CLK *clk); ++unsigned long MsOS_copy_from_user(void *to, __user const void *from, unsigned long n); ++unsigned long MsOS_copy_to_user(void *to, const void __user *from, unsigned long n); ++void MsOS_WaitForCPUWriteToDMem(void); ++void MsOS_ChipFlushCacheRange(unsigned long u32Addr, unsigned long u32Size); ++unsigned char MsOS_GetSCLFrameDelay(void); ++E_VIPSetRule_TYPE MsOS_GetVIPSetRule(void); ++void MsOS_SetVIPSetRule(E_VIPSetRule_TYPE EnSetRule); ++void MsOS_SetHVSPDigitalZoomMode(MS_BOOL bDrop); ++MS_BOOL MsOS_GetHVSPDigitalZoomMode(void); ++ ++void MsOS_SetSCLFrameDelay(unsigned char u8delay); ++void MsOS_CheckEachIPByCMDQIST(void); ++ ++// ++// System time ++// ++//MS_U32 MsOS_GetSystemTick (void); ++ ++MS_U32 MsOS_GetSystemTime (void); ++void MsOS_SetPollWait(void *filp,void *pWaitQueueHead,void *pstPollQueue); ++MS_U64 MsOS_GetSystemTimeStamp (void); ++ ++ ++MS_U32 MsOS_Timer_DiffTimeFromNow(MS_U32 u32TaskTimer); ///[OBSOLETE] ++ ++MS_U32 MsOS_Timer_DiffTime(MS_U32 u32Timer, MS_U32 u32TaskTimer); ///[OBSOLETE] ++//MS_BOOL MsOS_SetSystemTime (MS_U32 u32SystemTime); ++ ++ ++// ++// Queue ++// ++MS_S32 MsOS_CreateQueue (void *pStartAddr, ++ MS_U32 u32QueueSize, ++ MessageType eMessageType, ++ MS_U32 u32MessageSize, ++ MsOSAttribute eAttribute, ++ char *pQueueName); ++ ++MS_BOOL MsOS_DeleteQueue (MS_S32 s32QueueId); ++ ++MS_BOOL MsOS_SendToQueue (MS_S32 s32QueueId, MS_U8 *pu8Message, MS_U32 u32Size, MS_U32 u32WaitMs); ++ ++MS_BOOL MsOS_RecvFromQueue (MS_S32 s32QueueId, MS_U8 *pu8Message, MS_U32 u32IntendedSize, MS_U32 *pu32ActualSize, MS_U32 u32WaitMs); ++ ++MS_BOOL MsOS_PeekFromQueue (MS_S32 s32QueueId, MS_U8 *pu8Message, MS_U32 u32IntendedSize, MS_U32 *pu32ActualSize); ++ ++// ++// Atomic operation ++// ++void MsOS_AtomicSet(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++MS_S32 MsOS_AtomicRead(const MsOS_Atomic *pAtomic); ++ ++void MsOS_AtomicAdd(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++void MsOS_AtomicSub(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++ ++MS_S32 MsOS_AtomicAddReturn(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++MS_S32 MsOS_AtomicSubReturn(MsOS_Atomic *pAtomic, MS_S32 s32Value); ++ ++// ++// Per-thread data ++// ++MS_BOOL MsOS_CreateThreadDataIndex(MS_U32 *pu32Index); ++MS_BOOL MsOS_DeleteThreadDataIndex(MS_U32 u32Index); ++MS_BOOL MsOS_SetThreadData(MS_U32 u32Index, MS_U32 u32Data); ++MS_BOOL MsOS_GetThreadData(MS_U32 u32Index, MS_U32 *pu32Data); ++ ++ ++// ++// Interrupt management ++// ++MS_BOOL MsOS_AttachInterrupt (InterruptNum eIntNum, InterruptCb pIntCb,unsigned long flags,const char *name); ++ ++MS_BOOL MsOS_DetachInterrupt (InterruptNum eIntNum); ++ ++MS_BOOL MsOS_EnableInterrupt (InterruptNum eIntNum); ++ ++MS_BOOL MsOS_DisableInterrupt (InterruptNum eIntNum); ++ ++MS_BOOL MsOS_In_Interrupt (void); ++ ++MS_U32 MsOS_DisableAllInterrupts(void); ++ ++MS_BOOL MsOS_RestoreAllInterrupts(MS_U32 u32OldInterrupts); ++ ++MS_BOOL MsOS_EnableAllInterrupts(void); ++ ++ ++ ++#if defined(__aeon__) ++typedef enum { ++ E_EXCEPTION_BUS_ERROR = 2, ++ E_EXCEPTION_DATA_PAGE_FAULT, ++ E_EXCEPTION_INSTRUCTION_PAGE_FAULT, ++ E_EXCEPTION_TICK_TIMER, ///< tick timer, do not use directly ++ E_EXCEPTION_UNALIGNED_ACCESS, ++ E_EXCEPTION_ILLEGAL_INSTRUCTION, ++ E_EXCEPTION_EXTERNAL_INTERRUPT, ///< external interrupt, do not use directly ++ E_EXCEPTION_DTLB_MISS, ++ E_EXCEPTION_ITLB_MISS, ++ E_EXCEPTION_RANGE, ++ E_EXCEPTION_SYSCALL, ///< caused by l.sys ++ E_EXCEPTION_RESERVED, ++ E_EXCEPTION_TRAP, ///< caused by l.trap ++ E_EXCEPTION_MAX = E_EXCEPTION_TRAP, ++} MHAL_EXCEPTION_TYPE; ++ ++typedef enum { ++ E_INTERRUPT_TICK_TIMER, //< risc32 builtin tick timer ++ E_INTERRUPT_00 = 1, //< PIC interrupt start from 1 for handler performance ++ E_INTERRUPT_01, ++ E_INTERRUPT_02, ++ E_INTERRUPT_03, ++ E_INTERRUPT_04, ++ E_INTERRUPT_05, ++ E_INTERRUPT_06, ++ E_INTERRUPT_07, ++ E_INTERRUPT_08, ++ E_INTERRUPT_09, ++ E_INTERRUPT_10, ++ E_INTERRUPT_11, ++ E_INTERRUPT_12, ++ E_INTERRUPT_13, ++ E_INTERRUPT_14, ++ E_INTERRUPT_15, ++ E_INTERRUPT_16, ++ E_INTERRUPT_17, ++ E_INTERRUPT_18, ++ E_INTERRUPT_19, ++ E_INTERRUPT_20, ++ E_INTERRUPT_21, ++ E_INTERRUPT_22, ++ E_INTERRUPT_23, ++ E_INTERRUPT_24, ++ E_INTERRUPT_25, ++ E_INTERRUPT_26, ++ E_INTERRUPT_27, ++ E_INTERRUPT_28, ++ E_INTERRUPT_29, ++ E_INTERRUPT_30, ++ E_INTERRUPT_31, ++} MHAL_INTERRUPT_TYPE; ++ ++// Aliases for interrupt number ++#define E_INTERRUPT_FIQ E_INTERRUPT_02 ++#define E_INTERRUPT_IRQ E_INTERRUPT_03 ++#define E_INTERRUPT_UART E_INTERRUPT_19 ++#define E_INTERRUPT_MAX E_INTERRUPT_31 ++ ++typedef struct ++{ ++ unsigned long r[32]; ///< GPR registers ++#ifdef __AEONR2__ ++ unsigned long machi2; // Highest 32-bits of new 32x32=64 multiplier ++#endif ++ unsigned long machi; // High and low words of ++ unsigned long maclo; // multiply/accumulate reg ++ ++ // These are only saved for exceptions and interrupts ++ int vector; ///< vector number ++ int sr; ///< status register ++ unsigned long pc; ///< program counter ++ ++ // Saved only for exceptions, and not restored when continued: ++ // Effective address of instruction/data access that caused exception ++ unsigned long eear; ///< exception effective address ++} MHAL_SavedRegisters; ++#else ++typedef enum { ++ E_EXCEPTION_DATA_TLBERROR_ACCESS = 1, // TLB modification exception ++ E_EXCEPTION_DATA_TLBMISS_ACCESS, // TLB miss (Load or IFetch) ++ E_EXCEPTION_DATA_TLBMISS_WRITE, // TLB miss (Store) ++ E_EXCEPTION_DATA_UNALIGNED_ACCESS, // Address error (Load or Ifetch) ++ E_EXCEPTION_DATA_UNALIGNED_WRITE, // Address error (store) ++ E_EXCEPTION_CODE_ACCESS, // Bus error (Ifetch) ++ E_EXCEPTION_DATA_ACCESS, // Bus error (data load or store) ++ E_EXCEPTION_SYSTEM_CALL, // System call ++ E_EXCEPTION_INSTRUCTION_BP, // Break point ++ E_EXCEPTION_ILLEGAL_INSTRUCTION, // Reserved instruction ++ E_EXCEPTION_COPROCESSOR, // Coprocessor unusable ++ E_EXCEPTION_OVERFLOW, // Arithmetic overflow ++ E_EXCEPTION_RESERVED_13, // Reserved ++ E_EXCEPTION_DIV_BY_ZERO, // Division-by-zero [reserved vector] ++ E_EXCEPTION_FPU, // Floating point exception ++ E_EXCEPTION_MAX = E_EXCEPTION_FPU, ++} MHAL_EXCEPTION_TYPE; ++ ++typedef enum { ++ E_INTERRUPT_02 = 0, ++ E_INTERRUPT_03, ++ E_INTERRUPT_04, ++ E_INTERRUPT_05, ++ E_INTERRUPT_06, ++ E_INTERRUPT_07, ++} MHAL_INTERRUPT_TYPE; ++ ++// Aliases for interrupt number ++#define E_INTERRUPT_FIQ E_INTERRUPT_03 ++#define E_INTERRUPT_IRQ E_INTERRUPT_02 ++#define E_INTERRUPT_TICK_TIMER E_INTERRUPT_07 ++#define E_INTERRUPT_MAX E_INTERRUPT_07 ++#define E_EXCEPTION_TRAP E_EXCEPTION_RESERVED_13 ++ ++typedef struct ++{ ++ // These are common to all saved states ++ unsigned long d[32]; /* Data regs */ ++ unsigned long hi; /* hi word of mpy/div reg */ ++ unsigned long lo; /* lo word of mpy/div reg */ ++ ++ // The status register contains the interrupt-enable bit which needs ++ // to be preserved across context switches. ++ unsigned long sr; /* Status Reg */ ++ ++ // These are only saved for exceptions and interrupts ++ unsigned long vector; /* Vector number */ ++ unsigned long pc; /* Program Counter */ ++ ++ // These are only saved for exceptions, and are not restored ++ // when continued. ++ unsigned long cause; /* Exception cause register */ ++ unsigned long badvr; /* Bad virtual address reg */ ++ ++} MHAL_SavedRegisters; ++#endif ++ ++#if defined (__arm__) ++typedef void (*mhal_isr_t)(void); ++#else ++typedef void (*mhal_isr_t)(MHAL_SavedRegisters *regs, MS_U32 vector); ++#endif ++ ++MS_U32 MsOS_CPU_DisableInterrupt (void); ++ ++MS_BOOL MsOS_CPU_EnableInterrupt (void); ++ ++MS_BOOL MsOS_CPU_RestoreInterrupt (MS_U32 u32OldInterrupts); ++ ++MS_BOOL MsOS_CPU_MaskAllInterrupt (void); ++ ++MS_BOOL MsOS_CPU_MaskInterrupt (MHAL_INTERRUPT_TYPE intr_num); ++ ++MS_BOOL MsOS_CPU_UnMaskInterrupt (MHAL_INTERRUPT_TYPE intr_num); ++ ++MS_BOOL MsOS_CPU_LockInterrupt (void); ++ ++MS_BOOL MsOS_CPU_UnLockInterrupt (void); ++ ++MS_BOOL MsOS_CPU_AttachInterrupt (MHAL_INTERRUPT_TYPE intr_num, mhal_isr_t isr, MS_U32 dat); ++ ++MS_BOOL MsOS_CPU_DetachInterrupt (MHAL_INTERRUPT_TYPE intr_num); ++ ++MS_BOOL MsOS_CPU_AttachException (MHAL_EXCEPTION_TYPE expt_num, mhal_isr_t isr, MS_U32 dat); ++ ++MS_BOOL MsOS_CPU_DetachExceptiont (MHAL_EXCEPTION_TYPE expt_num); ++ ++MS_BOOL MsOS_CPU_SetEBASE (MS_U32 u32Addr); ++ ++ ++ ++ ++// ++// Cache Opertation ++// ++MS_BOOL MsOS_Dcache_Flush( MS_U32 u32Start , MS_U32 u32Size ); ++ ++MS_BOOL MsOS_Dcache_Invalidate( MS_U32 u32Start , MS_U32 u32Size ); ++ ++MS_BOOL MsOS_Dcache_Writeback( MS_U32 u32Start , MS_U32 u32Size ); ++ ++#if defined(CHIP_T12) || defined(CHIP_T8) || defined(CHIP_J2) || defined(CHIP_A2) || defined(CHIP_A5) || defined(CHIP_A3) ++MS_BOOL MsOS_L2Cache_Flush(void); ++MS_BOOL MsOS_L2Cache_Read(void); ++#endif ++ ++// ++// CPU relative Operation ++// ++void MsOS_Sync(void); ++ ++typedef enum //_MsOSMPool_DbgLevel ++{ ++ E_MsOSMPool_DBG_Release = 0, ++ E_MsOSMPool_DBG_L1, // display error msg ++} MsOSMPool_DbgLevel; ++ ++// Kernel related information ++MS_BOOL MDrv_SYS_Info(IO_Sys_Info_t* SysInfo); ++// MPool Operation ++void MsOS_MPool_SetDbgLevel(MsOSMPool_DbgLevel DbgLevel); ++MS_BOOL MsOS_MPool_Init(void); ++MS_BOOL MsOS_MPool_Get(void** pAddrVirt, MS_U32* pu32AddrPhys, MS_U32* pu32Size, MS_BOOL bNonCache); ++MS_BOOL MsOS_MPool_Close(void); ++MS_U32 MsOS_MPool_VA2PA(MS_U32 pAddrVirt); ++MS_U32 MsOS_MPool_PA2KSEG1(MS_U32 pAddrPhys); ++MS_U32 MsOS_MPool_PA2KSEG0(MS_U32 pAddrPhys); ++MS_BOOL MsOS_MPool_Dcache_Flush(MS_U32 pAddrVirt, MS_U32 u32Size); // the input address should be user mode cacheable address ++MS_BOOL MsOS_MPool_Mapping(MS_U8 u8MiuSel, MS_U32 u32Offset, MS_U32 u32MapSize, MS_BOOL bNonCache); ++MS_BOOL MsOS_MPool_Kernel_Detect(MS_U32 *lx_addr, MS_U32 *lx_size, MS_U32 *lx2_addr, MS_U32 *lx2_size); ++ ++#define MsOS_MPool_PA2VA MsOS_MPool_PA2KSEG1 ++ ++// Share memory operation ++#define MAX_CLIENT_NAME_LENGTH 50 ++#define MSOS_SHM_QUERY 0x00000000 ++#define MSOS_SHM_CREATE 0x00000001 ++ ++MS_BOOL MsOS_SHM_Init(void); ++MS_BOOL MsOS_SHM_GetId(MS_U8* pu8ClientName, MS_U32 u32BufSize, MS_U32* pu32ShmId, MS_U32* pu32Addr, MS_U32* pu32BufSize, MS_U32 u32Flag); ++MS_BOOL MsOS_SHM_FreeId(MS_U8* pu8ClientName, MS_U32 u32ShmId); ++ ++// ++// OS Dependent Macro ++// ++ ++// Worldwide thread safe macro ++// Usage: ++// MS_S32 os_X_MutexID; ++// os_X_MutexID = OS_CREATE_MUTEX(_M_); ++// if (os_X_MutexID < 0) { return FALSE; } ++// if (OS_OBTAIN_MUTEX(os_X_MutexID, 1000) == FALSE) { return FALSE; } ++// ... ++// OS_RELEASE_MUTEX(os_X_MutexID); ++// return X; ++// ++ ++#define OS_CREATE_MUTEX(_M_) MsOS_CreateMutex(E_MSOS_FIFO, "OS_"#_M_"_Mutex", MSOS_PROCESS_SHARED) ++#define OS_OBTAIN_MUTEX(_mx, _tm) MsOS_ObtainMutex(_mx, _tm) ++#define OS_RELEASE_MUTEX(_mx) MsOS_ReleaseMutex(_mx) ++#define OS_DELETE_MUTEX(_mx) MsOS_DeleteMutex(_mx) ++#define OS_DELAY_TASK(_msec) MsOS_DelayTask(_msec) ++#define OS_SYSTEM_TIME() MsOS_GetSystemTime() ++#define OS_ENTER_CRITICAL() MsOS_DisableAllInterrupts(); ++#define OS_EXIT_CRITICAL() MsOS_EnableAllInterrupts(); ++ ++//------------------------------------------------------------------------------------------------- ++// Virutal/Physial address operation ++//------------------------------------------------------------------------------------------------- ++MS_U32 MsOS_VA2PA(MS_U32 addr); ++MS_U32 MsOS_PA2KSEG0(MS_U32 addr); ++MS_U32 MsOS_PA2KSEG1_1(MS_U32 addr); ++void MsOS_FlushMemory(void); ++void MsOS_ReadMemory(void); ++ ++#define MS_VA2PA(_addr_) (MS_U32)MsOS_VA2PA((_addr_)) ++#define MS_PA2KSEG0(_addr_) (MS_U32)MsOS_PA2KSEG0((_addr_)) ++#define MS_PA2KSEG1(_addr_) (MS_U32)MsOS_PA2KSEG1_1((_addr_)) ++ ++//------------------------------------------------------------------------------------------------- ++// Debug message ++//------------------------------------------------------------------------------------------------- ++#define MS_CRITICAL_MSG(x) x // for dump critical message ++#define MS_FATAL_MSG(fmt,...) printf( "[MS_FATAL]: %s: %d \n" fmt, __FUNCTION__, __LINE__, ## __VA_ARGS__) ++ ++ ++#if defined (MSOS_TYPE_LINUX_KERNEL) ++#define printf(_fmt, _args...) printk(KERN_WARNING _fmt, ## _args) ++#define MsOS_scnprintf(buf, size, _fmt, _args...) scnprintf(buf, size, _fmt, ## _args) ++//#define printf printk ++#elif defined (MSOS_TYPE_CE) ++ ++typedef const wchar_t* LPCWSTR; ++extern void NKDbgPrintfW(LPCWSTR lpszFmt, ...); ++#define TXT(quote) L##quote ++#define printf(fmt, ...) NKDbgPrintfW(TXT(fmt), __VA_ARGS__) ++ ++#endif ++#if defined (MS_DEBUG) ++ #define MS_DEBUG_MSG(x) x ++#elif defined (MS_OPTIMIZE) ++ #define MS_DEBUG_MSG(x) // retail version remove debug message ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// debug ++//------------------------------------------------------------------------------------------------- ++extern void MsOS_RegMyDbg(void); ///< MsOS debug register itself debug ++ ++typedef MS_BOOL (*UartDbg_IP_CallBack) (int argc, char *argv[]); ///< MsOS debug call back function prototype ++ ++///< define your own name, help, callback mapping here ++typedef struct ++{ ++ const char *Func_Name; ++ const char *Func_Help; ++ UartDbg_IP_CallBack pCallBack; ++} MS_DBG_LINK; ++ ++///< for application to pass debug command into MsOS debug module ++extern MS_BOOL MsOS_Dbg_ParseCmd(char *Cmd, MS_U32 u32CmdLen); ++ ++///< register your main menu here ++extern MS_BOOL MsOS_Dbg_Regist(const char *Func_Name, const char *Func_Help, MS_DBG_LINK *pAryDbgLink); ++ ++///< for user to handle their own sub menu ++extern MS_BOOL MsOS_Dbg_ExecuteSubCB(const char *Func_Name, int argc, char *argv[], MS_DBG_LINK *pAryDbgLink); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif // _MS_OS_H_ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ.c +new file mode 100644 +index 00000000..0d8b6e98 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ.c +@@ -0,0 +1,9171 @@ ++// $Change: 628136 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#define _MDRV_PQ_C_ ++ ++ ++#ifdef MSOS_TYPE_LINUX ++#include ++#endif ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++#include "MsCommon.h" ++//#include "MsVersion.h" ++#include "MsOS.h" ++#include "hwreg_utility2.h" ++#include "color_reg.h" ++ ++ ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++#include "drvPQ_Datatypes.h" ++#include "mhal_pq.h" ++#include "drvPQ_Bin.h" ++ ++#include "QualityMode.c" ++ ++ ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++ ++#define PQTAB_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_PQTAB) x; } while(0); ++#define SRULE_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_SRULE) x; } while(0); ++#define CSCRULE_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_CSCRULE) x; } while(0); ++#define PQGRULE_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_GRULE) x; } while(0); ++#define PQBW_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_BW) x; } while(0); ++#define PQMADi_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_MADI) x; } while(0); ++#define PQINFO_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_INFO) x; } while(0); ++#define PQIOCTL_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_IOCTL) x; } while(0); ++#define PQP2P_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_P2P) x; } while(0); ++#define PQCOLOR_DBG(x) do { if( _u16PQDbgSwitch & PQ_DBG_COLOR) x; } while(0); ++ ++#if PQ_ENABLE_UNUSED_FUNC ++static MSIF_Version _drv_pq_version = { ++ ++ #if (defined( MSOS_TYPE_CE) || defined(MSOS_TYPE_LINUX_KERNEL)) ++ { PQ_DRV_VERSION }, ++ #else ++ .DDI = { PQ_DRV_VERSION }, ++ #endif ++}; ++ ++static MS_BOOL _bColorRange0_255[PQ_MAX_WINDOW]; ++static MS_BOOL _bPointToPointMode = FALSE; ++static MS_BOOL _bDS_En = FALSE; ++static MS_U16 _u16RW_Method = 0; ++ ++#endif ++ ++#if PQ_ENABLE_DEBUG ++MS_BOOL _u16DbgSwitch = 1; ++#endif ++ ++static MS_U16 _u16PQSrcType[PQ_MAX_WINDOW]; ++MS_U16 _u16PQSrcType_DBK_Detect[PQ_MAX_WINDOW]; //For Auto_DBK SW driver used ++ ++static PQ_INPUT_SOURCE_TYPE _enInputSourceType[PQ_MAX_WINDOW]; ++ ++ ++//whether current status is Point-to-point mode ++ ++static MS_U16 _u16PQDbgSwitch = 0; ++ ++ ++ ++typedef struct ++{ ++ // input timing ++ MS_U16 u16input_hsize; ++ MS_U16 u16input_vtotal; ++ MS_U16 u16input_vfreq; ++ ++ // output timing ++ MS_U16 u16output_hsize; ++ MS_U16 u16output_vtotal; ++ MS_U16 u16output_vfreq; ++ ++ // memory format ++ MS_BOOL bFBL; ++ MS_BOOL bMemFmt422; ++ MS_BOOL bInterlace; ++ MS_BOOL b4RMode; ++ MS_U8 u8BitsPerPixel; ++ ++ // osd ++ MS_BOOL bOSD_On; ++ MS_U16 u16OSD_hsize; ++ MS_U8 u8OSD_BitsPerPixel; ++ ++ // dram ++ MS_U32 u32MemBW; ++ MS_BOOL bSC_MIUSel; ++ MS_BOOL bGOP_MIUSel; ++ MS_BOOL bDDR2; ++ MS_U32 u32DDRFreq; ++ MS_U8 u8BusWidth; ++ MS_U32 u32Miu0MemSize; ++ MS_U32 u32Miu1MemSize; ++ ++ // PVR ++ MS_U32 u32PVR_BW; ++ ++ //AEON ++ MS_U32 u32MISC_BW; ++} BW_INFO_t; ++ ++#if (PQ_ENABLE_PIP) ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++static PQ_DISPLAY_TYPE genDisplayType = PQ_DISPLAY_ONE; ++#endif ++#endif ++ ++#if (defined( MSOS_TYPE_CE) || defined(MSOS_TYPE_LINUX_KERNEL)) ++#if PQ_ENABLE_UNUSED_FUNC ++static MS_PQ_INFO _info = {128, 217}; ++static MS_PQ_RFBL_INFO _stRFBL_Info = {FALSE, FALSE, 0 }; ++#endif ++static MS_PQ_Status _status = {FALSE, FALSE}; ++ ++#else ++static MS_PQ_INFO _info = {.u16Input_Src_Num = 128, .u8IP_Num = 217,}; ++static MS_PQ_Status _status = {.bIsInitialized = FALSE, .bIsRunning = FALSE, }; ++static MS_PQ_RFBL_INFO _stRFBL_Info = {.bEnable = FALSE, .bFilm = FALSE , .u8MADiType = 0, }; ++#endif ++ ++//static BW_INFO_t bw_info; ++ ++ ++#if(ENABLE_PQ_BIN) ++static MS_BOOL gbPQBinEnable = 0; ++MS_PQBin_Header_Info stPQBinHeaderInfo[MAX_PQ_BIN_NUM]; ++extern MS_PQTextBin_Header_Info stPQTextBinHeaderInfo[MAX_PQ_TEXT_BIN_NUM]; ++//extern MS_BOOL gbEnablePQTextBin; ++#endif ++ ++MS_S32 _PQ_Mutex = -1; ++ ++#ifdef MSOS_TYPE_LINUX ++pthread_mutex_t _PQ_MLoad_Mutex; ++#endif ++ ++////////////////////////////////////////////////////////////////// ++// PQ Patch ++MS_BOOL _bOSD_On = FALSE; ++ ++#if PQ_ENABLE_UNUSED_FUNC ++static MS_BOOL bSetFrameCount = TRUE; ++#endif ++ ++#if 0 //def _PDEBUG ++#define PTH_PQ_RET_CHK(_pf_) \ ++ ({ \ ++ int r = _pf_; \ ++ if (r != 0 && r != ETIMEDOUT) \ ++ fprintf(stderr, "[PTHREAD] %s: %d: %s: %s\r\n", __FILE__, __LINE__, #_pf_, strerror(r)); \ ++ r; \ ++ }) ++#else ++#define PTH_PQ_RET_CHK(_pf_) //_pf_ ++#endif ++ ++ ++#ifdef MSOS_TYPE_LINUX ++#define PQ_MLOAD_ENTRY() PTH_PQ_RET_CHK(pthread_mutex_lock(&_PQ_MLoad_Mutex)) ++#define PQ_MLOAD_RETURN() PTH_PQ_RET_CHK(pthread_mutex_unlock(&_PQ_MLoad_Mutex)) ++#else ++#define PQ_MLOAD_ENTRY() ++#define PQ_MLOAD_RETURN() ++#endif ++ ++////////////////////////////////////////////////////////////////// ++// OS related ++// ++// ++#define XC_PQ_WAIT_MUTEX (TICK_PER_ONE_MS * 50) // 50 ms ++ ++/* ++// Mutex & Lock ++static MS_S32 _s32XC_PQMutex = -1; ++ ++ ++#define XC_PQ_ENTRY() { if (_s32XC_PQMutex < 0) { return E_XC_ACE_FAIL; } \ ++ if(OS_OBTAIN_MUTEX(_s32XC_PQMutex, XC_PQ_WAIT_MUTEX) == FALSE) return E_XC_ACE_OBTAIN_MUTEX_FAIL; } ++ ++#define XC_PQ_RETURN(_ret) { OS_RELEASE_MUTEX(_s32XC_PQMutex); return _ret; } ++*/ ++ ++////////////////////////////////////////////////////////////////// ++void _MDrv_PQ_Clear_SRAM_Table_Index(void) ++{ ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Clear_SRAM_Table_Index(); ++ } ++ else ++#endif ++ { ++ MDrv_PQ_ClearTableIndex(MAIN); ++ #if ENABLE_PQ_EX ++ MDrv_PQ_ClearTableIndex(MAINEX); ++ #endif ++ ++ #if PQ_ENABLE_PIP ++ MDrv_PQ_ClearTableIndex(SUB); ++ MDrv_PQ_ClearTableIndex(SUBEX); ++ #endif ++ ++ #if ENABLE_MULTI_SCALER ++ ++ MDrv_PQ_ClearTableIndex(SC1_MAIN); ++ MDrv_PQ_ClearTableIndex(SC1_MAINEX); ++ ++ MDrv_PQ_ClearTableIndex(SC2_MAIN); ++ MDrv_PQ_ClearTableIndex(SC2_MAINEX); ++ MDrv_PQ_ClearTableIndex(SC2_SUB); ++ MDrv_PQ_ClearTableIndex(SC2_SUBEX); ++ #endif ++ } ++} ++ ++MS_BOOL MDrv_PQ_Init(MS_PQ_Init_Info *pstPQInitInfo) ++{ ++ PQTABLE_INFO PQTableInfo; ++#if(ENABLE_PQ_BIN) ++ MS_U8 i; ++ MS_U8 u8ID; ++#endif ++ if(_PQ_Mutex != -1) ++ { ++ printf("%s, already init\n", __FUNCTION__); ++ return TRUE; ++ } ++ ++ _PQ_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "_PQ_Mutex", MSOS_PROCESS_SHARED); ++ ++ if(_PQ_Mutex == -1) ++ { ++ (printf("[MAPI PQ][%06d] create mutex fail\r\n", __LINE__)); ++ return FALSE; ++ } ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTableInfo)); ++ ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ PTH_PQ_RET_CHK(pthread_mutexattr_t attr); ++ PTH_PQ_RET_CHK(pthread_mutexattr_init(&attr)); ++ PTH_PQ_RET_CHK(pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE)); ++ PTH_PQ_RET_CHK(pthread_mutex_init(&_PQ_MLoad_Mutex, &attr)); ++ #endif ++#endif ++ ++ _status.bIsInitialized = TRUE; ++ _status.bIsRunning = TRUE; ++ ++ _MDrv_PQ_Clear_SRAM_Table_Index(); ++ ++#if(ENABLE_PQ_BIN) ++ if(pstPQInitInfo->u8PQTextBinCnt) ++ { ++ //gbEnablePQTextBin = 1; ++ for(i = 0; i < pstPQInitInfo->u8PQTextBinCnt; i++) ++ { ++ #if PQ_ENABLE_UNUSED_FUNC ++ u8ID = pstPQInitInfo->stPQTextBinInfo[i].u8PQID; ++ stPQTextBinHeaderInfo[u8ID].u8BinID = pstPQInitInfo->stPQTextBinInfo[i].u8PQID; ++ #if !defined(MSOS_TYPE_LINUX) && !defined(MSOS_TYPE_LINUX_KERNEL) ++ stPQTextBinHeaderInfo[u8ID].u32BinStartAddress = MS_PA2KSEG0(pstPQInitInfo->stPQTextBinInfo[i].PQBin_PhyAddr); ++ #else ++ stPQTextBinHeaderInfo[u8ID].u32BinStartAddress = /*MS_PA2KSEG0*/(pstPQInitInfo->stPQTextBinInfo[i].PQBin_PhyAddr); ++ #endif ++ if(MDrv_PQTextBin_Parsing(&stPQTextBinHeaderInfo[u8ID]) == FALSE) ++ { ++ printf("MDrv_PQTextBin_Parsing: Parsing Fail, ID=%d \n", i); ++ return FALSE; ++ } ++ #endif ++ } ++ ++ } ++ else ++ { ++ //printf("NonPQBin_Text !!\r\n"); ++ //gbEnablePQTextBin = 0; ++ } ++ ++ if(pstPQInitInfo->u8PQBinCnt) ++ { ++ printf("Start PQ Bin Init \n"); ++ gbPQBinEnable = 1; ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, MAIN_WINDOW); ++ #if PQ_ENABLE_PIP ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SUB_WINDOW); ++ #endif ++ ++ #if ENABLE_MULTI_SCALER ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SC1_MAIN_WINDOW); ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SC2_MAIN_WINDOW); ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, SC2_SUB_WINDOW); ++ #endif ++ ++ switch(pstPQInitInfo->u16PnlWidth) ++ { ++ default: ++ case 1366: ++ MDrv_PQBin_SetPanelID(1, MAIN_WINDOW); ++ #if PQ_ENABLE_PIP ++ MDrv_PQBin_SetPanelID(1, SUB_WINDOW); ++ #endif ++ #if ENABLE_MULTI_SCALER ++ MDrv_PQBin_SetPanelID(1, SC2_MAIN_WINDOW); ++ MDrv_PQBin_SetPanelID(1, SC2_SUB_WINDOW); ++ MDrv_PQBin_SetPanelID(0, SC1_SUB_WINDOW); ++ #endif ++ break; ++ ++ case 1920: ++ MDrv_PQBin_SetPanelID(1, MAIN_WINDOW); ++ #if PQ_ENABLE_PIP ++ MDrv_PQBin_SetPanelID(1, SUB_WINDOW); ++ #endif ++ #if ENABLE_MULTI_SCALER ++ MDrv_PQBin_SetPanelID(1, SC2_MAIN_WINDOW); ++ MDrv_PQBin_SetPanelID(1, SC2_SUB_WINDOW); ++ MDrv_PQBin_SetPanelID(0, SC1_SUB_WINDOW); ++ #endif ++ break; ++ } ++ ++ //because main and sub's common table may be different, ++ //so we will take main's common table as correct one. ++ //so here load sub first and then use main's overwrite sub's ++ //Sub first ++ for(i = 0; i < MAX_PQ_BIN_NUM; i++) ++ { ++ if(pstPQInitInfo->stPQBinInfo[i].PQ_Bin_BufSize > 0) ++ { ++ PQ_WIN ePQWin; ++ u8ID = pstPQInitInfo->stPQBinInfo[i].u8PQID; ++ ePQWin = MDrv_PQBin_TransToPQWin(u8ID); ++ stPQBinHeaderInfo[u8ID].u8BinID = (MS_U8)pstPQInitInfo->stPQBinInfo[i].u8PQID; ++ stPQBinHeaderInfo[u8ID].u32BinStartAddress = (MS_U32)(pstPQInitInfo->stPQBinInfo[i].PQBin_PhyAddr); ++ MDrv_PQBin_Parsing(&stPQBinHeaderInfo[u8ID]); ++ MDrv_PQBin_LoadCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(ePQWin), &stPQBinHeaderInfo[u8ID]); ++ } ++ else ++ { ++ printf("MDrv_PQ_Init() Error: PQ_Bin_BufSize < 0 !! \r\n"); ++ } ++ } ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ //PQTableInfo = PQTableInfo; ++ #if(ENABLE_PQ_BIN) ++ gbPQBinEnable = 1; ++ #endif ++ ++ #else ++ MS_BOOL bSkipCommTable = TRUE; ++ ++ //printf("NonPQBin !! \r\n"); ++ #if(ENABLE_PQ_BIN) ++ gbPQBinEnable = 0; ++ #endif ++ ++ ++ MDrv_PQ_Set_DisplayType_Main(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ #if (PQ_ENABLE_PIP) ++ MDrv_PQ_Set_DisplayType_Sub(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Sub(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Main(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ ++ MDrv_PQ_Set_DisplayType_SC1_Main(pstPQInitInfo->u16PnlWidth, PQ_DISPLAY_ONE, bSkipCommTable); ++ #endif ++ ++ #if(ENABLE_PQ_LOAD_TABLE_INFO) ++ MDrv_PQ_PreInitLoadTableInfo(MAIN); ++ ++ #if ENABLE_PQ_EX ++ MDrv_PQ_PreInitLoadTableInfo(MAINEX); ++ #endif ++ ++ #if PQ_ENABLE_PIP ++ MDrv_PQ_PreInitLoadTableInfo(SUB); ++ MDrv_PQ_PreInitLoadTableInfo(SUBEX); ++ #endif ++ #endif ++ ++ #endif // end of #if(PQ_ONLY_SUPPORT_BIN == 0) ++ ++ } ++ ++#if 0 ++ // Set BK12 [40] [1:0] = b'11 to enable hw double buffer write ++ // at blanking area for changing memory format by L_BK_SCMI(0x02) ++ // this register is added after T2 U04 ++ Hal_PQ_set_memfmt_doublebuffer(PQ_MAIN_WINDOW, ENABLE); ++#if ENABLE_MULTI_SCALER ++ Hal_PQ_set_memfmt_doublebuffer(PQ_SC1_MAIN_WINDOW, ENABLE); ++ Hal_PQ_set_memfmt_doublebuffer(PQ_SC2_MAIN_WINDOW, ENABLE); ++#endif ++ ++ MsOS_Memcpy(&_stPQ_Info, pstPQInitInfo, sizeof(MS_PQ_Init_Info)); ++ ++ MsOS_Memset(&bw_info, 0x00, sizeof(bw_info)); ++ bw_info.bDDR2 = pstPQInitInfo->bDDR2; ++ bw_info.u32DDRFreq = pstPQInitInfo->u32DDRFreq; ++ bw_info.u8BusWidth = pstPQInitInfo->u8BusWidth; ++ bw_info.u16output_vtotal = pstPQInitInfo->u16Pnl_vtotal; ++ bw_info.u16output_hsize = pstPQInitInfo->u16PnlWidth; ++ bw_info.u16OSD_hsize = pstPQInitInfo->u16OSD_hsize; ++ bw_info.u32Miu0MemSize = pstPQInitInfo->u32miu0em_size; ++ bw_info.u32Miu1MemSize = pstPQInitInfo->u32miu1em_size; ++ ++ for(i = 0; i < PQ_MAX_WINDOW; i++) ++ _bColorRange0_255[i] = TRUE; ++#endif ++ ++#if (PQ_ENABLE_PIP) ++ #if (PQ_ONLY_SUPPORT_BIN == 0) ++ genDisplayType = PQ_DISPLAY_ONE; ++ #endif ++#endif ++ ++ return TRUE; ++} ++ ++void MDrv_PQ_DesideSrcType(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType) ++{ ++ _enInputSourceType[eWindow] = enInputSourceType; ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ _u16PQSrcType_DBK_Detect[eWindow] = _u16PQSrcType[eWindow]; //For Auto_DBK SW driver used ++ PQTAB_DBG(printf("[PQ_DesideSrcType] window=%u, enInputSrcType=%u, SrcType=%u\r\n", ++ eWindow, enInputSourceType, _u16PQSrcType[eWindow])); ++ ++ Hal_PQ_set_sourceidx(eWindow, _u16PQSrcType[eWindow]); ++ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(MAIN, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(MAINEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SUB, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SUBEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC1_MAIN, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC1_MAINEX, _u16PQSrcType[eWindow]); ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_MAIN, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_MAINEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_SUB, _u16PQSrcType[eWindow]); ++ MDrv_PQ_Set_LoadTableInfo_SrcType(SC2_SUBEX, _u16PQSrcType[eWindow]); ++ } ++ } ++#endif ++ ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ ++ } ++ ++#endif //#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_Main(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfo.pQuality_Map_Aray = (void*)(QMAP_1920_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_NR_Main: MST_GRule_1920_NR_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_MPEG_NR_Main:MST_GRule_1920_MPEG_NR_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_FILM_MODE_Main:MST_GRule_1920_FILM_MODE_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DYNAMIC_CONTRAST_Main:MST_GRule_1920_DYNAMIC_CONTRAST_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_ULTRAT_CLEAR_Main:MST_GRule_1920_ULTRAT_CLEAR_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DDR_SELECT_Main:MST_GRule_1920_DDR_SELECT_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_OSD_BW_Main:MST_GRule_1920_OSD_BW_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PTP_Main:MST_GRule_1920_PTP_Main); ++#endif ++ break; ++#if PQ_ENABLE_PIP ++ case PQ_DISPLAY_PIP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_PIP_Main: QMAP_1920_PIP_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_NR_Main: MST_GRule_1920_PIP_NR_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_MPEG_NR_Main:MST_GRule_1920_PIP_MPEG_NR_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_FILM_MODE_Main:MST_GRule_1920_PIP_FILM_MODE_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DYNAMIC_CONTRAST_Main:MST_GRule_1920_PIP_DYNAMIC_CONTRAST_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_ULTRAT_CLEAR_Main:MST_GRule_1920_PIP_ULTRAT_CLEAR_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DDR_SELECT_Main:MST_GRule_1920_PIP_DDR_SELECT_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_OSD_BW_Main:MST_GRule_1920_PIP_OSD_BW_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_PTP_Main:MST_GRule_1920_PIP_PTP_Main); ++#endif ++ ++ break; ++ ++ case PQ_DISPLAY_POP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_POP_Main: QMAP_1920_POP_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_NR_Main: MST_GRule_1920_POP_NR_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_MPEG_NR_Main:MST_GRule_1920_POP_MPEG_NR_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_FILM_MODE_Main:MST_GRule_1920_POP_FILM_MODE_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DYNAMIC_CONTRAST_Main:MST_GRule_1920_POP_DYNAMIC_CONTRAST_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_ULTRAT_CLEAR_Main:MST_GRule_1920_POP_ULTRAT_CLEAR_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DDR_SELECT_Main:MST_GRule_1920_POP_DDR_SELECT_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_OSD_BW_Main:MST_GRule_1920_POP_OSD_BW_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_PTP_Main:MST_GRule_1920_POP_PTP_Main); ++#endif ++ break; ++#endif ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_MAIN_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Main; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_Main; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Main; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_Main; ++ ++#if PQ_ENABLE_HSDRULE ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_Main; ++#endif ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_Main; ++#if PQ_ENABLE_CSCRULE ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_Main; ++#endif ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_Main; ++#endif ++ ++#if (PQ_ENABLE_HSDRULE) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_Main; ++#endif ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_Main; ++#if (PQ_ENABLE_CSCRULE) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_Main; ++#endif ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_Main; ++#endif ++ ++#if (PQ_ENABLE_HSDRULE) ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_Main; ++#endif ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_Main; ++ ++#if (PQ_ENABLE_CSCRULE) ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_Main; ++#endif ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_Main; ++#endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_Main; ++#endif ++ ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_Main; ++#endif ++ ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_Main; ++#endif ++ ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_Main; ++#endif ++ ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_Main; ++#endif ++ ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_Main; ++#endif ++ ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_Main; ++#endif ++ ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_PTP] = PQ_GRULE_PTP_NUM_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_PTP] = PQ_GRULE_PTP_IP_NUM_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_PTP] = (void*)MST_GRule_PTP_IP_Index_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_PTP] = (void*)MST_GRule_PTP_Main; ++#endif ++ ++ MDrv_PQ_AddTable_(MAIN, &PQTableInfo); ++ ++ if(!bSkipCommTable) ++ { ++#if (PQ_ENABLE_UNUSED_FUNC) ++ MDrv_PQ_LoadCommTable_(MAIN); ++#endif ++ } ++ ++#if (ENABLE_PQ_EX) ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Main_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_Main_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Main_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_Main_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Main_Ex; ++ break; ++ ++ case PQ_DISPLAY_PIP: ++#if PQ_ENABLE_PIP ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Main_Ex; ++#endif ++ break; ++ ++ case PQ_DISPLAY_POP: ++#if PQ_ENABLE_PIP ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Main_Ex; ++#endif ++ break; ++ } ++ ++ MDrv_PQ_AddTable_(MAINEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(MAINEX); ++ } ++ if((MS_U16)QM_INPUTTYPE_NUM_Main != (MS_U16)QM_INPUTTYPE_NUM_Main_Ex) ++ { ++ printf("PQ INPUTTYPE NUM MISMATCH: MAIN != EX"); ++ MS_ASSERT(0); ++ } ++#endif ++ return TRUE; ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++#endif ++} ++ ++void MDRv_PQ_Check_Type(PQ_WIN eWindow, PQ_CHECK_TYPE EnCheck) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ MDrv_PQ_Check_Type_(MAIN, EnCheck); ++ ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MDRv_PQ_Set_CmdqCfg(PQ_WIN eWindow, MS_BOOL bEnCMDQ, MS_U8 u8FmCnt,MS_BOOL bFire) ++{ ++ PQ_DBG(printf("%s %d, Win:%d, CMDQEn:%d, FmCnt:%d", __FUNCTION__, __LINE__, eWindow, bEnCMDQ, u8FmCnt)); ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ PQ_CMDQ_CONFIG CmdqCfg; ++ ++ CmdqCfg.bEnFmCnt = bEnCMDQ; ++ CmdqCfg.u8FmCnt = u8FmCnt; ++ CmdqCfg.bfire = bFire; ++ MDrv_PQ_Set_CmdqCfg_(MAIN, CmdqCfg); ++ ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++} ++void MDrv_PQ_init_RIU(MS_U32 riu_addr) ++{ ++ Hal_PQ_init_riu_base(riu_addr); ++} ++MS_U16 MDrv_PQ_GetIPRegCount(MS_U16 u16PQIPIdx) ++{ ++ ++ return MDrv_PQ_GetIPRegCount_(MAIN,_u16PQSrcType[0], (MS_U8)u16PQIPIdx); ++} ++void MDrv_PQ_LoadSettingByData(PQ_WIN eWindow, MS_U8 u8PQIPIdx, MS_U8 *pData, MS_U16 u16DataSize) ++{ ++ PQ_DBG(printf("%s %d, Win:%d, IPIdx:%d, Size%d \n", __FUNCTION__, __LINE__, eWindow, u8PQIPIdx, u16DataSize)); ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ } ++ else ++#endif ++ { ++ PQ_DATA_INFO DataInfo; ++ ++ DataInfo.pBuf = pData; ++ DataInfo.u16BufSize = u16DataSize; ++ MDrv_PQ_LoadTableByData_(MAIN, _u16PQSrcType[eWindow], u8PQIPIdx, &DataInfo); ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++} ++ ++ ++void MDrv_PQ_LoadSettings(PQ_WIN eWindow) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_MAIN]); ++ ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("MAIN table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#if(ENABLE_PQ_EX == 1) ++ PQTAB_DBG(printf("MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, MDrv_PQ_GetTableIndex(eWindow, PQ_IP_UC_CTL_Main), PQ_IP_UC_CTL_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SUB table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ ++ PQTAB_DBG(printf("SUB MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SC1_MAIN]); ++ ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SC1_MAIN table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC1_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#if(ENABLE_PQ_EX == 1) ++ PQTAB_DBG(printf("SC2_MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC1_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, MDrv_PQ_GetTableIndex(eWindow, PQ_IP_UC_CTL_SC1_Main), PQ_IP_UC_CTL_SC1_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SC2_MAIN]); ++ ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SC2_MAIN table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#if(ENABLE_PQ_EX == 1) ++ PQTAB_DBG(printf("SC2_MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, MDrv_PQ_GetTableIndex(eWindow, PQ_IP_UC_CTL_SC2_Main), PQ_IP_UC_CTL_SC2_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ ++ MDrv_PQBin_LoadTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_EXT_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ PQTAB_DBG(printf("SC2_SUB table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ ++ PQTAB_DBG(printf("SC2_SUB MAINEX table\r\n")); ++ MDrv_PQ_LoadTableBySrcType_(SC2_SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ PQTAB_DBG(printf("...done\r\n")); ++#endif ++ } ++ } ++#endif ++ ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_MAIN); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_MAIN_EX); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SUB); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SUB_EX); ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC1_MAIN); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC1_MAIN_EX); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_MAIN); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_MAIN_EX); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_SUB); ++ MDRV_PQ_PrintLoadTableInfo(PQ_LOAD_TABLE_SC2_SUB_EX); ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++#endif ++} ++ ++#if (PQ_ENABLE_UNUSED_FUNC) ++ ++MS_BOOL MDrv_PQ_Exit(void) ++{ ++ _MDrv_PQ_Clear_SRAM_Table_Index(); ++ return true; ++} ++ ++MS_U16 MDrv_PQ_GetIPNum(PQ_WIN eWindow) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(MAIN); ++#endif ++ } ++ } ++ ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SUB); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ // SC1_MAIN ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SC1_MAIN); ++#endif ++ } ++ } ++ // SC2_MAIN ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SC2_MAIN); ++#endif ++ } ++ } ++ // SC2_SUB ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetIPNum(&stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetIPNum_(SC2_SUB); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ ++ else ++ { ++ MS_ASSERT(0); ++ return 0xFFFF; ++ } ++} ++ ++MS_U16 MDrv_PQ_GetTableNum(PQ_WIN eWindow, MS_U16 u16PQIPIdx) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ UNUSED(u16PQIPIdx); ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ UNUSED(u16PQIPIdx); ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SC1_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ UNUSED(u16PQIPIdx); ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SC2_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetTableNum((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetTableNum_(SC2_SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++#endif //ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ return 0xFFFF; ++ } ++} ++ ++MS_U16 MDrv_PQ_GetCurrentTableIndex(PQ_WIN eWindow, MS_U16 u16PQIPIdx) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), u16PQIPIdx, PQ_BIN_STD_MAIN); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), u16PQIPIdx, PQ_BIN_STD_SUB); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), u16PQIPIdx, PQ_BIN_STD_SC1_MAIN); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SC1_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), u16PQIPIdx, PQ_BIN_STD_SC2_MAIN); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SC2_MAIN, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ return MDrv_PQBin_GetCurrentTableIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), u16PQIPIdx, PQ_BIN_STD_SC2_SUB); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ return 0xFFFF; ++#else ++ return MDrv_PQ_GetCurrentTableIndex_(SC2_SUB, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ return 0xFFFF; ++ } ++} ++ ++//Get main page setting from u16IPIdx(column), according to current input source type(row) ++MS_U16 MDrv_PQ_GetTableIndex(PQ_WIN eWindow, MS_U16 u16IPIdx) ++{ ++ MS_U8 u16TabIdx = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(MAIN, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SUB, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SC1_MAIN, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SC2_MAIN, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = (MS_U8)MDrv_PQBin_GetTableIndex(_u16PQSrcType[eWindow], ++ u16IPIdx, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = (MS_U8)MDrv_PQ_GetTableIndex_(SC2_SUB, _u16PQSrcType[eWindow], (MS_U8)u16IPIdx); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16TabIdx; ++} ++ ++static MS_U16 MDrv_PQ_GetXRuleIPIndex(PQ_WIN eWindow, MS_U16 u16XRuleType, MS_U16 u16XRuleIP) ++{ ++ MS_U8 u16IPIdx = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SC1_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SC2_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPIdx = (MS_U8)MDrv_PQBin_GetXRuleIPIndex(u16XRuleType, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPIdx = 0; ++#else ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex_(SC2_SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16IPIdx; ++} ++ ++static MS_U16 MDrv_PQ_GetXRuleTableIndex(PQ_WIN eWindow, MS_U16 u16XRuleType, MS_U16 u16XRuleIdx, MS_U16 u16XRuleIP) ++{ ++ MS_U16 u16TabIdx = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SC1_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SC2_MAIN, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16TabIdx = MDrv_PQBin_GetXRuleTableIndex(u16XRuleType, ++ u16XRuleIdx, ++ u16XRuleIP, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16TabIdx = 0; ++#else ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex_(SC2_SUB, (MS_U8)u16XRuleType, (MS_U8)u16XRuleIdx, (MS_U8)u16XRuleIP); ++#endif ++ } ++ } ++#endif ++ ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16TabIdx; ++} ++ ++static MS_U16 MDrv_PQ_GetXRuleIPNum(PQ_WIN eWindow, MS_U16 u16XRuleType) ++{ ++ MS_U16 u16IPNum = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(MAIN, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SUB, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SC1_MAIN, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SC2_MAIN, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16IPNum = MDrv_PQBin_GetXRuleIPNum(u16XRuleType, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16IPNum = 0; ++#else ++ u16IPNum = MDrv_PQ_GetXRuleIPNum_(SC2_SUB, (MS_U8)u16XRuleType); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16IPNum; ++} ++ ++#if (PQ_GRULE_NR_ENABLE || PQ_GRULE_OSD_BW_ENABLE) ++static MS_U16 MDrv_PQ_GetGRule_LevelIndex(PQ_WIN eWindow, MS_U16 u16GRuleType, MS_U16 u16GRuleLevelIndex) ++{ ++ MS_U16 u16Ret = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SC1_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SC2_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_LevelIndex((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ u16GRuleType, ++ u16GRuleLevelIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_LevelIndex_(SC2_SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleLevelIndex); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ return u16Ret; ++} ++ ++static MS_U16 MDrv_PQ_GetGRule_IPIndex(PQ_WIN eWindow, MS_U16 u16GRuleType, MS_U16 u16GRuleIPIndex) ++{ ++ MS_U16 u16Ret = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SC1_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SC2_MAIN, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = MDrv_PQBin_GetGRule_IPIndex(u16GRuleType, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = MDrv_PQ_GetGRule_IPIndex_(SC2_SUB, (MS_U8)u16GRuleType, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++ return u16Ret; ++} ++ ++static MS_U16 MDrv_PQ_GetGRule_TableIndex(PQ_WIN eWindow, MS_U16 u16GRuleType, MS_U16 u16PQ_NRIdx, MS_U16 u16GRuleIPIndex) ++{ ++ MS_U16 u16Ret = 0; ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)MDrv_PQ_GetGRule_TableIndex_(MAIN, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)(MDrv_PQ_GetGRule_TableIndex_(SUB, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex)); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)MDrv_PQ_GetGRule_TableIndex_(SC1_MAIN, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)MDrv_PQ_GetGRule_TableIndex_(SC2_MAIN, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ u16Ret = (MS_U8) MDrv_PQBin_GetGRule_TableIndex(u16GRuleType, ++ _u16PQSrcType[eWindow], ++ u16PQ_NRIdx, ++ u16GRuleIPIndex, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN) ++ u16Ret = 0; ++#else ++ u16Ret = (MS_U8)(MDrv_PQ_GetGRule_TableIndex_(SC2_SUB, (MS_U8)u16GRuleType, (MS_U8)_u16PQSrcType[eWindow], (MS_U8)u16PQ_NRIdx, (MS_U8)u16GRuleIPIndex)); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++ return u16Ret; ++} ++#endif ++ ++ ++void MDrv_PQ_LoadTableData(PQ_WIN eWindow, MS_U16 u16TabIdx, MS_U16 u16PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SC1_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SC2_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTableData((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB], ++ pTable, ++ u16TableSize); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTableData_(SC2_SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx, pTable, u16TableSize); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MDrv_PQ_LoadTable(PQ_WIN eWindow, MS_U16 u16TabIdx, MS_U16 u16PQIPIdx) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SC1_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SC2_MAIN, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_LoadTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ u16TabIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_LoadTable_(SC2_SUB, (MS_U8)u16TabIdx, (MS_U8)u16PQIPIdx); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++void MDrv_PQ_CheckSettings(PQ_WIN eWindow) ++{ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo MAINEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if(ENABLE_PQ_EX) ++ MDrv_PQ_CheckCommTable_(MAINEX); ++ MDrv_PQ_CheckTableBySrcType_(MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ MDrv_PQ_CheckCommTable_(MAIN); ++ MDrv_PQ_CheckTableBySrcType_(MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo SUBEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_CheckCommTable_(SUBEX); ++ MDrv_PQ_CheckTableBySrcType_(SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ MDrv_PQ_CheckCommTable_(SUB); ++ MDrv_PQ_CheckTableBySrcType_(SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo MAINEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC1_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC1_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if(ENABLE_PQ_EX) ++ MDrv_PQ_CheckCommTable_(SC1_MAINEX); ++ MDrv_PQ_CheckTableBySrcType_(SC1_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ MDrv_PQ_CheckCommTable_(SC1_MAIN); ++ MDrv_PQ_CheckTableBySrcType_(SC1_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++ ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo MAINEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_MAIN_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_MAIN]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if(ENABLE_PQ_EX) ++ MDrv_PQ_CheckCommTable_(SC2_MAINEX); ++ MDrv_PQ_CheckTableBySrcType_(SC2_MAINEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ MDrv_PQ_CheckCommTable_(SC2_MAIN); ++ MDrv_PQ_CheckTableBySrcType_(SC2_MAIN, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ //ToDo SUBEX ++ MDrv_PQBin_CheckCommTable((MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ ++ MDrv_PQBin_CheckTableBySrcType(_u16PQSrcType[eWindow], ++ PQ_BIN_IP_ALL, ++ (MS_U16)MDrv_PQBin_GetPanelIdx(PQ_SC2_SUB_WINDOW), ++ &stPQBinHeaderInfo[PQ_BIN_STD_SC2_SUB]); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_CheckCommTable_(SC2_SUBEX); ++ MDrv_PQ_CheckTableBySrcType_(SC2_SUBEX, _u16PQSrcType[eWindow], PQ_IP_ALL); ++ MDrv_PQ_CheckCommTable_(SC2_SUB); ++ MDrv_PQ_CheckTableBySrcType_(SC2_SUB, _u16PQSrcType[eWindow], PQ_IP_ALL); ++#endif ++ } ++ } ++#endif ++ ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++ ++ ++#if(ENABLE_PQ_MLOAD) ++void MDrv_PQ_Set_MLoadEn(PQ_WIN eWindow, MS_BOOL bEn) ++{ ++ if(MApi_XC_MLoad_GetStatus(eWindow) != E_MLOAD_ENABLED) ++ { ++ bEn = FALSE; ++ } ++ ++ if(bEn) ++ { ++ PQ_MLOAD_ENTRY(); ++ } ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(MAIN, bEn); ++#endif ++ } ++ ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SUB, bEn); ++#endif ++ } ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SC1_MAIN, bEn); ++#endif ++ } ++ ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SC2_MAIN, bEn); ++#endif ++ } ++ ++ } ++#if (PQ_ENABLE_PIP) ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ MDrv_PQBin_Set_MLoadEn(bEn); ++ } ++ else ++#endif ++ { ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ MDrv_PQ_Set_MLoadEn_(SC2_SUB, bEn); ++#endif ++ } ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ MS_ASSERT(0); ++ } ++ ++ ++ if(bEn == FALSE) ++ { ++ PQ_MLOAD_RETURN(); ++ } ++} ++#endif ++ ++ ++ ++void MDrv_PQ_Set_DTVInfo(PQ_WIN eWindow, MS_PQ_Dtv_Info *pstPQDTVInfo) ++{ ++ MsOS_Memcpy(&_stDTV_Info[eWindow], pstPQDTVInfo, sizeof(MS_PQ_Dtv_Info)); ++ ++ PQINFO_DBG(printf("PQ DTV Info:Win=%u, type=%u\r\n", eWindow, _stDTV_Info[eWindow].eType)); ++} ++ ++void MDrv_PQ_Set_MultiMediaInfo(PQ_WIN eWindow, MS_PQ_MuliMedia_Info *pstPQMMInfo) ++{ ++ MsOS_Memcpy(&_stMultiMedia_Info[eWindow], pstPQMMInfo, sizeof(MS_PQ_MuliMedia_Info)); ++ PQINFO_DBG(printf("PQ MM Info:Win=%u, type=%u\r\n", eWindow, _stMultiMedia_Info[eWindow].eType)); ++} ++ ++void MDrv_PQ_Set_VDInfo(PQ_WIN eWindow, MS_PQ_Vd_Info *pstPQVDInfo) ++{ ++ MsOS_Memcpy(&_stVD_Info[eWindow], pstPQVDInfo, sizeof(MS_PQ_Vd_Info)); ++ ++ PQINFO_DBG(printf("PQ VD Info:Win=%u, SigType=%u, bSCARTRGB=%u, VIFIn=%u\r\n", ++ eWindow, ++ _stVD_Info[eWindow].enVideoStandard, ++ _stVD_Info[eWindow].bIsSCART_RGB, ++ _stVD_Info[eWindow].bIsVIFIN)); ++ ++} ++ ++void MDrv_PQ_Set_ModeInfo(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info *pstPQModeInfo) ++{ ++ ++ MsOS_Memcpy(&_stMode_Info[eWindow], pstPQModeInfo, sizeof(MS_PQ_Mode_Info)); ++ ++ //printf("PQ Set Mode Info: %s, Src=%x\r\n", (eWindow)?("SubWin"):("MainWin"), enInputSourceType); ++ ++ if(QM_IsSourceYPbPr(enInputSourceType)) ++ { ++ if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 720))) && ++ (pstPQModeInfo->u16input_vsize < 500) && ++ (pstPQModeInfo->u16input_vfreq < 650)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x480_60I : ++ PQ_MD_720x480_60P; ++ ++ } ++ else if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 720)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 720))) && ++ (pstPQModeInfo->u16input_vsize < 600) && ++ (pstPQModeInfo->u16input_vfreq < 550)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x576_50I : ++ PQ_MD_720x576_50P; ++ } ++ else if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 1280)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 1280)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 1280)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 1280))) && ++ (pstPQModeInfo->u16input_vsize < 800) && ++ (pstPQModeInfo->bInterlace == FALSE)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1280x720_50P : ++ PQ_MD_1280x720_60P; ++ ++ } ++ else if(((QM_H_Size_Check_x1(pstPQModeInfo->u16input_hsize, 1920)) || ++ (QM_H_Size_Check_x2(pstPQModeInfo->u16input_hsize, 1920)) || ++ (QM_H_Size_Check_x4(pstPQModeInfo->u16input_hsize, 1920)) || ++ (QM_H_Size_Check_x8(pstPQModeInfo->u16input_hsize, 1920))) && ++ (pstPQModeInfo->u16input_vsize < 1100)) ++ { ++ if(pstPQModeInfo->bInterlace) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1920x1080_50I : ++ PQ_MD_1920x1080_60I; ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 245) ? PQ_MD_1920x1080_24P : ++ (pstPQModeInfo->u16input_vfreq < 270) ? PQ_MD_1920x1080_25P : ++ (pstPQModeInfo->u16input_vfreq < 350) ? PQ_MD_1920x1080_30P : ++ (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1920x1080_50P : ++ PQ_MD_1920x1080_60P; ++ ++ } ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = PQ_MD_720x576_50I; ++ } ++ } ++ else if(QM_IsSourceHDMI(enInputSourceType)) ++ { ++ if((pstPQModeInfo->u16input_hsize < 1500) && ++ (pstPQModeInfo->u16input_vsize < 500) && ++ (pstPQModeInfo->u16input_vfreq < 650)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x480_60I : ++ PQ_MD_720x480_60P; ++ ++ } ++ else if((pstPQModeInfo->u16input_hsize < 1500) && ++ (pstPQModeInfo->u16input_vsize < 600) && ++ (pstPQModeInfo->u16input_vfreq < 550)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->bInterlace) ? ++ PQ_MD_720x576_50I : ++ PQ_MD_720x576_50P; ++ } ++ else if((pstPQModeInfo->u16input_hsize < 1300) && ++ (pstPQModeInfo->u16input_vsize < 800) && ++ (pstPQModeInfo->bInterlace == FALSE)) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1280x720_50P : ++ PQ_MD_1280x720_60P; ++ ++ } ++ else if((pstPQModeInfo->u16input_hsize < 1930) && ++ (pstPQModeInfo->u16input_vsize < 1100)) ++ { ++ if(pstPQModeInfo->bInterlace) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1920x1080_50I : ++ PQ_MD_1920x1080_60I; ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 245) ? PQ_MD_1920x1080_24P : ++ (pstPQModeInfo->u16input_vfreq < 270) ? PQ_MD_1920x1080_25P : ++ (pstPQModeInfo->u16input_vfreq < 350) ? PQ_MD_1920x1080_30P : ++ (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1920x1080_50P : ++ PQ_MD_1920x1080_60P; ++ ++ } ++ } ++ else if(pstPQModeInfo->u16input_hsize < 1350 && ++ pstPQModeInfo->u16input_vsize < 1550) ++ { ++ //special handle 1280X1470p ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1280x720_50P : ++ PQ_MD_1280x720_60P; ++ } ++ } ++ else if(pstPQModeInfo->u16input_hsize < 1930 && ++ pstPQModeInfo->u16input_vsize < 2300) ++ { ++ //special handle 1920X2205p ++ if(pstPQModeInfo->bInterlace) ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 550) ? ++ PQ_MD_1920x1080_50I : ++ PQ_MD_1920x1080_60I; ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = (pstPQModeInfo->u16input_vfreq < 250) ? PQ_MD_1920x1080_24P : ++ (pstPQModeInfo->u16input_vfreq < 350) ? PQ_MD_1920x1080_30P : ++ (pstPQModeInfo->u16input_vfreq < 550) ? PQ_MD_1920x1080_50P : ++ PQ_MD_1920x1080_60P; ++ ++ } ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = PQ_MD_720x576_50I; ++ } ++ } ++ else ++ { ++ _u8ModeIndex[eWindow] = PQ_MD_Num; ++ } ++ ++ if(QM_IsSourceYPbPr(enInputSourceType) || QM_IsSourceHDMI(enInputSourceType)) ++ { ++ if(_u8ModeIndex[eWindow] <= (MS_U8)PQ_MD_720x576_50P) ++ _gIsSrcHDMode[eWindow] = 0; ++ else ++ _gIsSrcHDMode[eWindow] = 1; ++ ++ } ++ else ++ { ++ if(pstPQModeInfo->u16input_hsize >= 1200) ++ _gIsSrcHDMode[eWindow] = 1; ++ else ++ _gIsSrcHDMode[eWindow] = 0; ++ } ++ ++ PQINFO_DBG( ++ printf("PQ ModeInfo:%d input(%d, %d), disp(%d, %d), ModeIdx=%d, FBL=%u, Interlace=%u, InV=%u, OutV=%u, inVtt=%u\r\n", ++ eWindow, ++ _stMode_Info[eWindow].u16input_hsize, ++ _stMode_Info[eWindow].u16input_vsize, ++ _stMode_Info[eWindow].u16display_hsize, ++ _stMode_Info[eWindow].u16display_vsize, ++ _u8ModeIndex[eWindow], ++ _stMode_Info[eWindow].bFBL, ++ _stMode_Info[eWindow].bInterlace, ++ _stMode_Info[eWindow].u16input_vfreq, ++ _stMode_Info[eWindow].u16ouput_vfreq, ++ _stMode_Info[eWindow].u16input_vtotal); ++ ); ++ ++} ++ ++void MDrv_PQ_SetHDMIInfo(PQ_WIN eWindow, const MS_PQ_Hdmi_Info* const pstPQHDMIInfo) ++{ ++ _stHDMI_Info[eWindow].bIsHDMI = pstPQHDMIInfo->bIsHDMI; ++ _stHDMI_Info[eWindow].enColorFmt = pstPQHDMIInfo->enColorFmt; ++ ++ PQINFO_DBG(printf("PQ HDMI, bHDMI=%u, colorfmt=%u\r\n", ++ _stHDMI_Info[eWindow].bIsHDMI, ++ _stHDMI_Info[eWindow].enColorFmt)); ++} ++ ++void MDrv_PQ_SetHDMI_PC(PQ_WIN eWindow, MS_BOOL bIsTrue) ++{ ++ _stHDMI_Info[eWindow].bIsHDMIPC = bIsTrue; ++} ++ ++MS_BOOL MDrv_PQ_GetHDMI_PC_Status(PQ_WIN eWindow) ++{ ++ return _stHDMI_Info[eWindow].bIsHDMIPC; ++} ++ ++ ++ ++PQ_INPUT_SOURCE_TYPE MDrv_PQ_GetInputSourceType(PQ_WIN eWindow) ++{ ++ return _enInputSourceType[eWindow]; ++} ++ ++MS_U16 MDrv_PQ_GetSrcType(PQ_WIN eWindow) ++{ ++ return _u16PQSrcType[eWindow]; ++} ++ ++// if not HSD case, ignore return value ++static MS_BOOL _MDrv_PQ_LoadScalingTable(PQ_WIN eWindow, ++ MS_U8 eXRuleType, ++ MS_U8 u8XRuleIP, ++ MS_BOOL bPreV_ScalingDown, ++ MS_BOOL bInterlace, ++ MS_BOOL bColorSpaceYUV, ++ MS_U16 u16InputSize, ++ MS_U16 u16SizeAfterScaling) ++{ ++ MS_U32 u32Ratio; ++ MS_U16 u16IPIdx; ++#if(ENABLE_PQ_BIN) ++ MS_U16 u16TabIdx = gbPQBinEnable == 0 ? PQ_IP_NULL : PQ_BIN_IP_NULL; ++#else ++ MS_U16 u16TabIdx = PQ_IP_NULL; ++#endif ++ MS_U8 u8XRuleIdx = 0xFF; ++ ++ if(u16InputSize == 0) ++ u32Ratio = 2000; ++ else ++ u32Ratio = ((MS_U32) u16SizeAfterScaling * 1000) / u16InputSize; ++ ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex(eWindow, eXRuleType, u8XRuleIP); ++ ++ SRULE_DBG(printf("XRuleIP=%d, IPIdx=%d, input=%d, output=%d, ratio=%ld, \r\n", ++ (MS_U16)u8XRuleIP, (MS_U16)u16IPIdx, ++ u16InputSize, u16SizeAfterScaling, u32Ratio)); ++ ++#if PQ_ENABLE_HSDRULE ++ if(bPreV_ScalingDown && bInterlace) ++ { ++ u8XRuleIdx = PQ_HSDRule_PreV_ScalingDown_Interlace_Main; ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, (MS_U16)eXRuleType, (MS_U16)u8XRuleIdx, (MS_U16)u8XRuleIP); ++ } ++ else if(bPreV_ScalingDown && (!bInterlace)) ++ { ++ u8XRuleIdx = PQ_HSDRule_PreV_ScalingDown_Progressive_Main; ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, (MS_U16)eXRuleType, (MS_U16)u8XRuleIdx, (MS_U16)u8XRuleIP); ++ } ++#endif ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 0) && (u16TabIdx != PQ_IP_NULL)) || ++ ((gbPQBinEnable == 1) && (u16TabIdx != PQ_BIN_IP_NULL))) ++#else ++ if(u16TabIdx != PQ_IP_NULL) ++#endif ++ { ++ ++ SRULE_DBG(printf("u8XRuleIdx: PreV down, interlace:%u", bInterlace)); ++ SRULE_DBG(printf("(a)tabidx=%u\r\n", (MS_U16)u16TabIdx)); ++ } ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TabIdx == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TabIdx == PQ_IP_NULL))) ++#else ++ if(u16TabIdx == PQ_IP_NULL) ++#endif ++ { ++ if(u32Ratio > 1000) ++ { ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ SRULE_DBG(printf("u8XRuleIdx: >x1, ")); ++ SRULE_DBG(printf("(c)tabidx=%u\r\n", (MS_U16)u16TabIdx)); ++ } ++ else ++ { ++ ++ #if PQ_ENABLE_HSDRULE ++ if(bColorSpaceYUV) ++ { ++ if(u32Ratio == 1000) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_10x_YUV_Main; ++ else if(u32Ratio >= 900) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_09x_YUV_Main; ++ else if(u32Ratio >= 800) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_08x_YUV_Main; ++ else if(u32Ratio >= 700) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_07x_YUV_Main; ++ else if(u32Ratio >= 600) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_06x_YUV_Main; ++ else if(u32Ratio >= 500) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_05x_YUV_Main; ++ else if(u32Ratio >= 400) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_04x_YUV_Main; ++ else if(u32Ratio >= 300) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_03x_YUV_Main; ++ else if(u32Ratio >= 200) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_02x_YUV_Main; ++ else if(u32Ratio >= 100) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_01x_YUV_Main; ++ else ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_00x_YUV_Main; ++ } ++ else ++ { ++ if(u32Ratio == 1000) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_10x_RGB_Main; ++ else if(u32Ratio >= 900) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_09x_RGB_Main; ++ else if(u32Ratio >= 800) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_08x_RGB_Main; ++ else if(u32Ratio >= 700) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_07x_RGB_Main; ++ else if(u32Ratio >= 600) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_06x_RGB_Main; ++ else if(u32Ratio >= 500) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_05x_RGB_Main; ++ else if(u32Ratio >= 400) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_04x_RGB_Main; ++ else if(u32Ratio >= 300) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_03x_RGB_Main; ++ else if(u32Ratio >= 200) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_02x_RGB_Main; ++ else if(u32Ratio >= 100) ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_01x_RGB_Main; ++ else ++ u8XRuleIdx = PQ_HSDRule_ScalingDown_00x_RGB_Main; ++ } ++ #endif ++ SRULE_DBG(printf("u8XRuleIdx=%u, ", (MS_U16)u8XRuleIdx)); ++ if(u8XRuleIdx == 0xFF) ++ { ++ MS_ASSERT(0); ++ return 1; ++ } ++ ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, (MS_U16)eXRuleType, (MS_U16)u8XRuleIdx, (MS_U16)u8XRuleIP); ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TabIdx == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TabIdx == PQ_IP_NULL))) ++#else ++ if(u16TabIdx == PQ_IP_NULL) ++#endif ++ { ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ SRULE_DBG(printf("(d)tabidx=%u\r\n", u16TabIdx)); ++ } ++ else ++ { ++ SRULE_DBG(printf("(e)tabidx=%u\r\n", u16TabIdx)); ++ } ++ } ++ } ++ ++#if PQ_EN_DMS_SW_CTRL ++ // App will call halt_subwin to disconnet sub window. ++ // It will casue PQ display type to be PQ_DISPLAY_ONE. ++ // But, sub window is still on and DMS_LV_12 will be set ++ // to On in HSD rulee for main window. ++ // For fix this issue, we need to check sub window wheter ++ // on or off to descide DMS_LV_12 off or on. ++ ++ //Disable DMS_V12_L ++ // 1.VSD : V prescaling, 2. PIP, 3. FBL ++ if((((eXRuleType == E_XRULE_VSD)&&(bPreV_ScalingDown)) ++ ||_stMode_Info[eWindow].bFBL ++ || (E_XC_3D_INPUT_MODE_NONE != MApi_XC_Get_3D_Input_Mode(MAIN_WINDOW)) ++ ) && (PQ_IP_DMS_V_12L_Main == MDrv_PQ_GetXRuleIPIndex(eWindow, eXRuleType, u8XRuleIP)) ++ ) ++ { ++ //Disable De-Mosquito ++ u16TabIdx = PQ_IP_DMS_V_12L_OFF_Main; ++ } ++ #endif ++ ++ SRULE_DBG(printf("LoadScalingTable: TabIdx:%d IPIdx:%d \r\n", u16TabIdx, u16IPIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ ++#if PQ_ENABLE_HSDRULE ++ ++ if(eXRuleType == E_XRULE_VSD) ++ return (u16TabIdx == PQ_IP_VSD_Bilinear_Main) ; // PreVSDMode: 0:Cb, 1:Bilinear ++ else ++ return (u16TabIdx != PQ_IP_HSD_Y_CB_Main); // PreHSDMode - 0:Cb, 1:Adv ++#else ++ ++ return 1; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_LoadScalingTable(PQ_WIN eWindow, ++ MS_U8 eXRuleType, ++ MS_BOOL bPreV_ScalingDown, ++ MS_BOOL bInterlace, ++ MS_BOOL bColorSpaceYUV, ++ MS_U16 u16InputSize, ++ MS_U16 u16SizeAfterScaling) ++{ ++ MS_BOOL bRet = 0; // default is CB mode ++ MS_U16 i; ++ ++ if(eXRuleType > 3) ++ MS_ASSERT(0); ++ ++ SRULE_DBG(printf("[PQ_LoadScalingTable] HSD/VSD/HSP/VSP:%u\r\n", (MS_U16)eXRuleType)); ++ SRULE_DBG(printf("Pre_ScalingDown:%d, bInter:%d, bYUV:%d \r\n", bPreV_ScalingDown, bInterlace, bColorSpaceYUV)); ++ ++ for(i = 0; i < MDrv_PQ_GetXRuleIPNum(eWindow, (MS_U16)eXRuleType); i++) ++ { ++ MS_BOOL bSDMode; ++ bSDMode = _MDrv_PQ_LoadScalingTable(eWindow, ++ eXRuleType, ++ (MS_U8)i, ++ bPreV_ScalingDown, ++ bInterlace, ++ bColorSpaceYUV, ++ u16InputSize, ++ u16SizeAfterScaling); ++ bRet |= (bSDMode << (1 * i)); ++ } ++ ++ if(eXRuleType == E_XRULE_VSD) ++ { ++ bRet &= 0x01; ++ } ++#if 0 ++ //121 filter ++ if(((MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_LINE_ALTERNATIVE) || ++ (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_TOP_BOTTOM)) && ++ (MApi_XC_Get_3D_HW_Version() > 0)) ++ { ++ if((u16InputSize >= u16SizeAfterScaling) && (eXRuleType == E_XRULE_VSP)) ++ { ++ //if post V down, we will load 121 filter, and when it's post scaling case ++ //reload 121 filter's VSP_Y=SRAM_1_4Tap, VSP_C=C_SRAM_1, ++ // SRAM1=InvSinc4Tc4p4Fc50Apass01Astop55, C_SRAM1=C121 for main-win ++ //reload 121 filter's VSP_Y=SRAM_3_4Tap, VSP_C=C_SRAM_3, ++ // SRAM3=InvSinc4Tc4p4Fc50Apass01Astop55, C_SRAM3=C121 for sub-win ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VSP_Y_SRAM_1_4Tap_Main, PQ_IP_VSP_Y_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VSP_C_C_SRAM_1_Main, PQ_IP_VSP_C_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_SRAM1_InvSinc4Tc4p4Fc50Apass01Astop55_Main, PQ_IP_SRAM1_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_C_SRAM1_C121_Main, PQ_IP_C_SRAM1_Main); ++ ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_VSP_Y_SRAM_3_4Tap_Sub, PQ_IP_VSP_Y_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_VSP_C_C_SRAM_3_Sub, PQ_IP_VSP_C_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_SRAM3_InvSinc4Tc4p4Fc50Apass01Astop55_Sub, PQ_IP_SRAM3_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_C_SRAM3_C121_Sub, PQ_IP_C_SRAM3_Sub); ++ } ++ } ++#endif ++ ++ return bRet; ++} ++ ++ ++////////////////////////////////////////////////////////////////// ++// set color range of input source and take effect immediately ++// ++void MDrv_PQ_SetColorRange(PQ_WIN eWindow, MS_BOOL bColorRange0_255) ++{ ++ _bColorRange0_255[eWindow] = bColorRange0_255; ++ MDrv_PQ_SetCSC(eWindow, _gFourceColorFmt[eWindow]); ++} ++ ++MS_BOOL MDrv_PQ_Get_CSC_XRuleIdx(MS_BOOL *pbInputColorSpaceRGB, ++ MS_U16 * pu16DoCSC, ++ PQ_WIN eWindow, ++ PQ_FOURCE_COLOR_FMT enFourceColor, ++ MS_BOOL bLoadPQTable) ++{ ++#if PQ_ENABLE_CSCRULE ++ ++ MS_U16 u16XRuleIdx, u16XRuleIP; ++ MS_U16 u16IPIdx, u16TabIdx; ++ MS_U16 eXRuleType = E_XRULE_CSC; ++ MS_BOOL bInputTypeVideo; ++ MS_BOOL bInputResolutionHD = _gIsSrcHDMode[eWindow]; ++ MS_U16 u16YUV_CSC, u16RGB_CSC; ++ ++ _gFourceColorFmt[eWindow] = enFourceColor; ++ ++#if ENABLE_VGA_EIA_TIMING ++ if ((QM_IsSourceVGA(_enInputSourceType[eWindow]) || ++ QM_IsSourceDVI_HDMIPC(_enInputSourceType[eWindow], eWindow)) && !QM_IsInterlaced(eWindow)) ++#else ++ if(QM_IsSourceVGA(_enInputSourceType[eWindow]) || ++ (QM_IsSourceDVI_HDMIPC(_enInputSourceType[eWindow], eWindow) && !QM_IsInterlaced(eWindow))) ++#endif ++ { ++ CSCRULE_DBG(printf("PC mode\r\n")); ++ bInputTypeVideo = FALSE; ++ ++#if (PQ_ENABLE_PIP == 1) ++ if(eWindow == PQ_SUB_WINDOW) ++ { ++ printf("[%s][%d] VGA in sub video case, force PC mode to video mode \r\n", __FUNCTION__, __LINE__); ++ bInputTypeVideo = TRUE; ++ } ++#endif ++ } ++ else ++ { ++ CSCRULE_DBG(printf("VIDEO mode\r\n")); ++ bInputTypeVideo = TRUE; ++ } ++ ++ if(MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) ++ { ++ CSCRULE_DBG(printf("PointToPoint mode\r\n")); ++ bInputTypeVideo = FALSE; ++ } ++ ++ if( QM_IsSourceVGA(_enInputSourceType[eWindow]) || ++ (QM_IsSourceDVI_HDMIPC(_enInputSourceType[eWindow],eWindow)) || ++ (QM_IsSourceHDMI_Video(_enInputSourceType[eWindow],eWindow) && (QM_HDMIPC_COLORRGB(eWindow))) ) ++ { ++ CSCRULE_DBG(printf("Input RGB\r\n")); ++ (*pbInputColorSpaceRGB) = TRUE; ++ } ++ else ++ { ++ CSCRULE_DBG(printf("Input YUV\r\n")); ++ (*pbInputColorSpaceRGB) = FALSE; ++ } ++ ++ if (bInputTypeVideo) ++ { ++ if (*pbInputColorSpaceRGB) ++ { ++ if (eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : // fource to RGB and input is RGB, hence no need change ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : // fource to RGB and input is RGB, hence no need change ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#endif ++ } ++ else // InputColorSpaceYUV ++ { ++ if(enFourceColor == PQ_FOURCE_COLOR_RGB ) ++ { ++ MS_ASSERT(0); ++ PQTAB_DBG(printf("InputColorSpace is YUV, Fource Color Space is RGB!!!\r\n")); ++ } ++ ++ if(eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ ++ if(enFourceColor == PQ_FOURCE_COLOR_RGB) ++ { ++ if(bInputResolutionHD) ++ { ++ if(_bColorRange0_255[eWindow]) ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ else ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_HD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ } ++ else ++ { ++ if(_bColorRange0_255[eWindow]) ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ else ++ { ++ u16XRuleIdx = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_Video_RGB_SD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ } ++ } ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_Video_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ } ++#endif ++ } ++ } ++ else // InputTypePC ++ { ++ if (*pbInputColorSpaceRGB) ++ { ++ if (eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ u16RGB_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_SD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ else // InputResolutionHD ++ { ++ if (_bColorRange0_255[eWindow]) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_0_255_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ else // bInputDataRange16_235 ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16RGB_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_RGB_HD_16_235_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = enFourceColor == PQ_FOURCE_COLOR_RGB ? ++ u16YUV_CSC : ++ u16RGB_CSC; ++ } ++ } ++ } ++#endif ++ } ++ else // InputColorSpaceYUV ++ { ++ if(enFourceColor == PQ_FOURCE_COLOR_RGB ) ++ { ++ MS_ASSERT(0); ++ PQTAB_DBG(printf("InputColorSpace is YUV, Fource Color Space is RGB!!!\r\n")); ++ } ++ ++ if(eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ if (bInputResolutionHD == FALSE) ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_SD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ else // InputResolutionHD ++ { ++ u16YUV_CSC = eWindow == PQ_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_CSCRule_PC_YUV_HD_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16XRuleIdx = u16YUV_CSC; ++ } ++ } ++#endif ++ } ++ } ++ ++ for(u16XRuleIP=0; u16XRuleIP u16GRule_NR_Num) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < u16GRule_NR_IP_Num; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, u16GRule_Type, i); ++ ++ if(u16PQ_NRIdx == u16GRule_NR_Num) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, u16GRule_Type, u16PQ_NRIdx, i); ++ ++ PQGRULE_DBG(printf("[NR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_NRIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if (eWindow == PQ_SUB_WINDOW) ++ { ++ MS_U16 u16GRule_NR_Num = eWindow == PQ_SUB_WINDOW ? PQ_GRULE_NR_NUM_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRULE_NR_NUM_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ MS_U16 u16GRule_NR_IP_Num = eWindow == PQ_SUB_WINDOW ? PQ_GRULE_NR_IP_NUM_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRULE_NR_IP_NUM_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ ++ MS_U16 u16GRule_Type = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ if(u16PQ_NRIdx > u16GRule_NR_Num) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < u16GRule_NR_IP_Num; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, u16GRule_Type, i); ++ ++ if(u16PQ_NRIdx == u16GRule_NR_Num) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, u16GRule_Type, u16PQ_NRIdx, i); ++ ++ PQGRULE_DBG(printf("[NR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_NRIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++ } ++#endif ++ else ++ { ++ PQGRULE_DBG(printf("[NR] Not support case \r\n")); ++ } ++} ++#endif ++ ++ ++void MDrv_PQ_LoadNRTable(PQ_WIN eWindow, PQ_3D_NR_FUNCTION_TYPE en3DNRType) ++{ ++#if (PQ_GRULE_NR_ENABLE) ++ ++ MS_U16 u16PQ_NRIdx; ++ MS_U16 u16GRule_Type, u16GRule_Level; ++ ++ PQGRULE_DBG( printf("[PQ_LoadNRTable] ") ); ++ ++ if (eWindow == PQ_MAIN_WINDOW || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ u16GRule_Type = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ ++ if(en3DNRType == PQ_3D_NR_OFF) ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Off_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Off_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Off_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_AUTO) ++ { ++ // Auto NR will be process in msAPI_DynamicNR_Handler(), hence we only need to pre-setup the PQ table. ++ PQGRULE_DBG(printf("Auto\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Low_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Low_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Low_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_LOW) ++ { ++ PQGRULE_DBG(printf("Low\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Low_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Low_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Low_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_MID) ++ { ++ PQGRULE_DBG(printf("Mid\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_Middle_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_Middle_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_Middle_SC1_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_HIGH) ++ { ++ PQGRULE_DBG(printf("High\r\n")); ++ u16GRule_Level = eWindow == PQ_MAIN_WINDOW ? PQ_GRule_NR_High_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRule_NR_High_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRule_NR_High_SC2_Main : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_DEFAULT) ++ { ++ MS_U16 u16NR_Idx = eWindow == PQ_MAIN_WINDOW ? PQ_GRULE_NR_NUM_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_GRULE_NR_NUM_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_GRULE_NR_NUM_SC2_Main : ++ #endif ++ 0xFFFF; ++ PQGRULE_DBG(printf("Default\r\n")); ++ _MDrv_PQ_LoadNRTable(eWindow, u16NR_Idx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++ } ++#if PQ_ENABLE_PIP ++ else if (eWindow == PQ_SUB_WINDOW) ++ { ++ u16GRule_Type = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ if(en3DNRType == PQ_3D_NR_OFF) ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Off_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Off_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_AUTO) ++ { ++ // Auto NR will be process in msAPI_DynamicNR_Handler(), hence we only need to pre-setup the PQ table. ++ PQGRULE_DBG(printf("Auto\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Low_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Low_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_LOW) ++ { ++ PQGRULE_DBG(printf("Low\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Low_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Low_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_MID) ++ { ++ PQGRULE_DBG(printf("Mid\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_Middle_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_Middle_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_HIGH) ++ { ++ PQGRULE_DBG(printf("High\r\n")); ++ u16GRule_Level = eWindow == PQ_SUB_WINDOW ? PQ_GRule_NR_High_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRule_NR_High_SC2_Sub : ++ #endif ++ 0xFFFF; ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, u16GRule_Type, u16GRule_Level); ++ _MDrv_PQ_LoadNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(en3DNRType == PQ_3D_NR_DEFAULT) ++ { ++ MS_U16 u16NR_Idx = eWindow == PQ_SUB_WINDOW ? PQ_GRULE_NR_NUM_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_GRULE_NR_NUM_SC2_Sub : ++ #endif ++ 0xFFFF; ++ PQGRULE_DBG(printf("Default\r\n")); ++ _MDrv_PQ_LoadNRTable(eWindow, u16NR_Idx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++ } ++#endif ++ else ++ { ++ PQGRULE_DBG(printf("Not support case \r\n")); ++ } ++ ++#if 0 //trunk don't have janus code, it's obsolete ++#ifdef __AEONR2__ //patch for DDR2-800 on Janus ++ if(QM_IsInterlaced(eWindow) && QM_IsSourceMultiMedia(MDrv_PQ_GetInputSourceType(eWindow)) && (MApi_XC_ReadByte(0x110D30)==0x66)) ++ { ++ MS_U16 u16Input_HSize; ++ MS_U16 u16Input_VSize; ++ u16Input_HSize = _stMode_Info[eWindow].u16input_hsize; ++ u16Input_VSize = _stMode_Info[eWindow].u16input_vsize; ++ ++ if(u16Input_HSize>1280 && u16Input_VSize>=900) ++ { ++ MApi_XC_WriteByte(0x102F00, 0x12); ++ MApi_XC_WriteByte(0x102F03, 0x27); ++ MApi_XC_WriteByte(0x102F00, 0x06); ++ MApi_XC_WriteByte(0x102F42, MApi_XC_ReadByte(0x102F42)&0xFE); ++ } ++ } ++#endif ++#endif ++#endif // PQ_GRULE_NR_ENABLE ++} ++ ++#if PQ_GRULE_OSD_BW_ENABLE ++static void _MDrv_PQ_LoadOSD_BWTable(PQ_WIN eWindow, MS_U16 u16PQ_OSD_BW_Idx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ ++ if(u16PQ_OSD_BW_Idx > PQ_GRULE_OSD_BW_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_OSD_BW_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_OSD_BW_Main, i); ++ ++ if(u16PQ_OSD_BW_Idx == PQ_GRULE_OSD_BW_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSD_BW_Idx, i); ++ ++ PQGRULE_DBG(printf("[NR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u8TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_OSD_BW_Idx, i, u16IPIdx, u16IPIdx)); ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++ ++ ++void MDrv_PQ_LoadOSD_BWTable(PQ_WIN eWindow, PQ_OSD_BW_FUNCTION_TYPE enOSD_BW_Type) ++{ ++ MS_U16 u16PQ_NRIdx; ++ ++ PQGRULE_DBG(printf("[PQ_Load_OSD_BW_Table] ")); ++ ++ if(enOSD_BW_Type == PQ_OSD_BW_ON) ++ { ++ PQGRULE_DBG(printf("On\r\n")); ++ ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ if(bw_info.u32Miu1MemSize == 0) ++ { ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_Main); ++ _MDrv_PQ_LoadOSD_BWTable(eWindow, u16PQ_NRIdx); ++ } ++ else ++ { ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_Main); ++ _MDrv_PQ_LoadOSD_BWTable(eWindow, u16PQ_NRIdx); ++ } ++ #else ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_On_Main); ++ _MDrv_PQ_LoadOSD_BWTable(eWindow, u16PQ_NRIdx); ++ #endif ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++} ++#endif ++ ++#if PQ_GRULE_FILM_MODE_ENABLE ++static void _MDrv_PQ_LoadFilmModeTable(PQ_WIN eWindow, MS_U16 u16PQ_FilmModeIdx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ if(u16PQ_FilmModeIdx > PQ_GRULE_FILM_MODE_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_FILM_MODE_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_FILM_MODE_Main, i); ++ ++ if(u16PQ_FilmModeIdx == PQ_GRULE_FILM_MODE_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16TabIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_FILM_MODE_Main, u16PQ_FilmModeIdx, i); ++ ++ PQGRULE_DBG(printf("[FM]SRC: %u, FM: %u, FMIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_FilmModeIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++ ++void MDrv_PQ_LoadFilmModeTable(PQ_WIN eWindow, PQ_FILM_MODE_FUNCTION_TYPE enFilmModeType) ++{ ++#if PQ_GRULE_FILM_MODE_ENABLE ++ MS_U16 u16PQ_FilmModeIdx; ++ ++ if(enFilmModeType == PQ_FilmMode_OFF) ++ { ++ u16PQ_FilmModeIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_FILM_MODE_Main, PQ_GRule_FILM_MODE_Off_Main); ++ _MDrv_PQ_LoadFilmModeTable(eWindow, u16PQ_FilmModeIdx); ++ ++ } ++ else if(enFilmModeType == PQ_FilmMode_ON) ++ { ++ u16PQ_FilmModeIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_FILM_MODE_Main, PQ_GRule_FILM_MODE_On_Main); ++ _MDrv_PQ_LoadFilmModeTable(eWindow, u16PQ_FilmModeIdx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(enFilmModeType); ++#endif ++} ++ ++#if PQ_GRULE_DYNAMIC_CONTRAST_ENABLE ++static void _MDrv_PQ_DynamicContrastTable(PQ_WIN eWindow, MS_U16 u16PQ_DynContrIdx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ if(u16PQ_DynContrIdx > PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, i); ++ ++ if(u16PQ_DynContrIdx == PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16TabIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, u16PQ_DynContrIdx, i); ++ ++ PQGRULE_DBG(printf("[DC]SRC: %u, DC: %u, DCIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_DynContrIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_LoadDynamicContrastTable(PQ_WIN eWindow, PQ_DYNAMIC_CONTRAST_FUNCTION_TYPE enDynamicContrastType) ++{ ++#if PQ_GRULE_DYNAMIC_CONTRAST_ENABLE ++ MS_U16 u16PQ_DynContrIdx; ++ ++ if(enDynamicContrastType == PQ_DynContr_OFF) ++ { ++ u16PQ_DynContrIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, PQ_GRule_DYNAMIC_CONTRAST_Off_Main); ++ _MDrv_PQ_DynamicContrastTable(eWindow, u16PQ_DynContrIdx); ++ } ++ else if(enDynamicContrastType == PQ_DynContr_ON) ++ { ++ u16PQ_DynContrIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DYNAMIC_CONTRAST_Main, PQ_GRule_DYNAMIC_CONTRAST_On_Main); ++ _MDrv_PQ_DynamicContrastTable(eWindow, u16PQ_DynContrIdx); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(enDynamicContrastType); ++#endif ++} ++ ++ ++#if PQ_GRULE_MPEG_NR_ENABLE ++static void _MDrv_PQ_LoadMPEGNRTable(PQ_WIN eWindow, MS_U16 u16PQ_NRIdx) ++{ ++ MS_U16 i, u16IPIdx = 0, u16TabIdx = 0; ++ if(u16PQ_NRIdx > PQ_GRULE_MPEG_NR_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_MPEG_NR_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_MPEG_NR_Main, i); ++ ++ if(u16PQ_NRIdx == PQ_GRULE_MPEG_NR_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_MPEG_NR_Main, u16PQ_NRIdx, i); ++ ++ PQGRULE_DBG(printf("[MPEGNR]SRC: %u, NR: %u, NRIPIdx:%u, IPIdx:%u, u16TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_NRIdx, i, u16IPIdx, u16TabIdx)); ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_LoadMPEGNRTable(PQ_WIN eWindow, PQ_MPEG_NR_FUNCTION_TYPE enMPEGNRType) ++{ ++#if(PQ_GRULE_MPEG_NR_ENABLE) ++ MS_U16 u16PQ_NRIdx; ++ ++ PQGRULE_DBG(printf("[PQ_LoadMPEGNRTable] ")); ++ ++ if(enMPEGNRType == PQ_MPEG_NR_OFF) ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Off_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if( enMPEGNRType == PQ_MPEG_NR_AUTO ) ++ { ++ // Auto NR will be process in msAPI_DynamicNR_Handler(), hence we only need to pre-setup the PQ table. ++ PQGRULE_DBG(printf("Auto\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Low_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_LOW) ++ { ++ PQGRULE_DBG(printf("Low\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Low_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_MID) ++ { ++ PQGRULE_DBG(printf("Mid\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_Middle_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_HIGH) ++ { ++ PQGRULE_DBG(printf("High\r\n")); ++ u16PQ_NRIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_MPEG_NR_Main, PQ_GRule_MPEG_NR_High_Main); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, u16PQ_NRIdx); ++ } ++ else if(enMPEGNRType == PQ_MPEG_NR_DEFAULT) ++ { ++ PQGRULE_DBG(printf("Default\r\n")); ++ _MDrv_PQ_LoadMPEGNRTable(eWindow, PQ_GRULE_MPEG_NR_NUM_Main); ++ } ++ else ++ { ++ MS_ASSERT(0); ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(enMPEGNRType); ++#endif ++} ++#if PQ_GRULE_ULTRAT_CLEAR_ENABLE ++static void _MDrv_PQ_Load_ULTRACLEAR_Table(PQ_WIN eWindow, MS_U16 u16PQ_ULTRACLEAR_Idx) ++{ ++ MS_U16 i = 0, u16IPIdx = 0, u16TabIdx = 0; ++ ++ if(u16PQ_ULTRACLEAR_Idx > PQ_GRULE_ULTRAT_CLEAR_NUM_Main) ++ { ++ MS_ASSERT(0); ++ return; ++ } ++ ++ for(i = 0; i < PQ_GRULE_ULTRAT_CLEAR_IP_NUM_Main; i++) ++ { ++ u16IPIdx = MDrv_PQ_GetGRule_IPIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, i); ++ ++ if(u16PQ_ULTRACLEAR_Idx == PQ_GRULE_ULTRAT_CLEAR_NUM_Main) // see it as default ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ else ++ u16TabIdx = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, u16PQ_ULTRACLEAR_Idx, i); ++ ++ PQGRULE_DBG(printf("[UC]SRC: %u, UC: %u, UCIPIdx:%u, IPIdx:%u, u8TabIdx:%u\r\n", ++ _u16PQSrcType[eWindow], u16PQ_ULTRACLEAR_Idx, i, u16IPIdx, u16IPIdx)); ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_Load_ULTRACLEAR_Table(PQ_WIN eWindow, PQ_FEATURE_SWITCH_TYPE enCtrlType) ++{ ++ MS_U16 u16PQ_TableIdx = 0; ++#if PQ_GRULE_ULTRAT_CLEAR_ENABLE ++ PQGRULE_DBG(printf("[PQ_Load_ULTRACLEAR_Table] ")); ++ if(enCtrlType == PQ_FEATURE_SWITCH_ON) ++ { ++ PQGRULE_DBG(printf("On\r\n")); ++ u16PQ_TableIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, PQ_GRule_ULTRAT_CLEAR_On_Main); ++ _MDrv_PQ_Load_ULTRACLEAR_Table(eWindow, u16PQ_TableIdx); ++ } ++ else ++ { ++ PQGRULE_DBG(printf("Off\r\n")); ++ u16PQ_TableIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_ULTRAT_CLEAR_Main, PQ_GRule_ULTRAT_CLEAR_Off_Main); ++ _MDrv_PQ_Load_ULTRACLEAR_Table(eWindow, u16PQ_TableIdx); ++ } ++#else ++ UNUSED(u16PQ_TableIdx); ++ UNUSED(eWindow); ++ UNUSED(enCtrlType); ++ ++#endif ++ ++} ++ ++MS_BOOL MDrv_PQ_GRULE_Get_Support_Status(PQ_SUPPORTED_TYPE enType) ++{ ++ MS_BOOL bStatus = FALSE; ++ switch(enType) ++ { ++ case E_PQ_SUPPORTED_FILM: ++ if(PQ_GRULE_FILM_MODE_ENABLE) ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_NR: ++ if(PQ_GRULE_NR_ENABLE) ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_MPEG_NR: ++ if(PQ_GRULE_MPEG_NR_ENABLE) ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_BLACK_LEVEL: ++ bStatus = TRUE; ++ break; ++ case E_PQ_SUPPORTED_ULTRA_CLEAR: ++ if(PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ bStatus = TRUE; ++ break; ++ default: ++ break; ++ } ++ ++ return bStatus; ++ ++} ++ ++MS_U8 _MDrv_PQ_wait_output_vsync(PQ_WIN ePQWin, MS_U8 u8NumVSyncs, MS_U16 u16Timeout) ++{ ++ MS_U32 u32Time; ++ MS_U8 bVSync; ++ //MS_BOOL bMainWin = (ePQWin == PQ_MAIN_WINDOW) ? TRUE : FALSE; ++ ++ bVSync = 0; ++ u32Time = MsOS_GetSystemTime(); ++ ++ while(1) ++ { ++ if(Hal_PQ_get_output_vsync_value(ePQWin) == bVSync) ++ { ++ u8NumVSyncs--; ++ if(bVSync && (u8NumVSyncs == 0)) ++ break; ++ bVSync = !bVSync; ++ } ++ ++ if((MsOS_GetSystemTime() - u32Time) >= u16Timeout) ++ break; ++ } ++ ++ return u8NumVSyncs; ++} ++ ++MS_U8 _MDrv_PQ_wait_input_vsync(PQ_WIN ePQWin, MS_U8 u8NumVSyncs, MS_U16 u16Timeout) ++{ ++ MS_U32 u32Time; ++ //MS_BOOL bMainWin = (ePQWin == PQ_MAIN_WINDOW) ? TRUE : FALSE; ++ MS_U8 u8VsyncPolarity = Hal_PQ_get_input_vsync_polarity(ePQWin); ++ MS_U8 bVSync = !u8VsyncPolarity; ++ ++ u32Time = MsOS_GetSystemTime(); ++ ++ while(1) ++ { ++ if(Hal_PQ_get_input_vsync_value(ePQWin) == bVSync) ++ { ++ u8NumVSyncs--; ++ if((bVSync == u8VsyncPolarity) && (u8NumVSyncs == 0)) ++ break; ++ bVSync = !bVSync; ++ } ++ ++ if((MsOS_GetSystemTime() - u32Time) >= u16Timeout) ++ { ++ //printf("!!input vsync timeout\r\n"); ++ break; ++ } ++ } ++ ++ return u8NumVSyncs; ++} ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++void MDrv_PQ_Set_DBRule(PQ_WIN eWindow, MS_U16 u16MADi_Idx) ++{ ++ MS_U16 eXRuleType = E_XRULE_CSC; ++ MS_U16 u16XRuleIdx, u16XRuleIP; ++ MS_U16 u16IPIdx, u16TabIdx; ++ ++ eXRuleType = (_stMode_Info[eWindow].u16input_vfreq > 550) ? E_XRULE_DB_NTSC : E_XRULE_DB_PAL; ++ ++ if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_4R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_4R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_2R_Main; ++ } ++ else if(yHal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_MC) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_MC_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_2R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_4R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_27_4R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_2R) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_27_2R_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE8_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE10) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE10_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT8) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE_MOT8_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_P_MODE_MOT10_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_4R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_4R_880_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_2R_880_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_6R_MC_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_14F_6R_MC) == u16MADi_Idx) //Add New MADi mode ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_14F_6R_MC_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_MC_NW) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_MC_NW_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC_NW) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_6R_MC_NW_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_884) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_4R_884_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R_884) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_25_2R_884_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_4R_880_Main; ++ } ++ else if(Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R_880) == u16MADi_Idx) ++ { ++ u16XRuleIdx = PQ_DBRule_NTSC_24_2R_880_Main; ++ } ++ else ++ { ++ u16XRuleIdx = 0xFF; ++ } ++ ++ for(u16XRuleIP = 0; u16XRuleIP < MDrv_PQ_GetXRuleIPNum(eWindow, eXRuleType); u16XRuleIP++) ++ { ++ if(u16XRuleIdx == 0xFF) ++ continue; ++ ++ u16IPIdx = MDrv_PQ_GetXRuleIPIndex(eWindow, eXRuleType, u16XRuleIP); ++ u16TabIdx = MDrv_PQ_GetXRuleTableIndex(eWindow, eXRuleType, u16XRuleIdx, u16XRuleIP); ++ //(printf("u16XRuleIdx:%u, u16XRuleIP=%u, IPIdx=%u, TabIdx=%u\r\n", u16XRuleIdx, u16XRuleIP, u16IPIdx, u16TabIdx)); ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++} ++#endif ++ ++void MDrv_PQ_EnableMADIForce(PQ_WIN eWindow, MS_BOOL bFullMotion) ++{ ++#if PQ_ENABLE_FORCE_MADI ++ MS_U16 u16TabIdx, u16IPIdx; ++ if(bFullMotion) ++ { ++ ++ u16TabIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullMotion_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ } ++ else ++ { ++ u16TabIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_YC_FullStill_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Force_Main : ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Force_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Force_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Force_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_Force_SC2_Sub : ++ #endif ++ 0xFFFF; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, u16IPIdx); ++ ++ } ++#else ++UNUSED(eWindow); ++UNUSED(bFullMotion); ++#endif ++} ++ ++////////////////////////////////////////////////////////////////// ++// Load MADi/444To422/422To444 table ++// ++// parameter: ++// [IN] u8PQTabType ++// bMemFmt422: TRUE - 422 ++// FALSE - 444 ++// bFBL: TRUE - framebuffer-less mode ++// FALSE - framebuffer mode ++// [OUT] u8BitsPerPixel ++// bits per pixel for decided memory format ++// ++// return: deinterlace (MADi) mode ++// ++PQ_DEINTERLACE_MODE MDrv_PQ_SetMemFormat(PQ_WIN eWindow, MS_BOOL bMemFmt422, MS_BOOL bFBL, MS_U8 *pu8BitsPerPixel) ++{ ++ ++#if(PQ_ENABLE_MEMFMT) ++ ++ MS_U16 u16TabIdx_MemFormat = 0; ++ MS_U16 u16TabIdx_MADi = 0; ++ MS_U16 u16TabIdx_MADi_Motion=0xFFFF; ++ MS_U16 u16TabIdx_444To422 = 0; ++ MS_U16 u16TabIdx_422To444 = 0; ++ PQ_DEINTERLACE_MODE eDeInterlaceMode = PQ_DEINT_OFF; ++ MS_U8 u8FrameCount = 4; ++ ++ if(eWindow == PQ_MAIN_WINDOW ++#if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++#endif ++ ) ++ { ++#if 0 //Ryan ++ SCALER_WIN eSCWin = ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? SC2_MAIN_WINDOW : ++ eWindow == PQ_SC1_MAIN_WINDOW ? SC1_MAIN_WINDOW : ++ #endif ++ MAIN_WINDOW; ++ MApi_XC_Set_OPWriteOffEnable(ENABLE, eSCWin); //default ++#endif ++ } ++ else ++ { ++ PQINFO_DBG(printf("No need to enable OP write with sub window, it would change main window setting \r\n")); ++ } ++ ++ PQTAB_DBG(printf("==>In PQ : eWindow =%d\r\n", eWindow)); ++ ++ if(!bFBL) ++ { ++ // if MADi mode change from 25 <=> 27, cropping base address need to be recalculated. ++#if PQ_GRULE_OSD_BW_ENABLE ++ if(((_stMode_Info[eWindow].u16input_hsize >= 1280) && (_stMode_Info[eWindow].u16input_vsize >= 720)) && ++ (_bOSD_On)) ++ { ++ MDrv_PQ_GetMADiFromGrule(eWindow, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++ } ++ else ++#endif ++ { ++ MDrv_PQ_GetMADiInGeneral(eWindow, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++#if PQ_GRULE_OSD_BW_ENABLE ++ MDrv_PQ_Patch2Rto4RForFieldPackingMode(eWindow, u16TabIdx_MADi); ++#endif ++ } ++ ++ MDrv_PQ_GetMADiForRFBL(eWindow, bFBL, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++ } ++ else // FBL ++ { ++ MS_U8 u8FblMode = Hal_PQ_get_madi_fbl_mode(bMemFmt422, _stMode_Info[eWindow].bInterlace); ++ u16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, (MS_MADI_TYPE)u8FblMode); ++ } ++ ++ ++ PQMADi_DBG(printf("Memory is %s mode \r\n", (bFBL)?("1.FBL"):("2.FB"))); ++ PQMADi_DBG(printf("get MADi idx = %u\r\n", u16TabIdx_MADi)); ++ ++ MDrv_PQ_GetMemFmtInGeneral(eWindow, bMemFmt422, &u16TabIdx_MemFormat, &u16TabIdx_444To422, &u16TabIdx_422To444); ++ ++ PQTAB_DBG(printf("%s :u16TabIdx_444To422=%u\r\n", eWindow?"SubWin":"MainWin",u16TabIdx_444To422)); ++ PQTAB_DBG(printf("%s :u16TabIdx_422To444=%u\r\n", eWindow?"SubWin":"MainWin",u16TabIdx_422To444)); ++ PQMADi_DBG(printf("MemFmt is 422 : %s\r\n",(bMemFmt422)?("Yes"):("No"))); ++ ++ MDrv_PQ_GetBPPInfoFromMADi(eWindow, bMemFmt422, u16TabIdx_MADi, u16TabIdx_MemFormat, pu8BitsPerPixel, &eDeInterlaceMode, &u8FrameCount); ++ ++ PQMADi_DBG(printf("BitPerPixel =%d, DIMode =%x\r\n", *pu8BitsPerPixel, eDeInterlaceMode)); ++ ++ _gbMemfmt422[eWindow] = bMemFmt422; ++ ++ MDrv_PQ_ChangeMemConfigFor3D(eWindow, bMemFmt422, &u16TabIdx_MemFormat, &u16TabIdx_444To422, &u16TabIdx_422To444, ++ pu8BitsPerPixel, &u16TabIdx_MADi_Motion, &u16TabIdx_MADi); ++ ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ MS_U16 u16IPIdx; ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MemFormat_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MemFormat_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MemFormat_SC2_Main : ++ #endif ++ 0xFFFF; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MemFormat, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MADi, u16IPIdx); ++#if PQ_GRULE_OSD_BW_ENABLE ++ if(0xFFFF != u16TabIdx_MADi_Motion) ++ { ++ PQTAB_DBG(printf("u16TabIdx_MADi_Motion=%u\r\n", u16TabIdx_MADi_Motion)); ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_MADi_Motion_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_MADi_Motion_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_MADi_Motion_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MADi_Motion, u16IPIdx); ++ } ++#endif ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_444To422_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_444To422_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_444To422_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_444To422, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_422To444_Main : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_422To444_SC1_Main : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_422To444_SC2_Main : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_422To444, u16IPIdx); ++ } ++#if PQ_ENABLE_PIP ++ else ++ { ++ MS_U16 u16IPIdx; ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_MemFormat_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MemFormat_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MemFormat, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_MADi_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_MADi_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_MADi, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_444To422_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_444To422_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_444To422, u16IPIdx); ++ ++ u16IPIdx = eWindow == PQ_SUB_WINDOW ? PQ_IP_422To444_Sub : ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_422To444_SC2_Sub : ++ #endif ++ 0xFFFF; ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx_422To444, u16IPIdx); ++ } ++#endif ++ ++ PQTAB_DBG(printf("u16TabIdx_MemFormat=%u\r\n", u16TabIdx_MemFormat)); ++ PQTAB_DBG(printf("%s, u16TabIdx_MADi=%u\r\n", eWindow?"SUB_WIN":"MAIN_WIN",u16TabIdx_MADi)); ++ PQTAB_DBG(printf("%s, u16TabIdx_MADi=%u\r\n", eWindow?"SUB_WIN":"MAIN_WIN",u16TabIdx_MADi)); ++ PQTAB_DBG(printf("main :u16TabIdx_444To422=%u\r\n", u16TabIdx_444To422)); ++ PQTAB_DBG(printf("main :u16TabIdx_422To444=%u\r\n", u16TabIdx_422To444)); ++ ++#if (PQ_XRULE_DB_ENABLE == 1) ++ MDrv_PQ_Set_DBRule(eWindow, u16TabIdx_MADi); ++#endif ++ ++ MDrv_PQ_ForceBPPForDynamicMemFmt(eWindow, bMemFmt422, pu8BitsPerPixel); ++ MDrv_PQ_SetFrameNumber(eWindow, u16TabIdx_MADi, u8FrameCount); ++ ++ if(_bDS_En) ++ { ++ _u16RW_Method = Hal_PQ_get_rw_method(eWindow); ++ Hal_PQ_set_rw_method(eWindow, 0x4000); ++ } ++ return eDeInterlaceMode; ++#else ++ return PQ_DEINT_OFF; ++#endif ++} ++ ++void MDrv_PQ_ReduceBW_ForOSD(PQ_WIN eWindow, MS_BOOL bOSD_On) ++{ ++#if PQ_GRULE_OSD_BW_ENABLE ++ MS_U8 u8BitPerPixel = 0; ++{ ++ if((_stMode_Info[eWindow].u16input_hsize >= 1280) && (_stMode_Info[eWindow].u16input_vsize >= 720)) ++ { ++ PQBW_DBG(printf("[PQ_ReduceBW_ForOSD]:%u\r\n", bOSD_On)); ++ ++ _bOSD_On = bOSD_On; ++ bSetFrameCount = FALSE; ++ ++ MDrv_PQ_SetMemFormat( ++ eWindow, ++ _gbMemfmt422[eWindow], ++ _stMode_Info[eWindow].bFBL, ++ &u8BitPerPixel); ++ bSetFrameCount = TRUE; ++ ++ } ++} ++#else ++ UNUSED(eWindow); ++ UNUSED(bOSD_On); ++#endif ++ ++ return; ++} ++ ++void MDrv_PQ_ReduceBW_ForPVR(PQ_WIN eWindow, MS_BOOL bPVR_On) ++{ ++ UNUSED(eWindow); ++ UNUSED(bPVR_On); ++} ++ ++void _MDrv_PQ_Set_MVOP_UVShift(MS_BOOL bEnable) ++{ ++ MS_U8 regval; ++ ++ regval = MApi_XC_ReadByte(VOP_MPG_JPG_SWITCH); ++ ++ if(((regval & 0x10) == 0x10) && ((regval & 0x3) == 0x2)) ++ { ++ // 422 with MCU control mode ++ if(bEnable) ++ { ++ MS_ASSERT(0); ++ } ++ } ++ ++ // output 420 and interlace ++ //[IP - Sheet] : Main Page --- 420CUP ++ //[Project] : Titania2 ++ //[Description]: Chroma artifacts when 420to422 is applied duplicate method. ++ //[Root cause]: Apply 420to422 average algorithm to all DTV input cases. ++ //The average algorithm must cooperate with MVOP. ++ MApi_XC_WriteByteMask(VOP_UV_SHIFT, (bEnable) ? 1 : 0, 0x3); ++} ++ ++void MDrv_PQ_Set420upsampling(PQ_WIN eWindow, ++ MS_BOOL bFBL, ++ MS_BOOL bPreV_ScalingDown, ++ MS_U16 u16V_CropStart) ++{ ++#if PQ_ENABLE_420UPSAMPLING ++ ++ MS_U16 u16TabIdx; ++ ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_420CUP_Main); ++ ++ PQTAB_DBG(printf("[PQ_Set420upsampling]: SrcType:%u, FBL:%u, PreV down:%u, V_CropStart:%u, u8TabIdx=%u, ", ++ _u16PQSrcType[eWindow], bFBL, bPreV_ScalingDown, u16V_CropStart, u16TabIdx)); ++ ++ if((u16TabIdx == Hal_PQ_get_420_cup_idx(MS_420_CUP_ON)) && (!bPreV_ScalingDown) && (!bFBL)) ++ { ++ PQTAB_DBG(printf("UVShift: on\r\n")); ++ _MDrv_PQ_Set_MVOP_UVShift(ENABLE); ++ MDrv_PQ_LoadTable(eWindow, Hal_PQ_get_420_cup_idx(MS_420_CUP_ON), PQ_IP_420CUP_Main); ++ } ++ else // P mode should not do UV shift ++ { ++ PQTAB_DBG(printf("UVShift: off\r\n")); ++ _MDrv_PQ_Set_MVOP_UVShift(DISABLE); ++ MDrv_PQ_LoadTable(eWindow, Hal_PQ_get_420_cup_idx(MS_420_CUP_OFF), PQ_IP_420CUP_Main); ++ } ++ ++ if((u16V_CropStart & 0x3) == 0) // crop lines are multiple of 4 ++ Hal_PQ_set_420upSample(eWindow, 0x6666); ++ else if((u16V_CropStart & 0x1) == 0) // crop lines are multiple of 2 ++ Hal_PQ_set_420upSample(eWindow, 0x9999); ++ else ++ MS_ASSERT(0); ++#endif ++} ++ ++void MDrv_PQ_SetFilmMode(PQ_WIN eWindow, MS_BOOL bEnable) ++{ ++#if PQ_ENABLE_SETFILM_MODE ++ MS_U16 u16TabIdx; ++ ++ PQTAB_DBG(printf("[PQ_SetFilmMode]: PQTabType=%u, enable=%u\r\n", eWindow, bEnable)); ++ ++ if(bEnable) ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_Film32_Main); ++ else ++ u16TabIdx = PQ_IP_Film32_OFF_Main; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, PQ_IP_Film32_Main); ++ ++ if(bEnable) ++ u16TabIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_Film22_Main); ++ else ++ u16TabIdx = PQ_IP_Film22_OFF_Main; ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, PQ_IP_Film22_Main); ++#endif ++} ++ ++ ++void MDrv_PQ_SetNonLinearScaling(PQ_WIN eWindow, MS_U8 u8Level, MS_BOOL bEnable) ++{ ++#if PQ_ENABLE_NONLINEAR_SCALING ++ MS_U16 u16TabIdx; ++ PQTAB_DBG(printf("[PQ_SetNonLinearScaling]: Level=%u, enable=%u\r\n", u8Level, bEnable)); ++ ++ if(bEnable) ++ { ++ switch(_stPQ_Info.u16PnlWidth) ++ { ++ case 1920: ++ switch(u8Level) ++ { ++ case 2: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1920_2); ++ break; ++ case 1: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1920_1); ++ break; ++ case 0: ++ default: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1920_0); ++ break; ++ } ++ break; ++ case 1680: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1680); ++ break; ++ case 1440: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1440); ++ break; ++ case 1366: ++ switch(u8Level) ++ { ++ case 2: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1366_2); ++ break; ++ case 1: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1366_1); ++ break; ++ case 0: ++ default: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_1366_0); ++ break; ++ ++ } ++ break; ++ default: ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_OFF); ++ break; ++ ++ break; ++ } ++ } ++ else ++ { ++ u16TabIdx = Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_OFF); ++ } ++ ++ MDrv_PQ_LoadTable(eWindow, u16TabIdx, PQ_IP_HnonLinear_Main); ++#endif ++} ++ ++void MDrv_PQ_3DCloneforPIP(MS_BOOL bIpSync) ++{ ++#if 0 //Ryan ++ //MVOP_Handle stHdl = { E_MVOP_MODULE_MAIN }; ++ MS_BOOL bEnAltOutputState = FALSE; ++ ++//![for temporary A3-WinCE6 porting, 20120109] ++#if 0 //ndef MSOS_TYPE_CE ++ ++ if (E_MVOP_OK == MDrv_MVOP_GetCommand(&stHdl, E_MVOP_CMD_GET_3DLR_ALT_OUT, &bEnAltOutputState, sizeof(bEnAltOutputState))) ++ { ++ //printf("%s Get3DLRAltOutput=0x%x\r\n", __FUNCTION__, bEnAltOutputState); ++ } ++ else ++ { ++ //printf("Fail to query E_MVOP_CMD_GET_3DLR_ALT_OUT!!\r\n"); ++ } ++ ++#endif ++ ++ if((E_XC_3D_OUTPUT_LINE_ALTERNATIVE == MApi_XC_Get_3D_Output_Mode()) ++ || (E_XC_3D_OUTPUT_TOP_BOTTOM == MApi_XC_Get_3D_Output_Mode()) ++ || (E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF == MApi_XC_Get_3D_Output_Mode())) ++ { ++ #if 0 ++ MApi_XC_ACE_3DClonePQMap(E_ACE_WEAVETYPE_NONE); ++ //printf("3D:confirm to clone main/sub win\r\n"); ++ #endif ++ ++ if((MApi_XC_Get_3D_HW_Version() < 2) && bIpSync) ++ { ++ MApi_XC_3DMainSub_IPSync(); ++ //printf("3D:confirm to do main/sub win sync\r\n"); ++ } ++ } ++ else if(MApi_XC_IsCurrentFrameBufferLessMode() && bEnAltOutputState) ++ { ++ #if 0 ++ MApi_XC_ACE_3DClonePQMap(E_ACE_WEAVETYPE_H); ++ #endif ++ } ++ MApi_XC_3D_PostPQSetting(MAIN_WINDOW); ++#endif ++} ++ ++void MDrv_PQ_DisableFilmMode(PQ_WIN eWindow, MS_BOOL bOn) ++{ ++ if(bOn) ++ { ++ MDrv_PQ_SetFilmMode(eWindow, DISABLE); ++ } ++ else ++ { ++ MDrv_PQ_SetFilmMode(eWindow, ENABLE); ++ } ++} ++ ++MS_BOOL MDrv_PQ_DisableUCFeature(PQ_WIN eWindow) ++{ ++ MS_BOOL bRet = TRUE; ++ ++#if PQ_EN_UCNR_OFF ++ if(PQ_MAIN_WINDOW == eWindow) ++ { ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_UCNR_OFF_Main, PQ_IP_UCNR_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_UC_CTL_OFF_Main, PQ_IP_UC_CTL_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_UCDi_OFF_Main, PQ_IP_UCDi_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(PQ_SUB_WINDOW == eWindow) ++ { ++ #if defined(AMBER3) ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_UCNR_OFF_Sub, PQ_IP_UCNR_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_UC_CTL_OFF_Sub, PQ_IP_UC_CTL_Sub); ++ MDrv_PQ_LoadTable(PQ_SUB_WINDOW, PQ_IP_UCDi_OFF_Sub, PQ_IP_UCDi_Sub); ++ #endif ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(PQ_SC1_MAIN_WINDOW == eWindow) ++ { ++ MDrv_PQ_LoadTable(PQ_SC1_MAIN_WINDOW, PQ_IP_UCNR_OFF_SC1_Main, PQ_IP_UCNR_SC1_Main); ++ MDrv_PQ_LoadTable(PQ_SC1_MAIN_WINDOW, PQ_IP_UC_CTL_OFF_SC1_Main, PQ_IP_UC_CTL_SC1_Main); ++ MDrv_PQ_LoadTable(PQ_SC1_MAIN_WINDOW, PQ_IP_UCDi_OFF_SC1_Main, PQ_IP_UCDi_SC1_Main); ++ } ++ else if(PQ_SC2_MAIN_WINDOW == eWindow) ++ { ++ MDrv_PQ_LoadTable(PQ_SC2_MAIN_WINDOW, PQ_IP_UCNR_OFF_SC2_Main, PQ_IP_UCNR_SC2_Main); ++ MDrv_PQ_LoadTable(PQ_SC2_MAIN_WINDOW, PQ_IP_UC_CTL_OFF_SC2_Main, PQ_IP_UC_CTL_SC2_Main); ++ MDrv_PQ_LoadTable(PQ_SC2_MAIN_WINDOW, PQ_IP_UCDi_OFF_SC2_Main, PQ_IP_UCDi_SC2_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(PQ_SUB_WINDOW == eWindow) ++ { ++ #if defined(AMBER3) ++ MDrv_PQ_LoadTable(PQ_SC2_SUB_WINDOW, PQ_IP_UCNR_OFF_SC2_Sub, PQ_IP_UCNR_SC2_Sub); ++ MDrv_PQ_LoadTable(PQ_SC2_SUB_WINDOW, PQ_IP_UC_CTL_OFF_SC2_Sub, PQ_IP_UC_CTL_SC2_Sub); ++ MDrv_PQ_LoadTable(PQ_SC2_SUB_WINDOW, PQ_IP_UCDi_OFF_SC2_Sub, PQ_IP_UCDi_SC2_Sub); ++ #endif ++ } ++#endif ++#endif ++ ++ bRet = TRUE; ++#else ++ UNUSED(eWindow); ++ bRet = FALSE; ++#endif ++ return bRet; ++} ++ ++E_DRVPQ_ReturnValue MDrv_PQ_GetLibVer(const MSIF_Version **ppVersion) ++{ ++ if(ppVersion == NULL) ++ { ++ return E_DRVPQ_RET_FAIL; ++ } ++ ++ *ppVersion = &_drv_pq_version; ++ return E_DRVPQ_RET_OK; ++} ++ ++ ++PQ_ReturnValue MDrv_PQ_GetInfo(MS_PQ_INFO *pInfo) ++{ ++ MsOS_Memcpy((void*)pInfo, (void*)&_info, sizeof(MS_PQ_INFO)); ++ return E_PQ_RET_OK; ++} ++ ++MS_BOOL MDrv_PQ_GetStatus(MS_PQ_Status *pStatus) ++{ ++ MsOS_Memcpy((void*)pStatus, (void*)&_status, sizeof(MS_PQ_Status)); ++ return FALSE; ++} ++ ++MS_BOOL MDrv_PQ_SetDbgLevel(MS_U16 u16DbgSwitch) ++{ ++ _u16PQDbgSwitch = u16DbgSwitch; ++ return TRUE; ++} ++ ++void MDrv_PQ_Set_DisplayType(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, PQ_WIN ePQWin) ++{ ++ printf("!!!!!SetDisplayType %d %d \r\n", u16DisplayWidth, enDisplaType); ++#if (PQ_ENABLE_PIP) ++#if(ENABLE_PQ_BIN) ++ if(gbPQBinEnable) ++ { ++ if(ePQWin == PQ_SC1_MAIN_WINDOW) ++ { ++ MDrv_PQBin_SetPanelID(0, PQ_SC1_MAIN_WINDOW); ++ MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_ONE, ePQWin); ++ } ++ else ++ { ++ PQ_BIN_DISPLAY_TYPE enBinDispType; ++ ++ MDrv_PQBin_SetPanelID(u16DisplayWidth == 1366 ? 1 : 1, ePQWin); ++ ++ enBinDispType = enDisplaType == PQ_DISPLAY_ONE ? PQ_BIN_DISPLAY_ONE : ++ enDisplaType == PQ_DISPLAY_PIP ? PQ_BIN_DISPLAY_PIP : ++ PQ_BIN_DISPLAY_POP; ++ MDrv_PQBin_SetDisplayType(enBinDispType, ePQWin); ++ } ++ ++ } ++ else ++#endif ++ { ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ MS_BOOL bSkipCommTable = TRUE; ++ ++ if(genDisplayType != enDisplaType) ++ { ++ MDrv_PQ_Set_DisplayType_Sub(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_Main(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Sub(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC2_Main(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ MDrv_PQ_Set_DisplayType_SC1_Main(u16DisplayWidth, enDisplaType, bSkipCommTable); ++ ++ genDisplayType = enDisplaType; ++ } ++ ++#endif // #if PQ_ONLY_SUPPORT_BIN ++ ++ } ++ ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++#endif ++} ++ ++PQ_DISPLAY_TYPE MDrv_PQ_Get_DisplayType(void) ++{ ++#if (PQ_ENABLE_PIP) ++ ++ return genDisplayType; ++#else ++ return PQ_DISPLAY_ONE; ++#endif ++} ++ ++void MDrv_PQ_MADiForceMotionC(PQ_WIN eWindow, MS_BOOL bEnable) ++{ ++ MS_U16 u16DataC = 0; ++ u16DataC = Hal_PQ_get_force_c_motion(eWindow); ++ ++#if (PQ_ENABLE_PIP) ++ if(eWindow == PQ_SUB_WINDOW || eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ u16DataC <<= 8; ++ } ++#endif ++ ++ if(bEnable) ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ u16DataC |= 0x0080; ++ } ++ else ++ { ++ u16DataC |= 0x8000; ++ } ++ } ++ else ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ { ++ u16DataC &= 0x000F; ++ } ++ else ++ { ++ u16DataC &= 0x0F00; ++ } ++ } ++ Hal_PQ_set_force_c_motion(eWindow, u16DataC); ++ ++} ++ ++void MDrv_PQ_MADiForceMotionY(PQ_WIN eWindow, MS_BOOL bEnable) ++{ ++ MS_U16 u16Data = 0; ++ ++ u16Data = Hal_PQ_get_force_y_motion(eWindow); ++ ++#if (PQ_ENABLE_PIP) ++ if(eWindow == PQ_SUB_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC2_SUB_WINDOW ++ #endif ++ ) ++ { ++ u16Data <<= 8; ++ } ++#endif ++ ++ if(bEnable) ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ u16Data |= 0x0080; ++ else ++ u16Data |= 0x8000; ++ } ++ else ++ { ++ if(eWindow == PQ_MAIN_WINDOW ++ #if ENABLE_MULTI_SCALER ++ || eWindow == PQ_SC1_MAIN_WINDOW || eWindow == PQ_SC2_MAIN_WINDOW ++ #endif ++ ) ++ u16Data &= 0x003F; ++ else ++ u16Data &= 0x3F00; ++ } ++ ++ Hal_PQ_set_force_y_motion(eWindow, u16Data); ++} ++ ++void MDrv_PQ_SetRFblMode(MS_BOOL bEnable, MS_BOOL bFilm) ++{ ++ _stRFBL_Info.bEnable = bEnable; ++ _stRFBL_Info.bFilm = bFilm; ++ ++ if(!bEnable) //default mode ++ { ++ MDrv_PQ_MADiForceMotionY(PQ_MAIN_WINDOW, FALSE); ++ MDrv_PQ_MADiForceMotionC(PQ_MAIN_WINDOW, FALSE); ++ ++ _stRFBL_Info.u8MADiType = MS_MADI_24_2R; ++ //printf("[%s]-[%d] : Y/C motion : ( 0 , 0 ) \r\n", __FUNCTION__, __LINE__); ++ } ++ else ++ { ++ _stRFBL_Info.u8MADiType = (bFilm) ? (MS_U8)MS_MADI_24_RFBL_FILM : (MS_U8)MS_MADI_24_RFBL_NFILM; ++ MDrv_PQ_MADiForceMotionY(PQ_MAIN_WINDOW, FALSE); ++ MDrv_PQ_MADiForceMotionC(PQ_MAIN_WINDOW, (!bFilm)); ++ ++ //printf("[%s]-[%d] : Y/C motion : ( 0 , %d) \r\n", __FUNCTION__, __LINE__,(!bFilm)); ++ } ++} ++ ++void MDrv_PQ_GetRFblMode(MS_PQ_RFBL_INFO * pstInfo) ++{ ++ MsOS_Memcpy(pstInfo, &_stRFBL_Info, sizeof(MS_PQ_RFBL_INFO)); ++ return; ++} ++ ++#if (PQ_ENABLE_VD_SAMPLING) ++ ++MS_BOOL MDrv_PQ_Get_VDSampling_Info(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, PQ_VIDEOSTANDARD_TYPE eStandard, MS_PQ_VD_Sampling_Info *pInfo) ++{ ++ PQ_VIDEOSTANDARD_TYPE eCurStandard = _stVD_Info[eWindow].enVideoStandard; ++ MS_U16 u16CurSrc = _u16PQSrcType[eWindow]; ++ MS_U16 u16TableIdx; ++ MS_U16 u16IPIdx = Hal_PQ_get_ip_idx(MS_PQ_IP_VD_SAMPLING); ++ MS_U8 u8SampleTable[10]; ++ ++ MsOS_Memset(u8SampleTable, 0, sizeof(u8SampleTable)); ++ ++ PQINFO_DBG(printf("[PQ] GetVDSampling: win:%d, src:%d, standard:%d, PQIP=%x\r\n", eWindow, enInputSourceType, eStandard, u16IPIdx)); ++ if((((enInputSourceType >= PQ_INPUT_SOURCE_TV) && (enInputSourceType <= PQ_INPUT_SOURCE_SVIDEO))||(enInputSourceType == PQ_INPUT_SOURCE_SCART)) && ++ (eStandard < E_PQ_VIDEOSTANDARD_NOTSTANDARD) && ++ (u16IPIdx != 0xFFFF)) ++ { ++ _stVD_Info[eWindow].enVideoStandard = eStandard; ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ ++ ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ PQINFO_DBG(printf("[PQ] VDSampling: TableIdx=%d\r\n", u16TableIdx)); ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TableIdx == PQ_BIN_IP_NULL)) ++ || ((gbPQBinEnable == 0) && (u16TableIdx == PQ_IP_NULL))) ++#else ++ if(u16TableIdx == PQ_IP_NULL) ++#endif ++ { ++ pInfo->eType = PQ_VD_SAMPLING_OFF; ++ } ++ else ++ { ++ MDrv_PQ_LoadTableData(eWindow, u16TableIdx, u16IPIdx, u8SampleTable, 10); ++ pInfo->u16Vstart = ((MS_U16)u8SampleTable[0]) | (((MS_U16)u8SampleTable[1])<<8); ++ pInfo->u16Hstart = ((MS_U16)u8SampleTable[2]) | (((MS_U16)u8SampleTable[3])<<8); ++ pInfo->u16Hsize = ((MS_U16)u8SampleTable[4]) | (((MS_U16)u8SampleTable[5]) << 8); ++ pInfo->u16Vsize = ((MS_U16)u8SampleTable[6]) | (((MS_U16)u8SampleTable[7]) << 8); ++ pInfo->u16Htt = ((MS_U16)u8SampleTable[8]) | (((MS_U16)u8SampleTable[9]) << 8); ++ pInfo->eType = PQ_VD_SAMPLING_ON; ++ ++ PQINFO_DBG(printf("VD x:%x, y:%x, w:%x, h:%x, Htt=%x \r\n", ++ pInfo->u16Hstart, pInfo->u16Vstart, pInfo->u16Hsize, pInfo->u16Vsize, pInfo->u16Htt)); ++ } ++ ++ _stVD_Info[eWindow].enVideoStandard = eCurStandard; ++ _u16PQSrcType[eWindow] = u16CurSrc; ++ } ++ else ++ { ++ pInfo->eType = PQ_VD_SAMPLING_OFF; ++ } ++ return TRUE; ++} ++ ++#endif ++ ++ ++MS_BOOL _MDrv_PQ_Get_HSDSampling(PQ_WIN eWindow, MS_U32 *pu32ratio, MS_BOOL *bADVMode) ++{ ++#if PQ_ENABLE_HSDRULE ++ ++ MS_U16 u16IPIdx = Hal_PQ_get_ip_idx(MS_PQ_IP_HSD_SAMPLING); ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ if(u16IPIdx != 0xFFFF) ++ { ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ } ++ else ++ { ++#if(ENABLE_PQ_BIN) ++ u16TableIdx = (gbPQBinEnable) ? PQ_BIN_IP_NULL : PQ_IP_NULL; ++#else ++ u16TableIdx = PQ_IP_NULL; ++#endif ++ } ++ ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TableIdx == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TableIdx == PQ_IP_NULL))) ++#else ++ if(u16TableIdx == PQ_IP_NULL) ++#endif ++ { ++ *pu32ratio = 0; ++ bret = FALSE; ++ } ++ ++#if(PQ_ONLY_SUPPORT_BIN) ++ else if((( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_Y_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])) || ++ ( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_C_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])))) ++#elif(ENABLE_PQ_BIN) ++ else if(((gbPQBinEnable == 1) && ++ (( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_Y_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])) || ++ ( MDrv_PQBin_GetSkipRule(PQ_IP_HSD_C_Main, &stPQBinHeaderInfo[PQ_BIN_STD_MAIN])))) ++ || ++ ((MST_SkipRule_IP_Main[PQ_IP_HSD_Y_Main] == 1) || (MST_SkipRule_IP_Main[PQ_IP_HSD_C_Main] == 1)) ++ ) ++#else ++ else if((MST_SkipRule_IP_Main[PQ_IP_HSD_Y_Main] == 1) || (MST_SkipRule_IP_Main[PQ_IP_HSD_C_Main] == 1)) ++#endif ++ { ++ SRULE_DBG(printf("HSD_Y, HSD_C is True in SKipRule, driver consider HSDSampling is not defined in QMap.\r\n")); ++ *pu32ratio = 0; ++ bret = FALSE; ++ } ++ else ++ { ++#if PQ_NEW_HSD_SAMPLING_TYPE ++ if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_000)) ++ { ++ *pu32ratio = 1000; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_125)) ++ { ++ *pu32ratio = 875; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_250)) ++ { ++ *pu32ratio = 750; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_375)) ++ { ++ *pu32ratio = 625; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_500)) ++ { ++ *pu32ratio = 500; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_625)) ++ { ++ *pu32ratio = 375; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_750)) ++ { ++ *pu32ratio = 250; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_1_875)) ++ { ++ *pu32ratio = 125; ++ } ++ else if(u16TableIdx == Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_Div_2_000)) ++ { ++ *pu32ratio = 1; ++ } ++ else ++#endif ++ { ++ *pu32ratio = 0; ++ } ++ ++ bret = TRUE; ++ } ++ ++ // Load HSD_Y & HSD_C ++ if(bret) ++ { ++ MS_U16 u16HSD_Y_idx, u16HSD_C_idx; ++ ++ u16HSD_Y_idx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_HSD_Y_Main); ++ MDrv_PQ_LoadTable(eWindow, u16HSD_Y_idx, PQ_IP_HSD_Y_Main); ++ ++ u16HSD_C_idx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_HSD_C_Main); ++ MDrv_PQ_LoadTable(eWindow, u16HSD_C_idx, PQ_IP_HSD_C_Main); ++ ++ SRULE_DBG(printf("HSD_Y:%d, HSD_C:%d\r\n", u16HSD_Y_idx, u16HSD_C_idx)); ++ ++ *bADVMode = ((u16HSD_Y_idx == PQ_IP_HSD_Y_CB_Main) && ++ (u16HSD_C_idx == PQ_IP_HSD_C_CB_Main)) ? FALSE : TRUE; ++ } ++ else ++ { ++ *bADVMode = FALSE; ++ } ++ ++ ++ SRULE_DBG(printf("[PQ] GetHSDSampling, IPIdx=%d, Table=%d, ratio=%ld ret=%d\r\n", u16IPIdx, u16TableIdx, *pu32ratio, bret)); ++ ++ return bret; ++#else ++ return TRUE; ++#endif ++ ++} ++ ++ ++MS_BOOL MDrv_PQ_IOCTL(PQ_WIN eWindow, MS_U32 u32Flag, void *pBuf, MS_U32 u32BufSize) ++{ ++ MS_BOOL bret = TRUE; ++ ++ switch(u32Flag) ++ { ++ case E_PQ_IOCTL_HSD_SAMPLING: ++ { ++ if(u32BufSize == sizeof(PQ_HSD_SAMPLING_INFO)) ++ { ++ MS_U32 u32ratio; ++ MS_BOOL bADVMode; ++ ++ bret = _MDrv_PQ_Get_HSDSampling(eWindow, &u32ratio, &bADVMode); ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->u32ratio = u32ratio; ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->bADVMode = bADVMode; ++ bret = TRUE; ++ ++ //printf("ratio %lx, bADVmode=%d\r\n\r\n",((PQ_HSD_SAMPLING_INFO *)pBuf)->u32ratio, ((PQ_HSD_SAMPLING_INFO *)pBuf)->bADVMode); ++ ++ } ++ else ++ { ++ //printf("Size is not correct, in=%ld, %d\r\n", u32BufSize, sizeof(PQ_HSD_SAMPLING_INFO)); ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->u32ratio = 0; ++ ((PQ_HSD_SAMPLING_INFO *)pBuf)->bADVMode = 0; ++ bret = FALSE; ++ } ++ break; ++ } ++ ++ case E_PQ_IOCTL_PREVSD_BILINEAR: ++ bret = TRUE; ++ *((MS_BOOL *)pBuf) = TRUE; ++ break; ++ ++ case E_PQ_IOCTL_ADC_SAMPLING: ++ if(u32BufSize == sizeof(PQ_ADC_SAMPLING_INFO)) ++ { ++ ++ PQ_INPUT_SOURCE_TYPE enInputSrc = ((PQ_ADC_SAMPLING_INFO *)pBuf)->enPQSourceType; ++ MS_PQ_Mode_Info *pModeInfo = &(((PQ_ADC_SAMPLING_INFO *)pBuf)->stPQModeInfo); ++ MS_PQ_ADC_SAMPLING_TYPE enADCSamplingType = MDrv_PQ_Get_ADCSampling_Info(eWindow, enInputSrc, pModeInfo); ++ ++ if((enADCSamplingType == E_PQ_ADC_SAMPLING_NOT_SUPPORT) || (enADCSamplingType == E_PQ_ADC_SAMPLING_NONE)) ++ { ++ ((PQ_ADC_SAMPLING_INFO *)pBuf)->u16ratio = 1; ++ bret = FALSE; ++ } ++ else ++ { ++ ((PQ_ADC_SAMPLING_INFO *)pBuf)->u16ratio = (MS_U16)enADCSamplingType; ++ bret = TRUE; ++ } ++ } ++ else ++ { ++ bret = FALSE; ++ ((PQ_ADC_SAMPLING_INFO *)pBuf)->u16ratio = 1; ++ } ++ break; ++ case E_PQ_IOCTL_RFBL_CTRL: ++ //printf("IOCTL %lx\r\n", u32Flag); ++#if PQ_ENABLE_RFBL ++ bret = MDrv_PQ_Get_RFBL_Info(eWindow); ++#else ++ bret = FALSE; ++#endif ++ UNUSED(pBuf); ++ UNUSED(u32BufSize); ++ break; ++ ++ default: ++ printf("unknown IOCTL %lx\r\n", u32Flag); ++ UNUSED(pBuf); ++ UNUSED(u32BufSize); ++ bret = FALSE; ++ break; ++ } ++ ++ //printf("[PQ] IOCTL : win:%x, Flag=%08lx, size=%ld, ret:%x\r\n", eWindow, u32Flag, u32BufSize, bret); ++ ++ return bret; ++} ++ ++ ++MS_PQ_ADC_SAMPLING_TYPE MDrv_PQ_Get_ADCSampling_Info(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info *pstPQModeInfo) ++{ ++ MS_PQ_ADC_SAMPLING_TYPE enRetType; ++ MS_U16 u16PQSrcType; ++ MS_U16 u16TableIdx; ++ MS_PQ_Mode_Info stModeInfo; ++ ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ MsOS_Memcpy(&stModeInfo, &_stMode_Info[eWindow], sizeof(MS_PQ_Mode_Info)); ++ ++ MDrv_PQ_Set_ModeInfo(eWindow, enInputSourceType, pstPQModeInfo); ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ ++ if(Hal_PQ_get_ip_idx(MS_PQ_IP_ADC_SAMPLING) == 0xFFFF) ++ { ++ return E_PQ_ADC_SAMPLING_NOT_SUPPORT; ++ } ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, Hal_PQ_get_ip_idx(MS_PQ_IP_ADC_SAMPLING)); ++ ++ if(u16TableIdx == Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_X_1)) ++ { ++ enRetType = E_PQ_ADC_SAMPLING_X_1; ++ } ++ else if(u16TableIdx == Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_X_2)) ++ { ++ enRetType = E_PQ_ADC_SAMPLING_X_2; ++ } ++ else if(u16TableIdx == Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_X_4)) ++ { ++ enRetType = E_PQ_ADC_SAMPLING_X_4; ++ } ++ else ++ { ++ enRetType = E_PQ_ADC_SAMPLING_NONE; ++ } ++ ++ MsOS_Memcpy(&_stMode_Info[eWindow], &stModeInfo, sizeof(MS_PQ_Mode_Info)); ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ ++ return enRetType; ++} ++ ++MS_BOOL MDrv_PQ_Set3D_OnOff(MS_BOOL bEn) ++{ ++ _gIs3D_En = bEn; ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_SetH264_OnOff(MS_BOOL bEn) ++{ ++ _gIsH264 = bEn; ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_SetMM_OnOff(MS_BOOL bEn) ++{ ++ _gIsMMplayer = bEn; ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetCaps(MS_PQ_CAP_INFO *pInfo) ++{ ++ MS_BOOL bRet = TRUE; ++#if(PQ_ENABLE_PIP) ++ const XC_ApiInfo* pXC_ApiInfo = MApi_XC_GetInfo(); ++ if (pXC_ApiInfo != NULL) ++ { ++ pInfo->bPIP_Supported = ((pXC_ApiInfo->u8MaxWindowNum) >= 2) ? TRUE : FALSE; ++ } ++ else ++ { ++ pInfo->bPIP_Supported = FALSE; ++ bRet = FALSE; ++ } ++#else ++ pInfo->bPIP_Supported = FALSE; ++#endif ++ ++#if(PQ_ENABLE_3D_VIDEO) ++ pInfo->b3DVideo_Supported = TRUE; ++#else ++ pInfo->b3DVideo_Supported = FALSE; ++#endif ++ ++ return bRet; ++} ++ ++void MDRV_PQ_PrintLoadTableInfo(MS_PQ_PQLOADTABLE_WIN enPQWin) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++ MS_U16 u16IPIdx; ++ MS_U8 u8TabIdx; ++ MS_U16 u16IPNum; ++ ++ if(enPQWin == PQ_LOAD_TABLE_MAIN) ++ printf("[TableInfo::Main] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_MAIN_EX) ++ printf("[TableInfo::Main Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SUB) ++ printf("[TableInfo::SUB] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SUB_EX) ++ printf("[TableInfo::SUB Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN) ++ printf("[TableInfo::SC1_Main] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN_EX) ++ printf("[TableInfo::SC1_Main Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN) ++ printf("[TableInfo::SC2_Main] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN_EX) ++ printf("[TableInfo::SC2_Main Ex] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB) ++ printf("[TableInfo::SC2_SUB] \r\n"); ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB_EX) ++ printf("[TableInfo::SC2_SUB Ex] \r\n"); ++ else ++ return; ++ ++ u16IPNum = enPQWin == PQ_LOAD_TABLE_MAIN ? PQ_IP_NUM_Main : ++ enPQWin == PQ_LOAD_TABLE_MAIN_EX ? PQ_IP_NUM_Main_Ex : ++ enPQWin == PQ_LOAD_TABLE_SUB ? PQ_IP_NUM_Sub : ++ enPQWin == PQ_LOAD_TABLE_SUB_EX ? PQ_IP_NUM_Sub_Ex : ++ enPQWin == PQ_LOAD_TABLE_SC1_MAIN ? PQ_IP_NUM_SC1_Main : ++ enPQWin == PQ_LOAD_TABLE_SC1_MAIN_EX ? PQ_IP_NUM_SC1_Main_Ex : ++ enPQWin == PQ_LOAD_TABLE_SC2_MAIN ? PQ_IP_NUM_SC2_Main : ++ enPQWin == PQ_LOAD_TABLE_SC2_MAIN_EX ? PQ_IP_NUM_SC2_Main_Ex : ++ enPQWin == PQ_LOAD_TABLE_SC2_SUB ? PQ_IP_NUM_SC2_Sub : ++ enPQWin == PQ_LOAD_TABLE_SC2_SUB_EX ? PQ_IP_NUM_SC2_Sub_Ex : ++ 0; ++ ++ for(u16IPIdx = 0; u16IPIdx < u16IPNum; ++ u16IPIdx) ++ { ++ printf(" %u(%s)=", u16IPIdx, MDrv_PQ_GetIPName(u16IPIdx)); // IP Name ++ ++ if(enPQWin == PQ_LOAD_TABLE_MAIN) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(MAIN, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_MAIN_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(MAINEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ } ++ ++#if PQ_ENABLE_PIP ++ else if(enPQWin == PQ_LOAD_TABLE_SUB) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SUB, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SUB_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SUBEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ ++ } ++#endif ++ ++#if defined(CEDRIC) ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC1_MAIN, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SC1_MAIN_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC1_MAINEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ } ++ ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_MAIN, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_MAIN_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_MAINEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ } ++ ++#if PQ_ENABLE_PIP ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_SUB, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("%u(%s)\r\n", u8TabIdx, MDrv_PQ_GetTableName(u16IPIdx, u8TabIdx)); ++ } ++ else if(enPQWin == PQ_LOAD_TABLE_SC2_SUB_EX) ++ { ++ u8TabIdx = MDrv_PQ_Get_LoadTableInfo_IP_Tab(SC2_SUBEX, u16IPIdx); ++ if(u8TabIdx == 0xFF) ++ printf("_____\r\n"); ++ else ++ printf("Tab%u\r\n", u8TabIdx); ++ ++ } ++#endif ++ ++#endif // CEDRIC ++ else ++ { ++ } ++ } ++#else ++ UNUSED(enPQWin); ++#endif ++} ++ ++MS_BOOL MDrv_PQ_SetDS_OnOFF(PQ_WIN eWindow, MS_BOOL bEn) ++{ ++ //store the original value ++ _u16RW_Method = Hal_PQ_get_rw_method(eWindow); ++ if(bEn) ++ { ++ _bDS_En = TRUE; ++ } ++ else ++ { ++ _bDS_En = FALSE; ++ Hal_PQ_set_rw_method(eWindow, _u16RW_Method); ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_Get_RFBL_Info(PQ_WIN eWindow) ++{ ++#if 0//Ryan ++ ++ MS_BOOL bret = TRUE; ++ ++ MS_U16 u16TabIdx_MADi = 0; ++// PQ_WIN eWindow = (bIsMainWindow == TRUE) ? (PQ_MAIN_WINDOW):(PQ_SUB_WINDOW); ++ ++ u16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Main); ++ (printf("[PQ] MADI: u16TabIdx_MADi=%d\r\n", u16TabIdx_MADi)); ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TabIdx_MADi == PQ_BIN_IP_NULL)) || ++ ((gbPQBinEnable == 0) && (u16TabIdx_MADi == PQ_IP_NULL))) ++#else ++ if(u16TabIdx_MADi == PQ_IP_NULL) ++#endif ++ { ++ MApi_XC_EnableRequest_FrameBufferLess(DISABLE); ++ ++ bret = FALSE; ++ printf("[PQ] MADI: Get Null\r\n"); ++ printf("[PQ] MADI: DISABLE RFBL\r\n"); ++ ++ } ++ else ++ { ++ if((u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_2D)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_25D)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_YC)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_FILM)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE10_MOT)) ++ || (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE8_MOT)) ++ ++ ) ++ { ++ MApi_XC_EnableRequest_FrameBufferLess(ENABLE); ++ printf("[PQ] MADI: ENABLE RFBL\r\n"); ++ ++ } ++ else ++ { ++ MApi_XC_EnableRequest_FrameBufferLess(DISABLE); ++ printf("[PQ] MADI: DISABLE RFBL\r\n"); ++ ++ } ++ bret = TRUE; ++ } ++ ++ return bret; ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_CheckHDMode(PQ_WIN eWindow) ++{ ++ return _gIsSrcHDMode[eWindow]; ++} ++ ++//for Super Resolution interlace and SD mode detected use ++MS_BOOL MDrv_PQ_Get_Interlace_SD_mode(PQ_WIN ePQWin) ++{ ++ if(QM_IsInterlaced(ePQWin) && (QM_GetInputHSize(ePQWin) < 1500)) ++ { ++ return TRUE; ++ } ++ else ++ { ++ return FALSE; ++ } ++} ++ ++#if PQ_GRULE_PTP_ENABLE ++static void _MDrv_PQ_LoadPTPTable(PQ_WIN eWindow, MS_U16 u16PQ_PTP_Idx) ++{ ++ MS_U16 i, u16IPIdx=0, u16TabIdx=0; ++ ++ if (u16PQ_PTP_Idx > PQ_GRULE_PTP_LVL_NUM_Main){ ++ MS_ASSERT(0); return; ++ } ++ ++ for(i=0; istDispWin.x = (_stPQ_Info.u16PnlWidth - pstXC_SetWin_Info->stCropWin.width)/2; ++ pstXC_SetWin_Info->stDispWin.width = pstXC_SetWin_Info->stCropWin.width; ++ pstXC_SetWin_Info->stDispWin.y = (_stPQ_Info.u16PnlHeight- pstXC_SetWin_Info->stCropWin.height)/2; ++ pstXC_SetWin_Info->stDispWin.height = pstXC_SetWin_Info->stCropWin.height; ++ ++ //RGB HDMI, DVI, VGA ++ if((((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == TRUE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == FALSE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ (IsSrcTypeVga(pstXC_SetWin_Info->enInputSourceType))) && ++ (!pstXC_SetWin_Info->bInterlace)) ++ { ++ MApi_XC_EnableForceRGBin(TRUE, MAIN_WINDOW); ++ } ++ MApi_XC_Set_MemFmt(E_MS_XC_MEM_FMT_444); ++ } ++ else ++ { ++ MApi_XC_EnableForceRGBin(FALSE, MAIN_WINDOW); ++ MApi_XC_Set_MemFmt(E_MS_XC_MEM_FMT_AUTO); ++ } ++ ++ PQP2P_DBG(printf("[MDrv_PQ_Set_PointToPoint] True or False: %u\r\n",bEnable);) ++ _bPointToPointMode = bEnable; ++ ++ return TRUE; ++#endif ++} ++#endif ++ ++MS_BOOL MDrv_PQ_Get_PointToPoint(PQ_WIN eWindow) ++{ ++ UNUSED(eWindow); ++ return _bPointToPointMode; ++} ++ ++#if 0//Ryan ++MS_BOOL MDrv_PQ_Check_PointToPoint_Condition(XC_SETWIN_INFO *pstXC_SetWin_Info,PQ_WIN eWindow) ++{ ++ MS_BOOL bRet = FALSE; ++ ++ UNUSED(eWindow); ++ ++#if PQ_GRULE_PTP_ENABLE ++ // HDMI RGB, HDMI YUV444, DVI, YPbPr, VGA. ++ // all in progressive mode ++ PQP2P_DBG(printf("----HDMI source=%u, HDMIPacket=%u, RGB=%u, YUV444=%u, Ypbpr=%u, VGA=%u, interlace=%u\r\n", ++ (IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)), ++ (_stHDMI_Info[eWindow].bIsHDMI == TRUE), ++ (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW)), ++ (QM_HDMIPC_COLORYUV444(PQ_MAIN_WINDOW)), ++ (IsSrcTypeYPbPr(pstXC_SetWin_Info->enInputSourceType)), ++ (IsSrcTypeVga(pstXC_SetWin_Info->enInputSourceType)), ++ (pstXC_SetWin_Info->bInterlace) ++ );) ++ //at this time, the PQ input source has not been inited. so we use XC_SETWIN_INFO to check ++ //we cannot do the PTP when timing size is bigger than panel size ++ if((((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == TRUE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == TRUE) && (QM_HDMIPC_COLORYUV444(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == FALSE) && (QM_HDMIPC_COLORYUV444(PQ_MAIN_WINDOW))) || ++ ((IsSrcTypeHDMI(pstXC_SetWin_Info->enInputSourceType)) && (_stHDMI_Info[eWindow].bIsHDMI == FALSE) && (QM_HDMIPC_COLORRGB(PQ_MAIN_WINDOW))) || ++ (IsSrcTypeVga(pstXC_SetWin_Info->enInputSourceType)) || ++ (IsSrcTypeYPbPr(pstXC_SetWin_Info->enInputSourceType))) && ++ (!pstXC_SetWin_Info->bInterlace) && ++ ((_stPQ_Info.u16PnlWidth >= pstXC_SetWin_Info->stCropWin.width) && (_stPQ_Info.u16PnlHeight >= pstXC_SetWin_Info->stCropWin.height))) ++ { ++ bRet = TRUE; ++ } ++#else ++ UNUSED(pstXC_SetWin_Info); ++#endif ++ ++ PQP2P_DBG(printf("[MDrv_PQ_Check_PointToPoint_Condition] %u\r\n",bRet);) ++ ++ return bRet; ++} ++#endif ++ ++MS_BOOL MDrv_PQ_Update_MemFormat(void) ++{ ++ MS_U8 u8BitPerPixel = 0; ++ MDrv_PQ_SetMemFormat( ++ PQ_MAIN_WINDOW, ++ _gbMemfmt422[PQ_MAIN_WINDOW], ++ _stMode_Info[PQ_MAIN_WINDOW].bFBL, ++ &u8BitPerPixel); ++ ++ return TRUE; ++} ++ ++MS_U16 MDrv_PQ_GetVsize(void) ++{ ++ return _stMode_Info[PQ_MAIN_WINDOW].u16input_vsize; ++} ++ ++MS_BOOL MDrv_PQ_LOW_3dQuality(MS_BOOL bEnable) ++{ ++ if(bEnable) ++ { ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_Peaking_band_AV_NTSC_Main, PQ_IP_VIP_Peaking_band_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_VNMR_S2_Main, PQ_IP_VIP_VNMR_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_VLPF_coef1_0x6_Main, PQ_IP_VIP_VLPF_coef1_Main); ++#endif ++ } ++ else ++ { ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_Peaking_band_Main), PQ_IP_VIP_Peaking_band_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_VNMR_Main), PQ_IP_VIP_VNMR_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_VLPF_coef1_Main), PQ_IP_VIP_VLPF_coef1_Main); ++#endif ++ } ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_SetEnhanceQuality(void) ++{ ++#if PQ_VIP_RGBCMY_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_R_INC_3_Main, PQ_IP_VIP_ICC_R_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_G_INC_8_Main, PQ_IP_VIP_ICC_G_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_B_INC_6_Main, PQ_IP_VIP_ICC_B_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_C_INC_6_Main, PQ_IP_VIP_ICC_C_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_M_INC_6_Main, PQ_IP_VIP_ICC_M_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_Y_INC_7_Main, PQ_IP_VIP_ICC_Y_Main); ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_RestoreEnhanceQuality(void) ++{ ++#if PQ_VIP_RGBCMY_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_R_Main), PQ_IP_VIP_ICC_R_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_G_Main), PQ_IP_VIP_ICC_G_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_B_Main), PQ_IP_VIP_ICC_B_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_C_Main), PQ_IP_VIP_ICC_C_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_M_Main), PQ_IP_VIP_ICC_M_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, MDrv_PQ_GetTableIndex(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_Y_Main), PQ_IP_VIP_ICC_Y_Main); ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_RestoreOffQuality(void) ++{ ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_ON_Main, PQ_IP_VIP_ICC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IBC_ON_Main, PQ_IP_VIP_IBC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IHC_ON_Main, PQ_IP_VIP_IHC_Main); ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_MWE_SetOffQuality(void) ++{ ++#if PQ_VIP_CTL ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_ICC_OFF_Main, PQ_IP_VIP_ICC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IBC_OFF_Main, PQ_IP_VIP_IBC_Main); ++ MDrv_PQ_LoadTable(PQ_MAIN_WINDOW, PQ_IP_VIP_IHC_OFF_Main, PQ_IP_VIP_IHC_Main); ++#endif ++ return TRUE; ++} ++ ++//------------------------------------------------------------------------------------------------- ++// selection to VIP CSC ++// Both equation selection rules are ++// 0: SDTV(601) R G B : 16-235 ++// 1: SDTV(601) R G B : 0-255 ++/// @param bMainWin \b IN: Enable ++//------------------------------------------------------------------------------------------------- ++void MDrv_PQ_SetSelectCSC(MS_U16 u16selection, PQ_WIN ePQWin) ++{ ++ HAL_PQ_set_SelectCSC(u16selection, ePQWin); ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_Sub(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++ ++#if PQ_ENABLE_PIP && (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ PQTableInfo.eWin = PQ_SUB_WINDOW; ++ // Load Sub PQ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_Sub; ++ #endif ++ } ++ break; ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SUB_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Sub; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_Sub; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Sub; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_Sub; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_Sub; ++ #endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_Sub; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_Sub; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_Sub; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_Sub; ++#endif ++ ++ ++ MDrv_PQ_AddTable_(SUB, &PQTableInfo); ++ ++ ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SUB); ++ } ++ ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_Sub_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_Sub_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_Sub_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_Sub_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_Sub_Ex; ++ } ++ break; ++ } ++ MDrv_PQ_AddTable_(SUBEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SUBEX); ++ } ++ ++ return TRUE; ++ ++ ++#else ++ ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++ ++#endif ++} ++ ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_SC1_Main(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if 0//Ryan ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ printf("++++MDrv_PQ_Set_DisplayType_SC1_Main++++ \r\n"); ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfo.pQuality_Map_Aray = (void*)(QMAP_720_SC1_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)(MST_GRule_720_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)(MST_GRule_720_MPEG_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)(MST_GRule_720_FILM_MODE_SC1_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)(MST_GRule_720_DYNAMIC_CONTRAST_SC1_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)(MST_GRule_720_ULTRAT_CLEAR_SC1_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)(MST_GRule_720_DDR_SELECT_SC1_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)(MST_GRule_720_OSD_BW_SC1_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)(MST_GRule_PTP_SC1_Main); ++#endif ++ break; ++#if PQ_ENABLE_PIP_SC1 //// JoshChiang++, 20120730 //// ++ case PQ_DISPLAY_PIP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_PIP_SC1_Main: QMAP_1920_PIP_SC1_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_NR_SC1_Main: MST_GRule_1920_PIP_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_MPEG_NR_SC1_Main:MST_GRule_1920_PIP_MPEG_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_FILM_MODE_SC1_Main:MST_GRule_1920_PIP_FILM_MODE_SC1_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC1_Main:MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC1_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_ULTRAT_CLEAR_SC1_Main:MST_GRule_1920_PIP_ULTRAT_CLEAR_SC1_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DDR_SELECT_SC1_Main:MST_GRule_1920_PIP_DDR_SELECT_SC1_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_OSD_BW_SC1_Main:MST_GRule_1920_PIP_OSD_BW_SC1_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_PTP_SC1_Main:MST_GRule_1920_PIP_PTP_SC1_Main); ++#endif ++ ++ break; ++ ++ case PQ_DISPLAY_POP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_POP_SC1_Main: QMAP_1920_POP_SC1_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_NR_SC1_Main: MST_GRule_1920_POP_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_MPEG_NR_SC1_Main:MST_GRule_1920_POP_MPEG_NR_SC1_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_FILM_MODE_SC1_Main:MST_GRule_1920_POP_FILM_MODE_SC1_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC1_Main:MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC1_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_ULTRAT_CLEAR_SC1_Main:MST_GRule_1920_POP_ULTRAT_CLEAR_SC1_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DDR_SELECT_SC1_Main:MST_GRule_1920_POP_DDR_SELECT_SC1_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_OSD_BW_SC1_Main:MST_GRule_1920_POP_OSD_BW_SC1_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_PTP_SC1_Main:MST_GRule_1920_POP_PTP_SC1_Main); ++#endif ++ break; ++#endif ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SC1_MAIN_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC1_Main; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_SC1_Main; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC1_Main; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_SC1_Main; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_SC1_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_SC1_Main; ++#endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_SC1_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_SC1_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_SC1_Main; ++#endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_SC1_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_SC1_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_SC1_Main; ++#endif ++ ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_PTP] = PQ_GRULE_PTP_NUM_SC1_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_PTP] = PQ_GRULE_PTP_IP_NUM_SC1_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_PTP] = (void*)MST_GRule_PTP_IP_Index_SC1_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_PTP] = (void*)MST_GRule_PTP_SC1_Main; ++#endif ++ ++ MDrv_PQ_AddTable_(SC1_MAIN, &PQTableInfo); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC1_MAIN); ++ } ++ ++#if (ENABLE_PQ_EX) ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC1_Main_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_SC1_Main_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC1_Main_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_SC1_Main_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_720_SC1_Main_Ex; ++ break; ++ ++ case PQ_DISPLAY_PIP: ++#if PQ_ENABLE_PIP_SC1 //// JoshChiang++, 20120730 //// ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC1_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC1_Main_Ex; ++ } ++#endif ++ break; ++ ++ case PQ_DISPLAY_POP: ++#if PQ_ENABLE_PIP_SC1 //// JoshChiang++, 20120730 //// ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC1_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC1_Main_Ex; ++ } ++#endif ++ break; ++ } ++ ++ MDrv_PQ_AddTable_(SC1_MAINEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC1_MAINEX); ++ } ++ if((MS_U16)QM_INPUTTYPE_NUM_SC1_Main != (MS_U16)QM_INPUTTYPE_NUM_SC1_Main_Ex) ++ { ++ printf("PQ INPUTTYPE NUM MISMATCH: MAIN != EX"); ++ MS_ASSERT(0); ++ } ++#endif ++ return TRUE; ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++#endif ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_SC2_Main(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if 0//Ryan ++#if (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ printf("++++MDrv_PQ_Set_DisplayType_SC2_Main++++ \r\n"); ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_SC2_Main: QMAP_1920_SC2_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_NR_SC2_Main: MST_GRule_1920_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_MPEG_NR_SC2_Main:MST_GRule_1920_MPEG_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_FILM_MODE_SC2_Main:MST_GRule_1920_FILM_MODE_SC2_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DYNAMIC_CONTRAST_SC2_Main:MST_GRule_1920_DYNAMIC_CONTRAST_SC2_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_ULTRAT_CLEAR_SC2_Main:MST_GRule_1920_ULTRAT_CLEAR_SC2_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_DDR_SELECT_SC2_Main:MST_GRule_1920_DDR_SELECT_SC2_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_OSD_BW_SC2_Main:MST_GRule_1920_OSD_BW_SC2_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PTP_SC2_Main:MST_GRule_1920_PTP_SC2_Main); ++#endif ++ break; ++#if PQ_ENABLE_PIP ++ case PQ_DISPLAY_PIP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_PIP_SC2_Main: QMAP_1920_PIP_SC2_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_NR_SC2_Main: MST_GRule_1920_PIP_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_MPEG_NR_SC2_Main:MST_GRule_1920_PIP_MPEG_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_FILM_MODE_SC2_Main:MST_GRule_1920_PIP_FILM_MODE_SC2_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC2_Main:MST_GRule_1920_PIP_DYNAMIC_CONTRAST_SC2_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_ULTRAT_CLEAR_SC2_Main:MST_GRule_1920_PIP_ULTRAT_CLEAR_SC2_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_DDR_SELECT_SC2_Main:MST_GRule_1920_PIP_DDR_SELECT_SC2_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_OSD_BW_SC2_Main:MST_GRule_1920_PIP_OSD_BW_SC2_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_PIP_PTP_SC2_Main:MST_GRule_1920_PIP_PTP_SC2_Main); ++#endif ++ ++ break; ++ ++ case PQ_DISPLAY_POP: ++ PQTableInfo.pQuality_Map_Aray = (void*)((u16DisplayWidth == 1366)?QMAP_1920_POP_SC2_Main: QMAP_1920_POP_SC2_Main); ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_NR_SC2_Main: MST_GRule_1920_POP_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_MPEG_NR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_MPEG_NR_SC2_Main:MST_GRule_1920_POP_MPEG_NR_SC2_Main); ++#endif ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_FilmMode] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_FILM_MODE_SC2_Main:MST_GRule_1920_POP_FILM_MODE_SC2_Main); ++#endif ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_DynContr] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC2_Main:MST_GRule_1920_POP_DYNAMIC_CONTRAST_SC2_Main); ++#endif ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_ULTRACLEAR] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_ULTRAT_CLEAR_SC2_Main:MST_GRule_1920_POP_ULTRAT_CLEAR_SC2_Main); ++#endif ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_DDR_SELECT] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_DDR_SELECT_SC2_Main:MST_GRule_1920_POP_DDR_SELECT_SC2_Main); ++#endif ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_OSD_BW] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_OSD_BW_SC2_Main:MST_GRule_1920_POP_OSD_BW_SC2_Main); ++#endif ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.pGRule_Level[E_GRULE_PTP] = ++ (void*)((u16DisplayWidth == 1366)?MST_GRule_1920_POP_PTP_SC2_Main:MST_GRule_1920_POP_PTP_SC2_Main); ++#endif ++ break; ++#endif ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SC2_MAIN_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Main; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_SC2_Main; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Main; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Main; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_SC2_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_SC2_Main; ++#endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_SC2_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_SC2_Main; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_SC2_Main; ++#endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_SC2_Main; ++#if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_SC2_Main; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_MPEG_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_MPEG_NR] = PQ_GRULE_MPEG_NR_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_MPEG_NR] = (void*)MST_GRule_MPEG_NR_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_FILM_MODE_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_FilmMode] = PQ_GRULE_FILM_MODE_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_FilmMode] = (void*)MST_GRule_FILM_MODE_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_DYNAMIC_CONTRAST_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DynContr] = PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DynContr] = (void*)MST_GRule_DYNAMIC_CONTRAST_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_ULTRAT_CLEAR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_ULTRACLEAR] = PQ_GRULE_ULTRAT_CLEAR_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_ULTRACLEAR] = (void*)MST_GRule_ULTRAT_CLEAR_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_DDR_SELECT] = PQ_GRULE_DDR_SELECT_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_DDR_SELECT] = (void*)MST_GRule_DDR_SELECT_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_OSD_BW_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_OSD_BW] = PQ_GRULE_OSD_BW_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_OSD_BW] = (void*)MST_GRule_OSD_BW_SC2_Main; ++#endif ++ ++#if (PQ_GRULE_PTP_ENABLE == 1) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_PTP] = PQ_GRULE_PTP_NUM_SC2_Main; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_PTP] = PQ_GRULE_PTP_IP_NUM_SC2_Main; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_PTP] = (void*)MST_GRule_PTP_IP_Index_SC2_Main; ++ PQTableInfo.pGRule_Array[E_GRULE_PTP] = (void*)MST_GRule_PTP_SC2_Main; ++#endif ++ ++ MDrv_PQ_AddTable_(SC2_MAIN, &PQTableInfo); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_MAIN); ++ } ++ ++#if (ENABLE_PQ_EX) ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Main_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_SC2_Main_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Main_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Main_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Main_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++#if PQ_ENABLE_PIP ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Main_Ex; ++ } ++#endif ++ break; ++ ++ case PQ_DISPLAY_POP: ++#if PQ_ENABLE_PIP ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Main_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Main_Ex; ++ } ++#endif ++ break; ++ } ++ ++ MDrv_PQ_AddTable_(SC2_MAINEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_MAINEX); ++ } ++ if((MS_U16)QM_INPUTTYPE_NUM_SC2_Main != (MS_U16)QM_INPUTTYPE_NUM_SC2_Main_Ex) ++ { ++ printf("PQ INPUTTYPE NUM MISMATCH: MAIN != EX"); ++ MS_ASSERT(0); ++ } ++#endif ++ return TRUE; ++#else ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++#endif ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_Set_DisplayType_SC2_Sub(MS_U16 u16DisplayWidth, PQ_DISPLAY_TYPE enDisplaType, MS_BOOL bSkipCommTable) ++{ ++#if 0//Ryan ++#if PQ_ENABLE_PIP && (PQ_ONLY_SUPPORT_BIN == 0) ++ PQTABLE_INFO PQTableInfo; ++ PQTABLE_INFO PQTableInfoEx; ++ ++ MsOS_Memset(&PQTableInfo, 0, sizeof(PQTABLE_INFO)); ++ MsOS_Memset(&PQTableInfoEx, 0, sizeof(PQTABLE_INFO)); ++ ++ printf("++++MDrv_PQ_Set_DisplayType_SC2_Sub++++ \r\n"); ++ // Load SC2_Sub PQ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_SC2_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_NR_SC2_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_SC2_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_PIP_NR_SC2_Sub; ++ #endif ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_SC2_Sub; ++ #endif ++ } ++ else ++ { ++ PQTableInfo.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub; ++ #if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.pGRule_Level[E_GRULE_NR] = (void*)MST_GRule_1920_POP_NR_SC2_Sub; ++ #endif ++ } ++ break; ++ } ++ ++ // table config parameter ++ PQTableInfo.eWin = PQ_SC2_SUB_WINDOW; ++ PQTableInfo.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_IP_Num = PQ_IP_NUM_SC2_Sub; ++ PQTableInfo.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Sub; ++ PQTableInfo.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Sub; ++ ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSD] = PQ_HSDRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSD] = PQ_VSDRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_HSP] = PQ_HSPRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_VSP] = PQ_VSPRule_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_CSC] = PQ_CSCRule_IP_NUM_SC2_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_NTSC] = PQ_DBRule_NTSC_IP_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_XRule_IP_Num[E_XRULE_DB_PAL] = PQ_DBRule_PAL_IP_NUM_SC2_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSD] = (void*)MST_HSDRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSD] = (void*)MST_VSDRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_HSP] = (void*)MST_HSPRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_VSP] = (void*)MST_VSPRule_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_CSC] = (void*)MST_CSCRule_IP_Index_SC2_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_IP_Index_SC2_Sub; ++ PQTableInfo.pXRule_IP_Index[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_IP_Index_SC2_Sub; ++ #endif ++ ++ PQTableInfo.pXRule_Array[E_XRULE_HSD] = (void*)MST_HSDRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSD] = (void*)MST_VSDRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_HSP] = (void*)MST_HSPRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_VSP] = (void*)MST_VSPRule_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_CSC] = (void*)MST_CSCRule_Array_SC2_Sub; ++ #if (PQ_XRULE_DB_ENABLE == 1) ++ PQTableInfo.pXRule_Array[E_XRULE_DB_NTSC] = (void*)MST_DBRule_NTSC_Array_SC2_Sub; ++ PQTableInfo.pXRule_Array[E_XRULE_DB_PAL] = (void*)MST_DBRule_PAL_Array_SC2_Sub; ++ #endif ++ ++#if (PQ_GRULE_NR_ENABLE) ++ PQTableInfo.u8PQ_GRule_Num[E_GRULE_NR] = PQ_GRULE_NR_NUM_SC2_Sub; ++ PQTableInfo.u8PQ_GRule_IPNum[E_GRULE_NR] = PQ_GRULE_NR_IP_NUM_SC2_Sub; ++ PQTableInfo.pGRule_IP_Index[E_GRULE_NR] = (void*)MST_GRule_NR_IP_Index_SC2_Sub; ++ PQTableInfo.pGRule_Array[E_GRULE_NR] = (void*)MST_GRule_NR_SC2_Sub; ++#endif ++ ++ ++ MDrv_PQ_AddTable_(SC2_SUB, &PQTableInfo); ++ ++ ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_SUB); ++ } ++ ++ // table config parameter ++ PQTableInfoEx = PQTableInfo; ++ ++ PQTableInfoEx.u8PQ_InputType_Num = QM_INPUTTYPE_NUM_SC2_Sub_Ex; ++ PQTableInfoEx.u8PQ_IP_Num = PQ_IP_NUM_SC2_Sub_Ex; ++ PQTableInfoEx.pIPTAB_Info = (void*)PQ_IPTAB_INFO_SC2_Sub_Ex; ++ PQTableInfoEx.pSkipRuleIP = (void*)MST_SkipRule_IP_SC2_Sub_Ex; ++ ++ switch(enDisplaType) ++ { ++ default: ++ case PQ_DISPLAY_ONE: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_SC2_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_PIP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_PIP_SC2_Sub_Ex; ++ } ++ break; ++ ++ case PQ_DISPLAY_POP: ++ if(u16DisplayWidth == 1366) ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub_Ex; ++ } ++ else ++ { ++ PQTableInfoEx.pQuality_Map_Aray = (void*)QMAP_1920_POP_SC2_Sub_Ex; ++ } ++ break; ++ } ++ MDrv_PQ_AddTable_(SC2_SUBEX, &PQTableInfoEx); ++ if(!bSkipCommTable) ++ { ++ MDrv_PQ_LoadCommTable_(SC2_SUBEX); ++ } ++ ++ return TRUE; ++ ++ ++#else ++ ++ UNUSED(u16DisplayWidth); ++ UNUSED(enDisplaType); ++ UNUSED(bSkipCommTable); ++ return FALSE; ++ ++#endif ++#else ++ return TRUE; ++#endif ++} ++ ++ ++MS_BOOL MDrv_PQ_GetMADiFromGrule(PQ_WIN eWindow, MS_U16 *pu16TabIdx_MADi_Motion, MS_U16 *pu16TabIdx_MADi) ++{ ++#if PQ_GRULE_OSD_BW_ENABLE ++ MS_U16 u16PQ_OSDBWIdx = 0; ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ { ++ if(bw_info.u32Miu1MemSize ==0) // 1 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ } ++ #else //DDR select disable ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_Main, PQ_GRule_Lvl_OSD_BW_On_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ #endif ++ ++ #if (PQ_GRULE_OSD_BW_IP_NUM_Main > 1) ++ *pu16TabIdx_MADi_Motion = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_Main, u16PQ_OSDBWIdx, 1); // Add MADi_Motion ip ++ #else ++ UNUSED(pu16TabIdx_MADi_Motion); ++ #endif ++ } ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ { ++ if(bw_info.u32Miu1MemSize ==0) // 1 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ } ++ #else //DDR select disable ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, PQ_GRule_Lvl_OSD_BW_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ #endif ++ ++ #if (PQ_GRULE_OSD_BW_IP_NUM_SC1_Main > 1) ++ *pu16TabIdx_MADi_Motion = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC1_Main, u16PQ_OSDBWIdx, 1); // Add MADi_Motion ip ++ #else ++ UNUSED(pu16TabIdx_MADi_Motion); ++ #endif ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ #if PQ_GRULE_DDR_SELECT_ENABLE ++ { ++ if(bw_info.u32Miu1MemSize ==0) // 1 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, PQ_GRule_Lvl_OSD_BW_1DDR_On_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, PQ_GRule_Lvl_OSD_BW_2DDR_On_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ } ++ #else //DDR select disable ++ { ++ u16PQ_OSDBWIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, PQ_GRule_Lvl_OSD_BW_On_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 0); // only MADi ip ++ } ++ #endif ++ ++ #if (PQ_GRULE_OSD_BW_IP_NUM_SC2_Main > 1) ++ *pu16TabIdx_MADi_Motion = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_OSD_BW_SC2_Main, u16PQ_OSDBWIdx, 1); // Add MADi_Motion ip ++ #else ++ UNUSED(pu16TabIdx_MADi_Motion); ++ #endif ++ } ++#endif // ENABLE_MULTI_SCALER ++ else ++ { ++ // TODO: Should sub window need to consider the OSD BW ?? ++ } ++#else ++ UNUSED(eWindow); ++ UNUSED(pu16TabIdx_MADi_Motion); ++ UNUSED(pu16TabIdx_MADi); ++#endif ++ ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetMemFmtInGeneral(PQ_WIN eWindow, ++ MS_BOOL bMemFmt422, ++ MS_U16 *pu16TabIdx_MemFormat, ++ MS_U16 *pu16TabIdx_444To422, ++ MS_U16 *pu16TabIdx_422To444 ++ ) ++{ ++#if (PQ_ENABLE_MEMFMT) ++ if(bMemFmt422) ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC1_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_SC1_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_SC2_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ } ++ else ++ { ++ // use 444_10BIT mode only if < 1440x1080 ++ // frame buffer 1920x1080x3x2 == 1440x1080x4x2 ++ // also bandwidth not enough for 1920x1080 444_10BIT ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC1_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_SC1_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Main); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_SC2_Main; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MemFormat = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MemFormat_SC2_Sub); ++ *pu16TabIdx_444To422 = PQ_IP_444To422_OFF_SC2_Sub; ++ *pu16TabIdx_422To444 = Hal_PQ_get_422To444_idx((MS_422To444_TYPE)Hal_PQ_get_422To444_mode(bMemFmt422)); ++ } ++#endif ++#endif // ENABLE_MULTI_SCALER ++ } ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetMADiInGeneral(PQ_WIN eWindow, MS_U16 *pu16TabIdx_MADi_Motion, MS_U16 *pu16TabIdx_MADi) ++{ ++#if (PQ_ENABLE_MEMFMT) ++ UNUSED(pu16TabIdx_MADi_Motion); ++ UNUSED(pu16TabIdx_MADi); ++#if PQ_GRULE_DDR_SELECT_ENABLE ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ MS_U16 u16PQ_DDRSELIdx = 0; ++ if(bw_info.u32Miu1MemSize==0) // 1 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_Main, PQ_GRule_Lvl_DDR_SELECT_1DDR_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_Main, PQ_GRule_Lvl_DDR_SELECT_2DDR_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ } ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Sub); ++ } ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ MS_U16 u16PQ_DDRSELIdx = 0; ++ if(bw_info.u32Miu1MemSize==0) // 1 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, PQ_GRule_Lvl_DDR_SELECT_1DDR_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, PQ_GRule_Lvl_DDR_SELECT_2DDR_SC1_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC1_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ MS_U16 u16PQ_DDRSELIdx = 0; ++ if(bw_info.u32Miu1MemSize==0) // 1 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, PQ_GRule_Lvl_DDR_SELECT_1DDR_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ else // 2 DDR ++ { ++ u16PQ_DDRSELIdx = MDrv_PQ_GetGRule_LevelIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, PQ_GRule_Lvl_DDR_SELECT_2DDR_SC2_Main); ++ *pu16TabIdx_MADi = MDrv_PQ_GetGRule_TableIndex(eWindow, PQ_GRule_DDR_SELECT_SC2_Main, u16PQ_DDRSELIdx, 0); // only MADi ip ++ } ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC2_Sub); ++ } ++#endif // ENABLE_MULTI_SCALER ++#else //DDR select disable ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_Sub); ++ ++ } ++#endif ++ ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC2_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ *pu16TabIdx_MADi = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_MADi_SC2_Sub); ++ ++ } ++#endif ++#endif ++ //printf("$$[%s]:%d, %s, u16TabIdx_MADi=%u\r\n", __FUNCTION__, __LINE__, eWindow?"SUB":"MAIN", u16TabIdx_MADi); ++ } ++#endif ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetMADiForRFBL(PQ_WIN eWindow, MS_BOOL bFBL, MS_U16 *pu16TabIdx_MADi_Motion, MS_U16 *pu16TabIdx_MADi) ++{ ++ UNUSED(pu16TabIdx_MADi_Motion); ++ if((_stRFBL_Info.bEnable)&&(!bFBL)) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, (MS_MADI_TYPE)_stRFBL_Info.u8MADiType); ++ if(!_stMode_Info[eWindow].bInterlace) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_NO_MIU); ++ ++ MDrv_PQ_MADiForceMotionY(eWindow, FALSE); ++ MDrv_PQ_MADiForceMotionC(eWindow, FALSE); ++ //printf("[%s]-[%d] : disable Y/C motion\r\n", __FUNCTION__, __LINE__); ++ } ++ //printf("[%s]-[%d] : u16TabIdx_MADi = %d\r\n",__FUNCTION__,__LINE__,u16TabIdx_MADi); ++ } ++ ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_Patch2Rto4RForFieldPackingMode(PQ_WIN eWindow, MS_U16 u16TabIdx_MADi) ++{ ++#if 0//Ryan ++#if PQ_GRULE_OSD_BW_ENABLE ++ // Patch: in OSD turn off case, when 2R-->4R, J2, M10 with new OPM system will flash(4R-->2R is OK) ++ // we need to set 4R first, and wait some time, and do other MAdi setting, the flash will be ok. ++ // which is only for non-OS platform patch, since OS platform won't turn off OSD for DFB system. ++ // Only FieldPackingMode need this solution ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ if((MApi_XC_IsFieldPackingModeSupported() && ++ (_stMode_Info[eWindow].u16input_hsize>=1280)&& ++ (_stMode_Info[eWindow].u16input_vsize>=720) && ++ (!_bOSD_On)) && ++ ((u16TabIdx_MADi == PQ_IP_MADi_24_4R_Main) || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_Main) || ++ (u16TabIdx_MADi == PQ_IP_MADi_26_4R_Main) || (u16TabIdx_MADi == PQ_IP_MADi_27_4R_Main) ++#if PQ_MADI_88X_MODE ++ || (u16TabIdx_MADi == PQ_IP_MADi_24_4R_880_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_880_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_884_Main) ++#endif ++ )) ++ { ++ //set to 4R first, ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_03_L, 0 , 0x0002 ); ++ //delay ++ _MDrv_PQ_wait_output_vsync(eWindow, 1, 90); ++ } ++ } ++ ++#if ENABLE_MULTI_SCALER ++ if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ if((MApi_XC_IsFieldPackingModeSupported() && ++ (_stMode_Info[eWindow].u16input_hsize>=1280)&& ++ (_stMode_Info[eWindow].u16input_vsize>=720) && ++ (!_bOSD_On)) && ++ ((u16TabIdx_MADi == PQ_IP_MADi_24_4R_SC1_Main) || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_SC1_Main) || ++ (u16TabIdx_MADi == PQ_IP_MADi_26_4R_SC1_Main) || (u16TabIdx_MADi == PQ_IP_MADi_27_4R_SC1_Main) ++#if PQ_MADI_88X_MODE ++ || (u16TabIdx_MADi == PQ_IP_MADi_24_4R_880_SC1_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_880_SC1_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_884_SC1_Main) ++#endif ++ )) ++ { ++ //set to 4R first, ++ MApi_XC_W2BYTEMSK(REG_SC1_BK12_03_L, 0 , 0x0002 ); ++ //delay ++ _MDrv_PQ_wait_output_vsync(eWindow, 1, 90); ++ } ++ } ++ ++ if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ if((MApi_XC_IsFieldPackingModeSupported() && ++ (_stMode_Info[eWindow].u16input_hsize>=1280)&& ++ (_stMode_Info[eWindow].u16input_vsize>=720) && ++ (!_bOSD_On)) && ++ ((u16TabIdx_MADi == PQ_IP_MADi_24_4R_SC2_Main) || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_SC2_Main) || ++ (u16TabIdx_MADi == PQ_IP_MADi_26_4R_SC2_Main) || (u16TabIdx_MADi == PQ_IP_MADi_27_4R_SC2_Main) ++#if PQ_MADI_88X_MODE ++ || (u16TabIdx_MADi == PQ_IP_MADi_24_4R_880_SC2_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_880_SC2_Main) ++ || (u16TabIdx_MADi == PQ_IP_MADi_25_4R_884_SC2_Main) ++#endif ++ )) ++ { ++ //set to 4R first, ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_03_L, 0 , 0x0002 ); ++ //delay ++ _MDrv_PQ_wait_output_vsync(eWindow, 1, 90); ++ } ++ } ++#endif // ENABLE_MULTI_SCALER ++ ++#else ++ UNUSED(eWindow); ++ UNUSED(u16TabIdx_MADi); ++#endif ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_GetBPPInfoFromMADi(PQ_WIN eWindow, ++ MS_BOOL bMemFmt422, ++ MS_U16 u16TabIdx_MADi, ++ MS_U16 u16TabIdx_MemFormat, ++ MS_U8 *pu8BitsPerPixel, ++ PQ_DEINTERLACE_MODE *peDeInterlaceMode, ++ MS_U8 *pu8FrameCount ++ ) ++{ ++#if 0//Ryan ++ if(bMemFmt422) ++ { ++ // decide bits/pixel and deinterlace mode flag ++ if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_4R)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ ++ PQMADi_DBG(printf("24_4R PQ_DEINT_3DDI_HISTORY \r\n")); ++ } ++ else if( (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R)) || ++ (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_2R_880))) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("24_2R PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("25 4R PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ PQMADi_DBG(printf("25 4R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_14F_6R_MC)) //Add New MADi mode ++ { ++ *pu8BitsPerPixel = 24; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 14; ++ PQMADi_DBG(printf("25 14F 6R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_14F_8R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 14; ++ PQMADi_DBG(printf("25 14F 8R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_12F_8R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 12; ++ PQMADi_DBG(printf("25 12F 8R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_16F_8R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 16; ++ PQMADi_DBG(printf("25 16F 8R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_MC_NW)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_FilmPreDet)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R FilmPreDet_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_6R_FilmPreDet_PAL)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 6R FilmPreDet PAL_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_6R_FilmPreDet)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("24 6R FilmPreDet_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_6R_FilmPreDet_PAL)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("24 6R FilmPreDet PAL_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_8F_4R_MC)) ++ { ++ *pu8BitsPerPixel = 24; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ *pu8FrameCount = 8; ++ PQMADi_DBG(printf("25 8F 4R MC_PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++#if PQ_ENABLE_RFBL ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_2D)) // Need to ReDefine ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_25D)) // Need to ReDefine ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D)) // Need to ReDefine ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_YC)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_3D_FILM)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ } ++#endif ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("25 2 PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_26_4R)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("26 4 PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_26_2R)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ PQMADi_DBG(printf("26 2 PQ_DEINT_3DDI_HISTORY\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_4R)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_3DDI; ++ PQMADi_DBG(printf("27 4 PQ_DEINT_3DDI\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_27_2R)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_3DDI; ++ PQMADi_DBG(printf("27 2 PQ_DEINT_3DDI\r\n")); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 8 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE10)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 10 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT8)) ++ { ++ *pu8BitsPerPixel = 20; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P M 8 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P M 10 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_RFBL_FILM)) ++ { ++ *pu8BitsPerPixel = 12; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ //printf("==================================== MS_MADI_24_RFBL_FILM\r\n"); ++ //printf("24 PQ_DEINT_3DDI_HISTORY\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_24_RFBL_NFILM)) ++ { ++ *pu8BitsPerPixel = 12; ++ *peDeInterlaceMode = PQ_DEINT_3DDI_HISTORY; ++ //printf("==================================== MS_MADI_24_RFBL_NFILM\r\n"); ++ //printf("24 PQ_DEINT_3DDI_HISTORY\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_FBL_DNR)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_AVG; ++ //printf("==================================== MS_MADI_FBL_DNR\r\n"); ++ //printf("24 PQ_DEINT_2DDI_AVG\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_FBL_MIU)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_AVG; ++ //printf("==================================== MS_MADI_FBL_MIU\r\n"); ++ //printf("24 PQ_DEINT_2DDI_AVG\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_NO_MIU)) ++ { ++ *pu8BitsPerPixel = 16; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_AVG; ++ //printf("==================================== MS_MADI_P_MODE8_NO_MIU\r\n"); ++ //printf("24 PQ_DEINT_2DDI_AVG\r\n"); ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10_8Frame)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ PQMADi_DBG(printf("P M 10 8Frame PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 8; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MOT10_4Frame)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE, MAIN_WINDOW); ++ PQMADi_DBG(printf("P M 10 4Frame PQ_DEINT_2DDI_BOB\r\n")); ++ } ++ else if (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_3Frame)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE,MAIN_WINDOW); ++ PQMADi_DBG(printf("P M 10 3Frame PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 3; ++ } ++ else if (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_6Frame_6R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE,MAIN_WINDOW); ++ *pu8FrameCount = 6; ++ } ++ else if (u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_12Frame_8R)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ MApi_XC_Set_OPWriteOffEnable(DISABLE,MAIN_WINDOW); ++ *pu8FrameCount = 12; ++ } ++#if PQ_ENABLE_RFBL ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE10_MOT)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("RFBL P M 10 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_RFBL_P_MODE8_MOT)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("RFBL P M 8 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++#endif ++ else ++ { ++ MS_ASSERT(0); ++ PQMADi_DBG(printf("None\r\n")); ++ } ++ ++ } ++ else ++ { ++ //in order to disable user mode, ++ if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_444)) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 8 444 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if(u16TabIdx_MADi == Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE10_444)) ++ { ++ *pu8BitsPerPixel = 30; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("P 10 444 PQ_DEINT_2DDI_BOB\r\n")); ++ *pu8FrameCount = 2; ++ } ++ ++ if((u16TabIdx_MemFormat == PQ_IP_MemFormat_444_10BIT_Main) ++#if PQ_ENABLE_PIP ++ ||(u16TabIdx_MemFormat == PQ_IP_MemFormat_444_10BIT_Sub) ++#endif ++ ) ++ { ++ *pu8BitsPerPixel = 32; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("PQ_IP_MemFormat_444_10BIT\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else if((u16TabIdx_MemFormat == PQ_IP_MemFormat_444_8BIT_Main) ++#if PQ_ENABLE_PIP ++ ||(u16TabIdx_MemFormat == PQ_IP_MemFormat_444_8BIT_Sub) ++#endif ++ ) ++ { ++ *pu8BitsPerPixel = 24; ++ *peDeInterlaceMode = PQ_DEINT_2DDI_BOB; ++ PQMADi_DBG(printf("PQ_IP_MemFormat_444_8BIT\r\n")); ++ *pu8FrameCount = 2; ++ } ++ else ++ { ++ *pu8BitsPerPixel = 24; ++ PQMADi_DBG(printf("PQ_IP_MemFormat_422MF_Main\r\n")); ++ *pu8FrameCount = 2; ++ } ++ ++ if ( MApi_XC_R2BYTE(REG_SC_BK2A_02_L) & BIT(15) ) //if on need disable. ++ { ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, TRUE); ++#endif ++#if PQ_UC_CTL ++ MDrv_PQ_LoadTable(eWindow, PQ_IP_UC_CTL_OFF_Main, PQ_IP_UC_CTL_Main); ++#endif ++#if(ENABLE_PQ_MLOAD) ++ MDrv_PQ_Set_MLoadEn(eWindow, FALSE); ++#endif ++ } ++ } ++#endif ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_ChangeMemConfigFor3D(PQ_WIN eWindow, ++ MS_BOOL bMemFmt422, ++ MS_U16 *pu16TabIdx_MemFormat, ++ MS_U16 *pu16TabIdx_444To422, ++ MS_U16 *pu16TabIdx_422To444, ++ MS_U8 *pu8BitsPerPixel, ++ MS_U16 *pu16TabIdx_MADi_Motion, ++ MS_U16 *pu16TabIdx_MADi ++ ) ++{ ++#if 0 //Ryan ++ UNUSED(pu16TabIdx_MADi_Motion); ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ //reduce mem size, put it into 16M, 2 frame mode. ++ if((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) ++ && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE) ++ && (_stMode_Info[eWindow].u16input_hsize == 1920) ++ && (_stMode_Info[eWindow].u16input_vsize == 2205)) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_444); ++ *pu8BitsPerPixel = 16; ++ ++ // DVI is 444 input, we need to conver it to 422, otherwise DVI will use 32 bpp instead, not 16 ++ // because 444 format combine to the setting of pu16TabIdx_MemFormat ++ if(!bMemFmt422) ++ { ++ //PQ_IP_MemFormat_Main 422 ++ *pu16TabIdx_MemFormat = PQ_IP_MemFormat_422MF_Main; ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ //PQ_IP_422To444_Main on ++ *pu16TabIdx_422To444 = PQ_IP_422To444_ON_Main; ++ PQBW_DBG(printf("3D: force 422, 444to422 and 422to444 ON\r\n");) ++ } ++ ++ printf("3D: modify progressive memory fmt for 1080p framepacking\r\n"); ++ } ++ ++ if(MApi_XC_Get_3D_HW_Version() < 2) ++ { ++ //PQ main page maybe MADi mode to 8 field mode, but it cannot do madi for line by line output. ++ //so we force it back to normal 25_2R like mode. ++ if((MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_TOP_BOTTOM) && (TRUE == _stMode_Info[eWindow].bInterlace)) ++ { ++ // we must use MS_MADI_25_4R or 2R to avoid MC madi mode for dnr offset calcuation problem. ++ if(TRUE == _stMode_Info[eWindow].bInterlace) ++ { ++ if((_stMode_Info[eWindow].u16input_vsize >= 900) && ++ (_stMode_Info[eWindow].u16input_hsize >= 1440) && ++ (bw_info.u32Miu1MemSize==0))// 1ddr case, should save bw ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R); ++ PQBW_DBG(printf("3D: force to 25_2R\r\n");) ++ } ++ else ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_4R); ++ PQBW_DBG(printf("3D: force to 25_4R\r\n");) ++ } ++ } ++ ++ //Madi do line by line must use 422 format ++ if(!bMemFmt422) ++ { ++ //PQ_IP_MemFormat_Main 422 ++ *pu16TabIdx_MemFormat = PQ_IP_MemFormat_422MF_Main; ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ //PQ_IP_422To444_Main on ++ *pu16TabIdx_422To444 = PQ_IP_422To444_ON_Main; ++ PQBW_DBG(printf("3D: force 422, 444to422 and 422to444 ON\r\n");) ++ } ++ ++ // we can only process 422 format for E_XC_3D_INPUT_TOP_BOTTOM. ++ // so, if it's 444 format, we have to force it to be 422 and the u8BitsPerPixel is also changed to 24. ++ *pu8BitsPerPixel = 24; ++ PQBW_DBG(printf("3D:force u8BitsPerPixel to 24\r\n");) ++ } ++ ++ //frame alterntive must use bob mode ++ if((E_XC_3D_OUTPUT_FRAME_ALTERNATIVE_NOFRC == MApi_XC_Get_3D_Output_Mode()) || ++ (E_XC_3D_OUTPUT_FRAME_ALTERNATIVE == MApi_XC_Get_3D_Output_Mode())) ++ { ++ MDrv_PQ_EnableMADIForce(PQ_MAIN_WINDOW, TRUE); ++#if PQ_MADI_DFK ++ MDrv_PQ_LoadTable(eWindow, PQ_IP_MADi_DFK_OFF_Main, PQ_IP_MADi_DFK_Main); ++#endif ++ MDrv_PQ_LoadTable(eWindow, PQ_IP_EODi_OFF_Main, PQ_IP_EODi_Main); ++ } ++ //line by line must use weave mode ++ else if(E_XC_3D_OUTPUT_LINE_ALTERNATIVE == MApi_XC_Get_3D_Output_Mode()) ++ { ++ MDrv_PQ_EnableMADIForce(eWindow, FALSE); ++ } ++ ++ //None 3D case: by Ethan.Lee, saveing memory size for 1920x1200 ++ if ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_MODE_NONE) && ++ (MApi_XC_Get_3D_Output_Mode()== E_XC_3D_OUTPUT_MODE_NONE) ) ++ { ++ // Saving memory size for 1920x1200P HDMI 20110421EL ++ if ( (_stMode_Info[eWindow].u16input_vsize > 1100) && (QM_IsSourceHDMI_Video(_enInputSourceType[eWindow], eWindow))) ++ { ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE8_444); ++ *pu8BitsPerPixel = 16; ++ if(!bMemFmt422) ++ { ++ //PQ_IP_MemFormat_Main 422 ++ *pu16TabIdx_MemFormat = PQ_IP_MemFormat_422MF_Main; ++ *pu16TabIdx_444To422 = PQ_IP_444To422_ON_Main; ++ //PQ_IP_422To444_Main on ++ *pu16TabIdx_422To444 = PQ_IP_422To444_ON_Main; ++ PQBW_DBG(printf("3D: force 422, 444to422 and 422to444 ON\r\n");) ++ } ++ } ++ } ++ } ++ ++ //Frame packing interlace must use 25_2R for ++ // A. Madi for line by line output for old 3D engine. Or, ++ // B. better quality. (P mode will shaking a little) ++ if(((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_L) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_R) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_TOP_BOTTOM) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_SIDE_BY_SIDE_HALF) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_LINE_ALTERNATIVE) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ || ((MApi_XC_Get_3D_Input_Mode((SCALER_WIN)eWindow) == E_XC_3D_INPUT_FRAME_PACKING) && (MApi_XC_Get_3D_Output_Mode() == E_XC_3D_OUTPUT_FRAME_ALTERNATIVE) && (_stMode_Info[eWindow].u16input_vsize == 2228)) ++ ) ++ { ++ //framepacking interlace 1080i ++ *pu16TabIdx_MADi = Hal_PQ_get_madi_idx(eWindow, MS_MADI_25_2R); ++ _stMode_Info[eWindow].bInterlace = TRUE; ++ *pu8BitsPerPixel = 24; ++ ++ PQBW_DBG(printf("3D: force to 25_2R\r\n");) ++ } ++ } ++ return TRUE; ++#else ++ return TRUE; ++#endif ++} ++ ++MS_BOOL MDrv_PQ_ForceBPPForDynamicMemFmt(PQ_WIN eWindow, MS_BOOL bMemFmt422, MS_U8 *pu8BitsPerPixel) ++{ ++ //force Memory FMT and use the same pixel number to avoid the garbage when memory mode is changed. ++ if(bMemFmt422) ++ { ++ MS_U16 u16MemFMT= 0; ++ ++ if(!_stMode_Info[eWindow].bInterlace) ++ { ++ // for dynamically memory format changing, we need to keep it as 24 bits ++ if(SUPPORT_DYNAMIC_MEM_FMT)//STB could be false ++ { ++ *pu8BitsPerPixel = 24; ++ } ++ } ++ ++ if (eWindow == PQ_MAIN_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC_BK12_02_L, 0xFF); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC_BK12_42_L, 0xFF); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if (eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC1_BK12_02_L, 0xFF); ++ } ++ else if (eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC2_BK12_02_L, 0xFF); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ u16MemFMT = MApi_XC_R2BYTEMSK(REG_SC2_BK12_42_L, 0xFF); ++ } ++ #endif // ENABLE_MULTI_SCALER ++ ++ if((u16MemFMT == 0xBB) || (u16MemFMT == 0xAA) || (u16MemFMT == 0x99) || (u16MemFMT == 0x88)) ++ { ++ *pu8BitsPerPixel = 24; ++ } ++ else if((u16MemFMT == 0x55) || (u16MemFMT == 0x66) || (u16MemFMT == 0x44)) ++ { ++ *pu8BitsPerPixel = 20; ++ } ++ else ++ { ++ //decide by original setting ++ } ++ } ++ return TRUE; ++} ++ ++MS_BOOL MDrv_PQ_SetFrameNumber(PQ_WIN eWindow, MS_U16 u16TabIdx_MADi, MS_U8 u8FrameCount) ++{ ++ if(SUPPORT_SCMI_V2) ++ { ++ //Set Frame number ++ if((bSetFrameCount )&& ((_stMode_Info[eWindow].bInterlace) ++ ||(u16TabIdx_MADi == (Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_6Frame_6R))) ++ ||(u16TabIdx_MADi == (Hal_PQ_get_madi_idx(eWindow, MS_MADI_P_MODE_MC_12Frame_8R))))) ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_19_L, u8FrameCount , 0x001F); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_59_L, u8FrameCount , 0x001F); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC1_BK12_19_L, u8FrameCount , 0x001F); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_19_L, u8FrameCount , 0x001F); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_59_L, u8FrameCount , 0x001F); ++ } ++ #endif // ENABLE_MULTI_SCALER ++ ++ } ++ else ++ { ++ //When the frame mode from P_MODE_MC_6Frame_6R or P_MODE_MC_12Frame_8R transform to other P_MODE , set the frame config to 3 frame. ++ ++ if(eWindow == PQ_MAIN_WINDOW ++ #if PQ_ENABLE_PIP ++ || eWindow == PQ_SUB_WINDOW ++ #endif ++ ) ++ { ++ if ((MApi_XC_R2BYTEMSK(REG_SC_BK12_19_L , 0x001F ) == 0x0C)||(MApi_XC_R2BYTEMSK(REG_SC_BK12_19_L , 0x001F ) == 0x06)) ++ { ++ if (eWindow == PQ_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_19_L, 0x03 , 0x001F ); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_59_L, 0x03 , 0x001F ); ++ } ++ } ++ } ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC2_MAIN_WINDOW || eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ if ((MApi_XC_R2BYTEMSK(REG_SC2_BK12_19_L , 0x001F ) == 0x0C)||(MApi_XC_R2BYTEMSK(REG_SC2_BK12_19_L , 0x001F ) == 0x06)) ++ { ++ if (eWindow == PQ_MAIN_WINDOW) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_19_L, 0x03 , 0x001F ); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC2_BK12_59_L, 0x03 , 0x001F ); ++ } ++ } ++ } ++ else ++ { ++ if ((MApi_XC_R2BYTEMSK(REG_SC1_BK12_19_L , 0x001F ) == 0x0C)||(MApi_XC_R2BYTEMSK(REG_SC1_BK12_19_L , 0x001F ) == 0x06)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC1_BK12_19_L, 0x03 , 0x001F ); ++ } ++ } ++ #endif ++ } ++ } ++ return TRUE; ++} ++ ++#if (PQ_ENABLE_PICTURE) ++static MS_BOOL _MDrv_PQ_Get_Picture_3x3_Matrix(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret; ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_3x3matrix_PIC2_Main); ++ ++ PQCOLOR_DBG(printf("3x3matrix:win%d TabIdx:%d \n",eWindow, u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Sub : ++ PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_3x3matrix_PIC2_SC2_Sub : ++ PQ_IP_SRAM_3x3matrix_PIC2_SC1_Main : ++ #endif ++ PQ_IP_SRAM_3x3matrix_PIC2_Main; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_Main, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_Sub, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_SC1_Main, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_SC2_Main, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_3x3matrix_PIC2_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_3x3matrix_PIC2_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ return bret; ++} ++ ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_DLC(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_DLC_PIC1_Main); ++ ++ PQCOLOR_DBG(printf("DLC Curve:win:%d TabIdx:%d \n",eWindow, u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Sub : ++ PQ_IP_SRAM_DLC_PIC1_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_DLC_PIC1_SIZE_Main; ++ ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_DLC_PIC1_SC2_Sub : ++ PQ_IP_SRAM_DLC_PIC1_SC1_Main : ++ #endif ++ PQ_IP_SRAM_DLC_PIC1_Main; ++ ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_Main, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_Sub, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_SC1_Main, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_SC2_Main, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_DLC_PIC1_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_DLC_PIC1_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ } ++ ++ return bret; ++} ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_ColorSetting(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Main); ++ PQCOLOR_DBG(printf("ColorSetting: win:%d, TabIdx:%d \n",eWindow, u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Sub : ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Sub : ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Main; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Main, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_Sub, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC1_Main, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Main, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_Bri_Con_Hue_Sat_Sha_PIC1_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ ++ return bret; ++} ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_Gamma_TBL(PQ_WIN eWindow, MS_U16 *pBuf, PQ_PICTURE_TYPE enPictureType) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ MS_U16 u16PQIdx, u16Tabsize; ++ ++ u16TableIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_GammaTbl_R_PIC1_Main) : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_GammaTbl_G_PIC1_Main) : ++ MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_GammaTbl_B_PIC1_Main); ++ ++ PQCOLOR_DBG(printf("Gamma: TabIdx:%d \n", u16TableIdx)); ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_Main; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_Main; ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_Sub; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_Sub; ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SC1_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SC1_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SC1_Main; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_SC1_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_SC1_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_SC1_Main; ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SC2_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SC2_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SC2_Main; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_SC2_Main : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_SC2_Main : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_SC2_Main; ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ u16PQIdx = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SC2_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SC2_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SC2_Sub; ++ ++ u16Tabsize = enPictureType == E_PQ_PICTURE_GAMMA_TBL_R ? PQ_IP_SRAM_GammaTbl_R_PIC1_SIZE_SC2_Sub : ++ enPictureType == E_PQ_PICTURE_GAMMA_TBL_G ? PQ_IP_SRAM_GammaTbl_G_PIC1_SIZE_SC2_Sub : ++ PQ_IP_SRAM_GammaTbl_B_PIC1_SIZE_SC2_Sub; ++ } ++#endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ if(!bret) ++ { ++ return FALSE; ++ } ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ PQ_BIN_STD_SC1_MAIN; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16Tabsize); ++ ++ ++ } ++ else ++#endif ++ { ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, (MS_U8)u16PQIdx, (void *)pBuf, u16Tabsize); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ } ++ ++ return bret; ++} ++ ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_AutoColor(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_Auto_Color_PIC2_Main); ++ PQCOLOR_DBG(printf("AutoColor: TabIdx:%d \n", u16TableIdx)); ++ ++#if ENABLE_PQ_BIN ++ if(gbPQBinEnable) ++ { ++ MS_U8 PQBinID = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_BIN_STD_SC1_MAIN : ++ #endif ++ PQ_BIN_STD_MAIN; ++ ++ MS_U16 u16TabeSize = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Auto_Color_PIC2_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Auto_Color_PIC2_Main; ++ ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_Main, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Main); ++ } ++ #if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_Sub, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_Sub); ++ } ++ #endif ++ #if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_SC1_Main, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_SC2_Main, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Auto_Color_PIC2_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_Auto_Color_PIC2_SIZE_SC2_Sub); ++ } ++ #endif ++ else ++ { ++ bret = FALSE; ++ } ++ ++ } ++ ++ return bret; ++} ++ ++ ++static MS_BOOL _MDrv_PQ_Get_Picture_ColorTemp(PQ_WIN eWindow, MS_U16 *pBuf) ++{ ++ MS_U16 u16TableIdx; ++ MS_BOOL bret = TRUE; ++ ++ ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, PQ_IP_SRAM_Color_Temp_PIC1_Main); ++ PQCOLOR_DBG(printf("ColorTemp: TabIdx:%d \n", u16TableIdx)); ++ ++#if(ENABLE_PQ_BIN) ++ ++ ++ if(gbPQBinEnable) ++ { ++ ++ MS_U8 PQBinID = eWindow == PQ_MAIN_WINDOW ? PQ_BIN_STD_MAIN : ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_BIN_STD_SUB : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_BIN_STD_SC2_MAIN : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_BIN_STD_SC2_SUB : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_BIN_STD_SC1_MAIN : ++ #endif ++ PQ_BIN_STD_MAIN; ++ ++ MS_U16 u16TabeSize = eWindow == PQ_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Main : ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Main; ++ ++ MS_U16 u16PQIPIdx = eWindow == PQ_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_Main : ++ #if PQ_ENABLE_PIP ++ eWindow == PQ_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_Sub : ++ #endif ++ #if ENABLE_MULTI_SCALER ++ eWindow == PQ_SC2_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SC2_Main : ++ eWindow == PQ_SC2_SUB_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SC2_Sub : ++ eWindow == PQ_SC1_MAIN_WINDOW ? PQ_IP_SRAM_Color_Temp_PIC1_SC1_Main : ++ #endif ++ PQ_IP_SRAM_Color_Temp_PIC1_Main; ++ bret = MDrv_PQBin_LoadPictureSetting((MS_U16)MDrv_PQBin_GetPanelIdx(eWindow), ++ u16TableIdx, ++ u16PQIPIdx, ++ &stPQBinHeaderInfo[PQBinID], ++ (void *)pBuf, ++ u16TabeSize); ++ ++ ++ } ++ else ++#endif ++ { ++ ++ if(eWindow == PQ_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_Main, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Main); ++ } ++#if PQ_ENABLE_PIP ++ else if(eWindow == PQ_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_Sub, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_Sub); ++ } ++#endif ++#if ENABLE_MULTI_SCALER ++ else if(eWindow == PQ_SC1_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC1_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_SC1_Main, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC1_Main); ++ } ++ else if(eWindow == PQ_SC2_MAIN_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_MAIN, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_SC2_Main, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Main); ++ } ++ else if(eWindow == PQ_SC2_SUB_WINDOW) ++ { ++ bret = MDrv_PQ_LoadPictureSetting_(SC2_SUB, (MS_U8)u16TableIdx, PQ_IP_SRAM_Color_Temp_PIC1_SC2_Sub, (void *)pBuf, PQ_IP_SRAM_Color_Temp_PIC1_SIZE_SC2_Sub); ++ } ++#endif ++ else ++ { ++ bret = FALSE; ++ } ++ } ++ ++ return bret; ++} ++ ++MS_BOOL MDrv_PQ_Get_Sharpness(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info * pstPQModeInfo, MS_U8 *pu8Sharpness) ++{ ++ MS_BOOL bret = TRUE; ++ MS_U16 u16PQSrcType = 0; ++ MS_PQ_Mode_Info stModeInfo; ++ MS_U16 u16TableIdx; ++ MS_U16 u16IPIdx; ++ MS_U8 u8Peaking_Gain[1]; ++ ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ _u16PQSrcType[eWindow] = QM_AV_PAL_M_Main; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ MsOS_Memcpy(&stModeInfo, &_stMode_Info[eWindow], sizeof(MS_PQ_Mode_Info)); ++ MDrv_PQ_Set_ModeInfo(eWindow, enInputSourceType, pstPQModeInfo); ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ } ++ ++ PQCOLOR_DBG(printf("PQ_Get_Sharpness: win:%d SRC:%d \n", eWindow, _u16PQSrcType[eWindow])); ++ ++ u16IPIdx = PQ_IP_VIP_Peaking_gain_Main; ++ u16TableIdx = MDrv_PQ_GetTableIndex(eWindow, u16IPIdx); ++ ++#if(ENABLE_PQ_BIN) ++ if(((gbPQBinEnable == 1) && (u16TableIdx == PQ_BIN_IP_NULL)) ++ || ((gbPQBinEnable == 0) && (u16TableIdx == PQ_IP_NULL))) ++#else ++ if(u16TableIdx == PQ_IP_NULL) ++#endif ++ { ++ *pu8Sharpness = 0xFF; ++ bret = FALSE; ++ } ++ else ++ { ++ MDrv_PQ_LoadTableData(eWindow, u16TableIdx, u16IPIdx, u8Peaking_Gain, 1); ++ *pu8Sharpness = u8Peaking_Gain[0]; ++ ++ } ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ MsOS_Memcpy(&_stMode_Info[eWindow], &stModeInfo, sizeof(MS_PQ_Mode_Info)); ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ ++ return bret; ++} ++ ++ ++MS_BOOL MDrv_PQ_Get_Picture(PQ_WIN eWindow, PQ_INPUT_SOURCE_TYPE enInputSourceType, MS_PQ_Mode_Info * pstPQModeInfo, PQ_PICTURE_TYPE enType, void *pBuf) ++{ ++ MS_BOOL bret = FALSE; ++ MS_U16 u16PQSrcType = PQ_INPUT_SOURCE_NONE; ++ MS_PQ_Mode_Info stModeInfo; ++ ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ _u16PQSrcType[eWindow] = QM_AV_PAL_M_Main; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ ++ u16PQSrcType = _u16PQSrcType[eWindow]; ++ MsOS_Memcpy(&stModeInfo, &_stMode_Info[eWindow], sizeof(MS_PQ_Mode_Info)); ++ MDrv_PQ_Set_ModeInfo(eWindow, enInputSourceType, pstPQModeInfo); ++ _u16PQSrcType[eWindow] = QM_InputSourceToIndex(eWindow, enInputSourceType); ++ } ++ ++ ++ PQCOLOR_DBG(printf("PQ_Get_Picture: Type:%d SRC:%d \n", enType, _u16PQSrcType[eWindow])); ++ ++ switch(enType) ++ { ++ case E_PQ_PICTURE_3x3_MATRIX: ++ bret = _MDrv_PQ_Get_Picture_3x3_Matrix(eWindow, pBuf); ++ break; ++ ++ case E_PQ_PICTURE_DLC_CURVE: ++ bret = _MDrv_PQ_Get_Picture_DLC(eWindow, pBuf); ++ break; ++ ++ case E_PQ_PICTURE_COLOR_SETTING: ++ bret = _MDrv_PQ_Get_Picture_ColorSetting(eWindow, pBuf); ++ break; ++ ++ case E_PQ_PICTURE_GAMMA_TBL_R: ++ case E_PQ_PICTURE_GAMMA_TBL_G: ++ case E_PQ_PICTURE_GAMMA_TBL_B: ++ bret = _MDrv_PQ_Get_Picture_Gamma_TBL(eWindow, pBuf, enType); ++ break; ++ ++ case E_PQ_PICTURE_AUTO_COLOR: ++ bret = _MDrv_PQ_Get_Picture_AutoColor(eWindow, pBuf); ++ break; ++ ++ ++ case E_PQ_PICTURE_COLOR_TEMP: ++ bret = _MDrv_PQ_Get_Picture_ColorTemp(eWindow, pBuf); ++ break; ++ } ++ ++ if(enInputSourceType == PQ_INPUT_SOURCE_NONE) ++ { ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ else if(pstPQModeInfo && (enInputSourceType == PQ_INPUT_SOURCE_VGA || enInputSourceType == PQ_INPUT_SOURCE_YPBPR)) ++ { ++ MsOS_Memcpy(&_stMode_Info[eWindow], &stModeInfo, sizeof(MS_PQ_Mode_Info)); ++ _u16PQSrcType[eWindow] = u16PQSrcType; ++ } ++ ++ return bret; ++} ++#endif ++ ++#endif // PQ_ENABLE_UNUSED_FUNC +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ_Bin.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ_Bin.c +new file mode 100644 +index 00000000..8e9182a3 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ_Bin.c +@@ -0,0 +1,1764 @@ ++// $Change: 661747 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#define _DRV_PQ_BIN_C ++ ++ ++#ifdef MSOS_TYPE_LINUX ++#include ++#endif ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++ ++#include "MsCommon.h" ++#include "MsOS.h" ++#include "MsTypes.h" ++#include "hwreg_utility2.h" ++#include "color_reg.h" ++ ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ_Bin.h" ++#include "drvPQ_Datatypes.h" ++#include "drvPQ.h" ++ ++#include "mhal_pq.h" ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++#if(ENABLE_PQ_BIN) ++ ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++#define PQ_BIN_DBG_HEADER_DATA 0 ++#define PQ_BIN_DBG(x) //(x) ++#define PQ_BIN_DBG_HEADER(x) //(x) ++#define PQ_BIN_DUMP_DBG(x) //(x) ++#define PQ_BIN_DUMP_FILTER_DBG(x) //(x) ++#define PQ_BIN_XRULE_DBG(x) //(x) ++#define PQ_BIN_GRULE_DBG(x) //(x) ++#define PQ_TEXT_BIN_DBG_HEADER(x) //(x) ++#define PQ_TEXT_BIN_DBG(x) //(x) ++#define PQ_BIN_DBG_SRAMERROR(x) //(x) ++#define PQ_BIN_PICTURE(x) //(x) ++ ++#if (PQ_BIN_ENABLE_CHECK == 0) ++#define PQ_REG_FUNC( u32Reg, u8Value, u8Mask ) MApi_XC_WriteByteMask( u32Reg, u8Value, u8Mask ) ++#define PQ_REG_MLOAD_FUNC(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg-1, ((MS_U16)u8Value)<<8, ((MS_U16)u8Mask)<<8); \ ++ } \ ++ else \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg, u8Value, u8Mask); \ ++ } \ ++ }while(0) ++ ++#define PQ_REG_MLOAD_WRITE_CMD(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg-1; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask)<<8; \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value)<<8; \ ++ } \ ++ else \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask); \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value); \ ++ } \ ++ _u16MLoadCmdCnt++; \ ++ }while(0) ++ ++#else // #if(PQ_ENABLE_CHECK == 1) ++static MS_U8 _u8PQBinfunction = PQ_FUNC_DUMP_REG; ++static void _MDrv_PQBin_SetFunction(MS_U8 u8Func) ++{ ++ _u8PQBinfunction = u8Func; ++} ++ ++#define PQ_REG_FUNC( u16Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if (_u8PQBinfunction == PQ_FUNC_DUMP_REG) \ ++ { \ ++ MApi_XC_WriteByteMask( (MS_U32)u16Reg, u8Value, u8Mask ); \ ++ } \ ++ else \ ++ { \ ++ if ((MApi_XC_ReadByte((MS_U32)u16Reg) & u8Mask) != (u8Value & u8Mask)) \ ++ { \ ++ printf("[PQRegErr] "); \ ++ if ((u16Reg >> 8) == 0x2F) \ ++ { \ ++ printf("bk=%02x, ", (MS_U16)SC_BK_CURRENT); \ } \ ++ else if ((u16Reg >> 8) == 0x36) \ ++ { \ ++ printf("bk=%02x, ", (MS_U16)COMB_BK_CURRENT); \ } \ ++ printf("addr=%04x, mask=%02x, val=%02x[%02x]\n", \ u16Reg, (MS_U16)u8Mask, (MS_U16)MApi_XC_ReadByte((MS_U32)u16Reg), (MS_U16)u8Value); \ ++ } \ } \ ++ }while(0) ++#endif //#if (PQ_ENABLE_CHECK) ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variable ++//------------------------------------------------------------------------------------------------- ++static MS_U16 _u16PQTabIdx[PQ_MAX_WINDOW][PQ_BIN_MAX_PNL][PQ_BIN_MAX_IP]; // store all TabIdx of all IPs ++static MS_U8 _gPQBinDisplayType[PQ_MAX_WINDOW]; ++static MS_U8 _gPQBinPnlIdx[PQ_MAX_WINDOW]; ++static MS_BOOL _bMLoadEn = FALSE; ++#define MLOAD_MAX_CMD 30 ++static MS_U32 _u32MLoadCmd[MLOAD_MAX_CMD]; ++static MS_U16 _u16MLoadMsk[MLOAD_MAX_CMD]; ++static MS_U16 _u16MLoadVal[MLOAD_MAX_CMD]; ++static MS_U16 _u16MLoadCmdCnt = 0; ++ ++static MS_U16 u16ICC_CRD_Table[PQ_MAX_WINDOW]; ++static MS_U16 u16IHC_CRD_Table[PQ_MAX_WINDOW]; ++ ++static MS_U16 u16SRAM1Table[PQ_MAX_WINDOW]; ++static MS_U16 u16SRAM2Table[PQ_MAX_WINDOW]; ++static MS_U16 u16SRAM3Table[PQ_MAX_WINDOW]; ++static MS_U16 u16SRAM4Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM1Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM2Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM3Table[PQ_MAX_WINDOW]; ++static MS_U16 u16CSRAM4Table[PQ_MAX_WINDOW]; ++ ++//------------------------------------------------------------------------------------------------- ++// Function ++//------------------------------------------------------------------------------------------------- ++void MDrv_PQBin_Clear_SRAM_Table_Index(void) ++{ ++ MS_U8 i; ++ ++ for(i=0;iu16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DUMP_DBG(printf("[PQBin]IP_Info error: General Reg Table\n")); ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset; ++ for(i=0; i< pTabInfo->u16RegNum; i++) ++ { ++ u32Offset = ( PQ_BIN_BANK_SIZE + PQ_BIN_ADDR_SIZE + PQ_BIN_MASK_SIZE + (MS_U32)pTabInfo->u16GroupNum) * (MS_U32)i; ++ u8Bank = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Addr = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Mask = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset += pTabInfo->u16GroupIdx; ++ u8Value = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ PQ_BIN_DBG_SRAMERROR(printf("4 [read addr=%lx], GroupIdx=%x,RegNum=%x,reg=%04x, msk=%02x, val=%02x, u8CurBank=%x\n", ++ (u32Addr+u32Offset-(MS_U32)pTabInfo->u16GroupIdx),pTabInfo->u16GroupIdx,pTabInfo->u16RegNum,NON_PM_BASE | (((MS_U16)u8Bank) << 8) | (MS_U16)u8Addr, u8Mask, u8Value, u8Bank);) ++ ++ u32RegAddr = NON_PM_BASE | (((MS_U16)u8Bank) << 8) | (MS_U16)u8Addr; ++ ++ PQ_BIN_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\n", u32RegAddr, u8Mask, u8Value)); ++ ++ PQ_REG_FUNC(u32RegAddr, u8Value, u8Mask); ++ } ++} ++ ++void MDrv_PQBin_DumpCombRegTable(const MS_PQBin_IP_Table_Info* const pTabInfo) ++{ ++ MS_U16 i; ++ MS_U8 u8Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ MS_U32 u32Addr, u32Offset, u32RegAddr; ++ ++ COMB_BK_STORE; ++ ++ PQ_BIN_DUMP_DBG(printf("tab: comb\n")); ++ ++ if(pTabInfo->u16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DUMP_DBG(printf("[PQBin]IP_Info error: Comb Reg Table\n")); ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset; ++ for(i=0; i< pTabInfo->u16RegNum; i++) ++ { ++ u32Offset = ( PQ_BIN_BANK_SIZE + PQ_BIN_ADDR_SIZE + PQ_BIN_MASK_SIZE + (MS_U32)pTabInfo->u16GroupNum) * (MS_U32)i; ++ u8CurBank = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Addr = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Mask = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset += pTabInfo->u16GroupIdx; ++ u8Value = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ PQ_BIN_DBG_SRAMERROR(printf("2 [read addr=%lx], GroupIdx=%x,RegNum=%x,reg=%04lx, msk=%02x, val=%02x, u8CurBank=%x\n", ++ (u32Addr+u32Offset-(MS_U32)pTabInfo->u16GroupIdx),pTabInfo->u16GroupIdx,pTabInfo->u16RegNum,COMB_REG_BASE | (MS_U32)u8Addr, u8Mask, u8Value, u8CurBank);) ++ ++ if (u8CurBank != COMB_BK_CURRENT) ++ { ++ PQ_BIN_DUMP_DBG(printf("<>\n", u8CurBank)); ++ COMB_BK_SWITCH(u8CurBank); ++ } ++ ++ u32RegAddr = COMB_REG_BASE | (MS_U16)u8Addr; ++ ++ PQ_BIN_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\n", u32RegAddr, u8Mask, u8Value)); ++ PQ_REG_FUNC(u32RegAddr, u8Value, u8Mask); ++ ++ } ++ COMB_BK_RESTORE; ++} ++ ++ ++void MDrv_PQBin_DumpScalerRegTable(const MS_PQBin_IP_Table_Info* const pTabInfo) ++{ ++ MS_U32 u32RegAddr; ++ MS_U8 u8Mask; ++ MS_U8 u8Addr; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ MS_U32 u32Addr, u32Offset; ++ MS_U16 i; ++ ++#ifdef MSOS_TYPE_LINUX ++#if(ENABLE_PQ_MLOAD) ++ pthread_mutex_lock(&_PQ_MLoad_Mutex); ++#endif ++#endif ++ //consider dump reg amount is very large, so we shouldn't use MApi_XC_W2BYTE(), ++ // because mutex cost much time. ++ SC_BK_STORE_MUTEX; ++ ++ PQ_BIN_DUMP_DBG(printf("tab: sc\n")); ++ if(pTabInfo->u16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: Scaler Reg Table\n")); ++ ++ SC_BK_RESTORE_MUTEX; ++ ++#ifdef MSOS_TYPE_LINUX ++#if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++#endif ++#endif ++ ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset; ++ for(i=0; iu16RegNum; i++) ++ { ++ u32Offset = ( PQ_BIN_BANK_SIZE + PQ_BIN_ADDR_SIZE + PQ_BIN_MASK_SIZE + (MS_U32)pTabInfo->u16GroupNum) * (MS_U32)i; ++ u8CurBank = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Addr = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ u8Mask = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset += (MS_U32)pTabInfo->u16GroupIdx; ++ u8Value = MDrv_PQBin_GetByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ PQ_BIN_DBG_SRAMERROR(printf("1 [read addr=%lx], GroupIdx=%x,RegNum=%x,reg=%04lx, msk=%02x, val=%02x, u8CurBank=%x\n", ++ (u32Addr+u32Offset-(MS_U32)pTabInfo->u16GroupIdx),pTabInfo->u16GroupIdx,pTabInfo->u16RegNum,BK_SCALER_BASE | (MS_U32)u8Addr, u8Mask, u8Value, u8CurBank);) ++ ++ if(_bMLoadEn) ++ { ++ u32RegAddr = (((MS_U32)u8CurBank) << 8) | (MS_U32)u8Addr; ++ //PQ_REG_MLOAD_FUNC(u32RegAddr, u8Value, u8Mask); ++ PQ_REG_MLOAD_WRITE_CMD(u32RegAddr, u8Value, u8Mask); ++ } ++ else ++ { ++#if (SCALER_REGISTER_SPREAD) ++ u32RegAddr = BK_SCALER_BASE | (((MS_U32)u8CurBank) << 8) | (MS_U32)u8Addr; ++#else ++ if (u8CurBank != SC_BK_CURRENT) ++ { ++ PQ_BIN_DUMP_DBG(printf("<>\n", u8CurBank)); ++ SC_BK_SWITCH(u8CurBank); ++ } ++ ++ u32RegAddr = BK_SCALER_BASE | (MS_U32)u8Addr; ++#endif ++ PQ_REG_FUNC(u32RegAddr, u8Value, u8Mask); ++ } ++ PQ_BIN_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\n", u32RegAddr, u8Mask, u8Value)); ++ ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++ ++#ifdef MSOS_TYPE_LINUX ++#if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++#endif ++#endif ++} ++ ++void MDrv_PQBin_DumpFilterTable(MS_PQBin_IP_Table_Info *pTabInfo) ++{ ++ MS_U32 u32Addr; ++ PQ_BIN_DBG(printf("tab: sram\n")); ++ ++ if(pTabInfo->u16GroupIdx >= pTabInfo->u16GroupNum) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]IP_Info error: SRAM Table\n")); ++ return; ++ } ++ ++ u32Addr = pTabInfo->u32TabOffset + pTabInfo->u16GroupIdx * pTabInfo->u16RegNum; ++ ++ PQ_BIN_DUMP_FILTER_DBG(printf("PQ Filter Table: Win:%d, Type:%d \n", pTabInfo->ePQWin, pTabInfo->u16TableType)); ++ switch(pTabInfo->u16TableType) ++ { ++ case PQ_TABTYPE_SRAM1: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM1, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM2: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM2, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM3: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM3, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM4: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM4, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM1: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM1, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM2: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM2, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM3: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM3, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_C_SRAM4: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_C_SRAM4, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM_COLOR_INDEX: ++ Hal_PQ_set_sram_color_index_table(pTabInfo->ePQWin, SC_FILTER_SRAM_COLOR_INDEX, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_SNR: ++ Hal_PQ_set_sram_color_gain_snr_table(pTabInfo->ePQWin, SC_FILTER_SRAM_COLOR_GAIN_SNR, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_DNR: ++ Hal_PQ_set_sram_color_gain_dnr_table(pTabInfo->ePQWin, SC_FILTER_SRAM_COLOR_GAIN_DNR, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_VIP_ICC_CRD_SRAM: ++ Hal_PQ_set_sram_icc_crd_table(pTabInfo->ePQWin, SC_FILTER_SRAM_ICC_CRD, (void *)u32Addr); ++ break; ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ Hal_PQ_set_sram_ihc_crd_table(pTabInfo->ePQWin, SC_FILTER_SRAM_IHC_CRD, (void *)u32Addr); ++ break; ++ ++ default: ++ printf("[PQBin] Unknown sram type %u\n", pTabInfo->u16TableType); ++ MS_ASSERT(0); ++ break; ++ } ++} ++ ++void MDrv_PQBin_DumpTable(MS_PQBin_IP_Table_Info* pTabInfo) ++{ ++ // to save loading SRAM table time, SRAM are only downloaded ++ // when current SRAM table is different to previous SRAM table ++ ++ if ((pTabInfo->u16RegNum == 0) || (pTabInfo->u32TabOffset == PQ_BIN_ADDR_NULL)) ++ { ++ PQ_BIN_DUMP_DBG(printf("NULL Table\n")); ++ return; ++ } ++ ++ switch(pTabInfo->u16TableType) ++ { ++ case PQ_TABTYPE_SCALER: ++ MDrv_PQBin_DumpScalerRegTable(pTabInfo); ++ break; ++ case PQ_TABTYPE_COMB: ++ MDrv_PQBin_DumpCombRegTable(pTabInfo); ++ break; ++ case PQ_TABTYPE_GENERAL: ++ MDrv_PQBin_DumpGeneralRegTable(pTabInfo); ++ break; ++ case PQ_TABTYPE_SRAM1: ++ if (u16SRAM1Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram1: %u, new sram1: %u\n", ++ u16SRAM1Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM1Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram1: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM2: ++ if (u16SRAM2Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram2: %u, new sram2: %u\n", ++ u16SRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM2Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram2: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM3: ++ if (u16SRAM3Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram3: %u, new sram3: %u\n", ++ u16SRAM3Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM3Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram3: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM4: ++ if (u16SRAM4Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram4: %u, new sram4: %u\n", ++ u16SRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16SRAM4Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same sram4: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_C_SRAM1: ++ if (u16CSRAM1Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram1: %u, new Csram1: %u\n", ++ u16CSRAM1Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM1Table [pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram1: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM2: ++ if (u16CSRAM2Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old Csram2: %u, new Csram2: %u\n", ++ u16CSRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM2Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram2: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM3: ++ if (u16SRAM3Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old Csram3: %u, new Csram3: %u\n", ++ u16CSRAM3Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM3Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram3: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM4: ++ if (u16CSRAM4Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old sram4: %u, new Csram4: %u\n", ++ u16CSRAM2Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16CSRAM4Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ else ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]use the same Csram4: %u\n", pTabInfo->u16GroupIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ if(u16IHC_CRD_Table[pTabInfo->ePQWin] != pTabInfo->u16GroupIdx) ++ { ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]old IHC_CRD_SRAM: %u, new IHC_CRD_SRAM: %u\n", ++ u16IHC_CRD_Table[pTabInfo->ePQWin], pTabInfo->u16GroupIdx)); ++ ++ u16IHC_CRD_Table[pTabInfo->ePQWin] = pTabInfo->u16GroupIdx; ++ MDrv_PQBin_DumpFilterTable(pTabInfo); ++ } ++ break; ++ ++ default: ++ PQ_BIN_DUMP_FILTER_DBG(printf("[PQBin]DumpTable:unknown type: %u\n", pTabInfo->u16TableType)); ++ break; ++ } ++} ++ ++ ++// return total IP count ++MS_U16 MDrv_PQBin_GetIPNum(MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ PQ_BIN_DBG(printf("[PQBin]:IPNum=%u\n", pPQBinHeader->u16IP_Comm_Num)); ++ return pPQBinHeader->u16IP_Comm_Num; ++} ++ ++// return total table count of given IP ++MS_U16 MDrv_PQBin_GetTableNum(MS_U16 u16PQIPIdx, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U16 u16TabNum; ++ ++ u32Addr = pPQBinHeader->u32BinStartAddress + pPQBinHeader->u32IP_Comm_Offset; ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IP_GROUP_NUM_OFFSET; ++ u16TabNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ PQ_BIN_DBG(printf("[PQBin]TabNum=%u\n", u16TabNum)); ++ return u16TabNum; ++} ++ ++// return current used table index of given IP ++MS_U16 MDrv_PQBin_GetCurrentTableIndex(MS_U16 u16PnlIdx, MS_U16 u16PQIPIdx, MS_U8 u8BinID) ++{ ++ PQ_WIN ePQWin = MDrv_PQBin_TransToPQWin(u8BinID); ++ //printf("[PQBin]CurrTableIdx=%d\n", _u16PQTabIdx[u16PnlIdx][u16PQIPIdx]); ++ ++ return _u16PQTabIdx[ePQWin][u16PnlIdx][u16PQIPIdx]; ++} ++ ++ ++MS_U16 MDrv_PQBin_GetTableIndex(MS_U16 u16PQSrcType, MS_U16 u16PQIPIdx, MS_U16 u16PQPnlIdx, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U32 u32SourceLUT_Addr; ++ MS_U32 u32SourceLUT_Offset; ++ MS_U16 u16SourceLUT_SourceNum; ++ MS_U16 u16SourceLUT_IPNum; ++ MS_U32 u32SourceLUT_Data_Pitch; ++ MS_U16 u16TableIdx; ++ ++ if(u16PQPnlIdx >= pPQBinHeader->u16SourceLUT_PnlNum) ++ { ++ (printf("[PQBin]invalid panel type\n")); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ ++ u32Addr = pPQBinHeader->u32BinStartAddress + pPQBinHeader->u32SourceLUT_Offset; ++ u32Offset = pPQBinHeader->u32SourceLUT_Pitch * u16PQPnlIdx + PQ_BIN_SOURCELUT_SOURCE_NUM_OFFSET; ++ u16SourceLUT_SourceNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ if (u16PQSrcType >= u16SourceLUT_SourceNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]invalid input type\n")); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Offset = pPQBinHeader->u32SourceLUT_Pitch * u16PQPnlIdx + PQ_BIN_SOURCELUT_IP_NUM_OFFSET; ++ u16SourceLUT_IPNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ if (u16PQIPIdx >= u16SourceLUT_IPNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]invalid ip type\n")); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ ++ u32Offset = pPQBinHeader->u32SourceLUT_Pitch * u16PQPnlIdx + PQ_BIN_SOURCELUT_OFFSET_OFFSET; ++ u32SourceLUT_Addr = MDrv_PQBin_Get4ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32SourceLUT_Addr += pPQBinHeader->u32BinStartAddress + PQ_BIN_HEADER_LEN; ++ u32SourceLUT_Data_Pitch = (MS_U32)u16SourceLUT_IPNum * 2; ++ u32SourceLUT_Offset = u32SourceLUT_Data_Pitch * (MS_U32)u16PQSrcType + ++ (MS_U32)u16PQIPIdx * 2; ++ ++ u16TableIdx = MDrv_PQBin_Get2ByteData((void *)(u32SourceLUT_Addr+u32SourceLUT_Offset), ++ &u32SourceLUT_Offset); ++ PQ_BIN_DBG(printf("[PQBin]TableId=%u\n",u16TableIdx)); ++ return u16TableIdx; ++} ++ ++void MDrv_PQBin_GetTable(MS_U16 u16PnlIdx, MS_U16 u16TabIdx, MS_U16 u16PQIPIdx, MS_PQBin_IP_Table_Info *pTableInfo, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ PQ_WIN ePQWin = MDrv_PQBin_TransToPQWin(pPQBinHeader->u8BinID); ++ if((u16PnlIdx >= PQ_BIN_MAX_PNL) || (u16PQIPIdx >= PQ_BIN_MAX_IP)) ++ { ++ printf("[PQBin]:Out Of Range!! PnlIdx=%u, IPIdx=%u\n", u16PnlIdx, u16PQIPIdx); ++ MS_ASSERT(0); ++ return; ++ } ++ _u16PQTabIdx[ePQWin][u16PnlIdx][u16PQIPIdx] = u16TabIdx; ++ ++ if (u16TabIdx != PQ_BIN_IP_NULL) ++ { ++ u32Addr = pPQBinHeader->u32IP_Comm_Offset + ++ pPQBinHeader->u32BinStartAddress; ++ ++ if(u16TabIdx == PQ_BIN_IP_COMM) ++ { ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_TABLE_TYPE_OFFSET; ++ pTableInfo->u16TableType = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_COMM_REG_NUM_OFFSET; ++ pTableInfo->u16RegNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_COMMOFFSET_OFFSET; ++ pTableInfo->u32TabOffset = MDrv_PQBin_Get4ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ pTableInfo->u32TabOffset += (pPQBinHeader->u32BinStartAddress + PQ_BIN_HEADER_LEN); ++ ++ pTableInfo->u16GroupNum = 1; ++ pTableInfo->u16GroupIdx = 0; ++ } ++ else ++ { ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_TABLE_TYPE_OFFSET; ++ pTableInfo->u16TableType = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IP_REG_NUM_OFFSET; ++ pTableInfo->u16RegNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IP_GROUP_NUM_OFFSET; ++ pTableInfo->u16GroupNum = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)u16PQIPIdx + PQ_BIN_IP_COMM_IPOFFSET_OFFSET; ++ pTableInfo->u32TabOffset = MDrv_PQBin_Get4ByteData((void *)((void *)(u32Addr+u32Offset)), &u32Offset); ++ pTableInfo->u32TabOffset += (pPQBinHeader->u32BinStartAddress + PQ_BIN_HEADER_LEN); ++ ++ pTableInfo->u16GroupIdx = u16TabIdx; ++ } ++ } ++ else ++ { ++ pTableInfo->u16GroupIdx = 0; ++ pTableInfo->u32TabOffset = PQ_BIN_ADDR_NULL; ++ pTableInfo->u16RegNum = 0; ++ pTableInfo->u16TableType = 0; ++ pTableInfo->u16GroupNum = 0; ++ } ++ ++ pTableInfo->ePQWin = MDrv_PQBin_TransToPQWin(pPQBinHeader->u8BinID); ++ ++ PQ_BIN_DBG(printf("[PQBin]: GetTable: Offset=%lx, RegNum=%u, GroupIdx=%u, GroupNum=%u, Type=%u eWin=%d\n", ++ pTableInfo->u32TabOffset, ++ pTableInfo->u16RegNum, ++ pTableInfo->u16GroupIdx, ++ pTableInfo->u16GroupNum, ++ pTableInfo->u16TableType, ++ pTableInfo->ePQWin)); ++} ++ ++MS_BOOL MDrv_PQBin_LoadPictureSetting( ++ MS_U16 u16PnlIdx, ++ MS_U16 u16TabIdx, ++ MS_U16 u16PQIPIdx, ++ MS_PQBin_Header_Info *pPQBinHeader, ++ void *pTable, ++ MS_U16 u16TableSize) ++{ ++ MS_PQBin_IP_Table_Info stTableInfo; ++ MS_U32 u32Addr = 0; ++ ++ MsOS_Memset(&stTableInfo, 0, sizeof(MS_PQBin_IP_Table_Info)); ++ ++ MDrv_PQBin_GetTable(u16PnlIdx, ++ u16TabIdx, ++ u16PQIPIdx, ++ &stTableInfo, ++ pPQBinHeader); ++ ++ PQ_BIN_PICTURE(printf("PQ_Bin: Picture: pnlidx:%d, TabIdx:%d, ipidx:%d \r\n", u16PnlIdx, u16TabIdx, u16PQIPIdx)); ++ PQ_BIN_PICTURE(printf("PQ_Bin: Picture: RegNum:%d, TabType:%d, GroupIdx:%d \r\n", stTableInfo.u16RegNum, stTableInfo.u16TableType, stTableInfo.u16GroupIdx)); ++ if(stTableInfo.u16GroupIdx >= stTableInfo.u16GroupNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data\n")); ++ return FALSE; ++ } ++ ++ if(u16TableSize > stTableInfo.u16RegNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data is too big\n")); ++ return FALSE; ++ } ++ ++ if(stTableInfo.u16TableType == PQ_TABTYPE_PICTURE_1) ++ { ++ u32Addr = stTableInfo.u32TabOffset + stTableInfo.u16RegNum * stTableInfo.u16GroupIdx * sizeof(MS_U8); ++ MsOS_Memcpy((MS_U8 *)pTable, (MS_U8 *)u32Addr, sizeof(MS_U8)*stTableInfo.u16RegNum); ++ } ++ else if(stTableInfo.u16TableType == PQ_TABTYPE_PICTURE_2) ++ { ++ u32Addr = stTableInfo.u32TabOffset + stTableInfo.u16RegNum * stTableInfo.u16GroupIdx * sizeof(MS_U16); ++ MsOS_Memcpy((MS_U16 *)pTable, (MS_U16 *)u32Addr, sizeof(MS_U16)*stTableInfo.u16RegNum); ++ } ++ else ++ { ++ return FALSE; ++ } ++ ++ ++#if 0 ++{ ++ MS_U32 u32Offset = 0; ++ for(u32Offset=0; u32Offset= stTableInfo.u16GroupNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data\n")); ++ return; ++ } ++ ++ if(u16TableSize > stTableInfo.u16RegNum) ++ { ++ PQ_BIN_DBG(printf("[PQBin]IP_Info error: LoadTable Data is too big\n")); ++ return; ++ } ++ u32Addr = stTableInfo.u32TabOffset; ++ for(i=0; iu16IP_Comm_Num; i++) ++ { ++ PQ_BIN_DBG_SRAMERROR(printf("--------MDrv_PQBin_LoadCommTable: u16TabIdx=%u, u16PQIPIdx=%u\n", PQ_BIN_IP_COMM, i);) ++ MDrv_PQBin_GetTable(u16PnlIdx, ++ PQ_BIN_IP_COMM, ++ i, ++ &stTableInfo, ++ pPQBinHeader); ++ ++ if(((stTableInfo.u16TableType >= PQ_TABTYPE_SRAM1) && (stTableInfo.u16TableType <= PQ_TABTYPE_C_SRAM1)) || ++ (stTableInfo.u16TableType == PQ_TABTYPE_VIP_IHC_CRD_SRAM) || ++ (stTableInfo.u16TableType == PQ_TABTYPE_VIP_ICC_CRD_SRAM) ++ ) ++ { ++ continue; ++ } ++ ++ MDrv_PQBin_DumpTable(&stTableInfo); ++ } ++} ++ ++ ++ ++void MDrv_PQBin_Parsing(MS_PQBin_Header_Info *pPQBinHeader) ++{ ++ MS_U32 u32PQBin_Addr; ++ MS_U32 u32Offset; ++#if PQ_BIN_DBG_HEADER_DATA ++ MS_U32 u32tmpoffset; ++#endif ++ MS_U8 i; ++ ++ { // for printf ++ pPQBinHeader->u8Header[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8Version[PQ_BIN_VERSION_LEN] = '\0'; ++ pPQBinHeader->u8Dummy[PQ_BIN_DUMMY] = '\0'; ++ pPQBinHeader->u8GRuleHader[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8XRuleHader[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8SkipRuleHader[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8IP_Comm_Header[PQ_BIN_HEADER_LEN] = '\0'; ++ pPQBinHeader->u8SourceLUT_Header[PQ_BIN_HEADER_LEN] = '\0'; ++ } ++ ++ ++ u32Offset = 0; ++ u32PQBin_Addr = pPQBinHeader->u32BinStartAddress; ++ //printf("\n BinStartaDDR ID%u=%lx \n", pPQBinHeader->u8BinID, u32PQBin_Addr); ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8Version[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQBinHeader->u32StartOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQBinHeader->u32EndOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ for(i=0; i< PQ_BIN_DUMMY; i++) ++ { ++ pPQBinHeader->u8Dummy[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u8PQID = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("Header :%s \n", pPQBinHeader->u8Header)); ++ PQ_BIN_DBG_HEADER(printf("Version:%s \n", pPQBinHeader->u8Version)); ++ PQ_BIN_DBG_HEADER(printf("startADDR=%lx, EndAddr=%lx \n", pPQBinHeader->u32StartOffset, pPQBinHeader->u32EndOffset)); ++ PQ_BIN_DBG_HEADER(printf("Dummy :%s \n", pPQBinHeader->u8Dummy)); ++ PQ_BIN_DBG_HEADER(printf("PQID :%d \n", pPQBinHeader->u8PQID)); ++ //------------------------------------------------------------------------------------------- ++ // GRule ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8GRuleHader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16GRule_RuleNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQBinHeader->u16GRule_PnlNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ ++ PQ_BIN_DBG_HEADER(printf("GRuleHeader:%s\n", pPQBinHeader->u8GRuleHader)); ++ PQ_BIN_DBG_HEADER(printf("GRule: RuleNum=%u, PnlNum=%u \n", pPQBinHeader->u16GRule_RuleNum, pPQBinHeader->u16GRule_PnlNum)); ++ ++ pPQBinHeader->u32GRule_Offset = u32Offset; ++ pPQBinHeader->u32GRule_Pitch = PQ_BIN_GRULE_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32GRule_Pitch * (MS_U32)pPQBinHeader->u16GRule_RuleNum; ++ ++ ++ pPQBinHeader->u32GRule_Lvl_Offset = u32Offset; ++ pPQBinHeader->u32GRule_Lvl_Pitch = PQ_BIN_GRULE_LEVEL_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32GRule_Lvl_Pitch * (MS_U32)pPQBinHeader->u16GRule_RuleNum * (MS_U32)pPQBinHeader->u16GRule_PnlNum; ++ ++ PQ_BIN_DBG_HEADER(printf("GRule Rule : offset=%lx, pitch=%lu \n", pPQBinHeader->u32GRule_Offset, pPQBinHeader->u32GRule_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("GRule Level: offset=%lx, pitch=%lu \n", pPQBinHeader->u32GRule_Lvl_Offset, pPQBinHeader->u32GRule_Lvl_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("XRule Start:%lx\n", u32Offset)); ++ ++ //------------------------------------------------------------------------------------------- ++ // XRule ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8XRuleHader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQBinHeader->u16XRuleNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("XRuleHeader:%s\n", pPQBinHeader->u8XRuleHader)); ++ PQ_BIN_DBG_HEADER(printf("XRule: RuleNum=%u\n", pPQBinHeader->u16XRuleNum)); ++ ++ pPQBinHeader->u32XRule_Offset = u32Offset; ++ pPQBinHeader->u32XRUle_Pitch = PQ_BIN_XRULE_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32XRUle_Pitch * (MS_U32)pPQBinHeader->u16XRuleNum; ++ ++ PQ_BIN_DBG_HEADER(printf("XRule: offset=%lx, pitch=%lu\n",pPQBinHeader->u32XRule_Offset, pPQBinHeader->u32XRUle_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("SkipRule Start:%lx\n", u32Offset)); ++ ++ //------------------------------------------------------------------------------------------- ++ // SkipRule ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8SkipRuleHader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16SkipRule_IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQBinHeader->u32SkipRule_Offset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("SkipRuleHeader:%s IpNum=%u, Offset=%lx\n", pPQBinHeader->u8SkipRuleHader, pPQBinHeader->u16SkipRule_IPNum, pPQBinHeader->u32SkipRule_Offset)); ++ PQ_BIN_DBG_HEADER(printf("IP_Comm Start:%lx\n", u32Offset)); ++ ++ //------------------------------------------------------------------------------------------- ++ // IP & Common ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8IP_Comm_Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16IP_Comm_Num = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("IP_CommHeader:%s\n", pPQBinHeader->u8IP_Comm_Header)); ++ PQ_BIN_DBG_HEADER(printf("IP_Comm, Num=%u\n", pPQBinHeader->u16IP_Comm_Num)); ++ ++ pPQBinHeader->u32IP_Comm_Offset = u32Offset; ++ pPQBinHeader->u32IP_Comm_Pitch = PQ_BIN_IP_COMM_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32IP_Comm_Pitch * (MS_U32)pPQBinHeader->u16IP_Comm_Num; ++ ++ PQ_BIN_DBG_HEADER(printf("IP_Comm, Offset=%lx, pitch=%lu\n", pPQBinHeader->u32IP_Comm_Offset, pPQBinHeader->u32IP_Comm_Pitch)); ++ PQ_BIN_DBG_HEADER(printf("SourceLUT Start:%lx\n", u32Offset)); ++ //------------------------------------------------------------------------------------------- ++ // SourceLUT ++ // ++ for(i=0; i< PQ_BIN_HEADER_LEN; i++) ++ { ++ pPQBinHeader->u8SourceLUT_Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ pPQBinHeader->u16SourceLUT_PnlNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_DBG_HEADER(printf("SourceLUTHeader:%s\n", pPQBinHeader->u8SourceLUT_Header)); ++ PQ_BIN_DBG_HEADER(printf("SourceLUT, PnlNum=%u\n", pPQBinHeader->u16SourceLUT_PnlNum)); ++ ++ pPQBinHeader->u32SourceLUT_Offset = u32Offset; ++ pPQBinHeader->u32SourceLUT_Pitch = PQ_BIN_SOURCELUT_INFO_SIZE; ++ u32Offset += pPQBinHeader->u32SourceLUT_Pitch * (MS_U32)pPQBinHeader->u16SourceLUT_PnlNum; ++ ++ PQ_BIN_DBG_HEADER(printf("SourceLUT: offset=%lx, pitch=%lu\n", pPQBinHeader->u32SourceLUT_Offset, pPQBinHeader->u32SourceLUT_Pitch)); ++ ++ ++#if PQ_BIN_DBG_HEADER_DATA ++ // GRule ++ u32tmpoffset = pPQBinHeader->u32GRule_Offset; ++ for(i=0; iu16GRule_RuleNum; i++) ++ { ++ ++ MS_PQBin_GRule_Info stGRuleInfo; ++ ++ stGRuleInfo.u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u16SourceNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u32IPOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleInfo.u32RuleOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("GRule %u, IPNum=%u, SourceNum=%u, GroupNum=%u, IPOffset=%lx, RuleOffset=%lx\n", ++ i, ++ stGRuleInfo.u16IPNum, ++ stGRuleInfo.u16SourceNum, ++ stGRuleInfo.u16GroupNum, ++ stGRuleInfo.u32IPOffset, ++ stGRuleInfo.u32RuleOffset); ++ } ++ ++ // GRule Level ++ for(i=0; iu16GRule_RuleNum*pPQBinHeader->u16GRule_PnlNum; i++) ++ { ++ MS_PQBin_GRule_Level_Info stGRuleLvlInfo; ++ ++ stGRuleLvlInfo.u16LvlNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stGRuleLvlInfo.u32Offset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("GRule_Lvl %u, u16LvlNum=%u, u32Offset=%lx \n", ++ i, stGRuleLvlInfo.u16LvlNum, stGRuleLvlInfo.u32Offset); ++ } ++ ++ // XRule ++ u32tmpoffset = pPQBinHeader->u32XRule_Offset; ++ for(i=0; iu16XRuleNum; i++) ++ { ++ MS_PQBin_XRule_Info stXRuleInfo; ++ ++ stXRuleInfo.u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stXRuleInfo.u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stXRuleInfo.u32IPOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stXRuleInfo.u32GroupOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("XRule %u, IPNum=%u, GroupNum=%u, IPOffset=%lx, GroupOffset=%lx\n", ++ i, stXRuleInfo.u16IPNum, stXRuleInfo.u16GroupNum, stXRuleInfo.u32IPOffset, stXRuleInfo.u32GroupOffset); ++ } ++ ++ // IP & Common ++ u32tmpoffset = pPQBinHeader->u32IP_Comm_Offset; ++ for(i=0; iu16IP_Comm_Num; i++) ++ { ++ MS_PQBin_IP_Common_Info stIPCommInfo; ++ ++ stIPCommInfo.u16CommRegNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u16IPRegNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u16IPGroupNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u32CommOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stIPCommInfo.u32IPOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("IP_Comm %u, CommRegNum=%u, IPRegNum=%u, IPGroupNum=%u, CommOffset=%lx, IPOffset=%lx\n", ++ i, ++ stIPCommInfo.u16CommRegNum, ++ stIPCommInfo.u16IPRegNum, ++ stIPCommInfo.u16IPGroupNum, ++ stIPCommInfo.u32CommOffset, ++ stIPCommInfo.u32IPOffset); ++ } ++ ++ // SourceLUT ++ u32tmpoffset = pPQBinHeader->u32SourceLUT_Offset; ++ for(i=0; iu16SourceLUT_PnlNum; i++) ++ { ++ MS_PQBin_SourceLUT_Info stSourceLUTInfo; ++ ++ stSourceLUTInfo.u16SourceNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stSourceLUTInfo.u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ stSourceLUTInfo.u32Offset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32tmpoffset), &u32tmpoffset); ++ ++ printf("SourceLUT %u, SourceNum=%u, IPNum=%u, Offset=%lx\n", ++ i, ++ stSourceLUTInfo.u16SourceNum, ++ stSourceLUTInfo.u16IPNum, ++ stSourceLUTInfo.u32Offset); ++ ++ } ++#endif ++ ++} ++ ++ ++MS_U16 MDrv_PQBin_GetSkipRule(MS_U16 u16PQIPIdx, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U16 u16SkipRet; ++ ++ u32Addr = pPQBinHeader->u32SkipRule_Offset + ++ pPQBinHeader->u32BinStartAddress + ++ PQ_BIN_SKIPRULE_HEADER_LEN; ++ ++ u32Offset = u16PQIPIdx * 2; ++ u16SkipRet = MDrv_PQBin_Get2ByteData((void *)((void *)(u32Addr+u32Offset)) , &u32Offset); ++ return u16SkipRet; ++} ++ ++void MDrv_PQBin_LoadTableBySrcType( ++ MS_U16 u16PQSrcType, ++ MS_U16 u16PQIPIdx, ++ MS_U16 u16PQPnlIdx, ++ MS_PQBin_Header_Info *pPQBinHeader) ++{ ++ MS_U16 QMIPtype_size,i; ++ MS_U16 u16TabIdx; ++ MS_PQBin_IP_Table_Info stTableInfo; ++ //XC_ApiStatusEx stXCStatusEx; Ryan ++ ++ if (u16PQIPIdx==PQ_BIN_IP_ALL) ++ { ++ QMIPtype_size= MDrv_PQBin_GetIPNum(pPQBinHeader); ++ u16PQIPIdx=0; ++ } ++ else ++ { ++ QMIPtype_size=1; ++ } ++ ++ ++ for(i=0; iu32XRule_Offset + pPQBinHeader->u32BinStartAddress; ++ ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_IP_NUM_OFFSET; ++ u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_GROUPOFFSET_OFFSET; ++ u32Rule_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress; ++ ++ ++ u32Rule_Offset = (u16IPNum * u16XRuleIdx + u16XRuleIP ) * 2; ++ u16TableIdx = MDrv_PQBin_Get2ByteData((void *)(u32Rule_Addr+u32Rule_Offset), &u32Rule_Offset); ++ ++ PQ_BIN_XRULE_DBG(printf("[PQBin_XRule]: TableIdx=%u\n", u16TableIdx)); ++ return u16TableIdx; ++ ++} ++ ++MS_U16 MDrv_PQBin_GetXRuleIPIndex(MS_U16 u16XRuleType, MS_U16 u16XRuleIP, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U32 u32IP_Addr; ++ MS_U32 u32IP_Offset; ++ MS_U16 u16IPIdx; ++ ++ u32Addr = pPQBinHeader->u32XRule_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_IPOFFSET_OFFSET; ++ ++ u32IP_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress + PQ_BIN_XRULE_HEADER_LEN; ++ ++ u32IP_Offset = u16XRuleIP * 2; ++ ++ u16IPIdx = MDrv_PQBin_Get2ByteData((void *)(u32IP_Addr+u32IP_Offset), &u32IP_Offset); ++ ++ PQ_BIN_XRULE_DBG(printf("[PQBin_XRule]: IPIdx=%u\n", u16IPIdx)); ++ return u16IPIdx; ++ ++} ++ ++MS_U16 MDrv_PQBin_GetXRuleIPNum(MS_U16 u16XRuleType, MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr; ++ MS_U32 u32Offset; ++ MS_U16 u16IPNum; ++ ++ u32Addr = pPQBinHeader->u32XRule_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32XRUle_Pitch * u16XRuleType + PQ_BIN_XRULE_IP_NUM_OFFSET; ++ u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_XRULE_DBG(printf("[PQBin_XRule]: IPNum=%u\n", u16IPNum)); ++ return u16IPNum; ++} ++ ++ ++ ++MS_U16 MDrv_PQBin_GetGRule_LevelIndex( ++ MS_U16 u16PnlIdx, ++ MS_U16 u16GRuleType, ++ MS_U16 u16GRuleLvlIndex, ++ MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset, u32Lvl_Addr; ++ MS_U16 u16LvlNum; ++ MS_U16 u16LvlIdx; ++ ++ if(u16PnlIdx >= pPQBinHeader->u16GRule_PnlNum) ++ { ++ MS_ASSERT(0); ++ printf("GRue: Pnl idx out of rage =%u\n", u16PnlIdx); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Addr = pPQBinHeader->u32GRule_Lvl_Offset + pPQBinHeader->u32BinStartAddress; ++ ++ u32Offset = pPQBinHeader->u32GRule_Lvl_Pitch * (MS_U32) (u16PnlIdx + pPQBinHeader->u16GRule_PnlNum * u16GRuleType) + ++ PQ_BIN_GRULE_LEVEL_LVL_NUM_OFFSET; ++ u16LvlNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ if(u16GRuleLvlIndex >= u16LvlNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: lvl idx out of rage =%u\n", u16GRuleLvlIndex); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Addr = pPQBinHeader->u32GRule_Lvl_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32GRule_Lvl_Pitch * (MS_U32) (u16PnlIdx + pPQBinHeader->u16GRule_PnlNum * u16GRuleType) + ++ PQ_BIN_GRULE_LEVEL_OFFSET_OFFSET; ++ ++ u32Lvl_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Addr = u32Lvl_Addr + pPQBinHeader->u32BinStartAddress; ++ u32Offset = PQ_BIN_GRULE_HEADER_LEN + u16GRuleLvlIndex * 2; ++ ++ u16LvlIdx = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ PQ_BIN_GRULE_DBG(printf("[PQBin_GRule: LvlIdx=%u\n", u16LvlIdx)); ++ return u16LvlIdx; ++} ++ ++ ++MS_U16 MDrv_PQBin_GetGRule_IPIndex( ++ MS_U16 u16GRuleType, ++ MS_U16 u16GRuleIPIndex, ++ MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32IP_Addr, u32IP_Offset; ++ MS_U16 u16IPIdx; ++ ++ u32Addr = pPQBinHeader->u32GRule_Offset + pPQBinHeader->u32BinStartAddress; ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + ++ PQ_BIN_GRULE_IPOFFSET_OFFSET; ++ ++ u32IP_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress + PQ_BIN_GRULE_HEADER_LEN; ++ u32IP_Offset = u16GRuleIPIndex * 2; ++ u16IPIdx = MDrv_PQBin_Get2ByteData((void *)(u32IP_Addr+u32IP_Offset), &u32IP_Offset); ++ ++ PQ_BIN_GRULE_DBG(printf("[PQBin_GRule: IPIdx=%u\n", u16IPIdx)); ++ return u16IPIdx; ++} ++ ++MS_U16 MDrv_PQBin_GetGRule_TableIndex( ++ MS_U16 u16GRuleType, ++ MS_U16 u16PQSrcType, ++ MS_U16 u16PQ_NRIdx, ++ MS_U16 u16GRuleIPIndex, ++ MS_PQBin_Header_Info* pPQBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32Rule_Addr, u32Rule_Offset; ++ MS_U16 u16GroupNum, u16IPNum, u16SrcNum; ++ MS_U16 u16TableIdx; ++ ++ if(u16GRuleType >= pPQBinHeader->u16GRule_RuleNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: ruleid out of range=%u\n", u16GRuleType); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ u32Addr = pPQBinHeader->u32GRule_Offset + pPQBinHeader->u32BinStartAddress; ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_GROUP_NUM_OFFSET; ++ u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_IP_NUM_OFFSET; ++ u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_SOURCE_NUM_OFFSET; ++ u16SrcNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ ++ ++ if(u16PQSrcType >= u16SrcNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: SrcIdx out of range =%u\n", u16PQSrcType); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ if(u16PQ_NRIdx >= u16GroupNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: GroupIdx out of range =%u\n", u16PQ_NRIdx); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ if(u16GRuleIPIndex >= u16IPNum) ++ { ++ MS_ASSERT(0); ++ printf("GRule: IPIdx out of range =%u\n", u16GRuleIPIndex); ++ return PQ_BIN_IP_NULL; ++ } ++ ++ ++ u32Offset = pPQBinHeader->u32GRule_Pitch * u16GRuleType + PQ_BIN_GRULE_RULEOFFSET_OFFSET; ++ u32Rule_Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQBinHeader->u32BinStartAddress + PQ_BIN_GRULE_HEADER_LEN; ++ ++ ++ u32Rule_Offset = (u16IPNum * u16GroupNum * u16PQSrcType + ++ u16IPNum * u16PQ_NRIdx + ++ u16GRuleIPIndex) * 2; ++ u16TableIdx = MDrv_PQBin_Get2ByteData((void *)(u32Rule_Addr+u32Rule_Offset), &u32Rule_Offset); ++ PQ_BIN_GRULE_DBG(printf("[PQBin_GRule: TabIdx=%u\n", u16TableIdx)); ++ return u16TableIdx; ++} ++ ++ ++void MDrv_PQBin_CheckCommTable(MS_U16 u16PnlIdx, MS_PQBin_Header_Info * pPQBinHeader) ++{ ++#if (PQ_ENABLE_CHECK == 1) ++ _u8PQBinfunction = PQ_FUNC_CHK_REG; ++ MDrv_PQBin_LoadCommTable(u16PnlIdx, pPQBinHeader); ++ _u8PQBinfunction = PQ_FUNC_DUMP_REG; ++#else ++ UNUSED(u16PnlIdx); ++ UNUSED(pPQBinHeader); ++#endif ++} ++ ++void MDrv_PQBin_CheckTableBySrcType( ++ MS_U16 u16PQSrcType, ++ MS_U16 u16PQIPIdx, ++ MS_U16 u16PQPnlIdx, ++ MS_PQBin_Header_Info * pPQBinHeader) ++{ ++#if (PQ_ENABLE_CHECK == 1) ++ _u8PQBinfunction = PQ_FUNC_CHK_REG; ++ MDrv_PQBin_LoadTableBySrcType(u16PQSrcType, ++ u16PQIPIdx, ++ u16PQPnlIdx, ++ pPQBinHeader); ++ _u8PQBinfunction = PQ_FUNC_DUMP_REG; ++#else ++ UNUSED(u16PQSrcType); ++ UNUSED(u16PQIPIdx); ++ UNUSED(u16PQPnlIdx); ++ UNUSED(pPQBinHeader); ++#endif ++} ++ ++void MDrv_PQBin_SetDisplayType(PQ_BIN_DISPLAY_TYPE enDisplayType, PQ_WIN ePQWin) ++{ ++ _gPQBinDisplayType[ePQWin] = enDisplayType; ++} ++ ++PQ_BIN_DISPLAY_TYPE MDrv_PQBin_GetDisplayType(PQ_WIN ePQWin) ++{ ++ return (PQ_BIN_DISPLAY_TYPE)_gPQBinDisplayType[ePQWin]; ++} ++ ++void MDrv_PQBin_SetPanelID(MS_U8 u8PnlIDx, PQ_WIN ePQWin) ++{ ++ _gPQBinPnlIdx[ePQWin] = u8PnlIDx; ++} ++ ++MS_U8 MDrv_PQBin_GetPanelIdx(PQ_WIN ePQWin) ++{ ++#if (PQ_ENABLE_PIP) ++ if(ePQWin == PQ_SC1_MAIN_WINDOW) ++ return _gPQBinPnlIdx[ePQWin] * 1 + _gPQBinDisplayType[ePQWin]; // SC1 only has 720 panel ++ else ++ return _gPQBinPnlIdx[ePQWin] * PQ_BIN_DISPLAY_NUM + _gPQBinDisplayType[ePQWin]; ++#else ++ return _gPQBinPnlIdx[ePQWin] * 1 + _gPQBinDisplayType[ePQWin]; ++#endif ++} ++ ++void MDrv_PQBin_Set_MLoadEn(MS_BOOL bEn) ++{ ++ MS_U16 i; ++ ++ if(bEn == DISABLE) ++ { ++ //if spread reg, no need to use mutex, but it's ok to use mutex ++ // (because it's not MApi_XC_W2BYTE(), which has mutex already) ++ //if not spread reg, must use mutex to protect MLoad_trigger func. ++ SC_BK_STORE_MUTEX; ++ ++ if(_u16MLoadCmdCnt) ++ { ++ for(i=1; i<_u16MLoadCmdCnt; i++) ++ { ++ if(_u32MLoadCmd[i-1] == _u32MLoadCmd[i]) ++ { ++ _u16MLoadMsk[i] |= _u16MLoadMsk[i-1]; ++ _u16MLoadVal[i] |= _u16MLoadVal[i-1]; ++ } ++ } ++ #if(ENABLE_PQ_MLOAD) ++ MApi_XC_MLoad_WriteCmds_And_Fire( ++ &_u32MLoadCmd[0], &_u16MLoadVal[0], &_u16MLoadMsk[0], _u16MLoadCmdCnt); ++ #endif ++ ++ _u16MLoadCmdCnt = 0; ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++ } ++ ++ _bMLoadEn = bEn; ++} ++ ++//------------------------------------------------------------------------------ ++// Text Bin function ++//------------------------------------------------------------------------------ ++MS_BOOL MDrv_PQTextBin_Parsing(MS_PQTextBin_Header_Info *pPQTextBinHeader) ++{ ++ MS_U32 u32PQBin_Addr; ++ MS_U32 u32Offset; ++#if PQ_BIN_DBG_HEADER_DATA ++ MS_U32 u32tmpoffset; ++#endif ++ MS_U8 i; ++ ++ u32Offset = 0; ++ u32PQBin_Addr = pPQTextBinHeader->u32BinStartAddress; ++ printf("TextBinStartaDDR ID%u=%lx\n", pPQTextBinHeader->u8BinID, u32PQBin_Addr); ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8Header[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8Version[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ ++ pPQTextBinHeader->u32StartOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ pPQTextBinHeader->u32EndOffset = MDrv_PQBin_Get4ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ for(i=0; i< PQ_TEXT_BIN_DUMMY; i++) ++ { ++ pPQTextBinHeader->u8Dummy[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("Header :%s\n", pPQTextBinHeader->u8Header)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("Version:%s\n", pPQTextBinHeader->u8Version)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("startADDR=%lx, pPQTextBinHeader=%lx\n", pPQTextBinHeader->u32StartOffset, pPQTextBinHeader->u32EndOffset)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("Dummy :%s \n", pPQTextBinHeader->u8Dummy)); ++ ++ ++ if(pPQTextBinHeader->u8Header[0] != 0x43 || pPQTextBinHeader->u8Header[0] != 0x33 || ++ pPQTextBinHeader->u8Dummy[0] != 0xA5 || pPQTextBinHeader->u8Dummy[0] != 0x59) ++ { ++ printf("PQ Parsing Fail \n"); ++ return FALSE; ++ } ++ ++ ++ // SrcType ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8SrcTypeHeader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQTextBinHeader->u16SrcNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ PQ_TEXT_BIN_DBG_HEADER(printf("SrcTypeHeader:%s\n", pPQTextBinHeader->u8SrcTypeHeader)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("SrcType: RuleNum=%u\n", pPQTextBinHeader->u16SrcNum)); ++ ++ pPQTextBinHeader->u32SrcType_Offset = u32Offset; ++ pPQTextBinHeader->u32SrcType_Pitch = PQ_TEXT_BIN_SRCTYPE_INFO_SIZE; ++ u32Offset += pPQTextBinHeader->u32SrcType_Pitch * (MS_U32)pPQTextBinHeader->u16SrcNum; ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("SrcType: offset=%lx, pitch=%lu\n",pPQTextBinHeader->u32SrcType_Offset, pPQTextBinHeader->u32SrcType_Pitch)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName Start:%lx\n", u32Offset)); ++ ++ // IP Name ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8IPNameHeader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQTextBinHeader->u16IPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPNameHeader:%s\n", pPQTextBinHeader->u8IPNameHeader)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName: IPNum=%u\n", pPQTextBinHeader->u16IPNum)); ++ ++ pPQTextBinHeader->u32IPName_Offset = u32Offset; ++ pPQTextBinHeader->u32IPName_Pitch = PQ_TEXT_BIN_IPNAME_INFO_SIZE; ++ u32Offset += pPQTextBinHeader->u32IPName_Pitch * (MS_U32)pPQTextBinHeader->u16IPNum; ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName: offset=%lx, pitch=%lu\n",pPQTextBinHeader->u32IPName_Offset, pPQTextBinHeader->u32IPName_Pitch)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("GroupName Start:%lx\n", u32Offset)); ++ ++ // Group Name ++ for(i=0; i< PQ_TEXT_BIN_HEADER_LEN; i++) ++ { ++ pPQTextBinHeader->u8GroupNameHeader[i] = MDrv_PQBin_GetByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ } ++ pPQTextBinHeader->u16GroupIPNum = MDrv_PQBin_Get2ByteData((void *)(u32PQBin_Addr+u32Offset), &u32Offset); ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("GroupName:%s\n", pPQTextBinHeader->u8GroupNameHeader)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("GroupName: IPNum=%u\n", pPQTextBinHeader->u16GroupIPNum)); ++ ++ pPQTextBinHeader->u32IP_Group_Offset = u32Offset; ++ pPQTextBinHeader->u32IP_Group_pitch = PQ_TEXT_BIN_GROUPNAME_INFO_SIZE; ++ u32Offset += pPQTextBinHeader->u32IP_Group_pitch * (MS_U32)pPQTextBinHeader->u16GroupIPNum; ++ ++ PQ_TEXT_BIN_DBG_HEADER(printf("IPName: offset=%lx, pitch=%lu\n",pPQTextBinHeader->u32IP_Group_Offset, pPQTextBinHeader->u32IP_Group_pitch)); ++ PQ_TEXT_BIN_DBG_HEADER(printf("Group Start:%lx\n", u32Offset)); ++ ++ return TRUE; ++ ++} ++ ++MS_U32 MDrv_PQTextBin_GetSrcType(MS_U16 u16SrcIdx, MS_PQTextBin_Header_Info* pPQTextBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32DstAddr; ++ ++ if(u16SrcIdx >= pPQTextBinHeader->u16SrcNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetSrcType:: SrcIdx Out of range %u\n", u16SrcIdx); ++ u16SrcIdx = 0; ++ } ++ u32Addr = pPQTextBinHeader->u32SrcType_Offset + pPQTextBinHeader->u32BinStartAddress; ++ u32Offset = pPQTextBinHeader->u32SrcType_Pitch * u16SrcIdx + ++ PQ_TEXT_BIN_SRCTYPE_OFFSET_OFFSET; ++ ++ u32DstAddr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ PQ_TEXT_BIN_DBG(printf("PQTextBin SrcType: Addr%lx, SrcIdx%u\n", u32DstAddr, u16SrcIdx)); ++ return u32DstAddr; ++} ++ ++MS_U32 MDrv_PQTextBin_GetIPName(MS_U16 u16PQIPIdx, MS_PQTextBin_Header_Info* pPQTextBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32DstAddr; ++ ++ if(u16PQIPIdx >= pPQTextBinHeader->u16IPNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetIPName:: IPIdx Out of range %u\n", u16PQIPIdx); ++ u16PQIPIdx = 0; ++ } ++ u32Addr = pPQTextBinHeader->u32IPName_Offset + pPQTextBinHeader->u32BinStartAddress; ++ u32Offset = pPQTextBinHeader->u32IPName_Pitch * u16PQIPIdx + ++ PQ_TEXT_BIN_IPNAME_OFFSET_OFFSET; ++ ++ u32DstAddr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ PQ_TEXT_BIN_DBG(printf("PQTextBin IPName: %lx\n", u32DstAddr)); ++ return u32DstAddr; ++} ++ ++MS_U32 MDrv_PQTextBin_GetTableName(MS_U16 u16PQIPIdx, MS_U16 u16TabIdx, MS_PQTextBin_Header_Info* pPQTextBinHeader) ++{ ++ MS_U32 u32Addr, u32Offset; ++ MS_U32 u32DstAddr; ++ MS_U16 u16GroupNum; ++ MS_U32 u32Total_Len; ++ MS_U32 i; ++ ++ if(u16PQIPIdx >= pPQTextBinHeader->u16GroupIPNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetGroupName:: IPIdx Out of range %u\n", u16PQIPIdx); ++ u16PQIPIdx = 0; ++ } ++ ++ u32Addr = pPQTextBinHeader->u32IP_Group_Offset + pPQTextBinHeader->u32BinStartAddress; ++ u32Offset = pPQTextBinHeader->u32IP_Group_pitch * u16PQIPIdx + ++ PQ_TEXT_BIN_GROUPNAME_IPGROUP_GROUPNUM_OFFSET; ++ u16GroupNum = MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ ++ if(u16TabIdx >= u16GroupNum) ++ { ++ MS_ASSERT(0); ++ printf("[PQBinText] GetGroupName :: TableIdx Out of range %u\n", u16TabIdx); ++ u16TabIdx = 0; ++ } ++ u32Addr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ u32Offset = PQ_TEXT_BIN_GROUPNAME_GROUPOFFSET_OFFSET; ++ u32DstAddr = MDrv_PQBin_Get4ByteData((void *)(u32Addr+u32Offset), &u32Offset) + ++ pPQTextBinHeader->u32BinStartAddress; ++ ++ u32Total_Len = 0; ++ for(i=0; i< u16TabIdx; i++) ++ { ++ u32Offset = PQ_TEXT_BIN_GROUPNAME_GROUPOFFSET_LEN + ++ PQ_TEXT_BIN_GROUPNAME_GROUPLENGTH_LEN * i; ++ ++ u32Total_Len += MDrv_PQBin_Get2ByteData((void *)(u32Addr+u32Offset), &u32Offset); ++ } ++ ++ PQ_TEXT_BIN_DBG(printf("PQTextBin GroupName: %lx\n", (u32DstAddr+u32Total_Len))); ++ return (u32DstAddr+u32Total_Len); ++} ++ ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ_Text.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ_Text.c +new file mode 100644 +index 00000000..72ca383c +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvPQ_Text.c +@@ -0,0 +1,135 @@ ++// $Change: 600891 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++ ++#include "MsCommon.h" ++#include "MsTypes.h" ++ ++#include "drvPQ_Define.h" ++#include "drvPQ.h" ++ ++//#include "QualityMap_Text.c" ++#include "drvPQ_Bin.h" ++ ++ ++#if(ENABLE_PQ_BIN) ++MS_PQTextBin_Header_Info stPQTextBinHeaderInfo[MAX_PQ_TEXT_BIN_NUM]; ++MS_BOOL gbEnablePQTextBin = 0; ++#endif ++ ++#if 0 ++char* MDrv_PQ_GetSrcTypeName(PQ_WIN eWindow) ++{ ++#if(ENABLE_PQ_BIN) ++ if(gbEnablePQTextBin) ++ { ++ MS_U32 u32Addr; ++ MS_U16 u16SrcIDx = MDrv_PQ_GetSrcType(eWindow); ++ ++ u32Addr = MDrv_PQTextBin_GetSrcType(u16SrcIDx, &stPQTextBinHeaderInfo[eWindow]); ++ return ((char *)u32Addr); ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ return NULL; ++ #else ++ return PQ_INPUTTYPE_TEXT_Main[MDrv_PQ_GetSrcType(eWindow)]; ++ #endif ++ } ++} ++ ++char* MDrv_PQ_GetIPName(MS_U8 u8PQIPIdx) ++{ ++#if(ENABLE_PQ_BIN) ++ ++ if(gbEnablePQTextBin) ++ { ++ MS_U32 u32Addr;; ++ u32Addr = MDrv_PQTextBin_GetIPName((MS_U16)u8PQIPIdx, &stPQTextBinHeaderInfo[PQ_MAIN_WINDOW]); ++ return ((char *)u32Addr); ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ return NULL; ++ #else ++ return PQ_IP_Text_Main[u8PQIPIdx]; ++ #endif ++ } ++} ++ ++char* MDrv_PQ_GetTableName(MS_U8 u8PQIPIdx, MS_U8 u8TabIdx ) ++{ ++#if(ENABLE_PQ_BIN) ++ if(gbEnablePQTextBin) ++ { ++ MS_U32 u32Addr;; ++ u32Addr = MDrv_PQTextBin_GetTableName((MS_U16)u8PQIPIdx, ++ (MS_U16)u8TabIdx, ++ &stPQTextBinHeaderInfo[PQ_MAIN_WINDOW]); ++ return ((char *)u32Addr); ++ ++ } ++ else ++#endif ++ { ++ #if(PQ_ONLY_SUPPORT_BIN) ++ return NULL; ++ #else ++ char** PQ_Stream; ++ ++ PQ_Stream = PQ_IPTAB_TEXT_Main[u8PQIPIdx]; ++ return PQ_Stream[u8TabIdx]; ++ #endif ++ } ++} ++ ++#if 0 ++void MDrv_PQ_Text_Demo(SCALER_WIN eWindow) ++{ ++ MS_U8 u8IPIdx, u8TabIdx, u8IPNum, u8TabNum; ++ U16 u16PQSrcType; ++ ++ u16PQSrcType = MDrv_PQ_GetSrcType(eWindow); ++ printf("u16PQSrcType=%u\n", u16PQSrcType); ++ ++ u8IPNum = MDrv_PQ_GetIPNum(eWindow); ++ ++ for( u8IPIdx = 0; u8IPIdx < u8IPNum; u8IPIdx++) ++ { ++ u8TabNum = MDrv_PQ_GetTableNum(eWindow, u8IPIdx); ++ printf("IP:%u [%s], tabnum=%u\n", u8IPIdx, MDrv_PQ_GetIPName(u8IPIdx), u8TabNum); ++ ++ u8TabIdx = MDrv_PQ_GetCurrentTableIndex(eWindow, u8IPIdx); ++ printf("TAB:%u [%s]\n", u8TabIdx, ++ (u8TabIdx == PQ_IP_NULL) ? "null" : MDrv_PQ_GetTableName(u8IPIdx, u8TabIdx)); ++ } ++} ++#endif ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/drvbw.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvbw.c +new file mode 100644 +index 00000000..7d7ed40c +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/drvbw.c +@@ -0,0 +1,265 @@ ++// $Change: 617839 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++#include "MsCommon.h" ++#include "MsTypes.h" ++#include "hwreg_utility2.h" ++#include "drvXC_IOPort.h" ++#include "apiXC.h" ++#include "color_reg.h" ++#include "drvPQ_Define.h" ++#include "drvPQ.h" ++#include "QualityMode.h" ++ ++ ++extern MS_PQ_Mode_Info _stMode_Info[PQ_MAX_WINDOW]; ++ ++#define BW_DBG(x) //x ++ ++ ++ ++typedef struct ++{ ++ MS_U8 *pIPTable; ++ MS_U8 u8TabNums; ++ MS_U8 u8TabIdx; ++} TAB_Info; ++ ++#include "Cedric_QualityMap_BW.c" ++ ++static MS_U8 *pBwTable=(void*)BWTABLE; ++ ++static void _MDrv_BW_LoadTable(MS_U8 u8TabIdx) ++{ ++ TAB_Info tab_Info; ++ tab_Info.pIPTable = pBwTable; ++ tab_Info.u8TabNums = BWTABLE_NUMS; ++ tab_Info.u8TabIdx = u8TabIdx; ++ ++ BW_DBG(printf("[BW]LoadTable\n")); ++ ++ _MDrv_BW_DumpTable(&tab_Info); ++} ++ ++void MDrv_BW_LoadInitTable(void) ++{ ++ TAB_Info tab_Info; ++ tab_Info.pIPTable = (void*)BWTABLE_COM; ++ tab_Info.u8TabNums = 1; ++ tab_Info.u8TabIdx = 0; ++ ++ BW_DBG(printf("[BW]LoadCommTable\n")); ++ _MDrv_BW_DumpTable(&tab_Info); ++} ++ ++#ifdef __AEONR2__ //janus ++void MDrv_BW_LoadTableByContext(PQ_WIN eWindow) ++{ ++ MS_U16 u16Input_HSize; ++ MS_U16 u16Input_VSize; ++ MS_U16 u16Input_VFreq; ++ MS_BOOL bIsInterlaced; ++ MS_U8 u8TabIdx; ++ PQ_INPUT_SOURCE_TYPE pqInputSourceType; ++ ++ u16Input_HSize = _stMode_Info[eWindow].u16input_hsize; ++ u16Input_VSize = _stMode_Info[eWindow].u16input_vsize; ++ u16Input_VFreq = _stMode_Info[eWindow].u16input_vfreq; ++ bIsInterlaced = _stMode_Info[eWindow].bInterlace; ++ pqInputSourceType = MDrv_PQ_GetInputSourceType(eWindow); ++ ++ if ( QM_IsSourceMultiMedia(pqInputSourceType) ) ++ { ++ if(u16Input_HSize>1280 && u16Input_VSize>=900) ++ u8TabIdx = BWTABLE_MM; ++ else ++ u8TabIdx = BWTABLE_MM_720p; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced && (u16Input_VFreq >= 490)) ++ { ++ // 1920x1080@50/60p ++ if( QM_IsSourceVGA(pqInputSourceType) ) ++ { ++ u8TabIdx = BWTABLE_PC_mode; ++ } ++ else ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ } ++ else ++ { ++ if ( QM_IsSourceATV(pqInputSourceType) || QM_IsSourceAV(pqInputSourceType) || QM_IsSourceSV(pqInputSourceType) ) ++ u8TabIdx = BWTABLE_Normal_mode; ++ else ++ u8TabIdx = BWTABLE_case6; ++ } ++ ++ pBwTable=_MDrv_BW_DDR_Speed(); ++ ++ _MDrv_BW_LoadTable(u8TabIdx); ++} ++ ++#else ++ ++void MDrv_BW_LoadTableByContext(PQ_WIN eWindow) ++{ ++ ++ MS_U16 u16Input_HSize; ++ MS_U16 u16Input_VSize; ++ MS_BOOL bIsInterlaced; ++ MS_U8 u8TabIdx; ++ MS_U16 u16Input_VFreq; ++ MS_U16 u16input_vtotal; ++ ++ u16Input_HSize = _stMode_Info[eWindow].u16input_hsize; ++ u16Input_VSize = _stMode_Info[eWindow].u16input_vsize; ++ bIsInterlaced = _stMode_Info[eWindow].bInterlace; ++ u16Input_VFreq = _stMode_Info[eWindow].u16input_vfreq; ++ u16input_vtotal = _stMode_Info[eWindow].u16input_vtotal; ++ ++//![for temporary A3-WinCE6 porting, 20120109] ++#if (defined(MSOS_TYPE_CE) || defined(MSOS_TYPE_LINUX_KERNEL)) ++ ++ if (u16Input_HSize>=1440 && u16Input_VSize >= 900) ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ ++#else ++ ++ #if ((CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD) && !ENABLE_MIU_1) ++ ++ if(QM_IsSourceMultiMedia(MDrv_PQ_GetInputSourceType(eWindow))) ++ { ++ u8TabIdx = BWTABLE_MM; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced && (u16Input_VFreq >= 490)) ++ { ++ // 1920x1080@50/60p ++ if(QM_IsSourceVGA(MDrv_PQ_GetInputSourceType(eWindow))) ++ { ++ u8TabIdx = BWTABLE_PC_mode; ++ } ++ else ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ } ++ else ++ { ++ if(QM_IsSourceDTV(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize >= 720) //DTV 720P and 1080i case ++ { ++ //printf(">>>111 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_720p_1080i_mode; ++ } ++ else ++ { ++ //printf(">>>222 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ } ++ ++ #elif (CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD) ++ ++ if(u16Input_HSize>=1024 && u16Input_VSize >= 768 && !bIsInterlaced && (u16Input_VFreq >= 490) && QM_IsSourceVGA(MDrv_PQ_GetInputSourceType(eWindow))) ++ { ++ u8TabIdx = BWTABLE_PC_mode; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced) ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ else if(QM_IsSourceDTV(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize >= 720) //DTV 720P and 1080i case ++ { ++ //printf(">>>333 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_720p_1080i_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ ++ #elif (CHIP_FAMILY_TYPE == CHIP_FAMILY_A6) ++ ++ if(QM_IsSourceMultiMedia(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize > 2000) //MPO case ++ { ++ //printf(">>>333 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_mpo_mode; ++ } ++ else if (u16Input_HSize>=1440 && u16Input_VSize >= 900 && !bIsInterlaced) ++ { ++ if(QM_IsSourceVGA(MDrv_PQ_GetInputSourceType(eWindow)) && (u16input_vtotal ==1120)) ++ { ++ //printf("print u16input_vtotal = %d\n",u16input_vtotal); ++ //patch for special vga 1080p timing with vtotal 1120, htt 2576 ++ u8TabIdx = BWTABLE_S1080p_mode; ++ } ++ else ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ } ++ else ++ { ++ if(QM_IsSourceDTV(MDrv_PQ_GetInputSourceType(eWindow)) && u16Input_VSize > 720) //DTV 1080i case ++ { ++ //printf(">>>333 BWTABLE_720p_1080i_mode\n"); ++ u8TabIdx = BWTABLE_1080i_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ } ++ ++ #else ++ ++ if (u16Input_HSize>=1440 && u16Input_VSize >= 900) ++ { ++ u8TabIdx = BWTABLE_1080p_mode; ++ } ++ else ++ { ++ // printf(">>>444 BWTABLE_Normal_mode\n"); ++ u8TabIdx = BWTABLE_Normal_mode; ++ } ++ ++ #endif ++ ++#endif ++ ++ ++ _MDrv_BW_LoadTable(u8TabIdx); ++ ++} ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/QualityMap_Main.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/QualityMap_Main.c +new file mode 100644 +index 00000000..2b6bb796 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/QualityMap_Main.c +@@ -0,0 +1,50 @@ ++// $Change: 616729 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++ ++#define PQTABLE_NAME MAIN // table config parameter ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++#include "MsTypes.h" ++#include "color_reg.h" ++#include "drvPQ_Define.h" ++#include "drvPQ_Declare.h" ++#include "drvPQ.h" ++#include "hwreg_utility2.h" ++ ++#define PQTBL_REGTYPE PQTBL_NORMAL // table config parameter ++ ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++ ++#include "Infinity3e_Main.c" // table config parameter ++#include "Infinity3e_Main_1920.c" // table config parameter ++#include "Infinity3e_Main_HSPRule.c" // table config parameter ++#include "Infinity3e_Main_VSPRule.c" // table config parameter ++#include "Infinity3e_Main_GRule.c" // table config parameter ++#include "Infinity3e_Main_1920_GRule.c" // table config parameter ++#endif ++ ++#include "QualityMode.h" ++#include "drvPQ_Datatypes.h" ++#include "mhal_pq.h" ++#include "drvPQ_Template.h" +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/color_reg.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/color_reg.h +new file mode 100644 +index 00000000..ce1934e8 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/color_reg.h +@@ -0,0 +1,13951 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#ifndef _COLOR_REG_H_ ++#define _COLOR_REG_H_ ++/////////////////////////////////////////////////////// ++// Scaler Bank ++/////////////////////////////////////////////////////// ++#define REG_BANK_RESET 0x00 ++#define REG_BANK_GOPINT 0x00 ++#define REG_BANK_IP1F2 0x01 ++#define REG_BANK_IP2F2 0x02 ++#define REG_BANK_IP1F1 0x03 ++#define REG_BANK_IP2F1 0x04 ++#define REG_BANK_OPM 0x05 ++#define REG_BANK_DNR 0x06 ++#define REG_BANK_OP1 0x07 ++#define REG_BANK_OP1PIP 0x08 ++#define REG_BANK_OP1HVSP 0x09 ++#define REG_BANK_FILM 0x0A //T2 ++#define REG_BANK_ELA 0x0B ++#define REG_BANK_ACE 0x0C ++#define REG_BANK_HD 0x0E ++#define REG_BANK_S_VOP 0x0F ++#define REG_BANK_VOP 0x10 ++#define REG_BANK_TCON 0x11 ++#define REG_BANK_SCMI 0x12 //T2 ++#define REG_BANK_OD 0x16 ++#define REG_BANK_SRAM 0x17 ++#define REG_BANK_VIP 0x18 ++#define REG_BANK_VPS 0x19 ++#define REG_BANK_DLC 0x1A ++#define REG_BANK_OP1PIPEXT 0x1B ++#define REG_BANK_SmoothFilter 0x1C ++#define REG_BANK_MFC 0x1D ++#define REG_BANK_PIP 0x20 ++#define REG_BANK_EODI 0x21 ++#define REG_BANK_MADI 0x22 ++#define REG_BANK_HVSP 0x23 ++#define REG_BANK_DMS 0x26 ++#define REG_BANK_PRED 0x28 ++// Scaler Base ++#define BK_IPMUX_BASE 0x2E00 ++//#define BK_SCALER_BASE 0x102F00 ++#define BK_MOD_BASE 0x3200 ++#define BK_TCON_BASE 0x3000 ++#define BK_LPLL_BASE 0x3100 ++#define REG_GOP_BANK 0x101FFE ++#define MAKE_ADDR(_x_) (0x100000 | _x_) ++// MVOP Base ++#define VOP_MPG_JPG_SWITCH 0x1440 ++#define VOP_UV_SHIFT 0x1460 ++#define _PK_L_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2)) ++#define _PK_H_(bank, addr) (((MS_U16)bank << 8) | (MS_U16)(addr*2+1)) ++#define REG_SC_DUMMY _PK_L_(0xFF, 0x01) ++#define REG_TABLE_END 0xFFFF ++//---------------------------------------------- ++#define REG_SC_BK00_00_L _PK_L_(0x00, 0x00) ++#define REG_SC_BK00_00_H _PK_H_(0x00, 0x00) ++#define REG_SC_BK00_01_L _PK_L_(0x00, 0x01) ++#define REG_SC_BK00_01_H _PK_H_(0x00, 0x01) ++#define REG_SC_BK00_02_L _PK_L_(0x00, 0x02) ++#define REG_SC_BK00_02_H _PK_H_(0x00, 0x02) ++#define REG_SC_BK00_03_L _PK_L_(0x00, 0x03) ++#define REG_SC_BK00_03_H _PK_H_(0x00, 0x03) ++#define REG_SC_BK00_04_L _PK_L_(0x00, 0x04) ++#define REG_SC_BK00_04_H _PK_H_(0x00, 0x04) ++#define REG_SC_BK00_05_L _PK_L_(0x00, 0x05) ++#define REG_SC_BK00_05_H _PK_H_(0x00, 0x05) ++#define REG_SC_BK00_06_L _PK_L_(0x00, 0x06) ++#define REG_SC_BK00_06_H _PK_H_(0x00, 0x06) ++#define REG_SC_BK00_07_L _PK_L_(0x00, 0x07) ++#define REG_SC_BK00_07_H _PK_H_(0x00, 0x07) ++#define REG_SC_BK00_08_L _PK_L_(0x00, 0x08) ++#define REG_SC_BK00_08_H _PK_H_(0x00, 0x08) ++#define REG_SC_BK00_09_L _PK_L_(0x00, 0x09) ++#define REG_SC_BK00_09_H _PK_H_(0x00, 0x09) ++#define REG_SC_BK00_0A_L _PK_L_(0x00, 0x0A) ++#define REG_SC_BK00_0A_H _PK_H_(0x00, 0x0A) ++#define REG_SC_BK00_0B_L _PK_L_(0x00, 0x0B) ++#define REG_SC_BK00_0B_H _PK_H_(0x00, 0x0B) ++#define REG_SC_BK00_0C_L _PK_L_(0x00, 0x0C) ++#define REG_SC_BK00_0C_H _PK_H_(0x00, 0x0C) ++#define REG_SC_BK00_0D_L _PK_L_(0x00, 0x0D) ++#define REG_SC_BK00_0D_H _PK_H_(0x00, 0x0D) ++#define REG_SC_BK00_0E_L _PK_L_(0x00, 0x0E) ++#define REG_SC_BK00_0E_H _PK_H_(0x00, 0x0E) ++#define REG_SC_BK00_0F_L _PK_L_(0x00, 0x0F) ++#define REG_SC_BK00_0F_H _PK_H_(0x00, 0x0F) ++#define REG_SC_BK00_10_L _PK_L_(0x00, 0x10) ++#define REG_SC_BK00_10_H _PK_H_(0x00, 0x10) ++#define REG_SC_BK00_11_L _PK_L_(0x00, 0x11) ++#define REG_SC_BK00_11_H _PK_H_(0x00, 0x11) ++#define REG_SC_BK00_12_L _PK_L_(0x00, 0x12) ++#define REG_SC_BK00_12_H _PK_H_(0x00, 0x12) ++#define REG_SC_BK00_13_L _PK_L_(0x00, 0x13) ++#define REG_SC_BK00_13_H _PK_H_(0x00, 0x13) ++#define REG_SC_BK00_14_L _PK_L_(0x00, 0x14) ++#define REG_SC_BK00_14_H _PK_H_(0x00, 0x14) ++#define REG_SC_BK00_15_L _PK_L_(0x00, 0x15) ++#define REG_SC_BK00_15_H _PK_H_(0x00, 0x15) ++#define REG_SC_BK00_16_L _PK_L_(0x00, 0x16) ++#define REG_SC_BK00_16_H _PK_H_(0x00, 0x16) ++#define REG_SC_BK00_17_L _PK_L_(0x00, 0x17) ++#define REG_SC_BK00_17_H _PK_H_(0x00, 0x17) ++#define REG_SC_BK00_18_L _PK_L_(0x00, 0x18) ++#define REG_SC_BK00_18_H _PK_H_(0x00, 0x18) ++#define REG_SC_BK00_19_L _PK_L_(0x00, 0x19) ++#define REG_SC_BK00_19_H _PK_H_(0x00, 0x19) ++#define REG_SC_BK00_1A_L _PK_L_(0x00, 0x1A) ++#define REG_SC_BK00_1A_H _PK_H_(0x00, 0x1A) ++#define REG_SC_BK00_1B_L _PK_L_(0x00, 0x1B) ++#define REG_SC_BK00_1B_H _PK_H_(0x00, 0x1B) ++#define REG_SC_BK00_1C_L _PK_L_(0x00, 0x1C) ++#define REG_SC_BK00_1C_H _PK_H_(0x00, 0x1C) ++#define REG_SC_BK00_1D_L _PK_L_(0x00, 0x1D) ++#define REG_SC_BK00_1D_H _PK_H_(0x00, 0x1D) ++#define REG_SC_BK00_1E_L _PK_L_(0x00, 0x1E) ++#define REG_SC_BK00_1E_H _PK_H_(0x00, 0x1E) ++#define REG_SC_BK00_1F_L _PK_L_(0x00, 0x1F) ++#define REG_SC_BK00_1F_H _PK_H_(0x00, 0x1F) ++#define REG_SC_BK00_20_L _PK_L_(0x00, 0x20) ++#define REG_SC_BK00_20_H _PK_H_(0x00, 0x20) ++#define REG_SC_BK00_21_L _PK_L_(0x00, 0x21) ++#define REG_SC_BK00_21_H _PK_H_(0x00, 0x21) ++#define REG_SC_BK00_22_L _PK_L_(0x00, 0x22) ++#define REG_SC_BK00_22_H _PK_H_(0x00, 0x22) ++#define REG_SC_BK00_23_L _PK_L_(0x00, 0x23) ++#define REG_SC_BK00_23_H _PK_H_(0x00, 0x23) ++#define REG_SC_BK00_24_L _PK_L_(0x00, 0x24) ++#define REG_SC_BK00_24_H _PK_H_(0x00, 0x24) ++#define REG_SC_BK00_25_L _PK_L_(0x00, 0x25) ++#define REG_SC_BK00_25_H _PK_H_(0x00, 0x25) ++#define REG_SC_BK00_26_L _PK_L_(0x00, 0x26) ++#define REG_SC_BK00_26_H _PK_H_(0x00, 0x26) ++#define REG_SC_BK00_27_L _PK_L_(0x00, 0x27) ++#define REG_SC_BK00_27_H _PK_H_(0x00, 0x27) ++#define REG_SC_BK00_28_L _PK_L_(0x00, 0x28) ++#define REG_SC_BK00_28_H _PK_H_(0x00, 0x28) ++#define REG_SC_BK00_29_L _PK_L_(0x00, 0x29) ++#define REG_SC_BK00_29_H _PK_H_(0x00, 0x29) ++#define REG_SC_BK00_2A_L _PK_L_(0x00, 0x2A) ++#define REG_SC_BK00_2A_H _PK_H_(0x00, 0x2A) ++#define REG_SC_BK00_2B_L _PK_L_(0x00, 0x2B) ++#define REG_SC_BK00_2B_H _PK_H_(0x00, 0x2B) ++#define REG_SC_BK00_2C_L _PK_L_(0x00, 0x2C) ++#define REG_SC_BK00_2C_H _PK_H_(0x00, 0x2C) ++#define REG_SC_BK00_2D_L _PK_L_(0x00, 0x2D) ++#define REG_SC_BK00_2D_H _PK_H_(0x00, 0x2D) ++#define REG_SC_BK00_2E_L _PK_L_(0x00, 0x2E) ++#define REG_SC_BK00_2E_H _PK_H_(0x00, 0x2E) ++#define REG_SC_BK00_2F_L _PK_L_(0x00, 0x2F) ++#define REG_SC_BK00_2F_H _PK_H_(0x00, 0x2F) ++#define REG_SC_BK00_30_L _PK_L_(0x00, 0x30) ++#define REG_SC_BK00_30_H _PK_H_(0x00, 0x30) ++#define REG_SC_BK00_31_L _PK_L_(0x00, 0x31) ++#define REG_SC_BK00_31_H _PK_H_(0x00, 0x31) ++#define REG_SC_BK00_32_L _PK_L_(0x00, 0x32) ++#define REG_SC_BK00_32_H _PK_H_(0x00, 0x32) ++#define REG_SC_BK00_33_L _PK_L_(0x00, 0x33) ++#define REG_SC_BK00_33_H _PK_H_(0x00, 0x33) ++#define REG_SC_BK00_34_L _PK_L_(0x00, 0x34) ++#define REG_SC_BK00_34_H _PK_H_(0x00, 0x34) ++#define REG_SC_BK00_35_L _PK_L_(0x00, 0x35) ++#define REG_SC_BK00_35_H _PK_H_(0x00, 0x35) ++#define REG_SC_BK00_36_L _PK_L_(0x00, 0x36) ++#define REG_SC_BK00_36_H _PK_H_(0x00, 0x36) ++#define REG_SC_BK00_37_L _PK_L_(0x00, 0x37) ++#define REG_SC_BK00_37_H _PK_H_(0x00, 0x37) ++#define REG_SC_BK00_38_L _PK_L_(0x00, 0x38) ++#define REG_SC_BK00_38_H _PK_H_(0x00, 0x38) ++#define REG_SC_BK00_39_L _PK_L_(0x00, 0x39) ++#define REG_SC_BK00_39_H _PK_H_(0x00, 0x39) ++#define REG_SC_BK00_3A_L _PK_L_(0x00, 0x3A) ++#define REG_SC_BK00_3A_H _PK_H_(0x00, 0x3A) ++#define REG_SC_BK00_3B_L _PK_L_(0x00, 0x3B) ++#define REG_SC_BK00_3B_H _PK_H_(0x00, 0x3B) ++#define REG_SC_BK00_3C_L _PK_L_(0x00, 0x3C) ++#define REG_SC_BK00_3C_H _PK_H_(0x00, 0x3C) ++#define REG_SC_BK00_3D_L _PK_L_(0x00, 0x3D) ++#define REG_SC_BK00_3D_H _PK_H_(0x00, 0x3D) ++#define REG_SC_BK00_3E_L _PK_L_(0x00, 0x3E) ++#define REG_SC_BK00_3E_H _PK_H_(0x00, 0x3E) ++#define REG_SC_BK00_3F_L _PK_L_(0x00, 0x3F) ++#define REG_SC_BK00_3F_H _PK_H_(0x00, 0x3F) ++#define REG_SC_BK00_40_L _PK_L_(0x00, 0x40) ++#define REG_SC_BK00_40_H _PK_H_(0x00, 0x40) ++#define REG_SC_BK00_41_L _PK_L_(0x00, 0x41) ++#define REG_SC_BK00_41_H _PK_H_(0x00, 0x41) ++#define REG_SC_BK00_42_L _PK_L_(0x00, 0x42) ++#define REG_SC_BK00_42_H _PK_H_(0x00, 0x42) ++#define REG_SC_BK00_43_L _PK_L_(0x00, 0x43) ++#define REG_SC_BK00_43_H _PK_H_(0x00, 0x43) ++#define REG_SC_BK00_44_L _PK_L_(0x00, 0x44) ++#define REG_SC_BK00_44_H _PK_H_(0x00, 0x44) ++#define REG_SC_BK00_45_L _PK_L_(0x00, 0x45) ++#define REG_SC_BK00_45_H _PK_H_(0x00, 0x45) ++#define REG_SC_BK00_46_L _PK_L_(0x00, 0x46) ++#define REG_SC_BK00_46_H _PK_H_(0x00, 0x46) ++#define REG_SC_BK00_47_L _PK_L_(0x00, 0x47) ++#define REG_SC_BK00_47_H _PK_H_(0x00, 0x47) ++#define REG_SC_BK00_48_L _PK_L_(0x00, 0x48) ++#define REG_SC_BK00_48_H _PK_H_(0x00, 0x48) ++#define REG_SC_BK00_49_L _PK_L_(0x00, 0x49) ++#define REG_SC_BK00_49_H _PK_H_(0x00, 0x49) ++#define REG_SC_BK00_4A_L _PK_L_(0x00, 0x4A) ++#define REG_SC_BK00_4A_H _PK_H_(0x00, 0x4A) ++#define REG_SC_BK00_4B_L _PK_L_(0x00, 0x4B) ++#define REG_SC_BK00_4B_H _PK_H_(0x00, 0x4B) ++#define REG_SC_BK00_4C_L _PK_L_(0x00, 0x4C) ++#define REG_SC_BK00_4C_H _PK_H_(0x00, 0x4C) ++#define REG_SC_BK00_4D_L _PK_L_(0x00, 0x4D) ++#define REG_SC_BK00_4D_H _PK_H_(0x00, 0x4D) ++#define REG_SC_BK00_4E_L _PK_L_(0x00, 0x4E) ++#define REG_SC_BK00_4E_H _PK_H_(0x00, 0x4E) ++#define REG_SC_BK00_4F_L _PK_L_(0x00, 0x4F) ++#define REG_SC_BK00_4F_H _PK_H_(0x00, 0x4F) ++#define REG_SC_BK00_50_L _PK_L_(0x00, 0x50) ++#define REG_SC_BK00_50_H _PK_H_(0x00, 0x50) ++#define REG_SC_BK00_51_L _PK_L_(0x00, 0x51) ++#define REG_SC_BK00_51_H _PK_H_(0x00, 0x51) ++#define REG_SC_BK00_52_L _PK_L_(0x00, 0x52) ++#define REG_SC_BK00_52_H _PK_H_(0x00, 0x52) ++#define REG_SC_BK00_53_L _PK_L_(0x00, 0x53) ++#define REG_SC_BK00_53_H _PK_H_(0x00, 0x53) ++#define REG_SC_BK00_54_L _PK_L_(0x00, 0x54) ++#define REG_SC_BK00_54_H _PK_H_(0x00, 0x54) ++#define REG_SC_BK00_55_L _PK_L_(0x00, 0x55) ++#define REG_SC_BK00_55_H _PK_H_(0x00, 0x55) ++#define REG_SC_BK00_56_L _PK_L_(0x00, 0x56) ++#define REG_SC_BK00_56_H _PK_H_(0x00, 0x56) ++#define REG_SC_BK00_57_L _PK_L_(0x00, 0x57) ++#define REG_SC_BK00_57_H _PK_H_(0x00, 0x57) ++#define REG_SC_BK00_58_L _PK_L_(0x00, 0x58) ++#define REG_SC_BK00_58_H _PK_H_(0x00, 0x58) ++#define REG_SC_BK00_59_L _PK_L_(0x00, 0x59) ++#define REG_SC_BK00_59_H _PK_H_(0x00, 0x59) ++#define REG_SC_BK00_5A_L _PK_L_(0x00, 0x5A) ++#define REG_SC_BK00_5A_H _PK_H_(0x00, 0x5A) ++#define REG_SC_BK00_5B_L _PK_L_(0x00, 0x5B) ++#define REG_SC_BK00_5B_H _PK_H_(0x00, 0x5B) ++#define REG_SC_BK00_5C_L _PK_L_(0x00, 0x5C) ++#define REG_SC_BK00_5C_H _PK_H_(0x00, 0x5C) ++#define REG_SC_BK00_5D_L _PK_L_(0x00, 0x5D) ++#define REG_SC_BK00_5D_H _PK_H_(0x00, 0x5D) ++#define REG_SC_BK00_5E_L _PK_L_(0x00, 0x5E) ++#define REG_SC_BK00_5E_H _PK_H_(0x00, 0x5E) ++#define REG_SC_BK00_5F_L _PK_L_(0x00, 0x5F) ++#define REG_SC_BK00_5F_H _PK_H_(0x00, 0x5F) ++#define REG_SC_BK00_60_L _PK_L_(0x00, 0x60) ++#define REG_SC_BK00_60_H _PK_H_(0x00, 0x60) ++#define REG_SC_BK00_61_L _PK_L_(0x00, 0x61) ++#define REG_SC_BK00_61_H _PK_H_(0x00, 0x61) ++#define REG_SC_BK00_62_L _PK_L_(0x00, 0x62) ++#define REG_SC_BK00_62_H _PK_H_(0x00, 0x62) ++#define REG_SC_BK00_63_L _PK_L_(0x00, 0x63) ++#define REG_SC_BK00_63_H _PK_H_(0x00, 0x63) ++#define REG_SC_BK00_64_L _PK_L_(0x00, 0x64) ++#define REG_SC_BK00_64_H _PK_H_(0x00, 0x64) ++#define REG_SC_BK00_65_L _PK_L_(0x00, 0x65) ++#define REG_SC_BK00_65_H _PK_H_(0x00, 0x65) ++#define REG_SC_BK00_66_L _PK_L_(0x00, 0x66) ++#define REG_SC_BK00_66_H _PK_H_(0x00, 0x66) ++#define REG_SC_BK00_67_L _PK_L_(0x00, 0x67) ++#define REG_SC_BK00_67_H _PK_H_(0x00, 0x67) ++#define REG_SC_BK00_68_L _PK_L_(0x00, 0x68) ++#define REG_SC_BK00_68_H _PK_H_(0x00, 0x68) ++#define REG_SC_BK00_69_L _PK_L_(0x00, 0x69) ++#define REG_SC_BK00_69_H _PK_H_(0x00, 0x69) ++#define REG_SC_BK00_6A_L _PK_L_(0x00, 0x6A) ++#define REG_SC_BK00_6A_H _PK_H_(0x00, 0x6A) ++#define REG_SC_BK00_6B_L _PK_L_(0x00, 0x6B) ++#define REG_SC_BK00_6B_H _PK_H_(0x00, 0x6B) ++#define REG_SC_BK00_6C_L _PK_L_(0x00, 0x6C) ++#define REG_SC_BK00_6C_H _PK_H_(0x00, 0x6C) ++#define REG_SC_BK00_6D_L _PK_L_(0x00, 0x6D) ++#define REG_SC_BK00_6D_H _PK_H_(0x00, 0x6D) ++#define REG_SC_BK00_6E_L _PK_L_(0x00, 0x6E) ++#define REG_SC_BK00_6E_H _PK_H_(0x00, 0x6E) ++#define REG_SC_BK00_6F_L _PK_L_(0x00, 0x6F) ++#define REG_SC_BK00_6F_H _PK_H_(0x00, 0x6F) ++#define REG_SC_BK00_70_L _PK_L_(0x00, 0x70) ++#define REG_SC_BK00_70_H _PK_H_(0x00, 0x70) ++#define REG_SC_BK00_71_L _PK_L_(0x00, 0x71) ++#define REG_SC_BK00_71_H _PK_H_(0x00, 0x71) ++#define REG_SC_BK00_72_L _PK_L_(0x00, 0x72) ++#define REG_SC_BK00_72_H _PK_H_(0x00, 0x72) ++#define REG_SC_BK00_73_L _PK_L_(0x00, 0x73) ++#define REG_SC_BK00_73_H _PK_H_(0x00, 0x73) ++#define REG_SC_BK00_74_L _PK_L_(0x00, 0x74) ++#define REG_SC_BK00_74_H _PK_H_(0x00, 0x74) ++#define REG_SC_BK00_75_L _PK_L_(0x00, 0x75) ++#define REG_SC_BK00_75_H _PK_H_(0x00, 0x75) ++#define REG_SC_BK00_76_L _PK_L_(0x00, 0x76) ++#define REG_SC_BK00_76_H _PK_H_(0x00, 0x76) ++#define REG_SC_BK00_77_L _PK_L_(0x00, 0x77) ++#define REG_SC_BK00_77_H _PK_H_(0x00, 0x77) ++#define REG_SC_BK00_78_L _PK_L_(0x00, 0x78) ++#define REG_SC_BK00_78_H _PK_H_(0x00, 0x78) ++#define REG_SC_BK00_79_L _PK_L_(0x00, 0x79) ++#define REG_SC_BK00_79_H _PK_H_(0x00, 0x79) ++#define REG_SC_BK00_7A_L _PK_L_(0x00, 0x7A) ++#define REG_SC_BK00_7A_H _PK_H_(0x00, 0x7A) ++#define REG_SC_BK00_7B_L _PK_L_(0x00, 0x7B) ++#define REG_SC_BK00_7B_H _PK_H_(0x00, 0x7B) ++#define REG_SC_BK00_7C_L _PK_L_(0x00, 0x7C) ++#define REG_SC_BK00_7C_H _PK_H_(0x00, 0x7C) ++#define REG_SC_BK00_7D_L _PK_L_(0x00, 0x7D) ++#define REG_SC_BK00_7D_H _PK_H_(0x00, 0x7D) ++#define REG_SC_BK00_7E_L _PK_L_(0x00, 0x7E) ++#define REG_SC_BK00_7E_H _PK_H_(0x00, 0x7E) ++#define REG_SC_BK00_7F_L _PK_L_(0x00, 0x7F) ++#define REG_SC_BK00_7F_H _PK_H_(0x00, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK01_00_L _PK_L_(0x01, 0x00) ++#define REG_SC_BK01_00_H _PK_H_(0x01, 0x00) ++#define REG_SC_BK01_01_L _PK_L_(0x01, 0x01) ++#define REG_SC_BK01_01_H _PK_H_(0x01, 0x01) ++#define REG_SC_BK01_02_L _PK_L_(0x01, 0x02) ++#define REG_SC_BK01_02_H _PK_H_(0x01, 0x02) ++#define REG_SC_BK01_03_L _PK_L_(0x01, 0x03) ++#define REG_SC_BK01_03_H _PK_H_(0x01, 0x03) ++#define REG_SC_BK01_04_L _PK_L_(0x01, 0x04) ++#define REG_SC_BK01_04_H _PK_H_(0x01, 0x04) ++#define REG_SC_BK01_05_L _PK_L_(0x01, 0x05) ++#define REG_SC_BK01_05_H _PK_H_(0x01, 0x05) ++#define REG_SC_BK01_06_L _PK_L_(0x01, 0x06) ++#define REG_SC_BK01_06_H _PK_H_(0x01, 0x06) ++#define REG_SC_BK01_07_L _PK_L_(0x01, 0x07) ++#define REG_SC_BK01_07_H _PK_H_(0x01, 0x07) ++#define REG_SC_BK01_08_L _PK_L_(0x01, 0x08) ++#define REG_SC_BK01_08_H _PK_H_(0x01, 0x08) ++#define REG_SC_BK01_09_L _PK_L_(0x01, 0x09) ++#define REG_SC_BK01_09_H _PK_H_(0x01, 0x09) ++#define REG_SC_BK01_0A_L _PK_L_(0x01, 0x0A) ++#define REG_SC_BK01_0A_H _PK_H_(0x01, 0x0A) ++#define REG_SC_BK01_0B_L _PK_L_(0x01, 0x0B) ++#define REG_SC_BK01_0B_H _PK_H_(0x01, 0x0B) ++#define REG_SC_BK01_0C_L _PK_L_(0x01, 0x0C) ++#define REG_SC_BK01_0C_H _PK_H_(0x01, 0x0C) ++#define REG_SC_BK01_0D_L _PK_L_(0x01, 0x0D) ++#define REG_SC_BK01_0D_H _PK_H_(0x01, 0x0D) ++#define REG_SC_BK01_0E_L _PK_L_(0x01, 0x0E) ++#define REG_SC_BK01_0E_H _PK_H_(0x01, 0x0E) ++#define REG_SC_BK01_0F_L _PK_L_(0x01, 0x0F) ++#define REG_SC_BK01_0F_H _PK_H_(0x01, 0x0F) ++#define REG_SC_BK01_10_L _PK_L_(0x01, 0x10) ++#define REG_SC_BK01_10_H _PK_H_(0x01, 0x10) ++#define REG_SC_BK01_11_L _PK_L_(0x01, 0x11) ++#define REG_SC_BK01_11_H _PK_H_(0x01, 0x11) ++#define REG_SC_BK01_12_L _PK_L_(0x01, 0x12) ++#define REG_SC_BK01_12_H _PK_H_(0x01, 0x12) ++#define REG_SC_BK01_13_L _PK_L_(0x01, 0x13) ++#define REG_SC_BK01_13_H _PK_H_(0x01, 0x13) ++#define REG_SC_BK01_14_L _PK_L_(0x01, 0x14) ++#define REG_SC_BK01_14_H _PK_H_(0x01, 0x14) ++#define REG_SC_BK01_15_L _PK_L_(0x01, 0x15) ++#define REG_SC_BK01_15_H _PK_H_(0x01, 0x15) ++#define REG_SC_BK01_16_L _PK_L_(0x01, 0x16) ++#define REG_SC_BK01_16_H _PK_H_(0x01, 0x16) ++#define REG_SC_BK01_17_L _PK_L_(0x01, 0x17) ++#define REG_SC_BK01_17_H _PK_H_(0x01, 0x17) ++#define REG_SC_BK01_18_L _PK_L_(0x01, 0x18) ++#define REG_SC_BK01_18_H _PK_H_(0x01, 0x18) ++#define REG_SC_BK01_19_L _PK_L_(0x01, 0x19) ++#define REG_SC_BK01_19_H _PK_H_(0x01, 0x19) ++#define REG_SC_BK01_1A_L _PK_L_(0x01, 0x1A) ++#define REG_SC_BK01_1A_H _PK_H_(0x01, 0x1A) ++#define REG_SC_BK01_1B_L _PK_L_(0x01, 0x1B) ++#define REG_SC_BK01_1B_H _PK_H_(0x01, 0x1B) ++#define REG_SC_BK01_1C_L _PK_L_(0x01, 0x1C) ++#define REG_SC_BK01_1C_H _PK_H_(0x01, 0x1C) ++#define REG_SC_BK01_1D_L _PK_L_(0x01, 0x1D) ++#define REG_SC_BK01_1D_H _PK_H_(0x01, 0x1D) ++#define REG_SC_BK01_1E_L _PK_L_(0x01, 0x1E) ++#define REG_SC_BK01_1E_H _PK_H_(0x01, 0x1E) ++#define REG_SC_BK01_1F_L _PK_L_(0x01, 0x1F) ++#define REG_SC_BK01_1F_H _PK_H_(0x01, 0x1F) ++#define REG_SC_BK01_20_L _PK_L_(0x01, 0x20) ++#define REG_SC_BK01_20_H _PK_H_(0x01, 0x20) ++#define REG_SC_BK01_21_L _PK_L_(0x01, 0x21) ++#define REG_SC_BK01_21_H _PK_H_(0x01, 0x21) ++#define REG_SC_BK01_22_L _PK_L_(0x01, 0x22) ++#define REG_SC_BK01_22_H _PK_H_(0x01, 0x22) ++#define REG_SC_BK01_23_L _PK_L_(0x01, 0x23) ++#define REG_SC_BK01_23_H _PK_H_(0x01, 0x23) ++#define REG_SC_BK01_24_L _PK_L_(0x01, 0x24) ++#define REG_SC_BK01_24_H _PK_H_(0x01, 0x24) ++#define REG_SC_BK01_25_L _PK_L_(0x01, 0x25) ++#define REG_SC_BK01_25_H _PK_H_(0x01, 0x25) ++#define REG_SC_BK01_26_L _PK_L_(0x01, 0x26) ++#define REG_SC_BK01_26_H _PK_H_(0x01, 0x26) ++#define REG_SC_BK01_27_L _PK_L_(0x01, 0x27) ++#define REG_SC_BK01_27_H _PK_H_(0x01, 0x27) ++#define REG_SC_BK01_28_L _PK_L_(0x01, 0x28) ++#define REG_SC_BK01_28_H _PK_H_(0x01, 0x28) ++#define REG_SC_BK01_29_L _PK_L_(0x01, 0x29) ++#define REG_SC_BK01_29_H _PK_H_(0x01, 0x29) ++#define REG_SC_BK01_2A_L _PK_L_(0x01, 0x2A) ++#define REG_SC_BK01_2A_H _PK_H_(0x01, 0x2A) ++#define REG_SC_BK01_2B_L _PK_L_(0x01, 0x2B) ++#define REG_SC_BK01_2B_H _PK_H_(0x01, 0x2B) ++#define REG_SC_BK01_2C_L _PK_L_(0x01, 0x2C) ++#define REG_SC_BK01_2C_H _PK_H_(0x01, 0x2C) ++#define REG_SC_BK01_2D_L _PK_L_(0x01, 0x2D) ++#define REG_SC_BK01_2D_H _PK_H_(0x01, 0x2D) ++#define REG_SC_BK01_2E_L _PK_L_(0x01, 0x2E) ++#define REG_SC_BK01_2E_H _PK_H_(0x01, 0x2E) ++#define REG_SC_BK01_2F_L _PK_L_(0x01, 0x2F) ++#define REG_SC_BK01_2F_H _PK_H_(0x01, 0x2F) ++#define REG_SC_BK01_30_L _PK_L_(0x01, 0x30) ++#define REG_SC_BK01_30_H _PK_H_(0x01, 0x30) ++#define REG_SC_BK01_31_L _PK_L_(0x01, 0x31) ++#define REG_SC_BK01_31_H _PK_H_(0x01, 0x31) ++#define REG_SC_BK01_32_L _PK_L_(0x01, 0x32) ++#define REG_SC_BK01_32_H _PK_H_(0x01, 0x32) ++#define REG_SC_BK01_33_L _PK_L_(0x01, 0x33) ++#define REG_SC_BK01_33_H _PK_H_(0x01, 0x33) ++#define REG_SC_BK01_34_L _PK_L_(0x01, 0x34) ++#define REG_SC_BK01_34_H _PK_H_(0x01, 0x34) ++#define REG_SC_BK01_35_L _PK_L_(0x01, 0x35) ++#define REG_SC_BK01_35_H _PK_H_(0x01, 0x35) ++#define REG_SC_BK01_36_L _PK_L_(0x01, 0x36) ++#define REG_SC_BK01_36_H _PK_H_(0x01, 0x36) ++#define REG_SC_BK01_37_L _PK_L_(0x01, 0x37) ++#define REG_SC_BK01_37_H _PK_H_(0x01, 0x37) ++#define REG_SC_BK01_38_L _PK_L_(0x01, 0x38) ++#define REG_SC_BK01_38_H _PK_H_(0x01, 0x38) ++#define REG_SC_BK01_39_L _PK_L_(0x01, 0x39) ++#define REG_SC_BK01_39_H _PK_H_(0x01, 0x39) ++#define REG_SC_BK01_3A_L _PK_L_(0x01, 0x3A) ++#define REG_SC_BK01_3A_H _PK_H_(0x01, 0x3A) ++#define REG_SC_BK01_3B_L _PK_L_(0x01, 0x3B) ++#define REG_SC_BK01_3B_H _PK_H_(0x01, 0x3B) ++#define REG_SC_BK01_3C_L _PK_L_(0x01, 0x3C) ++#define REG_SC_BK01_3C_H _PK_H_(0x01, 0x3C) ++#define REG_SC_BK01_3D_L _PK_L_(0x01, 0x3D) ++#define REG_SC_BK01_3D_H _PK_H_(0x01, 0x3D) ++#define REG_SC_BK01_3E_L _PK_L_(0x01, 0x3E) ++#define REG_SC_BK01_3E_H _PK_H_(0x01, 0x3E) ++#define REG_SC_BK01_3F_L _PK_L_(0x01, 0x3F) ++#define REG_SC_BK01_3F_H _PK_H_(0x01, 0x3F) ++#define REG_SC_BK01_40_L _PK_L_(0x01, 0x40) ++#define REG_SC_BK01_40_H _PK_H_(0x01, 0x40) ++#define REG_SC_BK01_41_L _PK_L_(0x01, 0x41) ++#define REG_SC_BK01_41_H _PK_H_(0x01, 0x41) ++#define REG_SC_BK01_42_L _PK_L_(0x01, 0x42) ++#define REG_SC_BK01_42_H _PK_H_(0x01, 0x42) ++#define REG_SC_BK01_43_L _PK_L_(0x01, 0x43) ++#define REG_SC_BK01_43_H _PK_H_(0x01, 0x43) ++#define REG_SC_BK01_44_L _PK_L_(0x01, 0x44) ++#define REG_SC_BK01_44_H _PK_H_(0x01, 0x44) ++#define REG_SC_BK01_45_L _PK_L_(0x01, 0x45) ++#define REG_SC_BK01_45_H _PK_H_(0x01, 0x45) ++#define REG_SC_BK01_46_L _PK_L_(0x01, 0x46) ++#define REG_SC_BK01_46_H _PK_H_(0x01, 0x46) ++#define REG_SC_BK01_47_L _PK_L_(0x01, 0x47) ++#define REG_SC_BK01_47_H _PK_H_(0x01, 0x47) ++#define REG_SC_BK01_48_L _PK_L_(0x01, 0x48) ++#define REG_SC_BK01_48_H _PK_H_(0x01, 0x48) ++#define REG_SC_BK01_49_L _PK_L_(0x01, 0x49) ++#define REG_SC_BK01_49_H _PK_H_(0x01, 0x49) ++#define REG_SC_BK01_4A_L _PK_L_(0x01, 0x4A) ++#define REG_SC_BK01_4A_H _PK_H_(0x01, 0x4A) ++#define REG_SC_BK01_4B_L _PK_L_(0x01, 0x4B) ++#define REG_SC_BK01_4B_H _PK_H_(0x01, 0x4B) ++#define REG_SC_BK01_4C_L _PK_L_(0x01, 0x4C) ++#define REG_SC_BK01_4C_H _PK_H_(0x01, 0x4C) ++#define REG_SC_BK01_4D_L _PK_L_(0x01, 0x4D) ++#define REG_SC_BK01_4D_H _PK_H_(0x01, 0x4D) ++#define REG_SC_BK01_4E_L _PK_L_(0x01, 0x4E) ++#define REG_SC_BK01_4E_H _PK_H_(0x01, 0x4E) ++#define REG_SC_BK01_4F_L _PK_L_(0x01, 0x4F) ++#define REG_SC_BK01_4F_H _PK_H_(0x01, 0x4F) ++#define REG_SC_BK01_50_L _PK_L_(0x01, 0x50) ++#define REG_SC_BK01_50_H _PK_H_(0x01, 0x50) ++#define REG_SC_BK01_51_L _PK_L_(0x01, 0x51) ++#define REG_SC_BK01_51_H _PK_H_(0x01, 0x51) ++#define REG_SC_BK01_52_L _PK_L_(0x01, 0x52) ++#define REG_SC_BK01_52_H _PK_H_(0x01, 0x52) ++#define REG_SC_BK01_53_L _PK_L_(0x01, 0x53) ++#define REG_SC_BK01_53_H _PK_H_(0x01, 0x53) ++#define REG_SC_BK01_54_L _PK_L_(0x01, 0x54) ++#define REG_SC_BK01_54_H _PK_H_(0x01, 0x54) ++#define REG_SC_BK01_55_L _PK_L_(0x01, 0x55) ++#define REG_SC_BK01_55_H _PK_H_(0x01, 0x55) ++#define REG_SC_BK01_56_L _PK_L_(0x01, 0x56) ++#define REG_SC_BK01_56_H _PK_H_(0x01, 0x56) ++#define REG_SC_BK01_57_L _PK_L_(0x01, 0x57) ++#define REG_SC_BK01_57_H _PK_H_(0x01, 0x57) ++#define REG_SC_BK01_58_L _PK_L_(0x01, 0x58) ++#define REG_SC_BK01_58_H _PK_H_(0x01, 0x58) ++#define REG_SC_BK01_59_L _PK_L_(0x01, 0x59) ++#define REG_SC_BK01_59_H _PK_H_(0x01, 0x59) ++#define REG_SC_BK01_5A_L _PK_L_(0x01, 0x5A) ++#define REG_SC_BK01_5A_H _PK_H_(0x01, 0x5A) ++#define REG_SC_BK01_5B_L _PK_L_(0x01, 0x5B) ++#define REG_SC_BK01_5B_H _PK_H_(0x01, 0x5B) ++#define REG_SC_BK01_5C_L _PK_L_(0x01, 0x5C) ++#define REG_SC_BK01_5C_H _PK_H_(0x01, 0x5C) ++#define REG_SC_BK01_5D_L _PK_L_(0x01, 0x5D) ++#define REG_SC_BK01_5D_H _PK_H_(0x01, 0x5D) ++#define REG_SC_BK01_5E_L _PK_L_(0x01, 0x5E) ++#define REG_SC_BK01_5E_H _PK_H_(0x01, 0x5E) ++#define REG_SC_BK01_5F_L _PK_L_(0x01, 0x5F) ++#define REG_SC_BK01_5F_H _PK_H_(0x01, 0x5F) ++#define REG_SC_BK01_60_L _PK_L_(0x01, 0x60) ++#define REG_SC_BK01_60_H _PK_H_(0x01, 0x60) ++#define REG_SC_BK01_61_L _PK_L_(0x01, 0x61) ++#define REG_SC_BK01_61_H _PK_H_(0x01, 0x61) ++#define REG_SC_BK01_62_L _PK_L_(0x01, 0x62) ++#define REG_SC_BK01_62_H _PK_H_(0x01, 0x62) ++#define REG_SC_BK01_63_L _PK_L_(0x01, 0x63) ++#define REG_SC_BK01_63_H _PK_H_(0x01, 0x63) ++#define REG_SC_BK01_64_L _PK_L_(0x01, 0x64) ++#define REG_SC_BK01_64_H _PK_H_(0x01, 0x64) ++#define REG_SC_BK01_65_L _PK_L_(0x01, 0x65) ++#define REG_SC_BK01_65_H _PK_H_(0x01, 0x65) ++#define REG_SC_BK01_66_L _PK_L_(0x01, 0x66) ++#define REG_SC_BK01_66_H _PK_H_(0x01, 0x66) ++#define REG_SC_BK01_67_L _PK_L_(0x01, 0x67) ++#define REG_SC_BK01_67_H _PK_H_(0x01, 0x67) ++#define REG_SC_BK01_68_L _PK_L_(0x01, 0x68) ++#define REG_SC_BK01_68_H _PK_H_(0x01, 0x68) ++#define REG_SC_BK01_69_L _PK_L_(0x01, 0x69) ++#define REG_SC_BK01_69_H _PK_H_(0x01, 0x69) ++#define REG_SC_BK01_6A_L _PK_L_(0x01, 0x6A) ++#define REG_SC_BK01_6A_H _PK_H_(0x01, 0x6A) ++#define REG_SC_BK01_6B_L _PK_L_(0x01, 0x6B) ++#define REG_SC_BK01_6B_H _PK_H_(0x01, 0x6B) ++#define REG_SC_BK01_6C_L _PK_L_(0x01, 0x6C) ++#define REG_SC_BK01_6C_H _PK_H_(0x01, 0x6C) ++#define REG_SC_BK01_6D_L _PK_L_(0x01, 0x6D) ++#define REG_SC_BK01_6D_H _PK_H_(0x01, 0x6D) ++#define REG_SC_BK01_6E_L _PK_L_(0x01, 0x6E) ++#define REG_SC_BK01_6E_H _PK_H_(0x01, 0x6E) ++#define REG_SC_BK01_6F_L _PK_L_(0x01, 0x6F) ++#define REG_SC_BK01_6F_H _PK_H_(0x01, 0x6F) ++#define REG_SC_BK01_70_L _PK_L_(0x01, 0x70) ++#define REG_SC_BK01_70_H _PK_H_(0x01, 0x70) ++#define REG_SC_BK01_71_L _PK_L_(0x01, 0x71) ++#define REG_SC_BK01_71_H _PK_H_(0x01, 0x71) ++#define REG_SC_BK01_72_L _PK_L_(0x01, 0x72) ++#define REG_SC_BK01_72_H _PK_H_(0x01, 0x72) ++#define REG_SC_BK01_73_L _PK_L_(0x01, 0x73) ++#define REG_SC_BK01_73_H _PK_H_(0x01, 0x73) ++#define REG_SC_BK01_74_L _PK_L_(0x01, 0x74) ++#define REG_SC_BK01_74_H _PK_H_(0x01, 0x74) ++#define REG_SC_BK01_75_L _PK_L_(0x01, 0x75) ++#define REG_SC_BK01_75_H _PK_H_(0x01, 0x75) ++#define REG_SC_BK01_76_L _PK_L_(0x01, 0x76) ++#define REG_SC_BK01_76_H _PK_H_(0x01, 0x76) ++#define REG_SC_BK01_77_L _PK_L_(0x01, 0x77) ++#define REG_SC_BK01_77_H _PK_H_(0x01, 0x77) ++#define REG_SC_BK01_78_L _PK_L_(0x01, 0x78) ++#define REG_SC_BK01_78_H _PK_H_(0x01, 0x78) ++#define REG_SC_BK01_79_L _PK_L_(0x01, 0x79) ++#define REG_SC_BK01_79_H _PK_H_(0x01, 0x79) ++#define REG_SC_BK01_7A_L _PK_L_(0x01, 0x7A) ++#define REG_SC_BK01_7A_H _PK_H_(0x01, 0x7A) ++#define REG_SC_BK01_7B_L _PK_L_(0x01, 0x7B) ++#define REG_SC_BK01_7B_H _PK_H_(0x01, 0x7B) ++#define REG_SC_BK01_7C_L _PK_L_(0x01, 0x7C) ++#define REG_SC_BK01_7C_H _PK_H_(0x01, 0x7C) ++#define REG_SC_BK01_7D_L _PK_L_(0x01, 0x7D) ++#define REG_SC_BK01_7D_H _PK_H_(0x01, 0x7D) ++#define REG_SC_BK01_7E_L _PK_L_(0x01, 0x7E) ++#define REG_SC_BK01_7E_H _PK_H_(0x01, 0x7E) ++#define REG_SC_BK01_7F_L _PK_L_(0x01, 0x7F) ++#define REG_SC_BK01_7F_H _PK_H_(0x01, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK02_00_L _PK_L_(0x02, 0x00) ++#define REG_SC_BK02_00_H _PK_H_(0x02, 0x00) ++#define REG_SC_BK02_01_L _PK_L_(0x02, 0x01) ++#define REG_SC_BK02_01_H _PK_H_(0x02, 0x01) ++#define REG_SC_BK02_02_L _PK_L_(0x02, 0x02) ++#define REG_SC_BK02_02_H _PK_H_(0x02, 0x02) ++#define REG_SC_BK02_03_L _PK_L_(0x02, 0x03) ++#define REG_SC_BK02_03_H _PK_H_(0x02, 0x03) ++#define REG_SC_BK02_04_L _PK_L_(0x02, 0x04) ++#define REG_SC_BK02_04_H _PK_H_(0x02, 0x04) ++#define REG_SC_BK02_05_L _PK_L_(0x02, 0x05) ++#define REG_SC_BK02_05_H _PK_H_(0x02, 0x05) ++#define REG_SC_BK02_06_L _PK_L_(0x02, 0x06) ++#define REG_SC_BK02_06_H _PK_H_(0x02, 0x06) ++#define REG_SC_BK02_07_L _PK_L_(0x02, 0x07) ++#define REG_SC_BK02_07_H _PK_H_(0x02, 0x07) ++#define REG_SC_BK02_08_L _PK_L_(0x02, 0x08) ++#define REG_SC_BK02_08_H _PK_H_(0x02, 0x08) ++#define REG_SC_BK02_09_L _PK_L_(0x02, 0x09) ++#define REG_SC_BK02_09_H _PK_H_(0x02, 0x09) ++#define REG_SC_BK02_0A_L _PK_L_(0x02, 0x0A) ++#define REG_SC_BK02_0A_H _PK_H_(0x02, 0x0A) ++#define REG_SC_BK02_0B_L _PK_L_(0x02, 0x0B) ++#define REG_SC_BK02_0B_H _PK_H_(0x02, 0x0B) ++#define REG_SC_BK02_0C_L _PK_L_(0x02, 0x0C) ++#define REG_SC_BK02_0C_H _PK_H_(0x02, 0x0C) ++#define REG_SC_BK02_0D_L _PK_L_(0x02, 0x0D) ++#define REG_SC_BK02_0D_H _PK_H_(0x02, 0x0D) ++#define REG_SC_BK02_0E_L _PK_L_(0x02, 0x0E) ++#define REG_SC_BK02_0E_H _PK_H_(0x02, 0x0E) ++#define REG_SC_BK02_0F_L _PK_L_(0x02, 0x0F) ++#define REG_SC_BK02_0F_H _PK_H_(0x02, 0x0F) ++#define REG_SC_BK02_10_L _PK_L_(0x02, 0x10) ++#define REG_SC_BK02_10_H _PK_H_(0x02, 0x10) ++#define REG_SC_BK02_11_L _PK_L_(0x02, 0x11) ++#define REG_SC_BK02_11_H _PK_H_(0x02, 0x11) ++#define REG_SC_BK02_12_L _PK_L_(0x02, 0x12) ++#define REG_SC_BK02_12_H _PK_H_(0x02, 0x12) ++#define REG_SC_BK02_13_L _PK_L_(0x02, 0x13) ++#define REG_SC_BK02_13_H _PK_H_(0x02, 0x13) ++#define REG_SC_BK02_14_L _PK_L_(0x02, 0x14) ++#define REG_SC_BK02_14_H _PK_H_(0x02, 0x14) ++#define REG_SC_BK02_15_L _PK_L_(0x02, 0x15) ++#define REG_SC_BK02_15_H _PK_H_(0x02, 0x15) ++#define REG_SC_BK02_16_L _PK_L_(0x02, 0x16) ++#define REG_SC_BK02_16_H _PK_H_(0x02, 0x16) ++#define REG_SC_BK02_17_L _PK_L_(0x02, 0x17) ++#define REG_SC_BK02_17_H _PK_H_(0x02, 0x17) ++#define REG_SC_BK02_18_L _PK_L_(0x02, 0x18) ++#define REG_SC_BK02_18_H _PK_H_(0x02, 0x18) ++#define REG_SC_BK02_19_L _PK_L_(0x02, 0x19) ++#define REG_SC_BK02_19_H _PK_H_(0x02, 0x19) ++#define REG_SC_BK02_1A_L _PK_L_(0x02, 0x1A) ++#define REG_SC_BK02_1A_H _PK_H_(0x02, 0x1A) ++#define REG_SC_BK02_1B_L _PK_L_(0x02, 0x1B) ++#define REG_SC_BK02_1B_H _PK_H_(0x02, 0x1B) ++#define REG_SC_BK02_1C_L _PK_L_(0x02, 0x1C) ++#define REG_SC_BK02_1C_H _PK_H_(0x02, 0x1C) ++#define REG_SC_BK02_1D_L _PK_L_(0x02, 0x1D) ++#define REG_SC_BK02_1D_H _PK_H_(0x02, 0x1D) ++#define REG_SC_BK02_1E_L _PK_L_(0x02, 0x1E) ++#define REG_SC_BK02_1E_H _PK_H_(0x02, 0x1E) ++#define REG_SC_BK02_1F_L _PK_L_(0x02, 0x1F) ++#define REG_SC_BK02_1F_H _PK_H_(0x02, 0x1F) ++#define REG_SC_BK02_20_L _PK_L_(0x02, 0x20) ++#define REG_SC_BK02_20_H _PK_H_(0x02, 0x20) ++#define REG_SC_BK02_21_L _PK_L_(0x02, 0x21) ++#define REG_SC_BK02_21_H _PK_H_(0x02, 0x21) ++#define REG_SC_BK02_22_L _PK_L_(0x02, 0x22) ++#define REG_SC_BK02_22_H _PK_H_(0x02, 0x22) ++#define REG_SC_BK02_23_L _PK_L_(0x02, 0x23) ++#define REG_SC_BK02_23_H _PK_H_(0x02, 0x23) ++#define REG_SC_BK02_24_L _PK_L_(0x02, 0x24) ++#define REG_SC_BK02_24_H _PK_H_(0x02, 0x24) ++#define REG_SC_BK02_25_L _PK_L_(0x02, 0x25) ++#define REG_SC_BK02_25_H _PK_H_(0x02, 0x25) ++#define REG_SC_BK02_26_L _PK_L_(0x02, 0x26) ++#define REG_SC_BK02_26_H _PK_H_(0x02, 0x26) ++#define REG_SC_BK02_27_L _PK_L_(0x02, 0x27) ++#define REG_SC_BK02_27_H _PK_H_(0x02, 0x27) ++#define REG_SC_BK02_28_L _PK_L_(0x02, 0x28) ++#define REG_SC_BK02_28_H _PK_H_(0x02, 0x28) ++#define REG_SC_BK02_29_L _PK_L_(0x02, 0x29) ++#define REG_SC_BK02_29_H _PK_H_(0x02, 0x29) ++#define REG_SC_BK02_2A_L _PK_L_(0x02, 0x2A) ++#define REG_SC_BK02_2A_H _PK_H_(0x02, 0x2A) ++#define REG_SC_BK02_2B_L _PK_L_(0x02, 0x2B) ++#define REG_SC_BK02_2B_H _PK_H_(0x02, 0x2B) ++#define REG_SC_BK02_2C_L _PK_L_(0x02, 0x2C) ++#define REG_SC_BK02_2C_H _PK_H_(0x02, 0x2C) ++#define REG_SC_BK02_2D_L _PK_L_(0x02, 0x2D) ++#define REG_SC_BK02_2D_H _PK_H_(0x02, 0x2D) ++#define REG_SC_BK02_2E_L _PK_L_(0x02, 0x2E) ++#define REG_SC_BK02_2E_H _PK_H_(0x02, 0x2E) ++#define REG_SC_BK02_2F_L _PK_L_(0x02, 0x2F) ++#define REG_SC_BK02_2F_H _PK_H_(0x02, 0x2F) ++#define REG_SC_BK02_30_L _PK_L_(0x02, 0x30) ++#define REG_SC_BK02_30_H _PK_H_(0x02, 0x30) ++#define REG_SC_BK02_31_L _PK_L_(0x02, 0x31) ++#define REG_SC_BK02_31_H _PK_H_(0x02, 0x31) ++#define REG_SC_BK02_32_L _PK_L_(0x02, 0x32) ++#define REG_SC_BK02_32_H _PK_H_(0x02, 0x32) ++#define REG_SC_BK02_33_L _PK_L_(0x02, 0x33) ++#define REG_SC_BK02_33_H _PK_H_(0x02, 0x33) ++#define REG_SC_BK02_34_L _PK_L_(0x02, 0x34) ++#define REG_SC_BK02_34_H _PK_H_(0x02, 0x34) ++#define REG_SC_BK02_35_L _PK_L_(0x02, 0x35) ++#define REG_SC_BK02_35_H _PK_H_(0x02, 0x35) ++#define REG_SC_BK02_36_L _PK_L_(0x02, 0x36) ++#define REG_SC_BK02_36_H _PK_H_(0x02, 0x36) ++#define REG_SC_BK02_37_L _PK_L_(0x02, 0x37) ++#define REG_SC_BK02_37_H _PK_H_(0x02, 0x37) ++#define REG_SC_BK02_38_L _PK_L_(0x02, 0x38) ++#define REG_SC_BK02_38_H _PK_H_(0x02, 0x38) ++#define REG_SC_BK02_39_L _PK_L_(0x02, 0x39) ++#define REG_SC_BK02_39_H _PK_H_(0x02, 0x39) ++#define REG_SC_BK02_3A_L _PK_L_(0x02, 0x3A) ++#define REG_SC_BK02_3A_H _PK_H_(0x02, 0x3A) ++#define REG_SC_BK02_3B_L _PK_L_(0x02, 0x3B) ++#define REG_SC_BK02_3B_H _PK_H_(0x02, 0x3B) ++#define REG_SC_BK02_3C_L _PK_L_(0x02, 0x3C) ++#define REG_SC_BK02_3C_H _PK_H_(0x02, 0x3C) ++#define REG_SC_BK02_3D_L _PK_L_(0x02, 0x3D) ++#define REG_SC_BK02_3D_H _PK_H_(0x02, 0x3D) ++#define REG_SC_BK02_3E_L _PK_L_(0x02, 0x3E) ++#define REG_SC_BK02_3E_H _PK_H_(0x02, 0x3E) ++#define REG_SC_BK02_3F_L _PK_L_(0x02, 0x3F) ++#define REG_SC_BK02_3F_H _PK_H_(0x02, 0x3F) ++#define REG_SC_BK02_40_L _PK_L_(0x02, 0x40) ++#define REG_SC_BK02_40_H _PK_H_(0x02, 0x40) ++#define REG_SC_BK02_41_L _PK_L_(0x02, 0x41) ++#define REG_SC_BK02_41_H _PK_H_(0x02, 0x41) ++#define REG_SC_BK02_42_L _PK_L_(0x02, 0x42) ++#define REG_SC_BK02_42_H _PK_H_(0x02, 0x42) ++#define REG_SC_BK02_43_L _PK_L_(0x02, 0x43) ++#define REG_SC_BK02_43_H _PK_H_(0x02, 0x43) ++#define REG_SC_BK02_44_L _PK_L_(0x02, 0x44) ++#define REG_SC_BK02_44_H _PK_H_(0x02, 0x44) ++#define REG_SC_BK02_45_L _PK_L_(0x02, 0x45) ++#define REG_SC_BK02_45_H _PK_H_(0x02, 0x45) ++#define REG_SC_BK02_46_L _PK_L_(0x02, 0x46) ++#define REG_SC_BK02_46_H _PK_H_(0x02, 0x46) ++#define REG_SC_BK02_47_L _PK_L_(0x02, 0x47) ++#define REG_SC_BK02_47_H _PK_H_(0x02, 0x47) ++#define REG_SC_BK02_48_L _PK_L_(0x02, 0x48) ++#define REG_SC_BK02_48_H _PK_H_(0x02, 0x48) ++#define REG_SC_BK02_49_L _PK_L_(0x02, 0x49) ++#define REG_SC_BK02_49_H _PK_H_(0x02, 0x49) ++#define REG_SC_BK02_4A_L _PK_L_(0x02, 0x4A) ++#define REG_SC_BK02_4A_H _PK_H_(0x02, 0x4A) ++#define REG_SC_BK02_4B_L _PK_L_(0x02, 0x4B) ++#define REG_SC_BK02_4B_H _PK_H_(0x02, 0x4B) ++#define REG_SC_BK02_4C_L _PK_L_(0x02, 0x4C) ++#define REG_SC_BK02_4C_H _PK_H_(0x02, 0x4C) ++#define REG_SC_BK02_4D_L _PK_L_(0x02, 0x4D) ++#define REG_SC_BK02_4D_H _PK_H_(0x02, 0x4D) ++#define REG_SC_BK02_4E_L _PK_L_(0x02, 0x4E) ++#define REG_SC_BK02_4E_H _PK_H_(0x02, 0x4E) ++#define REG_SC_BK02_4F_L _PK_L_(0x02, 0x4F) ++#define REG_SC_BK02_4F_H _PK_H_(0x02, 0x4F) ++#define REG_SC_BK02_50_L _PK_L_(0x02, 0x50) ++#define REG_SC_BK02_50_H _PK_H_(0x02, 0x50) ++#define REG_SC_BK02_51_L _PK_L_(0x02, 0x51) ++#define REG_SC_BK02_51_H _PK_H_(0x02, 0x51) ++#define REG_SC_BK02_52_L _PK_L_(0x02, 0x52) ++#define REG_SC_BK02_52_H _PK_H_(0x02, 0x52) ++#define REG_SC_BK02_53_L _PK_L_(0x02, 0x53) ++#define REG_SC_BK02_53_H _PK_H_(0x02, 0x53) ++#define REG_SC_BK02_54_L _PK_L_(0x02, 0x54) ++#define REG_SC_BK02_54_H _PK_H_(0x02, 0x54) ++#define REG_SC_BK02_55_L _PK_L_(0x02, 0x55) ++#define REG_SC_BK02_55_H _PK_H_(0x02, 0x55) ++#define REG_SC_BK02_56_L _PK_L_(0x02, 0x56) ++#define REG_SC_BK02_56_H _PK_H_(0x02, 0x56) ++#define REG_SC_BK02_57_L _PK_L_(0x02, 0x57) ++#define REG_SC_BK02_57_H _PK_H_(0x02, 0x57) ++#define REG_SC_BK02_58_L _PK_L_(0x02, 0x58) ++#define REG_SC_BK02_58_H _PK_H_(0x02, 0x58) ++#define REG_SC_BK02_59_L _PK_L_(0x02, 0x59) ++#define REG_SC_BK02_59_H _PK_H_(0x02, 0x59) ++#define REG_SC_BK02_5A_L _PK_L_(0x02, 0x5A) ++#define REG_SC_BK02_5A_H _PK_H_(0x02, 0x5A) ++#define REG_SC_BK02_5B_L _PK_L_(0x02, 0x5B) ++#define REG_SC_BK02_5B_H _PK_H_(0x02, 0x5B) ++#define REG_SC_BK02_5C_L _PK_L_(0x02, 0x5C) ++#define REG_SC_BK02_5C_H _PK_H_(0x02, 0x5C) ++#define REG_SC_BK02_5D_L _PK_L_(0x02, 0x5D) ++#define REG_SC_BK02_5D_H _PK_H_(0x02, 0x5D) ++#define REG_SC_BK02_5E_L _PK_L_(0x02, 0x5E) ++#define REG_SC_BK02_5E_H _PK_H_(0x02, 0x5E) ++#define REG_SC_BK02_5F_L _PK_L_(0x02, 0x5F) ++#define REG_SC_BK02_5F_H _PK_H_(0x02, 0x5F) ++#define REG_SC_BK02_60_L _PK_L_(0x02, 0x60) ++#define REG_SC_BK02_60_H _PK_H_(0x02, 0x60) ++#define REG_SC_BK02_61_L _PK_L_(0x02, 0x61) ++#define REG_SC_BK02_61_H _PK_H_(0x02, 0x61) ++#define REG_SC_BK02_62_L _PK_L_(0x02, 0x62) ++#define REG_SC_BK02_62_H _PK_H_(0x02, 0x62) ++#define REG_SC_BK02_63_L _PK_L_(0x02, 0x63) ++#define REG_SC_BK02_63_H _PK_H_(0x02, 0x63) ++#define REG_SC_BK02_64_L _PK_L_(0x02, 0x64) ++#define REG_SC_BK02_64_H _PK_H_(0x02, 0x64) ++#define REG_SC_BK02_65_L _PK_L_(0x02, 0x65) ++#define REG_SC_BK02_65_H _PK_H_(0x02, 0x65) ++#define REG_SC_BK02_66_L _PK_L_(0x02, 0x66) ++#define REG_SC_BK02_66_H _PK_H_(0x02, 0x66) ++#define REG_SC_BK02_67_L _PK_L_(0x02, 0x67) ++#define REG_SC_BK02_67_H _PK_H_(0x02, 0x67) ++#define REG_SC_BK02_68_L _PK_L_(0x02, 0x68) ++#define REG_SC_BK02_68_H _PK_H_(0x02, 0x68) ++#define REG_SC_BK02_69_L _PK_L_(0x02, 0x69) ++#define REG_SC_BK02_69_H _PK_H_(0x02, 0x69) ++#define REG_SC_BK02_6A_L _PK_L_(0x02, 0x6A) ++#define REG_SC_BK02_6A_H _PK_H_(0x02, 0x6A) ++#define REG_SC_BK02_6B_L _PK_L_(0x02, 0x6B) ++#define REG_SC_BK02_6B_H _PK_H_(0x02, 0x6B) ++#define REG_SC_BK02_6C_L _PK_L_(0x02, 0x6C) ++#define REG_SC_BK02_6C_H _PK_H_(0x02, 0x6C) ++#define REG_SC_BK02_6D_L _PK_L_(0x02, 0x6D) ++#define REG_SC_BK02_6D_H _PK_H_(0x02, 0x6D) ++#define REG_SC_BK02_6E_L _PK_L_(0x02, 0x6E) ++#define REG_SC_BK02_6E_H _PK_H_(0x02, 0x6E) ++#define REG_SC_BK02_6F_L _PK_L_(0x02, 0x6F) ++#define REG_SC_BK02_6F_H _PK_H_(0x02, 0x6F) ++#define REG_SC_BK02_70_L _PK_L_(0x02, 0x70) ++#define REG_SC_BK02_70_H _PK_H_(0x02, 0x70) ++#define REG_SC_BK02_71_L _PK_L_(0x02, 0x71) ++#define REG_SC_BK02_71_H _PK_H_(0x02, 0x71) ++#define REG_SC_BK02_72_L _PK_L_(0x02, 0x72) ++#define REG_SC_BK02_72_H _PK_H_(0x02, 0x72) ++#define REG_SC_BK02_73_L _PK_L_(0x02, 0x73) ++#define REG_SC_BK02_73_H _PK_H_(0x02, 0x73) ++#define REG_SC_BK02_74_L _PK_L_(0x02, 0x74) ++#define REG_SC_BK02_74_H _PK_H_(0x02, 0x74) ++#define REG_SC_BK02_75_L _PK_L_(0x02, 0x75) ++#define REG_SC_BK02_75_H _PK_H_(0x02, 0x75) ++#define REG_SC_BK02_76_L _PK_L_(0x02, 0x76) ++#define REG_SC_BK02_76_H _PK_H_(0x02, 0x76) ++#define REG_SC_BK02_77_L _PK_L_(0x02, 0x77) ++#define REG_SC_BK02_77_H _PK_H_(0x02, 0x77) ++#define REG_SC_BK02_78_L _PK_L_(0x02, 0x78) ++#define REG_SC_BK02_78_H _PK_H_(0x02, 0x78) ++#define REG_SC_BK02_79_L _PK_L_(0x02, 0x79) ++#define REG_SC_BK02_79_H _PK_H_(0x02, 0x79) ++#define REG_SC_BK02_7A_L _PK_L_(0x02, 0x7A) ++#define REG_SC_BK02_7A_H _PK_H_(0x02, 0x7A) ++#define REG_SC_BK02_7B_L _PK_L_(0x02, 0x7B) ++#define REG_SC_BK02_7B_H _PK_H_(0x02, 0x7B) ++#define REG_SC_BK02_7C_L _PK_L_(0x02, 0x7C) ++#define REG_SC_BK02_7C_H _PK_H_(0x02, 0x7C) ++#define REG_SC_BK02_7D_L _PK_L_(0x02, 0x7D) ++#define REG_SC_BK02_7D_H _PK_H_(0x02, 0x7D) ++#define REG_SC_BK02_7E_L _PK_L_(0x02, 0x7E) ++#define REG_SC_BK02_7E_H _PK_H_(0x02, 0x7E) ++#define REG_SC_BK02_7F_L _PK_L_(0x02, 0x7F) ++#define REG_SC_BK02_7F_H _PK_H_(0x02, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK03_00_L _PK_L_(0x03, 0x00) ++#define REG_SC_BK03_00_H _PK_H_(0x03, 0x00) ++#define REG_SC_BK03_01_L _PK_L_(0x03, 0x01) ++#define REG_SC_BK03_01_H _PK_H_(0x03, 0x01) ++#define REG_SC_BK03_02_L _PK_L_(0x03, 0x02) ++#define REG_SC_BK03_02_H _PK_H_(0x03, 0x02) ++#define REG_SC_BK03_03_L _PK_L_(0x03, 0x03) ++#define REG_SC_BK03_03_H _PK_H_(0x03, 0x03) ++#define REG_SC_BK03_04_L _PK_L_(0x03, 0x04) ++#define REG_SC_BK03_04_H _PK_H_(0x03, 0x04) ++#define REG_SC_BK03_05_L _PK_L_(0x03, 0x05) ++#define REG_SC_BK03_05_H _PK_H_(0x03, 0x05) ++#define REG_SC_BK03_06_L _PK_L_(0x03, 0x06) ++#define REG_SC_BK03_06_H _PK_H_(0x03, 0x06) ++#define REG_SC_BK03_07_L _PK_L_(0x03, 0x07) ++#define REG_SC_BK03_07_H _PK_H_(0x03, 0x07) ++#define REG_SC_BK03_08_L _PK_L_(0x03, 0x08) ++#define REG_SC_BK03_08_H _PK_H_(0x03, 0x08) ++#define REG_SC_BK03_09_L _PK_L_(0x03, 0x09) ++#define REG_SC_BK03_09_H _PK_H_(0x03, 0x09) ++#define REG_SC_BK03_0A_L _PK_L_(0x03, 0x0A) ++#define REG_SC_BK03_0A_H _PK_H_(0x03, 0x0A) ++#define REG_SC_BK03_0B_L _PK_L_(0x03, 0x0B) ++#define REG_SC_BK03_0B_H _PK_H_(0x03, 0x0B) ++#define REG_SC_BK03_0C_L _PK_L_(0x03, 0x0C) ++#define REG_SC_BK03_0C_H _PK_H_(0x03, 0x0C) ++#define REG_SC_BK03_0D_L _PK_L_(0x03, 0x0D) ++#define REG_SC_BK03_0D_H _PK_H_(0x03, 0x0D) ++#define REG_SC_BK03_0E_L _PK_L_(0x03, 0x0E) ++#define REG_SC_BK03_0E_H _PK_H_(0x03, 0x0E) ++#define REG_SC_BK03_0F_L _PK_L_(0x03, 0x0F) ++#define REG_SC_BK03_0F_H _PK_H_(0x03, 0x0F) ++#define REG_SC_BK03_10_L _PK_L_(0x03, 0x10) ++#define REG_SC_BK03_10_H _PK_H_(0x03, 0x10) ++#define REG_SC_BK03_11_L _PK_L_(0x03, 0x11) ++#define REG_SC_BK03_11_H _PK_H_(0x03, 0x11) ++#define REG_SC_BK03_12_L _PK_L_(0x03, 0x12) ++#define REG_SC_BK03_12_H _PK_H_(0x03, 0x12) ++#define REG_SC_BK03_13_L _PK_L_(0x03, 0x13) ++#define REG_SC_BK03_13_H _PK_H_(0x03, 0x13) ++#define REG_SC_BK03_14_L _PK_L_(0x03, 0x14) ++#define REG_SC_BK03_14_H _PK_H_(0x03, 0x14) ++#define REG_SC_BK03_15_L _PK_L_(0x03, 0x15) ++#define REG_SC_BK03_15_H _PK_H_(0x03, 0x15) ++#define REG_SC_BK03_16_L _PK_L_(0x03, 0x16) ++#define REG_SC_BK03_16_H _PK_H_(0x03, 0x16) ++#define REG_SC_BK03_17_L _PK_L_(0x03, 0x17) ++#define REG_SC_BK03_17_H _PK_H_(0x03, 0x17) ++#define REG_SC_BK03_18_L _PK_L_(0x03, 0x18) ++#define REG_SC_BK03_18_H _PK_H_(0x03, 0x18) ++#define REG_SC_BK03_19_L _PK_L_(0x03, 0x19) ++#define REG_SC_BK03_19_H _PK_H_(0x03, 0x19) ++#define REG_SC_BK03_1A_L _PK_L_(0x03, 0x1A) ++#define REG_SC_BK03_1A_H _PK_H_(0x03, 0x1A) ++#define REG_SC_BK03_1B_L _PK_L_(0x03, 0x1B) ++#define REG_SC_BK03_1B_H _PK_H_(0x03, 0x1B) ++#define REG_SC_BK03_1C_L _PK_L_(0x03, 0x1C) ++#define REG_SC_BK03_1C_H _PK_H_(0x03, 0x1C) ++#define REG_SC_BK03_1D_L _PK_L_(0x03, 0x1D) ++#define REG_SC_BK03_1D_H _PK_H_(0x03, 0x1D) ++#define REG_SC_BK03_1E_L _PK_L_(0x03, 0x1E) ++#define REG_SC_BK03_1E_H _PK_H_(0x03, 0x1E) ++#define REG_SC_BK03_1F_L _PK_L_(0x03, 0x1F) ++#define REG_SC_BK03_1F_H _PK_H_(0x03, 0x1F) ++#define REG_SC_BK03_20_L _PK_L_(0x03, 0x20) ++#define REG_SC_BK03_20_H _PK_H_(0x03, 0x20) ++#define REG_SC_BK03_21_L _PK_L_(0x03, 0x21) ++#define REG_SC_BK03_21_H _PK_H_(0x03, 0x21) ++#define REG_SC_BK03_22_L _PK_L_(0x03, 0x22) ++#define REG_SC_BK03_22_H _PK_H_(0x03, 0x22) ++#define REG_SC_BK03_23_L _PK_L_(0x03, 0x23) ++#define REG_SC_BK03_23_H _PK_H_(0x03, 0x23) ++#define REG_SC_BK03_24_L _PK_L_(0x03, 0x24) ++#define REG_SC_BK03_24_H _PK_H_(0x03, 0x24) ++#define REG_SC_BK03_25_L _PK_L_(0x03, 0x25) ++#define REG_SC_BK03_25_H _PK_H_(0x03, 0x25) ++#define REG_SC_BK03_26_L _PK_L_(0x03, 0x26) ++#define REG_SC_BK03_26_H _PK_H_(0x03, 0x26) ++#define REG_SC_BK03_27_L _PK_L_(0x03, 0x27) ++#define REG_SC_BK03_27_H _PK_H_(0x03, 0x27) ++#define REG_SC_BK03_28_L _PK_L_(0x03, 0x28) ++#define REG_SC_BK03_28_H _PK_H_(0x03, 0x28) ++#define REG_SC_BK03_29_L _PK_L_(0x03, 0x29) ++#define REG_SC_BK03_29_H _PK_H_(0x03, 0x29) ++#define REG_SC_BK03_2A_L _PK_L_(0x03, 0x2A) ++#define REG_SC_BK03_2A_H _PK_H_(0x03, 0x2A) ++#define REG_SC_BK03_2B_L _PK_L_(0x03, 0x2B) ++#define REG_SC_BK03_2B_H _PK_H_(0x03, 0x2B) ++#define REG_SC_BK03_2C_L _PK_L_(0x03, 0x2C) ++#define REG_SC_BK03_2C_H _PK_H_(0x03, 0x2C) ++#define REG_SC_BK03_2D_L _PK_L_(0x03, 0x2D) ++#define REG_SC_BK03_2D_H _PK_H_(0x03, 0x2D) ++#define REG_SC_BK03_2E_L _PK_L_(0x03, 0x2E) ++#define REG_SC_BK03_2E_H _PK_H_(0x03, 0x2E) ++#define REG_SC_BK03_2F_L _PK_L_(0x03, 0x2F) ++#define REG_SC_BK03_2F_H _PK_H_(0x03, 0x2F) ++#define REG_SC_BK03_30_L _PK_L_(0x03, 0x30) ++#define REG_SC_BK03_30_H _PK_H_(0x03, 0x30) ++#define REG_SC_BK03_31_L _PK_L_(0x03, 0x31) ++#define REG_SC_BK03_31_H _PK_H_(0x03, 0x31) ++#define REG_SC_BK03_32_L _PK_L_(0x03, 0x32) ++#define REG_SC_BK03_32_H _PK_H_(0x03, 0x32) ++#define REG_SC_BK03_33_L _PK_L_(0x03, 0x33) ++#define REG_SC_BK03_33_H _PK_H_(0x03, 0x33) ++#define REG_SC_BK03_34_L _PK_L_(0x03, 0x34) ++#define REG_SC_BK03_34_H _PK_H_(0x03, 0x34) ++#define REG_SC_BK03_35_L _PK_L_(0x03, 0x35) ++#define REG_SC_BK03_35_H _PK_H_(0x03, 0x35) ++#define REG_SC_BK03_36_L _PK_L_(0x03, 0x36) ++#define REG_SC_BK03_36_H _PK_H_(0x03, 0x36) ++#define REG_SC_BK03_37_L _PK_L_(0x03, 0x37) ++#define REG_SC_BK03_37_H _PK_H_(0x03, 0x37) ++#define REG_SC_BK03_38_L _PK_L_(0x03, 0x38) ++#define REG_SC_BK03_38_H _PK_H_(0x03, 0x38) ++#define REG_SC_BK03_39_L _PK_L_(0x03, 0x39) ++#define REG_SC_BK03_39_H _PK_H_(0x03, 0x39) ++#define REG_SC_BK03_3A_L _PK_L_(0x03, 0x3A) ++#define REG_SC_BK03_3A_H _PK_H_(0x03, 0x3A) ++#define REG_SC_BK03_3B_L _PK_L_(0x03, 0x3B) ++#define REG_SC_BK03_3B_H _PK_H_(0x03, 0x3B) ++#define REG_SC_BK03_3C_L _PK_L_(0x03, 0x3C) ++#define REG_SC_BK03_3C_H _PK_H_(0x03, 0x3C) ++#define REG_SC_BK03_3D_L _PK_L_(0x03, 0x3D) ++#define REG_SC_BK03_3D_H _PK_H_(0x03, 0x3D) ++#define REG_SC_BK03_3E_L _PK_L_(0x03, 0x3E) ++#define REG_SC_BK03_3E_H _PK_H_(0x03, 0x3E) ++#define REG_SC_BK03_3F_L _PK_L_(0x03, 0x3F) ++#define REG_SC_BK03_3F_H _PK_H_(0x03, 0x3F) ++#define REG_SC_BK03_40_L _PK_L_(0x03, 0x40) ++#define REG_SC_BK03_40_H _PK_H_(0x03, 0x40) ++#define REG_SC_BK03_41_L _PK_L_(0x03, 0x41) ++#define REG_SC_BK03_41_H _PK_H_(0x03, 0x41) ++#define REG_SC_BK03_42_L _PK_L_(0x03, 0x42) ++#define REG_SC_BK03_42_H _PK_H_(0x03, 0x42) ++#define REG_SC_BK03_43_L _PK_L_(0x03, 0x43) ++#define REG_SC_BK03_43_H _PK_H_(0x03, 0x43) ++#define REG_SC_BK03_44_L _PK_L_(0x03, 0x44) ++#define REG_SC_BK03_44_H _PK_H_(0x03, 0x44) ++#define REG_SC_BK03_45_L _PK_L_(0x03, 0x45) ++#define REG_SC_BK03_45_H _PK_H_(0x03, 0x45) ++#define REG_SC_BK03_46_L _PK_L_(0x03, 0x46) ++#define REG_SC_BK03_46_H _PK_H_(0x03, 0x46) ++#define REG_SC_BK03_47_L _PK_L_(0x03, 0x47) ++#define REG_SC_BK03_47_H _PK_H_(0x03, 0x47) ++#define REG_SC_BK03_48_L _PK_L_(0x03, 0x48) ++#define REG_SC_BK03_48_H _PK_H_(0x03, 0x48) ++#define REG_SC_BK03_49_L _PK_L_(0x03, 0x49) ++#define REG_SC_BK03_49_H _PK_H_(0x03, 0x49) ++#define REG_SC_BK03_4A_L _PK_L_(0x03, 0x4A) ++#define REG_SC_BK03_4A_H _PK_H_(0x03, 0x4A) ++#define REG_SC_BK03_4B_L _PK_L_(0x03, 0x4B) ++#define REG_SC_BK03_4B_H _PK_H_(0x03, 0x4B) ++#define REG_SC_BK03_4C_L _PK_L_(0x03, 0x4C) ++#define REG_SC_BK03_4C_H _PK_H_(0x03, 0x4C) ++#define REG_SC_BK03_4D_L _PK_L_(0x03, 0x4D) ++#define REG_SC_BK03_4D_H _PK_H_(0x03, 0x4D) ++#define REG_SC_BK03_4E_L _PK_L_(0x03, 0x4E) ++#define REG_SC_BK03_4E_H _PK_H_(0x03, 0x4E) ++#define REG_SC_BK03_4F_L _PK_L_(0x03, 0x4F) ++#define REG_SC_BK03_4F_H _PK_H_(0x03, 0x4F) ++#define REG_SC_BK03_50_L _PK_L_(0x03, 0x50) ++#define REG_SC_BK03_50_H _PK_H_(0x03, 0x50) ++#define REG_SC_BK03_51_L _PK_L_(0x03, 0x51) ++#define REG_SC_BK03_51_H _PK_H_(0x03, 0x51) ++#define REG_SC_BK03_52_L _PK_L_(0x03, 0x52) ++#define REG_SC_BK03_52_H _PK_H_(0x03, 0x52) ++#define REG_SC_BK03_53_L _PK_L_(0x03, 0x53) ++#define REG_SC_BK03_53_H _PK_H_(0x03, 0x53) ++#define REG_SC_BK03_54_L _PK_L_(0x03, 0x54) ++#define REG_SC_BK03_54_H _PK_H_(0x03, 0x54) ++#define REG_SC_BK03_55_L _PK_L_(0x03, 0x55) ++#define REG_SC_BK03_55_H _PK_H_(0x03, 0x55) ++#define REG_SC_BK03_56_L _PK_L_(0x03, 0x56) ++#define REG_SC_BK03_56_H _PK_H_(0x03, 0x56) ++#define REG_SC_BK03_57_L _PK_L_(0x03, 0x57) ++#define REG_SC_BK03_57_H _PK_H_(0x03, 0x57) ++#define REG_SC_BK03_58_L _PK_L_(0x03, 0x58) ++#define REG_SC_BK03_58_H _PK_H_(0x03, 0x58) ++#define REG_SC_BK03_59_L _PK_L_(0x03, 0x59) ++#define REG_SC_BK03_59_H _PK_H_(0x03, 0x59) ++#define REG_SC_BK03_5A_L _PK_L_(0x03, 0x5A) ++#define REG_SC_BK03_5A_H _PK_H_(0x03, 0x5A) ++#define REG_SC_BK03_5B_L _PK_L_(0x03, 0x5B) ++#define REG_SC_BK03_5B_H _PK_H_(0x03, 0x5B) ++#define REG_SC_BK03_5C_L _PK_L_(0x03, 0x5C) ++#define REG_SC_BK03_5C_H _PK_H_(0x03, 0x5C) ++#define REG_SC_BK03_5D_L _PK_L_(0x03, 0x5D) ++#define REG_SC_BK03_5D_H _PK_H_(0x03, 0x5D) ++#define REG_SC_BK03_5E_L _PK_L_(0x03, 0x5E) ++#define REG_SC_BK03_5E_H _PK_H_(0x03, 0x5E) ++#define REG_SC_BK03_5F_L _PK_L_(0x03, 0x5F) ++#define REG_SC_BK03_5F_H _PK_H_(0x03, 0x5F) ++#define REG_SC_BK03_60_L _PK_L_(0x03, 0x60) ++#define REG_SC_BK03_60_H _PK_H_(0x03, 0x60) ++#define REG_SC_BK03_61_L _PK_L_(0x03, 0x61) ++#define REG_SC_BK03_61_H _PK_H_(0x03, 0x61) ++#define REG_SC_BK03_62_L _PK_L_(0x03, 0x62) ++#define REG_SC_BK03_62_H _PK_H_(0x03, 0x62) ++#define REG_SC_BK03_63_L _PK_L_(0x03, 0x63) ++#define REG_SC_BK03_63_H _PK_H_(0x03, 0x63) ++#define REG_SC_BK03_64_L _PK_L_(0x03, 0x64) ++#define REG_SC_BK03_64_H _PK_H_(0x03, 0x64) ++#define REG_SC_BK03_65_L _PK_L_(0x03, 0x65) ++#define REG_SC_BK03_65_H _PK_H_(0x03, 0x65) ++#define REG_SC_BK03_66_L _PK_L_(0x03, 0x66) ++#define REG_SC_BK03_66_H _PK_H_(0x03, 0x66) ++#define REG_SC_BK03_67_L _PK_L_(0x03, 0x67) ++#define REG_SC_BK03_67_H _PK_H_(0x03, 0x67) ++#define REG_SC_BK03_68_L _PK_L_(0x03, 0x68) ++#define REG_SC_BK03_68_H _PK_H_(0x03, 0x68) ++#define REG_SC_BK03_69_L _PK_L_(0x03, 0x69) ++#define REG_SC_BK03_69_H _PK_H_(0x03, 0x69) ++#define REG_SC_BK03_6A_L _PK_L_(0x03, 0x6A) ++#define REG_SC_BK03_6A_H _PK_H_(0x03, 0x6A) ++#define REG_SC_BK03_6B_L _PK_L_(0x03, 0x6B) ++#define REG_SC_BK03_6B_H _PK_H_(0x03, 0x6B) ++#define REG_SC_BK03_6C_L _PK_L_(0x03, 0x6C) ++#define REG_SC_BK03_6C_H _PK_H_(0x03, 0x6C) ++#define REG_SC_BK03_6D_L _PK_L_(0x03, 0x6D) ++#define REG_SC_BK03_6D_H _PK_H_(0x03, 0x6D) ++#define REG_SC_BK03_6E_L _PK_L_(0x03, 0x6E) ++#define REG_SC_BK03_6E_H _PK_H_(0x03, 0x6E) ++#define REG_SC_BK03_6F_L _PK_L_(0x03, 0x6F) ++#define REG_SC_BK03_6F_H _PK_H_(0x03, 0x6F) ++#define REG_SC_BK03_70_L _PK_L_(0x03, 0x70) ++#define REG_SC_BK03_70_H _PK_H_(0x03, 0x70) ++#define REG_SC_BK03_71_L _PK_L_(0x03, 0x71) ++#define REG_SC_BK03_71_H _PK_H_(0x03, 0x71) ++#define REG_SC_BK03_72_L _PK_L_(0x03, 0x72) ++#define REG_SC_BK03_72_H _PK_H_(0x03, 0x72) ++#define REG_SC_BK03_73_L _PK_L_(0x03, 0x73) ++#define REG_SC_BK03_73_H _PK_H_(0x03, 0x73) ++#define REG_SC_BK03_74_L _PK_L_(0x03, 0x74) ++#define REG_SC_BK03_74_H _PK_H_(0x03, 0x74) ++#define REG_SC_BK03_75_L _PK_L_(0x03, 0x75) ++#define REG_SC_BK03_75_H _PK_H_(0x03, 0x75) ++#define REG_SC_BK03_76_L _PK_L_(0x03, 0x76) ++#define REG_SC_BK03_76_H _PK_H_(0x03, 0x76) ++#define REG_SC_BK03_77_L _PK_L_(0x03, 0x77) ++#define REG_SC_BK03_77_H _PK_H_(0x03, 0x77) ++#define REG_SC_BK03_78_L _PK_L_(0x03, 0x78) ++#define REG_SC_BK03_78_H _PK_H_(0x03, 0x78) ++#define REG_SC_BK03_79_L _PK_L_(0x03, 0x79) ++#define REG_SC_BK03_79_H _PK_H_(0x03, 0x79) ++#define REG_SC_BK03_7A_L _PK_L_(0x03, 0x7A) ++#define REG_SC_BK03_7A_H _PK_H_(0x03, 0x7A) ++#define REG_SC_BK03_7B_L _PK_L_(0x03, 0x7B) ++#define REG_SC_BK03_7B_H _PK_H_(0x03, 0x7B) ++#define REG_SC_BK03_7C_L _PK_L_(0x03, 0x7C) ++#define REG_SC_BK03_7C_H _PK_H_(0x03, 0x7C) ++#define REG_SC_BK03_7D_L _PK_L_(0x03, 0x7D) ++#define REG_SC_BK03_7D_H _PK_H_(0x03, 0x7D) ++#define REG_SC_BK03_7E_L _PK_L_(0x03, 0x7E) ++#define REG_SC_BK03_7E_H _PK_H_(0x03, 0x7E) ++#define REG_SC_BK03_7F_L _PK_L_(0x03, 0x7F) ++#define REG_SC_BK03_7F_H _PK_H_(0x03, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK04_00_L _PK_L_(0x04, 0x00) ++#define REG_SC_BK04_00_H _PK_H_(0x04, 0x00) ++#define REG_SC_BK04_01_L _PK_L_(0x04, 0x01) ++#define REG_SC_BK04_01_H _PK_H_(0x04, 0x01) ++#define REG_SC_BK04_02_L _PK_L_(0x04, 0x02) ++#define REG_SC_BK04_02_H _PK_H_(0x04, 0x02) ++#define REG_SC_BK04_03_L _PK_L_(0x04, 0x03) ++#define REG_SC_BK04_03_H _PK_H_(0x04, 0x03) ++#define REG_SC_BK04_04_L _PK_L_(0x04, 0x04) ++#define REG_SC_BK04_04_H _PK_H_(0x04, 0x04) ++#define REG_SC_BK04_05_L _PK_L_(0x04, 0x05) ++#define REG_SC_BK04_05_H _PK_H_(0x04, 0x05) ++#define REG_SC_BK04_06_L _PK_L_(0x04, 0x06) ++#define REG_SC_BK04_06_H _PK_H_(0x04, 0x06) ++#define REG_SC_BK04_07_L _PK_L_(0x04, 0x07) ++#define REG_SC_BK04_07_H _PK_H_(0x04, 0x07) ++#define REG_SC_BK04_08_L _PK_L_(0x04, 0x08) ++#define REG_SC_BK04_08_H _PK_H_(0x04, 0x08) ++#define REG_SC_BK04_09_L _PK_L_(0x04, 0x09) ++#define REG_SC_BK04_09_H _PK_H_(0x04, 0x09) ++#define REG_SC_BK04_0A_L _PK_L_(0x04, 0x0A) ++#define REG_SC_BK04_0A_H _PK_H_(0x04, 0x0A) ++#define REG_SC_BK04_0B_L _PK_L_(0x04, 0x0B) ++#define REG_SC_BK04_0B_H _PK_H_(0x04, 0x0B) ++#define REG_SC_BK04_0C_L _PK_L_(0x04, 0x0C) ++#define REG_SC_BK04_0C_H _PK_H_(0x04, 0x0C) ++#define REG_SC_BK04_0D_L _PK_L_(0x04, 0x0D) ++#define REG_SC_BK04_0D_H _PK_H_(0x04, 0x0D) ++#define REG_SC_BK04_0E_L _PK_L_(0x04, 0x0E) ++#define REG_SC_BK04_0E_H _PK_H_(0x04, 0x0E) ++#define REG_SC_BK04_0F_L _PK_L_(0x04, 0x0F) ++#define REG_SC_BK04_0F_H _PK_H_(0x04, 0x0F) ++#define REG_SC_BK04_10_L _PK_L_(0x04, 0x10) ++#define REG_SC_BK04_10_H _PK_H_(0x04, 0x10) ++#define REG_SC_BK04_11_L _PK_L_(0x04, 0x11) ++#define REG_SC_BK04_11_H _PK_H_(0x04, 0x11) ++#define REG_SC_BK04_12_L _PK_L_(0x04, 0x12) ++#define REG_SC_BK04_12_H _PK_H_(0x04, 0x12) ++#define REG_SC_BK04_13_L _PK_L_(0x04, 0x13) ++#define REG_SC_BK04_13_H _PK_H_(0x04, 0x13) ++#define REG_SC_BK04_14_L _PK_L_(0x04, 0x14) ++#define REG_SC_BK04_14_H _PK_H_(0x04, 0x14) ++#define REG_SC_BK04_15_L _PK_L_(0x04, 0x15) ++#define REG_SC_BK04_15_H _PK_H_(0x04, 0x15) ++#define REG_SC_BK04_16_L _PK_L_(0x04, 0x16) ++#define REG_SC_BK04_16_H _PK_H_(0x04, 0x16) ++#define REG_SC_BK04_17_L _PK_L_(0x04, 0x17) ++#define REG_SC_BK04_17_H _PK_H_(0x04, 0x17) ++#define REG_SC_BK04_18_L _PK_L_(0x04, 0x18) ++#define REG_SC_BK04_18_H _PK_H_(0x04, 0x18) ++#define REG_SC_BK04_19_L _PK_L_(0x04, 0x19) ++#define REG_SC_BK04_19_H _PK_H_(0x04, 0x19) ++#define REG_SC_BK04_1A_L _PK_L_(0x04, 0x1A) ++#define REG_SC_BK04_1A_H _PK_H_(0x04, 0x1A) ++#define REG_SC_BK04_1B_L _PK_L_(0x04, 0x1B) ++#define REG_SC_BK04_1B_H _PK_H_(0x04, 0x1B) ++#define REG_SC_BK04_1C_L _PK_L_(0x04, 0x1C) ++#define REG_SC_BK04_1C_H _PK_H_(0x04, 0x1C) ++#define REG_SC_BK04_1D_L _PK_L_(0x04, 0x1D) ++#define REG_SC_BK04_1D_H _PK_H_(0x04, 0x1D) ++#define REG_SC_BK04_1E_L _PK_L_(0x04, 0x1E) ++#define REG_SC_BK04_1E_H _PK_H_(0x04, 0x1E) ++#define REG_SC_BK04_1F_L _PK_L_(0x04, 0x1F) ++#define REG_SC_BK04_1F_H _PK_H_(0x04, 0x1F) ++#define REG_SC_BK04_20_L _PK_L_(0x04, 0x20) ++#define REG_SC_BK04_20_H _PK_H_(0x04, 0x20) ++#define REG_SC_BK04_21_L _PK_L_(0x04, 0x21) ++#define REG_SC_BK04_21_H _PK_H_(0x04, 0x21) ++#define REG_SC_BK04_22_L _PK_L_(0x04, 0x22) ++#define REG_SC_BK04_22_H _PK_H_(0x04, 0x22) ++#define REG_SC_BK04_23_L _PK_L_(0x04, 0x23) ++#define REG_SC_BK04_23_H _PK_H_(0x04, 0x23) ++#define REG_SC_BK04_24_L _PK_L_(0x04, 0x24) ++#define REG_SC_BK04_24_H _PK_H_(0x04, 0x24) ++#define REG_SC_BK04_25_L _PK_L_(0x04, 0x25) ++#define REG_SC_BK04_25_H _PK_H_(0x04, 0x25) ++#define REG_SC_BK04_26_L _PK_L_(0x04, 0x26) ++#define REG_SC_BK04_26_H _PK_H_(0x04, 0x26) ++#define REG_SC_BK04_27_L _PK_L_(0x04, 0x27) ++#define REG_SC_BK04_27_H _PK_H_(0x04, 0x27) ++#define REG_SC_BK04_28_L _PK_L_(0x04, 0x28) ++#define REG_SC_BK04_28_H _PK_H_(0x04, 0x28) ++#define REG_SC_BK04_29_L _PK_L_(0x04, 0x29) ++#define REG_SC_BK04_29_H _PK_H_(0x04, 0x29) ++#define REG_SC_BK04_2A_L _PK_L_(0x04, 0x2A) ++#define REG_SC_BK04_2A_H _PK_H_(0x04, 0x2A) ++#define REG_SC_BK04_2B_L _PK_L_(0x04, 0x2B) ++#define REG_SC_BK04_2B_H _PK_H_(0x04, 0x2B) ++#define REG_SC_BK04_2C_L _PK_L_(0x04, 0x2C) ++#define REG_SC_BK04_2C_H _PK_H_(0x04, 0x2C) ++#define REG_SC_BK04_2D_L _PK_L_(0x04, 0x2D) ++#define REG_SC_BK04_2D_H _PK_H_(0x04, 0x2D) ++#define REG_SC_BK04_2E_L _PK_L_(0x04, 0x2E) ++#define REG_SC_BK04_2E_H _PK_H_(0x04, 0x2E) ++#define REG_SC_BK04_2F_L _PK_L_(0x04, 0x2F) ++#define REG_SC_BK04_2F_H _PK_H_(0x04, 0x2F) ++#define REG_SC_BK04_30_L _PK_L_(0x04, 0x30) ++#define REG_SC_BK04_30_H _PK_H_(0x04, 0x30) ++#define REG_SC_BK04_31_L _PK_L_(0x04, 0x31) ++#define REG_SC_BK04_31_H _PK_H_(0x04, 0x31) ++#define REG_SC_BK04_32_L _PK_L_(0x04, 0x32) ++#define REG_SC_BK04_32_H _PK_H_(0x04, 0x32) ++#define REG_SC_BK04_33_L _PK_L_(0x04, 0x33) ++#define REG_SC_BK04_33_H _PK_H_(0x04, 0x33) ++#define REG_SC_BK04_34_L _PK_L_(0x04, 0x34) ++#define REG_SC_BK04_34_H _PK_H_(0x04, 0x34) ++#define REG_SC_BK04_35_L _PK_L_(0x04, 0x35) ++#define REG_SC_BK04_35_H _PK_H_(0x04, 0x35) ++#define REG_SC_BK04_36_L _PK_L_(0x04, 0x36) ++#define REG_SC_BK04_36_H _PK_H_(0x04, 0x36) ++#define REG_SC_BK04_37_L _PK_L_(0x04, 0x37) ++#define REG_SC_BK04_37_H _PK_H_(0x04, 0x37) ++#define REG_SC_BK04_38_L _PK_L_(0x04, 0x38) ++#define REG_SC_BK04_38_H _PK_H_(0x04, 0x38) ++#define REG_SC_BK04_39_L _PK_L_(0x04, 0x39) ++#define REG_SC_BK04_39_H _PK_H_(0x04, 0x39) ++#define REG_SC_BK04_3A_L _PK_L_(0x04, 0x3A) ++#define REG_SC_BK04_3A_H _PK_H_(0x04, 0x3A) ++#define REG_SC_BK04_3B_L _PK_L_(0x04, 0x3B) ++#define REG_SC_BK04_3B_H _PK_H_(0x04, 0x3B) ++#define REG_SC_BK04_3C_L _PK_L_(0x04, 0x3C) ++#define REG_SC_BK04_3C_H _PK_H_(0x04, 0x3C) ++#define REG_SC_BK04_3D_L _PK_L_(0x04, 0x3D) ++#define REG_SC_BK04_3D_H _PK_H_(0x04, 0x3D) ++#define REG_SC_BK04_3E_L _PK_L_(0x04, 0x3E) ++#define REG_SC_BK04_3E_H _PK_H_(0x04, 0x3E) ++#define REG_SC_BK04_3F_L _PK_L_(0x04, 0x3F) ++#define REG_SC_BK04_3F_H _PK_H_(0x04, 0x3F) ++#define REG_SC_BK04_40_L _PK_L_(0x04, 0x40) ++#define REG_SC_BK04_40_H _PK_H_(0x04, 0x40) ++#define REG_SC_BK04_41_L _PK_L_(0x04, 0x41) ++#define REG_SC_BK04_41_H _PK_H_(0x04, 0x41) ++#define REG_SC_BK04_42_L _PK_L_(0x04, 0x42) ++#define REG_SC_BK04_42_H _PK_H_(0x04, 0x42) ++#define REG_SC_BK04_43_L _PK_L_(0x04, 0x43) ++#define REG_SC_BK04_43_H _PK_H_(0x04, 0x43) ++#define REG_SC_BK04_44_L _PK_L_(0x04, 0x44) ++#define REG_SC_BK04_44_H _PK_H_(0x04, 0x44) ++#define REG_SC_BK04_45_L _PK_L_(0x04, 0x45) ++#define REG_SC_BK04_45_H _PK_H_(0x04, 0x45) ++#define REG_SC_BK04_46_L _PK_L_(0x04, 0x46) ++#define REG_SC_BK04_46_H _PK_H_(0x04, 0x46) ++#define REG_SC_BK04_47_L _PK_L_(0x04, 0x47) ++#define REG_SC_BK04_47_H _PK_H_(0x04, 0x47) ++#define REG_SC_BK04_48_L _PK_L_(0x04, 0x48) ++#define REG_SC_BK04_48_H _PK_H_(0x04, 0x48) ++#define REG_SC_BK04_49_L _PK_L_(0x04, 0x49) ++#define REG_SC_BK04_49_H _PK_H_(0x04, 0x49) ++#define REG_SC_BK04_4A_L _PK_L_(0x04, 0x4A) ++#define REG_SC_BK04_4A_H _PK_H_(0x04, 0x4A) ++#define REG_SC_BK04_4B_L _PK_L_(0x04, 0x4B) ++#define REG_SC_BK04_4B_H _PK_H_(0x04, 0x4B) ++#define REG_SC_BK04_4C_L _PK_L_(0x04, 0x4C) ++#define REG_SC_BK04_4C_H _PK_H_(0x04, 0x4C) ++#define REG_SC_BK04_4D_L _PK_L_(0x04, 0x4D) ++#define REG_SC_BK04_4D_H _PK_H_(0x04, 0x4D) ++#define REG_SC_BK04_4E_L _PK_L_(0x04, 0x4E) ++#define REG_SC_BK04_4E_H _PK_H_(0x04, 0x4E) ++#define REG_SC_BK04_4F_L _PK_L_(0x04, 0x4F) ++#define REG_SC_BK04_4F_H _PK_H_(0x04, 0x4F) ++#define REG_SC_BK04_50_L _PK_L_(0x04, 0x50) ++#define REG_SC_BK04_50_H _PK_H_(0x04, 0x50) ++#define REG_SC_BK04_51_L _PK_L_(0x04, 0x51) ++#define REG_SC_BK04_51_H _PK_H_(0x04, 0x51) ++#define REG_SC_BK04_52_L _PK_L_(0x04, 0x52) ++#define REG_SC_BK04_52_H _PK_H_(0x04, 0x52) ++#define REG_SC_BK04_53_L _PK_L_(0x04, 0x53) ++#define REG_SC_BK04_53_H _PK_H_(0x04, 0x53) ++#define REG_SC_BK04_54_L _PK_L_(0x04, 0x54) ++#define REG_SC_BK04_54_H _PK_H_(0x04, 0x54) ++#define REG_SC_BK04_55_L _PK_L_(0x04, 0x55) ++#define REG_SC_BK04_55_H _PK_H_(0x04, 0x55) ++#define REG_SC_BK04_56_L _PK_L_(0x04, 0x56) ++#define REG_SC_BK04_56_H _PK_H_(0x04, 0x56) ++#define REG_SC_BK04_57_L _PK_L_(0x04, 0x57) ++#define REG_SC_BK04_57_H _PK_H_(0x04, 0x57) ++#define REG_SC_BK04_58_L _PK_L_(0x04, 0x58) ++#define REG_SC_BK04_58_H _PK_H_(0x04, 0x58) ++#define REG_SC_BK04_59_L _PK_L_(0x04, 0x59) ++#define REG_SC_BK04_59_H _PK_H_(0x04, 0x59) ++#define REG_SC_BK04_5A_L _PK_L_(0x04, 0x5A) ++#define REG_SC_BK04_5A_H _PK_H_(0x04, 0x5A) ++#define REG_SC_BK04_5B_L _PK_L_(0x04, 0x5B) ++#define REG_SC_BK04_5B_H _PK_H_(0x04, 0x5B) ++#define REG_SC_BK04_5C_L _PK_L_(0x04, 0x5C) ++#define REG_SC_BK04_5C_H _PK_H_(0x04, 0x5C) ++#define REG_SC_BK04_5D_L _PK_L_(0x04, 0x5D) ++#define REG_SC_BK04_5D_H _PK_H_(0x04, 0x5D) ++#define REG_SC_BK04_5E_L _PK_L_(0x04, 0x5E) ++#define REG_SC_BK04_5E_H _PK_H_(0x04, 0x5E) ++#define REG_SC_BK04_5F_L _PK_L_(0x04, 0x5F) ++#define REG_SC_BK04_5F_H _PK_H_(0x04, 0x5F) ++#define REG_SC_BK04_60_L _PK_L_(0x04, 0x60) ++#define REG_SC_BK04_60_H _PK_H_(0x04, 0x60) ++#define REG_SC_BK04_61_L _PK_L_(0x04, 0x61) ++#define REG_SC_BK04_61_H _PK_H_(0x04, 0x61) ++#define REG_SC_BK04_62_L _PK_L_(0x04, 0x62) ++#define REG_SC_BK04_62_H _PK_H_(0x04, 0x62) ++#define REG_SC_BK04_63_L _PK_L_(0x04, 0x63) ++#define REG_SC_BK04_63_H _PK_H_(0x04, 0x63) ++#define REG_SC_BK04_64_L _PK_L_(0x04, 0x64) ++#define REG_SC_BK04_64_H _PK_H_(0x04, 0x64) ++#define REG_SC_BK04_65_L _PK_L_(0x04, 0x65) ++#define REG_SC_BK04_65_H _PK_H_(0x04, 0x65) ++#define REG_SC_BK04_66_L _PK_L_(0x04, 0x66) ++#define REG_SC_BK04_66_H _PK_H_(0x04, 0x66) ++#define REG_SC_BK04_67_L _PK_L_(0x04, 0x67) ++#define REG_SC_BK04_67_H _PK_H_(0x04, 0x67) ++#define REG_SC_BK04_68_L _PK_L_(0x04, 0x68) ++#define REG_SC_BK04_68_H _PK_H_(0x04, 0x68) ++#define REG_SC_BK04_69_L _PK_L_(0x04, 0x69) ++#define REG_SC_BK04_69_H _PK_H_(0x04, 0x69) ++#define REG_SC_BK04_6A_L _PK_L_(0x04, 0x6A) ++#define REG_SC_BK04_6A_H _PK_H_(0x04, 0x6A) ++#define REG_SC_BK04_6B_L _PK_L_(0x04, 0x6B) ++#define REG_SC_BK04_6B_H _PK_H_(0x04, 0x6B) ++#define REG_SC_BK04_6C_L _PK_L_(0x04, 0x6C) ++#define REG_SC_BK04_6C_H _PK_H_(0x04, 0x6C) ++#define REG_SC_BK04_6D_L _PK_L_(0x04, 0x6D) ++#define REG_SC_BK04_6D_H _PK_H_(0x04, 0x6D) ++#define REG_SC_BK04_6E_L _PK_L_(0x04, 0x6E) ++#define REG_SC_BK04_6E_H _PK_H_(0x04, 0x6E) ++#define REG_SC_BK04_6F_L _PK_L_(0x04, 0x6F) ++#define REG_SC_BK04_6F_H _PK_H_(0x04, 0x6F) ++#define REG_SC_BK04_70_L _PK_L_(0x04, 0x70) ++#define REG_SC_BK04_70_H _PK_H_(0x04, 0x70) ++#define REG_SC_BK04_71_L _PK_L_(0x04, 0x71) ++#define REG_SC_BK04_71_H _PK_H_(0x04, 0x71) ++#define REG_SC_BK04_72_L _PK_L_(0x04, 0x72) ++#define REG_SC_BK04_72_H _PK_H_(0x04, 0x72) ++#define REG_SC_BK04_73_L _PK_L_(0x04, 0x73) ++#define REG_SC_BK04_73_H _PK_H_(0x04, 0x73) ++#define REG_SC_BK04_74_L _PK_L_(0x04, 0x74) ++#define REG_SC_BK04_74_H _PK_H_(0x04, 0x74) ++#define REG_SC_BK04_75_L _PK_L_(0x04, 0x75) ++#define REG_SC_BK04_75_H _PK_H_(0x04, 0x75) ++#define REG_SC_BK04_76_L _PK_L_(0x04, 0x76) ++#define REG_SC_BK04_76_H _PK_H_(0x04, 0x76) ++#define REG_SC_BK04_77_L _PK_L_(0x04, 0x77) ++#define REG_SC_BK04_77_H _PK_H_(0x04, 0x77) ++#define REG_SC_BK04_78_L _PK_L_(0x04, 0x78) ++#define REG_SC_BK04_78_H _PK_H_(0x04, 0x78) ++#define REG_SC_BK04_79_L _PK_L_(0x04, 0x79) ++#define REG_SC_BK04_79_H _PK_H_(0x04, 0x79) ++#define REG_SC_BK04_7A_L _PK_L_(0x04, 0x7A) ++#define REG_SC_BK04_7A_H _PK_H_(0x04, 0x7A) ++#define REG_SC_BK04_7B_L _PK_L_(0x04, 0x7B) ++#define REG_SC_BK04_7B_H _PK_H_(0x04, 0x7B) ++#define REG_SC_BK04_7C_L _PK_L_(0x04, 0x7C) ++#define REG_SC_BK04_7C_H _PK_H_(0x04, 0x7C) ++#define REG_SC_BK04_7D_L _PK_L_(0x04, 0x7D) ++#define REG_SC_BK04_7D_H _PK_H_(0x04, 0x7D) ++#define REG_SC_BK04_7E_L _PK_L_(0x04, 0x7E) ++#define REG_SC_BK04_7E_H _PK_H_(0x04, 0x7E) ++#define REG_SC_BK04_7F_L _PK_L_(0x04, 0x7F) ++#define REG_SC_BK04_7F_H _PK_H_(0x04, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK05_00_L _PK_L_(0x05, 0x00) ++#define REG_SC_BK05_00_H _PK_H_(0x05, 0x00) ++#define REG_SC_BK05_01_L _PK_L_(0x05, 0x01) ++#define REG_SC_BK05_01_H _PK_H_(0x05, 0x01) ++#define REG_SC_BK05_02_L _PK_L_(0x05, 0x02) ++#define REG_SC_BK05_02_H _PK_H_(0x05, 0x02) ++#define REG_SC_BK05_03_L _PK_L_(0x05, 0x03) ++#define REG_SC_BK05_03_H _PK_H_(0x05, 0x03) ++#define REG_SC_BK05_04_L _PK_L_(0x05, 0x04) ++#define REG_SC_BK05_04_H _PK_H_(0x05, 0x04) ++#define REG_SC_BK05_05_L _PK_L_(0x05, 0x05) ++#define REG_SC_BK05_05_H _PK_H_(0x05, 0x05) ++#define REG_SC_BK05_06_L _PK_L_(0x05, 0x06) ++#define REG_SC_BK05_06_H _PK_H_(0x05, 0x06) ++#define REG_SC_BK05_07_L _PK_L_(0x05, 0x07) ++#define REG_SC_BK05_07_H _PK_H_(0x05, 0x07) ++#define REG_SC_BK05_08_L _PK_L_(0x05, 0x08) ++#define REG_SC_BK05_08_H _PK_H_(0x05, 0x08) ++#define REG_SC_BK05_09_L _PK_L_(0x05, 0x09) ++#define REG_SC_BK05_09_H _PK_H_(0x05, 0x09) ++#define REG_SC_BK05_0A_L _PK_L_(0x05, 0x0A) ++#define REG_SC_BK05_0A_H _PK_H_(0x05, 0x0A) ++#define REG_SC_BK05_0B_L _PK_L_(0x05, 0x0B) ++#define REG_SC_BK05_0B_H _PK_H_(0x05, 0x0B) ++#define REG_SC_BK05_0C_L _PK_L_(0x05, 0x0C) ++#define REG_SC_BK05_0C_H _PK_H_(0x05, 0x0C) ++#define REG_SC_BK05_0D_L _PK_L_(0x05, 0x0D) ++#define REG_SC_BK05_0D_H _PK_H_(0x05, 0x0D) ++#define REG_SC_BK05_0E_L _PK_L_(0x05, 0x0E) ++#define REG_SC_BK05_0E_H _PK_H_(0x05, 0x0E) ++#define REG_SC_BK05_0F_L _PK_L_(0x05, 0x0F) ++#define REG_SC_BK05_0F_H _PK_H_(0x05, 0x0F) ++#define REG_SC_BK05_10_L _PK_L_(0x05, 0x10) ++#define REG_SC_BK05_10_H _PK_H_(0x05, 0x10) ++#define REG_SC_BK05_11_L _PK_L_(0x05, 0x11) ++#define REG_SC_BK05_11_H _PK_H_(0x05, 0x11) ++#define REG_SC_BK05_12_L _PK_L_(0x05, 0x12) ++#define REG_SC_BK05_12_H _PK_H_(0x05, 0x12) ++#define REG_SC_BK05_13_L _PK_L_(0x05, 0x13) ++#define REG_SC_BK05_13_H _PK_H_(0x05, 0x13) ++#define REG_SC_BK05_14_L _PK_L_(0x05, 0x14) ++#define REG_SC_BK05_14_H _PK_H_(0x05, 0x14) ++#define REG_SC_BK05_15_L _PK_L_(0x05, 0x15) ++#define REG_SC_BK05_15_H _PK_H_(0x05, 0x15) ++#define REG_SC_BK05_16_L _PK_L_(0x05, 0x16) ++#define REG_SC_BK05_16_H _PK_H_(0x05, 0x16) ++#define REG_SC_BK05_17_L _PK_L_(0x05, 0x17) ++#define REG_SC_BK05_17_H _PK_H_(0x05, 0x17) ++#define REG_SC_BK05_18_L _PK_L_(0x05, 0x18) ++#define REG_SC_BK05_18_H _PK_H_(0x05, 0x18) ++#define REG_SC_BK05_19_L _PK_L_(0x05, 0x19) ++#define REG_SC_BK05_19_H _PK_H_(0x05, 0x19) ++#define REG_SC_BK05_1A_L _PK_L_(0x05, 0x1A) ++#define REG_SC_BK05_1A_H _PK_H_(0x05, 0x1A) ++#define REG_SC_BK05_1B_L _PK_L_(0x05, 0x1B) ++#define REG_SC_BK05_1B_H _PK_H_(0x05, 0x1B) ++#define REG_SC_BK05_1C_L _PK_L_(0x05, 0x1C) ++#define REG_SC_BK05_1C_H _PK_H_(0x05, 0x1C) ++#define REG_SC_BK05_1D_L _PK_L_(0x05, 0x1D) ++#define REG_SC_BK05_1D_H _PK_H_(0x05, 0x1D) ++#define REG_SC_BK05_1E_L _PK_L_(0x05, 0x1E) ++#define REG_SC_BK05_1E_H _PK_H_(0x05, 0x1E) ++#define REG_SC_BK05_1F_L _PK_L_(0x05, 0x1F) ++#define REG_SC_BK05_1F_H _PK_H_(0x05, 0x1F) ++#define REG_SC_BK05_20_L _PK_L_(0x05, 0x20) ++#define REG_SC_BK05_20_H _PK_H_(0x05, 0x20) ++#define REG_SC_BK05_21_L _PK_L_(0x05, 0x21) ++#define REG_SC_BK05_21_H _PK_H_(0x05, 0x21) ++#define REG_SC_BK05_22_L _PK_L_(0x05, 0x22) ++#define REG_SC_BK05_22_H _PK_H_(0x05, 0x22) ++#define REG_SC_BK05_23_L _PK_L_(0x05, 0x23) ++#define REG_SC_BK05_23_H _PK_H_(0x05, 0x23) ++#define REG_SC_BK05_24_L _PK_L_(0x05, 0x24) ++#define REG_SC_BK05_24_H _PK_H_(0x05, 0x24) ++#define REG_SC_BK05_25_L _PK_L_(0x05, 0x25) ++#define REG_SC_BK05_25_H _PK_H_(0x05, 0x25) ++#define REG_SC_BK05_26_L _PK_L_(0x05, 0x26) ++#define REG_SC_BK05_26_H _PK_H_(0x05, 0x26) ++#define REG_SC_BK05_27_L _PK_L_(0x05, 0x27) ++#define REG_SC_BK05_27_H _PK_H_(0x05, 0x27) ++#define REG_SC_BK05_28_L _PK_L_(0x05, 0x28) ++#define REG_SC_BK05_28_H _PK_H_(0x05, 0x28) ++#define REG_SC_BK05_29_L _PK_L_(0x05, 0x29) ++#define REG_SC_BK05_29_H _PK_H_(0x05, 0x29) ++#define REG_SC_BK05_2A_L _PK_L_(0x05, 0x2A) ++#define REG_SC_BK05_2A_H _PK_H_(0x05, 0x2A) ++#define REG_SC_BK05_2B_L _PK_L_(0x05, 0x2B) ++#define REG_SC_BK05_2B_H _PK_H_(0x05, 0x2B) ++#define REG_SC_BK05_2C_L _PK_L_(0x05, 0x2C) ++#define REG_SC_BK05_2C_H _PK_H_(0x05, 0x2C) ++#define REG_SC_BK05_2D_L _PK_L_(0x05, 0x2D) ++#define REG_SC_BK05_2D_H _PK_H_(0x05, 0x2D) ++#define REG_SC_BK05_2E_L _PK_L_(0x05, 0x2E) ++#define REG_SC_BK05_2E_H _PK_H_(0x05, 0x2E) ++#define REG_SC_BK05_2F_L _PK_L_(0x05, 0x2F) ++#define REG_SC_BK05_2F_H _PK_H_(0x05, 0x2F) ++#define REG_SC_BK05_30_L _PK_L_(0x05, 0x30) ++#define REG_SC_BK05_30_H _PK_H_(0x05, 0x30) ++#define REG_SC_BK05_31_L _PK_L_(0x05, 0x31) ++#define REG_SC_BK05_31_H _PK_H_(0x05, 0x31) ++#define REG_SC_BK05_32_L _PK_L_(0x05, 0x32) ++#define REG_SC_BK05_32_H _PK_H_(0x05, 0x32) ++#define REG_SC_BK05_33_L _PK_L_(0x05, 0x33) ++#define REG_SC_BK05_33_H _PK_H_(0x05, 0x33) ++#define REG_SC_BK05_34_L _PK_L_(0x05, 0x34) ++#define REG_SC_BK05_34_H _PK_H_(0x05, 0x34) ++#define REG_SC_BK05_35_L _PK_L_(0x05, 0x35) ++#define REG_SC_BK05_35_H _PK_H_(0x05, 0x35) ++#define REG_SC_BK05_36_L _PK_L_(0x05, 0x36) ++#define REG_SC_BK05_36_H _PK_H_(0x05, 0x36) ++#define REG_SC_BK05_37_L _PK_L_(0x05, 0x37) ++#define REG_SC_BK05_37_H _PK_H_(0x05, 0x37) ++#define REG_SC_BK05_38_L _PK_L_(0x05, 0x38) ++#define REG_SC_BK05_38_H _PK_H_(0x05, 0x38) ++#define REG_SC_BK05_39_L _PK_L_(0x05, 0x39) ++#define REG_SC_BK05_39_H _PK_H_(0x05, 0x39) ++#define REG_SC_BK05_3A_L _PK_L_(0x05, 0x3A) ++#define REG_SC_BK05_3A_H _PK_H_(0x05, 0x3A) ++#define REG_SC_BK05_3B_L _PK_L_(0x05, 0x3B) ++#define REG_SC_BK05_3B_H _PK_H_(0x05, 0x3B) ++#define REG_SC_BK05_3C_L _PK_L_(0x05, 0x3C) ++#define REG_SC_BK05_3C_H _PK_H_(0x05, 0x3C) ++#define REG_SC_BK05_3D_L _PK_L_(0x05, 0x3D) ++#define REG_SC_BK05_3D_H _PK_H_(0x05, 0x3D) ++#define REG_SC_BK05_3E_L _PK_L_(0x05, 0x3E) ++#define REG_SC_BK05_3E_H _PK_H_(0x05, 0x3E) ++#define REG_SC_BK05_3F_L _PK_L_(0x05, 0x3F) ++#define REG_SC_BK05_3F_H _PK_H_(0x05, 0x3F) ++#define REG_SC_BK05_40_L _PK_L_(0x05, 0x40) ++#define REG_SC_BK05_40_H _PK_H_(0x05, 0x40) ++#define REG_SC_BK05_41_L _PK_L_(0x05, 0x41) ++#define REG_SC_BK05_41_H _PK_H_(0x05, 0x41) ++#define REG_SC_BK05_42_L _PK_L_(0x05, 0x42) ++#define REG_SC_BK05_42_H _PK_H_(0x05, 0x42) ++#define REG_SC_BK05_43_L _PK_L_(0x05, 0x43) ++#define REG_SC_BK05_43_H _PK_H_(0x05, 0x43) ++#define REG_SC_BK05_44_L _PK_L_(0x05, 0x44) ++#define REG_SC_BK05_44_H _PK_H_(0x05, 0x44) ++#define REG_SC_BK05_45_L _PK_L_(0x05, 0x45) ++#define REG_SC_BK05_45_H _PK_H_(0x05, 0x45) ++#define REG_SC_BK05_46_L _PK_L_(0x05, 0x46) ++#define REG_SC_BK05_46_H _PK_H_(0x05, 0x46) ++#define REG_SC_BK05_47_L _PK_L_(0x05, 0x47) ++#define REG_SC_BK05_47_H _PK_H_(0x05, 0x47) ++#define REG_SC_BK05_48_L _PK_L_(0x05, 0x48) ++#define REG_SC_BK05_48_H _PK_H_(0x05, 0x48) ++#define REG_SC_BK05_49_L _PK_L_(0x05, 0x49) ++#define REG_SC_BK05_49_H _PK_H_(0x05, 0x49) ++#define REG_SC_BK05_4A_L _PK_L_(0x05, 0x4A) ++#define REG_SC_BK05_4A_H _PK_H_(0x05, 0x4A) ++#define REG_SC_BK05_4B_L _PK_L_(0x05, 0x4B) ++#define REG_SC_BK05_4B_H _PK_H_(0x05, 0x4B) ++#define REG_SC_BK05_4C_L _PK_L_(0x05, 0x4C) ++#define REG_SC_BK05_4C_H _PK_H_(0x05, 0x4C) ++#define REG_SC_BK05_4D_L _PK_L_(0x05, 0x4D) ++#define REG_SC_BK05_4D_H _PK_H_(0x05, 0x4D) ++#define REG_SC_BK05_4E_L _PK_L_(0x05, 0x4E) ++#define REG_SC_BK05_4E_H _PK_H_(0x05, 0x4E) ++#define REG_SC_BK05_4F_L _PK_L_(0x05, 0x4F) ++#define REG_SC_BK05_4F_H _PK_H_(0x05, 0x4F) ++#define REG_SC_BK05_50_L _PK_L_(0x05, 0x50) ++#define REG_SC_BK05_50_H _PK_H_(0x05, 0x50) ++#define REG_SC_BK05_51_L _PK_L_(0x05, 0x51) ++#define REG_SC_BK05_51_H _PK_H_(0x05, 0x51) ++#define REG_SC_BK05_52_L _PK_L_(0x05, 0x52) ++#define REG_SC_BK05_52_H _PK_H_(0x05, 0x52) ++#define REG_SC_BK05_53_L _PK_L_(0x05, 0x53) ++#define REG_SC_BK05_53_H _PK_H_(0x05, 0x53) ++#define REG_SC_BK05_54_L _PK_L_(0x05, 0x54) ++#define REG_SC_BK05_54_H _PK_H_(0x05, 0x54) ++#define REG_SC_BK05_55_L _PK_L_(0x05, 0x55) ++#define REG_SC_BK05_55_H _PK_H_(0x05, 0x55) ++#define REG_SC_BK05_56_L _PK_L_(0x05, 0x56) ++#define REG_SC_BK05_56_H _PK_H_(0x05, 0x56) ++#define REG_SC_BK05_57_L _PK_L_(0x05, 0x57) ++#define REG_SC_BK05_57_H _PK_H_(0x05, 0x57) ++#define REG_SC_BK05_58_L _PK_L_(0x05, 0x58) ++#define REG_SC_BK05_58_H _PK_H_(0x05, 0x58) ++#define REG_SC_BK05_59_L _PK_L_(0x05, 0x59) ++#define REG_SC_BK05_59_H _PK_H_(0x05, 0x59) ++#define REG_SC_BK05_5A_L _PK_L_(0x05, 0x5A) ++#define REG_SC_BK05_5A_H _PK_H_(0x05, 0x5A) ++#define REG_SC_BK05_5B_L _PK_L_(0x05, 0x5B) ++#define REG_SC_BK05_5B_H _PK_H_(0x05, 0x5B) ++#define REG_SC_BK05_5C_L _PK_L_(0x05, 0x5C) ++#define REG_SC_BK05_5C_H _PK_H_(0x05, 0x5C) ++#define REG_SC_BK05_5D_L _PK_L_(0x05, 0x5D) ++#define REG_SC_BK05_5D_H _PK_H_(0x05, 0x5D) ++#define REG_SC_BK05_5E_L _PK_L_(0x05, 0x5E) ++#define REG_SC_BK05_5E_H _PK_H_(0x05, 0x5E) ++#define REG_SC_BK05_5F_L _PK_L_(0x05, 0x5F) ++#define REG_SC_BK05_5F_H _PK_H_(0x05, 0x5F) ++#define REG_SC_BK05_60_L _PK_L_(0x05, 0x60) ++#define REG_SC_BK05_60_H _PK_H_(0x05, 0x60) ++#define REG_SC_BK05_61_L _PK_L_(0x05, 0x61) ++#define REG_SC_BK05_61_H _PK_H_(0x05, 0x61) ++#define REG_SC_BK05_62_L _PK_L_(0x05, 0x62) ++#define REG_SC_BK05_62_H _PK_H_(0x05, 0x62) ++#define REG_SC_BK05_63_L _PK_L_(0x05, 0x63) ++#define REG_SC_BK05_63_H _PK_H_(0x05, 0x63) ++#define REG_SC_BK05_64_L _PK_L_(0x05, 0x64) ++#define REG_SC_BK05_64_H _PK_H_(0x05, 0x64) ++#define REG_SC_BK05_65_L _PK_L_(0x05, 0x65) ++#define REG_SC_BK05_65_H _PK_H_(0x05, 0x65) ++#define REG_SC_BK05_66_L _PK_L_(0x05, 0x66) ++#define REG_SC_BK05_66_H _PK_H_(0x05, 0x66) ++#define REG_SC_BK05_67_L _PK_L_(0x05, 0x67) ++#define REG_SC_BK05_67_H _PK_H_(0x05, 0x67) ++#define REG_SC_BK05_68_L _PK_L_(0x05, 0x68) ++#define REG_SC_BK05_68_H _PK_H_(0x05, 0x68) ++#define REG_SC_BK05_69_L _PK_L_(0x05, 0x69) ++#define REG_SC_BK05_69_H _PK_H_(0x05, 0x69) ++#define REG_SC_BK05_6A_L _PK_L_(0x05, 0x6A) ++#define REG_SC_BK05_6A_H _PK_H_(0x05, 0x6A) ++#define REG_SC_BK05_6B_L _PK_L_(0x05, 0x6B) ++#define REG_SC_BK05_6B_H _PK_H_(0x05, 0x6B) ++#define REG_SC_BK05_6C_L _PK_L_(0x05, 0x6C) ++#define REG_SC_BK05_6C_H _PK_H_(0x05, 0x6C) ++#define REG_SC_BK05_6D_L _PK_L_(0x05, 0x6D) ++#define REG_SC_BK05_6D_H _PK_H_(0x05, 0x6D) ++#define REG_SC_BK05_6E_L _PK_L_(0x05, 0x6E) ++#define REG_SC_BK05_6E_H _PK_H_(0x05, 0x6E) ++#define REG_SC_BK05_6F_L _PK_L_(0x05, 0x6F) ++#define REG_SC_BK05_6F_H _PK_H_(0x05, 0x6F) ++#define REG_SC_BK05_70_L _PK_L_(0x05, 0x70) ++#define REG_SC_BK05_70_H _PK_H_(0x05, 0x70) ++#define REG_SC_BK05_71_L _PK_L_(0x05, 0x71) ++#define REG_SC_BK05_71_H _PK_H_(0x05, 0x71) ++#define REG_SC_BK05_72_L _PK_L_(0x05, 0x72) ++#define REG_SC_BK05_72_H _PK_H_(0x05, 0x72) ++#define REG_SC_BK05_73_L _PK_L_(0x05, 0x73) ++#define REG_SC_BK05_73_H _PK_H_(0x05, 0x73) ++#define REG_SC_BK05_74_L _PK_L_(0x05, 0x74) ++#define REG_SC_BK05_74_H _PK_H_(0x05, 0x74) ++#define REG_SC_BK05_75_L _PK_L_(0x05, 0x75) ++#define REG_SC_BK05_75_H _PK_H_(0x05, 0x75) ++#define REG_SC_BK05_76_L _PK_L_(0x05, 0x76) ++#define REG_SC_BK05_76_H _PK_H_(0x05, 0x76) ++#define REG_SC_BK05_77_L _PK_L_(0x05, 0x77) ++#define REG_SC_BK05_77_H _PK_H_(0x05, 0x77) ++#define REG_SC_BK05_78_L _PK_L_(0x05, 0x78) ++#define REG_SC_BK05_78_H _PK_H_(0x05, 0x78) ++#define REG_SC_BK05_79_L _PK_L_(0x05, 0x79) ++#define REG_SC_BK05_79_H _PK_H_(0x05, 0x79) ++#define REG_SC_BK05_7A_L _PK_L_(0x05, 0x7A) ++#define REG_SC_BK05_7A_H _PK_H_(0x05, 0x7A) ++#define REG_SC_BK05_7B_L _PK_L_(0x05, 0x7B) ++#define REG_SC_BK05_7B_H _PK_H_(0x05, 0x7B) ++#define REG_SC_BK05_7C_L _PK_L_(0x05, 0x7C) ++#define REG_SC_BK05_7C_H _PK_H_(0x05, 0x7C) ++#define REG_SC_BK05_7D_L _PK_L_(0x05, 0x7D) ++#define REG_SC_BK05_7D_H _PK_H_(0x05, 0x7D) ++#define REG_SC_BK05_7E_L _PK_L_(0x05, 0x7E) ++#define REG_SC_BK05_7E_H _PK_H_(0x05, 0x7E) ++#define REG_SC_BK05_7F_L _PK_L_(0x05, 0x7F) ++#define REG_SC_BK05_7F_H _PK_H_(0x05, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK06_00_L _PK_L_(0x06, 0x00) ++#define REG_SC_BK06_00_H _PK_H_(0x06, 0x00) ++#define REG_SC_BK06_01_L _PK_L_(0x06, 0x01) ++#define REG_SC_BK06_01_H _PK_H_(0x06, 0x01) ++#define REG_SC_BK06_02_L _PK_L_(0x06, 0x02) ++#define REG_SC_BK06_02_H _PK_H_(0x06, 0x02) ++#define REG_SC_BK06_03_L _PK_L_(0x06, 0x03) ++#define REG_SC_BK06_03_H _PK_H_(0x06, 0x03) ++#define REG_SC_BK06_04_L _PK_L_(0x06, 0x04) ++#define REG_SC_BK06_04_H _PK_H_(0x06, 0x04) ++#define REG_SC_BK06_05_L _PK_L_(0x06, 0x05) ++#define REG_SC_BK06_05_H _PK_H_(0x06, 0x05) ++#define REG_SC_BK06_06_L _PK_L_(0x06, 0x06) ++#define REG_SC_BK06_06_H _PK_H_(0x06, 0x06) ++#define REG_SC_BK06_07_L _PK_L_(0x06, 0x07) ++#define REG_SC_BK06_07_H _PK_H_(0x06, 0x07) ++#define REG_SC_BK06_08_L _PK_L_(0x06, 0x08) ++#define REG_SC_BK06_08_H _PK_H_(0x06, 0x08) ++#define REG_SC_BK06_09_L _PK_L_(0x06, 0x09) ++#define REG_SC_BK06_09_H _PK_H_(0x06, 0x09) ++#define REG_SC_BK06_0A_L _PK_L_(0x06, 0x0A) ++#define REG_SC_BK06_0A_H _PK_H_(0x06, 0x0A) ++#define REG_SC_BK06_0B_L _PK_L_(0x06, 0x0B) ++#define REG_SC_BK06_0B_H _PK_H_(0x06, 0x0B) ++#define REG_SC_BK06_0C_L _PK_L_(0x06, 0x0C) ++#define REG_SC_BK06_0C_H _PK_H_(0x06, 0x0C) ++#define REG_SC_BK06_0D_L _PK_L_(0x06, 0x0D) ++#define REG_SC_BK06_0D_H _PK_H_(0x06, 0x0D) ++#define REG_SC_BK06_0E_L _PK_L_(0x06, 0x0E) ++#define REG_SC_BK06_0E_H _PK_H_(0x06, 0x0E) ++#define REG_SC_BK06_0F_L _PK_L_(0x06, 0x0F) ++#define REG_SC_BK06_0F_H _PK_H_(0x06, 0x0F) ++#define REG_SC_BK06_10_L _PK_L_(0x06, 0x10) ++#define REG_SC_BK06_10_H _PK_H_(0x06, 0x10) ++#define REG_SC_BK06_11_L _PK_L_(0x06, 0x11) ++#define REG_SC_BK06_11_H _PK_H_(0x06, 0x11) ++#define REG_SC_BK06_12_L _PK_L_(0x06, 0x12) ++#define REG_SC_BK06_12_H _PK_H_(0x06, 0x12) ++#define REG_SC_BK06_13_L _PK_L_(0x06, 0x13) ++#define REG_SC_BK06_13_H _PK_H_(0x06, 0x13) ++#define REG_SC_BK06_14_L _PK_L_(0x06, 0x14) ++#define REG_SC_BK06_14_H _PK_H_(0x06, 0x14) ++#define REG_SC_BK06_15_L _PK_L_(0x06, 0x15) ++#define REG_SC_BK06_15_H _PK_H_(0x06, 0x15) ++#define REG_SC_BK06_16_L _PK_L_(0x06, 0x16) ++#define REG_SC_BK06_16_H _PK_H_(0x06, 0x16) ++#define REG_SC_BK06_17_L _PK_L_(0x06, 0x17) ++#define REG_SC_BK06_17_H _PK_H_(0x06, 0x17) ++#define REG_SC_BK06_18_L _PK_L_(0x06, 0x18) ++#define REG_SC_BK06_18_H _PK_H_(0x06, 0x18) ++#define REG_SC_BK06_19_L _PK_L_(0x06, 0x19) ++#define REG_SC_BK06_19_H _PK_H_(0x06, 0x19) ++#define REG_SC_BK06_1A_L _PK_L_(0x06, 0x1A) ++#define REG_SC_BK06_1A_H _PK_H_(0x06, 0x1A) ++#define REG_SC_BK06_1B_L _PK_L_(0x06, 0x1B) ++#define REG_SC_BK06_1B_H _PK_H_(0x06, 0x1B) ++#define REG_SC_BK06_1C_L _PK_L_(0x06, 0x1C) ++#define REG_SC_BK06_1C_H _PK_H_(0x06, 0x1C) ++#define REG_SC_BK06_1D_L _PK_L_(0x06, 0x1D) ++#define REG_SC_BK06_1D_H _PK_H_(0x06, 0x1D) ++#define REG_SC_BK06_1E_L _PK_L_(0x06, 0x1E) ++#define REG_SC_BK06_1E_H _PK_H_(0x06, 0x1E) ++#define REG_SC_BK06_1F_L _PK_L_(0x06, 0x1F) ++#define REG_SC_BK06_1F_H _PK_H_(0x06, 0x1F) ++#define REG_SC_BK06_20_L _PK_L_(0x06, 0x20) ++#define REG_SC_BK06_20_H _PK_H_(0x06, 0x20) ++#define REG_SC_BK06_21_L _PK_L_(0x06, 0x21) ++#define REG_SC_BK06_21_H _PK_H_(0x06, 0x21) ++#define REG_SC_BK06_22_L _PK_L_(0x06, 0x22) ++#define REG_SC_BK06_22_H _PK_H_(0x06, 0x22) ++#define REG_SC_BK06_23_L _PK_L_(0x06, 0x23) ++#define REG_SC_BK06_23_H _PK_H_(0x06, 0x23) ++#define REG_SC_BK06_24_L _PK_L_(0x06, 0x24) ++#define REG_SC_BK06_24_H _PK_H_(0x06, 0x24) ++#define REG_SC_BK06_25_L _PK_L_(0x06, 0x25) ++#define REG_SC_BK06_25_H _PK_H_(0x06, 0x25) ++#define REG_SC_BK06_26_L _PK_L_(0x06, 0x26) ++#define REG_SC_BK06_26_H _PK_H_(0x06, 0x26) ++#define REG_SC_BK06_27_L _PK_L_(0x06, 0x27) ++#define REG_SC_BK06_27_H _PK_H_(0x06, 0x27) ++#define REG_SC_BK06_28_L _PK_L_(0x06, 0x28) ++#define REG_SC_BK06_28_H _PK_H_(0x06, 0x28) ++#define REG_SC_BK06_29_L _PK_L_(0x06, 0x29) ++#define REG_SC_BK06_29_H _PK_H_(0x06, 0x29) ++#define REG_SC_BK06_2A_L _PK_L_(0x06, 0x2A) ++#define REG_SC_BK06_2A_H _PK_H_(0x06, 0x2A) ++#define REG_SC_BK06_2B_L _PK_L_(0x06, 0x2B) ++#define REG_SC_BK06_2B_H _PK_H_(0x06, 0x2B) ++#define REG_SC_BK06_2C_L _PK_L_(0x06, 0x2C) ++#define REG_SC_BK06_2C_H _PK_H_(0x06, 0x2C) ++#define REG_SC_BK06_2D_L _PK_L_(0x06, 0x2D) ++#define REG_SC_BK06_2D_H _PK_H_(0x06, 0x2D) ++#define REG_SC_BK06_2E_L _PK_L_(0x06, 0x2E) ++#define REG_SC_BK06_2E_H _PK_H_(0x06, 0x2E) ++#define REG_SC_BK06_2F_L _PK_L_(0x06, 0x2F) ++#define REG_SC_BK06_2F_H _PK_H_(0x06, 0x2F) ++#define REG_SC_BK06_30_L _PK_L_(0x06, 0x30) ++#define REG_SC_BK06_30_H _PK_H_(0x06, 0x30) ++#define REG_SC_BK06_31_L _PK_L_(0x06, 0x31) ++#define REG_SC_BK06_31_H _PK_H_(0x06, 0x31) ++#define REG_SC_BK06_32_L _PK_L_(0x06, 0x32) ++#define REG_SC_BK06_32_H _PK_H_(0x06, 0x32) ++#define REG_SC_BK06_33_L _PK_L_(0x06, 0x33) ++#define REG_SC_BK06_33_H _PK_H_(0x06, 0x33) ++#define REG_SC_BK06_34_L _PK_L_(0x06, 0x34) ++#define REG_SC_BK06_34_H _PK_H_(0x06, 0x34) ++#define REG_SC_BK06_35_L _PK_L_(0x06, 0x35) ++#define REG_SC_BK06_35_H _PK_H_(0x06, 0x35) ++#define REG_SC_BK06_36_L _PK_L_(0x06, 0x36) ++#define REG_SC_BK06_36_H _PK_H_(0x06, 0x36) ++#define REG_SC_BK06_37_L _PK_L_(0x06, 0x37) ++#define REG_SC_BK06_37_H _PK_H_(0x06, 0x37) ++#define REG_SC_BK06_38_L _PK_L_(0x06, 0x38) ++#define REG_SC_BK06_38_H _PK_H_(0x06, 0x38) ++#define REG_SC_BK06_39_L _PK_L_(0x06, 0x39) ++#define REG_SC_BK06_39_H _PK_H_(0x06, 0x39) ++#define REG_SC_BK06_3A_L _PK_L_(0x06, 0x3A) ++#define REG_SC_BK06_3A_H _PK_H_(0x06, 0x3A) ++#define REG_SC_BK06_3B_L _PK_L_(0x06, 0x3B) ++#define REG_SC_BK06_3B_H _PK_H_(0x06, 0x3B) ++#define REG_SC_BK06_3C_L _PK_L_(0x06, 0x3C) ++#define REG_SC_BK06_3C_H _PK_H_(0x06, 0x3C) ++#define REG_SC_BK06_3D_L _PK_L_(0x06, 0x3D) ++#define REG_SC_BK06_3D_H _PK_H_(0x06, 0x3D) ++#define REG_SC_BK06_3E_L _PK_L_(0x06, 0x3E) ++#define REG_SC_BK06_3E_H _PK_H_(0x06, 0x3E) ++#define REG_SC_BK06_3F_L _PK_L_(0x06, 0x3F) ++#define REG_SC_BK06_3F_H _PK_H_(0x06, 0x3F) ++#define REG_SC_BK06_40_L _PK_L_(0x06, 0x40) ++#define REG_SC_BK06_40_H _PK_H_(0x06, 0x40) ++#define REG_SC_BK06_41_L _PK_L_(0x06, 0x41) ++#define REG_SC_BK06_41_H _PK_H_(0x06, 0x41) ++#define REG_SC_BK06_42_L _PK_L_(0x06, 0x42) ++#define REG_SC_BK06_42_H _PK_H_(0x06, 0x42) ++#define REG_SC_BK06_43_L _PK_L_(0x06, 0x43) ++#define REG_SC_BK06_43_H _PK_H_(0x06, 0x43) ++#define REG_SC_BK06_44_L _PK_L_(0x06, 0x44) ++#define REG_SC_BK06_44_H _PK_H_(0x06, 0x44) ++#define REG_SC_BK06_45_L _PK_L_(0x06, 0x45) ++#define REG_SC_BK06_45_H _PK_H_(0x06, 0x45) ++#define REG_SC_BK06_46_L _PK_L_(0x06, 0x46) ++#define REG_SC_BK06_46_H _PK_H_(0x06, 0x46) ++#define REG_SC_BK06_47_L _PK_L_(0x06, 0x47) ++#define REG_SC_BK06_47_H _PK_H_(0x06, 0x47) ++#define REG_SC_BK06_48_L _PK_L_(0x06, 0x48) ++#define REG_SC_BK06_48_H _PK_H_(0x06, 0x48) ++#define REG_SC_BK06_49_L _PK_L_(0x06, 0x49) ++#define REG_SC_BK06_49_H _PK_H_(0x06, 0x49) ++#define REG_SC_BK06_4A_L _PK_L_(0x06, 0x4A) ++#define REG_SC_BK06_4A_H _PK_H_(0x06, 0x4A) ++#define REG_SC_BK06_4B_L _PK_L_(0x06, 0x4B) ++#define REG_SC_BK06_4B_H _PK_H_(0x06, 0x4B) ++#define REG_SC_BK06_4C_L _PK_L_(0x06, 0x4C) ++#define REG_SC_BK06_4C_H _PK_H_(0x06, 0x4C) ++#define REG_SC_BK06_4D_L _PK_L_(0x06, 0x4D) ++#define REG_SC_BK06_4D_H _PK_H_(0x06, 0x4D) ++#define REG_SC_BK06_4E_L _PK_L_(0x06, 0x4E) ++#define REG_SC_BK06_4E_H _PK_H_(0x06, 0x4E) ++#define REG_SC_BK06_4F_L _PK_L_(0x06, 0x4F) ++#define REG_SC_BK06_4F_H _PK_H_(0x06, 0x4F) ++#define REG_SC_BK06_50_L _PK_L_(0x06, 0x50) ++#define REG_SC_BK06_50_H _PK_H_(0x06, 0x50) ++#define REG_SC_BK06_51_L _PK_L_(0x06, 0x51) ++#define REG_SC_BK06_51_H _PK_H_(0x06, 0x51) ++#define REG_SC_BK06_52_L _PK_L_(0x06, 0x52) ++#define REG_SC_BK06_52_H _PK_H_(0x06, 0x52) ++#define REG_SC_BK06_53_L _PK_L_(0x06, 0x53) ++#define REG_SC_BK06_53_H _PK_H_(0x06, 0x53) ++#define REG_SC_BK06_54_L _PK_L_(0x06, 0x54) ++#define REG_SC_BK06_54_H _PK_H_(0x06, 0x54) ++#define REG_SC_BK06_55_L _PK_L_(0x06, 0x55) ++#define REG_SC_BK06_55_H _PK_H_(0x06, 0x55) ++#define REG_SC_BK06_56_L _PK_L_(0x06, 0x56) ++#define REG_SC_BK06_56_H _PK_H_(0x06, 0x56) ++#define REG_SC_BK06_57_L _PK_L_(0x06, 0x57) ++#define REG_SC_BK06_57_H _PK_H_(0x06, 0x57) ++#define REG_SC_BK06_58_L _PK_L_(0x06, 0x58) ++#define REG_SC_BK06_58_H _PK_H_(0x06, 0x58) ++#define REG_SC_BK06_59_L _PK_L_(0x06, 0x59) ++#define REG_SC_BK06_59_H _PK_H_(0x06, 0x59) ++#define REG_SC_BK06_5A_L _PK_L_(0x06, 0x5A) ++#define REG_SC_BK06_5A_H _PK_H_(0x06, 0x5A) ++#define REG_SC_BK06_5B_L _PK_L_(0x06, 0x5B) ++#define REG_SC_BK06_5B_H _PK_H_(0x06, 0x5B) ++#define REG_SC_BK06_5C_L _PK_L_(0x06, 0x5C) ++#define REG_SC_BK06_5C_H _PK_H_(0x06, 0x5C) ++#define REG_SC_BK06_5D_L _PK_L_(0x06, 0x5D) ++#define REG_SC_BK06_5D_H _PK_H_(0x06, 0x5D) ++#define REG_SC_BK06_5E_L _PK_L_(0x06, 0x5E) ++#define REG_SC_BK06_5E_H _PK_H_(0x06, 0x5E) ++#define REG_SC_BK06_5F_L _PK_L_(0x06, 0x5F) ++#define REG_SC_BK06_5F_H _PK_H_(0x06, 0x5F) ++#define REG_SC_BK06_60_L _PK_L_(0x06, 0x60) ++#define REG_SC_BK06_60_H _PK_H_(0x06, 0x60) ++#define REG_SC_BK06_61_L _PK_L_(0x06, 0x61) ++#define REG_SC_BK06_61_H _PK_H_(0x06, 0x61) ++#define REG_SC_BK06_62_L _PK_L_(0x06, 0x62) ++#define REG_SC_BK06_62_H _PK_H_(0x06, 0x62) ++#define REG_SC_BK06_63_L _PK_L_(0x06, 0x63) ++#define REG_SC_BK06_63_H _PK_H_(0x06, 0x63) ++#define REG_SC_BK06_64_L _PK_L_(0x06, 0x64) ++#define REG_SC_BK06_64_H _PK_H_(0x06, 0x64) ++#define REG_SC_BK06_65_L _PK_L_(0x06, 0x65) ++#define REG_SC_BK06_65_H _PK_H_(0x06, 0x65) ++#define REG_SC_BK06_66_L _PK_L_(0x06, 0x66) ++#define REG_SC_BK06_66_H _PK_H_(0x06, 0x66) ++#define REG_SC_BK06_67_L _PK_L_(0x06, 0x67) ++#define REG_SC_BK06_67_H _PK_H_(0x06, 0x67) ++#define REG_SC_BK06_68_L _PK_L_(0x06, 0x68) ++#define REG_SC_BK06_68_H _PK_H_(0x06, 0x68) ++#define REG_SC_BK06_69_L _PK_L_(0x06, 0x69) ++#define REG_SC_BK06_69_H _PK_H_(0x06, 0x69) ++#define REG_SC_BK06_6A_L _PK_L_(0x06, 0x6A) ++#define REG_SC_BK06_6A_H _PK_H_(0x06, 0x6A) ++#define REG_SC_BK06_6B_L _PK_L_(0x06, 0x6B) ++#define REG_SC_BK06_6B_H _PK_H_(0x06, 0x6B) ++#define REG_SC_BK06_6C_L _PK_L_(0x06, 0x6C) ++#define REG_SC_BK06_6C_H _PK_H_(0x06, 0x6C) ++#define REG_SC_BK06_6D_L _PK_L_(0x06, 0x6D) ++#define REG_SC_BK06_6D_H _PK_H_(0x06, 0x6D) ++#define REG_SC_BK06_6E_L _PK_L_(0x06, 0x6E) ++#define REG_SC_BK06_6E_H _PK_H_(0x06, 0x6E) ++#define REG_SC_BK06_6F_L _PK_L_(0x06, 0x6F) ++#define REG_SC_BK06_6F_H _PK_H_(0x06, 0x6F) ++#define REG_SC_BK06_70_L _PK_L_(0x06, 0x70) ++#define REG_SC_BK06_70_H _PK_H_(0x06, 0x70) ++#define REG_SC_BK06_71_L _PK_L_(0x06, 0x71) ++#define REG_SC_BK06_71_H _PK_H_(0x06, 0x71) ++#define REG_SC_BK06_72_L _PK_L_(0x06, 0x72) ++#define REG_SC_BK06_72_H _PK_H_(0x06, 0x72) ++#define REG_SC_BK06_73_L _PK_L_(0x06, 0x73) ++#define REG_SC_BK06_73_H _PK_H_(0x06, 0x73) ++#define REG_SC_BK06_74_L _PK_L_(0x06, 0x74) ++#define REG_SC_BK06_74_H _PK_H_(0x06, 0x74) ++#define REG_SC_BK06_75_L _PK_L_(0x06, 0x75) ++#define REG_SC_BK06_75_H _PK_H_(0x06, 0x75) ++#define REG_SC_BK06_76_L _PK_L_(0x06, 0x76) ++#define REG_SC_BK06_76_H _PK_H_(0x06, 0x76) ++#define REG_SC_BK06_77_L _PK_L_(0x06, 0x77) ++#define REG_SC_BK06_77_H _PK_H_(0x06, 0x77) ++#define REG_SC_BK06_78_L _PK_L_(0x06, 0x78) ++#define REG_SC_BK06_78_H _PK_H_(0x06, 0x78) ++#define REG_SC_BK06_79_L _PK_L_(0x06, 0x79) ++#define REG_SC_BK06_79_H _PK_H_(0x06, 0x79) ++#define REG_SC_BK06_7A_L _PK_L_(0x06, 0x7A) ++#define REG_SC_BK06_7A_H _PK_H_(0x06, 0x7A) ++#define REG_SC_BK06_7B_L _PK_L_(0x06, 0x7B) ++#define REG_SC_BK06_7B_H _PK_H_(0x06, 0x7B) ++#define REG_SC_BK06_7C_L _PK_L_(0x06, 0x7C) ++#define REG_SC_BK06_7C_H _PK_H_(0x06, 0x7C) ++#define REG_SC_BK06_7D_L _PK_L_(0x06, 0x7D) ++#define REG_SC_BK06_7D_H _PK_H_(0x06, 0x7D) ++#define REG_SC_BK06_7E_L _PK_L_(0x06, 0x7E) ++#define REG_SC_BK06_7E_H _PK_H_(0x06, 0x7E) ++#define REG_SC_BK06_7F_L _PK_L_(0x06, 0x7F) ++#define REG_SC_BK06_7F_H _PK_H_(0x06, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK07_00_L _PK_L_(0x07, 0x00) ++#define REG_SC_BK07_00_H _PK_H_(0x07, 0x00) ++#define REG_SC_BK07_01_L _PK_L_(0x07, 0x01) ++#define REG_SC_BK07_01_H _PK_H_(0x07, 0x01) ++#define REG_SC_BK07_02_L _PK_L_(0x07, 0x02) ++#define REG_SC_BK07_02_H _PK_H_(0x07, 0x02) ++#define REG_SC_BK07_03_L _PK_L_(0x07, 0x03) ++#define REG_SC_BK07_03_H _PK_H_(0x07, 0x03) ++#define REG_SC_BK07_04_L _PK_L_(0x07, 0x04) ++#define REG_SC_BK07_04_H _PK_H_(0x07, 0x04) ++#define REG_SC_BK07_05_L _PK_L_(0x07, 0x05) ++#define REG_SC_BK07_05_H _PK_H_(0x07, 0x05) ++#define REG_SC_BK07_06_L _PK_L_(0x07, 0x06) ++#define REG_SC_BK07_06_H _PK_H_(0x07, 0x06) ++#define REG_SC_BK07_07_L _PK_L_(0x07, 0x07) ++#define REG_SC_BK07_07_H _PK_H_(0x07, 0x07) ++#define REG_SC_BK07_08_L _PK_L_(0x07, 0x08) ++#define REG_SC_BK07_08_H _PK_H_(0x07, 0x08) ++#define REG_SC_BK07_09_L _PK_L_(0x07, 0x09) ++#define REG_SC_BK07_09_H _PK_H_(0x07, 0x09) ++#define REG_SC_BK07_0A_L _PK_L_(0x07, 0x0A) ++#define REG_SC_BK07_0A_H _PK_H_(0x07, 0x0A) ++#define REG_SC_BK07_0B_L _PK_L_(0x07, 0x0B) ++#define REG_SC_BK07_0B_H _PK_H_(0x07, 0x0B) ++#define REG_SC_BK07_0C_L _PK_L_(0x07, 0x0C) ++#define REG_SC_BK07_0C_H _PK_H_(0x07, 0x0C) ++#define REG_SC_BK07_0D_L _PK_L_(0x07, 0x0D) ++#define REG_SC_BK07_0D_H _PK_H_(0x07, 0x0D) ++#define REG_SC_BK07_0E_L _PK_L_(0x07, 0x0E) ++#define REG_SC_BK07_0E_H _PK_H_(0x07, 0x0E) ++#define REG_SC_BK07_0F_L _PK_L_(0x07, 0x0F) ++#define REG_SC_BK07_0F_H _PK_H_(0x07, 0x0F) ++#define REG_SC_BK07_10_L _PK_L_(0x07, 0x10) ++#define REG_SC_BK07_10_H _PK_H_(0x07, 0x10) ++#define REG_SC_BK07_11_L _PK_L_(0x07, 0x11) ++#define REG_SC_BK07_11_H _PK_H_(0x07, 0x11) ++#define REG_SC_BK07_12_L _PK_L_(0x07, 0x12) ++#define REG_SC_BK07_12_H _PK_H_(0x07, 0x12) ++#define REG_SC_BK07_13_L _PK_L_(0x07, 0x13) ++#define REG_SC_BK07_13_H _PK_H_(0x07, 0x13) ++#define REG_SC_BK07_14_L _PK_L_(0x07, 0x14) ++#define REG_SC_BK07_14_H _PK_H_(0x07, 0x14) ++#define REG_SC_BK07_15_L _PK_L_(0x07, 0x15) ++#define REG_SC_BK07_15_H _PK_H_(0x07, 0x15) ++#define REG_SC_BK07_16_L _PK_L_(0x07, 0x16) ++#define REG_SC_BK07_16_H _PK_H_(0x07, 0x16) ++#define REG_SC_BK07_17_L _PK_L_(0x07, 0x17) ++#define REG_SC_BK07_17_H _PK_H_(0x07, 0x17) ++#define REG_SC_BK07_18_L _PK_L_(0x07, 0x18) ++#define REG_SC_BK07_18_H _PK_H_(0x07, 0x18) ++#define REG_SC_BK07_19_L _PK_L_(0x07, 0x19) ++#define REG_SC_BK07_19_H _PK_H_(0x07, 0x19) ++#define REG_SC_BK07_1A_L _PK_L_(0x07, 0x1A) ++#define REG_SC_BK07_1A_H _PK_H_(0x07, 0x1A) ++#define REG_SC_BK07_1B_L _PK_L_(0x07, 0x1B) ++#define REG_SC_BK07_1B_H _PK_H_(0x07, 0x1B) ++#define REG_SC_BK07_1C_L _PK_L_(0x07, 0x1C) ++#define REG_SC_BK07_1C_H _PK_H_(0x07, 0x1C) ++#define REG_SC_BK07_1D_L _PK_L_(0x07, 0x1D) ++#define REG_SC_BK07_1D_H _PK_H_(0x07, 0x1D) ++#define REG_SC_BK07_1E_L _PK_L_(0x07, 0x1E) ++#define REG_SC_BK07_1E_H _PK_H_(0x07, 0x1E) ++#define REG_SC_BK07_1F_L _PK_L_(0x07, 0x1F) ++#define REG_SC_BK07_1F_H _PK_H_(0x07, 0x1F) ++#define REG_SC_BK07_20_L _PK_L_(0x07, 0x20) ++#define REG_SC_BK07_20_H _PK_H_(0x07, 0x20) ++#define REG_SC_BK07_21_L _PK_L_(0x07, 0x21) ++#define REG_SC_BK07_21_H _PK_H_(0x07, 0x21) ++#define REG_SC_BK07_22_L _PK_L_(0x07, 0x22) ++#define REG_SC_BK07_22_H _PK_H_(0x07, 0x22) ++#define REG_SC_BK07_23_L _PK_L_(0x07, 0x23) ++#define REG_SC_BK07_23_H _PK_H_(0x07, 0x23) ++#define REG_SC_BK07_24_L _PK_L_(0x07, 0x24) ++#define REG_SC_BK07_24_H _PK_H_(0x07, 0x24) ++#define REG_SC_BK07_25_L _PK_L_(0x07, 0x25) ++#define REG_SC_BK07_25_H _PK_H_(0x07, 0x25) ++#define REG_SC_BK07_26_L _PK_L_(0x07, 0x26) ++#define REG_SC_BK07_26_H _PK_H_(0x07, 0x26) ++#define REG_SC_BK07_27_L _PK_L_(0x07, 0x27) ++#define REG_SC_BK07_27_H _PK_H_(0x07, 0x27) ++#define REG_SC_BK07_28_L _PK_L_(0x07, 0x28) ++#define REG_SC_BK07_28_H _PK_H_(0x07, 0x28) ++#define REG_SC_BK07_29_L _PK_L_(0x07, 0x29) ++#define REG_SC_BK07_29_H _PK_H_(0x07, 0x29) ++#define REG_SC_BK07_2A_L _PK_L_(0x07, 0x2A) ++#define REG_SC_BK07_2A_H _PK_H_(0x07, 0x2A) ++#define REG_SC_BK07_2B_L _PK_L_(0x07, 0x2B) ++#define REG_SC_BK07_2B_H _PK_H_(0x07, 0x2B) ++#define REG_SC_BK07_2C_L _PK_L_(0x07, 0x2C) ++#define REG_SC_BK07_2C_H _PK_H_(0x07, 0x2C) ++#define REG_SC_BK07_2D_L _PK_L_(0x07, 0x2D) ++#define REG_SC_BK07_2D_H _PK_H_(0x07, 0x2D) ++#define REG_SC_BK07_2E_L _PK_L_(0x07, 0x2E) ++#define REG_SC_BK07_2E_H _PK_H_(0x07, 0x2E) ++#define REG_SC_BK07_2F_L _PK_L_(0x07, 0x2F) ++#define REG_SC_BK07_2F_H _PK_H_(0x07, 0x2F) ++#define REG_SC_BK07_30_L _PK_L_(0x07, 0x30) ++#define REG_SC_BK07_30_H _PK_H_(0x07, 0x30) ++#define REG_SC_BK07_31_L _PK_L_(0x07, 0x31) ++#define REG_SC_BK07_31_H _PK_H_(0x07, 0x31) ++#define REG_SC_BK07_32_L _PK_L_(0x07, 0x32) ++#define REG_SC_BK07_32_H _PK_H_(0x07, 0x32) ++#define REG_SC_BK07_33_L _PK_L_(0x07, 0x33) ++#define REG_SC_BK07_33_H _PK_H_(0x07, 0x33) ++#define REG_SC_BK07_34_L _PK_L_(0x07, 0x34) ++#define REG_SC_BK07_34_H _PK_H_(0x07, 0x34) ++#define REG_SC_BK07_35_L _PK_L_(0x07, 0x35) ++#define REG_SC_BK07_35_H _PK_H_(0x07, 0x35) ++#define REG_SC_BK07_36_L _PK_L_(0x07, 0x36) ++#define REG_SC_BK07_36_H _PK_H_(0x07, 0x36) ++#define REG_SC_BK07_37_L _PK_L_(0x07, 0x37) ++#define REG_SC_BK07_37_H _PK_H_(0x07, 0x37) ++#define REG_SC_BK07_38_L _PK_L_(0x07, 0x38) ++#define REG_SC_BK07_38_H _PK_H_(0x07, 0x38) ++#define REG_SC_BK07_39_L _PK_L_(0x07, 0x39) ++#define REG_SC_BK07_39_H _PK_H_(0x07, 0x39) ++#define REG_SC_BK07_3A_L _PK_L_(0x07, 0x3A) ++#define REG_SC_BK07_3A_H _PK_H_(0x07, 0x3A) ++#define REG_SC_BK07_3B_L _PK_L_(0x07, 0x3B) ++#define REG_SC_BK07_3B_H _PK_H_(0x07, 0x3B) ++#define REG_SC_BK07_3C_L _PK_L_(0x07, 0x3C) ++#define REG_SC_BK07_3C_H _PK_H_(0x07, 0x3C) ++#define REG_SC_BK07_3D_L _PK_L_(0x07, 0x3D) ++#define REG_SC_BK07_3D_H _PK_H_(0x07, 0x3D) ++#define REG_SC_BK07_3E_L _PK_L_(0x07, 0x3E) ++#define REG_SC_BK07_3E_H _PK_H_(0x07, 0x3E) ++#define REG_SC_BK07_3F_L _PK_L_(0x07, 0x3F) ++#define REG_SC_BK07_3F_H _PK_H_(0x07, 0x3F) ++#define REG_SC_BK07_40_L _PK_L_(0x07, 0x40) ++#define REG_SC_BK07_40_H _PK_H_(0x07, 0x40) ++#define REG_SC_BK07_41_L _PK_L_(0x07, 0x41) ++#define REG_SC_BK07_41_H _PK_H_(0x07, 0x41) ++#define REG_SC_BK07_42_L _PK_L_(0x07, 0x42) ++#define REG_SC_BK07_42_H _PK_H_(0x07, 0x42) ++#define REG_SC_BK07_43_L _PK_L_(0x07, 0x43) ++#define REG_SC_BK07_43_H _PK_H_(0x07, 0x43) ++#define REG_SC_BK07_44_L _PK_L_(0x07, 0x44) ++#define REG_SC_BK07_44_H _PK_H_(0x07, 0x44) ++#define REG_SC_BK07_45_L _PK_L_(0x07, 0x45) ++#define REG_SC_BK07_45_H _PK_H_(0x07, 0x45) ++#define REG_SC_BK07_46_L _PK_L_(0x07, 0x46) ++#define REG_SC_BK07_46_H _PK_H_(0x07, 0x46) ++#define REG_SC_BK07_47_L _PK_L_(0x07, 0x47) ++#define REG_SC_BK07_47_H _PK_H_(0x07, 0x47) ++#define REG_SC_BK07_48_L _PK_L_(0x07, 0x48) ++#define REG_SC_BK07_48_H _PK_H_(0x07, 0x48) ++#define REG_SC_BK07_49_L _PK_L_(0x07, 0x49) ++#define REG_SC_BK07_49_H _PK_H_(0x07, 0x49) ++#define REG_SC_BK07_4A_L _PK_L_(0x07, 0x4A) ++#define REG_SC_BK07_4A_H _PK_H_(0x07, 0x4A) ++#define REG_SC_BK07_4B_L _PK_L_(0x07, 0x4B) ++#define REG_SC_BK07_4B_H _PK_H_(0x07, 0x4B) ++#define REG_SC_BK07_4C_L _PK_L_(0x07, 0x4C) ++#define REG_SC_BK07_4C_H _PK_H_(0x07, 0x4C) ++#define REG_SC_BK07_4D_L _PK_L_(0x07, 0x4D) ++#define REG_SC_BK07_4D_H _PK_H_(0x07, 0x4D) ++#define REG_SC_BK07_4E_L _PK_L_(0x07, 0x4E) ++#define REG_SC_BK07_4E_H _PK_H_(0x07, 0x4E) ++#define REG_SC_BK07_4F_L _PK_L_(0x07, 0x4F) ++#define REG_SC_BK07_4F_H _PK_H_(0x07, 0x4F) ++#define REG_SC_BK07_50_L _PK_L_(0x07, 0x50) ++#define REG_SC_BK07_50_H _PK_H_(0x07, 0x50) ++#define REG_SC_BK07_51_L _PK_L_(0x07, 0x51) ++#define REG_SC_BK07_51_H _PK_H_(0x07, 0x51) ++#define REG_SC_BK07_52_L _PK_L_(0x07, 0x52) ++#define REG_SC_BK07_52_H _PK_H_(0x07, 0x52) ++#define REG_SC_BK07_53_L _PK_L_(0x07, 0x53) ++#define REG_SC_BK07_53_H _PK_H_(0x07, 0x53) ++#define REG_SC_BK07_54_L _PK_L_(0x07, 0x54) ++#define REG_SC_BK07_54_H _PK_H_(0x07, 0x54) ++#define REG_SC_BK07_55_L _PK_L_(0x07, 0x55) ++#define REG_SC_BK07_55_H _PK_H_(0x07, 0x55) ++#define REG_SC_BK07_56_L _PK_L_(0x07, 0x56) ++#define REG_SC_BK07_56_H _PK_H_(0x07, 0x56) ++#define REG_SC_BK07_57_L _PK_L_(0x07, 0x57) ++#define REG_SC_BK07_57_H _PK_H_(0x07, 0x57) ++#define REG_SC_BK07_58_L _PK_L_(0x07, 0x58) ++#define REG_SC_BK07_58_H _PK_H_(0x07, 0x58) ++#define REG_SC_BK07_59_L _PK_L_(0x07, 0x59) ++#define REG_SC_BK07_59_H _PK_H_(0x07, 0x59) ++#define REG_SC_BK07_5A_L _PK_L_(0x07, 0x5A) ++#define REG_SC_BK07_5A_H _PK_H_(0x07, 0x5A) ++#define REG_SC_BK07_5B_L _PK_L_(0x07, 0x5B) ++#define REG_SC_BK07_5B_H _PK_H_(0x07, 0x5B) ++#define REG_SC_BK07_5C_L _PK_L_(0x07, 0x5C) ++#define REG_SC_BK07_5C_H _PK_H_(0x07, 0x5C) ++#define REG_SC_BK07_5D_L _PK_L_(0x07, 0x5D) ++#define REG_SC_BK07_5D_H _PK_H_(0x07, 0x5D) ++#define REG_SC_BK07_5E_L _PK_L_(0x07, 0x5E) ++#define REG_SC_BK07_5E_H _PK_H_(0x07, 0x5E) ++#define REG_SC_BK07_5F_L _PK_L_(0x07, 0x5F) ++#define REG_SC_BK07_5F_H _PK_H_(0x07, 0x5F) ++#define REG_SC_BK07_60_L _PK_L_(0x07, 0x60) ++#define REG_SC_BK07_60_H _PK_H_(0x07, 0x60) ++#define REG_SC_BK07_61_L _PK_L_(0x07, 0x61) ++#define REG_SC_BK07_61_H _PK_H_(0x07, 0x61) ++#define REG_SC_BK07_62_L _PK_L_(0x07, 0x62) ++#define REG_SC_BK07_62_H _PK_H_(0x07, 0x62) ++#define REG_SC_BK07_63_L _PK_L_(0x07, 0x63) ++#define REG_SC_BK07_63_H _PK_H_(0x07, 0x63) ++#define REG_SC_BK07_64_L _PK_L_(0x07, 0x64) ++#define REG_SC_BK07_64_H _PK_H_(0x07, 0x64) ++#define REG_SC_BK07_65_L _PK_L_(0x07, 0x65) ++#define REG_SC_BK07_65_H _PK_H_(0x07, 0x65) ++#define REG_SC_BK07_66_L _PK_L_(0x07, 0x66) ++#define REG_SC_BK07_66_H _PK_H_(0x07, 0x66) ++#define REG_SC_BK07_67_L _PK_L_(0x07, 0x67) ++#define REG_SC_BK07_67_H _PK_H_(0x07, 0x67) ++#define REG_SC_BK07_68_L _PK_L_(0x07, 0x68) ++#define REG_SC_BK07_68_H _PK_H_(0x07, 0x68) ++#define REG_SC_BK07_69_L _PK_L_(0x07, 0x69) ++#define REG_SC_BK07_69_H _PK_H_(0x07, 0x69) ++#define REG_SC_BK07_6A_L _PK_L_(0x07, 0x6A) ++#define REG_SC_BK07_6A_H _PK_H_(0x07, 0x6A) ++#define REG_SC_BK07_6B_L _PK_L_(0x07, 0x6B) ++#define REG_SC_BK07_6B_H _PK_H_(0x07, 0x6B) ++#define REG_SC_BK07_6C_L _PK_L_(0x07, 0x6C) ++#define REG_SC_BK07_6C_H _PK_H_(0x07, 0x6C) ++#define REG_SC_BK07_6D_L _PK_L_(0x07, 0x6D) ++#define REG_SC_BK07_6D_H _PK_H_(0x07, 0x6D) ++#define REG_SC_BK07_6E_L _PK_L_(0x07, 0x6E) ++#define REG_SC_BK07_6E_H _PK_H_(0x07, 0x6E) ++#define REG_SC_BK07_6F_L _PK_L_(0x07, 0x6F) ++#define REG_SC_BK07_6F_H _PK_H_(0x07, 0x6F) ++#define REG_SC_BK07_70_L _PK_L_(0x07, 0x70) ++#define REG_SC_BK07_70_H _PK_H_(0x07, 0x70) ++#define REG_SC_BK07_71_L _PK_L_(0x07, 0x71) ++#define REG_SC_BK07_71_H _PK_H_(0x07, 0x71) ++#define REG_SC_BK07_72_L _PK_L_(0x07, 0x72) ++#define REG_SC_BK07_72_H _PK_H_(0x07, 0x72) ++#define REG_SC_BK07_73_L _PK_L_(0x07, 0x73) ++#define REG_SC_BK07_73_H _PK_H_(0x07, 0x73) ++#define REG_SC_BK07_74_L _PK_L_(0x07, 0x74) ++#define REG_SC_BK07_74_H _PK_H_(0x07, 0x74) ++#define REG_SC_BK07_75_L _PK_L_(0x07, 0x75) ++#define REG_SC_BK07_75_H _PK_H_(0x07, 0x75) ++#define REG_SC_BK07_76_L _PK_L_(0x07, 0x76) ++#define REG_SC_BK07_76_H _PK_H_(0x07, 0x76) ++#define REG_SC_BK07_77_L _PK_L_(0x07, 0x77) ++#define REG_SC_BK07_77_H _PK_H_(0x07, 0x77) ++#define REG_SC_BK07_78_L _PK_L_(0x07, 0x78) ++#define REG_SC_BK07_78_H _PK_H_(0x07, 0x78) ++#define REG_SC_BK07_79_L _PK_L_(0x07, 0x79) ++#define REG_SC_BK07_79_H _PK_H_(0x07, 0x79) ++#define REG_SC_BK07_7A_L _PK_L_(0x07, 0x7A) ++#define REG_SC_BK07_7A_H _PK_H_(0x07, 0x7A) ++#define REG_SC_BK07_7B_L _PK_L_(0x07, 0x7B) ++#define REG_SC_BK07_7B_H _PK_H_(0x07, 0x7B) ++#define REG_SC_BK07_7C_L _PK_L_(0x07, 0x7C) ++#define REG_SC_BK07_7C_H _PK_H_(0x07, 0x7C) ++#define REG_SC_BK07_7D_L _PK_L_(0x07, 0x7D) ++#define REG_SC_BK07_7D_H _PK_H_(0x07, 0x7D) ++#define REG_SC_BK07_7E_L _PK_L_(0x07, 0x7E) ++#define REG_SC_BK07_7E_H _PK_H_(0x07, 0x7E) ++#define REG_SC_BK07_7F_L _PK_L_(0x07, 0x7F) ++#define REG_SC_BK07_7F_H _PK_H_(0x07, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK08_00_L _PK_L_(0x08, 0x00) ++#define REG_SC_BK08_00_H _PK_H_(0x08, 0x00) ++#define REG_SC_BK08_01_L _PK_L_(0x08, 0x01) ++#define REG_SC_BK08_01_H _PK_H_(0x08, 0x01) ++#define REG_SC_BK08_02_L _PK_L_(0x08, 0x02) ++#define REG_SC_BK08_02_H _PK_H_(0x08, 0x02) ++#define REG_SC_BK08_03_L _PK_L_(0x08, 0x03) ++#define REG_SC_BK08_03_H _PK_H_(0x08, 0x03) ++#define REG_SC_BK08_04_L _PK_L_(0x08, 0x04) ++#define REG_SC_BK08_04_H _PK_H_(0x08, 0x04) ++#define REG_SC_BK08_05_L _PK_L_(0x08, 0x05) ++#define REG_SC_BK08_05_H _PK_H_(0x08, 0x05) ++#define REG_SC_BK08_06_L _PK_L_(0x08, 0x06) ++#define REG_SC_BK08_06_H _PK_H_(0x08, 0x06) ++#define REG_SC_BK08_07_L _PK_L_(0x08, 0x07) ++#define REG_SC_BK08_07_H _PK_H_(0x08, 0x07) ++#define REG_SC_BK08_08_L _PK_L_(0x08, 0x08) ++#define REG_SC_BK08_08_H _PK_H_(0x08, 0x08) ++#define REG_SC_BK08_09_L _PK_L_(0x08, 0x09) ++#define REG_SC_BK08_09_H _PK_H_(0x08, 0x09) ++#define REG_SC_BK08_0A_L _PK_L_(0x08, 0x0A) ++#define REG_SC_BK08_0A_H _PK_H_(0x08, 0x0A) ++#define REG_SC_BK08_0B_L _PK_L_(0x08, 0x0B) ++#define REG_SC_BK08_0B_H _PK_H_(0x08, 0x0B) ++#define REG_SC_BK08_0C_L _PK_L_(0x08, 0x0C) ++#define REG_SC_BK08_0C_H _PK_H_(0x08, 0x0C) ++#define REG_SC_BK08_0D_L _PK_L_(0x08, 0x0D) ++#define REG_SC_BK08_0D_H _PK_H_(0x08, 0x0D) ++#define REG_SC_BK08_0E_L _PK_L_(0x08, 0x0E) ++#define REG_SC_BK08_0E_H _PK_H_(0x08, 0x0E) ++#define REG_SC_BK08_0F_L _PK_L_(0x08, 0x0F) ++#define REG_SC_BK08_0F_H _PK_H_(0x08, 0x0F) ++#define REG_SC_BK08_10_L _PK_L_(0x08, 0x10) ++#define REG_SC_BK08_10_H _PK_H_(0x08, 0x10) ++#define REG_SC_BK08_11_L _PK_L_(0x08, 0x11) ++#define REG_SC_BK08_11_H _PK_H_(0x08, 0x11) ++#define REG_SC_BK08_12_L _PK_L_(0x08, 0x12) ++#define REG_SC_BK08_12_H _PK_H_(0x08, 0x12) ++#define REG_SC_BK08_13_L _PK_L_(0x08, 0x13) ++#define REG_SC_BK08_13_H _PK_H_(0x08, 0x13) ++#define REG_SC_BK08_14_L _PK_L_(0x08, 0x14) ++#define REG_SC_BK08_14_H _PK_H_(0x08, 0x14) ++#define REG_SC_BK08_15_L _PK_L_(0x08, 0x15) ++#define REG_SC_BK08_15_H _PK_H_(0x08, 0x15) ++#define REG_SC_BK08_16_L _PK_L_(0x08, 0x16) ++#define REG_SC_BK08_16_H _PK_H_(0x08, 0x16) ++#define REG_SC_BK08_17_L _PK_L_(0x08, 0x17) ++#define REG_SC_BK08_17_H _PK_H_(0x08, 0x17) ++#define REG_SC_BK08_18_L _PK_L_(0x08, 0x18) ++#define REG_SC_BK08_18_H _PK_H_(0x08, 0x18) ++#define REG_SC_BK08_19_L _PK_L_(0x08, 0x19) ++#define REG_SC_BK08_19_H _PK_H_(0x08, 0x19) ++#define REG_SC_BK08_1A_L _PK_L_(0x08, 0x1A) ++#define REG_SC_BK08_1A_H _PK_H_(0x08, 0x1A) ++#define REG_SC_BK08_1B_L _PK_L_(0x08, 0x1B) ++#define REG_SC_BK08_1B_H _PK_H_(0x08, 0x1B) ++#define REG_SC_BK08_1C_L _PK_L_(0x08, 0x1C) ++#define REG_SC_BK08_1C_H _PK_H_(0x08, 0x1C) ++#define REG_SC_BK08_1D_L _PK_L_(0x08, 0x1D) ++#define REG_SC_BK08_1D_H _PK_H_(0x08, 0x1D) ++#define REG_SC_BK08_1E_L _PK_L_(0x08, 0x1E) ++#define REG_SC_BK08_1E_H _PK_H_(0x08, 0x1E) ++#define REG_SC_BK08_1F_L _PK_L_(0x08, 0x1F) ++#define REG_SC_BK08_1F_H _PK_H_(0x08, 0x1F) ++#define REG_SC_BK08_20_L _PK_L_(0x08, 0x20) ++#define REG_SC_BK08_20_H _PK_H_(0x08, 0x20) ++#define REG_SC_BK08_21_L _PK_L_(0x08, 0x21) ++#define REG_SC_BK08_21_H _PK_H_(0x08, 0x21) ++#define REG_SC_BK08_22_L _PK_L_(0x08, 0x22) ++#define REG_SC_BK08_22_H _PK_H_(0x08, 0x22) ++#define REG_SC_BK08_23_L _PK_L_(0x08, 0x23) ++#define REG_SC_BK08_23_H _PK_H_(0x08, 0x23) ++#define REG_SC_BK08_24_L _PK_L_(0x08, 0x24) ++#define REG_SC_BK08_24_H _PK_H_(0x08, 0x24) ++#define REG_SC_BK08_25_L _PK_L_(0x08, 0x25) ++#define REG_SC_BK08_25_H _PK_H_(0x08, 0x25) ++#define REG_SC_BK08_26_L _PK_L_(0x08, 0x26) ++#define REG_SC_BK08_26_H _PK_H_(0x08, 0x26) ++#define REG_SC_BK08_27_L _PK_L_(0x08, 0x27) ++#define REG_SC_BK08_27_H _PK_H_(0x08, 0x27) ++#define REG_SC_BK08_28_L _PK_L_(0x08, 0x28) ++#define REG_SC_BK08_28_H _PK_H_(0x08, 0x28) ++#define REG_SC_BK08_29_L _PK_L_(0x08, 0x29) ++#define REG_SC_BK08_29_H _PK_H_(0x08, 0x29) ++#define REG_SC_BK08_2A_L _PK_L_(0x08, 0x2A) ++#define REG_SC_BK08_2A_H _PK_H_(0x08, 0x2A) ++#define REG_SC_BK08_2B_L _PK_L_(0x08, 0x2B) ++#define REG_SC_BK08_2B_H _PK_H_(0x08, 0x2B) ++#define REG_SC_BK08_2C_L _PK_L_(0x08, 0x2C) ++#define REG_SC_BK08_2C_H _PK_H_(0x08, 0x2C) ++#define REG_SC_BK08_2D_L _PK_L_(0x08, 0x2D) ++#define REG_SC_BK08_2D_H _PK_H_(0x08, 0x2D) ++#define REG_SC_BK08_2E_L _PK_L_(0x08, 0x2E) ++#define REG_SC_BK08_2E_H _PK_H_(0x08, 0x2E) ++#define REG_SC_BK08_2F_L _PK_L_(0x08, 0x2F) ++#define REG_SC_BK08_2F_H _PK_H_(0x08, 0x2F) ++#define REG_SC_BK08_30_L _PK_L_(0x08, 0x30) ++#define REG_SC_BK08_30_H _PK_H_(0x08, 0x30) ++#define REG_SC_BK08_31_L _PK_L_(0x08, 0x31) ++#define REG_SC_BK08_31_H _PK_H_(0x08, 0x31) ++#define REG_SC_BK08_32_L _PK_L_(0x08, 0x32) ++#define REG_SC_BK08_32_H _PK_H_(0x08, 0x32) ++#define REG_SC_BK08_33_L _PK_L_(0x08, 0x33) ++#define REG_SC_BK08_33_H _PK_H_(0x08, 0x33) ++#define REG_SC_BK08_34_L _PK_L_(0x08, 0x34) ++#define REG_SC_BK08_34_H _PK_H_(0x08, 0x34) ++#define REG_SC_BK08_35_L _PK_L_(0x08, 0x35) ++#define REG_SC_BK08_35_H _PK_H_(0x08, 0x35) ++#define REG_SC_BK08_36_L _PK_L_(0x08, 0x36) ++#define REG_SC_BK08_36_H _PK_H_(0x08, 0x36) ++#define REG_SC_BK08_37_L _PK_L_(0x08, 0x37) ++#define REG_SC_BK08_37_H _PK_H_(0x08, 0x37) ++#define REG_SC_BK08_38_L _PK_L_(0x08, 0x38) ++#define REG_SC_BK08_38_H _PK_H_(0x08, 0x38) ++#define REG_SC_BK08_39_L _PK_L_(0x08, 0x39) ++#define REG_SC_BK08_39_H _PK_H_(0x08, 0x39) ++#define REG_SC_BK08_3A_L _PK_L_(0x08, 0x3A) ++#define REG_SC_BK08_3A_H _PK_H_(0x08, 0x3A) ++#define REG_SC_BK08_3B_L _PK_L_(0x08, 0x3B) ++#define REG_SC_BK08_3B_H _PK_H_(0x08, 0x3B) ++#define REG_SC_BK08_3C_L _PK_L_(0x08, 0x3C) ++#define REG_SC_BK08_3C_H _PK_H_(0x08, 0x3C) ++#define REG_SC_BK08_3D_L _PK_L_(0x08, 0x3D) ++#define REG_SC_BK08_3D_H _PK_H_(0x08, 0x3D) ++#define REG_SC_BK08_3E_L _PK_L_(0x08, 0x3E) ++#define REG_SC_BK08_3E_H _PK_H_(0x08, 0x3E) ++#define REG_SC_BK08_3F_L _PK_L_(0x08, 0x3F) ++#define REG_SC_BK08_3F_H _PK_H_(0x08, 0x3F) ++#define REG_SC_BK08_40_L _PK_L_(0x08, 0x40) ++#define REG_SC_BK08_40_H _PK_H_(0x08, 0x40) ++#define REG_SC_BK08_41_L _PK_L_(0x08, 0x41) ++#define REG_SC_BK08_41_H _PK_H_(0x08, 0x41) ++#define REG_SC_BK08_42_L _PK_L_(0x08, 0x42) ++#define REG_SC_BK08_42_H _PK_H_(0x08, 0x42) ++#define REG_SC_BK08_43_L _PK_L_(0x08, 0x43) ++#define REG_SC_BK08_43_H _PK_H_(0x08, 0x43) ++#define REG_SC_BK08_44_L _PK_L_(0x08, 0x44) ++#define REG_SC_BK08_44_H _PK_H_(0x08, 0x44) ++#define REG_SC_BK08_45_L _PK_L_(0x08, 0x45) ++#define REG_SC_BK08_45_H _PK_H_(0x08, 0x45) ++#define REG_SC_BK08_46_L _PK_L_(0x08, 0x46) ++#define REG_SC_BK08_46_H _PK_H_(0x08, 0x46) ++#define REG_SC_BK08_47_L _PK_L_(0x08, 0x47) ++#define REG_SC_BK08_47_H _PK_H_(0x08, 0x47) ++#define REG_SC_BK08_48_L _PK_L_(0x08, 0x48) ++#define REG_SC_BK08_48_H _PK_H_(0x08, 0x48) ++#define REG_SC_BK08_49_L _PK_L_(0x08, 0x49) ++#define REG_SC_BK08_49_H _PK_H_(0x08, 0x49) ++#define REG_SC_BK08_4A_L _PK_L_(0x08, 0x4A) ++#define REG_SC_BK08_4A_H _PK_H_(0x08, 0x4A) ++#define REG_SC_BK08_4B_L _PK_L_(0x08, 0x4B) ++#define REG_SC_BK08_4B_H _PK_H_(0x08, 0x4B) ++#define REG_SC_BK08_4C_L _PK_L_(0x08, 0x4C) ++#define REG_SC_BK08_4C_H _PK_H_(0x08, 0x4C) ++#define REG_SC_BK08_4D_L _PK_L_(0x08, 0x4D) ++#define REG_SC_BK08_4D_H _PK_H_(0x08, 0x4D) ++#define REG_SC_BK08_4E_L _PK_L_(0x08, 0x4E) ++#define REG_SC_BK08_4E_H _PK_H_(0x08, 0x4E) ++#define REG_SC_BK08_4F_L _PK_L_(0x08, 0x4F) ++#define REG_SC_BK08_4F_H _PK_H_(0x08, 0x4F) ++#define REG_SC_BK08_50_L _PK_L_(0x08, 0x50) ++#define REG_SC_BK08_50_H _PK_H_(0x08, 0x50) ++#define REG_SC_BK08_51_L _PK_L_(0x08, 0x51) ++#define REG_SC_BK08_51_H _PK_H_(0x08, 0x51) ++#define REG_SC_BK08_52_L _PK_L_(0x08, 0x52) ++#define REG_SC_BK08_52_H _PK_H_(0x08, 0x52) ++#define REG_SC_BK08_53_L _PK_L_(0x08, 0x53) ++#define REG_SC_BK08_53_H _PK_H_(0x08, 0x53) ++#define REG_SC_BK08_54_L _PK_L_(0x08, 0x54) ++#define REG_SC_BK08_54_H _PK_H_(0x08, 0x54) ++#define REG_SC_BK08_55_L _PK_L_(0x08, 0x55) ++#define REG_SC_BK08_55_H _PK_H_(0x08, 0x55) ++#define REG_SC_BK08_56_L _PK_L_(0x08, 0x56) ++#define REG_SC_BK08_56_H _PK_H_(0x08, 0x56) ++#define REG_SC_BK08_57_L _PK_L_(0x08, 0x57) ++#define REG_SC_BK08_57_H _PK_H_(0x08, 0x57) ++#define REG_SC_BK08_58_L _PK_L_(0x08, 0x58) ++#define REG_SC_BK08_58_H _PK_H_(0x08, 0x58) ++#define REG_SC_BK08_59_L _PK_L_(0x08, 0x59) ++#define REG_SC_BK08_59_H _PK_H_(0x08, 0x59) ++#define REG_SC_BK08_5A_L _PK_L_(0x08, 0x5A) ++#define REG_SC_BK08_5A_H _PK_H_(0x08, 0x5A) ++#define REG_SC_BK08_5B_L _PK_L_(0x08, 0x5B) ++#define REG_SC_BK08_5B_H _PK_H_(0x08, 0x5B) ++#define REG_SC_BK08_5C_L _PK_L_(0x08, 0x5C) ++#define REG_SC_BK08_5C_H _PK_H_(0x08, 0x5C) ++#define REG_SC_BK08_5D_L _PK_L_(0x08, 0x5D) ++#define REG_SC_BK08_5D_H _PK_H_(0x08, 0x5D) ++#define REG_SC_BK08_5E_L _PK_L_(0x08, 0x5E) ++#define REG_SC_BK08_5E_H _PK_H_(0x08, 0x5E) ++#define REG_SC_BK08_5F_L _PK_L_(0x08, 0x5F) ++#define REG_SC_BK08_5F_H _PK_H_(0x08, 0x5F) ++#define REG_SC_BK08_60_L _PK_L_(0x08, 0x60) ++#define REG_SC_BK08_60_H _PK_H_(0x08, 0x60) ++#define REG_SC_BK08_61_L _PK_L_(0x08, 0x61) ++#define REG_SC_BK08_61_H _PK_H_(0x08, 0x61) ++#define REG_SC_BK08_62_L _PK_L_(0x08, 0x62) ++#define REG_SC_BK08_62_H _PK_H_(0x08, 0x62) ++#define REG_SC_BK08_63_L _PK_L_(0x08, 0x63) ++#define REG_SC_BK08_63_H _PK_H_(0x08, 0x63) ++#define REG_SC_BK08_64_L _PK_L_(0x08, 0x64) ++#define REG_SC_BK08_64_H _PK_H_(0x08, 0x64) ++#define REG_SC_BK08_65_L _PK_L_(0x08, 0x65) ++#define REG_SC_BK08_65_H _PK_H_(0x08, 0x65) ++#define REG_SC_BK08_66_L _PK_L_(0x08, 0x66) ++#define REG_SC_BK08_66_H _PK_H_(0x08, 0x66) ++#define REG_SC_BK08_67_L _PK_L_(0x08, 0x67) ++#define REG_SC_BK08_67_H _PK_H_(0x08, 0x67) ++#define REG_SC_BK08_68_L _PK_L_(0x08, 0x68) ++#define REG_SC_BK08_68_H _PK_H_(0x08, 0x68) ++#define REG_SC_BK08_69_L _PK_L_(0x08, 0x69) ++#define REG_SC_BK08_69_H _PK_H_(0x08, 0x69) ++#define REG_SC_BK08_6A_L _PK_L_(0x08, 0x6A) ++#define REG_SC_BK08_6A_H _PK_H_(0x08, 0x6A) ++#define REG_SC_BK08_6B_L _PK_L_(0x08, 0x6B) ++#define REG_SC_BK08_6B_H _PK_H_(0x08, 0x6B) ++#define REG_SC_BK08_6C_L _PK_L_(0x08, 0x6C) ++#define REG_SC_BK08_6C_H _PK_H_(0x08, 0x6C) ++#define REG_SC_BK08_6D_L _PK_L_(0x08, 0x6D) ++#define REG_SC_BK08_6D_H _PK_H_(0x08, 0x6D) ++#define REG_SC_BK08_6E_L _PK_L_(0x08, 0x6E) ++#define REG_SC_BK08_6E_H _PK_H_(0x08, 0x6E) ++#define REG_SC_BK08_6F_L _PK_L_(0x08, 0x6F) ++#define REG_SC_BK08_6F_H _PK_H_(0x08, 0x6F) ++#define REG_SC_BK08_70_L _PK_L_(0x08, 0x70) ++#define REG_SC_BK08_70_H _PK_H_(0x08, 0x70) ++#define REG_SC_BK08_71_L _PK_L_(0x08, 0x71) ++#define REG_SC_BK08_71_H _PK_H_(0x08, 0x71) ++#define REG_SC_BK08_72_L _PK_L_(0x08, 0x72) ++#define REG_SC_BK08_72_H _PK_H_(0x08, 0x72) ++#define REG_SC_BK08_73_L _PK_L_(0x08, 0x73) ++#define REG_SC_BK08_73_H _PK_H_(0x08, 0x73) ++#define REG_SC_BK08_74_L _PK_L_(0x08, 0x74) ++#define REG_SC_BK08_74_H _PK_H_(0x08, 0x74) ++#define REG_SC_BK08_75_L _PK_L_(0x08, 0x75) ++#define REG_SC_BK08_75_H _PK_H_(0x08, 0x75) ++#define REG_SC_BK08_76_L _PK_L_(0x08, 0x76) ++#define REG_SC_BK08_76_H _PK_H_(0x08, 0x76) ++#define REG_SC_BK08_77_L _PK_L_(0x08, 0x77) ++#define REG_SC_BK08_77_H _PK_H_(0x08, 0x77) ++#define REG_SC_BK08_78_L _PK_L_(0x08, 0x78) ++#define REG_SC_BK08_78_H _PK_H_(0x08, 0x78) ++#define REG_SC_BK08_79_L _PK_L_(0x08, 0x79) ++#define REG_SC_BK08_79_H _PK_H_(0x08, 0x79) ++#define REG_SC_BK08_7A_L _PK_L_(0x08, 0x7A) ++#define REG_SC_BK08_7A_H _PK_H_(0x08, 0x7A) ++#define REG_SC_BK08_7B_L _PK_L_(0x08, 0x7B) ++#define REG_SC_BK08_7B_H _PK_H_(0x08, 0x7B) ++#define REG_SC_BK08_7C_L _PK_L_(0x08, 0x7C) ++#define REG_SC_BK08_7C_H _PK_H_(0x08, 0x7C) ++#define REG_SC_BK08_7D_L _PK_L_(0x08, 0x7D) ++#define REG_SC_BK08_7D_H _PK_H_(0x08, 0x7D) ++#define REG_SC_BK08_7E_L _PK_L_(0x08, 0x7E) ++#define REG_SC_BK08_7E_H _PK_H_(0x08, 0x7E) ++#define REG_SC_BK08_7F_L _PK_L_(0x08, 0x7F) ++#define REG_SC_BK08_7F_H _PK_H_(0x08, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK09_00_L _PK_L_(0x09, 0x00) ++#define REG_SC_BK09_00_H _PK_H_(0x09, 0x00) ++#define REG_SC_BK09_01_L _PK_L_(0x09, 0x01) ++#define REG_SC_BK09_01_H _PK_H_(0x09, 0x01) ++#define REG_SC_BK09_02_L _PK_L_(0x09, 0x02) ++#define REG_SC_BK09_02_H _PK_H_(0x09, 0x02) ++#define REG_SC_BK09_03_L _PK_L_(0x09, 0x03) ++#define REG_SC_BK09_03_H _PK_H_(0x09, 0x03) ++#define REG_SC_BK09_04_L _PK_L_(0x09, 0x04) ++#define REG_SC_BK09_04_H _PK_H_(0x09, 0x04) ++#define REG_SC_BK09_05_L _PK_L_(0x09, 0x05) ++#define REG_SC_BK09_05_H _PK_H_(0x09, 0x05) ++#define REG_SC_BK09_06_L _PK_L_(0x09, 0x06) ++#define REG_SC_BK09_06_H _PK_H_(0x09, 0x06) ++#define REG_SC_BK09_07_L _PK_L_(0x09, 0x07) ++#define REG_SC_BK09_07_H _PK_H_(0x09, 0x07) ++#define REG_SC_BK09_08_L _PK_L_(0x09, 0x08) ++#define REG_SC_BK09_08_H _PK_H_(0x09, 0x08) ++#define REG_SC_BK09_09_L _PK_L_(0x09, 0x09) ++#define REG_SC_BK09_09_H _PK_H_(0x09, 0x09) ++#define REG_SC_BK09_0A_L _PK_L_(0x09, 0x0A) ++#define REG_SC_BK09_0A_H _PK_H_(0x09, 0x0A) ++#define REG_SC_BK09_0B_L _PK_L_(0x09, 0x0B) ++#define REG_SC_BK09_0B_H _PK_H_(0x09, 0x0B) ++#define REG_SC_BK09_0C_L _PK_L_(0x09, 0x0C) ++#define REG_SC_BK09_0C_H _PK_H_(0x09, 0x0C) ++#define REG_SC_BK09_0D_L _PK_L_(0x09, 0x0D) ++#define REG_SC_BK09_0D_H _PK_H_(0x09, 0x0D) ++#define REG_SC_BK09_0E_L _PK_L_(0x09, 0x0E) ++#define REG_SC_BK09_0E_H _PK_H_(0x09, 0x0E) ++#define REG_SC_BK09_0F_L _PK_L_(0x09, 0x0F) ++#define REG_SC_BK09_0F_H _PK_H_(0x09, 0x0F) ++#define REG_SC_BK09_10_L _PK_L_(0x09, 0x10) ++#define REG_SC_BK09_10_H _PK_H_(0x09, 0x10) ++#define REG_SC_BK09_11_L _PK_L_(0x09, 0x11) ++#define REG_SC_BK09_11_H _PK_H_(0x09, 0x11) ++#define REG_SC_BK09_12_L _PK_L_(0x09, 0x12) ++#define REG_SC_BK09_12_H _PK_H_(0x09, 0x12) ++#define REG_SC_BK09_13_L _PK_L_(0x09, 0x13) ++#define REG_SC_BK09_13_H _PK_H_(0x09, 0x13) ++#define REG_SC_BK09_14_L _PK_L_(0x09, 0x14) ++#define REG_SC_BK09_14_H _PK_H_(0x09, 0x14) ++#define REG_SC_BK09_15_L _PK_L_(0x09, 0x15) ++#define REG_SC_BK09_15_H _PK_H_(0x09, 0x15) ++#define REG_SC_BK09_16_L _PK_L_(0x09, 0x16) ++#define REG_SC_BK09_16_H _PK_H_(0x09, 0x16) ++#define REG_SC_BK09_17_L _PK_L_(0x09, 0x17) ++#define REG_SC_BK09_17_H _PK_H_(0x09, 0x17) ++#define REG_SC_BK09_18_L _PK_L_(0x09, 0x18) ++#define REG_SC_BK09_18_H _PK_H_(0x09, 0x18) ++#define REG_SC_BK09_19_L _PK_L_(0x09, 0x19) ++#define REG_SC_BK09_19_H _PK_H_(0x09, 0x19) ++#define REG_SC_BK09_1A_L _PK_L_(0x09, 0x1A) ++#define REG_SC_BK09_1A_H _PK_H_(0x09, 0x1A) ++#define REG_SC_BK09_1B_L _PK_L_(0x09, 0x1B) ++#define REG_SC_BK09_1B_H _PK_H_(0x09, 0x1B) ++#define REG_SC_BK09_1C_L _PK_L_(0x09, 0x1C) ++#define REG_SC_BK09_1C_H _PK_H_(0x09, 0x1C) ++#define REG_SC_BK09_1D_L _PK_L_(0x09, 0x1D) ++#define REG_SC_BK09_1D_H _PK_H_(0x09, 0x1D) ++#define REG_SC_BK09_1E_L _PK_L_(0x09, 0x1E) ++#define REG_SC_BK09_1E_H _PK_H_(0x09, 0x1E) ++#define REG_SC_BK09_1F_L _PK_L_(0x09, 0x1F) ++#define REG_SC_BK09_1F_H _PK_H_(0x09, 0x1F) ++#define REG_SC_BK09_20_L _PK_L_(0x09, 0x20) ++#define REG_SC_BK09_20_H _PK_H_(0x09, 0x20) ++#define REG_SC_BK09_21_L _PK_L_(0x09, 0x21) ++#define REG_SC_BK09_21_H _PK_H_(0x09, 0x21) ++#define REG_SC_BK09_22_L _PK_L_(0x09, 0x22) ++#define REG_SC_BK09_22_H _PK_H_(0x09, 0x22) ++#define REG_SC_BK09_23_L _PK_L_(0x09, 0x23) ++#define REG_SC_BK09_23_H _PK_H_(0x09, 0x23) ++#define REG_SC_BK09_24_L _PK_L_(0x09, 0x24) ++#define REG_SC_BK09_24_H _PK_H_(0x09, 0x24) ++#define REG_SC_BK09_25_L _PK_L_(0x09, 0x25) ++#define REG_SC_BK09_25_H _PK_H_(0x09, 0x25) ++#define REG_SC_BK09_26_L _PK_L_(0x09, 0x26) ++#define REG_SC_BK09_26_H _PK_H_(0x09, 0x26) ++#define REG_SC_BK09_27_L _PK_L_(0x09, 0x27) ++#define REG_SC_BK09_27_H _PK_H_(0x09, 0x27) ++#define REG_SC_BK09_28_L _PK_L_(0x09, 0x28) ++#define REG_SC_BK09_28_H _PK_H_(0x09, 0x28) ++#define REG_SC_BK09_29_L _PK_L_(0x09, 0x29) ++#define REG_SC_BK09_29_H _PK_H_(0x09, 0x29) ++#define REG_SC_BK09_2A_L _PK_L_(0x09, 0x2A) ++#define REG_SC_BK09_2A_H _PK_H_(0x09, 0x2A) ++#define REG_SC_BK09_2B_L _PK_L_(0x09, 0x2B) ++#define REG_SC_BK09_2B_H _PK_H_(0x09, 0x2B) ++#define REG_SC_BK09_2C_L _PK_L_(0x09, 0x2C) ++#define REG_SC_BK09_2C_H _PK_H_(0x09, 0x2C) ++#define REG_SC_BK09_2D_L _PK_L_(0x09, 0x2D) ++#define REG_SC_BK09_2D_H _PK_H_(0x09, 0x2D) ++#define REG_SC_BK09_2E_L _PK_L_(0x09, 0x2E) ++#define REG_SC_BK09_2E_H _PK_H_(0x09, 0x2E) ++#define REG_SC_BK09_2F_L _PK_L_(0x09, 0x2F) ++#define REG_SC_BK09_2F_H _PK_H_(0x09, 0x2F) ++#define REG_SC_BK09_30_L _PK_L_(0x09, 0x30) ++#define REG_SC_BK09_30_H _PK_H_(0x09, 0x30) ++#define REG_SC_BK09_31_L _PK_L_(0x09, 0x31) ++#define REG_SC_BK09_31_H _PK_H_(0x09, 0x31) ++#define REG_SC_BK09_32_L _PK_L_(0x09, 0x32) ++#define REG_SC_BK09_32_H _PK_H_(0x09, 0x32) ++#define REG_SC_BK09_33_L _PK_L_(0x09, 0x33) ++#define REG_SC_BK09_33_H _PK_H_(0x09, 0x33) ++#define REG_SC_BK09_34_L _PK_L_(0x09, 0x34) ++#define REG_SC_BK09_34_H _PK_H_(0x09, 0x34) ++#define REG_SC_BK09_35_L _PK_L_(0x09, 0x35) ++#define REG_SC_BK09_35_H _PK_H_(0x09, 0x35) ++#define REG_SC_BK09_36_L _PK_L_(0x09, 0x36) ++#define REG_SC_BK09_36_H _PK_H_(0x09, 0x36) ++#define REG_SC_BK09_37_L _PK_L_(0x09, 0x37) ++#define REG_SC_BK09_37_H _PK_H_(0x09, 0x37) ++#define REG_SC_BK09_38_L _PK_L_(0x09, 0x38) ++#define REG_SC_BK09_38_H _PK_H_(0x09, 0x38) ++#define REG_SC_BK09_39_L _PK_L_(0x09, 0x39) ++#define REG_SC_BK09_39_H _PK_H_(0x09, 0x39) ++#define REG_SC_BK09_3A_L _PK_L_(0x09, 0x3A) ++#define REG_SC_BK09_3A_H _PK_H_(0x09, 0x3A) ++#define REG_SC_BK09_3B_L _PK_L_(0x09, 0x3B) ++#define REG_SC_BK09_3B_H _PK_H_(0x09, 0x3B) ++#define REG_SC_BK09_3C_L _PK_L_(0x09, 0x3C) ++#define REG_SC_BK09_3C_H _PK_H_(0x09, 0x3C) ++#define REG_SC_BK09_3D_L _PK_L_(0x09, 0x3D) ++#define REG_SC_BK09_3D_H _PK_H_(0x09, 0x3D) ++#define REG_SC_BK09_3E_L _PK_L_(0x09, 0x3E) ++#define REG_SC_BK09_3E_H _PK_H_(0x09, 0x3E) ++#define REG_SC_BK09_3F_L _PK_L_(0x09, 0x3F) ++#define REG_SC_BK09_3F_H _PK_H_(0x09, 0x3F) ++#define REG_SC_BK09_40_L _PK_L_(0x09, 0x40) ++#define REG_SC_BK09_40_H _PK_H_(0x09, 0x40) ++#define REG_SC_BK09_41_L _PK_L_(0x09, 0x41) ++#define REG_SC_BK09_41_H _PK_H_(0x09, 0x41) ++#define REG_SC_BK09_42_L _PK_L_(0x09, 0x42) ++#define REG_SC_BK09_42_H _PK_H_(0x09, 0x42) ++#define REG_SC_BK09_43_L _PK_L_(0x09, 0x43) ++#define REG_SC_BK09_43_H _PK_H_(0x09, 0x43) ++#define REG_SC_BK09_44_L _PK_L_(0x09, 0x44) ++#define REG_SC_BK09_44_H _PK_H_(0x09, 0x44) ++#define REG_SC_BK09_45_L _PK_L_(0x09, 0x45) ++#define REG_SC_BK09_45_H _PK_H_(0x09, 0x45) ++#define REG_SC_BK09_46_L _PK_L_(0x09, 0x46) ++#define REG_SC_BK09_46_H _PK_H_(0x09, 0x46) ++#define REG_SC_BK09_47_L _PK_L_(0x09, 0x47) ++#define REG_SC_BK09_47_H _PK_H_(0x09, 0x47) ++#define REG_SC_BK09_48_L _PK_L_(0x09, 0x48) ++#define REG_SC_BK09_48_H _PK_H_(0x09, 0x48) ++#define REG_SC_BK09_49_L _PK_L_(0x09, 0x49) ++#define REG_SC_BK09_49_H _PK_H_(0x09, 0x49) ++#define REG_SC_BK09_4A_L _PK_L_(0x09, 0x4A) ++#define REG_SC_BK09_4A_H _PK_H_(0x09, 0x4A) ++#define REG_SC_BK09_4B_L _PK_L_(0x09, 0x4B) ++#define REG_SC_BK09_4B_H _PK_H_(0x09, 0x4B) ++#define REG_SC_BK09_4C_L _PK_L_(0x09, 0x4C) ++#define REG_SC_BK09_4C_H _PK_H_(0x09, 0x4C) ++#define REG_SC_BK09_4D_L _PK_L_(0x09, 0x4D) ++#define REG_SC_BK09_4D_H _PK_H_(0x09, 0x4D) ++#define REG_SC_BK09_4E_L _PK_L_(0x09, 0x4E) ++#define REG_SC_BK09_4E_H _PK_H_(0x09, 0x4E) ++#define REG_SC_BK09_4F_L _PK_L_(0x09, 0x4F) ++#define REG_SC_BK09_4F_H _PK_H_(0x09, 0x4F) ++#define REG_SC_BK09_50_L _PK_L_(0x09, 0x50) ++#define REG_SC_BK09_50_H _PK_H_(0x09, 0x50) ++#define REG_SC_BK09_51_L _PK_L_(0x09, 0x51) ++#define REG_SC_BK09_51_H _PK_H_(0x09, 0x51) ++#define REG_SC_BK09_52_L _PK_L_(0x09, 0x52) ++#define REG_SC_BK09_52_H _PK_H_(0x09, 0x52) ++#define REG_SC_BK09_53_L _PK_L_(0x09, 0x53) ++#define REG_SC_BK09_53_H _PK_H_(0x09, 0x53) ++#define REG_SC_BK09_54_L _PK_L_(0x09, 0x54) ++#define REG_SC_BK09_54_H _PK_H_(0x09, 0x54) ++#define REG_SC_BK09_55_L _PK_L_(0x09, 0x55) ++#define REG_SC_BK09_55_H _PK_H_(0x09, 0x55) ++#define REG_SC_BK09_56_L _PK_L_(0x09, 0x56) ++#define REG_SC_BK09_56_H _PK_H_(0x09, 0x56) ++#define REG_SC_BK09_57_L _PK_L_(0x09, 0x57) ++#define REG_SC_BK09_57_H _PK_H_(0x09, 0x57) ++#define REG_SC_BK09_58_L _PK_L_(0x09, 0x58) ++#define REG_SC_BK09_58_H _PK_H_(0x09, 0x58) ++#define REG_SC_BK09_59_L _PK_L_(0x09, 0x59) ++#define REG_SC_BK09_59_H _PK_H_(0x09, 0x59) ++#define REG_SC_BK09_5A_L _PK_L_(0x09, 0x5A) ++#define REG_SC_BK09_5A_H _PK_H_(0x09, 0x5A) ++#define REG_SC_BK09_5B_L _PK_L_(0x09, 0x5B) ++#define REG_SC_BK09_5B_H _PK_H_(0x09, 0x5B) ++#define REG_SC_BK09_5C_L _PK_L_(0x09, 0x5C) ++#define REG_SC_BK09_5C_H _PK_H_(0x09, 0x5C) ++#define REG_SC_BK09_5D_L _PK_L_(0x09, 0x5D) ++#define REG_SC_BK09_5D_H _PK_H_(0x09, 0x5D) ++#define REG_SC_BK09_5E_L _PK_L_(0x09, 0x5E) ++#define REG_SC_BK09_5E_H _PK_H_(0x09, 0x5E) ++#define REG_SC_BK09_5F_L _PK_L_(0x09, 0x5F) ++#define REG_SC_BK09_5F_H _PK_H_(0x09, 0x5F) ++#define REG_SC_BK09_60_L _PK_L_(0x09, 0x60) ++#define REG_SC_BK09_60_H _PK_H_(0x09, 0x60) ++#define REG_SC_BK09_61_L _PK_L_(0x09, 0x61) ++#define REG_SC_BK09_61_H _PK_H_(0x09, 0x61) ++#define REG_SC_BK09_62_L _PK_L_(0x09, 0x62) ++#define REG_SC_BK09_62_H _PK_H_(0x09, 0x62) ++#define REG_SC_BK09_63_L _PK_L_(0x09, 0x63) ++#define REG_SC_BK09_63_H _PK_H_(0x09, 0x63) ++#define REG_SC_BK09_64_L _PK_L_(0x09, 0x64) ++#define REG_SC_BK09_64_H _PK_H_(0x09, 0x64) ++#define REG_SC_BK09_65_L _PK_L_(0x09, 0x65) ++#define REG_SC_BK09_65_H _PK_H_(0x09, 0x65) ++#define REG_SC_BK09_66_L _PK_L_(0x09, 0x66) ++#define REG_SC_BK09_66_H _PK_H_(0x09, 0x66) ++#define REG_SC_BK09_67_L _PK_L_(0x09, 0x67) ++#define REG_SC_BK09_67_H _PK_H_(0x09, 0x67) ++#define REG_SC_BK09_68_L _PK_L_(0x09, 0x68) ++#define REG_SC_BK09_68_H _PK_H_(0x09, 0x68) ++#define REG_SC_BK09_69_L _PK_L_(0x09, 0x69) ++#define REG_SC_BK09_69_H _PK_H_(0x09, 0x69) ++#define REG_SC_BK09_6A_L _PK_L_(0x09, 0x6A) ++#define REG_SC_BK09_6A_H _PK_H_(0x09, 0x6A) ++#define REG_SC_BK09_6B_L _PK_L_(0x09, 0x6B) ++#define REG_SC_BK09_6B_H _PK_H_(0x09, 0x6B) ++#define REG_SC_BK09_6C_L _PK_L_(0x09, 0x6C) ++#define REG_SC_BK09_6C_H _PK_H_(0x09, 0x6C) ++#define REG_SC_BK09_6D_L _PK_L_(0x09, 0x6D) ++#define REG_SC_BK09_6D_H _PK_H_(0x09, 0x6D) ++#define REG_SC_BK09_6E_L _PK_L_(0x09, 0x6E) ++#define REG_SC_BK09_6E_H _PK_H_(0x09, 0x6E) ++#define REG_SC_BK09_6F_L _PK_L_(0x09, 0x6F) ++#define REG_SC_BK09_6F_H _PK_H_(0x09, 0x6F) ++#define REG_SC_BK09_70_L _PK_L_(0x09, 0x70) ++#define REG_SC_BK09_70_H _PK_H_(0x09, 0x70) ++#define REG_SC_BK09_71_L _PK_L_(0x09, 0x71) ++#define REG_SC_BK09_71_H _PK_H_(0x09, 0x71) ++#define REG_SC_BK09_72_L _PK_L_(0x09, 0x72) ++#define REG_SC_BK09_72_H _PK_H_(0x09, 0x72) ++#define REG_SC_BK09_73_L _PK_L_(0x09, 0x73) ++#define REG_SC_BK09_73_H _PK_H_(0x09, 0x73) ++#define REG_SC_BK09_74_L _PK_L_(0x09, 0x74) ++#define REG_SC_BK09_74_H _PK_H_(0x09, 0x74) ++#define REG_SC_BK09_75_L _PK_L_(0x09, 0x75) ++#define REG_SC_BK09_75_H _PK_H_(0x09, 0x75) ++#define REG_SC_BK09_76_L _PK_L_(0x09, 0x76) ++#define REG_SC_BK09_76_H _PK_H_(0x09, 0x76) ++#define REG_SC_BK09_77_L _PK_L_(0x09, 0x77) ++#define REG_SC_BK09_77_H _PK_H_(0x09, 0x77) ++#define REG_SC_BK09_78_L _PK_L_(0x09, 0x78) ++#define REG_SC_BK09_78_H _PK_H_(0x09, 0x78) ++#define REG_SC_BK09_79_L _PK_L_(0x09, 0x79) ++#define REG_SC_BK09_79_H _PK_H_(0x09, 0x79) ++#define REG_SC_BK09_7A_L _PK_L_(0x09, 0x7A) ++#define REG_SC_BK09_7A_H _PK_H_(0x09, 0x7A) ++#define REG_SC_BK09_7B_L _PK_L_(0x09, 0x7B) ++#define REG_SC_BK09_7B_H _PK_H_(0x09, 0x7B) ++#define REG_SC_BK09_7C_L _PK_L_(0x09, 0x7C) ++#define REG_SC_BK09_7C_H _PK_H_(0x09, 0x7C) ++#define REG_SC_BK09_7D_L _PK_L_(0x09, 0x7D) ++#define REG_SC_BK09_7D_H _PK_H_(0x09, 0x7D) ++#define REG_SC_BK09_7E_L _PK_L_(0x09, 0x7E) ++#define REG_SC_BK09_7E_H _PK_H_(0x09, 0x7E) ++#define REG_SC_BK09_7F_L _PK_L_(0x09, 0x7F) ++#define REG_SC_BK09_7F_H _PK_H_(0x09, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0A_00_L _PK_L_(0x0A, 0x00) ++#define REG_SC_BK0A_00_H _PK_H_(0x0A, 0x00) ++#define REG_SC_BK0A_01_L _PK_L_(0x0A, 0x01) ++#define REG_SC_BK0A_01_H _PK_H_(0x0A, 0x01) ++#define REG_SC_BK0A_02_L _PK_L_(0x0A, 0x02) ++#define REG_SC_BK0A_02_H _PK_H_(0x0A, 0x02) ++#define REG_SC_BK0A_03_L _PK_L_(0x0A, 0x03) ++#define REG_SC_BK0A_03_H _PK_H_(0x0A, 0x03) ++#define REG_SC_BK0A_04_L _PK_L_(0x0A, 0x04) ++#define REG_SC_BK0A_04_H _PK_H_(0x0A, 0x04) ++#define REG_SC_BK0A_05_L _PK_L_(0x0A, 0x05) ++#define REG_SC_BK0A_05_H _PK_H_(0x0A, 0x05) ++#define REG_SC_BK0A_06_L _PK_L_(0x0A, 0x06) ++#define REG_SC_BK0A_06_H _PK_H_(0x0A, 0x06) ++#define REG_SC_BK0A_07_L _PK_L_(0x0A, 0x07) ++#define REG_SC_BK0A_07_H _PK_H_(0x0A, 0x07) ++#define REG_SC_BK0A_08_L _PK_L_(0x0A, 0x08) ++#define REG_SC_BK0A_08_H _PK_H_(0x0A, 0x08) ++#define REG_SC_BK0A_09_L _PK_L_(0x0A, 0x09) ++#define REG_SC_BK0A_09_H _PK_H_(0x0A, 0x09) ++#define REG_SC_BK0A_0A_L _PK_L_(0x0A, 0x0A) ++#define REG_SC_BK0A_0A_H _PK_H_(0x0A, 0x0A) ++#define REG_SC_BK0A_0B_L _PK_L_(0x0A, 0x0B) ++#define REG_SC_BK0A_0B_H _PK_H_(0x0A, 0x0B) ++#define REG_SC_BK0A_0C_L _PK_L_(0x0A, 0x0C) ++#define REG_SC_BK0A_0C_H _PK_H_(0x0A, 0x0C) ++#define REG_SC_BK0A_0D_L _PK_L_(0x0A, 0x0D) ++#define REG_SC_BK0A_0D_H _PK_H_(0x0A, 0x0D) ++#define REG_SC_BK0A_0E_L _PK_L_(0x0A, 0x0E) ++#define REG_SC_BK0A_0E_H _PK_H_(0x0A, 0x0E) ++#define REG_SC_BK0A_0F_L _PK_L_(0x0A, 0x0F) ++#define REG_SC_BK0A_0F_H _PK_H_(0x0A, 0x0F) ++#define REG_SC_BK0A_10_L _PK_L_(0x0A, 0x10) ++#define REG_SC_BK0A_10_H _PK_H_(0x0A, 0x10) ++#define REG_SC_BK0A_11_L _PK_L_(0x0A, 0x11) ++#define REG_SC_BK0A_11_H _PK_H_(0x0A, 0x11) ++#define REG_SC_BK0A_12_L _PK_L_(0x0A, 0x12) ++#define REG_SC_BK0A_12_H _PK_H_(0x0A, 0x12) ++#define REG_SC_BK0A_13_L _PK_L_(0x0A, 0x13) ++#define REG_SC_BK0A_13_H _PK_H_(0x0A, 0x13) ++#define REG_SC_BK0A_14_L _PK_L_(0x0A, 0x14) ++#define REG_SC_BK0A_14_H _PK_H_(0x0A, 0x14) ++#define REG_SC_BK0A_15_L _PK_L_(0x0A, 0x15) ++#define REG_SC_BK0A_15_H _PK_H_(0x0A, 0x15) ++#define REG_SC_BK0A_16_L _PK_L_(0x0A, 0x16) ++#define REG_SC_BK0A_16_H _PK_H_(0x0A, 0x16) ++#define REG_SC_BK0A_17_L _PK_L_(0x0A, 0x17) ++#define REG_SC_BK0A_17_H _PK_H_(0x0A, 0x17) ++#define REG_SC_BK0A_18_L _PK_L_(0x0A, 0x18) ++#define REG_SC_BK0A_18_H _PK_H_(0x0A, 0x18) ++#define REG_SC_BK0A_19_L _PK_L_(0x0A, 0x19) ++#define REG_SC_BK0A_19_H _PK_H_(0x0A, 0x19) ++#define REG_SC_BK0A_1A_L _PK_L_(0x0A, 0x1A) ++#define REG_SC_BK0A_1A_H _PK_H_(0x0A, 0x1A) ++#define REG_SC_BK0A_1B_L _PK_L_(0x0A, 0x1B) ++#define REG_SC_BK0A_1B_H _PK_H_(0x0A, 0x1B) ++#define REG_SC_BK0A_1C_L _PK_L_(0x0A, 0x1C) ++#define REG_SC_BK0A_1C_H _PK_H_(0x0A, 0x1C) ++#define REG_SC_BK0A_1D_L _PK_L_(0x0A, 0x1D) ++#define REG_SC_BK0A_1D_H _PK_H_(0x0A, 0x1D) ++#define REG_SC_BK0A_1E_L _PK_L_(0x0A, 0x1E) ++#define REG_SC_BK0A_1E_H _PK_H_(0x0A, 0x1E) ++#define REG_SC_BK0A_1F_L _PK_L_(0x0A, 0x1F) ++#define REG_SC_BK0A_1F_H _PK_H_(0x0A, 0x1F) ++#define REG_SC_BK0A_20_L _PK_L_(0x0A, 0x20) ++#define REG_SC_BK0A_20_H _PK_H_(0x0A, 0x20) ++#define REG_SC_BK0A_21_L _PK_L_(0x0A, 0x21) ++#define REG_SC_BK0A_21_H _PK_H_(0x0A, 0x21) ++#define REG_SC_BK0A_22_L _PK_L_(0x0A, 0x22) ++#define REG_SC_BK0A_22_H _PK_H_(0x0A, 0x22) ++#define REG_SC_BK0A_23_L _PK_L_(0x0A, 0x23) ++#define REG_SC_BK0A_23_H _PK_H_(0x0A, 0x23) ++#define REG_SC_BK0A_24_L _PK_L_(0x0A, 0x24) ++#define REG_SC_BK0A_24_H _PK_H_(0x0A, 0x24) ++#define REG_SC_BK0A_25_L _PK_L_(0x0A, 0x25) ++#define REG_SC_BK0A_25_H _PK_H_(0x0A, 0x25) ++#define REG_SC_BK0A_26_L _PK_L_(0x0A, 0x26) ++#define REG_SC_BK0A_26_H _PK_H_(0x0A, 0x26) ++#define REG_SC_BK0A_27_L _PK_L_(0x0A, 0x27) ++#define REG_SC_BK0A_27_H _PK_H_(0x0A, 0x27) ++#define REG_SC_BK0A_28_L _PK_L_(0x0A, 0x28) ++#define REG_SC_BK0A_28_H _PK_H_(0x0A, 0x28) ++#define REG_SC_BK0A_29_L _PK_L_(0x0A, 0x29) ++#define REG_SC_BK0A_29_H _PK_H_(0x0A, 0x29) ++#define REG_SC_BK0A_2A_L _PK_L_(0x0A, 0x2A) ++#define REG_SC_BK0A_2A_H _PK_H_(0x0A, 0x2A) ++#define REG_SC_BK0A_2B_L _PK_L_(0x0A, 0x2B) ++#define REG_SC_BK0A_2B_H _PK_H_(0x0A, 0x2B) ++#define REG_SC_BK0A_2C_L _PK_L_(0x0A, 0x2C) ++#define REG_SC_BK0A_2C_H _PK_H_(0x0A, 0x2C) ++#define REG_SC_BK0A_2D_L _PK_L_(0x0A, 0x2D) ++#define REG_SC_BK0A_2D_H _PK_H_(0x0A, 0x2D) ++#define REG_SC_BK0A_2E_L _PK_L_(0x0A, 0x2E) ++#define REG_SC_BK0A_2E_H _PK_H_(0x0A, 0x2E) ++#define REG_SC_BK0A_2F_L _PK_L_(0x0A, 0x2F) ++#define REG_SC_BK0A_2F_H _PK_H_(0x0A, 0x2F) ++#define REG_SC_BK0A_30_L _PK_L_(0x0A, 0x30) ++#define REG_SC_BK0A_30_H _PK_H_(0x0A, 0x30) ++#define REG_SC_BK0A_31_L _PK_L_(0x0A, 0x31) ++#define REG_SC_BK0A_31_H _PK_H_(0x0A, 0x31) ++#define REG_SC_BK0A_32_L _PK_L_(0x0A, 0x32) ++#define REG_SC_BK0A_32_H _PK_H_(0x0A, 0x32) ++#define REG_SC_BK0A_33_L _PK_L_(0x0A, 0x33) ++#define REG_SC_BK0A_33_H _PK_H_(0x0A, 0x33) ++#define REG_SC_BK0A_34_L _PK_L_(0x0A, 0x34) ++#define REG_SC_BK0A_34_H _PK_H_(0x0A, 0x34) ++#define REG_SC_BK0A_35_L _PK_L_(0x0A, 0x35) ++#define REG_SC_BK0A_35_H _PK_H_(0x0A, 0x35) ++#define REG_SC_BK0A_36_L _PK_L_(0x0A, 0x36) ++#define REG_SC_BK0A_36_H _PK_H_(0x0A, 0x36) ++#define REG_SC_BK0A_37_L _PK_L_(0x0A, 0x37) ++#define REG_SC_BK0A_37_H _PK_H_(0x0A, 0x37) ++#define REG_SC_BK0A_38_L _PK_L_(0x0A, 0x38) ++#define REG_SC_BK0A_38_H _PK_H_(0x0A, 0x38) ++#define REG_SC_BK0A_39_L _PK_L_(0x0A, 0x39) ++#define REG_SC_BK0A_39_H _PK_H_(0x0A, 0x39) ++#define REG_SC_BK0A_3A_L _PK_L_(0x0A, 0x3A) ++#define REG_SC_BK0A_3A_H _PK_H_(0x0A, 0x3A) ++#define REG_SC_BK0A_3B_L _PK_L_(0x0A, 0x3B) ++#define REG_SC_BK0A_3B_H _PK_H_(0x0A, 0x3B) ++#define REG_SC_BK0A_3C_L _PK_L_(0x0A, 0x3C) ++#define REG_SC_BK0A_3C_H _PK_H_(0x0A, 0x3C) ++#define REG_SC_BK0A_3D_L _PK_L_(0x0A, 0x3D) ++#define REG_SC_BK0A_3D_H _PK_H_(0x0A, 0x3D) ++#define REG_SC_BK0A_3E_L _PK_L_(0x0A, 0x3E) ++#define REG_SC_BK0A_3E_H _PK_H_(0x0A, 0x3E) ++#define REG_SC_BK0A_3F_L _PK_L_(0x0A, 0x3F) ++#define REG_SC_BK0A_3F_H _PK_H_(0x0A, 0x3F) ++#define REG_SC_BK0A_40_L _PK_L_(0x0A, 0x40) ++#define REG_SC_BK0A_40_H _PK_H_(0x0A, 0x40) ++#define REG_SC_BK0A_41_L _PK_L_(0x0A, 0x41) ++#define REG_SC_BK0A_41_H _PK_H_(0x0A, 0x41) ++#define REG_SC_BK0A_42_L _PK_L_(0x0A, 0x42) ++#define REG_SC_BK0A_42_H _PK_H_(0x0A, 0x42) ++#define REG_SC_BK0A_43_L _PK_L_(0x0A, 0x43) ++#define REG_SC_BK0A_43_H _PK_H_(0x0A, 0x43) ++#define REG_SC_BK0A_44_L _PK_L_(0x0A, 0x44) ++#define REG_SC_BK0A_44_H _PK_H_(0x0A, 0x44) ++#define REG_SC_BK0A_45_L _PK_L_(0x0A, 0x45) ++#define REG_SC_BK0A_45_H _PK_H_(0x0A, 0x45) ++#define REG_SC_BK0A_46_L _PK_L_(0x0A, 0x46) ++#define REG_SC_BK0A_46_H _PK_H_(0x0A, 0x46) ++#define REG_SC_BK0A_47_L _PK_L_(0x0A, 0x47) ++#define REG_SC_BK0A_47_H _PK_H_(0x0A, 0x47) ++#define REG_SC_BK0A_48_L _PK_L_(0x0A, 0x48) ++#define REG_SC_BK0A_48_H _PK_H_(0x0A, 0x48) ++#define REG_SC_BK0A_49_L _PK_L_(0x0A, 0x49) ++#define REG_SC_BK0A_49_H _PK_H_(0x0A, 0x49) ++#define REG_SC_BK0A_4A_L _PK_L_(0x0A, 0x4A) ++#define REG_SC_BK0A_4A_H _PK_H_(0x0A, 0x4A) ++#define REG_SC_BK0A_4B_L _PK_L_(0x0A, 0x4B) ++#define REG_SC_BK0A_4B_H _PK_H_(0x0A, 0x4B) ++#define REG_SC_BK0A_4C_L _PK_L_(0x0A, 0x4C) ++#define REG_SC_BK0A_4C_H _PK_H_(0x0A, 0x4C) ++#define REG_SC_BK0A_4D_L _PK_L_(0x0A, 0x4D) ++#define REG_SC_BK0A_4D_H _PK_H_(0x0A, 0x4D) ++#define REG_SC_BK0A_4E_L _PK_L_(0x0A, 0x4E) ++#define REG_SC_BK0A_4E_H _PK_H_(0x0A, 0x4E) ++#define REG_SC_BK0A_4F_L _PK_L_(0x0A, 0x4F) ++#define REG_SC_BK0A_4F_H _PK_H_(0x0A, 0x4F) ++#define REG_SC_BK0A_50_L _PK_L_(0x0A, 0x50) ++#define REG_SC_BK0A_50_H _PK_H_(0x0A, 0x50) ++#define REG_SC_BK0A_51_L _PK_L_(0x0A, 0x51) ++#define REG_SC_BK0A_51_H _PK_H_(0x0A, 0x51) ++#define REG_SC_BK0A_52_L _PK_L_(0x0A, 0x52) ++#define REG_SC_BK0A_52_H _PK_H_(0x0A, 0x52) ++#define REG_SC_BK0A_53_L _PK_L_(0x0A, 0x53) ++#define REG_SC_BK0A_53_H _PK_H_(0x0A, 0x53) ++#define REG_SC_BK0A_54_L _PK_L_(0x0A, 0x54) ++#define REG_SC_BK0A_54_H _PK_H_(0x0A, 0x54) ++#define REG_SC_BK0A_55_L _PK_L_(0x0A, 0x55) ++#define REG_SC_BK0A_55_H _PK_H_(0x0A, 0x55) ++#define REG_SC_BK0A_56_L _PK_L_(0x0A, 0x56) ++#define REG_SC_BK0A_56_H _PK_H_(0x0A, 0x56) ++#define REG_SC_BK0A_57_L _PK_L_(0x0A, 0x57) ++#define REG_SC_BK0A_57_H _PK_H_(0x0A, 0x57) ++#define REG_SC_BK0A_58_L _PK_L_(0x0A, 0x58) ++#define REG_SC_BK0A_58_H _PK_H_(0x0A, 0x58) ++#define REG_SC_BK0A_59_L _PK_L_(0x0A, 0x59) ++#define REG_SC_BK0A_59_H _PK_H_(0x0A, 0x59) ++#define REG_SC_BK0A_5A_L _PK_L_(0x0A, 0x5A) ++#define REG_SC_BK0A_5A_H _PK_H_(0x0A, 0x5A) ++#define REG_SC_BK0A_5B_L _PK_L_(0x0A, 0x5B) ++#define REG_SC_BK0A_5B_H _PK_H_(0x0A, 0x5B) ++#define REG_SC_BK0A_5C_L _PK_L_(0x0A, 0x5C) ++#define REG_SC_BK0A_5C_H _PK_H_(0x0A, 0x5C) ++#define REG_SC_BK0A_5D_L _PK_L_(0x0A, 0x5D) ++#define REG_SC_BK0A_5D_H _PK_H_(0x0A, 0x5D) ++#define REG_SC_BK0A_5E_L _PK_L_(0x0A, 0x5E) ++#define REG_SC_BK0A_5E_H _PK_H_(0x0A, 0x5E) ++#define REG_SC_BK0A_5F_L _PK_L_(0x0A, 0x5F) ++#define REG_SC_BK0A_5F_H _PK_H_(0x0A, 0x5F) ++#define REG_SC_BK0A_60_L _PK_L_(0x0A, 0x60) ++#define REG_SC_BK0A_60_H _PK_H_(0x0A, 0x60) ++#define REG_SC_BK0A_61_L _PK_L_(0x0A, 0x61) ++#define REG_SC_BK0A_61_H _PK_H_(0x0A, 0x61) ++#define REG_SC_BK0A_62_L _PK_L_(0x0A, 0x62) ++#define REG_SC_BK0A_62_H _PK_H_(0x0A, 0x62) ++#define REG_SC_BK0A_63_L _PK_L_(0x0A, 0x63) ++#define REG_SC_BK0A_63_H _PK_H_(0x0A, 0x63) ++#define REG_SC_BK0A_64_L _PK_L_(0x0A, 0x64) ++#define REG_SC_BK0A_64_H _PK_H_(0x0A, 0x64) ++#define REG_SC_BK0A_65_L _PK_L_(0x0A, 0x65) ++#define REG_SC_BK0A_65_H _PK_H_(0x0A, 0x65) ++#define REG_SC_BK0A_66_L _PK_L_(0x0A, 0x66) ++#define REG_SC_BK0A_66_H _PK_H_(0x0A, 0x66) ++#define REG_SC_BK0A_67_L _PK_L_(0x0A, 0x67) ++#define REG_SC_BK0A_67_H _PK_H_(0x0A, 0x67) ++#define REG_SC_BK0A_68_L _PK_L_(0x0A, 0x68) ++#define REG_SC_BK0A_68_H _PK_H_(0x0A, 0x68) ++#define REG_SC_BK0A_69_L _PK_L_(0x0A, 0x69) ++#define REG_SC_BK0A_69_H _PK_H_(0x0A, 0x69) ++#define REG_SC_BK0A_6A_L _PK_L_(0x0A, 0x6A) ++#define REG_SC_BK0A_6A_H _PK_H_(0x0A, 0x6A) ++#define REG_SC_BK0A_6B_L _PK_L_(0x0A, 0x6B) ++#define REG_SC_BK0A_6B_H _PK_H_(0x0A, 0x6B) ++#define REG_SC_BK0A_6C_L _PK_L_(0x0A, 0x6C) ++#define REG_SC_BK0A_6C_H _PK_H_(0x0A, 0x6C) ++#define REG_SC_BK0A_6D_L _PK_L_(0x0A, 0x6D) ++#define REG_SC_BK0A_6D_H _PK_H_(0x0A, 0x6D) ++#define REG_SC_BK0A_6E_L _PK_L_(0x0A, 0x6E) ++#define REG_SC_BK0A_6E_H _PK_H_(0x0A, 0x6E) ++#define REG_SC_BK0A_6F_L _PK_L_(0x0A, 0x6F) ++#define REG_SC_BK0A_6F_H _PK_H_(0x0A, 0x6F) ++#define REG_SC_BK0A_70_L _PK_L_(0x0A, 0x70) ++#define REG_SC_BK0A_70_H _PK_H_(0x0A, 0x70) ++#define REG_SC_BK0A_71_L _PK_L_(0x0A, 0x71) ++#define REG_SC_BK0A_71_H _PK_H_(0x0A, 0x71) ++#define REG_SC_BK0A_72_L _PK_L_(0x0A, 0x72) ++#define REG_SC_BK0A_72_H _PK_H_(0x0A, 0x72) ++#define REG_SC_BK0A_73_L _PK_L_(0x0A, 0x73) ++#define REG_SC_BK0A_73_H _PK_H_(0x0A, 0x73) ++#define REG_SC_BK0A_74_L _PK_L_(0x0A, 0x74) ++#define REG_SC_BK0A_74_H _PK_H_(0x0A, 0x74) ++#define REG_SC_BK0A_75_L _PK_L_(0x0A, 0x75) ++#define REG_SC_BK0A_75_H _PK_H_(0x0A, 0x75) ++#define REG_SC_BK0A_76_L _PK_L_(0x0A, 0x76) ++#define REG_SC_BK0A_76_H _PK_H_(0x0A, 0x76) ++#define REG_SC_BK0A_77_L _PK_L_(0x0A, 0x77) ++#define REG_SC_BK0A_77_H _PK_H_(0x0A, 0x77) ++#define REG_SC_BK0A_78_L _PK_L_(0x0A, 0x78) ++#define REG_SC_BK0A_78_H _PK_H_(0x0A, 0x78) ++#define REG_SC_BK0A_79_L _PK_L_(0x0A, 0x79) ++#define REG_SC_BK0A_79_H _PK_H_(0x0A, 0x79) ++#define REG_SC_BK0A_7A_L _PK_L_(0x0A, 0x7A) ++#define REG_SC_BK0A_7A_H _PK_H_(0x0A, 0x7A) ++#define REG_SC_BK0A_7B_L _PK_L_(0x0A, 0x7B) ++#define REG_SC_BK0A_7B_H _PK_H_(0x0A, 0x7B) ++#define REG_SC_BK0A_7C_L _PK_L_(0x0A, 0x7C) ++#define REG_SC_BK0A_7C_H _PK_H_(0x0A, 0x7C) ++#define REG_SC_BK0A_7D_L _PK_L_(0x0A, 0x7D) ++#define REG_SC_BK0A_7D_H _PK_H_(0x0A, 0x7D) ++#define REG_SC_BK0A_7E_L _PK_L_(0x0A, 0x7E) ++#define REG_SC_BK0A_7E_H _PK_H_(0x0A, 0x7E) ++#define REG_SC_BK0A_7F_L _PK_L_(0x0A, 0x7F) ++#define REG_SC_BK0A_7F_H _PK_H_(0x0A, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0B_00_L _PK_L_(0x0B, 0x00) ++#define REG_SC_BK0B_00_H _PK_H_(0x0B, 0x00) ++#define REG_SC_BK0B_01_L _PK_L_(0x0B, 0x01) ++#define REG_SC_BK0B_01_H _PK_H_(0x0B, 0x01) ++#define REG_SC_BK0B_02_L _PK_L_(0x0B, 0x02) ++#define REG_SC_BK0B_02_H _PK_H_(0x0B, 0x02) ++#define REG_SC_BK0B_03_L _PK_L_(0x0B, 0x03) ++#define REG_SC_BK0B_03_H _PK_H_(0x0B, 0x03) ++#define REG_SC_BK0B_04_L _PK_L_(0x0B, 0x04) ++#define REG_SC_BK0B_04_H _PK_H_(0x0B, 0x04) ++#define REG_SC_BK0B_05_L _PK_L_(0x0B, 0x05) ++#define REG_SC_BK0B_05_H _PK_H_(0x0B, 0x05) ++#define REG_SC_BK0B_06_L _PK_L_(0x0B, 0x06) ++#define REG_SC_BK0B_06_H _PK_H_(0x0B, 0x06) ++#define REG_SC_BK0B_07_L _PK_L_(0x0B, 0x07) ++#define REG_SC_BK0B_07_H _PK_H_(0x0B, 0x07) ++#define REG_SC_BK0B_08_L _PK_L_(0x0B, 0x08) ++#define REG_SC_BK0B_08_H _PK_H_(0x0B, 0x08) ++#define REG_SC_BK0B_09_L _PK_L_(0x0B, 0x09) ++#define REG_SC_BK0B_09_H _PK_H_(0x0B, 0x09) ++#define REG_SC_BK0B_0A_L _PK_L_(0x0B, 0x0A) ++#define REG_SC_BK0B_0A_H _PK_H_(0x0B, 0x0A) ++#define REG_SC_BK0B_0B_L _PK_L_(0x0B, 0x0B) ++#define REG_SC_BK0B_0B_H _PK_H_(0x0B, 0x0B) ++#define REG_SC_BK0B_0C_L _PK_L_(0x0B, 0x0C) ++#define REG_SC_BK0B_0C_H _PK_H_(0x0B, 0x0C) ++#define REG_SC_BK0B_0D_L _PK_L_(0x0B, 0x0D) ++#define REG_SC_BK0B_0D_H _PK_H_(0x0B, 0x0D) ++#define REG_SC_BK0B_0E_L _PK_L_(0x0B, 0x0E) ++#define REG_SC_BK0B_0E_H _PK_H_(0x0B, 0x0E) ++#define REG_SC_BK0B_0F_L _PK_L_(0x0B, 0x0F) ++#define REG_SC_BK0B_0F_H _PK_H_(0x0B, 0x0F) ++#define REG_SC_BK0B_10_L _PK_L_(0x0B, 0x10) ++#define REG_SC_BK0B_10_H _PK_H_(0x0B, 0x10) ++#define REG_SC_BK0B_11_L _PK_L_(0x0B, 0x11) ++#define REG_SC_BK0B_11_H _PK_H_(0x0B, 0x11) ++#define REG_SC_BK0B_12_L _PK_L_(0x0B, 0x12) ++#define REG_SC_BK0B_12_H _PK_H_(0x0B, 0x12) ++#define REG_SC_BK0B_13_L _PK_L_(0x0B, 0x13) ++#define REG_SC_BK0B_13_H _PK_H_(0x0B, 0x13) ++#define REG_SC_BK0B_14_L _PK_L_(0x0B, 0x14) ++#define REG_SC_BK0B_14_H _PK_H_(0x0B, 0x14) ++#define REG_SC_BK0B_15_L _PK_L_(0x0B, 0x15) ++#define REG_SC_BK0B_15_H _PK_H_(0x0B, 0x15) ++#define REG_SC_BK0B_16_L _PK_L_(0x0B, 0x16) ++#define REG_SC_BK0B_16_H _PK_H_(0x0B, 0x16) ++#define REG_SC_BK0B_17_L _PK_L_(0x0B, 0x17) ++#define REG_SC_BK0B_17_H _PK_H_(0x0B, 0x17) ++#define REG_SC_BK0B_18_L _PK_L_(0x0B, 0x18) ++#define REG_SC_BK0B_18_H _PK_H_(0x0B, 0x18) ++#define REG_SC_BK0B_19_L _PK_L_(0x0B, 0x19) ++#define REG_SC_BK0B_19_H _PK_H_(0x0B, 0x19) ++#define REG_SC_BK0B_1A_L _PK_L_(0x0B, 0x1A) ++#define REG_SC_BK0B_1A_H _PK_H_(0x0B, 0x1A) ++#define REG_SC_BK0B_1B_L _PK_L_(0x0B, 0x1B) ++#define REG_SC_BK0B_1B_H _PK_H_(0x0B, 0x1B) ++#define REG_SC_BK0B_1C_L _PK_L_(0x0B, 0x1C) ++#define REG_SC_BK0B_1C_H _PK_H_(0x0B, 0x1C) ++#define REG_SC_BK0B_1D_L _PK_L_(0x0B, 0x1D) ++#define REG_SC_BK0B_1D_H _PK_H_(0x0B, 0x1D) ++#define REG_SC_BK0B_1E_L _PK_L_(0x0B, 0x1E) ++#define REG_SC_BK0B_1E_H _PK_H_(0x0B, 0x1E) ++#define REG_SC_BK0B_1F_L _PK_L_(0x0B, 0x1F) ++#define REG_SC_BK0B_1F_H _PK_H_(0x0B, 0x1F) ++#define REG_SC_BK0B_20_L _PK_L_(0x0B, 0x20) ++#define REG_SC_BK0B_20_H _PK_H_(0x0B, 0x20) ++#define REG_SC_BK0B_21_L _PK_L_(0x0B, 0x21) ++#define REG_SC_BK0B_21_H _PK_H_(0x0B, 0x21) ++#define REG_SC_BK0B_22_L _PK_L_(0x0B, 0x22) ++#define REG_SC_BK0B_22_H _PK_H_(0x0B, 0x22) ++#define REG_SC_BK0B_23_L _PK_L_(0x0B, 0x23) ++#define REG_SC_BK0B_23_H _PK_H_(0x0B, 0x23) ++#define REG_SC_BK0B_24_L _PK_L_(0x0B, 0x24) ++#define REG_SC_BK0B_24_H _PK_H_(0x0B, 0x24) ++#define REG_SC_BK0B_25_L _PK_L_(0x0B, 0x25) ++#define REG_SC_BK0B_25_H _PK_H_(0x0B, 0x25) ++#define REG_SC_BK0B_26_L _PK_L_(0x0B, 0x26) ++#define REG_SC_BK0B_26_H _PK_H_(0x0B, 0x26) ++#define REG_SC_BK0B_27_L _PK_L_(0x0B, 0x27) ++#define REG_SC_BK0B_27_H _PK_H_(0x0B, 0x27) ++#define REG_SC_BK0B_28_L _PK_L_(0x0B, 0x28) ++#define REG_SC_BK0B_28_H _PK_H_(0x0B, 0x28) ++#define REG_SC_BK0B_29_L _PK_L_(0x0B, 0x29) ++#define REG_SC_BK0B_29_H _PK_H_(0x0B, 0x29) ++#define REG_SC_BK0B_2A_L _PK_L_(0x0B, 0x2A) ++#define REG_SC_BK0B_2A_H _PK_H_(0x0B, 0x2A) ++#define REG_SC_BK0B_2B_L _PK_L_(0x0B, 0x2B) ++#define REG_SC_BK0B_2B_H _PK_H_(0x0B, 0x2B) ++#define REG_SC_BK0B_2C_L _PK_L_(0x0B, 0x2C) ++#define REG_SC_BK0B_2C_H _PK_H_(0x0B, 0x2C) ++#define REG_SC_BK0B_2D_L _PK_L_(0x0B, 0x2D) ++#define REG_SC_BK0B_2D_H _PK_H_(0x0B, 0x2D) ++#define REG_SC_BK0B_2E_L _PK_L_(0x0B, 0x2E) ++#define REG_SC_BK0B_2E_H _PK_H_(0x0B, 0x2E) ++#define REG_SC_BK0B_2F_L _PK_L_(0x0B, 0x2F) ++#define REG_SC_BK0B_2F_H _PK_H_(0x0B, 0x2F) ++#define REG_SC_BK0B_30_L _PK_L_(0x0B, 0x30) ++#define REG_SC_BK0B_30_H _PK_H_(0x0B, 0x30) ++#define REG_SC_BK0B_31_L _PK_L_(0x0B, 0x31) ++#define REG_SC_BK0B_31_H _PK_H_(0x0B, 0x31) ++#define REG_SC_BK0B_32_L _PK_L_(0x0B, 0x32) ++#define REG_SC_BK0B_32_H _PK_H_(0x0B, 0x32) ++#define REG_SC_BK0B_33_L _PK_L_(0x0B, 0x33) ++#define REG_SC_BK0B_33_H _PK_H_(0x0B, 0x33) ++#define REG_SC_BK0B_34_L _PK_L_(0x0B, 0x34) ++#define REG_SC_BK0B_34_H _PK_H_(0x0B, 0x34) ++#define REG_SC_BK0B_35_L _PK_L_(0x0B, 0x35) ++#define REG_SC_BK0B_35_H _PK_H_(0x0B, 0x35) ++#define REG_SC_BK0B_36_L _PK_L_(0x0B, 0x36) ++#define REG_SC_BK0B_36_H _PK_H_(0x0B, 0x36) ++#define REG_SC_BK0B_37_L _PK_L_(0x0B, 0x37) ++#define REG_SC_BK0B_37_H _PK_H_(0x0B, 0x37) ++#define REG_SC_BK0B_38_L _PK_L_(0x0B, 0x38) ++#define REG_SC_BK0B_38_H _PK_H_(0x0B, 0x38) ++#define REG_SC_BK0B_39_L _PK_L_(0x0B, 0x39) ++#define REG_SC_BK0B_39_H _PK_H_(0x0B, 0x39) ++#define REG_SC_BK0B_3A_L _PK_L_(0x0B, 0x3A) ++#define REG_SC_BK0B_3A_H _PK_H_(0x0B, 0x3A) ++#define REG_SC_BK0B_3B_L _PK_L_(0x0B, 0x3B) ++#define REG_SC_BK0B_3B_H _PK_H_(0x0B, 0x3B) ++#define REG_SC_BK0B_3C_L _PK_L_(0x0B, 0x3C) ++#define REG_SC_BK0B_3C_H _PK_H_(0x0B, 0x3C) ++#define REG_SC_BK0B_3D_L _PK_L_(0x0B, 0x3D) ++#define REG_SC_BK0B_3D_H _PK_H_(0x0B, 0x3D) ++#define REG_SC_BK0B_3E_L _PK_L_(0x0B, 0x3E) ++#define REG_SC_BK0B_3E_H _PK_H_(0x0B, 0x3E) ++#define REG_SC_BK0B_3F_L _PK_L_(0x0B, 0x3F) ++#define REG_SC_BK0B_3F_H _PK_H_(0x0B, 0x3F) ++#define REG_SC_BK0B_40_L _PK_L_(0x0B, 0x40) ++#define REG_SC_BK0B_40_H _PK_H_(0x0B, 0x40) ++#define REG_SC_BK0B_41_L _PK_L_(0x0B, 0x41) ++#define REG_SC_BK0B_41_H _PK_H_(0x0B, 0x41) ++#define REG_SC_BK0B_42_L _PK_L_(0x0B, 0x42) ++#define REG_SC_BK0B_42_H _PK_H_(0x0B, 0x42) ++#define REG_SC_BK0B_43_L _PK_L_(0x0B, 0x43) ++#define REG_SC_BK0B_43_H _PK_H_(0x0B, 0x43) ++#define REG_SC_BK0B_44_L _PK_L_(0x0B, 0x44) ++#define REG_SC_BK0B_44_H _PK_H_(0x0B, 0x44) ++#define REG_SC_BK0B_45_L _PK_L_(0x0B, 0x45) ++#define REG_SC_BK0B_45_H _PK_H_(0x0B, 0x45) ++#define REG_SC_BK0B_46_L _PK_L_(0x0B, 0x46) ++#define REG_SC_BK0B_46_H _PK_H_(0x0B, 0x46) ++#define REG_SC_BK0B_47_L _PK_L_(0x0B, 0x47) ++#define REG_SC_BK0B_47_H _PK_H_(0x0B, 0x47) ++#define REG_SC_BK0B_48_L _PK_L_(0x0B, 0x48) ++#define REG_SC_BK0B_48_H _PK_H_(0x0B, 0x48) ++#define REG_SC_BK0B_49_L _PK_L_(0x0B, 0x49) ++#define REG_SC_BK0B_49_H _PK_H_(0x0B, 0x49) ++#define REG_SC_BK0B_4A_L _PK_L_(0x0B, 0x4A) ++#define REG_SC_BK0B_4A_H _PK_H_(0x0B, 0x4A) ++#define REG_SC_BK0B_4B_L _PK_L_(0x0B, 0x4B) ++#define REG_SC_BK0B_4B_H _PK_H_(0x0B, 0x4B) ++#define REG_SC_BK0B_4C_L _PK_L_(0x0B, 0x4C) ++#define REG_SC_BK0B_4C_H _PK_H_(0x0B, 0x4C) ++#define REG_SC_BK0B_4D_L _PK_L_(0x0B, 0x4D) ++#define REG_SC_BK0B_4D_H _PK_H_(0x0B, 0x4D) ++#define REG_SC_BK0B_4E_L _PK_L_(0x0B, 0x4E) ++#define REG_SC_BK0B_4E_H _PK_H_(0x0B, 0x4E) ++#define REG_SC_BK0B_4F_L _PK_L_(0x0B, 0x4F) ++#define REG_SC_BK0B_4F_H _PK_H_(0x0B, 0x4F) ++#define REG_SC_BK0B_50_L _PK_L_(0x0B, 0x50) ++#define REG_SC_BK0B_50_H _PK_H_(0x0B, 0x50) ++#define REG_SC_BK0B_51_L _PK_L_(0x0B, 0x51) ++#define REG_SC_BK0B_51_H _PK_H_(0x0B, 0x51) ++#define REG_SC_BK0B_52_L _PK_L_(0x0B, 0x52) ++#define REG_SC_BK0B_52_H _PK_H_(0x0B, 0x52) ++#define REG_SC_BK0B_53_L _PK_L_(0x0B, 0x53) ++#define REG_SC_BK0B_53_H _PK_H_(0x0B, 0x53) ++#define REG_SC_BK0B_54_L _PK_L_(0x0B, 0x54) ++#define REG_SC_BK0B_54_H _PK_H_(0x0B, 0x54) ++#define REG_SC_BK0B_55_L _PK_L_(0x0B, 0x55) ++#define REG_SC_BK0B_55_H _PK_H_(0x0B, 0x55) ++#define REG_SC_BK0B_56_L _PK_L_(0x0B, 0x56) ++#define REG_SC_BK0B_56_H _PK_H_(0x0B, 0x56) ++#define REG_SC_BK0B_57_L _PK_L_(0x0B, 0x57) ++#define REG_SC_BK0B_57_H _PK_H_(0x0B, 0x57) ++#define REG_SC_BK0B_58_L _PK_L_(0x0B, 0x58) ++#define REG_SC_BK0B_58_H _PK_H_(0x0B, 0x58) ++#define REG_SC_BK0B_59_L _PK_L_(0x0B, 0x59) ++#define REG_SC_BK0B_59_H _PK_H_(0x0B, 0x59) ++#define REG_SC_BK0B_5A_L _PK_L_(0x0B, 0x5A) ++#define REG_SC_BK0B_5A_H _PK_H_(0x0B, 0x5A) ++#define REG_SC_BK0B_5B_L _PK_L_(0x0B, 0x5B) ++#define REG_SC_BK0B_5B_H _PK_H_(0x0B, 0x5B) ++#define REG_SC_BK0B_5C_L _PK_L_(0x0B, 0x5C) ++#define REG_SC_BK0B_5C_H _PK_H_(0x0B, 0x5C) ++#define REG_SC_BK0B_5D_L _PK_L_(0x0B, 0x5D) ++#define REG_SC_BK0B_5D_H _PK_H_(0x0B, 0x5D) ++#define REG_SC_BK0B_5E_L _PK_L_(0x0B, 0x5E) ++#define REG_SC_BK0B_5E_H _PK_H_(0x0B, 0x5E) ++#define REG_SC_BK0B_5F_L _PK_L_(0x0B, 0x5F) ++#define REG_SC_BK0B_5F_H _PK_H_(0x0B, 0x5F) ++#define REG_SC_BK0B_60_L _PK_L_(0x0B, 0x60) ++#define REG_SC_BK0B_60_H _PK_H_(0x0B, 0x60) ++#define REG_SC_BK0B_61_L _PK_L_(0x0B, 0x61) ++#define REG_SC_BK0B_61_H _PK_H_(0x0B, 0x61) ++#define REG_SC_BK0B_62_L _PK_L_(0x0B, 0x62) ++#define REG_SC_BK0B_62_H _PK_H_(0x0B, 0x62) ++#define REG_SC_BK0B_63_L _PK_L_(0x0B, 0x63) ++#define REG_SC_BK0B_63_H _PK_H_(0x0B, 0x63) ++#define REG_SC_BK0B_64_L _PK_L_(0x0B, 0x64) ++#define REG_SC_BK0B_64_H _PK_H_(0x0B, 0x64) ++#define REG_SC_BK0B_65_L _PK_L_(0x0B, 0x65) ++#define REG_SC_BK0B_65_H _PK_H_(0x0B, 0x65) ++#define REG_SC_BK0B_66_L _PK_L_(0x0B, 0x66) ++#define REG_SC_BK0B_66_H _PK_H_(0x0B, 0x66) ++#define REG_SC_BK0B_67_L _PK_L_(0x0B, 0x67) ++#define REG_SC_BK0B_67_H _PK_H_(0x0B, 0x67) ++#define REG_SC_BK0B_68_L _PK_L_(0x0B, 0x68) ++#define REG_SC_BK0B_68_H _PK_H_(0x0B, 0x68) ++#define REG_SC_BK0B_69_L _PK_L_(0x0B, 0x69) ++#define REG_SC_BK0B_69_H _PK_H_(0x0B, 0x69) ++#define REG_SC_BK0B_6A_L _PK_L_(0x0B, 0x6A) ++#define REG_SC_BK0B_6A_H _PK_H_(0x0B, 0x6A) ++#define REG_SC_BK0B_6B_L _PK_L_(0x0B, 0x6B) ++#define REG_SC_BK0B_6B_H _PK_H_(0x0B, 0x6B) ++#define REG_SC_BK0B_6C_L _PK_L_(0x0B, 0x6C) ++#define REG_SC_BK0B_6C_H _PK_H_(0x0B, 0x6C) ++#define REG_SC_BK0B_6D_L _PK_L_(0x0B, 0x6D) ++#define REG_SC_BK0B_6D_H _PK_H_(0x0B, 0x6D) ++#define REG_SC_BK0B_6E_L _PK_L_(0x0B, 0x6E) ++#define REG_SC_BK0B_6E_H _PK_H_(0x0B, 0x6E) ++#define REG_SC_BK0B_6F_L _PK_L_(0x0B, 0x6F) ++#define REG_SC_BK0B_6F_H _PK_H_(0x0B, 0x6F) ++#define REG_SC_BK0B_70_L _PK_L_(0x0B, 0x70) ++#define REG_SC_BK0B_70_H _PK_H_(0x0B, 0x70) ++#define REG_SC_BK0B_71_L _PK_L_(0x0B, 0x71) ++#define REG_SC_BK0B_71_H _PK_H_(0x0B, 0x71) ++#define REG_SC_BK0B_72_L _PK_L_(0x0B, 0x72) ++#define REG_SC_BK0B_72_H _PK_H_(0x0B, 0x72) ++#define REG_SC_BK0B_73_L _PK_L_(0x0B, 0x73) ++#define REG_SC_BK0B_73_H _PK_H_(0x0B, 0x73) ++#define REG_SC_BK0B_74_L _PK_L_(0x0B, 0x74) ++#define REG_SC_BK0B_74_H _PK_H_(0x0B, 0x74) ++#define REG_SC_BK0B_75_L _PK_L_(0x0B, 0x75) ++#define REG_SC_BK0B_75_H _PK_H_(0x0B, 0x75) ++#define REG_SC_BK0B_76_L _PK_L_(0x0B, 0x76) ++#define REG_SC_BK0B_76_H _PK_H_(0x0B, 0x76) ++#define REG_SC_BK0B_77_L _PK_L_(0x0B, 0x77) ++#define REG_SC_BK0B_77_H _PK_H_(0x0B, 0x77) ++#define REG_SC_BK0B_78_L _PK_L_(0x0B, 0x78) ++#define REG_SC_BK0B_78_H _PK_H_(0x0B, 0x78) ++#define REG_SC_BK0B_79_L _PK_L_(0x0B, 0x79) ++#define REG_SC_BK0B_79_H _PK_H_(0x0B, 0x79) ++#define REG_SC_BK0B_7A_L _PK_L_(0x0B, 0x7A) ++#define REG_SC_BK0B_7A_H _PK_H_(0x0B, 0x7A) ++#define REG_SC_BK0B_7B_L _PK_L_(0x0B, 0x7B) ++#define REG_SC_BK0B_7B_H _PK_H_(0x0B, 0x7B) ++#define REG_SC_BK0B_7C_L _PK_L_(0x0B, 0x7C) ++#define REG_SC_BK0B_7C_H _PK_H_(0x0B, 0x7C) ++#define REG_SC_BK0B_7D_L _PK_L_(0x0B, 0x7D) ++#define REG_SC_BK0B_7D_H _PK_H_(0x0B, 0x7D) ++#define REG_SC_BK0B_7E_L _PK_L_(0x0B, 0x7E) ++#define REG_SC_BK0B_7E_H _PK_H_(0x0B, 0x7E) ++#define REG_SC_BK0B_7F_L _PK_L_(0x0B, 0x7F) ++#define REG_SC_BK0B_7F_H _PK_H_(0x0B, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0C_00_L _PK_L_(0x0C, 0x00) ++#define REG_SC_BK0C_00_H _PK_H_(0x0C, 0x00) ++#define REG_SC_BK0C_01_L _PK_L_(0x0C, 0x01) ++#define REG_SC_BK0C_01_H _PK_H_(0x0C, 0x01) ++#define REG_SC_BK0C_02_L _PK_L_(0x0C, 0x02) ++#define REG_SC_BK0C_02_H _PK_H_(0x0C, 0x02) ++#define REG_SC_BK0C_03_L _PK_L_(0x0C, 0x03) ++#define REG_SC_BK0C_03_H _PK_H_(0x0C, 0x03) ++#define REG_SC_BK0C_04_L _PK_L_(0x0C, 0x04) ++#define REG_SC_BK0C_04_H _PK_H_(0x0C, 0x04) ++#define REG_SC_BK0C_05_L _PK_L_(0x0C, 0x05) ++#define REG_SC_BK0C_05_H _PK_H_(0x0C, 0x05) ++#define REG_SC_BK0C_06_L _PK_L_(0x0C, 0x06) ++#define REG_SC_BK0C_06_H _PK_H_(0x0C, 0x06) ++#define REG_SC_BK0C_07_L _PK_L_(0x0C, 0x07) ++#define REG_SC_BK0C_07_H _PK_H_(0x0C, 0x07) ++#define REG_SC_BK0C_08_L _PK_L_(0x0C, 0x08) ++#define REG_SC_BK0C_08_H _PK_H_(0x0C, 0x08) ++#define REG_SC_BK0C_09_L _PK_L_(0x0C, 0x09) ++#define REG_SC_BK0C_09_H _PK_H_(0x0C, 0x09) ++#define REG_SC_BK0C_0A_L _PK_L_(0x0C, 0x0A) ++#define REG_SC_BK0C_0A_H _PK_H_(0x0C, 0x0A) ++#define REG_SC_BK0C_0B_L _PK_L_(0x0C, 0x0B) ++#define REG_SC_BK0C_0B_H _PK_H_(0x0C, 0x0B) ++#define REG_SC_BK0C_0C_L _PK_L_(0x0C, 0x0C) ++#define REG_SC_BK0C_0C_H _PK_H_(0x0C, 0x0C) ++#define REG_SC_BK0C_0D_L _PK_L_(0x0C, 0x0D) ++#define REG_SC_BK0C_0D_H _PK_H_(0x0C, 0x0D) ++#define REG_SC_BK0C_0E_L _PK_L_(0x0C, 0x0E) ++#define REG_SC_BK0C_0E_H _PK_H_(0x0C, 0x0E) ++#define REG_SC_BK0C_0F_L _PK_L_(0x0C, 0x0F) ++#define REG_SC_BK0C_0F_H _PK_H_(0x0C, 0x0F) ++#define REG_SC_BK0C_10_L _PK_L_(0x0C, 0x10) ++#define REG_SC_BK0C_10_H _PK_H_(0x0C, 0x10) ++#define REG_SC_BK0C_11_L _PK_L_(0x0C, 0x11) ++#define REG_SC_BK0C_11_H _PK_H_(0x0C, 0x11) ++#define REG_SC_BK0C_12_L _PK_L_(0x0C, 0x12) ++#define REG_SC_BK0C_12_H _PK_H_(0x0C, 0x12) ++#define REG_SC_BK0C_13_L _PK_L_(0x0C, 0x13) ++#define REG_SC_BK0C_13_H _PK_H_(0x0C, 0x13) ++#define REG_SC_BK0C_14_L _PK_L_(0x0C, 0x14) ++#define REG_SC_BK0C_14_H _PK_H_(0x0C, 0x14) ++#define REG_SC_BK0C_15_L _PK_L_(0x0C, 0x15) ++#define REG_SC_BK0C_15_H _PK_H_(0x0C, 0x15) ++#define REG_SC_BK0C_16_L _PK_L_(0x0C, 0x16) ++#define REG_SC_BK0C_16_H _PK_H_(0x0C, 0x16) ++#define REG_SC_BK0C_17_L _PK_L_(0x0C, 0x17) ++#define REG_SC_BK0C_17_H _PK_H_(0x0C, 0x17) ++#define REG_SC_BK0C_18_L _PK_L_(0x0C, 0x18) ++#define REG_SC_BK0C_18_H _PK_H_(0x0C, 0x18) ++#define REG_SC_BK0C_19_L _PK_L_(0x0C, 0x19) ++#define REG_SC_BK0C_19_H _PK_H_(0x0C, 0x19) ++#define REG_SC_BK0C_1A_L _PK_L_(0x0C, 0x1A) ++#define REG_SC_BK0C_1A_H _PK_H_(0x0C, 0x1A) ++#define REG_SC_BK0C_1B_L _PK_L_(0x0C, 0x1B) ++#define REG_SC_BK0C_1B_H _PK_H_(0x0C, 0x1B) ++#define REG_SC_BK0C_1C_L _PK_L_(0x0C, 0x1C) ++#define REG_SC_BK0C_1C_H _PK_H_(0x0C, 0x1C) ++#define REG_SC_BK0C_1D_L _PK_L_(0x0C, 0x1D) ++#define REG_SC_BK0C_1D_H _PK_H_(0x0C, 0x1D) ++#define REG_SC_BK0C_1E_L _PK_L_(0x0C, 0x1E) ++#define REG_SC_BK0C_1E_H _PK_H_(0x0C, 0x1E) ++#define REG_SC_BK0C_1F_L _PK_L_(0x0C, 0x1F) ++#define REG_SC_BK0C_1F_H _PK_H_(0x0C, 0x1F) ++#define REG_SC_BK0C_20_L _PK_L_(0x0C, 0x20) ++#define REG_SC_BK0C_20_H _PK_H_(0x0C, 0x20) ++#define REG_SC_BK0C_21_L _PK_L_(0x0C, 0x21) ++#define REG_SC_BK0C_21_H _PK_H_(0x0C, 0x21) ++#define REG_SC_BK0C_22_L _PK_L_(0x0C, 0x22) ++#define REG_SC_BK0C_22_H _PK_H_(0x0C, 0x22) ++#define REG_SC_BK0C_23_L _PK_L_(0x0C, 0x23) ++#define REG_SC_BK0C_23_H _PK_H_(0x0C, 0x23) ++#define REG_SC_BK0C_24_L _PK_L_(0x0C, 0x24) ++#define REG_SC_BK0C_24_H _PK_H_(0x0C, 0x24) ++#define REG_SC_BK0C_25_L _PK_L_(0x0C, 0x25) ++#define REG_SC_BK0C_25_H _PK_H_(0x0C, 0x25) ++#define REG_SC_BK0C_26_L _PK_L_(0x0C, 0x26) ++#define REG_SC_BK0C_26_H _PK_H_(0x0C, 0x26) ++#define REG_SC_BK0C_27_L _PK_L_(0x0C, 0x27) ++#define REG_SC_BK0C_27_H _PK_H_(0x0C, 0x27) ++#define REG_SC_BK0C_28_L _PK_L_(0x0C, 0x28) ++#define REG_SC_BK0C_28_H _PK_H_(0x0C, 0x28) ++#define REG_SC_BK0C_29_L _PK_L_(0x0C, 0x29) ++#define REG_SC_BK0C_29_H _PK_H_(0x0C, 0x29) ++#define REG_SC_BK0C_2A_L _PK_L_(0x0C, 0x2A) ++#define REG_SC_BK0C_2A_H _PK_H_(0x0C, 0x2A) ++#define REG_SC_BK0C_2B_L _PK_L_(0x0C, 0x2B) ++#define REG_SC_BK0C_2B_H _PK_H_(0x0C, 0x2B) ++#define REG_SC_BK0C_2C_L _PK_L_(0x0C, 0x2C) ++#define REG_SC_BK0C_2C_H _PK_H_(0x0C, 0x2C) ++#define REG_SC_BK0C_2D_L _PK_L_(0x0C, 0x2D) ++#define REG_SC_BK0C_2D_H _PK_H_(0x0C, 0x2D) ++#define REG_SC_BK0C_2E_L _PK_L_(0x0C, 0x2E) ++#define REG_SC_BK0C_2E_H _PK_H_(0x0C, 0x2E) ++#define REG_SC_BK0C_2F_L _PK_L_(0x0C, 0x2F) ++#define REG_SC_BK0C_2F_H _PK_H_(0x0C, 0x2F) ++#define REG_SC_BK0C_30_L _PK_L_(0x0C, 0x30) ++#define REG_SC_BK0C_30_H _PK_H_(0x0C, 0x30) ++#define REG_SC_BK0C_31_L _PK_L_(0x0C, 0x31) ++#define REG_SC_BK0C_31_H _PK_H_(0x0C, 0x31) ++#define REG_SC_BK0C_32_L _PK_L_(0x0C, 0x32) ++#define REG_SC_BK0C_32_H _PK_H_(0x0C, 0x32) ++#define REG_SC_BK0C_33_L _PK_L_(0x0C, 0x33) ++#define REG_SC_BK0C_33_H _PK_H_(0x0C, 0x33) ++#define REG_SC_BK0C_34_L _PK_L_(0x0C, 0x34) ++#define REG_SC_BK0C_34_H _PK_H_(0x0C, 0x34) ++#define REG_SC_BK0C_35_L _PK_L_(0x0C, 0x35) ++#define REG_SC_BK0C_35_H _PK_H_(0x0C, 0x35) ++#define REG_SC_BK0C_36_L _PK_L_(0x0C, 0x36) ++#define REG_SC_BK0C_36_H _PK_H_(0x0C, 0x36) ++#define REG_SC_BK0C_37_L _PK_L_(0x0C, 0x37) ++#define REG_SC_BK0C_37_H _PK_H_(0x0C, 0x37) ++#define REG_SC_BK0C_38_L _PK_L_(0x0C, 0x38) ++#define REG_SC_BK0C_38_H _PK_H_(0x0C, 0x38) ++#define REG_SC_BK0C_39_L _PK_L_(0x0C, 0x39) ++#define REG_SC_BK0C_39_H _PK_H_(0x0C, 0x39) ++#define REG_SC_BK0C_3A_L _PK_L_(0x0C, 0x3A) ++#define REG_SC_BK0C_3A_H _PK_H_(0x0C, 0x3A) ++#define REG_SC_BK0C_3B_L _PK_L_(0x0C, 0x3B) ++#define REG_SC_BK0C_3B_H _PK_H_(0x0C, 0x3B) ++#define REG_SC_BK0C_3C_L _PK_L_(0x0C, 0x3C) ++#define REG_SC_BK0C_3C_H _PK_H_(0x0C, 0x3C) ++#define REG_SC_BK0C_3D_L _PK_L_(0x0C, 0x3D) ++#define REG_SC_BK0C_3D_H _PK_H_(0x0C, 0x3D) ++#define REG_SC_BK0C_3E_L _PK_L_(0x0C, 0x3E) ++#define REG_SC_BK0C_3E_H _PK_H_(0x0C, 0x3E) ++#define REG_SC_BK0C_3F_L _PK_L_(0x0C, 0x3F) ++#define REG_SC_BK0C_3F_H _PK_H_(0x0C, 0x3F) ++#define REG_SC_BK0C_40_L _PK_L_(0x0C, 0x40) ++#define REG_SC_BK0C_40_H _PK_H_(0x0C, 0x40) ++#define REG_SC_BK0C_41_L _PK_L_(0x0C, 0x41) ++#define REG_SC_BK0C_41_H _PK_H_(0x0C, 0x41) ++#define REG_SC_BK0C_42_L _PK_L_(0x0C, 0x42) ++#define REG_SC_BK0C_42_H _PK_H_(0x0C, 0x42) ++#define REG_SC_BK0C_43_L _PK_L_(0x0C, 0x43) ++#define REG_SC_BK0C_43_H _PK_H_(0x0C, 0x43) ++#define REG_SC_BK0C_44_L _PK_L_(0x0C, 0x44) ++#define REG_SC_BK0C_44_H _PK_H_(0x0C, 0x44) ++#define REG_SC_BK0C_45_L _PK_L_(0x0C, 0x45) ++#define REG_SC_BK0C_45_H _PK_H_(0x0C, 0x45) ++#define REG_SC_BK0C_46_L _PK_L_(0x0C, 0x46) ++#define REG_SC_BK0C_46_H _PK_H_(0x0C, 0x46) ++#define REG_SC_BK0C_47_L _PK_L_(0x0C, 0x47) ++#define REG_SC_BK0C_47_H _PK_H_(0x0C, 0x47) ++#define REG_SC_BK0C_48_L _PK_L_(0x0C, 0x48) ++#define REG_SC_BK0C_48_H _PK_H_(0x0C, 0x48) ++#define REG_SC_BK0C_49_L _PK_L_(0x0C, 0x49) ++#define REG_SC_BK0C_49_H _PK_H_(0x0C, 0x49) ++#define REG_SC_BK0C_4A_L _PK_L_(0x0C, 0x4A) ++#define REG_SC_BK0C_4A_H _PK_H_(0x0C, 0x4A) ++#define REG_SC_BK0C_4B_L _PK_L_(0x0C, 0x4B) ++#define REG_SC_BK0C_4B_H _PK_H_(0x0C, 0x4B) ++#define REG_SC_BK0C_4C_L _PK_L_(0x0C, 0x4C) ++#define REG_SC_BK0C_4C_H _PK_H_(0x0C, 0x4C) ++#define REG_SC_BK0C_4D_L _PK_L_(0x0C, 0x4D) ++#define REG_SC_BK0C_4D_H _PK_H_(0x0C, 0x4D) ++#define REG_SC_BK0C_4E_L _PK_L_(0x0C, 0x4E) ++#define REG_SC_BK0C_4E_H _PK_H_(0x0C, 0x4E) ++#define REG_SC_BK0C_4F_L _PK_L_(0x0C, 0x4F) ++#define REG_SC_BK0C_4F_H _PK_H_(0x0C, 0x4F) ++#define REG_SC_BK0C_50_L _PK_L_(0x0C, 0x50) ++#define REG_SC_BK0C_50_H _PK_H_(0x0C, 0x50) ++#define REG_SC_BK0C_51_L _PK_L_(0x0C, 0x51) ++#define REG_SC_BK0C_51_H _PK_H_(0x0C, 0x51) ++#define REG_SC_BK0C_52_L _PK_L_(0x0C, 0x52) ++#define REG_SC_BK0C_52_H _PK_H_(0x0C, 0x52) ++#define REG_SC_BK0C_53_L _PK_L_(0x0C, 0x53) ++#define REG_SC_BK0C_53_H _PK_H_(0x0C, 0x53) ++#define REG_SC_BK0C_54_L _PK_L_(0x0C, 0x54) ++#define REG_SC_BK0C_54_H _PK_H_(0x0C, 0x54) ++#define REG_SC_BK0C_55_L _PK_L_(0x0C, 0x55) ++#define REG_SC_BK0C_55_H _PK_H_(0x0C, 0x55) ++#define REG_SC_BK0C_56_L _PK_L_(0x0C, 0x56) ++#define REG_SC_BK0C_56_H _PK_H_(0x0C, 0x56) ++#define REG_SC_BK0C_57_L _PK_L_(0x0C, 0x57) ++#define REG_SC_BK0C_57_H _PK_H_(0x0C, 0x57) ++#define REG_SC_BK0C_58_L _PK_L_(0x0C, 0x58) ++#define REG_SC_BK0C_58_H _PK_H_(0x0C, 0x58) ++#define REG_SC_BK0C_59_L _PK_L_(0x0C, 0x59) ++#define REG_SC_BK0C_59_H _PK_H_(0x0C, 0x59) ++#define REG_SC_BK0C_5A_L _PK_L_(0x0C, 0x5A) ++#define REG_SC_BK0C_5A_H _PK_H_(0x0C, 0x5A) ++#define REG_SC_BK0C_5B_L _PK_L_(0x0C, 0x5B) ++#define REG_SC_BK0C_5B_H _PK_H_(0x0C, 0x5B) ++#define REG_SC_BK0C_5C_L _PK_L_(0x0C, 0x5C) ++#define REG_SC_BK0C_5C_H _PK_H_(0x0C, 0x5C) ++#define REG_SC_BK0C_5D_L _PK_L_(0x0C, 0x5D) ++#define REG_SC_BK0C_5D_H _PK_H_(0x0C, 0x5D) ++#define REG_SC_BK0C_5E_L _PK_L_(0x0C, 0x5E) ++#define REG_SC_BK0C_5E_H _PK_H_(0x0C, 0x5E) ++#define REG_SC_BK0C_5F_L _PK_L_(0x0C, 0x5F) ++#define REG_SC_BK0C_5F_H _PK_H_(0x0C, 0x5F) ++#define REG_SC_BK0C_60_L _PK_L_(0x0C, 0x60) ++#define REG_SC_BK0C_60_H _PK_H_(0x0C, 0x60) ++#define REG_SC_BK0C_61_L _PK_L_(0x0C, 0x61) ++#define REG_SC_BK0C_61_H _PK_H_(0x0C, 0x61) ++#define REG_SC_BK0C_62_L _PK_L_(0x0C, 0x62) ++#define REG_SC_BK0C_62_H _PK_H_(0x0C, 0x62) ++#define REG_SC_BK0C_63_L _PK_L_(0x0C, 0x63) ++#define REG_SC_BK0C_63_H _PK_H_(0x0C, 0x63) ++#define REG_SC_BK0C_64_L _PK_L_(0x0C, 0x64) ++#define REG_SC_BK0C_64_H _PK_H_(0x0C, 0x64) ++#define REG_SC_BK0C_65_L _PK_L_(0x0C, 0x65) ++#define REG_SC_BK0C_65_H _PK_H_(0x0C, 0x65) ++#define REG_SC_BK0C_66_L _PK_L_(0x0C, 0x66) ++#define REG_SC_BK0C_66_H _PK_H_(0x0C, 0x66) ++#define REG_SC_BK0C_67_L _PK_L_(0x0C, 0x67) ++#define REG_SC_BK0C_67_H _PK_H_(0x0C, 0x67) ++#define REG_SC_BK0C_68_L _PK_L_(0x0C, 0x68) ++#define REG_SC_BK0C_68_H _PK_H_(0x0C, 0x68) ++#define REG_SC_BK0C_69_L _PK_L_(0x0C, 0x69) ++#define REG_SC_BK0C_69_H _PK_H_(0x0C, 0x69) ++#define REG_SC_BK0C_6A_L _PK_L_(0x0C, 0x6A) ++#define REG_SC_BK0C_6A_H _PK_H_(0x0C, 0x6A) ++#define REG_SC_BK0C_6B_L _PK_L_(0x0C, 0x6B) ++#define REG_SC_BK0C_6B_H _PK_H_(0x0C, 0x6B) ++#define REG_SC_BK0C_6C_L _PK_L_(0x0C, 0x6C) ++#define REG_SC_BK0C_6C_H _PK_H_(0x0C, 0x6C) ++#define REG_SC_BK0C_6D_L _PK_L_(0x0C, 0x6D) ++#define REG_SC_BK0C_6D_H _PK_H_(0x0C, 0x6D) ++#define REG_SC_BK0C_6E_L _PK_L_(0x0C, 0x6E) ++#define REG_SC_BK0C_6E_H _PK_H_(0x0C, 0x6E) ++#define REG_SC_BK0C_6F_L _PK_L_(0x0C, 0x6F) ++#define REG_SC_BK0C_6F_H _PK_H_(0x0C, 0x6F) ++#define REG_SC_BK0C_70_L _PK_L_(0x0C, 0x70) ++#define REG_SC_BK0C_70_H _PK_H_(0x0C, 0x70) ++#define REG_SC_BK0C_71_L _PK_L_(0x0C, 0x71) ++#define REG_SC_BK0C_71_H _PK_H_(0x0C, 0x71) ++#define REG_SC_BK0C_72_L _PK_L_(0x0C, 0x72) ++#define REG_SC_BK0C_72_H _PK_H_(0x0C, 0x72) ++#define REG_SC_BK0C_73_L _PK_L_(0x0C, 0x73) ++#define REG_SC_BK0C_73_H _PK_H_(0x0C, 0x73) ++#define REG_SC_BK0C_74_L _PK_L_(0x0C, 0x74) ++#define REG_SC_BK0C_74_H _PK_H_(0x0C, 0x74) ++#define REG_SC_BK0C_75_L _PK_L_(0x0C, 0x75) ++#define REG_SC_BK0C_75_H _PK_H_(0x0C, 0x75) ++#define REG_SC_BK0C_76_L _PK_L_(0x0C, 0x76) ++#define REG_SC_BK0C_76_H _PK_H_(0x0C, 0x76) ++#define REG_SC_BK0C_77_L _PK_L_(0x0C, 0x77) ++#define REG_SC_BK0C_77_H _PK_H_(0x0C, 0x77) ++#define REG_SC_BK0C_78_L _PK_L_(0x0C, 0x78) ++#define REG_SC_BK0C_78_H _PK_H_(0x0C, 0x78) ++#define REG_SC_BK0C_79_L _PK_L_(0x0C, 0x79) ++#define REG_SC_BK0C_79_H _PK_H_(0x0C, 0x79) ++#define REG_SC_BK0C_7A_L _PK_L_(0x0C, 0x7A) ++#define REG_SC_BK0C_7A_H _PK_H_(0x0C, 0x7A) ++#define REG_SC_BK0C_7B_L _PK_L_(0x0C, 0x7B) ++#define REG_SC_BK0C_7B_H _PK_H_(0x0C, 0x7B) ++#define REG_SC_BK0C_7C_L _PK_L_(0x0C, 0x7C) ++#define REG_SC_BK0C_7C_H _PK_H_(0x0C, 0x7C) ++#define REG_SC_BK0C_7D_L _PK_L_(0x0C, 0x7D) ++#define REG_SC_BK0C_7D_H _PK_H_(0x0C, 0x7D) ++#define REG_SC_BK0C_7E_L _PK_L_(0x0C, 0x7E) ++#define REG_SC_BK0C_7E_H _PK_H_(0x0C, 0x7E) ++#define REG_SC_BK0C_7F_L _PK_L_(0x0C, 0x7F) ++#define REG_SC_BK0C_7F_H _PK_H_(0x0C, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0D_00_L _PK_L_(0x0D, 0x00) ++#define REG_SC_BK0D_00_H _PK_H_(0x0D, 0x00) ++#define REG_SC_BK0D_01_L _PK_L_(0x0D, 0x01) ++#define REG_SC_BK0D_01_H _PK_H_(0x0D, 0x01) ++#define REG_SC_BK0D_02_L _PK_L_(0x0D, 0x02) ++#define REG_SC_BK0D_02_H _PK_H_(0x0D, 0x02) ++#define REG_SC_BK0D_03_L _PK_L_(0x0D, 0x03) ++#define REG_SC_BK0D_03_H _PK_H_(0x0D, 0x03) ++#define REG_SC_BK0D_04_L _PK_L_(0x0D, 0x04) ++#define REG_SC_BK0D_04_H _PK_H_(0x0D, 0x04) ++#define REG_SC_BK0D_05_L _PK_L_(0x0D, 0x05) ++#define REG_SC_BK0D_05_H _PK_H_(0x0D, 0x05) ++#define REG_SC_BK0D_06_L _PK_L_(0x0D, 0x06) ++#define REG_SC_BK0D_06_H _PK_H_(0x0D, 0x06) ++#define REG_SC_BK0D_07_L _PK_L_(0x0D, 0x07) ++#define REG_SC_BK0D_07_H _PK_H_(0x0D, 0x07) ++#define REG_SC_BK0D_08_L _PK_L_(0x0D, 0x08) ++#define REG_SC_BK0D_08_H _PK_H_(0x0D, 0x08) ++#define REG_SC_BK0D_09_L _PK_L_(0x0D, 0x09) ++#define REG_SC_BK0D_09_H _PK_H_(0x0D, 0x09) ++#define REG_SC_BK0D_0A_L _PK_L_(0x0D, 0x0A) ++#define REG_SC_BK0D_0A_H _PK_H_(0x0D, 0x0A) ++#define REG_SC_BK0D_0B_L _PK_L_(0x0D, 0x0B) ++#define REG_SC_BK0D_0B_H _PK_H_(0x0D, 0x0B) ++#define REG_SC_BK0D_0C_L _PK_L_(0x0D, 0x0C) ++#define REG_SC_BK0D_0C_H _PK_H_(0x0D, 0x0C) ++#define REG_SC_BK0D_0D_L _PK_L_(0x0D, 0x0D) ++#define REG_SC_BK0D_0D_H _PK_H_(0x0D, 0x0D) ++#define REG_SC_BK0D_0E_L _PK_L_(0x0D, 0x0E) ++#define REG_SC_BK0D_0E_H _PK_H_(0x0D, 0x0E) ++#define REG_SC_BK0D_0F_L _PK_L_(0x0D, 0x0F) ++#define REG_SC_BK0D_0F_H _PK_H_(0x0D, 0x0F) ++#define REG_SC_BK0D_10_L _PK_L_(0x0D, 0x10) ++#define REG_SC_BK0D_10_H _PK_H_(0x0D, 0x10) ++#define REG_SC_BK0D_11_L _PK_L_(0x0D, 0x11) ++#define REG_SC_BK0D_11_H _PK_H_(0x0D, 0x11) ++#define REG_SC_BK0D_12_L _PK_L_(0x0D, 0x12) ++#define REG_SC_BK0D_12_H _PK_H_(0x0D, 0x12) ++#define REG_SC_BK0D_13_L _PK_L_(0x0D, 0x13) ++#define REG_SC_BK0D_13_H _PK_H_(0x0D, 0x13) ++#define REG_SC_BK0D_14_L _PK_L_(0x0D, 0x14) ++#define REG_SC_BK0D_14_H _PK_H_(0x0D, 0x14) ++#define REG_SC_BK0D_15_L _PK_L_(0x0D, 0x15) ++#define REG_SC_BK0D_15_H _PK_H_(0x0D, 0x15) ++#define REG_SC_BK0D_16_L _PK_L_(0x0D, 0x16) ++#define REG_SC_BK0D_16_H _PK_H_(0x0D, 0x16) ++#define REG_SC_BK0D_17_L _PK_L_(0x0D, 0x17) ++#define REG_SC_BK0D_17_H _PK_H_(0x0D, 0x17) ++#define REG_SC_BK0D_18_L _PK_L_(0x0D, 0x18) ++#define REG_SC_BK0D_18_H _PK_H_(0x0D, 0x18) ++#define REG_SC_BK0D_19_L _PK_L_(0x0D, 0x19) ++#define REG_SC_BK0D_19_H _PK_H_(0x0D, 0x19) ++#define REG_SC_BK0D_1A_L _PK_L_(0x0D, 0x1A) ++#define REG_SC_BK0D_1A_H _PK_H_(0x0D, 0x1A) ++#define REG_SC_BK0D_1B_L _PK_L_(0x0D, 0x1B) ++#define REG_SC_BK0D_1B_H _PK_H_(0x0D, 0x1B) ++#define REG_SC_BK0D_1C_L _PK_L_(0x0D, 0x1C) ++#define REG_SC_BK0D_1C_H _PK_H_(0x0D, 0x1C) ++#define REG_SC_BK0D_1D_L _PK_L_(0x0D, 0x1D) ++#define REG_SC_BK0D_1D_H _PK_H_(0x0D, 0x1D) ++#define REG_SC_BK0D_1E_L _PK_L_(0x0D, 0x1E) ++#define REG_SC_BK0D_1E_H _PK_H_(0x0D, 0x1E) ++#define REG_SC_BK0D_1F_L _PK_L_(0x0D, 0x1F) ++#define REG_SC_BK0D_1F_H _PK_H_(0x0D, 0x1F) ++#define REG_SC_BK0D_20_L _PK_L_(0x0D, 0x20) ++#define REG_SC_BK0D_20_H _PK_H_(0x0D, 0x20) ++#define REG_SC_BK0D_21_L _PK_L_(0x0D, 0x21) ++#define REG_SC_BK0D_21_H _PK_H_(0x0D, 0x21) ++#define REG_SC_BK0D_22_L _PK_L_(0x0D, 0x22) ++#define REG_SC_BK0D_22_H _PK_H_(0x0D, 0x22) ++#define REG_SC_BK0D_23_L _PK_L_(0x0D, 0x23) ++#define REG_SC_BK0D_23_H _PK_H_(0x0D, 0x23) ++#define REG_SC_BK0D_24_L _PK_L_(0x0D, 0x24) ++#define REG_SC_BK0D_24_H _PK_H_(0x0D, 0x24) ++#define REG_SC_BK0D_25_L _PK_L_(0x0D, 0x25) ++#define REG_SC_BK0D_25_H _PK_H_(0x0D, 0x25) ++#define REG_SC_BK0D_26_L _PK_L_(0x0D, 0x26) ++#define REG_SC_BK0D_26_H _PK_H_(0x0D, 0x26) ++#define REG_SC_BK0D_27_L _PK_L_(0x0D, 0x27) ++#define REG_SC_BK0D_27_H _PK_H_(0x0D, 0x27) ++#define REG_SC_BK0D_28_L _PK_L_(0x0D, 0x28) ++#define REG_SC_BK0D_28_H _PK_H_(0x0D, 0x28) ++#define REG_SC_BK0D_29_L _PK_L_(0x0D, 0x29) ++#define REG_SC_BK0D_29_H _PK_H_(0x0D, 0x29) ++#define REG_SC_BK0D_2A_L _PK_L_(0x0D, 0x2A) ++#define REG_SC_BK0D_2A_H _PK_H_(0x0D, 0x2A) ++#define REG_SC_BK0D_2B_L _PK_L_(0x0D, 0x2B) ++#define REG_SC_BK0D_2B_H _PK_H_(0x0D, 0x2B) ++#define REG_SC_BK0D_2C_L _PK_L_(0x0D, 0x2C) ++#define REG_SC_BK0D_2C_H _PK_H_(0x0D, 0x2C) ++#define REG_SC_BK0D_2D_L _PK_L_(0x0D, 0x2D) ++#define REG_SC_BK0D_2D_H _PK_H_(0x0D, 0x2D) ++#define REG_SC_BK0D_2E_L _PK_L_(0x0D, 0x2E) ++#define REG_SC_BK0D_2E_H _PK_H_(0x0D, 0x2E) ++#define REG_SC_BK0D_2F_L _PK_L_(0x0D, 0x2F) ++#define REG_SC_BK0D_2F_H _PK_H_(0x0D, 0x2F) ++#define REG_SC_BK0D_30_L _PK_L_(0x0D, 0x30) ++#define REG_SC_BK0D_30_H _PK_H_(0x0D, 0x30) ++#define REG_SC_BK0D_31_L _PK_L_(0x0D, 0x31) ++#define REG_SC_BK0D_31_H _PK_H_(0x0D, 0x31) ++#define REG_SC_BK0D_32_L _PK_L_(0x0D, 0x32) ++#define REG_SC_BK0D_32_H _PK_H_(0x0D, 0x32) ++#define REG_SC_BK0D_33_L _PK_L_(0x0D, 0x33) ++#define REG_SC_BK0D_33_H _PK_H_(0x0D, 0x33) ++#define REG_SC_BK0D_34_L _PK_L_(0x0D, 0x34) ++#define REG_SC_BK0D_34_H _PK_H_(0x0D, 0x34) ++#define REG_SC_BK0D_35_L _PK_L_(0x0D, 0x35) ++#define REG_SC_BK0D_35_H _PK_H_(0x0D, 0x35) ++#define REG_SC_BK0D_36_L _PK_L_(0x0D, 0x36) ++#define REG_SC_BK0D_36_H _PK_H_(0x0D, 0x36) ++#define REG_SC_BK0D_37_L _PK_L_(0x0D, 0x37) ++#define REG_SC_BK0D_37_H _PK_H_(0x0D, 0x37) ++#define REG_SC_BK0D_38_L _PK_L_(0x0D, 0x38) ++#define REG_SC_BK0D_38_H _PK_H_(0x0D, 0x38) ++#define REG_SC_BK0D_39_L _PK_L_(0x0D, 0x39) ++#define REG_SC_BK0D_39_H _PK_H_(0x0D, 0x39) ++#define REG_SC_BK0D_3A_L _PK_L_(0x0D, 0x3A) ++#define REG_SC_BK0D_3A_H _PK_H_(0x0D, 0x3A) ++#define REG_SC_BK0D_3B_L _PK_L_(0x0D, 0x3B) ++#define REG_SC_BK0D_3B_H _PK_H_(0x0D, 0x3B) ++#define REG_SC_BK0D_3C_L _PK_L_(0x0D, 0x3C) ++#define REG_SC_BK0D_3C_H _PK_H_(0x0D, 0x3C) ++#define REG_SC_BK0D_3D_L _PK_L_(0x0D, 0x3D) ++#define REG_SC_BK0D_3D_H _PK_H_(0x0D, 0x3D) ++#define REG_SC_BK0D_3E_L _PK_L_(0x0D, 0x3E) ++#define REG_SC_BK0D_3E_H _PK_H_(0x0D, 0x3E) ++#define REG_SC_BK0D_3F_L _PK_L_(0x0D, 0x3F) ++#define REG_SC_BK0D_3F_H _PK_H_(0x0D, 0x3F) ++#define REG_SC_BK0D_40_L _PK_L_(0x0D, 0x40) ++#define REG_SC_BK0D_40_H _PK_H_(0x0D, 0x40) ++#define REG_SC_BK0D_41_L _PK_L_(0x0D, 0x41) ++#define REG_SC_BK0D_41_H _PK_H_(0x0D, 0x41) ++#define REG_SC_BK0D_42_L _PK_L_(0x0D, 0x42) ++#define REG_SC_BK0D_42_H _PK_H_(0x0D, 0x42) ++#define REG_SC_BK0D_43_L _PK_L_(0x0D, 0x43) ++#define REG_SC_BK0D_43_H _PK_H_(0x0D, 0x43) ++#define REG_SC_BK0D_44_L _PK_L_(0x0D, 0x44) ++#define REG_SC_BK0D_44_H _PK_H_(0x0D, 0x44) ++#define REG_SC_BK0D_45_L _PK_L_(0x0D, 0x45) ++#define REG_SC_BK0D_45_H _PK_H_(0x0D, 0x45) ++#define REG_SC_BK0D_46_L _PK_L_(0x0D, 0x46) ++#define REG_SC_BK0D_46_H _PK_H_(0x0D, 0x46) ++#define REG_SC_BK0D_47_L _PK_L_(0x0D, 0x47) ++#define REG_SC_BK0D_47_H _PK_H_(0x0D, 0x47) ++#define REG_SC_BK0D_48_L _PK_L_(0x0D, 0x48) ++#define REG_SC_BK0D_48_H _PK_H_(0x0D, 0x48) ++#define REG_SC_BK0D_49_L _PK_L_(0x0D, 0x49) ++#define REG_SC_BK0D_49_H _PK_H_(0x0D, 0x49) ++#define REG_SC_BK0D_4A_L _PK_L_(0x0D, 0x4A) ++#define REG_SC_BK0D_4A_H _PK_H_(0x0D, 0x4A) ++#define REG_SC_BK0D_4B_L _PK_L_(0x0D, 0x4B) ++#define REG_SC_BK0D_4B_H _PK_H_(0x0D, 0x4B) ++#define REG_SC_BK0D_4C_L _PK_L_(0x0D, 0x4C) ++#define REG_SC_BK0D_4C_H _PK_H_(0x0D, 0x4C) ++#define REG_SC_BK0D_4D_L _PK_L_(0x0D, 0x4D) ++#define REG_SC_BK0D_4D_H _PK_H_(0x0D, 0x4D) ++#define REG_SC_BK0D_4E_L _PK_L_(0x0D, 0x4E) ++#define REG_SC_BK0D_4E_H _PK_H_(0x0D, 0x4E) ++#define REG_SC_BK0D_4F_L _PK_L_(0x0D, 0x4F) ++#define REG_SC_BK0D_4F_H _PK_H_(0x0D, 0x4F) ++#define REG_SC_BK0D_50_L _PK_L_(0x0D, 0x50) ++#define REG_SC_BK0D_50_H _PK_H_(0x0D, 0x50) ++#define REG_SC_BK0D_51_L _PK_L_(0x0D, 0x51) ++#define REG_SC_BK0D_51_H _PK_H_(0x0D, 0x51) ++#define REG_SC_BK0D_52_L _PK_L_(0x0D, 0x52) ++#define REG_SC_BK0D_52_H _PK_H_(0x0D, 0x52) ++#define REG_SC_BK0D_53_L _PK_L_(0x0D, 0x53) ++#define REG_SC_BK0D_53_H _PK_H_(0x0D, 0x53) ++#define REG_SC_BK0D_54_L _PK_L_(0x0D, 0x54) ++#define REG_SC_BK0D_54_H _PK_H_(0x0D, 0x54) ++#define REG_SC_BK0D_55_L _PK_L_(0x0D, 0x55) ++#define REG_SC_BK0D_55_H _PK_H_(0x0D, 0x55) ++#define REG_SC_BK0D_56_L _PK_L_(0x0D, 0x56) ++#define REG_SC_BK0D_56_H _PK_H_(0x0D, 0x56) ++#define REG_SC_BK0D_57_L _PK_L_(0x0D, 0x57) ++#define REG_SC_BK0D_57_H _PK_H_(0x0D, 0x57) ++#define REG_SC_BK0D_58_L _PK_L_(0x0D, 0x58) ++#define REG_SC_BK0D_58_H _PK_H_(0x0D, 0x58) ++#define REG_SC_BK0D_59_L _PK_L_(0x0D, 0x59) ++#define REG_SC_BK0D_59_H _PK_H_(0x0D, 0x59) ++#define REG_SC_BK0D_5A_L _PK_L_(0x0D, 0x5A) ++#define REG_SC_BK0D_5A_H _PK_H_(0x0D, 0x5A) ++#define REG_SC_BK0D_5B_L _PK_L_(0x0D, 0x5B) ++#define REG_SC_BK0D_5B_H _PK_H_(0x0D, 0x5B) ++#define REG_SC_BK0D_5C_L _PK_L_(0x0D, 0x5C) ++#define REG_SC_BK0D_5C_H _PK_H_(0x0D, 0x5C) ++#define REG_SC_BK0D_5D_L _PK_L_(0x0D, 0x5D) ++#define REG_SC_BK0D_5D_H _PK_H_(0x0D, 0x5D) ++#define REG_SC_BK0D_5E_L _PK_L_(0x0D, 0x5E) ++#define REG_SC_BK0D_5E_H _PK_H_(0x0D, 0x5E) ++#define REG_SC_BK0D_5F_L _PK_L_(0x0D, 0x5F) ++#define REG_SC_BK0D_5F_H _PK_H_(0x0D, 0x5F) ++#define REG_SC_BK0D_60_L _PK_L_(0x0D, 0x60) ++#define REG_SC_BK0D_60_H _PK_H_(0x0D, 0x60) ++#define REG_SC_BK0D_61_L _PK_L_(0x0D, 0x61) ++#define REG_SC_BK0D_61_H _PK_H_(0x0D, 0x61) ++#define REG_SC_BK0D_62_L _PK_L_(0x0D, 0x62) ++#define REG_SC_BK0D_62_H _PK_H_(0x0D, 0x62) ++#define REG_SC_BK0D_63_L _PK_L_(0x0D, 0x63) ++#define REG_SC_BK0D_63_H _PK_H_(0x0D, 0x63) ++#define REG_SC_BK0D_64_L _PK_L_(0x0D, 0x64) ++#define REG_SC_BK0D_64_H _PK_H_(0x0D, 0x64) ++#define REG_SC_BK0D_65_L _PK_L_(0x0D, 0x65) ++#define REG_SC_BK0D_65_H _PK_H_(0x0D, 0x65) ++#define REG_SC_BK0D_66_L _PK_L_(0x0D, 0x66) ++#define REG_SC_BK0D_66_H _PK_H_(0x0D, 0x66) ++#define REG_SC_BK0D_67_L _PK_L_(0x0D, 0x67) ++#define REG_SC_BK0D_67_H _PK_H_(0x0D, 0x67) ++#define REG_SC_BK0D_68_L _PK_L_(0x0D, 0x68) ++#define REG_SC_BK0D_68_H _PK_H_(0x0D, 0x68) ++#define REG_SC_BK0D_69_L _PK_L_(0x0D, 0x69) ++#define REG_SC_BK0D_69_H _PK_H_(0x0D, 0x69) ++#define REG_SC_BK0D_6A_L _PK_L_(0x0D, 0x6A) ++#define REG_SC_BK0D_6A_H _PK_H_(0x0D, 0x6A) ++#define REG_SC_BK0D_6B_L _PK_L_(0x0D, 0x6B) ++#define REG_SC_BK0D_6B_H _PK_H_(0x0D, 0x6B) ++#define REG_SC_BK0D_6C_L _PK_L_(0x0D, 0x6C) ++#define REG_SC_BK0D_6C_H _PK_H_(0x0D, 0x6C) ++#define REG_SC_BK0D_6D_L _PK_L_(0x0D, 0x6D) ++#define REG_SC_BK0D_6D_H _PK_H_(0x0D, 0x6D) ++#define REG_SC_BK0D_6E_L _PK_L_(0x0D, 0x6E) ++#define REG_SC_BK0D_6E_H _PK_H_(0x0D, 0x6E) ++#define REG_SC_BK0D_6F_L _PK_L_(0x0D, 0x6F) ++#define REG_SC_BK0D_6F_H _PK_H_(0x0D, 0x6F) ++#define REG_SC_BK0D_70_L _PK_L_(0x0D, 0x70) ++#define REG_SC_BK0D_70_H _PK_H_(0x0D, 0x70) ++#define REG_SC_BK0D_71_L _PK_L_(0x0D, 0x71) ++#define REG_SC_BK0D_71_H _PK_H_(0x0D, 0x71) ++#define REG_SC_BK0D_72_L _PK_L_(0x0D, 0x72) ++#define REG_SC_BK0D_72_H _PK_H_(0x0D, 0x72) ++#define REG_SC_BK0D_73_L _PK_L_(0x0D, 0x73) ++#define REG_SC_BK0D_73_H _PK_H_(0x0D, 0x73) ++#define REG_SC_BK0D_74_L _PK_L_(0x0D, 0x74) ++#define REG_SC_BK0D_74_H _PK_H_(0x0D, 0x74) ++#define REG_SC_BK0D_75_L _PK_L_(0x0D, 0x75) ++#define REG_SC_BK0D_75_H _PK_H_(0x0D, 0x75) ++#define REG_SC_BK0D_76_L _PK_L_(0x0D, 0x76) ++#define REG_SC_BK0D_76_H _PK_H_(0x0D, 0x76) ++#define REG_SC_BK0D_77_L _PK_L_(0x0D, 0x77) ++#define REG_SC_BK0D_77_H _PK_H_(0x0D, 0x77) ++#define REG_SC_BK0D_78_L _PK_L_(0x0D, 0x78) ++#define REG_SC_BK0D_78_H _PK_H_(0x0D, 0x78) ++#define REG_SC_BK0D_79_L _PK_L_(0x0D, 0x79) ++#define REG_SC_BK0D_79_H _PK_H_(0x0D, 0x79) ++#define REG_SC_BK0D_7A_L _PK_L_(0x0D, 0x7A) ++#define REG_SC_BK0D_7A_H _PK_H_(0x0D, 0x7A) ++#define REG_SC_BK0D_7B_L _PK_L_(0x0D, 0x7B) ++#define REG_SC_BK0D_7B_H _PK_H_(0x0D, 0x7B) ++#define REG_SC_BK0D_7C_L _PK_L_(0x0D, 0x7C) ++#define REG_SC_BK0D_7C_H _PK_H_(0x0D, 0x7C) ++#define REG_SC_BK0D_7D_L _PK_L_(0x0D, 0x7D) ++#define REG_SC_BK0D_7D_H _PK_H_(0x0D, 0x7D) ++#define REG_SC_BK0D_7E_L _PK_L_(0x0D, 0x7E) ++#define REG_SC_BK0D_7E_H _PK_H_(0x0D, 0x7E) ++#define REG_SC_BK0D_7F_L _PK_L_(0x0D, 0x7F) ++#define REG_SC_BK0D_7F_H _PK_H_(0x0D, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0E_00_L _PK_L_(0x0E, 0x00) ++#define REG_SC_BK0E_00_H _PK_H_(0x0E, 0x00) ++#define REG_SC_BK0E_01_L _PK_L_(0x0E, 0x01) ++#define REG_SC_BK0E_01_H _PK_H_(0x0E, 0x01) ++#define REG_SC_BK0E_02_L _PK_L_(0x0E, 0x02) ++#define REG_SC_BK0E_02_H _PK_H_(0x0E, 0x02) ++#define REG_SC_BK0E_03_L _PK_L_(0x0E, 0x03) ++#define REG_SC_BK0E_03_H _PK_H_(0x0E, 0x03) ++#define REG_SC_BK0E_04_L _PK_L_(0x0E, 0x04) ++#define REG_SC_BK0E_04_H _PK_H_(0x0E, 0x04) ++#define REG_SC_BK0E_05_L _PK_L_(0x0E, 0x05) ++#define REG_SC_BK0E_05_H _PK_H_(0x0E, 0x05) ++#define REG_SC_BK0E_06_L _PK_L_(0x0E, 0x06) ++#define REG_SC_BK0E_06_H _PK_H_(0x0E, 0x06) ++#define REG_SC_BK0E_07_L _PK_L_(0x0E, 0x07) ++#define REG_SC_BK0E_07_H _PK_H_(0x0E, 0x07) ++#define REG_SC_BK0E_08_L _PK_L_(0x0E, 0x08) ++#define REG_SC_BK0E_08_H _PK_H_(0x0E, 0x08) ++#define REG_SC_BK0E_09_L _PK_L_(0x0E, 0x09) ++#define REG_SC_BK0E_09_H _PK_H_(0x0E, 0x09) ++#define REG_SC_BK0E_0A_L _PK_L_(0x0E, 0x0A) ++#define REG_SC_BK0E_0A_H _PK_H_(0x0E, 0x0A) ++#define REG_SC_BK0E_0B_L _PK_L_(0x0E, 0x0B) ++#define REG_SC_BK0E_0B_H _PK_H_(0x0E, 0x0B) ++#define REG_SC_BK0E_0C_L _PK_L_(0x0E, 0x0C) ++#define REG_SC_BK0E_0C_H _PK_H_(0x0E, 0x0C) ++#define REG_SC_BK0E_0D_L _PK_L_(0x0E, 0x0D) ++#define REG_SC_BK0E_0D_H _PK_H_(0x0E, 0x0D) ++#define REG_SC_BK0E_0E_L _PK_L_(0x0E, 0x0E) ++#define REG_SC_BK0E_0E_H _PK_H_(0x0E, 0x0E) ++#define REG_SC_BK0E_0F_L _PK_L_(0x0E, 0x0F) ++#define REG_SC_BK0E_0F_H _PK_H_(0x0E, 0x0F) ++#define REG_SC_BK0E_10_L _PK_L_(0x0E, 0x10) ++#define REG_SC_BK0E_10_H _PK_H_(0x0E, 0x10) ++#define REG_SC_BK0E_11_L _PK_L_(0x0E, 0x11) ++#define REG_SC_BK0E_11_H _PK_H_(0x0E, 0x11) ++#define REG_SC_BK0E_12_L _PK_L_(0x0E, 0x12) ++#define REG_SC_BK0E_12_H _PK_H_(0x0E, 0x12) ++#define REG_SC_BK0E_13_L _PK_L_(0x0E, 0x13) ++#define REG_SC_BK0E_13_H _PK_H_(0x0E, 0x13) ++#define REG_SC_BK0E_14_L _PK_L_(0x0E, 0x14) ++#define REG_SC_BK0E_14_H _PK_H_(0x0E, 0x14) ++#define REG_SC_BK0E_15_L _PK_L_(0x0E, 0x15) ++#define REG_SC_BK0E_15_H _PK_H_(0x0E, 0x15) ++#define REG_SC_BK0E_16_L _PK_L_(0x0E, 0x16) ++#define REG_SC_BK0E_16_H _PK_H_(0x0E, 0x16) ++#define REG_SC_BK0E_17_L _PK_L_(0x0E, 0x17) ++#define REG_SC_BK0E_17_H _PK_H_(0x0E, 0x17) ++#define REG_SC_BK0E_18_L _PK_L_(0x0E, 0x18) ++#define REG_SC_BK0E_18_H _PK_H_(0x0E, 0x18) ++#define REG_SC_BK0E_19_L _PK_L_(0x0E, 0x19) ++#define REG_SC_BK0E_19_H _PK_H_(0x0E, 0x19) ++#define REG_SC_BK0E_1A_L _PK_L_(0x0E, 0x1A) ++#define REG_SC_BK0E_1A_H _PK_H_(0x0E, 0x1A) ++#define REG_SC_BK0E_1B_L _PK_L_(0x0E, 0x1B) ++#define REG_SC_BK0E_1B_H _PK_H_(0x0E, 0x1B) ++#define REG_SC_BK0E_1C_L _PK_L_(0x0E, 0x1C) ++#define REG_SC_BK0E_1C_H _PK_H_(0x0E, 0x1C) ++#define REG_SC_BK0E_1D_L _PK_L_(0x0E, 0x1D) ++#define REG_SC_BK0E_1D_H _PK_H_(0x0E, 0x1D) ++#define REG_SC_BK0E_1E_L _PK_L_(0x0E, 0x1E) ++#define REG_SC_BK0E_1E_H _PK_H_(0x0E, 0x1E) ++#define REG_SC_BK0E_1F_L _PK_L_(0x0E, 0x1F) ++#define REG_SC_BK0E_1F_H _PK_H_(0x0E, 0x1F) ++#define REG_SC_BK0E_20_L _PK_L_(0x0E, 0x20) ++#define REG_SC_BK0E_20_H _PK_H_(0x0E, 0x20) ++#define REG_SC_BK0E_21_L _PK_L_(0x0E, 0x21) ++#define REG_SC_BK0E_21_H _PK_H_(0x0E, 0x21) ++#define REG_SC_BK0E_22_L _PK_L_(0x0E, 0x22) ++#define REG_SC_BK0E_22_H _PK_H_(0x0E, 0x22) ++#define REG_SC_BK0E_23_L _PK_L_(0x0E, 0x23) ++#define REG_SC_BK0E_23_H _PK_H_(0x0E, 0x23) ++#define REG_SC_BK0E_24_L _PK_L_(0x0E, 0x24) ++#define REG_SC_BK0E_24_H _PK_H_(0x0E, 0x24) ++#define REG_SC_BK0E_25_L _PK_L_(0x0E, 0x25) ++#define REG_SC_BK0E_25_H _PK_H_(0x0E, 0x25) ++#define REG_SC_BK0E_26_L _PK_L_(0x0E, 0x26) ++#define REG_SC_BK0E_26_H _PK_H_(0x0E, 0x26) ++#define REG_SC_BK0E_27_L _PK_L_(0x0E, 0x27) ++#define REG_SC_BK0E_27_H _PK_H_(0x0E, 0x27) ++#define REG_SC_BK0E_28_L _PK_L_(0x0E, 0x28) ++#define REG_SC_BK0E_28_H _PK_H_(0x0E, 0x28) ++#define REG_SC_BK0E_29_L _PK_L_(0x0E, 0x29) ++#define REG_SC_BK0E_29_H _PK_H_(0x0E, 0x29) ++#define REG_SC_BK0E_2A_L _PK_L_(0x0E, 0x2A) ++#define REG_SC_BK0E_2A_H _PK_H_(0x0E, 0x2A) ++#define REG_SC_BK0E_2B_L _PK_L_(0x0E, 0x2B) ++#define REG_SC_BK0E_2B_H _PK_H_(0x0E, 0x2B) ++#define REG_SC_BK0E_2C_L _PK_L_(0x0E, 0x2C) ++#define REG_SC_BK0E_2C_H _PK_H_(0x0E, 0x2C) ++#define REG_SC_BK0E_2D_L _PK_L_(0x0E, 0x2D) ++#define REG_SC_BK0E_2D_H _PK_H_(0x0E, 0x2D) ++#define REG_SC_BK0E_2E_L _PK_L_(0x0E, 0x2E) ++#define REG_SC_BK0E_2E_H _PK_H_(0x0E, 0x2E) ++#define REG_SC_BK0E_2F_L _PK_L_(0x0E, 0x2F) ++#define REG_SC_BK0E_2F_H _PK_H_(0x0E, 0x2F) ++#define REG_SC_BK0E_30_L _PK_L_(0x0E, 0x30) ++#define REG_SC_BK0E_30_H _PK_H_(0x0E, 0x30) ++#define REG_SC_BK0E_31_L _PK_L_(0x0E, 0x31) ++#define REG_SC_BK0E_31_H _PK_H_(0x0E, 0x31) ++#define REG_SC_BK0E_32_L _PK_L_(0x0E, 0x32) ++#define REG_SC_BK0E_32_H _PK_H_(0x0E, 0x32) ++#define REG_SC_BK0E_33_L _PK_L_(0x0E, 0x33) ++#define REG_SC_BK0E_33_H _PK_H_(0x0E, 0x33) ++#define REG_SC_BK0E_34_L _PK_L_(0x0E, 0x34) ++#define REG_SC_BK0E_34_H _PK_H_(0x0E, 0x34) ++#define REG_SC_BK0E_35_L _PK_L_(0x0E, 0x35) ++#define REG_SC_BK0E_35_H _PK_H_(0x0E, 0x35) ++#define REG_SC_BK0E_36_L _PK_L_(0x0E, 0x36) ++#define REG_SC_BK0E_36_H _PK_H_(0x0E, 0x36) ++#define REG_SC_BK0E_37_L _PK_L_(0x0E, 0x37) ++#define REG_SC_BK0E_37_H _PK_H_(0x0E, 0x37) ++#define REG_SC_BK0E_38_L _PK_L_(0x0E, 0x38) ++#define REG_SC_BK0E_38_H _PK_H_(0x0E, 0x38) ++#define REG_SC_BK0E_39_L _PK_L_(0x0E, 0x39) ++#define REG_SC_BK0E_39_H _PK_H_(0x0E, 0x39) ++#define REG_SC_BK0E_3A_L _PK_L_(0x0E, 0x3A) ++#define REG_SC_BK0E_3A_H _PK_H_(0x0E, 0x3A) ++#define REG_SC_BK0E_3B_L _PK_L_(0x0E, 0x3B) ++#define REG_SC_BK0E_3B_H _PK_H_(0x0E, 0x3B) ++#define REG_SC_BK0E_3C_L _PK_L_(0x0E, 0x3C) ++#define REG_SC_BK0E_3C_H _PK_H_(0x0E, 0x3C) ++#define REG_SC_BK0E_3D_L _PK_L_(0x0E, 0x3D) ++#define REG_SC_BK0E_3D_H _PK_H_(0x0E, 0x3D) ++#define REG_SC_BK0E_3E_L _PK_L_(0x0E, 0x3E) ++#define REG_SC_BK0E_3E_H _PK_H_(0x0E, 0x3E) ++#define REG_SC_BK0E_3F_L _PK_L_(0x0E, 0x3F) ++#define REG_SC_BK0E_3F_H _PK_H_(0x0E, 0x3F) ++#define REG_SC_BK0E_40_L _PK_L_(0x0E, 0x40) ++#define REG_SC_BK0E_40_H _PK_H_(0x0E, 0x40) ++#define REG_SC_BK0E_41_L _PK_L_(0x0E, 0x41) ++#define REG_SC_BK0E_41_H _PK_H_(0x0E, 0x41) ++#define REG_SC_BK0E_42_L _PK_L_(0x0E, 0x42) ++#define REG_SC_BK0E_42_H _PK_H_(0x0E, 0x42) ++#define REG_SC_BK0E_43_L _PK_L_(0x0E, 0x43) ++#define REG_SC_BK0E_43_H _PK_H_(0x0E, 0x43) ++#define REG_SC_BK0E_44_L _PK_L_(0x0E, 0x44) ++#define REG_SC_BK0E_44_H _PK_H_(0x0E, 0x44) ++#define REG_SC_BK0E_45_L _PK_L_(0x0E, 0x45) ++#define REG_SC_BK0E_45_H _PK_H_(0x0E, 0x45) ++#define REG_SC_BK0E_46_L _PK_L_(0x0E, 0x46) ++#define REG_SC_BK0E_46_H _PK_H_(0x0E, 0x46) ++#define REG_SC_BK0E_47_L _PK_L_(0x0E, 0x47) ++#define REG_SC_BK0E_47_H _PK_H_(0x0E, 0x47) ++#define REG_SC_BK0E_48_L _PK_L_(0x0E, 0x48) ++#define REG_SC_BK0E_48_H _PK_H_(0x0E, 0x48) ++#define REG_SC_BK0E_49_L _PK_L_(0x0E, 0x49) ++#define REG_SC_BK0E_49_H _PK_H_(0x0E, 0x49) ++#define REG_SC_BK0E_4A_L _PK_L_(0x0E, 0x4A) ++#define REG_SC_BK0E_4A_H _PK_H_(0x0E, 0x4A) ++#define REG_SC_BK0E_4B_L _PK_L_(0x0E, 0x4B) ++#define REG_SC_BK0E_4B_H _PK_H_(0x0E, 0x4B) ++#define REG_SC_BK0E_4C_L _PK_L_(0x0E, 0x4C) ++#define REG_SC_BK0E_4C_H _PK_H_(0x0E, 0x4C) ++#define REG_SC_BK0E_4D_L _PK_L_(0x0E, 0x4D) ++#define REG_SC_BK0E_4D_H _PK_H_(0x0E, 0x4D) ++#define REG_SC_BK0E_4E_L _PK_L_(0x0E, 0x4E) ++#define REG_SC_BK0E_4E_H _PK_H_(0x0E, 0x4E) ++#define REG_SC_BK0E_4F_L _PK_L_(0x0E, 0x4F) ++#define REG_SC_BK0E_4F_H _PK_H_(0x0E, 0x4F) ++#define REG_SC_BK0E_50_L _PK_L_(0x0E, 0x50) ++#define REG_SC_BK0E_50_H _PK_H_(0x0E, 0x50) ++#define REG_SC_BK0E_51_L _PK_L_(0x0E, 0x51) ++#define REG_SC_BK0E_51_H _PK_H_(0x0E, 0x51) ++#define REG_SC_BK0E_52_L _PK_L_(0x0E, 0x52) ++#define REG_SC_BK0E_52_H _PK_H_(0x0E, 0x52) ++#define REG_SC_BK0E_53_L _PK_L_(0x0E, 0x53) ++#define REG_SC_BK0E_53_H _PK_H_(0x0E, 0x53) ++#define REG_SC_BK0E_54_L _PK_L_(0x0E, 0x54) ++#define REG_SC_BK0E_54_H _PK_H_(0x0E, 0x54) ++#define REG_SC_BK0E_55_L _PK_L_(0x0E, 0x55) ++#define REG_SC_BK0E_55_H _PK_H_(0x0E, 0x55) ++#define REG_SC_BK0E_56_L _PK_L_(0x0E, 0x56) ++#define REG_SC_BK0E_56_H _PK_H_(0x0E, 0x56) ++#define REG_SC_BK0E_57_L _PK_L_(0x0E, 0x57) ++#define REG_SC_BK0E_57_H _PK_H_(0x0E, 0x57) ++#define REG_SC_BK0E_58_L _PK_L_(0x0E, 0x58) ++#define REG_SC_BK0E_58_H _PK_H_(0x0E, 0x58) ++#define REG_SC_BK0E_59_L _PK_L_(0x0E, 0x59) ++#define REG_SC_BK0E_59_H _PK_H_(0x0E, 0x59) ++#define REG_SC_BK0E_5A_L _PK_L_(0x0E, 0x5A) ++#define REG_SC_BK0E_5A_H _PK_H_(0x0E, 0x5A) ++#define REG_SC_BK0E_5B_L _PK_L_(0x0E, 0x5B) ++#define REG_SC_BK0E_5B_H _PK_H_(0x0E, 0x5B) ++#define REG_SC_BK0E_5C_L _PK_L_(0x0E, 0x5C) ++#define REG_SC_BK0E_5C_H _PK_H_(0x0E, 0x5C) ++#define REG_SC_BK0E_5D_L _PK_L_(0x0E, 0x5D) ++#define REG_SC_BK0E_5D_H _PK_H_(0x0E, 0x5D) ++#define REG_SC_BK0E_5E_L _PK_L_(0x0E, 0x5E) ++#define REG_SC_BK0E_5E_H _PK_H_(0x0E, 0x5E) ++#define REG_SC_BK0E_5F_L _PK_L_(0x0E, 0x5F) ++#define REG_SC_BK0E_5F_H _PK_H_(0x0E, 0x5F) ++#define REG_SC_BK0E_60_L _PK_L_(0x0E, 0x60) ++#define REG_SC_BK0E_60_H _PK_H_(0x0E, 0x60) ++#define REG_SC_BK0E_61_L _PK_L_(0x0E, 0x61) ++#define REG_SC_BK0E_61_H _PK_H_(0x0E, 0x61) ++#define REG_SC_BK0E_62_L _PK_L_(0x0E, 0x62) ++#define REG_SC_BK0E_62_H _PK_H_(0x0E, 0x62) ++#define REG_SC_BK0E_63_L _PK_L_(0x0E, 0x63) ++#define REG_SC_BK0E_63_H _PK_H_(0x0E, 0x63) ++#define REG_SC_BK0E_64_L _PK_L_(0x0E, 0x64) ++#define REG_SC_BK0E_64_H _PK_H_(0x0E, 0x64) ++#define REG_SC_BK0E_65_L _PK_L_(0x0E, 0x65) ++#define REG_SC_BK0E_65_H _PK_H_(0x0E, 0x65) ++#define REG_SC_BK0E_66_L _PK_L_(0x0E, 0x66) ++#define REG_SC_BK0E_66_H _PK_H_(0x0E, 0x66) ++#define REG_SC_BK0E_67_L _PK_L_(0x0E, 0x67) ++#define REG_SC_BK0E_67_H _PK_H_(0x0E, 0x67) ++#define REG_SC_BK0E_68_L _PK_L_(0x0E, 0x68) ++#define REG_SC_BK0E_68_H _PK_H_(0x0E, 0x68) ++#define REG_SC_BK0E_69_L _PK_L_(0x0E, 0x69) ++#define REG_SC_BK0E_69_H _PK_H_(0x0E, 0x69) ++#define REG_SC_BK0E_6A_L _PK_L_(0x0E, 0x6A) ++#define REG_SC_BK0E_6A_H _PK_H_(0x0E, 0x6A) ++#define REG_SC_BK0E_6B_L _PK_L_(0x0E, 0x6B) ++#define REG_SC_BK0E_6B_H _PK_H_(0x0E, 0x6B) ++#define REG_SC_BK0E_6C_L _PK_L_(0x0E, 0x6C) ++#define REG_SC_BK0E_6C_H _PK_H_(0x0E, 0x6C) ++#define REG_SC_BK0E_6D_L _PK_L_(0x0E, 0x6D) ++#define REG_SC_BK0E_6D_H _PK_H_(0x0E, 0x6D) ++#define REG_SC_BK0E_6E_L _PK_L_(0x0E, 0x6E) ++#define REG_SC_BK0E_6E_H _PK_H_(0x0E, 0x6E) ++#define REG_SC_BK0E_6F_L _PK_L_(0x0E, 0x6F) ++#define REG_SC_BK0E_6F_H _PK_H_(0x0E, 0x6F) ++#define REG_SC_BK0E_70_L _PK_L_(0x0E, 0x70) ++#define REG_SC_BK0E_70_H _PK_H_(0x0E, 0x70) ++#define REG_SC_BK0E_71_L _PK_L_(0x0E, 0x71) ++#define REG_SC_BK0E_71_H _PK_H_(0x0E, 0x71) ++#define REG_SC_BK0E_72_L _PK_L_(0x0E, 0x72) ++#define REG_SC_BK0E_72_H _PK_H_(0x0E, 0x72) ++#define REG_SC_BK0E_73_L _PK_L_(0x0E, 0x73) ++#define REG_SC_BK0E_73_H _PK_H_(0x0E, 0x73) ++#define REG_SC_BK0E_74_L _PK_L_(0x0E, 0x74) ++#define REG_SC_BK0E_74_H _PK_H_(0x0E, 0x74) ++#define REG_SC_BK0E_75_L _PK_L_(0x0E, 0x75) ++#define REG_SC_BK0E_75_H _PK_H_(0x0E, 0x75) ++#define REG_SC_BK0E_76_L _PK_L_(0x0E, 0x76) ++#define REG_SC_BK0E_76_H _PK_H_(0x0E, 0x76) ++#define REG_SC_BK0E_77_L _PK_L_(0x0E, 0x77) ++#define REG_SC_BK0E_77_H _PK_H_(0x0E, 0x77) ++#define REG_SC_BK0E_78_L _PK_L_(0x0E, 0x78) ++#define REG_SC_BK0E_78_H _PK_H_(0x0E, 0x78) ++#define REG_SC_BK0E_79_L _PK_L_(0x0E, 0x79) ++#define REG_SC_BK0E_79_H _PK_H_(0x0E, 0x79) ++#define REG_SC_BK0E_7A_L _PK_L_(0x0E, 0x7A) ++#define REG_SC_BK0E_7A_H _PK_H_(0x0E, 0x7A) ++#define REG_SC_BK0E_7B_L _PK_L_(0x0E, 0x7B) ++#define REG_SC_BK0E_7B_H _PK_H_(0x0E, 0x7B) ++#define REG_SC_BK0E_7C_L _PK_L_(0x0E, 0x7C) ++#define REG_SC_BK0E_7C_H _PK_H_(0x0E, 0x7C) ++#define REG_SC_BK0E_7D_L _PK_L_(0x0E, 0x7D) ++#define REG_SC_BK0E_7D_H _PK_H_(0x0E, 0x7D) ++#define REG_SC_BK0E_7E_L _PK_L_(0x0E, 0x7E) ++#define REG_SC_BK0E_7E_H _PK_H_(0x0E, 0x7E) ++#define REG_SC_BK0E_7F_L _PK_L_(0x0E, 0x7F) ++#define REG_SC_BK0E_7F_H _PK_H_(0x0E, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK0F_00_L _PK_L_(0x0F, 0x00) ++#define REG_SC_BK0F_00_H _PK_H_(0x0F, 0x00) ++#define REG_SC_BK0F_01_L _PK_L_(0x0F, 0x01) ++#define REG_SC_BK0F_01_H _PK_H_(0x0F, 0x01) ++#define REG_SC_BK0F_02_L _PK_L_(0x0F, 0x02) ++#define REG_SC_BK0F_02_H _PK_H_(0x0F, 0x02) ++#define REG_SC_BK0F_03_L _PK_L_(0x0F, 0x03) ++#define REG_SC_BK0F_03_H _PK_H_(0x0F, 0x03) ++#define REG_SC_BK0F_04_L _PK_L_(0x0F, 0x04) ++#define REG_SC_BK0F_04_H _PK_H_(0x0F, 0x04) ++#define REG_SC_BK0F_05_L _PK_L_(0x0F, 0x05) ++#define REG_SC_BK0F_05_H _PK_H_(0x0F, 0x05) ++#define REG_SC_BK0F_06_L _PK_L_(0x0F, 0x06) ++#define REG_SC_BK0F_06_H _PK_H_(0x0F, 0x06) ++#define REG_SC_BK0F_07_L _PK_L_(0x0F, 0x07) ++#define REG_SC_BK0F_07_H _PK_H_(0x0F, 0x07) ++#define REG_SC_BK0F_08_L _PK_L_(0x0F, 0x08) ++#define REG_SC_BK0F_08_H _PK_H_(0x0F, 0x08) ++#define REG_SC_BK0F_09_L _PK_L_(0x0F, 0x09) ++#define REG_SC_BK0F_09_H _PK_H_(0x0F, 0x09) ++#define REG_SC_BK0F_0A_L _PK_L_(0x0F, 0x0A) ++#define REG_SC_BK0F_0A_H _PK_H_(0x0F, 0x0A) ++#define REG_SC_BK0F_0B_L _PK_L_(0x0F, 0x0B) ++#define REG_SC_BK0F_0B_H _PK_H_(0x0F, 0x0B) ++#define REG_SC_BK0F_0C_L _PK_L_(0x0F, 0x0C) ++#define REG_SC_BK0F_0C_H _PK_H_(0x0F, 0x0C) ++#define REG_SC_BK0F_0D_L _PK_L_(0x0F, 0x0D) ++#define REG_SC_BK0F_0D_H _PK_H_(0x0F, 0x0D) ++#define REG_SC_BK0F_0E_L _PK_L_(0x0F, 0x0E) ++#define REG_SC_BK0F_0E_H _PK_H_(0x0F, 0x0E) ++#define REG_SC_BK0F_0F_L _PK_L_(0x0F, 0x0F) ++#define REG_SC_BK0F_0F_H _PK_H_(0x0F, 0x0F) ++#define REG_SC_BK0F_10_L _PK_L_(0x0F, 0x10) ++#define REG_SC_BK0F_10_H _PK_H_(0x0F, 0x10) ++#define REG_SC_BK0F_11_L _PK_L_(0x0F, 0x11) ++#define REG_SC_BK0F_11_H _PK_H_(0x0F, 0x11) ++#define REG_SC_BK0F_12_L _PK_L_(0x0F, 0x12) ++#define REG_SC_BK0F_12_H _PK_H_(0x0F, 0x12) ++#define REG_SC_BK0F_13_L _PK_L_(0x0F, 0x13) ++#define REG_SC_BK0F_13_H _PK_H_(0x0F, 0x13) ++#define REG_SC_BK0F_14_L _PK_L_(0x0F, 0x14) ++#define REG_SC_BK0F_14_H _PK_H_(0x0F, 0x14) ++#define REG_SC_BK0F_15_L _PK_L_(0x0F, 0x15) ++#define REG_SC_BK0F_15_H _PK_H_(0x0F, 0x15) ++#define REG_SC_BK0F_16_L _PK_L_(0x0F, 0x16) ++#define REG_SC_BK0F_16_H _PK_H_(0x0F, 0x16) ++#define REG_SC_BK0F_17_L _PK_L_(0x0F, 0x17) ++#define REG_SC_BK0F_17_H _PK_H_(0x0F, 0x17) ++#define REG_SC_BK0F_18_L _PK_L_(0x0F, 0x18) ++#define REG_SC_BK0F_18_H _PK_H_(0x0F, 0x18) ++#define REG_SC_BK0F_19_L _PK_L_(0x0F, 0x19) ++#define REG_SC_BK0F_19_H _PK_H_(0x0F, 0x19) ++#define REG_SC_BK0F_1A_L _PK_L_(0x0F, 0x1A) ++#define REG_SC_BK0F_1A_H _PK_H_(0x0F, 0x1A) ++#define REG_SC_BK0F_1B_L _PK_L_(0x0F, 0x1B) ++#define REG_SC_BK0F_1B_H _PK_H_(0x0F, 0x1B) ++#define REG_SC_BK0F_1C_L _PK_L_(0x0F, 0x1C) ++#define REG_SC_BK0F_1C_H _PK_H_(0x0F, 0x1C) ++#define REG_SC_BK0F_1D_L _PK_L_(0x0F, 0x1D) ++#define REG_SC_BK0F_1D_H _PK_H_(0x0F, 0x1D) ++#define REG_SC_BK0F_1E_L _PK_L_(0x0F, 0x1E) ++#define REG_SC_BK0F_1E_H _PK_H_(0x0F, 0x1E) ++#define REG_SC_BK0F_1F_L _PK_L_(0x0F, 0x1F) ++#define REG_SC_BK0F_1F_H _PK_H_(0x0F, 0x1F) ++#define REG_SC_BK0F_20_L _PK_L_(0x0F, 0x20) ++#define REG_SC_BK0F_20_H _PK_H_(0x0F, 0x20) ++#define REG_SC_BK0F_21_L _PK_L_(0x0F, 0x21) ++#define REG_SC_BK0F_21_H _PK_H_(0x0F, 0x21) ++#define REG_SC_BK0F_22_L _PK_L_(0x0F, 0x22) ++#define REG_SC_BK0F_22_H _PK_H_(0x0F, 0x22) ++#define REG_SC_BK0F_23_L _PK_L_(0x0F, 0x23) ++#define REG_SC_BK0F_23_H _PK_H_(0x0F, 0x23) ++#define REG_SC_BK0F_24_L _PK_L_(0x0F, 0x24) ++#define REG_SC_BK0F_24_H _PK_H_(0x0F, 0x24) ++#define REG_SC_BK0F_25_L _PK_L_(0x0F, 0x25) ++#define REG_SC_BK0F_25_H _PK_H_(0x0F, 0x25) ++#define REG_SC_BK0F_26_L _PK_L_(0x0F, 0x26) ++#define REG_SC_BK0F_26_H _PK_H_(0x0F, 0x26) ++#define REG_SC_BK0F_27_L _PK_L_(0x0F, 0x27) ++#define REG_SC_BK0F_27_H _PK_H_(0x0F, 0x27) ++#define REG_SC_BK0F_28_L _PK_L_(0x0F, 0x28) ++#define REG_SC_BK0F_28_H _PK_H_(0x0F, 0x28) ++#define REG_SC_BK0F_29_L _PK_L_(0x0F, 0x29) ++#define REG_SC_BK0F_29_H _PK_H_(0x0F, 0x29) ++#define REG_SC_BK0F_2A_L _PK_L_(0x0F, 0x2A) ++#define REG_SC_BK0F_2A_H _PK_H_(0x0F, 0x2A) ++#define REG_SC_BK0F_2B_L _PK_L_(0x0F, 0x2B) ++#define REG_SC_BK0F_2B_H _PK_H_(0x0F, 0x2B) ++#define REG_SC_BK0F_2C_L _PK_L_(0x0F, 0x2C) ++#define REG_SC_BK0F_2C_H _PK_H_(0x0F, 0x2C) ++#define REG_SC_BK0F_2D_L _PK_L_(0x0F, 0x2D) ++#define REG_SC_BK0F_2D_H _PK_H_(0x0F, 0x2D) ++#define REG_SC_BK0F_2E_L _PK_L_(0x0F, 0x2E) ++#define REG_SC_BK0F_2E_H _PK_H_(0x0F, 0x2E) ++#define REG_SC_BK0F_2F_L _PK_L_(0x0F, 0x2F) ++#define REG_SC_BK0F_2F_H _PK_H_(0x0F, 0x2F) ++#define REG_SC_BK0F_30_L _PK_L_(0x0F, 0x30) ++#define REG_SC_BK0F_30_H _PK_H_(0x0F, 0x30) ++#define REG_SC_BK0F_31_L _PK_L_(0x0F, 0x31) ++#define REG_SC_BK0F_31_H _PK_H_(0x0F, 0x31) ++#define REG_SC_BK0F_32_L _PK_L_(0x0F, 0x32) ++#define REG_SC_BK0F_32_H _PK_H_(0x0F, 0x32) ++#define REG_SC_BK0F_33_L _PK_L_(0x0F, 0x33) ++#define REG_SC_BK0F_33_H _PK_H_(0x0F, 0x33) ++#define REG_SC_BK0F_34_L _PK_L_(0x0F, 0x34) ++#define REG_SC_BK0F_34_H _PK_H_(0x0F, 0x34) ++#define REG_SC_BK0F_35_L _PK_L_(0x0F, 0x35) ++#define REG_SC_BK0F_35_H _PK_H_(0x0F, 0x35) ++#define REG_SC_BK0F_36_L _PK_L_(0x0F, 0x36) ++#define REG_SC_BK0F_36_H _PK_H_(0x0F, 0x36) ++#define REG_SC_BK0F_37_L _PK_L_(0x0F, 0x37) ++#define REG_SC_BK0F_37_H _PK_H_(0x0F, 0x37) ++#define REG_SC_BK0F_38_L _PK_L_(0x0F, 0x38) ++#define REG_SC_BK0F_38_H _PK_H_(0x0F, 0x38) ++#define REG_SC_BK0F_39_L _PK_L_(0x0F, 0x39) ++#define REG_SC_BK0F_39_H _PK_H_(0x0F, 0x39) ++#define REG_SC_BK0F_3A_L _PK_L_(0x0F, 0x3A) ++#define REG_SC_BK0F_3A_H _PK_H_(0x0F, 0x3A) ++#define REG_SC_BK0F_3B_L _PK_L_(0x0F, 0x3B) ++#define REG_SC_BK0F_3B_H _PK_H_(0x0F, 0x3B) ++#define REG_SC_BK0F_3C_L _PK_L_(0x0F, 0x3C) ++#define REG_SC_BK0F_3C_H _PK_H_(0x0F, 0x3C) ++#define REG_SC_BK0F_3D_L _PK_L_(0x0F, 0x3D) ++#define REG_SC_BK0F_3D_H _PK_H_(0x0F, 0x3D) ++#define REG_SC_BK0F_3E_L _PK_L_(0x0F, 0x3E) ++#define REG_SC_BK0F_3E_H _PK_H_(0x0F, 0x3E) ++#define REG_SC_BK0F_3F_L _PK_L_(0x0F, 0x3F) ++#define REG_SC_BK0F_3F_H _PK_H_(0x0F, 0x3F) ++#define REG_SC_BK0F_40_L _PK_L_(0x0F, 0x40) ++#define REG_SC_BK0F_40_H _PK_H_(0x0F, 0x40) ++#define REG_SC_BK0F_41_L _PK_L_(0x0F, 0x41) ++#define REG_SC_BK0F_41_H _PK_H_(0x0F, 0x41) ++#define REG_SC_BK0F_42_L _PK_L_(0x0F, 0x42) ++#define REG_SC_BK0F_42_H _PK_H_(0x0F, 0x42) ++#define REG_SC_BK0F_43_L _PK_L_(0x0F, 0x43) ++#define REG_SC_BK0F_43_H _PK_H_(0x0F, 0x43) ++#define REG_SC_BK0F_44_L _PK_L_(0x0F, 0x44) ++#define REG_SC_BK0F_44_H _PK_H_(0x0F, 0x44) ++#define REG_SC_BK0F_45_L _PK_L_(0x0F, 0x45) ++#define REG_SC_BK0F_45_H _PK_H_(0x0F, 0x45) ++#define REG_SC_BK0F_46_L _PK_L_(0x0F, 0x46) ++#define REG_SC_BK0F_46_H _PK_H_(0x0F, 0x46) ++#define REG_SC_BK0F_47_L _PK_L_(0x0F, 0x47) ++#define REG_SC_BK0F_47_H _PK_H_(0x0F, 0x47) ++#define REG_SC_BK0F_48_L _PK_L_(0x0F, 0x48) ++#define REG_SC_BK0F_48_H _PK_H_(0x0F, 0x48) ++#define REG_SC_BK0F_49_L _PK_L_(0x0F, 0x49) ++#define REG_SC_BK0F_49_H _PK_H_(0x0F, 0x49) ++#define REG_SC_BK0F_4A_L _PK_L_(0x0F, 0x4A) ++#define REG_SC_BK0F_4A_H _PK_H_(0x0F, 0x4A) ++#define REG_SC_BK0F_4B_L _PK_L_(0x0F, 0x4B) ++#define REG_SC_BK0F_4B_H _PK_H_(0x0F, 0x4B) ++#define REG_SC_BK0F_4C_L _PK_L_(0x0F, 0x4C) ++#define REG_SC_BK0F_4C_H _PK_H_(0x0F, 0x4C) ++#define REG_SC_BK0F_4D_L _PK_L_(0x0F, 0x4D) ++#define REG_SC_BK0F_4D_H _PK_H_(0x0F, 0x4D) ++#define REG_SC_BK0F_4E_L _PK_L_(0x0F, 0x4E) ++#define REG_SC_BK0F_4E_H _PK_H_(0x0F, 0x4E) ++#define REG_SC_BK0F_4F_L _PK_L_(0x0F, 0x4F) ++#define REG_SC_BK0F_4F_H _PK_H_(0x0F, 0x4F) ++#define REG_SC_BK0F_50_L _PK_L_(0x0F, 0x50) ++#define REG_SC_BK0F_50_H _PK_H_(0x0F, 0x50) ++#define REG_SC_BK0F_51_L _PK_L_(0x0F, 0x51) ++#define REG_SC_BK0F_51_H _PK_H_(0x0F, 0x51) ++#define REG_SC_BK0F_52_L _PK_L_(0x0F, 0x52) ++#define REG_SC_BK0F_52_H _PK_H_(0x0F, 0x52) ++#define REG_SC_BK0F_53_L _PK_L_(0x0F, 0x53) ++#define REG_SC_BK0F_53_H _PK_H_(0x0F, 0x53) ++#define REG_SC_BK0F_54_L _PK_L_(0x0F, 0x54) ++#define REG_SC_BK0F_54_H _PK_H_(0x0F, 0x54) ++#define REG_SC_BK0F_55_L _PK_L_(0x0F, 0x55) ++#define REG_SC_BK0F_55_H _PK_H_(0x0F, 0x55) ++#define REG_SC_BK0F_56_L _PK_L_(0x0F, 0x56) ++#define REG_SC_BK0F_56_H _PK_H_(0x0F, 0x56) ++#define REG_SC_BK0F_57_L _PK_L_(0x0F, 0x57) ++#define REG_SC_BK0F_57_H _PK_H_(0x0F, 0x57) ++#define REG_SC_BK0F_58_L _PK_L_(0x0F, 0x58) ++#define REG_SC_BK0F_58_H _PK_H_(0x0F, 0x58) ++#define REG_SC_BK0F_59_L _PK_L_(0x0F, 0x59) ++#define REG_SC_BK0F_59_H _PK_H_(0x0F, 0x59) ++#define REG_SC_BK0F_5A_L _PK_L_(0x0F, 0x5A) ++#define REG_SC_BK0F_5A_H _PK_H_(0x0F, 0x5A) ++#define REG_SC_BK0F_5B_L _PK_L_(0x0F, 0x5B) ++#define REG_SC_BK0F_5B_H _PK_H_(0x0F, 0x5B) ++#define REG_SC_BK0F_5C_L _PK_L_(0x0F, 0x5C) ++#define REG_SC_BK0F_5C_H _PK_H_(0x0F, 0x5C) ++#define REG_SC_BK0F_5D_L _PK_L_(0x0F, 0x5D) ++#define REG_SC_BK0F_5D_H _PK_H_(0x0F, 0x5D) ++#define REG_SC_BK0F_5E_L _PK_L_(0x0F, 0x5E) ++#define REG_SC_BK0F_5E_H _PK_H_(0x0F, 0x5E) ++#define REG_SC_BK0F_5F_L _PK_L_(0x0F, 0x5F) ++#define REG_SC_BK0F_5F_H _PK_H_(0x0F, 0x5F) ++#define REG_SC_BK0F_60_L _PK_L_(0x0F, 0x60) ++#define REG_SC_BK0F_60_H _PK_H_(0x0F, 0x60) ++#define REG_SC_BK0F_61_L _PK_L_(0x0F, 0x61) ++#define REG_SC_BK0F_61_H _PK_H_(0x0F, 0x61) ++#define REG_SC_BK0F_62_L _PK_L_(0x0F, 0x62) ++#define REG_SC_BK0F_62_H _PK_H_(0x0F, 0x62) ++#define REG_SC_BK0F_63_L _PK_L_(0x0F, 0x63) ++#define REG_SC_BK0F_63_H _PK_H_(0x0F, 0x63) ++#define REG_SC_BK0F_64_L _PK_L_(0x0F, 0x64) ++#define REG_SC_BK0F_64_H _PK_H_(0x0F, 0x64) ++#define REG_SC_BK0F_65_L _PK_L_(0x0F, 0x65) ++#define REG_SC_BK0F_65_H _PK_H_(0x0F, 0x65) ++#define REG_SC_BK0F_66_L _PK_L_(0x0F, 0x66) ++#define REG_SC_BK0F_66_H _PK_H_(0x0F, 0x66) ++#define REG_SC_BK0F_67_L _PK_L_(0x0F, 0x67) ++#define REG_SC_BK0F_67_H _PK_H_(0x0F, 0x67) ++#define REG_SC_BK0F_68_L _PK_L_(0x0F, 0x68) ++#define REG_SC_BK0F_68_H _PK_H_(0x0F, 0x68) ++#define REG_SC_BK0F_69_L _PK_L_(0x0F, 0x69) ++#define REG_SC_BK0F_69_H _PK_H_(0x0F, 0x69) ++#define REG_SC_BK0F_6A_L _PK_L_(0x0F, 0x6A) ++#define REG_SC_BK0F_6A_H _PK_H_(0x0F, 0x6A) ++#define REG_SC_BK0F_6B_L _PK_L_(0x0F, 0x6B) ++#define REG_SC_BK0F_6B_H _PK_H_(0x0F, 0x6B) ++#define REG_SC_BK0F_6C_L _PK_L_(0x0F, 0x6C) ++#define REG_SC_BK0F_6C_H _PK_H_(0x0F, 0x6C) ++#define REG_SC_BK0F_6D_L _PK_L_(0x0F, 0x6D) ++#define REG_SC_BK0F_6D_H _PK_H_(0x0F, 0x6D) ++#define REG_SC_BK0F_6E_L _PK_L_(0x0F, 0x6E) ++#define REG_SC_BK0F_6E_H _PK_H_(0x0F, 0x6E) ++#define REG_SC_BK0F_6F_L _PK_L_(0x0F, 0x6F) ++#define REG_SC_BK0F_6F_H _PK_H_(0x0F, 0x6F) ++#define REG_SC_BK0F_70_L _PK_L_(0x0F, 0x70) ++#define REG_SC_BK0F_70_H _PK_H_(0x0F, 0x70) ++#define REG_SC_BK0F_71_L _PK_L_(0x0F, 0x71) ++#define REG_SC_BK0F_71_H _PK_H_(0x0F, 0x71) ++#define REG_SC_BK0F_72_L _PK_L_(0x0F, 0x72) ++#define REG_SC_BK0F_72_H _PK_H_(0x0F, 0x72) ++#define REG_SC_BK0F_73_L _PK_L_(0x0F, 0x73) ++#define REG_SC_BK0F_73_H _PK_H_(0x0F, 0x73) ++#define REG_SC_BK0F_74_L _PK_L_(0x0F, 0x74) ++#define REG_SC_BK0F_74_H _PK_H_(0x0F, 0x74) ++#define REG_SC_BK0F_75_L _PK_L_(0x0F, 0x75) ++#define REG_SC_BK0F_75_H _PK_H_(0x0F, 0x75) ++#define REG_SC_BK0F_76_L _PK_L_(0x0F, 0x76) ++#define REG_SC_BK0F_76_H _PK_H_(0x0F, 0x76) ++#define REG_SC_BK0F_77_L _PK_L_(0x0F, 0x77) ++#define REG_SC_BK0F_77_H _PK_H_(0x0F, 0x77) ++#define REG_SC_BK0F_78_L _PK_L_(0x0F, 0x78) ++#define REG_SC_BK0F_78_H _PK_H_(0x0F, 0x78) ++#define REG_SC_BK0F_79_L _PK_L_(0x0F, 0x79) ++#define REG_SC_BK0F_79_H _PK_H_(0x0F, 0x79) ++#define REG_SC_BK0F_7A_L _PK_L_(0x0F, 0x7A) ++#define REG_SC_BK0F_7A_H _PK_H_(0x0F, 0x7A) ++#define REG_SC_BK0F_7B_L _PK_L_(0x0F, 0x7B) ++#define REG_SC_BK0F_7B_H _PK_H_(0x0F, 0x7B) ++#define REG_SC_BK0F_7C_L _PK_L_(0x0F, 0x7C) ++#define REG_SC_BK0F_7C_H _PK_H_(0x0F, 0x7C) ++#define REG_SC_BK0F_7D_L _PK_L_(0x0F, 0x7D) ++#define REG_SC_BK0F_7D_H _PK_H_(0x0F, 0x7D) ++#define REG_SC_BK0F_7E_L _PK_L_(0x0F, 0x7E) ++#define REG_SC_BK0F_7E_H _PK_H_(0x0F, 0x7E) ++#define REG_SC_BK0F_7F_L _PK_L_(0x0F, 0x7F) ++#define REG_SC_BK0F_7F_H _PK_H_(0x0F, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK10_00_L _PK_L_(0x10, 0x00) ++#define REG_SC_BK10_00_H _PK_H_(0x10, 0x00) ++#define REG_SC_BK10_01_L _PK_L_(0x10, 0x01) ++#define REG_SC_BK10_01_H _PK_H_(0x10, 0x01) ++#define REG_SC_BK10_02_L _PK_L_(0x10, 0x02) ++#define REG_SC_BK10_02_H _PK_H_(0x10, 0x02) ++#define REG_SC_BK10_03_L _PK_L_(0x10, 0x03) ++#define REG_SC_BK10_03_H _PK_H_(0x10, 0x03) ++#define REG_SC_BK10_04_L _PK_L_(0x10, 0x04) ++#define REG_SC_BK10_04_H _PK_H_(0x10, 0x04) ++#define REG_SC_BK10_05_L _PK_L_(0x10, 0x05) ++#define REG_SC_BK10_05_H _PK_H_(0x10, 0x05) ++#define REG_SC_BK10_06_L _PK_L_(0x10, 0x06) ++#define REG_SC_BK10_06_H _PK_H_(0x10, 0x06) ++#define REG_SC_BK10_07_L _PK_L_(0x10, 0x07) ++#define REG_SC_BK10_07_H _PK_H_(0x10, 0x07) ++#define REG_SC_BK10_08_L _PK_L_(0x10, 0x08) ++#define REG_SC_BK10_08_H _PK_H_(0x10, 0x08) ++#define REG_SC_BK10_09_L _PK_L_(0x10, 0x09) ++#define REG_SC_BK10_09_H _PK_H_(0x10, 0x09) ++#define REG_SC_BK10_0A_L _PK_L_(0x10, 0x0A) ++#define REG_SC_BK10_0A_H _PK_H_(0x10, 0x0A) ++#define REG_SC_BK10_0B_L _PK_L_(0x10, 0x0B) ++#define REG_SC_BK10_0B_H _PK_H_(0x10, 0x0B) ++#define REG_SC_BK10_0C_L _PK_L_(0x10, 0x0C) ++#define REG_SC_BK10_0C_H _PK_H_(0x10, 0x0C) ++#define REG_SC_BK10_0D_L _PK_L_(0x10, 0x0D) ++#define REG_SC_BK10_0D_H _PK_H_(0x10, 0x0D) ++#define REG_SC_BK10_0E_L _PK_L_(0x10, 0x0E) ++#define REG_SC_BK10_0E_H _PK_H_(0x10, 0x0E) ++#define REG_SC_BK10_0F_L _PK_L_(0x10, 0x0F) ++#define REG_SC_BK10_0F_H _PK_H_(0x10, 0x0F) ++#define REG_SC_BK10_10_L _PK_L_(0x10, 0x10) ++#define REG_SC_BK10_10_H _PK_H_(0x10, 0x10) ++#define REG_SC_BK10_11_L _PK_L_(0x10, 0x11) ++#define REG_SC_BK10_11_H _PK_H_(0x10, 0x11) ++#define REG_SC_BK10_12_L _PK_L_(0x10, 0x12) ++#define REG_SC_BK10_12_H _PK_H_(0x10, 0x12) ++#define REG_SC_BK10_13_L _PK_L_(0x10, 0x13) ++#define REG_SC_BK10_13_H _PK_H_(0x10, 0x13) ++#define REG_SC_BK10_14_L _PK_L_(0x10, 0x14) ++#define REG_SC_BK10_14_H _PK_H_(0x10, 0x14) ++#define REG_SC_BK10_15_L _PK_L_(0x10, 0x15) ++#define REG_SC_BK10_15_H _PK_H_(0x10, 0x15) ++#define REG_SC_BK10_16_L _PK_L_(0x10, 0x16) ++#define REG_SC_BK10_16_H _PK_H_(0x10, 0x16) ++#define REG_SC_BK10_17_L _PK_L_(0x10, 0x17) ++#define REG_SC_BK10_17_H _PK_H_(0x10, 0x17) ++#define REG_SC_BK10_18_L _PK_L_(0x10, 0x18) ++#define REG_SC_BK10_18_H _PK_H_(0x10, 0x18) ++#define REG_SC_BK10_19_L _PK_L_(0x10, 0x19) ++#define REG_SC_BK10_19_H _PK_H_(0x10, 0x19) ++#define REG_SC_BK10_1A_L _PK_L_(0x10, 0x1A) ++#define REG_SC_BK10_1A_H _PK_H_(0x10, 0x1A) ++#define REG_SC_BK10_1B_L _PK_L_(0x10, 0x1B) ++#define REG_SC_BK10_1B_H _PK_H_(0x10, 0x1B) ++#define REG_SC_BK10_1C_L _PK_L_(0x10, 0x1C) ++#define REG_SC_BK10_1C_H _PK_H_(0x10, 0x1C) ++#define REG_SC_BK10_1D_L _PK_L_(0x10, 0x1D) ++#define REG_SC_BK10_1D_H _PK_H_(0x10, 0x1D) ++#define REG_SC_BK10_1E_L _PK_L_(0x10, 0x1E) ++#define REG_SC_BK10_1E_H _PK_H_(0x10, 0x1E) ++#define REG_SC_BK10_1F_L _PK_L_(0x10, 0x1F) ++#define REG_SC_BK10_1F_H _PK_H_(0x10, 0x1F) ++#define REG_SC_BK10_20_L _PK_L_(0x10, 0x20) ++#define REG_SC_BK10_20_H _PK_H_(0x10, 0x20) ++#define REG_SC_BK10_21_L _PK_L_(0x10, 0x21) ++#define REG_SC_BK10_21_H _PK_H_(0x10, 0x21) ++#define REG_SC_BK10_22_L _PK_L_(0x10, 0x22) ++#define REG_SC_BK10_22_H _PK_H_(0x10, 0x22) ++#define REG_SC_BK10_23_L _PK_L_(0x10, 0x23) ++#define REG_SC_BK10_23_H _PK_H_(0x10, 0x23) ++#define REG_SC_BK10_24_L _PK_L_(0x10, 0x24) ++#define REG_SC_BK10_24_H _PK_H_(0x10, 0x24) ++#define REG_SC_BK10_25_L _PK_L_(0x10, 0x25) ++#define REG_SC_BK10_25_H _PK_H_(0x10, 0x25) ++#define REG_SC_BK10_26_L _PK_L_(0x10, 0x26) ++#define REG_SC_BK10_26_H _PK_H_(0x10, 0x26) ++#define REG_SC_BK10_27_L _PK_L_(0x10, 0x27) ++#define REG_SC_BK10_27_H _PK_H_(0x10, 0x27) ++#define REG_SC_BK10_28_L _PK_L_(0x10, 0x28) ++#define REG_SC_BK10_28_H _PK_H_(0x10, 0x28) ++#define REG_SC_BK10_29_L _PK_L_(0x10, 0x29) ++#define REG_SC_BK10_29_H _PK_H_(0x10, 0x29) ++#define REG_SC_BK10_2A_L _PK_L_(0x10, 0x2A) ++#define REG_SC_BK10_2A_H _PK_H_(0x10, 0x2A) ++#define REG_SC_BK10_2B_L _PK_L_(0x10, 0x2B) ++#define REG_SC_BK10_2B_H _PK_H_(0x10, 0x2B) ++#define REG_SC_BK10_2C_L _PK_L_(0x10, 0x2C) ++#define REG_SC_BK10_2C_H _PK_H_(0x10, 0x2C) ++#define REG_SC_BK10_2D_L _PK_L_(0x10, 0x2D) ++#define REG_SC_BK10_2D_H _PK_H_(0x10, 0x2D) ++#define REG_SC_BK10_2E_L _PK_L_(0x10, 0x2E) ++#define REG_SC_BK10_2E_H _PK_H_(0x10, 0x2E) ++#define REG_SC_BK10_2F_L _PK_L_(0x10, 0x2F) ++#define REG_SC_BK10_2F_H _PK_H_(0x10, 0x2F) ++#define REG_SC_BK10_30_L _PK_L_(0x10, 0x30) ++#define REG_SC_BK10_30_H _PK_H_(0x10, 0x30) ++#define REG_SC_BK10_31_L _PK_L_(0x10, 0x31) ++#define REG_SC_BK10_31_H _PK_H_(0x10, 0x31) ++#define REG_SC_BK10_32_L _PK_L_(0x10, 0x32) ++#define REG_SC_BK10_32_H _PK_H_(0x10, 0x32) ++#define REG_SC_BK10_33_L _PK_L_(0x10, 0x33) ++#define REG_SC_BK10_33_H _PK_H_(0x10, 0x33) ++#define REG_SC_BK10_34_L _PK_L_(0x10, 0x34) ++#define REG_SC_BK10_34_H _PK_H_(0x10, 0x34) ++#define REG_SC_BK10_35_L _PK_L_(0x10, 0x35) ++#define REG_SC_BK10_35_H _PK_H_(0x10, 0x35) ++#define REG_SC_BK10_36_L _PK_L_(0x10, 0x36) ++#define REG_SC_BK10_36_H _PK_H_(0x10, 0x36) ++#define REG_SC_BK10_37_L _PK_L_(0x10, 0x37) ++#define REG_SC_BK10_37_H _PK_H_(0x10, 0x37) ++#define REG_SC_BK10_38_L _PK_L_(0x10, 0x38) ++#define REG_SC_BK10_38_H _PK_H_(0x10, 0x38) ++#define REG_SC_BK10_39_L _PK_L_(0x10, 0x39) ++#define REG_SC_BK10_39_H _PK_H_(0x10, 0x39) ++#define REG_SC_BK10_3A_L _PK_L_(0x10, 0x3A) ++#define REG_SC_BK10_3A_H _PK_H_(0x10, 0x3A) ++#define REG_SC_BK10_3B_L _PK_L_(0x10, 0x3B) ++#define REG_SC_BK10_3B_H _PK_H_(0x10, 0x3B) ++#define REG_SC_BK10_3C_L _PK_L_(0x10, 0x3C) ++#define REG_SC_BK10_3C_H _PK_H_(0x10, 0x3C) ++#define REG_SC_BK10_3D_L _PK_L_(0x10, 0x3D) ++#define REG_SC_BK10_3D_H _PK_H_(0x10, 0x3D) ++#define REG_SC_BK10_3E_L _PK_L_(0x10, 0x3E) ++#define REG_SC_BK10_3E_H _PK_H_(0x10, 0x3E) ++#define REG_SC_BK10_3F_L _PK_L_(0x10, 0x3F) ++#define REG_SC_BK10_3F_H _PK_H_(0x10, 0x3F) ++#define REG_SC_BK10_40_L _PK_L_(0x10, 0x40) ++#define REG_SC_BK10_40_H _PK_H_(0x10, 0x40) ++#define REG_SC_BK10_41_L _PK_L_(0x10, 0x41) ++#define REG_SC_BK10_41_H _PK_H_(0x10, 0x41) ++#define REG_SC_BK10_42_L _PK_L_(0x10, 0x42) ++#define REG_SC_BK10_42_H _PK_H_(0x10, 0x42) ++#define REG_SC_BK10_43_L _PK_L_(0x10, 0x43) ++#define REG_SC_BK10_43_H _PK_H_(0x10, 0x43) ++#define REG_SC_BK10_44_L _PK_L_(0x10, 0x44) ++#define REG_SC_BK10_44_H _PK_H_(0x10, 0x44) ++#define REG_SC_BK10_45_L _PK_L_(0x10, 0x45) ++#define REG_SC_BK10_45_H _PK_H_(0x10, 0x45) ++#define REG_SC_BK10_46_L _PK_L_(0x10, 0x46) ++#define REG_SC_BK10_46_H _PK_H_(0x10, 0x46) ++#define REG_SC_BK10_47_L _PK_L_(0x10, 0x47) ++#define REG_SC_BK10_47_H _PK_H_(0x10, 0x47) ++#define REG_SC_BK10_48_L _PK_L_(0x10, 0x48) ++#define REG_SC_BK10_48_H _PK_H_(0x10, 0x48) ++#define REG_SC_BK10_49_L _PK_L_(0x10, 0x49) ++#define REG_SC_BK10_49_H _PK_H_(0x10, 0x49) ++#define REG_SC_BK10_4A_L _PK_L_(0x10, 0x4A) ++#define REG_SC_BK10_4A_H _PK_H_(0x10, 0x4A) ++#define REG_SC_BK10_4B_L _PK_L_(0x10, 0x4B) ++#define REG_SC_BK10_4B_H _PK_H_(0x10, 0x4B) ++#define REG_SC_BK10_4C_L _PK_L_(0x10, 0x4C) ++#define REG_SC_BK10_4C_H _PK_H_(0x10, 0x4C) ++#define REG_SC_BK10_4D_L _PK_L_(0x10, 0x4D) ++#define REG_SC_BK10_4D_H _PK_H_(0x10, 0x4D) ++#define REG_SC_BK10_4E_L _PK_L_(0x10, 0x4E) ++#define REG_SC_BK10_4E_H _PK_H_(0x10, 0x4E) ++#define REG_SC_BK10_4F_L _PK_L_(0x10, 0x4F) ++#define REG_SC_BK10_4F_H _PK_H_(0x10, 0x4F) ++#define REG_SC_BK10_50_L _PK_L_(0x10, 0x50) ++#define REG_SC_BK10_50_H _PK_H_(0x10, 0x50) ++#define REG_SC_BK10_51_L _PK_L_(0x10, 0x51) ++#define REG_SC_BK10_51_H _PK_H_(0x10, 0x51) ++#define REG_SC_BK10_52_L _PK_L_(0x10, 0x52) ++#define REG_SC_BK10_52_H _PK_H_(0x10, 0x52) ++#define REG_SC_BK10_53_L _PK_L_(0x10, 0x53) ++#define REG_SC_BK10_53_H _PK_H_(0x10, 0x53) ++#define REG_SC_BK10_54_L _PK_L_(0x10, 0x54) ++#define REG_SC_BK10_54_H _PK_H_(0x10, 0x54) ++#define REG_SC_BK10_55_L _PK_L_(0x10, 0x55) ++#define REG_SC_BK10_55_H _PK_H_(0x10, 0x55) ++#define REG_SC_BK10_56_L _PK_L_(0x10, 0x56) ++#define REG_SC_BK10_56_H _PK_H_(0x10, 0x56) ++#define REG_SC_BK10_57_L _PK_L_(0x10, 0x57) ++#define REG_SC_BK10_57_H _PK_H_(0x10, 0x57) ++#define REG_SC_BK10_58_L _PK_L_(0x10, 0x58) ++#define REG_SC_BK10_58_H _PK_H_(0x10, 0x58) ++#define REG_SC_BK10_59_L _PK_L_(0x10, 0x59) ++#define REG_SC_BK10_59_H _PK_H_(0x10, 0x59) ++#define REG_SC_BK10_5A_L _PK_L_(0x10, 0x5A) ++#define REG_SC_BK10_5A_H _PK_H_(0x10, 0x5A) ++#define REG_SC_BK10_5B_L _PK_L_(0x10, 0x5B) ++#define REG_SC_BK10_5B_H _PK_H_(0x10, 0x5B) ++#define REG_SC_BK10_5C_L _PK_L_(0x10, 0x5C) ++#define REG_SC_BK10_5C_H _PK_H_(0x10, 0x5C) ++#define REG_SC_BK10_5D_L _PK_L_(0x10, 0x5D) ++#define REG_SC_BK10_5D_H _PK_H_(0x10, 0x5D) ++#define REG_SC_BK10_5E_L _PK_L_(0x10, 0x5E) ++#define REG_SC_BK10_5E_H _PK_H_(0x10, 0x5E) ++#define REG_SC_BK10_5F_L _PK_L_(0x10, 0x5F) ++#define REG_SC_BK10_5F_H _PK_H_(0x10, 0x5F) ++#define REG_SC_BK10_60_L _PK_L_(0x10, 0x60) ++#define REG_SC_BK10_60_H _PK_H_(0x10, 0x60) ++#define REG_SC_BK10_61_L _PK_L_(0x10, 0x61) ++#define REG_SC_BK10_61_H _PK_H_(0x10, 0x61) ++#define REG_SC_BK10_62_L _PK_L_(0x10, 0x62) ++#define REG_SC_BK10_62_H _PK_H_(0x10, 0x62) ++#define REG_SC_BK10_63_L _PK_L_(0x10, 0x63) ++#define REG_SC_BK10_63_H _PK_H_(0x10, 0x63) ++#define REG_SC_BK10_64_L _PK_L_(0x10, 0x64) ++#define REG_SC_BK10_64_H _PK_H_(0x10, 0x64) ++#define REG_SC_BK10_65_L _PK_L_(0x10, 0x65) ++#define REG_SC_BK10_65_H _PK_H_(0x10, 0x65) ++#define REG_SC_BK10_66_L _PK_L_(0x10, 0x66) ++#define REG_SC_BK10_66_H _PK_H_(0x10, 0x66) ++#define REG_SC_BK10_67_L _PK_L_(0x10, 0x67) ++#define REG_SC_BK10_67_H _PK_H_(0x10, 0x67) ++#define REG_SC_BK10_68_L _PK_L_(0x10, 0x68) ++#define REG_SC_BK10_68_H _PK_H_(0x10, 0x68) ++#define REG_SC_BK10_69_L _PK_L_(0x10, 0x69) ++#define REG_SC_BK10_69_H _PK_H_(0x10, 0x69) ++#define REG_SC_BK10_6A_L _PK_L_(0x10, 0x6A) ++#define REG_SC_BK10_6A_H _PK_H_(0x10, 0x6A) ++#define REG_SC_BK10_6B_L _PK_L_(0x10, 0x6B) ++#define REG_SC_BK10_6B_H _PK_H_(0x10, 0x6B) ++#define REG_SC_BK10_6C_L _PK_L_(0x10, 0x6C) ++#define REG_SC_BK10_6C_H _PK_H_(0x10, 0x6C) ++#define REG_SC_BK10_6D_L _PK_L_(0x10, 0x6D) ++#define REG_SC_BK10_6D_H _PK_H_(0x10, 0x6D) ++#define REG_SC_BK10_6E_L _PK_L_(0x10, 0x6E) ++#define REG_SC_BK10_6E_H _PK_H_(0x10, 0x6E) ++#define REG_SC_BK10_6F_L _PK_L_(0x10, 0x6F) ++#define REG_SC_BK10_6F_H _PK_H_(0x10, 0x6F) ++#define REG_SC_BK10_70_L _PK_L_(0x10, 0x70) ++#define REG_SC_BK10_70_H _PK_H_(0x10, 0x70) ++#define REG_SC_BK10_71_L _PK_L_(0x10, 0x71) ++#define REG_SC_BK10_71_H _PK_H_(0x10, 0x71) ++#define REG_SC_BK10_72_L _PK_L_(0x10, 0x72) ++#define REG_SC_BK10_72_H _PK_H_(0x10, 0x72) ++#define REG_SC_BK10_73_L _PK_L_(0x10, 0x73) ++#define REG_SC_BK10_73_H _PK_H_(0x10, 0x73) ++#define REG_SC_BK10_74_L _PK_L_(0x10, 0x74) ++#define REG_SC_BK10_74_H _PK_H_(0x10, 0x74) ++#define REG_SC_BK10_75_L _PK_L_(0x10, 0x75) ++#define REG_SC_BK10_75_H _PK_H_(0x10, 0x75) ++#define REG_SC_BK10_76_L _PK_L_(0x10, 0x76) ++#define REG_SC_BK10_76_H _PK_H_(0x10, 0x76) ++#define REG_SC_BK10_77_L _PK_L_(0x10, 0x77) ++#define REG_SC_BK10_77_H _PK_H_(0x10, 0x77) ++#define REG_SC_BK10_78_L _PK_L_(0x10, 0x78) ++#define REG_SC_BK10_78_H _PK_H_(0x10, 0x78) ++#define REG_SC_BK10_79_L _PK_L_(0x10, 0x79) ++#define REG_SC_BK10_79_H _PK_H_(0x10, 0x79) ++#define REG_SC_BK10_7A_L _PK_L_(0x10, 0x7A) ++#define REG_SC_BK10_7A_H _PK_H_(0x10, 0x7A) ++#define REG_SC_BK10_7B_L _PK_L_(0x10, 0x7B) ++#define REG_SC_BK10_7B_H _PK_H_(0x10, 0x7B) ++#define REG_SC_BK10_7C_L _PK_L_(0x10, 0x7C) ++#define REG_SC_BK10_7C_H _PK_H_(0x10, 0x7C) ++#define REG_SC_BK10_7D_L _PK_L_(0x10, 0x7D) ++#define REG_SC_BK10_7D_H _PK_H_(0x10, 0x7D) ++#define REG_SC_BK10_7E_L _PK_L_(0x10, 0x7E) ++#define REG_SC_BK10_7E_H _PK_H_(0x10, 0x7E) ++#define REG_SC_BK10_7F_L _PK_L_(0x10, 0x7F) ++#define REG_SC_BK10_7F_H _PK_H_(0x10, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK11_00_L _PK_L_(0x11, 0x00) ++#define REG_SC_BK11_00_H _PK_H_(0x11, 0x00) ++#define REG_SC_BK11_01_L _PK_L_(0x11, 0x01) ++#define REG_SC_BK11_01_H _PK_H_(0x11, 0x01) ++#define REG_SC_BK11_02_L _PK_L_(0x11, 0x02) ++#define REG_SC_BK11_02_H _PK_H_(0x11, 0x02) ++#define REG_SC_BK11_03_L _PK_L_(0x11, 0x03) ++#define REG_SC_BK11_03_H _PK_H_(0x11, 0x03) ++#define REG_SC_BK11_04_L _PK_L_(0x11, 0x04) ++#define REG_SC_BK11_04_H _PK_H_(0x11, 0x04) ++#define REG_SC_BK11_05_L _PK_L_(0x11, 0x05) ++#define REG_SC_BK11_05_H _PK_H_(0x11, 0x05) ++#define REG_SC_BK11_06_L _PK_L_(0x11, 0x06) ++#define REG_SC_BK11_06_H _PK_H_(0x11, 0x06) ++#define REG_SC_BK11_07_L _PK_L_(0x11, 0x07) ++#define REG_SC_BK11_07_H _PK_H_(0x11, 0x07) ++#define REG_SC_BK11_08_L _PK_L_(0x11, 0x08) ++#define REG_SC_BK11_08_H _PK_H_(0x11, 0x08) ++#define REG_SC_BK11_09_L _PK_L_(0x11, 0x09) ++#define REG_SC_BK11_09_H _PK_H_(0x11, 0x09) ++#define REG_SC_BK11_0A_L _PK_L_(0x11, 0x0A) ++#define REG_SC_BK11_0A_H _PK_H_(0x11, 0x0A) ++#define REG_SC_BK11_0B_L _PK_L_(0x11, 0x0B) ++#define REG_SC_BK11_0B_H _PK_H_(0x11, 0x0B) ++#define REG_SC_BK11_0C_L _PK_L_(0x11, 0x0C) ++#define REG_SC_BK11_0C_H _PK_H_(0x11, 0x0C) ++#define REG_SC_BK11_0D_L _PK_L_(0x11, 0x0D) ++#define REG_SC_BK11_0D_H _PK_H_(0x11, 0x0D) ++#define REG_SC_BK11_0E_L _PK_L_(0x11, 0x0E) ++#define REG_SC_BK11_0E_H _PK_H_(0x11, 0x0E) ++#define REG_SC_BK11_0F_L _PK_L_(0x11, 0x0F) ++#define REG_SC_BK11_0F_H _PK_H_(0x11, 0x0F) ++#define REG_SC_BK11_10_L _PK_L_(0x11, 0x10) ++#define REG_SC_BK11_10_H _PK_H_(0x11, 0x10) ++#define REG_SC_BK11_11_L _PK_L_(0x11, 0x11) ++#define REG_SC_BK11_11_H _PK_H_(0x11, 0x11) ++#define REG_SC_BK11_12_L _PK_L_(0x11, 0x12) ++#define REG_SC_BK11_12_H _PK_H_(0x11, 0x12) ++#define REG_SC_BK11_13_L _PK_L_(0x11, 0x13) ++#define REG_SC_BK11_13_H _PK_H_(0x11, 0x13) ++#define REG_SC_BK11_14_L _PK_L_(0x11, 0x14) ++#define REG_SC_BK11_14_H _PK_H_(0x11, 0x14) ++#define REG_SC_BK11_15_L _PK_L_(0x11, 0x15) ++#define REG_SC_BK11_15_H _PK_H_(0x11, 0x15) ++#define REG_SC_BK11_16_L _PK_L_(0x11, 0x16) ++#define REG_SC_BK11_16_H _PK_H_(0x11, 0x16) ++#define REG_SC_BK11_17_L _PK_L_(0x11, 0x17) ++#define REG_SC_BK11_17_H _PK_H_(0x11, 0x17) ++#define REG_SC_BK11_18_L _PK_L_(0x11, 0x18) ++#define REG_SC_BK11_18_H _PK_H_(0x11, 0x18) ++#define REG_SC_BK11_19_L _PK_L_(0x11, 0x19) ++#define REG_SC_BK11_19_H _PK_H_(0x11, 0x19) ++#define REG_SC_BK11_1A_L _PK_L_(0x11, 0x1A) ++#define REG_SC_BK11_1A_H _PK_H_(0x11, 0x1A) ++#define REG_SC_BK11_1B_L _PK_L_(0x11, 0x1B) ++#define REG_SC_BK11_1B_H _PK_H_(0x11, 0x1B) ++#define REG_SC_BK11_1C_L _PK_L_(0x11, 0x1C) ++#define REG_SC_BK11_1C_H _PK_H_(0x11, 0x1C) ++#define REG_SC_BK11_1D_L _PK_L_(0x11, 0x1D) ++#define REG_SC_BK11_1D_H _PK_H_(0x11, 0x1D) ++#define REG_SC_BK11_1E_L _PK_L_(0x11, 0x1E) ++#define REG_SC_BK11_1E_H _PK_H_(0x11, 0x1E) ++#define REG_SC_BK11_1F_L _PK_L_(0x11, 0x1F) ++#define REG_SC_BK11_1F_H _PK_H_(0x11, 0x1F) ++#define REG_SC_BK11_20_L _PK_L_(0x11, 0x20) ++#define REG_SC_BK11_20_H _PK_H_(0x11, 0x20) ++#define REG_SC_BK11_21_L _PK_L_(0x11, 0x21) ++#define REG_SC_BK11_21_H _PK_H_(0x11, 0x21) ++#define REG_SC_BK11_22_L _PK_L_(0x11, 0x22) ++#define REG_SC_BK11_22_H _PK_H_(0x11, 0x22) ++#define REG_SC_BK11_23_L _PK_L_(0x11, 0x23) ++#define REG_SC_BK11_23_H _PK_H_(0x11, 0x23) ++#define REG_SC_BK11_24_L _PK_L_(0x11, 0x24) ++#define REG_SC_BK11_24_H _PK_H_(0x11, 0x24) ++#define REG_SC_BK11_25_L _PK_L_(0x11, 0x25) ++#define REG_SC_BK11_25_H _PK_H_(0x11, 0x25) ++#define REG_SC_BK11_26_L _PK_L_(0x11, 0x26) ++#define REG_SC_BK11_26_H _PK_H_(0x11, 0x26) ++#define REG_SC_BK11_27_L _PK_L_(0x11, 0x27) ++#define REG_SC_BK11_27_H _PK_H_(0x11, 0x27) ++#define REG_SC_BK11_28_L _PK_L_(0x11, 0x28) ++#define REG_SC_BK11_28_H _PK_H_(0x11, 0x28) ++#define REG_SC_BK11_29_L _PK_L_(0x11, 0x29) ++#define REG_SC_BK11_29_H _PK_H_(0x11, 0x29) ++#define REG_SC_BK11_2A_L _PK_L_(0x11, 0x2A) ++#define REG_SC_BK11_2A_H _PK_H_(0x11, 0x2A) ++#define REG_SC_BK11_2B_L _PK_L_(0x11, 0x2B) ++#define REG_SC_BK11_2B_H _PK_H_(0x11, 0x2B) ++#define REG_SC_BK11_2C_L _PK_L_(0x11, 0x2C) ++#define REG_SC_BK11_2C_H _PK_H_(0x11, 0x2C) ++#define REG_SC_BK11_2D_L _PK_L_(0x11, 0x2D) ++#define REG_SC_BK11_2D_H _PK_H_(0x11, 0x2D) ++#define REG_SC_BK11_2E_L _PK_L_(0x11, 0x2E) ++#define REG_SC_BK11_2E_H _PK_H_(0x11, 0x2E) ++#define REG_SC_BK11_2F_L _PK_L_(0x11, 0x2F) ++#define REG_SC_BK11_2F_H _PK_H_(0x11, 0x2F) ++#define REG_SC_BK11_30_L _PK_L_(0x11, 0x30) ++#define REG_SC_BK11_30_H _PK_H_(0x11, 0x30) ++#define REG_SC_BK11_31_L _PK_L_(0x11, 0x31) ++#define REG_SC_BK11_31_H _PK_H_(0x11, 0x31) ++#define REG_SC_BK11_32_L _PK_L_(0x11, 0x32) ++#define REG_SC_BK11_32_H _PK_H_(0x11, 0x32) ++#define REG_SC_BK11_33_L _PK_L_(0x11, 0x33) ++#define REG_SC_BK11_33_H _PK_H_(0x11, 0x33) ++#define REG_SC_BK11_34_L _PK_L_(0x11, 0x34) ++#define REG_SC_BK11_34_H _PK_H_(0x11, 0x34) ++#define REG_SC_BK11_35_L _PK_L_(0x11, 0x35) ++#define REG_SC_BK11_35_H _PK_H_(0x11, 0x35) ++#define REG_SC_BK11_36_L _PK_L_(0x11, 0x36) ++#define REG_SC_BK11_36_H _PK_H_(0x11, 0x36) ++#define REG_SC_BK11_37_L _PK_L_(0x11, 0x37) ++#define REG_SC_BK11_37_H _PK_H_(0x11, 0x37) ++#define REG_SC_BK11_38_L _PK_L_(0x11, 0x38) ++#define REG_SC_BK11_38_H _PK_H_(0x11, 0x38) ++#define REG_SC_BK11_39_L _PK_L_(0x11, 0x39) ++#define REG_SC_BK11_39_H _PK_H_(0x11, 0x39) ++#define REG_SC_BK11_3A_L _PK_L_(0x11, 0x3A) ++#define REG_SC_BK11_3A_H _PK_H_(0x11, 0x3A) ++#define REG_SC_BK11_3B_L _PK_L_(0x11, 0x3B) ++#define REG_SC_BK11_3B_H _PK_H_(0x11, 0x3B) ++#define REG_SC_BK11_3C_L _PK_L_(0x11, 0x3C) ++#define REG_SC_BK11_3C_H _PK_H_(0x11, 0x3C) ++#define REG_SC_BK11_3D_L _PK_L_(0x11, 0x3D) ++#define REG_SC_BK11_3D_H _PK_H_(0x11, 0x3D) ++#define REG_SC_BK11_3E_L _PK_L_(0x11, 0x3E) ++#define REG_SC_BK11_3E_H _PK_H_(0x11, 0x3E) ++#define REG_SC_BK11_3F_L _PK_L_(0x11, 0x3F) ++#define REG_SC_BK11_3F_H _PK_H_(0x11, 0x3F) ++#define REG_SC_BK11_40_L _PK_L_(0x11, 0x40) ++#define REG_SC_BK11_40_H _PK_H_(0x11, 0x40) ++#define REG_SC_BK11_41_L _PK_L_(0x11, 0x41) ++#define REG_SC_BK11_41_H _PK_H_(0x11, 0x41) ++#define REG_SC_BK11_42_L _PK_L_(0x11, 0x42) ++#define REG_SC_BK11_42_H _PK_H_(0x11, 0x42) ++#define REG_SC_BK11_43_L _PK_L_(0x11, 0x43) ++#define REG_SC_BK11_43_H _PK_H_(0x11, 0x43) ++#define REG_SC_BK11_44_L _PK_L_(0x11, 0x44) ++#define REG_SC_BK11_44_H _PK_H_(0x11, 0x44) ++#define REG_SC_BK11_45_L _PK_L_(0x11, 0x45) ++#define REG_SC_BK11_45_H _PK_H_(0x11, 0x45) ++#define REG_SC_BK11_46_L _PK_L_(0x11, 0x46) ++#define REG_SC_BK11_46_H _PK_H_(0x11, 0x46) ++#define REG_SC_BK11_47_L _PK_L_(0x11, 0x47) ++#define REG_SC_BK11_47_H _PK_H_(0x11, 0x47) ++#define REG_SC_BK11_48_L _PK_L_(0x11, 0x48) ++#define REG_SC_BK11_48_H _PK_H_(0x11, 0x48) ++#define REG_SC_BK11_49_L _PK_L_(0x11, 0x49) ++#define REG_SC_BK11_49_H _PK_H_(0x11, 0x49) ++#define REG_SC_BK11_4A_L _PK_L_(0x11, 0x4A) ++#define REG_SC_BK11_4A_H _PK_H_(0x11, 0x4A) ++#define REG_SC_BK11_4B_L _PK_L_(0x11, 0x4B) ++#define REG_SC_BK11_4B_H _PK_H_(0x11, 0x4B) ++#define REG_SC_BK11_4C_L _PK_L_(0x11, 0x4C) ++#define REG_SC_BK11_4C_H _PK_H_(0x11, 0x4C) ++#define REG_SC_BK11_4D_L _PK_L_(0x11, 0x4D) ++#define REG_SC_BK11_4D_H _PK_H_(0x11, 0x4D) ++#define REG_SC_BK11_4E_L _PK_L_(0x11, 0x4E) ++#define REG_SC_BK11_4E_H _PK_H_(0x11, 0x4E) ++#define REG_SC_BK11_4F_L _PK_L_(0x11, 0x4F) ++#define REG_SC_BK11_4F_H _PK_H_(0x11, 0x4F) ++#define REG_SC_BK11_50_L _PK_L_(0x11, 0x50) ++#define REG_SC_BK11_50_H _PK_H_(0x11, 0x50) ++#define REG_SC_BK11_51_L _PK_L_(0x11, 0x51) ++#define REG_SC_BK11_51_H _PK_H_(0x11, 0x51) ++#define REG_SC_BK11_52_L _PK_L_(0x11, 0x52) ++#define REG_SC_BK11_52_H _PK_H_(0x11, 0x52) ++#define REG_SC_BK11_53_L _PK_L_(0x11, 0x53) ++#define REG_SC_BK11_53_H _PK_H_(0x11, 0x53) ++#define REG_SC_BK11_54_L _PK_L_(0x11, 0x54) ++#define REG_SC_BK11_54_H _PK_H_(0x11, 0x54) ++#define REG_SC_BK11_55_L _PK_L_(0x11, 0x55) ++#define REG_SC_BK11_55_H _PK_H_(0x11, 0x55) ++#define REG_SC_BK11_56_L _PK_L_(0x11, 0x56) ++#define REG_SC_BK11_56_H _PK_H_(0x11, 0x56) ++#define REG_SC_BK11_57_L _PK_L_(0x11, 0x57) ++#define REG_SC_BK11_57_H _PK_H_(0x11, 0x57) ++#define REG_SC_BK11_58_L _PK_L_(0x11, 0x58) ++#define REG_SC_BK11_58_H _PK_H_(0x11, 0x58) ++#define REG_SC_BK11_59_L _PK_L_(0x11, 0x59) ++#define REG_SC_BK11_59_H _PK_H_(0x11, 0x59) ++#define REG_SC_BK11_5A_L _PK_L_(0x11, 0x5A) ++#define REG_SC_BK11_5A_H _PK_H_(0x11, 0x5A) ++#define REG_SC_BK11_5B_L _PK_L_(0x11, 0x5B) ++#define REG_SC_BK11_5B_H _PK_H_(0x11, 0x5B) ++#define REG_SC_BK11_5C_L _PK_L_(0x11, 0x5C) ++#define REG_SC_BK11_5C_H _PK_H_(0x11, 0x5C) ++#define REG_SC_BK11_5D_L _PK_L_(0x11, 0x5D) ++#define REG_SC_BK11_5D_H _PK_H_(0x11, 0x5D) ++#define REG_SC_BK11_5E_L _PK_L_(0x11, 0x5E) ++#define REG_SC_BK11_5E_H _PK_H_(0x11, 0x5E) ++#define REG_SC_BK11_5F_L _PK_L_(0x11, 0x5F) ++#define REG_SC_BK11_5F_H _PK_H_(0x11, 0x5F) ++#define REG_SC_BK11_60_L _PK_L_(0x11, 0x60) ++#define REG_SC_BK11_60_H _PK_H_(0x11, 0x60) ++#define REG_SC_BK11_61_L _PK_L_(0x11, 0x61) ++#define REG_SC_BK11_61_H _PK_H_(0x11, 0x61) ++#define REG_SC_BK11_62_L _PK_L_(0x11, 0x62) ++#define REG_SC_BK11_62_H _PK_H_(0x11, 0x62) ++#define REG_SC_BK11_63_L _PK_L_(0x11, 0x63) ++#define REG_SC_BK11_63_H _PK_H_(0x11, 0x63) ++#define REG_SC_BK11_64_L _PK_L_(0x11, 0x64) ++#define REG_SC_BK11_64_H _PK_H_(0x11, 0x64) ++#define REG_SC_BK11_65_L _PK_L_(0x11, 0x65) ++#define REG_SC_BK11_65_H _PK_H_(0x11, 0x65) ++#define REG_SC_BK11_66_L _PK_L_(0x11, 0x66) ++#define REG_SC_BK11_66_H _PK_H_(0x11, 0x66) ++#define REG_SC_BK11_67_L _PK_L_(0x11, 0x67) ++#define REG_SC_BK11_67_H _PK_H_(0x11, 0x67) ++#define REG_SC_BK11_68_L _PK_L_(0x11, 0x68) ++#define REG_SC_BK11_68_H _PK_H_(0x11, 0x68) ++#define REG_SC_BK11_69_L _PK_L_(0x11, 0x69) ++#define REG_SC_BK11_69_H _PK_H_(0x11, 0x69) ++#define REG_SC_BK11_6A_L _PK_L_(0x11, 0x6A) ++#define REG_SC_BK11_6A_H _PK_H_(0x11, 0x6A) ++#define REG_SC_BK11_6B_L _PK_L_(0x11, 0x6B) ++#define REG_SC_BK11_6B_H _PK_H_(0x11, 0x6B) ++#define REG_SC_BK11_6C_L _PK_L_(0x11, 0x6C) ++#define REG_SC_BK11_6C_H _PK_H_(0x11, 0x6C) ++#define REG_SC_BK11_6D_L _PK_L_(0x11, 0x6D) ++#define REG_SC_BK11_6D_H _PK_H_(0x11, 0x6D) ++#define REG_SC_BK11_6E_L _PK_L_(0x11, 0x6E) ++#define REG_SC_BK11_6E_H _PK_H_(0x11, 0x6E) ++#define REG_SC_BK11_6F_L _PK_L_(0x11, 0x6F) ++#define REG_SC_BK11_6F_H _PK_H_(0x11, 0x6F) ++#define REG_SC_BK11_70_L _PK_L_(0x11, 0x70) ++#define REG_SC_BK11_70_H _PK_H_(0x11, 0x70) ++#define REG_SC_BK11_71_L _PK_L_(0x11, 0x71) ++#define REG_SC_BK11_71_H _PK_H_(0x11, 0x71) ++#define REG_SC_BK11_72_L _PK_L_(0x11, 0x72) ++#define REG_SC_BK11_72_H _PK_H_(0x11, 0x72) ++#define REG_SC_BK11_73_L _PK_L_(0x11, 0x73) ++#define REG_SC_BK11_73_H _PK_H_(0x11, 0x73) ++#define REG_SC_BK11_74_L _PK_L_(0x11, 0x74) ++#define REG_SC_BK11_74_H _PK_H_(0x11, 0x74) ++#define REG_SC_BK11_75_L _PK_L_(0x11, 0x75) ++#define REG_SC_BK11_75_H _PK_H_(0x11, 0x75) ++#define REG_SC_BK11_76_L _PK_L_(0x11, 0x76) ++#define REG_SC_BK11_76_H _PK_H_(0x11, 0x76) ++#define REG_SC_BK11_77_L _PK_L_(0x11, 0x77) ++#define REG_SC_BK11_77_H _PK_H_(0x11, 0x77) ++#define REG_SC_BK11_78_L _PK_L_(0x11, 0x78) ++#define REG_SC_BK11_78_H _PK_H_(0x11, 0x78) ++#define REG_SC_BK11_79_L _PK_L_(0x11, 0x79) ++#define REG_SC_BK11_79_H _PK_H_(0x11, 0x79) ++#define REG_SC_BK11_7A_L _PK_L_(0x11, 0x7A) ++#define REG_SC_BK11_7A_H _PK_H_(0x11, 0x7A) ++#define REG_SC_BK11_7B_L _PK_L_(0x11, 0x7B) ++#define REG_SC_BK11_7B_H _PK_H_(0x11, 0x7B) ++#define REG_SC_BK11_7C_L _PK_L_(0x11, 0x7C) ++#define REG_SC_BK11_7C_H _PK_H_(0x11, 0x7C) ++#define REG_SC_BK11_7D_L _PK_L_(0x11, 0x7D) ++#define REG_SC_BK11_7D_H _PK_H_(0x11, 0x7D) ++#define REG_SC_BK11_7E_L _PK_L_(0x11, 0x7E) ++#define REG_SC_BK11_7E_H _PK_H_(0x11, 0x7E) ++#define REG_SC_BK11_7F_L _PK_L_(0x11, 0x7F) ++#define REG_SC_BK11_7F_H _PK_H_(0x11, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK12_00_L _PK_L_(0x12, 0x00) ++#define REG_SC_BK12_00_H _PK_H_(0x12, 0x00) ++#define REG_SC_BK12_01_L _PK_L_(0x12, 0x01) ++#define REG_SC_BK12_01_H _PK_H_(0x12, 0x01) ++#define REG_SC_BK12_02_L _PK_L_(0x12, 0x02) ++#define REG_SC_BK12_02_H _PK_H_(0x12, 0x02) ++#define REG_SC_BK12_03_L _PK_L_(0x12, 0x03) ++#define REG_SC_BK12_03_H _PK_H_(0x12, 0x03) ++#define REG_SC_BK12_04_L _PK_L_(0x12, 0x04) ++#define REG_SC_BK12_04_H _PK_H_(0x12, 0x04) ++#define REG_SC_BK12_05_L _PK_L_(0x12, 0x05) ++#define REG_SC_BK12_05_H _PK_H_(0x12, 0x05) ++#define REG_SC_BK12_06_L _PK_L_(0x12, 0x06) ++#define REG_SC_BK12_06_H _PK_H_(0x12, 0x06) ++#define REG_SC_BK12_07_L _PK_L_(0x12, 0x07) ++#define REG_SC_BK12_07_H _PK_H_(0x12, 0x07) ++#define REG_SC_BK12_08_L _PK_L_(0x12, 0x08) ++#define REG_SC_BK12_08_H _PK_H_(0x12, 0x08) ++#define REG_SC_BK12_09_L _PK_L_(0x12, 0x09) ++#define REG_SC_BK12_09_H _PK_H_(0x12, 0x09) ++#define REG_SC_BK12_0A_L _PK_L_(0x12, 0x0A) ++#define REG_SC_BK12_0A_H _PK_H_(0x12, 0x0A) ++#define REG_SC_BK12_0B_L _PK_L_(0x12, 0x0B) ++#define REG_SC_BK12_0B_H _PK_H_(0x12, 0x0B) ++#define REG_SC_BK12_0C_L _PK_L_(0x12, 0x0C) ++#define REG_SC_BK12_0C_H _PK_H_(0x12, 0x0C) ++#define REG_SC_BK12_0D_L _PK_L_(0x12, 0x0D) ++#define REG_SC_BK12_0D_H _PK_H_(0x12, 0x0D) ++#define REG_SC_BK12_0E_L _PK_L_(0x12, 0x0E) ++#define REG_SC_BK12_0E_H _PK_H_(0x12, 0x0E) ++#define REG_SC_BK12_0F_L _PK_L_(0x12, 0x0F) ++#define REG_SC_BK12_0F_H _PK_H_(0x12, 0x0F) ++#define REG_SC_BK12_10_L _PK_L_(0x12, 0x10) ++#define REG_SC_BK12_10_H _PK_H_(0x12, 0x10) ++#define REG_SC_BK12_11_L _PK_L_(0x12, 0x11) ++#define REG_SC_BK12_11_H _PK_H_(0x12, 0x11) ++#define REG_SC_BK12_12_L _PK_L_(0x12, 0x12) ++#define REG_SC_BK12_12_H _PK_H_(0x12, 0x12) ++#define REG_SC_BK12_13_L _PK_L_(0x12, 0x13) ++#define REG_SC_BK12_13_H _PK_H_(0x12, 0x13) ++#define REG_SC_BK12_14_L _PK_L_(0x12, 0x14) ++#define REG_SC_BK12_14_H _PK_H_(0x12, 0x14) ++#define REG_SC_BK12_15_L _PK_L_(0x12, 0x15) ++#define REG_SC_BK12_15_H _PK_H_(0x12, 0x15) ++#define REG_SC_BK12_16_L _PK_L_(0x12, 0x16) ++#define REG_SC_BK12_16_H _PK_H_(0x12, 0x16) ++#define REG_SC_BK12_17_L _PK_L_(0x12, 0x17) ++#define REG_SC_BK12_17_H _PK_H_(0x12, 0x17) ++#define REG_SC_BK12_18_L _PK_L_(0x12, 0x18) ++#define REG_SC_BK12_18_H _PK_H_(0x12, 0x18) ++#define REG_SC_BK12_19_L _PK_L_(0x12, 0x19) ++#define REG_SC_BK12_19_H _PK_H_(0x12, 0x19) ++#define REG_SC_BK12_1A_L _PK_L_(0x12, 0x1A) ++#define REG_SC_BK12_1A_H _PK_H_(0x12, 0x1A) ++#define REG_SC_BK12_1B_L _PK_L_(0x12, 0x1B) ++#define REG_SC_BK12_1B_H _PK_H_(0x12, 0x1B) ++#define REG_SC_BK12_1C_L _PK_L_(0x12, 0x1C) ++#define REG_SC_BK12_1C_H _PK_H_(0x12, 0x1C) ++#define REG_SC_BK12_1D_L _PK_L_(0x12, 0x1D) ++#define REG_SC_BK12_1D_H _PK_H_(0x12, 0x1D) ++#define REG_SC_BK12_1E_L _PK_L_(0x12, 0x1E) ++#define REG_SC_BK12_1E_H _PK_H_(0x12, 0x1E) ++#define REG_SC_BK12_1F_L _PK_L_(0x12, 0x1F) ++#define REG_SC_BK12_1F_H _PK_H_(0x12, 0x1F) ++#define REG_SC_BK12_20_L _PK_L_(0x12, 0x20) ++#define REG_SC_BK12_20_H _PK_H_(0x12, 0x20) ++#define REG_SC_BK12_21_L _PK_L_(0x12, 0x21) ++#define REG_SC_BK12_21_H _PK_H_(0x12, 0x21) ++#define REG_SC_BK12_22_L _PK_L_(0x12, 0x22) ++#define REG_SC_BK12_22_H _PK_H_(0x12, 0x22) ++#define REG_SC_BK12_23_L _PK_L_(0x12, 0x23) ++#define REG_SC_BK12_23_H _PK_H_(0x12, 0x23) ++#define REG_SC_BK12_24_L _PK_L_(0x12, 0x24) ++#define REG_SC_BK12_24_H _PK_H_(0x12, 0x24) ++#define REG_SC_BK12_25_L _PK_L_(0x12, 0x25) ++#define REG_SC_BK12_25_H _PK_H_(0x12, 0x25) ++#define REG_SC_BK12_26_L _PK_L_(0x12, 0x26) ++#define REG_SC_BK12_26_H _PK_H_(0x12, 0x26) ++#define REG_SC_BK12_27_L _PK_L_(0x12, 0x27) ++#define REG_SC_BK12_27_H _PK_H_(0x12, 0x27) ++#define REG_SC_BK12_28_L _PK_L_(0x12, 0x28) ++#define REG_SC_BK12_28_H _PK_H_(0x12, 0x28) ++#define REG_SC_BK12_29_L _PK_L_(0x12, 0x29) ++#define REG_SC_BK12_29_H _PK_H_(0x12, 0x29) ++#define REG_SC_BK12_2A_L _PK_L_(0x12, 0x2A) ++#define REG_SC_BK12_2A_H _PK_H_(0x12, 0x2A) ++#define REG_SC_BK12_2B_L _PK_L_(0x12, 0x2B) ++#define REG_SC_BK12_2B_H _PK_H_(0x12, 0x2B) ++#define REG_SC_BK12_2C_L _PK_L_(0x12, 0x2C) ++#define REG_SC_BK12_2C_H _PK_H_(0x12, 0x2C) ++#define REG_SC_BK12_2D_L _PK_L_(0x12, 0x2D) ++#define REG_SC_BK12_2D_H _PK_H_(0x12, 0x2D) ++#define REG_SC_BK12_2E_L _PK_L_(0x12, 0x2E) ++#define REG_SC_BK12_2E_H _PK_H_(0x12, 0x2E) ++#define REG_SC_BK12_2F_L _PK_L_(0x12, 0x2F) ++#define REG_SC_BK12_2F_H _PK_H_(0x12, 0x2F) ++#define REG_SC_BK12_30_L _PK_L_(0x12, 0x30) ++#define REG_SC_BK12_30_H _PK_H_(0x12, 0x30) ++#define REG_SC_BK12_31_L _PK_L_(0x12, 0x31) ++#define REG_SC_BK12_31_H _PK_H_(0x12, 0x31) ++#define REG_SC_BK12_32_L _PK_L_(0x12, 0x32) ++#define REG_SC_BK12_32_H _PK_H_(0x12, 0x32) ++#define REG_SC_BK12_33_L _PK_L_(0x12, 0x33) ++#define REG_SC_BK12_33_H _PK_H_(0x12, 0x33) ++#define REG_SC_BK12_34_L _PK_L_(0x12, 0x34) ++#define REG_SC_BK12_34_H _PK_H_(0x12, 0x34) ++#define REG_SC_BK12_35_L _PK_L_(0x12, 0x35) ++#define REG_SC_BK12_35_H _PK_H_(0x12, 0x35) ++#define REG_SC_BK12_36_L _PK_L_(0x12, 0x36) ++#define REG_SC_BK12_36_H _PK_H_(0x12, 0x36) ++#define REG_SC_BK12_37_L _PK_L_(0x12, 0x37) ++#define REG_SC_BK12_37_H _PK_H_(0x12, 0x37) ++#define REG_SC_BK12_38_L _PK_L_(0x12, 0x38) ++#define REG_SC_BK12_38_H _PK_H_(0x12, 0x38) ++#define REG_SC_BK12_39_L _PK_L_(0x12, 0x39) ++#define REG_SC_BK12_39_H _PK_H_(0x12, 0x39) ++#define REG_SC_BK12_3A_L _PK_L_(0x12, 0x3A) ++#define REG_SC_BK12_3A_H _PK_H_(0x12, 0x3A) ++#define REG_SC_BK12_3B_L _PK_L_(0x12, 0x3B) ++#define REG_SC_BK12_3B_H _PK_H_(0x12, 0x3B) ++#define REG_SC_BK12_3C_L _PK_L_(0x12, 0x3C) ++#define REG_SC_BK12_3C_H _PK_H_(0x12, 0x3C) ++#define REG_SC_BK12_3D_L _PK_L_(0x12, 0x3D) ++#define REG_SC_BK12_3D_H _PK_H_(0x12, 0x3D) ++#define REG_SC_BK12_3E_L _PK_L_(0x12, 0x3E) ++#define REG_SC_BK12_3E_H _PK_H_(0x12, 0x3E) ++#define REG_SC_BK12_3F_L _PK_L_(0x12, 0x3F) ++#define REG_SC_BK12_3F_H _PK_H_(0x12, 0x3F) ++#define REG_SC_BK12_40_L _PK_L_(0x12, 0x40) ++#define REG_SC_BK12_40_H _PK_H_(0x12, 0x40) ++#define REG_SC_BK12_41_L _PK_L_(0x12, 0x41) ++#define REG_SC_BK12_41_H _PK_H_(0x12, 0x41) ++#define REG_SC_BK12_42_L _PK_L_(0x12, 0x42) ++#define REG_SC_BK12_42_H _PK_H_(0x12, 0x42) ++#define REG_SC_BK12_43_L _PK_L_(0x12, 0x43) ++#define REG_SC_BK12_43_H _PK_H_(0x12, 0x43) ++#define REG_SC_BK12_44_L _PK_L_(0x12, 0x44) ++#define REG_SC_BK12_44_H _PK_H_(0x12, 0x44) ++#define REG_SC_BK12_45_L _PK_L_(0x12, 0x45) ++#define REG_SC_BK12_45_H _PK_H_(0x12, 0x45) ++#define REG_SC_BK12_46_L _PK_L_(0x12, 0x46) ++#define REG_SC_BK12_46_H _PK_H_(0x12, 0x46) ++#define REG_SC_BK12_47_L _PK_L_(0x12, 0x47) ++#define REG_SC_BK12_47_H _PK_H_(0x12, 0x47) ++#define REG_SC_BK12_48_L _PK_L_(0x12, 0x48) ++#define REG_SC_BK12_48_H _PK_H_(0x12, 0x48) ++#define REG_SC_BK12_49_L _PK_L_(0x12, 0x49) ++#define REG_SC_BK12_49_H _PK_H_(0x12, 0x49) ++#define REG_SC_BK12_4A_L _PK_L_(0x12, 0x4A) ++#define REG_SC_BK12_4A_H _PK_H_(0x12, 0x4A) ++#define REG_SC_BK12_4B_L _PK_L_(0x12, 0x4B) ++#define REG_SC_BK12_4B_H _PK_H_(0x12, 0x4B) ++#define REG_SC_BK12_4C_L _PK_L_(0x12, 0x4C) ++#define REG_SC_BK12_4C_H _PK_H_(0x12, 0x4C) ++#define REG_SC_BK12_4D_L _PK_L_(0x12, 0x4D) ++#define REG_SC_BK12_4D_H _PK_H_(0x12, 0x4D) ++#define REG_SC_BK12_4E_L _PK_L_(0x12, 0x4E) ++#define REG_SC_BK12_4E_H _PK_H_(0x12, 0x4E) ++#define REG_SC_BK12_4F_L _PK_L_(0x12, 0x4F) ++#define REG_SC_BK12_4F_H _PK_H_(0x12, 0x4F) ++#define REG_SC_BK12_50_L _PK_L_(0x12, 0x50) ++#define REG_SC_BK12_50_H _PK_H_(0x12, 0x50) ++#define REG_SC_BK12_51_L _PK_L_(0x12, 0x51) ++#define REG_SC_BK12_51_H _PK_H_(0x12, 0x51) ++#define REG_SC_BK12_52_L _PK_L_(0x12, 0x52) ++#define REG_SC_BK12_52_H _PK_H_(0x12, 0x52) ++#define REG_SC_BK12_53_L _PK_L_(0x12, 0x53) ++#define REG_SC_BK12_53_H _PK_H_(0x12, 0x53) ++#define REG_SC_BK12_54_L _PK_L_(0x12, 0x54) ++#define REG_SC_BK12_54_H _PK_H_(0x12, 0x54) ++#define REG_SC_BK12_55_L _PK_L_(0x12, 0x55) ++#define REG_SC_BK12_55_H _PK_H_(0x12, 0x55) ++#define REG_SC_BK12_56_L _PK_L_(0x12, 0x56) ++#define REG_SC_BK12_56_H _PK_H_(0x12, 0x56) ++#define REG_SC_BK12_57_L _PK_L_(0x12, 0x57) ++#define REG_SC_BK12_57_H _PK_H_(0x12, 0x57) ++#define REG_SC_BK12_58_L _PK_L_(0x12, 0x58) ++#define REG_SC_BK12_58_H _PK_H_(0x12, 0x58) ++#define REG_SC_BK12_59_L _PK_L_(0x12, 0x59) ++#define REG_SC_BK12_59_H _PK_H_(0x12, 0x59) ++#define REG_SC_BK12_5A_L _PK_L_(0x12, 0x5A) ++#define REG_SC_BK12_5A_H _PK_H_(0x12, 0x5A) ++#define REG_SC_BK12_5B_L _PK_L_(0x12, 0x5B) ++#define REG_SC_BK12_5B_H _PK_H_(0x12, 0x5B) ++#define REG_SC_BK12_5C_L _PK_L_(0x12, 0x5C) ++#define REG_SC_BK12_5C_H _PK_H_(0x12, 0x5C) ++#define REG_SC_BK12_5D_L _PK_L_(0x12, 0x5D) ++#define REG_SC_BK12_5D_H _PK_H_(0x12, 0x5D) ++#define REG_SC_BK12_5E_L _PK_L_(0x12, 0x5E) ++#define REG_SC_BK12_5E_H _PK_H_(0x12, 0x5E) ++#define REG_SC_BK12_5F_L _PK_L_(0x12, 0x5F) ++#define REG_SC_BK12_5F_H _PK_H_(0x12, 0x5F) ++#define REG_SC_BK12_60_L _PK_L_(0x12, 0x60) ++#define REG_SC_BK12_60_H _PK_H_(0x12, 0x60) ++#define REG_SC_BK12_61_L _PK_L_(0x12, 0x61) ++#define REG_SC_BK12_61_H _PK_H_(0x12, 0x61) ++#define REG_SC_BK12_62_L _PK_L_(0x12, 0x62) ++#define REG_SC_BK12_62_H _PK_H_(0x12, 0x62) ++#define REG_SC_BK12_63_L _PK_L_(0x12, 0x63) ++#define REG_SC_BK12_63_H _PK_H_(0x12, 0x63) ++#define REG_SC_BK12_64_L _PK_L_(0x12, 0x64) ++#define REG_SC_BK12_64_H _PK_H_(0x12, 0x64) ++#define REG_SC_BK12_65_L _PK_L_(0x12, 0x65) ++#define REG_SC_BK12_65_H _PK_H_(0x12, 0x65) ++#define REG_SC_BK12_66_L _PK_L_(0x12, 0x66) ++#define REG_SC_BK12_66_H _PK_H_(0x12, 0x66) ++#define REG_SC_BK12_67_L _PK_L_(0x12, 0x67) ++#define REG_SC_BK12_67_H _PK_H_(0x12, 0x67) ++#define REG_SC_BK12_68_L _PK_L_(0x12, 0x68) ++#define REG_SC_BK12_68_H _PK_H_(0x12, 0x68) ++#define REG_SC_BK12_69_L _PK_L_(0x12, 0x69) ++#define REG_SC_BK12_69_H _PK_H_(0x12, 0x69) ++#define REG_SC_BK12_6A_L _PK_L_(0x12, 0x6A) ++#define REG_SC_BK12_6A_H _PK_H_(0x12, 0x6A) ++#define REG_SC_BK12_6B_L _PK_L_(0x12, 0x6B) ++#define REG_SC_BK12_6B_H _PK_H_(0x12, 0x6B) ++#define REG_SC_BK12_6C_L _PK_L_(0x12, 0x6C) ++#define REG_SC_BK12_6C_H _PK_H_(0x12, 0x6C) ++#define REG_SC_BK12_6D_L _PK_L_(0x12, 0x6D) ++#define REG_SC_BK12_6D_H _PK_H_(0x12, 0x6D) ++#define REG_SC_BK12_6E_L _PK_L_(0x12, 0x6E) ++#define REG_SC_BK12_6E_H _PK_H_(0x12, 0x6E) ++#define REG_SC_BK12_6F_L _PK_L_(0x12, 0x6F) ++#define REG_SC_BK12_6F_H _PK_H_(0x12, 0x6F) ++#define REG_SC_BK12_70_L _PK_L_(0x12, 0x70) ++#define REG_SC_BK12_70_H _PK_H_(0x12, 0x70) ++#define REG_SC_BK12_71_L _PK_L_(0x12, 0x71) ++#define REG_SC_BK12_71_H _PK_H_(0x12, 0x71) ++#define REG_SC_BK12_72_L _PK_L_(0x12, 0x72) ++#define REG_SC_BK12_72_H _PK_H_(0x12, 0x72) ++#define REG_SC_BK12_73_L _PK_L_(0x12, 0x73) ++#define REG_SC_BK12_73_H _PK_H_(0x12, 0x73) ++#define REG_SC_BK12_74_L _PK_L_(0x12, 0x74) ++#define REG_SC_BK12_74_H _PK_H_(0x12, 0x74) ++#define REG_SC_BK12_75_L _PK_L_(0x12, 0x75) ++#define REG_SC_BK12_75_H _PK_H_(0x12, 0x75) ++#define REG_SC_BK12_76_L _PK_L_(0x12, 0x76) ++#define REG_SC_BK12_76_H _PK_H_(0x12, 0x76) ++#define REG_SC_BK12_77_L _PK_L_(0x12, 0x77) ++#define REG_SC_BK12_77_H _PK_H_(0x12, 0x77) ++#define REG_SC_BK12_78_L _PK_L_(0x12, 0x78) ++#define REG_SC_BK12_78_H _PK_H_(0x12, 0x78) ++#define REG_SC_BK12_79_L _PK_L_(0x12, 0x79) ++#define REG_SC_BK12_79_H _PK_H_(0x12, 0x79) ++#define REG_SC_BK12_7A_L _PK_L_(0x12, 0x7A) ++#define REG_SC_BK12_7A_H _PK_H_(0x12, 0x7A) ++#define REG_SC_BK12_7B_L _PK_L_(0x12, 0x7B) ++#define REG_SC_BK12_7B_H _PK_H_(0x12, 0x7B) ++#define REG_SC_BK12_7C_L _PK_L_(0x12, 0x7C) ++#define REG_SC_BK12_7C_H _PK_H_(0x12, 0x7C) ++#define REG_SC_BK12_7D_L _PK_L_(0x12, 0x7D) ++#define REG_SC_BK12_7D_H _PK_H_(0x12, 0x7D) ++#define REG_SC_BK12_7E_L _PK_L_(0x12, 0x7E) ++#define REG_SC_BK12_7E_H _PK_H_(0x12, 0x7E) ++#define REG_SC_BK12_7F_L _PK_L_(0x12, 0x7F) ++#define REG_SC_BK12_7F_H _PK_H_(0x12, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK13_00_L _PK_L_(0x13, 0x00) ++#define REG_SC_BK13_00_H _PK_H_(0x13, 0x00) ++#define REG_SC_BK13_01_L _PK_L_(0x13, 0x01) ++#define REG_SC_BK13_01_H _PK_H_(0x13, 0x01) ++#define REG_SC_BK13_02_L _PK_L_(0x13, 0x02) ++#define REG_SC_BK13_02_H _PK_H_(0x13, 0x02) ++#define REG_SC_BK13_03_L _PK_L_(0x13, 0x03) ++#define REG_SC_BK13_03_H _PK_H_(0x13, 0x03) ++#define REG_SC_BK13_04_L _PK_L_(0x13, 0x04) ++#define REG_SC_BK13_04_H _PK_H_(0x13, 0x04) ++#define REG_SC_BK13_05_L _PK_L_(0x13, 0x05) ++#define REG_SC_BK13_05_H _PK_H_(0x13, 0x05) ++#define REG_SC_BK13_06_L _PK_L_(0x13, 0x06) ++#define REG_SC_BK13_06_H _PK_H_(0x13, 0x06) ++#define REG_SC_BK13_07_L _PK_L_(0x13, 0x07) ++#define REG_SC_BK13_07_H _PK_H_(0x13, 0x07) ++#define REG_SC_BK13_08_L _PK_L_(0x13, 0x08) ++#define REG_SC_BK13_08_H _PK_H_(0x13, 0x08) ++#define REG_SC_BK13_09_L _PK_L_(0x13, 0x09) ++#define REG_SC_BK13_09_H _PK_H_(0x13, 0x09) ++#define REG_SC_BK13_0A_L _PK_L_(0x13, 0x0A) ++#define REG_SC_BK13_0A_H _PK_H_(0x13, 0x0A) ++#define REG_SC_BK13_0B_L _PK_L_(0x13, 0x0B) ++#define REG_SC_BK13_0B_H _PK_H_(0x13, 0x0B) ++#define REG_SC_BK13_0C_L _PK_L_(0x13, 0x0C) ++#define REG_SC_BK13_0C_H _PK_H_(0x13, 0x0C) ++#define REG_SC_BK13_0D_L _PK_L_(0x13, 0x0D) ++#define REG_SC_BK13_0D_H _PK_H_(0x13, 0x0D) ++#define REG_SC_BK13_0E_L _PK_L_(0x13, 0x0E) ++#define REG_SC_BK13_0E_H _PK_H_(0x13, 0x0E) ++#define REG_SC_BK13_0F_L _PK_L_(0x13, 0x0F) ++#define REG_SC_BK13_0F_H _PK_H_(0x13, 0x0F) ++#define REG_SC_BK13_10_L _PK_L_(0x13, 0x10) ++#define REG_SC_BK13_10_H _PK_H_(0x13, 0x10) ++#define REG_SC_BK13_11_L _PK_L_(0x13, 0x11) ++#define REG_SC_BK13_11_H _PK_H_(0x13, 0x11) ++#define REG_SC_BK13_12_L _PK_L_(0x13, 0x12) ++#define REG_SC_BK13_12_H _PK_H_(0x13, 0x12) ++#define REG_SC_BK13_13_L _PK_L_(0x13, 0x13) ++#define REG_SC_BK13_13_H _PK_H_(0x13, 0x13) ++#define REG_SC_BK13_14_L _PK_L_(0x13, 0x14) ++#define REG_SC_BK13_14_H _PK_H_(0x13, 0x14) ++#define REG_SC_BK13_15_L _PK_L_(0x13, 0x15) ++#define REG_SC_BK13_15_H _PK_H_(0x13, 0x15) ++#define REG_SC_BK13_16_L _PK_L_(0x13, 0x16) ++#define REG_SC_BK13_16_H _PK_H_(0x13, 0x16) ++#define REG_SC_BK13_17_L _PK_L_(0x13, 0x17) ++#define REG_SC_BK13_17_H _PK_H_(0x13, 0x17) ++#define REG_SC_BK13_18_L _PK_L_(0x13, 0x18) ++#define REG_SC_BK13_18_H _PK_H_(0x13, 0x18) ++#define REG_SC_BK13_19_L _PK_L_(0x13, 0x19) ++#define REG_SC_BK13_19_H _PK_H_(0x13, 0x19) ++#define REG_SC_BK13_1A_L _PK_L_(0x13, 0x1A) ++#define REG_SC_BK13_1A_H _PK_H_(0x13, 0x1A) ++#define REG_SC_BK13_1B_L _PK_L_(0x13, 0x1B) ++#define REG_SC_BK13_1B_H _PK_H_(0x13, 0x1B) ++#define REG_SC_BK13_1C_L _PK_L_(0x13, 0x1C) ++#define REG_SC_BK13_1C_H _PK_H_(0x13, 0x1C) ++#define REG_SC_BK13_1D_L _PK_L_(0x13, 0x1D) ++#define REG_SC_BK13_1D_H _PK_H_(0x13, 0x1D) ++#define REG_SC_BK13_1E_L _PK_L_(0x13, 0x1E) ++#define REG_SC_BK13_1E_H _PK_H_(0x13, 0x1E) ++#define REG_SC_BK13_1F_L _PK_L_(0x13, 0x1F) ++#define REG_SC_BK13_1F_H _PK_H_(0x13, 0x1F) ++#define REG_SC_BK13_20_L _PK_L_(0x13, 0x20) ++#define REG_SC_BK13_20_H _PK_H_(0x13, 0x20) ++#define REG_SC_BK13_21_L _PK_L_(0x13, 0x21) ++#define REG_SC_BK13_21_H _PK_H_(0x13, 0x21) ++#define REG_SC_BK13_22_L _PK_L_(0x13, 0x22) ++#define REG_SC_BK13_22_H _PK_H_(0x13, 0x22) ++#define REG_SC_BK13_23_L _PK_L_(0x13, 0x23) ++#define REG_SC_BK13_23_H _PK_H_(0x13, 0x23) ++#define REG_SC_BK13_24_L _PK_L_(0x13, 0x24) ++#define REG_SC_BK13_24_H _PK_H_(0x13, 0x24) ++#define REG_SC_BK13_25_L _PK_L_(0x13, 0x25) ++#define REG_SC_BK13_25_H _PK_H_(0x13, 0x25) ++#define REG_SC_BK13_26_L _PK_L_(0x13, 0x26) ++#define REG_SC_BK13_26_H _PK_H_(0x13, 0x26) ++#define REG_SC_BK13_27_L _PK_L_(0x13, 0x27) ++#define REG_SC_BK13_27_H _PK_H_(0x13, 0x27) ++#define REG_SC_BK13_28_L _PK_L_(0x13, 0x28) ++#define REG_SC_BK13_28_H _PK_H_(0x13, 0x28) ++#define REG_SC_BK13_29_L _PK_L_(0x13, 0x29) ++#define REG_SC_BK13_29_H _PK_H_(0x13, 0x29) ++#define REG_SC_BK13_2A_L _PK_L_(0x13, 0x2A) ++#define REG_SC_BK13_2A_H _PK_H_(0x13, 0x2A) ++#define REG_SC_BK13_2B_L _PK_L_(0x13, 0x2B) ++#define REG_SC_BK13_2B_H _PK_H_(0x13, 0x2B) ++#define REG_SC_BK13_2C_L _PK_L_(0x13, 0x2C) ++#define REG_SC_BK13_2C_H _PK_H_(0x13, 0x2C) ++#define REG_SC_BK13_2D_L _PK_L_(0x13, 0x2D) ++#define REG_SC_BK13_2D_H _PK_H_(0x13, 0x2D) ++#define REG_SC_BK13_2E_L _PK_L_(0x13, 0x2E) ++#define REG_SC_BK13_2E_H _PK_H_(0x13, 0x2E) ++#define REG_SC_BK13_2F_L _PK_L_(0x13, 0x2F) ++#define REG_SC_BK13_2F_H _PK_H_(0x13, 0x2F) ++#define REG_SC_BK13_30_L _PK_L_(0x13, 0x30) ++#define REG_SC_BK13_30_H _PK_H_(0x13, 0x30) ++#define REG_SC_BK13_31_L _PK_L_(0x13, 0x31) ++#define REG_SC_BK13_31_H _PK_H_(0x13, 0x31) ++#define REG_SC_BK13_32_L _PK_L_(0x13, 0x32) ++#define REG_SC_BK13_32_H _PK_H_(0x13, 0x32) ++#define REG_SC_BK13_33_L _PK_L_(0x13, 0x33) ++#define REG_SC_BK13_33_H _PK_H_(0x13, 0x33) ++#define REG_SC_BK13_34_L _PK_L_(0x13, 0x34) ++#define REG_SC_BK13_34_H _PK_H_(0x13, 0x34) ++#define REG_SC_BK13_35_L _PK_L_(0x13, 0x35) ++#define REG_SC_BK13_35_H _PK_H_(0x13, 0x35) ++#define REG_SC_BK13_36_L _PK_L_(0x13, 0x36) ++#define REG_SC_BK13_36_H _PK_H_(0x13, 0x36) ++#define REG_SC_BK13_37_L _PK_L_(0x13, 0x37) ++#define REG_SC_BK13_37_H _PK_H_(0x13, 0x37) ++#define REG_SC_BK13_38_L _PK_L_(0x13, 0x38) ++#define REG_SC_BK13_38_H _PK_H_(0x13, 0x38) ++#define REG_SC_BK13_39_L _PK_L_(0x13, 0x39) ++#define REG_SC_BK13_39_H _PK_H_(0x13, 0x39) ++#define REG_SC_BK13_3A_L _PK_L_(0x13, 0x3A) ++#define REG_SC_BK13_3A_H _PK_H_(0x13, 0x3A) ++#define REG_SC_BK13_3B_L _PK_L_(0x13, 0x3B) ++#define REG_SC_BK13_3B_H _PK_H_(0x13, 0x3B) ++#define REG_SC_BK13_3C_L _PK_L_(0x13, 0x3C) ++#define REG_SC_BK13_3C_H _PK_H_(0x13, 0x3C) ++#define REG_SC_BK13_3D_L _PK_L_(0x13, 0x3D) ++#define REG_SC_BK13_3D_H _PK_H_(0x13, 0x3D) ++#define REG_SC_BK13_3E_L _PK_L_(0x13, 0x3E) ++#define REG_SC_BK13_3E_H _PK_H_(0x13, 0x3E) ++#define REG_SC_BK13_3F_L _PK_L_(0x13, 0x3F) ++#define REG_SC_BK13_3F_H _PK_H_(0x13, 0x3F) ++#define REG_SC_BK13_40_L _PK_L_(0x13, 0x40) ++#define REG_SC_BK13_40_H _PK_H_(0x13, 0x40) ++#define REG_SC_BK13_41_L _PK_L_(0x13, 0x41) ++#define REG_SC_BK13_41_H _PK_H_(0x13, 0x41) ++#define REG_SC_BK13_42_L _PK_L_(0x13, 0x42) ++#define REG_SC_BK13_42_H _PK_H_(0x13, 0x42) ++#define REG_SC_BK13_43_L _PK_L_(0x13, 0x43) ++#define REG_SC_BK13_43_H _PK_H_(0x13, 0x43) ++#define REG_SC_BK13_44_L _PK_L_(0x13, 0x44) ++#define REG_SC_BK13_44_H _PK_H_(0x13, 0x44) ++#define REG_SC_BK13_45_L _PK_L_(0x13, 0x45) ++#define REG_SC_BK13_45_H _PK_H_(0x13, 0x45) ++#define REG_SC_BK13_46_L _PK_L_(0x13, 0x46) ++#define REG_SC_BK13_46_H _PK_H_(0x13, 0x46) ++#define REG_SC_BK13_47_L _PK_L_(0x13, 0x47) ++#define REG_SC_BK13_47_H _PK_H_(0x13, 0x47) ++#define REG_SC_BK13_48_L _PK_L_(0x13, 0x48) ++#define REG_SC_BK13_48_H _PK_H_(0x13, 0x48) ++#define REG_SC_BK13_49_L _PK_L_(0x13, 0x49) ++#define REG_SC_BK13_49_H _PK_H_(0x13, 0x49) ++#define REG_SC_BK13_4A_L _PK_L_(0x13, 0x4A) ++#define REG_SC_BK13_4A_H _PK_H_(0x13, 0x4A) ++#define REG_SC_BK13_4B_L _PK_L_(0x13, 0x4B) ++#define REG_SC_BK13_4B_H _PK_H_(0x13, 0x4B) ++#define REG_SC_BK13_4C_L _PK_L_(0x13, 0x4C) ++#define REG_SC_BK13_4C_H _PK_H_(0x13, 0x4C) ++#define REG_SC_BK13_4D_L _PK_L_(0x13, 0x4D) ++#define REG_SC_BK13_4D_H _PK_H_(0x13, 0x4D) ++#define REG_SC_BK13_4E_L _PK_L_(0x13, 0x4E) ++#define REG_SC_BK13_4E_H _PK_H_(0x13, 0x4E) ++#define REG_SC_BK13_4F_L _PK_L_(0x13, 0x4F) ++#define REG_SC_BK13_4F_H _PK_H_(0x13, 0x4F) ++#define REG_SC_BK13_50_L _PK_L_(0x13, 0x50) ++#define REG_SC_BK13_50_H _PK_H_(0x13, 0x50) ++#define REG_SC_BK13_51_L _PK_L_(0x13, 0x51) ++#define REG_SC_BK13_51_H _PK_H_(0x13, 0x51) ++#define REG_SC_BK13_52_L _PK_L_(0x13, 0x52) ++#define REG_SC_BK13_52_H _PK_H_(0x13, 0x52) ++#define REG_SC_BK13_53_L _PK_L_(0x13, 0x53) ++#define REG_SC_BK13_53_H _PK_H_(0x13, 0x53) ++#define REG_SC_BK13_54_L _PK_L_(0x13, 0x54) ++#define REG_SC_BK13_54_H _PK_H_(0x13, 0x54) ++#define REG_SC_BK13_55_L _PK_L_(0x13, 0x55) ++#define REG_SC_BK13_55_H _PK_H_(0x13, 0x55) ++#define REG_SC_BK13_56_L _PK_L_(0x13, 0x56) ++#define REG_SC_BK13_56_H _PK_H_(0x13, 0x56) ++#define REG_SC_BK13_57_L _PK_L_(0x13, 0x57) ++#define REG_SC_BK13_57_H _PK_H_(0x13, 0x57) ++#define REG_SC_BK13_58_L _PK_L_(0x13, 0x58) ++#define REG_SC_BK13_58_H _PK_H_(0x13, 0x58) ++#define REG_SC_BK13_59_L _PK_L_(0x13, 0x59) ++#define REG_SC_BK13_59_H _PK_H_(0x13, 0x59) ++#define REG_SC_BK13_5A_L _PK_L_(0x13, 0x5A) ++#define REG_SC_BK13_5A_H _PK_H_(0x13, 0x5A) ++#define REG_SC_BK13_5B_L _PK_L_(0x13, 0x5B) ++#define REG_SC_BK13_5B_H _PK_H_(0x13, 0x5B) ++#define REG_SC_BK13_5C_L _PK_L_(0x13, 0x5C) ++#define REG_SC_BK13_5C_H _PK_H_(0x13, 0x5C) ++#define REG_SC_BK13_5D_L _PK_L_(0x13, 0x5D) ++#define REG_SC_BK13_5D_H _PK_H_(0x13, 0x5D) ++#define REG_SC_BK13_5E_L _PK_L_(0x13, 0x5E) ++#define REG_SC_BK13_5E_H _PK_H_(0x13, 0x5E) ++#define REG_SC_BK13_5F_L _PK_L_(0x13, 0x5F) ++#define REG_SC_BK13_5F_H _PK_H_(0x13, 0x5F) ++#define REG_SC_BK13_60_L _PK_L_(0x13, 0x60) ++#define REG_SC_BK13_60_H _PK_H_(0x13, 0x60) ++#define REG_SC_BK13_61_L _PK_L_(0x13, 0x61) ++#define REG_SC_BK13_61_H _PK_H_(0x13, 0x61) ++#define REG_SC_BK13_62_L _PK_L_(0x13, 0x62) ++#define REG_SC_BK13_62_H _PK_H_(0x13, 0x62) ++#define REG_SC_BK13_63_L _PK_L_(0x13, 0x63) ++#define REG_SC_BK13_63_H _PK_H_(0x13, 0x63) ++#define REG_SC_BK13_64_L _PK_L_(0x13, 0x64) ++#define REG_SC_BK13_64_H _PK_H_(0x13, 0x64) ++#define REG_SC_BK13_65_L _PK_L_(0x13, 0x65) ++#define REG_SC_BK13_65_H _PK_H_(0x13, 0x65) ++#define REG_SC_BK13_66_L _PK_L_(0x13, 0x66) ++#define REG_SC_BK13_66_H _PK_H_(0x13, 0x66) ++#define REG_SC_BK13_67_L _PK_L_(0x13, 0x67) ++#define REG_SC_BK13_67_H _PK_H_(0x13, 0x67) ++#define REG_SC_BK13_68_L _PK_L_(0x13, 0x68) ++#define REG_SC_BK13_68_H _PK_H_(0x13, 0x68) ++#define REG_SC_BK13_69_L _PK_L_(0x13, 0x69) ++#define REG_SC_BK13_69_H _PK_H_(0x13, 0x69) ++#define REG_SC_BK13_6A_L _PK_L_(0x13, 0x6A) ++#define REG_SC_BK13_6A_H _PK_H_(0x13, 0x6A) ++#define REG_SC_BK13_6B_L _PK_L_(0x13, 0x6B) ++#define REG_SC_BK13_6B_H _PK_H_(0x13, 0x6B) ++#define REG_SC_BK13_6C_L _PK_L_(0x13, 0x6C) ++#define REG_SC_BK13_6C_H _PK_H_(0x13, 0x6C) ++#define REG_SC_BK13_6D_L _PK_L_(0x13, 0x6D) ++#define REG_SC_BK13_6D_H _PK_H_(0x13, 0x6D) ++#define REG_SC_BK13_6E_L _PK_L_(0x13, 0x6E) ++#define REG_SC_BK13_6E_H _PK_H_(0x13, 0x6E) ++#define REG_SC_BK13_6F_L _PK_L_(0x13, 0x6F) ++#define REG_SC_BK13_6F_H _PK_H_(0x13, 0x6F) ++#define REG_SC_BK13_70_L _PK_L_(0x13, 0x70) ++#define REG_SC_BK13_70_H _PK_H_(0x13, 0x70) ++#define REG_SC_BK13_71_L _PK_L_(0x13, 0x71) ++#define REG_SC_BK13_71_H _PK_H_(0x13, 0x71) ++#define REG_SC_BK13_72_L _PK_L_(0x13, 0x72) ++#define REG_SC_BK13_72_H _PK_H_(0x13, 0x72) ++#define REG_SC_BK13_73_L _PK_L_(0x13, 0x73) ++#define REG_SC_BK13_73_H _PK_H_(0x13, 0x73) ++#define REG_SC_BK13_74_L _PK_L_(0x13, 0x74) ++#define REG_SC_BK13_74_H _PK_H_(0x13, 0x74) ++#define REG_SC_BK13_75_L _PK_L_(0x13, 0x75) ++#define REG_SC_BK13_75_H _PK_H_(0x13, 0x75) ++#define REG_SC_BK13_76_L _PK_L_(0x13, 0x76) ++#define REG_SC_BK13_76_H _PK_H_(0x13, 0x76) ++#define REG_SC_BK13_77_L _PK_L_(0x13, 0x77) ++#define REG_SC_BK13_77_H _PK_H_(0x13, 0x77) ++#define REG_SC_BK13_78_L _PK_L_(0x13, 0x78) ++#define REG_SC_BK13_78_H _PK_H_(0x13, 0x78) ++#define REG_SC_BK13_79_L _PK_L_(0x13, 0x79) ++#define REG_SC_BK13_79_H _PK_H_(0x13, 0x79) ++#define REG_SC_BK13_7A_L _PK_L_(0x13, 0x7A) ++#define REG_SC_BK13_7A_H _PK_H_(0x13, 0x7A) ++#define REG_SC_BK13_7B_L _PK_L_(0x13, 0x7B) ++#define REG_SC_BK13_7B_H _PK_H_(0x13, 0x7B) ++#define REG_SC_BK13_7C_L _PK_L_(0x13, 0x7C) ++#define REG_SC_BK13_7C_H _PK_H_(0x13, 0x7C) ++#define REG_SC_BK13_7D_L _PK_L_(0x13, 0x7D) ++#define REG_SC_BK13_7D_H _PK_H_(0x13, 0x7D) ++#define REG_SC_BK13_7E_L _PK_L_(0x13, 0x7E) ++#define REG_SC_BK13_7E_H _PK_H_(0x13, 0x7E) ++#define REG_SC_BK13_7F_L _PK_L_(0x13, 0x7F) ++#define REG_SC_BK13_7F_H _PK_H_(0x13, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK14_00_L _PK_L_(0x14, 0x00) ++#define REG_SC_BK14_00_H _PK_H_(0x14, 0x00) ++#define REG_SC_BK14_01_L _PK_L_(0x14, 0x01) ++#define REG_SC_BK14_01_H _PK_H_(0x14, 0x01) ++#define REG_SC_BK14_02_L _PK_L_(0x14, 0x02) ++#define REG_SC_BK14_02_H _PK_H_(0x14, 0x02) ++#define REG_SC_BK14_03_L _PK_L_(0x14, 0x03) ++#define REG_SC_BK14_03_H _PK_H_(0x14, 0x03) ++#define REG_SC_BK14_04_L _PK_L_(0x14, 0x04) ++#define REG_SC_BK14_04_H _PK_H_(0x14, 0x04) ++#define REG_SC_BK14_05_L _PK_L_(0x14, 0x05) ++#define REG_SC_BK14_05_H _PK_H_(0x14, 0x05) ++#define REG_SC_BK14_06_L _PK_L_(0x14, 0x06) ++#define REG_SC_BK14_06_H _PK_H_(0x14, 0x06) ++#define REG_SC_BK14_07_L _PK_L_(0x14, 0x07) ++#define REG_SC_BK14_07_H _PK_H_(0x14, 0x07) ++#define REG_SC_BK14_08_L _PK_L_(0x14, 0x08) ++#define REG_SC_BK14_08_H _PK_H_(0x14, 0x08) ++#define REG_SC_BK14_09_L _PK_L_(0x14, 0x09) ++#define REG_SC_BK14_09_H _PK_H_(0x14, 0x09) ++#define REG_SC_BK14_0A_L _PK_L_(0x14, 0x0A) ++#define REG_SC_BK14_0A_H _PK_H_(0x14, 0x0A) ++#define REG_SC_BK14_0B_L _PK_L_(0x14, 0x0B) ++#define REG_SC_BK14_0B_H _PK_H_(0x14, 0x0B) ++#define REG_SC_BK14_0C_L _PK_L_(0x14, 0x0C) ++#define REG_SC_BK14_0C_H _PK_H_(0x14, 0x0C) ++#define REG_SC_BK14_0D_L _PK_L_(0x14, 0x0D) ++#define REG_SC_BK14_0D_H _PK_H_(0x14, 0x0D) ++#define REG_SC_BK14_0E_L _PK_L_(0x14, 0x0E) ++#define REG_SC_BK14_0E_H _PK_H_(0x14, 0x0E) ++#define REG_SC_BK14_0F_L _PK_L_(0x14, 0x0F) ++#define REG_SC_BK14_0F_H _PK_H_(0x14, 0x0F) ++#define REG_SC_BK14_10_L _PK_L_(0x14, 0x10) ++#define REG_SC_BK14_10_H _PK_H_(0x14, 0x10) ++#define REG_SC_BK14_11_L _PK_L_(0x14, 0x11) ++#define REG_SC_BK14_11_H _PK_H_(0x14, 0x11) ++#define REG_SC_BK14_12_L _PK_L_(0x14, 0x12) ++#define REG_SC_BK14_12_H _PK_H_(0x14, 0x12) ++#define REG_SC_BK14_13_L _PK_L_(0x14, 0x13) ++#define REG_SC_BK14_13_H _PK_H_(0x14, 0x13) ++#define REG_SC_BK14_14_L _PK_L_(0x14, 0x14) ++#define REG_SC_BK14_14_H _PK_H_(0x14, 0x14) ++#define REG_SC_BK14_15_L _PK_L_(0x14, 0x15) ++#define REG_SC_BK14_15_H _PK_H_(0x14, 0x15) ++#define REG_SC_BK14_16_L _PK_L_(0x14, 0x16) ++#define REG_SC_BK14_16_H _PK_H_(0x14, 0x16) ++#define REG_SC_BK14_17_L _PK_L_(0x14, 0x17) ++#define REG_SC_BK14_17_H _PK_H_(0x14, 0x17) ++#define REG_SC_BK14_18_L _PK_L_(0x14, 0x18) ++#define REG_SC_BK14_18_H _PK_H_(0x14, 0x18) ++#define REG_SC_BK14_19_L _PK_L_(0x14, 0x19) ++#define REG_SC_BK14_19_H _PK_H_(0x14, 0x19) ++#define REG_SC_BK14_1A_L _PK_L_(0x14, 0x1A) ++#define REG_SC_BK14_1A_H _PK_H_(0x14, 0x1A) ++#define REG_SC_BK14_1B_L _PK_L_(0x14, 0x1B) ++#define REG_SC_BK14_1B_H _PK_H_(0x14, 0x1B) ++#define REG_SC_BK14_1C_L _PK_L_(0x14, 0x1C) ++#define REG_SC_BK14_1C_H _PK_H_(0x14, 0x1C) ++#define REG_SC_BK14_1D_L _PK_L_(0x14, 0x1D) ++#define REG_SC_BK14_1D_H _PK_H_(0x14, 0x1D) ++#define REG_SC_BK14_1E_L _PK_L_(0x14, 0x1E) ++#define REG_SC_BK14_1E_H _PK_H_(0x14, 0x1E) ++#define REG_SC_BK14_1F_L _PK_L_(0x14, 0x1F) ++#define REG_SC_BK14_1F_H _PK_H_(0x14, 0x1F) ++#define REG_SC_BK14_20_L _PK_L_(0x14, 0x20) ++#define REG_SC_BK14_20_H _PK_H_(0x14, 0x20) ++#define REG_SC_BK14_21_L _PK_L_(0x14, 0x21) ++#define REG_SC_BK14_21_H _PK_H_(0x14, 0x21) ++#define REG_SC_BK14_22_L _PK_L_(0x14, 0x22) ++#define REG_SC_BK14_22_H _PK_H_(0x14, 0x22) ++#define REG_SC_BK14_23_L _PK_L_(0x14, 0x23) ++#define REG_SC_BK14_23_H _PK_H_(0x14, 0x23) ++#define REG_SC_BK14_24_L _PK_L_(0x14, 0x24) ++#define REG_SC_BK14_24_H _PK_H_(0x14, 0x24) ++#define REG_SC_BK14_25_L _PK_L_(0x14, 0x25) ++#define REG_SC_BK14_25_H _PK_H_(0x14, 0x25) ++#define REG_SC_BK14_26_L _PK_L_(0x14, 0x26) ++#define REG_SC_BK14_26_H _PK_H_(0x14, 0x26) ++#define REG_SC_BK14_27_L _PK_L_(0x14, 0x27) ++#define REG_SC_BK14_27_H _PK_H_(0x14, 0x27) ++#define REG_SC_BK14_28_L _PK_L_(0x14, 0x28) ++#define REG_SC_BK14_28_H _PK_H_(0x14, 0x28) ++#define REG_SC_BK14_29_L _PK_L_(0x14, 0x29) ++#define REG_SC_BK14_29_H _PK_H_(0x14, 0x29) ++#define REG_SC_BK14_2A_L _PK_L_(0x14, 0x2A) ++#define REG_SC_BK14_2A_H _PK_H_(0x14, 0x2A) ++#define REG_SC_BK14_2B_L _PK_L_(0x14, 0x2B) ++#define REG_SC_BK14_2B_H _PK_H_(0x14, 0x2B) ++#define REG_SC_BK14_2C_L _PK_L_(0x14, 0x2C) ++#define REG_SC_BK14_2C_H _PK_H_(0x14, 0x2C) ++#define REG_SC_BK14_2D_L _PK_L_(0x14, 0x2D) ++#define REG_SC_BK14_2D_H _PK_H_(0x14, 0x2D) ++#define REG_SC_BK14_2E_L _PK_L_(0x14, 0x2E) ++#define REG_SC_BK14_2E_H _PK_H_(0x14, 0x2E) ++#define REG_SC_BK14_2F_L _PK_L_(0x14, 0x2F) ++#define REG_SC_BK14_2F_H _PK_H_(0x14, 0x2F) ++#define REG_SC_BK14_30_L _PK_L_(0x14, 0x30) ++#define REG_SC_BK14_30_H _PK_H_(0x14, 0x30) ++#define REG_SC_BK14_31_L _PK_L_(0x14, 0x31) ++#define REG_SC_BK14_31_H _PK_H_(0x14, 0x31) ++#define REG_SC_BK14_32_L _PK_L_(0x14, 0x32) ++#define REG_SC_BK14_32_H _PK_H_(0x14, 0x32) ++#define REG_SC_BK14_33_L _PK_L_(0x14, 0x33) ++#define REG_SC_BK14_33_H _PK_H_(0x14, 0x33) ++#define REG_SC_BK14_34_L _PK_L_(0x14, 0x34) ++#define REG_SC_BK14_34_H _PK_H_(0x14, 0x34) ++#define REG_SC_BK14_35_L _PK_L_(0x14, 0x35) ++#define REG_SC_BK14_35_H _PK_H_(0x14, 0x35) ++#define REG_SC_BK14_36_L _PK_L_(0x14, 0x36) ++#define REG_SC_BK14_36_H _PK_H_(0x14, 0x36) ++#define REG_SC_BK14_37_L _PK_L_(0x14, 0x37) ++#define REG_SC_BK14_37_H _PK_H_(0x14, 0x37) ++#define REG_SC_BK14_38_L _PK_L_(0x14, 0x38) ++#define REG_SC_BK14_38_H _PK_H_(0x14, 0x38) ++#define REG_SC_BK14_39_L _PK_L_(0x14, 0x39) ++#define REG_SC_BK14_39_H _PK_H_(0x14, 0x39) ++#define REG_SC_BK14_3A_L _PK_L_(0x14, 0x3A) ++#define REG_SC_BK14_3A_H _PK_H_(0x14, 0x3A) ++#define REG_SC_BK14_3B_L _PK_L_(0x14, 0x3B) ++#define REG_SC_BK14_3B_H _PK_H_(0x14, 0x3B) ++#define REG_SC_BK14_3C_L _PK_L_(0x14, 0x3C) ++#define REG_SC_BK14_3C_H _PK_H_(0x14, 0x3C) ++#define REG_SC_BK14_3D_L _PK_L_(0x14, 0x3D) ++#define REG_SC_BK14_3D_H _PK_H_(0x14, 0x3D) ++#define REG_SC_BK14_3E_L _PK_L_(0x14, 0x3E) ++#define REG_SC_BK14_3E_H _PK_H_(0x14, 0x3E) ++#define REG_SC_BK14_3F_L _PK_L_(0x14, 0x3F) ++#define REG_SC_BK14_3F_H _PK_H_(0x14, 0x3F) ++#define REG_SC_BK14_40_L _PK_L_(0x14, 0x40) ++#define REG_SC_BK14_40_H _PK_H_(0x14, 0x40) ++#define REG_SC_BK14_41_L _PK_L_(0x14, 0x41) ++#define REG_SC_BK14_41_H _PK_H_(0x14, 0x41) ++#define REG_SC_BK14_42_L _PK_L_(0x14, 0x42) ++#define REG_SC_BK14_42_H _PK_H_(0x14, 0x42) ++#define REG_SC_BK14_43_L _PK_L_(0x14, 0x43) ++#define REG_SC_BK14_43_H _PK_H_(0x14, 0x43) ++#define REG_SC_BK14_44_L _PK_L_(0x14, 0x44) ++#define REG_SC_BK14_44_H _PK_H_(0x14, 0x44) ++#define REG_SC_BK14_45_L _PK_L_(0x14, 0x45) ++#define REG_SC_BK14_45_H _PK_H_(0x14, 0x45) ++#define REG_SC_BK14_46_L _PK_L_(0x14, 0x46) ++#define REG_SC_BK14_46_H _PK_H_(0x14, 0x46) ++#define REG_SC_BK14_47_L _PK_L_(0x14, 0x47) ++#define REG_SC_BK14_47_H _PK_H_(0x14, 0x47) ++#define REG_SC_BK14_48_L _PK_L_(0x14, 0x48) ++#define REG_SC_BK14_48_H _PK_H_(0x14, 0x48) ++#define REG_SC_BK14_49_L _PK_L_(0x14, 0x49) ++#define REG_SC_BK14_49_H _PK_H_(0x14, 0x49) ++#define REG_SC_BK14_4A_L _PK_L_(0x14, 0x4A) ++#define REG_SC_BK14_4A_H _PK_H_(0x14, 0x4A) ++#define REG_SC_BK14_4B_L _PK_L_(0x14, 0x4B) ++#define REG_SC_BK14_4B_H _PK_H_(0x14, 0x4B) ++#define REG_SC_BK14_4C_L _PK_L_(0x14, 0x4C) ++#define REG_SC_BK14_4C_H _PK_H_(0x14, 0x4C) ++#define REG_SC_BK14_4D_L _PK_L_(0x14, 0x4D) ++#define REG_SC_BK14_4D_H _PK_H_(0x14, 0x4D) ++#define REG_SC_BK14_4E_L _PK_L_(0x14, 0x4E) ++#define REG_SC_BK14_4E_H _PK_H_(0x14, 0x4E) ++#define REG_SC_BK14_4F_L _PK_L_(0x14, 0x4F) ++#define REG_SC_BK14_4F_H _PK_H_(0x14, 0x4F) ++#define REG_SC_BK14_50_L _PK_L_(0x14, 0x50) ++#define REG_SC_BK14_50_H _PK_H_(0x14, 0x50) ++#define REG_SC_BK14_51_L _PK_L_(0x14, 0x51) ++#define REG_SC_BK14_51_H _PK_H_(0x14, 0x51) ++#define REG_SC_BK14_52_L _PK_L_(0x14, 0x52) ++#define REG_SC_BK14_52_H _PK_H_(0x14, 0x52) ++#define REG_SC_BK14_53_L _PK_L_(0x14, 0x53) ++#define REG_SC_BK14_53_H _PK_H_(0x14, 0x53) ++#define REG_SC_BK14_54_L _PK_L_(0x14, 0x54) ++#define REG_SC_BK14_54_H _PK_H_(0x14, 0x54) ++#define REG_SC_BK14_55_L _PK_L_(0x14, 0x55) ++#define REG_SC_BK14_55_H _PK_H_(0x14, 0x55) ++#define REG_SC_BK14_56_L _PK_L_(0x14, 0x56) ++#define REG_SC_BK14_56_H _PK_H_(0x14, 0x56) ++#define REG_SC_BK14_57_L _PK_L_(0x14, 0x57) ++#define REG_SC_BK14_57_H _PK_H_(0x14, 0x57) ++#define REG_SC_BK14_58_L _PK_L_(0x14, 0x58) ++#define REG_SC_BK14_58_H _PK_H_(0x14, 0x58) ++#define REG_SC_BK14_59_L _PK_L_(0x14, 0x59) ++#define REG_SC_BK14_59_H _PK_H_(0x14, 0x59) ++#define REG_SC_BK14_5A_L _PK_L_(0x14, 0x5A) ++#define REG_SC_BK14_5A_H _PK_H_(0x14, 0x5A) ++#define REG_SC_BK14_5B_L _PK_L_(0x14, 0x5B) ++#define REG_SC_BK14_5B_H _PK_H_(0x14, 0x5B) ++#define REG_SC_BK14_5C_L _PK_L_(0x14, 0x5C) ++#define REG_SC_BK14_5C_H _PK_H_(0x14, 0x5C) ++#define REG_SC_BK14_5D_L _PK_L_(0x14, 0x5D) ++#define REG_SC_BK14_5D_H _PK_H_(0x14, 0x5D) ++#define REG_SC_BK14_5E_L _PK_L_(0x14, 0x5E) ++#define REG_SC_BK14_5E_H _PK_H_(0x14, 0x5E) ++#define REG_SC_BK14_5F_L _PK_L_(0x14, 0x5F) ++#define REG_SC_BK14_5F_H _PK_H_(0x14, 0x5F) ++#define REG_SC_BK14_60_L _PK_L_(0x14, 0x60) ++#define REG_SC_BK14_60_H _PK_H_(0x14, 0x60) ++#define REG_SC_BK14_61_L _PK_L_(0x14, 0x61) ++#define REG_SC_BK14_61_H _PK_H_(0x14, 0x61) ++#define REG_SC_BK14_62_L _PK_L_(0x14, 0x62) ++#define REG_SC_BK14_62_H _PK_H_(0x14, 0x62) ++#define REG_SC_BK14_63_L _PK_L_(0x14, 0x63) ++#define REG_SC_BK14_63_H _PK_H_(0x14, 0x63) ++#define REG_SC_BK14_64_L _PK_L_(0x14, 0x64) ++#define REG_SC_BK14_64_H _PK_H_(0x14, 0x64) ++#define REG_SC_BK14_65_L _PK_L_(0x14, 0x65) ++#define REG_SC_BK14_65_H _PK_H_(0x14, 0x65) ++#define REG_SC_BK14_66_L _PK_L_(0x14, 0x66) ++#define REG_SC_BK14_66_H _PK_H_(0x14, 0x66) ++#define REG_SC_BK14_67_L _PK_L_(0x14, 0x67) ++#define REG_SC_BK14_67_H _PK_H_(0x14, 0x67) ++#define REG_SC_BK14_68_L _PK_L_(0x14, 0x68) ++#define REG_SC_BK14_68_H _PK_H_(0x14, 0x68) ++#define REG_SC_BK14_69_L _PK_L_(0x14, 0x69) ++#define REG_SC_BK14_69_H _PK_H_(0x14, 0x69) ++#define REG_SC_BK14_6A_L _PK_L_(0x14, 0x6A) ++#define REG_SC_BK14_6A_H _PK_H_(0x14, 0x6A) ++#define REG_SC_BK14_6B_L _PK_L_(0x14, 0x6B) ++#define REG_SC_BK14_6B_H _PK_H_(0x14, 0x6B) ++#define REG_SC_BK14_6C_L _PK_L_(0x14, 0x6C) ++#define REG_SC_BK14_6C_H _PK_H_(0x14, 0x6C) ++#define REG_SC_BK14_6D_L _PK_L_(0x14, 0x6D) ++#define REG_SC_BK14_6D_H _PK_H_(0x14, 0x6D) ++#define REG_SC_BK14_6E_L _PK_L_(0x14, 0x6E) ++#define REG_SC_BK14_6E_H _PK_H_(0x14, 0x6E) ++#define REG_SC_BK14_6F_L _PK_L_(0x14, 0x6F) ++#define REG_SC_BK14_6F_H _PK_H_(0x14, 0x6F) ++#define REG_SC_BK14_70_L _PK_L_(0x14, 0x70) ++#define REG_SC_BK14_70_H _PK_H_(0x14, 0x70) ++#define REG_SC_BK14_71_L _PK_L_(0x14, 0x71) ++#define REG_SC_BK14_71_H _PK_H_(0x14, 0x71) ++#define REG_SC_BK14_72_L _PK_L_(0x14, 0x72) ++#define REG_SC_BK14_72_H _PK_H_(0x14, 0x72) ++#define REG_SC_BK14_73_L _PK_L_(0x14, 0x73) ++#define REG_SC_BK14_73_H _PK_H_(0x14, 0x73) ++#define REG_SC_BK14_74_L _PK_L_(0x14, 0x74) ++#define REG_SC_BK14_74_H _PK_H_(0x14, 0x74) ++#define REG_SC_BK14_75_L _PK_L_(0x14, 0x75) ++#define REG_SC_BK14_75_H _PK_H_(0x14, 0x75) ++#define REG_SC_BK14_76_L _PK_L_(0x14, 0x76) ++#define REG_SC_BK14_76_H _PK_H_(0x14, 0x76) ++#define REG_SC_BK14_77_L _PK_L_(0x14, 0x77) ++#define REG_SC_BK14_77_H _PK_H_(0x14, 0x77) ++#define REG_SC_BK14_78_L _PK_L_(0x14, 0x78) ++#define REG_SC_BK14_78_H _PK_H_(0x14, 0x78) ++#define REG_SC_BK14_79_L _PK_L_(0x14, 0x79) ++#define REG_SC_BK14_79_H _PK_H_(0x14, 0x79) ++#define REG_SC_BK14_7A_L _PK_L_(0x14, 0x7A) ++#define REG_SC_BK14_7A_H _PK_H_(0x14, 0x7A) ++#define REG_SC_BK14_7B_L _PK_L_(0x14, 0x7B) ++#define REG_SC_BK14_7B_H _PK_H_(0x14, 0x7B) ++#define REG_SC_BK14_7C_L _PK_L_(0x14, 0x7C) ++#define REG_SC_BK14_7C_H _PK_H_(0x14, 0x7C) ++#define REG_SC_BK14_7D_L _PK_L_(0x14, 0x7D) ++#define REG_SC_BK14_7D_H _PK_H_(0x14, 0x7D) ++#define REG_SC_BK14_7E_L _PK_L_(0x14, 0x7E) ++#define REG_SC_BK14_7E_H _PK_H_(0x14, 0x7E) ++#define REG_SC_BK14_7F_L _PK_L_(0x14, 0x7F) ++#define REG_SC_BK14_7F_H _PK_H_(0x14, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK15_00_L _PK_L_(0x15, 0x00) ++#define REG_SC_BK15_00_H _PK_H_(0x15, 0x00) ++#define REG_SC_BK15_01_L _PK_L_(0x15, 0x01) ++#define REG_SC_BK15_01_H _PK_H_(0x15, 0x01) ++#define REG_SC_BK15_02_L _PK_L_(0x15, 0x02) ++#define REG_SC_BK15_02_H _PK_H_(0x15, 0x02) ++#define REG_SC_BK15_03_L _PK_L_(0x15, 0x03) ++#define REG_SC_BK15_03_H _PK_H_(0x15, 0x03) ++#define REG_SC_BK15_04_L _PK_L_(0x15, 0x04) ++#define REG_SC_BK15_04_H _PK_H_(0x15, 0x04) ++#define REG_SC_BK15_05_L _PK_L_(0x15, 0x05) ++#define REG_SC_BK15_05_H _PK_H_(0x15, 0x05) ++#define REG_SC_BK15_06_L _PK_L_(0x15, 0x06) ++#define REG_SC_BK15_06_H _PK_H_(0x15, 0x06) ++#define REG_SC_BK15_07_L _PK_L_(0x15, 0x07) ++#define REG_SC_BK15_07_H _PK_H_(0x15, 0x07) ++#define REG_SC_BK15_08_L _PK_L_(0x15, 0x08) ++#define REG_SC_BK15_08_H _PK_H_(0x15, 0x08) ++#define REG_SC_BK15_09_L _PK_L_(0x15, 0x09) ++#define REG_SC_BK15_09_H _PK_H_(0x15, 0x09) ++#define REG_SC_BK15_0A_L _PK_L_(0x15, 0x0A) ++#define REG_SC_BK15_0A_H _PK_H_(0x15, 0x0A) ++#define REG_SC_BK15_0B_L _PK_L_(0x15, 0x0B) ++#define REG_SC_BK15_0B_H _PK_H_(0x15, 0x0B) ++#define REG_SC_BK15_0C_L _PK_L_(0x15, 0x0C) ++#define REG_SC_BK15_0C_H _PK_H_(0x15, 0x0C) ++#define REG_SC_BK15_0D_L _PK_L_(0x15, 0x0D) ++#define REG_SC_BK15_0D_H _PK_H_(0x15, 0x0D) ++#define REG_SC_BK15_0E_L _PK_L_(0x15, 0x0E) ++#define REG_SC_BK15_0E_H _PK_H_(0x15, 0x0E) ++#define REG_SC_BK15_0F_L _PK_L_(0x15, 0x0F) ++#define REG_SC_BK15_0F_H _PK_H_(0x15, 0x0F) ++#define REG_SC_BK15_10_L _PK_L_(0x15, 0x10) ++#define REG_SC_BK15_10_H _PK_H_(0x15, 0x10) ++#define REG_SC_BK15_11_L _PK_L_(0x15, 0x11) ++#define REG_SC_BK15_11_H _PK_H_(0x15, 0x11) ++#define REG_SC_BK15_12_L _PK_L_(0x15, 0x12) ++#define REG_SC_BK15_12_H _PK_H_(0x15, 0x12) ++#define REG_SC_BK15_13_L _PK_L_(0x15, 0x13) ++#define REG_SC_BK15_13_H _PK_H_(0x15, 0x13) ++#define REG_SC_BK15_14_L _PK_L_(0x15, 0x14) ++#define REG_SC_BK15_14_H _PK_H_(0x15, 0x14) ++#define REG_SC_BK15_15_L _PK_L_(0x15, 0x15) ++#define REG_SC_BK15_15_H _PK_H_(0x15, 0x15) ++#define REG_SC_BK15_16_L _PK_L_(0x15, 0x16) ++#define REG_SC_BK15_16_H _PK_H_(0x15, 0x16) ++#define REG_SC_BK15_17_L _PK_L_(0x15, 0x17) ++#define REG_SC_BK15_17_H _PK_H_(0x15, 0x17) ++#define REG_SC_BK15_18_L _PK_L_(0x15, 0x18) ++#define REG_SC_BK15_18_H _PK_H_(0x15, 0x18) ++#define REG_SC_BK15_19_L _PK_L_(0x15, 0x19) ++#define REG_SC_BK15_19_H _PK_H_(0x15, 0x19) ++#define REG_SC_BK15_1A_L _PK_L_(0x15, 0x1A) ++#define REG_SC_BK15_1A_H _PK_H_(0x15, 0x1A) ++#define REG_SC_BK15_1B_L _PK_L_(0x15, 0x1B) ++#define REG_SC_BK15_1B_H _PK_H_(0x15, 0x1B) ++#define REG_SC_BK15_1C_L _PK_L_(0x15, 0x1C) ++#define REG_SC_BK15_1C_H _PK_H_(0x15, 0x1C) ++#define REG_SC_BK15_1D_L _PK_L_(0x15, 0x1D) ++#define REG_SC_BK15_1D_H _PK_H_(0x15, 0x1D) ++#define REG_SC_BK15_1E_L _PK_L_(0x15, 0x1E) ++#define REG_SC_BK15_1E_H _PK_H_(0x15, 0x1E) ++#define REG_SC_BK15_1F_L _PK_L_(0x15, 0x1F) ++#define REG_SC_BK15_1F_H _PK_H_(0x15, 0x1F) ++#define REG_SC_BK15_20_L _PK_L_(0x15, 0x20) ++#define REG_SC_BK15_20_H _PK_H_(0x15, 0x20) ++#define REG_SC_BK15_21_L _PK_L_(0x15, 0x21) ++#define REG_SC_BK15_21_H _PK_H_(0x15, 0x21) ++#define REG_SC_BK15_22_L _PK_L_(0x15, 0x22) ++#define REG_SC_BK15_22_H _PK_H_(0x15, 0x22) ++#define REG_SC_BK15_23_L _PK_L_(0x15, 0x23) ++#define REG_SC_BK15_23_H _PK_H_(0x15, 0x23) ++#define REG_SC_BK15_24_L _PK_L_(0x15, 0x24) ++#define REG_SC_BK15_24_H _PK_H_(0x15, 0x24) ++#define REG_SC_BK15_25_L _PK_L_(0x15, 0x25) ++#define REG_SC_BK15_25_H _PK_H_(0x15, 0x25) ++#define REG_SC_BK15_26_L _PK_L_(0x15, 0x26) ++#define REG_SC_BK15_26_H _PK_H_(0x15, 0x26) ++#define REG_SC_BK15_27_L _PK_L_(0x15, 0x27) ++#define REG_SC_BK15_27_H _PK_H_(0x15, 0x27) ++#define REG_SC_BK15_28_L _PK_L_(0x15, 0x28) ++#define REG_SC_BK15_28_H _PK_H_(0x15, 0x28) ++#define REG_SC_BK15_29_L _PK_L_(0x15, 0x29) ++#define REG_SC_BK15_29_H _PK_H_(0x15, 0x29) ++#define REG_SC_BK15_2A_L _PK_L_(0x15, 0x2A) ++#define REG_SC_BK15_2A_H _PK_H_(0x15, 0x2A) ++#define REG_SC_BK15_2B_L _PK_L_(0x15, 0x2B) ++#define REG_SC_BK15_2B_H _PK_H_(0x15, 0x2B) ++#define REG_SC_BK15_2C_L _PK_L_(0x15, 0x2C) ++#define REG_SC_BK15_2C_H _PK_H_(0x15, 0x2C) ++#define REG_SC_BK15_2D_L _PK_L_(0x15, 0x2D) ++#define REG_SC_BK15_2D_H _PK_H_(0x15, 0x2D) ++#define REG_SC_BK15_2E_L _PK_L_(0x15, 0x2E) ++#define REG_SC_BK15_2E_H _PK_H_(0x15, 0x2E) ++#define REG_SC_BK15_2F_L _PK_L_(0x15, 0x2F) ++#define REG_SC_BK15_2F_H _PK_H_(0x15, 0x2F) ++#define REG_SC_BK15_30_L _PK_L_(0x15, 0x30) ++#define REG_SC_BK15_30_H _PK_H_(0x15, 0x30) ++#define REG_SC_BK15_31_L _PK_L_(0x15, 0x31) ++#define REG_SC_BK15_31_H _PK_H_(0x15, 0x31) ++#define REG_SC_BK15_32_L _PK_L_(0x15, 0x32) ++#define REG_SC_BK15_32_H _PK_H_(0x15, 0x32) ++#define REG_SC_BK15_33_L _PK_L_(0x15, 0x33) ++#define REG_SC_BK15_33_H _PK_H_(0x15, 0x33) ++#define REG_SC_BK15_34_L _PK_L_(0x15, 0x34) ++#define REG_SC_BK15_34_H _PK_H_(0x15, 0x34) ++#define REG_SC_BK15_35_L _PK_L_(0x15, 0x35) ++#define REG_SC_BK15_35_H _PK_H_(0x15, 0x35) ++#define REG_SC_BK15_36_L _PK_L_(0x15, 0x36) ++#define REG_SC_BK15_36_H _PK_H_(0x15, 0x36) ++#define REG_SC_BK15_37_L _PK_L_(0x15, 0x37) ++#define REG_SC_BK15_37_H _PK_H_(0x15, 0x37) ++#define REG_SC_BK15_38_L _PK_L_(0x15, 0x38) ++#define REG_SC_BK15_38_H _PK_H_(0x15, 0x38) ++#define REG_SC_BK15_39_L _PK_L_(0x15, 0x39) ++#define REG_SC_BK15_39_H _PK_H_(0x15, 0x39) ++#define REG_SC_BK15_3A_L _PK_L_(0x15, 0x3A) ++#define REG_SC_BK15_3A_H _PK_H_(0x15, 0x3A) ++#define REG_SC_BK15_3B_L _PK_L_(0x15, 0x3B) ++#define REG_SC_BK15_3B_H _PK_H_(0x15, 0x3B) ++#define REG_SC_BK15_3C_L _PK_L_(0x15, 0x3C) ++#define REG_SC_BK15_3C_H _PK_H_(0x15, 0x3C) ++#define REG_SC_BK15_3D_L _PK_L_(0x15, 0x3D) ++#define REG_SC_BK15_3D_H _PK_H_(0x15, 0x3D) ++#define REG_SC_BK15_3E_L _PK_L_(0x15, 0x3E) ++#define REG_SC_BK15_3E_H _PK_H_(0x15, 0x3E) ++#define REG_SC_BK15_3F_L _PK_L_(0x15, 0x3F) ++#define REG_SC_BK15_3F_H _PK_H_(0x15, 0x3F) ++#define REG_SC_BK15_40_L _PK_L_(0x15, 0x40) ++#define REG_SC_BK15_40_H _PK_H_(0x15, 0x40) ++#define REG_SC_BK15_41_L _PK_L_(0x15, 0x41) ++#define REG_SC_BK15_41_H _PK_H_(0x15, 0x41) ++#define REG_SC_BK15_42_L _PK_L_(0x15, 0x42) ++#define REG_SC_BK15_42_H _PK_H_(0x15, 0x42) ++#define REG_SC_BK15_43_L _PK_L_(0x15, 0x43) ++#define REG_SC_BK15_43_H _PK_H_(0x15, 0x43) ++#define REG_SC_BK15_44_L _PK_L_(0x15, 0x44) ++#define REG_SC_BK15_44_H _PK_H_(0x15, 0x44) ++#define REG_SC_BK15_45_L _PK_L_(0x15, 0x45) ++#define REG_SC_BK15_45_H _PK_H_(0x15, 0x45) ++#define REG_SC_BK15_46_L _PK_L_(0x15, 0x46) ++#define REG_SC_BK15_46_H _PK_H_(0x15, 0x46) ++#define REG_SC_BK15_47_L _PK_L_(0x15, 0x47) ++#define REG_SC_BK15_47_H _PK_H_(0x15, 0x47) ++#define REG_SC_BK15_48_L _PK_L_(0x15, 0x48) ++#define REG_SC_BK15_48_H _PK_H_(0x15, 0x48) ++#define REG_SC_BK15_49_L _PK_L_(0x15, 0x49) ++#define REG_SC_BK15_49_H _PK_H_(0x15, 0x49) ++#define REG_SC_BK15_4A_L _PK_L_(0x15, 0x4A) ++#define REG_SC_BK15_4A_H _PK_H_(0x15, 0x4A) ++#define REG_SC_BK15_4B_L _PK_L_(0x15, 0x4B) ++#define REG_SC_BK15_4B_H _PK_H_(0x15, 0x4B) ++#define REG_SC_BK15_4C_L _PK_L_(0x15, 0x4C) ++#define REG_SC_BK15_4C_H _PK_H_(0x15, 0x4C) ++#define REG_SC_BK15_4D_L _PK_L_(0x15, 0x4D) ++#define REG_SC_BK15_4D_H _PK_H_(0x15, 0x4D) ++#define REG_SC_BK15_4E_L _PK_L_(0x15, 0x4E) ++#define REG_SC_BK15_4E_H _PK_H_(0x15, 0x4E) ++#define REG_SC_BK15_4F_L _PK_L_(0x15, 0x4F) ++#define REG_SC_BK15_4F_H _PK_H_(0x15, 0x4F) ++#define REG_SC_BK15_50_L _PK_L_(0x15, 0x50) ++#define REG_SC_BK15_50_H _PK_H_(0x15, 0x50) ++#define REG_SC_BK15_51_L _PK_L_(0x15, 0x51) ++#define REG_SC_BK15_51_H _PK_H_(0x15, 0x51) ++#define REG_SC_BK15_52_L _PK_L_(0x15, 0x52) ++#define REG_SC_BK15_52_H _PK_H_(0x15, 0x52) ++#define REG_SC_BK15_53_L _PK_L_(0x15, 0x53) ++#define REG_SC_BK15_53_H _PK_H_(0x15, 0x53) ++#define REG_SC_BK15_54_L _PK_L_(0x15, 0x54) ++#define REG_SC_BK15_54_H _PK_H_(0x15, 0x54) ++#define REG_SC_BK15_55_L _PK_L_(0x15, 0x55) ++#define REG_SC_BK15_55_H _PK_H_(0x15, 0x55) ++#define REG_SC_BK15_56_L _PK_L_(0x15, 0x56) ++#define REG_SC_BK15_56_H _PK_H_(0x15, 0x56) ++#define REG_SC_BK15_57_L _PK_L_(0x15, 0x57) ++#define REG_SC_BK15_57_H _PK_H_(0x15, 0x57) ++#define REG_SC_BK15_58_L _PK_L_(0x15, 0x58) ++#define REG_SC_BK15_58_H _PK_H_(0x15, 0x58) ++#define REG_SC_BK15_59_L _PK_L_(0x15, 0x59) ++#define REG_SC_BK15_59_H _PK_H_(0x15, 0x59) ++#define REG_SC_BK15_5A_L _PK_L_(0x15, 0x5A) ++#define REG_SC_BK15_5A_H _PK_H_(0x15, 0x5A) ++#define REG_SC_BK15_5B_L _PK_L_(0x15, 0x5B) ++#define REG_SC_BK15_5B_H _PK_H_(0x15, 0x5B) ++#define REG_SC_BK15_5C_L _PK_L_(0x15, 0x5C) ++#define REG_SC_BK15_5C_H _PK_H_(0x15, 0x5C) ++#define REG_SC_BK15_5D_L _PK_L_(0x15, 0x5D) ++#define REG_SC_BK15_5D_H _PK_H_(0x15, 0x5D) ++#define REG_SC_BK15_5E_L _PK_L_(0x15, 0x5E) ++#define REG_SC_BK15_5E_H _PK_H_(0x15, 0x5E) ++#define REG_SC_BK15_5F_L _PK_L_(0x15, 0x5F) ++#define REG_SC_BK15_5F_H _PK_H_(0x15, 0x5F) ++#define REG_SC_BK15_60_L _PK_L_(0x15, 0x60) ++#define REG_SC_BK15_60_H _PK_H_(0x15, 0x60) ++#define REG_SC_BK15_61_L _PK_L_(0x15, 0x61) ++#define REG_SC_BK15_61_H _PK_H_(0x15, 0x61) ++#define REG_SC_BK15_62_L _PK_L_(0x15, 0x62) ++#define REG_SC_BK15_62_H _PK_H_(0x15, 0x62) ++#define REG_SC_BK15_63_L _PK_L_(0x15, 0x63) ++#define REG_SC_BK15_63_H _PK_H_(0x15, 0x63) ++#define REG_SC_BK15_64_L _PK_L_(0x15, 0x64) ++#define REG_SC_BK15_64_H _PK_H_(0x15, 0x64) ++#define REG_SC_BK15_65_L _PK_L_(0x15, 0x65) ++#define REG_SC_BK15_65_H _PK_H_(0x15, 0x65) ++#define REG_SC_BK15_66_L _PK_L_(0x15, 0x66) ++#define REG_SC_BK15_66_H _PK_H_(0x15, 0x66) ++#define REG_SC_BK15_67_L _PK_L_(0x15, 0x67) ++#define REG_SC_BK15_67_H _PK_H_(0x15, 0x67) ++#define REG_SC_BK15_68_L _PK_L_(0x15, 0x68) ++#define REG_SC_BK15_68_H _PK_H_(0x15, 0x68) ++#define REG_SC_BK15_69_L _PK_L_(0x15, 0x69) ++#define REG_SC_BK15_69_H _PK_H_(0x15, 0x69) ++#define REG_SC_BK15_6A_L _PK_L_(0x15, 0x6A) ++#define REG_SC_BK15_6A_H _PK_H_(0x15, 0x6A) ++#define REG_SC_BK15_6B_L _PK_L_(0x15, 0x6B) ++#define REG_SC_BK15_6B_H _PK_H_(0x15, 0x6B) ++#define REG_SC_BK15_6C_L _PK_L_(0x15, 0x6C) ++#define REG_SC_BK15_6C_H _PK_H_(0x15, 0x6C) ++#define REG_SC_BK15_6D_L _PK_L_(0x15, 0x6D) ++#define REG_SC_BK15_6D_H _PK_H_(0x15, 0x6D) ++#define REG_SC_BK15_6E_L _PK_L_(0x15, 0x6E) ++#define REG_SC_BK15_6E_H _PK_H_(0x15, 0x6E) ++#define REG_SC_BK15_6F_L _PK_L_(0x15, 0x6F) ++#define REG_SC_BK15_6F_H _PK_H_(0x15, 0x6F) ++#define REG_SC_BK15_70_L _PK_L_(0x15, 0x70) ++#define REG_SC_BK15_70_H _PK_H_(0x15, 0x70) ++#define REG_SC_BK15_71_L _PK_L_(0x15, 0x71) ++#define REG_SC_BK15_71_H _PK_H_(0x15, 0x71) ++#define REG_SC_BK15_72_L _PK_L_(0x15, 0x72) ++#define REG_SC_BK15_72_H _PK_H_(0x15, 0x72) ++#define REG_SC_BK15_73_L _PK_L_(0x15, 0x73) ++#define REG_SC_BK15_73_H _PK_H_(0x15, 0x73) ++#define REG_SC_BK15_74_L _PK_L_(0x15, 0x74) ++#define REG_SC_BK15_74_H _PK_H_(0x15, 0x74) ++#define REG_SC_BK15_75_L _PK_L_(0x15, 0x75) ++#define REG_SC_BK15_75_H _PK_H_(0x15, 0x75) ++#define REG_SC_BK15_76_L _PK_L_(0x15, 0x76) ++#define REG_SC_BK15_76_H _PK_H_(0x15, 0x76) ++#define REG_SC_BK15_77_L _PK_L_(0x15, 0x77) ++#define REG_SC_BK15_77_H _PK_H_(0x15, 0x77) ++#define REG_SC_BK15_78_L _PK_L_(0x15, 0x78) ++#define REG_SC_BK15_78_H _PK_H_(0x15, 0x78) ++#define REG_SC_BK15_79_L _PK_L_(0x15, 0x79) ++#define REG_SC_BK15_79_H _PK_H_(0x15, 0x79) ++#define REG_SC_BK15_7A_L _PK_L_(0x15, 0x7A) ++#define REG_SC_BK15_7A_H _PK_H_(0x15, 0x7A) ++#define REG_SC_BK15_7B_L _PK_L_(0x15, 0x7B) ++#define REG_SC_BK15_7B_H _PK_H_(0x15, 0x7B) ++#define REG_SC_BK15_7C_L _PK_L_(0x15, 0x7C) ++#define REG_SC_BK15_7C_H _PK_H_(0x15, 0x7C) ++#define REG_SC_BK15_7D_L _PK_L_(0x15, 0x7D) ++#define REG_SC_BK15_7D_H _PK_H_(0x15, 0x7D) ++#define REG_SC_BK15_7E_L _PK_L_(0x15, 0x7E) ++#define REG_SC_BK15_7E_H _PK_H_(0x15, 0x7E) ++#define REG_SC_BK15_7F_L _PK_L_(0x15, 0x7F) ++#define REG_SC_BK15_7F_H _PK_H_(0x15, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK16_00_L _PK_L_(0x16, 0x00) ++#define REG_SC_BK16_00_H _PK_H_(0x16, 0x00) ++#define REG_SC_BK16_01_L _PK_L_(0x16, 0x01) ++#define REG_SC_BK16_01_H _PK_H_(0x16, 0x01) ++#define REG_SC_BK16_02_L _PK_L_(0x16, 0x02) ++#define REG_SC_BK16_02_H _PK_H_(0x16, 0x02) ++#define REG_SC_BK16_03_L _PK_L_(0x16, 0x03) ++#define REG_SC_BK16_03_H _PK_H_(0x16, 0x03) ++#define REG_SC_BK16_04_L _PK_L_(0x16, 0x04) ++#define REG_SC_BK16_04_H _PK_H_(0x16, 0x04) ++#define REG_SC_BK16_05_L _PK_L_(0x16, 0x05) ++#define REG_SC_BK16_05_H _PK_H_(0x16, 0x05) ++#define REG_SC_BK16_06_L _PK_L_(0x16, 0x06) ++#define REG_SC_BK16_06_H _PK_H_(0x16, 0x06) ++#define REG_SC_BK16_07_L _PK_L_(0x16, 0x07) ++#define REG_SC_BK16_07_H _PK_H_(0x16, 0x07) ++#define REG_SC_BK16_08_L _PK_L_(0x16, 0x08) ++#define REG_SC_BK16_08_H _PK_H_(0x16, 0x08) ++#define REG_SC_BK16_09_L _PK_L_(0x16, 0x09) ++#define REG_SC_BK16_09_H _PK_H_(0x16, 0x09) ++#define REG_SC_BK16_0A_L _PK_L_(0x16, 0x0A) ++#define REG_SC_BK16_0A_H _PK_H_(0x16, 0x0A) ++#define REG_SC_BK16_0B_L _PK_L_(0x16, 0x0B) ++#define REG_SC_BK16_0B_H _PK_H_(0x16, 0x0B) ++#define REG_SC_BK16_0C_L _PK_L_(0x16, 0x0C) ++#define REG_SC_BK16_0C_H _PK_H_(0x16, 0x0C) ++#define REG_SC_BK16_0D_L _PK_L_(0x16, 0x0D) ++#define REG_SC_BK16_0D_H _PK_H_(0x16, 0x0D) ++#define REG_SC_BK16_0E_L _PK_L_(0x16, 0x0E) ++#define REG_SC_BK16_0E_H _PK_H_(0x16, 0x0E) ++#define REG_SC_BK16_0F_L _PK_L_(0x16, 0x0F) ++#define REG_SC_BK16_0F_H _PK_H_(0x16, 0x0F) ++#define REG_SC_BK16_10_L _PK_L_(0x16, 0x10) ++#define REG_SC_BK16_10_H _PK_H_(0x16, 0x10) ++#define REG_SC_BK16_11_L _PK_L_(0x16, 0x11) ++#define REG_SC_BK16_11_H _PK_H_(0x16, 0x11) ++#define REG_SC_BK16_12_L _PK_L_(0x16, 0x12) ++#define REG_SC_BK16_12_H _PK_H_(0x16, 0x12) ++#define REG_SC_BK16_13_L _PK_L_(0x16, 0x13) ++#define REG_SC_BK16_13_H _PK_H_(0x16, 0x13) ++#define REG_SC_BK16_14_L _PK_L_(0x16, 0x14) ++#define REG_SC_BK16_14_H _PK_H_(0x16, 0x14) ++#define REG_SC_BK16_15_L _PK_L_(0x16, 0x15) ++#define REG_SC_BK16_15_H _PK_H_(0x16, 0x15) ++#define REG_SC_BK16_16_L _PK_L_(0x16, 0x16) ++#define REG_SC_BK16_16_H _PK_H_(0x16, 0x16) ++#define REG_SC_BK16_17_L _PK_L_(0x16, 0x17) ++#define REG_SC_BK16_17_H _PK_H_(0x16, 0x17) ++#define REG_SC_BK16_18_L _PK_L_(0x16, 0x18) ++#define REG_SC_BK16_18_H _PK_H_(0x16, 0x18) ++#define REG_SC_BK16_19_L _PK_L_(0x16, 0x19) ++#define REG_SC_BK16_19_H _PK_H_(0x16, 0x19) ++#define REG_SC_BK16_1A_L _PK_L_(0x16, 0x1A) ++#define REG_SC_BK16_1A_H _PK_H_(0x16, 0x1A) ++#define REG_SC_BK16_1B_L _PK_L_(0x16, 0x1B) ++#define REG_SC_BK16_1B_H _PK_H_(0x16, 0x1B) ++#define REG_SC_BK16_1C_L _PK_L_(0x16, 0x1C) ++#define REG_SC_BK16_1C_H _PK_H_(0x16, 0x1C) ++#define REG_SC_BK16_1D_L _PK_L_(0x16, 0x1D) ++#define REG_SC_BK16_1D_H _PK_H_(0x16, 0x1D) ++#define REG_SC_BK16_1E_L _PK_L_(0x16, 0x1E) ++#define REG_SC_BK16_1E_H _PK_H_(0x16, 0x1E) ++#define REG_SC_BK16_1F_L _PK_L_(0x16, 0x1F) ++#define REG_SC_BK16_1F_H _PK_H_(0x16, 0x1F) ++#define REG_SC_BK16_20_L _PK_L_(0x16, 0x20) ++#define REG_SC_BK16_20_H _PK_H_(0x16, 0x20) ++#define REG_SC_BK16_21_L _PK_L_(0x16, 0x21) ++#define REG_SC_BK16_21_H _PK_H_(0x16, 0x21) ++#define REG_SC_BK16_22_L _PK_L_(0x16, 0x22) ++#define REG_SC_BK16_22_H _PK_H_(0x16, 0x22) ++#define REG_SC_BK16_23_L _PK_L_(0x16, 0x23) ++#define REG_SC_BK16_23_H _PK_H_(0x16, 0x23) ++#define REG_SC_BK16_24_L _PK_L_(0x16, 0x24) ++#define REG_SC_BK16_24_H _PK_H_(0x16, 0x24) ++#define REG_SC_BK16_25_L _PK_L_(0x16, 0x25) ++#define REG_SC_BK16_25_H _PK_H_(0x16, 0x25) ++#define REG_SC_BK16_26_L _PK_L_(0x16, 0x26) ++#define REG_SC_BK16_26_H _PK_H_(0x16, 0x26) ++#define REG_SC_BK16_27_L _PK_L_(0x16, 0x27) ++#define REG_SC_BK16_27_H _PK_H_(0x16, 0x27) ++#define REG_SC_BK16_28_L _PK_L_(0x16, 0x28) ++#define REG_SC_BK16_28_H _PK_H_(0x16, 0x28) ++#define REG_SC_BK16_29_L _PK_L_(0x16, 0x29) ++#define REG_SC_BK16_29_H _PK_H_(0x16, 0x29) ++#define REG_SC_BK16_2A_L _PK_L_(0x16, 0x2A) ++#define REG_SC_BK16_2A_H _PK_H_(0x16, 0x2A) ++#define REG_SC_BK16_2B_L _PK_L_(0x16, 0x2B) ++#define REG_SC_BK16_2B_H _PK_H_(0x16, 0x2B) ++#define REG_SC_BK16_2C_L _PK_L_(0x16, 0x2C) ++#define REG_SC_BK16_2C_H _PK_H_(0x16, 0x2C) ++#define REG_SC_BK16_2D_L _PK_L_(0x16, 0x2D) ++#define REG_SC_BK16_2D_H _PK_H_(0x16, 0x2D) ++#define REG_SC_BK16_2E_L _PK_L_(0x16, 0x2E) ++#define REG_SC_BK16_2E_H _PK_H_(0x16, 0x2E) ++#define REG_SC_BK16_2F_L _PK_L_(0x16, 0x2F) ++#define REG_SC_BK16_2F_H _PK_H_(0x16, 0x2F) ++#define REG_SC_BK16_30_L _PK_L_(0x16, 0x30) ++#define REG_SC_BK16_30_H _PK_H_(0x16, 0x30) ++#define REG_SC_BK16_31_L _PK_L_(0x16, 0x31) ++#define REG_SC_BK16_31_H _PK_H_(0x16, 0x31) ++#define REG_SC_BK16_32_L _PK_L_(0x16, 0x32) ++#define REG_SC_BK16_32_H _PK_H_(0x16, 0x32) ++#define REG_SC_BK16_33_L _PK_L_(0x16, 0x33) ++#define REG_SC_BK16_33_H _PK_H_(0x16, 0x33) ++#define REG_SC_BK16_34_L _PK_L_(0x16, 0x34) ++#define REG_SC_BK16_34_H _PK_H_(0x16, 0x34) ++#define REG_SC_BK16_35_L _PK_L_(0x16, 0x35) ++#define REG_SC_BK16_35_H _PK_H_(0x16, 0x35) ++#define REG_SC_BK16_36_L _PK_L_(0x16, 0x36) ++#define REG_SC_BK16_36_H _PK_H_(0x16, 0x36) ++#define REG_SC_BK16_37_L _PK_L_(0x16, 0x37) ++#define REG_SC_BK16_37_H _PK_H_(0x16, 0x37) ++#define REG_SC_BK16_38_L _PK_L_(0x16, 0x38) ++#define REG_SC_BK16_38_H _PK_H_(0x16, 0x38) ++#define REG_SC_BK16_39_L _PK_L_(0x16, 0x39) ++#define REG_SC_BK16_39_H _PK_H_(0x16, 0x39) ++#define REG_SC_BK16_3A_L _PK_L_(0x16, 0x3A) ++#define REG_SC_BK16_3A_H _PK_H_(0x16, 0x3A) ++#define REG_SC_BK16_3B_L _PK_L_(0x16, 0x3B) ++#define REG_SC_BK16_3B_H _PK_H_(0x16, 0x3B) ++#define REG_SC_BK16_3C_L _PK_L_(0x16, 0x3C) ++#define REG_SC_BK16_3C_H _PK_H_(0x16, 0x3C) ++#define REG_SC_BK16_3D_L _PK_L_(0x16, 0x3D) ++#define REG_SC_BK16_3D_H _PK_H_(0x16, 0x3D) ++#define REG_SC_BK16_3E_L _PK_L_(0x16, 0x3E) ++#define REG_SC_BK16_3E_H _PK_H_(0x16, 0x3E) ++#define REG_SC_BK16_3F_L _PK_L_(0x16, 0x3F) ++#define REG_SC_BK16_3F_H _PK_H_(0x16, 0x3F) ++#define REG_SC_BK16_40_L _PK_L_(0x16, 0x40) ++#define REG_SC_BK16_40_H _PK_H_(0x16, 0x40) ++#define REG_SC_BK16_41_L _PK_L_(0x16, 0x41) ++#define REG_SC_BK16_41_H _PK_H_(0x16, 0x41) ++#define REG_SC_BK16_42_L _PK_L_(0x16, 0x42) ++#define REG_SC_BK16_42_H _PK_H_(0x16, 0x42) ++#define REG_SC_BK16_43_L _PK_L_(0x16, 0x43) ++#define REG_SC_BK16_43_H _PK_H_(0x16, 0x43) ++#define REG_SC_BK16_44_L _PK_L_(0x16, 0x44) ++#define REG_SC_BK16_44_H _PK_H_(0x16, 0x44) ++#define REG_SC_BK16_45_L _PK_L_(0x16, 0x45) ++#define REG_SC_BK16_45_H _PK_H_(0x16, 0x45) ++#define REG_SC_BK16_46_L _PK_L_(0x16, 0x46) ++#define REG_SC_BK16_46_H _PK_H_(0x16, 0x46) ++#define REG_SC_BK16_47_L _PK_L_(0x16, 0x47) ++#define REG_SC_BK16_47_H _PK_H_(0x16, 0x47) ++#define REG_SC_BK16_48_L _PK_L_(0x16, 0x48) ++#define REG_SC_BK16_48_H _PK_H_(0x16, 0x48) ++#define REG_SC_BK16_49_L _PK_L_(0x16, 0x49) ++#define REG_SC_BK16_49_H _PK_H_(0x16, 0x49) ++#define REG_SC_BK16_4A_L _PK_L_(0x16, 0x4A) ++#define REG_SC_BK16_4A_H _PK_H_(0x16, 0x4A) ++#define REG_SC_BK16_4B_L _PK_L_(0x16, 0x4B) ++#define REG_SC_BK16_4B_H _PK_H_(0x16, 0x4B) ++#define REG_SC_BK16_4C_L _PK_L_(0x16, 0x4C) ++#define REG_SC_BK16_4C_H _PK_H_(0x16, 0x4C) ++#define REG_SC_BK16_4D_L _PK_L_(0x16, 0x4D) ++#define REG_SC_BK16_4D_H _PK_H_(0x16, 0x4D) ++#define REG_SC_BK16_4E_L _PK_L_(0x16, 0x4E) ++#define REG_SC_BK16_4E_H _PK_H_(0x16, 0x4E) ++#define REG_SC_BK16_4F_L _PK_L_(0x16, 0x4F) ++#define REG_SC_BK16_4F_H _PK_H_(0x16, 0x4F) ++#define REG_SC_BK16_50_L _PK_L_(0x16, 0x50) ++#define REG_SC_BK16_50_H _PK_H_(0x16, 0x50) ++#define REG_SC_BK16_51_L _PK_L_(0x16, 0x51) ++#define REG_SC_BK16_51_H _PK_H_(0x16, 0x51) ++#define REG_SC_BK16_52_L _PK_L_(0x16, 0x52) ++#define REG_SC_BK16_52_H _PK_H_(0x16, 0x52) ++#define REG_SC_BK16_53_L _PK_L_(0x16, 0x53) ++#define REG_SC_BK16_53_H _PK_H_(0x16, 0x53) ++#define REG_SC_BK16_54_L _PK_L_(0x16, 0x54) ++#define REG_SC_BK16_54_H _PK_H_(0x16, 0x54) ++#define REG_SC_BK16_55_L _PK_L_(0x16, 0x55) ++#define REG_SC_BK16_55_H _PK_H_(0x16, 0x55) ++#define REG_SC_BK16_56_L _PK_L_(0x16, 0x56) ++#define REG_SC_BK16_56_H _PK_H_(0x16, 0x56) ++#define REG_SC_BK16_57_L _PK_L_(0x16, 0x57) ++#define REG_SC_BK16_57_H _PK_H_(0x16, 0x57) ++#define REG_SC_BK16_58_L _PK_L_(0x16, 0x58) ++#define REG_SC_BK16_58_H _PK_H_(0x16, 0x58) ++#define REG_SC_BK16_59_L _PK_L_(0x16, 0x59) ++#define REG_SC_BK16_59_H _PK_H_(0x16, 0x59) ++#define REG_SC_BK16_5A_L _PK_L_(0x16, 0x5A) ++#define REG_SC_BK16_5A_H _PK_H_(0x16, 0x5A) ++#define REG_SC_BK16_5B_L _PK_L_(0x16, 0x5B) ++#define REG_SC_BK16_5B_H _PK_H_(0x16, 0x5B) ++#define REG_SC_BK16_5C_L _PK_L_(0x16, 0x5C) ++#define REG_SC_BK16_5C_H _PK_H_(0x16, 0x5C) ++#define REG_SC_BK16_5D_L _PK_L_(0x16, 0x5D) ++#define REG_SC_BK16_5D_H _PK_H_(0x16, 0x5D) ++#define REG_SC_BK16_5E_L _PK_L_(0x16, 0x5E) ++#define REG_SC_BK16_5E_H _PK_H_(0x16, 0x5E) ++#define REG_SC_BK16_5F_L _PK_L_(0x16, 0x5F) ++#define REG_SC_BK16_5F_H _PK_H_(0x16, 0x5F) ++#define REG_SC_BK16_60_L _PK_L_(0x16, 0x60) ++#define REG_SC_BK16_60_H _PK_H_(0x16, 0x60) ++#define REG_SC_BK16_61_L _PK_L_(0x16, 0x61) ++#define REG_SC_BK16_61_H _PK_H_(0x16, 0x61) ++#define REG_SC_BK16_62_L _PK_L_(0x16, 0x62) ++#define REG_SC_BK16_62_H _PK_H_(0x16, 0x62) ++#define REG_SC_BK16_63_L _PK_L_(0x16, 0x63) ++#define REG_SC_BK16_63_H _PK_H_(0x16, 0x63) ++#define REG_SC_BK16_64_L _PK_L_(0x16, 0x64) ++#define REG_SC_BK16_64_H _PK_H_(0x16, 0x64) ++#define REG_SC_BK16_65_L _PK_L_(0x16, 0x65) ++#define REG_SC_BK16_65_H _PK_H_(0x16, 0x65) ++#define REG_SC_BK16_66_L _PK_L_(0x16, 0x66) ++#define REG_SC_BK16_66_H _PK_H_(0x16, 0x66) ++#define REG_SC_BK16_67_L _PK_L_(0x16, 0x67) ++#define REG_SC_BK16_67_H _PK_H_(0x16, 0x67) ++#define REG_SC_BK16_68_L _PK_L_(0x16, 0x68) ++#define REG_SC_BK16_68_H _PK_H_(0x16, 0x68) ++#define REG_SC_BK16_69_L _PK_L_(0x16, 0x69) ++#define REG_SC_BK16_69_H _PK_H_(0x16, 0x69) ++#define REG_SC_BK16_6A_L _PK_L_(0x16, 0x6A) ++#define REG_SC_BK16_6A_H _PK_H_(0x16, 0x6A) ++#define REG_SC_BK16_6B_L _PK_L_(0x16, 0x6B) ++#define REG_SC_BK16_6B_H _PK_H_(0x16, 0x6B) ++#define REG_SC_BK16_6C_L _PK_L_(0x16, 0x6C) ++#define REG_SC_BK16_6C_H _PK_H_(0x16, 0x6C) ++#define REG_SC_BK16_6D_L _PK_L_(0x16, 0x6D) ++#define REG_SC_BK16_6D_H _PK_H_(0x16, 0x6D) ++#define REG_SC_BK16_6E_L _PK_L_(0x16, 0x6E) ++#define REG_SC_BK16_6E_H _PK_H_(0x16, 0x6E) ++#define REG_SC_BK16_6F_L _PK_L_(0x16, 0x6F) ++#define REG_SC_BK16_6F_H _PK_H_(0x16, 0x6F) ++#define REG_SC_BK16_70_L _PK_L_(0x16, 0x70) ++#define REG_SC_BK16_70_H _PK_H_(0x16, 0x70) ++#define REG_SC_BK16_71_L _PK_L_(0x16, 0x71) ++#define REG_SC_BK16_71_H _PK_H_(0x16, 0x71) ++#define REG_SC_BK16_72_L _PK_L_(0x16, 0x72) ++#define REG_SC_BK16_72_H _PK_H_(0x16, 0x72) ++#define REG_SC_BK16_73_L _PK_L_(0x16, 0x73) ++#define REG_SC_BK16_73_H _PK_H_(0x16, 0x73) ++#define REG_SC_BK16_74_L _PK_L_(0x16, 0x74) ++#define REG_SC_BK16_74_H _PK_H_(0x16, 0x74) ++#define REG_SC_BK16_75_L _PK_L_(0x16, 0x75) ++#define REG_SC_BK16_75_H _PK_H_(0x16, 0x75) ++#define REG_SC_BK16_76_L _PK_L_(0x16, 0x76) ++#define REG_SC_BK16_76_H _PK_H_(0x16, 0x76) ++#define REG_SC_BK16_77_L _PK_L_(0x16, 0x77) ++#define REG_SC_BK16_77_H _PK_H_(0x16, 0x77) ++#define REG_SC_BK16_78_L _PK_L_(0x16, 0x78) ++#define REG_SC_BK16_78_H _PK_H_(0x16, 0x78) ++#define REG_SC_BK16_79_L _PK_L_(0x16, 0x79) ++#define REG_SC_BK16_79_H _PK_H_(0x16, 0x79) ++#define REG_SC_BK16_7A_L _PK_L_(0x16, 0x7A) ++#define REG_SC_BK16_7A_H _PK_H_(0x16, 0x7A) ++#define REG_SC_BK16_7B_L _PK_L_(0x16, 0x7B) ++#define REG_SC_BK16_7B_H _PK_H_(0x16, 0x7B) ++#define REG_SC_BK16_7C_L _PK_L_(0x16, 0x7C) ++#define REG_SC_BK16_7C_H _PK_H_(0x16, 0x7C) ++#define REG_SC_BK16_7D_L _PK_L_(0x16, 0x7D) ++#define REG_SC_BK16_7D_H _PK_H_(0x16, 0x7D) ++#define REG_SC_BK16_7E_L _PK_L_(0x16, 0x7E) ++#define REG_SC_BK16_7E_H _PK_H_(0x16, 0x7E) ++#define REG_SC_BK16_7F_L _PK_L_(0x16, 0x7F) ++#define REG_SC_BK16_7F_H _PK_H_(0x16, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK17_00_L _PK_L_(0x17, 0x00) ++#define REG_SC_BK17_00_H _PK_H_(0x17, 0x00) ++#define REG_SC_BK17_01_L _PK_L_(0x17, 0x01) ++#define REG_SC_BK17_01_H _PK_H_(0x17, 0x01) ++#define REG_SC_BK17_02_L _PK_L_(0x17, 0x02) ++#define REG_SC_BK17_02_H _PK_H_(0x17, 0x02) ++#define REG_SC_BK17_03_L _PK_L_(0x17, 0x03) ++#define REG_SC_BK17_03_H _PK_H_(0x17, 0x03) ++#define REG_SC_BK17_04_L _PK_L_(0x17, 0x04) ++#define REG_SC_BK17_04_H _PK_H_(0x17, 0x04) ++#define REG_SC_BK17_05_L _PK_L_(0x17, 0x05) ++#define REG_SC_BK17_05_H _PK_H_(0x17, 0x05) ++#define REG_SC_BK17_06_L _PK_L_(0x17, 0x06) ++#define REG_SC_BK17_06_H _PK_H_(0x17, 0x06) ++#define REG_SC_BK17_07_L _PK_L_(0x17, 0x07) ++#define REG_SC_BK17_07_H _PK_H_(0x17, 0x07) ++#define REG_SC_BK17_08_L _PK_L_(0x17, 0x08) ++#define REG_SC_BK17_08_H _PK_H_(0x17, 0x08) ++#define REG_SC_BK17_09_L _PK_L_(0x17, 0x09) ++#define REG_SC_BK17_09_H _PK_H_(0x17, 0x09) ++#define REG_SC_BK17_0A_L _PK_L_(0x17, 0x0A) ++#define REG_SC_BK17_0A_H _PK_H_(0x17, 0x0A) ++#define REG_SC_BK17_0B_L _PK_L_(0x17, 0x0B) ++#define REG_SC_BK17_0B_H _PK_H_(0x17, 0x0B) ++#define REG_SC_BK17_0C_L _PK_L_(0x17, 0x0C) ++#define REG_SC_BK17_0C_H _PK_H_(0x17, 0x0C) ++#define REG_SC_BK17_0D_L _PK_L_(0x17, 0x0D) ++#define REG_SC_BK17_0D_H _PK_H_(0x17, 0x0D) ++#define REG_SC_BK17_0E_L _PK_L_(0x17, 0x0E) ++#define REG_SC_BK17_0E_H _PK_H_(0x17, 0x0E) ++#define REG_SC_BK17_0F_L _PK_L_(0x17, 0x0F) ++#define REG_SC_BK17_0F_H _PK_H_(0x17, 0x0F) ++#define REG_SC_BK17_10_L _PK_L_(0x17, 0x10) ++#define REG_SC_BK17_10_H _PK_H_(0x17, 0x10) ++#define REG_SC_BK17_11_L _PK_L_(0x17, 0x11) ++#define REG_SC_BK17_11_H _PK_H_(0x17, 0x11) ++#define REG_SC_BK17_12_L _PK_L_(0x17, 0x12) ++#define REG_SC_BK17_12_H _PK_H_(0x17, 0x12) ++#define REG_SC_BK17_13_L _PK_L_(0x17, 0x13) ++#define REG_SC_BK17_13_H _PK_H_(0x17, 0x13) ++#define REG_SC_BK17_14_L _PK_L_(0x17, 0x14) ++#define REG_SC_BK17_14_H _PK_H_(0x17, 0x14) ++#define REG_SC_BK17_15_L _PK_L_(0x17, 0x15) ++#define REG_SC_BK17_15_H _PK_H_(0x17, 0x15) ++#define REG_SC_BK17_16_L _PK_L_(0x17, 0x16) ++#define REG_SC_BK17_16_H _PK_H_(0x17, 0x16) ++#define REG_SC_BK17_17_L _PK_L_(0x17, 0x17) ++#define REG_SC_BK17_17_H _PK_H_(0x17, 0x17) ++#define REG_SC_BK17_18_L _PK_L_(0x17, 0x18) ++#define REG_SC_BK17_18_H _PK_H_(0x17, 0x18) ++#define REG_SC_BK17_19_L _PK_L_(0x17, 0x19) ++#define REG_SC_BK17_19_H _PK_H_(0x17, 0x19) ++#define REG_SC_BK17_1A_L _PK_L_(0x17, 0x1A) ++#define REG_SC_BK17_1A_H _PK_H_(0x17, 0x1A) ++#define REG_SC_BK17_1B_L _PK_L_(0x17, 0x1B) ++#define REG_SC_BK17_1B_H _PK_H_(0x17, 0x1B) ++#define REG_SC_BK17_1C_L _PK_L_(0x17, 0x1C) ++#define REG_SC_BK17_1C_H _PK_H_(0x17, 0x1C) ++#define REG_SC_BK17_1D_L _PK_L_(0x17, 0x1D) ++#define REG_SC_BK17_1D_H _PK_H_(0x17, 0x1D) ++#define REG_SC_BK17_1E_L _PK_L_(0x17, 0x1E) ++#define REG_SC_BK17_1E_H _PK_H_(0x17, 0x1E) ++#define REG_SC_BK17_1F_L _PK_L_(0x17, 0x1F) ++#define REG_SC_BK17_1F_H _PK_H_(0x17, 0x1F) ++#define REG_SC_BK17_20_L _PK_L_(0x17, 0x20) ++#define REG_SC_BK17_20_H _PK_H_(0x17, 0x20) ++#define REG_SC_BK17_21_L _PK_L_(0x17, 0x21) ++#define REG_SC_BK17_21_H _PK_H_(0x17, 0x21) ++#define REG_SC_BK17_22_L _PK_L_(0x17, 0x22) ++#define REG_SC_BK17_22_H _PK_H_(0x17, 0x22) ++#define REG_SC_BK17_23_L _PK_L_(0x17, 0x23) ++#define REG_SC_BK17_23_H _PK_H_(0x17, 0x23) ++#define REG_SC_BK17_24_L _PK_L_(0x17, 0x24) ++#define REG_SC_BK17_24_H _PK_H_(0x17, 0x24) ++#define REG_SC_BK17_25_L _PK_L_(0x17, 0x25) ++#define REG_SC_BK17_25_H _PK_H_(0x17, 0x25) ++#define REG_SC_BK17_26_L _PK_L_(0x17, 0x26) ++#define REG_SC_BK17_26_H _PK_H_(0x17, 0x26) ++#define REG_SC_BK17_27_L _PK_L_(0x17, 0x27) ++#define REG_SC_BK17_27_H _PK_H_(0x17, 0x27) ++#define REG_SC_BK17_28_L _PK_L_(0x17, 0x28) ++#define REG_SC_BK17_28_H _PK_H_(0x17, 0x28) ++#define REG_SC_BK17_29_L _PK_L_(0x17, 0x29) ++#define REG_SC_BK17_29_H _PK_H_(0x17, 0x29) ++#define REG_SC_BK17_2A_L _PK_L_(0x17, 0x2A) ++#define REG_SC_BK17_2A_H _PK_H_(0x17, 0x2A) ++#define REG_SC_BK17_2B_L _PK_L_(0x17, 0x2B) ++#define REG_SC_BK17_2B_H _PK_H_(0x17, 0x2B) ++#define REG_SC_BK17_2C_L _PK_L_(0x17, 0x2C) ++#define REG_SC_BK17_2C_H _PK_H_(0x17, 0x2C) ++#define REG_SC_BK17_2D_L _PK_L_(0x17, 0x2D) ++#define REG_SC_BK17_2D_H _PK_H_(0x17, 0x2D) ++#define REG_SC_BK17_2E_L _PK_L_(0x17, 0x2E) ++#define REG_SC_BK17_2E_H _PK_H_(0x17, 0x2E) ++#define REG_SC_BK17_2F_L _PK_L_(0x17, 0x2F) ++#define REG_SC_BK17_2F_H _PK_H_(0x17, 0x2F) ++#define REG_SC_BK17_30_L _PK_L_(0x17, 0x30) ++#define REG_SC_BK17_30_H _PK_H_(0x17, 0x30) ++#define REG_SC_BK17_31_L _PK_L_(0x17, 0x31) ++#define REG_SC_BK17_31_H _PK_H_(0x17, 0x31) ++#define REG_SC_BK17_32_L _PK_L_(0x17, 0x32) ++#define REG_SC_BK17_32_H _PK_H_(0x17, 0x32) ++#define REG_SC_BK17_33_L _PK_L_(0x17, 0x33) ++#define REG_SC_BK17_33_H _PK_H_(0x17, 0x33) ++#define REG_SC_BK17_34_L _PK_L_(0x17, 0x34) ++#define REG_SC_BK17_34_H _PK_H_(0x17, 0x34) ++#define REG_SC_BK17_35_L _PK_L_(0x17, 0x35) ++#define REG_SC_BK17_35_H _PK_H_(0x17, 0x35) ++#define REG_SC_BK17_36_L _PK_L_(0x17, 0x36) ++#define REG_SC_BK17_36_H _PK_H_(0x17, 0x36) ++#define REG_SC_BK17_37_L _PK_L_(0x17, 0x37) ++#define REG_SC_BK17_37_H _PK_H_(0x17, 0x37) ++#define REG_SC_BK17_38_L _PK_L_(0x17, 0x38) ++#define REG_SC_BK17_38_H _PK_H_(0x17, 0x38) ++#define REG_SC_BK17_39_L _PK_L_(0x17, 0x39) ++#define REG_SC_BK17_39_H _PK_H_(0x17, 0x39) ++#define REG_SC_BK17_3A_L _PK_L_(0x17, 0x3A) ++#define REG_SC_BK17_3A_H _PK_H_(0x17, 0x3A) ++#define REG_SC_BK17_3B_L _PK_L_(0x17, 0x3B) ++#define REG_SC_BK17_3B_H _PK_H_(0x17, 0x3B) ++#define REG_SC_BK17_3C_L _PK_L_(0x17, 0x3C) ++#define REG_SC_BK17_3C_H _PK_H_(0x17, 0x3C) ++#define REG_SC_BK17_3D_L _PK_L_(0x17, 0x3D) ++#define REG_SC_BK17_3D_H _PK_H_(0x17, 0x3D) ++#define REG_SC_BK17_3E_L _PK_L_(0x17, 0x3E) ++#define REG_SC_BK17_3E_H _PK_H_(0x17, 0x3E) ++#define REG_SC_BK17_3F_L _PK_L_(0x17, 0x3F) ++#define REG_SC_BK17_3F_H _PK_H_(0x17, 0x3F) ++#define REG_SC_BK17_40_L _PK_L_(0x17, 0x40) ++#define REG_SC_BK17_40_H _PK_H_(0x17, 0x40) ++#define REG_SC_BK17_41_L _PK_L_(0x17, 0x41) ++#define REG_SC_BK17_41_H _PK_H_(0x17, 0x41) ++#define REG_SC_BK17_42_L _PK_L_(0x17, 0x42) ++#define REG_SC_BK17_42_H _PK_H_(0x17, 0x42) ++#define REG_SC_BK17_43_L _PK_L_(0x17, 0x43) ++#define REG_SC_BK17_43_H _PK_H_(0x17, 0x43) ++#define REG_SC_BK17_44_L _PK_L_(0x17, 0x44) ++#define REG_SC_BK17_44_H _PK_H_(0x17, 0x44) ++#define REG_SC_BK17_45_L _PK_L_(0x17, 0x45) ++#define REG_SC_BK17_45_H _PK_H_(0x17, 0x45) ++#define REG_SC_BK17_46_L _PK_L_(0x17, 0x46) ++#define REG_SC_BK17_46_H _PK_H_(0x17, 0x46) ++#define REG_SC_BK17_47_L _PK_L_(0x17, 0x47) ++#define REG_SC_BK17_47_H _PK_H_(0x17, 0x47) ++#define REG_SC_BK17_48_L _PK_L_(0x17, 0x48) ++#define REG_SC_BK17_48_H _PK_H_(0x17, 0x48) ++#define REG_SC_BK17_49_L _PK_L_(0x17, 0x49) ++#define REG_SC_BK17_49_H _PK_H_(0x17, 0x49) ++#define REG_SC_BK17_4A_L _PK_L_(0x17, 0x4A) ++#define REG_SC_BK17_4A_H _PK_H_(0x17, 0x4A) ++#define REG_SC_BK17_4B_L _PK_L_(0x17, 0x4B) ++#define REG_SC_BK17_4B_H _PK_H_(0x17, 0x4B) ++#define REG_SC_BK17_4C_L _PK_L_(0x17, 0x4C) ++#define REG_SC_BK17_4C_H _PK_H_(0x17, 0x4C) ++#define REG_SC_BK17_4D_L _PK_L_(0x17, 0x4D) ++#define REG_SC_BK17_4D_H _PK_H_(0x17, 0x4D) ++#define REG_SC_BK17_4E_L _PK_L_(0x17, 0x4E) ++#define REG_SC_BK17_4E_H _PK_H_(0x17, 0x4E) ++#define REG_SC_BK17_4F_L _PK_L_(0x17, 0x4F) ++#define REG_SC_BK17_4F_H _PK_H_(0x17, 0x4F) ++#define REG_SC_BK17_50_L _PK_L_(0x17, 0x50) ++#define REG_SC_BK17_50_H _PK_H_(0x17, 0x50) ++#define REG_SC_BK17_51_L _PK_L_(0x17, 0x51) ++#define REG_SC_BK17_51_H _PK_H_(0x17, 0x51) ++#define REG_SC_BK17_52_L _PK_L_(0x17, 0x52) ++#define REG_SC_BK17_52_H _PK_H_(0x17, 0x52) ++#define REG_SC_BK17_53_L _PK_L_(0x17, 0x53) ++#define REG_SC_BK17_53_H _PK_H_(0x17, 0x53) ++#define REG_SC_BK17_54_L _PK_L_(0x17, 0x54) ++#define REG_SC_BK17_54_H _PK_H_(0x17, 0x54) ++#define REG_SC_BK17_55_L _PK_L_(0x17, 0x55) ++#define REG_SC_BK17_55_H _PK_H_(0x17, 0x55) ++#define REG_SC_BK17_56_L _PK_L_(0x17, 0x56) ++#define REG_SC_BK17_56_H _PK_H_(0x17, 0x56) ++#define REG_SC_BK17_57_L _PK_L_(0x17, 0x57) ++#define REG_SC_BK17_57_H _PK_H_(0x17, 0x57) ++#define REG_SC_BK17_58_L _PK_L_(0x17, 0x58) ++#define REG_SC_BK17_58_H _PK_H_(0x17, 0x58) ++#define REG_SC_BK17_59_L _PK_L_(0x17, 0x59) ++#define REG_SC_BK17_59_H _PK_H_(0x17, 0x59) ++#define REG_SC_BK17_5A_L _PK_L_(0x17, 0x5A) ++#define REG_SC_BK17_5A_H _PK_H_(0x17, 0x5A) ++#define REG_SC_BK17_5B_L _PK_L_(0x17, 0x5B) ++#define REG_SC_BK17_5B_H _PK_H_(0x17, 0x5B) ++#define REG_SC_BK17_5C_L _PK_L_(0x17, 0x5C) ++#define REG_SC_BK17_5C_H _PK_H_(0x17, 0x5C) ++#define REG_SC_BK17_5D_L _PK_L_(0x17, 0x5D) ++#define REG_SC_BK17_5D_H _PK_H_(0x17, 0x5D) ++#define REG_SC_BK17_5E_L _PK_L_(0x17, 0x5E) ++#define REG_SC_BK17_5E_H _PK_H_(0x17, 0x5E) ++#define REG_SC_BK17_5F_L _PK_L_(0x17, 0x5F) ++#define REG_SC_BK17_5F_H _PK_H_(0x17, 0x5F) ++#define REG_SC_BK17_60_L _PK_L_(0x17, 0x60) ++#define REG_SC_BK17_60_H _PK_H_(0x17, 0x60) ++#define REG_SC_BK17_61_L _PK_L_(0x17, 0x61) ++#define REG_SC_BK17_61_H _PK_H_(0x17, 0x61) ++#define REG_SC_BK17_62_L _PK_L_(0x17, 0x62) ++#define REG_SC_BK17_62_H _PK_H_(0x17, 0x62) ++#define REG_SC_BK17_63_L _PK_L_(0x17, 0x63) ++#define REG_SC_BK17_63_H _PK_H_(0x17, 0x63) ++#define REG_SC_BK17_64_L _PK_L_(0x17, 0x64) ++#define REG_SC_BK17_64_H _PK_H_(0x17, 0x64) ++#define REG_SC_BK17_65_L _PK_L_(0x17, 0x65) ++#define REG_SC_BK17_65_H _PK_H_(0x17, 0x65) ++#define REG_SC_BK17_66_L _PK_L_(0x17, 0x66) ++#define REG_SC_BK17_66_H _PK_H_(0x17, 0x66) ++#define REG_SC_BK17_67_L _PK_L_(0x17, 0x67) ++#define REG_SC_BK17_67_H _PK_H_(0x17, 0x67) ++#define REG_SC_BK17_68_L _PK_L_(0x17, 0x68) ++#define REG_SC_BK17_68_H _PK_H_(0x17, 0x68) ++#define REG_SC_BK17_69_L _PK_L_(0x17, 0x69) ++#define REG_SC_BK17_69_H _PK_H_(0x17, 0x69) ++#define REG_SC_BK17_6A_L _PK_L_(0x17, 0x6A) ++#define REG_SC_BK17_6A_H _PK_H_(0x17, 0x6A) ++#define REG_SC_BK17_6B_L _PK_L_(0x17, 0x6B) ++#define REG_SC_BK17_6B_H _PK_H_(0x17, 0x6B) ++#define REG_SC_BK17_6C_L _PK_L_(0x17, 0x6C) ++#define REG_SC_BK17_6C_H _PK_H_(0x17, 0x6C) ++#define REG_SC_BK17_6D_L _PK_L_(0x17, 0x6D) ++#define REG_SC_BK17_6D_H _PK_H_(0x17, 0x6D) ++#define REG_SC_BK17_6E_L _PK_L_(0x17, 0x6E) ++#define REG_SC_BK17_6E_H _PK_H_(0x17, 0x6E) ++#define REG_SC_BK17_6F_L _PK_L_(0x17, 0x6F) ++#define REG_SC_BK17_6F_H _PK_H_(0x17, 0x6F) ++#define REG_SC_BK17_70_L _PK_L_(0x17, 0x70) ++#define REG_SC_BK17_70_H _PK_H_(0x17, 0x70) ++#define REG_SC_BK17_71_L _PK_L_(0x17, 0x71) ++#define REG_SC_BK17_71_H _PK_H_(0x17, 0x71) ++#define REG_SC_BK17_72_L _PK_L_(0x17, 0x72) ++#define REG_SC_BK17_72_H _PK_H_(0x17, 0x72) ++#define REG_SC_BK17_73_L _PK_L_(0x17, 0x73) ++#define REG_SC_BK17_73_H _PK_H_(0x17, 0x73) ++#define REG_SC_BK17_74_L _PK_L_(0x17, 0x74) ++#define REG_SC_BK17_74_H _PK_H_(0x17, 0x74) ++#define REG_SC_BK17_75_L _PK_L_(0x17, 0x75) ++#define REG_SC_BK17_75_H _PK_H_(0x17, 0x75) ++#define REG_SC_BK17_76_L _PK_L_(0x17, 0x76) ++#define REG_SC_BK17_76_H _PK_H_(0x17, 0x76) ++#define REG_SC_BK17_77_L _PK_L_(0x17, 0x77) ++#define REG_SC_BK17_77_H _PK_H_(0x17, 0x77) ++#define REG_SC_BK17_78_L _PK_L_(0x17, 0x78) ++#define REG_SC_BK17_78_H _PK_H_(0x17, 0x78) ++#define REG_SC_BK17_79_L _PK_L_(0x17, 0x79) ++#define REG_SC_BK17_79_H _PK_H_(0x17, 0x79) ++#define REG_SC_BK17_7A_L _PK_L_(0x17, 0x7A) ++#define REG_SC_BK17_7A_H _PK_H_(0x17, 0x7A) ++#define REG_SC_BK17_7B_L _PK_L_(0x17, 0x7B) ++#define REG_SC_BK17_7B_H _PK_H_(0x17, 0x7B) ++#define REG_SC_BK17_7C_L _PK_L_(0x17, 0x7C) ++#define REG_SC_BK17_7C_H _PK_H_(0x17, 0x7C) ++#define REG_SC_BK17_7D_L _PK_L_(0x17, 0x7D) ++#define REG_SC_BK17_7D_H _PK_H_(0x17, 0x7D) ++#define REG_SC_BK17_7E_L _PK_L_(0x17, 0x7E) ++#define REG_SC_BK17_7E_H _PK_H_(0x17, 0x7E) ++#define REG_SC_BK17_7F_L _PK_L_(0x17, 0x7F) ++#define REG_SC_BK17_7F_H _PK_H_(0x17, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK18_00_L _PK_L_(0x18, 0x00) ++#define REG_SC_BK18_00_H _PK_H_(0x18, 0x00) ++#define REG_SC_BK18_01_L _PK_L_(0x18, 0x01) ++#define REG_SC_BK18_01_H _PK_H_(0x18, 0x01) ++#define REG_SC_BK18_02_L _PK_L_(0x18, 0x02) ++#define REG_SC_BK18_02_H _PK_H_(0x18, 0x02) ++#define REG_SC_BK18_03_L _PK_L_(0x18, 0x03) ++#define REG_SC_BK18_03_H _PK_H_(0x18, 0x03) ++#define REG_SC_BK18_04_L _PK_L_(0x18, 0x04) ++#define REG_SC_BK18_04_H _PK_H_(0x18, 0x04) ++#define REG_SC_BK18_05_L _PK_L_(0x18, 0x05) ++#define REG_SC_BK18_05_H _PK_H_(0x18, 0x05) ++#define REG_SC_BK18_06_L _PK_L_(0x18, 0x06) ++#define REG_SC_BK18_06_H _PK_H_(0x18, 0x06) ++#define REG_SC_BK18_07_L _PK_L_(0x18, 0x07) ++#define REG_SC_BK18_07_H _PK_H_(0x18, 0x07) ++#define REG_SC_BK18_08_L _PK_L_(0x18, 0x08) ++#define REG_SC_BK18_08_H _PK_H_(0x18, 0x08) ++#define REG_SC_BK18_09_L _PK_L_(0x18, 0x09) ++#define REG_SC_BK18_09_H _PK_H_(0x18, 0x09) ++#define REG_SC_BK18_0A_L _PK_L_(0x18, 0x0A) ++#define REG_SC_BK18_0A_H _PK_H_(0x18, 0x0A) ++#define REG_SC_BK18_0B_L _PK_L_(0x18, 0x0B) ++#define REG_SC_BK18_0B_H _PK_H_(0x18, 0x0B) ++#define REG_SC_BK18_0C_L _PK_L_(0x18, 0x0C) ++#define REG_SC_BK18_0C_H _PK_H_(0x18, 0x0C) ++#define REG_SC_BK18_0D_L _PK_L_(0x18, 0x0D) ++#define REG_SC_BK18_0D_H _PK_H_(0x18, 0x0D) ++#define REG_SC_BK18_0E_L _PK_L_(0x18, 0x0E) ++#define REG_SC_BK18_0E_H _PK_H_(0x18, 0x0E) ++#define REG_SC_BK18_0F_L _PK_L_(0x18, 0x0F) ++#define REG_SC_BK18_0F_H _PK_H_(0x18, 0x0F) ++#define REG_SC_BK18_10_L _PK_L_(0x18, 0x10) ++#define REG_SC_BK18_10_H _PK_H_(0x18, 0x10) ++#define REG_SC_BK18_11_L _PK_L_(0x18, 0x11) ++#define REG_SC_BK18_11_H _PK_H_(0x18, 0x11) ++#define REG_SC_BK18_12_L _PK_L_(0x18, 0x12) ++#define REG_SC_BK18_12_H _PK_H_(0x18, 0x12) ++#define REG_SC_BK18_13_L _PK_L_(0x18, 0x13) ++#define REG_SC_BK18_13_H _PK_H_(0x18, 0x13) ++#define REG_SC_BK18_14_L _PK_L_(0x18, 0x14) ++#define REG_SC_BK18_14_H _PK_H_(0x18, 0x14) ++#define REG_SC_BK18_15_L _PK_L_(0x18, 0x15) ++#define REG_SC_BK18_15_H _PK_H_(0x18, 0x15) ++#define REG_SC_BK18_16_L _PK_L_(0x18, 0x16) ++#define REG_SC_BK18_16_H _PK_H_(0x18, 0x16) ++#define REG_SC_BK18_17_L _PK_L_(0x18, 0x17) ++#define REG_SC_BK18_17_H _PK_H_(0x18, 0x17) ++#define REG_SC_BK18_18_L _PK_L_(0x18, 0x18) ++#define REG_SC_BK18_18_H _PK_H_(0x18, 0x18) ++#define REG_SC_BK18_19_L _PK_L_(0x18, 0x19) ++#define REG_SC_BK18_19_H _PK_H_(0x18, 0x19) ++#define REG_SC_BK18_1A_L _PK_L_(0x18, 0x1A) ++#define REG_SC_BK18_1A_H _PK_H_(0x18, 0x1A) ++#define REG_SC_BK18_1B_L _PK_L_(0x18, 0x1B) ++#define REG_SC_BK18_1B_H _PK_H_(0x18, 0x1B) ++#define REG_SC_BK18_1C_L _PK_L_(0x18, 0x1C) ++#define REG_SC_BK18_1C_H _PK_H_(0x18, 0x1C) ++#define REG_SC_BK18_1D_L _PK_L_(0x18, 0x1D) ++#define REG_SC_BK18_1D_H _PK_H_(0x18, 0x1D) ++#define REG_SC_BK18_1E_L _PK_L_(0x18, 0x1E) ++#define REG_SC_BK18_1E_H _PK_H_(0x18, 0x1E) ++#define REG_SC_BK18_1F_L _PK_L_(0x18, 0x1F) ++#define REG_SC_BK18_1F_H _PK_H_(0x18, 0x1F) ++#define REG_SC_BK18_20_L _PK_L_(0x18, 0x20) ++#define REG_SC_BK18_20_H _PK_H_(0x18, 0x20) ++#define REG_SC_BK18_21_L _PK_L_(0x18, 0x21) ++#define REG_SC_BK18_21_H _PK_H_(0x18, 0x21) ++#define REG_SC_BK18_22_L _PK_L_(0x18, 0x22) ++#define REG_SC_BK18_22_H _PK_H_(0x18, 0x22) ++#define REG_SC_BK18_23_L _PK_L_(0x18, 0x23) ++#define REG_SC_BK18_23_H _PK_H_(0x18, 0x23) ++#define REG_SC_BK18_24_L _PK_L_(0x18, 0x24) ++#define REG_SC_BK18_24_H _PK_H_(0x18, 0x24) ++#define REG_SC_BK18_25_L _PK_L_(0x18, 0x25) ++#define REG_SC_BK18_25_H _PK_H_(0x18, 0x25) ++#define REG_SC_BK18_26_L _PK_L_(0x18, 0x26) ++#define REG_SC_BK18_26_H _PK_H_(0x18, 0x26) ++#define REG_SC_BK18_27_L _PK_L_(0x18, 0x27) ++#define REG_SC_BK18_27_H _PK_H_(0x18, 0x27) ++#define REG_SC_BK18_28_L _PK_L_(0x18, 0x28) ++#define REG_SC_BK18_28_H _PK_H_(0x18, 0x28) ++#define REG_SC_BK18_29_L _PK_L_(0x18, 0x29) ++#define REG_SC_BK18_29_H _PK_H_(0x18, 0x29) ++#define REG_SC_BK18_2A_L _PK_L_(0x18, 0x2A) ++#define REG_SC_BK18_2A_H _PK_H_(0x18, 0x2A) ++#define REG_SC_BK18_2B_L _PK_L_(0x18, 0x2B) ++#define REG_SC_BK18_2B_H _PK_H_(0x18, 0x2B) ++#define REG_SC_BK18_2C_L _PK_L_(0x18, 0x2C) ++#define REG_SC_BK18_2C_H _PK_H_(0x18, 0x2C) ++#define REG_SC_BK18_2D_L _PK_L_(0x18, 0x2D) ++#define REG_SC_BK18_2D_H _PK_H_(0x18, 0x2D) ++#define REG_SC_BK18_2E_L _PK_L_(0x18, 0x2E) ++#define REG_SC_BK18_2E_H _PK_H_(0x18, 0x2E) ++#define REG_SC_BK18_2F_L _PK_L_(0x18, 0x2F) ++#define REG_SC_BK18_2F_H _PK_H_(0x18, 0x2F) ++#define REG_SC_BK18_30_L _PK_L_(0x18, 0x30) ++#define REG_SC_BK18_30_H _PK_H_(0x18, 0x30) ++#define REG_SC_BK18_31_L _PK_L_(0x18, 0x31) ++#define REG_SC_BK18_31_H _PK_H_(0x18, 0x31) ++#define REG_SC_BK18_32_L _PK_L_(0x18, 0x32) ++#define REG_SC_BK18_32_H _PK_H_(0x18, 0x32) ++#define REG_SC_BK18_33_L _PK_L_(0x18, 0x33) ++#define REG_SC_BK18_33_H _PK_H_(0x18, 0x33) ++#define REG_SC_BK18_34_L _PK_L_(0x18, 0x34) ++#define REG_SC_BK18_34_H _PK_H_(0x18, 0x34) ++#define REG_SC_BK18_35_L _PK_L_(0x18, 0x35) ++#define REG_SC_BK18_35_H _PK_H_(0x18, 0x35) ++#define REG_SC_BK18_36_L _PK_L_(0x18, 0x36) ++#define REG_SC_BK18_36_H _PK_H_(0x18, 0x36) ++#define REG_SC_BK18_37_L _PK_L_(0x18, 0x37) ++#define REG_SC_BK18_37_H _PK_H_(0x18, 0x37) ++#define REG_SC_BK18_38_L _PK_L_(0x18, 0x38) ++#define REG_SC_BK18_38_H _PK_H_(0x18, 0x38) ++#define REG_SC_BK18_39_L _PK_L_(0x18, 0x39) ++#define REG_SC_BK18_39_H _PK_H_(0x18, 0x39) ++#define REG_SC_BK18_3A_L _PK_L_(0x18, 0x3A) ++#define REG_SC_BK18_3A_H _PK_H_(0x18, 0x3A) ++#define REG_SC_BK18_3B_L _PK_L_(0x18, 0x3B) ++#define REG_SC_BK18_3B_H _PK_H_(0x18, 0x3B) ++#define REG_SC_BK18_3C_L _PK_L_(0x18, 0x3C) ++#define REG_SC_BK18_3C_H _PK_H_(0x18, 0x3C) ++#define REG_SC_BK18_3D_L _PK_L_(0x18, 0x3D) ++#define REG_SC_BK18_3D_H _PK_H_(0x18, 0x3D) ++#define REG_SC_BK18_3E_L _PK_L_(0x18, 0x3E) ++#define REG_SC_BK18_3E_H _PK_H_(0x18, 0x3E) ++#define REG_SC_BK18_3F_L _PK_L_(0x18, 0x3F) ++#define REG_SC_BK18_3F_H _PK_H_(0x18, 0x3F) ++#define REG_SC_BK18_40_L _PK_L_(0x18, 0x40) ++#define REG_SC_BK18_40_H _PK_H_(0x18, 0x40) ++#define REG_SC_BK18_41_L _PK_L_(0x18, 0x41) ++#define REG_SC_BK18_41_H _PK_H_(0x18, 0x41) ++#define REG_SC_BK18_42_L _PK_L_(0x18, 0x42) ++#define REG_SC_BK18_42_H _PK_H_(0x18, 0x42) ++#define REG_SC_BK18_43_L _PK_L_(0x18, 0x43) ++#define REG_SC_BK18_43_H _PK_H_(0x18, 0x43) ++#define REG_SC_BK18_44_L _PK_L_(0x18, 0x44) ++#define REG_SC_BK18_44_H _PK_H_(0x18, 0x44) ++#define REG_SC_BK18_45_L _PK_L_(0x18, 0x45) ++#define REG_SC_BK18_45_H _PK_H_(0x18, 0x45) ++#define REG_SC_BK18_46_L _PK_L_(0x18, 0x46) ++#define REG_SC_BK18_46_H _PK_H_(0x18, 0x46) ++#define REG_SC_BK18_47_L _PK_L_(0x18, 0x47) ++#define REG_SC_BK18_47_H _PK_H_(0x18, 0x47) ++#define REG_SC_BK18_48_L _PK_L_(0x18, 0x48) ++#define REG_SC_BK18_48_H _PK_H_(0x18, 0x48) ++#define REG_SC_BK18_49_L _PK_L_(0x18, 0x49) ++#define REG_SC_BK18_49_H _PK_H_(0x18, 0x49) ++#define REG_SC_BK18_4A_L _PK_L_(0x18, 0x4A) ++#define REG_SC_BK18_4A_H _PK_H_(0x18, 0x4A) ++#define REG_SC_BK18_4B_L _PK_L_(0x18, 0x4B) ++#define REG_SC_BK18_4B_H _PK_H_(0x18, 0x4B) ++#define REG_SC_BK18_4C_L _PK_L_(0x18, 0x4C) ++#define REG_SC_BK18_4C_H _PK_H_(0x18, 0x4C) ++#define REG_SC_BK18_4D_L _PK_L_(0x18, 0x4D) ++#define REG_SC_BK18_4D_H _PK_H_(0x18, 0x4D) ++#define REG_SC_BK18_4E_L _PK_L_(0x18, 0x4E) ++#define REG_SC_BK18_4E_H _PK_H_(0x18, 0x4E) ++#define REG_SC_BK18_4F_L _PK_L_(0x18, 0x4F) ++#define REG_SC_BK18_4F_H _PK_H_(0x18, 0x4F) ++#define REG_SC_BK18_50_L _PK_L_(0x18, 0x50) ++#define REG_SC_BK18_50_H _PK_H_(0x18, 0x50) ++#define REG_SC_BK18_51_L _PK_L_(0x18, 0x51) ++#define REG_SC_BK18_51_H _PK_H_(0x18, 0x51) ++#define REG_SC_BK18_52_L _PK_L_(0x18, 0x52) ++#define REG_SC_BK18_52_H _PK_H_(0x18, 0x52) ++#define REG_SC_BK18_53_L _PK_L_(0x18, 0x53) ++#define REG_SC_BK18_53_H _PK_H_(0x18, 0x53) ++#define REG_SC_BK18_54_L _PK_L_(0x18, 0x54) ++#define REG_SC_BK18_54_H _PK_H_(0x18, 0x54) ++#define REG_SC_BK18_55_L _PK_L_(0x18, 0x55) ++#define REG_SC_BK18_55_H _PK_H_(0x18, 0x55) ++#define REG_SC_BK18_56_L _PK_L_(0x18, 0x56) ++#define REG_SC_BK18_56_H _PK_H_(0x18, 0x56) ++#define REG_SC_BK18_57_L _PK_L_(0x18, 0x57) ++#define REG_SC_BK18_57_H _PK_H_(0x18, 0x57) ++#define REG_SC_BK18_58_L _PK_L_(0x18, 0x58) ++#define REG_SC_BK18_58_H _PK_H_(0x18, 0x58) ++#define REG_SC_BK18_59_L _PK_L_(0x18, 0x59) ++#define REG_SC_BK18_59_H _PK_H_(0x18, 0x59) ++#define REG_SC_BK18_5A_L _PK_L_(0x18, 0x5A) ++#define REG_SC_BK18_5A_H _PK_H_(0x18, 0x5A) ++#define REG_SC_BK18_5B_L _PK_L_(0x18, 0x5B) ++#define REG_SC_BK18_5B_H _PK_H_(0x18, 0x5B) ++#define REG_SC_BK18_5C_L _PK_L_(0x18, 0x5C) ++#define REG_SC_BK18_5C_H _PK_H_(0x18, 0x5C) ++#define REG_SC_BK18_5D_L _PK_L_(0x18, 0x5D) ++#define REG_SC_BK18_5D_H _PK_H_(0x18, 0x5D) ++#define REG_SC_BK18_5E_L _PK_L_(0x18, 0x5E) ++#define REG_SC_BK18_5E_H _PK_H_(0x18, 0x5E) ++#define REG_SC_BK18_5F_L _PK_L_(0x18, 0x5F) ++#define REG_SC_BK18_5F_H _PK_H_(0x18, 0x5F) ++#define REG_SC_BK18_60_L _PK_L_(0x18, 0x60) ++#define REG_SC_BK18_60_H _PK_H_(0x18, 0x60) ++#define REG_SC_BK18_61_L _PK_L_(0x18, 0x61) ++#define REG_SC_BK18_61_H _PK_H_(0x18, 0x61) ++#define REG_SC_BK18_62_L _PK_L_(0x18, 0x62) ++#define REG_SC_BK18_62_H _PK_H_(0x18, 0x62) ++#define REG_SC_BK18_63_L _PK_L_(0x18, 0x63) ++#define REG_SC_BK18_63_H _PK_H_(0x18, 0x63) ++#define REG_SC_BK18_64_L _PK_L_(0x18, 0x64) ++#define REG_SC_BK18_64_H _PK_H_(0x18, 0x64) ++#define REG_SC_BK18_65_L _PK_L_(0x18, 0x65) ++#define REG_SC_BK18_65_H _PK_H_(0x18, 0x65) ++#define REG_SC_BK18_66_L _PK_L_(0x18, 0x66) ++#define REG_SC_BK18_66_H _PK_H_(0x18, 0x66) ++#define REG_SC_BK18_67_L _PK_L_(0x18, 0x67) ++#define REG_SC_BK18_67_H _PK_H_(0x18, 0x67) ++#define REG_SC_BK18_68_L _PK_L_(0x18, 0x68) ++#define REG_SC_BK18_68_H _PK_H_(0x18, 0x68) ++#define REG_SC_BK18_69_L _PK_L_(0x18, 0x69) ++#define REG_SC_BK18_69_H _PK_H_(0x18, 0x69) ++#define REG_SC_BK18_6A_L _PK_L_(0x18, 0x6A) ++#define REG_SC_BK18_6A_H _PK_H_(0x18, 0x6A) ++#define REG_SC_BK18_6B_L _PK_L_(0x18, 0x6B) ++#define REG_SC_BK18_6B_H _PK_H_(0x18, 0x6B) ++#define REG_SC_BK18_6C_L _PK_L_(0x18, 0x6C) ++#define REG_SC_BK18_6C_H _PK_H_(0x18, 0x6C) ++#define REG_SC_BK18_6D_L _PK_L_(0x18, 0x6D) ++#define REG_SC_BK18_6D_H _PK_H_(0x18, 0x6D) ++#define REG_SC_BK18_6E_L _PK_L_(0x18, 0x6E) ++#define REG_SC_BK18_6E_H _PK_H_(0x18, 0x6E) ++#define REG_SC_BK18_6F_L _PK_L_(0x18, 0x6F) ++#define REG_SC_BK18_6F_H _PK_H_(0x18, 0x6F) ++#define REG_SC_BK18_70_L _PK_L_(0x18, 0x70) ++#define REG_SC_BK18_70_H _PK_H_(0x18, 0x70) ++#define REG_SC_BK18_71_L _PK_L_(0x18, 0x71) ++#define REG_SC_BK18_71_H _PK_H_(0x18, 0x71) ++#define REG_SC_BK18_72_L _PK_L_(0x18, 0x72) ++#define REG_SC_BK18_72_H _PK_H_(0x18, 0x72) ++#define REG_SC_BK18_73_L _PK_L_(0x18, 0x73) ++#define REG_SC_BK18_73_H _PK_H_(0x18, 0x73) ++#define REG_SC_BK18_74_L _PK_L_(0x18, 0x74) ++#define REG_SC_BK18_74_H _PK_H_(0x18, 0x74) ++#define REG_SC_BK18_75_L _PK_L_(0x18, 0x75) ++#define REG_SC_BK18_75_H _PK_H_(0x18, 0x75) ++#define REG_SC_BK18_76_L _PK_L_(0x18, 0x76) ++#define REG_SC_BK18_76_H _PK_H_(0x18, 0x76) ++#define REG_SC_BK18_77_L _PK_L_(0x18, 0x77) ++#define REG_SC_BK18_77_H _PK_H_(0x18, 0x77) ++#define REG_SC_BK18_78_L _PK_L_(0x18, 0x78) ++#define REG_SC_BK18_78_H _PK_H_(0x18, 0x78) ++#define REG_SC_BK18_79_L _PK_L_(0x18, 0x79) ++#define REG_SC_BK18_79_H _PK_H_(0x18, 0x79) ++#define REG_SC_BK18_7A_L _PK_L_(0x18, 0x7A) ++#define REG_SC_BK18_7A_H _PK_H_(0x18, 0x7A) ++#define REG_SC_BK18_7B_L _PK_L_(0x18, 0x7B) ++#define REG_SC_BK18_7B_H _PK_H_(0x18, 0x7B) ++#define REG_SC_BK18_7C_L _PK_L_(0x18, 0x7C) ++#define REG_SC_BK18_7C_H _PK_H_(0x18, 0x7C) ++#define REG_SC_BK18_7D_L _PK_L_(0x18, 0x7D) ++#define REG_SC_BK18_7D_H _PK_H_(0x18, 0x7D) ++#define REG_SC_BK18_7E_L _PK_L_(0x18, 0x7E) ++#define REG_SC_BK18_7E_H _PK_H_(0x18, 0x7E) ++#define REG_SC_BK18_7F_L _PK_L_(0x18, 0x7F) ++#define REG_SC_BK18_7F_H _PK_H_(0x18, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK19_00_L _PK_L_(0x19, 0x00) ++#define REG_SC_BK19_00_H _PK_H_(0x19, 0x00) ++#define REG_SC_BK19_01_L _PK_L_(0x19, 0x01) ++#define REG_SC_BK19_01_H _PK_H_(0x19, 0x01) ++#define REG_SC_BK19_02_L _PK_L_(0x19, 0x02) ++#define REG_SC_BK19_02_H _PK_H_(0x19, 0x02) ++#define REG_SC_BK19_03_L _PK_L_(0x19, 0x03) ++#define REG_SC_BK19_03_H _PK_H_(0x19, 0x03) ++#define REG_SC_BK19_04_L _PK_L_(0x19, 0x04) ++#define REG_SC_BK19_04_H _PK_H_(0x19, 0x04) ++#define REG_SC_BK19_05_L _PK_L_(0x19, 0x05) ++#define REG_SC_BK19_05_H _PK_H_(0x19, 0x05) ++#define REG_SC_BK19_06_L _PK_L_(0x19, 0x06) ++#define REG_SC_BK19_06_H _PK_H_(0x19, 0x06) ++#define REG_SC_BK19_07_L _PK_L_(0x19, 0x07) ++#define REG_SC_BK19_07_H _PK_H_(0x19, 0x07) ++#define REG_SC_BK19_08_L _PK_L_(0x19, 0x08) ++#define REG_SC_BK19_08_H _PK_H_(0x19, 0x08) ++#define REG_SC_BK19_09_L _PK_L_(0x19, 0x09) ++#define REG_SC_BK19_09_H _PK_H_(0x19, 0x09) ++#define REG_SC_BK19_0A_L _PK_L_(0x19, 0x0A) ++#define REG_SC_BK19_0A_H _PK_H_(0x19, 0x0A) ++#define REG_SC_BK19_0B_L _PK_L_(0x19, 0x0B) ++#define REG_SC_BK19_0B_H _PK_H_(0x19, 0x0B) ++#define REG_SC_BK19_0C_L _PK_L_(0x19, 0x0C) ++#define REG_SC_BK19_0C_H _PK_H_(0x19, 0x0C) ++#define REG_SC_BK19_0D_L _PK_L_(0x19, 0x0D) ++#define REG_SC_BK19_0D_H _PK_H_(0x19, 0x0D) ++#define REG_SC_BK19_0E_L _PK_L_(0x19, 0x0E) ++#define REG_SC_BK19_0E_H _PK_H_(0x19, 0x0E) ++#define REG_SC_BK19_0F_L _PK_L_(0x19, 0x0F) ++#define REG_SC_BK19_0F_H _PK_H_(0x19, 0x0F) ++#define REG_SC_BK19_10_L _PK_L_(0x19, 0x10) ++#define REG_SC_BK19_10_H _PK_H_(0x19, 0x10) ++#define REG_SC_BK19_11_L _PK_L_(0x19, 0x11) ++#define REG_SC_BK19_11_H _PK_H_(0x19, 0x11) ++#define REG_SC_BK19_12_L _PK_L_(0x19, 0x12) ++#define REG_SC_BK19_12_H _PK_H_(0x19, 0x12) ++#define REG_SC_BK19_13_L _PK_L_(0x19, 0x13) ++#define REG_SC_BK19_13_H _PK_H_(0x19, 0x13) ++#define REG_SC_BK19_14_L _PK_L_(0x19, 0x14) ++#define REG_SC_BK19_14_H _PK_H_(0x19, 0x14) ++#define REG_SC_BK19_15_L _PK_L_(0x19, 0x15) ++#define REG_SC_BK19_15_H _PK_H_(0x19, 0x15) ++#define REG_SC_BK19_16_L _PK_L_(0x19, 0x16) ++#define REG_SC_BK19_16_H _PK_H_(0x19, 0x16) ++#define REG_SC_BK19_17_L _PK_L_(0x19, 0x17) ++#define REG_SC_BK19_17_H _PK_H_(0x19, 0x17) ++#define REG_SC_BK19_18_L _PK_L_(0x19, 0x18) ++#define REG_SC_BK19_18_H _PK_H_(0x19, 0x18) ++#define REG_SC_BK19_19_L _PK_L_(0x19, 0x19) ++#define REG_SC_BK19_19_H _PK_H_(0x19, 0x19) ++#define REG_SC_BK19_1A_L _PK_L_(0x19, 0x1A) ++#define REG_SC_BK19_1A_H _PK_H_(0x19, 0x1A) ++#define REG_SC_BK19_1B_L _PK_L_(0x19, 0x1B) ++#define REG_SC_BK19_1B_H _PK_H_(0x19, 0x1B) ++#define REG_SC_BK19_1C_L _PK_L_(0x19, 0x1C) ++#define REG_SC_BK19_1C_H _PK_H_(0x19, 0x1C) ++#define REG_SC_BK19_1D_L _PK_L_(0x19, 0x1D) ++#define REG_SC_BK19_1D_H _PK_H_(0x19, 0x1D) ++#define REG_SC_BK19_1E_L _PK_L_(0x19, 0x1E) ++#define REG_SC_BK19_1E_H _PK_H_(0x19, 0x1E) ++#define REG_SC_BK19_1F_L _PK_L_(0x19, 0x1F) ++#define REG_SC_BK19_1F_H _PK_H_(0x19, 0x1F) ++#define REG_SC_BK19_20_L _PK_L_(0x19, 0x20) ++#define REG_SC_BK19_20_H _PK_H_(0x19, 0x20) ++#define REG_SC_BK19_21_L _PK_L_(0x19, 0x21) ++#define REG_SC_BK19_21_H _PK_H_(0x19, 0x21) ++#define REG_SC_BK19_22_L _PK_L_(0x19, 0x22) ++#define REG_SC_BK19_22_H _PK_H_(0x19, 0x22) ++#define REG_SC_BK19_23_L _PK_L_(0x19, 0x23) ++#define REG_SC_BK19_23_H _PK_H_(0x19, 0x23) ++#define REG_SC_BK19_24_L _PK_L_(0x19, 0x24) ++#define REG_SC_BK19_24_H _PK_H_(0x19, 0x24) ++#define REG_SC_BK19_25_L _PK_L_(0x19, 0x25) ++#define REG_SC_BK19_25_H _PK_H_(0x19, 0x25) ++#define REG_SC_BK19_26_L _PK_L_(0x19, 0x26) ++#define REG_SC_BK19_26_H _PK_H_(0x19, 0x26) ++#define REG_SC_BK19_27_L _PK_L_(0x19, 0x27) ++#define REG_SC_BK19_27_H _PK_H_(0x19, 0x27) ++#define REG_SC_BK19_28_L _PK_L_(0x19, 0x28) ++#define REG_SC_BK19_28_H _PK_H_(0x19, 0x28) ++#define REG_SC_BK19_29_L _PK_L_(0x19, 0x29) ++#define REG_SC_BK19_29_H _PK_H_(0x19, 0x29) ++#define REG_SC_BK19_2A_L _PK_L_(0x19, 0x2A) ++#define REG_SC_BK19_2A_H _PK_H_(0x19, 0x2A) ++#define REG_SC_BK19_2B_L _PK_L_(0x19, 0x2B) ++#define REG_SC_BK19_2B_H _PK_H_(0x19, 0x2B) ++#define REG_SC_BK19_2C_L _PK_L_(0x19, 0x2C) ++#define REG_SC_BK19_2C_H _PK_H_(0x19, 0x2C) ++#define REG_SC_BK19_2D_L _PK_L_(0x19, 0x2D) ++#define REG_SC_BK19_2D_H _PK_H_(0x19, 0x2D) ++#define REG_SC_BK19_2E_L _PK_L_(0x19, 0x2E) ++#define REG_SC_BK19_2E_H _PK_H_(0x19, 0x2E) ++#define REG_SC_BK19_2F_L _PK_L_(0x19, 0x2F) ++#define REG_SC_BK19_2F_H _PK_H_(0x19, 0x2F) ++#define REG_SC_BK19_30_L _PK_L_(0x19, 0x30) ++#define REG_SC_BK19_30_H _PK_H_(0x19, 0x30) ++#define REG_SC_BK19_31_L _PK_L_(0x19, 0x31) ++#define REG_SC_BK19_31_H _PK_H_(0x19, 0x31) ++#define REG_SC_BK19_32_L _PK_L_(0x19, 0x32) ++#define REG_SC_BK19_32_H _PK_H_(0x19, 0x32) ++#define REG_SC_BK19_33_L _PK_L_(0x19, 0x33) ++#define REG_SC_BK19_33_H _PK_H_(0x19, 0x33) ++#define REG_SC_BK19_34_L _PK_L_(0x19, 0x34) ++#define REG_SC_BK19_34_H _PK_H_(0x19, 0x34) ++#define REG_SC_BK19_35_L _PK_L_(0x19, 0x35) ++#define REG_SC_BK19_35_H _PK_H_(0x19, 0x35) ++#define REG_SC_BK19_36_L _PK_L_(0x19, 0x36) ++#define REG_SC_BK19_36_H _PK_H_(0x19, 0x36) ++#define REG_SC_BK19_37_L _PK_L_(0x19, 0x37) ++#define REG_SC_BK19_37_H _PK_H_(0x19, 0x37) ++#define REG_SC_BK19_38_L _PK_L_(0x19, 0x38) ++#define REG_SC_BK19_38_H _PK_H_(0x19, 0x38) ++#define REG_SC_BK19_39_L _PK_L_(0x19, 0x39) ++#define REG_SC_BK19_39_H _PK_H_(0x19, 0x39) ++#define REG_SC_BK19_3A_L _PK_L_(0x19, 0x3A) ++#define REG_SC_BK19_3A_H _PK_H_(0x19, 0x3A) ++#define REG_SC_BK19_3B_L _PK_L_(0x19, 0x3B) ++#define REG_SC_BK19_3B_H _PK_H_(0x19, 0x3B) ++#define REG_SC_BK19_3C_L _PK_L_(0x19, 0x3C) ++#define REG_SC_BK19_3C_H _PK_H_(0x19, 0x3C) ++#define REG_SC_BK19_3D_L _PK_L_(0x19, 0x3D) ++#define REG_SC_BK19_3D_H _PK_H_(0x19, 0x3D) ++#define REG_SC_BK19_3E_L _PK_L_(0x19, 0x3E) ++#define REG_SC_BK19_3E_H _PK_H_(0x19, 0x3E) ++#define REG_SC_BK19_3F_L _PK_L_(0x19, 0x3F) ++#define REG_SC_BK19_3F_H _PK_H_(0x19, 0x3F) ++#define REG_SC_BK19_40_L _PK_L_(0x19, 0x40) ++#define REG_SC_BK19_40_H _PK_H_(0x19, 0x40) ++#define REG_SC_BK19_41_L _PK_L_(0x19, 0x41) ++#define REG_SC_BK19_41_H _PK_H_(0x19, 0x41) ++#define REG_SC_BK19_42_L _PK_L_(0x19, 0x42) ++#define REG_SC_BK19_42_H _PK_H_(0x19, 0x42) ++#define REG_SC_BK19_43_L _PK_L_(0x19, 0x43) ++#define REG_SC_BK19_43_H _PK_H_(0x19, 0x43) ++#define REG_SC_BK19_44_L _PK_L_(0x19, 0x44) ++#define REG_SC_BK19_44_H _PK_H_(0x19, 0x44) ++#define REG_SC_BK19_45_L _PK_L_(0x19, 0x45) ++#define REG_SC_BK19_45_H _PK_H_(0x19, 0x45) ++#define REG_SC_BK19_46_L _PK_L_(0x19, 0x46) ++#define REG_SC_BK19_46_H _PK_H_(0x19, 0x46) ++#define REG_SC_BK19_47_L _PK_L_(0x19, 0x47) ++#define REG_SC_BK19_47_H _PK_H_(0x19, 0x47) ++#define REG_SC_BK19_48_L _PK_L_(0x19, 0x48) ++#define REG_SC_BK19_48_H _PK_H_(0x19, 0x48) ++#define REG_SC_BK19_49_L _PK_L_(0x19, 0x49) ++#define REG_SC_BK19_49_H _PK_H_(0x19, 0x49) ++#define REG_SC_BK19_4A_L _PK_L_(0x19, 0x4A) ++#define REG_SC_BK19_4A_H _PK_H_(0x19, 0x4A) ++#define REG_SC_BK19_4B_L _PK_L_(0x19, 0x4B) ++#define REG_SC_BK19_4B_H _PK_H_(0x19, 0x4B) ++#define REG_SC_BK19_4C_L _PK_L_(0x19, 0x4C) ++#define REG_SC_BK19_4C_H _PK_H_(0x19, 0x4C) ++#define REG_SC_BK19_4D_L _PK_L_(0x19, 0x4D) ++#define REG_SC_BK19_4D_H _PK_H_(0x19, 0x4D) ++#define REG_SC_BK19_4E_L _PK_L_(0x19, 0x4E) ++#define REG_SC_BK19_4E_H _PK_H_(0x19, 0x4E) ++#define REG_SC_BK19_4F_L _PK_L_(0x19, 0x4F) ++#define REG_SC_BK19_4F_H _PK_H_(0x19, 0x4F) ++#define REG_SC_BK19_50_L _PK_L_(0x19, 0x50) ++#define REG_SC_BK19_50_H _PK_H_(0x19, 0x50) ++#define REG_SC_BK19_51_L _PK_L_(0x19, 0x51) ++#define REG_SC_BK19_51_H _PK_H_(0x19, 0x51) ++#define REG_SC_BK19_52_L _PK_L_(0x19, 0x52) ++#define REG_SC_BK19_52_H _PK_H_(0x19, 0x52) ++#define REG_SC_BK19_53_L _PK_L_(0x19, 0x53) ++#define REG_SC_BK19_53_H _PK_H_(0x19, 0x53) ++#define REG_SC_BK19_54_L _PK_L_(0x19, 0x54) ++#define REG_SC_BK19_54_H _PK_H_(0x19, 0x54) ++#define REG_SC_BK19_55_L _PK_L_(0x19, 0x55) ++#define REG_SC_BK19_55_H _PK_H_(0x19, 0x55) ++#define REG_SC_BK19_56_L _PK_L_(0x19, 0x56) ++#define REG_SC_BK19_56_H _PK_H_(0x19, 0x56) ++#define REG_SC_BK19_57_L _PK_L_(0x19, 0x57) ++#define REG_SC_BK19_57_H _PK_H_(0x19, 0x57) ++#define REG_SC_BK19_58_L _PK_L_(0x19, 0x58) ++#define REG_SC_BK19_58_H _PK_H_(0x19, 0x58) ++#define REG_SC_BK19_59_L _PK_L_(0x19, 0x59) ++#define REG_SC_BK19_59_H _PK_H_(0x19, 0x59) ++#define REG_SC_BK19_5A_L _PK_L_(0x19, 0x5A) ++#define REG_SC_BK19_5A_H _PK_H_(0x19, 0x5A) ++#define REG_SC_BK19_5B_L _PK_L_(0x19, 0x5B) ++#define REG_SC_BK19_5B_H _PK_H_(0x19, 0x5B) ++#define REG_SC_BK19_5C_L _PK_L_(0x19, 0x5C) ++#define REG_SC_BK19_5C_H _PK_H_(0x19, 0x5C) ++#define REG_SC_BK19_5D_L _PK_L_(0x19, 0x5D) ++#define REG_SC_BK19_5D_H _PK_H_(0x19, 0x5D) ++#define REG_SC_BK19_5E_L _PK_L_(0x19, 0x5E) ++#define REG_SC_BK19_5E_H _PK_H_(0x19, 0x5E) ++#define REG_SC_BK19_5F_L _PK_L_(0x19, 0x5F) ++#define REG_SC_BK19_5F_H _PK_H_(0x19, 0x5F) ++#define REG_SC_BK19_60_L _PK_L_(0x19, 0x60) ++#define REG_SC_BK19_60_H _PK_H_(0x19, 0x60) ++#define REG_SC_BK19_61_L _PK_L_(0x19, 0x61) ++#define REG_SC_BK19_61_H _PK_H_(0x19, 0x61) ++#define REG_SC_BK19_62_L _PK_L_(0x19, 0x62) ++#define REG_SC_BK19_62_H _PK_H_(0x19, 0x62) ++#define REG_SC_BK19_63_L _PK_L_(0x19, 0x63) ++#define REG_SC_BK19_63_H _PK_H_(0x19, 0x63) ++#define REG_SC_BK19_64_L _PK_L_(0x19, 0x64) ++#define REG_SC_BK19_64_H _PK_H_(0x19, 0x64) ++#define REG_SC_BK19_65_L _PK_L_(0x19, 0x65) ++#define REG_SC_BK19_65_H _PK_H_(0x19, 0x65) ++#define REG_SC_BK19_66_L _PK_L_(0x19, 0x66) ++#define REG_SC_BK19_66_H _PK_H_(0x19, 0x66) ++#define REG_SC_BK19_67_L _PK_L_(0x19, 0x67) ++#define REG_SC_BK19_67_H _PK_H_(0x19, 0x67) ++#define REG_SC_BK19_68_L _PK_L_(0x19, 0x68) ++#define REG_SC_BK19_68_H _PK_H_(0x19, 0x68) ++#define REG_SC_BK19_69_L _PK_L_(0x19, 0x69) ++#define REG_SC_BK19_69_H _PK_H_(0x19, 0x69) ++#define REG_SC_BK19_6A_L _PK_L_(0x19, 0x6A) ++#define REG_SC_BK19_6A_H _PK_H_(0x19, 0x6A) ++#define REG_SC_BK19_6B_L _PK_L_(0x19, 0x6B) ++#define REG_SC_BK19_6B_H _PK_H_(0x19, 0x6B) ++#define REG_SC_BK19_6C_L _PK_L_(0x19, 0x6C) ++#define REG_SC_BK19_6C_H _PK_H_(0x19, 0x6C) ++#define REG_SC_BK19_6D_L _PK_L_(0x19, 0x6D) ++#define REG_SC_BK19_6D_H _PK_H_(0x19, 0x6D) ++#define REG_SC_BK19_6E_L _PK_L_(0x19, 0x6E) ++#define REG_SC_BK19_6E_H _PK_H_(0x19, 0x6E) ++#define REG_SC_BK19_6F_L _PK_L_(0x19, 0x6F) ++#define REG_SC_BK19_6F_H _PK_H_(0x19, 0x6F) ++#define REG_SC_BK19_70_L _PK_L_(0x19, 0x70) ++#define REG_SC_BK19_70_H _PK_H_(0x19, 0x70) ++#define REG_SC_BK19_71_L _PK_L_(0x19, 0x71) ++#define REG_SC_BK19_71_H _PK_H_(0x19, 0x71) ++#define REG_SC_BK19_72_L _PK_L_(0x19, 0x72) ++#define REG_SC_BK19_72_H _PK_H_(0x19, 0x72) ++#define REG_SC_BK19_73_L _PK_L_(0x19, 0x73) ++#define REG_SC_BK19_73_H _PK_H_(0x19, 0x73) ++#define REG_SC_BK19_74_L _PK_L_(0x19, 0x74) ++#define REG_SC_BK19_74_H _PK_H_(0x19, 0x74) ++#define REG_SC_BK19_75_L _PK_L_(0x19, 0x75) ++#define REG_SC_BK19_75_H _PK_H_(0x19, 0x75) ++#define REG_SC_BK19_76_L _PK_L_(0x19, 0x76) ++#define REG_SC_BK19_76_H _PK_H_(0x19, 0x76) ++#define REG_SC_BK19_77_L _PK_L_(0x19, 0x77) ++#define REG_SC_BK19_77_H _PK_H_(0x19, 0x77) ++#define REG_SC_BK19_78_L _PK_L_(0x19, 0x78) ++#define REG_SC_BK19_78_H _PK_H_(0x19, 0x78) ++#define REG_SC_BK19_79_L _PK_L_(0x19, 0x79) ++#define REG_SC_BK19_79_H _PK_H_(0x19, 0x79) ++#define REG_SC_BK19_7A_L _PK_L_(0x19, 0x7A) ++#define REG_SC_BK19_7A_H _PK_H_(0x19, 0x7A) ++#define REG_SC_BK19_7B_L _PK_L_(0x19, 0x7B) ++#define REG_SC_BK19_7B_H _PK_H_(0x19, 0x7B) ++#define REG_SC_BK19_7C_L _PK_L_(0x19, 0x7C) ++#define REG_SC_BK19_7C_H _PK_H_(0x19, 0x7C) ++#define REG_SC_BK19_7D_L _PK_L_(0x19, 0x7D) ++#define REG_SC_BK19_7D_H _PK_H_(0x19, 0x7D) ++#define REG_SC_BK19_7E_L _PK_L_(0x19, 0x7E) ++#define REG_SC_BK19_7E_H _PK_H_(0x19, 0x7E) ++#define REG_SC_BK19_7F_L _PK_L_(0x19, 0x7F) ++#define REG_SC_BK19_7F_H _PK_H_(0x19, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1A_00_L _PK_L_(0x1A, 0x00) ++#define REG_SC_BK1A_00_H _PK_H_(0x1A, 0x00) ++#define REG_SC_BK1A_01_L _PK_L_(0x1A, 0x01) ++#define REG_SC_BK1A_01_H _PK_H_(0x1A, 0x01) ++#define REG_SC_BK1A_02_L _PK_L_(0x1A, 0x02) ++#define REG_SC_BK1A_02_H _PK_H_(0x1A, 0x02) ++#define REG_SC_BK1A_03_L _PK_L_(0x1A, 0x03) ++#define REG_SC_BK1A_03_H _PK_H_(0x1A, 0x03) ++#define REG_SC_BK1A_04_L _PK_L_(0x1A, 0x04) ++#define REG_SC_BK1A_04_H _PK_H_(0x1A, 0x04) ++#define REG_SC_BK1A_05_L _PK_L_(0x1A, 0x05) ++#define REG_SC_BK1A_05_H _PK_H_(0x1A, 0x05) ++#define REG_SC_BK1A_06_L _PK_L_(0x1A, 0x06) ++#define REG_SC_BK1A_06_H _PK_H_(0x1A, 0x06) ++#define REG_SC_BK1A_07_L _PK_L_(0x1A, 0x07) ++#define REG_SC_BK1A_07_H _PK_H_(0x1A, 0x07) ++#define REG_SC_BK1A_08_L _PK_L_(0x1A, 0x08) ++#define REG_SC_BK1A_08_H _PK_H_(0x1A, 0x08) ++#define REG_SC_BK1A_09_L _PK_L_(0x1A, 0x09) ++#define REG_SC_BK1A_09_H _PK_H_(0x1A, 0x09) ++#define REG_SC_BK1A_0A_L _PK_L_(0x1A, 0x0A) ++#define REG_SC_BK1A_0A_H _PK_H_(0x1A, 0x0A) ++#define REG_SC_BK1A_0B_L _PK_L_(0x1A, 0x0B) ++#define REG_SC_BK1A_0B_H _PK_H_(0x1A, 0x0B) ++#define REG_SC_BK1A_0C_L _PK_L_(0x1A, 0x0C) ++#define REG_SC_BK1A_0C_H _PK_H_(0x1A, 0x0C) ++#define REG_SC_BK1A_0D_L _PK_L_(0x1A, 0x0D) ++#define REG_SC_BK1A_0D_H _PK_H_(0x1A, 0x0D) ++#define REG_SC_BK1A_0E_L _PK_L_(0x1A, 0x0E) ++#define REG_SC_BK1A_0E_H _PK_H_(0x1A, 0x0E) ++#define REG_SC_BK1A_0F_L _PK_L_(0x1A, 0x0F) ++#define REG_SC_BK1A_0F_H _PK_H_(0x1A, 0x0F) ++#define REG_SC_BK1A_10_L _PK_L_(0x1A, 0x10) ++#define REG_SC_BK1A_10_H _PK_H_(0x1A, 0x10) ++#define REG_SC_BK1A_11_L _PK_L_(0x1A, 0x11) ++#define REG_SC_BK1A_11_H _PK_H_(0x1A, 0x11) ++#define REG_SC_BK1A_12_L _PK_L_(0x1A, 0x12) ++#define REG_SC_BK1A_12_H _PK_H_(0x1A, 0x12) ++#define REG_SC_BK1A_13_L _PK_L_(0x1A, 0x13) ++#define REG_SC_BK1A_13_H _PK_H_(0x1A, 0x13) ++#define REG_SC_BK1A_14_L _PK_L_(0x1A, 0x14) ++#define REG_SC_BK1A_14_H _PK_H_(0x1A, 0x14) ++#define REG_SC_BK1A_15_L _PK_L_(0x1A, 0x15) ++#define REG_SC_BK1A_15_H _PK_H_(0x1A, 0x15) ++#define REG_SC_BK1A_16_L _PK_L_(0x1A, 0x16) ++#define REG_SC_BK1A_16_H _PK_H_(0x1A, 0x16) ++#define REG_SC_BK1A_17_L _PK_L_(0x1A, 0x17) ++#define REG_SC_BK1A_17_H _PK_H_(0x1A, 0x17) ++#define REG_SC_BK1A_18_L _PK_L_(0x1A, 0x18) ++#define REG_SC_BK1A_18_H _PK_H_(0x1A, 0x18) ++#define REG_SC_BK1A_19_L _PK_L_(0x1A, 0x19) ++#define REG_SC_BK1A_19_H _PK_H_(0x1A, 0x19) ++#define REG_SC_BK1A_1A_L _PK_L_(0x1A, 0x1A) ++#define REG_SC_BK1A_1A_H _PK_H_(0x1A, 0x1A) ++#define REG_SC_BK1A_1B_L _PK_L_(0x1A, 0x1B) ++#define REG_SC_BK1A_1B_H _PK_H_(0x1A, 0x1B) ++#define REG_SC_BK1A_1C_L _PK_L_(0x1A, 0x1C) ++#define REG_SC_BK1A_1C_H _PK_H_(0x1A, 0x1C) ++#define REG_SC_BK1A_1D_L _PK_L_(0x1A, 0x1D) ++#define REG_SC_BK1A_1D_H _PK_H_(0x1A, 0x1D) ++#define REG_SC_BK1A_1E_L _PK_L_(0x1A, 0x1E) ++#define REG_SC_BK1A_1E_H _PK_H_(0x1A, 0x1E) ++#define REG_SC_BK1A_1F_L _PK_L_(0x1A, 0x1F) ++#define REG_SC_BK1A_1F_H _PK_H_(0x1A, 0x1F) ++#define REG_SC_BK1A_20_L _PK_L_(0x1A, 0x20) ++#define REG_SC_BK1A_20_H _PK_H_(0x1A, 0x20) ++#define REG_SC_BK1A_21_L _PK_L_(0x1A, 0x21) ++#define REG_SC_BK1A_21_H _PK_H_(0x1A, 0x21) ++#define REG_SC_BK1A_22_L _PK_L_(0x1A, 0x22) ++#define REG_SC_BK1A_22_H _PK_H_(0x1A, 0x22) ++#define REG_SC_BK1A_23_L _PK_L_(0x1A, 0x23) ++#define REG_SC_BK1A_23_H _PK_H_(0x1A, 0x23) ++#define REG_SC_BK1A_24_L _PK_L_(0x1A, 0x24) ++#define REG_SC_BK1A_24_H _PK_H_(0x1A, 0x24) ++#define REG_SC_BK1A_25_L _PK_L_(0x1A, 0x25) ++#define REG_SC_BK1A_25_H _PK_H_(0x1A, 0x25) ++#define REG_SC_BK1A_26_L _PK_L_(0x1A, 0x26) ++#define REG_SC_BK1A_26_H _PK_H_(0x1A, 0x26) ++#define REG_SC_BK1A_27_L _PK_L_(0x1A, 0x27) ++#define REG_SC_BK1A_27_H _PK_H_(0x1A, 0x27) ++#define REG_SC_BK1A_28_L _PK_L_(0x1A, 0x28) ++#define REG_SC_BK1A_28_H _PK_H_(0x1A, 0x28) ++#define REG_SC_BK1A_29_L _PK_L_(0x1A, 0x29) ++#define REG_SC_BK1A_29_H _PK_H_(0x1A, 0x29) ++#define REG_SC_BK1A_2A_L _PK_L_(0x1A, 0x2A) ++#define REG_SC_BK1A_2A_H _PK_H_(0x1A, 0x2A) ++#define REG_SC_BK1A_2B_L _PK_L_(0x1A, 0x2B) ++#define REG_SC_BK1A_2B_H _PK_H_(0x1A, 0x2B) ++#define REG_SC_BK1A_2C_L _PK_L_(0x1A, 0x2C) ++#define REG_SC_BK1A_2C_H _PK_H_(0x1A, 0x2C) ++#define REG_SC_BK1A_2D_L _PK_L_(0x1A, 0x2D) ++#define REG_SC_BK1A_2D_H _PK_H_(0x1A, 0x2D) ++#define REG_SC_BK1A_2E_L _PK_L_(0x1A, 0x2E) ++#define REG_SC_BK1A_2E_H _PK_H_(0x1A, 0x2E) ++#define REG_SC_BK1A_2F_L _PK_L_(0x1A, 0x2F) ++#define REG_SC_BK1A_2F_H _PK_H_(0x1A, 0x2F) ++#define REG_SC_BK1A_30_L _PK_L_(0x1A, 0x30) ++#define REG_SC_BK1A_30_H _PK_H_(0x1A, 0x30) ++#define REG_SC_BK1A_31_L _PK_L_(0x1A, 0x31) ++#define REG_SC_BK1A_31_H _PK_H_(0x1A, 0x31) ++#define REG_SC_BK1A_32_L _PK_L_(0x1A, 0x32) ++#define REG_SC_BK1A_32_H _PK_H_(0x1A, 0x32) ++#define REG_SC_BK1A_33_L _PK_L_(0x1A, 0x33) ++#define REG_SC_BK1A_33_H _PK_H_(0x1A, 0x33) ++#define REG_SC_BK1A_34_L _PK_L_(0x1A, 0x34) ++#define REG_SC_BK1A_34_H _PK_H_(0x1A, 0x34) ++#define REG_SC_BK1A_35_L _PK_L_(0x1A, 0x35) ++#define REG_SC_BK1A_35_H _PK_H_(0x1A, 0x35) ++#define REG_SC_BK1A_36_L _PK_L_(0x1A, 0x36) ++#define REG_SC_BK1A_36_H _PK_H_(0x1A, 0x36) ++#define REG_SC_BK1A_37_L _PK_L_(0x1A, 0x37) ++#define REG_SC_BK1A_37_H _PK_H_(0x1A, 0x37) ++#define REG_SC_BK1A_38_L _PK_L_(0x1A, 0x38) ++#define REG_SC_BK1A_38_H _PK_H_(0x1A, 0x38) ++#define REG_SC_BK1A_39_L _PK_L_(0x1A, 0x39) ++#define REG_SC_BK1A_39_H _PK_H_(0x1A, 0x39) ++#define REG_SC_BK1A_3A_L _PK_L_(0x1A, 0x3A) ++#define REG_SC_BK1A_3A_H _PK_H_(0x1A, 0x3A) ++#define REG_SC_BK1A_3B_L _PK_L_(0x1A, 0x3B) ++#define REG_SC_BK1A_3B_H _PK_H_(0x1A, 0x3B) ++#define REG_SC_BK1A_3C_L _PK_L_(0x1A, 0x3C) ++#define REG_SC_BK1A_3C_H _PK_H_(0x1A, 0x3C) ++#define REG_SC_BK1A_3D_L _PK_L_(0x1A, 0x3D) ++#define REG_SC_BK1A_3D_H _PK_H_(0x1A, 0x3D) ++#define REG_SC_BK1A_3E_L _PK_L_(0x1A, 0x3E) ++#define REG_SC_BK1A_3E_H _PK_H_(0x1A, 0x3E) ++#define REG_SC_BK1A_3F_L _PK_L_(0x1A, 0x3F) ++#define REG_SC_BK1A_3F_H _PK_H_(0x1A, 0x3F) ++#define REG_SC_BK1A_40_L _PK_L_(0x1A, 0x40) ++#define REG_SC_BK1A_40_H _PK_H_(0x1A, 0x40) ++#define REG_SC_BK1A_41_L _PK_L_(0x1A, 0x41) ++#define REG_SC_BK1A_41_H _PK_H_(0x1A, 0x41) ++#define REG_SC_BK1A_42_L _PK_L_(0x1A, 0x42) ++#define REG_SC_BK1A_42_H _PK_H_(0x1A, 0x42) ++#define REG_SC_BK1A_43_L _PK_L_(0x1A, 0x43) ++#define REG_SC_BK1A_43_H _PK_H_(0x1A, 0x43) ++#define REG_SC_BK1A_44_L _PK_L_(0x1A, 0x44) ++#define REG_SC_BK1A_44_H _PK_H_(0x1A, 0x44) ++#define REG_SC_BK1A_45_L _PK_L_(0x1A, 0x45) ++#define REG_SC_BK1A_45_H _PK_H_(0x1A, 0x45) ++#define REG_SC_BK1A_46_L _PK_L_(0x1A, 0x46) ++#define REG_SC_BK1A_46_H _PK_H_(0x1A, 0x46) ++#define REG_SC_BK1A_47_L _PK_L_(0x1A, 0x47) ++#define REG_SC_BK1A_47_H _PK_H_(0x1A, 0x47) ++#define REG_SC_BK1A_48_L _PK_L_(0x1A, 0x48) ++#define REG_SC_BK1A_48_H _PK_H_(0x1A, 0x48) ++#define REG_SC_BK1A_49_L _PK_L_(0x1A, 0x49) ++#define REG_SC_BK1A_49_H _PK_H_(0x1A, 0x49) ++#define REG_SC_BK1A_4A_L _PK_L_(0x1A, 0x4A) ++#define REG_SC_BK1A_4A_H _PK_H_(0x1A, 0x4A) ++#define REG_SC_BK1A_4B_L _PK_L_(0x1A, 0x4B) ++#define REG_SC_BK1A_4B_H _PK_H_(0x1A, 0x4B) ++#define REG_SC_BK1A_4C_L _PK_L_(0x1A, 0x4C) ++#define REG_SC_BK1A_4C_H _PK_H_(0x1A, 0x4C) ++#define REG_SC_BK1A_4D_L _PK_L_(0x1A, 0x4D) ++#define REG_SC_BK1A_4D_H _PK_H_(0x1A, 0x4D) ++#define REG_SC_BK1A_4E_L _PK_L_(0x1A, 0x4E) ++#define REG_SC_BK1A_4E_H _PK_H_(0x1A, 0x4E) ++#define REG_SC_BK1A_4F_L _PK_L_(0x1A, 0x4F) ++#define REG_SC_BK1A_4F_H _PK_H_(0x1A, 0x4F) ++#define REG_SC_BK1A_50_L _PK_L_(0x1A, 0x50) ++#define REG_SC_BK1A_50_H _PK_H_(0x1A, 0x50) ++#define REG_SC_BK1A_51_L _PK_L_(0x1A, 0x51) ++#define REG_SC_BK1A_51_H _PK_H_(0x1A, 0x51) ++#define REG_SC_BK1A_52_L _PK_L_(0x1A, 0x52) ++#define REG_SC_BK1A_52_H _PK_H_(0x1A, 0x52) ++#define REG_SC_BK1A_53_L _PK_L_(0x1A, 0x53) ++#define REG_SC_BK1A_53_H _PK_H_(0x1A, 0x53) ++#define REG_SC_BK1A_54_L _PK_L_(0x1A, 0x54) ++#define REG_SC_BK1A_54_H _PK_H_(0x1A, 0x54) ++#define REG_SC_BK1A_55_L _PK_L_(0x1A, 0x55) ++#define REG_SC_BK1A_55_H _PK_H_(0x1A, 0x55) ++#define REG_SC_BK1A_56_L _PK_L_(0x1A, 0x56) ++#define REG_SC_BK1A_56_H _PK_H_(0x1A, 0x56) ++#define REG_SC_BK1A_57_L _PK_L_(0x1A, 0x57) ++#define REG_SC_BK1A_57_H _PK_H_(0x1A, 0x57) ++#define REG_SC_BK1A_58_L _PK_L_(0x1A, 0x58) ++#define REG_SC_BK1A_58_H _PK_H_(0x1A, 0x58) ++#define REG_SC_BK1A_59_L _PK_L_(0x1A, 0x59) ++#define REG_SC_BK1A_59_H _PK_H_(0x1A, 0x59) ++#define REG_SC_BK1A_5A_L _PK_L_(0x1A, 0x5A) ++#define REG_SC_BK1A_5A_H _PK_H_(0x1A, 0x5A) ++#define REG_SC_BK1A_5B_L _PK_L_(0x1A, 0x5B) ++#define REG_SC_BK1A_5B_H _PK_H_(0x1A, 0x5B) ++#define REG_SC_BK1A_5C_L _PK_L_(0x1A, 0x5C) ++#define REG_SC_BK1A_5C_H _PK_H_(0x1A, 0x5C) ++#define REG_SC_BK1A_5D_L _PK_L_(0x1A, 0x5D) ++#define REG_SC_BK1A_5D_H _PK_H_(0x1A, 0x5D) ++#define REG_SC_BK1A_5E_L _PK_L_(0x1A, 0x5E) ++#define REG_SC_BK1A_5E_H _PK_H_(0x1A, 0x5E) ++#define REG_SC_BK1A_5F_L _PK_L_(0x1A, 0x5F) ++#define REG_SC_BK1A_5F_H _PK_H_(0x1A, 0x5F) ++#define REG_SC_BK1A_60_L _PK_L_(0x1A, 0x60) ++#define REG_SC_BK1A_60_H _PK_H_(0x1A, 0x60) ++#define REG_SC_BK1A_61_L _PK_L_(0x1A, 0x61) ++#define REG_SC_BK1A_61_H _PK_H_(0x1A, 0x61) ++#define REG_SC_BK1A_62_L _PK_L_(0x1A, 0x62) ++#define REG_SC_BK1A_62_H _PK_H_(0x1A, 0x62) ++#define REG_SC_BK1A_63_L _PK_L_(0x1A, 0x63) ++#define REG_SC_BK1A_63_H _PK_H_(0x1A, 0x63) ++#define REG_SC_BK1A_64_L _PK_L_(0x1A, 0x64) ++#define REG_SC_BK1A_64_H _PK_H_(0x1A, 0x64) ++#define REG_SC_BK1A_65_L _PK_L_(0x1A, 0x65) ++#define REG_SC_BK1A_65_H _PK_H_(0x1A, 0x65) ++#define REG_SC_BK1A_66_L _PK_L_(0x1A, 0x66) ++#define REG_SC_BK1A_66_H _PK_H_(0x1A, 0x66) ++#define REG_SC_BK1A_67_L _PK_L_(0x1A, 0x67) ++#define REG_SC_BK1A_67_H _PK_H_(0x1A, 0x67) ++#define REG_SC_BK1A_68_L _PK_L_(0x1A, 0x68) ++#define REG_SC_BK1A_68_H _PK_H_(0x1A, 0x68) ++#define REG_SC_BK1A_69_L _PK_L_(0x1A, 0x69) ++#define REG_SC_BK1A_69_H _PK_H_(0x1A, 0x69) ++#define REG_SC_BK1A_6A_L _PK_L_(0x1A, 0x6A) ++#define REG_SC_BK1A_6A_H _PK_H_(0x1A, 0x6A) ++#define REG_SC_BK1A_6B_L _PK_L_(0x1A, 0x6B) ++#define REG_SC_BK1A_6B_H _PK_H_(0x1A, 0x6B) ++#define REG_SC_BK1A_6C_L _PK_L_(0x1A, 0x6C) ++#define REG_SC_BK1A_6C_H _PK_H_(0x1A, 0x6C) ++#define REG_SC_BK1A_6D_L _PK_L_(0x1A, 0x6D) ++#define REG_SC_BK1A_6D_H _PK_H_(0x1A, 0x6D) ++#define REG_SC_BK1A_6E_L _PK_L_(0x1A, 0x6E) ++#define REG_SC_BK1A_6E_H _PK_H_(0x1A, 0x6E) ++#define REG_SC_BK1A_6F_L _PK_L_(0x1A, 0x6F) ++#define REG_SC_BK1A_6F_H _PK_H_(0x1A, 0x6F) ++#define REG_SC_BK1A_70_L _PK_L_(0x1A, 0x70) ++#define REG_SC_BK1A_70_H _PK_H_(0x1A, 0x70) ++#define REG_SC_BK1A_71_L _PK_L_(0x1A, 0x71) ++#define REG_SC_BK1A_71_H _PK_H_(0x1A, 0x71) ++#define REG_SC_BK1A_72_L _PK_L_(0x1A, 0x72) ++#define REG_SC_BK1A_72_H _PK_H_(0x1A, 0x72) ++#define REG_SC_BK1A_73_L _PK_L_(0x1A, 0x73) ++#define REG_SC_BK1A_73_H _PK_H_(0x1A, 0x73) ++#define REG_SC_BK1A_74_L _PK_L_(0x1A, 0x74) ++#define REG_SC_BK1A_74_H _PK_H_(0x1A, 0x74) ++#define REG_SC_BK1A_75_L _PK_L_(0x1A, 0x75) ++#define REG_SC_BK1A_75_H _PK_H_(0x1A, 0x75) ++#define REG_SC_BK1A_76_L _PK_L_(0x1A, 0x76) ++#define REG_SC_BK1A_76_H _PK_H_(0x1A, 0x76) ++#define REG_SC_BK1A_77_L _PK_L_(0x1A, 0x77) ++#define REG_SC_BK1A_77_H _PK_H_(0x1A, 0x77) ++#define REG_SC_BK1A_78_L _PK_L_(0x1A, 0x78) ++#define REG_SC_BK1A_78_H _PK_H_(0x1A, 0x78) ++#define REG_SC_BK1A_79_L _PK_L_(0x1A, 0x79) ++#define REG_SC_BK1A_79_H _PK_H_(0x1A, 0x79) ++#define REG_SC_BK1A_7A_L _PK_L_(0x1A, 0x7A) ++#define REG_SC_BK1A_7A_H _PK_H_(0x1A, 0x7A) ++#define REG_SC_BK1A_7B_L _PK_L_(0x1A, 0x7B) ++#define REG_SC_BK1A_7B_H _PK_H_(0x1A, 0x7B) ++#define REG_SC_BK1A_7C_L _PK_L_(0x1A, 0x7C) ++#define REG_SC_BK1A_7C_H _PK_H_(0x1A, 0x7C) ++#define REG_SC_BK1A_7D_L _PK_L_(0x1A, 0x7D) ++#define REG_SC_BK1A_7D_H _PK_H_(0x1A, 0x7D) ++#define REG_SC_BK1A_7E_L _PK_L_(0x1A, 0x7E) ++#define REG_SC_BK1A_7E_H _PK_H_(0x1A, 0x7E) ++#define REG_SC_BK1A_7F_L _PK_L_(0x1A, 0x7F) ++#define REG_SC_BK1A_7F_H _PK_H_(0x1A, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1B_00_L _PK_L_(0x1B, 0x00) ++#define REG_SC_BK1B_00_H _PK_H_(0x1B, 0x00) ++#define REG_SC_BK1B_01_L _PK_L_(0x1B, 0x01) ++#define REG_SC_BK1B_01_H _PK_H_(0x1B, 0x01) ++#define REG_SC_BK1B_02_L _PK_L_(0x1B, 0x02) ++#define REG_SC_BK1B_02_H _PK_H_(0x1B, 0x02) ++#define REG_SC_BK1B_03_L _PK_L_(0x1B, 0x03) ++#define REG_SC_BK1B_03_H _PK_H_(0x1B, 0x03) ++#define REG_SC_BK1B_04_L _PK_L_(0x1B, 0x04) ++#define REG_SC_BK1B_04_H _PK_H_(0x1B, 0x04) ++#define REG_SC_BK1B_05_L _PK_L_(0x1B, 0x05) ++#define REG_SC_BK1B_05_H _PK_H_(0x1B, 0x05) ++#define REG_SC_BK1B_06_L _PK_L_(0x1B, 0x06) ++#define REG_SC_BK1B_06_H _PK_H_(0x1B, 0x06) ++#define REG_SC_BK1B_07_L _PK_L_(0x1B, 0x07) ++#define REG_SC_BK1B_07_H _PK_H_(0x1B, 0x07) ++#define REG_SC_BK1B_08_L _PK_L_(0x1B, 0x08) ++#define REG_SC_BK1B_08_H _PK_H_(0x1B, 0x08) ++#define REG_SC_BK1B_09_L _PK_L_(0x1B, 0x09) ++#define REG_SC_BK1B_09_H _PK_H_(0x1B, 0x09) ++#define REG_SC_BK1B_0A_L _PK_L_(0x1B, 0x0A) ++#define REG_SC_BK1B_0A_H _PK_H_(0x1B, 0x0A) ++#define REG_SC_BK1B_0B_L _PK_L_(0x1B, 0x0B) ++#define REG_SC_BK1B_0B_H _PK_H_(0x1B, 0x0B) ++#define REG_SC_BK1B_0C_L _PK_L_(0x1B, 0x0C) ++#define REG_SC_BK1B_0C_H _PK_H_(0x1B, 0x0C) ++#define REG_SC_BK1B_0D_L _PK_L_(0x1B, 0x0D) ++#define REG_SC_BK1B_0D_H _PK_H_(0x1B, 0x0D) ++#define REG_SC_BK1B_0E_L _PK_L_(0x1B, 0x0E) ++#define REG_SC_BK1B_0E_H _PK_H_(0x1B, 0x0E) ++#define REG_SC_BK1B_0F_L _PK_L_(0x1B, 0x0F) ++#define REG_SC_BK1B_0F_H _PK_H_(0x1B, 0x0F) ++#define REG_SC_BK1B_10_L _PK_L_(0x1B, 0x10) ++#define REG_SC_BK1B_10_H _PK_H_(0x1B, 0x10) ++#define REG_SC_BK1B_11_L _PK_L_(0x1B, 0x11) ++#define REG_SC_BK1B_11_H _PK_H_(0x1B, 0x11) ++#define REG_SC_BK1B_12_L _PK_L_(0x1B, 0x12) ++#define REG_SC_BK1B_12_H _PK_H_(0x1B, 0x12) ++#define REG_SC_BK1B_13_L _PK_L_(0x1B, 0x13) ++#define REG_SC_BK1B_13_H _PK_H_(0x1B, 0x13) ++#define REG_SC_BK1B_14_L _PK_L_(0x1B, 0x14) ++#define REG_SC_BK1B_14_H _PK_H_(0x1B, 0x14) ++#define REG_SC_BK1B_15_L _PK_L_(0x1B, 0x15) ++#define REG_SC_BK1B_15_H _PK_H_(0x1B, 0x15) ++#define REG_SC_BK1B_16_L _PK_L_(0x1B, 0x16) ++#define REG_SC_BK1B_16_H _PK_H_(0x1B, 0x16) ++#define REG_SC_BK1B_17_L _PK_L_(0x1B, 0x17) ++#define REG_SC_BK1B_17_H _PK_H_(0x1B, 0x17) ++#define REG_SC_BK1B_18_L _PK_L_(0x1B, 0x18) ++#define REG_SC_BK1B_18_H _PK_H_(0x1B, 0x18) ++#define REG_SC_BK1B_19_L _PK_L_(0x1B, 0x19) ++#define REG_SC_BK1B_19_H _PK_H_(0x1B, 0x19) ++#define REG_SC_BK1B_1A_L _PK_L_(0x1B, 0x1A) ++#define REG_SC_BK1B_1A_H _PK_H_(0x1B, 0x1A) ++#define REG_SC_BK1B_1B_L _PK_L_(0x1B, 0x1B) ++#define REG_SC_BK1B_1B_H _PK_H_(0x1B, 0x1B) ++#define REG_SC_BK1B_1C_L _PK_L_(0x1B, 0x1C) ++#define REG_SC_BK1B_1C_H _PK_H_(0x1B, 0x1C) ++#define REG_SC_BK1B_1D_L _PK_L_(0x1B, 0x1D) ++#define REG_SC_BK1B_1D_H _PK_H_(0x1B, 0x1D) ++#define REG_SC_BK1B_1E_L _PK_L_(0x1B, 0x1E) ++#define REG_SC_BK1B_1E_H _PK_H_(0x1B, 0x1E) ++#define REG_SC_BK1B_1F_L _PK_L_(0x1B, 0x1F) ++#define REG_SC_BK1B_1F_H _PK_H_(0x1B, 0x1F) ++#define REG_SC_BK1B_20_L _PK_L_(0x1B, 0x20) ++#define REG_SC_BK1B_20_H _PK_H_(0x1B, 0x20) ++#define REG_SC_BK1B_21_L _PK_L_(0x1B, 0x21) ++#define REG_SC_BK1B_21_H _PK_H_(0x1B, 0x21) ++#define REG_SC_BK1B_22_L _PK_L_(0x1B, 0x22) ++#define REG_SC_BK1B_22_H _PK_H_(0x1B, 0x22) ++#define REG_SC_BK1B_23_L _PK_L_(0x1B, 0x23) ++#define REG_SC_BK1B_23_H _PK_H_(0x1B, 0x23) ++#define REG_SC_BK1B_24_L _PK_L_(0x1B, 0x24) ++#define REG_SC_BK1B_24_H _PK_H_(0x1B, 0x24) ++#define REG_SC_BK1B_25_L _PK_L_(0x1B, 0x25) ++#define REG_SC_BK1B_25_H _PK_H_(0x1B, 0x25) ++#define REG_SC_BK1B_26_L _PK_L_(0x1B, 0x26) ++#define REG_SC_BK1B_26_H _PK_H_(0x1B, 0x26) ++#define REG_SC_BK1B_27_L _PK_L_(0x1B, 0x27) ++#define REG_SC_BK1B_27_H _PK_H_(0x1B, 0x27) ++#define REG_SC_BK1B_28_L _PK_L_(0x1B, 0x28) ++#define REG_SC_BK1B_28_H _PK_H_(0x1B, 0x28) ++#define REG_SC_BK1B_29_L _PK_L_(0x1B, 0x29) ++#define REG_SC_BK1B_29_H _PK_H_(0x1B, 0x29) ++#define REG_SC_BK1B_2A_L _PK_L_(0x1B, 0x2A) ++#define REG_SC_BK1B_2A_H _PK_H_(0x1B, 0x2A) ++#define REG_SC_BK1B_2B_L _PK_L_(0x1B, 0x2B) ++#define REG_SC_BK1B_2B_H _PK_H_(0x1B, 0x2B) ++#define REG_SC_BK1B_2C_L _PK_L_(0x1B, 0x2C) ++#define REG_SC_BK1B_2C_H _PK_H_(0x1B, 0x2C) ++#define REG_SC_BK1B_2D_L _PK_L_(0x1B, 0x2D) ++#define REG_SC_BK1B_2D_H _PK_H_(0x1B, 0x2D) ++#define REG_SC_BK1B_2E_L _PK_L_(0x1B, 0x2E) ++#define REG_SC_BK1B_2E_H _PK_H_(0x1B, 0x2E) ++#define REG_SC_BK1B_2F_L _PK_L_(0x1B, 0x2F) ++#define REG_SC_BK1B_2F_H _PK_H_(0x1B, 0x2F) ++#define REG_SC_BK1B_30_L _PK_L_(0x1B, 0x30) ++#define REG_SC_BK1B_30_H _PK_H_(0x1B, 0x30) ++#define REG_SC_BK1B_31_L _PK_L_(0x1B, 0x31) ++#define REG_SC_BK1B_31_H _PK_H_(0x1B, 0x31) ++#define REG_SC_BK1B_32_L _PK_L_(0x1B, 0x32) ++#define REG_SC_BK1B_32_H _PK_H_(0x1B, 0x32) ++#define REG_SC_BK1B_33_L _PK_L_(0x1B, 0x33) ++#define REG_SC_BK1B_33_H _PK_H_(0x1B, 0x33) ++#define REG_SC_BK1B_34_L _PK_L_(0x1B, 0x34) ++#define REG_SC_BK1B_34_H _PK_H_(0x1B, 0x34) ++#define REG_SC_BK1B_35_L _PK_L_(0x1B, 0x35) ++#define REG_SC_BK1B_35_H _PK_H_(0x1B, 0x35) ++#define REG_SC_BK1B_36_L _PK_L_(0x1B, 0x36) ++#define REG_SC_BK1B_36_H _PK_H_(0x1B, 0x36) ++#define REG_SC_BK1B_37_L _PK_L_(0x1B, 0x37) ++#define REG_SC_BK1B_37_H _PK_H_(0x1B, 0x37) ++#define REG_SC_BK1B_38_L _PK_L_(0x1B, 0x38) ++#define REG_SC_BK1B_38_H _PK_H_(0x1B, 0x38) ++#define REG_SC_BK1B_39_L _PK_L_(0x1B, 0x39) ++#define REG_SC_BK1B_39_H _PK_H_(0x1B, 0x39) ++#define REG_SC_BK1B_3A_L _PK_L_(0x1B, 0x3A) ++#define REG_SC_BK1B_3A_H _PK_H_(0x1B, 0x3A) ++#define REG_SC_BK1B_3B_L _PK_L_(0x1B, 0x3B) ++#define REG_SC_BK1B_3B_H _PK_H_(0x1B, 0x3B) ++#define REG_SC_BK1B_3C_L _PK_L_(0x1B, 0x3C) ++#define REG_SC_BK1B_3C_H _PK_H_(0x1B, 0x3C) ++#define REG_SC_BK1B_3D_L _PK_L_(0x1B, 0x3D) ++#define REG_SC_BK1B_3D_H _PK_H_(0x1B, 0x3D) ++#define REG_SC_BK1B_3E_L _PK_L_(0x1B, 0x3E) ++#define REG_SC_BK1B_3E_H _PK_H_(0x1B, 0x3E) ++#define REG_SC_BK1B_3F_L _PK_L_(0x1B, 0x3F) ++#define REG_SC_BK1B_3F_H _PK_H_(0x1B, 0x3F) ++#define REG_SC_BK1B_40_L _PK_L_(0x1B, 0x40) ++#define REG_SC_BK1B_40_H _PK_H_(0x1B, 0x40) ++#define REG_SC_BK1B_41_L _PK_L_(0x1B, 0x41) ++#define REG_SC_BK1B_41_H _PK_H_(0x1B, 0x41) ++#define REG_SC_BK1B_42_L _PK_L_(0x1B, 0x42) ++#define REG_SC_BK1B_42_H _PK_H_(0x1B, 0x42) ++#define REG_SC_BK1B_43_L _PK_L_(0x1B, 0x43) ++#define REG_SC_BK1B_43_H _PK_H_(0x1B, 0x43) ++#define REG_SC_BK1B_44_L _PK_L_(0x1B, 0x44) ++#define REG_SC_BK1B_44_H _PK_H_(0x1B, 0x44) ++#define REG_SC_BK1B_45_L _PK_L_(0x1B, 0x45) ++#define REG_SC_BK1B_45_H _PK_H_(0x1B, 0x45) ++#define REG_SC_BK1B_46_L _PK_L_(0x1B, 0x46) ++#define REG_SC_BK1B_46_H _PK_H_(0x1B, 0x46) ++#define REG_SC_BK1B_47_L _PK_L_(0x1B, 0x47) ++#define REG_SC_BK1B_47_H _PK_H_(0x1B, 0x47) ++#define REG_SC_BK1B_48_L _PK_L_(0x1B, 0x48) ++#define REG_SC_BK1B_48_H _PK_H_(0x1B, 0x48) ++#define REG_SC_BK1B_49_L _PK_L_(0x1B, 0x49) ++#define REG_SC_BK1B_49_H _PK_H_(0x1B, 0x49) ++#define REG_SC_BK1B_4A_L _PK_L_(0x1B, 0x4A) ++#define REG_SC_BK1B_4A_H _PK_H_(0x1B, 0x4A) ++#define REG_SC_BK1B_4B_L _PK_L_(0x1B, 0x4B) ++#define REG_SC_BK1B_4B_H _PK_H_(0x1B, 0x4B) ++#define REG_SC_BK1B_4C_L _PK_L_(0x1B, 0x4C) ++#define REG_SC_BK1B_4C_H _PK_H_(0x1B, 0x4C) ++#define REG_SC_BK1B_4D_L _PK_L_(0x1B, 0x4D) ++#define REG_SC_BK1B_4D_H _PK_H_(0x1B, 0x4D) ++#define REG_SC_BK1B_4E_L _PK_L_(0x1B, 0x4E) ++#define REG_SC_BK1B_4E_H _PK_H_(0x1B, 0x4E) ++#define REG_SC_BK1B_4F_L _PK_L_(0x1B, 0x4F) ++#define REG_SC_BK1B_4F_H _PK_H_(0x1B, 0x4F) ++#define REG_SC_BK1B_50_L _PK_L_(0x1B, 0x50) ++#define REG_SC_BK1B_50_H _PK_H_(0x1B, 0x50) ++#define REG_SC_BK1B_51_L _PK_L_(0x1B, 0x51) ++#define REG_SC_BK1B_51_H _PK_H_(0x1B, 0x51) ++#define REG_SC_BK1B_52_L _PK_L_(0x1B, 0x52) ++#define REG_SC_BK1B_52_H _PK_H_(0x1B, 0x52) ++#define REG_SC_BK1B_53_L _PK_L_(0x1B, 0x53) ++#define REG_SC_BK1B_53_H _PK_H_(0x1B, 0x53) ++#define REG_SC_BK1B_54_L _PK_L_(0x1B, 0x54) ++#define REG_SC_BK1B_54_H _PK_H_(0x1B, 0x54) ++#define REG_SC_BK1B_55_L _PK_L_(0x1B, 0x55) ++#define REG_SC_BK1B_55_H _PK_H_(0x1B, 0x55) ++#define REG_SC_BK1B_56_L _PK_L_(0x1B, 0x56) ++#define REG_SC_BK1B_56_H _PK_H_(0x1B, 0x56) ++#define REG_SC_BK1B_57_L _PK_L_(0x1B, 0x57) ++#define REG_SC_BK1B_57_H _PK_H_(0x1B, 0x57) ++#define REG_SC_BK1B_58_L _PK_L_(0x1B, 0x58) ++#define REG_SC_BK1B_58_H _PK_H_(0x1B, 0x58) ++#define REG_SC_BK1B_59_L _PK_L_(0x1B, 0x59) ++#define REG_SC_BK1B_59_H _PK_H_(0x1B, 0x59) ++#define REG_SC_BK1B_5A_L _PK_L_(0x1B, 0x5A) ++#define REG_SC_BK1B_5A_H _PK_H_(0x1B, 0x5A) ++#define REG_SC_BK1B_5B_L _PK_L_(0x1B, 0x5B) ++#define REG_SC_BK1B_5B_H _PK_H_(0x1B, 0x5B) ++#define REG_SC_BK1B_5C_L _PK_L_(0x1B, 0x5C) ++#define REG_SC_BK1B_5C_H _PK_H_(0x1B, 0x5C) ++#define REG_SC_BK1B_5D_L _PK_L_(0x1B, 0x5D) ++#define REG_SC_BK1B_5D_H _PK_H_(0x1B, 0x5D) ++#define REG_SC_BK1B_5E_L _PK_L_(0x1B, 0x5E) ++#define REG_SC_BK1B_5E_H _PK_H_(0x1B, 0x5E) ++#define REG_SC_BK1B_5F_L _PK_L_(0x1B, 0x5F) ++#define REG_SC_BK1B_5F_H _PK_H_(0x1B, 0x5F) ++#define REG_SC_BK1B_60_L _PK_L_(0x1B, 0x60) ++#define REG_SC_BK1B_60_H _PK_H_(0x1B, 0x60) ++#define REG_SC_BK1B_61_L _PK_L_(0x1B, 0x61) ++#define REG_SC_BK1B_61_H _PK_H_(0x1B, 0x61) ++#define REG_SC_BK1B_62_L _PK_L_(0x1B, 0x62) ++#define REG_SC_BK1B_62_H _PK_H_(0x1B, 0x62) ++#define REG_SC_BK1B_63_L _PK_L_(0x1B, 0x63) ++#define REG_SC_BK1B_63_H _PK_H_(0x1B, 0x63) ++#define REG_SC_BK1B_64_L _PK_L_(0x1B, 0x64) ++#define REG_SC_BK1B_64_H _PK_H_(0x1B, 0x64) ++#define REG_SC_BK1B_65_L _PK_L_(0x1B, 0x65) ++#define REG_SC_BK1B_65_H _PK_H_(0x1B, 0x65) ++#define REG_SC_BK1B_66_L _PK_L_(0x1B, 0x66) ++#define REG_SC_BK1B_66_H _PK_H_(0x1B, 0x66) ++#define REG_SC_BK1B_67_L _PK_L_(0x1B, 0x67) ++#define REG_SC_BK1B_67_H _PK_H_(0x1B, 0x67) ++#define REG_SC_BK1B_68_L _PK_L_(0x1B, 0x68) ++#define REG_SC_BK1B_68_H _PK_H_(0x1B, 0x68) ++#define REG_SC_BK1B_69_L _PK_L_(0x1B, 0x69) ++#define REG_SC_BK1B_69_H _PK_H_(0x1B, 0x69) ++#define REG_SC_BK1B_6A_L _PK_L_(0x1B, 0x6A) ++#define REG_SC_BK1B_6A_H _PK_H_(0x1B, 0x6A) ++#define REG_SC_BK1B_6B_L _PK_L_(0x1B, 0x6B) ++#define REG_SC_BK1B_6B_H _PK_H_(0x1B, 0x6B) ++#define REG_SC_BK1B_6C_L _PK_L_(0x1B, 0x6C) ++#define REG_SC_BK1B_6C_H _PK_H_(0x1B, 0x6C) ++#define REG_SC_BK1B_6D_L _PK_L_(0x1B, 0x6D) ++#define REG_SC_BK1B_6D_H _PK_H_(0x1B, 0x6D) ++#define REG_SC_BK1B_6E_L _PK_L_(0x1B, 0x6E) ++#define REG_SC_BK1B_6E_H _PK_H_(0x1B, 0x6E) ++#define REG_SC_BK1B_6F_L _PK_L_(0x1B, 0x6F) ++#define REG_SC_BK1B_6F_H _PK_H_(0x1B, 0x6F) ++#define REG_SC_BK1B_70_L _PK_L_(0x1B, 0x70) ++#define REG_SC_BK1B_70_H _PK_H_(0x1B, 0x70) ++#define REG_SC_BK1B_71_L _PK_L_(0x1B, 0x71) ++#define REG_SC_BK1B_71_H _PK_H_(0x1B, 0x71) ++#define REG_SC_BK1B_72_L _PK_L_(0x1B, 0x72) ++#define REG_SC_BK1B_72_H _PK_H_(0x1B, 0x72) ++#define REG_SC_BK1B_73_L _PK_L_(0x1B, 0x73) ++#define REG_SC_BK1B_73_H _PK_H_(0x1B, 0x73) ++#define REG_SC_BK1B_74_L _PK_L_(0x1B, 0x74) ++#define REG_SC_BK1B_74_H _PK_H_(0x1B, 0x74) ++#define REG_SC_BK1B_75_L _PK_L_(0x1B, 0x75) ++#define REG_SC_BK1B_75_H _PK_H_(0x1B, 0x75) ++#define REG_SC_BK1B_76_L _PK_L_(0x1B, 0x76) ++#define REG_SC_BK1B_76_H _PK_H_(0x1B, 0x76) ++#define REG_SC_BK1B_77_L _PK_L_(0x1B, 0x77) ++#define REG_SC_BK1B_77_H _PK_H_(0x1B, 0x77) ++#define REG_SC_BK1B_78_L _PK_L_(0x1B, 0x78) ++#define REG_SC_BK1B_78_H _PK_H_(0x1B, 0x78) ++#define REG_SC_BK1B_79_L _PK_L_(0x1B, 0x79) ++#define REG_SC_BK1B_79_H _PK_H_(0x1B, 0x79) ++#define REG_SC_BK1B_7A_L _PK_L_(0x1B, 0x7A) ++#define REG_SC_BK1B_7A_H _PK_H_(0x1B, 0x7A) ++#define REG_SC_BK1B_7B_L _PK_L_(0x1B, 0x7B) ++#define REG_SC_BK1B_7B_H _PK_H_(0x1B, 0x7B) ++#define REG_SC_BK1B_7C_L _PK_L_(0x1B, 0x7C) ++#define REG_SC_BK1B_7C_H _PK_H_(0x1B, 0x7C) ++#define REG_SC_BK1B_7D_L _PK_L_(0x1B, 0x7D) ++#define REG_SC_BK1B_7D_H _PK_H_(0x1B, 0x7D) ++#define REG_SC_BK1B_7E_L _PK_L_(0x1B, 0x7E) ++#define REG_SC_BK1B_7E_H _PK_H_(0x1B, 0x7E) ++#define REG_SC_BK1B_7F_L _PK_L_(0x1B, 0x7F) ++#define REG_SC_BK1B_7F_H _PK_H_(0x1B, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1C_00_L _PK_L_(0x1C, 0x00) ++#define REG_SC_BK1C_00_H _PK_H_(0x1C, 0x00) ++#define REG_SC_BK1C_01_L _PK_L_(0x1C, 0x01) ++#define REG_SC_BK1C_01_H _PK_H_(0x1C, 0x01) ++#define REG_SC_BK1C_02_L _PK_L_(0x1C, 0x02) ++#define REG_SC_BK1C_02_H _PK_H_(0x1C, 0x02) ++#define REG_SC_BK1C_03_L _PK_L_(0x1C, 0x03) ++#define REG_SC_BK1C_03_H _PK_H_(0x1C, 0x03) ++#define REG_SC_BK1C_04_L _PK_L_(0x1C, 0x04) ++#define REG_SC_BK1C_04_H _PK_H_(0x1C, 0x04) ++#define REG_SC_BK1C_05_L _PK_L_(0x1C, 0x05) ++#define REG_SC_BK1C_05_H _PK_H_(0x1C, 0x05) ++#define REG_SC_BK1C_06_L _PK_L_(0x1C, 0x06) ++#define REG_SC_BK1C_06_H _PK_H_(0x1C, 0x06) ++#define REG_SC_BK1C_07_L _PK_L_(0x1C, 0x07) ++#define REG_SC_BK1C_07_H _PK_H_(0x1C, 0x07) ++#define REG_SC_BK1C_08_L _PK_L_(0x1C, 0x08) ++#define REG_SC_BK1C_08_H _PK_H_(0x1C, 0x08) ++#define REG_SC_BK1C_09_L _PK_L_(0x1C, 0x09) ++#define REG_SC_BK1C_09_H _PK_H_(0x1C, 0x09) ++#define REG_SC_BK1C_0A_L _PK_L_(0x1C, 0x0A) ++#define REG_SC_BK1C_0A_H _PK_H_(0x1C, 0x0A) ++#define REG_SC_BK1C_0B_L _PK_L_(0x1C, 0x0B) ++#define REG_SC_BK1C_0B_H _PK_H_(0x1C, 0x0B) ++#define REG_SC_BK1C_0C_L _PK_L_(0x1C, 0x0C) ++#define REG_SC_BK1C_0C_H _PK_H_(0x1C, 0x0C) ++#define REG_SC_BK1C_0D_L _PK_L_(0x1C, 0x0D) ++#define REG_SC_BK1C_0D_H _PK_H_(0x1C, 0x0D) ++#define REG_SC_BK1C_0E_L _PK_L_(0x1C, 0x0E) ++#define REG_SC_BK1C_0E_H _PK_H_(0x1C, 0x0E) ++#define REG_SC_BK1C_0F_L _PK_L_(0x1C, 0x0F) ++#define REG_SC_BK1C_0F_H _PK_H_(0x1C, 0x0F) ++#define REG_SC_BK1C_10_L _PK_L_(0x1C, 0x10) ++#define REG_SC_BK1C_10_H _PK_H_(0x1C, 0x10) ++#define REG_SC_BK1C_11_L _PK_L_(0x1C, 0x11) ++#define REG_SC_BK1C_11_H _PK_H_(0x1C, 0x11) ++#define REG_SC_BK1C_12_L _PK_L_(0x1C, 0x12) ++#define REG_SC_BK1C_12_H _PK_H_(0x1C, 0x12) ++#define REG_SC_BK1C_13_L _PK_L_(0x1C, 0x13) ++#define REG_SC_BK1C_13_H _PK_H_(0x1C, 0x13) ++#define REG_SC_BK1C_14_L _PK_L_(0x1C, 0x14) ++#define REG_SC_BK1C_14_H _PK_H_(0x1C, 0x14) ++#define REG_SC_BK1C_15_L _PK_L_(0x1C, 0x15) ++#define REG_SC_BK1C_15_H _PK_H_(0x1C, 0x15) ++#define REG_SC_BK1C_16_L _PK_L_(0x1C, 0x16) ++#define REG_SC_BK1C_16_H _PK_H_(0x1C, 0x16) ++#define REG_SC_BK1C_17_L _PK_L_(0x1C, 0x17) ++#define REG_SC_BK1C_17_H _PK_H_(0x1C, 0x17) ++#define REG_SC_BK1C_18_L _PK_L_(0x1C, 0x18) ++#define REG_SC_BK1C_18_H _PK_H_(0x1C, 0x18) ++#define REG_SC_BK1C_19_L _PK_L_(0x1C, 0x19) ++#define REG_SC_BK1C_19_H _PK_H_(0x1C, 0x19) ++#define REG_SC_BK1C_1A_L _PK_L_(0x1C, 0x1A) ++#define REG_SC_BK1C_1A_H _PK_H_(0x1C, 0x1A) ++#define REG_SC_BK1C_1B_L _PK_L_(0x1C, 0x1B) ++#define REG_SC_BK1C_1B_H _PK_H_(0x1C, 0x1B) ++#define REG_SC_BK1C_1C_L _PK_L_(0x1C, 0x1C) ++#define REG_SC_BK1C_1C_H _PK_H_(0x1C, 0x1C) ++#define REG_SC_BK1C_1D_L _PK_L_(0x1C, 0x1D) ++#define REG_SC_BK1C_1D_H _PK_H_(0x1C, 0x1D) ++#define REG_SC_BK1C_1E_L _PK_L_(0x1C, 0x1E) ++#define REG_SC_BK1C_1E_H _PK_H_(0x1C, 0x1E) ++#define REG_SC_BK1C_1F_L _PK_L_(0x1C, 0x1F) ++#define REG_SC_BK1C_1F_H _PK_H_(0x1C, 0x1F) ++#define REG_SC_BK1C_20_L _PK_L_(0x1C, 0x20) ++#define REG_SC_BK1C_20_H _PK_H_(0x1C, 0x20) ++#define REG_SC_BK1C_21_L _PK_L_(0x1C, 0x21) ++#define REG_SC_BK1C_21_H _PK_H_(0x1C, 0x21) ++#define REG_SC_BK1C_22_L _PK_L_(0x1C, 0x22) ++#define REG_SC_BK1C_22_H _PK_H_(0x1C, 0x22) ++#define REG_SC_BK1C_23_L _PK_L_(0x1C, 0x23) ++#define REG_SC_BK1C_23_H _PK_H_(0x1C, 0x23) ++#define REG_SC_BK1C_24_L _PK_L_(0x1C, 0x24) ++#define REG_SC_BK1C_24_H _PK_H_(0x1C, 0x24) ++#define REG_SC_BK1C_25_L _PK_L_(0x1C, 0x25) ++#define REG_SC_BK1C_25_H _PK_H_(0x1C, 0x25) ++#define REG_SC_BK1C_26_L _PK_L_(0x1C, 0x26) ++#define REG_SC_BK1C_26_H _PK_H_(0x1C, 0x26) ++#define REG_SC_BK1C_27_L _PK_L_(0x1C, 0x27) ++#define REG_SC_BK1C_27_H _PK_H_(0x1C, 0x27) ++#define REG_SC_BK1C_28_L _PK_L_(0x1C, 0x28) ++#define REG_SC_BK1C_28_H _PK_H_(0x1C, 0x28) ++#define REG_SC_BK1C_29_L _PK_L_(0x1C, 0x29) ++#define REG_SC_BK1C_29_H _PK_H_(0x1C, 0x29) ++#define REG_SC_BK1C_2A_L _PK_L_(0x1C, 0x2A) ++#define REG_SC_BK1C_2A_H _PK_H_(0x1C, 0x2A) ++#define REG_SC_BK1C_2B_L _PK_L_(0x1C, 0x2B) ++#define REG_SC_BK1C_2B_H _PK_H_(0x1C, 0x2B) ++#define REG_SC_BK1C_2C_L _PK_L_(0x1C, 0x2C) ++#define REG_SC_BK1C_2C_H _PK_H_(0x1C, 0x2C) ++#define REG_SC_BK1C_2D_L _PK_L_(0x1C, 0x2D) ++#define REG_SC_BK1C_2D_H _PK_H_(0x1C, 0x2D) ++#define REG_SC_BK1C_2E_L _PK_L_(0x1C, 0x2E) ++#define REG_SC_BK1C_2E_H _PK_H_(0x1C, 0x2E) ++#define REG_SC_BK1C_2F_L _PK_L_(0x1C, 0x2F) ++#define REG_SC_BK1C_2F_H _PK_H_(0x1C, 0x2F) ++#define REG_SC_BK1C_30_L _PK_L_(0x1C, 0x30) ++#define REG_SC_BK1C_30_H _PK_H_(0x1C, 0x30) ++#define REG_SC_BK1C_31_L _PK_L_(0x1C, 0x31) ++#define REG_SC_BK1C_31_H _PK_H_(0x1C, 0x31) ++#define REG_SC_BK1C_32_L _PK_L_(0x1C, 0x32) ++#define REG_SC_BK1C_32_H _PK_H_(0x1C, 0x32) ++#define REG_SC_BK1C_33_L _PK_L_(0x1C, 0x33) ++#define REG_SC_BK1C_33_H _PK_H_(0x1C, 0x33) ++#define REG_SC_BK1C_34_L _PK_L_(0x1C, 0x34) ++#define REG_SC_BK1C_34_H _PK_H_(0x1C, 0x34) ++#define REG_SC_BK1C_35_L _PK_L_(0x1C, 0x35) ++#define REG_SC_BK1C_35_H _PK_H_(0x1C, 0x35) ++#define REG_SC_BK1C_36_L _PK_L_(0x1C, 0x36) ++#define REG_SC_BK1C_36_H _PK_H_(0x1C, 0x36) ++#define REG_SC_BK1C_37_L _PK_L_(0x1C, 0x37) ++#define REG_SC_BK1C_37_H _PK_H_(0x1C, 0x37) ++#define REG_SC_BK1C_38_L _PK_L_(0x1C, 0x38) ++#define REG_SC_BK1C_38_H _PK_H_(0x1C, 0x38) ++#define REG_SC_BK1C_39_L _PK_L_(0x1C, 0x39) ++#define REG_SC_BK1C_39_H _PK_H_(0x1C, 0x39) ++#define REG_SC_BK1C_3A_L _PK_L_(0x1C, 0x3A) ++#define REG_SC_BK1C_3A_H _PK_H_(0x1C, 0x3A) ++#define REG_SC_BK1C_3B_L _PK_L_(0x1C, 0x3B) ++#define REG_SC_BK1C_3B_H _PK_H_(0x1C, 0x3B) ++#define REG_SC_BK1C_3C_L _PK_L_(0x1C, 0x3C) ++#define REG_SC_BK1C_3C_H _PK_H_(0x1C, 0x3C) ++#define REG_SC_BK1C_3D_L _PK_L_(0x1C, 0x3D) ++#define REG_SC_BK1C_3D_H _PK_H_(0x1C, 0x3D) ++#define REG_SC_BK1C_3E_L _PK_L_(0x1C, 0x3E) ++#define REG_SC_BK1C_3E_H _PK_H_(0x1C, 0x3E) ++#define REG_SC_BK1C_3F_L _PK_L_(0x1C, 0x3F) ++#define REG_SC_BK1C_3F_H _PK_H_(0x1C, 0x3F) ++#define REG_SC_BK1C_40_L _PK_L_(0x1C, 0x40) ++#define REG_SC_BK1C_40_H _PK_H_(0x1C, 0x40) ++#define REG_SC_BK1C_41_L _PK_L_(0x1C, 0x41) ++#define REG_SC_BK1C_41_H _PK_H_(0x1C, 0x41) ++#define REG_SC_BK1C_42_L _PK_L_(0x1C, 0x42) ++#define REG_SC_BK1C_42_H _PK_H_(0x1C, 0x42) ++#define REG_SC_BK1C_43_L _PK_L_(0x1C, 0x43) ++#define REG_SC_BK1C_43_H _PK_H_(0x1C, 0x43) ++#define REG_SC_BK1C_44_L _PK_L_(0x1C, 0x44) ++#define REG_SC_BK1C_44_H _PK_H_(0x1C, 0x44) ++#define REG_SC_BK1C_45_L _PK_L_(0x1C, 0x45) ++#define REG_SC_BK1C_45_H _PK_H_(0x1C, 0x45) ++#define REG_SC_BK1C_46_L _PK_L_(0x1C, 0x46) ++#define REG_SC_BK1C_46_H _PK_H_(0x1C, 0x46) ++#define REG_SC_BK1C_47_L _PK_L_(0x1C, 0x47) ++#define REG_SC_BK1C_47_H _PK_H_(0x1C, 0x47) ++#define REG_SC_BK1C_48_L _PK_L_(0x1C, 0x48) ++#define REG_SC_BK1C_48_H _PK_H_(0x1C, 0x48) ++#define REG_SC_BK1C_49_L _PK_L_(0x1C, 0x49) ++#define REG_SC_BK1C_49_H _PK_H_(0x1C, 0x49) ++#define REG_SC_BK1C_4A_L _PK_L_(0x1C, 0x4A) ++#define REG_SC_BK1C_4A_H _PK_H_(0x1C, 0x4A) ++#define REG_SC_BK1C_4B_L _PK_L_(0x1C, 0x4B) ++#define REG_SC_BK1C_4B_H _PK_H_(0x1C, 0x4B) ++#define REG_SC_BK1C_4C_L _PK_L_(0x1C, 0x4C) ++#define REG_SC_BK1C_4C_H _PK_H_(0x1C, 0x4C) ++#define REG_SC_BK1C_4D_L _PK_L_(0x1C, 0x4D) ++#define REG_SC_BK1C_4D_H _PK_H_(0x1C, 0x4D) ++#define REG_SC_BK1C_4E_L _PK_L_(0x1C, 0x4E) ++#define REG_SC_BK1C_4E_H _PK_H_(0x1C, 0x4E) ++#define REG_SC_BK1C_4F_L _PK_L_(0x1C, 0x4F) ++#define REG_SC_BK1C_4F_H _PK_H_(0x1C, 0x4F) ++#define REG_SC_BK1C_50_L _PK_L_(0x1C, 0x50) ++#define REG_SC_BK1C_50_H _PK_H_(0x1C, 0x50) ++#define REG_SC_BK1C_51_L _PK_L_(0x1C, 0x51) ++#define REG_SC_BK1C_51_H _PK_H_(0x1C, 0x51) ++#define REG_SC_BK1C_52_L _PK_L_(0x1C, 0x52) ++#define REG_SC_BK1C_52_H _PK_H_(0x1C, 0x52) ++#define REG_SC_BK1C_53_L _PK_L_(0x1C, 0x53) ++#define REG_SC_BK1C_53_H _PK_H_(0x1C, 0x53) ++#define REG_SC_BK1C_54_L _PK_L_(0x1C, 0x54) ++#define REG_SC_BK1C_54_H _PK_H_(0x1C, 0x54) ++#define REG_SC_BK1C_55_L _PK_L_(0x1C, 0x55) ++#define REG_SC_BK1C_55_H _PK_H_(0x1C, 0x55) ++#define REG_SC_BK1C_56_L _PK_L_(0x1C, 0x56) ++#define REG_SC_BK1C_56_H _PK_H_(0x1C, 0x56) ++#define REG_SC_BK1C_57_L _PK_L_(0x1C, 0x57) ++#define REG_SC_BK1C_57_H _PK_H_(0x1C, 0x57) ++#define REG_SC_BK1C_58_L _PK_L_(0x1C, 0x58) ++#define REG_SC_BK1C_58_H _PK_H_(0x1C, 0x58) ++#define REG_SC_BK1C_59_L _PK_L_(0x1C, 0x59) ++#define REG_SC_BK1C_59_H _PK_H_(0x1C, 0x59) ++#define REG_SC_BK1C_5A_L _PK_L_(0x1C, 0x5A) ++#define REG_SC_BK1C_5A_H _PK_H_(0x1C, 0x5A) ++#define REG_SC_BK1C_5B_L _PK_L_(0x1C, 0x5B) ++#define REG_SC_BK1C_5B_H _PK_H_(0x1C, 0x5B) ++#define REG_SC_BK1C_5C_L _PK_L_(0x1C, 0x5C) ++#define REG_SC_BK1C_5C_H _PK_H_(0x1C, 0x5C) ++#define REG_SC_BK1C_5D_L _PK_L_(0x1C, 0x5D) ++#define REG_SC_BK1C_5D_H _PK_H_(0x1C, 0x5D) ++#define REG_SC_BK1C_5E_L _PK_L_(0x1C, 0x5E) ++#define REG_SC_BK1C_5E_H _PK_H_(0x1C, 0x5E) ++#define REG_SC_BK1C_5F_L _PK_L_(0x1C, 0x5F) ++#define REG_SC_BK1C_5F_H _PK_H_(0x1C, 0x5F) ++#define REG_SC_BK1C_60_L _PK_L_(0x1C, 0x60) ++#define REG_SC_BK1C_60_H _PK_H_(0x1C, 0x60) ++#define REG_SC_BK1C_61_L _PK_L_(0x1C, 0x61) ++#define REG_SC_BK1C_61_H _PK_H_(0x1C, 0x61) ++#define REG_SC_BK1C_62_L _PK_L_(0x1C, 0x62) ++#define REG_SC_BK1C_62_H _PK_H_(0x1C, 0x62) ++#define REG_SC_BK1C_63_L _PK_L_(0x1C, 0x63) ++#define REG_SC_BK1C_63_H _PK_H_(0x1C, 0x63) ++#define REG_SC_BK1C_64_L _PK_L_(0x1C, 0x64) ++#define REG_SC_BK1C_64_H _PK_H_(0x1C, 0x64) ++#define REG_SC_BK1C_65_L _PK_L_(0x1C, 0x65) ++#define REG_SC_BK1C_65_H _PK_H_(0x1C, 0x65) ++#define REG_SC_BK1C_66_L _PK_L_(0x1C, 0x66) ++#define REG_SC_BK1C_66_H _PK_H_(0x1C, 0x66) ++#define REG_SC_BK1C_67_L _PK_L_(0x1C, 0x67) ++#define REG_SC_BK1C_67_H _PK_H_(0x1C, 0x67) ++#define REG_SC_BK1C_68_L _PK_L_(0x1C, 0x68) ++#define REG_SC_BK1C_68_H _PK_H_(0x1C, 0x68) ++#define REG_SC_BK1C_69_L _PK_L_(0x1C, 0x69) ++#define REG_SC_BK1C_69_H _PK_H_(0x1C, 0x69) ++#define REG_SC_BK1C_6A_L _PK_L_(0x1C, 0x6A) ++#define REG_SC_BK1C_6A_H _PK_H_(0x1C, 0x6A) ++#define REG_SC_BK1C_6B_L _PK_L_(0x1C, 0x6B) ++#define REG_SC_BK1C_6B_H _PK_H_(0x1C, 0x6B) ++#define REG_SC_BK1C_6C_L _PK_L_(0x1C, 0x6C) ++#define REG_SC_BK1C_6C_H _PK_H_(0x1C, 0x6C) ++#define REG_SC_BK1C_6D_L _PK_L_(0x1C, 0x6D) ++#define REG_SC_BK1C_6D_H _PK_H_(0x1C, 0x6D) ++#define REG_SC_BK1C_6E_L _PK_L_(0x1C, 0x6E) ++#define REG_SC_BK1C_6E_H _PK_H_(0x1C, 0x6E) ++#define REG_SC_BK1C_6F_L _PK_L_(0x1C, 0x6F) ++#define REG_SC_BK1C_6F_H _PK_H_(0x1C, 0x6F) ++#define REG_SC_BK1C_70_L _PK_L_(0x1C, 0x70) ++#define REG_SC_BK1C_70_H _PK_H_(0x1C, 0x70) ++#define REG_SC_BK1C_71_L _PK_L_(0x1C, 0x71) ++#define REG_SC_BK1C_71_H _PK_H_(0x1C, 0x71) ++#define REG_SC_BK1C_72_L _PK_L_(0x1C, 0x72) ++#define REG_SC_BK1C_72_H _PK_H_(0x1C, 0x72) ++#define REG_SC_BK1C_73_L _PK_L_(0x1C, 0x73) ++#define REG_SC_BK1C_73_H _PK_H_(0x1C, 0x73) ++#define REG_SC_BK1C_74_L _PK_L_(0x1C, 0x74) ++#define REG_SC_BK1C_74_H _PK_H_(0x1C, 0x74) ++#define REG_SC_BK1C_75_L _PK_L_(0x1C, 0x75) ++#define REG_SC_BK1C_75_H _PK_H_(0x1C, 0x75) ++#define REG_SC_BK1C_76_L _PK_L_(0x1C, 0x76) ++#define REG_SC_BK1C_76_H _PK_H_(0x1C, 0x76) ++#define REG_SC_BK1C_77_L _PK_L_(0x1C, 0x77) ++#define REG_SC_BK1C_77_H _PK_H_(0x1C, 0x77) ++#define REG_SC_BK1C_78_L _PK_L_(0x1C, 0x78) ++#define REG_SC_BK1C_78_H _PK_H_(0x1C, 0x78) ++#define REG_SC_BK1C_79_L _PK_L_(0x1C, 0x79) ++#define REG_SC_BK1C_79_H _PK_H_(0x1C, 0x79) ++#define REG_SC_BK1C_7A_L _PK_L_(0x1C, 0x7A) ++#define REG_SC_BK1C_7A_H _PK_H_(0x1C, 0x7A) ++#define REG_SC_BK1C_7B_L _PK_L_(0x1C, 0x7B) ++#define REG_SC_BK1C_7B_H _PK_H_(0x1C, 0x7B) ++#define REG_SC_BK1C_7C_L _PK_L_(0x1C, 0x7C) ++#define REG_SC_BK1C_7C_H _PK_H_(0x1C, 0x7C) ++#define REG_SC_BK1C_7D_L _PK_L_(0x1C, 0x7D) ++#define REG_SC_BK1C_7D_H _PK_H_(0x1C, 0x7D) ++#define REG_SC_BK1C_7E_L _PK_L_(0x1C, 0x7E) ++#define REG_SC_BK1C_7E_H _PK_H_(0x1C, 0x7E) ++#define REG_SC_BK1C_7F_L _PK_L_(0x1C, 0x7F) ++#define REG_SC_BK1C_7F_H _PK_H_(0x1C, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1D_00_L _PK_L_(0x1D, 0x00) ++#define REG_SC_BK1D_00_H _PK_H_(0x1D, 0x00) ++#define REG_SC_BK1D_01_L _PK_L_(0x1D, 0x01) ++#define REG_SC_BK1D_01_H _PK_H_(0x1D, 0x01) ++#define REG_SC_BK1D_02_L _PK_L_(0x1D, 0x02) ++#define REG_SC_BK1D_02_H _PK_H_(0x1D, 0x02) ++#define REG_SC_BK1D_03_L _PK_L_(0x1D, 0x03) ++#define REG_SC_BK1D_03_H _PK_H_(0x1D, 0x03) ++#define REG_SC_BK1D_04_L _PK_L_(0x1D, 0x04) ++#define REG_SC_BK1D_04_H _PK_H_(0x1D, 0x04) ++#define REG_SC_BK1D_05_L _PK_L_(0x1D, 0x05) ++#define REG_SC_BK1D_05_H _PK_H_(0x1D, 0x05) ++#define REG_SC_BK1D_06_L _PK_L_(0x1D, 0x06) ++#define REG_SC_BK1D_06_H _PK_H_(0x1D, 0x06) ++#define REG_SC_BK1D_07_L _PK_L_(0x1D, 0x07) ++#define REG_SC_BK1D_07_H _PK_H_(0x1D, 0x07) ++#define REG_SC_BK1D_08_L _PK_L_(0x1D, 0x08) ++#define REG_SC_BK1D_08_H _PK_H_(0x1D, 0x08) ++#define REG_SC_BK1D_09_L _PK_L_(0x1D, 0x09) ++#define REG_SC_BK1D_09_H _PK_H_(0x1D, 0x09) ++#define REG_SC_BK1D_0A_L _PK_L_(0x1D, 0x0A) ++#define REG_SC_BK1D_0A_H _PK_H_(0x1D, 0x0A) ++#define REG_SC_BK1D_0B_L _PK_L_(0x1D, 0x0B) ++#define REG_SC_BK1D_0B_H _PK_H_(0x1D, 0x0B) ++#define REG_SC_BK1D_0C_L _PK_L_(0x1D, 0x0C) ++#define REG_SC_BK1D_0C_H _PK_H_(0x1D, 0x0C) ++#define REG_SC_BK1D_0D_L _PK_L_(0x1D, 0x0D) ++#define REG_SC_BK1D_0D_H _PK_H_(0x1D, 0x0D) ++#define REG_SC_BK1D_0E_L _PK_L_(0x1D, 0x0E) ++#define REG_SC_BK1D_0E_H _PK_H_(0x1D, 0x0E) ++#define REG_SC_BK1D_0F_L _PK_L_(0x1D, 0x0F) ++#define REG_SC_BK1D_0F_H _PK_H_(0x1D, 0x0F) ++#define REG_SC_BK1D_10_L _PK_L_(0x1D, 0x10) ++#define REG_SC_BK1D_10_H _PK_H_(0x1D, 0x10) ++#define REG_SC_BK1D_11_L _PK_L_(0x1D, 0x11) ++#define REG_SC_BK1D_11_H _PK_H_(0x1D, 0x11) ++#define REG_SC_BK1D_12_L _PK_L_(0x1D, 0x12) ++#define REG_SC_BK1D_12_H _PK_H_(0x1D, 0x12) ++#define REG_SC_BK1D_13_L _PK_L_(0x1D, 0x13) ++#define REG_SC_BK1D_13_H _PK_H_(0x1D, 0x13) ++#define REG_SC_BK1D_14_L _PK_L_(0x1D, 0x14) ++#define REG_SC_BK1D_14_H _PK_H_(0x1D, 0x14) ++#define REG_SC_BK1D_15_L _PK_L_(0x1D, 0x15) ++#define REG_SC_BK1D_15_H _PK_H_(0x1D, 0x15) ++#define REG_SC_BK1D_16_L _PK_L_(0x1D, 0x16) ++#define REG_SC_BK1D_16_H _PK_H_(0x1D, 0x16) ++#define REG_SC_BK1D_17_L _PK_L_(0x1D, 0x17) ++#define REG_SC_BK1D_17_H _PK_H_(0x1D, 0x17) ++#define REG_SC_BK1D_18_L _PK_L_(0x1D, 0x18) ++#define REG_SC_BK1D_18_H _PK_H_(0x1D, 0x18) ++#define REG_SC_BK1D_19_L _PK_L_(0x1D, 0x19) ++#define REG_SC_BK1D_19_H _PK_H_(0x1D, 0x19) ++#define REG_SC_BK1D_1A_L _PK_L_(0x1D, 0x1A) ++#define REG_SC_BK1D_1A_H _PK_H_(0x1D, 0x1A) ++#define REG_SC_BK1D_1B_L _PK_L_(0x1D, 0x1B) ++#define REG_SC_BK1D_1B_H _PK_H_(0x1D, 0x1B) ++#define REG_SC_BK1D_1C_L _PK_L_(0x1D, 0x1C) ++#define REG_SC_BK1D_1C_H _PK_H_(0x1D, 0x1C) ++#define REG_SC_BK1D_1D_L _PK_L_(0x1D, 0x1D) ++#define REG_SC_BK1D_1D_H _PK_H_(0x1D, 0x1D) ++#define REG_SC_BK1D_1E_L _PK_L_(0x1D, 0x1E) ++#define REG_SC_BK1D_1E_H _PK_H_(0x1D, 0x1E) ++#define REG_SC_BK1D_1F_L _PK_L_(0x1D, 0x1F) ++#define REG_SC_BK1D_1F_H _PK_H_(0x1D, 0x1F) ++#define REG_SC_BK1D_20_L _PK_L_(0x1D, 0x20) ++#define REG_SC_BK1D_20_H _PK_H_(0x1D, 0x20) ++#define REG_SC_BK1D_21_L _PK_L_(0x1D, 0x21) ++#define REG_SC_BK1D_21_H _PK_H_(0x1D, 0x21) ++#define REG_SC_BK1D_22_L _PK_L_(0x1D, 0x22) ++#define REG_SC_BK1D_22_H _PK_H_(0x1D, 0x22) ++#define REG_SC_BK1D_23_L _PK_L_(0x1D, 0x23) ++#define REG_SC_BK1D_23_H _PK_H_(0x1D, 0x23) ++#define REG_SC_BK1D_24_L _PK_L_(0x1D, 0x24) ++#define REG_SC_BK1D_24_H _PK_H_(0x1D, 0x24) ++#define REG_SC_BK1D_25_L _PK_L_(0x1D, 0x25) ++#define REG_SC_BK1D_25_H _PK_H_(0x1D, 0x25) ++#define REG_SC_BK1D_26_L _PK_L_(0x1D, 0x26) ++#define REG_SC_BK1D_26_H _PK_H_(0x1D, 0x26) ++#define REG_SC_BK1D_27_L _PK_L_(0x1D, 0x27) ++#define REG_SC_BK1D_27_H _PK_H_(0x1D, 0x27) ++#define REG_SC_BK1D_28_L _PK_L_(0x1D, 0x28) ++#define REG_SC_BK1D_28_H _PK_H_(0x1D, 0x28) ++#define REG_SC_BK1D_29_L _PK_L_(0x1D, 0x29) ++#define REG_SC_BK1D_29_H _PK_H_(0x1D, 0x29) ++#define REG_SC_BK1D_2A_L _PK_L_(0x1D, 0x2A) ++#define REG_SC_BK1D_2A_H _PK_H_(0x1D, 0x2A) ++#define REG_SC_BK1D_2B_L _PK_L_(0x1D, 0x2B) ++#define REG_SC_BK1D_2B_H _PK_H_(0x1D, 0x2B) ++#define REG_SC_BK1D_2C_L _PK_L_(0x1D, 0x2C) ++#define REG_SC_BK1D_2C_H _PK_H_(0x1D, 0x2C) ++#define REG_SC_BK1D_2D_L _PK_L_(0x1D, 0x2D) ++#define REG_SC_BK1D_2D_H _PK_H_(0x1D, 0x2D) ++#define REG_SC_BK1D_2E_L _PK_L_(0x1D, 0x2E) ++#define REG_SC_BK1D_2E_H _PK_H_(0x1D, 0x2E) ++#define REG_SC_BK1D_2F_L _PK_L_(0x1D, 0x2F) ++#define REG_SC_BK1D_2F_H _PK_H_(0x1D, 0x2F) ++#define REG_SC_BK1D_30_L _PK_L_(0x1D, 0x30) ++#define REG_SC_BK1D_30_H _PK_H_(0x1D, 0x30) ++#define REG_SC_BK1D_31_L _PK_L_(0x1D, 0x31) ++#define REG_SC_BK1D_31_H _PK_H_(0x1D, 0x31) ++#define REG_SC_BK1D_32_L _PK_L_(0x1D, 0x32) ++#define REG_SC_BK1D_32_H _PK_H_(0x1D, 0x32) ++#define REG_SC_BK1D_33_L _PK_L_(0x1D, 0x33) ++#define REG_SC_BK1D_33_H _PK_H_(0x1D, 0x33) ++#define REG_SC_BK1D_34_L _PK_L_(0x1D, 0x34) ++#define REG_SC_BK1D_34_H _PK_H_(0x1D, 0x34) ++#define REG_SC_BK1D_35_L _PK_L_(0x1D, 0x35) ++#define REG_SC_BK1D_35_H _PK_H_(0x1D, 0x35) ++#define REG_SC_BK1D_36_L _PK_L_(0x1D, 0x36) ++#define REG_SC_BK1D_36_H _PK_H_(0x1D, 0x36) ++#define REG_SC_BK1D_37_L _PK_L_(0x1D, 0x37) ++#define REG_SC_BK1D_37_H _PK_H_(0x1D, 0x37) ++#define REG_SC_BK1D_38_L _PK_L_(0x1D, 0x38) ++#define REG_SC_BK1D_38_H _PK_H_(0x1D, 0x38) ++#define REG_SC_BK1D_39_L _PK_L_(0x1D, 0x39) ++#define REG_SC_BK1D_39_H _PK_H_(0x1D, 0x39) ++#define REG_SC_BK1D_3A_L _PK_L_(0x1D, 0x3A) ++#define REG_SC_BK1D_3A_H _PK_H_(0x1D, 0x3A) ++#define REG_SC_BK1D_3B_L _PK_L_(0x1D, 0x3B) ++#define REG_SC_BK1D_3B_H _PK_H_(0x1D, 0x3B) ++#define REG_SC_BK1D_3C_L _PK_L_(0x1D, 0x3C) ++#define REG_SC_BK1D_3C_H _PK_H_(0x1D, 0x3C) ++#define REG_SC_BK1D_3D_L _PK_L_(0x1D, 0x3D) ++#define REG_SC_BK1D_3D_H _PK_H_(0x1D, 0x3D) ++#define REG_SC_BK1D_3E_L _PK_L_(0x1D, 0x3E) ++#define REG_SC_BK1D_3E_H _PK_H_(0x1D, 0x3E) ++#define REG_SC_BK1D_3F_L _PK_L_(0x1D, 0x3F) ++#define REG_SC_BK1D_3F_H _PK_H_(0x1D, 0x3F) ++#define REG_SC_BK1D_40_L _PK_L_(0x1D, 0x40) ++#define REG_SC_BK1D_40_H _PK_H_(0x1D, 0x40) ++#define REG_SC_BK1D_41_L _PK_L_(0x1D, 0x41) ++#define REG_SC_BK1D_41_H _PK_H_(0x1D, 0x41) ++#define REG_SC_BK1D_42_L _PK_L_(0x1D, 0x42) ++#define REG_SC_BK1D_42_H _PK_H_(0x1D, 0x42) ++#define REG_SC_BK1D_43_L _PK_L_(0x1D, 0x43) ++#define REG_SC_BK1D_43_H _PK_H_(0x1D, 0x43) ++#define REG_SC_BK1D_44_L _PK_L_(0x1D, 0x44) ++#define REG_SC_BK1D_44_H _PK_H_(0x1D, 0x44) ++#define REG_SC_BK1D_45_L _PK_L_(0x1D, 0x45) ++#define REG_SC_BK1D_45_H _PK_H_(0x1D, 0x45) ++#define REG_SC_BK1D_46_L _PK_L_(0x1D, 0x46) ++#define REG_SC_BK1D_46_H _PK_H_(0x1D, 0x46) ++#define REG_SC_BK1D_47_L _PK_L_(0x1D, 0x47) ++#define REG_SC_BK1D_47_H _PK_H_(0x1D, 0x47) ++#define REG_SC_BK1D_48_L _PK_L_(0x1D, 0x48) ++#define REG_SC_BK1D_48_H _PK_H_(0x1D, 0x48) ++#define REG_SC_BK1D_49_L _PK_L_(0x1D, 0x49) ++#define REG_SC_BK1D_49_H _PK_H_(0x1D, 0x49) ++#define REG_SC_BK1D_4A_L _PK_L_(0x1D, 0x4A) ++#define REG_SC_BK1D_4A_H _PK_H_(0x1D, 0x4A) ++#define REG_SC_BK1D_4B_L _PK_L_(0x1D, 0x4B) ++#define REG_SC_BK1D_4B_H _PK_H_(0x1D, 0x4B) ++#define REG_SC_BK1D_4C_L _PK_L_(0x1D, 0x4C) ++#define REG_SC_BK1D_4C_H _PK_H_(0x1D, 0x4C) ++#define REG_SC_BK1D_4D_L _PK_L_(0x1D, 0x4D) ++#define REG_SC_BK1D_4D_H _PK_H_(0x1D, 0x4D) ++#define REG_SC_BK1D_4E_L _PK_L_(0x1D, 0x4E) ++#define REG_SC_BK1D_4E_H _PK_H_(0x1D, 0x4E) ++#define REG_SC_BK1D_4F_L _PK_L_(0x1D, 0x4F) ++#define REG_SC_BK1D_4F_H _PK_H_(0x1D, 0x4F) ++#define REG_SC_BK1D_50_L _PK_L_(0x1D, 0x50) ++#define REG_SC_BK1D_50_H _PK_H_(0x1D, 0x50) ++#define REG_SC_BK1D_51_L _PK_L_(0x1D, 0x51) ++#define REG_SC_BK1D_51_H _PK_H_(0x1D, 0x51) ++#define REG_SC_BK1D_52_L _PK_L_(0x1D, 0x52) ++#define REG_SC_BK1D_52_H _PK_H_(0x1D, 0x52) ++#define REG_SC_BK1D_53_L _PK_L_(0x1D, 0x53) ++#define REG_SC_BK1D_53_H _PK_H_(0x1D, 0x53) ++#define REG_SC_BK1D_54_L _PK_L_(0x1D, 0x54) ++#define REG_SC_BK1D_54_H _PK_H_(0x1D, 0x54) ++#define REG_SC_BK1D_55_L _PK_L_(0x1D, 0x55) ++#define REG_SC_BK1D_55_H _PK_H_(0x1D, 0x55) ++#define REG_SC_BK1D_56_L _PK_L_(0x1D, 0x56) ++#define REG_SC_BK1D_56_H _PK_H_(0x1D, 0x56) ++#define REG_SC_BK1D_57_L _PK_L_(0x1D, 0x57) ++#define REG_SC_BK1D_57_H _PK_H_(0x1D, 0x57) ++#define REG_SC_BK1D_58_L _PK_L_(0x1D, 0x58) ++#define REG_SC_BK1D_58_H _PK_H_(0x1D, 0x58) ++#define REG_SC_BK1D_59_L _PK_L_(0x1D, 0x59) ++#define REG_SC_BK1D_59_H _PK_H_(0x1D, 0x59) ++#define REG_SC_BK1D_5A_L _PK_L_(0x1D, 0x5A) ++#define REG_SC_BK1D_5A_H _PK_H_(0x1D, 0x5A) ++#define REG_SC_BK1D_5B_L _PK_L_(0x1D, 0x5B) ++#define REG_SC_BK1D_5B_H _PK_H_(0x1D, 0x5B) ++#define REG_SC_BK1D_5C_L _PK_L_(0x1D, 0x5C) ++#define REG_SC_BK1D_5C_H _PK_H_(0x1D, 0x5C) ++#define REG_SC_BK1D_5D_L _PK_L_(0x1D, 0x5D) ++#define REG_SC_BK1D_5D_H _PK_H_(0x1D, 0x5D) ++#define REG_SC_BK1D_5E_L _PK_L_(0x1D, 0x5E) ++#define REG_SC_BK1D_5E_H _PK_H_(0x1D, 0x5E) ++#define REG_SC_BK1D_5F_L _PK_L_(0x1D, 0x5F) ++#define REG_SC_BK1D_5F_H _PK_H_(0x1D, 0x5F) ++#define REG_SC_BK1D_60_L _PK_L_(0x1D, 0x60) ++#define REG_SC_BK1D_60_H _PK_H_(0x1D, 0x60) ++#define REG_SC_BK1D_61_L _PK_L_(0x1D, 0x61) ++#define REG_SC_BK1D_61_H _PK_H_(0x1D, 0x61) ++#define REG_SC_BK1D_62_L _PK_L_(0x1D, 0x62) ++#define REG_SC_BK1D_62_H _PK_H_(0x1D, 0x62) ++#define REG_SC_BK1D_63_L _PK_L_(0x1D, 0x63) ++#define REG_SC_BK1D_63_H _PK_H_(0x1D, 0x63) ++#define REG_SC_BK1D_64_L _PK_L_(0x1D, 0x64) ++#define REG_SC_BK1D_64_H _PK_H_(0x1D, 0x64) ++#define REG_SC_BK1D_65_L _PK_L_(0x1D, 0x65) ++#define REG_SC_BK1D_65_H _PK_H_(0x1D, 0x65) ++#define REG_SC_BK1D_66_L _PK_L_(0x1D, 0x66) ++#define REG_SC_BK1D_66_H _PK_H_(0x1D, 0x66) ++#define REG_SC_BK1D_67_L _PK_L_(0x1D, 0x67) ++#define REG_SC_BK1D_67_H _PK_H_(0x1D, 0x67) ++#define REG_SC_BK1D_68_L _PK_L_(0x1D, 0x68) ++#define REG_SC_BK1D_68_H _PK_H_(0x1D, 0x68) ++#define REG_SC_BK1D_69_L _PK_L_(0x1D, 0x69) ++#define REG_SC_BK1D_69_H _PK_H_(0x1D, 0x69) ++#define REG_SC_BK1D_6A_L _PK_L_(0x1D, 0x6A) ++#define REG_SC_BK1D_6A_H _PK_H_(0x1D, 0x6A) ++#define REG_SC_BK1D_6B_L _PK_L_(0x1D, 0x6B) ++#define REG_SC_BK1D_6B_H _PK_H_(0x1D, 0x6B) ++#define REG_SC_BK1D_6C_L _PK_L_(0x1D, 0x6C) ++#define REG_SC_BK1D_6C_H _PK_H_(0x1D, 0x6C) ++#define REG_SC_BK1D_6D_L _PK_L_(0x1D, 0x6D) ++#define REG_SC_BK1D_6D_H _PK_H_(0x1D, 0x6D) ++#define REG_SC_BK1D_6E_L _PK_L_(0x1D, 0x6E) ++#define REG_SC_BK1D_6E_H _PK_H_(0x1D, 0x6E) ++#define REG_SC_BK1D_6F_L _PK_L_(0x1D, 0x6F) ++#define REG_SC_BK1D_6F_H _PK_H_(0x1D, 0x6F) ++#define REG_SC_BK1D_70_L _PK_L_(0x1D, 0x70) ++#define REG_SC_BK1D_70_H _PK_H_(0x1D, 0x70) ++#define REG_SC_BK1D_71_L _PK_L_(0x1D, 0x71) ++#define REG_SC_BK1D_71_H _PK_H_(0x1D, 0x71) ++#define REG_SC_BK1D_72_L _PK_L_(0x1D, 0x72) ++#define REG_SC_BK1D_72_H _PK_H_(0x1D, 0x72) ++#define REG_SC_BK1D_73_L _PK_L_(0x1D, 0x73) ++#define REG_SC_BK1D_73_H _PK_H_(0x1D, 0x73) ++#define REG_SC_BK1D_74_L _PK_L_(0x1D, 0x74) ++#define REG_SC_BK1D_74_H _PK_H_(0x1D, 0x74) ++#define REG_SC_BK1D_75_L _PK_L_(0x1D, 0x75) ++#define REG_SC_BK1D_75_H _PK_H_(0x1D, 0x75) ++#define REG_SC_BK1D_76_L _PK_L_(0x1D, 0x76) ++#define REG_SC_BK1D_76_H _PK_H_(0x1D, 0x76) ++#define REG_SC_BK1D_77_L _PK_L_(0x1D, 0x77) ++#define REG_SC_BK1D_77_H _PK_H_(0x1D, 0x77) ++#define REG_SC_BK1D_78_L _PK_L_(0x1D, 0x78) ++#define REG_SC_BK1D_78_H _PK_H_(0x1D, 0x78) ++#define REG_SC_BK1D_79_L _PK_L_(0x1D, 0x79) ++#define REG_SC_BK1D_79_H _PK_H_(0x1D, 0x79) ++#define REG_SC_BK1D_7A_L _PK_L_(0x1D, 0x7A) ++#define REG_SC_BK1D_7A_H _PK_H_(0x1D, 0x7A) ++#define REG_SC_BK1D_7B_L _PK_L_(0x1D, 0x7B) ++#define REG_SC_BK1D_7B_H _PK_H_(0x1D, 0x7B) ++#define REG_SC_BK1D_7C_L _PK_L_(0x1D, 0x7C) ++#define REG_SC_BK1D_7C_H _PK_H_(0x1D, 0x7C) ++#define REG_SC_BK1D_7D_L _PK_L_(0x1D, 0x7D) ++#define REG_SC_BK1D_7D_H _PK_H_(0x1D, 0x7D) ++#define REG_SC_BK1D_7E_L _PK_L_(0x1D, 0x7E) ++#define REG_SC_BK1D_7E_H _PK_H_(0x1D, 0x7E) ++#define REG_SC_BK1D_7F_L _PK_L_(0x1D, 0x7F) ++#define REG_SC_BK1D_7F_H _PK_H_(0x1D, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1E_00_L _PK_L_(0x1E, 0x00) ++#define REG_SC_BK1E_00_H _PK_H_(0x1E, 0x00) ++#define REG_SC_BK1E_01_L _PK_L_(0x1E, 0x01) ++#define REG_SC_BK1E_01_H _PK_H_(0x1E, 0x01) ++#define REG_SC_BK1E_02_L _PK_L_(0x1E, 0x02) ++#define REG_SC_BK1E_02_H _PK_H_(0x1E, 0x02) ++#define REG_SC_BK1E_03_L _PK_L_(0x1E, 0x03) ++#define REG_SC_BK1E_03_H _PK_H_(0x1E, 0x03) ++#define REG_SC_BK1E_04_L _PK_L_(0x1E, 0x04) ++#define REG_SC_BK1E_04_H _PK_H_(0x1E, 0x04) ++#define REG_SC_BK1E_05_L _PK_L_(0x1E, 0x05) ++#define REG_SC_BK1E_05_H _PK_H_(0x1E, 0x05) ++#define REG_SC_BK1E_06_L _PK_L_(0x1E, 0x06) ++#define REG_SC_BK1E_06_H _PK_H_(0x1E, 0x06) ++#define REG_SC_BK1E_07_L _PK_L_(0x1E, 0x07) ++#define REG_SC_BK1E_07_H _PK_H_(0x1E, 0x07) ++#define REG_SC_BK1E_08_L _PK_L_(0x1E, 0x08) ++#define REG_SC_BK1E_08_H _PK_H_(0x1E, 0x08) ++#define REG_SC_BK1E_09_L _PK_L_(0x1E, 0x09) ++#define REG_SC_BK1E_09_H _PK_H_(0x1E, 0x09) ++#define REG_SC_BK1E_0A_L _PK_L_(0x1E, 0x0A) ++#define REG_SC_BK1E_0A_H _PK_H_(0x1E, 0x0A) ++#define REG_SC_BK1E_0B_L _PK_L_(0x1E, 0x0B) ++#define REG_SC_BK1E_0B_H _PK_H_(0x1E, 0x0B) ++#define REG_SC_BK1E_0C_L _PK_L_(0x1E, 0x0C) ++#define REG_SC_BK1E_0C_H _PK_H_(0x1E, 0x0C) ++#define REG_SC_BK1E_0D_L _PK_L_(0x1E, 0x0D) ++#define REG_SC_BK1E_0D_H _PK_H_(0x1E, 0x0D) ++#define REG_SC_BK1E_0E_L _PK_L_(0x1E, 0x0E) ++#define REG_SC_BK1E_0E_H _PK_H_(0x1E, 0x0E) ++#define REG_SC_BK1E_0F_L _PK_L_(0x1E, 0x0F) ++#define REG_SC_BK1E_0F_H _PK_H_(0x1E, 0x0F) ++#define REG_SC_BK1E_10_L _PK_L_(0x1E, 0x10) ++#define REG_SC_BK1E_10_H _PK_H_(0x1E, 0x10) ++#define REG_SC_BK1E_11_L _PK_L_(0x1E, 0x11) ++#define REG_SC_BK1E_11_H _PK_H_(0x1E, 0x11) ++#define REG_SC_BK1E_12_L _PK_L_(0x1E, 0x12) ++#define REG_SC_BK1E_12_H _PK_H_(0x1E, 0x12) ++#define REG_SC_BK1E_13_L _PK_L_(0x1E, 0x13) ++#define REG_SC_BK1E_13_H _PK_H_(0x1E, 0x13) ++#define REG_SC_BK1E_14_L _PK_L_(0x1E, 0x14) ++#define REG_SC_BK1E_14_H _PK_H_(0x1E, 0x14) ++#define REG_SC_BK1E_15_L _PK_L_(0x1E, 0x15) ++#define REG_SC_BK1E_15_H _PK_H_(0x1E, 0x15) ++#define REG_SC_BK1E_16_L _PK_L_(0x1E, 0x16) ++#define REG_SC_BK1E_16_H _PK_H_(0x1E, 0x16) ++#define REG_SC_BK1E_17_L _PK_L_(0x1E, 0x17) ++#define REG_SC_BK1E_17_H _PK_H_(0x1E, 0x17) ++#define REG_SC_BK1E_18_L _PK_L_(0x1E, 0x18) ++#define REG_SC_BK1E_18_H _PK_H_(0x1E, 0x18) ++#define REG_SC_BK1E_19_L _PK_L_(0x1E, 0x19) ++#define REG_SC_BK1E_19_H _PK_H_(0x1E, 0x19) ++#define REG_SC_BK1E_1A_L _PK_L_(0x1E, 0x1A) ++#define REG_SC_BK1E_1A_H _PK_H_(0x1E, 0x1A) ++#define REG_SC_BK1E_1B_L _PK_L_(0x1E, 0x1B) ++#define REG_SC_BK1E_1B_H _PK_H_(0x1E, 0x1B) ++#define REG_SC_BK1E_1C_L _PK_L_(0x1E, 0x1C) ++#define REG_SC_BK1E_1C_H _PK_H_(0x1E, 0x1C) ++#define REG_SC_BK1E_1D_L _PK_L_(0x1E, 0x1D) ++#define REG_SC_BK1E_1D_H _PK_H_(0x1E, 0x1D) ++#define REG_SC_BK1E_1E_L _PK_L_(0x1E, 0x1E) ++#define REG_SC_BK1E_1E_H _PK_H_(0x1E, 0x1E) ++#define REG_SC_BK1E_1F_L _PK_L_(0x1E, 0x1F) ++#define REG_SC_BK1E_1F_H _PK_H_(0x1E, 0x1F) ++#define REG_SC_BK1E_20_L _PK_L_(0x1E, 0x20) ++#define REG_SC_BK1E_20_H _PK_H_(0x1E, 0x20) ++#define REG_SC_BK1E_21_L _PK_L_(0x1E, 0x21) ++#define REG_SC_BK1E_21_H _PK_H_(0x1E, 0x21) ++#define REG_SC_BK1E_22_L _PK_L_(0x1E, 0x22) ++#define REG_SC_BK1E_22_H _PK_H_(0x1E, 0x22) ++#define REG_SC_BK1E_23_L _PK_L_(0x1E, 0x23) ++#define REG_SC_BK1E_23_H _PK_H_(0x1E, 0x23) ++#define REG_SC_BK1E_24_L _PK_L_(0x1E, 0x24) ++#define REG_SC_BK1E_24_H _PK_H_(0x1E, 0x24) ++#define REG_SC_BK1E_25_L _PK_L_(0x1E, 0x25) ++#define REG_SC_BK1E_25_H _PK_H_(0x1E, 0x25) ++#define REG_SC_BK1E_26_L _PK_L_(0x1E, 0x26) ++#define REG_SC_BK1E_26_H _PK_H_(0x1E, 0x26) ++#define REG_SC_BK1E_27_L _PK_L_(0x1E, 0x27) ++#define REG_SC_BK1E_27_H _PK_H_(0x1E, 0x27) ++#define REG_SC_BK1E_28_L _PK_L_(0x1E, 0x28) ++#define REG_SC_BK1E_28_H _PK_H_(0x1E, 0x28) ++#define REG_SC_BK1E_29_L _PK_L_(0x1E, 0x29) ++#define REG_SC_BK1E_29_H _PK_H_(0x1E, 0x29) ++#define REG_SC_BK1E_2A_L _PK_L_(0x1E, 0x2A) ++#define REG_SC_BK1E_2A_H _PK_H_(0x1E, 0x2A) ++#define REG_SC_BK1E_2B_L _PK_L_(0x1E, 0x2B) ++#define REG_SC_BK1E_2B_H _PK_H_(0x1E, 0x2B) ++#define REG_SC_BK1E_2C_L _PK_L_(0x1E, 0x2C) ++#define REG_SC_BK1E_2C_H _PK_H_(0x1E, 0x2C) ++#define REG_SC_BK1E_2D_L _PK_L_(0x1E, 0x2D) ++#define REG_SC_BK1E_2D_H _PK_H_(0x1E, 0x2D) ++#define REG_SC_BK1E_2E_L _PK_L_(0x1E, 0x2E) ++#define REG_SC_BK1E_2E_H _PK_H_(0x1E, 0x2E) ++#define REG_SC_BK1E_2F_L _PK_L_(0x1E, 0x2F) ++#define REG_SC_BK1E_2F_H _PK_H_(0x1E, 0x2F) ++#define REG_SC_BK1E_30_L _PK_L_(0x1E, 0x30) ++#define REG_SC_BK1E_30_H _PK_H_(0x1E, 0x30) ++#define REG_SC_BK1E_31_L _PK_L_(0x1E, 0x31) ++#define REG_SC_BK1E_31_H _PK_H_(0x1E, 0x31) ++#define REG_SC_BK1E_32_L _PK_L_(0x1E, 0x32) ++#define REG_SC_BK1E_32_H _PK_H_(0x1E, 0x32) ++#define REG_SC_BK1E_33_L _PK_L_(0x1E, 0x33) ++#define REG_SC_BK1E_33_H _PK_H_(0x1E, 0x33) ++#define REG_SC_BK1E_34_L _PK_L_(0x1E, 0x34) ++#define REG_SC_BK1E_34_H _PK_H_(0x1E, 0x34) ++#define REG_SC_BK1E_35_L _PK_L_(0x1E, 0x35) ++#define REG_SC_BK1E_35_H _PK_H_(0x1E, 0x35) ++#define REG_SC_BK1E_36_L _PK_L_(0x1E, 0x36) ++#define REG_SC_BK1E_36_H _PK_H_(0x1E, 0x36) ++#define REG_SC_BK1E_37_L _PK_L_(0x1E, 0x37) ++#define REG_SC_BK1E_37_H _PK_H_(0x1E, 0x37) ++#define REG_SC_BK1E_38_L _PK_L_(0x1E, 0x38) ++#define REG_SC_BK1E_38_H _PK_H_(0x1E, 0x38) ++#define REG_SC_BK1E_39_L _PK_L_(0x1E, 0x39) ++#define REG_SC_BK1E_39_H _PK_H_(0x1E, 0x39) ++#define REG_SC_BK1E_3A_L _PK_L_(0x1E, 0x3A) ++#define REG_SC_BK1E_3A_H _PK_H_(0x1E, 0x3A) ++#define REG_SC_BK1E_3B_L _PK_L_(0x1E, 0x3B) ++#define REG_SC_BK1E_3B_H _PK_H_(0x1E, 0x3B) ++#define REG_SC_BK1E_3C_L _PK_L_(0x1E, 0x3C) ++#define REG_SC_BK1E_3C_H _PK_H_(0x1E, 0x3C) ++#define REG_SC_BK1E_3D_L _PK_L_(0x1E, 0x3D) ++#define REG_SC_BK1E_3D_H _PK_H_(0x1E, 0x3D) ++#define REG_SC_BK1E_3E_L _PK_L_(0x1E, 0x3E) ++#define REG_SC_BK1E_3E_H _PK_H_(0x1E, 0x3E) ++#define REG_SC_BK1E_3F_L _PK_L_(0x1E, 0x3F) ++#define REG_SC_BK1E_3F_H _PK_H_(0x1E, 0x3F) ++#define REG_SC_BK1E_40_L _PK_L_(0x1E, 0x40) ++#define REG_SC_BK1E_40_H _PK_H_(0x1E, 0x40) ++#define REG_SC_BK1E_41_L _PK_L_(0x1E, 0x41) ++#define REG_SC_BK1E_41_H _PK_H_(0x1E, 0x41) ++#define REG_SC_BK1E_42_L _PK_L_(0x1E, 0x42) ++#define REG_SC_BK1E_42_H _PK_H_(0x1E, 0x42) ++#define REG_SC_BK1E_43_L _PK_L_(0x1E, 0x43) ++#define REG_SC_BK1E_43_H _PK_H_(0x1E, 0x43) ++#define REG_SC_BK1E_44_L _PK_L_(0x1E, 0x44) ++#define REG_SC_BK1E_44_H _PK_H_(0x1E, 0x44) ++#define REG_SC_BK1E_45_L _PK_L_(0x1E, 0x45) ++#define REG_SC_BK1E_45_H _PK_H_(0x1E, 0x45) ++#define REG_SC_BK1E_46_L _PK_L_(0x1E, 0x46) ++#define REG_SC_BK1E_46_H _PK_H_(0x1E, 0x46) ++#define REG_SC_BK1E_47_L _PK_L_(0x1E, 0x47) ++#define REG_SC_BK1E_47_H _PK_H_(0x1E, 0x47) ++#define REG_SC_BK1E_48_L _PK_L_(0x1E, 0x48) ++#define REG_SC_BK1E_48_H _PK_H_(0x1E, 0x48) ++#define REG_SC_BK1E_49_L _PK_L_(0x1E, 0x49) ++#define REG_SC_BK1E_49_H _PK_H_(0x1E, 0x49) ++#define REG_SC_BK1E_4A_L _PK_L_(0x1E, 0x4A) ++#define REG_SC_BK1E_4A_H _PK_H_(0x1E, 0x4A) ++#define REG_SC_BK1E_4B_L _PK_L_(0x1E, 0x4B) ++#define REG_SC_BK1E_4B_H _PK_H_(0x1E, 0x4B) ++#define REG_SC_BK1E_4C_L _PK_L_(0x1E, 0x4C) ++#define REG_SC_BK1E_4C_H _PK_H_(0x1E, 0x4C) ++#define REG_SC_BK1E_4D_L _PK_L_(0x1E, 0x4D) ++#define REG_SC_BK1E_4D_H _PK_H_(0x1E, 0x4D) ++#define REG_SC_BK1E_4E_L _PK_L_(0x1E, 0x4E) ++#define REG_SC_BK1E_4E_H _PK_H_(0x1E, 0x4E) ++#define REG_SC_BK1E_4F_L _PK_L_(0x1E, 0x4F) ++#define REG_SC_BK1E_4F_H _PK_H_(0x1E, 0x4F) ++#define REG_SC_BK1E_50_L _PK_L_(0x1E, 0x50) ++#define REG_SC_BK1E_50_H _PK_H_(0x1E, 0x50) ++#define REG_SC_BK1E_51_L _PK_L_(0x1E, 0x51) ++#define REG_SC_BK1E_51_H _PK_H_(0x1E, 0x51) ++#define REG_SC_BK1E_52_L _PK_L_(0x1E, 0x52) ++#define REG_SC_BK1E_52_H _PK_H_(0x1E, 0x52) ++#define REG_SC_BK1E_53_L _PK_L_(0x1E, 0x53) ++#define REG_SC_BK1E_53_H _PK_H_(0x1E, 0x53) ++#define REG_SC_BK1E_54_L _PK_L_(0x1E, 0x54) ++#define REG_SC_BK1E_54_H _PK_H_(0x1E, 0x54) ++#define REG_SC_BK1E_55_L _PK_L_(0x1E, 0x55) ++#define REG_SC_BK1E_55_H _PK_H_(0x1E, 0x55) ++#define REG_SC_BK1E_56_L _PK_L_(0x1E, 0x56) ++#define REG_SC_BK1E_56_H _PK_H_(0x1E, 0x56) ++#define REG_SC_BK1E_57_L _PK_L_(0x1E, 0x57) ++#define REG_SC_BK1E_57_H _PK_H_(0x1E, 0x57) ++#define REG_SC_BK1E_58_L _PK_L_(0x1E, 0x58) ++#define REG_SC_BK1E_58_H _PK_H_(0x1E, 0x58) ++#define REG_SC_BK1E_59_L _PK_L_(0x1E, 0x59) ++#define REG_SC_BK1E_59_H _PK_H_(0x1E, 0x59) ++#define REG_SC_BK1E_5A_L _PK_L_(0x1E, 0x5A) ++#define REG_SC_BK1E_5A_H _PK_H_(0x1E, 0x5A) ++#define REG_SC_BK1E_5B_L _PK_L_(0x1E, 0x5B) ++#define REG_SC_BK1E_5B_H _PK_H_(0x1E, 0x5B) ++#define REG_SC_BK1E_5C_L _PK_L_(0x1E, 0x5C) ++#define REG_SC_BK1E_5C_H _PK_H_(0x1E, 0x5C) ++#define REG_SC_BK1E_5D_L _PK_L_(0x1E, 0x5D) ++#define REG_SC_BK1E_5D_H _PK_H_(0x1E, 0x5D) ++#define REG_SC_BK1E_5E_L _PK_L_(0x1E, 0x5E) ++#define REG_SC_BK1E_5E_H _PK_H_(0x1E, 0x5E) ++#define REG_SC_BK1E_5F_L _PK_L_(0x1E, 0x5F) ++#define REG_SC_BK1E_5F_H _PK_H_(0x1E, 0x5F) ++#define REG_SC_BK1E_60_L _PK_L_(0x1E, 0x60) ++#define REG_SC_BK1E_60_H _PK_H_(0x1E, 0x60) ++#define REG_SC_BK1E_61_L _PK_L_(0x1E, 0x61) ++#define REG_SC_BK1E_61_H _PK_H_(0x1E, 0x61) ++#define REG_SC_BK1E_62_L _PK_L_(0x1E, 0x62) ++#define REG_SC_BK1E_62_H _PK_H_(0x1E, 0x62) ++#define REG_SC_BK1E_63_L _PK_L_(0x1E, 0x63) ++#define REG_SC_BK1E_63_H _PK_H_(0x1E, 0x63) ++#define REG_SC_BK1E_64_L _PK_L_(0x1E, 0x64) ++#define REG_SC_BK1E_64_H _PK_H_(0x1E, 0x64) ++#define REG_SC_BK1E_65_L _PK_L_(0x1E, 0x65) ++#define REG_SC_BK1E_65_H _PK_H_(0x1E, 0x65) ++#define REG_SC_BK1E_66_L _PK_L_(0x1E, 0x66) ++#define REG_SC_BK1E_66_H _PK_H_(0x1E, 0x66) ++#define REG_SC_BK1E_67_L _PK_L_(0x1E, 0x67) ++#define REG_SC_BK1E_67_H _PK_H_(0x1E, 0x67) ++#define REG_SC_BK1E_68_L _PK_L_(0x1E, 0x68) ++#define REG_SC_BK1E_68_H _PK_H_(0x1E, 0x68) ++#define REG_SC_BK1E_69_L _PK_L_(0x1E, 0x69) ++#define REG_SC_BK1E_69_H _PK_H_(0x1E, 0x69) ++#define REG_SC_BK1E_6A_L _PK_L_(0x1E, 0x6A) ++#define REG_SC_BK1E_6A_H _PK_H_(0x1E, 0x6A) ++#define REG_SC_BK1E_6B_L _PK_L_(0x1E, 0x6B) ++#define REG_SC_BK1E_6B_H _PK_H_(0x1E, 0x6B) ++#define REG_SC_BK1E_6C_L _PK_L_(0x1E, 0x6C) ++#define REG_SC_BK1E_6C_H _PK_H_(0x1E, 0x6C) ++#define REG_SC_BK1E_6D_L _PK_L_(0x1E, 0x6D) ++#define REG_SC_BK1E_6D_H _PK_H_(0x1E, 0x6D) ++#define REG_SC_BK1E_6E_L _PK_L_(0x1E, 0x6E) ++#define REG_SC_BK1E_6E_H _PK_H_(0x1E, 0x6E) ++#define REG_SC_BK1E_6F_L _PK_L_(0x1E, 0x6F) ++#define REG_SC_BK1E_6F_H _PK_H_(0x1E, 0x6F) ++#define REG_SC_BK1E_70_L _PK_L_(0x1E, 0x70) ++#define REG_SC_BK1E_70_H _PK_H_(0x1E, 0x70) ++#define REG_SC_BK1E_71_L _PK_L_(0x1E, 0x71) ++#define REG_SC_BK1E_71_H _PK_H_(0x1E, 0x71) ++#define REG_SC_BK1E_72_L _PK_L_(0x1E, 0x72) ++#define REG_SC_BK1E_72_H _PK_H_(0x1E, 0x72) ++#define REG_SC_BK1E_73_L _PK_L_(0x1E, 0x73) ++#define REG_SC_BK1E_73_H _PK_H_(0x1E, 0x73) ++#define REG_SC_BK1E_74_L _PK_L_(0x1E, 0x74) ++#define REG_SC_BK1E_74_H _PK_H_(0x1E, 0x74) ++#define REG_SC_BK1E_75_L _PK_L_(0x1E, 0x75) ++#define REG_SC_BK1E_75_H _PK_H_(0x1E, 0x75) ++#define REG_SC_BK1E_76_L _PK_L_(0x1E, 0x76) ++#define REG_SC_BK1E_76_H _PK_H_(0x1E, 0x76) ++#define REG_SC_BK1E_77_L _PK_L_(0x1E, 0x77) ++#define REG_SC_BK1E_77_H _PK_H_(0x1E, 0x77) ++#define REG_SC_BK1E_78_L _PK_L_(0x1E, 0x78) ++#define REG_SC_BK1E_78_H _PK_H_(0x1E, 0x78) ++#define REG_SC_BK1E_79_L _PK_L_(0x1E, 0x79) ++#define REG_SC_BK1E_79_H _PK_H_(0x1E, 0x79) ++#define REG_SC_BK1E_7A_L _PK_L_(0x1E, 0x7A) ++#define REG_SC_BK1E_7A_H _PK_H_(0x1E, 0x7A) ++#define REG_SC_BK1E_7B_L _PK_L_(0x1E, 0x7B) ++#define REG_SC_BK1E_7B_H _PK_H_(0x1E, 0x7B) ++#define REG_SC_BK1E_7C_L _PK_L_(0x1E, 0x7C) ++#define REG_SC_BK1E_7C_H _PK_H_(0x1E, 0x7C) ++#define REG_SC_BK1E_7D_L _PK_L_(0x1E, 0x7D) ++#define REG_SC_BK1E_7D_H _PK_H_(0x1E, 0x7D) ++#define REG_SC_BK1E_7E_L _PK_L_(0x1E, 0x7E) ++#define REG_SC_BK1E_7E_H _PK_H_(0x1E, 0x7E) ++#define REG_SC_BK1E_7F_L _PK_L_(0x1E, 0x7F) ++#define REG_SC_BK1E_7F_H _PK_H_(0x1E, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK1F_00_L _PK_L_(0x1F, 0x00) ++#define REG_SC_BK1F_00_H _PK_H_(0x1F, 0x00) ++#define REG_SC_BK1F_01_L _PK_L_(0x1F, 0x01) ++#define REG_SC_BK1F_01_H _PK_H_(0x1F, 0x01) ++#define REG_SC_BK1F_02_L _PK_L_(0x1F, 0x02) ++#define REG_SC_BK1F_02_H _PK_H_(0x1F, 0x02) ++#define REG_SC_BK1F_03_L _PK_L_(0x1F, 0x03) ++#define REG_SC_BK1F_03_H _PK_H_(0x1F, 0x03) ++#define REG_SC_BK1F_04_L _PK_L_(0x1F, 0x04) ++#define REG_SC_BK1F_04_H _PK_H_(0x1F, 0x04) ++#define REG_SC_BK1F_05_L _PK_L_(0x1F, 0x05) ++#define REG_SC_BK1F_05_H _PK_H_(0x1F, 0x05) ++#define REG_SC_BK1F_06_L _PK_L_(0x1F, 0x06) ++#define REG_SC_BK1F_06_H _PK_H_(0x1F, 0x06) ++#define REG_SC_BK1F_07_L _PK_L_(0x1F, 0x07) ++#define REG_SC_BK1F_07_H _PK_H_(0x1F, 0x07) ++#define REG_SC_BK1F_08_L _PK_L_(0x1F, 0x08) ++#define REG_SC_BK1F_08_H _PK_H_(0x1F, 0x08) ++#define REG_SC_BK1F_09_L _PK_L_(0x1F, 0x09) ++#define REG_SC_BK1F_09_H _PK_H_(0x1F, 0x09) ++#define REG_SC_BK1F_0A_L _PK_L_(0x1F, 0x0A) ++#define REG_SC_BK1F_0A_H _PK_H_(0x1F, 0x0A) ++#define REG_SC_BK1F_0B_L _PK_L_(0x1F, 0x0B) ++#define REG_SC_BK1F_0B_H _PK_H_(0x1F, 0x0B) ++#define REG_SC_BK1F_0C_L _PK_L_(0x1F, 0x0C) ++#define REG_SC_BK1F_0C_H _PK_H_(0x1F, 0x0C) ++#define REG_SC_BK1F_0D_L _PK_L_(0x1F, 0x0D) ++#define REG_SC_BK1F_0D_H _PK_H_(0x1F, 0x0D) ++#define REG_SC_BK1F_0E_L _PK_L_(0x1F, 0x0E) ++#define REG_SC_BK1F_0E_H _PK_H_(0x1F, 0x0E) ++#define REG_SC_BK1F_0F_L _PK_L_(0x1F, 0x0F) ++#define REG_SC_BK1F_0F_H _PK_H_(0x1F, 0x0F) ++#define REG_SC_BK1F_10_L _PK_L_(0x1F, 0x10) ++#define REG_SC_BK1F_10_H _PK_H_(0x1F, 0x10) ++#define REG_SC_BK1F_11_L _PK_L_(0x1F, 0x11) ++#define REG_SC_BK1F_11_H _PK_H_(0x1F, 0x11) ++#define REG_SC_BK1F_12_L _PK_L_(0x1F, 0x12) ++#define REG_SC_BK1F_12_H _PK_H_(0x1F, 0x12) ++#define REG_SC_BK1F_13_L _PK_L_(0x1F, 0x13) ++#define REG_SC_BK1F_13_H _PK_H_(0x1F, 0x13) ++#define REG_SC_BK1F_14_L _PK_L_(0x1F, 0x14) ++#define REG_SC_BK1F_14_H _PK_H_(0x1F, 0x14) ++#define REG_SC_BK1F_15_L _PK_L_(0x1F, 0x15) ++#define REG_SC_BK1F_15_H _PK_H_(0x1F, 0x15) ++#define REG_SC_BK1F_16_L _PK_L_(0x1F, 0x16) ++#define REG_SC_BK1F_16_H _PK_H_(0x1F, 0x16) ++#define REG_SC_BK1F_17_L _PK_L_(0x1F, 0x17) ++#define REG_SC_BK1F_17_H _PK_H_(0x1F, 0x17) ++#define REG_SC_BK1F_18_L _PK_L_(0x1F, 0x18) ++#define REG_SC_BK1F_18_H _PK_H_(0x1F, 0x18) ++#define REG_SC_BK1F_19_L _PK_L_(0x1F, 0x19) ++#define REG_SC_BK1F_19_H _PK_H_(0x1F, 0x19) ++#define REG_SC_BK1F_1A_L _PK_L_(0x1F, 0x1A) ++#define REG_SC_BK1F_1A_H _PK_H_(0x1F, 0x1A) ++#define REG_SC_BK1F_1B_L _PK_L_(0x1F, 0x1B) ++#define REG_SC_BK1F_1B_H _PK_H_(0x1F, 0x1B) ++#define REG_SC_BK1F_1C_L _PK_L_(0x1F, 0x1C) ++#define REG_SC_BK1F_1C_H _PK_H_(0x1F, 0x1C) ++#define REG_SC_BK1F_1D_L _PK_L_(0x1F, 0x1D) ++#define REG_SC_BK1F_1D_H _PK_H_(0x1F, 0x1D) ++#define REG_SC_BK1F_1E_L _PK_L_(0x1F, 0x1E) ++#define REG_SC_BK1F_1E_H _PK_H_(0x1F, 0x1E) ++#define REG_SC_BK1F_1F_L _PK_L_(0x1F, 0x1F) ++#define REG_SC_BK1F_1F_H _PK_H_(0x1F, 0x1F) ++#define REG_SC_BK1F_20_L _PK_L_(0x1F, 0x20) ++#define REG_SC_BK1F_20_H _PK_H_(0x1F, 0x20) ++#define REG_SC_BK1F_21_L _PK_L_(0x1F, 0x21) ++#define REG_SC_BK1F_21_H _PK_H_(0x1F, 0x21) ++#define REG_SC_BK1F_22_L _PK_L_(0x1F, 0x22) ++#define REG_SC_BK1F_22_H _PK_H_(0x1F, 0x22) ++#define REG_SC_BK1F_23_L _PK_L_(0x1F, 0x23) ++#define REG_SC_BK1F_23_H _PK_H_(0x1F, 0x23) ++#define REG_SC_BK1F_24_L _PK_L_(0x1F, 0x24) ++#define REG_SC_BK1F_24_H _PK_H_(0x1F, 0x24) ++#define REG_SC_BK1F_25_L _PK_L_(0x1F, 0x25) ++#define REG_SC_BK1F_25_H _PK_H_(0x1F, 0x25) ++#define REG_SC_BK1F_26_L _PK_L_(0x1F, 0x26) ++#define REG_SC_BK1F_26_H _PK_H_(0x1F, 0x26) ++#define REG_SC_BK1F_27_L _PK_L_(0x1F, 0x27) ++#define REG_SC_BK1F_27_H _PK_H_(0x1F, 0x27) ++#define REG_SC_BK1F_28_L _PK_L_(0x1F, 0x28) ++#define REG_SC_BK1F_28_H _PK_H_(0x1F, 0x28) ++#define REG_SC_BK1F_29_L _PK_L_(0x1F, 0x29) ++#define REG_SC_BK1F_29_H _PK_H_(0x1F, 0x29) ++#define REG_SC_BK1F_2A_L _PK_L_(0x1F, 0x2A) ++#define REG_SC_BK1F_2A_H _PK_H_(0x1F, 0x2A) ++#define REG_SC_BK1F_2B_L _PK_L_(0x1F, 0x2B) ++#define REG_SC_BK1F_2B_H _PK_H_(0x1F, 0x2B) ++#define REG_SC_BK1F_2C_L _PK_L_(0x1F, 0x2C) ++#define REG_SC_BK1F_2C_H _PK_H_(0x1F, 0x2C) ++#define REG_SC_BK1F_2D_L _PK_L_(0x1F, 0x2D) ++#define REG_SC_BK1F_2D_H _PK_H_(0x1F, 0x2D) ++#define REG_SC_BK1F_2E_L _PK_L_(0x1F, 0x2E) ++#define REG_SC_BK1F_2E_H _PK_H_(0x1F, 0x2E) ++#define REG_SC_BK1F_2F_L _PK_L_(0x1F, 0x2F) ++#define REG_SC_BK1F_2F_H _PK_H_(0x1F, 0x2F) ++#define REG_SC_BK1F_30_L _PK_L_(0x1F, 0x30) ++#define REG_SC_BK1F_30_H _PK_H_(0x1F, 0x30) ++#define REG_SC_BK1F_31_L _PK_L_(0x1F, 0x31) ++#define REG_SC_BK1F_31_H _PK_H_(0x1F, 0x31) ++#define REG_SC_BK1F_32_L _PK_L_(0x1F, 0x32) ++#define REG_SC_BK1F_32_H _PK_H_(0x1F, 0x32) ++#define REG_SC_BK1F_33_L _PK_L_(0x1F, 0x33) ++#define REG_SC_BK1F_33_H _PK_H_(0x1F, 0x33) ++#define REG_SC_BK1F_34_L _PK_L_(0x1F, 0x34) ++#define REG_SC_BK1F_34_H _PK_H_(0x1F, 0x34) ++#define REG_SC_BK1F_35_L _PK_L_(0x1F, 0x35) ++#define REG_SC_BK1F_35_H _PK_H_(0x1F, 0x35) ++#define REG_SC_BK1F_36_L _PK_L_(0x1F, 0x36) ++#define REG_SC_BK1F_36_H _PK_H_(0x1F, 0x36) ++#define REG_SC_BK1F_37_L _PK_L_(0x1F, 0x37) ++#define REG_SC_BK1F_37_H _PK_H_(0x1F, 0x37) ++#define REG_SC_BK1F_38_L _PK_L_(0x1F, 0x38) ++#define REG_SC_BK1F_38_H _PK_H_(0x1F, 0x38) ++#define REG_SC_BK1F_39_L _PK_L_(0x1F, 0x39) ++#define REG_SC_BK1F_39_H _PK_H_(0x1F, 0x39) ++#define REG_SC_BK1F_3A_L _PK_L_(0x1F, 0x3A) ++#define REG_SC_BK1F_3A_H _PK_H_(0x1F, 0x3A) ++#define REG_SC_BK1F_3B_L _PK_L_(0x1F, 0x3B) ++#define REG_SC_BK1F_3B_H _PK_H_(0x1F, 0x3B) ++#define REG_SC_BK1F_3C_L _PK_L_(0x1F, 0x3C) ++#define REG_SC_BK1F_3C_H _PK_H_(0x1F, 0x3C) ++#define REG_SC_BK1F_3D_L _PK_L_(0x1F, 0x3D) ++#define REG_SC_BK1F_3D_H _PK_H_(0x1F, 0x3D) ++#define REG_SC_BK1F_3E_L _PK_L_(0x1F, 0x3E) ++#define REG_SC_BK1F_3E_H _PK_H_(0x1F, 0x3E) ++#define REG_SC_BK1F_3F_L _PK_L_(0x1F, 0x3F) ++#define REG_SC_BK1F_3F_H _PK_H_(0x1F, 0x3F) ++#define REG_SC_BK1F_40_L _PK_L_(0x1F, 0x40) ++#define REG_SC_BK1F_40_H _PK_H_(0x1F, 0x40) ++#define REG_SC_BK1F_41_L _PK_L_(0x1F, 0x41) ++#define REG_SC_BK1F_41_H _PK_H_(0x1F, 0x41) ++#define REG_SC_BK1F_42_L _PK_L_(0x1F, 0x42) ++#define REG_SC_BK1F_42_H _PK_H_(0x1F, 0x42) ++#define REG_SC_BK1F_43_L _PK_L_(0x1F, 0x43) ++#define REG_SC_BK1F_43_H _PK_H_(0x1F, 0x43) ++#define REG_SC_BK1F_44_L _PK_L_(0x1F, 0x44) ++#define REG_SC_BK1F_44_H _PK_H_(0x1F, 0x44) ++#define REG_SC_BK1F_45_L _PK_L_(0x1F, 0x45) ++#define REG_SC_BK1F_45_H _PK_H_(0x1F, 0x45) ++#define REG_SC_BK1F_46_L _PK_L_(0x1F, 0x46) ++#define REG_SC_BK1F_46_H _PK_H_(0x1F, 0x46) ++#define REG_SC_BK1F_47_L _PK_L_(0x1F, 0x47) ++#define REG_SC_BK1F_47_H _PK_H_(0x1F, 0x47) ++#define REG_SC_BK1F_48_L _PK_L_(0x1F, 0x48) ++#define REG_SC_BK1F_48_H _PK_H_(0x1F, 0x48) ++#define REG_SC_BK1F_49_L _PK_L_(0x1F, 0x49) ++#define REG_SC_BK1F_49_H _PK_H_(0x1F, 0x49) ++#define REG_SC_BK1F_4A_L _PK_L_(0x1F, 0x4A) ++#define REG_SC_BK1F_4A_H _PK_H_(0x1F, 0x4A) ++#define REG_SC_BK1F_4B_L _PK_L_(0x1F, 0x4B) ++#define REG_SC_BK1F_4B_H _PK_H_(0x1F, 0x4B) ++#define REG_SC_BK1F_4C_L _PK_L_(0x1F, 0x4C) ++#define REG_SC_BK1F_4C_H _PK_H_(0x1F, 0x4C) ++#define REG_SC_BK1F_4D_L _PK_L_(0x1F, 0x4D) ++#define REG_SC_BK1F_4D_H _PK_H_(0x1F, 0x4D) ++#define REG_SC_BK1F_4E_L _PK_L_(0x1F, 0x4E) ++#define REG_SC_BK1F_4E_H _PK_H_(0x1F, 0x4E) ++#define REG_SC_BK1F_4F_L _PK_L_(0x1F, 0x4F) ++#define REG_SC_BK1F_4F_H _PK_H_(0x1F, 0x4F) ++#define REG_SC_BK1F_50_L _PK_L_(0x1F, 0x50) ++#define REG_SC_BK1F_50_H _PK_H_(0x1F, 0x50) ++#define REG_SC_BK1F_51_L _PK_L_(0x1F, 0x51) ++#define REG_SC_BK1F_51_H _PK_H_(0x1F, 0x51) ++#define REG_SC_BK1F_52_L _PK_L_(0x1F, 0x52) ++#define REG_SC_BK1F_52_H _PK_H_(0x1F, 0x52) ++#define REG_SC_BK1F_53_L _PK_L_(0x1F, 0x53) ++#define REG_SC_BK1F_53_H _PK_H_(0x1F, 0x53) ++#define REG_SC_BK1F_54_L _PK_L_(0x1F, 0x54) ++#define REG_SC_BK1F_54_H _PK_H_(0x1F, 0x54) ++#define REG_SC_BK1F_55_L _PK_L_(0x1F, 0x55) ++#define REG_SC_BK1F_55_H _PK_H_(0x1F, 0x55) ++#define REG_SC_BK1F_56_L _PK_L_(0x1F, 0x56) ++#define REG_SC_BK1F_56_H _PK_H_(0x1F, 0x56) ++#define REG_SC_BK1F_57_L _PK_L_(0x1F, 0x57) ++#define REG_SC_BK1F_57_H _PK_H_(0x1F, 0x57) ++#define REG_SC_BK1F_58_L _PK_L_(0x1F, 0x58) ++#define REG_SC_BK1F_58_H _PK_H_(0x1F, 0x58) ++#define REG_SC_BK1F_59_L _PK_L_(0x1F, 0x59) ++#define REG_SC_BK1F_59_H _PK_H_(0x1F, 0x59) ++#define REG_SC_BK1F_5A_L _PK_L_(0x1F, 0x5A) ++#define REG_SC_BK1F_5A_H _PK_H_(0x1F, 0x5A) ++#define REG_SC_BK1F_5B_L _PK_L_(0x1F, 0x5B) ++#define REG_SC_BK1F_5B_H _PK_H_(0x1F, 0x5B) ++#define REG_SC_BK1F_5C_L _PK_L_(0x1F, 0x5C) ++#define REG_SC_BK1F_5C_H _PK_H_(0x1F, 0x5C) ++#define REG_SC_BK1F_5D_L _PK_L_(0x1F, 0x5D) ++#define REG_SC_BK1F_5D_H _PK_H_(0x1F, 0x5D) ++#define REG_SC_BK1F_5E_L _PK_L_(0x1F, 0x5E) ++#define REG_SC_BK1F_5E_H _PK_H_(0x1F, 0x5E) ++#define REG_SC_BK1F_5F_L _PK_L_(0x1F, 0x5F) ++#define REG_SC_BK1F_5F_H _PK_H_(0x1F, 0x5F) ++#define REG_SC_BK1F_60_L _PK_L_(0x1F, 0x60) ++#define REG_SC_BK1F_60_H _PK_H_(0x1F, 0x60) ++#define REG_SC_BK1F_61_L _PK_L_(0x1F, 0x61) ++#define REG_SC_BK1F_61_H _PK_H_(0x1F, 0x61) ++#define REG_SC_BK1F_62_L _PK_L_(0x1F, 0x62) ++#define REG_SC_BK1F_62_H _PK_H_(0x1F, 0x62) ++#define REG_SC_BK1F_63_L _PK_L_(0x1F, 0x63) ++#define REG_SC_BK1F_63_H _PK_H_(0x1F, 0x63) ++#define REG_SC_BK1F_64_L _PK_L_(0x1F, 0x64) ++#define REG_SC_BK1F_64_H _PK_H_(0x1F, 0x64) ++#define REG_SC_BK1F_65_L _PK_L_(0x1F, 0x65) ++#define REG_SC_BK1F_65_H _PK_H_(0x1F, 0x65) ++#define REG_SC_BK1F_66_L _PK_L_(0x1F, 0x66) ++#define REG_SC_BK1F_66_H _PK_H_(0x1F, 0x66) ++#define REG_SC_BK1F_67_L _PK_L_(0x1F, 0x67) ++#define REG_SC_BK1F_67_H _PK_H_(0x1F, 0x67) ++#define REG_SC_BK1F_68_L _PK_L_(0x1F, 0x68) ++#define REG_SC_BK1F_68_H _PK_H_(0x1F, 0x68) ++#define REG_SC_BK1F_69_L _PK_L_(0x1F, 0x69) ++#define REG_SC_BK1F_69_H _PK_H_(0x1F, 0x69) ++#define REG_SC_BK1F_6A_L _PK_L_(0x1F, 0x6A) ++#define REG_SC_BK1F_6A_H _PK_H_(0x1F, 0x6A) ++#define REG_SC_BK1F_6B_L _PK_L_(0x1F, 0x6B) ++#define REG_SC_BK1F_6B_H _PK_H_(0x1F, 0x6B) ++#define REG_SC_BK1F_6C_L _PK_L_(0x1F, 0x6C) ++#define REG_SC_BK1F_6C_H _PK_H_(0x1F, 0x6C) ++#define REG_SC_BK1F_6D_L _PK_L_(0x1F, 0x6D) ++#define REG_SC_BK1F_6D_H _PK_H_(0x1F, 0x6D) ++#define REG_SC_BK1F_6E_L _PK_L_(0x1F, 0x6E) ++#define REG_SC_BK1F_6E_H _PK_H_(0x1F, 0x6E) ++#define REG_SC_BK1F_6F_L _PK_L_(0x1F, 0x6F) ++#define REG_SC_BK1F_6F_H _PK_H_(0x1F, 0x6F) ++#define REG_SC_BK1F_70_L _PK_L_(0x1F, 0x70) ++#define REG_SC_BK1F_70_H _PK_H_(0x1F, 0x70) ++#define REG_SC_BK1F_71_L _PK_L_(0x1F, 0x71) ++#define REG_SC_BK1F_71_H _PK_H_(0x1F, 0x71) ++#define REG_SC_BK1F_72_L _PK_L_(0x1F, 0x72) ++#define REG_SC_BK1F_72_H _PK_H_(0x1F, 0x72) ++#define REG_SC_BK1F_73_L _PK_L_(0x1F, 0x73) ++#define REG_SC_BK1F_73_H _PK_H_(0x1F, 0x73) ++#define REG_SC_BK1F_74_L _PK_L_(0x1F, 0x74) ++#define REG_SC_BK1F_74_H _PK_H_(0x1F, 0x74) ++#define REG_SC_BK1F_75_L _PK_L_(0x1F, 0x75) ++#define REG_SC_BK1F_75_H _PK_H_(0x1F, 0x75) ++#define REG_SC_BK1F_76_L _PK_L_(0x1F, 0x76) ++#define REG_SC_BK1F_76_H _PK_H_(0x1F, 0x76) ++#define REG_SC_BK1F_77_L _PK_L_(0x1F, 0x77) ++#define REG_SC_BK1F_77_H _PK_H_(0x1F, 0x77) ++#define REG_SC_BK1F_78_L _PK_L_(0x1F, 0x78) ++#define REG_SC_BK1F_78_H _PK_H_(0x1F, 0x78) ++#define REG_SC_BK1F_79_L _PK_L_(0x1F, 0x79) ++#define REG_SC_BK1F_79_H _PK_H_(0x1F, 0x79) ++#define REG_SC_BK1F_7A_L _PK_L_(0x1F, 0x7A) ++#define REG_SC_BK1F_7A_H _PK_H_(0x1F, 0x7A) ++#define REG_SC_BK1F_7B_L _PK_L_(0x1F, 0x7B) ++#define REG_SC_BK1F_7B_H _PK_H_(0x1F, 0x7B) ++#define REG_SC_BK1F_7C_L _PK_L_(0x1F, 0x7C) ++#define REG_SC_BK1F_7C_H _PK_H_(0x1F, 0x7C) ++#define REG_SC_BK1F_7D_L _PK_L_(0x1F, 0x7D) ++#define REG_SC_BK1F_7D_H _PK_H_(0x1F, 0x7D) ++#define REG_SC_BK1F_7E_L _PK_L_(0x1F, 0x7E) ++#define REG_SC_BK1F_7E_H _PK_H_(0x1F, 0x7E) ++#define REG_SC_BK1F_7F_L _PK_L_(0x1F, 0x7F) ++#define REG_SC_BK1F_7F_H _PK_H_(0x1F, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK20_00_L _PK_L_(0x20, 0x00) ++#define REG_SC_BK20_00_H _PK_H_(0x20, 0x00) ++#define REG_SC_BK20_01_L _PK_L_(0x20, 0x01) ++#define REG_SC_BK20_01_H _PK_H_(0x20, 0x01) ++#define REG_SC_BK20_02_L _PK_L_(0x20, 0x02) ++#define REG_SC_BK20_02_H _PK_H_(0x20, 0x02) ++#define REG_SC_BK20_03_L _PK_L_(0x20, 0x03) ++#define REG_SC_BK20_03_H _PK_H_(0x20, 0x03) ++#define REG_SC_BK20_04_L _PK_L_(0x20, 0x04) ++#define REG_SC_BK20_04_H _PK_H_(0x20, 0x04) ++#define REG_SC_BK20_05_L _PK_L_(0x20, 0x05) ++#define REG_SC_BK20_05_H _PK_H_(0x20, 0x05) ++#define REG_SC_BK20_06_L _PK_L_(0x20, 0x06) ++#define REG_SC_BK20_06_H _PK_H_(0x20, 0x06) ++#define REG_SC_BK20_07_L _PK_L_(0x20, 0x07) ++#define REG_SC_BK20_07_H _PK_H_(0x20, 0x07) ++#define REG_SC_BK20_08_L _PK_L_(0x20, 0x08) ++#define REG_SC_BK20_08_H _PK_H_(0x20, 0x08) ++#define REG_SC_BK20_09_L _PK_L_(0x20, 0x09) ++#define REG_SC_BK20_09_H _PK_H_(0x20, 0x09) ++#define REG_SC_BK20_0A_L _PK_L_(0x20, 0x0A) ++#define REG_SC_BK20_0A_H _PK_H_(0x20, 0x0A) ++#define REG_SC_BK20_0B_L _PK_L_(0x20, 0x0B) ++#define REG_SC_BK20_0B_H _PK_H_(0x20, 0x0B) ++#define REG_SC_BK20_0C_L _PK_L_(0x20, 0x0C) ++#define REG_SC_BK20_0C_H _PK_H_(0x20, 0x0C) ++#define REG_SC_BK20_0D_L _PK_L_(0x20, 0x0D) ++#define REG_SC_BK20_0D_H _PK_H_(0x20, 0x0D) ++#define REG_SC_BK20_0E_L _PK_L_(0x20, 0x0E) ++#define REG_SC_BK20_0E_H _PK_H_(0x20, 0x0E) ++#define REG_SC_BK20_0F_L _PK_L_(0x20, 0x0F) ++#define REG_SC_BK20_0F_H _PK_H_(0x20, 0x0F) ++#define REG_SC_BK20_10_L _PK_L_(0x20, 0x10) ++#define REG_SC_BK20_10_H _PK_H_(0x20, 0x10) ++#define REG_SC_BK20_11_L _PK_L_(0x20, 0x11) ++#define REG_SC_BK20_11_H _PK_H_(0x20, 0x11) ++#define REG_SC_BK20_12_L _PK_L_(0x20, 0x12) ++#define REG_SC_BK20_12_H _PK_H_(0x20, 0x12) ++#define REG_SC_BK20_13_L _PK_L_(0x20, 0x13) ++#define REG_SC_BK20_13_H _PK_H_(0x20, 0x13) ++#define REG_SC_BK20_14_L _PK_L_(0x20, 0x14) ++#define REG_SC_BK20_14_H _PK_H_(0x20, 0x14) ++#define REG_SC_BK20_15_L _PK_L_(0x20, 0x15) ++#define REG_SC_BK20_15_H _PK_H_(0x20, 0x15) ++#define REG_SC_BK20_16_L _PK_L_(0x20, 0x16) ++#define REG_SC_BK20_16_H _PK_H_(0x20, 0x16) ++#define REG_SC_BK20_17_L _PK_L_(0x20, 0x17) ++#define REG_SC_BK20_17_H _PK_H_(0x20, 0x17) ++#define REG_SC_BK20_18_L _PK_L_(0x20, 0x18) ++#define REG_SC_BK20_18_H _PK_H_(0x20, 0x18) ++#define REG_SC_BK20_19_L _PK_L_(0x20, 0x19) ++#define REG_SC_BK20_19_H _PK_H_(0x20, 0x19) ++#define REG_SC_BK20_1A_L _PK_L_(0x20, 0x1A) ++#define REG_SC_BK20_1A_H _PK_H_(0x20, 0x1A) ++#define REG_SC_BK20_1B_L _PK_L_(0x20, 0x1B) ++#define REG_SC_BK20_1B_H _PK_H_(0x20, 0x1B) ++#define REG_SC_BK20_1C_L _PK_L_(0x20, 0x1C) ++#define REG_SC_BK20_1C_H _PK_H_(0x20, 0x1C) ++#define REG_SC_BK20_1D_L _PK_L_(0x20, 0x1D) ++#define REG_SC_BK20_1D_H _PK_H_(0x20, 0x1D) ++#define REG_SC_BK20_1E_L _PK_L_(0x20, 0x1E) ++#define REG_SC_BK20_1E_H _PK_H_(0x20, 0x1E) ++#define REG_SC_BK20_1F_L _PK_L_(0x20, 0x1F) ++#define REG_SC_BK20_1F_H _PK_H_(0x20, 0x1F) ++#define REG_SC_BK20_20_L _PK_L_(0x20, 0x20) ++#define REG_SC_BK20_20_H _PK_H_(0x20, 0x20) ++#define REG_SC_BK20_21_L _PK_L_(0x20, 0x21) ++#define REG_SC_BK20_21_H _PK_H_(0x20, 0x21) ++#define REG_SC_BK20_22_L _PK_L_(0x20, 0x22) ++#define REG_SC_BK20_22_H _PK_H_(0x20, 0x22) ++#define REG_SC_BK20_23_L _PK_L_(0x20, 0x23) ++#define REG_SC_BK20_23_H _PK_H_(0x20, 0x23) ++#define REG_SC_BK20_24_L _PK_L_(0x20, 0x24) ++#define REG_SC_BK20_24_H _PK_H_(0x20, 0x24) ++#define REG_SC_BK20_25_L _PK_L_(0x20, 0x25) ++#define REG_SC_BK20_25_H _PK_H_(0x20, 0x25) ++#define REG_SC_BK20_26_L _PK_L_(0x20, 0x26) ++#define REG_SC_BK20_26_H _PK_H_(0x20, 0x26) ++#define REG_SC_BK20_27_L _PK_L_(0x20, 0x27) ++#define REG_SC_BK20_27_H _PK_H_(0x20, 0x27) ++#define REG_SC_BK20_28_L _PK_L_(0x20, 0x28) ++#define REG_SC_BK20_28_H _PK_H_(0x20, 0x28) ++#define REG_SC_BK20_29_L _PK_L_(0x20, 0x29) ++#define REG_SC_BK20_29_H _PK_H_(0x20, 0x29) ++#define REG_SC_BK20_2A_L _PK_L_(0x20, 0x2A) ++#define REG_SC_BK20_2A_H _PK_H_(0x20, 0x2A) ++#define REG_SC_BK20_2B_L _PK_L_(0x20, 0x2B) ++#define REG_SC_BK20_2B_H _PK_H_(0x20, 0x2B) ++#define REG_SC_BK20_2C_L _PK_L_(0x20, 0x2C) ++#define REG_SC_BK20_2C_H _PK_H_(0x20, 0x2C) ++#define REG_SC_BK20_2D_L _PK_L_(0x20, 0x2D) ++#define REG_SC_BK20_2D_H _PK_H_(0x20, 0x2D) ++#define REG_SC_BK20_2E_L _PK_L_(0x20, 0x2E) ++#define REG_SC_BK20_2E_H _PK_H_(0x20, 0x2E) ++#define REG_SC_BK20_2F_L _PK_L_(0x20, 0x2F) ++#define REG_SC_BK20_2F_H _PK_H_(0x20, 0x2F) ++#define REG_SC_BK20_30_L _PK_L_(0x20, 0x30) ++#define REG_SC_BK20_30_H _PK_H_(0x20, 0x30) ++#define REG_SC_BK20_31_L _PK_L_(0x20, 0x31) ++#define REG_SC_BK20_31_H _PK_H_(0x20, 0x31) ++#define REG_SC_BK20_32_L _PK_L_(0x20, 0x32) ++#define REG_SC_BK20_32_H _PK_H_(0x20, 0x32) ++#define REG_SC_BK20_33_L _PK_L_(0x20, 0x33) ++#define REG_SC_BK20_33_H _PK_H_(0x20, 0x33) ++#define REG_SC_BK20_34_L _PK_L_(0x20, 0x34) ++#define REG_SC_BK20_34_H _PK_H_(0x20, 0x34) ++#define REG_SC_BK20_35_L _PK_L_(0x20, 0x35) ++#define REG_SC_BK20_35_H _PK_H_(0x20, 0x35) ++#define REG_SC_BK20_36_L _PK_L_(0x20, 0x36) ++#define REG_SC_BK20_36_H _PK_H_(0x20, 0x36) ++#define REG_SC_BK20_37_L _PK_L_(0x20, 0x37) ++#define REG_SC_BK20_37_H _PK_H_(0x20, 0x37) ++#define REG_SC_BK20_38_L _PK_L_(0x20, 0x38) ++#define REG_SC_BK20_38_H _PK_H_(0x20, 0x38) ++#define REG_SC_BK20_39_L _PK_L_(0x20, 0x39) ++#define REG_SC_BK20_39_H _PK_H_(0x20, 0x39) ++#define REG_SC_BK20_3A_L _PK_L_(0x20, 0x3A) ++#define REG_SC_BK20_3A_H _PK_H_(0x20, 0x3A) ++#define REG_SC_BK20_3B_L _PK_L_(0x20, 0x3B) ++#define REG_SC_BK20_3B_H _PK_H_(0x20, 0x3B) ++#define REG_SC_BK20_3C_L _PK_L_(0x20, 0x3C) ++#define REG_SC_BK20_3C_H _PK_H_(0x20, 0x3C) ++#define REG_SC_BK20_3D_L _PK_L_(0x20, 0x3D) ++#define REG_SC_BK20_3D_H _PK_H_(0x20, 0x3D) ++#define REG_SC_BK20_3E_L _PK_L_(0x20, 0x3E) ++#define REG_SC_BK20_3E_H _PK_H_(0x20, 0x3E) ++#define REG_SC_BK20_3F_L _PK_L_(0x20, 0x3F) ++#define REG_SC_BK20_3F_H _PK_H_(0x20, 0x3F) ++#define REG_SC_BK20_40_L _PK_L_(0x20, 0x40) ++#define REG_SC_BK20_40_H _PK_H_(0x20, 0x40) ++#define REG_SC_BK20_41_L _PK_L_(0x20, 0x41) ++#define REG_SC_BK20_41_H _PK_H_(0x20, 0x41) ++#define REG_SC_BK20_42_L _PK_L_(0x20, 0x42) ++#define REG_SC_BK20_42_H _PK_H_(0x20, 0x42) ++#define REG_SC_BK20_43_L _PK_L_(0x20, 0x43) ++#define REG_SC_BK20_43_H _PK_H_(0x20, 0x43) ++#define REG_SC_BK20_44_L _PK_L_(0x20, 0x44) ++#define REG_SC_BK20_44_H _PK_H_(0x20, 0x44) ++#define REG_SC_BK20_45_L _PK_L_(0x20, 0x45) ++#define REG_SC_BK20_45_H _PK_H_(0x20, 0x45) ++#define REG_SC_BK20_46_L _PK_L_(0x20, 0x46) ++#define REG_SC_BK20_46_H _PK_H_(0x20, 0x46) ++#define REG_SC_BK20_47_L _PK_L_(0x20, 0x47) ++#define REG_SC_BK20_47_H _PK_H_(0x20, 0x47) ++#define REG_SC_BK20_48_L _PK_L_(0x20, 0x48) ++#define REG_SC_BK20_48_H _PK_H_(0x20, 0x48) ++#define REG_SC_BK20_49_L _PK_L_(0x20, 0x49) ++#define REG_SC_BK20_49_H _PK_H_(0x20, 0x49) ++#define REG_SC_BK20_4A_L _PK_L_(0x20, 0x4A) ++#define REG_SC_BK20_4A_H _PK_H_(0x20, 0x4A) ++#define REG_SC_BK20_4B_L _PK_L_(0x20, 0x4B) ++#define REG_SC_BK20_4B_H _PK_H_(0x20, 0x4B) ++#define REG_SC_BK20_4C_L _PK_L_(0x20, 0x4C) ++#define REG_SC_BK20_4C_H _PK_H_(0x20, 0x4C) ++#define REG_SC_BK20_4D_L _PK_L_(0x20, 0x4D) ++#define REG_SC_BK20_4D_H _PK_H_(0x20, 0x4D) ++#define REG_SC_BK20_4E_L _PK_L_(0x20, 0x4E) ++#define REG_SC_BK20_4E_H _PK_H_(0x20, 0x4E) ++#define REG_SC_BK20_4F_L _PK_L_(0x20, 0x4F) ++#define REG_SC_BK20_4F_H _PK_H_(0x20, 0x4F) ++#define REG_SC_BK20_50_L _PK_L_(0x20, 0x50) ++#define REG_SC_BK20_50_H _PK_H_(0x20, 0x50) ++#define REG_SC_BK20_51_L _PK_L_(0x20, 0x51) ++#define REG_SC_BK20_51_H _PK_H_(0x20, 0x51) ++#define REG_SC_BK20_52_L _PK_L_(0x20, 0x52) ++#define REG_SC_BK20_52_H _PK_H_(0x20, 0x52) ++#define REG_SC_BK20_53_L _PK_L_(0x20, 0x53) ++#define REG_SC_BK20_53_H _PK_H_(0x20, 0x53) ++#define REG_SC_BK20_54_L _PK_L_(0x20, 0x54) ++#define REG_SC_BK20_54_H _PK_H_(0x20, 0x54) ++#define REG_SC_BK20_55_L _PK_L_(0x20, 0x55) ++#define REG_SC_BK20_55_H _PK_H_(0x20, 0x55) ++#define REG_SC_BK20_56_L _PK_L_(0x20, 0x56) ++#define REG_SC_BK20_56_H _PK_H_(0x20, 0x56) ++#define REG_SC_BK20_57_L _PK_L_(0x20, 0x57) ++#define REG_SC_BK20_57_H _PK_H_(0x20, 0x57) ++#define REG_SC_BK20_58_L _PK_L_(0x20, 0x58) ++#define REG_SC_BK20_58_H _PK_H_(0x20, 0x58) ++#define REG_SC_BK20_59_L _PK_L_(0x20, 0x59) ++#define REG_SC_BK20_59_H _PK_H_(0x20, 0x59) ++#define REG_SC_BK20_5A_L _PK_L_(0x20, 0x5A) ++#define REG_SC_BK20_5A_H _PK_H_(0x20, 0x5A) ++#define REG_SC_BK20_5B_L _PK_L_(0x20, 0x5B) ++#define REG_SC_BK20_5B_H _PK_H_(0x20, 0x5B) ++#define REG_SC_BK20_5C_L _PK_L_(0x20, 0x5C) ++#define REG_SC_BK20_5C_H _PK_H_(0x20, 0x5C) ++#define REG_SC_BK20_5D_L _PK_L_(0x20, 0x5D) ++#define REG_SC_BK20_5D_H _PK_H_(0x20, 0x5D) ++#define REG_SC_BK20_5E_L _PK_L_(0x20, 0x5E) ++#define REG_SC_BK20_5E_H _PK_H_(0x20, 0x5E) ++#define REG_SC_BK20_5F_L _PK_L_(0x20, 0x5F) ++#define REG_SC_BK20_5F_H _PK_H_(0x20, 0x5F) ++#define REG_SC_BK20_60_L _PK_L_(0x20, 0x60) ++#define REG_SC_BK20_60_H _PK_H_(0x20, 0x60) ++#define REG_SC_BK20_61_L _PK_L_(0x20, 0x61) ++#define REG_SC_BK20_61_H _PK_H_(0x20, 0x61) ++#define REG_SC_BK20_62_L _PK_L_(0x20, 0x62) ++#define REG_SC_BK20_62_H _PK_H_(0x20, 0x62) ++#define REG_SC_BK20_63_L _PK_L_(0x20, 0x63) ++#define REG_SC_BK20_63_H _PK_H_(0x20, 0x63) ++#define REG_SC_BK20_64_L _PK_L_(0x20, 0x64) ++#define REG_SC_BK20_64_H _PK_H_(0x20, 0x64) ++#define REG_SC_BK20_65_L _PK_L_(0x20, 0x65) ++#define REG_SC_BK20_65_H _PK_H_(0x20, 0x65) ++#define REG_SC_BK20_66_L _PK_L_(0x20, 0x66) ++#define REG_SC_BK20_66_H _PK_H_(0x20, 0x66) ++#define REG_SC_BK20_67_L _PK_L_(0x20, 0x67) ++#define REG_SC_BK20_67_H _PK_H_(0x20, 0x67) ++#define REG_SC_BK20_68_L _PK_L_(0x20, 0x68) ++#define REG_SC_BK20_68_H _PK_H_(0x20, 0x68) ++#define REG_SC_BK20_69_L _PK_L_(0x20, 0x69) ++#define REG_SC_BK20_69_H _PK_H_(0x20, 0x69) ++#define REG_SC_BK20_6A_L _PK_L_(0x20, 0x6A) ++#define REG_SC_BK20_6A_H _PK_H_(0x20, 0x6A) ++#define REG_SC_BK20_6B_L _PK_L_(0x20, 0x6B) ++#define REG_SC_BK20_6B_H _PK_H_(0x20, 0x6B) ++#define REG_SC_BK20_6C_L _PK_L_(0x20, 0x6C) ++#define REG_SC_BK20_6C_H _PK_H_(0x20, 0x6C) ++#define REG_SC_BK20_6D_L _PK_L_(0x20, 0x6D) ++#define REG_SC_BK20_6D_H _PK_H_(0x20, 0x6D) ++#define REG_SC_BK20_6E_L _PK_L_(0x20, 0x6E) ++#define REG_SC_BK20_6E_H _PK_H_(0x20, 0x6E) ++#define REG_SC_BK20_6F_L _PK_L_(0x20, 0x6F) ++#define REG_SC_BK20_6F_H _PK_H_(0x20, 0x6F) ++#define REG_SC_BK20_70_L _PK_L_(0x20, 0x70) ++#define REG_SC_BK20_70_H _PK_H_(0x20, 0x70) ++#define REG_SC_BK20_71_L _PK_L_(0x20, 0x71) ++#define REG_SC_BK20_71_H _PK_H_(0x20, 0x71) ++#define REG_SC_BK20_72_L _PK_L_(0x20, 0x72) ++#define REG_SC_BK20_72_H _PK_H_(0x20, 0x72) ++#define REG_SC_BK20_73_L _PK_L_(0x20, 0x73) ++#define REG_SC_BK20_73_H _PK_H_(0x20, 0x73) ++#define REG_SC_BK20_74_L _PK_L_(0x20, 0x74) ++#define REG_SC_BK20_74_H _PK_H_(0x20, 0x74) ++#define REG_SC_BK20_75_L _PK_L_(0x20, 0x75) ++#define REG_SC_BK20_75_H _PK_H_(0x20, 0x75) ++#define REG_SC_BK20_76_L _PK_L_(0x20, 0x76) ++#define REG_SC_BK20_76_H _PK_H_(0x20, 0x76) ++#define REG_SC_BK20_77_L _PK_L_(0x20, 0x77) ++#define REG_SC_BK20_77_H _PK_H_(0x20, 0x77) ++#define REG_SC_BK20_78_L _PK_L_(0x20, 0x78) ++#define REG_SC_BK20_78_H _PK_H_(0x20, 0x78) ++#define REG_SC_BK20_79_L _PK_L_(0x20, 0x79) ++#define REG_SC_BK20_79_H _PK_H_(0x20, 0x79) ++#define REG_SC_BK20_7A_L _PK_L_(0x20, 0x7A) ++#define REG_SC_BK20_7A_H _PK_H_(0x20, 0x7A) ++#define REG_SC_BK20_7B_L _PK_L_(0x20, 0x7B) ++#define REG_SC_BK20_7B_H _PK_H_(0x20, 0x7B) ++#define REG_SC_BK20_7C_L _PK_L_(0x20, 0x7C) ++#define REG_SC_BK20_7C_H _PK_H_(0x20, 0x7C) ++#define REG_SC_BK20_7D_L _PK_L_(0x20, 0x7D) ++#define REG_SC_BK20_7D_H _PK_H_(0x20, 0x7D) ++#define REG_SC_BK20_7E_L _PK_L_(0x20, 0x7E) ++#define REG_SC_BK20_7E_H _PK_H_(0x20, 0x7E) ++#define REG_SC_BK20_7F_L _PK_L_(0x20, 0x7F) ++#define REG_SC_BK20_7F_H _PK_H_(0x20, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK21_00_L _PK_L_(0x21, 0x00) ++#define REG_SC_BK21_00_H _PK_H_(0x21, 0x00) ++#define REG_SC_BK21_01_L _PK_L_(0x21, 0x01) ++#define REG_SC_BK21_01_H _PK_H_(0x21, 0x01) ++#define REG_SC_BK21_02_L _PK_L_(0x21, 0x02) ++#define REG_SC_BK21_02_H _PK_H_(0x21, 0x02) ++#define REG_SC_BK21_03_L _PK_L_(0x21, 0x03) ++#define REG_SC_BK21_03_H _PK_H_(0x21, 0x03) ++#define REG_SC_BK21_04_L _PK_L_(0x21, 0x04) ++#define REG_SC_BK21_04_H _PK_H_(0x21, 0x04) ++#define REG_SC_BK21_05_L _PK_L_(0x21, 0x05) ++#define REG_SC_BK21_05_H _PK_H_(0x21, 0x05) ++#define REG_SC_BK21_06_L _PK_L_(0x21, 0x06) ++#define REG_SC_BK21_06_H _PK_H_(0x21, 0x06) ++#define REG_SC_BK21_07_L _PK_L_(0x21, 0x07) ++#define REG_SC_BK21_07_H _PK_H_(0x21, 0x07) ++#define REG_SC_BK21_08_L _PK_L_(0x21, 0x08) ++#define REG_SC_BK21_08_H _PK_H_(0x21, 0x08) ++#define REG_SC_BK21_09_L _PK_L_(0x21, 0x09) ++#define REG_SC_BK21_09_H _PK_H_(0x21, 0x09) ++#define REG_SC_BK21_0A_L _PK_L_(0x21, 0x0A) ++#define REG_SC_BK21_0A_H _PK_H_(0x21, 0x0A) ++#define REG_SC_BK21_0B_L _PK_L_(0x21, 0x0B) ++#define REG_SC_BK21_0B_H _PK_H_(0x21, 0x0B) ++#define REG_SC_BK21_0C_L _PK_L_(0x21, 0x0C) ++#define REG_SC_BK21_0C_H _PK_H_(0x21, 0x0C) ++#define REG_SC_BK21_0D_L _PK_L_(0x21, 0x0D) ++#define REG_SC_BK21_0D_H _PK_H_(0x21, 0x0D) ++#define REG_SC_BK21_0E_L _PK_L_(0x21, 0x0E) ++#define REG_SC_BK21_0E_H _PK_H_(0x21, 0x0E) ++#define REG_SC_BK21_0F_L _PK_L_(0x21, 0x0F) ++#define REG_SC_BK21_0F_H _PK_H_(0x21, 0x0F) ++#define REG_SC_BK21_10_L _PK_L_(0x21, 0x10) ++#define REG_SC_BK21_10_H _PK_H_(0x21, 0x10) ++#define REG_SC_BK21_11_L _PK_L_(0x21, 0x11) ++#define REG_SC_BK21_11_H _PK_H_(0x21, 0x11) ++#define REG_SC_BK21_12_L _PK_L_(0x21, 0x12) ++#define REG_SC_BK21_12_H _PK_H_(0x21, 0x12) ++#define REG_SC_BK21_13_L _PK_L_(0x21, 0x13) ++#define REG_SC_BK21_13_H _PK_H_(0x21, 0x13) ++#define REG_SC_BK21_14_L _PK_L_(0x21, 0x14) ++#define REG_SC_BK21_14_H _PK_H_(0x21, 0x14) ++#define REG_SC_BK21_15_L _PK_L_(0x21, 0x15) ++#define REG_SC_BK21_15_H _PK_H_(0x21, 0x15) ++#define REG_SC_BK21_16_L _PK_L_(0x21, 0x16) ++#define REG_SC_BK21_16_H _PK_H_(0x21, 0x16) ++#define REG_SC_BK21_17_L _PK_L_(0x21, 0x17) ++#define REG_SC_BK21_17_H _PK_H_(0x21, 0x17) ++#define REG_SC_BK21_18_L _PK_L_(0x21, 0x18) ++#define REG_SC_BK21_18_H _PK_H_(0x21, 0x18) ++#define REG_SC_BK21_19_L _PK_L_(0x21, 0x19) ++#define REG_SC_BK21_19_H _PK_H_(0x21, 0x19) ++#define REG_SC_BK21_1A_L _PK_L_(0x21, 0x1A) ++#define REG_SC_BK21_1A_H _PK_H_(0x21, 0x1A) ++#define REG_SC_BK21_1B_L _PK_L_(0x21, 0x1B) ++#define REG_SC_BK21_1B_H _PK_H_(0x21, 0x1B) ++#define REG_SC_BK21_1C_L _PK_L_(0x21, 0x1C) ++#define REG_SC_BK21_1C_H _PK_H_(0x21, 0x1C) ++#define REG_SC_BK21_1D_L _PK_L_(0x21, 0x1D) ++#define REG_SC_BK21_1D_H _PK_H_(0x21, 0x1D) ++#define REG_SC_BK21_1E_L _PK_L_(0x21, 0x1E) ++#define REG_SC_BK21_1E_H _PK_H_(0x21, 0x1E) ++#define REG_SC_BK21_1F_L _PK_L_(0x21, 0x1F) ++#define REG_SC_BK21_1F_H _PK_H_(0x21, 0x1F) ++#define REG_SC_BK21_20_L _PK_L_(0x21, 0x20) ++#define REG_SC_BK21_20_H _PK_H_(0x21, 0x20) ++#define REG_SC_BK21_21_L _PK_L_(0x21, 0x21) ++#define REG_SC_BK21_21_H _PK_H_(0x21, 0x21) ++#define REG_SC_BK21_22_L _PK_L_(0x21, 0x22) ++#define REG_SC_BK21_22_H _PK_H_(0x21, 0x22) ++#define REG_SC_BK21_23_L _PK_L_(0x21, 0x23) ++#define REG_SC_BK21_23_H _PK_H_(0x21, 0x23) ++#define REG_SC_BK21_24_L _PK_L_(0x21, 0x24) ++#define REG_SC_BK21_24_H _PK_H_(0x21, 0x24) ++#define REG_SC_BK21_25_L _PK_L_(0x21, 0x25) ++#define REG_SC_BK21_25_H _PK_H_(0x21, 0x25) ++#define REG_SC_BK21_26_L _PK_L_(0x21, 0x26) ++#define REG_SC_BK21_26_H _PK_H_(0x21, 0x26) ++#define REG_SC_BK21_27_L _PK_L_(0x21, 0x27) ++#define REG_SC_BK21_27_H _PK_H_(0x21, 0x27) ++#define REG_SC_BK21_28_L _PK_L_(0x21, 0x28) ++#define REG_SC_BK21_28_H _PK_H_(0x21, 0x28) ++#define REG_SC_BK21_29_L _PK_L_(0x21, 0x29) ++#define REG_SC_BK21_29_H _PK_H_(0x21, 0x29) ++#define REG_SC_BK21_2A_L _PK_L_(0x21, 0x2A) ++#define REG_SC_BK21_2A_H _PK_H_(0x21, 0x2A) ++#define REG_SC_BK21_2B_L _PK_L_(0x21, 0x2B) ++#define REG_SC_BK21_2B_H _PK_H_(0x21, 0x2B) ++#define REG_SC_BK21_2C_L _PK_L_(0x21, 0x2C) ++#define REG_SC_BK21_2C_H _PK_H_(0x21, 0x2C) ++#define REG_SC_BK21_2D_L _PK_L_(0x21, 0x2D) ++#define REG_SC_BK21_2D_H _PK_H_(0x21, 0x2D) ++#define REG_SC_BK21_2E_L _PK_L_(0x21, 0x2E) ++#define REG_SC_BK21_2E_H _PK_H_(0x21, 0x2E) ++#define REG_SC_BK21_2F_L _PK_L_(0x21, 0x2F) ++#define REG_SC_BK21_2F_H _PK_H_(0x21, 0x2F) ++#define REG_SC_BK21_30_L _PK_L_(0x21, 0x30) ++#define REG_SC_BK21_30_H _PK_H_(0x21, 0x30) ++#define REG_SC_BK21_31_L _PK_L_(0x21, 0x31) ++#define REG_SC_BK21_31_H _PK_H_(0x21, 0x31) ++#define REG_SC_BK21_32_L _PK_L_(0x21, 0x32) ++#define REG_SC_BK21_32_H _PK_H_(0x21, 0x32) ++#define REG_SC_BK21_33_L _PK_L_(0x21, 0x33) ++#define REG_SC_BK21_33_H _PK_H_(0x21, 0x33) ++#define REG_SC_BK21_34_L _PK_L_(0x21, 0x34) ++#define REG_SC_BK21_34_H _PK_H_(0x21, 0x34) ++#define REG_SC_BK21_35_L _PK_L_(0x21, 0x35) ++#define REG_SC_BK21_35_H _PK_H_(0x21, 0x35) ++#define REG_SC_BK21_36_L _PK_L_(0x21, 0x36) ++#define REG_SC_BK21_36_H _PK_H_(0x21, 0x36) ++#define REG_SC_BK21_37_L _PK_L_(0x21, 0x37) ++#define REG_SC_BK21_37_H _PK_H_(0x21, 0x37) ++#define REG_SC_BK21_38_L _PK_L_(0x21, 0x38) ++#define REG_SC_BK21_38_H _PK_H_(0x21, 0x38) ++#define REG_SC_BK21_39_L _PK_L_(0x21, 0x39) ++#define REG_SC_BK21_39_H _PK_H_(0x21, 0x39) ++#define REG_SC_BK21_3A_L _PK_L_(0x21, 0x3A) ++#define REG_SC_BK21_3A_H _PK_H_(0x21, 0x3A) ++#define REG_SC_BK21_3B_L _PK_L_(0x21, 0x3B) ++#define REG_SC_BK21_3B_H _PK_H_(0x21, 0x3B) ++#define REG_SC_BK21_3C_L _PK_L_(0x21, 0x3C) ++#define REG_SC_BK21_3C_H _PK_H_(0x21, 0x3C) ++#define REG_SC_BK21_3D_L _PK_L_(0x21, 0x3D) ++#define REG_SC_BK21_3D_H _PK_H_(0x21, 0x3D) ++#define REG_SC_BK21_3E_L _PK_L_(0x21, 0x3E) ++#define REG_SC_BK21_3E_H _PK_H_(0x21, 0x3E) ++#define REG_SC_BK21_3F_L _PK_L_(0x21, 0x3F) ++#define REG_SC_BK21_3F_H _PK_H_(0x21, 0x3F) ++#define REG_SC_BK21_40_L _PK_L_(0x21, 0x40) ++#define REG_SC_BK21_40_H _PK_H_(0x21, 0x40) ++#define REG_SC_BK21_41_L _PK_L_(0x21, 0x41) ++#define REG_SC_BK21_41_H _PK_H_(0x21, 0x41) ++#define REG_SC_BK21_42_L _PK_L_(0x21, 0x42) ++#define REG_SC_BK21_42_H _PK_H_(0x21, 0x42) ++#define REG_SC_BK21_43_L _PK_L_(0x21, 0x43) ++#define REG_SC_BK21_43_H _PK_H_(0x21, 0x43) ++#define REG_SC_BK21_44_L _PK_L_(0x21, 0x44) ++#define REG_SC_BK21_44_H _PK_H_(0x21, 0x44) ++#define REG_SC_BK21_45_L _PK_L_(0x21, 0x45) ++#define REG_SC_BK21_45_H _PK_H_(0x21, 0x45) ++#define REG_SC_BK21_46_L _PK_L_(0x21, 0x46) ++#define REG_SC_BK21_46_H _PK_H_(0x21, 0x46) ++#define REG_SC_BK21_47_L _PK_L_(0x21, 0x47) ++#define REG_SC_BK21_47_H _PK_H_(0x21, 0x47) ++#define REG_SC_BK21_48_L _PK_L_(0x21, 0x48) ++#define REG_SC_BK21_48_H _PK_H_(0x21, 0x48) ++#define REG_SC_BK21_49_L _PK_L_(0x21, 0x49) ++#define REG_SC_BK21_49_H _PK_H_(0x21, 0x49) ++#define REG_SC_BK21_4A_L _PK_L_(0x21, 0x4A) ++#define REG_SC_BK21_4A_H _PK_H_(0x21, 0x4A) ++#define REG_SC_BK21_4B_L _PK_L_(0x21, 0x4B) ++#define REG_SC_BK21_4B_H _PK_H_(0x21, 0x4B) ++#define REG_SC_BK21_4C_L _PK_L_(0x21, 0x4C) ++#define REG_SC_BK21_4C_H _PK_H_(0x21, 0x4C) ++#define REG_SC_BK21_4D_L _PK_L_(0x21, 0x4D) ++#define REG_SC_BK21_4D_H _PK_H_(0x21, 0x4D) ++#define REG_SC_BK21_4E_L _PK_L_(0x21, 0x4E) ++#define REG_SC_BK21_4E_H _PK_H_(0x21, 0x4E) ++#define REG_SC_BK21_4F_L _PK_L_(0x21, 0x4F) ++#define REG_SC_BK21_4F_H _PK_H_(0x21, 0x4F) ++#define REG_SC_BK21_50_L _PK_L_(0x21, 0x50) ++#define REG_SC_BK21_50_H _PK_H_(0x21, 0x50) ++#define REG_SC_BK21_51_L _PK_L_(0x21, 0x51) ++#define REG_SC_BK21_51_H _PK_H_(0x21, 0x51) ++#define REG_SC_BK21_52_L _PK_L_(0x21, 0x52) ++#define REG_SC_BK21_52_H _PK_H_(0x21, 0x52) ++#define REG_SC_BK21_53_L _PK_L_(0x21, 0x53) ++#define REG_SC_BK21_53_H _PK_H_(0x21, 0x53) ++#define REG_SC_BK21_54_L _PK_L_(0x21, 0x54) ++#define REG_SC_BK21_54_H _PK_H_(0x21, 0x54) ++#define REG_SC_BK21_55_L _PK_L_(0x21, 0x55) ++#define REG_SC_BK21_55_H _PK_H_(0x21, 0x55) ++#define REG_SC_BK21_56_L _PK_L_(0x21, 0x56) ++#define REG_SC_BK21_56_H _PK_H_(0x21, 0x56) ++#define REG_SC_BK21_57_L _PK_L_(0x21, 0x57) ++#define REG_SC_BK21_57_H _PK_H_(0x21, 0x57) ++#define REG_SC_BK21_58_L _PK_L_(0x21, 0x58) ++#define REG_SC_BK21_58_H _PK_H_(0x21, 0x58) ++#define REG_SC_BK21_59_L _PK_L_(0x21, 0x59) ++#define REG_SC_BK21_59_H _PK_H_(0x21, 0x59) ++#define REG_SC_BK21_5A_L _PK_L_(0x21, 0x5A) ++#define REG_SC_BK21_5A_H _PK_H_(0x21, 0x5A) ++#define REG_SC_BK21_5B_L _PK_L_(0x21, 0x5B) ++#define REG_SC_BK21_5B_H _PK_H_(0x21, 0x5B) ++#define REG_SC_BK21_5C_L _PK_L_(0x21, 0x5C) ++#define REG_SC_BK21_5C_H _PK_H_(0x21, 0x5C) ++#define REG_SC_BK21_5D_L _PK_L_(0x21, 0x5D) ++#define REG_SC_BK21_5D_H _PK_H_(0x21, 0x5D) ++#define REG_SC_BK21_5E_L _PK_L_(0x21, 0x5E) ++#define REG_SC_BK21_5E_H _PK_H_(0x21, 0x5E) ++#define REG_SC_BK21_5F_L _PK_L_(0x21, 0x5F) ++#define REG_SC_BK21_5F_H _PK_H_(0x21, 0x5F) ++#define REG_SC_BK21_60_L _PK_L_(0x21, 0x60) ++#define REG_SC_BK21_60_H _PK_H_(0x21, 0x60) ++#define REG_SC_BK21_61_L _PK_L_(0x21, 0x61) ++#define REG_SC_BK21_61_H _PK_H_(0x21, 0x61) ++#define REG_SC_BK21_62_L _PK_L_(0x21, 0x62) ++#define REG_SC_BK21_62_H _PK_H_(0x21, 0x62) ++#define REG_SC_BK21_63_L _PK_L_(0x21, 0x63) ++#define REG_SC_BK21_63_H _PK_H_(0x21, 0x63) ++#define REG_SC_BK21_64_L _PK_L_(0x21, 0x64) ++#define REG_SC_BK21_64_H _PK_H_(0x21, 0x64) ++#define REG_SC_BK21_65_L _PK_L_(0x21, 0x65) ++#define REG_SC_BK21_65_H _PK_H_(0x21, 0x65) ++#define REG_SC_BK21_66_L _PK_L_(0x21, 0x66) ++#define REG_SC_BK21_66_H _PK_H_(0x21, 0x66) ++#define REG_SC_BK21_67_L _PK_L_(0x21, 0x67) ++#define REG_SC_BK21_67_H _PK_H_(0x21, 0x67) ++#define REG_SC_BK21_68_L _PK_L_(0x21, 0x68) ++#define REG_SC_BK21_68_H _PK_H_(0x21, 0x68) ++#define REG_SC_BK21_69_L _PK_L_(0x21, 0x69) ++#define REG_SC_BK21_69_H _PK_H_(0x21, 0x69) ++#define REG_SC_BK21_6A_L _PK_L_(0x21, 0x6A) ++#define REG_SC_BK21_6A_H _PK_H_(0x21, 0x6A) ++#define REG_SC_BK21_6B_L _PK_L_(0x21, 0x6B) ++#define REG_SC_BK21_6B_H _PK_H_(0x21, 0x6B) ++#define REG_SC_BK21_6C_L _PK_L_(0x21, 0x6C) ++#define REG_SC_BK21_6C_H _PK_H_(0x21, 0x6C) ++#define REG_SC_BK21_6D_L _PK_L_(0x21, 0x6D) ++#define REG_SC_BK21_6D_H _PK_H_(0x21, 0x6D) ++#define REG_SC_BK21_6E_L _PK_L_(0x21, 0x6E) ++#define REG_SC_BK21_6E_H _PK_H_(0x21, 0x6E) ++#define REG_SC_BK21_6F_L _PK_L_(0x21, 0x6F) ++#define REG_SC_BK21_6F_H _PK_H_(0x21, 0x6F) ++#define REG_SC_BK21_70_L _PK_L_(0x21, 0x70) ++#define REG_SC_BK21_70_H _PK_H_(0x21, 0x70) ++#define REG_SC_BK21_71_L _PK_L_(0x21, 0x71) ++#define REG_SC_BK21_71_H _PK_H_(0x21, 0x71) ++#define REG_SC_BK21_72_L _PK_L_(0x21, 0x72) ++#define REG_SC_BK21_72_H _PK_H_(0x21, 0x72) ++#define REG_SC_BK21_73_L _PK_L_(0x21, 0x73) ++#define REG_SC_BK21_73_H _PK_H_(0x21, 0x73) ++#define REG_SC_BK21_74_L _PK_L_(0x21, 0x74) ++#define REG_SC_BK21_74_H _PK_H_(0x21, 0x74) ++#define REG_SC_BK21_75_L _PK_L_(0x21, 0x75) ++#define REG_SC_BK21_75_H _PK_H_(0x21, 0x75) ++#define REG_SC_BK21_76_L _PK_L_(0x21, 0x76) ++#define REG_SC_BK21_76_H _PK_H_(0x21, 0x76) ++#define REG_SC_BK21_77_L _PK_L_(0x21, 0x77) ++#define REG_SC_BK21_77_H _PK_H_(0x21, 0x77) ++#define REG_SC_BK21_78_L _PK_L_(0x21, 0x78) ++#define REG_SC_BK21_78_H _PK_H_(0x21, 0x78) ++#define REG_SC_BK21_79_L _PK_L_(0x21, 0x79) ++#define REG_SC_BK21_79_H _PK_H_(0x21, 0x79) ++#define REG_SC_BK21_7A_L _PK_L_(0x21, 0x7A) ++#define REG_SC_BK21_7A_H _PK_H_(0x21, 0x7A) ++#define REG_SC_BK21_7B_L _PK_L_(0x21, 0x7B) ++#define REG_SC_BK21_7B_H _PK_H_(0x21, 0x7B) ++#define REG_SC_BK21_7C_L _PK_L_(0x21, 0x7C) ++#define REG_SC_BK21_7C_H _PK_H_(0x21, 0x7C) ++#define REG_SC_BK21_7D_L _PK_L_(0x21, 0x7D) ++#define REG_SC_BK21_7D_H _PK_H_(0x21, 0x7D) ++#define REG_SC_BK21_7E_L _PK_L_(0x21, 0x7E) ++#define REG_SC_BK21_7E_H _PK_H_(0x21, 0x7E) ++#define REG_SC_BK21_7F_L _PK_L_(0x21, 0x7F) ++#define REG_SC_BK21_7F_H _PK_H_(0x21, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK22_00_L _PK_L_(0x22, 0x00) ++#define REG_SC_BK22_00_H _PK_H_(0x22, 0x00) ++#define REG_SC_BK22_01_L _PK_L_(0x22, 0x01) ++#define REG_SC_BK22_01_H _PK_H_(0x22, 0x01) ++#define REG_SC_BK22_02_L _PK_L_(0x22, 0x02) ++#define REG_SC_BK22_02_H _PK_H_(0x22, 0x02) ++#define REG_SC_BK22_03_L _PK_L_(0x22, 0x03) ++#define REG_SC_BK22_03_H _PK_H_(0x22, 0x03) ++#define REG_SC_BK22_04_L _PK_L_(0x22, 0x04) ++#define REG_SC_BK22_04_H _PK_H_(0x22, 0x04) ++#define REG_SC_BK22_05_L _PK_L_(0x22, 0x05) ++#define REG_SC_BK22_05_H _PK_H_(0x22, 0x05) ++#define REG_SC_BK22_06_L _PK_L_(0x22, 0x06) ++#define REG_SC_BK22_06_H _PK_H_(0x22, 0x06) ++#define REG_SC_BK22_07_L _PK_L_(0x22, 0x07) ++#define REG_SC_BK22_07_H _PK_H_(0x22, 0x07) ++#define REG_SC_BK22_08_L _PK_L_(0x22, 0x08) ++#define REG_SC_BK22_08_H _PK_H_(0x22, 0x08) ++#define REG_SC_BK22_09_L _PK_L_(0x22, 0x09) ++#define REG_SC_BK22_09_H _PK_H_(0x22, 0x09) ++#define REG_SC_BK22_0A_L _PK_L_(0x22, 0x0A) ++#define REG_SC_BK22_0A_H _PK_H_(0x22, 0x0A) ++#define REG_SC_BK22_0B_L _PK_L_(0x22, 0x0B) ++#define REG_SC_BK22_0B_H _PK_H_(0x22, 0x0B) ++#define REG_SC_BK22_0C_L _PK_L_(0x22, 0x0C) ++#define REG_SC_BK22_0C_H _PK_H_(0x22, 0x0C) ++#define REG_SC_BK22_0D_L _PK_L_(0x22, 0x0D) ++#define REG_SC_BK22_0D_H _PK_H_(0x22, 0x0D) ++#define REG_SC_BK22_0E_L _PK_L_(0x22, 0x0E) ++#define REG_SC_BK22_0E_H _PK_H_(0x22, 0x0E) ++#define REG_SC_BK22_0F_L _PK_L_(0x22, 0x0F) ++#define REG_SC_BK22_0F_H _PK_H_(0x22, 0x0F) ++#define REG_SC_BK22_10_L _PK_L_(0x22, 0x10) ++#define REG_SC_BK22_10_H _PK_H_(0x22, 0x10) ++#define REG_SC_BK22_11_L _PK_L_(0x22, 0x11) ++#define REG_SC_BK22_11_H _PK_H_(0x22, 0x11) ++#define REG_SC_BK22_12_L _PK_L_(0x22, 0x12) ++#define REG_SC_BK22_12_H _PK_H_(0x22, 0x12) ++#define REG_SC_BK22_13_L _PK_L_(0x22, 0x13) ++#define REG_SC_BK22_13_H _PK_H_(0x22, 0x13) ++#define REG_SC_BK22_14_L _PK_L_(0x22, 0x14) ++#define REG_SC_BK22_14_H _PK_H_(0x22, 0x14) ++#define REG_SC_BK22_15_L _PK_L_(0x22, 0x15) ++#define REG_SC_BK22_15_H _PK_H_(0x22, 0x15) ++#define REG_SC_BK22_16_L _PK_L_(0x22, 0x16) ++#define REG_SC_BK22_16_H _PK_H_(0x22, 0x16) ++#define REG_SC_BK22_17_L _PK_L_(0x22, 0x17) ++#define REG_SC_BK22_17_H _PK_H_(0x22, 0x17) ++#define REG_SC_BK22_18_L _PK_L_(0x22, 0x18) ++#define REG_SC_BK22_18_H _PK_H_(0x22, 0x18) ++#define REG_SC_BK22_19_L _PK_L_(0x22, 0x19) ++#define REG_SC_BK22_19_H _PK_H_(0x22, 0x19) ++#define REG_SC_BK22_1A_L _PK_L_(0x22, 0x1A) ++#define REG_SC_BK22_1A_H _PK_H_(0x22, 0x1A) ++#define REG_SC_BK22_1B_L _PK_L_(0x22, 0x1B) ++#define REG_SC_BK22_1B_H _PK_H_(0x22, 0x1B) ++#define REG_SC_BK22_1C_L _PK_L_(0x22, 0x1C) ++#define REG_SC_BK22_1C_H _PK_H_(0x22, 0x1C) ++#define REG_SC_BK22_1D_L _PK_L_(0x22, 0x1D) ++#define REG_SC_BK22_1D_H _PK_H_(0x22, 0x1D) ++#define REG_SC_BK22_1E_L _PK_L_(0x22, 0x1E) ++#define REG_SC_BK22_1E_H _PK_H_(0x22, 0x1E) ++#define REG_SC_BK22_1F_L _PK_L_(0x22, 0x1F) ++#define REG_SC_BK22_1F_H _PK_H_(0x22, 0x1F) ++#define REG_SC_BK22_20_L _PK_L_(0x22, 0x20) ++#define REG_SC_BK22_20_H _PK_H_(0x22, 0x20) ++#define REG_SC_BK22_21_L _PK_L_(0x22, 0x21) ++#define REG_SC_BK22_21_H _PK_H_(0x22, 0x21) ++#define REG_SC_BK22_22_L _PK_L_(0x22, 0x22) ++#define REG_SC_BK22_22_H _PK_H_(0x22, 0x22) ++#define REG_SC_BK22_23_L _PK_L_(0x22, 0x23) ++#define REG_SC_BK22_23_H _PK_H_(0x22, 0x23) ++#define REG_SC_BK22_24_L _PK_L_(0x22, 0x24) ++#define REG_SC_BK22_24_H _PK_H_(0x22, 0x24) ++#define REG_SC_BK22_25_L _PK_L_(0x22, 0x25) ++#define REG_SC_BK22_25_H _PK_H_(0x22, 0x25) ++#define REG_SC_BK22_26_L _PK_L_(0x22, 0x26) ++#define REG_SC_BK22_26_H _PK_H_(0x22, 0x26) ++#define REG_SC_BK22_27_L _PK_L_(0x22, 0x27) ++#define REG_SC_BK22_27_H _PK_H_(0x22, 0x27) ++#define REG_SC_BK22_28_L _PK_L_(0x22, 0x28) ++#define REG_SC_BK22_28_H _PK_H_(0x22, 0x28) ++#define REG_SC_BK22_29_L _PK_L_(0x22, 0x29) ++#define REG_SC_BK22_29_H _PK_H_(0x22, 0x29) ++#define REG_SC_BK22_2A_L _PK_L_(0x22, 0x2A) ++#define REG_SC_BK22_2A_H _PK_H_(0x22, 0x2A) ++#define REG_SC_BK22_2B_L _PK_L_(0x22, 0x2B) ++#define REG_SC_BK22_2B_H _PK_H_(0x22, 0x2B) ++#define REG_SC_BK22_2C_L _PK_L_(0x22, 0x2C) ++#define REG_SC_BK22_2C_H _PK_H_(0x22, 0x2C) ++#define REG_SC_BK22_2D_L _PK_L_(0x22, 0x2D) ++#define REG_SC_BK22_2D_H _PK_H_(0x22, 0x2D) ++#define REG_SC_BK22_2E_L _PK_L_(0x22, 0x2E) ++#define REG_SC_BK22_2E_H _PK_H_(0x22, 0x2E) ++#define REG_SC_BK22_2F_L _PK_L_(0x22, 0x2F) ++#define REG_SC_BK22_2F_H _PK_H_(0x22, 0x2F) ++#define REG_SC_BK22_30_L _PK_L_(0x22, 0x30) ++#define REG_SC_BK22_30_H _PK_H_(0x22, 0x30) ++#define REG_SC_BK22_31_L _PK_L_(0x22, 0x31) ++#define REG_SC_BK22_31_H _PK_H_(0x22, 0x31) ++#define REG_SC_BK22_32_L _PK_L_(0x22, 0x32) ++#define REG_SC_BK22_32_H _PK_H_(0x22, 0x32) ++#define REG_SC_BK22_33_L _PK_L_(0x22, 0x33) ++#define REG_SC_BK22_33_H _PK_H_(0x22, 0x33) ++#define REG_SC_BK22_34_L _PK_L_(0x22, 0x34) ++#define REG_SC_BK22_34_H _PK_H_(0x22, 0x34) ++#define REG_SC_BK22_35_L _PK_L_(0x22, 0x35) ++#define REG_SC_BK22_35_H _PK_H_(0x22, 0x35) ++#define REG_SC_BK22_36_L _PK_L_(0x22, 0x36) ++#define REG_SC_BK22_36_H _PK_H_(0x22, 0x36) ++#define REG_SC_BK22_37_L _PK_L_(0x22, 0x37) ++#define REG_SC_BK22_37_H _PK_H_(0x22, 0x37) ++#define REG_SC_BK22_38_L _PK_L_(0x22, 0x38) ++#define REG_SC_BK22_38_H _PK_H_(0x22, 0x38) ++#define REG_SC_BK22_39_L _PK_L_(0x22, 0x39) ++#define REG_SC_BK22_39_H _PK_H_(0x22, 0x39) ++#define REG_SC_BK22_3A_L _PK_L_(0x22, 0x3A) ++#define REG_SC_BK22_3A_H _PK_H_(0x22, 0x3A) ++#define REG_SC_BK22_3B_L _PK_L_(0x22, 0x3B) ++#define REG_SC_BK22_3B_H _PK_H_(0x22, 0x3B) ++#define REG_SC_BK22_3C_L _PK_L_(0x22, 0x3C) ++#define REG_SC_BK22_3C_H _PK_H_(0x22, 0x3C) ++#define REG_SC_BK22_3D_L _PK_L_(0x22, 0x3D) ++#define REG_SC_BK22_3D_H _PK_H_(0x22, 0x3D) ++#define REG_SC_BK22_3E_L _PK_L_(0x22, 0x3E) ++#define REG_SC_BK22_3E_H _PK_H_(0x22, 0x3E) ++#define REG_SC_BK22_3F_L _PK_L_(0x22, 0x3F) ++#define REG_SC_BK22_3F_H _PK_H_(0x22, 0x3F) ++#define REG_SC_BK22_40_L _PK_L_(0x22, 0x40) ++#define REG_SC_BK22_40_H _PK_H_(0x22, 0x40) ++#define REG_SC_BK22_41_L _PK_L_(0x22, 0x41) ++#define REG_SC_BK22_41_H _PK_H_(0x22, 0x41) ++#define REG_SC_BK22_42_L _PK_L_(0x22, 0x42) ++#define REG_SC_BK22_42_H _PK_H_(0x22, 0x42) ++#define REG_SC_BK22_43_L _PK_L_(0x22, 0x43) ++#define REG_SC_BK22_43_H _PK_H_(0x22, 0x43) ++#define REG_SC_BK22_44_L _PK_L_(0x22, 0x44) ++#define REG_SC_BK22_44_H _PK_H_(0x22, 0x44) ++#define REG_SC_BK22_45_L _PK_L_(0x22, 0x45) ++#define REG_SC_BK22_45_H _PK_H_(0x22, 0x45) ++#define REG_SC_BK22_46_L _PK_L_(0x22, 0x46) ++#define REG_SC_BK22_46_H _PK_H_(0x22, 0x46) ++#define REG_SC_BK22_47_L _PK_L_(0x22, 0x47) ++#define REG_SC_BK22_47_H _PK_H_(0x22, 0x47) ++#define REG_SC_BK22_48_L _PK_L_(0x22, 0x48) ++#define REG_SC_BK22_48_H _PK_H_(0x22, 0x48) ++#define REG_SC_BK22_49_L _PK_L_(0x22, 0x49) ++#define REG_SC_BK22_49_H _PK_H_(0x22, 0x49) ++#define REG_SC_BK22_4A_L _PK_L_(0x22, 0x4A) ++#define REG_SC_BK22_4A_H _PK_H_(0x22, 0x4A) ++#define REG_SC_BK22_4B_L _PK_L_(0x22, 0x4B) ++#define REG_SC_BK22_4B_H _PK_H_(0x22, 0x4B) ++#define REG_SC_BK22_4C_L _PK_L_(0x22, 0x4C) ++#define REG_SC_BK22_4C_H _PK_H_(0x22, 0x4C) ++#define REG_SC_BK22_4D_L _PK_L_(0x22, 0x4D) ++#define REG_SC_BK22_4D_H _PK_H_(0x22, 0x4D) ++#define REG_SC_BK22_4E_L _PK_L_(0x22, 0x4E) ++#define REG_SC_BK22_4E_H _PK_H_(0x22, 0x4E) ++#define REG_SC_BK22_4F_L _PK_L_(0x22, 0x4F) ++#define REG_SC_BK22_4F_H _PK_H_(0x22, 0x4F) ++#define REG_SC_BK22_50_L _PK_L_(0x22, 0x50) ++#define REG_SC_BK22_50_H _PK_H_(0x22, 0x50) ++#define REG_SC_BK22_51_L _PK_L_(0x22, 0x51) ++#define REG_SC_BK22_51_H _PK_H_(0x22, 0x51) ++#define REG_SC_BK22_52_L _PK_L_(0x22, 0x52) ++#define REG_SC_BK22_52_H _PK_H_(0x22, 0x52) ++#define REG_SC_BK22_53_L _PK_L_(0x22, 0x53) ++#define REG_SC_BK22_53_H _PK_H_(0x22, 0x53) ++#define REG_SC_BK22_54_L _PK_L_(0x22, 0x54) ++#define REG_SC_BK22_54_H _PK_H_(0x22, 0x54) ++#define REG_SC_BK22_55_L _PK_L_(0x22, 0x55) ++#define REG_SC_BK22_55_H _PK_H_(0x22, 0x55) ++#define REG_SC_BK22_56_L _PK_L_(0x22, 0x56) ++#define REG_SC_BK22_56_H _PK_H_(0x22, 0x56) ++#define REG_SC_BK22_57_L _PK_L_(0x22, 0x57) ++#define REG_SC_BK22_57_H _PK_H_(0x22, 0x57) ++#define REG_SC_BK22_58_L _PK_L_(0x22, 0x58) ++#define REG_SC_BK22_58_H _PK_H_(0x22, 0x58) ++#define REG_SC_BK22_59_L _PK_L_(0x22, 0x59) ++#define REG_SC_BK22_59_H _PK_H_(0x22, 0x59) ++#define REG_SC_BK22_5A_L _PK_L_(0x22, 0x5A) ++#define REG_SC_BK22_5A_H _PK_H_(0x22, 0x5A) ++#define REG_SC_BK22_5B_L _PK_L_(0x22, 0x5B) ++#define REG_SC_BK22_5B_H _PK_H_(0x22, 0x5B) ++#define REG_SC_BK22_5C_L _PK_L_(0x22, 0x5C) ++#define REG_SC_BK22_5C_H _PK_H_(0x22, 0x5C) ++#define REG_SC_BK22_5D_L _PK_L_(0x22, 0x5D) ++#define REG_SC_BK22_5D_H _PK_H_(0x22, 0x5D) ++#define REG_SC_BK22_5E_L _PK_L_(0x22, 0x5E) ++#define REG_SC_BK22_5E_H _PK_H_(0x22, 0x5E) ++#define REG_SC_BK22_5F_L _PK_L_(0x22, 0x5F) ++#define REG_SC_BK22_5F_H _PK_H_(0x22, 0x5F) ++#define REG_SC_BK22_60_L _PK_L_(0x22, 0x60) ++#define REG_SC_BK22_60_H _PK_H_(0x22, 0x60) ++#define REG_SC_BK22_61_L _PK_L_(0x22, 0x61) ++#define REG_SC_BK22_61_H _PK_H_(0x22, 0x61) ++#define REG_SC_BK22_62_L _PK_L_(0x22, 0x62) ++#define REG_SC_BK22_62_H _PK_H_(0x22, 0x62) ++#define REG_SC_BK22_63_L _PK_L_(0x22, 0x63) ++#define REG_SC_BK22_63_H _PK_H_(0x22, 0x63) ++#define REG_SC_BK22_64_L _PK_L_(0x22, 0x64) ++#define REG_SC_BK22_64_H _PK_H_(0x22, 0x64) ++#define REG_SC_BK22_65_L _PK_L_(0x22, 0x65) ++#define REG_SC_BK22_65_H _PK_H_(0x22, 0x65) ++#define REG_SC_BK22_66_L _PK_L_(0x22, 0x66) ++#define REG_SC_BK22_66_H _PK_H_(0x22, 0x66) ++#define REG_SC_BK22_67_L _PK_L_(0x22, 0x67) ++#define REG_SC_BK22_67_H _PK_H_(0x22, 0x67) ++#define REG_SC_BK22_68_L _PK_L_(0x22, 0x68) ++#define REG_SC_BK22_68_H _PK_H_(0x22, 0x68) ++#define REG_SC_BK22_69_L _PK_L_(0x22, 0x69) ++#define REG_SC_BK22_69_H _PK_H_(0x22, 0x69) ++#define REG_SC_BK22_6A_L _PK_L_(0x22, 0x6A) ++#define REG_SC_BK22_6A_H _PK_H_(0x22, 0x6A) ++#define REG_SC_BK22_6B_L _PK_L_(0x22, 0x6B) ++#define REG_SC_BK22_6B_H _PK_H_(0x22, 0x6B) ++#define REG_SC_BK22_6C_L _PK_L_(0x22, 0x6C) ++#define REG_SC_BK22_6C_H _PK_H_(0x22, 0x6C) ++#define REG_SC_BK22_6D_L _PK_L_(0x22, 0x6D) ++#define REG_SC_BK22_6D_H _PK_H_(0x22, 0x6D) ++#define REG_SC_BK22_6E_L _PK_L_(0x22, 0x6E) ++#define REG_SC_BK22_6E_H _PK_H_(0x22, 0x6E) ++#define REG_SC_BK22_6F_L _PK_L_(0x22, 0x6F) ++#define REG_SC_BK22_6F_H _PK_H_(0x22, 0x6F) ++#define REG_SC_BK22_70_L _PK_L_(0x22, 0x70) ++#define REG_SC_BK22_70_H _PK_H_(0x22, 0x70) ++#define REG_SC_BK22_71_L _PK_L_(0x22, 0x71) ++#define REG_SC_BK22_71_H _PK_H_(0x22, 0x71) ++#define REG_SC_BK22_72_L _PK_L_(0x22, 0x72) ++#define REG_SC_BK22_72_H _PK_H_(0x22, 0x72) ++#define REG_SC_BK22_73_L _PK_L_(0x22, 0x73) ++#define REG_SC_BK22_73_H _PK_H_(0x22, 0x73) ++#define REG_SC_BK22_74_L _PK_L_(0x22, 0x74) ++#define REG_SC_BK22_74_H _PK_H_(0x22, 0x74) ++#define REG_SC_BK22_75_L _PK_L_(0x22, 0x75) ++#define REG_SC_BK22_75_H _PK_H_(0x22, 0x75) ++#define REG_SC_BK22_76_L _PK_L_(0x22, 0x76) ++#define REG_SC_BK22_76_H _PK_H_(0x22, 0x76) ++#define REG_SC_BK22_77_L _PK_L_(0x22, 0x77) ++#define REG_SC_BK22_77_H _PK_H_(0x22, 0x77) ++#define REG_SC_BK22_78_L _PK_L_(0x22, 0x78) ++#define REG_SC_BK22_78_H _PK_H_(0x22, 0x78) ++#define REG_SC_BK22_79_L _PK_L_(0x22, 0x79) ++#define REG_SC_BK22_79_H _PK_H_(0x22, 0x79) ++#define REG_SC_BK22_7A_L _PK_L_(0x22, 0x7A) ++#define REG_SC_BK22_7A_H _PK_H_(0x22, 0x7A) ++#define REG_SC_BK22_7B_L _PK_L_(0x22, 0x7B) ++#define REG_SC_BK22_7B_H _PK_H_(0x22, 0x7B) ++#define REG_SC_BK22_7C_L _PK_L_(0x22, 0x7C) ++#define REG_SC_BK22_7C_H _PK_H_(0x22, 0x7C) ++#define REG_SC_BK22_7D_L _PK_L_(0x22, 0x7D) ++#define REG_SC_BK22_7D_H _PK_H_(0x22, 0x7D) ++#define REG_SC_BK22_7E_L _PK_L_(0x22, 0x7E) ++#define REG_SC_BK22_7E_H _PK_H_(0x22, 0x7E) ++#define REG_SC_BK22_7F_L _PK_L_(0x22, 0x7F) ++#define REG_SC_BK22_7F_H _PK_H_(0x22, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK23_00_L _PK_L_(0x23, 0x00) ++#define REG_SC_BK23_00_H _PK_H_(0x23, 0x00) ++#define REG_SC_BK23_01_L _PK_L_(0x23, 0x01) ++#define REG_SC_BK23_01_H _PK_H_(0x23, 0x01) ++#define REG_SC_BK23_02_L _PK_L_(0x23, 0x02) ++#define REG_SC_BK23_02_H _PK_H_(0x23, 0x02) ++#define REG_SC_BK23_03_L _PK_L_(0x23, 0x03) ++#define REG_SC_BK23_03_H _PK_H_(0x23, 0x03) ++#define REG_SC_BK23_04_L _PK_L_(0x23, 0x04) ++#define REG_SC_BK23_04_H _PK_H_(0x23, 0x04) ++#define REG_SC_BK23_05_L _PK_L_(0x23, 0x05) ++#define REG_SC_BK23_05_H _PK_H_(0x23, 0x05) ++#define REG_SC_BK23_06_L _PK_L_(0x23, 0x06) ++#define REG_SC_BK23_06_H _PK_H_(0x23, 0x06) ++#define REG_SC_BK23_07_L _PK_L_(0x23, 0x07) ++#define REG_SC_BK23_07_H _PK_H_(0x23, 0x07) ++#define REG_SC_BK23_08_L _PK_L_(0x23, 0x08) ++#define REG_SC_BK23_08_H _PK_H_(0x23, 0x08) ++#define REG_SC_BK23_09_L _PK_L_(0x23, 0x09) ++#define REG_SC_BK23_09_H _PK_H_(0x23, 0x09) ++#define REG_SC_BK23_0A_L _PK_L_(0x23, 0x0A) ++#define REG_SC_BK23_0A_H _PK_H_(0x23, 0x0A) ++#define REG_SC_BK23_0B_L _PK_L_(0x23, 0x0B) ++#define REG_SC_BK23_0B_H _PK_H_(0x23, 0x0B) ++#define REG_SC_BK23_0C_L _PK_L_(0x23, 0x0C) ++#define REG_SC_BK23_0C_H _PK_H_(0x23, 0x0C) ++#define REG_SC_BK23_0D_L _PK_L_(0x23, 0x0D) ++#define REG_SC_BK23_0D_H _PK_H_(0x23, 0x0D) ++#define REG_SC_BK23_0E_L _PK_L_(0x23, 0x0E) ++#define REG_SC_BK23_0E_H _PK_H_(0x23, 0x0E) ++#define REG_SC_BK23_0F_L _PK_L_(0x23, 0x0F) ++#define REG_SC_BK23_0F_H _PK_H_(0x23, 0x0F) ++#define REG_SC_BK23_10_L _PK_L_(0x23, 0x10) ++#define REG_SC_BK23_10_H _PK_H_(0x23, 0x10) ++#define REG_SC_BK23_11_L _PK_L_(0x23, 0x11) ++#define REG_SC_BK23_11_H _PK_H_(0x23, 0x11) ++#define REG_SC_BK23_12_L _PK_L_(0x23, 0x12) ++#define REG_SC_BK23_12_H _PK_H_(0x23, 0x12) ++#define REG_SC_BK23_13_L _PK_L_(0x23, 0x13) ++#define REG_SC_BK23_13_H _PK_H_(0x23, 0x13) ++#define REG_SC_BK23_14_L _PK_L_(0x23, 0x14) ++#define REG_SC_BK23_14_H _PK_H_(0x23, 0x14) ++#define REG_SC_BK23_15_L _PK_L_(0x23, 0x15) ++#define REG_SC_BK23_15_H _PK_H_(0x23, 0x15) ++#define REG_SC_BK23_16_L _PK_L_(0x23, 0x16) ++#define REG_SC_BK23_16_H _PK_H_(0x23, 0x16) ++#define REG_SC_BK23_17_L _PK_L_(0x23, 0x17) ++#define REG_SC_BK23_17_H _PK_H_(0x23, 0x17) ++#define REG_SC_BK23_18_L _PK_L_(0x23, 0x18) ++#define REG_SC_BK23_18_H _PK_H_(0x23, 0x18) ++#define REG_SC_BK23_19_L _PK_L_(0x23, 0x19) ++#define REG_SC_BK23_19_H _PK_H_(0x23, 0x19) ++#define REG_SC_BK23_1A_L _PK_L_(0x23, 0x1A) ++#define REG_SC_BK23_1A_H _PK_H_(0x23, 0x1A) ++#define REG_SC_BK23_1B_L _PK_L_(0x23, 0x1B) ++#define REG_SC_BK23_1B_H _PK_H_(0x23, 0x1B) ++#define REG_SC_BK23_1C_L _PK_L_(0x23, 0x1C) ++#define REG_SC_BK23_1C_H _PK_H_(0x23, 0x1C) ++#define REG_SC_BK23_1D_L _PK_L_(0x23, 0x1D) ++#define REG_SC_BK23_1D_H _PK_H_(0x23, 0x1D) ++#define REG_SC_BK23_1E_L _PK_L_(0x23, 0x1E) ++#define REG_SC_BK23_1E_H _PK_H_(0x23, 0x1E) ++#define REG_SC_BK23_1F_L _PK_L_(0x23, 0x1F) ++#define REG_SC_BK23_1F_H _PK_H_(0x23, 0x1F) ++#define REG_SC_BK23_20_L _PK_L_(0x23, 0x20) ++#define REG_SC_BK23_20_H _PK_H_(0x23, 0x20) ++#define REG_SC_BK23_21_L _PK_L_(0x23, 0x21) ++#define REG_SC_BK23_21_H _PK_H_(0x23, 0x21) ++#define REG_SC_BK23_22_L _PK_L_(0x23, 0x22) ++#define REG_SC_BK23_22_H _PK_H_(0x23, 0x22) ++#define REG_SC_BK23_23_L _PK_L_(0x23, 0x23) ++#define REG_SC_BK23_23_H _PK_H_(0x23, 0x23) ++#define REG_SC_BK23_24_L _PK_L_(0x23, 0x24) ++#define REG_SC_BK23_24_H _PK_H_(0x23, 0x24) ++#define REG_SC_BK23_25_L _PK_L_(0x23, 0x25) ++#define REG_SC_BK23_25_H _PK_H_(0x23, 0x25) ++#define REG_SC_BK23_26_L _PK_L_(0x23, 0x26) ++#define REG_SC_BK23_26_H _PK_H_(0x23, 0x26) ++#define REG_SC_BK23_27_L _PK_L_(0x23, 0x27) ++#define REG_SC_BK23_27_H _PK_H_(0x23, 0x27) ++#define REG_SC_BK23_28_L _PK_L_(0x23, 0x28) ++#define REG_SC_BK23_28_H _PK_H_(0x23, 0x28) ++#define REG_SC_BK23_29_L _PK_L_(0x23, 0x29) ++#define REG_SC_BK23_29_H _PK_H_(0x23, 0x29) ++#define REG_SC_BK23_2A_L _PK_L_(0x23, 0x2A) ++#define REG_SC_BK23_2A_H _PK_H_(0x23, 0x2A) ++#define REG_SC_BK23_2B_L _PK_L_(0x23, 0x2B) ++#define REG_SC_BK23_2B_H _PK_H_(0x23, 0x2B) ++#define REG_SC_BK23_2C_L _PK_L_(0x23, 0x2C) ++#define REG_SC_BK23_2C_H _PK_H_(0x23, 0x2C) ++#define REG_SC_BK23_2D_L _PK_L_(0x23, 0x2D) ++#define REG_SC_BK23_2D_H _PK_H_(0x23, 0x2D) ++#define REG_SC_BK23_2E_L _PK_L_(0x23, 0x2E) ++#define REG_SC_BK23_2E_H _PK_H_(0x23, 0x2E) ++#define REG_SC_BK23_2F_L _PK_L_(0x23, 0x2F) ++#define REG_SC_BK23_2F_H _PK_H_(0x23, 0x2F) ++#define REG_SC_BK23_30_L _PK_L_(0x23, 0x30) ++#define REG_SC_BK23_30_H _PK_H_(0x23, 0x30) ++#define REG_SC_BK23_31_L _PK_L_(0x23, 0x31) ++#define REG_SC_BK23_31_H _PK_H_(0x23, 0x31) ++#define REG_SC_BK23_32_L _PK_L_(0x23, 0x32) ++#define REG_SC_BK23_32_H _PK_H_(0x23, 0x32) ++#define REG_SC_BK23_33_L _PK_L_(0x23, 0x33) ++#define REG_SC_BK23_33_H _PK_H_(0x23, 0x33) ++#define REG_SC_BK23_34_L _PK_L_(0x23, 0x34) ++#define REG_SC_BK23_34_H _PK_H_(0x23, 0x34) ++#define REG_SC_BK23_35_L _PK_L_(0x23, 0x35) ++#define REG_SC_BK23_35_H _PK_H_(0x23, 0x35) ++#define REG_SC_BK23_36_L _PK_L_(0x23, 0x36) ++#define REG_SC_BK23_36_H _PK_H_(0x23, 0x36) ++#define REG_SC_BK23_37_L _PK_L_(0x23, 0x37) ++#define REG_SC_BK23_37_H _PK_H_(0x23, 0x37) ++#define REG_SC_BK23_38_L _PK_L_(0x23, 0x38) ++#define REG_SC_BK23_38_H _PK_H_(0x23, 0x38) ++#define REG_SC_BK23_39_L _PK_L_(0x23, 0x39) ++#define REG_SC_BK23_39_H _PK_H_(0x23, 0x39) ++#define REG_SC_BK23_3A_L _PK_L_(0x23, 0x3A) ++#define REG_SC_BK23_3A_H _PK_H_(0x23, 0x3A) ++#define REG_SC_BK23_3B_L _PK_L_(0x23, 0x3B) ++#define REG_SC_BK23_3B_H _PK_H_(0x23, 0x3B) ++#define REG_SC_BK23_3C_L _PK_L_(0x23, 0x3C) ++#define REG_SC_BK23_3C_H _PK_H_(0x23, 0x3C) ++#define REG_SC_BK23_3D_L _PK_L_(0x23, 0x3D) ++#define REG_SC_BK23_3D_H _PK_H_(0x23, 0x3D) ++#define REG_SC_BK23_3E_L _PK_L_(0x23, 0x3E) ++#define REG_SC_BK23_3E_H _PK_H_(0x23, 0x3E) ++#define REG_SC_BK23_3F_L _PK_L_(0x23, 0x3F) ++#define REG_SC_BK23_3F_H _PK_H_(0x23, 0x3F) ++#define REG_SC_BK23_40_L _PK_L_(0x23, 0x40) ++#define REG_SC_BK23_40_H _PK_H_(0x23, 0x40) ++#define REG_SC_BK23_41_L _PK_L_(0x23, 0x41) ++#define REG_SC_BK23_41_H _PK_H_(0x23, 0x41) ++#define REG_SC_BK23_42_L _PK_L_(0x23, 0x42) ++#define REG_SC_BK23_42_H _PK_H_(0x23, 0x42) ++#define REG_SC_BK23_43_L _PK_L_(0x23, 0x43) ++#define REG_SC_BK23_43_H _PK_H_(0x23, 0x43) ++#define REG_SC_BK23_44_L _PK_L_(0x23, 0x44) ++#define REG_SC_BK23_44_H _PK_H_(0x23, 0x44) ++#define REG_SC_BK23_45_L _PK_L_(0x23, 0x45) ++#define REG_SC_BK23_45_H _PK_H_(0x23, 0x45) ++#define REG_SC_BK23_46_L _PK_L_(0x23, 0x46) ++#define REG_SC_BK23_46_H _PK_H_(0x23, 0x46) ++#define REG_SC_BK23_47_L _PK_L_(0x23, 0x47) ++#define REG_SC_BK23_47_H _PK_H_(0x23, 0x47) ++#define REG_SC_BK23_48_L _PK_L_(0x23, 0x48) ++#define REG_SC_BK23_48_H _PK_H_(0x23, 0x48) ++#define REG_SC_BK23_49_L _PK_L_(0x23, 0x49) ++#define REG_SC_BK23_49_H _PK_H_(0x23, 0x49) ++#define REG_SC_BK23_4A_L _PK_L_(0x23, 0x4A) ++#define REG_SC_BK23_4A_H _PK_H_(0x23, 0x4A) ++#define REG_SC_BK23_4B_L _PK_L_(0x23, 0x4B) ++#define REG_SC_BK23_4B_H _PK_H_(0x23, 0x4B) ++#define REG_SC_BK23_4C_L _PK_L_(0x23, 0x4C) ++#define REG_SC_BK23_4C_H _PK_H_(0x23, 0x4C) ++#define REG_SC_BK23_4D_L _PK_L_(0x23, 0x4D) ++#define REG_SC_BK23_4D_H _PK_H_(0x23, 0x4D) ++#define REG_SC_BK23_4E_L _PK_L_(0x23, 0x4E) ++#define REG_SC_BK23_4E_H _PK_H_(0x23, 0x4E) ++#define REG_SC_BK23_4F_L _PK_L_(0x23, 0x4F) ++#define REG_SC_BK23_4F_H _PK_H_(0x23, 0x4F) ++#define REG_SC_BK23_50_L _PK_L_(0x23, 0x50) ++#define REG_SC_BK23_50_H _PK_H_(0x23, 0x50) ++#define REG_SC_BK23_51_L _PK_L_(0x23, 0x51) ++#define REG_SC_BK23_51_H _PK_H_(0x23, 0x51) ++#define REG_SC_BK23_52_L _PK_L_(0x23, 0x52) ++#define REG_SC_BK23_52_H _PK_H_(0x23, 0x52) ++#define REG_SC_BK23_53_L _PK_L_(0x23, 0x53) ++#define REG_SC_BK23_53_H _PK_H_(0x23, 0x53) ++#define REG_SC_BK23_54_L _PK_L_(0x23, 0x54) ++#define REG_SC_BK23_54_H _PK_H_(0x23, 0x54) ++#define REG_SC_BK23_55_L _PK_L_(0x23, 0x55) ++#define REG_SC_BK23_55_H _PK_H_(0x23, 0x55) ++#define REG_SC_BK23_56_L _PK_L_(0x23, 0x56) ++#define REG_SC_BK23_56_H _PK_H_(0x23, 0x56) ++#define REG_SC_BK23_57_L _PK_L_(0x23, 0x57) ++#define REG_SC_BK23_57_H _PK_H_(0x23, 0x57) ++#define REG_SC_BK23_58_L _PK_L_(0x23, 0x58) ++#define REG_SC_BK23_58_H _PK_H_(0x23, 0x58) ++#define REG_SC_BK23_59_L _PK_L_(0x23, 0x59) ++#define REG_SC_BK23_59_H _PK_H_(0x23, 0x59) ++#define REG_SC_BK23_5A_L _PK_L_(0x23, 0x5A) ++#define REG_SC_BK23_5A_H _PK_H_(0x23, 0x5A) ++#define REG_SC_BK23_5B_L _PK_L_(0x23, 0x5B) ++#define REG_SC_BK23_5B_H _PK_H_(0x23, 0x5B) ++#define REG_SC_BK23_5C_L _PK_L_(0x23, 0x5C) ++#define REG_SC_BK23_5C_H _PK_H_(0x23, 0x5C) ++#define REG_SC_BK23_5D_L _PK_L_(0x23, 0x5D) ++#define REG_SC_BK23_5D_H _PK_H_(0x23, 0x5D) ++#define REG_SC_BK23_5E_L _PK_L_(0x23, 0x5E) ++#define REG_SC_BK23_5E_H _PK_H_(0x23, 0x5E) ++#define REG_SC_BK23_5F_L _PK_L_(0x23, 0x5F) ++#define REG_SC_BK23_5F_H _PK_H_(0x23, 0x5F) ++#define REG_SC_BK23_60_L _PK_L_(0x23, 0x60) ++#define REG_SC_BK23_60_H _PK_H_(0x23, 0x60) ++#define REG_SC_BK23_61_L _PK_L_(0x23, 0x61) ++#define REG_SC_BK23_61_H _PK_H_(0x23, 0x61) ++#define REG_SC_BK23_62_L _PK_L_(0x23, 0x62) ++#define REG_SC_BK23_62_H _PK_H_(0x23, 0x62) ++#define REG_SC_BK23_63_L _PK_L_(0x23, 0x63) ++#define REG_SC_BK23_63_H _PK_H_(0x23, 0x63) ++#define REG_SC_BK23_64_L _PK_L_(0x23, 0x64) ++#define REG_SC_BK23_64_H _PK_H_(0x23, 0x64) ++#define REG_SC_BK23_65_L _PK_L_(0x23, 0x65) ++#define REG_SC_BK23_65_H _PK_H_(0x23, 0x65) ++#define REG_SC_BK23_66_L _PK_L_(0x23, 0x66) ++#define REG_SC_BK23_66_H _PK_H_(0x23, 0x66) ++#define REG_SC_BK23_67_L _PK_L_(0x23, 0x67) ++#define REG_SC_BK23_67_H _PK_H_(0x23, 0x67) ++#define REG_SC_BK23_68_L _PK_L_(0x23, 0x68) ++#define REG_SC_BK23_68_H _PK_H_(0x23, 0x68) ++#define REG_SC_BK23_69_L _PK_L_(0x23, 0x69) ++#define REG_SC_BK23_69_H _PK_H_(0x23, 0x69) ++#define REG_SC_BK23_6A_L _PK_L_(0x23, 0x6A) ++#define REG_SC_BK23_6A_H _PK_H_(0x23, 0x6A) ++#define REG_SC_BK23_6B_L _PK_L_(0x23, 0x6B) ++#define REG_SC_BK23_6B_H _PK_H_(0x23, 0x6B) ++#define REG_SC_BK23_6C_L _PK_L_(0x23, 0x6C) ++#define REG_SC_BK23_6C_H _PK_H_(0x23, 0x6C) ++#define REG_SC_BK23_6D_L _PK_L_(0x23, 0x6D) ++#define REG_SC_BK23_6D_H _PK_H_(0x23, 0x6D) ++#define REG_SC_BK23_6E_L _PK_L_(0x23, 0x6E) ++#define REG_SC_BK23_6E_H _PK_H_(0x23, 0x6E) ++#define REG_SC_BK23_6F_L _PK_L_(0x23, 0x6F) ++#define REG_SC_BK23_6F_H _PK_H_(0x23, 0x6F) ++#define REG_SC_BK23_70_L _PK_L_(0x23, 0x70) ++#define REG_SC_BK23_70_H _PK_H_(0x23, 0x70) ++#define REG_SC_BK23_71_L _PK_L_(0x23, 0x71) ++#define REG_SC_BK23_71_H _PK_H_(0x23, 0x71) ++#define REG_SC_BK23_72_L _PK_L_(0x23, 0x72) ++#define REG_SC_BK23_72_H _PK_H_(0x23, 0x72) ++#define REG_SC_BK23_73_L _PK_L_(0x23, 0x73) ++#define REG_SC_BK23_73_H _PK_H_(0x23, 0x73) ++#define REG_SC_BK23_74_L _PK_L_(0x23, 0x74) ++#define REG_SC_BK23_74_H _PK_H_(0x23, 0x74) ++#define REG_SC_BK23_75_L _PK_L_(0x23, 0x75) ++#define REG_SC_BK23_75_H _PK_H_(0x23, 0x75) ++#define REG_SC_BK23_76_L _PK_L_(0x23, 0x76) ++#define REG_SC_BK23_76_H _PK_H_(0x23, 0x76) ++#define REG_SC_BK23_77_L _PK_L_(0x23, 0x77) ++#define REG_SC_BK23_77_H _PK_H_(0x23, 0x77) ++#define REG_SC_BK23_78_L _PK_L_(0x23, 0x78) ++#define REG_SC_BK23_78_H _PK_H_(0x23, 0x78) ++#define REG_SC_BK23_79_L _PK_L_(0x23, 0x79) ++#define REG_SC_BK23_79_H _PK_H_(0x23, 0x79) ++#define REG_SC_BK23_7A_L _PK_L_(0x23, 0x7A) ++#define REG_SC_BK23_7A_H _PK_H_(0x23, 0x7A) ++#define REG_SC_BK23_7B_L _PK_L_(0x23, 0x7B) ++#define REG_SC_BK23_7B_H _PK_H_(0x23, 0x7B) ++#define REG_SC_BK23_7C_L _PK_L_(0x23, 0x7C) ++#define REG_SC_BK23_7C_H _PK_H_(0x23, 0x7C) ++#define REG_SC_BK23_7D_L _PK_L_(0x23, 0x7D) ++#define REG_SC_BK23_7D_H _PK_H_(0x23, 0x7D) ++#define REG_SC_BK23_7E_L _PK_L_(0x23, 0x7E) ++#define REG_SC_BK23_7E_H _PK_H_(0x23, 0x7E) ++#define REG_SC_BK23_7F_L _PK_L_(0x23, 0x7F) ++#define REG_SC_BK23_7F_H _PK_H_(0x23, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK24_00_L _PK_L_(0x24, 0x00) ++#define REG_SC_BK24_00_H _PK_H_(0x24, 0x00) ++#define REG_SC_BK24_01_L _PK_L_(0x24, 0x01) ++#define REG_SC_BK24_01_H _PK_H_(0x24, 0x01) ++#define REG_SC_BK24_02_L _PK_L_(0x24, 0x02) ++#define REG_SC_BK24_02_H _PK_H_(0x24, 0x02) ++#define REG_SC_BK24_03_L _PK_L_(0x24, 0x03) ++#define REG_SC_BK24_03_H _PK_H_(0x24, 0x03) ++#define REG_SC_BK24_04_L _PK_L_(0x24, 0x04) ++#define REG_SC_BK24_04_H _PK_H_(0x24, 0x04) ++#define REG_SC_BK24_05_L _PK_L_(0x24, 0x05) ++#define REG_SC_BK24_05_H _PK_H_(0x24, 0x05) ++#define REG_SC_BK24_06_L _PK_L_(0x24, 0x06) ++#define REG_SC_BK24_06_H _PK_H_(0x24, 0x06) ++#define REG_SC_BK24_07_L _PK_L_(0x24, 0x07) ++#define REG_SC_BK24_07_H _PK_H_(0x24, 0x07) ++#define REG_SC_BK24_08_L _PK_L_(0x24, 0x08) ++#define REG_SC_BK24_08_H _PK_H_(0x24, 0x08) ++#define REG_SC_BK24_09_L _PK_L_(0x24, 0x09) ++#define REG_SC_BK24_09_H _PK_H_(0x24, 0x09) ++#define REG_SC_BK24_0A_L _PK_L_(0x24, 0x0A) ++#define REG_SC_BK24_0A_H _PK_H_(0x24, 0x0A) ++#define REG_SC_BK24_0B_L _PK_L_(0x24, 0x0B) ++#define REG_SC_BK24_0B_H _PK_H_(0x24, 0x0B) ++#define REG_SC_BK24_0C_L _PK_L_(0x24, 0x0C) ++#define REG_SC_BK24_0C_H _PK_H_(0x24, 0x0C) ++#define REG_SC_BK24_0D_L _PK_L_(0x24, 0x0D) ++#define REG_SC_BK24_0D_H _PK_H_(0x24, 0x0D) ++#define REG_SC_BK24_0E_L _PK_L_(0x24, 0x0E) ++#define REG_SC_BK24_0E_H _PK_H_(0x24, 0x0E) ++#define REG_SC_BK24_0F_L _PK_L_(0x24, 0x0F) ++#define REG_SC_BK24_0F_H _PK_H_(0x24, 0x0F) ++#define REG_SC_BK24_10_L _PK_L_(0x24, 0x10) ++#define REG_SC_BK24_10_H _PK_H_(0x24, 0x10) ++#define REG_SC_BK24_11_L _PK_L_(0x24, 0x11) ++#define REG_SC_BK24_11_H _PK_H_(0x24, 0x11) ++#define REG_SC_BK24_12_L _PK_L_(0x24, 0x12) ++#define REG_SC_BK24_12_H _PK_H_(0x24, 0x12) ++#define REG_SC_BK24_13_L _PK_L_(0x24, 0x13) ++#define REG_SC_BK24_13_H _PK_H_(0x24, 0x13) ++#define REG_SC_BK24_14_L _PK_L_(0x24, 0x14) ++#define REG_SC_BK24_14_H _PK_H_(0x24, 0x14) ++#define REG_SC_BK24_15_L _PK_L_(0x24, 0x15) ++#define REG_SC_BK24_15_H _PK_H_(0x24, 0x15) ++#define REG_SC_BK24_16_L _PK_L_(0x24, 0x16) ++#define REG_SC_BK24_16_H _PK_H_(0x24, 0x16) ++#define REG_SC_BK24_17_L _PK_L_(0x24, 0x17) ++#define REG_SC_BK24_17_H _PK_H_(0x24, 0x17) ++#define REG_SC_BK24_18_L _PK_L_(0x24, 0x18) ++#define REG_SC_BK24_18_H _PK_H_(0x24, 0x18) ++#define REG_SC_BK24_19_L _PK_L_(0x24, 0x19) ++#define REG_SC_BK24_19_H _PK_H_(0x24, 0x19) ++#define REG_SC_BK24_1A_L _PK_L_(0x24, 0x1A) ++#define REG_SC_BK24_1A_H _PK_H_(0x24, 0x1A) ++#define REG_SC_BK24_1B_L _PK_L_(0x24, 0x1B) ++#define REG_SC_BK24_1B_H _PK_H_(0x24, 0x1B) ++#define REG_SC_BK24_1C_L _PK_L_(0x24, 0x1C) ++#define REG_SC_BK24_1C_H _PK_H_(0x24, 0x1C) ++#define REG_SC_BK24_1D_L _PK_L_(0x24, 0x1D) ++#define REG_SC_BK24_1D_H _PK_H_(0x24, 0x1D) ++#define REG_SC_BK24_1E_L _PK_L_(0x24, 0x1E) ++#define REG_SC_BK24_1E_H _PK_H_(0x24, 0x1E) ++#define REG_SC_BK24_1F_L _PK_L_(0x24, 0x1F) ++#define REG_SC_BK24_1F_H _PK_H_(0x24, 0x1F) ++#define REG_SC_BK24_20_L _PK_L_(0x24, 0x20) ++#define REG_SC_BK24_20_H _PK_H_(0x24, 0x20) ++#define REG_SC_BK24_21_L _PK_L_(0x24, 0x21) ++#define REG_SC_BK24_21_H _PK_H_(0x24, 0x21) ++#define REG_SC_BK24_22_L _PK_L_(0x24, 0x22) ++#define REG_SC_BK24_22_H _PK_H_(0x24, 0x22) ++#define REG_SC_BK24_23_L _PK_L_(0x24, 0x23) ++#define REG_SC_BK24_23_H _PK_H_(0x24, 0x23) ++#define REG_SC_BK24_24_L _PK_L_(0x24, 0x24) ++#define REG_SC_BK24_24_H _PK_H_(0x24, 0x24) ++#define REG_SC_BK24_25_L _PK_L_(0x24, 0x25) ++#define REG_SC_BK24_25_H _PK_H_(0x24, 0x25) ++#define REG_SC_BK24_26_L _PK_L_(0x24, 0x26) ++#define REG_SC_BK24_26_H _PK_H_(0x24, 0x26) ++#define REG_SC_BK24_27_L _PK_L_(0x24, 0x27) ++#define REG_SC_BK24_27_H _PK_H_(0x24, 0x27) ++#define REG_SC_BK24_28_L _PK_L_(0x24, 0x28) ++#define REG_SC_BK24_28_H _PK_H_(0x24, 0x28) ++#define REG_SC_BK24_29_L _PK_L_(0x24, 0x29) ++#define REG_SC_BK24_29_H _PK_H_(0x24, 0x29) ++#define REG_SC_BK24_2A_L _PK_L_(0x24, 0x2A) ++#define REG_SC_BK24_2A_H _PK_H_(0x24, 0x2A) ++#define REG_SC_BK24_2B_L _PK_L_(0x24, 0x2B) ++#define REG_SC_BK24_2B_H _PK_H_(0x24, 0x2B) ++#define REG_SC_BK24_2C_L _PK_L_(0x24, 0x2C) ++#define REG_SC_BK24_2C_H _PK_H_(0x24, 0x2C) ++#define REG_SC_BK24_2D_L _PK_L_(0x24, 0x2D) ++#define REG_SC_BK24_2D_H _PK_H_(0x24, 0x2D) ++#define REG_SC_BK24_2E_L _PK_L_(0x24, 0x2E) ++#define REG_SC_BK24_2E_H _PK_H_(0x24, 0x2E) ++#define REG_SC_BK24_2F_L _PK_L_(0x24, 0x2F) ++#define REG_SC_BK24_2F_H _PK_H_(0x24, 0x2F) ++#define REG_SC_BK24_30_L _PK_L_(0x24, 0x30) ++#define REG_SC_BK24_30_H _PK_H_(0x24, 0x30) ++#define REG_SC_BK24_31_L _PK_L_(0x24, 0x31) ++#define REG_SC_BK24_31_H _PK_H_(0x24, 0x31) ++#define REG_SC_BK24_32_L _PK_L_(0x24, 0x32) ++#define REG_SC_BK24_32_H _PK_H_(0x24, 0x32) ++#define REG_SC_BK24_33_L _PK_L_(0x24, 0x33) ++#define REG_SC_BK24_33_H _PK_H_(0x24, 0x33) ++#define REG_SC_BK24_34_L _PK_L_(0x24, 0x34) ++#define REG_SC_BK24_34_H _PK_H_(0x24, 0x34) ++#define REG_SC_BK24_35_L _PK_L_(0x24, 0x35) ++#define REG_SC_BK24_35_H _PK_H_(0x24, 0x35) ++#define REG_SC_BK24_36_L _PK_L_(0x24, 0x36) ++#define REG_SC_BK24_36_H _PK_H_(0x24, 0x36) ++#define REG_SC_BK24_37_L _PK_L_(0x24, 0x37) ++#define REG_SC_BK24_37_H _PK_H_(0x24, 0x37) ++#define REG_SC_BK24_38_L _PK_L_(0x24, 0x38) ++#define REG_SC_BK24_38_H _PK_H_(0x24, 0x38) ++#define REG_SC_BK24_39_L _PK_L_(0x24, 0x39) ++#define REG_SC_BK24_39_H _PK_H_(0x24, 0x39) ++#define REG_SC_BK24_3A_L _PK_L_(0x24, 0x3A) ++#define REG_SC_BK24_3A_H _PK_H_(0x24, 0x3A) ++#define REG_SC_BK24_3B_L _PK_L_(0x24, 0x3B) ++#define REG_SC_BK24_3B_H _PK_H_(0x24, 0x3B) ++#define REG_SC_BK24_3C_L _PK_L_(0x24, 0x3C) ++#define REG_SC_BK24_3C_H _PK_H_(0x24, 0x3C) ++#define REG_SC_BK24_3D_L _PK_L_(0x24, 0x3D) ++#define REG_SC_BK24_3D_H _PK_H_(0x24, 0x3D) ++#define REG_SC_BK24_3E_L _PK_L_(0x24, 0x3E) ++#define REG_SC_BK24_3E_H _PK_H_(0x24, 0x3E) ++#define REG_SC_BK24_3F_L _PK_L_(0x24, 0x3F) ++#define REG_SC_BK24_3F_H _PK_H_(0x24, 0x3F) ++#define REG_SC_BK24_40_L _PK_L_(0x24, 0x40) ++#define REG_SC_BK24_40_H _PK_H_(0x24, 0x40) ++#define REG_SC_BK24_41_L _PK_L_(0x24, 0x41) ++#define REG_SC_BK24_41_H _PK_H_(0x24, 0x41) ++#define REG_SC_BK24_42_L _PK_L_(0x24, 0x42) ++#define REG_SC_BK24_42_H _PK_H_(0x24, 0x42) ++#define REG_SC_BK24_43_L _PK_L_(0x24, 0x43) ++#define REG_SC_BK24_43_H _PK_H_(0x24, 0x43) ++#define REG_SC_BK24_44_L _PK_L_(0x24, 0x44) ++#define REG_SC_BK24_44_H _PK_H_(0x24, 0x44) ++#define REG_SC_BK24_45_L _PK_L_(0x24, 0x45) ++#define REG_SC_BK24_45_H _PK_H_(0x24, 0x45) ++#define REG_SC_BK24_46_L _PK_L_(0x24, 0x46) ++#define REG_SC_BK24_46_H _PK_H_(0x24, 0x46) ++#define REG_SC_BK24_47_L _PK_L_(0x24, 0x47) ++#define REG_SC_BK24_47_H _PK_H_(0x24, 0x47) ++#define REG_SC_BK24_48_L _PK_L_(0x24, 0x48) ++#define REG_SC_BK24_48_H _PK_H_(0x24, 0x48) ++#define REG_SC_BK24_49_L _PK_L_(0x24, 0x49) ++#define REG_SC_BK24_49_H _PK_H_(0x24, 0x49) ++#define REG_SC_BK24_4A_L _PK_L_(0x24, 0x4A) ++#define REG_SC_BK24_4A_H _PK_H_(0x24, 0x4A) ++#define REG_SC_BK24_4B_L _PK_L_(0x24, 0x4B) ++#define REG_SC_BK24_4B_H _PK_H_(0x24, 0x4B) ++#define REG_SC_BK24_4C_L _PK_L_(0x24, 0x4C) ++#define REG_SC_BK24_4C_H _PK_H_(0x24, 0x4C) ++#define REG_SC_BK24_4D_L _PK_L_(0x24, 0x4D) ++#define REG_SC_BK24_4D_H _PK_H_(0x24, 0x4D) ++#define REG_SC_BK24_4E_L _PK_L_(0x24, 0x4E) ++#define REG_SC_BK24_4E_H _PK_H_(0x24, 0x4E) ++#define REG_SC_BK24_4F_L _PK_L_(0x24, 0x4F) ++#define REG_SC_BK24_4F_H _PK_H_(0x24, 0x4F) ++#define REG_SC_BK24_50_L _PK_L_(0x24, 0x50) ++#define REG_SC_BK24_50_H _PK_H_(0x24, 0x50) ++#define REG_SC_BK24_51_L _PK_L_(0x24, 0x51) ++#define REG_SC_BK24_51_H _PK_H_(0x24, 0x51) ++#define REG_SC_BK24_52_L _PK_L_(0x24, 0x52) ++#define REG_SC_BK24_52_H _PK_H_(0x24, 0x52) ++#define REG_SC_BK24_53_L _PK_L_(0x24, 0x53) ++#define REG_SC_BK24_53_H _PK_H_(0x24, 0x53) ++#define REG_SC_BK24_54_L _PK_L_(0x24, 0x54) ++#define REG_SC_BK24_54_H _PK_H_(0x24, 0x54) ++#define REG_SC_BK24_55_L _PK_L_(0x24, 0x55) ++#define REG_SC_BK24_55_H _PK_H_(0x24, 0x55) ++#define REG_SC_BK24_56_L _PK_L_(0x24, 0x56) ++#define REG_SC_BK24_56_H _PK_H_(0x24, 0x56) ++#define REG_SC_BK24_57_L _PK_L_(0x24, 0x57) ++#define REG_SC_BK24_57_H _PK_H_(0x24, 0x57) ++#define REG_SC_BK24_58_L _PK_L_(0x24, 0x58) ++#define REG_SC_BK24_58_H _PK_H_(0x24, 0x58) ++#define REG_SC_BK24_59_L _PK_L_(0x24, 0x59) ++#define REG_SC_BK24_59_H _PK_H_(0x24, 0x59) ++#define REG_SC_BK24_5A_L _PK_L_(0x24, 0x5A) ++#define REG_SC_BK24_5A_H _PK_H_(0x24, 0x5A) ++#define REG_SC_BK24_5B_L _PK_L_(0x24, 0x5B) ++#define REG_SC_BK24_5B_H _PK_H_(0x24, 0x5B) ++#define REG_SC_BK24_5C_L _PK_L_(0x24, 0x5C) ++#define REG_SC_BK24_5C_H _PK_H_(0x24, 0x5C) ++#define REG_SC_BK24_5D_L _PK_L_(0x24, 0x5D) ++#define REG_SC_BK24_5D_H _PK_H_(0x24, 0x5D) ++#define REG_SC_BK24_5E_L _PK_L_(0x24, 0x5E) ++#define REG_SC_BK24_5E_H _PK_H_(0x24, 0x5E) ++#define REG_SC_BK24_5F_L _PK_L_(0x24, 0x5F) ++#define REG_SC_BK24_5F_H _PK_H_(0x24, 0x5F) ++#define REG_SC_BK24_60_L _PK_L_(0x24, 0x60) ++#define REG_SC_BK24_60_H _PK_H_(0x24, 0x60) ++#define REG_SC_BK24_61_L _PK_L_(0x24, 0x61) ++#define REG_SC_BK24_61_H _PK_H_(0x24, 0x61) ++#define REG_SC_BK24_62_L _PK_L_(0x24, 0x62) ++#define REG_SC_BK24_62_H _PK_H_(0x24, 0x62) ++#define REG_SC_BK24_63_L _PK_L_(0x24, 0x63) ++#define REG_SC_BK24_63_H _PK_H_(0x24, 0x63) ++#define REG_SC_BK24_64_L _PK_L_(0x24, 0x64) ++#define REG_SC_BK24_64_H _PK_H_(0x24, 0x64) ++#define REG_SC_BK24_65_L _PK_L_(0x24, 0x65) ++#define REG_SC_BK24_65_H _PK_H_(0x24, 0x65) ++#define REG_SC_BK24_66_L _PK_L_(0x24, 0x66) ++#define REG_SC_BK24_66_H _PK_H_(0x24, 0x66) ++#define REG_SC_BK24_67_L _PK_L_(0x24, 0x67) ++#define REG_SC_BK24_67_H _PK_H_(0x24, 0x67) ++#define REG_SC_BK24_68_L _PK_L_(0x24, 0x68) ++#define REG_SC_BK24_68_H _PK_H_(0x24, 0x68) ++#define REG_SC_BK24_69_L _PK_L_(0x24, 0x69) ++#define REG_SC_BK24_69_H _PK_H_(0x24, 0x69) ++#define REG_SC_BK24_6A_L _PK_L_(0x24, 0x6A) ++#define REG_SC_BK24_6A_H _PK_H_(0x24, 0x6A) ++#define REG_SC_BK24_6B_L _PK_L_(0x24, 0x6B) ++#define REG_SC_BK24_6B_H _PK_H_(0x24, 0x6B) ++#define REG_SC_BK24_6C_L _PK_L_(0x24, 0x6C) ++#define REG_SC_BK24_6C_H _PK_H_(0x24, 0x6C) ++#define REG_SC_BK24_6D_L _PK_L_(0x24, 0x6D) ++#define REG_SC_BK24_6D_H _PK_H_(0x24, 0x6D) ++#define REG_SC_BK24_6E_L _PK_L_(0x24, 0x6E) ++#define REG_SC_BK24_6E_H _PK_H_(0x24, 0x6E) ++#define REG_SC_BK24_6F_L _PK_L_(0x24, 0x6F) ++#define REG_SC_BK24_6F_H _PK_H_(0x24, 0x6F) ++#define REG_SC_BK24_70_L _PK_L_(0x24, 0x70) ++#define REG_SC_BK24_70_H _PK_H_(0x24, 0x70) ++#define REG_SC_BK24_71_L _PK_L_(0x24, 0x71) ++#define REG_SC_BK24_71_H _PK_H_(0x24, 0x71) ++#define REG_SC_BK24_72_L _PK_L_(0x24, 0x72) ++#define REG_SC_BK24_72_H _PK_H_(0x24, 0x72) ++#define REG_SC_BK24_73_L _PK_L_(0x24, 0x73) ++#define REG_SC_BK24_73_H _PK_H_(0x24, 0x73) ++#define REG_SC_BK24_74_L _PK_L_(0x24, 0x74) ++#define REG_SC_BK24_74_H _PK_H_(0x24, 0x74) ++#define REG_SC_BK24_75_L _PK_L_(0x24, 0x75) ++#define REG_SC_BK24_75_H _PK_H_(0x24, 0x75) ++#define REG_SC_BK24_76_L _PK_L_(0x24, 0x76) ++#define REG_SC_BK24_76_H _PK_H_(0x24, 0x76) ++#define REG_SC_BK24_77_L _PK_L_(0x24, 0x77) ++#define REG_SC_BK24_77_H _PK_H_(0x24, 0x77) ++#define REG_SC_BK24_78_L _PK_L_(0x24, 0x78) ++#define REG_SC_BK24_78_H _PK_H_(0x24, 0x78) ++#define REG_SC_BK24_79_L _PK_L_(0x24, 0x79) ++#define REG_SC_BK24_79_H _PK_H_(0x24, 0x79) ++#define REG_SC_BK24_7A_L _PK_L_(0x24, 0x7A) ++#define REG_SC_BK24_7A_H _PK_H_(0x24, 0x7A) ++#define REG_SC_BK24_7B_L _PK_L_(0x24, 0x7B) ++#define REG_SC_BK24_7B_H _PK_H_(0x24, 0x7B) ++#define REG_SC_BK24_7C_L _PK_L_(0x24, 0x7C) ++#define REG_SC_BK24_7C_H _PK_H_(0x24, 0x7C) ++#define REG_SC_BK24_7D_L _PK_L_(0x24, 0x7D) ++#define REG_SC_BK24_7D_H _PK_H_(0x24, 0x7D) ++#define REG_SC_BK24_7E_L _PK_L_(0x24, 0x7E) ++#define REG_SC_BK24_7E_H _PK_H_(0x24, 0x7E) ++#define REG_SC_BK24_7F_L _PK_L_(0x24, 0x7F) ++#define REG_SC_BK24_7F_H _PK_H_(0x24, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK25_00_L _PK_L_(0x25, 0x00) ++#define REG_SC_BK25_00_H _PK_H_(0x25, 0x00) ++#define REG_SC_BK25_01_L _PK_L_(0x25, 0x01) ++#define REG_SC_BK25_01_H _PK_H_(0x25, 0x01) ++#define REG_SC_BK25_02_L _PK_L_(0x25, 0x02) ++#define REG_SC_BK25_02_H _PK_H_(0x25, 0x02) ++#define REG_SC_BK25_03_L _PK_L_(0x25, 0x03) ++#define REG_SC_BK25_03_H _PK_H_(0x25, 0x03) ++#define REG_SC_BK25_04_L _PK_L_(0x25, 0x04) ++#define REG_SC_BK25_04_H _PK_H_(0x25, 0x04) ++#define REG_SC_BK25_05_L _PK_L_(0x25, 0x05) ++#define REG_SC_BK25_05_H _PK_H_(0x25, 0x05) ++#define REG_SC_BK25_06_L _PK_L_(0x25, 0x06) ++#define REG_SC_BK25_06_H _PK_H_(0x25, 0x06) ++#define REG_SC_BK25_07_L _PK_L_(0x25, 0x07) ++#define REG_SC_BK25_07_H _PK_H_(0x25, 0x07) ++#define REG_SC_BK25_08_L _PK_L_(0x25, 0x08) ++#define REG_SC_BK25_08_H _PK_H_(0x25, 0x08) ++#define REG_SC_BK25_09_L _PK_L_(0x25, 0x09) ++#define REG_SC_BK25_09_H _PK_H_(0x25, 0x09) ++#define REG_SC_BK25_0A_L _PK_L_(0x25, 0x0A) ++#define REG_SC_BK25_0A_H _PK_H_(0x25, 0x0A) ++#define REG_SC_BK25_0B_L _PK_L_(0x25, 0x0B) ++#define REG_SC_BK25_0B_H _PK_H_(0x25, 0x0B) ++#define REG_SC_BK25_0C_L _PK_L_(0x25, 0x0C) ++#define REG_SC_BK25_0C_H _PK_H_(0x25, 0x0C) ++#define REG_SC_BK25_0D_L _PK_L_(0x25, 0x0D) ++#define REG_SC_BK25_0D_H _PK_H_(0x25, 0x0D) ++#define REG_SC_BK25_0E_L _PK_L_(0x25, 0x0E) ++#define REG_SC_BK25_0E_H _PK_H_(0x25, 0x0E) ++#define REG_SC_BK25_0F_L _PK_L_(0x25, 0x0F) ++#define REG_SC_BK25_0F_H _PK_H_(0x25, 0x0F) ++#define REG_SC_BK25_10_L _PK_L_(0x25, 0x10) ++#define REG_SC_BK25_10_H _PK_H_(0x25, 0x10) ++#define REG_SC_BK25_11_L _PK_L_(0x25, 0x11) ++#define REG_SC_BK25_11_H _PK_H_(0x25, 0x11) ++#define REG_SC_BK25_12_L _PK_L_(0x25, 0x12) ++#define REG_SC_BK25_12_H _PK_H_(0x25, 0x12) ++#define REG_SC_BK25_13_L _PK_L_(0x25, 0x13) ++#define REG_SC_BK25_13_H _PK_H_(0x25, 0x13) ++#define REG_SC_BK25_14_L _PK_L_(0x25, 0x14) ++#define REG_SC_BK25_14_H _PK_H_(0x25, 0x14) ++#define REG_SC_BK25_15_L _PK_L_(0x25, 0x15) ++#define REG_SC_BK25_15_H _PK_H_(0x25, 0x15) ++#define REG_SC_BK25_16_L _PK_L_(0x25, 0x16) ++#define REG_SC_BK25_16_H _PK_H_(0x25, 0x16) ++#define REG_SC_BK25_17_L _PK_L_(0x25, 0x17) ++#define REG_SC_BK25_17_H _PK_H_(0x25, 0x17) ++#define REG_SC_BK25_18_L _PK_L_(0x25, 0x18) ++#define REG_SC_BK25_18_H _PK_H_(0x25, 0x18) ++#define REG_SC_BK25_19_L _PK_L_(0x25, 0x19) ++#define REG_SC_BK25_19_H _PK_H_(0x25, 0x19) ++#define REG_SC_BK25_1A_L _PK_L_(0x25, 0x1A) ++#define REG_SC_BK25_1A_H _PK_H_(0x25, 0x1A) ++#define REG_SC_BK25_1B_L _PK_L_(0x25, 0x1B) ++#define REG_SC_BK25_1B_H _PK_H_(0x25, 0x1B) ++#define REG_SC_BK25_1C_L _PK_L_(0x25, 0x1C) ++#define REG_SC_BK25_1C_H _PK_H_(0x25, 0x1C) ++#define REG_SC_BK25_1D_L _PK_L_(0x25, 0x1D) ++#define REG_SC_BK25_1D_H _PK_H_(0x25, 0x1D) ++#define REG_SC_BK25_1E_L _PK_L_(0x25, 0x1E) ++#define REG_SC_BK25_1E_H _PK_H_(0x25, 0x1E) ++#define REG_SC_BK25_1F_L _PK_L_(0x25, 0x1F) ++#define REG_SC_BK25_1F_H _PK_H_(0x25, 0x1F) ++#define REG_SC_BK25_20_L _PK_L_(0x25, 0x20) ++#define REG_SC_BK25_20_H _PK_H_(0x25, 0x20) ++#define REG_SC_BK25_21_L _PK_L_(0x25, 0x21) ++#define REG_SC_BK25_21_H _PK_H_(0x25, 0x21) ++#define REG_SC_BK25_22_L _PK_L_(0x25, 0x22) ++#define REG_SC_BK25_22_H _PK_H_(0x25, 0x22) ++#define REG_SC_BK25_23_L _PK_L_(0x25, 0x23) ++#define REG_SC_BK25_23_H _PK_H_(0x25, 0x23) ++#define REG_SC_BK25_24_L _PK_L_(0x25, 0x24) ++#define REG_SC_BK25_24_H _PK_H_(0x25, 0x24) ++#define REG_SC_BK25_25_L _PK_L_(0x25, 0x25) ++#define REG_SC_BK25_25_H _PK_H_(0x25, 0x25) ++#define REG_SC_BK25_26_L _PK_L_(0x25, 0x26) ++#define REG_SC_BK25_26_H _PK_H_(0x25, 0x26) ++#define REG_SC_BK25_27_L _PK_L_(0x25, 0x27) ++#define REG_SC_BK25_27_H _PK_H_(0x25, 0x27) ++#define REG_SC_BK25_28_L _PK_L_(0x25, 0x28) ++#define REG_SC_BK25_28_H _PK_H_(0x25, 0x28) ++#define REG_SC_BK25_29_L _PK_L_(0x25, 0x29) ++#define REG_SC_BK25_29_H _PK_H_(0x25, 0x29) ++#define REG_SC_BK25_2A_L _PK_L_(0x25, 0x2A) ++#define REG_SC_BK25_2A_H _PK_H_(0x25, 0x2A) ++#define REG_SC_BK25_2B_L _PK_L_(0x25, 0x2B) ++#define REG_SC_BK25_2B_H _PK_H_(0x25, 0x2B) ++#define REG_SC_BK25_2C_L _PK_L_(0x25, 0x2C) ++#define REG_SC_BK25_2C_H _PK_H_(0x25, 0x2C) ++#define REG_SC_BK25_2D_L _PK_L_(0x25, 0x2D) ++#define REG_SC_BK25_2D_H _PK_H_(0x25, 0x2D) ++#define REG_SC_BK25_2E_L _PK_L_(0x25, 0x2E) ++#define REG_SC_BK25_2E_H _PK_H_(0x25, 0x2E) ++#define REG_SC_BK25_2F_L _PK_L_(0x25, 0x2F) ++#define REG_SC_BK25_2F_H _PK_H_(0x25, 0x2F) ++#define REG_SC_BK25_30_L _PK_L_(0x25, 0x30) ++#define REG_SC_BK25_30_H _PK_H_(0x25, 0x30) ++#define REG_SC_BK25_31_L _PK_L_(0x25, 0x31) ++#define REG_SC_BK25_31_H _PK_H_(0x25, 0x31) ++#define REG_SC_BK25_32_L _PK_L_(0x25, 0x32) ++#define REG_SC_BK25_32_H _PK_H_(0x25, 0x32) ++#define REG_SC_BK25_33_L _PK_L_(0x25, 0x33) ++#define REG_SC_BK25_33_H _PK_H_(0x25, 0x33) ++#define REG_SC_BK25_34_L _PK_L_(0x25, 0x34) ++#define REG_SC_BK25_34_H _PK_H_(0x25, 0x34) ++#define REG_SC_BK25_35_L _PK_L_(0x25, 0x35) ++#define REG_SC_BK25_35_H _PK_H_(0x25, 0x35) ++#define REG_SC_BK25_36_L _PK_L_(0x25, 0x36) ++#define REG_SC_BK25_36_H _PK_H_(0x25, 0x36) ++#define REG_SC_BK25_37_L _PK_L_(0x25, 0x37) ++#define REG_SC_BK25_37_H _PK_H_(0x25, 0x37) ++#define REG_SC_BK25_38_L _PK_L_(0x25, 0x38) ++#define REG_SC_BK25_38_H _PK_H_(0x25, 0x38) ++#define REG_SC_BK25_39_L _PK_L_(0x25, 0x39) ++#define REG_SC_BK25_39_H _PK_H_(0x25, 0x39) ++#define REG_SC_BK25_3A_L _PK_L_(0x25, 0x3A) ++#define REG_SC_BK25_3A_H _PK_H_(0x25, 0x3A) ++#define REG_SC_BK25_3B_L _PK_L_(0x25, 0x3B) ++#define REG_SC_BK25_3B_H _PK_H_(0x25, 0x3B) ++#define REG_SC_BK25_3C_L _PK_L_(0x25, 0x3C) ++#define REG_SC_BK25_3C_H _PK_H_(0x25, 0x3C) ++#define REG_SC_BK25_3D_L _PK_L_(0x25, 0x3D) ++#define REG_SC_BK25_3D_H _PK_H_(0x25, 0x3D) ++#define REG_SC_BK25_3E_L _PK_L_(0x25, 0x3E) ++#define REG_SC_BK25_3E_H _PK_H_(0x25, 0x3E) ++#define REG_SC_BK25_3F_L _PK_L_(0x25, 0x3F) ++#define REG_SC_BK25_3F_H _PK_H_(0x25, 0x3F) ++#define REG_SC_BK25_40_L _PK_L_(0x25, 0x40) ++#define REG_SC_BK25_40_H _PK_H_(0x25, 0x40) ++#define REG_SC_BK25_41_L _PK_L_(0x25, 0x41) ++#define REG_SC_BK25_41_H _PK_H_(0x25, 0x41) ++#define REG_SC_BK25_42_L _PK_L_(0x25, 0x42) ++#define REG_SC_BK25_42_H _PK_H_(0x25, 0x42) ++#define REG_SC_BK25_43_L _PK_L_(0x25, 0x43) ++#define REG_SC_BK25_43_H _PK_H_(0x25, 0x43) ++#define REG_SC_BK25_44_L _PK_L_(0x25, 0x44) ++#define REG_SC_BK25_44_H _PK_H_(0x25, 0x44) ++#define REG_SC_BK25_45_L _PK_L_(0x25, 0x45) ++#define REG_SC_BK25_45_H _PK_H_(0x25, 0x45) ++#define REG_SC_BK25_46_L _PK_L_(0x25, 0x46) ++#define REG_SC_BK25_46_H _PK_H_(0x25, 0x46) ++#define REG_SC_BK25_47_L _PK_L_(0x25, 0x47) ++#define REG_SC_BK25_47_H _PK_H_(0x25, 0x47) ++#define REG_SC_BK25_48_L _PK_L_(0x25, 0x48) ++#define REG_SC_BK25_48_H _PK_H_(0x25, 0x48) ++#define REG_SC_BK25_49_L _PK_L_(0x25, 0x49) ++#define REG_SC_BK25_49_H _PK_H_(0x25, 0x49) ++#define REG_SC_BK25_4A_L _PK_L_(0x25, 0x4A) ++#define REG_SC_BK25_4A_H _PK_H_(0x25, 0x4A) ++#define REG_SC_BK25_4B_L _PK_L_(0x25, 0x4B) ++#define REG_SC_BK25_4B_H _PK_H_(0x25, 0x4B) ++#define REG_SC_BK25_4C_L _PK_L_(0x25, 0x4C) ++#define REG_SC_BK25_4C_H _PK_H_(0x25, 0x4C) ++#define REG_SC_BK25_4D_L _PK_L_(0x25, 0x4D) ++#define REG_SC_BK25_4D_H _PK_H_(0x25, 0x4D) ++#define REG_SC_BK25_4E_L _PK_L_(0x25, 0x4E) ++#define REG_SC_BK25_4E_H _PK_H_(0x25, 0x4E) ++#define REG_SC_BK25_4F_L _PK_L_(0x25, 0x4F) ++#define REG_SC_BK25_4F_H _PK_H_(0x25, 0x4F) ++#define REG_SC_BK25_50_L _PK_L_(0x25, 0x50) ++#define REG_SC_BK25_50_H _PK_H_(0x25, 0x50) ++#define REG_SC_BK25_51_L _PK_L_(0x25, 0x51) ++#define REG_SC_BK25_51_H _PK_H_(0x25, 0x51) ++#define REG_SC_BK25_52_L _PK_L_(0x25, 0x52) ++#define REG_SC_BK25_52_H _PK_H_(0x25, 0x52) ++#define REG_SC_BK25_53_L _PK_L_(0x25, 0x53) ++#define REG_SC_BK25_53_H _PK_H_(0x25, 0x53) ++#define REG_SC_BK25_54_L _PK_L_(0x25, 0x54) ++#define REG_SC_BK25_54_H _PK_H_(0x25, 0x54) ++#define REG_SC_BK25_55_L _PK_L_(0x25, 0x55) ++#define REG_SC_BK25_55_H _PK_H_(0x25, 0x55) ++#define REG_SC_BK25_56_L _PK_L_(0x25, 0x56) ++#define REG_SC_BK25_56_H _PK_H_(0x25, 0x56) ++#define REG_SC_BK25_57_L _PK_L_(0x25, 0x57) ++#define REG_SC_BK25_57_H _PK_H_(0x25, 0x57) ++#define REG_SC_BK25_58_L _PK_L_(0x25, 0x58) ++#define REG_SC_BK25_58_H _PK_H_(0x25, 0x58) ++#define REG_SC_BK25_59_L _PK_L_(0x25, 0x59) ++#define REG_SC_BK25_59_H _PK_H_(0x25, 0x59) ++#define REG_SC_BK25_5A_L _PK_L_(0x25, 0x5A) ++#define REG_SC_BK25_5A_H _PK_H_(0x25, 0x5A) ++#define REG_SC_BK25_5B_L _PK_L_(0x25, 0x5B) ++#define REG_SC_BK25_5B_H _PK_H_(0x25, 0x5B) ++#define REG_SC_BK25_5C_L _PK_L_(0x25, 0x5C) ++#define REG_SC_BK25_5C_H _PK_H_(0x25, 0x5C) ++#define REG_SC_BK25_5D_L _PK_L_(0x25, 0x5D) ++#define REG_SC_BK25_5D_H _PK_H_(0x25, 0x5D) ++#define REG_SC_BK25_5E_L _PK_L_(0x25, 0x5E) ++#define REG_SC_BK25_5E_H _PK_H_(0x25, 0x5E) ++#define REG_SC_BK25_5F_L _PK_L_(0x25, 0x5F) ++#define REG_SC_BK25_5F_H _PK_H_(0x25, 0x5F) ++#define REG_SC_BK25_60_L _PK_L_(0x25, 0x60) ++#define REG_SC_BK25_60_H _PK_H_(0x25, 0x60) ++#define REG_SC_BK25_61_L _PK_L_(0x25, 0x61) ++#define REG_SC_BK25_61_H _PK_H_(0x25, 0x61) ++#define REG_SC_BK25_62_L _PK_L_(0x25, 0x62) ++#define REG_SC_BK25_62_H _PK_H_(0x25, 0x62) ++#define REG_SC_BK25_63_L _PK_L_(0x25, 0x63) ++#define REG_SC_BK25_63_H _PK_H_(0x25, 0x63) ++#define REG_SC_BK25_64_L _PK_L_(0x25, 0x64) ++#define REG_SC_BK25_64_H _PK_H_(0x25, 0x64) ++#define REG_SC_BK25_65_L _PK_L_(0x25, 0x65) ++#define REG_SC_BK25_65_H _PK_H_(0x25, 0x65) ++#define REG_SC_BK25_66_L _PK_L_(0x25, 0x66) ++#define REG_SC_BK25_66_H _PK_H_(0x25, 0x66) ++#define REG_SC_BK25_67_L _PK_L_(0x25, 0x67) ++#define REG_SC_BK25_67_H _PK_H_(0x25, 0x67) ++#define REG_SC_BK25_68_L _PK_L_(0x25, 0x68) ++#define REG_SC_BK25_68_H _PK_H_(0x25, 0x68) ++#define REG_SC_BK25_69_L _PK_L_(0x25, 0x69) ++#define REG_SC_BK25_69_H _PK_H_(0x25, 0x69) ++#define REG_SC_BK25_6A_L _PK_L_(0x25, 0x6A) ++#define REG_SC_BK25_6A_H _PK_H_(0x25, 0x6A) ++#define REG_SC_BK25_6B_L _PK_L_(0x25, 0x6B) ++#define REG_SC_BK25_6B_H _PK_H_(0x25, 0x6B) ++#define REG_SC_BK25_6C_L _PK_L_(0x25, 0x6C) ++#define REG_SC_BK25_6C_H _PK_H_(0x25, 0x6C) ++#define REG_SC_BK25_6D_L _PK_L_(0x25, 0x6D) ++#define REG_SC_BK25_6D_H _PK_H_(0x25, 0x6D) ++#define REG_SC_BK25_6E_L _PK_L_(0x25, 0x6E) ++#define REG_SC_BK25_6E_H _PK_H_(0x25, 0x6E) ++#define REG_SC_BK25_6F_L _PK_L_(0x25, 0x6F) ++#define REG_SC_BK25_6F_H _PK_H_(0x25, 0x6F) ++#define REG_SC_BK25_70_L _PK_L_(0x25, 0x70) ++#define REG_SC_BK25_70_H _PK_H_(0x25, 0x70) ++#define REG_SC_BK25_71_L _PK_L_(0x25, 0x71) ++#define REG_SC_BK25_71_H _PK_H_(0x25, 0x71) ++#define REG_SC_BK25_72_L _PK_L_(0x25, 0x72) ++#define REG_SC_BK25_72_H _PK_H_(0x25, 0x72) ++#define REG_SC_BK25_73_L _PK_L_(0x25, 0x73) ++#define REG_SC_BK25_73_H _PK_H_(0x25, 0x73) ++#define REG_SC_BK25_74_L _PK_L_(0x25, 0x74) ++#define REG_SC_BK25_74_H _PK_H_(0x25, 0x74) ++#define REG_SC_BK25_75_L _PK_L_(0x25, 0x75) ++#define REG_SC_BK25_75_H _PK_H_(0x25, 0x75) ++#define REG_SC_BK25_76_L _PK_L_(0x25, 0x76) ++#define REG_SC_BK25_76_H _PK_H_(0x25, 0x76) ++#define REG_SC_BK25_77_L _PK_L_(0x25, 0x77) ++#define REG_SC_BK25_77_H _PK_H_(0x25, 0x77) ++#define REG_SC_BK25_78_L _PK_L_(0x25, 0x78) ++#define REG_SC_BK25_78_H _PK_H_(0x25, 0x78) ++#define REG_SC_BK25_79_L _PK_L_(0x25, 0x79) ++#define REG_SC_BK25_79_H _PK_H_(0x25, 0x79) ++#define REG_SC_BK25_7A_L _PK_L_(0x25, 0x7A) ++#define REG_SC_BK25_7A_H _PK_H_(0x25, 0x7A) ++#define REG_SC_BK25_7B_L _PK_L_(0x25, 0x7B) ++#define REG_SC_BK25_7B_H _PK_H_(0x25, 0x7B) ++#define REG_SC_BK25_7C_L _PK_L_(0x25, 0x7C) ++#define REG_SC_BK25_7C_H _PK_H_(0x25, 0x7C) ++#define REG_SC_BK25_7D_L _PK_L_(0x25, 0x7D) ++#define REG_SC_BK25_7D_H _PK_H_(0x25, 0x7D) ++#define REG_SC_BK25_7E_L _PK_L_(0x25, 0x7E) ++#define REG_SC_BK25_7E_H _PK_H_(0x25, 0x7E) ++#define REG_SC_BK25_7F_L _PK_L_(0x25, 0x7F) ++#define REG_SC_BK25_7F_H _PK_H_(0x25, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK26_00_L _PK_L_(0x26, 0x00) ++#define REG_SC_BK26_00_H _PK_H_(0x26, 0x00) ++#define REG_SC_BK26_01_L _PK_L_(0x26, 0x01) ++#define REG_SC_BK26_01_H _PK_H_(0x26, 0x01) ++#define REG_SC_BK26_02_L _PK_L_(0x26, 0x02) ++#define REG_SC_BK26_02_H _PK_H_(0x26, 0x02) ++#define REG_SC_BK26_03_L _PK_L_(0x26, 0x03) ++#define REG_SC_BK26_03_H _PK_H_(0x26, 0x03) ++#define REG_SC_BK26_04_L _PK_L_(0x26, 0x04) ++#define REG_SC_BK26_04_H _PK_H_(0x26, 0x04) ++#define REG_SC_BK26_05_L _PK_L_(0x26, 0x05) ++#define REG_SC_BK26_05_H _PK_H_(0x26, 0x05) ++#define REG_SC_BK26_06_L _PK_L_(0x26, 0x06) ++#define REG_SC_BK26_06_H _PK_H_(0x26, 0x06) ++#define REG_SC_BK26_07_L _PK_L_(0x26, 0x07) ++#define REG_SC_BK26_07_H _PK_H_(0x26, 0x07) ++#define REG_SC_BK26_08_L _PK_L_(0x26, 0x08) ++#define REG_SC_BK26_08_H _PK_H_(0x26, 0x08) ++#define REG_SC_BK26_09_L _PK_L_(0x26, 0x09) ++#define REG_SC_BK26_09_H _PK_H_(0x26, 0x09) ++#define REG_SC_BK26_0A_L _PK_L_(0x26, 0x0A) ++#define REG_SC_BK26_0A_H _PK_H_(0x26, 0x0A) ++#define REG_SC_BK26_0B_L _PK_L_(0x26, 0x0B) ++#define REG_SC_BK26_0B_H _PK_H_(0x26, 0x0B) ++#define REG_SC_BK26_0C_L _PK_L_(0x26, 0x0C) ++#define REG_SC_BK26_0C_H _PK_H_(0x26, 0x0C) ++#define REG_SC_BK26_0D_L _PK_L_(0x26, 0x0D) ++#define REG_SC_BK26_0D_H _PK_H_(0x26, 0x0D) ++#define REG_SC_BK26_0E_L _PK_L_(0x26, 0x0E) ++#define REG_SC_BK26_0E_H _PK_H_(0x26, 0x0E) ++#define REG_SC_BK26_0F_L _PK_L_(0x26, 0x0F) ++#define REG_SC_BK26_0F_H _PK_H_(0x26, 0x0F) ++#define REG_SC_BK26_10_L _PK_L_(0x26, 0x10) ++#define REG_SC_BK26_10_H _PK_H_(0x26, 0x10) ++#define REG_SC_BK26_11_L _PK_L_(0x26, 0x11) ++#define REG_SC_BK26_11_H _PK_H_(0x26, 0x11) ++#define REG_SC_BK26_12_L _PK_L_(0x26, 0x12) ++#define REG_SC_BK26_12_H _PK_H_(0x26, 0x12) ++#define REG_SC_BK26_13_L _PK_L_(0x26, 0x13) ++#define REG_SC_BK26_13_H _PK_H_(0x26, 0x13) ++#define REG_SC_BK26_14_L _PK_L_(0x26, 0x14) ++#define REG_SC_BK26_14_H _PK_H_(0x26, 0x14) ++#define REG_SC_BK26_15_L _PK_L_(0x26, 0x15) ++#define REG_SC_BK26_15_H _PK_H_(0x26, 0x15) ++#define REG_SC_BK26_16_L _PK_L_(0x26, 0x16) ++#define REG_SC_BK26_16_H _PK_H_(0x26, 0x16) ++#define REG_SC_BK26_17_L _PK_L_(0x26, 0x17) ++#define REG_SC_BK26_17_H _PK_H_(0x26, 0x17) ++#define REG_SC_BK26_18_L _PK_L_(0x26, 0x18) ++#define REG_SC_BK26_18_H _PK_H_(0x26, 0x18) ++#define REG_SC_BK26_19_L _PK_L_(0x26, 0x19) ++#define REG_SC_BK26_19_H _PK_H_(0x26, 0x19) ++#define REG_SC_BK26_1A_L _PK_L_(0x26, 0x1A) ++#define REG_SC_BK26_1A_H _PK_H_(0x26, 0x1A) ++#define REG_SC_BK26_1B_L _PK_L_(0x26, 0x1B) ++#define REG_SC_BK26_1B_H _PK_H_(0x26, 0x1B) ++#define REG_SC_BK26_1C_L _PK_L_(0x26, 0x1C) ++#define REG_SC_BK26_1C_H _PK_H_(0x26, 0x1C) ++#define REG_SC_BK26_1D_L _PK_L_(0x26, 0x1D) ++#define REG_SC_BK26_1D_H _PK_H_(0x26, 0x1D) ++#define REG_SC_BK26_1E_L _PK_L_(0x26, 0x1E) ++#define REG_SC_BK26_1E_H _PK_H_(0x26, 0x1E) ++#define REG_SC_BK26_1F_L _PK_L_(0x26, 0x1F) ++#define REG_SC_BK26_1F_H _PK_H_(0x26, 0x1F) ++#define REG_SC_BK26_20_L _PK_L_(0x26, 0x20) ++#define REG_SC_BK26_20_H _PK_H_(0x26, 0x20) ++#define REG_SC_BK26_21_L _PK_L_(0x26, 0x21) ++#define REG_SC_BK26_21_H _PK_H_(0x26, 0x21) ++#define REG_SC_BK26_22_L _PK_L_(0x26, 0x22) ++#define REG_SC_BK26_22_H _PK_H_(0x26, 0x22) ++#define REG_SC_BK26_23_L _PK_L_(0x26, 0x23) ++#define REG_SC_BK26_23_H _PK_H_(0x26, 0x23) ++#define REG_SC_BK26_24_L _PK_L_(0x26, 0x24) ++#define REG_SC_BK26_24_H _PK_H_(0x26, 0x24) ++#define REG_SC_BK26_25_L _PK_L_(0x26, 0x25) ++#define REG_SC_BK26_25_H _PK_H_(0x26, 0x25) ++#define REG_SC_BK26_26_L _PK_L_(0x26, 0x26) ++#define REG_SC_BK26_26_H _PK_H_(0x26, 0x26) ++#define REG_SC_BK26_27_L _PK_L_(0x26, 0x27) ++#define REG_SC_BK26_27_H _PK_H_(0x26, 0x27) ++#define REG_SC_BK26_28_L _PK_L_(0x26, 0x28) ++#define REG_SC_BK26_28_H _PK_H_(0x26, 0x28) ++#define REG_SC_BK26_29_L _PK_L_(0x26, 0x29) ++#define REG_SC_BK26_29_H _PK_H_(0x26, 0x29) ++#define REG_SC_BK26_2A_L _PK_L_(0x26, 0x2A) ++#define REG_SC_BK26_2A_H _PK_H_(0x26, 0x2A) ++#define REG_SC_BK26_2B_L _PK_L_(0x26, 0x2B) ++#define REG_SC_BK26_2B_H _PK_H_(0x26, 0x2B) ++#define REG_SC_BK26_2C_L _PK_L_(0x26, 0x2C) ++#define REG_SC_BK26_2C_H _PK_H_(0x26, 0x2C) ++#define REG_SC_BK26_2D_L _PK_L_(0x26, 0x2D) ++#define REG_SC_BK26_2D_H _PK_H_(0x26, 0x2D) ++#define REG_SC_BK26_2E_L _PK_L_(0x26, 0x2E) ++#define REG_SC_BK26_2E_H _PK_H_(0x26, 0x2E) ++#define REG_SC_BK26_2F_L _PK_L_(0x26, 0x2F) ++#define REG_SC_BK26_2F_H _PK_H_(0x26, 0x2F) ++#define REG_SC_BK26_30_L _PK_L_(0x26, 0x30) ++#define REG_SC_BK26_30_H _PK_H_(0x26, 0x30) ++#define REG_SC_BK26_31_L _PK_L_(0x26, 0x31) ++#define REG_SC_BK26_31_H _PK_H_(0x26, 0x31) ++#define REG_SC_BK26_32_L _PK_L_(0x26, 0x32) ++#define REG_SC_BK26_32_H _PK_H_(0x26, 0x32) ++#define REG_SC_BK26_33_L _PK_L_(0x26, 0x33) ++#define REG_SC_BK26_33_H _PK_H_(0x26, 0x33) ++#define REG_SC_BK26_34_L _PK_L_(0x26, 0x34) ++#define REG_SC_BK26_34_H _PK_H_(0x26, 0x34) ++#define REG_SC_BK26_35_L _PK_L_(0x26, 0x35) ++#define REG_SC_BK26_35_H _PK_H_(0x26, 0x35) ++#define REG_SC_BK26_36_L _PK_L_(0x26, 0x36) ++#define REG_SC_BK26_36_H _PK_H_(0x26, 0x36) ++#define REG_SC_BK26_37_L _PK_L_(0x26, 0x37) ++#define REG_SC_BK26_37_H _PK_H_(0x26, 0x37) ++#define REG_SC_BK26_38_L _PK_L_(0x26, 0x38) ++#define REG_SC_BK26_38_H _PK_H_(0x26, 0x38) ++#define REG_SC_BK26_39_L _PK_L_(0x26, 0x39) ++#define REG_SC_BK26_39_H _PK_H_(0x26, 0x39) ++#define REG_SC_BK26_3A_L _PK_L_(0x26, 0x3A) ++#define REG_SC_BK26_3A_H _PK_H_(0x26, 0x3A) ++#define REG_SC_BK26_3B_L _PK_L_(0x26, 0x3B) ++#define REG_SC_BK26_3B_H _PK_H_(0x26, 0x3B) ++#define REG_SC_BK26_3C_L _PK_L_(0x26, 0x3C) ++#define REG_SC_BK26_3C_H _PK_H_(0x26, 0x3C) ++#define REG_SC_BK26_3D_L _PK_L_(0x26, 0x3D) ++#define REG_SC_BK26_3D_H _PK_H_(0x26, 0x3D) ++#define REG_SC_BK26_3E_L _PK_L_(0x26, 0x3E) ++#define REG_SC_BK26_3E_H _PK_H_(0x26, 0x3E) ++#define REG_SC_BK26_3F_L _PK_L_(0x26, 0x3F) ++#define REG_SC_BK26_3F_H _PK_H_(0x26, 0x3F) ++#define REG_SC_BK26_40_L _PK_L_(0x26, 0x40) ++#define REG_SC_BK26_40_H _PK_H_(0x26, 0x40) ++#define REG_SC_BK26_41_L _PK_L_(0x26, 0x41) ++#define REG_SC_BK26_41_H _PK_H_(0x26, 0x41) ++#define REG_SC_BK26_42_L _PK_L_(0x26, 0x42) ++#define REG_SC_BK26_42_H _PK_H_(0x26, 0x42) ++#define REG_SC_BK26_43_L _PK_L_(0x26, 0x43) ++#define REG_SC_BK26_43_H _PK_H_(0x26, 0x43) ++#define REG_SC_BK26_44_L _PK_L_(0x26, 0x44) ++#define REG_SC_BK26_44_H _PK_H_(0x26, 0x44) ++#define REG_SC_BK26_45_L _PK_L_(0x26, 0x45) ++#define REG_SC_BK26_45_H _PK_H_(0x26, 0x45) ++#define REG_SC_BK26_46_L _PK_L_(0x26, 0x46) ++#define REG_SC_BK26_46_H _PK_H_(0x26, 0x46) ++#define REG_SC_BK26_47_L _PK_L_(0x26, 0x47) ++#define REG_SC_BK26_47_H _PK_H_(0x26, 0x47) ++#define REG_SC_BK26_48_L _PK_L_(0x26, 0x48) ++#define REG_SC_BK26_48_H _PK_H_(0x26, 0x48) ++#define REG_SC_BK26_49_L _PK_L_(0x26, 0x49) ++#define REG_SC_BK26_49_H _PK_H_(0x26, 0x49) ++#define REG_SC_BK26_4A_L _PK_L_(0x26, 0x4A) ++#define REG_SC_BK26_4A_H _PK_H_(0x26, 0x4A) ++#define REG_SC_BK26_4B_L _PK_L_(0x26, 0x4B) ++#define REG_SC_BK26_4B_H _PK_H_(0x26, 0x4B) ++#define REG_SC_BK26_4C_L _PK_L_(0x26, 0x4C) ++#define REG_SC_BK26_4C_H _PK_H_(0x26, 0x4C) ++#define REG_SC_BK26_4D_L _PK_L_(0x26, 0x4D) ++#define REG_SC_BK26_4D_H _PK_H_(0x26, 0x4D) ++#define REG_SC_BK26_4E_L _PK_L_(0x26, 0x4E) ++#define REG_SC_BK26_4E_H _PK_H_(0x26, 0x4E) ++#define REG_SC_BK26_4F_L _PK_L_(0x26, 0x4F) ++#define REG_SC_BK26_4F_H _PK_H_(0x26, 0x4F) ++#define REG_SC_BK26_50_L _PK_L_(0x26, 0x50) ++#define REG_SC_BK26_50_H _PK_H_(0x26, 0x50) ++#define REG_SC_BK26_51_L _PK_L_(0x26, 0x51) ++#define REG_SC_BK26_51_H _PK_H_(0x26, 0x51) ++#define REG_SC_BK26_52_L _PK_L_(0x26, 0x52) ++#define REG_SC_BK26_52_H _PK_H_(0x26, 0x52) ++#define REG_SC_BK26_53_L _PK_L_(0x26, 0x53) ++#define REG_SC_BK26_53_H _PK_H_(0x26, 0x53) ++#define REG_SC_BK26_54_L _PK_L_(0x26, 0x54) ++#define REG_SC_BK26_54_H _PK_H_(0x26, 0x54) ++#define REG_SC_BK26_55_L _PK_L_(0x26, 0x55) ++#define REG_SC_BK26_55_H _PK_H_(0x26, 0x55) ++#define REG_SC_BK26_56_L _PK_L_(0x26, 0x56) ++#define REG_SC_BK26_56_H _PK_H_(0x26, 0x56) ++#define REG_SC_BK26_57_L _PK_L_(0x26, 0x57) ++#define REG_SC_BK26_57_H _PK_H_(0x26, 0x57) ++#define REG_SC_BK26_58_L _PK_L_(0x26, 0x58) ++#define REG_SC_BK26_58_H _PK_H_(0x26, 0x58) ++#define REG_SC_BK26_59_L _PK_L_(0x26, 0x59) ++#define REG_SC_BK26_59_H _PK_H_(0x26, 0x59) ++#define REG_SC_BK26_5A_L _PK_L_(0x26, 0x5A) ++#define REG_SC_BK26_5A_H _PK_H_(0x26, 0x5A) ++#define REG_SC_BK26_5B_L _PK_L_(0x26, 0x5B) ++#define REG_SC_BK26_5B_H _PK_H_(0x26, 0x5B) ++#define REG_SC_BK26_5C_L _PK_L_(0x26, 0x5C) ++#define REG_SC_BK26_5C_H _PK_H_(0x26, 0x5C) ++#define REG_SC_BK26_5D_L _PK_L_(0x26, 0x5D) ++#define REG_SC_BK26_5D_H _PK_H_(0x26, 0x5D) ++#define REG_SC_BK26_5E_L _PK_L_(0x26, 0x5E) ++#define REG_SC_BK26_5E_H _PK_H_(0x26, 0x5E) ++#define REG_SC_BK26_5F_L _PK_L_(0x26, 0x5F) ++#define REG_SC_BK26_5F_H _PK_H_(0x26, 0x5F) ++#define REG_SC_BK26_60_L _PK_L_(0x26, 0x60) ++#define REG_SC_BK26_60_H _PK_H_(0x26, 0x60) ++#define REG_SC_BK26_61_L _PK_L_(0x26, 0x61) ++#define REG_SC_BK26_61_H _PK_H_(0x26, 0x61) ++#define REG_SC_BK26_62_L _PK_L_(0x26, 0x62) ++#define REG_SC_BK26_62_H _PK_H_(0x26, 0x62) ++#define REG_SC_BK26_63_L _PK_L_(0x26, 0x63) ++#define REG_SC_BK26_63_H _PK_H_(0x26, 0x63) ++#define REG_SC_BK26_64_L _PK_L_(0x26, 0x64) ++#define REG_SC_BK26_64_H _PK_H_(0x26, 0x64) ++#define REG_SC_BK26_65_L _PK_L_(0x26, 0x65) ++#define REG_SC_BK26_65_H _PK_H_(0x26, 0x65) ++#define REG_SC_BK26_66_L _PK_L_(0x26, 0x66) ++#define REG_SC_BK26_66_H _PK_H_(0x26, 0x66) ++#define REG_SC_BK26_67_L _PK_L_(0x26, 0x67) ++#define REG_SC_BK26_67_H _PK_H_(0x26, 0x67) ++#define REG_SC_BK26_68_L _PK_L_(0x26, 0x68) ++#define REG_SC_BK26_68_H _PK_H_(0x26, 0x68) ++#define REG_SC_BK26_69_L _PK_L_(0x26, 0x69) ++#define REG_SC_BK26_69_H _PK_H_(0x26, 0x69) ++#define REG_SC_BK26_6A_L _PK_L_(0x26, 0x6A) ++#define REG_SC_BK26_6A_H _PK_H_(0x26, 0x6A) ++#define REG_SC_BK26_6B_L _PK_L_(0x26, 0x6B) ++#define REG_SC_BK26_6B_H _PK_H_(0x26, 0x6B) ++#define REG_SC_BK26_6C_L _PK_L_(0x26, 0x6C) ++#define REG_SC_BK26_6C_H _PK_H_(0x26, 0x6C) ++#define REG_SC_BK26_6D_L _PK_L_(0x26, 0x6D) ++#define REG_SC_BK26_6D_H _PK_H_(0x26, 0x6D) ++#define REG_SC_BK26_6E_L _PK_L_(0x26, 0x6E) ++#define REG_SC_BK26_6E_H _PK_H_(0x26, 0x6E) ++#define REG_SC_BK26_6F_L _PK_L_(0x26, 0x6F) ++#define REG_SC_BK26_6F_H _PK_H_(0x26, 0x6F) ++#define REG_SC_BK26_70_L _PK_L_(0x26, 0x70) ++#define REG_SC_BK26_70_H _PK_H_(0x26, 0x70) ++#define REG_SC_BK26_71_L _PK_L_(0x26, 0x71) ++#define REG_SC_BK26_71_H _PK_H_(0x26, 0x71) ++#define REG_SC_BK26_72_L _PK_L_(0x26, 0x72) ++#define REG_SC_BK26_72_H _PK_H_(0x26, 0x72) ++#define REG_SC_BK26_73_L _PK_L_(0x26, 0x73) ++#define REG_SC_BK26_73_H _PK_H_(0x26, 0x73) ++#define REG_SC_BK26_74_L _PK_L_(0x26, 0x74) ++#define REG_SC_BK26_74_H _PK_H_(0x26, 0x74) ++#define REG_SC_BK26_75_L _PK_L_(0x26, 0x75) ++#define REG_SC_BK26_75_H _PK_H_(0x26, 0x75) ++#define REG_SC_BK26_76_L _PK_L_(0x26, 0x76) ++#define REG_SC_BK26_76_H _PK_H_(0x26, 0x76) ++#define REG_SC_BK26_77_L _PK_L_(0x26, 0x77) ++#define REG_SC_BK26_77_H _PK_H_(0x26, 0x77) ++#define REG_SC_BK26_78_L _PK_L_(0x26, 0x78) ++#define REG_SC_BK26_78_H _PK_H_(0x26, 0x78) ++#define REG_SC_BK26_79_L _PK_L_(0x26, 0x79) ++#define REG_SC_BK26_79_H _PK_H_(0x26, 0x79) ++#define REG_SC_BK26_7A_L _PK_L_(0x26, 0x7A) ++#define REG_SC_BK26_7A_H _PK_H_(0x26, 0x7A) ++#define REG_SC_BK26_7B_L _PK_L_(0x26, 0x7B) ++#define REG_SC_BK26_7B_H _PK_H_(0x26, 0x7B) ++#define REG_SC_BK26_7C_L _PK_L_(0x26, 0x7C) ++#define REG_SC_BK26_7C_H _PK_H_(0x26, 0x7C) ++#define REG_SC_BK26_7D_L _PK_L_(0x26, 0x7D) ++#define REG_SC_BK26_7D_H _PK_H_(0x26, 0x7D) ++#define REG_SC_BK26_7E_L _PK_L_(0x26, 0x7E) ++#define REG_SC_BK26_7E_H _PK_H_(0x26, 0x7E) ++#define REG_SC_BK26_7F_L _PK_L_(0x26, 0x7F) ++#define REG_SC_BK26_7F_H _PK_H_(0x26, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK27_00_L _PK_L_(0x27, 0x00) ++#define REG_SC_BK27_00_H _PK_H_(0x27, 0x00) ++#define REG_SC_BK27_01_L _PK_L_(0x27, 0x01) ++#define REG_SC_BK27_01_H _PK_H_(0x27, 0x01) ++#define REG_SC_BK27_02_L _PK_L_(0x27, 0x02) ++#define REG_SC_BK27_02_H _PK_H_(0x27, 0x02) ++#define REG_SC_BK27_03_L _PK_L_(0x27, 0x03) ++#define REG_SC_BK27_03_H _PK_H_(0x27, 0x03) ++#define REG_SC_BK27_04_L _PK_L_(0x27, 0x04) ++#define REG_SC_BK27_04_H _PK_H_(0x27, 0x04) ++#define REG_SC_BK27_05_L _PK_L_(0x27, 0x05) ++#define REG_SC_BK27_05_H _PK_H_(0x27, 0x05) ++#define REG_SC_BK27_06_L _PK_L_(0x27, 0x06) ++#define REG_SC_BK27_06_H _PK_H_(0x27, 0x06) ++#define REG_SC_BK27_07_L _PK_L_(0x27, 0x07) ++#define REG_SC_BK27_07_H _PK_H_(0x27, 0x07) ++#define REG_SC_BK27_08_L _PK_L_(0x27, 0x08) ++#define REG_SC_BK27_08_H _PK_H_(0x27, 0x08) ++#define REG_SC_BK27_09_L _PK_L_(0x27, 0x09) ++#define REG_SC_BK27_09_H _PK_H_(0x27, 0x09) ++#define REG_SC_BK27_0A_L _PK_L_(0x27, 0x0A) ++#define REG_SC_BK27_0A_H _PK_H_(0x27, 0x0A) ++#define REG_SC_BK27_0B_L _PK_L_(0x27, 0x0B) ++#define REG_SC_BK27_0B_H _PK_H_(0x27, 0x0B) ++#define REG_SC_BK27_0C_L _PK_L_(0x27, 0x0C) ++#define REG_SC_BK27_0C_H _PK_H_(0x27, 0x0C) ++#define REG_SC_BK27_0D_L _PK_L_(0x27, 0x0D) ++#define REG_SC_BK27_0D_H _PK_H_(0x27, 0x0D) ++#define REG_SC_BK27_0E_L _PK_L_(0x27, 0x0E) ++#define REG_SC_BK27_0E_H _PK_H_(0x27, 0x0E) ++#define REG_SC_BK27_0F_L _PK_L_(0x27, 0x0F) ++#define REG_SC_BK27_0F_H _PK_H_(0x27, 0x0F) ++#define REG_SC_BK27_10_L _PK_L_(0x27, 0x10) ++#define REG_SC_BK27_10_H _PK_H_(0x27, 0x10) ++#define REG_SC_BK27_11_L _PK_L_(0x27, 0x11) ++#define REG_SC_BK27_11_H _PK_H_(0x27, 0x11) ++#define REG_SC_BK27_12_L _PK_L_(0x27, 0x12) ++#define REG_SC_BK27_12_H _PK_H_(0x27, 0x12) ++#define REG_SC_BK27_13_L _PK_L_(0x27, 0x13) ++#define REG_SC_BK27_13_H _PK_H_(0x27, 0x13) ++#define REG_SC_BK27_14_L _PK_L_(0x27, 0x14) ++#define REG_SC_BK27_14_H _PK_H_(0x27, 0x14) ++#define REG_SC_BK27_15_L _PK_L_(0x27, 0x15) ++#define REG_SC_BK27_15_H _PK_H_(0x27, 0x15) ++#define REG_SC_BK27_16_L _PK_L_(0x27, 0x16) ++#define REG_SC_BK27_16_H _PK_H_(0x27, 0x16) ++#define REG_SC_BK27_17_L _PK_L_(0x27, 0x17) ++#define REG_SC_BK27_17_H _PK_H_(0x27, 0x17) ++#define REG_SC_BK27_18_L _PK_L_(0x27, 0x18) ++#define REG_SC_BK27_18_H _PK_H_(0x27, 0x18) ++#define REG_SC_BK27_19_L _PK_L_(0x27, 0x19) ++#define REG_SC_BK27_19_H _PK_H_(0x27, 0x19) ++#define REG_SC_BK27_1A_L _PK_L_(0x27, 0x1A) ++#define REG_SC_BK27_1A_H _PK_H_(0x27, 0x1A) ++#define REG_SC_BK27_1B_L _PK_L_(0x27, 0x1B) ++#define REG_SC_BK27_1B_H _PK_H_(0x27, 0x1B) ++#define REG_SC_BK27_1C_L _PK_L_(0x27, 0x1C) ++#define REG_SC_BK27_1C_H _PK_H_(0x27, 0x1C) ++#define REG_SC_BK27_1D_L _PK_L_(0x27, 0x1D) ++#define REG_SC_BK27_1D_H _PK_H_(0x27, 0x1D) ++#define REG_SC_BK27_1E_L _PK_L_(0x27, 0x1E) ++#define REG_SC_BK27_1E_H _PK_H_(0x27, 0x1E) ++#define REG_SC_BK27_1F_L _PK_L_(0x27, 0x1F) ++#define REG_SC_BK27_1F_H _PK_H_(0x27, 0x1F) ++#define REG_SC_BK27_20_L _PK_L_(0x27, 0x20) ++#define REG_SC_BK27_20_H _PK_H_(0x27, 0x20) ++#define REG_SC_BK27_21_L _PK_L_(0x27, 0x21) ++#define REG_SC_BK27_21_H _PK_H_(0x27, 0x21) ++#define REG_SC_BK27_22_L _PK_L_(0x27, 0x22) ++#define REG_SC_BK27_22_H _PK_H_(0x27, 0x22) ++#define REG_SC_BK27_23_L _PK_L_(0x27, 0x23) ++#define REG_SC_BK27_23_H _PK_H_(0x27, 0x23) ++#define REG_SC_BK27_24_L _PK_L_(0x27, 0x24) ++#define REG_SC_BK27_24_H _PK_H_(0x27, 0x24) ++#define REG_SC_BK27_25_L _PK_L_(0x27, 0x25) ++#define REG_SC_BK27_25_H _PK_H_(0x27, 0x25) ++#define REG_SC_BK27_26_L _PK_L_(0x27, 0x26) ++#define REG_SC_BK27_26_H _PK_H_(0x27, 0x26) ++#define REG_SC_BK27_27_L _PK_L_(0x27, 0x27) ++#define REG_SC_BK27_27_H _PK_H_(0x27, 0x27) ++#define REG_SC_BK27_28_L _PK_L_(0x27, 0x28) ++#define REG_SC_BK27_28_H _PK_H_(0x27, 0x28) ++#define REG_SC_BK27_29_L _PK_L_(0x27, 0x29) ++#define REG_SC_BK27_29_H _PK_H_(0x27, 0x29) ++#define REG_SC_BK27_2A_L _PK_L_(0x27, 0x2A) ++#define REG_SC_BK27_2A_H _PK_H_(0x27, 0x2A) ++#define REG_SC_BK27_2B_L _PK_L_(0x27, 0x2B) ++#define REG_SC_BK27_2B_H _PK_H_(0x27, 0x2B) ++#define REG_SC_BK27_2C_L _PK_L_(0x27, 0x2C) ++#define REG_SC_BK27_2C_H _PK_H_(0x27, 0x2C) ++#define REG_SC_BK27_2D_L _PK_L_(0x27, 0x2D) ++#define REG_SC_BK27_2D_H _PK_H_(0x27, 0x2D) ++#define REG_SC_BK27_2E_L _PK_L_(0x27, 0x2E) ++#define REG_SC_BK27_2E_H _PK_H_(0x27, 0x2E) ++#define REG_SC_BK27_2F_L _PK_L_(0x27, 0x2F) ++#define REG_SC_BK27_2F_H _PK_H_(0x27, 0x2F) ++#define REG_SC_BK27_30_L _PK_L_(0x27, 0x30) ++#define REG_SC_BK27_30_H _PK_H_(0x27, 0x30) ++#define REG_SC_BK27_31_L _PK_L_(0x27, 0x31) ++#define REG_SC_BK27_31_H _PK_H_(0x27, 0x31) ++#define REG_SC_BK27_32_L _PK_L_(0x27, 0x32) ++#define REG_SC_BK27_32_H _PK_H_(0x27, 0x32) ++#define REG_SC_BK27_33_L _PK_L_(0x27, 0x33) ++#define REG_SC_BK27_33_H _PK_H_(0x27, 0x33) ++#define REG_SC_BK27_34_L _PK_L_(0x27, 0x34) ++#define REG_SC_BK27_34_H _PK_H_(0x27, 0x34) ++#define REG_SC_BK27_35_L _PK_L_(0x27, 0x35) ++#define REG_SC_BK27_35_H _PK_H_(0x27, 0x35) ++#define REG_SC_BK27_36_L _PK_L_(0x27, 0x36) ++#define REG_SC_BK27_36_H _PK_H_(0x27, 0x36) ++#define REG_SC_BK27_37_L _PK_L_(0x27, 0x37) ++#define REG_SC_BK27_37_H _PK_H_(0x27, 0x37) ++#define REG_SC_BK27_38_L _PK_L_(0x27, 0x38) ++#define REG_SC_BK27_38_H _PK_H_(0x27, 0x38) ++#define REG_SC_BK27_39_L _PK_L_(0x27, 0x39) ++#define REG_SC_BK27_39_H _PK_H_(0x27, 0x39) ++#define REG_SC_BK27_3A_L _PK_L_(0x27, 0x3A) ++#define REG_SC_BK27_3A_H _PK_H_(0x27, 0x3A) ++#define REG_SC_BK27_3B_L _PK_L_(0x27, 0x3B) ++#define REG_SC_BK27_3B_H _PK_H_(0x27, 0x3B) ++#define REG_SC_BK27_3C_L _PK_L_(0x27, 0x3C) ++#define REG_SC_BK27_3C_H _PK_H_(0x27, 0x3C) ++#define REG_SC_BK27_3D_L _PK_L_(0x27, 0x3D) ++#define REG_SC_BK27_3D_H _PK_H_(0x27, 0x3D) ++#define REG_SC_BK27_3E_L _PK_L_(0x27, 0x3E) ++#define REG_SC_BK27_3E_H _PK_H_(0x27, 0x3E) ++#define REG_SC_BK27_3F_L _PK_L_(0x27, 0x3F) ++#define REG_SC_BK27_3F_H _PK_H_(0x27, 0x3F) ++#define REG_SC_BK27_40_L _PK_L_(0x27, 0x40) ++#define REG_SC_BK27_40_H _PK_H_(0x27, 0x40) ++#define REG_SC_BK27_41_L _PK_L_(0x27, 0x41) ++#define REG_SC_BK27_41_H _PK_H_(0x27, 0x41) ++#define REG_SC_BK27_42_L _PK_L_(0x27, 0x42) ++#define REG_SC_BK27_42_H _PK_H_(0x27, 0x42) ++#define REG_SC_BK27_43_L _PK_L_(0x27, 0x43) ++#define REG_SC_BK27_43_H _PK_H_(0x27, 0x43) ++#define REG_SC_BK27_44_L _PK_L_(0x27, 0x44) ++#define REG_SC_BK27_44_H _PK_H_(0x27, 0x44) ++#define REG_SC_BK27_45_L _PK_L_(0x27, 0x45) ++#define REG_SC_BK27_45_H _PK_H_(0x27, 0x45) ++#define REG_SC_BK27_46_L _PK_L_(0x27, 0x46) ++#define REG_SC_BK27_46_H _PK_H_(0x27, 0x46) ++#define REG_SC_BK27_47_L _PK_L_(0x27, 0x47) ++#define REG_SC_BK27_47_H _PK_H_(0x27, 0x47) ++#define REG_SC_BK27_48_L _PK_L_(0x27, 0x48) ++#define REG_SC_BK27_48_H _PK_H_(0x27, 0x48) ++#define REG_SC_BK27_49_L _PK_L_(0x27, 0x49) ++#define REG_SC_BK27_49_H _PK_H_(0x27, 0x49) ++#define REG_SC_BK27_4A_L _PK_L_(0x27, 0x4A) ++#define REG_SC_BK27_4A_H _PK_H_(0x27, 0x4A) ++#define REG_SC_BK27_4B_L _PK_L_(0x27, 0x4B) ++#define REG_SC_BK27_4B_H _PK_H_(0x27, 0x4B) ++#define REG_SC_BK27_4C_L _PK_L_(0x27, 0x4C) ++#define REG_SC_BK27_4C_H _PK_H_(0x27, 0x4C) ++#define REG_SC_BK27_4D_L _PK_L_(0x27, 0x4D) ++#define REG_SC_BK27_4D_H _PK_H_(0x27, 0x4D) ++#define REG_SC_BK27_4E_L _PK_L_(0x27, 0x4E) ++#define REG_SC_BK27_4E_H _PK_H_(0x27, 0x4E) ++#define REG_SC_BK27_4F_L _PK_L_(0x27, 0x4F) ++#define REG_SC_BK27_4F_H _PK_H_(0x27, 0x4F) ++#define REG_SC_BK27_50_L _PK_L_(0x27, 0x50) ++#define REG_SC_BK27_50_H _PK_H_(0x27, 0x50) ++#define REG_SC_BK27_51_L _PK_L_(0x27, 0x51) ++#define REG_SC_BK27_51_H _PK_H_(0x27, 0x51) ++#define REG_SC_BK27_52_L _PK_L_(0x27, 0x52) ++#define REG_SC_BK27_52_H _PK_H_(0x27, 0x52) ++#define REG_SC_BK27_53_L _PK_L_(0x27, 0x53) ++#define REG_SC_BK27_53_H _PK_H_(0x27, 0x53) ++#define REG_SC_BK27_54_L _PK_L_(0x27, 0x54) ++#define REG_SC_BK27_54_H _PK_H_(0x27, 0x54) ++#define REG_SC_BK27_55_L _PK_L_(0x27, 0x55) ++#define REG_SC_BK27_55_H _PK_H_(0x27, 0x55) ++#define REG_SC_BK27_56_L _PK_L_(0x27, 0x56) ++#define REG_SC_BK27_56_H _PK_H_(0x27, 0x56) ++#define REG_SC_BK27_57_L _PK_L_(0x27, 0x57) ++#define REG_SC_BK27_57_H _PK_H_(0x27, 0x57) ++#define REG_SC_BK27_58_L _PK_L_(0x27, 0x58) ++#define REG_SC_BK27_58_H _PK_H_(0x27, 0x58) ++#define REG_SC_BK27_59_L _PK_L_(0x27, 0x59) ++#define REG_SC_BK27_59_H _PK_H_(0x27, 0x59) ++#define REG_SC_BK27_5A_L _PK_L_(0x27, 0x5A) ++#define REG_SC_BK27_5A_H _PK_H_(0x27, 0x5A) ++#define REG_SC_BK27_5B_L _PK_L_(0x27, 0x5B) ++#define REG_SC_BK27_5B_H _PK_H_(0x27, 0x5B) ++#define REG_SC_BK27_5C_L _PK_L_(0x27, 0x5C) ++#define REG_SC_BK27_5C_H _PK_H_(0x27, 0x5C) ++#define REG_SC_BK27_5D_L _PK_L_(0x27, 0x5D) ++#define REG_SC_BK27_5D_H _PK_H_(0x27, 0x5D) ++#define REG_SC_BK27_5E_L _PK_L_(0x27, 0x5E) ++#define REG_SC_BK27_5E_H _PK_H_(0x27, 0x5E) ++#define REG_SC_BK27_5F_L _PK_L_(0x27, 0x5F) ++#define REG_SC_BK27_5F_H _PK_H_(0x27, 0x5F) ++#define REG_SC_BK27_60_L _PK_L_(0x27, 0x60) ++#define REG_SC_BK27_60_H _PK_H_(0x27, 0x60) ++#define REG_SC_BK27_61_L _PK_L_(0x27, 0x61) ++#define REG_SC_BK27_61_H _PK_H_(0x27, 0x61) ++#define REG_SC_BK27_62_L _PK_L_(0x27, 0x62) ++#define REG_SC_BK27_62_H _PK_H_(0x27, 0x62) ++#define REG_SC_BK27_63_L _PK_L_(0x27, 0x63) ++#define REG_SC_BK27_63_H _PK_H_(0x27, 0x63) ++#define REG_SC_BK27_64_L _PK_L_(0x27, 0x64) ++#define REG_SC_BK27_64_H _PK_H_(0x27, 0x64) ++#define REG_SC_BK27_65_L _PK_L_(0x27, 0x65) ++#define REG_SC_BK27_65_H _PK_H_(0x27, 0x65) ++#define REG_SC_BK27_66_L _PK_L_(0x27, 0x66) ++#define REG_SC_BK27_66_H _PK_H_(0x27, 0x66) ++#define REG_SC_BK27_67_L _PK_L_(0x27, 0x67) ++#define REG_SC_BK27_67_H _PK_H_(0x27, 0x67) ++#define REG_SC_BK27_68_L _PK_L_(0x27, 0x68) ++#define REG_SC_BK27_68_H _PK_H_(0x27, 0x68) ++#define REG_SC_BK27_69_L _PK_L_(0x27, 0x69) ++#define REG_SC_BK27_69_H _PK_H_(0x27, 0x69) ++#define REG_SC_BK27_6A_L _PK_L_(0x27, 0x6A) ++#define REG_SC_BK27_6A_H _PK_H_(0x27, 0x6A) ++#define REG_SC_BK27_6B_L _PK_L_(0x27, 0x6B) ++#define REG_SC_BK27_6B_H _PK_H_(0x27, 0x6B) ++#define REG_SC_BK27_6C_L _PK_L_(0x27, 0x6C) ++#define REG_SC_BK27_6C_H _PK_H_(0x27, 0x6C) ++#define REG_SC_BK27_6D_L _PK_L_(0x27, 0x6D) ++#define REG_SC_BK27_6D_H _PK_H_(0x27, 0x6D) ++#define REG_SC_BK27_6E_L _PK_L_(0x27, 0x6E) ++#define REG_SC_BK27_6E_H _PK_H_(0x27, 0x6E) ++#define REG_SC_BK27_6F_L _PK_L_(0x27, 0x6F) ++#define REG_SC_BK27_6F_H _PK_H_(0x27, 0x6F) ++#define REG_SC_BK27_70_L _PK_L_(0x27, 0x70) ++#define REG_SC_BK27_70_H _PK_H_(0x27, 0x70) ++#define REG_SC_BK27_71_L _PK_L_(0x27, 0x71) ++#define REG_SC_BK27_71_H _PK_H_(0x27, 0x71) ++#define REG_SC_BK27_72_L _PK_L_(0x27, 0x72) ++#define REG_SC_BK27_72_H _PK_H_(0x27, 0x72) ++#define REG_SC_BK27_73_L _PK_L_(0x27, 0x73) ++#define REG_SC_BK27_73_H _PK_H_(0x27, 0x73) ++#define REG_SC_BK27_74_L _PK_L_(0x27, 0x74) ++#define REG_SC_BK27_74_H _PK_H_(0x27, 0x74) ++#define REG_SC_BK27_75_L _PK_L_(0x27, 0x75) ++#define REG_SC_BK27_75_H _PK_H_(0x27, 0x75) ++#define REG_SC_BK27_76_L _PK_L_(0x27, 0x76) ++#define REG_SC_BK27_76_H _PK_H_(0x27, 0x76) ++#define REG_SC_BK27_77_L _PK_L_(0x27, 0x77) ++#define REG_SC_BK27_77_H _PK_H_(0x27, 0x77) ++#define REG_SC_BK27_78_L _PK_L_(0x27, 0x78) ++#define REG_SC_BK27_78_H _PK_H_(0x27, 0x78) ++#define REG_SC_BK27_79_L _PK_L_(0x27, 0x79) ++#define REG_SC_BK27_79_H _PK_H_(0x27, 0x79) ++#define REG_SC_BK27_7A_L _PK_L_(0x27, 0x7A) ++#define REG_SC_BK27_7A_H _PK_H_(0x27, 0x7A) ++#define REG_SC_BK27_7B_L _PK_L_(0x27, 0x7B) ++#define REG_SC_BK27_7B_H _PK_H_(0x27, 0x7B) ++#define REG_SC_BK27_7C_L _PK_L_(0x27, 0x7C) ++#define REG_SC_BK27_7C_H _PK_H_(0x27, 0x7C) ++#define REG_SC_BK27_7D_L _PK_L_(0x27, 0x7D) ++#define REG_SC_BK27_7D_H _PK_H_(0x27, 0x7D) ++#define REG_SC_BK27_7E_L _PK_L_(0x27, 0x7E) ++#define REG_SC_BK27_7E_H _PK_H_(0x27, 0x7E) ++#define REG_SC_BK27_7F_L _PK_L_(0x27, 0x7F) ++#define REG_SC_BK27_7F_H _PK_H_(0x27, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK28_00_L _PK_L_(0x28, 0x00) ++#define REG_SC_BK28_00_H _PK_H_(0x28, 0x00) ++#define REG_SC_BK28_01_L _PK_L_(0x28, 0x01) ++#define REG_SC_BK28_01_H _PK_H_(0x28, 0x01) ++#define REG_SC_BK28_02_L _PK_L_(0x28, 0x02) ++#define REG_SC_BK28_02_H _PK_H_(0x28, 0x02) ++#define REG_SC_BK28_03_L _PK_L_(0x28, 0x03) ++#define REG_SC_BK28_03_H _PK_H_(0x28, 0x03) ++#define REG_SC_BK28_04_L _PK_L_(0x28, 0x04) ++#define REG_SC_BK28_04_H _PK_H_(0x28, 0x04) ++#define REG_SC_BK28_05_L _PK_L_(0x28, 0x05) ++#define REG_SC_BK28_05_H _PK_H_(0x28, 0x05) ++#define REG_SC_BK28_06_L _PK_L_(0x28, 0x06) ++#define REG_SC_BK28_06_H _PK_H_(0x28, 0x06) ++#define REG_SC_BK28_07_L _PK_L_(0x28, 0x07) ++#define REG_SC_BK28_07_H _PK_H_(0x28, 0x07) ++#define REG_SC_BK28_08_L _PK_L_(0x28, 0x08) ++#define REG_SC_BK28_08_H _PK_H_(0x28, 0x08) ++#define REG_SC_BK28_09_L _PK_L_(0x28, 0x09) ++#define REG_SC_BK28_09_H _PK_H_(0x28, 0x09) ++#define REG_SC_BK28_0A_L _PK_L_(0x28, 0x0A) ++#define REG_SC_BK28_0A_H _PK_H_(0x28, 0x0A) ++#define REG_SC_BK28_0B_L _PK_L_(0x28, 0x0B) ++#define REG_SC_BK28_0B_H _PK_H_(0x28, 0x0B) ++#define REG_SC_BK28_0C_L _PK_L_(0x28, 0x0C) ++#define REG_SC_BK28_0C_H _PK_H_(0x28, 0x0C) ++#define REG_SC_BK28_0D_L _PK_L_(0x28, 0x0D) ++#define REG_SC_BK28_0D_H _PK_H_(0x28, 0x0D) ++#define REG_SC_BK28_0E_L _PK_L_(0x28, 0x0E) ++#define REG_SC_BK28_0E_H _PK_H_(0x28, 0x0E) ++#define REG_SC_BK28_0F_L _PK_L_(0x28, 0x0F) ++#define REG_SC_BK28_0F_H _PK_H_(0x28, 0x0F) ++#define REG_SC_BK28_10_L _PK_L_(0x28, 0x10) ++#define REG_SC_BK28_10_H _PK_H_(0x28, 0x10) ++#define REG_SC_BK28_11_L _PK_L_(0x28, 0x11) ++#define REG_SC_BK28_11_H _PK_H_(0x28, 0x11) ++#define REG_SC_BK28_12_L _PK_L_(0x28, 0x12) ++#define REG_SC_BK28_12_H _PK_H_(0x28, 0x12) ++#define REG_SC_BK28_13_L _PK_L_(0x28, 0x13) ++#define REG_SC_BK28_13_H _PK_H_(0x28, 0x13) ++#define REG_SC_BK28_14_L _PK_L_(0x28, 0x14) ++#define REG_SC_BK28_14_H _PK_H_(0x28, 0x14) ++#define REG_SC_BK28_15_L _PK_L_(0x28, 0x15) ++#define REG_SC_BK28_15_H _PK_H_(0x28, 0x15) ++#define REG_SC_BK28_16_L _PK_L_(0x28, 0x16) ++#define REG_SC_BK28_16_H _PK_H_(0x28, 0x16) ++#define REG_SC_BK28_17_L _PK_L_(0x28, 0x17) ++#define REG_SC_BK28_17_H _PK_H_(0x28, 0x17) ++#define REG_SC_BK28_18_L _PK_L_(0x28, 0x18) ++#define REG_SC_BK28_18_H _PK_H_(0x28, 0x18) ++#define REG_SC_BK28_19_L _PK_L_(0x28, 0x19) ++#define REG_SC_BK28_19_H _PK_H_(0x28, 0x19) ++#define REG_SC_BK28_1A_L _PK_L_(0x28, 0x1A) ++#define REG_SC_BK28_1A_H _PK_H_(0x28, 0x1A) ++#define REG_SC_BK28_1B_L _PK_L_(0x28, 0x1B) ++#define REG_SC_BK28_1B_H _PK_H_(0x28, 0x1B) ++#define REG_SC_BK28_1C_L _PK_L_(0x28, 0x1C) ++#define REG_SC_BK28_1C_H _PK_H_(0x28, 0x1C) ++#define REG_SC_BK28_1D_L _PK_L_(0x28, 0x1D) ++#define REG_SC_BK28_1D_H _PK_H_(0x28, 0x1D) ++#define REG_SC_BK28_1E_L _PK_L_(0x28, 0x1E) ++#define REG_SC_BK28_1E_H _PK_H_(0x28, 0x1E) ++#define REG_SC_BK28_1F_L _PK_L_(0x28, 0x1F) ++#define REG_SC_BK28_1F_H _PK_H_(0x28, 0x1F) ++#define REG_SC_BK28_20_L _PK_L_(0x28, 0x20) ++#define REG_SC_BK28_20_H _PK_H_(0x28, 0x20) ++#define REG_SC_BK28_21_L _PK_L_(0x28, 0x21) ++#define REG_SC_BK28_21_H _PK_H_(0x28, 0x21) ++#define REG_SC_BK28_22_L _PK_L_(0x28, 0x22) ++#define REG_SC_BK28_22_H _PK_H_(0x28, 0x22) ++#define REG_SC_BK28_23_L _PK_L_(0x28, 0x23) ++#define REG_SC_BK28_23_H _PK_H_(0x28, 0x23) ++#define REG_SC_BK28_24_L _PK_L_(0x28, 0x24) ++#define REG_SC_BK28_24_H _PK_H_(0x28, 0x24) ++#define REG_SC_BK28_25_L _PK_L_(0x28, 0x25) ++#define REG_SC_BK28_25_H _PK_H_(0x28, 0x25) ++#define REG_SC_BK28_26_L _PK_L_(0x28, 0x26) ++#define REG_SC_BK28_26_H _PK_H_(0x28, 0x26) ++#define REG_SC_BK28_27_L _PK_L_(0x28, 0x27) ++#define REG_SC_BK28_27_H _PK_H_(0x28, 0x27) ++#define REG_SC_BK28_28_L _PK_L_(0x28, 0x28) ++#define REG_SC_BK28_28_H _PK_H_(0x28, 0x28) ++#define REG_SC_BK28_29_L _PK_L_(0x28, 0x29) ++#define REG_SC_BK28_29_H _PK_H_(0x28, 0x29) ++#define REG_SC_BK28_2A_L _PK_L_(0x28, 0x2A) ++#define REG_SC_BK28_2A_H _PK_H_(0x28, 0x2A) ++#define REG_SC_BK28_2B_L _PK_L_(0x28, 0x2B) ++#define REG_SC_BK28_2B_H _PK_H_(0x28, 0x2B) ++#define REG_SC_BK28_2C_L _PK_L_(0x28, 0x2C) ++#define REG_SC_BK28_2C_H _PK_H_(0x28, 0x2C) ++#define REG_SC_BK28_2D_L _PK_L_(0x28, 0x2D) ++#define REG_SC_BK28_2D_H _PK_H_(0x28, 0x2D) ++#define REG_SC_BK28_2E_L _PK_L_(0x28, 0x2E) ++#define REG_SC_BK28_2E_H _PK_H_(0x28, 0x2E) ++#define REG_SC_BK28_2F_L _PK_L_(0x28, 0x2F) ++#define REG_SC_BK28_2F_H _PK_H_(0x28, 0x2F) ++#define REG_SC_BK28_30_L _PK_L_(0x28, 0x30) ++#define REG_SC_BK28_30_H _PK_H_(0x28, 0x30) ++#define REG_SC_BK28_31_L _PK_L_(0x28, 0x31) ++#define REG_SC_BK28_31_H _PK_H_(0x28, 0x31) ++#define REG_SC_BK28_32_L _PK_L_(0x28, 0x32) ++#define REG_SC_BK28_32_H _PK_H_(0x28, 0x32) ++#define REG_SC_BK28_33_L _PK_L_(0x28, 0x33) ++#define REG_SC_BK28_33_H _PK_H_(0x28, 0x33) ++#define REG_SC_BK28_34_L _PK_L_(0x28, 0x34) ++#define REG_SC_BK28_34_H _PK_H_(0x28, 0x34) ++#define REG_SC_BK28_35_L _PK_L_(0x28, 0x35) ++#define REG_SC_BK28_35_H _PK_H_(0x28, 0x35) ++#define REG_SC_BK28_36_L _PK_L_(0x28, 0x36) ++#define REG_SC_BK28_36_H _PK_H_(0x28, 0x36) ++#define REG_SC_BK28_37_L _PK_L_(0x28, 0x37) ++#define REG_SC_BK28_37_H _PK_H_(0x28, 0x37) ++#define REG_SC_BK28_38_L _PK_L_(0x28, 0x38) ++#define REG_SC_BK28_38_H _PK_H_(0x28, 0x38) ++#define REG_SC_BK28_39_L _PK_L_(0x28, 0x39) ++#define REG_SC_BK28_39_H _PK_H_(0x28, 0x39) ++#define REG_SC_BK28_3A_L _PK_L_(0x28, 0x3A) ++#define REG_SC_BK28_3A_H _PK_H_(0x28, 0x3A) ++#define REG_SC_BK28_3B_L _PK_L_(0x28, 0x3B) ++#define REG_SC_BK28_3B_H _PK_H_(0x28, 0x3B) ++#define REG_SC_BK28_3C_L _PK_L_(0x28, 0x3C) ++#define REG_SC_BK28_3C_H _PK_H_(0x28, 0x3C) ++#define REG_SC_BK28_3D_L _PK_L_(0x28, 0x3D) ++#define REG_SC_BK28_3D_H _PK_H_(0x28, 0x3D) ++#define REG_SC_BK28_3E_L _PK_L_(0x28, 0x3E) ++#define REG_SC_BK28_3E_H _PK_H_(0x28, 0x3E) ++#define REG_SC_BK28_3F_L _PK_L_(0x28, 0x3F) ++#define REG_SC_BK28_3F_H _PK_H_(0x28, 0x3F) ++#define REG_SC_BK28_40_L _PK_L_(0x28, 0x40) ++#define REG_SC_BK28_40_H _PK_H_(0x28, 0x40) ++#define REG_SC_BK28_41_L _PK_L_(0x28, 0x41) ++#define REG_SC_BK28_41_H _PK_H_(0x28, 0x41) ++#define REG_SC_BK28_42_L _PK_L_(0x28, 0x42) ++#define REG_SC_BK28_42_H _PK_H_(0x28, 0x42) ++#define REG_SC_BK28_43_L _PK_L_(0x28, 0x43) ++#define REG_SC_BK28_43_H _PK_H_(0x28, 0x43) ++#define REG_SC_BK28_44_L _PK_L_(0x28, 0x44) ++#define REG_SC_BK28_44_H _PK_H_(0x28, 0x44) ++#define REG_SC_BK28_45_L _PK_L_(0x28, 0x45) ++#define REG_SC_BK28_45_H _PK_H_(0x28, 0x45) ++#define REG_SC_BK28_46_L _PK_L_(0x28, 0x46) ++#define REG_SC_BK28_46_H _PK_H_(0x28, 0x46) ++#define REG_SC_BK28_47_L _PK_L_(0x28, 0x47) ++#define REG_SC_BK28_47_H _PK_H_(0x28, 0x47) ++#define REG_SC_BK28_48_L _PK_L_(0x28, 0x48) ++#define REG_SC_BK28_48_H _PK_H_(0x28, 0x48) ++#define REG_SC_BK28_49_L _PK_L_(0x28, 0x49) ++#define REG_SC_BK28_49_H _PK_H_(0x28, 0x49) ++#define REG_SC_BK28_4A_L _PK_L_(0x28, 0x4A) ++#define REG_SC_BK28_4A_H _PK_H_(0x28, 0x4A) ++#define REG_SC_BK28_4B_L _PK_L_(0x28, 0x4B) ++#define REG_SC_BK28_4B_H _PK_H_(0x28, 0x4B) ++#define REG_SC_BK28_4C_L _PK_L_(0x28, 0x4C) ++#define REG_SC_BK28_4C_H _PK_H_(0x28, 0x4C) ++#define REG_SC_BK28_4D_L _PK_L_(0x28, 0x4D) ++#define REG_SC_BK28_4D_H _PK_H_(0x28, 0x4D) ++#define REG_SC_BK28_4E_L _PK_L_(0x28, 0x4E) ++#define REG_SC_BK28_4E_H _PK_H_(0x28, 0x4E) ++#define REG_SC_BK28_4F_L _PK_L_(0x28, 0x4F) ++#define REG_SC_BK28_4F_H _PK_H_(0x28, 0x4F) ++#define REG_SC_BK28_50_L _PK_L_(0x28, 0x50) ++#define REG_SC_BK28_50_H _PK_H_(0x28, 0x50) ++#define REG_SC_BK28_51_L _PK_L_(0x28, 0x51) ++#define REG_SC_BK28_51_H _PK_H_(0x28, 0x51) ++#define REG_SC_BK28_52_L _PK_L_(0x28, 0x52) ++#define REG_SC_BK28_52_H _PK_H_(0x28, 0x52) ++#define REG_SC_BK28_53_L _PK_L_(0x28, 0x53) ++#define REG_SC_BK28_53_H _PK_H_(0x28, 0x53) ++#define REG_SC_BK28_54_L _PK_L_(0x28, 0x54) ++#define REG_SC_BK28_54_H _PK_H_(0x28, 0x54) ++#define REG_SC_BK28_55_L _PK_L_(0x28, 0x55) ++#define REG_SC_BK28_55_H _PK_H_(0x28, 0x55) ++#define REG_SC_BK28_56_L _PK_L_(0x28, 0x56) ++#define REG_SC_BK28_56_H _PK_H_(0x28, 0x56) ++#define REG_SC_BK28_57_L _PK_L_(0x28, 0x57) ++#define REG_SC_BK28_57_H _PK_H_(0x28, 0x57) ++#define REG_SC_BK28_58_L _PK_L_(0x28, 0x58) ++#define REG_SC_BK28_58_H _PK_H_(0x28, 0x58) ++#define REG_SC_BK28_59_L _PK_L_(0x28, 0x59) ++#define REG_SC_BK28_59_H _PK_H_(0x28, 0x59) ++#define REG_SC_BK28_5A_L _PK_L_(0x28, 0x5A) ++#define REG_SC_BK28_5A_H _PK_H_(0x28, 0x5A) ++#define REG_SC_BK28_5B_L _PK_L_(0x28, 0x5B) ++#define REG_SC_BK28_5B_H _PK_H_(0x28, 0x5B) ++#define REG_SC_BK28_5C_L _PK_L_(0x28, 0x5C) ++#define REG_SC_BK28_5C_H _PK_H_(0x28, 0x5C) ++#define REG_SC_BK28_5D_L _PK_L_(0x28, 0x5D) ++#define REG_SC_BK28_5D_H _PK_H_(0x28, 0x5D) ++#define REG_SC_BK28_5E_L _PK_L_(0x28, 0x5E) ++#define REG_SC_BK28_5E_H _PK_H_(0x28, 0x5E) ++#define REG_SC_BK28_5F_L _PK_L_(0x28, 0x5F) ++#define REG_SC_BK28_5F_H _PK_H_(0x28, 0x5F) ++#define REG_SC_BK28_60_L _PK_L_(0x28, 0x60) ++#define REG_SC_BK28_60_H _PK_H_(0x28, 0x60) ++#define REG_SC_BK28_61_L _PK_L_(0x28, 0x61) ++#define REG_SC_BK28_61_H _PK_H_(0x28, 0x61) ++#define REG_SC_BK28_62_L _PK_L_(0x28, 0x62) ++#define REG_SC_BK28_62_H _PK_H_(0x28, 0x62) ++#define REG_SC_BK28_63_L _PK_L_(0x28, 0x63) ++#define REG_SC_BK28_63_H _PK_H_(0x28, 0x63) ++#define REG_SC_BK28_64_L _PK_L_(0x28, 0x64) ++#define REG_SC_BK28_64_H _PK_H_(0x28, 0x64) ++#define REG_SC_BK28_65_L _PK_L_(0x28, 0x65) ++#define REG_SC_BK28_65_H _PK_H_(0x28, 0x65) ++#define REG_SC_BK28_66_L _PK_L_(0x28, 0x66) ++#define REG_SC_BK28_66_H _PK_H_(0x28, 0x66) ++#define REG_SC_BK28_67_L _PK_L_(0x28, 0x67) ++#define REG_SC_BK28_67_H _PK_H_(0x28, 0x67) ++#define REG_SC_BK28_68_L _PK_L_(0x28, 0x68) ++#define REG_SC_BK28_68_H _PK_H_(0x28, 0x68) ++#define REG_SC_BK28_69_L _PK_L_(0x28, 0x69) ++#define REG_SC_BK28_69_H _PK_H_(0x28, 0x69) ++#define REG_SC_BK28_6A_L _PK_L_(0x28, 0x6A) ++#define REG_SC_BK28_6A_H _PK_H_(0x28, 0x6A) ++#define REG_SC_BK28_6B_L _PK_L_(0x28, 0x6B) ++#define REG_SC_BK28_6B_H _PK_H_(0x28, 0x6B) ++#define REG_SC_BK28_6C_L _PK_L_(0x28, 0x6C) ++#define REG_SC_BK28_6C_H _PK_H_(0x28, 0x6C) ++#define REG_SC_BK28_6D_L _PK_L_(0x28, 0x6D) ++#define REG_SC_BK28_6D_H _PK_H_(0x28, 0x6D) ++#define REG_SC_BK28_6E_L _PK_L_(0x28, 0x6E) ++#define REG_SC_BK28_6E_H _PK_H_(0x28, 0x6E) ++#define REG_SC_BK28_6F_L _PK_L_(0x28, 0x6F) ++#define REG_SC_BK28_6F_H _PK_H_(0x28, 0x6F) ++#define REG_SC_BK28_70_L _PK_L_(0x28, 0x70) ++#define REG_SC_BK28_70_H _PK_H_(0x28, 0x70) ++#define REG_SC_BK28_71_L _PK_L_(0x28, 0x71) ++#define REG_SC_BK28_71_H _PK_H_(0x28, 0x71) ++#define REG_SC_BK28_72_L _PK_L_(0x28, 0x72) ++#define REG_SC_BK28_72_H _PK_H_(0x28, 0x72) ++#define REG_SC_BK28_73_L _PK_L_(0x28, 0x73) ++#define REG_SC_BK28_73_H _PK_H_(0x28, 0x73) ++#define REG_SC_BK28_74_L _PK_L_(0x28, 0x74) ++#define REG_SC_BK28_74_H _PK_H_(0x28, 0x74) ++#define REG_SC_BK28_75_L _PK_L_(0x28, 0x75) ++#define REG_SC_BK28_75_H _PK_H_(0x28, 0x75) ++#define REG_SC_BK28_76_L _PK_L_(0x28, 0x76) ++#define REG_SC_BK28_76_H _PK_H_(0x28, 0x76) ++#define REG_SC_BK28_77_L _PK_L_(0x28, 0x77) ++#define REG_SC_BK28_77_H _PK_H_(0x28, 0x77) ++#define REG_SC_BK28_78_L _PK_L_(0x28, 0x78) ++#define REG_SC_BK28_78_H _PK_H_(0x28, 0x78) ++#define REG_SC_BK28_79_L _PK_L_(0x28, 0x79) ++#define REG_SC_BK28_79_H _PK_H_(0x28, 0x79) ++#define REG_SC_BK28_7A_L _PK_L_(0x28, 0x7A) ++#define REG_SC_BK28_7A_H _PK_H_(0x28, 0x7A) ++#define REG_SC_BK28_7B_L _PK_L_(0x28, 0x7B) ++#define REG_SC_BK28_7B_H _PK_H_(0x28, 0x7B) ++#define REG_SC_BK28_7C_L _PK_L_(0x28, 0x7C) ++#define REG_SC_BK28_7C_H _PK_H_(0x28, 0x7C) ++#define REG_SC_BK28_7D_L _PK_L_(0x28, 0x7D) ++#define REG_SC_BK28_7D_H _PK_H_(0x28, 0x7D) ++#define REG_SC_BK28_7E_L _PK_L_(0x28, 0x7E) ++#define REG_SC_BK28_7E_H _PK_H_(0x28, 0x7E) ++#define REG_SC_BK28_7F_L _PK_L_(0x28, 0x7F) ++#define REG_SC_BK28_7F_H _PK_H_(0x28, 0x7F) ++//----------------------------------------------//---------------------------------------------- ++#define REG_SC_BK29_00_L _PK_L_(0x29, 0x00) ++#define REG_SC_BK29_00_H _PK_H_(0x29, 0x00) ++#define REG_SC_BK29_01_L _PK_L_(0x29, 0x01) ++#define REG_SC_BK29_01_H _PK_H_(0x29, 0x01) ++#define REG_SC_BK29_02_L _PK_L_(0x29, 0x02) ++#define REG_SC_BK29_02_H _PK_H_(0x29, 0x02) ++#define REG_SC_BK29_03_L _PK_L_(0x29, 0x03) ++#define REG_SC_BK29_03_H _PK_H_(0x29, 0x03) ++#define REG_SC_BK29_04_L _PK_L_(0x29, 0x04) ++#define REG_SC_BK29_04_H _PK_H_(0x29, 0x04) ++#define REG_SC_BK29_05_L _PK_L_(0x29, 0x05) ++#define REG_SC_BK29_05_H _PK_H_(0x29, 0x05) ++#define REG_SC_BK29_06_L _PK_L_(0x29, 0x06) ++#define REG_SC_BK29_06_H _PK_H_(0x29, 0x06) ++#define REG_SC_BK29_07_L _PK_L_(0x29, 0x07) ++#define REG_SC_BK29_07_H _PK_H_(0x29, 0x07) ++#define REG_SC_BK29_08_L _PK_L_(0x29, 0x08) ++#define REG_SC_BK29_08_H _PK_H_(0x29, 0x08) ++#define REG_SC_BK29_09_L _PK_L_(0x29, 0x09) ++#define REG_SC_BK29_09_H _PK_H_(0x29, 0x09) ++#define REG_SC_BK29_0A_L _PK_L_(0x29, 0x0A) ++#define REG_SC_BK29_0A_H _PK_H_(0x29, 0x0A) ++#define REG_SC_BK29_0B_L _PK_L_(0x29, 0x0B) ++#define REG_SC_BK29_0B_H _PK_H_(0x29, 0x0B) ++#define REG_SC_BK29_0C_L _PK_L_(0x29, 0x0C) ++#define REG_SC_BK29_0C_H _PK_H_(0x29, 0x0C) ++#define REG_SC_BK29_0D_L _PK_L_(0x29, 0x0D) ++#define REG_SC_BK29_0D_H _PK_H_(0x29, 0x0D) ++#define REG_SC_BK29_0E_L _PK_L_(0x29, 0x0E) ++#define REG_SC_BK29_0E_H _PK_H_(0x29, 0x0E) ++#define REG_SC_BK29_0F_L _PK_L_(0x29, 0x0F) ++#define REG_SC_BK29_0F_H _PK_H_(0x29, 0x0F) ++#define REG_SC_BK29_10_L _PK_L_(0x29, 0x10) ++#define REG_SC_BK29_10_H _PK_H_(0x29, 0x10) ++#define REG_SC_BK29_11_L _PK_L_(0x29, 0x11) ++#define REG_SC_BK29_11_H _PK_H_(0x29, 0x11) ++#define REG_SC_BK29_12_L _PK_L_(0x29, 0x12) ++#define REG_SC_BK29_12_H _PK_H_(0x29, 0x12) ++#define REG_SC_BK29_13_L _PK_L_(0x29, 0x13) ++#define REG_SC_BK29_13_H _PK_H_(0x29, 0x13) ++#define REG_SC_BK29_14_L _PK_L_(0x29, 0x14) ++#define REG_SC_BK29_14_H _PK_H_(0x29, 0x14) ++#define REG_SC_BK29_15_L _PK_L_(0x29, 0x15) ++#define REG_SC_BK29_15_H _PK_H_(0x29, 0x15) ++#define REG_SC_BK29_16_L _PK_L_(0x29, 0x16) ++#define REG_SC_BK29_16_H _PK_H_(0x29, 0x16) ++#define REG_SC_BK29_17_L _PK_L_(0x29, 0x17) ++#define REG_SC_BK29_17_H _PK_H_(0x29, 0x17) ++#define REG_SC_BK29_18_L _PK_L_(0x29, 0x18) ++#define REG_SC_BK29_18_H _PK_H_(0x29, 0x18) ++#define REG_SC_BK29_19_L _PK_L_(0x29, 0x19) ++#define REG_SC_BK29_19_H _PK_H_(0x29, 0x19) ++#define REG_SC_BK29_1A_L _PK_L_(0x29, 0x1A) ++#define REG_SC_BK29_1A_H _PK_H_(0x29, 0x1A) ++#define REG_SC_BK29_1B_L _PK_L_(0x29, 0x1B) ++#define REG_SC_BK29_1B_H _PK_H_(0x29, 0x1B) ++#define REG_SC_BK29_1C_L _PK_L_(0x29, 0x1C) ++#define REG_SC_BK29_1C_H _PK_H_(0x29, 0x1C) ++#define REG_SC_BK29_1D_L _PK_L_(0x29, 0x1D) ++#define REG_SC_BK29_1D_H _PK_H_(0x29, 0x1D) ++#define REG_SC_BK29_1E_L _PK_L_(0x29, 0x1E) ++#define REG_SC_BK29_1E_H _PK_H_(0x29, 0x1E) ++#define REG_SC_BK29_1F_L _PK_L_(0x29, 0x1F) ++#define REG_SC_BK29_1F_H _PK_H_(0x29, 0x1F) ++#define REG_SC_BK29_20_L _PK_L_(0x29, 0x20) ++#define REG_SC_BK29_20_H _PK_H_(0x29, 0x20) ++#define REG_SC_BK29_21_L _PK_L_(0x29, 0x21) ++#define REG_SC_BK29_21_H _PK_H_(0x29, 0x21) ++#define REG_SC_BK29_22_L _PK_L_(0x29, 0x22) ++#define REG_SC_BK29_22_H _PK_H_(0x29, 0x22) ++#define REG_SC_BK29_23_L _PK_L_(0x29, 0x23) ++#define REG_SC_BK29_23_H _PK_H_(0x29, 0x23) ++#define REG_SC_BK29_24_L _PK_L_(0x29, 0x24) ++#define REG_SC_BK29_24_H _PK_H_(0x29, 0x24) ++#define REG_SC_BK29_25_L _PK_L_(0x29, 0x25) ++#define REG_SC_BK29_25_H _PK_H_(0x29, 0x25) ++#define REG_SC_BK29_26_L _PK_L_(0x29, 0x26) ++#define REG_SC_BK29_26_H _PK_H_(0x29, 0x26) ++#define REG_SC_BK29_27_L _PK_L_(0x29, 0x27) ++#define REG_SC_BK29_27_H _PK_H_(0x29, 0x27) ++#define REG_SC_BK29_28_L _PK_L_(0x29, 0x28) ++#define REG_SC_BK29_28_H _PK_H_(0x29, 0x28) ++#define REG_SC_BK29_29_L _PK_L_(0x29, 0x29) ++#define REG_SC_BK29_29_H _PK_H_(0x29, 0x29) ++#define REG_SC_BK29_2A_L _PK_L_(0x29, 0x2A) ++#define REG_SC_BK29_2A_H _PK_H_(0x29, 0x2A) ++#define REG_SC_BK29_2B_L _PK_L_(0x29, 0x2B) ++#define REG_SC_BK29_2B_H _PK_H_(0x29, 0x2B) ++#define REG_SC_BK29_2C_L _PK_L_(0x29, 0x2C) ++#define REG_SC_BK29_2C_H _PK_H_(0x29, 0x2C) ++#define REG_SC_BK29_2D_L _PK_L_(0x29, 0x2D) ++#define REG_SC_BK29_2D_H _PK_H_(0x29, 0x2D) ++#define REG_SC_BK29_2E_L _PK_L_(0x29, 0x2E) ++#define REG_SC_BK29_2E_H _PK_H_(0x29, 0x2E) ++#define REG_SC_BK29_2F_L _PK_L_(0x29, 0x2F) ++#define REG_SC_BK29_2F_H _PK_H_(0x29, 0x2F) ++#define REG_SC_BK29_30_L _PK_L_(0x29, 0x30) ++#define REG_SC_BK29_30_H _PK_H_(0x29, 0x30) ++#define REG_SC_BK29_31_L _PK_L_(0x29, 0x31) ++#define REG_SC_BK29_31_H _PK_H_(0x29, 0x31) ++#define REG_SC_BK29_32_L _PK_L_(0x29, 0x32) ++#define REG_SC_BK29_32_H _PK_H_(0x29, 0x32) ++#define REG_SC_BK29_33_L _PK_L_(0x29, 0x33) ++#define REG_SC_BK29_33_H _PK_H_(0x29, 0x33) ++#define REG_SC_BK29_34_L _PK_L_(0x29, 0x34) ++#define REG_SC_BK29_34_H _PK_H_(0x29, 0x34) ++#define REG_SC_BK29_35_L _PK_L_(0x29, 0x35) ++#define REG_SC_BK29_35_H _PK_H_(0x29, 0x35) ++#define REG_SC_BK29_36_L _PK_L_(0x29, 0x36) ++#define REG_SC_BK29_36_H _PK_H_(0x29, 0x36) ++#define REG_SC_BK29_37_L _PK_L_(0x29, 0x37) ++#define REG_SC_BK29_37_H _PK_H_(0x29, 0x37) ++#define REG_SC_BK29_38_L _PK_L_(0x29, 0x38) ++#define REG_SC_BK29_38_H _PK_H_(0x29, 0x38) ++#define REG_SC_BK29_39_L _PK_L_(0x29, 0x39) ++#define REG_SC_BK29_39_H _PK_H_(0x29, 0x39) ++#define REG_SC_BK29_3A_L _PK_L_(0x29, 0x3A) ++#define REG_SC_BK29_3A_H _PK_H_(0x29, 0x3A) ++#define REG_SC_BK29_3B_L _PK_L_(0x29, 0x3B) ++#define REG_SC_BK29_3B_H _PK_H_(0x29, 0x3B) ++#define REG_SC_BK29_3C_L _PK_L_(0x29, 0x3C) ++#define REG_SC_BK29_3C_H _PK_H_(0x29, 0x3C) ++#define REG_SC_BK29_3D_L _PK_L_(0x29, 0x3D) ++#define REG_SC_BK29_3D_H _PK_H_(0x29, 0x3D) ++#define REG_SC_BK29_3E_L _PK_L_(0x29, 0x3E) ++#define REG_SC_BK29_3E_H _PK_H_(0x29, 0x3E) ++#define REG_SC_BK29_3F_L _PK_L_(0x29, 0x3F) ++#define REG_SC_BK29_3F_H _PK_H_(0x29, 0x3F) ++#define REG_SC_BK29_40_L _PK_L_(0x29, 0x40) ++#define REG_SC_BK29_40_H _PK_H_(0x29, 0x40) ++#define REG_SC_BK29_41_L _PK_L_(0x29, 0x41) ++#define REG_SC_BK29_41_H _PK_H_(0x29, 0x41) ++#define REG_SC_BK29_42_L _PK_L_(0x29, 0x42) ++#define REG_SC_BK29_42_H _PK_H_(0x29, 0x42) ++#define REG_SC_BK29_43_L _PK_L_(0x29, 0x43) ++#define REG_SC_BK29_43_H _PK_H_(0x29, 0x43) ++#define REG_SC_BK29_44_L _PK_L_(0x29, 0x44) ++#define REG_SC_BK29_44_H _PK_H_(0x29, 0x44) ++#define REG_SC_BK29_45_L _PK_L_(0x29, 0x45) ++#define REG_SC_BK29_45_H _PK_H_(0x29, 0x45) ++#define REG_SC_BK29_46_L _PK_L_(0x29, 0x46) ++#define REG_SC_BK29_46_H _PK_H_(0x29, 0x46) ++#define REG_SC_BK29_47_L _PK_L_(0x29, 0x47) ++#define REG_SC_BK29_47_H _PK_H_(0x29, 0x47) ++#define REG_SC_BK29_48_L _PK_L_(0x29, 0x48) ++#define REG_SC_BK29_48_H _PK_H_(0x29, 0x48) ++#define REG_SC_BK29_49_L _PK_L_(0x29, 0x49) ++#define REG_SC_BK29_49_H _PK_H_(0x29, 0x49) ++#define REG_SC_BK29_4A_L _PK_L_(0x29, 0x4A) ++#define REG_SC_BK29_4A_H _PK_H_(0x29, 0x4A) ++#define REG_SC_BK29_4B_L _PK_L_(0x29, 0x4B) ++#define REG_SC_BK29_4B_H _PK_H_(0x29, 0x4B) ++#define REG_SC_BK29_4C_L _PK_L_(0x29, 0x4C) ++#define REG_SC_BK29_4C_H _PK_H_(0x29, 0x4C) ++#define REG_SC_BK29_4D_L _PK_L_(0x29, 0x4D) ++#define REG_SC_BK29_4D_H _PK_H_(0x29, 0x4D) ++#define REG_SC_BK29_4E_L _PK_L_(0x29, 0x4E) ++#define REG_SC_BK29_4E_H _PK_H_(0x29, 0x4E) ++#define REG_SC_BK29_4F_L _PK_L_(0x29, 0x4F) ++#define REG_SC_BK29_4F_H _PK_H_(0x29, 0x4F) ++#define REG_SC_BK29_50_L _PK_L_(0x29, 0x50) ++#define REG_SC_BK29_50_H _PK_H_(0x29, 0x50) ++#define REG_SC_BK29_51_L _PK_L_(0x29, 0x51) ++#define REG_SC_BK29_51_H _PK_H_(0x29, 0x51) ++#define REG_SC_BK29_52_L _PK_L_(0x29, 0x52) ++#define REG_SC_BK29_52_H _PK_H_(0x29, 0x52) ++#define REG_SC_BK29_53_L _PK_L_(0x29, 0x53) ++#define REG_SC_BK29_53_H _PK_H_(0x29, 0x53) ++#define REG_SC_BK29_54_L _PK_L_(0x29, 0x54) ++#define REG_SC_BK29_54_H _PK_H_(0x29, 0x54) ++#define REG_SC_BK29_55_L _PK_L_(0x29, 0x55) ++#define REG_SC_BK29_55_H _PK_H_(0x29, 0x55) ++#define REG_SC_BK29_56_L _PK_L_(0x29, 0x56) ++#define REG_SC_BK29_56_H _PK_H_(0x29, 0x56) ++#define REG_SC_BK29_57_L _PK_L_(0x29, 0x57) ++#define REG_SC_BK29_57_H _PK_H_(0x29, 0x57) ++#define REG_SC_BK29_58_L _PK_L_(0x29, 0x58) ++#define REG_SC_BK29_58_H _PK_H_(0x29, 0x58) ++#define REG_SC_BK29_59_L _PK_L_(0x29, 0x59) ++#define REG_SC_BK29_59_H _PK_H_(0x29, 0x59) ++#define REG_SC_BK29_5A_L _PK_L_(0x29, 0x5A) ++#define REG_SC_BK29_5A_H _PK_H_(0x29, 0x5A) ++#define REG_SC_BK29_5B_L _PK_L_(0x29, 0x5B) ++#define REG_SC_BK29_5B_H _PK_H_(0x29, 0x5B) ++#define REG_SC_BK29_5C_L _PK_L_(0x29, 0x5C) ++#define REG_SC_BK29_5C_H _PK_H_(0x29, 0x5C) ++#define REG_SC_BK29_5D_L _PK_L_(0x29, 0x5D) ++#define REG_SC_BK29_5D_H _PK_H_(0x29, 0x5D) ++#define REG_SC_BK29_5E_L _PK_L_(0x29, 0x5E) ++#define REG_SC_BK29_5E_H _PK_H_(0x29, 0x5E) ++#define REG_SC_BK29_5F_L _PK_L_(0x29, 0x5F) ++#define REG_SC_BK29_5F_H _PK_H_(0x29, 0x5F) ++#define REG_SC_BK29_60_L _PK_L_(0x29, 0x60) ++#define REG_SC_BK29_60_H _PK_H_(0x29, 0x60) ++#define REG_SC_BK29_61_L _PK_L_(0x29, 0x61) ++#define REG_SC_BK29_61_H _PK_H_(0x29, 0x61) ++#define REG_SC_BK29_62_L _PK_L_(0x29, 0x62) ++#define REG_SC_BK29_62_H _PK_H_(0x29, 0x62) ++#define REG_SC_BK29_63_L _PK_L_(0x29, 0x63) ++#define REG_SC_BK29_63_H _PK_H_(0x29, 0x63) ++#define REG_SC_BK29_64_L _PK_L_(0x29, 0x64) ++#define REG_SC_BK29_64_H _PK_H_(0x29, 0x64) ++#define REG_SC_BK29_65_L _PK_L_(0x29, 0x65) ++#define REG_SC_BK29_65_H _PK_H_(0x29, 0x65) ++#define REG_SC_BK29_66_L _PK_L_(0x29, 0x66) ++#define REG_SC_BK29_66_H _PK_H_(0x29, 0x66) ++#define REG_SC_BK29_67_L _PK_L_(0x29, 0x67) ++#define REG_SC_BK29_67_H _PK_H_(0x29, 0x67) ++#define REG_SC_BK29_68_L _PK_L_(0x29, 0x68) ++#define REG_SC_BK29_68_H _PK_H_(0x29, 0x68) ++#define REG_SC_BK29_69_L _PK_L_(0x29, 0x69) ++#define REG_SC_BK29_69_H _PK_H_(0x29, 0x69) ++#define REG_SC_BK29_6A_L _PK_L_(0x29, 0x6A) ++#define REG_SC_BK29_6A_H _PK_H_(0x29, 0x6A) ++#define REG_SC_BK29_6B_L _PK_L_(0x29, 0x6B) ++#define REG_SC_BK29_6B_H _PK_H_(0x29, 0x6B) ++#define REG_SC_BK29_6C_L _PK_L_(0x29, 0x6C) ++#define REG_SC_BK29_6C_H _PK_H_(0x29, 0x6C) ++#define REG_SC_BK29_6D_L _PK_L_(0x29, 0x6D) ++#define REG_SC_BK29_6D_H _PK_H_(0x29, 0x6D) ++#define REG_SC_BK29_6E_L _PK_L_(0x29, 0x6E) ++#define REG_SC_BK29_6E_H _PK_H_(0x29, 0x6E) ++#define REG_SC_BK29_6F_L _PK_L_(0x29, 0x6F) ++#define REG_SC_BK29_6F_H _PK_H_(0x29, 0x6F) ++#define REG_SC_BK29_70_L _PK_L_(0x29, 0x70) ++#define REG_SC_BK29_70_H _PK_H_(0x29, 0x70) ++#define REG_SC_BK29_71_L _PK_L_(0x29, 0x71) ++#define REG_SC_BK29_71_H _PK_H_(0x29, 0x71) ++#define REG_SC_BK29_72_L _PK_L_(0x29, 0x72) ++#define REG_SC_BK29_72_H _PK_H_(0x29, 0x72) ++#define REG_SC_BK29_73_L _PK_L_(0x29, 0x73) ++#define REG_SC_BK29_73_H _PK_H_(0x29, 0x73) ++#define REG_SC_BK29_74_L _PK_L_(0x29, 0x74) ++#define REG_SC_BK29_74_H _PK_H_(0x29, 0x74) ++#define REG_SC_BK29_75_L _PK_L_(0x29, 0x75) ++#define REG_SC_BK29_75_H _PK_H_(0x29, 0x75) ++#define REG_SC_BK29_76_L _PK_L_(0x29, 0x76) ++#define REG_SC_BK29_76_H _PK_H_(0x29, 0x76) ++#define REG_SC_BK29_77_L _PK_L_(0x29, 0x77) ++#define REG_SC_BK29_77_H _PK_H_(0x29, 0x77) ++#define REG_SC_BK29_78_L _PK_L_(0x29, 0x78) ++#define REG_SC_BK29_78_H _PK_H_(0x29, 0x78) ++#define REG_SC_BK29_79_L _PK_L_(0x29, 0x79) ++#define REG_SC_BK29_79_H _PK_H_(0x29, 0x79) ++#define REG_SC_BK29_7A_L _PK_L_(0x29, 0x7A) ++#define REG_SC_BK29_7A_H _PK_H_(0x29, 0x7A) ++#define REG_SC_BK29_7B_L _PK_L_(0x29, 0x7B) ++#define REG_SC_BK29_7B_H _PK_H_(0x29, 0x7B) ++#define REG_SC_BK29_7C_L _PK_L_(0x29, 0x7C) ++#define REG_SC_BK29_7C_H _PK_H_(0x29, 0x7C) ++#define REG_SC_BK29_7D_L _PK_L_(0x29, 0x7D) ++#define REG_SC_BK29_7D_H _PK_H_(0x29, 0x7D) ++#define REG_SC_BK29_7E_L _PK_L_(0x29, 0x7E) ++#define REG_SC_BK29_7E_H _PK_H_(0x29, 0x7E) ++#define REG_SC_BK29_7F_L _PK_L_(0x29, 0x7F) ++#define REG_SC_BK29_7F_H _PK_H_(0x29, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK2A_00_L _PK_L_(0x2A, 0x00) ++#define REG_SC_BK2A_00_H _PK_H_(0x2A, 0x00) ++#define REG_SC_BK2A_01_L _PK_L_(0x2A, 0x01) ++#define REG_SC_BK2A_01_H _PK_H_(0x2A, 0x01) ++#define REG_SC_BK2A_02_L _PK_L_(0x2A, 0x02) ++#define REG_SC_BK2A_02_H _PK_H_(0x2A, 0x02) ++#define REG_SC_BK2A_03_L _PK_L_(0x2A, 0x03) ++#define REG_SC_BK2A_03_H _PK_H_(0x2A, 0x03) ++#define REG_SC_BK2A_04_L _PK_L_(0x2A, 0x04) ++#define REG_SC_BK2A_04_H _PK_H_(0x2A, 0x04) ++#define REG_SC_BK2A_05_L _PK_L_(0x2A, 0x05) ++#define REG_SC_BK2A_05_H _PK_H_(0x2A, 0x05) ++#define REG_SC_BK2A_06_L _PK_L_(0x2A, 0x06) ++#define REG_SC_BK2A_06_H _PK_H_(0x2A, 0x06) ++#define REG_SC_BK2A_07_L _PK_L_(0x2A, 0x07) ++#define REG_SC_BK2A_07_H _PK_H_(0x2A, 0x07) ++#define REG_SC_BK2A_08_L _PK_L_(0x2A, 0x08) ++#define REG_SC_BK2A_08_H _PK_H_(0x2A, 0x08) ++#define REG_SC_BK2A_09_L _PK_L_(0x2A, 0x09) ++#define REG_SC_BK2A_09_H _PK_H_(0x2A, 0x09) ++#define REG_SC_BK2A_0A_L _PK_L_(0x2A, 0x0A) ++#define REG_SC_BK2A_0A_H _PK_H_(0x2A, 0x0A) ++#define REG_SC_BK2A_0B_L _PK_L_(0x2A, 0x0B) ++#define REG_SC_BK2A_0B_H _PK_H_(0x2A, 0x0B) ++#define REG_SC_BK2A_0C_L _PK_L_(0x2A, 0x0C) ++#define REG_SC_BK2A_0C_H _PK_H_(0x2A, 0x0C) ++#define REG_SC_BK2A_0D_L _PK_L_(0x2A, 0x0D) ++#define REG_SC_BK2A_0D_H _PK_H_(0x2A, 0x0D) ++#define REG_SC_BK2A_0E_L _PK_L_(0x2A, 0x0E) ++#define REG_SC_BK2A_0E_H _PK_H_(0x2A, 0x0E) ++#define REG_SC_BK2A_0F_L _PK_L_(0x2A, 0x0F) ++#define REG_SC_BK2A_0F_H _PK_H_(0x2A, 0x0F) ++#define REG_SC_BK2A_10_L _PK_L_(0x2A, 0x10) ++#define REG_SC_BK2A_10_H _PK_H_(0x2A, 0x10) ++#define REG_SC_BK2A_11_L _PK_L_(0x2A, 0x11) ++#define REG_SC_BK2A_11_H _PK_H_(0x2A, 0x11) ++#define REG_SC_BK2A_12_L _PK_L_(0x2A, 0x12) ++#define REG_SC_BK2A_12_H _PK_H_(0x2A, 0x12) ++#define REG_SC_BK2A_13_L _PK_L_(0x2A, 0x13) ++#define REG_SC_BK2A_13_H _PK_H_(0x2A, 0x13) ++#define REG_SC_BK2A_14_L _PK_L_(0x2A, 0x14) ++#define REG_SC_BK2A_14_H _PK_H_(0x2A, 0x14) ++#define REG_SC_BK2A_15_L _PK_L_(0x2A, 0x15) ++#define REG_SC_BK2A_15_H _PK_H_(0x2A, 0x15) ++#define REG_SC_BK2A_16_L _PK_L_(0x2A, 0x16) ++#define REG_SC_BK2A_16_H _PK_H_(0x2A, 0x16) ++#define REG_SC_BK2A_17_L _PK_L_(0x2A, 0x17) ++#define REG_SC_BK2A_17_H _PK_H_(0x2A, 0x17) ++#define REG_SC_BK2A_18_L _PK_L_(0x2A, 0x18) ++#define REG_SC_BK2A_18_H _PK_H_(0x2A, 0x18) ++#define REG_SC_BK2A_19_L _PK_L_(0x2A, 0x19) ++#define REG_SC_BK2A_19_H _PK_H_(0x2A, 0x19) ++#define REG_SC_BK2A_1A_L _PK_L_(0x2A, 0x1A) ++#define REG_SC_BK2A_1A_H _PK_H_(0x2A, 0x1A) ++#define REG_SC_BK2A_1B_L _PK_L_(0x2A, 0x1B) ++#define REG_SC_BK2A_1B_H _PK_H_(0x2A, 0x1B) ++#define REG_SC_BK2A_1C_L _PK_L_(0x2A, 0x1C) ++#define REG_SC_BK2A_1C_H _PK_H_(0x2A, 0x1C) ++#define REG_SC_BK2A_1D_L _PK_L_(0x2A, 0x1D) ++#define REG_SC_BK2A_1D_H _PK_H_(0x2A, 0x1D) ++#define REG_SC_BK2A_1E_L _PK_L_(0x2A, 0x1E) ++#define REG_SC_BK2A_1E_H _PK_H_(0x2A, 0x1E) ++#define REG_SC_BK2A_1F_L _PK_L_(0x2A, 0x1F) ++#define REG_SC_BK2A_1F_H _PK_H_(0x2A, 0x1F) ++#define REG_SC_BK2A_20_L _PK_L_(0x2A, 0x20) ++#define REG_SC_BK2A_20_H _PK_H_(0x2A, 0x20) ++#define REG_SC_BK2A_21_L _PK_L_(0x2A, 0x21) ++#define REG_SC_BK2A_21_H _PK_H_(0x2A, 0x21) ++#define REG_SC_BK2A_22_L _PK_L_(0x2A, 0x22) ++#define REG_SC_BK2A_22_H _PK_H_(0x2A, 0x22) ++#define REG_SC_BK2A_23_L _PK_L_(0x2A, 0x23) ++#define REG_SC_BK2A_23_H _PK_H_(0x2A, 0x23) ++#define REG_SC_BK2A_24_L _PK_L_(0x2A, 0x24) ++#define REG_SC_BK2A_24_H _PK_H_(0x2A, 0x24) ++#define REG_SC_BK2A_25_L _PK_L_(0x2A, 0x25) ++#define REG_SC_BK2A_25_H _PK_H_(0x2A, 0x25) ++#define REG_SC_BK2A_26_L _PK_L_(0x2A, 0x26) ++#define REG_SC_BK2A_26_H _PK_H_(0x2A, 0x26) ++#define REG_SC_BK2A_27_L _PK_L_(0x2A, 0x27) ++#define REG_SC_BK2A_27_H _PK_H_(0x2A, 0x27) ++#define REG_SC_BK2A_28_L _PK_L_(0x2A, 0x28) ++#define REG_SC_BK2A_28_H _PK_H_(0x2A, 0x28) ++#define REG_SC_BK2A_29_L _PK_L_(0x2A, 0x29) ++#define REG_SC_BK2A_29_H _PK_H_(0x2A, 0x29) ++#define REG_SC_BK2A_2A_L _PK_L_(0x2A, 0x2A) ++#define REG_SC_BK2A_2A_H _PK_H_(0x2A, 0x2A) ++#define REG_SC_BK2A_2B_L _PK_L_(0x2A, 0x2B) ++#define REG_SC_BK2A_2B_H _PK_H_(0x2A, 0x2B) ++#define REG_SC_BK2A_2C_L _PK_L_(0x2A, 0x2C) ++#define REG_SC_BK2A_2C_H _PK_H_(0x2A, 0x2C) ++#define REG_SC_BK2A_2D_L _PK_L_(0x2A, 0x2D) ++#define REG_SC_BK2A_2D_H _PK_H_(0x2A, 0x2D) ++#define REG_SC_BK2A_2E_L _PK_L_(0x2A, 0x2E) ++#define REG_SC_BK2A_2E_H _PK_H_(0x2A, 0x2E) ++#define REG_SC_BK2A_2F_L _PK_L_(0x2A, 0x2F) ++#define REG_SC_BK2A_2F_H _PK_H_(0x2A, 0x2F) ++#define REG_SC_BK2A_30_L _PK_L_(0x2A, 0x30) ++#define REG_SC_BK2A_30_H _PK_H_(0x2A, 0x30) ++#define REG_SC_BK2A_31_L _PK_L_(0x2A, 0x31) ++#define REG_SC_BK2A_31_H _PK_H_(0x2A, 0x31) ++#define REG_SC_BK2A_32_L _PK_L_(0x2A, 0x32) ++#define REG_SC_BK2A_32_H _PK_H_(0x2A, 0x32) ++#define REG_SC_BK2A_33_L _PK_L_(0x2A, 0x33) ++#define REG_SC_BK2A_33_H _PK_H_(0x2A, 0x33) ++#define REG_SC_BK2A_34_L _PK_L_(0x2A, 0x34) ++#define REG_SC_BK2A_34_H _PK_H_(0x2A, 0x34) ++#define REG_SC_BK2A_35_L _PK_L_(0x2A, 0x35) ++#define REG_SC_BK2A_35_H _PK_H_(0x2A, 0x35) ++#define REG_SC_BK2A_36_L _PK_L_(0x2A, 0x36) ++#define REG_SC_BK2A_36_H _PK_H_(0x2A, 0x36) ++#define REG_SC_BK2A_37_L _PK_L_(0x2A, 0x37) ++#define REG_SC_BK2A_37_H _PK_H_(0x2A, 0x37) ++#define REG_SC_BK2A_38_L _PK_L_(0x2A, 0x38) ++#define REG_SC_BK2A_38_H _PK_H_(0x2A, 0x38) ++#define REG_SC_BK2A_39_L _PK_L_(0x2A, 0x39) ++#define REG_SC_BK2A_39_H _PK_H_(0x2A, 0x39) ++#define REG_SC_BK2A_3A_L _PK_L_(0x2A, 0x3A) ++#define REG_SC_BK2A_3A_H _PK_H_(0x2A, 0x3A) ++#define REG_SC_BK2A_3B_L _PK_L_(0x2A, 0x3B) ++#define REG_SC_BK2A_3B_H _PK_H_(0x2A, 0x3B) ++#define REG_SC_BK2A_3C_L _PK_L_(0x2A, 0x3C) ++#define REG_SC_BK2A_3C_H _PK_H_(0x2A, 0x3C) ++#define REG_SC_BK2A_3D_L _PK_L_(0x2A, 0x3D) ++#define REG_SC_BK2A_3D_H _PK_H_(0x2A, 0x3D) ++#define REG_SC_BK2A_3E_L _PK_L_(0x2A, 0x3E) ++#define REG_SC_BK2A_3E_H _PK_H_(0x2A, 0x3E) ++#define REG_SC_BK2A_3F_L _PK_L_(0x2A, 0x3F) ++#define REG_SC_BK2A_3F_H _PK_H_(0x2A, 0x3F) ++#define REG_SC_BK2A_40_L _PK_L_(0x2A, 0x40) ++#define REG_SC_BK2A_40_H _PK_H_(0x2A, 0x40) ++#define REG_SC_BK2A_41_L _PK_L_(0x2A, 0x41) ++#define REG_SC_BK2A_41_H _PK_H_(0x2A, 0x41) ++#define REG_SC_BK2A_42_L _PK_L_(0x2A, 0x42) ++#define REG_SC_BK2A_42_H _PK_H_(0x2A, 0x42) ++#define REG_SC_BK2A_43_L _PK_L_(0x2A, 0x43) ++#define REG_SC_BK2A_43_H _PK_H_(0x2A, 0x43) ++#define REG_SC_BK2A_44_L _PK_L_(0x2A, 0x44) ++#define REG_SC_BK2A_44_H _PK_H_(0x2A, 0x44) ++#define REG_SC_BK2A_45_L _PK_L_(0x2A, 0x45) ++#define REG_SC_BK2A_45_H _PK_H_(0x2A, 0x45) ++#define REG_SC_BK2A_46_L _PK_L_(0x2A, 0x46) ++#define REG_SC_BK2A_46_H _PK_H_(0x2A, 0x46) ++#define REG_SC_BK2A_47_L _PK_L_(0x2A, 0x47) ++#define REG_SC_BK2A_47_H _PK_H_(0x2A, 0x47) ++#define REG_SC_BK2A_48_L _PK_L_(0x2A, 0x48) ++#define REG_SC_BK2A_48_H _PK_H_(0x2A, 0x48) ++#define REG_SC_BK2A_49_L _PK_L_(0x2A, 0x49) ++#define REG_SC_BK2A_49_H _PK_H_(0x2A, 0x49) ++#define REG_SC_BK2A_4A_L _PK_L_(0x2A, 0x4A) ++#define REG_SC_BK2A_4A_H _PK_H_(0x2A, 0x4A) ++#define REG_SC_BK2A_4B_L _PK_L_(0x2A, 0x4B) ++#define REG_SC_BK2A_4B_H _PK_H_(0x2A, 0x4B) ++#define REG_SC_BK2A_4C_L _PK_L_(0x2A, 0x4C) ++#define REG_SC_BK2A_4C_H _PK_H_(0x2A, 0x4C) ++#define REG_SC_BK2A_4D_L _PK_L_(0x2A, 0x4D) ++#define REG_SC_BK2A_4D_H _PK_H_(0x2A, 0x4D) ++#define REG_SC_BK2A_4E_L _PK_L_(0x2A, 0x4E) ++#define REG_SC_BK2A_4E_H _PK_H_(0x2A, 0x4E) ++#define REG_SC_BK2A_4F_L _PK_L_(0x2A, 0x4F) ++#define REG_SC_BK2A_4F_H _PK_H_(0x2A, 0x4F) ++#define REG_SC_BK2A_50_L _PK_L_(0x2A, 0x50) ++#define REG_SC_BK2A_50_H _PK_H_(0x2A, 0x50) ++#define REG_SC_BK2A_51_L _PK_L_(0x2A, 0x51) ++#define REG_SC_BK2A_51_H _PK_H_(0x2A, 0x51) ++#define REG_SC_BK2A_52_L _PK_L_(0x2A, 0x52) ++#define REG_SC_BK2A_52_H _PK_H_(0x2A, 0x52) ++#define REG_SC_BK2A_53_L _PK_L_(0x2A, 0x53) ++#define REG_SC_BK2A_53_H _PK_H_(0x2A, 0x53) ++#define REG_SC_BK2A_54_L _PK_L_(0x2A, 0x54) ++#define REG_SC_BK2A_54_H _PK_H_(0x2A, 0x54) ++#define REG_SC_BK2A_55_L _PK_L_(0x2A, 0x55) ++#define REG_SC_BK2A_55_H _PK_H_(0x2A, 0x55) ++#define REG_SC_BK2A_56_L _PK_L_(0x2A, 0x56) ++#define REG_SC_BK2A_56_H _PK_H_(0x2A, 0x56) ++#define REG_SC_BK2A_57_L _PK_L_(0x2A, 0x57) ++#define REG_SC_BK2A_57_H _PK_H_(0x2A, 0x57) ++#define REG_SC_BK2A_58_L _PK_L_(0x2A, 0x58) ++#define REG_SC_BK2A_58_H _PK_H_(0x2A, 0x58) ++#define REG_SC_BK2A_59_L _PK_L_(0x2A, 0x59) ++#define REG_SC_BK2A_59_H _PK_H_(0x2A, 0x59) ++#define REG_SC_BK2A_5A_L _PK_L_(0x2A, 0x5A) ++#define REG_SC_BK2A_5A_H _PK_H_(0x2A, 0x5A) ++#define REG_SC_BK2A_5B_L _PK_L_(0x2A, 0x5B) ++#define REG_SC_BK2A_5B_H _PK_H_(0x2A, 0x5B) ++#define REG_SC_BK2A_5C_L _PK_L_(0x2A, 0x5C) ++#define REG_SC_BK2A_5C_H _PK_H_(0x2A, 0x5C) ++#define REG_SC_BK2A_5D_L _PK_L_(0x2A, 0x5D) ++#define REG_SC_BK2A_5D_H _PK_H_(0x2A, 0x5D) ++#define REG_SC_BK2A_5E_L _PK_L_(0x2A, 0x5E) ++#define REG_SC_BK2A_5E_H _PK_H_(0x2A, 0x5E) ++#define REG_SC_BK2A_5F_L _PK_L_(0x2A, 0x5F) ++#define REG_SC_BK2A_5F_H _PK_H_(0x2A, 0x5F) ++#define REG_SC_BK2A_60_L _PK_L_(0x2A, 0x60) ++#define REG_SC_BK2A_60_H _PK_H_(0x2A, 0x60) ++#define REG_SC_BK2A_61_L _PK_L_(0x2A, 0x61) ++#define REG_SC_BK2A_61_H _PK_H_(0x2A, 0x61) ++#define REG_SC_BK2A_62_L _PK_L_(0x2A, 0x62) ++#define REG_SC_BK2A_62_H _PK_H_(0x2A, 0x62) ++#define REG_SC_BK2A_63_L _PK_L_(0x2A, 0x63) ++#define REG_SC_BK2A_63_H _PK_H_(0x2A, 0x63) ++#define REG_SC_BK2A_64_L _PK_L_(0x2A, 0x64) ++#define REG_SC_BK2A_64_H _PK_H_(0x2A, 0x64) ++#define REG_SC_BK2A_65_L _PK_L_(0x2A, 0x65) ++#define REG_SC_BK2A_65_H _PK_H_(0x2A, 0x65) ++#define REG_SC_BK2A_66_L _PK_L_(0x2A, 0x66) ++#define REG_SC_BK2A_66_H _PK_H_(0x2A, 0x66) ++#define REG_SC_BK2A_67_L _PK_L_(0x2A, 0x67) ++#define REG_SC_BK2A_67_H _PK_H_(0x2A, 0x67) ++#define REG_SC_BK2A_68_L _PK_L_(0x2A, 0x68) ++#define REG_SC_BK2A_68_H _PK_H_(0x2A, 0x68) ++#define REG_SC_BK2A_69_L _PK_L_(0x2A, 0x69) ++#define REG_SC_BK2A_69_H _PK_H_(0x2A, 0x69) ++#define REG_SC_BK2A_6A_L _PK_L_(0x2A, 0x6A) ++#define REG_SC_BK2A_6A_H _PK_H_(0x2A, 0x6A) ++#define REG_SC_BK2A_6B_L _PK_L_(0x2A, 0x6B) ++#define REG_SC_BK2A_6B_H _PK_H_(0x2A, 0x6B) ++#define REG_SC_BK2A_6C_L _PK_L_(0x2A, 0x6C) ++#define REG_SC_BK2A_6C_H _PK_H_(0x2A, 0x6C) ++#define REG_SC_BK2A_6D_L _PK_L_(0x2A, 0x6D) ++#define REG_SC_BK2A_6D_H _PK_H_(0x2A, 0x6D) ++#define REG_SC_BK2A_6E_L _PK_L_(0x2A, 0x6E) ++#define REG_SC_BK2A_6E_H _PK_H_(0x2A, 0x6E) ++#define REG_SC_BK2A_6F_L _PK_L_(0x2A, 0x6F) ++#define REG_SC_BK2A_6F_H _PK_H_(0x2A, 0x6F) ++#define REG_SC_BK2A_70_L _PK_L_(0x2A, 0x70) ++#define REG_SC_BK2A_70_H _PK_H_(0x2A, 0x70) ++#define REG_SC_BK2A_71_L _PK_L_(0x2A, 0x71) ++#define REG_SC_BK2A_71_H _PK_H_(0x2A, 0x71) ++#define REG_SC_BK2A_72_L _PK_L_(0x2A, 0x72) ++#define REG_SC_BK2A_72_H _PK_H_(0x2A, 0x72) ++#define REG_SC_BK2A_73_L _PK_L_(0x2A, 0x73) ++#define REG_SC_BK2A_73_H _PK_H_(0x2A, 0x73) ++#define REG_SC_BK2A_74_L _PK_L_(0x2A, 0x74) ++#define REG_SC_BK2A_74_H _PK_H_(0x2A, 0x74) ++#define REG_SC_BK2A_75_L _PK_L_(0x2A, 0x75) ++#define REG_SC_BK2A_75_H _PK_H_(0x2A, 0x75) ++#define REG_SC_BK2A_76_L _PK_L_(0x2A, 0x76) ++#define REG_SC_BK2A_76_H _PK_H_(0x2A, 0x76) ++#define REG_SC_BK2A_77_L _PK_L_(0x2A, 0x77) ++#define REG_SC_BK2A_77_H _PK_H_(0x2A, 0x77) ++#define REG_SC_BK2A_78_L _PK_L_(0x2A, 0x78) ++#define REG_SC_BK2A_78_H _PK_H_(0x2A, 0x78) ++#define REG_SC_BK2A_79_L _PK_L_(0x2A, 0x79) ++#define REG_SC_BK2A_79_H _PK_H_(0x2A, 0x79) ++#define REG_SC_BK2A_7A_L _PK_L_(0x2A, 0x7A) ++#define REG_SC_BK2A_7A_H _PK_H_(0x2A, 0x7A) ++#define REG_SC_BK2A_7B_L _PK_L_(0x2A, 0x7B) ++#define REG_SC_BK2A_7B_H _PK_H_(0x2A, 0x7B) ++#define REG_SC_BK2A_7C_L _PK_L_(0x2A, 0x7C) ++#define REG_SC_BK2A_7C_H _PK_H_(0x2A, 0x7C) ++#define REG_SC_BK2A_7D_L _PK_L_(0x2A, 0x7D) ++#define REG_SC_BK2A_7D_H _PK_H_(0x2A, 0x7D) ++#define REG_SC_BK2A_7E_L _PK_L_(0x2A, 0x7E) ++#define REG_SC_BK2A_7E_H _PK_H_(0x2A, 0x7E) ++#define REG_SC_BK2A_7F_L _PK_L_(0x2A, 0x7F) ++#define REG_SC_BK2A_7F_H _PK_H_(0x2A, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK2B_00_L _PK_L_(0x2B, 0x00) ++#define REG_SC_BK2B_00_H _PK_H_(0x2B, 0x00) ++#define REG_SC_BK2B_01_L _PK_L_(0x2B, 0x01) ++#define REG_SC_BK2B_01_H _PK_H_(0x2B, 0x01) ++#define REG_SC_BK2B_02_L _PK_L_(0x2B, 0x02) ++#define REG_SC_BK2B_02_H _PK_H_(0x2B, 0x02) ++#define REG_SC_BK2B_03_L _PK_L_(0x2B, 0x03) ++#define REG_SC_BK2B_03_H _PK_H_(0x2B, 0x03) ++#define REG_SC_BK2B_04_L _PK_L_(0x2B, 0x04) ++#define REG_SC_BK2B_04_H _PK_H_(0x2B, 0x04) ++#define REG_SC_BK2B_05_L _PK_L_(0x2B, 0x05) ++#define REG_SC_BK2B_05_H _PK_H_(0x2B, 0x05) ++#define REG_SC_BK2B_06_L _PK_L_(0x2B, 0x06) ++#define REG_SC_BK2B_06_H _PK_H_(0x2B, 0x06) ++#define REG_SC_BK2B_07_L _PK_L_(0x2B, 0x07) ++#define REG_SC_BK2B_07_H _PK_H_(0x2B, 0x07) ++#define REG_SC_BK2B_08_L _PK_L_(0x2B, 0x08) ++#define REG_SC_BK2B_08_H _PK_H_(0x2B, 0x08) ++#define REG_SC_BK2B_09_L _PK_L_(0x2B, 0x09) ++#define REG_SC_BK2B_09_H _PK_H_(0x2B, 0x09) ++#define REG_SC_BK2B_0A_L _PK_L_(0x2B, 0x0A) ++#define REG_SC_BK2B_0A_H _PK_H_(0x2B, 0x0A) ++#define REG_SC_BK2B_0B_L _PK_L_(0x2B, 0x0B) ++#define REG_SC_BK2B_0B_H _PK_H_(0x2B, 0x0B) ++#define REG_SC_BK2B_0C_L _PK_L_(0x2B, 0x0C) ++#define REG_SC_BK2B_0C_H _PK_H_(0x2B, 0x0C) ++#define REG_SC_BK2B_0D_L _PK_L_(0x2B, 0x0D) ++#define REG_SC_BK2B_0D_H _PK_H_(0x2B, 0x0D) ++#define REG_SC_BK2B_0E_L _PK_L_(0x2B, 0x0E) ++#define REG_SC_BK2B_0E_H _PK_H_(0x2B, 0x0E) ++#define REG_SC_BK2B_0F_L _PK_L_(0x2B, 0x0F) ++#define REG_SC_BK2B_0F_H _PK_H_(0x2B, 0x0F) ++#define REG_SC_BK2B_10_L _PK_L_(0x2B, 0x10) ++#define REG_SC_BK2B_10_H _PK_H_(0x2B, 0x10) ++#define REG_SC_BK2B_11_L _PK_L_(0x2B, 0x11) ++#define REG_SC_BK2B_11_H _PK_H_(0x2B, 0x11) ++#define REG_SC_BK2B_12_L _PK_L_(0x2B, 0x12) ++#define REG_SC_BK2B_12_H _PK_H_(0x2B, 0x12) ++#define REG_SC_BK2B_13_L _PK_L_(0x2B, 0x13) ++#define REG_SC_BK2B_13_H _PK_H_(0x2B, 0x13) ++#define REG_SC_BK2B_14_L _PK_L_(0x2B, 0x14) ++#define REG_SC_BK2B_14_H _PK_H_(0x2B, 0x14) ++#define REG_SC_BK2B_15_L _PK_L_(0x2B, 0x15) ++#define REG_SC_BK2B_15_H _PK_H_(0x2B, 0x15) ++#define REG_SC_BK2B_16_L _PK_L_(0x2B, 0x16) ++#define REG_SC_BK2B_16_H _PK_H_(0x2B, 0x16) ++#define REG_SC_BK2B_17_L _PK_L_(0x2B, 0x17) ++#define REG_SC_BK2B_17_H _PK_H_(0x2B, 0x17) ++#define REG_SC_BK2B_18_L _PK_L_(0x2B, 0x18) ++#define REG_SC_BK2B_18_H _PK_H_(0x2B, 0x18) ++#define REG_SC_BK2B_19_L _PK_L_(0x2B, 0x19) ++#define REG_SC_BK2B_19_H _PK_H_(0x2B, 0x19) ++#define REG_SC_BK2B_1A_L _PK_L_(0x2B, 0x1A) ++#define REG_SC_BK2B_1A_H _PK_H_(0x2B, 0x1A) ++#define REG_SC_BK2B_1B_L _PK_L_(0x2B, 0x1B) ++#define REG_SC_BK2B_1B_H _PK_H_(0x2B, 0x1B) ++#define REG_SC_BK2B_1C_L _PK_L_(0x2B, 0x1C) ++#define REG_SC_BK2B_1C_H _PK_H_(0x2B, 0x1C) ++#define REG_SC_BK2B_1D_L _PK_L_(0x2B, 0x1D) ++#define REG_SC_BK2B_1D_H _PK_H_(0x2B, 0x1D) ++#define REG_SC_BK2B_1E_L _PK_L_(0x2B, 0x1E) ++#define REG_SC_BK2B_1E_H _PK_H_(0x2B, 0x1E) ++#define REG_SC_BK2B_1F_L _PK_L_(0x2B, 0x1F) ++#define REG_SC_BK2B_1F_H _PK_H_(0x2B, 0x1F) ++#define REG_SC_BK2B_20_L _PK_L_(0x2B, 0x20) ++#define REG_SC_BK2B_20_H _PK_H_(0x2B, 0x20) ++#define REG_SC_BK2B_21_L _PK_L_(0x2B, 0x21) ++#define REG_SC_BK2B_21_H _PK_H_(0x2B, 0x21) ++#define REG_SC_BK2B_22_L _PK_L_(0x2B, 0x22) ++#define REG_SC_BK2B_22_H _PK_H_(0x2B, 0x22) ++#define REG_SC_BK2B_23_L _PK_L_(0x2B, 0x23) ++#define REG_SC_BK2B_23_H _PK_H_(0x2B, 0x23) ++#define REG_SC_BK2B_24_L _PK_L_(0x2B, 0x24) ++#define REG_SC_BK2B_24_H _PK_H_(0x2B, 0x24) ++#define REG_SC_BK2B_25_L _PK_L_(0x2B, 0x25) ++#define REG_SC_BK2B_25_H _PK_H_(0x2B, 0x25) ++#define REG_SC_BK2B_26_L _PK_L_(0x2B, 0x26) ++#define REG_SC_BK2B_26_H _PK_H_(0x2B, 0x26) ++#define REG_SC_BK2B_27_L _PK_L_(0x2B, 0x27) ++#define REG_SC_BK2B_27_H _PK_H_(0x2B, 0x27) ++#define REG_SC_BK2B_28_L _PK_L_(0x2B, 0x28) ++#define REG_SC_BK2B_28_H _PK_H_(0x2B, 0x28) ++#define REG_SC_BK2B_29_L _PK_L_(0x2B, 0x29) ++#define REG_SC_BK2B_29_H _PK_H_(0x2B, 0x29) ++#define REG_SC_BK2B_2A_L _PK_L_(0x2B, 0x2A) ++#define REG_SC_BK2B_2A_H _PK_H_(0x2B, 0x2A) ++#define REG_SC_BK2B_2B_L _PK_L_(0x2B, 0x2B) ++#define REG_SC_BK2B_2B_H _PK_H_(0x2B, 0x2B) ++#define REG_SC_BK2B_2C_L _PK_L_(0x2B, 0x2C) ++#define REG_SC_BK2B_2C_H _PK_H_(0x2B, 0x2C) ++#define REG_SC_BK2B_2D_L _PK_L_(0x2B, 0x2D) ++#define REG_SC_BK2B_2D_H _PK_H_(0x2B, 0x2D) ++#define REG_SC_BK2B_2E_L _PK_L_(0x2B, 0x2E) ++#define REG_SC_BK2B_2E_H _PK_H_(0x2B, 0x2E) ++#define REG_SC_BK2B_2F_L _PK_L_(0x2B, 0x2F) ++#define REG_SC_BK2B_2F_H _PK_H_(0x2B, 0x2F) ++#define REG_SC_BK2B_30_L _PK_L_(0x2B, 0x30) ++#define REG_SC_BK2B_30_H _PK_H_(0x2B, 0x30) ++#define REG_SC_BK2B_31_L _PK_L_(0x2B, 0x31) ++#define REG_SC_BK2B_31_H _PK_H_(0x2B, 0x31) ++#define REG_SC_BK2B_32_L _PK_L_(0x2B, 0x32) ++#define REG_SC_BK2B_32_H _PK_H_(0x2B, 0x32) ++#define REG_SC_BK2B_33_L _PK_L_(0x2B, 0x33) ++#define REG_SC_BK2B_33_H _PK_H_(0x2B, 0x33) ++#define REG_SC_BK2B_34_L _PK_L_(0x2B, 0x34) ++#define REG_SC_BK2B_34_H _PK_H_(0x2B, 0x34) ++#define REG_SC_BK2B_35_L _PK_L_(0x2B, 0x35) ++#define REG_SC_BK2B_35_H _PK_H_(0x2B, 0x35) ++#define REG_SC_BK2B_36_L _PK_L_(0x2B, 0x36) ++#define REG_SC_BK2B_36_H _PK_H_(0x2B, 0x36) ++#define REG_SC_BK2B_37_L _PK_L_(0x2B, 0x37) ++#define REG_SC_BK2B_37_H _PK_H_(0x2B, 0x37) ++#define REG_SC_BK2B_38_L _PK_L_(0x2B, 0x38) ++#define REG_SC_BK2B_38_H _PK_H_(0x2B, 0x38) ++#define REG_SC_BK2B_39_L _PK_L_(0x2B, 0x39) ++#define REG_SC_BK2B_39_H _PK_H_(0x2B, 0x39) ++#define REG_SC_BK2B_3A_L _PK_L_(0x2B, 0x3A) ++#define REG_SC_BK2B_3A_H _PK_H_(0x2B, 0x3A) ++#define REG_SC_BK2B_3B_L _PK_L_(0x2B, 0x3B) ++#define REG_SC_BK2B_3B_H _PK_H_(0x2B, 0x3B) ++#define REG_SC_BK2B_3C_L _PK_L_(0x2B, 0x3C) ++#define REG_SC_BK2B_3C_H _PK_H_(0x2B, 0x3C) ++#define REG_SC_BK2B_3D_L _PK_L_(0x2B, 0x3D) ++#define REG_SC_BK2B_3D_H _PK_H_(0x2B, 0x3D) ++#define REG_SC_BK2B_3E_L _PK_L_(0x2B, 0x3E) ++#define REG_SC_BK2B_3E_H _PK_H_(0x2B, 0x3E) ++#define REG_SC_BK2B_3F_L _PK_L_(0x2B, 0x3F) ++#define REG_SC_BK2B_3F_H _PK_H_(0x2B, 0x3F) ++#define REG_SC_BK2B_40_L _PK_L_(0x2B, 0x40) ++#define REG_SC_BK2B_40_H _PK_H_(0x2B, 0x40) ++#define REG_SC_BK2B_41_L _PK_L_(0x2B, 0x41) ++#define REG_SC_BK2B_41_H _PK_H_(0x2B, 0x41) ++#define REG_SC_BK2B_42_L _PK_L_(0x2B, 0x42) ++#define REG_SC_BK2B_42_H _PK_H_(0x2B, 0x42) ++#define REG_SC_BK2B_43_L _PK_L_(0x2B, 0x43) ++#define REG_SC_BK2B_43_H _PK_H_(0x2B, 0x43) ++#define REG_SC_BK2B_44_L _PK_L_(0x2B, 0x44) ++#define REG_SC_BK2B_44_H _PK_H_(0x2B, 0x44) ++#define REG_SC_BK2B_45_L _PK_L_(0x2B, 0x45) ++#define REG_SC_BK2B_45_H _PK_H_(0x2B, 0x45) ++#define REG_SC_BK2B_46_L _PK_L_(0x2B, 0x46) ++#define REG_SC_BK2B_46_H _PK_H_(0x2B, 0x46) ++#define REG_SC_BK2B_47_L _PK_L_(0x2B, 0x47) ++#define REG_SC_BK2B_47_H _PK_H_(0x2B, 0x47) ++#define REG_SC_BK2B_48_L _PK_L_(0x2B, 0x48) ++#define REG_SC_BK2B_48_H _PK_H_(0x2B, 0x48) ++#define REG_SC_BK2B_49_L _PK_L_(0x2B, 0x49) ++#define REG_SC_BK2B_49_H _PK_H_(0x2B, 0x49) ++#define REG_SC_BK2B_4A_L _PK_L_(0x2B, 0x4A) ++#define REG_SC_BK2B_4A_H _PK_H_(0x2B, 0x4A) ++#define REG_SC_BK2B_4B_L _PK_L_(0x2B, 0x4B) ++#define REG_SC_BK2B_4B_H _PK_H_(0x2B, 0x4B) ++#define REG_SC_BK2B_4C_L _PK_L_(0x2B, 0x4C) ++#define REG_SC_BK2B_4C_H _PK_H_(0x2B, 0x4C) ++#define REG_SC_BK2B_4D_L _PK_L_(0x2B, 0x4D) ++#define REG_SC_BK2B_4D_H _PK_H_(0x2B, 0x4D) ++#define REG_SC_BK2B_4E_L _PK_L_(0x2B, 0x4E) ++#define REG_SC_BK2B_4E_H _PK_H_(0x2B, 0x4E) ++#define REG_SC_BK2B_4F_L _PK_L_(0x2B, 0x4F) ++#define REG_SC_BK2B_4F_H _PK_H_(0x2B, 0x4F) ++#define REG_SC_BK2B_50_L _PK_L_(0x2B, 0x50) ++#define REG_SC_BK2B_50_H _PK_H_(0x2B, 0x50) ++#define REG_SC_BK2B_51_L _PK_L_(0x2B, 0x51) ++#define REG_SC_BK2B_51_H _PK_H_(0x2B, 0x51) ++#define REG_SC_BK2B_52_L _PK_L_(0x2B, 0x52) ++#define REG_SC_BK2B_52_H _PK_H_(0x2B, 0x52) ++#define REG_SC_BK2B_53_L _PK_L_(0x2B, 0x53) ++#define REG_SC_BK2B_53_H _PK_H_(0x2B, 0x53) ++#define REG_SC_BK2B_54_L _PK_L_(0x2B, 0x54) ++#define REG_SC_BK2B_54_H _PK_H_(0x2B, 0x54) ++#define REG_SC_BK2B_55_L _PK_L_(0x2B, 0x55) ++#define REG_SC_BK2B_55_H _PK_H_(0x2B, 0x55) ++#define REG_SC_BK2B_56_L _PK_L_(0x2B, 0x56) ++#define REG_SC_BK2B_56_H _PK_H_(0x2B, 0x56) ++#define REG_SC_BK2B_57_L _PK_L_(0x2B, 0x57) ++#define REG_SC_BK2B_57_H _PK_H_(0x2B, 0x57) ++#define REG_SC_BK2B_58_L _PK_L_(0x2B, 0x58) ++#define REG_SC_BK2B_58_H _PK_H_(0x2B, 0x58) ++#define REG_SC_BK2B_59_L _PK_L_(0x2B, 0x59) ++#define REG_SC_BK2B_59_H _PK_H_(0x2B, 0x59) ++#define REG_SC_BK2B_5A_L _PK_L_(0x2B, 0x5A) ++#define REG_SC_BK2B_5A_H _PK_H_(0x2B, 0x5A) ++#define REG_SC_BK2B_5B_L _PK_L_(0x2B, 0x5B) ++#define REG_SC_BK2B_5B_H _PK_H_(0x2B, 0x5B) ++#define REG_SC_BK2B_5C_L _PK_L_(0x2B, 0x5C) ++#define REG_SC_BK2B_5C_H _PK_H_(0x2B, 0x5C) ++#define REG_SC_BK2B_5D_L _PK_L_(0x2B, 0x5D) ++#define REG_SC_BK2B_5D_H _PK_H_(0x2B, 0x5D) ++#define REG_SC_BK2B_5E_L _PK_L_(0x2B, 0x5E) ++#define REG_SC_BK2B_5E_H _PK_H_(0x2B, 0x5E) ++#define REG_SC_BK2B_5F_L _PK_L_(0x2B, 0x5F) ++#define REG_SC_BK2B_5F_H _PK_H_(0x2B, 0x5F) ++#define REG_SC_BK2B_60_L _PK_L_(0x2B, 0x60) ++#define REG_SC_BK2B_60_H _PK_H_(0x2B, 0x60) ++#define REG_SC_BK2B_61_L _PK_L_(0x2B, 0x61) ++#define REG_SC_BK2B_61_H _PK_H_(0x2B, 0x61) ++#define REG_SC_BK2B_62_L _PK_L_(0x2B, 0x62) ++#define REG_SC_BK2B_62_H _PK_H_(0x2B, 0x62) ++#define REG_SC_BK2B_63_L _PK_L_(0x2B, 0x63) ++#define REG_SC_BK2B_63_H _PK_H_(0x2B, 0x63) ++#define REG_SC_BK2B_64_L _PK_L_(0x2B, 0x64) ++#define REG_SC_BK2B_64_H _PK_H_(0x2B, 0x64) ++#define REG_SC_BK2B_65_L _PK_L_(0x2B, 0x65) ++#define REG_SC_BK2B_65_H _PK_H_(0x2B, 0x65) ++#define REG_SC_BK2B_66_L _PK_L_(0x2B, 0x66) ++#define REG_SC_BK2B_66_H _PK_H_(0x2B, 0x66) ++#define REG_SC_BK2B_67_L _PK_L_(0x2B, 0x67) ++#define REG_SC_BK2B_67_H _PK_H_(0x2B, 0x67) ++#define REG_SC_BK2B_68_L _PK_L_(0x2B, 0x68) ++#define REG_SC_BK2B_68_H _PK_H_(0x2B, 0x68) ++#define REG_SC_BK2B_69_L _PK_L_(0x2B, 0x69) ++#define REG_SC_BK2B_69_H _PK_H_(0x2B, 0x69) ++#define REG_SC_BK2B_6A_L _PK_L_(0x2B, 0x6A) ++#define REG_SC_BK2B_6A_H _PK_H_(0x2B, 0x6A) ++#define REG_SC_BK2B_6B_L _PK_L_(0x2B, 0x6B) ++#define REG_SC_BK2B_6B_H _PK_H_(0x2B, 0x6B) ++#define REG_SC_BK2B_6C_L _PK_L_(0x2B, 0x6C) ++#define REG_SC_BK2B_6C_H _PK_H_(0x2B, 0x6C) ++#define REG_SC_BK2B_6D_L _PK_L_(0x2B, 0x6D) ++#define REG_SC_BK2B_6D_H _PK_H_(0x2B, 0x6D) ++#define REG_SC_BK2B_6E_L _PK_L_(0x2B, 0x6E) ++#define REG_SC_BK2B_6E_H _PK_H_(0x2B, 0x6E) ++#define REG_SC_BK2B_6F_L _PK_L_(0x2B, 0x6F) ++#define REG_SC_BK2B_6F_H _PK_H_(0x2B, 0x6F) ++#define REG_SC_BK2B_70_L _PK_L_(0x2B, 0x70) ++#define REG_SC_BK2B_70_H _PK_H_(0x2B, 0x70) ++#define REG_SC_BK2B_71_L _PK_L_(0x2B, 0x71) ++#define REG_SC_BK2B_71_H _PK_H_(0x2B, 0x71) ++#define REG_SC_BK2B_72_L _PK_L_(0x2B, 0x72) ++#define REG_SC_BK2B_72_H _PK_H_(0x2B, 0x72) ++#define REG_SC_BK2B_73_L _PK_L_(0x2B, 0x73) ++#define REG_SC_BK2B_73_H _PK_H_(0x2B, 0x73) ++#define REG_SC_BK2B_74_L _PK_L_(0x2B, 0x74) ++#define REG_SC_BK2B_74_H _PK_H_(0x2B, 0x74) ++#define REG_SC_BK2B_75_L _PK_L_(0x2B, 0x75) ++#define REG_SC_BK2B_75_H _PK_H_(0x2B, 0x75) ++#define REG_SC_BK2B_76_L _PK_L_(0x2B, 0x76) ++#define REG_SC_BK2B_76_H _PK_H_(0x2B, 0x76) ++#define REG_SC_BK2B_77_L _PK_L_(0x2B, 0x77) ++#define REG_SC_BK2B_77_H _PK_H_(0x2B, 0x77) ++#define REG_SC_BK2B_78_L _PK_L_(0x2B, 0x78) ++#define REG_SC_BK2B_78_H _PK_H_(0x2B, 0x78) ++#define REG_SC_BK2B_79_L _PK_L_(0x2B, 0x79) ++#define REG_SC_BK2B_79_H _PK_H_(0x2B, 0x79) ++#define REG_SC_BK2B_7A_L _PK_L_(0x2B, 0x7A) ++#define REG_SC_BK2B_7A_H _PK_H_(0x2B, 0x7A) ++#define REG_SC_BK2B_7B_L _PK_L_(0x2B, 0x7B) ++#define REG_SC_BK2B_7B_H _PK_H_(0x2B, 0x7B) ++#define REG_SC_BK2B_7C_L _PK_L_(0x2B, 0x7C) ++#define REG_SC_BK2B_7C_H _PK_H_(0x2B, 0x7C) ++#define REG_SC_BK2B_7D_L _PK_L_(0x2B, 0x7D) ++#define REG_SC_BK2B_7D_H _PK_H_(0x2B, 0x7D) ++#define REG_SC_BK2B_7E_L _PK_L_(0x2B, 0x7E) ++#define REG_SC_BK2B_7E_H _PK_H_(0x2B, 0x7E) ++#define REG_SC_BK2B_7F_L _PK_L_(0x2B, 0x7F) ++#define REG_SC_BK2B_7F_H _PK_H_(0x2B, 0x7F) ++//---------------------------------------------- ++#define REG_SC_BK2C_00_L _PK_L_(0x2C, 0x00) ++#define REG_SC_BK2C_00_H _PK_H_(0x2C, 0x00) ++#define REG_SC_BK2C_01_L _PK_L_(0x2C, 0x01) ++#define REG_SC_BK2C_01_H _PK_H_(0x2C, 0x01) ++#define REG_SC_BK2C_02_L _PK_L_(0x2C, 0x02) ++#define REG_SC_BK2C_02_H _PK_H_(0x2C, 0x02) ++#define REG_SC_BK2C_03_L _PK_L_(0x2C, 0x03) ++#define REG_SC_BK2C_03_H _PK_H_(0x2C, 0x03) ++#define REG_SC_BK2C_04_L _PK_L_(0x2C, 0x04) ++#define REG_SC_BK2C_04_H _PK_H_(0x2C, 0x04) ++#define REG_SC_BK2C_05_L _PK_L_(0x2C, 0x05) ++#define REG_SC_BK2C_05_H _PK_H_(0x2C, 0x05) ++#define REG_SC_BK2C_06_L _PK_L_(0x2C, 0x06) ++#define REG_SC_BK2C_06_H _PK_H_(0x2C, 0x06) ++#define REG_SC_BK2C_07_L _PK_L_(0x2C, 0x07) ++#define REG_SC_BK2C_07_H _PK_H_(0x2C, 0x07) ++#define REG_SC_BK2C_08_L _PK_L_(0x2C, 0x08) ++#define REG_SC_BK2C_08_H _PK_H_(0x2C, 0x08) ++#define REG_SC_BK2C_09_L _PK_L_(0x2C, 0x09) ++#define REG_SC_BK2C_09_H _PK_H_(0x2C, 0x09) ++#define REG_SC_BK2C_0A_L _PK_L_(0x2C, 0x0A) ++#define REG_SC_BK2C_0A_H _PK_H_(0x2C, 0x0A) ++#define REG_SC_BK2C_0B_L _PK_L_(0x2C, 0x0B) ++#define REG_SC_BK2C_0B_H _PK_H_(0x2C, 0x0B) ++#define REG_SC_BK2C_0C_L _PK_L_(0x2C, 0x0C) ++#define REG_SC_BK2C_0C_H _PK_H_(0x2C, 0x0C) ++#define REG_SC_BK2C_0D_L _PK_L_(0x2C, 0x0D) ++#define REG_SC_BK2C_0D_H _PK_H_(0x2C, 0x0D) ++#define REG_SC_BK2C_0E_L _PK_L_(0x2C, 0x0E) ++#define REG_SC_BK2C_0E_H _PK_H_(0x2C, 0x0E) ++#define REG_SC_BK2C_0F_L _PK_L_(0x2C, 0x0F) ++#define REG_SC_BK2C_0F_H _PK_H_(0x2C, 0x0F) ++#define REG_SC_BK2C_10_L _PK_L_(0x2C, 0x10) ++#define REG_SC_BK2C_10_H _PK_H_(0x2C, 0x10) ++#define REG_SC_BK2C_11_L _PK_L_(0x2C, 0x11) ++#define REG_SC_BK2C_11_H _PK_H_(0x2C, 0x11) ++#define REG_SC_BK2C_12_L _PK_L_(0x2C, 0x12) ++#define REG_SC_BK2C_12_H _PK_H_(0x2C, 0x12) ++#define REG_SC_BK2C_13_L _PK_L_(0x2C, 0x13) ++#define REG_SC_BK2C_13_H _PK_H_(0x2C, 0x13) ++#define REG_SC_BK2C_14_L _PK_L_(0x2C, 0x14) ++#define REG_SC_BK2C_14_H _PK_H_(0x2C, 0x14) ++#define REG_SC_BK2C_15_L _PK_L_(0x2C, 0x15) ++#define REG_SC_BK2C_15_H _PK_H_(0x2C, 0x15) ++#define REG_SC_BK2C_16_L _PK_L_(0x2C, 0x16) ++#define REG_SC_BK2C_16_H _PK_H_(0x2C, 0x16) ++#define REG_SC_BK2C_17_L _PK_L_(0x2C, 0x17) ++#define REG_SC_BK2C_17_H _PK_H_(0x2C, 0x17) ++#define REG_SC_BK2C_18_L _PK_L_(0x2C, 0x18) ++#define REG_SC_BK2C_18_H _PK_H_(0x2C, 0x18) ++#define REG_SC_BK2C_19_L _PK_L_(0x2C, 0x19) ++#define REG_SC_BK2C_19_H _PK_H_(0x2C, 0x19) ++#define REG_SC_BK2C_1A_L _PK_L_(0x2C, 0x1A) ++#define REG_SC_BK2C_1A_H _PK_H_(0x2C, 0x1A) ++#define REG_SC_BK2C_1B_L _PK_L_(0x2C, 0x1B) ++#define REG_SC_BK2C_1B_H _PK_H_(0x2C, 0x1B) ++#define REG_SC_BK2C_1C_L _PK_L_(0x2C, 0x1C) ++#define REG_SC_BK2C_1C_H _PK_H_(0x2C, 0x1C) ++#define REG_SC_BK2C_1D_L _PK_L_(0x2C, 0x1D) ++#define REG_SC_BK2C_1D_H _PK_H_(0x2C, 0x1D) ++#define REG_SC_BK2C_1E_L _PK_L_(0x2C, 0x1E) ++#define REG_SC_BK2C_1E_H _PK_H_(0x2C, 0x1E) ++#define REG_SC_BK2C_1F_L _PK_L_(0x2C, 0x1F) ++#define REG_SC_BK2C_1F_H _PK_H_(0x2C, 0x1F) ++#define REG_SC_BK2C_20_L _PK_L_(0x2C, 0x20) ++#define REG_SC_BK2C_20_H _PK_H_(0x2C, 0x20) ++#define REG_SC_BK2C_21_L _PK_L_(0x2C, 0x21) ++#define REG_SC_BK2C_21_H _PK_H_(0x2C, 0x21) ++#define REG_SC_BK2C_22_L _PK_L_(0x2C, 0x22) ++#define REG_SC_BK2C_22_H _PK_H_(0x2C, 0x22) ++#define REG_SC_BK2C_23_L _PK_L_(0x2C, 0x23) ++#define REG_SC_BK2C_23_H _PK_H_(0x2C, 0x23) ++#define REG_SC_BK2C_24_L _PK_L_(0x2C, 0x24) ++#define REG_SC_BK2C_24_H _PK_H_(0x2C, 0x24) ++#define REG_SC_BK2C_25_L _PK_L_(0x2C, 0x25) ++#define REG_SC_BK2C_25_H _PK_H_(0x2C, 0x25) ++#define REG_SC_BK2C_26_L _PK_L_(0x2C, 0x26) ++#define REG_SC_BK2C_26_H _PK_H_(0x2C, 0x26) ++#define REG_SC_BK2C_27_L _PK_L_(0x2C, 0x27) ++#define REG_SC_BK2C_27_H _PK_H_(0x2C, 0x27) ++#define REG_SC_BK2C_28_L _PK_L_(0x2C, 0x28) ++#define REG_SC_BK2C_28_H _PK_H_(0x2C, 0x28) ++#define REG_SC_BK2C_29_L _PK_L_(0x2C, 0x29) ++#define REG_SC_BK2C_29_H _PK_H_(0x2C, 0x29) ++#define REG_SC_BK2C_2A_L _PK_L_(0x2C, 0x2A) ++#define REG_SC_BK2C_2A_H _PK_H_(0x2C, 0x2A) ++#define REG_SC_BK2C_2B_L _PK_L_(0x2C, 0x2B) ++#define REG_SC_BK2C_2B_H _PK_H_(0x2C, 0x2B) ++#define REG_SC_BK2C_2C_L _PK_L_(0x2C, 0x2C) ++#define REG_SC_BK2C_2C_H _PK_H_(0x2C, 0x2C) ++#define REG_SC_BK2C_2D_L _PK_L_(0x2C, 0x2D) ++#define REG_SC_BK2C_2D_H _PK_H_(0x2C, 0x2D) ++#define REG_SC_BK2C_2E_L _PK_L_(0x2C, 0x2E) ++#define REG_SC_BK2C_2E_H _PK_H_(0x2C, 0x2E) ++#define REG_SC_BK2C_2F_L _PK_L_(0x2C, 0x2F) ++#define REG_SC_BK2C_2F_H _PK_H_(0x2C, 0x2F) ++#define REG_SC_BK2C_30_L _PK_L_(0x2C, 0x30) ++#define REG_SC_BK2C_30_H _PK_H_(0x2C, 0x30) ++#define REG_SC_BK2C_31_L _PK_L_(0x2C, 0x31) ++#define REG_SC_BK2C_31_H _PK_H_(0x2C, 0x31) ++#define REG_SC_BK2C_32_L _PK_L_(0x2C, 0x32) ++#define REG_SC_BK2C_32_H _PK_H_(0x2C, 0x32) ++#define REG_SC_BK2C_33_L _PK_L_(0x2C, 0x33) ++#define REG_SC_BK2C_33_H _PK_H_(0x2C, 0x33) ++#define REG_SC_BK2C_34_L _PK_L_(0x2C, 0x34) ++#define REG_SC_BK2C_34_H _PK_H_(0x2C, 0x34) ++#define REG_SC_BK2C_35_L _PK_L_(0x2C, 0x35) ++#define REG_SC_BK2C_35_H _PK_H_(0x2C, 0x35) ++#define REG_SC_BK2C_36_L _PK_L_(0x2C, 0x36) ++#define REG_SC_BK2C_36_H _PK_H_(0x2C, 0x36) ++#define REG_SC_BK2C_37_L _PK_L_(0x2C, 0x37) ++#define REG_SC_BK2C_37_H _PK_H_(0x2C, 0x37) ++#define REG_SC_BK2C_38_L _PK_L_(0x2C, 0x38) ++#define REG_SC_BK2C_38_H _PK_H_(0x2C, 0x38) ++#define REG_SC_BK2C_39_L _PK_L_(0x2C, 0x39) ++#define REG_SC_BK2C_39_H _PK_H_(0x2C, 0x39) ++#define REG_SC_BK2C_3A_L _PK_L_(0x2C, 0x3A) ++#define REG_SC_BK2C_3A_H _PK_H_(0x2C, 0x3A) ++#define REG_SC_BK2C_3B_L _PK_L_(0x2C, 0x3B) ++#define REG_SC_BK2C_3B_H _PK_H_(0x2C, 0x3B) ++#define REG_SC_BK2C_3C_L _PK_L_(0x2C, 0x3C) ++#define REG_SC_BK2C_3C_H _PK_H_(0x2C, 0x3C) ++#define REG_SC_BK2C_3D_L _PK_L_(0x2C, 0x3D) ++#define REG_SC_BK2C_3D_H _PK_H_(0x2C, 0x3D) ++#define REG_SC_BK2C_3E_L _PK_L_(0x2C, 0x3E) ++#define REG_SC_BK2C_3E_H _PK_H_(0x2C, 0x3E) ++#define REG_SC_BK2C_3F_L _PK_L_(0x2C, 0x3F) ++#define REG_SC_BK2C_3F_H _PK_H_(0x2C, 0x3F) ++#define REG_SC_BK2C_40_L _PK_L_(0x2C, 0x40) ++#define REG_SC_BK2C_40_H _PK_H_(0x2C, 0x40) ++#define REG_SC_BK2C_41_L _PK_L_(0x2C, 0x41) ++#define REG_SC_BK2C_41_H _PK_H_(0x2C, 0x41) ++#define REG_SC_BK2C_42_L _PK_L_(0x2C, 0x42) ++#define REG_SC_BK2C_42_H _PK_H_(0x2C, 0x42) ++#define REG_SC_BK2C_43_L _PK_L_(0x2C, 0x43) ++#define REG_SC_BK2C_43_H _PK_H_(0x2C, 0x43) ++#define REG_SC_BK2C_44_L _PK_L_(0x2C, 0x44) ++#define REG_SC_BK2C_44_H _PK_H_(0x2C, 0x44) ++#define REG_SC_BK2C_45_L _PK_L_(0x2C, 0x45) ++#define REG_SC_BK2C_45_H _PK_H_(0x2C, 0x45) ++#define REG_SC_BK2C_46_L _PK_L_(0x2C, 0x46) ++#define REG_SC_BK2C_46_H _PK_H_(0x2C, 0x46) ++#define REG_SC_BK2C_47_L _PK_L_(0x2C, 0x47) ++#define REG_SC_BK2C_47_H _PK_H_(0x2C, 0x47) ++#define REG_SC_BK2C_48_L _PK_L_(0x2C, 0x48) ++#define REG_SC_BK2C_48_H _PK_H_(0x2C, 0x48) ++#define REG_SC_BK2C_49_L _PK_L_(0x2C, 0x49) ++#define REG_SC_BK2C_49_H _PK_H_(0x2C, 0x49) ++#define REG_SC_BK2C_4A_L _PK_L_(0x2C, 0x4A) ++#define REG_SC_BK2C_4A_H _PK_H_(0x2C, 0x4A) ++#define REG_SC_BK2C_4B_L _PK_L_(0x2C, 0x4B) ++#define REG_SC_BK2C_4B_H _PK_H_(0x2C, 0x4B) ++#define REG_SC_BK2C_4C_L _PK_L_(0x2C, 0x4C) ++#define REG_SC_BK2C_4C_H _PK_H_(0x2C, 0x4C) ++#define REG_SC_BK2C_4D_L _PK_L_(0x2C, 0x4D) ++#define REG_SC_BK2C_4D_H _PK_H_(0x2C, 0x4D) ++#define REG_SC_BK2C_4E_L _PK_L_(0x2C, 0x4E) ++#define REG_SC_BK2C_4E_H _PK_H_(0x2C, 0x4E) ++#define REG_SC_BK2C_4F_L _PK_L_(0x2C, 0x4F) ++#define REG_SC_BK2C_4F_H _PK_H_(0x2C, 0x4F) ++#define REG_SC_BK2C_50_L _PK_L_(0x2C, 0x50) ++#define REG_SC_BK2C_50_H _PK_H_(0x2C, 0x50) ++#define REG_SC_BK2C_51_L _PK_L_(0x2C, 0x51) ++#define REG_SC_BK2C_51_H _PK_H_(0x2C, 0x51) ++#define REG_SC_BK2C_52_L _PK_L_(0x2C, 0x52) ++#define REG_SC_BK2C_52_H _PK_H_(0x2C, 0x52) ++#define REG_SC_BK2C_53_L _PK_L_(0x2C, 0x53) ++#define REG_SC_BK2C_53_H _PK_H_(0x2C, 0x53) ++#define REG_SC_BK2C_54_L _PK_L_(0x2C, 0x54) ++#define REG_SC_BK2C_54_H _PK_H_(0x2C, 0x54) ++#define REG_SC_BK2C_55_L _PK_L_(0x2C, 0x55) ++#define REG_SC_BK2C_55_H _PK_H_(0x2C, 0x55) ++#define REG_SC_BK2C_56_L _PK_L_(0x2C, 0x56) ++#define REG_SC_BK2C_56_H _PK_H_(0x2C, 0x56) ++#define REG_SC_BK2C_57_L _PK_L_(0x2C, 0x57) ++#define REG_SC_BK2C_57_H _PK_H_(0x2C, 0x57) ++#define REG_SC_BK2C_58_L _PK_L_(0x2C, 0x58) ++#define REG_SC_BK2C_58_H _PK_H_(0x2C, 0x58) ++#define REG_SC_BK2C_59_L _PK_L_(0x2C, 0x59) ++#define REG_SC_BK2C_59_H _PK_H_(0x2C, 0x59) ++#define REG_SC_BK2C_5A_L _PK_L_(0x2C, 0x5A) ++#define REG_SC_BK2C_5A_H _PK_H_(0x2C, 0x5A) ++#define REG_SC_BK2C_5B_L _PK_L_(0x2C, 0x5B) ++#define REG_SC_BK2C_5B_H _PK_H_(0x2C, 0x5B) ++#define REG_SC_BK2C_5C_L _PK_L_(0x2C, 0x5C) ++#define REG_SC_BK2C_5C_H _PK_H_(0x2C, 0x5C) ++#define REG_SC_BK2C_5D_L _PK_L_(0x2C, 0x5D) ++#define REG_SC_BK2C_5D_H _PK_H_(0x2C, 0x5D) ++#define REG_SC_BK2C_5E_L _PK_L_(0x2C, 0x5E) ++#define REG_SC_BK2C_5E_H _PK_H_(0x2C, 0x5E) ++#define REG_SC_BK2C_5F_L _PK_L_(0x2C, 0x5F) ++#define REG_SC_BK2C_5F_H _PK_H_(0x2C, 0x5F) ++#define REG_SC_BK2C_60_L _PK_L_(0x2C, 0x60) ++#define REG_SC_BK2C_60_H _PK_H_(0x2C, 0x60) ++#define REG_SC_BK2C_61_L _PK_L_(0x2C, 0x61) ++#define REG_SC_BK2C_61_H _PK_H_(0x2C, 0x61) ++#define REG_SC_BK2C_62_L _PK_L_(0x2C, 0x62) ++#define REG_SC_BK2C_62_H _PK_H_(0x2C, 0x62) ++#define REG_SC_BK2C_63_L _PK_L_(0x2C, 0x63) ++#define REG_SC_BK2C_63_H _PK_H_(0x2C, 0x63) ++#define REG_SC_BK2C_64_L _PK_L_(0x2C, 0x64) ++#define REG_SC_BK2C_64_H _PK_H_(0x2C, 0x64) ++#define REG_SC_BK2C_65_L _PK_L_(0x2C, 0x65) ++#define REG_SC_BK2C_65_H _PK_H_(0x2C, 0x65) ++#define REG_SC_BK2C_66_L _PK_L_(0x2C, 0x66) ++#define REG_SC_BK2C_66_H _PK_H_(0x2C, 0x66) ++#define REG_SC_BK2C_67_L _PK_L_(0x2C, 0x67) ++#define REG_SC_BK2C_67_H _PK_H_(0x2C, 0x67) ++#define REG_SC_BK2C_68_L _PK_L_(0x2C, 0x68) ++#define REG_SC_BK2C_68_H _PK_H_(0x2C, 0x68) ++#define REG_SC_BK2C_69_L _PK_L_(0x2C, 0x69) ++#define REG_SC_BK2C_69_H _PK_H_(0x2C, 0x69) ++#define REG_SC_BK2C_6A_L _PK_L_(0x2C, 0x6A) ++#define REG_SC_BK2C_6A_H _PK_H_(0x2C, 0x6A) ++#define REG_SC_BK2C_6B_L _PK_L_(0x2C, 0x6B) ++#define REG_SC_BK2C_6B_H _PK_H_(0x2C, 0x6B) ++#define REG_SC_BK2C_6C_L _PK_L_(0x2C, 0x6C) ++#define REG_SC_BK2C_6C_H _PK_H_(0x2C, 0x6C) ++#define REG_SC_BK2C_6D_L _PK_L_(0x2C, 0x6D) ++#define REG_SC_BK2C_6D_H _PK_H_(0x2C, 0x6D) ++#define REG_SC_BK2C_6E_L _PK_L_(0x2C, 0x6E) ++#define REG_SC_BK2C_6E_H _PK_H_(0x2C, 0x6E) ++#define REG_SC_BK2C_6F_L _PK_L_(0x2C, 0x6F) ++#define REG_SC_BK2C_6F_H _PK_H_(0x2C, 0x6F) ++#define REG_SC_BK2C_70_L _PK_L_(0x2C, 0x70) ++#define REG_SC_BK2C_70_H _PK_H_(0x2C, 0x70) ++#define REG_SC_BK2C_71_L _PK_L_(0x2C, 0x71) ++#define REG_SC_BK2C_71_H _PK_H_(0x2C, 0x71) ++#define REG_SC_BK2C_72_L _PK_L_(0x2C, 0x72) ++#define REG_SC_BK2C_72_H _PK_H_(0x2C, 0x72) ++#define REG_SC_BK2C_73_L _PK_L_(0x2C, 0x73) ++#define REG_SC_BK2C_73_H _PK_H_(0x2C, 0x73) ++#define REG_SC_BK2C_74_L _PK_L_(0x2C, 0x74) ++#define REG_SC_BK2C_74_H _PK_H_(0x2C, 0x74) ++#define REG_SC_BK2C_75_L _PK_L_(0x2C, 0x75) ++#define REG_SC_BK2C_75_H _PK_H_(0x2C, 0x75) ++#define REG_SC_BK2C_76_L _PK_L_(0x2C, 0x76) ++#define REG_SC_BK2C_76_H _PK_H_(0x2C, 0x76) ++#define REG_SC_BK2C_77_L _PK_L_(0x2C, 0x77) ++#define REG_SC_BK2C_77_H _PK_H_(0x2C, 0x77) ++#define REG_SC_BK2C_78_L _PK_L_(0x2C, 0x78) ++#define REG_SC_BK2C_78_H _PK_H_(0x2C, 0x78) ++#define REG_SC_BK2C_79_L _PK_L_(0x2C, 0x79) ++#define REG_SC_BK2C_79_H _PK_H_(0x2C, 0x79) ++#define REG_SC_BK2C_7A_L _PK_L_(0x2C, 0x7A) ++#define REG_SC_BK2C_7A_H _PK_H_(0x2C, 0x7A) ++#define REG_SC_BK2C_7B_L _PK_L_(0x2C, 0x7B) ++#define REG_SC_BK2C_7B_H _PK_H_(0x2C, 0x7B) ++#define REG_SC_BK2C_7C_L _PK_L_(0x2C, 0x7C) ++#define REG_SC_BK2C_7C_H _PK_H_(0x2C, 0x7C) ++#define REG_SC_BK2C_7D_L _PK_L_(0x2C, 0x7D) ++#define REG_SC_BK2C_7D_H _PK_H_(0x2C, 0x7D) ++#define REG_SC_BK2C_7E_L _PK_L_(0x2C, 0x7E) ++#define REG_SC_BK2C_7E_H _PK_H_(0x2C, 0x7E) ++#define REG_SC_BK2C_7F_L _PK_L_(0x2C, 0x7F) ++#define REG_SC_BK2C_7F_H _PK_H_(0x2C, 0x7F) ++#define REG_SC_BK30_01_L _PK_L_(0x30, 0x01) ++#define REG_SC_BK30_01_H _PK_H_(0x30, 0x01) ++#define REG_SC_BK30_02_L _PK_L_(0x30, 0x02) ++#define REG_SC_BK30_02_H _PK_H_(0x30, 0x02) ++#define REG_SC_BK30_03_L _PK_L_(0x30, 0x03) ++#define REG_SC_BK30_03_H _PK_H_(0x30, 0x03) ++//---------------------------------------------- ++#define REG_BK35_00_L 0x3500 ++#define REG_BK35_00_H 0x3501 ++#define REG_BK35_01_L 0x3502 ++#define REG_BK35_01_H 0x3503 ++#define REG_BK35_02_L 0x3504 ++#define REG_BK35_02_H 0x3505 ++#define REG_BK35_03_L 0x3506 ++#define REG_BK35_03_H 0x3507 ++#define REG_BK35_04_L 0x3508 ++#define REG_BK35_04_H 0x3509 ++#define REG_BK35_05_L 0x350A ++#define REG_BK35_05_H 0x350B ++#define REG_BK35_06_L 0x350C ++#define REG_BK35_06_H 0x350D ++#define REG_BK35_07_L 0x350E ++#define REG_BK35_07_H 0x350F ++#define REG_BK35_08_L 0x3510 ++#define REG_BK35_08_H 0x3511 ++#define REG_BK35_09_L 0x3512 ++#define REG_BK35_09_H 0x3513 ++#define REG_BK35_0A_L 0x3514 ++#define REG_BK35_0A_H 0x3515 ++#define REG_BK35_0B_L 0x3516 ++#define REG_BK35_0B_H 0x3517 ++#define REG_BK35_0C_L 0x3518 ++#define REG_BK35_0C_H 0x3519 ++#define REG_BK35_0D_L 0x351A ++#define REG_BK35_0D_H 0x351B ++#define REG_BK35_0E_L 0x351C ++#define REG_BK35_0E_H 0x351D ++#define REG_BK35_0F_L 0x351E ++#define REG_BK35_0F_H 0x351F ++#define REG_BK35_10_L 0x3520 ++#define REG_BK35_10_H 0x3521 ++#define REG_BK35_11_L 0x3522 ++#define REG_BK35_11_H 0x3523 ++#define REG_BK35_12_L 0x3524 ++#define REG_BK35_12_H 0x3525 ++#define REG_BK35_13_L 0x3526 ++#define REG_BK35_13_H 0x3527 ++#define REG_BK35_14_L 0x3528 ++#define REG_BK35_14_H 0x3529 ++#define REG_BK35_15_L 0x352A ++#define REG_BK35_15_H 0x352B ++#define REG_BK35_16_L 0x352C ++#define REG_BK35_16_H 0x352D ++#define REG_BK35_17_L 0x352E ++#define REG_BK35_17_H 0x352F ++#define REG_BK35_18_L 0x3530 ++#define REG_BK35_18_H 0x3531 ++#define REG_BK35_19_L 0x3532 ++#define REG_BK35_19_H 0x3533 ++#define REG_BK35_1A_L 0x3534 ++#define REG_BK35_1A_H 0x3535 ++#define REG_BK35_1B_L 0x3536 ++#define REG_BK35_1B_H 0x3537 ++#define REG_BK35_1C_L 0x3538 ++#define REG_BK35_1C_H 0x3539 ++#define REG_BK35_1D_L 0x353A ++#define REG_BK35_1D_H 0x353B ++#define REG_BK35_1E_L 0x353C ++#define REG_BK35_1E_H 0x353D ++#define REG_BK35_1F_L 0x353E ++#define REG_BK35_1F_H 0x353F ++#define REG_BK35_20_L 0x3540 ++#define REG_BK35_20_H 0x3541 ++#define REG_BK35_21_L 0x3542 ++#define REG_BK35_21_H 0x3543 ++#define REG_BK35_22_L 0x3544 ++#define REG_BK35_22_H 0x3545 ++#define REG_BK35_23_L 0x3546 ++#define REG_BK35_23_H 0x3547 ++#define REG_BK35_24_L 0x3548 ++#define REG_BK35_24_H 0x3549 ++#define REG_BK35_25_L 0x354A ++#define REG_BK35_25_H 0x354B ++#define REG_BK35_26_L 0x354C ++#define REG_BK35_26_H 0x354D ++#define REG_BK35_27_L 0x354E ++#define REG_BK35_27_H 0x354F ++#define REG_BK35_28_L 0x3550 ++#define REG_BK35_28_H 0x3551 ++#define REG_BK35_29_L 0x3552 ++#define REG_BK35_29_H 0x3553 ++#define REG_BK35_2A_L 0x3554 ++#define REG_BK35_2A_H 0x3555 ++#define REG_BK35_2B_L 0x3556 ++#define REG_BK35_2B_H 0x3557 ++#define REG_BK35_2C_L 0x3558 ++#define REG_BK35_2C_H 0x3559 ++#define REG_BK35_2D_L 0x355A ++#define REG_BK35_2D_H 0x355B ++#define REG_BK35_2E_L 0x355C ++#define REG_BK35_2E_H 0x355D ++#define REG_BK35_2F_L 0x355E ++#define REG_BK35_2F_H 0x355F ++#define REG_BK35_30_L 0x3560 ++#define REG_BK35_30_H 0x3561 ++#define REG_BK35_31_L 0x3562 ++#define REG_BK35_31_H 0x3563 ++#define REG_BK35_32_L 0x3564 ++#define REG_BK35_32_H 0x3565 ++#define REG_BK35_33_L 0x3566 ++#define REG_BK35_33_H 0x3567 ++#define REG_BK35_34_L 0x3568 ++#define REG_BK35_34_H 0x3569 ++#define REG_BK35_35_L 0x356A ++#define REG_BK35_35_H 0x356B ++#define REG_BK35_36_L 0x356C ++#define REG_BK35_36_H 0x356D ++#define REG_BK35_37_L 0x356E ++#define REG_BK35_37_H 0x356F ++#define REG_BK35_38_L 0x3570 ++#define REG_BK35_38_H 0x3571 ++#define REG_BK35_39_L 0x3572 ++#define REG_BK35_39_H 0x3573 ++#define REG_BK35_3A_L 0x3574 ++#define REG_BK35_3A_H 0x3575 ++#define REG_BK35_3B_L 0x3576 ++#define REG_BK35_3B_H 0x3577 ++#define REG_BK35_3C_L 0x3578 ++#define REG_BK35_3C_H 0x3579 ++#define REG_BK35_3D_L 0x357A ++#define REG_BK35_3D_H 0x357B ++#define REG_BK35_3E_L 0x357C ++#define REG_BK35_3E_H 0x357D ++#define REG_BK35_3F_L 0x357E ++#define REG_BK35_3F_H 0x357F ++#define REG_BK35_40_L 0x3580 ++#define REG_BK35_40_H 0x3581 ++#define REG_BK35_41_L 0x3582 ++#define REG_BK35_41_H 0x3583 ++#define REG_BK35_42_L 0x3584 ++#define REG_BK35_42_H 0x3585 ++#define REG_BK35_43_L 0x3586 ++#define REG_BK35_43_H 0x3587 ++#define REG_BK35_44_L 0x3588 ++#define REG_BK35_44_H 0x3589 ++#define REG_BK35_45_L 0x358A ++#define REG_BK35_45_H 0x358B ++#define REG_BK35_46_L 0x358C ++#define REG_BK35_46_H 0x358D ++#define REG_BK35_47_L 0x358E ++#define REG_BK35_47_H 0x358F ++#define REG_BK35_48_L 0x3590 ++#define REG_BK35_48_H 0x3591 ++#define REG_BK35_49_L 0x3592 ++#define REG_BK35_49_H 0x3593 ++#define REG_BK35_4A_L 0x3594 ++#define REG_BK35_4A_H 0x3595 ++#define REG_BK35_4B_L 0x3596 ++#define REG_BK35_4B_H 0x3597 ++#define REG_BK35_4C_L 0x3598 ++#define REG_BK35_4C_H 0x3599 ++#define REG_BK35_4D_L 0x359A ++#define REG_BK35_4D_H 0x359B ++#define REG_BK35_4E_L 0x359C ++#define REG_BK35_4E_H 0x359D ++#define REG_BK35_4F_L 0x359E ++#define REG_BK35_4F_H 0x359F ++#define REG_BK35_50_L 0x35A0 ++#define REG_BK35_50_H 0x35A1 ++#define REG_BK35_51_L 0x35A2 ++#define REG_BK35_51_H 0x35A3 ++#define REG_BK35_52_L 0x35A4 ++#define REG_BK35_52_H 0x35A5 ++#define REG_BK35_53_L 0x35A6 ++#define REG_BK35_53_H 0x35A7 ++#define REG_BK35_54_L 0x35A8 ++#define REG_BK35_54_H 0x35A9 ++#define REG_BK35_55_L 0x35AA ++#define REG_BK35_55_H 0x35AB ++#define REG_BK35_56_L 0x35AC ++#define REG_BK35_56_H 0x35AD ++#define REG_BK35_57_L 0x35AE ++#define REG_BK35_57_H 0x35AF ++#define REG_BK35_58_L 0x35B0 ++#define REG_BK35_58_H 0x35B1 ++#define REG_BK35_59_L 0x35B2 ++#define REG_BK35_59_H 0x35B3 ++#define REG_BK35_5A_L 0x35B4 ++#define REG_BK35_5A_H 0x35B5 ++#define REG_BK35_5B_L 0x35B6 ++#define REG_BK35_5B_H 0x35B7 ++#define REG_BK35_5C_L 0x35B8 ++#define REG_BK35_5C_H 0x35B9 ++#define REG_BK35_5D_L 0x35BA ++#define REG_BK35_5D_H 0x35BB ++#define REG_BK35_5E_L 0x35BC ++#define REG_BK35_5E_H 0x35BD ++#define REG_BK35_5F_L 0x35BE ++#define REG_BK35_5F_H 0x35BF ++#define REG_BK35_60_L 0x35C0 ++#define REG_BK35_60_H 0x35C1 ++#define REG_BK35_61_L 0x35C2 ++#define REG_BK35_61_H 0x35C3 ++#define REG_BK35_62_L 0x35C4 ++#define REG_BK35_62_H 0x35C5 ++#define REG_BK35_63_L 0x35C6 ++#define REG_BK35_63_H 0x35C7 ++#define REG_BK35_64_L 0x35C8 ++#define REG_BK35_64_H 0x35C9 ++#define REG_BK35_65_L 0x35CA ++#define REG_BK35_65_H 0x35CB ++#define REG_BK35_66_L 0x35CC ++#define REG_BK35_66_H 0x35CD ++#define REG_BK35_67_L 0x35CE ++#define REG_BK35_67_H 0x35CF ++#define REG_BK35_68_L 0x35D0 ++#define REG_BK35_68_H 0x35D1 ++#define REG_BK35_69_L 0x35D2 ++#define REG_BK35_69_H 0x35D3 ++#define REG_BK35_6A_L 0x35D4 ++#define REG_BK35_6A_H 0x35D5 ++#define REG_BK35_6B_L 0x35D6 ++#define REG_BK35_6B_H 0x35D7 ++#define REG_BK35_6C_L 0x35D8 ++#define REG_BK35_6C_H 0x35D9 ++#define REG_BK35_6D_L 0x35DA ++#define REG_BK35_6D_H 0x35DB ++#define REG_BK35_6E_L 0x35DC ++#define REG_BK35_6E_H 0x35DD ++#define REG_BK35_6F_L 0x35DE ++#define REG_BK35_6F_H 0x35DF ++#define REG_BK35_70_L 0x35E0 ++#define REG_BK35_70_H 0x35E1 ++#define REG_BK35_71_L 0x35E2 ++#define REG_BK35_71_H 0x35E3 ++#define REG_BK35_72_L 0x35E4 ++#define REG_BK35_72_H 0x35E5 ++#define REG_BK35_73_L 0x35E6 ++#define REG_BK35_73_H 0x35E7 ++#define REG_BK35_74_L 0x35E8 ++#define REG_BK35_74_H 0x35E9 ++#define REG_BK35_75_L 0x35EA ++#define REG_BK35_75_H 0x35EB ++#define REG_BK35_76_L 0x35EC ++#define REG_BK35_76_H 0x35ED ++#define REG_BK35_77_L 0x35EE ++#define REG_BK35_77_H 0x35EF ++#define REG_BK35_78_L 0x35F0 ++#define REG_BK35_78_H 0x35F1 ++#define REG_BK35_79_L 0x35F2 ++#define REG_BK35_79_H 0x35F3 ++#define REG_BK35_7A_L 0x35F4 ++#define REG_BK35_7A_H 0x35F5 ++#define REG_BK35_7B_L 0x35F6 ++#define REG_BK35_7B_H 0x35F7 ++#define REG_BK35_7C_L 0x35F8 ++#define REG_BK35_7C_H 0x35F9 ++#define REG_BK35_7D_L 0x35FA ++#define REG_BK35_7D_H 0x35FB ++#define REG_BK35_7E_L 0x35FC ++#define REG_BK35_7E_H 0x35FD ++#define REG_BK35_7F_L 0x35FE ++#define REG_BK35_7F_H 0x35FF ++//---------------------------------------------- ++#define REG_COMB_BK00_00_L _PK_L_(0x00, 0x00) ++#define REG_COMB_BK00_00_H _PK_H_(0x00, 0x00) ++#define REG_COMB_BK00_01_L _PK_L_(0x00, 0x01) ++#define REG_COMB_BK00_01_H _PK_H_(0x00, 0x01) ++#define REG_COMB_BK00_02_L _PK_L_(0x00, 0x02) ++#define REG_COMB_BK00_02_H _PK_H_(0x00, 0x02) ++#define REG_COMB_BK00_03_L _PK_L_(0x00, 0x03) ++#define REG_COMB_BK00_03_H _PK_H_(0x00, 0x03) ++#define REG_COMB_BK00_04_L _PK_L_(0x00, 0x04) ++#define REG_COMB_BK00_04_H _PK_H_(0x00, 0x04) ++#define REG_COMB_BK00_05_L _PK_L_(0x00, 0x05) ++#define REG_COMB_BK00_05_H _PK_H_(0x00, 0x05) ++#define REG_COMB_BK00_06_L _PK_L_(0x00, 0x06) ++#define REG_COMB_BK00_06_H _PK_H_(0x00, 0x06) ++#define REG_COMB_BK00_07_L _PK_L_(0x00, 0x07) ++#define REG_COMB_BK00_07_H _PK_H_(0x00, 0x07) ++#define REG_COMB_BK00_08_L _PK_L_(0x00, 0x08) ++#define REG_COMB_BK00_08_H _PK_H_(0x00, 0x08) ++#define REG_COMB_BK00_09_L _PK_L_(0x00, 0x09) ++#define REG_COMB_BK00_09_H _PK_H_(0x00, 0x09) ++#define REG_COMB_BK00_0A_L _PK_L_(0x00, 0x0A) ++#define REG_COMB_BK00_0A_H _PK_H_(0x00, 0x0A) ++#define REG_COMB_BK00_0B_L _PK_L_(0x00, 0x0B) ++#define REG_COMB_BK00_0B_H _PK_H_(0x00, 0x0B) ++#define REG_COMB_BK00_0C_L _PK_L_(0x00, 0x0C) ++#define REG_COMB_BK00_0C_H _PK_H_(0x00, 0x0C) ++#define REG_COMB_BK00_0D_L _PK_L_(0x00, 0x0D) ++#define REG_COMB_BK00_0D_H _PK_H_(0x00, 0x0D) ++#define REG_COMB_BK00_0E_L _PK_L_(0x00, 0x0E) ++#define REG_COMB_BK00_0E_H _PK_H_(0x00, 0x0E) ++#define REG_COMB_BK00_0F_L _PK_L_(0x00, 0x0F) ++#define REG_COMB_BK00_0F_H _PK_H_(0x00, 0x0F) ++#define REG_COMB_BK00_10_L _PK_L_(0x00, 0x10) ++#define REG_COMB_BK00_10_H _PK_H_(0x00, 0x10) ++#define REG_COMB_BK00_11_L _PK_L_(0x00, 0x11) ++#define REG_COMB_BK00_11_H _PK_H_(0x00, 0x11) ++#define REG_COMB_BK00_12_L _PK_L_(0x00, 0x12) ++#define REG_COMB_BK00_12_H _PK_H_(0x00, 0x12) ++#define REG_COMB_BK00_13_L _PK_L_(0x00, 0x13) ++#define REG_COMB_BK00_13_H _PK_H_(0x00, 0x13) ++#define REG_COMB_BK00_14_L _PK_L_(0x00, 0x14) ++#define REG_COMB_BK00_14_H _PK_H_(0x00, 0x14) ++#define REG_COMB_BK00_15_L _PK_L_(0x00, 0x15) ++#define REG_COMB_BK00_15_H _PK_H_(0x00, 0x15) ++#define REG_COMB_BK00_16_L _PK_L_(0x00, 0x16) ++#define REG_COMB_BK00_16_H _PK_H_(0x00, 0x16) ++#define REG_COMB_BK00_17_L _PK_L_(0x00, 0x17) ++#define REG_COMB_BK00_17_H _PK_H_(0x00, 0x17) ++#define REG_COMB_BK00_18_L _PK_L_(0x00, 0x18) ++#define REG_COMB_BK00_18_H _PK_H_(0x00, 0x18) ++#define REG_COMB_BK00_19_L _PK_L_(0x00, 0x19) ++#define REG_COMB_BK00_19_H _PK_H_(0x00, 0x19) ++#define REG_COMB_BK00_1A_L _PK_L_(0x00, 0x1A) ++#define REG_COMB_BK00_1A_H _PK_H_(0x00, 0x1A) ++#define REG_COMB_BK00_1B_L _PK_L_(0x00, 0x1B) ++#define REG_COMB_BK00_1B_H _PK_H_(0x00, 0x1B) ++#define REG_COMB_BK00_1C_L _PK_L_(0x00, 0x1C) ++#define REG_COMB_BK00_1C_H _PK_H_(0x00, 0x1C) ++#define REG_COMB_BK00_1D_L _PK_L_(0x00, 0x1D) ++#define REG_COMB_BK00_1D_H _PK_H_(0x00, 0x1D) ++#define REG_COMB_BK00_1E_L _PK_L_(0x00, 0x1E) ++#define REG_COMB_BK00_1E_H _PK_H_(0x00, 0x1E) ++#define REG_COMB_BK00_1F_L _PK_L_(0x00, 0x1F) ++#define REG_COMB_BK00_1F_H _PK_H_(0x00, 0x1F) ++#define REG_COMB_BK00_20_L _PK_L_(0x00, 0x20) ++#define REG_COMB_BK00_20_H _PK_H_(0x00, 0x20) ++#define REG_COMB_BK00_21_L _PK_L_(0x00, 0x21) ++#define REG_COMB_BK00_21_H _PK_H_(0x00, 0x21) ++#define REG_COMB_BK00_22_L _PK_L_(0x00, 0x22) ++#define REG_COMB_BK00_22_H _PK_H_(0x00, 0x22) ++#define REG_COMB_BK00_23_L _PK_L_(0x00, 0x23) ++#define REG_COMB_BK00_23_H _PK_H_(0x00, 0x23) ++#define REG_COMB_BK00_24_L _PK_L_(0x00, 0x24) ++#define REG_COMB_BK00_24_H _PK_H_(0x00, 0x24) ++#define REG_COMB_BK00_25_L _PK_L_(0x00, 0x25) ++#define REG_COMB_BK00_25_H _PK_H_(0x00, 0x25) ++#define REG_COMB_BK00_26_L _PK_L_(0x00, 0x26) ++#define REG_COMB_BK00_26_H _PK_H_(0x00, 0x26) ++#define REG_COMB_BK00_27_L _PK_L_(0x00, 0x27) ++#define REG_COMB_BK00_27_H _PK_H_(0x00, 0x27) ++#define REG_COMB_BK00_28_L _PK_L_(0x00, 0x28) ++#define REG_COMB_BK00_28_H _PK_H_(0x00, 0x28) ++#define REG_COMB_BK00_29_L _PK_L_(0x00, 0x29) ++#define REG_COMB_BK00_29_H _PK_H_(0x00, 0x29) ++#define REG_COMB_BK00_2A_L _PK_L_(0x00, 0x2A) ++#define REG_COMB_BK00_2A_H _PK_H_(0x00, 0x2A) ++#define REG_COMB_BK00_2B_L _PK_L_(0x00, 0x2B) ++#define REG_COMB_BK00_2B_H _PK_H_(0x00, 0x2B) ++#define REG_COMB_BK00_2C_L _PK_L_(0x00, 0x2C) ++#define REG_COMB_BK00_2C_H _PK_H_(0x00, 0x2C) ++#define REG_COMB_BK00_2D_L _PK_L_(0x00, 0x2D) ++#define REG_COMB_BK00_2D_H _PK_H_(0x00, 0x2D) ++#define REG_COMB_BK00_2E_L _PK_L_(0x00, 0x2E) ++#define REG_COMB_BK00_2E_H _PK_H_(0x00, 0x2E) ++#define REG_COMB_BK00_2F_L _PK_L_(0x00, 0x2F) ++#define REG_COMB_BK00_2F_H _PK_H_(0x00, 0x2F) ++#define REG_COMB_BK00_30_L _PK_L_(0x00, 0x30) ++#define REG_COMB_BK00_30_H _PK_H_(0x00, 0x30) ++#define REG_COMB_BK00_31_L _PK_L_(0x00, 0x31) ++#define REG_COMB_BK00_31_H _PK_H_(0x00, 0x31) ++#define REG_COMB_BK00_32_L _PK_L_(0x00, 0x32) ++#define REG_COMB_BK00_32_H _PK_H_(0x00, 0x32) ++#define REG_COMB_BK00_33_L _PK_L_(0x00, 0x33) ++#define REG_COMB_BK00_33_H _PK_H_(0x00, 0x33) ++#define REG_COMB_BK00_34_L _PK_L_(0x00, 0x34) ++#define REG_COMB_BK00_34_H _PK_H_(0x00, 0x34) ++#define REG_COMB_BK00_35_L _PK_L_(0x00, 0x35) ++#define REG_COMB_BK00_35_H _PK_H_(0x00, 0x35) ++#define REG_COMB_BK00_36_L _PK_L_(0x00, 0x36) ++#define REG_COMB_BK00_36_H _PK_H_(0x00, 0x36) ++#define REG_COMB_BK00_37_L _PK_L_(0x00, 0x37) ++#define REG_COMB_BK00_37_H _PK_H_(0x00, 0x37) ++#define REG_COMB_BK00_38_L _PK_L_(0x00, 0x38) ++#define REG_COMB_BK00_38_H _PK_H_(0x00, 0x38) ++#define REG_COMB_BK00_39_L _PK_L_(0x00, 0x39) ++#define REG_COMB_BK00_39_H _PK_H_(0x00, 0x39) ++#define REG_COMB_BK00_3A_L _PK_L_(0x00, 0x3A) ++#define REG_COMB_BK00_3A_H _PK_H_(0x00, 0x3A) ++#define REG_COMB_BK00_3B_L _PK_L_(0x00, 0x3B) ++#define REG_COMB_BK00_3B_H _PK_H_(0x00, 0x3B) ++#define REG_COMB_BK00_3C_L _PK_L_(0x00, 0x3C) ++#define REG_COMB_BK00_3C_H _PK_H_(0x00, 0x3C) ++#define REG_COMB_BK00_3D_L _PK_L_(0x00, 0x3D) ++#define REG_COMB_BK00_3D_H _PK_H_(0x00, 0x3D) ++#define REG_COMB_BK00_3E_L _PK_L_(0x00, 0x3E) ++#define REG_COMB_BK00_3E_H _PK_H_(0x00, 0x3E) ++#define REG_COMB_BK00_3F_L _PK_L_(0x00, 0x3F) ++#define REG_COMB_BK00_3F_H _PK_H_(0x00, 0x3F) ++#define REG_COMB_BK00_40_L _PK_L_(0x00, 0x40) ++#define REG_COMB_BK00_40_H _PK_H_(0x00, 0x40) ++#define REG_COMB_BK00_41_L _PK_L_(0x00, 0x41) ++#define REG_COMB_BK00_41_H _PK_H_(0x00, 0x41) ++#define REG_COMB_BK00_42_L _PK_L_(0x00, 0x42) ++#define REG_COMB_BK00_42_H _PK_H_(0x00, 0x42) ++#define REG_COMB_BK00_43_L _PK_L_(0x00, 0x43) ++#define REG_COMB_BK00_43_H _PK_H_(0x00, 0x43) ++#define REG_COMB_BK00_44_L _PK_L_(0x00, 0x44) ++#define REG_COMB_BK00_44_H _PK_H_(0x00, 0x44) ++#define REG_COMB_BK00_45_L _PK_L_(0x00, 0x45) ++#define REG_COMB_BK00_45_H _PK_H_(0x00, 0x45) ++#define REG_COMB_BK00_46_L _PK_L_(0x00, 0x46) ++#define REG_COMB_BK00_46_H _PK_H_(0x00, 0x46) ++#define REG_COMB_BK00_47_L _PK_L_(0x00, 0x47) ++#define REG_COMB_BK00_47_H _PK_H_(0x00, 0x47) ++#define REG_COMB_BK00_48_L _PK_L_(0x00, 0x48) ++#define REG_COMB_BK00_48_H _PK_H_(0x00, 0x48) ++#define REG_COMB_BK00_49_L _PK_L_(0x00, 0x49) ++#define REG_COMB_BK00_49_H _PK_H_(0x00, 0x49) ++#define REG_COMB_BK00_4A_L _PK_L_(0x00, 0x4A) ++#define REG_COMB_BK00_4A_H _PK_H_(0x00, 0x4A) ++#define REG_COMB_BK00_4B_L _PK_L_(0x00, 0x4B) ++#define REG_COMB_BK00_4B_H _PK_H_(0x00, 0x4B) ++#define REG_COMB_BK00_4C_L _PK_L_(0x00, 0x4C) ++#define REG_COMB_BK00_4C_H _PK_H_(0x00, 0x4C) ++#define REG_COMB_BK00_4D_L _PK_L_(0x00, 0x4D) ++#define REG_COMB_BK00_4D_H _PK_H_(0x00, 0x4D) ++#define REG_COMB_BK00_4E_L _PK_L_(0x00, 0x4E) ++#define REG_COMB_BK00_4E_H _PK_H_(0x00, 0x4E) ++#define REG_COMB_BK00_4F_L _PK_L_(0x00, 0x4F) ++#define REG_COMB_BK00_4F_H _PK_H_(0x00, 0x4F) ++#define REG_COMB_BK00_50_L _PK_L_(0x00, 0x50) ++#define REG_COMB_BK00_50_H _PK_H_(0x00, 0x50) ++#define REG_COMB_BK00_51_L _PK_L_(0x00, 0x51) ++#define REG_COMB_BK00_51_H _PK_H_(0x00, 0x51) ++#define REG_COMB_BK00_52_L _PK_L_(0x00, 0x52) ++#define REG_COMB_BK00_52_H _PK_H_(0x00, 0x52) ++#define REG_COMB_BK00_53_L _PK_L_(0x00, 0x53) ++#define REG_COMB_BK00_53_H _PK_H_(0x00, 0x53) ++#define REG_COMB_BK00_54_L _PK_L_(0x00, 0x54) ++#define REG_COMB_BK00_54_H _PK_H_(0x00, 0x54) ++#define REG_COMB_BK00_55_L _PK_L_(0x00, 0x55) ++#define REG_COMB_BK00_55_H _PK_H_(0x00, 0x55) ++#define REG_COMB_BK00_56_L _PK_L_(0x00, 0x56) ++#define REG_COMB_BK00_56_H _PK_H_(0x00, 0x56) ++#define REG_COMB_BK00_57_L _PK_L_(0x00, 0x57) ++#define REG_COMB_BK00_57_H _PK_H_(0x00, 0x57) ++#define REG_COMB_BK00_58_L _PK_L_(0x00, 0x58) ++#define REG_COMB_BK00_58_H _PK_H_(0x00, 0x58) ++#define REG_COMB_BK00_59_L _PK_L_(0x00, 0x59) ++#define REG_COMB_BK00_59_H _PK_H_(0x00, 0x59) ++#define REG_COMB_BK00_5A_L _PK_L_(0x00, 0x5A) ++#define REG_COMB_BK00_5A_H _PK_H_(0x00, 0x5A) ++#define REG_COMB_BK00_5B_L _PK_L_(0x00, 0x5B) ++#define REG_COMB_BK00_5B_H _PK_H_(0x00, 0x5B) ++#define REG_COMB_BK00_5C_L _PK_L_(0x00, 0x5C) ++#define REG_COMB_BK00_5C_H _PK_H_(0x00, 0x5C) ++#define REG_COMB_BK00_5D_L _PK_L_(0x00, 0x5D) ++#define REG_COMB_BK00_5D_H _PK_H_(0x00, 0x5D) ++#define REG_COMB_BK00_5E_L _PK_L_(0x00, 0x5E) ++#define REG_COMB_BK00_5E_H _PK_H_(0x00, 0x5E) ++#define REG_COMB_BK00_5F_L _PK_L_(0x00, 0x5F) ++#define REG_COMB_BK00_5F_H _PK_H_(0x00, 0x5F) ++#define REG_COMB_BK00_60_L _PK_L_(0x00, 0x60) ++#define REG_COMB_BK00_60_H _PK_H_(0x00, 0x60) ++#define REG_COMB_BK00_61_L _PK_L_(0x00, 0x61) ++#define REG_COMB_BK00_61_H _PK_H_(0x00, 0x61) ++#define REG_COMB_BK00_62_L _PK_L_(0x00, 0x62) ++#define REG_COMB_BK00_62_H _PK_H_(0x00, 0x62) ++#define REG_COMB_BK00_63_L _PK_L_(0x00, 0x63) ++#define REG_COMB_BK00_63_H _PK_H_(0x00, 0x63) ++#define REG_COMB_BK00_64_L _PK_L_(0x00, 0x64) ++#define REG_COMB_BK00_64_H _PK_H_(0x00, 0x64) ++#define REG_COMB_BK00_65_L _PK_L_(0x00, 0x65) ++#define REG_COMB_BK00_65_H _PK_H_(0x00, 0x65) ++#define REG_COMB_BK00_66_L _PK_L_(0x00, 0x66) ++#define REG_COMB_BK00_66_H _PK_H_(0x00, 0x66) ++#define REG_COMB_BK00_67_L _PK_L_(0x00, 0x67) ++#define REG_COMB_BK00_67_H _PK_H_(0x00, 0x67) ++#define REG_COMB_BK00_68_L _PK_L_(0x00, 0x68) ++#define REG_COMB_BK00_68_H _PK_H_(0x00, 0x68) ++#define REG_COMB_BK00_69_L _PK_L_(0x00, 0x69) ++#define REG_COMB_BK00_69_H _PK_H_(0x00, 0x69) ++#define REG_COMB_BK00_6A_L _PK_L_(0x00, 0x6A) ++#define REG_COMB_BK00_6A_H _PK_H_(0x00, 0x6A) ++#define REG_COMB_BK00_6B_L _PK_L_(0x00, 0x6B) ++#define REG_COMB_BK00_6B_H _PK_H_(0x00, 0x6B) ++#define REG_COMB_BK00_6C_L _PK_L_(0x00, 0x6C) ++#define REG_COMB_BK00_6C_H _PK_H_(0x00, 0x6C) ++#define REG_COMB_BK00_6D_L _PK_L_(0x00, 0x6D) ++#define REG_COMB_BK00_6D_H _PK_H_(0x00, 0x6D) ++#define REG_COMB_BK00_6E_L _PK_L_(0x00, 0x6E) ++#define REG_COMB_BK00_6E_H _PK_H_(0x00, 0x6E) ++#define REG_COMB_BK00_6F_L _PK_L_(0x00, 0x6F) ++#define REG_COMB_BK00_6F_H _PK_H_(0x00, 0x6F) ++#define REG_COMB_BK00_70_L _PK_L_(0x00, 0x70) ++#define REG_COMB_BK00_70_H _PK_H_(0x00, 0x70) ++#define REG_COMB_BK00_71_L _PK_L_(0x00, 0x71) ++#define REG_COMB_BK00_71_H _PK_H_(0x00, 0x71) ++#define REG_COMB_BK00_72_L _PK_L_(0x00, 0x72) ++#define REG_COMB_BK00_72_H _PK_H_(0x00, 0x72) ++#define REG_COMB_BK00_73_L _PK_L_(0x00, 0x73) ++#define REG_COMB_BK00_73_H _PK_H_(0x00, 0x73) ++#define REG_COMB_BK00_74_L _PK_L_(0x00, 0x74) ++#define REG_COMB_BK00_74_H _PK_H_(0x00, 0x74) ++#define REG_COMB_BK00_75_L _PK_L_(0x00, 0x75) ++#define REG_COMB_BK00_75_H _PK_H_(0x00, 0x75) ++#define REG_COMB_BK00_76_L _PK_L_(0x00, 0x76) ++#define REG_COMB_BK00_76_H _PK_H_(0x00, 0x76) ++#define REG_COMB_BK00_77_L _PK_L_(0x00, 0x77) ++#define REG_COMB_BK00_77_H _PK_H_(0x00, 0x77) ++#define REG_COMB_BK00_78_L _PK_L_(0x00, 0x78) ++#define REG_COMB_BK00_78_H _PK_H_(0x00, 0x78) ++#define REG_COMB_BK00_79_L _PK_L_(0x00, 0x79) ++#define REG_COMB_BK00_79_H _PK_H_(0x00, 0x79) ++#define REG_COMB_BK00_7A_L _PK_L_(0x00, 0x7A) ++#define REG_COMB_BK00_7A_H _PK_H_(0x00, 0x7A) ++#define REG_COMB_BK00_7B_L _PK_L_(0x00, 0x7B) ++#define REG_COMB_BK00_7B_H _PK_H_(0x00, 0x7B) ++#define REG_COMB_BK00_7C_L _PK_L_(0x00, 0x7C) ++#define REG_COMB_BK00_7C_H _PK_H_(0x00, 0x7C) ++#define REG_COMB_BK00_7D_L _PK_L_(0x00, 0x7D) ++#define REG_COMB_BK00_7D_H _PK_H_(0x00, 0x7D) ++#define REG_COMB_BK00_7E_L _PK_L_(0x00, 0x7E) ++#define REG_COMB_BK00_7E_H _PK_H_(0x00, 0x7E) ++#define REG_COMB_BK00_7F_L _PK_L_(0x00, 0x7F) ++#define REG_COMB_BK00_7F_H _PK_H_(0x00, 0x7F) ++//---------------------------------------------- ++#define REG_COMB_BK01_00_L _PK_L_(0x01, 0x00) ++#define REG_COMB_BK01_00_H _PK_H_(0x01, 0x00) ++#define REG_COMB_BK01_01_L _PK_L_(0x01, 0x01) ++#define REG_COMB_BK01_01_H _PK_H_(0x01, 0x01) ++#define REG_COMB_BK01_02_L _PK_L_(0x01, 0x02) ++#define REG_COMB_BK01_02_H _PK_H_(0x01, 0x02) ++#define REG_COMB_BK01_03_L _PK_L_(0x01, 0x03) ++#define REG_COMB_BK01_03_H _PK_H_(0x01, 0x03) ++#define REG_COMB_BK01_04_L _PK_L_(0x01, 0x04) ++#define REG_COMB_BK01_04_H _PK_H_(0x01, 0x04) ++#define REG_COMB_BK01_05_L _PK_L_(0x01, 0x05) ++#define REG_COMB_BK01_05_H _PK_H_(0x01, 0x05) ++#define REG_COMB_BK01_06_L _PK_L_(0x01, 0x06) ++#define REG_COMB_BK01_06_H _PK_H_(0x01, 0x06) ++#define REG_COMB_BK01_07_L _PK_L_(0x01, 0x07) ++#define REG_COMB_BK01_07_H _PK_H_(0x01, 0x07) ++#define REG_COMB_BK01_08_L _PK_L_(0x01, 0x08) ++#define REG_COMB_BK01_08_H _PK_H_(0x01, 0x08) ++#define REG_COMB_BK01_09_L _PK_L_(0x01, 0x09) ++#define REG_COMB_BK01_09_H _PK_H_(0x01, 0x09) ++#define REG_COMB_BK01_0A_L _PK_L_(0x01, 0x0A) ++#define REG_COMB_BK01_0A_H _PK_H_(0x01, 0x0A) ++#define REG_COMB_BK01_0B_L _PK_L_(0x01, 0x0B) ++#define REG_COMB_BK01_0B_H _PK_H_(0x01, 0x0B) ++#define REG_COMB_BK01_0C_L _PK_L_(0x01, 0x0C) ++#define REG_COMB_BK01_0C_H _PK_H_(0x01, 0x0C) ++#define REG_COMB_BK01_0D_L _PK_L_(0x01, 0x0D) ++#define REG_COMB_BK01_0D_H _PK_H_(0x01, 0x0D) ++#define REG_COMB_BK01_0E_L _PK_L_(0x01, 0x0E) ++#define REG_COMB_BK01_0E_H _PK_H_(0x01, 0x0E) ++#define REG_COMB_BK01_0F_L _PK_L_(0x01, 0x0F) ++#define REG_COMB_BK01_0F_H _PK_H_(0x01, 0x0F) ++#define REG_COMB_BK01_10_L _PK_L_(0x01, 0x10) ++#define REG_COMB_BK01_10_H _PK_H_(0x01, 0x10) ++#define REG_COMB_BK01_11_L _PK_L_(0x01, 0x11) ++#define REG_COMB_BK01_11_H _PK_H_(0x01, 0x11) ++#define REG_COMB_BK01_12_L _PK_L_(0x01, 0x12) ++#define REG_COMB_BK01_12_H _PK_H_(0x01, 0x12) ++#define REG_COMB_BK01_13_L _PK_L_(0x01, 0x13) ++#define REG_COMB_BK01_13_H _PK_H_(0x01, 0x13) ++#define REG_COMB_BK01_14_L _PK_L_(0x01, 0x14) ++#define REG_COMB_BK01_14_H _PK_H_(0x01, 0x14) ++#define REG_COMB_BK01_15_L _PK_L_(0x01, 0x15) ++#define REG_COMB_BK01_15_H _PK_H_(0x01, 0x15) ++#define REG_COMB_BK01_16_L _PK_L_(0x01, 0x16) ++#define REG_COMB_BK01_16_H _PK_H_(0x01, 0x16) ++#define REG_COMB_BK01_17_L _PK_L_(0x01, 0x17) ++#define REG_COMB_BK01_17_H _PK_H_(0x01, 0x17) ++#define REG_COMB_BK01_18_L _PK_L_(0x01, 0x18) ++#define REG_COMB_BK01_18_H _PK_H_(0x01, 0x18) ++#define REG_COMB_BK01_19_L _PK_L_(0x01, 0x19) ++#define REG_COMB_BK01_19_H _PK_H_(0x01, 0x19) ++#define REG_COMB_BK01_1A_L _PK_L_(0x01, 0x1A) ++#define REG_COMB_BK01_1A_H _PK_H_(0x01, 0x1A) ++#define REG_COMB_BK01_1B_L _PK_L_(0x01, 0x1B) ++#define REG_COMB_BK01_1B_H _PK_H_(0x01, 0x1B) ++#define REG_COMB_BK01_1C_L _PK_L_(0x01, 0x1C) ++#define REG_COMB_BK01_1C_H _PK_H_(0x01, 0x1C) ++#define REG_COMB_BK01_1D_L _PK_L_(0x01, 0x1D) ++#define REG_COMB_BK01_1D_H _PK_H_(0x01, 0x1D) ++#define REG_COMB_BK01_1E_L _PK_L_(0x01, 0x1E) ++#define REG_COMB_BK01_1E_H _PK_H_(0x01, 0x1E) ++#define REG_COMB_BK01_1F_L _PK_L_(0x01, 0x1F) ++#define REG_COMB_BK01_1F_H _PK_H_(0x01, 0x1F) ++#define REG_COMB_BK01_20_L _PK_L_(0x01, 0x20) ++#define REG_COMB_BK01_20_H _PK_H_(0x01, 0x20) ++#define REG_COMB_BK01_21_L _PK_L_(0x01, 0x21) ++#define REG_COMB_BK01_21_H _PK_H_(0x01, 0x21) ++#define REG_COMB_BK01_22_L _PK_L_(0x01, 0x22) ++#define REG_COMB_BK01_22_H _PK_H_(0x01, 0x22) ++#define REG_COMB_BK01_23_L _PK_L_(0x01, 0x23) ++#define REG_COMB_BK01_23_H _PK_H_(0x01, 0x23) ++#define REG_COMB_BK01_24_L _PK_L_(0x01, 0x24) ++#define REG_COMB_BK01_24_H _PK_H_(0x01, 0x24) ++#define REG_COMB_BK01_25_L _PK_L_(0x01, 0x25) ++#define REG_COMB_BK01_25_H _PK_H_(0x01, 0x25) ++#define REG_COMB_BK01_26_L _PK_L_(0x01, 0x26) ++#define REG_COMB_BK01_26_H _PK_H_(0x01, 0x26) ++#define REG_COMB_BK01_27_L _PK_L_(0x01, 0x27) ++#define REG_COMB_BK01_27_H _PK_H_(0x01, 0x27) ++#define REG_COMB_BK01_28_L _PK_L_(0x01, 0x28) ++#define REG_COMB_BK01_28_H _PK_H_(0x01, 0x28) ++#define REG_COMB_BK01_29_L _PK_L_(0x01, 0x29) ++#define REG_COMB_BK01_29_H _PK_H_(0x01, 0x29) ++#define REG_COMB_BK01_2A_L _PK_L_(0x01, 0x2A) ++#define REG_COMB_BK01_2A_H _PK_H_(0x01, 0x2A) ++#define REG_COMB_BK01_2B_L _PK_L_(0x01, 0x2B) ++#define REG_COMB_BK01_2B_H _PK_H_(0x01, 0x2B) ++#define REG_COMB_BK01_2C_L _PK_L_(0x01, 0x2C) ++#define REG_COMB_BK01_2C_H _PK_H_(0x01, 0x2C) ++#define REG_COMB_BK01_2D_L _PK_L_(0x01, 0x2D) ++#define REG_COMB_BK01_2D_H _PK_H_(0x01, 0x2D) ++#define REG_COMB_BK01_2E_L _PK_L_(0x01, 0x2E) ++#define REG_COMB_BK01_2E_H _PK_H_(0x01, 0x2E) ++#define REG_COMB_BK01_2F_L _PK_L_(0x01, 0x2F) ++#define REG_COMB_BK01_2F_H _PK_H_(0x01, 0x2F) ++#define REG_COMB_BK01_30_L _PK_L_(0x01, 0x30) ++#define REG_COMB_BK01_30_H _PK_H_(0x01, 0x30) ++#define REG_COMB_BK01_31_L _PK_L_(0x01, 0x31) ++#define REG_COMB_BK01_31_H _PK_H_(0x01, 0x31) ++#define REG_COMB_BK01_32_L _PK_L_(0x01, 0x32) ++#define REG_COMB_BK01_32_H _PK_H_(0x01, 0x32) ++#define REG_COMB_BK01_33_L _PK_L_(0x01, 0x33) ++#define REG_COMB_BK01_33_H _PK_H_(0x01, 0x33) ++#define REG_COMB_BK01_34_L _PK_L_(0x01, 0x34) ++#define REG_COMB_BK01_34_H _PK_H_(0x01, 0x34) ++#define REG_COMB_BK01_35_L _PK_L_(0x01, 0x35) ++#define REG_COMB_BK01_35_H _PK_H_(0x01, 0x35) ++#define REG_COMB_BK01_36_L _PK_L_(0x01, 0x36) ++#define REG_COMB_BK01_36_H _PK_H_(0x01, 0x36) ++#define REG_COMB_BK01_37_L _PK_L_(0x01, 0x37) ++#define REG_COMB_BK01_37_H _PK_H_(0x01, 0x37) ++#define REG_COMB_BK01_38_L _PK_L_(0x01, 0x38) ++#define REG_COMB_BK01_38_H _PK_H_(0x01, 0x38) ++#define REG_COMB_BK01_39_L _PK_L_(0x01, 0x39) ++#define REG_COMB_BK01_39_H _PK_H_(0x01, 0x39) ++#define REG_COMB_BK01_3A_L _PK_L_(0x01, 0x3A) ++#define REG_COMB_BK01_3A_H _PK_H_(0x01, 0x3A) ++#define REG_COMB_BK01_3B_L _PK_L_(0x01, 0x3B) ++#define REG_COMB_BK01_3B_H _PK_H_(0x01, 0x3B) ++#define REG_COMB_BK01_3C_L _PK_L_(0x01, 0x3C) ++#define REG_COMB_BK01_3C_H _PK_H_(0x01, 0x3C) ++#define REG_COMB_BK01_3D_L _PK_L_(0x01, 0x3D) ++#define REG_COMB_BK01_3D_H _PK_H_(0x01, 0x3D) ++#define REG_COMB_BK01_3E_L _PK_L_(0x01, 0x3E) ++#define REG_COMB_BK01_3E_H _PK_H_(0x01, 0x3E) ++#define REG_COMB_BK01_3F_L _PK_L_(0x01, 0x3F) ++#define REG_COMB_BK01_3F_H _PK_H_(0x01, 0x3F) ++#define REG_COMB_BK01_40_L _PK_L_(0x01, 0x40) ++#define REG_COMB_BK01_40_H _PK_H_(0x01, 0x40) ++#define REG_COMB_BK01_41_L _PK_L_(0x01, 0x41) ++#define REG_COMB_BK01_41_H _PK_H_(0x01, 0x41) ++#define REG_COMB_BK01_42_L _PK_L_(0x01, 0x42) ++#define REG_COMB_BK01_42_H _PK_H_(0x01, 0x42) ++#define REG_COMB_BK01_43_L _PK_L_(0x01, 0x43) ++#define REG_COMB_BK01_43_H _PK_H_(0x01, 0x43) ++#define REG_COMB_BK01_44_L _PK_L_(0x01, 0x44) ++#define REG_COMB_BK01_44_H _PK_H_(0x01, 0x44) ++#define REG_COMB_BK01_45_L _PK_L_(0x01, 0x45) ++#define REG_COMB_BK01_45_H _PK_H_(0x01, 0x45) ++#define REG_COMB_BK01_46_L _PK_L_(0x01, 0x46) ++#define REG_COMB_BK01_46_H _PK_H_(0x01, 0x46) ++#define REG_COMB_BK01_47_L _PK_L_(0x01, 0x47) ++#define REG_COMB_BK01_47_H _PK_H_(0x01, 0x47) ++#define REG_COMB_BK01_48_L _PK_L_(0x01, 0x48) ++#define REG_COMB_BK01_48_H _PK_H_(0x01, 0x48) ++#define REG_COMB_BK01_49_L _PK_L_(0x01, 0x49) ++#define REG_COMB_BK01_49_H _PK_H_(0x01, 0x49) ++#define REG_COMB_BK01_4A_L _PK_L_(0x01, 0x4A) ++#define REG_COMB_BK01_4A_H _PK_H_(0x01, 0x4A) ++#define REG_COMB_BK01_4B_L _PK_L_(0x01, 0x4B) ++#define REG_COMB_BK01_4B_H _PK_H_(0x01, 0x4B) ++#define REG_COMB_BK01_4C_L _PK_L_(0x01, 0x4C) ++#define REG_COMB_BK01_4C_H _PK_H_(0x01, 0x4C) ++#define REG_COMB_BK01_4D_L _PK_L_(0x01, 0x4D) ++#define REG_COMB_BK01_4D_H _PK_H_(0x01, 0x4D) ++#define REG_COMB_BK01_4E_L _PK_L_(0x01, 0x4E) ++#define REG_COMB_BK01_4E_H _PK_H_(0x01, 0x4E) ++#define REG_COMB_BK01_4F_L _PK_L_(0x01, 0x4F) ++#define REG_COMB_BK01_4F_H _PK_H_(0x01, 0x4F) ++#define REG_COMB_BK01_50_L _PK_L_(0x01, 0x50) ++#define REG_COMB_BK01_50_H _PK_H_(0x01, 0x50) ++#define REG_COMB_BK01_51_L _PK_L_(0x01, 0x51) ++#define REG_COMB_BK01_51_H _PK_H_(0x01, 0x51) ++#define REG_COMB_BK01_52_L _PK_L_(0x01, 0x52) ++#define REG_COMB_BK01_52_H _PK_H_(0x01, 0x52) ++#define REG_COMB_BK01_53_L _PK_L_(0x01, 0x53) ++#define REG_COMB_BK01_53_H _PK_H_(0x01, 0x53) ++#define REG_COMB_BK01_54_L _PK_L_(0x01, 0x54) ++#define REG_COMB_BK01_54_H _PK_H_(0x01, 0x54) ++#define REG_COMB_BK01_55_L _PK_L_(0x01, 0x55) ++#define REG_COMB_BK01_55_H _PK_H_(0x01, 0x55) ++#define REG_COMB_BK01_56_L _PK_L_(0x01, 0x56) ++#define REG_COMB_BK01_56_H _PK_H_(0x01, 0x56) ++#define REG_COMB_BK01_57_L _PK_L_(0x01, 0x57) ++#define REG_COMB_BK01_57_H _PK_H_(0x01, 0x57) ++#define REG_COMB_BK01_58_L _PK_L_(0x01, 0x58) ++#define REG_COMB_BK01_58_H _PK_H_(0x01, 0x58) ++#define REG_COMB_BK01_59_L _PK_L_(0x01, 0x59) ++#define REG_COMB_BK01_59_H _PK_H_(0x01, 0x59) ++#define REG_COMB_BK01_5A_L _PK_L_(0x01, 0x5A) ++#define REG_COMB_BK01_5A_H _PK_H_(0x01, 0x5A) ++#define REG_COMB_BK01_5B_L _PK_L_(0x01, 0x5B) ++#define REG_COMB_BK01_5B_H _PK_H_(0x01, 0x5B) ++#define REG_COMB_BK01_5C_L _PK_L_(0x01, 0x5C) ++#define REG_COMB_BK01_5C_H _PK_H_(0x01, 0x5C) ++#define REG_COMB_BK01_5D_L _PK_L_(0x01, 0x5D) ++#define REG_COMB_BK01_5D_H _PK_H_(0x01, 0x5D) ++#define REG_COMB_BK01_5E_L _PK_L_(0x01, 0x5E) ++#define REG_COMB_BK01_5E_H _PK_H_(0x01, 0x5E) ++#define REG_COMB_BK01_5F_L _PK_L_(0x01, 0x5F) ++#define REG_COMB_BK01_5F_H _PK_H_(0x01, 0x5F) ++#define REG_COMB_BK01_60_L _PK_L_(0x01, 0x60) ++#define REG_COMB_BK01_60_H _PK_H_(0x01, 0x60) ++#define REG_COMB_BK01_61_L _PK_L_(0x01, 0x61) ++#define REG_COMB_BK01_61_H _PK_H_(0x01, 0x61) ++#define REG_COMB_BK01_62_L _PK_L_(0x01, 0x62) ++#define REG_COMB_BK01_62_H _PK_H_(0x01, 0x62) ++#define REG_COMB_BK01_63_L _PK_L_(0x01, 0x63) ++#define REG_COMB_BK01_63_H _PK_H_(0x01, 0x63) ++#define REG_COMB_BK01_64_L _PK_L_(0x01, 0x64) ++#define REG_COMB_BK01_64_H _PK_H_(0x01, 0x64) ++#define REG_COMB_BK01_65_L _PK_L_(0x01, 0x65) ++#define REG_COMB_BK01_65_H _PK_H_(0x01, 0x65) ++#define REG_COMB_BK01_66_L _PK_L_(0x01, 0x66) ++#define REG_COMB_BK01_66_H _PK_H_(0x01, 0x66) ++#define REG_COMB_BK01_67_L _PK_L_(0x01, 0x67) ++#define REG_COMB_BK01_67_H _PK_H_(0x01, 0x67) ++#define REG_COMB_BK01_68_L _PK_L_(0x01, 0x68) ++#define REG_COMB_BK01_68_H _PK_H_(0x01, 0x68) ++#define REG_COMB_BK01_69_L _PK_L_(0x01, 0x69) ++#define REG_COMB_BK01_69_H _PK_H_(0x01, 0x69) ++#define REG_COMB_BK01_6A_L _PK_L_(0x01, 0x6A) ++#define REG_COMB_BK01_6A_H _PK_H_(0x01, 0x6A) ++#define REG_COMB_BK01_6B_L _PK_L_(0x01, 0x6B) ++#define REG_COMB_BK01_6B_H _PK_H_(0x01, 0x6B) ++#define REG_COMB_BK01_6C_L _PK_L_(0x01, 0x6C) ++#define REG_COMB_BK01_6C_H _PK_H_(0x01, 0x6C) ++#define REG_COMB_BK01_6D_L _PK_L_(0x01, 0x6D) ++#define REG_COMB_BK01_6D_H _PK_H_(0x01, 0x6D) ++#define REG_COMB_BK01_6E_L _PK_L_(0x01, 0x6E) ++#define REG_COMB_BK01_6E_H _PK_H_(0x01, 0x6E) ++#define REG_COMB_BK01_6F_L _PK_L_(0x01, 0x6F) ++#define REG_COMB_BK01_6F_H _PK_H_(0x01, 0x6F) ++#define REG_COMB_BK01_70_L _PK_L_(0x01, 0x70) ++#define REG_COMB_BK01_70_H _PK_H_(0x01, 0x70) ++#define REG_COMB_BK01_71_L _PK_L_(0x01, 0x71) ++#define REG_COMB_BK01_71_H _PK_H_(0x01, 0x71) ++#define REG_COMB_BK01_72_L _PK_L_(0x01, 0x72) ++#define REG_COMB_BK01_72_H _PK_H_(0x01, 0x72) ++#define REG_COMB_BK01_73_L _PK_L_(0x01, 0x73) ++#define REG_COMB_BK01_73_H _PK_H_(0x01, 0x73) ++#define REG_COMB_BK01_74_L _PK_L_(0x01, 0x74) ++#define REG_COMB_BK01_74_H _PK_H_(0x01, 0x74) ++#define REG_COMB_BK01_75_L _PK_L_(0x01, 0x75) ++#define REG_COMB_BK01_75_H _PK_H_(0x01, 0x75) ++#define REG_COMB_BK01_76_L _PK_L_(0x01, 0x76) ++#define REG_COMB_BK01_76_H _PK_H_(0x01, 0x76) ++#define REG_COMB_BK01_77_L _PK_L_(0x01, 0x77) ++#define REG_COMB_BK01_77_H _PK_H_(0x01, 0x77) ++#define REG_COMB_BK01_78_L _PK_L_(0x01, 0x78) ++#define REG_COMB_BK01_78_H _PK_H_(0x01, 0x78) ++#define REG_COMB_BK01_79_L _PK_L_(0x01, 0x79) ++#define REG_COMB_BK01_79_H _PK_H_(0x01, 0x79) ++#define REG_COMB_BK01_7A_L _PK_L_(0x01, 0x7A) ++#define REG_COMB_BK01_7A_H _PK_H_(0x01, 0x7A) ++#define REG_COMB_BK01_7B_L _PK_L_(0x01, 0x7B) ++#define REG_COMB_BK01_7B_H _PK_H_(0x01, 0x7B) ++#define REG_COMB_BK01_7C_L _PK_L_(0x01, 0x7C) ++#define REG_COMB_BK01_7C_H _PK_H_(0x01, 0x7C) ++#define REG_COMB_BK01_7D_L _PK_L_(0x01, 0x7D) ++#define REG_COMB_BK01_7D_H _PK_H_(0x01, 0x7D) ++#define REG_COMB_BK01_7E_L _PK_L_(0x01, 0x7E) ++#define REG_COMB_BK01_7E_H _PK_H_(0x01, 0x7E) ++#define REG_COMB_BK01_7F_L _PK_L_(0x01, 0x7F) ++#define REG_COMB_BK01_7F_H _PK_H_(0x01, 0x7F) ++//---------------------------------------------- ++#define REG_COMB_BK02_00_L _PK_L_(0x02, 0x00) ++#define REG_COMB_BK02_00_H _PK_H_(0x02, 0x00) ++#define REG_COMB_BK02_01_L _PK_L_(0x02, 0x01) ++#define REG_COMB_BK02_01_H _PK_H_(0x02, 0x01) ++#define REG_COMB_BK02_02_L _PK_L_(0x02, 0x02) ++#define REG_COMB_BK02_02_H _PK_H_(0x02, 0x02) ++#define REG_COMB_BK02_03_L _PK_L_(0x02, 0x03) ++#define REG_COMB_BK02_03_H _PK_H_(0x02, 0x03) ++#define REG_COMB_BK02_04_L _PK_L_(0x02, 0x04) ++#define REG_COMB_BK02_04_H _PK_H_(0x02, 0x04) ++#define REG_COMB_BK02_05_L _PK_L_(0x02, 0x05) ++#define REG_COMB_BK02_05_H _PK_H_(0x02, 0x05) ++#define REG_COMB_BK02_06_L _PK_L_(0x02, 0x06) ++#define REG_COMB_BK02_06_H _PK_H_(0x02, 0x06) ++#define REG_COMB_BK02_07_L _PK_L_(0x02, 0x07) ++#define REG_COMB_BK02_07_H _PK_H_(0x02, 0x07) ++#define REG_COMB_BK02_08_L _PK_L_(0x02, 0x08) ++#define REG_COMB_BK02_08_H _PK_H_(0x02, 0x08) ++#define REG_COMB_BK02_09_L _PK_L_(0x02, 0x09) ++#define REG_COMB_BK02_09_H _PK_H_(0x02, 0x09) ++#define REG_COMB_BK02_0A_L _PK_L_(0x02, 0x0A) ++#define REG_COMB_BK02_0A_H _PK_H_(0x02, 0x0A) ++#define REG_COMB_BK02_0B_L _PK_L_(0x02, 0x0B) ++#define REG_COMB_BK02_0B_H _PK_H_(0x02, 0x0B) ++#define REG_COMB_BK02_0C_L _PK_L_(0x02, 0x0C) ++#define REG_COMB_BK02_0C_H _PK_H_(0x02, 0x0C) ++#define REG_COMB_BK02_0D_L _PK_L_(0x02, 0x0D) ++#define REG_COMB_BK02_0D_H _PK_H_(0x02, 0x0D) ++#define REG_COMB_BK02_0E_L _PK_L_(0x02, 0x0E) ++#define REG_COMB_BK02_0E_H _PK_H_(0x02, 0x0E) ++#define REG_COMB_BK02_0F_L _PK_L_(0x02, 0x0F) ++#define REG_COMB_BK02_0F_H _PK_H_(0x02, 0x0F) ++#define REG_COMB_BK02_10_L _PK_L_(0x02, 0x10) ++#define REG_COMB_BK02_10_H _PK_H_(0x02, 0x10) ++#define REG_COMB_BK02_11_L _PK_L_(0x02, 0x11) ++#define REG_COMB_BK02_11_H _PK_H_(0x02, 0x11) ++#define REG_COMB_BK02_12_L _PK_L_(0x02, 0x12) ++#define REG_COMB_BK02_12_H _PK_H_(0x02, 0x12) ++#define REG_COMB_BK02_13_L _PK_L_(0x02, 0x13) ++#define REG_COMB_BK02_13_H _PK_H_(0x02, 0x13) ++#define REG_COMB_BK02_14_L _PK_L_(0x02, 0x14) ++#define REG_COMB_BK02_14_H _PK_H_(0x02, 0x14) ++#define REG_COMB_BK02_15_L _PK_L_(0x02, 0x15) ++#define REG_COMB_BK02_15_H _PK_H_(0x02, 0x15) ++#define REG_COMB_BK02_16_L _PK_L_(0x02, 0x16) ++#define REG_COMB_BK02_16_H _PK_H_(0x02, 0x16) ++#define REG_COMB_BK02_17_L _PK_L_(0x02, 0x17) ++#define REG_COMB_BK02_17_H _PK_H_(0x02, 0x17) ++#define REG_COMB_BK02_18_L _PK_L_(0x02, 0x18) ++#define REG_COMB_BK02_18_H _PK_H_(0x02, 0x18) ++#define REG_COMB_BK02_19_L _PK_L_(0x02, 0x19) ++#define REG_COMB_BK02_19_H _PK_H_(0x02, 0x19) ++#define REG_COMB_BK02_1A_L _PK_L_(0x02, 0x1A) ++#define REG_COMB_BK02_1A_H _PK_H_(0x02, 0x1A) ++#define REG_COMB_BK02_1B_L _PK_L_(0x02, 0x1B) ++#define REG_COMB_BK02_1B_H _PK_H_(0x02, 0x1B) ++#define REG_COMB_BK02_1C_L _PK_L_(0x02, 0x1C) ++#define REG_COMB_BK02_1C_H _PK_H_(0x02, 0x1C) ++#define REG_COMB_BK02_1D_L _PK_L_(0x02, 0x1D) ++#define REG_COMB_BK02_1D_H _PK_H_(0x02, 0x1D) ++#define REG_COMB_BK02_1E_L _PK_L_(0x02, 0x1E) ++#define REG_COMB_BK02_1E_H _PK_H_(0x02, 0x1E) ++#define REG_COMB_BK02_1F_L _PK_L_(0x02, 0x1F) ++#define REG_COMB_BK02_1F_H _PK_H_(0x02, 0x1F) ++#define REG_COMB_BK02_20_L _PK_L_(0x02, 0x20) ++#define REG_COMB_BK02_20_H _PK_H_(0x02, 0x20) ++#define REG_COMB_BK02_21_L _PK_L_(0x02, 0x21) ++#define REG_COMB_BK02_21_H _PK_H_(0x02, 0x21) ++#define REG_COMB_BK02_22_L _PK_L_(0x02, 0x22) ++#define REG_COMB_BK02_22_H _PK_H_(0x02, 0x22) ++#define REG_COMB_BK02_23_L _PK_L_(0x02, 0x23) ++#define REG_COMB_BK02_23_H _PK_H_(0x02, 0x23) ++#define REG_COMB_BK02_24_L _PK_L_(0x02, 0x24) ++#define REG_COMB_BK02_24_H _PK_H_(0x02, 0x24) ++#define REG_COMB_BK02_25_L _PK_L_(0x02, 0x25) ++#define REG_COMB_BK02_25_H _PK_H_(0x02, 0x25) ++#define REG_COMB_BK02_26_L _PK_L_(0x02, 0x26) ++#define REG_COMB_BK02_26_H _PK_H_(0x02, 0x26) ++#define REG_COMB_BK02_27_L _PK_L_(0x02, 0x27) ++#define REG_COMB_BK02_27_H _PK_H_(0x02, 0x27) ++#define REG_COMB_BK02_28_L _PK_L_(0x02, 0x28) ++#define REG_COMB_BK02_28_H _PK_H_(0x02, 0x28) ++#define REG_COMB_BK02_29_L _PK_L_(0x02, 0x29) ++#define REG_COMB_BK02_29_H _PK_H_(0x02, 0x29) ++#define REG_COMB_BK02_2A_L _PK_L_(0x02, 0x2A) ++#define REG_COMB_BK02_2A_H _PK_H_(0x02, 0x2A) ++#define REG_COMB_BK02_2B_L _PK_L_(0x02, 0x2B) ++#define REG_COMB_BK02_2B_H _PK_H_(0x02, 0x2B) ++#define REG_COMB_BK02_2C_L _PK_L_(0x02, 0x2C) ++#define REG_COMB_BK02_2C_H _PK_H_(0x02, 0x2C) ++#define REG_COMB_BK02_2D_L _PK_L_(0x02, 0x2D) ++#define REG_COMB_BK02_2D_H _PK_H_(0x02, 0x2D) ++#define REG_COMB_BK02_2E_L _PK_L_(0x02, 0x2E) ++#define REG_COMB_BK02_2E_H _PK_H_(0x02, 0x2E) ++#define REG_COMB_BK02_2F_L _PK_L_(0x02, 0x2F) ++#define REG_COMB_BK02_2F_H _PK_H_(0x02, 0x2F) ++#define REG_COMB_BK02_30_L _PK_L_(0x02, 0x30) ++#define REG_COMB_BK02_30_H _PK_H_(0x02, 0x30) ++#define REG_COMB_BK02_31_L _PK_L_(0x02, 0x31) ++#define REG_COMB_BK02_31_H _PK_H_(0x02, 0x31) ++#define REG_COMB_BK02_32_L _PK_L_(0x02, 0x32) ++#define REG_COMB_BK02_32_H _PK_H_(0x02, 0x32) ++#define REG_COMB_BK02_33_L _PK_L_(0x02, 0x33) ++#define REG_COMB_BK02_33_H _PK_H_(0x02, 0x33) ++#define REG_COMB_BK02_34_L _PK_L_(0x02, 0x34) ++#define REG_COMB_BK02_34_H _PK_H_(0x02, 0x34) ++#define REG_COMB_BK02_35_L _PK_L_(0x02, 0x35) ++#define REG_COMB_BK02_35_H _PK_H_(0x02, 0x35) ++#define REG_COMB_BK02_36_L _PK_L_(0x02, 0x36) ++#define REG_COMB_BK02_36_H _PK_H_(0x02, 0x36) ++#define REG_COMB_BK02_37_L _PK_L_(0x02, 0x37) ++#define REG_COMB_BK02_37_H _PK_H_(0x02, 0x37) ++#define REG_COMB_BK02_38_L _PK_L_(0x02, 0x38) ++#define REG_COMB_BK02_38_H _PK_H_(0x02, 0x38) ++#define REG_COMB_BK02_39_L _PK_L_(0x02, 0x39) ++#define REG_COMB_BK02_39_H _PK_H_(0x02, 0x39) ++#define REG_COMB_BK02_3A_L _PK_L_(0x02, 0x3A) ++#define REG_COMB_BK02_3A_H _PK_H_(0x02, 0x3A) ++#define REG_COMB_BK02_3B_L _PK_L_(0x02, 0x3B) ++#define REG_COMB_BK02_3B_H _PK_H_(0x02, 0x3B) ++#define REG_COMB_BK02_3C_L _PK_L_(0x02, 0x3C) ++#define REG_COMB_BK02_3C_H _PK_H_(0x02, 0x3C) ++#define REG_COMB_BK02_3D_L _PK_L_(0x02, 0x3D) ++#define REG_COMB_BK02_3D_H _PK_H_(0x02, 0x3D) ++#define REG_COMB_BK02_3E_L _PK_L_(0x02, 0x3E) ++#define REG_COMB_BK02_3E_H _PK_H_(0x02, 0x3E) ++#define REG_COMB_BK02_3F_L _PK_L_(0x02, 0x3F) ++#define REG_COMB_BK02_3F_H _PK_H_(0x02, 0x3F) ++#define REG_COMB_BK02_40_L _PK_L_(0x02, 0x40) ++#define REG_COMB_BK02_40_H _PK_H_(0x02, 0x40) ++#define REG_COMB_BK02_41_L _PK_L_(0x02, 0x41) ++#define REG_COMB_BK02_41_H _PK_H_(0x02, 0x41) ++#define REG_COMB_BK02_42_L _PK_L_(0x02, 0x42) ++#define REG_COMB_BK02_42_H _PK_H_(0x02, 0x42) ++#define REG_COMB_BK02_43_L _PK_L_(0x02, 0x43) ++#define REG_COMB_BK02_43_H _PK_H_(0x02, 0x43) ++#define REG_COMB_BK02_44_L _PK_L_(0x02, 0x44) ++#define REG_COMB_BK02_44_H _PK_H_(0x02, 0x44) ++#define REG_COMB_BK02_45_L _PK_L_(0x02, 0x45) ++#define REG_COMB_BK02_45_H _PK_H_(0x02, 0x45) ++#define REG_COMB_BK02_46_L _PK_L_(0x02, 0x46) ++#define REG_COMB_BK02_46_H _PK_H_(0x02, 0x46) ++#define REG_COMB_BK02_47_L _PK_L_(0x02, 0x47) ++#define REG_COMB_BK02_47_H _PK_H_(0x02, 0x47) ++#define REG_COMB_BK02_48_L _PK_L_(0x02, 0x48) ++#define REG_COMB_BK02_48_H _PK_H_(0x02, 0x48) ++#define REG_COMB_BK02_49_L _PK_L_(0x02, 0x49) ++#define REG_COMB_BK02_49_H _PK_H_(0x02, 0x49) ++#define REG_COMB_BK02_4A_L _PK_L_(0x02, 0x4A) ++#define REG_COMB_BK02_4A_H _PK_H_(0x02, 0x4A) ++#define REG_COMB_BK02_4B_L _PK_L_(0x02, 0x4B) ++#define REG_COMB_BK02_4B_H _PK_H_(0x02, 0x4B) ++#define REG_COMB_BK02_4C_L _PK_L_(0x02, 0x4C) ++#define REG_COMB_BK02_4C_H _PK_H_(0x02, 0x4C) ++#define REG_COMB_BK02_4D_L _PK_L_(0x02, 0x4D) ++#define REG_COMB_BK02_4D_H _PK_H_(0x02, 0x4D) ++#define REG_COMB_BK02_4E_L _PK_L_(0x02, 0x4E) ++#define REG_COMB_BK02_4E_H _PK_H_(0x02, 0x4E) ++#define REG_COMB_BK02_4F_L _PK_L_(0x02, 0x4F) ++#define REG_COMB_BK02_4F_H _PK_H_(0x02, 0x4F) ++#define REG_COMB_BK02_50_L _PK_L_(0x02, 0x50) ++#define REG_COMB_BK02_50_H _PK_H_(0x02, 0x50) ++#define REG_COMB_BK02_51_L _PK_L_(0x02, 0x51) ++#define REG_COMB_BK02_51_H _PK_H_(0x02, 0x51) ++#define REG_COMB_BK02_52_L _PK_L_(0x02, 0x52) ++#define REG_COMB_BK02_52_H _PK_H_(0x02, 0x52) ++#define REG_COMB_BK02_53_L _PK_L_(0x02, 0x53) ++#define REG_COMB_BK02_53_H _PK_H_(0x02, 0x53) ++#define REG_COMB_BK02_54_L _PK_L_(0x02, 0x54) ++#define REG_COMB_BK02_54_H _PK_H_(0x02, 0x54) ++#define REG_COMB_BK02_55_L _PK_L_(0x02, 0x55) ++#define REG_COMB_BK02_55_H _PK_H_(0x02, 0x55) ++#define REG_COMB_BK02_56_L _PK_L_(0x02, 0x56) ++#define REG_COMB_BK02_56_H _PK_H_(0x02, 0x56) ++#define REG_COMB_BK02_57_L _PK_L_(0x02, 0x57) ++#define REG_COMB_BK02_57_H _PK_H_(0x02, 0x57) ++#define REG_COMB_BK02_58_L _PK_L_(0x02, 0x58) ++#define REG_COMB_BK02_58_H _PK_H_(0x02, 0x58) ++#define REG_COMB_BK02_59_L _PK_L_(0x02, 0x59) ++#define REG_COMB_BK02_59_H _PK_H_(0x02, 0x59) ++#define REG_COMB_BK02_5A_L _PK_L_(0x02, 0x5A) ++#define REG_COMB_BK02_5A_H _PK_H_(0x02, 0x5A) ++#define REG_COMB_BK02_5B_L _PK_L_(0x02, 0x5B) ++#define REG_COMB_BK02_5B_H _PK_H_(0x02, 0x5B) ++#define REG_COMB_BK02_5C_L _PK_L_(0x02, 0x5C) ++#define REG_COMB_BK02_5C_H _PK_H_(0x02, 0x5C) ++#define REG_COMB_BK02_5D_L _PK_L_(0x02, 0x5D) ++#define REG_COMB_BK02_5D_H _PK_H_(0x02, 0x5D) ++#define REG_COMB_BK02_5E_L _PK_L_(0x02, 0x5E) ++#define REG_COMB_BK02_5E_H _PK_H_(0x02, 0x5E) ++#define REG_COMB_BK02_5F_L _PK_L_(0x02, 0x5F) ++#define REG_COMB_BK02_5F_H _PK_H_(0x02, 0x5F) ++#define REG_COMB_BK02_60_L _PK_L_(0x02, 0x60) ++#define REG_COMB_BK02_60_H _PK_H_(0x02, 0x60) ++#define REG_COMB_BK02_61_L _PK_L_(0x02, 0x61) ++#define REG_COMB_BK02_61_H _PK_H_(0x02, 0x61) ++#define REG_COMB_BK02_62_L _PK_L_(0x02, 0x62) ++#define REG_COMB_BK02_62_H _PK_H_(0x02, 0x62) ++#define REG_COMB_BK02_63_L _PK_L_(0x02, 0x63) ++#define REG_COMB_BK02_63_H _PK_H_(0x02, 0x63) ++#define REG_COMB_BK02_64_L _PK_L_(0x02, 0x64) ++#define REG_COMB_BK02_64_H _PK_H_(0x02, 0x64) ++#define REG_COMB_BK02_65_L _PK_L_(0x02, 0x65) ++#define REG_COMB_BK02_65_H _PK_H_(0x02, 0x65) ++#define REG_COMB_BK02_66_L _PK_L_(0x02, 0x66) ++#define REG_COMB_BK02_66_H _PK_H_(0x02, 0x66) ++#define REG_COMB_BK02_67_L _PK_L_(0x02, 0x67) ++#define REG_COMB_BK02_67_H _PK_H_(0x02, 0x67) ++#define REG_COMB_BK02_68_L _PK_L_(0x02, 0x68) ++#define REG_COMB_BK02_68_H _PK_H_(0x02, 0x68) ++#define REG_COMB_BK02_69_L _PK_L_(0x02, 0x69) ++#define REG_COMB_BK02_69_H _PK_H_(0x02, 0x69) ++#define REG_COMB_BK02_6A_L _PK_L_(0x02, 0x6A) ++#define REG_COMB_BK02_6A_H _PK_H_(0x02, 0x6A) ++#define REG_COMB_BK02_6B_L _PK_L_(0x02, 0x6B) ++#define REG_COMB_BK02_6B_H _PK_H_(0x02, 0x6B) ++#define REG_COMB_BK02_6C_L _PK_L_(0x02, 0x6C) ++#define REG_COMB_BK02_6C_H _PK_H_(0x02, 0x6C) ++#define REG_COMB_BK02_6D_L _PK_L_(0x02, 0x6D) ++#define REG_COMB_BK02_6D_H _PK_H_(0x02, 0x6D) ++#define REG_COMB_BK02_6E_L _PK_L_(0x02, 0x6E) ++#define REG_COMB_BK02_6E_H _PK_H_(0x02, 0x6E) ++#define REG_COMB_BK02_6F_L _PK_L_(0x02, 0x6F) ++#define REG_COMB_BK02_6F_H _PK_H_(0x02, 0x6F) ++#define REG_COMB_BK02_70_L _PK_L_(0x02, 0x70) ++#define REG_COMB_BK02_70_H _PK_H_(0x02, 0x70) ++#define REG_COMB_BK02_71_L _PK_L_(0x02, 0x71) ++#define REG_COMB_BK02_71_H _PK_H_(0x02, 0x71) ++#define REG_COMB_BK02_72_L _PK_L_(0x02, 0x72) ++#define REG_COMB_BK02_72_H _PK_H_(0x02, 0x72) ++#define REG_COMB_BK02_73_L _PK_L_(0x02, 0x73) ++#define REG_COMB_BK02_73_H _PK_H_(0x02, 0x73) ++#define REG_COMB_BK02_74_L _PK_L_(0x02, 0x74) ++#define REG_COMB_BK02_74_H _PK_H_(0x02, 0x74) ++#define REG_COMB_BK02_75_L _PK_L_(0x02, 0x75) ++#define REG_COMB_BK02_75_H _PK_H_(0x02, 0x75) ++#define REG_COMB_BK02_76_L _PK_L_(0x02, 0x76) ++#define REG_COMB_BK02_76_H _PK_H_(0x02, 0x76) ++#define REG_COMB_BK02_77_L _PK_L_(0x02, 0x77) ++#define REG_COMB_BK02_77_H _PK_H_(0x02, 0x77) ++#define REG_COMB_BK02_78_L _PK_L_(0x02, 0x78) ++#define REG_COMB_BK02_78_H _PK_H_(0x02, 0x78) ++#define REG_COMB_BK02_79_L _PK_L_(0x02, 0x79) ++#define REG_COMB_BK02_79_H _PK_H_(0x02, 0x79) ++#define REG_COMB_BK02_7A_L _PK_L_(0x02, 0x7A) ++#define REG_COMB_BK02_7A_H _PK_H_(0x02, 0x7A) ++#define REG_COMB_BK02_7B_L _PK_L_(0x02, 0x7B) ++#define REG_COMB_BK02_7B_H _PK_H_(0x02, 0x7B) ++#define REG_COMB_BK02_7C_L _PK_L_(0x02, 0x7C) ++#define REG_COMB_BK02_7C_H _PK_H_(0x02, 0x7C) ++#define REG_COMB_BK02_7D_L _PK_L_(0x02, 0x7D) ++#define REG_COMB_BK02_7D_H _PK_H_(0x02, 0x7D) ++#define REG_COMB_BK02_7E_L _PK_L_(0x02, 0x7E) ++#define REG_COMB_BK02_7E_H _PK_H_(0x02, 0x7E) ++#define REG_COMB_BK02_7F_L _PK_L_(0x02, 0x7F) ++#define REG_COMB_BK02_7F_H _PK_H_(0x02, 0x7F) ++#define REG_COMB_BK03_00_L _PK_L_(0x03, 0x00) ++#define REG_COMB_BK03_00_H _PK_H_(0x03, 0x00) ++#define REG_COMB_BK03_01_L _PK_L_(0x03, 0x01) ++#define REG_COMB_BK03_01_H _PK_H_(0x03, 0x01) ++#define REG_COMB_BK03_02_L _PK_L_(0x03, 0x02) ++#define REG_COMB_BK03_02_H _PK_H_(0x03, 0x02) ++#define REG_COMB_BK03_03_L _PK_L_(0x03, 0x03) ++#define REG_COMB_BK03_03_H _PK_H_(0x03, 0x03) ++#define REG_COMB_BK03_04_L _PK_L_(0x03, 0x04) ++#define REG_COMB_BK03_04_H _PK_H_(0x03, 0x04) ++#define REG_COMB_BK03_05_L _PK_L_(0x03, 0x05) ++#define REG_COMB_BK03_05_H _PK_H_(0x03, 0x05) ++#define REG_COMB_BK03_06_L _PK_L_(0x03, 0x06) ++#define REG_COMB_BK03_06_H _PK_H_(0x03, 0x06) ++#define REG_COMB_BK03_07_L _PK_L_(0x03, 0x07) ++#define REG_COMB_BK03_07_H _PK_H_(0x03, 0x07) ++#define REG_COMB_BK03_08_L _PK_L_(0x03, 0x08) ++#define REG_COMB_BK03_08_H _PK_H_(0x03, 0x08) ++#define REG_COMB_BK03_09_L _PK_L_(0x03, 0x09) ++#define REG_COMB_BK03_09_H _PK_H_(0x03, 0x09) ++#define REG_COMB_BK03_0A_L _PK_L_(0x03, 0x0A) ++#define REG_COMB_BK03_0A_H _PK_H_(0x03, 0x0A) ++#define REG_COMB_BK03_0B_L _PK_L_(0x03, 0x0B) ++#define REG_COMB_BK03_0B_H _PK_H_(0x03, 0x0B) ++#define REG_COMB_BK03_0C_L _PK_L_(0x03, 0x0C) ++#define REG_COMB_BK03_0C_H _PK_H_(0x03, 0x0C) ++#define REG_COMB_BK03_0D_L _PK_L_(0x03, 0x0D) ++#define REG_COMB_BK03_0D_H _PK_H_(0x03, 0x0D) ++#define REG_COMB_BK03_0E_L _PK_L_(0x03, 0x0E) ++#define REG_COMB_BK03_0E_H _PK_H_(0x03, 0x0E) ++#define REG_COMB_BK03_0F_L _PK_L_(0x03, 0x0F) ++#define REG_COMB_BK03_0F_H _PK_H_(0x03, 0x0F) ++#define REG_COMB_BK03_10_L _PK_L_(0x03, 0x10) ++#define REG_COMB_BK03_10_H _PK_H_(0x03, 0x10) ++#define REG_COMB_BK03_11_L _PK_L_(0x03, 0x11) ++#define REG_COMB_BK03_11_H _PK_H_(0x03, 0x11) ++#define REG_COMB_BK03_12_L _PK_L_(0x03, 0x12) ++#define REG_COMB_BK03_12_H _PK_H_(0x03, 0x12) ++#define REG_COMB_BK03_13_L _PK_L_(0x03, 0x13) ++#define REG_COMB_BK03_13_H _PK_H_(0x03, 0x13) ++#define REG_COMB_BK03_14_L _PK_L_(0x03, 0x14) ++#define REG_COMB_BK03_14_H _PK_H_(0x03, 0x14) ++#define REG_COMB_BK03_15_L _PK_L_(0x03, 0x15) ++#define REG_COMB_BK03_15_H _PK_H_(0x03, 0x15) ++#define REG_COMB_BK03_16_L _PK_L_(0x03, 0x16) ++#define REG_COMB_BK03_16_H _PK_H_(0x03, 0x16) ++#define REG_COMB_BK03_17_L _PK_L_(0x03, 0x17) ++#define REG_COMB_BK03_17_H _PK_H_(0x03, 0x17) ++#define REG_COMB_BK03_18_L _PK_L_(0x03, 0x18) ++#define REG_COMB_BK03_18_H _PK_H_(0x03, 0x18) ++#define REG_COMB_BK03_19_L _PK_L_(0x03, 0x19) ++#define REG_COMB_BK03_19_H _PK_H_(0x03, 0x19) ++#define REG_COMB_BK03_1A_L _PK_L_(0x03, 0x1A) ++#define REG_COMB_BK03_1A_H _PK_H_(0x03, 0x1A) ++#define REG_COMB_BK03_1B_L _PK_L_(0x03, 0x1B) ++#define REG_COMB_BK03_1B_H _PK_H_(0x03, 0x1B) ++#define REG_COMB_BK03_1C_L _PK_L_(0x03, 0x1C) ++#define REG_COMB_BK03_1C_H _PK_H_(0x03, 0x1C) ++#define REG_COMB_BK03_1D_L _PK_L_(0x03, 0x1D) ++#define REG_COMB_BK03_1D_H _PK_H_(0x03, 0x1D) ++#define REG_COMB_BK03_1E_L _PK_L_(0x03, 0x1E) ++#define REG_COMB_BK03_1E_H _PK_H_(0x03, 0x1E) ++#define REG_COMB_BK03_1F_L _PK_L_(0x03, 0x1F) ++#define REG_COMB_BK03_1F_H _PK_H_(0x03, 0x1F) ++#define REG_COMB_BK03_20_L _PK_L_(0x03, 0x20) ++#define REG_COMB_BK03_20_H _PK_H_(0x03, 0x20) ++#define REG_COMB_BK03_21_L _PK_L_(0x03, 0x21) ++#define REG_COMB_BK03_21_H _PK_H_(0x03, 0x21) ++#define REG_COMB_BK03_22_L _PK_L_(0x03, 0x22) ++#define REG_COMB_BK03_22_H _PK_H_(0x03, 0x22) ++#define REG_COMB_BK03_23_L _PK_L_(0x03, 0x23) ++#define REG_COMB_BK03_23_H _PK_H_(0x03, 0x23) ++#define REG_COMB_BK03_24_L _PK_L_(0x03, 0x24) ++#define REG_COMB_BK03_24_H _PK_H_(0x03, 0x24) ++#define REG_COMB_BK03_25_L _PK_L_(0x03, 0x25) ++#define REG_COMB_BK03_25_H _PK_H_(0x03, 0x25) ++#define REG_COMB_BK03_26_L _PK_L_(0x03, 0x26) ++#define REG_COMB_BK03_26_H _PK_H_(0x03, 0x26) ++#define REG_COMB_BK03_27_L _PK_L_(0x03, 0x27) ++#define REG_COMB_BK03_27_H _PK_H_(0x03, 0x27) ++#define REG_COMB_BK03_28_L _PK_L_(0x03, 0x28) ++#define REG_COMB_BK03_28_H _PK_H_(0x03, 0x28) ++#define REG_COMB_BK03_29_L _PK_L_(0x03, 0x29) ++#define REG_COMB_BK03_29_H _PK_H_(0x03, 0x29) ++#define REG_COMB_BK03_2A_L _PK_L_(0x03, 0x2A) ++#define REG_COMB_BK03_2A_H _PK_H_(0x03, 0x2A) ++#define REG_COMB_BK03_2B_L _PK_L_(0x03, 0x2B) ++#define REG_COMB_BK03_2B_H _PK_H_(0x03, 0x2B) ++#define REG_COMB_BK03_2C_L _PK_L_(0x03, 0x2C) ++#define REG_COMB_BK03_2C_H _PK_H_(0x03, 0x2C) ++#define REG_COMB_BK03_2D_L _PK_L_(0x03, 0x2D) ++#define REG_COMB_BK03_2D_H _PK_H_(0x03, 0x2D) ++#define REG_COMB_BK03_2E_L _PK_L_(0x03, 0x2E) ++#define REG_COMB_BK03_2E_H _PK_H_(0x03, 0x2E) ++#define REG_COMB_BK03_2F_L _PK_L_(0x03, 0x2F) ++#define REG_COMB_BK03_2F_H _PK_H_(0x03, 0x2F) ++#define REG_COMB_BK03_30_L _PK_L_(0x03, 0x30) ++#define REG_COMB_BK03_30_H _PK_H_(0x03, 0x30) ++#define REG_COMB_BK03_31_L _PK_L_(0x03, 0x31) ++#define REG_COMB_BK03_31_H _PK_H_(0x03, 0x31) ++#define REG_COMB_BK03_32_L _PK_L_(0x03, 0x32) ++#define REG_COMB_BK03_32_H _PK_H_(0x03, 0x32) ++#define REG_COMB_BK03_33_L _PK_L_(0x03, 0x33) ++#define REG_COMB_BK03_33_H _PK_H_(0x03, 0x33) ++#define REG_COMB_BK03_34_L _PK_L_(0x03, 0x34) ++#define REG_COMB_BK03_34_H _PK_H_(0x03, 0x34) ++#define REG_COMB_BK03_35_L _PK_L_(0x03, 0x35) ++#define REG_COMB_BK03_35_H _PK_H_(0x03, 0x35) ++#define REG_COMB_BK03_36_L _PK_L_(0x03, 0x36) ++#define REG_COMB_BK03_36_H _PK_H_(0x03, 0x36) ++#define REG_COMB_BK03_37_L _PK_L_(0x03, 0x37) ++#define REG_COMB_BK03_37_H _PK_H_(0x03, 0x37) ++#define REG_COMB_BK03_38_L _PK_L_(0x03, 0x38) ++#define REG_COMB_BK03_38_H _PK_H_(0x03, 0x38) ++#define REG_COMB_BK03_39_L _PK_L_(0x03, 0x39) ++#define REG_COMB_BK03_39_H _PK_H_(0x03, 0x39) ++#define REG_COMB_BK03_3A_L _PK_L_(0x03, 0x3A) ++#define REG_COMB_BK03_3A_H _PK_H_(0x03, 0x3A) ++#define REG_COMB_BK03_3B_L _PK_L_(0x03, 0x3B) ++#define REG_COMB_BK03_3B_H _PK_H_(0x03, 0x3B) ++#define REG_COMB_BK03_3C_L _PK_L_(0x03, 0x3C) ++#define REG_COMB_BK03_3C_H _PK_H_(0x03, 0x3C) ++#define REG_COMB_BK03_3D_L _PK_L_(0x03, 0x3D) ++#define REG_COMB_BK03_3D_H _PK_H_(0x03, 0x3D) ++#define REG_COMB_BK03_3E_L _PK_L_(0x03, 0x3E) ++#define REG_COMB_BK03_3E_H _PK_H_(0x03, 0x3E) ++#define REG_COMB_BK03_3F_L _PK_L_(0x03, 0x3F) ++#define REG_COMB_BK03_3F_H _PK_H_(0x03, 0x3F) ++#define REG_COMB_BK03_40_L _PK_L_(0x03, 0x40) ++#define REG_COMB_BK03_40_H _PK_H_(0x03, 0x40) ++#define REG_COMB_BK03_41_L _PK_L_(0x03, 0x41) ++#define REG_COMB_BK03_41_H _PK_H_(0x03, 0x41) ++#define REG_COMB_BK03_42_L _PK_L_(0x03, 0x42) ++#define REG_COMB_BK03_42_H _PK_H_(0x03, 0x42) ++#define REG_COMB_BK03_43_L _PK_L_(0x03, 0x43) ++#define REG_COMB_BK03_43_H _PK_H_(0x03, 0x43) ++#define REG_COMB_BK03_44_L _PK_L_(0x03, 0x44) ++#define REG_COMB_BK03_44_H _PK_H_(0x03, 0x44) ++#define REG_COMB_BK03_45_L _PK_L_(0x03, 0x45) ++#define REG_COMB_BK03_45_H _PK_H_(0x03, 0x45) ++#define REG_COMB_BK03_46_L _PK_L_(0x03, 0x46) ++#define REG_COMB_BK03_46_H _PK_H_(0x03, 0x46) ++#define REG_COMB_BK03_47_L _PK_L_(0x03, 0x47) ++#define REG_COMB_BK03_47_H _PK_H_(0x03, 0x47) ++#define REG_COMB_BK03_48_L _PK_L_(0x03, 0x48) ++#define REG_COMB_BK03_48_H _PK_H_(0x03, 0x48) ++#define REG_COMB_BK03_49_L _PK_L_(0x03, 0x49) ++#define REG_COMB_BK03_49_H _PK_H_(0x03, 0x49) ++#define REG_COMB_BK03_4A_L _PK_L_(0x03, 0x4A) ++#define REG_COMB_BK03_4A_H _PK_H_(0x03, 0x4A) ++#define REG_COMB_BK03_4B_L _PK_L_(0x03, 0x4B) ++#define REG_COMB_BK03_4B_H _PK_H_(0x03, 0x4B) ++#define REG_COMB_BK03_4C_L _PK_L_(0x03, 0x4C) ++#define REG_COMB_BK03_4C_H _PK_H_(0x03, 0x4C) ++#define REG_COMB_BK03_4D_L _PK_L_(0x03, 0x4D) ++#define REG_COMB_BK03_4D_H _PK_H_(0x03, 0x4D) ++#define REG_COMB_BK03_4E_L _PK_L_(0x03, 0x4E) ++#define REG_COMB_BK03_4E_H _PK_H_(0x03, 0x4E) ++#define REG_COMB_BK03_4F_L _PK_L_(0x03, 0x4F) ++#define REG_COMB_BK03_4F_H _PK_H_(0x03, 0x4F) ++#define REG_COMB_BK03_50_L _PK_L_(0x03, 0x50) ++#define REG_COMB_BK03_50_H _PK_H_(0x03, 0x50) ++#define REG_COMB_BK03_51_L _PK_L_(0x03, 0x51) ++#define REG_COMB_BK03_51_H _PK_H_(0x03, 0x51) ++#define REG_COMB_BK03_52_L _PK_L_(0x03, 0x52) ++#define REG_COMB_BK03_52_H _PK_H_(0x03, 0x52) ++#define REG_COMB_BK03_53_L _PK_L_(0x03, 0x53) ++#define REG_COMB_BK03_53_H _PK_H_(0x03, 0x53) ++#define REG_COMB_BK03_54_L _PK_L_(0x03, 0x54) ++#define REG_COMB_BK03_54_H _PK_H_(0x03, 0x54) ++#define REG_COMB_BK03_55_L _PK_L_(0x03, 0x55) ++#define REG_COMB_BK03_55_H _PK_H_(0x03, 0x55) ++#define REG_COMB_BK03_56_L _PK_L_(0x03, 0x56) ++#define REG_COMB_BK03_56_H _PK_H_(0x03, 0x56) ++#define REG_COMB_BK03_57_L _PK_L_(0x03, 0x57) ++#define REG_COMB_BK03_57_H _PK_H_(0x03, 0x57) ++#define REG_COMB_BK03_58_L _PK_L_(0x03, 0x58) ++#define REG_COMB_BK03_58_H _PK_H_(0x03, 0x58) ++#define REG_COMB_BK03_59_L _PK_L_(0x03, 0x59) ++#define REG_COMB_BK03_59_H _PK_H_(0x03, 0x59) ++#define REG_COMB_BK03_5A_L _PK_L_(0x03, 0x5A) ++#define REG_COMB_BK03_5A_H _PK_H_(0x03, 0x5A) ++#define REG_COMB_BK03_5B_L _PK_L_(0x03, 0x5B) ++#define REG_COMB_BK03_5B_H _PK_H_(0x03, 0x5B) ++#define REG_COMB_BK03_5C_L _PK_L_(0x03, 0x5C) ++#define REG_COMB_BK03_5C_H _PK_H_(0x03, 0x5C) ++#define REG_COMB_BK03_5D_L _PK_L_(0x03, 0x5D) ++#define REG_COMB_BK03_5D_H _PK_H_(0x03, 0x5D) ++#define REG_COMB_BK03_5E_L _PK_L_(0x03, 0x5E) ++#define REG_COMB_BK03_5E_H _PK_H_(0x03, 0x5E) ++#define REG_COMB_BK03_5F_L _PK_L_(0x03, 0x5F) ++#define REG_COMB_BK03_5F_H _PK_H_(0x03, 0x5F) ++#define REG_COMB_BK03_60_L _PK_L_(0x03, 0x60) ++#define REG_COMB_BK03_60_H _PK_H_(0x03, 0x60) ++#define REG_COMB_BK03_61_L _PK_L_(0x03, 0x61) ++#define REG_COMB_BK03_61_H _PK_H_(0x03, 0x61) ++#define REG_COMB_BK03_62_L _PK_L_(0x03, 0x62) ++#define REG_COMB_BK03_62_H _PK_H_(0x03, 0x62) ++#define REG_COMB_BK03_63_L _PK_L_(0x03, 0x63) ++#define REG_COMB_BK03_63_H _PK_H_(0x03, 0x63) ++#define REG_COMB_BK03_64_L _PK_L_(0x03, 0x64) ++#define REG_COMB_BK03_64_H _PK_H_(0x03, 0x64) ++#define REG_COMB_BK03_65_L _PK_L_(0x03, 0x65) ++#define REG_COMB_BK03_65_H _PK_H_(0x03, 0x65) ++#define REG_COMB_BK03_66_L _PK_L_(0x03, 0x66) ++#define REG_COMB_BK03_66_H _PK_H_(0x03, 0x66) ++#define REG_COMB_BK03_67_L _PK_L_(0x03, 0x67) ++#define REG_COMB_BK03_67_H _PK_H_(0x03, 0x67) ++#define REG_COMB_BK03_68_L _PK_L_(0x03, 0x68) ++#define REG_COMB_BK03_68_H _PK_H_(0x03, 0x68) ++#define REG_COMB_BK03_69_L _PK_L_(0x03, 0x69) ++#define REG_COMB_BK03_69_H _PK_H_(0x03, 0x69) ++#define REG_COMB_BK03_6A_L _PK_L_(0x03, 0x6A) ++#define REG_COMB_BK03_6A_H _PK_H_(0x03, 0x6A) ++#define REG_COMB_BK03_6B_L _PK_L_(0x03, 0x6B) ++#define REG_COMB_BK03_6B_H _PK_H_(0x03, 0x6B) ++#define REG_COMB_BK03_6C_L _PK_L_(0x03, 0x6C) ++#define REG_COMB_BK03_6C_H _PK_H_(0x03, 0x6C) ++#define REG_COMB_BK03_6D_L _PK_L_(0x03, 0x6D) ++#define REG_COMB_BK03_6D_H _PK_H_(0x03, 0x6D) ++#define REG_COMB_BK03_6E_L _PK_L_(0x03, 0x6E) ++#define REG_COMB_BK03_6E_H _PK_H_(0x03, 0x6E) ++#define REG_COMB_BK03_6F_L _PK_L_(0x03, 0x6F) ++#define REG_COMB_BK03_6F_H _PK_H_(0x03, 0x6F) ++#define REG_COMB_BK03_70_L _PK_L_(0x03, 0x70) ++#define REG_COMB_BK03_70_H _PK_H_(0x03, 0x70) ++#define REG_COMB_BK03_71_L _PK_L_(0x03, 0x71) ++#define REG_COMB_BK03_71_H _PK_H_(0x03, 0x71) ++#define REG_COMB_BK03_72_L _PK_L_(0x03, 0x72) ++#define REG_COMB_BK03_72_H _PK_H_(0x03, 0x72) ++#define REG_COMB_BK03_73_L _PK_L_(0x03, 0x73) ++#define REG_COMB_BK03_73_H _PK_H_(0x03, 0x73) ++#define REG_COMB_BK03_74_L _PK_L_(0x03, 0x74) ++#define REG_COMB_BK03_74_H _PK_H_(0x03, 0x74) ++#define REG_COMB_BK03_75_L _PK_L_(0x03, 0x75) ++#define REG_COMB_BK03_75_H _PK_H_(0x03, 0x75) ++#define REG_COMB_BK03_76_L _PK_L_(0x03, 0x76) ++#define REG_COMB_BK03_76_H _PK_H_(0x03, 0x76) ++#define REG_COMB_BK03_77_L _PK_L_(0x03, 0x77) ++#define REG_COMB_BK03_77_H _PK_H_(0x03, 0x77) ++#define REG_COMB_BK03_78_L _PK_L_(0x03, 0x78) ++#define REG_COMB_BK03_78_H _PK_H_(0x03, 0x78) ++#define REG_COMB_BK03_79_L _PK_L_(0x03, 0x79) ++#define REG_COMB_BK03_79_H _PK_H_(0x03, 0x79) ++#define REG_COMB_BK03_7A_L _PK_L_(0x03, 0x7A) ++#define REG_COMB_BK03_7A_H _PK_H_(0x03, 0x7A) ++#define REG_COMB_BK03_7B_L _PK_L_(0x03, 0x7B) ++#define REG_COMB_BK03_7B_H _PK_H_(0x03, 0x7B) ++#define REG_COMB_BK03_7C_L _PK_L_(0x03, 0x7C) ++#define REG_COMB_BK03_7C_H _PK_H_(0x03, 0x7C) ++#define REG_COMB_BK03_7D_L _PK_L_(0x03, 0x7D) ++#define REG_COMB_BK03_7D_H _PK_H_(0x03, 0x7D) ++#define REG_COMB_BK03_7E_L _PK_L_(0x03, 0x7E) ++#define REG_COMB_BK03_7E_H _PK_H_(0x03, 0x7E) ++#define REG_COMB_BK03_7F_L _PK_L_(0x03, 0x7F) ++#define REG_COMB_BK03_7F_H _PK_H_(0x03, 0x7F) ++#define REG_COMB_BK04_00_L _PK_L_(0x04, 0x00) ++#define REG_COMB_BK04_00_H _PK_H_(0x04, 0x00) ++#define REG_COMB_BK04_01_L _PK_L_(0x04, 0x01) ++#define REG_COMB_BK04_01_H _PK_H_(0x04, 0x01) ++#define REG_COMB_BK04_02_L _PK_L_(0x04, 0x02) ++#define REG_COMB_BK04_02_H _PK_H_(0x04, 0x02) ++#define REG_COMB_BK04_03_L _PK_L_(0x04, 0x03) ++#define REG_COMB_BK04_03_H _PK_H_(0x04, 0x03) ++#define REG_COMB_BK04_04_L _PK_L_(0x04, 0x04) ++#define REG_COMB_BK04_04_H _PK_H_(0x04, 0x04) ++#define REG_COMB_BK04_05_L _PK_L_(0x04, 0x05) ++#define REG_COMB_BK04_05_H _PK_H_(0x04, 0x05) ++#define REG_COMB_BK04_06_L _PK_L_(0x04, 0x06) ++#define REG_COMB_BK04_06_H _PK_H_(0x04, 0x06) ++#define REG_COMB_BK04_07_L _PK_L_(0x04, 0x07) ++#define REG_COMB_BK04_07_H _PK_H_(0x04, 0x07) ++#define REG_COMB_BK04_08_L _PK_L_(0x04, 0x08) ++#define REG_COMB_BK04_08_H _PK_H_(0x04, 0x08) ++#define REG_COMB_BK04_09_L _PK_L_(0x04, 0x09) ++#define REG_COMB_BK04_09_H _PK_H_(0x04, 0x09) ++#define REG_COMB_BK04_0A_L _PK_L_(0x04, 0x0A) ++#define REG_COMB_BK04_0A_H _PK_H_(0x04, 0x0A) ++#define REG_COMB_BK04_0B_L _PK_L_(0x04, 0x0B) ++#define REG_COMB_BK04_0B_H _PK_H_(0x04, 0x0B) ++#define REG_COMB_BK04_0C_L _PK_L_(0x04, 0x0C) ++#define REG_COMB_BK04_0C_H _PK_H_(0x04, 0x0C) ++#define REG_COMB_BK04_0D_L _PK_L_(0x04, 0x0D) ++#define REG_COMB_BK04_0D_H _PK_H_(0x04, 0x0D) ++#define REG_COMB_BK04_0E_L _PK_L_(0x04, 0x0E) ++#define REG_COMB_BK04_0E_H _PK_H_(0x04, 0x0E) ++#define REG_COMB_BK04_0F_L _PK_L_(0x04, 0x0F) ++#define REG_COMB_BK04_0F_H _PK_H_(0x04, 0x0F) ++#define REG_COMB_BK04_10_L _PK_L_(0x04, 0x10) ++#define REG_COMB_BK04_10_H _PK_H_(0x04, 0x10) ++#define REG_COMB_BK04_11_L _PK_L_(0x04, 0x11) ++#define REG_COMB_BK04_11_H _PK_H_(0x04, 0x11) ++#define REG_COMB_BK04_12_L _PK_L_(0x04, 0x12) ++#define REG_COMB_BK04_12_H _PK_H_(0x04, 0x12) ++#define REG_COMB_BK04_13_L _PK_L_(0x04, 0x13) ++#define REG_COMB_BK04_13_H _PK_H_(0x04, 0x13) ++#define REG_COMB_BK04_14_L _PK_L_(0x04, 0x14) ++#define REG_COMB_BK04_14_H _PK_H_(0x04, 0x14) ++#define REG_COMB_BK04_15_L _PK_L_(0x04, 0x15) ++#define REG_COMB_BK04_15_H _PK_H_(0x04, 0x15) ++#define REG_COMB_BK04_16_L _PK_L_(0x04, 0x16) ++#define REG_COMB_BK04_16_H _PK_H_(0x04, 0x16) ++#define REG_COMB_BK04_17_L _PK_L_(0x04, 0x17) ++#define REG_COMB_BK04_17_H _PK_H_(0x04, 0x17) ++#define REG_COMB_BK04_18_L _PK_L_(0x04, 0x18) ++#define REG_COMB_BK04_18_H _PK_H_(0x04, 0x18) ++#define REG_COMB_BK04_19_L _PK_L_(0x04, 0x19) ++#define REG_COMB_BK04_19_H _PK_H_(0x04, 0x19) ++#define REG_COMB_BK04_1A_L _PK_L_(0x04, 0x1A) ++#define REG_COMB_BK04_1A_H _PK_H_(0x04, 0x1A) ++#define REG_COMB_BK04_1B_L _PK_L_(0x04, 0x1B) ++#define REG_COMB_BK04_1B_H _PK_H_(0x04, 0x1B) ++#define REG_COMB_BK04_1C_L _PK_L_(0x04, 0x1C) ++#define REG_COMB_BK04_1C_H _PK_H_(0x04, 0x1C) ++#define REG_COMB_BK04_1D_L _PK_L_(0x04, 0x1D) ++#define REG_COMB_BK04_1D_H _PK_H_(0x04, 0x1D) ++#define REG_COMB_BK04_1E_L _PK_L_(0x04, 0x1E) ++#define REG_COMB_BK04_1E_H _PK_H_(0x04, 0x1E) ++#define REG_COMB_BK04_1F_L _PK_L_(0x04, 0x1F) ++#define REG_COMB_BK04_1F_H _PK_H_(0x04, 0x1F) ++#define REG_COMB_BK04_20_L _PK_L_(0x04, 0x20) ++#define REG_COMB_BK04_20_H _PK_H_(0x04, 0x20) ++#define REG_COMB_BK04_21_L _PK_L_(0x04, 0x21) ++#define REG_COMB_BK04_21_H _PK_H_(0x04, 0x21) ++#define REG_COMB_BK04_22_L _PK_L_(0x04, 0x22) ++#define REG_COMB_BK04_22_H _PK_H_(0x04, 0x22) ++#define REG_COMB_BK04_23_L _PK_L_(0x04, 0x23) ++#define REG_COMB_BK04_23_H _PK_H_(0x04, 0x23) ++#define REG_COMB_BK04_24_L _PK_L_(0x04, 0x24) ++#define REG_COMB_BK04_24_H _PK_H_(0x04, 0x24) ++#define REG_COMB_BK04_25_L _PK_L_(0x04, 0x25) ++#define REG_COMB_BK04_25_H _PK_H_(0x04, 0x25) ++#define REG_COMB_BK04_26_L _PK_L_(0x04, 0x26) ++#define REG_COMB_BK04_26_H _PK_H_(0x04, 0x26) ++#define REG_COMB_BK04_27_L _PK_L_(0x04, 0x27) ++#define REG_COMB_BK04_27_H _PK_H_(0x04, 0x27) ++#define REG_COMB_BK04_28_L _PK_L_(0x04, 0x28) ++#define REG_COMB_BK04_28_H _PK_H_(0x04, 0x28) ++#define REG_COMB_BK04_29_L _PK_L_(0x04, 0x29) ++#define REG_COMB_BK04_29_H _PK_H_(0x04, 0x29) ++#define REG_COMB_BK04_2A_L _PK_L_(0x04, 0x2A) ++#define REG_COMB_BK04_2A_H _PK_H_(0x04, 0x2A) ++#define REG_COMB_BK04_2B_L _PK_L_(0x04, 0x2B) ++#define REG_COMB_BK04_2B_H _PK_H_(0x04, 0x2B) ++#define REG_COMB_BK04_2C_L _PK_L_(0x04, 0x2C) ++#define REG_COMB_BK04_2C_H _PK_H_(0x04, 0x2C) ++#define REG_COMB_BK04_2D_L _PK_L_(0x04, 0x2D) ++#define REG_COMB_BK04_2D_H _PK_H_(0x04, 0x2D) ++#define REG_COMB_BK04_2E_L _PK_L_(0x04, 0x2E) ++#define REG_COMB_BK04_2E_H _PK_H_(0x04, 0x2E) ++#define REG_COMB_BK04_2F_L _PK_L_(0x04, 0x2F) ++#define REG_COMB_BK04_2F_H _PK_H_(0x04, 0x2F) ++#define REG_COMB_BK04_30_L _PK_L_(0x04, 0x30) ++#define REG_COMB_BK04_30_H _PK_H_(0x04, 0x30) ++#define REG_COMB_BK04_31_L _PK_L_(0x04, 0x31) ++#define REG_COMB_BK04_31_H _PK_H_(0x04, 0x31) ++#define REG_COMB_BK04_32_L _PK_L_(0x04, 0x32) ++#define REG_COMB_BK04_32_H _PK_H_(0x04, 0x32) ++#define REG_COMB_BK04_33_L _PK_L_(0x04, 0x33) ++#define REG_COMB_BK04_33_H _PK_H_(0x04, 0x33) ++#define REG_COMB_BK04_34_L _PK_L_(0x04, 0x34) ++#define REG_COMB_BK04_34_H _PK_H_(0x04, 0x34) ++#define REG_COMB_BK04_35_L _PK_L_(0x04, 0x35) ++#define REG_COMB_BK04_35_H _PK_H_(0x04, 0x35) ++#define REG_COMB_BK04_36_L _PK_L_(0x04, 0x36) ++#define REG_COMB_BK04_36_H _PK_H_(0x04, 0x36) ++#define REG_COMB_BK04_37_L _PK_L_(0x04, 0x37) ++#define REG_COMB_BK04_37_H _PK_H_(0x04, 0x37) ++#define REG_COMB_BK04_38_L _PK_L_(0x04, 0x38) ++#define REG_COMB_BK04_38_H _PK_H_(0x04, 0x38) ++#define REG_COMB_BK04_39_L _PK_L_(0x04, 0x39) ++#define REG_COMB_BK04_39_H _PK_H_(0x04, 0x39) ++#define REG_COMB_BK04_3A_L _PK_L_(0x04, 0x3A) ++#define REG_COMB_BK04_3A_H _PK_H_(0x04, 0x3A) ++#define REG_COMB_BK04_3B_L _PK_L_(0x04, 0x3B) ++#define REG_COMB_BK04_3B_H _PK_H_(0x04, 0x3B) ++#define REG_COMB_BK04_3C_L _PK_L_(0x04, 0x3C) ++#define REG_COMB_BK04_3C_H _PK_H_(0x04, 0x3C) ++#define REG_COMB_BK04_3D_L _PK_L_(0x04, 0x3D) ++#define REG_COMB_BK04_3D_H _PK_H_(0x04, 0x3D) ++#define REG_COMB_BK04_3E_L _PK_L_(0x04, 0x3E) ++#define REG_COMB_BK04_3E_H _PK_H_(0x04, 0x3E) ++#define REG_COMB_BK04_3F_L _PK_L_(0x04, 0x3F) ++#define REG_COMB_BK04_3F_H _PK_H_(0x04, 0x3F) ++#define REG_COMB_BK04_40_L _PK_L_(0x04, 0x40) ++#define REG_COMB_BK04_40_H _PK_H_(0x04, 0x40) ++#define REG_COMB_BK04_41_L _PK_L_(0x04, 0x41) ++#define REG_COMB_BK04_41_H _PK_H_(0x04, 0x41) ++#define REG_COMB_BK04_42_L _PK_L_(0x04, 0x42) ++#define REG_COMB_BK04_42_H _PK_H_(0x04, 0x42) ++#define REG_COMB_BK04_43_L _PK_L_(0x04, 0x43) ++#define REG_COMB_BK04_43_H _PK_H_(0x04, 0x43) ++#define REG_COMB_BK04_44_L _PK_L_(0x04, 0x44) ++#define REG_COMB_BK04_44_H _PK_H_(0x04, 0x44) ++#define REG_COMB_BK04_45_L _PK_L_(0x04, 0x45) ++#define REG_COMB_BK04_45_H _PK_H_(0x04, 0x45) ++#define REG_COMB_BK04_46_L _PK_L_(0x04, 0x46) ++#define REG_COMB_BK04_46_H _PK_H_(0x04, 0x46) ++#define REG_COMB_BK04_47_L _PK_L_(0x04, 0x47) ++#define REG_COMB_BK04_47_H _PK_H_(0x04, 0x47) ++#define REG_COMB_BK04_48_L _PK_L_(0x04, 0x48) ++#define REG_COMB_BK04_48_H _PK_H_(0x04, 0x48) ++#define REG_COMB_BK04_49_L _PK_L_(0x04, 0x49) ++#define REG_COMB_BK04_49_H _PK_H_(0x04, 0x49) ++#define REG_COMB_BK04_4A_L _PK_L_(0x04, 0x4A) ++#define REG_COMB_BK04_4A_H _PK_H_(0x04, 0x4A) ++#define REG_COMB_BK04_4B_L _PK_L_(0x04, 0x4B) ++#define REG_COMB_BK04_4B_H _PK_H_(0x04, 0x4B) ++#define REG_COMB_BK04_4C_L _PK_L_(0x04, 0x4C) ++#define REG_COMB_BK04_4C_H _PK_H_(0x04, 0x4C) ++#define REG_COMB_BK04_4D_L _PK_L_(0x04, 0x4D) ++#define REG_COMB_BK04_4D_H _PK_H_(0x04, 0x4D) ++#define REG_COMB_BK04_4E_L _PK_L_(0x04, 0x4E) ++#define REG_COMB_BK04_4E_H _PK_H_(0x04, 0x4E) ++#define REG_COMB_BK04_4F_L _PK_L_(0x04, 0x4F) ++#define REG_COMB_BK04_4F_H _PK_H_(0x04, 0x4F) ++#define REG_COMB_BK04_50_L _PK_L_(0x04, 0x50) ++#define REG_COMB_BK04_50_H _PK_H_(0x04, 0x50) ++#define REG_COMB_BK04_51_L _PK_L_(0x04, 0x51) ++#define REG_COMB_BK04_51_H _PK_H_(0x04, 0x51) ++#define REG_COMB_BK04_52_L _PK_L_(0x04, 0x52) ++#define REG_COMB_BK04_52_H _PK_H_(0x04, 0x52) ++#define REG_COMB_BK04_53_L _PK_L_(0x04, 0x53) ++#define REG_COMB_BK04_53_H _PK_H_(0x04, 0x53) ++#define REG_COMB_BK04_54_L _PK_L_(0x04, 0x54) ++#define REG_COMB_BK04_54_H _PK_H_(0x04, 0x54) ++#define REG_COMB_BK04_55_L _PK_L_(0x04, 0x55) ++#define REG_COMB_BK04_55_H _PK_H_(0x04, 0x55) ++#define REG_COMB_BK04_56_L _PK_L_(0x04, 0x56) ++#define REG_COMB_BK04_56_H _PK_H_(0x04, 0x56) ++#define REG_COMB_BK04_57_L _PK_L_(0x04, 0x57) ++#define REG_COMB_BK04_57_H _PK_H_(0x04, 0x57) ++#define REG_COMB_BK04_58_L _PK_L_(0x04, 0x58) ++#define REG_COMB_BK04_58_H _PK_H_(0x04, 0x58) ++#define REG_COMB_BK04_59_L _PK_L_(0x04, 0x59) ++#define REG_COMB_BK04_59_H _PK_H_(0x04, 0x59) ++#define REG_COMB_BK04_5A_L _PK_L_(0x04, 0x5A) ++#define REG_COMB_BK04_5A_H _PK_H_(0x04, 0x5A) ++#define REG_COMB_BK04_5B_L _PK_L_(0x04, 0x5B) ++#define REG_COMB_BK04_5B_H _PK_H_(0x04, 0x5B) ++#define REG_COMB_BK04_5C_L _PK_L_(0x04, 0x5C) ++#define REG_COMB_BK04_5C_H _PK_H_(0x04, 0x5C) ++#define REG_COMB_BK04_5D_L _PK_L_(0x04, 0x5D) ++#define REG_COMB_BK04_5D_H _PK_H_(0x04, 0x5D) ++#define REG_COMB_BK04_5E_L _PK_L_(0x04, 0x5E) ++#define REG_COMB_BK04_5E_H _PK_H_(0x04, 0x5E) ++#define REG_COMB_BK04_5F_L _PK_L_(0x04, 0x5F) ++#define REG_COMB_BK04_5F_H _PK_H_(0x04, 0x5F) ++#define REG_COMB_BK04_60_L _PK_L_(0x04, 0x60) ++#define REG_COMB_BK04_60_H _PK_H_(0x04, 0x60) ++#define REG_COMB_BK04_61_L _PK_L_(0x04, 0x61) ++#define REG_COMB_BK04_61_H _PK_H_(0x04, 0x61) ++#define REG_COMB_BK04_62_L _PK_L_(0x04, 0x62) ++#define REG_COMB_BK04_62_H _PK_H_(0x04, 0x62) ++#define REG_COMB_BK04_63_L _PK_L_(0x04, 0x63) ++#define REG_COMB_BK04_63_H _PK_H_(0x04, 0x63) ++#define REG_COMB_BK04_64_L _PK_L_(0x04, 0x64) ++#define REG_COMB_BK04_64_H _PK_H_(0x04, 0x64) ++#define REG_COMB_BK04_65_L _PK_L_(0x04, 0x65) ++#define REG_COMB_BK04_65_H _PK_H_(0x04, 0x65) ++#define REG_COMB_BK04_66_L _PK_L_(0x04, 0x66) ++#define REG_COMB_BK04_66_H _PK_H_(0x04, 0x66) ++#define REG_COMB_BK04_67_L _PK_L_(0x04, 0x67) ++#define REG_COMB_BK04_67_H _PK_H_(0x04, 0x67) ++#define REG_COMB_BK04_68_L _PK_L_(0x04, 0x68) ++#define REG_COMB_BK04_68_H _PK_H_(0x04, 0x68) ++#define REG_COMB_BK04_69_L _PK_L_(0x04, 0x69) ++#define REG_COMB_BK04_69_H _PK_H_(0x04, 0x69) ++#define REG_COMB_BK04_6A_L _PK_L_(0x04, 0x6A) ++#define REG_COMB_BK04_6A_H _PK_H_(0x04, 0x6A) ++#define REG_COMB_BK04_6B_L _PK_L_(0x04, 0x6B) ++#define REG_COMB_BK04_6B_H _PK_H_(0x04, 0x6B) ++#define REG_COMB_BK04_6C_L _PK_L_(0x04, 0x6C) ++#define REG_COMB_BK04_6C_H _PK_H_(0x04, 0x6C) ++#define REG_COMB_BK04_6D_L _PK_L_(0x04, 0x6D) ++#define REG_COMB_BK04_6D_H _PK_H_(0x04, 0x6D) ++#define REG_COMB_BK04_6E_L _PK_L_(0x04, 0x6E) ++#define REG_COMB_BK04_6E_H _PK_H_(0x04, 0x6E) ++#define REG_COMB_BK04_6F_L _PK_L_(0x04, 0x6F) ++#define REG_COMB_BK04_6F_H _PK_H_(0x04, 0x6F) ++#define REG_COMB_BK04_70_L _PK_L_(0x04, 0x70) ++#define REG_COMB_BK04_70_H _PK_H_(0x04, 0x70) ++#define REG_COMB_BK04_71_L _PK_L_(0x04, 0x71) ++#define REG_COMB_BK04_71_H _PK_H_(0x04, 0x71) ++#define REG_COMB_BK04_72_L _PK_L_(0x04, 0x72) ++#define REG_COMB_BK04_72_H _PK_H_(0x04, 0x72) ++#define REG_COMB_BK04_73_L _PK_L_(0x04, 0x73) ++#define REG_COMB_BK04_73_H _PK_H_(0x04, 0x73) ++#define REG_COMB_BK04_74_L _PK_L_(0x04, 0x74) ++#define REG_COMB_BK04_74_H _PK_H_(0x04, 0x74) ++#define REG_COMB_BK04_75_L _PK_L_(0x04, 0x75) ++#define REG_COMB_BK04_75_H _PK_H_(0x04, 0x75) ++#define REG_COMB_BK04_76_L _PK_L_(0x04, 0x76) ++#define REG_COMB_BK04_76_H _PK_H_(0x04, 0x76) ++#define REG_COMB_BK04_77_L _PK_L_(0x04, 0x77) ++#define REG_COMB_BK04_77_H _PK_H_(0x04, 0x77) ++#define REG_COMB_BK04_78_L _PK_L_(0x04, 0x78) ++#define REG_COMB_BK04_78_H _PK_H_(0x04, 0x78) ++#define REG_COMB_BK04_79_L _PK_L_(0x04, 0x79) ++#define REG_COMB_BK04_79_H _PK_H_(0x04, 0x79) ++#define REG_COMB_BK04_7A_L _PK_L_(0x04, 0x7A) ++#define REG_COMB_BK04_7A_H _PK_H_(0x04, 0x7A) ++#define REG_COMB_BK04_7B_L _PK_L_(0x04, 0x7B) ++#define REG_COMB_BK04_7B_H _PK_H_(0x04, 0x7B) ++#define REG_COMB_BK04_7C_L _PK_L_(0x04, 0x7C) ++#define REG_COMB_BK04_7C_H _PK_H_(0x04, 0x7C) ++#define REG_COMB_BK04_7D_L _PK_L_(0x04, 0x7D) ++#define REG_COMB_BK04_7D_H _PK_H_(0x04, 0x7D) ++#define REG_COMB_BK04_7E_L _PK_L_(0x04, 0x7E) ++#define REG_COMB_BK04_7E_H _PK_H_(0x04, 0x7E) ++#define REG_COMB_BK04_7F_L _PK_L_(0x04, 0x7F) ++#define REG_COMB_BK04_7F_H _PK_H_(0x04, 0x7F) ++#define REG_COMB_BK05_00_L _PK_L_(0x05, 0x00) ++#define REG_COMB_BK05_00_H _PK_H_(0x05, 0x00) ++#define REG_COMB_BK05_01_L _PK_L_(0x05, 0x01) ++#define REG_COMB_BK05_01_H _PK_H_(0x05, 0x01) ++#define REG_COMB_BK05_02_L _PK_L_(0x05, 0x02) ++#define REG_COMB_BK05_02_H _PK_H_(0x05, 0x02) ++#define REG_COMB_BK05_03_L _PK_L_(0x05, 0x03) ++#define REG_COMB_BK05_03_H _PK_H_(0x05, 0x03) ++#define REG_COMB_BK05_04_L _PK_L_(0x05, 0x04) ++#define REG_COMB_BK05_04_H _PK_H_(0x05, 0x04) ++#define REG_COMB_BK05_05_L _PK_L_(0x05, 0x05) ++#define REG_COMB_BK05_05_H _PK_H_(0x05, 0x05) ++#define REG_COMB_BK05_06_L _PK_L_(0x05, 0x06) ++#define REG_COMB_BK05_06_H _PK_H_(0x05, 0x06) ++#define REG_COMB_BK05_07_L _PK_L_(0x05, 0x07) ++#define REG_COMB_BK05_07_H _PK_H_(0x05, 0x07) ++#define REG_COMB_BK05_08_L _PK_L_(0x05, 0x08) ++#define REG_COMB_BK05_08_H _PK_H_(0x05, 0x08) ++#define REG_COMB_BK05_09_L _PK_L_(0x05, 0x09) ++#define REG_COMB_BK05_09_H _PK_H_(0x05, 0x09) ++#define REG_COMB_BK05_0A_L _PK_L_(0x05, 0x0A) ++#define REG_COMB_BK05_0A_H _PK_H_(0x05, 0x0A) ++#define REG_COMB_BK05_0B_L _PK_L_(0x05, 0x0B) ++#define REG_COMB_BK05_0B_H _PK_H_(0x05, 0x0B) ++#define REG_COMB_BK05_0C_L _PK_L_(0x05, 0x0C) ++#define REG_COMB_BK05_0C_H _PK_H_(0x05, 0x0C) ++#define REG_COMB_BK05_0D_L _PK_L_(0x05, 0x0D) ++#define REG_COMB_BK05_0D_H _PK_H_(0x05, 0x0D) ++#define REG_COMB_BK05_0E_L _PK_L_(0x05, 0x0E) ++#define REG_COMB_BK05_0E_H _PK_H_(0x05, 0x0E) ++#define REG_COMB_BK05_0F_L _PK_L_(0x05, 0x0F) ++#define REG_COMB_BK05_0F_H _PK_H_(0x05, 0x0F) ++#define REG_COMB_BK05_10_L _PK_L_(0x05, 0x10) ++#define REG_COMB_BK05_10_H _PK_H_(0x05, 0x10) ++#define REG_COMB_BK05_11_L _PK_L_(0x05, 0x11) ++#define REG_COMB_BK05_11_H _PK_H_(0x05, 0x11) ++#define REG_COMB_BK05_12_L _PK_L_(0x05, 0x12) ++#define REG_COMB_BK05_12_H _PK_H_(0x05, 0x12) ++#define REG_COMB_BK05_13_L _PK_L_(0x05, 0x13) ++#define REG_COMB_BK05_13_H _PK_H_(0x05, 0x13) ++#define REG_COMB_BK05_14_L _PK_L_(0x05, 0x14) ++#define REG_COMB_BK05_14_H _PK_H_(0x05, 0x14) ++#define REG_COMB_BK05_15_L _PK_L_(0x05, 0x15) ++#define REG_COMB_BK05_15_H _PK_H_(0x05, 0x15) ++#define REG_COMB_BK05_16_L _PK_L_(0x05, 0x16) ++#define REG_COMB_BK05_16_H _PK_H_(0x05, 0x16) ++#define REG_COMB_BK05_17_L _PK_L_(0x05, 0x17) ++#define REG_COMB_BK05_17_H _PK_H_(0x05, 0x17) ++#define REG_COMB_BK05_18_L _PK_L_(0x05, 0x18) ++#define REG_COMB_BK05_18_H _PK_H_(0x05, 0x18) ++#define REG_COMB_BK05_19_L _PK_L_(0x05, 0x19) ++#define REG_COMB_BK05_19_H _PK_H_(0x05, 0x19) ++#define REG_COMB_BK05_1A_L _PK_L_(0x05, 0x1A) ++#define REG_COMB_BK05_1A_H _PK_H_(0x05, 0x1A) ++#define REG_COMB_BK05_1B_L _PK_L_(0x05, 0x1B) ++#define REG_COMB_BK05_1B_H _PK_H_(0x05, 0x1B) ++#define REG_COMB_BK05_1C_L _PK_L_(0x05, 0x1C) ++#define REG_COMB_BK05_1C_H _PK_H_(0x05, 0x1C) ++#define REG_COMB_BK05_1D_L _PK_L_(0x05, 0x1D) ++#define REG_COMB_BK05_1D_H _PK_H_(0x05, 0x1D) ++#define REG_COMB_BK05_1E_L _PK_L_(0x05, 0x1E) ++#define REG_COMB_BK05_1E_H _PK_H_(0x05, 0x1E) ++#define REG_COMB_BK05_1F_L _PK_L_(0x05, 0x1F) ++#define REG_COMB_BK05_1F_H _PK_H_(0x05, 0x1F) ++#define REG_COMB_BK05_20_L _PK_L_(0x05, 0x20) ++#define REG_COMB_BK05_20_H _PK_H_(0x05, 0x20) ++#define REG_COMB_BK05_21_L _PK_L_(0x05, 0x21) ++#define REG_COMB_BK05_21_H _PK_H_(0x05, 0x21) ++#define REG_COMB_BK05_22_L _PK_L_(0x05, 0x22) ++#define REG_COMB_BK05_22_H _PK_H_(0x05, 0x22) ++#define REG_COMB_BK05_23_L _PK_L_(0x05, 0x23) ++#define REG_COMB_BK05_23_H _PK_H_(0x05, 0x23) ++#define REG_COMB_BK05_24_L _PK_L_(0x05, 0x24) ++#define REG_COMB_BK05_24_H _PK_H_(0x05, 0x24) ++#define REG_COMB_BK05_25_L _PK_L_(0x05, 0x25) ++#define REG_COMB_BK05_25_H _PK_H_(0x05, 0x25) ++#define REG_COMB_BK05_26_L _PK_L_(0x05, 0x26) ++#define REG_COMB_BK05_26_H _PK_H_(0x05, 0x26) ++#define REG_COMB_BK05_27_L _PK_L_(0x05, 0x27) ++#define REG_COMB_BK05_27_H _PK_H_(0x05, 0x27) ++#define REG_COMB_BK05_28_L _PK_L_(0x05, 0x28) ++#define REG_COMB_BK05_28_H _PK_H_(0x05, 0x28) ++#define REG_COMB_BK05_29_L _PK_L_(0x05, 0x29) ++#define REG_COMB_BK05_29_H _PK_H_(0x05, 0x29) ++#define REG_COMB_BK05_2A_L _PK_L_(0x05, 0x2A) ++#define REG_COMB_BK05_2A_H _PK_H_(0x05, 0x2A) ++#define REG_COMB_BK05_2B_L _PK_L_(0x05, 0x2B) ++#define REG_COMB_BK05_2B_H _PK_H_(0x05, 0x2B) ++#define REG_COMB_BK05_2C_L _PK_L_(0x05, 0x2C) ++#define REG_COMB_BK05_2C_H _PK_H_(0x05, 0x2C) ++#define REG_COMB_BK05_2D_L _PK_L_(0x05, 0x2D) ++#define REG_COMB_BK05_2D_H _PK_H_(0x05, 0x2D) ++#define REG_COMB_BK05_2E_L _PK_L_(0x05, 0x2E) ++#define REG_COMB_BK05_2E_H _PK_H_(0x05, 0x2E) ++#define REG_COMB_BK05_2F_L _PK_L_(0x05, 0x2F) ++#define REG_COMB_BK05_2F_H _PK_H_(0x05, 0x2F) ++#define REG_COMB_BK05_30_L _PK_L_(0x05, 0x30) ++#define REG_COMB_BK05_30_H _PK_H_(0x05, 0x30) ++#define REG_COMB_BK05_31_L _PK_L_(0x05, 0x31) ++#define REG_COMB_BK05_31_H _PK_H_(0x05, 0x31) ++#define REG_COMB_BK05_32_L _PK_L_(0x05, 0x32) ++#define REG_COMB_BK05_32_H _PK_H_(0x05, 0x32) ++#define REG_COMB_BK05_33_L _PK_L_(0x05, 0x33) ++#define REG_COMB_BK05_33_H _PK_H_(0x05, 0x33) ++#define REG_COMB_BK05_34_L _PK_L_(0x05, 0x34) ++#define REG_COMB_BK05_34_H _PK_H_(0x05, 0x34) ++#define REG_COMB_BK05_35_L _PK_L_(0x05, 0x35) ++#define REG_COMB_BK05_35_H _PK_H_(0x05, 0x35) ++#define REG_COMB_BK05_36_L _PK_L_(0x05, 0x36) ++#define REG_COMB_BK05_36_H _PK_H_(0x05, 0x36) ++#define REG_COMB_BK05_37_L _PK_L_(0x05, 0x37) ++#define REG_COMB_BK05_37_H _PK_H_(0x05, 0x37) ++#define REG_COMB_BK05_38_L _PK_L_(0x05, 0x38) ++#define REG_COMB_BK05_38_H _PK_H_(0x05, 0x38) ++#define REG_COMB_BK05_39_L _PK_L_(0x05, 0x39) ++#define REG_COMB_BK05_39_H _PK_H_(0x05, 0x39) ++#define REG_COMB_BK05_3A_L _PK_L_(0x05, 0x3A) ++#define REG_COMB_BK05_3A_H _PK_H_(0x05, 0x3A) ++#define REG_COMB_BK05_3B_L _PK_L_(0x05, 0x3B) ++#define REG_COMB_BK05_3B_H _PK_H_(0x05, 0x3B) ++#define REG_COMB_BK05_3C_L _PK_L_(0x05, 0x3C) ++#define REG_COMB_BK05_3C_H _PK_H_(0x05, 0x3C) ++#define REG_COMB_BK05_3D_L _PK_L_(0x05, 0x3D) ++#define REG_COMB_BK05_3D_H _PK_H_(0x05, 0x3D) ++#define REG_COMB_BK05_3E_L _PK_L_(0x05, 0x3E) ++#define REG_COMB_BK05_3E_H _PK_H_(0x05, 0x3E) ++#define REG_COMB_BK05_3F_L _PK_L_(0x05, 0x3F) ++#define REG_COMB_BK05_3F_H _PK_H_(0x05, 0x3F) ++#define REG_COMB_BK05_40_L _PK_L_(0x05, 0x40) ++#define REG_COMB_BK05_40_H _PK_H_(0x05, 0x40) ++#define REG_COMB_BK05_41_L _PK_L_(0x05, 0x41) ++#define REG_COMB_BK05_41_H _PK_H_(0x05, 0x41) ++#define REG_COMB_BK05_42_L _PK_L_(0x05, 0x42) ++#define REG_COMB_BK05_42_H _PK_H_(0x05, 0x42) ++#define REG_COMB_BK05_43_L _PK_L_(0x05, 0x43) ++#define REG_COMB_BK05_43_H _PK_H_(0x05, 0x43) ++#define REG_COMB_BK05_44_L _PK_L_(0x05, 0x44) ++#define REG_COMB_BK05_44_H _PK_H_(0x05, 0x44) ++#define REG_COMB_BK05_45_L _PK_L_(0x05, 0x45) ++#define REG_COMB_BK05_45_H _PK_H_(0x05, 0x45) ++#define REG_COMB_BK05_46_L _PK_L_(0x05, 0x46) ++#define REG_COMB_BK05_46_H _PK_H_(0x05, 0x46) ++#define REG_COMB_BK05_47_L _PK_L_(0x05, 0x47) ++#define REG_COMB_BK05_47_H _PK_H_(0x05, 0x47) ++#define REG_COMB_BK05_48_L _PK_L_(0x05, 0x48) ++#define REG_COMB_BK05_48_H _PK_H_(0x05, 0x48) ++#define REG_COMB_BK05_49_L _PK_L_(0x05, 0x49) ++#define REG_COMB_BK05_49_H _PK_H_(0x05, 0x49) ++#define REG_COMB_BK05_4A_L _PK_L_(0x05, 0x4A) ++#define REG_COMB_BK05_4A_H _PK_H_(0x05, 0x4A) ++#define REG_COMB_BK05_4B_L _PK_L_(0x05, 0x4B) ++#define REG_COMB_BK05_4B_H _PK_H_(0x05, 0x4B) ++#define REG_COMB_BK05_4C_L _PK_L_(0x05, 0x4C) ++#define REG_COMB_BK05_4C_H _PK_H_(0x05, 0x4C) ++#define REG_COMB_BK05_4D_L _PK_L_(0x05, 0x4D) ++#define REG_COMB_BK05_4D_H _PK_H_(0x05, 0x4D) ++#define REG_COMB_BK05_4E_L _PK_L_(0x05, 0x4E) ++#define REG_COMB_BK05_4E_H _PK_H_(0x05, 0x4E) ++#define REG_COMB_BK05_4F_L _PK_L_(0x05, 0x4F) ++#define REG_COMB_BK05_4F_H _PK_H_(0x05, 0x4F) ++#define REG_COMB_BK05_50_L _PK_L_(0x05, 0x50) ++#define REG_COMB_BK05_50_H _PK_H_(0x05, 0x50) ++#define REG_COMB_BK05_51_L _PK_L_(0x05, 0x51) ++#define REG_COMB_BK05_51_H _PK_H_(0x05, 0x51) ++#define REG_COMB_BK05_52_L _PK_L_(0x05, 0x52) ++#define REG_COMB_BK05_52_H _PK_H_(0x05, 0x52) ++#define REG_COMB_BK05_53_L _PK_L_(0x05, 0x53) ++#define REG_COMB_BK05_53_H _PK_H_(0x05, 0x53) ++#define REG_COMB_BK05_54_L _PK_L_(0x05, 0x54) ++#define REG_COMB_BK05_54_H _PK_H_(0x05, 0x54) ++#define REG_COMB_BK05_55_L _PK_L_(0x05, 0x55) ++#define REG_COMB_BK05_55_H _PK_H_(0x05, 0x55) ++#define REG_COMB_BK05_56_L _PK_L_(0x05, 0x56) ++#define REG_COMB_BK05_56_H _PK_H_(0x05, 0x56) ++#define REG_COMB_BK05_57_L _PK_L_(0x05, 0x57) ++#define REG_COMB_BK05_57_H _PK_H_(0x05, 0x57) ++#define REG_COMB_BK05_58_L _PK_L_(0x05, 0x58) ++#define REG_COMB_BK05_58_H _PK_H_(0x05, 0x58) ++#define REG_COMB_BK05_59_L _PK_L_(0x05, 0x59) ++#define REG_COMB_BK05_59_H _PK_H_(0x05, 0x59) ++#define REG_COMB_BK05_5A_L _PK_L_(0x05, 0x5A) ++#define REG_COMB_BK05_5A_H _PK_H_(0x05, 0x5A) ++#define REG_COMB_BK05_5B_L _PK_L_(0x05, 0x5B) ++#define REG_COMB_BK05_5B_H _PK_H_(0x05, 0x5B) ++#define REG_COMB_BK05_5C_L _PK_L_(0x05, 0x5C) ++#define REG_COMB_BK05_5C_H _PK_H_(0x05, 0x5C) ++#define REG_COMB_BK05_5D_L _PK_L_(0x05, 0x5D) ++#define REG_COMB_BK05_5D_H _PK_H_(0x05, 0x5D) ++#define REG_COMB_BK05_5E_L _PK_L_(0x05, 0x5E) ++#define REG_COMB_BK05_5E_H _PK_H_(0x05, 0x5E) ++#define REG_COMB_BK05_5F_L _PK_L_(0x05, 0x5F) ++#define REG_COMB_BK05_5F_H _PK_H_(0x05, 0x5F) ++#define REG_COMB_BK05_60_L _PK_L_(0x05, 0x60) ++#define REG_COMB_BK05_60_H _PK_H_(0x05, 0x60) ++#define REG_COMB_BK05_61_L _PK_L_(0x05, 0x61) ++#define REG_COMB_BK05_61_H _PK_H_(0x05, 0x61) ++#define REG_COMB_BK05_62_L _PK_L_(0x05, 0x62) ++#define REG_COMB_BK05_62_H _PK_H_(0x05, 0x62) ++#define REG_COMB_BK05_63_L _PK_L_(0x05, 0x63) ++#define REG_COMB_BK05_63_H _PK_H_(0x05, 0x63) ++#define REG_COMB_BK05_64_L _PK_L_(0x05, 0x64) ++#define REG_COMB_BK05_64_H _PK_H_(0x05, 0x64) ++#define REG_COMB_BK05_65_L _PK_L_(0x05, 0x65) ++#define REG_COMB_BK05_65_H _PK_H_(0x05, 0x65) ++#define REG_COMB_BK05_66_L _PK_L_(0x05, 0x66) ++#define REG_COMB_BK05_66_H _PK_H_(0x05, 0x66) ++#define REG_COMB_BK05_67_L _PK_L_(0x05, 0x67) ++#define REG_COMB_BK05_67_H _PK_H_(0x05, 0x67) ++#define REG_COMB_BK05_68_L _PK_L_(0x05, 0x68) ++#define REG_COMB_BK05_68_H _PK_H_(0x05, 0x68) ++#define REG_COMB_BK05_69_L _PK_L_(0x05, 0x69) ++#define REG_COMB_BK05_69_H _PK_H_(0x05, 0x69) ++#define REG_COMB_BK05_6A_L _PK_L_(0x05, 0x6A) ++#define REG_COMB_BK05_6A_H _PK_H_(0x05, 0x6A) ++#define REG_COMB_BK05_6B_L _PK_L_(0x05, 0x6B) ++#define REG_COMB_BK05_6B_H _PK_H_(0x05, 0x6B) ++#define REG_COMB_BK05_6C_L _PK_L_(0x05, 0x6C) ++#define REG_COMB_BK05_6C_H _PK_H_(0x05, 0x6C) ++#define REG_COMB_BK05_6D_L _PK_L_(0x05, 0x6D) ++#define REG_COMB_BK05_6D_H _PK_H_(0x05, 0x6D) ++#define REG_COMB_BK05_6E_L _PK_L_(0x05, 0x6E) ++#define REG_COMB_BK05_6E_H _PK_H_(0x05, 0x6E) ++#define REG_COMB_BK05_6F_L _PK_L_(0x05, 0x6F) ++#define REG_COMB_BK05_6F_H _PK_H_(0x05, 0x6F) ++#define REG_COMB_BK05_70_L _PK_L_(0x05, 0x70) ++#define REG_COMB_BK05_70_H _PK_H_(0x05, 0x70) ++#define REG_COMB_BK05_71_L _PK_L_(0x05, 0x71) ++#define REG_COMB_BK05_71_H _PK_H_(0x05, 0x71) ++#define REG_COMB_BK05_72_L _PK_L_(0x05, 0x72) ++#define REG_COMB_BK05_72_H _PK_H_(0x05, 0x72) ++#define REG_COMB_BK05_73_L _PK_L_(0x05, 0x73) ++#define REG_COMB_BK05_73_H _PK_H_(0x05, 0x73) ++#define REG_COMB_BK05_74_L _PK_L_(0x05, 0x74) ++#define REG_COMB_BK05_74_H _PK_H_(0x05, 0x74) ++#define REG_COMB_BK05_75_L _PK_L_(0x05, 0x75) ++#define REG_COMB_BK05_75_H _PK_H_(0x05, 0x75) ++#define REG_COMB_BK05_76_L _PK_L_(0x05, 0x76) ++#define REG_COMB_BK05_76_H _PK_H_(0x05, 0x76) ++#define REG_COMB_BK05_77_L _PK_L_(0x05, 0x77) ++#define REG_COMB_BK05_77_H _PK_H_(0x05, 0x77) ++#define REG_COMB_BK05_78_L _PK_L_(0x05, 0x78) ++#define REG_COMB_BK05_78_H _PK_H_(0x05, 0x78) ++#define REG_COMB_BK05_79_L _PK_L_(0x05, 0x79) ++#define REG_COMB_BK05_79_H _PK_H_(0x05, 0x79) ++#define REG_COMB_BK05_7A_L _PK_L_(0x05, 0x7A) ++#define REG_COMB_BK05_7A_H _PK_H_(0x05, 0x7A) ++#define REG_COMB_BK05_7B_L _PK_L_(0x05, 0x7B) ++#define REG_COMB_BK05_7B_H _PK_H_(0x05, 0x7B) ++#define REG_COMB_BK05_7C_L _PK_L_(0x05, 0x7C) ++#define REG_COMB_BK05_7C_H _PK_H_(0x05, 0x7C) ++#define REG_COMB_BK05_7D_L _PK_L_(0x05, 0x7D) ++#define REG_COMB_BK05_7D_H _PK_H_(0x05, 0x7D) ++#define REG_COMB_BK05_7E_L _PK_L_(0x05, 0x7E) ++#define REG_COMB_BK05_7E_H _PK_H_(0x05, 0x7E) ++#define REG_COMB_BK05_7F_L _PK_L_(0x05, 0x7F) ++#define REG_COMB_BK05_7F_H _PK_H_(0x05, 0x7F) ++//---------------------------------------------- ++#define REG_BK2C_00_L 0x2C00 ++#define REG_BK2C_00_H 0x2C01 ++#define REG_BK2C_01_L 0x2C02 ++#define REG_BK2C_01_H 0x2C03 ++#define REG_BK2C_02_L 0x2C04 ++#define REG_BK2C_02_H 0x2C05 ++#define REG_BK2C_03_L 0x2C06 ++#define REG_BK2C_03_H 0x2C07 ++#define REG_BK2C_04_L 0x2C08 ++#define REG_BK2C_04_H 0x2C09 ++#define REG_BK2C_05_L 0x2C0A ++#define REG_BK2C_05_H 0x2C0B ++#define REG_BK2C_06_L 0x2C0C ++#define REG_BK2C_06_H 0x2C0D ++#define REG_BK2C_07_L 0x2C0E ++#define REG_BK2C_07_H 0x2C0F ++#define REG_BK2C_08_L 0x2C10 ++#define REG_BK2C_08_H 0x2C11 ++#define REG_BK2C_09_L 0x2C12 ++#define REG_BK2C_09_H 0x2C13 ++#define REG_BK2C_0A_L 0x2C14 ++#define REG_BK2C_0A_H 0x2C15 ++#define REG_BK2C_0B_L 0x2C16 ++#define REG_BK2C_0B_H 0x2C17 ++#define REG_BK2C_0C_L 0x2C18 ++#define REG_BK2C_0C_H 0x2C19 ++#define REG_BK2C_0D_L 0x2C1A ++#define REG_BK2C_0D_H 0x2C1B ++#define REG_BK2C_0E_L 0x2C1C ++#define REG_BK2C_0E_H 0x2C1D ++#define REG_BK2C_0F_L 0x2C1E ++#define REG_BK2C_0F_H 0x2C1F ++#define REG_BK2C_10_L 0x2C20 ++#define REG_BK2C_10_H 0x2C21 ++#define REG_BK2C_11_L 0x2C22 ++#define REG_BK2C_11_H 0x2C23 ++#define REG_BK2C_12_L 0x2C24 ++#define REG_BK2C_12_H 0x2C25 ++#define REG_BK2C_13_L 0x2C26 ++#define REG_BK2C_13_H 0x2C27 ++#define REG_BK2C_14_L 0x2C28 ++#define REG_BK2C_14_H 0x2C29 ++#define REG_BK2C_15_L 0x2C2A ++#define REG_BK2C_15_H 0x2C2B ++#define REG_BK2C_16_L 0x2C2C ++#define REG_BK2C_16_H 0x2C2D ++#define REG_BK2C_17_L 0x2C2E ++#define REG_BK2C_17_H 0x2C2F ++#define REG_BK2C_18_L 0x2C30 ++#define REG_BK2C_18_H 0x2C31 ++#define REG_BK2C_19_L 0x2C32 ++#define REG_BK2C_19_H 0x2C33 ++#define REG_BK2C_1A_L 0x2C34 ++#define REG_BK2C_1A_H 0x2C35 ++#define REG_BK2C_1B_L 0x2C36 ++#define REG_BK2C_1B_H 0x2C37 ++#define REG_BK2C_1C_L 0x2C38 ++#define REG_BK2C_1C_H 0x2C39 ++#define REG_BK2C_1D_L 0x2C3A ++#define REG_BK2C_1D_H 0x2C3B ++#define REG_BK2C_1E_L 0x2C3C ++#define REG_BK2C_1E_H 0x2C3D ++#define REG_BK2C_1F_L 0x2C3E ++#define REG_BK2C_1F_H 0x2C3F ++#define REG_BK2C_20_L 0x2C40 ++#define REG_BK2C_20_H 0x2C41 ++#define REG_BK2C_21_L 0x2C42 ++#define REG_BK2C_21_H 0x2C43 ++#define REG_BK2C_22_L 0x2C44 ++#define REG_BK2C_22_H 0x2C45 ++#define REG_BK2C_23_L 0x2C46 ++#define REG_BK2C_23_H 0x2C47 ++#define REG_BK2C_24_L 0x2C48 ++#define REG_BK2C_24_H 0x2C49 ++#define REG_BK2C_25_L 0x2C4A ++#define REG_BK2C_25_H 0x2C4B ++#define REG_BK2C_26_L 0x2C4C ++#define REG_BK2C_26_H 0x2C4D ++#define REG_BK2C_27_L 0x2C4E ++#define REG_BK2C_27_H 0x2C4F ++#define REG_BK2C_28_L 0x2C50 ++#define REG_BK2C_28_H 0x2C51 ++#define REG_BK2C_29_L 0x2C52 ++#define REG_BK2C_29_H 0x2C53 ++#define REG_BK2C_2A_L 0x2C54 ++#define REG_BK2C_2A_H 0x2C55 ++#define REG_BK2C_2B_L 0x2C56 ++#define REG_BK2C_2B_H 0x2C57 ++#define REG_BK2C_2C_L 0x2C58 ++#define REG_BK2C_2C_H 0x2C59 ++#define REG_BK2C_2D_L 0x2C5A ++#define REG_BK2C_2D_H 0x2C5B ++#define REG_BK2C_2E_L 0x2C5C ++#define REG_BK2C_2E_H 0x2C5D ++#define REG_BK2C_2F_L 0x2C5E ++#define REG_BK2C_2F_H 0x2C5F ++#define REG_BK2C_30_L 0x2C60 ++#define REG_BK2C_30_H 0x2C61 ++#define REG_BK2C_31_L 0x2C62 ++#define REG_BK2C_31_H 0x2C63 ++#define REG_BK2C_32_L 0x2C64 ++#define REG_BK2C_32_H 0x2C65 ++#define REG_BK2C_33_L 0x2C66 ++#define REG_BK2C_33_H 0x2C67 ++#define REG_BK2C_34_L 0x2C68 ++#define REG_BK2C_34_H 0x2C69 ++#define REG_BK2C_35_L 0x2C6A ++#define REG_BK2C_35_H 0x2C6B ++#define REG_BK2C_36_L 0x2C6C ++#define REG_BK2C_36_H 0x2C6D ++#define REG_BK2C_37_L 0x2C6E ++#define REG_BK2C_37_H 0x2C6F ++#define REG_BK2C_38_L 0x2C70 ++#define REG_BK2C_38_H 0x2C71 ++#define REG_BK2C_39_L 0x2C72 ++#define REG_BK2C_39_H 0x2C73 ++#define REG_BK2C_3A_L 0x2C74 ++#define REG_BK2C_3A_H 0x2C75 ++#define REG_BK2C_3B_L 0x2C76 ++#define REG_BK2C_3B_H 0x2C77 ++#define REG_BK2C_3C_L 0x2C78 ++#define REG_BK2C_3C_H 0x2C79 ++#define REG_BK2C_3D_L 0x2C7A ++#define REG_BK2C_3D_H 0x2C7B ++#define REG_BK2C_3E_L 0x2C7C ++#define REG_BK2C_3E_H 0x2C7D ++#define REG_BK2C_3F_L 0x2C7E ++#define REG_BK2C_3F_H 0x2C7F ++#define REG_BK2C_40_L 0x2C80 ++#define REG_BK2C_40_H 0x2C81 ++#define REG_BK2C_41_L 0x2C82 ++#define REG_BK2C_41_H 0x2C83 ++#define REG_BK2C_42_L 0x2C84 ++#define REG_BK2C_42_H 0x2C85 ++#define REG_BK2C_43_L 0x2C86 ++#define REG_BK2C_43_H 0x2C87 ++#define REG_BK2C_44_L 0x2C88 ++#define REG_BK2C_44_H 0x2C89 ++#define REG_BK2C_45_L 0x2C8A ++#define REG_BK2C_45_H 0x2C8B ++#define REG_BK2C_46_L 0x2C8C ++#define REG_BK2C_46_H 0x2C8D ++#define REG_BK2C_47_L 0x2C8E ++#define REG_BK2C_47_H 0x2C8F ++#define REG_BK2C_48_L 0x2C90 ++#define REG_BK2C_48_H 0x2C91 ++#define REG_BK2C_49_L 0x2C92 ++#define REG_BK2C_49_H 0x2C93 ++#define REG_BK2C_4A_L 0x2C94 ++#define REG_BK2C_4A_H 0x2C95 ++#define REG_BK2C_4B_L 0x2C96 ++#define REG_BK2C_4B_H 0x2C97 ++#define REG_BK2C_4C_L 0x2C98 ++#define REG_BK2C_4C_H 0x2C99 ++#define REG_BK2C_4D_L 0x2C9A ++#define REG_BK2C_4D_H 0x2C9B ++#define REG_BK2C_4E_L 0x2C9C ++#define REG_BK2C_4E_H 0x2C9D ++#define REG_BK2C_4F_L 0x2C9E ++#define REG_BK2C_4F_H 0x2C9F ++#define REG_BK2C_50_L 0x2CA0 ++#define REG_BK2C_50_H 0x2CA1 ++#define REG_BK2C_51_L 0x2CA2 ++#define REG_BK2C_51_H 0x2CA3 ++#define REG_BK2C_52_L 0x2CA4 ++#define REG_BK2C_52_H 0x2CA5 ++#define REG_BK2C_53_L 0x2CA6 ++#define REG_BK2C_53_H 0x2CA7 ++#define REG_BK2C_54_L 0x2CA8 ++#define REG_BK2C_54_H 0x2CA9 ++#define REG_BK2C_55_L 0x2CAA ++#define REG_BK2C_55_H 0x2CAB ++#define REG_BK2C_56_L 0x2CAC ++#define REG_BK2C_56_H 0x2CAD ++#define REG_BK2C_57_L 0x2CAE ++#define REG_BK2C_57_H 0x2CAF ++#define REG_BK2C_58_L 0x2CB0 ++#define REG_BK2C_58_H 0x2CB1 ++#define REG_BK2C_59_L 0x2CB2 ++#define REG_BK2C_59_H 0x2CB3 ++#define REG_BK2C_5A_L 0x2CB4 ++#define REG_BK2C_5A_H 0x2CB5 ++#define REG_BK2C_5B_L 0x2CB6 ++#define REG_BK2C_5B_H 0x2CB7 ++#define REG_BK2C_5C_L 0x2CB8 ++#define REG_BK2C_5C_H 0x2CB9 ++#define REG_BK2C_5D_L 0x2CBA ++#define REG_BK2C_5D_H 0x2CBB ++#define REG_BK2C_5E_L 0x2CBC ++#define REG_BK2C_5E_H 0x2CBD ++#define REG_BK2C_5F_L 0x2CBE ++#define REG_BK2C_5F_H 0x2CBF ++#define REG_BK2C_60_L 0x2CC0 ++#define REG_BK2C_60_H 0x2CC1 ++#define REG_BK2C_61_L 0x2CC2 ++#define REG_BK2C_61_H 0x2CC3 ++#define REG_BK2C_62_L 0x2CC4 ++#define REG_BK2C_62_H 0x2CC5 ++#define REG_BK2C_63_L 0x2CC6 ++#define REG_BK2C_63_H 0x2CC7 ++#define REG_BK2C_64_L 0x2CC8 ++#define REG_BK2C_64_H 0x2CC9 ++#define REG_BK2C_65_L 0x2CCA ++#define REG_BK2C_65_H 0x2CCB ++#define REG_BK2C_66_L 0x2CCC ++#define REG_BK2C_66_H 0x2CCD ++#define REG_BK2C_67_L 0x2CCE ++#define REG_BK2C_67_H 0x2CCF ++#define REG_BK2C_68_L 0x2CD0 ++#define REG_BK2C_68_H 0x2CD1 ++#define REG_BK2C_69_L 0x2CD2 ++#define REG_BK2C_69_H 0x2CD3 ++#define REG_BK2C_6A_L 0x2CD4 ++#define REG_BK2C_6A_H 0x2CD5 ++#define REG_BK2C_6B_L 0x2CD6 ++#define REG_BK2C_6B_H 0x2CD7 ++#define REG_BK2C_6C_L 0x2CD8 ++#define REG_BK2C_6C_H 0x2CD9 ++#define REG_BK2C_6D_L 0x2CDA ++#define REG_BK2C_6D_H 0x2CDB ++#define REG_BK2C_6E_L 0x2CDC ++#define REG_BK2C_6E_H 0x2CDD ++#define REG_BK2C_6F_L 0x2CDE ++#define REG_BK2C_6F_H 0x2CDF ++#define REG_BK2C_70_L 0x2CE0 ++#define REG_BK2C_70_H 0x2CE1 ++#define REG_BK2C_71_L 0x2CE2 ++#define REG_BK2C_71_H 0x2CE3 ++#define REG_BK2C_72_L 0x2CE4 ++#define REG_BK2C_72_H 0x2CE5 ++#define REG_BK2C_73_L 0x2CE6 ++#define REG_BK2C_73_H 0x2CE7 ++#define REG_BK2C_74_L 0x2CE8 ++#define REG_BK2C_74_H 0x2CE9 ++#define REG_BK2C_75_L 0x2CEA ++#define REG_BK2C_75_H 0x2CEB ++#define REG_BK2C_76_L 0x2CEC ++#define REG_BK2C_76_H 0x2CED ++#define REG_BK2C_77_L 0x2CEE ++#define REG_BK2C_77_H 0x2CEF ++#define REG_BK2C_78_L 0x2CF0 ++#define REG_BK2C_78_H 0x2CF1 ++#define REG_BK2C_79_L 0x2CF2 ++#define REG_BK2C_79_H 0x2CF3 ++#define REG_BK2C_7A_L 0x2CF4 ++#define REG_BK2C_7A_H 0x2CF5 ++#define REG_BK2C_7B_L 0x2CF6 ++#define REG_BK2C_7B_H 0x2CF7 ++#define REG_BK2C_7C_L 0x2CF8 ++#define REG_BK2C_7C_H 0x2CF9 ++#define REG_BK2C_7D_L 0x2CFA ++#define REG_BK2C_7D_H 0x2CFB ++#define REG_BK2C_7E_L 0x2CFC ++#define REG_BK2C_7E_H 0x2CFD ++#define REG_BK2C_7F_L 0x2CFE ++#define REG_BK2C_7F_H 0x2CFF ++//---------------------------------------------- ++#define REG_BK38_00_L 0x3800 ++#define REG_BK38_00_H 0x3801 ++#define REG_BK38_01_L 0x3802 ++#define REG_BK38_01_H 0x3803 ++#define REG_BK38_02_L 0x3804 ++#define REG_BK38_02_H 0x3805 ++#define REG_BK38_03_L 0x3806 ++#define REG_BK38_03_H 0x3807 ++#define REG_BK38_04_L 0x3808 ++#define REG_BK38_04_H 0x3809 ++#define REG_BK38_05_L 0x380A ++#define REG_BK38_05_H 0x380B ++#define REG_BK38_06_L 0x380C ++#define REG_BK38_06_H 0x380D ++#define REG_BK38_07_L 0x380E ++#define REG_BK38_07_H 0x380F ++#define REG_BK38_08_L 0x3810 ++#define REG_BK38_08_H 0x3811 ++#define REG_BK38_09_L 0x3812 ++#define REG_BK38_09_H 0x3813 ++#define REG_BK38_0A_L 0x3814 ++#define REG_BK38_0A_H 0x3815 ++#define REG_BK38_0B_L 0x3816 ++#define REG_BK38_0B_H 0x3817 ++#define REG_BK38_0C_L 0x3818 ++#define REG_BK38_0C_H 0x3819 ++#define REG_BK38_0D_L 0x381A ++#define REG_BK38_0D_H 0x381B ++#define REG_BK38_0E_L 0x381C ++#define REG_BK38_0E_H 0x381D ++#define REG_BK38_0F_L 0x381E ++#define REG_BK38_0F_H 0x381F ++#define REG_BK38_10_L 0x3820 ++#define REG_BK38_10_H 0x3821 ++#define REG_BK38_11_L 0x3822 ++#define REG_BK38_11_H 0x3823 ++#define REG_BK38_12_L 0x3824 ++#define REG_BK38_12_H 0x3825 ++#define REG_BK38_13_L 0x3826 ++#define REG_BK38_13_H 0x3827 ++#define REG_BK38_14_L 0x3828 ++#define REG_BK38_14_H 0x3829 ++#define REG_BK38_15_L 0x382A ++#define REG_BK38_15_H 0x382B ++#define REG_BK38_16_L 0x382C ++#define REG_BK38_16_H 0x382D ++#define REG_BK38_17_L 0x382E ++#define REG_BK38_17_H 0x382F ++#define REG_BK38_18_L 0x3830 ++#define REG_BK38_18_H 0x3831 ++#define REG_BK38_19_L 0x3832 ++#define REG_BK38_19_H 0x3833 ++#define REG_BK38_1A_L 0x3834 ++#define REG_BK38_1A_H 0x3835 ++#define REG_BK38_1B_L 0x3836 ++#define REG_BK38_1B_H 0x3837 ++#define REG_BK38_1C_L 0x3838 ++#define REG_BK38_1C_H 0x3839 ++#define REG_BK38_1D_L 0x383A ++#define REG_BK38_1D_H 0x383B ++#define REG_BK38_1E_L 0x383C ++#define REG_BK38_1E_H 0x383D ++#define REG_BK38_1F_L 0x383E ++#define REG_BK38_1F_H 0x383F ++#define REG_BK38_20_L 0x3840 ++#define REG_BK38_20_H 0x3841 ++#define REG_BK38_21_L 0x3842 ++#define REG_BK38_21_H 0x3843 ++#define REG_BK38_22_L 0x3844 ++#define REG_BK38_22_H 0x3845 ++#define REG_BK38_23_L 0x3846 ++#define REG_BK38_23_H 0x3847 ++#define REG_BK38_24_L 0x3848 ++#define REG_BK38_24_H 0x3849 ++#define REG_BK38_25_L 0x384A ++#define REG_BK38_25_H 0x384B ++#define REG_BK38_26_L 0x384C ++#define REG_BK38_26_H 0x384D ++#define REG_BK38_27_L 0x384E ++#define REG_BK38_27_H 0x384F ++#define REG_BK38_28_L 0x3850 ++#define REG_BK38_28_H 0x3851 ++#define REG_BK38_29_L 0x3852 ++#define REG_BK38_29_H 0x3853 ++#define REG_BK38_2A_L 0x3854 ++#define REG_BK38_2A_H 0x3855 ++#define REG_BK38_2B_L 0x3856 ++#define REG_BK38_2B_H 0x3857 ++#define REG_BK38_2C_L 0x3858 ++#define REG_BK38_2C_H 0x3859 ++#define REG_BK38_2D_L 0x385A ++#define REG_BK38_2D_H 0x385B ++#define REG_BK38_2E_L 0x385C ++#define REG_BK38_2E_H 0x385D ++#define REG_BK38_2F_L 0x385E ++#define REG_BK38_2F_H 0x385F ++#define REG_BK38_30_L 0x3860 ++#define REG_BK38_30_H 0x3861 ++#define REG_BK38_31_L 0x3862 ++#define REG_BK38_31_H 0x3863 ++#define REG_BK38_32_L 0x3864 ++#define REG_BK38_32_H 0x3865 ++#define REG_BK38_33_L 0x3866 ++#define REG_BK38_33_H 0x3867 ++#define REG_BK38_34_L 0x3868 ++#define REG_BK38_34_H 0x3869 ++#define REG_BK38_35_L 0x386A ++#define REG_BK38_35_H 0x386B ++#define REG_BK38_36_L 0x386C ++#define REG_BK38_36_H 0x386D ++#define REG_BK38_37_L 0x386E ++#define REG_BK38_37_H 0x386F ++#define REG_BK38_38_L 0x3870 ++#define REG_BK38_38_H 0x3871 ++#define REG_BK38_39_L 0x3872 ++#define REG_BK38_39_H 0x3873 ++#define REG_BK38_3A_L 0x3874 ++#define REG_BK38_3A_H 0x3875 ++#define REG_BK38_3B_L 0x3876 ++#define REG_BK38_3B_H 0x3877 ++#define REG_BK38_3C_L 0x3878 ++#define REG_BK38_3C_H 0x3879 ++#define REG_BK38_3D_L 0x387A ++#define REG_BK38_3D_H 0x387B ++#define REG_BK38_3E_L 0x387C ++#define REG_BK38_3E_H 0x387D ++#define REG_BK38_3F_L 0x387E ++#define REG_BK38_3F_H 0x387F ++#define REG_BK38_40_L 0x3880 ++#define REG_BK38_40_H 0x3881 ++#define REG_BK38_41_L 0x3882 ++#define REG_BK38_41_H 0x3883 ++#define REG_BK38_42_L 0x3884 ++#define REG_BK38_42_H 0x3885 ++#define REG_BK38_43_L 0x3886 ++#define REG_BK38_43_H 0x3887 ++#define REG_BK38_44_L 0x3888 ++#define REG_BK38_44_H 0x3889 ++#define REG_BK38_45_L 0x388A ++#define REG_BK38_45_H 0x388B ++#define REG_BK38_46_L 0x388C ++#define REG_BK38_46_H 0x388D ++#define REG_BK38_47_L 0x388E ++#define REG_BK38_47_H 0x388F ++#define REG_BK38_48_L 0x3890 ++#define REG_BK38_48_H 0x3891 ++#define REG_BK38_49_L 0x3892 ++#define REG_BK38_49_H 0x3893 ++#define REG_BK38_4A_L 0x3894 ++#define REG_BK38_4A_H 0x3895 ++#define REG_BK38_4B_L 0x3896 ++#define REG_BK38_4B_H 0x3897 ++#define REG_BK38_4C_L 0x3898 ++#define REG_BK38_4C_H 0x3899 ++#define REG_BK38_4D_L 0x389A ++#define REG_BK38_4D_H 0x389B ++#define REG_BK38_4E_L 0x389C ++#define REG_BK38_4E_H 0x389D ++#define REG_BK38_4F_L 0x389E ++#define REG_BK38_4F_H 0x389F ++#define REG_BK38_50_L 0x38A0 ++#define REG_BK38_50_H 0x38A1 ++#define REG_BK38_51_L 0x38A2 ++#define REG_BK38_51_H 0x38A3 ++#define REG_BK38_52_L 0x38A4 ++#define REG_BK38_52_H 0x38A5 ++#define REG_BK38_53_L 0x38A6 ++#define REG_BK38_53_H 0x38A7 ++#define REG_BK38_54_L 0x38A8 ++#define REG_BK38_54_H 0x38A9 ++#define REG_BK38_55_L 0x38AA ++#define REG_BK38_55_H 0x38AB ++#define REG_BK38_56_L 0x38AC ++#define REG_BK38_56_H 0x38AD ++#define REG_BK38_57_L 0x38AE ++#define REG_BK38_57_H 0x38AF ++#define REG_BK38_58_L 0x38B0 ++#define REG_BK38_58_H 0x38B1 ++#define REG_BK38_59_L 0x38B2 ++#define REG_BK38_59_H 0x38B3 ++#define REG_BK38_5A_L 0x38B4 ++#define REG_BK38_5A_H 0x38B5 ++#define REG_BK38_5B_L 0x38B6 ++#define REG_BK38_5B_H 0x38B7 ++#define REG_BK38_5C_L 0x38B8 ++#define REG_BK38_5C_H 0x38B9 ++#define REG_BK38_5D_L 0x38BA ++#define REG_BK38_5D_H 0x38BB ++#define REG_BK38_5E_L 0x38BC ++#define REG_BK38_5E_H 0x38BD ++#define REG_BK38_5F_L 0x38BE ++#define REG_BK38_5F_H 0x38BF ++#define REG_BK38_60_L 0x38C0 ++#define REG_BK38_60_H 0x38C1 ++#define REG_BK38_61_L 0x38C2 ++#define REG_BK38_61_H 0x38C3 ++#define REG_BK38_62_L 0x38C4 ++#define REG_BK38_62_H 0x38C5 ++#define REG_BK38_63_L 0x38C6 ++#define REG_BK38_63_H 0x38C7 ++#define REG_BK38_64_L 0x38C8 ++#define REG_BK38_64_H 0x38C9 ++#define REG_BK38_65_L 0x38CA ++#define REG_BK38_65_H 0x38CB ++#define REG_BK38_66_L 0x38CC ++#define REG_BK38_66_H 0x38CD ++#define REG_BK38_67_L 0x38CE ++#define REG_BK38_67_H 0x38CF ++#define REG_BK38_68_L 0x38D0 ++#define REG_BK38_68_H 0x38D1 ++#define REG_BK38_69_L 0x38D2 ++#define REG_BK38_69_H 0x38D3 ++#define REG_BK38_6A_L 0x38D4 ++#define REG_BK38_6A_H 0x38D5 ++#define REG_BK38_6B_L 0x38D6 ++#define REG_BK38_6B_H 0x38D7 ++#define REG_BK38_6C_L 0x38D8 ++#define REG_BK38_6C_H 0x38D9 ++#define REG_BK38_6D_L 0x38DA ++#define REG_BK38_6D_H 0x38DB ++#define REG_BK38_6E_L 0x38DC ++#define REG_BK38_6E_H 0x38DD ++#define REG_BK38_6F_L 0x38DE ++#define REG_BK38_6F_H 0x38DF ++#define REG_BK38_70_L 0x38E0 ++#define REG_BK38_70_H 0x38E1 ++#define REG_BK38_71_L 0x38E2 ++#define REG_BK38_71_H 0x38E3 ++#define REG_BK38_72_L 0x38E4 ++#define REG_BK38_72_H 0x38E5 ++#define REG_BK38_73_L 0x38E6 ++#define REG_BK38_73_H 0x38E7 ++#define REG_BK38_74_L 0x38E8 ++#define REG_BK38_74_H 0x38E9 ++#define REG_BK38_75_L 0x38EA ++#define REG_BK38_75_H 0x38EB ++#define REG_BK38_76_L 0x38EC ++#define REG_BK38_76_H 0x38ED ++#define REG_BK38_77_L 0x38EE ++#define REG_BK38_77_H 0x38EF ++#define REG_BK38_78_L 0x38F0 ++#define REG_BK38_78_H 0x38F1 ++#define REG_BK38_79_L 0x38F2 ++#define REG_BK38_79_H 0x38F3 ++#define REG_BK38_7A_L 0x38F4 ++#define REG_BK38_7A_H 0x38F5 ++#define REG_BK38_7B_L 0x38F6 ++#define REG_BK38_7B_H 0x38F7 ++#define REG_BK38_7C_L 0x38F8 ++#define REG_BK38_7C_H 0x38F9 ++#define REG_BK38_7D_L 0x38FA ++#define REG_BK38_7D_H 0x38FB ++#define REG_BK38_7E_L 0x38FC ++#define REG_BK38_7E_H 0x38FD ++#define REG_BK38_7F_L 0x38FE ++#define REG_BK38_7F_H 0x38FF ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/drvPQ_Declare.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/drvPQ_Declare.h +new file mode 100644 +index 00000000..4479d296 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/drvPQ_Declare.h +@@ -0,0 +1,500 @@ ++#ifndef _DRVPQ_DECLARE_H ++#define _DRVPQ_DECLARE_H ++ ++ ++/////////////////////////////////////////////////////////////////////////////// ++// function macro ++// ++//### MDrv_PQ_DumpTable ++#define MDrv_PQ_DumpTable_(PQTABLE_NAME, pIP_Info) \ ++ MDrv_PQ_DumpTable_##PQTABLE_NAME(pIP_Info) ++ ++#define DECLARE_MDrv_PQ_DumpTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_DumpTable_##PQTABLE_NAME(EN_IP_Info* pIP_Info); ++ ++#define INSTALL_MDrv_PQ_DumpTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_DumpTable_##PQTABLE_NAME(EN_IP_Info* pIP_Info){ \ ++ _MDrv_PQ_DumpTable(pIP_Info); \ ++ } ++ ++ ++//### MDrv_PQ_GetIPNum ++#define MDrv_PQ_GetIPNum_(PQTABLE_NAME) \ ++ MDrv_PQ_GetIPNum_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_GetIPNum_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetIPNum_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_GetIPNum_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetIPNum_##PQTABLE_NAME(void){ \ ++ return _MDrv_PQ_GetIPNum(); \ ++ } ++ ++ ++//### MDrv_PQ_GetTableNum ++#define MDrv_PQ_GetTableNum_(PQTABLE_NAME, u8PQIPIdx) \ ++ MDrv_PQ_GetTableNum_##PQTABLE_NAME(u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetTableNum_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetTableNum_##PQTABLE_NAME(MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetTableNum_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetTableNum_##PQTABLE_NAME(MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetTableNum(u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_GetCurrentTableIndex ++#define MDrv_PQ_GetCurrentTableIndex_(PQTABLE_NAME, u8PQIPIdx) \ ++ MDrv_PQ_GetCurrentTableIndex_##PQTABLE_NAME(u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetCurrentTableIndex_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetCurrentTableIndex_##PQTABLE_NAME(MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetCurrentTableIndex_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetCurrentTableIndex_##PQTABLE_NAME(MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetCurrentTableIndex(u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_GetTableIndex ++#define MDrv_PQ_GetTableIndex_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_GetTableIndex_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetTableIndex_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetTableIndex_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetTableIndex_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetTableIndex_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetTableIndex(u16PQSrcType, u8PQIPIdx ); \ ++ } ++ ++ ++//### MDrv_PQ_GetTable ++#define MDrv_PQ_GetTable_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx) \ ++ MDrv_PQ_GetTable_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetTable_(PQTABLE_NAME) \ ++ extern EN_IP_Info MDrv_PQ_GetTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetTable_(PQTABLE_NAME) \ ++ EN_IP_Info MDrv_PQ_GetTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx){ \ ++ return _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_LoadTableData ++#define MDrv_PQ_LoadTableData_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx, pTable, u16TableSize) \ ++ MDrv_PQ_LoadTableData_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx, pTable, u16TableSize) ++ ++#define DECLARE_MDrv_PQ_LoadTableData_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTableData_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize); ++ ++#define INSTALL_MDrv_PQ_LoadTableData_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTableData_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize){ \ ++ _MDrv_PQ_LoadTableData(u8TabIdx, u8PQIPIdx, pTable, u16TableSize); \ ++ } ++ ++//### MDrv_PQ_LoadTable ++#define MDrv_PQ_LoadTable_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx) \ ++ MDrv_PQ_LoadTable_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_LoadTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_LoadTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTable_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx){ \ ++ _MDrv_PQ_LoadTable(u8TabIdx, u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_LoadCommTable ++#define MDrv_PQ_LoadCommTable_(PQTABLE_NAME) \ ++ MDrv_PQ_LoadCommTable_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_LoadCommTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadCommTable_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_LoadCommTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadCommTable_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_LoadCommTable(); \ ++ } ++ ++ ++//### MDrv_PQ_AddTable ++#define MDrv_PQ_AddTable_(PQTABLE_NAME, pPQTableInfo) \ ++ MDrv_PQ_AddTable_##PQTABLE_NAME(pPQTableInfo) ++ ++#define DECLARE_MDrv_PQ_AddTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_AddTable_##PQTABLE_NAME(PQTABLE_INFO *pPQTableInfo); ++ ++ ++#define INSTALL_MDrv_PQ_AddTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_AddTable_##PQTABLE_NAME(PQTABLE_INFO *pPQTableInfo){ \ ++ _MDrv_PQ_AddTable(pPQTableInfo); \ ++ } ++ ++ ++//### MDrv_PQ_LoadTableBySrcType ++#define MDrv_PQ_LoadTableBySrcType_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_LoadTableBySrcType_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_LoadTableBySrcType_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_LoadTableBySrcType_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx){ \ ++ _MDrv_PQ_LoadTableBySrcType(u16PQSrcType, u8PQIPIdx); \ ++ } ++ ++ ++//### MDrv_PQ_Set_CmdqCfg ++#define MDrv_PQ_Set_CmdqCfg_(PQTABLE_NAME, CmdqCfg) \ ++ MDrv_PQ_Set_CmdqCfg_##PQTABLE_NAME(CmdqCfg) ++ ++#define DECLARE_MDrv_PQ_Set_CmdqCfg_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_CmdqCfg_##PQTABLE_NAME(PQ_CMDQ_CONFIG CmdqCfg); ++ ++#define INSTALL_MDrv_PQ_Set_CmdqCfg_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_CmdqCfg_##PQTABLE_NAME(PQ_CMDQ_CONFIG CmdqCfg) {\ ++ _MDrv_PQ_Set_CmdqCfg(CmdqCfg); \ ++ } ++//### MDrv_PQ_Set_CmdqCfg ++#define MDrv_PQ_GetIPRegCount_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_GetIPRegCount_##PQTABLE_NAME(u16PQSrcType,u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_GetIPRegCount_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_GetIPRegCount_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_GetIPRegCount_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_GetIPRegCount_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx) {\ ++ return _MDrv_PQ_GetIPRegCount(u16PQSrcType,u8PQIPIdx); \ ++ } ++ ++ ++//### MDRv_PQ_Check_Reg ++#define MDrv_PQ_Check_Type_(PQTABLE_NAME, EnCheck) \ ++ MDrv_PQ_Check_Type_##PQTABLE_NAME(EnCheck) ++ ++#define DECLARE_MDrv_PQ_Check_Type_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Check_Type_##PQTABLE_NAME(PQ_CHECK_TYPE EnCheck); ++ ++#define INSTALL_MDrv_PQ_Check_Type_(PQTABLE_NAME) \ ++ void MDrv_PQ_Check_Type_##PQTABLE_NAME(PQ_CHECK_TYPE EnCheck) {\ ++ _MDrv_PQ_Check_Type(EnCheck); \ ++ } ++ ++ ++//### MDrv_PQ_LoadTableByData ++#define MDrv_PQ_LoadTableByData_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx, pData) \ ++ MDrv_PQ_LoadTableByData_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx, pData) ++ ++#define DECLARE_MDrv_PQ_LoadTableByData_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_LoadTableByData_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx, PQ_DATA_INFO *pData); ++ ++#define INSTALL_MDrv_PQ_LoadTableByData_(PQTABLE_NAME) \ ++ void MDrv_PQ_LoadTableByData_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx, PQ_DATA_INFO *pData){ \ ++ _MDrv_PQ_LoadTableByData(u16PQSrcType, u8PQIPIdx, pData); \ ++ } ++ ++ ++//### MDrv_PQ_CheckCommTable ++#define MDrv_PQ_CheckCommTable_(PQTABLE_NAME) \ ++ MDrv_PQ_CheckCommTable_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_CheckCommTable_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_CheckCommTable_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_CheckCommTable_(PQTABLE_NAME) \ ++ void MDrv_PQ_CheckCommTable_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_CheckCommTable(); \ ++ } ++ ++ ++//### MDrv_PQ_CheckTableBySrcType ++#define MDrv_PQ_CheckTableBySrcType_(PQTABLE_NAME, u16PQSrcType, u8PQIPIdx) \ ++ MDrv_PQ_CheckTableBySrcType_##PQTABLE_NAME(u16PQSrcType, u8PQIPIdx) ++ ++#define DECLARE_MDrv_PQ_CheckTableBySrcType_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_CheckTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx); ++ ++#define INSTALL_MDrv_PQ_CheckTableBySrcType_(PQTABLE_NAME) \ ++ void MDrv_PQ_CheckTableBySrcType_##PQTABLE_NAME(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx){ \ ++ _MDrv_PQ_CheckTableBySrcType(u16PQSrcType, u8PQIPIdx); \ ++ } ++ ++//### MDrv_PQ_GetXRuleIPIndex ++#define MDrv_PQ_GetXRuleIPIndex_(PQTABLE_NAME, u8XRuleType, u8XRuleIP) \ ++ MDrv_PQ_GetXRuleIPIndex_##PQTABLE_NAME(u8XRuleType, u8XRuleIP) ++ ++#define DECLARE_MDrv_PQ_GetXRuleIPIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetXRuleIPIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIP); ++ ++#define INSTALL_MDrv_PQ_GetXRuleIPIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetXRuleIPIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIP){ \ ++ return _MDrv_PQ_GetXRuleIPIndex(u8XRuleType, u8XRuleIP); \ ++ } ++ ++//### MDrv_PQ_GetXRuleTableIndex ++#define MDrv_PQ_GetXRuleTableIndex_(PQTABLE_NAME, u8XRuleType, u8XRuleIdx, u8XRuleIP) \ ++ MDrv_PQ_GetXRuleTableIndex_##PQTABLE_NAME(u8XRuleType, u8XRuleIdx, u8XRuleIP) ++ ++#define DECLARE_MDrv_PQ_GetXRuleTableIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetXRuleTableIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIdx, MS_U8 u8XRuleIP); ++ ++#define INSTALL_MDrv_PQ_GetXRuleTableIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetXRuleTableIndex_##PQTABLE_NAME(MS_U8 u8XRuleType, MS_U8 u8XRuleIdx, MS_U8 u8XRuleIP){ \ ++ return _MDrv_PQ_GetXRuleTableIndex(u8XRuleType, u8XRuleIdx, u8XRuleIP); \ ++ } ++ ++ ++//### MDrv_PQ_GetXRuleIPNum ++#define MDrv_PQ_GetXRuleIPNum_(PQTABLE_NAME, u8XRuleType) \ ++ MDrv_PQ_GetXRuleIPNum_##PQTABLE_NAME(u8XRuleType) ++ ++#define DECLARE_MDrv_PQ_GetXRuleIPNum_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetXRuleIPNum_##PQTABLE_NAME(MS_U8 u8XRuleType); ++ ++#define INSTALL_MDrv_PQ_GetXRuleIPNum_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetXRuleIPNum_##PQTABLE_NAME(MS_U8 u8XRuleType){ \ ++ return _MDrv_PQ_GetXRuleIPNum(u8XRuleType); \ ++ } ++ ++ ++//### MDrv_PQ_GetGRule_LevelIndex ++#define MDrv_PQ_GetGRule_LevelIndex_(PQTABLE_NAME, u8GRuleType, u8GRuleLevelIndex) \ ++ MDrv_PQ_GetGRule_LevelIndex_##PQTABLE_NAME(u8GRuleType, u8GRuleLevelIndex) ++ ++#define DECLARE_MDrv_PQ_GetGRule_LevelIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetGRule_LevelIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleLevelIndex); ++ ++#define INSTALL_MDrv_PQ_GetGRule_LevelIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetGRule_LevelIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleLevelIndex){ \ ++ return _MDrv_PQ_GetGRule_LevelIndex(u8GRuleType, u8GRuleLevelIndex); \ ++ } ++ ++ ++//### MDrv_PQ_GetGRule_IPIndex ++#define MDrv_PQ_GetGRule_IPIndex_(PQTABLE_NAME, u8GRuleType, u8GRuleIPIndex) \ ++ MDrv_PQ_GetGRule_IPIndex_##PQTABLE_NAME(u8GRuleType, u8GRuleIPIndex) ++ ++#define DECLARE_MDrv_PQ_GetGRule_IPIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetGRule_IPIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleIPIndex); ++ ++#define INSTALL_MDrv_PQ_GetGRule_IPIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetGRule_IPIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8GRuleIPIndex){ \ ++ return _MDrv_PQ_GetGRule_IPIndex(u8GRuleType, u8GRuleIPIndex); \ ++ } ++ ++ ++//### MDrv_PQ_GetGRule_TableIndex ++#define MDrv_PQ_GetGRule_TableIndex_(PQTABLE_NAME, u8GRuleType, u8PQSrcType, u8PQ_NRIdx, u8GRuleIPIndex) \ ++ MDrv_PQ_GetGRule_TableIndex_##PQTABLE_NAME(u8GRuleType, u8PQSrcType, u8PQ_NRIdx, u8GRuleIPIndex) ++ ++#define DECLARE_MDrv_PQ_GetGRule_TableIndex_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_GetGRule_TableIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8PQSrcType, MS_U8 u8PQ_NRIdx, MS_U8 u8GRuleIPIndex); ++ ++#define INSTALL_MDrv_PQ_GetGRule_TableIndex_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_GetGRule_TableIndex_##PQTABLE_NAME(MS_U8 u8GRuleType, MS_U8 u8PQSrcType, MS_U8 u8PQ_NRIdx, MS_U8 u8GRuleIPIndex){ \ ++ return _MDrv_PQ_GetGRule_TableIndex(u8GRuleType, u8PQSrcType, u8PQ_NRIdx, u8GRuleIPIndex); \ ++ } ++ ++//### MDrv_PQ_Set_MLoadEn ++#define MDrv_PQ_Set_MLoadEn_(PQTABLE_NAME, bEn) \ ++ MDrv_PQ_Set_MLoadEn_##PQTABLE_NAME(bEn) ++ ++#define DECLARE_MDrv_PQ_Set_MLoadEn_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_MLoadEn_##PQTABLE_NAME(MS_BOOL bEn); ++ ++#define INSTALL_MDrv_PQ_Set_MLoadEn_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_MLoadEn_##PQTABLE_NAME(MS_BOOL bEn){ \ ++ _MDrv_PQ_Set_MLoadEn(bEn); \ ++ } ++ ++ ++//### MDrv_PQ_PreInitLoadTableInfo ++#define MDrv_PQ_PreInitLoadTableInfo(PQTABLE_NAME) \ ++ MDrv_PQ_PreInitLoadTableInfo_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_PreInitLoadTableInfo_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_PreInitLoadTableInfo_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_PreInitLoadTableInfo_(PQTABLE_NAME) \ ++ void MDrv_PQ_PreInitLoadTableInfo_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_PreInitLoadTableInfo(); \ ++ } ++ ++//### _MDrv_PQ_Set_LoadTableInfo_IP_Tab ++#define MDrv_PQ_Set_LoadTableInfo_IP_Tab(PQTABLE_NAME, u16IPIdx, u8TabIdx) \ ++ MDrv_PQ_Set_LoadTableInfo_IP_Tab_##PQTABLE_NAME(u16IPIdx, u8TabIdx) ++ ++#define DECLARE_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx, MS_U8 u8TabIdx); ++ ++#define INSTALL_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx, MS_U8 u8TabIdx){ \ ++ _MDrv_PQ_Set_LoadTableInfo_IP_Tab(u16IPIdx, u8TabIdx); \ ++ } ++ ++ ++//### _MDrv_PQ_Get_LoadTableInfo_IP_Tab ++#define MDrv_PQ_Get_LoadTableInfo_IP_Tab(PQTABLE_NAME, u16IPIdx) \ ++ MDrv_PQ_Get_LoadTableInfo_IP_Tab_##PQTABLE_NAME(u16IPIdx) ++ ++#define DECLARE_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ extern MS_U8 MDrv_PQ_Get_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx); ++ ++#define INSTALL_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(PQTABLE_NAME) \ ++ MS_U8 MDrv_PQ_Get_LoadTableInfo_IP_Tab_##PQTABLE_NAME(MS_U16 u16IPIdx){ \ ++ return _MDrv_PQ_Get_LoadTableInfo_IP_Tab(u16IPIdx); \ ++ } ++ ++ ++//### _MDrv_PQ_Set_LoadTableInfo_SrcType ++#define MDrv_PQ_Set_LoadTableInfo_SrcType(PQTABLE_NAME, u16SrcType) \ ++ MDrv_PQ_Set_LoadTableInfo_SrcType_##PQTABLE_NAME(u16SrcType) ++ ++#define DECLARE_MDrv_PQ_Set_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_Set_LoadTableInfo_SrcType_##PQTABLE_NAME(MS_U16 u16SrcType); ++ ++#define INSTALL_MDrv_PQ_Set_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ void MDrv_PQ_Set_LoadTableInfo_SrcType_##PQTABLE_NAME(MS_U16 u16SrcType){ \ ++ _MDrv_PQ_Set_LoadTableInfo_SrcType(u16SrcType); \ ++ } ++ ++ ++//### _MDrv_PQ_Get_LoadTableInfo_SrcType ++#define MDrv_PQ_Get_LoadTableInfo_SrcType(PQTABLE_NAME) \ ++ MDrv_PQ_Get_LoadTableInfo_SrcType_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_Get_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ extern MS_U16 MDrv_PQ_Get_LoadTableInfo_SrcType_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_Get_LoadTableInfo_SrcType_(PQTABLE_NAME) \ ++ MS_U16 MDrv_PQ_Get_LoadTableInfo_SrcType_##PQTABLE_NAME(void){ \ ++ return _MDrv_PQ_Get_LoadTableInfo_SrcType(); \ ++ } ++ ++ ++//### _MDrv_PQ_ClearTableIndex ++#define MDrv_PQ_ClearTableIndex(PQTABLE_NAME) \ ++ MDrv_PQ_ClearTableIndex_##PQTABLE_NAME() ++ ++#define DECLARE_MDrv_PQ_ClearTableIndex_(PQTABLE_NAME) \ ++ extern void MDrv_PQ_ClearTableIndex_##PQTABLE_NAME(void); ++ ++#define INSTALL_MDrv_PQ_ClearTableIndex_(PQTABLE_NAME) \ ++ void MDrv_PQ_ClearTableIndex_##PQTABLE_NAME(void){ \ ++ _MDrv_PQ_ClearTableIndex(); \ ++ } ++ ++ ++//### MDrv_PQ_LoadPictureSetting ++#define MDrv_PQ_LoadPictureSetting_(PQTABLE_NAME, u8TabIdx, u8PQIPIdx, pTable, u16TableSize) \ ++ MDrv_PQ_LoadPictureSetting_##PQTABLE_NAME(u8TabIdx, u8PQIPIdx, pTable, u16TableSize) ++ ++#define DECLARE_MDrv_PQ_LoadPictureSetting_(PQTABLE_NAME) \ ++ extern MS_BOOL MDrv_PQ_LoadPictureSetting_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, void *pTable, MS_U16 u16TableSize); ++ ++#define INSTALL_MDrv_PQ_LoadPictureSetting_(PQTABLE_NAME) \ ++ MS_BOOL MDrv_PQ_LoadPictureSetting_##PQTABLE_NAME(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, void *pTable, MS_U16 u16TableSize){ \ ++ return _MDrv_PQ_LoadPictureSetting(u8TabIdx, u8PQIPIdx, pTable, u16TableSize); \ ++ } ++ ++ ++ ++#define DECLARE_PQ_FUNCTIONS(table_name) \ ++ DECLARE_MDrv_PQ_LoadCommTable_(table_name) \ ++ DECLARE_MDrv_PQ_DumpTable_(table_name) \ ++ DECLARE_MDrv_PQ_GetIPNum_(table_name) \ ++ DECLARE_MDrv_PQ_GetTableNum_(table_name) \ ++ DECLARE_MDrv_PQ_GetTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetCurrentTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetTable_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTableData_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTable_(table_name) \ ++ DECLARE_MDrv_PQ_LoadCommTable_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTableBySrcType_(table_name) \ ++ DECLARE_MDrv_PQ_Set_CmdqCfg_(table_name) \ ++ DECLARE_MDrv_PQ_GetIPRegCount_(table_name) \ ++ DECLARE_MDrv_PQ_Check_Type_(table_name) \ ++ DECLARE_MDrv_PQ_LoadTableByData_(table_name) \ ++ DECLARE_MDrv_PQ_CheckCommTable_(table_name) \ ++ DECLARE_MDrv_PQ_CheckTableBySrcType_(table_name) \ ++ DECLARE_MDrv_PQ_AddTable_(table_name) \ ++ DECLARE_MDrv_PQ_GetXRuleIPIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetXRuleTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetXRuleIPNum_(table_name) \ ++ DECLARE_MDrv_PQ_GetGRule_LevelIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetGRule_IPIndex_(table_name) \ ++ DECLARE_MDrv_PQ_GetGRule_TableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_Set_MLoadEn_(table_name) \ ++ DECLARE_MDrv_PQ_PreInitLoadTableInfo_(table_name) \ ++ DECLARE_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(table_name) \ ++ DECLARE_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(table_name) \ ++ DECLARE_MDrv_PQ_Set_LoadTableInfo_SrcType_(table_name) \ ++ DECLARE_MDrv_PQ_Get_LoadTableInfo_SrcType_(table_name) \ ++ DECLARE_MDrv_PQ_ClearTableIndex_(table_name) \ ++ DECLARE_MDrv_PQ_LoadPictureSetting_(table_name) ++ ++ ++#if PQ_ENABLE_UNUSED_FUNC ++#define INSTALL_PQ_FUNCTIONS(table_name) \ ++ INSTALL_MDrv_PQ_DumpTable_(table_name) \ ++ INSTALL_MDrv_PQ_GetIPNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetCurrentTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetTable_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableData_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTable_(table_name) \ ++ INSTALL_MDrv_PQ_LoadCommTable_(table_name) \ ++ INSTALL_MDrv_PQ_Set_CmdqCfg_(table_name) \ ++ INSTALL_MDrv_PQ_Check_Type_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableByData_(table_name) \ ++ INSTALL_MDrv_PQ_CheckCommTable_(table_name) \ ++ INSTALL_MDrv_PQ_CheckTableBySrcType_(table_name) \ ++ INSTALL_MDrv_PQ_AddTable_(table_name) \ ++ INSTALL_MDrv_PQ_GetXRuleIPIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetXRuleTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetXRuleIPNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetGRule_LevelIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetGRule_IPIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetGRule_TableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_PreInitLoadTableInfo_(table_name) \ ++ INSTALL_MDrv_PQ_Set_LoadTableInfo_IP_Tab_(table_name) \ ++ INSTALL_MDrv_PQ_Get_LoadTableInfo_IP_Tab_(table_name) \ ++ INSTALL_MDrv_PQ_Set_LoadTableInfo_SrcType_(table_name) \ ++ INSTALL_MDrv_PQ_Get_LoadTableInfo_SrcType_(table_name) \ ++ INSTALL_MDrv_PQ_ClearTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetIPRegCount_(table_name) \ ++ INSTALL_MDrv_PQ_LoadPictureSetting_(table_name) ++#else ++ ++#define INSTALL_PQ_FUNCTIONS(table_name) \ ++ INSTALL_MDrv_PQ_DumpTable_(table_name) \ ++ INSTALL_MDrv_PQ_GetIPNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableNum_(table_name) \ ++ INSTALL_MDrv_PQ_GetIPRegCount_(table_name) \ ++ INSTALL_MDrv_PQ_GetTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetCurrentTableIndex_(table_name) \ ++ INSTALL_MDrv_PQ_GetTable_(table_name) \ ++ INSTALL_MDrv_PQ_Set_CmdqCfg_(table_name) \ ++ INSTALL_MDrv_PQ_Check_Type_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableByData_(table_name) \ ++ INSTALL_MDrv_PQ_AddTable_(table_name) \ ++ INSTALL_MDrv_PQ_LoadTableBySrcType_(table_name) \ ++ INSTALL_MDrv_PQ_ClearTableIndex_(table_name) ++#endif ++ ++// TODO: declare PQ functions for all tables in this file ++DECLARE_PQ_FUNCTIONS(MAIN) // table config parameter ++ ++ ++// SC ++#include "Infinity3e_Main.h" // table config parameter ++#include "Infinity3e_Main_HSPRule.h" // table config parameter ++#include "Infinity3e_Main_VSPRule.h" // table config parameter ++#include "Infinity3e_Main_GRule.h" // table config parameter ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/drvPQ_Define.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/drvPQ_Define.h +new file mode 100644 +index 00000000..7e443aa5 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/drvPQ_Define.h +@@ -0,0 +1,550 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRVPQ_DEFINE_H_ ++#define _DRVPQ_DEFINE_H_ ++ ++#define PQ_ONLY_SUPPORT_BIN 0 ++#define PQ_ENABLE_DEBUG 0 ++#define PQ_ENABLE_CHECK 0 ++ ++#define ENABLE_PQ_CMDQ 1 ++#define ENABLE_PQ_BIN 0 ++#define ENABLE_PQ_MLOAD 0 ++#define ENABLE_PQ_EX 0 ++ ++#define ENABLE_MULTI_SCALER 0 ++ ++#define PQ_ENABLE_420UPSAMPLING 0 ++#define PQ_ENABLE_NONLINEAR_SCALING 0 ++#define PQ_ENABLE_SETFILM_MODE 0 ++#define PQ_ENABLE_MEMFMT 0 ++#define PQ_ENABLE_CSCRULE 0 ++#define PQ_ENABLE_HSDRULE 0 ++#define PQ_ENABLE_PICTURE 0 ++#define PQ_ENABLE_UNUSED_FUNC 0 ++ ++#define PQ_ENABLE_VD_SAMPLING 0 ++#define PQ_ENABLE_PIP 0 ++#define PQ_ENABLE_3D_VIDEO 1 ++#define PQ_ENABLE_IOCTL 1 ++#define PQ_ENABLE_COLOR 1 ++ ++//!! for SC1 PIP setting !!// ++#define PQ_ENABLE_PIP_SC1 0 ++ ++#define PQ_QM_CVBS 0 ++#define PQ_QM_YPBPR 0 ++#define PQ_QM_PC 0 ++#define PQ_QM_HMDI 0 ++#define PQ_QM_HDMI_PC 0 ++#define PQ_QM_DTV 0 ++#define PQ_QM_MM_VIDEO 0 ++#define PQ_QM_MM_PHOTO 0 ++#define PQ_QM_ISP 1 ++#define PQ_QM_3D 0 ++#define PQ_EX_ENABLE 0 ++#define PQ_SKIPRULE_ENABLE 1 ++ ++#define PQ_GRULE_NR_ENABLE 0 ++#define PQ_GRULE_MPEG_NR_ENABLE 0 ++#define PQ_GRULE_DDR_SELECT_ENABLE 0 ++#define PQ_GRULE_OSD_BW_ENABLE 0 ++#define PQ_GRULE_FILM_MODE_ENABLE 0 ++#define PQ_GRULE_DYNAMIC_CONTRAST_ENABLE 0 ++#define PQ_GRULE_ULTRAT_CLEAR_ENABLE 0 ++#define PQ_GRULE_PTP_ENABLE 0 ++#define PQ_XRULE_DB_ENABLE 0 ++ ++#define ESTIMATE_AVAILABLE_RATE 85 ++#define PQ_ENABLE_FORCE_MADI 0 ++#define PQ_NEW_HSD_SAMPLING_TYPE 0 ++#define PQ_BW_H264_ENABLE 0 ++#define PQ_BW_MM_ENABLE 0 ++#define PQ_MADI_88X_MODE 0 ++#define PQ_UC_CTL 0 ++#define PQ_MADI_DFK 0 ++#define PQ_VIP_CTL 0 ++#define PQ_VIP_RGBCMY_CTL 0 ++ ++ ++#define PQ_EN_DMS_SW_CTRL FALSE ++#define PQ_ENABLE_RFBL FALSE ++#define PQ_EN_UCNR_OFF FALSE ++ ++#define MAIN_WINDOW 0 ++#define SUB_WINDOW 1 ++ ++extern MS_S32 _PQ_Mutex ; ++ ++#if defined (MSOS_TYPE_LINUX) ++extern pthread_mutex_t _PQ_MLoad_Mutex; ++#endif ++ ++#if PQ_ENABLE_DEBUG ++extern MS_BOOL _u16DbgSwitch; ++#define PQ_DBG(x) \ ++do{ \ ++ if (_u16DbgSwitch){ \ ++ x; \ ++ } \ ++}while(0) ++ ++#define PQ_DUMP_DBG(x) x ++#define PQ_DUMP_FILTER_DBG(x) x ++#else ++#define PQ_ERR(x) x ++#define PQ_DBG(x) ++#define PQ_DUMP_DBG(x) ++#define PQ_DUMP_FILTER_DBG(x) //x ++#endif ++ ++#define PQ_MAP_REG(reg) (((reg)>>8)&0xFF), ((reg)&0xFF) ++#define REG_ADDR_SIZE 2 ++#define REG_MASK_SIZE 1 ++ ++#define PQ_IP_NULL 0xFF ++ ++#define PQTBL_EX 0x10 ++#define PQTBL_NORMAL 0x11 ++ ++#define E_XRULE_HSD 0 ++#define E_XRULE_VSD 1 ++#define E_XRULE_HSP 2 ++#define E_XRULE_VSP 3 ++#define E_XRULE_CSC 4 ++ ++#if PQ_XRULE_DB_ENABLE ++#define E_XRULE_DB_NTSC 5 ++#define E_XRULE_DB_PAL 6 ++#define E_XRULE_NUM 7 ++#else ++#define E_XRULE_NUM 5 ++#endif ++ ++//Here must be the same order as MST_GRule_Index_Main ++typedef enum { ++ E_GRULE_NR, ++#if(PQ_GRULE_OSD_BW_ENABLE == 1) ++ E_GRULE_OSD_BW, ++#endif ++#if(PQ_GRULE_MPEG_NR_ENABLE == 1) ++ E_GRULE_MPEG_NR, ++#endif ++#if(PQ_GRULE_FILM_MODE_ENABLE == 1) ++ E_GRULE_FilmMode, ++#endif ++#if(PQ_GRULE_DYNAMIC_CONTRAST_ENABLE == 1) ++ E_GRULE_DynContr, ++#endif ++#if(PQ_GRULE_DDR_SELECT_ENABLE == 1) ++ E_GRULE_DDR_SELECT, ++#endif ++#if(PQ_GRULE_ULTRAT_CLEAR_ENABLE == 1) ++ E_GRULE_ULTRACLEAR, ++#endif ++#if(PQ_GRULE_PTP_ENABLE == 1) ++ E_GRULE_PTP, ++#endif ++ E_GRULE_NUM, ++} EN_GRULE_INDEX; ++ ++ ++#define _END_OF_TBL_ 0xFFFF ++ ++ ++typedef enum { ++ PQ_TABTYPE_GENERAL, ++ PQ_TABTYPE_COMB, ++ PQ_TABTYPE_SCALER, ++ PQ_TABTYPE_SRAM1, ++ PQ_TABTYPE_SRAM2, ++ PQ_TABTYPE_SRAM3, ++ PQ_TABTYPE_SRAM4, ++ PQ_TABTYPE_C_SRAM1, ++ PQ_TABTYPE_C_SRAM2, ++ PQ_TABTYPE_C_SRAM3, ++ PQ_TABTYPE_C_SRAM4, ++ PQ_TABTYPE_SRAM_COLOR_INDEX, ++ PQ_TABTYPE_SRAM_COLOR_GAIN_SNR, ++ PQ_TABTYPE_SRAM_COLOR_GAIN_DNR, ++ PQ_TABTYPE_VIP_IHC_CRD_SRAM, ++ PQ_TABTYPE_VIP_ICC_CRD_SRAM, ++ PQ_TABTYPE_XVYCC_DE_GAMMA_SRAM, ++ PQ_TABTYPE_XVYCC_GAMMA_SRAM, ++ PQ_TABTYPE_SWDRIVER, ++ PQ_TABTYPE_PICTURE_1, ++ PQ_TABTYPE_PICTURE_2, ++ PQ_TABTYPE_WDR_Loc_TBL_0_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_1_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_2_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_3_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_4_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_5_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_6_SRAM, ++ PQ_TABTYPE_WDR_Loc_TBL_7_SRAM, ++ PQ_TABTYPE_PRIVACY_MASK_SRAM, ++ PQ_TABTYPE_YUV_Gamma_tblU_SRAM, ++ PQ_TABTYPE_YUV_Gamma_tblV_SRAM, ++ PQ_TABTYPE_YUV_Gamma_tblY_SRAM, ++ PQ_TABTYPE_ColorEng_GM10to12_Tbl_R_SRAM, ++ PQ_TABTYPE_ColorEng_GM10to12_Tbl_G_SRAM, ++ PQ_TABTYPE_ColorEng_GM10to12_Tbl_B_SRAM, ++ PQ_TABTYPE_ColorEng_GM12to10_CrcTbl_R_SRAM, ++ PQ_TABTYPE_ColorEng_GM12to10_CrcTbl_G_SRAM, ++ PQ_TABTYPE_ColorEng_GM12to10_CrcTbl_B_SRAM, ++ PQ_TABTYPE_Max, ++} EN_PQ_TABTYPE; ++ ++ ++typedef enum ++{ ++ PQ_MD_720x480_60I, // 00 ++ PQ_MD_720x480_60P, // 01 ++ PQ_MD_720x576_50I, // 02 ++ PQ_MD_720x576_50P, // 03 ++ PQ_MD_1280x720_50P, // 04 ++ PQ_MD_1280x720_60P, // 05 ++ PQ_MD_1920x1080_50I, // 06 ++ PQ_MD_1920x1080_60I, // 07 ++ PQ_MD_1920x1080_24P, // 08 ++ PQ_MD_1920x1080_25P, // 09 ++ PQ_MD_1920x1080_30P, // 10 ++ PQ_MD_1920x1080_50P, // 11 ++ PQ_MD_1920x1080_60P, // 12 ++ PQ_MD_Num, ++}PQ_MODE_INDEX; ++ ++typedef enum ++{ ++ PQ_CHECK_OFF = 0, // reset before test ++ PQ_CHECK_REG = 1, // test register mode ++ PQ_CHECK_SIZE = 2, // test size mode ++ PQ_CHECK_NUM, ++}PQ_CHECK_TYPE; ++ ++typedef struct ++{ ++ MS_U8 *pIPCommTable; ++ MS_U8 *pIPTable; ++ MS_U8 u8TabNums; ++ MS_U8 u8TabType; ++} EN_IPTAB_INFO; ++ ++typedef struct ++{ ++ MS_U8 *pIPTable; ++ MS_U8 u8TabNums; ++ MS_U8 u8TabType; ++ MS_U8 u8TabIdx; ++} EN_IP_Info; ++ ++ ++enum ++{ ++ PQ_FUNC_DUMP_REG, ++ PQ_FUNC_CHK_REG, ++}; ++ ++#define PQ_MUX_DEBUG 0 ++ ++#define SCALER_REGISTER_SPREAD 1 ++ ++#if(SCALER_REGISTER_SPREAD) ++ #define BK_SCALER_BASE 0x120000 ++ ++ // no need to store bank for spread reg ++ #define SC_BK_STORE_NOMUTEX ++ ++ #define SC_BK_RESTORE_NOMUTEX ++ ++ ++ #if(PQ_MUX_DEBUG) ++ // no need to store bank for spread reg ++ #define SC_BK_STORE_MUTEX \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ printf("==========================\n"); \ ++ printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ ++ } ++ ++ // restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++ #else ++ #define SC_BK_STORE_MUTEX \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ } ++ ++ // restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++ #endif ++ ++ ++ ++ // switch bank ++ #define SC_BK_SWITCH(_x_) ++ ++ #define SC_BK_CURRENT (u8CurBank) ++#else ++ #define BK_SCALER_BASE 0x102F00 ++ ++ #define SC_BK_STORE_NOMUTEX \ ++ MS_U8 u8Bank; \ ++ u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) ++ ++ // restore bank ++ #define SC_BK_RESTORE_NOMUTEX MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); ++ ++#if(PQ_MUX_DEBUG) ++// store bank ++ #define SC_BK_STORE_MUTEX \ ++ MS_U8 u8Bank; \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ printf("==========================\n"); \ ++ printf("[%s][%s][%06d] Mutex taking timeout\n",__FILE__,__FUNCTION__,__LINE__); \ ++ } \ ++ u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) ++ ++// restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++#else ++ #define SC_BK_STORE_MUTEX \ ++ MS_U8 u8Bank; \ ++ if(!MsOS_ObtainMutex(_PQ_Mutex, MSOS_WAIT_FOREVER)) \ ++ { \ ++ } \ ++ u8Bank = MApi_XC_ReadByte(BK_SCALER_BASE) ++ ++// restore bank ++ #define SC_BK_RESTORE_MUTEX \ ++ MApi_XC_WriteByte(BK_SCALER_BASE, u8Bank); \ ++ MsOS_ReleaseMutex(_PQ_Mutex); ++#endif ++ ++// switch bank ++#define SC_BK_SWITCH(_x_)\ ++ MApi_XC_WriteByte(BK_SCALER_BASE, _x_) ++ ++#define SC_BK_CURRENT \ ++ MApi_XC_ReadByte(BK_SCALER_BASE) ++#endif ++ ++ ++ ++// store bank ++#define COMB_BK_STORE \ ++ MS_U8 u8Bank; \ ++ u8Bank = MApi_XC_ReadByte(COMB_REG_BASE) ++ ++// restore bank ++#define COMB_BK_RESTORE \ ++ MApi_XC_WriteByte(COMB_REG_BASE, u8Bank) ++// switch bank ++#define COMB_BK_SWITCH(_x_)\ ++ MApi_XC_WriteByte(COMB_REG_BASE, _x_) ++ ++#define COMB_BK_CURRENT \ ++ MApi_XC_ReadByte(COMB_REG_BASE) ++ ++ ++ ++#define PQ_IP_COMM 0xfe ++#define PQ_IP_ALL 0xff ++ ++ ++typedef enum ++{ ++ /// Main window ++ PQ_MAIN_WINDOW=0, ++ ++ /// The max support window of PQ ++ PQ_MAX_WINDOW ++}PQ_WIN; ++ ++ ++typedef struct { ++ PQ_WIN eWin; ++ MS_U8 u8PQ_InputType_Num; ++ MS_U8 u8PQ_IP_Num; ++ MS_U8 *pQuality_Map_Aray; ++ EN_IPTAB_INFO *pIPTAB_Info; ++ MS_U8 *pSkipRuleIP; ++ ++ MS_U8 u8PQ_XRule_IP_Num[E_XRULE_NUM]; ++ MS_U8 *pXRule_IP_Index[E_XRULE_NUM]; ++ MS_U8 *pXRule_Array[E_XRULE_NUM]; ++ ++ MS_U8 u8PQ_GRule_Num[E_GRULE_NUM]; ++ MS_U8 u8PQ_GRule_IPNum[E_GRULE_NUM]; ++ MS_U8 u8PQ_GRule_LevelNum[E_GRULE_NUM]; ++ MS_U8 *pGRule_IP_Index[E_GRULE_NUM]; ++ MS_U8 *pGRule_Array[E_GRULE_NUM]; ++ MS_U8 *pGRule_Level[E_GRULE_NUM]; ++} PQTABLE_INFO; ++ ++/** ++ * FOURCE COLOR FMT ++ */ ++typedef enum ++{ ++ /// Default ++ PQ_FOURCE_COLOR_DEFAULT, ++ /// RGB ++ PQ_FOURCE_COLOR_RGB, ++ /// YUV ++ PQ_FOURCE_COLOR_YUV, ++}PQ_FOURCE_COLOR_FMT; ++ ++/** ++ * PQ DEINTERLACE MODE ++ */ ++typedef enum ++{ ++ /// off ++ PQ_DEINT_OFF=0, ++ /// 2DDI BOB ++ PQ_DEINT_2DDI_BOB, ++ /// 2DDI AVG ++ PQ_DEINT_2DDI_AVG, ++ /// 3DDI History(24 bit) ++ PQ_DEINT_3DDI_HISTORY, ++ /// 3DDI(16 bit) ++ PQ_DEINT_3DDI, ++} PQ_DEINTERLACE_MODE; ++/** ++ * Video data information to supply when in PQ mode. ++ */ ++typedef struct ++{ ++ /// is FBL or not ++ MS_BOOL bFBL; ++ /// is interlace mode or not ++ MS_BOOL bInterlace; ++ /// input Horizontal size ++ MS_U16 u16input_hsize; ++ /// input Vertical size ++ MS_U16 u16input_vsize; ++ /// input Vertical total ++ MS_U16 u16input_vtotal; ++ /// input Vertical frequency ++ MS_U16 u16input_vfreq; ++ /// output Vertical frequency ++ MS_U16 u16ouput_vfreq; ++ /// Display Horizontal size ++ MS_U16 u16display_hsize; ++ /// Display Vertical size ++ MS_U16 u16display_vsize; ++}MS_PQ_Mode_Info; ++ ++/** ++ * INPUT SOURCE TYPE ++ */ ++typedef enum ++{ ++ /// VGA ++ PQ_INPUT_SOURCE_VGA, ++ /// TV ++ PQ_INPUT_SOURCE_TV, ++ ++ /// CVBS ++ PQ_INPUT_SOURCE_CVBS, ++ ++ /// S-video ++ PQ_INPUT_SOURCE_SVIDEO, ++ ++ /// Component ++ PQ_INPUT_SOURCE_YPBPR, ++ /// Scart ++ PQ_INPUT_SOURCE_SCART, ++ ++ ++ /// HDMI ++ PQ_INPUT_SOURCE_HDMI, ++ ++ /// DTV ++ PQ_INPUT_SOURCE_DTV, ++ ++ /// DVI ++ PQ_INPUT_SOURCE_DVI, ++ ++ // Application source ++ /// Storage ++ PQ_INPUT_SOURCE_STORAGE, ++ /// KTV ++ PQ_INPUT_SOURCE_KTV, ++ /// JPEG ++ PQ_INPUT_SOURCE_JPEG, ++ ++ // BT656 ++ PQ_INPUT_SOURCE_BT656, ++ ++ // ISP ++ PQ_INPUT_SOURCE_ISP, ++ ++ /// The max support number of PQ input source ++ PQ_INPUT_SOURCE_NUM, ++ /// None ++ PQ_INPUT_SOURCE_NONE = PQ_INPUT_SOURCE_NUM, ++} PQ_INPUT_SOURCE_TYPE; ++ ++ ++// PQ Function ++typedef enum ++{ ++ E_PQ_IOCTL_NONE = 0x00000000, ++ E_PQ_IOCTL_HSD_SAMPLING = 0x00000001, ++ E_PQ_IOCTL_PREVSD_BILINEAR = 0x00000002, ++ E_PQ_IOCTL_ADC_SAMPLING = 0x00000003, ++ E_PQ_IOCTL_RFBL_CTRL = 0x00000004, ++ ++ E_PQ_IOCTL_NUM, ++}PQ_IOCTL_FLAG_TYPE; ++ ++ ++typedef struct ++{ ++ MS_U32 u32ratio; ++ MS_BOOL bADVMode; ++}PQ_HSD_SAMPLING_INFO; ++ ++typedef struct ++{ ++ PQ_INPUT_SOURCE_TYPE enPQSourceType; ++ MS_PQ_Mode_Info stPQModeInfo; ++ MS_U16 u16ratio; ++}PQ_ADC_SAMPLING_INFO; ++ ++typedef struct ++{ ++ MS_U8 *pBuf; ++ MS_U16 u16BufSize; ++}PQ_DATA_INFO; ++ ++typedef struct ++{ ++ MS_BOOL bEnFmCnt; ++ MS_U8 u8FmCnt; ++ MS_BOOL bfire; ++}PQ_CMDQ_CONFIG; ++ ++#endif /* _DRVPQ_DEFINE_H_ */ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/hwreg_pq.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/hwreg_pq.h +new file mode 100644 +index 00000000..5a8129cd +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/hwreg_pq.h +@@ -0,0 +1,20 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#define REG_SCALER_BASE 0x130000 ++#define COMB_REG_BASE 0x103600 ++#define NON_PM_BASE 0x100000 +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/mhal_pq.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/mhal_pq.h +new file mode 100644 +index 00000000..b37d7c82 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/mhal_pq.h +@@ -0,0 +1,103 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (!¡±MStar Confidential Information!¡L) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++//============================================================================== ++#ifndef MHAL_PQ_H ++#define MHAL_PQ_H ++ ++#define MEMFMT24BIT_YC10BIT_MOT 0xBB ++#define MEMFMT24BIT_YC8BIT_MOT 0xAA ++#define MEMFMT24BIT_YC10BIT 0x99 ++#define MEMFMT24BIT_YC8BIT 0x88 ++#define MEMFMT24BIT_CLEAR 0x00 ++ ++#define SC_FILTER_Y_SRAM1 0x00 ++#define SC_FILTER_Y_SRAM2 0x01 ++#define SC_FILTER_Y_SRAM3 0x02 ++#define SC_FILTER_Y_SRAM4 0x03 ++#define SC_FILTER_C_SRAM1 0x04 ++#define SC_FILTER_C_SRAM2 0x05 ++#define SC_FILTER_C_SRAM3 0x06 ++#define SC_FILTER_C_SRAM4 0x07 ++#define SC_FILTER_SRAM_COLOR_INDEX 0x08 ++#define SC_FILTER_SRAM_COLOR_GAIN_SNR 0x09 ++#define SC_FILTER_SRAM_COLOR_GAIN_DNR 0x0A ++#define SC_FILTER_SRAM_ICC_CRD 0x0B ++#define SC_FILTER_SRAM_IHC_CRD 0x0C ++#define SC_FILTER_SRAM_XVYCC_DE_GAMMA 0x0D ++#define SC_FILTER_SRAM_XVYCC_GAMMA 0x0E ++ ++#define FILTER_SRAM_SC1 0x00 ++#define FILTER_SRAM_SC2 0x01 ++#define FILTER_SRAM_SC3 0x02 ++ ++ ++ ++#define SUPPORT_SCMI_V2 TRUE ++#define SUPPORT_DYNAMIC_MEM_FMT TRUE ++ ++void Hal_PQ_init_riu_base(MS_U32 u32riu_base); ++MS_U8 Hal_PQ_get_sync_flag(PQ_WIN ePQWin); ++MS_U8 Hal_PQ_get_input_vsync_value(PQ_WIN ePQWin); ++MS_U8 Hal_PQ_get_output_vsync_value(PQ_WIN ePQWin); ++MS_U8 Hal_PQ_get_input_vsync_polarity(PQ_WIN ePQWin); ++void Hal_PQ_set_memfmt_doublebuffer(PQ_WIN ePQWin, MS_BOOL bEn); ++void Hal_PQ_set_sourceidx(PQ_WIN ePQWin, MS_U16 u16Idx); ++void Hal_PQ_set_mem_fmt(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask); ++void Hal_PQ_set_mem_fmt_en(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask); ++void Hal_PQ_set_420upSample(PQ_WIN ePQWin, MS_U16 u16value); ++void Hal_PQ_set_force_y_motion(PQ_WIN ePQWin, MS_U16 u16value); ++MS_U8 Hal_PQ_get_force_y_motion(PQ_WIN ePQWin); ++void Hal_PQ_set_force_c_motion(PQ_WIN ePQWin, MS_U16 u16value); ++MS_U8 Hal_PQ_get_force_c_motion(PQ_WIN ePQWin); ++void Hal_PQ_set_dipf_temporal(PQ_WIN ePQWin, MS_U16 u16val); ++MS_U16 Hal_PQ_get_dipf_temporal(PQ_WIN ePQWin); ++void Hal_PQ_set_dipf_spatial(PQ_WIN ePQWin, MS_U16 u16val); ++MS_U8 Hal_PQ_get_dipf_spatial(PQ_WIN ePQWin); ++void Hal_PQ_set_vsp_sram_filter(PQ_WIN ePQWin, MS_U8 u8vale); ++MS_U8 Hal_PQ_get_vsp_sram_filter(PQ_WIN ePQWin); ++void Hal_PQ_set_dnr(PQ_WIN ePQWin, MS_U8 u8val); ++MS_U8 Hal_PQ_get_dnr(PQ_WIN ePQWin); ++void Hal_PQ_set_presnr(PQ_WIN ePQWin, MS_U8 u8val); ++MS_U8 Hal_PQ_get_presnr(PQ_WIN ePQWin); ++void Hal_PQ_set_film(PQ_WIN ePQWin, MS_U16 u16val); ++MS_U8 Hal_PQ_get_film(PQ_WIN ePQWin); ++void Hal_PQ_set_yc_sram(MS_U8 enID, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_color_index_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_color_gain_snr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_color_gain_dnr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++MS_U16 Hal_PQ_get_420_cup_idx(MS_420_CUP_TYPE etype); ++MS_U16 Hal_PQ_get_hnonlinear_idx(MS_HNONLINEAR_TYPE etype); ++MS_U16 Hal_PQ_get_422To444_idx(MS_422To444_TYPE etype); ++MS_U8 Hal_PQ_get_422To444_mode(MS_BOOL bMemFmt422); ++MS_U8 Hal_PQ_get_madi_fbl_mode(MS_BOOL bMemFmt422,MS_BOOL bInterlace); ++MS_U16 Hal_PQ_get_csc_ip_idx(MS_CSC_IP_TYPE enCSC); ++MS_U8 Hal_PQ_get_madi_fbl_mode(MS_BOOL bMemFmt422,MS_BOOL bInterlace); ++MS_U16 Hal_PQ_get_csc_ip_idx(MS_CSC_IP_TYPE enCSC); ++MS_U16 Hal_PQ_get_madi_idx(PQ_WIN ePQWin, MS_MADI_TYPE etype); ++MS_U16 Hal_PQ_get_sram_size(MS_U16 u16sramtype); ++MS_U16 Hal_PQ_get_ip_idx(MS_PQ_IP_TYPE eType); ++MS_U16 Hal_PQ_get_hsd_sampling_idx(MS_HSD_SAMPLING_TYPE eType); ++void Hal_PQ_OPWriteOff_Enable(MS_BOOL bEna); ++MS_U16 Hal_PQ_get_adc_sampling_idx(MS_ADC_SAMPLING_TYPE eType); ++void Hal_PQ_set_sram_ihc_crd_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++void Hal_PQ_set_sram_icc_crd_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData); ++MS_U16 Hal_PQ_get_rw_method(PQ_WIN ePQWin); ++void Hal_PQ_set_rw_method(PQ_WIN ePQWin, MS_U16 u16method); ++MS_BOOL HAL_PQ_user_mode_control(void); ++void HAL_PQ_set_SelectCSC(MS_U16 u16selection, PQ_WIN ePQWin); ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main.c +new file mode 100644 +index 00000000..ca087b0a +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main.c +@@ -0,0 +1,10438 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (; MStar; Confidential; Information; ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//**************************************************** ++// Quality Map CodeGen Version 4.0 ++// 1920 ++// Infinity3e ++// 12/4/2016 4:12:59 PM ++// 39630.43853 ++//**************************************************** ++ ++#ifndef _INFINITY3E_MAIN_C_ ++#define _INFINITY3E_MAIN_C_ ++ ++#if PQ_SKIPRULE_ENABLE ++ ++ unsigned char MST_SkipRule_IP_Main[PQ_IP_NUM_Main]= ++{ ++ /* MCNR */ 0, /* LDC */ 1, /* LDC_422_444_422 */ 1, /* NLM */ 1, ++ /* 422to444 */ 1, /* VIP */ 1, /* VIP_pseudo */ 1, /* VIP_LineBuffer */ 1, ++ /* VIP_HLPF */ 1, /* VIP_HLPF_dither */ 1, /* VIP_VLPF_coef1 */ 1, /* VIP_VLPF_coef2 */ 1, ++ /* VIP_VLPF_dither */ 1, /* VIP_Peaking */ 1, /* VIP_Peaking_band */ 1, /* VIP_Peaking_adptive */ 1, ++ /* VIP_Peaking_Pcoring */ 1, /* VIP_Peaking_Pcoring_ad_Y */ 1, /* VIP_Peaking_gain */ 1, /* VIP_Peaking_gain_ad_Y */ 1, ++ /* VIP_LCE */ 1, /* VIP_LCE_dither */ 1, /* VIP_LCE_setting */ 1, /* VIP_LCE_curve */ 1, ++ /* VIP_DLC_His_range */ 1, /* VIP_DLC */ 1, /* VIP_DLC_dither */ 1, /* VIP_DLC_His_rangeH */ 1, ++ /* VIP_DLC_His_rangeV */ 1, /* VIP_DLC_PC */ 1, /* VIP_YC_gain_offset */ 1, /* VIP_UVC */ 1, ++ /* VIP_FCC_full_range */ 1, /* VIP_FCC_bdry_dist */ 1, /* VIP_FCC_T1 */ 1, /* VIP_FCC_T2 */ 1, ++ /* VIP_FCC_T3 */ 1, /* VIP_FCC_T4 */ 1, /* VIP_FCC_T5 */ 1, /* VIP_FCC_T6 */ 1, ++ /* VIP_FCC_T7 */ 1, /* VIP_FCC_T8 */ 1, /* VIP_FCC_T9 */ 1, /* VIP_IHC */ 1, ++ /* VIP_IHC_Ymode */ 1, /* VIP_IHC_dither */ 1, /* VIP_IHC_CRD_SRAM */ 1, /* VIP_IHC_SETTING */ 1, ++ /* VIP_ICC */ 1, /* VIP_ICC_Ymode */ 1, /* VIP_ICC_dither */ 1, /* VIP_ICC_CRD_SRAM */ 1, ++ /* VIP_ICC_SETTING */ 1, /* VIP_Ymode_Yvalue_ALL */ 1, /* VIP_Ymode_Yvalue_SETTING */ 1, /* VIP_IBC */ 1, ++ /* VIP_IBC_dither */ 1, /* VIP_IBC_SETTING */ 1, /* VIP_ACK */ 1, /* VIP_YCbCr_Clip */ 1, ++ /* VSP_Y_SC1 */ 1, /* VSP_C_SC1 */ 1, /* VSP_CoRing_SC1 */ 1, /* VSP_DeRing_SC1 */ 1, ++ /* VSP_Dither_SC1 */ 1, /* VSP_PreVBound_SC1 */ 1, /* AntiPAL_filter_SC1 */ 1, /* 422To444_SC1 */ 1, ++ /* HSP_Y_SC1 */ 1, /* HSP_C_SC1 */ 1, /* HSP_CoRing_SC1 */ 1, /* HSP_DeRing_SC1 */ 1, ++ /* HSP_Dither_SC1 */ 1, /* HnonLinear_SC1 */ 1, /* SRAM1 */ 1, /* SRAM2 */ 1, ++ /* SRAM3 */ 1, /* SRAM4 */ 1, /* C_SRAM1 */ 1, /* C_SRAM2 */ 1, ++ /* C_SRAM3 */ 1, /* C_SRAM4 */ 1, /* VSP_Y_SC2 */ 1, /* VSP_C_SC2 */ 1, ++ /* VSP_CoRing_SC2 */ 1, /* VSP_DeRing_SC2 */ 1, /* VSP_Dither_SC2 */ 1, /* VSP_PreVBound_SC2 */ 1, ++ /* AntiPAL_filter_SC2 */ 1, /* 422To444_SC2 */ 1, /* HSP_Y_SC2 */ 1, /* HSP_C_SC2 */ 1, ++ /* HSP_CoRing_SC2 */ 1, /* HSP_DeRing_SC2 */ 1, /* HSP_Dither_SC2 */ 1, /* HnonLinear_SC2 */ 1, ++ /* VSP_Y_SC3 */ 1, /* VSP_C_SC3 */ 1, /* VSP_CoRing_SC3 */ 1, /* VSP_DeRing_SC3 */ 1, ++ /* VSP_Dither_SC3 */ 1, /* VSP_PreVBound_SC3 */ 1, /* AntiPAL_filter_SC3 */ 1, /* 422To444_SC3 */ 1, ++ /* HSP_Y_SC3 */ 1, /* HSP_C_SC3 */ 1, /* HSP_CoRing_SC3 */ 1, /* HSP_DeRing_SC3 */ 1, ++ /* HSP_Dither_SC3 */ 1, /* HnonLinear_SC3 */ 1, /* WDR_Loc_TBL_0_SRAM */ 1, /* WDR_Loc_TBL_1_SRAM */ 1, ++ /* WDR_Loc_TBL_2_SRAM */ 1, /* WDR_Loc_TBL_3_SRAM */ 1, /* WDR_Loc_TBL_4_SRAM */ 1, /* WDR_Loc_TBL_5_SRAM */ 1, ++ /* WDR_Loc_TBL_6_SRAM */ 1, /* WDR_Loc_TBL_7_SRAM */ 1, /* YUV_Gamma_tblU_SRAM */ 1, /* YUV_Gamma_tblV_SRAM */ 1, ++ /* YUV_Gamma_tblY_SRAM */ 1, /* ColorEng_GM10to12_Tbl_R_SRAM */ 1, /* ColorEng_GM10to12_Tbl_G_SRAM */ 1, /* ColorEng_GM10to12_Tbl_B_SRAM */ 1, ++ /* ColorEng_GM12to10_CrcTbl_R_SRAM */ 1, /* ColorEng_GM12to10_CrcTbl_G_SRAM */ 1, /* ColorEng_GM12to10_CrcTbl_B_SRAM */ 1, /* YEE */ 0, ++ /* YEE_AC_LUT */ 0, /* WDR_Glob */ 0, /* WDR_Loc */ 0, /* MXNR */ 0, ++ /* UV_ADJUST */ 0, /* XNR */ 1, /* YC10_UVM10 */ 0, /* Color_Transfer */ 0, ++ /* YUV_Gamma */ 0, /* ColorEng_422to444 */ 0, /* ColorEng_YUVtoRGB */ 0, /* ColorEng_GM10to12 */ 0, ++ /* ColorEng_CCM */ 0, /* ColorEng_HSV */ 0, /* ColorEng_GM12to10 */ 0, /* ColorEng_RGBtoYUV */ 0, ++ /* ColorEng_444to422 */ 0, /* SWDriver */ 1, /* SC_End */ 1, ++}; ++ ++#endif ++//**************************************************** ++// MCNR ++//**************************************************** ++ unsigned char MST_MCNR_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_MCNR_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_MCNR_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK29_01_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_01_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_01_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_01_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_02_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_10_L), 0x7f, 0x4a/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_10_H), 0x1f, 0xc/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_11_L), 0x1f, 0x8/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_11_H), 0x1f, 0xe/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_12_L), 0x0f, 0x8/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_12_L), 0x80, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_14_L), 0x03, 0x1/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_14_L), 0x70, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_14_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_14_H), 0x80, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_15_L), 0xff, 0x6f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_15_H), 0x07, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_16_L), 0xff, 0x92/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_16_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_18_L), 0x01, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_19_L), 0xff, 0x54/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_19_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_1A_L), 0xff, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_1A_H), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_1B_L), 0xff, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_1B_H), 0x0f, 0x4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_L), 0x01, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_L), 0x02, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_L), 0x04, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_50_H), 0x1f, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_51_L), 0x1f, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_52_L), 0x07, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_52_L), 0x70, 0x30/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_52_L), 0x80, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_52_H), 0x0f, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_54_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_54_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_54_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_54_L), 0xf0, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_54_H), 0xff, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_55_L), 0xff, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_55_H), 0xff, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_56_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_56_L), 0x0f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_56_H), 0xff, 0x28/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_57_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_57_L), 0xf0, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_58_L), 0x3f, 0x3e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_58_H), 0x3f, 0x3f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_59_L), 0x3f, 0x3c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_59_H), 0x3f, 0x3d/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5A_L), 0x3f, 0x3c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5A_H), 0x3f, 0x3c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5B_L), 0x3f, 0x30/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5B_H), 0x3f, 0x38/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5C_L), 0x3f, 0x1c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5C_H), 0x3f, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5D_L), 0x3f, 0x0c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5D_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5E_L), 0x3f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5E_H), 0x3f, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5F_L), 0x3f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_5F_H), 0x3f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_60_L), 0x3f, 0x3e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_60_H), 0x3f, 0x3f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_61_L), 0x3f, 0x3c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_61_H), 0x3f, 0x3d/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_62_L), 0x3f, 0x34/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_62_H), 0x3f, 0x38/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_63_L), 0x3f, 0x28/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_63_H), 0x3f, 0x2c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_64_L), 0x3f, 0x1c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_64_H), 0x3f, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_65_L), 0x3f, 0x14/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_65_H), 0x3f, 0x18/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_66_L), 0x3f, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_66_H), 0x3f, 0x0c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_67_L), 0x3f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_67_H), 0x3f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_68_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_68_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_69_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_69_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6A_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6A_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6B_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6B_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6C_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6C_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6D_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6D_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6E_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6E_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6F_L), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK29_6F_H), 0x3f, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// LDC ++//**************************************************** ++ unsigned char MST_LDC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_LDC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_LDC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK18_03_H), 0x10, 0x00/*OFF*/, ++ 0x10/*ON*/, }, ++ { PQ_MAP_REG(REG_SC_BK24_00_L), 0x01, 0x00/*OFF*/, ++ 0x01/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// LDC_422_444_422 ++//**************************************************** ++ unsigned char MST_LDC_422_444_422_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_LDC_422_444_422_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_LDC_422_444_422_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK24_1D_L), 0x03, 0x02/*md1434_avg*/, }, ++ { PQ_MAP_REG(REG_SC_BK24_1F_L), 0x07, 0x07/*md1434_avg*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// NLM ++//**************************************************** ++ unsigned char MST_NLM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_NLM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_NLM_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK17_01_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_L), 0x02, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_L), 0x04, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x04, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x08, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_01_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_02_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_02_H), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_03_L), 0x0F, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_03_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_04_L), 0x3F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_04_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_04_H), 0x60, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_20_H), 0x3F, 0x1C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_20_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_21_H), 0x3F, 0x18/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_21_L), 0x3F, 0x15/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_22_H), 0x3F, 0x12/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_22_L), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_23_H), 0x3F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_23_L), 0x3F, 0x0C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_24_H), 0x3F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_24_L), 0x3F, 0x09/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_25_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_25_L), 0x3F, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_26_H), 0x3F, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_26_L), 0x3F, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_27_H), 0x3F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_27_L), 0x3F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_28_H), 0x3F, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_28_L), 0x3F, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_29_H), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_29_L), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2A_H), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2A_L), 0x3F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2B_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2B_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2C_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2C_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2D_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2D_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2E_H), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2E_L), 0x3F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_2F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_30_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_30_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_31_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_31_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_32_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_32_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_33_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_33_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_34_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_34_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_35_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_35_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_36_H), 0x1F, 0x0C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_36_L), 0x1F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_37_H), 0x1F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_37_L), 0x1F, 0x0D/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_38_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_38_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_39_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_39_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3A_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3A_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3B_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3B_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3C_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3C_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3D_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3D_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3E_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3E_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3F_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_3F_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_40_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_40_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_41_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_41_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_42_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_42_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_43_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_43_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_44_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_44_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_45_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_45_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_46_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_46_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_47_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_47_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_48_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_48_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_49_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_49_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4A_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4A_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4B_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4B_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4C_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4C_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4D_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4D_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4E_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4E_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4F_H), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_4F_L), 0x1F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_50_H), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_50_L), 0x3F, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_51_H), 0x3F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_51_L), 0x3F, 0x0F/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_52_H), 0x3F, 0x0A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_52_L), 0x3F, 0x0C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_53_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_53_L), 0x3F, 0x09/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_54_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_54_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_55_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_55_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_56_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_56_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_57_H), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_57_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_58_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_58_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_59_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_59_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5A_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5A_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5B_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5B_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_5C_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_10_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_10_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_11_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_11_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_12_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_12_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_13_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_13_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_14_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_14_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_15_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_15_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_16_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_16_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_17_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_17_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_18_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_18_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_19_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_19_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1A_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1A_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1B_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1B_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1C_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1C_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1D_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1D_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1E_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1E_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1F_H), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK17_1F_L), 0x1F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422to444 ++//**************************************************** ++ unsigned char MST_422to444_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422to444_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422to444_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_72_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_72_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP ++//**************************************************** ++ unsigned char MST_VIP_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_70_L), 0x01, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_pseudo ++//**************************************************** ++ unsigned char MST_VIP_pseudo_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_pseudo_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_pseudo_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_78_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_78_L), 0x06, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LineBuffer ++//**************************************************** ++ unsigned char MST_VIP_LineBuffer_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LineBuffer_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LineBuffer_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_HLPF ++//**************************************************** ++ unsigned char MST_VIP_HLPF_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_HLPF_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_HLPF_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x70, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_HLPF_dither ++//**************************************************** ++ unsigned char MST_VIP_HLPF_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_HLPF_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_HLPF_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_VLPF_coef1 ++//**************************************************** ++ unsigned char MST_VIP_VLPF_coef1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_VLPF_coef1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_VLPF_coef1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_12_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_VLPF_coef2 ++//**************************************************** ++ unsigned char MST_VIP_VLPF_coef2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_VLPF_coef2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_VLPF_coef2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_12_H), 0x70, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_VLPF_dither ++//**************************************************** ++ unsigned char MST_VIP_VLPF_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_VLPF_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_VLPF_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking ++//**************************************************** ++ unsigned char MST_VIP_Peaking_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x01, 0x00/*OFF*/, ++ 0x01/*W2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_L), 0x80, 0x80/*OFF*/, ++ 0x80/*W2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_0B_H), 0x40, 0x00/*OFF*/, ++ 0x40/*W2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_0B_L), 0x01, 0x00/*OFF*/, ++ 0x00/*W2*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_band ++//**************************************************** ++ unsigned char MST_VIP_Peaking_band_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_band_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_band_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_10_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_11_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_18_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_18_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_19_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_19_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1A_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1A_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1B_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1B_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1C_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1D_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1E_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_1F_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_20_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_20_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_21_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_21_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_22_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_22_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_23_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_23_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_24_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_24_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_25_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_25_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_26_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_26_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_27_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_27_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_33_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_34_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_38_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_adptive ++//**************************************************** ++ unsigned char MST_VIP_Peaking_adptive_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_adptive_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_adptive_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_31_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_40_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_40_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_41_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_41_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_42_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_42_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_43_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_43_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_44_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_44_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_45_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_45_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_46_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_46_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_47_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_47_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_48_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_48_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_49_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_49_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_4F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6A_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6B_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6C_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_L), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_6D_H), 0xE0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_68_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_68_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_69_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_69_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_6F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_Pcoring ++//**************************************************** ++ unsigned char MST_VIP_Peaking_Pcoring_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_Pcoring_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_Pcoring_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_13_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_13_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_30_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_Pcoring_ad_Y ++//**************************************************** ++ unsigned char MST_VIP_Peaking_Pcoring_ad_Y_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_Pcoring_ad_Y_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_Pcoring_ad_Y_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_70_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_70_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_70_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_70_L), 0x30, 0x30/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_71_L), 0x3F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_71_H), 0x3F, 0x50/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_72_L), 0x3F, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_72_H), 0x3F, 0x70/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_73_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_73_H), 0x3F, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_74_L), 0x3F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_74_H), 0x3F, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_gain ++//**************************************************** ++ unsigned char MST_VIP_Peaking_gain_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_gain_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_gain_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_13_H), 0x7F, 0x10/*0x10*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_3E_L), 0x80, 0x00/*0x10*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_3E_L), 0x7F, 0x00/*0x10*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_3E_H), 0x7F, 0x00/*0x10*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Peaking_gain_ad_Y ++//**************************************************** ++ unsigned char MST_VIP_Peaking_gain_ad_Y_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Peaking_gain_ad_Y_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Peaking_gain_ad_Y_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1D_55_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_55_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_55_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_55_L), 0x30, 0x30/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_L), 0x0F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_L), 0xF0, 0x50/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_H), 0x0F, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_56_H), 0xF0, 0x70/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_L), 0x0F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_L), 0xF0, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_H), 0x0F, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1D_57_H), 0xF0, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE ++//**************************************************** ++ unsigned char MST_VIP_LCE_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_71_H), 0xff, 0x9f/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE_dither ++//**************************************************** ++ unsigned char MST_VIP_LCE_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE_setting ++//**************************************************** ++ unsigned char MST_VIP_LCE_setting_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_setting_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_setting_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x02, 0x02/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x04, 0x04/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x10, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_L), 0x40, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_H), 0x0F, 0x0B/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_10_H), 0xF0, 0x80/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_11_L), 0xFF, 0x02/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_11_H), 0xFF, 0x38/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_12_L), 0x7F, 0x3F/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_12_H), 0xFF, 0x50/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_13_L), 0x3F, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_13_H), 0xFF, 0x10/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_14_L), 0x0F, 0x04/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_14_H), 0x3F, 0x10/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_19_L), 0xFF, 0x40/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_1A_L), 0x3F, 0x10/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_1A_H), 0x0F, 0x08/*S3*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_1B_L), 0x1F, 0x00/*S3*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_LCE_curve ++//**************************************************** ++ unsigned char MST_VIP_LCE_curve_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_LCE_curve_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_LCE_curve_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK21_17_L), 0xFF, 0x08/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_17_H), 0xFF, 0x40/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_18_L), 0xFF, 0x96/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_18_H), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_30_L), 0xFF, 0x0A/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_30_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_31_L), 0xFF, 0x1B/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_31_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_32_L), 0xFF, 0x29/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_32_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_33_L), 0xFF, 0x35/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_33_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_34_L), 0xFF, 0x44/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_34_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_35_L), 0xFF, 0x56/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_35_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_36_L), 0xFF, 0x67/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_36_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_37_L), 0xFF, 0x78/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_37_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_38_L), 0xFF, 0x89/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_38_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_39_L), 0xFF, 0x99/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_39_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3A_L), 0xFF, 0xA8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3A_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3B_L), 0xFF, 0xB6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3B_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3C_L), 0xFF, 0xC5/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3C_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3D_L), 0xFF, 0xD6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3D_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3E_L), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3E_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3F_L), 0xFF, 0xF8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_3F_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_40_L), 0xFF, 0x0A/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_40_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_41_L), 0xFF, 0x1B/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_41_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_42_L), 0xFF, 0x29/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_42_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_43_L), 0xFF, 0x35/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_43_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_44_L), 0xFF, 0x44/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_44_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_45_L), 0xFF, 0x56/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_45_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_46_L), 0xFF, 0x67/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_46_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_47_L), 0xFF, 0x78/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_47_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_48_L), 0xFF, 0x89/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_48_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_49_L), 0xFF, 0x99/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_49_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4A_L), 0xFF, 0xA8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4A_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4B_L), 0xFF, 0xB6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4B_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4C_L), 0xFF, 0xC5/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4C_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4D_L), 0xFF, 0xD6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4D_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4E_L), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4E_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4F_L), 0xFF, 0xF8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_4F_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_50_L), 0xFF, 0x0A/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_50_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_51_L), 0xFF, 0x1B/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_51_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_52_L), 0xFF, 0x29/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_52_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_53_L), 0xFF, 0x35/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_53_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_54_L), 0xFF, 0x44/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_54_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_55_L), 0xFF, 0x56/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_55_H), 0x03, 0x02/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_56_L), 0xFF, 0x67/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_56_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_57_L), 0xFF, 0x78/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_57_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_58_L), 0xFF, 0x89/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_58_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_59_L), 0xFF, 0x99/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_59_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5A_L), 0xFF, 0xA8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5A_H), 0x03, 0x01/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5B_L), 0xFF, 0xB6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5B_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5C_L), 0xFF, 0xC5/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5C_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5D_L), 0xFF, 0xD6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5D_H), 0x03, 0x00/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5E_L), 0xFF, 0xE6/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5E_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5F_L), 0xFF, 0xF8/*CV1*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_5F_H), 0x03, 0x03/*CV1*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_His_range ++//**************************************************** ++ unsigned char MST_VIP_DLC_His_range_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_His_range_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_His_range_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_08_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC ++//**************************************************** ++ unsigned char MST_VIP_DLC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_30_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_10_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_10_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_11_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_11_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_12_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_12_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_13_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_13_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_14_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_14_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_15_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_15_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_16_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_16_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_17_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_17_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_18_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_18_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_19_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_19_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1A_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1A_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1B_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1B_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1C_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1C_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1D_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1D_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1E_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1E_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1F_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_1F_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_20_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_20_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_21_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_21_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_22_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_22_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_23_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_23_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_24_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_24_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_25_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_25_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_26_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_26_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_27_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_27_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_28_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_28_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_29_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_29_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2A_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2A_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2B_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2B_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2C_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2C_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2D_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2D_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2E_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2E_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2F_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_2F_H), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_78_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_79_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7A_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7B_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7C_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7D_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7E_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_L), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0x03, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0x0C, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0x30, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_7F_H), 0xC0, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_40_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_40_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_41_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_41_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_42_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_42_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_43_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_43_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_44_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_44_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_45_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_45_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_46_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_46_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_47_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_47_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_48_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_48_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_49_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_49_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4A_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4A_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4B_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4B_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4C_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4C_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4D_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4D_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4E_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4E_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4F_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_4F_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_50_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_50_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_51_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_51_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_52_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_52_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_53_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_53_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_54_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_54_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_55_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_55_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_56_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_56_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_57_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_57_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_58_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_58_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_59_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_59_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5A_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5A_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5B_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5B_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5C_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5C_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5D_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5D_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5E_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5E_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5F_L), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_5F_H), 0xFF, 0x0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_75_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_77_L), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_77_H), 0x40, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_76_L), 0xFF, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_76_H), 0x01, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_77_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_04_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_04_L), 0x02, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_dither ++//**************************************************** ++ unsigned char MST_VIP_DLC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_04_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_His_rangeH ++//**************************************************** ++ unsigned char MST_VIP_DLC_His_rangeH_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_His_rangeH_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_His_rangeH_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1F_03_L), 0xFF, 0x0C/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_03_H), 0x01, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_04_L), 0xFF, 0xE4/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_04_H), 0x01, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_His_rangeV ++//**************************************************** ++ unsigned char MST_VIP_DLC_His_rangeV_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_His_rangeV_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_His_rangeV_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1F_01_L), 0xFF, 0x06/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_01_H), 0x03, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_02_L), 0xFF, 0x7A/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_02_H), 0x03, 0x00/*90pa_1920*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_DLC_PC ++//**************************************************** ++ unsigned char MST_VIP_DLC_PC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_DLC_PC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_DLC_PC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_04_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_04_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_YC_gain_offset ++//**************************************************** ++ unsigned char MST_VIP_YC_gain_offset_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_YC_gain_offset_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_YC_gain_offset_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_38_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_38_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_39_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_39_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3A_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3B_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3C_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3D_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3E_H), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3F_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_3F_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_UVC ++//**************************************************** ++ unsigned char MST_VIP_UVC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_UVC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_UVC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1E_08_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_08_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_64_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_64_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_65_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1E_65_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_62_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_62_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_63_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_63_H), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_64_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_61_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_79_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7A_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK21_7B_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_full_range ++//**************************************************** ++ unsigned char MST_VIP_FCC_full_range_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_full_range_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_full_range_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_40_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_40_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_41_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_48_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_48_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_49_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_49_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_4F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_45_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_50_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_50_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_51_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_51_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_52_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_52_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_53_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_53_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_54_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_54_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_55_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_55_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_56_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_56_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_57_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_57_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_45_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_58_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_58_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_59_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_59_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5A_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5A_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5B_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5B_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5C_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5C_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5D_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5D_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5E_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5E_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5F_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_5F_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_46_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_60_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_60_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_61_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_61_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_62_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_62_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_63_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_63_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_64_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_64_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_65_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_65_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_66_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_66_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_67_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_67_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1F_46_H), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_bdry_dist ++//**************************************************** ++ unsigned char MST_VIP_FCC_bdry_dist_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_bdry_dist_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_bdry_dist_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T1 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_18_L), 0xFF, 0x73/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_18_H), 0xFF, 0x9B/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_L), 0x0F, 0x84/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0x03, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0x0C, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0x30, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_L), 0xC0, 0xB2/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_45_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_45_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_46_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_46_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_47_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_47_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_48_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_48_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T2 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_19_L), 0xFF, 0x6E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_19_H), 0xFF, 0xAC/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_L), 0xF0, 0x84/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0x03, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0x0C, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0x30, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_24_H), 0xC0, 0xBA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_49_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_49_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T3 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1A_L), 0xFF, 0xA5/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1A_H), 0xFF, 0x70/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_H), 0x0F, 0x44/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_L), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4F_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_4F_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_50_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_50_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T4 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T4_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T4_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T4_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1B_L), 0xFF, 0x53/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1B_H), 0xFF, 0xB3/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_20_H), 0xF0, 0x44/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_25_H), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_41_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_51_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_51_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_52_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_52_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_53_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_53_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_54_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_54_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T5 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T5_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T5_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T5_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1C_L), 0xFF, 0x5A/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1C_H), 0xFF, 0x75/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_L), 0x0F, 0x88/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_L), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_55_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_55_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_56_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_56_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_57_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_57_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_58_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_58_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T6 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T6_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T6_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T6_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1D_L), 0xFF, 0xB0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1D_H), 0xFF, 0x48/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_L), 0xF0, 0x88/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0x03, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0x0C, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0x30, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_26_H), 0xC0, 0xFB/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_59_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_59_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_60_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_60_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_61_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_61_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_62_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_62_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T7 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T7_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T7_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T7_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1E_L), 0xFF, 0x74/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1E_H), 0xFF, 0xC8/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_H), 0x0F, 0x58/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0x03, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0x0C, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0x30, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_L), 0xC0, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_63_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_63_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_64_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_64_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_65_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_65_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_66_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_66_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T8 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T8_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T8_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T8_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1F_L), 0xFF, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_1F_H), 0xFF, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_21_H), 0xF0, 0x58/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0x03, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0x0C, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0x30, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_27_H), 0xC0, 0xAA/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_42_H), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_67_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_67_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_68_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_68_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_69_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_69_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6A_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_FCC_T9 ++//**************************************************** ++ unsigned char MST_VIP_FCC_T9_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_FCC_T9_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_FCC_T9_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_10_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_22_L), 0x0F, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_28_L), 0x07, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_28_L), 0x38, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_10_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_43_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_43_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_44_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_44_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6B_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_6E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC ++//**************************************************** ++ unsigned char MST_VIP_IHC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_24_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC_Ymode ++//**************************************************** ++ unsigned char MST_VIP_IHC_Ymode_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_Ymode_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_Ymode_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_68_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_68_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC_dither ++//**************************************************** ++ unsigned char MST_VIP_IHC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_24_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IHC_CRD_SRAM ++//**************************************************** ++ unsigned char MST_VIP_IHC_CRD_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_CRD_SRAM_Main[][PQ_IP_VIP_IHC_CRD_SRAM_SIZE_Main]= ++{ ++{//15wins3 ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x52,0x00, ++ 0xB2,0x00, ++ 0xC2,0x00, ++ 0x72,0x00, ++ 0x69,0x00, ++ 0x99,0x00, ++ 0xF9,0x00, ++ 0x69,0x01, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xC4,0x01, ++ 0x34,0x01, ++ 0x84,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x82,0x00, ++ 0x22,0x01, ++ 0x42,0x01, ++ 0x02,0x01, ++ 0xA2,0x00, ++ 0x42,0x00, ++ 0x79,0x00, ++ 0xF9,0x00, ++ 0x79,0x01, ++ 0xE4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x74,0x01, ++ 0xA4,0x00, ++ 0x52,0x00, ++ 0x22,0x01, ++ 0x92,0x01, ++ 0x72,0x01, ++ 0x32,0x01, ++ 0xD2,0x00, ++ 0x52,0x00, ++ 0x69,0x00, ++ 0xF9,0x00, ++ 0x89,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x73,0x01, ++ 0x32,0x00, ++ 0x42,0x01, ++ 0x72,0x01, ++ 0x92,0x01, ++ 0x72,0x01, ++ 0x12,0x01, ++ 0x82,0x00, ++ 0x39,0x00, ++ 0xF9,0x00, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x62,0x00, ++ 0x02,0x01, ++ 0x32,0x01, ++ 0x72,0x01, ++ 0x92,0x01, ++ 0x52,0x01, ++ 0xD2,0x00, ++ 0x72,0x00, ++ 0xF9,0x00, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x52,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x12,0x01, ++ 0x52,0x01, ++ 0x92,0x01, ++ 0x32,0x01, ++ 0xD2,0x00, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x52,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x32,0x01, ++ 0x92,0x01, ++ 0x52,0x01, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xE3,0x01, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xD2,0x00, ++ 0x32,0x01, ++ 0x89,0x00, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xC3,0x01, ++ 0xA3,0x01, ++ 0x83,0x01, ++ 0x73,0x01, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x00,0x00, ++ 0x83,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0x06,0x01, ++ 0x16,0x01, ++ 0x26,0x01, ++ 0x46,0x01, ++ 0x66,0x01, ++ 0x96,0x01, ++ 0xB6,0x01, ++ 0xF7,0x00, ++ 0x27,0x01, ++ 0x65,0x00, ++ 0xC5,0x00, ++ 0x45,0x00, ++ 0x33,0x00, ++ 0x53,0x00, ++ 0x73,0x00, ++ 0x83,0x00, ++ 0x66,0x01, ++ 0x76,0x01, ++ 0x96,0x01, ++ 0xB6,0x01, ++ 0xBA,0x01, ++ 0x7A,0x01, ++ 0xE7,0x00, ++ 0xFC,0x00, ++ 0x21,0x01, ++ 0xA5,0x00, ++ 0x75,0x01, ++ 0x25,0x01, ++ 0xC5,0x00, ++ 0x75,0x00, ++ 0x45,0x00, ++ 0x13,0x00, ++ 0x96,0x01, ++ 0xB6,0x01, ++ 0xB6,0x01, ++ 0x96,0x01, ++ 0x5A,0x01, ++ 0xEA,0x00, ++ 0xAB,0x00, ++ 0xA1,0x00, ++ 0x21,0x01, ++ 0x25,0x00, ++ 0x15,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x05,0x01, ++ 0xC5,0x00, ++ 0x95,0x00, ++ 0x46,0x01, ++ 0xA6,0x01, ++ 0x7A,0x01, ++ 0x4A,0x01, ++ 0xEA,0x00, ++ 0x6A,0x00, ++ 0x91,0x00, ++ 0xE1,0x00, ++ 0x21,0x01, ++ 0x61,0x00, ++ 0xA5,0x00, ++ 0x35,0x01, ++ 0x75,0x01, ++ 0x65,0x01, ++ 0x25,0x01, ++ 0xF5,0x00, ++ 0xC6,0x00, ++ 0x6A,0x01, ++ 0x3A,0x01, ++ 0xEA,0x00, ++ 0x8A,0x00, ++ 0x21,0x00, ++ 0xD1,0x00, ++ 0x11,0x01, ++ 0x21,0x01, ++ 0x81,0x00, ++ 0x65,0x00, ++ 0xE5,0x00, ++ 0x45,0x01, ++ 0x75,0x01, ++ 0x65,0x01, ++ 0x45,0x01, ++ 0x4A,0x00, ++ 0xDA,0x00, ++ 0xEA,0x00, ++ 0x9A,0x00, ++ 0x71,0x00, ++ 0x71,0x00, ++ 0x01,0x01, ++ 0x31,0x01, ++ 0x21,0x01, ++ 0xA1,0x00, ++ 0x25,0x00, ++ 0xA5,0x00, ++ 0x15,0x01, ++ 0x55,0x01, ++ 0x75,0x01, ++ 0x15,0x01, ++ 0x00,0x00, ++ 0x4A,0x00, ++ 0x7A,0x00, ++ 0x71,0x00, ++ 0xA1,0x00, ++ 0xA1,0x00, ++ 0x11,0x01, ++ 0x41,0x01, ++ 0x21,0x01, ++ 0xB1,0x00, ++ 0x41,0x00, ++ 0x75,0x00, ++ 0xD5,0x00, ++ 0x25,0x01, ++ 0x05,0x01, ++ 0x75,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x61,0x00, ++ 0xA1,0x00, ++ 0xD1,0x00, ++ 0xD1,0x00, ++ 0x21,0x01, ++ 0x41,0x01, ++ 0x21,0x01, ++ 0xC1,0x00, ++ 0x61,0x00, ++ 0x45,0x00, ++ 0x95,0x00, ++ 0x95,0x00, ++ 0x55,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x83,0x00, ++ 0x33,0x01, ++ 0xC3,0x01, ++ 0xF3,0x01, ++ 0xC3,0x01, ++ 0x63,0x01, ++ 0xF3,0x00, ++ 0x93,0x00, ++ 0x33,0x00, ++ 0x65,0x00, ++ 0xB5,0x00, ++ 0xA5,0x00, ++ 0x55,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x12,0x00, ++ 0x92,0x00, ++ 0xC2,0x00, ++ 0xA2,0x00, ++ 0x49,0x00, ++ 0x99,0x00, ++ 0xB9,0x00, ++ 0x39,0x01, ++ 0x94,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x84,0x01, ++ 0xD4,0x00, ++ 0x24,0x00, ++ 0x00,0x00, ++ 0x22,0x00, ++ 0xD2,0x00, ++ 0x52,0x01, ++ 0x22,0x01, ++ 0xD2,0x00, ++ 0x52,0x00, ++ 0x79,0x00, ++ 0xB9,0x00, ++ 0x39,0x01, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xD4,0x01, ++ 0x04,0x01, ++ 0x34,0x00, ++ 0xB2,0x00, ++ 0x82,0x01, ++ 0x92,0x01, ++ 0x52,0x01, ++ 0x02,0x01, ++ 0x92,0x00, ++ 0x62,0x00, ++ 0xA9,0x00, ++ 0x49,0x01, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xE4,0x01, ++ 0xF3,0x00, ++ 0x02,0x01, ++ 0x62,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x42,0x01, ++ 0xD2,0x00, ++ 0x32,0x00, ++ 0x89,0x00, ++ 0x59,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xB3,0x01, ++ 0xE2,0x00, ++ 0x12,0x01, ++ 0x52,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x22,0x01, ++ 0x72,0x00, ++ 0x69,0x00, ++ 0x69,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x82,0x00, ++ 0xB2,0x00, ++ 0xF2,0x00, ++ 0x32,0x01, ++ 0x82,0x01, ++ 0x72,0x01, ++ 0xD2,0x00, ++ 0x29,0x00, ++ 0x84,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0x02,0x01, ++ 0x72,0x01, ++ 0x52,0x01, ++ 0xD2,0x00, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xD3,0x01, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA2,0x00, ++ 0x32,0x01, ++ 0x92,0x01, ++ 0x94,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xE3,0x01, ++ 0xB3,0x01, ++ 0x93,0x01, ++ 0x73,0x01, ++ 0x63,0x01, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x98,0x00, ++ 0x3F,0x00, ++ 0xE4,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0x06,0x01, ++ 0x16,0x01, ++ 0x36,0x01, ++ 0x56,0x01, ++ 0x76,0x01, ++ 0xB6,0x01, ++ 0xC7,0x00, ++ 0xF7,0x00, ++ 0x65,0x00, ++ 0x25,0x01, ++ 0x75,0x00, ++ 0x33,0x00, ++ 0x43,0x00, ++ 0x63,0x00, ++ 0x73,0x00, ++ 0x83,0x00, ++ 0x66,0x01, ++ 0x86,0x01, ++ 0xA6,0x01, ++ 0xB6,0x01, ++ 0xAA,0x01, ++ 0x4A,0x01, ++ 0xBB,0x00, ++ 0xFE,0x00, ++ 0x61,0x00, ++ 0x35,0x01, ++ 0x65,0x01, ++ 0xF5,0x00, ++ 0xA5,0x00, ++ 0x65,0x00, ++ 0x35,0x00, ++ 0x23,0x00, ++ 0xB6,0x01, ++ 0xB6,0x01, ++ 0xA6,0x01, ++ 0x7A,0x01, ++ 0x2A,0x01, ++ 0x9A,0x00, ++ 0xAB,0x00, ++ 0x11,0x01, ++ 0xA1,0x00, ++ 0xA5,0x00, ++ 0x55,0x01, ++ 0x75,0x01, ++ 0x25,0x01, ++ 0xE5,0x00, ++ 0xA5,0x00, ++ 0x75,0x00, ++ 0xB6,0x01, ++ 0x9A,0x01, ++ 0x6A,0x01, ++ 0x1A,0x01, ++ 0xAA,0x00, ++ 0x31,0x00, ++ 0xE1,0x00, ++ 0x31,0x01, ++ 0xC1,0x00, ++ 0x45,0x00, ++ 0xF5,0x00, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0x05,0x01, ++ 0xD5,0x00, ++ 0x4A,0x01, ++ 0x4A,0x01, ++ 0x0A,0x01, ++ 0xBA,0x00, ++ 0x61,0x00, ++ 0x71,0x00, ++ 0x11,0x01, ++ 0x41,0x01, ++ 0xD1,0x00, ++ 0x15,0x00, ++ 0xA5,0x00, ++ 0x25,0x01, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x05,0x01, ++ 0xAA,0x00, ++ 0x0A,0x01, ++ 0xCA,0x00, ++ 0x6A,0x00, ++ 0x71,0x00, ++ 0xB1,0x00, ++ 0x31,0x01, ++ 0x51,0x01, ++ 0xE1,0x00, ++ 0x61,0x00, ++ 0x65,0x00, ++ 0xD5,0x00, ++ 0x35,0x01, ++ 0x75,0x01, ++ 0x75,0x01, ++ 0xB5,0x00, ++ 0x1A,0x00, ++ 0x6A,0x00, ++ 0x7A,0x00, ++ 0x71,0x00, ++ 0xA1,0x00, ++ 0xD1,0x00, ++ 0x41,0x01, ++ 0x51,0x01, ++ 0xF1,0x00, ++ 0x71,0x00, ++ 0x45,0x00, ++ 0xA5,0x00, ++ 0x05,0x01, ++ 0x35,0x01, ++ 0xC5,0x00, ++ 0x25,0x00, ++ 0x00,0x00, ++ 0x61,0x00, ++ 0x61,0x00, ++ 0xA1,0x00, ++ 0xD1,0x00, ++ 0xF1,0x00, ++ 0x41,0x01, ++ 0x61,0x01, ++ 0xF1,0x00, ++ 0x91,0x00, ++ 0x65,0x00, ++ 0x75,0x00, ++ 0xA5,0x00, ++ 0x75,0x00, ++ 0x15,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x22,0x00, ++ 0xB2,0x00, ++ 0x02,0x01, ++ 0xE2,0x00, ++ 0x82,0x00, ++ 0x59,0x00, ++ 0x89,0x00, ++ 0xF9,0x00, ++ 0x69,0x01, ++ 0xD4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xB4,0x01, ++ 0xF4,0x00, ++ 0x34,0x00, ++ 0x12,0x00, ++ 0xD2,0x00, ++ 0x82,0x01, ++ 0x62,0x01, ++ 0x12,0x01, ++ 0xB2,0x00, ++ 0x52,0x00, ++ 0x79,0x00, ++ 0xF9,0x00, ++ 0x79,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xE4,0x01, ++ 0x04,0x01, ++ 0x92,0x00, ++ 0x52,0x01, ++ 0x92,0x01, ++ 0x82,0x01, ++ 0x52,0x01, ++ 0xF2,0x00, ++ 0x52,0x00, ++ 0x59,0x00, ++ 0xF9,0x00, ++ 0x94,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xD3,0x01, ++ 0x52,0x00, ++ 0x22,0x01, ++ 0x52,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x32,0x01, ++ 0xA2,0x00, ++ 0x29,0x00, ++ 0xF9,0x00, ++ 0xB4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x62,0x00, ++ 0xD2,0x00, ++ 0x02,0x01, ++ 0x42,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x02,0x01, ++ 0xA2,0x00, ++ 0xF9,0x00, ++ 0xE4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x22,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x22,0x01, ++ 0x72,0x01, ++ 0x72,0x01, ++ 0x12,0x01, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x52,0x01, ++ 0x92,0x01, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xE3,0x01, ++ 0xC3,0x01, ++ 0xA3,0x01, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD2,0x00, ++ 0x79,0x00, ++ 0x94,0x01, ++ 0xC3,0x01, ++ 0x83,0x01, ++ 0x63,0x01, ++ 0x43,0x01, ++ 0x43,0x01, ++ 0x33,0x01, ++ 0xD6,0x00, ++ 0xD6,0x00, ++ 0xE6,0x00, ++ 0xF6,0x00, ++ 0x06,0x01, ++ 0x26,0x01, ++ 0x66,0x01, ++ 0x4D,0x01, ++ 0x25,0x01, ++ 0x65,0x00, ++ 0x25,0x00, ++ 0x73,0x00, ++ 0x93,0x00, ++ 0xA3,0x00, ++ 0xB3,0x00, ++ 0xB3,0x00, ++ 0x36,0x01, ++ 0x46,0x01, ++ 0x66,0x01, ++ 0x86,0x01, ++ 0xA6,0x01, ++ 0xB6,0x01, ++ 0x67,0x00, ++ 0xF7,0x00, ++ 0x21,0x01, ++ 0x65,0x00, ++ 0x55,0x01, ++ 0xC5,0x00, ++ 0x65,0x00, ++ 0x33,0x00, ++ 0x33,0x00, ++ 0x43,0x00, ++ 0x86,0x01, ++ 0xA6,0x01, ++ 0xB6,0x01, ++ 0xB6,0x01, ++ 0x9A,0x01, ++ 0x3A,0x01, ++ 0xAB,0x00, ++ 0xAB,0x00, ++ 0x21,0x01, ++ 0x65,0x00, ++ 0x45,0x01, ++ 0x65,0x01, ++ 0x15,0x01, ++ 0xC5,0x00, ++ 0x85,0x00, ++ 0x55,0x00, ++ 0x76,0x01, ++ 0xB6,0x01, ++ 0xAA,0x01, ++ 0x7A,0x01, ++ 0x1A,0x01, ++ 0xAA,0x00, ++ 0x71,0x00, ++ 0xD1,0x00, ++ 0x21,0x01, ++ 0x41,0x00, ++ 0xD5,0x00, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x35,0x01, ++ 0xF5,0x00, ++ 0xC5,0x00, ++ 0x06,0x01, ++ 0x8A,0x01, ++ 0x5A,0x01, ++ 0x1A,0x01, ++ 0xBA,0x00, ++ 0x51,0x00, ++ 0xB1,0x00, ++ 0x01,0x01, ++ 0x21,0x01, ++ 0x71,0x00, ++ 0x85,0x00, ++ 0x15,0x01, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x15,0x01, ++ 0x8A,0x00, ++ 0x3A,0x01, ++ 0x0A,0x01, ++ 0xBA,0x00, ++ 0x51,0x00, ++ 0x51,0x00, ++ 0xE1,0x00, ++ 0x21,0x01, ++ 0x21,0x01, ++ 0x91,0x00, ++ 0x45,0x00, ++ 0xC5,0x00, ++ 0x25,0x01, ++ 0x75,0x01, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0x1A,0x00, ++ 0x8A,0x00, ++ 0xCA,0x00, ++ 0x51,0x00, ++ 0x91,0x00, ++ 0x91,0x00, ++ 0x11,0x01, ++ 0x31,0x01, ++ 0x21,0x01, ++ 0xB1,0x00, ++ 0x15,0x00, ++ 0x85,0x00, ++ 0xF5,0x00, ++ 0x45,0x01, ++ 0x65,0x01, ++ 0xC5,0x00, ++ 0x00,0x00, ++ 0x21,0x00, ++ 0x61,0x00, ++ 0x81,0x00, ++ 0xB1,0x00, ++ 0xB1,0x00, ++ 0x21,0x01, ++ 0x41,0x01, ++ 0x21,0x01, ++ 0xC1,0x00, ++ 0x51,0x00, ++ 0x65,0x00, ++ 0xB5,0x00, ++ 0xE5,0x00, ++ 0xA5,0x00, ++ 0x25,0x00, ++ 0x00,0x00, ++ 0x23,0x00, ++ 0xD3,0x00, ++ 0x83,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x93,0x01, ++ 0x23,0x01, ++ 0xC3,0x00, ++ 0x63,0x00, ++ 0x35,0x00, ++ 0x95,0x00, ++ 0xB5,0x00, ++ 0x85,0x00, ++ 0x15,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x72,0x00, ++ 0xE2,0x00, ++ 0x12,0x01, ++ 0xB2,0x00, ++ 0x49,0x00, ++ 0x89,0x00, ++ 0xB9,0x00, ++ 0x39,0x01, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x54,0x01, ++ 0x94,0x00, ++ 0x00,0x00, ++ 0x72,0x00, ++ 0x32,0x01, ++ 0x82,0x01, ++ 0x42,0x01, ++ 0xE2,0x00, ++ 0x82,0x00, ++ 0x79,0x00, ++ 0xA9,0x00, ++ 0x39,0x01, ++ 0xB4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x74,0x01, ++ 0x93,0x00, ++ 0xE2,0x00, ++ 0x82,0x01, ++ 0x92,0x01, ++ 0x72,0x01, ++ 0x22,0x01, ++ 0xB2,0x00, ++ 0x52,0x00, ++ 0x99,0x00, ++ 0x49,0x01, ++ 0xD4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0x53,0x01, ++ 0x12,0x01, ++ 0x42,0x01, ++ 0x72,0x01, ++ 0x92,0x01, ++ 0x62,0x01, ++ 0xF2,0x00, ++ 0x22,0x00, ++ 0x79,0x00, ++ 0x59,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xB2,0x00, ++ 0xE2,0x00, ++ 0x22,0x01, ++ 0x62,0x01, ++ 0x92,0x01, ++ 0x42,0x01, ++ 0xA2,0x00, ++ 0x49,0x00, ++ 0x79,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xB2,0x00, ++ 0xF2,0x00, ++ 0x42,0x01, ++ 0x92,0x01, ++ 0x12,0x01, ++ 0x82,0x00, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA8,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0x12,0x01, ++ 0x92,0x01, ++ 0x32,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xD3,0x01, ++ 0xB3,0x01, ++ 0xA3,0x01, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD2,0x00, ++ 0xD2,0x00, ++ 0xF4,0x00, ++ 0xF3,0x01, ++ 0xA3,0x01, ++ 0x73,0x01, ++ 0x53,0x01, ++ 0x43,0x01, ++ 0x33,0x01, ++ 0x33,0x01, ++ 0xD6,0x00, ++ 0xD6,0x00, ++ 0xE6,0x00, ++ 0xF6,0x00, ++ 0x16,0x01, ++ 0x46,0x01, ++ 0x4D,0x01, ++ 0xFD,0x00, ++ 0x65,0x00, ++ 0x45,0x00, ++ 0x53,0x00, ++ 0x83,0x00, ++ 0x93,0x00, ++ 0xA3,0x00, ++ 0xB3,0x00, ++ 0xC3,0x00, ++ 0x46,0x01, ++ 0x56,0x01, ++ 0x76,0x01, ++ 0x96,0x01, ++ 0xB6,0x01, ++ 0x96,0x01, ++ 0xF7,0x00, ++ 0xFE,0x00, ++ 0x65,0x00, ++ 0x75,0x01, ++ 0x05,0x01, ++ 0x65,0x00, ++ 0x65,0x00, ++ 0x23,0x00, ++ 0x33,0x00, ++ 0x53,0x00, ++ 0x96,0x01, ++ 0xA6,0x01, ++ 0xB6,0x01, ++ 0xAA,0x01, ++ 0x6A,0x01, ++ 0xEA,0x00, ++ 0xAB,0x00, ++ 0xE1,0x00, ++ 0x81,0x00, ++ 0xE5,0x00, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0xE5,0x00, ++ 0xA5,0x00, ++ 0x75,0x00, ++ 0x45,0x00, ++ 0xB6,0x01, ++ 0xA6,0x01, ++ 0x8A,0x01, ++ 0x4A,0x01, ++ 0xEA,0x00, ++ 0x5A,0x00, ++ 0xD1,0x00, ++ 0x21,0x01, ++ 0xB1,0x00, ++ 0x75,0x00, ++ 0x25,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x15,0x01, ++ 0xE5,0x00, ++ 0xB5,0x00, ++ 0x96,0x01, ++ 0x7A,0x01, ++ 0x3A,0x01, ++ 0xEA,0x00, ++ 0x7A,0x00, ++ 0x41,0x00, ++ 0x01,0x01, ++ 0x41,0x01, ++ 0xD1,0x00, ++ 0x25,0x00, ++ 0xC5,0x00, ++ 0x45,0x01, ++ 0x75,0x01, ++ 0x65,0x01, ++ 0x35,0x01, ++ 0x05,0x01, ++ 0xFA,0x00, ++ 0x2A,0x01, ++ 0xEA,0x00, ++ 0x9A,0x00, ++ 0x51,0x00, ++ 0x91,0x00, ++ 0x21,0x01, ++ 0x51,0x01, ++ 0xE1,0x00, ++ 0x41,0x00, ++ 0x85,0x00, ++ 0xF5,0x00, ++ 0x55,0x01, ++ 0x75,0x01, ++ 0x75,0x01, ++ 0xE5,0x00, ++ 0x5A,0x00, ++ 0xBA,0x00, ++ 0xAA,0x00, ++ 0x51,0x00, ++ 0x91,0x00, ++ 0xC1,0x00, ++ 0x31,0x01, ++ 0x51,0x01, ++ 0xE1,0x00, ++ 0x71,0x00, ++ 0x55,0x00, ++ 0xC5,0x00, ++ 0x15,0x01, ++ 0x55,0x01, ++ 0x25,0x01, ++ 0x75,0x00, ++ 0x00,0x00, ++ 0x61,0x00, ++ 0x61,0x00, ++ 0x81,0x00, ++ 0xB1,0x00, ++ 0xE1,0x00, ++ 0x41,0x01, ++ 0x51,0x01, ++ 0xF1,0x00, ++ 0x81,0x00, ++ 0x65,0x00, ++ 0x95,0x00, ++ 0xE5,0x00, ++ 0xD5,0x00, ++ 0x65,0x00, ++ 0x00,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// VIP_IHC_SETTING ++//**************************************************** ++ unsigned char MST_VIP_IHC_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IHC_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IHC_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_25_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_38_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_40_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_48_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_25_H), 0x7F, 0x1E/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_38_H), 0x7F, 0x17/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_40_H), 0x7F, 0x24/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_48_H), 0x7F, 0x2A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_26_L), 0x7F, 0x67/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_39_L), 0x7F, 0x54/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_41_L), 0x7F, 0x6A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_49_L), 0x7F, 0x65/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_26_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_39_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_41_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_49_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_27_L), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3A_L), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_42_L), 0x7F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4A_L), 0x7F, 0x49/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_27_H), 0x7F, 0x50/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3A_H), 0x7F, 0x4F/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_42_H), 0x7F, 0x50/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4A_H), 0x7F, 0x50/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_28_L), 0x7F, 0x15/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3B_L), 0x7F, 0x1B/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_43_L), 0x7F, 0x1A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4B_L), 0x7F, 0x1D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_28_H), 0x7F, 0x21/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3B_H), 0x7F, 0x1E/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_43_H), 0x7F, 0x23/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4B_H), 0x7F, 0x1D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_29_L), 0x7F, 0x51/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3C_L), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_44_L), 0x7F, 0x15/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4C_L), 0x7F, 0x42/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_29_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3C_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_44_H), 0x7F, 0x4C/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4C_H), 0x7F, 0x54/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2A_L), 0x7F, 0x11/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3D_L), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_45_L), 0x7F, 0x0C/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4D_L), 0x7F, 0x19/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2A_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3D_H), 0x7F, 0x18/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_45_H), 0x7F, 0x1D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4D_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2B_L), 0x7F, 0x5D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3E_L), 0x7F, 0x1E/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_46_L), 0x7F, 0x1C/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4E_L), 0x7F, 0x22/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2B_H), 0x7F, 0x1A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3E_H), 0x7F, 0x14/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_46_H), 0x7F, 0x14/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4E_H), 0x7F, 0x27/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2C_L), 0x7F, 0x26/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3F_L), 0x7F, 0x2D/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_47_L), 0x7F, 0x26/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4F_L), 0x7F, 0x41/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_2C_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_3F_H), 0x7F, 0x40/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_47_H), 0x7F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_4F_H), 0x7F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC ++//**************************************************** ++ unsigned char MST_VIP_ICC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_60_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_60_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6B_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6B_H), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6C_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_6C_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC_Ymode ++//**************************************************** ++ unsigned char MST_VIP_ICC_Ymode_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_Ymode_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_Ymode_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_50_L), 0x80, 0x80/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_50_L), 0x02, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_38_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_40_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_48_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_38_H), 0x0F, 0x07/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_40_H), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_48_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_39_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_41_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_49_L), 0x0F, 0x08/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_39_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_41_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_49_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3A_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x10, 0x10/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_42_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x10, 0x10/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4A_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3A_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_42_H), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4A_H), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3B_L), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_43_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4B_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3B_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_43_H), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4B_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3C_L), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_44_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4C_L), 0x0F, 0x08/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3C_H), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_44_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4C_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3D_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_45_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4D_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3D_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_45_H), 0x0F, 0x07/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4D_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3E_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_46_L), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4E_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3E_H), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_46_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4E_H), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3F_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_47_L), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4F_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_3F_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_51_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_47_H), 0x0F, 0x07/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_53_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_4F_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_55_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC_dither ++//**************************************************** ++ unsigned char MST_VIP_ICC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_60_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ICC_CRD_SRAM ++//**************************************************** ++ unsigned char MST_VIP_ICC_CRD_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_CRD_SRAM_Main[][PQ_IP_VIP_ICC_CRD_SRAM_SIZE_Main]= ++{ ++{//15wins3 ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x52,0x00, ++ 0xB2,0x00, ++ 0xC2,0x00, ++ 0x72,0x00, ++ 0x69,0x00, ++ 0x99,0x00, ++ 0xF9,0x00, ++ 0x69,0x01, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xC4,0x01, ++ 0x34,0x01, ++ 0x84,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x82,0x00, ++ 0x22,0x01, ++ 0x42,0x01, ++ 0x02,0x01, ++ 0xA2,0x00, ++ 0x42,0x00, ++ 0x79,0x00, ++ 0xF9,0x00, ++ 0x79,0x01, ++ 0xE4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x74,0x01, ++ 0xA4,0x00, ++ 0x52,0x00, ++ 0x22,0x01, ++ 0x92,0x01, ++ 0x72,0x01, ++ 0x32,0x01, ++ 0xD2,0x00, ++ 0x52,0x00, ++ 0x69,0x00, ++ 0xF9,0x00, ++ 0x89,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x73,0x01, ++ 0x32,0x00, ++ 0x42,0x01, ++ 0x72,0x01, ++ 0x92,0x01, ++ 0x72,0x01, ++ 0x12,0x01, ++ 0x82,0x00, ++ 0x39,0x00, ++ 0xF9,0x00, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x62,0x00, ++ 0x02,0x01, ++ 0x32,0x01, ++ 0x72,0x01, ++ 0x92,0x01, ++ 0x52,0x01, ++ 0xD2,0x00, ++ 0x72,0x00, ++ 0xF9,0x00, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x52,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x12,0x01, ++ 0x52,0x01, ++ 0x92,0x01, ++ 0x32,0x01, ++ 0xD2,0x00, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x52,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x32,0x01, ++ 0x92,0x01, ++ 0x52,0x01, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xE3,0x01, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xD2,0x00, ++ 0x32,0x01, ++ 0x89,0x00, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xC3,0x01, ++ 0xA3,0x01, ++ 0x83,0x01, ++ 0x73,0x01, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x00,0x00, ++ 0x83,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0x26,0x00, ++ 0x36,0x00, ++ 0x46,0x00, ++ 0x56,0x00, ++ 0x66,0x00, ++ 0x86,0x00, ++ 0xB6,0x00, ++ 0xF7,0x00, ++ 0x27,0x01, ++ 0x65,0x00, ++ 0xC5,0x00, ++ 0x45,0x00, ++ 0x33,0x00, ++ 0x53,0x00, ++ 0x73,0x00, ++ 0x83,0x00, ++ 0xA6,0x00, ++ 0x96,0x00, ++ 0x66,0x00, ++ 0x76,0x00, ++ 0x2A,0x00, ++ 0x8A,0x00, ++ 0xE7,0x00, ++ 0xFC,0x00, ++ 0x21,0x01, ++ 0xA5,0x00, ++ 0x75,0x01, ++ 0x25,0x01, ++ 0xC5,0x00, ++ 0x75,0x00, ++ 0x45,0x00, ++ 0x13,0x00, ++ 0xA6,0x00, ++ 0x96,0x00, ++ 0x66,0x00, ++ 0x66,0x00, ++ 0xBA,0x00, ++ 0xEA,0x00, ++ 0x5B,0x00, ++ 0xA1,0x00, ++ 0x21,0x01, ++ 0x25,0x00, ++ 0x15,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x05,0x01, ++ 0xC5,0x00, ++ 0x95,0x00, ++ 0x86,0x00, ++ 0x66,0x00, ++ 0x8A,0x00, ++ 0xCA,0x00, ++ 0xEA,0x00, ++ 0x7A,0x00, ++ 0x91,0x00, ++ 0xE1,0x00, ++ 0x21,0x01, ++ 0x61,0x00, ++ 0xA5,0x00, ++ 0x35,0x01, ++ 0x75,0x01, ++ 0x65,0x01, ++ 0x25,0x01, ++ 0xF5,0x00, ++ 0x66,0x00, ++ 0xAA,0x00, ++ 0xDA,0x00, ++ 0xEA,0x00, ++ 0x9A,0x00, ++ 0x21,0x00, ++ 0xD1,0x00, ++ 0x11,0x01, ++ 0x21,0x01, ++ 0x81,0x00, ++ 0x65,0x00, ++ 0xE5,0x00, ++ 0x45,0x01, ++ 0x75,0x01, ++ 0x65,0x01, ++ 0x45,0x01, ++ 0x2A,0x00, ++ 0xAA,0x00, ++ 0xEA,0x00, ++ 0xAA,0x00, ++ 0x71,0x00, ++ 0x71,0x00, ++ 0x01,0x01, ++ 0x31,0x01, ++ 0x21,0x01, ++ 0xA1,0x00, ++ 0x25,0x00, ++ 0xA5,0x00, ++ 0x15,0x01, ++ 0x55,0x01, ++ 0x75,0x01, ++ 0x15,0x01, ++ 0x00,0x00, ++ 0x4A,0x00, ++ 0x8A,0x00, ++ 0x71,0x00, ++ 0xA1,0x00, ++ 0xA1,0x00, ++ 0x11,0x01, ++ 0x41,0x01, ++ 0x21,0x01, ++ 0xB1,0x00, ++ 0x41,0x00, ++ 0x75,0x00, ++ 0xD5,0x00, ++ 0x25,0x01, ++ 0x05,0x01, ++ 0x75,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x61,0x00, ++ 0xA1,0x00, ++ 0xD1,0x00, ++ 0xD1,0x00, ++ 0x21,0x01, ++ 0x41,0x01, ++ 0x21,0x01, ++ 0xC1,0x00, ++ 0x61,0x00, ++ 0x45,0x00, ++ 0x95,0x00, ++ 0x95,0x00, ++ 0x55,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x83,0x00, ++ 0x33,0x01, ++ 0xC3,0x01, ++ 0xF3,0x01, ++ 0xC3,0x01, ++ 0x63,0x01, ++ 0xF3,0x00, ++ 0x93,0x00, ++ 0x33,0x00, ++ 0x65,0x00, ++ 0xB5,0x00, ++ 0xA5,0x00, ++ 0x55,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x12,0x00, ++ 0x92,0x00, ++ 0xC2,0x00, ++ 0xA2,0x00, ++ 0x49,0x00, ++ 0x99,0x00, ++ 0xB9,0x00, ++ 0x39,0x01, ++ 0x94,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x84,0x01, ++ 0xD4,0x00, ++ 0x24,0x00, ++ 0x00,0x00, ++ 0x22,0x00, ++ 0xD2,0x00, ++ 0x52,0x01, ++ 0x22,0x01, ++ 0xD2,0x00, ++ 0x52,0x00, ++ 0x79,0x00, ++ 0xB9,0x00, ++ 0x39,0x01, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xD4,0x01, ++ 0x04,0x01, ++ 0x34,0x00, ++ 0xB2,0x00, ++ 0x82,0x01, ++ 0x92,0x01, ++ 0x52,0x01, ++ 0x02,0x01, ++ 0x92,0x00, ++ 0x62,0x00, ++ 0xA9,0x00, ++ 0x49,0x01, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xE4,0x01, ++ 0xF3,0x00, ++ 0x02,0x01, ++ 0x62,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x42,0x01, ++ 0xD2,0x00, ++ 0x32,0x00, ++ 0x89,0x00, ++ 0x59,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xB3,0x01, ++ 0xE2,0x00, ++ 0x12,0x01, ++ 0x52,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x22,0x01, ++ 0x72,0x00, ++ 0x69,0x00, ++ 0x69,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x82,0x00, ++ 0xB2,0x00, ++ 0xF2,0x00, ++ 0x32,0x01, ++ 0x82,0x01, ++ 0x72,0x01, ++ 0xD2,0x00, ++ 0x29,0x00, ++ 0x84,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0x02,0x01, ++ 0x72,0x01, ++ 0x52,0x01, ++ 0xD2,0x00, ++ 0xC4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xD3,0x01, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA2,0x00, ++ 0x32,0x01, ++ 0x92,0x01, ++ 0x94,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xE3,0x01, ++ 0xB3,0x01, ++ 0x93,0x01, ++ 0x73,0x01, ++ 0x63,0x01, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x88,0x00, ++ 0x3F,0x00, ++ 0xE4,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0xF3,0x00, ++ 0x36,0x00, ++ 0x36,0x00, ++ 0x46,0x00, ++ 0x56,0x00, ++ 0x76,0x00, ++ 0x96,0x00, ++ 0xC7,0x00, ++ 0xF7,0x00, ++ 0x65,0x00, ++ 0x25,0x01, ++ 0x75,0x00, ++ 0x33,0x00, ++ 0x43,0x00, ++ 0x63,0x00, ++ 0x73,0x00, ++ 0x83,0x00, ++ 0xA6,0x00, ++ 0x76,0x00, ++ 0x46,0x00, ++ 0x56,0x00, ++ 0x5A,0x00, ++ 0xCA,0x00, ++ 0xBB,0x00, ++ 0xFE,0x00, ++ 0x61,0x00, ++ 0x35,0x01, ++ 0x65,0x01, ++ 0xF5,0x00, ++ 0xA5,0x00, ++ 0x65,0x00, ++ 0x35,0x00, ++ 0x23,0x00, ++ 0xA6,0x00, ++ 0x76,0x00, ++ 0x46,0x00, ++ 0x8A,0x00, ++ 0xDA,0x00, ++ 0xAA,0x00, ++ 0xAB,0x00, ++ 0x11,0x01, ++ 0xA1,0x00, ++ 0xA5,0x00, ++ 0x55,0x01, ++ 0x75,0x01, ++ 0x25,0x01, ++ 0xE5,0x00, ++ 0xA5,0x00, ++ 0x75,0x00, ++ 0x76,0x00, ++ 0x6A,0x00, ++ 0xAA,0x00, ++ 0xEA,0x00, ++ 0xBA,0x00, ++ 0x31,0x00, ++ 0xE1,0x00, ++ 0x31,0x01, ++ 0xC1,0x00, ++ 0x45,0x00, ++ 0xF5,0x00, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0x05,0x01, ++ 0xD5,0x00, ++ 0x7A,0x00, ++ 0xBA,0x00, ++ 0xEA,0x00, ++ 0xCA,0x00, ++ 0x61,0x00, ++ 0x71,0x00, ++ 0x11,0x01, ++ 0x41,0x01, ++ 0xD1,0x00, ++ 0x15,0x00, ++ 0xA5,0x00, ++ 0x25,0x01, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x05,0x01, ++ 0x6A,0x00, ++ 0xEA,0x00, ++ 0xCA,0x00, ++ 0x7A,0x00, ++ 0x71,0x00, ++ 0xB1,0x00, ++ 0x31,0x01, ++ 0x51,0x01, ++ 0xE1,0x00, ++ 0x61,0x00, ++ 0x65,0x00, ++ 0xD5,0x00, ++ 0x35,0x01, ++ 0x75,0x01, ++ 0x75,0x01, ++ 0xB5,0x00, ++ 0x1A,0x00, ++ 0x7A,0x00, ++ 0x8A,0x00, ++ 0x71,0x00, ++ 0xA1,0x00, ++ 0xD1,0x00, ++ 0x41,0x01, ++ 0x51,0x01, ++ 0xF1,0x00, ++ 0x71,0x00, ++ 0x45,0x00, ++ 0xA5,0x00, ++ 0x05,0x01, ++ 0x35,0x01, ++ 0xC5,0x00, ++ 0x25,0x00, ++ 0x00,0x00, ++ 0x61,0x00, ++ 0x61,0x00, ++ 0xA1,0x00, ++ 0xD1,0x00, ++ 0xF1,0x00, ++ 0x41,0x01, ++ 0x61,0x01, ++ 0xF1,0x00, ++ 0x91,0x00, ++ 0x65,0x00, ++ 0x75,0x00, ++ 0xA5,0x00, ++ 0x75,0x00, ++ 0x15,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x22,0x00, ++ 0xB2,0x00, ++ 0x02,0x01, ++ 0xE2,0x00, ++ 0x82,0x00, ++ 0x59,0x00, ++ 0x89,0x00, ++ 0xF9,0x00, ++ 0x69,0x01, ++ 0xD4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xB4,0x01, ++ 0xF4,0x00, ++ 0x34,0x00, ++ 0x12,0x00, ++ 0xD2,0x00, ++ 0x82,0x01, ++ 0x62,0x01, ++ 0x12,0x01, ++ 0xB2,0x00, ++ 0x52,0x00, ++ 0x79,0x00, ++ 0xF9,0x00, ++ 0x79,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xE4,0x01, ++ 0x04,0x01, ++ 0x92,0x00, ++ 0x52,0x01, ++ 0x92,0x01, ++ 0x82,0x01, ++ 0x52,0x01, ++ 0xF2,0x00, ++ 0x52,0x00, ++ 0x59,0x00, ++ 0xF9,0x00, ++ 0x94,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xD3,0x01, ++ 0x52,0x00, ++ 0x22,0x01, ++ 0x52,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x32,0x01, ++ 0xA2,0x00, ++ 0x29,0x00, ++ 0xF9,0x00, ++ 0xB4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x62,0x00, ++ 0xD2,0x00, ++ 0x02,0x01, ++ 0x42,0x01, ++ 0x82,0x01, ++ 0x82,0x01, ++ 0x02,0x01, ++ 0xA2,0x00, ++ 0xF9,0x00, ++ 0xE4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x22,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x22,0x01, ++ 0x72,0x01, ++ 0x72,0x01, ++ 0x12,0x01, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA8,0x00, ++ 0xA8,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xD2,0x00, ++ 0x52,0x01, ++ 0x92,0x01, ++ 0xF9,0x00, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xE3,0x01, ++ 0xC3,0x01, ++ 0xA3,0x01, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD2,0x00, ++ 0x79,0x00, ++ 0x94,0x01, ++ 0xC3,0x01, ++ 0x83,0x01, ++ 0x63,0x01, ++ 0x43,0x01, ++ 0x43,0x01, ++ 0x33,0x01, ++ 0x26,0x00, ++ 0x36,0x00, ++ 0x46,0x00, ++ 0x56,0x00, ++ 0x66,0x00, ++ 0x86,0x00, ++ 0xB6,0x00, ++ 0x4D,0x01, ++ 0x25,0x01, ++ 0x65,0x00, ++ 0x25,0x00, ++ 0x73,0x00, ++ 0x93,0x00, ++ 0xA3,0x00, ++ 0xB3,0x00, ++ 0xB3,0x00, ++ 0x96,0x00, ++ 0xA6,0x00, ++ 0xB6,0x00, ++ 0xB6,0x00, ++ 0x66,0x00, ++ 0x66,0x00, ++ 0x67,0x00, ++ 0xF7,0x00, ++ 0x21,0x01, ++ 0x65,0x00, ++ 0x55,0x01, ++ 0xC5,0x00, ++ 0x65,0x00, ++ 0x33,0x00, ++ 0x33,0x00, ++ 0x43,0x00, ++ 0xA6,0x00, ++ 0x96,0x00, ++ 0x66,0x00, ++ 0x66,0x00, ++ 0x7A,0x00, ++ 0xDA,0x00, ++ 0x9B,0x00, ++ 0x7B,0x00, ++ 0x21,0x01, ++ 0x65,0x00, ++ 0x45,0x01, ++ 0x65,0x01, ++ 0x15,0x01, ++ 0xC5,0x00, ++ 0x85,0x00, ++ 0x55,0x00, ++ 0x86,0x00, ++ 0x66,0x00, ++ 0x5A,0x00, ++ 0x9A,0x00, ++ 0xEA,0x00, ++ 0xBA,0x00, ++ 0x71,0x00, ++ 0xD1,0x00, ++ 0x21,0x01, ++ 0x41,0x00, ++ 0xD5,0x00, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x35,0x01, ++ 0xF5,0x00, ++ 0xC5,0x00, ++ 0x56,0x00, ++ 0x7A,0x00, ++ 0xBA,0x00, ++ 0xEA,0x00, ++ 0xCA,0x00, ++ 0x51,0x00, ++ 0xB1,0x00, ++ 0x01,0x01, ++ 0x21,0x01, ++ 0x71,0x00, ++ 0x85,0x00, ++ 0x15,0x01, ++ 0x65,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x15,0x01, ++ 0x3A,0x00, ++ 0xBA,0x00, ++ 0xEA,0x00, ++ 0xCA,0x00, ++ 0x51,0x00, ++ 0x51,0x00, ++ 0xE1,0x00, ++ 0x21,0x01, ++ 0x21,0x01, ++ 0x91,0x00, ++ 0x45,0x00, ++ 0xC5,0x00, ++ 0x25,0x01, ++ 0x75,0x01, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0x1A,0x00, ++ 0x7A,0x00, ++ 0xCA,0x00, ++ 0x51,0x00, ++ 0x91,0x00, ++ 0x91,0x00, ++ 0x11,0x01, ++ 0x31,0x01, ++ 0x21,0x01, ++ 0xB1,0x00, ++ 0x15,0x00, ++ 0x85,0x00, ++ 0xF5,0x00, ++ 0x45,0x01, ++ 0x65,0x01, ++ 0xC5,0x00, ++ 0x00,0x00, ++ 0x21,0x00, ++ 0x61,0x00, ++ 0x81,0x00, ++ 0xB1,0x00, ++ 0xB1,0x00, ++ 0x21,0x01, ++ 0x41,0x01, ++ 0x21,0x01, ++ 0xC1,0x00, ++ 0x51,0x00, ++ 0x65,0x00, ++ 0xB5,0x00, ++ 0xE5,0x00, ++ 0xA5,0x00, ++ 0x25,0x00, ++ 0x00,0x00, ++ 0x23,0x00, ++ 0xD3,0x00, ++ 0x83,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0x93,0x01, ++ 0x23,0x01, ++ 0xC3,0x00, ++ 0x63,0x00, ++ 0x35,0x00, ++ 0x95,0x00, ++ 0xB5,0x00, ++ 0x85,0x00, ++ 0x15,0x00, ++ 0x00,0x00, ++ 0x00,0x00, ++ 0x72,0x00, ++ 0xE2,0x00, ++ 0x12,0x01, ++ 0xB2,0x00, ++ 0x42,0x00, ++ 0x89,0x00, ++ 0xB9,0x00, ++ 0x39,0x01, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x54,0x01, ++ 0x94,0x00, ++ 0x00,0x00, ++ 0x72,0x00, ++ 0x32,0x01, ++ 0x82,0x01, ++ 0x42,0x01, ++ 0xE2,0x00, ++ 0x82,0x00, ++ 0x79,0x00, ++ 0xA9,0x00, ++ 0x39,0x01, ++ 0xB4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0x74,0x01, ++ 0x93,0x00, ++ 0xE2,0x00, ++ 0x82,0x01, ++ 0x92,0x01, ++ 0x72,0x01, ++ 0x22,0x01, ++ 0xB2,0x00, ++ 0x52,0x00, ++ 0x99,0x00, ++ 0x49,0x01, ++ 0xD4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0x53,0x01, ++ 0x12,0x01, ++ 0x42,0x01, ++ 0x72,0x01, ++ 0x92,0x01, ++ 0x62,0x01, ++ 0xF2,0x00, ++ 0x22,0x00, ++ 0x79,0x00, ++ 0x59,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xB2,0x00, ++ 0xE2,0x00, ++ 0x22,0x01, ++ 0x62,0x01, ++ 0x92,0x01, ++ 0x42,0x01, ++ 0xA2,0x00, ++ 0x49,0x00, ++ 0x79,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xB2,0x00, ++ 0xF2,0x00, ++ 0x42,0x01, ++ 0x92,0x01, ++ 0x12,0x01, ++ 0x82,0x00, ++ 0xA4,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xA8,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0xA2,0x00, ++ 0x12,0x01, ++ 0x92,0x01, ++ 0x32,0x01, ++ 0xF4,0x01, ++ 0xF4,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xF3,0x01, ++ 0xD3,0x01, ++ 0xB3,0x01, ++ 0xA3,0x01, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD8,0x00, ++ 0xD2,0x00, ++ 0xD2,0x00, ++ 0xF4,0x00, ++ 0xF3,0x01, ++ 0xA3,0x01, ++ 0x73,0x01, ++ 0x53,0x01, ++ 0x43,0x01, ++ 0x33,0x01, ++ 0x33,0x01, ++ 0x36,0x00, ++ 0x36,0x00, ++ 0x46,0x00, ++ 0x56,0x00, ++ 0x76,0x00, ++ 0x96,0x00, ++ 0x4D,0x01, ++ 0xFD,0x00, ++ 0x65,0x00, ++ 0x45,0x00, ++ 0x53,0x00, ++ 0x83,0x00, ++ 0x93,0x00, ++ 0xA3,0x00, ++ 0xB3,0x00, ++ 0xC3,0x00, ++ 0x96,0x00, ++ 0xA6,0x00, ++ 0xB6,0x00, ++ 0xA6,0x00, ++ 0x66,0x00, ++ 0x66,0x00, ++ 0xF7,0x00, ++ 0xFE,0x00, ++ 0x65,0x00, ++ 0x75,0x01, ++ 0x05,0x01, ++ 0x65,0x00, ++ 0x65,0x00, ++ 0x23,0x00, ++ 0x33,0x00, ++ 0x53,0x00, ++ 0xA6,0x00, ++ 0x76,0x00, ++ 0x46,0x00, ++ 0x4A,0x00, ++ 0xAA,0x00, ++ 0xEA,0x00, ++ 0x7B,0x00, ++ 0xE1,0x00, ++ 0x81,0x00, ++ 0xE5,0x00, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0xE5,0x00, ++ 0xA5,0x00, ++ 0x75,0x00, ++ 0x45,0x00, ++ 0x76,0x00, ++ 0x46,0x00, ++ 0x7A,0x00, ++ 0xCA,0x00, ++ 0xEA,0x00, ++ 0x6A,0x00, ++ 0xD1,0x00, ++ 0x21,0x01, ++ 0xB1,0x00, ++ 0x75,0x00, ++ 0x25,0x01, ++ 0x75,0x01, ++ 0x55,0x01, ++ 0x15,0x01, ++ 0xE5,0x00, ++ 0xB5,0x00, ++ 0x66,0x00, ++ 0x9A,0x00, ++ 0xDA,0x00, ++ 0xEA,0x00, ++ 0x8A,0x00, ++ 0x41,0x00, ++ 0x01,0x01, ++ 0x41,0x01, ++ 0xD1,0x00, ++ 0x25,0x00, ++ 0xC5,0x00, ++ 0x45,0x01, ++ 0x75,0x01, ++ 0x65,0x01, ++ 0x35,0x01, ++ 0x05,0x01, ++ 0x7A,0x00, ++ 0xDA,0x00, ++ 0xEA,0x00, ++ 0xAA,0x00, ++ 0x51,0x00, ++ 0x91,0x00, ++ 0x21,0x01, ++ 0x51,0x01, ++ 0xE1,0x00, ++ 0x41,0x00, ++ 0x85,0x00, ++ 0xF5,0x00, ++ 0x55,0x01, ++ 0x75,0x01, ++ 0x75,0x01, ++ 0xE5,0x00, ++ 0x4A,0x00, ++ 0xAA,0x00, ++ 0xAA,0x00, ++ 0x51,0x00, ++ 0x91,0x00, ++ 0xC1,0x00, ++ 0x31,0x01, ++ 0x51,0x01, ++ 0xE1,0x00, ++ 0x71,0x00, ++ 0x55,0x00, ++ 0xC5,0x00, ++ 0x15,0x01, ++ 0x55,0x01, ++ 0x25,0x01, ++ 0x75,0x00, ++ 0x00,0x00, ++ 0x61,0x00, ++ 0x61,0x00, ++ 0x81,0x00, ++ 0xB1,0x00, ++ 0xE1,0x00, ++ 0x41,0x01, ++ 0x51,0x01, ++ 0xF1,0x00, ++ 0x81,0x00, ++ 0x65,0x00, ++ 0x95,0x00, ++ 0xE5,0x00, ++ 0xD5,0x00, ++ 0x65,0x00, ++ 0x00,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// VIP_ICC_SETTING ++//**************************************************** ++ unsigned char MST_VIP_ICC_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ICC_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ICC_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_61_L), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_61_H), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_62_L), 0x0F, 0x0A/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_62_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x08, 0x08/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_63_L), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_63_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x20, 0x20/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_64_L), 0x0F, 0x03/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_64_H), 0x0F, 0x01/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_L), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_65_L), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x01, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_65_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x02, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_66_L), 0x0F, 0x05/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x04, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_66_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x08, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_67_L), 0x0F, 0x04/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x10, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_67_H), 0x0F, 0x02/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x20, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_68_L), 0x0F, 0x06/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x40, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_68_H), 0x0F, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_69_H), 0x80, 0x00/*HDMI_HD*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Ymode_Yvalue_ALL ++//**************************************************** ++ unsigned char MST_VIP_Ymode_Yvalue_ALL_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Ymode_Yvalue_ALL_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Ymode_Yvalue_ALL_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_36_L), 0xFF, 0x20/*Y1*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_36_H), 0xFF, 0x40/*Y1*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_37_L), 0xFF, 0x60/*Y1*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_37_H), 0xFF, 0x80/*Y1*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_Ymode_Yvalue_SETTING ++//**************************************************** ++ unsigned char MST_VIP_Ymode_Yvalue_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_Ymode_Yvalue_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_Ymode_Yvalue_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1B_08_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_08_H), 0xFF, 0x40/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_09_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_09_H), 0xFF, 0x80/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0A_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0A_H), 0xFF, 0x51/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0B_L), 0xFF, 0x9F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0B_H), 0xFF, 0xD7/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0C_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0C_H), 0xFF, 0x44/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0D_L), 0xFF, 0x7F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0D_H), 0xFF, 0xC8/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0E_L), 0xFF, 0x0E/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0E_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0F_L), 0xFF, 0x84/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_0F_H), 0xFF, 0xBD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_10_L), 0xFF, 0x0C/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_10_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_11_L), 0xFF, 0x82/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_11_H), 0xFF, 0xCD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_12_L), 0xFF, 0x4A/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_12_H), 0xFF, 0x6A/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_13_L), 0xFF, 0xA1/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_13_H), 0xFF, 0xD3/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_14_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_14_H), 0xFF, 0x53/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_15_L), 0xFF, 0x8E/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_15_H), 0xFF, 0xCE/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_16_L), 0xFF, 0x22/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_16_H), 0xFF, 0x4F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_17_L), 0xFF, 0x94/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_17_H), 0xFF, 0xB1/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_18_L), 0xFF, 0x22/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_18_H), 0xFF, 0x46/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_19_L), 0xFF, 0xAA/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_19_H), 0xFF, 0xCD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1A_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1A_H), 0xFF, 0x40/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1B_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1B_H), 0xFF, 0x80/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1C_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1C_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1D_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1D_H), 0xFF, 0xBD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1E_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1E_H), 0xFF, 0x42/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1F_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_1F_H), 0xFF, 0x84/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_20_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_20_H), 0xFF, 0x58/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_21_L), 0xFF, 0x92/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_21_H), 0xFF, 0xED/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_22_L), 0xFF, 0x24/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_22_H), 0xFF, 0x4F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_23_L), 0xFF, 0x91/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_23_H), 0xFF, 0xAD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_24_L), 0xFF, 0x24/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_24_H), 0xFF, 0x4F/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_25_L), 0xFF, 0x91/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_25_H), 0xFF, 0xAD/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_26_L), 0xFF, 0x20/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_26_H), 0xFF, 0x40/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_27_L), 0xFF, 0x60/*Y2*/, }, ++ { PQ_MAP_REG(REG_SC_BK1B_27_H), 0xFF, 0x80/*Y2*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IBC ++//**************************************************** ++ unsigned char MST_VIP_IBC_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IBC_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IBC_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IBC_dither ++//**************************************************** ++ unsigned char MST_VIP_IBC_dither_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IBC_dither_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IBC_dither_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_10_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_IBC_SETTING ++//**************************************************** ++ unsigned char MST_VIP_IBC_SETTING_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_IBC_SETTING_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_IBC_SETTING_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK20_11_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_11_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_12_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_12_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_13_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_13_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_14_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_14_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_15_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_15_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_16_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_16_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_17_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_17_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_18_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_18_H), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_21_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK20_21_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_ACK ++//**************************************************** ++ unsigned char MST_VIP_ACK_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_ACK_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_ACK_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_38_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_38_L), 0x10, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_38_L), 0x80, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_39_L), 0x3F, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_39_H), 0x3F, 0x0E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3A_L), 0x0F, 0xC0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3A_L), 0xF0, 0xC0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3A_H), 0x1F, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_L), 0x7F, 0x3C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_L), 0x80, 0x3C/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_H), 0x0F, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_3B_H), 0x60, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VIP_YCbCr_Clip ++//**************************************************** ++ unsigned char MST_VIP_YCbCr_Clip_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VIP_YCbCr_Clip_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VIP_YCbCr_Clip_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK1C_78_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_79_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_79_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7A_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7A_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7B_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7B_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7C_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7C_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7D_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7D_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7E_L), 0xFF, 0xFF/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK1C_7E_H), 0x03, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Y_SC1 ++//**************************************************** ++ unsigned char MST_VSP_Y_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Y_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Y_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_C_SC1 ++//**************************************************** ++ unsigned char MST_VSP_C_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_C_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_C_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_H), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_CoRing_SC1 ++//**************************************************** ++ unsigned char MST_VSP_CoRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_CoRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_CoRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0E_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_DeRing_SC1 ++//**************************************************** ++ unsigned char MST_VSP_DeRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_DeRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_DeRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_11_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_11_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_20_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Dither_SC1 ++//**************************************************** ++ unsigned char MST_VSP_Dither_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Dither_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Dither_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_PreVBound_SC1 ++//**************************************************** ++ unsigned char MST_VSP_PreVBound_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_PreVBound_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_PreVBound_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_13_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// AntiPAL_filter_SC1 ++//**************************************************** ++ unsigned char MST_AntiPAL_filter_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_AntiPAL_filter_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AntiPAL_filter_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_68_L), 0x1F, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_69_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_69_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422To444_SC1 ++//**************************************************** ++ unsigned char MST_422To444_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422To444_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422To444_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_L), 0x80, 0x80/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Y_SC1 ++//**************************************************** ++ unsigned char MST_HSP_Y_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Y_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Y_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_C_SC1 ++//**************************************************** ++ unsigned char MST_HSP_C_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_C_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_C_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0B_L), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_CoRing_SC1 ++//**************************************************** ++ unsigned char MST_HSP_CoRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_CoRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_CoRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0D_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_DeRing_SC1 ++//**************************************************** ++ unsigned char MST_HSP_DeRing_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_DeRing_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_DeRing_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0F_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0F_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0F_H), 0X03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_0F_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_L), 0X0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_20_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Dither_SC1 ++//**************************************************** ++ unsigned char MST_HSP_Dither_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Dither_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Dither_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_0C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HnonLinear_SC1 ++//**************************************************** ++ unsigned char MST_HnonLinear_SC1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HnonLinear_SC1_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HnonLinear_SC1_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_13_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_14_L), 0xFF, 0x7E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_14_H), 0xFF, 0x72/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_15_L), 0xFF, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_15_H), 0x80, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_15_H), 0x7F, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_16_L), 0xFF, 0x21/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_16_H), 0xFF, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// SRAM1 ++//**************************************************** ++ unsigned char MST_SRAM1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM1_Main[][PQ_IP_SRAM1_SIZE_Main]= ++{ ++{//InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G11 ++ 0x02,0xf8,0x91,0x80,0x83, ++ 0x02,0xf8,0xa1,0x00,0x84, ++ 0x00,0xf8,0xc1,0x00,0x84, ++ 0x01,0xf7,0xe1,0x00,0x84, ++ 0x02,0xf7,0xf1,0x00,0x84, ++ 0x03,0xf7,0x11,0x81,0x84, ++ 0x05,0xf5,0x41,0x81,0x84, ++ 0x06,0xf7,0x51,0x01,0x85, ++ 0x07,0xf7,0x61,0x01,0x85, ++ 0x08,0xf3,0x91,0x01,0x85, ++ 0x09,0xf3,0xa1,0x01,0x85, ++ 0x0a,0xf3,0xc1,0x81,0x85, ++ 0x0b,0xef,0xf1,0x81,0x85, ++ 0x0c,0xef,0x01,0x82,0x85, ++ 0x0d,0xf1,0x21,0x82,0x86, ++ 0x0e,0xed,0x51,0x82,0x86, ++ 0x0f,0xed,0x61,0x82,0x86, ++ 0x10,0xeb,0x81,0x82,0x86, ++ 0x11,0xe9,0xa1,0x82,0x86, ++ 0x12,0xe9,0xd1,0x82,0x87, ++ 0x13,0xe5,0x01,0x83,0x87, ++ 0x14,0xe5,0x11,0x83,0x87, ++ 0x15,0xe1,0x41,0x83,0x87, ++ 0x14,0xdd,0x61,0x03,0x88, ++ 0x15,0xd9,0x91,0x03,0x88, ++ 0x16,0xd9,0xb1,0x83,0x88, ++ 0x17,0xd5,0xe1,0x83,0x88, ++ 0x17,0xd3,0x01,0x04,0x89, ++ 0x18,0xcf,0x31,0x04,0x89, ++ 0x19,0xcd,0x51,0x04,0x89, ++ 0x19,0xcd,0x61,0x84,0x89, ++ 0x1a,0xc9,0x91,0x84,0x89, ++ 0x1b,0xc5,0xd1,0x04,0x8a, ++ 0x1a,0xc1,0xe1,0x04,0x8a, ++ 0x1b,0xbf,0x01,0x05,0x8a, ++ 0x1b,0xbb,0x31,0x85,0x8a, ++ 0x1c,0xb9,0x51,0x85,0x8a, ++ 0x1c,0xb5,0x81,0x05,0x8b, ++ 0x1d,0xb3,0xa1,0x05,0x8b, ++ 0x1d,0xad,0xd1,0x05,0x8b, ++ 0x1e,0xab,0x01,0x86,0x8b, ++ 0x1d,0xa5,0x21,0x86,0x8b, ++ 0x1e,0xa1,0x61,0x06,0x8c, ++ 0x1e,0x9d,0x81,0x06,0x8c, ++ 0x1e,0x99,0xa1,0x06,0x8c, ++ 0x1f,0x95,0xe1,0x86,0x8c, ++ 0x1f,0x93,0xf1,0x86,0x8c, ++ 0x1e,0x8b,0x31,0x07,0x8d, ++ 0x1f,0x87,0x61,0x07,0x8d, ++ 0x1f,0x83,0x81,0x07,0x8d, ++ 0x1f,0x81,0xa1,0x87,0x8d, ++ 0x1f,0x7b,0xd1,0x87,0x8d, ++ 0x20,0x79,0xf1,0x87,0x8d, ++ 0x1f,0x71,0x21,0x88,0x8d, ++ 0x1f,0x6b,0x51,0x88,0x8d, ++ 0x1f,0x69,0x71,0x08,0x8e, ++ 0x1f,0x63,0xa1,0x08,0x8e, ++ 0x1f,0x61,0xc1,0x88,0x8e, ++ 0x1f,0x5b,0xf1,0x88,0x8e, ++ 0x1f,0x55,0x31,0x09,0x8f, ++ 0x1f,0x51,0x51,0x09,0x8f, ++ 0x1f,0x4b,0x81,0x09,0x8f, ++ 0x1f,0x45,0xb1,0x09,0x8f, ++ 0x1f,0x41,0xd1,0x09,0x8f ++}, ++ ++{//InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G12 ++ 0x13,0x47,0x72,0xc0,0x84, ++ 0x13,0x47,0x62,0x40,0x85, ++ 0x15,0x47,0x32,0xc0,0x85, ++ 0x16,0x47,0x22,0xc0,0x85, ++ 0x17,0x45,0x02,0x80,0x85, ++ 0x18,0x45,0x22,0x00,0x86, ++ 0x1a,0x45,0x52,0x80,0x86, ++ 0x1b,0x43,0x72,0x80,0x86, ++ 0x1c,0x43,0x82,0x80,0x86, ++ 0x1d,0x41,0xb2,0x00,0x87, ++ 0x1e,0x41,0xc2,0x00,0x87, ++ 0x1f,0x3f,0xf2,0x80,0x87, ++ 0x20,0x3d,0x22,0x01,0x88, ++ 0x21,0x3b,0x42,0x01,0x88, ++ 0x22,0x3b,0x62,0x81,0x88, ++ 0x23,0x39,0x92,0x01,0x89, ++ 0x24,0x37,0xb2,0x01,0x89, ++ 0x25,0x33,0xe2,0x01,0x89, ++ 0x26,0x33,0xf2,0x01,0x89, ++ 0x26,0x2d,0x42,0x02,0x8a, ++ 0x27,0x29,0x72,0x02,0x8a, ++ 0x28,0x2b,0x82,0x82,0x8a, ++ 0x29,0x27,0xb2,0x82,0x8a, ++ 0x29,0x23,0xe2,0x02,0x8b, ++ 0x2a,0x21,0x12,0x83,0x8b, ++ 0x2a,0x1b,0x42,0x83,0x8b, ++ 0x2b,0x19,0x72,0x03,0x8c, ++ 0x2b,0x15,0xa2,0x83,0x8c, ++ 0x2c,0x11,0xd2,0x83,0x8c, ++ 0x2d,0x0f,0x02,0x04,0x8d, ++ 0x2c,0x09,0x22,0x04,0x8d, ++ 0x2d,0x05,0x52,0x04,0x8d, ++ 0x2e,0x03,0x92,0x04,0x8e, ++ 0x2e,0xff,0xb1,0x04,0x8e, ++ 0x2f,0xfd,0xe1,0x84,0x8e, ++ 0x2e,0xf5,0x11,0x85,0x8e, ++ 0x2f,0xf1,0x41,0x85,0x8e, ++ 0x2f,0xef,0x71,0x85,0x8f, ++ 0x30,0xeb,0xa1,0x85,0x8f, ++ 0x2f,0xe5,0xd1,0x05,0x90, ++ 0x30,0xe1,0x01,0x06,0x90, ++ 0x30,0xdb,0x31,0x06,0x90, ++ 0x30,0xd5,0x81,0x06,0x91, ++ 0x30,0xcf,0xb1,0x06,0x91, ++ 0x30,0xcf,0xc1,0x86,0x91, ++ 0x30,0xc5,0x11,0x87,0x91, ++ 0x30,0xc1,0x31,0x87,0x91, ++ 0x30,0xbd,0x71,0x87,0x92, ++ 0x30,0xb5,0xc1,0x07,0x93, ++ 0x30,0xb3,0xd1,0x07,0x93, ++ 0x30,0xab,0x11,0x08,0x93, ++ 0x2f,0xa5,0x41,0x88,0x93, ++ 0x30,0xa1,0x71,0x88,0x93, ++ 0x30,0x9b,0xa1,0x88,0x93, ++ 0x2f,0x95,0xd1,0x08,0x94, ++ 0x2f,0x8f,0x01,0x09,0x94, ++ 0x2f,0x89,0x41,0x89,0x94, ++ 0x2e,0x83,0x71,0x09,0x95, ++ 0x2e,0x7d,0xa1,0x09,0x95, ++ 0x2f,0x79,0xe1,0x89,0x95, ++ 0x2e,0x6f,0x21,0x8a,0x95, ++ 0x2e,0x6b,0x51,0x0a,0x96, ++ 0x2d,0x63,0x81,0x0a,0x96, ++ 0x2d,0x5f,0xb1,0x8a,0x96 ++}, ++ ++{//InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G13 ++ 0x29,0x9b,0x82,0x41,0x86, ++ 0x29,0x99,0x62,0xc1,0x86, ++ 0x2b,0x97,0x32,0xc1,0x86, ++ 0x2c,0x97,0x12,0x41,0x87, ++ 0x2d,0x97,0x02,0x41,0x87, ++ 0x2e,0x95,0xc2,0x40,0x88, ++ 0x30,0x93,0x92,0x40,0x88, ++ 0x31,0x95,0x82,0xc0,0x88, ++ 0x32,0x93,0x62,0xc0,0x88, ++ 0x32,0x8b,0x22,0xc0,0x88, ++ 0x33,0x8d,0x12,0x40,0x89, ++ 0x34,0x8b,0x22,0x80,0x89, ++ 0x35,0x87,0x62,0x00,0x8a, ++ 0x36,0x87,0x72,0x00,0x8a, ++ 0x37,0x85,0xb2,0x00,0x8b, ++ 0x38,0x81,0xe2,0x00,0x8b, ++ 0x39,0x81,0x02,0x81,0x8b, ++ 0x39,0x7b,0x32,0x81,0x8b, ++ 0x3a,0x7b,0x52,0x01,0x8c, ++ 0x3b,0x77,0xa2,0x01,0x8d, ++ 0x3c,0x73,0xd2,0x01,0x8d, ++ 0x3d,0x71,0xf2,0x01,0x8d, ++ 0x3e,0x6d,0x32,0x82,0x8d, ++ 0x3d,0x69,0x62,0x82,0x8e, ++ 0x3e,0x63,0xa2,0x82,0x8e, ++ 0x3f,0x61,0xd2,0x02,0x8f, ++ 0x3f,0x59,0x12,0x03,0x8f, ++ 0x3f,0x57,0x42,0x03,0x90, ++ 0x40,0x53,0x82,0x83,0x90, ++ 0x40,0x4d,0xb2,0x83,0x90, ++ 0x40,0x4b,0xd2,0x03,0x91, ++ 0x41,0x47,0x02,0x04,0x91, ++ 0x42,0x41,0x62,0x04,0x92, ++ 0x41,0x3d,0x72,0x04,0x92, ++ 0x42,0x39,0xb2,0x84,0x92, ++ 0x41,0x31,0xf2,0x04,0x93, ++ 0x42,0x2d,0x22,0x05,0x93, ++ 0x42,0x29,0x62,0x05,0x94, ++ 0x42,0x23,0x92,0x05,0x94, ++ 0x42,0x1d,0xd2,0x85,0x94, ++ 0x43,0x19,0x12,0x06,0x95, ++ 0x42,0x11,0x42,0x06,0x95, ++ 0x43,0x0d,0x92,0x06,0x96, ++ 0x42,0x05,0xd2,0x86,0x96, ++ 0x42,0x01,0xf2,0x86,0x96, ++ 0x42,0xf7,0x51,0x07,0x97, ++ 0x42,0xf5,0x61,0x07,0x97, ++ 0x41,0xeb,0xc1,0x07,0x98, ++ 0x42,0xe5,0x11,0x88,0x98, ++ 0x41,0xdf,0x31,0x88,0x98, ++ 0x41,0xd9,0x71,0x08,0x99, ++ 0x40,0xcf,0xb1,0x08,0x99, ++ 0x41,0xcd,0xe1,0x88,0x99, ++ 0x40,0xc5,0x21,0x09,0x9a, ++ 0x40,0xbd,0x61,0x09,0x9a, ++ 0x3f,0xb5,0xa1,0x89,0x9a, ++ 0x3e,0xad,0xd1,0x89,0x9a, ++ 0x3e,0xa9,0x11,0x8a,0x9b, ++ 0x3e,0xa3,0x51,0x0a,0x9c, ++ 0x3e,0x9b,0xa1,0x8a,0x9c, ++ 0x3d,0x91,0xe1,0x8a,0x9c, ++ 0x3d,0x8b,0x21,0x0b,0x9d, ++ 0x3c,0x81,0x61,0x0b,0x9d, ++ 0x3c,0x7d,0x91,0x8b,0x9d ++}, ++ ++{//InvSinc4Tc4p4Fc65Apass3Astop60G14 ++ 0x33,0xbb,0xc2,0x41,0x87, ++ 0x35,0xb7,0x82,0x41,0x87, ++ 0x36,0xb7,0x62,0xc1,0x87, ++ 0x37,0xb5,0x42,0xc1,0x87, ++ 0x38,0xb7,0x32,0x41,0x88, ++ 0x39,0xb5,0x12,0x41,0x88, ++ 0x39,0xaf,0xd2,0xc0,0x88, ++ 0x3a,0xad,0xb2,0xc0,0x88, ++ 0x3b,0xad,0x92,0x40,0x89, ++ 0x3c,0xab,0x72,0x40,0x89, ++ 0x3d,0xa7,0x32,0xc0,0x89, ++ 0x3e,0xa7,0x02,0x80,0x8a, ++ 0x3f,0xa5,0x22,0x80,0x8a, ++ 0x3f,0x9f,0x62,0x00,0x8b, ++ 0x40,0x9d,0x82,0x00,0x8b, ++ 0x40,0x9b,0xa2,0x80,0x8b, ++ 0x41,0x99,0xc2,0x80,0x8b, ++ 0x42,0x95,0x02,0x01,0x8c, ++ 0x42,0x8f,0x42,0x81,0x8c, ++ 0x43,0x8d,0x62,0x81,0x8c, ++ 0x43,0x89,0xa2,0x81,0x8d, ++ 0x44,0x85,0xe2,0x01,0x8e, ++ 0x45,0x85,0xf2,0x01,0x8e, ++ 0x45,0x7f,0x32,0x82,0x8e, ++ 0x45,0x79,0x62,0x82,0x8e, ++ 0x45,0x75,0x92,0x02,0x8f, ++ 0x46,0x71,0xd2,0x82,0x8f, ++ 0x46,0x6b,0x02,0x83,0x8f, ++ 0x46,0x65,0x42,0x03,0x90, ++ 0x46,0x61,0x82,0x03,0x91, ++ 0x46,0x59,0xc2,0x03,0x91, ++ 0x46,0x57,0xe2,0x83,0x91, ++ 0x47,0x53,0x22,0x04,0x92, ++ 0x46,0x4d,0x42,0x04,0x92, ++ 0x47,0x49,0x82,0x84,0x92, ++ 0x46,0x43,0xa2,0x84,0x92, ++ 0x47,0x3b,0x02,0x05,0x93, ++ 0x46,0x35,0x32,0x85,0x93, ++ 0x47,0x31,0x72,0x05,0x94, ++ 0x46,0x27,0xb2,0x05,0x94, ++ 0x46,0x23,0xf2,0x05,0x95, ++ 0x46,0x1d,0x32,0x86,0x95, ++ 0x45,0x15,0x72,0x06,0x96, ++ 0x46,0x11,0xb2,0x86,0x96, ++ 0x46,0x0b,0xe2,0x86,0x96, ++ 0x45,0x03,0x22,0x07,0x97, ++ 0x44,0xfd,0x41,0x07,0x97, ++ 0x45,0xf5,0xa1,0x87,0x97, ++ 0x44,0xef,0xd1,0x07,0x98, ++ 0x43,0xe7,0x11,0x88,0x98, ++ 0x43,0xdf,0x51,0x88,0x98, ++ 0x43,0xd9,0x91,0x08,0x99, ++ 0x42,0xcf,0xe1,0x88,0x99, ++ 0x42,0xcb,0x01,0x89,0x99, ++ 0x41,0xc3,0x41,0x09,0x9a, ++ 0x40,0xb9,0x91,0x89,0x9a, ++ 0x41,0xb5,0xd1,0x09,0x9b, ++ 0x40,0xad,0x11,0x8a,0x9b, ++ 0x3f,0xa3,0x51,0x8a,0x9b, ++ 0x3f,0x9f,0x81,0x0a,0x9c, ++ 0x3e,0x97,0xc1,0x8a,0x9c, ++ 0x3d,0x8d,0x01,0x8b,0x9c, ++ 0x3d,0x85,0x51,0x0b,0x9d, ++ 0x3c,0x81,0x71,0x8b,0x9d ++}, ++ ++}; ++ ++//**************************************************** ++// SRAM2 ++//**************************************************** ++ unsigned char MST_SRAM2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM2_Main[][PQ_IP_SRAM2_SIZE_Main]= ++{ ++{//InvSinc4Tc4p4Fc85Fstop134Apass01Astop50 ++ 0x17,0xa8,0x91,0x01,0x82, ++ 0x17,0xa8,0xa1,0x81,0x82, ++ 0x15,0xa8,0xc1,0x81,0x82, ++ 0x14,0xa8,0xd1,0x81,0x82, ++ 0x13,0xa8,0xe1,0x81,0x82, ++ 0x12,0xa8,0x01,0x02,0x83, ++ 0x10,0xa8,0x21,0x02,0x83, ++ 0x0f,0xa8,0x31,0x02,0x83, ++ 0x0e,0xa8,0x41,0x02,0x83, ++ 0x0d,0xa6,0x61,0x02,0x83, ++ 0x0c,0xa6,0x71,0x02,0x83, ++ 0x0b,0xa6,0x91,0x82,0x83, ++ 0x0a,0xa4,0xb1,0x82,0x83, ++ 0x09,0xa4,0xc1,0x82,0x83, ++ 0x08,0xa4,0xe1,0x02,0x84, ++ 0x07,0xa2,0x01,0x03,0x84, ++ 0x06,0xa2,0x11,0x03,0x84, ++ 0x05,0xa0,0x31,0x03,0x84, ++ 0x04,0xa0,0x41,0x03,0x84, ++ 0x03,0x9e,0x71,0x83,0x84, ++ 0x02,0x9c,0x91,0x83,0x84, ++ 0x01,0x9c,0xa1,0x83,0x84, ++ 0x00,0x9a,0xc1,0x83,0x84, ++ 0x00,0x98,0xe1,0x03,0x85, ++ 0x01,0x97,0x01,0x04,0x85, ++ 0x02,0x95,0x21,0x04,0x85, ++ 0x03,0x93,0x41,0x04,0x85, ++ 0x03,0x91,0x61,0x84,0x85, ++ 0x04,0x8f,0x81,0x84,0x85, ++ 0x05,0x8d,0xa1,0x84,0x85, ++ 0x05,0x8b,0xb1,0x84,0x85, ++ 0x06,0x89,0xd1,0x84,0x85, ++ 0x07,0x87,0x01,0x05,0x86, ++ 0x07,0x85,0x11,0x05,0x86, ++ 0x08,0x83,0x31,0x05,0x86, ++ 0x08,0x7f,0x51,0x05,0x86, ++ 0x09,0x7d,0x71,0x05,0x86, ++ 0x09,0x7b,0x91,0x85,0x86, ++ 0x0a,0x79,0xb1,0x85,0x86, ++ 0x0a,0x75,0xd1,0x85,0x86, ++ 0x0b,0x73,0xf1,0x85,0x86, ++ 0x0b,0x6f,0x11,0x86,0x86, ++ 0x0c,0x6d,0x41,0x06,0x87, ++ 0x0c,0x69,0x61,0x06,0x87, ++ 0x0c,0x67,0x71,0x06,0x87, ++ 0x0d,0x63,0xa1,0x06,0x87, ++ 0x0d,0x61,0xb1,0x06,0x87, ++ 0x0d,0x5d,0xe1,0x86,0x87, ++ 0x0e,0x59,0x11,0x87,0x87, ++ 0x0e,0x57,0x21,0x87,0x87, ++ 0x0e,0x53,0x41,0x87,0x87, ++ 0x0e,0x4f,0x61,0x87,0x87, ++ 0x0f,0x4d,0x81,0x87,0x87, ++ 0x0f,0x49,0xa1,0x87,0x87, ++ 0x0f,0x45,0xc1,0x87,0x87, ++ 0x0f,0x41,0xe1,0x87,0x87, ++ 0x0f,0x3d,0x01,0x88,0x87, ++ 0x0f,0x3b,0x21,0x08,0x88, ++ 0x0f,0x37,0x41,0x08,0x88, ++ 0x10,0x33,0x71,0x08,0x88, ++ 0x10,0x2f,0x91,0x08,0x88, ++ 0x10,0x2b,0xb1,0x08,0x88, ++ 0x10,0x27,0xd1,0x08,0x88, ++ 0x10,0x23,0xf1,0x08,0x88 ++}, ++ ++{//InvSinc4Tc4p4Fc75Fstop124Apass0001Astop40 ++ 0x28,0x70,0x81,0x02,0x84, ++ 0x27,0x70,0x91,0x02,0x84, ++ 0x26,0x70,0xa1,0x02,0x84, ++ 0x24,0x70,0xc1,0x02,0x84, ++ 0x23,0x70,0xe1,0x82,0x84, ++ 0x22,0x70,0xf1,0x82,0x84, ++ 0x21,0x70,0x01,0x83,0x84, ++ 0x20,0x70,0x11,0x83,0x84, ++ 0x1e,0x70,0x31,0x83,0x84, ++ 0x1d,0x70,0x41,0x83,0x84, ++ 0x1c,0x70,0x61,0x03,0x85, ++ 0x1b,0x70,0x71,0x03,0x85, ++ 0x1a,0x6e,0x91,0x03,0x85, ++ 0x19,0x6e,0xa1,0x03,0x85, ++ 0x18,0x6e,0xb1,0x03,0x85, ++ 0x17,0x6e,0xd1,0x83,0x85, ++ 0x16,0x6c,0xf1,0x83,0x85, ++ 0x15,0x6c,0x01,0x84,0x85, ++ 0x14,0x6c,0x11,0x84,0x85, ++ 0x13,0x6a,0x31,0x84,0x85, ++ 0x12,0x6a,0x41,0x84,0x85, ++ 0x11,0x6a,0x51,0x84,0x85, ++ 0x10,0x68,0x81,0x04,0x86, ++ 0x0f,0x68,0x91,0x04,0x86, ++ 0x0e,0x66,0xb1,0x04,0x86, ++ 0x0d,0x64,0xd1,0x04,0x86, ++ 0x0c,0x64,0xe1,0x04,0x86, ++ 0x0b,0x62,0x01,0x05,0x86, ++ 0x0a,0x62,0x11,0x05,0x86, ++ 0x0a,0x60,0x21,0x05,0x86, ++ 0x09,0x5e,0x41,0x05,0x86, ++ 0x08,0x5e,0x61,0x85,0x86, ++ 0x07,0x5c,0x81,0x85,0x86, ++ 0x06,0x5a,0xa1,0x85,0x86, ++ 0x06,0x58,0xb1,0x85,0x86, ++ 0x05,0x58,0xc1,0x85,0x86, ++ 0x04,0x56,0xe1,0x85,0x86, ++ 0x03,0x54,0x01,0x86,0x86, ++ 0x03,0x52,0x11,0x86,0x86, ++ 0x02,0x50,0x31,0x86,0x86, ++ 0x01,0x4e,0x51,0x86,0x86, ++ 0x01,0x4c,0x61,0x86,0x86, ++ 0x00,0x4a,0x81,0x86,0x86, ++ 0x00,0x48,0x91,0x86,0x86, ++ 0x01,0x47,0xb1,0x86,0x86, ++ 0x02,0x45,0xd1,0x86,0x86, ++ 0x02,0x43,0xe1,0x86,0x86, ++ 0x03,0x41,0x01,0x87,0x86, ++ 0x03,0x3f,0x11,0x87,0x86, ++ 0x04,0x3b,0x31,0x07,0x86, ++ 0x04,0x39,0x41,0x07,0x86, ++ 0x05,0x37,0x61,0x07,0x86, ++ 0x05,0x35,0x71,0x07,0x86, ++ 0x06,0x33,0x91,0x07,0x86, ++ 0x06,0x2f,0xb1,0x07,0x86, ++ 0x07,0x2d,0xd1,0x07,0x86, ++ 0x07,0x2b,0xe1,0x07,0x86, ++ 0x07,0x27,0xf1,0x87,0x85, ++ 0x08,0x25,0x11,0x88,0x85, ++ 0x08,0x23,0x21,0x88,0x85, ++ 0x09,0x1f,0x51,0x88,0x85, ++ 0x09,0x1d,0x51,0x08,0x85, ++ 0x09,0x1b,0x61,0x08,0x85, ++ 0x09,0x17,0x81,0x08,0x85 ++}, ++ ++{//InvSinc4Tc4p4Fc50Apass01Astop55 ++ 0x3a,0xfe,0xb0,0x03,0x06, ++ 0x3a,0x00,0xc1,0x03,0x05, ++ 0x39,0x02,0xd1,0x83,0x04, ++ 0x39,0x04,0xe1,0x83,0x03, ++ 0x38,0x04,0x01,0x04,0x03, ++ 0x38,0x06,0x01,0x84,0x02, ++ 0x37,0x06,0x11,0x84,0x02, ++ 0x37,0x06,0x21,0x04,0x02, ++ 0x36,0x06,0x31,0x04,0x02, ++ 0x35,0x06,0x41,0x04,0x02, ++ 0x34,0x06,0x51,0x04,0x02, ++ 0x34,0x06,0x51,0x04,0x02, ++ 0x33,0x06,0x61,0x04,0x02, ++ 0x32,0x06,0x71,0x04,0x02, ++ 0x32,0x06,0x71,0x04,0x02, ++ 0x31,0x04,0x91,0x04,0x02, ++ 0x30,0x04,0x91,0x84,0x02, ++ 0x2f,0x04,0xa1,0x84,0x02, ++ 0x2f,0x04,0xa1,0x84,0x02, ++ 0x2e,0x02,0xc1,0x84,0x02, ++ 0x2d,0x02,0xd1,0x84,0x02, ++ 0x2c,0x02,0xe1,0x84,0x02, ++ 0x2c,0x02,0xe1,0x84,0x02, ++ 0x2b,0x00,0xf1,0x04,0x03, ++ 0x2a,0x00,0x01,0x05,0x03, ++ 0x2a,0x00,0x01,0x05,0x03, ++ 0x29,0xfe,0x10,0x85,0x03, ++ 0x28,0xfe,0x20,0x85,0x03, ++ 0x28,0xfe,0x20,0x85,0x03, ++ 0x27,0xfc,0x40,0x85,0x03, ++ 0x26,0xfc,0x40,0x05,0x04, ++ 0x26,0xfc,0x40,0x05,0x04, ++ 0x25,0xfa,0x60,0x05,0x04, ++ 0x24,0xfa,0x70,0x05,0x04, ++ 0x24,0xfa,0x70,0x05,0x04, ++ 0x23,0xf8,0x80,0x85,0x04, ++ 0x22,0xf8,0x90,0x85,0x04, ++ 0x22,0xf6,0xa0,0x85,0x04, ++ 0x21,0xf6,0xa0,0x05,0x05, ++ 0x21,0xf4,0xb0,0x05,0x05, ++ 0x20,0xf4,0xc0,0x05,0x05, ++ 0x1f,0xf2,0xd0,0x85,0x05, ++ 0x1f,0xf2,0xd0,0x85,0x05, ++ 0x1e,0xf0,0xf0,0x85,0x05, ++ 0x1e,0xf0,0xf0,0x85,0x05, ++ 0x1d,0xf0,0xf0,0x05,0x06, ++ 0x1c,0xee,0x10,0x06,0x06, ++ 0x1c,0xec,0x10,0x86,0x06, ++ 0x1b,0xec,0x20,0x86,0x06, ++ 0x1b,0xea,0x30,0x86,0x06, ++ 0x1a,0xea,0x30,0x06,0x07, ++ 0x1a,0xe8,0x40,0x06,0x07, ++ 0x19,0xe8,0x50,0x06,0x07, ++ 0x19,0xe6,0x50,0x86,0x07, ++ 0x18,0xe6,0x60,0x86,0x07, ++ 0x18,0xe4,0x60,0x06,0x08, ++ 0x17,0xe2,0x80,0x06,0x08, ++ 0x17,0xe2,0x80,0x06,0x08, ++ 0x16,0xe0,0x90,0x86,0x08, ++ 0x16,0xe0,0x90,0x86,0x08, ++ 0x15,0xde,0xa0,0x06,0x09, ++ 0x15,0xdc,0xb0,0x06,0x09, ++ 0x14,0xdc,0xb0,0x86,0x09, ++ 0x14,0xda,0xc0,0x86,0x09 ++}, ++ ++{//InvSinc4Tc4p4Fc45Apass01Astop40 ++ 0x3c,0xdc,0xd0,0x83,0x0c, ++ 0x3c,0xdc,0xe0,0x03,0x0c, ++ 0x3c,0xde,0xf0,0x03,0x0b, ++ 0x3c,0xe0,0x00,0x04,0x0a, ++ 0x3c,0xe0,0x10,0x84,0x09, ++ 0x3b,0xe2,0x20,0x04,0x09, ++ 0x3b,0xe2,0x30,0x84,0x08, ++ 0x3b,0xe4,0x30,0x04,0x08, ++ 0x3a,0xe4,0x40,0x04,0x08, ++ 0x3a,0xe4,0x50,0x84,0x07, ++ 0x39,0xe4,0x60,0x84,0x07, ++ 0x39,0xe6,0x70,0x84,0x06, ++ 0x38,0xe6,0x70,0x04,0x07, ++ 0x38,0xe6,0x80,0x84,0x06, ++ 0x37,0xe6,0x90,0x84,0x06, ++ 0x37,0xe6,0x90,0x84,0x06, ++ 0x36,0xe6,0xa0,0x84,0x06, ++ 0x35,0xe6,0xb0,0x84,0x06, ++ 0x35,0xe6,0xb0,0x84,0x06, ++ 0x34,0xe6,0xc0,0x84,0x06, ++ 0x34,0xe6,0xc0,0x84,0x06, ++ 0x33,0xe6,0xd0,0x84,0x06, ++ 0x33,0xe4,0xe0,0x84,0x06, ++ 0x32,0xe4,0xf0,0x84,0x06, ++ 0x31,0xe4,0x00,0x85,0x06, ++ 0x31,0xe4,0x00,0x85,0x06, ++ 0x30,0xe4,0x10,0x85,0x06, ++ 0x30,0xe4,0x10,0x85,0x06, ++ 0x2f,0xe2,0x20,0x05,0x07, ++ 0x2e,0xe2,0x30,0x05,0x07, ++ 0x2e,0xe2,0x30,0x05,0x07, ++ 0x2d,0xe2,0x40,0x05,0x07, ++ 0x2d,0xe0,0x40,0x85,0x07, ++ 0x2c,0xe0,0x50,0x85,0x07, ++ 0x2b,0xe0,0x60,0x85,0x07, ++ 0x2b,0xe0,0x60,0x85,0x07, ++ 0x2a,0xde,0x70,0x05,0x08, ++ 0x2a,0xde,0x70,0x05,0x08, ++ 0x29,0xde,0x70,0x85,0x08, ++ 0x29,0xdc,0x80,0x85,0x08, ++ 0x28,0xdc,0x90,0x85,0x08, ++ 0x27,0xdc,0x90,0x05,0x09, ++ 0x27,0xda,0xa0,0x05,0x09, ++ 0x26,0xda,0xa0,0x85,0x09, ++ 0x26,0xda,0xa0,0x85,0x09, ++ 0x25,0xd8,0xc0,0x85,0x09, ++ 0x25,0xd8,0xc0,0x85,0x09, ++ 0x24,0xd8,0xc0,0x05,0x0a, ++ 0x23,0xd6,0xd0,0x85,0x0a, ++ 0x23,0xd6,0xd0,0x85,0x0a, ++ 0x22,0xd4,0xf0,0x85,0x0a, ++ 0x22,0xd4,0xe0,0x05,0x0b, ++ 0x21,0xd4,0xf0,0x05,0x0b, ++ 0x21,0xd2,0x00,0x06,0x0b, ++ 0x20,0xd2,0x00,0x86,0x0b, ++ 0x20,0xd0,0x10,0x86,0x0b, ++ 0x1f,0xd0,0x10,0x06,0x0c, ++ 0x1f,0xd0,0x10,0x06,0x0c, ++ 0x1e,0xce,0x20,0x86,0x0c, ++ 0x1e,0xce,0x20,0x86,0x0c, ++ 0x1d,0xcc,0x30,0x06,0x0d, ++ 0x1d,0xcc,0x30,0x06,0x0d, ++ 0x1c,0xca,0x40,0x86,0x0d, ++ 0x1c,0xca,0x40,0x86,0x0d ++}, ++ ++}; ++ ++//**************************************************** ++// SRAM3 ++//**************************************************** ++ unsigned char MST_SRAM3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM3_Main[][PQ_IP_SRAM3_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// SRAM4 ++//**************************************************** ++ unsigned char MST_SRAM4_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SRAM4_Main[][PQ_IP_SRAM4_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00, ++ 0x00,0x00,0x00,0x00,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM1 ++//**************************************************** ++ unsigned char MST_C_SRAM1_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM1_Main[][PQ_IP_C_SRAM1_SIZE_Main]= ++{ ++{//C121 ++ 0x40,0x00,0x01,0x04,0x00, ++ 0x3f,0xfe,0x10,0x84,0x00, ++ 0x3f,0xfe,0x10,0x84,0x00, ++ 0x3e,0xfc,0x20,0x04,0x01, ++ 0x3e,0xfc,0x20,0x04,0x01, ++ 0x3d,0xfa,0x30,0x84,0x01, ++ 0x3d,0xfa,0x30,0x84,0x01, ++ 0x3c,0xf8,0x40,0x04,0x02, ++ 0x3c,0xf8,0x40,0x04,0x02, ++ 0x3b,0xf6,0x50,0x84,0x02, ++ 0x3b,0xf6,0x50,0x84,0x02, ++ 0x3a,0xf4,0x60,0x04,0x03, ++ 0x3a,0xf4,0x60,0x04,0x03, ++ 0x39,0xf2,0x70,0x84,0x03, ++ 0x39,0xf2,0x70,0x84,0x03, ++ 0x38,0xf0,0x80,0x04,0x04, ++ 0x38,0xf0,0x80,0x04,0x04, ++ 0x37,0xee,0x90,0x84,0x04, ++ 0x37,0xee,0x90,0x84,0x04, ++ 0x36,0xec,0xa0,0x04,0x05, ++ 0x36,0xec,0xa0,0x04,0x05, ++ 0x35,0xea,0xb0,0x84,0x05, ++ 0x35,0xea,0xb0,0x84,0x05, ++ 0x34,0xe8,0xc0,0x04,0x06, ++ 0x34,0xe8,0xc0,0x04,0x06, ++ 0x33,0xe6,0xd0,0x84,0x06, ++ 0x33,0xe6,0xd0,0x84,0x06, ++ 0x32,0xe4,0xe0,0x04,0x07, ++ 0x32,0xe4,0xe0,0x04,0x07, ++ 0x31,0xe2,0xf0,0x84,0x07, ++ 0x31,0xe2,0xf0,0x84,0x07, ++ 0x30,0xe0,0x00,0x05,0x08, ++ 0x30,0xe0,0x00,0x05,0x08, ++ 0x2f,0xde,0x10,0x85,0x08, ++ 0x2f,0xde,0x10,0x85,0x08, ++ 0x2e,0xdc,0x20,0x05,0x09, ++ 0x2e,0xdc,0x20,0x05,0x09, ++ 0x2d,0xda,0x30,0x85,0x09, ++ 0x2d,0xda,0x30,0x85,0x09, ++ 0x2c,0xd8,0x40,0x05,0x0a, ++ 0x2c,0xd8,0x40,0x05,0x0a, ++ 0x2b,0xd6,0x50,0x85,0x0a, ++ 0x2b,0xd6,0x50,0x85,0x0a, ++ 0x2a,0xd4,0x60,0x05,0x0b, ++ 0x2a,0xd4,0x60,0x05,0x0b, ++ 0x29,0xd2,0x70,0x85,0x0b, ++ 0x29,0xd2,0x70,0x85,0x0b, ++ 0x28,0xd0,0x80,0x05,0x0c, ++ 0x28,0xd0,0x80,0x05,0x0c, ++ 0x27,0xce,0x90,0x85,0x0c, ++ 0x27,0xce,0x90,0x85,0x0c, ++ 0x26,0xcc,0xa0,0x05,0x0d, ++ 0x26,0xcc,0xa0,0x05,0x0d, ++ 0x25,0xca,0xb0,0x85,0x0d, ++ 0x25,0xca,0xb0,0x85,0x0d, ++ 0x24,0xc8,0xc0,0x05,0x0e, ++ 0x24,0xc8,0xc0,0x05,0x0e, ++ 0x23,0xc6,0xd0,0x85,0x0e, ++ 0x23,0xc6,0xd0,0x85,0x0e, ++ 0x22,0xc4,0xe0,0x05,0x0f, ++ 0x22,0xc4,0xe0,0x05,0x0f, ++ 0x21,0xc2,0xf0,0x85,0x0f, ++ 0x21,0xc2,0xf0,0x85,0x0f, ++ 0x20,0xc0,0x00,0x06,0x10 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM2 ++//**************************************************** ++ unsigned char MST_C_SRAM2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM2_Main[][PQ_IP_C_SRAM2_SIZE_Main]= ++{ ++{//C2121 ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM3 ++//**************************************************** ++ unsigned char MST_C_SRAM3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM3_Main[][PQ_IP_C_SRAM3_SIZE_Main]= ++{ ++{//C161 ++ 0x20,0x80,0x01,0x02,0x00, ++ 0x20,0x7e,0x11,0x02,0x00, ++ 0x1f,0x7c,0x21,0x82,0x00, ++ 0x1f,0x78,0x41,0x82,0x00, ++ 0x1f,0x76,0x51,0x82,0x00, ++ 0x1f,0x74,0x61,0x82,0x00, ++ 0x1e,0x72,0x71,0x02,0x01, ++ 0x1e,0x6e,0x91,0x02,0x01, ++ 0x1e,0x6c,0xa1,0x02,0x01, ++ 0x1e,0x6a,0xb1,0x02,0x01, ++ 0x1d,0x68,0xc1,0x82,0x01, ++ 0x1d,0x64,0xe1,0x82,0x01, ++ 0x1d,0x62,0xf1,0x82,0x01, ++ 0x1d,0x60,0x01,0x83,0x01, ++ 0x1c,0x5e,0x11,0x03,0x02, ++ 0x1c,0x5a,0x31,0x03,0x02, ++ 0x1c,0x58,0x41,0x03,0x02, ++ 0x1c,0x56,0x51,0x03,0x02, ++ 0x1b,0x54,0x61,0x83,0x02, ++ 0x1b,0x50,0x81,0x83,0x02, ++ 0x1b,0x4e,0x91,0x83,0x02, ++ 0x1b,0x4c,0xa1,0x83,0x02, ++ 0x1a,0x4a,0xb1,0x03,0x03, ++ 0x1a,0x46,0xd1,0x03,0x03, ++ 0x1a,0x44,0xe1,0x03,0x03, ++ 0x1a,0x42,0xf1,0x03,0x03, ++ 0x19,0x40,0x01,0x84,0x03, ++ 0x19,0x3c,0x21,0x84,0x03, ++ 0x19,0x3a,0x31,0x84,0x03, ++ 0x19,0x38,0x41,0x84,0x03, ++ 0x18,0x36,0x51,0x04,0x04, ++ 0x18,0x32,0x71,0x04,0x04, ++ 0x18,0x30,0x81,0x04,0x04, ++ 0x18,0x2e,0x91,0x04,0x04, ++ 0x17,0x2c,0xa1,0x84,0x04, ++ 0x17,0x28,0xc1,0x84,0x04, ++ 0x17,0x26,0xd1,0x84,0x04, ++ 0x17,0x24,0xe1,0x84,0x04, ++ 0x16,0x22,0xf1,0x04,0x05, ++ 0x16,0x1e,0x11,0x05,0x05, ++ 0x16,0x1c,0x21,0x05,0x05, ++ 0x16,0x1a,0x31,0x05,0x05, ++ 0x15,0x18,0x41,0x85,0x05, ++ 0x15,0x14,0x61,0x85,0x05, ++ 0x15,0x12,0x71,0x85,0x05, ++ 0x15,0x10,0x81,0x85,0x05, ++ 0x14,0x0e,0x91,0x05,0x06, ++ 0x14,0x0a,0xb1,0x05,0x06, ++ 0x14,0x08,0xc1,0x05,0x06, ++ 0x14,0x06,0xd1,0x05,0x06, ++ 0x13,0x04,0xe1,0x85,0x06, ++ 0x13,0x00,0x01,0x86,0x06, ++ 0x13,0xfe,0x10,0x86,0x06, ++ 0x13,0xfc,0x20,0x86,0x06, ++ 0x12,0xfa,0x30,0x06,0x07, ++ 0x12,0xf6,0x50,0x06,0x07, ++ 0x12,0xf4,0x60,0x06,0x07, ++ 0x12,0xf2,0x70,0x06,0x07, ++ 0x11,0xf0,0x80,0x86,0x07, ++ 0x11,0xec,0xa0,0x86,0x07, ++ 0x11,0xea,0xb0,0x86,0x07, ++ 0x11,0xe8,0xc0,0x86,0x07, ++ 0x10,0xe6,0xd0,0x06,0x08, ++ 0x10,0xe2,0xf0,0x06,0x08 ++}, ++ ++}; ++ ++//**************************************************** ++// C_SRAM4 ++//**************************************************** ++ unsigned char MST_C_SRAM4_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_C_SRAM4_Main[][PQ_IP_C_SRAM4_SIZE_Main]= ++{ ++{//C2121 ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x54,0x58,0x40,0x05,0x16, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x52,0x5c,0x20,0x05,0x17, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x50,0x60,0x00,0x05,0x18, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4e,0x64,0xe0,0x04,0x19, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4c,0x68,0xc0,0x04,0x1a, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x4a,0x6c,0xa0,0x04,0x1b, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x48,0x70,0x80,0x04,0x1c, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x46,0x74,0x60,0x04,0x1d, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x44,0x78,0x40,0x04,0x1e, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x42,0x7c,0x20,0x04,0x1f, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20, ++ 0x40,0x80,0x00,0x04,0x20 ++}, ++ ++}; ++ ++//**************************************************** ++// VSP_Y_SC2 ++//**************************************************** ++ unsigned char MST_VSP_Y_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Y_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Y_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_C_SC2 ++//**************************************************** ++ unsigned char MST_VSP_C_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_C_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_C_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_H), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_CoRing_SC2 ++//**************************************************** ++ unsigned char MST_VSP_CoRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_CoRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_CoRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0E_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_DeRing_SC2 ++//**************************************************** ++ unsigned char MST_VSP_DeRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_DeRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_DeRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_11_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_11_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_20_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Dither_SC2 ++//**************************************************** ++ unsigned char MST_VSP_Dither_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Dither_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Dither_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_PreVBound_SC2 ++//**************************************************** ++ unsigned char MST_VSP_PreVBound_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_PreVBound_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_PreVBound_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_13_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// AntiPAL_filter_SC2 ++//**************************************************** ++ unsigned char MST_AntiPAL_filter_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_AntiPAL_filter_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AntiPAL_filter_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_68_L), 0x1F, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_69_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_69_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422To444_SC2 ++//**************************************************** ++ unsigned char MST_422To444_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422To444_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422To444_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_L), 0x80, 0x80/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Y_SC2 ++//**************************************************** ++ unsigned char MST_HSP_Y_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Y_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Y_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_C_SC2 ++//**************************************************** ++ unsigned char MST_HSP_C_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_C_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_C_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x20, 0x00/*Bypass*/, ++ 0x02/*Bilinear*/, ++ 0x04/*C_SRAM_1*/, ++ 0x06/*C_SRAM_2*/, ++ 0x08/*C_SRAM_3*/, ++ 0x0A/*C_SRAM_4*/, ++ 0x10/*SRAM_1_4Tap*/, ++ 0x30/*SRAM_2_4Tap*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x10, 0x00/*Bypass*/, ++ 0x02/*Bilinear*/, ++ 0x04/*C_SRAM_1*/, ++ 0x06/*C_SRAM_2*/, ++ 0x08/*C_SRAM_3*/, ++ 0x0A/*C_SRAM_4*/, ++ 0x10/*SRAM_1_4Tap*/, ++ 0x30/*SRAM_2_4Tap*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0B_L), 0x0E, 0x00/*Bypass*/, ++ 0x02/*Bilinear*/, ++ 0x04/*C_SRAM_1*/, ++ 0x06/*C_SRAM_2*/, ++ 0x08/*C_SRAM_3*/, ++ 0x0A/*C_SRAM_4*/, ++ 0x10/*SRAM_1_4Tap*/, ++ 0x30/*SRAM_2_4Tap*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_CoRing_SC2 ++//**************************************************** ++ unsigned char MST_HSP_CoRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_CoRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_CoRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0D_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_DeRing_SC2 ++//**************************************************** ++ unsigned char MST_HSP_DeRing_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_DeRing_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_DeRing_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0F_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0F_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0F_H), 0X03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_0F_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_L), 0X0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_20_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Dither_SC2 ++//**************************************************** ++ unsigned char MST_HSP_Dither_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Dither_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Dither_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_0C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HnonLinear_SC2 ++//**************************************************** ++ unsigned char MST_HnonLinear_SC2_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HnonLinear_SC2_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HnonLinear_SC2_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_13_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_14_L), 0xFF, 0x7E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_14_H), 0xFF, 0x72/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_15_L), 0xFF, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_15_H), 0x80, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_15_H), 0x7F, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_16_L), 0xFF, 0x21/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_16_H), 0xFF, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Y_SC3 ++//**************************************************** ++ unsigned char MST_VSP_Y_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Y_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Y_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_C_SC3 ++//**************************************************** ++ unsigned char MST_VSP_C_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_C_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_C_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_H), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_CoRing_SC3 ++//**************************************************** ++ unsigned char MST_VSP_CoRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_CoRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_CoRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0E_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0E_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_DeRing_SC3 ++//**************************************************** ++ unsigned char MST_VSP_DeRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_DeRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_DeRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_11_L), 0x3F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_11_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_11_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_11_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_L), 0x0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_12_H), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_20_H), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_Dither_SC3 ++//**************************************************** ++ unsigned char MST_VSP_Dither_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_Dither_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_Dither_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// VSP_PreVBound_SC3 ++//**************************************************** ++ unsigned char MST_VSP_PreVBound_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_VSP_PreVBound_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_VSP_PreVBound_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_13_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// AntiPAL_filter_SC3 ++//**************************************************** ++ unsigned char MST_AntiPAL_filter_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_AntiPAL_filter_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_AntiPAL_filter_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_68_L), 0x1F, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_69_L), 0x7F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_69_H), 0x1F, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// 422To444_SC3 ++//**************************************************** ++ unsigned char MST_422To444_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_422To444_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_422To444_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_L), 0x80, 0x80/*ON*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Y_SC3 ++//**************************************************** ++ unsigned char MST_HSP_Y_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Y_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Y_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x80, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x40, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x01, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_C_SC3 ++//**************************************************** ++ unsigned char MST_HSP_C_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_C_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_C_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x20, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x10, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0B_L), 0x0E, 0x00/*Bypass*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_CoRing_SC3 ++//**************************************************** ++ unsigned char MST_HSP_CoRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_CoRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_CoRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0D_L), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0D_H), 0xFF, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_DeRing_SC3 ++//**************************************************** ++ unsigned char MST_HSP_DeRing_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_DeRing_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_DeRing_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0F_L), 0x1F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0F_L), 0xC0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0F_H), 0X03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_0F_H), 0xFC, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_L), 0X0C, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_L), 0xF0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_H), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_10_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_20_L), 0x0F, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HSP_Dither_SC3 ++//**************************************************** ++ unsigned char MST_HSP_Dither_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HSP_Dither_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HSP_Dither_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_0C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// HnonLinear_SC3 ++//**************************************************** ++ unsigned char MST_HnonLinear_SC3_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_HnonLinear_SC3_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_HnonLinear_SC3_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_13_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_14_L), 0xFF, 0x7E/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_14_H), 0xFF, 0x72/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_15_L), 0xFF, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_15_H), 0x80, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_15_H), 0x7F, 0x91/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_16_L), 0xFF, 0x21/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_16_H), 0xFF, 0x10/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_0_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_0_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_0_SRAM_Main[][PQ_IP_WDR_Loc_TBL_0_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x0f,0x03, ++ 0x37,0x03, ++ 0xfd,0x01, ++ 0xc4,0x03, ++ 0x24,0x01, ++ 0x93,0x02, ++ 0xac,0x03, ++ 0xe0,0x00, ++ 0x81,0x02, ++ 0x5f,0x03, ++ 0x51,0x03, ++ 0xbd,0x03, ++ 0x9a,0x03, ++ 0x3e,0x01, ++ 0xbf,0x01, ++ 0xc7,0x00, ++ 0xbf,0x03, ++ 0xd9,0x02, ++ 0xaf,0x03, ++ 0x89,0x01, ++ 0x9f,0x00, ++ 0x03,0x02, ++ 0x2a,0x03, ++ 0xd7,0x03, ++ 0x8a,0x00, ++ 0x83,0x03, ++ 0x13,0x03, ++ 0x44,0x01, ++ 0x6d,0x02, ++ 0x40,0x03, ++ 0x6c,0x00, ++ 0xaf,0x02, ++ 0x9d,0x00, ++ 0x3b,0x01, ++ 0x7c,0x03, ++ 0x0d,0x01, ++ 0x44,0x01, ++ 0x52,0x01, ++ 0x03,0x00, ++ 0xeb,0x03, ++ 0xb7,0x01, ++ 0xdf,0x01, ++ 0xe9,0x00, ++ 0x02,0x01, ++ 0x62,0x03, ++ 0x98,0x02, ++ 0x6b,0x02, ++ 0x2d,0x00, ++ 0x97,0x03, ++ 0x4e,0x01, ++ 0x56,0x01, ++ 0x40,0x03, ++ 0x05,0x01, ++ 0x6f,0x03, ++ 0x24,0x02, ++ 0x0e,0x02, ++ 0xf9,0x03, ++ 0x64,0x01, ++ 0xc2,0x00, ++ 0xe6,0x03, ++ 0x6a,0x00, ++ 0x36,0x02, ++ 0xab,0x03, ++ 0x2f,0x02 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_1_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_1_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_1_SRAM_Main[][PQ_IP_WDR_Loc_TBL_1_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x6c,0x01, ++ 0xa6,0x00, ++ 0xf9,0x01, ++ 0x98,0x00, ++ 0xa6,0x00, ++ 0x35,0x01, ++ 0x01,0x01, ++ 0xd2,0x01, ++ 0x06,0x01, ++ 0xdb,0x01, ++ 0x6c,0x01, ++ 0xf7,0x00, ++ 0x5b,0x03, ++ 0x34,0x00, ++ 0xb2,0x03, ++ 0x26,0x03, ++ 0xe3,0x01, ++ 0xb6,0x00, ++ 0x47,0x03, ++ 0xc5,0x02, ++ 0xa8,0x00, ++ 0xf2,0x02, ++ 0x31,0x03, ++ 0x16,0x00, ++ 0x12,0x02, ++ 0x64,0x02, ++ 0xdb,0x01, ++ 0x70,0x03, ++ 0x18,0x03, ++ 0x20,0x03, ++ 0x4a,0x02, ++ 0x8d,0x02, ++ 0xa0,0x01, ++ 0x13,0x02, ++ 0x73,0x01, ++ 0x66,0x02, ++ 0x3c,0x03, ++ 0x6c,0x00, ++ 0xcc,0x01, ++ 0x7b,0x02, ++ 0x9b,0x02, ++ 0xf2,0x00, ++ 0x5f,0x00, ++ 0x16,0x01, ++ 0xa1,0x03, ++ 0x81,0x00, ++ 0x85,0x00, ++ 0xce,0x01, ++ 0x12,0x01, ++ 0x2d,0x02, ++ 0xeb,0x02, ++ 0xeb,0x02, ++ 0xd5,0x00, ++ 0x0f,0x03, ++ 0x41,0x03, ++ 0x73,0x00, ++ 0x11,0x03, ++ 0xf4,0x02, ++ 0x67,0x03, ++ 0x57,0x01, ++ 0x66,0x01, ++ 0xc4,0x01, ++ 0xd1,0x00, ++ 0x59,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_2_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_2_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_2_SRAM_Main[][PQ_IP_WDR_Loc_TBL_2_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x77,0x00, ++ 0xcb,0x01, ++ 0x92,0x03, ++ 0x15,0x00, ++ 0x3e,0x00, ++ 0x58,0x00, ++ 0x5e,0x03, ++ 0xc3,0x03, ++ 0xb7,0x01, ++ 0x00,0x01, ++ 0x8b,0x02, ++ 0x14,0x00, ++ 0x54,0x00, ++ 0xe4,0x01, ++ 0xad,0x02, ++ 0xcc,0x02, ++ 0x63,0x03, ++ 0x37,0x00, ++ 0x4c,0x02, ++ 0xb2,0x03, ++ 0xd4,0x03, ++ 0x79,0x00, ++ 0x55,0x01, ++ 0x0c,0x01, ++ 0x3b,0x00, ++ 0x4c,0x02, ++ 0xd3,0x03, ++ 0x12,0x00, ++ 0x00,0x02, ++ 0x74,0x03, ++ 0xd1,0x00, ++ 0x23,0x00, ++ 0xfa,0x00, ++ 0x1e,0x00, ++ 0x1e,0x02, ++ 0x4d,0x00, ++ 0x13,0x00, ++ 0x35,0x00, ++ 0xa1,0x00, ++ 0xad,0x03, ++ 0x5f,0x00, ++ 0x8c,0x00, ++ 0x2b,0x02, ++ 0x82,0x01, ++ 0x4b,0x01, ++ 0x18,0x02, ++ 0x41,0x02, ++ 0x4b,0x01, ++ 0x28,0x03, ++ 0x72,0x00, ++ 0xf8,0x02, ++ 0xd1,0x02, ++ 0xe7,0x02, ++ 0x7b,0x02, ++ 0x32,0x01, ++ 0x99,0x00, ++ 0x14,0x00, ++ 0xaf,0x02, ++ 0x83,0x01, ++ 0x56,0x01, ++ 0x25,0x00, ++ 0xbd,0x00, ++ 0xf0,0x02, ++ 0x34,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_3_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_3_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_3_SRAM_Main[][PQ_IP_WDR_Loc_TBL_3_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x5e,0x00, ++ 0x8b,0x00, ++ 0xf5,0x03, ++ 0x9c,0x02, ++ 0x82,0x03, ++ 0x43,0x01, ++ 0x59,0x00, ++ 0x13,0x03, ++ 0xf7,0x03, ++ 0x0d,0x01, ++ 0x74,0x00, ++ 0x25,0x01, ++ 0xd1,0x02, ++ 0x8b,0x03, ++ 0x37,0x01, ++ 0x97,0x02, ++ 0x9b,0x03, ++ 0x8c,0x01, ++ 0x42,0x00, ++ 0x94,0x03, ++ 0xbe,0x03, ++ 0x2d,0x00, ++ 0x0a,0x00, ++ 0x6e,0x00, ++ 0x58,0x02, ++ 0x35,0x00, ++ 0xad,0x02, ++ 0x57,0x00, ++ 0xd7,0x01, ++ 0xd3,0x01, ++ 0x9d,0x00, ++ 0x82,0x03, ++ 0x3b,0x01, ++ 0x36,0x01, ++ 0x06,0x01, ++ 0xdb,0x03, ++ 0xaa,0x02, ++ 0x2e,0x01, ++ 0xc1,0x00, ++ 0xc5,0x00, ++ 0x52,0x03, ++ 0xbd,0x02, ++ 0x98,0x02, ++ 0x91,0x00, ++ 0xc4,0x01, ++ 0xea,0x00, ++ 0x42,0x00, ++ 0x23,0x03, ++ 0xac,0x01, ++ 0xf9,0x00, ++ 0xb3,0x00, ++ 0xe3,0x02, ++ 0xb5,0x00, ++ 0xb6,0x01, ++ 0xee,0x00, ++ 0x8a,0x03, ++ 0x55,0x03, ++ 0x17,0x02, ++ 0xa3,0x02, ++ 0x43,0x01, ++ 0x09,0x03, ++ 0x3f,0x02, ++ 0x94,0x02, ++ 0xea,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_4_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_4_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_4_SRAM_Main[][PQ_IP_WDR_Loc_TBL_4_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x8e,0x03, ++ 0x6b,0x00, ++ 0x92,0x01, ++ 0x46,0x03, ++ 0x8d,0x01, ++ 0x3c,0x03, ++ 0xa4,0x00, ++ 0x2e,0x00, ++ 0x16,0x02, ++ 0x59,0x01, ++ 0x93,0x00, ++ 0x4c,0x02, ++ 0xe6,0x03, ++ 0x4c,0x03, ++ 0x34,0x02, ++ 0x69,0x01, ++ 0x92,0x00, ++ 0xb7,0x03, ++ 0x39,0x03, ++ 0x48,0x00, ++ 0x02,0x00, ++ 0xc1,0x03, ++ 0x09,0x01, ++ 0x60,0x03, ++ 0xf7,0x03, ++ 0x1c,0x01, ++ 0xbd,0x01, ++ 0x11,0x02, ++ 0x54,0x01, ++ 0xb3,0x00, ++ 0xd8,0x03, ++ 0x6a,0x01, ++ 0x3c,0x03, ++ 0x1c,0x01, ++ 0x53,0x02, ++ 0x7d,0x02, ++ 0x54,0x01, ++ 0x36,0x00, ++ 0x57,0x03, ++ 0xdd,0x00, ++ 0x57,0x03, ++ 0x4f,0x01, ++ 0x31,0x01, ++ 0x62,0x02, ++ 0x76,0x03, ++ 0x60,0x02, ++ 0x3c,0x02, ++ 0x0d,0x01, ++ 0x3e,0x03, ++ 0x4a,0x01, ++ 0x8e,0x00, ++ 0x96,0x00, ++ 0x32,0x01, ++ 0x49,0x01, ++ 0x3d,0x01, ++ 0x51,0x03, ++ 0xe6,0x03, ++ 0xa2,0x02, ++ 0x9f,0x00, ++ 0xee,0x01, ++ 0xfd,0x01, ++ 0x05,0x01, ++ 0x0f,0x03, ++ 0x01,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_5_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_5_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_5_SRAM_Main[][PQ_IP_WDR_Loc_TBL_5_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0xdc,0x02, ++ 0x90,0x03, ++ 0x29,0x03, ++ 0x71,0x01, ++ 0x09,0x02, ++ 0x5d,0x01, ++ 0x18,0x03, ++ 0x8b,0x01, ++ 0xba,0x01, ++ 0x83,0x00, ++ 0x0b,0x03, ++ 0x3a,0x03, ++ 0x76,0x00, ++ 0x32,0x02, ++ 0x0c,0x02, ++ 0xc8,0x00, ++ 0x55,0x03, ++ 0x60,0x00, ++ 0xae,0x03, ++ 0xa6,0x02, ++ 0xd0,0x03, ++ 0x0b,0x03, ++ 0x42,0x03, ++ 0x10,0x01, ++ 0x33,0x00, ++ 0x4c,0x03, ++ 0xd9,0x02, ++ 0x1b,0x01, ++ 0x1f,0x03, ++ 0x8e,0x02, ++ 0x01,0x03, ++ 0x4b,0x02, ++ 0xd8,0x02, ++ 0x6e,0x03, ++ 0x51,0x00, ++ 0xfe,0x01, ++ 0x68,0x03, ++ 0x60,0x01, ++ 0x8f,0x03, ++ 0x5e,0x02, ++ 0xcc,0x03, ++ 0xee,0x00, ++ 0xdc,0x01, ++ 0xb6,0x02, ++ 0xb1,0x03, ++ 0x28,0x02, ++ 0x33,0x01, ++ 0x30,0x01, ++ 0x96,0x01, ++ 0xee,0x01, ++ 0x41,0x03, ++ 0xaa,0x02, ++ 0x01,0x01, ++ 0x8b,0x01, ++ 0x31,0x02, ++ 0xa6,0x00, ++ 0xba,0x00, ++ 0x97,0x02, ++ 0x45,0x02, ++ 0x3d,0x03, ++ 0x5c,0x02, ++ 0x30,0x02, ++ 0xd0,0x02, ++ 0xa6,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_6_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_6_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_6_SRAM_Main[][PQ_IP_WDR_Loc_TBL_6_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x60,0x01, ++ 0x8a,0x00, ++ 0x9c,0x03, ++ 0x73,0x02, ++ 0xf5,0x02, ++ 0x74,0x03, ++ 0xaa,0x03, ++ 0xa5,0x02, ++ 0x63,0x00, ++ 0x9d,0x03, ++ 0x0a,0x02, ++ 0xf9,0x03, ++ 0xe0,0x03, ++ 0x55,0x03, ++ 0xa7,0x00, ++ 0x73,0x03, ++ 0x95,0x00, ++ 0xac,0x01, ++ 0xf8,0x00, ++ 0xa1,0x03, ++ 0x08,0x03, ++ 0x66,0x00, ++ 0x02,0x03, ++ 0x69,0x03, ++ 0xea,0x03, ++ 0x4b,0x01, ++ 0x9e,0x01, ++ 0x41,0x03, ++ 0xe3,0x00, ++ 0xbd,0x03, ++ 0x72,0x02, ++ 0xdd,0x02, ++ 0x5c,0x02, ++ 0x12,0x03, ++ 0x31,0x03, ++ 0xaf,0x02, ++ 0xe4,0x03, ++ 0x71,0x00, ++ 0xae,0x00, ++ 0x24,0x00, ++ 0xde,0x01, ++ 0x96,0x01, ++ 0xe8,0x02, ++ 0xc0,0x03, ++ 0x86,0x00, ++ 0x97,0x03, ++ 0x6a,0x01, ++ 0x93,0x03, ++ 0x66,0x02, ++ 0x6d,0x01, ++ 0xf8,0x03, ++ 0x4c,0x02, ++ 0x3b,0x01, ++ 0x47,0x00, ++ 0x5d,0x02, ++ 0x82,0x03, ++ 0xec,0x01, ++ 0x2d,0x01, ++ 0x98,0x03, ++ 0x28,0x00, ++ 0x79,0x02, ++ 0x94,0x03, ++ 0x3d,0x03, ++ 0x48,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// WDR_Loc_TBL_7_SRAM ++//**************************************************** ++ unsigned char MST_WDR_Loc_TBL_7_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_TBL_7_SRAM_Main[][PQ_IP_WDR_Loc_TBL_7_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x58,0x03, ++ 0xcb,0x02, ++ 0x3b,0x00, ++ 0xd3,0x02, ++ 0x2e,0x01, ++ 0x0e,0x01, ++ 0xaa,0x03, ++ 0xe2,0x01, ++ 0xa3,0x03, ++ 0x4e,0x01, ++ 0xe4,0x03, ++ 0x61,0x03, ++ 0xd1,0x01, ++ 0xb1,0x00, ++ 0xd7,0x00, ++ 0x48,0x00, ++ 0xae,0x03, ++ 0x8d,0x03, ++ 0xf2,0x03, ++ 0x05,0x03, ++ 0xa5,0x01, ++ 0x69,0x02, ++ 0x29,0x01, ++ 0x6d,0x02, ++ 0x00,0x01, ++ 0xb0,0x02, ++ 0x2a,0x03, ++ 0x25,0x00, ++ 0xb1,0x00, ++ 0xdf,0x01, ++ 0xe6,0x01, ++ 0x37,0x01, ++ 0x1c,0x03, ++ 0xdc,0x01, ++ 0x54,0x02, ++ 0x25,0x03, ++ 0xf9,0x00, ++ 0xb7,0x00, ++ 0x56,0x02, ++ 0x8c,0x03, ++ 0x8a,0x03, ++ 0x37,0x02, ++ 0x33,0x00, ++ 0x6e,0x02, ++ 0x84,0x02, ++ 0x97,0x02, ++ 0xbe,0x03, ++ 0x53,0x02, ++ 0xd0,0x01, ++ 0xe7,0x02, ++ 0x8f,0x01, ++ 0x65,0x02, ++ 0x59,0x03, ++ 0x27,0x01, ++ 0x64,0x01, ++ 0x72,0x00, ++ 0x73,0x03, ++ 0x12,0x01, ++ 0x2d,0x01, ++ 0x70,0x01, ++ 0x7c,0x03, ++ 0x0b,0x00, ++ 0x8e,0x00, ++ 0xcd,0x02 ++}, ++ ++}; ++ ++//**************************************************** ++// YUV_Gamma_tblU_SRAM ++//**************************************************** ++ unsigned char MST_YUV_Gamma_tblU_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YUV_Gamma_tblU_SRAM_Main[][PQ_IP_YUV_Gamma_tblU_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x93,0x00, ++ 0x86,0x01, ++ 0x2d,0x00, ++ 0xa6,0x00, ++ 0xc3,0x00, ++ 0x0f,0x00, ++ 0x1e,0x01, ++ 0x61,0x00, ++ 0xd0,0x00, ++ 0x32,0x01, ++ 0x3a,0x01, ++ 0xd3,0x00, ++ 0xe0,0x01, ++ 0x9a,0x01, ++ 0xce,0x00, ++ 0x23,0x00, ++ 0xeb,0x00, ++ 0xa5,0x00, ++ 0x05,0x01, ++ 0xe6,0x00, ++ 0x69,0x01, ++ 0xec,0x00, ++ 0xc9,0x00, ++ 0xd3,0x01, ++ 0x59,0x00, ++ 0x19,0x01, ++ 0xd8,0x01, ++ 0xa5,0x01, ++ 0x70,0x01, ++ 0xe5,0x00, ++ 0x22,0x00, ++ 0x46,0x01, ++ 0x9f,0x00, ++ 0x67,0x00, ++ 0x5f,0x01, ++ 0x3f,0x00, ++ 0xbe,0x01, ++ 0x9f,0x01, ++ 0xee,0x00, ++ 0x57,0x01, ++ 0x95,0x00, ++ 0x3f,0x00, ++ 0xe8,0x01, ++ 0x8a,0x01, ++ 0x0a,0x01, ++ 0xb0,0x01, ++ 0x82,0x01, ++ 0x2a,0x01, ++ 0xa3,0x01, ++ 0x68,0x01, ++ 0xa1,0x01, ++ 0x4a,0x01, ++ 0x3d,0x00, ++ 0x65,0x01, ++ 0xb7,0x01, ++ 0x6c,0x01, ++ 0x02,0x01, ++ 0x05,0x01, ++ 0xda,0x01, ++ 0x67,0x01, ++ 0xae,0x01, ++ 0x05,0x00, ++ 0x23,0x00, ++ 0x94,0x01, ++ 0xfd,0x00, ++ 0xd0,0x01, ++ 0x43,0x00, ++ 0x35,0x01, ++ 0x6b,0x00, ++ 0x0c,0x01, ++ 0x5f,0x01, ++ 0x21,0x01, ++ 0x2e,0x00, ++ 0x5d,0x01, ++ 0x2c,0x00, ++ 0xaf,0x00, ++ 0x6d,0x01, ++ 0x75,0x01, ++ 0x45,0x01, ++ 0xdc,0x00, ++ 0xc0,0x00, ++ 0x5a,0x01, ++ 0xc9,0x01, ++ 0xba,0x01, ++ 0xe2,0x00, ++ 0xf1,0x00, ++ 0x31,0x00, ++ 0x17,0x00, ++ 0xb2,0x01, ++ 0xcb,0x00, ++ 0x6c,0x01, ++ 0x64,0x01, ++ 0x68,0x01, ++ 0x29,0x01, ++ 0x3d,0x00, ++ 0xe9,0x01, ++ 0x12,0x00, ++ 0x4e,0x01, ++ 0xcc,0x00, ++ 0x25,0x01, ++ 0x4c,0x01, ++ 0x02,0x01, ++ 0x87,0x00, ++ 0x7b,0x00, ++ 0x3e,0x00, ++ 0x5d,0x00, ++ 0x3b,0x00, ++ 0x1d,0x00, ++ 0xce,0x01, ++ 0xd6,0x01, ++ 0x6c,0x00, ++ 0x36,0x00, ++ 0x26,0x01, ++ 0x88,0x00, ++ 0xf0,0x01, ++ 0x53,0x00, ++ 0x61,0x00, ++ 0xbc,0x00, ++ 0xcb,0x00, ++ 0x0f,0x01, ++ 0x8c,0x01, ++ 0xb7,0x00, ++ 0x44,0x01, ++ 0xf9,0x01, ++ 0xe2,0x01, ++ 0xc1,0x01, ++ 0x45,0x01, ++ 0xc5,0x01 ++}, ++ ++}; ++ ++//**************************************************** ++// YUV_Gamma_tblV_SRAM ++//**************************************************** ++ unsigned char MST_YUV_Gamma_tblV_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YUV_Gamma_tblV_SRAM_Main[][PQ_IP_YUV_Gamma_tblV_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0xa7,0x00, ++ 0x9b,0x01, ++ 0x4b,0x00, ++ 0xea,0x01, ++ 0x57,0x00, ++ 0x2e,0x00, ++ 0x02,0x00, ++ 0xb1,0x00, ++ 0x2c,0x00, ++ 0x04,0x01, ++ 0x8c,0x01, ++ 0xef,0x01, ++ 0xfb,0x00, ++ 0xc1,0x00, ++ 0x76,0x01, ++ 0xed,0x01, ++ 0x6f,0x00, ++ 0x26,0x00, ++ 0xe2,0x01, ++ 0xdf,0x01, ++ 0xdf,0x00, ++ 0x76,0x00, ++ 0xfe,0x01, ++ 0xe0,0x00, ++ 0x60,0x00, ++ 0x17,0x01, ++ 0xb9,0x00, ++ 0x39,0x00, ++ 0x13,0x01, ++ 0x75,0x00, ++ 0xaf,0x00, ++ 0xe0,0x00, ++ 0xbc,0x00, ++ 0x24,0x00, ++ 0x5d,0x01, ++ 0x3e,0x00, ++ 0x92,0x01, ++ 0x3f,0x00, ++ 0x98,0x01, ++ 0x2c,0x00, ++ 0x50,0x00, ++ 0x0e,0x00, ++ 0x36,0x01, ++ 0x38,0x00, ++ 0x86,0x01, ++ 0xe4,0x01, ++ 0x0a,0x00, ++ 0x26,0x00, ++ 0x32,0x00, ++ 0x49,0x00, ++ 0x0a,0x00, ++ 0xb3,0x01, ++ 0x86,0x01, ++ 0x50,0x00, ++ 0xce,0x00, ++ 0x96,0x01, ++ 0x07,0x00, ++ 0x42,0x01, ++ 0x39,0x00, ++ 0xc2,0x01, ++ 0xd3,0x01, ++ 0x7d,0x01, ++ 0x6e,0x00, ++ 0xe9,0x00, ++ 0x41,0x00, ++ 0x98,0x00, ++ 0x02,0x01, ++ 0x3d,0x01, ++ 0xa1,0x00, ++ 0xc0,0x00, ++ 0x6f,0x01, ++ 0x71,0x00, ++ 0x5e,0x00, ++ 0x60,0x01, ++ 0xc3,0x00, ++ 0xfe,0x00, ++ 0x4a,0x00, ++ 0x00,0x01, ++ 0x95,0x00, ++ 0xa4,0x00, ++ 0x2b,0x01, ++ 0x65,0x00, ++ 0x34,0x01, ++ 0x28,0x00, ++ 0x98,0x01, ++ 0xf7,0x00, ++ 0x1d,0x01, ++ 0x5d,0x00, ++ 0x01,0x01, ++ 0x64,0x00, ++ 0xaa,0x01, ++ 0x60,0x00, ++ 0x05,0x00, ++ 0x79,0x01, ++ 0x06,0x01, ++ 0x1d,0x01, ++ 0x05,0x00, ++ 0x52,0x00, ++ 0x5a,0x01, ++ 0x11,0x00, ++ 0xf2,0x01, ++ 0xac,0x01, ++ 0x47,0x01, ++ 0x4a,0x01, ++ 0x69,0x00, ++ 0x96,0x01, ++ 0x93,0x01, ++ 0xac,0x00, ++ 0xf4,0x00, ++ 0x4b,0x01, ++ 0x1a,0x00, ++ 0x6f,0x00, ++ 0xad,0x00, ++ 0x52,0x00, ++ 0x02,0x00, ++ 0xe6,0x00, ++ 0x07,0x00, ++ 0xe6,0x00, ++ 0x2f,0x01, ++ 0x7b,0x01, ++ 0xdf,0x01, ++ 0x95,0x01, ++ 0xf1,0x00, ++ 0xf8,0x00, ++ 0xd5,0x01, ++ 0x23,0x00, ++ 0xf7,0x01, ++ 0x03,0x01 ++}, ++ ++}; ++ ++//**************************************************** ++// YUV_Gamma_tblY_SRAM ++//**************************************************** ++ unsigned char MST_YUV_Gamma_tblY_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YUV_Gamma_tblY_SRAM_Main[][PQ_IP_YUV_Gamma_tblY_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x60,0x01, ++ 0xa0,0x02, ++ 0x9e,0x02, ++ 0x76,0x01, ++ 0x4a,0x00, ++ 0x47,0x00, ++ 0x48,0x01, ++ 0x40,0x02, ++ 0xa9,0x00, ++ 0xa0,0x03, ++ 0xb6,0x03, ++ 0xbe,0x03, ++ 0x0c,0x03, ++ 0x2c,0x00, ++ 0x00,0x02, ++ 0x05,0x00, ++ 0x2c,0x00, ++ 0xef,0x00, ++ 0x82,0x01, ++ 0xa0,0x01, ++ 0x75,0x02, ++ 0x53,0x02, ++ 0xdf,0x03, ++ 0x0e,0x01, ++ 0x31,0x02, ++ 0x3e,0x00, ++ 0x2b,0x01, ++ 0xcb,0x00, ++ 0xd4,0x01, ++ 0x9b,0x03, ++ 0xcc,0x03, ++ 0x1c,0x00, ++ 0x20,0x02, ++ 0x71,0x00, ++ 0xc9,0x02, ++ 0xae,0x02, ++ 0xbf,0x03, ++ 0x96,0x03, ++ 0x13,0x01, ++ 0x3d,0x01, ++ 0xeb,0x01, ++ 0x42,0x01, ++ 0x72,0x02, ++ 0x3e,0x01, ++ 0xc5,0x03, ++ 0x70,0x03, ++ 0xb9,0x00, ++ 0xd8,0x03, ++ 0x08,0x00, ++ 0x65,0x01, ++ 0xd0,0x01, ++ 0x30,0x02, ++ 0xa0,0x00, ++ 0x4d,0x03, ++ 0x50,0x01, ++ 0x2a,0x03, ++ 0xe1,0x01, ++ 0x2c,0x03, ++ 0x32,0x02, ++ 0xca,0x00, ++ 0xe8,0x02, ++ 0x34,0x02, ++ 0x4b,0x03, ++ 0x4d,0x01, ++ 0xcd,0x02, ++ 0xa9,0x03, ++ 0x23,0x03, ++ 0x1d,0x02, ++ 0x4e,0x00, ++ 0x6e,0x00, ++ 0xd3,0x01, ++ 0xbc,0x00, ++ 0x81,0x03, ++ 0x56,0x00, ++ 0x7f,0x01, ++ 0xcd,0x03, ++ 0x47,0x03, ++ 0x6b,0x00, ++ 0x1a,0x00, ++ 0x56,0x00, ++ 0x01,0x02, ++ 0x33,0x03, ++ 0x03,0x03, ++ 0x56,0x01, ++ 0x45,0x03, ++ 0x27,0x02, ++ 0x2d,0x03, ++ 0xe2,0x01, ++ 0x1a,0x02, ++ 0x71,0x01, ++ 0x63,0x02, ++ 0xcd,0x03, ++ 0x6d,0x01, ++ 0x10,0x01, ++ 0x4e,0x00, ++ 0x15,0x03, ++ 0x52,0x02, ++ 0x91,0x00, ++ 0xdf,0x03, ++ 0x28,0x00, ++ 0xc3,0x01, ++ 0x64,0x00, ++ 0xbf,0x03, ++ 0x17,0x01, ++ 0x5e,0x01, ++ 0x09,0x02, ++ 0x58,0x02, ++ 0xfa,0x03, ++ 0xe8,0x00, ++ 0x1b,0x02, ++ 0x22,0x00, ++ 0x7e,0x02, ++ 0x14,0x00, ++ 0x6c,0x01, ++ 0xde,0x00, ++ 0xc7,0x00, ++ 0x45,0x02, ++ 0x49,0x00, ++ 0x3f,0x02, ++ 0xde,0x03, ++ 0xde,0x03, ++ 0x07,0x01, ++ 0xca,0x00, ++ 0xb2,0x01, ++ 0xc6,0x02, ++ 0xfe,0x00, ++ 0x64,0x01, ++ 0xc7,0x02, ++ 0xb8,0x01, ++ 0x09,0x01, ++ 0x52,0x00, ++ 0xd3,0x03, ++ 0x0c,0x00, ++ 0xb2,0x00, ++ 0x31,0x00, ++ 0x47,0x03, ++ 0x92,0x01, ++ 0x29,0x01, ++ 0x97,0x01, ++ 0xf6,0x00, ++ 0x1c,0x00, ++ 0x22,0x03, ++ 0xf1,0x01, ++ 0xf4,0x03, ++ 0x56,0x02, ++ 0xc5,0x00, ++ 0x43,0x02, ++ 0xd8,0x00, ++ 0x9a,0x01, ++ 0xb8,0x02, ++ 0x6d,0x00, ++ 0x6a,0x00, ++ 0x4f,0x02, ++ 0x8a,0x01, ++ 0x91,0x03, ++ 0xf6,0x00, ++ 0x7b,0x00, ++ 0x6e,0x02, ++ 0x3c,0x02, ++ 0x53,0x02, ++ 0x26,0x00, ++ 0x97,0x00, ++ 0xeb,0x02, ++ 0xc8,0x02, ++ 0x35,0x03, ++ 0x2f,0x02, ++ 0x9d,0x01, ++ 0xe9,0x00, ++ 0x4f,0x00, ++ 0x1f,0x02, ++ 0xf9,0x02, ++ 0x8b,0x00, ++ 0x79,0x00, ++ 0xc0,0x01, ++ 0xc6,0x03, ++ 0xfa,0x02, ++ 0x02,0x03, ++ 0x91,0x03, ++ 0x36,0x01, ++ 0x82,0x00, ++ 0x63,0x01, ++ 0x21,0x02, ++ 0xbd,0x00, ++ 0x6f,0x03, ++ 0xad,0x02, ++ 0x38,0x00, ++ 0x05,0x00, ++ 0xb8,0x02, ++ 0x2f,0x00, ++ 0x71,0x01, ++ 0xa5,0x03, ++ 0x4c,0x00, ++ 0xe7,0x02, ++ 0x5f,0x00, ++ 0x41,0x01, ++ 0x4c,0x01, ++ 0x6c,0x03, ++ 0x54,0x01, ++ 0x9b,0x03, ++ 0x35,0x00, ++ 0xe5,0x03, ++ 0xfa,0x02, ++ 0x59,0x01, ++ 0x29,0x03, ++ 0xb5,0x01, ++ 0xd4,0x03, ++ 0x01,0x01, ++ 0x73,0x02, ++ 0x72,0x02, ++ 0xc6,0x01, ++ 0xdb,0x02, ++ 0x58,0x01, ++ 0xdc,0x01, ++ 0xc9,0x02, ++ 0x57,0x03, ++ 0x79,0x01, ++ 0x5a,0x00, ++ 0xeb,0x03, ++ 0x8f,0x02, ++ 0xb7,0x02, ++ 0xa7,0x03, ++ 0xb7,0x01, ++ 0x90,0x03, ++ 0xe4,0x03, ++ 0x64,0x01, ++ 0x25,0x03, ++ 0x06,0x00, ++ 0x44,0x02, ++ 0xff,0x00, ++ 0x39,0x02, ++ 0xe3,0x02, ++ 0x06,0x00, ++ 0xc8,0x00, ++ 0x66,0x03, ++ 0xb1,0x02, ++ 0xdf,0x03, ++ 0xa4,0x03, ++ 0xe0,0x02, ++ 0x1f,0x02, ++ 0xe0,0x01, ++ 0x1e,0x03, ++ 0xf7,0x00, ++ 0x74,0x03, ++ 0x93,0x03, ++ 0x63,0x03, ++ 0x9a,0x00, ++ 0x83,0x01, ++ 0xaf,0x03, ++ 0xd6,0x00, ++ 0x22,0x01, ++ 0xbc,0x02, ++ 0x50,0x03, ++ 0xcb,0x00, ++ 0x90,0x02, ++ 0x0b,0x01, ++ 0xef,0x00 ++}, ++ ++}; ++ ++//**************************************************** ++// ColorEng_GM10to12_Tbl_R_SRAM ++//**************************************************** ++ unsigned char MST_ColorEng_GM10to12_Tbl_R_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM10to12_Tbl_R_SRAM_Main[][PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00, ++ 0x04,0x00, ++ 0x08,0x00, ++ 0x0c,0x00, ++ 0x10,0x00, ++ 0x13,0x00, ++ 0x15,0x00, ++ 0x18,0x00, ++ 0x1b,0x00, ++ 0x1e,0x00, ++ 0x21,0x00, ++ 0x24,0x00, ++ 0x28,0x00, ++ 0x2b,0x00, ++ 0x2f,0x00, ++ 0x32,0x00, ++ 0x36,0x00, ++ 0x39,0x00, ++ 0x3d,0x00, ++ 0x40,0x00, ++ 0x44,0x00, ++ 0x48,0x00, ++ 0x4c,0x00, ++ 0x50,0x00, ++ 0x53,0x00, ++ 0x57,0x00, ++ 0x5b,0x00, ++ 0x5f,0x00, ++ 0x63,0x00, ++ 0x67,0x00, ++ 0x6b,0x00, ++ 0x6f,0x00, ++ 0x74,0x00, ++ 0x78,0x00, ++ 0x7d,0x00, ++ 0x81,0x00, ++ 0x86,0x00, ++ 0x8a,0x00, ++ 0x8e,0x00, ++ 0x92,0x00, ++ 0x97,0x00, ++ 0x9c,0x00, ++ 0xa1,0x00, ++ 0xa6,0x00, ++ 0xab,0x00, ++ 0xb0,0x00, ++ 0xb5,0x00, ++ 0xba,0x00, ++ 0xbe,0x00, ++ 0xc4,0x00, ++ 0xca,0x00, ++ 0xd0,0x00, ++ 0xd6,0x00, ++ 0xdc,0x00, ++ 0xe1,0x00, ++ 0xe7,0x00, ++ 0xed,0x00, ++ 0xf3,0x00, ++ 0xf9,0x00, ++ 0x00,0x01, ++ 0x07,0x01, ++ 0x0e,0x01, ++ 0x16,0x01, ++ 0x1e,0x01, ++ 0x26,0x01, ++ 0x2e,0x01, ++ 0x36,0x01, ++ 0x3e,0x01, ++ 0x44,0x01, ++ 0x49,0x01, ++ 0x4e,0x01, ++ 0x54,0x01, ++ 0x59,0x01, ++ 0x5e,0x01, ++ 0x66,0x01, ++ 0x6e,0x01, ++ 0x74,0x01, ++ 0x7a,0x01, ++ 0x7f,0x01, ++ 0x84,0x01, ++ 0x8a,0x01, ++ 0x8f,0x01, ++ 0x96,0x01, ++ 0x9e,0x01, ++ 0xa4,0x01, ++ 0xa9,0x01, ++ 0xaf,0x01, ++ 0xb6,0x01, ++ 0xbe,0x01, ++ 0xc4,0x01, ++ 0xc9,0x01, ++ 0xce,0x01, ++ 0xd6,0x01, ++ 0xde,0x01, ++ 0xe4,0x01, ++ 0xea,0x01, ++ 0xef,0x01, ++ 0xf6,0x01, ++ 0xfe,0x01, ++ 0x06,0x02, ++ 0x0e,0x02, ++ 0x14,0x02, ++ 0x1a,0x02, ++ 0x1f,0x02, ++ 0x26,0x02, ++ 0x2e,0x02, ++ 0x36,0x02, ++ 0x3e,0x02, ++ 0x46,0x02, ++ 0x4e,0x02, ++ 0x56,0x02, ++ 0x5e,0x02, ++ 0x64,0x02, ++ 0x69,0x02, ++ 0x6f,0x02, ++ 0x76,0x02, ++ 0x7e,0x02, ++ 0x86,0x02, ++ 0x8e,0x02, ++ 0x96,0x02, ++ 0x9e,0x02, ++ 0xa6,0x02, ++ 0xae,0x02, ++ 0xb6,0x02, ++ 0xbe,0x02, ++ 0xc6,0x02, ++ 0xce,0x02, ++ 0xdc,0x02, ++ 0xe6,0x02, ++ 0xed,0x02, ++ 0xf4,0x02, ++ 0xfc,0x02, ++ 0x04,0x03, ++ 0x0c,0x03, ++ 0x14,0x03, ++ 0x1c,0x03, ++ 0x24,0x03, ++ 0x2c,0x03, ++ 0x38,0x03, ++ 0x44,0x03, ++ 0x4c,0x03, ++ 0x54,0x03, ++ 0x5c,0x03, ++ 0x68,0x03, ++ 0x74,0x03, ++ 0x7c,0x03, ++ 0x84,0x03, ++ 0x8c,0x03, ++ 0x98,0x03, ++ 0xa4,0x03, ++ 0xac,0x03, ++ 0xb8,0x03, ++ 0xc4,0x03, ++ 0xcc,0x03, ++ 0xd8,0x03, ++ 0xe4,0x03, ++ 0xec,0x03, ++ 0xf8,0x03, ++ 0x08,0x04, ++ 0x14,0x04, ++ 0x1c,0x04, ++ 0x28,0x04, ++ 0x34,0x04, ++ 0x3c,0x04, ++ 0x48,0x04, ++ 0x58,0x04, ++ 0x64,0x04, ++ 0x6c,0x04, ++ 0x78,0x04, ++ 0x88,0x04, ++ 0x98,0x04, ++ 0xa4,0x04, ++ 0xac,0x04, ++ 0xb8,0x04, ++ 0xc8,0x04, ++ 0xd8,0x04, ++ 0xe8,0x04, ++ 0xf8,0x04, ++ 0x08,0x05, ++ 0x14,0x05, ++ 0x1c,0x05, ++ 0x28,0x05, ++ 0x38,0x05, ++ 0x48,0x05, ++ 0x58,0x05, ++ 0x68,0x05, ++ 0x78,0x05, ++ 0x88,0x05, ++ 0x98,0x05, ++ 0xa8,0x05, ++ 0xb8,0x05, ++ 0xc8,0x05, ++ 0xd8,0x05, ++ 0xf0,0x05, ++ 0x08,0x06, ++ 0x18,0x06, ++ 0x28,0x06, ++ 0x38,0x06, ++ 0x48,0x06, ++ 0x60,0x06, ++ 0x78,0x06, ++ 0x88,0x06, ++ 0x98,0x06, ++ 0xb0,0x06, ++ 0xc8,0x06, ++ 0xd8,0x06, ++ 0xf0,0x06, ++ 0x08,0x07, ++ 0x20,0x07, ++ 0x38,0x07, ++ 0x50,0x07, ++ 0x68,0x07, ++ 0x80,0x07, ++ 0x96,0x07, ++ 0xa8,0x07, ++ 0xc8,0x07, ++ 0xe4,0x07, ++ 0xf8,0x07, ++ 0x18,0x08, ++ 0x38,0x08, ++ 0x58,0x08, ++ 0x78,0x08, ++ 0x98,0x08, ++ 0xb8,0x08, ++ 0xd8,0x08, ++ 0xf8,0x08, ++ 0x18,0x09, ++ 0x38,0x09, ++ 0x5c,0x09, ++ 0x90,0x09, ++ 0xb0,0x09, ++ 0xcb,0x09, ++ 0xe8,0x09, ++ 0x00,0x0a, ++ 0x20,0x0a, ++ 0x3a,0x0a, ++ 0x58,0x0a, ++ 0x78,0x0a, ++ 0x98,0x0a, ++ 0xb8,0x0a, ++ 0xe0,0x0a, ++ 0x00,0x0b, ++ 0x28,0x0b, ++ 0x50,0x0b, ++ 0x78,0x0b, ++ 0xa0,0x0b, ++ 0xd0,0x0b, ++ 0x00,0x0c, ++ 0x40,0x0c, ++ 0x70,0x0c, ++ 0xb0,0x0c, ++ 0x00,0x0d, ++ 0x50,0x0d, ++ 0xc0,0x0d, ++ 0x50,0x0e, ++ 0x80,0x0f ++}, ++ ++}; ++ ++//**************************************************** ++// ColorEng_GM10to12_Tbl_G_SRAM ++//**************************************************** ++ unsigned char MST_ColorEng_GM10to12_Tbl_G_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM10to12_Tbl_G_SRAM_Main[][PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00, ++ 0x09,0x00, ++ 0x12,0x00, ++ 0x1c,0x00, ++ 0x25,0x00, ++ 0x2e,0x00, ++ 0x37,0x00, ++ 0x41,0x00, ++ 0x50,0x00, ++ 0x5f,0x00, ++ 0x6e,0x00, ++ 0x82,0x00, ++ 0x91,0x00, ++ 0xa0,0x00, ++ 0xaf,0x00, ++ 0xb9,0x00, ++ 0xc3,0x00, ++ 0xd2,0x00, ++ 0xdc,0x00, ++ 0xe6,0x00, ++ 0xf0,0x00, ++ 0xfa,0x00, ++ 0x04,0x01, ++ 0x0e,0x01, ++ 0x18,0x01, ++ 0x22,0x01, ++ 0x2c,0x01, ++ 0x36,0x01, ++ 0x40,0x01, ++ 0x4a,0x01, ++ 0x54,0x01, ++ 0x5e,0x01, ++ 0x68,0x01, ++ 0x72,0x01, ++ 0x7a,0x01, ++ 0x82,0x01, ++ 0x8a,0x01, ++ 0x92,0x01, ++ 0x9a,0x01, ++ 0xa2,0x01, ++ 0xaa,0x01, ++ 0xb2,0x01, ++ 0xba,0x01, ++ 0xc2,0x01, ++ 0xca,0x01, ++ 0xd2,0x01, ++ 0xda,0x01, ++ 0xe2,0x01, ++ 0xea,0x01, ++ 0xf2,0x01, ++ 0xfa,0x01, ++ 0x01,0x02, ++ 0x08,0x02, ++ 0x0f,0x02, ++ 0x16,0x02, ++ 0x1d,0x02, ++ 0x24,0x02, ++ 0x2b,0x02, ++ 0x32,0x02, ++ 0x39,0x02, ++ 0x40,0x02, ++ 0x47,0x02, ++ 0x4e,0x02, ++ 0x55,0x02, ++ 0x5c,0x02, ++ 0x63,0x02, ++ 0x6a,0x02, ++ 0x71,0x02, ++ 0x78,0x02, ++ 0x7f,0x02, ++ 0x86,0x02, ++ 0x8d,0x02, ++ 0x94,0x02, ++ 0x9b,0x02, ++ 0xa2,0x02, ++ 0xa9,0x02, ++ 0xb0,0x02, ++ 0xb7,0x02, ++ 0xbe,0x02, ++ 0xc5,0x02, ++ 0xcb,0x02, ++ 0xd1,0x02, ++ 0xd7,0x02, ++ 0xdd,0x02, ++ 0xe3,0x02, ++ 0xe9,0x02, ++ 0xef,0x02, ++ 0xf5,0x02, ++ 0xfc,0x02, ++ 0x02,0x03, ++ 0x07,0x03, ++ 0x0b,0x03, ++ 0x0f,0x03, ++ 0x13,0x03, ++ 0x17,0x03, ++ 0x1b,0x03, ++ 0x1f,0x03, ++ 0x23,0x03, ++ 0x27,0x03, ++ 0x2b,0x03, ++ 0x2f,0x03, ++ 0x33,0x03, ++ 0x37,0x03, ++ 0x3a,0x03, ++ 0x3d,0x03, ++ 0x40,0x03, ++ 0x43,0x03, ++ 0x46,0x03, ++ 0x49,0x03, ++ 0x4c,0x03, ++ 0x4f,0x03, ++ 0x52,0x03, ++ 0x55,0x03, ++ 0x58,0x03, ++ 0x5b,0x03, ++ 0x5e,0x03, ++ 0x61,0x03, ++ 0x64,0x03, ++ 0x67,0x03, ++ 0x6a,0x03, ++ 0x6d,0x03, ++ 0x70,0x03, ++ 0x73,0x03, ++ 0x76,0x03, ++ 0x79,0x03, ++ 0x7c,0x03, ++ 0x7f,0x03, ++ 0x81,0x03, ++ 0x83,0x03, ++ 0x85,0x03, ++ 0x87,0x03, ++ 0x89,0x03, ++ 0x8b,0x03, ++ 0x8d,0x03, ++ 0x8f,0x03, ++ 0x91,0x03, ++ 0x93,0x03, ++ 0x95,0x03, ++ 0x97,0x03, ++ 0x99,0x03, ++ 0x9b,0x03, ++ 0x9d,0x03, ++ 0x9f,0x03, ++ 0xa1,0x03, ++ 0xa3,0x03, ++ 0xa5,0x03, ++ 0xa7,0x03, ++ 0xa9,0x03, ++ 0xab,0x03, ++ 0xad,0x03, ++ 0xaf,0x03, ++ 0xb1,0x03, ++ 0xb3,0x03, ++ 0xb5,0x03, ++ 0xb7,0x03, ++ 0xb9,0x03, ++ 0xbb,0x03, ++ 0xbd,0x03, ++ 0xbf,0x03, ++ 0xc0,0x03, ++ 0xc1,0x03, ++ 0xc2,0x03, ++ 0xc3,0x03, ++ 0xc4,0x03, ++ 0xc5,0x03, ++ 0xc6,0x03, ++ 0xc7,0x03, ++ 0xc8,0x03, ++ 0xc9,0x03, ++ 0xca,0x03, ++ 0xcb,0x03, ++ 0xcc,0x03, ++ 0xcd,0x03, ++ 0xce,0x03, ++ 0xcf,0x03, ++ 0xd0,0x03, ++ 0xd1,0x03, ++ 0xd2,0x03, ++ 0xd3,0x03, ++ 0xd4,0x03, ++ 0xd5,0x03, ++ 0xd6,0x03, ++ 0xd7,0x03, ++ 0xd8,0x03, ++ 0xd9,0x03, ++ 0xda,0x03, ++ 0xdb,0x03, ++ 0xdc,0x03, ++ 0xdd,0x03, ++ 0xde,0x03, ++ 0xdf,0x03, ++ 0xe0,0x03, ++ 0xe1,0x03, ++ 0xe2,0x03, ++ 0xe3,0x03, ++ 0xe4,0x03, ++ 0xe5,0x03, ++ 0xe6,0x03, ++ 0xe7,0x03, ++ 0xe7,0x03, ++ 0xe8,0x03, ++ 0xe8,0x03, ++ 0xe9,0x03, ++ 0xe9,0x03, ++ 0xea,0x03, ++ 0xea,0x03, ++ 0xeb,0x03, ++ 0xeb,0x03, ++ 0xec,0x03, ++ 0xec,0x03, ++ 0xed,0x03, ++ 0xed,0x03, ++ 0xee,0x03, ++ 0xee,0x03, ++ 0xef,0x03, ++ 0xef,0x03, ++ 0xf0,0x03, ++ 0xf0,0x03, ++ 0xf1,0x03, ++ 0xf1,0x03, ++ 0xf2,0x03, ++ 0xf2,0x03, ++ 0xf3,0x03, ++ 0xf3,0x03, ++ 0xf4,0x03, ++ 0xf4,0x03, ++ 0xf5,0x03, ++ 0xf5,0x03, ++ 0xf6,0x03, ++ 0xf6,0x03, ++ 0xf7,0x03, ++ 0xf7,0x03, ++ 0xf8,0x03, ++ 0xf8,0x03, ++ 0xf9,0x03, ++ 0xf9,0x03, ++ 0xfa,0x03, ++ 0xfa,0x03, ++ 0xfb,0x03, ++ 0xfb,0x03, ++ 0xfc,0x03, ++ 0xfc,0x03, ++ 0xfd,0x03, ++ 0xfd,0x03, ++ 0xfe,0x03, ++ 0xfe,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// ColorEng_GM10to12_Tbl_B_SRAM ++//**************************************************** ++ unsigned char MST_ColorEng_GM10to12_Tbl_B_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM10to12_Tbl_B_SRAM_Main[][PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00, ++ 0x09,0x00, ++ 0x12,0x00, ++ 0x1c,0x00, ++ 0x25,0x00, ++ 0x2e,0x00, ++ 0x37,0x00, ++ 0x41,0x00, ++ 0x50,0x00, ++ 0x5f,0x00, ++ 0x6e,0x00, ++ 0x82,0x00, ++ 0x91,0x00, ++ 0xa0,0x00, ++ 0xaf,0x00, ++ 0xb9,0x00, ++ 0xc3,0x00, ++ 0xd2,0x00, ++ 0xdc,0x00, ++ 0xe6,0x00, ++ 0xf0,0x00, ++ 0xfa,0x00, ++ 0x04,0x01, ++ 0x0e,0x01, ++ 0x18,0x01, ++ 0x22,0x01, ++ 0x2c,0x01, ++ 0x36,0x01, ++ 0x40,0x01, ++ 0x4a,0x01, ++ 0x54,0x01, ++ 0x5e,0x01, ++ 0x68,0x01, ++ 0x72,0x01, ++ 0x7a,0x01, ++ 0x82,0x01, ++ 0x8a,0x01, ++ 0x92,0x01, ++ 0x9a,0x01, ++ 0xa2,0x01, ++ 0xaa,0x01, ++ 0xb2,0x01, ++ 0xba,0x01, ++ 0xc2,0x01, ++ 0xca,0x01, ++ 0xd2,0x01, ++ 0xda,0x01, ++ 0xe2,0x01, ++ 0xea,0x01, ++ 0xf2,0x01, ++ 0xfa,0x01, ++ 0x01,0x02, ++ 0x08,0x02, ++ 0x0f,0x02, ++ 0x16,0x02, ++ 0x1d,0x02, ++ 0x24,0x02, ++ 0x2b,0x02, ++ 0x32,0x02, ++ 0x39,0x02, ++ 0x40,0x02, ++ 0x47,0x02, ++ 0x4e,0x02, ++ 0x55,0x02, ++ 0x5c,0x02, ++ 0x63,0x02, ++ 0x6a,0x02, ++ 0x71,0x02, ++ 0x78,0x02, ++ 0x7f,0x02, ++ 0x86,0x02, ++ 0x8d,0x02, ++ 0x94,0x02, ++ 0x9b,0x02, ++ 0xa2,0x02, ++ 0xa9,0x02, ++ 0xb0,0x02, ++ 0xb7,0x02, ++ 0xbe,0x02, ++ 0xc5,0x02, ++ 0xcb,0x02, ++ 0xd1,0x02, ++ 0xd7,0x02, ++ 0xdd,0x02, ++ 0xe3,0x02, ++ 0xe9,0x02, ++ 0xef,0x02, ++ 0xf5,0x02, ++ 0xfc,0x02, ++ 0x02,0x03, ++ 0x07,0x03, ++ 0x0b,0x03, ++ 0x0f,0x03, ++ 0x13,0x03, ++ 0x17,0x03, ++ 0x1b,0x03, ++ 0x1f,0x03, ++ 0x23,0x03, ++ 0x27,0x03, ++ 0x2b,0x03, ++ 0x2f,0x03, ++ 0x33,0x03, ++ 0x37,0x03, ++ 0x3a,0x03, ++ 0x3d,0x03, ++ 0x40,0x03, ++ 0x43,0x03, ++ 0x46,0x03, ++ 0x49,0x03, ++ 0x4c,0x03, ++ 0x4f,0x03, ++ 0x52,0x03, ++ 0x55,0x03, ++ 0x58,0x03, ++ 0x5b,0x03, ++ 0x5e,0x03, ++ 0x61,0x03, ++ 0x64,0x03, ++ 0x67,0x03, ++ 0x6a,0x03, ++ 0x6d,0x03, ++ 0x70,0x03, ++ 0x73,0x03, ++ 0x76,0x03, ++ 0x79,0x03, ++ 0x7c,0x03, ++ 0x7f,0x03, ++ 0x81,0x03, ++ 0x83,0x03, ++ 0x85,0x03, ++ 0x87,0x03, ++ 0x89,0x03, ++ 0x8b,0x03, ++ 0x8d,0x03, ++ 0x8f,0x03, ++ 0x91,0x03, ++ 0x93,0x03, ++ 0x95,0x03, ++ 0x97,0x03, ++ 0x99,0x03, ++ 0x9b,0x03, ++ 0x9d,0x03, ++ 0x9f,0x03, ++ 0xa1,0x03, ++ 0xa3,0x03, ++ 0xa5,0x03, ++ 0xa7,0x03, ++ 0xa9,0x03, ++ 0xab,0x03, ++ 0xad,0x03, ++ 0xaf,0x03, ++ 0xb1,0x03, ++ 0xb3,0x03, ++ 0xb5,0x03, ++ 0xb7,0x03, ++ 0xb9,0x03, ++ 0xbb,0x03, ++ 0xbd,0x03, ++ 0xbf,0x03, ++ 0xc0,0x03, ++ 0xc1,0x03, ++ 0xc2,0x03, ++ 0xc3,0x03, ++ 0xc4,0x03, ++ 0xc5,0x03, ++ 0xc6,0x03, ++ 0xc7,0x03, ++ 0xc8,0x03, ++ 0xc9,0x03, ++ 0xca,0x03, ++ 0xcb,0x03, ++ 0xcc,0x03, ++ 0xcd,0x03, ++ 0xce,0x03, ++ 0xcf,0x03, ++ 0xd0,0x03, ++ 0xd1,0x03, ++ 0xd2,0x03, ++ 0xd3,0x03, ++ 0xd4,0x03, ++ 0xd5,0x03, ++ 0xd6,0x03, ++ 0xd7,0x03, ++ 0xd8,0x03, ++ 0xd9,0x03, ++ 0xda,0x03, ++ 0xdb,0x03, ++ 0xdc,0x03, ++ 0xdd,0x03, ++ 0xde,0x03, ++ 0xdf,0x03, ++ 0xe0,0x03, ++ 0xe1,0x03, ++ 0xe2,0x03, ++ 0xe3,0x03, ++ 0xe4,0x03, ++ 0xe5,0x03, ++ 0xe6,0x03, ++ 0xe7,0x03, ++ 0xe7,0x03, ++ 0xe8,0x03, ++ 0xe8,0x03, ++ 0xe9,0x03, ++ 0xe9,0x03, ++ 0xea,0x03, ++ 0xea,0x03, ++ 0xeb,0x03, ++ 0xeb,0x03, ++ 0xec,0x03, ++ 0xec,0x03, ++ 0xed,0x03, ++ 0xed,0x03, ++ 0xee,0x03, ++ 0xee,0x03, ++ 0xef,0x03, ++ 0xef,0x03, ++ 0xf0,0x03, ++ 0xf0,0x03, ++ 0xf1,0x03, ++ 0xf1,0x03, ++ 0xf2,0x03, ++ 0xf2,0x03, ++ 0xf3,0x03, ++ 0xf3,0x03, ++ 0xf4,0x03, ++ 0xf4,0x03, ++ 0xf5,0x03, ++ 0xf5,0x03, ++ 0xf6,0x03, ++ 0xf6,0x03, ++ 0xf7,0x03, ++ 0xf7,0x03, ++ 0xf8,0x03, ++ 0xf8,0x03, ++ 0xf9,0x03, ++ 0xf9,0x03, ++ 0xfa,0x03, ++ 0xfa,0x03, ++ 0xfb,0x03, ++ 0xfb,0x03, ++ 0xfc,0x03, ++ 0xfc,0x03, ++ 0xfd,0x03, ++ 0xfd,0x03, ++ 0xfe,0x03, ++ 0xfe,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// ColorEng_GM12to10_CrcTbl_R_SRAM ++//**************************************************** ++ unsigned char MST_ColorEng_GM12to10_CrcTbl_R_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM12to10_CrcTbl_R_SRAM_Main[][PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00, ++ 0x09,0x00, ++ 0x12,0x00, ++ 0x1c,0x00, ++ 0x25,0x00, ++ 0x2e,0x00, ++ 0x37,0x00, ++ 0x41,0x00, ++ 0x50,0x00, ++ 0x5f,0x00, ++ 0x6e,0x00, ++ 0x82,0x00, ++ 0x91,0x00, ++ 0xa0,0x00, ++ 0xaf,0x00, ++ 0xb9,0x00, ++ 0xc3,0x00, ++ 0xd2,0x00, ++ 0xdc,0x00, ++ 0xe6,0x00, ++ 0xf0,0x00, ++ 0xfa,0x00, ++ 0x04,0x01, ++ 0x0e,0x01, ++ 0x18,0x01, ++ 0x22,0x01, ++ 0x2c,0x01, ++ 0x36,0x01, ++ 0x40,0x01, ++ 0x4a,0x01, ++ 0x54,0x01, ++ 0x5e,0x01, ++ 0x68,0x01, ++ 0x72,0x01, ++ 0x7a,0x01, ++ 0x82,0x01, ++ 0x8a,0x01, ++ 0x92,0x01, ++ 0x9a,0x01, ++ 0xa2,0x01, ++ 0xaa,0x01, ++ 0xb2,0x01, ++ 0xba,0x01, ++ 0xc2,0x01, ++ 0xca,0x01, ++ 0xd2,0x01, ++ 0xda,0x01, ++ 0xe2,0x01, ++ 0xea,0x01, ++ 0xf2,0x01, ++ 0xfa,0x01, ++ 0x01,0x02, ++ 0x08,0x02, ++ 0x0f,0x02, ++ 0x16,0x02, ++ 0x1d,0x02, ++ 0x24,0x02, ++ 0x2b,0x02, ++ 0x32,0x02, ++ 0x39,0x02, ++ 0x40,0x02, ++ 0x47,0x02, ++ 0x4e,0x02, ++ 0x55,0x02, ++ 0x5c,0x02, ++ 0x63,0x02, ++ 0x6a,0x02, ++ 0x71,0x02, ++ 0x78,0x02, ++ 0x7f,0x02, ++ 0x86,0x02, ++ 0x8d,0x02, ++ 0x94,0x02, ++ 0x9b,0x02, ++ 0xa2,0x02, ++ 0xa9,0x02, ++ 0xb0,0x02, ++ 0xb7,0x02, ++ 0xbe,0x02, ++ 0xc5,0x02, ++ 0xcb,0x02, ++ 0xd1,0x02, ++ 0xd7,0x02, ++ 0xdd,0x02, ++ 0xe3,0x02, ++ 0xe9,0x02, ++ 0xef,0x02, ++ 0xf5,0x02, ++ 0xfc,0x02, ++ 0x02,0x03, ++ 0x07,0x03, ++ 0x0b,0x03, ++ 0x0f,0x03, ++ 0x13,0x03, ++ 0x17,0x03, ++ 0x1b,0x03, ++ 0x1f,0x03, ++ 0x23,0x03, ++ 0x27,0x03, ++ 0x2b,0x03, ++ 0x2f,0x03, ++ 0x33,0x03, ++ 0x37,0x03, ++ 0x3a,0x03, ++ 0x3d,0x03, ++ 0x40,0x03, ++ 0x43,0x03, ++ 0x46,0x03, ++ 0x49,0x03, ++ 0x4c,0x03, ++ 0x4f,0x03, ++ 0x52,0x03, ++ 0x55,0x03, ++ 0x58,0x03, ++ 0x5b,0x03, ++ 0x5e,0x03, ++ 0x61,0x03, ++ 0x64,0x03, ++ 0x67,0x03, ++ 0x6a,0x03, ++ 0x6d,0x03, ++ 0x70,0x03, ++ 0x73,0x03, ++ 0x76,0x03, ++ 0x79,0x03, ++ 0x7c,0x03, ++ 0x7f,0x03, ++ 0x81,0x03, ++ 0x83,0x03, ++ 0x85,0x03, ++ 0x87,0x03, ++ 0x89,0x03, ++ 0x8b,0x03, ++ 0x8d,0x03, ++ 0x8f,0x03, ++ 0x91,0x03, ++ 0x93,0x03, ++ 0x95,0x03, ++ 0x97,0x03, ++ 0x99,0x03, ++ 0x9b,0x03, ++ 0x9d,0x03, ++ 0x9f,0x03, ++ 0xa1,0x03, ++ 0xa3,0x03, ++ 0xa5,0x03, ++ 0xa7,0x03, ++ 0xa9,0x03, ++ 0xab,0x03, ++ 0xad,0x03, ++ 0xaf,0x03, ++ 0xb1,0x03, ++ 0xb3,0x03, ++ 0xb5,0x03, ++ 0xb7,0x03, ++ 0xb9,0x03, ++ 0xbb,0x03, ++ 0xbd,0x03, ++ 0xbf,0x03, ++ 0xc0,0x03, ++ 0xc1,0x03, ++ 0xc2,0x03, ++ 0xc3,0x03, ++ 0xc4,0x03, ++ 0xc5,0x03, ++ 0xc6,0x03, ++ 0xc7,0x03, ++ 0xc8,0x03, ++ 0xc9,0x03, ++ 0xca,0x03, ++ 0xcb,0x03, ++ 0xcc,0x03, ++ 0xcd,0x03, ++ 0xce,0x03, ++ 0xcf,0x03, ++ 0xd0,0x03, ++ 0xd1,0x03, ++ 0xd2,0x03, ++ 0xd3,0x03, ++ 0xd4,0x03, ++ 0xd5,0x03, ++ 0xd6,0x03, ++ 0xd7,0x03, ++ 0xd8,0x03, ++ 0xd9,0x03, ++ 0xda,0x03, ++ 0xdb,0x03, ++ 0xdc,0x03, ++ 0xdd,0x03, ++ 0xde,0x03, ++ 0xdf,0x03, ++ 0xe0,0x03, ++ 0xe1,0x03, ++ 0xe2,0x03, ++ 0xe3,0x03, ++ 0xe4,0x03, ++ 0xe5,0x03, ++ 0xe6,0x03, ++ 0xe7,0x03, ++ 0xe7,0x03, ++ 0xe8,0x03, ++ 0xe8,0x03, ++ 0xe9,0x03, ++ 0xe9,0x03, ++ 0xea,0x03, ++ 0xea,0x03, ++ 0xeb,0x03, ++ 0xeb,0x03, ++ 0xec,0x03, ++ 0xec,0x03, ++ 0xed,0x03, ++ 0xed,0x03, ++ 0xee,0x03, ++ 0xee,0x03, ++ 0xef,0x03, ++ 0xef,0x03, ++ 0xf0,0x03, ++ 0xf0,0x03, ++ 0xf1,0x03, ++ 0xf1,0x03, ++ 0xf2,0x03, ++ 0xf2,0x03, ++ 0xf3,0x03, ++ 0xf3,0x03, ++ 0xf4,0x03, ++ 0xf4,0x03, ++ 0xf5,0x03, ++ 0xf5,0x03, ++ 0xf6,0x03, ++ 0xf6,0x03, ++ 0xf7,0x03, ++ 0xf7,0x03, ++ 0xf8,0x03, ++ 0xf8,0x03, ++ 0xf9,0x03, ++ 0xf9,0x03, ++ 0xfa,0x03, ++ 0xfa,0x03, ++ 0xfb,0x03, ++ 0xfb,0x03, ++ 0xfc,0x03, ++ 0xfc,0x03, ++ 0xfd,0x03, ++ 0xfd,0x03, ++ 0xfe,0x03, ++ 0xfe,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// ColorEng_GM12to10_CrcTbl_G_SRAM ++//**************************************************** ++ unsigned char MST_ColorEng_GM12to10_CrcTbl_G_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM12to10_CrcTbl_G_SRAM_Main[][PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00, ++ 0x09,0x00, ++ 0x12,0x00, ++ 0x1c,0x00, ++ 0x25,0x00, ++ 0x2e,0x00, ++ 0x37,0x00, ++ 0x41,0x00, ++ 0x50,0x00, ++ 0x5f,0x00, ++ 0x6e,0x00, ++ 0x82,0x00, ++ 0x91,0x00, ++ 0xa0,0x00, ++ 0xaf,0x00, ++ 0xb9,0x00, ++ 0xc3,0x00, ++ 0xd2,0x00, ++ 0xdc,0x00, ++ 0xe6,0x00, ++ 0xf0,0x00, ++ 0xfa,0x00, ++ 0x04,0x01, ++ 0x0e,0x01, ++ 0x18,0x01, ++ 0x22,0x01, ++ 0x2c,0x01, ++ 0x36,0x01, ++ 0x40,0x01, ++ 0x4a,0x01, ++ 0x54,0x01, ++ 0x5e,0x01, ++ 0x68,0x01, ++ 0x72,0x01, ++ 0x7a,0x01, ++ 0x82,0x01, ++ 0x8a,0x01, ++ 0x92,0x01, ++ 0x9a,0x01, ++ 0xa2,0x01, ++ 0xaa,0x01, ++ 0xb2,0x01, ++ 0xba,0x01, ++ 0xc2,0x01, ++ 0xca,0x01, ++ 0xd2,0x01, ++ 0xda,0x01, ++ 0xe2,0x01, ++ 0xea,0x01, ++ 0xf2,0x01, ++ 0xfa,0x01, ++ 0x01,0x02, ++ 0x08,0x02, ++ 0x0f,0x02, ++ 0x16,0x02, ++ 0x1d,0x02, ++ 0x24,0x02, ++ 0x2b,0x02, ++ 0x32,0x02, ++ 0x39,0x02, ++ 0x40,0x02, ++ 0x47,0x02, ++ 0x4e,0x02, ++ 0x55,0x02, ++ 0x5c,0x02, ++ 0x63,0x02, ++ 0x6a,0x02, ++ 0x71,0x02, ++ 0x78,0x02, ++ 0x7f,0x02, ++ 0x86,0x02, ++ 0x8d,0x02, ++ 0x94,0x02, ++ 0x9b,0x02, ++ 0xa2,0x02, ++ 0xa9,0x02, ++ 0xb0,0x02, ++ 0xb7,0x02, ++ 0xbe,0x02, ++ 0xc5,0x02, ++ 0xcb,0x02, ++ 0xd1,0x02, ++ 0xd7,0x02, ++ 0xdd,0x02, ++ 0xe3,0x02, ++ 0xe9,0x02, ++ 0xef,0x02, ++ 0xf5,0x02, ++ 0xfc,0x02, ++ 0x02,0x03, ++ 0x07,0x03, ++ 0x0b,0x03, ++ 0x0f,0x03, ++ 0x13,0x03, ++ 0x17,0x03, ++ 0x1b,0x03, ++ 0x1f,0x03, ++ 0x23,0x03, ++ 0x27,0x03, ++ 0x2b,0x03, ++ 0x2f,0x03, ++ 0x33,0x03, ++ 0x37,0x03, ++ 0x3a,0x03, ++ 0x3d,0x03, ++ 0x40,0x03, ++ 0x43,0x03, ++ 0x46,0x03, ++ 0x49,0x03, ++ 0x4c,0x03, ++ 0x4f,0x03, ++ 0x52,0x03, ++ 0x55,0x03, ++ 0x58,0x03, ++ 0x5b,0x03, ++ 0x5e,0x03, ++ 0x61,0x03, ++ 0x64,0x03, ++ 0x67,0x03, ++ 0x6a,0x03, ++ 0x6d,0x03, ++ 0x70,0x03, ++ 0x73,0x03, ++ 0x76,0x03, ++ 0x79,0x03, ++ 0x7c,0x03, ++ 0x7f,0x03, ++ 0x81,0x03, ++ 0x83,0x03, ++ 0x85,0x03, ++ 0x87,0x03, ++ 0x89,0x03, ++ 0x8b,0x03, ++ 0x8d,0x03, ++ 0x8f,0x03, ++ 0x91,0x03, ++ 0x93,0x03, ++ 0x95,0x03, ++ 0x97,0x03, ++ 0x99,0x03, ++ 0x9b,0x03, ++ 0x9d,0x03, ++ 0x9f,0x03, ++ 0xa1,0x03, ++ 0xa3,0x03, ++ 0xa5,0x03, ++ 0xa7,0x03, ++ 0xa9,0x03, ++ 0xab,0x03, ++ 0xad,0x03, ++ 0xaf,0x03, ++ 0xb1,0x03, ++ 0xb3,0x03, ++ 0xb5,0x03, ++ 0xb7,0x03, ++ 0xb9,0x03, ++ 0xbb,0x03, ++ 0xbd,0x03, ++ 0xbf,0x03, ++ 0xc0,0x03, ++ 0xc1,0x03, ++ 0xc2,0x03, ++ 0xc3,0x03, ++ 0xc4,0x03, ++ 0xc5,0x03, ++ 0xc6,0x03, ++ 0xc7,0x03, ++ 0xc8,0x03, ++ 0xc9,0x03, ++ 0xca,0x03, ++ 0xcb,0x03, ++ 0xcc,0x03, ++ 0xcd,0x03, ++ 0xce,0x03, ++ 0xcf,0x03, ++ 0xd0,0x03, ++ 0xd1,0x03, ++ 0xd2,0x03, ++ 0xd3,0x03, ++ 0xd4,0x03, ++ 0xd5,0x03, ++ 0xd6,0x03, ++ 0xd7,0x03, ++ 0xd8,0x03, ++ 0xd9,0x03, ++ 0xda,0x03, ++ 0xdb,0x03, ++ 0xdc,0x03, ++ 0xdd,0x03, ++ 0xde,0x03, ++ 0xdf,0x03, ++ 0xe0,0x03, ++ 0xe1,0x03, ++ 0xe2,0x03, ++ 0xe3,0x03, ++ 0xe4,0x03, ++ 0xe5,0x03, ++ 0xe6,0x03, ++ 0xe7,0x03, ++ 0xe7,0x03, ++ 0xe8,0x03, ++ 0xe8,0x03, ++ 0xe9,0x03, ++ 0xe9,0x03, ++ 0xea,0x03, ++ 0xea,0x03, ++ 0xeb,0x03, ++ 0xeb,0x03, ++ 0xec,0x03, ++ 0xec,0x03, ++ 0xed,0x03, ++ 0xed,0x03, ++ 0xee,0x03, ++ 0xee,0x03, ++ 0xef,0x03, ++ 0xef,0x03, ++ 0xf0,0x03, ++ 0xf0,0x03, ++ 0xf1,0x03, ++ 0xf1,0x03, ++ 0xf2,0x03, ++ 0xf2,0x03, ++ 0xf3,0x03, ++ 0xf3,0x03, ++ 0xf4,0x03, ++ 0xf4,0x03, ++ 0xf5,0x03, ++ 0xf5,0x03, ++ 0xf6,0x03, ++ 0xf6,0x03, ++ 0xf7,0x03, ++ 0xf7,0x03, ++ 0xf8,0x03, ++ 0xf8,0x03, ++ 0xf9,0x03, ++ 0xf9,0x03, ++ 0xfa,0x03, ++ 0xfa,0x03, ++ 0xfb,0x03, ++ 0xfb,0x03, ++ 0xfc,0x03, ++ 0xfc,0x03, ++ 0xfd,0x03, ++ 0xfd,0x03, ++ 0xfe,0x03, ++ 0xfe,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// ColorEng_GM12to10_CrcTbl_B_SRAM ++//**************************************************** ++ unsigned char MST_ColorEng_GM12to10_CrcTbl_B_SRAM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM12to10_CrcTbl_B_SRAM_Main[][PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_SIZE_Main]= ++{ ++{//OFF ++ 0x00,0x00, ++ 0x09,0x00, ++ 0x12,0x00, ++ 0x1c,0x00, ++ 0x25,0x00, ++ 0x2e,0x00, ++ 0x37,0x00, ++ 0x41,0x00, ++ 0x50,0x00, ++ 0x5f,0x00, ++ 0x6e,0x00, ++ 0x82,0x00, ++ 0x91,0x00, ++ 0xa0,0x00, ++ 0xaf,0x00, ++ 0xb9,0x00, ++ 0xc3,0x00, ++ 0xd2,0x00, ++ 0xdc,0x00, ++ 0xe6,0x00, ++ 0xf0,0x00, ++ 0xfa,0x00, ++ 0x04,0x01, ++ 0x0e,0x01, ++ 0x18,0x01, ++ 0x22,0x01, ++ 0x2c,0x01, ++ 0x36,0x01, ++ 0x40,0x01, ++ 0x4a,0x01, ++ 0x54,0x01, ++ 0x5e,0x01, ++ 0x68,0x01, ++ 0x72,0x01, ++ 0x7a,0x01, ++ 0x82,0x01, ++ 0x8a,0x01, ++ 0x92,0x01, ++ 0x9a,0x01, ++ 0xa2,0x01, ++ 0xaa,0x01, ++ 0xb2,0x01, ++ 0xba,0x01, ++ 0xc2,0x01, ++ 0xca,0x01, ++ 0xd2,0x01, ++ 0xda,0x01, ++ 0xe2,0x01, ++ 0xea,0x01, ++ 0xf2,0x01, ++ 0xfa,0x01, ++ 0x01,0x02, ++ 0x08,0x02, ++ 0x0f,0x02, ++ 0x16,0x02, ++ 0x1d,0x02, ++ 0x24,0x02, ++ 0x2b,0x02, ++ 0x32,0x02, ++ 0x39,0x02, ++ 0x40,0x02, ++ 0x47,0x02, ++ 0x4e,0x02, ++ 0x55,0x02, ++ 0x5c,0x02, ++ 0x63,0x02, ++ 0x6a,0x02, ++ 0x71,0x02, ++ 0x78,0x02, ++ 0x7f,0x02, ++ 0x86,0x02, ++ 0x8d,0x02, ++ 0x94,0x02, ++ 0x9b,0x02, ++ 0xa2,0x02, ++ 0xa9,0x02, ++ 0xb0,0x02, ++ 0xb7,0x02, ++ 0xbe,0x02, ++ 0xc5,0x02, ++ 0xcb,0x02, ++ 0xd1,0x02, ++ 0xd7,0x02, ++ 0xdd,0x02, ++ 0xe3,0x02, ++ 0xe9,0x02, ++ 0xef,0x02, ++ 0xf5,0x02, ++ 0xfc,0x02, ++ 0x02,0x03, ++ 0x07,0x03, ++ 0x0b,0x03, ++ 0x0f,0x03, ++ 0x13,0x03, ++ 0x17,0x03, ++ 0x1b,0x03, ++ 0x1f,0x03, ++ 0x23,0x03, ++ 0x27,0x03, ++ 0x2b,0x03, ++ 0x2f,0x03, ++ 0x33,0x03, ++ 0x37,0x03, ++ 0x3a,0x03, ++ 0x3d,0x03, ++ 0x40,0x03, ++ 0x43,0x03, ++ 0x46,0x03, ++ 0x49,0x03, ++ 0x4c,0x03, ++ 0x4f,0x03, ++ 0x52,0x03, ++ 0x55,0x03, ++ 0x58,0x03, ++ 0x5b,0x03, ++ 0x5e,0x03, ++ 0x61,0x03, ++ 0x64,0x03, ++ 0x67,0x03, ++ 0x6a,0x03, ++ 0x6d,0x03, ++ 0x70,0x03, ++ 0x73,0x03, ++ 0x76,0x03, ++ 0x79,0x03, ++ 0x7c,0x03, ++ 0x7f,0x03, ++ 0x81,0x03, ++ 0x83,0x03, ++ 0x85,0x03, ++ 0x87,0x03, ++ 0x89,0x03, ++ 0x8b,0x03, ++ 0x8d,0x03, ++ 0x8f,0x03, ++ 0x91,0x03, ++ 0x93,0x03, ++ 0x95,0x03, ++ 0x97,0x03, ++ 0x99,0x03, ++ 0x9b,0x03, ++ 0x9d,0x03, ++ 0x9f,0x03, ++ 0xa1,0x03, ++ 0xa3,0x03, ++ 0xa5,0x03, ++ 0xa7,0x03, ++ 0xa9,0x03, ++ 0xab,0x03, ++ 0xad,0x03, ++ 0xaf,0x03, ++ 0xb1,0x03, ++ 0xb3,0x03, ++ 0xb5,0x03, ++ 0xb7,0x03, ++ 0xb9,0x03, ++ 0xbb,0x03, ++ 0xbd,0x03, ++ 0xbf,0x03, ++ 0xc0,0x03, ++ 0xc1,0x03, ++ 0xc2,0x03, ++ 0xc3,0x03, ++ 0xc4,0x03, ++ 0xc5,0x03, ++ 0xc6,0x03, ++ 0xc7,0x03, ++ 0xc8,0x03, ++ 0xc9,0x03, ++ 0xca,0x03, ++ 0xcb,0x03, ++ 0xcc,0x03, ++ 0xcd,0x03, ++ 0xce,0x03, ++ 0xcf,0x03, ++ 0xd0,0x03, ++ 0xd1,0x03, ++ 0xd2,0x03, ++ 0xd3,0x03, ++ 0xd4,0x03, ++ 0xd5,0x03, ++ 0xd6,0x03, ++ 0xd7,0x03, ++ 0xd8,0x03, ++ 0xd9,0x03, ++ 0xda,0x03, ++ 0xdb,0x03, ++ 0xdc,0x03, ++ 0xdd,0x03, ++ 0xde,0x03, ++ 0xdf,0x03, ++ 0xe0,0x03, ++ 0xe1,0x03, ++ 0xe2,0x03, ++ 0xe3,0x03, ++ 0xe4,0x03, ++ 0xe5,0x03, ++ 0xe6,0x03, ++ 0xe7,0x03, ++ 0xe7,0x03, ++ 0xe8,0x03, ++ 0xe8,0x03, ++ 0xe9,0x03, ++ 0xe9,0x03, ++ 0xea,0x03, ++ 0xea,0x03, ++ 0xeb,0x03, ++ 0xeb,0x03, ++ 0xec,0x03, ++ 0xec,0x03, ++ 0xed,0x03, ++ 0xed,0x03, ++ 0xee,0x03, ++ 0xee,0x03, ++ 0xef,0x03, ++ 0xef,0x03, ++ 0xf0,0x03, ++ 0xf0,0x03, ++ 0xf1,0x03, ++ 0xf1,0x03, ++ 0xf2,0x03, ++ 0xf2,0x03, ++ 0xf3,0x03, ++ 0xf3,0x03, ++ 0xf4,0x03, ++ 0xf4,0x03, ++ 0xf5,0x03, ++ 0xf5,0x03, ++ 0xf6,0x03, ++ 0xf6,0x03, ++ 0xf7,0x03, ++ 0xf7,0x03, ++ 0xf8,0x03, ++ 0xf8,0x03, ++ 0xf9,0x03, ++ 0xf9,0x03, ++ 0xfa,0x03, ++ 0xfa,0x03, ++ 0xfb,0x03, ++ 0xfb,0x03, ++ 0xfc,0x03, ++ 0xfc,0x03, ++ 0xfd,0x03, ++ 0xfd,0x03, ++ 0xfe,0x03, ++ 0xfe,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03, ++ 0xff,0x03 ++}, ++ ++}; ++ ++//**************************************************** ++// YEE ++//**************************************************** ++ unsigned char MST_YEE_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YEE_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_YEE_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK28_00_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_00_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_01_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_01_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_02_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_03_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_03_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_04_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_04_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_05_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_05_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_06_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_06_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_07_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_07_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_08_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_08_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_09_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_09_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0A_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0A_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0B_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_0F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_10_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_10_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_11_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_11_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_12_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_12_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_13_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_13_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_14_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_15_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_15_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_16_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_16_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_17_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_17_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_18_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_18_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_19_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_19_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1A_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1B_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1C_L), 0xff, 0x60/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1D_L), 0xff, 0xff/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1D_H), 0x0f, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1E_L), 0xff, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_1F_L), 0x0f, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_20_L), 0xff, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_20_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_21_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_21_H), 0x03, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_22_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_22_H), 0x03, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_23_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_23_H), 0x03, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_24_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_24_H), 0x03, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_25_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_25_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_25_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_25_L), 0x70, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_26_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_26_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_26_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_27_L), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_27_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_27_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_28_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_28_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_29_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_29_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2A_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2B_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2D_L), 0xff, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2E_L), 0xff, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2F_L), 0x0f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_2F_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_30_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_30_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_31_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_32_L), 0xff, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_32_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_33_L), 0xff, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_33_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_34_L), 0xff, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_34_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_35_L), 0x3f, 0x3f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_35_H), 0x3f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_36_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_36_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_37_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_37_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_38_L), 0xff, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_39_L), 0x0f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_39_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3A_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3A_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3B_L), 0x0f, 0x0a/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3D_L), 0xff, 0x1e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3E_L), 0xff, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3F_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_3F_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_40_L), 0x0f, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_40_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_41_L), 0x0f, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_42_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_42_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_43_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_43_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_44_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_44_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_45_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_45_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_46_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_46_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_47_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_47_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_48_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_48_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_49_L), 0x0f, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_49_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4A_L), 0x0f, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4B_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4B_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4C_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4D_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4E_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4F_L), 0xff, 0xa4/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_4F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_50_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_50_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_51_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_51_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_52_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_52_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_53_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_53_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_54_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_54_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_55_L), 0xff, 0xff/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_55_H), 0x0f, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_56_L), 0xff, 0xff/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_56_H), 0x0f, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_60_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_60_H), 0x0f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_61_L), 0xff, 0xff/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_61_H), 0x0f, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_62_L), 0xff, 0x9b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_62_H), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_63_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_63_H), 0x0f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_64_L), 0xff, 0xa0/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_64_H), 0x0f, 0x0e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_65_L), 0xff, 0x25/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_65_H), 0x0f, 0x0d/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_66_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_66_H), 0x0f, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_67_L), 0xff, 0x17/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_67_H), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_68_L), 0xff, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_68_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_69_L), 0xff, 0x32/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_69_H), 0x0f, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6A_L), 0xff, 0x59/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6A_H), 0x0f, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6B_L), 0xff, 0x75/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6B_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6C_L), 0xff, 0x53/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6C_H), 0x0f, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6D_L), 0xff, 0xad/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6D_H), 0x0f, 0x0e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6E_H), 0x0f, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_6F_H), 0x0f, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_70_L), 0xff, 0x53/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_70_H), 0x0f, 0x0e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_71_L), 0xff, 0xad/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_71_H), 0x0f, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_72_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_72_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// YEE_AC_LUT ++//**************************************************** ++ unsigned char MST_YEE_AC_LUT_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YEE_AC_LUT_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_YEE_AC_LUT_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK28_58_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_58_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_59_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_59_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5A_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5B_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5C_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5D_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5E_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5F_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_5F_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_73_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_73_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_74_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_74_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_75_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_75_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_76_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_76_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_77_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_77_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_78_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_78_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_79_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_79_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7A_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7B_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7C_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7D_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7E_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_7E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_3E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_3E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5E_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5F_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5F_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_76_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_76_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_77_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_77_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_78_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_78_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_79_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_79_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7A_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7B_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7C_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7D_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7E_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_7E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_57_L), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_57_L), 0x0c, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK28_57_L), 0x30, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// WDR_Glob ++//**************************************************** ++ unsigned char MST_WDR_Glob_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Glob_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_WDR_Glob_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK27_00_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_00_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_00_L), 0x3c, 0x08/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_01_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_01_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_02_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_02_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_03_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_04_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_04_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_04_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_04_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_05_L), 0x0f, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_05_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_05_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_05_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_06_L), 0x0f, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_06_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_06_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_06_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_07_L), 0x0f, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_07_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_07_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_07_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_08_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_08_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_08_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_08_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_09_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_09_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0A_L), 0xff, 0x50/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0A_H), 0xff, 0xaf/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0B_L), 0xff, 0x1e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0B_H), 0xff, 0x78/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0C_L), 0xff, 0x49/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0C_H), 0xff, 0x60/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0D_L), 0xff, 0xdf/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0D_H), 0xff, 0x48/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0E_L), 0xff, 0xa7/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0E_H), 0xff, 0x3c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0F_L), 0xff, 0x66/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_0F_H), 0xff, 0x2f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_10_L), 0xff, 0x2e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_10_H), 0xff, 0x23/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_11_L), 0xff, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_11_H), 0xff, 0x1d/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_12_L), 0xff, 0x36/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_12_H), 0xff, 0x19/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_13_L), 0xff, 0x88/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_13_H), 0xff, 0x14/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_14_L), 0xff, 0xbe/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_14_H), 0xff, 0x0f/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_15_L), 0xff, 0x86/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_15_H), 0xff, 0x0b/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_16_L), 0xff, 0x76/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_16_H), 0xff, 0x09/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_17_L), 0xff, 0x4e/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_17_H), 0xff, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_18_L), 0xff, 0x23/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_18_H), 0xff, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_19_L), 0xff, 0x60/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_19_H), 0xff, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1A_L), 0xff, 0xd5/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1A_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1B_L), 0xff, 0x6c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1B_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1C_L), 0xff, 0x19/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1C_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1D_L), 0xff, 0xd5/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1D_H), 0xff, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1E_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1E_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1E_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1E_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1F_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1F_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1F_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_1F_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_20_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_20_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_21_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_21_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_22_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_22_H), 0xff, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_23_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_23_H), 0xff, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_24_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_24_H), 0xff, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_25_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_25_H), 0xff, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_26_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_26_H), 0xff, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_27_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_27_H), 0xff, 0x03/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_28_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_28_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_29_L), 0x0f, 0x0c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_29_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_29_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_29_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2A_L), 0x0f, 0x0c/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2A_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2A_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2A_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2B_H), 0xff, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2C_H), 0xff, 0x14/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2D_H), 0xff, 0x24/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2E_H), 0xff, 0x34/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_2F_H), 0xff, 0x44/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_30_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_30_H), 0xff, 0x54/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_31_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_31_H), 0xff, 0x64/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_32_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_32_H), 0xff, 0x74/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_33_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_33_H), 0xff, 0x84/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_34_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// WDR_Loc ++//**************************************************** ++ unsigned char MST_WDR_Loc_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_WDR_Loc_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_WDR_Loc_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK27_37_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_37_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_38_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_38_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_38_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_38_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_39_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_39_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_39_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_39_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3A_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3B_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_3F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_40_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_40_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_41_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_41_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_42_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_42_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_43_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_43_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_44_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_44_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_45_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_45_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_46_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_46_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_47_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_47_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_48_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_48_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_49_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_49_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_4F_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_50_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_50_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_51_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_51_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_52_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_52_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_53_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_53_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_54_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_54_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_55_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_55_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_56_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_56_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_57_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_57_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_58_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_58_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_59_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_59_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5E_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_5F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_60_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_61_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_61_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_62_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_62_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_62_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_62_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_63_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_63_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_63_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_63_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_64_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_64_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_65_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_65_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_66_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_66_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_67_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_67_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_68_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_68_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_69_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_69_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6A_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6B_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6D_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6D_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6D_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6D_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6E_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6E_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6E_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6E_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_6F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_70_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_70_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_71_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_71_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_72_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_72_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_73_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_73_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_74_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_74_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_75_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_75_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_76_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_76_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_77_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK27_77_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// MXNR ++//**************************************************** ++ unsigned char MST_MXNR_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_MXNR_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_MXNR_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK26_00_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_00_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_01_L), 0x7f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_01_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_02_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_02_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_03_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_03_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_04_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_04_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_05_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_05_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_06_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_06_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_07_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_07_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_08_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_08_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_09_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_09_H), 0x03, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// UV_ADJUST ++//**************************************************** ++ unsigned char MST_UV_ADJUST_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_UV_ADJUST_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_UV_ADJUST_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK26_20_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_20_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_20_L), 0x0c, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_20_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_20_L), 0x60, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_20_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_21_L), 0x0f, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_21_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_21_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_21_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_22_L), 0x0f, 0x06/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_22_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_22_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_22_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_23_L), 0x0f, 0x07/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_23_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_23_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_23_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_24_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_24_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_24_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_24_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_25_L), 0x0f, 0x05/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_25_L), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_25_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_25_H), 0xf0, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_26_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_26_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_27_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_27_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_28_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_28_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_29_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_29_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2A_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2A_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2B_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2B_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2C_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2D_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2E_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2F_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_2F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_30_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_30_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_31_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_31_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_32_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_32_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_33_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_33_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_34_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_34_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_35_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_35_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_36_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_36_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_37_L), 0xff, 0x80/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_37_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_38_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_38_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_39_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_39_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_3A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_3A_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// XNR ++//**************************************************** ++ unsigned char MST_XNR_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_XNR_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_XNR_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK26_50_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_50_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_50_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_50_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_50_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_51_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_51_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_52_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_52_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_53_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_54_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_54_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_55_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_55_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_56_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_56_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_57_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_57_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_58_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_58_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_59_L), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5A_L), 0x7f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5A_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_5B_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// YC10_UVM10 ++//**************************************************** ++ unsigned char MST_YC10_UVM10_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YC10_UVM10_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_YC10_UVM10_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK26_60_L), 0x01, 0x01/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_60_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_61_L), 0xff, 0x40/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_62_L), 0x7f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_63_L), 0xff, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_64_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_65_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_66_L), 0xff, 0x20/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// Color_Transfer ++//**************************************************** ++ unsigned char MST_Color_Transfer_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_Color_Transfer_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_Color_Transfer_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK26_68_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_68_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_69_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_69_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6A_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6B_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6D_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6E_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_6F_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_70_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_70_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_71_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_71_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_72_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_72_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_73_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_73_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_74_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_74_H), 0x07, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_75_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_75_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// YUV_Gamma ++//**************************************************** ++ unsigned char MST_YUV_Gamma_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_YUV_Gamma_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_YUV_Gamma_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK26_40_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_40_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4B_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4C_H), 0x03, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4D_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK26_4E_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_422to444 ++//**************************************************** ++ unsigned char MST_ColorEng_422to444_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_422to444_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_422to444_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_6A_L), 0x06, 0x02/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_YUVtoRGB ++//**************************************************** ++ unsigned char MST_ColorEng_YUVtoRGB_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_YUVtoRGB_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_YUVtoRGB_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_60_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_61_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_61_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_62_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_62_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_63_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_63_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_64_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_64_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_65_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_65_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_66_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_66_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_67_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_67_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_68_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_68_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_69_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_69_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_GM10to12 ++//**************************************************** ++ unsigned char MST_ColorEng_GM10to12_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM10to12_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_GM10to12_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_76_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_76_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_76_L), 0xfc, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_76_H), 0x3f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_76_H), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_CCM ++//**************************************************** ++ unsigned char MST_ColorEng_CCM_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_CCM_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_CCM_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_62_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_63_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_63_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_64_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_64_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_65_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_65_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_66_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_66_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_67_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_67_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_68_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_68_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_69_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_69_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6A_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6B_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_78_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_79_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_79_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_HSV ++//**************************************************** ++ unsigned char MST_ColorEng_HSV_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_HSV_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_HSV_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK10_60_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_61_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_61_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_62_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_62_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_63_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_63_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_64_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_64_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_65_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_65_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_66_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_66_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_67_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_67_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_68_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_68_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_69_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_69_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6A_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6B_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6C_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6C_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6D_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6E_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_6F_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_70_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_70_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_71_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_71_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_72_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_72_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_73_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_73_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_74_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_74_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_75_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_75_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_76_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_76_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_77_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_77_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_78_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK10_78_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_70_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_70_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_71_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_71_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_72_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_72_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_73_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_73_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_74_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_74_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_75_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_75_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_76_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_76_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_77_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_77_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_78_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_78_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_79_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_79_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_7A_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_7A_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_7B_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK12_7B_H), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_GM12to10 ++//**************************************************** ++ unsigned char MST_ColorEng_GM12to10_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_GM12to10_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_GM12to10_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_77_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_77_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_77_L), 0xfc, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_77_H), 0x0f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_77_H), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_RGBtoYUV ++//**************************************************** ++ unsigned char MST_ColorEng_RGBtoYUV_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_RGBtoYUV_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_RGBtoYUV_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x20, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x40, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_L), 0x80, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_H), 0x01, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_H), 0x02, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_H), 0x04, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6C_H), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6D_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6D_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6E_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6E_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6F_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_6F_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_70_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_70_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_71_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_71_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_72_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_72_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_73_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_73_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_74_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_74_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_75_L), 0xff, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_75_H), 0x1f, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// ColorEng_444to422 ++//**************************************************** ++ unsigned char MST_ColorEng_444to422_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_ColorEng_444to422_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_ColorEng_444to422_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK11_60_L), 0x07, 0x04/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_60_L), 0x08, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_SC_BK11_60_L), 0x10, 0x00/*OFF*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// SWDriver ++//**************************************************** ++ unsigned char MST_SWDriver_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SWDriver_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SWDriver_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++//**************************************************** ++// SC_End ++//**************************************************** ++ unsigned char MST_SC_End_COM_Main[][4] = ++{ // Reg Mask Value ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ unsigned char MST_SC_End_Main[][REG_ADDR_SIZE+REG_MASK_SIZE+PQ_IP_SC_End_NUMS_Main]= ++{ ++ { PQ_MAP_REG(REG_SC_BK22_7F_L), 0x07, 0x07/*End*/, }, ++ { PQ_MAP_REG(REG_TABLE_END), 0x00, 0x00 } ++}; ++ ++ ++ EN_IPTAB_INFO PQ_IPTAB_INFO_Main[]= ++{ ++{*MST_MCNR_COM_Main, *MST_MCNR_Main, PQ_IP_MCNR_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_LDC_COM_Main, *MST_LDC_Main, PQ_IP_LDC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_LDC_422_444_422_COM_Main, *MST_LDC_422_444_422_Main, PQ_IP_LDC_422_444_422_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_NLM_COM_Main, *MST_NLM_Main, PQ_IP_NLM_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422to444_COM_Main, *MST_422to444_Main, PQ_IP_422to444_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_COM_Main, *MST_VIP_Main, PQ_IP_VIP_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_pseudo_COM_Main, *MST_VIP_pseudo_Main, PQ_IP_VIP_pseudo_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LineBuffer_COM_Main, *MST_VIP_LineBuffer_Main, PQ_IP_VIP_LineBuffer_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_HLPF_COM_Main, *MST_VIP_HLPF_Main, PQ_IP_VIP_HLPF_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_HLPF_dither_COM_Main, *MST_VIP_HLPF_dither_Main, PQ_IP_VIP_HLPF_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_VLPF_coef1_COM_Main, *MST_VIP_VLPF_coef1_Main, PQ_IP_VIP_VLPF_coef1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_VLPF_coef2_COM_Main, *MST_VIP_VLPF_coef2_Main, PQ_IP_VIP_VLPF_coef2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_VLPF_dither_COM_Main, *MST_VIP_VLPF_dither_Main, PQ_IP_VIP_VLPF_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_COM_Main, *MST_VIP_Peaking_Main, PQ_IP_VIP_Peaking_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_band_COM_Main, *MST_VIP_Peaking_band_Main, PQ_IP_VIP_Peaking_band_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_adptive_COM_Main, *MST_VIP_Peaking_adptive_Main, PQ_IP_VIP_Peaking_adptive_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_Pcoring_COM_Main, *MST_VIP_Peaking_Pcoring_Main, PQ_IP_VIP_Peaking_Pcoring_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_Pcoring_ad_Y_COM_Main, *MST_VIP_Peaking_Pcoring_ad_Y_Main, PQ_IP_VIP_Peaking_Pcoring_ad_Y_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_gain_COM_Main, *MST_VIP_Peaking_gain_Main, PQ_IP_VIP_Peaking_gain_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Peaking_gain_ad_Y_COM_Main, *MST_VIP_Peaking_gain_ad_Y_Main, PQ_IP_VIP_Peaking_gain_ad_Y_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_COM_Main, *MST_VIP_LCE_Main, PQ_IP_VIP_LCE_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_dither_COM_Main, *MST_VIP_LCE_dither_Main, PQ_IP_VIP_LCE_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_setting_COM_Main, *MST_VIP_LCE_setting_Main, PQ_IP_VIP_LCE_setting_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_LCE_curve_COM_Main, *MST_VIP_LCE_curve_Main, PQ_IP_VIP_LCE_curve_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_His_range_COM_Main, *MST_VIP_DLC_His_range_Main, PQ_IP_VIP_DLC_His_range_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_COM_Main, *MST_VIP_DLC_Main, PQ_IP_VIP_DLC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_dither_COM_Main, *MST_VIP_DLC_dither_Main, PQ_IP_VIP_DLC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_His_rangeH_COM_Main, *MST_VIP_DLC_His_rangeH_Main, PQ_IP_VIP_DLC_His_rangeH_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_His_rangeV_COM_Main, *MST_VIP_DLC_His_rangeV_Main, PQ_IP_VIP_DLC_His_rangeV_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_DLC_PC_COM_Main, *MST_VIP_DLC_PC_Main, PQ_IP_VIP_DLC_PC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_YC_gain_offset_COM_Main, *MST_VIP_YC_gain_offset_Main, PQ_IP_VIP_YC_gain_offset_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_UVC_COM_Main, *MST_VIP_UVC_Main, PQ_IP_VIP_UVC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_full_range_COM_Main, *MST_VIP_FCC_full_range_Main, PQ_IP_VIP_FCC_full_range_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_bdry_dist_COM_Main, *MST_VIP_FCC_bdry_dist_Main, PQ_IP_VIP_FCC_bdry_dist_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T1_COM_Main, *MST_VIP_FCC_T1_Main, PQ_IP_VIP_FCC_T1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T2_COM_Main, *MST_VIP_FCC_T2_Main, PQ_IP_VIP_FCC_T2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T3_COM_Main, *MST_VIP_FCC_T3_Main, PQ_IP_VIP_FCC_T3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T4_COM_Main, *MST_VIP_FCC_T4_Main, PQ_IP_VIP_FCC_T4_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T5_COM_Main, *MST_VIP_FCC_T5_Main, PQ_IP_VIP_FCC_T5_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T6_COM_Main, *MST_VIP_FCC_T6_Main, PQ_IP_VIP_FCC_T6_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T7_COM_Main, *MST_VIP_FCC_T7_Main, PQ_IP_VIP_FCC_T7_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T8_COM_Main, *MST_VIP_FCC_T8_Main, PQ_IP_VIP_FCC_T8_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_FCC_T9_COM_Main, *MST_VIP_FCC_T9_Main, PQ_IP_VIP_FCC_T9_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_COM_Main, *MST_VIP_IHC_Main, PQ_IP_VIP_IHC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_Ymode_COM_Main, *MST_VIP_IHC_Ymode_Main, PQ_IP_VIP_IHC_Ymode_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_dither_COM_Main, *MST_VIP_IHC_dither_Main, PQ_IP_VIP_IHC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IHC_CRD_SRAM_COM_Main, *MST_VIP_IHC_CRD_SRAM_Main, PQ_IP_VIP_IHC_CRD_SRAM_NUMS_Main, PQ_TABTYPE_VIP_IHC_CRD_SRAM}, ++{*MST_VIP_IHC_SETTING_COM_Main, *MST_VIP_IHC_SETTING_Main, PQ_IP_VIP_IHC_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_COM_Main, *MST_VIP_ICC_Main, PQ_IP_VIP_ICC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_Ymode_COM_Main, *MST_VIP_ICC_Ymode_Main, PQ_IP_VIP_ICC_Ymode_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_dither_COM_Main, *MST_VIP_ICC_dither_Main, PQ_IP_VIP_ICC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ICC_CRD_SRAM_COM_Main, *MST_VIP_ICC_CRD_SRAM_Main, PQ_IP_VIP_ICC_CRD_SRAM_NUMS_Main, PQ_TABTYPE_VIP_ICC_CRD_SRAM}, ++{*MST_VIP_ICC_SETTING_COM_Main, *MST_VIP_ICC_SETTING_Main, PQ_IP_VIP_ICC_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Ymode_Yvalue_ALL_COM_Main, *MST_VIP_Ymode_Yvalue_ALL_Main, PQ_IP_VIP_Ymode_Yvalue_ALL_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_Ymode_Yvalue_SETTING_COM_Main, *MST_VIP_Ymode_Yvalue_SETTING_Main, PQ_IP_VIP_Ymode_Yvalue_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IBC_COM_Main, *MST_VIP_IBC_Main, PQ_IP_VIP_IBC_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IBC_dither_COM_Main, *MST_VIP_IBC_dither_Main, PQ_IP_VIP_IBC_dither_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_IBC_SETTING_COM_Main, *MST_VIP_IBC_SETTING_Main, PQ_IP_VIP_IBC_SETTING_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_ACK_COM_Main, *MST_VIP_ACK_Main, PQ_IP_VIP_ACK_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VIP_YCbCr_Clip_COM_Main, *MST_VIP_YCbCr_Clip_Main, PQ_IP_VIP_YCbCr_Clip_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Y_SC1_COM_Main, *MST_VSP_Y_SC1_Main, PQ_IP_VSP_Y_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_C_SC1_COM_Main, *MST_VSP_C_SC1_Main, PQ_IP_VSP_C_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_CoRing_SC1_COM_Main, *MST_VSP_CoRing_SC1_Main, PQ_IP_VSP_CoRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_DeRing_SC1_COM_Main, *MST_VSP_DeRing_SC1_Main, PQ_IP_VSP_DeRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Dither_SC1_COM_Main, *MST_VSP_Dither_SC1_Main, PQ_IP_VSP_Dither_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_PreVBound_SC1_COM_Main, *MST_VSP_PreVBound_SC1_Main, PQ_IP_VSP_PreVBound_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_AntiPAL_filter_SC1_COM_Main, *MST_AntiPAL_filter_SC1_Main, PQ_IP_AntiPAL_filter_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422To444_SC1_COM_Main, *MST_422To444_SC1_Main, PQ_IP_422To444_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Y_SC1_COM_Main, *MST_HSP_Y_SC1_Main, PQ_IP_HSP_Y_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_C_SC1_COM_Main, *MST_HSP_C_SC1_Main, PQ_IP_HSP_C_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_CoRing_SC1_COM_Main, *MST_HSP_CoRing_SC1_Main, PQ_IP_HSP_CoRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_DeRing_SC1_COM_Main, *MST_HSP_DeRing_SC1_Main, PQ_IP_HSP_DeRing_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Dither_SC1_COM_Main, *MST_HSP_Dither_SC1_Main, PQ_IP_HSP_Dither_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HnonLinear_SC1_COM_Main, *MST_HnonLinear_SC1_Main, PQ_IP_HnonLinear_SC1_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_SRAM1_COM_Main, *MST_SRAM1_Main, PQ_IP_SRAM1_NUMS_Main, PQ_TABTYPE_SRAM1}, ++{*MST_SRAM2_COM_Main, *MST_SRAM2_Main, PQ_IP_SRAM2_NUMS_Main, PQ_TABTYPE_SRAM2}, ++{*MST_SRAM3_COM_Main, *MST_SRAM3_Main, PQ_IP_SRAM3_NUMS_Main, PQ_TABTYPE_SRAM3}, ++{*MST_SRAM4_COM_Main, *MST_SRAM4_Main, PQ_IP_SRAM4_NUMS_Main, PQ_TABTYPE_SRAM4}, ++{*MST_C_SRAM1_COM_Main, *MST_C_SRAM1_Main, PQ_IP_C_SRAM1_NUMS_Main, PQ_TABTYPE_C_SRAM1}, ++{*MST_C_SRAM2_COM_Main, *MST_C_SRAM2_Main, PQ_IP_C_SRAM2_NUMS_Main, PQ_TABTYPE_C_SRAM2}, ++{*MST_C_SRAM3_COM_Main, *MST_C_SRAM3_Main, PQ_IP_C_SRAM3_NUMS_Main, PQ_TABTYPE_C_SRAM3}, ++{*MST_C_SRAM4_COM_Main, *MST_C_SRAM4_Main, PQ_IP_C_SRAM4_NUMS_Main, PQ_TABTYPE_C_SRAM4}, ++{*MST_VSP_Y_SC2_COM_Main, *MST_VSP_Y_SC2_Main, PQ_IP_VSP_Y_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_C_SC2_COM_Main, *MST_VSP_C_SC2_Main, PQ_IP_VSP_C_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_CoRing_SC2_COM_Main, *MST_VSP_CoRing_SC2_Main, PQ_IP_VSP_CoRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_DeRing_SC2_COM_Main, *MST_VSP_DeRing_SC2_Main, PQ_IP_VSP_DeRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Dither_SC2_COM_Main, *MST_VSP_Dither_SC2_Main, PQ_IP_VSP_Dither_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_PreVBound_SC2_COM_Main, *MST_VSP_PreVBound_SC2_Main, PQ_IP_VSP_PreVBound_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_AntiPAL_filter_SC2_COM_Main, *MST_AntiPAL_filter_SC2_Main, PQ_IP_AntiPAL_filter_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422To444_SC2_COM_Main, *MST_422To444_SC2_Main, PQ_IP_422To444_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Y_SC2_COM_Main, *MST_HSP_Y_SC2_Main, PQ_IP_HSP_Y_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_C_SC2_COM_Main, *MST_HSP_C_SC2_Main, PQ_IP_HSP_C_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_CoRing_SC2_COM_Main, *MST_HSP_CoRing_SC2_Main, PQ_IP_HSP_CoRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_DeRing_SC2_COM_Main, *MST_HSP_DeRing_SC2_Main, PQ_IP_HSP_DeRing_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Dither_SC2_COM_Main, *MST_HSP_Dither_SC2_Main, PQ_IP_HSP_Dither_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HnonLinear_SC2_COM_Main, *MST_HnonLinear_SC2_Main, PQ_IP_HnonLinear_SC2_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Y_SC3_COM_Main, *MST_VSP_Y_SC3_Main, PQ_IP_VSP_Y_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_C_SC3_COM_Main, *MST_VSP_C_SC3_Main, PQ_IP_VSP_C_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_CoRing_SC3_COM_Main, *MST_VSP_CoRing_SC3_Main, PQ_IP_VSP_CoRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_DeRing_SC3_COM_Main, *MST_VSP_DeRing_SC3_Main, PQ_IP_VSP_DeRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_Dither_SC3_COM_Main, *MST_VSP_Dither_SC3_Main, PQ_IP_VSP_Dither_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_VSP_PreVBound_SC3_COM_Main, *MST_VSP_PreVBound_SC3_Main, PQ_IP_VSP_PreVBound_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_AntiPAL_filter_SC3_COM_Main, *MST_AntiPAL_filter_SC3_Main, PQ_IP_AntiPAL_filter_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_422To444_SC3_COM_Main, *MST_422To444_SC3_Main, PQ_IP_422To444_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Y_SC3_COM_Main, *MST_HSP_Y_SC3_Main, PQ_IP_HSP_Y_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_C_SC3_COM_Main, *MST_HSP_C_SC3_Main, PQ_IP_HSP_C_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_CoRing_SC3_COM_Main, *MST_HSP_CoRing_SC3_Main, PQ_IP_HSP_CoRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_DeRing_SC3_COM_Main, *MST_HSP_DeRing_SC3_Main, PQ_IP_HSP_DeRing_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HSP_Dither_SC3_COM_Main, *MST_HSP_Dither_SC3_Main, PQ_IP_HSP_Dither_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_HnonLinear_SC3_COM_Main, *MST_HnonLinear_SC3_Main, PQ_IP_HnonLinear_SC3_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_WDR_Loc_TBL_0_SRAM_COM_Main, *MST_WDR_Loc_TBL_0_SRAM_Main, PQ_IP_WDR_Loc_TBL_0_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_0_SRAM}, ++{*MST_WDR_Loc_TBL_1_SRAM_COM_Main, *MST_WDR_Loc_TBL_1_SRAM_Main, PQ_IP_WDR_Loc_TBL_1_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_1_SRAM}, ++{*MST_WDR_Loc_TBL_2_SRAM_COM_Main, *MST_WDR_Loc_TBL_2_SRAM_Main, PQ_IP_WDR_Loc_TBL_2_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_2_SRAM}, ++{*MST_WDR_Loc_TBL_3_SRAM_COM_Main, *MST_WDR_Loc_TBL_3_SRAM_Main, PQ_IP_WDR_Loc_TBL_3_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_3_SRAM}, ++{*MST_WDR_Loc_TBL_4_SRAM_COM_Main, *MST_WDR_Loc_TBL_4_SRAM_Main, PQ_IP_WDR_Loc_TBL_4_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_4_SRAM}, ++{*MST_WDR_Loc_TBL_5_SRAM_COM_Main, *MST_WDR_Loc_TBL_5_SRAM_Main, PQ_IP_WDR_Loc_TBL_5_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_5_SRAM}, ++{*MST_WDR_Loc_TBL_6_SRAM_COM_Main, *MST_WDR_Loc_TBL_6_SRAM_Main, PQ_IP_WDR_Loc_TBL_6_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_6_SRAM}, ++{*MST_WDR_Loc_TBL_7_SRAM_COM_Main, *MST_WDR_Loc_TBL_7_SRAM_Main, PQ_IP_WDR_Loc_TBL_7_SRAM_NUMS_Main, PQ_TABTYPE_WDR_Loc_TBL_7_SRAM}, ++{*MST_YUV_Gamma_tblU_SRAM_COM_Main, *MST_YUV_Gamma_tblU_SRAM_Main, PQ_IP_YUV_Gamma_tblU_SRAM_NUMS_Main, PQ_TABTYPE_YUV_Gamma_tblU_SRAM}, ++{*MST_YUV_Gamma_tblV_SRAM_COM_Main, *MST_YUV_Gamma_tblV_SRAM_Main, PQ_IP_YUV_Gamma_tblV_SRAM_NUMS_Main, PQ_TABTYPE_YUV_Gamma_tblV_SRAM}, ++{*MST_YUV_Gamma_tblY_SRAM_COM_Main, *MST_YUV_Gamma_tblY_SRAM_Main, PQ_IP_YUV_Gamma_tblY_SRAM_NUMS_Main, PQ_TABTYPE_YUV_Gamma_tblY_SRAM}, ++{*MST_ColorEng_GM10to12_Tbl_R_SRAM_COM_Main, *MST_ColorEng_GM10to12_Tbl_R_SRAM_Main, PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_NUMS_Main, PQ_TABTYPE_ColorEng_GM10to12_Tbl_R_SRAM}, ++{*MST_ColorEng_GM10to12_Tbl_G_SRAM_COM_Main, *MST_ColorEng_GM10to12_Tbl_G_SRAM_Main, PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_NUMS_Main, PQ_TABTYPE_ColorEng_GM10to12_Tbl_G_SRAM}, ++{*MST_ColorEng_GM10to12_Tbl_B_SRAM_COM_Main, *MST_ColorEng_GM10to12_Tbl_B_SRAM_Main, PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_NUMS_Main, PQ_TABTYPE_ColorEng_GM10to12_Tbl_B_SRAM}, ++{*MST_ColorEng_GM12to10_CrcTbl_R_SRAM_COM_Main, *MST_ColorEng_GM12to10_CrcTbl_R_SRAM_Main, PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_NUMS_Main, PQ_TABTYPE_ColorEng_GM12to10_CrcTbl_R_SRAM}, ++{*MST_ColorEng_GM12to10_CrcTbl_G_SRAM_COM_Main, *MST_ColorEng_GM12to10_CrcTbl_G_SRAM_Main, PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_NUMS_Main, PQ_TABTYPE_ColorEng_GM12to10_CrcTbl_G_SRAM}, ++{*MST_ColorEng_GM12to10_CrcTbl_B_SRAM_COM_Main, *MST_ColorEng_GM12to10_CrcTbl_B_SRAM_Main, PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_NUMS_Main, PQ_TABTYPE_ColorEng_GM12to10_CrcTbl_B_SRAM}, ++{*MST_YEE_COM_Main, *MST_YEE_Main, PQ_IP_YEE_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_YEE_AC_LUT_COM_Main, *MST_YEE_AC_LUT_Main, PQ_IP_YEE_AC_LUT_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_WDR_Glob_COM_Main, *MST_WDR_Glob_Main, PQ_IP_WDR_Glob_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_WDR_Loc_COM_Main, *MST_WDR_Loc_Main, PQ_IP_WDR_Loc_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_MXNR_COM_Main, *MST_MXNR_Main, PQ_IP_MXNR_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_UV_ADJUST_COM_Main, *MST_UV_ADJUST_Main, PQ_IP_UV_ADJUST_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_XNR_COM_Main, *MST_XNR_Main, PQ_IP_XNR_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_YC10_UVM10_COM_Main, *MST_YC10_UVM10_Main, PQ_IP_YC10_UVM10_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_Color_Transfer_COM_Main, *MST_Color_Transfer_Main, PQ_IP_Color_Transfer_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_YUV_Gamma_COM_Main, *MST_YUV_Gamma_Main, PQ_IP_YUV_Gamma_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_422to444_COM_Main, *MST_ColorEng_422to444_Main, PQ_IP_ColorEng_422to444_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_YUVtoRGB_COM_Main, *MST_ColorEng_YUVtoRGB_Main, PQ_IP_ColorEng_YUVtoRGB_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_GM10to12_COM_Main, *MST_ColorEng_GM10to12_Main, PQ_IP_ColorEng_GM10to12_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_CCM_COM_Main, *MST_ColorEng_CCM_Main, PQ_IP_ColorEng_CCM_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_HSV_COM_Main, *MST_ColorEng_HSV_Main, PQ_IP_ColorEng_HSV_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_GM12to10_COM_Main, *MST_ColorEng_GM12to10_Main, PQ_IP_ColorEng_GM12to10_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_RGBtoYUV_COM_Main, *MST_ColorEng_RGBtoYUV_Main, PQ_IP_ColorEng_RGBtoYUV_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_ColorEng_444to422_COM_Main, *MST_ColorEng_444to422_Main, PQ_IP_ColorEng_444to422_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_SWDriver_COM_Main, *MST_SWDriver_Main, PQ_IP_SWDriver_NUMS_Main, PQ_TABTYPE_SCALER}, ++{*MST_SC_End_COM_Main, *MST_SC_End_Main, PQ_IP_SC_End_NUMS_Main, PQ_TABTYPE_SCALER}, ++}; ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main.h +new file mode 100644 +index 00000000..a7240883 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main.h +@@ -0,0 +1,1293 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (; MStar; Confidential; Information; ) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//**************************************************** ++// Quality Map CodeGen Version 4.0 ++// 1920 ++// Infinity3e ++// 10/28/2016 6:17:43 PM ++// 39630.43853 ++//**************************************************** ++ ++#ifndef _INFINITY3E_MAIN_H_ ++#define _INFINITY3E_MAIN_H_ ++ ++#define PQ_IP_NUM_Main 147 ++#define PQ_IP_VIP_IHC_CRD_SRAM_SIZE_Main 2178 ++#define PQ_IP_VIP_ICC_CRD_SRAM_SIZE_Main 2178 ++#define PQ_IP_SRAM1_SIZE_Main 320 ++#define PQ_IP_SRAM2_SIZE_Main 320 ++#define PQ_IP_SRAM3_SIZE_Main 640 ++#define PQ_IP_SRAM4_SIZE_Main 640 ++#define PQ_IP_C_SRAM1_SIZE_Main 320 ++#define PQ_IP_C_SRAM2_SIZE_Main 320 ++#define PQ_IP_C_SRAM3_SIZE_Main 320 ++#define PQ_IP_C_SRAM4_SIZE_Main 320 ++#define PQ_IP_WDR_Loc_TBL_0_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_1_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_2_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_3_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_4_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_5_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_6_SRAM_SIZE_Main 128 ++#define PQ_IP_WDR_Loc_TBL_7_SRAM_SIZE_Main 128 ++#define PQ_IP_YUV_Gamma_tblU_SRAM_SIZE_Main 256 ++#define PQ_IP_YUV_Gamma_tblV_SRAM_SIZE_Main 256 ++#define PQ_IP_YUV_Gamma_tblY_SRAM_SIZE_Main 512 ++#define PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_SIZE_Main 512 ++#define PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_SIZE_Main 512 ++#define PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_SIZE_Main 512 ++#define PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_SIZE_Main 512 ++#define PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_SIZE_Main 512 ++#define PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_SIZE_Main 512 ++ ++typedef enum ++{ ++ #if PQ_QM_ISP ++ QM_FHD_YUV422_Main, //0 ++ #endif ++ QM_INPUTTYPE_NUM_Main, // 1 ++} SC_QUALITY_MAP_INDEX_e_Main; ++ ++typedef enum ++{ ++PQ_IP_MCNR_Main, //0 ++PQ_IP_LDC_Main, //1 ++PQ_IP_LDC_422_444_422_Main, //2 ++PQ_IP_NLM_Main, //3 ++PQ_IP_422to444_Main, //4 ++PQ_IP_VIP_Main, //5 ++PQ_IP_VIP_pseudo_Main, //6 ++PQ_IP_VIP_LineBuffer_Main, //7 ++PQ_IP_VIP_HLPF_Main, //8 ++PQ_IP_VIP_HLPF_dither_Main, //9 ++PQ_IP_VIP_VLPF_coef1_Main, //10 ++PQ_IP_VIP_VLPF_coef2_Main, //11 ++PQ_IP_VIP_VLPF_dither_Main, //12 ++PQ_IP_VIP_Peaking_Main, //13 ++PQ_IP_VIP_Peaking_band_Main, //14 ++PQ_IP_VIP_Peaking_adptive_Main, //15 ++PQ_IP_VIP_Peaking_Pcoring_Main, //16 ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_Main, //17 ++PQ_IP_VIP_Peaking_gain_Main, //18 ++PQ_IP_VIP_Peaking_gain_ad_Y_Main, //19 ++PQ_IP_VIP_LCE_Main, //20 ++PQ_IP_VIP_LCE_dither_Main, //21 ++PQ_IP_VIP_LCE_setting_Main, //22 ++PQ_IP_VIP_LCE_curve_Main, //23 ++PQ_IP_VIP_DLC_His_range_Main, //24 ++PQ_IP_VIP_DLC_Main, //25 ++PQ_IP_VIP_DLC_dither_Main, //26 ++PQ_IP_VIP_DLC_His_rangeH_Main, //27 ++PQ_IP_VIP_DLC_His_rangeV_Main, //28 ++PQ_IP_VIP_DLC_PC_Main, //29 ++PQ_IP_VIP_YC_gain_offset_Main, //30 ++PQ_IP_VIP_UVC_Main, //31 ++PQ_IP_VIP_FCC_full_range_Main, //32 ++PQ_IP_VIP_FCC_bdry_dist_Main, //33 ++PQ_IP_VIP_FCC_T1_Main, //34 ++PQ_IP_VIP_FCC_T2_Main, //35 ++PQ_IP_VIP_FCC_T3_Main, //36 ++PQ_IP_VIP_FCC_T4_Main, //37 ++PQ_IP_VIP_FCC_T5_Main, //38 ++PQ_IP_VIP_FCC_T6_Main, //39 ++PQ_IP_VIP_FCC_T7_Main, //40 ++PQ_IP_VIP_FCC_T8_Main, //41 ++PQ_IP_VIP_FCC_T9_Main, //42 ++PQ_IP_VIP_IHC_Main, //43 ++PQ_IP_VIP_IHC_Ymode_Main, //44 ++PQ_IP_VIP_IHC_dither_Main, //45 ++PQ_IP_VIP_IHC_CRD_SRAM_Main, //46 ++PQ_IP_VIP_IHC_SETTING_Main, //47 ++PQ_IP_VIP_ICC_Main, //48 ++PQ_IP_VIP_ICC_Ymode_Main, //49 ++PQ_IP_VIP_ICC_dither_Main, //50 ++PQ_IP_VIP_ICC_CRD_SRAM_Main, //51 ++PQ_IP_VIP_ICC_SETTING_Main, //52 ++PQ_IP_VIP_Ymode_Yvalue_ALL_Main, //53 ++PQ_IP_VIP_Ymode_Yvalue_SETTING_Main, //54 ++PQ_IP_VIP_IBC_Main, //55 ++PQ_IP_VIP_IBC_dither_Main, //56 ++PQ_IP_VIP_IBC_SETTING_Main, //57 ++PQ_IP_VIP_ACK_Main, //58 ++PQ_IP_VIP_YCbCr_Clip_Main, //59 ++PQ_IP_VSP_Y_SC1_Main, //60 ++PQ_IP_VSP_C_SC1_Main, //61 ++PQ_IP_VSP_CoRing_SC1_Main, //62 ++PQ_IP_VSP_DeRing_SC1_Main, //63 ++PQ_IP_VSP_Dither_SC1_Main, //64 ++PQ_IP_VSP_PreVBound_SC1_Main, //65 ++PQ_IP_AntiPAL_filter_SC1_Main, //66 ++PQ_IP_422To444_SC1_Main, //67 ++PQ_IP_HSP_Y_SC1_Main, //68 ++PQ_IP_HSP_C_SC1_Main, //69 ++PQ_IP_HSP_CoRing_SC1_Main, //70 ++PQ_IP_HSP_DeRing_SC1_Main, //71 ++PQ_IP_HSP_Dither_SC1_Main, //72 ++PQ_IP_HnonLinear_SC1_Main, //73 ++PQ_IP_SRAM1_Main, //74 ++PQ_IP_SRAM2_Main, //75 ++PQ_IP_SRAM3_Main, //76 ++PQ_IP_SRAM4_Main, //77 ++PQ_IP_C_SRAM1_Main, //78 ++PQ_IP_C_SRAM2_Main, //79 ++PQ_IP_C_SRAM3_Main, //80 ++PQ_IP_C_SRAM4_Main, //81 ++PQ_IP_VSP_Y_SC2_Main, //82 ++PQ_IP_VSP_C_SC2_Main, //83 ++PQ_IP_VSP_CoRing_SC2_Main, //84 ++PQ_IP_VSP_DeRing_SC2_Main, //85 ++PQ_IP_VSP_Dither_SC2_Main, //86 ++PQ_IP_VSP_PreVBound_SC2_Main, //87 ++PQ_IP_AntiPAL_filter_SC2_Main, //88 ++PQ_IP_422To444_SC2_Main, //89 ++PQ_IP_HSP_Y_SC2_Main, //90 ++PQ_IP_HSP_C_SC2_Main, //91 ++PQ_IP_HSP_CoRing_SC2_Main, //92 ++PQ_IP_HSP_DeRing_SC2_Main, //93 ++PQ_IP_HSP_Dither_SC2_Main, //94 ++PQ_IP_HnonLinear_SC2_Main, //95 ++PQ_IP_VSP_Y_SC3_Main, //96 ++PQ_IP_VSP_C_SC3_Main, //97 ++PQ_IP_VSP_CoRing_SC3_Main, //98 ++PQ_IP_VSP_DeRing_SC3_Main, //99 ++PQ_IP_VSP_Dither_SC3_Main, //100 ++PQ_IP_VSP_PreVBound_SC3_Main, //101 ++PQ_IP_AntiPAL_filter_SC3_Main, //102 ++PQ_IP_422To444_SC3_Main, //103 ++PQ_IP_HSP_Y_SC3_Main, //104 ++PQ_IP_HSP_C_SC3_Main, //105 ++PQ_IP_HSP_CoRing_SC3_Main, //106 ++PQ_IP_HSP_DeRing_SC3_Main, //107 ++PQ_IP_HSP_Dither_SC3_Main, //108 ++PQ_IP_HnonLinear_SC3_Main, //109 ++PQ_IP_WDR_Loc_TBL_0_SRAM_Main, //110 ++PQ_IP_WDR_Loc_TBL_1_SRAM_Main, //111 ++PQ_IP_WDR_Loc_TBL_2_SRAM_Main, //112 ++PQ_IP_WDR_Loc_TBL_3_SRAM_Main, //113 ++PQ_IP_WDR_Loc_TBL_4_SRAM_Main, //114 ++PQ_IP_WDR_Loc_TBL_5_SRAM_Main, //115 ++PQ_IP_WDR_Loc_TBL_6_SRAM_Main, //116 ++PQ_IP_WDR_Loc_TBL_7_SRAM_Main, //117 ++PQ_IP_YUV_Gamma_tblY_SRAM_Main, //118 ++PQ_IP_YUV_Gamma_tblU_SRAM_Main, //119 ++PQ_IP_YUV_Gamma_tblV_SRAM_Main, //120 ++PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_Main, //121 ++PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_Main, //122 ++PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_Main, //123 ++PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_Main, //124 ++PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_Main, //125 ++PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_Main, //126 ++PQ_IP_YEE_Main, //127 ++PQ_IP_YEE_AC_LUT_Main, //128 ++PQ_IP_WDR_Glob_Main, //129 ++PQ_IP_WDR_Loc_Main, //130 ++PQ_IP_MXNR_Main, //131 ++PQ_IP_UV_ADJUST_Main, //132 ++PQ_IP_XNR_Main, //133 ++PQ_IP_YC10_UVM10_Main, //134 ++PQ_IP_Color_Transfer_Main, //135 ++PQ_IP_YUV_Gamma_Main, //136 ++PQ_IP_ColorEng_422to444_Main, //137 ++PQ_IP_ColorEng_YUVtoRGB_Main, //138 ++PQ_IP_ColorEng_GM10to12_Main, //139 ++PQ_IP_ColorEng_CCM_Main, //140 ++PQ_IP_ColorEng_HSV_Main, //141 ++PQ_IP_ColorEng_GM12to10_Main, //142 ++PQ_IP_ColorEng_RGBtoYUV_Main, //143 ++PQ_IP_ColorEng_444to422_Main, //144 ++PQ_IP_SWDriver_Main, //145 ++PQ_IP_SC_End_Main, //146 ++ } PQ_IPTYPE_Main; ++ ++typedef enum ++{ ++PQ_IP_MCNR_COM_Main, //0 ++PQ_IP_LDC_COM_Main, //1 ++PQ_IP_LDC_422_444_422_COM_Main, //2 ++PQ_IP_NLM_COM_Main, //3 ++PQ_IP_422to444_COM_Main, //4 ++PQ_IP_VIP_COM_Main, //5 ++PQ_IP_VIP_pseudo_COM_Main, //6 ++PQ_IP_VIP_LineBuffer_COM_Main, //7 ++PQ_IP_VIP_HLPF_COM_Main, //8 ++PQ_IP_VIP_HLPF_dither_COM_Main, //9 ++PQ_IP_VIP_VLPF_coef1_COM_Main, //10 ++PQ_IP_VIP_VLPF_coef2_COM_Main, //11 ++PQ_IP_VIP_VLPF_dither_COM_Main, //12 ++PQ_IP_VIP_Peaking_COM_Main, //13 ++PQ_IP_VIP_Peaking_band_COM_Main, //14 ++PQ_IP_VIP_Peaking_adptive_COM_Main, //15 ++PQ_IP_VIP_Peaking_Pcoring_COM_Main, //16 ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_COM_Main, //17 ++PQ_IP_VIP_Peaking_gain_COM_Main, //18 ++PQ_IP_VIP_Peaking_gain_ad_Y_COM_Main, //19 ++PQ_IP_VIP_LCE_COM_Main, //20 ++PQ_IP_VIP_LCE_dither_COM_Main, //21 ++PQ_IP_VIP_LCE_setting_COM_Main, //22 ++PQ_IP_VIP_LCE_curve_COM_Main, //23 ++PQ_IP_VIP_DLC_His_range_COM_Main, //24 ++PQ_IP_VIP_DLC_COM_Main, //25 ++PQ_IP_VIP_DLC_dither_COM_Main, //26 ++PQ_IP_VIP_DLC_His_rangeH_COM_Main, //27 ++PQ_IP_VIP_DLC_His_rangeV_COM_Main, //28 ++PQ_IP_VIP_DLC_PC_COM_Main, //29 ++PQ_IP_VIP_YC_gain_offset_COM_Main, //30 ++PQ_IP_VIP_UVC_COM_Main, //31 ++PQ_IP_VIP_FCC_full_range_COM_Main, //32 ++PQ_IP_VIP_FCC_bdry_dist_COM_Main, //33 ++PQ_IP_VIP_FCC_T1_COM_Main, //34 ++PQ_IP_VIP_FCC_T2_COM_Main, //35 ++PQ_IP_VIP_FCC_T3_COM_Main, //36 ++PQ_IP_VIP_FCC_T4_COM_Main, //37 ++PQ_IP_VIP_FCC_T5_COM_Main, //38 ++PQ_IP_VIP_FCC_T6_COM_Main, //39 ++PQ_IP_VIP_FCC_T7_COM_Main, //40 ++PQ_IP_VIP_FCC_T8_COM_Main, //41 ++PQ_IP_VIP_FCC_T9_COM_Main, //42 ++PQ_IP_VIP_IHC_COM_Main, //43 ++PQ_IP_VIP_IHC_Ymode_COM_Main, //44 ++PQ_IP_VIP_IHC_dither_COM_Main, //45 ++PQ_IP_VIP_IHC_CRD_SRAM_COM_Main, //46 ++PQ_IP_VIP_IHC_SETTING_COM_Main, //47 ++PQ_IP_VIP_ICC_COM_Main, //48 ++PQ_IP_VIP_ICC_Ymode_COM_Main, //49 ++PQ_IP_VIP_ICC_dither_COM_Main, //50 ++PQ_IP_VIP_ICC_CRD_SRAM_COM_Main, //51 ++PQ_IP_VIP_ICC_SETTING_COM_Main, //52 ++PQ_IP_VIP_Ymode_Yvalue_ALL_COM_Main, //53 ++PQ_IP_VIP_Ymode_Yvalue_SETTING_COM_Main, //54 ++PQ_IP_VIP_IBC_COM_Main, //55 ++PQ_IP_VIP_IBC_dither_COM_Main, //56 ++PQ_IP_VIP_IBC_SETTING_COM_Main, //57 ++PQ_IP_VIP_ACK_COM_Main, //58 ++PQ_IP_VIP_YCbCr_Clip_COM_Main, //59 ++PQ_IP_VSP_Y_SC1_COM_Main, //60 ++PQ_IP_VSP_C_SC1_COM_Main, //61 ++PQ_IP_VSP_CoRing_SC1_COM_Main, //62 ++PQ_IP_VSP_DeRing_SC1_COM_Main, //63 ++PQ_IP_VSP_Dither_SC1_COM_Main, //64 ++PQ_IP_VSP_PreVBound_SC1_COM_Main, //65 ++PQ_IP_AntiPAL_filter_SC1_COM_Main, //66 ++PQ_IP_422To444_SC1_COM_Main, //67 ++PQ_IP_HSP_Y_SC1_COM_Main, //68 ++PQ_IP_HSP_C_SC1_COM_Main, //69 ++PQ_IP_HSP_CoRing_SC1_COM_Main, //70 ++PQ_IP_HSP_DeRing_SC1_COM_Main, //71 ++PQ_IP_HSP_Dither_SC1_COM_Main, //72 ++PQ_IP_HnonLinear_SC1_COM_Main, //73 ++PQ_IP_SRAM1_COM_Main, //74 ++PQ_IP_SRAM2_COM_Main, //75 ++PQ_IP_SRAM3_COM_Main, //76 ++PQ_IP_SRAM4_COM_Main, //77 ++PQ_IP_C_SRAM1_COM_Main, //78 ++PQ_IP_C_SRAM2_COM_Main, //79 ++PQ_IP_C_SRAM3_COM_Main, //80 ++PQ_IP_C_SRAM4_COM_Main, //81 ++PQ_IP_VSP_Y_SC2_COM_Main, //82 ++PQ_IP_VSP_C_SC2_COM_Main, //83 ++PQ_IP_VSP_CoRing_SC2_COM_Main, //84 ++PQ_IP_VSP_DeRing_SC2_COM_Main, //85 ++PQ_IP_VSP_Dither_SC2_COM_Main, //86 ++PQ_IP_VSP_PreVBound_SC2_COM_Main, //87 ++PQ_IP_AntiPAL_filter_SC2_COM_Main, //88 ++PQ_IP_422To444_SC2_COM_Main, //89 ++PQ_IP_HSP_Y_SC2_COM_Main, //90 ++PQ_IP_HSP_C_SC2_COM_Main, //91 ++PQ_IP_HSP_CoRing_SC2_COM_Main, //92 ++PQ_IP_HSP_DeRing_SC2_COM_Main, //93 ++PQ_IP_HSP_Dither_SC2_COM_Main, //94 ++PQ_IP_HnonLinear_SC2_COM_Main, //95 ++PQ_IP_VSP_Y_SC3_COM_Main, //96 ++PQ_IP_VSP_C_SC3_COM_Main, //97 ++PQ_IP_VSP_CoRing_SC3_COM_Main, //98 ++PQ_IP_VSP_DeRing_SC3_COM_Main, //99 ++PQ_IP_VSP_Dither_SC3_COM_Main, //100 ++PQ_IP_VSP_PreVBound_SC3_COM_Main, //101 ++PQ_IP_AntiPAL_filter_SC3_COM_Main, //102 ++PQ_IP_422To444_SC3_COM_Main, //103 ++PQ_IP_HSP_Y_SC3_COM_Main, //104 ++PQ_IP_HSP_C_SC3_COM_Main, //105 ++PQ_IP_HSP_CoRing_SC3_COM_Main, //106 ++PQ_IP_HSP_DeRing_SC3_COM_Main, //107 ++PQ_IP_HSP_Dither_SC3_COM_Main, //108 ++PQ_IP_HnonLinear_SC3_COM_Main, //109 ++PQ_IP_WDR_Loc_TBL_0_SRAM_COM_Main, //110 ++PQ_IP_WDR_Loc_TBL_1_SRAM_COM_Main, //111 ++PQ_IP_WDR_Loc_TBL_2_SRAM_COM_Main, //112 ++PQ_IP_WDR_Loc_TBL_3_SRAM_COM_Main, //113 ++PQ_IP_WDR_Loc_TBL_4_SRAM_COM_Main, //114 ++PQ_IP_WDR_Loc_TBL_5_SRAM_COM_Main, //115 ++PQ_IP_WDR_Loc_TBL_6_SRAM_COM_Main, //116 ++PQ_IP_WDR_Loc_TBL_7_SRAM_COM_Main, //117 ++PQ_IP_YUV_Gamma_tblY_SRAM_COM_Main, //118 ++PQ_IP_YUV_Gamma_tblU_SRAM_COM_Main, //119 ++PQ_IP_YUV_Gamma_tblV_SRAM_COM_Main, //120 ++PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_COM_Main, //121 ++PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_COM_Main, //122 ++PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_COM_Main, //123 ++PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_COM_Main, //124 ++PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_COM_Main, //125 ++PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_COM_Main, //126 ++PQ_IP_YEE_COM_Main, //127 ++PQ_IP_YEE_AC_LUT_COM_Main, //128 ++PQ_IP_WDR_Glob_COM_Main, //129 ++PQ_IP_WDR_Loc_COM_Main, //130 ++PQ_IP_MXNR_COM_Main, //131 ++PQ_IP_UV_ADJUST_COM_Main, //132 ++PQ_IP_XNR_COM_Main, //133 ++PQ_IP_YC10_UVM10_COM_Main, //134 ++PQ_IP_Color_Transfer_COM_Main, //135 ++PQ_IP_YUV_Gamma_COM_Main, //136 ++PQ_IP_ColorEng_422to444_COM_Main, //137 ++PQ_IP_ColorEng_YUVtoRGB_COM_Main, //138 ++PQ_IP_ColorEng_GM10to12_COM_Main, //139 ++PQ_IP_ColorEng_CCM_COM_Main, //140 ++PQ_IP_ColorEng_HSV_COM_Main, //141 ++PQ_IP_ColorEng_GM12to10_COM_Main, //142 ++PQ_IP_ColorEng_RGBtoYUV_COM_Main, //143 ++PQ_IP_ColorEng_444to422_COM_Main, //144 ++PQ_IP_SWDriver_COM_Main, //145 ++PQ_IP_SC_End_COM_Main, //146 ++PQ_IP_COM_NUMS_Main ++} PQ_IP_COM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_MCNR_OFF_Main, ++PQ_IP_MCNR_NUMS_Main ++} PQ_IP_MCNR_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_LDC_OFF_Main, ++PQ_IP_LDC_ON_Main, ++PQ_IP_LDC_NUMS_Main ++} PQ_IP_LDC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_LDC_422_444_422_md1434_avg_Main, ++PQ_IP_LDC_422_444_422_NUMS_Main ++} PQ_IP_LDC_422_444_422_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_NLM_OFF_Main, ++PQ_IP_NLM_NUMS_Main ++} PQ_IP_NLM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422to444_OFF_Main, ++PQ_IP_422to444_NUMS_Main ++} PQ_IP_422to444_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_OFF_Main, ++PQ_IP_VIP_NUMS_Main ++} PQ_IP_VIP_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_pseudo_OFF_Main, ++PQ_IP_VIP_pseudo_NUMS_Main ++} PQ_IP_VIP_pseudo_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LineBuffer_OFF_Main, ++PQ_IP_VIP_LineBuffer_NUMS_Main ++} PQ_IP_VIP_LineBuffer_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_HLPF_OFF_Main, ++PQ_IP_VIP_HLPF_NUMS_Main ++} PQ_IP_VIP_HLPF_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_HLPF_dither_OFF_Main, ++PQ_IP_VIP_HLPF_dither_NUMS_Main ++} PQ_IP_VIP_HLPF_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_VLPF_coef1_OFF_Main, ++PQ_IP_VIP_VLPF_coef1_NUMS_Main ++} PQ_IP_VIP_VLPF_coef1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_VLPF_coef2_OFF_Main, ++PQ_IP_VIP_VLPF_coef2_NUMS_Main ++} PQ_IP_VIP_VLPF_coef2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_VLPF_dither_OFF_Main, ++PQ_IP_VIP_VLPF_dither_NUMS_Main ++} PQ_IP_VIP_VLPF_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_OFF_Main, ++PQ_IP_VIP_Peaking_W2_Main, ++PQ_IP_VIP_Peaking_NUMS_Main ++} PQ_IP_VIP_Peaking_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_band_OFF_Main, ++PQ_IP_VIP_Peaking_band_NUMS_Main ++} PQ_IP_VIP_Peaking_band_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_adptive_OFF_Main, ++PQ_IP_VIP_Peaking_adptive_NUMS_Main ++} PQ_IP_VIP_Peaking_adptive_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_Pcoring_OFF_Main, ++PQ_IP_VIP_Peaking_Pcoring_NUMS_Main ++} PQ_IP_VIP_Peaking_Pcoring_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_OFF_Main, ++PQ_IP_VIP_Peaking_Pcoring_ad_Y_NUMS_Main ++} PQ_IP_VIP_Peaking_Pcoring_ad_Y_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_gain_0x10_Main, ++PQ_IP_VIP_Peaking_gain_NUMS_Main ++} PQ_IP_VIP_Peaking_gain_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Peaking_gain_ad_Y_OFF_Main, ++PQ_IP_VIP_Peaking_gain_ad_Y_NUMS_Main ++} PQ_IP_VIP_Peaking_gain_ad_Y_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_OFF_Main, ++PQ_IP_VIP_LCE_NUMS_Main ++} PQ_IP_VIP_LCE_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_dither_OFF_Main, ++PQ_IP_VIP_LCE_dither_NUMS_Main ++} PQ_IP_VIP_LCE_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_setting_S3_Main, ++PQ_IP_VIP_LCE_setting_NUMS_Main ++} PQ_IP_VIP_LCE_setting_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_LCE_curve_CV1_Main, ++PQ_IP_VIP_LCE_curve_NUMS_Main ++} PQ_IP_VIP_LCE_curve_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_His_range_OFF_Main, ++PQ_IP_VIP_DLC_His_range_NUMS_Main ++} PQ_IP_VIP_DLC_His_range_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_OFF_Main, ++PQ_IP_VIP_DLC_NUMS_Main ++} PQ_IP_VIP_DLC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_dither_OFF_Main, ++PQ_IP_VIP_DLC_dither_NUMS_Main ++} PQ_IP_VIP_DLC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_His_rangeH_90pa_1920_Main, ++PQ_IP_VIP_DLC_His_rangeH_NUMS_Main ++} PQ_IP_VIP_DLC_His_rangeH_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_His_rangeV_90pa_1920_Main, ++PQ_IP_VIP_DLC_His_rangeV_NUMS_Main ++} PQ_IP_VIP_DLC_His_rangeV_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_DLC_PC_OFF_Main, ++PQ_IP_VIP_DLC_PC_NUMS_Main ++} PQ_IP_VIP_DLC_PC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_YC_gain_offset_OFF_Main, ++PQ_IP_VIP_YC_gain_offset_NUMS_Main ++} PQ_IP_VIP_YC_gain_offset_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_UVC_OFF_Main, ++PQ_IP_VIP_UVC_NUMS_Main ++} PQ_IP_VIP_UVC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_full_range_OFF_Main, ++PQ_IP_VIP_FCC_full_range_NUMS_Main ++} PQ_IP_VIP_FCC_full_range_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_bdry_dist_OFF_Main, ++PQ_IP_VIP_FCC_bdry_dist_NUMS_Main ++} PQ_IP_VIP_FCC_bdry_dist_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T1_OFF_Main, ++PQ_IP_VIP_FCC_T1_NUMS_Main ++} PQ_IP_VIP_FCC_T1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T2_OFF_Main, ++PQ_IP_VIP_FCC_T2_NUMS_Main ++} PQ_IP_VIP_FCC_T2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T3_OFF_Main, ++PQ_IP_VIP_FCC_T3_NUMS_Main ++} PQ_IP_VIP_FCC_T3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T4_OFF_Main, ++PQ_IP_VIP_FCC_T4_NUMS_Main ++} PQ_IP_VIP_FCC_T4_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T5_OFF_Main, ++PQ_IP_VIP_FCC_T5_NUMS_Main ++} PQ_IP_VIP_FCC_T5_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T6_OFF_Main, ++PQ_IP_VIP_FCC_T6_NUMS_Main ++} PQ_IP_VIP_FCC_T6_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T7_OFF_Main, ++PQ_IP_VIP_FCC_T7_NUMS_Main ++} PQ_IP_VIP_FCC_T7_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T8_OFF_Main, ++PQ_IP_VIP_FCC_T8_NUMS_Main ++} PQ_IP_VIP_FCC_T8_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_FCC_T9_OFF_Main, ++PQ_IP_VIP_FCC_T9_NUMS_Main ++} PQ_IP_VIP_FCC_T9_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_OFF_Main, ++PQ_IP_VIP_IHC_NUMS_Main ++} PQ_IP_VIP_IHC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_Ymode_OFF_Main, ++PQ_IP_VIP_IHC_Ymode_NUMS_Main ++} PQ_IP_VIP_IHC_Ymode_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_dither_OFF_Main, ++PQ_IP_VIP_IHC_dither_NUMS_Main ++} PQ_IP_VIP_IHC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_CRD_SRAM_15wins3_Main, ++PQ_IP_VIP_IHC_CRD_SRAM_NUMS_Main ++} PQ_IP_VIP_IHC_CRD_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IHC_SETTING_HDMI_HD_Main, ++PQ_IP_VIP_IHC_SETTING_NUMS_Main ++} PQ_IP_VIP_IHC_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_OFF_Main, ++PQ_IP_VIP_ICC_NUMS_Main ++} PQ_IP_VIP_ICC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_Ymode_HDMI_HD_Main, ++PQ_IP_VIP_ICC_Ymode_NUMS_Main ++} PQ_IP_VIP_ICC_Ymode_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_dither_OFF_Main, ++PQ_IP_VIP_ICC_dither_NUMS_Main ++} PQ_IP_VIP_ICC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_CRD_SRAM_15wins3_Main, ++PQ_IP_VIP_ICC_CRD_SRAM_NUMS_Main ++} PQ_IP_VIP_ICC_CRD_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ICC_SETTING_HDMI_HD_Main, ++PQ_IP_VIP_ICC_SETTING_NUMS_Main ++} PQ_IP_VIP_ICC_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Ymode_Yvalue_ALL_Y1_Main, ++PQ_IP_VIP_Ymode_Yvalue_ALL_NUMS_Main ++} PQ_IP_VIP_Ymode_Yvalue_ALL_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_Ymode_Yvalue_SETTING_Y2_Main, ++PQ_IP_VIP_Ymode_Yvalue_SETTING_NUMS_Main ++} PQ_IP_VIP_Ymode_Yvalue_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IBC_OFF_Main, ++PQ_IP_VIP_IBC_NUMS_Main ++} PQ_IP_VIP_IBC_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IBC_dither_OFF_Main, ++PQ_IP_VIP_IBC_dither_NUMS_Main ++} PQ_IP_VIP_IBC_dither_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_IBC_SETTING_OFF_Main, ++PQ_IP_VIP_IBC_SETTING_NUMS_Main ++} PQ_IP_VIP_IBC_SETTING_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_ACK_OFF_Main, ++PQ_IP_VIP_ACK_NUMS_Main ++} PQ_IP_VIP_ACK_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VIP_YCbCr_Clip_OFF_Main, ++PQ_IP_VIP_YCbCr_Clip_NUMS_Main ++} PQ_IP_VIP_YCbCr_Clip_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Y_SC1_Bypass_Main, ++PQ_IP_VSP_Y_SC1_NUMS_Main ++} PQ_IP_VSP_Y_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_C_SC1_Bypass_Main, ++PQ_IP_VSP_C_SC1_NUMS_Main ++} PQ_IP_VSP_C_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_CoRing_SC1_OFF_Main, ++PQ_IP_VSP_CoRing_SC1_NUMS_Main ++} PQ_IP_VSP_CoRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_DeRing_SC1_OFF_Main, ++PQ_IP_VSP_DeRing_SC1_NUMS_Main ++} PQ_IP_VSP_DeRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Dither_SC1_OFF_Main, ++PQ_IP_VSP_Dither_SC1_NUMS_Main ++} PQ_IP_VSP_Dither_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_PreVBound_SC1_OFF_Main, ++PQ_IP_VSP_PreVBound_SC1_NUMS_Main ++} PQ_IP_VSP_PreVBound_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_AntiPAL_filter_SC1_OFF_Main, ++PQ_IP_AntiPAL_filter_SC1_NUMS_Main ++} PQ_IP_AntiPAL_filter_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422To444_SC1_ON_Main, ++PQ_IP_422To444_SC1_NUMS_Main ++} PQ_IP_422To444_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Y_SC1_Bypass_Main, ++PQ_IP_HSP_Y_SC1_NUMS_Main ++} PQ_IP_HSP_Y_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_C_SC1_Bypass_Main, ++PQ_IP_HSP_C_SC1_NUMS_Main ++} PQ_IP_HSP_C_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_CoRing_SC1_OFF_Main, ++PQ_IP_HSP_CoRing_SC1_NUMS_Main ++} PQ_IP_HSP_CoRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_DeRing_SC1_OFF_Main, ++PQ_IP_HSP_DeRing_SC1_NUMS_Main ++} PQ_IP_HSP_DeRing_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Dither_SC1_OFF_Main, ++PQ_IP_HSP_Dither_SC1_NUMS_Main ++} PQ_IP_HSP_Dither_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HnonLinear_SC1_OFF_Main, ++PQ_IP_HnonLinear_SC1_NUMS_Main ++} PQ_IP_HnonLinear_SC1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM1_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G11_Main, ++PQ_IP_SRAM1_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G12_Main, ++PQ_IP_SRAM1_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G13_Main, ++PQ_IP_SRAM1_InvSinc4Tc4p4Fc65Apass3Astop60G14_Main, ++PQ_IP_SRAM1_NUMS_Main ++} PQ_IP_SRAM1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM2_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50_Main, ++PQ_IP_SRAM2_InvSinc4Tc4p4Fc75Fstop124Apass0001Astop40_Main, ++PQ_IP_SRAM2_InvSinc4Tc4p4Fc50Apass01Astop55_Main, ++PQ_IP_SRAM2_InvSinc4Tc4p4Fc45Apass01Astop40_Main, ++PQ_IP_SRAM2_NUMS_Main ++} PQ_IP_SRAM2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM3_OFF_Main, ++PQ_IP_SRAM3_NUMS_Main ++} PQ_IP_SRAM3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SRAM4_OFF_Main, ++PQ_IP_SRAM4_NUMS_Main ++} PQ_IP_SRAM4_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM1_C121_Main, ++PQ_IP_C_SRAM1_NUMS_Main ++} PQ_IP_C_SRAM1_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM2_C2121_Main, ++PQ_IP_C_SRAM2_NUMS_Main ++} PQ_IP_C_SRAM2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM3_C161_Main, ++PQ_IP_C_SRAM3_NUMS_Main ++} PQ_IP_C_SRAM3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_C_SRAM4_C2121_Main, ++PQ_IP_C_SRAM4_NUMS_Main ++} PQ_IP_C_SRAM4_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Y_SC2_Bypass_Main, ++PQ_IP_VSP_Y_SC2_NUMS_Main ++} PQ_IP_VSP_Y_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_C_SC2_Bypass_Main, ++PQ_IP_VSP_C_SC2_NUMS_Main ++} PQ_IP_VSP_C_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_CoRing_SC2_OFF_Main, ++PQ_IP_VSP_CoRing_SC2_NUMS_Main ++} PQ_IP_VSP_CoRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_DeRing_SC2_OFF_Main, ++PQ_IP_VSP_DeRing_SC2_NUMS_Main ++} PQ_IP_VSP_DeRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Dither_SC2_OFF_Main, ++PQ_IP_VSP_Dither_SC2_NUMS_Main ++} PQ_IP_VSP_Dither_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_PreVBound_SC2_OFF_Main, ++PQ_IP_VSP_PreVBound_SC2_NUMS_Main ++} PQ_IP_VSP_PreVBound_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_AntiPAL_filter_SC2_OFF_Main, ++PQ_IP_AntiPAL_filter_SC2_NUMS_Main ++} PQ_IP_AntiPAL_filter_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422To444_SC2_ON_Main, ++PQ_IP_422To444_SC2_NUMS_Main ++} PQ_IP_422To444_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Y_SC2_Bypass_Main, ++PQ_IP_HSP_Y_SC2_NUMS_Main ++} PQ_IP_HSP_Y_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_C_SC2_Bypass_Main, ++PQ_IP_HSP_C_SC2_Bilinear_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_1_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_2_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_3_Main, ++PQ_IP_HSP_C_SC2_C_SRAM_4_Main, ++PQ_IP_HSP_C_SC2_SRAM_1_4Tap_Main, ++PQ_IP_HSP_C_SC2_SRAM_2_4Tap_Main, ++PQ_IP_HSP_C_SC2_NUMS_Main ++} PQ_IP_HSP_C_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_CoRing_SC2_OFF_Main, ++PQ_IP_HSP_CoRing_SC2_NUMS_Main ++} PQ_IP_HSP_CoRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_DeRing_SC2_OFF_Main, ++PQ_IP_HSP_DeRing_SC2_NUMS_Main ++} PQ_IP_HSP_DeRing_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Dither_SC2_OFF_Main, ++PQ_IP_HSP_Dither_SC2_NUMS_Main ++} PQ_IP_HSP_Dither_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HnonLinear_SC2_OFF_Main, ++PQ_IP_HnonLinear_SC2_NUMS_Main ++} PQ_IP_HnonLinear_SC2_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Y_SC3_Bypass_Main, ++PQ_IP_VSP_Y_SC3_NUMS_Main ++} PQ_IP_VSP_Y_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_C_SC3_Bypass_Main, ++PQ_IP_VSP_C_SC3_NUMS_Main ++} PQ_IP_VSP_C_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_CoRing_SC3_OFF_Main, ++PQ_IP_VSP_CoRing_SC3_NUMS_Main ++} PQ_IP_VSP_CoRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_DeRing_SC3_OFF_Main, ++PQ_IP_VSP_DeRing_SC3_NUMS_Main ++} PQ_IP_VSP_DeRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_Dither_SC3_OFF_Main, ++PQ_IP_VSP_Dither_SC3_NUMS_Main ++} PQ_IP_VSP_Dither_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_VSP_PreVBound_SC3_OFF_Main, ++PQ_IP_VSP_PreVBound_SC3_NUMS_Main ++} PQ_IP_VSP_PreVBound_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_AntiPAL_filter_SC3_OFF_Main, ++PQ_IP_AntiPAL_filter_SC3_NUMS_Main ++} PQ_IP_AntiPAL_filter_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_422To444_SC3_ON_Main, ++PQ_IP_422To444_SC3_NUMS_Main ++} PQ_IP_422To444_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Y_SC3_Bypass_Main, ++PQ_IP_HSP_Y_SC3_NUMS_Main ++} PQ_IP_HSP_Y_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_C_SC3_Bypass_Main, ++PQ_IP_HSP_C_SC3_NUMS_Main ++} PQ_IP_HSP_C_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_CoRing_SC3_OFF_Main, ++PQ_IP_HSP_CoRing_SC3_NUMS_Main ++} PQ_IP_HSP_CoRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_DeRing_SC3_OFF_Main, ++PQ_IP_HSP_DeRing_SC3_NUMS_Main ++} PQ_IP_HSP_DeRing_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HSP_Dither_SC3_OFF_Main, ++PQ_IP_HSP_Dither_SC3_NUMS_Main ++} PQ_IP_HSP_Dither_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_HnonLinear_SC3_OFF_Main, ++PQ_IP_HnonLinear_SC3_NUMS_Main ++} PQ_IP_HnonLinear_SC3_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_0_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_0_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_0_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_1_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_1_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_1_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_2_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_2_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_2_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_3_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_3_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_3_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_4_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_4_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_4_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_5_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_5_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_5_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_6_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_6_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_6_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_TBL_7_SRAM_OFF_Main, ++PQ_IP_WDR_Loc_TBL_7_SRAM_NUMS_Main ++} PQ_IP_WDR_Loc_TBL_7_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YUV_Gamma_tblU_SRAM_OFF_Main, ++PQ_IP_YUV_Gamma_tblU_SRAM_NUMS_Main ++} PQ_IP_YUV_Gamma_tblU_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YUV_Gamma_tblV_SRAM_OFF_Main, ++PQ_IP_YUV_Gamma_tblV_SRAM_NUMS_Main ++} PQ_IP_YUV_Gamma_tblV_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YUV_Gamma_tblY_SRAM_OFF_Main, ++PQ_IP_YUV_Gamma_tblY_SRAM_NUMS_Main ++} PQ_IP_YUV_Gamma_tblY_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_OFF_Main, ++PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_NUMS_Main ++} PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_OFF_Main, ++PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_NUMS_Main ++} PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_OFF_Main, ++PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_NUMS_Main ++} PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_OFF_Main, ++PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_NUMS_Main ++} PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_OFF_Main, ++PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_NUMS_Main ++} PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_OFF_Main, ++PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_NUMS_Main ++} PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YEE_OFF_Main, ++PQ_IP_YEE_NUMS_Main ++} PQ_IP_YEE_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YEE_AC_LUT_OFF_Main, ++PQ_IP_YEE_AC_LUT_NUMS_Main ++} PQ_IP_YEE_AC_LUT_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Glob_OFF_Main, ++PQ_IP_WDR_Glob_NUMS_Main ++} PQ_IP_WDR_Glob_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_WDR_Loc_OFF_Main, ++PQ_IP_WDR_Loc_NUMS_Main ++} PQ_IP_WDR_Loc_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_MXNR_OFF_Main, ++PQ_IP_MXNR_NUMS_Main ++} PQ_IP_MXNR_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_UV_ADJUST_OFF_Main, ++PQ_IP_UV_ADJUST_NUMS_Main ++} PQ_IP_UV_ADJUST_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_XNR_OFF_Main, ++PQ_IP_XNR_NUMS_Main ++} PQ_IP_XNR_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YC10_UVM10_OFF_Main, ++PQ_IP_YC10_UVM10_NUMS_Main ++} PQ_IP_YC10_UVM10_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_Color_Transfer_OFF_Main, ++PQ_IP_Color_Transfer_NUMS_Main ++} PQ_IP_Color_Transfer_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_YUV_Gamma_OFF_Main, ++PQ_IP_YUV_Gamma_NUMS_Main ++} PQ_IP_YUV_Gamma_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_422to444_OFF_Main, ++PQ_IP_ColorEng_422to444_NUMS_Main ++} PQ_IP_ColorEng_422to444_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_YUVtoRGB_OFF_Main, ++PQ_IP_ColorEng_YUVtoRGB_NUMS_Main ++} PQ_IP_ColorEng_YUVtoRGB_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM10to12_OFF_Main, ++PQ_IP_ColorEng_GM10to12_NUMS_Main ++} PQ_IP_ColorEng_GM10to12_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_CCM_OFF_Main, ++PQ_IP_ColorEng_CCM_NUMS_Main ++} PQ_IP_ColorEng_CCM_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_HSV_OFF_Main, ++PQ_IP_ColorEng_HSV_NUMS_Main ++} PQ_IP_ColorEng_HSV_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_GM12to10_OFF_Main, ++PQ_IP_ColorEng_GM12to10_NUMS_Main ++} PQ_IP_ColorEng_GM12to10_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_RGBtoYUV_OFF_Main, ++PQ_IP_ColorEng_RGBtoYUV_NUMS_Main ++} PQ_IP_ColorEng_RGBtoYUV_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_ColorEng_444to422_OFF_Main, ++PQ_IP_ColorEng_444to422_NUMS_Main ++} PQ_IP_ColorEng_444to422_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SWDriver_OFF_Main, ++PQ_IP_SWDriver_ON_Main, ++PQ_IP_SWDriver_SD_FRC_Main, ++PQ_IP_SWDriver_NUMS_Main ++} PQ_IP_SWDriver_Group_Main; ++ ++typedef enum ++{ ++PQ_IP_SC_End_End_Main, ++PQ_IP_SC_End_NUMS_Main ++} PQ_IP_SC_End_Group_Main; ++ ++extern unsigned char MST_SkipRule_IP_Main[PQ_IP_NUM_Main]; ++extern EN_IPTAB_INFO PQ_IPTAB_INFO_Main[]; ++extern unsigned char MST_VIP_IHC_CRD_SRAM_Main[][PQ_IP_VIP_IHC_CRD_SRAM_SIZE_Main]; ++extern unsigned char MST_VIP_ICC_CRD_SRAM_Main[][PQ_IP_VIP_ICC_CRD_SRAM_SIZE_Main]; ++extern unsigned char MST_SRAM1_Main[][PQ_IP_SRAM1_SIZE_Main]; ++extern unsigned char MST_C_SRAM1_Main[][PQ_IP_C_SRAM1_SIZE_Main]; ++extern unsigned char MST_SRAM2_Main[][PQ_IP_SRAM2_SIZE_Main]; ++extern unsigned char MST_C_SRAM2_Main[][PQ_IP_C_SRAM2_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_0_SRAM_Main[][PQ_IP_WDR_Loc_TBL_0_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_1_SRAM_Main[][PQ_IP_WDR_Loc_TBL_1_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_2_SRAM_Main[][PQ_IP_WDR_Loc_TBL_2_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_3_SRAM_Main[][PQ_IP_WDR_Loc_TBL_3_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_4_SRAM_Main[][PQ_IP_WDR_Loc_TBL_4_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_5_SRAM_Main[][PQ_IP_WDR_Loc_TBL_5_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_6_SRAM_Main[][PQ_IP_WDR_Loc_TBL_6_SRAM_SIZE_Main]; ++extern unsigned char MST_WDR_Loc_TBL_7_SRAM_Main[][PQ_IP_WDR_Loc_TBL_7_SRAM_SIZE_Main]; ++extern unsigned char MST_YUV_Gamma_tblY_SRAM_Main[][PQ_IP_YUV_Gamma_tblY_SRAM_SIZE_Main]; ++extern unsigned char MST_YUV_Gamma_tblU_SRAM_Main[][PQ_IP_YUV_Gamma_tblU_SRAM_SIZE_Main]; ++extern unsigned char MST_YUV_Gamma_tblV_SRAM_Main[][PQ_IP_YUV_Gamma_tblV_SRAM_SIZE_Main]; ++extern unsigned char MST_ColorEng_GM10to12_Tbl_R_SRAM_Main[][PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_SIZE_Main]; ++extern unsigned char MST_ColorEng_GM10to12_Tbl_G_SRAM_Main[][PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_SIZE_Main]; ++extern unsigned char MST_ColorEng_GM10to12_Tbl_B_SRAM_Main[][PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_SIZE_Main]; ++extern unsigned char MST_ColorEng_GM12to10_CrcTbl_R_SRAM_Main[][PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_SIZE_Main]; ++extern unsigned char MST_ColorEng_GM12to10_CrcTbl_G_SRAM_Main[][PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_SIZE_Main]; ++extern unsigned char MST_ColorEng_GM12to10_CrcTbl_B_SRAM_Main[][PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_SIZE_Main]; ++extern unsigned char QMAP_1920_Main[QM_INPUTTYPE_NUM_Main][PQ_IP_NUM_Main]; ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_1920.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_1920.c +new file mode 100644 +index 00000000..37ad7d06 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_1920.c +@@ -0,0 +1,38 @@ ++ ++ unsigned char QMAP_1920_Main[QM_INPUTTYPE_NUM_Main][PQ_IP_NUM_Main]= ++{ ++ #if PQ_QM_ISP ++ {//1920 FHD_YUV422, 0 ++ PQ_IP_MCNR_OFF_Main, PQ_IP_LDC_OFF_Main, PQ_IP_LDC_422_444_422_md1434_avg_Main, PQ_IP_NLM_OFF_Main, PQ_IP_422to444_OFF_Main, ++ PQ_IP_VIP_OFF_Main, PQ_IP_VIP_pseudo_OFF_Main, PQ_IP_VIP_LineBuffer_OFF_Main, PQ_IP_VIP_HLPF_OFF_Main, PQ_IP_VIP_HLPF_dither_OFF_Main, ++ PQ_IP_VIP_VLPF_coef1_OFF_Main, PQ_IP_VIP_VLPF_coef2_OFF_Main, PQ_IP_VIP_VLPF_dither_OFF_Main, PQ_IP_VIP_Peaking_W2_Main, PQ_IP_VIP_Peaking_band_OFF_Main, ++ PQ_IP_VIP_Peaking_adptive_OFF_Main, PQ_IP_VIP_Peaking_Pcoring_OFF_Main, PQ_IP_VIP_Peaking_Pcoring_ad_Y_OFF_Main, PQ_IP_VIP_Peaking_gain_0x10_Main, PQ_IP_VIP_Peaking_gain_ad_Y_OFF_Main, ++ PQ_IP_VIP_LCE_OFF_Main, PQ_IP_VIP_LCE_dither_OFF_Main, PQ_IP_VIP_LCE_setting_S3_Main, PQ_IP_VIP_LCE_curve_CV1_Main, PQ_IP_VIP_DLC_His_range_OFF_Main, ++ PQ_IP_VIP_DLC_OFF_Main, PQ_IP_VIP_DLC_dither_OFF_Main, PQ_IP_VIP_DLC_His_rangeH_90pa_1920_Main, PQ_IP_VIP_DLC_His_rangeV_90pa_1920_Main, PQ_IP_VIP_DLC_PC_OFF_Main, ++ PQ_IP_VIP_YC_gain_offset_OFF_Main, PQ_IP_VIP_UVC_OFF_Main, PQ_IP_VIP_FCC_full_range_OFF_Main, PQ_IP_VIP_FCC_bdry_dist_OFF_Main, PQ_IP_VIP_FCC_T1_OFF_Main, ++ PQ_IP_VIP_FCC_T2_OFF_Main, PQ_IP_VIP_FCC_T3_OFF_Main, PQ_IP_VIP_FCC_T4_OFF_Main, PQ_IP_VIP_FCC_T5_OFF_Main, PQ_IP_VIP_FCC_T6_OFF_Main, ++ PQ_IP_VIP_FCC_T7_OFF_Main, PQ_IP_VIP_FCC_T8_OFF_Main, PQ_IP_VIP_FCC_T9_OFF_Main, PQ_IP_VIP_IHC_OFF_Main, PQ_IP_VIP_IHC_Ymode_OFF_Main, ++ PQ_IP_VIP_IHC_dither_OFF_Main, PQ_IP_VIP_IHC_CRD_SRAM_15wins3_Main, PQ_IP_VIP_IHC_SETTING_HDMI_HD_Main, PQ_IP_VIP_ICC_OFF_Main, PQ_IP_VIP_ICC_Ymode_HDMI_HD_Main, ++ PQ_IP_VIP_ICC_dither_OFF_Main, PQ_IP_VIP_ICC_CRD_SRAM_15wins3_Main, PQ_IP_VIP_ICC_SETTING_HDMI_HD_Main, PQ_IP_VIP_Ymode_Yvalue_ALL_Y1_Main, PQ_IP_VIP_Ymode_Yvalue_SETTING_Y2_Main, ++ PQ_IP_VIP_IBC_OFF_Main, PQ_IP_VIP_IBC_dither_OFF_Main, PQ_IP_VIP_IBC_SETTING_OFF_Main, PQ_IP_VIP_ACK_OFF_Main, PQ_IP_VIP_YCbCr_Clip_OFF_Main, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_SRAM1_InvSinc4Tc4p4Fc85Fstop134Apass01Astop50G13_Main, ++ PQ_IP_SRAM2_InvSinc4Tc4p4Fc45Apass01Astop40_Main, PQ_IP_SRAM3_OFF_Main, PQ_IP_SRAM4_OFF_Main, PQ_IP_C_SRAM1_C121_Main, PQ_IP_C_SRAM2_C2121_Main, ++ PQ_IP_C_SRAM3_C161_Main, PQ_IP_C_SRAM4_C2121_Main, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ PQ_IP_WDR_Loc_TBL_0_SRAM_OFF_Main, PQ_IP_WDR_Loc_TBL_1_SRAM_OFF_Main, PQ_IP_WDR_Loc_TBL_2_SRAM_OFF_Main, PQ_IP_WDR_Loc_TBL_3_SRAM_OFF_Main, PQ_IP_WDR_Loc_TBL_4_SRAM_OFF_Main, ++ PQ_IP_WDR_Loc_TBL_5_SRAM_OFF_Main, PQ_IP_WDR_Loc_TBL_6_SRAM_OFF_Main, PQ_IP_WDR_Loc_TBL_7_SRAM_OFF_Main, PQ_IP_YUV_Gamma_tblY_SRAM_OFF_Main, PQ_IP_YUV_Gamma_tblU_SRAM_OFF_Main, ++ PQ_IP_YUV_Gamma_tblV_SRAM_OFF_Main, PQ_IP_ColorEng_GM10to12_Tbl_R_SRAM_OFF_Main, PQ_IP_ColorEng_GM10to12_Tbl_G_SRAM_OFF_Main, PQ_IP_ColorEng_GM10to12_Tbl_B_SRAM_OFF_Main, PQ_IP_ColorEng_GM12to10_CrcTbl_R_SRAM_OFF_Main, ++ PQ_IP_ColorEng_GM12to10_CrcTbl_G_SRAM_OFF_Main, PQ_IP_ColorEng_GM12to10_CrcTbl_B_SRAM_OFF_Main, PQ_IP_YEE_OFF_Main, PQ_IP_YEE_AC_LUT_OFF_Main, PQ_IP_WDR_Glob_OFF_Main, ++ PQ_IP_WDR_Loc_OFF_Main, PQ_IP_MXNR_OFF_Main, PQ_IP_UV_ADJUST_OFF_Main, PQ_IP_XNR_OFF_Main, PQ_IP_YC10_UVM10_OFF_Main, ++ PQ_IP_Color_Transfer_OFF_Main, PQ_IP_YUV_Gamma_OFF_Main, PQ_IP_ColorEng_422to444_OFF_Main, PQ_IP_ColorEng_YUVtoRGB_OFF_Main, PQ_IP_ColorEng_GM10to12_OFF_Main, ++ PQ_IP_ColorEng_CCM_OFF_Main, PQ_IP_ColorEng_HSV_OFF_Main, PQ_IP_ColorEng_GM12to10_OFF_Main, PQ_IP_ColorEng_RGBtoYUV_OFF_Main, PQ_IP_ColorEng_444to422_OFF_Main, ++ PQ_IP_SWDriver_ON_Main, PQ_IP_SC_End_End_Main, ++ }, ++ #endif ++}; +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_1920_GRule.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_1920_GRule.c +new file mode 100644 +index 00000000..e7fcd0cc +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_1920_GRule.c +@@ -0,0 +1,8 @@ ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ unsigned char MST_GRule_1920_DYNAMIC_CONTRAST_Main[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_Main]= ++{ ++ PQ_GRule_DYNAMIC_CONTRAST_Off_Main, ++ PQ_GRule_DYNAMIC_CONTRAST_On_Main, ++}; ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_GRule.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_GRule.c +new file mode 100644 +index 00000000..6e035057 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_GRule.c +@@ -0,0 +1,24 @@ ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ unsigned char MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main[PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]= ++{ ++ PQ_IP_VIP_DLC_Main, ++}; ++#endif ++ ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ unsigned char MST_GRule_DYNAMIC_CONTRAST_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]= ++{ ++ #if PQ_QM_ISP ++ {//FHD_YUV422, 0 ++ {//Off ++ PQ_IP_VIP_DLC_OFF_Main, ++ }, ++ {//On ++ PQ_IP_VIP_DLC_OFF_Main, ++ }, ++ }, ++ #endif ++}; ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_GRule.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_GRule.h +new file mode 100644 +index 00000000..b5795054 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_GRule.h +@@ -0,0 +1,48 @@ ++#define PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE 1 ++#define PQ_GRULE_DEFINE_AUTO_GEN 1 ++#if (PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE) ++typedef enum ++{ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++ PQ_GRule_DYNAMIC_CONTRAST_Main, ++#endif ++ ++} ++MST_GRule_Index_Main; ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++typedef enum ++{ ++ PQ_GRule_DYNAMIC_CONTRAST_Off_Main, ++ PQ_GRule_DYNAMIC_CONTRAST_On_Main, ++} ++MST_GRule_DYNAMIC_CONTRAST_Index_Main; ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++typedef enum ++{ ++ PQ_GRule_Lvl_DYNAMIC_CONTRAST_Off_Main, ++ PQ_GRule_Lvl_DYNAMIC_CONTRAST_On_Main, ++} ++MST_GRule_DYNAMIC_CONTRAST_LvL_Index_Main; ++#endif ++ ++ ++#define PQ_GRULE_RULE_NUM_Main 1 ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++#define PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main 1 ++#define PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main 2 ++#define PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_Main 2 ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++extern unsigned char MST_GRule_DYNAMIC_CONTRAST_IP_Index_Main[PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]; ++extern unsigned char MST_GRule_DYNAMIC_CONTRAST_Main[QM_INPUTTYPE_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_NUM_Main][PQ_GRULE_DYNAMIC_CONTRAST_IP_NUM_Main]; ++#endif ++ ++#if PQ_GRULE_UFSC_DYNAMIC_CONTRAST_ENABLE ++extern unsigned char MST_GRule_1920_DYNAMIC_CONTRAST_Main[PQ_GRULE_DYNAMIC_CONTRAST_LVL_NUM_Main]; ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_HSPRule.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_HSPRule.c +new file mode 100644 +index 00000000..5b99a066 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_HSPRule.c +@@ -0,0 +1,84 @@ ++ ++ unsigned char MST_HSPRule_IP_Index_Main[PQ_HSPRule_IP_NUM_Main]= ++{ ++ PQ_IP_HSP_Y_SC1_Main, ++ PQ_IP_HSP_C_SC1_Main, ++ PQ_IP_SRAM2_Main, ++}; ++ ++ ++ unsigned char MST_HSPRule_Array_Main[PQ_HSPRule_NUM_Main][PQ_HSPRule_IP_NUM_Main]= ++{ ++ {//PreV_ScalingDown_Interlace, 0 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//PreV_ScalingDown_Progressive, 1 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_YUV, 2 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_RGB, 3 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_YUV, 4 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_RGB, 5 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_YUV, 6 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_RGB, 7 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_YUV, 8 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_RGB, 9 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_YUV, 10 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_RGB, 11 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_YUV, 12 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_RGB, 13 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_YUV, 14 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_RGB, 15 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_YUV, 16 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_RGB, 17 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_YUV, 18 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_RGB, 19 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_YUV, 20 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_RGB, 21 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_YUV, 22 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_RGB, 23 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++}; +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_HSPRule.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_HSPRule.h +new file mode 100644 +index 00000000..1f0fd410 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_HSPRule.h +@@ -0,0 +1,35 @@ ++#define PQ_HSPRule_ID_Main 0 ++#define PQ_HSPRule_IP_NUM_Main 3 ++#define PQ_HSPRule_NUM_Main 24 ++ ++ ++typedef enum ++{ ++PQ_HSPRule_PreV_ScalingDown_Interlace_Main, ++PQ_HSPRule_PreV_ScalingDown_Progressive_Main, ++PQ_HSPRule_ScalingDown_00x_YUV_Main, ++PQ_HSPRule_ScalingDown_00x_RGB_Main, ++PQ_HSPRule_ScalingDown_01x_YUV_Main, ++PQ_HSPRule_ScalingDown_01x_RGB_Main, ++PQ_HSPRule_ScalingDown_02x_YUV_Main, ++PQ_HSPRule_ScalingDown_02x_RGB_Main, ++PQ_HSPRule_ScalingDown_03x_YUV_Main, ++PQ_HSPRule_ScalingDown_03x_RGB_Main, ++PQ_HSPRule_ScalingDown_04x_YUV_Main, ++PQ_HSPRule_ScalingDown_04x_RGB_Main, ++PQ_HSPRule_ScalingDown_05x_YUV_Main, ++PQ_HSPRule_ScalingDown_05x_RGB_Main, ++PQ_HSPRule_ScalingDown_06x_YUV_Main, ++PQ_HSPRule_ScalingDown_06x_RGB_Main, ++PQ_HSPRule_ScalingDown_07x_YUV_Main, ++PQ_HSPRule_ScalingDown_07x_RGB_Main, ++PQ_HSPRule_ScalingDown_08x_YUV_Main, ++PQ_HSPRule_ScalingDown_08x_RGB_Main, ++PQ_HSPRule_ScalingDown_09x_YUV_Main, ++PQ_HSPRule_ScalingDown_09x_RGB_Main, ++PQ_HSPRule_ScalingDown_10x_YUV_Main, ++PQ_HSPRule_ScalingDown_10x_RGB_Main, ++} ++MST_HSPRule_Index_Main; ++extern unsigned char MST_HSPRule_IP_Index_Main[PQ_HSPRule_IP_NUM_Main]; ++extern unsigned char MST_HSPRule_Array_Main[PQ_HSPRule_NUM_Main][PQ_HSPRule_IP_NUM_Main]; +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_VSPRule.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_VSPRule.c +new file mode 100644 +index 00000000..a06e045d +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_VSPRule.c +@@ -0,0 +1,84 @@ ++ ++ unsigned char MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]= ++{ ++ PQ_IP_VSP_Y_SC1_Main, ++ PQ_IP_VSP_C_SC1_Main, ++ PQ_IP_SRAM1_Main, ++}; ++ ++ ++ unsigned char MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]= ++{ ++ {//PreV_ScalingDown_Interlace, 0 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//PreV_ScalingDown_Progressive, 1 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_YUV, 2 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_00x_RGB, 3 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_YUV, 4 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_01x_RGB, 5 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_YUV, 6 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_02x_RGB, 7 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_YUV, 8 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_03x_RGB, 9 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_YUV, 10 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_04x_RGB, 11 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_YUV, 12 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_05x_RGB, 13 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_YUV, 14 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_06x_RGB, 15 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_YUV, 16 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_07x_RGB, 17 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_YUV, 18 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_08x_RGB, 19 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_YUV, 20 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_09x_RGB, 21 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_YUV, 22 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++ {//ScalingDown_10x_RGB, 23 ++ PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, ++ }, ++}; +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_VSPRule.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_VSPRule.h +new file mode 100644 +index 00000000..d600dcfc +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_Main_VSPRule.h +@@ -0,0 +1,35 @@ ++#define PQ_VSPRule_ID_Main 1 ++#define PQ_VSPRule_IP_NUM_Main 3 ++#define PQ_VSPRule_NUM_Main 24 ++ ++ ++typedef enum ++{ ++PQ_VSPRule_PreV_ScalingDown_Interlace_Main, ++PQ_VSPRule_PreV_ScalingDown_Progressive_Main, ++PQ_VSPRule_ScalingDown_00x_YUV_Main, ++PQ_VSPRule_ScalingDown_00x_RGB_Main, ++PQ_VSPRule_ScalingDown_01x_YUV_Main, ++PQ_VSPRule_ScalingDown_01x_RGB_Main, ++PQ_VSPRule_ScalingDown_02x_YUV_Main, ++PQ_VSPRule_ScalingDown_02x_RGB_Main, ++PQ_VSPRule_ScalingDown_03x_YUV_Main, ++PQ_VSPRule_ScalingDown_03x_RGB_Main, ++PQ_VSPRule_ScalingDown_04x_YUV_Main, ++PQ_VSPRule_ScalingDown_04x_RGB_Main, ++PQ_VSPRule_ScalingDown_05x_YUV_Main, ++PQ_VSPRule_ScalingDown_05x_RGB_Main, ++PQ_VSPRule_ScalingDown_06x_YUV_Main, ++PQ_VSPRule_ScalingDown_06x_RGB_Main, ++PQ_VSPRule_ScalingDown_07x_YUV_Main, ++PQ_VSPRule_ScalingDown_07x_RGB_Main, ++PQ_VSPRule_ScalingDown_08x_YUV_Main, ++PQ_VSPRule_ScalingDown_08x_RGB_Main, ++PQ_VSPRule_ScalingDown_09x_YUV_Main, ++PQ_VSPRule_ScalingDown_09x_RGB_Main, ++PQ_VSPRule_ScalingDown_10x_YUV_Main, ++PQ_VSPRule_ScalingDown_10x_RGB_Main, ++} ++MST_VSPRule_Index_Main; ++extern unsigned char MST_VSPRule_IP_Index_Main[PQ_VSPRule_IP_NUM_Main]; ++extern unsigned char MST_VSPRule_Array_Main[PQ_VSPRule_NUM_Main][PQ_VSPRule_IP_NUM_Main]; +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_QualityMap_Simplify.xls b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_QualityMap_Simplify.xls +new file mode 100644 +index 00000000..f3a07eee +Binary files /dev/null and b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/include/sc/Infinity3e_QualityMap_Simplify.xls differ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/mhal_pq.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/mhal_pq.c +new file mode 100644 +index 00000000..cb3bb953 +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/hal/mhal_pq.c +@@ -0,0 +1,608 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// $Change: 617839 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++#define MHAL_PQ_C ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++// Common Definition ++#if defined(MSOS_TYPE_LINUX_KERNEL) ++#include ++#include ++#else ++#include ++#endif ++ ++#include "MsCommon.h" ++#include "MsOS.h" ++ ++// Internal Definition ++#include "hwreg_utility2.h" ++#include "hwreg.h" ++#include "drvPQ_Define.h" ++ ++#include "Infinity3e_Main.h" // table config parameter ++ ++ ++#include "drvPQ_Datatypes.h" ++#include "mhal_pq.h" ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Local Structures ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++MS_U32 PQ_RIU_BASE; ++ ++// Put this function here because hwreg_utility2 only for hal. ++void Hal_PQ_init_riu_base(MS_U32 u32riu_base) ++{ ++ PQ_RIU_BASE = u32riu_base; ++} ++ ++#if (PQ_ENABLE_UNUSED_FUNC) ++ ++MS_U8 Hal_PQ_get_sync_flag(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++ ++MS_U8 Hal_PQ_get_input_vsync_value(PQ_WIN ePQWin) ++{ ++ return (Hal_PQ_get_sync_flag(ePQWin) & 0x04) ? 1:0; ++} ++ ++MS_U8 Hal_PQ_get_output_vsync_value(PQ_WIN ePQWin) ++{ ++ return (Hal_PQ_get_sync_flag(ePQWin) & 0x01) ? 1 : 0; ++} ++ ++MS_U8 Hal_PQ_get_input_vsync_polarity(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_memfmt_doublebuffer(PQ_WIN ePQWin, MS_BOOL bEn) ++{ ++ ++} ++#endif ++ ++void Hal_PQ_set_sourceidx(PQ_WIN ePQWin, MS_U16 u16Idx) ++{ ++ ++} ++ ++#if (PQ_ENABLE_UNUSED_FUNC) ++ ++void Hal_PQ_set_mem_fmt(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask) ++{ ++ ++} ++ ++void Hal_PQ_set_mem_fmt_en(PQ_WIN ePQWin, MS_U16 u16val, MS_U16 u16Mask) ++{ ++ ++} ++ ++void Hal_PQ_set_420upSample(PQ_WIN ePQWin, MS_U16 u16value) ++{ ++ ++} ++ ++void Hal_PQ_set_force_y_motion(PQ_WIN ePQWin, MS_U16 u16value) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_force_y_motion(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_force_c_motion(PQ_WIN ePQWin, MS_U16 u16value) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_force_c_motion(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_dipf_temporal(PQ_WIN ePQWin, MS_U16 u16val) ++{ ++} ++ ++MS_U16 Hal_PQ_get_dipf_temporal(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_dipf_spatial(PQ_WIN ePQWin, MS_U16 u16val) ++{ ++} ++ ++MS_U8 Hal_PQ_get_dipf_spatial(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_vsp_sram_filter(PQ_WIN ePQWin, MS_U8 u8vale) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_vsp_sram_filter(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_dnr(PQ_WIN ePQWin, MS_U8 u8val) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_dnr(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++ ++void Hal_PQ_set_presnr(PQ_WIN ePQWin, MS_U8 u8val) ++{ ++} ++ ++MS_U8 Hal_PQ_get_presnr(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++ ++void Hal_PQ_set_film(PQ_WIN ePQWin, MS_U16 u16val) ++{ ++ ++} ++ ++MS_U8 Hal_PQ_get_film(PQ_WIN ePQWin) ++{ ++ return 0; ++} ++#endif ++ ++void Hal_PQ_set_yc_sram(MS_U8 enID, MS_U8 u8sramtype, void *pData) ++{ ++ MS_U32 u32reg_41, u32reg_42, u32reg_43; ++ MS_U32 u32Addr; ++ MS_U8 u8Ramcode[10]; ++ MS_U16 u16IdxBase = 0; ++ MS_U16 i, j, x; ++ MS_BOOL bC_SRAM; ++ ++#ifdef C3_SIM ++ return; ++#endif ++ ++ if(enID == FILTER_SRAM_SC2) ++ { ++ u32reg_41 = REG_SCL_HVSP1_41_L; ++ u32reg_42 = REG_SCL_HVSP1_42_L; ++ u32reg_43 = REG_SCL_HVSP1_43_L; ++ } ++ else if(enID == FILTER_SRAM_SC3) ++ { ++ u32reg_41 = REG_SCL_HVSP2_41_L; ++ u32reg_42 = REG_SCL_HVSP2_43_L; ++ u32reg_43 = REG_SCL_HVSP2_43_L; ++ } ++ else ++ { ++ u32reg_41 = REG_SCL_HVSP0_41_L; ++ u32reg_42 = REG_SCL_HVSP0_42_L; ++ u32reg_43 = REG_SCL_HVSP0_43_L; ++ } ++ ++ bC_SRAM = u8sramtype >= SC_FILTER_C_SRAM1 ? TRUE : FALSE; ++ ++ if(u8sramtype == SC_FILTER_Y_SRAM1 || u8sramtype == SC_FILTER_C_SRAM1) ++ { ++ u16IdxBase = 0x00; ++ } ++ else if(u8sramtype == SC_FILTER_Y_SRAM2 || u8sramtype == SC_FILTER_C_SRAM2) ++ { ++ u16IdxBase = 0x40; ++ } ++ else if(u8sramtype == SC_FILTER_Y_SRAM3 || u8sramtype == SC_FILTER_C_SRAM3) ++ { ++ u16IdxBase = 0x80; ++ } ++ else ++ { ++ u16IdxBase = 0xC0; ++ } ++ ++ u32Addr = (MS_U32)pData; ++ ++ W2BYTEMSK(u32reg_41, bC_SRAM ? BIT1 : BIT0, BIT1|BIT0); // reg_cram_rw_en ++ ++ for(i=0; i<64; i++) ++ { ++ while(MApi_XC_R2BYTE(u32reg_41) & BIT8); ++ j=i*5; ++ ++ MApi_XC_W2BYTEMSK(u32reg_42,(i|u16IdxBase), 0x00FF); ++ for ( x=0;x<5;x++ ) ++ { ++ u8Ramcode[x] = *((MS_U8 *)(u32Addr + (j+x))); ++ } ++ ++ MApi_XC_W2BYTE(u32reg_43+0x00, (((MS_U16)u8Ramcode[1])<<8|(MS_U16)u8Ramcode[0])); ++ MApi_XC_W2BYTE(u32reg_43+0x02, (((MS_U16)u8Ramcode[3])<<8|(MS_U16)u8Ramcode[2])); ++ MApi_XC_W2BYTEMSK(u32reg_43+0x04, ((MS_U16)u8Ramcode[4]), 0x00FF); ++ ++ ++ MApi_XC_W2BYTEMSK(u32reg_41, BIT8, BIT8); ++ } ++} ++ ++void Hal_PQ_set_sram_color_index_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ //ToDo ++ ++} ++ ++void Hal_PQ_set_sram_color_gain_snr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ ++} ++ ++ ++void Hal_PQ_set_sram_color_gain_dnr_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ ++} ++ ++#define ICC_H_SIZE 32 ++#define ICC_V_SIZE 32 ++void Hal_PQ_set_sram_icc_crd_table(PQ_WIN ePQWin, MS_U8 u8sramtype, void *pData) ++{ ++ MS_U16 i; ++ MS_U16 u16Ramcode_L,u16Ramcode_H; ++ MS_U16 u16Ramcode; ++ MS_U32 u32Addr; ++ MS_U32 u32BK18_78, u32BK18_79, u32BK18_7A; ++ ++ if(u8sramtype != SC_FILTER_SRAM_ICC_CRD) ++ { ++ return; ++ } ++ ++ if(ePQWin == PQ_MAIN_WINDOW) ++ { ++ u32BK18_78 = REG_VIP_ACE2_78_L; ++ u32BK18_79 = REG_VIP_ACE2_79_L; ++ u32BK18_7A = REG_VIP_ACE2_7A_L; ++ } ++ else ++ { ++ return; ++ } ++ ++ u32Addr = (MS_U32)pData; ++ ++ MApi_XC_W2BYTEMSK(u32BK18_78, BIT(0), BIT(0)); // io_en disable ++ ++ for(i=0; i<(ICC_H_SIZE*ICC_V_SIZE); i++) ++ { ++ u16Ramcode_L = *((MS_U8 *)(u32Addr + (2*i))); ++ u16Ramcode_H = *((MS_U8 *)(u32Addr + (2*i+1))); ++ u16Ramcode = ((u16Ramcode_H & 0x01)<<8)+u16Ramcode_L; ++ ++ //while (MApi_XC_R2BYTE(u32BK18_7A) & BIT(15)); ++ MApi_XC_W2BYTEMSK(u32BK18_79, i, 0x03FF); // address ++ MApi_XC_W2BYTEMSK(u32BK18_7A, (u16Ramcode & 0x1FF), 0x01FF); //data[8:0] ++ MApi_XC_W2BYTEMSK(u32BK18_7A, BIT(15), BIT(15)); // io_w enable ++ ++ } ++ ++ MApi_XC_W2BYTEMSK(u32BK18_78, 0, BIT(0)); // io_en enable ++} ++ ++ ++#define IHC_H_SIZE 33 ++#define IHC_V_SIZE 33 ++#define BUF_BYTE_SIZE (IHC_H_SIZE*IHC_V_SIZE) ++#define MAX_SRAM_SIZE 0x124 ++ ++#define SRAM1_IHC_COUNT 289//81 ++#define SRAM2_IHC_COUNT 272//72 ++#define SRAM3_IHC_COUNT 272//72 ++#define SRAM4_IHC_COUNT 256//64 ++ ++#define SRAM1_IHC_OFFSET 0 ++#define SRAM2_IHC_OFFSET SRAM1_IHC_COUNT ++#define SRAM3_IHC_OFFSET (SRAM2_IHC_OFFSET + SRAM2_IHC_COUNT) ++#define SRAM4_IHC_OFFSET (SRAM3_IHC_OFFSET + SRAM3_IHC_COUNT) ++ ++#define SRAM_IHC_TOTAL_COUNT SRAM1_IHC_COUNT + SRAM2_IHC_COUNT + SRAM3_IHC_COUNT + SRAM4_IHC_COUNT ++ ++ ++void _Hal_PQ_set_sram_ihc_crd_table(PQ_WIN ePQWin, MS_U16 *pBuf, MS_U8 u8SRAM_Idx, MS_U16 u16Cnt) ++{ ++ MS_U16 i; ++ MS_U32 u32BK18_7C, u32BK18_7D, u32BK18_7E; ++ ++ if(u8SRAM_Idx > 3) ++ { ++ u8SRAM_Idx = 0; ++ } ++ ++ if(ePQWin == PQ_MAIN_WINDOW) ++ { ++ u32BK18_7C = REG_VIP_ACE2_7C_L; ++ u32BK18_7D = REG_VIP_ACE2_7D_L; ++ u32BK18_7E = REG_VIP_ACE2_7E_L; ++ } ++ else ++ { ++ return; ++ } ++ ++ ++ MApi_XC_W2BYTEMSK(u32BK18_7C, BIT(0), BIT(0)); // io_en disable ++ MApi_XC_W2BYTEMSK(u32BK18_7C, u8SRAM_Idx<<1, BIT(2)|BIT(1)); // sram select ++ ++ for(i=0; i u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hup_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_444_PC_Hup_Vno_Main; ++ } ++ } ++ else if (u16Input_HSize > u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hdown_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hdown_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_444_PC_Hdown_Vno_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hno_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_444_PC_Hno_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_444_PC_Hno_Vno_Main; ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceHDMI(enInputSourceType) ++ #if(PQ_ENABLE_UNUSED_FUNC) ++ && QM_HDMIPC_COLORYUV422(eWindow) ++ #endif ++ ) ++ { ++#if (PQ_QM_HDMI_PC) ++ // PC YUV422 ++ if (u16Input_HSize < u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hup_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hup_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_422_PC_Hup_Vno_Main; ++ } ++ } ++ else if (u16Input_HSize > u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hdown_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hdown_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_422_PC_Hdown_Vno_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hno_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_HDMI_422_PC_Hno_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_422_PC_Hno_Vno_Main; ++ } ++ } ++#endif ++ } ++ else //(QM_HDMIPC_COLORRGB(eWindow)) & default ++ { ++#if (PQ_QM_PC) ++ // PC RGB ++ if (u16Input_HSize < u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hup_Vno_Main; ++ } ++ } ++ else if (u16Input_HSize > u16Disp_HSize) ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hdown_Vno_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VSize < u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vup_Main; ++ } ++ else if (u16Input_VSize > u16Disp_VSize) ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vdown_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_Main; ++ } ++ } ++#endif ++ } ++ } ++ else if (QM_IsSourceHDMI(enInputSourceType) ++#if ENABLE_VGA_EIA_TIMING ++ || QM_IsSourceVGA(enInputSourceType) //interlace VGA comes here ++#endif ++ ) ++ { ++#if (PQ_QM_HMDI) ++#if 0//debug message ++ if(QM_HDMIPC_COLORRGB(eWindow)) ++ printf("HDMI RGB\n"); ++ else if(QM_HDMIPC_COLORYUV444(eWindow)) ++ printf("HDMI YUV 444\n"); ++ else ++ printf("HDMI YUV 422\n"); ++#endif ++ if( QM_IsSourceHDMI(enInputSourceType) && QM_HDMIPC_COLORRGB(eWindow) && ++ (MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) && (!bIsInterlaced)) ++ { ++ // HDMI RGB progressive ++ u16SrcType = QM_DVI_Dsub_HDMI_RGB_PC_Hno_Vno_Main; ++ } ++ else if( QM_IsSourceHDMI(enInputSourceType) && QM_HDMIPC_COLORYUV444(eWindow) && ++ (MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) && (!bIsInterlaced)) ++ { ++ // HDMI YUV444 progressive ++ u16SrcType = QM_HDMI_444_PC_Hno_Vno_Main; ++ } ++ else ++ { ++ // HDMI ++ if ((u16Input_HSize < 800) && (u16Input_VSize < 500)) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_HDMI_480i_Main; ++ else ++ u16SrcType = QM_HDMI_480p_Main; ++ } ++ else if ((u16Input_HSize < 800) && (u16Input_VSize < 600)) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_HDMI_576i_Main; ++ else ++ u16SrcType = QM_HDMI_576p_Main; ++ } ++ else if ((u16Input_HSize < 1300) && (u16Input_VSize < 800) && (!bIsInterlaced)) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_HDMI_720p_60hz_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_HDMI_720p_50hz_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_720p_24hz_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_HDMI_1080i_60hz_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_1080i_50hz_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_HDMI_1080p_60hz_Main; ++ } ++ else if(u16Input_VFreq > 450) ++ { ++ u16SrcType = QM_HDMI_1080p_50hz_Main; ++ } ++ else // Other timing ++ { ++ u16SrcType = QM_HDMI_1080p_24hz_Main; ++ } ++ } ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceYPbPr(enInputSourceType)) ++ { ++#if (PQ_QM_YPBPR) ++ if( QM_IsSourceYPbPr(enInputSourceType) && ++ (MDrv_PQ_Get_PointToPoint(PQ_MAIN_WINDOW)) && (!bIsInterlaced)) ++ { ++ // YUV444 progressive ++ u16SrcType = QM_HDMI_444_PC_Hno_Vno_Main; ++ } ++ else if (QM_IsYPbPr_720x480_60I(eWindow)){ ++ u16SrcType = QM_YPbPr_480i_Main; ++ } ++ else if (QM_IsYPbPr_720x480_60P(eWindow)){ ++ u16SrcType = QM_YPbPr_480p_Main; ++ } ++ else if (QM_IsYPbPr_720x576_50I(eWindow)){ ++ u16SrcType = QM_YPbPr_576i_Main; ++ } ++ else if (QM_IsYPbPr_720x576_50P(eWindow)){ ++ u16SrcType = QM_YPbPr_576p_Main; ++ } ++ else if (QM_IsYPbPr_1280x720_50P(eWindow)){ ++ u16SrcType = QM_YPbPr_720p_50hz_Main; ++ } ++ else if (QM_IsYPbPr_1280x720_60P(eWindow)){ ++ u16SrcType = QM_YPbPr_720p_60hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_50I(eWindow)){ ++ u16SrcType = QM_YPbPr_1080i_50hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_60I(eWindow)){ ++ u16SrcType = QM_YPbPr_1080i_60hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_24P(eWindow) || QM_IsYPbPr_1920x1080_30P(eWindow) || QM_IsYPbPr_1920x1080_25P(eWindow) ){ ++ u16SrcType = QM_YPbPr_1080p_24hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_50P(eWindow)){ ++ u16SrcType = QM_YPbPr_1080p_50hz_Main; ++ } ++ else if (QM_IsYPbPr_1920x1080_60P(eWindow)){ ++ u16SrcType = QM_YPbPr_1080p_60hz_Main; ++ } ++ else { ++ u16SrcType = QM_YPbPr_720p_24hz_Main; ++ } ++#endif ++ } ++ else if(QM_IsSrource656(enInputSourceType)) ++ { ++#if (PQ_QM_CVBS) ++ if(u16Input_VSize <= 480) ++ { ++ if(bIsInterlaced) ++ { ++ u16SrcType = QM_HDMI_480i_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_480p_Main; ++ } ++ } ++ else ++ { ++ if(bIsInterlaced) ++ { ++ u16SrcType = QM_HDMI_576i_Main; ++ } ++ else ++ { ++ u16SrcType = QM_HDMI_576p_Main; ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceDTV(enInputSourceType)) ++ { ++#if (PQ_QM_DTV) ++ if(QM_IsDTV_IFRAME(eWindow)) ++ { ++ #if 1 //( CHIP_FAMILY_TYPE != CHIP_FAMILY_S7J) ++ //If PQ has devide the iframe setting according to P/I mode, then use new PQ srctype ++ if (u16Input_VSize < 720) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_iFrame_SD_interlace_Main; ++ else ++ u16SrcType = QM_DTV_iFrame_SD_progressive_Main; ++ } ++ else ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_iFrame_HD_interlace_Main; ++ else ++ u16SrcType = QM_DTV_iFrame_HD_progressive_Main; ++ } ++ #else ++ u16SrcType = QM_DTV_iFrame_Main; ++ #endif ++ } ++ else if (QM_IsDTV_MPEG2(eWindow)) ++ { ++ if (u16Input_VSize < 500) ++ { ++ if ((u16Input_HSize < 400) && bIsInterlaced) ++ { ++ u16SrcType = QM_DTV_480i_352x480_MPEG2_Main; ++ } ++ else ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_480i_MPEG2_Main; ++ else ++ u16SrcType = QM_DTV_480p_MPEG2_Main; ++ } ++ } ++ else if (u16Input_VSize < 650) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_576i_MPEG2_Main; ++ else ++ u16SrcType = QM_DTV_576p_MPEG2_Main; ++ } ++ else if ((u16Input_VSize < 900) && (bIsInterlaced==0)) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_720p_60hz_MPEG2_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_720p_50hz_MPEG2_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_720p_24hz_MPEG2_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080i_60hz_MPEG2_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080i_50hz_MPEG2_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080p_60hz_MPEG2_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_1080p_50hz_MPEG2_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080p_24hz_MPEG2_Main; ++ } ++ ++ } ++ } ++ } ++ else // QM_IsDTV_H264(eWindow) ++ { ++ if ((u16Input_HSize < 1260) && (u16Input_VSize < 650)) ++ { ++ if (u16Input_VSize < 500) ++ { ++ if ((u16Input_HSize < 400) && bIsInterlaced) ++ { ++ u16SrcType = QM_DTV_480i_352x480_H264_Main; ++ } ++ else ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_480i_H264_Main; ++ else ++ u16SrcType = QM_DTV_480p_H264_Main; ++ } ++ } ++ else if (u16Input_VSize < 650) ++ { ++ if (bIsInterlaced) ++ u16SrcType = QM_DTV_576i_H264_Main; ++ else ++ u16SrcType = QM_DTV_576p_H264_Main; ++ } ++ } ++ else ++ { ++ if ((u16Input_VSize < 900) && (bIsInterlaced==0)) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_720p_60hz_H264_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_720p_50hz_H264_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_720p_24hz_H264_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080i_60hz_H264_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080i_50hz_H264_Main; ++ } ++ } ++ else ++ { ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_DTV_1080p_60hz_H264_Main; ++ } ++ else if(u16Input_VFreq > 250) ++ { ++ u16SrcType = QM_DTV_1080p_50hz_H264_Main; ++ } ++ else ++ { ++ u16SrcType = QM_DTV_1080p_24hz_H264_Main; ++ } ++ } ++ } ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceMultiMedia(enInputSourceType)) ++ { ++#if (PQ_QM_MM_VIDEO) || (PQ_QM_MM_PHOTO) ++ if (QM_IsMultiMediaMOVIE(eWindow)) ++ { ++ if ((u16Input_HSize <= 720) && (u16Input_VSize <= 576)) ++ { ++ if (bIsInterlaced) ++ { ++ u16SrcType = QM_Multimedia_video_SD_interlace_Main; ++ } ++ else ++ { ++ u16SrcType = QM_Multimedia_video_SD_progressive_Main; ++ } ++ } ++ else ++ { ++ if (bIsInterlaced) ++ { ++ u16SrcType = QM_Multimedia_video_HD_interlace_Main; ++ } ++ else ++ { ++ u16SrcType = QM_Multimedia_video_HD_progressive_Main; ++ } ++ } ++ } ++ else //QM_IsMultiMediaPHOTO(eWindow) ++ { ++ if ((u16Input_HSize <= 720) && (u16Input_VSize <= 576)) ++ { ++ u16SrcType = QM_Multimedia_photo_SD_progressive_Main; ++ } ++ else ++ { ++ u16SrcType = QM_Multimedia_photo_HD_progressive_Main; ++ } ++ } ++#endif ++ } ++#if (PQ_ENABLE_UNUSED_FUNC) ++ else if (QM_IsSourceScartRGB(enInputSourceType, eWindow)) ++ { ++#if (PQ_QM_CVBS) ++ if (u16Input_VFreq > 550) ++ { ++ u16SrcType = QM_SCART_RGB_NTSC_Main; ++ } ++ else ++ { ++ u16SrcType = QM_SCART_RGB_PAL_Main; ++ } ++#endif ++ } ++ else if (QM_IsSourceScartCVBS(enInputSourceType, eWindow)) ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_SCART_AV_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_SCART_AV_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_SCART_AV_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_SCART_AV_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_SCART_AV_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_SCART_AV_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_SCART_AV_PAL_BGHI_Main; ++ break; ++ } ++#endif ++ } ++#endif ++ else if (QM_IsSourceATV(enInputSourceType)) ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ if (QM_FRONTEND_RFIN(eWindow)) ++ { ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_RF_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_RF_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_RF_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_RF_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_RF_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_RF_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_RF_PAL_BGHI_Main; ++ break; ++ } ++ } ++ else // QM_FRONTEND_VIFIN(eWindow) ++ { ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_VIF_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_VIF_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_VIF_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_VIF_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_VIF_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_VIF_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_VIF_PAL_BGHI_Main; ++ break; ++ } ++ } ++#endif ++ } ++ else if (QM_IsSourceSV(enInputSourceType)) ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_SV_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_SV_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_SV_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_SV_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_SV_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_SV_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_SV_PAL_BGHI_Main; ++ break; ++ } ++#endif ++ } ++ ++ else if(QM_IsSourceISP(enInputSourceType)) ++ { ++#if (PQ_QM_ISP) ++ u16SrcType = QM_FHD_YUV422_Main; ++#endif ++ } ++ else // AV ++ { ++#if (PQ_QM_CVBS) ++ eStandard = QM_GetATVStandard(eWindow); ++ switch(eStandard) ++ { ++ case E_PQ_VIDEOSTANDARD_PAL_M: ++ u16SrcType = QM_AV_PAL_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_N: ++ u16SrcType = QM_AV_PAL_N_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_44: ++ u16SrcType = QM_AV_NTSC_44_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_60: ++ u16SrcType = QM_AV_PAL_60_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_NTSC_M: ++ u16SrcType = QM_AV_NTSC_M_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_SECAM: ++ u16SrcType = QM_AV_SECAM_Main; ++ break; ++ case E_PQ_VIDEOSTANDARD_PAL_BGHI: ++ default: ++ u16SrcType = QM_AV_PAL_BGHI_Main; ++ break; ++ } ++#endif ++ } ++ return u16SrcType; ++ ++} +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/include/QualityMode.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/include/QualityMode.h +new file mode 100644 +index 00000000..ed0e302f +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/include/QualityMode.h +@@ -0,0 +1,78 @@ ++ ++ ++#define QM_IsSourceVGA(x) ((x)==PQ_INPUT_SOURCE_VGA) ++#define QM_IsSourceHDMI(x) ((x)==PQ_INPUT_SOURCE_HDMI) ++#define QM_IsSourceDVI_HDMIPC(x,y) (QM_IsSourceHDMI(x) && (_stHDMI_Info[y].bIsHDMI == FALSE)) ++#define QM_IsSourceHDMI_Video(x,y) (QM_IsSourceHDMI(x) && (_stHDMI_Info[y].bIsHDMI == TRUE) && (_stHDMI_Info[y].bIsHDMIPC == FALSE)) ++#define QM_IsSourceHDMI_PC(x,y) (QM_IsSourceHDMI(x) && (_stHDMI_Info[y].bIsHDMI == TRUE) && (_stHDMI_Info[y].bIsHDMIPC == TRUE)) ++ ++#define QM_HDMIPC_COLORRGB(x) (_stHDMI_Info[x].enColorFmt == PQ_HDMI_COLOR_RGB) ++#define QM_HDMIPC_COLORYUV422(x) (_stHDMI_Info[x].enColorFmt == PQ_HDMI_COLOR_YUV_422) ++#define QM_HDMIPC_COLORYUV444(x) (_stHDMI_Info[x].enColorFmt == PQ_HDMI_COLOR_YUV_444) ++ ++#define QM_IsSrource656(x) ((x)== PQ_INPUT_SOURCE_BT656) ++ ++#define QM_IsSourceYPbPr(x) ((x)==PQ_INPUT_SOURCE_YPBPR) ++ ++#define QM_IsSourceYPbPrSD(x,y) (QM_IsSourceYPbPr(x) \ ++ && ( _u8ModeIndex[y] == PQ_MD_720x480_60I \ ++ ||_u8ModeIndex[y] == PQ_MD_720x480_60P \ ++ ||_u8ModeIndex[y] == PQ_MD_720x576_50I \ ++ ||_u8ModeIndex[y] == PQ_MD_720x576_50P) ) ++ ++#define QM_IsSourceDTV(x) ((x)==PQ_INPUT_SOURCE_DTV) ++#define QM_IsSourceMultiMedia(x) (((x)>=PQ_INPUT_SOURCE_STORAGE) && ((x)<=PQ_INPUT_SOURCE_JPEG)) ++ ++#define QM_IsMultiMediaMOVIE(x) (_stMultiMedia_Info[x].eType == E_PQ_MULTIMEDIA_MOVIE) ++#define QM_IsMultiMediaPHOTO(x) (_stMultiMedia_Info[x].eType == E_PQ_MULTIMEDIA_PHOTO) ++ ++#define QM_IsDTV_MPEG2(x) (_stDTV_Info[x].eType == E_PQ_DTV_MPEG2) ++#define QM_IsDTV_H264(x) (_stDTV_Info[x].eType == E_PQ_DTV_H264) ++#define QM_IsDTV_IFRAME(x) (_stDTV_Info[x].eType == E_PQ_DTV_IFRAME) ++ ++#define QM_IsSourceScartRGB(x,y) (((x)==PQ_INPUT_SOURCE_SCART) && (_stVD_Info[y].bIsSCART_RGB == TRUE)) ++#define QM_IsSourceScartCVBS(x,y) (((x)==PQ_INPUT_SOURCE_SCART) && (_stVD_Info[y].bIsSCART_RGB == FALSE)) ++#define QM_IsSourceScart(x) ((x)==PQ_INPUT_SOURCE_SCART) ++#define QM_IsSourceATV(x) ((x)==PQ_INPUT_SOURCE_TV) ++#define QM_IsSourceSV(x) ((x)==PQ_INPUT_SOURCE_SVIDEO) ++#define QM_IsSourceAV(x) ((x)==PQ_INPUT_SOURCE_CVBS) ++#define QM_IsSourceVD(x) ( QM_IsSourceATV(x) \ ++ || QM_IsSourceAV(x) \ ++ || QM_IsSourceSV(x) \ ++ || QM_IsSourceScart(x) ) ++#define QM_IsSourceISP(x) ((x) == PQ_INPUT_SOURCE_ISP) ++#define QM_Is3DVideo() (_gIs3D_En == TRUE) ++ ++#define QM_FRONTEND_RFIN(x) (!_stVD_Info[x].bIsVIFIN) ++#define QM_FRONTEND_VIFIN(x) (_stVD_Info[x].bIsVIFIN) ++ ++#define QM_GetInputHSize(x) (_stMode_Info[x].u16input_hsize) ++#define QM_GetInputVSize(x) (_stMode_Info[x].u16input_vsize) ++ ++#define QM_H_Size_Check_x1(x, y) ( ((x) < ((y)*1+50)) && ((x) > ((y)*1-50)) ) ++#define QM_H_Size_Check_x2(x, y) ( ((x) < ((y)*2+50)) && ((x) > ((y)*2-50)) ) ++#define QM_H_Size_Check_x4(x, y) ( ((x) < ((y)*4+50)) && ((x) > ((y)*4-50)) ) ++#define QM_H_Size_Check_x8(x, y) ( ((x) < ((y)*8+50)) && ((x) > ((y)*8-50)) ) ++ ++#define QM_IsYPbPr_720x480_60I(x) (_u8ModeIndex[x] == PQ_MD_720x480_60I) ++#define QM_IsYPbPr_720x480_60P(x) (_u8ModeIndex[x] == PQ_MD_720x480_60P) ++#define QM_IsYPbPr_720x576_50I(x) (_u8ModeIndex[x] == PQ_MD_720x576_50I) ++#define QM_IsYPbPr_720x576_50P(x) (_u8ModeIndex[x] == PQ_MD_720x576_50P) ++#define QM_IsYPbPr_1280x720_50P(x) (_u8ModeIndex[x] == PQ_MD_1280x720_50P) ++#define QM_IsYPbPr_1280x720_60P(x) (_u8ModeIndex[x] == PQ_MD_1280x720_60P) ++#define QM_IsYPbPr_1920x1080_50I(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_50I) ++#define QM_IsYPbPr_1920x1080_60I(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_60I) ++ ++#define QM_IsYPbPr_1920x1080_24P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_24P) ++#define QM_IsYPbPr_1920x1080_25P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_25P) ++#define QM_IsYPbPr_1920x1080_30P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_30P) ++#define QM_IsYPbPr_1920x1080_50P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_50P) ++#define QM_IsYPbPr_1920x1080_60P(x) (_u8ModeIndex[x] == PQ_MD_1920x1080_60P) ++ ++#define QM_GetInputVFreq(x) (_stMode_Info[x].u16input_vfreq) ++#define QM_IsInterlaced(x) (_stMode_Info[x].bInterlace) ++ ++#define QM_GetDispHSize(x) (_stMode_Info[x].u16display_hsize) ++#define QM_GetDispVSize(x) (_stMode_Info[x].u16display_vsize) ++ ++#define QM_GetATVStandard(x) (_stVD_Info[x].enVideoStandard) +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/include/drvPQ.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/include/drvPQ.h +new file mode 100644 +index 00000000..fc94691f +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/include/drvPQ.h +@@ -0,0 +1,1397 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// @file drvPQ.h ++/// @brief PQ interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef _DRVPQ_H_ ++#define _DRVPQ_H_ ++ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Macro and Define ++//------------------------------------------------------------------------------------------------- ++ ++#define MSIF_PQ_TAG {'M','S','I','F'} // MSIF ++#define MSIF_PQ_CLASS {'0','0'} // DRV/API (DDI) ++#define MSIF_PQ_CUS 0x0000 // MStar Common library ++#define MSIF_PQ_MOD 0x0000 // MStar Common library ++#define MSIF_PQ_CHIP 0x0000 ++#define MSIF_PQ_CPU '0' ++#define MSIF_PQ_OS '0' ++ ++// library information ++ ++/// the PQ lib code ++#define MSIF_PQ_LIB_CODE {'P','Q','_','_'} ++/// the PQ lib version ++#define MSIF_PQ_LIBVER {'0','0'} ++/// the PQ build number ++#define MSIF_PQ_BUILDNUM {'0','7'} ++/// the PQ CL ++#define MSIF_PQ_CHANGELIST {'0','0','3','5','3','5','7','6'} ++ ++/// the PQ driver version ++#define PQ_DRV_VERSION /* Character String for DRV/API version */ \ ++ MSIF_PQ_TAG, /* 'MSIF' */ \ ++ MSIF_PQ_CLASS, /* '00' */ \ ++ MSIF_PQ_CUS, /* 0x0000 */ \ ++ MSIF_PQ_MOD, /* 0x0000 */ \ ++ MSIF_PQ_CHIP, \ ++ MSIF_PQ_CPU, \ ++ MSIF_PQ_LIB_CODE , /* IP__ */ \ ++ MSIF_PQ_LIBVER , /* 0.0 ~ Z.Z */ \ ++ MSIF_PQ_BUILDNUM , /* 00 ~ 99 */ \ ++ MSIF_PQ_CHANGELIST, /* CL# */ \ ++ MSIF_PQ_OS ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++ ++#define ENABLE_PQ_LOAD_TABLE_INFO 0 ///= CMDQ_MAX_CMD_SIZE) \ ++ { \ ++ _u16CMDQCmdCnt = CMDQ_MAX_CMD_SIZE-1; \ ++ } \ ++ \ ++ }while(0) ++#endif ++ ++ ++#if (PQ_ENABLE_CHECK == 0) ++ #define PQ_REG_FUNC_READ( u32Reg) MApi_XC_ReadByte(u32Reg) ++ #define PQ_REG_FUNC( u32Reg, u8Value, u8Mask ) MApi_XC_WriteByteMask( u32Reg, u8Value, u8Mask ) ++ #define PQ_REG_FUNC_xc( u32Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if(u32Reg %2){ \ ++ MApi_XC_W2BYTEMSK(u32Reg-1, ((MS_U16)u8Value)<<8, ((MS_U16)u8Mask)<<8); \ ++ }else{ \ ++ MApi_XC_W2BYTEMSK(u32Reg, u8Value, u8Mask); \ ++ }\ ++ }while(0) ++ ++ #define PQ_REG_MLOAD_WRITE_CMD(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg-1; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask)<<8; \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value)<<8; \ ++ } \ ++ else \ ++ { \ ++ _u32MLoadCmd[_u16MLoadCmdCnt] = u32Reg; \ ++ _u16MLoadMsk[_u16MLoadCmdCnt] = ((MS_U16)u8Mask); \ ++ _u16MLoadVal[_u16MLoadCmdCnt] = ((MS_U16)u8Value); \ ++ } \ ++ _u16MLoadCmdCnt++; \ ++ if(_u16MLoadCmdCnt >= MLOAD_MAX_CMD)\ ++ {\ ++ printf("[PQ ERROR] ====ML overflow !!! \r\n");\ ++ _u16MLoadCmdCnt = MLOAD_MAX_CMD - 1; \ ++ }\ ++ }while(0) ++ ++ #define PQ_REG_MLOAD_FUNC(u32Reg,u8Value,u8Mask) \ ++ do{ \ ++ if(u32Reg%2) \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg-1, ((MS_U16)u8Value)<<8, ((MS_U16)u8Mask)<<8); \ ++ } \ ++ else \ ++ { \ ++ MApi_XC_MLoad_WriteCmd_And_Fire(u32Reg, u8Value, u8Mask); \ ++ } \ ++ }while(0) ++ ++ #define PQ_SWREG_FUNC( u16Reg, u8Value, u8Mask ) SWReg_WriteByteMask( u16Reg, u8Value, u8Mask ) ++ ++ ++#else // #if(PQ_ENABLE_CHECK == 1) ++ ++static MS_U8 _u8PQfunction = PQ_FUNC_DUMP_REG; ++ ++static void _MDrv_PQ_SetFunction(MS_U8 u8Func) ++{ ++ _u8PQfunction = u8Func; ++} ++ ++#define PQ_REG_FUNC( u16Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if (_u8PQfunction == PQ_FUNC_DUMP_REG){ \ ++ MApi_XC_WriteByteMask( (MS_U32)u16Reg, u8Value, u8Mask ); \ ++ }else{ \ ++ if ((MApi_XC_ReadByte((MS_U32)u16Reg) & u8Mask) != ((u8Value) & (u8Mask))){ \ ++ printf("[PQRegErr] "); \ ++ if (((u16Reg) >> 8) == 0x2F){ \ ++ printf("bk=%02x, ", (MS_U16)SC_BK_CURRENT); \ ++ } \ ++ else if (((u16Reg) >> 8) == 0x36){ \ ++ printf("bk=%02x, ", (MS_U16)COMB_BK_CURRENT); \ ++ } \ ++ printf("addr=%04x, mask=%02x, val=%02x[%02x]\r\n", \ ++ u16Reg, (MS_U16)u8Mask, (MS_U16)MApi_XC_ReadByte((MS_U32)u16Reg), (MS_U16)u8Value); \ ++ } \ ++ } \ ++ }while(0) ++ ++#define PQ_SWREG_FUNC( u16Reg, u8Value, u8Mask ) \ ++ do{ \ ++ if (_u8PQfunction == PQ_FUNC_DUMP_REG){ \ ++ SWReg_WriteByteMask( u16Reg, u8Value, u8Mask ); \ ++ }else{ \ ++ if (SWReg[u16Reg] & (u8Mask) != (u8Value) & (u8Mask)){ \ ++ printf("[PQSWRegErr] "); \ ++ printf("addr=%04x, mask=%02x, val=%02x[%02x]\r\n", \ ++ u16Reg, (MS_U16)u8Mask, (MS_U16)SWReg[u16Reg], (MS_U16)u8Value); \ ++ } \ ++ } \ ++ }while(0) ++ ++#endif //#if (PQ_ENABLE_CHECK) ++ ++ ++#if(PQ_ONLY_SUPPORT_BIN == 0) ++#if 0 ++static void _MDrv_PQ_Set_MLoadEn(MS_BOOL bEn) ++{ ++ MS_U16 i; ++ if(bEn == DISABLE) ++ { ++ //if spread reg, no need to use mutex, but it's ok to use mutex ++ // (because it's not MApi_XC_W2BYTE(), which has mutex already) ++ //if not spread reg, must use mutex to protect MLoad_trigger func. ++ SC_BK_STORE_MUTEX; ++ ++ if(_u16MLoadCmdCnt) ++ { ++ for(i=1; i<_u16MLoadCmdCnt; i++) ++ { ++ if(_u32MLoadCmd[i-1] == _u32MLoadCmd[i]) ++ { ++ _u16MLoadMsk[i] |= _u16MLoadMsk[i-1]; ++ _u16MLoadVal[i] |= _u16MLoadVal[i-1]; ++ } ++ } ++ #if(ENABLE_PQ_MLOAD) ++ ++ MApi_XC_MLoad_WriteCmds_And_Fire( ++ &_u32MLoadCmd[0], &_u16MLoadVal[0], &_u16MLoadMsk[0], _u16MLoadCmdCnt); ++ #endif ++ _u16MLoadCmdCnt = 0; ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++ } ++ else ++ { ++ //_u16MLoadCmdCnt = 0; ++ } ++ ++ _bMLoadEn = bEn; ++} ++#endif ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ ++static void _MDrv_PQ_PreInitLoadTableInfo(void) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ ++ MS_U16 u16IPIdx; ++ g_PQLoadTableInfo._u16CurInputSrcType = -1; ++ for( u16IPIdx = 0; u16IPIdx < MAX_IP_NUM; ++ u16IPIdx ) ++ { ++ g_PQLoadTableInfo._au8IPGroupIdx[u16IPIdx] = 0xFF; ++ } ++#endif ++ ++} ++ ++static void _MDrv_PQ_Set_LoadTableInfo_IP_Tab(MS_U16 u16IPIdx, MS_U8 u8TabIdx) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ g_PQLoadTableInfo._au8IPGroupIdx[u16IPIdx] = u8TabIdx; ++#else ++ UNUSED(u16IPIdx); ++ UNUSED(u8TabIdx); ++#endif ++ ++} ++ ++static MS_U8 _MDrv_PQ_Get_LoadTableInfo_IP_Tab(MS_U16 u16IPIdx) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ return g_PQLoadTableInfo._au8IPGroupIdx[u16IPIdx]; ++#else ++ UNUSED(u16IPIdx); ++ return 0xFF; ++#endif ++} ++ ++static void _MDrv_PQ_Set_LoadTableInfo_SrcType(MS_U16 u16SrcType) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ g_PQLoadTableInfo._u16CurInputSrcType = u16SrcType; ++#else ++ UNUSED(u16SrcType); ++#endif ++} ++ ++static MS_U16 _MDrv_PQ_Get_LoadTableInfo_SrcType(void) ++{ ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ return g_PQLoadTableInfo._u16CurInputSrcType; ++#else ++ return 0xFFFF; ++#endif ++} ++#endif ++ ++static void _MDrv_PQ_DumpGeneralRegTable(EN_IP_Info* pIP_Info) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ ++ PQ_DUMP_DBG(printf("tab: general\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: General Reg Table\r\n")); ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pIP_Info->pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ break; ++ ++ u32Addr |= NON_PM_BASE; ++ PQ_DUMP_DBG(printf("[addr=%04lx, msk=%02x, val=%02x]\r\n", u32Addr, u8Mask, u8Value)); ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ } ++} ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ ++static void _MDrv_PQ_DumpCombRegTable(EN_IP_Info* pIP_Info) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ COMB_BK_STORE; ++ ++ PQ_DUMP_DBG(printf("tab: comb\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Comb Reg Table\r\n")); ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pIP_Info->pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ break; ++ ++ u8CurBank = (MS_U8)(u32Addr >> 8); ++ if (u8CurBank != COMB_BK_CURRENT) ++ { ++ PQ_DUMP_DBG(printf("<>\r\n", u8CurBank)); ++ COMB_BK_SWITCH(u8CurBank); ++ } ++ ++ u32Addr = COMB_REG_BASE | (u32Addr & 0x00FF); ++ ++ PQ_DUMP_DBG(printf("[addr=%04x, msk=%02x, val=%02x]\r\n", (int)u32Addr, u8Mask, u8Value)); ++ ++/* ++//Only works for T4, obsolete in main trunk. ++ #if (CHIP_FAMILY_TYPE == CHIP_FAMILY_S7LD) ++ // patch Comb register H part can not be written by 16 bits riu ++ if((u32Addr == (COMB_REG_BASE + 0x47)) || ++ (u32Addr == (COMB_REG_BASE + 0x5F)) || ++ (u32Addr == (COMB_REG_BASE + 0x8F)) || ++ (u32Addr == (COMB_REG_BASE + 0xD7)) || ++ (u32Addr == (COMB_REG_BASE + 0xDF))) ++ { ++ MS_U8 u8low, u8High; ++ MS_U16 u16value; ++ ++ u8low = MApi_XC_ReadByte(u32Addr-1); ++ u8High = MApi_XC_ReadByte(u32Addr); ++ u16value = (u8High & ~u8Mask) | (u8Value & u8Mask); ++ u16value = (u16value<<8) | u16value; ++ ++ MApi_XC_Write2ByteMask(u32Addr-1, u16value, 0xFFFF); ++ PQ_REG_FUNC(u32Addr-1, u8low, 0xFF); ++ } ++ else ++ #endif ++*/ ++ { ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ } ++ ++ COMB_BK_RESTORE; ++} ++#endif ++ ++static void _MDrv_PQ_CMDQ_Fire(MS_U8 u8FmCnt) ++{ ++ MS_U16 i; ++ MS_CMDQ_CMDReg stCfg; ++ for(i=0; i<_u16CMDQCmdCnt; i++) ++ { ++ Drv_CMDQ_FillCmd(&stCfg, _u32CMDQ_Cmd[i], _u16CMDQ_Val[i], _u16CMDQ_Msk[i]); ++ Drv_CMDQ_WriteCmd(EN_CMDQ_TYPE_IP0, &stCfg, 0); ++ SCL_DBG(SCL_DBG_LV_DRVCMDQ()&EN_DBGMG_CMDQEVEL_NORMAL, "Cmdq:: ADD:%04lX, VAL:%02X, MSK:%02X, FMCnt:%02X\n" ++ ,_u32CMDQ_Cmd[i], _u16CMDQ_Val[i],_u16CMDQ_Msk[i], u8FmCnt); ++ } ++ ++ _u16CMDQCmdCnt = 0; ++ if(_bfire_En) ++ { ++ Drv_CMDQ_Fire(EN_CMDQ_TYPE_IP0,TRUE); ++ Drv_CMDQ_SetEventForFire(); ++ } ++} ++ ++static void _MDrv_PQ_DumpSclaerRegTableByData(EN_IP_Info* pIP_Info, PQ_DATA_INFO *pData) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++ MS_U8 u8CurBank = 0xff; ++ MS_U16 u16DataIdx; ++ ++ ++ SC_BK_STORE_MUTEX; ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[PQ]%s %d:: CmdqEn:%d, CmdqFmCnt=%d\n" ++ , __FUNCTION__, __LINE__, _bCMDQ_En, _u8CMDQ_FmCnt); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums) ++ { ++ PQ_ERR(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ ++ SC_BK_RESTORE_MUTEX; ++ ++ return; ++ } ++ ++ u16DataIdx = 0; ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pData->pBuf[u16DataIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ { ++ break; ++ } ++ u8CurBank = (MS_U8)(u32Addr >> 8); ++ ++ #if (SCALER_REGISTER_SPREAD) ++ u32Addr = BK_SCALER_BASE | u32Addr; ++ #else ++ if (u8CurBank != SC_BK_CURRENT) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "<>\r\n",u8CurBank); ++ SC_BK_SWITCH(u8CurBank); ++ } ++ ++ u32Addr = BK_SCALER_BASE | (u32Addr & 0x00FF); ++ #endif ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "BK =%04X, addr=%02X, msk=%02X, value=%02X\r\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)u8Value); ++ #if (ENABLE_PQ_CMDQ) ++ ++ if(_bCMDQ_En) ++ { ++ PQ_REG_CMDQ_Write(u32Addr, u8Value, u8Mask); ++ } ++ else if(_bcheckReg) ++ { ++ MS_U8 u8MaskL; ++ MS_U8 u8Value_CMDQ; ++ MS_U32 u32Addr_CMDQ; ++ u8Value_CMDQ=PQ_REG_FUNC_READ(u32Addr); ++ if((u8Value_CMDQ&u8Mask)!=(u8Value&u8Mask)) ++ { ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ (SCL_DBGERR("BK =%04X, addr=%02X, msk=%02X, value=%02X ckvalue=%02X\r\n",(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)(u8Value&u8Mask), (MS_U16)(u8Value_CMDQ))); ++ } ++ else if(((u8Value)==(0xFF))&&((u8Value_CMDQ&u8Mask)!=u8Mask)) ++ { ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ (SCL_DBGERR("BK =%04X, addr=%02X, msk=%02X, value=%02X ckvalue=%02X\r\n",(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)(u8Value&u8Mask), (MS_U16)(u8Value_CMDQ))); ++ } ++ else ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "pass BK =%04X, addr=%02X value=%02X ckvalue=%02X\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)(u8Value&u8Mask), (MS_U16)(u8Value_CMDQ&u8Mask)); ++ } ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ u32Addr_CMDQ = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ if(((u32Addr%2)&&(((u32Addr&0xFF)-1)==((u32Addr_CMDQ&0xFF))))&&(u32Addr_CMDQ != _END_OF_TBL_))//is H level and next L level ++ { ++ u8MaskL = pIP_Info->pIPTable[2]; ++ if(u8MaskL==0xFF) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[warning HL]BK =%04X, addr=%02X\r\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8),(MS_U16)(u32Addr&0xFF)); ++ } ++ } ++ pIP_Info->pIPTable-=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // roll back ++ } ++ else if(_bcheckPQsize) ++ { ++ if((u8Mask & u8Value)==0 &&(u8Value!=0)) ++ { ++ (printf("[PQ-major]BK =%04X, addr=%02X, msk=%02X, value=%02X ,msk&val=%02X \r\n",(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask,(MS_U16)(u8Value) ,(MS_U16)(u8Value&u8Mask))); ++ } ++ else if((u8Value!=0 && u8Value!=0xFF) &&(~u8Mask & u8Value)) ++ { ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[PQ-minor]BK =%04X, addr=%02X, msk=%02X, value=%02X ,msk&val=%02X \r\n" ++ ,(MS_U16)((u32Addr&0xFFFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask,(MS_U16)(u8Value) ,(MS_U16)(u8Value&u8Mask)); ++ } ++ } ++ else ++ #endif ++ { ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ u16DataIdx++; ++ if(u16DataIdx > pData->u16BufSize) ++ { ++ printf("%s %d, Data size is smaller than PQ table, idx:%d size:%d\n", ++ __FUNCTION__, __LINE__, u16DataIdx, pData->u16BufSize); ++ break; ++ } ++ } ++ ++#if (ENABLE_PQ_CMDQ) ++ if(_bCMDQ_En) ++ { ++ _MDrv_PQ_CMDQ_Fire(_u8CMDQ_FmCnt); ++ } ++#endif ++ if(u16DataIdx != pData->u16BufSize) ++ { ++ printf("%s %d, Data size is bigger than PQ table, idx:%d, size:%d\n", ++ __FUNCTION__, __LINE__, u16DataIdx, pData->u16BufSize); ++ } ++ ++ SC_BK_RESTORE_MUTEX; ++} ++ ++ ++ ++static void _MDrv_PQ_DumpScalerRegTable(EN_IP_Info* pIP_Info) ++{ ++ MS_U32 u32Addr; ++ MS_U8 u8Mask; ++ MS_U8 u8Value; ++#if (!SCALER_REGISTER_SPREAD) ++ MS_U8 u8CurBank; ++#endif ++ ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ pthread_mutex_lock(&_PQ_MLoad_Mutex); ++ #endif ++#endif ++ ++ SC_BK_STORE_MUTEX; ++ PQ_DUMP_DBG(printf("tab: sc\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums) ++ { ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ ++ SC_BK_RESTORE_MUTEX; ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++ #endif ++#endif ++ ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (pIP_Info->pIPTable[0]<<8) + pIP_Info->pIPTable[1]; ++ u8Mask = pIP_Info->pIPTable[2]; ++ u8Value = pIP_Info->pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabIdx]; ++ ++ if (u32Addr == _END_OF_TBL_) // check end of table ++ break; ++#if (!SCALER_REGISTER_SPREAD) ++ u8CurBank = (MS_U8)(u32Addr >> 8); ++#endif ++ PQ_DUMP_DBG(printf("XC bk =%x, addr=%x, msk=%x, value=%x\r\n", (MS_U16)((u32Addr&0xFF00)>>8), (MS_U16)(u32Addr&0xFF), (MS_U16)u8Mask, (MS_U16)u8Value)); ++#if(ENABLE_PQ_MLOAD) ++ if(_bMLoadEn) ++ { ++ //printf("MLad: %lx, %x, %x\r\n", u32Addr, u8Value, u8Mask); ++ PQ_REG_MLOAD_WRITE_CMD(u32Addr, u8Value, u8Mask); ++ //PQ_REG_MLOAD_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ else ++#endif ++ { ++ #if (SCALER_REGISTER_SPREAD) ++ u32Addr = BK_SCALER_BASE | u32Addr; ++ #else ++ if (u8CurBank != SC_BK_CURRENT) ++ { ++ PQ_DUMP_DBG(printf("<>\r\n", u8CurBank)); ++ SC_BK_SWITCH(u8CurBank); ++ } ++ ++ u32Addr = BK_SCALER_BASE | (u32Addr & 0x00FF); ++ #endif ++ PQ_REG_FUNC(u32Addr, u8Value, u8Mask); ++ } ++ pIP_Info->pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+pIP_Info->u8TabNums); // next ++ } ++ ++ ++ SC_BK_RESTORE_MUTEX; ++ ++#ifdef MSOS_TYPE_LINUX ++ #if(ENABLE_PQ_MLOAD) ++ pthread_mutex_unlock(&_PQ_MLoad_Mutex); ++ #endif ++#endif ++} ++ ++static void _MDrv_PQ_DumpFilterTable(EN_IP_Info* pIP_Info) ++{ ++ ++ PQ_DUMP_FILTER_DBG(printf("tab: sram\r\n")); ++ if (pIP_Info->u8TabIdx >= pIP_Info->u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: SRAM Table\r\n")); ++ return; ++ } ++ PQ_DUMP_FILTER_DBG(printf("pIP_Info->u8TabType: %u\r\n",pIP_Info->u8TabType)); ++ switch(pIP_Info->u8TabType) ++ { ++ case PQ_TABTYPE_SRAM_COLOR_INDEX: ++ Hal_PQ_set_sram_color_index_table(_PQTableInfo.eWin, SC_FILTER_SRAM_COLOR_INDEX, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_COLOR_INDEX)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_SNR: ++ Hal_PQ_set_sram_color_gain_snr_table(_PQTableInfo.eWin, SC_FILTER_SRAM_COLOR_GAIN_SNR, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_COLOR_GAIN_SNR)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM_COLOR_GAIN_DNR: ++ Hal_PQ_set_sram_color_gain_snr_table(_PQTableInfo.eWin, SC_FILTER_SRAM_COLOR_GAIN_DNR, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_COLOR_GAIN_DNR)])); ++ break; ++ ++ case PQ_TABTYPE_VIP_ICC_CRD_SRAM: ++ Hal_PQ_set_sram_icc_crd_table(_PQTableInfo.eWin, SC_FILTER_SRAM_ICC_CRD, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_ICC_CRD)])); ++ break; ++ ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ Hal_PQ_set_sram_ihc_crd_table(_PQTableInfo.eWin, SC_FILTER_SRAM_IHC_CRD, (void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_SRAM_IHC_CRD)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM1: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM1 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM1)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM2: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM2 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM2)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM3: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM3 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM3)])); ++ break; ++ ++ case PQ_TABTYPE_SRAM4: ++ Hal_PQ_set_yc_sram(FILTER_SRAM_SC1, SC_FILTER_Y_SRAM4 ,(void *)((MS_U32)&pIP_Info->pIPTable[pIP_Info->u8TabIdx * Hal_PQ_get_sram_size(SC_FILTER_Y_SRAM4)])); ++ break; ++ ++ default: ++ printf("[PQ]Unknown sram type %u\r\n", pIP_Info->u8TabType); ++ break; ++ } ++ PQ_DUMP_FILTER_DBG(printf("tab load finish\r\n")); ++} ++ ++static void _MDrv_PQ_ClearTableIndex(void) ++{ ++ ++ _u8ICC_CRD_Table = 0xFF; ++ _u8IHC_CRD_Table = 0xFF; ++ _u8SRAM1Table = 0xFF; ++ _u8SRAM2Table = 0xFF; ++ _u8SRAM3Table =0xFF; ++ _u8SRAM4Table = 0xFF; ++ _u8CSRAM1Table = 0xFF; ++ _u8CSRAM2Table = 0xFF; ++ _u8CSRAM3Table = 0xFF; ++ _u8CSRAM4Table = 0xFF; ++} ++ ++ ++static void _MDrv_PQ_DumpTable(EN_IP_Info* pIP_Info) ++{ ++ // to save loading SRAM table time, SRAM are only downloaded ++ // when current SRAM table is different to previous SRAM table ++ if (pIP_Info->pIPTable == NULL) ++ { ++ PQ_DUMP_DBG(printf("NULL Table\r\n")); ++ return; ++ } ++ PQ_DUMP_DBG(printf("Table Type =%x, Index =%x\r\n", (MS_U16)pIP_Info->u8TabType, (MS_U16)pIP_Info->u8TabIdx)); ++ switch(pIP_Info->u8TabType ) ++ { ++ ++ case PQ_TABTYPE_SCALER: ++ _MDrv_PQ_DumpScalerRegTable(pIP_Info); ++ break; ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ case PQ_TABTYPE_COMB: ++ _MDrv_PQ_DumpCombRegTable(pIP_Info); ++ break; ++#endif ++ ++ case PQ_TABTYPE_SRAM1: ++ if (_u8SRAM1Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old sram1: %u, new sram1: %u\r\n", ++ (MS_U16)_u8SRAM1Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM1Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram1: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ case PQ_TABTYPE_SRAM2: ++ if (_u8SRAM2Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old sram2: %u, new sram2: %u\r\n", ++ (MS_U16)_u8SRAM2Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM2Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram2: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_SRAM3: ++ if (_u8SRAM3Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old sram3: %u, new sram3: %u\r\n", ++ (MS_U16)_u8SRAM3Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM3Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram3: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_SRAM4: ++ if (_u8SRAM4Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old s ram4: %u, new sram4: %u\r\n", ++ (MS_U16)_u8SRAM4Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8SRAM4Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram4: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ ++ case PQ_TABTYPE_C_SRAM1: ++ if (_u8CSRAM1Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram1: %u, new Csram1: %u\r\n", ++ (MS_U16)_u8CSRAM1Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM1Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same Csram1: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ case PQ_TABTYPE_C_SRAM2: ++ if (_u8CSRAM2Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram2: %u, new Csram2: %u\r\n", ++ (MS_U16)_u8CSRAM2Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM2Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same Csram2: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_C_SRAM3: ++ if (_u8CSRAM3Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram3: %u, new Csram3: %u\r\n", ++ (MS_U16)_u8CSRAM3Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM3Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same sram3: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_C_SRAM4: ++ if (_u8CSRAM4Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old Csram4: %u, new Csram4: %u\r\n", ++ (MS_U16)_u8CSRAM4Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8CSRAM4Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ } ++ else ++ { ++ PQ_DUMP_FILTER_DBG(printf("use the same Csram4: %u\r\n", (MS_U16)pIP_Info->u8TabIdx)); ++ } ++ break; ++ ++ case PQ_TABTYPE_VIP_ICC_CRD_SRAM: ++ if( _u8ICC_CRD_Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old ICC_CRD_SRAM: %u, new ICC_CRD_SRAM: %u\r\n", ++ (MS_U16)_u8ICC_CRD_Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8ICC_CRD_Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ ++ } ++ break; ++ ++ case PQ_TABTYPE_VIP_IHC_CRD_SRAM: ++ if( _u8IHC_CRD_Table != pIP_Info->u8TabIdx) ++ { ++ PQ_DUMP_FILTER_DBG(printf("old IHC_CRD_SRAM: %u, new IHC_CRD_SRAM: %u\r\n", ++ (MS_U16)_u8IHC_CRD_Table, (MS_U16)pIP_Info->u8TabIdx)); ++ _u8IHC_CRD_Table = pIP_Info->u8TabIdx; ++ _MDrv_PQ_DumpFilterTable(pIP_Info); ++ ++ } ++ break; ++ ++ case PQ_TABTYPE_GENERAL: ++ _MDrv_PQ_DumpGeneralRegTable(pIP_Info); ++ break; ++ ++ case PQ_TABTYPE_PICTURE_1: ++ case PQ_TABTYPE_PICTURE_2: ++ break; ++ ++ default: ++ PQ_DUMP_DBG(printf("[PQ]DumpTable:unknown type: %u\r\n", pIP_Info->u8TabType)); ++ break; ++ } ++} ++ ++// return total IP count ++static MS_U16 _MDrv_PQ_GetIPNum(void) ++{ ++ PQ_DBG(printf("[PQ]IPNum=%u\r\n",_PQTableInfo.u8PQ_IP_Num)); ++ return (MS_U16)_PQTableInfo.u8PQ_IP_Num; ++} ++ ++// return total table count of given IP ++static MS_U16 _MDrv_PQ_GetTableNum(MS_U8 u8PQIPIdx) ++{ ++ PQ_DBG(printf("[PQ]TabNum=%u\r\n", _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabNums)); ++ return (MS_U16)_PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabNums; ++} ++ ++// return current used table index of given IP ++static MS_U16 _MDrv_PQ_GetCurrentTableIndex(MS_U8 u8PQIPIdx) ++{ ++ PQ_DBG(printf("[PQ]CurrTableIdx=%u\r\n", _u8PQTabIdx[u8PQIPIdx])); ++ return (MS_U16)_u8PQTabIdx[u8PQIPIdx]; ++} ++ ++static MS_U16 _MDrv_PQ_GetTableIndex(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx) ++{ ++ if (u16PQSrcType >=_PQTableInfo.u8PQ_InputType_Num){ ++ PQ_DBG(printf("[PQ]invalid input type\r\n")); ++ return PQ_IP_NULL; ++ } ++ if (u8PQIPIdx >= _PQTableInfo.u8PQ_IP_Num){ ++ PQ_DBG(printf("[PQ]invalid ip type\r\n")); ++ return PQ_IP_NULL; ++ } ++ ++ PQ_DBG(printf("[PQ]TableIdx=%u\r\n",(MS_U16)_PQTableInfo.pQuality_Map_Aray[u16PQSrcType * _PQTableInfo.u8PQ_IP_Num + u8PQIPIdx])); ++ ++ return (MS_U16)_PQTableInfo.pQuality_Map_Aray[u16PQSrcType * _PQTableInfo.u8PQ_IP_Num + u8PQIPIdx]; ++} ++ ++static EN_IP_Info _MDrv_PQ_GetTable(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ _u8PQTabIdx[u8PQIPIdx] = u8TabIdx; ++ if (u8TabIdx != PQ_IP_NULL && u8TabIdx != PQ_IP_COMM) { ++ ip_Info.pIPTable = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].pIPTable; ++ ip_Info.u8TabNums = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabNums; ++ ip_Info.u8TabType = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabType; ++ ip_Info.u8TabIdx = u8TabIdx; ++ } ++ else if (u8TabIdx == PQ_IP_COMM) { ++ ip_Info.pIPTable = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].pIPCommTable; ++ ip_Info.u8TabNums = 1; ++ ip_Info.u8TabType = _PQTableInfo.pIPTAB_Info[u8PQIPIdx].u8TabType; ++ ip_Info.u8TabIdx = 0; ++ } ++ else { ++ ip_Info.pIPTable = 0; ++ ip_Info.u8TabNums = 0; ++ ip_Info.u8TabType = 0; ++ ip_Info.u8TabIdx = 0; ++ } ++ return ip_Info; ++} ++ ++#if PQ_ENABLE_UNUSED_FUNC ++ ++static void _MDrv_PQ_LoadTableData(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, MS_U8 *pTable, MS_U16 u16TableSize) ++{ ++ EN_IP_Info ip_Info; ++ MS_U32 u32Addr; ++ MS_U16 u16Idx = 0; ++ ++ ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ if (ip_Info.u8TabIdx >= ip_Info.u8TabNums){ ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ return; ++ } ++ ++ while (1) ++ { ++ u32Addr = (ip_Info.pIPTable[0]<<8) + ip_Info.pIPTable[1]; ++ pTable[u16Idx++] = ip_Info.pIPTable[REG_ADDR_SIZE+REG_MASK_SIZE+ip_Info.u8TabIdx]; ++ ++ if(u16Idx > u16TableSize || u32Addr == _END_OF_TBL_) ++ break; ++ ++ ip_Info.pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+ip_Info.u8TabNums); // next ++ } ++} ++ ++static void _MDrv_PQ_LoadTable(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ _MDrv_PQ_DumpTable(&ip_Info); ++#if(ENABLE_PQ_LOAD_TABLE_INFO) ++ _MDrv_PQ_Set_LoadTableInfo_IP_Tab(u8PQIPIdx, u8TabIdx); ++#endif ++ ++} ++ ++static MS_BOOL _MDrv_PQ_LoadPictureSetting(MS_U8 u8TabIdx, MS_U8 u8PQIPIdx, void *pTable, MS_U16 u16TableSize) ++{ ++ EN_IP_Info ip_Info; ++ MS_U32 u32Addr; ++ ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ if (ip_Info.u8TabIdx >= ip_Info.u8TabNums) ++ { ++ PQ_DUMP_DBG(printf("[PQ]IP_Info error: Scaler Reg Table\r\n")); ++ return FALSE; ++ } ++ ++ //printf("TabType:%d TabNums:%d, TabIdx:%d addr:%x \r\n", ip_Info.u8TabType, ip_Info.u8TabNums, ip_Info.u8TabIdx, ip_Info.pIPTable); ++ ++ u32Addr = u16TableSize * ip_Info.u8TabIdx; ++ if(ip_Info.u8TabType == PQ_TABTYPE_PICTURE_1) ++ { ++ MS_U8 *pu8PQTbl = (MS_U8 *)ip_Info.pIPTable; ++ MsOS_Memcpy((MS_U8 *)pTable, &pu8PQTbl[u32Addr], sizeof(MS_U8)*u16TableSize); ++ } ++ else if(ip_Info.u8TabType == PQ_TABTYPE_PICTURE_2) ++ { ++ MS_U16 *pu16PQTbl = (MS_U16 *)ip_Info.pIPTable; ++ MsOS_Memcpy((MS_U16 *)pTable, &pu16PQTbl[u32Addr], sizeof(MS_U16)*u16TableSize); ++ ++ } ++ else ++ { ++ return FALSE; ++ } ++ ++#if 0 ++{ ++ MS_U16 u16Idx = 0; ++ for(u16Idx=0; u16Idx= PQ_TABTYPE_SRAM1 && ip_Info.u8TabType <= PQ_TABTYPE_C_SRAM1) || ++ ip_Info.u8TabType == PQ_TABTYPE_VIP_IHC_CRD_SRAM || ++ ip_Info.u8TabType == PQ_TABTYPE_VIP_ICC_CRD_SRAM) ++ { ++ continue; ++ } ++ #endif ++ _MDrv_PQ_DumpTable(&ip_Info); ++ } ++} ++ ++ ++static MS_U8 _MDrv_PQ_GetXRuleTableIndex(MS_U8 u8XRuleType, MS_U8 u8XRuleIdx, MS_U8 u8XRuleIP) ++{ ++ MS_U8 *pArray = _PQTableInfo.pXRule_Array[u8XRuleType]; ++ return pArray[((MS_U16)u8XRuleIdx) * _PQTableInfo.u8PQ_XRule_IP_Num[u8XRuleType] + u8XRuleIP]; ++} ++ ++static MS_U8 _MDrv_PQ_GetXRuleIPIndex(MS_U8 u8XRuleType, MS_U8 u8XRuleIP) ++{ ++ MS_U8 *pArray = _PQTableInfo.pXRule_IP_Index[u8XRuleType]; ++ return pArray[u8XRuleIP]; ++} ++ ++static MS_U8 _MDrv_PQ_GetXRuleIPNum(MS_U8 u8XRuleType) ++{ ++ return _PQTableInfo.u8PQ_XRule_IP_Num[u8XRuleType]; ++} ++ ++static MS_U8 _MDrv_PQ_GetGRule_LevelIndex(MS_U8 u8GRuleType, MS_U8 u8GRuleLvlIndex) ++{ ++ MS_U8 *pArray = _PQTableInfo.pGRule_Level[u8GRuleType]; ++ return pArray[u8GRuleLvlIndex]; ++} ++ ++static MS_U8 _MDrv_PQ_GetGRule_IPIndex(MS_U8 u8GRuleType, MS_U8 u8GRuleIPIndex) ++{ ++ MS_U8 *pArray = _PQTableInfo.pGRule_IP_Index[u8GRuleType]; ++ return pArray[u8GRuleIPIndex]; ++} ++ ++static MS_U8 _MDrv_PQ_GetGRule_TableIndex(MS_U8 u8GRuleType, MS_U8 u8PQSrcType, MS_U8 u8PQ_NRIdx, MS_U8 u8GRuleIPIndex) ++{ ++// return _PQTableInfo.pGRule_Array[u8PQSrcType][u8PQ_NRIdx][u8GRuleIPIndex]; ++ MS_U16 u16index; ++ MS_U8 *pArray = _PQTableInfo.pGRule_Array[u8GRuleType]; ++ ++ u16index = ((MS_U16)u8PQSrcType) * _PQTableInfo.u8PQ_GRule_Num[u8GRuleType] * _PQTableInfo.u8PQ_GRule_IPNum[u8GRuleType] + ++ ((MS_U16)u8PQ_NRIdx) * _PQTableInfo.u8PQ_GRule_IPNum[u8GRuleType] + ++ u8GRuleIPIndex; ++ return pArray[u16index]; ++} ++#endif ++ ++static void _MDrv_PQ_Set_CmdqCfg(PQ_CMDQ_CONFIG CmdqCfg) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[PQ]%s %d:: En=%d, FmCnt=%d\n",__FUNCTION__, __LINE__, CmdqCfg.bEnFmCnt, CmdqCfg.u8FmCnt); ++#if (ENABLE_PQ_CMDQ) ++ _bCMDQ_En = CmdqCfg.bEnFmCnt; ++ _u8CMDQ_FmCnt = CmdqCfg.bEnFmCnt ? CmdqCfg.u8FmCnt : 0; ++ _bfire_En = CmdqCfg.bfire; ++ _u16CMDQCmdCnt = 0; ++#endif ++} ++static MS_U16 _MDrv_PQ_GetIPRegCount(MS_U16 u16PQSrcType,MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ MS_U8 u8TabIdx; ++ MS_U32 u32Addr; ++ MS_U16 u16DataIdx = 0; ++ ++ u8TabIdx = (MS_U8)_MDrv_PQ_GetTableIndex(u16PQSrcType, u8PQIPIdx); ++ ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[PQ]%s %d::SrcType=%d, IPIdx=%d, TabType=%d\r\n" ++ ,__FUNCTION__, __LINE__, u16PQSrcType, u8PQIPIdx, ip_Info.u8TabType); ++ while (1) ++ { ++ u32Addr = (ip_Info.pIPTable[0]<<8) + ip_Info.pIPTable[1]; ++ if(u32Addr == _END_OF_TBL_) // check end of table ++ { ++ break; ++ } ++ ip_Info.pIPTable+=(REG_ADDR_SIZE+REG_MASK_SIZE+ip_Info.u8TabNums); // next ++ u16DataIdx++; ++ } ++ return u16DataIdx; ++} ++static void _MDrv_PQ_Check_Type(PQ_CHECK_TYPE EnCheck) ++{ ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[PQ]%s %d:: En=%d\n", __FUNCTION__, __LINE__, EnCheck); ++ if(EnCheck == PQ_CHECK_REG) ++ { ++ _bcheckReg = 1; ++ } ++ else if(EnCheck == PQ_CHECK_SIZE) ++ { ++ _bcheckPQsize= 1; ++ } ++ else if(EnCheck == PQ_CHECK_OFF) ++ { ++ _bcheckReg = 0; ++ _bcheckPQsize= 0; ++ } ++} ++ ++static void _MDrv_PQ_SetPQDebugFlag(MS_U8 u8PQIPIdx) ++{ ++ switch (u8PQIPIdx) ++ { ++ case PQ_IP_MCNR_Main ... PQ_IP_NLM_Main: ++ case PQ_IP_XNR_Main: ++ gu8debugflag = EN_DBGMG_PQLEVEL_BEFORECROP; ++ break; ++ ++ case PQ_IP_ColorEng_422to444_Main ... PQ_IP_ColorEng_444to422_Main: ++ gu8debugflag = EN_DBGMG_PQLEVEL_COLORENG; ++ break; ++ case PQ_IP_VIP_HLPF_Main ... PQ_IP_VIP_UVC_Main: ++ case PQ_IP_VIP_ACK_Main ... PQ_IP_VIP_YCbCr_Clip_Main: ++ gu8debugflag = EN_DBGMG_PQLEVEL_VIPY; ++ break; ++ case PQ_IP_VIP_FCC_full_range_Main ... PQ_IP_VIP_IBC_SETTING_Main: ++ gu8debugflag = EN_DBGMG_PQLEVEL_VIPC; ++ break; ++ ++ case PQ_IP_YEE_Main ... PQ_IP_UV_ADJUST_Main: ++ gu8debugflag = EN_DBGMG_PQLEVEL_AIP; ++ break; ++ ++ case PQ_IP_YC10_UVM10_Main ... PQ_IP_YUV_Gamma_Main: ++ gu8debugflag = EN_DBGMG_PQLEVEL_AIPPOST; ++ break; ++ default: ++ gu8debugflag = EN_DBGMG_PQLEVEL_ELSE; ++ break; ++ } ++ ++} ++ ++static void _MDrv_PQ_LoadTableByData(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx, PQ_DATA_INFO *pData) ++{ ++ EN_IP_Info ip_Info; ++ MS_U8 u8TabIdx; ++ ++ u8TabIdx = (MS_U8)_MDrv_PQ_GetTableIndex(u16PQSrcType, u8PQIPIdx); ++ _MDrv_PQ_SetPQDebugFlag(u8PQIPIdx); ++ ip_Info = _MDrv_PQ_GetTable(u8TabIdx, u8PQIPIdx); ++ SCL_DBG(SCL_DBG_LV_DRVPQ() &gu8debugflag, "[PQ]%s %d::SrcType=%d, IPIdx=%d, TabType=%d\r\n" ++ ,__FUNCTION__, __LINE__, u16PQSrcType, u8PQIPIdx, ip_Info.u8TabType); ++ ++ ++ switch(ip_Info.u8TabType) ++ { ++ case PQ_TABTYPE_SCALER: ++ _MDrv_PQ_DumpSclaerRegTableByData(&ip_Info, pData); ++ break; ++ ++ default: ++ printf("[PQ]%s %d: Unsupport TabType:%d\n", __FUNCTION__, __LINE__, ip_Info.u8TabType); ++ break; ++ } ++} ++ ++ ++static void _MDrv_PQ_LoadTableBySrcType(MS_U16 u16PQSrcType, MS_U8 u8PQIPIdx) ++{ ++ EN_IP_Info ip_Info; ++ MS_U8 QMIPtype_size,i; ++ MS_U8 u8TabIdx = 0; ++ //XC_ApiStatusEx stXCStatusEx; Ryan ++ ++ if (u8PQIPIdx==PQ_IP_ALL) ++ { ++ QMIPtype_size=_PQTableInfo.u8PQ_IP_Num; ++ u8PQIPIdx=0; ++ } ++ else ++ { ++ QMIPtype_size=1; ++ } ++ ++ //for debug ++ //msAPI_Scaler_SetBlueScreen(DISABLE, 0x00); ++ //MApi_XC_GenerateBlackVideo(FALSE); ++ ++ for(i=0; i> 8)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \ ++ } \ ++ RIU_MACRO_END ++ ++#define MDrv_Write2Byte_ve( u32Reg, u16Val ) \ ++ RIU_MACRO_START \ ++ if ( ((u32Reg) & 0x01) ) \ ++ { \ ++ RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ ++ RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \ ++ } \ ++ RIU_MACRO_END ++ ++ ++#define MDrv_Write3Byte( u32Reg, u32Val ) \ ++ RIU_MACRO_START \ ++ if ((u32Reg) & 0x01) \ ++ { \ ++ RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ ++ RIU_WRITE_2BYTE( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ ++ } \ ++ RIU_MACRO_END ++ ++#define MDrv_Write4Byte( u32Reg, u32Val ) \ ++ RIU_MACRO_START \ ++ if ((u32Reg) & 0x01) \ ++ { \ ++ RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ ++ RIU_WRITE_2BYTE( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ ++ RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ ++ } \ ++ else \ ++ { \ ++ RIU_WRITE_2BYTE( (u32Reg) <<1 , u32Val); \ ++ RIU_WRITE_2BYTE( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ ++ } \ ++ RIU_MACRO_END ++ ++#define MDrv_WriteByteMask( u32Reg, u8Val, u8Msk ) \ ++ RIU_MACRO_START \ ++ RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ ++ RIU_MACRO_END ++//============================================================= ++// Just for Scaler ++ ++#define SC_R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1) & (u16mask) ) ) ++#define SC_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ ( ( RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) )) ++#define SC_W2BYTE( u32Reg, u16Val)\ ++ ( ( RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1 , u16Val ) ) ) ++#define SC_R4BYTE( u32Reg )\ ++ ( ( RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + 2 ) << 1 )) << 16)) ++#define SC_W4BYTE( u32Reg, u32Val)\ ++ RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ ++ RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) ) ++#define SC_R2BYTE( u32Reg ) \ ++ ( ( RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFFFF) ) <<1 ) ) ) ++ ++ ++//============================================================= ++//General ( Make sure u32Reg is not ODD ++#define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) ++#define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) ++#define W4BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ ++ RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) ++#define R4BYTE( u32Reg )\ ++ ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) ++ ++#define R2BYTEMSK( u32Reg, u16mask)\ ++ ( ( RIU_READ_2BYTE( (u32Reg)<< 1) & u16mask ) ) ++ ++#define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ ++ RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ++#define W2BYTEMSK1( u32Reg, u16Val, u16Mask)\ ++ ( ( RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ) ) ++#define W3BYTE( u32Reg, u32Val)\ ++ ( { RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ ++ RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); } ) ++ ++//------------------------------------------------------------------------------------------------- ++// Type and Structure ++//------------------------------------------------------------------------------------------------- ++//------------------------------------------------------------------------------------------------- ++// Function and Variable ++//------------------------------------------------------------------------------------------------- ++#define MApi_XC_ReadByte(u32Reg) MDrv_ReadByte(u32Reg) ++#define MApi_XC_WriteByteMask(u32Reg, u8Val, u8Msk) MDrv_WriteByteMask( u32Reg, u8Val, u8Msk ) ++#define MApi_XC_WriteByte(u32Reg, u8Val) MDrv_WriteByte( u32Reg, u8Val ) ++ ++#define MApi_XC_R2BYTE(u32Reg) SC_R2BYTE( u32Reg ) ++#define MApi_XC_R2BYTEMSK(u32Reg, u16mask) SC_R2BYTEMSK( u32Reg, u16mask) ++ ++#define MApi_XC_W2BYTE(u32Reg, u16Val) SC_W2BYTE( u32Reg, u16Val) ++#define MApi_XC_W2BYTEMSK(u32Reg, u16Val, u16mask) SC_W2BYTEMSK( u32Reg, u16Val, u16mask) ++ ++#endif +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/include/msAPI_Scaler_Adaptive.h b/drivers/mstar/scl/infinity3/src/mxlib/pq/include/msAPI_Scaler_Adaptive.h +new file mode 100644 +index 00000000..5d33151f +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/include/msAPI_Scaler_Adaptive.h +@@ -0,0 +1,76 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++#ifndef DRV_SCALER_ADAPTIVE_H ++#define DRV_SCALER_ADAPTIVE_H ++ ++/******************************************************************************/ ++/* Macro */ ++/* ****************************************************************************/ ++#ifdef __cplusplus ++extern "C" ++{ ++#endif ++ ++/******************************************************************************/ ++/* definition */ ++/* ****************************************************************************/ ++ ++#ifdef DRV_SCALER_NR_C ++#define INTERFACE ++#else ++#define INTERFACE extern ++#endif ++ ++/******************************************************************************/ ++/* Global Variables */ ++/******************************************************************************/ ++ ++//************************************************************************* ++// Enums ++//************************************************************************* ++ ++//************************************************************************* ++// Structures ++//************************************************************************* ++typedef enum ++{ ++ Level_Low=0, ++ Level_MID, ++ Level_High, ++ ++ MAX_Level ++}XC_CTRL_LEVEL; ++ ++/********************************************************************************/ ++/* Function Prototypes */ ++/********************************************************************************/ ++INTERFACE MS_U8 MApi_XC_GetCurrentMotionValue(void); ++INTERFACE void MApi_XC_AdaptiveTuning(void); ++INTERFACE void MApi_XC_FilmMode_AnyCandence_Enable(MS_BOOL bEnable); ++INTERFACE void MApi_XC_DBK_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel); ++INTERFACE void MApi_XC_DMS_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel); ++INTERFACE void MApi_XC_SotreCurrentValue(void); ++INTERFACE void MApi_XC_ReSotreToDefault(void); ++ ++#undef INTERFACE ++#ifdef __cplusplus ++} ++#endif ++ ++ ++#endif /* DRV_SCALER_ADAPTIVE_H */ +diff --git a/drivers/mstar/scl/infinity3/src/mxlib/pq/msAPI_Scaler_Adaptive.c b/drivers/mstar/scl/infinity3/src/mxlib/pq/msAPI_Scaler_Adaptive.c +new file mode 100644 +index 00000000..91ee1a3f +--- /dev/null ++++ b/drivers/mstar/scl/infinity3/src/mxlib/pq/msAPI_Scaler_Adaptive.c +@@ -0,0 +1,4406 @@ ++// $Change: 616729 $ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2008-2009 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// ("MStar Confidential Information") by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++/// ++/// file drvTEMP.c ++/// @brief TEMP Driver Interface ++/// @author MStar Semiconductor Inc. ++/////////////////////////////////////////////////////////////////////////////////////////////////// ++#define DRV_SCALER_ADAPTIVE_C ++ ++#ifdef UTOPIA ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Include Files ++//------------------------------------------------------------------------------------------------- ++#include ++ ++// Common Definition ++#include "MsCommon.h" ++#include "MsOS.h" ++#include "MsTypes.h" ++ ++// Internal Definition ++#include "color_reg.h" ++#include "color_SC1_reg.h" ++#include "color_SC2_reg.h" ++ ++#include "drvXC_IOPort.h" ++ ++#include "apiXC.h" ++//#include "apiXC_Dlc.h" ++#include "msAPI_Scaler_Adaptive.h" ++ ++#ifndef UNUSED //to avoid compile warnings... ++#define UNUSED(var) (void)((var) = (var)) ++#endif ++ ++//------------------------------------------------------------------------------------------------- ++// Driver Compiler Options ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Defines ++//------------------------------------------------------------------------------------------------- ++#define DRVSCA_DBG(x) //x ++#define DBG_DEFEATHERING 0 ++#define DBG_DEFLICKERING 0 ++#define DBG_DEBOUNCING 0 ++#define DBG_DYNAMIC_SNR 0 ++#define DBG_DYNAMIC_DNR 0 ++ ++// DeFeathering ++#define MDP_CNT 2 ++#define ENABLE_MDP 0 //Motion decrase progressively enable ++ ++#define DEFETHERING_LV1_TH 30000 ++#define DEFETHERING_LV2_TH 5000 ++#define DEFETHERING_LV3_TH 2000 ++#define DEFETHERING_LV1_CNT 25 ++#define DEFETHERING_LV2_CNT 20 ++#define DEFETHERING_LV3_CNT 5 ++ ++#define SST_STATIC_CORE_TH_LV1_VALUE 0x14 //ryan update ++#define SST_STATIC_CORE_TH_LV2_VALUE 0x0C //ryan update ++#define SST_STATIC_CORE_TH_LV3_VALUE 0x06 //ryan update ++#define SST_STATIC_CORE_TH_LV4_VALUE 0x00 //ryan update ++ ++// DeFlickering ++#define DEFLICKERING_TH 52000 ++#define DEFLICKERING_CNT 150 ++ ++// DeBouncing ++#define DEBOUNCING_TH 35000 ++#define DEBOUNCING_CNT 10 ++ ++// Dynamic SNR ++#define DYNAMIC_SNR_TH 2000 ++#define DYNAMIC_SNR_CNT 30 ++ ++// Dynamic DNR ++//#define DYNAMIC_DNR_TH 6000 ++ ++#define DNR_TABLEY_0L_Zero_VALUE 0xDD ++#define DNR_TABLEY_0H_Zero_VALUE 0xBD ++#define DNR_TABLEY_1L_Zero_VALUE 0x79 ++#define DNR_TABLEY_1H_Zero_VALUE 0x35 ++#define DNR_TABLEY_2L_Zero_VALUE 0x11 ++#define DNR_TABLEY_2H_Zero_VALUE 0x00 ++#define DNR_TABLEY_3L_Zero_VALUE 0x00 ++#define DNR_TABLEY_3H_Zero_VALUE 0x00 ++ ++#define DNR_TABLEY_0L_LV2_VALUE 0xCC ++#define DNR_TABLEY_0H_LV2_VALUE 0xAC ++#define DNR_TABLEY_1L_LV2_VALUE 0x68 ++#define DNR_TABLEY_1H_LV2_VALUE 0x24 ++#define DNR_TABLEY_2L_LV2_VALUE 0x00 ++#define DNR_TABLEY_2H_LV2_VALUE 0x00 ++#define DNR_TABLEY_3L_LV2_VALUE 0x00 ++#define DNR_TABLEY_3H_LV2_VALUE 0x00 ++ ++#define DNR_TABLEY_0L_LV3_VALUE 0x67 ++#define DNR_TABLEY_0H_LV3_VALUE 0x45 ++#define DNR_TABLEY_1L_LV3_VALUE 0x33 ++#define DNR_TABLEY_1H_LV3_VALUE 0x22 ++#define DNR_TABLEY_2L_LV3_VALUE 0x11 ++#define DNR_TABLEY_2H_LV3_VALUE 0x00 ++#define DNR_TABLEY_3L_LV3_VALUE 0x00 ++#define DNR_TABLEY_3H_LV3_VALUE 0x00 ++ ++// Dynamic Film 22 ++#define DYNAMIC_FILM22_TH 520000 ++ ++extern MS_U16 _u16PQSrcType_DBK_Detect[PQ_MAX_WINDOW]; //For Auto_DBK SW driver used ++static MS_U16 _u16PQPre_SrcType = 255; //For Auto_DBK SW driver used ++static MS_BOOL data_read = true; //For Auto_DBK SW driver used ++ ++ ++#define Auto_DeBlock_En TRUE ++//------------------------------------------------------------------------------------------------- ++// Local Structurs ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++static MS_BOOL g_bAnyCandenceEnable = TRUE; ++ ++//------------------------------------------------------------------------------------------------- ++// Local Variables ++//------------------------------------------------------------------------------------------------- ++ ++//------------------------------------------------------------------------------------------------- ++// Debug Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Local Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++ ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8)MApi_XC_R2BYTEMSK(REG_SC_BK22_7C_L, 0xFF); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl2(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8)(MApi_XC_R2BYTEMSK(REG_SC_BK22_7C_L, 0xFF00) >> 8); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl3(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8) (MApi_XC_R2BYTEMSK(REG_SC_BK30_01_L, 0x8000) >> 8); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Get control register for adaptive tuning function ++///@return MS_U8: Control status ++/******************************************************************************/ ++MS_U8 MDrv_SC_get_adaptive_ctrl4(void) ++{ ++ MS_U8 u8Ctrl; ++ ++ u8Ctrl = (MS_U8)(MS_U8)MApi_XC_R2BYTEMSK(REG_SC_BK22_7E_L, 0xFF); ++ ++ return u8Ctrl; ++} ++ ++/******************************************************************************/ ++///Read motion value (F2 motion status) ++///@return MS_U8: Motion value ++/******************************************************************************/ ++MS_U32 MDrv_SC_read_motion_value1(void) ++{ ++ ++ MS_U32 u32MotionValue; ++ MS_U32 u32RegMadi_1C, u32RegMadi_1B, u32RegMadi_1A; ++ ++ u32RegMadi_1C = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0E_L, 0x3F); ++ u32RegMadi_1B = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0D_L, 0xFF00); ++ u32RegMadi_1A = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0D_L, 0x00FF); ++ ++ u32RegMadi_1C = u32RegMadi_1C * 0x10000UL; ++ ++ u32MotionValue = (u32RegMadi_1C + u32RegMadi_1B + u32RegMadi_1A) ; ++ ++ DRVSCA_DBG(printf("MotionValue = 0x%lx\n", u32MotionValue)); ++ ++ return u32MotionValue; ++} ++ ++/******************************************************************************/ ++///Read motion value (Motion count status) ++///@return MS_U8: Motion value ++/******************************************************************************/ ++MS_U32 MDrv_SC_read_motion_value2(void) ++{ ++ ++ MS_U32 u32MotionValue; ++ ++ u32MotionValue = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK0A_1A_L, 0x7F); ++ ++ return u32MotionValue; ++} ++ ++//------------------------------------------------------------------------------------------------- ++/// Read motion value (Motion count status) ++/// @return MS_U8: Motion value ++//------------------------------------------------------------------------------------------------- ++MS_U8 MApi_XC_GetCurrentMotionValue(void) ++{ ++ ++ MS_U8 u8MotionValue; ++ ++ u8MotionValue = (MS_U8)((MApi_XC_R2BYTEMSK(REG_SC_BK22_0E_L, 0x3F) << 2) | ++ (MApi_XC_R2BYTEMSK(REG_SC_BK22_0D_L, 0xC000) >> 6)); ++ ++ return u8MotionValue; ++} ++ ++/******************************************************************************/ ++///Read VCnt value ++///@return MS_U8: VCnt value ++/******************************************************************************/ ++MS_U8 MDrv_SC_read_v_cnt(void) ++{ ++ MS_U8 u8VCnt; ++ ++ u8VCnt = (MS_U8)(MApi_XC_R2BYTEMSK(REG_SC_BK22_0E_L, 0xC0) >> 6); ++ return u8VCnt; ++} ++ ++/******************************************************************************/ ++///Read SDHDD Detect Threshold value ++///@return MS_U16: HDSDD_Det_Threshold value ++/******************************************************************************/ ++MS_U16 MDrv_SC_read_HDSDD_Det_Threshold_value(void) ++{ ++ ++ MS_U16 u16Value; ++ ++ u16Value = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ return u16Value; ++} ++ ++/******************************************************************************/ ++///MCDi Driver ++/******************************************************************************/ ++#define ENABLE_XXX_V_MOVING 0x01 ++#define ENABLE_XXX_SST 0x02 ++#define ENABLE_XXX_EodiWeight 0x04 ++ ++ ++void MDrv_SC_mcdi_driver(MS_U32 u32MotionValue) ++{ ++ MS_U32 u32Reg78, u32Reg79, u32Reg7A, u32Reg7B, u32Reg7C, u32Reg7D, u32Reg7E, filmFeatherCount; ++ MS_U32 curCounter3, cntDiff; ++ MS_U8 u8xxxCtrl; ++ MS_BOOL verticalMovingU, horizontalMoving, slowMotion, featheringScene, featheringScene2; ++ static MS_U8 u8SkipCnt; ++ static MS_U8 featheringFrameCount; ++ static MS_U8 s8DeBouncingCnt; ++ static MS_U8 stillFrameCnt; ++ static MS_U8 filmCnt = 0; ++ static MS_U32 preCounter3 = 0; ++ static MS_U8 eodiCnt = 0; ++ MS_BOOL skipCond; ++ MS_BOOL verticalMoving2; ++ MS_BOOL filmDisableMCDiDFK; ++ ++ MS_U16 reg_debouncing_th, reg_debouncing_cnt; ++ MS_BOOL film; ++ ++ u8xxxCtrl = 0xFF; //MApi_XC_R2BYTE(REG_SC_BK2A_1F_L) >> 8; ++ ++ u32Reg78 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ u32Reg79 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ u32Reg7A = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ u32Reg7B = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); ++ u32Reg7C = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32Reg7D = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32Reg7E = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ filmFeatherCount = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ //if(!MirrorEnable) ++ if(MApi_XC_GetMirrorModeType(MAIN_WINDOW) == MIRROR_NORMAL) ++ { ++ //Non_Mirror ++ verticalMovingU = (u32Reg7E > 0x0100) && (u32Reg7E > 8 * u32Reg7C) && (u32Reg7E > 8 * u32Reg7D); ++ verticalMoving2 = (((u32Reg7E > 0x200) && (u32Reg7E > u32Reg7C)) || ((u32Reg7D > 0x200) && (u32Reg7D > u32Reg7C))); ++ horizontalMoving = (u32Reg79 > 0x200) && (u32Reg7B < 0x40) && (u32Reg79 > u32Reg78) && (!verticalMoving2); ++ slowMotion = (u32Reg7A > 0x200) && (u32Reg7B < 0x40) && (!verticalMoving2); ++ //featheringScene = (u32MotionValue > 0x0F) && (u32Reg7B > 0x800); ++ featheringScene = (u32Reg7B > 0x100) && (u32Reg7B > u32Reg79 / 4) && (u32Reg7B > u32Reg7A / 4); ++ skipCond = (u32Reg7A > 8 * u32Reg79) && (u32Reg7B > 0x600); ++ featheringScene2 = (u32Reg7B > 0x200) && (u32Reg7B > u32Reg79 / 8) && (u32Reg7B > u32Reg7A / 8); ++ } ++ else ++ { ++ //Mirror ++ verticalMovingU = (u32Reg7D > 0x0100) && (u32Reg7D > 8 * u32Reg7C) && (u32Reg7D > 8 * u32Reg7E); ++ verticalMoving2 = (((u32Reg7D > 0x200) && (u32Reg7D > u32Reg7C)) || ((u32Reg7E > 0x200) && (u32Reg7E > u32Reg7C))); ++ horizontalMoving = (u32Reg79 > 0x200) && (u32Reg7B < 0x40) && (u32Reg79 > u32Reg78) && (!verticalMoving2); ++ slowMotion = (u32Reg7A > 0x200) && (u32Reg7B < 0x40) && (!verticalMoving2); ++ //featheringScene = (u32MotionValue > 0x0F) && (u32Reg7B > 0x800); ++ featheringScene = (u32Reg7B > 0x100) && (u32Reg7B > u32Reg79 / 4) && (u32Reg7B > u32Reg7A / 4); ++ skipCond = (u32Reg7A > 8 * u32Reg79) && (u32Reg7B > 0x600); ++ featheringScene2 = (u32Reg7B > 0x200) && (u32Reg7B > u32Reg79 / 8) && (u32Reg7B > u32Reg7A / 8); ++ } ++ ++ if(false == skipCond) ++ { ++ if(u8SkipCnt == 0) ++ u8SkipCnt = 0; ++ else ++ u8SkipCnt--; ++ } ++ else ++ { ++ if(u8SkipCnt > 0x40) ++ u8SkipCnt = 0x40; ++ else ++ u8SkipCnt++; ++ } ++ ++ if(filmFeatherCount > 0x100) ++ { ++ if(featheringFrameCount < 0x80) ++ featheringFrameCount ++; ++ } ++ else ++ { ++ featheringFrameCount = 0; ++ } ++ ++ if((u32MotionValue == 0) && (u32Reg7B < 0x20)) ++ { ++ if(stillFrameCnt < 0x20) ++ stillFrameCnt ++; ++ } ++ else ++ { ++ stillFrameCnt = 0; ++ } ++ ++ //////////////////////////////////////////////////////////////// ++ // film content disable mcdi/dfk ++ //////////////////////////////////////////////////////////////// ++ ++ curCounter3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ cntDiff = (preCounter3 > curCounter3) ? preCounter3 - curCounter3 : curCounter3 - preCounter3; ++ ++ if(cntDiff > 0x1500) ++ { ++ if(filmCnt != 10) ++ filmCnt++; ++ } ++ else if(filmCnt != 0) ++ { ++ filmCnt--; ++ } ++ ++ preCounter3 = curCounter3; ++ //printf("filmCnt = [%x]\n", filmCnt); ++ filmDisableMCDiDFK = (filmCnt > 5); ++ ++ //////////////////////////////////////////////////////////////// ++ // eodi counter ++ //////////////////////////////////////////////////////////////// ++ ++ if(featheringScene2) ++ { ++ if(eodiCnt < 40) ++ eodiCnt += 4; ++ } ++ else ++ { ++ if(eodiCnt > 0) ++ eodiCnt--; ++ } ++ ++ ++ ///////////////////////////////////////////////////////////////// ++ // SST (De-Feathering) ++ ///////////////////////////////////////////////////////////////// ++ if(u8xxxCtrl & ENABLE_XXX_SST) ++ { ++ if(featheringScene || filmDisableMCDiDFK) // moving & feather ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x3100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0100, 0x0F00); // SST motion shift1 ++ } ++ else if((u32Reg79 > 0x200) && (u32Reg7B < 0x40)) // patch sony temple ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x1100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0200, 0x0F00); // SST motion shift1 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x3100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0100, 0x0F00); // SST motion shift1 ++ } ++ } ++ ++ // disable DFK when verticalMovingU ++ if((true == verticalMovingU) || (u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // default DFK ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x2000, 0xF000); // default DFK ++ } ++ ++ // Favor MCDi-V when verticalMovingU ++ if(true == verticalMovingU) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0800, 0x0800); // Enable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x0FF0, 0xFFFF); // favor MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x2800, 0x3C00); // enable MCDi U for blending and history ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // reduce motion history ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0000, 0x0800); // Disable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x8888, 0xFFFF); // default MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x0000, 0x3C00); // Use MCDi-H as default ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // default MCDi motion history ++ } ++ ++ // DFK EodiW1, 2 ++ if((s8DeBouncingCnt < 0x3) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if((true == verticalMovingU) || verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW -> LG tower ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x2c30, 0xFF30); // disable EodiW for DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x18F1, 0xFF30); // default ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0040, 0x00F0); // default DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c10, 0xFF30); // default ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4488, 0x00F0); ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x0020, 0x00F0); ++ ++ // DFK check feathering gain ++ if((stillFrameCnt > 0x8) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0100, 0x0F00); ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // reduce DFK feathering weight ++ } ++ else if(u32Reg7B > 0x100) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // feather -> increase ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // default for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // default ++ } ++ ++ // EodiWeight for MCDi ++ if(true == verticalMovingU) ++ { ++ //if ( u32Reg7A > 0x200 && u32Reg7A/4 > u32Reg79 ) // not-found >> horizontal : Church ++ if((u32Reg7A > 0x100) && (u32Reg7A / 2 > u32Reg79)) // not-found >> horizontal : Church ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); // church ++ } ++ else // LG Tower ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4200, 0xFF0F); // LG Tower ++ } ++ } ++ else if((false == verticalMovingU) && horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x1800, 0xFF0F); // reduce EodiW for MCDi ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4408, 0xFF0F); ++ } ++ else if(eodiCnt > 25) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0001, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4400, 0xFF0F); ++ } ++ else if(eodiCnt < 10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC830, 0xFFFF); // reduce EodiW on MCDi ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC832, 0xFFFF); // reduce EodiW on MCDi ++ ++ // MCDi check Feathering weight ++ if((true == verticalMovingU) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight -> for church ++ } ++ else if(horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0060, 0x00F0); // default MCDi Feathering Weight ++ } ++ // multi-burst skip ++ if((u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0000, 0x0080); // disable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(u8SkipCnt < 0x10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0080, 0x0080); // enable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xc000, 0xF000); // ++ ++ ///////////////////////////////////////////////////////////////// ++ // De-bouncing ++ ///////////////////////////////////////////////////////////////// ++ ++ ++ ++ reg_debouncing_th = 0x0A; ++ reg_debouncing_cnt = 0x03; ++ ++ if(u32MotionValue <= reg_debouncing_th) ++ { ++ s8DeBouncingCnt = 0; ++ } ++ else ++ { ++ if(s8DeBouncingCnt < 0xff) ++ s8DeBouncingCnt++; ++ } ++ ++ ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ if((s8DeBouncingCnt >= reg_debouncing_cnt) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x0004, 0x000e); // history weight = 1 ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 1 ++ } ++ /* ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_17_L, (MS_U16)0x02c0, 0xFFFF); // fetch no. ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_07_L, (MS_U16)0x2088, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x1000, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_12_L, (MS_U16)0x0000, 0x0001); // disable CCS ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, (MS_U16)0x0000, 0x0001); // disable DHD ++ */ ++} ++ ++void MDrv_SC_mcdi_driver_new(MS_U32 u32MotionValue, MS_U8 u8MotLvl) ++{ ++ MS_U32 u32Reg78, u32Reg79, u32Reg7A, u32Reg7B, u32Reg7C, u32Reg7D, u32Reg7E, filmFeatherCount; ++ MS_U32 curCounter3, cntDiff; ++ MS_U8 u8xxxCtrl; ++ MS_BOOL verticalMovingU, horizontalMoving, slowMotion, featheringScene, featheringScene2, movingScene; ++ static MS_U8 u8SkipCnt; ++ static MS_U8 featheringFrameCount; ++ static MS_U8 s8DeBouncingCnt; ++ //static MS_U8 stillFrameCnt; ++ static MS_U8 filmCnt = 0; ++ static MS_U32 preCounter3 = 0; ++ static MS_U8 eodiCnt = 0; ++ static MS_U8 verticalMovingUCnt = 0; ++ MS_BOOL skipCond; ++ MS_BOOL verticalMoving2; ++ MS_BOOL filmDisableMCDiDFK; ++ ++ MS_BOOL film; ++ ++ ++ u8xxxCtrl = 0xFF; //MApi_XC_R2BYTE(REG_SC_BK2A_1F_L) >> 8; ++ u32Reg78 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); // isMV0 ++ u32Reg79 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); // Horzontal Moving ++ u32Reg7A = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); // MV not found ++ u32Reg7B = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); // Feathering ++ u32Reg7C = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32Reg7D = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32Reg7E = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ filmFeatherCount = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ //printf("motion level = %x\n", u8MotLvl ); ++// if(!MirrorEnable) ++ if(MApi_XC_GetMirrorModeType(MAIN_WINDOW) == MIRROR_NORMAL) ++ { ++ //Non_Mirror ++ verticalMovingU = ((u32Reg7E > 0x0100) && (u32Reg7E / 8 > u32Reg7C) && (u32Reg7E / 8 > u32Reg7D) && (u32Reg78 > u32Reg79 / 8)) || ++ ((u32Reg7E > 0x0040) && (u32Reg7E / 32 > u32Reg7C) && (u32Reg7E / 32 > u32Reg7D) && (u32Reg78 > u32Reg79 / 8)); ++ movingScene = (u32Reg7E > 0x0080) && (u32Reg7E / 4 > u32Reg7C) && (u32Reg7E / 4 > u32Reg7D) && // V-moving-up && ++ (u32Reg79 > 0x0200) && (u32Reg79 / 4 > u32Reg78); // H-moving ++ } ++ else ++ { ++ //Mirror ++ verticalMovingU = ((u32Reg7D > 0x0100) && (u32Reg7D / 8 > u32Reg7C) && (u32Reg7D / 8 > u32Reg7E) && (u32Reg78 > u32Reg79 / 8)) || ++ ((u32Reg7D > 0x0040) && (u32Reg7D / 32 > u32Reg7C) && (u32Reg7D / 32 > u32Reg7E) && (u32Reg78 > u32Reg79 / 8)); ++ movingScene = (u32Reg7D > 0x0080) && (u32Reg7D / 4 > u32Reg7C) && (u32Reg7D / 4 > u32Reg7E) && // V-moving-up && ++ (u32Reg79 > 0x0200) && (u32Reg79 / 4 > u32Reg78); // H-moving ++ } ++ ++ verticalMoving2 = (((u32Reg7E > 0x200) && (u32Reg7E > u32Reg7C)) || ((u32Reg7D > 0x200) && (u32Reg7D > u32Reg7C))) && (u32Reg78 > u32Reg79 / 8); ++ ++ /*verticalMovingU = ( (u32Reg7E > 0x0100) && (u32Reg7E/8 > u32Reg7C) && (u32Reg7E/8 > u32Reg7D) && (u32Reg78 > u32Reg79) ) || ++ ( (u32Reg7E > 0x0040) && (u32Reg7E/32 > u32Reg7C) && (u32Reg7E/32 > u32Reg7D) && (u32Reg78 > u32Reg79) ); ++ verticalMoving2 = ( ( u32Reg7E > 0x200 && u32Reg7E > u32Reg7C ) || ( u32Reg7D > 0x200 && u32Reg7D > u32Reg7C ) ) && (u32Reg78 > u32Reg79); ++ *///ian ++ ++ //horizontalMoving = u32Reg79 > 0x200 && u32Reg7B < 0x40 && u32Reg79 > u32Reg78 && !verticalMoving2; ++ horizontalMoving = (u32Reg79 > 0x200) && (u32Reg79 / 16 > u32Reg78) && (u32Reg79 > u32Reg7A / 2) && ++ (u32Reg7C > 0x100) && (u32Reg7C / 2 > u32Reg7D) && (u32Reg7C / 2 > u32Reg7E) ; ++ ++ /* horizontalMoving = u32Reg79 > 0x200 && u32Reg79/16 > u32Reg78 && u32Reg79/4 > u32Reg7A && ++ u32Reg7C > 0x100 && u32Reg7C/4 > u32Reg7D && u32Reg7C/4 > u32Reg7E ; ++ *///ian ++ ++ slowMotion = (u32Reg7A > 0x200) && (u32Reg7B < 0x40) && (!verticalMoving2); ++ //featheringScene = (u32MotionValue > 0x0F) && (u32Reg7B > 0x800); ++ featheringScene = (u32Reg7B > 0x100) && (u32Reg7B > u32Reg79 / 4) && (u32Reg7B > u32Reg7A / 4) && (u32MotionValue > 0x10); ++ skipCond = (u32Reg7A > 8 * u32Reg79) && (u32Reg7B > 0x600); ++ featheringScene2 = (u32Reg7B > 0x200) && (u32Reg7B > u32Reg79 / 8) && (u32Reg7B > u32Reg7A / 8) && (!horizontalMoving) && (u32MotionValue > 0x10); ++ ++#if 0 ++ if(true == verticalMovingU) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x1000, 0xFFFF); // show verticalMovingU ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x0000, 0xFFFF); // show verticalMovingU ++ } ++#endif ++ ++ if(verticalMovingU) ++ { ++ if(verticalMovingUCnt != 0xff) ++ { ++ verticalMovingUCnt ++; ++ } ++ } ++ else ++ { ++ verticalMovingUCnt = 0; ++ } ++ ++ if(false == skipCond) ++ { ++ if(u8SkipCnt == 0) ++ u8SkipCnt = 0; ++ else ++ u8SkipCnt--; ++ } ++ else ++ { ++ if(u8SkipCnt > 0x40) ++ u8SkipCnt = 0x40; ++ else ++ u8SkipCnt++; ++ } ++ ++ if(filmFeatherCount > 0x100) ++ { ++ if(featheringFrameCount < 0x80) ++ featheringFrameCount ++; ++ } ++ else ++ { ++ featheringFrameCount = 0; ++ } ++ /* ++ if ( u32MotionValue == 0 && u32Reg7B < 0x20 ) ++ { ++ stillFrameCnt = 0x20; ++ } ++ else ++ { ++ stillFrameCnt = 0; ++ } ++ */ ++ //////////////////////////////////////////////////////////////// ++ // film content disable mcdi/dfk ++ //////////////////////////////////////////////////////////////// ++ ++ curCounter3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ cntDiff = (preCounter3 > curCounter3) ? preCounter3 - curCounter3 : curCounter3 - preCounter3; ++ ++ if(cntDiff > 0x1500) ++ { ++ if(filmCnt != 10) ++ filmCnt++; ++ } ++ else if(filmCnt != 0) ++ { ++ filmCnt--; ++ } ++ ++ preCounter3 = curCounter3; ++ //printf("filmCnt = [%x]\n", filmCnt); ++ filmDisableMCDiDFK = (filmCnt > 5); ++ ++ //////////////////////////////////////////////////////////////// ++ // eodi counter ++ //////////////////////////////////////////////////////////////// ++ ++ if(featheringScene2) ++ { ++ if(eodiCnt < 40) ++ eodiCnt += 4; ++ } ++ else ++ { ++ if(eodiCnt > 0) ++ eodiCnt--; ++ } ++ ++ ///////////////////////////////////////////////////////////////// ++ // SST (De-Feathering) ++ ///////////////////////////////////////////////////////////////// ++ if(u8xxxCtrl & ENABLE_XXX_SST) ++ { ++ if(movingScene || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0xF100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x0F00); // SST motion shift1 ++ } ++ /* ++ else if ( (u32Reg79 > 0x200 && u32Reg7B < 0x40) || (stillFrameCnt>=10) ) // patch sony temple, but champion bubble !? ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x1100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0200, 0x0F00); // SST motion shift1 ++ } ++ */ ++ else if((u32MotionValue < 0x10) && (u32Reg7B > 0x1000)) // special patch for Toshiba... -> tend to still ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x3100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0200, 0x0F00); // SST motion shift1 ++ } ++ else if(featheringScene) // moving & feather ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0xF100, 0xFF00); // increase SST weighting with checking feathering... ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x0F00); // SST motion shift1 ++ } ++ else if((u8MotLvl >= 3) && (u32Reg7B > 0x40) && (u32Reg7B > u32Reg7A / 16)) // for sony champion bubbles ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0xF100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x0F00); // SST motion shift1 ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_29_L, (MS_U16)0x2100, 0xFF00); // default SST setting ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0100, 0x0F00); // SST motion shift1 ++ } ++ } ++ ++ // disable DFK when verticalMovingU ++ if((true == verticalMovingU) || (u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // default DFK ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x2000, 0xF000); // default DFK ++ } ++ ++ if(verticalMovingUCnt > 0x20) // for church ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x0FF0, 0xFFFF); // favor MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x2800, 0x3C0F); // enable MCDi U for blending and history ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_34_L, (MS_U16)0x8888, 0xFFFF); // default MCDi Weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_36_L, (MS_U16)0x0000, 0x3C0F); // Use MCDi-H as default ++ } ++ ++ // Favor MCDi-V when verticalMovingU ++ if(1) //true == verticalMovingU ) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0800, 0x0800); // Enable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // reduce motion history ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)0x0800, 0x0800); // Disable MCDi-V ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x4000, 0xF000); // default MCDi motion history ++ } ++ ++ // DFK EodiW1, 2 ++ if((s8DeBouncingCnt < 0x3) || filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if((true == verticalMovingU) || verticalMoving2) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW -> LG tower ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0080, 0x00F0); // reduce DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x2c30, 0xFF30); // disable EodiW for DFK ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c30, 0xFF30); // disable EodiW for DFK ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0010, 0x00F0); // increase EodiW ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x18F1, 0xFF30); // default ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0040, 0x00F0); // default DFK EodiWeight ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x4c10, 0xFF30); // default ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)0x0c10, 0xFF30); // default ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4488, 0x00F0); ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x0020, 0x00F0); ++ ++ // DFK check feathering gain ++ if(filmDisableMCDiDFK) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xf000, 0xF000); // ++ } ++ else if(u32MotionValue == 0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // reduce DFK feathering weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x1000, 0xF000); // ++ } ++ else if((false == verticalMovingU) && slowMotion) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // reduce DFK feathering weight ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x1000, 0xF000); // ++ } ++ else if(u32Reg7B > 0x100) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // feather -> increase ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xc000, 0xF000); // ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0800, 0x0F00); // default for china ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0f00, 0x0F00); // default ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x4000, 0xF000); // ++ } ++ ++ // EodiWeight for MCDi ++ if(true == verticalMovingU) ++ { ++ //if ( u32Reg7A > 0x200 && u32Reg7A/4 > u32Reg79 ) // not-found >> horizontal : Church ++ if((u32Reg7A > 0x100) && (u32Reg7A / 2 > u32Reg79)) // not-found >> horizontal : Church ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); // church ++ } ++ else // LG Tower ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0004, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4200, 0xFF0F); // LG Tower ++ } ++ } ++ else if((false == verticalMovingU) && horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // reduce EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x1800, 0xFF0F); // reduce EodiW for MCDi ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8))) // RF/AV default, eodi weight strong ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // increase EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4408, 0xFF0F); ++ } ++ else if(eodiCnt > 25) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0001, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4400, 0xFF0F); ++ } ++ else if(eodiCnt < 10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2C_L, (MS_U16)0x0002, 0x000F); // default EodiWeight for MCDi ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)0x4800, 0xFF0F); ++ } ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK2A_1F_L, BIT(8)) && (!horizontalMoving)) // RF/AV default, eodi weight strong ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC830, 0xFFFF); // reduce EodiW on MCDi ++ else if(!horizontalMoving) ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC832, 0xFFFF); // reduce EodiW on MCDi ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_29_L, (MS_U16)0xC836, 0xFFFF); ++ ++ // MCDi check Feathering weight ++ if(filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0060, 0x00F0); // reduce MCDi feathering weight -> for church ++ } ++ else if(true == verticalMovingU) //new add ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight -> for church ++ } ++ else if(horizontalMoving) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0000, 0x00F0); // reduce MCDi feathering weight ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)0x0060, 0x00F0); // default MCDi Feathering Weight ++ } ++ // multi-burst skip ++ if((u8SkipCnt > 0x20) || filmDisableMCDiDFK) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0000, 0x0080); // disable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0x0000, 0xFFFF); // disable DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0x0000, 0xF000); // disable DFK ++ } ++ else if(u8SkipCnt < 0x10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)0x0080, 0x0080); // enable mcdi ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)0xA8FF, 0xFFFF); // default DFK ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2A_L, (MS_U16)0xF000, 0xF000); // default DFK ++ } ++ ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0xc000, 0xF000); // ++ if(u32MotionValue == 0) // still picture -> tend to still ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x0800, 0x0FFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0000, 0x00FF); // ++ } ++ else // default ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2B_L, (MS_U16)0x0888, 0x0FFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2C_L, (MS_U16)0x0088, 0x00FF); // ++ } ++ ++ ///////////////////////////////////////////////////////////////// ++ // De-bouncing ++ ///////////////////////////////////////////////////////////////// ++#if 0 ++ MS_U16 reg_debouncing_th, reg_debouncing_cnt; ++ ++ reg_debouncing_th = 0x0A; ++ reg_debouncing_cnt = 0x03; ++ ++ if(u32MotionValue <= reg_debouncing_th) ++ { ++ s8DeBouncingCnt = 0; ++ } ++ else ++ { ++ if(s8DeBouncingCnt < 0xff) ++ s8DeBouncingCnt++; ++ } ++ ++ MS_BOOL film; ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ ++ if((s8DeBouncingCnt >= reg_debouncing_cnt) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x0004, 0x000e); // history weight = 2 ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 1 ++ } ++#endif ++ ++ ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ if((u8MotLvl >= 1) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x0004, 0x000e); // history weight = 2 ++ //MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, 0x000c, 0x000e); // history weight = 1 ++ } ++ /* ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_17_L, (MS_U16)0x02c0, 0xFFFF); // fetch no. ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_07_L, (MS_U16)0x2088, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, (MS_U16)0x1000, 0xFFFF); // ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_12_L, (MS_U16)0x0000, 0x0001); // disable CCS ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, (MS_U16)0x0000, 0x0001); // disable DHD ++ */ ++} ++ ++#define MF_Gain 30 ++MS_U32 MDrv_SC_T12_UC_SmallMoving(void) ++{ ++ MS_U32 before_MC_feather; ++ MS_U32 nonMV0_Comfirm, MV_Contradict; ++ MS_U32 MovingFeather, MV_Confirm; ++ static MS_U32 PrevMV_Confirm = 0; ++ ++ before_MC_feather = MApi_XC_R2BYTE(REG_SC_BK2A_77_L) ; ++ nonMV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ MV_Contradict = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ MV_Confirm = (nonMV0_Comfirm + MV_Contradict) >> 1; ++ ++ MV_Confirm = (PrevMV_Confirm * 3 + MV_Confirm) >> 2; ++ PrevMV_Confirm = MV_Confirm; ++ ++ if(MV_Confirm > (before_MC_feather * MF_Gain)) ++ MovingFeather = MV_Confirm - ((before_MC_feather * MF_Gain)) ; ++ else ++ MovingFeather = 0; ++ ++ return MovingFeather; // "Big": in seach range "Small": out of seach range ++} ++ ++#define OOSRF_Gain 4 ++#define OOSRF_Power 2 ++MS_U32 MDrv_SC_T12_UC_InSearchRange_Feather(void) ++{ ++ MS_U32 before_MC_feather, after_MC_feather; ++ MS_U32 MC_OOSRF; ++ static MS_U32 Prev_before_MC_feather = 0; ++ static MS_U32 Prev_after_MC_feather = 0; ++ ++ before_MC_feather = MApi_XC_R2BYTE(REG_SC_BK2A_77_L) ; ++ after_MC_feather = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); ++ ++ before_MC_feather = (Prev_before_MC_feather * 3 + before_MC_feather) >> 2; ++ Prev_before_MC_feather = before_MC_feather; ++ ++ after_MC_feather = (Prev_after_MC_feather * 3 + after_MC_feather) >> 2; ++ Prev_after_MC_feather = after_MC_feather; ++ ++ if(before_MC_feather > (after_MC_feather * OOSRF_Gain) >> OOSRF_Power) ++ MC_OOSRF = before_MC_feather - ((after_MC_feather * OOSRF_Gain) >> OOSRF_Power) ; ++ else ++ MC_OOSRF = 0; ++ ++ return MC_OOSRF; // "Big": in seach range "Small": out of seach range ++} ++ ++ ++#define OOSRMC_Gain 20 ++MS_U32 MDrv_SC_T12_UC_InSearchRange_MvComfirm(void) ++{ ++ MS_U32 MV0_Comfirm, nonMV0_Comfirm, MV_Contradict; ++ static MS_U32 Prev_MV0_Comfirm = 0; ++ static MS_U32 Prev_nonMV0_Comfirm = 0; ++ static MS_U32 Prev_MV_Contradict = 0; ++ MS_U32 MV_Comfirm, MC_OOSRMC; ++ ++ MV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ nonMV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ MV_Contradict = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ MV0_Comfirm = (Prev_MV0_Comfirm * 3 + MV0_Comfirm) >> 2; ++ Prev_MV0_Comfirm = MV0_Comfirm; ++ ++ nonMV0_Comfirm = (Prev_nonMV0_Comfirm * 3 + nonMV0_Comfirm) >> 2; ++ Prev_nonMV0_Comfirm = nonMV0_Comfirm; ++ ++ MV_Contradict = (Prev_MV_Contradict * 3 + MV_Contradict) >> 2; ++ Prev_MV_Contradict = MV_Contradict; ++ ++ MV_Comfirm = MV0_Comfirm + nonMV0_Comfirm; ++ ++ if(MV_Comfirm > MV_Contradict * OOSRMC_Gain) ++ MC_OOSRMC = MV_Comfirm - MV_Contradict * OOSRMC_Gain; ++ else ++ MC_OOSRMC = 0; ++ ++ return MC_OOSRMC; // "Big": in seach range "Small": out of seach range ++ ++} ++ ++#define ISR_NONMV0_Gain 15 ++MS_U32 MDrv_SC_T12_UC_InSearchRange_nonMv0Comfirm(void) ++{ ++ MS_U32 MV0_Comfirm, nonMV0_Comfirm, MV_Contradict; ++ static MS_U32 Prev_MV0_Comfirm = 0; ++ static MS_U32 Prev_nonMV0_Comfirm = 0; ++ static MS_U32 Prev_MV_Contradict = 0; ++ MS_U32 MV_Comfirm, Comfirm_Value; ++ ++ MV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ nonMV0_Comfirm = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ MV_Contradict = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ MV0_Comfirm = (Prev_MV0_Comfirm * 3 + MV0_Comfirm) >> 2; ++ Prev_MV0_Comfirm = MV0_Comfirm; ++ ++ nonMV0_Comfirm = (Prev_nonMV0_Comfirm * 3 + nonMV0_Comfirm) >> 2; ++ Prev_nonMV0_Comfirm = nonMV0_Comfirm; ++ ++ MV_Contradict = (Prev_MV_Contradict * 3 + MV_Contradict) >> 2; ++ Prev_MV_Contradict = MV_Contradict; ++ ++ MV_Comfirm = /*MV0_Comfim +*/nonMV0_Comfirm; ++ ++ if(MV_Comfirm > MV_Contradict * ISR_NONMV0_Gain) ++ Comfirm_Value = MV_Comfirm - MV_Contradict * ISR_NONMV0_Gain; ++ else ++ Comfirm_Value = 0; ++ ++ return Comfirm_Value; // "Big": in seach range "Small": out of seach range ++ ++} ++ ++void MDrv_SC_T12_DIPF_TemporalGainControl(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 TemporalGainControl = 0x0F; ++ ++ //printf("====OOSRMC=%x===\n",OOSRMC); ++ //printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(TemporalGainControl > 0x00) ++ TemporalGainControl--; ++ else ++ TemporalGainControl = 0; ++ } ++ else ++ { ++ if(TemporalGainControl < 0x0F) ++ TemporalGainControl++; ++ else ++ TemporalGainControl = 0x0F; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_14_L, (MS_U16)TemporalGainControl, 0x000F); ++ ++} ++ ++#define ComplexOffset_MaxValue 0x06 ++#define ComplexOffset_MinValue 0x00 ++void MDrv_SC_T12_UCDi_ComplexOffset(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 ComplexOffset = ComplexOffset_MaxValue; ++ ++ //printf("====OOSRMC=%x===\n",OOSRMC); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(ComplexOffset > ComplexOffset_MinValue) ++ ComplexOffset--; ++ else ++ ComplexOffset = ComplexOffset_MinValue; ++ } ++ else ++ { ++ if(ComplexOffset < ComplexOffset_MaxValue) ++ ComplexOffset++; ++ else ++ ComplexOffset = ComplexOffset_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)ComplexOffset << 4, 0x00F0); ++ ++} ++ ++#define OP1_HisWeight_MaxValue 0x0E ++#define OP1_HisWeight_MinValue 0x04 ++void MDrv_SC_T12_UCDi_OP1_HisWeight(MS_U8 u8MotLvl) ++{ ++ MS_BOOL film; ++ ++ film = ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0008) == 0x0008) || // film22 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0010) == 0x0010) || // film32 ++ ((MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, 0x0040) == 0x0040) ; // film any ++ ++ if((u8MotLvl >= 1) || (true == film)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, OP1_HisWeight_MaxValue, 0x000e); // history weight = 6 ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, OP1_HisWeight_MinValue, 0x000e); // history weight = 2 ++ } ++} ++ ++#define A5_HIS_MOTION_TH 0x0A ++void MDrv_SC_A5_UCDi_OP1_HisWeight(const MS_U32 u32MotionValue) ++{ ++ //MS_BOOL film; ++ static MS_U32 reg_his_weight = OP1_HisWeight_MinValue; ++ ++ //MS_U8 motion_level; ++ static MS_U32 u32MotionValue_prev = 0; ++ ++ if( u32MotionValue_prev < u32MotionValue ) ++ u32MotionValue_prev = ((u32MotionValue_prev*3 )+ u32MotionValue ) >> 2; ++ else ++ u32MotionValue_prev = u32MotionValue; ++ ++ //printf("===u32MotionValue_prev==%x=\n",u32MotionValue_prev); ++ //printf("===u16_unmatch_3==%x=\n",u16_unmatch_3); ++ ++ if( u32MotionValue_prev < A5_HIS_MOTION_TH ) ++ { ++ if( reg_his_weight > OP1_HisWeight_MinValue ) ++ reg_his_weight--; ++ else ++ reg_his_weight = OP1_HisWeight_MinValue; ++ } ++ else ++ { ++ if( reg_his_weight < OP1_HisWeight_MaxValue ) ++ reg_his_weight++; ++ else ++ reg_his_weight = OP1_HisWeight_MaxValue; ++ } ++ ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_02_L, (MS_U16)reg_his_weight, 0x000E); ++ ++} ++ ++#define FeatherValueGain_MaxValue 0x02 ++#define FeatherValueGain_MinValue 0x00 ++void MDrv_SC_T12_UCDi_FeatherValueGain(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 FeatherValue = FeatherValueGain_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ // printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(FeatherValue > FeatherValueGain_MinValue) ++ FeatherValue--; ++ else ++ FeatherValue = FeatherValueGain_MinValue; ++ } ++ else ++ { ++ if(FeatherValue < FeatherValueGain_MaxValue) ++ FeatherValue++; ++ else ++ FeatherValue = FeatherValueGain_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2D_L, (MS_U16)FeatherValue << 12, 0xF000); ++ ++} ++ ++#define W2SadGain_MaxValue 0x0C ++#define W2SadGain_MinValue 0x08 ++void MDrv_SC_T12_UCDi_W2SadGain(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 W2SadGain = FeatherValueGain_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ UNUSED(OOSRMC); ++ UNUSED(OOSRF); ++ ++ if(ISR_NONMV0 > 1000) //&& OOSRF > 50) ++ { ++ if(W2SadGain < W2SadGain_MaxValue) ++ W2SadGain++; ++ else ++ W2SadGain = W2SadGain_MaxValue; ++ } ++ else ++ { ++ if(W2SadGain > W2SadGain_MinValue) ++ W2SadGain--; ++ else ++ W2SadGain = W2SadGain_MinValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2D_L, (MS_U16)W2SadGain << 8, 0x0F00); ++ ++} ++ ++#define VerticalMovingUdRatio_MaxValue 0x0F ++#define VerticalMovingUdRatio_MinValue 0x07 ++void MDrv_SC_T12_UCDi_VerticalMovingUdRatio(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 VerticalMovingUdRatioValue = VerticalMovingUdRatio_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ // printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ UNUSED(ISR_NONMV0); ++ ++ //if( ISR_NONMV0 > 1000) ++ if( OOSRF > 0x300 ) ++ { ++ if(VerticalMovingUdRatioValue > VerticalMovingUdRatio_MinValue) ++ VerticalMovingUdRatioValue--; ++ else ++ VerticalMovingUdRatioValue = VerticalMovingUdRatio_MinValue; ++ } ++ else ++ { ++ if(VerticalMovingUdRatioValue < VerticalMovingUdRatio_MaxValue) ++ VerticalMovingUdRatioValue++; ++ else ++ VerticalMovingUdRatioValue = VerticalMovingUdRatio_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_28_L, (MS_U16)VerticalMovingUdRatioValue, 0x000F); ++ ++} ++ ++#define KFC_8bitMotionGain_MaxValue 0x08 ++#define KFC_8bitMotionGain_MinValue 0x04 //0 have feather issue. ++void MDrv_SC_T12_KFC_8bitMotionGain(MS_U32 SmallMoving) ++{ ++ static MS_U16 KFC_8bitMotionGainValue = KFC_8bitMotionGain_MaxValue; ++ ++ //printf("====SmallMoving=%x===\n",SmallMoving); ++ //MApi_XC_W2BYTEMSK(REG_SC_BK20_1D_L, 0x0008, 0x003F); ++ ++ if(SmallMoving > 500) ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x1000, 0x1000); ++ if(KFC_8bitMotionGainValue > KFC_8bitMotionGain_MinValue) ++ KFC_8bitMotionGainValue--; ++ else ++ KFC_8bitMotionGainValue = KFC_8bitMotionGain_MinValue; ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x0000, 0x1000); ++ if(KFC_8bitMotionGainValue < KFC_8bitMotionGain_MaxValue) ++ KFC_8bitMotionGainValue++; ++ else ++ KFC_8bitMotionGainValue = KFC_8bitMotionGain_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_3B_L, (MS_U16)KFC_8bitMotionGainValue << 4, 0x00F0); ++ ++} ++ ++#define UCDi_EODiWGain_MaxValue 0x0F ++#define UCDi_EODiWGain_MinValue 0x00 ++void MDrv_SC_T12_UCDi_EODiWGain(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 EODiWGainValue = UCDi_EODiWGain_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ // printf("====OOSRF=%x===\n",OOSRF); ++ UNUSED(OOSRMC); ++ ++ if((ISR_NONMV0 > 1000) && (OOSRF > 50)) ++ { ++ if(EODiWGainValue > UCDi_EODiWGain_MinValue) ++ EODiWGainValue--; ++ else ++ EODiWGainValue = UCDi_EODiWGain_MinValue; ++ } ++ else ++ { ++ if(EODiWGainValue < UCDi_EODiWGain_MaxValue) ++ EODiWGainValue++; ++ else ++ EODiWGainValue = UCDi_EODiWGain_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_2A_L, (MS_U16)EODiWGainValue << 12, 0xF000); ++ ++} ++ ++#define UCDi_HistoryRatio_MaxValue 0x07 ++#define UCDi_HistoryRatio_MinValue 0x04 ++void MDrv_SC_T12_UCDi_HistoryRatio(MS_U32 OOSRMC, MS_U32 OOSRF, MS_U32 ISR_NONMV0) ++{ ++ static MS_U16 HistoryRatioValue = UCDi_HistoryRatio_MaxValue; ++ ++ // printf("====OOSRMC=%x===\n",OOSRMC); ++ ++ // MApi_XC_W2BYTEMSK(REG_SC_BK20_1D_L, 0x0008, 0x00FF); ++ UNUSED(OOSRMC); ++ ++ if((ISR_NONMV0 > 1000) && (OOSRF > 50)) ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x1000, 0x1000); ++ if(HistoryRatioValue > UCDi_HistoryRatio_MinValue) ++ HistoryRatioValue--; ++ else ++ HistoryRatioValue = UCDi_HistoryRatio_MinValue; ++ } ++ else ++ { ++ //MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x0000, 0x1000); ++ if(HistoryRatioValue < UCDi_HistoryRatio_MaxValue) ++ HistoryRatioValue++; ++ else ++ HistoryRatioValue = UCDi_HistoryRatio_MaxValue; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)HistoryRatioValue << 12, 0xF000); ++ ++} ++ ++#define KFC_EODIW_GAIN_MAX 4 ++#define KFC_EODIW_GAIN_MIN 0 ++void MDrv_SC_A5_KFC_EODiW(const MS_U32 IsVerticalMoving) ++{ ++ MS_U32 Statistics_cplx_pixel; ++ //MS_U32 meVerticalMoving; ++ static MS_U32 Statistics_cplx_pixel_iir = KFC_EODIW_GAIN_MIN; ++ static MS_U32 reg_kfc_eodiw_gain = KFC_EODIW_GAIN_MAX ; ++ ++ Statistics_cplx_pixel = ((Statistics_cplx_pixel_iir*3 )+ MApi_XC_R2BYTE(REG_SC_BK2A_7F_L) ) >> 2; ++ Statistics_cplx_pixel_iir = Statistics_cplx_pixel; ++ ++ if( (IsVerticalMoving < 0x150) && (Statistics_cplx_pixel_iir > 0x1000) ) ++ { ++ if( reg_kfc_eodiw_gain > KFC_EODIW_GAIN_MIN ) ++ reg_kfc_eodiw_gain--; ++ else ++ reg_kfc_eodiw_gain = KFC_EODIW_GAIN_MIN; ++ //reg_kfc_eodiw_gain = MAX(KFC_EODIW_GAIN_MIN, reg_kfc_eodiw_gain - 1); ++ } ++ else ++ { ++ if( reg_kfc_eodiw_gain < KFC_EODIW_GAIN_MAX ) ++ reg_kfc_eodiw_gain++; ++ else ++ reg_kfc_eodiw_gain = KFC_EODIW_GAIN_MAX; ++ //reg_kfc_eodiw_gain = MIN(KFC_EODIW_GAIN_MAX, reg_kfc_eodiw_gain + 1); ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_28_L, (MS_U16)reg_kfc_eodiw_gain << 12, 0xF000); ++} ++ ++#define SONYC_KFC_EN_MAX 1 ++#define SONYC_KFC_EN_MIN 0 ++#define SONYC_CPLX_GAIN_MAX 4 ++#define SONYC_CPLX_GAIN_MIN 0 ++void MDrv_SC_A5_SonyChurch(const MS_U32 IsVerticalMoving, const MS_U32 IsHorizontalMoving, const MS_U32 u32MotionValue, const MS_BOOL lg107_en) ++{ ++ static MS_U32 reg_kfc_en = SONYC_KFC_EN_MAX ; ++ static MS_U32 reg_mcdi_cplx_gain = SONYC_CPLX_GAIN_MAX; ++ ++ //IsHorizontalMoving=IsHorizontalMoving; ++ ++ if( (IsVerticalMoving > 0xF0) && (IsHorizontalMoving < 1) && (u32MotionValue > 0x40000) ) ++ { ++ if( reg_mcdi_cplx_gain > SONYC_CPLX_GAIN_MIN ) ++ reg_mcdi_cplx_gain--; ++ else ++ reg_mcdi_cplx_gain = SONYC_CPLX_GAIN_MIN; ++ ++ if( reg_kfc_en > SONYC_KFC_EN_MIN ) ++ reg_kfc_en--; ++ else ++ reg_kfc_en = SONYC_KFC_EN_MIN; ++ } ++ else ++ { ++ if( reg_mcdi_cplx_gain < SONYC_CPLX_GAIN_MAX ) ++ reg_mcdi_cplx_gain++; ++ else ++ reg_mcdi_cplx_gain = SONYC_CPLX_GAIN_MAX; ++ ++ if( reg_kfc_en < SONYC_KFC_EN_MAX ) ++ reg_kfc_en++; ++ else ++ reg_kfc_en = SONYC_KFC_EN_MAX; ++ } ++ ++ if( !lg107_en ) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_04_L, (MS_U16)reg_kfc_en<<1, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)reg_mcdi_cplx_gain<<8, 0x0F00); ++ } ++} ++ ++#define LG107_FEATHER_GAIN_MAX 2 ++#define LG107_FEATHER_GAIN_MIN 0 ++#define LG107_CPLX_OFFSET_MAX 6 ++#define LG107_CPLX_OFFSET_MIN 0 ++#define LG107_CPLX_GAIN_MAX 15 ++#define LG107_CPLX_GAIN_MIN 4 ++MS_BOOL MDrv_SC_A5_LG107(const MS_U32 IsVerticalMoving, const MS_U32 IsHorizontalMoving, const MS_U32 total_feather, const MS_U32 mvComfirm, const MS_U32 colorSum,const MS_U32 u32MotionValue, const MS_U32 uComplex ) ++{ ++ static MS_U32 reg_mcdi_feather_gain = LG107_FEATHER_GAIN_MAX ; ++ static MS_U32 reg_mcdi_cplx_offset = LG107_CPLX_OFFSET_MAX ; ++ static MS_U32 reg_mcdi_cplx_gain = LG107_CPLX_GAIN_MIN ; ++ MS_BOOL lg107_en; ++ //printf("====IsVerticalMoving=%x===\n",IsVerticalMoving); ++ //printf("====IsHorizontalMoving=%x===\n",IsHorizontalMoving); ++ //printf("====total_feather=%x===\n",total_feather); ++ //printf("====mvComfirm=%x===\n",mvComfirm); ++ //printf("====colorSum=%x===\n",colorSum); ++ // printf("====u32MotionValue=%x===\n",u32MotionValue); ++ ++ if( (IsVerticalMoving < 20) && (IsHorizontalMoving < 200) && (total_feather < 100) && (mvComfirm > 200) && (colorSum > 200) && (u32MotionValue > 0x3500) && (uComplex < 0x700)) ++ { ++ lg107_en = TRUE; ++ ++ if( reg_mcdi_feather_gain > LG107_FEATHER_GAIN_MIN ) ++ reg_mcdi_feather_gain--; ++ else ++ reg_mcdi_feather_gain = LG107_FEATHER_GAIN_MIN; ++ ++ if( reg_mcdi_cplx_offset > LG107_CPLX_OFFSET_MIN ) ++ reg_mcdi_cplx_offset--; ++ else ++ reg_mcdi_cplx_offset = LG107_CPLX_OFFSET_MIN; ++ ++ if( reg_mcdi_cplx_gain < LG107_CPLX_GAIN_MAX ) ++ reg_mcdi_cplx_gain++; ++ else ++ reg_mcdi_cplx_gain = LG107_CPLX_GAIN_MAX; ++ } ++ else ++ { ++ lg107_en = FALSE; ++ ++ if( reg_mcdi_feather_gain < LG107_FEATHER_GAIN_MAX ) ++ reg_mcdi_feather_gain++; ++ else ++ reg_mcdi_feather_gain = LG107_FEATHER_GAIN_MAX; ++ ++ if( reg_mcdi_cplx_offset < LG107_CPLX_OFFSET_MAX ) ++ reg_mcdi_cplx_offset++; ++ else ++ reg_mcdi_cplx_offset = LG107_CPLX_OFFSET_MAX; ++ ++ if( reg_mcdi_cplx_gain > LG107_CPLX_GAIN_MIN ) ++ reg_mcdi_cplx_gain--; ++ else ++ reg_mcdi_cplx_gain = LG107_CPLX_GAIN_MIN; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2D_L, (MS_U16)reg_mcdi_feather_gain<<12, 0xF000); // 2 to 0 ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)reg_mcdi_cplx_offset<<4, 0x00F0);// 6 to 0 ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_2E_L, (MS_U16)reg_mcdi_cplx_gain<<8, 0x0F00);// 4 to F ++ ++return lg107_en; ++} ++ ++MS_U32 MDrv_SC_A5_ComplexSum(void) ++{ ++ static MS_U32 IsComplex_iir = 0xFFFF; ++ MS_U32 IsComplex; ++ ++ IsComplex = MApi_XC_R2BYTE(REG_SC_BK2A_7F_L); ++ ++ IsComplex = (IsComplex_iir*3 + IsComplex ) >> 2; ++ IsComplex_iir = IsComplex; ++ ++ return IsComplex_iir; ++} ++ ++MS_U32 MDrv_SC_A5_KFC_IsVerticalMoving(void) ++{ ++ MS_U32 u32_mvc, u32_mvu, u32_mvd; ++ MS_U32 me_vertical; ++ static MS_U32 IsVerticalMoving_iir = 0; ++ ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ if ((u32_mvu > u32_mvc) && (u32_mvu > u32_mvd) /*&& (u32_mvu > 0x200*/) ++ { ++ if( u32_mvu > (u32_mvc+u32_mvd)/2 ) ++ me_vertical = (u32_mvu - (u32_mvc+u32_mvd)/2); ++ else ++ me_vertical = 0; ++ //me_vertical = MAX(0, u32_mvu - (u32_mvc+u32_mvd)/2); ++ } ++ else if((u32_mvd > u32_mvc) && (u32_mvd > u32_mvu) /*&& (u32_mvd > 0x200)*/) ++ { ++ if( u32_mvd > (u32_mvc+u32_mvu)/2 ) ++ me_vertical = (u32_mvd - (u32_mvc+u32_mvu)/2); ++ else ++ me_vertical = 0; ++ //me_vertical = MAX(0, u32_mvd - (u32_mvc+u32_mvu)/2); ++ } ++ else ++ { ++ me_vertical = 0; ++ } ++ ++ if( me_vertical > 255 ) ++ me_vertical = 255; ++ ++ me_vertical = (IsVerticalMoving_iir*3 + me_vertical ) >> 2; ++ IsVerticalMoving_iir = me_vertical; ++ ++ return me_vertical; ++} ++ ++MS_U32 MDrv_SC_A5_IsHorizontalMoving(void) ++{ ++ MS_U32 u32_mvc, u32_mvu, u32_mvd; ++ MS_U32 me_horizontal; ++ static MS_U32 IsHorizontalMoving_iir = 0; ++ ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ if ((u32_mvc > u32_mvu) && (u32_mvc > u32_mvd) /*&& (u32_mvu > 0x200*/) ++ { ++ if( u32_mvc > (u32_mvu+u32_mvd)/2 ) ++ me_horizontal = (u32_mvc - (u32_mvu+u32_mvd)/2); ++ else ++ me_horizontal = 0; ++ } ++ else ++ { ++ me_horizontal = 0; ++ } ++ ++ if( me_horizontal > 255 ) ++ me_horizontal = 255; ++ ++ me_horizontal = (IsHorizontalMoving_iir*3 + me_horizontal ) >> 2; ++ IsHorizontalMoving_iir = me_horizontal; ++ ++ return me_horizontal; ++} ++ ++ ++MS_U32 MDrv_SC_A5_ColorPixelSum(void) ++{ ++ MS_U32 colorSum; ++ static MS_U32 colorSum_iir = 0; ++ ++ colorSum = MApi_XC_R2BYTE(REG_SC_BK1A_6E_L); ++ colorSum = colorSum / 8; ++ ++ if( colorSum > 255 ) ++ colorSum = 255; ++ ++ colorSum = ((colorSum_iir*3 )+ colorSum ) >> 2; ++ colorSum_iir = colorSum; ++ ++ return colorSum_iir; ++} ++ ++ ++MS_U32 MDrv_SC_A5_TotalFeather(void) ++{ ++ MS_U32 mv0_feather, nonMv0_feather; ++ MS_U32 total_feather; ++ static MS_U32 total_feather_iir = 255; ++ ++ mv0_feather = MApi_XC_R2BYTE(REG_SC_BK2A_77_L); ++ nonMv0_feather = MApi_XC_R2BYTE(REG_SC_BK2A_7B_L); ++ ++ total_feather = ( mv0_feather + nonMv0_feather ) / 4; ++ ++ if( total_feather > 255 ) ++ total_feather = 255; ++ ++ total_feather = ((total_feather_iir*3 )+ total_feather ) >> 2; ++ total_feather_iir = total_feather; ++ ++ return total_feather_iir; ++} ++ ++#define TOTAL_MV_TIME 10 ++MS_U32 MDrv_SC_A5_TotalMvComfirm(void) ++{ ++ MS_U32 mv0, nonMv0, notFound; ++ MS_U32 total_mv, mvComfirm; ++ static MS_U32 mvComfirm_iir = 0; ++ ++ mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ nonMv0 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ notFound = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ ++ total_mv = mv0 + nonMv0; ++ ++ if( total_mv > notFound*TOTAL_MV_TIME ) ++ mvComfirm = total_mv - notFound*TOTAL_MV_TIME; ++ else ++ mvComfirm = 0; ++ ++ if( mvComfirm > 255 ) ++ mvComfirm = 255; ++ ++ mvComfirm = ((mvComfirm_iir*3 )+ mvComfirm ) >> 2; ++ mvComfirm_iir = mvComfirm; ++ ++ return mvComfirm_iir; ++} ++ ++/******************************************************************************/ ++///Extend MCNR Driver ++/******************************************************************************/ ++void MDrv_SC_Extend_UCNR_driver(void) ++{ ++ MS_U32 u32_is_mv0, u32_non_mv0, u32_mvNotFound, u32_mvc, u32_mvu, u32_mvd; ++ MS_BOOL me_not_confirm , me_vertical, still_pattern; ++ static MS_U8 u8notConfirmCnt; ++ static MS_U32 last_u32_mvNotFound; ++ ++ u32_is_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ u32_non_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ u32_mvNotFound = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ ///////////////////////////////////////////////////////////////// ++ // NR Patch 1 ++ ///////////////////////////////////////////////////////////////// ++ ++ me_not_confirm = (u32_is_mv0 < 0x0200) && (u32_non_mv0 < 0x0200) ; ++ me_vertical = ((u32_mvu > u32_mvc) && (u32_mvu > u32_mvd) && (u32_mvu > 0x200)) || ++ ((u32_mvd > u32_mvc) && (u32_mvd > u32_mvu) && (u32_mvd > 0x200)); ++ ++ still_pattern = (u32_is_mv0 < 0x0020) && (u32_non_mv0 < 0x0020) && (u32_mvNotFound < 0x0020); ++ ++ if(!still_pattern) ++ { ++ if(false == me_not_confirm) ++ { ++ if(u8notConfirmCnt > 0) ++ { ++ u8notConfirmCnt--; ++ } ++ } ++ else ++ { ++ if(u8notConfirmCnt <= 0x40) ++ { ++ u8notConfirmCnt++; ++ } ++ } ++ } ++ ++ if(1) ++ { ++ if ( (u8notConfirmCnt > 0x30)|| me_vertical ) // low nr strength ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else if(u8notConfirmCnt < 0x10) ++ { ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xdddd, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ } ++ ++ if ( (u32_is_mv0 > 0x200) && ((u32_is_mv0/2) > u32_non_mv0) && ((u32_is_mv0/2) > u32_mvNotFound) ) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // still picture, reduce random motion ++ } ++ else if(u32_non_mv0 > u32_is_mv0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // default random motion ++ } ++ } ++ ++ last_u32_mvNotFound = u32_mvNotFound; ++} ++ ++/******************************************************************************/ ++///MCNR Driver ++/******************************************************************************/ ++ ++void MDrv_SC_mcnr_driver(void) ++{ ++ MS_U32 u32_is_mv0, u32_non_mv0, u32_mvNotFound, u32_mvc, u32_mvu, u32_mvd; ++ MS_BOOL me_not_confirm , me_vertical; ++ static MS_U8 u8notConfirmCnt; ++ static MS_U32 last_u32_mvNotFound; ++ ++ u32_is_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_78_L); ++ u32_non_mv0 = MApi_XC_R2BYTE(REG_SC_BK2A_79_L); ++ u32_mvNotFound = MApi_XC_R2BYTE(REG_SC_BK2A_7A_L); ++ u32_mvc = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32_mvu = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32_mvd = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ ++ ///////////////////////////////////////////////////////////////// ++ // NR Patch 1 ++ ///////////////////////////////////////////////////////////////// ++ ++ me_not_confirm = (u32_is_mv0 < 0x0200) && (u32_non_mv0 < 0x0200); ++ me_vertical = ((u32_mvu > u32_mvc) && (u32_mvu > u32_mvd) && (u32_mvu > 0x200)) || ++ ((u32_mvd > u32_mvc) && (u32_mvd > u32_mvu) && (u32_mvd > 0x200)); ++ ++ if(false == me_not_confirm) ++ { ++ if(u8notConfirmCnt > 0) ++ { ++ u8notConfirmCnt--; ++ } ++ } ++ else ++ { ++ if(u8notConfirmCnt <= 0x40) ++ { ++ u8notConfirmCnt++; ++ } ++ } ++ ++ if(1) ++ { ++ if((u8notConfirmCnt > 0x30) || me_vertical) // low nr strength ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else if(u8notConfirmCnt < 0x10) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_08_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_09_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0A_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0B_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0C_L, (MS_U16)0xDDDD, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0D_L, (MS_U16)0xBA98, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0E_L, (MS_U16)0x7654, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_0F_L, (MS_U16)0x3210, 0xFFFF); ++ } ++ ++ if((u32_is_mv0 > 0x200) && (u32_is_mv0 / 2 > u32_non_mv0) && (u32_is_mv0 / 2 > u32_mvNotFound)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // still picture, reduce random motion ++ } ++ else if(u32_non_mv0 > u32_is_mv0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // moving picture, increase random motion ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK2A_1B_L, (MS_U16)0x0064, 0x00FF); // default random motion ++ } ++ } ++ ++ last_u32_mvNotFound = u32_mvNotFound; ++} ++ ++/******************************************************************************/ ++///DeFeathering ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_de_feathering(MS_U32 u32MotionValue) ++{ ++ static MS_U32 u32DeFeatherCntLv1 = 0; ++ static MS_U32 u32DeFeatherCntLv2 = 0; ++ static MS_U32 u32DeFeatherCntLv3 = 0; ++ MS_U8 u8SST_Static_Core_TH; ++ MS_U32 reg_defethering_lv1_cnt; ++ MS_U32 reg_defethering_lv2_cnt; ++ MS_U32 reg_mdp_cnt; ++ ++ reg_defethering_lv1_cnt = 0x0A; ++ reg_defethering_lv2_cnt = 0x08; ++ reg_mdp_cnt = 0x01; ++ ++ // motion level count ++ if(u32MotionValue >= DEFETHERING_LV1_TH) ++ { ++ if(u32DeFeatherCntLv1 < reg_defethering_lv1_cnt) ++ u32DeFeatherCntLv1++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv1 >= reg_mdp_cnt) ++ u32DeFeatherCntLv1 = u32DeFeatherCntLv1 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv1 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV2_TH) ++ { ++ if(u32DeFeatherCntLv2 < reg_defethering_lv2_cnt) ++ u32DeFeatherCntLv2++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv2 >= reg_mdp_cnt) ++ u32DeFeatherCntLv2 = u32DeFeatherCntLv2 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv2 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV3_TH) ++ { ++ if(u32DeFeatherCntLv3 < DEFETHERING_LV3_CNT) ++ u32DeFeatherCntLv3++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv3 >= reg_mdp_cnt) ++ u32DeFeatherCntLv3 = u32DeFeatherCntLv3 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv3 = 0; ++ } ++ ++ //DeFeathering begin ++ if(u32DeFeatherCntLv1 >= reg_defethering_lv1_cnt) ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV1_VALUE; ++ } ++ else if(u32DeFeatherCntLv2 >= reg_defethering_lv2_cnt) ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV2_VALUE; ++ } ++ else if(u32DeFeatherCntLv3 >= DEFETHERING_LV3_CNT) ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV3_VALUE; ++ } ++ else ++ { ++ u8SST_Static_Core_TH = SST_STATIC_CORE_TH_LV4_VALUE; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_1A_L, (MS_U16)u8SST_Static_Core_TH, 0xFF); ++} ++ ++ ++int MDrv_SC_motion_level(MS_U32 u32MotionValue) ++{ ++ static MS_U32 u32DeFeatherCntLv1 = 0; ++ static MS_U32 u32DeFeatherCntLv2 = 0; ++ static MS_U32 u32DeFeatherCntLv3 = 0; ++ MS_U8 u8MotLvl; ++ MS_U32 reg_defethering_lv1_cnt; ++ MS_U32 reg_defethering_lv2_cnt; ++ MS_U32 reg_mdp_cnt; ++ ++ reg_defethering_lv1_cnt = 0x0A; ++ reg_defethering_lv2_cnt = 0x08; ++ reg_mdp_cnt = 0x01; ++ ++ // motion level count ++ if(u32MotionValue >= DEFETHERING_LV1_TH) ++ { ++ if(u32DeFeatherCntLv1 < reg_defethering_lv1_cnt) ++ u32DeFeatherCntLv1++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv1 >= reg_mdp_cnt) ++ u32DeFeatherCntLv1 = u32DeFeatherCntLv1 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv1 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV2_TH) ++ { ++ if(u32DeFeatherCntLv2 < reg_defethering_lv2_cnt) ++ u32DeFeatherCntLv2++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv2 >= reg_mdp_cnt) ++ u32DeFeatherCntLv2 = u32DeFeatherCntLv2 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv2 = 0; ++ } ++ ++ if(u32MotionValue >= DEFETHERING_LV3_TH) ++ { ++ if(u32DeFeatherCntLv3 < DEFETHERING_LV3_CNT) ++ u32DeFeatherCntLv3++; ++ } ++ else ++ { ++ if(u32DeFeatherCntLv3 >= reg_mdp_cnt) ++ u32DeFeatherCntLv3 = u32DeFeatherCntLv3 - reg_mdp_cnt; ++ //if(reg_mdp_cnt == 0xFF) ++ //u32DeFeatherCntLv3 = 0; ++ } ++ ++ //level begin ++ if(u32DeFeatherCntLv1 >= reg_defethering_lv1_cnt) ++ { ++ u8MotLvl = 3; ++ } ++ else if(u32DeFeatherCntLv2 >= reg_defethering_lv2_cnt) ++ { ++ u8MotLvl = 2; ++ } ++ else if(u32DeFeatherCntLv3 >= DEFETHERING_LV3_CNT) ++ { ++ u8MotLvl = 1; ++ } ++ else ++ { ++ u8MotLvl = 0; ++ } ++ ++ return u8MotLvl; ++ ++} ++ ++ ++/******************************************************************************/ ++///DeFlickering ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_de_flickering(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DeFlickerCnt = 0; ++ MS_U32 reg_m_feat_smooth_hle_th, reg_m_feat_smooth_shrink; ++ ++ reg_m_feat_smooth_hle_th = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_1E_L, 0xF000); // Feat Smooth HLE TH ++ reg_m_feat_smooth_shrink = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_1E_L, 0x8F); ++ ++ if(u32MotionValue >= DEFLICKERING_TH) ++ { ++ if(s32DeFlickerCnt < 65535) ++ s32DeFlickerCnt++; ++ } ++ else ++ { ++ s32DeFlickerCnt = 0; ++ } ++ ++ if(s32DeFlickerCnt >= DEFLICKERING_CNT) ++ { ++ reg_m_feat_smooth_hle_th += 0x0300; ++ reg_m_feat_smooth_shrink += 0x10; ++ } ++ else ++ { ++ reg_m_feat_smooth_hle_th += 0x0700; ++ reg_m_feat_smooth_shrink += 0x30; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_1E_L, (MS_U16)reg_m_feat_smooth_shrink, 0xFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_1E_L, (MS_U16)reg_m_feat_smooth_hle_th, 0xFF00); ++ ++} ++ ++/******************************************************************************/ ++///DeBouncing ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++#define DEBOUNCING_GAIN 1 //0 ++void MDrv_SC_de_bouncing(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DeBouncingCnt = 0; ++ MS_U32 reg_his_wt_f2; ++ MS_U32 reg_debouncing_th; ++ int reg_debouncing_cnt; ++ ++ reg_debouncing_th = 0x0A; ++ reg_debouncing_cnt = 0x03; ++ ++ reg_his_wt_f2 = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK22_0A_L, 0xF8); // history ratio weighting ++ ++ if(u32MotionValue <= reg_debouncing_th * DEBOUNCING_GAIN) ++ { ++ s32DeBouncingCnt = 0; ++ } ++ else ++ { ++ if(s32DeBouncingCnt < 65535) ++ s32DeBouncingCnt++; ++ } ++ ++ if(s32DeBouncingCnt >= reg_debouncing_cnt) ++ { ++ reg_his_wt_f2 += 0x06; // history = 6 moving ++ } ++ else ++ { ++ reg_his_wt_f2 += 0x03; // history = 3 still ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_0A_L, (MS_U16)reg_his_wt_f2, 0xFF); ++} ++ ++/******************************************************************************/ ++///DePreSNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_de_pre_snr(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DePreSNRCnt = 0; ++ MS_U8 reg_preSnr_en = 0; ++ MS_U32 reg_preSnr_th; ++ int reg_preSnr_cnt; ++ ++ reg_preSnr_th = 0x06; ++ reg_preSnr_cnt = 0x01; ++ ++ if(u32MotionValue <= reg_preSnr_th * DEBOUNCING_GAIN) ++ { ++ s32DePreSNRCnt = 0; ++ } ++ else ++ { ++ if(s32DePreSNRCnt < 65535) ++ s32DePreSNRCnt++; ++ } ++ ++ if(s32DePreSNRCnt >= reg_preSnr_cnt) ++ { ++ reg_preSnr_en = 0x01; // enable pre-snr ++ } ++ else ++ { ++ reg_preSnr_en = 0x00; // disable pre-snr ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK06_22_L, (MS_U16)reg_preSnr_en, BIT(0)); ++} ++ ++/******************************************************************************/ ++///Dynamic SNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_dynamic_snr(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32DynamicSnrCnt = 0; ++#if (DBG_DYNAMIC_SNR) ++ static MS_S32 s32CurrentLevel = -1; ++ static MS_S32 s32LastLevel = -1; ++#endif ++ MS_U8 u8SNR_Bypass; ++ MS_U32 reg_snr_cnt; ++ ++ reg_snr_cnt = (MS_U32)MApi_XC_R2BYTEMSK(REG_SC_BK0B_77_L, 0xFF); ++ ++ if(u32MotionValue <= DYNAMIC_SNR_TH) ++ { ++ s32DynamicSnrCnt = 0; ++ } ++ else ++ { ++ if(s32DynamicSnrCnt < 65535) ++ s32DynamicSnrCnt++; ++ } ++ ++ if(s32DynamicSnrCnt >= (MS_S32)reg_snr_cnt) ++ { ++ u8SNR_Bypass = 0; // SNR enable ++ ++#if (DBG_DYNAMIC_SNR) ++ s32CurrentLevel = 1; ++#endif ++ } ++ else ++ { ++ u8SNR_Bypass = 1; // SNR disable ++ ++#if (DBG_DYNAMIC_SNR) ++ s32CurrentLevel = 2; ++#endif ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_70_L, (MS_U16)u8SNR_Bypass, 0xFF); ++ ++#if (DBG_DYNAMIC_SNR) ++ if(s32CurrentLevel != s32LastLevel) ++ { ++ if(s32CurrentLevel == 1) ++ printf("SNR = Enable[%x]\n", s32CurrentLevel); ++ else ++ printf("SNR = Disable[%x]\n", s32CurrentLevel); ++ ++ s32LastLevel = s32CurrentLevel; ++ } ++#endif ++} ++ ++/******************************************************************************/ ++///FantasticDNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++void MDrv_SC_fantastic_dnr(void) ++{ ++ static MS_S32 s32Cnt = 0; ++ MS_U8 u8DNR_TblY_0L, u8DNR_TblY_0H, u8DNR_TblY_1L, u8DNR_TblY_1H; ++ MS_U8 u8DNR_TblY_2L, u8DNR_TblY_2H, u8DNR_TblY_3L, u8DNR_TblY_3H; ++ ++ s32Cnt++; ++ ++ if(s32Cnt % 2 == 0) ++ { ++ u8DNR_TblY_0L = 0xDE; ++ u8DNR_TblY_0H = 0xDD; ++ u8DNR_TblY_1L = 0x79; ++ u8DNR_TblY_1H = 0x67; ++ u8DNR_TblY_2L = 0x56; ++ u8DNR_TblY_2H = 0x45; ++ u8DNR_TblY_3L = 0x11; ++ u8DNR_TblY_3H = 0x00; ++ } ++ else ++ { ++ u8DNR_TblY_0L = 0xCD; ++ u8DNR_TblY_0H = 0x39; ++ u8DNR_TblY_1L = 0x34; ++ u8DNR_TblY_1H = 0x11; ++ u8DNR_TblY_2L = 0x00; ++ u8DNR_TblY_2H = 0x00; ++ u8DNR_TblY_3L = 0x00; ++ u8DNR_TblY_3H = 0x00; ++ } ++ MApi_XC_W2BYTE(REG_SC_BK06_40_L, ((MS_U16)u8DNR_TblY_0L | (((MS_U16) u8DNR_TblY_0H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_41_L, ((MS_U16)u8DNR_TblY_1L | (((MS_U16) u8DNR_TblY_1H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_42_L, ((MS_U16)u8DNR_TblY_2L | (((MS_U16) u8DNR_TblY_2H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_43_L, ((MS_U16)u8DNR_TblY_3L | (((MS_U16) u8DNR_TblY_3H) << 8))); ++ ++} ++ ++/******************************************************************************/ ++///Dynamic DNR ++///@param u32MotionValue \ IN: Motion value ++/******************************************************************************/ ++#define DYNAMIC_DNR_TH 1000 ++void MDrv_SC_dynamic_dnr(MS_U32 u32MotionValue) ++{ ++ static MS_S32 s32ZeroCnt = 0; ++ static MS_S32 s32StillCnt = 0; ++ MS_U8 u8DNR_TblY_0L, u8DNR_TblY_0H, u8DNR_TblY_1L, u8DNR_TblY_1H; ++ MS_U8 u8DNR_TblY_2L, u8DNR_TblY_2H, u8DNR_TblY_3L, u8DNR_TblY_3H; ++ ++ if(u32MotionValue <= DYNAMIC_DNR_TH) ++ { ++ if(s32StillCnt < 65535) ++ s32StillCnt++; ++ } ++ else ++ { ++ s32StillCnt = 0; ++ } ++ ++ if(u32MotionValue == 0) ++ { ++ if(s32ZeroCnt < 65535) ++ s32ZeroCnt++; ++ } ++ else ++ { ++ s32ZeroCnt = 0; ++ } ++ ++ if(s32ZeroCnt >= 18) ++ { ++ u8DNR_TblY_0L = 0xDE; ++ u8DNR_TblY_0H = 0xDD; ++ u8DNR_TblY_1L = 0x79; ++ u8DNR_TblY_1H = 0x67; ++ u8DNR_TblY_2L = 0x56; ++ u8DNR_TblY_2H = 0x45; ++ u8DNR_TblY_3L = 0x11; ++ u8DNR_TblY_3H = 0x00; ++ } ++ else if(s32StillCnt >= 8) //still ++ { ++ u8DNR_TblY_0L = 0xCE; ++ u8DNR_TblY_0H = 0xAC; ++ u8DNR_TblY_1L = 0x78; ++ u8DNR_TblY_1H = 0x34; ++ u8DNR_TblY_2L = 0x12; ++ u8DNR_TblY_2H = 0x00; ++ u8DNR_TblY_3L = 0x00; ++ u8DNR_TblY_3H = 0x00; ++ ++ } ++ else //moving ++ { ++ u8DNR_TblY_0L = 0xCD; ++ u8DNR_TblY_0H = 0x39; ++ u8DNR_TblY_1L = 0x34; ++ u8DNR_TblY_1H = 0x11; ++ u8DNR_TblY_2L = 0x00; ++ u8DNR_TblY_2H = 0x00; ++ u8DNR_TblY_3L = 0x00; ++ u8DNR_TblY_3H = 0x00; ++ } ++ MApi_XC_W2BYTE(REG_SC_BK06_40_L, ((MS_U16)u8DNR_TblY_0L | (((MS_U16) u8DNR_TblY_0H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_41_L, ((MS_U16)u8DNR_TblY_1L | (((MS_U16) u8DNR_TblY_1H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_42_L, ((MS_U16)u8DNR_TblY_2L | (((MS_U16) u8DNR_TblY_2H) << 8))); ++ MApi_XC_W2BYTE(REG_SC_BK06_43_L, ((MS_U16)u8DNR_TblY_3L | (((MS_U16) u8DNR_TblY_3H) << 8))); ++ ++} ++ ++void MDrv_SC_dynamic_film_mode(void) ++{ ++ MS_U8 u8Value; ++ MS_U16 u16_unmatch_3; ++ static MS_U8 u8PrevLuma, u8_unmatch_3_Cnt; ++ static MS_U16 _u16BackupReg0x10 = 0; ++ static MS_U16 _u16BackupReg0x24 = 0; ++ static MS_BOOL _bEnableFilmMode = FALSE; ++ XC_ApiStatus stXCStatus; ++ ++ MS_U32 u32MotionValue; ++ ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ if(stXCStatus.bDoneFPLL && _bEnableFilmMode) ++ { ++ _bEnableFilmMode = FALSE; ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, _u16BackupReg0x10, BIT(14)|BIT(15)); //f2 22/32 film mode enable ++ if(g_bAnyCandenceEnable) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, _u16BackupReg0x24, BIT(15)); //film any cadance enable f2 ++ } ++ } ++ ++ if(stXCStatus.bInterlace) ++ { ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(3)))//only active at Film22 ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x02)<<8, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x02) << 8, 0xFF00); ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(4))) // only active at Film32 ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x06) << 8, 0x1F00); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F) << 8, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x10) << 8, 0xFF00); ++ } ++ ++///--> new for T3 ++ //T3 add new feature for film mode to enhance the film lock or not ++ MApi_XC_FilmMode_P(); ++///--> end ++ } ++ ++ #if 0 ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3 + MApi_XC_DLC_GetAverageValue()) >> 2); ++ #else ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3) >> 2); ++ #endif ++ ++ u8PrevLuma = u8Value; ++ u32MotionValue = MDrv_SC_read_motion_value1(); ++ if(u32MotionValue < 1200) ++ { ++ if(u8Value < 0x48) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x00); ++ } ++ else if((u8Value<0x88)&(u8Value >= 0x48)) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x0011); ++ } ++ else ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x1111); ++ } ++ } ++ else ++ { ++ if(u8Value < 0x48) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x2222); ++ } ++ else if((u8Value<0x88)&(u8Value >= 0x48)) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x5555); ++ } ++ else ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0xAAAA); ++ } ++ } ++#if 0 ++ // for Fulke 4 vertical line pattern ++ ++ if(ucValue < 0x18) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, 0x1000, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_0C_L, 0x0400, 0xFFFF); ++ } ++#endif ++ ++ if( (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(14) ) == BIT(14) ) // Film22 On,f2 22 film mode enable ++ || (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(15) ) == BIT(15) ) ) // Film32 On,f2 32 film mode enable ++ { ++ if (!stXCStatus.bDoneFPLL) // Make not frame LOCKED then turn off FilmMode ++ { ++ _bEnableFilmMode = TRUE; ++ _u16BackupReg0x10 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_10_L, BIT(14)|BIT(15)); ++ _u16BackupReg0x24 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_24_L, BIT(15)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, 0x0, BIT(14)|BIT(15)); //f2 22/32 film mode disable ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, 0x0, BIT(15)); //film any cadance disable f2 ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, BIT(1), BIT(1)); //hardware film mode DISABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, BIT(1)|BIT(2), BIT(1) | BIT(2)); //software film mode DISABLE ++ } ++ else // Make sure frame LOCKED then turn on FilmMode ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); //hardware film mode ENABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); //software film mode ENABLE ++ ++ ///--> new add function for skip film mode in still pattern ++ if((!MApi_XC_R2BYTEMSK(REG_SC_BK12_03_L, BIT(1)))&&(!MApi_XC_R2BYTEMSK(REG_SC_BK0A_02_L, BIT(14)))) // 2R mode can't enter this loop ++ { ++ u16_unmatch_3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ if( (u16_unmatch_3 > 0x100) ) ++ u8_unmatch_3_Cnt = 0; ++ else if(u8_unmatch_3_Cnt == 0xFF) ++ u8_unmatch_3_Cnt = 0xFF; ++ else ++ u8_unmatch_3_Cnt = u8_unmatch_3_Cnt + 1; ++ ++ if(u8_unmatch_3_Cnt > 0x05) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0002, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0006, 0x0006); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0000, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0000, 0x0006); ++ } ++ } ++ } ++ } ++ else ++ { ++ // DEFAULT value of hardware and software film mode suggested by SY.Shih ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); ++ } ++} ++ ++ ++void MDrv_SC_film_driver(MS_U16 u16Width) ++{ ++ XC_ApiStatus stXCStatus; ++ static MS_U8 u8FilmCnt,u8_unmatch_3_Cnt; ++ static MS_U16 _u16BackupReg0x10 = 0; ++ static MS_U16 _u16BackupReg0x24 = 0; ++ static MS_BOOL _bEnableFilmMode = FALSE; ++ ++ MS_U32 u32Reg7C, u32Reg7D, u32Reg7E, u16_unmatch_3; ++ MS_BOOL verticalMovingU, sd_source=true; ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ u32Reg7C = MApi_XC_R2BYTE(REG_SC_BK2A_7C_L); ++ u32Reg7D = MApi_XC_R2BYTE(REG_SC_BK2A_7D_L); ++ u32Reg7E = MApi_XC_R2BYTE(REG_SC_BK2A_7E_L); ++ ++ // for all chip ++ if(u16Width >= 1280) ++ { ++ sd_source = false; ++ } ++ // for MCNR only ++ verticalMovingU = (u32Reg7E > 0x0100) && (u32Reg7E > 8 * u32Reg7C) && (u32Reg7E > 8 * u32Reg7D); ++ ++ ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ if(stXCStatus.bDoneFPLL && _bEnableFilmMode) ++ { ++ _bEnableFilmMode = FALSE; ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, _u16BackupReg0x10, BIT(14)|BIT(15)); //f2 22/32 film mode enable ++ if(g_bAnyCandenceEnable) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, _u16BackupReg0x24, BIT(15)); //film any cadance enable f2 ++ } ++ } ++ ++ if(stXCStatus.bInterlace) ++ { ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(3)))//only active at Film22 ++ { ++ if(sd_source) // SD: smaller counter 1 th easier to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x01) << 8, 0x1F00); ++ } ++ else // HD: bigger counter 1 th harder to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F)<<8, 0x1F00); ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x02) << 8, 0xFF00); ++ } ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(4))) // only active at Film32 ++ { ++ if(sd_source) // SD: smaller counter 1 th easier to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x06) << 8, 0x1F00); ++ } ++ else // HD: bigger counter 1 th harder to jump out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F)<<8, 0x1F00); ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x10) << 8, 0xFF00); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, ((MS_U16)0x1F) << 8, 0x1F00); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_05_L, ((MS_U16)0x10) << 8, 0xFF00); ++ } ++ ++///--> new for T3 ++ //T3 add new feature for film mode to enhance the film lock or not ++ MApi_XC_FilmMode_P(); ++///--> end ++ ++ if( (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(14) ) == BIT(14) ) // Film22 On,f2 22 film mode enable ++ || (MApi_XC_R2BYTEMSK( REG_SC_BK0A_10_L, BIT(15) ) == BIT(15) ) ) // Film32 On,f2 32 film mode enable ++ { ++ if (!stXCStatus.bDoneFPLL) // Make not frame LOCKED then turn off FilmMode ++ { ++ _bEnableFilmMode = TRUE; ++ _u16BackupReg0x10 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_10_L, BIT(14)|BIT(15)); ++ _u16BackupReg0x24 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_24_L, BIT(15)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_10_L, 0x0, BIT(14)|BIT(15)); //f2 22/32 film mode disable ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, 0x0, BIT(15)); //film any cadance disable f2 ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, BIT(1), BIT(1)); //hardware film mode DISABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, BIT(1)|BIT(2), BIT(1) | BIT(2)); //software film mode DISABLE ++ } ++ else // Make sure frame LOCKED then turn on FilmMode ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); //hardware film mode ENABLE ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); //software film mode ENABLE ++ ++ ///--> new add function for skip film mode in still pattern ++ if((!MApi_XC_R2BYTEMSK(REG_SC_BK12_03_L, BIT(1)))&&(!MApi_XC_R2BYTEMSK(REG_SC_BK0A_02_L, BIT(14)))) // 2R mode can't enter this loop ++ { ++ u16_unmatch_3 = MApi_XC_R2BYTE(REG_SC_BK0A_0B_L); ++ ++ if((u16_unmatch_3 > 0x100)) ++ u8_unmatch_3_Cnt = 0; ++ else if(u8_unmatch_3_Cnt == 0xFF) ++ u8_unmatch_3_Cnt = 0xFF; ++ else ++ u8_unmatch_3_Cnt = u8_unmatch_3_Cnt + 1; ++ ++ ///--> Jump out Film for LG tower ++ if( !verticalMovingU ) ++ u8FilmCnt = 0; ++ else if(u8FilmCnt == 0xFF) ++ u8FilmCnt = 0xFF; ++ else ++ u8FilmCnt = u8FilmCnt + 1; ++ ++ ++ if(u8FilmCnt>0x05) // vertical moving, fake out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0002, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0006, 0x0006); ++ } ++ else if(u8_unmatch_3_Cnt > 0x05) // still video, fake out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0002, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0006, 0x0006); ++ } ++ else // default setting, turn off fake out ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0x0000, 0x0002); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0x0000, 0x0006); ++ } ++ } ++ } ++ } ++ else ++ { ++ // DEFAULT value of hardware and software film mode suggested by SY.Shih ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_1E_L, 0, BIT(1)); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_21_L, 0, BIT(1) | BIT(2)); ++ } ++ ++ ++///--> end ++ ++#if 0 ++ if(true == verticalMovingU) ++ { ++ MApi_XC_W2BYTE(REG_SC_BK0A_02_L, 0x2122); ++ MApi_XC_W2BYTE(REG_SC_BK0A_0C_L, 0x2222); ++ } ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_02_L, 0x0000, 0x2000); ++#endif ++ // for debug usage ++ //MApi_XC_W2BYTE(REG_SC_BK22_7A_L, 0x1000); ++ //MApi_XC_W2BYTE(REG_SC_BK20_1D_L, 0x0000); ++ ++ } // end interlace loop ++} ++ ++void MDrv_SC_Janus_DHD_driver(void) ++{ ++ // dhd shining line patch ++ static MS_U32 u32videoCnt = 0; ++ ++ if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(3))) // film22 ++ u32videoCnt = 0; ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(4))) // film32 ++ u32videoCnt = 0; ++ else if(MApi_XC_R2BYTEMSK(REG_SC_BK0A_21_L, BIT(6))) ++ u32videoCnt = 0; ++ else if(u32videoCnt >= 10000) ++ u32videoCnt = 10000; ++ else ++ u32videoCnt++; ++ ++ if(u32videoCnt >= 60) // 2 sec ++ { ++ // turn on dhd, 6R ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_05_L, 0x8000, 0x8000); // 6R ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, 0x0001, 0x0001); // dhd on ++ } ++ else ++ { ++ // turn off dhd, 4R ++ MApi_XC_W2BYTEMSK(REG_SC_BK12_05_L, 0x0000, 0x8000); // 4R ++ MApi_XC_W2BYTEMSK(REG_SC_BK05_20_L, 0x0000, 0x0001); // dhd off ++ } ++ ++} ++ ++#define HD_ACT_TH 10 ++#define HDSDD_SPEED 1 ++#define HDSDD_DIV 0 ++#define HD_SPEED 2 ++#define SD_SPEED 8 ++ ++void MDrv_SC_SDHD_DETECT_driver(void) ++{ ++ MS_U8 u8Value; ++ MS_U16 u16MinPixel, u16MaxPixel, MaxMinPixel; ++ MS_U32 HDcnt_Act; ++ //MS_U32 HDcnt_NonAct; ++ MS_U32 SDcnt_Act; ++ //MS_U32 SDcnt_NonAct; ++ static MS_U16 HD_ConfirmCnt = 0xFF; // 0x7FFF == 0 ++ static MS_U8 u8PrevLuma = 0; ++ static MS_U16 u16PrevMinPixel = 0; ++ static MS_U16 u16PrevMaxPixel = 0; ++ MS_U32 HD_ConfirmCnt_Reg; ++ MS_U16 HDSDD_Det_threshold, HDSDD_Det_offset; ++ ++ //HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ //SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ HDSDD_Det_offset = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ //printf("====HDcnt_Act===%x\n",HDcnt_Act); ++ //printf("====SDcnt_Act===%x\n",SDcnt_Act); ++ //printf("====HDcnt_NonAct===%x\n",HDcnt_NonAct); ++ //printf("====SDcnt_NonAct===%x\n",SDcnt_NonAct); ++ ++ #if 0 ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3 + MApi_XC_DLC_GetAverageValue()) >> 2); ++ #else ++ u8Value = (MS_U8)((MS_U32)((MS_U32)u8PrevLuma * 3) >> 2); ++ #endif ++ u8PrevLuma = u8Value; ++ ++ u16MaxPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0x00FF); ++ u16MaxPixel = (u16PrevMaxPixel * 3 + u16MaxPixel) >> 2; ++ u16PrevMaxPixel = u16MaxPixel; ++ ++ u16MinPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0xFF00) >> 8; ++ u16MinPixel = (u16PrevMinPixel * 3 + u16MinPixel) >> 2; ++ u16PrevMinPixel = u16MinPixel; ++ ++ MaxMinPixel = u16MaxPixel - u16MinPixel; ++ //printf("===u8MinPixel=%x==\n",u16MinPixel); ++ //printf("===MaxMinPixel=%x==\n",MaxMinPixel); ++ ++ if(u8Value >= 0xFF) ++ u8Value = 0xFF; ++ //printf("===AvgLuma=%x==\n",u8Value); ++ ++ HDSDD_Det_threshold = HDSDD_Det_offset + ((MaxMinPixel * 6) >> 2) + ((u8Value * 5) >> 2); ++ //printf("===HDSDD_Det_threshold=%x==\n",HDSDD_Det_threshold); ++ ++#if 0 ++ { ++ if(u8Value > 0x80) ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++ else if(u8Value > 0x40) ++ Cur_HDSDD_Det_threshold = ((u16HDSDD_Det_Threshold * 3) >> 2); ++ else if(u8Value > 0x20) ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold >> 1); ++ else ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold >> 2); ++ } ++ else ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++#endif ++ ++ if(HDSDD_Det_threshold >= 0xFFFF) ++ { ++ HDSDD_Det_threshold = 0xFFFF; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_71_L, (MS_U16)HDSDD_Det_threshold, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_72_L, (MS_U16)(HDSDD_Det_threshold >> 1), 0xFFFF); ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ ++ if((HDcnt_Act > HD_ACT_TH) && (SDcnt_Act != 0)) ++ { ++ if(HD_ConfirmCnt < HD_SPEED) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - HD_SPEED; ++ } ++ else if(SDcnt_Act != 0) //&& HDcnt_NonAct !=0) // && (HDcnt_NonAct < 0x90000)) ++ { ++ if(HD_ConfirmCnt > (0xFF - SD_SPEED)) ++ HD_ConfirmCnt = 0xFF; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt + SD_SPEED; ++ } ++ else ++ { ++ if(HD_ConfirmCnt < 1) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - 1; ++ } ++ ++ if(HD_ConfirmCnt > 0x80) ++ HD_ConfirmCnt_Reg = HD_ConfirmCnt - 0x80; ++ else ++ HD_ConfirmCnt_Reg = 0; ++ ++ HD_ConfirmCnt_Reg = (HD_ConfirmCnt_Reg * HDSDD_SPEED) >> HDSDD_DIV; ++ ++ if(HD_ConfirmCnt_Reg > 0x3F) ++ HD_ConfirmCnt_Reg = 0x3F; ++ ++ //printf("====HD_ConfirmCnt_Reg===%x\n",HD_ConfirmCnt_Reg); ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK23_54_L, (MS_U16)HD_ConfirmCnt_Reg, 0x003F); ++ ++} ++ ++void MDrv_SC_NEW_SDHD_DETECT_driver(void) ++{ ++ MS_U8 u8Value,FEATHER_CNT_TH; ++ MS_U16 u16MinPixel,u16MaxPixel, MaxMinPixel; ++ MS_U32 HDcnt_Act; ++ //MS_U32 HDcnt_NonAct; ++ MS_U32 FeatherCnt; ++ MS_U32 SDcnt_Act; ++ //MS_U32 SDcnt_NonAct; ++ static MS_U32 PreFeatherCnt = 0; ++ static MS_U16 HD_ConfirmCnt = 0xFF; // 0x7FFF == 0 ++ static MS_U8 u8PrevLuma = 0; ++ static MS_U16 u16PrevMinPixel = 0; ++ static MS_U16 u16PrevMaxPixel = 0; ++ MS_U32 HD_ConfirmCnt_Reg; ++ MS_U16 HDSDD_Det_threshold,HDSDD_Det_offset; ++ ++ //HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ //SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ HDSDD_Det_offset = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ FeatherCnt = MApi_XC_R2BYTE(REG_SC_BK23_56_L); //New add for A1 chip ++ FEATHER_CNT_TH = MApi_XC_R2BYTEMSK(REG_SC_BK22_7D_L, 0xFF00)>>8; ++ ++ //printf("====HDcnt_Act===%x\n",HDcnt_Act); ++ //printf("====SDcnt_Act===%x\n",SDcnt_Act); ++ //printf("====HDcnt_NonAct===%x\n",HDcnt_NonAct); ++ //printf("====SDcnt_NonAct===%x\n",SDcnt_NonAct); ++ ++ FeatherCnt = ( PreFeatherCnt*3 + FeatherCnt ) >> 2; ++ PreFeatherCnt = FeatherCnt; ++ ++ #if 0 ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3 + MApi_XC_DLC_GetAverageValue())>>2); ++ #else ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3)>>2); ++ #endif ++ ++ u8PrevLuma = u8Value; ++ ++ u16MaxPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0x00FF); ++ u16MaxPixel = (u16PrevMaxPixel*3 + u16MaxPixel ) >> 2; ++ u16PrevMaxPixel = u16MaxPixel; ++ ++ u16MinPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0xFF00)>>8; ++ u16MinPixel = (u16PrevMinPixel*3 + u16MinPixel ) >> 2; ++ u16PrevMinPixel = u16MinPixel; ++ ++ MaxMinPixel = u16MaxPixel - u16MinPixel; ++ //printf("===u8MinPixel=%x==\n",u16MinPixel); ++ //printf("===MaxMinPixel=%x==\n",MaxMinPixel); ++ ++ ++ if(u8Value>=0xFF) ++ u8Value = 0xFF; ++ //printf("===AvgLuma=%x==\n",u8Value); ++ ++ HDSDD_Det_threshold = HDSDD_Det_offset +((MaxMinPixel*6)>>2) + ((u8Value*5)>>2); ++ //printf("===HDSDD_Det_threshold=%x==\n",HDSDD_Det_threshold); ++ ++ #if 0 ++ { ++ if( u8Value > 0x80) ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++ else if( u8Value > 0x40) ++ Cur_HDSDD_Det_threshold = ((u16HDSDD_Det_Threshold*3)>>2); ++ else if( u8Value > 0x20) ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold>>1); ++ else ++ Cur_HDSDD_Det_threshold = (u16HDSDD_Det_Threshold>>2); ++ } ++ else ++ Cur_HDSDD_Det_threshold = u16HDSDD_Det_Threshold; ++ #endif ++ ++ if(HDSDD_Det_threshold >=0xFFFF) ++ { ++ HDSDD_Det_threshold=0xFFFF; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_71_L, (MS_U16)HDSDD_Det_threshold, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_72_L, (MS_U16)(HDSDD_Det_threshold>>1), 0xFFFF); ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ //SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ ++ ++ if( (HDcnt_Act > HD_ACT_TH) && (SDcnt_Act != 0) ) ++ { ++ if(HD_ConfirmCnt < HD_SPEED) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - HD_SPEED; ++ } ++ else if( (SDcnt_Act != 0) && (FeatherCnt > FEATHER_CNT_TH) )//&& HDcnt_NonAct !=0) // && (HDcnt_NonAct < 0x90000)) ++ { ++ if(HD_ConfirmCnt > (0xFF - SD_SPEED)) ++ HD_ConfirmCnt = 0xFF; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt + SD_SPEED;; ++ ++ } ++ else ++ { ++ if(HD_ConfirmCnt < 1) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - 1; ++ } ++ ++ if( HD_ConfirmCnt > 0x80 ) ++ HD_ConfirmCnt_Reg = HD_ConfirmCnt - 0x80; ++ else ++ HD_ConfirmCnt_Reg = 0; ++ ++ HD_ConfirmCnt_Reg = (HD_ConfirmCnt_Reg*HDSDD_SPEED) >> HDSDD_DIV; ++ ++ if( HD_ConfirmCnt_Reg > 0x3F ) ++ HD_ConfirmCnt_Reg = 0x3F; ++ ++ //Debug mode for SDHDD detection function ++#if 0 ++ if( HD_ConfirmCnt_Reg == 0x3F ) ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x1000, 0x1000); ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK22_7A_L, 0x0000, 0x1000); ++ ++#endif ++ //printf("====HD_ConfirmCnt_Reg===%x\n",HD_ConfirmCnt_Reg); ++ MApi_XC_W2BYTEMSK(REG_SC_BK23_54_L, (MS_U16)HD_ConfirmCnt_Reg, 0x003F); ++ ++} ++ ++ ++MS_U8 MDrv_SC_NEW_SDHD_DETECT_report(void) ++{ ++ MS_U8 u8Value; ++ MS_U16 u16MinPixel,u16MaxPixel, MaxMinPixel; ++ MS_U32 HDcnt_Act, FeatherCnt; ++ MS_U32 SDcnt_Act, SDcnt_NonAct; ++ static MS_U32 PreFeatherCnt = 0; ++ static MS_U16 HD_ConfirmCnt = 0xFF; // 0x7FFF == 0 ++ static MS_U8 u8PrevLuma = 0; ++ static MS_U16 u16PrevMinPixel = 0; ++ static MS_U16 u16PrevMaxPixel = 0; ++ MS_U32 HD_ConfirmCnt_Reg; ++ MS_U16 HDSDD_Det_threshold,HDSDD_Det_offset; ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ HDSDD_Det_offset = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK22_7F_L, 0xFFFF); ++ ++ FeatherCnt = MApi_XC_R2BYTE(REG_SC_BK23_56_L); //New add for A1 chip ++ //FEATHER_CNT_TH = MApi_XC_R2BYTEMSK(REG_SC_BK22_7D_L, 0xFF00)>>8; ++ //printf("====HDcnt_Act===%x\n",HDcnt_Act); ++ //printf("====SDcnt_Act===%x\n",SDcnt_Act); ++ //printf("====HDcnt_NonAct===%x\n",HDcnt_NonAct); ++ //printf("====SDcnt_NonAct===%x\n",SDcnt_NonAct); ++ ++ FeatherCnt = ( PreFeatherCnt*3 + FeatherCnt ) >> 2; ++ PreFeatherCnt = FeatherCnt; ++ ++ #if 0 ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3 + MApi_XC_DLC_GetAverageValue())>>2); ++ #else ++ u8Value=(MS_U8)((MS_U32)((MS_U32)u8PrevLuma*3)>>2); ++ #endif ++ u8PrevLuma = u8Value; ++ ++ u16MaxPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0x00FF); ++ u16MaxPixel = (u16PrevMaxPixel*3 + u16MaxPixel ) >> 2; ++ u16PrevMaxPixel = u16MaxPixel; ++ ++ u16MinPixel = MApi_XC_R2BYTEMSK(REG_SC_BK1A_0B_L, 0xFF00)>>8; ++ u16MinPixel = (u16PrevMinPixel*3 + u16MinPixel ) >> 2; ++ u16PrevMinPixel = u16MinPixel; ++ ++ MaxMinPixel = u16MaxPixel - u16MinPixel; ++ //printf("===u8MinPixel=%x==\n",u16MinPixel); ++ //printf("===MaxMinPixel=%x==\n",MaxMinPixel); ++ ++ if(u8Value>=0xFF) ++ u8Value = 0xFF; ++ //printf("===AvgLuma=%x==\n",u8Value); ++ ++ HDSDD_Det_threshold = HDSDD_Det_offset +((MaxMinPixel*6)>>2) + ((u8Value*5)>>2); ++ //printf("===HDSDD_Det_threshold=%x==\n",HDSDD_Det_threshold); ++ ++ if(HDSDD_Det_threshold >=0xFFFF) ++ { ++ HDSDD_Det_threshold=0xFFFF; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_71_L, (MS_U16)HDSDD_Det_threshold, 0xFFFF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK02_72_L, (MS_U16)(HDSDD_Det_threshold>>1), 0xFFFF); ++ ++ HDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_75_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_74_L); ++ SDcnt_Act = (MApi_XC_R2BYTE(REG_SC_BK02_77_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_76_L); ++ //HDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_79_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_78_L); ++ SDcnt_NonAct = (MApi_XC_R2BYTE(REG_SC_BK02_7B_L) << 16) + MApi_XC_R2BYTE(REG_SC_BK02_7A_L); ++ ++ if( (HDcnt_Act > HD_ACT_TH) && (SDcnt_Act != 0) ) ++ { ++ if(HD_ConfirmCnt < HD_SPEED) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - HD_SPEED; ++ } ++ else if( SDcnt_Act != 0 ) //*&& FeatherCnt > FEATHER_CNT_TH*/ )//&& HDcnt_NonAct !=0) // && (HDcnt_NonAct < 0x90000)) ++ { ++ if(HD_ConfirmCnt > (0xFF - SD_SPEED)) ++ HD_ConfirmCnt = 0xFF; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt + SD_SPEED; ++ } ++ else ++ { ++ if(HD_ConfirmCnt < 1) ++ HD_ConfirmCnt = 0; ++ else ++ HD_ConfirmCnt = HD_ConfirmCnt - 1; ++ } ++ ++ if( HD_ConfirmCnt > 0x80 ) ++ HD_ConfirmCnt_Reg = HD_ConfirmCnt - 0x80; ++ else ++ HD_ConfirmCnt_Reg = 0; ++ ++ HD_ConfirmCnt_Reg = (HD_ConfirmCnt_Reg*HDSDD_SPEED) >> HDSDD_DIV; ++ ++ if( HD_ConfirmCnt_Reg > 0x3F ) ++ HD_ConfirmCnt_Reg = 0x3F; ++ ++ return ((MS_U8)(HD_ConfirmCnt_Reg&0x003F)); ++} ++ ++ ++#if (Auto_DeBlock_En) ++#define ADBW_HD_Loop_Ini_Start 40 ++#define ADBW_HD_Max_Range_End 1440 ++#define ADBW_SD_Loop_Ini_Start 20 ++#define ADBW_SD_Max_Range_End 720 ++static MS_U32 Auto_DBK_Width_val = 8; ++static MS_U32 Auto_DBK_Width_val_tmp = 32; // format is xxxxx.xx ++static MS_U32 Pre_DBK_Width_val = 8; ++ ++void MDrv_SC_Auto_Detect_Blocking_Width_driver(MS_U8 u8SD2HDValue) ++{ ++ int data_ack_en; ++ //int temp_data; ++ int blkwidth_data[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; ++ int blkwidth_s_data[32] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; ++ long blockiness_data[1440]; ++ MS_BOOL blocking_peakidx[1440]; ++ int bin; ++ int check_width = MApi_XC_R2BYTEMSK(REG_SC_BK12_0F_L, 0xFFFF); ++ int Loop_Ini_Start = (check_width>0x700) ? ADBW_HD_Loop_Ini_Start : ADBW_SD_Loop_Ini_Start; ++ int Max_Range_End = (check_width>0x700) ? ADBW_HD_Max_Range_End : ADBW_SD_Max_Range_End; ++ long fme_blockiness; ++ long frame_maxin_d = 0; ++ long local_maxin_d; ++ int left7,right7; ++ int left2 = 0; ++ int right2 = 0; ++ int left1,right1; ++ int bestblock_width = 8; ++ MS_U32 iir_strength = 2; ++ MS_U8 NMY_DBK_en = 1; ++ //MS_U8 NMY_DBK_gain = 0x10; ++ MS_U32 DBK_frame_blockiness = 0; ++ MS_U32 DBK_frame_blockiness_sum = 0; ++ static MS_U32 DBK_frame_blockiness_iir = 0; ++ MS_U16 test_dummy = MApi_XC_R2BYTEMSK(REG_SC_BK30_01_L, 0x7FFF); ++ MS_U16 test_dummy2 = MApi_XC_R2BYTEMSK(REG_SC_BK30_02_L, 0xFFFF); ++ MS_U16 test_dummy3 = MApi_XC_R2BYTEMSK(REG_SC_BK30_03_L, 0x00FF); ++ MS_U16 dbk_debug_enable = MApi_XC_R2BYTEMSK(REG_SC_BK30_03_L, 0xFFFF)>>15; ++ MS_U16 dbk_iir_diff_thrd = MApi_XC_R2BYTEMSK(REG_SC_BK30_03_L, 0x7F00)>>8; ++ static MS_U16 NMR_Ctrl=0; ++ static MS_U16 NMR_Strength=0; ++ MS_U32 iir_strength_NM = 2; ++ MS_S32 DBK_frame_blockiness_diff=0; ++ //MS_S32 DBK_frame_blockiness_offset=0; ++ static MS_U32 pre_DBK_frame_blockiness=0; ++ int peak_from_blkwidth_data=0; ++ ++ int loc_max = 0; ++ int loc_min = 65535; ++ int cnt; ++ int bestblock_cnt_m = 0; ++ int bestblock_lf1 = 0; ++ int bestblock_idx = 0; ++ int bestblock_rt1 = 0; ++ int bestblock_cnt_m2 = 0; ++ int bestblock_idx2 = 0; ++ int bestblock_cnt_m3 = 0; ++ int bestblock_idx3 = 0; ++ int start_idx = 0; ++ int Currx2_0 = 0; ++ int Lf12x1_1 = 0; ++ int Rt12x1_1 = 0; ++ int Currx1 = 0; ++ int Loc_Maxx0_99 = 0; ++ int local_maxin_dx3= 0; ++ int Pre_DBK_Width_val_tmp; ++ ++ ++ MS_BOOL condition1 = FALSE; ++ MS_BOOL condition2 = FALSE; ++ MS_BOOL condition3 = FALSE; ++ MS_BOOL condition4 = FALSE; ++ ++ ++ // setting HD mode enable ++ if(check_width>0x700) ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_41_L, 0x1, 0x0001); // HD mode ++ else ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_41_L, 0x0, 0x0001); // SD mode ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_38_L, 0x4, 0x0004); // setting vertical iir enable ++ ++ //--------- Blockiness Histogram Request start ---------// ++ ++ // write 0 to request register ++ //MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 0, 0x0001); ++ // write 1 to request register ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 1, 0x0001); ++ ++ //--------- Blockiness Histogram Request end ---------// ++ ++ //--------- Blockiness Histogram Acknowledge start ---------// ++ ++ data_ack_en = MApi_XC_R2BYTEMSK(REG_SC_BK0C_0D_L, 0x0002); ++ ++ //--------- Blockiness Histogram Acknowledge end ---------// ++ ++ //--------- Function Process start ---------// ++ if(data_ack_en) ++ { ++ // write 1 to sram_io_en register ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 0x100, 0x0100); ++ for(bin = 0; bin < Max_Range_End; bin++) ++ { ++ // write address ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0E_L, (MS_U16)(0x8000 + bin), 0xFFFF); ++ // read data from selected address ++ blockiness_data[bin] = MApi_XC_R2BYTEMSK(REG_SC_BK0C_0F_L, 0xFFFF); ++ //printf("blockiness[%4d] is %d\n",bin,blockiness_data[bin]); ++ } ++ ++ //printf("blockiness is %d\n",bin); ++ //read frame blockiness data ++ fme_blockiness = ((MApi_XC_R2BYTEMSK(REG_SC_BK0C_61_L, 0xFFFF))<<16) | (MApi_XC_R2BYTEMSK(REG_SC_BK0C_60_L, 0xFFFF)); // frame blockiness data report 32 bit ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_0D_L, 0, 0x0001); ++ //printf("fme_blockiness is %d\n\n",fme_blockiness); ++ ++ //------- find the max local minmax difference start -------// ++ for(bin = Loop_Ini_Start; bin < (Max_Range_End - 40); bin++) ++ { ++ left2 = bin - 2; ++ right2 = bin + 2; ++ ++ loc_max = 0; ++ loc_min = 65535; ++ ++ for(cnt = left2; cnt <= right2; cnt++) ++ { ++ //find max ++ if(blockiness_data[cnt] > loc_max) ++ loc_max = blockiness_data[cnt]; ++ ++ //find min ++ if(blockiness_data[cnt] < loc_min) ++ loc_min = blockiness_data[cnt]; ++ } ++ ++ if(loc_max > loc_min) ++ local_maxin_d = loc_max - loc_min; ++ else ++ local_maxin_d = 0; ++ ++ if(local_maxin_d > frame_maxin_d) ++ frame_maxin_d = local_maxin_d; ++ ++ } ++ //------- find the max local minmax difference end -------// ++ ++ for(bin = 0; bin < Max_Range_End; bin++) ++ blocking_peakidx[bin] = false; ++ ++ //------- find peak index start -------// ++ for(bin = 0; bin < (Max_Range_End - 40); bin++) ++ { ++ left7 = (bin < 7) ? 0 : bin - 7; ++ left1 = (bin < 1) ? 0 : bin - 1; ++ right1 = bin + 1; ++ right7 = bin + 7; ++ ++ loc_max = 0; ++ loc_min = 65535; ++ ++ for(cnt = left7; cnt <= right7; cnt++) ++ { ++ //find max ++ if(blockiness_data[cnt] > loc_max) ++ loc_max = blockiness_data[cnt]; ++ ++ //find min ++ if(blockiness_data[cnt] < loc_min) ++ loc_min = blockiness_data[cnt]; ++ } ++ ++ if(loc_max > loc_min) ++ local_maxin_d = loc_max - loc_min; ++ else ++ local_maxin_d = 0; ++ ++ Currx2_0 = (blockiness_data[bin]<<1); // data x 2 ++ Lf12x1_1 = ((blockiness_data[left1] + blockiness_data[left2])*11)/10; // data x 1.1 ++ Rt12x1_1 = ((blockiness_data[right1] + blockiness_data[right2])*11)/10; // data x 1.1 ++ Currx1 = blockiness_data[bin]; // data x 1 ++ Loc_Maxx0_99 = (loc_max*85)/100; // data x 0.85 // ori is data x 0.99 ++ local_maxin_dx3 = local_maxin_d*3; // data x 3 ++ ++ if((Currx2_0>Lf12x1_1)&&(Currx2_0>Rt12x1_1)&&(Currx1>Loc_Maxx0_99)&&(local_maxin_dx3>frame_maxin_d) && (blockiness_data[bin] > blockiness_data[left1]) && (blockiness_data[bin] > blockiness_data[right1])) ++ blocking_peakidx[cnt] = true; ++ } ++ //------- find peak index end -------// ++ ++ //------- find best block width start -------// ++ start_idx = 0; ++ ++ for(bin = 0; bin < Max_Range_End; bin++) ++ { ++ if((blocking_peakidx[bin]==true)&&(bin!=start_idx)) ++ { ++ cnt = bin - start_idx; ++ if( cnt < 31) ++ blkwidth_data[cnt] += 1; ++ ++ start_idx = bin; ++ } ++ } ++ //------- find best block width end -------// ++ peak_from_blkwidth_data = 0; ++ for(bin = 8; bin < 31; bin ++) ++ { ++ if( blkwidth_data[bin]> peak_from_blkwidth_data ) ++ peak_from_blkwidth_data = blkwidth_data[bin]; ++ } ++ //------- summarize 1x3 on blkwidth start -------// ++ ++ for(bin = 5; bin < 31; bin ++) ++ { ++ left1 = (bin < 1) ? 0 : bin - 1; ++ right1 = (bin >= 31) ? 30 : bin + 1; ++ ++ loc_max = 0; ++ ++ for(cnt = left1; cnt <= right1; cnt++) ++ { ++ //find max ++ if(blkwidth_data[cnt] > loc_max) ++ loc_max = blkwidth_data[cnt]; ++ } ++ ++ if(blkwidth_data[bin] > (loc_max>>1)) ++ blkwidth_s_data[bin] = blkwidth_data[left1] + blkwidth_data[bin] + blkwidth_data[right1]; ++ } ++ ++ //------- summarize 1x3 on blkwidth end -------// ++ ++ //------- find the 1st max block width start -------// ++ ++ for(bin = 5; bin < 31; bin++) ++ { ++ if(blkwidth_s_data[bin] > bestblock_cnt_m) ++ { ++ bestblock_cnt_m = blkwidth_s_data[bin]; ++ bestblock_idx = bin; ++ } ++ } ++ ++ bestblock_lf1 = bestblock_idx - 1; ++ bestblock_rt1 = bestblock_idx + 1; ++ blkwidth_s_data[bestblock_idx] = 0; ++ ++ //printf("1st width is %d | cnt is %d\n",bestblock_idx,bestblock_cnt_m); ++ //------- find the 1st max block width end -------// ++ ++ //------- find the 2nd max block width start -------// ++ ++ ++ for(bin = 5; bin < 31; bin++) ++ { ++ if((blkwidth_s_data[bin] > bestblock_cnt_m2)&&((bin > bestblock_rt1) || (bin < bestblock_lf1))) ++ { ++ bestblock_cnt_m2 = blkwidth_s_data[bin]; ++ bestblock_idx2 = bin; ++ } ++ } ++ ++ bestblock_lf1 = bestblock_idx2 - 1; ++ bestblock_rt1 = bestblock_idx2 + 1; ++ blkwidth_s_data[bestblock_idx2] = 0; ++ ++ //printf("2nd width is %d | cnt is %d\n",bestblock_idx2,bestblock_cnt_m2); ++ //------- find the 2nd max block width end -------// ++ ++ //------- find the 3rd max block width start -------// ++ ++ ++ for(bin = 5; bin < 31; bin++) ++ { ++ if((blkwidth_s_data[bin] > bestblock_cnt_m3)&&((bin > bestblock_rt1) || (bin < bestblock_lf1))) ++ { ++ bestblock_cnt_m3 = blkwidth_s_data[bin]; ++ bestblock_idx3 = bin; ++ } ++ } ++ ++ //printf("3rd width is %d | cnt is %d\n",bestblock_idx3,bestblock_cnt_m3); ++ //------- find the 3rd max block width end -------// ++ ++ //printf("SD2HD is %d\n",u8SD2HDValue); ++ ++ if((u8SD2HDValue>=60)&&(check_width>0x700)) ++ { ++ if((bestblock_idx>=20)&&(bestblock_idx<=22)) ++ { ++ bestblock_cnt_m = 100; ++ //printf("SD2HD is 1st\n"); ++ } ++ else if((bestblock_idx2>=20)&&(bestblock_idx2<=22)) ++ { ++ bestblock_idx = bestblock_idx2; ++ bestblock_cnt_m = 100; ++ //printf("SD2HD is 2nd\n"); ++ } ++ else if((bestblock_idx3>=20)&&(bestblock_idx3<=22)) ++ { ++ bestblock_idx = bestblock_idx3; ++ bestblock_cnt_m = 100; ++ //printf("SD2HD is 3rd\n"); ++ } ++ } ++ ++ //------- calculate best block width start -------// ++ condition1 = ((bestblock_cnt_m<<1) >= (bestblock_cnt_m2*3)) ? true : false; // m1 >= m2*1.5 ++ condition2 = ((bestblock_cnt_m ) >= (bestblock_cnt_m3<<1)) ? true : false; // m1 >= m3*2 ++ condition3 = (bestblock_cnt_m > 15) ? true : false; ++ condition4 = (bestblock_idx > 6) ? true : false; ++ ++ if(condition1&& condition2&&condition3&&condition4) ++ { ++ bestblock_width = bestblock_idx; ++ ++ if((u8SD2HDValue==00)&&(check_width>0x700)&&(bestblock_width==16)) ++ bestblock_width = 8; ++ ++ Pre_DBK_Width_val = bestblock_width; ++ //printf("##bestblock_width is %d##\n",bestblock_width); ++ } ++ //printf("Pre_DBK_Width_val is %d\n",Pre_DBK_Width_val); ++ ++ // iir ++ Pre_DBK_Width_val_tmp = (Pre_DBK_Width_val<<2); // format is xxxxx.xx ++ Auto_DBK_Width_val_tmp = ((iir_strength*Pre_DBK_Width_val_tmp) + (8-iir_strength)*Auto_DBK_Width_val_tmp)/8; // format is xxxxx.xx ++ Auto_DBK_Width_val = (Auto_DBK_Width_val_tmp>>2); // format is xxxxx.0 ++ ++ if(Auto_DBK_Width_val<=8) ++ { ++ Auto_DBK_Width_val = 8; ++ left1 = 8; ++ right1 = 8; ++ } ++ else ++ { ++ left1 = (Auto_DBK_Width_val < 1) ? 0 : Auto_DBK_Width_val - 1; ++ right1 = (Auto_DBK_Width_val >=31) ? 31 : Auto_DBK_Width_val + 1; ++ } ++ ++ // write interval left && interval right ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_39_L, (MS_U16)((right1<<8)|left1), 0xFFFF); ++ //------- calculate best block width end -------// ++ //printf("Final width is %d <=====\n",Auto_DBK_Width_val); ++ ++ if(data_read) ++ { ++ NMR_Ctrl = MApi_XC_R2BYTEMSK(REG_SC_BK0C_50_L, 0x0001); ++ NMR_Strength = MApi_XC_R2BYTEMSK(REG_SC_BK0C_54_L, 0x003F); ++ data_read = false; ++ } ++ ++ DBK_frame_blockiness_sum=0; ++ for(bin = 0; bin < (Max_Range_End ); bin=bin+Auto_DBK_Width_val) ++ { ++ loc_max = 0; ++ loc_min = 0xFFFFFFFF; ++ ++ for(cnt = 0; ((MS_U32)cnt) <= Auto_DBK_Width_val-1; cnt++) ++ { ++ //find max ++ if(((MS_U32)blockiness_data[bin+cnt] > ((MS_U32)loc_max))&&((bin+cnt)<1440)) ++ loc_max = (MS_U32)blockiness_data[bin+cnt]; ++ ++ //find min ++ if(((MS_U32)blockiness_data[bin+cnt] < ((MS_U32)loc_min))&&((bin+cnt)<1440)) ++ loc_min = (MS_U32)blockiness_data[bin+cnt]; ++ } ++ ++ if(loc_max > loc_min) ++ { ++ local_maxin_d = loc_max - loc_min; ++ } ++ else ++ { ++ local_maxin_d = 0; ++ } ++ DBK_frame_blockiness_sum += local_maxin_d; ++ } ++ //printf("====DBK_frame_blockiness_sum= %x \n",DBK_frame_blockiness_sum); ++ ++ DBK_frame_blockiness = DBK_frame_blockiness_sum*Auto_DBK_Width_val / (Max_Range_End) ; ++ ++ //printf("====DBK_frame_blockiness= %x \n",DBK_frame_blockiness); ++ ++ if(pre_DBK_frame_blockiness >= DBK_frame_blockiness) ++ { ++ DBK_frame_blockiness_diff = pre_DBK_frame_blockiness - DBK_frame_blockiness; ++ } ++ else ++ { ++ DBK_frame_blockiness_diff = DBK_frame_blockiness - pre_DBK_frame_blockiness; ++ } ++ /* ++ if(u8SD2HDValue>=60) ++ { ++ DBK_frame_blockiness_offset= 0xB00; ++ } ++ else ++ { ++ DBK_frame_blockiness_offset = 0 ; ++ } ++ */ ++ ++ if( DBK_frame_blockiness_diff > ((dbk_iir_diff_thrd<<8) )) ++ { ++ iir_strength_NM = 8; ++ } ++ else ++ { ++ iir_strength_NM = 2; ++ } ++ ++ DBK_frame_blockiness_iir = (DBK_frame_blockiness*iir_strength_NM+ DBK_frame_blockiness_iir*(8-iir_strength_NM))/8; ++ ++ if(dbk_debug_enable) ++ { ++ printf("DBK_frame_blockiness_sum is %lx <=====\n",DBK_frame_blockiness_sum); ++ printf("DBK_frame_blockiness is %lx <=====\n",DBK_frame_blockiness); ++ printf("DBK_frame_blockiness_iir is %lx <=====\n",DBK_frame_blockiness_iir); ++ printf("u8SD2HDValue is %x <=====\n",u8SD2HDValue); ++ } ++ ++ pre_DBK_frame_blockiness = DBK_frame_blockiness; ++ ++ if((fme_blockiness>= (test_dummy3 <<8)) && (peak_from_blkwidth_data>=10) ) //0x100000 // multiburst pan ++ { ++ if(DBK_frame_blockiness_iir>= (test_dummy)) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMY_DBK_en, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, 0x1F, 0x003F); ++ } ++ else if((DBK_frame_blockiness_iir< (test_dummy)) && (DBK_frame_blockiness_iir >= (test_dummy2))) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMY_DBK_en, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, 0x15, 0x003F); ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMR_Ctrl, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, NMR_Strength, 0x003F); ++ } ++ } ++ else ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_50_L, NMR_Ctrl, 0x0001); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_54_L, NMR_Strength, 0x003F); ++ } ++ ++ //printf("====End==%lx=\n",MsOS_GetSystemTime()); ++ } ++ //--------- Function Process end ---------// ++} ++#endif ++ ++static MS_U32 md_adjust_level_iir = 0; ++static MS_U32 psnr_std_level_thrd_iir = 0; ++static MS_U32 dnr_std_thrd_iir = 0; ++static MS_U32 luma_sum_pre=0; ++ ++//static MS_U32 hismatch_level_thrd_iir=0 ; ++static MS_U16 dnr_md_high_thrd_level_iir =0; ++static MS_U16 dnr_md_low_thrd_level_iir =0; ++ ++//void MDrv_SC_HISNR_T9_driver(U16 u16Width, U16 u16Height) ++void MDrv_SC_HISNR_driver(MS_U16 u16Width, MS_U16 u16Height) ++{ ++ MS_BOOL histogram_ack_en=0; ++ MS_U16 noise_histogram[16]; ++ MS_U16 noise_histogram_scaled[16]; ++ MS_U32 scaled_ratio = 4; ++ //MS_U16 rounding_bit=0; ++ MS_U16 bin; ++ // define value ++ MS_U16 noise_level_low_thrd_0 = 0x0; ++ MS_U16 noise_level_low_thrd_1 = 0x18; ++ MS_U16 noise_level_low_thrd_2 = 0x28; ++ MS_U16 noise_level_low_thrd_3 = 0x38; ++ MS_U16 noise_level_high_thrd_3 = 0x60; ++ // AUTO NR, HISDNR ++ MS_U16 noise_bin_step = 0x00; ++ MS_U16 noise_bin_thrd = 0x4C; ++ MS_U16 pause_ack = 0; ++ // ++ //MS_U16 hismatch_level0,hismatch_level1,hismatch_level2,hismatch_level3; ++ MS_U16 dnr_std_level0,dnr_std_level1,dnr_std_level2, dnr_std_level3; ++ MS_U16 md_adjust_level0,md_adjust_level1,md_adjust_level2, md_adjust_level3; ++ MS_U16 psnr_std_level0_thrd,psnr_std_level1_thrd,psnr_std_level2_thrd, psnr_std_level3_thrd; ++ MS_U16 dnr_md_high_thrd_level0,dnr_md_low_thrd_level0; ++ MS_U16 dnr_md_high_thrd_level1,dnr_md_low_thrd_level1; ++ MS_U16 dnr_md_high_thrd_level2,dnr_md_low_thrd_level2; ++ MS_U16 dnr_md_high_thrd_level3,dnr_md_low_thrd_level3; ++ // ++ //MS_U16 hismatch_level_thrd=0; ++ MS_U16 dnr_std_level=0; ++ MS_U16 dnr_md_high_thrd_level=0; ++ MS_U16 dnr_md_low_thrd_level=0; ++ MS_U16 md_adjust_level=0; ++ MS_U16 psnr_std_level_thrd=0; ++ // MS_U16 PSNR_his_bs_bit; ++ MS_U16 md_pre_shift=0; ++ MS_U16 md_pre_gain=0; ++ ++ MS_U16 u16Height_div; ++ MS_U16 V_start_height; ++ MS_U16 V_end_height; ++ MS_U16 V_active_height; ++ MS_U16 H_start_width,H_end_width; ++ ++ MS_U16 H_active_width; ++ MS_U32 pixel_number; // directly take ++ MS_U16 LargerThanHigh; ++ MS_U16 Off_from_low; ++ //MS_U16 cond_diagonal; ++ MS_U16 adjust_alpha; ++ MS_U32 weighted_sum; ++ MS_U32 weighted_sumother=0; ++ MS_U32 luma_sum; ++ MS_S32 luma_avg_pre; // 16bits ++ MS_S32 luma_avg; ++ MS_S32 luma_avg_diff; ++ MS_U32 iir_strength; ++ MS_U16 histogram_max = 0; ++ MS_U16 histogram_maxdiff=0; ++ MS_U16 BitsValue_4; ++ MS_U16 max_bin = 0; ++ MS_U16 max_value = 0; ++ MS_U16 result; ++ MS_U32 adjust_result; ++ MS_U16 calculated_result; ++ MS_U16 noise_level_int=0; ++ MS_U16 noise_strength; ++ MS_S16 md_adjust_level_offset=md_adjust_level; ++ ++ XC_ApiStatus stXCStatus; ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ if(stXCStatus.bInterlace) ++ u16Height_div = u16Height / 2 ; ++ else ++ u16Height_div = u16Height ; ++ ++ ++ scaled_ratio = (MS_U32)(4.0 * (u16Width*u16Height_div/172800)); // 720*240 = 172800 ++ ++ if(scaled_ratio<4) ++ scaled_ratio =4; ++ ++ if(u16Width<=1000) ++ V_start_height = u16Height_div/240; ++ else ++ V_start_height = 0x10; ++ ++ V_end_height = (u16Height_div - V_start_height*8)/8; ++ V_active_height = (V_end_height-V_start_height)*8; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_32_L, V_start_height, 0x00FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_32_L, V_end_height<<8, 0xFF00); ++ ++ H_start_width = 0; ++ H_end_width = u16Width/8; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_31_L, H_start_width, 0x00FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_31_L, H_end_width<<8, 0xFF00); ++ ++ H_active_width = (H_end_width-H_start_width)*8; ++ pixel_number =(H_active_width*V_active_height) ; // directly take ++ ++ //------------------------------------------------------- ++ while ( !histogram_ack_en ) ++ histogram_ack_en = (MApi_XC_R2BYTEMSK(REG_SC_BK0E_01_L, BIT(2))?TRUE:FALSE); ++ ++ if (histogram_ack_en) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_01_L, 1, BIT(2)); ++ ++ noise_histogram[0] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_10_L, 0xFFFF); ++ noise_histogram[1] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_11_L, 0xFFFF); ++ noise_histogram[2] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_12_L, 0xFFFF); ++ noise_histogram[3] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_13_L, 0xFFFF); ++ noise_histogram[4] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_14_L, 0xFFFF); ++ noise_histogram[5] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_15_L, 0xFFFF); ++ noise_histogram[6] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_16_L, 0xFFFF); ++ noise_histogram[7] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_17_L, 0xFFFF); ++ noise_histogram[8] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_18_L, 0xFFFF); ++ noise_histogram[9] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_19_L, 0xFFFF); ++ noise_histogram[10] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1A_L, 0xFFFF); ++ noise_histogram[11] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1B_L, 0xFFFF); ++ noise_histogram[12] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1C_L, 0xFFFF); ++ noise_histogram[13] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1D_L, 0xFFFF); ++ noise_histogram[14] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1E_L, 0xFFFF); ++ noise_histogram[15] = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_1F_L, 0xFFFF); ++ ++ for(bin=0; bin<16; bin++) ++ noise_histogram_scaled[bin] = (MS_U16)((MS_S32)noise_histogram[bin]/scaled_ratio); ++ ++ weighted_sum = noise_histogram_scaled[0]*64*scaled_ratio; // 6bits ++ ++ for(bin=5; bin<16; bin++) ++ weighted_sumother += noise_histogram_scaled[bin]; ++ // read luma sum ++ luma_sum = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_48_L, 0xFFFF); ++ ++ // get image size 480i,1080i ++ ++ //------- ++ luma_avg_pre = (luma_sum_pre*16384)/pixel_number; // 16bits ++ luma_avg = (luma_sum*16384)/pixel_number; ++ luma_avg_diff = (MS_U16) abs(luma_avg_pre-luma_avg); ++ ++ luma_sum_pre = luma_sum; ++ ++ iir_strength=2; ++ ++ // remove pause_ack ++ if(luma_avg_diff>=20) ++ iir_strength=8; ++ ++ // alpha before moodify ++ if( (weighted_sum >= (3*pixel_number/4)) && (weighted_sumother!=0)) ++ { ++ pause_ack = 2; ++ } ++ ++ //if(pause_ack==0) ++ { ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_20_L, noise_histogram_scaled[0], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_21_L, noise_histogram_scaled[1], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_22_L, noise_histogram_scaled[2], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_23_L, noise_histogram_scaled[3], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_24_L, noise_histogram_scaled[4], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_25_L, noise_histogram_scaled[5], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_26_L, noise_histogram_scaled[6], 0x03FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_27_L, noise_histogram_scaled[7], 0x03FF); ++ } ++ ++ //hismatch_level0 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_07_L, 0x00FF); ++ //hismatch_level1 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_08_L, 0x00FF); ++ //hismatch_level2 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_09_L, 0x00FF); ++ //hismatch_level3 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_49_L, 0xFF00)>>8); ++ ++ dnr_std_level0 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_07_L, 0xFF00)>>8); ++ dnr_std_level1 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_08_L, 0xFF00)>>8); ++ dnr_std_level2 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_09_L, 0xFF00)>>8); ++ dnr_std_level3 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_4B_L, 0x00FF); ++ ++ dnr_md_high_thrd_level0 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_03_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level0 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_03_L, 0x00FF); ++ dnr_md_high_thrd_level1 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_04_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level1 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_04_L, 0x00FF); ++ dnr_md_high_thrd_level2 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_05_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level2 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_05_L, 0x00FF); ++ dnr_md_high_thrd_level3 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_4A_L, 0xFF00)>>8); ++ dnr_md_low_thrd_level3 = (MS_U16)MApi_XC_R2BYTEMSK(REG_SC_BK0E_4A_L, 0x00FF); ++ ++ md_adjust_level0 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_06_L, 0x000F)>>0); ++ md_adjust_level1 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_06_L, 0x00F0)>>4); ++ md_adjust_level2 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_06_L, 0x0F00)>>8); ++ md_adjust_level3 = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_49_L, 0x000F)>>0); ++ ++ psnr_std_level0_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2A_L, 0x00FF)>>0); ++ psnr_std_level1_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2B_L, 0xFF00)>>8); ++ psnr_std_level2_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2C_L, 0x00FF)>>0); ++ psnr_std_level3_thrd = (MS_U16)(MApi_XC_R2BYTEMSK(REG_SC_BK0E_2D_L, 0x00FF)>>0); ++ ++ for (bin =0; bin<8;bin++) ++ { ++ if(histogram_max<=noise_histogram_scaled[bin]) ++ histogram_max=noise_histogram_scaled[bin] ; ++ } ++ ++ for (bin =0; bin<8;bin++) ++ histogram_maxdiff +=abs(histogram_max-noise_histogram_scaled[bin]) ; ++ ++ if( histogram_maxdiff > noise_bin_thrd ) ++ { ++ //cond_diagonal = 1; ++ adjust_alpha = 0xF; ++ } ++ else ++ { ++ Off_from_low = noise_bin_thrd - histogram_maxdiff; ++ //cond_diagonal = 0; ++ switch( noise_bin_step ) ++ { ++ case 0: BitsValue_4 = Off_from_low &0xF; ++ LargerThanHigh = ( ( Off_from_low >> 4) >0 ) ? 1 : 0; ++ break; ++ case 1: BitsValue_4 = (Off_from_low>>1 )&0xF; ++ LargerThanHigh = ( ( Off_from_low >>5) >0 ) ? 1 : 0; ++ break; ++ case 2: BitsValue_4 = ( Off_from_low >>2)&0xF; ++ LargerThanHigh = ( ( Off_from_low >>6) >0 ) ? 1 : 0; ++ break; ++ case 3: BitsValue_4 = ( Off_from_low>>3 )&0xF; ++ LargerThanHigh = ( ( Off_from_low >>7) >0 ) ? 1 : 0; ++ break; ++ ++ default: ++ break; ++ } // end switch ++ ++ if( LargerThanHigh == 1) ++ adjust_alpha = 0; ++ else ++ adjust_alpha = ~BitsValue_4; ++ adjust_alpha = adjust_alpha &0x0F; ++ ++ } // end of diag switch ++ ++ //MS_U16 max_result = 0; ++ ++ for(bin=0; bin<5;bin++) ++ { ++ if(noise_histogram_scaled[bin]+noise_histogram_scaled[bin+1]>=max_value) ++ max_value = noise_histogram_scaled[bin]+noise_histogram_scaled[bin+1]; ++ } ++ ++ for (bin=0; bin<5;bin++) ++ { ++ if( (noise_histogram_scaled[bin]+noise_histogram_scaled[bin+1])==max_value) ++ max_bin = bin; ++ } ++ ++ if ( 0 == max_bin ) //34 is ok , wh ++ result = 16; ++ else if ( 1 == max_bin) ++ result = 32; ++ else if ( 2 == max_bin) ++ result = 48; ++ else if(3 == max_bin) ++ result =64; ++ else if( (4 == max_bin) || (5 == max_bin) ) ++ result = 80; // 70 @@@@@@@@@ ++ else ++ result= 16; ++ ++ adjust_result = (MS_U32)((result * adjust_alpha+8)/16.0); ++ calculated_result = (MS_U16)(adjust_result); ++ ++ if ( (noise_level_low_thrd_0 <= calculated_result) && (calculated_result < noise_level_low_thrd_1)) //34 is ok , wh ++ { ++ noise_level_int = 0; ++ } ++ else if ( (noise_level_low_thrd_1 <= calculated_result) && (calculated_result< noise_level_low_thrd_2)) ++ { ++ noise_level_int = 1; ++ } ++ else if ( (noise_level_low_thrd_2 <= calculated_result) && (calculated_result< noise_level_low_thrd_3)) ++ { ++ noise_level_int = 2; ++ } ++ else if((noise_level_low_thrd_3 <= calculated_result) && (calculated_result < noise_level_high_thrd_3)) ++ { ++ noise_level_int =3; ++ } ++ ++ noise_strength = MApi_XC_R2BYTEMSK(REG_SC_BK0E_4B_L, 0xFF00)>>8; ++ ++ if(noise_level_int==0) ++ { ++ //hismatch_level_thrd = hismatch_level0; ++ dnr_std_level = dnr_std_level0; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level0; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level0; ++ md_adjust_level = md_adjust_level0; ++ psnr_std_level_thrd = psnr_std_level0_thrd; ++ md_pre_shift = 5; ++ md_pre_gain = 6; ++ } ++ else if(noise_level_int==1) ++ { ++ //hismatch_level_thrd = hismatch_level1; ++ dnr_std_level = dnr_std_level1; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level1; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level1; ++ md_adjust_level = md_adjust_level1; ++ psnr_std_level_thrd = psnr_std_level1_thrd; ++ md_pre_shift = 2; ++ md_pre_gain = 1; ++ } ++ else if(noise_level_int==2) ++ { ++ //hismatch_level_thrd = hismatch_level2; ++ dnr_std_level = dnr_std_level2; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level2; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level2; ++ md_adjust_level = md_adjust_level2; ++ psnr_std_level_thrd = psnr_std_level2_thrd; ++ md_pre_shift = 2; ++ md_pre_gain = 1; ++ ++ } ++ else if(noise_level_int==3 ) ++ { ++ //hismatch_level_thrd = hismatch_level3 ; ++ dnr_std_level = dnr_std_level3; ++ dnr_md_high_thrd_level = dnr_md_high_thrd_level3; ++ dnr_md_low_thrd_level = dnr_md_low_thrd_level3; ++ md_adjust_level = md_adjust_level3; ++ psnr_std_level_thrd = psnr_std_level3_thrd; ++ md_pre_shift = 2; ++ md_pre_gain = 1; ++ ++ } ++ ++ md_adjust_level_offset = md_adjust_level; ++ ++ if(noise_strength==0) ++ md_adjust_level_offset = (md_adjust_level-2); ++ else if(noise_strength==1) ++ md_adjust_level_offset = (md_adjust_level-1); ++ else if(noise_strength==3) ++ md_adjust_level_offset = (md_adjust_level+1); ++ else if(noise_strength==4) ++ md_adjust_level_offset = (md_adjust_level+2); ++ ++ if(md_adjust_level_offset<0) ++ md_adjust_level_offset = 0; ++ else if(md_adjust_level_offset>0xF) ++ md_adjust_level_offset = 0xF; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_30_L, md_pre_gain, 0x003F); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_30_L, (md_pre_shift<<8), 0x0700); ++ ++ //if(pause_ack == 0) ++ //{ ++ // hismatch_level_thrd_iir= (iir_strength*hismatch_level_thrd + (8-iir_strength)*hismatch_level_thrd_iir)/8 ; ++ // rounding_bit = (iir_strength*hismatch_level_thrd + (8-iir_strength)*hismatch_level_thrd_iir)&0x04; ++ //} ++ //MApi_XC_W2BYTEMSK(REG_SC_BK0E_0C_L, (MS_U16)(hismatch_level_thrd_iir+rounding_bit/4) , 0x00FF); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0C_L, 0 , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ dnr_std_thrd_iir = (iir_strength*dnr_std_level *4+ (8-iir_strength)*dnr_std_thrd_iir)/8 ; // *4/8(iir) = /2 ==> X.2 format ++ //rounding_bit = (iir_strength*dnr_std_level + (8-iir_strength)*dnr_std_thrd_iir)&0x04; ++ } ++ if(pause_ack == 2) ++ dnr_std_thrd_iir= 5*4 ; ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0D_L, (MS_U16)( dnr_std_thrd_iir/4 + (dnr_std_thrd_iir&0x02)/2 ) , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ //dnr_md_high_thrd_level_iir= (iir_strength*dnr_md_high_thrd_level + (8-iir_strength)*dnr_md_high_thrd_level_iir)/2.0 ; // *4/8(iir) = /2 ==> X.2 format ++ dnr_md_high_thrd_level_iir= (MS_U16)((iir_strength*dnr_md_high_thrd_level *4+ (8-iir_strength)*dnr_md_high_thrd_level_iir)/8) ; // *4/8(iir) = /2 ==> X.2 format ++ //rounding_bit = (iir_strength*dnr_md_high_thrd_level + (8-iir_strength)*dnr_md_high_thrd_level_iir)&0x04; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0B_L, (MS_U16)(dnr_md_high_thrd_level_iir/4 + (dnr_md_high_thrd_level_iir&0x02)/2) , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ dnr_md_low_thrd_level_iir= (MS_U16)((iir_strength*dnr_md_low_thrd_level*4+ (8-iir_strength)*dnr_md_low_thrd_level_iir)/8) ; // *4/8(iir) = /2 ==> X.2 format ++ //rounding_bit = (iir_strength*dnr_md_low_thrd_level + (8-iir_strength)*dnr_md_low_thrd_level_iir)&0x04; ++ } ++ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_0A_L, (MS_U16)(dnr_md_low_thrd_level_iir/4 + (dnr_md_low_thrd_level_iir&0x02)/2 ) , 0x00FF); ++ ++ //if(pause_ack == 0) ++ { ++ md_adjust_level_iir= (iir_strength*md_adjust_level_offset*4 +(8-iir_strength)*md_adjust_level_iir)/8 ; ++ //rounding_bit = (iir_strength*md_adjust_level +(8-iir_strength)*md_adjust_level_iir)&0x04; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_06_L, ((MS_U16)(md_adjust_level_iir/4 + (md_adjust_level_iir&0x02)/2) )<<0xC , 0xF000); ++ ++ //if(pause_ack == 0) ++ { ++ psnr_std_level_thrd_iir= (iir_strength*psnr_std_level_thrd*4 + (8-iir_strength)*psnr_std_level_thrd_iir)/8 ; ++ //rounding_bit = (iir_strength*psnr_std_level_thrd + (8-iir_strength)*psnr_std_level_thrd_iir)&0x04; ++ } ++ MApi_XC_W2BYTEMSK(REG_SC_BK0E_2D_L, ((MS_U16)( psnr_std_level_thrd_iir/4 + (psnr_std_level_thrd_iir&0x02)/2 ) )<<0x8 , 0xFF00); ++ } ++ ++} ++ ++ ++static MS_U16 g_u16BK0A_24 = 0; ++static MS_U16 g_u16BK0C_10 = 0; ++static MS_U16 g_u16BK0C_39 = 0; ++static MS_U16 g_u16BK0C_3A = 0; ++static MS_U16 g_u16BK0C_40 = 0; ++static MS_U16 g_u16BK0C_41 = 0; ++static MS_U16 g_u16BK0C_42 = 0; ++static MS_U16 g_u16BK26_10 = 0; ++static MS_U16 g_u16BK26_11 = 0; ++static MS_U16 g_u16BK26_12 = 0; ++static MS_U16 g_u16BK26_13 = 0; ++static MS_U16 g_u16BK26_18 = 0; ++ ++/******************************************************************************/ ++///Film mode control for Any Candence ++///@param bEnable \ IN: Enable/Disable control ++/******************************************************************************/ ++void MApi_XC_FilmMode_AnyCandence_Enable(MS_BOOL bEnable) ++{ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, (bEnable ? (BIT(15)) : 0), BIT(15)); ++ g_bAnyCandenceEnable = bEnable; ++} ++ ++/******************************************************************************/ ++///De-Blocking Control ++///@param bEnable \ IN: Enable/Disable control ++/******************************************************************************/ ++void MApi_XC_DBK_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel) ++{ ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, bEnable, BIT(0)); ++ if(bEnable) ++ { ++ switch(eLevel) ++ { ++ default: ++ case Level_Low: ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, (0x1F) << 8, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, 0x0709); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_3A_L, 0x06, 0x00FF); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, 0x0563); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, 0x0442); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, 0x0412); ++ break; ++ case Level_MID: ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, (0x40) << 8, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, 0x0709); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_3A_L, 0x05, 0x00FF); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, 0x0767); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, 0x0742); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, 0x0912); ++ break; ++ case Level_High: ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_10_L, (0x80) << 8, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, 0x0709); ++ MApi_XC_W2BYTEMSK(REG_SC_BK0C_3A_L, 0x05, 0x00FF); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, 0x0767); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, 0x0742); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, 0x0902); ++ break; ++ } ++ } ++} ++ ++ ++/******************************************************************************/ ++///De-Mosquito Control ++///@param bEnable \ IN: Enable/Disable control ++/******************************************************************************/ ++void MApi_XC_DMS_Control(MS_BOOL bEnable, XC_CTRL_LEVEL eLevel) ++{ ++ MApi_XC_W2BYTEMSK(REG_SC_BK26_10_L, bEnable, BIT(0)); ++ if(bEnable) ++ { ++ switch(eLevel) ++ { ++ default: ++ case Level_Low: ++ MApi_XC_W2BYTEMSK(REG_SC_BK26_10_L, 0x1000, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK26_11_L, 0x0110); ++ MApi_XC_W2BYTE(REG_SC_BK26_12_L, 0x0000); ++ MApi_XC_W2BYTE(REG_SC_BK26_13_L, 0x0006); ++ MApi_XC_W2BYTE(REG_SC_BK26_18_L, 0x0020); ++ break; ++ case Level_MID: ++ break; ++ case Level_High: ++ MApi_XC_W2BYTEMSK(REG_SC_BK26_10_L, 0x1500, 0xFF00); ++ MApi_XC_W2BYTE(REG_SC_BK26_11_L, 0x0110); ++ MApi_XC_W2BYTE(REG_SC_BK26_12_L, 0x0000); ++ MApi_XC_W2BYTE(REG_SC_BK26_13_L, 0x0110); ++ MApi_XC_W2BYTE(REG_SC_BK26_18_L, 0x0000); ++ break; ++ } ++ } ++ ++} ++ ++/******************************************************************************/ ++///Store the Current value ++/******************************************************************************/ ++void MApi_XC_SotreCurrentValue(void) ++{ ++ //for AnyCandence Film Mode ++ g_u16BK0A_24 = MApi_XC_R2BYTEMSK(REG_SC_BK0A_24_L, BIT(15)); ++ ++ //for DBK ++ g_u16BK0C_10 = MApi_XC_R2BYTE(REG_SC_BK0C_10_L); ++ g_u16BK0C_39 = MApi_XC_R2BYTE(REG_SC_BK0C_39_L); ++ g_u16BK0C_3A = MApi_XC_R2BYTE(REG_SC_BK0C_3A_L); ++ g_u16BK0C_40 = MApi_XC_R2BYTE(REG_SC_BK0C_40_L); ++ g_u16BK0C_41 = MApi_XC_R2BYTE(REG_SC_BK0C_41_L); ++ g_u16BK0C_42 = MApi_XC_R2BYTE(REG_SC_BK0C_42_L); ++ ++ //for DMS ++ g_u16BK26_10 = MApi_XC_R2BYTE(REG_SC_BK26_10_L); ++ g_u16BK26_11 = MApi_XC_R2BYTE(REG_SC_BK26_11_L); ++ g_u16BK26_12 = MApi_XC_R2BYTE(REG_SC_BK26_12_L); ++ g_u16BK26_13 = MApi_XC_R2BYTE(REG_SC_BK26_13_L); ++ g_u16BK26_18 = MApi_XC_R2BYTE(REG_SC_BK26_18_L); ++} ++ ++/******************************************************************************/ ++///Store the Current value ++/******************************************************************************/ ++void MApi_XC_ReSotreToDefault(void) ++{ ++ //for AnyCandence Film Mode ++ MApi_XC_W2BYTEMSK(REG_SC_BK0A_24_L, g_u16BK0A_24, BIT(15)); ++ ++ //for DBK ++ MApi_XC_W2BYTE(REG_SC_BK0C_10_L, g_u16BK0C_10); ++ MApi_XC_W2BYTE(REG_SC_BK0C_39_L, g_u16BK0C_39); ++ MApi_XC_W2BYTE(REG_SC_BK0C_3A_L, g_u16BK0C_3A); ++ MApi_XC_W2BYTE(REG_SC_BK0C_40_L, g_u16BK0C_40); ++ MApi_XC_W2BYTE(REG_SC_BK0C_41_L, g_u16BK0C_41); ++ MApi_XC_W2BYTE(REG_SC_BK0C_42_L, g_u16BK0C_42); ++ ++ //for DMS ++ MApi_XC_W2BYTE(REG_SC_BK26_10_L, g_u16BK26_10); ++ MApi_XC_W2BYTE(REG_SC_BK26_11_L, g_u16BK26_11); ++ MApi_XC_W2BYTE(REG_SC_BK26_12_L, g_u16BK26_12); ++ MApi_XC_W2BYTE(REG_SC_BK26_13_L, g_u16BK26_13); ++ MApi_XC_W2BYTE(REG_SC_BK26_18_L, g_u16BK26_18); ++} ++ ++#define ENABLE_SCALER_DEFEATHERING 0x01 //BK22_7C_L ++#define ENABLE_SCALER_DEFLICKERING 0x02 ++#define ENABLE_SCALER_DEBOUNCING 0x04 ++#define ENABLE_SCALER_DYNAMIC_SNR 0x08 ++#define ENABLE_SCALER_DYNAMIC_DNR 0x10 ++#define ENABLE_SCALER_DYNAMIC_FILM22 0x20 ++#define ENABLE_SCALER_DEPRESNR 0x40 ++#define ENABLE_SCALER_FANTASTICDNR 0x80 ++#define ENABLE_SCALER_MCDI_DRIVER 0x01 //BK22_7C_H ++#define ENABLE_SCALER_MCNR_DRIVER 0x02 ++#define ENABLE_SCALER_FILM_DRIVER 0x04 ++#define ENABLE_SCALER_JANUS_DHD_DRIVER 0x08 ++#define ENABLE_SCALER_HISDNR_DRIVER 0x10 ++#define ENABLE_SCALER_SDHD_DETECT_DRIVER 0x20 ++#define ENABLE_SCALER_T12_UCDI_DRIVER 0x40 ++#define ENABLE_SCALER_NEW_SDHD_DETECT_DRIVER 0x80 ++#define ENABLE_SCALER_EXTEND_UCDI_DRIVER 0x01 //BK22_7E_L ++#define ENABLE_SCALER_NEW_FILM_DRIVER 0x02 ++#define ENABLE_SCALER_EXTEND_UCNR_DRIVER 0x04 ++#define ENABLE_SCALER_AUTO_DBK_DRIVER 0x80 // BK30_01_L[15] ++ ++//------------------------------------------------------------------------------------------------- ++/// this function does adaptive tuning periodic ++//------------------------------------------------------------------------------------------------- ++void MApi_XC_AdaptiveTuning(void) ++{ ++ static MS_U8 u8PreviousVcnt = 0; ++ MS_U8 u8CurrentVcnt; ++ MS_U8 u8Ctrl,ColorSum; ++ MS_U8 u8Ctrl2; ++ MS_U8 u8Ctrl3; ++ MS_U8 u8Ctrl4; ++ MS_U32 u32MotionValue,u32MotionValue2,OOSRMC,OOSRF,ISR_NONMV0,SmallMoving,VerticalMoving,HorizontalMoving,TotalFeather,TotalMvComfirm; ++ MS_U32 uComplex; ++ MS_U8 u8MotLvl,u8SDHDDReportValue; ++ XC_ApiStatus stXCStatus; ++ MS_BOOL lg107_en; ++ MsOS_Memset(&stXCStatus, 0x00, sizeof(stXCStatus)); ++ ++ // ++ // Check VCnt ++ // ++ u8CurrentVcnt = MDrv_SC_read_v_cnt(); ++ if (u8PreviousVcnt == u8CurrentVcnt) ++ { ++ return; ++ } ++ else ++ { ++ u8PreviousVcnt = u8CurrentVcnt; ++ } ++ ++ // ++ // Get adaptive function control ++ // ++ u8Ctrl = MDrv_SC_get_adaptive_ctrl(); ++ u8Ctrl2 = MDrv_SC_get_adaptive_ctrl2(); ++ u8Ctrl3 = MDrv_SC_get_adaptive_ctrl3(); ++ u8Ctrl4 = MDrv_SC_get_adaptive_ctrl4(); ++ // ++ // Get motion value ++ // ++ u32MotionValue = MDrv_SC_read_motion_value1(); ++ u32MotionValue2 = MDrv_SC_read_motion_value2(); ++ ++ // ++ // Get UCDi status ++ // ++ OOSRMC = MDrv_SC_T12_UC_InSearchRange_MvComfirm(); ++ OOSRF = MDrv_SC_T12_UC_InSearchRange_Feather(); ++ ISR_NONMV0 = MDrv_SC_T12_UC_InSearchRange_nonMv0Comfirm(); ++ SmallMoving = MDrv_SC_T12_UC_SmallMoving(); ++ VerticalMoving = MDrv_SC_A5_KFC_IsVerticalMoving(); ++ ++ HorizontalMoving = MDrv_SC_A5_IsHorizontalMoving(); ++ TotalFeather = MDrv_SC_A5_TotalFeather(); ++ TotalMvComfirm = MDrv_SC_A5_TotalMvComfirm(); ++ ColorSum = (MS_U8)MDrv_SC_A5_ColorPixelSum(); ++ uComplex = MDrv_SC_A5_ComplexSum(); ++ ++ //printf("===VerticalMoving==%x=\n",VerticalMoving); ++ //printf("===HorizontalMoving==%x=\n",HorizontalMoving); ++ //printf("===u32MotionValue==%x=\n",u32MotionValue); ++ //printf("===OOSRF==%x=\n",OOSRF); ++ //printf("===ISR_NONMV0==%x=\n",ISR_NONMV0); ++ // ++ // Adaptive functions ++ // ++ ++ if(_u16PQPre_SrcType != _u16PQSrcType_DBK_Detect[PQ_MAIN_WINDOW]) //For Auto_DBK SW driver used ++ { ++ _u16PQPre_SrcType = _u16PQSrcType_DBK_Detect[PQ_MAIN_WINDOW]; ++ data_read = true; ++ } ++ ++ ++ if (u8Ctrl3 & ENABLE_SCALER_AUTO_DBK_DRIVER) //New Add for AUTO DBK Test ++ { ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ u8SDHDDReportValue = MDrv_SC_NEW_SDHD_DETECT_report(); // W/O Feather detect ++ MDrv_SC_Auto_Detect_Blocking_Width_driver(u8SDHDDReportValue); // Auto_Detect_Blocking_Width ++ } ++ ++ if(u8Ctrl4 & ENABLE_SCALER_EXTEND_UCDI_DRIVER) ++ { ++ ++ } ++ else ++ { ++ // ++ // T12 UCDi function ++ // ++ if (u8Ctrl2 & ENABLE_SCALER_T12_UCDI_DRIVER) ++ { ++ //u8MotLvl = MDrv_SC_motion_level(u32MotionValue); ++ //MDrv_SC_T12_UCDi_OP1_HisWeight(u8MotLvl); ++ MDrv_SC_T12_UCDi_FeatherValueGain(OOSRMC, OOSRF, ISR_NONMV0); ++ //MDrv_SC_T12_DIPF_TemporalGainControl(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_VerticalMovingUdRatio(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_ComplexOffset(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_W2SadGain(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_KFC_8bitMotionGain(SmallMoving); ++ MDrv_SC_T12_UCDi_EODiWGain(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_T12_UCDi_HistoryRatio(OOSRMC, OOSRF, ISR_NONMV0); ++ MDrv_SC_A5_UCDi_OP1_HisWeight(u32MotionValue2); ++ MDrv_SC_A5_KFC_EODiW(VerticalMoving); ++ lg107_en = MDrv_SC_A5_LG107(VerticalMoving, HorizontalMoving, TotalFeather, TotalMvComfirm,ColorSum,u32MotionValue, uComplex); ++ MDrv_SC_A5_SonyChurch(VerticalMoving, HorizontalMoving, u32MotionValue, lg107_en ); ++ } ++ else ++ { ++ if (u8Ctrl2 & ENABLE_SCALER_MCDI_DRIVER) ++ { ++ MDrv_SC_mcdi_driver(u32MotionValue2); ++ } ++ else ++ { ++ u8MotLvl = MDrv_SC_motion_level(u32MotionValue); ++ MDrv_SC_mcdi_driver_new(u32MotionValue2, u8MotLvl); ++ } ++ ++ } ++ } ++ ++ if(u8Ctrl4 & ENABLE_SCALER_EXTEND_UCNR_DRIVER) ++ { ++ MDrv_SC_Extend_UCNR_driver(); ++ } ++ else ++ { ++ if (u8Ctrl2 & ENABLE_SCALER_MCNR_DRIVER) ++ { ++ MDrv_SC_mcnr_driver(); ++ } ++ } ++ if (u8Ctrl2 & ENABLE_SCALER_SDHD_DETECT_DRIVER) ++ { ++ MDrv_SC_SDHD_DETECT_driver(); ++ } ++ ++ if (u8Ctrl2 & ENABLE_SCALER_NEW_SDHD_DETECT_DRIVER) ++ { ++ MDrv_SC_NEW_SDHD_DETECT_driver(); ++ } ++ ++ if(u8Ctrl4 & ENABLE_SCALER_NEW_FILM_DRIVER) ++ { ++ ++ } ++ else ++ { ++ if (u8Ctrl2 & ENABLE_SCALER_FILM_DRIVER) ++ { ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ MDrv_SC_film_driver(stXCStatus.u16H_SizeAfterPreScaling); ++ } ++ else ++ { ++ MDrv_SC_dynamic_film_mode(); // for T2 and before ++ } ++ } ++ ++ if (u8Ctrl2 & ENABLE_SCALER_JANUS_DHD_DRIVER) ++ { ++ MDrv_SC_Janus_DHD_driver(); ++ } ++ ++ if (u8Ctrl2 & ENABLE_SCALER_HISDNR_DRIVER) ++ { ++ if(MApi_XC_GetStatus(&stXCStatus, MAIN_WINDOW) == FALSE) ++ { ++ printf("MApi_XC_GetStatus failed because of InitData wrong, please update header file and compile again\n"); ++ } ++ ++ MDrv_SC_HISNR_driver(stXCStatus.stCropWin.width, stXCStatus.stCropWin.height); ++ } ++// else ++// { ++//dnr_md_high_thrd_level_iir=0; ++//dnr_md_low_thrd_level_iir=0; ++// } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEFEATHERING) ++ { ++ MDrv_SC_de_feathering(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEFLICKERING) ++ { ++ MDrv_SC_de_flickering(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEBOUNCING) ++ { ++ MDrv_SC_de_bouncing(u32MotionValue2); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DYNAMIC_SNR) ++ { ++ MDrv_SC_dynamic_snr(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DYNAMIC_DNR) ++ { ++ MDrv_SC_dynamic_dnr(u32MotionValue); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_DEPRESNR) ++ { ++ MDrv_SC_de_pre_snr(u32MotionValue2); ++ } ++ ++ if (u8Ctrl & ENABLE_SCALER_FANTASTICDNR) ++ { ++ MDrv_SC_fantastic_dnr(); ++ } ++} ++ ++#endif //#ifdef UTOPIA ++ ++#undef DRV_SCALER_ADAPTIVE_C +diff --git a/drivers/mstar/scl/scl b/drivers/mstar/scl/scl +new file mode 100644 +index 00000000..d8bac352 +Binary files /dev/null and b/drivers/mstar/scl/scl differ +diff --git a/drivers/mstar/sdmmc/Kconfig b/drivers/mstar/sdmmc/Kconfig +new file mode 100644 +index 00000000..60ec4e54 +--- /dev/null ++++ b/drivers/mstar/sdmmc/Kconfig +@@ -0,0 +1,199 @@ ++config MS_SDMMC ++ tristate "Mstar SD/MMC Card Interface Support" ++ depends on MMC ++ default n ++ ---help--- ++ Enable SD/MMC Driver Support for MStar Product ++ ++config MS_SDMMC_SLOTNUMS ++ int "Mstar SD/MMC Total Slot Number" ++ depends on MS_SDMMC ++ default 1 ++ range 1 3 ++ ---help--- ++ How many SDMMC Slots ++ ++config MS_SDMMC1_IP ++ int "Mstar IP Select Order of SD/MMC1" ++ depends on MS_SDMMC ++ default 0 ++ range 0 2 ++ ---help--- ++ The IP Select Order of SDMMC1 ++ ++config MS_SDMMC2_IP ++ int "Mstar IP Select Order of SD/MMC2" ++ depends on MS_SDMMC ++ default 1 ++ range 0 2 ++ ---help--- ++ The IP Select Order of SDMMC2 ++ ++ config MS_SDMMC3_IP ++ int "Mstar IP Select Order of SD/MMC3" ++ depends on MS_SDMMC ++ default 2 ++ range 0 2 ++ ---help--- ++ The IP Select Order of SDMMC3 ++ ++config MS_SDMMC1_PAD ++ int "Mstar PAD Select Order of SD/MMC1" ++ depends on MS_SDMMC ++ default 0 ++ range 0 2 ++ ---help--- ++ The PAD Select Order of SDMMC1 ++ ++config MS_SDMMC2_PAD ++ int "Mstar PAD Select Order of SD/MMC2" ++ depends on MS_SDMMC ++ default 1 ++ range 0 2 ++ ---help--- ++ The PAD Select Order of SDMMC2 ++ ++config MS_SDMMC3_PAD ++ int "Mstar PAD Select Order of SD/MMC3" ++ depends on MS_SDMMC ++ default 2 ++ range 0 2 ++ ---help--- ++ The PAD Select Order of SDMMC1 ++ ++ ++config MS_SDMMC_REVCDZ ++ bool "Mstar SD/MMC Reverse CDZ Pin" ++ depends on MS_SDMMC ++ default n ++ ---help--- ++ For SD Socket Type, Revert the CDZ pin Value for Card Detection ++ ++config MS_SDMMC_TCARD ++ bool "Mstar SD/MMC T-Flash Card Using" ++ depends on MS_SDMMC ++ default n ++ ---help--- ++ For T-Flash Socket, We don't use WP Pin ++ ++config MS_SDMMC_REVWP ++ bool "Mstar SD/MMC Reverse WP Pin" ++ depends on !MS_SDMMC_TCARD && MS_SDMMC ++ default n ++ ---help--- ++ For SD Socket Type, Revert the WP pin Value for Write Protection ++ ++config MS_SDMMC1_MAXCLK ++ int "Mstar SD/MMC1 Maximum Clock" ++ depends on MS_SDMMC ++ default 32000000 ++ range 300000 50000000 ++ ---help--- ++ The maximun Clock of SDMMC1 ++ ++config MS_SDMMC1_MAXDLVL ++ int "Mstar SD/MMC1 Maximum DownLevel" ++ depends on MS_SDMMC ++ default 0 ++ range 0 5 ++ ---help--- ++ The maximun Clock Downgrade Level of SDMMC1 ++ ++config MS_SDMMC1_PASSLVL ++ int "Mstar SD/MMC1 Pass Level" ++ depends on MS_SDMMC ++ default 0 ++ range 0 5 ++ ---help--- ++ The maximun Clock Pass Level of SDMMC1 ++ ++config MS_SDMMC1_INTCDZ ++ bool "Mstar SD/MMC1 Int CDZ Support" ++ depends on MS_SDMMC ++ default n ++ ---help--- ++ For SD1, Whether we need to run hotplug funciton (HW consideration) ++ ++config MS_SDMMC1_FAKECDZ ++ bool "Mstar SD/MMC1 Fake CDZ" ++ depends on !MS_SDMMC1_INTCDZ && MS_SDMMC ++ default n ++ ---help--- ++ For SD1, Whether we need to assume card detection always true (HW consideration) ++ ++ ++config MS_SDMMC2_MAXCLK ++ int "Mstar SD/MMC2 Maximum Clock" ++ depends on MS_SDMMC ++ default 32000000 ++ range 300000 50000000 ++ ---help--- ++ The maximun Clock of SDMMC2 ++ ++config MS_SDMMC2_MAXDLVL ++ int "Mstar SD/MMC2 Maximum DownLevel" ++ depends on MS_SDMMC ++ default 0 ++ range 0 5 ++ ---help--- ++ The maximun Clock Downgrade Level of SDMMC2 ++ ++config MS_SDMMC2_PASSLVL ++ int "Mstar SD/MMC2 Pass Level" ++ depends on MS_SDMMC ++ default 0 ++ range 0 5 ++ ---help--- ++ The maximun Clock Pass Level of SDMMC2 ++ ++config MS_SDMMC2_INTCDZ ++ bool "Mstar SD/MMC2 Int CDZ Support" ++ depends on MS_SDMMC ++ default n ++ ---help--- ++ For SD2, Whether we need to run hotplug funciton (HW consideration) ++ ++config MS_SDMMC2_FAKECDZ ++ bool "Mstar SD/MMC2 Fake CDZ" ++ depends on !MS_SDMMC2_INTCDZ && MS_SDMMC ++ default n ++ ---help--- ++ For SD2, Whether we need to assume card detection always true (HW consideration) ++ ++config MS_SDMMC3_MAXCLK ++ int "Mstar SD/MMC3 Maximum Clock" ++ depends on MS_SDMMC ++ default 32000000 ++ range 300000 50000000 ++ ---help--- ++ The maximun Clock of SDMMC3 ++ ++config MS_SDMMC3_MAXDLVL ++ int "Mstar SD/MMC3 Maximum DownLevel" ++ depends on MS_SDMMC ++ default 0 ++ range 0 5 ++ ---help--- ++ The maximun Clock Downgrade Level of SDMMC3 ++ ++config MS_SDMMC3_PASSLVL ++ int "Mstar SD/MMC3 Pass Level" ++ depends on MS_SDMMC ++ default 0 ++ range 0 5 ++ ---help--- ++ The maximun Clock Pass Level of SDMMC3 ++ ++config MS_SDMMC3_INTCDZ ++ bool "Mstar SD/MMC3 Int CDZ Support" ++ depends on MS_SDMMC ++ default n ++ ---help--- ++ For SD3, Whether we need to run hotplug funciton (HW consideration) ++ ++config MS_SDMMC3_FAKECDZ ++ bool "Mstar SD/MMC3 Fake CDZ" ++ depends on !MS_SDMMC3_INTCDZ && MS_SDMMC ++ default n ++ ---help--- ++ For SD3, Whether we need to assume card detection always true (HW consideration) +diff --git a/drivers/mstar/sdmmc/Makefile b/drivers/mstar/sdmmc/Makefile +new file mode 100644 +index 00000000..67b2621f +--- /dev/null ++++ b/drivers/mstar/sdmmc/Makefile +@@ -0,0 +1,22 @@ ++obj-$(CONFIG_MS_SDMMC) += kdrv_sdmmc.o ++kdrv_sdmmc-y = src/hal_card_regs.o src/hal_card_timer.o ++ ++ifeq ($(CONFIG_ARCH_CEDRIC),y) ++kdrv_sdmmc-y += src/hal_card_intr.o ++kdrv_sdmmc-y += src/hal_sdmmc.o ++kdrv_sdmmc-y += src/hal_card_platform_c3.o ++else ifeq ($(CONFIG_ARCH_CHICAGO),y) ++kdrv_sdmmc-y += src/hal_card_intr.o ++kdrv_sdmmc-y += src/hal_sdmmc.o ++kdrv_sdmmc-y += src/hal_card_platform_c4.o ++else ifeq ($(CONFIG_ARCH_INFINITY),y) ++kdrv_sdmmc-y += src/hal_card_intr_v5.o ++kdrv_sdmmc-y += src/hal_sdmmc_v5.o ++kdrv_sdmmc-y += src/hal_card_platform_iNF.o ++else ifeq ($(CONFIG_ARCH_INFINITY3),y) ++kdrv_sdmmc-y += src/hal_card_intr_v5.o ++kdrv_sdmmc-y += src/hal_sdmmc_v5.o ++kdrv_sdmmc-y += src/hal_card_platform_iNF3.o ++endif ++ ++kdrv_sdmmc-y += ms_sdmmc_lnx.o +diff --git a/drivers/mstar/sdmmc/inc/hal_card_base.h b/drivers/mstar/sdmmc/inc/hal_card_base.h +new file mode 100644 +index 00000000..e8281c39 +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_base.h +@@ -0,0 +1,300 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_base.h ++ * @author jeremy.wang (2015/05/29) ++ * Desc: ++ * This header file is independent. ++ * We could put different hal_card_base.h in different build code folder but the same name. ++ * We want to distinguish between this and others settings but the same project. ++ * Specific define is freedom for each project, but we need to put it at inner code of project define. ++ * ++ * For Base Setting: ++ * (1) BASE Project/OS/CPU/FCIE/Ver.. Option Type Define ++ * (2) BASE TYPE Define ++ * (3) BASE OS/CPU define and Include Files for Different OS/CPU ++ * (4) BASE Debug System ++ * (5) BASE Project/FCIE/Ver.. Define ++ * ++ * P.S. D_XX for define and D_XX__ two under line("__") to distinguish define and its define option. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_BASE_H ++#define __HAL_CARD_BASE_H ++ ++//*********************************************************************************************************** ++// (1) BASE Project/OS/CPU/FCIE/ICVer.. Option Type Define ++//*********************************************************************************************************** ++ ++// Project Option Type Define ++//----------------------------------------------------------------------------------------------------------- ++#define D_PROJECT__C3 1 //Cedric Project ++#define D_PROJECT__C4 2 //Chicago Project ++#define D_PROJECT__iNF 3 //iNfinity Project ++#define D_PROJECT__iNF3 4 //iNfinity3 Project ++ ++// OS Type Option ++//----------------------------------------------------------------------------------------------------------- ++#define D_OS__LINUX 1 ++#define D_OS__UBOOT 2 ++#define D_OS__WINCE 3 ++#define D_OS__EBOOT 4 ++#define D_OS__YBOX 5 ++#define D_OS__NONE 6 ++ ++// CPU Type Option ++//----------------------------------------------------------------------------------------------------------- ++#define D_CPU__ARM 1 ++#define D_CPU__MIPS 2 ++ ++// FCIE Type Major Version ++//----------------------------------------------------------------------------------------------------------- ++#define D_FCIE_M_VER__04 1 ++#define D_FCIE_M_VER__05 2 ++ ++// FCIE Type Revision Version ++//----------------------------------------------------------------------------------------------------------- ++#define D_FCIE_R_VER__00 0 ++#define D_FCIE_R_VER__01 1 ++#define D_FCIE_R_VER__02 2 ++#define D_FCIE_R_VER__03 3 ++#define D_FCIE_R_VER__04 4 ++#define D_FCIE_R_VER__05 5 ++ ++// BOARD Type Version ++//----------------------------------------------------------------------------------------------------------- ++#define D_BOARD_VER__00 0 ++#define D_BOARD_VER__01 1 ++#define D_BOARD_VER__02 2 ++#define D_BOARD_VER__03 3 ++#define D_BOARD_VER__04 4 ++#define D_BOARD_VER__05 5 ++ ++// IC Version Option ++//----------------------------------------------------------------------------------------------------------- ++#define D_ICVER__00 0 ++#define D_ICVER__01 1 ++#define D_ICVER__02 2 ++#define D_ICVER__03 3 ++#define D_ICVER__04 4 ++#define D_ICVER__05 5 ++#define D_ICVER__06 6 ++#define D_ICVER__07 7 ++#define D_ICVER__08 8 ++#define D_ICVER__09 9 ++ ++ ++//*********************************************************************************************************** ++// (2) BASE Type Define ++//*********************************************************************************************************** ++typedef unsigned char U8_T; ++typedef unsigned short U16_T; ++typedef unsigned int U32_T; ++typedef unsigned long long U64_T; ++typedef signed char S8_T; ++typedef signed short S16_T; ++typedef signed int S32_T; ++typedef signed long long S64_T; ++typedef unsigned char BOOL_T; ++ ++#define FALSE 0 ++#define TRUE 1 ++ ++#define BIT00_T 0x0001 ++#define BIT01_T 0x0002 ++#define BIT02_T 0x0004 ++#define BIT03_T 0x0008 ++#define BIT04_T 0x0010 ++#define BIT05_T 0x0020 ++#define BIT06_T 0x0040 ++#define BIT07_T 0x0080 ++#define BIT08_T 0x0100 ++#define BIT09_T 0x0200 ++#define BIT10_T 0x0400 ++#define BIT11_T 0x0800 ++#define BIT12_T 0x1000 ++#define BIT13_T 0x2000 ++#define BIT14_T 0x4000 ++#define BIT15_T 0x8000 ++#define BIT16_T 0x00010000 ++#define BIT17_T 0x00020000 ++#define BIT18_T 0x00040000 ++#define BIT19_T 0x00080000 ++#define BIT20_T 0x00100000 ++#define BIT21_T 0x00200000 ++#define BIT22_T 0x00400000 ++#define BIT23_T 0x00800000 ++#define BIT24_T 0x01000000 ++#define BIT25_T 0x02000000 ++#define BIT26_T 0x04000000 ++#define BIT27_T 0x08000000 ++#define BIT28_T 0x10000000 ++#define BIT29_T 0x20000000 ++#define BIT30_T 0x40000000 ++#define BIT31_T 0x80000000 ++ ++typedef enum ++{ ++ EV_IP_FCIE1 = 0, ++ EV_IP_FCIE2 = 1, ++ EV_IP_FCIE3 = 2, ++ ++} IPEmType; ++ ++ ++typedef enum ++{ ++ EV_PORT_SD = 0, ++ EV_PORT_SDIO1 = 1, ++ EV_PORT_SDIO2 = 2, ++ EV_PFCIE5_FCIE = 3, //Use Port Setting for FCIE5 Function Ctrl Setting ++ EV_PFCIE5_SDIO = 4, //Use Port Setting for FCIE5 Function Ctrl Setting ++ ++} PortEmType; ++ ++typedef enum ++{ ++ EV_PAD1 = 0, ++ EV_PAD2 = 1, ++ EV_PAD3 = 2, ++ EV_PAD4 = 3, ++ EV_PAD5 = 4, ++ ++} PADEmType; ++ ++ ++typedef enum ++{ ++ EV_BUS_LOW = 0, ++ EV_BUS_DEF = 1, ++ EV_BUS_HS = 2, ++ EV_BUS_SDR12 = 3, ++ EV_BUS_SDR25 = 4, ++ EV_BUS_SDR50 = 5, ++ EV_BUS_SDR104 = 6, ++ EV_BUS_DDR50 = 7, ++ EV_BUS_HS200 = 8, ++ ++} BusTimingEmType; ++ ++ ++typedef enum ++{ ++ EV_OK = 0, ++ EV_FAIL = 1, ++ ++} RetEmType; ++ ++ ++//*********************************************************************************************************** ++// (3) BASE OS/CPU define and Include Files for Different OS/CPU ++//*********************************************************************************************************** ++#define D_OS D_OS__LINUX ++#define D_CPU D_CPU__ARM ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++//########################################################################################################### ++#elif (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++#include ++//########################################################################################################### ++#elif (D_OS == D_OS__NONE) ++//########################################################################################################### ++#include ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++ ++//*********************************************************************************************************** ++// (4) BASE Debug System ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#define prtstring(s) printk(s) ++#define prtUInt(v) printk("%u", v) ++#define prtU8(v) printk("0x%02X", v) ++#define prtU8Hex(v) printk("0x%02X", v) ++#define prtU16Hex(v) printk("0x%04X", v) ++#define prtU32Hex(v) printk("0x%08X", v) ++//########################################################################################################### ++#elif (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++#define prtstring(s) printf(s) ++#define prtUInt(v) printf("%u", v) ++#define prtU8(v) printf("0x%02X", v) ++#define prtU8Hex(v) printf("0x%02X", v) ++#define prtU16Hex(v) printf("0x%04X", v) ++#define prtU32Hex(v) printf("0x%08X", v) ++//########################################################################################################### ++#elif (D_OS == D_OS__NONE) ++//########################################################################################################### ++#define prtstring(s) uart_write_string((unsigned char*)s) ++#define prtUInt(v) uart_write_U32_hex(v) ++#define prtU8(v) uart_write_U8_hex(v) ++#define prtU8Hex(v) uart_write_U8_hex(v) ++#define prtU16Hex(v) uart_write_U16_hex(v) ++#define prtU32Hex(v) uart_write_U32_hex(v) ++//########################################################################################################### ++#elif (D_OS == D_OS__YBOX) ++//########################################################################################################### ++#define prtstring(s) printf(s) ++#define prtUInt(v) printf("%u", v) ++#define prtU8(v) printf("0x%02X", v) ++#define prtU8Hex(v) printf("0x%02X", v) ++#define prtU16Hex(v) printf("0x%04X", v) ++#define prtU32Hex(v) printf("0x%08X", v) ++//########################################################################################################### ++#else ++//########################################################################################################### ++#define prtstring(s) printf(s) ++#define prtUInt(v) printf("%u", v) ++#define prtU8(v) printf("0x%02X", v) ++#define prtU8Hex(v) printf("0x%02X", v) ++#define prtU16Hex(v) printf("0x%04X", v) ++#define prtU32Hex(v) printf("0x%08X", v) ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++ ++//*********************************************************************************************************** ++// (5) BASE Project/FCIE/Ver.. Define ++//*********************************************************************************************************** ++ ++#define D_ICVER D_ICVER_00 ++#define D_FCIE_R_VER D_FCIE_R_VER__00 ++//#define D_BDVER 0 ++ ++ ++//########################################################################################################### ++#if defined(CONFIG_ARCH_CEDRIC) ++//########################################################################################################### ++#define D_PROJECT D_PROJECT__C3 ++#define D_FCIE_M_VER D_FCIE_M_VER__04 ++//########################################################################################################### ++#elif defined(CONFIG_ARCH_CHICAGO) ++//########################################################################################################### ++#define D_PROJECT D_PROJECT__C4 ++#define D_FCIE_M_VER D_FCIE_M_VER__04 ++//########################################################################################################### ++#elif defined(CONFIG_ARCH_INFINITY) ++//########################################################################################################### ++#define D_PROJECT D_PROJECT__iNF ++#define D_FCIE_M_VER D_FCIE_M_VER__05 ++//########################################################################################################### ++#elif defined(CONFIG_ARCH_INFINITY3) ++//########################################################################################################### ++#define D_PROJECT D_PROJECT__iNF3 ++#define D_FCIE_M_VER D_FCIE_M_VER__05 ++//########################################################################################################### ++#endif ++ ++ ++ ++#endif //End of __HAL_CARD_BASE_H +\ No newline at end of file +diff --git a/drivers/mstar/sdmmc/inc/hal_card_intr.h b/drivers/mstar/sdmmc/inc/hal_card_intr.h +new file mode 100644 +index 00000000..325e586c +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_intr.h +@@ -0,0 +1,84 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_intr.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of hal_card_intr.c. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_INTR_H ++#define __HAL_CARD_INTR_H ++ ++#include "hal_card_regs.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++//#if (D_PROJECT == D_PROJECT__CB2) //For Columbus2 ++//########################################################################################################### ++ ++//########################################################################################################### ++//#elif (D_PROJECT == D_PROJECT__G2) //For G2 ++//########################################################################################################### ++ ++#define WT_INT_RISKTIME 10 //(ms) Add Risk Time for wait_event_timer ++ ++//########################################################################################################### ++//#endif ++ ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++ ++ ++typedef enum ++{ ++ EV_INT_SD = BIT00_T, ++ EV_INT_MS = BIT01_T, ++ EV_INT_CF = BIT02_T, ++ EV_INT_SM = BIT03_T, ++ EV_INT_XD = BIT04_T, ++ ++} IntCardEmType; ++ ++typedef struct ++{ ++ U32_T slotNo; ++ IPEmType eIP; ++ IntCardEmType eCardInt; ++ void * p_data; ++ ++} IntSourceStruct; ++ ++ ++void Hal_CARD_INT_MIEIntCtrl(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable); ++BOOL_T Hal_CARD_INT_MIEIntRunning(IPEmType eIP, IntCardEmType eCardInt); ++ ++void Hal_CARD_INT_SetMIEIntEn(IPEmType eIP, IntCardEmType eCardInt, U16_T u16RegMIEIntEN); ++void Hal_CARD_INT_SetMIEIntEn_ForSDIO(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable); ++ ++void Hal_CARD_INT_ClearMIEEvent(IPEmType eIP); ++U16_T Hal_CARD_INT_GetMIEEvent(IPEmType eIP); ++ ++BOOL_T Hal_CARD_INT_WaitMIEEvent(IPEmType eIP, U16_T u16ReqEvent, U32_T u32WaitMs); ++void Hal_CARD_INT_StopWaitMIEEventCtrl(IPEmType eIP, BOOL_T bEnable); ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include ++#include ++ ++irqreturn_t Hal_CARD_INT_MIE(int irq, void *p_dev_id); ++ ++#endif ++//########################################################################################################### ++ ++ ++ ++ ++#endif //End of __HAL_CARD_INTR_H +diff --git a/drivers/mstar/sdmmc/inc/hal_card_intr_v5.h b/drivers/mstar/sdmmc/inc/hal_card_intr_v5.h +new file mode 100644 +index 00000000..e008bc1b +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_intr_v5.h +@@ -0,0 +1,83 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_intr.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of hal_card_intr.c. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_INTR_H ++#define __HAL_CARD_INTR_H ++ ++#include "hal_card_regs.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++//#if (D_PROJECT == D_PROJECT__CB2) //For Columbus2 ++//########################################################################################################### ++ ++//########################################################################################################### ++//#elif (D_PROJECT == D_PROJECT__G2) //For G2 ++//########################################################################################################### ++ ++#define WT_INT_RISKTIME 10 //(ms) Add Risk Time for wait_event_timer ++ ++//########################################################################################################### ++//#endif ++ ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++ ++ ++typedef enum ++{ ++ EV_INT_SD = BIT00_T, ++ EV_INT_MS = BIT01_T, ++ EV_INT_CF = BIT02_T, ++ EV_INT_SM = BIT03_T, ++ EV_INT_XD = BIT04_T, ++ ++} IntCardEmType; ++ ++typedef struct ++{ ++ U32_T slotNo; ++ IPEmType eIP; ++ IntCardEmType eCardInt; ++ void * p_data; ++ ++} IntSourceStruct; ++ ++ ++void Hal_CARD_INT_MIEIntCtrl(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable); ++BOOL_T Hal_CARD_INT_MIEIntRunning(IPEmType eIP, IntCardEmType eCardInt); ++ ++void Hal_CARD_INT_SetMIEIntEn(IPEmType eIP, IntCardEmType eCardInt, U16_T u16RegMIEIntEN); ++void Hal_CARD_INT_SetMIEIntEn_ForSDIO(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable); ++void Hal_CARD_INT_ClearMIEEvent(IPEmType eIP); ++U16_T Hal_CARD_INT_GetMIEEvent(IPEmType eIP); ++ ++BOOL_T Hal_CARD_INT_WaitMIEEvent(IPEmType eIP, U16_T u16ReqEvent, U32_T u32WaitMs); ++void Hal_CARD_INT_StopWaitMIEEventCtrl(IPEmType eIP, BOOL_T bEnable); ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include ++#include ++ ++irqreturn_t Hal_CARD_INT_MIE(int irq, void *p_dev_id); ++ ++#endif ++//########################################################################################################### ++ ++ ++ ++ ++#endif //End of __HAL_CARD_INTR_H +diff --git a/drivers/mstar/sdmmc/inc/hal_card_platform.h b/drivers/mstar/sdmmc/inc/hal_card_platform.h +new file mode 100644 +index 00000000..b86f9f39 +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_platform.h +@@ -0,0 +1,117 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of hal_card_platform_XX.c. ++ * Every project has the same header file. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_PLATFORM_H ++#define __HAL_CARD_PLATFORM_H ++ ++#include "hal_card_regs.h" ++ ++typedef enum ++{ ++ EV_PULLDOWN, ++ EV_PULLUP, ++ ++} PinPullEmType; ++ ++typedef enum ++{ ++ EV_GPIO1 = 0, ++ EV_GPIO2 = 1, ++ EV_GPIO3 = 2, ++ ++} GPIOEmType; ++ ++typedef enum ++{ ++ EV_GPIO_OPT1 = 0, ++ EV_GPIO_OPT2 = 1, ++ EV_GPIO_OPT3 = 2, ++ EV_GPIO_OPT4 = 3, ++ EV_GPIO_OPT5 = 4, ++ ++} GPIOOptEmType; ++ ++typedef enum ++{ ++ EV_NORVOL = 0, ++ EV_LOWVOL = 1, ++ EV_MINVOL = 2, ++ ++} PADVddEmType; ++ ++typedef enum ++{ ++ EV_VDD_DUMMY = 0, ++ EV_VDD_165_195 = BIT07_T, ++ EV_VDD_20_21 = BIT08_T, ++ EV_VDD_21_22 = BIT09_T, ++ EV_VDD_22_23 = BIT10_T, ++ EV_VDD_23_24 = BIT11_T, ++ EV_VDD_24_25 = BIT12_T, ++ EV_VDD_25_26 = BIT13_T, ++ EV_VDD_26_27 = BIT14_T, ++ EV_VDD_27_28 = BIT15_T, ++ EV_VDD_28_29 = BIT16_T, ++ EV_VDD_29_30 = BIT17_T, ++ EV_VDD_30_31 = BIT18_T, ++ EV_VDD_31_32 = BIT19_T, ++ EV_VDD_32_33 = BIT20_T, ++ EV_VDD_33_34 = BIT21_T, ++ EV_VDD_34_35 = BIT22_T, ++ EV_VDD_35_36 = BIT23_T, ++ EV_VDD_50 = BIT24_T, ++ ++} VddEmType; ++ ++ ++void Hal_CARD_IPOnceSetting(IPEmType eIP); ++void Hal_CARD_IPBeginSetting(IPEmType eIP); ++void Hal_CARD_IPEndSetting(IPEmType eIP); ++ ++// PAD Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_InitPADPin(PADEmType ePAD, BOOL_T bTwoCard); ++void Hal_CARD_SetPADToPortPath(IPEmType eIP, PortEmType ePort, PADEmType ePAD, BOOL_T bTwoCard); ++void Hal_CARD_PullPADPin(PADEmType ePAD, PinPullEmType ePinPull, BOOL_T bTwoCard); ++ ++// Clock Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_SetClock(IPEmType eIP, U32_T u32ClkFromIPSet); ++U32_T Hal_CARD_FindClockSetting(IPEmType eIP, U32_T u32ReffClk, U8_T u8PassLevel, U8_T u8DownLevel); ++void Hal_CARD_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming); ++ ++// Power and Voltage Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_SetPADPower(PADEmType ePAD, PADVddEmType ePADVdd); ++void Hal_CARD_PowerOn(PADEmType ePAD, U16_T u16DelayMs); ++void Hal_CARD_PowerOff(PADEmType ePAD, U16_T u16DelayMs); ++ ++// Card Detect and GPIO Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++void Hal_CARD_InitGPIO(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bEnable); ++BOOL_T Hal_CARD_GetGPIOState(GPIOEmType eGPIO, PADEmType ePAD); ++void Hal_CARD_SetGPIOState(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bOutputState); ++U32_T Hal_CARD_GetGPIONum(GPIOEmType eGPIO, PADEmType ePAD); ++ ++ ++void Hal_CARD_SetGPIOIntAttr(GPIOEmType eGPIO, PADEmType ePAD, GPIOOptEmType eGPIOOPT); ++BOOL_T Hal_CARD_GPIOIntFilter(GPIOEmType eGPIO, PADEmType ePAD); ++ ++// MIU Setting for Card Platform ++//---------------------------------------------------------------------------------------------------------- ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr); ++ ++#endif //End of __HAL_CARD_PLATFORM_H ++ ++ ++ ++ ++ ++ +diff --git a/drivers/mstar/sdmmc/inc/hal_card_regs.h b/drivers/mstar/sdmmc/inc/hal_card_regs.h +new file mode 100644 +index 00000000..1209c44d +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_regs.h +@@ -0,0 +1,166 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_regs.h ++ * @author jeremy.wang (2015/08/12) ++ * Desc: ++ * This file is the header file of hal_card_regs.c. ++ * ++ * For Base RegisterSetting: ++ * (1) BASE Register Address ++ * (2) BASE Register Operation ++ * (3) BASE FCIE Reg Meaning Position (Including File) ++ * ++ * P.S. If you want to use only IP for single card or dual cards, ++ * please modify FCIE1 and FCIE2 setting to the same reg position. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_REGS_H ++#define __HAL_CARD_REGS_H ++ ++#include "hal_card_base.h" ++ ++//*********************************************************************************************************** ++// (1) BASE Register Address ++//*********************************************************************************************************** ++ ++ ++//########################################################################################################### ++#if (D_PROJECT == D_PROJECT__C3) ++//########################################################################################################### ++ ++#define A_RIU_BASE (0x1F000000) ++ ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9000) // SDIO0_0_BANK ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9080) // SDIO0_1_BANK ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9100) // SDIO0_2_BANK ++ ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9400) // SDIO2_0_BANK ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9480) // SDIO2_1_BANK ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9500) // SDIO2_2_BANK ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9200) // SDIO1_0_BANK ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9280) // SDIO1_1_BANK ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA9300) // SDIO1_2_BANK ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__C4) ++//########################################################################################################### ++ ++#define A_RIU_BASE (0x1F000000) ++ ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0A00) // SDIO0_0_BANK ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0A80) // SDIO0_1_BANK ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0B00) // SDIO0_2_BANK ++ ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0A00) ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0A80) ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0B00) ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0A00) ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0A80) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0B00) ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__iNF) ++//########################################################################################################### ++ ++#define A_RIU_BASE (0x1F000000) ++ ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //SDIO0_0_BANK ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //SDIO0_1_BANK ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //SDIO0_2_BANK ++ ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //FCIE0_0_BANK ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) //FCIE0_1_BANK ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) //FCIE0_2_BANK ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__iNF3) ++//########################################################################################################### ++ ++#define A_RIU_BASE (0x1F000000) ++ ++#define A_FCIE1_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0800) //SDIO0_0_BANK ++#define A_FCIE1_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0880) //SDIO0_1_BANK ++#define A_FCIE1_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0900) //SDIO0_2_BANK ++ ++#define A_FCIE2_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) //FCIE0_0_BANK ++#define A_FCIE2_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) //FCIE0_1_BANK ++#define A_FCIE2_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) //FCIE0_2_BANK ++ ++#define A_FCIE3_0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0100) ++#define A_FCIE3_1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0180) ++#define A_FCIE3_2_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0xA0200) ++ ++//########################################################################################################### ++#endif ++ ++ ++//*********************************************************************************************************** ++// (2) BASE Register Operation ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ //#if (D_PROJECT == D_PROJECT__C3) || (D_PROJECT == D_PROJECT__C4) || (D_PROJECT == D_PROJECT__iNF) ++ #include "../../../mstar/include/ms_platform.h" //IO_ADDRESS // IO Mapping Address ++ #define IO_MAPADDR(Reg_Addr) IO_ADDRESS(Reg_Addr) ++ //#endif ++//########################################################################################################### ++#else ++//########################################################################################################### ++#define IO_MAPADDR(Reg_Addr) Reg_Addr ++//########################################################################################################### ++#endif ++ ++#define D_MIU_WIDTH 8 // Special MIU WIDTH for FCIE4 ++#define REG_OFFSET_BITS 2 // Register Offset Byte (2= 4byte = 32bits) ++#define GET_CARD_REG_ADDR(x, y) ((x)+((y) << REG_OFFSET_BITS)) ++ ++#define CARD_REG(Reg_Addr) (*(volatile U16_T*)(IO_MAPADDR(Reg_Addr)) ) ++#define CARD_REG_L8(Reg_Addr) (*(volatile U8_T*)(IO_MAPADDR(Reg_Addr)) ) ++#define CARD_REG_H8(Reg_Addr) (*( (volatile U8_T*)(IO_MAPADDR(Reg_Addr))+1) ) ++ ++#define CARD_REG_SETBIT(Reg_Addr, Value) CARD_REG(Reg_Addr) |= (Value) ++#define CARD_REG_CLRBIT(Reg_Addr, Value) CARD_REG(Reg_Addr) &= (~(Value)) ++ ++#define CARD_REG_L8_SETBIT(Reg_Addr, Value) CARD_REG_L8(Reg_Addr) |= (Value) ++#define CARD_REG_H8_SETBIT(Reg_Addr, Value) CARD_REG_H8(Reg_Addr) |= (Value) ++#define CARD_REG_L8_CLRBIT(Reg_Addr, Value) CARD_REG_L8(Reg_Addr) &= (~(Value)) ++#define CARD_REG_H8_CLRBIT(Reg_Addr, Value) CARD_REG_H8(Reg_Addr) &= (~(Value)) ++ ++#define CARD_BANK(Bank_Addr) IO_MAPADDR(Bank_Addr) ++ ++volatile void* Hal_CREG_GET_REG_BANK(IPEmType eIP, U8_T u8Bank); ++void Hal_CREG_SET_PORT(IPEmType eIP, PortEmType ePort); ++volatile PortEmType Hal_CREG_GET_PORT(IPEmType eIP); ++ ++#define GET_CARD_BANK Hal_CREG_GET_REG_BANK ++#define GET_CARD_PORT Hal_CREG_GET_PORT ++#define SET_CARD_PORT Hal_CREG_SET_PORT ++ ++//*********************************************************************************************************** ++// (3) BASE FCIE Reg Meaning Position (Including File) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_FCIE_M_VER == D_FCIE_M_VER__04) ++//########################################################################################################### ++#include "hal_card_regs_v4.h" ++//########################################################################################################### ++#elif (D_FCIE_M_VER == D_FCIE_M_VER__05) ++//########################################################################################################### ++#include "hal_card_regs_v5.h" ++//########################################################################################################### ++#endif ++ ++ ++#endif //End of __HAL_CARD_REGS_H ++ ++ +diff --git a/drivers/mstar/sdmmc/inc/hal_card_regs_v4.h b/drivers/mstar/sdmmc/inc/hal_card_regs_v4.h +new file mode 100644 +index 00000000..f98dbf92 +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_regs_v4.h +@@ -0,0 +1,375 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_regs_v4.h ++ * @author jeremy.wang (2015/08/13) ++ * Desc: ++ * This file is the header file for hal_card_regs.h ++ * ++ * We add a new header file to describe the meaning positions of fcie5 registers ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_REGS_V4_H ++#define __HAL_CARD_REGS_V4_H ++ ++//============================================ ++//MIE_EVENT:offset 0x00 ++//============================================ ++#define R_MMA_DATA_END BIT00_T ++#define R_SD_CMD_END BIT01_T ++#define R_SD_DATA_END BIT02_T ++#define R_MS_DATA_END BIT03_T ++#define R_CF_CMD_END BIT04_T ++#define R_CF_DATA_END BIT05_T ++#define R_SM_JOB_END BIT06_T ++#define R_SDIO_INT BIT07_T ++#define R_MIU_WP_ERR BIT08_T ++#define R_NC_JOB_END BIT09_T ++#define R_NC_RIU2NAND_END BIT10_T ++#define R_CARD_DMA_END BIT11_T ++#define R_NC_R2N_ECC_ERR BIT12_T ++#define R_PWR_SAVE_END BIT13_T ++#define R_MMA_LSDONE_END BIT14_T ++#define R_BOOT_DONE_END BIT15_T //NEW ++ ++//============================================ ++//MIE_INT_EN:offset 0x01 ++//============================================ ++#define R_MMA_DATA_END_EN BIT00_T ++#define R_SD_CMD_END_EN BIT01_T ++#define R_SD_DATA_END_EN BIT02_T ++#define R_MS_DATA_END_EN BIT03_T ++#define R_CF_CMD_END_EN BIT04_T ++#define R_CF_DATA_END_EN BIT05_T ++#define R_SM_JOB_END_EN BIT06_T ++#define R_SDIO_INT_EN BIT07_T ++#define R_MIU_WP_ERR_EN BIT08_T ++#define R_NC_JOB_END_EN BIT09_T ++#define R_NC_RIU2NAND_EN BIT10_T ++#define R_CARD_DMA_END_EN BIT11_T ++#define R_PWR_SAVE_END_EN BIT13_T ++#define R_MMA_LSDONE_END_EN BIT14_T ++#define R_BOOT_DONE_END_EN BIT15_T //NEW ++ ++//============================================ ++//MMA_PRIORITY:offset 0x02 ++//============================================ ++#define R_MMA_R_PRIORITY BIT00_T ++#define R_MMA_W_PRIORITY BIT01_T ++#define R_JOB_RW_DIR BIT02_T ++#define R_DATA_SCRAM_EN BIT03_T ++#define R_MIU_REQ_RST BIT04_T ++#define R_FIFO_CLK_RDY BIT05_T ++#define R_MIU_BUS_BURST16 BIT08_T ++#define R_MIU_BUS_BURST32 BIT09_T ++#define R_MIU_BUS_CTRL_EN BIT10_T ++#define R_MIU_CLK_EN_SW BIT12_T //NEW ++#define R_MIU_CLK_EN_HW BIT13_T //NEW ++#define R_MIU_CLK_CTL_SW BIT14_T //NEW ++#define R_MIU_CLK_FREE BIT15_T //NEW ++ ++//============================================ ++//CARD_EVENT:offset 0x05 ++//============================================ ++#define R_SD_STS_CHG BIT00_T ++#define R_MS_STS_CHG BIT01_T ++#define R_CF_STS_CHG BIT02_T ++#define R_SM_STS_CHG BIT03_T ++#define R_XD_STS_CHG BIT04_T ++#define R_SD_PWR_OC_CHG BIT05_T ++#define R_CF_PWR_OC_CHG BIT06_T ++#define R_SDIO_STS_CHG BIT07_T ++#define R_SDIO2_STS_CHG BIT08_T ++ ++//============================================ ++//CARD_INT_EN:offset 0x06 ++//============================================ ++#define R_SD_STS_EN BIT00_T ++#define R_MS_STS_EN BIT01_T ++#define R_CF_STS_EN BIT02_T ++#define R_SM_STS_EN BIT03_T ++#define R_XD_STS_EN BIT04_T ++#define R_SD_PWR_OC_DET_EN BIT05_T ++#define R_CF_PWR_OC_DET_EN BIT06_T ++#define R_SD_CD_SRC BIT07_T // 0: SD_CDZ, 1: SD_DAT3 ++#define R_SDIO_STS_EN BIT08_T ++#define R_SDIO_CD_SRC BIT09_T ++#define R_SDIO2_STS_EN BIT10_T ++ ++//============================================ ++//CARD_DET:offset 0x07 ++//============================================ ++#define R_SD_DET_N BIT00_T ++#define R_MS_DET_N BIT01_T ++#define R_CF_DET_N BIT02_T ++#define R_SM_DET_N BIT03_T ++#define R_XD_DET_N BIT04_T ++#define R_SD_OCDET_STS BIT05_T ++#define R_CF_OCDET_STS BIT06_T ++#define R_SDIO_DET_N BIT07_T ++#define R_NF_RDBZ_STS BIT08_T // C3 ++#define R_SDIO2_DET_N BIT09_T ++ ++//============================================ ++//CARD_PWR:offset 0x08 ++//============================================ ++#define R_SD_PWR_ON BIT00_T ++#define R_CF_PWR_ON BIT01_T ++#define R_SD_PWR_PAD_OEN BIT02_T ++#define R_CF_PWR_PAD_OEN BIT03_T ++#define R_RIU2NAND_JOB_END_ACT BIT06_T // C3 for test ++#define R_NC_JOB_END_ACT BIT07_T // C3 for test ++ ++//============================================ ++//INTR_TEST:offset 0x09 all for test ++//============================================ ++#define R_FORCE_MMA_DATA_END BIT00_T ++#define R_FORCE_SD_CMD_END BIT01_T ++#define R_FORCE_SD_DATA_END BIT02_T ++#define R_FORCE_MS_DATA_END BIT03_T ++#define R_FORCE_CF_REQ_END BIT04_T ++#define R_FORCE_CF_DATA_END BIT05_T ++#define R_FORCE_SM_JOB_END BIT06_T ++#define R_FORCE_NC_JOB_END BIT06_T // for backward compatible ++#define R_FORCE_SDIO_INT BIT07_T ++#define R_FORCE_SD_STS_CHG BIT08_T ++#define R_FORCE_MS_STS_CHG BIT09_T ++#define R_FORCE_CF_STS_CHG BIT10_T ++#define R_FORCE_SM_STS_CHG BIT11_T ++#define R_FORCE_XD_STS_CHG BIT12_T ++#define R_FORCE_SD_OC_STS_CHG BIT13_T ++#define R_FORCE_CF_OC_STS_CHG BIT14_T ++#define R_FORCE_SDIO_STS_CHG BIT15_T ++ ++//============================================ ++//MIE_PATH_CTL:offset 0x0A ++//============================================ ++#define R_MMA_ENABLE BIT00_T ++#define R_SD_EN BIT01_T ++#define R_MS_EN BIT02_T ++#define R_CF_EN BIT03_T ++#define R_SM_EN BIT04_T ++#define R_NC_EN BIT05_T ++ ++//============================================ ++//JOB_BL_CNT:offset 0xB ++//============================================ ++#define R_JOB_BL_CNT0 BIT00_T ++#define R_JOB_BL_CNT1 BIT01_T ++#define R_JOB_BL_CNT2 BIT02_T ++#define R_JOB_BL_CNT3 BIT03_T ++#define R_JOB_BL_CNT4 BIT04_T ++#define R_JOB_BL_CNT5 BIT05_T ++#define R_JOB_BL_CNT6 BIT06_T ++#define R_JOB_BL_CNT7 BIT07_T ++ ++//============================================ ++//TR_BK_CNT:offset 0xC ++//============================================ ++#define R_TR_BK_CNT0 BIT00_T ++#define R_TR_BK_CNT1 BIT01_T ++#define R_TR_BK_CNT2 BIT02_T ++#define R_TR_BK_CNT3 BIT03_T ++#define R_TR_BK_CNT4 BIT04_T ++#define R_TR_BK_CNT5 BIT05_T ++#define R_TR_BK_CNT6 BIT06_T ++#define R_TR_BK_CNT7 BIT07_T ++ ++//============================================ ++//SD_MODE:offset 0x10 ++//============================================ ++#define R_SD_CLK_EN BIT00_T ++#define R_SD_4BITS BIT01_T ++#define R_SD_8BITS BIT02_T ++#define R_SDDRL BIT03_T ++#define R_SD_CS_EN BIT04_T ++#define R_SD_DEST BIT05_T // 0: Data FIFO, 1: CIF FIFO ++#define R_SD_DATSYNC BIT06_T ++#define R_MMC_BUS_TEST BIT07_T ++#define R_SDIO_RDWAIT BIT08_T ++#define R_SDIO_SD_BUS_SW BIT09_T ++#define R_SD_DMA_RD_CLK_STOP BIT11_T ++#define R_SDIO_PORT_SEL BIT12_T ++ ++//============================================ ++//SD_CTL:offset 0x11 ++//============================================ ++#define R_SD_RSPR2_EN BIT00_T // Response R2 type ++#define R_SD_RSP_EN BIT01_T ++#define R_SD_CMD_EN BIT02_T ++#define R_SD_DTRX_EN BIT03_T ++#define R_SD_DTRX_DIR BIT04_T // 0: R, 1:W ++#define R_SDIO_INT_MOD0 BIT08_T ++#define R_SDIO_INT_MOD1 BIT09_T ++#define R_SDIO_DET_ON BIT10_T ++#define R_SDIO_DET_INTSRC BIT11_T ++ ++//============================================ ++//SD_STS:offset 0x12 ++//============================================ ++#define R_SD_DAT_CERR BIT00_T ++#define R_SD_DAT_STSERR BIT01_T ++#define R_SD_DAT_STSNEG BIT02_T ++#define R_SD_CMD_NORSP BIT03_T ++#define R_SD_CMDRSP_CERR BIT04_T ++#define R_SD_WR_PRO_N BIT05_T ++#define R_SD_DAT0 BIT08_T ++#define R_SD_DAT1 BIT09_T ++#define R_SD_DAT2 BIT10_T ++#define R_SD_DAT3 BIT11_T ++#define R_SD_DAT4 BIT12_T ++#define R_SD_DAT5 BIT13_T ++#define R_SD_DAT6 BIT14_T ++#define R_SD_DAT7 BIT15_T ++ ++//============================================ ++//MS_CTL:offset 0x14 ++//============================================ ++#define R_MS_REGTRX_EN BIT00_T ++#define R_MS_DTRX_EN BIT01_T ++#define R_MS_BUS_DIR BIT02_T // 0: read form card, 1: Write to card ++#define R_MS_BURST BIT03_T ++#define R_MS_DEST BIT04_T ++ ++//============================================ ++//EMMC_PATH_CTL:offset 0x16 ++//============================================ ++#define R_EMMC_EN BIT00_T ++ ++//============================================ ++//CF_CTL:offset 0x1A ++//============================================ ++#define R_CF_REG_EN BIT00_T ++#define R_CF_DTRX_EN BIT01_T ++#define R_CF_BUS_DIR BIT02_T ++#define R_CF_DEST BIT03_T // 0: Data FIFO, 1: CIF FIFO ++#define R_CF_BURST BIT04_T ++#define R_CF_IORDY_DIS BIT05_T ++#define R_CF_BURST_ERR BIT06_T ++ ++//============================================ ++//SDIO_CTL:offset 0x1B ++//============================================ ++#define R_SDIO_BLK_MOD BIT15_T ++ ++//============================================ ++//SDIO_STS:offset 0x1E ++//============================================ ++#define R_SDIO_DAT0 BIT00_T ++#define R_SDIO_DAT1 BIT01_T ++#define R_SDIO_DAT2 BIT02_T ++#define R_SDIO_DAT3 BIT03_T ++ ++#define R_SDIO2_DAT0 BIT08_T ++#define R_SDIO2_DAT1 BIT09_T ++#define R_SDIO2_DAT2 BIT10_T ++#define R_SDIO2_DAT3 BIT11_T ++ ++//============================================ ++//NC_CIF_FIFO_CTL:offset 0x25 ++//============================================ ++// only need in montage serious ++#define R_CIFC_RD_REQ BIT00_T ++#define R_CIFD_RD_REQ BIT01_T ++ ++//============================================ ++//SM_CTL:offset 0x2B ++//============================================ ++#define R_SM_REG_EN BIT00_T ++#define R_SM_DTRX_EN BIT01_T ++#define R_SM_BUS_DIR BIT02_T ++#define R_SM_DEST BIT03_T ++#define R_SM_BURST BIT04_T ++ ++ ++//============================================ ++//NC_REORDER:offset 0x2D ++//============================================ ++#define R_MIU_WDEN_PATCH_DIS BIT07_T ++#define R_CSREG_PAD_IN_SEL BIT15_T ++ ++ ++//============================================ ++//eMMC_BOOT_CONFIG:offset 0x2F ++//============================================ ++#define R_BOOT_ST2 BIT00_T ++#define R_BOOT_END_EN BIT01_T ++#define R_BOOT_FROM_EN BIT02_T ++#define R_MACRO_EN BIT08_T ++#define R_SDDDRMODE BIT09_T ++#define R_SDYPASSMODE BIT10_T ++#define R_SDRINBYPASS BIT11_T ++#define R_FROM_TMUX BIT12_T ++#define R_CLKOE_DEL_EN BIT13_T ++#define R_SBIT_DDR_SEL BIT14_T ++ ++ ++//============================================ ++//TEST_MODE:offset 0x30 ++//============================================ ++#define R_DBFA_BISTFAIL BIT00_T ++#define R_DBFB_BISTFAIL BIT01_T ++#define R_CIFC_BISTFAIL BIT02_T ++#define R_CIFD_BISTFAIL BIT03_T ++#define R_PAD_SWAP BIT07_T ++#define R_DEBUG_MODE0 BIT08_T ++#define R_DEBUG_MODE1 BIT09_T ++#define R_DEBUG_MODE2 BIT10_T ++#define R_SD_MS_COBUS BIT11_T ++#define R_FCIE_SOFT_RST BIT12_T ++#define R_NFIE_SOFT_RESETZ BIT12_T // For backward compatible ++#define R_ENDIAN_SEL BIT13_T ++ ++//============================================ ++//NC_MISC offser 0x31 ++//============================================ ++//============================================ ++//PWRSAVE_MASK 0x34 ++//============================================ ++//============================================ ++//RWRSAVE_CTL 0x35 ++//============================================ ++#define R_PWRSAVE_EN BIT00_T ++#define R_PWRSAVE_TEST BIT01_T ++#define R_PWRSAVE_INT_EN BIT02_T ++#define R_PWRSAVE_RST_N BIT03_T // low active ++#define R_PWRSAVE_RIU_TEST BIT05_T ++#define R_PWRSAVE_HW_REST BIT06_T ++#define R_PWRSAVE_LOSS_PWR BIT07_T ++ ++//============================================ ++//MIU_WP_MIN_AH_S :offset 0x38 ++//============================================ ++#define R_MIU_WP_EN BIT08_T ++#define R_FORCE_MIU_WP_ERR BIT09_T ++//============================================ ++//MIU_WP_MIN_AL :offset 0x39 ++//============================================ ++//============================================ ++//MIU_WP_MAX_AH :offset 0x3A ++//============================================ ++//============================================ ++//MIU_WP_MAX_AL :offset 0x3B ++//============================================ ++//============================================ ++//MIU_WP_ERR_AH :offset 0x3C ++//============================================ ++//============================================ ++//MIU_WP_ERR_AL :offset 0x3D ++//============================================ ++//============================================ ++//FCIE_INFO :offset 0x3F ++//============================================ ++#define R_SDMMC_HW BIT00_T ++#define R_MS_HW BIT01_T ++#define R_CF_HW BIT02_T ++#define R_SM_HW BIT03_T ++#define R_SDIO_HW BIT04_T ++#define R_NAND_HW BIT05_T ++#define R_MIU_BUS_WIDTH (BIT06_T|WBIT07) ++#define R_MIU_BUS_ALIGN_BYTE BIT08_T ++#define R_PROGRAM_PAD BIT09_T ++#define R_PROGRAM_CLK BIT10_T ++ ++ ++#endif //End of __HAL_CARD_REGS_V4_H +diff --git a/drivers/mstar/sdmmc/inc/hal_card_regs_v5.h b/drivers/mstar/sdmmc/inc/hal_card_regs_v5.h +new file mode 100644 +index 00000000..d570792e +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_regs_v5.h +@@ -0,0 +1,226 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_regs_v5.h ++ * @author jeremy.wang (2015/06/03) ++ * Desc: ++ * This file is the header file for hal_card_regs.h ++ * ++ * We add a new header file to describe the meaning positions of fcie5 registers ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_CARD_REGS_V5_H ++#define __HAL_CARD_REGS_V5_H ++ ++//============================================ ++//MIE_EVENT: offset 0x00 ++//============================================ ++#define R_DATA_END BIT00_T ++#define R_CMD_END BIT01_T ++#define R_ERR_STS BIT02_T ++#define R_SDIO_INT BIT03_T ++#define R_BUSY_END_INT BIT04_T ++#define R_R2N_RDY_INT BIT05_T ++#define R_CARD_CHANGE BIT06_T ++#define R_CARD2_CHANGE BIT07_T ++ ++ ++//============================================ ++//MIE_INT_EN: offset 0x01 ++//============================================ ++#define R_DATA_END_IEN BIT00_T ++#define R_CMD_END_IEN BIT01_T ++#define R_ERR_STS_IEN BIT02_T ++#define R_SDIO_INT_IEN BIT03_T ++#define R_BUSY_END_IEN BIT04_T ++#define R_R2N_RDY_INT_IEN BIT05_T ++#define R_CARD_CHANGE_IEN BIT06_T ++#define R_CARD2_CHANGE_IEN BIT07_T ++ ++//============================================ ++//MMA_PRI_REG: offset 0x02 ++//============================================ ++#define R_MIU_R_PRIORITY BIT00_T ++#define R_MIU_W_PRIORITY BIT01_T ++ ++#define R_MIU1_SELECT BIT02_T ++#define R_MIU2_SELECT BIT03_T ++#define R_MIU3_SELECT (BIT03_T|BIT02_T) ++ ++#define R_MIU_BUS_BURST2 BIT04_T ++#define R_MIU_BUS_BURST4 BIT05_T ++#define R_MIU_BUS_BURST8 (BIT05_T|BIT04_T) ++ ++//============================================ ++//MIE_FUNC_CTL: offset 0x07 ++//============================================ ++#define R_EMMC_EN BIT00_T ++#define R_SD_EN BIT01_T ++#define R_SDIO_MODE BIT02_T ++ ++ ++//============================================ ++//SD_MODE: offset 0x0B ++//============================================ ++#define R_CLK_EN BIT00_T ++#define R_BUS_WIDTH_4 BIT01_T ++#define R_BUS_WIDTH_8 BIT02_T ++#define R_DEST_R2N BIT04_T ++#define R_DATASYNC BIT05_T ++#define R_DMA_RD_CLK_STOP BIT07_T ++#define R_DIS_WR_BUSY_CHK BIT08_T ++ ++ ++//============================================ ++//SD_CTL: offset 0x0C ++//============================================ ++#define R_RSPR2_EN BIT00_T ++#define R_RSP_EN BIT01_T ++#define R_CMD_EN BIT02_T ++#define R_DTRX_EN BIT03_T ++#define R_JOB_DIR BIT04_T ++#define R_ADMA_EN BIT05_T ++#define R_JOB_START BIT06_T ++#define R_CHK_CMD BIT07_T ++#define R_BUSY_DET_ON BIT08_T ++#define R_ERR_DET_ON BIT09_T ++ ++ ++//============================================ ++//SD_STS: offset 0x0D ++//============================================ ++#define R_DAT_RD_CERR BIT00_T ++#define R_DAT_WR_CERR BIT01_T ++#define R_DAT_WR_TOUT BIT02_T ++#define R_CMD_NORSP BIT03_T ++#define R_CMDRSP_CERR BIT04_T ++#define R_DAT_RD_TOUT BIT05_T ++#define R_CARD_BUSY BIT06_T ++#define R_DAT0 BIT08_T ++#define R_DAT1 BIT09_T ++#define R_DAT2 BIT10_T ++#define R_DAT3 BIT11_T ++#define R_DAT4 BIT12_T ++#define R_DAT5 BIT13_T ++#define R_DAT6 BIT14_T ++#define R_DAT7 BIT15_T ++ ++ ++//============================================ ++//BOOT_MOD:offset 0x0E ++//============================================ ++#define R_BOOT_MODE BIT02_T ++ ++ ++//============================================ ++//DDR_MOD: offset 0x0F ++//============================================ ++#define R_PAD_IN_BYPASS BIT00_T ++#define R_PAD_IN_RDY_SEL BIT01_T ++#define R_PRE_FULL_SEL0 BIT02_T ++#define R_PRE_FULL_SEL1 BIT03_T ++#define R_DDR_MACRO_EN BIT07_T ++#define R_DDR_EN BIT08_T ++#define R_PAD_CLK_SEL BIT10_T ++#define R_PAD_IN_SEL_IP BIT11_T ++#define R_DDR_MACRO32_EN BIT12_T ++#define R_PAD_IN_SEL BIT13_T ++#define R_FALL_LATCH BIT14_T ++#define R_PAD_IN_MASK BIT15_T ++ ++ ++//============================================ ++//SDIO_MOD: offset 0x11 ++//============================================ ++#define R_SDIO_INT_MOD0 BIT00_T ++#define R_SDIO_INT_MOD1 BIT01_T ++#define R_SDIO_INT_MOD_SW_EN BIT02_T ++#define R_SDIO_DET_INT_SRC BIT03_T ++#define R_SDIO_INT_TUNE0 BIT04_T ++#define R_SDIO_INT_TUNE1 BIT05_T ++#define R_SDIO_INT_TUNE2 BIT06_T ++#define R_SDIO_INT_TUNE_CLR0 BIT07_T ++#define R_SDIO_INT_TUNE_CLR1 BIT08_T ++#define R_SDIO_INT_TUNE_CLR2 BIT09_T ++#define R_SDIO_RDWAIT_EN BIT11_T ++#define R_SDIO_BLK_GAP_DIS BIT12_T ++#define R_SDIO_INT_STOP_DMA BIT13_T ++#define R_SDIO_INT_TUNE_SW BIT14_T ++#define R_SDIO_INT_ASYN_EN BIT15_T ++ ++ ++//============================================ ++//TEST_MOD: offset 0x15 ++//============================================ ++#define R_SDDR1 BIT00_T ++#define R_SD_DEBUG_MOD0 BIT01_T ++#define R_SD_DEBUG_MOD1 BIT02_T ++#define R_SD_DEBUG_MOD2 BIT03_T ++#define R_BIST_MODE BIT04_T ++ ++ ++//============================================ ++//WR_SBIT_TIMER: offset 0x17 ++//============================================ ++#define R_WR_SBIT_TIMER_EN BIT15_T ++ ++ ++//============================================ ++//RD_SBIT_TIMER: offset 0x18 ++//============================================ ++#define R_RD_SBIT_TIMER_EN BIT15_T ++ ++ ++//============================================ ++//SDIO_DET_ON: offset 0x2F ++//============================================ ++#define R_SDIO_DET_ON BIT00_T ++ ++ ++//============================================ ++//CIFD_EVENT: offset 0x30 ++//============================================ ++#define R_WBUF_FULL BIT00_T ++#define R_WBUF_EMPTY_TRIG BIT01_T ++#define R_RBUF_FULL_TRIG BIT02_T ++#define R_RBUF_EMPTY BIT03_T ++ ++ ++//============================================ ++//CIFD_INT_EN: offset 0x31 ++//============================================ ++#define R_WBUF_FULL_IEN BIT00_T ++#define R_RBUF_EMPTY_IEN BIT01_T ++#define R_F_WBUF_FULL_INT BIT08_T ++#define R_F_RBUF_EMPTY_INT BIT09_T ++ ++ ++//============================================ ++//BOOT_MODE:offset 0x37 ++//============================================ ++#define R_NAND_BOOT_EN BIT00_T ++#define R_BOOTSRAM_ACCESS_SEL BIT01_T ++#define R_IMI_SEL BIT02_T ++ ++ ++//============================================ ++//CIFD_INT_EN: offset 0x39 ++//============================================ ++#define R_DEBUG_MOD0 BIT08_T ++#define R_DEBUG_MOD1 BIT09_T ++#define R_DEBUG_MOD2 BIT10_T ++#define R_DEBUG_MOD3 BIT11_T ++ ++ ++//============================================ ++//FCIE_RST:offset 0x3F ++//============================================ ++#define R_FCIE_SOFT_RST BIT00_T ++#define R_RST_MIU_STS BIT01_T ++#define R_RST_MIE_STS BIT02_T ++#define R_RST_MCU_STS BIT03_T ++#define R_RST_ECC_STS BIT04_T ++ ++ ++ ++#endif //End of __HAL_CARD_FCIE5_H +diff --git a/drivers/mstar/sdmmc/inc/hal_card_timer.h b/drivers/mstar/sdmmc/inc/hal_card_timer.h +new file mode 100644 +index 00000000..b0c58d2b +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_card_timer.h +@@ -0,0 +1,20 @@ ++#ifndef __HAL_CARD_TIMER_H ++#define __HAL_CARD_TIMER_H ++ ++#include "hal_card_regs.h" ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include ++//########################################################################################################### ++#endif ++ ++U32_T Hal_Timer_mDelay(U32_T u32_msec); ++U32_T Hal_Timer_uDelay(U32_T u32_usec); ++U32_T Hal_Timer_mSleep(U32_T u32_msec); ++ ++ ++ ++#endif //End of __HAL_CARD_TIMER_H +diff --git a/drivers/mstar/sdmmc/inc/hal_sdmmc.h b/drivers/mstar/sdmmc/inc/hal_sdmmc.h +new file mode 100644 +index 00000000..aa494861 +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_sdmmc.h +@@ -0,0 +1,223 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_sdmmc.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of hal_sdmmc.c. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __HAL_SDMMC_H ++#define __HAL_SDMMC_H ++ ++#include "hal_card_regs.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_PROJECT == D_PROJECT__C3) //For Cedric ++//########################################################################################################### ++ ++#define EN_MIU_WDEN_PATCH_DIS (FALSE) ++ ++#define V_MIUCLK_CTRL_INIT (R_MIU_CLK_EN_HW) //HW ++#define V_MIUBUS_CTRL_INIT 0 //Disable MIU Bus Burst Ctrl ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__C4) //For Chicago ++//########################################################################################################### ++ ++#define EN_MIU_WDEN_PATCH_DIS (FALSE) ++ ++#define V_MIUCLK_CTRL_INIT (R_MIU_CLK_EN_HW) //HW ++#define V_MIUBUS_CTRL_INIT 0 //Disable MIU Bus Burst Ctrl ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++//########################################################################################################### ++#else //Templete Description ++//########################################################################################################### ++/* ++ ++#define EN_MIU_WDEN_PATCH_DIS (FALSE) ++ ++#define V_MIUCLK_CTRL_INIT (R_MIU_CLK_EN_SW|R_MIU_CLK_CTL_SW) //SW ++#define V_MIUBUS_CTRL_INIT (R_MIU_BUS_CTRL_EN) //Enable and Burst8 (32Bytes) ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++*/ ++#endif ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) //For LInux ++//########################################################################################################### ++#define EN_BIND_CARD_INT (TRUE) ++//########################################################################################################### ++#elif (D_OS == D_OS__UBOOT) //For UBoot ++//########################################################################################################### ++#define EN_BIND_CARD_INT (FALSE) ++//########################################################################################################### ++#endif ++ ++ ++ ++//*********************************************************************************************************** ++ ++typedef enum ++{ ++ //SD_STS Reg Error ++ EV_STS_OK = 0x0000, ++ EV_STS_DAT_CERR = BIT00_T, ++ EV_STS_DAT_STSERR = BIT01_T, ++ EV_STS_DAT_STSNEG = BIT02_T, ++ EV_STS_NORSP = BIT03_T, ++ EV_STS_RSP_CERR = BIT04_T, ++ ++ //SD IP Error ++ EV_STS_RIU_ERR = BIT05_T, ++ EV_STS_MIE_TOUT = BIT06_T, ++ EV_STS_FIFO_NRDY = BIT07_T, ++ EV_STS_DAT0_BUSY = BIT08_T, ++ ++ //Stop Wait Process Error ++ EV_SWPROC_ERR = BIT09_T, ++ ++ //SD Driver Check Error ++ EV_CMD8_PERR = BIT10_T, //Not Use ++ EV_OCR_BERR = BIT11_T, //Not Use ++ EV_OUT_VOL_RANGE = BIT12_T, //Not Use ++ EV_STATE_ERR = BIT13_T, //Not Use ++ ++ //Other Error ++ EV_OTHER_ERR = BIT15_T, ++ ++ ++} RspErrEmType; ++ ++//(5bits: Position Mapping to SD_CTL) (4bits: Identity) ++typedef enum ++{ ++ EV_CMDRSP =0x000, ++ EV_CMDREAD =0x001, ++ EV_CMDWRITE =0x101, ++ ++} CmdEmType; ++ ++//(6bits: Position Mapping to SD_Mode) (8bits: Position Mapping to MIE_Path) ++typedef enum ++{ ++ EV_EMP = 0x0000, ++ EV_DMA = 0x0001, ++ EV_CIF = 0x2000, ++ ++} TransEmType; ++ ++//(2bits: Rsp Mapping to SD_CTL) (4bits: Identity) (8bits: RspSize) ++typedef enum ++{ ++ EV_NO = 0x0000, //No response type ++ EV_R1 = 0x2105, ++ EV_R1B = 0x2205, ++ EV_R2 = 0x3310, ++ EV_R3 = 0x2405, ++ EV_R4 = 0x2505, ++ EV_R5 = 0x2605, ++ EV_R6 = 0x2705, ++ EV_R7 = 0x2805, ++ ++} SDMMCRspEmType; ++ ++ ++typedef enum ++{ ++ EV_BUS_1BIT = 0x00, ++ EV_BUS_4BITS = 0x02, ++ EV_BUS_8BITS = 0x04, ++ ++} SDMMCBusWidthEmType; ++ ++ ++typedef enum ++{ ++ EV_EGRP_OK = 0x0, ++ EV_EGRP_TOUT = 0x1, ++ EV_EGRP_COMM = 0x2, ++ EV_EGRP_OTHER = 0x3, ++ ++} ErrGrpEmType; ++ ++ ++typedef struct ++{ ++ U8_T u8Cmd; ++ U32_T u32Arg; ++ U32_T u32ErrLine; ++ RspErrEmType eErrCode; ++ U8_T u8RspSize; ++ U8_T u8ArrRspToken[0x10]; ++ ++} RspStruct; ++ ++ ++// SDMMC Mechanism Detection Function ++//---------------------------------------------------------------------------------------------------------- ++BOOL_T Hal_SDMMC_WriteProtect(IPEmType eIP); ++BOOL_T Hal_SDMMC_CardDetect(IPEmType eIP); ++ ++// SDMMC Operation Function ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_SetDataWidth(IPEmType eIP, SDMMCBusWidthEmType eBusWidth); ++void Hal_SDMMC_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming); ++void Hal_SDMMC_SetNrcDelay(IPEmType eIP, U32_T u32RealClk); ++ ++void Hal_SDMMC_SetCmdToken(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg); ++RspStruct* Hal_SDMMC_GetRspToken(IPEmType eIP); ++void Hal_SDMMC_TransCmdSetting(IPEmType eIP, TransEmType eTransType, U16_T u16BlkCnt, U16_T u16BlkSize, volatile U32_T u32BufAddr, volatile U8_T *pu8Buf); ++RspErrEmType Hal_SDMMC_SendCmdAndWaitProcess(IPEmType eIP, TransEmType eTransType, CmdEmType eCmdType, SDMMCRspEmType eRspType, BOOL_T bCloseClk); ++RspErrEmType Hal_SDMMC_RunBrokenDmaAndWaitProcess(IPEmType eIP, CmdEmType eCmdType); ++ ++// SDMMC Special Operation Function ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_ClkCtrl(IPEmType eIP, BOOL_T bEnable, U16_T u16DelayMs); ++void Hal_SDMMC_Reset(IPEmType eIP); ++void Hal_SDMMC_StopProcessCtrl(IPEmType eIP, BOOL_T bEnable); ++BOOL_T Hal_SDMMC_OtherPreUse(IPEmType eIP); ++ErrGrpEmType Hal_SDMMC_ErrGroup(RspErrEmType eErrType); ++ ++// SDMMC Information ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_DumpMemTool(U8_T u8ListNum, volatile U8_T *pu8Buf); ++U8_T Hal_SDMMC_GetDATBusLevel(IPEmType eIP); ++U16_T Hal_SDMMC_GetMIEEvent(IPEmType eIP); ++ ++// SDMMC SDIO Setting ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_SDIODeviceCtrl(IPEmType eIP, BOOL_T bEnable); ++void Hal_SDMMC_SDIOIntDetCtrl(IPEmType eIP, BOOL_T bEnable); ++void Hal_SDMMC_SetSDIOIntBeginSetting(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg, CmdEmType eCmdType, U16_T u16BlkCnt); ++void Hal_SDMMC_SetSDIOIntEndSetting(IPEmType eIP, RspErrEmType eRspErr, U16_T u16BlkCnt); ++ ++// SDMMC Interrupt Setting ++//---------------------------------------------------------------------------------------------------------- ++#if(EN_BIND_CARD_INT) ++ ++void Hal_SDMMC_MIEIntCtrl(IPEmType eIP, BOOL_T bEnable); ++ ++void Hal_SDMMC_SetMIEIntEn_ForV4(IPEmType eIP, TransEmType eTransType); ++ ++#endif //End of EN_BIND_CARD_INT ++ ++ ++ ++#endif //End of __HAL_SDMMC_H +diff --git a/drivers/mstar/sdmmc/inc/hal_sdmmc_v5.h b/drivers/mstar/sdmmc/inc/hal_sdmmc_v5.h +new file mode 100644 +index 00000000..559e077e +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/hal_sdmmc_v5.h +@@ -0,0 +1,209 @@ ++#ifndef __HAL_SDMMC_V5_H ++#define __HAL_SDMMC_V5_H ++ ++#include "hal_card_regs.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_PROJECT == D_PROJECT__iNF) ++//########################################################################################################### ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__iNF3) ++//########################################################################################################### ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++//########################################################################################################### ++#else ++//########################################################################################################### ++ ++#define WT_EVENT_RSP 10 //(ms) ++#define WT_EVENT_READ 2000 //(ms) ++#define WT_EVENT_WRITE 3000 //(ms) ++ ++//########################################################################################################### ++#endif ++ ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) //For LInux ++//########################################################################################################### ++#define EN_BIND_CARD_INT (TRUE) ++//########################################################################################################### ++#else ++//########################################################################################################### ++#define EN_BIND_CARD_INT (FALSE) ++//########################################################################################################### ++#endif ++ ++ ++ ++typedef enum ++{ ++ //SD_STS Reg Error ++ EV_STS_OK = 0x0000, ++ EV_STS_RD_CERR = BIT00_T, ++ EV_STS_WD_CERR = BIT01_T, ++ EV_STS_WR_TOUT = BIT02_T, ++ EV_STS_NORSP = BIT03_T, ++ EV_STS_RSP_CERR = BIT04_T, ++ EV_STS_RD_TOUT = BIT05_T, ++ ++ //SD IP Error ++ EV_STS_RIU_ERR = BIT06_T, ++ EV_STS_DAT0_BUSY = BIT07_T, ++ EV_STS_MIE_TOUT = BIT08_T, ++ ++ //Stop Wait Process Error ++ EV_SWPROC_ERR = BIT09_T, ++ ++ //SD Check Error ++ EV_CMD8_PERR = BIT10_T, ++ EV_OCR_BERR = BIT11_T, ++ EV_OUT_VOL_RANGE = BIT12_T, ++ EV_STATE_ERR = BIT13_T, ++ ++ //Other Error ++ EV_OTHER_ERR = BIT15_T, ++ ++ ++} RspErrEmType; ++ ++typedef enum ++{ ++ EV_CMDRSP =0x000, ++ EV_CMDREAD =0x001, ++ EV_CMDWRITE =0x101, ++ ++} CmdEmType; ++ ++typedef enum ++{ ++ EV_EMP = 0x0000, ++ EV_ADMA = 0x0020, //Add at FCIE5 ++ EV_DMA = 0x0080, //Change at FCIE5 ++ EV_CIF = 0x1000, //Change at FCIE5 ++ ++} TransEmType; ++ ++//(2bits: Rsp Mapping to SD_CTL) (4bits: Identity) (8bits: RspSize) ++typedef enum ++{ ++ EV_NO = 0x0000, //No response type ++ EV_R1 = 0x2105, ++ EV_R1B = 0x2205, ++ EV_R2 = 0x3310, ++ EV_R3 = 0x2405, ++ EV_R4 = 0x2505, ++ EV_R5 = 0x2605, ++ EV_R6 = 0x2705, ++ EV_R7 = 0x2805, ++ ++} SDMMCRspEmType; ++ ++typedef enum ++{ ++ EV_BUS_1BIT = 0x00, ++ EV_BUS_4BITS = 0x02, ++ EV_BUS_8BITS = 0x04, ++ ++} SDMMCBusWidthEmType; ++ ++typedef enum ++{ ++ EV_MIE = 0x0, ++ EV_CIFD = 0x1, ++ ++} IPEventEmType; ++ ++ ++typedef enum ++{ ++ EV_EGRP_OK = 0x0, ++ EV_EGRP_TOUT = 0x1, ++ EV_EGRP_COMM = 0x2, ++ EV_EGRP_OTHER = 0x3, ++ ++} ErrGrpEmType; ++ ++typedef struct ++{ ++ U8_T u8Cmd; ++ U32_T u32Arg; //Mark for ROM ++ U32_T u32ErrLine; //Mark for ROM ++ RspErrEmType eErrCode; ++ U8_T u8RspSize; //Mark for ROM ++ U8_T u8ArrRspToken[0x10]; //U8_T u8ArrRspToken[0x10]; //Mark for ROM ++ ++} RspStruct; ++ ++ ++typedef struct ++{ ++ U32_T u32_End : 1; ++ U32_T u32_MiuSel : 2; ++ U32_T : 13; ++ U32_T u32_JobCnt : 16; ++ U32_T u32_Address; ++ U32_T u32_DmaLen; ++ U32_T u32_Dummy; ++ ++} AdmaDescStruct; ++ ++ ++// SDMMC Operation Function ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_SetDataWidth(IPEmType eIP, SDMMCBusWidthEmType eBusWidth); ++void Hal_SDMMC_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming); ++void Hal_SDMMC_SetNrcDelay(IPEmType eIP, U32_T u32RealClk); ++ ++void Hal_SDMMC_SetCmdToken(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg); ++RspStruct* Hal_SDMMC_GetRspToken(IPEmType eIP); ++void Hal_SDMMC_TransCmdSetting(IPEmType eIP, TransEmType eTransType, U16_T u16BlkCnt, U16_T u16BlkSize, volatile U32_T u32BufAddr, volatile U8_T *pu8Buf); ++RspErrEmType Hal_SDMMC_SendCmdAndWaitProcess(IPEmType eIP, TransEmType eTransType, CmdEmType eCmdType, SDMMCRspEmType eRspType, BOOL_T bCloseClk); ++RspErrEmType Hal_SDMMC_RunBrokenDmaAndWaitProcess(IPEmType eIP, CmdEmType eCmdType); ++void Hal_SDMMC_ADMASetting(volatile void *pDMATable, U8_T u8Item, U32_T u32SubLen, U16_T u16SubBCnt, U32_T u32SubAddr, U8_T u8MIUSel, BOOL_T bEnd); ++ ++// SDMMC Special Operation Function ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_ClkCtrl(IPEmType eIP, BOOL_T bEnable, U16_T u16DelayMs); ++void Hal_SDMMC_Reset(IPEmType eIP); ++void Hal_SDMMC_StopProcessCtrl(IPEmType eIP, BOOL_T bEnable); ++BOOL_T Hal_SDMMC_OtherPreUse(IPEmType eIP); ++ErrGrpEmType Hal_SDMMC_ErrGroup(RspErrEmType eErrType); ++ ++// SDMMC Information ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_DumpMemTool(U8_T u8ListNum, volatile U8_T *pu8Buf); ++U8_T Hal_SDMMC_GetDATBusLevel(IPEmType eIP); ++U16_T Hal_SDMMC_GetMIEEvent(IPEmType eIP); ++ ++// SDMMC SDIO Setting ++//---------------------------------------------------------------------------------------------------------- ++void Hal_SDMMC_SDIODeviceCtrl(IPEmType eIP, BOOL_T bEnable); ++void Hal_SDMMC_SDIOIntDetCtrl(IPEmType eIP, BOOL_T bEnable); ++void Hal_SDMMC_SetSDIOIntBeginSetting(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg, CmdEmType eCmdType, U16_T u16BlkCnt); ++void Hal_SDMMC_SetSDIOIntEndSetting(IPEmType eIP, RspErrEmType eRspErr, U16_T u16BlkCnt); ++ ++// SDMMC Interrupt Setting ++//---------------------------------------------------------------------------------------------------------- ++#if(EN_BIND_CARD_INT) ++ ++void Hal_SDMMC_MIEIntCtrl(IPEmType eIP, BOOL_T bEnable); ++ ++ ++#endif //End of EN_BIND_CARD_INT ++ ++ ++ ++#endif //End of __HAL_SDMMC_V5_H +diff --git a/drivers/mstar/sdmmc/inc/ms_sdmmc_lnx.h b/drivers/mstar/sdmmc/inc/ms_sdmmc_lnx.h +new file mode 100644 +index 00000000..3c73f36a +--- /dev/null ++++ b/drivers/mstar/sdmmc/inc/ms_sdmmc_lnx.h +@@ -0,0 +1,563 @@ ++/*************************************************************************************************************** ++ * ++ * FileName ms_sdmmc_lnx.h ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This file is the header file of ms_sdmmc_lnx.c. ++ * ++ ***************************************************************************************************************/ ++ ++#ifndef __MS_SDMMC_LNX_H ++#define __MS_SDMMC_LNX_H ++ ++#include ++#include ++#include "hal_card_base.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Externel) ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if (D_PROJECT == D_PROJECT__iNF3) //For iNF3 (Two Slots) ++//########################################################################################################### ++ ++ #define EN_DEV_TREE_SUP (TRUE) ++ ++ #define D_IP1_IP EV_IP_FCIE1 //SDIO ++ #define D_IP1_PORT EV_PFCIE5_SDIO //Port Setting for FCIE5 (SDIO) ++ ++ #define D_IP2_IP EV_IP_FCIE2 //FCIE ++ #define D_IP2_PORT EV_PFCIE5_FCIE //Port Setting for FCIE5 (FCIE) ++ ++ #define D_IP3_IP EV_IP_FCIE3 //FCIE ++ #define D_IP3_PORT EV_PFCIE5_FCIE //Port Setting for FCIE5 (FCIE) ++ ++ ++ #define WT_POWERUP 20 //(ms) ++ #define WT_POWERON 60 //(ms) ++ #define WT_POWEROFF 80 //(ms) ++ ++ ++ #define D_SDMMC1_MUTEX EV_MUTEX1 ++ #define D_SDMMC2_MUTEX EV_MUTEX2 ++ #define D_SDMMC3_MUTEX EV_MUTEX3 ++ ++ #define EV_SDMMC1_DOWN_LVL (FALSE) ++ #define EV_SDMMC2_DOWN_LVL (FALSE) ++ #define EV_SDMMC3_DOWN_LVL (FALSE) ++ ++ #define EV_SDMMC1_SDIO_IRQ (FALSE) ++ #define EV_SDMMC2_SDIO_IRQ (FALSE) ++ #define EV_SDMMC3_SDIO_IRQ (FALSE) ++ #define EV_SDMMC1_SDIO_PRT (FALSE) ++ #define EV_SDMMC2_SDIO_PRT (FALSE) ++ #define EV_SDMMC3_SDIO_PRT (FALSE) ++ ++ #include "../../../mstar/include/infinity3/irqs.h" ++ ++ #define V_IP1_MIEIRQ (INT_IRQ_SDIO+32) ++ #define V_IP2_MIEIRQ (INT_IRQ_FCIE+32) ++ #define V_IP3_MIEIRQ 0 ++ ++ #define V_IP_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ ++ #define V_PAD1_CDZIRQ (INT_FIQ_SD_CDZ+32) ++ #define V_PAD2_CDZIRQ (INT_PMSLEEP_GPIO_7+160) ++ #define V_PAD3_CDZIRQ 0 ++ ++ #define V_PAD1_PWRGPIO (19) ++ #define V_PAD2_PWRGPIO 0 ++ #define V_PAD3_PWRGPIO 0 ++ ++ #define V_PAD1_CDZIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_PAD2_CDZIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_PAD3_CDZIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ ++ #define EN_PAD1_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD2_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD3_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD1_CDZIRQ_WAKEUP (FALSE) ++ #define EN_PAD2_CDZIRQ_WAKEUP (FALSE) ++ #define EN_PAD3_CDZIRQ_WAKEUP (FALSE) ++ ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__iNF) //For iNfinity ++//########################################################################################################### ++ ++ #define EN_DEV_TREE_SUP (TRUE) ++ ++ #define D_IP1_IP EV_IP_FCIE1 //SDIO ++ #define D_IP1_PORT EV_PFCIE5_SDIO //Port Setting for FCIE5 (SDIO) ++ ++ #define D_IP2_IP EV_IP_FCIE2 //FCIE ++ #define D_IP2_PORT EV_PFCIE5_FCIE //Port Setting for FCIE5 (FCIE) ++ ++ #define D_IP3_IP EV_IP_FCIE3 //FCIE ++ #define D_IP3_PORT EV_PFCIE5_FCIE //Port Setting for FCIE5 (FCIE) ++ ++ #define WT_POWERUP 20 //(ms) ++ #define WT_POWERON 60 //(ms) ++ #define WT_POWEROFF 25 //(ms) ++ ++ ++ #define D_SDMMC1_MUTEX EV_MUTEX1 ++ #define D_SDMMC2_MUTEX EV_MUTEX2 ++ #define D_SDMMC3_MUTEX EV_MUTEX3 ++ ++ #define EV_SDMMC1_DOWN_LVL (FALSE) ++ #define EV_SDMMC2_DOWN_LVL (FALSE) ++ #define EV_SDMMC3_DOWN_LVL (FALSE) ++ ++ #define EV_SDMMC1_SDIO_IRQ (FALSE) ++ #define EV_SDMMC2_SDIO_IRQ (FALSE) ++ #define EV_SDMMC3_SDIO_IRQ (FALSE) ++ #define EV_SDMMC1_SDIO_PRT (FALSE) ++ #define EV_SDMMC2_SDIO_PRT (FALSE) ++ #define EV_SDMMC3_SDIO_PRT (FALSE) ++ ++ #include "../../../mstar/include/infinity/irqs.h" ++ ++ #define V_IP1_MIEIRQ (INT_IRQ_SDIO+32) ++ #define V_IP2_MIEIRQ (INT_IRQ_FCIE+32) ++ #define V_IP3_MIEIRQ 0 ++ ++ #define V_IP_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ ++ #define V_PAD1_CDZIRQ (INT_FIQ_SD_CDZ+32) ++ #define V_PAD2_CDZIRQ (INT_FIQ_SD_CDZ+32) ++ #define V_PAD3_CDZIRQ 0 ++ ++ #define V_PAD1_PWRGPIO 0 ++ #define V_PAD2_PWRGPIO 0 ++ #define V_PAD3_PWRGPIO 0 ++ ++ #define V_PAD1_CDZIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_PAD2_CDZIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_PAD3_CDZIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ ++ #define EN_PAD1_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD2_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD3_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD1_CDZIRQ_WAKEUP (FALSE) ++ #define EN_PAD2_CDZIRQ_WAKEUP (FALSE) ++ #define EN_PAD3_CDZIRQ_WAKEUP (FALSE) ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__C3) //For Cedric ++//########################################################################################################### ++ #define D_SDMMC1_IP EV_IP_FCIE1 //SDIO0 ++ #define D_SDMMC1_PORT EV_PORT_SDIO1 //Port Setting ++ #define D_SDMMC1_PAD EV_PAD1 //PAD_SD0 ++ #define D_SDMMC1_MUTEX EV_MUTEX1 ++ ++ #define D_SDMMC2_IP EV_IP_FCIE2 //SDIO1 ++ #define D_SDMMC2_PORT EV_PORT_SDIO1 ++ #define D_SDMMC2_PAD EV_PAD2 //PAD_SD1 ++ #define D_SDMMC2_MUTEX EV_MUTEX2 ++ ++ #define D_SDMMC3_IP EV_IP_FCIE3 //SDIO0 ++ #define D_SDMMC3_PORT EV_PORT_SDIO1 //Port Setting ++ #define D_SDMMC3_PAD EV_PAD3 //PAD_SD0 ++ #define D_SDMMC3_MUTEX EV_MUTEX3 //EV_NOMUTEX ++ ++ #define WT_POWERUP 20 //(ms) ++ #define WT_POWERON 60 //(ms) ++ #define WT_POWEROFF 25 //(ms) ++ ++ #define EN_DEV_TREE_SUP (TRUE) ++ ++ #define EN_PAD1_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD2_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD3_CDZIRQ_SHARD (FALSE) ++ #define EN_PAD1_CDZIRQ_WAKEUP (FALSE) ++ #define EN_PAD2_CDZIRQ_WAKEUP (FALSE) ++ #define EN_PAD3_CDZIRQ_WAKEUP (FALSE) ++ #define EV_SDMMC1_DOWN_LVL (FALSE) ++ #define EV_SDMMC2_DOWN_LVL (FALSE) ++ #define EV_SDMMC3_DOWN_LVL (FALSE) ++ ++ #define EV_SDMMC1_SDIO_IRQ (FALSE) ++ #define EV_SDMMC2_SDIO_IRQ (FALSE) ++ #define EV_SDMMC3_SDIO_IRQ (TRUE) ++ #define EV_SDMMC1_SDIO_PRT (FALSE) ++ #define EV_SDMMC2_SDIO_PRT (FALSE) ++ #define EV_SDMMC3_SDIO_PRT (TRUE) ++ ++ #define V_SDMMC1_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC2_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC3_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC1_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ #define V_SDMMC2_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ #define V_SDMMC3_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ ++ #include "../../../mstar/include/cedric/irqs.h" ++ #define V_SDMMC1_MIEIRQ INT_IRQ_SDIO2RIU ++ #define V_SDMMC2_MIEIRQ INT_IRQ_SDIO2_2RIU ++ #define V_SDMMC3_MIEIRQ INT_IRQ_SDIO1_2RIU ++ #define V_SDMMC1_CDZIRQ INT_PMU_SD_DETECT0 ++ #define V_SDMMC2_CDZIRQ INT_PMU_SD_DETECT2 ++ #define V_SDMMC3_CDZIRQ INT_PMU_SD_DETECT1 ++ ++ ++//########################################################################################################### ++#elif (D_PROJECT == D_PROJECT__C4) //For Chicago ++//########################################################################################################### ++ #define D_SDMMC1_IP EV_IP_FCIE1 //SDIO ++ #define D_SDMMC1_PORT EV_PORT_SDIO1 ++ #define D_SDMMC1_PAD EV_PAD1 //PAD_SD ++ #define D_SDMMC1_MUTEX EV_MUTEX1 ++ ++ #define D_SDMMC2_IP EV_IP_FCIE2 ++ #define D_SDMMC2_PORT EV_PORT_SDIO1 ++ #define D_SDMMC2_PAD EV_PAD2 //PAD_HSL ++ #define D_SDMMC2_MUTEX EV_MUTEX2 ++ ++ #define D_SDMMC3_IP EV_IP_FCIE3 //SDIO0 ++ #define D_SDMMC3_PORT EV_PORT_SDIO1 //Port Setting ++ #define D_SDMMC3_PAD EV_PAD3 //PAD_SD0 ++ #define D_SDMMC3_MUTEX EV_MUTEX3 //EV_NOMUTEX ++ ++ #define WT_POWERUP 20 //(ms) //Waiting time for Power up ++ #define WT_POWERON 60 //(ms) //Waiting time for Power on ++ #define WT_POWEROFF 20 //(ms) //Waiting time for Power off ++ ++ #define EN_DEV_TREE_SUP (FALSE) ++ ++ #define EN_SDMMC1_CDZIRQ_SHARD (FALSE) ++ #define EN_SDMMC2_CDZIRQ_SHARD (FALSE) ++ #define EN_SDMMC3_CDZIRQ_SHARD (FALSE) ++ #define EN_SDMMC1_CDZIRQ_WAKEUP (FALSE) ++ #define EN_SDMMC2_CDZIRQ_WAKEUP (FALSE) ++ #define EN_SDMMC3_CDZIRQ_WAKEUP (FALSE) ++ #define EV_SDMMC1_DOWN_LVL (FALSE) ++ #define EV_SDMMC2_DOWN_LVL (FALSE) ++ #define EV_SDMMC3_DOWN_LVL (FALSE) ++ ++ #define EV_SDMMC1_SDIO_IRQ (TRUE) ++ #define EV_SDMMC2_SDIO_IRQ (FALSE) ++ #define EV_SDMMC3_SDIO_IRQ (FALSE) ++ #define EV_SDMMC1_SDIO_PRT (FALSE) ++ #define EV_SDMMC2_SDIO_PRT (FALSE) ++ #define EV_SDMMC3_SDIO_PRT (FALSE) ++ ++ #define V_SDMMC1_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC2_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC3_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC1_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ #define V_SDMMC2_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ #define V_SDMMC3_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ ++ #include "../../../mstar/include/chicago/irqs.h" ++ #define V_SDMMC1_MIEIRQ INT_IRQ_SDIO ++ #define V_SDMMC2_MIEIRQ 0 ++ #define V_SDMMC3_MIEIRQ 0 ++ #define V_SDMMC1_CDZIRQ INT_PMU_SD_DETECT ++ #define V_SDMMC2_CDZIRQ 0 ++ #define V_SDMMC3_CDZIRQ 0 ++ ++//########################################################################################################### ++#else //Templete Description ++//########################################################################################################### ++/* ++ #define D_SDMMC1_IP //IP Setting ++ #define D_SDMMC1_PORT //Port Setting ++ #define D_SDMMC1_PAD //PAD from Platform Setting ++ #define D_SDMMC1_MUTEX //Mutex Setting ++ #define D_SDMMC1_HSBUS //Run Which High Bus Mode => EV_BYPS_HS/EV_TSDR_HS/EV_SDR_HS ++ ++ //If we have dual cards, the value of D_SDMMC2_IP must differ from the value of D_SDMMC1_IP. ++ //If we have only single card, D_SDMMC2_IP/D_SDMMC2_PORT/D_SDMMC2_PAD have no meaning, ++ //You could set them the same with D_SDMMC1 series. ++ ++ #define D_SDMMC2_IP ++ #define D_SDMMC2_PORT ++ #define D_SDMMC2_PAD ++ #define D_SDMMC2_MUTEX ++ #define D_SDMMC1_HSBUS ++ ++ #define WT_POWERUP 5 //(ms) //Waiting time for Power up ++ #define WT_POWERON 5 //(ms) //Waiting time for Power on ++ #define WT_POWEROFF 20 //(ms) //Waiting time for Power off ++ ++ #define EN_SDMMC1_CDZIRQ_SHARD (FALSE) ++ #define EN_SDMMC2_CDZIRQ_SHARD (FALSE) ++ #define EN_SDMMC1_CDZIRQ_WAKEUP (TRUE) ++ #define EN_SDMMC2_CDZIRQ_WAKEUP (FALSE) ++ #define EN_SDMMC2_MUTEXSHARE (TRUE) //Share NAND Mutex ++ #define EV_SDMMC1_DOWN_LVL (FALSE) ++ #define EV_SDMMC2_DOWN_LVL (FALSE) ++ ++ #define V_SDMMC1_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC2_MIEIRQ_PARA IRQF_SHARED|IRQF_DISABLED ++ #define V_SDMMC1_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ #define V_SDMMC2_CDZIRQ_PARA IRQ_TYPE_EDGE_BOTH|IRQF_DISABLED ++ ++ #include ++ #define V_SDMMC1_MIEIRQ E_IRQ_SDIO ++ #define V_SDMMC2_MIEIRQ E_IRQ_FCIE ++ #define V_SDMMC1_CDZIRQ 0 ++ #define V_SDMMC2_CDZIRQ 0 ++*/ ++//########################################################################################################### ++#endif ++//########################################################################################################### ++ ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC_CARDNUMS) ++ #define V_SDMMC_SLOTNUMS CONFIG_MSTAR_SDMMC_SLOTNUMS ++#elif defined(CONFIG_MS_SDMMC_CARDNUMS) ++ #define V_SDMMC_SLOTNUMS CONFIG_MS_SDMMC_SLOTNUMS ++#else ++ #define V_SDMMC_SLOTNUMS 1 ++#endif ++ ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC1_IP) ++ #define V_SLOT0_IP CONFIG_MSTAR_SDMMC1_IP ++#elif defined(CONFIG_MS_SDMMC1_IP) ++ #define V_SLOT0_IP CONFIG_MS_SDMMC1_IP ++#else ++ #define V_SLOT0_IP 0 ++#endif ++#if defined(CONFIG_MSTAR_SDMMC2_IP) ++ #define V_SLOT1_IP CONFIG_MSTAR_SDMMC2_IP ++#elif defined(CONFIG_MS_SDMMC2_IP) ++ #define V_SLOT1_IP CONFIG_MS_SDMMC2_IP ++#else ++ #define V_SLOT1_IP 1 ++#endif ++#if defined(CONFIG_MSTAR_SDMMC3_IP) ++ #define V_SLOT2_IP CONFIG_MSTAR_SDMMC3_IP ++#elif defined(CONFIG_MS_SDMMC3_IP) ++ #define V_SLOT2_IP CONFIG_MS_SDMMC3_IP ++#else ++ #define V_SLOT2_IP 2 ++#endif ++ ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC1_PAD) ++ #define V_SLOT0_PAD CONFIG_MSTAR_SDMMC1_PAD ++#elif defined(CONFIG_MS_SDMMC1_PAD) ++ #define V_SLOT0_PAD CONFIG_MS_SDMMC1_PAD ++#else ++ #define V_SLOT0_PAD 0 ++#endif ++#if defined(CONFIG_MSTAR_SDMMC2_PAD) ++ #define V_SLOT1_PAD CONFIG_MSTAR_SDMMC2_PAD ++#elif defined(CONFIG_MS_SDMMC2_IP) ++ #define V_SLOT1_PAD CONFIG_MS_SDMMC2_PAD ++#else ++ #define V_SLOT1_PAD 1 ++#endif ++#if defined(CONFIG_MSTAR_SDMMC3_PAD) ++ #define V_SLOT2_PAD CONFIG_MSTAR_SDMMC3_PAD ++#elif defined(CONFIG_MS_SDMMC3_PAD) ++ #define V_SLOT2_PAD CONFIG_MS_SDMMC3_PAD ++#else ++ #define V_SLOT2_PAD 2 ++#endif ++ ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC_REVCDZ) || defined(CONFIG_MS_SDMMC_REVCDZ) ++ #define EN_SDMMC_CDZREV (TRUE) ++#else ++ #define EN_SDMMC_CDZREV (FALSE) ++#endif ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC_TCARD) || defined(CONFIG_MS_SDMMC_TCARD) ++ #define EN_SDMMC_TCARD (TRUE) ++#else ++ #define EN_SDMMC_TCARD (TRUE) ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC_REVWP) || defined(CONFIG_MS_SDMMC_REVWP) ++ #define EN_SDMMC_WPREV (TRUE) ++#else ++ #define EN_SDMMC_WPREV (FALSE) ++#endif ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC1_MAXCLK) ++ #define V_SDMMC1_MAX_CLK CONFIG_MSTAR_SDMMC1_MAXCLK ++#elif defined(CONFIG_MS_SDMMC1_MAXCLK) ++ #define V_SDMMC1_MAX_CLK CONFIG_MS_SDMMC1_MAXCLK ++#else ++ #define V_SDMMC1_MAX_CLK 400000 ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC1_MAXDLVL) ++ #define V_SDMMC1_MAX_DLVL CONFIG_MSTAR_SDMMC1_MAXDLVL ++#elif defined(CONFIG_MS_SDMMC1_MAXDLVL) ++ #define V_SDMMC1_MAX_DLVL CONFIG_MS_SDMMC1_MAXDLVL ++#else ++ #define V_SDMMC1_MAX_DLVL 0 ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC1_PASSLVL) ++ #define V_SDMMC1_PASS_LVL CONFIG_MSTAR_SDMMC1_PASSLVL ++#elif defined(CONFIG_MS_SDMMC1_PASSLVL) ++ #define V_SDMMC1_PASS_LVL CONFIG_MS_SDMMC1_PASSLVL ++#else ++ #define V_SDMMC1_PASS_LVL 0 ++#endif ++ ++ ++#if defined(CONFIG_MSTAR_SDMMC1_INTCDZ) || defined(CONFIG_MS_SDMMC1_INTCDZ) ++ #define EN_SDMMC1_INTCDZ (TRUE) ++#else ++ #define EN_SDMMC1_INTCDZ (FALSE) ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC1_FAKECDZ) || defined(CONFIG_MS_SDMMC1_FAKECDZ) ++ #define EN_SDMMC1_FAKECDZ (TRUE) ++#else ++ #define EN_SDMMC1_FAKECDZ (FALSE) ++#endif ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC2_MAXCLK) ++ #define V_SDMMC2_MAX_CLK CONFIG_MSTAR_SDMMC2_MAXCLK ++#elif defined(CONFIG_MS_SDMMC2_MAXCLK) ++ #define V_SDMMC2_MAX_CLK CONFIG_MS_SDMMC2_MAXCLK ++#else ++ #define V_SDMMC2_MAX_CLK 400000 ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC2_MAXDLVL) ++ #define V_SDMMC2_MAX_DLVL CONFIG_MSTAR_SDMMC2_MAXDLVL ++#elif defined(CONFIG_MS_SDMMC2_MAXDLVL) ++ #define V_SDMMC2_MAX_DLVL CONFIG_MS_SDMMC2_MAXDLVL ++#else ++ #define V_SDMMC2_MAX_DLVL 0 ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC2_PASSLVL) ++ #define V_SDMMC2_PASS_LVL CONFIG_MSTAR_SDMMC2_PASSLVL ++#elif defined(CONFIG_MS_SDMMC2_PASSLVL) ++ #define V_SDMMC2_PASS_LVL CONFIG_MS_SDMMC2_PASSLVL ++#else ++ #define V_SDMMC2_PASS_LVL 0 ++#endif ++ ++ ++ ++#if defined(CONFIG_MSTAR_SDMMC2_INTCDZ) || defined(CONFIG_MS_SDMMC2_INTCDZ) ++ #define EN_SDMMC2_INTCDZ (TRUE) ++#else ++ #define EN_SDMMC2_INTCDZ (FALSE) ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC2_FAKECDZ) || defined(CONFIG_MS_SDMMC2_FAKECDZ) ++ #define EN_SDMMC2_FAKECDZ (TRUE) ++#else ++ #define EN_SDMMC2_FAKECDZ (FALSE) ++#endif ++//------------------------------------------------------------------------------------------------ ++#if defined(CONFIG_MSTAR_SDMMC3_MAXCLK) ++ #define V_SDMMC3_MAX_CLK CONFIG_MSTAR_SDMMC3_MAXCLK ++#elif defined(CONFIG_MS_SDMMC3_MAXCLK) ++ #define V_SDMMC3_MAX_CLK CONFIG_MS_SDMMC3_MAXCLK ++#else ++ #define V_SDMMC3_MAX_CLK 400000 ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC3_MAXDLVL) ++ #define V_SDMMC3_MAX_DLVL CONFIG_MSTAR_SDMMC3_MAXDLVL ++#elif defined(CONFIG_MS_SDMMC3_MAXDLVL) ++ #define V_SDMMC3_MAX_DLVL CONFIG_MS_SDMMC3_MAXDLVL ++#else ++ #define V_SDMMC3_MAX_DLVL 0 ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC3_PASSLVL) ++ #define V_SDMMC3_PASS_LVL CONFIG_MSTAR_SDMMC3_PASSLVL ++#elif defined(CONFIG_MS_SDMMC3_PASSLVL) ++ #define V_SDMMC3_PASS_LVL CONFIG_MS_SDMMC3_PASSLVL ++#else ++ #define V_SDMMC3_PASS_LVL 0 ++#endif ++ ++ ++ ++#if defined(CONFIG_MSTAR_SDMMC3_INTCDZ) || defined(CONFIG_MS_SDMMC3_INTCDZ) ++ #define EN_SDMMC3_INTCDZ (TRUE) ++#else ++ #define EN_SDMMC3_INTCDZ (FALSE) ++#endif ++ ++#if defined(CONFIG_MSTAR_SDMMC3_FAKECDZ) || defined(CONFIG_MS_SDMMC3_FAKECDZ) ++ #define EN_SDMMC3_FAKECDZ (TRUE) ++#else ++ #define EN_SDMMC3_FAKECDZ (FALSE) ++#endif ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++typedef enum ++{ ++ EV_SDMMC1 = 0, ++ EV_SDMMC2 = 1, ++ EV_SDMMC3 = 2, ++ ++} SlotEmType; ++ ++typedef enum ++{ ++ EV_MUTEX1 = 0, ++ EV_MUTEX2 = 1, ++ EV_MUTEXS = 2, ++ EV_MUTEX3 = 3, ++ EV_NOMUTEX = 4, ++ ++} MutexEmType; ++ ++struct ms_sdmmc_host ++{ ++ struct platform_device *pdev; ++ struct ms_sdmmc_slot *sdmmc_slot[3]; ++}; ++ ++struct ms_sdmmc_slot ++{ ++ struct mmc_host *mmc; ++ ++ unsigned int slotNo; //Slot No. ++ unsigned int mieIRQNo; //MIE IRQ No. ++ unsigned int cdzIRQNo; //CDZ IRQ No. ++ unsigned int cdzGPIONo; //CDZ GPIO No. ++ unsigned int pwrGPIONo; //PWR GPIO No. ++ unsigned int pmrsaveClk; //Power Saving Clock ++ ++ unsigned int initFlag; //First Time Init Flag ++ unsigned int sdioFlag; //SDIO Device Flag ++ ++ unsigned int currClk; //Current Clock ++ unsigned int currRealClk; //Current Real Clock ++ unsigned char currWidth; //Current Bus Width ++ unsigned char currTiming; //Current Bus Timning ++ unsigned char currPowrMode; //Current PowerMode ++ unsigned char currBusMode; //Current Bus Mode ++ unsigned short currVdd; //Current Vdd ++ unsigned char currDDR; //Current DDR ++ unsigned char currDownLevel; //Current Down Level ++ unsigned char currTimeoutCnt; //Current Timeout Count ++ ++ int read_only; //WP ++ int card_det; //Card Detect ++ ++ /****** DMA buffer used for transmitting *******/ ++ u32 *dma_buffer; ++ dma_addr_t dma_phy_addr; ++ ++ /****** ADMA buffer used for transmitting *******/ ++ u32 *adma_buffer; ++ dma_addr_t adma_phy_addr; ++ ++ /***** Tasklet for hotplug ******/ ++ struct tasklet_struct hotplug_tasklet; ++ ++}; /* struct ms_sdmmc_hot*/ ++ ++ ++#endif // End of __MS_SDMMC_LNX_H ++ +diff --git a/drivers/mstar/sdmmc/ms_sdmmc_lnx.c b/drivers/mstar/sdmmc/ms_sdmmc_lnx.c +new file mode 100644 +index 00000000..b474ce87 +--- /dev/null ++++ b/drivers/mstar/sdmmc/ms_sdmmc_lnx.c +@@ -0,0 +1,2166 @@ ++/*************************************************************************************************************** ++ * ++ * FileName ms_sdmmc_lnx.c ++ * @author jeremy.wang (2012/01/10) ++ * Desc: ++ * This layer between Linux SD Driver layer and IP Hal layer. ++ * (1) The goal is we don't need to change any Linux SD Driver code, but we can handle here. ++ * (2) You could define Function/Ver option for using, but don't add Project option here. ++ * (3) You could use function option by Project option, but please add to ms_sdmmc.h ++ * ++ ***************************************************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "inc/ms_sdmmc_lnx.h" ++#include "inc/hal_card_platform.h" ++ ++//########################################################################################################### ++#if (D_FCIE_M_VER == D_FCIE_M_VER__04) ++//########################################################################################################### ++#include "inc/hal_sdmmc.h" ++#include "inc/hal_card_intr.h" ++//########################################################################################################### ++#elif (D_FCIE_M_VER == D_FCIE_M_VER__05) ++//########################################################################################################### ++#include "inc/hal_sdmmc_v5.h" ++#include "inc/hal_card_intr_v5.h" ++//########################################################################################################### ++#endif ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++#include ++#include ++#include ++#include ++#endif ++ ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++#define EN_SDMMC_TRFUNC (FALSE) ++#define EN_SDMMC_TRSDIO (FALSE) ++#define EN_SDMMC_MIEINT_MODE (TRUE) ++#define EN_SDMMC_BRO_DMA (TRUE) ++#define EN_SDMMC_ADV_DMA (TRUE) ++#define EN_SDMMC_DCACHE_FLUSH (TRUE) ++ ++#define EN_SDMMC_POLLING_CDZ (FALSE) ++#define EN_SDMMC_CHG_PWR_PIN (FALSE) ++#define EN_SDMMC_NOCDZ_NDERR (FALSE) ++ ++/****** For Allocation buffer *******/ ++#define MAX_BLK_SIZE 512 //Maximum Transfer Block Size ++#define MAX_BLK_COUNT 1024 //Maximum Transfer Block Count ++#define MAX_SEG_CNT 128 ++ ++/****** For broken DMA *******/ ++#define MAX_BRO_BLK_COUNT 1024 //Maximum Broken DMA Transfer Block Count ++ ++/****** For SD Debounce Setting *******/ ++#define WT_DB_PLUG 30 //Waiting time for Insert Debounce ++#define WT_DB_UNPLUG 30 //Waiting time for Unplug Debounce ++#define WT_DB_SW_PLUG 300 //Waiting time for Plug Delay Process ++#define WT_DB_SW_UNPLUG 0 //Waiting time for Uplug Delay Process ++ ++//*********************************************************************************************************** ++ ++// Const Variable for Dynanmic Setting ++//----------------------------------------------------------------------------------------------------------- ++ ++static const IPEmType ge_IPSet[3] = {D_IP1_IP, D_IP2_IP, D_IP3_IP}; ++static const PortEmType ge_PORTSet[3] = {D_IP1_PORT, D_IP2_PORT, D_IP3_PORT}; ++static const U16_T gu16_MieIntNoSet[3] = {V_IP1_MIEIRQ, V_IP2_MIEIRQ, V_IP3_MIEIRQ}; ++ ++static const PADEmType ge_PADSet[3] = {EV_PAD1, EV_PAD2, EV_PAD3}; ++static const U16_T gu16_CdzIntNoSet[3] = {V_PAD1_CDZIRQ, V_PAD2_CDZIRQ, V_PAD3_CDZIRQ}; ++ ++static const BOOL_T gb_ShareCDZIRQSet[3] = {EN_PAD1_CDZIRQ_SHARD, EN_PAD2_CDZIRQ_SHARD, EN_PAD3_CDZIRQ_SHARD}; ++static const BOOL_T gb_WakeupCDZIRQSet[3] = {EN_PAD1_CDZIRQ_WAKEUP, EN_PAD2_CDZIRQ_WAKEUP, EN_PAD3_CDZIRQ_WAKEUP}; ++static const U32_T gu32_CDZIRQParaSet[3] = {V_PAD1_CDZIRQ_PARA, V_PAD2_CDZIRQ_PARA, V_PAD3_CDZIRQ_PARA}; ++ ++// Global Variable for Each Slot ++//----------------------------------------------------------------------------------------------------------- ++static U8_T gu8_IPOrderSlot[3] = {V_SLOT0_IP, V_SLOT1_IP, V_SLOT2_IP}; ++static U8_T gu8_PADOrderSlot[3] = {V_SLOT0_PAD, V_SLOT1_PAD, V_SLOT2_PAD}; ++ ++static IPEmType ge_IPSlot[3] = {D_IP1_IP, D_IP2_IP, D_IP3_IP}; ++static PortEmType ge_PORTSlot[3] = {D_IP1_PORT, D_IP2_PORT, D_IP3_PORT}; ++static U16_T gu16_MieIntNoSlot[3] = {V_IP1_MIEIRQ, V_IP2_MIEIRQ, V_IP3_MIEIRQ}; ++ ++static PADEmType ge_PADSlot[3] = {EV_PAD1, EV_PAD2, EV_PAD3}; ++static U16_T gu16_CdzIntNoSlot[3] = {V_PAD1_CDZIRQ, V_PAD2_CDZIRQ, V_PAD3_CDZIRQ}; ++ ++static BOOL_T gb_ShareCDZIRQSlot[3] = {EN_PAD1_CDZIRQ_SHARD, EN_PAD2_CDZIRQ_SHARD, EN_PAD3_CDZIRQ_SHARD}; ++static BOOL_T gb_WakeupCDZIRQSlot[3] = {EN_PAD1_CDZIRQ_WAKEUP, EN_PAD2_CDZIRQ_WAKEUP, EN_PAD3_CDZIRQ_WAKEUP}; ++static U32_T gu32_CDZIRQParaSlot[3] = {V_PAD1_CDZIRQ_PARA, V_PAD2_CDZIRQ_PARA, V_PAD3_CDZIRQ_PARA}; ++ ++static MutexEmType ge_MutexSlot[3] = {D_SDMMC1_MUTEX, D_SDMMC2_MUTEX, D_SDMMC3_MUTEX}; ++ ++static U32_T gu32_MaxDLVLSlot[3] = {V_SDMMC1_MAX_DLVL, V_SDMMC2_MAX_DLVL, V_SDMMC3_MAX_DLVL}; ++static U32_T gu32_PassLVLSlot[3] = {V_SDMMC1_PASS_LVL, V_SDMMC2_PASS_LVL, V_SDMMC3_PASS_LVL}; ++ ++static BOOL_T gb_DownLVLSlot[3] = {EV_SDMMC1_DOWN_LVL, EV_SDMMC2_DOWN_LVL, EV_SDMMC3_DOWN_LVL}; ++static BOOL_T gb_SDIOIRQSlot[3] = {EV_SDMMC1_SDIO_IRQ, EV_SDMMC2_SDIO_IRQ, EV_SDMMC3_SDIO_IRQ}; ++static BOOL_T gb_SDIOPRTSlot[3] = {EV_SDMMC1_SDIO_PRT, EV_SDMMC2_SDIO_PRT, EV_SDMMC3_SDIO_PRT}; ++ ++//Dync DTS Setting ++static U32_T gu32_MaxClkSlot[3] = {V_SDMMC1_MAX_CLK, V_SDMMC2_MAX_CLK, V_SDMMC3_MAX_CLK}; ++static BOOL_T gb_IntCDZSlot[3] = {EN_SDMMC1_INTCDZ, EN_SDMMC2_INTCDZ, EN_SDMMC3_INTCDZ}; ++static BOOL_T gb_FakeCDZSlot[3] = {EN_SDMMC1_FAKECDZ, EN_SDMMC2_FAKECDZ, EN_SDMMC3_FAKECDZ}; ++static U32_T gu32_PwrNoSlot[3] = {V_PAD1_PWRGPIO, V_PAD2_PWRGPIO, V_PAD3_PWRGPIO}; ++ ++ ++ ++static IntSourceStruct gst_IntSourceSlot[3]; ++static spinlock_t g_RegLockSlot[3]; ++ ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++struct clk* gp_clkSlot[3]; ++struct clk* gp_clkMCMSlot[3]; ++struct clk* gp_clkSRAMSlot[3]; ++#endif ++ ++ ++// Global Variable for All Slot: ++//----------------------------------------------------------------------------------------------------------- ++static BOOL_T gb_ReverseCDZ = EN_SDMMC_CDZREV; ++static U8_T gu8_SlotNums = V_SDMMC_SLOTNUMS; ++ ++static volatile BOOL_T gb_RejectSuspend = (FALSE); ++static volatile BOOL_T gb_AlwaysSwitchPAD = (FALSE); ++ ++extern struct mutex FCIE3_mutex; // use fcie mutex in other driver ++DEFINE_MUTEX(sdmmc1_mutex); ++DEFINE_MUTEX(sdmmc2_mutex); ++DEFINE_MUTEX(sdmmc3_mutex); ++ ++ ++#define L3_FLUSH_PIPE() Chip_Flush_MIU_Pipe() ++ ++ ++// String Name ++//----------------------------------------------------------------------------------------------------------- ++#define DRIVER_NAME "ms_sdmmc" ++#define DRIVER_DESC "Mstar SD/MMC Card Interface driver" ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_SDMMC_TRFUNC) ++ #define pr_sd_err(fmt, arg...) // ++ #define pr_sd_main(fmt, arg...) printk(fmt, ##arg) ++ #define pr_sd_dbg(fmt, arg...) //printk(fmt, ##arg) ++#else ++ #define pr_sd_err(fmt, arg...) printk(fmt, ##arg) ++ #define pr_sd_main(fmt, arg...) // ++ #define pr_sd_dbg(fmt, arg...) // ++#endif ++ ++#if (EN_SDMMC_TRSDIO) ++ #define pr_sdio_main(fmt, arg...) printk(fmt, ##arg) ++#else ++ #define pr_sdio_main(fmt, arg...) ++#endif ++ ++ ++// Section Process Begin ++//------------------------------------------------------------------------------------------------ ++static void _CRIT_SECT_BEGIN(SlotEmType eSlot) ++{ ++ MutexEmType eMutex = ge_MutexSlot[eSlot]; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ if(eMutex == EV_MUTEX1) ++ mutex_lock(&sdmmc1_mutex); ++ //else if(eMutex == EV_MUTEXS) ++ //mutex_lock(&FCIE3_mutex); ++ else if(eMutex == EV_MUTEX2) ++ mutex_lock(&sdmmc2_mutex); ++ else if(eMutex == EV_MUTEX3) ++ mutex_lock(&sdmmc3_mutex); ++ ++ Hal_CARD_IPBeginSetting(eIP); ++ ++} ++ ++ ++// Section Process End ++//------------------------------------------------------------------------------------------------ ++static void _CRIT_SECT_END(SlotEmType eSlot) ++{ ++ MutexEmType eMutex = ge_MutexSlot[eSlot]; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ Hal_CARD_IPEndSetting(eIP); ++ ++ if(eMutex == EV_MUTEX1) ++ mutex_unlock(&sdmmc1_mutex); ++ //else if(eMutex == EV_MUTEXS) ++ //mutex_unlock(&FCIE3_mutex); ++ else if(eMutex == EV_MUTEX2) ++ mutex_unlock(&sdmmc2_mutex); ++ else if(eMutex == EV_MUTEX3) ++ mutex_unlock(&sdmmc3_mutex); ++ ++} ++ ++ ++// ++//----------------------------------------------------------------------------------------------------------- ++#if (D_FCIE_M_VER == D_FCIE_M_VER__04) ++static void _CRIT_SetMIEIntEn_ForV4(SlotEmType eSlot, TransEmType eTransType) ++{ ++ unsigned long flags; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ spin_lock_irqsave(&g_RegLockSlot[eSlot], flags); ++ ++ Hal_SDMMC_SetMIEIntEn_ForV4(eIP, eTransType); ++ ++ spin_unlock_irqrestore(&g_RegLockSlot[eSlot], flags); ++ ++} ++#else ++#define _CRIT_SetMIEIntEn_ForV4(Slot, TransType) //Null for FCIE5... ++#endif ++ ++ ++// Dynamic IP PAD Mapping ++//------------------------------------------------------------------------------------------------ ++static void _Dyn_IP_PAD_Mappingg(SlotEmType eSlot) ++{ ++ ++ U8_T u8IP_idx = gu8_IPOrderSlot[eSlot]; ++ U8_T u8PAD_idx = gu8_PADOrderSlot[eSlot]; ++ ++ ge_IPSlot[eSlot] = ge_IPSet[u8IP_idx]; ++ ge_PORTSlot[eSlot] = ge_PORTSet[u8IP_idx]; ++ gu16_MieIntNoSlot[eSlot] = gu16_MieIntNoSet[u8IP_idx]; ++ ++ ge_PADSlot[eSlot] = ge_PADSet[u8PAD_idx]; ++ gu16_CdzIntNoSlot[eSlot] = gu16_CdzIntNoSet[u8PAD_idx]; ++ ++ gb_ShareCDZIRQSlot[eSlot] = gb_ShareCDZIRQSet[u8PAD_idx]; ++ gb_WakeupCDZIRQSlot[eSlot] = gb_WakeupCDZIRQSet[u8PAD_idx]; ++ gu32_CDZIRQParaSlot[eSlot] = gu32_CDZIRQParaSet[u8PAD_idx]; ++ ++} ++ ++ ++ ++// Switch PAD ++//------------------------------------------------------------------------------------------------ ++static void _SwitchPAD(SlotEmType eSlot) ++{ ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ PortEmType ePort = ge_PORTSlot[eSlot]; ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ ++ Hal_CARD_SetPADToPortPath(eIP, ePort, ePAD, FALSE); ++ Hal_CARD_InitPADPin(ePAD, FALSE); ++ ++} ++ ++ ++// Set Bus Voltage ++//------------------------------------------------------------------------------------------------ ++static void _SetBusVdd(SlotEmType eSlot, U8_T u8Vdd) ++{ ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ ++ /****** Simple Setting Here ******/ ++ Hal_CARD_SetPADPower(ePAD, (PADVddEmType)u8Vdd); ++ ++} ++ ++ ++// Set Power ++//------------------------------------------------------------------------------------------------ ++static void _SetPower(SlotEmType eSlot, U8_T u8PowerMode) ++{ ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ ++ if(u8PowerMode == MMC_POWER_OFF) // Power Off ++ { ++ Hal_SDMMC_ClkCtrl(eIP, FALSE, 0); ++ Hal_CARD_PullPADPin(ePAD, EV_PULLDOWN, FALSE); ++ ++ if(EN_SDMMC_CHG_PWR_PIN) ++ { ++ if(gu32_PwrNoSlot[eSlot]>0) ++ { ++ gpio_direction_output(gu32_PwrNoSlot[eSlot], 1); // GPIO Power Off ++ msleep(WT_POWEROFF); ++ } ++ } ++ else ++ { ++ Hal_CARD_PowerOff(ePAD, WT_POWEROFF); //For SD PAD ++ } ++ ++ } ++ else if(u8PowerMode == MMC_POWER_UP) // Power Up ++ { ++ Hal_CARD_PullPADPin(ePAD, EV_PULLUP, FALSE); ++ ++ if(EN_SDMMC_CHG_PWR_PIN) ++ { ++ if(gu32_PwrNoSlot[eSlot]>0) ++ { ++ gpio_direction_output(gu32_PwrNoSlot[eSlot], 0); // GPIO Power Off ++ msleep(WT_POWERUP); ++ } ++ } ++ else ++ { ++ Hal_CARD_PowerOn(ePAD, WT_POWERUP); ++ } ++ ++ ++ ++ } ++ else if(u8PowerMode == MMC_POWER_ON) // Power On ++ { ++ Hal_SDMMC_ClkCtrl(eIP, TRUE, WT_POWERON); ++ Hal_SDMMC_Reset(eIP); ++ } ++ ++} ++ ++ ++//------------------------------------------------------------------------------------------------ ++static U32_T _SetClock(SlotEmType eSlot, unsigned int u32ReffClk, U8_T u8PassLevel, U8_T u8DownLevel) ++{ ++ U32_T u32RealClk =0 ; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ if(u32ReffClk) ++ { ++ u32RealClk = Hal_CARD_FindClockSetting(eIP, (U32_T)u32ReffClk, u8PassLevel, u8DownLevel); ++ ++ #if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ clk_set_rate(gp_clkSlot[eSlot], u32RealClk); ++ #else ++ Hal_CARD_SetClock(eIP, u32RealClk); ++ #endif ++ ++ Hal_SDMMC_SetNrcDelay(eIP, u32RealClk); ++ } ++ ++ return u32RealClk; ++} ++ ++ ++//------------------------------------------------------------------------------------------------ ++static void _SetBusWidth(SlotEmType eSlot, U8_T u8BusWidth) ++{ ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ switch(u8BusWidth) ++ { ++ case MMC_BUS_WIDTH_1: ++ Hal_SDMMC_SetDataWidth(eIP, EV_BUS_1BIT); ++ break; ++ case MMC_BUS_WIDTH_4: ++ Hal_SDMMC_SetDataWidth(eIP, EV_BUS_4BITS); ++ break; ++ case MMC_BUS_WIDTH_8: ++ Hal_SDMMC_SetDataWidth(eIP, EV_BUS_8BITS); ++ break; ++ } ++} ++ ++ ++//------------------------------------------------------------------------------------------------ ++static void _SetBusTiming(SlotEmType eSlot, U8_T u8BusTiming) ++{ ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ switch(u8BusTiming) ++ { ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) ++ case MMC_TIMING_UHS_SDR12: ++#endif ++ case MMC_TIMING_LEGACY: ++ /****** For Default Speed ******/ ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_DEF); ++ Hal_CARD_SetBusTiming(eIP, EV_BUS_DEF); ++ break; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 8, 0)) ++ case MMC_TIMING_UHS_SDR25: ++#endif ++ case MMC_TIMING_SD_HS: ++ case MMC_TIMING_MMC_HS: ++ case MMC_TIMING_UHS_SDR50: ++ case MMC_TIMING_UHS_SDR104: ++ case MMC_TIMING_MMC_HS200: ++ /****** For High Speed ******/ ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_HS); ++ Hal_CARD_SetBusTiming(eIP, EV_BUS_HS); ++ break; ++ ++ case MMC_TIMING_UHS_DDR50: ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_DDR50); ++ Hal_CARD_SetBusTiming(eIP, EV_BUS_DDR50); ++ break; ++ ++ default: ++ /****** For 300KHz IP Issue but not for Default Speed ******/ ++ Hal_SDMMC_SetBusTiming(eIP, EV_BUS_LOW); ++ Hal_CARD_SetBusTiming(eIP, EV_BUS_LOW); ++ break; ++ } ++ ++ ++} ++ ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _GetCardDetect(SlotEmType eSlot) ++{ ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ ++ if(gb_FakeCDZSlot[eSlot]) ++ { ++ return (TRUE); ++ } ++ else ++ { ++ ++ if(gb_ReverseCDZ) ++ return !Hal_CARD_GetGPIOState((GPIOEmType)eSlot, ePAD); ++ else ++ return Hal_CARD_GetGPIOState((GPIOEmType)eSlot, ePAD); ++ ++ } ++ ++ return (FALSE); ++} ++ ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _GetWriteProtect(SlotEmType eSlot) ++{ ++ ++#if(EN_SDMMC_TCARD) ++ return (FALSE); ++#else ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ #if(EN_SDMMC_WPREV) ++ return !Hal_SDMMC_WriteProtect(eIP); ++ #else ++ return Hal_SDMMC_WriteProtect(eIP); ++ #endif ++ ++#endif ++ ++} ++ ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _CardDetect_PlugDebounce(SlotEmType eSlot, U32_T u32WaitMs, BOOL_T bPrePlugStatus) ++{ ++ BOOL_T bCurrPlugStatus = bPrePlugStatus; ++ U32_T u32DiffTime = 0; ++ ++ while(u32DiffTime < u32WaitMs) ++ { ++ mdelay(1); ++ u32DiffTime++; ++ ++ bCurrPlugStatus = _GetCardDetect(eSlot); ++ ++ if (bPrePlugStatus != bCurrPlugStatus) ++ { ++ /****** Print the Debounce ******/ ++ /*if(bPrePlugStatus) ++ printk("#"); ++ else ++ printk("$");*/ ++ /*********************************/ ++ break; ++ } ++ } ++ return bCurrPlugStatus; ++} ++ ++//------------------------------------------------------------------------------------------------ ++static U16_T _PreDataBufferProcess(TransEmType eTransType, struct mmc_data *data, struct ms_sdmmc_slot *sdmmchost, volatile U32_T *pu32AddrArr) ++{ ++ struct scatterlist *p_sg = 0; ++ U8_T u8Dir = ( (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE ); ++ U16_T u16sg_idx = 0; ++ ++#if (!EN_SDMMC_BRO_DMA) ++ U32_T *pSGbuf = 0; ++ U32_T u32TranBytes = 0; ++ U32_T u32TotalSize = data->blksz * data->blocks; ++ unsigned *pDMAbuf = sdmmchost->dma_buffer; ++ ++#elif (EN_SDMMC_BRO_DMA) && (EN_SDMMC_ADV_DMA) ++ U16_T u16SubBCnt = 0; ++ U32_T u32SubLen = 0; ++ BOOL_T bEnd = (FALSE); ++ unsigned *pADMAbuf = sdmmchost->adma_buffer; ++ ++#endif ++ ++ if(eTransType == EV_CIF) ++ { ++ p_sg = &data->sg[0]; ++ pu32AddrArr[0] = (U32_T)( page_address(sg_page(p_sg)) + p_sg->offset ); ++ return 1; ++ } ++ ++#if (EN_SDMMC_BRO_DMA) ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++#else ++ if(data->sg_len==1) ++#endif ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ p_sg->dma_address = dma_map_page(NULL, sg_page(p_sg), p_sg->offset, p_sg->length, u8Dir); ++ ++ if(dma_mapping_error(NULL, p_sg->dma_address)) //Add to avoid unmap warning! ++ return 0; ++ ++ if((p_sg->dma_address==0) || (p_sg->dma_address==~0)) //Mapping Error! ++ return 0; ++ ++ pu32AddrArr[u16sg_idx] = (U32_T)p_sg->dma_address; ++ } ++ ++#if (EN_SDMMC_BRO_DMA) && (EN_SDMMC_ADV_DMA) ++ ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++ { ++ if( u16sg_idx==((data->sg_len)-1) ) ++ bEnd = (TRUE); ++ ++ u32SubLen = data->sg[u16sg_idx].length; ++ u16SubBCnt = (U16_T)(u32SubLen/data->blksz); ++ Hal_SDMMC_ADMASetting((volatile void *)pADMAbuf, u16sg_idx, u32SubLen, u16SubBCnt, (U32_T)pu32AddrArr[u16sg_idx], 0, bEnd); ++ } ++ ++ L3_FLUSH_PIPE(); //Avoid L3 issue ++ ++ pu32AddrArr[0] = (U32_T) sdmmchost->adma_phy_addr; ++ return 1; ++ ++#elif (EN_SDMMC_BRO_DMA) ++ ++ if(data->flags & MMC_DATA_WRITE) ++ L3_FLUSH_PIPE(); //Avoid L3 issue ++ ++ return (U16_T)data->sg_len; ++ ++#else ++ else ++ { ++ if(data->flags & MMC_DATA_WRITE) //SGbuf => DMA buf ++ { ++ while(u16sg_idx < data->sg_len) ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ ++ pSGbuf = kmap_atomic(sg_page(p_sg), KM_BIO_SRC_IRQ) + p_sg->offset; ++ u32TranBytes = min(u32TotalSize, p_sg->length); ++ memcpy(pDMAbuf, pSGbuf, u32TranBytes); ++ u32TotalSize -= u32TranBytes; ++ pDMAbuf += (u32TranBytes >> 2) ; ++ kunmap_atomic(pSGbuf, KM_BIO_SRC_IRQ); ++ ++ u16sg_idx++; ++ } ++ ++ L3_FLUSH_PIPE(); //Avoid L3 issue ++ ++ } ++ ++ pu32AddrArr[0] = (U32_T) sdmmchost->dma_phy_addr; ++ ++ } ++ ++ return 1; ++ ++#endif ++ ++} ++//------------------------------------------------------------------------------------------------ ++static void _PostDataBufferProcess(TransEmType eTransType, struct mmc_data *data, struct ms_sdmmc_slot *sdmmchost) ++{ ++ struct scatterlist *p_sg = 0; ++ U8_T u8Dir = ( (data->flags & MMC_DATA_READ) ? DMA_FROM_DEVICE : DMA_TO_DEVICE ); ++ U16_T u16sg_idx = 0; ++ ++#if (!EN_SDMMC_BRO_DMA) ++ U32_T *pSGbuf = 0; ++ U32_T u32TranBytes = 0; ++ U32_T u32TotalSize = data->blksz * data->blocks; ++ unsigned *pDMAbuf = sdmmchost->dma_buffer; ++#endif ++ ++ if(eTransType == EV_CIF) ++ return; ++ ++ ++#if (EN_SDMMC_BRO_DMA) ++ ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ dma_unmap_page(NULL, p_sg->dma_address, p_sg->length, u8Dir); ++ if ( (u8Dir==DMA_FROM_DEVICE) && EN_SDMMC_DCACHE_FLUSH && (sg_page(p_sg) != NULL) && !PageSlab(sg_page(p_sg)) ) ++ flush_dcache_page(sg_page(p_sg)); ++ } ++ ++#else ++ ++ if(data->sg_len==1) ++ { ++ p_sg = &data->sg[0]; ++ dma_unmap_page(NULL, p_sg->dma_address, p_sg->length, u8Dir); ++ if ( (u8Dir==DMA_FROM_DEVICE) && EN_SDMMC_DCACHE_FLUSH && (sg_page(p_sg) != NULL) && !PageSlab(sg_page(p_sg)) ) ++ flush_dcache_page(sg_page(p_sg)); ++ } ++ else ++ { ++ if(data->flags & MMC_DATA_READ) //SGbuf => DMA buf ++ { ++ for(u16sg_idx=0 ; u16sg_idx< data->sg_len ; u16sg_idx++) ++ { ++ p_sg = &data->sg[u16sg_idx]; ++ ++ pSGbuf = kmap_atomic(sg_page(p_sg), KM_BIO_SRC_IRQ) + p_sg->offset; ++ u32TranBytes = min(u32TotalSize, p_sg->length); ++ memcpy(pSGbuf, pDMAbuf, u32TranBytes); ++ u32TotalSize -= u32TranBytes; ++ pDMAbuf += (u32TranBytes >> 2) ; ++ ++ flush_dcache_page(sg_page(p_sg)); ++ kunmap_atomic(pSGbuf, KM_BIO_SRC_IRQ); ++ } ++ ++ //Avoid L3 issue ++ L3_FLUSH_PIPE(); ++ ++ } ++ } ++ ++#endif ++ ++} ++ ++//------------------------------------------------------------------------------------------------ ++static U32_T _TransArrToUInt(U8_T u8Sep1, U8_T u8Sep2, U8_T u8Sep3, U8_T u8Sep4) ++{ ++ return ((((uint)u8Sep1)<<24) | (((uint)u8Sep2)<<16) | (((uint)u8Sep3)<<8) | ((uint)u8Sep4)); ++} ++//------------------------------------------------------------------------------------------------ ++static SDMMCRspEmType _TransRspType(unsigned int u32Rsp) ++{ ++ ++ switch(u32Rsp) ++ { ++ case MMC_RSP_NONE: ++ return EV_NO; ++ case MMC_RSP_R1: ++ //case MMC_RSP_R5: ++ //case MMC_RSP_R6: ++ //case MMC_RSP_R7: ++ return EV_R1; ++ case MMC_RSP_R1B: ++ return EV_R1B; ++ case MMC_RSP_R2: ++ return EV_R2; ++ case MMC_RSP_R3: ++ //case MMC_RSP_R4: ++ return EV_R3; ++ default: ++ return EV_R1; ++ } ++ ++} ++//------------------------------------------------------------------------------------------------ ++static BOOL_T _PassPrintCMD(SlotEmType eSlot, U8_T u32Cmd, U32_T u32Arg, BOOL_T bSDIODev) ++{ ++ ++ if( (u32Cmd == SD_IO_RW_DIRECT) && bSDIODev) ++ return (FALSE); ++ ++ ++ if(gb_SDIOPRTSlot[eSlot]) //SDIO Use ++ { ++ if(u32Cmd == SD_SEND_IF_COND) ++ { ++ return (TRUE); ++ } ++ else if(u32Cmd == SD_IO_RW_DIRECT) ++ { ++ if( (u32Arg == 0x00000C00) || (u32Arg == 0x80000C08)) ++ return (TRUE); ++ } ++ return (FALSE); ++ } ++ ++ // SD Use ++ switch(u32Cmd) ++ { ++ case MMC_SEND_OP_COND: //MMC =>Cmd_1 ++ case SD_IO_SEND_OP_COND: //SDIO =>Cmd_5 ++ case SD_SEND_IF_COND: //SD =>Cmd_8 ++ case SD_IO_RW_DIRECT: //SDIO =>Cmd_52 ++ case MMC_SEND_STATUS: //SD =>CMD13 ++ case MMC_APP_CMD: //SD =>Cmd55 ++ return (TRUE); ++ break; ++ ++ } ++ ++ return (FALSE); ++ ++} ++ ++//------------------------------------------------------------------------------------------------ ++static int _RequestEndProcess(CmdEmType eCmdType, RspErrEmType eErrType, struct ms_sdmmc_slot *p_sdmmc_slot, struct mmc_data *data) ++{ ++ int nErr = 0; ++ BOOL_T bNeedDownLevel = FALSE; ++ ErrGrpEmType eErrGrp; ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ if( eErrType == EV_STS_OK ) ++ { ++ pr_sdio_main("_[%01X]", Hal_SDMMC_GetDATBusLevel(eIP)); ++ pr_sd_main("@\n"); ++ } ++ else ++ { ++ pr_sd_main("=> (Err: 0x%04X)", (U16_T)eErrType); ++ nErr = (U32_T) eErrType; ++ ++ if(eCmdType != EV_CMDRSP) ++ { ++ ++ eErrGrp = Hal_SDMMC_ErrGroup(eErrType); ++ ++ switch((U16_T)eErrGrp) ++ { ++ case EV_EGRP_TOUT: ++ nErr = -ETIMEDOUT; ++ break; ++ ++ case EV_EGRP_COMM: ++ nErr = -EILSEQ; ++ bNeedDownLevel = TRUE; ++ break; ++ } ++ ++ ++ ++ } ++ ++ } ++ ++ /****** (1) SD Re-Detection after timeout******/ ++ if(gb_IntCDZSlot[eSlot] || (!EN_SDMMC_POLLING_CDZ)) ++ { ++ if(eCmdType != EV_CMDRSP) ++ { ++ if( eErrType == EV_STS_OK ) ++ p_sdmmc_slot->currTimeoutCnt = 0; ++ else if(eErrType == EV_STS_MIE_TOUT) ++ p_sdmmc_slot->currTimeoutCnt++; ++ ++ if(p_sdmmc_slot->currTimeoutCnt>=3) ++ { ++ Hal_SDMMC_StopProcessCtrl(eIP, TRUE); ++ mmc_detect_change(p_sdmmc_slot->mmc, msecs_to_jiffies(WT_DB_SW_UNPLUG)); ++ p_sdmmc_slot->currTimeoutCnt =0; ++ printk("\n>> [sdmmc_%u] Auto Re-Dectection.........\n\n", eSlot); ++ } ++ } ++ } ++ ++ if( eErrType == EV_STS_OK ) ++ return nErr; ++ ++ ++ /****** (2) Special Error Process for Stop Wait Process ******/ ++ if(eErrType == EV_SWPROC_ERR && data && EN_SDMMC_NOCDZ_NDERR) ++ { ++ data->bytes_xfered = data->blksz * data->blocks; ++ nErr = 0; ++ pr_sd_main("_Pass"); ++ } ++ ++ pr_sd_main("\n"); ++ ++ /****** (3) Downgrad Clock Speed for Some Bus Errors ******/ ++ if(bNeedDownLevel && gb_DownLVLSlot[eSlot]) ++ { ++ if( (p_sdmmc_slot->currDownLevel+1) <= gu32_MaxDLVLSlot[eSlot]) ++ p_sdmmc_slot->currDownLevel += 1; ++ ++ p_sdmmc_slot->currRealClk = _SetClock(eSlot, p_sdmmc_slot->currClk, gu32_PassLVLSlot[eSlot], p_sdmmc_slot->currDownLevel); ++ printk(">> [sdmmc_%u] Downgrade Clk from (Clk=%u)=> (Real=%u)\n", eSlot, p_sdmmc_slot->currClk, p_sdmmc_slot->currRealClk); ++ } ++ ++ ++ return nErr; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_cdzint ++ * @author jeremy.wang (2012/5/8) ++ * Desc: Int funtion for GPIO Card Detection ++ * ++ * @param irq : ++ * @param p_dev_id : ++ * ++ * @return irqreturn_t : ++ ----------------------------------------------------------------------------------------------------------*/ ++static irqreturn_t ms_sdmmc_cdzint(int irq, void *p_dev_id) ++{ ++ irqreturn_t irq_t = IRQ_NONE; ++ IntSourceStruct* pstIntSource = p_dev_id; ++ SlotEmType eSlot = (SlotEmType)pstIntSource->slotNo; ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ struct ms_sdmmc_slot *p_sdmmc_slot = pstIntSource->p_data; ++ ++ if(!gb_ShareCDZIRQSlot[eSlot]) ++ disable_irq_nosync(irq); ++ ++ if(Hal_CARD_GPIOIntFilter((GPIOEmType)eSlot, ePAD)) ++ { ++ tasklet_schedule(&p_sdmmc_slot->hotplug_tasklet); ++ irq_t = IRQ_HANDLED; ++ } ++ ++ return irq_t; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_hotplug ++ * @author jeremy.wang (2012/1/5) ++ * Desc: Hotplug function for Card Detection ++ * ++ * @param data : ms_sdmmc_slot struct pointer ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_hotplug(unsigned long data) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = (struct ms_sdmmc_slot *) data; ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ GPIOOptEmType eINSOPT = EV_GPIO_OPT3; ++ GPIOOptEmType eEJTOPT = EV_GPIO_OPT4; ++ ++ ++ if (gb_ReverseCDZ) ++ { ++ eINSOPT = EV_GPIO_OPT4; ++ eEJTOPT = EV_GPIO_OPT3; ++ } ++ ++ ++ printk("\n>> [sdmmc_%u] CDZ... ", eSlot); ++ ++LABEL_LOOP_HOTPLUG: ++ ++ if( _GetCardDetect(eSlot) ) // Insert (CDZ) ++ { ++ if( (FALSE) == _CardDetect_PlugDebounce(eSlot, WT_DB_PLUG, TRUE) ) ++ goto LABEL_LOOP_HOTPLUG; ++ ++ mmc_detect_change(p_sdmmc_slot->mmc, msecs_to_jiffies(WT_DB_SW_PLUG)); ++ printk("(INS) OK!\n"); ++ ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)eSlot, ePAD, EV_GPIO_OPT1); ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)eSlot, ePAD, eINSOPT); ++ ++ ++ } ++ else // Remove (CDZ) ++ { ++ if( (TRUE) == _CardDetect_PlugDebounce(eSlot, WT_DB_UNPLUG, FALSE) ) ++ goto LABEL_LOOP_HOTPLUG; ++ ++ if (p_sdmmc_slot->mmc->card) ++ mmc_card_set_removed(p_sdmmc_slot->mmc->card); ++ ++ Hal_SDMMC_StopProcessCtrl(eIP, TRUE); ++ mmc_detect_change(p_sdmmc_slot->mmc, msecs_to_jiffies(WT_DB_SW_UNPLUG)); ++ printk("(EJT) OK!\n"); ++ ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)eSlot, ePAD, EV_GPIO_OPT1); ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)eSlot, ePAD, eEJTOPT); ++ ++ } ++ ++ if(!gb_ShareCDZIRQSlot[eSlot]) ++ enable_irq(p_sdmmc_slot->cdzIRQNo); ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_enable ++ * @author jeremy.wang (2012/3/21) ++ * Desc: Something we want to do before Host Enable ++ * ++ * @param p_mmc_host : ++ * ++ * @return int : 0 = Success, >0 = Error ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_enable(struct mmc_host *p_mmc_host) ++{ ++ gb_RejectSuspend = TRUE; ++ return 0; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_disable ++ * @author jeremy.wang (2012/3/21) ++ * Desc: Something we want to do before Host Disable ++ * ++ * @param p_mmc_host : ++ * @param lazy : msec for delay work ++ * ++ * @return int : 0 = No Delay, <0 = Error, >0 = Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) ++static int ms_sdmmc_disable(struct mmc_host *p_mmc_host, int lazy) ++{ ++ gb_RejectSuspend = FALSE; ++ return lazy; ++} ++#else ++static int ms_sdmmc_disable(struct mmc_host *p_mmc_host) ++{ ++ gb_RejectSuspend = FALSE; ++ return 0; ++} ++#endif ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_request ++ * @author jeremy.wang (2011/5/19) ++ * Desc: Request funciton for any commmand ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * @param p_mmc_req : mmc_request structure pointer ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_request(struct mmc_host *p_mmc_host, struct mmc_request *p_mmc_req) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ struct mmc_command *cmd = p_mmc_req->cmd; ++ struct mmc_command *stop = p_mmc_req->stop; ++ struct mmc_data *data = p_mmc_req->data; ++ ++ RspStruct * eRspSt; ++ RspErrEmType eErr = EV_STS_OK; ++ CmdEmType eCmdType = EV_CMDRSP; ++ TransEmType eTransType = ((EN_SDMMC_ADV_DMA) && (EN_SDMMC_BRO_DMA) ? EV_ADMA : EV_DMA ); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ volatile U32_T au32Addr[MAX_SEG_CNT]; ++ ++ BOOL_T bCloseClock = FALSE; ++ U8_T u8CMD = 0; ++ U16_T u16BlkSize = 0, u16BlkCnt = 0, u16SubBlkCnt = 0; ++ U16_T u16ProcCnt = 0, u16Idx= 0; ++ U32_T u32Arg = 0, u32SubLen = 0; ++ ++ ++ _CRIT_SECT_BEGIN(eSlot); ++ ++ u8CMD =(U8_T)cmd->opcode; ++ u32Arg = (U32_T)cmd->arg; ++ ++ if(Hal_SDMMC_OtherPreUse(eIP) || gb_AlwaysSwitchPAD) ++ _SwitchPAD(eSlot); ++ ++ if(!p_sdmmc_slot->mmc->card) ++ Hal_SDMMC_StopProcessCtrl(eIP, FALSE); ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ clk_set_rate(gp_clkSlot[eSlot], p_sdmmc_slot->currRealClk); ++#else ++ Hal_CARD_SetClock(eIP, p_sdmmc_slot->currRealClk); ++#endif ++ ++ pr_sdio_main("_[%01X]_", Hal_SDMMC_GetDATBusLevel(eIP)); ++ pr_sd_main(">> [sdmmc_%u] CMD_%u (0x%08X)", eSlot, u8CMD, u32Arg); ++ ++ /***** Specail Case for FCIE4 SDIO ******/ ++ _CRIT_SetMIEIntEn_ForV4(eSlot, (!data ? EV_EMP : EV_DMA)); ++ ++ Hal_SDMMC_SetCmdToken(eIP, u8CMD, u32Arg); ++ /****** Simple SD command *******/ ++ if(!data) ++ { ++ Hal_SDMMC_SetSDIOIntBeginSetting(eIP, u8CMD, u32Arg, EV_CMDRSP, 0); ++ eErr = Hal_SDMMC_SendCmdAndWaitProcess(eIP, EV_EMP, EV_CMDRSP, _TransRspType(mmc_resp_type(cmd)), TRUE); ++ Hal_SDMMC_SetSDIOIntEndSetting(eIP, eErr, 0); ++ } ++ else // R/W SD Command ++ { ++ u16BlkSize = (U16_T)data->blksz; ++ u16BlkCnt = (U16_T)data->blocks; ++ u32SubLen = (U32_T) data->sg[0].length; ++ u16SubBlkCnt = (U16_T)(u32SubLen/u16BlkSize); ++ ++ eCmdType = ( (data->flags & MMC_DATA_READ) ? EV_CMDREAD : EV_CMDWRITE ); ++ bCloseClock = ( (stop) ? FALSE : TRUE ); ++ ++ pr_sd_main("__[Sgl: %u] (TB: %u)(BSz: %u)", (U16_T)data->sg_len, u16BlkCnt, u16BlkSize); ++ ++ u16ProcCnt = _PreDataBufferProcess(eTransType, data, p_sdmmc_slot, au32Addr); ++ if(u16ProcCnt==0) ++ { ++ pr_err("\n>> [sdmmc_%u] Err: DMA Mapping Addr Error!\n", eSlot); ++ eErr = EV_OTHER_ERR; ++ goto LABEL_SD_ERR; ++ } ++ else if(u16ProcCnt==1) ++ { ++ u32SubLen = u16BlkSize * u16BlkCnt; ++ u16SubBlkCnt = u16BlkCnt; ++ } ++ ++ pr_sd_dbg("\n____[0] =>> (SBCnt: %u)__[Addr: 0x%08X]", u16SubBlkCnt, au32Addr[0]); ++ ++ Hal_SDMMC_TransCmdSetting(eIP, eTransType, u16SubBlkCnt, u16BlkSize, Hal_CARD_TransMIUAddr(au32Addr[0]), (volatile U8_T*)au32Addr[0]); ++ Hal_SDMMC_SetSDIOIntBeginSetting(eIP, u8CMD, u32Arg, eCmdType, u16BlkCnt); ++ eErr = Hal_SDMMC_SendCmdAndWaitProcess(eIP, eTransType, eCmdType, _TransRspType(mmc_resp_type(cmd)), bCloseClock); ++ ++ ++ if( ((U16_T)eErr) == EV_STS_OK ) ++ { ++ data->bytes_xfered += u32SubLen; ++ ++ /****** Broken DMA *******/ ++ for(u16Idx=1 ; u16Idxsg[u16Idx].length; ++ u16SubBlkCnt = (U16_T)(u32SubLen/u16BlkSize); ++ pr_sd_dbg("\n____[%u] =>> (SBCnt: %u)__[Addr: 0x%08X]", u16Idx, u16SubBlkCnt, au32Addr[u16Idx]); ++ ++ Hal_SDMMC_TransCmdSetting(eIP, eTransType, u16SubBlkCnt, u16BlkSize, Hal_CARD_TransMIUAddr(au32Addr[u16Idx]), (volatile U8_T *)au32Addr[u16Idx]); ++ eErr = Hal_SDMMC_RunBrokenDmaAndWaitProcess(eIP, eCmdType); ++ ++ if((U16_T)eErr) break; ++ data->bytes_xfered += u32SubLen; ++ } ++ } ++ ++ Hal_SDMMC_SetSDIOIntEndSetting(eIP, eErr, u16BlkCnt); ++ ++ _PostDataBufferProcess(eTransType, data, p_sdmmc_slot); ++ ++ } ++ ++ ++LABEL_SD_ERR: ++ ++ cmd->error = _RequestEndProcess(eCmdType, eErr, p_sdmmc_slot, data); ++ ++ if(data) ++ data->error = cmd->error; ++ ++ eRspSt = Hal_SDMMC_GetRspToken(eIP); ++ cmd->resp[0] = _TransArrToUInt(eRspSt->u8ArrRspToken[1], eRspSt->u8ArrRspToken[2], eRspSt->u8ArrRspToken[3], eRspSt->u8ArrRspToken[4]); ++ if(eRspSt->u8RspSize == 0x10) ++ { ++ cmd->resp[1] = _TransArrToUInt(eRspSt->u8ArrRspToken[5], eRspSt->u8ArrRspToken[6], eRspSt->u8ArrRspToken[7], eRspSt->u8ArrRspToken[8]); ++ cmd->resp[2] = _TransArrToUInt(eRspSt->u8ArrRspToken[9], eRspSt->u8ArrRspToken[10], eRspSt->u8ArrRspToken[11], eRspSt->u8ArrRspToken[12]); ++ cmd->resp[3] = _TransArrToUInt(eRspSt->u8ArrRspToken[13], eRspSt->u8ArrRspToken[14], eRspSt->u8ArrRspToken[15], 0); ++ } ++ ++ /****** Print Error Message******/ ++ if(!data && cmd->error && !_PassPrintCMD(eSlot, u8CMD, u32Arg, (BOOL_T)p_sdmmc_slot->sdioFlag)) //Cmd Err but Pass Print Some Cmds ++ { ++ if(cmd->error == -EILSEQ) ++ pr_sd_err(">> [sdmmc_%u] Warn: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)\n", eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine); ++ else ++ pr_sd_err(">> [sdmmc_%u] Err: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)\n", eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine); ++ } ++ else if(data && data->error) //Data Err ++ { ++ if(data->error == -EILSEQ) ++ pr_sd_err(">> [sdmmc_%u] Warn: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)(B:%u/%u)(I:%u/%u)\n", \ ++ eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine, u16SubBlkCnt, u16BlkCnt, u16Idx, u16ProcCnt); ++ else ++ pr_sd_err(">> [sdmmc_%u] Err: #Cmd_%u (0x%08X)=>(E: 0x%04X)(S: 0x%08X)__(L:%u)(B:%u/%u)(I:%u/%u)\n", \ ++ eSlot, u8CMD, u32Arg, (U16_T)eErr, cmd->resp[0], eRspSt->u32ErrLine, u16SubBlkCnt, u16BlkCnt, u16Idx, u16ProcCnt); ++ } ++ ++ /****** Send Stop Cmd ******/ ++ if(stop) ++ { ++ u8CMD = (U8_T)stop->opcode; ++ u32Arg = (U32_T)stop->arg; ++ pr_sd_main(">> [sdmmc_%u]_CMD_%u (0x%08X)", eSlot, u8CMD, u32Arg); ++ ++ /***** Specail Case for FCIE4 SDIO ******/ ++ _CRIT_SetMIEIntEn_ForV4(eSlot, (!data ? EV_EMP : EV_DMA)); ++ ++ Hal_SDMMC_SetCmdToken(eIP, u8CMD, u32Arg); ++ Hal_SDMMC_SetSDIOIntBeginSetting(eIP, u8CMD, u32Arg, EV_CMDRSP, 0); ++ eErr = Hal_SDMMC_SendCmdAndWaitProcess(eIP, EV_EMP, EV_CMDRSP, _TransRspType(mmc_resp_type(stop)), TRUE); ++ Hal_SDMMC_SetSDIOIntEndSetting(eIP, eErr, 0); ++ ++ stop->error = _RequestEndProcess(EV_CMDRSP, eErr, p_sdmmc_slot, data); ++ ++ eRspSt = Hal_SDMMC_GetRspToken(eIP); ++ stop->resp[0] = _TransArrToUInt(eRspSt->u8ArrRspToken[1], eRspSt->u8ArrRspToken[2], eRspSt->u8ArrRspToken[3], eRspSt->u8ArrRspToken[4]); ++ ++ if(stop->error) ++ pr_sd_err(">> [sdmmc_%u] Err: #Cmd_12 => (E: 0x%04X)(S: 0x%08X)__(L:%u)\n", eSlot, (U16_T)eErr, stop->resp[0], eRspSt->u32ErrLine); ++ ++ ++ } ++ ++ //Hal_CARD_SetClock(eIP, p_sdmmc_slot->pmrsaveClk); // For Power Saving ++ ++ _CRIT_SECT_END(eSlot); ++ ++ mmc_request_done(p_mmc_host, p_mmc_req); ++ ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_set_ios ++ * @author jeremy.wang (2011/5/19) ++ * Desc: Set IO bus Behavior ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * @param p_mmc_ios : mmc_ios structure pointer ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_set_ios(struct mmc_host *p_mmc_host, struct mmc_ios *p_mmc_ios) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ _CRIT_SECT_BEGIN(eSlot); ++ ++ _SwitchPAD(eSlot); ++ ++ /****** Clock Setting*******/ ++ if(p_sdmmc_slot->currClk != p_mmc_ios->clock) ++ { ++/* Modified by Spade: enable clk in probe ++ #if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ if(p_mmc_ios->clock>0) ++ clk_prepare_enable(gp_clkSlot[eSlot]); ++ else ++ clk_disable_unprepare(gp_clkSlot[eSlot]); ++ #endif ++*/ ++ p_sdmmc_slot->currDownLevel = 0; ++ p_sdmmc_slot->currClk = p_mmc_ios->clock; ++ p_sdmmc_slot->currRealClk = _SetClock(eSlot, p_sdmmc_slot->currClk, 0, p_sdmmc_slot->currDownLevel); ++ ++ if( (p_sdmmc_slot->currRealClk==0) && (p_sdmmc_slot->currClk!=0) ) ++ printk(">> [sdmmc_%u] Set IOS => Clk=Error\n", eSlot); ++ else if(p_sdmmc_slot->currRealClk <= 400000) ++ _SetBusTiming(eSlot, 0xFF); ++ else ++ printk(">> [sdmmc_%u] Set IOS => Clk=%u (Real=%u)\n", eSlot, p_sdmmc_slot->currClk, p_sdmmc_slot->currRealClk); ++ } ++ ++ /****** Power Switch Setting *******/ ++ if(p_sdmmc_slot->currPowrMode != p_mmc_ios->power_mode) ++ { ++ p_sdmmc_slot->currPowrMode = p_mmc_ios->power_mode; ++ pr_sd_main(">> [sdmmc_%u] Set IOS => Power=%u\n", eSlot, p_sdmmc_slot->currPowrMode); ++ _SetPower(eSlot, p_sdmmc_slot->currPowrMode); ++ ++ if(p_sdmmc_slot->currPowrMode == MMC_POWER_OFF) ++ { ++ p_sdmmc_slot->initFlag = 0; ++ p_sdmmc_slot->sdioFlag = 0; ++ } ++ } ++ ++ /****** Bus Width Setting*******/ ++ if( (p_sdmmc_slot->currWidth != p_mmc_ios->bus_width) || !p_sdmmc_slot->initFlag) ++ { ++ p_sdmmc_slot->currWidth = p_mmc_ios->bus_width; ++ _SetBusWidth(eSlot, p_sdmmc_slot->currWidth); ++ pr_sd_main(">> [sdmmc_%u] Set IOS => BusWidth=%u\n", eSlot, p_sdmmc_slot->currWidth); ++ } ++ ++ /****** Bus Timing Setting*******/ ++ if( (p_sdmmc_slot->currTiming != p_mmc_ios->timing) || !p_sdmmc_slot->initFlag) ++ { ++ p_sdmmc_slot->currTiming = p_mmc_ios->timing; ++ _SetBusTiming(eSlot, p_sdmmc_slot->currTiming); ++ pr_sd_main(">> [sdmmc_%u] Set IOS => BusTiming=%u\n", eSlot, p_sdmmc_slot->currTiming); ++ } ++ ++ /****** Voltage Setting *******/ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 8)) ++ if( (p_sdmmc_slot->currVdd != p_mmc_ios->signal_voltage) || !p_sdmmc_slot->initFlag) ++ { ++ p_sdmmc_slot->currVdd = p_mmc_ios->signal_voltage; ++ pr_sd_main(">> [sdmmc_%u] Set IOS => Voltage=%u\n", eSlot, p_sdmmc_slot->currVdd); ++ _SetBusVdd(eSlot, p_sdmmc_slot->currVdd); ++ } ++#else ++ _SetBusVdd(eSlot, EV_NORVOL); ++#endif ++ ++ p_sdmmc_slot->initFlag = 1; ++ ++ _CRIT_SECT_END(eSlot); ++ ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_get_ro ++ * @author jeremy.wang (2011/5/19) ++ * Desc: Get SD card read/write permission ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * ++ * @return int : 1 = read-only, 0 = read-write. ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_get_ro(struct mmc_host *p_mmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ _CRIT_SECT_BEGIN(eSlot); ++ ++ _SwitchPAD(eSlot); ++ ++ if( _GetWriteProtect(eSlot) ) //For CB2 HW Circuit, WP=>NWP ++ p_sdmmc_slot->read_only = 1; ++ else ++ p_sdmmc_slot->read_only = 0; ++ ++ _CRIT_SECT_END(eSlot); ++ ++ pr_sd_main(">> [sdmmc_%u] Get RO => (%d)\n", eSlot, p_sdmmc_slot->read_only); ++ ++ return p_sdmmc_slot->read_only; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_get_cd ++ * @author jeremy.wang (2011/6/17) ++ * Desc: Get SD card detection status ++ * ++ * @param p_mmc_host : mmc_host structure pointer ++ * ++ * @return int : 1 = Present ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_get_cd(struct mmc_host *p_mmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ ++ //_CRIT_SECT_BEGIN(eSlot); ++ ++ //_SwitchPAD(eSlot); ++ ++ if( _GetCardDetect(eSlot) ) ++ p_sdmmc_slot->card_det = 1; ++ else ++ p_sdmmc_slot->card_det = 0; ++ ++ //_CRIT_SECT_END(eSlot); ++ ++ if(!EN_SDMMC_POLLING_CDZ) ++ printk(">> [sdmmc_%u] Get CD => (%d)\n", eSlot, p_sdmmc_slot->card_det); ++ ++ return p_sdmmc_slot->card_det; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_init_card ++ * @author jeremy.wang (2012/2/20) ++ * Desc: ++ * ++ * @param p_mmc_host : ++ * @param p_mmc_card : ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_init_card(struct mmc_host *p_mmc_host, struct mmc_card *p_mmc_card) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++ Hal_SDMMC_SDIODeviceCtrl(eIP, TRUE); ++ p_sdmmc_slot->sdioFlag = 1; ++ ++ printk(">> [sdmmc_%u] Found SDIO Device!\n", eSlot); ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_enable_sdio_irq ++ * @author jeremy.wang (2012/2/20) ++ * Desc: ++ * ++ * @param p_mmc_host : ++ * @param enable : ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_enable_sdio_irq(struct mmc_host *p_mmc_host, int enable) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = mmc_priv(p_mmc_host); ++ SlotEmType eSlot = (SlotEmType)p_sdmmc_slot->slotNo; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ ++#if (D_FCIE_M_VER == D_FCIE_M_VER__04) ++ unsigned long flags; ++ spin_lock_irqsave(&g_RegLockSlot[eSlot], flags); ++#endif ++ ++ Hal_SDMMC_SDIOIntDetCtrl(eIP, (BOOL_T)enable); ++ ++#if (D_FCIE_M_VER == D_FCIE_M_VER__04) ++ spin_unlock_irqrestore(&g_RegLockSlot[eSlot], flags); ++#endif ++ ++ if(enable) ++ { ++ pr_sdio_main(">> [sdmmc_%u] =========> SDIO IRQ EN=> (%d)\n", eSlot, enable); ++ } ++ ++} ++ ++/********************************************************************************************************** ++ * Define Static Global Structs ++ **********************************************************************************************************/ ++/*---------------------------------------------------------------------------------------------------------- ++ * st_mmc_ops ++ ----------------------------------------------------------------------------------------------------------*/ ++static const struct mmc_host_ops st_mmc_ops = ++{ ++ .enable = ms_sdmmc_enable, ++ .disable = ms_sdmmc_disable, ++ .request = ms_sdmmc_request, ++ .set_ios = ms_sdmmc_set_ios, ++ .get_ro = ms_sdmmc_get_ro, ++ .get_cd = ms_sdmmc_get_cd, ++ .init_card = ms_sdmmc_init_card, ++ .enable_sdio_irq = ms_sdmmc_enable_sdio_irq, ++ ++}; ++ ++ ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_dts_init ++ * @author jeremy.wang (2017/3/24) ++ * Desc: Device Tree Init ++ * ++ * @param p_dev : platform device ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_dts_init(struct platform_device *p_dev) ++{ ++ U8_T slotNo, ipidx = 0; ++ SlotEmType eSlot; ++ ++ U32_T u32_IPOrderSlot[3]; ++ U32_T u32_PADOrderSlot[3]; ++ U32_T u32_IntCDZSlot[3]; ++ U32_T u32_FakeCDZSlot[3]; ++ U32_T u32_SlotNums = 0; ++ U32_T u32_ReverseCDZ = 0; ++ ++ if(of_property_read_u32(p_dev->dev.of_node, "slotnum" , &u32_SlotNums)) ++ return 1; ++ if(of_property_read_u32(p_dev->dev.of_node, "revcdz" , &u32_ReverseCDZ)) ++ return 1; ++ if(of_property_read_u32_array(p_dev->dev.of_node, "slot-ip-orders", (U32_T*)u32_IPOrderSlot, 3)) ++ return 1; ++ if(of_property_read_u32_array(p_dev->dev.of_node, "slot-pad-orders", (U32_T*)u32_PADOrderSlot, 3)) ++ return 1; ++ if(of_property_read_u32_array(p_dev->dev.of_node, "slot-fakecdzs", (U32_T*)u32_FakeCDZSlot, 3)) ++ return 1; ++ if(of_property_read_u32_array(p_dev->dev.of_node, "slot-intcdzs", (U32_T*)u32_IntCDZSlot, 3)) ++ return 1; ++ if(of_property_read_u32_array(p_dev->dev.of_node, "slot-max-clks", (U32_T*)gu32_MaxClkSlot, 3)) ++ return 1; ++ if(of_property_read_u32_array(p_dev->dev.of_node, "slot-pwr-gpios", (U32_T *)gu32_PwrNoSlot, 3)) ++ return 1; ++ ++ ++ //Debug ++ /* ++ pr_err(">> [sdmmc] SlotNums= %u\n", u32_SlotNums); ++ pr_err(">> [sdmmc] SlotIPs[0-2]= %u, %u, %u \n", u32_IPOrderSlot[0], u32_IPOrderSlot[1], u32_IPOrderSlot[2]); ++ pr_err(">> [sdmmc] SlotPADs[0-2]= %u, %u, %u \n", u32_PADOrderSlot[0], u32_PADOrderSlot[1], u32_PADOrderSlot[2]); ++ pr_err(">> [sdmmc] SlotMaxClk[0-2]= %u, %u, %u \n", gu32_MaxClkSlot[0], gu32_MaxClkSlot[1], gu32_MaxClkSlot[2]); ++ pr_err(">> [sdmmc] SlotFakeCDZ[0-2]= %u, %u, %u \n", u32_FakeCDZSlot[0], u32_FakeCDZSlot[1], u32_FakeCDZSlot[2]); ++ pr_err(">> [sdmmc] SlotHotplug[0-2]= %u, %u, %u \n", u32_HotplugSlot[0], u32_HotplugSlot[1], u32_HotplugSlot[2]); ++ pr_err(">> [sdmmc] RevCDZ= %u\n", u32_ReverseCDZ); ++ */ ++ ++ gu8_SlotNums = (U8_T)u32_SlotNums; ++ gb_ReverseCDZ = (BOOL_T)u32_ReverseCDZ; ++ ++ for(slotNo =0; slotNo<3; slotNo++) ++ { ++ eSlot = (SlotEmType)slotNo; ++ ++ gu8_IPOrderSlot[eSlot] = (U8_T)u32_IPOrderSlot[eSlot]; ++ gu8_PADOrderSlot[eSlot] = (U8_T)u32_PADOrderSlot[eSlot]; ++ gb_FakeCDZSlot[eSlot] = (BOOL_T)u32_FakeCDZSlot[eSlot]; ++ gb_IntCDZSlot[eSlot] = (BOOL_T)u32_IntCDZSlot[eSlot]; ++ ++ } ++ ++ for(slotNo =0; slotNodev.of_node, (ipidx*3)); ++ gp_clkMCMSlot[eSlot] = of_clk_get(p_dev->dev.of_node, (ipidx*3) + 1); ++ gp_clkSRAMSlot[eSlot] = of_clk_get(p_dev->dev.of_node, (ipidx*3) + 2); ++ ++ if(IS_ERR(gp_clkSlot[slotNo]) ) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to get dts clock tree!\n", slotNo); ++ return 1; ++ } ++ ++ clk_prepare_enable(gp_clkMCMSlot[slotNo]); ++ clk_prepare_enable(gp_clkSRAMSlot[slotNo]); ++ clk_prepare_enable(gp_clkSlot[slotNo]); ++ ++ } ++ ++ return 0; ++ ++} ++ ++#endif ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_init_slot ++ * @author jeremy.wang (2015/12/9) ++ * Desc: Init Slot Setting ++ * ++ * @param slotNo : Slot Number ++ * @param p_sdmmc_host : ms_sdmmc_host ++ * ++ * @return int : Error Status; Return 0 if no error ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_init_slot(unsigned int slotNo, struct ms_sdmmc_host *p_sdmmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot; ++ struct mmc_host *p_mmc_host; ++ SlotEmType eSlot = (SlotEmType)slotNo; ++ IPEmType eIP = ge_IPSlot[eSlot]; ++ PADEmType ePAD = ge_PADSlot[eSlot]; ++ ++ int nRet = 0; ++ ++ /****** (1) Allocte MMC and SDMMC host ******/ ++ p_mmc_host = mmc_alloc_host(sizeof(struct ms_sdmmc_slot), &p_sdmmc_host->pdev->dev); ++ ++ if (!p_mmc_host) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate mmc_host!\n", slotNo); ++ return -ENOMEM; ++ } ++ ++ /****** (2) SDMMC host setting ******/ ++ p_sdmmc_slot = mmc_priv(p_mmc_host); ++ ++#if (!EN_SDMMC_BRO_DMA) ++ ++ p_sdmmc_slot->dma_buffer = dma_alloc_coherent(NULL, MAX_BLK_COUNT * MAX_BLK_SIZE, &p_sdmmc_slot->dma_phy_addr, GFP_KERNEL); ++ if (!p_sdmmc_slot->dma_buffer) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate sdmmc_host DMA buffer\n", slotNo); ++ return -ENOMEM; ++ } ++ ++#elif (EN_SDMMC_ADV_DMA) ++ ++ p_sdmmc_slot->adma_buffer = dma_alloc_coherent(NULL, sizeof(AdmaDescStruct) * MAX_SEG_CNT, &p_sdmmc_slot->adma_phy_addr, GFP_KERNEL); ++ if (!p_sdmmc_slot->adma_buffer) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to Allocate sdmmc_host ADMA buffer\n", slotNo); ++ return -ENOMEM; ++ } ++ ++#endif ++ ++ p_sdmmc_slot->mmc = p_mmc_host; ++ p_sdmmc_slot->slotNo = slotNo; ++ p_sdmmc_slot->pmrsaveClk = Hal_CARD_FindClockSetting(eIP, 400000, 0, 0); ++ p_sdmmc_slot->mieIRQNo = gu16_MieIntNoSlot[eSlot]; ++ p_sdmmc_slot->cdzIRQNo = gu16_CdzIntNoSlot[eSlot]; ++ p_sdmmc_slot->cdzGPIONo = Hal_CARD_GetGPIONum((GPIOEmType)slotNo, ePAD); ++ p_sdmmc_slot->pwrGPIONo = gu32_PwrNoSlot[eSlot]; ++ p_sdmmc_slot->initFlag = 0; ++ p_sdmmc_slot->sdioFlag = 0; ++ ++ p_sdmmc_slot->currClk = 0; ++ p_sdmmc_slot->currWidth = 0; ++ p_sdmmc_slot->currTiming = 0; ++ p_sdmmc_slot->currPowrMode = 0; ++ p_sdmmc_slot->currVdd = 0; ++ p_sdmmc_slot->currDDR = 0; ++ ++ ++ /***** (3) MMC host setting ******/ ++ p_mmc_host->ops = &st_mmc_ops; ++ p_mmc_host->f_min = p_sdmmc_slot->pmrsaveClk; ++ p_mmc_host->f_max = gu32_MaxClkSlot[eSlot]; ++ ++ p_mmc_host->ocr_avail = MMC_VDD_32_33|MMC_VDD_31_32|MMC_VDD_30_31|MMC_VDD_29_30|MMC_VDD_28_29|MMC_VDD_27_28|MMC_VDD_165_195; ++ p_mmc_host->caps = MMC_CAP_4_BIT_DATA|MMC_CAP_MMC_HIGHSPEED|MMC_CAP_SD_HIGHSPEED|MMC_CAP_NONREMOVABLE; ++ ++ if(!gb_IntCDZSlot[eSlot] && EN_SDMMC_POLLING_CDZ) ++ p_mmc_host->caps |= MMC_CAP_NEEDS_POLL; ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 4, 0)) ++ p_mmc_host->caps |= MMC_CAP_DISABLE; ++#endif ++ ++#if (EN_SDMMC_BRO_DMA) ++ p_mmc_host->max_blk_count = MAX_BRO_BLK_COUNT; ++#else ++ p_mmc_host->max_blk_count = MAX_BLK_COUNT; ++#endif ++ p_mmc_host->max_blk_size = MAX_BLK_SIZE; ++ ++ p_mmc_host->max_req_size = p_mmc_host->max_blk_count * p_mmc_host->max_blk_size; ++ p_mmc_host->max_seg_size = p_mmc_host->max_req_size; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++ p_mmc_host->max_segs = MAX_SEG_CNT; ++#else ++ p_mmc_host->max_phys_segs = MAX_SEG_CNT; ++ p_mmc_host->max_hw_segs = MAX_SEG_CNT; ++#endif ++ ++ p_sdmmc_host->sdmmc_slot[slotNo] = p_sdmmc_slot; ++ ++ /****** (4) IP Once Setting for Different Platform ******/ ++ Hal_CARD_IPOnceSetting(eIP); ++ ++ /****** (5) Init GPIO Setting ******/ ++ Hal_CARD_InitGPIO((GPIOEmType)slotNo, ePAD, !gb_FakeCDZSlot[eSlot]); ++ ++ if(EN_SDMMC_CHG_PWR_PIN) ++ { ++ nRet = gpio_request(p_sdmmc_slot->pwrGPIONo, "SD Power Pin"); ++ ++ if(nRet > 0 ) ++ printk(">> [sdmmc_%u] PWR Ctrl use Dyn GPIO: (%u)\n", slotNo, p_sdmmc_slot->pwrGPIONo); ++ else ++ { ++ printk(">> [sdmmc_%u] Err: Faild to request PWR GPIO (%u)\n", slotNo, p_sdmmc_slot->pwrGPIONo); ++ gu32_PwrNoSlot[eSlot] = 0; ++ } ++ } ++ ++ ++ /****** (6) Interrupt Source Setting ******/ ++ gst_IntSourceSlot[eSlot].slotNo = slotNo; ++ gst_IntSourceSlot[eSlot].eIP = eIP; ++ gst_IntSourceSlot[eSlot].eCardInt = EV_INT_SD; ++ gst_IntSourceSlot[eSlot].p_data = p_sdmmc_slot; ++ ++ /***** (7) Spinlock Init for Reg Protection ******/ ++ spin_lock_init(&g_RegLockSlot[slotNo]); ++ ++ /****** (8) Register IP IRQ *******/ ++ Hal_SDMMC_MIEIntCtrl(eIP, FALSE); ++ if(EN_SDMMC_MIEINT_MODE) ++ { ++ nRet = request_irq(p_sdmmc_slot->mieIRQNo, Hal_CARD_INT_MIE, V_IP_MIEIRQ_PARA, DRIVER_NAME, &gst_IntSourceSlot[eSlot]); ++ if (nRet) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to request MIE Interrupt (%u)!\n", slotNo, p_sdmmc_slot->mieIRQNo); ++ goto LABEL_OUT2; ++ } ++ ++ Hal_SDMMC_MIEIntCtrl(eIP, TRUE); ++ ++ if(gb_SDIOIRQSlot[eSlot]) ++ { ++ p_mmc_host->caps |= MMC_CAP_SDIO_IRQ; ++ printk(">> [sdmmc_%u] Enable SDIO Interrupt Mode! \n", slotNo); ++ ++ } ++ } ++ ++ mmc_add_host(p_mmc_host); ++ ++ if(!gb_IntCDZSlot[eSlot]) ++ { ++ if(EN_SDMMC_POLLING_CDZ) ++ printk(">> [sdmmc_%u] Polling CDZ use Fake CDZ: (%u)\n", slotNo, gb_FakeCDZSlot[eSlot]); ++ else ++ printk(">> [sdmmc_%u] Normal CDZ use Fake CDZ: (%u)\n", slotNo, gb_FakeCDZSlot[eSlot]); ++ ++ goto LABEL_OUT0; ++ } ++ ++ ++ /****** (9) Register Ext CDZ IRQ *******/ ++ if(!p_sdmmc_slot->cdzIRQNo) ++ { ++ if(p_sdmmc_slot->cdzGPIONo && gpio_to_irq(p_sdmmc_slot->cdzGPIONo)> 0 ) ++ p_sdmmc_slot->cdzIRQNo = gpio_to_irq(p_sdmmc_slot->cdzGPIONo); ++ } ++ ++ ++ tasklet_init(&p_sdmmc_slot->hotplug_tasklet, ms_sdmmc_hotplug, (unsigned long)p_sdmmc_slot); ++ ++ if(p_sdmmc_slot->cdzIRQNo) ++ { ++ ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)slotNo, ePAD, (_GetCardDetect(eSlot)? EV_GPIO_OPT3 : EV_GPIO_OPT4)); ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)slotNo, ePAD, EV_GPIO_OPT1); ++ ++ nRet = request_irq(p_sdmmc_slot->cdzIRQNo, ms_sdmmc_cdzint, gu32_CDZIRQParaSlot[eSlot], DRIVER_NAME, &gst_IntSourceSlot[eSlot]); ++ if(nRet) ++ { ++ pr_err(">> [sdmmc_%u] Err: Failed to request CDZ Interrupt (%u)!\n", slotNo, p_sdmmc_slot->cdzIRQNo); ++ goto LABEL_OUT1; ++ } ++ ++ printk(">> [sdmmc_%u] Int CDZ use Ext GPIO IRQ: (%u)\n", slotNo, p_sdmmc_slot->cdzIRQNo); ++ ++ Hal_CARD_SetGPIOIntAttr((GPIOEmType)slotNo, ePAD, EV_GPIO_OPT2); ++ ++ if(gb_WakeupCDZIRQSlot[eSlot]) ++ irq_set_irq_wake(p_sdmmc_slot->cdzIRQNo, TRUE); ++ ++ } ++ else ++ { ++ printk(">> [sdmmc_%u] CDZ IRQ doesn't exist!\n", slotNo); ++ BUG_ON(1); //Coult not continue, it must be solved first (config issue) ++ } ++ ++ ++LABEL_OUT0: ++ return 0; ++ ++LABEL_OUT1: ++ tasklet_kill(&p_sdmmc_slot->hotplug_tasklet); ++ free_irq(p_sdmmc_slot->mieIRQNo, &gst_IntSourceSlot[eSlot]); ++ ++ mmc_remove_host(p_mmc_host); ++ mmc_free_host(p_mmc_host); ++ ++LABEL_OUT2: ++#if (!EN_SDMMC_BRO_DMA) ++ if (p_sdmmc_slot->dma_buffer) ++ dma_free_coherent(NULL, MAX_BLK_COUNT * MAX_BLK_SIZE, p_sdmmc_slot->dma_buffer, p_sdmmc_slot->dma_phy_addr); ++#endif ++ ++ return nRet; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_probe ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Probe Platform Device ++ * ++ * @param p_dev : platform_device ++ * ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++//struct ms_sdmmc_host *p_sdmmc_host; ++static int ms_sdmmc_probe(struct platform_device *p_dev) ++{ ++ struct ms_sdmmc_host *p_sdmmc_host; ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ printk(KERN_INFO ">> [sdmmc] ms_sdmmc_probe \n"); ++ ++ p_sdmmc_host = kzalloc(sizeof(struct ms_sdmmc_host), GFP_KERNEL); ++ ++ if (!p_sdmmc_host) ++ { ++ pr_err(">> [sdmmc] Err: Failed to Allocate p_sdmmc_host!\n\n"); ++ return -ENOMEM; ++ } ++ ++ p_sdmmc_host->pdev = p_dev; ++ ++ /***** device data setting ******/ ++ platform_set_drvdata(p_dev, p_sdmmc_host); ++ ++ /***** device PM wakeup setting ******/ ++ device_init_wakeup(&p_dev->dev, 1); ++ ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ ++ if(ms_sdmmc_dts_init(p_dev)) ++ { ++ pr_err(">> [sdmmc] Err: Failed to use DTS funciton!\n\n"); ++ } ++ ++#endif ++ ++ for(slotNo =0; slotNo> [sdmmc_%u] Probe Platform Devices...(Ret:%d) \n", slotNo, ret); ++ if(ret!=0) ++ { ++ tret = ret; ++ } ++ ++ } ++ ++ if(tret!=0) ++ kfree(p_sdmmc_host); ++ ++ return tret; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_remove_slot ++ * @author jeremy.wang (2015/12/9) ++ * Desc: Remove Slot Setting ++ * ++ * @param slotNo : Slot Number ++ * @param p_sdmmc_host : ms_sdmmc_host ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_remove_slot(unsigned int slotNo, struct ms_sdmmc_host *p_sdmmc_host) ++{ ++ struct ms_sdmmc_slot *p_sdmmc_slot = p_sdmmc_host->sdmmc_slot[slotNo]; ++ struct mmc_host *p_mmc_host = p_sdmmc_slot->mmc; ++ SlotEmType eSlot = (SlotEmType)slotNo; ++ ++ mmc_remove_host(p_mmc_host); ++ ++ if (p_sdmmc_slot->dma_buffer) ++ dma_free_coherent(NULL, MAX_BLK_COUNT*MAX_BLK_SIZE, p_sdmmc_slot->dma_buffer, p_sdmmc_slot->dma_phy_addr); ++ ++ if(EN_SDMMC_MIEINT_MODE) ++ free_irq(p_sdmmc_slot->mieIRQNo, &gst_IntSourceSlot[eSlot]); ++ ++ mmc_free_host(p_mmc_host); ++ ++ if(gb_IntCDZSlot[eSlot]) ++ { ++ tasklet_kill(&p_sdmmc_slot->hotplug_tasklet); ++ if(p_sdmmc_slot->cdzIRQNo) ++ free_irq(p_sdmmc_slot->cdzIRQNo, &gst_IntSourceSlot[eSlot]); ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_remove ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Revmoe MMC host ++ * ++ * @param p_dev : platform device structure ++ * ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++static int ms_sdmmc_remove(struct platform_device *p_dev) ++{ ++ struct ms_sdmmc_host *p_sdmmc_host = platform_get_drvdata(p_dev); ++ unsigned int slotNo = 0; ++ ++ platform_set_drvdata(p_dev, NULL); ++ ++ for(slotNo=0; slotNo> [sdmmc_%u] Remove devices...\n", slotNo); ++ ++ } ++ ++ return 0; ++} ++ ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ ++ #ifdef CONFIG_PM ++ static int ms_sdmmc_devpm_prepare(struct device *dev) ++ { ++ return 0; ++ } ++ ++ static void ms_sdmmc_devpm_complete(struct device *dev) ++ { ++ ++ } ++ ++ static int ms_sdmmc_devpm_suspend(struct device *dev) ++ { ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ for(slotNo=0; slotNo> [sdmmc_%u] Suspend device pm...(Ret:%u) \n", slotNo, ret); ++ } ++ ++ return tret; ++ } ++ ++ static int ms_sdmmc_devpm_resume(struct device *dev) ++ { ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ for(slotNo=0; slotNo> [sdmmc_%u] Resume device pm...(Ret:%u) \n", slotNo, ret); ++ } ++ ++ return tret; ++ } ++ ++ #else ++ ++ #define ms_sdmmc_devpm_prepare NULL ++ #define ms_sdmmc_devpm_complete NULL ++ #define ms_sdmmc_devpm_suspend NULL ++ #define ms_sdmmc_devpm_resume NULL ++ ++ #endif ++ ++ static int ms_sdmmc_devpm_runtime_suspend(struct device *dev) ++ { ++ printk(">> [sdmmc] Runtime Suspend device pm...\n"); ++ return 0; ++ } ++ ++ static int ms_sdmmc_devpm_runtime_resume(struct device *dev) ++ { ++ printk(">> [sdmmc] Runtime Resume device pm...\n"); ++ return 0; ++ } ++ ++ #define ms_sdmmc_suspend NULL ++ #define ms_sdmmc_resume NULL ++ ++ ++#else ++ ++ #ifdef CONFIG_PM ++ ++ #if ( LINUX_VERSION_CODE < KERNEL_VERSION(3, 11, 0) ) // CONFIG_PM ++ ++ /*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_suspend ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Suspend MMC host ++ * ++ * @param p_dev : platform device structure ++ * @param state : Power Management Transition State ++ * ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++ static int ms_sdmmc_suspend(struct platform_device *p_dev, pm_message_t state) ++ { ++ struct ms_sdmmc_host *p_sdmmc_host = platform_get_drvdata(p_dev); ++ struct mmc_host *p_mmc_host; ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ ++ for(slotNo=0; slotNosdmmc_slot[slotNo]->mmc; ++ ++ if (p_mmc_host) ++ { ++ ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) ++ ret = mmc_suspend_host(p_mmc_host); ++ #else ++ ret = mmc_suspend_host(p_mmc_host, state); ++ #endif ++ printk(">> [sdmmc_%u] Suspend host...(Ret:%u) \n", slotNo, ret); ++ ++ if(ret!=0) ++ tret = ret; ++ } ++ ++ } ++ ++ return tret; ++ } ++ ++ /*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_resume ++ * @author jeremy.wang (2011/5/18) ++ * Desc: Resume MMC host ++ * ++ * @param p_dev : platform device structure ++ * @return int : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++ static int ms_sdmmc_resume(struct platform_device *p_dev) ++ { ++ struct ms_sdmmc_host *p_sdmmc_host = platform_get_drvdata(p_dev); ++ struct mmc_host *p_mmc_host; ++ unsigned int slotNo = 0; ++ int ret = 0, tret = 0; ++ ++ for(slotNo=0; slotNosdmmc_slot[slotNo]->mmc; ++ if (p_mmc_host) ++ { ++ ret = mmc_resume_host(p_mmc_host); ++ printk(">> [sdmmc_%u] Resume host...(Ret:%u) \n", slotNo, ret); ++ if(ret!=0) ++ tret = ret; ++ } ++ } ++ ++ return tret; ++ } ++ ++ #else ++ ++ static int ms_sdmmc_suspend(struct platform_device *p_dev, pm_message_t state) ++ { ++ int ret = 0; ++ return ret; ++ } ++ ++ static int ms_sdmmc_resume(struct platform_device *p_dev) ++ { ++ int ret = 0; ++ return ret; ++ } ++ ++ #endif ++ ++ #else // !CONFIG_PM ++ ++ //Current driver does not support following two functions, therefore set them to NULL. ++ #define ms_sdmmc_suspend NULL ++ #define ms_sdmmc_resume NULL ++ ++ #endif // End of CONFIG_PM ++ ++ ++ ++#endif ++ ++ ++/********************************************************************************************************** ++ * Define Static Global Structs ++ **********************************************************************************************************/ ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++/*---------------------------------------------------------------------------------------------------------- ++ * ms_sdmmc_of_match_table ++ ----------------------------------------------------------------------------------------------------------*/ ++static const struct of_device_id ms_sdmmc_of_match_table[] = { ++ { .compatible = "mstar,sdmmc" }, ++ {} ++}; ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ms_sdmmc_dev_pm_ops ++ ----------------------------------------------------------------------------------------------------------*/ ++static struct dev_pm_ops ms_sdmmc_dev_pm_ops = { ++ .suspend = ms_sdmmc_devpm_suspend, ++ .resume = ms_sdmmc_devpm_resume, ++ .prepare = ms_sdmmc_devpm_prepare, ++ .complete = ms_sdmmc_devpm_complete, ++ .runtime_suspend = ms_sdmmc_devpm_runtime_suspend, ++ .runtime_resume = ms_sdmmc_devpm_runtime_resume, ++}; ++ ++#else ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * st_ms_sdmmc_device ++ ----------------------------------------------------------------------------------------------------------*/ ++static u64 mmc_dmamask = 0xffffffffUL; ++static struct platform_device ms_sdmmc_pltdev = ++{ ++ .name = DRIVER_NAME, ++ .id = 0, ++ .dev = ++ { ++ .dma_mask = &mmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL, ++ }, ++}; ++ ++#endif //End of (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * st_ms_sdmmc_driver ++ ----------------------------------------------------------------------------------------------------------*/ ++static struct platform_driver ms_sdmmc_pltdrv = ++{ ++ .remove = ms_sdmmc_remove,/*__exit_p(ms_sdmmc_remove)*/ ++ .suspend = ms_sdmmc_suspend, ++ .resume = ms_sdmmc_resume, ++ .probe = ms_sdmmc_probe, ++ .driver = ++ { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ ++#if (defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ .of_match_table = of_match_ptr(ms_sdmmc_of_match_table), ++ .pm = &ms_sdmmc_dev_pm_ops, ++#endif ++ ++ }, ++}; ++ ++ ++/********************************************************************************************************** ++ * Init & Exit Modules ++ **********************************************************************************************************/ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_mci_init ++ * @author jeremy.wang (2011/7/18) ++ * Desc: Linux Module Function for Init ++ * ++ * @return s32 __init : Error Status; Return 0 if no error. ++ ----------------------------------------------------------------------------------------------------------*/ ++static s32 ms_sdmmc_init(void) ++{ ++ ++ printk(KERN_INFO ">> [sdmmc] %s Driver Initializing... \n", DRIVER_NAME); ++ ++#if !(defined(CONFIG_OF) && (EN_DEV_TREE_SUP)) ++ platform_device_register(&ms_sdmmc_pltdev); ++#endif ++ ++ return platform_driver_register(&ms_sdmmc_pltdrv); ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_exit ++ * @author jeremy.wang (2011/9/8) ++ * Desc: Linux Module Function for Exit ++ ----------------------------------------------------------------------------------------------------------*/ ++static void ms_sdmmc_exit(void) ++{ ++ platform_driver_unregister(&ms_sdmmc_pltdrv); ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: ms_sdmmc_cdzgpio_swctrl ++ * @author jeremy.wang (2015/1/7) ++ * Desc: Switch CDZ GPIO to output state and control its state ++ * ++ * @param slotNo : GPIO1/GPIO2/GPIO3... ++ * @param bOutputState : SW control output state ++ ----------------------------------------------------------------------------------------------------------*/ ++void ms_sdmmc_cdzgpio_swctrl(unsigned int slotNo, bool bOutputState) ++{ ++ PADEmType ePAD = ge_PADSlot[slotNo]; ++ ++ pr_sdio_main(">> [sdmmc_%u] cdzgpio sw ctrl output(%u) \n", slotNo, bOutputState); ++ Hal_CARD_SetGPIOState((GPIOEmType)slotNo, ePAD, bOutputState); ++} ++EXPORT_SYMBOL(ms_sdmmc_cdzgpio_swctrl); ++ ++ ++ ++module_init(ms_sdmmc_init); ++module_exit(ms_sdmmc_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION(DRIVER_DESC); ++MODULE_AUTHOR("Jeremy_Wang"); +diff --git a/drivers/mstar/sdmmc/src/hal_card_intr.c b/drivers/mstar/sdmmc/src/hal_card_intr.c +new file mode 100644 +index 00000000..e51ca2c6 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_intr.c +@@ -0,0 +1,475 @@ ++ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_intr.c ++ * @author jeremy.wang (2011/07/21) ++ * Desc: ++ * The Interrupt behavior of all cards will run here. ++ * The goal is that we don't need to change HAL Level code (But its h file code) ++ * ++ * The limitations were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API or HAL level, not driver flow process. ++ * (3) MIE Event Int and Card Change Event Int function belong to here. ++ * (4) FCIE/SDIO IP interrupt register function belong to here. ++ * (5) Because ISR belongs to OS design, so we must use OS define option to separate them. ++ * (6) This c file could not use project/cpu/icver/specific define option here, but its h file could. ++ * ++ * P.S. EN_XX for ON/OFF Define, V_XX for Value Define, ++ * RT_XX for Retry Times Define, WT_XX for Wait Time Define, M_XX for Mask Value Define ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_intr.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Enable Setting ++//----------------------------------------------------------------------------------------------------------- ++#define EN_TRFUNC (TRUE) ++ ++// Value Setting ++//----------------------------------------------------------------------------------------------------------- ++#define V_MAXSLOTS 2 ++ ++ ++//*********************************************************************************************************** ++ ++ ++// Reg Static Init Setting ++//----------------------------------------------------------------------------------------------------------- ++//#define V_SD_MIE_INT_INIT (R_SD_CMD_END_EN|R_SD_DATA_END_EN|R_CARD_DMA_END_EN|R_MMA_LSDONE_END_EN) ++ ++// Mask Range ++//----------------------------------------------------------------------------------------------------------- ++#define M_SD_DCRCSTS (R_SD_DAT_CERR|R_SD_DAT_STSERR|R_SD_DAT_STSNEG) ++ ++#define M_CARD_INT_EN (R_MMA_DATA_END_EN|R_SD_CMD_END_EN|R_SD_DATA_END_EN|R_MS_DATA_END_EN| \ ++ R_CF_CMD_END_EN|R_CF_DATA_END_EN|R_SM_JOB_END_EN|R_CARD_DMA_END_EN|R_MMA_LSDONE_END_EN) ++ ++// Mask Reg Value ++//----------------------------------------------------------------------------------------------------------- ++#define M_REG_DCRCERR(IP) (CARD_REG(A_SD_STS_REG(IP)) & M_SD_DCRCSTS) //0x1F ++ ++ ++//IP_FCIE or IP_SDIO Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_SD_REG_POS(IP) GET_CARD_BANK(IP, 0) ++ ++#define A_MIE_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x00) ++#define A_MIE_INT_EN_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x01) ++ ++#define A_CARD_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x05) ++#define A_CARD_INT_EN_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x06) ++#define A_SD_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x12) ++#define A_EMMC_PATH_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x16) ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile U16_T gu16_MIEINT_Mode[3] = {0}; ++static volatile U16_T gu16_MIEEvent_ForInt[3] = {0}; //MIEEvent for Interrupt ++static volatile U16_T gu16_MIEIntEN_ForSDIO[3] = {0}; ++static volatile BOOL_T gb_StopWaitMIE[3] = {0}; ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_TRFUNC) ++ #define TR_INT(p) p ++#else ++ #define TR_INT(p) ++#endif ++ ++// Register Operation Define ==> For Return SD Change Status Pos ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_SDCHG(IPEmType eIP) ++{ ++ PortEmType ePort = GET_CARD_PORT(eIP); ++ ++ switch( (U8_T)ePort ) ++ { ++ case (U8_T)EV_PORT_SDIO1: ++ return R_SDIO_STS_CHG; ++ case (U8_T)EV_PORT_SDIO2: ++ return R_SDIO2_STS_CHG; ++ case (U8_T) EV_PORT_SD: ++ return R_SD_STS_CHG; ++ default: ++ return 0; ++ } ++} ++ ++// Register Operation Define ==> For Return SD Change Status Int Pos ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_SDCHG_INTEN(IPEmType eIP) ++{ ++ PortEmType ePort = GET_CARD_PORT(eIP); ++ ++ switch( (U8_T)ePort ) ++ { ++ case (U8_T)EV_PORT_SDIO1: ++ return R_SDIO_STS_EN; ++ case (U8_T)EV_PORT_SDIO2: ++ return R_SDIO2_STS_EN; ++ case (U8_T) EV_PORT_SD: ++ return R_SD_STS_EN; ++ default: ++ return 0; ++ } ++} ++ ++ ++BOOL_T _CARD_INT_SaveMIEEvent(IPEmType eIP) ++{ ++ U16_T u16Reg = CARD_REG(A_MIE_EVENT_REG(eIP)); ++ ++ if(CARD_REG(A_EMMC_PATH_CTL_REG(eIP)) & R_EMMC_EN) //Emmc Event ++ return (FALSE); ++ ++ gu16_MIEEvent_ForInt[eIP] |= u16Reg; //Summary All 0x00Reg Event ++ ++ u16Reg &= CARD_REG(A_MIE_INT_EN_REG(eIP)); ++ ++ /****** Clean Card MIE Event *******/ ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = (M_CARD_INT_EN & u16Reg); ++ ++#if 0 // For Debug whether event clear or not ++ prtstring("Debug: [MIE_EVENT_REG]= "); ++ prtU16Hex(CARD_REG(A_MIE_EVENT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ while(1) ++ { ++ } ++#endif ++ ++ ++ ++ return (TRUE); ++} ++ ++ ++static BOOL_T _CARD_INT_DetectSDIOInt(IPEmType eIP) ++{ ++ U16_T u16Reg = CARD_REG(A_MIE_EVENT_REG(eIP)); ++ ++ if( (u16Reg & R_SDIO_INT) && (gu16_MIEIntEN_ForSDIO[eIP] == R_SDIO_INT_EN) ) ++ { ++ //printk("_M[%04X]_", CARD_REG(A_MIE_EVENT_REG(eIP))); ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = R_SDIO_INT; //Clear SDIO_EVENT to avoid trig int again ++ ++ /****** Fix IP Bug for DAT1 CRC error, sdio will trig interrupt ******/ ++ if(!M_REG_DCRCERR(eIP)) ++ return (TRUE); ++ else ++ return (FALSE); ++ } ++ ++ return (FALSE); ++ ++} ++ ++ ++BOOL_T _CARD_INT_DetectCDZEvent(IPEmType eIP, IntCardEmType eCardInt) ++{ ++ U16_T u16CardEvent = 0, u16CardInt = 0; ++ BOOL_T bRet = FALSE; ++ ++ ++ u16CardEvent = CARD_REG(A_CARD_EVENT_REG(eIP)); ++ u16CardInt = CARD_REG(A_CARD_INT_EN_REG(eIP)); ++ ++ if((u16CardEvent==0) || (u16CardInt==0)) // No Card Int Event ++ return FALSE; ++ ++ TR_INT(prtstring("\n>> @@@@@ DetectCH...CINT(")); ++ TR_INT(prtU16Hex(u16CardInt)); ++ TR_INT(prtstring("),CENT(")); ++ TR_INT(prtU16Hex(u16CardEvent)); ++ TR_INT(prtstring(")\n")); ++ ++ if(eCardInt == EV_INT_SD) ++ { ++ if( (u16CardEvent & _REG_SDCHG(eIP)) && (u16CardInt & _REG_SDCHG_INTEN(eIP)) ) ++ { ++ CARD_REG_CLRBIT(A_CARD_INT_EN_REG(eIP), _REG_SDCHG_INTEN(eIP)); //Disable SDMMC Card Change Int ++ bRet = TRUE; ++ } ++ } ++ ++ return bRet; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIEIntCtrl ++ * @author jeremy.wang (2015/11/4) ++ * Desc: Enable Card MIE Interrupt Mode ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCardInt : SD/MS/CF/XD... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_MIEIntCtrl(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable) ++{ ++ if(bEnable) ++ gu16_MIEINT_Mode[eIP] |= eCardInt; ++ else ++ gu16_MIEINT_Mode[eIP] &= (~eCardInt); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIEIntRunning ++ * @author jeremy.wang (2011/9/7) ++ * Desc: Check Int Mode Running or Not ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCardInt : SD/MS/CF/XD... ++ * ++ * @return BOOL_T : Interrupt Running or Not ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_INT_MIEIntRunning(IPEmType eIP, IntCardEmType eCardInt) ++{ ++ if(gu16_MIEINT_Mode[eIP] & eCardInt ) ++ return (TRUE); ++ else ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_SetMIEIntEn ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Set MIE_Int_En to Trig Interrupt ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCardInt : SD/MS/CF/XD... ++ * @param u16RegMIEIntEN : MIE_Int_En Reg Setting ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_SetMIEIntEn(IPEmType eIP, IntCardEmType eCardInt, U16_T u16RegMIEIntEN) ++{ ++ /****** Set SD MIE Int Event ******/ ++ if(eCardInt == EV_INT_SD) ++ { ++ if(gu16_MIEINT_Mode[eIP] & EV_INT_SD) ++ CARD_REG(A_MIE_INT_EN_REG(eIP)) = (u16RegMIEIntEN | gu16_MIEIntEN_ForSDIO[eIP]) ; //Enable MIE_INT_EN ++ else ++ CARD_REG(A_MIE_INT_EN_REG(eIP)) = 0; //Clear MIE_INT_EN to Avoid Interrupt ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_SetMIEIntEn_ForSDIO ++ * @author jeremy.wang (2014/5/28) ++ * Desc: ++ * ++ * @param eIP : ++ * @param eCardInt : ++ * @param bEnable : ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_SetMIEIntEn_ForSDIO(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable) ++{ ++ if(eCardInt == EV_INT_SD) ++ { ++ if(gu16_MIEINT_Mode[eIP] & EV_INT_SD) ++ { ++ if(bEnable) ++ { ++ /****** Specail Process: Clear SDIO Int to avoid trig Int after SDIO Int Enable ******/ ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = R_SDIO_INT; ++ ++ gu16_MIEIntEN_ForSDIO[eIP] = R_SDIO_INT_EN; ++ CARD_REG_SETBIT(A_MIE_INT_EN_REG(eIP), R_SDIO_INT_EN); ++ } ++ else ++ { ++ gu16_MIEIntEN_ForSDIO[eIP] = 0; ++ CARD_REG_CLRBIT(A_MIE_INT_EN_REG(eIP), R_SDIO_INT_EN); ++ } ++ } ++ } ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_ClearMIEEvent ++ * @author jeremy.wang (2011/9/7) ++ * Desc: Clear MIE Event That We Have Saved in Interrupt Mode ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_ClearMIEEvent(IPEmType eIP) ++{ ++ gu16_MIEEvent_ForInt[eIP] = 0; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_GetMIEEvent ++ * @author jeremy.wang (2011/9/7) ++ * Desc: Get Current MIE Event That We Have Saved in Interrupt Mode ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ++ * @return U16_T : Current MIE Event ++ ----------------------------------------------------------------------------------------------------------*/ ++U16_T Hal_CARD_INT_GetMIEEvent(IPEmType eIP) ++{ ++ return gu16_MIEEvent_ForInt[eIP]; ++} ++ ++ ++//*********************************************************************************************************** ++// Interrupt Handler Function ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++static DECLARE_WAIT_QUEUE_HEAD(fcie1_mieint_wait); ++static DECLARE_WAIT_QUEUE_HEAD(fcie2_mieint_wait); ++static DECLARE_WAIT_QUEUE_HEAD(fcie3_mieint_wait); ++ ++#endif ++//########################################################################################################### ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_WaitMIEEvent ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Set WaitQueue Handler to Wait MIE Event ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u16ReqEvent : MIE Event for waiting ++ * @param u32WaitMs : Waiting Time (ms) ++ * ++ * @return BOOL_T : TRUE (Success), FALSE (Timeout) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_INT_WaitMIEEvent(IPEmType eIP, U16_T u16ReqEvent, U32_T u32WaitMs) ++{ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ if(eIP==EV_IP_FCIE1) ++ wait_event_timeout(fcie1_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ else if((eIP==EV_IP_FCIE2)) ++ wait_event_timeout(fcie2_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ else if((eIP==EV_IP_FCIE3)) ++ wait_event_timeout(fcie3_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ ++ ++ if((gu16_MIEEvent_ForInt[eIP] & u16ReqEvent) != u16ReqEvent) ++ return FALSE; ++ ++ return TRUE; ++//########################################################################################################### ++#endif ++ ++ /****** Not Support (Ex: D_OS_ARCH = D_OS_UBOOT) ******/ ++ return FALSE; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_StopWaitMIEEventCtrl ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Stop Wait MIE Event to Avoid Long Time Waiting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_StopWaitMIEEventCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ gb_StopWaitMIE[eIP] = bEnable; ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ if(gb_StopWaitMIE[eIP]) ++ { ++ /****** Break Current Wait Event *******/ ++ if(eIP==EV_IP_FCIE1) ++ wake_up(&fcie1_mieint_wait); ++ else if((eIP==EV_IP_FCIE2)) ++ wake_up(&fcie2_mieint_wait); ++ else if((eIP==EV_IP_FCIE3)) ++ wake_up(&fcie3_mieint_wait); ++ } ++#endif ++//########################################################################################################### ++ ++} ++ ++ ++//*********************************************************************************************************** ++// Interrupt Function ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include "../inc/ms_sdmmc_lnx.h" ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIE ++ * @author jeremy.wang (2012/2/13) ++ * Desc: ++ * ++ * @param irq : ++ * @param p_dev_id : ++ * ++ * @return irqreturn_t : ++ ----------------------------------------------------------------------------------------------------------*/ ++irqreturn_t Hal_CARD_INT_MIE(int irq, void *p_dev_id) ++{ ++ irqreturn_t irq_t = IRQ_NONE; ++ IntSourceStruct* pstIntSource = p_dev_id; ++ IPEmType eIP = pstIntSource->eIP; ++ //IntCardEmType eCardInt = pstIntSource->eCardInt; ++ struct ms_sdmmc_slot *p_sdmmc_slot = pstIntSource->p_data; ++ ++ if(_CARD_INT_DetectSDIOInt(eIP)) ++ { ++ mmc_signal_sdio_irq(p_sdmmc_slot->mmc); ++ irq_t = IRQ_HANDLED; ++ } ++ ++ if(_CARD_INT_SaveMIEEvent(eIP)) ++ { ++ if(eIP==EV_IP_FCIE1) ++ wake_up(&fcie1_mieint_wait); ++ else if((eIP==EV_IP_FCIE2)) ++ wake_up(&fcie2_mieint_wait); ++ else if((eIP==EV_IP_FCIE3)) ++ wake_up(&fcie3_mieint_wait); ++ ++ irq_t = IRQ_HANDLED; ++ } ++ ++ return irq_t; ++} ++ ++ ++//########################################################################################################### ++#endif ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/drivers/mstar/sdmmc/src/hal_card_intr_v5.c b/drivers/mstar/sdmmc/src/hal_card_intr_v5.c +new file mode 100644 +index 00000000..ec5f1d00 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_intr_v5.c +@@ -0,0 +1,385 @@ ++ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_intr_v5.c ++ * @author jeremy.wang (2015/10/29) ++ * Desc: ++ * The Interrupt behavior of all cards will run here. ++ * The goal is that we don't need to change HAL Level code (But its h file code) ++ * ++ * The limitations were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API or HAL level, not driver flow process. ++ * (3) MIE Event Int and Card Change Event Int function belong to here. ++ * (4) FCIE/SDIO IP interrupt register function belong to here. ++ * (5) Because ISR belongs to OS design, so we must use OS define option to separate them. ++ * (6) This c file could not use project/cpu/icver/specific define option here, but its h file could. ++ * ++ * P.S. EN_XX for ON/OFF Define, V_XX for Value Define, ++ * RT_XX for Retry Times Define, WT_XX for Wait Time Define, M_XX for Mask Value Define ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_intr_v5.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Enable Setting ++//----------------------------------------------------------------------------------------------------------- ++#define EN_TRFUNC (TRUE) ++ ++// Value Setting ++//----------------------------------------------------------------------------------------------------------- ++#define V_MAXSLOTS 2 ++ ++ ++//*********************************************************************************************************** ++ ++ ++// Reg Static Init Setting ++//----------------------------------------------------------------------------------------------------------- ++//#define V_SD_MIE_INT_INIT (R_SD_CMD_END_EN|R_SD_DATA_END_EN|R_CARD_DMA_END_EN|R_MMA_LSDONE_END_EN) ++ ++// Mask Range ++//----------------------------------------------------------------------------------------------------------- ++#define M_CARD_INT_EN (R_DATA_END_IEN|R_CMD_END_IEN|R_BUSY_END_IEN) ++ ++// Mask Reg Value ++//----------------------------------------------------------------------------------------------------------- ++#define M_REG_DCRCERR(IP) (CARD_REG(A_SD_STS_REG(IP)) & M_SD_DCRCSTS) //0x1F ++ ++ ++//IP_FCIE or IP_SDIO Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_SD_REG_POS(IP) GET_CARD_BANK(IP, 0) ++ ++#define A_MIE_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x00) ++#define A_MIE_INT_EN_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x01) ++ ++#define A_MIE_FUNC_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x07) ++#define A_SD_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0D) ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile U16_T gu16_MIEINT_Mode[3] = {0}; ++static volatile U16_T gu16_MIEEvent_ForInt[3] = {0}; //MIEEvent for Interrupt ++static volatile U16_T gu16_MIEIntEN_ForSDIO[3] = {0}; ++static volatile BOOL_T gb_StopWaitMIE[3] = {0}; ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_TRFUNC) ++ #define TR_INT(p) p ++#else ++ #define TR_INT(p) ++#endif ++ ++ ++ ++BOOL_T _CARD_INT_SaveMIEEvent(IPEmType eIP) ++{ ++ U16_T u16Reg = CARD_REG(A_MIE_EVENT_REG(eIP)); ++ ++ if ( CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) & R_EMMC_EN ) //Emmc Event ++ return (FALSE); ++ ++ gu16_MIEEvent_ForInt[eIP] |= u16Reg; //Summary All 0x00Reg Event ++ ++ u16Reg &= CARD_REG(A_MIE_INT_EN_REG(eIP)); ++ ++ /****** Clean Card MIE Event *******/ ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = (M_CARD_INT_EN & u16Reg); ++ ++#if 0 // For Debug whether event clear or not ++ prtstring("Debug: [MIE_EVENT_REG]= "); ++ prtU16Hex(CARD_REG(A_MIE_EVENT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ while(1) ++ { ++ } ++#endif ++ ++ return (TRUE); ++} ++ ++ ++static BOOL_T _CARD_INT_DetectSDIOInt(IPEmType eIP) ++{ ++ U16_T u16Reg = CARD_REG(A_MIE_EVENT_REG(eIP)); ++ ++ if( (u16Reg & R_SDIO_INT) && (gu16_MIEIntEN_ForSDIO[eIP] == R_SDIO_INT_IEN) ) ++ { ++ //printk("_M[%04X]_", CARD_REG(A_MIE_EVENT_REG(eIP))); ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = R_SDIO_INT; //Clear SDIO_EVENT to avoid trig int again ++ ++ return (TRUE); ++ } ++ ++ return (FALSE); ++ ++} ++ ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIEIntCtrl ++ * @author jeremy.wang (2015/11/4) ++ * Desc: Enable Card MIE Interrupt Mode ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCardInt : SD/MS/CF/XD... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_MIEIntCtrl(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable) ++{ ++ if(bEnable) ++ gu16_MIEINT_Mode[eIP] |= eCardInt; ++ else ++ gu16_MIEINT_Mode[eIP] &= (~eCardInt); ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIEIntRunning ++ * @author jeremy.wang (2011/9/7) ++ * Desc: Check Int Mode Running or Not ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCardInt : SD/MS/CF/XD... ++ * ++ * @return BOOL_T : Interrupt Running or Not ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_INT_MIEIntRunning(IPEmType eIP, IntCardEmType eCardInt) ++{ ++ if(gu16_MIEINT_Mode[eIP] & eCardInt ) ++ return (TRUE); ++ else ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_SetMIEIntEn ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Set MIE_Int_En to Trig Interrupt ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCardInt : SD/MS/CF/XD... ++ * @param u16RegMIEIntEN : MIE_Int_En Reg Setting ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_SetMIEIntEn(IPEmType eIP, IntCardEmType eCardInt, U16_T u16RegMIEIntEN) ++{ ++ /****** Set SD MIE Int Event ******/ ++ if(eCardInt == EV_INT_SD) ++ { ++ if(gu16_MIEINT_Mode[eIP] & EV_INT_SD) ++ CARD_REG(A_MIE_INT_EN_REG(eIP)) = (u16RegMIEIntEN | gu16_MIEIntEN_ForSDIO[eIP]) ; //Enable MIE_INT_EN ++ else ++ CARD_REG(A_MIE_INT_EN_REG(eIP)) = 0; //Clear MIE_INT_EN to Avoid Interrupt ++ } ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_SetMIEIntEn_ForSDIO ++ * @author jeremy.wang (2014/5/28) ++ * Desc: ++ * ++ * @param eIP : ++ * @param eCardInt : ++ * @param bEnable : ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_SetMIEIntEn_ForSDIO(IPEmType eIP, IntCardEmType eCardInt, BOOL_T bEnable) ++{ ++ if(eCardInt == EV_INT_SD) ++ { ++ if(gu16_MIEINT_Mode[eIP] & EV_INT_SD) ++ { ++ if(bEnable) ++ { ++ /****** Specail Process: Clear SDIO Int to avoid trig Int after SDIO Int Enable ******/ ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = R_SDIO_INT; ++ ++ gu16_MIEIntEN_ForSDIO[eIP] = R_SDIO_INT_IEN; ++ CARD_REG_SETBIT(A_MIE_INT_EN_REG(eIP), R_SDIO_INT_IEN); ++ } ++ else ++ { ++ gu16_MIEIntEN_ForSDIO[eIP] = 0; ++ CARD_REG_CLRBIT(A_MIE_INT_EN_REG(eIP), R_SDIO_INT_IEN); ++ } ++ } ++ } ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_ClearMIEEvent ++ * @author jeremy.wang (2011/9/7) ++ * Desc: Clear MIE Event That We Have Saved in Interrupt Mode ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_ClearMIEEvent(IPEmType eIP) ++{ ++ gu16_MIEEvent_ForInt[eIP] = 0; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_GetMIEEvent ++ * @author jeremy.wang (2011/9/7) ++ * Desc: Get Current MIE Event That We Have Saved in Interrupt Mode ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ++ * @return U16_T : Current MIE Event ++ ----------------------------------------------------------------------------------------------------------*/ ++U16_T Hal_CARD_INT_GetMIEEvent(IPEmType eIP) ++{ ++ return gu16_MIEEvent_ForInt[eIP]; ++} ++ ++ ++//*********************************************************************************************************** ++// Interrupt Handler Function ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++static DECLARE_WAIT_QUEUE_HEAD(fcie1_mieint_wait); ++static DECLARE_WAIT_QUEUE_HEAD(fcie2_mieint_wait); ++static DECLARE_WAIT_QUEUE_HEAD(fcie3_mieint_wait); ++ ++#endif ++//########################################################################################################### ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_WaitMIEEvent ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Set WaitQueue Handler to Wait MIE Event ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u16ReqEvent : MIE Event for waiting ++ * @param u32WaitMs : Waiting Time (ms) ++ * ++ * @return BOOL_T : TRUE (Success), FALSE (Timeout) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_INT_WaitMIEEvent(IPEmType eIP, U16_T u16ReqEvent, U32_T u32WaitMs) ++{ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ if(eIP==EV_IP_FCIE1) ++ wait_event_timeout(fcie1_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ else if((eIP==EV_IP_FCIE2)) ++ wait_event_timeout(fcie2_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ else if((eIP==EV_IP_FCIE3)) ++ wait_event_timeout(fcie3_mieint_wait, ((gu16_MIEEvent_ForInt[eIP]& u16ReqEvent) == u16ReqEvent) || gb_StopWaitMIE[eIP], msecs_to_jiffies(u32WaitMs+WT_INT_RISKTIME)); ++ ++ ++ if((gu16_MIEEvent_ForInt[eIP] & u16ReqEvent) != u16ReqEvent) ++ return FALSE; ++ ++ return TRUE; ++//########################################################################################################### ++#endif ++ ++ /****** Not Support (Ex: D_OS_ARCH = D_OS_UBOOT) ******/ ++ return FALSE; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_StopWaitMIEEventCtrl ++ * @author jeremy.wang (2011/12/20) ++ * Desc: Stop Wait MIE Event to Avoid Long Time Waiting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_INT_StopWaitMIEEventCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ gb_StopWaitMIE[eIP] = bEnable; ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ if(gb_StopWaitMIE[eIP]) ++ { ++ /****** Break Current Wait Event *******/ ++ if(eIP==EV_IP_FCIE1) ++ wake_up(&fcie1_mieint_wait); ++ else if((eIP==EV_IP_FCIE2)) ++ wake_up(&fcie2_mieint_wait); ++ else if((eIP==EV_IP_FCIE3)) ++ wake_up(&fcie3_mieint_wait); ++ } ++#endif ++//########################################################################################################### ++ ++} ++ ++ ++//*********************************************************************************************************** ++// Interrupt Function ++//*********************************************************************************************************** ++ ++//########################################################################################################### ++#if(D_OS == D_OS__LINUX) ++//########################################################################################################### ++#include ++#include "../inc/ms_sdmmc_lnx.h" ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_INT_MIE ++ * @author jeremy.wang (2012/2/13) ++ * Desc: ++ * ++ * @param irq : ++ * @param p_dev_id : ++ * ++ * @return irqreturn_t : ++ ----------------------------------------------------------------------------------------------------------*/ ++irqreturn_t Hal_CARD_INT_MIE(int irq, void *p_dev_id) ++{ ++ irqreturn_t irq_t = IRQ_NONE; ++ IntSourceStruct* pstIntSource = p_dev_id; ++ IPEmType eIP = pstIntSource->eIP; ++ //IntCardEmType eCardInt = pstIntSource->eCardInt; ++ struct ms_sdmmc_slot *p_sdmmc_slot = pstIntSource->p_data; ++ ++ if(_CARD_INT_DetectSDIOInt(eIP)) ++ { ++ mmc_signal_sdio_irq(p_sdmmc_slot->mmc); ++ irq_t = IRQ_HANDLED; ++ } ++ ++ if(_CARD_INT_SaveMIEEvent(eIP)) ++ { ++ if(eIP == EV_IP_FCIE1) ++ wake_up(&fcie1_mieint_wait); ++ else if((eIP==EV_IP_FCIE2)) ++ wake_up(&fcie2_mieint_wait); ++ else if((eIP==EV_IP_FCIE3)) ++ wake_up(&fcie3_mieint_wait); ++ ++ irq_t = IRQ_HANDLED; ++ } ++ ++ return irq_t; ++} ++ ++ ++//########################################################################################################### ++#endif +diff --git a/drivers/mstar/sdmmc/src/hal_card_platform_c3.c b/drivers/mstar/sdmmc/src/hal_card_platform_c3.c +new file mode 100644 +index 00000000..2c26dbf2 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_platform_c3.c +@@ -0,0 +1,1115 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_msw8x68.c ++ * @author jeremy.wang (2010/10/14) ++ * Desc: ++ * The platform Setting of all cards will run here. ++ * Every Project will have XX project name for different hal_card_platform_XX.c files ++ * The goal is that we don't need to change "other" HAL Level code. ++ * ++ * The limitations were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API level, not driver flow process. ++ * (3) IP Init, PADPath, PADInit, Clock and Power function belong to here. ++ * (4) Timer Setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Platform Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00) ++#define A_CHIPGPIO1_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80D00) ++#define A_CHIPGPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81580) ++#define A_CLKGEN0_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80580) ++#define A_PMSLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700) ++#define A_PMGPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780) ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 24000000 ++#define CLK1_9 19636000 //19.63MHz ++#define CLK1_8 17615000 //17.61MHz ++#define CLK1_7 14400000 //14.40MHz ++#define CLK1_6 12000000 ++#define CLK1_5 300000 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 36000000 ++#define CLK2_C 30750000 ++#define CLK2_B 27000000 ++#define CLK2_A 21500000 ++#define CLK2_9 20000000 ++#define CLK2_8 18000000 ++#define CLK2_7 15500000 ++#define CLK2_6 12000000 ++#define CLK2_5 300000 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 24000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile BusTimingEmType ge_BusTiming[3] = {0}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPOnceSetting ++ * @author jeremy.wang (2015/7/17) ++ * Desc: IP once setting , it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPOnceSetting(IPEmType eIP) ++{ ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x00), BIT00_T); //reg_all_pad_in => Off ++ ++} ++ ++ ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPBeginSetting ++ * @author jeremy.wang (2015/7/29) ++ * Desc: IP begin setting before every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPBeginSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ //ge_BusTiming[eIP]; ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x10), BIT12_T); //SDIO flash macro bypass mode => ON ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x10), BIT12_T); //SDIO flash macro bypass mode ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPEndSetting ++ * @author jeremy.wang (2015/7/29) ++ * Desc: IP end setting after every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPEndSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitPADPin ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Init PAD Pin Status ( pull enable, pull up/down, driving strength) ++ * ++ * @param ePAD : PAD ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitPADPin(PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ ++ if(ePAD == EV_PAD1) //Pad SD0 ++ { ++ ++ //SD0_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT02_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT02_T); //pull down ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT02_T); //drv:0 ++ ++ //SD0_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT14_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT14_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT14_T); //drv:0 ++ ++ //SD0_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT00_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT00_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT00_T); //drv:0 ++ ++ //SD0_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT15_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT15_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT15_T); //drv:0 ++ ++ //SD0_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT13_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT13_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT13_T); //drv:0 ++ ++ //SD0_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT12_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT12_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT12_T); //drv:0 ++ ++ ++ } ++ else if(ePAD==EV_PAD2) //Pad SD2 ++ { ++ //SD2_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT10_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT10_T); //pull down ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT10_T); //drv:0 ++ ++ //SD2_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT09_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT09_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT09_T); //drv:0 ++ ++ //SD2_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT08_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT08_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT08_T); //drv:0 ++ ++ //SD2_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT07_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT07_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT07_T); //drv:0 ++ ++ //SD2_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT06_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT06_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT06_T); //drv:0 ++ ++ //SD2_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT05_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT05_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT05_T); //drv:0 ++ ++ } ++ else if(ePAD==EV_PAD3) ++ { ++ //SD2_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1C), BIT03_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT03_T); //pull down ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x18), BIT03_T); //drv:0 ++ ++ //SD2_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT09_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT09_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT09_T); //drv:0 ++ ++ //SD2_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT11_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT11_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT11_T); //drv:0 ++ ++ //SD2_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT10_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT10_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT10_T); //drv:0 ++ ++ //SD2_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT08_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT08_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT08_T); //drv:0 ++ ++ //SD2_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1B), BIT07_T); //pe en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT07_T); //pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x17), BIT07_T); //drv:0 ++ ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADToPortPath ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Set PAD to connect IP Port ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param ePort : Port (But FCIE5 use it to decide FCIE or SDIO IP) ++ * @param ePAD : PAD ++ * @param bTwoCard : 1-bit two cards or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADToPortPath(IPEmType eIP, PortEmType ePort, PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ SET_CARD_PORT(eIP, ePort); ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ if(ePort == EV_PORT_SDIO1) ++ { ++ if(ePAD == EV_PAD1) //Pad SD0 ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x02), BIT00_T); //sdio mode0 selection ++ } ++ } ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ if(ePort == EV_PORT_SDIO1) ++ { ++ if(ePAD == EV_PAD2) //Pad SD2 ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x02), BIT04_T); //sdio mode2 selection ++ } ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ if(ePort == EV_PORT_SDIO1) ++ { ++ if(ePAD == EV_PAD3) //Pad SD2 ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x02), BIT02_T); //sdio mode1 selection ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x02), BIT03_T); //sdio mode1 selection ++ } ++ } ++ ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PullPADPin ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Pull PAD Pin for Special Purpose (Avoid Power loss.., Save Power) ++ * ++ * @param ePAD : PAD ++ * @param ePinPull : Pull up/Pull down ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PullPADPin(PADEmType ePAD, PinPullEmType ePinPull, BOOL_T bTwoCard) ++{ ++ ++ if(ePAD == EV_PAD1) //PAD_SD0 ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ //SD0_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT00_T); //pull down ++ ++ //SD0_D1, SD0_CMD, SD0_D2, SD0_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT15_T|BIT14_T|BIT13_T|BIT12_T); //pull down ++ ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ //SD0_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT00_T); //pull up ++ ++ //SD0_D1, SD0_CMD, SD0_D2, SD0_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT15_T|BIT14_T|BIT13_T|BIT12_T); //pull up ++ ++ } ++ ++ } ++ else if(ePAD == EV_PAD2) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ //SD2_CMD, SD2_D0, SD2_D1, SD2_D2, SD2_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT09_T|BIT08_T|BIT07_T|BIT06_T|BIT05_T); //pull down ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ ++ //SD2_CMD, SD2_D0, SD2_D1, SD2_D2, SD2_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1E), BIT09_T|BIT08_T|BIT07_T|BIT06_T|BIT05_T); //pull up ++ } ++ } ++ else if(ePAD == EV_PAD3) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ //SD3_D0, SD3_D1, SD3_CMD, SD3_D2, SD3_D3 ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT11_T|BIT10_T|BIT09_T|BIT08_T|BIT07_T); //pull down ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ //SD3_D0, SD3_D1, SD3_CMD, SD3_D2, SD3_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x1D), BIT11_T|BIT10_T|BIT09_T|BIT08_T|BIT07_T); //pull up ++ } ++ } ++ ++ ++ ++ ++} ++ ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetClock ++ * @author jeremy.wang (2015/7/23) ++ * Desc: Set Clock Level by Real Clock from IP ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ClkFromIPSet : Clock Value From IP Source Set ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetClock(IPEmType eIP, U32_T u32ClkFromIPSet) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT01_T|BIT00_T); //[1]: Clk_i [0]: Clk_g ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT05_T|BIT04_T|BIT03_T|BIT02_T); //[5:2]: Clk_sel ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x1A), BIT00_T); //spread clk source gating ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT15_T|BIT09_T|BIT08_T|BIT07_T|BIT06_T|BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT04_T); //4 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT03_T); //2 ++ break; ++ case CLK1_A: //24000KHz ++ break; ++ case CLK1_9: //19630KHz ==> spread clock ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT05_T|BIT04_T); //12: spd clk ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x1A), BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[3:2]: Spd Clk_sel [1]: Spd Clk_i [0]: Spd Clk_g ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT15_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT03_T|BIT01_T|BIT00_T); //11 ++ break; ++ ++ case CLK1_8: //17610KHz ==> spread clock ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT05_T|BIT04_T); //12: spd clk ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x1A), BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[3:2]: Spd Clk_sel [1]: Spd Clk_i [0]: Spd Clk_g ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT15_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT03_T|BIT02_T|BIT00_T); //13 ++ break; ++ ++ case CLK1_7: //14400KHz ==> spread clock ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT05_T|BIT04_T); //12: spd clk ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x1A), BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[3~2]: Spd Clk_sel [1]: Spd Clk_i [0]: Spd Clk_g ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT15_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x65), BIT03_T|BIT02_T|BIT01_T|BIT00_T); //15 ++ break; ++ ++ case CLK1_6: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT02_T); //1 ++ break; ++ ++ case CLK1_5: ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT05_T|BIT04_T|BIT02_T); //13 ++ break; ++ ++ /*case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT01_T|BIT00_T); //[1]: clk_i [0]: Clk_g ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT06_T|BIT05_T|BIT04_T|BIT03_T|BIT02_T); //[6:2]: clk sel ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x0E), BIT01_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK2_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT05_T); //8 ++ break; ++ case CLK2_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ case CLK2_D: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK2_C: //30750KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK2_B: //27000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT04_T); //4 ++ break; ++ case CLK2_A: //21500KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK2_9: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT06_T|BIT04_T|BIT03_T|BIT02_T); //23 ++ break; ++ case CLK2_8: //18000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT06_T|BIT04_T|BIT03_T); //22 ++ break; ++ case CLK2_7: //15500KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT06_T|BIT04_T|BIT02_T); //21 ++ break; ++ case CLK2_6: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT03_T); //2 ++ break; ++ case CLK2_5: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x6A), BIT05_T|BIT04_T|BIT03_T); //14 ++ break; ++ ++ /*case CLK2_4: ++ case CLK_3: ++ break; ++ case CLK2_2: ++ break; ++ case CLK2_1: ++ break; ++ case CLK2_0: ++ break;*/ ++ ++ } ++ ++ ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT09_T|BIT08_T); //[1]: clk_i [0]: Clk_g ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT13_T|BIT12_T|BIT11_T|BIT10_T); //[6:2] : select clock source ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK3_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT12_T|BIT11_T); //6 ++ break; ++ case CLK3_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT12_T|BIT10_T); //5 ++ break; ++ case CLK3_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT12_T); //4 ++ break; ++ case CLK3_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT11_T|BIT10_T); //3 ++ break; ++ case CLK3_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT11_T); //2 ++ break; ++ case CLK3_A: //24000KHz ++ break; ++ case CLK3_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT10_T); //1 ++ break; ++ case CLK3_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN0_BANK,0x69), BIT13_T|BIT12_T|BIT10_T); //13 ++ break; ++ ++ /*case CLK2_4: ++ case CLK_3: ++ break; ++ case CLK2_2: ++ break; ++ case CLK2_1: ++ break; ++ case CLK2_0: ++ break;*/ ++ ++ } ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_FindClockSetting ++ * @author jeremy.wang (2015/7/20) ++ * Desc: Find Real Clock Level Setting by Reference Clock ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ReffClk : Reference Clock Value ++ * @param u8PassLevel : Pass Level to Clock Speed ++ * @param u8DownLevel : Down Level to Decrease Clock Speed ++ * ++ * @return U32_T : Real Clock ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_FindClockSetting(IPEmType eIP, U32_T u32ReffClk, U8_T u8PassLevel, U8_T u8DownLevel) ++{ ++ U8_T u8LV = u8PassLevel; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ /****** For decrease clock speed******/ ++ if( (u8DownLevel) && (u32RealClk) && ((u8LV+u8DownLevel)<=15) ) ++ { ++ if(u32ClkArr[eIP][u8LV+u8DownLevel]>0) //Have Level for setting ++ u32RealClk = u32ClkArr[eIP][u8LV+u8DownLevel]; ++ } ++ ++ return u32RealClk; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetBusTiming ++ * @author jeremy.wang (2015/7/20) ++ * Desc: Platform Setting for different Bus Timing ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming) ++{ ++ ge_BusTiming[eIP] = eBusTiming; ++} ++ ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADPower ++ * @author jeremy.wang (2015/7/30) ++ * Desc: Set PAD power to different voltage ++ * ++ * @param ePAD : PAD ++ * @param ePADVdd : NORMAL/MIN/LOW Voltage Level ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADPower(PADEmType ePAD, PADVddEmType ePADVdd) ++{ ++ ++ if(ePAD == EV_PAD1) //Pad SD0 ++ { ++ } ++ else if(ePAD == EV_PAD2) //PAD_SD2 ++ { ++ ++ } ++ else if(ePAD == EV_PAD3) ++ { ++ if(ePADVdd == EV_NORVOL) ++ { ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK,0x20), BIT00_T); //reg_ldovio3_a_en ++ } ++ } ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOn ++ * @author jeremy.wang (2015/7/29) ++ * Desc: Power ON Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms for stable power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOn(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ if(ePAD==EV_PAD1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT03_T); //output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT03_T); //output 0 ++ } ++ else if(ePAD==EV_PAD2) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x13), BIT01_T); //reg_p1_enable_b1 = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x15), BIT01_T); //reg_pwm1_mode = 0 ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO_BANK, 0x05), BIT01_T); //output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO_BANK, 0x05), BIT00_T); //output mode 0 ++ } ++ ++ Hal_Timer_mDelay(u16DelayMs); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOff ++ * @author jeremy.wang (2015/7/29) ++ * Desc: Power Off Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms to confirm no any spower ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOff(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ ++ if(ePAD==EV_PAD1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT03_T); //output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT03_T); //output 1 ++ } ++ else if(ePAD==EV_PAD2) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x13), BIT01_T); //reg_p1_enable_b1 = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO1_BANK, 0x15), BIT01_T); //reg_pwm1_mode = 0 ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPGPIO_BANK, 0x05), BIT01_T); //output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPGPIO_BANK, 0x05), BIT00_T); //output mode 1 ++ ++ } ++ ++ Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitGPIO ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Init GPIO Setting for CDZ or other GPIO (Pull high/low and driving, base SD/GPIO mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bEnable : Enable GPIO or disable GPIO to avoid loss power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitGPIO(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bEnable) ++{ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x00), BIT12_T); //[1] cdz mode, [0] sd gpio mode ++ ++ if(bEnable) ++ { ++ //SD0_CDZ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT04_T|BIT03_T); //pull up //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT02_T); //drv:0 ++ } ++ else ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT03_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT04_T|BIT02_T); //pull down //drv:0 ++ } ++ } ++ else if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x00), BIT14_T); //[1] cdz gpio mode, [0] sd gpio mode ++ if(bEnable) ++ { ++ //SD2_CDZ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT10_T|BIT09_T); //pull up //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT08_T); //drv:0 ++ } ++ else ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT09_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT10_T|BIT08_T); //pull down //drv:0 ++ } ++ } ++ else if( eGPIO==EV_GPIO3 ) //EV_GPIO3 for Slot2 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x00), BIT13_T); //[1] cdz gpio mode, [0] sd gpio mode ++ if(bEnable) ++ { ++ //SD1_CDZ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT07_T|BIT06_T); //pull up //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT05_T); //drv:0 ++ } ++ else ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT06_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x01), BIT07_T|BIT05_T); //pull down //drv:0 ++ } ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO input mode value (Include input mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : Insert (TRUE) or Remove (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GetGPIOState(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ if(CARD_REG(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x09)) & BIT00_T) // CDZ SD0 ++ return (FALSE); ++ else ++ return (TRUE); ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ if(CARD_REG(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x09)) & BIT02_T) // CDZ SD2 ++ return (FALSE); ++ else ++ return (TRUE); ++ } ++ if( eGPIO==EV_GPIO3 ) //EV_GPIO2 for Slot 2 ++ { ++ if(CARD_REG(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x09)) & BIT01_T) // CDZ SD1 ++ return (FALSE); ++ else ++ return (TRUE); ++ } ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO output mode value (Include output mode setting), it's for SDIO WIFI control using ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bOutputState : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOState(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bOutputState) ++{ ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT00_T); //PMU_GPIO_OUT_EN ++ ++ if(bOutputState) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT00_T); //PMU_GPIO_OUT=1 ++ } ++ else ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT00_T); //PMU_GPIO_OUT=0 ++ } ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT02_T); //PMU_GPIO_OUT_EN ++ ++ if(bOutputState) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT02_T); //PMU_GPIO_OUT=1 ++ } ++ else ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT02_T); //PMU_GPIO_OUT=0 ++ } ++ } ++ if( eGPIO==EV_GPIO3 ) //EV_GPIO2 for Slot 1 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT01_T); //PMU_GPIO_OUT_EN ++ if(bOutputState) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT01_T); //PMU_GPIO_OUT=1 ++ } ++ else ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT01_T); //PMU_GPIO_OUT=0 ++ } ++ ++ } ++ ++ // Add a 500ms Delay after card removing to avoid the next card inserting issue ++ if(bOutputState==1) ++ { ++ Hal_Timer_mSleep(500); ++ } ++ else // For 0->1, 1->0 stable ++ { ++ Hal_Timer_mSleep(1); ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIONum ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO number for special platform (like Linux) to use it get irq number ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return U32_T : GPIO number ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_GetGPIONum(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ S32_T s32GPIO = -1; ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ //s32GPIO = DrvPadmuxGetGpio(IO_CHIP_INDEX_SD_CDZ); ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ } ++ ++ if(s32GPIO>0) ++ return (U32_T)s32GPIO; ++ else ++ return 0; ++} ++ ++ ++#if (D_OS == D_OS__LINUX) ++#include ++#include ++#endif ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOIntAttr ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO Interrupt Attribute (Option 1..5), it could design for different requirement ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param eGPIOOPT : Option1/Option2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOIntAttr(GPIOEmType eGPIO, PADEmType ePAD, GPIOOptEmType eGPIOOPT) ++{ ++ ++#if (D_OS == D_OS__LINUX) ++ struct irq_data sd_irqdata; ++ struct irq_chip *chip; ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ sd_irqdata.irq = INT_PMU_SD_DETECT0; ++ chip = irq_get_chip(sd_irqdata.irq); ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) //clear interrupt ++ { ++ chip->irq_ack(&sd_irqdata); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x75), BIT00_T); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) //sd polarity _HI Trig for remove ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)); ++// ms_irq_set_polarity(&sd_irqdata , 0); ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x7B), BIT00_T); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) //sd polarity _LO Trig for insert ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_RISING|IRQ_TYPE_LEVEL_LOW)); ++// ms_irq_set_polarity(&sd_irqdata , 1); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x7B), BIT00_T); ++ ++ } ++ ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ sd_irqdata.irq = INT_PMU_SD_DETECT2; ++ chip = irq_get_chip(sd_irqdata.irq); ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) ++ { ++ chip->irq_ack(&sd_irqdata); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x75), BIT02_T); //clear interrupt ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)); ++// ms_irq_set_polarity(&sd_irqdata , 0); ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x7B), BIT02_T); //sd polarity _HI Trig for remove ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_RISING|IRQ_TYPE_LEVEL_LOW)); ++// ms_irq_set_polarity(&sd_irqdata , 1); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x7B), BIT02_T); //sd polarity _LO Trig for insert ++ } ++ } ++ else if(eGPIO==EV_GPIO3) ++ { ++ sd_irqdata.irq = INT_PMU_SD_DETECT1; ++ chip = irq_get_chip(sd_irqdata.irq); ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) ++ { ++ chip->irq_ack(&sd_irqdata); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)); ++// ms_irq_set_polarity(&sd_irqdata , 0); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_RISING|IRQ_TYPE_LEVEL_LOW)); ++// ms_irq_set_polarity(&sd_irqdata , 1); ++ } ++ } ++ ++ ++#endif ++} ++ ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GPIOIntFilter ++ * @author jeremy.wang (2016/12/15) ++ * Desc: GPIO Interrupt Filter, it could design to filter GPIO Interrupt (Many sources belong to the same one) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GPIOIntFilter(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO2 ) ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO3 ) ++ { ++ return (TRUE); ++ } ++ ++ return (FALSE); ++} ++ ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr) ++{ ++ return u32Addr; ++} +diff --git a/drivers/mstar/sdmmc/src/hal_card_platform_c4.c b/drivers/mstar/sdmmc/src/hal_card_platform_c4.c +new file mode 100644 +index 00000000..d896223a +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_platform_c4.c +@@ -0,0 +1,887 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_c4.c ++ * @author jeremy.wang (2010/10/14) ++ * Desc: ++ * The platform Setting of all cards will run here. ++ * Every Project will have XX project name for different hal_card_platform_XX.c files ++ * The goal is that we don't need to change "other" HAL Level code. ++ * ++ * The limitations were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API level, not driver flow process. ++ * (3) IP Init, PAD setting, clock setting and power setting belong to here. ++ * (4) Timer Setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Platform Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_PAD_TOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0580) ++#define A_PMU_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x1F80) ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x0F00) ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++ ++#define CLK1_F 48000000 ++#define CLK1_E 40000000 ++#define CLK1_D 36000000 ++#define CLK1_C 32000000 ++#define CLK1_B 27625000 ++#define CLK1_A 24000000 ++#define CLK1_9 18420000 //18.42MHz ++#define CLK1_8 15790000 //15.79MHz ++#define CLK1_7 12000000 //12MHz ++#define CLK1_6 300000 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 36000000 ++#define CLK2_C 30750000 ++#define CLK2_B 27000000 ++#define CLK2_A 21500000 ++#define CLK2_9 20000000 ++#define CLK2_8 18000000 ++#define CLK2_7 15500000 ++#define CLK2_6 12000000 ++#define CLK2_5 300000 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 24000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile BusTimingEmType ge_BusTiming[3] = {0}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitIPOnce ++ * @author jeremy.wang (2012/6/7) ++ * Desc: IP Once Setting , it's about platform setting. ++ * ++ * @param eIP : ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPOnceSetting(IPEmType eIP) ++{ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x00), BIT01_T); //reg_all_pad_in => Close ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT03_T); //reg_all_pad_in => Close ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitSetting ++ * @author jeremy.wang (2011/12/1) ++ * Desc: IP Begin Setting before every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPBeginSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++ ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPEndSetting ++ * @author jeremy.wang (2012/5/3) ++ * Desc: IP End Setting after every operation, it's about platform setting. ++ * ++ * @param eIP : ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPEndSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitPADPin ++ * @author jeremy.wang (2011/12/1) ++ * Desc: Init PAD Pin Status ( pull enable, pull up/down, driving strength) ++ * ++ * @param ePAD : PAD ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitPADPin(PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ ++ if(ePAD == EV_PAD1) //Pad SD0 ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x07), BIT13_T|BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD, CLK => pull en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x08), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T); //D3, D2, D1, D0, CMD => pull up ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x08), BIT00_T); //CLK => pull down ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x07), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD, CLK => drv: 0 ++ ++#if (D_OS == D_OS__UBOOT) ++ //SD0_CDZ for IP CDZ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7C), BIT07_T); //[1] cdz gpio mode, [0] sd gpio mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT01_T|BIT00_T); //pull up //ps en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT02_T); //drv: 0 ++#endif ++ ++ } ++ else if(ePAD==EV_PAD2) //Pad SD2 ++ { ++ ++ } ++ else if(ePAD==EV_PAD3) ++ { ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADToPortPath ++ * @author jeremy.wang (2011/12/1) ++ * Desc: Set PAD to connect IP Port ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param ePort : IP Port ++ * @param ePAD : PAD (Could Set NOPAD for 1-bit two cards) ++ * @param bTwoCard : 1-bit two cards or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADToPortPath(IPEmType eIP, PortEmType ePort, PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ SET_CARD_PORT(eIP, ePort); ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ if(ePort == EV_PORT_SDIO1) ++ { ++ if(ePAD == EV_PAD1) //Pad SD0 ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x01), BIT10_T); //reg_sdio_mode = 1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x01), BIT11_T); ++ } ++ } ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ if(ePort == EV_PORT_SDIO1) ++ { ++ if(ePAD == EV_PAD2) //Pad SD2 ++ { ++ } ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ if(ePort == EV_PORT_SDIO1) ++ { ++ if(ePAD == EV_PAD3) //Pad SD2 ++ { ++ } ++ } ++ ++ } ++ ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PullPADPin ++ * @author jeremy.wang (2011/12/1) ++ * Desc: Pull PAD Pin for Special Purpose (Avoid Power loss.., Save Power) ++ * ++ * @param ePAD : PAD ++ * @param ePinPull : Pull up/Pull down ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PullPADPin(PADEmType ePAD, PinPullEmType ePinPull, BOOL_T bTwoCard) ++{ ++ ++ if(ePAD == EV_PAD1) //PAD_SD0 ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x08), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T); //D3, D2, D1, D0, CMD => pull down ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PAD_TOP_BANK, 0x08), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T); //D3, D2, D1, D0, CMD => pull up ++ ++ } ++ ++ } ++ else if(ePAD == EV_PAD2) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ ++ } ++ } ++ else if(ePAD == EV_PAD3) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ ++ } ++ } ++ ++ ++ ++ ++} ++ ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetClock ++ * @author jeremy.wang (2011/12/14) ++ * Desc: Set Clock Level by Real Clock from IP ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32KClkFromIP : Clock Value From IP Source Set ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetClock(IPEmType eIP, U32_T u32ClkFromIPSet) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T|BIT09_T|BIT08_T|BIT07_T|BIT06_T); //[10:8]: Clk_Sel [7]: Clk_i [6]: Clk_g ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT10_T|BIT09_T|BIT08_T|BIT07_T|BIT06_T|BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T|BIT09_T); //6 ++ break; ++ case CLK1_E: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T|BIT08_T); //5 ++ break; ++ case CLK1_D: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T); //4 ++ break; ++ case CLK1_C: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT09_T|BIT08_T); //3 ++ break; ++ case CLK1_B: //27625KHz ==> spread clock ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T|BIT09_T|BIT08_T); //7: spd clk ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT03_T); //4 ++ break; ++ case CLK1_A: //24000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT09_T); //2 ++ break; ++ case CLK1_9: //18420KHz ==> spread clock ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T|BIT09_T|BIT08_T); //7: spd clk ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT03_T|BIT02_T); //6 ++ break; ++ ++ case CLK1_8: //15790KHz ==> spread clock ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT10_T|BIT09_T|BIT08_T); //7: spd clk ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT00_T); ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x30), BIT03_T|BIT02_T|BIT01_T); //7 ++ break; ++ ++ case CLK1_7: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK,0x25),BIT08_T); //0 ++ break; ++ ++ case CLK1_6: //300KHz ++ break; ++ ++ /* ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ ++ switch(u32ClkFromIPSet) ++ { ++ /* ++ case CLK2_F: //48000KHz ++ break; ++ case CLK2_E: //43200KHz ++ break; ++ case CLK2_D: //36000KHz ++ break; ++ case CLK2_C: //30750KHz ++ break; ++ case CLK2_B: //27000KHz ++ break; ++ case CLK2_A: //21500KHz ++ break; ++ case CLK2_9: //20000KHz ++ break; ++ case CLK2_8: //18000KHz ++ break; ++ case CLK2_7: //15500KHz ++ break; ++ case CLK2_6: //12000KHz ++ break; ++ case CLK2_5: //300KHz ++ break; ++ case CLK2_4: ++ break; ++ case CLK_3: ++ break; ++ case CLK2_2: ++ break; ++ case CLK2_1: ++ break; ++ case CLK2_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ switch(u32ClkFromIPSet) ++ { ++ /* ++ case CLK3_F: //48000KHz ++ break; ++ case CLK3_E: //43200KHz ++ break; ++ case CLK3_D: //40000KHz ++ break; ++ case CLK3_C: //36000KHz ++ break; ++ case CLK3_B: //32000KHz ++ break; ++ case CLK3_A: //24000KHz ++ break; ++ case CLK3_9: //12000KHz ++ break; ++ case CLK3_8: //300KHz ++ break; ++ case CLK2_4: ++ break; ++ case CLK_3: ++ break; ++ case CLK2_2: ++ break; ++ case CLK2_1: ++ break; ++ case CLK2_0: ++ break;*/ ++ ++ } ++ ++ } ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_FindClockSetting ++ * @author jeremy.wang (2012/5/22) ++ * Desc: Find Real Clock Level Setting by Reference Clock ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ReffClk : Reference Clock Value ++ * @param u8PassLevel : Pass Level to Clock Speed ++ * @param u8DownLevel : Down Level to Decrease Clock Speed ++ * ++ * @return U32_T : Real Clock ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_FindClockSetting(IPEmType eIP, U32_T u32ReffClk, U8_T u8PassLevel, U8_T u8DownLevel) ++{ ++ U8_T u8LV = u8PassLevel; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ /****** For decrease clock speed******/ ++ if( (u8DownLevel) && (u32RealClk) && ((u8LV+u8DownLevel)<=15) ) ++ { ++ if(u32ClkArr[eIP][u8LV+u8DownLevel]>0) //Have Level for setting ++ u32RealClk = u32ClkArr[eIP][u8LV+u8DownLevel]; ++ } ++ ++ return u32RealClk; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetBusTiming ++ * @author jeremy.wang (2015/1/20) ++ * Desc: Platform Setting for different Bus Timing ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming) ++{ ++ ge_BusTiming[eIP] = eBusTiming; ++} ++ ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADPower ++ * @author jeremy.wang (2012/1/4) ++ * Desc: Set PAD Power to Different Voltage ++ * ++ * @param ePAD : PAD ++ * @param ePADVdd : LOW/MIDDLE/HIGH Voltage Level ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADPower(PADEmType ePAD, PADVddEmType ePADVdd) ++{ ++ ++ if(ePAD == EV_PAD1) //Pad SD0 ++ { ++ } ++ else if(ePAD == EV_PAD2) //PAD_SD2 ++ { ++ ++ } ++ else if(ePAD == EV_PAD3) ++ { ++ if(ePADVdd == EV_NORVOL) ++ { ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK,0x20), BIT00_T); //reg_ldovio3_a_en ++ } ++ } ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOn ++ * @author jeremy.wang (2011/12/13) ++ * Desc: Power on Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms for Stable Power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOn(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ if(ePAD==EV_PAD1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7E), BIT00_T); //CARD_POWER_CTL1 //output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7D), BIT00_T); // output:0 ++ ++ } ++ else if(ePAD==EV_PAD2) ++ { ++ } ++ ++ Hal_Timer_mDelay(u16DelayMs); ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOff ++ * @author jeremy.wang (2011/12/13) ++ * Desc: Power off Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms to Confirm No Power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOff(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ ++ if(ePAD==EV_PAD1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7E), BIT00_T); //CARD_POWER_CTL1 //output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7D), BIT00_T); // output:1 ++ } ++ else if(ePAD==EV_PAD2) ++ { ++ } ++ ++ Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitGPIO ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Init GPIO Setting for CDZ or other GPIO (Pull high/low and driving, base SD/GPIO mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bEnable : Enable GPIO or disable GPIO to avoid loss power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitGPIO(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bEnable) ++{ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7C), BIT07_T); //[1] cdz mode, [0] sd gpio mode ++ ++ if(bEnable) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT01_T|BIT00_T); //pull up //ps en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT02_T); //drv: 0 ++ } ++ else ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT00_T); //pe en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7F), BIT02_T|BIT01_T); //drv: 0 //pull down ++ } ++ } ++ else if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ if(bEnable) ++ { ++ } ++ else ++ { ++ } ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO input mode value (Include input mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : Insert (TRUE) or Remove (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GetGPIOState(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ if(CARD_REG(GET_CARD_REG_ADDR(A_PMU_BANK, 0x04)) & BIT12_T) // CDZ SD0 ++ return (FALSE); ++ else ++ return (TRUE); ++ ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO1 for Slot 1 ++ { ++ } ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO output mode value (Include output mode setting), it's for SDIO WIFI control using ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bOutputState : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOState(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bOutputState) ++{ ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7E), BIT12_T); //PMU_GPIO_OUT_EN ++ ++ if(bOutputState) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7D), BIT12_T); //PMU_GPIO_OUT=1 ++ } ++ else ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMU_BANK, 0x7D), BIT12_T); //PMU_GPIO_OUT=0 ++ } ++ ++ } ++ ++ // Add a 500ms Delay after card removing to avoid the next card inserting issue ++ if(bOutputState==1) ++ { ++ Hal_Timer_mSleep(500); ++ } ++ else // For 0->1, 1->0 stable ++ { ++ Hal_Timer_mSleep(1); ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIONum ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO number for special platform (like Linux) to use it get irq number ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return U32_T : GPIO number ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_GetGPIONum(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ S32_T s32GPIO = -1; ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ //s32GPIO = DrvPadmuxGetGpio(IO_CHIP_INDEX_SD_CDZ); ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ } ++ ++ if(s32GPIO>0) ++ return (U32_T)s32GPIO; ++ else ++ return 0; ++} ++ ++ ++#if (D_OS == D_OS__LINUX) ++//#include ++#include ++#endif ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOIntAttr ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO Interrupt Attribute (Option 1..5), it could design for different requirement ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param eGPIOOPT : Option1/Option2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOIntAttr(GPIOEmType eGPIO, PADEmType ePAD, GPIOOptEmType eGPIOOPT) ++{ ++ ++#if (D_OS == D_OS__LINUX) ++ ++ struct irq_data sd_irqdata; ++ struct irq_chip *chip; ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ sd_irqdata.irq = INT_PMU_SD_DETECT; ++ chip = irq_get_chip(sd_irqdata.irq); ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) //clear interrupt ++ { ++ chip->irq_ack(&sd_irqdata); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) //sd polarity _HI Trig for remove ++ { ++ //ms_irq_set_polarity(&sd_irqdata , 0); //C4 Edge Trig, Don't need to set polarity ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) //sd polarity _LO Trig for insert ++ { ++ //ms_irq_set_polarity(&sd_irqdata , 1); //C4 Edge Trig, Don't need to set polarity ++ ++ } ++ ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) ++ { ++ } ++ ++ ++ } ++ ++#endif ++ ++} ++ ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GPIOIntFilter ++ * @author jeremy.wang (2016/12/15) ++ * Desc: GPIO Interrupt Filter, it could design to filter GPIO Interrupt (Many sources belong to the same one) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GPIOIntFilter(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO2 ) ++ { ++ return (TRUE); ++ } ++ ++ return (FALSE); ++} ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2012/6/7) ++ * Desc: ++ * ++ * @param u32Addr : ++ * ++ * @return U32_T : ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr) ++{ ++ return u32Addr; ++} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff --git a/drivers/mstar/sdmmc/src/hal_card_platform_iNF.c b/drivers/mstar/sdmmc/src/hal_card_platform_iNF.c +new file mode 100644 +index 00000000..84a457c6 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_platform_iNF.c +@@ -0,0 +1,849 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF.c ++ * @author jeremy.wang (2010/10/14) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00) ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00) ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700) ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780) ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00) ++#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900) ++ ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile BusTimingEmType ge_BusTiming[3] = {0}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPOnceSetting ++ * @author jeremy.wang (2015/7/17) ++ * Desc: IP once setting , it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPOnceSetting(IPEmType eIP) ++{ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); //reg_all_pad_in => Close ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_MCM_SC_GP_BANK, 0x09), 0xF000); //Test ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ //Enable Clock Source to avoid reset fail ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ //Enable Clock Source to avoid reset fail ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPBeginSetting ++ * @author jeremy.wang (2015/7/29) ++ * Desc: IP begin setting before every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPBeginSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPEndSetting ++ * @author jeremy.wang (2015/7/29) ++ * Desc: IP end setting after every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPEndSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitPADPin ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Init PAD Pin Status ( pull enable, pull up/down, driving strength) ++ * ++ * @param ePAD : PAD ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitPADPin(PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ ++ if( (ePAD == EV_PAD1) || (ePAD == EV_PAD3) ) //PAD_SD (Use PAD3 instead PAD1 (No power ctrl) ) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 ++ } ++ else if (ePAD == EV_PAD2) //PAD_NAND ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x30), BIT06_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADToPortPath ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Set PAD to connect IP Port ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param ePort : Port (But FCIE5 use it to decide FCIE or SDIO IP) ++ * @param ePAD : PAD ++ * @param bTwoCard : 1-bit two cards or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADToPortPath(IPEmType eIP, PortEmType ePort, PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ SET_CARD_PORT(eIP, ePort); ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ if( (ePAD == EV_PAD1) || (ePAD == EV_PAD3) ) //PAD_SD (Use PAD3 instead PAD1 (No power ctrl) ) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sd mode ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ ++ if(ePAD == EV_PAD2) //PAD_NAND ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd mode ++ } ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PullPADPin ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Pull PAD Pin for Special Purpose (Avoid Power loss.., Save Power) ++ * ++ * @param ePAD : PAD ++ * @param ePinPull : Pull up/Pull down ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PullPADPin(PADEmType ePAD, PinPullEmType ePinPull, BOOL_T bTwoCard) ++{ ++ ++ if( (ePAD == EV_PAD1) || (ePAD == EV_PAD3) ) //PAD_SD (Use PAD3 instead PAD1 (No power ctrl) ) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull dis ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull en ++ } ++ ++ } ++ else if(ePAD == EV_PAD2) ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull dis ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull en ++ } ++ ++ } ++} ++ ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetClock ++ * @author jeremy.wang (2015/7/23) ++ * Desc: Set Clock Level by Real Clock from IP ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ClkFromIPSet : Clock Value From IP Source Set ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetClock(IPEmType eIP, U32_T u32ClkFromIPSet) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ /* ++ case CLK1_7: ++ break; ++ case CLK1_6: ++ break; ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T); //8 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT02_T); //9 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT03_T); //10 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T); //12 ++ break; ++ /* ++ case CLK1_7: ++ break; ++ case CLK1_6: ++ break; ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ switch(u32ClkFromIPSet) ++ { ++ /* ++ case CLK3_F: //48000KHz ++ break; ++ case CLK3_E: //43200KHz ++ break; ++ case CLK3_D: //40000KHz ++ break; ++ case CLK3_C: //36000KHz ++ break; ++ case CLK3_B: //32000KHz ++ break; ++ case CLK3_A: //24000KHz ++ break; ++ case CLK3_9: //12000KHz ++ break; ++ case CLK3_8: //300KHz ++ break; ++ case CLK2_4: ++ break; ++ case CLK_3: ++ break; ++ case CLK2_2: ++ break; ++ case CLK2_1: ++ break; ++ case CLK2_0: ++ break;*/ ++ ++ } ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_FindClockSetting ++ * @author jeremy.wang (2015/7/20) ++ * Desc: Find Real Clock Level Setting by Reference Clock ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ReffClk : Reference Clock Value ++ * @param u8PassLevel : Pass Level to Clock Speed ++ * @param u8DownLevel : Down Level to Decrease Clock Speed ++ * ++ * @return U32_T : Real Clock ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_FindClockSetting(IPEmType eIP, U32_T u32ReffClk, U8_T u8PassLevel, U8_T u8DownLevel) ++{ ++ U8_T u8LV = u8PassLevel; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ /****** For decrease clock speed******/ ++ if( (u8DownLevel) && (u32RealClk) && ((u8LV+u8DownLevel)<=15) ) ++ { ++ if(u32ClkArr[eIP][u8LV+u8DownLevel]>0) //Have Level for setting ++ u32RealClk = u32ClkArr[eIP][u8LV+u8DownLevel]; ++ } ++ ++ return u32RealClk; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetBusTiming ++ * @author jeremy.wang (2015/7/20) ++ * Desc: Platform Setting for different Bus Timing ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming) ++{ ++ ge_BusTiming[eIP] = eBusTiming; ++} ++ ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADPower ++ * @author jeremy.wang (2015/7/30) ++ * Desc: Set PAD power to different voltage ++ * ++ * @param ePAD : PAD ++ * @param ePADVdd : NORMAL/MIN/LOW Voltage Level ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADPower(PADEmType ePAD, PADVddEmType ePADVdd) ++{ ++ ++ if(ePAD == EV_PAD1) ++ { ++ } ++ else if(ePAD == EV_PAD2) ++ { ++ ++ } ++ else if(ePAD == EV_PAD3) ++ { ++ if(ePADVdd == EV_NORVOL) ++ { ++ } ++ } ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOn ++ * @author jeremy.wang (2015/7/29) ++ * Desc: Power ON Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms for stable power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOn(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ if( (ePAD==EV_PAD1) || (ePAD==EV_PAD2) ) ++ { ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:0 ++ ++ } ++ else if(ePAD==EV_PAD3) ++ { ++ //Do Nothing (Because PAD3=PAD1 but no power ctrl) ++ } ++ ++ Hal_Timer_mDelay(u16DelayMs); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOff ++ * @author jeremy.wang (2015/7/29) ++ * Desc: Power Off Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms to confirm no any spower ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOff(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ if( (ePAD==EV_PAD1) || (ePAD==EV_PAD2) ) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:1 ++ ++ } ++ else if(ePAD==EV_PAD3) ++ { ++ //Do Nothing (Because PAD3=PAD1 but no power ctrl) ++ } ++ ++ Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitGPIO ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Init GPIO Setting for CDZ or other GPIO (Pull high/low and driving, base SD/GPIO mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bEnable : Enable GPIO or disable GPIO to avoid loss power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitGPIO(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bEnable) ++{ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ ++ if(bEnable) ++ { ++ //Could not control, always Pull EN/High ++ } ++ else ++ { ++ //Could not control, always Pull EN/High ++ } ++ } ++ else if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ if(bEnable) ++ { ++ } ++ else ++ { ++ } ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO input mode value (Include input mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : Insert (TRUE) or Remove (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GetGPIOState(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ U16_T u16Reg = 0; ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ u16Reg = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ ++ if(!u16Reg) //Low Active ++ return (TRUE); ++ else ++ return (FALSE); ++ ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ } ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO output mode value (Include output mode setting), it's for SDIO WIFI control using ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bOutputState : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOState(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bOutputState) ++{ ++ ++ /*if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT00_T); //PMU_GPIO_OUT_EN ++ ++ if(bOutputState) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT00_T); //PMU_GPIO_OUT=1 ++ } ++ else ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT00_T); //PMU_GPIO_OUT=0 ++ } ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ } ++ if( eGPIO==EV_GPIO3 ) //EV_GPIO2 for Slot 1 ++ { ++ } ++ ++ // Add a 500ms Delay after card removing to avoid the next card inserting issue ++ if(bOutputState==1) ++ { ++ Hal_Timer_mSleep(500); ++ } ++ else // For 0->1, 1->0 stable ++ { ++ Hal_Timer_mSleep(1); ++ }*/ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIONum ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO number for special platform (like Linux) to use it get irq number ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return U32_T : GPIO number ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_GetGPIONum(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ S32_T s32GPIO = -1; ++ ++ /*if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ //s32GPIO = DrvPadmuxGetGpio(IO_CHIP_INDEX_SD_CDZ); ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ }*/ ++ ++ if(s32GPIO>0) ++ return (U32_T)s32GPIO; ++ else ++ return 0; ++} ++ ++ ++#if (D_OS == D_OS__LINUX) ++#include ++#include "../../../mstar/include/infinity/irqs.h" ++#endif ++ ++ ++extern struct irq_chip gic_arch_extn; ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOIntAttr ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO Interrupt Attribute (Option 1..5), it could design for different requirement ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param eGPIOOPT : Option1/Option2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOIntAttr(GPIOEmType eGPIO, PADEmType ePAD, GPIOOptEmType eGPIOOPT) ++{ ++ ++#if (D_OS == D_OS__LINUX) ++ struct irq_data sd_irqdata; ++ struct irq_chip *chip; ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ sd_irqdata.irq = (INT_FIQ_SD_CDZ+32); ++ sd_irqdata.hwirq = (INT_FIQ_SD_CDZ+32); ++ ++#ifdef CONFIG_ARM_GIC ++ chip= &gic_arch_extn; ++#else ++ chip = irq_get_chip(sd_irqdata.irq); ++#endif ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) //clear interrupt ++ { ++ chip->irq_ack(&sd_irqdata); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x75), BIT00_T); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) //sd polarity _HI Trig for remove ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_FALLING|IRQ_TYPE_LEVEL_HIGH)); ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x7B), BIT00_T); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) //sd polarity _LO Trig for insert ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_RISING|IRQ_TYPE_LEVEL_LOW)); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x7B), BIT00_T); ++ } ++ ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ } ++ else if(eGPIO==EV_GPIO3) ++ { ++ ++ } ++#endif ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GPIOIntFilter ++ * @author jeremy.wang (2016/12/15) ++ * Desc: GPIO Interrupt Filter, it could design to filter GPIO Interrupt (Many sources belong to the same one) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GPIOIntFilter(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO2 ) ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO3 ) ++ { ++ return (TRUE); ++ } ++ ++ return (FALSE); ++} ++ ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr) ++{ ++ return u32Addr; ++} +diff --git a/drivers/mstar/sdmmc/src/hal_card_platform_iNF3.c b/drivers/mstar/sdmmc/src/hal_card_platform_iNF3.c +new file mode 100644 +index 00000000..1ed289b8 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_platform_iNF3.c +@@ -0,0 +1,1020 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_platform_iNF3.c ++ * @author jeremy.wang (2016/11/29) ++ * Desc: ++ * The platform setting of all cards will run here. ++ * Because register setting that doesn't belong to FCIE/SDIO may have different register setting at different projects. ++ * The goal is that we don't need to change "other" HAL_XX.c Level code. (Timing, FCIE/SDIO) ++ * ++ * The limitations were listed as below: ++ * (1) Each Project will have XX project name for different hal_card_platform_XX.c files. ++ * (2) IP init, PAD , clock, power and miu setting belong to here. ++ * (4) Timer setting doesn't belong to here, because it will be included by other HAL level. ++ * (5) FCIE/SDIO IP Reg Setting doesn't belong to here. ++ * (6) If we could, we don't need to change any code of hal_card_platform.h ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_platform.h" ++#include "../inc/hal_card_timer.h" ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Platform Register Basic Address ++//------------------------------------------------------------------------------------ ++#define A_CLKGEN_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81C00) ++#define A_PADTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x81E00) ++#define A_PM_SLEEP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00700) ++#define A_PM_GPIO_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x00780) ++#define A_CHIPTOP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x80F00) ++#define A_MCM_SC_GP_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89900) ++#define A_SC_GP_CTRL_BANK GET_CARD_REG_ADDR(A_RIU_BASE, 0x89980) ++ ++// Clock Level Setting (From High Speed to Low Speed) ++//----------------------------------------------------------------------------------------------------------- ++#define CLK1_F 48000000 ++#define CLK1_E 43200000 ++#define CLK1_D 40000000 ++#define CLK1_C 36000000 ++#define CLK1_B 32000000 ++#define CLK1_A 20000000 ++#define CLK1_9 12000000 ++#define CLK1_8 300000 ++#define CLK1_7 0 ++#define CLK1_6 0 ++#define CLK1_5 0 ++#define CLK1_4 0 ++#define CLK1_3 0 ++#define CLK1_2 0 ++#define CLK1_1 0 ++#define CLK1_0 0 ++ ++#define CLK2_F 48000000 ++#define CLK2_E 43200000 ++#define CLK2_D 40000000 ++#define CLK2_C 36000000 ++#define CLK2_B 32000000 ++#define CLK2_A 20000000 ++#define CLK2_9 12000000 ++#define CLK2_8 300000 ++#define CLK2_7 0 ++#define CLK2_6 0 ++#define CLK2_5 0 ++#define CLK2_4 0 ++#define CLK2_3 0 ++#define CLK2_2 0 ++#define CLK2_1 0 ++#define CLK2_0 0 ++ ++#define CLK3_F 48000000 ++#define CLK3_E 43200000 ++#define CLK3_D 40000000 ++#define CLK3_C 36000000 ++#define CLK3_B 32000000 ++#define CLK3_A 20000000 ++#define CLK3_9 12000000 ++#define CLK3_8 300000 ++#define CLK3_7 0 ++#define CLK3_6 0 ++#define CLK3_5 0 ++#define CLK3_4 0 ++#define CLK3_3 0 ++#define CLK3_2 0 ++#define CLK3_1 0 ++#define CLK3_0 0 ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static volatile BusTimingEmType ge_BusTiming[3] = {0}; ++ ++ ++//*********************************************************************************************************** ++// IP Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPOnceSetting ++ * @author jeremy.wang (2015/7/17) ++ * Desc: IP once setting , it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPOnceSetting(IPEmType eIP) ++{ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x50), BIT15_T); //reg_all_pad_in => Close ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_MCM_SC_GP_BANK, 0x09), 0xF000); //Test ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ //Enable Clock Source to avoid reset fail ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ //Enable Clock Source to avoid reset fail ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPBeginSetting ++ * @author jeremy.wang (2015/7/29) ++ * Desc: IP begin setting before every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPBeginSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_IPEndSetting ++ * @author jeremy.wang (2015/7/29) ++ * Desc: IP end setting after every operation, it's about platform setting. ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_IPEndSetting(IPEmType eIP) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ } ++} ++ ++//*********************************************************************************************************** ++// PAD Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitPADPin ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Init PAD Pin Status ( pull enable, pull up/down, driving strength) ++ * ++ * @param ePAD : PAD ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitPADPin(PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ ++ if(ePAD == EV_PAD1) //PAD_SD ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 ++ } ++ else if (ePAD == EV_PAD2) //PAD_NAND ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull en ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x30), BIT06_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //CLK, D3, D2, D1, D0, CMD => drv: 0 ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADToPortPath ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Set PAD to connect IP Port ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param ePort : Port (But FCIE5 use it to decide FCIE or SDIO IP) ++ * @param ePAD : PAD ++ * @param bTwoCard : 1-bit two cards or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADToPortPath(IPEmType eIP, PortEmType ePort, PADEmType ePAD, BOOL_T bTwoCard) ++{ ++ SET_CARD_PORT(eIP, ePort); ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ if(ePAD == EV_PAD1) //PAD_SD ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sdio mode1 = 1 ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ ++ if(ePAD == EV_PAD2) //PAD_NAND ++ { ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT00_T); //reg_emmc_mode = 0 ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd_mode2 = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd_mode1 = 1 ++ ++ } ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PullPADPin ++ * @author jeremy.wang (2015/7/28) ++ * Desc: Pull PAD Pin for Special Purpose (Avoid Power loss.., Save Power) ++ * ++ * @param ePAD : PAD ++ * @param ePinPull : Pull up/Pull down ++ * @param bTwoCard : two card(1 bit) or not ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PullPADPin(PADEmType ePAD, PinPullEmType ePinPull, BOOL_T bTwoCard) ++{ ++ ++ if(ePAD == EV_PAD1) //PAD_SD ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull dis ++ ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sdio mode1 = 0 ++ ++ ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT04_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT04_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT04_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT04_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT04_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT04_T); // output:0 ++ ++ ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x32), BIT12_T|BIT11_T|BIT10_T|BIT09_T|BIT08_T); //D3, D2, D1, D0, CMD=> pull en ++ ++ ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x50), BIT05_T); // input mode ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x51), BIT05_T); // input mode ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x52), BIT05_T); // input mode ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x53), BIT05_T); // input mode ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x54), BIT05_T); // input mode ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x55), BIT05_T); // input mode ++ ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 ++ ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT08_T); //sdio mode1 =1 ++ ++ ++ } ++ ++ } ++ else if(ePAD == EV_PAD2) //PAD_NAND ++ { ++ if(ePinPull ==EV_PULLDOWN) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull dis ++ ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT01_T|BIT00_T); //reg_emmc_mode = 0 //rst=0 ++ // ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd mode2 = 0 // ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd mode1 = 0 ++ ++ //SD_ClK ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT04_T); // output:0 ++ ++ //SD_CMD ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT04_T); // output:0 ++ ++ //SD_D0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT04_T); // output:0 ++ ++ //SD_D1 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT04_T); // output:0 ++ ++ //SD_D2 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT04_T); // output:0 ++ ++ //SD_D3 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT04_T); // output:0 ++ ++ ++ } ++ else if(ePinPull == EV_PULLUP) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x31), BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //D3, D2, D1, D0, CMD=> pull en ++ ++ //SD_CLK ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x42), BIT05_T); // input mode ++ ++ //SD_CMD ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x40), BIT05_T); // input mode ++ ++ //SD_D0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x43), BIT05_T); // input mode ++ ++ //SD_D1 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x44), BIT05_T); // input mode ++ ++ //SD_D2 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x45), BIT05_T); // input mode ++ ++ //SD_D3 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x46), BIT05_T); // input mode ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT00_T); //reg_nand_mode = 0 ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x13), BIT00_T); //reg_emmc_mode = 0 ++ ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT03_T); //sd_mode2 = 0 ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CHIPTOP_BANK, 0x08), BIT02_T); //sd_mode1 = 1 ++ ++ ++ ++ } ++ ++ } ++} ++ ++ ++//*********************************************************************************************************** ++// Clock Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetClock ++ * @author jeremy.wang (2015/7/23) ++ * Desc: Set Clock Level by Real Clock from IP ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ClkFromIPSet : Clock Value From IP Source Set ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetClock(IPEmType eIP, U32_T u32ClkFromIPSet) ++{ ++ ++ if(eIP == EV_IP_FCIE1) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK1_F: //48000KHz ++ break; ++ case CLK1_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT02_T); //1 ++ break; ++ case CLK1_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT03_T); //2 ++ break; ++ case CLK1_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK1_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T); //4 ++ break; ++ case CLK1_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK1_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK1_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x45), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ /* ++ case CLK1_7: ++ break; ++ case CLK1_6: ++ break; ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE2) ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T|BIT03_T|BIT02_T|BIT01_T|BIT00_T); //[5:2]: Clk_Sel [1]: Clk_i [0]: Clk_g ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_SC_GP_CTRL_BANK,0x25), BIT07_T); // select clk_fcie_p ++ ++ switch(u32ClkFromIPSet) ++ { ++ case CLK2_F: //48000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT02_T); //5 ++ break; ++ case CLK2_E: //43200KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT03_T); //6 ++ break; ++ case CLK2_D: //40000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT04_T|BIT03_T|BIT02_T); //7 ++ break; ++ case CLK2_C: //36000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T); //8 ++ break; ++ case CLK2_B: //32000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT02_T); //9 ++ break; ++ case CLK2_A: //20000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT03_T); //10 ++ break; ++ case CLK2_9: //12000KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT03_T|BIT02_T); //3 ++ break; ++ case CLK2_8: //300KHz ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_CLKGEN_BANK,0x43), BIT05_T|BIT04_T); //12 ++ break; ++ /* ++ case CLK1_7: ++ break; ++ case CLK1_6: ++ break; ++ case CLK1_5: ++ break; ++ case CLK1_4: ++ break; ++ case CLK1_3: ++ break; ++ case CLK1_2: ++ break; ++ case CLK1_1: ++ break; ++ case CLK1_0: ++ break;*/ ++ ++ } ++ ++ } ++ else if(eIP == EV_IP_FCIE3) ++ { ++ switch(u32ClkFromIPSet) ++ { ++ /* ++ case CLK3_F: //48000KHz ++ break; ++ case CLK3_E: //43200KHz ++ break; ++ case CLK3_D: //40000KHz ++ break; ++ case CLK3_C: //36000KHz ++ break; ++ case CLK3_B: //32000KHz ++ break; ++ case CLK3_A: //24000KHz ++ break; ++ case CLK3_9: //12000KHz ++ break; ++ case CLK3_8: //300KHz ++ break; ++ case CLK2_4: ++ break; ++ case CLK_3: ++ break; ++ case CLK2_2: ++ break; ++ case CLK2_1: ++ break; ++ case CLK2_0: ++ break;*/ ++ ++ } ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_FindClockSetting ++ * @author jeremy.wang (2015/7/20) ++ * Desc: Find Real Clock Level Setting by Reference Clock ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32ReffClk : Reference Clock Value ++ * @param u8PassLevel : Pass Level to Clock Speed ++ * @param u8DownLevel : Down Level to Decrease Clock Speed ++ * ++ * @return U32_T : Real Clock ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_FindClockSetting(IPEmType eIP, U32_T u32ReffClk, U8_T u8PassLevel, U8_T u8DownLevel) ++{ ++ U8_T u8LV = u8PassLevel; ++ U32_T u32RealClk = 0; ++ U32_T u32ClkArr[3][16] = { \ ++ {CLK1_F, CLK1_E, CLK1_D, CLK1_C, CLK1_B, CLK1_A, CLK1_9, CLK1_8, CLK1_7, CLK1_6, CLK1_5, CLK1_4, CLK1_3, CLK1_2, CLK1_1, CLK1_0} \ ++ ,{CLK2_F, CLK2_E, CLK2_D, CLK2_C, CLK2_B, CLK2_A, CLK2_9, CLK2_8, CLK2_7, CLK2_6, CLK2_5, CLK2_4, CLK2_3, CLK2_2, CLK2_1, CLK2_0} \ ++ ,{CLK3_F, CLK3_E, CLK3_D, CLK3_C, CLK3_B, CLK3_A, CLK3_9, CLK3_8, CLK3_7, CLK3_6, CLK3_5, CLK3_4, CLK3_3, CLK3_2, CLK3_1, CLK3_0} }; ++ ++ for(; u8LV<16; u8LV++) ++ { ++ if( (u32ReffClk >= u32ClkArr[eIP][u8LV]) || (u8LV==15) || (u32ClkArr[eIP][u8LV+1]==0) ) ++ { ++ u32RealClk = u32ClkArr[eIP][u8LV]; ++ break; ++ } ++ } ++ ++ /****** For decrease clock speed******/ ++ if( (u8DownLevel) && (u32RealClk) && ((u8LV+u8DownLevel)<=15) ) ++ { ++ if(u32ClkArr[eIP][u8LV+u8DownLevel]>0) //Have Level for setting ++ u32RealClk = u32ClkArr[eIP][u8LV+u8DownLevel]; ++ } ++ ++ return u32RealClk; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetBusTiming ++ * @author jeremy.wang (2015/7/20) ++ * Desc: Platform Setting for different Bus Timing ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming) ++{ ++ ge_BusTiming[eIP] = eBusTiming; ++} ++ ++ ++//*********************************************************************************************************** ++// Power and Voltage Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetPADPower ++ * @author jeremy.wang (2015/7/30) ++ * Desc: Set PAD power to different voltage ++ * ++ * @param ePAD : PAD ++ * @param ePADVdd : NORMAL/MIN/LOW Voltage Level ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetPADPower(PADEmType ePAD, PADVddEmType ePADVdd) ++{ ++ ++ if(ePAD == EV_PAD1) ++ { ++ } ++ else if(ePAD == EV_PAD2) ++ { ++ ++ } ++ else if(ePAD == EV_PAD3) ++ { ++ if(ePADVdd == EV_NORVOL) ++ { ++ } ++ } ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOn ++ * @author jeremy.wang (2015/7/29) ++ * Desc: Power ON Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms for stable power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOn(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:0 ++ ++ ++ } ++ else if(ePAD==EV_PAD2) //PAD_NAND ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT00_T); // output mode ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT01_T); // output:0 ++ } ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_PowerOff ++ * @author jeremy.wang (2015/7/29) ++ * Desc: Power Off Card Power ++ * ++ * @param ePAD : PAD ++ * @param u16DelayMs : Delay ms to confirm no any spower ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_PowerOff(PADEmType ePAD, U16_T u16DelayMs) ++{ ++ if( (ePAD==EV_PAD1)) //PAD_SD ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT05_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PADTOP_BANK, 0x17), BIT04_T); // output:1 ++ ++ } ++ else if(ePAD==EV_PAD2) //PAD_NAND ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT00_T); // output mode ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x06), BIT01_T); // output:0 ++ ++ } ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++//*********************************************************************************************************** ++// Card Detect and GPIO Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_InitGPIO ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Init GPIO Setting for CDZ or other GPIO (Pull high/low and driving, base SD/GPIO mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bEnable : Enable GPIO or disable GPIO to avoid loss power ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_InitGPIO(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bEnable) ++{ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ if(bEnable) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ } ++ } ++ else if(ePAD==EV_PAD2) //PAD_NAND ++ { ++ if(bEnable) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x07), BIT00_T); //input mode ++ } ++ } ++ ++ } ++ else if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x28), BIT14_T); //SD_CDZ mode en ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47), BIT00_T); //input mode ++ } ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO input mode value (Include input mode setting) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : Insert (TRUE) or Remove (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GetGPIOState(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ U16_T u16Reg = 0; ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ u16Reg = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ } ++ else if(ePAD==EV_PAD2) //PAD_NAND ++ { ++ u16Reg = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x07)) & BIT02_T; ++ } ++ ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ u16Reg = CARD_REG(GET_CARD_REG_ADDR(A_PM_GPIO_BANK, 0x47)) & BIT02_T; ++ } ++ ++ if(!u16Reg) //Low Active ++ return (TRUE); ++ else ++ return (FALSE); ++ ++ ++ ++ } ++ ++ if(!u16Reg) //Low Active ++ return (TRUE); ++ else ++ return (FALSE); ++ ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOState ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO output mode value (Include output mode setting), it's for SDIO WIFI control using ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param bOutputState : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOState(GPIOEmType eGPIO, PADEmType ePAD, BOOL_T bOutputState) ++{ ++ ++ /*if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x05), BIT00_T); //PMU_GPIO_OUT_EN ++ ++ if(bOutputState) ++ { ++ CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT00_T); //PMU_GPIO_OUT=1 ++ } ++ else ++ { ++ CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PMGPIO_BANK, 0x07), BIT00_T); //PMU_GPIO_OUT=0 ++ } ++ } ++ if( eGPIO==EV_GPIO2 ) //EV_GPIO2 for Slot 1 ++ { ++ } ++ if( eGPIO==EV_GPIO3 ) //EV_GPIO2 for Slot 1 ++ { ++ } ++ ++ // Add a 500ms Delay after card removing to avoid the next card inserting issue ++ if(bOutputState==1) ++ { ++ Hal_Timer_mSleep(500); ++ } ++ else // For 0->1, 1->0 stable ++ { ++ Hal_Timer_mSleep(1); ++ }*/ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GetGPIONum ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Get GPIO number for special platform (like Linux) to use it get irq number ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return U32_T : GPIO number ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_GetGPIONum(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ //S32_T s32GPIO = -1; ++ ++ /*if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ //s32GPIO = DrvPadmuxGetGpio(IO_CHIP_INDEX_SD_CDZ); ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ }*/ ++ ++ /*if(s32GPIO>0) ++ return (U32_T)s32GPIO; ++ else ++ return 0;*/ ++ ++ return 0; ++} ++ ++ ++#if (D_OS == D_OS__LINUX) ++#include ++#include "../../../mstar/include/infinity/irqs.h" ++#endif ++ ++extern struct irq_chip gic_arch_extn; ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_SetGPIOIntAttr ++ * @author jeremy.wang (2016/12/15) ++ * Desc: Set GPIO Interrupt Attribute (Option 1..5), it could design for different requirement ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * @param eGPIOOPT : Option1/Option2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_CARD_SetGPIOIntAttr(GPIOEmType eGPIO, PADEmType ePAD, GPIOOptEmType eGPIOOPT) ++{ ++ ++#if (D_OS == D_OS__LINUX) ++ struct irq_data sd_irqdata; ++ struct irq_chip *chip; ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ sd_irqdata.irq = (INT_FIQ_SD_CDZ+32); ++ sd_irqdata.hwirq = (INT_FIQ_SD_CDZ+32); ++ } ++ else if(ePAD==EV_PAD2) //PAD_NAND ++ { ++ sd_irqdata.irq = (INT_PMSLEEP_GPIO_7+160); ++ sd_irqdata.hwirq = (INT_PMSLEEP_GPIO_7+160); ++ } ++ } ++ else if( eGPIO==EV_GPIO2) ++ { ++ if(ePAD==EV_PAD1) //PAD_SD ++ { ++ sd_irqdata.irq = (INT_FIQ_SD_CDZ+32); ++ sd_irqdata.hwirq = (INT_FIQ_SD_CDZ+32); ++ } ++ ++ } ++ else if(eGPIO==EV_GPIO3) ++ { ++ } ++ ++#ifdef CONFIG_ARM_GIC ++ chip= &gic_arch_extn; ++#else ++ chip = irq_get_chip(sd_irqdata.irq); ++#endif ++ ++ if(eGPIOOPT==EV_GPIO_OPT1) //clear interrupt ++ { ++ chip->irq_ack(&sd_irqdata); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PMSLEEP_BANK, 0x75), BIT00_T); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT2)) ++ { ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT3)) //sd polarity _HI Trig for remove ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_RISING)); ++ //CARD_REG_CLRBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x7B), BIT00_T); ++ } ++ else if((eGPIOOPT==EV_GPIO_OPT4)) //sd polarity _LO Trig for insert ++ { ++ chip->irq_set_type(&sd_irqdata,(IRQ_TYPE_EDGE_FALLING)); ++ //CARD_REG_SETBIT(GET_CARD_REG_ADDR(A_PM_SLEEP_BANK, 0x7B), BIT00_T); ++ } ++ ++ ++#endif ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_GPIOIntFilter ++ * @author jeremy.wang (2016/12/15) ++ * Desc: GPIO Interrupt Filter, it could design to filter GPIO Interrupt (Many sources belong to the same one) ++ * ++ * @param eGPIO : GPIO1/GPIO2/... ++ * @param ePAD : PAD ++ * ++ * @return BOOL_T : TRUE or FALSE ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_CARD_GPIOIntFilter(GPIOEmType eGPIO, PADEmType ePAD) ++{ ++ ++ if( eGPIO==EV_GPIO1 ) //EV_GPIO1 for Slot 0 ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO2 ) ++ { ++ return (TRUE); ++ } ++ else if( eGPIO==EV_GPIO3 ) ++ { ++ return (TRUE); ++ } ++ ++ return (FALSE); ++} ++ ++ ++//*********************************************************************************************************** ++// MIU Setting for Card Platform ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_CARD_TransMIUAddr ++ * @author jeremy.wang (2015/7/31) ++ * Desc: Transfer original address to HW special dma address (MIU0/MIU1) ++ * ++ * @param u32Addr : Original address ++ * ++ * @return U32_T : DMA address ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_CARD_TransMIUAddr(U32_T u32Addr) ++{ ++ return u32Addr; ++} +diff --git a/drivers/mstar/sdmmc/src/hal_card_regs.c b/drivers/mstar/sdmmc/src/hal_card_regs.c +new file mode 100644 +index 00000000..b58d789a +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_regs.c +@@ -0,0 +1,57 @@ ++//////////////////////////////////////////////////////////////////////////////// ++// ++// Copyright (c) 2006-2012 MStar Semiconductor, Inc. ++// All rights reserved. ++// ++// Unless otherwise stipulated in writing, any and all information contained ++// herein regardless in any format shall remain the sole proprietary of ++// MStar Semiconductor Inc. and be kept in strict confidence ++// (MStar Confidential Information) by the recipient. ++// Any unauthorized act including without limitation unauthorized disclosure, ++// copying, use, reproduction, sale, distribution, modification, disassembling, ++// reverse engineering and compiling of the contents of MStar Confidential ++// Information is unlawful and strictly prohibited. MStar hereby reserves the ++// rights to any and all damages, losses, costs and expenses resulting therefrom. ++// ++//////////////////////////////////////////////////////////////////////////////// ++ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_regs.c ++ * @author jeremy.wang (2015/06/01) ++ * Desc: ++ * For Dynamic IP Address Reading and Port Setting. ++ * We could get current REG/CIFC/CIFD Bank Address anytime! ++ * We use global varible to record current port setting of IP, then we could use it to decide reg postions. ++ * The goal is that we don't need to change HAL Level code. (But its h file code) ++ * ++ * The limitations were listed as below: ++ * (1) This c file could not use project/cpu/icver/specific define option here, but its h file could. ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_regs.h" ++ ++static volatile PortEmType gePort[3]; ++ ++void Hal_CREG_SET_PORT(IPEmType eIP, PortEmType ePort) ++{ ++ gePort[eIP] = ePort; ++} ++ ++volatile PortEmType Hal_CREG_GET_PORT(IPEmType eIP) ++{ ++ return gePort[eIP]; ++} ++ ++volatile void* Hal_CREG_GET_REG_BANK(IPEmType eIP, U8_T u8Bank) ++{ ++ void* pIPBANKArr[3][3] ={ ++ {(void*)(A_FCIE1_0_BANK), (void*)(A_FCIE1_1_BANK), (void*)(A_FCIE1_2_BANK)}, \ ++ {(void*)(A_FCIE2_0_BANK), (void*)(A_FCIE2_1_BANK), (void*)(A_FCIE2_2_BANK)}, \ ++ {(void*)(A_FCIE3_0_BANK), (void*)(A_FCIE3_1_BANK), (void*)(A_FCIE3_2_BANK)}\ ++ }; ++ ++ return pIPBANKArr[eIP][u8Bank]; ++ ++} +diff --git a/drivers/mstar/sdmmc/src/hal_card_timer.c b/drivers/mstar/sdmmc/src/hal_card_timer.c +new file mode 100644 +index 00000000..33382a67 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_card_timer.c +@@ -0,0 +1,92 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_card_timer.c ++ * @author jeremy.wang (2012/01/13) ++ * Desc: ++ * All of timer behavior will run here. ++ * The goal is that we don't need to change HAL Level code (But its h file code) ++ * ++ * The limitation were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API level, not driver flow process. ++ * (2) Delay and GetTimerTick function belong to here. ++ * (3) Because timer may belong to OS design or HW timer, so we could use OS define option to separate them. ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_card_timer.h" ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_Timer_mDelay ++ * @author jeremy.wang (2013/7/19) ++ * Desc: Run millisecond delay ++ * ++ * @param u32_msec : Millisecond for Delay ++ * ++ * @return U32_T : Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_Timer_mDelay(U32_T u32_msec) ++{ ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) || (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++ mdelay(u32_msec); ++ return u32_msec; ++//########################################################################################################### ++#endif ++ return 0; ++ ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_Timer_uDelay ++ * @author jeremy.wang (2013/7/19) ++ * Desc: Run micro-second delay ++ * ++ * @param u32_usec : Micro-second for Delay ++ * ++ * @return U32_T : Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_Timer_uDelay(U32_T u32_usec) ++{ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) || (D_OS == D_OS__UBOOT) ++//########################################################################################################### ++ udelay(u32_usec); ++ return u32_usec; ++//########################################################################################################### ++#endif ++ ++ return 0; ++} ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_Timer_mSleep ++ * @author jeremy.wang (2015/1/15) ++ * Desc: Run millisecond sleep ++ * ++ * @param u32_msec : Millisecond for Sleep ++ * ++ * @return U32_T : Delay time ++ ----------------------------------------------------------------------------------------------------------*/ ++U32_T Hal_Timer_mSleep(U32_T u32_msec) ++{ ++ ++//########################################################################################################### ++#if (D_OS == D_OS__LINUX) ++//########################################################################################################### ++ msleep(u32_msec); ++ return u32_msec; ++//########################################################################################################### ++#endif ++ return 0; ++ ++} ++ ++ ++ ++ +diff --git a/drivers/mstar/sdmmc/src/hal_sdmmc.c b/drivers/mstar/sdmmc/src/hal_sdmmc.c +new file mode 100644 +index 00000000..392d78f9 +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_sdmmc.c +@@ -0,0 +1,1367 @@ ++ ++/*************************************************************************************************************** ++ * ++ * FileName hal_sdmmc.c ++ * @author jeremy.wang (2011/07/21) ++ * Desc: ++ * HAL SD Driver will support basic SD function but not flow process. ++ * The goal is that we don't need to change HAL Level code (But its h file code) ++ * ++ * The limitation were listed as below: ++ * (1) This c file belongs to HAL level. ++ * (2) Its h file is included by driver API level, not driver flow process. ++ * (3) FCIE/SDIO IP register and buffer opertion function belong to here. ++ * (4) Only IP flow concept, but not SD command concept. ++ * (5) This c file could not use project/os/cpu/icver/specific define option here, but its h file could. ++ * ++ * P.S. EN_XX for ON/OFF Define, , V_XX for Value Define, ++ * RT_XX for Retry Times Define, WT_XX for Wait Time Define, M_XX for Mask Value Define ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_sdmmc.h" ++#include "../inc/hal_card_timer.h" ++ ++#if(EN_BIND_CARD_INT) ++#include "../inc/hal_card_intr.h" //inlcue but may not use ++#endif ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Enable Setting ++//----------------------------------------------------------------------------------------------------------- ++#define EN_TRFUNC (FALSE) ++#define EN_DUMPREG (TRUE) ++#define EN_BYTEMODE (TRUE) ++#define EN_BYPASSMODE (TRUE) //BYPASS MODE or ADVANCE MODE(SDR/DDR) ++ ++// Retry Times ++//----------------------------------------------------------------------------------------------------------- ++#define RT_CLEAN_SDSTS 3 ++#define RT_CLEAN_MIEEVENT 3 ++ ++// Wait Time ++//----------------------------------------------------------------------------------------------------------- ++#define WT_DAT0HI_END 3000 //(ms) ++#define WT_FIFO_CLK_RDY 100 //(ms) ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++ ++// Reg Static Init Setting ++//----------------------------------------------------------------------------------------------------------- ++#define V_MIE_PATH_INIT R_SD_EN ++#define V_MMA_PRI_INIT (R_MMA_R_PRIORITY|R_MMA_W_PRIORITY|V_MIUCLK_CTRL_INIT|V_MIUBUS_CTRL_INIT) ++#define V_MIE_INT_EN_INIT (R_SD_CMD_END_EN) ++#define V_RSP_SIZE_INIT 0x0 ++#define V_CMD_SIZE_INIT 0x05 ++#define V_SD_CTL_INIT (R_SDIO_DET_INTSRC) ++#define V_SD_MODE_INIT (R_SD_CLK_EN|R_SD_CS_EN) ++#define V_SD_BOOTCFG_INIT 0x0 ++ ++#if (EN_MIU_WDEN_PATCH_DIS) ++#define V_NC_REORDER_INIT (R_MIU_WDEN_PATCH_DIS) ++#else ++#define V_NC_REORDER_INIT 0x0 ++#endif ++ ++ ++// Mask Range ++//----------------------------------------------------------------------------------------------------------- ++#define M_SD_ERRSTS (R_SD_DAT_CERR|R_SD_DAT_STSERR|R_SD_DAT_STSNEG|R_SD_CMD_NORSP|R_SD_CMDRSP_CERR) //0x1F ++#define M_SD_MIEEVENT (R_MMA_DATA_END|R_SD_CMD_END|R_SD_DATA_END|R_CARD_DMA_END|R_MMA_LSDONE_END) ++ ++ ++// Mask Reg Value ++//----------------------------------------------------------------------------------------------------------- ++#define M_REG_STSERR(IP) (CARD_REG(A_SD_STS_REG(IP)) & M_SD_ERRSTS) //0x1F ++#define M_REG_SDMIEEvent(IP) (CARD_REG(A_MIE_EVENT_REG(IP)) & M_SD_MIEEVENT) ++#define M_REG_FIFORDYCHK(IP) (CARD_REG(A_MMA_PRI_REG_REG(IP)) & R_JOB_RW_DIR & R_FIFO_CLK_RDY) ++ ++ ++//IP_FCIE or IP_SDIO Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_SD_REG_POS(IP) GET_CARD_BANK(IP, 0) ++#define A_SD_CFIFO_POS(IP) GET_CARD_BANK(IP, 1) ++#define A_SD_CIFD_BANK(IP) GET_CARD_BANK(IP, 2) ++ ++#define A_MIE_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x00) ++#define A_MMA_PRI_REG_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x02) ++#define A_MIU_DMA1_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x03) ++#define A_MIU_DMA0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x04) ++#define A_CARD_DET_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x07) ++#define A_CARD_PWR_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x08) ++#define A_INTR_TEST_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x09) ++#define A_MIE_PATH_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0A) ++#define A_JOB_BL_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0B) ++#define A_TR_BK_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0C) ++#define A_RSP_SIZE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0D) ++#define A_CMD_SIZE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0E) ++#define A_CARD_WD_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0F) ++#define A_SD_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x10) ++#define A_SD_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x11) ++#define A_SD_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x12) ++#define A_EMMC_PATH_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x16) ++#define A_SDIO_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x1B) ++#define A_SDIO_ADDR0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x1C) ++#define A_SDIO_ADDR1_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x1D) ++#define A_SDIO_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x1E) ++#define A_NC_REORDER_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x2D) ++#define A_DAM_OFFSET_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x2E) ++#define A_EMMC_BOOTCFG_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x2F) ++#define A_TEST_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x30) ++#define A_TEST_DEBUG1_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x31) ++#define A_TEST_DEBUG2_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x32) ++ ++#define A_CFIFO_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CFIFO_POS(IP), OFFSET) ++#define A_CIFD_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CIFD_BANK(IP), OFFSET) ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static RspStruct gst_RspStruct[3]; ++static volatile BOOL_T gb_StopWProc[3] = {0}; ++static volatile U16_T gu16_WT_NRC[3] = {0}; //Waiting Time for Nrc (us) ++static volatile U16_T gu16_SD_MODE_DatLine[3] = {0}; ++ ++static volatile U16_T gu16_SD_MODE_DatSync[3] = {0}; ++static volatile U16_T gu16_PAD_IN_SEL[3] = {0}; ++static volatile U16_T gu16_EMMC_BOOTCFG_REG[3] = {0}; ++ ++static volatile BOOL_T gb_SDIODevice[3] = {0}; ++static volatile U16_T gu16_SD_CTL_SDIO_IntMode[3] = {0}; ++static volatile U16_T gu16_SD_CTL_SDIO_Det[3] = {0}; ++static volatile U16_T gu16_SDIO_DetOn_RunOnce[3] = {0}; ++ ++static volatile U8_T* gpu8Buf[3]; ++ ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_TRFUNC) ++ #define TR_H_SDMMC(p) p ++#else ++ #define TR_H_SDMMC(p) ++#endif ++ ++ ++// Register Operation Define ==> For Get Current Port Setting ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_GetPortSetting(IPEmType eIP) ++{ ++ PortEmType ePort = GET_CARD_PORT(eIP); ++ ++ if( ePort == EV_PORT_SDIO1) ++ return R_SDIO_SD_BUS_SW; ++ else if ( ePort == EV_PORT_SDIO2 ) ++ return (R_SDIO_SD_BUS_SW|R_SDIO_PORT_SEL); ++ else ++ return 0; ++} ++ ++ ++// Register Operation Define ==> For Get Current DAT0 Value ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_GetDAT0(IPEmType eIP) ++{ ++ PortEmType ePort = GET_CARD_PORT(eIP); ++ ++ if( ePort == EV_PORT_SDIO1) ++ return (CARD_REG(A_SDIO_STS_REG(eIP)) & R_SDIO_DAT0); ++ else if ( ePort == EV_PORT_SDIO2 ) ++ return (CARD_REG(A_SDIO_STS_REG(eIP)) & R_SDIO2_DAT0); ++ else ++ return (CARD_REG(A_SD_STS_REG(eIP)) & R_SD_DAT0); ++} ++ ++ ++// Register Operation Define ==> For Get Current CDET Value ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_GetCDET(IPEmType eIP) ++{ ++ PortEmType ePort = GET_CARD_PORT(eIP); ++ ++ if( ePort == EV_PORT_SDIO1) ++ return (CARD_REG(A_CARD_DET_REG(eIP)) & R_SDIO_DET_N); ++ else if ( ePort == EV_PORT_SDIO2 ) ++ return (CARD_REG(A_CARD_DET_REG(eIP)) & R_SDIO2_DET_N); ++ else ++ return (CARD_REG(A_CARD_DET_REG(eIP)) & R_SD_DET_N); ++} ++ ++ ++// Register Operation Define ==> For Clean Reg and Special Case ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_ClearSDSTS(IPEmType eIP, U8_T u8Retry) ++{ ++ do ++ { ++ CARD_REG_SETBIT(A_SD_STS_REG(eIP), M_SD_ERRSTS); ++ ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if ( !M_REG_STSERR(eIP) ) ++ return EV_OK; ++ else if(!u8Retry) ++ return EV_FAIL; ++ ++ } while(u8Retry--); ++ return EV_FAIL; ++} ++ ++ ++// Register Operation Define ==> For Clear MIE Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_ClearMIEEvent(IPEmType eIP, U8_T u8Retry) ++{ ++ /****** Clean global MIEEvent for Interrupt ******/ ++#if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_ClearMIEEvent(eIP); ++#endif ++ ++ /****** Clean MIEEvent Reg *******/ ++ do ++ { ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = M_SD_MIEEVENT; ++ ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if ( !M_REG_SDMIEEvent(eIP) ) ++ return EV_OK; ++ else if(!u8Retry) ++ return EV_FAIL; ++ ++ }while(u8Retry--); ++ return EV_FAIL; ++} ++ ++ ++// Register Operation Define ==> For Wait DAT0 High ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitDat0HI(IPEmType eIP, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++ do ++ { ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if ( _REG_GetDAT0(eIP) ) ++ return EV_OK; ++ ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while(u32DiffTime <= (u32WaitMs*1000)); ++ ++ return EV_FAIL; ++} ++ ++ ++// Register Operation Define ==> For Wait FIFO Clk Ready ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitFIFOClkRdy(IPEmType eIP, CmdEmType eCmdType, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++ do ++ { ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if( M_REG_FIFORDYCHK(eIP) == ((eCmdType>>6) & R_FIFO_CLK_RDY) ) ++ return EV_OK; ++ ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while(u32DiffTime <= (u32WaitMs*1000)); ++ return EV_FAIL; ++} ++ ++ ++// Register Operation Define ==> For Wait MIE Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitMIEEvent(IPEmType eIP, U16_T u16ReqEvent, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++#if(EN_BIND_CARD_INT) ++ if ( Hal_CARD_INT_MIEIntRunning(eIP, EV_INT_SD) ) // Interrupt Mode ++ { ++ if ( !Hal_CARD_INT_WaitMIEEvent(eIP, u16ReqEvent, u32WaitMs) ) ++ return EV_FAIL; ++ else ++ return EV_OK; ++ } else // Polling Mode ++#endif ++ { ++ do ++ { ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if ( (CARD_REG(A_MIE_EVENT_REG(eIP))&u16ReqEvent) == u16ReqEvent ) ++ return EV_OK; ++ ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while(u32DiffTime <= (u32WaitMs*1000)); ++ return EV_FAIL; ++ } ++ ++} ++ ++// Register Operation Define ==> For Software Reset ++//----------------------------------------------------------------------------------------------------------- ++static void _REG_ResetIP(IPEmType eIP) ++{ ++ ++ CARD_REG_CLRBIT(A_MIE_PATH_CTL_REG(eIP), R_MMA_ENABLE); //Avoid MMA_Enable lock (Auto Clear Fail) ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_SD_CMD_EN|R_SD_DTRX_EN); //Avoid SD_CMD_EN/DTRX_EN lock (Auto Clear Fail) ++ CARD_REG_CLRBIT(A_MMA_PRI_REG_REG(eIP), R_MIU_CLK_EN_HW); //Avoid MIU_CLK_EN_HW lock (Auto Clear Fail) ++ ++ CARD_REG_SETBIT(A_MMA_PRI_REG_REG(eIP), R_MIU_REQ_RST); //Avoid MIU Request lock (MIU hold) ++ ++ Hal_Timer_mDelay(1); ++ ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_FCIE_SOFT_RST); ++ ++ Hal_Timer_mDelay(1); //50x time => 2T (Max 20us) ++ ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), R_FCIE_SOFT_RST); ++ ++ Hal_Timer_mDelay(1); //50x time => 2T (Max 20us) ++ ++ CARD_REG_CLRBIT(A_MMA_PRI_REG_REG(eIP), R_MIU_REQ_RST); ++} ++ ++ ++// Register Operation Define ==> Fix CIFD (SRAM) First Time R/W Bug ++//----------------------------------------------------------------------------------------------------------- ++static void _REG_CIFDEmptyRW(IPEmType eIP) ++{ ++ U16_T u16FixSRAMBug = 0x00; ++ ++ CARD_REG(A_CIFD_OFFSET(eIP, 0)) = u16FixSRAMBug; ++ CARD_REG(A_CIFD_OFFSET(eIP, 1)) = CARD_REG(A_CIFD_OFFSET(eIP, 0)); ++ u16FixSRAMBug = CARD_REG(A_CIFD_OFFSET(eIP, 1)); ++ ++} ++ ++ ++// IP Buffer Operation => Get Byte Value form Register ++//----------------------------------------------------------------------------------------------------------- ++static U8_T _BUF_GetByteFromRegAddr(volatile void *pBuf, U16_T u16Pos) ++{ ++ if(u16Pos & 0x1) ++ return CARD_REG_H8(GET_CARD_REG_ADDR(pBuf, u16Pos>>1)); ++ else ++ return CARD_REG_L8(GET_CARD_REG_ADDR(pBuf, u16Pos>>1)); ++} ++ ++ ++// IP Buffer Operation => CIFD FIFO Buffer Operation Define ++//----------------------------------------------------------------------------------------------------------- ++void _BUF_CIFD_DATA_IO(IPEmType eIP, CmdEmType eCmdType, volatile U16_T *pu16Buf, U8_T u8WordCnt) ++{ ++ U8_T u8Pos = 0; ++ ++ for ( u8Pos = 0; u8Pos < u8WordCnt; u8Pos++ ) ++ { ++ if ( eCmdType==EV_CMDREAD ) ++ pu16Buf[u8Pos] = CARD_REG(A_CIFD_OFFSET(eIP, u8Pos)); ++ else ++ CARD_REG(A_CIFD_OFFSET(eIP, u8Pos)) = pu16Buf[u8Pos]; ++ } ++ ++} ++ ++ ++// SDMMC Internel Logic Function ++//----------------------------------------------------------------------------------------------------------- ++static void _SDMMC_REG_Dump(IPEmType eIP) ++{ ++ ++#if (EN_DUMPREG) ++ ++ U8_T u8Pos, u8DGMode; ++ ++ prtstring("\n----------------------------------------------------\r\n"); ++ prtstring(" CMD_"); ++ prtUInt(gst_RspStruct[eIP].u8Cmd); ++ prtstring(" (Arg: "); ++ prtU32Hex(gst_RspStruct[eIP].u32Arg); ++ prtstring(") [Line: "); ++ prtUInt(gst_RspStruct[eIP].u32ErrLine); ++ prtstring("]\r\n"); ++ ++ prtstring("----------------------------------------------------\r\n"); ++ ++ for(u8Pos = 0; u8Pos < gst_RspStruct[eIP].u8RspSize; u8Pos++) ++ { ++ if( (u8Pos == 0) || (u8Pos == 8) ) ++ prtstring("["); ++ ++ prtU8Hex(_BUF_GetByteFromRegAddr((volatile void *)A_SD_CFIFO_POS(eIP), u8Pos)); ++ prtstring(","); ++ ++ if( (u8Pos == 7) || (u8Pos == (gst_RspStruct[eIP].u8RspSize-1)) ) ++ prtstring("]\n"); ++ } ++ ++ prtstring("---------------DumpReg------------------------------\r\n"); ++ ++ prtstring("[0x0A][MIE_PATH_CTL_REG]= "); ++ prtU16Hex(CARD_REG(A_MIE_PATH_CTL_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x10][SD_MODE_REG]= "); ++ prtU16Hex(CARD_REG(A_SD_MODE_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x11][SD_CTL_REG]= "); ++ prtU16Hex(CARD_REG(A_SD_CTL_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x12][SD_STS_REG]= "); ++ prtU16Hex(CARD_REG(A_SD_STS_REG(eIP))); ++ prtstring("\r\n"); ++ ++ if(GET_CARD_PORT(eIP) != EV_PORT_SD) ++ { ++ prtstring("[0x1E][SDIO_STS_REG]= "); ++ prtU16Hex(CARD_REG(A_SDIO_STS_REG(eIP))); ++ prtstring("\r\n"); ++ } ++ ++#if(EN_BIND_CARD_INT) ++ if ( Hal_CARD_INT_MIEIntRunning(eIP, EV_INT_SD) ) // Interrupt Mode ++ { ++ prtstring("[gu16_MIEEvent_ForInt]= "); ++ prtU16Hex(Hal_CARD_INT_GetMIEEvent(eIP)); ++ prtstring("\r\n"); ++ } ++#endif ++ ++ prtstring("[0x01][MIE_EVENT_REG]= "); ++ prtU16Hex(CARD_REG(A_MIE_EVENT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ ++ prtstring("[0x02][MMA_PRI_REG_REG]= "); ++ prtU16Hex(CARD_REG(A_MMA_PRI_REG_REG(eIP))); ++ prtstring("\r\n"); ++ ++#if (EN_BYTEMODE) ++ prtstring("[0x1D][SDIO_ADDR1_REG]= "); ++ prtU16Hex(CARD_REG(A_SDIO_ADDR1_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x1C][SDIO_ADDR0_REG]= "); ++ prtU16Hex(CARD_REG(A_SDIO_ADDR0_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x1B][SDIO_CTL_REG]= "); ++ prtU16Hex(CARD_REG(A_SDIO_CTL_REG(eIP))); ++ prtstring("\r\n"); ++#else ++ prtstring("[0x03][MIU_DMA1_REG]= "); ++ prtU16Hex(CARD_REG(A_MIU_DMA1_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x04][MIU_DMA0_REG]= "); ++ prtU16Hex(CARD_REG(A_MIU_DMA0_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x2E][DAM_OFFSET_REG]= "); ++ prtU16Hex(CARD_REG(A_DAM_OFFSET_REG(eIP))); ++ prtstring("\r\n"); ++#endif ++ ++ prtstring("[0x0B][JOB_BL_CNT_REG]= "); ++ prtU16Hex(CARD_REG(A_JOB_BL_CNT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x0C][TR_BK_CNT_REG]= "); ++ prtU16Hex(CARD_REG(A_TR_BK_CNT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x0F][CARD_WD_CNT_REG]= "); ++ prtU16Hex(CARD_REG(A_CARD_WD_CNT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x31][SDMMC_DEBUG1]= "); ++ for(u8DGMode = 1; u8DGMode <=7; u8DGMode++) ++ { ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_DEBUG_MODE0 | R_DEBUG_MODE1 | R_DEBUG_MODE2); ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), (u8DGMode<<8)); ++ prtU16Hex(CARD_REG(A_TEST_DEBUG1_REG(eIP))); ++ prtstring(", "); ++ } ++ prtstring("\r\n"); ++ prtstring("[0x32][SDMMC_DEBUG2]= "); ++ ++ for(u8DGMode = 1; u8DGMode <=7; u8DGMode++) ++ { ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_DEBUG_MODE0 | R_DEBUG_MODE1 | R_DEBUG_MODE2); ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), (u8DGMode<<8)); ++ prtU16Hex(CARD_REG(A_TEST_DEBUG2_REG(eIP))); ++ prtstring(", "); ++ ++ } ++ prtstring("\r\n"); ++ ++ prtstring("----------------------------------------------------\r\n"); ++ ++#endif //End #if(EN_DUMPREG) ++ ++} ++ ++ ++static RspErrEmType _SDMMC_EndProcess(IPEmType eIP, CmdEmType eCmdType, RspErrEmType eRspErr, BOOL_T bCloseClk, int Line) ++{ ++ U16_T u16RspErr = (U16_T)eRspErr; ++ U16_T u16IPErr = EV_STS_RIU_ERR | EV_STS_MIE_TOUT | EV_STS_FIFO_NRDY | EV_STS_DAT0_BUSY; ++ ++ /****** (1) Record Information *******/ ++ gst_RspStruct[eIP].u32ErrLine = (U32_T)Line; ++ gst_RspStruct[eIP].u8RspSize = (U8_T)CARD_REG(A_RSP_SIZE_REG(eIP)); ++ gst_RspStruct[eIP].eErrCode = eRspErr; ++ ++ /****** (2) Dump and the Reg Info + Reset IP *******/ ++ ++ if ( u16RspErr && gb_StopWProc[eIP] ) ++ { ++ eRspErr = EV_SWPROC_ERR; ++ _REG_ResetIP(eIP); ++ } ++ else if( u16RspErr & u16IPErr ) //SD IP Error ++ { ++ _SDMMC_REG_Dump(eIP); ++ _REG_ResetIP(eIP); ++ } ++ else if( u16RspErr & M_SD_ERRSTS ) //SD_STS Reg Error ++ { ++ //Do Nothing ++ } ++ ++ /****** (3) Close clock and DMA Stop function ******/ ++ if(bCloseClk && !gb_SDIODevice[eIP]) ++ CARD_REG_CLRBIT(A_SD_MODE_REG(eIP), R_SD_CLK_EN|R_SD_DMA_RD_CLK_STOP); ++ ++ /****** (4) Clock MIU Clock (SW) when SW open or not *******/ ++ CARD_REG_CLRBIT(A_MMA_PRI_REG_REG(eIP), R_MIU_CLK_EN_SW); ++ ++ return eRspErr; ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Mechanism Detection Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_WriteProtect ++ * @author jeremy.wang (2011/12/1) ++ * Desc: Check Card Write Protect ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * ++ * @return BOOL_T : Write Protect or not ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_SDMMC_WriteProtect(IPEmType eIP) ++{ ++ CARD_REG(A_MIE_PATH_CTL_REG(eIP)) = V_MIE_PATH_INIT; ++ CARD_REG(A_SD_MODE_REG(eIP)) = _REG_GetPortSetting(eIP); ++ ++ if ( CARD_REG(A_SD_STS_REG(eIP)) & R_SD_WR_PRO_N ) ++ return (FALSE); //No Write Protect ++ return (TRUE); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_CardDetect ++ * @author jeremy.wang (2011/10/11) ++ * Desc: Check Card Detection ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * ++ * @return BOOL_T : Card Detection or not ++ ----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_SDMMC_CardDetect(IPEmType eIP) ++{ ++ CARD_REG_SETBIT(A_MIE_PATH_CTL_REG(eIP), V_MIE_PATH_INIT); ++ CARD_REG_SETBIT(A_SD_MODE_REG(eIP), _REG_GetPortSetting(eIP)); ++ ++ if ( _REG_GetCDET(eIP) ) ++ return (FALSE); //No Card Detect ++ return (TRUE); ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Operation Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetDataWidth ++ * @author jeremy.wang (2011/11/28) ++ * Desc: According as Data Bus Width to Set IP DataWidth ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eBusWidth : 1BIT/4BITs/8BITs ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetDataWidth(IPEmType eIP, SDMMCBusWidthEmType eBusWidth) ++{ ++ gu16_SD_MODE_DatLine[eIP] = (U16_T)eBusWidth; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetBusTiming ++ * @author jeremy.wang (2015/7/29) ++ * Desc: ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming) ++{ ++ gu16_PAD_IN_SEL[eIP] = 0; ++ ++ switch ( eBusTiming ) ++ { ++ case EV_BUS_LOW: ++ gu16_SD_MODE_DatSync[eIP] = R_SD_DATSYNC; ++ gu16_EMMC_BOOTCFG_REG[eIP] = R_SDYPASSMODE; ++ break; ++ case EV_BUS_DEF: ++ gu16_SD_MODE_DatSync[eIP] = 0; ++ gu16_EMMC_BOOTCFG_REG[eIP] = R_SDYPASSMODE; ++ break; ++ ++#if (EN_BYPASSMODE) ++ case EV_BUS_HS: ++ gu16_SD_MODE_DatSync[eIP] = R_SD_DATSYNC; ++ gu16_EMMC_BOOTCFG_REG[eIP] = R_SDYPASSMODE; ++ break; ++ default: ++ break; ++ ++#else ++ //ADVANCE MODE(SDR/DDR) ==> Other can't run bypass mode ++ ++ case EV_BUS_HS: ++ gu16_PAD_IN_SEL[eIP] = R_CSREG_PAD_IN_SEL; // T-Mux SDR ++ gu16_SD_MODE_DatSync[eIP] = R_SD_DATSYNC; ++ gu16_EMMC_BOOTCFG_REG[eIP] = 0; ++ break; ++ ++ case EV_BUS_SDR12: ++ break; ++ case EV_BUS_SDR25: ++ break; ++ case EV_BUS_SDR50: ++ break; ++ case EV_BUS_SDR104: ++ break; ++ case EV_BUS_DDR50: ++ break; ++ case EV_BUS_HS200: ++ break; ++ default: ++ break; ++ ++#endif ++ ++ ++ ++ ++ ++ } ++ ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++* Function: Hal_SDMMC_SetNrcDelay ++* @author jeremy.wang (2015/8/18) ++ * Desc: According as Current Clock to Set Nrc Delay ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u32RealClk : Real Clock ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetNrcDelay(IPEmType eIP, U32_T u32RealClk) ++{ ++ ++ if( u32RealClk >= 8000000 ) //>=8MHz ++ gu16_WT_NRC[eIP] = 1; ++ else if( u32RealClk >= 4000000 ) //>=4MHz ++ gu16_WT_NRC[eIP] = 2; ++ else if( u32RealClk >= 2000000 ) //>=2MHz ++ gu16_WT_NRC[eIP] = 4; ++ else if( u32RealClk >= 1000000 ) //>=1MHz ++ gu16_WT_NRC[eIP] = 8; ++ else if( u32RealClk >= 400000 ) //>=400KHz ++ gu16_WT_NRC[eIP] = 20; ++ else if( u32RealClk >= 300000 ) //>=300KHz ++ gu16_WT_NRC[eIP] = 27; ++ else if( u32RealClk >= 100000 ) //>=100KHz ++ gu16_WT_NRC[eIP] = 81; ++ else if(u32RealClk==0) ++ gu16_WT_NRC[eIP] = 100; //Add Default Value (100us) ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++* Function: Hal_SDMMC_SetCmdToken ++* @author jeremy.wang (2015/10/12) ++* Desc: Set Cmd Token ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u8Cmd : SD Command ++ * @param u32Arg : SD Argument ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetCmdToken(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg) ++{ ++ gst_RspStruct[eIP].u8Cmd = u8Cmd; ++ gst_RspStruct[eIP].u32Arg = u32Arg; ++ ++ CARD_REG(A_CFIFO_OFFSET(eIP, 0)) = (((U8_T)(u32Arg>>24))<<8) | (0x40 + u8Cmd); ++ CARD_REG(A_CFIFO_OFFSET(eIP, 1)) = (((U8_T)(u32Arg>>8))<<8) | ((U8_T)(u32Arg>>16)); ++ CARD_REG(A_CFIFO_OFFSET(eIP, 2)) = (U8_T)u32Arg; ++ ++ TR_H_SDMMC(prtstring("[S_")); TR_H_SDMMC(prtUInt(eIP)); ++ TR_H_SDMMC(prtstring("] CMD_")); TR_H_SDMMC(prtUInt(u8Cmd)); ++ ++ TR_H_SDMMC(prtstring(" (")); ++ TR_H_SDMMC(prtU32Hex(u32Arg)); ++ TR_H_SDMMC(prtstring(")")); ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++* Function: Hal_SDMMC_GetRspToken ++* @author jeremy.wang (2015/7/9) ++* Desc: Get Command Response Info ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * ++ * @return RspStruct* : Response Struct ++ ----------------------------------------------------------------------------------------------------------*/ ++RspStruct* Hal_SDMMC_GetRspToken(IPEmType eIP) ++{ ++ U8_T u8Pos; ++ ++ TR_H_SDMMC(prtstring(" =>Rsp: (")); ++ TR_H_SDMMC(prtU32Hex((U16_T)gst_RspStruct[eIP].eErrCode)); ++ TR_H_SDMMC(prtstring(")\r\n")); ++ ++ for(u8Pos=0; u8Pos<0x10; u8Pos++ ) ++ gst_RspStruct[eIP].u8ArrRspToken[u8Pos] = 0; ++ ++ TR_H_SDMMC(prtstring("[")); ++ ++ for(u8Pos=0; u8Pos < gst_RspStruct[eIP].u8RspSize; u8Pos++) ++ { ++ gst_RspStruct[eIP].u8ArrRspToken[u8Pos] = _BUF_GetByteFromRegAddr((volatile void *)A_SD_CFIFO_POS(eIP), u8Pos); ++ ++ TR_H_SDMMC(prtU8Hex(gst_RspStruct[eIP].u8ArrRspToken[u8Pos])); ++ TR_H_SDMMC(prtstring(", ")); ++ ++ } ++ TR_H_SDMMC(prtstring("]")); ++ ++ TR_H_SDMMC(prtstring("\r\n\r\n")); ++ ++ return &gst_RspStruct[eIP]; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_TransCmdSetting ++ * @author jeremy.wang (2011/12/1) ++ * Desc: For Data Transfer Setting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eTransType : CIFD/DMA/NONE ++ * @param u16BlkCnt : Block Cnt ++ * @param u16BlkSize : Block Size ++ * @param u32BufAddr : Memory Address (32bits) ++ * @param pu8Buf : If run CIFD, it neet the buf pointer to do io between CIFD and Buf ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_TransCmdSetting(IPEmType eIP, TransEmType eTransType, U16_T u16BlkCnt, U16_T u16BlkSize, volatile U32_T u32BufAddr, volatile U8_T *pu8Buf) ++{ ++ ++#if(!EN_BYTEMODE) ++ #if (D_MIU_WIDTH==4) ++ U8_T u8BitMask[8]={0x0F,0x0E,0x0C,0x08}; ++ #else ++ U8_T u8BitMask[8]={0xFF,0xFE,0xFC,0xF8,0xF0,0xE0,0xC0,0x80}; ++ #endif ++#endif ++ ++ if(eTransType == EV_DMA) ++ { ++ /***** Block Count ******/ ++ CARD_REG(A_JOB_BL_CNT_REG(eIP)) = u16BlkCnt; ++ ++ /****** Block Size and DMA Addr******/ ++#if(EN_BYTEMODE) ++ CARD_REG(A_SDIO_ADDR1_REG(eIP)) = (U16_T)(u32BufAddr>>16); ++ CARD_REG(A_SDIO_ADDR0_REG(eIP)) = (U16_T)(u32BufAddr); ++ CARD_REG(A_SDIO_CTL_REG(eIP)) = u16BlkSize | R_SDIO_BLK_MOD; ++#else ++ CARD_REG(A_MIU_DMA1_REG(eIP)) = (U16_T)(((u32BufAddr&0xFFFFFFF)/D_MIU_WIDTH)>>16); ++ CARD_REG(A_MIU_DMA0_REG(eIP)) = (U16_T)((u32BufAddr)/D_MIU_WIDTH); ++ CARD_REG(A_DAM_OFFSET_REG9(eIP)) = u8BitMask[u32BufAddr&(D_MIU_WIDTH-1)]; ++ CARD_REG(A_SDIO_CTL_REG(eIP)) = 0x00; ++#endif ++ ++ CARD_REG(A_CARD_WD_CNT_REG(eIP)) = 0x00; ++ ++ } ++ else //CIFD ++ { ++ if( (u16BlkSize>=512) || (u16BlkSize==0)) ++ CARD_REG(A_CARD_WD_CNT_REG(eIP)) = 0; ++ else ++ { ++ CARD_REG(A_CARD_WD_CNT_REG(eIP)) = (u16BlkSize/2); //Word Count (Max: 256Words==>512Bytes) ++ } ++ ++ CARD_REG(A_SDIO_CTL_REG(eIP)) = 0x00; ++ ++ gpu8Buf[eIP] = pu8Buf; ++ ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SendCmdAndWaitProcess ++ * @author jeremy.wang (2011/11/28) ++ * Desc: Send CMD and Wait Process ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eTransType : CIFD/DMA/NONE ++ * @param eCmdType : CMDRSP/READ/WRITE ++ * @param eRspType : R1/R2/R3/... ++ * @param bCloseClk : Close Clock or not ++ * ++ * @return RspErrEmType : Response Error Code ++ ----------------------------------------------------------------------------------------------------------*/ ++RspErrEmType Hal_SDMMC_SendCmdAndWaitProcess(IPEmType eIP, TransEmType eTransType, CmdEmType eCmdType, SDMMCRspEmType eRspType, BOOL_T bCloseClk) ++{ ++ U32_T u32WaitMS = WT_EVENT_RSP; ++ U16_T u16WaitMIEEvent = R_SD_CMD_END; ++ U16_T u16MIE_PATH_MMA_EN = (U8_T)eTransType; ++ U16_T u16MIE_TRANS_END = (u16MIE_PATH_MMA_EN<<14) | (u16MIE_PATH_MMA_EN<<11) | ((!u16MIE_PATH_MMA_EN)<<2); ++ U16_T u16VAR_SD_MODE = _REG_GetPortSetting(eIP) | gu16_SD_MODE_DatLine[eIP] | gu16_SD_MODE_DatSync[eIP] ; ++ ++ CARD_REG(A_RSP_SIZE_REG(eIP)) = V_RSP_SIZE_INIT | ((U8_T)eRspType); ++ CARD_REG(A_CMD_SIZE_REG(eIP)) = V_CMD_SIZE_INIT; ++ CARD_REG(A_MIE_PATH_CTL_REG(eIP)) = V_MIE_PATH_INIT; ++ CARD_REG(A_EMMC_PATH_CTL_REG(eIP)) = 0; ++ CARD_REG(A_SD_MODE_REG(eIP)) = V_SD_MODE_INIT | u16VAR_SD_MODE | (eTransType>>8) | (gb_SDIODevice[eIP] ? 0 : (u16MIE_PATH_MMA_EN<<11)); ++ CARD_REG(A_SD_CTL_REG(eIP)) = V_SD_CTL_INIT | gu16_SD_CTL_SDIO_Det[eIP] | gu16_SD_CTL_SDIO_IntMode[eIP] | (eRspType>>12) | (eCmdType>>4); ++ ++ CARD_REG(A_MMA_PRI_REG_REG(eIP)) = V_MMA_PRI_INIT | (eCmdType>>6); ++ ++ CARD_REG_SETBIT(A_NC_REORDER_REG(eIP), V_NC_REORDER_INIT | gu16_PAD_IN_SEL[eIP]); ++ CARD_REG(A_EMMC_BOOTCFG_REG(eIP)) = V_SD_BOOTCFG_INIT | gu16_EMMC_BOOTCFG_REG[eIP]; ++ ++ Hal_Timer_uDelay(gu16_WT_NRC[eIP]); ++ ++ /*if ( _REG_WaitDat0HI(eIP, WT_DAT0HI_END) ) ++ return _SDMMC_ErrProcess(eIP, EV_STS_DAT0_BUSY, TRUE, __LINE__);*/ ++ ++ if ( _REG_ClearSDSTS(eIP, RT_CLEAN_SDSTS) || _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__); ++ ++ if ( (eTransType== EV_DMA) && _REG_WaitFIFOClkRdy(eIP, eCmdType, WT_FIFO_CLK_RDY) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_FIFO_NRDY, bCloseClk, __LINE__); ++ ++/*#if(EN_BIND_CARD_INT) ++ //Because IP has bug, and it may have chance to access the same register, so we need to do os lock outside ++ Hal_CARD_INT_SetMIEIntEn(eIP, EV_INT_SD, V_MIE_INT_EN_INIT | u16MIE_TRANS_END); ++#endif*/ ++ ++ if(eCmdType==EV_CMDREAD) ++ { ++ u16WaitMIEEvent |= u16MIE_TRANS_END; ++ u32WaitMS |= WT_EVENT_READ; ++ CARD_REG_SETBIT(A_MIE_PATH_CTL_REG(eIP), u16MIE_PATH_MMA_EN); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_SD_CMD_EN | R_SD_DTRX_EN) ); ++ } ++ else ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_SD_CMD_EN); ++ ++ if ( _REG_WaitMIEEvent(eIP, u16WaitMIEEvent, u32WaitMS) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ //====== Trans Data between CIFD and Buf ====== ++ if( eTransType==EV_CIF ) ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)gpu8Buf[eIP], (U8_T)CARD_REG(A_CARD_WD_CNT_REG(eIP)) ); ++ ++ if ( (eRspType == EV_R1B) && _REG_WaitDat0HI(eIP, WT_DAT0HI_END) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_DAT0_BUSY, bCloseClk, __LINE__); ++ else if( (eRspType == EV_R3) || (eRspType == EV_R4) ) // For IP CRC bug ++ CARD_REG(A_SD_STS_REG(eIP)) = R_SD_CMDRSP_CERR; //Clear CMD CRC Error ++ ++ ++ if( (eCmdType==EV_CMDWRITE) && (!M_REG_STSERR(eIP)) ) ++ { ++ if ( _REG_ClearSDSTS(eIP, RT_CLEAN_SDSTS) || _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__); ++ ++ CARD_REG_SETBIT(A_MIE_PATH_CTL_REG(eIP), u16MIE_PATH_MMA_EN); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_SD_DTRX_EN); ++ ++ if ( _REG_WaitMIEEvent(eIP, u16MIE_TRANS_END, WT_EVENT_WRITE) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ if ( (eTransType== EV_CIF) && _REG_WaitDat0HI(eIP, WT_DAT0HI_END) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_DAT0_BUSY, bCloseClk, __LINE__); ++ ++ } ++ ++ return _SDMMC_EndProcess(eIP, eCmdType, (RspErrEmType)M_REG_STSERR(eIP), bCloseClk, __LINE__); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_RunBrokenDmaAndWaitProcess ++ * @author jeremy.wang (2011/12/1) ++ * Desc: For Broken DMA Data Transfer ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eCmdType : READ/WRITE ++ * ++ * @return RspErrEmType : Response Error Code ++ ----------------------------------------------------------------------------------------------------------*/ ++RspErrEmType Hal_SDMMC_RunBrokenDmaAndWaitProcess(IPEmType eIP, CmdEmType eCmdType) ++{ ++ U32_T u32WaitMS = 0; ++ ++ if(eCmdType==EV_CMDREAD) ++ u32WaitMS = WT_EVENT_READ; ++ else if(eCmdType==EV_CMDWRITE) ++ u32WaitMS = WT_EVENT_WRITE; ++ ++ if ( _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, FALSE, __LINE__); ++ ++ if (_REG_WaitFIFOClkRdy(eIP, eCmdType, WT_FIFO_CLK_RDY)) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_FIFO_NRDY, FALSE, __LINE__); ++ ++ CARD_REG_SETBIT(A_MIE_PATH_CTL_REG(eIP), R_MMA_ENABLE); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_SD_DTRX_EN); ++ ++ if ( _REG_WaitMIEEvent(eIP, R_CARD_DMA_END|R_MMA_LSDONE_END, u32WaitMS) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, FALSE, __LINE__); ++ ++ return _SDMMC_EndProcess(eIP, eCmdType, (RspErrEmType)M_REG_STSERR(eIP), FALSE, __LINE__); ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Operation Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_ClkCtrl ++ * @author jeremy.wang (2015/11/4) ++ * Desc: Enable IP clock output ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ * @param u16DelayMs : Delay ms to Specail Purpose ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_ClkCtrl(IPEmType eIP, BOOL_T bEnable, U16_T u16DelayMs) ++{ ++ CARD_REG(A_MIE_PATH_CTL_REG(eIP)) = V_MIE_PATH_INIT; ++ CARD_REG(A_SD_MODE_REG(eIP)) = _REG_GetPortSetting(eIP); ++ ++ if( bEnable ) ++ CARD_REG_SETBIT(A_SD_MODE_REG(eIP), R_SD_CLK_EN ); ++ else ++ CARD_REG_CLRBIT(A_SD_MODE_REG(eIP), R_SD_CLK_EN ); ++ ++ Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_OtherPreUse ++* @author jeremy.wang (2015/7/17) ++* Desc: Use this for avoid SD/EMMC to use FCIE at the same time ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return BOOL_T : (TRUE: Other driver usnig) ++----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_SDMMC_OtherPreUse(IPEmType eIP) ++{ ++ if(CARD_REG(A_EMMC_PATH_CTL_REG(eIP)) & R_EMMC_EN) //Emmc Path ++ return (TRUE); ++ ++ if(!(CARD_REG(A_MIE_PATH_CTL_REG(eIP)) & R_SD_EN)) //Not SD Path ++ return (TRUE); ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_ErrGroup ++ * @author jeremy.wang (2015/10/28) ++ * Desc: transfer response error type to group error type ++ * ++ * @param eRspErrType : Response Error Type ++ * ++ * @return ErrGrpEmType : Group Error Type ++ ----------------------------------------------------------------------------------------------------------*/ ++ErrGrpEmType Hal_SDMMC_ErrGroup(RspErrEmType eRspErrType) ++{ ++ ++ switch((U16_T)eRspErrType) ++ { ++ case EV_STS_OK: ++ return EV_EGRP_OK; ++ ++ case EV_STS_NORSP: ++ case EV_STS_RIU_ERR: ++ case EV_STS_MIE_TOUT: ++ case EV_STS_FIFO_NRDY: ++ case EV_STS_DAT0_BUSY: ++ return EV_EGRP_TOUT; ++ ++ case EV_STS_DAT_CERR: ++ case EV_STS_DAT_STSERR: ++ case EV_STS_DAT_STSNEG: ++ case EV_STS_RSP_CERR: ++ return EV_EGRP_COMM; ++ ++ default: ++ return EV_EGRP_OTHER; ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_Reset ++ * @author jeremy.wang (2011/11/30) ++ * Desc: Reset IP to avoid IP dead + Touch CIFD first time to avoid latch issue ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_Reset(IPEmType eIP) ++{ ++ _REG_ResetIP(eIP); ++ _REG_CIFDEmptyRW(eIP); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_StopProcessCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Stop process to avoid long time waiting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_StopProcessCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ gb_StopWProc[eIP] = bEnable; ++ ++#if(EN_BIND_CARD_INT) ++ if ( gb_StopWProc[eIP] ) ++ Hal_CARD_INT_StopWaitMIEEventCtrl(eIP, TRUE); ++ else ++ Hal_CARD_INT_StopWaitMIEEventCtrl(eIP, FALSE); ++#endif ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Information ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_DumpMemTool ++* @author jeremy.wang (2015/7/29) ++* Desc: Help us to dump memory ++* ++* @param u8ListNum : Each List Num include 16 bytes ++* @param pu8Buf : Buffer Pointer ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_DumpMemTool(U8_T u8ListNum, volatile U8_T *pu8Buf) ++{ ++ U16_T u16Pos=0; ++ U8_T u8ListPos; ++ U32_T u32BufAddr = (U32_T)pu8Buf; ++ prtstring("\r\n $[Prt MEM_DATA: "); ++ prtU32Hex(u32BufAddr); ++ prtstring(" ]\r\n"); ++ ++ for(u8ListPos=0 ; u8ListPos >8); ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_GetMIEEvent ++ * @author jeremy.wang (2014/6/10) ++ * Desc: ++ * ++ * @param eIP : ++ * ++ * @return U16_T : ++ ----------------------------------------------------------------------------------------------------------*/ ++U16_T Hal_SDMMC_GetMIEEvent(IPEmType eIP) ++{ ++ return CARD_REG(A_MIE_EVENT_REG(eIP)); ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC SDIO Setting ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SDIODeviceCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Enable SDIO device for do something for SDIO case ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SDIODeviceCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ if(bEnable) ++ gb_SDIODevice[eIP] = TRUE; ++ else ++ gb_SDIODevice[eIP] = FALSE; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SDIOIntDetCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Enable SDIO interrupt detection ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SDIOIntDetCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(bEnable) ++ { ++ if(!gu16_SDIO_DetOn_RunOnce[eIP]) ++ { ++ gu16_SDIO_DetOn_RunOnce[eIP] = TRUE; // For IP Bug, We just Run Once to avoid two thread use gu16_SD_CTL_SDIO_Det ++ gu16_SD_CTL_SDIO_Det[eIP] = R_SDIO_DET_ON ; //Always On !! for IP Design Limitation ++ } ++ } ++ ++ #if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_SetMIEIntEn_ForSDIO(eIP, EV_INT_SD, bEnable); ++ #endif // End of EN_BIND_CARD_INT ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetSDIOIntBeginSetting ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Set SDIO Int begin setting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u8Cmd : SDIO Command ++ * @param u32Arg : SDIO Argument ++ * @param eCmdType : CMDRSP/READ/WRITE ++ * @param u16BlkCnt : Block Cnt ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetSDIOIntBeginSetting(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg, CmdEmType eCmdType, U16_T u16BlkCnt) ++{ ++ BOOL_T bSDIOAbortMode = (u8Cmd == 52) && ( (u32Arg & 0x83FFFE00) == 0x80000C00); ++ ++ gu16_SD_CTL_SDIO_IntMode[eIP] = 0; ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(eCmdType != EV_CMDRSP) ++ { ++ if(u16BlkCnt == 1) ++ gu16_SD_CTL_SDIO_IntMode[eIP] = R_SDIO_INT_MOD1; ++ else ++ { ++ //gu16_SD_CTL_SDIO_IntMode[eIP] = R_SDIO_INT_MOD0 | R_SDIO_INT_MOD1; ++ /****** IP Bug, We could not use Multiple block Mode *******/ ++ gu16_SD_CTL_SDIO_Det[eIP] = 0; ++ } ++ } ++ else if ( (u8Cmd == 12) || bSDIOAbortMode) ++ { ++ gu16_SD_CTL_SDIO_IntMode[eIP] = R_SDIO_INT_MOD0; ++ } ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetSDIOIntEndSetting ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Set SDIO Int end setting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eRspErr : Response Error Type ++ * @param u16BlkCnt : Block Cnt ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetSDIOIntEndSetting(IPEmType eIP, RspErrEmType eRspErr, U16_T u16BlkCnt) ++{ ++ U16_T u16RspErr = (U16_T)eRspErr; ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(u16BlkCnt>1) ++ { ++ /****** IP Bug, We could not use Multiple block Mode *******/ ++ gu16_SD_CTL_SDIO_Det[eIP] = R_SDIO_DET_ON; ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_SDIO_DET_ON); ++ } ++ ++ if(u16RspErr>0) ++ { ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_SDIO_INT_MOD0 | R_SDIO_INT_MOD1); ++ } ++ } ++} ++ ++ ++ ++//*********************************************************************************************************** ++// SDMMC Interrupt Setting ++//*********************************************************************************************************** ++ ++#if(EN_BIND_CARD_INT) ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_MIEIntCtrl ++ * @author jeremy.wang (2015/11/2) ++ * Desc: Enable MIE event interrupt control ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_MIEIntCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ Hal_CARD_INT_MIEIntCtrl(eIP, EV_INT_SD, bEnable); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetMIEIntEn_ForV4 ++ * @author jeremy.wang (2014/5/28) ++ * Desc: Design a MIE Int enable funtion for host semaphone process to avoid access the same register issue ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param eTransType : CIFD/DMA/NONE ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetMIEIntEn_ForV4(IPEmType eIP, TransEmType eTransType) ++{ ++ U16_T u16MIE_PATH_MMA_EN = (U8_T)eTransType; ++ U16_T u16MIE_TRANS_END = (u16MIE_PATH_MMA_EN<<14) | (u16MIE_PATH_MMA_EN<<11) | ((!u16MIE_PATH_MMA_EN)<<2); ++ Hal_CARD_INT_SetMIEIntEn(eIP, EV_INT_SD, V_MIE_INT_EN_INIT | u16MIE_TRANS_END); ++ ++} ++ ++ ++#endif // End of EN_BIND_CARD_INT ++ +diff --git a/drivers/mstar/sdmmc/src/hal_sdmmc_v5.c b/drivers/mstar/sdmmc/src/hal_sdmmc_v5.c +new file mode 100644 +index 00000000..a7ef65af +--- /dev/null ++++ b/drivers/mstar/sdmmc/src/hal_sdmmc_v5.c +@@ -0,0 +1,1324 @@ ++/*************************************************************************************************************** ++ * ++ * FileName hal_sdmmc_v5.c (Driver Version) ++ * @author jeremy.wang (2015/07/06) ++ * Desc: ++ * HAL SD Driver will support basic SD function but not flow process. ++ * (1) It included Register and Buffer opertion code. ++ * (2) h file will has APIs for Driver, but just SD abstract, not register abstract. ++ * ++ ***************************************************************************************************************/ ++ ++#include "../inc/hal_sdmmc_v5.h" ++#include "../inc/hal_card_timer.h" ++ ++#if(EN_BIND_CARD_INT) ++#include "../inc/hal_card_intr_v5.h" //inlcue but may not use ++#endif ++ ++ ++//*********************************************************************************************************** ++// Config Setting (Internel) ++//*********************************************************************************************************** ++ ++// Enable Setting ++//----------------------------------------------------------------------------------------------------------- ++#define EN_TRFUNC (FALSE) ++#define EN_DUMPREG (TRUE) ++#define EN_BYPASSMODE (FALSE) //BYPASS MODE or ADVANCE MODE(SDR/DDR) ++ ++ ++// Retry Times ++//----------------------------------------------------------------------------------------------------------- ++#define RT_CLEAN_SDSTS 3 ++#define RT_CLEAN_MIEEVENT 3 ++ ++// Wait Time ++//----------------------------------------------------------------------------------------------------------- ++#define WT_DAT0HI_END 1000 //(ms) ++#define WT_EVENT_CIFD 500 //(ms) ++#define WT_RESET 100 //(ms) ++ ++//*********************************************************************************************************** ++//*********************************************************************************************************** ++ ++// Reg Static Init Setting ++//----------------------------------------------------------------------------------------------------------- ++#define V_MIE_PATH_INIT 0 ++#define V_MMA_PRI_INIT (R_MIU_R_PRIORITY|R_MIU_W_PRIORITY) ++#define V_MIE_INT_EN_INIT (R_DATA_END_IEN|R_CMD_END_IEN|R_SDIO_INT_IEN|R_BUSY_END_IEN) ++#define V_RSP_SIZE_INIT 0 ++#define V_CMD_SIZE_INIT (5<<8) ++#define V_SD_CTL_INIT 0 ++#define V_SD_MODE_INIT (R_CLK_EN) // Add ++#define V_SDIO_MODE_INIT 0 ++#define V_DDR_MODE_INIT 0 ++ ++ ++// Mask Range ++//----------------------------------------------------------------------------------------------------------- ++#define M_SD_ERRSTS (R_DAT_RD_CERR|R_DAT_WR_CERR|R_DAT_WR_TOUT|R_CMD_NORSP|R_CMDRSP_CERR|R_DAT_RD_TOUT) ++#define M_SD_MIEEVENT (R_DATA_END|R_CMD_END|R_ERR_STS|R_BUSY_END_INT|R_R2N_RDY_INT) ++#define M_RST_STS (R_RST_MIU_STS|R_RST_MIE_STS|R_RST_MCU_STS) ++ ++ ++// Mask Reg Value ++//----------------------------------------------------------------------------------------------------------- ++#define M_REG_STSERR(IP) (CARD_REG(A_SD_STS_REG(IP)) & M_SD_ERRSTS) ++#define M_REG_SDMIEEvent(IP) (CARD_REG(A_MIE_EVENT_REG(IP)) & M_SD_MIEEVENT) ++#define M_REG_GETDAT0(IP) (CARD_REG(A_SD_STS_REG(IP)) & R_DAT0) ++ ++ ++//----------------------------------------------------------------------------------------------------------- ++//IP_FCIE or IP_SDIO Register Basic Address ++//----------------------------------------------------------------------------------------------------------- ++#define A_SD_REG_POS(IP) GET_CARD_BANK(IP, 0) ++#define A_SD_CFIFO_POS(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x20) //Always at FCIE5 ++#define A_SD_CIFD_POS(IP) GET_CARD_BANK(IP, 1) ++ ++#define A_SD_CIFD_R_POS(IP) GET_CARD_REG_ADDR(A_SD_CIFD_POS(IP), 0x00) ++#define A_SD_CIFD_W_POS(IP) GET_CARD_REG_ADDR(A_SD_CIFD_POS(IP), 0x20) ++ ++#define A_MIE_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x00) ++#define A_MMA_PRI_REG_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x02) ++#define A_DMA_ADDR_15_0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x03) ++#define A_DMA_ADDR_31_16_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x04) ++#define A_DMA_LEN_15_0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x05) ++#define A_DMA_LEN_31_16_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x06) ++#define A_MIE_FUNC_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x07) ++#define A_JOB_BLK_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x08) ++#define A_BLK_SIZE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x09) ++#define A_CMD_RSP_SIZE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0A) ++#define A_SD_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0B) ++#define A_SD_CTL_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0C) ++#define A_SD_STS_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0D) ++#define A_BOOT_MOD_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0E) ++#define A_DDR_MOD_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x0F) ++#define A_DDR_TOGGLE_CNT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x10) ++#define A_SDIO_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x11) ++#define A_TEST_MODE_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x15) ++ ++#define A_WR_SBIT_TIMER_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x17) ++#define A_RD_SBIT_TIMER_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x18) ++ ++#define A_SDIO_DET_ON(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x2F) ++ ++#define A_CIFD_EVENT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x30) ++#define A_CIFD_INT_EN_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x31) ++ ++#define A_BOOT_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x37) ++ ++#define A_DBG_BUS0_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x38) ++#define A_DBG_BUS1_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x39) ++#define A_FCIE_RST_REG(IP) GET_CARD_REG_ADDR(A_SD_REG_POS(IP), 0x3F) ++ ++#define A_CFIFO_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CFIFO_POS(IP), OFFSET) ++#define A_CIFD_R_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CIFD_R_POS(IP), OFFSET) ++#define A_CIFD_W_OFFSET(IP, OFFSET) GET_CARD_REG_ADDR(A_SD_CIFD_W_POS(IP), OFFSET) ++ ++ ++// Reg Dynamic Variable ++//----------------------------------------------------------------------------------------------------------- ++static RspStruct gst_RspStruct[3]; ++static volatile BOOL_T gb_StopWProc[3] = {0}; ++static volatile U16_T gu16_WT_NRC[3] = {0}; //Waiting Time for Nrc (us) ++ ++static volatile U16_T gu16_SD_MODE_DatLine[3] = {0}; ++ ++static volatile U16_T gu16_DDR_MODE_REG[3] = {0}; ++static volatile U16_T gu16_DDR_MODE_REG_ForR2N[3] = {0}; ++ ++static volatile BOOL_T gb_SDIODevice[3] = {0}; ++static volatile U16_T gu16_SDIO_MODE_IntMode[3] = {0}; ++static volatile U16_T gu16_SDIO_IntEn_RunOnce[3] = {0}; ++ ++ ++static volatile U8_T* gpu8Buf[3]; ++ ++ ++// Trace Funcion ++//----------------------------------------------------------------------------------------------------------- ++#if (EN_TRFUNC) ++ #define TR_H_SDMMC(p) p ++#else ++ #define TR_H_SDMMC(p) ++#endif ++ ++ ++// Register Opertation Define ==> For FCIE5 Special FCIE/SDIO Function Ctrl Setting ++//----------------------------------------------------------------------------------------------------------- ++static U16_T _REG_GetMIEFunCtlSetting(IPEmType eIP) ++{ ++ PortEmType ePort = GET_CARD_PORT(eIP); ++ ++ return (ePort==EV_PFCIE5_FCIE ? R_SD_EN : R_SDIO_MODE); ++} ++ ++ ++// Register Operation Define ==> For Clean Reg and Special Case ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_ClearSDSTS(IPEmType eIP, U8_T u8Retry) ++{ ++ do ++ { ++ CARD_REG_SETBIT(A_SD_STS_REG(eIP), M_SD_ERRSTS); ++ ++ if ( gb_StopWProc[eIP] ) ++ break; ++ ++ if ( !M_REG_STSERR(eIP) ) ++ return EV_OK; ++ else if(!u8Retry) ++ break; ++ ++ } while(u8Retry--); ++ ++ return EV_FAIL; //mark for coverity scan ++} ++ ++ ++// Register Operation Define ==> For Clear MIE Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_ClearMIEEvent(IPEmType eIP, U8_T u8Retry) ++{ ++ /****** Clean global MIEEvent for Interrupt ******/ ++#if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_ClearMIEEvent(eIP); ++#endif ++ ++ /****** Clean MIEEvent Reg *******/ ++ do ++ { ++ CARD_REG(A_MIE_EVENT_REG(eIP)) = M_SD_MIEEVENT; ++ ++ if ( gb_StopWProc[eIP] ) ++ break; ++ ++ if ( !M_REG_SDMIEEvent(eIP) ) ++ return EV_OK; ++ else if( !u8Retry ) ++ break; ++ ++ }while( u8Retry-- ); ++ ++ return EV_FAIL; //mark for coverity scan ++ ++} ++ ++ ++// Register Operation Define ==> For Wait DAT0 High ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitDat0HI(IPEmType eIP, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++#if(EN_BIND_CARD_INT) ++ if ( Hal_CARD_INT_MIEIntRunning(eIP, EV_INT_SD) ) // Interrupt Mode ++ { ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), R_BUSY_DET_ON ); ++ ++ if ( !Hal_CARD_INT_WaitMIEEvent(eIP, R_BUSY_END_INT, u32WaitMs) ) ++ return EV_FAIL; ++ else ++ return EV_OK; ++ ++ } ++ else // Polling Mode ++#endif ++ { ++ do ++ { ++ ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if ( M_REG_GETDAT0(eIP) ) ++ return EV_OK; ++ ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while( u32DiffTime <= (u32WaitMs*1000) ); ++ ++ } ++ return EV_FAIL; ++ ++} ++ ++ ++// Register Operation Define ==> For Wait MIE Event or CIFD Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _REG_WaitEvent(IPEmType eIP, IPEventEmType eEvent, U16_T u16ReqEvent, U32_T u32WaitMs) ++{ ++ U32_T u32DiffTime = 0; ++ ++#if(EN_BIND_CARD_INT) ++ if ( Hal_CARD_INT_MIEIntRunning(eIP, EV_INT_SD) ) // Interrupt Mode ++ { ++ if(eEvent == EV_MIE) ++ { ++ if ( !Hal_CARD_INT_WaitMIEEvent(eIP, u16ReqEvent, u32WaitMs) ) ++ return EV_FAIL; ++ else ++ return EV_OK; ++ } ++ ++ } ++ else // Polling Mode ++#endif ++ { ++ do ++ { ++ ++ if ( gb_StopWProc[eIP] ) ++ return EV_FAIL; ++ ++ if(eEvent == EV_MIE) ++ { ++ if ( (CARD_REG(A_MIE_EVENT_REG(eIP))&u16ReqEvent) == u16ReqEvent ) ++ return EV_OK; ++ } ++ else if(eEvent == EV_CIFD ) ++ { ++ if ( (CARD_REG(A_CIFD_EVENT_REG(eIP))&u16ReqEvent) == u16ReqEvent ) ++ return EV_OK; ++ } ++ ++ Hal_Timer_mDelay(1); ++ u32DiffTime++; ++ }while(u32DiffTime <= u32WaitMs); ++ ++ } ++ ++ return EV_FAIL; ++ ++} ++ ++ ++// Register Operation Define ==> For Software Reset ++//----------------------------------------------------------------------------------------------------------- ++static void _REG_ResetIP(IPEmType eIP) ++{ ++ U32_T u32DiffTime = 0; ++ ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_JOB_START); //Clear For Safe ? ++ ++ CARD_REG_CLRBIT(A_FCIE_RST_REG(eIP), R_FCIE_SOFT_RST); ++ ++ do ++ { ++ if( (CARD_REG(A_FCIE_RST_REG(eIP)) & M_RST_STS) == M_RST_STS ) ++ break; ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ }while ( u32DiffTime <= (1000*WT_RESET) ); ++ ++ if ( u32DiffTime > (1000*WT_RESET) ) ++ prtstring("[HSD] IP Reset Switch Low Fail !!\r\n"); ++ ++ ++ u32DiffTime = 0; ++ CARD_REG_SETBIT(A_FCIE_RST_REG(eIP), R_FCIE_SOFT_RST); ++ ++ do ++ { ++ if( (CARD_REG(A_FCIE_RST_REG(eIP)) & M_RST_STS) == 0 ) ++ break; ++ Hal_Timer_uDelay(1); ++ u32DiffTime++; ++ ++ }while ( u32DiffTime <= (1000* WT_RESET) ); ++ ++ if ( u32DiffTime > (1000*WT_RESET) ) ++ prtstring("[HSD] IP Reset Switch High Fail !!\r\n"); ++ ++ ++ ++} ++ ++ ++// IP Buffer Operation => Get Byte Value form Register ++//----------------------------------------------------------------------------------------------------------- ++static U8_T _BUF_GetByteFromRegAddr(volatile void *pBuf, U16_T u16Pos) ++{ ++ if(u16Pos & 0x1) ++ return CARD_REG_H8(GET_CARD_REG_ADDR(pBuf, u16Pos>>1)); ++ else ++ return CARD_REG_L8(GET_CARD_REG_ADDR(pBuf, u16Pos>>1)); ++ ++} ++ ++ ++// IP Buffer Operation => CIFD FIFO Buffer Operation Define ++//----------------------------------------------------------------------------------------------------------- ++void _BUF_CIFD_DATA_IO(IPEmType eIP, CmdEmType eCmdType, volatile U16_T *pu16Buf, U8_T u8WordCnt) ++{ ++ U8_T u8Pos = 0; ++ ++ for ( u8Pos = 0; u8Pos < u8WordCnt; u8Pos++ ) ++ { ++ if ( eCmdType==EV_CMDREAD ) ++ pu16Buf[u8Pos] = CARD_REG(A_CIFD_R_OFFSET(eIP, u8Pos)); ++ else ++ CARD_REG(A_CIFD_W_OFFSET(eIP, u8Pos)) = pu16Buf[u8Pos]; ++ } ++ ++} ++ ++ ++// IP Buffer Operation => CIFD FIFO Buffer Operation for waiting FCIE5 special Event ++//----------------------------------------------------------------------------------------------------------- ++static RetEmType _BUF_CIFD_WaitEvent(IPEmType eIP, CmdEmType eCmdType, volatile U8_T *pu8R2NBuf) ++{ ++ U8_T u8RegionNo = 0, u8RegionMax = 0, u8RemainByte = 0; ++ U32_T u32_TranLen = CARD_REG(A_DMA_LEN_15_0_REG(eIP)) + ( CARD_REG(A_DMA_LEN_31_16_REG(eIP)) << 16 ); ++ ++ u8RemainByte = u32_TranLen & (64-1); // u32_TranLen % 64 ++ u8RegionMax = (u32_TranLen>>6) + (u8RemainByte ? 1: 0); ++ ++ for(u8RegionNo=0; u8RegionNo0) ) ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), u8RemainByte/2); ++ else ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), 32); ++ ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_WBUF_FULL; ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_WBUF_EMPTY_TRIG; ++ } ++ else // Write ++ { ++ if ( (u8RegionNo == (u8RegionMax-1)) && (u8RemainByte>0) ) ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), u8RemainByte/2); ++ else ++ _BUF_CIFD_DATA_IO(eIP, eCmdType, (volatile U16_T *)(pu8R2NBuf + (u8RegionNo << 6)), 32); ++ ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_RBUF_FULL_TRIG; ++ ++ if ( _REG_WaitEvent(eIP, EV_CIFD, R_RBUF_EMPTY, WT_EVENT_CIFD) ) ++ return EV_FAIL; ++ ++ CARD_REG(A_CIFD_EVENT_REG(eIP)) = R_RBUF_EMPTY; ++ ++ } ++ ++ } ++ ++ return EV_OK; ++ ++} ++ ++ ++// SDMMC Internel Logic Function ++//----------------------------------------------------------------------------------------------------------- ++static void _SDMMC_REG_Dump(IPEmType eIP) ++{ ++ ++#if (EN_DUMPREG) ++ ++ U8_T u8Pos, u8DGMode; ++ ++ prtstring("\n----------------------------------------------------\r\n"); ++ prtstring(" CMD_"); ++ prtUInt(gst_RspStruct[eIP].u8Cmd); ++ prtstring(" (Arg: "); ++ prtU32Hex(gst_RspStruct[eIP].u32Arg); ++ prtstring(") [Line: "); ++ prtUInt(gst_RspStruct[eIP].u32ErrLine); ++ prtstring("]\r\n"); ++ prtstring("----------------------------------------------------\r\n"); ++ ++ for(u8Pos = 0; u8Pos < gst_RspStruct[eIP].u8RspSize; u8Pos++) ++ { ++ if( (u8Pos == 0) || (u8Pos == 8) ) ++ prtstring("["); ++ ++ prtU8Hex(_BUF_GetByteFromRegAddr((volatile void *)A_SD_CFIFO_POS(eIP), u8Pos)); ++ prtstring(","); ++ ++ if( (u8Pos == 7) || (u8Pos == (gst_RspStruct[eIP].u8RspSize-1)) ) ++ prtstring("]\n"); ++ } ++ ++ prtstring("---------------DumpReg------------------------------\r\n"); ++ prtstring("[0x07][MIE_FUNC_CTL_REG]= "); ++ prtU16Hex(CARD_REG(A_MIE_FUNC_CTL_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x0B][SD_MODE_REG]= "); ++ prtU16Hex(CARD_REG(A_SD_MODE_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x0C][SD_CTL_REG]= "); ++ prtU16Hex(CARD_REG(A_SD_CTL_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x0F][DDR_MOD_REG]= "); ++ prtU16Hex(CARD_REG(A_DDR_MOD_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x0D][SD_STS_REG]= "); ++ prtU16Hex(CARD_REG(A_SD_STS_REG(eIP))); ++ prtstring("\r\n"); ++ ++#if(EN_BIND_CARD_INT) ++ if ( Hal_CARD_INT_MIEIntRunning(eIP, EV_INT_SD) ) // Interrupt Mode ++ { ++ prtstring("[gu16_MIEEvent_ForInt]= "); ++ prtU16Hex(Hal_CARD_INT_GetMIEEvent(eIP)); ++ prtstring("\r\n"); ++ } ++#endif ++ ++ prtstring("[0x00][MIE_EVENT_REG]= "); ++ prtU16Hex(CARD_REG(A_MIE_EVENT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x03][MMA_ADDR_15_0_REG]= "); ++ prtU16Hex(CARD_REG(A_DMA_ADDR_15_0_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x04][MMA_ADDR_31_16_REG]= "); ++ prtU16Hex(CARD_REG(A_DMA_ADDR_31_16_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x05][MMA_LEN_15_0_REG]= "); ++ prtU16Hex(CARD_REG(A_DMA_LEN_15_0_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x06][MMA_LEN_31_16_REG]= "); ++ prtU16Hex(CARD_REG(A_DMA_LEN_31_16_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x08][JOB_BLK_CNT]= "); ++ prtU16Hex(CARD_REG(A_JOB_BLK_CNT_REG(eIP))); ++ prtstring("\r\n"); ++ ++ prtstring("[0x09][BLK_SIZE]= "); ++ prtU16Hex(CARD_REG(A_BLK_SIZE_REG(eIP))); ++ prtstring("\r\n"); ++ ++ ++ CARD_REG_CLRBIT(A_DBG_BUS1_REG(eIP), R_DEBUG_MOD0 | R_DEBUG_MOD1 | R_DEBUG_MOD2 | R_DEBUG_MOD3 ); ++ CARD_REG_SETBIT(A_DBG_BUS1_REG(eIP), R_DEBUG_MOD0 | R_DEBUG_MOD2); //Mode 5 ++ ++ prtstring("[0x38][DEBUG_BUS0]= "); ++ for(u8DGMode = 1; u8DGMode <=4; u8DGMode++) ++ { ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_SD_DEBUG_MOD0 | R_SD_DEBUG_MOD1 | R_SD_DEBUG_MOD2); ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), (u8DGMode<<1)); ++ prtU16Hex(CARD_REG(A_DBG_BUS0_REG(eIP))); ++ prtstring(", "); ++ } ++ prtstring("\r\n"); ++ prtstring("[0x39][DEBUG_BUS1]= "); ++ ++ for(u8DGMode = 1; u8DGMode <=4; u8DGMode++) ++ { ++ CARD_REG_CLRBIT(A_TEST_MODE_REG(eIP), R_SD_DEBUG_MOD0 | R_SD_DEBUG_MOD1 | R_SD_DEBUG_MOD2); ++ CARD_REG_SETBIT(A_TEST_MODE_REG(eIP), (u8DGMode<<1)); ++ prtU16Hex(CARD_REG(A_DBG_BUS1_REG(eIP))); ++ prtstring(", "); ++ ++ } ++ ++ prtstring("\r\n"); ++ prtstring("----------------------------------------------------\r\n"); ++ ++#endif //End #if(EN_DUMPREG) ++ ++ ++} ++ ++ ++static RspErrEmType _SDMMC_EndProcess(IPEmType eIP, CmdEmType eCmdType, RspErrEmType eRspErr, BOOL_T bCloseClk, int Line) ++{ ++ U16_T u16RspErr = (U16_T)eRspErr; ++ U16_T u16IPErr = EV_STS_RIU_ERR | EV_STS_MIE_TOUT | EV_STS_DAT0_BUSY; ++ ++ /****** (1) Record Information *******/ ++ gst_RspStruct[eIP].u32ErrLine = (U32_T)Line; ++ gst_RspStruct[eIP].u8RspSize = (U8_T)CARD_REG(A_CMD_RSP_SIZE_REG(eIP)); ++ gst_RspStruct[eIP].eErrCode = eRspErr; ++ ++ /****** (2) Dump and the Reg Info + Reset IP *******/ ++ if ( u16RspErr && gb_StopWProc[eIP] ) ++ { ++ eRspErr = EV_SWPROC_ERR; ++ _REG_ResetIP(eIP); ++ } ++ else if( u16RspErr & u16IPErr ) //SD IP Error ++ { ++ _SDMMC_REG_Dump(eIP); ++ _REG_ResetIP(eIP); ++ } ++ else if( u16RspErr & M_SD_ERRSTS ) //SD_STS Reg Error ++ { ++ //Do Nothing ++ } ++ ++ /****** (3) Close clock and DMA Stop function ******/ ++ if(bCloseClk && !gb_SDIODevice[eIP]) ++ CARD_REG_CLRBIT(A_SD_MODE_REG(eIP), R_CLK_EN | R_DMA_RD_CLK_STOP); ++ ++ return eRspErr; ++ ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC HAL Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetDataWidth ++* @author jeremy.wang (2015/7/9) ++* Desc: According as Data Bus Width to Set IP DataWidth ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eBusWidth : 1BIT/4BITs/8BITs ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetDataWidth(IPEmType eIP, SDMMCBusWidthEmType eBusWidth) ++{ ++ gu16_SD_MODE_DatLine[eIP] = (U16_T)eBusWidth; ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetBusTiming ++* @author jeremy.wang (2015/7/29) ++* Desc: ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eBusTiming : LOW/DEF/HS/SDR12/DDR... ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetBusTiming(IPEmType eIP, BusTimingEmType eBusTiming) ++{ ++ ++ switch ( eBusTiming ) ++ { ++ ++#if (EN_BYPASSMODE) ++ ++ case EV_BUS_LOW: ++ case EV_BUS_DEF: ++ gu16_DDR_MODE_REG[eIP] = 0; ++ gu16_DDR_MODE_REG_ForR2N[eIP] = gu16_DDR_MODE_REG[eIP] | R_PAD_IN_BYPASS; ++ break; ++ case EV_BUS_HS: ++ gu16_DDR_MODE_REG[eIP] = 0; ++ gu16_DDR_MODE_REG_ForR2N[eIP] = gu16_DDR_MODE_REG[eIP] | 0; ++ break; ++ default: ++ break; ++#else ++ //ADVANCE MODE(SDR/DDR) ==> Other can't run bypass mode ++ ++ case EV_BUS_LOW: ++ case EV_BUS_DEF: ++ case EV_BUS_HS: ++ gu16_DDR_MODE_REG[eIP] = (R_PAD_CLK_SEL|R_PAD_IN_SEL|R_FALL_LATCH); ++ gu16_DDR_MODE_REG_ForR2N[eIP] = gu16_DDR_MODE_REG[eIP] | R_PAD_IN_RDY_SEL | R_PRE_FULL_SEL0 | R_PRE_FULL_SEL1; ++ break; ++ case EV_BUS_SDR12: ++ break; ++ case EV_BUS_SDR25: ++ break; ++ case EV_BUS_SDR50: ++ break; ++ case EV_BUS_SDR104: ++ break; ++ case EV_BUS_DDR50: ++ break; ++ case EV_BUS_HS200: ++ break; ++ default: ++ break; ++#endif ++ ++ ++ } ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetNrcDelay ++* @author jeremy.wang (2015/7/9) ++* Desc: According as Current Clock to Set Nrc Delay ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param u32RealClk : Real Clock ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetNrcDelay(IPEmType eIP, U32_T u32RealClk) ++{ ++ ++ if( u32RealClk >= 8000000 ) //>=8MHz ++ gu16_WT_NRC[eIP] = 1; ++ else if( u32RealClk >= 4000000 ) //>=4MHz ++ gu16_WT_NRC[eIP] = 2; ++ else if( u32RealClk >= 2000000 ) //>=2MHz ++ gu16_WT_NRC[eIP] = 4; ++ else if( u32RealClk >= 1000000 ) //>=1MHz ++ gu16_WT_NRC[eIP] = 8; ++ else if( u32RealClk >= 400000 ) //>=400KHz ++ gu16_WT_NRC[eIP] = 20; ++ else if( u32RealClk >= 300000 ) //>=300KHz ++ gu16_WT_NRC[eIP] = 27; ++ else if( u32RealClk >= 100000 ) //>=100KHz ++ gu16_WT_NRC[eIP] = 81; ++ else if(u32RealClk==0) ++ gu16_WT_NRC[eIP] = 100; //Default ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SetCmdToken ++* @author jeremy.wang (2015/7/8) ++* Desc: Set Cmd Token ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param u8Cmd : SD Command ++* @param u32Arg : SD Argument ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetCmdToken(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg) ++{ ++ gst_RspStruct[eIP].u8Cmd = u8Cmd; ++ gst_RspStruct[eIP].u32Arg = u32Arg; ++ ++ CARD_REG(A_CFIFO_OFFSET(eIP, 0)) = (((U8_T)(u32Arg>>24))<<8) | (0x40 + u8Cmd); ++ CARD_REG(A_CFIFO_OFFSET(eIP, 1)) = (((U8_T)(u32Arg>>8))<<8) | ((U8_T)(u32Arg>>16)); ++ CARD_REG(A_CFIFO_OFFSET(eIP, 2)) = (U8_T)u32Arg; ++ ++ TR_H_SDMMC(prtstring("[S_")); TR_H_SDMMC(prtUInt(eIP)); ++ TR_H_SDMMC(prtstring("] CMD_")); TR_H_SDMMC(prtUInt(u8Cmd)); ++ ++ TR_H_SDMMC(prtstring(" (")); ++ TR_H_SDMMC(prtU32Hex(u32Arg)); ++ TR_H_SDMMC(prtstring(")")); ++ ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_GetRspToken ++* @author jeremy.wang (2015/7/9) ++* Desc: Get Command Response Info ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return RspStruct* : Response Struct ++----------------------------------------------------------------------------------------------------------*/ ++RspStruct* Hal_SDMMC_GetRspToken(IPEmType eIP) ++{ ++ U8_T u8Pos; ++ ++ TR_H_SDMMC(prtstring(" =>RSP: (")); ++ TR_H_SDMMC(prtU16Hex((U16_T)gst_RspStruct[eIP].eErrCode)); ++ TR_H_SDMMC(prtstring(")\r\n")); ++ ++ for(u8Pos=0; u8Pos<0x10; u8Pos++ ) ++ gst_RspStruct[eIP].u8ArrRspToken[u8Pos] = 0; ++ ++ TR_H_SDMMC(prtstring("[")); ++ ++ for(u8Pos=0; u8Pos< gst_RspStruct[eIP].u8RspSize; u8Pos++) ++ { ++ gst_RspStruct[eIP].u8ArrRspToken[u8Pos] = _BUF_GetByteFromRegAddr((volatile void *)A_SD_CFIFO_POS(eIP), u8Pos); ++ TR_H_SDMMC(prtU8Hex(gst_RspStruct[eIP].u8ArrRspToken[u8Pos])); ++ TR_H_SDMMC(prtstring(", ")); ++ ++ } ++ ++ TR_H_SDMMC(prtstring("]\r\n\r\n")); ++ ++ return &gst_RspStruct[eIP]; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_TransCmdSetting ++* @author jeremy.wang (2015/7/15) ++* Desc: For Data Transfer Setting ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eTransType : CIFD/DMA/ADMA/NONE ++* @param u16BCnt : Block Cnt ++* @param u16BlkSize : Block Size ++* @param u32BufAddr : Memory Address or DMA Table Address (32bits) ++* @param pu8Buf : If run CIFD, it neet the buf pointer to do io between CIFD and Buf ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_TransCmdSetting(IPEmType eIP, TransEmType eTransType, U16_T u16BlkCnt, U16_T u16BlkSize, volatile U32_T u32BufAddr, volatile U8_T *pu8Buf) ++{ ++ U32_T u32_TranLen = u16BlkCnt * u16BlkSize; ++ ++ CARD_REG(A_BLK_SIZE_REG(eIP)) = u16BlkSize; ++ ++ if (eTransType==EV_ADMA) ++ { ++ CARD_REG(A_JOB_BLK_CNT_REG(eIP)) = 1; //ADMA BLK_CNT = 1 ++ CARD_REG(A_DMA_LEN_15_0_REG(eIP)) = 0x10; //ADMA Fixed Value = 0x10 ++ CARD_REG(A_DMA_LEN_31_16_REG(eIP)) = 0; ++ } ++ else //R2N or DMA ++ { ++ CARD_REG(A_JOB_BLK_CNT_REG(eIP)) = u16BlkCnt; ++ CARD_REG(A_DMA_LEN_15_0_REG(eIP)) = (U16_T)(u32_TranLen & 0xFFFF); ++ CARD_REG(A_DMA_LEN_31_16_REG(eIP)) = (U16_T)(u32_TranLen >> 16); ++ } ++ ++ if( (eTransType== EV_DMA) || (eTransType==EV_ADMA) ) ++ { ++ CARD_REG(A_DMA_ADDR_15_0_REG(eIP)) = (U16_T)(u32BufAddr & 0xFFFF); ++ CARD_REG(A_DMA_ADDR_31_16_REG(eIP)) = (U16_T)(u32BufAddr >> 16); ++ } ++ else //CIFD (R2N) ++ { ++ gpu8Buf[eIP] = pu8Buf; ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_SendCmdAndWaitProcess ++* @author jeremy.wang (2015/7/14) ++* Desc: Send SD Command and Waiting for Process ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eTransType : CIFD/DMA/ADMA/NONE ++* @param eCmdType : CMDRSP/READ/WRITIE ++* @param eRspType : R1/R2/R3/... ++* @param bCloseClk : Close Clock or not ++* ++* @return RspErrEmType : Response Error Code ++----------------------------------------------------------------------------------------------------------*/ ++RspErrEmType Hal_SDMMC_SendCmdAndWaitProcess(IPEmType eIP, TransEmType eTransType, CmdEmType eCmdType, SDMMCRspEmType eRspType, BOOL_T bCloseClk) ++{ ++ U32_T u32WaitMS = WT_EVENT_RSP; ++ U16_T u16WaitMIEEvent = R_CMD_END; ++ ++ CARD_REG(A_CMD_RSP_SIZE_REG(eIP)) = V_CMD_SIZE_INIT | ((U8_T)eRspType); ++ CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) = V_MIE_PATH_INIT | _REG_GetMIEFunCtlSetting(eIP); ++ CARD_REG(A_SD_MODE_REG(eIP)) = V_SD_MODE_INIT | (eTransType>>8) | gu16_SD_MODE_DatLine[eIP] | ((U8_T)(eTransType & R_DMA_RD_CLK_STOP)); ++ CARD_REG(A_SD_CTL_REG(eIP)) = V_SD_CTL_INIT | (eRspType>>12) | (eCmdType>>4) | ((U8_T)(eTransType & R_ADMA_EN)); ++ CARD_REG(A_SDIO_MODE_REG(eIP)) = V_SDIO_MODE_INIT | gu16_SDIO_MODE_IntMode[eIP]; ++ ++ CARD_REG_CLRBIT(A_BOOT_MOD_REG(eIP), R_BOOT_MODE); ++ CARD_REG_CLRBIT(A_BOOT_REG(eIP), (R_NAND_BOOT_EN | R_BOOTSRAM_ACCESS_SEL | R_IMI_SEL)); ++ ++ CARD_REG(A_MMA_PRI_REG_REG(eIP)) = V_MMA_PRI_INIT; ++ CARD_REG(A_DDR_MOD_REG(eIP)) = V_DDR_MODE_INIT | (eTransType==EV_CIF ? gu16_DDR_MODE_REG_ForR2N[eIP] : gu16_DDR_MODE_REG[eIP]); ++ ++ Hal_Timer_uDelay(gu16_WT_NRC[eIP]); ++ ++ if( _REG_ClearSDSTS(eIP, RT_CLEAN_SDSTS) || _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__);; ++ ++#if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_SetMIEIntEn(eIP, EV_INT_SD, V_MIE_INT_EN_INIT); ++#endif ++ ++ if(eCmdType==EV_CMDREAD) ++ { ++ if (eTransType!=EV_CIF) ++ { ++ u16WaitMIEEvent |= R_DATA_END; ++ u32WaitMS |= WT_EVENT_READ; ++ } ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_CMD_EN | R_DTRX_EN | R_JOB_START) ); ++ } ++ else ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_CMD_EN | R_JOB_START) ); ++ ++ if(_REG_WaitEvent(eIP, EV_MIE, u16WaitMIEEvent, u32WaitMS)) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ //====== Special Case for R2N CIFD Read Transfer ====== ++ if( (eCmdType==EV_CMDREAD) && (eTransType==EV_CIF) ) ++ { ++ if(_BUF_CIFD_WaitEvent(eIP, eCmdType, gpu8Buf[eIP])) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ if(_REG_WaitEvent(eIP, EV_MIE, R_DATA_END, WT_EVENT_READ)) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ } ++ ++ if( (eRspType == EV_R1B) && _REG_WaitDat0HI(eIP, WT_DAT0HI_END) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_DAT0_BUSY, bCloseClk, __LINE__); ++ else if( (eRspType == EV_R3) || (eRspType == EV_R4) ) // For IP CRC bug ++ CARD_REG(A_SD_STS_REG(eIP)) = R_CMDRSP_CERR; //Clear CMD CRC Error ++ ++ if( (eCmdType == EV_CMDWRITE) && (!M_REG_STSERR(eIP)) ) ++ { ++ if( _REG_ClearSDSTS(eIP, RT_CLEAN_SDSTS) || _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, bCloseClk, __LINE__);; ++ ++ CARD_REG(A_SD_CTL_REG(eIP)) = V_SD_CTL_INIT |(eCmdType>>4) | ((U8_T)(eTransType & R_ADMA_EN)); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_DTRX_EN | R_JOB_START) ); ++ ++ //====== Special Case for R2N CIFD Write Transfer ====== ++ if ( (eTransType==EV_CIF) && _BUF_CIFD_WaitEvent(eIP, eCmdType, gpu8Buf[eIP]) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ if(_REG_WaitEvent(eIP, EV_MIE, R_DATA_END, WT_EVENT_WRITE)) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, bCloseClk, __LINE__); ++ ++ } ++ ++ return _SDMMC_EndProcess(eIP, eCmdType, (RspErrEmType)M_REG_STSERR(eIP), bCloseClk, __LINE__); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_RunBrokenDmaAndWaitProcess ++* @author jeremy.wang (2015/7/29) ++* Desc: For Broken DMA Data Transfer ++* ++* @param eIP : FCIE1/FCIE2/... ++* @param eCmdType : READ/WRITE ++* ++* @return RspErrEmType : Response Error Code ++----------------------------------------------------------------------------------------------------------*/ ++RspErrEmType Hal_SDMMC_RunBrokenDmaAndWaitProcess(IPEmType eIP, CmdEmType eCmdType) ++{ ++ U32_T u32WaitMS = 0; ++ ++ if(eCmdType==EV_CMDREAD) ++ u32WaitMS = WT_EVENT_READ; ++ else if(eCmdType==EV_CMDWRITE) ++ u32WaitMS = WT_EVENT_WRITE; ++ ++ if ( _REG_ClearMIEEvent(eIP, RT_CLEAN_MIEEVENT) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_RIU_ERR, FALSE, __LINE__); ++ ++ CARD_REG_CLRBIT(A_SD_CTL_REG(eIP), R_CMD_EN ); ++ CARD_REG_SETBIT(A_SD_CTL_REG(eIP), (R_DTRX_EN | R_JOB_START) ); ++ ++ if ( _REG_WaitEvent(eIP, EV_MIE, R_DATA_END, u32WaitMS) ) ++ return _SDMMC_EndProcess(eIP, eCmdType, EV_STS_MIE_TOUT, FALSE, __LINE__); ++ ++ return _SDMMC_EndProcess(eIP, eCmdType, (RspErrEmType)M_REG_STSERR(eIP), FALSE, __LINE__); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_ADMASetting ++* @author jeremy.wang (2015/7/13) ++* Desc: For ADMA Data Transfer Settings ++* ++* @param pDMATable : DMA Table memory address pointer ++* @param u8Item : DMA Table Item 0 ~ ++* @param u32SubLen : DMA Table DMA Len ++* @param u32SubBCnt : DMA Table Job Blk Cnt ++* @param u32SubAddr : DMA Table DMA Addr ++* @param u8MIUSel : MIU Select ++* @param bEnd : End Flag ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_ADMASetting(volatile void *pDMATable, U8_T u8Item, U32_T u32SubLen, U16_T u16SubBCnt, U32_T u32SubAddr, U8_T u8MIUSel, BOOL_T bEnd) ++{ ++ //U16_T u16Pos; ++ ++ AdmaDescStruct* pst_AdmaDescStruct = (AdmaDescStruct*) pDMATable; ++ ++ pst_AdmaDescStruct = (pst_AdmaDescStruct+u8Item); ++ memset(pst_AdmaDescStruct, 0, sizeof(AdmaDescStruct)); ++ ++ pst_AdmaDescStruct->u32_DmaLen = u32SubLen; ++ pst_AdmaDescStruct->u32_Address = u32SubAddr; ++ pst_AdmaDescStruct->u32_JobCnt = u16SubBCnt; ++ pst_AdmaDescStruct->u32_MiuSel = u8MIUSel; ++ pst_AdmaDescStruct->u32_End = bEnd; ++ ++ /*prtstring("\r\n"); ++ prtstring("gpst_AdmaDescStruct Pos=("); ++ prtU32Hex((U32_T)pst_AdmaDescStruct); ++ prtstring(")\r\n"); ++ ++ for(u16Pos=0; u16Pos<192 ; u16Pos++) ++ { ++ if( (u16Pos%12)==0) ++ (prtstring("\r\n")); ++ ++ (prtstring("[")); ++ (prtU8Hex( *(pu8Buf+u16Pos))); ++ (prtstring("]")); ++ ++ }*/ ++ ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Operation Function ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_ClkCtrl ++ * @author jeremy.wang (2015/11/4) ++ * Desc: Enable IP clock output ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ * @param u16DelayMs : Delay ms to Specail Purpose ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_ClkCtrl(IPEmType eIP, BOOL_T bEnable, U16_T u16DelayMs) ++{ ++ CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) = V_MIE_PATH_INIT | _REG_GetMIEFunCtlSetting(eIP); ++ ++ if( bEnable ) ++ CARD_REG_SETBIT(A_SD_MODE_REG(eIP), R_CLK_EN); ++ else ++ CARD_REG_CLRBIT(A_SD_MODE_REG(eIP), R_CLK_EN); ++ ++ Hal_Timer_mSleep(u16DelayMs); ++ //Hal_Timer_mDelay(u16DelayMs); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_Reset ++* @author jeremy.wang (2015/7/17) ++* Desc: Reset IP to avoid IP dead ++* ++* @param eIP : FCIE1/FCIE2/... ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_Reset(IPEmType eIP) ++{ ++ _REG_ResetIP(eIP); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_StopProcessCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Stop process to avoid long time waiting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_StopProcessCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ gb_StopWProc[eIP] = bEnable; ++ ++#if(EN_BIND_CARD_INT) ++ if ( gb_StopWProc[eIP] ) ++ Hal_CARD_INT_StopWaitMIEEventCtrl(eIP, TRUE); ++ else ++ Hal_CARD_INT_StopWaitMIEEventCtrl(eIP, FALSE); ++#endif ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_OtherPreUse ++* @author jeremy.wang (2015/7/17) ++* Desc: Use this for avoid SD/EMMC to use FCIE at the same time ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return BOOL_T : (TRUE: Other driver usnig) ++----------------------------------------------------------------------------------------------------------*/ ++BOOL_T Hal_SDMMC_OtherPreUse(IPEmType eIP) ++{ ++ ++ if ( CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) & R_EMMC_EN ) ++ return (TRUE); ++ ++ if ( !(CARD_REG(A_MIE_FUNC_CTL_REG(eIP)) & (R_SD_EN | R_SDIO_MODE)) ) //Not SD Path ++ return (TRUE); ++ ++ return (FALSE); ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_ErrGroup ++ * @author jeremy.wang (2015/10/28) ++ * Desc: transfer response error type to group error type ++ * ++ * @param eRspErrType : Response Error Type ++ * ++ * @return ErrGrpEmType : Group Error Type ++ ----------------------------------------------------------------------------------------------------------*/ ++ErrGrpEmType Hal_SDMMC_ErrGroup(RspErrEmType eRspErrType) ++{ ++ ++ switch((U16_T)eRspErrType) ++ { ++ case EV_STS_OK: ++ return EV_EGRP_OK; ++ ++ case EV_STS_WR_TOUT: ++ case EV_STS_NORSP: ++ case EV_STS_RD_TOUT: ++ case EV_STS_RIU_ERR: ++ case EV_STS_DAT0_BUSY: ++ case EV_STS_MIE_TOUT: ++ return EV_EGRP_TOUT; ++ ++ case EV_STS_RD_CERR: ++ case EV_STS_WD_CERR: ++ case EV_STS_RSP_CERR: ++ return EV_EGRP_COMM; ++ ++ default: ++ return EV_EGRP_OTHER; ++ } ++ ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Information ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_DumpMemTool ++* @author jeremy.wang (2015/7/29) ++* Desc: Help us to dump memory ++* ++* @param u8ListNum : Each List Num include 16 bytes ++* @param pu8Buf : Buffer Pointer ++----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_DumpMemTool(U8_T u8ListNum, volatile U8_T *pu8Buf) ++{ ++ U16_T u16Pos=0; ++ U8_T u8ListPos; ++ U32_T u32BufAddr = (U32_T)pu8Buf; ++ prtstring("\r\n $[Prt MEM_DATA: "); ++ prtU32Hex(u32BufAddr); ++ prtstring(" ]\r\n"); ++ ++ for(u8ListPos=0 ; u8ListPos >8); ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++* ++* Function: Hal_SDMMC_GetMIEEvent ++* @author jeremy.wang (2015/7/31) ++* Desc: Monitor MIE Event for debug ++* ++* @param eIP : FCIE1/FCIE2/... ++* ++* @return U16_T : Return MIE Event ++----------------------------------------------------------------------------------------------------------*/ ++U16_T Hal_SDMMC_GetMIEEvent(IPEmType eIP) ++{ ++ return CARD_REG(A_MIE_EVENT_REG(eIP)); ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC SDIO Setting ++//*********************************************************************************************************** ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SDIODeviceCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Enable SDIO device for do something for SDIO case ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SDIODeviceCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ if(bEnable) ++ gb_SDIODevice[eIP] = TRUE; ++ else ++ gb_SDIODevice[eIP] = FALSE; ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SDIOIntDetCtrl ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Enable SDIO interrupt detection ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SDIOIntDetCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(bEnable) ++ { ++ if(!gu16_SDIO_IntEn_RunOnce[eIP]) ++ { ++ gu16_SDIO_IntEn_RunOnce[eIP] = TRUE; //If we confirm this device is SDIO, we enable the int_en once ++ ++ #if(EN_BIND_CARD_INT) ++ Hal_CARD_INT_SetMIEIntEn_ForSDIO(eIP, EV_INT_SD, bEnable); ++ #endif // End of EN_BIND_CARD_INT ++ ++ } ++ ++ CARD_REG_SETBIT(A_SDIO_DET_ON(eIP), R_SDIO_DET_ON); ++ } ++ else ++ { ++ //Auto Clear at FCIE5 ? ++ CARD_REG_CLRBIT(A_SDIO_DET_ON(eIP), R_SDIO_DET_ON); ++ } ++ ++ ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetSDIOIntBeginSetting ++ * @author jeremy.wang (2015/11/3) ++ * Desc: Set SDIO Int begin setting ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param u8Cmd : SDIO Command ++ * @param u32Arg : SDIO Argument ++ * @param eCmdType : CMDRSP/READ/WRITE ++ * @param u16BlkCnt : Block Cnt ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetSDIOIntBeginSetting(IPEmType eIP, U8_T u8Cmd, U32_T u32Arg, CmdEmType eCmdType, U16_T u16BlkCnt) ++{ ++ BOOL_T bSDIOAbortMode = (u8Cmd == 52) && ( (u32Arg & 0x83FFFE00) == 0x80000C00); ++ ++ gu16_SDIO_MODE_IntMode[eIP] = 0; ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(eCmdType != EV_CMDRSP) ++ { ++ if(u16BlkCnt == 1) ++ gu16_SDIO_MODE_IntMode[eIP] = R_SDIO_INT_MOD1; ++ else ++ gu16_SDIO_MODE_IntMode[eIP] = R_SDIO_INT_MOD0 | R_SDIO_INT_MOD1; ++ } ++ else if ( (u8Cmd == 12) || bSDIOAbortMode) ++ { ++ gu16_SDIO_MODE_IntMode[eIP] = R_SDIO_INT_MOD0; ++ } ++ } ++ ++} ++ ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_SetSDIOIntEndSetting ++ * @author jeremy.wang (2015/10/29) ++ * Desc: ++ * ++ * @param eIP : ++ * @param eRspErr : ++ * @param u16BlkCnt : ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_SetSDIOIntEndSetting(IPEmType eIP, RspErrEmType eRspErr, U16_T u16BlkCnt) ++{ ++ U16_T u16RspErr = (U16_T)eRspErr; ++ ++ if(gb_SDIODevice[eIP]) ++ { ++ if(u16BlkCnt>1) ++ { ++ ++ } ++ if(u16RspErr>0) ++ { ++ } ++ } ++} ++ ++ ++//*********************************************************************************************************** ++// SDMMC Interrupt Setting ++//*********************************************************************************************************** ++ ++#if(EN_BIND_CARD_INT) ++ ++/*---------------------------------------------------------------------------------------------------------- ++ * ++ * Function: Hal_SDMMC_MIEIntCtrl ++ * @author jeremy.wang (2015/11/2) ++ * Desc: Enable MIE event interrupt control ++ * ++ * @param eIP : FCIE1/FCIE2/... ++ * @param bEnable : Enable (TRUE) or Disable (FALSE) ++ ----------------------------------------------------------------------------------------------------------*/ ++void Hal_SDMMC_MIEIntCtrl(IPEmType eIP, BOOL_T bEnable) ++{ ++ Hal_CARD_INT_MIEIntCtrl(eIP, EV_INT_SD, bEnable); ++} ++ ++ ++ ++#endif // End of EN_BIND_CARD_INT +diff --git a/drivers/mstar/serial/Kconfig b/drivers/mstar/serial/Kconfig +new file mode 100644 +index 00000000..f4659822 +--- /dev/null ++++ b/drivers/mstar/serial/Kconfig +@@ -0,0 +1,5 @@ ++config MS_SERIAL ++ bool "Serial / UART driver" ++ select SERIAL_CORE ++ select SERIAL_CORE_CONSOLE ++ default y +\ No newline at end of file +diff --git a/drivers/mstar/serial/Makefile b/drivers/mstar/serial/Makefile +new file mode 100644 +index 00000000..79dec221 +--- /dev/null ++++ b/drivers/mstar/serial/Makefile +@@ -0,0 +1,7 @@ ++CONFIG_MSTAR_CHIP_NAME := $(subst ",,$(CONFIG_MSTAR_CHIP_NAME)) ++ ++# general options ++EXTRA_CFLAGS += -Idrivers/mstar/include ++EXTRA_CFLAGS += -Idrivers/mstar/include/$(CONFIG_MSTAR_CHIP_NAME) ++ ++obj-$(CONFIG_MS_SERIAL) += ms_uart.o +diff --git a/drivers/mstar/serial/ms_uart.c b/drivers/mstar/serial/ms_uart.c +new file mode 100644 +index 00000000..4dfd3f14 +--- /dev/null ++++ b/drivers/mstar/serial/ms_uart.c +@@ -0,0 +1,2126 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ms_platform.h" ++#include "mdrv_types.h" ++#include "gpio.h" ++ ++#define UART_DEBUG 0 ++ ++#if UART_DEBUG ++#define UART_DBG(fmt, arg...) printk(KERN_INFO fmt, ##arg) ++#else ++#define UART_DBG(fmt, arg...) ++#endif ++#define UART_ERR(fmt, arg...) printk(KERN_ERR fmt, ##arg) ++ ++#define MUX_PM_UART 0 ++#define MUX_FUART 1 ++#define MUX_UART0 2 ++#define MUX_UART1 3 ++ ++#define REG_UART_MODE 0x1F203C0C ++#define REG_UART_SEL 0x1F203D4C ++#define REG_FORCE_RX_DISABLE 0x1F203D5C ++ ++#define UART_TX_TASK 0 /* use tasklet to send TX char */ ++#define UART_USE_LOOPBACK 0 /* use UART loopback mode to avoid external input */ ++#define UART_USE_SPINLOCK 0 /* set IER use spinlock to ensure atomic */ ++ ++#define NR_CONSOLE_PORTS 1 ++#define MS_CONSOLE_DEV "ttyS" ++ ++#define REG_DLL_THR_RBR(p) GET_REG_ADDR((u32)p->membase, (0x00)) ++#define REG_DLH_IER(p) GET_REG_ADDR((u32)p->membase, (0x02)) ++#define REG_IIR_FCR(p) GET_REG_ADDR((u32)p->membase, (0x04)) ++#define REG_LCR(p) GET_REG_ADDR((u32)p->membase, (0x06)) ++#define REG_MCR(p) GET_REG_ADDR((u32)p->membase, (0x08)) ++#define REG_LSR(p) GET_REG_ADDR((u32)p->membase, (0x0A)) ++#define REG_MSR(p) GET_REG_ADDR((u32)p->membase, (0x0C)) ++#define REG_USR(p) GET_REG_ADDR((u32)p->membase, (0x0E)) ++#define REG_TFL(p) GET_REG_ADDR((u32)p->membase, (0x10)) ++#define REG_RFL(p) GET_REG_ADDR((u32)p->membase, (0x12)) ++#define REG_RST(p) GET_REG_ADDR((u32)p->membase, (0x14)) ++ ++/* Interrupt Enable Register (IER)*/ ++#define UART_IER_RDI 0x01 /* Received Data Available Interrupt */ ++#define UART_IER_THRI 0x02 /* Transmitter Holding Register Empty Interrupt */ ++#define UART_IER_RLSI 0x04 /* Receiver Line Status Interrupt */ ++#define UART_IER_MSI 0x08 /* Modem Status Interrupt */ ++ ++/* Interrupt Identification Register (IIR) */ ++#define UART_IIR_MSI 0x00 /* 0000: Modem Status */ ++#define UART_IIR_NO_INT 0x01 /* 0001: No pending interrupts */ ++#define UART_IIR_THRI 0x02 /* 0010: Transmitter Holding Register Empty */ ++#define UART_IIR_RDI 0x04 /* 0100: Receiver Data Available */ ++#define UART_IIR_RLSI 0x06 /* 0110: Receiver Line Status */ ++#define UART_IIR_BUSY 0x07 /* 0111: Busy detect indication (try to write LCR while UART is busy) */ ++#define UART_IIR_RX_TIMEOUT 0x0C /* 1100: Character timeout */ ++#define UART_IIR_ID_MASK 0x0F /* Mask Bit[3:0] for IIR */ ++ ++/* FIFO Control Register (FCR) */ ++#define UART_FCR_FIFO_ENABLE 0x01 /* Clear & Reset Rx FIFO buffer */ ++#define UART_FCR_CLEAR_RCVR 0x02 /* Clear & Reset Rx FIFO buffer */ ++#define UART_FCR_CLEAR_XMIT 0x04 /* Clear & Reset Tx FIFO buffer */ ++#define UART_FCR_TRIGGER_TX_L0 0x00 /* Trigger Write when emtpy */ ++#define UART_FCR_TRIGGER_TX_L1 0x10 /* Trigger Write when 2 characters */ ++#define UART_FCR_TRIGGER_TX_L2 0x20 /* Trigger Write when 1/4 full */ ++#define UART_FCR_TRIGGER_TX_L3 0x30 /* Trigger Write when 1/2 full */ ++#define UART_FCR_TRIGGER_RX_L0 0x00 /* Trigger Read when there is 1 char*/ ++#define UART_FCR_TRIGGER_RX_L1 0x40 /* Trigger Read when 1/4 full */ ++#define UART_FCR_TRIGGER_RX_L2 0x80 /* Trigger Read when 1/2 full */ ++#define UART_FCR_TRIGGER_RX_L3 0xC0 /* Trigger Read when 2 less then full */ ++ ++/* Line Control Register (LCR) */ ++#define UART_LCR_WL_MASK 0x03 /* Word length mask */ ++#define UART_LCR_WLEN5 0x00 /* Word length is 5 bits */ ++#define UART_LCR_WLEN6 0x01 /* Word length is 6 bits */ ++#define UART_LCR_WLEN7 0x02 /* Word length is 7 bits */ ++#define UART_LCR_WLEN8 0x03 /* Word length is 8 bits */ ++#define UART_LCR_STOP_MASK 0x04 /* Stop bit mask */ ++#define UART_LCR_STOP1 0x00 /* Stop length is 1 bit */ ++#define UART_LCR_STOP2 0x04 /* Stop length is 1.5 bits (5-bit char), 2 bits (otherwise) */ ++#define UART_LCR_PARITY_EN 0x08 /* Parity Enable */ ++#define UART_LCR_PARITY_SEL 0x10 /* Even Parity Select */ ++#define UART_LCR_SBC 0x40 /* Set break control */ ++#define UART_LCR_DLAB 0x80 /* Divisor Latch Access bit, 1=Divisor Latch, 0=Normal Register */ ++ ++#define UART_MCR_DTR 0x01 ++#define UART_MCR_RTS 0x02 ++#define UART_MCR_OUT1 0x04 ++#define UART_MCR_OUT2 0x08 ++#define UART_MCR_LOOPBACK 0x10 ++#define UART_MCR_AFCE 0x20 ++ ++/* Line Status Register */ ++#define UART_LSR_DR 0x01 /* Data Ready, at least one char in FIFO buffer*/ ++#define UART_LSR_OE 0x02 /* Overrun Error, FIFO buffer is full */ ++#define UART_LSR_PE 0x04 /* Parity Error */ ++#define UART_LSR_FE 0x08 /* Framing Error, no valid stop bit */ ++#define UART_LSR_BI 0x10 /* Break Interrupt */ ++#define UART_LSR_THRE 0x20 /* Tx FIFO buffer is empty*/ ++#define UART_LSR_TEMT 0x40 /* Both TX FIFO buffer & shift register are empty */ ++#define UART_LSR_TX_ERROR 0x80 /* Tx FIFO buffer is error */ ++ ++#define UART_USR_BUSY 0x01 ++#define UART_USR_TXFIFO_NOT_FULL 0x02 ++#define UART_USR_TXFIFO_EMPTY 0x04 ++ ++ ++#define UR2DMA_TX_BUF_LENGTH 0x1000 //must be 8 byte aligned, linux should better be PAGE_ALIGN ++#define UR2DMA_RX_BUF_LENGTH 0x1000 //must be 8 byte aligned, linux should better be PAGE_ALIGN ++ ++#define URDMA_RX_TIMEOUT 0x0F ++#define URDMA_TX_TIMEOUT 0x0F ++ ++#define URDMA_RX_INTR_LEVEL 0x500 //need to think ++ ++#define URDMA_RX_INTR_TYPE_TIMEOUT 1 ++#define URDMA_RX_INTR_TYPE_THRESHOLD 2 ++ ++#define URDMA_INTR_STATUS_RX 1 ++#define URDMA_INTR_STATUS_TX 2 ++ ++#define URDMA_LOU16(u32Val) ((U16)(u32Val)&0xFFFF) ++#define URDMA_HIU16(u32Val) ((U16)((u32Val) >> 16)&0x0FFF) ++ ++#define URDMA_logical2bus(x) (x&0x0FFFFFFF) ++ ++/* Warning: Little Endian */ ++typedef struct reg_urdma ++{ ++ union ++ { ++ volatile U16 reg00; ++ struct ++ { ++ volatile U16 sw_rst : 1; /* BIT0 */ ++ volatile U16 urdma_mode : 1; /* BIT1 */ ++ volatile U16 tx_urdma_en : 1; /* BIT2 */ ++ volatile U16 rx_urdma_en : 1; /* BIT3 */ ++ volatile U16 tx_endian : 1; /* BIT4 */ ++ volatile U16 rx_endian : 1; /* BIT5 */ ++ volatile U16 tx_sw_rst : 1; /* BIT6 */ ++ volatile U16 rx_sw_rst : 1; /* BIT7 */ ++ volatile U16 reserve00 : 3; /* BIT8 ~ BIT10 */ ++ volatile U16 rx_op_mode : 1; /* BIT11 */ ++ volatile U16 tx_busy : 1; /* BIT12 */ ++ volatile U16 rx_busy : 1; /* BIT13 */ ++ volatile U16 reserve01 : 2; /* BIT14 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space00; ++ ++ union ++ { ++ volatile U16 reg01; ++ struct ++ { ++ volatile U16 intr_threshold : 12; /* BIT0 ~ BIT11 */ ++ volatile U16 reserve02 : 4; /* BIT12 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space01; ++ ++ union ++ { ++ volatile U16 reg02; ++ struct ++ { ++ volatile U16 tx_buf_base_h : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space02; ++ ++ union ++ { ++ volatile U16 reg03; ++ struct ++ { ++ volatile U16 tx_buf_base_l : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space03; ++ ++ union ++ { ++ volatile U16 reg04; ++ struct ++ { ++ volatile U16 tx_buf_size : 13; /* BIT0 ~ BIT12 */ ++ volatile U16 reserve04 : 3; /* BIT13 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space04; ++ ++ union ++ { ++ volatile U16 reg05; ++ struct ++ { ++ volatile U16 tx_buf_rptr : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space05; ++ ++ union ++ { ++ volatile U16 reg06; ++ struct ++ { ++ volatile U16 tx_buf_wptr : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space06; ++ ++ union ++ { ++ volatile U16 reg07; ++ struct ++ { ++ volatile U16 tx_timeout : 4; /* BIT0 ~ BIT3 */ ++ volatile U16 reserve05 : 12; /* BIT4 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space07; ++ ++ union ++ { ++ volatile U16 reg08; ++ struct ++ { ++ volatile U16 rx_buf_base_h : 16; /* BIT0 ~ BIT7 */ ++ } ; ++ } ; ++ U16 space08; ++ ++ union ++ { ++ volatile U16 reg09; ++ struct ++ { ++ volatile U16 rx_buf_base_l : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space09; ++ ++ union ++ { ++ volatile U16 reg0a; ++ struct ++ { ++ volatile U16 rx_buf_size : 13; /* BIT0 ~ BIT12 */ ++ volatile U16 reserve07 : 3; /* BIT13 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space0a; ++ ++ union ++ { ++ volatile U16 reg0b; ++ struct ++ { ++ volatile U16 rx_buf_wptr : 16; /* BIT0 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space0b; ++ ++ union ++ { ++ volatile U16 reg0c; ++ struct ++ { ++ volatile U16 rx_timeout : 4; /* BIT0 ~ BIT3 */ ++ volatile U16 reserve08 : 12; /* BIT4 ~ BIT15 */ ++ } ; ++ } ; ++ U16 space0c; ++ ++ union ++ { ++ volatile U16 reg0d; ++ struct ++ { ++ volatile U16 rx_intr_clr : 1; /* BIT0 */ ++ volatile U16 rx_intr1_en : 1; /* BIT1 */ ++ volatile U16 rx_intr2_en : 1; /* BIT2 */ ++ volatile U16 reserve09 : 1; /* BIT3 */ ++ volatile U16 rx_intr1 : 1; /* BIT4 */ ++ volatile U16 rx_intr2 : 1; /* BIT5 */ ++ volatile U16 reserve0a : 1; /* BIT6 */ ++ volatile U16 rx_mcu_intr : 1; /* BIT7 */ ++ volatile U16 tx_intr_clr : 1; /* BIT8 */ ++ volatile U16 tx_intr_en : 1; /* BIT9 */ ++ volatile U16 reserve0b : 5; /* BIT10 ~ BIT14 */ ++ volatile U16 tx_mcu_intr : 1; /* BIT15 */ ++ } ; ++ } ; ++} reg_urdma; ++ ++ ++struct ms_urdma ++{ ++ reg_urdma *reg_base; ++ unsigned int urdma_irq; ++ u8 *rx_buf; ++ u8 *tx_buf; ++ dma_addr_t rx_urdma_base; ++ dma_addr_t tx_urdma_base; ++ u32 rx_urdma_size; ++ u32 tx_urdma_size; ++ u16 sw_rx_rptr; ++}; ++ ++ ++struct ms_uart_port { ++ struct uart_port port; ++ struct ms_urdma *urdma; ++ struct device *dev; ++ struct clk *clk; ++ int use_dma; ++#if UART_TX_TASK ++ struct tasklet_struct xmit_tasklet; ++#endif ++ int rx_guard; ++ u8 backupIER; ++ u8 backupLCR; ++ u8 backupMCR; ++ u16 backupDivisor; ++ u8 padmux; ++ u8 pad_mode; ++}; ++ ++ ++static void ms_uart_console_write(struct console *co, const char *str, u32 count); ++static s32 ms_uart_console_setup(struct console *co, char *options); ++ ++static struct ms_uart_port *console_ports[NR_CONSOLE_PORTS]; ++static struct ms_uart_port console_port; ++static struct uart_driver ms_uart_driver; ++ ++ ++/* Serial Console Structure Definition */ ++static struct console ms_uart_console = ++{ ++ .name = MS_CONSOLE_DEV, ++ .write = ms_uart_console_write, ++ .setup = ms_uart_console_setup, ++ .flags = CON_PRINTBUFFER, ++ .device = uart_console_device, ++ .data = &ms_uart_driver, ++ .index = -1, ++}; ++ ++ ++static struct uart_driver ms_uart_driver = { ++ .owner = THIS_MODULE, ++ .driver_name = "ms_uart", ++ .dev_name = "ttyS", ++ .nr = 8, ++ .cons = &ms_uart_console, ++}; ++ ++ ++ ++extern void Chip_UART_Disable_Line(int line); ++extern void Chip_UART_Enable_Line(int line); ++ ++void URDMA_Reset(struct uart_port *p); ++void URDMA_Activate(struct uart_port *p,BOOL bEnable); ++void URDMA_TxEnable(struct uart_port *p,BOOL bEnable); ++void URDMA_RxEnable(struct uart_port *p,BOOL bEnable); ++U8 URDMA_GetInterruptStatus(struct uart_port *p); ++void URDMA_TxInit(struct uart_port *p); ++void URDMA_RxInit(struct uart_port *p); ++void URDMA_TxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnable); ++void URDMA_TxClearInterrupt(struct uart_port *p); ++void URDMA_RxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnableTimeout); ++void URDMA_RxSetupThresholdInterrupt(struct uart_port *p,BOOL bEnableThreshold); ++U8 URDMA_RxGetInterrupt(struct uart_port *p); ++void URDMA_RxClearInterrupt(struct uart_port *p); ++U32 URDMA_GetWritableSize(struct uart_port *p); ++void URDMA_StartTx(struct uart_port *p); ++void URDMA_StartRx(struct uart_port *p); ++ ++ ++void inline ms_uart_clear_fifos(struct uart_port *p) ++{ ++ unsigned int timeout=0; ++ ++ while( ((INREG8(REG_USR(p)) & UART_USR_BUSY)) && timeout < 2000) ++ timeout++; ++ OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE); ++ OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); ++ OUTREG8(REG_IIR_FCR(p), 0); ++} ++ ++void ms_select_pad(struct uart_port *p, u8 padmux, u8 pad_mode) ++{ ++ u8 select=0; ++ ++ if(p->line == 0) ++ select=2; ++ else if(p->line == 1) ++ select=3; ++ else if(p->line == 2) ++ select=1; ++ else ++ { ++ UART_ERR("[%s] port line %d is not supported\n", __func__, p->line); ++ return; ++ } ++ ++ switch(padmux) ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_UART_SEL, select << 0, 0xF << 0); //reg_uart_sel0[3:0] ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 0, 0x3 << 0); //reg_uart_mode[1:0] ++ OUTREGMSK16(REG_UART_SEL, select << 4, 0xF << 4); //reg_uart_sel0[7:4] ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 4, 0x3 << 4); //reg_uart_mode[5:4] ++ OUTREGMSK16(REG_UART_SEL, select << 8, 0xF << 8); //reg_uart_sel0[11:8] ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_UART_MODE, pad_mode << 8, 0x3 << 8); //reg_uart_mode[9:8] ++ OUTREGMSK16(REG_UART_SEL, select << 12, 0xF << 12); //reg_uart_sel0[15:12] ++ break; ++ default: ++ UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++void ms_force_rx_disable(u8 padmux, BOOL status) ++{ ++ switch(padmux) //set 0 for disable, 1 for enable ++ { ++ case MUX_PM_UART: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 2, 1 << 2); ++ break; ++ case MUX_FUART: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 0, 1 << 0); ++ break; ++ case MUX_UART0: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 1, 1 << 1); ++ break; ++ case MUX_UART1: ++ OUTREGMSK16(REG_FORCE_RX_DISABLE, (~status) << 3, 1 << 3); ++ break; ++ default: ++ UART_ERR("[%s] Padmux %d not defined\n", __func__, padmux); ++ break; ++ } ++} ++ ++U16 ms_uart_set_clk(struct uart_port *p, u32 request_baud) ++{ ++ //struct clk *clk; ++ unsigned int num_parents; ++ struct clk **clk_parents; ++ unsigned int tolerance, rate, divisor, real_baud; ++ struct ms_uart_port *mp; ++ int i; ++ ++ if(!p->dev) ++ { ++ //do nothing because clk and device node not ready ++ return 0; ++ } ++ else ++ { ++ mp = (struct ms_uart_port*)(p->dev->driver_data); ++ if (IS_ERR(mp->clk)) { ++ UART_ERR("%s: of_clk_get failed\n", p->dev->of_node->full_name); ++ p->uartclk=172800000; ++ return 0; ++ } ++ num_parents = __clk_get_num_parents(mp->clk); ++ ++ if(!num_parents) ++ { ++ p->uartclk=clk_get_rate(mp->clk); ++ return 0; ++ } ++ else ++ { ++ if(of_property_read_u32(p->dev->of_node, "tolerance", &tolerance)) ++ { ++ UART_DBG("%s: use default tolerance 3%%\n", __func__); ++ tolerance = 3; ++ } ++ ++ clk_parents = kzalloc((sizeof(*clk_parents) * num_parents), GFP_KERNEL); ++ if(!clk_parents) ++ { ++ UART_DBG("%s: failed to allocate memory\n", __func__); ++ kfree(clk_parents); ++ p->uartclk=clk_get_rate(mp->clk); ++ return 0; ++ } ++ ++ for(i = 0; i < num_parents; i++) ++ { ++ clk_parents[i] = clk_get_parent_by_index(mp->clk, i); ++ rate = clk_get_rate(clk_get_parent_by_index(mp->clk, i)); ++ divisor = (rate + (8*request_baud)) / (16*request_baud); ++ real_baud = rate / (16 * divisor); ++ ++ UART_DBG("[uart%d]foreach parent divisor0x%02X, real_baud%d,uart_clk%d\n", p->line, divisor, real_baud,rate); ++ if( (abs(real_baud - request_baud)*100/request_baud) < tolerance) ++ { ++ clk_set_parent(mp->clk, clk_parents[i]); ++ p->uartclk=clk_get_rate(mp->clk); ++ UART_DBG("[uart%d] uartclk=%d, request_baud=%d, real_baud=%d, divisor=0x%X\n", p->line, p->uartclk, request_baud, real_baud, divisor); ++ break; ++ } ++ } ++ ++ if(i >= num_parents) ++ { ++ UART_ERR("[uart%d] can't find suitable clk for baud=%d tolerance=%d%%, will not changed\n", p->line, request_baud, tolerance); ++ divisor = 0; ++ } ++ kfree(clk_parents); ++ return divisor; ++ } ++ } ++} ++ ++void ms_uart_set_divisor(struct uart_port *p, u16 divisor) ++{ ++ ms_uart_clear_fifos(p); ++ ++ // enable Divisor Latch Access, so Divisor Latch register can be accessed ++ OUTREG8(REG_LCR(p), INREG8(REG_LCR(p)) | UART_LCR_DLAB); ++ OUTREG8(REG_DLH_IER(p), (u8 )((divisor >> 8) & 0xff)); ++ OUTREG8(REG_DLL_THR_RBR(p), (u8 )(divisor & 0xff)); ++ // disable Divisor Latch Access ++ OUTREG8(REG_LCR(p), INREG8(REG_LCR(p)) & ~UART_LCR_DLAB); ++} ++ ++static void ms_uart_console_putchar(struct uart_port *p, s32 ch) ++{ ++ u8 lsr_u8 = 0; /* Line Status Register (LSR) */ ++ ++ /* Check if Transmit FIFO full */ ++ /* we can not modify the Tx FIFO size, default is 1 byte size*/ ++ ++ lsr_u8 = INREG8(REG_LSR(p)); ++ while(!(lsr_u8 & UART_LSR_THRE)) ++ { ++ lsr_u8 = INREG8(REG_LSR(p)); ++ } ++ ++ OUTREG8(REG_DLL_THR_RBR(p),ch); ++ ++ /* Check if both TX FIFO buffer & shift register are empty */ ++ //lsr_u8 = INREG8(REG_LSR(p)); ++ //while((lsr_u8 & (UART_LSR_TEMT | UART_LSR_THRE)) != (UART_LSR_TEMT | UART_LSR_THRE)) ++ //{ ++ // lsr_u8 = INREG8(REG_LSR(p)); ++ //} ++} ++ ++ ++static void ms_uart_console_write(struct console *co, const char *str, u32 count) ++{ ++ struct ms_uart_port *mp; ++ struct uart_port *p; ++ unsigned long flags; ++ int locked = 1; ++ ++ if( (!str )|| co->index>=NR_CONSOLE_PORTS || co->index < 0) ++ { ++ return; ++ } ++ ++ mp = console_ports[co->index]; ++ p = &(mp->port); ++ ++ if (p->sysrq || oops_in_progress) ++ locked = spin_trylock_irqsave(&p->lock, flags); ++ else ++ spin_lock_irqsave(&p->lock, flags); ++ ++ if(!mp->use_dma) ++ uart_console_write(p, str, count, ms_uart_console_putchar); ++ ++ ++ if (locked) ++ spin_unlock_irqrestore(&p->lock, flags); ++ ++ return; ++} ++ ++ ++static s32 __init ms_uart_console_setup(struct console *co, char *options) ++{ ++ /* Define Local Variables */ ++ s32 baud =115200; ++ s32 bits = 8; ++ s32 parity = 'n'; ++ s32 flow = 'n'; ++ ++ if(!options) ++ { ++ options = "115200n8r"; /* Set default baudrate for console*/ ++ } ++ ++ /* validate console port index */ ++ if(co->index == -1 || co->index >= NR_CONSOLE_PORTS) ++ { ++ co->index = 0; ++ } ++ ++ /* parsing the command line arguments */ ++ uart_parse_options(options, &baud, &parity, &bits, &flow); ++ if(console_ports[co->index]==NULL){ ++ return -ENODEV; ++ } ++ ++ return uart_set_options(&(console_ports[co->index]->port), co, baud, parity, bits, flow); ++} ++ ++static void ms_uart_add_console_port(struct ms_uart_port *ur) ++{ ++ if(ur->port.line < NR_CONSOLE_PORTS ) ++ { ++ console_ports[ur->port.line] = ur; ++ } ++} ++ ++static const char * ms_uart_type(struct uart_port *pPort_st) ++{ ++ return NULL; ++} ++ ++static void ms_uart_release_port(struct uart_port *pPort_st) ++{ ++ ++} ++ ++static s32 ms_uart_request_port(struct uart_port *pPort_st) ++{ ++ int ret=0; ++ return ret; ++} ++ ++static void ms_uart_config_port(struct uart_port *pPort_st, s32 flags) ++{ ++ ++} ++ ++static s32 ms_uart_verify_port(struct uart_port *pPort_st, struct serial_struct *ser) ++{ ++ int ret=0; ++ return ret; ++} ++ ++ ++static void ms_uart_enable_ms(struct uart_port *pPort_st) ++{ ++ ++} ++ ++static u32 ms_uart_get_mctrl(struct uart_port *pPort_st) ++{ ++ return (TIOCM_CAR|TIOCM_CTS|TIOCM_DSR); ++} ++ ++static void ms_uart_set_mctrl(struct uart_port *pPort_st, u32 mctrl) ++{ ++ ++} ++ ++ ++static void ms_uart_break_ctl(struct uart_port *pPort_st, s32 break_state) ++{ ++ ++} ++ ++ ++static void ms_uart_stop_tx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp = (struct ms_uart_port*)(p->dev->driver_data); ++ ++ if(!mp->use_dma) ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI); ++ //NOTE: Read IIR to clear dummy THRI after disable THRI occurred at ZEBU -- Spade ++ INREG8(REG_IIR_FCR(p)); ++#endif ++ } ++ else ++ { ++// printk(KERN_ERR "DMA_TX_STOP\n"); ++ URDMA_TxSetupTimeoutInterrupt(p, FALSE); ++ } ++} ++ ++static void ms_uart_stop_rx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ if(!mp->use_dma) ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ CLRREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ CLRREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++#endif ++ } ++} ++ ++static void ms_uart_start_tx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ if(!mp->use_dma) ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI); ++#endif ++ } ++ else ++ { ++// pr_err("DMA_TX_START\n"); ++ URDMA_TxSetupTimeoutInterrupt(p, TRUE); ++ URDMA_StartTx(p); ++ } ++} ++ ++static u32 ms_uart_tx_empty(struct uart_port *p) ++{ ++ int ret=0; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ if(!mp->use_dma) ++ { ++ /* Check if both TX FIFO buffer & shift register are empty */ ++ if((INREG8(REG_LSR(p)) & (UART_LSR_TEMT | UART_LSR_THRE)) == (UART_LSR_TEMT | UART_LSR_THRE)) ++ { ++ ret=TIOCSER_TEMT; /*if no support, also return this */ ++ } ++ ++ } ++ else ++ { ++ if(mp->urdma->reg_base->tx_buf_rptr == mp->urdma->reg_base->tx_buf_wptr) ++ { ++ return TIOCSER_TEMT; /*if no support, also return this */ ++ } ++ else ++ { ++ return 0; ++ } ++ } ++ ++ return ret; ++} ++ ++#if UART_TX_TASK ++static void ms_do_xmit_task(unsigned long port_address) ++{ ++ /* Define Local Variables */ ++ s32 count = 0; ++ struct circ_buf *xmit; ++ u8 u8USR = 0; ++ struct uart_port* p = (struct uart_port*) ((void *) port_address); ++ ++ /* Parameter out-of-bound check */ ++ if (!p) ++ { ++ UART_ERR("ms_do_xmit_task: port is NULL\n"); ++ return; ++ } ++ ++ xmit = &p->state->xmit; ++ ++ if (p->x_char) ++ { ++ ++ while( !( INREG8(REG_LSR(p)) & UART_LSR_THRE ) ) ++ { ++ //nothing to do ++ } ++ ++ OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]); ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ p->icount.tx++; ++ p->x_char = 0; ++ return; ++ } ++ ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ return; ++ } ++ ++ u8USR = INREG8(REG_USR(p)); ++ if (UART_USR_TXFIFO_EMPTY == (u8USR & (UART_USR_TXFIFO_EMPTY))) // Tx FIFO Empty ++ { ++ count = p->fifosize; ++ } ++ else if (UART_USR_TXFIFO_NOT_FULL == (u8USR & (UART_USR_TXFIFO_NOT_FULL))) // not empty, but not full ++ { ++ count = 1; ++ } ++ ++ do { ++ OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]); ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ p->icount.tx++; ++ ++ if (uart_circ_empty(xmit)) ++ { ++ break; ++ } ++ } while (--count > 0); ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(p); ++ ++ if (uart_circ_empty(xmit)) ++ { ++ ms_uart_stop_tx(p); ++ return; ++ } ++ ++#if UART_USE_SPINLOCK ++ { ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++ } ++#else ++ SETREG8(REG_DLH_IER(p), UART_IER_THRI); ++#endif ++ return; ++} ++ ++#else // UART_TX_TASK = 0 ++static void ms_putchar(struct uart_port *p) ++{ ++ /* Define Local Variables */ ++ int count; ++ struct circ_buf *xmit; ++ u8 u8USR = 0; ++ ++ /* Parameter out-of-bound check */ ++ if (!p) ++ { ++ UART_ERR("ms_putchar: port is NULL\n"); ++ return; ++ } ++ ++ xmit = &p->state->xmit; ++ ++ if (p->x_char) ++ { ++ while( !( INREG8(REG_USR(p)) & UART_USR_TXFIFO_NOT_FULL ) ) ++ { ++ //nothing to do ++ } ++ OUTREG8(REG_DLL_THR_RBR(p), p->x_char); ++ p->icount.tx++; ++ p->x_char = 0; ++ return; ++ } ++ ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ return; ++ } ++ ++ u8USR = INREG8(REG_USR(p)); ++ ++ if (UART_USR_TXFIFO_EMPTY == (u8USR & (UART_USR_TXFIFO_EMPTY))) // Tx FIFO Empty ++ { ++ count = p->fifosize; ++ } ++ else if (UART_USR_TXFIFO_NOT_FULL == (u8USR & (UART_USR_TXFIFO_NOT_FULL))) // not empty, but not full ++ { ++ count = 1; ++ }else ++ { ++ count = 1; ++ } ++ ++ do { ++ OUTREG8(REG_DLL_THR_RBR(p), xmit->buf[xmit->tail]); ++ ++ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); ++ p->icount.tx++; ++ ++ if (uart_circ_empty(xmit)) ++ { ++ break; ++ } ++ } while (--count > 0); ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(p); ++ ++ if (uart_circ_empty(xmit)) ++ { ++ ms_uart_stop_tx(p); ++ } ++} ++#endif ++ ++ ++static void ms_getchar(struct uart_port *p) ++{ ++ u8 lsr = 0; /* Line Status Register (LSR) */ ++ u32 flag = 0; ++ u32 ch = 0; /* Character read from UART port */ ++ int max_count = p->fifosize; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ static u8 rx_disable = 0, pad_disable = 0; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&p->lock, flags); ++ ++ /* Read Line Status Register */ ++ lsr = INREG8(REG_LSR(p)); ++ ++ /* check if Receiver Data Ready */ ++ if((lsr & UART_LSR_DR) != UART_LSR_DR) ++ { ++ mp->rx_guard++; ++ if(unlikely(mp->rx_guard>2000)) ++ { ++ ch=INREG8(REG_DLL_THR_RBR(p)); ++ UART_ERR("rx interrupts error!!!!!"); ++ mp->rx_guard=0; ++ } ++ /* Data NOT Ready */ ++ return ; ++ } ++ mp->rx_guard=0; ++ ++ /* while data ready, start to read data from UART FIFO */ ++ do{ ++ flag = TTY_NORMAL; ++ /* read data from UART IP */ ++ ch = INREG8(REG_DLL_THR_RBR(p)); ++ p->icount.rx++; ++ ++ if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE | UART_LSR_FE | UART_LSR_OE))) ++ { ++ if (lsr & UART_LSR_BI) { ++ lsr &= ~(UART_LSR_FE | UART_LSR_PE); ++ p->icount.brk++; ++ /* ++ * We do the SysRQ and SAK checking ++ * here because otherwise the break ++ * may get masked by ignore_status_mask ++ * or read_status_mask. ++ */ ++ if (uart_handle_break(p)) ++ goto IGNORE_CHAR; ++ } ++ else if (lsr & UART_LSR_PE) ++ { ++ p->icount.parity++; ++ } ++ else if (lsr & UART_LSR_FE) ++ { ++ p->icount.frame++; ++ } ++ else if (lsr & UART_LSR_OE) ++ { ++ p->icount.overrun++; ++ } ++ ++ /* ++ * Mask off conditions which should be ingored. ++ */ ++ lsr &= p->read_status_mask; ++ ++ if (lsr & UART_LSR_BI) { ++ UART_DBG("handling break....\n"); ++ flag = TTY_BREAK; ++ } ++ else if (lsr & UART_LSR_PE) ++ { ++ flag = TTY_PARITY; ++ } ++ else if (lsr & UART_LSR_FE) ++ { ++ flag = TTY_FRAME; ++ } ++ } ++ #ifdef SUPPORT_SYSRQ ++ if (uart_handle_sysrq_char(p, ch)) ++ { ++ goto IGNORE_CHAR; ++ } ++ #endif ++ uart_insert_char(p, lsr, UART_LSR_OE, ch, flag); ++ ++ //when receive '11111', disable UART RX to use TV tool ++ if(ch == '1') ++ rx_disable++; ++ else ++ rx_disable=0; ++ ++ if(rx_disable == 5) ++ { ++ CLRREG16(0x1F001C24, 0x1<<11); ++ rx_disable=0; ++ } ++ //when receive '22222', disable UART PAD to use TV tool ++ if(ch == '2') ++ pad_disable++; ++ else ++ pad_disable=0; ++ ++ if(pad_disable == 5) ++ { ++ CLRREG16(0x1F203D4C, 0x000F); ++ pad_disable=0; ++ } ++ ++IGNORE_CHAR: ++ lsr = INREG8(REG_LSR(p)); ++ }while((max_count-- >0)&&(lsr & UART_LSR_DR)); ++ ++ spin_unlock_irqrestore(&p->lock, flags); ++ tty_flip_buffer_push(&p->state->port); ++} ++ ++static irqreturn_t ms_uart_interrupt(s32 irq, void *dev_id) ++{ ++ /* Define Local Variables */ ++ u8 iir_fcr = 0; /* Interrupt Identification Register (IIR) */ ++ struct uart_port *p = dev_id; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ u8 count=0, retry=100; ++ ++ if(mp->use_dma) ++ { ++ u8 status = URDMA_GetInterruptStatus(p); ++ if(status & URDMA_INTR_STATUS_RX) ++ { ++ u8 intr_type = URDMA_RxGetInterrupt(p); ++ ++ if(intr_type & URDMA_RX_INTR_TYPE_TIMEOUT) ++ { ++ URDMA_RxSetupTimeoutInterrupt(p,FALSE); ++ } ++ ++ if(intr_type & URDMA_RX_INTR_TYPE_THRESHOLD) ++ { ++ URDMA_RxSetupThresholdInterrupt(p,FALSE); ++ } ++ URDMA_RxClearInterrupt(p); ++ ++ URDMA_StartRx(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ } ++ else if(status & URDMA_INTR_STATUS_TX) ++ { ++ URDMA_TxClearInterrupt(p); ++ //do nothing ++ } ++ else ++ UART_ERR("URDMA dummy interrupt!\n"); ++ } ++ else ++ { ++ /* Read Interrupt Identification Register */ ++ iir_fcr = INREG8(REG_IIR_FCR(p)) & UART_IIR_ID_MASK; ++ ++ if( (iir_fcr == UART_IIR_RDI || iir_fcr == UART_IIR_RX_TIMEOUT) ) /* Receive Data Available or Character timeout */ ++ { ++ ms_getchar(p); ++ } ++ else if( iir_fcr == UART_IIR_THRI ) /* Transmitter Holding Register Empty */ ++ { ++ #if UART_TX_TASK ++ #if UART_USE_SPINLOCK ++ unsigned long flags=0; ++ spin_lock_irqsave(&p->lock, flags); ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI); ++ spin_unlock_irqrestore(&p->lock, flags); ++ #else ++ CLRREG8(REG_DLH_IER(p), UART_IER_THRI); ++ #endif ++ ++ tasklet_schedule(&mp->xmit_tasklet); ++ #else ++ ms_putchar(p); ++ #endif ++ } ++ else if( iir_fcr == UART_IIR_MSI ) /* Modem Status */ ++ { ++ UART_ERR("UART Interrupt: Modem status\n"); ++ // Read MSR to clear ++ INREG8(REG_MSR(p)); ++ } ++ else if( iir_fcr == UART_IIR_BUSY ) /* Busy detect indication */ ++ { ++ // Read USR to clear ++ INREG8(REG_USR(p)); ++ ++ while( ((INREG8(REG_IIR_FCR(p)) & UART_IIR_ID_MASK) == UART_IIR_BUSY) && (count < retry)) ++ { ++ // Read USR to clear ++ INREG8(REG_USR(p)); ++ count++; ++ } ++ if (count == retry) ++ UART_ERR("UART Interrupt: UART_IIR_BUSY\n"); ++ ++ } ++ else if( iir_fcr == UART_IIR_RLSI ) /* Receiver line status */ ++ { ++ // Read LSR to clear ++ INREG8(REG_LSR(p)); ++ } ++ else if( iir_fcr == UART_IIR_NO_INT ) /* No pending interrupts */ ++ { ++ while( ((INREG8(REG_USR(p)) & UART_USR_BUSY) == UART_USR_BUSY) && (count < retry)) ++ { ++ count++; ++ } ++ if (count == retry) ++ UART_ERR("UART%d Interrupt: No IRQ rasied by UART, but come in to UART ISR. IIR:0x%02X USR:0x%02X\n", p->line, iir_fcr, INREG8(REG_USR(p))); ++ } ++ else /* Unknown Status */ ++ { ++ UART_ERR("UART Unknown Interrupt, IIR:0x%02X\n", iir_fcr); ++ } ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static s32 ms_uart_startup(struct uart_port *p) ++{ ++ /* Define Local Variables */ ++ int rc = 0; ++ struct ms_uart_port *mp = (struct ms_uart_port*)p->dev->driver_data; ++ ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ ms_uart_clear_fifos(p); ++ ++ /*we do not support CTS now*/ ++ p->flags &= ~ASYNC_CTS_FLOW; ++ ++#if UART_TX_TASK ++ tasklet_init(&mp->xmit_tasklet, ms_do_xmit_task, (unsigned long)p); ++#endif ++ ++ if(mp->use_dma) ++ { ++ rc = request_irq(mp->urdma->urdma_irq, ms_uart_interrupt, IRQF_SHARED, "ms_serial_dma",p); ++ } ++ else ++ { ++ OUTREG8(REG_DLH_IER(p), 0); ++ INREG8(REG_LSR(p)); ++ INREG8(REG_DLL_THR_RBR(p)); ++ INREG8(REG_IIR_FCR(p)); ++ INREG8(REG_MSR(p)); ++ rc = request_irq(p->irq, ms_uart_interrupt, IRQF_SHARED, "ms_serial",p); ++ } ++ ++ /* Print UART interrupt request status */ ++ if (rc) { ++ /* UART interrupt request failed */ ++ UART_ERR("ms_startup(): UART%d request_irq()is failed. return code=%d\n", p->line, rc); ++ } else { ++ /* UART interrupt request passed */ ++ UART_DBG("ms_startup(): UART%d request_irq() is passed.\n", p->line); ++ } ++ ++ mp->rx_guard=0; ++ ++ ++ if(mp->use_dma) ++ { ++ URDMA_Reset(p); ++ URDMA_Activate(p,TRUE); ++ URDMA_TxInit(p); ++ URDMA_TxEnable(p,TRUE); ++ URDMA_RxInit(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ URDMA_RxEnable(p,TRUE); ++ } ++ else ++ { ++#if UART_USE_SPINLOCK ++ unsigned long flags; ++ spin_lock_irqsave(&p->lock, flags); ++ SETREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++ spin_unlock_irqrestore(&p->lock, flags); ++#else ++ SETREG8(REG_DLH_IER(p), UART_IER_RDI | UART_IER_RLSI); ++#endif ++ } ++ ++ ms_force_rx_disable(mp->padmux, ENABLE); ++ ms_select_pad(p, mp->padmux, mp->pad_mode); ++ ++ return rc; ++} ++ ++ ++static void ms_uart_shutdown(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(mp->use_dma) ++ { ++ URDMA_RxEnable(p,FALSE); ++ URDMA_TxEnable(p,FALSE); ++ URDMA_TxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_TxClearInterrupt(p); ++ URDMA_RxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_RxSetupThresholdInterrupt(p,FALSE); ++ URDMA_RxClearInterrupt(p); ++ URDMA_Activate(p,FALSE); ++ disable_irq(mp->urdma->urdma_irq); ++ free_irq(mp->urdma->urdma_irq, p); ++ } ++ else ++ { ++#if UART_USE_LOOPBACK ++ //set loopback mode ++ SETREG8(REG_MCR(p), 0x10); ++#endif ++ CLRREG8(REG_LCR(p), UART_LCR_SBC); ++ ms_uart_clear_fifos(p); ++ INREG8(REG_DLL_THR_RBR(p)); ++ ++#if UART_USE_LOOPBACK ++ //clear loopback mode ++ CLRREG8(REG_MCR(p), 0x10); ++#endif ++ //OUTREG8(REG_DLH_IER(p), 0); ++ disable_irq(p->irq); ++ free_irq(p->irq, p); ++ } ++ ++ ms_force_rx_disable(mp->padmux, DISABLE); ++} ++ ++static void ms_uart_set_termios(struct uart_port *p, struct ktermios *pTermios_st, struct ktermios *pOld_st) ++{ ++ /* Define Local Variables */ ++ struct ms_uart_port *mp; ++ u8 uartflag = 0; ++ u16 divisor = 0; ++ u32 baudrate = 0; ++ ++ //OUTREG8(REG_DLH_IER(p), 0); ++ ++ if(p->dev) ++ { ++ mp=(struct ms_uart_port*)p->dev->driver_data; ++ if(mp->use_dma) ++ URDMA_Activate(p,FALSE); ++ ms_force_rx_disable(mp->padmux, DISABLE); ++ } ++ ++ /*------- Configure Chararacter Size --------*/ ++ switch (pTermios_st->c_cflag & CSIZE) ++ { ++ case CS5: /* Word length is 5 bits */ ++ uartflag |= UART_LCR_WLEN5; ++ break; ++ case CS6: /* Word length is 6 bits */ ++ uartflag |= UART_LCR_WLEN6; ++ break; ++ case CS7: /* Word length is 7 bits */ ++ uartflag |= UART_LCR_WLEN7; ++ break; ++ case CS8: /* Word length is 8 bits */ ++ uartflag |= UART_LCR_WLEN8; ++ break; ++ default: ++ UART_ERR("%s unsupported bits:%d\n", __FUNCTION__, pTermios_st->c_cflag & CSIZE); ++ break; ++ } ++ ++ /*------------ Configure Stop bit -----------*/ ++ if (pTermios_st->c_cflag & CSTOPB) ++ { ++ /* Stop length is 1.5 bits (5-bit char), 2 bits (otherwise) */ ++ uartflag |= UART_LCR_STOP2; ++ } ++ else ++ { ++ /* Stop length is 1 bit */ ++ uartflag |= UART_LCR_STOP1; ++ } ++ ++ /*----------- Configure Parity --------------*/ ++ if (pTermios_st->c_cflag & PARENB) ++ { ++ /* Parity Enable */ ++ uartflag |= UART_LCR_PARITY_EN; ++ ++ /* Set Odd/Even Parity */ ++ if (pTermios_st->c_cflag & PARODD) ++ { ++ /* Odd Parity */ ++ uartflag &= (~UART_LCR_PARITY_SEL); ++ } ++ else ++ { ++ /* Even Parity */ ++ uartflag |= UART_LCR_PARITY_SEL; ++ } ++ } ++ else ++ { ++ /* Parity Disable */ ++ uartflag &= (~UART_LCR_PARITY_EN); ++ } ++ OUTREG8(REG_LCR(p), uartflag); ++ ++ //NOTE: we are going to set LCR, be carefully here ++ baudrate = uart_get_baud_rate(p, pTermios_st, pOld_st, 0, 115200 * 8); ++ divisor = ms_uart_set_clk(p, baudrate); ++ if(divisor) ++ ms_uart_set_divisor(p, divisor); ++ ++ OUTREG8(REG_IIR_FCR(p), UART_FCR_FIFO_ENABLE | UART_FCR_TRIGGER_TX_L0 | UART_FCR_TRIGGER_RX_L3); ++ INREG8(REG_DLL_THR_RBR(p)); ++ ++ if(p->dev) ++ { ++ if(mp->use_dma) ++ { ++ URDMA_Reset(p); ++ URDMA_Activate(p,TRUE); ++ URDMA_TxInit(p); ++ URDMA_TxEnable(p,TRUE); ++ URDMA_RxInit(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ URDMA_RxEnable(p,TRUE); ++ } ++ ms_force_rx_disable(mp->padmux, ENABLE); ++ } ++} ++ ++/* UART Operations */ ++static struct uart_ops ms_uart_ops = ++{ ++ .tx_empty = ms_uart_tx_empty, ++ .set_mctrl = ms_uart_set_mctrl, /* Not supported in MSB2501 */ ++ .get_mctrl = ms_uart_get_mctrl, /* Not supported in MSB2501 */ ++ .stop_tx = ms_uart_stop_tx, ++ .start_tx = ms_uart_start_tx, ++ .stop_rx = ms_uart_stop_rx, ++ .enable_ms = ms_uart_enable_ms, /* Not supported in MSB2501 */ ++ .break_ctl = ms_uart_break_ctl, /* Not supported in MSB2501 */ ++ .startup = ms_uart_startup, ++ .shutdown = ms_uart_shutdown, ++ .set_termios = ms_uart_set_termios, ++ .type = ms_uart_type, /* Not supported in MSB2501 */ ++ .release_port = ms_uart_release_port, /* Not supported in MSB2501 */ ++ .request_port = ms_uart_request_port, /* Not supported in MSB2501 */ ++ .config_port = ms_uart_config_port, /* Not supported in MSB2501 */ ++ .verify_port = ms_uart_verify_port, /* Not supported in MSB2501 */ ++}; ++ ++#ifdef CONFIG_PM ++static s32 ms_uart_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ struct ms_uart_port *mp=platform_get_drvdata(pdev); ++ struct uart_port *p=&mp->port; ++ ++ UART_DBG("[%s] uart%d\n", __func__, p->line); ++ ++ if(mp->use_dma) ++ { ++ URDMA_RxEnable(p,FALSE); ++ URDMA_TxEnable(p,FALSE); ++ URDMA_TxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_TxClearInterrupt(p); ++ URDMA_RxSetupTimeoutInterrupt(p,FALSE); ++ URDMA_RxSetupThresholdInterrupt(p,FALSE); ++ URDMA_RxClearInterrupt(p); ++ URDMA_Activate(p,FALSE); ++ } ++ ++ uart_suspend_port(&ms_uart_driver, p); ++ ++ mp->backupIER = INREG8(REG_DLH_IER(p)); ++ mp->backupLCR = INREG8(REG_LCR(p)); ++ mp->backupMCR = INREG8(REG_MCR(p)); ++ ++ OUTREG8(REG_DLH_IER(p), 0); ++ ms_uart_clear_fifos(p); ++ ++ OUTREG8(REG_LCR(p) , mp->backupLCR | UART_LCR_DLAB); ++ ++ mp->backupDivisor = (INREG8(REG_DLH_IER(p)) << 8); ++ mp->backupDivisor |= (INREG8(REG_DLL_THR_RBR(p)) & 0xFF); ++ ++ if (!IS_ERR(mp->clk)) ++ clk_disable_unprepare(mp->clk); ++ ++ return 0; ++} ++ ++static s32 ms_uart_resume(struct platform_device *pdev) ++{ ++ struct ms_uart_port *mp=platform_get_drvdata(pdev); ++ struct uart_port *p=&mp->port; ++ ++ if (!IS_ERR(mp->clk)) ++ clk_prepare_enable(mp->clk); ++ ++ ms_uart_set_divisor(p, mp->backupDivisor); ++ ++ OUTREG8(REG_MCR(p), mp->backupMCR); ++ OUTREG8(REG_LCR(p), mp->backupLCR); ++ OUTREG8(REG_DLH_IER(p), mp->backupIER); ++ ++ if(mp->use_dma) ++ { ++ URDMA_Reset(p); ++ URDMA_Activate(p,TRUE); ++ URDMA_TxInit(p); ++ URDMA_TxEnable(p,TRUE); ++ URDMA_RxInit(p); ++ URDMA_RxSetupTimeoutInterrupt(p,TRUE); ++ URDMA_RxSetupThresholdInterrupt(p,TRUE); ++ URDMA_RxEnable(p,TRUE); ++ } ++ ++ uart_resume_port(&ms_uart_driver, &mp->port); ++ ++ UART_DBG("[%s] uart%d\n", __func__, p->line); ++ ++ return 0; ++} ++#endif ++ ++static s32 ms_uart_remove(struct platform_device *pdev) ++{ ++ struct ms_uart_port *mp=platform_get_drvdata(pdev); ++ ++ uart_remove_one_port(&ms_uart_driver,&mp->port); ++ ++ if(mp->use_dma) ++ { ++ dma_free_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH), &mp->urdma->rx_urdma_base, GFP_KERNEL); ++ dma_free_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH), &mp->urdma->tx_urdma_base, GFP_KERNEL); ++ } ++ ++ if (!IS_ERR(mp->clk)) ++ clk_disable_unprepare(mp->clk); ++ ++ return 0; ++} ++ ++static s32 ms_uart_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct ms_uart_port *mp; ++ struct ms_urdma *urdma; ++ struct resource *res; ++ int tx_pad; ++ ++ if(!pdev) ++ { ++ UART_ERR("ms_uart_probe() parameter pdev is NULL\n"); ++ return -ENOMEM; ++ } ++ mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL); ++ if (!mp) ++ return -ENOMEM; ++ ++ spin_lock_init(&mp->port.lock); ++ ++ mp->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); ++ /*if (mp->port.line < 0) { ++ UART_ERR("[%s] failed to get alias/pdev id = %d\n", __func__, mp->port.line); ++ return -EINVAL; ++ }*/ ++ pdev->id=mp->port.line; ++ ++ mp->clk = of_clk_get(pdev->dev.of_node, 0); ++ if(IS_ERR(mp->clk)) ++ { ++ UART_ERR("[%s] of_clk_get failed\n", __func__); ++ return -EINVAL; ++ } ++ //enable clk in probe, because if UART no clk, it can not be accessed. ++ clk_prepare_enable(mp->clk); ++ mp->port.uartclk = clk_get_rate(mp->clk); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ UART_ERR("no memory resource defined\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ mp->port.membase = (void *)res->start; ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (res == NULL) { ++ UART_ERR("no irq resource defined\n"); ++ ret = -ENODEV; ++ goto out; ++ } ++ mp->port.irq = res->start; ++ ++ of_property_read_u32(pdev->dev.of_node, "dma", &mp->use_dma); ++ ++ if(mp->use_dma) ++ { ++ mp->urdma = devm_kzalloc(&pdev->dev, sizeof(*urdma), GFP_KERNEL); ++ if (!mp->urdma) ++ { ++ mp->use_dma=0; ++ goto dma_err; ++ } ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (res == NULL) ++ { ++ mp->use_dma = 0; ++ UART_ERR("no urdma memory resource defined...\n"); ++ goto dma_err; ++ } ++ mp->urdma->reg_base = (reg_urdma *)IO_ADDRESS(res->start); ++ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); ++ if (res == NULL) ++ { ++ mp->use_dma = 0; ++ UART_ERR("no urdma irq resource defined\n"); ++ goto dma_err; ++ } ++ mp->urdma->urdma_irq = res->start; ++ mp->port.irq = res->start; ++ ++ mp->urdma->rx_buf = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH), ++ &mp->urdma->rx_urdma_base, GFP_KERNEL); ++ mp->urdma->tx_buf = dma_alloc_coherent(&pdev->dev, PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH), ++ &mp->urdma->tx_urdma_base, GFP_KERNEL); ++ if(!mp->urdma->rx_buf || !mp->urdma->tx_buf) ++ { ++ mp->use_dma = 0; ++ UART_ERR("Allocate urdma rx_buffer/tx_buffer failed, use UART mode\n"); ++ goto dma_err; ++ } ++ mp->urdma->rx_urdma_size = PAGE_ALIGN(UR2DMA_RX_BUF_LENGTH); ++ mp->urdma->tx_urdma_size = PAGE_ALIGN(UR2DMA_TX_BUF_LENGTH); ++ UART_DBG("[%s] URDMA mode enable, reg_base=0x%08X, irq=%d\n", __func__, (unsigned int)(mp->urdma->reg_base), mp->urdma->urdma_irq); ++ UART_ERR("URDMA rx_buf=0x%08X(phy:0x%08X) tx_buf=0x%08X(phy:0x%08X) size=0x%X\n", (unsigned int)mp->urdma->rx_buf, (unsigned int)mp->urdma->rx_urdma_base, (unsigned int)mp->urdma->tx_buf, (unsigned int)mp->urdma->tx_urdma_base, mp->urdma->rx_urdma_size); ++ } ++dma_err: ++ mp->port.type = PORT_8250; ++ mp->port.dev = &pdev->dev; ++ mp->port.ops=&ms_uart_ops; ++ mp->port.regshift = 0; ++ mp->port.fifosize = 16; ++ mp->port.timeout =HZ; ++ mp->port.iotype=UPIO_MEM; ++ ++ UART_DBG("[%s] line=%d name=%s\n", __func__, mp->port.line, pdev->name); ++ ++ //[2016.11.15] Add padmux select from DTB by Spade ++ if(of_property_read_u32(pdev->dev.of_node, "pad", &tx_pad)) //read property failed ++ { ++ //set default pad ++ if(mp->port.line==0) ++ { ++ UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_PM_UART"); ++ mp->padmux=MUX_PM_UART; ++ } ++ else if(mp->port.line==1) ++ { ++ UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_UART1"); ++ mp->padmux=MUX_UART1; ++ } ++ else if(mp->port.line==2) ++ { ++ UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, "MUX_FUART"); ++ mp->padmux=MUX_FUART; ++ } ++ else ++ { ++ UART_ERR("[%s] port line %d is not supported\n", __func__, mp->port.line); ++ ret = -EINVAL; ++ goto out; ++ } ++ } ++ else //read property successfully ++ { ++ switch(tx_pad) ++ { ++ case PAD_FUART_RX: ++ mp->padmux=MUX_FUART; ++ mp->pad_mode=0x1; ++ break; ++ ++ case PAD_GPIO0: ++ mp->padmux=MUX_FUART; ++ mp->pad_mode=0x2; ++ break; ++ ++ case PAD_UART0_TX: ++ mp->padmux=MUX_UART0; ++ mp->pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_TX: ++ mp->padmux=MUX_UART0; ++ mp->pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO4: ++ mp->padmux=MUX_UART0; ++ mp->pad_mode=0x3; ++ break; ++ ++ case PAD_UART1_TX: ++ mp->padmux=MUX_UART1; ++ mp->pad_mode=0x1; ++ break; ++ ++ case PAD_FUART_RTS: ++ mp->padmux=MUX_UART1; ++ mp->pad_mode=0x2; ++ break; ++ ++ case PAD_GPIO6: ++ mp->padmux=MUX_UART1; ++ mp->pad_mode=0x3; ++ break; ++ ++ default: ++ UART_ERR("[%s] Use undefined pad number %d\n", __func__, tx_pad); ++ ret = -EINVAL; ++ goto out; ++ } ++ UART_ERR("[%s] uart port %d use %s\n", __func__, mp->port.line, (mp->padmux==MUX_FUART)?"MUX_FUART":(mp->padmux==MUX_UART0)?"MUX_UART0":"MUX_UART1"); ++ } ++ ++ platform_set_drvdata(pdev, mp); ++ ++ ret = uart_add_one_port(&ms_uart_driver, &mp->port); ++ if (ret != 0) ++ goto out; ++ ++ return 0; ++out: ++ UART_ERR("[UART%d]: failure [%s]: %d\n", mp->port.line, __func__, ret); ++ clk_disable_unprepare(mp->clk); ++ return ret; ++} ++ ++static const struct of_device_id ms_uart_of_match_table[] = { ++ { .compatible = "mstar,uart" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, ms_uart_of_match_table); ++ ++static struct platform_driver ms_uart_platform_driver = { ++ .remove = ms_uart_remove, ++ .probe = ms_uart_probe, ++#ifdef CONFIG_PM ++ .suspend = ms_uart_suspend, ++ .resume = ms_uart_resume, ++#endif ++ .driver = { ++ .name = "ms_uart", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(ms_uart_of_match_table), ++ }, ++}; ++ ++static s32 __init ms_uart_module_init(void) ++{ ++ int ret; ++ ++ ret = uart_register_driver(&ms_uart_driver); ++ if (ret != 0) ++ return ret; ++ ret = platform_driver_register(&ms_uart_platform_driver); ++ if (ret != 0) ++ { ++ UART_ERR("[ms_uart]platform_driver_register failed!!\n"); ++ uart_unregister_driver(&ms_uart_driver); ++ } ++ return ret; ++} ++ ++ ++static void __exit ms_uart_module_exit(void) ++{ ++ platform_driver_unregister(&ms_uart_platform_driver); ++ uart_unregister_driver(&ms_uart_driver); ++} ++ ++module_init(ms_uart_module_init); ++module_exit(ms_uart_module_exit); ++ ++ ++static int __init ms_early_console_init(void) ++{ ++ struct device_node *console_np; ++ struct resource res; ++ ++ ++ console_np=of_find_node_by_path("console"); ++ if(!console_np) ++ return -ENODEV; ++ ++ ++ BUG_ON( of_address_to_resource(console_np,0,&res) ); ++ ++ console_port.port.membase = (void *)res.start; ++ ++ console_port.port.type = PORT_8250; ++ ++ console_port.port.ops=&ms_uart_ops; ++ console_port.port.regshift = 0; ++ console_port.port.fifosize = 16; ++ console_port.port.line=0; ++ console_port.port.cons=&ms_uart_console; ++ ++ ms_uart_add_console_port(&console_port); ++ register_console(&ms_uart_console); ++ ++ ++ return 0; ++} ++ ++console_initcall(ms_early_console_init); ++ ++void URDMA_Reset(struct uart_port *p) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->urdma_mode=1; ++ ++ mp->urdma->reg_base->tx_urdma_en = 0; ++ mp->urdma->reg_base->rx_urdma_en = 0; ++ ++ mp->urdma->reg_base->tx_intr_en = 0; ++ mp->urdma->reg_base->rx_intr1_en = 0; ++ mp->urdma->reg_base->rx_intr2_en = 0; ++ ++ /* clear interrupt status */ ++ mp->urdma->reg_base->tx_intr_clr = 1; ++ mp->urdma->reg_base->rx_intr_clr = 1; ++ ++ ++ /* software reset */ ++ mp->urdma->reg_base->sw_rst = 1; ++ ++ /* make sure rx_busy is off */ ++ for(i=0; (mp->urdma->reg_base->rx_busy || mp->urdma->reg_base->tx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ break; ++ } ++ } ++ ++ mdelay(10); ++ ++ mp->urdma->reg_base->sw_rst = 0; ++ ++ mp->urdma->reg_base->urdma_mode=0; ++} ++ ++void URDMA_Activate(struct uart_port *p,BOOL bEnable) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->urdma_mode=bEnable?TRUE:FALSE; ++ UART_DBG("URDMA_Activate: %d\n", bEnable); ++ ++} ++ ++void URDMA_TxEnable(struct uart_port *p,BOOL bEnable) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(bEnable) ++ { ++ mp->urdma->reg_base->tx_urdma_en = 1; ++ } ++ else ++ { ++ mp->urdma->reg_base->tx_urdma_en = 0; ++ for(i=0; (mp->urdma->reg_base->tx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ } ++} ++ ++void URDMA_RxEnable(struct uart_port *p,BOOL bEnable) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(bEnable) ++ { ++ mp->urdma->reg_base->rx_urdma_en = 1; ++ } ++ else ++ { ++ mp->urdma->reg_base->rx_urdma_en = 0; ++ for(i=0; (mp->urdma->reg_base->rx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ } ++} ++ ++U8 URDMA_GetInterruptStatus(struct uart_port *p) ++{ ++ U8 stat=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(mp->urdma->reg_base->rx_mcu_intr) ++ { ++ stat|=URDMA_INTR_STATUS_RX; ++ } ++ ++ if(mp->urdma->reg_base->tx_mcu_intr) ++ { ++ stat|=URDMA_INTR_STATUS_TX; ++ } ++ ++ return stat; ++} ++ ++void URDMA_TxInit(struct uart_port *p) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->tx_urdma_en = 0; /* disable dma */ ++ mp->urdma->reg_base->tx_sw_rst = 1; ++ for(i=0; (mp->urdma->reg_base->tx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ ++ mp->urdma->reg_base->tx_sw_rst = 0; ++ mp->urdma->reg_base->tx_buf_base_h = URDMA_HIU16((U32)mp->urdma->tx_urdma_base); ++ mp->urdma->reg_base->tx_buf_base_l = URDMA_LOU16((U32)mp->urdma->tx_urdma_base); ++ mp->urdma->reg_base->tx_buf_size = (mp->urdma->tx_urdma_size/8); ++ mp->urdma->reg_base->tx_timeout = URDMA_TX_TIMEOUT; ++ mp->urdma->reg_base->tx_buf_wptr = 0x0; ++ ++ //2015.10.21 Refine: initialize tx_buf_wptr to 1 because HW behavior is not correct from 0 to 1 ++ //2016.11.27 Refine: remove initial value for tx_buf_wptr ++ //mp->urdma->reg_base->tx_buf_wptr = 0x1; ++} ++ ++void URDMA_RxInit(struct uart_port *p) ++{ ++ unsigned int i=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_urdma_en = 0; /* disable dma */ ++ mp->urdma->reg_base->rx_sw_rst = 1; ++ for(i=0; (mp->urdma->reg_base->rx_busy); i++) ++ { ++ if(0xFFFF == i) ++ { ++ return; ++ } ++ } ++ ++ mp->urdma->reg_base->rx_sw_rst=0; ++ mp->urdma->reg_base->rx_buf_base_h = URDMA_HIU16((U32)mp->urdma->rx_urdma_base); ++ mp->urdma->reg_base->rx_buf_base_l = URDMA_LOU16((U32)mp->urdma->rx_urdma_base); ++ mp->urdma->reg_base->rx_buf_size = (mp->urdma->rx_urdma_size/8); ++ mp->urdma->reg_base->intr_threshold = URDMA_RX_INTR_LEVEL; ++ mp->urdma->reg_base->rx_timeout = URDMA_RX_TIMEOUT; /* receive timeout. */ ++ ++ //need to clear buffer? ++ //memset(dma_rx_buf[fuartNum].Buffer,0,dma_rx_buf[fuartNum].Length); ++ ++ //2016.11.27 Refine: sw_rx_rptr is the index of rx_buf we have read ++ //Give initial value (size-1) according to HW behavior ++ mp->urdma->sw_rx_rptr = mp->urdma->rx_urdma_size - 1; ++} ++ ++void URDMA_TxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnable) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->tx_intr_en = bEnable?1:0; ++} ++ ++void URDMA_TxClearInterrupt(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->tx_intr_clr = 1; /* clear int status */ ++} ++ ++void URDMA_RxSetupTimeoutInterrupt(struct uart_port *p,BOOL bEnableTimeout) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_intr1_en=bEnableTimeout?1:0; ++} ++ ++void URDMA_RxSetupThresholdInterrupt(struct uart_port *p,BOOL bEnableThreshold) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_intr2_en=bEnableThreshold?1:0; ++} ++ ++U8 URDMA_RxGetInterrupt(struct uart_port *p) ++{ ++ U8 intr=0; ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ if(mp->urdma->reg_base->rx_intr1) ++ { ++ intr |= URDMA_RX_INTR_TYPE_TIMEOUT; ++ } ++ ++ if(mp->urdma->reg_base->rx_intr2) ++ { ++ intr |= URDMA_RX_INTR_TYPE_THRESHOLD; ++ } ++ ++ return intr; ++} ++ ++void URDMA_RxClearInterrupt(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ mp->urdma->reg_base->rx_intr_clr = 1; /* clear int status */ ++} ++ ++U32 URDMA_GetWritableSize(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ ++ return (U32)((mp->urdma->reg_base->tx_buf_rptr - mp->urdma->reg_base->tx_buf_wptr - 1) & (mp->urdma->rx_urdma_size - 1)); ++} ++ ++void URDMA_StartTx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ struct circ_buf *xmit = &p->state->xmit; ++ U16 circ_buf_out_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); ++ U16 tx_buf_space, tx_end; ++ ++ /* tx_buf_wptr point to the byte have been written to buffer */ ++ /* tx_buf_rptr point to the byte have been sent */ ++ /* if tx_buf_rptr meets tx_buf_wptr, it means all written bytes in buffer have been sent */ ++ /* In this case, the space equal to buffer size */ ++ ++ U16 sw_tx_wptr = mp->urdma->reg_base->tx_buf_wptr; ++ U16 sw_tx_rptr = mp->urdma->reg_base->tx_buf_rptr; ++ ++ if(sw_tx_wptr == (mp->urdma->tx_urdma_size-1)) //wptr meet the end of buffer, start from (0), end at (rptr) ++ { ++ sw_tx_wptr = 0; ++ tx_buf_space = sw_tx_rptr; ++ } ++ else if(sw_tx_wptr >= sw_tx_rptr) //start from (wptr+1), end at (buffer_size-1) ++ { ++ sw_tx_wptr+=1; ++ tx_buf_space = mp->urdma->tx_urdma_size - sw_tx_wptr; ++ } ++ else //start from (wptr+1), end at (rptr) ++ { ++ sw_tx_wptr+=1; ++ tx_buf_space = sw_tx_rptr - sw_tx_wptr; ++ } ++ ++ //pr_debug("sw_wp=%4x, sw_rp=%4x, tx_space=%4x, circ_buf_out_size=%4x, head=%4x, tail=%4x\n", sw_tx_wptr, sw_tx_rptr, tx_space, circ_buf_out_size, xmit->head, xmit->tail); ++ ++ if(circ_buf_out_size > tx_buf_space) //tx_cnt > tx_space ++ { ++ memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]), &xmit->buf[xmit->tail], tx_buf_space); ++ p->icount.tx += tx_buf_space; ++ xmit->tail += tx_buf_space; ++ circ_buf_out_size -= tx_buf_space; ++ ++ //now we can start write from (0), end at (min[sw_tx_rptr,circ_buf_out_size]) ++ tx_end = circ_buf_out_size >= sw_tx_rptr ? sw_tx_rptr : circ_buf_out_size; ++ memcpy((void *)(&mp->urdma->tx_buf[0]), &xmit->buf[xmit->tail], tx_end); ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ p->icount.tx += tx_end; ++ xmit->tail = (xmit->tail + tx_end) & (UART_XMIT_SIZE - 1); ++ mp->urdma->reg_base->tx_buf_wptr = tx_end; ++ } ++ else //tx_cnt <= tx_space ++ { ++ memcpy((void *)(&mp->urdma->tx_buf[sw_tx_wptr]),&xmit->buf[xmit->tail], circ_buf_out_size); ++ ++ Chip_Flush_MIU_Pipe(); ++ ++ p->icount.tx += circ_buf_out_size; ++ xmit->tail = (xmit->tail + circ_buf_out_size) & (UART_XMIT_SIZE - 1); ++ mp->urdma->reg_base->tx_buf_wptr += circ_buf_out_size; ++ } ++ ++ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) ++ uart_write_wakeup(p); ++ ++ if (uart_circ_empty(xmit) || uart_tx_stopped(p)) ++ { ++ ms_uart_stop_tx(p); ++ } ++ return; ++} ++ ++void URDMA_StartRx(struct uart_port *p) ++{ ++ struct ms_uart_port *mp=(struct ms_uart_port*)p->dev->driver_data; ++ U16 sw_rx_wptr = mp->urdma->reg_base->rx_buf_wptr; ++ U16 sw_rx_rptr = mp->urdma->sw_rx_rptr; ++ U16 in_size = (sw_rx_wptr - sw_rx_rptr) & (mp->urdma->rx_urdma_size - 1); //read from (sw_rx_rptr+1), end at (sw_rx_wptr) ++ U16 rptr_to_end = mp->urdma->rx_urdma_size - sw_rx_rptr - 1; ++ ++ /* sw_rx_wptr point to the byte already read from UART */ ++ /* sw_rx_rptr point to the byte have been read */ ++ /* if sw_rx_rptr equal to sw_rx_wptr, it means all bytes in buffer have been read */ ++ ++ if(sw_rx_rptr==mp->urdma->rx_urdma_size - 1) //initial case ++ { ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[0], in_size - rptr_to_end); ++ p->icount.rx += in_size - rptr_to_end; ++ //update global sw_rx_rptr ++ mp->urdma->sw_rx_rptr = in_size - rptr_to_end -1; ++ tty_flip_buffer_push(&p->state->port); ++ pr_debug("(0) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size); ++ } ++ else if(in_size > rptr_to_end) ++ { ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[sw_rx_rptr+1], rptr_to_end); ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[0], in_size - rptr_to_end); ++ p->icount.rx += in_size; ++ //update global sw_rx_rptr ++ mp->urdma->sw_rx_rptr = (in_size - rptr_to_end - 1); ++ tty_flip_buffer_push(&p->state->port); ++ pr_debug("(1) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size); ++ } ++ else ++ { ++ tty_insert_flip_string(&p->state->port, &mp->urdma->rx_buf[(sw_rx_rptr+1)&(mp->urdma->rx_urdma_size-1)], in_size); ++ p->icount.rx += in_size; ++ //update global sw_rx_rptr ++ mp->urdma->sw_rx_rptr += in_size & (mp->urdma->rx_urdma_size - 1); //avoid sw_rx_rptr overflow ++ tty_flip_buffer_push(&p->state->port); ++ pr_debug("(2) sw_rx_rptr=0x%4x, in_size=0x%4x\n", mp->urdma->sw_rx_rptr, in_size); ++ } ++ return; ++} ++ ++ +diff --git a/drivers/mstar/sound/Kconfig b/drivers/mstar/sound/Kconfig +new file mode 100644 +index 00000000..412932b7 +--- /dev/null ++++ b/drivers/mstar/sound/Kconfig +@@ -0,0 +1,15 @@ ++menuconfig MS_SOUND ++ tristate "Audio driver" ++ select SOUND ++ select SND ++ select SND_SOC ++ select SND_PCM ++ help ++ Say Y or M if you want to add support for codecs attached to ++ the iNfinity3e Bach Aduio driver. ++ ++ ++config MS_SOUND_INFINITY3 ++ tristate "Audio support for iNfinity3e" ++ depends on MS_SOUND ++ depends on ARCH_INFINITY3 +diff --git a/drivers/mstar/sound/Makefile b/drivers/mstar/sound/Makefile +new file mode 100644 +index 00000000..42d76cbd +--- /dev/null ++++ b/drivers/mstar/sound/Makefile +@@ -0,0 +1,9 @@ ++EXTRA_CFLAGS += -Idrivers/mstar/include ++ ++# iNfinity3e Platform Support ++obj-$(CONFIG_MS_SOUND_INFINITY3) += infinity_dai.o infinity_pcm.o infinity_soc.o infinity_codec.o infinity_dma.o infinity.o ++ ++ ++ ++ ++ +diff --git a/drivers/mstar/sound/bach_audio_debug.h b/drivers/mstar/sound/bach_audio_debug.h +new file mode 100644 +index 00000000..08e3c711 +--- /dev/null ++++ b/drivers/mstar/sound/bach_audio_debug.h +@@ -0,0 +1,50 @@ ++/*------------------------------------------------------------------------------ ++ Copyright (c) 2010 MStar Semiconductor, Inc. All rights reserved. ++------------------------------------------------------------------------------*/ ++#ifndef _BACH_AUDIO_DEBUG_H_ ++#define _BACH_AUDIO_DEBUG_H_ ++//------------------------------------------------------------------------------ ++// Macros ++//------------------------------------------------------------------------------ ++ ++#if 0 ++#define TRACE_LEVEL_TAG 1 ++#define ERROR_LEVEL_TAG 1 ++#define DAI_LEVEL_TAG 0 ++#define CODEC_LEVEL_TAG 1 ++#define PLATFORM_LEVEL_TAG 1 ++#define PCM_LEVEL_TAG 1 ++#define PCM_DEBUG_LEVEL_TAG 0 ++#define PLAYBACK_IRQ_LEVEL_TAG 0 ++#define CAPTURE_IRQ_LEVEL_TAG 0 ++#else ++#define TRACE_LEVEL_TAG 0 ++#define ERROR_LEVEL_TAG 1 ++#define DAI_LEVEL_TAG 0 ++#define CODEC_LEVEL_TAG 0 ++#define PLATFORM_LEVEL_TAG 0 ++#define PCM_LEVEL_TAG 0 ++#define PCM_DEBUG_LEVEL_TAG 0 ++#define PLAYBACK_IRQ_LEVEL_TAG 0 ++#define CAPTURE_IRQ_LEVEL_TAG 0 ++#endif ++ ++ ++#define TRACE_LEVEL "[AUDIO TRACE]" ++#define ERROR_LEVEL "[AUDIO ERROR]" ++#define DAI_LEVEL "[AUDIO DAI]" ++#define CODEC_LEVEL "[AUDIO CODEC]" ++#define PLATFORM_LEVEL "[AUDIO PLATFORM]" ++#define PCM_LEVEL "[AUDIO PCM]" ++#define PCM_DEBUG_LEVEL "[PCM DEBUG]" ++#define PLAYBACK_IRQ_LEVEL "[PLAYBACK IRQ]" ++#define CAPTURE_IRQ_LEVEL "[CAPTURE IRQ]" ++ ++#define LOG_MSG 1 ++#if LOG_MSG ++#define AUD_PRINTF(level ,fmt, arg...) if (level##_TAG) printk(KERN_ERR level fmt, ##arg); ++#else ++#define AUD_PRINTF(level ,fmt, arg...) ++#endif ++ ++#endif /* _BACH_AUDIO_DEBUG_H_ */ +diff --git a/drivers/mstar/sound/infinity.c b/drivers/mstar/sound/infinity.c +new file mode 100644 +index 00000000..24d8ed91 +--- /dev/null ++++ b/drivers/mstar/sound/infinity.c +@@ -0,0 +1,1424 @@ ++// $Change: 548282 $ ++// ++// bach.cpp ++// ++// defines for the registers in the iNfinity3 BACH chip ++// ++// ++#if defined(__linux__) ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "infinity.h" ++ ++ ++#define DELAY(x) mdelay(x) ++#define SLEEP(x) schedule_timeout(msecs_to_jiffies(x * 1000)) ++#define UDELAY(x) udelay(x) //CAPDELAY(1000*us) ++ ++#endif ++ ++ ++const U16 g_nInfinityDmaIntReg[BACH_DMA_NUM][BACH_DMA_INT_NUM] = ++{ ++ {REG_WR_UNDERRUN_INT_EN, REG_WR_OVERRUN_INT_EN, 0, REG_WR_FULL_INT_EN}, ++ {REG_RD_UNDERRUN_INT_EN, REG_RD_OVERRUN_INT_EN, REG_RD_EMPTY_INT_EN, 0} ++}; ++ ++static S8 m_nInfinityDpgaGain[4] = {0, 0, 0, 0}; ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Variables ++//------------------------------------------------------------------------------------------------- ++ ++ ++static DMACHANNEL m_infinitydmachannel[2]; // info about dma channel states ++ ++static U32 m_pInfinityBaseRegAddr; ++static U32 m_pInfinityAudBank1RegAddr; ++static U32 m_pInfinityAudBank2RegAddr; ++static U32 m_pInfinityAudBank3RegAddr; ++ ++static BOOL m_bADCActive; ++static BOOL m_bDACActive; ++ ++static U16 m_nMicGain = 0x0; ++static U16 m_nMicInGain = 0x011; ++static U16 m_nLineInGain = 0x000; ++ ++static BOOL m_bInfinityAtopStatus[BACH_ATOP_NUM]; ++ ++ ++ ++ ++//------------------------------------------------------------------------------------------------- ++// Global Functions ++//------------------------------------------------------------------------------------------------- ++U16 InfinityGetMaskReg(BachRegBank_e nBank, U8 nAddr) ++{ ++ return InfinityReadReg(nBank, nAddr); ++} ++ ++void InfinitySetBank1BaseAddr(U32 addr) ++{ ++ m_pInfinityAudBank1RegAddr = addr; ++} ++ ++void InfinitySetBank2BaseAddr(U32 addr) ++{ ++ m_pInfinityAudBank2RegAddr = addr; ++} ++ ++void InfinitySetBank3BaseAddr(U32 addr) ++{ ++ m_pInfinityAudBank3RegAddr = addr; ++} ++ ++ ++ ++ ++void InfinitySetBankBaseAddr(U32 addr) ++{ ++ m_pInfinityBaseRegAddr = addr; ++ m_pInfinityAudBank1RegAddr = addr + (U32)(BACH_REG_BANK_1 << 1); ++ m_pInfinityAudBank2RegAddr = addr + (U32)(BACH_REG_BANK_2 << 1); ++ m_pInfinityAudBank3RegAddr = addr + (U32)(BACH_REG_BANK_3 << 1); ++} ++EXPORT_SYMBOL_GPL(InfinitySetBankBaseAddr); ++ ++void InfinityWriteReg2Byte(U32 nAddr, U16 nValue) ++{ ++ WRITE_WORD(m_pInfinityBaseRegAddr + ((nAddr) << 1), nValue); ++} ++ ++void InfinityWriteRegByte(U32 nAddr, U8 nValue) ++{ ++ WRITE_BYTE(m_pInfinityBaseRegAddr + ((nAddr) << 1) - ((nAddr) & 1), nValue); ++} ++ ++U16 InfinityReadReg2Byte(U32 nAddr) ++{ ++ return READ_WORD(m_pInfinityBaseRegAddr + ((nAddr) << 1)); ++} ++EXPORT_SYMBOL_GPL(InfinityReadReg2Byte); ++ ++U8 InfinityReadRegByte(U32 nAddr) ++{ ++ return READ_BYTE(m_pInfinityBaseRegAddr + ((nAddr) << 1) - ((nAddr) & 1)); ++} ++ ++void InfinityWriteReg(BachRegBank_e nBank, U8 nAddr, U16 regMsk, U16 nValue) ++{ ++ U16 nConfigValue; ++ ++ switch(nBank) ++ { ++ case BACH_REG_BANK1: ++ nConfigValue = READ_WORD(m_pInfinityAudBank1RegAddr + ((nAddr) << 1)); ++ nConfigValue &= ~regMsk; ++ nConfigValue |= (nValue & regMsk); ++ WRITE_WORD(m_pInfinityAudBank1RegAddr + ((nAddr) << 1), nConfigValue); ++ break; ++ case BACH_REG_BANK2: ++ nConfigValue = READ_WORD(m_pInfinityAudBank2RegAddr + ((nAddr) << 1)); ++ nConfigValue &= ~regMsk; ++ nConfigValue |= (nValue & regMsk); ++ WRITE_WORD(m_pInfinityAudBank2RegAddr + ((nAddr) << 1), nConfigValue); ++ break; ++ case BACH_REG_BANK3: ++ nConfigValue = READ_WORD(m_pInfinityAudBank3RegAddr + ((nAddr) << 1)); ++ nConfigValue &= ~regMsk; ++ nConfigValue |= (nValue & regMsk); ++ WRITE_WORD(m_pInfinityAudBank3RegAddr + ((nAddr) << 1), nConfigValue); ++ break; ++ default: ++ ERRMSG("WAVEDEV.DLL: InfinityWriteReg - ERROR bank default case!\n"); ++ break; ++ } ++} ++ ++ ++U16 InfinityReadReg(BachRegBank_e nBank, U8 nAddr) ++{ ++ switch(nBank) ++ { ++ case BACH_REG_BANK1: ++ return READ_WORD(m_pInfinityAudBank1RegAddr + ((nAddr) << 1)); ++ case BACH_REG_BANK2: ++ return READ_WORD(m_pInfinityAudBank2RegAddr + ((nAddr) << 1)); ++ case BACH_REG_BANK3: ++ return READ_WORD(m_pInfinityAudBank3RegAddr + ((nAddr) << 1)); ++ default: ++ ERRMSG("WAVEDEV.DLL: InfinityReadReg - ERROR bank default case!\n"); ++ return 0; ++ } ++} ++ ++//------------------------------------------------------------------------------ ++// ++// Function: BachC3::MapHardware ++// ++// Description ++// Maps port address, assigns SysIntr. ++// ++// Parameters ++// u32RegAddr: [in] Physical address of audio hardware register. ++// u32RegLength: [in] Length of the address space of audio hardware register. ++// ++// Return Value ++// Returns TRUE if device was mapped properly ++// Return FALSE if device could not be mapped ++//------------------------------------------------------------------------------ ++void InfinityDmaInitChannel( U32 nChannelIndex, ++ U32 nPhysDMAAddr, ++ U32 nBufferSize, ++ U32 nChannels, ++ U32 nSampleSize, ++ U32 nSampleRate, ++ U32 nOverrunTh, ++ U32 nUnderrunTh ++ ) ++{ ++ //U16 nConfigValue; ++ ++ // save off the info for power managment ++ m_infinitydmachannel[nChannelIndex].nPhysDMAAddr = nPhysDMAAddr; ++ m_infinitydmachannel[nChannelIndex].nBufferSize = nBufferSize; ++ m_infinitydmachannel[nChannelIndex].nChannels = nChannels; ++ m_infinitydmachannel[nChannelIndex].nSampleSize = nSampleSize; ++ m_infinitydmachannel[nChannelIndex].nSampleRate = nSampleRate; ++ ++ ++ // Set up the physical DMA buffer address ++ InfinityDmaSetPhyAddr((BachDmaChannel_e)nChannelIndex, nPhysDMAAddr, nBufferSize); ++ ++ ++ // Set up the underrun and overrun ++ //DmaSetThreshold((BachDmaChannel_e)nChannelIndex, nBufferSize+MIU_WORD_BYTE_SIZE, (nBufferSize/4)*3); ++ InfinityDmaSetThreshold((BachDmaChannel_e)nChannelIndex, nOverrunTh, nUnderrunTh); ++ ++ // Set up channel mode ++ InfinityDmaSetChMode((BachDmaChannel_e)nChannelIndex, (nChannels==1 ? TRUE:FALSE)); ++ ++ return ; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaInitChannel); ++ ++void InfinityDmaReset(void) ++{ ++ //rest DMA1 interal register ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_4, 0xFFFF, 0); //reset DMA 1 read size ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_12, 0xFFFF, 0); //reset DMA 1 write size ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_SW_RST_DMA, REG_SW_RST_DMA); //DMA 1 software reset ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_SW_RST_DMA, 0); ++ ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, (REG_PRIORITY_KEEP_HIGH | REG_RD_LEVEL_CNT_LIVE_MASK), ++ (REG_PRIORITY_KEEP_HIGH | REG_RD_LEVEL_CNT_LIVE_MASK)); ++ ++ //enable DMA interrupt ++ InfinityWriteReg(BACH_REG_BANK2, BACH_INT_EN, REG_DMA_INT_EN, REG_DMA_INT_EN); ++} ++EXPORT_SYMBOL_GPL(InfinityDmaReset); ++ ++void InfinityDmaReInit(BachDmaChannel_e eDmaChannel) ++{ ++ switch ( eDmaChannel ) ++ { ++ case BACH_DMA_READER1: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_TRIG, 0); // prevent from triggering levelcount at toggling init step ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_INIT, REG_RD_INIT); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_INIT, 0); ++ break; ++ ++ case BACH_DMA_WRITER1: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_TRIG, 0); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_INIT, REG_WR_INIT); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_INIT, 0); ++ break; ++ ++ default: ++ ERRMSG("InfinityDmaReInit - ERROR bank default case!\n"); ++ break; ++ } ++ ++} ++ ++void InfinityDmaEnable(BachDmaChannel_e eDmaChannel, BOOL bEnable) ++{ ++ switch ( eDmaChannel ) ++ { ++ case BACH_DMA_READER1: ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, ++ (REG_RD_EMPTY_INT_EN | REG_RD_UNDERRUN_INT_EN), ++ (bEnable ? (REG_RD_EMPTY_INT_EN | REG_RD_UNDERRUN_INT_EN) : 0)); ++ ++ if(bEnable) ++ { ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_ENABLE, REG_ENABLE); //reader prefetch enable, it should be enabled before reader enable ++ udelay(10); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_ENABLE, REG_RD_ENABLE); ++ } ++ else ++ { ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_ENABLE, 0); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_ENABLE, 0); //reader prefetch enable, it has to be disabled before dma init ++ } ++ ++ break; ++ ++ case BACH_DMA_WRITER1: ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, ++ (REG_WR_FULL_INT_EN | REG_WR_OVERRUN_INT_EN), ++ (bEnable ? (REG_WR_FULL_INT_EN | REG_WR_OVERRUN_INT_EN) : 0)); ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_ENABLE, (bEnable ? REG_WR_ENABLE : 0)); ++ ++ break; ++ ++ default: ++ ERRMSG("InfinityDmaEnable - ERROR bank default case!\n"); ++ break; ++ ++ } ++ ++} ++ ++void InfinityDmaStartChannel(BachDmaChannel_e eDmaChannel) ++{ ++ InfinityDmaClearInt(eDmaChannel); ++ InfinityDmaEnable(eDmaChannel, TRUE); ++ m_infinitydmachannel[eDmaChannel].nDMAChannelState = DMA_RUNNING; // save the state ++ return; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaStartChannel); ++ ++void InfinityDmaStopChannel(BachDmaChannel_e eDmaChannel) ++{ ++ InfinityDmaEnable(eDmaChannel, FALSE); ++ InfinityDmaReInit(eDmaChannel); ++ ++ //Sleep(100); ++ // save the state ++ m_infinitydmachannel[eDmaChannel].nDMAChannelState = DMA_STOPPED; ++ return; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaStopChannel); ++ ++/** ++ * \brief clear DMA2 interrupt ++ */ ++void InfinityDmaClearInt(BachDmaChannel_e eDmaChannel) ++{ ++ switch(eDmaChannel) ++ { ++ ++ case BACH_DMA_WRITER1: ++ //DMA writer full flag clear / DMA writer local buffer full flag clear ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_WR_FULL_FLAG_CLR, REG_WR_FULL_FLAG_CLR); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_WR_FULL_FLAG_CLR, 0); ++ break; ++ ++ case BACH_DMA_READER1: ++ //DMA reader empty flag clear / DMA reader local buffer empty flag clear ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_RD_EMPTY_FLAG_CLR, REG_RD_EMPTY_FLAG_CLR); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, REG_RD_EMPTY_FLAG_CLR, 0); ++ ++ break; ++ ++ default: ++ ERRMSG("InfinityDmaClearInt - ERROR bank default case!\n"); ++ break; ++ } ++ ++ return; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaClearInt); ++ ++U32 InfinityDmaGetLevelCnt(BachDmaChannel_e eDmaChannel) ++{ ++ U16 nConfigValue = 0; ++ U32 nByteSize = 0; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ { ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_LEVEL_CNT_MASK, REG_WR_LEVEL_CNT_MASK); ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_15); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_LEVEL_CNT_MASK, 0); ++ nConfigValue = ((nConfigValue>8)? (nConfigValue-8):0); //level count contains the local buffer data size ++ break; ++ } ++ ++ case BACH_DMA_READER1: ++ { ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_LEVEL_CNT_MASK, REG_RD_LEVEL_CNT_MASK); ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_7); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_LEVEL_CNT_MASK, 0); ++ break; ++ } ++ ++ default: ++ ERRMSG("InfinityDmaGetLevelCnt - ERROR bank default case!\n"); ++ return 0; ++ ++ } ++ ++ nByteSize = nConfigValue * MIU_WORD_BYTE_SIZE; ++ ++ return nByteSize; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaGetLevelCnt); ++ ++ ++void InfinityDmaSetThreshold(BachDmaChannel_e eDmaChannel, U32 nOverrunTh, U32 nUnderrunTh) ++{ ++ U16 nMiuOverrunTh, nMiuUnderrunTh; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ nMiuOverrunTh = (U16)((nOverrunTh / MIU_WORD_BYTE_SIZE) & REG_WR_OVERRUN_TH_MSK); ++ nMiuUnderrunTh = (U16)((nUnderrunTh / MIU_WORD_BYTE_SIZE) & REG_WR_UNDERRUN_TH_MSK); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_13, 0xFFFF, nMiuOverrunTh); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_14, 0xFFFF, nMiuUnderrunTh); ++ break; ++ ++ case BACH_DMA_READER1: ++ ++ nMiuOverrunTh = (U16)((nOverrunTh / MIU_WORD_BYTE_SIZE) & REG_RD_OVERRUN_TH_MSK); ++ nMiuUnderrunTh = (U16)((nUnderrunTh / MIU_WORD_BYTE_SIZE) & REG_RD_UNDERRUN_TH_MSK); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_5, 0xFFFF, nMiuOverrunTh); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_6, 0xFFFF, nMiuUnderrunTh); ++ break; ++ ++ default: ++ ERRMSG("InfinityDmaSetThreshold - ERROR bank default case!\n"); ++ break; ++ } ++ ++} ++EXPORT_SYMBOL_GPL(InfinityDmaSetThreshold); ++ ++/** ++ * \brief DMA set MIU address ++ */ ++void InfinityDmaSetPhyAddr(BachDmaChannel_e eDmaChannel, U32 nBufAddrOffset, U32 nBufSize) ++{ ++ U16 nMiuAddrLo, nMiuAddrHi, nMiuSize; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ nMiuAddrLo = (U16)((nBufAddrOffset / MIU_WORD_BYTE_SIZE) & REG_WR_BASE_ADDR_LO_MSK); ++ nMiuAddrHi = (U16)(((nBufAddrOffset / MIU_WORD_BYTE_SIZE) >> REG_WR_BASE_ADDR_HI_OFFSET) & REG_WR_BASE_ADDR_HI_MSK); ++ nMiuSize = (U16)((nBufSize / MIU_WORD_BYTE_SIZE) & REG_WR_BUFF_SIZE_MSK); ++ ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_BASE_ADDR_LO_MSK, nMiuAddrLo); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_10, REG_WR_BASE_ADDR_HI_MSK, nMiuAddrHi); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_11, 0xFFFF, nMiuSize); ++ ++ break; ++ ++ case BACH_DMA_READER1: ++ ++ nMiuAddrLo = (U16)((nBufAddrOffset / MIU_WORD_BYTE_SIZE) & REG_RD_BASE_ADDR_LO_MSK); ++ nMiuAddrHi = (U16)(((nBufAddrOffset / MIU_WORD_BYTE_SIZE) >> REG_RD_BASE_ADDR_HI_OFFSET) & REG_RD_BASE_ADDR_HI_MSK); ++ nMiuSize = (U16)((nBufSize / MIU_WORD_BYTE_SIZE) & REG_RD_BUFF_SIZE_MSK); ++ ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_BASE_ADDR_LO_MSK, nMiuAddrLo); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_2, REG_RD_BASE_ADDR_HI_MSK, nMiuAddrHi); ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_3, 0xFFFF, nMiuSize); ++ ++ break; ++ ++ default: ++ ERRMSG("InfinityDmaSetPhyAddr - ERROR bank default case!\n"); ++ break; ++ ++ } ++ ++} ++ ++BOOL InfinityDmaMaskInt(BachDmaChannel_e eDmaChan, BachDmaInterrupt_e eDmaInt, BOOL bMask) ++{ ++ switch(eDmaChan) ++ { ++ case BACH_DMA_READER1: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, ++ g_nInfinityDmaIntReg[BACH_DMA_READER1][eDmaInt], (bMask ? 0 : g_nInfinityDmaIntReg[BACH_DMA_READER1][eDmaInt])); ++ break; ++ ++ case BACH_DMA_WRITER1: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_0, ++ g_nInfinityDmaIntReg[BACH_DMA_WRITER1][eDmaInt], (bMask ? 0 : g_nInfinityDmaIntReg[BACH_DMA_WRITER1][eDmaInt])); ++ break; ++ ++ default: ++ return FALSE; ++ } ++ ++ return TRUE; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaMaskInt); ++ ++BOOL InfinityDmaIsFull(BachDmaChannel_e eDmaChannel) ++{ ++ U16 nConfigValue; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_WR_FULL_FLAG) ? TRUE : FALSE; ++ ++ default: ++ return FALSE; ++ } ++} ++EXPORT_SYMBOL_GPL(InfinityDmaIsFull); ++ ++BOOL InfinityDmaIsEmpty(BachDmaChannel_e eDmaChannel) ++{ ++ U16 nConfigValue; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_READER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_RD_EMPTY_FLAG) ? TRUE : FALSE; ++ ++ default: ++ return FALSE; ++ } ++} ++EXPORT_SYMBOL_GPL(InfinityDmaIsEmpty); ++ ++BOOL InfinityDmaIsLocalEmpty(BachDmaChannel_e eDmaChannel) ++{ ++ U16 nConfigValue; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_READER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_RD_LOCALBUF_EMPTY) ? TRUE : FALSE; ++ ++ default: ++ return FALSE; ++ } ++} ++ ++ ++BOOL InfinityDmaIsUnderrun(BachDmaChannel_e eDmaChannel) ++{ ++ U16 nConfigValue; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_WR_UNDERRUN_FLAG) ? TRUE : FALSE; ++ ++ case BACH_DMA_READER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_RD_UNDERRUN_FLAG) ? TRUE : FALSE; ++ ++ default: ++ ERRMSG("InfinityDmaIsUnderrun - ERROR default case!\n"); ++ return FALSE; ++ } ++ ++ return FALSE; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaIsUnderrun); ++ ++BOOL InfinityDmaIsOverrun(BachDmaChannel_e eDmaChannel) ++{ ++ U16 nConfigValue; ++ ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_WR_OVERRUN_FLAG) ? TRUE : FALSE; ++ ++ case BACH_DMA_READER1: ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_8); ++ return (nConfigValue & REG_RD_OVERRUN_FLAG) ? TRUE : FALSE; ++ ++ default: ++ return FALSE; ++ } ++ ++ return FALSE; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaIsOverrun); ++ ++U32 InfinityDmaTrigLevelCnt(BachDmaChannel_e eDmaChannel, U32 nDataSize) ++{ ++ U16 nConfigValue = 0; ++ ++ nConfigValue = (U16)((nDataSize / MIU_WORD_BYTE_SIZE) & REG_WR_SIZE_MSK); ++ nDataSize = nConfigValue * MIU_WORD_BYTE_SIZE; ++ ++ if (nConfigValue > 0) ++ { ++ switch(eDmaChannel) ++ { ++ case BACH_DMA_WRITER1: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_12, 0xFFFF, nConfigValue); ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9); ++ if(nConfigValue & REG_WR_TRIG) ++ { ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_TRIG, 0); ++ } ++ else ++ { ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_9, REG_WR_TRIG, REG_WR_TRIG); ++ } ++ ++ break; ++ ++ case BACH_DMA_READER1: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_4, 0xFFFF, nConfigValue); ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1); ++ if(nConfigValue & REG_RD_TRIG) ++ { ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_TRIG, 0); ++ } ++ else ++ { ++ InfinityWriteReg(BACH_REG_BANK1, BACH_DMA1_CTRL_1, REG_RD_TRIG, REG_RD_TRIG); ++ } ++ break; ++ ++ default: ++ ERRMSG("InfinityDmaTrigLevelCnt - ERROR bank default case!\n"); ++ return 0; ++ } ++ ++ return nDataSize; ++ } ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(InfinityDmaTrigLevelCnt); ++ ++U32 InfinityRateToU32(BachRate_e eRate) ++{ ++ switch(eRate) ++ { ++ case BACH_RATE_8K: ++ return 8000; ++ case BACH_RATE_11K: ++ return 11025; ++ case BACH_RATE_12K: ++ return 12000; ++ case BACH_RATE_16K: ++ return 16000; ++ case BACH_RATE_22K: ++ return 22050; ++ case BACH_RATE_24K: ++ return 24000; ++ case BACH_RATE_32K: ++ return 32000; ++ case BACH_RATE_44K: ++ return 44100; ++ case BACH_RATE_48K: ++ return 48000; ++ default: ++ return 0; ++ } ++} ++ ++BachRate_e InfinityRateFromU32(U32 nRate) ++{ ++ switch(nRate) ++ { ++ case 8000: ++ return BACH_RATE_8K; ++ case 11025: ++ return BACH_RATE_11K; ++ case 12000: ++ return BACH_RATE_12K; ++ case 16000: ++ return BACH_RATE_16K; ++ case 22050: ++ return BACH_RATE_22K; ++ case 24000: ++ return BACH_RATE_24K; ++ case 32000: ++ return BACH_RATE_32K; ++ case 44100: ++ return BACH_RATE_44K; ++ case 48000: ++ return BACH_RATE_48K; ++ default: ++ return BACH_RATE_NULL; ++ } ++} ++EXPORT_SYMBOL_GPL(InfinityRateFromU32); ++ ++BOOL InfinityDmaSetRate(BachDmaChannel_e eDmaChannel, BachRate_e eRate) ++{ ++ ++ //TODO: ++ switch(eDmaChannel) ++ { ++ //ADC rate should be set according to the DMA writer rate ++ case BACH_DMA_WRITER1: ++ switch(eRate) ++ { ++ case BACH_RATE_8K: ++ InfinityWriteReg(BACH_REG_BANK1, BACH_SR0_SEL, REG_WRITER_SEL_MSK, 0< BACH_DPGA_GAIN_MAX_DB) ++ s8Gain = BACH_DPGA_GAIN_MAX_DB; ++ else if(s8Gain < BACH_DPGA_GAIN_MIN_DB) ++ s8Gain = BACH_DPGA_GAIN_MIN_DB; ++ ++ if(s8Gain == BACH_DPGA_GAIN_MIN_DB) ++ *pu8GainIdx = BACH_DPGA_GAIN_MIN_IDX; ++ else ++ *pu8GainIdx = (U8)(-2 * s8Gain); //index = -2 * (gain) ,because step = -0.5dB ++} ++ ++S8 InfinityDpgaGetGain(BachDpga_e eDpga) ++{ ++ U16 nConfigValue; ++ U8 nGainIdx, nAddr; ++ S8 nGain; ++ ++ switch(eDpga) ++ { ++ case BACH_DPGA_MMC1: ++ nAddr = BACH_MMC1_DPGA_CFG2; ++ break; ++ case BACH_DPGA_ADC: ++ nAddr = BACH_ADC_DPGA_CFG2; ++ break; ++ case BACH_DPGA_AEC1: ++ nAddr = BACH_AEC1_DPGA_CFG2; ++ break; ++ case BACH_DPGA_DEC1: ++ nAddr = BACH_MMCDEC1_DPGA_CFG2; ++ break; ++ default: ++ ERRMSG("InfinityDpgaGetGain - ERROR default case!\n"); ++ return 0; ++ } ++ ++ nConfigValue = InfinityReadReg(BACH_REG_BANK1, nAddr); ++ nGainIdx = (U8)(nConfigValue & REG_GAIN_L_MSK); ++ if(nGainIdx == BACH_DPGA_GAIN_MIN_IDX) ++ nGain = BACH_DPGA_GAIN_MIN_DB; ++ else ++ nGain = -((S8)nGainIdx) / 2; ++ return nGain; ++} ++ ++void InfinityDpgaSetGain(BachDpga_e eDpga, S8 s8Gain) ++{ ++ U8 nAddr; ++ U8 nGainIdx,nLGain,nRGain; ++ ++ InfinityDpgaCalGain(s8Gain, &nGainIdx); ++ ++ switch(eDpga) ++ { ++ case BACH_DPGA_MMC1: ++ nAddr = BACH_MMC1_DPGA_CFG2; ++ nLGain = nGainIdx; ++ nRGain = nGainIdx; ++ break; ++ case BACH_DPGA_ADC: ++ nAddr = BACH_ADC_DPGA_CFG2; ++ nLGain = nGainIdx; ++ nRGain = 0; ++ break; ++ case BACH_DPGA_AEC1: ++ nAddr = BACH_AEC1_DPGA_CFG2; ++ nLGain = nGainIdx; ++ nRGain = 0; ++ break; ++ case BACH_DPGA_DEC1: ++ nAddr = BACH_MMCDEC1_DPGA_CFG2; ++ nLGain = nGainIdx; ++ nRGain = nGainIdx; ++ break; ++ default: ++ ERRMSG("InfinityDpgaSetGain - ERROR default case!\n"); ++ return; ++ } ++ ++ //set gain ++ InfinityWriteReg(BACH_REG_BANK1, nAddr, REG_GAIN_R_MSK | REG_GAIN_L_MSK, (nRGain< BACH_ATOP_NUM) ++ return FALSE; ++ else ++ { ++ if(!(m_bADCActive||m_bDACActive)) ++ InfinityAtopEnableRef(TRUE); ++ if(ePath<2) ++ { ++ if(ePath==BACH_ATOP_LINEIN) ++ { ++ if(m_bInfinityAtopStatus[BACH_ATOP_MIC]) ++ return FALSE; ++ else if(!m_bInfinityAtopStatus[BACH_ATOP_LINEIN]) ++ InfinityAtopLineIn(TRUE); ++ } ++ else ++ { ++ if(m_bInfinityAtopStatus[BACH_ATOP_LINEIN]) ++ return FALSE; ++ else if(!m_bInfinityAtopStatus[BACH_ATOP_MIC]) ++ InfinityAtopMic(TRUE); ++ } ++ } ++ else ++ { ++ if(!m_bDACActive) ++ InfinityAtopDac(TRUE); ++ } ++ return TRUE; ++ } ++} ++EXPORT_SYMBOL_GPL(InfinityOpenAtop); ++ ++BOOL InfinityCloseAtop(BachAtopPath_e ePath) ++{ ++ switch(ePath) ++ { ++ case BACH_ATOP_LINEIN: ++ if(m_bInfinityAtopStatus[BACH_ATOP_LINEIN]) ++ InfinityAtopLineIn(FALSE); ++ break; ++ case BACH_ATOP_MIC: ++ if(m_bInfinityAtopStatus[BACH_ATOP_MIC]) ++ InfinityAtopMic(FALSE); ++ break; ++ case BACH_ATOP_LINEOUT: ++ if(m_bInfinityAtopStatus[BACH_ATOP_LINEOUT]) ++ InfinityAtopDac(FALSE); ++ break; ++ default: ++ return FALSE; ++ } ++ ++ if(!(m_bADCActive || m_bDACActive)) ++ InfinityAtopEnableRef(FALSE); ++ return TRUE; ++} ++EXPORT_SYMBOL_GPL(InfinityCloseAtop); ++ ++/*BOOL InfinityAtopMicGain(U16 nLevel) ++{ ++ if(nLevel>7) ++ { ++ ERRMSG("BachAtopMicGain - ERROR!! not Support.\n"); ++ return FALSE; ++ } ++ ++ if(nLevel==2) ++ m_nMicInGain = 0x0; ++ else if(nLevel<2) ++ m_nMicInGain = 0x1 + nLevel; ++ else if(nLevel) ++ m_nMicInGain = nLevel; ++ ++ if(m_bInfinityAtopStatus[BACH_ATOP_MIC]) ++ { ++ InfinityWriteReg(BACH_REG_BANK3, BACH_ANALOG_CTRL06, REG_SEL_GAIN_INMUX0_MSK | REG_SEL_GAIN_INMUX1_MSK, m_nMicInGain<3) ++ { ++ ERRMSG("BachAtopMicPreGain - ERROR!! not Support.\n"); ++ return FALSE; ++ } ++ ++ m_nMicGain = nLevel; ++ ++ if(m_bInfinityAtopStatus[BACH_ATOP_MIC]) ++ { ++ InfinityWriteReg(BACH_REG_BANK3, BACH_ANALOG_CTRL08, REG_SEL_MICGAIN_STG1_L_MSK | REG_SEL_MICGAIN_STG1_R_MSK, m_nMicGain<7) ++ { ++ ERRMSG("BachAtopLineInGain - ERROR!! Level too large .\n"); ++ return FALSE; ++ } ++ ++ if(nLevel==2) ++ m_nLineInGain = 0x0; ++ else if(nLevel<2) ++ m_nLineInGain = 0x1 + nLevel; ++ else if(nLevel) ++ m_nLineInGain = nLevel; ++ ++ if(m_bInfinityAtopStatus[BACH_ATOP_LINEIN]) ++ InfinityWriteReg(BACH_REG_BANK3, BACH_ANALOG_CTRL06, REG_SEL_GAIN_INMUX0_MSK | REG_SEL_GAIN_INMUX1_MSK, m_nLineInGain<7) ++ { ++ ERRMSG("InfinityAtopAdcGain - ERROR!! Level too large .\n"); ++ return FALSE; ++ } ++ ++ if(nLevel==2) ++ nGain = 0x0; ++ else if(nLevel<2) ++ nGain = 0x1 + nLevel; ++ else if(nLevel) ++ nGain = nLevel; ++ ++ if(eAtop == BACH_ATOP_LINEIN) ++ m_nLineInGain = nGain; ++ else if(eAtop == BACH_ATOP_MIC) ++ m_nMicInGain = nGain; ++ else ++ { ++ ERRMSG("InfinityAtopAdcGain - ERROR!! ADC source error.\n"); ++ return FALSE; ++ } ++ ++ if(m_bInfinityAtopStatus[eAtop]) ++ InfinityWriteReg(BACH_REG_BANK3, BACH_ANALOG_CTRL06, REG_SEL_GAIN_INMUX0_MSK | REG_SEL_GAIN_INMUX1_MSK, nGain< ++#include ++typedef unsigned int U32; ++typedef int S32; ++typedef bool BOOL; ++ ++#define TRUE 1 ++#define FALSE 0 ++ ++//#define ERRMSG printk ++#define ERRMSG(fmt, arg...) printk(KERN_ERR "